Patent ID: 7155626
Filing Date: 2006-12-26
Classification: G06F

Abstract:
1. A data processor, comprising: a first plurality of circuit resources which operate synchronously with a second clock signal; a clock generating circuit for generating a first clock signal; a clock thinning-out circuit for thinning out the first clock signal to provide the second clock signal; a second plurality of circuit resources which operate synchronously with a third clock signal provided by the clock thinning out circuit; and the clock thinning-out circuit includes a mode setting circuit for selectively setting a first mode in which the first clock signal is thinned out to provide the second clock signal and the first clock signal is not thinned out to provide the third clock signal, a second mode in which the first clock signal is thinned out to provide the third clock signal and the first clock signal is not thinned out to provide the second clock signal, and a third mode in which the first clock signal is thinned out to provide the second clock signal and the third clock signal.