Patent ID: 8149644
Filing Date: 2012-04-03
Classification: G11C

Abstract:
1. A memory system comprising: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage, where the semiconductor memory operates in synchronization with a clock signal; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage, where the first control unit operates in synchronization with the clock signal; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory provided by the first control unit; wherein the memory input/output circuit comprises: an input buffer; a level shifter, disposed between the input buffer and the internal circuit, that converts a signal level of the second power supply voltage outputted from the input buffer into a signal level of the first power supply voltage; and a switch circuit that selectively couples the output of the level shifter or the output of the input buffer to the internal circuit based on a relationship between the second power supply voltage and the first power supply voltage.