Patent ID: 7411822
Filing Date: 2008-08-12
Classification: G11C,H01L

Abstract:
1. A memory, comprising: a multiplicity of nonvolatile memory cells, each nonvolatile memory cell being formed by a memory transistor configured so that electrical charge carriers are stored in nonvolatile fashion; the memory transistors are arranged in a matrix having a plurality of rows and columns; a first source/drain terminal of each memory transistor of a first column coupled to an electrically conductive conductor track in a first metallization plane; a first source/drain terminal of each memory transistor of a second column adjacent to the first column coupled to an electrically conductive conductor track in a second metallization plane; a first source/drain terminal of each memory transistor of a third column adjacent to the second column coupled to an electrically conductive conductor track in the first metallization plane; and a first source/drain terminal of each memory transistor of a fourth column adjacent to the third column coupled to an electrically conductive conductor track in the second metallization plane, wherein the second metallization plane is different than the first metallization plane, wherein a second source/drain terminal of each memory transistor is connected to a respective electrically conductive conductor track in a third metallization plane, the third metallization plane being different than the first metallization plane and different than the second metallization plane.