Patent ID: 6480024
Filing Date: 2002-11-12
Classification: H03K

Abstract:
A circuit configuration for programming a delay in a signal path, comprising:an input terminal for receiving an input signal; an output terminal for providing an output signal; a first signal path section with a first delay, said first signal path section having an input end connected to said input terminal and having an output end; a second signal path section with a second delay that is different from the first delay of said first signal path section, said second signal path section having an input end connected to said input terminal and having an output end; a multiplexer having an input connected to said output end of said first signal path section and said output end of said second signal path section, said multiplexer having an output connected to said output terminal; and a drive circuit including: supply terminals for receiving a supply voltage, a first path connected between said terminals for receiving the supply voltage, said first path including two transistors connected together to define a first node, said first path including a first programmable path section and a second programmable path section, one of said first programmable path section and said second programmable path section programmed to be switched on and another one of said first programmable path section and said second programmable path section programmed to be switched off, and a second path connected between said terminals for receiving the supply voltage, said second path including two transistors connected together to define a second node, said second path including a first programmable path section and a second programmable path section, one of said first programmable path section of said second path and said second programmable path section of said second path programmed to be switched on and another one of said first programmable path section of said second path and said second programmable path section of said second path programmed to be switched off, said two transistors of said first path being controllable by complimentary control signals, and said two transistors of said second path being controllable by the complimentary control signals, and said multiplexer having a control input connected to said first node and said second node.