Patent ID: 7200056
Filing Date: 2007-04-03
Classification: G11C

Abstract:
1. A method of replacing memory cells in a memory, the method comprising: generating a first; plurality of values; selecting a second plurality of values from the first plurality of values, the second plurality of values representing potential solutions for memory row/column replacement; determining locations of failed memory cells within a memory array; using the second plurality of values to store in a first storage circuit, row/column indications of the location of the determined failed memory cells, wherein the memory array is implemented in an integrated circuit, the integratcd circuit includes at least one redundant row of a first number (RR) and at least one redundant column of a second number (RC), wherein the selecting of the second plurality of values from the first plurality of values further includes determined whether each value of the first plurality of values includes one of a number of logical 1's or a number of logical 0's equal to one of RR or RC.