Patent ID: 6720594
Filing Date: 2004-04-13
Classification: H01L

Abstract:
An imager system comprisinga scanning control circuit for generating gate voltage signals on a plurality of gate lines; a continuous sensor layer; a bias voltage source; and a plurality of pixels arranged in an array, each pixel including: a sensor including an associated portion of the continuous sensor layer and having a first terminal connected to the bias voltage source, the sensor also having a second terminal; a storage capacitor having a first terminal coupled to the second terminal of the sensor, and a second terminal connected to a system voltage source; and an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit; wherein the imager system further comprises means connected to at least one of the sensor and the access transistor of each of said plurality of pixels for controlling a voltage across the sensor of each of the plurality of pixels such that the sensor of each of the plurality of pixels is prevented from reaching saturation.