Patent ID: 7544543
Filing Date: 2009-06-09
Classification: G11C,H01L

Abstract:
1. A method for manufacturing a semiconductor device with a capacitor and a fuse, comprising: forming an insulating layer over a semiconductor substrate; forming a storage node hole in the insulating layer to define a capacitor region and a fuse region; forming a barrier metal layer in the storage node hole; forming a dielectric layer on the barrier metal and the insulating layer; forming a lower metal layer for a plate electrode on the dielectric layer so as to fill the storage node hole; removing a portion of the lower metal layer disposed on an upper surface of the dielectric layer, wherein a remaining portion of the lower metal layer fills the storage node hole; forming an upper metal layer on the remaining portion of the lower metal layer and the dielectric layer; and patterning the upper metal layer to form a capacitor region having the dielectric layer, the remaining portion of the lower metal layer, and the upper metal layer sequentially stacked therein, and a fuse layer having a sequentially stacked structure of the dielectric layer and the upper metal layer sequentially stacked therein.