Patent ID: 8553445
Filing Date: 2013-10-08
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of resistive memory cells that are connected to a plurality of word lines and a plurality of bit lines and each of which comprises a first variable resistance material film; and a resistor switch having first, second and third terminals, wherein the resistor switch comprises a second variable resistance material film and is configured to control a current path between the second and third terminals in response to a switching control signal received by the first terminal, wherein each of the bit lines comprises a first line portion and a second line portion, wherein the first and second line portions are electrically separated from each other by an intermediate region disposed between the first and second line portions, and wherein the first line portion is connected to the resistive memory cell and the second terminal, the second line portion is connected to the third terminal, and the resistor switch is disposed at the intermediate region and is configured to control a current path between the first and second line portions.