Patent ID: 6501122
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A Flash EEPROM device comprising:a polysilicon floating gate on the surface of a semiconductor substrate having a first oxide layer thereunder wherein said polysilicon floating gate comprises a first layer and a second layer wherein said second layer is thinner than said first layer wherein the top surface of said first layer is smooth thereby making the top surface of said floating gate smooth; a second oxide layer overlying said semiconductor substrate adjacent to said floating gate and having the same thickness as said first layer of said floating gate and said first oxide layer together; source and drain regions within said semiconductor substrate associated with said floating gate; an interpoly dielectric layer overlying said polysilicon floating gate; a control gate overlying said interpoly dielectric layer; an insulating layer overlying said semiconductor substrate and said control gate; and a patterned metal layer overlying said insulating layer and extending through contact openings in said insulating layer to underlying said control gate and to underlying said source and drain regions to complete said Flash EEPROM device.