Patent ID: 9164937
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A system, comprising: a controller; a plurality of memory modules coupled to the controller by a bi-directional data bus, and each memory module of the plurality of memory modules coupled to a respective other memory module of the plurality of memory modules by the bi-directional data bus, wherein each memory module of the plurality of memory modules is configured to process memory commands issued from the controller, wherein a first memory module of the plurality of memory modules includes bypass circuitry configured to capture write data associated with a write command passing to a third memory module of the plurality of memory modules, and wherein the first memory module is further configured to allow read data associated with a read command to return from a second memory module of the plurality of memory modules before allowing the captured write data to continue on to the third memory module, and wherein the bypass circuit is further configured to put an output buffer in a high impedance state responsive to storing write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between first and second data bus interfaces of the memory module of the plurality of memory modules.