Patent ID: 6601122
Filing Date: 2003-07-29
Classification: G06F

Abstract:
A method of handling an interrupt request in a computer system, comprising the steps of:establishing a default address associated with a default interrupt service routine for servicing an interrupt request, said default address referencing a location in a memory device of said computer system external to a processor of said computer system handling said interrupt request; programmably setting an override address associated with an alternate interrupt service routine for servicing said interrupt request, said override address referencing a location in an on-chip memory area within said processor handling said interrupt request; programmably setting a selection value which controls interrupt address selection logic within said processor handling said interrupt request; receiving said interrupt request; selecting only one of said default address and said override address with said interrupt address selection logic based on said selection value; and servicing the interrupt request using the interrupt service routine associated with the address selected by said selecting step; and further comprising the steps of: turning on a validation bit in response to said setting a selection value step; providing the default address and the override address as separate inputs to a multiplexing device; and selecting the override address using the multiplexing device based on the validation bit.