Patent ID: 6467006
Filing Date: 2002-10-15
Classification: H04L

Abstract:
A method of allocating master priority to a unique one of a plurality of interconnected processors, said method comprising:(a) providing one data storage register for each one of said processors; (b) interconnecting said registers and said processors with a logical message passing network having an arbitrary topology to enable any one of said processors to store data in all of said registers, and to enable each one of said processors to read data stored in said one register provided for said each one of said processors; (c) allocating a unique multiple bit identifier to each one of said processors; (d) synchronizing said processors with one another by broadcasting a logical data write message across said network to said processors; and, (e) arbitratively selecting and allocating said master priority to that one of said processors for which said allocated identifier has a value lower than the value of any other one of said identifiers allocated to any other one of said processors.