Patent ID: 6369625
Filing Date: 2002-04-09
Classification: H03L

Abstract:
A phase locked loop circuit (â€œPLLâ€ ) comprising:phase difference detecting means for detecting a phase difference of a PLL output signal in relation to an input signal; oscillation means for outputting the PLL output signal having a repetition frequency corresponding to a voltage level of a phase difference signal representative of the phase difference detected by said phase difference detecting means; and control means active when phase advanced condition or phase retarded condition of the PLL output signal relative to the input signal is continued, for controlling a voltage level of said frequency difference signal depending upon a number of times the phase advanced condition or phase retarded condition of the output signal relative to the input signal is continued, wherein said control means includes a pulse width modulator for generating a pulse width corresponding number of times the phase advanced condition or phase retarded condition of the output signal relative to the input signal is continued, and an integration circuit for integrating a pulse width modulated pulses, an integrated output level of said integration circuit is added to said phase difference signal.