Patent ID: 8674424
Filing Date: 2014-03-18
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a gate over a substrate; a gate dielectric between the gate and the substrate, wherein two gaps are present at both sides of the gate dielectric and between the gate and the substrate; two charge storage layers, each including a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of a sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein an edge of the first extension portion protrudes from a sidewall of the second extension portion, and a ratio of a length of the body portion to a length of the first extension portion ranges from 2:1 to 5:1; two doped regions in the substrate at both sides of the gate, wherein the first extension portion and the second extension portion of each charge storage layer are located over one of the doped regions; and a word line connecting the gate of the memory device to a gate of another memory device and covering at least one of the two doped regions.