Patent ID: 6565374
Filing Date: 2003-05-20
Classification: H01R,H05K

Abstract:
A high density vertical surface mount package having a substrate and at least one packaged semiconductor die comprising:a substrate having a plurality of circuits located on at least one surface thereof and having at least two apertures therethrough; two J-shaped locking pins for attaching and removal of said at least one packaged semiconductor die to said substrate, each J-shaped locking pin of said two J-shaped locking pins including a stem portion and a hooking portion, said hooking portion having a curved portion formed on a first end of said stem portion and having a thickness, each J-shaped locking pin of said two J-shaped locking pins attached to said substrate using an aperture therein for engaging said substrate, said curved portion of said hooking portion of said each of said two J-shaped locking pins facing each other and aligned having said curved portion of said hooking portion of the other J-shaped locking pin of said two J-shaped locking pins facing said other J-shaped locking pin of said two J-shaped locking pins; and at least one packaged semiconductor die having a first edge for vertically supporting said at least one packaged semiconductor die on said substrate, having at least one J-shaped locking edge located on each side adjacent said first edge of said at least one packaged semiconductor die for receiving said curved portion of said hooking portion of said each J-shaped locking pin of said two J-shaped locking pins attached to said substrate, said at least one packaged semiconductor die having a thickness no wider than said thickness of said hooking portion of said each J-shaped locking pin of said two J-shaped locking pins for connecting said at least one packaged semiconductor die to said substrate while allowing removal therefrom, and having a plurality of in-line package leads extending along a length of said first edge of said at least one packaged semiconductor die, each lead of said plurality of leads extending downwardly from said at least one packaged semiconductor die, a portion of said each of said plurality of leads extending below said at least one packaged semiconductor die and resiliently biasing a portion of said each of said plurality of leads against at least one circuit of said plurality of circuits located on said at least one surface of said substrate.