Patent ID: 6535966
Filing Date: 2003-03-18
Classification: G06F

Abstract:
A memory controller for a memory subsystem of a computer system, the memory controller for processing references to the memory subsystem and for directing those references to any memory devices of the memory subsystem, the memory controller for connection to a predetermined maximum number of memory devices of the memory subsystem and where each memory device is capable of maintaining a maximum number of simultaneously open pages, the memory controller comprising:a first interface to a processor bus; an address mapper coupled to the first interface and to a page tracking buffer; a state machine for controlling the memory controller; and an interface to memory devices, coupled to the address mapper; wherein the page tracking buffer further comprises a row address content addressable memory for determining when a reference is in a n open page, and a bank content addressable memory for determining when a reference is to the same bank as an open page; wherein upon a reference to a page in the same bank as an open page the memory controller closes that open page prior to opening the page associated with the reference; wherein the page tracking buffer has a plurality of lines in its row address content addressable memory and in its bank content addressable memory, each line corresponding to at most one open page, the number of lines is less than the product of the maximum number of memory devices times the maximum number of simultaneously open pages of each device; and wherein the page tracking buffer provides for tracking any open page of any of the memory devices while tracking a maximum number of open pages equal to the number of lines of its row address content addressable memory.