Patent ID: 7733079
Filing Date: 2010-06-08
Classification: G01R,G06F

Abstract:
1. A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, comprising: in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer, wherein upon testing, the selector selects the second input, an output of the one buffer is input to the first input of an adjacent selector located downstream in the chain-connection, the first input is selected in the adjacent selector, and the output of the one buffer is input to an adjacent buffer, the output of the one buffer is transferred down to a buffer at an ending point of the chain-connection sequentially through a selector and a buffer located downstream in the chain-connection, and a circuit for observing an output of the buffer at the ending point of the chain-connection is provided.