Patent ID: 6820107
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A square root extraction circuit for processing binary input data (0.a(1)) a(2) a(3). . . a(n)) using a square root extraction algorithm to output binary square root data (0.q(1) q(2) q(3). . . q(m)), said square root extraction algorithm including an algorithm for determining said square root data on the basis of said input data by only additions of square root partial data q(l) to q(m) in q(l) to q(m) order, said square root extraction circuit comprising:first to mth digit calculating portions each including a plurality of adders connected in series to that carries are propagated therethrough, wherein respective ones of said adders which are connected in the last position in said first to mth digit calculating portions provide carry outputs serving as said square root partial data q(l) to q(m), respectively, in accordance with said square root extraction algorithm, wherein said square root extraction circuit outputs said output binary square root data (0.q(1) q(2) q(3). . . q(m)) without using any controllable add/subtract cells.