Patent ID: 7646665
Filing Date: 2010-01-12
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cell blocks, each of which includes a plurality of memory, cells that are respectively coupled to a plurality of word lines and a plurality of bit lines; a word line control unit configured to activate word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, wherein the word line control unit comprises: a first row decoder configured to receive a first row address signal and to supply block selection signals configured to select the respective memory cell blocks; a second row decoder configured to receive a second row address signal and the respective block selection signals and to generate word line enable signals configured to activate the main word lines: a third row decoder configured to receive a third row address signal and the block selection signals and to supply word line driving signals; and a sub-word line driver configured to receive the word line enable signals and the word line driving signals and to activate the word lines; and a write circuit configured to write data in the memory cell blocks that correspond to the row address signals and to not write data in the memory cell blocks that do not correspond to the row address signals, during the test operation.