Patent ID: 6489242
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material during a subsequent CMP planarization step which comprises:a) forming a layer of low k dielectric material over raised portions of an underlying integrated circuit structure; b) forming a capping layer of dielectric material over said layer of low k dielectric material; c) depositing a planarization layer over said capping layer; d) then forming a removable mask over said planarization layer deposited over said capping layer, said mask having openings formed therein to expose a portion of the upper surface of said deposited planarization layer over said capping layer over at least some of said raised portions of said integrated circuit structure; e) etching exposed portions of at least said planarization layer through such openings in said mask to reduce the overall volume of said planarization layer over said capping layer and over said one of said dielectric layers overlying said raised portions of said integrated circuit structure; and f) removing said mask; whereby removal, before a CMP planarization step, of a portion of the overall volume of at least said planarization layer over said capping layer and over said one of said dielectric layers over said raised portions of said integrated circuit structure inhibits cracking of said layer of low k dielectric material layer.