Patent ID: 7941645
Filing Date: 2011-05-10
Classification: G06F,G06T

Abstract:
1. A processor configured to process an isochronous data stream, the processor comprising: a state register including an assembly buffer, an arm buffer, and an active buffer, each buffer being configured to store a respective value of a control parameter; a functional unit coupled to the state register and configured to perform a transformation operation on the isochronous data stream in response to an active value of the control parameter, the active value being obtained from the active buffer; a control module coupled to the state register and configured to receive a stream of control instructions and to update an arm value of the control parameter in the arm buffer in response to the control instructions, wherein the control instructions include a set instruction instructing the control module to store an assembly value for the control parameter in the assembly buffer and an update instruction instructing the control module to transfer the assembly value from the assembly buffer to the arm buffer, and wherein each update instruction is associated with a presentation interval parameter specifying a number of load events to be received before another update instruction may be executed; and an activation unit coupled to receive a load signal propagating synchronously with the isochronous data stream, wherein the load signal defines a load event that begins with a transition of the load signal to an asserted state and ends with a transition of the load signal to a deasserted state, the activation unit being configured to detect the beginning of the load event and further configured to update the active value of the control parameter by transferring the arm value from the arm buffer to the active buffer in response to the load event, wherein the activation unit is further configured to inhibit the control module from updating the arm buffer by executing the update instruction while the active buffer is being updated.