Patent ID: 6061291
Filing Date: 2000-05-09
Classification: G11C

Abstract:
A memory circuit comprising:an array of fuses that can be selectively blown to indicate a fuse address of a defective column of a memory array to be substituted by a redundant column,a decoder for receiving a mask, that selectively masks out certain columns of a group of columns from being written during a block write operations, and said fuse address from said array of fuses, said decoder for generating a first signal for disabling said redundant column during said block write operation when said mask masks out said defective column,a column multiplexer receiving column address, a mask single and a second signal for enabling single column specified by said column address, said column multiplexer also for simultaneously enabling each of one or more columns specified by said mask signal and for disabling each column masked out by said mask signal, andlogic circuitry receiving said fuse address, said column address, and said first signal, said logic circuitry for generating said second signal for disabling said column multiplexer when said fuse address matches said column address, said second signal also for enabling said redundant column, said lock circuitry also for disabling said redundant column in response to said first signal.