Patent ID: 8862835
Filing Date: 2014-10-14
Classification: G06F

Abstract:
1. A dual port register file comprising: a clock signal; a memory array comprising: synchronous write address decode logic having inputs and outputs, wherein the synchronous write address decode logic outputs select which row from the group of rows of memory array registers data is written; a write port, the write port comprising: a read port, the read port comprising an asynchronous read address; asynchronous read address decode logic having inputs and outputs wherein the outputs from the asynchronous read address decode logic select which row of memory array registers is read from the memory array, wherein an asynchronous read address is electrically connected to the inputs of the asynchronous read address decode logic; wherein when the write address stored in the pipelined synchronous write address registers is identical to the asynchronous read address, a result of a bit-wise ANDing of the output from the pipelined synchronous data registers and the output from the pipelined synchronous bit-write registers is output from the dual port register file.