Patent ID: 6392911
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A memory circuit comprising:plurality of memory cell arrays; a plurality of rows of bit-line sense amplifiers, each said row of bit-line sense amplifiers is disposed between and coupled to a pair of adjacent memory cell arrays; a plurality of bit-line select controllers, each said bit-line select controller having a first bit-line select control line extending therefrom and coupling to one of said rows of bit-line sense amplifiers for controlling the operation thereof; wherein said first bit-line select control line is used to control the coupling between said one of said rows of bit-line sense amplifiers and one member of said pair of adjacent memory cell arrays; and wherein, once switched on, said first bit-line select control line is switched off only when the other member of said pair of adjacent memory cell arrays is to be activated.