Patent ID: 8143672
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate having a well formed therein; a diode region located within the well formed in the substrate, the diode region having a plurality of protection diodes; a pad region overlapped with an upper part of the diode region, the pad region having a pad installed corresponding to an external connection terminal; an upper metal layer positioned under a lower part of the pad and a lower metal layer positioned under a lower part of the upper metal layer, wherein the diode region includes a first conductive active region and a second conductive active region and wherein the lower metal layer includes: a first gate pattern having an open region, a unit gate frame and a gate frame shape extended corresponding to the a first conductive active region of the diode region; and a second pattern of a rectangular shape, wherein the first pattern having the gate frame shape and the second pattern of a rectangular shape together form a combined structure having a web shape, and wherein the second pattern is isolated from the unit gate frame of the first pattern within the open region of the first pattern, corresponding to the second conductive active region of the diode region and wherein the unit gate frame of the first pattern is a frame of a square; a contact plug unit positioned on the diode region, wherein the contact plug unit connects at least one of a plurality of active regions constituting the diode region to the pad, and wherein the contact plug unit includes a first via contact part and a metal contact part, wherein the first via contact part connects the upper metal layer to the lower metal layer, wherein the metal contact part connects the at least one of the plurality of active regions to the lower metal layer, wherein the first via contact part and the metal contact part are vertically overlapped with each other and wherein the first via contact part and the metal contact part both vertically overlap with the diode region located within the well formed in the substrate; and a second via contact part electrically connecting the pad region and the upper metal layer, the second via contact part being connected to the pad and positioned under the lower part of the pad, and the second via contact part being positioned between the pad region and the upper metal layer and overlapped with the diode region located within the well formed in the substrate.