Patent ID: 8698310
Filing Date: 2014-04-15
Classification: B81B,H01H,H01P

Abstract:
1. A manufacturing method for a signal line comprising the steps of: forming a second insulating layer at an upper surface of a second semiconductor substrate in an SOI substrate in which a first semiconductor substrate and the second semiconductor substrate are welded while holding a first insulating layer therebetween; patterning the second insulating layer in a band manner to form an upper insulating layer for a signal line; manufacturing a strip conductor for a signal line along the upper insulating layer at an upper surface of the upper insulating layer; etching and removing the second semiconductor substrate in a region exposed to the outside from the upper insulating layer to form a semiconductor layer for a signal line with the second semiconductor substrate; and etching and removing the first insulating layer in a region exposed to the outside from the semiconductor layer to form a lower insulating layer for a signal line with the first insulating layer at an upper surface of a base for the signal line including the first semiconductor substrate.