Patent ID: 9190158
Filing Date: 2015-11-17
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device, outputting a data value determined according to a majority rule by reading-out data from each of a plurality of memory cells for an odd number of times not less than three times, wherein the plurality of memory cells is connected to corresponding word lines and connected to and between a plurality of bit lines and a plurality of source lines, the non-volatile semiconductor memory device comprising: an odd number of latch circuits, which are not less than three latch circuits, each of which comprising a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence; and a control circuit, connecting the capacitor of each of the odd number of latch circuits in parallel after the capacitor of each of the odd number of latch circuits selectively holding the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and determining the data value by the majority rule based on a composite voltage of the capacitor of each of the odd number of latch circuits connected in parallel.