Patent ID: 7339813
Filing Date: 2008-03-04
Classification: G11C

Abstract:
1. A memory structure comprising: a first memory resistor connected between a first voltage source and a first active transistor at a first active transistor source; a first load transistor connected between a drain voltage and the first active transistor at a first active transistor drain; and a first output connected at the first active transistor drain; a second memory resistor connected between a second voltage source and a second active transistor at a second active transistor source; a second load transistor connected between the drain voltage and the second active transistor at a second active transistor drain; and a second output connected at the second active transistor drain; and a word line connected to a gate of the first active transistor and to a gate of the second active transistor wherein, with one of the first memory resistor and second memory resistor set to a high resistance and the other of the first memory resistor and second memory resistor set to a low resistance, the output connected to one of the memory resistors is high and the output connected to the other of the memory resistors is low.