Patent ID: 6093597
Filing Date: 2000-07-25
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor memory device, comprising the steps of:forming on a semiconductor substrate an n-channel driver MOS transistor having a first gate electrode, a first drain layer and a first source layer and an n-channel transfer MOS transistor having a second gate electrode, first and second diffusion layers;forming a first insulating film on said driver and transfer MOS transistors;forming, on said first insulating film, a p-channel load thin film transistor having a third gate electrode, a second source layer functioning as a power supply line pattern, a second drain layer and a gate insulator, a fourth gate electrode of another load thin film transistor extending to the second drain layer;forming a second insulating film contacting said third gate electrode and including said gate insulator on said load thin film transistor and said first insulating film;forming a contact for connecting said second drain layer of said load thin film transistor and said fourth gate electrode of said another load thin film transistor to said first gate electrode of said driver transistor and said first diffusion layer of said transfer transistor;forming a third insulating film on said second insulating film; andforming a bit line on said third insulating film and a bit contact for connecting said bit line to said second diffusion layer.