Patent ID: 6724033
Filing Date: 2004-04-20
Classification: H01L,Y10S

Abstract:
A memory cell comprising one of a plurality of laterally adjacent memory cells forming a memory array, the memory cell comprising a fork-like structure including a plurality of vertically upstanding storage poly node portions mutually separated by a plurality of recesses and a plate electrode layer extending substantially conformally over the plurality of storage poly node portions with a capacitor dielectric disposed therebetween, the plurality of storage poly node portions, the capacitor dielectric and the plate electrode layer together forming the fork-like structure so that an upper surface of the plate electrode layer substantially conformally mimics a fork-like upper surface of the plurality of vertically upstanding storage poly node portions, the plurality of storage poly node portions of the memory cell being laterally spaced from storage poly node portions of any adjacent memory cell of the plurality of memory cells forming the memory array by a peripheral boundary, wherein each recess of the plurality of recesses is of lesser lateral extent between the storage poly node portions of the memory cell than a smallest lateral distance from any storage poly node portion of the memory cell across the peripheral boundary to any storage poly node portion of any laterally adjacent memory cell of the plurality of memory cells forming the memory array, the memory cell produced by the method comprising:providing an intermediate structure comprising a substrate having at least one thick field oxide area, at least one implanted drain region and at least one implanted source region; the intermediate structure further including at least one transistor gate member spanning between the at least one implanted drain region and the at least one implanted source region on an upper surface of the substrate; the intermediate structure further including a bitline within at least one layer of insulative material, wherein the bitline is in electrical communication with the at least one implanted source region, and a storage poly layer on an upper surface of the at least one insulative material layer, wherein a portion of the storage poly layer extends through the at least one insulative material layer to contact the at least one implanted drain region; applying an etch mask on the storage poly layer, wherein the etch mask includes a boundary opening for defining the peripheral boundary about the plurality of storage poly node portions and includes a plurality of apertures positioned over the storage poly layer for forming the plurality of recesses in the storage poly layer within the peripheral boundary and for separating an upper portion of the storage poly layer into the plurality of vertically upstanding storage poly node portions; simultaneously etching the storage poly layer to form the peripheral boundary and to form the plurality of recesses; removing the etch mask; applying the capacitor dielectric substantially conformally over the plurality of vertically upstanding storage poly node portions; and applying the plate electrode layer substantially conformally over the capacitor dielectric so that the upper surface of the plate electrode layer substantially conformally mimics the fork-like upper surface of the plurality of vertically upstanding storage poly node portions.