Patent ID: 6018481
Filing Date: 2000-01-25
Classification: G11C

Abstract:
A dynamic semiconductor memory device, comprising:a bit line pair including a bit line and a complementary bit line;a word line arranged to cross said bit line substantially at right angles;data transfer gates each connected to said bit line and complementary bit line, each of said data transfer gates having a first control terminal for controlling a conduction state of said transfer gate;a column selection line connected to said first control terminal of each of said data transfer gates;a charging circuit having an input terminal and two output terminals, said two output terminals of said charging circuit being respectively connected to said bit line and said complementary bit line;a current limiting element having a conduction path and a second control terminal for controlling a conduction state of said conduction path, a first end of said conduction path of said current limiting element being connected to said input terminal of said charging circuit and said second control terminal being connected to said column selection line; andfirst potential supplying means connected to a second end of said conduction path of said current limiting element, for applying a first potential thereto, wherein said current limiting element is a depletion type NMOS transistor which has source and drain terminals and a gate electrode and said current limiting element threshold voltage is negative, said first and second ends of said conduction path being said source and drain terminals and said second control terminal being said gate electrode.