Patent ID: 6127703
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A lateral thin-film Silicon-On-Insulator (SOI) PMOS device comprising a semiconductor substrate, a buried insulating layer on said substrate, and a lateral PMOS transistor device in an SOI layer on said buried insulating layer and having a source region of p-type conductivity formed in a body region of n-type conductivity, a lateral drift region of n-type conductivity type adjacent said body region, a drain region of p-type conductivity and laterally spaced apart from said body region by said lateral drift region, and a gate electrode over a part of said body region in which a channel region is formed during operation and extending over a part of said lateral drift region adjacent said body region, said gate electrode being insulated from said body region and drift region by an insulation region, characterized in that said lateral drift region is provided with a linearly-graded charge profile over at least a major portion of its lateral extent such that the doping level in said lateral drift region increases in a direction from said drain region toward said source region, and in that a surface-adjoining p-type conductivity drain extension region is provided in said drift region and extends from said drain region to adjacent to, but not in direct contact with, said source region.