Patent ID: 7161403
Filing Date: 2007-01-09
Classification: B82Y,G11C,Y10S

Abstract:
1. A master-slave flip-flop circuit, comprising: a data input; a first clock input and a second clock input for providing non-overlapping first and second clock signals; a first input buffer coupled to the data input and the first clock input for gating the data input under the control of the first clock input; a master storage element coupled to the input buffer for storing a first data value representative of the data input, wherein the master storage element is constructed of at least one nanotube switching element; a second input buffer coupled to the master storage element and the second clock input for gating the first data value under the control of the second clock input; a slave storage element coupled to the second input buffer for storing a second data value representative of the first data value, wherein the slave storage element is constructed of at least one nanotube switching element; and a data output coupled to the slave storage element.