Patent ID: 6667653
Filing Date: 2003-12-23
Classification: G05F

Abstract:
A nearly zero temperature coefficient current reference circuit comprising:a positive temperature coefficient current reference circuit having inputs comprising a gate voltage value, a delta voltage value, and a drain voltage value, and having outputs comprising a current reference value, wherein said gate voltage value comprises a positive temperature coefficient value, wherein said delta voltage value comprises a positive temperature coefficient value, wherein said drain voltage value comprises a positive temperature coefficient value, and wherein said current reference value comprises a positive temperature coefficient current reference value; and a negative coefficient current reference circuit having inputs comprising a gate voltage value, a delta voltage value, and a drain voltage value, and having outputs comprising a current reference value, wherein said gate voltage value comprises a negative temperature coefficient value, wherein said delta voltage value comprises a negative temperature coefficient value, wherein said drain voltage value comprises a positive temperature coefficient value, wherein said current reference value comprises a negative temperature coefficient current reference value, and wherein each of said positive temperature coefficient current reference circuit and said negative temperature coefficient current reference circuit comprises: a first MOS transistor having gate, drain, and source, wherein a gate voltage value is coupled from said gate to said source; a second MOS transistor having gate, drain, and source, wherein said second MOS transistor is of the same size and type as said first said MOS transistor, wherein said source is coupled to said first MOS transistor source, and wherein said gate voltage value plus a delta voltage value is coupled from said gate to said source, a means of forcing drain voltage value from said drain to said source of said first MOS transistor and from said drain to said source of said second MOS transistor such that said first MOS transistor and said second MOS transistor conduct drain currents in the linear mode; and a means of subtracting said first MCS transistor drain current from said second MOS transistor drain current to thereby create a current reference wherein said current reference does not depend upon the threshold voltage of said first and second MOS transistors; and a means of adding said positive temperature coefficient current reference value to said negative temperature coefficient current reference value to thereby obtain a nearly zero temperature coefficient current reference.