Patent ID: 6287928
Filing Date: 2001-09-11
Classification: B05D,B82Y,G11C,H01L,Y10S

Abstract:
A method of fabricating transistor which has an npn or pnp junction formed from quantum dots arrayed on the surface of a substrate having an insulation layer on the surface thereof, which comprises the step of arraying donor impurities and accepter impurities with a pitch of the size of said metalloprotein complex on the surface of said substrates said method composing the steps of:(a) fabricating metalloprotein complex hetero-trimer by holding accepter impurities or donor impurities on both sides of said donor impurities and said accepter impurities formed from metal atom aggregates;(b) having metalloprotein complex hetero-trimer adsorbed onto an LB membrane developed on the surface of an aqueous solution;(c) placing said LB membrane having said metalloprotein complex hetero-trimer adsorbed thereon on a substrate which is durable to temperatures beyond the burn-out temperature of protein;(d) burning out said protein through heat treatment in an inert gas that does not react with said substrate; and(e) reducing said metal atom aggregates in a reducing atmosphere; which further comprises the steps of:(f) forming an n-type region, a p-type region and a pn junction by diffusing the donor impurities and the accepter impurities via said insulation layer into said substrate by heat treatment;(g) forming an electrode section by patterning electrodes of a specified configuration; and(h) irradiating said n-type region, p-type region and said electrode section with electron beam of a scanning electron microscope, of which beam width is set to be not greater than said pitch, in vacuum in the presence of a trace of carbon compound, while scanning said electron beam to have carbon vapor-deposited between the n-type region and the electrode section, and between the p-type region and the electrode section, thereby forming lead wires.