Patent ID: 6048800
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A process for planarizing a surface of a semiconductor device, comprising the sequential steps of:(a) forming at least two first and second overlapped stepped portions on a semiconductor body, said first and second stepped portions having an exposed vertical edge, said second stepped portion being formed only partially over said first stepped portion;(b) covering, with a first layer, said first and second overlapped stepped portions and at least a portion of said semiconductor body;(c) repeating (k-1) times the steps of forming on said first layer a 2m-th layer having a higher polishing rate than that of said first layer, where m is 1,2 . . . k-1, and 2.ltoreq.k, and subsequently forming on a 2m-th layer a (2m+1)-th layer having a lower polishing rate than that of said 2m-th layer;(d) forming over the foregoing a 2k-th layer having a higher polishing rate than that of last 2m th+1 layer; and(e) polishing all of the layers until the first layer formed on an uppermost portion of said at least first and second overlapped stepped portions is exposed.