Patent ID: 8569810
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate structure on a channel portion of a semiconductor substrate; a source region and a drain region on opposing sides of the channel portion of the semiconductor substrate; an interlevel dielectric layer present on the semiconductor substrate, the source region, the drain region and the gate structure; an opening to at least one of the source region and the drain region present through the interlevel dielectric layer; at least one dielectric sidewall spacer in direct contact with a sidewall of the opening; a metal semiconductor alloy contact present at a base portion of the opening and extending into the semiconductor substrate, wherein a portion of the metal semiconductor alloy contact that extends into the semiconductor substrate is present under and in direct contact with a base surface of the at least one dielectric sidewall spacer, wherein sidewalls of the metal semiconductor alloy contact are substantially aligned with the sidewall of the opening; and an interconnect filling the opening, wherein the interconnect is in contact with the metal semiconductor alloy contact and the at least one dielectric sidewall spacer.