Patent ID: 8230402
Filing Date: 2012-07-24
Classification: G06F

Abstract:
1. A method for testing and debugging of dynamic binary translation wherein a dynamic binary translator allows a target binary to be executed transparently on a host machine having a different computer architecture than a target machine, and wherein, at run-time, the dynamic binary translator translates the target binary to produce a same program behavior on the host machine as when the target binary is executed on the target machine, the method comprising: selecting a minimum set of target machine states for simulation at run-time; translating a series of target machine instructions from the target binary into a series of host machine instructions; during translation, inserting a plurality of check points into the series of host machine instructions, each check point being configured to determine a simulated target machine state using information saved by the translated target binary, wherein inserting the plurality of check points further comprises attempting to insert a check point in the series of host machine instructions at a virtual boundary of a target machine instruction, and in the event that the virtual boundary is blurred due to overlapping of the host machine instructions for at least two target machine instructions, omitting the insertion of the check point at the blurred virtual boundary; during translation, inserting a plurality of verification points into the series of host machine instructions; executing the series of host machine instructions, including the check points and verification points; wherein the execution of a check point determines a simulated target machine state using information saved by the translated target binary; and wherein the execution of a verification point sends information pertaining to simulated target machine states to an external verifier.