Patent ID: 6778599
Filing Date: 2004-08-17
Classification: H03H,H04L

Abstract:
A digital data receiver, comprising:a front end, coupled to receive an input signal transmitted over a communication channel, the signal representing a stream of transmitted symbols with a given input symbol rate, and to generate, responsive to the input signal, a stream of received samples at a processing rate that is a non-integer rational multiple of the input symbol rate; a feed-forward equalizer, coupled to receive input samples at the processing rate, responsive to the received samples, and to generate forward-equalized samples at the input symbol rate, the feed-forward equalizer comprising: a first plurality of taps, arranged in series to receive a succession of the input samples at the processing rate; a second plurality of registers operative to store filter coefficients in a number of groups, such that each group contains one filter coefficient for each of the first plurality of taps; a third plurality of multipliers, coupled to multiply the samples in the taps by the corresponding filter coefficients so as to generate respective tap outputs for each one of the groups; one or more summers, coupled to sum the tap outputs for each one of the groups, thus generating respective group equalized partial sums; and at least one switch, operative to select among the groups at the input symbol rate, so that the equalized partial sums are output in alternation as the forward-equalized samples; and decision circuitry, coupled to process the forward-equalized samples so as to generate a stream of estimated symbols at the input symbol rate.