Patent ID: 7161223
Filing Date: 2007-01-09
Classification: H01L,H03K

Abstract:
1. A pn junction diode for an integrated circuit comprising: a substrate of a first conductivity type; a first region of relatively thick material formed on a surface of the substrate; a second region of relatively thick material formed on the surface of the substrate a predetermined lateral distance from the first region; a first contact of a second conductivity type with high dopant density formed in the substrate adjacent the surface of the substrate, the first contact is positioned between the first and second regions, wherein first edges of the first and second regions are used as a mask to define the edges of the first contact; a first top gate of the first conductivity type formed in the substrate adjacent the surface of the substrate, a first edge of the first top gate is adjacent a second edge of to first region, wherein the lateral length of the first region defines the lateral distance between the first top gate and the first contact; and a second top gate of the first conductivity type formed in the substrate adjacent the surface of the substrate, a first edge of the second top gate is adjacent a second edge of the second region, wherein the lateral length of the second region defines the lateral distance between the second top gate and the first contact.