Patent ID: 8667231
Filing Date: 2014-03-04
Classification: G06F

Abstract:
1. A computer implemented method for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread, the method comprising: executing at a computing system a string of instructions to complete a transaction of the first thread, beginning with one instruction of the string of instructions; determining at the computing system whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread; based on determining that the one instruction is part of the active AIG, determining whether a private-to-transaction (PTRAN) bit associated with an address of the one instruction in a main memory of the computing system is set, the PTRAN bit being located in the main memory, the main memory comprising a plurality of memory increments, and each of the plurality of memory increments having a respective directly addressable PTRAN bit in the main memory; based on determining that the PTRAN bit associated with the address of the one instruction in the main memory is not set: executing at the computing system the one instruction under a normal execution mode based on determining that the one instruction is not part of an active AIG.