Patent ID: 6195305
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A semiconductor integrated circuit comprising:an external terminal which receives an external power supply voltage;an internal voltage generation circuit which generates either or both of a low voltage lower than said external power supply voltage and a high voltage higher than said external power supply voltage;a first internal circuit operating on said external power supply voltage or said high voltage; anda second internal circuit operating on said low voltage,wherein said first internal circuit comprises a first MOSFET with a gate insulation film having a large thickness adapted to said external power supply voltage or high voltage,wherein said second internal circuit comprises a second MOSFET with a gate insulation film having a small thickness adapted to said low voltage,wherein said first internal circuit comprises a third internal circuit operating on said high voltage,wherein said second internal circuit comprises a fourth internal circuit operated in association with the operation of said third internal circuit, andwherein said fourth internal circuit is operated by an operation timing signal which is delayed from the operation timing signal of said third internal circuit by a first delay circuit including a MOSFET having a gate insulation film having said large thickness.