Patent ID: 6229335
Filing Date: 2001-05-08
Classification: H03K

Abstract:
An input/output buffer capable of supporting a multiple of transmission buses, wherein the input/output buffer is connected to a microprocessor connector through transmission lines, the input/output buffer comprising:a coordinating controller;a logic control circuit for receiving a microprocessor-type signal;a first transistor and a second transistor coupled to the logic control circuit and an input/output pad of the input/output buffer, wherein both the first and the second transistors are controlled by the logic control circuit;a first resistor element coupled to a terminal voltage source and a terminal of the first transistor, wherein the first resistor element is controlled by the coordinating controller;a second resistor element coupled to a terminal voltage source and a terminal of the second transistor, wherein the second resistor element is also able to pick up an external control signal for determining its state of conductivity; anda buffer for receiving a signal voltage, an input terminal is connected to a reference voltage, and the signal voltage is compared with the reference voltage to generate an output voltage to the coordinating controller, whereupon the coordinating controller then modifies the resistance of the first resistor element according to the output voltage from the buffer,wherein when the microprocessor-type signal is at a first voltage level, the first transistor and the second resistor element are conductive so that the transmission lines follow the specification of a first transmission bus, whereas when the microprocessor detection signal is at a second voltage level, the first transistor, the second transistor and the first resistor element are all conductive so that the transmission lines follow the specification of a second transmission bus.