Patent ID: 6130470
Filing Date: 2000-10-10
Classification: H01L,Y10S

Abstract:
A flip-flop based memory cell having enhanced cell capacitance, the memory cell comprising:a portion of a semiconductor substrate;a first pull down transistor coupled to a first storage node; anda second pull down transistor coupled to a second storage node, wherein the first pull down transistor is adjacent the second pull down transistor and the first pull down transistor is separated from the second pull down transistor by a trench formed in the portion of the semiconductor substrate, the trench including a first trench wall, a second trench wall spaced from the first trench wall, a first conductive plate being disposed on the first trench wall and a second conductive plate being disposed on the second trench wall, the first and second conductive plates being insulated from the semiconductor substrate, whereby conductive material associated with the first and second plates enhances the capacitance associated with at least one of the first storage node and the second storage node.