Patent ID: 6472734
Filing Date: 2002-10-29
Classification: H01L,H05K

Abstract:
A stacked semiconductor device comprising:a first wiring board; and a second wiring board whose surface is opposed to an underside of the first wiring board, wherein the first wiring board includes a wiring pattern formed on at least one surface of the first wiring board, a first semiconductor element connected to the wiring pattern and arranged on the underside of the first wiring board, a first connecting section formed on the surface of the first wiring board and used to connect the first wiring board to an external device, and a second connecting section formed on the underside of the first wiring board and used to connect the first wiring board to the external device; the second wiring board includes a wiring pattern formed on at least one surface of the second wiring board, a second semiconductor element connected to the wiring pattern and arranged on an underside of the second wiring board, a third connecting section formed on the surface of the second wiring board and used to connect the second wiring board to the external device, and a fourth connecting section formed on the underside of the second wiring board and used to connect the second wiring board to the external device; the second connecting section has a first external connecting land; the third connecting section is arranged opposite to the first external connecting land and has a second external connecting land which is smaller than the first external connecting land; and the second and third connecting sections are formed such that a combined thickness thereof provides a given space between the first semiconductor element and the second wiring board.