Patent ID: 7510930
Filing Date: 2009-03-31
Classification: H01L

Abstract:
1. A method for fabricating a recessed gate MOS transistor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate has a main surface, an array area and a support circuit area; forming a plurality of trench capacitors inlaid in the array area of the semiconductor substrate, wherein each of the trench capacitors is capped by a trench top layer extruding from the main surface; depositing an etching stop layer on the main surface and covering the trench top layer; forming a masking spacer on sidewall of the trench top layer; oxidizing the masking spacer to form an oxide spacer; using the oxide spacer as an etching hard mask, dry etching the etching stop layer and the semiconductor substrate, thereby forming a self-aligned gate trench; forming a gate dielectric layer on side and bottom of the gate trench; and forming a gate material layer on the gate dielectric layer to fill the gate trench.