Patent ID: 7151024
Filing Date: 2006-12-19
Classification: H01L

Abstract:
1. A method of forming memory cells comprising: patterning and etching a substrate comprising silicon carbide doped a first conductivity type so as to form trenches extending along intersecting first and second directions so as to define a plurality of vertically extending pillars; filling the trenches with insulator; selectively removing the insulator from trenches extending in the first direction; doping upper regions of the pillars and the trenches extending in the first direction with dopant of a second conductivity type so as to define drain regions and source lines respectively; depositing gate dielectric along first sides of the pillars; depositing capacitor dielectric along opposed second sides of the pillars; forming conductive word lines extending along the first direction atop the gate dielectric; forming body capacitor plates atop the capacitor dielectric; and forming data/bit lines interconnecting drain regions along the second direction.