Patent ID: 6823072
Filing Date: 2004-11-23
Classification: H04N

Abstract:
A peak to peak detector circuit for use in a television receiver, the circuit comprising: means for receiving left (L) and right (R) stereo audio channel signals and forming an L+R audio signal indicative of the sum of the left and right stereo audio channel signals; clamping means responsive to said L+R audio signal for generating a variable dc signal having a time and amplitude relationship corresponding to said L+R audio signal, wherein said clamping means limits a minimum amplitude associated with said variable dc signal to a predetermined minimal value; and rectifying means responsive to said variable dc signal for generating a dc output signal having an amplitude proportional to the peak to peak amplitude of said L +R audio signal,wherein said clamping means comprises a summing amplifier having an input terminal for receiving said L+R audio signal and an output terminal coupled to a first terminal of a resistor, a capacitor having first and second terminals, said first terminal coupled to a second terminal of said resistor, and said second terminal coupled to the cathode electrode of a diode; and wherein said rectifying means includes a second capacitor coupled between a second diode and a reference potential, wherein when said second diode conducts, said second capacitor is charged according to said dc output signal; and wherein said rectifying means further includes a second resistor in parallel with said second capacitor to form a discharge circuit operative to discharge said detector circuit according to a given discharge time value when said L+R audio signal is of substantially zero amplitude.