Patent ID: 7379335
Filing Date: 2008-05-27
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array having a plurality of memory cell units each having a plurality of electrically-programmable memory cell connected in series; a plurality of word lines each connected to each of control gates of said plurality of memory cells, said plurality of word lines including a selected word line connected to a control gate of selected one of said memory cells for programming, and a plurality of unselected word lines different from said selected word line; a bit line connected to one end of said memory cell unit; and a source line connected to an other end of the memory cell unit; wherein, when data is programmed into the selected memory cells, a first potential is applied to said selected word line, and a first unselected word line adjacent, toward a source line side, to said selected word line is set to floating state, and thereafter, a second potential which is higher than said first potential is applied to said selected word line.