Patent ID: 7949917
Filing Date: 2011-05-24
Classification: G06F

Abstract:
1. A system, comprising: storage comprising first and second data; and circuit logic coupled to the storage, said circuit logic receives a plurality of clock signals; wherein, as a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic; wherein the system resets said circuit logic between providing said first data and providing said second data; wherein said circuit logic comprises a first flip-flop (FF), a second FF, a third FF and a fourth FF, and wherein the first and second FFs couple without an intervening FF, and wherein the third and fourth FFs couple without an intervening FF, and wherein the first and second FFs operate using a clock signal of different frequency than that used by the third and fourth FFs.