Patent ID: 8653670
Filing Date: 2014-02-18
Classification: H01L

Abstract:
1. An interconnect assembly for an embedded chip package, the interconnect assembly comprising: a dielectric layer; a first metal layer comprising a plurality of upper contact pads, wherein a first surface of the plurality of upper contact pads is affixed to a top surface of the dielectric layer; a second metal layer comprising a plurality of lower contact pads, wherein a first surface of the plurality of lower contact pads is affixed to a bottom surface of the dielectric layer; a plurality of metalized connections formed through the dielectric layer and in contact with the plurality of upper contact pads and the plurality of lower contact pads to form electrical connections therebetween, wherein a portion of a bottom surface of the plurality of metalized connections is directly coupled to the top surface of the dielectric layer; wherein at least one input/output (I/O) of a first side of the interconnect assembly is formed on a second surface of the plurality of lower contact pads, opposite the first surface of the plurality of lower contact pads; and wherein at least one I/O of a second side of the interconnect assembly is formed on a second surface of the plurality of upper contact pads, opposite the first surface of the plurality of upper contact pads.