Patent ID: 9069911
Filing Date: 2015-06-30
Classification: G06F,Y02D

Abstract:
1. A data processing system comprising: a first single chip data processor; a second single chip data processor including a central processing unit (CPU), a first external interface circuit, an internal bus coupled to the CPU and the first external interface circuit, and an internal circuit; an external device; a first external bus coupled to the first and second single chip data processor; and a second external bus coupled to the second single chip data processor and the external device, wherein the internal circuit is coupled to the first external bus and the second external bus, wherein the second single chip data processor has a standby mode in which power is supplied to the internal circuit and power is not supplied to the first external interface, and has an operating mode in which power is supplied to the second single chip data processor and the CPU fetches an instruction, wherein, when the second single chip data processor is in the operating mode, the first data processor accesses the second data processor through the first external interface circuit and the second data processor supplies a signal to the second external bus, and wherein, when the second single chip data processor is in the standby mode, the first data processor accesses the external device through the internal circuit.