Patent ID: 6320126
Filing Date: 2001-11-20
Classification: H01L,H05K,Y02P

Abstract:
An integrated circuit package comprising:a carrier having a pair of major opposing external surfaces, an external side surface disposed between said major opposing surfaces, at least one routing strip integral with said carrier and a cavity defined in said carrier and extending through said carrier between said pair of major opposing surfaces, a portion of said routing strip extending into said cavity;at least one terminal for external connection to said carrier disposed on said side surface of said carrier, said at least one terminal being electrically connected with said at least one routing strip;a chip adhered to said carrier along one of said opposing major surfaces, said chip having at least one bonding pad extending into said cavity;an electrical connection disposed within said cavity connecting said at least one bonding pad to said at least one routing strip; andpotting material disposed in said cavity covering said portion of said at least one routing strip disposed within said cavity, said electrical connection and said at least one bonding pad and forming a surface coplanar with at the other of said pair of opposing major surfaces.