Patent ID: 6665230
Filing Date: 2003-12-16
Classification: G11C,H03K

Abstract:
Circuitry for delaying an input signal according to a programmable delay value, comprising:clock capturing circuitry for determining a number of delay elements needed to capture a clock cycle of a clock signal with the same frequency as the input signal; delay calculation circuitry for: receiving the number of delay elements needed to capture the clock cycle from the clock capturing circuitry; receiving the programmable delay value; and calculating a number of delay elements needed to delay the input signal by the programmable delay value; and delay circuitry comprising: an input for receiving the input signal; a select input for receiving the number of delay elements needed to delay the input signal by the programmable delay value from the delay calculation circuitry; and a chain of delay elements, wherein the number of delay elements that the input signal is passed through is determined by the select input.