Patent ID: 6762640
Filing Date: 2004-07-13
Classification: G05F

Abstract:
A bias voltage generating circuit comprising:a first power terminal for receiving a first voltage from outside; a second power terminal for receiving a second voltage from the outside; a bias voltage output terminal for outputting a bias voltage to the outside; a first MOS transistor having a drain and a gate connected to the first power terminal and a backgate connected to the second power terminal; a second MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the first-MOS transistor, and a backgate connected to the second power terminal; a third MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the first MOS transistor, and a backgate connected to the second power terminal; a fourth MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the second MOS transistor, and a backgate connected to the second power terminal; a fifth MOS transistor having a drain connected to the source of the third MOS transistor, a gate connected to the source of the fourth MOS transistor, a source connected to the bias voltage output terminal, and a backgate connected to the first power terminal; a first capacitive element having one end connected to the source of the first MOS transistor and the other end for receiving a first clock signal; a second capacitive element having one end connected to the source of the second MOS transistor and the other end for receiving a second clock signal having a phase opposite to that of the first clock signal; a third capacitive element having one end connected to the source of the third MOS transistor and the other end for receiving a third clock signal; and a fourth capacitive element having one end connected to the source of the fourth MOS transistor and the other end for receiving a fourth clock signal.