Patent ID: 7279410
Filing Date: 2007-10-09
Classification: H01L

Abstract:
1. A method for forming an integrated circuit structure comprising: forming a first etch stop layer over said integrated circuit structure associated with a substrate; forming a second etch stop layer on the first etch stop layer; patterning a portion of the second etch stop layer, thereby defining a first region having the first etch stop layer and a second region having the second etch stop layer overlying the first etch stop layer, and wherein the second region is a region that experiences etching at a rate that is greater than the first region, wherein the second etch stop layer is not situated in the first region; forming a layer of dielectric material over the first and second regions; forming a cap layer over the layer of dielectric material; patterning the cap layer and the layer of dielectric material to define two via or trench openings, wherein a first via or trench opening is in the first region and a second via or trench opening is in the second region, and both the first and second via or trench openings extend down to the first etch stop layer; removing the first etch stop layer with the first and second via or trench openings; and filling the two via or trench openings with a conductive material, wherein the cap layer has an optimized thickness.