Patent ID: 6387762
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method of manufacturing a ferroelectric memory device comprising the steps of:stacking a ferroelectric layer and a conductor layer on a semiconductor substrate in order, forming a gate structure section including the ferroelectric layer and the conductor layer by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into a pair of regions spaced apart from each other with the gate structure section interposed therebetween in a surface layer section of the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the semiconductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities, thereby to form a pair of impurity diffused layers in the pair of regions respectively.