Patent ID: 6768195
Filing Date: 2004-07-27
Classification: H01L

Abstract:
A multi-chip semiconductor device comprising:a first semiconductor device baying a first surface, the first surface including a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members; and a second semiconductor device having a second surface, the second surface including a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device, wherein a first plurality of circuit pads on the first surface are substantially aligned with a second plurality of circuit pads on the second surface, such that a center point of each of the first plurality of circuit pads is located within three microns, in a lateral direction, the lateral direction parallel to a plane through one of the first surface and the second surface, of a corresponding center point of each of the second plurality of circuit pads, and wherein the first plurality of circuit pads are capacitively coupled to the second plurality of circuit pads.