Patent ID: 6706591
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method of fabricating a capacitor structure for a dynamic random access memory (DRAM), device, on a semiconductor substrate, comprising the steps of:providing a transfer gate transistor on said semiconductor substrate, comprised of a gate structure on an underlying gate insulator layer, and comprised with a source/drain region located in an area of said semiconductor substrate not covered by said gate structure; forming a conductive plug structure in an opening in an insulator layer, with said conductive plug structure overlying and contacting a portion of a top surface of a source region; depositing an intrinsic polysilicon layer on the top surface of said insulator layer, and on the top surface of said conductive plug structure; performing a series of ion implantation procedures at various implantation energies, to create ion implanted veins at different depths in said intrinsic polysilicon layer, with regions of said intrinsic polysilicon layer located between said ion implanted veins remaining as intrinsic polysilicon regions; performing a dry etch procedure to define a storage node structure from said intrinsic polysilicon layer, with an isotropic component of said dry etch procedure selectively etching lateral grooves in said ion implanted veins, resulting in a necked profile, storage node structure featuring said lateral grooves in the sides of said necked profile, storage node structure; forming a capacitor dielectric layer on said necked profile, storage node structure; and forming an upper electrode structure on said capacitor dielectric layer resulting in said capacitor structure comprised of said upper electrode structure, of said capacitor dielectric layer, and of underlying, said necked profile, storage node structure.