Patent ID: 6358843
Filing Date: 2002-03-19
Classification: G03F,H01L

Abstract:
In a method of fabricating a via of an interconnecting line in an integrated circuit comprising the steps of:forming at least one connecting line adjacent a semiconductor substrate; forming an insulating layer on said connecting line; forming a photoresist layer on said insulating layer; exposing the photoresist layer to a first line exposure pattern of a dosage insufficient to develop the exposed pattern; rotating the exposure pattern and the semiconductor substrate 90Â° relative to each other; exposing the photoresist layer to a second overlapping line exposure pattern of a dosage insufficient to develop the exposed pattern while the semiconductor substrate is in the second position, the overlapping exposures creating via photoresist areas with the combined dosage being sufficient to develop the via photoresist areas; and developing the overlapping exposures of the via areas in the photoresist to create via openings smaller in the insulating layer than achievable by a single exposure.