Patent ID: 6191039
Filing Date: 2001-02-20
Classification: C09G,H01L,Y10S

Abstract:
A method of fabricating a planarized structure on a semiconductor substrate, wherein doped polysilicon plugs are embedded in contact openings in a layer of silicon oxide, the method comprising the following steps:providing a semiconductor substrate having a layer of silicon oxide deposited thereon and into which are etched contact openings;providing a layer of doped polysilicon above the layer of silicon oxide and within the contact openings;chemical-mechanical polishing the layer of doped polysilicon to the layer of silicon oxide by a two-step process, the first CMP step comprising chemical-mechanical polishing using a first polishing slurry which is selective to said doped polysilicon; andfurther chemical-mechanical polishing the layer of doped polysilicon by a second CMP step comprising chemical-mechanical polishing using a second polishing slurry which polishes both the doped polysilicon and the silicon oxide.