Patent ID: 7870553
Filing Date: 2011-01-11
Classification: G06F,Y02D

Abstract:
1. A multiprocessing system, comprising: a multithreading microprocessor, comprising: a multiprocessor operating system (OS), configured to schedule execution of said threads on said first plurality of TCs, wherein a thread of said threads executing on one of said first plurality of TCs is configured to update said shared TLB, and prior to updating said TLB to: wherein said multithreading microprocessor further comprises: wherein said TLB-disabling thread disabling interrupts comprises disabling interrupts on said VPE; wherein said multithreading microprocessor further comprises: wherein said TLB-disabling thread is further configured, prior to updating said shared TLB, to disable said instruction scheduler from dispatching instructions from any of said first and second plurality of TCs except from said one of said plurality of TCs on which said TLB-updating thread is executing; and wherein said TLB-disabling thread is further configured, after updating said shared TLB, to restore said instruction scheduler to an instruction-dispatching state said instruction scheduler was in prior to disabling said instruction scheduler from dispatching instructions from any of said first and second plurality of TCs except from said one of said plurality of TCs on which said TLB-updating thread is executing.