Patent ID: 6534853
Filing Date: 2003-03-18
Classification: G01R,H01L

Abstract:
A semiconductor wafer comprises:a plurality of semiconductor chips, each chip having an integrated circuit forming surface formed on the same plane of the semiconductor wafer, wherein the chip has a plurality of bonding pads on the integrated circuit forming surface; a plurality of cutting paths, each cutting path being formed between two adjoining chips; a plurality of metal interconnects being on the integrated circuit forming surface of the chip and electrically connecting with the corresponding bonding pad respectively; a passivation layer covering the plurality of the metal interconnects and having a plurality of the first openings and the second openings; a plurality of test pads located at the first openings of the passivation layer and connecting to the corresponding bonding pad through a corresponding metal interconnect; and a plurality of contact pads being located at the second opening of the passivation layer, wherein the contact pad is connected in series with corresponding metal interconnect between the corresponding bonding pad and test pad.