Patent ID: 6778431
Filing Date: 2004-08-17
Classification: G11C

Abstract:
A magnetic memory circuit, comprising:a plurality of memory cells; a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells; at least one bit line programming circuit configurable as at least one of a current source for generating a programming current for writing a logical state of at least one memory cell, and a current sink for returning the programming current; a first set of switches being disabled at least during a read operation of the memory cells and at least a portion of the first set of switches being selectively enabled during a write operation of the memory cells, each switch in the first set of switches being configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal; at least one sense amplifier; and a second set of switches being disabled at least during a write operation of the memory cells and at least a portion of the second set of switches being selectively enabled during a read operation of the memory cells, each switch in the second set of switches being configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.