Patent ID: 7122412
Filing Date: 2006-10-17
Classification: H01L

Abstract:
1. A method of forming a field effect transistor (FET) structure in a silicon on insulator (SOI) layer, comprising the steps of: providing said SOI layer on a semiconductor substrate; defining a FET shape in said SOI layer with said FET shape having a necked channel region and having spaced wider silicon shapes disposed on opposite sides of said necked channel region, said necked channel region having a central portion where said necked channel region has its smallest width, and said necked channel region increasing progressively in width on each side of said central portion in directions away from said central portion toward each of said wider silicon shapes; forming a gate insulator layer on sides of said FET shape; forming a gate structure on said central portion of said necked channel region of said FET shape, with said gate structure engaging said gate insulator layer on each side of necked channel region; forming a source/drain region in said wider silicon shapes; forming an insulator spacer on sides of said FET shape not covered by said gate structure, and on sides of said gate structure; and forming a metal silicide layer on said source/drain region resulting in said FET structure comprised with said necked channel region.