Patent ID: 7079579
Filing Date: 2006-07-18
Classification: H04N

Abstract:
1. A block matching processor for flexibly supporting block matching motion estimation at motion vector prediction modes for a plurality of matching blocks of pixels having non-uniform sizes that are multiples of a smallest matching block of said plurality of matching blocks, said processor comprising: a plurality of difference unit (D-unit) arrays configured for respectively generating an absolute value of a respective smallest size matching block, each of the plural D-unit array comprising a plurality of D-units that are arranged to correspond with an arrangement of pixels of a respective smallest size matching block, each D-unit array being configured for calculating the pixel-to-pixel differences between the pixels of a current frame and the corresponding pixels of a reference frame and for converting the differences to absolute values; and at least one accumulator unit (A-unit) including a plurality of accumulators, said accumulator unit being connected to the D-unit arrays for generating an SAD (Sum of Absolute Difference) for each smallest size matching block, and an SAD for all of the plurality of matching blocks of pixels having non-uniform sizes by hierarchical addition of the absolute values of the smallest size matching blocks received from the D-unit arrays.