Patent ID: 6870879
Filing Date: 2005-03-22
Classification: H03H

Abstract:
1. An interpolation filter circuit for shaping a power spectral density (PSD) of a digital output signal of a digital transmission communication device, the interpolation filter circuit performing filtering and clockrate conversion of a digital input signal received from a data source with a symbol-clock data rate, the interpolation filter circuit comprising: a second order Finite Impulse Response (FIR) filter for receiving the digital input signal having the symbol-clock data rate and for emitting a filtered digital output signal having an upper cutoff frequency which is equal to half the symbol-clock data rate, said FIR filter filtering the digital input signal in such a way that a power spectral density characteristic of the emitted filtered digital output signal coincides with a prescribed desired power spectral density characteristic, the desired power spectral density characteristic being constant in a passband frequency range; a resampling filter connected downstream of said FIR filter for increasing the clock data rate of the digital input signal filtered by said FIR filter, said resampling filter emitting a resampled digital signal; and a second order IIR filter connected downstream of said resampling filter and emitting a filtered digital output signal, said IIR filter for filtering the resampled digital signal emitted by the resampling filter in such a way that, in a cutoff frequency range having a lower cutoff frequency equal to half the symbol-clock data rate, a power spectral density characteristic of the filtered digital output signal emitted by said IIR filter coincides with a prescribed desired power spectral density characteristic, the desired power spectral density characteristic falling with a specific edge steepness in the cutoff frequency range; said FIR filter including: a first delay element and a second delay element; a data line connecting said first delay element and said second delay element into a chain; a first multiplier for multiplying the digital input signal by a first filter coefficient and emitting a digital data signal; a second multiplier for multiplying the digital data signal emitted by said first delay element by a second filter coefficient and emitting a digital data signal; and a third multiplier for multiplying the digital data signal emitted by said second delay element by a third filter coefficient and emitting a digital data signal; the second filter coefficient being not greater than the negative of the first filter coefficient, and the first filter coefficient being identical to the third filter coefficient.