Patent ID: 9130056
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A method of dicing a semiconductor wafer having integrated circuits on a front side thereof, the method comprising: laminating a pre-patterned bi-layer wafer-level underfill material stack on the integrated circuits of the semiconductor wafer, the pre-patterned bi-layer wafer-level underfill material stack having regions corresponding to the integrated circuits and gaps corresponding to dicing streets between the integrated circuits; plasma etching to form trenches in the semiconductor wafer in alignment with the dicing streets to singulate the integrated circuits, wherein an upper layer of the pre-patterned bi-layer wafer-level underfill material stack protects the integrated circuits during the plasma etching; and subsequent to the plasma etching, removing some but not all remaining portions of the upper layer of the pre-patterned bi-layer wafer-level underfill material stack.