Patent ID: 6052767
Filing Date: 2000-04-18
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array having a plurality of memory cells and for writing data to and reading the same from each of addresses specified by external address signals;at least one redundant memory cell array for writing and reading data in place of a defective memory cell when the defective memory cell exists in said memory cell array; anda memory selective unit for determining whether one of serially-input addresses corresponds to each of addresses of defective memory cells;wherein said memory selective unit includes defective address judging means for sequentially judging whether or not the serially-input addresses correspond to the addresses of the defective memory cells without a serial-to-parallel conversion of the serially input addresses;wherein said memory selective unit includes defective address judging means for judging whether or not said each serially-input address corresponds to an address of a defective memory cell prior to being subjected to serial-to-parallel conversion;wherein said defective address judging means comprises a parallel/serial conversion circuit for capturing addresses of defective memory cells from external serial addresses, and a logical operation circuit for comparing the addresses of the defective memory cells and the serial addresses and outputting the results of comparison therefrom; andwherein said logical operation circuit comprises an exclusive OR operation circuit, said memory selective unit further comprising a redundant memory selective circuit connected to said exclusive OR operation circuit, and said redundant memory selective circuit outputting a signal for selecting an address of said redundant memory cell array in place of the memory cell array when the results of comparison result in coincidence.