Patent ID: 7132866
Filing Date: 2006-11-07
Classification: H03L

Abstract:
1. A method of controlling a delay-locked loop (DLL) module, said method comprising: receiving a clock signal; comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances; producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances; utilizing the correction signal to change a delay setting; and forwarding the correction signal to slave DLL modules in communication with the DLL module; wherein the comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced; further comprising the step of updating a state register for the DLL based on whether the DLL is in a locked state.