Patent ID: 6720631
Filing Date: 2004-04-13
Classification: H01L,Y10S

Abstract:
A transistor comprising:a gate dielectric disposed over a semiconductor substrate; a gate electrode disposed over said gate dielectric, said gate electrode having laterally opposed sidewalls; a pair of tip regions disposed within said semiconductor substrate adjacent to said gate electrode, said pair of tip regions being shallow, heavily doped, and substantially aligned to said sidewalls of said gate electrode; a pair of spacer structures disposed adjacent to said gate electrode, said pair of spacer structures being deposited and comprising: a first layer, said first layer covering said sidewalls of said gate electrode and said semiconductor substrate adjacent to said sidewalls; and a second layer, said second layer covering said first layer; and a pair of source/drain regions within said semiconductor substrate adjacent to said pair of spacer structures, wherein a supply voltage of less than 5 volts is coupled to said pair of source/drain regions to reduce hot electron charging effects in said gate dielectric to acceptable levels.