Patent ID: 6842033
Filing Date: 2005-01-11
Classification: G01R,H03K

Abstract:
1. An apparatus for controlling a delay time of a signal in a semiconductor device, the apparatus comprising: a test mode delay section for receiving a pulse signal and outputting first to (N+1)th control signals; and a test delay section for delaying an input signal for a predetermined time by the first to the (N+1)th control signals and outputting the delayed signal, wherein a delay time required for outputting the input signal as an output signal is controlled according to an enabled control signal from among the first to the (N+1)th control signals, the first to the (N+1)th control signals are sequentially enabled by the pulse signal, and, after the (N−1)th control signal is enabled, the Nth and the (N+1)th control signals are alternately enabled every time the pulse signal is toggled.