Patent ID: 7763506
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A method for producing an integrated circuit including a vertical JFET, the method comprising: creating a mask on a main surface of a semiconductor substrate having a semiconductor layer of a first conductivity type at the main surface; implanting a second conductivity type material into the main surface at a first and a second side of the mask; removing the mask; creating a source layer of semiconductor material of the first conductivity type on the main surface of the substrate; and short-circuiting the second conductivity type material of the first or the second side with the source layer of the first conductivity type; wherein the short-circuiting includes removing semiconductor material at the first and/or second side of the mask up to the second conductivity type material, and depositing conductive material on the source layer and on the second conductivity type material at the first or the second side.