Patent ID: 6042444
Filing Date: 2000-03-28
Classification: H01J

Abstract:
A method for fabricating a field emission display cathode, the method comprising the steps of:forming a pad oxide layer on a substrate;forming a doped polysilicon layer on the pad oxide layer;patterning a part of the doped polysilicon layer to form a plurality of field emitters on top of the remaining doped polysilicon layer, wherein each of the field emitters has an chimney shape with a top surface and a sidewall meeting other with an acute angle;patterning the remaining doped polysilicon layer under the field emitters to form a plurality of field emission arrays, wherein each of the field emission arrays has at least one field emitter;performing a sharpening process to sharpen the acute angle between the top surface and the sidewall of each field emitter;forming a first dielectric layer and a second dielectric layer over the substrate in sequence, wherein the first dielectric layer and the second dielectric layer are conformal to the field emitters and the doped polysilicon layer;forming a third dielectric layer on the second dielectric layer;planarizing the third dielectric layer to expose the second dielectric layer on a top portion of each of the field emitters;removing the exposed second dielectric layer;forming an oxide layer on the third dielectric layer and a top surface of the first dielectric layer on the top portion of the field emitter;forming a self-aligned metal layer on the oxide layer;removing a portion of the self-aligned metal layer to expose the oxide layer on the top portion of the field emitter, wherein the remaining self-aligned metal layer is serving as a plurality of gates; andremoving the exposed oxide layer and the first dielectric layer on the top portion of the field emitter.