Patent ID: 6380776
Filing Date: 2002-04-30
Classification: H03L

Abstract:
A method of synchronizing clock signals in a digital circuit, wherein the digital circuit receives an input clock and a reference clock, generates a generated clock from the input clock and synchronizes the generated clock to the reference clock, comprising:sampling a value of the reference clock at a plurality of points near a transition point of the generated clock; determining from the sampling whether the reference clock transitioned from a first state to a second state before, after or within an acceptable range of the transition point of the generated clock; upon determining that the reference clock transitioned before the transition point of the generated clock, shortening one period of the generated clock; upon determining that the reference clock transitioned after the transition point of the generated clock, lengthening one period of the generated clock; and upon determining that the reference clock transitioned within the acceptable range of the transition point of the generated clock, maintaining the period of the generated clock.