Patent ID: 8989202
Filing Date: 2015-03-24
Classification: H04L

Abstract:
1. A network device comprising: a media access controller (MAC) configured to receive a packet received by the network device; a first series of elements configured to forward from the media access controller (MAC) to a backplane, the first series of elements comprising a first processor and a first memory, the first processor configured to process the packet and store corresponding packet data in the first memory; a second series of elements configured to forward data from the backplane to the MAC, the second series of elements comprising a second processor and a second memory; and a path that enables the packet data to be forwarded from an element in the first series of elements to an element in the second series of elements without using the backplane, wherein the element in the first series of elements is a first application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) and the element in the second series of elements is a second FPGA, wherein the first ASIC or FPGA is different from the second FPGA; wherein the element in the second series of elements, which receives the packet data forwarded using the path, is configured to: