Patent ID: 8503967
Filing Date: 2013-08-06
Classification: H03F

Abstract:
1. An amplifier receiving an input signal and providing an output signal in response, comprising: a main amplifier core comprising an input node, an output node and a sum node, the input node being coupled to the input signal and interfacing an interface resistance, and the main amplifier core arranged to provide an interior signal to the sum node and output the output signal at the output node in response to signals provided to the sum node; an auxiliary amplifier core comprising a first auxiliary node and a second auxiliary node, the first auxiliary node coupled to the input node, and the auxiliary amplifier core arranged to provide an auxiliary signal to the second auxiliary node in response to a signal at the first auxiliary node; a feedback circuit coupled between the first auxiliary node and the second auxiliary node, and arranged to provide a feedback resistance between the first auxiliary node and the second auxiliary node; and a weighting circuit coupled between the second auxiliary node and the sum node, and arranged to weight the auxiliary signal by a weighting gain and provide a cancelling signal to the sum node in response to the weighted auxiliary signal; wherein the weighting gain is in association with a ratio between the feedback resistance and the interface resistance.