Patent ID: 6373911
Filing Date: 2002-04-16
Classification: H03L,H04L

Abstract:
A bit synchronization circuit comprising:multi-phase clock generating means for generating mutually different phases of plurality of clocks in synchronism with input reference clock; a plurality of decision means for respectively deciding input data using different phases output from said multi-phase clock generating means as data decision clock; phase comparator means for performing phase comparator between said input data and respective clocks of different phases output from said multi-phase clock generating means; phase determining means for determining a clock occurring level transition timing at substantially center portion of mutually adjacent level transition timings of said input data depending upon a plurality of phase comparator outputs of said phase comparator means; and selection means for selecting and outputting an output of said decision means taking the clock determined by said phase determining means as said data decision clock, phase of said input data to said phase comparator means and said decision means being the same and phases of said clocks to said phase comparator means and said decision means being the same.