Patent ID: 6225642
Filing Date: 2001-05-01
Classification: H01L

Abstract:
A buried channel vertical double-diffusion MOS device wherein electron mobility inside the channel is increased and capacitor effect between a gate and a substrate of a transistor is decreased, comprising:a substrate;a drain region located above the substrate and doped by the first dopants to form a region having a first conductivity;a gate region located above the substrate surface and doped by second dopants to form a region having a second conductivity different than the first conductivity;a source region located in the substrate between two neighboring gate regions and doped by third dopants to form a region having the first conductivity; anda channel region located above the drain region and isolated from the gate region by a gate-insulating layer, the channel region further including;a main region doped by fourth dopants to form a region having the first conductivity;a doping region having a first conductivity under the P-type gate, wherein the doping region is capable of increasing the electron mobility inside the channel and lowering the capacitor effect between the gate and the substrate;a buried channel region located underneath the doping region and the gate insulating layer in the gate region and doped by fifth dopants to form a region having the first conductivity, wherein the fifth dopants in the buried channel are for adjusting the threshold voltage of the buried channel vertical double-diffusion MOS device;a first region doped by sixth dopants to form a region having the second conductivity and located in the substrate between two neighboring gate regions next to the source region with a portion extending to a region underneath the gate; anda second region doped by seventh dopants to form a region having the second conductivity and located beneath the source region next to the first region, but not in direct contact with the source region.