Patent ID: 6041337
Filing Date: 2000-03-21
Classification: G06F

Abstract:
A method for flexibly expanding a digital bus input signal with an efficient implementation for a linear function utilizing spare gates in a Programmable Logic Array or Field Programmable Gate Array for generating an output digital signal for controlling a target digital modules comprising the steps of:(a) generating a difference signal Xd in an UP-DOWN counter module which represents the value of a source-setting pulse stream signal (A) reduced by a feedback pulse stream digital signal (C);(b) adding a N-bit digital intercept parameter value ""a"" to said Xd signal to generate an N-bit digital signal, such that Xd+a=Xa.(c) multiplying said N-bit digital signal Xa by a slope parameter ""b"" to develop an (N+q) bit digital output signal Y, where q represents the digital offset value in binary notation corresponding to the specific value of the slope parameter ""b"" such that bXa=Y and thus Y=bXd+ba.