Patent ID: 6298472
Filing Date: 2001-10-02
Classification: G06F

Abstract:
A method of synthesizing the datapath of a logic system, said datapath having an associated functional behavior, said method comprising essentially the steps of:providing a first abstract description of encoded statements specifying said functional behavior of said datapath of said logic system to a behavioral synthesis tool to generate a second physical description of encoded statements specifying system level circuit structures for performing said functional behavior of said datapath of said logic system;partitioning said second description into a plurality of sub-descriptions corresponding to functional system blocks having at least a datapath block;mapping said sub-descriptions to a set of control signals;controlling an array of re-configurable datapath circuits with said set of control signals to perform said functional behavior of said datapath of said logic hardware, said array being controlled by said set of control signals so as to configure said datapath circuits into groups of datapath circuits to form larger datapath structures to provide increased data throughput and said array being controlled such that said datapath circuits and datapath structures each perform a selected one of a plurality of different functions to simulate said functional behavior of said logic system.