Patent ID: 9070617
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. An intermediate transistor structure, comprising: a compound Group III-V substrate having a source region and a drain region that are spaced apart from each other adjacent to a surface of the substrate and that define a channel there between; a gate stack structure disposed over the channel; a layer of electrically insulating dielectric material disposed over the gate stack structure and over a first portion of the source region and over a first portion of the drain region, the first portion of the source region and the first portion of the drain region each being a portion that underlies a first edge and a second edge, respectively, of the gate stack structure; a source contact precursor comprised of a first layer of amorphous germanium disposed upon a second portion of the source region that is laterally adjacent to the first portion of the source region; a drain contact precursor comprised of a second layer of amorphous germanium disposed upon a second portion of the drain region that is laterally adjacent to the first portion of the drain region; and a layer comprised of metal that overlies the layer of electrically insulating dielectric material, the source contact precursor and the drain contact precursor; where each of the first layer of amorphous germanium and the second layer of amorphous germanium contains phosphorous.