Patent ID: 7485529
Filing Date: 2009-02-03
Classification: G11C,H01L

Abstract:
1. A method of fabricating a non-volatile memory, comprising the steps of: providing a substrate; forming a plurality of stacked gate structures on the substrate, wherein the stacked gate structures are separated from each other by a gap, and each stacked gate structure comprises a select gate dielectric layer, a select gate and a cap layer; forming a source region and a drain region in the substrate, wherein the source region and the drain region are formed separate from each other by at least two stacked gate structures; forming a tunneling dielectric layer over the substrate between every two stacked gate structures, and forming an insulating layer over the source region and the drain region, wherein the insulating layer has a thickness greater than a thickness of the tunneling dielectric layer; forming a first conductive layer over the substrate; patterning the first conductive layer to form a plurality of floating gates between every two neighboring stacked gate structures; forming an inter-gate dielectric layer over the substrate; forming a second conductive layer over the substrate; and patterning the second conductive layer to form a plurality of mutually connected control gates in the gap between every two neighboring stacked gate structures.