Patent ID: 7796439
Filing Date: 2010-09-14
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cell strings arranged along a first direction respectively, each of the memory cell strings including a plurality of memory cells having current paths connected in series along a second direction which is perpendicular to the first direction, each of the memory cells having a charge accumulation layer and a control electrode, the control electrode extending in the first direction and connected to a memory cell located in an adjacent memory cell string; a plurality of bit lines extending in the second direction, each of the bit lines electrically connected to one end of the current path of the associated memory cell string; a source line extending in the first direction and electrically connected to the other end of the current paths of the memory cell strings; a sense amplifier including a plurality of sense amplifier circuits, each of the sense amplifier circuit electrically connected to one of the bit lines, respectively; a data buffer including a plurality of first latch circuits, each of the first latch circuits electrically connected to one of the bit lines; an input terminal holding data from an external device; and a control circuit executing a first verify write operation and a second verify write operation;