Patent ID: 8635583
Filing Date: 2014-01-21
Classification: G06F,H01L

Abstract:
1. A standard cell library stored on a non-transitory computer readable storage device, the standard cell library used by a processor to produce a layout for fabricating at least one aspect of a finished semiconductor device, comprising: the standard cell library including cells wherein at least one transistor in at least one cell is associated with an annotation layer, and the annotation layer itself also defines a gate length biasing to be applied to the at least one transistor of the at least one cell when the processor produces the biased layout, wherein the gate length biasing is an amount of change to a gate length of the at least one transistor, the amount of change is defined by the annotation layer; wherein the annotation layer comprises layout information, and the layout information includes design-specific directives that require implementation of the amount of change to the gate length of the at least one transistor when the processor produces the biased layout.