Patent ID: 8174470
Filing Date: 2012-05-08
Classification: G09G

Abstract:
1. A liquid crystal display (LCD) device comprising: a system supplying a vertical synchronizing signal, a horizontal synchronizing signal and clock signals to a interface circuit, and generating an input voltage from its power source, wherein the input voltage is a source signal of a reference voltage, a high gate voltage and a low gate voltage; a timing controller to generate an initial POL signal, wherein the timing controller generates the initial POL signal using the input voltage from the system, wherein the input voltage from the system is supplied directly to the timing controller, wherein the timing controller realigns digital video data input from the system through the interface circuit; a signal stabilizer to receive the initial POL signal from the timing controller and a constant voltage from a source, and to generate a stabilized POL signal using the received constant voltage and the received initial POL signal, wherein the source that supplies the constant voltage is a DC-to-DC converter; a common voltage generator to generate a common voltage signal using the stabilized POL signal and to supply the generated common voltage signal to an LCD panel; a gate driver to generate scan pulses using the high gate voltage and the low gate voltage, and to supply the scan pulses to gate lines of the LCD panel; and a data driver to convert the digital video data input from the timing controller to analog gamma voltages corresponding to a gray level; wherein the interface circuit, the timing controller, the signal stabilizer, the source, the common voltage generator, the gate driver and the data driver are provided with the input voltage from the power source of the system; wherein the DC-to-DC converter boosts or decompresses the input voltage from the power source of the system to generate the reference voltage, the high gate voltage and the low gate voltage; wherein the signal stabilizer includes: a first switching device having a base terminal to which the initial POL signal input, a collector terminal to which the constant voltage is input, and an emitter terminal connected to a ground terminal; a second switching device having a base terminal connected to the collector terminal of the first switching device, a collector terminal to which the constant voltage is input, and an emitter terminal connected to the ground terminal; wherein the collector terminal of the second switching device is connected to the common voltage generator so as to provide the stabilized POL signal to the common voltage generator; wherein the common voltage generator includes: an inversion amplifier to invert and amplify a differential voltage between the stabilized POL signal input to its inversion terminal and an offset voltage input to its non-inversion terminal; a buffer to buffer a voltage output from the inversion amplifier depending on a level of the voltage output from the inversion amplifier and feeding an output voltage of the buffer back to the inversion amplifier to amplify the output voltage of the buffer; a noise attenuator having a capacitor connected between an output terminal of the inversion amplifier and the inversion terminal, and a resistor connected between the output terminal of the inversion amplifier and an input terminal of the buffer; and wherein the initial POL signal output from the timing controller is not constant and varies depending on the input voltage.