Patent ID: 6345374
Filing Date: 2002-02-05
Classification: G11B

Abstract:
A code error correcting apparatus comprising:a digital processor for performing a predetermined process on digital data and generating an identification signal synchronized with the output timing of the digital data; a latch circuit connected to said digital processor, for latching a plurality of processed digital data in accordance with the identification signal; an input interface circuit connected to said latch circuit and an external memory circuit, for receiving the plurality of processed digital data from said latch circuit and storing the plurality of digital data in the external memory circuit; a code error correcting circuit connected to the external memory circuit, for receiving the plurality of processed digital data from the external memory circuit, performing a code error correction process on the plurality of digital data, and overwriting the corrected data into the external memory circuit; and an output interface circuit connected to the external memory circuit, for reading the plurality of corrected processed digital data from the external memory circuit, wherein said digital processor, said latch circuit, said input interface circuit and said code error correcting circuit are integrated on a single semiconductor substrate.