Patent ID: 7736978
Filing Date: 2010-06-15
Classification: H01L

Abstract:
1. A method of manufacturing a trench transistor comprising: forming a plurality of trenches defined by a corresponding plurality of semiconductor mesas, a height of the plurality of mesas defining a depth of the plurality of trenches, the mesas having dopants of the first conductivity type; lining each of the plurality of trenches with a thin layer of gate dielectric material; substantially filling each dielectric-lined trench with conductive material to form a gate electrode of the transistor; forming a doped well in the plurality of mesas to a depth that is less than the depth of the plurality of trenches, the doped well having dopants of a second conductivity type opposite to said first conductivity type; forming a source region inside the doped well and extending to a depth that is less than the depth of the well, the source region having dopants of the first conductivity type; forming a heavy body structure inside the doped well, the heavy body structure including a region having dopants of the second conductivity type with a peak concentration occurring at a peak concentration depth below the depth of the source region and above the depth of the doped well; forming a contact area on the surface of the plurality of mesas; wherein forming a plurality of trenches comprises patterning and etching the plurality of trenches that extend in parallel along a longitudinal axis; and wherein the step of forming the contact area comprises forming a ladder-shaped source contact region surrounding heavy body contact regions.