Patent ID: 6088261
Filing Date: 2000-07-11
Classification: G06F,G11C

Abstract:
A semiconductor memory comprising a plurality of memory cells having a charge storage layer, a gate electrode, and a source/drain to change a charge storage state step by step in said charge storage layer by applying a predetermined voltage to at least said gate electrode and said source/drain, identification numbers defined in a one-to-one correspondence with the storage states being written and read out by checking a charge storage state in said charge storage layer, comprising:encoding means for converting input data sequences into at least alternate predetermined ones of identification numbers more than a possible number of data sequences;storage means having said memory cells arranged in a matrix manner to store the identification numbers in corresponding memory cells; anddecoding means for detecting an identification number stored in a selected predetermined memory cell, reading out the identification number from said memory cell by performing error correction, if an error occurs in the identification number, assuming that the error has occurred due to a first transition from an upper state in which electric charge is stored in said charge storage layer to a lower state in which electric charge is emitted therefrom by using a property that a probability of a second transition from the lower state in which electric charge is emitted from said charge storage layer to the upper state in which electric charge is stored therein is negligibly small compared to a probability of the first transition, decoding the identification number into the data sequence on the basis of the conversion, and outputting the data sequence.