Patent ID: 6185122
Filing Date: 2001-02-06
Classification: G11C,H01L

Abstract:
A memory array comprising:a first plurality of spaced-apart, parallel, substantially coplanar conductors;a second plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors, said first and second conductors being generally orthogonal to one another; anda plurality of first memory cells each comprising a first steering element in contact with a first state change element, each cell directly disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors, the first steering elements being in contact with the second conductors;a third plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors, the third conductors running in the same direction as the first conductors;a plurality of second memory cells each comprising a second steering element in contact with a second state change element, each cell directly disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors, the second steering elements being in contact with the second conductors.