Patent ID: 7514749
Filing Date: 2009-04-07
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device having, over one and same semiconductor substrate: a first MISFET of a first breakdown voltage formed in a first region; and a second MISFET of a second breakdown voltage lower than the first breakdown voltage formed in a second region, the method comprising the steps of: (a) forming an element isolation region in a main surface of the semiconductor substrate; (b) introducing an impurity ion into the first region of the semiconductor substrate to form a first semiconductor region where a source and a drain of the first MISFET are formed; (c) forming a first gate insulating film over the main surface of the first region of the semiconductor substrate; (d) depositing a first conductive film over the first gate insulating film and patterning the first conductive film to form a first gate electrode of the first MISFET in the first region; (e) after the step (d), forming a second gate insulating film over the main surface of the second region of the semiconductor substrate; (f) depositing a second conductive film over the second gate insulating film and patterning the second conductive film to form a second gate electrode of the second MISFET in the second region; and (g) introducing an impurity ion into the second region of the semiconductor substrate to form a third semiconductor region serving as a source and a drain of the second MISFET,