Patent ID: 6724026
Filing Date: 2004-04-20
Classification: G11C,H01L

Abstract:
An integrated circuit comprising:at least one memory cell pair having first and second memory cells arranged in a memory group, a memory cell includes a cell transistor having first and second diffusion regions and a cell capacitor having a dielectric layer between first and second electrodes, wherein the cell transistors of the memory cell pair share a common second diffusion region; a first bottom electrode plug coupling the first electrode of first memory cell capacitor to the common second diffusion region; a second bottom electrode plug coupling the first electrode of the second memory cell capacitor to the common second diffusion region; and the second electrode of the first memory cell capacitor is coupled to the first diffusion region of the first memory cell transistor and the second electrode of the second memory cell capacitor is coupled to the first diffusion region of the second cell transistor.