Patent ID: 9160312
Filing Date: 2015-10-13
Classification: G11C,H03K

Abstract:
1. A method for reducing leakage current in an integrated circuit comprising a plurality of sub-blocks of circuitry each including an upper power-supply terminal, a lower power-supply terminal, and an input or output signal terminal, the method comprising steps of: coupling the upper and lower power-supply terminals of the sub-blocks of the plurality of sub-blocks to couple the sub-blocks in parallel between upper and lower active-mode power supplies when the integrated circuit is operating in an active mode; coupling the upper and lower power-supply terminals of two or more sub-blocks of the plurality of sub-blocks to couple the two or more sub-blocks in series between upper and lower standby-mode power supplies when the integrated circuit is operating in a standby mode; and activating isolation circuitry within one of the two or more sub-blocks to isolate circuitry of the one sub-block from the input or output signal terminal of the one sub-block when the integrated circuit is operating in the standby mode.