Patent ID: 6518630
Filing Date: 2003-02-11
Classification: G02F,H01L

Abstract:
A thin film transistor array substrate, comprising:a substrate; a gate wire formed on the substrate, the gate wire comprising a gate line and a gate electrode; a gate insulating layer covering the gate wire; a semiconductor pattern formed on the gate insulating layer; a data wire formed on the gate insulating layer and the semiconductor pattern and comprising a data line, a source electrode and a drain electrode, the data wire having a multiple-layered structure comprising a first metallic layer and an intermetallic compound layer; a protective layer formed on the data wire and the semiconductor pattern, the protective layer having a first contact hole exposing the drain electrode; and a pixel electrode contacting the drain electrode through the first contact hole, wherein the pixel electrode is in direct contact with the intermetallic compound layer in the first contact hole.