Patent ID: 6362087
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method for fabricating a microelectronic fabrication comprising:providing a substrate; forming over the substrate a patterned bond pad layer; forming over the substrate and in electrical communication with the patterned bond pad layer a first barrier layer; and forming over the first barrier layer on top of the patterned bond pad layer a patterned redistribution layer; forming over the patterned redistribution layer a second barrier layer; forming over the second barrier layer and in electrical communication with the patterned redistribution layer a patterned terminal electrode layer, wherein at least one of the first barrier layer and the second barrier layer is formed of tri-layer stack comprising: a first titanium-tungsten alloy layer; a titanium-tungsten alloy nitride layer formed upon the first titanium-tungsten alloy layer; and a second titanium-tungsten alloy layer formed upon the titanium-tungsten alloy nitride layer.