Patent ID: 8949514
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. An integrated circuit device comprising: a stack processor comprising a processor core and an interrupt controller; and a ferroelectric random access memory coupled to said processor core for storing associated program code and data, wherein the stack processor further comprises a data stack including a top portion comprising first volatile memory in the processor core and a bottom portion comprising a first portion of the ferroelectric random access memory, and a return stack including a top portion comprising second volatile memory in the processor core and a bottom portion comprising a second portion of the ferroelectric random access memory, wherein the stack processor is configured to transfer data between the data and return stacks in response to a stack-based computer programming language comprising 64 possible instructions based upon a 16 bit word, and wherein each of said instructions in said 16 bit word comprises 3 five bit instructions and a 16th bit applicable to each of said 3 five bit instructions.