Patent ID: 7454593
Filing Date: 2008-11-18
Classification: G06F

Abstract:
1. A parallel processor comprising: a plurality of row buses divided into a plurality of segments; an array of processing elements arranged in rows and columns, each of the processing elements including a column enable input and a row enable input, each of the processing elements being enabled responsive to receiving a column activation signal at its column enable input and a row activation signal at its row enable input, each of the processing elements being coupled to each adjacent processing element through a respective segment of a respective one of the row buses and being operable to load the digital signals from the row bus segment to which it is coupled responsive to being enabled by receiving a column activation signal at its column enable input and a row activation signal at its row enable input, each of the processing elements being further operable when the processing element is enabled to couple digital signals to each adjacent processing element through a respective segment of the row bus to which it coupled; a respective column select line connected to the column enable inputs of the processing elements in each column; a respective row select line connected to the row enable inputs of the processing elements in each row; a respective column edge register for each row of processing elements in the array of processing elements, each of the column edge registers being coupled through a respective segment of one of the row buses to the processing element at one end of the respective row and to the processing element at the other end of the respective row, each of the column edge registers being operable to couple digital signals between the processing element at the one end of the respective row through the row bus segment to which it is coupled and the processing element at the other end of the respective row; and interconnection logic included in each of the processing elements, the interconnection logic being operable when the processing element is enabled to apply to one of the segments of the row bus to which it coupled digital signals corresponding to a value that it is a logical combination of the value corresponding to digital signals applied to another of the segments of the row bus by the column edge register for that row and a value generated by the processing element, and wherein the interconnection logic is operable apply the digital signals corresponding to the logical combination value to the segment of the row bus upon receiving the digital signals coupled to the row bus segment by the column edge register.