Patent ID: 6385738
Filing Date: 2002-05-07
Classification: H04L

Abstract:
A system for testing a networking device comprising:a phase-locked loop (PLL) for generating a transmit clock signal in response to a basic clock signal; a reset extension circuit for latching the basic clock signal and the transmit clock signal when the PLL stabilizes, and for generating a secondary reset signal; a physical layer (PHY) device generating encoded signals that represent a known valid bit pattern, wherein an initial polarity state of the encoded signals is based upon the secondary reset signal; and a signal analyzer circuit for checking whether a transmitted bit pattern associated with the generated encoded signals matches the known valid bit pattern by decoding the encoded signals and comparing the transmitted bit pattern with the known valid bit pattern, a match between the transmitted bit pattern and the known valid bit pattern indicating operation of the PHY device in accordance with a prescribed operation.