Patent ID: 6101624
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A method for detecting and correcting anomalies in a field-programmable gate array (FPGA), said FPGA having a memory for storing a word-organized directed graph of networked logic functions; a configurable chip including logic functions, paths, and connection elements; and an arrangement coupling the memory and the chip for programming the connection elements to constitute a physically realizable image of the directed graph, the method comprising the steps of:(a) forming parity images of groups of words of the graph in the memory and storing said parity images in a failure-independent part of the same or other memory;(b) accessing a set of words from the memory, calculating an ECC residue, and comparing the ECC residue with an ECC signature previously derived from an error-free copy of the same set of words;(c) in the event of a comparison match, either repeating steps (b)-(d) over another set of words or terminating the test; and(d) in the event of a comparison mismatch, invoking a step selected from a set of steps consisting of (1) notification only of error, (2) error notification and immediate verification testing of counterpart logic chip functions, and (3) error notification, parity image correction of the words in error, reprogramming of the chip functions utilizing the corrected graph, and verification testing of the counterpart logic chip functions.