Patent ID: 8600724
Filing Date: 2013-12-03
Classification: G06F

Abstract:
1. A method of verifying a processor design using a processor simulation model in a simulation environment, wherein said processor simulation model comprises at least one execution unit for executing at least one instr uction of a test file, said method comprising: tracking, by operation of one or more computer processors, each execution of each of said at least one instruction by creating a monitor queue with a queue element for each instruction currently being executed, wherein each queue element holds instruction information including (i) an instruction identifier that identifies a type of a corresponding instruction and (ii) an execution cycle counter that holds a counter value indicating a number of execution cycles that the corresponding instruction has executed up to the current point in time; monitoring relevant signals in each execution cycle, wherein said relevant signals include an end of instruction signal; upon determining that said end of instruction signal is active, removing the oldest queue element from said monitor queue, and comparing the instruction information held by said oldest queue element against a set of trap elements included in a trap file; and upon determining that said oldest queue element matches a trap element in said set of trap elements, collecting the instruction information held by said oldest queue element in a monitor file by creating a monitor case comprising the instruction information held by said oldest queue element and a current test case of said test file, wherein said current test case comprises the instruction identifier held by said oldest queue element and corresponding input data.