Patent ID: 8316342
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. A method of concurrently generating a layout for an electronic circuit across a plurality of design entry tools, comprising: capturing, using one or more computing devices, a first plurality of first electronic components in a first design entry tool; capturing, using one or more computing devices, a second plurality of second electronic components in a second design entry tool; providing, using one or more computing devices, at least a first interface from the first plurality to the second plurality in the first design entry tool; populating, using one or more computing devices, the first interface through the second design entry tool; exporting, one or more computing devices, a first netlist representing a first interconnection of the first electronic components in the layout from the first design entry tool; exporting, using one or more computing devices, a second netlist representing a second interconnection of the second electronic components in the layout from the second design entry tool; and exporting, one or more computing devices, a third netlist representing the first interface from the first plurality to the second plurality from the first design entry tool, wherein the third netlist stitches the first netlist to the second netlist.