Patent ID: 6456548
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A semiconductor storage device, comprising:a plurality of current-to-voltage (I-V) converter circuits, each I-V converter circuit being coupled to at least one digit line and providing an output voltage according to a current flowing in the digit line, the current varying according to a value stored in a selected memory cell; a reference voltage generating circuit that provides a reference voltage according to a current flowing in a reference digit line; a plurality of latch-type sense amplifiers, each latch-type sense amplifier comprising a first sense amplifier (SA) input coupled to at least one I-V converter circuit; a second SA input coupled to the reference voltage generating circuit; a latch that is controlled according to a control signal and includes a first latch input and a second latch input; a first transfer switch coupled between the first SA input and first latch input that includes a first transistor that receives the control signal at a first control terminal and a second transistor that receives a complementary control signal at a second control terminal; and a second transfer switch coupled between the second SA input and second latch input that includes a third transistor that receives the control signal at a third control terminal.