Patent ID: 9054084
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. An integrated circuit comprising: a first I/O cell having: a second I/O cell on a first side of the first I/O cell, the second I/O cell having: a third I/O cell on a second side of the first I/O cell, the second side opposite the first side, the third I/O cell having: wherein the first recess is sized to receive a portion of the second bond pad including two directly adjacent sequential corners of the second bond pad; wherein the first matching recess is sized to receive a portion of the third bond pad including two directly adjacent sequential corners of the third bond pad; wherein the second matching recess and the third matching recess are sized together to receive the first bond pad; wherein the first bond pad and the second bond pad have a first horizontal overlap of at least about 5%; and wherein the first bond pad and the third bond pad have a second horizontal overlap of at least about 5%.