Patent ID: 8236681
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor integrated circuit device comprising the steps of: (a) carrying out first dry etching to form, toward a lower-level buried interconnect disposed in an insulating film over the device surface of a wafer, a via hole that extends from the upper surface of the insulating film to the upper surface of an etch stop film over the lower-level buried interconnect which is to be coupled to an upper-level buried interconnect; (b) after the step (a), carrying out, in an etching chamber, second dry etching to extend the via hole to the upper surface of the lower-level buried interconnect while the back surface of the wafer is retained on a wafer stage associated with an electrostatic chuck; (c) after the step (b), subjecting, in the etching chamber, the device surface of the wafer to gas phase plasma treatment in an atmosphere having nitrogen as a main component while the back surface of the wafer is retained on the wafer stage; and (d) after the step (c), removing electrostatic charge from the wafer by using gas phase plasma in an atmosphere having argon as a main component while the back surface of the wafer is retained on the wafer stage.