Patent ID: 7082072
Filing Date: 2006-07-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a pair of memory sub arrays, which share a sense amplifier, each of which has a plurality of memory cells arranged in a matrix, each of columns of the matrix being connected to a pair of bit lines, and each of rows of the matrix being connected to a word line; and a control signal generating circuit which sequentially outputs first and second refresh start signals within an operation time period corresponding to an external refresh command in response to an internal refresh command, wherein a first refreshing operation is carried out to first memory cells connected to a first word line of one of said memory sub arrays in response to said first refresh start signal and a second refreshing operation is carried out to second memory cells connected to a second word line different from said first word line in said memory sub array in response to said second refresh start signal.