Patent ID: 7589997
Filing Date: 2009-09-15
Classification: G06F,G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a memory cell array including a plurality of memory cells that are connected to word lines extending in a row direction and bit lines extending in a column direction, store x-bit information corresponding to 2 a row decoder that is connected to said word lines and supplies a voltage to said word lines to make said memory cells operate; a sense amplifier device that is connected to said bit lines, reads data stored in said memory cells and retains the read data and data written to said memory cells; a code word generating circuit that creates an ECC frame composed of input information data and redundant data to be stored in said memory cells based on said information data; and an error correcting circuit that corrects said information data based on said information data and said redundant data of said ECC frame, wherein data contained in said ECC frame is allocated as a first data group to be stored in a first memory cell group composed of a plurality of first memory cells selected by a first word line and a second data group to be stored in a second memory cell group composed of a plurality of second memory cells selected by a second word line.