Patent ID: 9148270
Filing Date: 2015-09-29
Classification: G06F,H04L

Abstract:
1. A method performed by a processing system that comprises at least one interchip interface module, the method comprising: assigning a first priority to a first-type communication channel in a first time slice of a set of multiple time slices based at least in part upon a criterion, the set of multiple time slices comprising the first time slice and a second time slice; identifying a contiguous memory area in a memory element in the interchip interface module; storing a first data item from the first-type communication channel into the contiguous memory area in response to the first priority being assigned to the first-type communication channel; identifying communication channels of one or more types other than the first-type comprising one or more data items that fit a remaining portion of the memory element; arbitrating among the communication channels of one or more types other than the first-type in the second time slice; and in response to the arbitrating, storing a second data item from one of the communication channels of one or more types other than the first-type in the memory element in the interchip interface module.