Patent ID: 6418058
Filing Date: 2002-07-09
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array having a matrix arrangement of electrically rewritable memory cells which form a plurality of memory cell units each including a plurality of said memory cells; a decoder to decode an address and to select a memory cell of said memory cell array; a sense amplifier to detect read-out data from said memory cell array and to latch write data to said memory cell array; a read-out controller to read out data from a memory cell selected from a memory cell unit selected by said decoder; a write controller to write data in a memory cell selected from a memory cell unit selected by said decoder by applying a write voltage thereto; and a write verify read-out controller to read out data from a selected memory cell in order to confirm the status of data writing by said write controller, under a bias condition ensuring that a cell current flowing in said memory cell unit which is made conductive upon read-out operation for judging whether predetermined data was written in one of memory cell forming said memory cell unit becomes larger than the current flowing in said memory cell unit which is made conductive upon read-out operation for specifying data written in said memory cell.