Patent ID: 7158433
Filing Date: 2007-01-02
Classification: G11C

Abstract:
1. A semiconductor storage device having a memory cell array in which a plurality of memory cells is provided at intersections of a plurality of bit lines and a plurality of word lines and executing refreshing for holding data, comprising: memory cells for pairing provided on said memory cell array, for compensating for errors of each memory cell; a control circuit for checking a data holding ability of each of memory cells under test in a predetermined period after power-on; a storage circuit for storing information which specifies said memory cells under test for which it is determined that said data holding ability is low in the checking of said control circuit; and a selecting-line activating circuit for activating a selecting line for pairing corresponding to said memory cells for pairing based on a result of comparing a specific address to be input with the information stored in said storage circuit.