Patent ID: 6621760
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A method comprising:generating a write strobe signal to latch output data into a memory unit comprising one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices, the write strobe signal having an edge transition at approximately the center of a data window corresponding to the output data; delaying a first receive clock signal by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal, the first delayed receive clock signal being used to latch incoming data from the memory unit; and aligning the edge transition of the write strobe signal and the data window corresponding to the output data such that the edge transition of the write strobe signal approximately corresponds to the center of the data window, wherein aligning comprises: driving the output data in response to the rising edge transitions of a first and a second clock signal, respectively, the first and second clock signals being phase shifted by one half of a clock period corresponding to the frequency of the first and second clock signals; and driving the write strobe signal in response to the rising edge transitions of a third and a fourth clock signal, respectively, the third and fourth clock signals being phase shifted by one half of the clock period, the output data and the write strobe signal having approximately the same clock to output time.