Patent ID: 9183916
Filing Date: 2015-11-10
Classification: G11C,H01L

Abstract:
1. A non-volatile memory cell array comprising: a plurality of substantially parallel bit lines; and a plurality of substantially parallel word lines, wherein the word lines are oriented substantially orthogonally in relation to the bit lines, wherein the word lines span the bit lines at a plurality of cross-points, wherein each cross-point in the plurality of cross-points establishes a memory cell, wherein each memory cell is configured to transition from an open-circuit state to a diode state in response to a first voltage pulse with a first polarity applied across its corresponding cross-point, wherein each memory cell is configured to transition from the diode state to the open-circuit state in response to a second voltage pulse with a second polarity opposite to the first polarity applied across its corresponding cross-point, wherein there is no physical contact between the word line and the bit line at the cross-point defining a memory cell when the memory cell is in the open-circuit state, wherein there is physical contact between the word line and the bit line at the cross-point defining a memory cell when the memory cell is in the diode state, and wherein a current rectifying effect is exhibited in the diode state.