Patent ID: 6567876
Filing Date: 2003-05-20
Classification: G06F,Y02D

Abstract:
A computer system, comprising:a processor; a memory array coupled to said processor; a primary expansion bus coupled to said processor and said memory array; and a bus bridge coupled to said expansion bus, said bus bridge comprising: a primary bus interface that transmits and receives data over said primary expansion bus; and a secondary bus interface coupled to said primary bus interface and configured to transmit and receive data over a hot pluggable secondary expansion bus, wherein said bus bridge captures the values of signals on said primary expansion bus and transmits the captured bus values through said secondary bus interface; wherein said bus bridge receives primary expansion bus values through said secondary bus interface and drives said primary expansion bus with the received bus values; wherein said secondary expansion bus comprises a serial bus; said computer system also including a peripheral device coupled to said expansion bus and a sideband signal coupling said peripheral device to said bus bridge, wherein said bus bridge captures the value of the sideband signal and transmits the captured sideband value through said serial bus; wherein said bus bridge also receives a sideband value through said serial bus interface and drives the sideband signal with the received sideband value; and wherein said bus bridge includes a packetizer coupled to said primary and secondary bus interfaces, wherein said packetizer creates outgoing data packets that carry captured signals transmitted through said serial bus interface.