Patent ID: 7855111
Filing Date: 2010-12-21
Classification: H01L

Abstract:
1. A method for forming an integrated circuit substrate, comprising the steps of: providing a single crystal substrate wafer, comprised of silicon with a first crystal lattice orientation; forming a directly bonded silicon (DSB) layer with a second crystal lattice orientation on a top surface of said substrate wafer; forming an amorphization photoresist pattern on a top surface of said DSB layer which exposes the top surface of said DSB layer in a region defined for recrystallization to said first crystal lattice orientation; performing a first amorphization ion implant process whereby a first amorphous layer is formed in said DSB layer and said substrate wafer in said region defined for recrystallization to said first crystal lattice orientation, with a depth greater than a thickness of said DSB layer; performing a second amorphization ion implant process whereby a second amorphous layer is formed in said DSB layer in said region defined for recrystallization to said first crystal lattice orientation, with a depth between one-half and one-fourth of said depth of said first amorphous layer; forming a low temperature silicon dioxide layer on a top surface of said DSB layer and said region defined for recrystallization to said first crystal lattice orientation; performing a solid phase epitaxy (SPE) process in which said first amorphous layer and said second amorphous layer are recrystallized to said first crystal lattice orientation, thereby forming an SPE layer; performing an anneal process in which defects at an interface between said SPE layer and said DSB layer are reduced; forming a sacrificial layer of silicon dioxide on the top surface of said DSB layer and a top surface of said SPE layer; and forming a region of field oxide at an interface between said SPE layer and said DSB layer.