Patent ID: 7160786
Filing Date: 2007-01-09
Classification: H01L

Abstract:
1. A layout method of a semiconductor device on a silicon on insulator substrate having a semiconductor substrate and an active layer insulated from the semiconductor substrate by a buried oxide layer, the method comprising: separating the active layer into a plurality of active regions by a field isolation film having a thickness such that a bottom of the field isolation film reaches an upper surface of the buried oxide film; placing one or more first doped regions in first one or more of the plurality of active regions; placing an antenna wire in an antenna wiring layer electrically connected to the one or more first doped regions directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer; and when a ratio of a total area of the antenna wire to a total area of the one or more first doped regions exceeds a predetermined value, performing at least one of: adding a dummy doped region in a second one of the plurality of active regions, the dummy doped region being electrically connected to the one or more first doped regions through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer; adding a junction diode formed in a surface of the semiconductor substrate, the junction diode being electrically connected to the one or more first doped regions through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer; dividing the antenna wire into two parts and electrically connecting the two parts through a third connecting wire in an upper wiring layer above the antenna wiring layer; and dividing one of the antenna wire and the at least one first connecting wire into two parts, and inserting a buffer between the two parts.