Patent ID: 9224666
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A circuit arrangement comprising: a substrate, a connecting element and a chip, wherein the substrate provides on its surface at least a partial metallization, wherein the connecting element is applied to the metallization, wherein the chip is applied to the connecting element, wherein the connecting element provides an electrically non-conductive glass layer which is applied to the metallization, wherein the glass layer extends completely between the chip and the substrate; wherein an adhesive layer is applied between the chip and the glass layer, wherein the metallization extends between the glass layer and the substrate so that the glass layer can be applied to the metallization, wherein a through connection connects the metallization on an upper side of the substrate to a lower side of the substrate in an area of the connecting element, wherein the glass layer is substantially adapted to a surface of the metallization, and a thickness of the glass layer is configured to electrically insulate the chip from the metallization while minimizing a thermal resistance between the chip and the metallization, wherein the metallization is applied to the substrate by a thick-layer process, wherein the metallization provides a maximum surface roughness in a range of 1 μm to 5 μm, and wherein the glass layer provides a maximum average thickness in a range of 5 μm to 12 μm.