Patent ID: 7715266
Filing Date: 2010-05-11
Classification: G11C

Abstract:
1. A memory detecting circuit, comprising: a first switch element comprising: a second switch element comprising: a third switch element comprising: a fourth switch element comprising: a fifth switch element comprising: a first indication device connected to the second end of the second switch element; and a second indication device connected to the second end of the fourth switch element; wherein upon the condition that memories are only installed into the memory sockets of the first channel, the first memory detecting signal is at a low voltage level, and the second memory detecting signal is at a high voltage level, thereby the first switch element and the second switch element are turned off, the third switch element and the fourth switch element are turned on, and the fifth switch element is turned off, so that the first indication device indicates the memories run in a single channel mode; wherein upon the condition that the memories are only installed into the memory sockets of the second channel, the first memory detecting signal is at a high voltage level, and the second memory detecting signal is at a low voltage level, thereby the first switch element and the second switch element are turned on, the third switch element and the fourth switch element are turned off, and the fifth switch element is turned off, so that the first indication device indicates the memories run in the single channel mode; and wherein upon the condition that the memories are installed into the memory sockets of the first and the second channels respectively, the first and second memory detecting signals are both at a low voltage level, thereby the first switch element, the second switch element, the third switch element and the fourth switch element are turned off, and the fifth switch element are turned on, so that the second indication device indicates the memories run in a dual channel mode.