Patent ID: 8762614
Filing Date: 2014-06-24
Classification: G06F,H03M

Abstract:
1. An apparatus for analog-to-digital conversion with early interrupt capability, comprising: a digital processor and a memory coupled to the digital processor; an interrupt controller coupled to the digital processor, wherein the interrupt controller is adapted to handle interrupts to the digital processor based upon information from a selected analog channel; an analog-to-digital converter (ADC) having a plurality of pipelined stages for converting a sampled analog signal from the selected analog channel to a digital representation thereof; a plurality of pipelined registers arranged to transfer the information from the selected analog channel from one register to a next register at each clock pulse thereto, wherein transfer time through each of the plurality of pipelined registers is substantially the same as delay time through each of the plurality of pipelined stages of the ADC; and a circuit for selecting a one of the plurality of pipelined registers, wherein a conversion ready delay time of the information from the selected analog channel is equal to the delay time at the selected one of the plurality of pipelined registers, whereby the information from the selected analog channel is available to the interrupt controller after the conversion ready delay time.