Patent ID: 6122316
Filing Date: 2000-09-19
Classification: H04N

Abstract:
A system for decoding an encoded data bitstream, comprising:a first core, comprising a video bitstream data processor having a rotating shift register decoder and a discrete cosine transfer computing device; anda second core, comprising a multistage inverse discrete cosine transform unit and a motion compensator;wherein said first core has the ability to operate on a first predetermined set of macroblock data while said second core simultaneously operates on a second predetermined set of macroblock data;wherein said rotating shift registered decoder comprises:a floating point register arrangement for receiving and loading therein at least one fixed length data word;a size determiner for determining a size of variable length data objects;a tracking element for computing a total number of used bits based on each variable length data object size;and wherein:said variable length data object is transferred from at least one register in said floating point register arrangement to a rotating register; andany empty registers in said floating point register arrangement are refilled with an additional fixed length data word.