Patent ID: 7767476
Filing Date: 2010-08-03
Classification: G02F,H01L

Abstract:
1. A manufacturing method of an array substrate, comprising the steps of: forming, within each pixel, at least a gate bus of a thin film transistor and a plurality of structures, the gate bus and the structures being formed from a metal film formed on the substrate, and the structures being arranged in an irregular pattern; forming an under layer on the substrate over the thin film transistor and over the plurality of structures to form irregularities, controlled by the plurality of structures, on a surface of the under layer; forming on the under layer a thin film with irregularities profiling the surface of the under layer; forming a resist layer on the thin film; forming a regularly arranged resist pattern by patterning the resist layer; performing an optical inspection of the resist layer to optically detect a defect in the resist pattern; and etching the thin film while using the resist pattern as a mask; wherein the resist pattern is formed without openings within each pixel so that the irregularities of the thin film are not recognized through the resist pattern in the optical inspection.