Patent ID: 9057921
Filing Date: 2015-06-16
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel, comprising: a first substrate; a gate line and a data line on the first substrate; a storage electrode line on the first substrate, wherein a constant voltage is applied thereto; a first thin film transistor which is connected to the gate line and the data line, and comprises a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor which is connected to the gate line and the data line, and comprises a second gate electrode, a second source electrode and a second drain electrode; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line, and comprises a third gate electrode, a third source electrode and a third drain electrode; an extension electrode which extends from the third gate electrode and overlaps the first drain electrode; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor, wherein the third source electrode of the third thin film transistor is directly connected to the second drain electrode of the second thin film transistor.