Patent ID: 6569726
Filing Date: 2003-05-27
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:providing a substrate having a gate structure thereon, wherein the gate structure includes a gate oxide layer, a gate electrode over the gate oxide layer and a spacer on a sidewall of the gate electrode; forming source/drain regions in the substrate on each side of the gate structure; forming self-aligned silicide layers over the exposed gate electrode and the source/drain regions of the gate structure; forming a silicon nitride etching stop layer over the substrate; conducting a fluoride blanket implantation on the silicon nitride etching stop layer; forming a dielectric layer over the substrate; patterning the dielectric layer to form a borderless contact opening that exposes a portion of the silicon nitride etching stop layer; removing the exposed silicon nitride etching stop layer; forming a metallic layer over the substrate completely filling the borderless contact opening; conducting a chemical-mechanical polishing operation to remove excess metallic material outside the borderless contact opening.