Patent ID: 8637362
Filing Date: 2014-01-28
Classification: H01L

Abstract:
1. A method of fabricating a memory array comprising: forming a pillar extending generally upward from an upper surface of a semiconductive substrate and generally aligned atop a corresponding data/bit line; forming a source region generally at a lower portion of the pillar so as to be in electrical communication with the corresponding data/bit line; forming a drain region generally at an upper portion of the pillar, wherein the pillar intermediate the source and drain regions is substantially fully depleted; forming a gate structure substantially about the pillar in lateral directions, the pillar, the source region, the drain region, and the gate structure comprising an access transistor, the access transistor being substantially off with no applied gate potential; and forming at least one conductive word line extending generally transversely to the corresponding data/bit line and in electrical contact with the gate structure along at least a first surface thereof such that bias voltage applied to the conductive word line is communicated about the pillar via the gate structure.