Patent ID: 8243520
Filing Date: 2012-08-14
Classification: G11C

Abstract:
1. A method of operating an integrated circuit, the method comprising: applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed value; determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level; determining a change in a programming behavior of the plurality of non-volatile memory cells based on the fail count; adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality of non-volatile memory cells.