Patent ID: 6303974
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A semiconductor device comprising, in a housing:a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the housing; andelectrically conductive contact pin arrangements projecting from electrically insulated channels in the preformed sub-assembly, an inward end of each of said pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip, wherein:there is a sheet of electrically conductive material, resting in recesses on the inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of said pin arrangements;the emitter electrode has a first, outer planar face and an opposing, inner surface comprising pillars of material delineated by recesses formed on the inner surface of the emitter electrode, the walls of the pillars being substantially at right angles to the outer face of the emitter electrode and top faces of the pillars being coplanar and substantially parallel to the first, outer face; andsaid preformed sub-assembly includes a preform of electrically insulating material and contains apertures to accommodate the pillars so that it can be lowered thereover, the preform being of such height that, when finally assembled, it stands a little higher than the tops of the pillars and being also provided with a shallow recessed central area essentially level with the tops of the pillars.