Patent ID: 6476478
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A semiconductor chip package comprising:a die pad having opposed top and bottom surfaces; a semiconductor die mounted to the top surface of the die pad and having at least one bond pad disposed thereon; a plurality of leads projecting inwardly toward semiconductor die, each of the leads being of a lead thickness and having a body which defines opposed top and bottom surfaces and an inner end, at least one of the leads having a tab which projects from the body such that no portion of the tab extends beyond the bottom surface of the body; a package mold having a bottom surface and a cavity which is partially defined by an upper surface of a floor of the package mold, the floor having a floor thickness between the upper surface thereof and the bottom surface of the package mold which is substantially equal to the lead thickness; the package mold being formed such that portions of the top surfaces of the leads extending to the inner ends thereof are exposed within and substantially flush with the upper surface of the floor, the bottom surfaces of the leads are exposed within and substantially flush with the bottom surface of the package mold, and the tab is entirely encapsulated within the package mold.