Patent ID: 6218850
Filing Date: 2001-04-17
Classification: G01R,H05K

Abstract:
An apparatus provided for selecting high-reliability integrated circuits, said apparatus comprising:two pattern boards for providing testing signals for the tested integrated circuits and amplifying the testing signals;a main board for receiving said amplified testing signals from said pattern board, wherein the testing signals pass through electronic circuits in said main board;a signal board for receiving said amplified testing signals from said other pattern board, wherein the testing signals pass through electronic circuits in said signal board which can be removed from said apparatus;a plurality of daughter cards for receiving the signals from said main board and said signal board, wherein the testing signals pass through electronic circuits in said plurality of daughter cards which can be removed from said apparatus;a plurality of socket cards for receiving the signals from said plurality of daughter cards, wherein the signals are sent to the integrated circuits supported by sockets in said plurality of socket cards which can be removed from said apparatus;a feedthrough card for directing the testing signals from said pattern board to said main board, and other feedthrough card for directing the testing signals from said other pattern board to said signal board; anda plurality groups of needle conductors in rows, wherein some groups of said needle conductors in rows are used for signal transmission between two said pattern boards, some groups of said needle conductors in rows are used for signal transmission between said main board and said plurality of daughter cards, some groups of said needle conductors in rows are used for signal transmission between said signal board and said plurality of daughter cards, and some groups of said needle conductors in rows are used for signal transmission between said plurality of daughter cards and said plurality of socket cards.