Patent ID: 6723628
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising the steps of:(a) forming an interlayer dielectric layer over a substrate; (b) forming a wetting layer over and in direct contact with the interlayer dielectric layer; (c) forming at least a portion of a metal wiring layer over the wetting layer at a temperature of at least 350Â° C., and forming an alloy layer including a material comprising the wetting layer and a material comprising the metal wiring layer, wherein the alloy layer is formed between and in direct contact with both the wetting layer and the metal wiring layer, wherein the alloy layer is formed to have a thickness that is two to three times greater than that of the wetting layer; and (d) forming a bonding pad section by patterning a portion of the wetting layer and the metal wiring layer.