Patent ID: 6436590
Filing Date: 2002-08-20
Classification: G03F,G06F

Abstract:
A set of masks for defining a layer of material in an integrated circuit, said set of masks comprising:a first mask having phase shifting areas in an opaque field which define at least a first structure including a transistor gate having a larger gate dimension and a smaller gate dimension in said layer, the phase shifting areas including a first phase shift area and a second phase shift area having respective lengths and widths, where destructive interference occurs between said first phase shift area and said second phase shift area, and the first mask further includes an opaque material positioned along the lengths of, and between said first phase shift area and said second phase shift area affecting the smaller gate dimension, wherein said lengths substantially define the larger gate dimension with extensions to account for potential mask misalignment; and a second mask which defines other structure for said layer, and includes areas for preventing erasure of said first structure.