Patent ID: 7769798
Filing Date: 2010-08-03
Classification: H03M

Abstract:
1. An analog min-sum iterative decoder comprising: a plurality of standard CMOS variable nodes and a plurality of standard CMOS check nodes, the variable nodes and the check nodes being interconnected with a plurality of interconnections in accordance with a code to be decoded; wherein real-valued messages are passed on each interconnection between one of said variable nodes and one of said check nodes; wherein each standard CMOS check node comprises: a respective real to absolute and sign function for each input to the check node, the real to absolute and sign function producing a respective absolute value output and a respective sign output; for each input to the check node: a respective minimum WTA function connected to receive absolute value outputs of the real to absolute and sign functions other than the absolute value output respective the input, adapted to produce a minimum WTA output which is a minimum of the absolute value inputs; a respective XOR function connected to receive sign outputs of the real to absolute and sign functions other than the sign output respective the input, adapted to produce a sign output; an absolute and sign to real converter connected to receive the minimum WTA output and the sign output, adapted to produce a real valued output.