Patent ID: 7630273
Filing Date: 2009-12-08
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of memory cells arranged in rows and columns; a plurality of write word lines and a plurality of read word lines which are placed correspondingly to the respective rows of the plurality of memory cells; a plurality of write bit lines and a plurality of read bit lines which are placed correspondingly to the respective columns of the plurality of memory cells; a plurality of sense amplifiers provided correspondingly to the respective write bit lines to amplify potentials of the corresponding write bit lines; and a plurality of write-word-line drivers disposed correspondingly to the respective rows of the plurality of memory cells to drive the write word lines in the corresponding rows, wherein each of the memory cells includes a flip-flop having a pair of storage nodes for storing data, a write transistor connected to each of the corresponding write bit line and the corresponding write word line, and a read transistor connected to each of the corresponding read bit line and the corresponding read word line, during a write cycle, the selected write-word-line driver drives the corresponding write word line such that a potential of the corresponding write word line is lower in a first period as a predetermined period after an initiation of the write cycle than in a second period as a predetermined period after the first period, and the sense amplifiers amplify the potentials of the corresponding write bit lines in the first period.