Patent ID: 7483321
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A semiconductor memory device comprising: a memory cell array; a deserializer configured to generate a deserialized data by deserializing a first serialized data; a decoder configured to generate a first data, a command signal, an address signal and a first redundancy code by decoding the deserialized data; a redundancy code checker configured to generate a status signal by comparing the first data with the first redundancy code to detect an error in the first data; a control circuit configured to store the first data in the memory cell array or output a second data stored in the memory cell array in response to the command signal and the address signal; a redundancy code generator configured to generate a second redundancy code by using the second data; and a serializer configured to generate a second serialized data by serializing the second data and the second redundancy code.