Patent ID: 7945834
Filing Date: 2011-05-17
Classification: G01R

Abstract:
1. A testing circuit for the testing of an integrated circuit core or circuitry external to an integrated circuit core, the testing circuit comprising: a shift register circuit comprising a plurality of cells, for passing test signals, the cells being arranged as a plurality of banks of cells in series; a serial input and a serial output for connection to the input and output of the shift register circuit; a plurality of parallel inputs and outputs, wherein the parallel inputs are for passing test signals to the integrated circuit core for testing of the core, wherein a plurality of scan chain segments are defined, each between a parallel input and a respective parallel output, the scan chain segments each comprising a bank of cells of the shift register circuit, a core scan chain portion, a first bypass path around the core scan chain portion and a second bypass path around the bank of cells of the shift register circuit, wherein each scan chain segment further comprises a latching element in series with the bank of cells and the core scan chain portion.