Patent ID: 9195463
Filing Date: 2015-11-24
Classification: G06F

Abstract:
1. A method of prenormalizing denormal floating point values stored in a floating point register file in a processing core of the type including an issue unit and a floating point execution unit coupled to the floating point register file, wherein the issue unit is configured to issue instructions from an instruction stream to the floating point execution unit for execution thereby, the method comprising: speculatively scanning the floating point register file with background scavenging logic coupled to the floating point register file to identify a floating point register that stores a denormal floating point value, wherein speculatively scanning the floating point register file includes sequencing through each of a plurality of floating point registers in the floating point register file; wherein speculatively scanning the floating point register file is not performed specifically in response to any instruction in the instruction stream; in response to identifying the floating point register, issuing a first instruction to the floating point execution unit coupled to the floating point register file during a spare cycle of the floating point execution unit, wherein the first instruction is configured to normalize the denormal floating point value to generate a normal floating point value; storing the normal floating point value in a scratch register in response to execution of the first instruction by the floating point execution unit; and in response to a second instruction from the instruction stream that references the floating point register that stores the denormal floating point value, modifying the second instruction to reference the scratch register and issuing the modified second instruction to the floating point execution unit such that the modified second instruction uses the normal floating point value.