Patent ID: 6872589
Filing Date: 2005-03-29
Classification: H01L

Abstract:
1. A method of forming a chip level package, said method comprising: forming a thin film interconnect structure over a metal substrate having first and second opposing surfaces, the thin film interconnect structure comprising a first dielectric layer formed directly on the first surface of the metal substrate, a first metalization layer formed over the first dielectric layer, said first metalization layer including a first plurality bonding pads formed over a first region of the substrate and a plurality of signal lines formed over a second region of the substrate, a second dielectric layer formed over the first metalization layer and a second metalization layer including a second plurality of bonding pads, wherein the second plurality of bonding pads have a pitch that is greater than a pitch of the first plurality of bonding pads; forming an aperture between the first and second surfaces of the metal substrate in said first region opposite the first plurality of bonding pads; and positioning an integrated circuit die in the aperture and attaching the die to the first plurality of bonding pads.