Patent ID: 6473848
Filing Date: 2002-10-29
Classification: G06F

Abstract:
A method for controlling memory access on a machine with non-uniform memory access distributed over several modules, each module comprising one or more processors CPU for executing tasks on a virtual or physical addressing space by means of effective addresses generating logical page numbers to which it is possible to make physical page numbers correspond in the memory by means of a correlation table, the generation of a logical page number causing a task to have a first-level page-fault type exception when the logical page number is absent from the correlation table, comprisinga first step of activating, following each first-level page-fault type exception, a function (Trace), which records the value of an effective address that has generated the logical page number that has caused the exception, a date when the exception is caused, an identifier of the task using the effective address, an identifier of the processor executing the task, and a physical page number corresponding to the logical page number that has caused the exception; and wherein the activating of the function (Trace) is called from within the task having the exception and executed by the one or more processors.