Patent ID: 7312121
Filing Date: 2007-12-25
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, the method comprising: forming a first insulating layer covering a conductive pad contacting an impurity region of a semiconductor substrate; sequentially forming a first bit line conductive layer, an etch stopper layer, a second bit line conductive layer and a second insulating layer on the first insulating layer; patterning the first bit line conductive layer, the etch stopper layer, the second bit line conductive layer and the second insulating layer to form a first bit line conductive layer pattern, an etch stopper layer pattern, a second bit line conductive layer pattern and a second insulating layer pattern that expose a part of the first insulating layer; forming a third insulating layer covering the exposed surfaces of the first insulating layer, the second bit line conductive layer pattern and the second insulating layer pattern; removing a part of the third insulating layer and the second insulating layer pattern to expose an upper surface of the second bit line conductive layer pattern and an upper surface of the third insulating layer; sequentially removing the exposed portion of the third insulating layer and a part of the first insulating layer to expose a portion of the conductive pad; forming a first spacer layer on side walls of the second bit line conductive layer pattern, the etch stopper layer pattern, the first bit line conductive layer pattern and the first insulating layer; removing an upper portion of the second bit line conductive layer pattern until a portion of the etch stopper layer pattern is exposed and an upper portion of the first spacer layer is protruded; respectively forming an insulating layer pattern on the etch stopper layer pattern and a second spacer layer on a side wall of the first spacer; and forming a conductive plug, which is in contact with the conductive pad between the second spacer layers.