Patent ID: 9098653
Filing Date: 2015-08-04
Classification: G06F

Abstract:
1. A computer implemented method for verifying processor-sparing functions, the method comprising: executing, by one or more processors, a first simulation for a simulated processor core; blocking instruction dispatch; determining whether queues for the simulated processor core have drained; unblocking instruction dispatch to continue the first simulation in response to determining that the queues have not drained; in response to determining that the queues have drained, creating a simulation model dump during the execution of the first simulation, wherein the first simulation is stored, at least in part, in a computer-readable storage device; executing, by the one or more processors, a second simulation for the simulated processor core; creating a saved state of the simulated processor core during the second simulation; quieting the second simulation; replacing, by the one or more processors, a state of the simulated processor core according to a state saved in the simulation model dump; setting, by the one or more processors, the simulated processor core to execute processor-sparing code, wherein the processor-sparing code is configured to transfer a last good state of a failed processor core to a different processor core, wherein second simulation configures the simulated processor core as the different processor core; and resuming the second simulation.