Patent ID: 6182020
Filing Date: 2001-01-30
Classification: G06F

Abstract:
A method executing in a computer-aided logic design system for designing and testing logic circuitry prior to physical implementation, wherein the method verifies compliance of a logic design with a preselected set of design rules that specify logical relationships between electrical signals, wherein the logic design includes one or more electrical signals, wherein the logic design includes clock signal generation means for outputing a clock signal, wherein the clock signal generation means is coupled to one or more components having a clock signal input, the method comprising the following steps:providing a design rule to check whether more than one clock signal generation means is used in the logic design;providing a logic design file incorporating the initial logic design in computer-readable form;comparing at least portions of the initial design to the design rule; andproviding a user-discernable indication of any violation of the design rule by the initial logic design.