Patent ID: 6140170
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method for the manufacture of complementary integrated circuit devices comprising the steps of:(a) providing a silicon substrate, said silicon substrate having a surface and a backside, and a thickness T, as measured between said surface and said backside,(b) implanting n-type impurities into selected regions of the surface of said silicon substrate to form a plurality of n-wells, said n-wells having a quadrilateral shaped perimeter, and extending into said silicon substrate to depth d,(c) implanting p-type impurities into selected regions of a silicon substrate to form a plurality of p-wells, said p-wells having a quadrilateral shaped perimeter, and extending into said silicon substrate to depth d,(d) implanting an n+ contact into at least a portion of said perimeter of each of said n-wells, said n+ contact extending to a depth of approximately d,(e) implanting a p+ contact into at least a portion of said perimeter of each of said p-wells, said p+ contact extending to a depth of approximately d,(f) implanting an n+ impurity region into each n-well to a depth of less than 0.5 d,(g) implanting a p+ impurity region into each p-well to a depth of less than 0.5 d,(h) forming isolation regions around the perimeter of each of said n-wells and p-wells,(i) forming an oxide layer on the surface of said silicon substrate,(j) attaching the surface of said silicon substrate to a handle wafer, and(k) grinding the backside of said silicon substrate to a depth of at least T-d to expose said n-wells and p-wells.