Patent ID: 8958264
Filing Date: 2015-02-17
Classification: G11C,H03K

Abstract:
1. A semiconductor integrated circuit comprising: a first dynamic circuit for receiving a plurality of input signals and a first clock signal and controlling a level of a first dynamic node; a first transistor provided between a second dynamic node and a first power supply, for being conduction controlled in accordance with the level of the first dynamic node; a second transistor provided between the second dynamic node and the first power supply so as to be in series with the first transistor, for being conduction controlled in accordance with a second clock signal; and a second dynamic circuit for outputting an output signal having a logical value corresponding to a level of the second dynamic node; wherein when the plurality of input signals is in a first state, the first dynamic circuit keeps the first dynamic node at a first level where the first transistor is conducted, and yet, when the plurality of input signals is in a second state other than the first state, the first dynamic circuit switches the first dynamic node between the first level and a second level where the first transistor is non-conducted in accordance with the first clock signal; and wherein the second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.