Patent ID: 6519695
Filing Date: 2003-02-11
Classification: H04L

Abstract:
A computational engine comprises:a control unit that includes: memory arranged to store micro instructions relating to a computational algorithm, and an address unit operably coupled to receive an input relating to the computational algorithm from an external source, wherein the input causes at least some of the micro instructions to be retrieved from the memory; and a data path unit operably coupled to receive the at least some of the micro instructions and directly perform corresponding actions, the data unit includes: a pair of register files operably coupled in a double buffering manner such that one of the pair of register files is receiving parameters for a subsequent computation while another one of the pair of register files is used for a current computation; a plurality of floating point units, wherein at least one of the plurality of floating point units provide a specific action in response to at least one of the at least some of the data path control words; and data flow coupling operably coupled to the plurality of floating point units and the pair of register files, wherein the data flow coupling, in response to the at least some of the data path control words, provides coupling between at least one of the plurality of floating point units and at least one of the pair of register files.