Patent ID: 8970892
Filing Date: 2015-03-03
Classification: H04N

Abstract:
1. A memory control device, comprising: an address mapping unit configured to assign a main scanning address indicating a pixel position in a main scanning direction of a two-dimensional image in which pixels are arranged in the main scanning direction and in a sub-scanning direction which is perpendicular to the main scanning direction in a matrix form, and a sub-scanning address indicating the pixel position in the sub-scanning direction, to a column address, a row address and a bank address of an SDRAM; the address mapping unit assigning lower N bit(s) for indicating an address corresponding to a burst size of a burst transfer among the main scanning address, to lower bit(s) of the column address, and assigning predetermined number of bit(s) arranged successively to an upper bit side of the lower N bit(s) among the main scanning address, to the bank address; and an access executing unit configured to read or write one line of image data in the main scanning direction by carrying out the burst transfer successively multiple times in a multibank operation while the sub-scanning address is changed at an end of the burst transfer, wherein the N is a positive integer.