Patent ID: 6647456
Filing Date: 2003-11-11
Classification: G06F

Abstract:
A method, comprising:providing at least three parallel-coupled memory controller subsystems each capable of: queuing read commands and write commands to be sent to the memory in at least one read/write queue with an input coupled to a computer component and an output coupled to memory, queuing precharge commands to be sent to the memory in a precharge queue with an input coupled to the computer component and an output coupled to the memory, and queuing activate commands to be sent to the memory in an activate queue with an input coupled to the computer component and an output coupled to the memory, wherein the precharge commands and the activate commands are queued in parallel for reducing the latency and increasing bandwidth associated with accessing the memory; wherein a first one of the memory controller subsystems is coupled to a graphics unit computer component, a second one of the memory controller subsystems is coupled to a central processing computer component, and a third one of the memory controller subsystems is coupled to a display refresh module computer component.