Patent ID: 6472304
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A method for the manufacture of semiconductor integrated circuits comprising the sequential steps of:(a) forming a first conductive interconnection layer on a semiconductor substrate, (b) depositing a first dielectric layer on said first conductive interconnection layer, (c) forming at least one interlevel opening in said first dielectric layer to expose a portion of said first conductive interconnection layer, (d) depositing a first barrier layer on said first dielectric layer, and into said interlevel opening, (e) depositing a copper layer on said first barrier layer, said copper layer having a thickness sufficient to fill said interlevel opening, and being deposited by the steps of: 1. depositing a strike layer of copper on the first barrier layer, and 2. electrolytically depositing a copper layer on the strike layer, (f) planarizing the surface of the structure produced in step (e) using chemical mechanical polishing leaving a planar copper plug in a planar surface, (g) depositing a planar barrier layer on said planar surface and on said copper plug, (h) depositing a planar aluminum layer on said planar barrier layer, (i) forming a mask on the planar aluminum layer overlying the copper plug leaving portions of the planar aluminum layer exposed, (j) etching away the exposed portions of said planar aluminum layer and said planar barrier layer to leave a planar barrier layer pad and a planar aluminum layer pad on said copper plug, and (k) thermocompression bonding a conductive wire to said planar aluminum layer pad.