Patent ID: 7950144
Filing Date: 2011-05-31
Classification: H01L,Y10T

Abstract:
1. A method for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant, the method comprising: determining a number of build-up layers required for the integrated electronic panel assembly, wherein each build-up layer contributes an amount of concavity to the integrated electronic panel assembly; predicting a level of global convex warpage on the integrated electronic panel assembly provided by the presence of an embedded ground plane (EGP) alone within the integrated electronic panel assembly and in the absence of any build-up layers, wherein determining an amount of local convex warpage to be introduced into the integrated electronic panel assembly which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly, further for counteracting a total concavity introduced subsequently by processing of the determined build-up layers sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly, wherein