Patent ID: 6212542
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler, said method comprising:providing a multiscalar program including a plurality of threads that are each composed of a plurality of instructions of a selected instruction set architecture, each of said plurality of threads having a single entry point and a plurality of possible exit points, wherein one of said plurality of instructions forms said single entry point and others of said plurality of instructions form said plurality of possible exit points, said multiscalar program further including thread code descriptive of said plurality of threads, said thread code including a plurality of data structures that are each associated with a respective one of said plurality of threads and each specify possible exit points of the associated thread;supplying a third data structure among said plurality of data structures to said thread scheduler, said third data structure being associated with a third thread among said plurality of threads, wherein said third data structure associates a first data structure of a first thread among said plurality of threads with a first possible exit point of said third thread and associates a second data structure of a second thread among said plurality of threads with a second possible exit point of said third thread;assigning said third thread to a selected one of said plurality of processing elements for execution;after said supplying and prior to completing execution of said third thread, selecting, within said thread scheduler, from among said first and said second possible exit points of said third thread; andin response to said selection, loading a corresponding one of said first and second data structures into said thread scheduler for processing.