Patent ID: 7361537
Filing Date: 2008-04-22
Classification: H01L

Abstract:
1. A method of fabricating a recess channel trench comprising: ion-implanting a semiconductor substrate to form an impurity region; forming a polysilicon layer on the semiconductor substrate; selectively etching the polysilicon layer and the semiconductor substrate to form a trench that defines an active region; filling the trench with an insulating material, and planarizing the resultant structure to form a shallow trench isolation (STI) structure and an interlayer insulating layer; forming a mask layer on the polysilicon layer and the interlayer insulating layer, and selectively etching the mask layer, the polysilicon layer and the interlayer insulating layer, thereby forming an opening to define a contact pad; forming a spacer along a sidewall of the opening, and anisotropically etching the semiconductor substrate to form a recess channel trench, using the spacer and the mask layer as an etch mask; forming a gate insulating layer along an inner wall of the recess channel trench; forming a gate conductive layer on the gate insulating layer to fill the recess channel trench; and removing the selectively-etched mask layer to expose the polysilicon layer, and forming a capping layer on the gate conductive layer.