Patent ID: 6177318
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising:providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer; etching said siliconnitride layer to the dimension of said word gate;forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed;vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask;removing said block out mask;forming a insulator layer on said vertical sidewall;forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer, wherein the width of said spacer layer is the channel for said device;ion implanting a N type dopant into said substrate to form a device region therein;removing said disposable sidewall spacer layer;removing the exposed gate silicon oxide layer;forming a composite layer of silicon oxide, silicon nitride and silicon oxide over said vertical sidewall and device region; andforming said control gate sidewall spacer on said vertical sidewall and said composite layer.