Patent ID: 7782092
Filing Date: 2010-08-24
Classification: G01R

Abstract:
1. A test circuit, comprising: a plurality of pass gates; and a plurality of drive devices including a pull-up output and a pull-down output electrically isolated from each other, and wherein one of said outputs of said drive devices are connected to inputs of said pass gates and wherein other ones of said outputs are connected to outputs of said pass gates, whereby a delay through said pass gates can be determined for state changes caused by said one of said outputs of said drive devices substantially independent of pass gate delay for an opposite state change, wherein said pass gates are connected in a cascade configuration with each one of said drive devices interposed between each pair of said pass gates, wherein a predetermined one of said outputs of each of said drive devices is connected to an input of a next one of said pass gates and wherein another one of said output is connected to an output of said next pass gate, and wherein an output of a last one of said plurality of pass gates has an output coupled back to an input of a first one of pass gates, whereby said test circuit forms a ring oscillator having a frequency dependent on a delay through said plurality of pass gates.