Patent ID: 6895452
Filing Date: 2005-05-17
Classification: G06F,H04N

Abstract:
1. An execution architecture, the architecture comprising: a memory array, the array having first and second blocks, first and second I/O ports, first and second address ports, and a configuration control port, where a first value of a configuration control signal received at the configuration control port configures the first block to be coupled to the first I/O port and the first address port and the second block to be coupled to the second I/O port and the second address port, and a second value of the configuration control signal configures the first block to be coupled to the second I/O port and the second address port and the second block to be coupled to the first I/O port and the first address port; a data controller and address generator (DCAG) having an address output port and a control input port, the address output port of the DCAG being coupled to the first address port of the memory array and the DCAG being configured to generate address values at the DCAG address output port responsive to a vector data control signal received at the DCAG control input port; a DMA controller and address generator (DMACAG) having an address output port and a control input port, the address output port of the DMACAG being coupled to the second address port of the memory array and the DMACAG being configured to generate address values at the DMACAG address output port responsive to a DMA control signal received at the DMACAG control input port; a first execution unit having first and second I/O ports, the first I/O port of the first execution unit being coupled to the first I/O port of the memory array; a first local memory array having a first I/O port and a first address port, the first I/O port of the first local memory being coupled to the second I/O port of the first execution unit; and a first local address generator (LAG) having an address output port and a control input port, the address output port of the first LAG being coupled to the first address port of the first local memory array and the first LAG being configured to generate address values at the first LAG address output port responsive to a first execution control signal received at the first LAG control input port.