Patent ID: 8409948
Filing Date: 2013-04-02
Classification: H01L

Abstract:
1. A method of a forming transistors, comprising: forming a plurality of spaced-apart fins over a material, each of said fins comprising transistor pillars alternating with dielectric material pillars; the transistor pillars comprising semiconductor material; each of the transistor pillars having three segments; with said three segments being a bottom source/drain segment, a channel segment over the bottom source/drain segment, and a top source/drain segment over the channel segment; and forming electrically conductive gate material along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain segments of the transistor pillars; the oxide being an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature.