Patent ID: 6279130
Filing Date: 2001-08-21
Classification: G01R

Abstract:
Trigger delay compensation apparatus for use in a digital storage oscilloscope, comprising:a trigger circuit for receiving a TRIGGER OUT signal generated from a logic analyzer in response to a logic analyzer trigger event signal, and starting a post trigger counter in response thereto;data entry circuitry for entering data input by a user, said data being representative of a delay between a reception of said logic analyzer trigger event signal and said generation of said TRIGGER OUT signal by said logic analyzer;a post trigger counter for stopping an acquisition of signal data upon expiration of a count of said post trigger counter;a controller, coupled to said data entry circuitry and to said post trigger counter for receiving said delay representative data, and adjusting said count of said post trigger counter in a direction to compensate for said delay; anddisplay circuitry for displaying a portion of said acquisition centered about said logic analyzer trigger event.