Patent ID: 7324791
Filing Date: 2008-01-29
Classification: H03F,H03K

Abstract:
1. A low-noise differential bias circuit for supplying a low-noise bias current to bases or gates of a pair of differential transistors, the low-noise differential bias circuit comprising: a first resistor having a first end being connected to a base or gate of one of the pair of differential transistors; a second resistor having a first end being connected to a base or gate of another one of the pair of differential transistors; a third resistor having a first end being connected to a second end of the first resistor; a fourth resistor having a first end being connected to a second end of the second resistor; a first transistor, a second end of the third resistor being connected to a base or gate of the first transistor; and a second transistor, a second end of the fourth resistor being connected to a base or gate of the second transistor, wherein a direct-current voltage is supplied to a connection point between the first resistor and the third resistor, another connection point between the second resistor and the fourth resistor, a collector or drain of the first transistor, and a collector or drain of the second transistor, from a voltage supply point through a ground element that includes: a fifth resistor connecting the collector or drain of the first transistor to the voltage supply point; a sixth resistor connecting the collector or drain of the second transistor to the voltage supply point; a third transistor, a base or gate of the third transistor being connected to the collector or drain of the first transistor, and an emitter or source of the third transistor being connected to the connection point between the first resistor and the third resistor; a fourth transistor, a base or gate of the fourth transistor being connected to the collector or drain of the second transistor, and an emitter or source of the fourth transistor being connected to the other connection point between the second resistor and the fourth resistor; a first capacitor connecting the collector or drain of the first transistor to an emitter or source of the first transistor; and a second capacitor connecting the collector or drain of the second transistor to an emitter or source of the second transistor.