Patent ID: 8796660
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A nonvolatile memory element array comprising a plurality of nonvolatile memory elements each of which comprises: a substrate; an interlayer insulating layer provided on the substrate; a resistance variable element having a lower electrode covered with the interlayer insulating layer, an upper electrode provided to be located farther from the substrate than the lower electrode, and a resistance variable layer interposed between the upper electrode and the lower electrode; and a diode having a first electrode which is provided to be located farther from the substrate than the upper electrode and is connected in series with the upper electrode, a second electrode which is provided to be located farther from the substrate than the first electrode, and an insulating layer or semiconductor layer which is interposed between the first electrode and the second electrode; wherein the resistance variable element has a characteristic in which a resistance value of the resistance variable element becomes a high-resistance value and a low-resistance value which is lower than the high-resistance value alternately, when electric pulses having different polarities are applied between the lower electrode and the upper electrode alternately; wherein the first electrode, the insulating layer or semiconductor layer, and the second electrode form a MIM diode or a MSM diode; wherein the interlayer insulating layer is provided with a contact hole penetrating through the interlayer insulating layer in a direction substantially perpendicular to a main surface of the substrate and reaching the lower electrode: wherein the resistance variable layer is embedded in the contact hole; wherein when an area of a portion where the insulating layer or semiconductor layer is in contact with the first electrode is a first area and an area of a portion where the resistance variable layer is in contact with the upper electrode is a second area, the first area is larger than the second area; and wherein a contour of the resistance variable layer is inward relative to a contour of the upper electrode when viewed from the direction perpendicular to the main surface of the substrate, wherein a plurality of lower electrodes are arranged to extend in parallel with each other within a first plane parallel to the main surface of the substrate; wherein a plurality of second electrodes are arranged to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plurality of lower electrodes; wherein resistance variable layers are provided between the plurality of lower electrodes and the plurality of second electrodes to respectively correspond to three-dimensional cross points between the lower electrodes and the second electrodes to form the plurality of nonvolatile memory elements which are provided to respectively correspond to the three-dimensional cross points; and wherein the resistance variable layers are provided on a common lower electrode such that the resistance variable layers are physically in contact with the common lower electrode and are spaced apart from each other via the interlayer insulating layer.