Patent ID: 7709926
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A device structure manufactured in a semiconductor-on-insulator substrate having a semiconductor layer, a handle wafer, and a buried insulating layer between the semiconductor layer and the handle wafer, the device structure comprising: a first isolation region that includes a plurality of dielectric regions that extend from a top surface of the semiconductor layer to a first depth; a device region of the semiconductor layer surrounded by the plurality of dielectric regions of the first isolation region, the device region including a first doped region and a second doped region each extending from the top surface of the semiconductor layer to the buried insulating layer; a second isolation region in the semiconductor layer that extends from the top surface of the device region to a second depth shallower than the first depth, the second isolation region disposed laterally between the first doped region and the second isolation region; and a third doped region in the semiconductor layer, the third doped region oppositely doped relative to the first doped region, the third doped region defining a first p-n junction along an interface of direct contact with the first doped region, and the third doped region disposed vertically in a stacked arrangement between the second isolation region and the buried insulating layer.