Patent ID: 7468985
Filing Date: 2008-12-23
Classification: H04L

Abstract:
1. A packet storage subsystem comprising: a buffer containing a plurality of entries each uniquely addressed by an n-bit address; and an m-bit packet-processing address register employed by a processing unit to store an address for a packet being processed by the processing unit, wherein an m-bit address value within the packet-processing address register is mapped or masked to produce an n-bit address for a buffer entry containing the packet being processed, wherein each of a plurality of processing units sharing access to the buffer has an associated m-bit packet-processing address register employed by the respective processing unit to store an address for a packet being processed by that processing unit, wherein m-bit address values within each packet-processing address register are mapped or masked to produce an n-bit address for a buffer entry containing the packet being processed, wherein the buffer is a circular buffer, the packet storage subsystem further comprising: wherein m is different from n.