Patent ID: 6229186
Filing Date: 2001-05-08
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising a plurality of memory cells each comprising:first and second inverters each of which comprises a drive transistor having a first conductivity type and a load transistor having a second conductivity type connected in series between a first power voltage supply line for supplying a first power voltage and a second power voltage supply line for supplying a second power voltage and having gates connected in common and an input terminal of the first inverter is connected to an output terminal of the second inverter and an output terminal of the first inverter is connected to an input terminal of the second inverter, andtwo word transistors having the first conductivity type each having one impurity region functioning as a source or drain connected to the input terminal of each inverter, having the other impurity regions connected to different bit lines, and having gates connected to different word lines,the other impurity region of one of the two word transistors being connected to an upper-layer bit line via a bit line connecting interconnection extending in the word line direction, andat least one of said first power voltage supply line and said second power voltage supply line and said bit line connecting interconnection being a trench interconnection formed by a conductive material buried in a trench formed through the same interlayer insulating layer.