Patent ID: 7816723
Filing Date: 2010-10-19
Classification: G11C,H01L

Abstract:
1. An electrically programmable and erasable memory device comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region therebetween; an electrically conductive floating gate having a first portion disposed over and insulated from the channel region, and a second portion disposed over and insulated from the first region and including a sharpened edge; an electrically conductive P/E gate having a first portion disposed over and insulated from the first region, and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material; an electrically conductive select gate disposed laterally adjacent to and insulated from the floating gate and disposed over and insulated from the channel region; and control circuitry configured to: