Patent ID: 9042182
Filing Date: 2015-05-26
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of electrically-rewritable memory cells each connected to a word line and a local bit line; a plurality of local sense amplifiers connected to the local bit lines, the plurality of local sense amplifiers being configured to invert data of the memory cells, respectively, and to output the inverted data to a global bit line; a global sense amplifier configured to compute a logical sum of outputs of the plurality of local sense amplifiers; and an address decoder configured to switch between a first verification and a second verification, the first verification causing the plurality of local sense amplifiers to operate and causing data of a first subset of the plurality of memory cells connected to the plurality of local sense amplifiers to be verified simultaneously, the second verification causing the plurality of local sense amplifiers to stop, causing the local bit lines connected to at least one of the local sense amplifiers to be directly connected with the global bit line, and causing data of a second subset of the plurality of memory cells connected to the at least one of the local sense amplifiers to be verified simultaneously.