Patent ID: 8024693
Filing Date: 2011-09-20
Classification: G06F

Abstract:
1. A method for optimizing a circuit design during a logic synthesis stage to reduce routing congestion during a placement and routing stage, comprising: identifying a first circuit structure in the circuit design, wherein the first circuit structure includes a first set of interconnections between a first set of signal sources and a first set of signal loads, wherein the first set of interconnections causes a first number of crossovers in the first circuit structure, and wherein the first number of crossovers are expected to cause routing congestion during the placement and routing stage; generating a second circuit structure which is functionally equivalent to the first circuit structure, wherein the second circuit structure includes a second set of interconnections between a second set of signal sources and a second set of signal loads, wherein the second set of interconnections causes a second number of crossovers in the second circuit structure which is substantially less than the first number of crossovers; and replacing, by computer, the first circuit structure in the circuit design with the second circuit structure, thereby substantially reducing crossovers in the circuit design, which, in turn, reduces routing congestion during the placement and routing stage.