Patent ID: 6981063
Filing Date: 2005-12-27
Classification: H04J,H04L,H04Q

Abstract:
1. A method for time synchronization of a switching computer system having at least one main computer with, in each case, at least one assigned secondary computer, each main and secondary computer being respectively provided with at least one internal clock and being connected via at least one ATM bus, the method comprising the steps of: transmitting, via the at least one main computer and along the ATM bus, with an N-th interrupt of a sequence of interrupts which are transmitted at a fixed time interval, a synchronization message with a time indication, the time indication corresponding to a time of day of the main computer at an instant of the N-th interrupt plus the fixed time interval; reading, via the at least one secondary computer, the synchronization message via the ATM bus; setting, via the at least one secondary computer, the internal clock of the at least one secondary computer to the communicated time indication upon the occurrence of next interrupt; transmitting, via the at least one secondary computer and along the ATM bus, a success message with an identifier of the secondary computer to the main computer; reading, via the main computer, the success message; deciding, via the main computer, based on a message propagation time, whether the success message was transmitted at a proper time; defining, in the case of a correctly timed transmission, the corresponding secondary computer as synchronized; and defining, in the case of a non-correctly timed transmission, the corresponding secondary computer as unsynchronized.