Patent ID: 8375239
Filing Date: 2013-02-12
Classification: G06F

Abstract:
1. A clock-control-signal-generation circuit which generates a control signal for clock switching, and which is placed in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal, comprising: a before-switching clock processing unit, including an after-switching clock processing unit, including wherein the before-switching clock processing unit makes active and outputs the first clock-stop-permission signal on condition that one of the first and second detection signals is active, the before-switching clock processing unit makes active and outputs the second clock-stop-permission signal on condition that the third detection signal is active, and the after-switching clock processing unit makes active and outputs the clock-resume-permission signal on condition that one of the fourth to seventh detection signals is active.