Patent ID: 7666739
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A method for fabricating a split charge storage node semiconductor memory device comprising the steps of: forming a gate insulator layer on a surface of a semiconductor substrate; depositing a layer of gate electrode forming material overlying the gate insulator layer and patterning the layer of gate electrode forming material to form a control gate electrode having a first edge and a second edge; etching the gate insulator layer to form an undercut region at each of the first edge and the second edge of the control gate electrode, the undercut region exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode; depositing a layer of silicon in the undercut region to form a first layer of silicon on the portion of the semiconductor substrate and a second layer of silicon on the underside portion of the control gate electrode; oxidizing the layer of silicon to form a first layer of silicon oxide on the portion of the semiconductor substrate and a second layer of silicon oxide on the underside portion of the control gate electrode and leaving a void between the first layer of silicon oxide and the second layer of silicon oxide; and filling the void with a charge storage material.