Patent ID: 6880070
Filing Date: 2005-04-12
Classification: G06F,H04L

Abstract:
1. A processor synchronous with an instruction clock signal, comprising: an execution control unit synchronous with the instruction clock signal and operable to execute an instruction per clock cycle of the instruction clock signal; an input pipeline unit synchronous with the instruction clock signal and operable to receive a stream of input data words one data word per clock cycle of the instruction clock signal, the input pipeline unit further operable to selectively output one input data word per clock cycle of the instruction clock signal; a data modify unit coupled to the input pipeline unit, the data modify unit operable to selectively modify input data words received from the input pipeline unit according to instruction-specified operators to generate modified data words one modified data word per clock cycle of the instruction clock signal; a processor output selector operable to selectively output, at each clock cycle of the instruction clock signal, an instruction-specified one of the input data words and the modified data words; and wherein the execution control unit is operable to repeat execution of a current instruction having a background mode operator during a next clock cycle of the instruction clock signal.