Patent ID: 6437625
Filing Date: 2002-08-20
Classification: H03K

Abstract:
A latch comprising:a first logic circuit LCI receiving a first data signal D1, a first clock signal C1 and a second clock signal C2 and generating a first sampled data output SD1, wherein said LCI including a first pull-up circuit PU2 electrically coupled to said D1, said C1, said C2 and said SD1, and a first pull-down circuit PD1 electrically coupled to said D1, said C1, said C2 and said SD1; a second logic circuit LC2 receiving a second data signal D2, said C1, and said C2 and generating a second sampled data output SD2, wherein said LC2 including a second pull-up circuit PU2 electrically coupled to said D2, said C1, said C2 and said SD2, and a second pull-down circuit PD2 electrically coupled to said D2, said C1, said C2 and said SD2; a third logic circuit LC3 receiving said SD1, said C1, said C2, and a second latch output LO2 and generating a first latch output LO1, wherein said LC3 including a third pull-up circuit PU3 coupled to said SD1 and said LO2, and a third pull-down circuit PD3 coupled to said SD1, said C1, said C2, and said LO2; and a fourth logic circuit LC4 receiving said SD2, said C1, said C2, and said LO1 and generating said LO2, wherein said LC4 including a fourth pull-up circuit PU4 coupled to said SD2 and said LO1, and a fourth pull-down circuit PD4 coupled to said SD2, said C1, said C2, and said LO1.