Patent ID: 8957459
Filing Date: 2015-02-17
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor device comprising a memory cell including: a first conductivity type first MIS transistor coupled between a first voltage and a first node; a second conductivity type first MIS transistor coupled between the first node and a second voltage different from the first voltage; a second conductivity type second MIS transistor coupled between the first node and the second voltage in parallel with the second conductivity type first MIS transistor; a first conductivity type second MIS transistor coupled between the first voltage and a second node; a second conductivity type third MIS transistor coupled between the second node and the second voltage; a second conductivity type fourth MIS transistor coupled between the second node and the second voltage in parallel with the second conductivity type third MIS transistor; a second conductivity type fifth MIS transistor coupled between the first node and a first bit line; a second conductivity type sixth MIS transistor coupled between the second node and a second bit line; a second conductivity type seventh MIS transistor coupled between the first node and a third bit line; and a second conductivity type eighth MIS transistor coupled between the second node and a fourth bit line, wherein the second conductivity type first MIS transistor and the second conductivity type fifth MIS transistor are disposed in a first active region, wherein the second conductivity type second MIS transistor and the second conductivity type seventh MIS transistor are disposed in a second active region, wherein the second conductivity type third MIS transistor and the second conductivity type sixth MIS transistor are disposed in a third active region, wherein the second conductivity type fourth MIS transistor and the second conductivity type eighth MIS transistor are disposed in a fourth active region, wherein a first gate wiring extends in a first direction over the first active region, wherein a second gate wiring extends in the first direction over the first active region and the second active region, wherein a third gate wiring extends in the first direction over the fourth active region, and wherein a fourth gate wiring extends in the first direction over the third active region and the fourth active region, wherein a fifth gate wiring extends in the first direction over the second active region, wherein a sixth gate wiring extends in the first direction over the third active region, wherein a first wiring is electrically coupled to a source region of the second conductivity type first MIS transistor in the first active region and a source region of the second conductivity type second MIS transistor in the second active region, wherein a second wiring is electrically coupled to the first gate wiring, wherein the first wiring is disposed between the third bit line and the first bit line, wherein the first bit line is disposed between the first wiring and the second wiring, wherein a third wiring is electrically coupled to a source region of the second conductivity type third MIS transistor in the third active region and a source region of the second conductivity type fourth MIS transistor in the fourth active region, wherein a fourth wiring is electrically coupled to the third gate wiring, wherein the third wiring is disposed between the fourth bit line and the second bit line, wherein the fourth bit line is disposed between the third wiring and the fourth wiring, wherein a fifth wiring is electrically coupled to the fifth gate wiring, wherein a sixth wiring is electrically coupled to the sixth gate wiring, wherein the third bit line is disposed between the fifth wiring and the first wiring, wherein the second bit line is disposed between the sixth wiring and the third wiring, wherein the first to sixth wirings and the first to fourth bit lines are provided in a same wiring layer among a plurality of wiring layers provided over a semiconductor substrate, and wherein the first to fourth bit lines extend in a second direction perpendicular to the first direction.