Patent ID: 6205069
Filing Date: 2001-03-20
Classification: G11C

Abstract:
semiconductor memory device comprising:a memory cell array comprising a first group of memory cells and a second group of memory cells;a first group of input-output (IO) line pairs, the first group of IO line pairs transferring data to and from the first group of memory cells;a second group of IO line pairs, the second group of IO line pairs transferring data to and from the second group of memory cells;a precharge circuit precharging the first and second groups of IO line pairs, in response to a first precharge signal and a second precharge signal, respectively; anda precharge controller producing the first and second precharge signals, wherein in a normal mode operation of the memory device, the precharge controller activates the first and second precharge signals so that the first and second groups of IO line pairs are precharged when a write interrupt is detected, and in a full page mode, the precharge controller activates one of the first and second precharge signals so that one of the first and second groups of IO line pairs are precharged while data are written to the memory cell array through the other after writing data into the memory cell array through the one.