Patent ID: 7979681
Filing Date: 2011-07-12
Classification: G06F

Abstract:
1. A method comprising: identifying a first block of bits within a result to be written to a destination register by an execution unit, the result comprising a plurality of bits including the first block of bits and a second block of bits, the first block of bits having a zero value corresponding to a first portion of the destination register and the second block of bits having a non-zero value corresponding to a second portion of the destination register; selectively writing the second block of bits to the second portion of the destination register without writing the first block of bits to the first portion of the destination register irrespective of a value stored in the first portion of the destination register; providing a first encoded bit value to a control register, the first encoded bit value indicating that the first block of bits has the zero value; providing a second encoded bit value to the control register, the second bit value indicating that the second block of bits has the non-zero value; maintaining a first register read enable line inactive based on the first encoded bit value, wherein the first register read enable line is associated with the first portion of the destination register; selectively loading the second block of bits from the second portion of the destination register to the execution unit based on the second encoded bit value by selectively activating a second register read enable line associated with the second portion of the destination register based on the second encoded bit value; and providing a third block of bits having a value of zero to the execution unit in place of the value stored in the first portion of the destination register.