Patent ID: 7590958
Filing Date: 2009-09-15
Classification: G06F

Abstract:
1. A method for performing performance analysis of a semiconductor chip design, the semiconductor chip design comprising a plurality of elements, the elements including one or more embedded semiconductor devices and one or more embedded interconnects, the method comprising: distributing power dissipated by at least some of the elements among the plurality of elements; constructing a three-dimensional full-chip thermal model of the semiconductor chip design in accordance with the distributed power, the thermal model depicting a respective computed temperature for each of the at least some of the elements; calculating, using a processor, a respective value of a semiconductor performance parameter for each of the at least some of the elements, in accordance with the respective computed temperature; providing the respective values of the semiconductor performance parameter to at least one performance analysis tool for assessment of the power dissipated by the at least some of the elements; receiving a first input computed, at least in part, by the at least one performance analysis tool as a result of the assessment, the first input comprising updated values for the power dissipated by the at least some of the elements; and calculating, using a processor, a respective modified temperature for each of the at least some of the elements in accordance with the first input, wherein the one or more embedded interconnects are deployed, at least in part, to connect the one or more embedded semiconductor devices.