Patent ID: 6255687
Filing Date: 2001-07-03
Classification: H01L,Y10S

Abstract:
A memory structure comprising:a semiconductor substrate;a contact plug;a storage node formed over the semiconductor substrate and composed of a layer of polysilicon on a surface of a volume of silicon-containing material, the layer of polysilicon being composed of at least one of HSG polysilicon and CSG polysilicon, the volume of silicon-containing material being in contact with said contact plug and having an ion concentration therein that is in a range from about 1.times.10.sup.15 ions per cm.sup.3 of silicon-containing material to about 1.times.10.sup.22 ions per cm.sup.3 of silicon-containing material, wherein said ion concentration presents an ion concentration gradient through said silicon-containing material, said storage node comprising:a base in contact with said contact plug; anda free-standing wall extending from said base and having opposing non-planar surfaces, wherein said free-standing wall is provided with a shape that is partly determined by said ion concentration gradient;a dielectric layer upon said storage node; andan electrically conductive cell plate upon said dielectric layer.