Patent ID: 8901670
Filing Date: 2014-12-02
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate structure on a channel region of a semiconductor substrate, wherein the gate structure includes a gate dielectric on the semiconductor substrate, a metal gate conductor on the gate dielectric and a metal semiconductor alloy gate conductor on the metal gate conductor; at least one spacer present on the sidewalls of the gate structure; a source region and a drain region present in contact with the semiconductor substrate on opposing sides of the channel region, wherein each of the source region and the drain region include a metal semiconductor contact having a different composition than the metal semiconductor alloy gate conductor; a continuous encapsulating dielectric layer extending over the gate structure, the at least one spacer and at least a portion of the source and drain region, wherein the continuous encapsulating dielectric layer is composed of a high-k dielectric selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof; a uniform dielectric layer positioned between the continuous encapsulating dielectric layer, the entire outermost and topmost surfaces of said at least one spacer and the metal semiconductor contact and having a base directly contacting a topmost surface of said semiconductor substrate; and a dielectric layer overlaying said continuous encapsulating dielectric layer, wherein said continuous encapsulating dielectric layer covers the entirety of the gate structure.