Patent ID: 6611218
Filing Date: 2003-08-26
Classification: H03L,H03M

Abstract:
A data combiner comprising:a. a current-steering circuit including: i. a first clock terminal adapted to receive a first clock signal of a first clock phase; ii. a second clock terminal adapted to receive a second clock signal of a second clock phase; iii. a first data terminal adapted to receive a first series of data bits; iv. a second data terminal adapted to receive a second series of data bits synchronized with the first series of data bits so that pairs of data bits arrive at the first and second data terminals substantially simultaneously; and v. a data output terminal; vi. wherein the current-steering circuit is adapted to combine the first and second series of data bits into a third series of data bits and to provide the third series of data bits on the data output terminal; and b. a current source connected to the data output terminal.