Patent ID: 6178133
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A row command unit in an integrated circuit including N memory banks, comprising:N row control latches, each row control latch having an output coupled to a respective memory bank and having an enable terminal and a control terminal, the row control latch latching a signal applied on the control terminal when an active enable signal is applied on the enable terminal;M delay circuits where M is less than N, each delay circuit generating a row control signal on an output terminal responsive to an activation signal applied on an input terminal; anda bank control circuit coupled to the respective input terminals of the delay circuits and adapted to receive sequentially applied bank address and bank control signals, the bank control circuit also having a plurality of output terminals, each output terminal coupled to a respective enable terminal of one of the row control latches, the bank control circuit operable to apply an active enable signal to a selected one of the row control latches responsive to the applied bank control and bank address signals, and also operable to select one of the delay circuits, the bank control circuit applying the activation signal to the selected delay circuit and further applying the row control signal of the selected delay circuit to the control terminal of the selected row control latch to thereby cause the selected row control latch to latch the row control signal and apply the latched row control signal to access a row of memory cells in the corresponding memory bank.