Patent ID: 6195721
Filing Date: 2001-02-27
Classification: G06F

Abstract:
An interface circuit for inter-processor data transfer management comprising:means coupled between a requesting processor bus and a responding processor bus for storing in response to a transfer request initiated by the requesting processor an address and data, the address being an access address to the responding processor and the data being data from the requesting processor for storage at the access address for a write request or data from the responding processor for transfer from the access address for a read request; andmeans coupled between the requesting processor bus and the responding processor bus for controlling the storing means and for communicating with requesting and responding processors so that the processors are decoupled from the data transfer in that the transfer request by the requesting processor for access to the responding processor is acknowledged by the controlling means so that the requesting processor may continue its processing until an interrupt is received from the controlling means indicating that the controlling means has completed the request and is ready to receive another request, and the controlling means arbitrates for access to the responding processor bus to complete the data transfer between the responding processor and the storing means so that the responding processor may continue its processing while the data transfer takes place;whereby the interface circuit controls the data transfer between the requesting and responding processors so that the processors do not stall during such data transfer.