Patent ID: 8953668
Filing Date: 2015-02-10
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit, comprising: a sampler for sampling an input data according to a recovery clock to generate an edge value and a sampling value; a phase detector for performing phase detection according to the edge value and the sampling value to generate a detection value; a filter for generating a control word according to the detection value; and a phase digital-to-analog converter for adjusting a phase of a reference clock according to the control word to generate the recovery clock with a corresponding phase; wherein the control word does not contain jitter when the filter operates in a normal mode and the control word contains jitter when the filter operates in a measure mode; wherein the filter comprises: a proportional unit for multiplying the detection value by a proportional constant to generate a proportional value; an integral unit for integrating the detection value and multiplying the integrated detection value by an integral constant to generate an integral value; a jitter source for generating a jittered voltage signal according to a control signal while operating in the measure mode, the litter source being disabled while operating in the normal mode; an adder for adding the proportional value and the integral value; and an integrator for integrating the output of the adder to generate the control word; wherein an output of the jitter source is added to an output of the phase detector using a second adder, and wherein an output of the second adder is inputted to the proportional unit and the integral unit, an input terminal of the proportional unit and an input terminal of the integral unit.