Patent ID: 6260118
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A computer system, comprising:a multitude of independent microprocessing units;a multiprocessor bus;a multitude of cache storage units, each cache storage unit of the multitude of cache storage units coupled to one of the multitude of microprocessing units;a multitude of bus interface units (BIUs), each BIU of the multitude of BIUs coupling each respective microprocessing unit through each respective cache storage unit to the multiprocessor bus;an I/O bus for coupling to I/O devices; anda memory controller coupled to the multiprocessor bus and the I/O bus for processing requests from any one of the multitude of independent microprocessing units for determining which addresses forming a block having a plurality of cache lines need to be snooped and for implementing a cache storage unit block snoop operation for the block when a determination is made that an address needs to be snooped and, alternatively, an I/O operation when a determination is made that the address does not need to be snooped.