Patent ID: 6097660
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory banks disposed in a first direction each memory bank having a plurality of memory cell arrays and a plurality of sense amplifiers, wherein said plurality of memory cell arrays and said plurality of sense amplifiers are alternately disposed in a second direction perpendicular to the first direction;a plurality of row decoder sections, each row decoder section having a plurality of row decoders disposed in the second direction, wherein said plurality of row decoder sections and said plurality of memory banks are disposed in the first direction;a column decoder section provided adjacent to said plurality of memory banks and said plurality of row decoder sections, said column decoder section having a plurality of column decoders disposed in the first direction;a plurality of first data lines laid in the first direction, respectively provided for said plurality of memory banks, and connected with said plurality of sense amplifiers in accordance with a signal outputted from said column decoder section;a plurality of second data lines laid in the first direction, penetrating through said plurality of memory banks, and shared by said plurality of first data lines; anda plurality of switching elements, each switching element having a first end connected to one of said plurality of first data lines and a second end connected to one of said plurality of second data lines, wherein said plurality of switching elements are controlled by a bank activation signal for at least one of said plurality of memory banks corresponding to at least one of said plurality of first data lines.