Patent ID: 8432744
Filing Date: 2013-04-30
Classification: G11C

Abstract:
1. A semiconductor storage device, comprising: a plurality of memory cells which electrically will rewrite data; a well control circuit configured to output an erasure voltage to be applied to the well; a first pump circuit configured to output a voltage set by boosting an input voltage to the well control circuit; a second pump circuit configured to output a voltage set by boosting the input voltage to the well control circuit and output a voltage higher than that of the first pump circuit; a pump switching detecting circuit configured to output an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit; and an erase pulse control circuit configured to set target voltages of the first pump circuit and the second pump circuit, wherein, in the erasure operation, when the erasure voltage is less than an assist boundary value, the pump switching detecting circuit performs the boosting operation on the first pump circuit on the basis of the assist signal and outputs the boosting voltage, and when the erasure voltage is equal to or more than the assist boundary value, the pump switching detecting circuit performs the boosting operation on the second pump circuit on the basis of the assist signal and outputs a boosting voltage, the erasure pulse control circuit sets the target voltages of the first pump circuit and the second pump circuit to be increased stepwisely, on the basis of the setting values to set the target voltages, and the well control circuit applies the erasure voltage that is output from the first pump circuit or the second pump circuit to be activated and is increased stepwisely to the well.