Patent ID: 8762599
Filing Date: 2014-06-24
Classification: G06F

Abstract:
1. An apparatus comprising: a core to generate a registration message to delegate a poll operation to an input/output (IO) interconnect; the IO interconnect coupled to the core, the IO interconnect to include a poll table having a plurality of entries each having a first address field to store a first address to be received in a registration message, a destination address field to store a destination address in a system memory to be received in the registration message, and an initial value field to store an initial value associated with the first address received in the registration message; and at least one device coupled to the IO interconnect to perform an operation for an application to be executed on the core and to include at least one status register, the IO interconnect including a poll delegation logic to poll the at least one status register responsive to information in a poll table entry, and to issue a write transaction to the destination address if a polled value of the at least one status register differs from an initial value of the at least one status register stored in the poll table entry.