Patent ID: 8404551
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A method of forming a planar transistor on a semiconductor bulk substrate, comprising the steps of implanting a highly doped screening layer on the semiconductor bulk substrate, the highly doped screening layer having a preselected dopant concentration and thickness; forming a threshold voltage set region above and in contact with the highly doped screening layer, the threshold voltage set region having a preselected thickness, the threshold voltage set region being co-extensive with the screening layer, the threshold voltage set region having a preselected dopant concentration that is less than the dopant concentration of the highly doped screening layer; forming a substantially undoped channel on the threshold voltage set region, the substantially undoped channel extending to a source and a drain, the substantially undoped channel being co-extensive with the screening layer and the threshold voltage set region, the substantially undoped channel having a selected thickness, the screening layer and the threshold voltage set region extending to the source and drain; forming a gate on a transistor substrate; implanting source/drain extensions into the substantially undoped channel between the source and the drain that have a dopant concentration of less than about 1×10