Patent ID: 9159629
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A method comprising: forming over a semiconductor substrate a buffer layer having a lattice constant mismatch with the semiconductor substrate; forming a semiconductor-capping layer over the buffer layer, wherein the semiconductor-capping layer has a lattice constant smaller than a lattice constant of the buffer layer; forming a gate dielectric layer over the buffer layer; forming a gate electrode layer over the gate dielectric layer; patterning the gate dielectric layer and the gate electrode layer to form the gate dielectric and the gate electrode, respectively; etching a semiconductor layer underlying the gate dielectric using the gate electrode and the gate dielectric as an etching mask; after the etching the semiconductor layer, forming a gate spacer on sidewalls of the gate dielectric and the gate electrode, wherein a bottom surface of the gate spacer is in contact with a top surface of the semiconductor-capping layer, and wherein the gate spacer extends below the gate dielectric; recessing a portion of the buffer layer to form a recess, wherein during the recessing, the gate electrode and the gate spacer are used as an etching mask; and forming a source/drain region adjacent to the gate spacer.