Patent ID: 6498092
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A method for fabricating a semiconductor device having a dual damascene line structure, the method comprising the steps of:forming a first interlayer insulation layer on a semiconductor substrate on which a first conductive pattern has been formed; forming an etching stopper on the first interlayer insulation layer; forming an etching stopper pattern above the first conductive pattern by patterning the etching stopper, the etching stopper pattern remaining after patterning being localized to regions corresponding to the first conductive pattern; depositing a second interlayer insulation layer on the etching stopper pattern; patterning the second interlayer insulation layer, thereby forming a first metal trench exposing the etching stopper pattern, and thereby forming a second metal trench formed through the second interlayer insulation layer and a portion of the first interlayer insulation layer; providing a via contact hole exposing the first conductive pattern in an area corresponding to the first metal trench; and forming a second conductive layer in the first metal trench, the second metal trench and the via contact hole.