Patent ID: 8693253
Filing Date: 2014-04-08
Classification: G11C,H01L

Abstract:
1. A NAND flash memory, comprising at least one memory structure including: a plurality of first bitlines and a plurality of second bitlines extending along a first direction; a plurality of first charge-trapping stacks positioned over the first bitline, wherein each of the plurality of first charge-trapping stacks has at least one first charge-trapping region, and the plurality of first charge-trapping stacks are separated from each other; a plurality of second charge-trapping stacks positioned below the second bitlines, wherein each of the plurality of second charge-trapping stacks has at least one second charge-trapping region, and the plurality of second charge-trapping stacks are separated from each other; and a plurality of wordlines positioned between the first charge-trapping stacks and the second charge-trapping stacks, wherein the plurality of wordlines extending along a second direction; wherein the plurality of first charge-trapping region and the plurality of second charge-trapping region are stacked along a third direction substantially perpendicular to the first direction and the second direction.