Patent ID: 6086238
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A method of shape processing for extracting an interconnect capacitance event within an integrated circuit layout for parasitic capacitance estimation, said method comprising the steps of:identifying a plurality of coordinates of an overlapping region formed by at least one interconnect;classifying each metal layer present within said overlapping region;determining each interconnect edge present on each side of said overlapping region; anddetermining a neighbor in a direction perpendicular to an east side and a west side of said overlapping region bytraversing in-order along a scanline to locate each vertical interconnect edge while said scanline is intersecting said overlapping region at a scanstop;comparing each west-pointing interconnect edges on said scanline to a plurality of east-pointing interconnect edges stored in a second scan-buffer for locating a corresponding east-pointing interconnect edge; andrecording a distance and a netname of said corresponding east-interconnect edge.