Patent ID: 7627721
Filing Date: 2009-12-01
Classification: G06F,H04L

Abstract:
1. An advanced processor, comprising: a plurality of processor cores each having a data cache; a data switch interconnect directly coupled with the data cache of each of the plurality of processor cores and configured to pass memory related information among the plurality of processor cores; a level 2 cache coupled to the data switch interconnect and configured to employ a coherency technique that allows the sharing of dirty cache lines across the plurality of processor cores, wherein the data switch interconnect includes a ring arrangement with a plurality of ring elements each coupled to a respective data cache of each of the plurality of processor cores and a respective portion of the level 2 cache; a fast messaging ring component directly coupled the plurality of processor cores, the fast messaging ring component including a ring input coupled to an insertion queue and a receive queue; and a plurality of communication ports coupled with the fast messaging ring component for providing communication with a plurality of high-speed processor I/O devices.