Patent ID: 6707758
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A semiconductor memory device inputting and outputting data synchronously with rise and fall of an external clock, comprising:a memory cell array storing data; a clock generation circuit generating first and second internal clocks corresponding to the rise and the fall of said external clock, respectively, synchronously with said external clock; at least one clock select circuit selecting one of said first and second internal clocks as a first operation clock and selecting the other one of said first and second internal clocks as a second operation clock in accordance with the number of cycles from receiving a command to read the data from said memory cell array until starting to output the read data read from said memory cell array to an outside; at least one signal recovery circuit recovering a signal outputted from said clock select circuit; and at least one data output circuit receiving said first and second operation clocks outputted from said signal recovery circuit, and outputting said read data to the outside synchronously with said first and second operation clocks.