Patent ID: 6171894
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method of manufacturing a BICMOS integrated circuit including an NPN transistor in a heavily-doped P-type wafer coated with a lightly-doped P-type epitaxial layer, including the steps of:forming an N-type doped well to form the collector of a bipolar transistor, this well having a relatively high and substantially homogeneous doping level;coating the structure with a polysilicon seed layer and opening the sandwich above portions of the collector well;epitaxially growing undoped silicon, then epitaxially growing P-type doped silicon forming above the collector region a single-crystal silicon base region;depositing an insulating layer and opening it at the location of the emitter;depositing N-type emitter polysilicon;etching the emitter polysilicon beyond useful areas;etching the base silicon outside the useful areas while leaving in place, in particular, a portion above a thick oxide region;forming spacers;forming a collector contact area at the same time as the drain implantation of the N-channel MOS transistors; andperforming a P-type base contact area implantation at the same time as the drain and source implantations of the P-channel MOS transistors.