Patent ID: 7563662
Filing Date: 2009-07-21
Classification: B82Y,H01L

Abstract:
1. A process for forming a non-volatile memory device, wherein the process comprises: forming a trench field isolation region over a substrate to define an active region in the substrate, wherein the active region comprises a first portion, a non-volatile memory portion, and a logic portion; forming a sacrificial insulating layer over the first portion of the active region, the non-volatile memory portion of the active region, and the logic portion of the active region; removing a first portion of the sacrificial insulating layer from over the non-volatile memory portion of the active region, wherein a first portion of the trench field isolation region from over the non-volatile memory portion is exposed after the first portion of the sacrificial insulating layer is removed; forming a first gate dielectric layer over the non-volatile memory portion of the active region; forming a charge storage layer over the substrate; forming a control gate conductor layer over the charge storage layer; removing first portions of the charge storage layer and control gate conductor layer that overlie the first portion of the active region; removing a second portion of the sacrificial insulating layer from over the first portion of the active region, wherein a second portion of the trench field isolation region is exposed after the second portion of the sacrificial insulating layer is removed; forming a second gate dielectric layer over the first portion of the active region, wherein forming the second gate dielectric layer is performed after forming the first gate dielectric layer; forming a first resist mask over a first part of the logic portion of the active region to define a first opening; removing second portions of the control gate conductor layer and charge storage layer underlying the first opening in the first resist mask; implanting a first dopant for a first well region within the first part of the logic portion, wherein the first well region underlies the first opening; removing a third portion of the sacrificial insulating layer from over the first part of the logic portion of the active region, wherein a third portion of the trench field isolation region is exposed after the third portion of the sacrificial insulating layer is removed; removing the first resist mask; and forming a third gate dielectric layer over the logic portion of the active region, wherein forming the third gate dielectric layer is performed after forming the first gate dielectric layer, forming the second gate dielectric layer, and implanting the first dopant.