Patent ID: 7929333
Filing Date: 2011-04-19
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines, wherein the write/read circuit is configured to be able to change over between a transfer state, in which the data can be transferred between the paired bit lines connected to one of the sub arrays arranged on a front stage and the paired bit lines connected to other one of the sub arrays arranged on a rear stage, and a precharge state in which the paired bit lines are precharged, and wherein the write/read circuit switches over a state from the precharge state to the transfer state after the data read from the memory cells is reflected on the paired bit lines connected to one of the sub arrays arranged on the front stage.