Patent ID: 9069565
Filing Date: 2015-06-30
Classification: G06F

Abstract:
1. A processor that executes instructions of a plurality of threads in each of a plurality of cycle stages, the processor comprising: first selectors that select input instruction addresses of instructions of a plurality of threads or a branch target address of a branch instruction to be predicted and that output addresses of the plurality of threads; a second selector that selects one of the addresses of the plurality of threads output by the first selectors; a branch prediction circuit that predicts and outputs a branch direction, which indicates whether the branch instruction of the address selected by the second selector is branched, based on the selected address in a first cycle stage of the plurality of cycle stages and that predicts and outputs the branch target address of the branch instruction to be predicted based on the selected address in a second cycle stage later than the first cycle stage; and a thread arbitration circuit that controls selection of the addresses of the threads by the first selectors and the second selector based on the branch direction output by the branch prediction circuit.