Patent ID: 7186595
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. A method of manufacturing a solid picture element having a semiconductor substrate of a first conductive type with a first surface, a transistor located within the semiconductor substrate for amplifying charges, a charge accumulation region of a second conductive type located within the semiconductor substrate, the charge accumulation region having a margin located a first distance from the transistor, a depletion prevention region of the first conductive type located between the charge accumulation region and the first surface of the semiconductor substrate, the depletion prevention region having a margin located a second distance from the transistor, and a transfer gate located on the first surface of the semiconductor substrate between the depletion prevention region and the translator overlapping a portion of the depletion prevention region margin and the charge accumulation region margin, the charge accumulation region margin being closer to the transistor than the depletion prevention margin, the transfer gate controlling transfer of charges from the charge accumulation region to the transistor, the substrate and the depletion prevention region have different impurity concentrations, the method comprising the steps: implanting ions of the first conductive type at a first angle to the first surface of the semiconductor substrate using the transfer gate as a mask and forming the charge accumulation region such that it is within the semiconductor substrate and doesn't contact the first surface of the semiconductor substrate; and implanting ions of the second conductive type at a second angle to the first surface of the semiconductor substrate using the transfer gate as a mask and forming the depletion prevention region such that it is between the charge accumulation region and the first surface of the semiconductor substrate; wherein the first angle is not greater than the second angle, thereby causing the first distance of the charge accumulation region margin to the transistor to be no greater than the second distance of depletion prevention region margin to the transistor.