Patent ID: 7391654
Filing Date: 2008-06-24
Classification: G11C

Abstract:
1. A method for erasing a flash memory device comprising a plurality of memory blocks, each memory block having a plurality of memory cells organized in columns and rows, the method comprising: performing an erase operation on a first memory block; determining if any of the plurality of memory cells of the first memory block is unerased by performing an erase verification operation that comprises biasing all of the rows of the first memory block substantially simultaneously with an erase verify read potential; and performing a selective erase operation only on rows comprising an unerased memory cell in response to a normal memory read operation that determines which memory cells of the first memory block remain unerased wherein the normal memory read operation comprises biasing only a selected row of the first memory block with a normal read potential and biasing the remaining rows of the first memory block at a V