Patent ID: 6037212
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating a storage capacitor electrode structure for use in a semiconductor memory cell including a transfer transistor formed on a substrate, the method comprising:forming a first insulating layer over the transfer transistor;forming a first conducting layer which penetrates the first insulating layer and contacts a source/drain region of the transfer transistor;forming a protruding layer above the first conducting layer, the protruding layer having a series of steps leading up to a top surface level;forming a second conducting layer on the protruding layer;forming a second insulating layer on the second conducting layer;removing selective portions of the second insulating layer and the second conducting layer to form a surface at the level of the protruding layer top surface;forming a third conducting layer on the surface at the level of the protruding layer top surface which contacts the second conducting layer;removing selective portions of the third conductive layer and the protruding layer to form an opening to the level of the first conducting layer, the opening having a sidewall;forming a fourth conducting layer on the sidewall of the opening and contacting the third and the first conducting layers; andremoving selective portions of the second conducting layer and the third conducting layer, and removing entirely the second insulating layer and the protruding layer;wherein the storage capacitor electrode structure includes the first, second, third and fourth conducting layers.