Patent ID: 7005743
Filing Date: 2006-02-28
Classification: H01L

Abstract:
1. A semiconductor device comprising a wiring board formed with a plurality of electrodes, a semiconductor integrated circuit chip formed with a plurality of bumps, and a sealing resin for bonding the electrodes and bumps at corresponding positions and further surrounding the bonding portions of the electrodes and bumps to adhere said wiring board and semiconductor integrated circuit chip, wherein each individual bump is formed under the condition that quantities ΦA, H, and F are in the region defined by a following formula C1, and adjacent bumps are formed under the condition that the interval between adjacent bumps is in the region defined by a formula C2: where, ΦA denotes a top diameter of a bump bonded with an electrode; H denotes a height of a bump, defined as the distance from the semiconductor integrated circuit chip to the end of the bump bonded with an electrode; F denotes a linear thermal expansion coefficient of the sealing resin; a a L denotes the interval (distance) between adjacent bumps; b b