Patent ID: 6115287
Filing Date: 2000-09-05
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a NAND string constituted of a plurality of memory cell transistors connected in series, each of the memory cell transistors having:a semiconductor layer formed on an insulation layer and isolated by an element isolation insulation layer;a gate insulation layer formed on the semiconductor layer;a charge storing layer formed on the gate insulation layer; anda control gate layer formed on the charge storing layer with an insulation layer arranged therebetween;a bit line connected to a drain side of the NAND string; anda source line connected to a source side of the NAND string,wherein a first potential is applied to at least one of the bit line and the source line, and one of a second potential, which is higher than the first potential, and a third potential, which is lower than the first potential, is applied to the control gate layer of each of the memory cell transistors, thereby to transfer charges between a channel and the charge storing layer of each of the memory cell transistors.