Patent ID: 7763942
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A pixel structure, comprising: a substrate; a semiconductor pattern and a data line, formed on the substrate, wherein the semiconductor pattern has a source region, a drain region, a channel region, and a lightly doped region, the source region and the drain region are respectively located on two sides of the channel region, and the lightly doped region is located between the channel region and the source region and between the channel region and the drain region; a scan line, formed on the substrate, and located above the data line; a gate pattern, formed on the semiconductor pattern, and electrically connected to the scan line; a gate insulation layer, located between the gate pattern and the semiconductor pattern; a source pattern and a drain pattern, respectively disposed on two sides of the gate pattern, and respectively electrically connected to the source region and the drain region, wherein the source pattern is further electrically connected to the data line; a protective layer, disposed on the substrate to cover the semiconductor pattern, the data line, the scan line, the gate pattern, the source pattern, and the drain pattern, and having a contact window for exposing the drain pattern; and a pixel electrode, disposed on the protective layer, and electrically connected to the drain pattern through the contact window.