Patent ID: 8493259
Filing Date: 2013-07-23
Classification: H03M

Abstract:
1. A stage of a pipelined analog-to-digital converter, comprising: a first pair of comparators configured to compare an input voltage received at an input node to a first positive reference voltage and to a first negative reference voltage, respectively, each of the first pair of comparators configured to output respective digital signals to an encoder; a second pair of comparators configured to compare the input voltage received at the input node to a second positive reference voltage and to a second negative reference voltage, respectively, each of the second pair of comparators configured to output respective digital signals to the encoder; a third pair of comparators configured to compare the input voltage received at the input node to a third positive reference voltage and to a third negative reference voltage, respectively, each of the third pair of comparators configured to output respective signals to a random number generator; a comparator configured to compare the input voltage received at the input node to ground voltage potential and output a signal to the random generator; and a multiplying digital-to-analog converter configured to output a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.