Patent ID: 6122215
Filing Date: 2000-09-19
Classification: G11C

Abstract:
A semiconductor memory device comprising:a dynamic memory cell array;a row circuit for selecting a row of said memory cell array;a column circuit for selecting a column of said memory cell array;a write circuit for writing data into said memory cell array;a RAS buffer for supplying RAS input signal to said row circuit;a CAS buffer for supplying an input CAS signal to said column circuit;a WE buffer for supplying an input WE signal to said write circuit;a first voltage lowering circuit of feedback type having a P-channel MOS transistor exclusively used for supplying a potential created by lowering the power supply voltage supplied from the exterior to at least one of said RAS buffer, CAS buffer and WE buffer as a power supply voltage thereof;a bit line precharge potential generating circuit for generating a precharge potential of bit lines of said memory cell array;a memory cell plate potential generating circuit for generating a plate potential of memory cells of said memory cell array; anda second voltage lowering circuit of feedback type having a P-channel MOS transistor exclusively used for supplying a potential created by lowering the power supply voltage supplied from the exterior to part of at least one of said bit line precharge potential generating circuit and said memory cell plate potential generating circuit as a power supply voltage thereof.