Patent ID: 8946027
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A method for manufacturing a fin field effect transistor (FinFET), comprising: forming a dummy gate over a portion of a silicon (Si) fin of said FinFET, said fin being formed on a silicon germanium (SiGe) layer, which contacts a crystalline Si substrate devoid of an insulator; forming source/drain (S/D) regions on each side of said dummy gate in said Si fin; depositing extrinsic S/D regions on said S/D regions of said Si fin and portions of said SiGe layer not covered by said dummy gate; removing said dummy gate and exposing a channel region of said Si fin and portions of said SiGe layer orthogonal to said channel region; removing portions of said SiGe layer from beneath said channel region, removing portions of said SiGe layer adjacent to ends of said channel region that underlie portions of said S/D regions of said Si fin, and removing portions of said SiGe layer that are exposed and orthogonal to said channel region, and replacing said portions of said SiGe layer that are removed with an insulator to electrically isolate said channel region and said portions of said S/D regions adjacent to said channel region of said Si fin from said crystalline Si substrate; depositing a conformal dielectric on said channel region of said Si fin and said insulator; and filling a space delimited by said conformal dielectric with a gate stack over said channel region of said Si fin.