Patent ID: 8823062
Filing Date: 2014-09-02
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: six linear-shaped conductive structures formed to extend lengthwise in a parallel direction to each other, a first of the six linear-shaped conductive structures forming gate electrodes of both a first p-transistor and a first n-transistor, a second of the six linear-shaped conductive structures forming a gate electrode of a second p-transistor, a third of the six linear-shaped conductive structures forming a gate electrode of a second n-transistor, a fourth of the six linear-shaped conductive structures forming a gate electrode of a third p-transistor, a fifth of the six linear-shaped conductive structures forming a gate electrode of a third n-transistor, a sixth of the six linear-shaped conductive structures forming gate electrodes of both a fourth p-transistor and a fourth n-transistor, wherein each of the second and fourth linear-shaped conductive structures does not form a gate electrode of any n-transistor, wherein each of the third and fifth linear-shaped conductive structures does not form a gate electrode of any p-transistor, the second and third linear-shaped conductive structures having substantially co-aligned lengthwise-oriented centerlines and separated from each other by a first end-to-end spacing, the fourth and fifth linear-shaped conductive structures having substantially co-aligned lengthwise-oriented centerlines and separated from each other by a second end-to-end spacing, wherein an end of the second linear-shaped conductive structure adjacent to the first end-to-end spacing is offset in the parallel direction from an end of the fourth linear-shaped conductive structure adjacent to the second end-to-end spacing, and/or an end of the third linear-shaped conductive structure adjacent to the first end-to-end spacing is offset in the parallel direction from an end of the fifth linear-shaped conductive structure adjacent to the second end-to-end spacing.