Patent ID: 6720610
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a semiconductor substrate; a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate; floating gates formed in said element-forming regions via a first gate insulating film and separated for individual of said element-forming regions, a level of a top surface of said first gate insulating film being lower than a level of a top surface of said element isolation/insulation film and a part of said floating gates reaching a side surface of said element isolation/insulation films; a second gate insulating film formed on said floating gates, at least a part of said second gate insulating film reaching a top surface of said element isolation/insulation films; control gates formed on said floating gates by said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control ages, wherein said second gate insulating film is divided and separated only above said element isolation/insulation films.