Patent ID: 8980739
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A method of forming bumps of a semiconductor device with reduced solder bump collapse, the method comprising: preparing a semiconductor substrate in which pads are exposed externally through a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose a portion of the seed layer on the pads; forming pillars by performing a primary electroplating at a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars, such that at least a portion of the solder layer directly contacts a top surface of the photoresist pattern; removing the photoresist pattern; performing a thermal treatment on the semiconductor substrate using formic acid (HCO2H) such that a natural oxide layer is removed; forming solder bumps, in which solder partially covers surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps after forming the solder bumps.