Patent ID: 8615621
Filing Date: 2013-12-24
Classification: G06F

Abstract:
1. An electronic device, comprising: a memory interface operative to provide mechanical and electrical connectivity to memory media; a data communication bus connected to the memory interface; an Application Processor Engine (APE) connected to the data communication bus and operative to execute application programs, and further operative to write data to and read data from memory media, when connected to the memory interface via the data communication bus; and an Accelerated Storage Controller (ASC) comprising a device port configurably connected to the data communication bus; wherein the ASC is configurably operative to transfer data between an external host, when connected via the communication port, and memory media, when connected to the memory interface, via the host port and the data communication bus; wherein the ASC is further configurably operative to functionally disconnect the host port from the data communication bus to allow the APE to read data from and write data to memory media, when connected to the memory interface, via the data communication bus; wherein the APE is configurably operative to transfer data to and from the ASC via the data communication bus and the device port; and wherein the APE is further configurably operative to transfer data to and from an external host via the data communication bus, and the device port and communication port of the ASC.