Patent ID: 7642844
Filing Date: 2010-01-05
Classification: H01L

Abstract:
1. A semiconductor integrated circuit, comprising: a semiconductor substrate; two or more wells formed in the semiconductor substrate; two or more diffusion layers formed in the two or more wells; a plurality of interconnects formed in an interconnect layer, the two or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential; and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the two or more wells and connected to a first diffusion layer of the two or more diffusion layers that is formed in the first well, wherein the two or more wells include a second well, and a second interconnect of the plurality of interconnects that is set to the second potential is connected to the second well and to a second diffusion layer of the two or more diffusion layers that is formed in the second well, and wherein a conduction type of the first diffusion layer is different from a conduction type of the second diffusion layer.