Patent ID: 6703902
Filing Date: 2004-03-09
Classification: H03C,H03L

Abstract:
A phase locked loop (PLL) for reducing electromagnetic interference (EMI) comprising:a pre-divider for generating a reference frequency signal by dividing the signal inputted to the PLL by a pre-defined value; a phase detector for receiving the reference frequency signal and a feedback signal, detecting the phase difference between the two signals, generating a control signal depending on the detected phase difference and outputting a control voltage generated as a result of processing of the control signal by a pre-defined process; a voltage controlled oscillator (VCO) for receiving the control voltage and multiple switching control signals, and outputting a first oscillation signal having a pre-defined frequency in response to the control voltage while outputting a second oscillation signal which is delayed by as much as n-times (where n is an integer) the basic delay time of the first oscillation signal, in response to the multiple switching control signals; a main divider for receiving the second oscillation signal and outputting the feedback signal that commands the increase or decrease of the frequency of the first oscillation signal; a modulation control block for receiving modulation frequency data, modulation rate data, the feedback signal, and the second oscillation signal, and outputting the multiple switching control signals; and a post-divider for receiving the first oscillation signal and outputting signals by dividing the first oscillation signal by a pre-defined value.