Patent ID: 9110126
Filing Date: 2015-08-18
Classification: G01R,H01L

Abstract:
1. A method for measuring the interface condition density, wherein, the method is applied by a conductance technique, the method comprises the steps of: biasing a MOS capacitor structure to be measured in an accumulation condition, measuring the MOS capacitor structure under a fixed bias voltage and at predetermined scanning frequencies in the accumulation condition by using a Gp-G model, wherein, the Gp-G model is formed by connecting in series an accumulation capacitance Cox and a resistor Rs and is equivalent with a measurement model; the measurement model is formed by connecting in parallel a measurement capacitor Cm and a measurement resistor Gm; and calculating the values of the series resistor Rs at respective predetermined scanning frequencies to obtain a series resistor model varying with the predetermined scanning frequencies; wherein, the value of the series resistor Rs is obtained according to the measurement model and the Gp-G model as follows: wherein Z m is the impedance value of the measurement model, and Z accumulation is the impedance value of the Gp-G model; obtaining an accurate model in an inversion condition from the series resistor model, wherein, the accurate model in the inversion condition is formed by connecting the parallel connection of the depletion capacitance Cc and the depletion resistor Gc in series with the series resistor Rs, wherein the depletion capacitance Cc and the depletion resistor Gc are calculated according to the following equations respectively: obtaining measurement results of interface condition according to the accurate model.