Patent ID: 6795442
Filing Date: 2004-09-21
Classification: H04L

Abstract:
A system comprising:source and destination devices interconnected by a network including at least one communication link, the source device being operable to transmit message packets over one or more virtual circuits established over the network to the destination device, the destination device being operable to receive the message packets thereover, A. the source device comprising a transmit section that comprises a transmitter and a transmit scheduler, the transmitter being configured to transmit message packets for the respective virtual circuits for the source device, and the transmit scheduler being configured to schedule transmission of message packets by the transmitter so that messages are transmitted in a round-robin manner as among ones of the virtual circuits; and B. comprising (a) a receive buffer operable to store linked lists of data from received message packets, each linked list corresponding to a specific virtual circuit, (b) a memory, (c) a receive host operable to transfer data from the receive buffer to the memory of the destination device and (d) a receive scheduler, configured to schedule high priority virtual circuits in a round-robin manner and low priority virtual circuits in a round-robin manner for the receive host to transfer data from the receive buffer to the memory.