Patent ID: 6567298
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of storage cells for storing data by storing charge in capacitive elements, with a first terminal of each of the capacitive elements in the plurality of storage cells being connected to a common reference terminal, and the charge being stored by being injected into and released from a second terminal of each of the capacitive elements; potential fluctuation suppression capacitive elements connected to the reference terminal, for suppressing a potential fluctuation associated with the charge injected from each of the capacitive elements by capacitive coupling when the charge is injected into or released from the second terminal of each of the capacitive elements; capacitive connection switch elements for connecting the reference terminal with the potential fluctuation suppression capacitive elements; and a power supply detection circuit for detecting the input of a power supply voltage, wherein the capacitive connection switch elements are brought into conduction to electrically connect the reference terminal with the potential fluctuation suppression capacitive elements during a predetermined time period after the detection by the power supply detection circuit.