Patent ID: 9184285
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a first conduction type drain layer formed in the semiconductor substrate and situated at a lower face of the semiconductor device; a second conduction type base layer formed in the semiconductor substrate and situated above the drain layer; a plurality of trenches formed in the base layer; a gate insulating film formed on an inner wall of each of the trenches; a gate electrode buried in each of the trenches; a first conduction type source layer formed in the base layer to a depth less than a lower surface of the base layer and situated between each of the trenches; a second conduction type high concentration layer formed in the base layer to a depth less than a lower surface of the base layer and greater than the depth of the source layer between the source layer and the trench, coupled to the base layer, and having a higher concentration of dopant than that of the base layer, an interlayer insulating film overlying the base layer and the plurality of trenches; a source electrode overlying the interlayer insulating film; and a plurality of contacts buried in the interlayer insulating film coupling the source electrode with the source layer and the second conduction type high concentration layer, wherein the trench, the source layer, and the second conduction type high concentration layer are arranged in this order repetitively in plan view, and one lateral side of the trench faces the source layer and another lateral side of the trench faces the second conduction type high concentration layer, and the base layer is located between immediately adjacent trenches, is L-shaped, and directly contacts sidewalls of the immediately adjacent trenches.