Patent ID: 7216328
Filing Date: 2007-05-08
Classification: G06F

Abstract:
1. An interface for integrating hardware system component cores used for customizing a FPGA-based SoC, the interface comprising: a slave connection circuitry communicatively interfaced to a processor bus; a master connection circuitry communicatively interfaced to said processor bus; wherein the slave connection circuitry is coupled between the processor bus and a selected hardware system component core, and the master connection circuitry is coupled between the processor bus and the selected hardware system component core; a multiplexer for selecting one of said slave connection circuitry and said master connection circuitry for providing communication between a processor bus and a selected hardware system component core used for customizing the FPGA-based SoC; and wherein the multiplexer is coupled between the slave connection circuitry and the selected hardware system component core and is coupled between the master connection circuitry and the selected hardware system component core.