Patent ID: 6032264
Filing Date: 2000-02-29
Classification: G11C

Abstract:
A memory comprising:a memory array addressable with row and column addresses;a row counter connected to supply row addresses to the memory array;a column counter connected to supply column addresses to the memory array;control circuitry coupled to the row counter and the column counter;failure detection circuitry for detecting errors during memory access, the failure detection circuitry being coupled to the memory array and the control circuitry;a failure counter coupled to the failure detection circuitry and the control circuitry to maintain a count of errors for a column or row; andrepair circuitry coupled to the control circuitry and the memory array and controlled by the control circuitry;wherein the control circuitry is configured to operate the row and column counters to access memory elements in the memory array in a predetermined column order and in a predetermined row order and to cause the repair circuitry to substitute a column or row in the memory array with a respective redundant column or row in the memory array when the failure counter reaches a predetermined threshold for a column or row, said control circuitry being configured to cause the repair circuitry to substitute the redundant column or row prior to subsequent columns or rows being accessed.