Patent ID: 6765413
Filing Date: 2004-07-20
Classification: G11C

Abstract:
A bus circuit comprising:a plurality of substantially parallel signal lines for transmitting data thereon, each signal line including one or more bi-directional inverting repeaters, each bi-directional inverting repeater connected between first and second connection nodes on one of the signal lines, wherein each bi-directional inverting repeater receives a first signal from the first connection node and outputs a logically inverted signal of the first signal to the second connection node in a first direction data transmission, and receives a second signal from the second connection node and outputs a logically inverted signal of the second signal to the first connection node in a second direction data transmission, the bi-directional inverting repeaters are positioned on each signal line such that data transmitted on each signal line and data transmitted on the signal line adjacent to said each signal line are in opposite phase on approximately one-half of the signal line, and the signal lines are divided into alternating even-numbered signal lines and odd-numbered signal lines, and the bi-directional inverting repeaters of the even-numbered signal lines are substantially offset with respect to the bi-directional inverting repeaters of the odd-numbered signal lines along a length of the signal lines.