Patent ID: 7437400
Filing Date: 2008-10-14
Classification: G06F

Abstract:
1. A data processing apparatus for adding n-bit significands of first and second floating point operands to produce an n-bit result, the data processing apparatus comprising: determination logic operable to determine which of the first and second floating point operands is the larger operand; first adder logic operable, if predetermined criteria exists, to perform an addition of the n-bit significands of the first and second floating point operands to produce a sum value; second adder logic operable, if said predetermined criteria does not exist, to perform an addition of the n-bit significands of the first and second floating point operands; and result logic operable to derive the n-bit result from either an output of the first adder logic or an output of the second adder logic; if the addition is a like-signed addition, said predetermined criteria being determined to exist for a set of situations where the sum value produced by the first adder logic will require an effective one-bit right shift to normalise the sum value; and if the addition is an unlike-signed addition, said predetermined criteria being determined to exist for a set of situations where the sum value produced by the first adder logic will require at least an effective one-bit left shift to normalise the sum value.