Patent ID: 6979996
Filing Date: 2005-12-27
Classification: G01R

Abstract:
1. An apparatus for eliminating time delay errors during automatic testing of electronics, using automatic test equipment comprising: device interface board wiring having a device interface board signal time delay; a device socket connected to said device interface board wiring, having a device socket signal time delay; first channel and second channel pin electronics wiring connected to said device interface board wiring, having pin electronics signal time delays; a first channel including a set of driver electronics, said set of driver electronics including inputs for receiving drive data, drive timing edge source data, and a first channel output, said first channel output transmitting information to a device under test through said first channel pin electronics, said device interface board wiring, and said device socket; a second channel having a set of receiver electronics, said set of receiver electronics including inputs for comparison data source information, comparison timing edge source information, and an output from said device under test; and a compiler to automatically route said drive timing edge source data, signal levels, and data to said first channel, and said comparison timing edge source information, signal levels, and data to said second channel; said first and second channels separate and distinct from one another and compensating for time delay errors when said device under test is electronically exercised.