Patent ID: 8818785
Filing Date: 2014-08-26
Classification: G06F

Abstract:
1. A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode, comprising: receiving a first netlist having an entry for the tucked transistor device in a computing apparatus, the entry defining parameters associated with the gate electrode and the diffusion region; and adding a parasitic capacitance component to the entry in the computing apparatus, the parasitic capacitance component representing a gate capacitance between the floating gate and the diffusion region, wherein adding the parasitic capacitance component comprises generating a first value for the parasitic capacitance component based on a first capacitance of the floating gate electrode present in an initial portion of an operating range of the tucked transistor device and generating a second value for the parasitic capacitance component based on a capacitance of the floating gate electrode present in an inversion region of an operating range of the tucked transistor device; generating the first netlist based on the first value; generating a second netlist based on the second value; simulating operation of the tucked transistor device using a transistor device model and the first netlist to generate a first simulation result; and simulating operation of the tucked transistor device using the transistor device model and the second netlist to generate a second simulation result.