Patent ID: 7243172
Filing Date: 2007-07-10
Classification: G06F

Abstract:
1. In an integrated circuit multiprocessor switching device, an apparatus for transferring data from a first bus to a memory bus, comprising: a first interface circuit for receiving packet data for a plurality of channels and transferring the packet data on the plurality of channels to a first bus having a first data width; a memory bus having a second data width that is larger than the first data width; a packet manager circuit coupled between the first bus and the memory bus to transfer data from each of a plurality of channels received from the first interface circuit to memory under control of a corresponding plurality of descriptors, said packet manager circuit comprising, an input buffer coupled to the first bus, comprising a buffer region for each of the plurality of channels; an alignment circuit coupled to the input buffer for shifting data stored in the input buffer to output shifted data; a data merge circuit coupled to the alignment circuit to store in a fragment storage register the shifted data from the alignment circuit that is not written to memory in a first data cycle, said data merge circuit combining data stored in the fragment storage register with data stored in the input buffer in a second data cycle to form a merged data value that is written to the memory bus; and a controller for controlling the shifting of data in the alignment circuit in response to an offset contained in a corresponding descriptor and for writing the shifted data to the memory bus.