Patent ID: 6457124
Filing Date: 2002-09-24
Classification: G06F

Abstract:
A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer;the integrated circuit chip including: an on-chip CPU with a plurality of registers; a communication bus for addressing a plurality of devices assigned to a single memory address space of the CPU and providing a parallel communication path between the CPU and a first memory local to the CPU; an address memory for storing the assignment of addresses to the plurality of devices; and an external communication port connected to the communication bus, the port having an internal connection to the communication bus of an internal parallel signal format and an external connection to the external computer of an external signal format less parallel than the internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby the port can be addressed by execution of an instruction by the CPU; wherein the external computer includes a second memory local to the external computer, which is accessible by the CPU through the port; and wherein the computer system includes address diversion means for reconfiguring the memory address space of the CPU so as to assign to the port memory addresses of another one of the plurality of devices.