Patent ID: 7169676
Filing Date: 2007-01-30
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising the steps of: forming a polycrystalline silicon gate electrode overlying a surface of a silicon substrate, said gate electrode having a first side and a second side; forming an impurity doped region in said silicon substrate in self alignment with said gate electrode; forming a first spacer on said first side and a second spacer on said second side; implanting an impurity ion selectively into said first spacer with an angle greater than zero from an axis perpendicular to said surface of said silicon substrate; etching said ion implanted first spacer to remove a portion thereof; depositing a silicon film overlying a remainder of said first spacer, said impurity doped region, and said second spacer; anisotropically etching said silicon film to form a first silicon spacer disposed proximate to said first side of said gate electrode; exposing a portion of said gate electrode and at least a portion of said impurity doped region; and depositing a silicide-forming metal on said exposed portion of said gate electrode, said at least a portion of said impurity doped region, and said first silicon spacer to form a silicide contact that electrically couples said gate electrode and said impurity doped region.