Patent ID: 8312397
Filing Date: 2012-11-13
Classification: G06F,H01L,Y02P

Abstract:
1. A layout pattern generating apparatus comprising: a net list configured to store connection data in a semiconductor device; a cell library in which pattern data of a plurality of cells including rework cells and fill cells are stored; a display unit; and a layout pattern generating and editing section configured to arrange said pattern data of the plurality of cells, including the rework cells and the fill cells, in a semiconductor chip area, based on said connection data, to display on said display unit, to calculate a distribution of wiring occupation rates in the semiconductor chip area and an average of the wiring occupation rates, and to generate a layout pattern in which a dummy wiring pattern is arranged in a wiring layer, based on the distribution and the average of the wiring occupation rates, wherein said layout pattern generating and editing section generates a new layout pattern by deleting said dummy wiring pattern, specifying a specific rework cell among arranged rework cells, generating a specific pattern of a predetermined shape in the wiring layer of said specific rework cell of the new layout pattern, arranging a new dummy wiring pattern in at least a part of said wiring layer of un-specific rework cells of said rework cells other than said specific rework cell and said fill cells, deleting said specific pattern from the wiring layer of said specific rework cell, arranging said specific rework cell as a logic cell, and arranging a wiring pattern in said wiring layer of said specific rework cell, when a part of the arranged rework cells is used as the logic cell.