Patent ID: 7373621
Filing Date: 2008-05-13
Classification: G01R,G06F

Abstract:
1. A method for using a programmable logic device test generation tool to generate test configuration data and test vectors for testing a programmable logic device integrated circuit, comprising: generating a graph of the programmable logic device integrated circuit with the programmable logic device test generation tool; using the programmable logic device test generation tool to automatically extract multiple testable subgraphs from the graph in separate processing sessions; processing each extracted testable subgraph in a separate processing session with the programmable logic device test generation tool to produce a corresponding set of test configuration data and test vectors for testing the programmable logic device, wherein the graph and the extracted testable subgraphs contain nodes and edges and wherein the edges represent programmable connections in the programmable logic device integrated circuit; and during each procession session, using a cost function to determine which portion of the extracted testable subgraph is to be processed, wherein using the cost function comprises incrementing a cost function threshold in successive processing iterations to selectively increase the portion of the extracted testable subgraph that is processed.