Patent ID: 7026667
Filing Date: 2006-04-11
Classification: G06F

Abstract:
1. A semiconductor integrated circuit device comprising: a clock signal transmission line including a plurality of straight portions arranged side by side with their longitudinal directions approximately in parallel with each other and forming a path from a point on the line via said plurality of straight portions one after another along their longitudinal directions to reach another point on the line; a plurality of storage circuits operating in synchronization with a clock signal; and a plurality of signal lines each connected to said clock signal transmission line to supply said clock signal to at least one of said plurality of storage circuits; said clock signal transmission line including at least one portion located between two of said plurality of straight portions through which the clock signal having been transmitted on one of said plurality of straight portions in one direction along the longitudinal direction is guided such that the same clock signal is transmitted on succeeding one of said straight portions in the opposite direction along the longitudinal direction, and said plurality of signal lines including a first signal line connected to a first straight portion among said plurality of straight portions and a second signal line connected to a second straight portion, that is different from said first straight portion, among said plurality of straight portions.