Patent ID: 8324666
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A semiconductor integrated circuit apparatus, comprising: a substrate comprising a surface region; a well structure within the substrate; a first region within the well structure, the first region being characterized by impurities for threshold voltage adjustment; a second region within the well structure, the second region being substantially free of impurities for threshold voltage adjustment; isolation regions within the well structure; a channel region within the first region; a gate dielectric layer overlying the channel region; a gate stack overlying the gate dielectric layer, the gate stack comprising a silicide layer overlying a polysilicon layer; LDD structures on sides of the channel region; spacers on sides of the gate stack; a source region and a drain region; and a contact structure over the source region, a junction between the contact structure and the source region being substantially within the second region.