Patent ID: 6199031
Filing Date: 2001-03-06
Classification: G06F

Abstract:
A system for testing and verifying an ASIC (application specific integrated circuit) design at different levels of abstraction, wherein the ASIC design includes a logic entity and a processor entity, the system comprising:a computer system including a processor coupled to a memory via a bus, the computer system operable for executing software, where the software causes the computer system to implement:a model of the ASIC design, the model embodied in HDL (hardware description language), the model including a logic entity and a processor entity;a simulator adapted to test the model; anda test interface for interfacing the model with the simulator, the test interface comprising:a simulator portion coupled to the simulator;a model portion coupled to the logic entity and the processor entity, the model portion and the simulator portion coupled to exchange information, the model portion embodied in HDL; andthe model portion operable to obtain a register status of the processor entity and provide the register status to the simulator via the simulator portion such that the register status is observable by the simulator as the model is simulated at different of levels of abstraction.