Patent ID: 6774037
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method of forming an integrated circuit comprising:forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate; forming a sacrificial hard mask on said dielectric layer; patterning a first photoresist layer on said sacrificial hard mask, to define a first etched region; forming said first etched region into said dielectric layer while simultaneously removing substantially all of said first photoresist layer; covering said sacrificial hard mask and filling said first etched region with a sacrificial fill layer; patterning a second photoresist layer over said sacrificial fill layer, to define a second etched region; and forming said second etched region into said sacrificial fill layer and said dielectric layer while simultaneously removing substantially all of said second photoresist layer and at least a portion of said sacrificial fill layer; and removing remaining portions of said sacrificial fill layer in said first etched region and said second etched region and over said sacrificial hard mask.