Patent ID: 6754743
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A FIFO buffer arrangement for temporarily buffering a data packet from an incoming data stream before releasing said data packet into an outgoing data stream, comprising a memory device, a write pointer register, a read pointer register, said data packet containing a plurality of bytes; said memory device comprising a write access port and a read access port, said write pointer register containing a write pointer; said read pointer register containing a read pointer; said write pointer being arranged to indicate a first location in said memory device, momentary available for storing said data packet; said read pointer being arranged to indicate a second location in said memory device, momentary available for releasing a stored data packet to the out-going data stream, said FIFO buffer arrangement comprises:a controller complex and additional memory, said controller complex being connected to said additional memory, to said memory device, and to said read pointer register, said additional memory being arranged to store at least one additional data packet, said controller complex being arranged to: continuously monitor the arrival of said at least one additional data packet in said additional memory; store a registered write pointer value each time at least one additional data packet arrives in said additional memory, said registered write pointer value having a predetermined relation with a momentary value of said write pointer at that time; continuously monitor a momentary value of said read pointer; check whether said read pointer has said predetermined relation with said registered write pointer value; if so, read said at least one additional data packet from said additional memory and insert said at least one additional data packet in said outgoing data stream; read content from said second location in said memory device and insert said content into said outgoing data stream.