Patent ID: 7038511
Filing Date: 2006-05-02
Classification: H03L

Abstract:
1. A method for compensating for variance from a relationship between a first delay and a second delay the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and second reference delay; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a signal indicative of the relationship between the first delay and the second delay; stabilizing the signal, the stabilized signal for use as the control signal for the adjustable delay; and adjusting in accordance with the stabilized signal a parameter affecting the relationship between the first delay and the second delay in response to the determined relationship being outside a variance range by setting a transition point at which a variable delay line having a plurality of first delay circuits and having a plurality of second delay circuits switches from a first delay circuit of the plurality to a second delay circuit of the plurality in accordance with the stabilized signal when the first and second delayed clock signals are in phase.