Patent ID: 6577259
Filing Date: 2003-06-10
Classification: H03M

Abstract:
A sigma-delta modulator for converting a digital input signal into a quantized output signal, comprising:a first-order sigma-delta modulator, comprising: a first adder receiving a modulator input signal and a first quantization error value, forming a first aggregate signal, a first delay circuit receiving the first aggregate signal and delaying the first aggregate signal by one clock unit, a decision circuit receiving the delayed first aggregate signal and outputting the quantized output signal, and a second adder receiving the delayed first aggregate signal from the first delay circuit and the quantized output signal and negating the quantized output signal, forming the first quantization error value; and a plurality of n parallelized branches, each branch receiving the digital input signal, a first branch of the n branches comprising the first-order sigma-delta modulator and outputting the quantized output signal and a first quantization error value, and each branch of the n branches, other than the first branch, comprising: a second delay circuit receiving the digital input signal and delaying the digital input signal by iâˆ’1 clock units, where 1a switch receiving, and temporally sampling, the delayed digital input signal, a third adder receiving the sampled signal and a second quantization error value from the preceding branch, forming a second aggregate signal, a multi-bit quantizer receiving the second aggregate signal from the third adder and outputting an output signal delayed by iâˆ’1 clock units, and a fourth adder receiving the output signal, negated, from the multi-bit quantizer and the second aggregate signal from the third adder, forming the second quantization error value.