Patent ID: 6502161
Filing Date: 2002-12-31
Classification: G06F,G11C,Y02D

Abstract:
A memory system comprising:a memory controller having an interface that includes a plurality of memory subsystem ports; a first memory subsystem including: a buffer device having a first port and a second port, and a plurality of memory devices coupled to the buffer device via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the memory controller via the buffer device; and a plurality of point-to-point links, each point-to-point link of the plurality of point-to-point links having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of point-to-point links including a first point-to-point link to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports.