Patent ID: 7855917
Filing Date: 2010-12-21
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a semiconductor layer; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer in an electrically floating state, and storing logic data based on a charge amount accumulated therein; a first gate dielectric film provided on a first surface of the body region; a first gate electrode provided on the first surface via the first gate dielectric film; a second gate dielectric film provided on a second surface of the body region different from the first surface; a second gate electrode provided on the second surface via the second gate dielectric film; a driver driving the first gate electrode and the second gate electrode; and a sense amplifier reading logic data from or writing logic data into memory cells including the source layer, the drain layer, and the body region, wherein the sense amplifier writes into the memory cells first logic data in a state that a voltage of the second gate electrode at a data writing time is brought closer to a potential of the source layer than a voltage of the second gate electrode at a data holding time, carriers in the body regions of the memory cells being discharged from the body regions during a writing operation of the first logic data.