Patent ID: 9100208
Filing Date: 2015-08-04
Classification: H04J,H04L

Abstract:
1. A multiservice access device, comprising: a synchronous network receiver for receiving synchronous network traffic; a plurality of network interface debuggers integral to the multiservice access device for generating messages related to the status of the synchronous network; a packet processor for processing the synchronous network traffic and messages into packetized synchronous network data for asynchronous transmission over an Ethernet network in a first bus format; a first bus translator for translating the first bus format into a second bus format; an Ethernet processor for receiving the packetized synchronous network data in the second bus format and asynchronously transmitting the packetized synchronous network data over Ethernet; a clock synchronizing device for receiving clock information from a plurality of devices and status information from the synchronous network receiver, the network interface debuggers, and the packet processor and determining a clock, and providing the clock to the synchronous network receiver, the network interface debuggers, and the packet processor; and a processor for managing the operation of the transceiver, the packet processor, and the Ethernet processor, wherein the processor sends and receives control information from the Ethernet processor on a third bus interface.