Patent ID: 6825058
Filing Date: 2004-11-30
Classification: G11C,H01L

Abstract:
A method of manufacturing a memory structure comprising:a) providing a semiconductor substrate; b) creating a doped well having a depth to define the memory area; c) employing a shallow trench isolation process to divide the doped well into a plurality of doped lines isolated from each other; d) forming a plurality of diodes by forming doped regions of the opposite polarity in contact with regions of the plurality of doped lines; e) depositing a bottom electrode overlying each doped region; f) depositing a layer of perovskite material overlying the bottom electrode; g) removing the layer of perovskite material from regions outside a memory array area, whereby the layer of perovskite material remains within the memory array area; and h) forming a plurality of top electrodes overlying the layer of perovskite material.