Patent ID: 7475310
Filing Date: 2009-01-06
Classification: G01R

Abstract:
1. A signal output circuit for outputting an output signal in accordance with a predetermined system timing, the signal output circuit comprising: a shift register that receives an input signal and delays the input signal in accordance with the system timing; a flip-flop that receives the input signal delayed by the shift register in response to a clock signal supplied thereto, and outputs the input signal as the output signal; and an initializing section that measures a delay amount achieved by the shift register and judges whether the measured delay amount is in accordance with the system timing, the initializing section including: an input section that inputs a reference signal into the shift register; a counting section that counts the number of pulses of the clock signal by using the reference signal as a trigger, and causes inputting of the clock signal into the flip-flop to be suspended when a value indicating a result of the counting reaches a value set in accordance with the system timing; a measuring section that measures a signal output from the flip-flop in a case where the inputting of the clock signal is suspended; and a judging section that judges whether the signal measured by the measuring section corresponds to the reference signal.