Patent ID: 6075564
Filing Date: 2000-06-13
Classification: H04N

Abstract:
A solid-state imaging apparatus comprising:a photosensitive pixel comprising:a photodiode for converting an input optical signal into a current signal; anda first switch having a first terminal connected to a signal output terminal of said photodiode and a second terminal for outputting the current signal generated in said photodiode, said first switch opening and closing according to a level of a charge readout instruction signal;a signal-converting circuit for outputting a digital signal corresponding to an amount of charge flowing therein due to said current signal received thereby, said signal-converting circuit comprising:an integrating, circuit which selectively performs a time quadrature operation of said current signal received from said photosensitive pixel and an initializing operation for the time quadrature operation and output signal so as to output a first voltage signal which selectively corresponds to the voltage signal of a result of time quadrature of said current signal and an initial level of voltage signal with reference to time, said integrating circuit selectively executing the time quadrature operation of said current signal and the initializing operation for the time quadrature operation and output signal according to a level of a reset instruction signal received thereby;a clamping circuit having a first input terminal for receiving said first voltage signal transmitted from said integrating circuit and a second input terminal for receiving comparative voltage signal, selectively executing a clamping operation and an operation for generating a voltage level corresponding to voltage levels of said first voltage signal and comparative voltage signal, and outputting a second voltage signal which selectively corresponds to the voltage level at the clamping operation and the voltage level corresponding to the voltage levels of said first voltage signal and comparative voltage signal with reference to time, said clamping circuit selectively executing said clamping operation and generating operation according to a level of a clamping instruction signal received;a second switch disposed between said integrating circuit and said clamping circuit, and having a first terminal connected to an output terminal of said integrating terminal and a second terminal connected to the first input terminal of said clamping circuit, said second switch opening and closing according to a level of a sampling instruction signal;a comparator circuit for receiving said second voltage signal outputted from said clamping circuit, comparing voltage levels of said second voltage signal and a first reference voltage in terms of magnitude, and outputting a comparison result signal corresponding to a result of comparison; anda data holding circuit for receiving a digital counter signal and said comparison result signal, holding the digital counter signal at a moment when said comparison result signal changes in a predetermined manner, and outputting thus held signal;a timing control section for outputting said charge readout instruction signal, said reset instruction signal, said sampling instruction signal, and said clamping instruction signal; anda comparison control section for outputting said digital counter signal with a predetermined period in which a digital value carried thereby changes and said comparative voltage signal whose voltage level changes over a predetermined duration.