Patent ID: 6576537
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A method for fabricating a memory cell on a substrate, wherein a gate stack having a tunneling dielectric, a first conductive layer and a cap layer is formed on the substrate, and the first conductive layer includes one layer selected from the group consisting of a polysilicon layer and an amorphous silicon layer, the method comprising:forming source/drain regions in the substrate adjacent to the gate stack; forming a plurality of spacers on sidewalls of the gate stack; selectively etching the substrate to form a trench using the spacers and the gate stack as a mask; forming a first dielectric material layer over the substrate to fill the trench; removing a top portion of the first dielectric material layer, wherein a remaining portion of the first dielectric material layer forms a plurality of isolation structures with a down set level from a top of the spacers; removing the cap layer; forming a patterned second conductive layer on the first conductive layer, wherein the patterned second conductive layer extends over a portion of the isolation structures; forming a second dielectric layer over the substrate; and forming a control gate over the second dielectric layer.