Patent ID: 6516362
Filing Date: 2003-02-04
Classification: G06F

Abstract:
A processor-based device adapted to communicate between multiple devices operating at different clock frequencies, the computer system comprising:a processor; a communications bus coupled to the processor; an internal device coupled to the communications bus to read information from the communications bus and to write information to the communications bus; a first clock signal for driving the internal device in a first clock frequency domain; an external device coupled to the communications bus to read information from the communications bus and to write information to the communications bus; a second clock signal for driving the external device in a second clock frequency domain, the second clock signal and the second clock frequency domain corresponding to a different frequency than the first clock signal and the first clock frequency domain; and a synchronization device coupled to the communications bus and driven by the second clock signal to synchronize information on the communications bus between the first clock frequency domain and the second clock frequency domain.