Patent ID: 7954102
Filing Date: 2011-05-31
Classification: G06F

Abstract:
1. A scheduling method in a multithreading processor including a plurality of context units, each of which comprises a program counter and an instruction buffer, the scheduling method comprising: allotting a plurality of executable threads respectively to a plurality of context; setting a fetch stall reference value, which is a threshold for the number of times of fetch stalls; fetching by a fetch unit, a next instruction from a cache memory at an address specified by the program counter, and storing the fetched next instruction in the instruction buffer for each of the plurality of context units; decoding by a decoding unit, next instructions stored in the instruction buffers of the plurality of context units; executing by an instruction execution unit, the decoded next instructions of the plurality of context units; recording in a fetch stall counter, the number of times of fetch stalls in a given period during the decoding by the decoding unit; and dynamically deciding the number of threads paired together for simultaneous execution according to the number of times of fetch stalls recorded in the fetch stall counter, so as to decrease the number of context units in execution within the plurality of context units corresponding to the decided number of threads when the recorded number of times of fetch stalls exceeds the fetch stall reference value, and to increase the number of context units in execution within the plurality of context units corresponding to the decided number of threads when the recorded number of times of fetch stalls does not exceed the fetch stall reference value.