Patent ID: 7716442
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. Apparatus comprising multiple data devices and a bus arbiter controlling access by the devices to an external memory via an interface, wherein the external memory comprises multiple read registers, each of which supports burst-mode access by a corresponding data device, with the bus arbiter selecting one of the multiple read registers to be used following an initial access burst according to the identity of the data device requiring access, interrupting burst-mode access by one device to allow burst-mode access by another device according to predetermined priorities associated with said devices, and resuming the burst-mode access by the one device, wherein the initial access burst by the one device is longer than an immediate subsequent access burst by the one device, and when burst-mode access by the one device is resumed after being interrupted by the burst-mode access by the another device, the burst-mode access by the one device has a same period as the immediate subsequent access burst by the one device.