Patent ID: 6812111
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method for fabricating a MOS transistor, comprising:forming a multi-layered insulation layer, including at least two insulation layers, on a substrate; patterning the multi-layered insulation layer to form an opening exposing a predetermined region of the substrate, wherein the opening has a stair-shaped sidewall such that an upper portion of the opening is wider than a lower portion of the opening; forming a gate insulation layer on the exposed substrate; forming a gate electrode filling the opening on the gate insulation layer; removing the multi-layered insulation layer to form a gate electrode having a notch region under an edge portion thereof, the multi-layered insulation layer being removed from the notch region; and following removing the multi-layered insulation layer, forming source and drain regions in the substrate using the gate electrode having the notch region as an ion implantation mask.