Patent ID: 6731443
Filing Date: 2004-05-04
Classification: G11B

Abstract:
An integrated circuit for optimizing a bit-error rate of a read/write channel coupled with a hard disk drive, the integrated circuit comprising:a bit pattern generator circuit operative to generate a digital signal having a selected pattern at a bit pattern generator output; a first summing circuit having a first input, a second input, and an output, the first input being coupled with the bit pattern generator output and being operative to receive the digital signal having a selected pattern, the second input being operative to receive a processed binary data signal representing data read from a magnetic data storage medium, the summing circuit being operative to generate an interference signal at the first summing circuit output, the interference signal representing a difference between the digital signal provided at the first input and the processed binary data signal at the second input; a scaling circuit having an input coupled with the output for the first summing circuit and operative to receive the interference signal, the scaling circuit being operative to generate a scaled interference signal at the scaling circuit output; and a second summing circuit having a first input, a second input, and an output, the first input being coupled with the scaling circuit output and operative to receive the scaled interference signal, the second input coupled with the bit pattern generator output and operative to receive the digital signal, the second summing circuit being operative to combine the digital signal and the scaled interference signal, the combined signals being provided at the second summing circuit output.