Patent ID: 7432739
Filing Date: 2008-10-07
Classification: H03K

Abstract:
1. A low voltage CMOS (Complementary Metal Oxide Semiconductor) process tri-state buffer applied to a low voltage CMOS process integrated circuit, the tri-state buffer receiving an enable signal and having an output terminal, the output terminal being held in a high impedance state when the enable signal is disabled, the tri-state buffer comprising: a logic device configured to receive an input signal and the enable signal, and generate a first control signal and a second control signal according to the input signal and the enable signal, the logic device including: a biasing device configured to receive the first control signal, control a voltage level of a third control signal according to the first control signal, and output the third control signal; a switch device configured to receive the second control signal and the third control signal and coupling the output terminal to a first external voltage source and a second external voltage source when the second control signal and the third control signal are enabled, thereby to make a voltage level of the output terminal equal to a voltage level of the first external voltage source and a voltage level of the second external voltage source, respectively; and a discharge device configured to receive the first control signal and the third control signal and discharge the third control signal according to the first control signal, thereby to shorten a voltage level falling time of the third control signal, wherein when the enable signal is disabled, the second control signal and the third control signal are disabled to make the output terminal float with respect to the first external voltage source and the second external voltage source and to hold the output terminal in a high impedance state.