Patent ID: 6780761
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A via-first dual damascene process, comprising:providing a semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate, wherein the dielectric layer has a via opening exposing the conductive structure; filling the via opening with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer; etching the GFP layer back to a depth such that an exposed surface of the GFP layer in lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening; and performing a surface treatment for altering surface property of the sidewalls and the exposed surface of the GFP layer, thereby preventing a subsequent deep UV photoresist from interacting with the sidewalls or the exposed surface of the GFP layer either in a chemical or physical way, wherein the surface treatment is using active radicals having a relatively low etching rate (with respect to the GFP layer) to contact the sidewalls and the exposed surface of the GFP layer.