Patent ID: 6181631
Filing Date: 2001-01-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:plural memory cell arrays,an address buffers for outputting address data,address decoders, which are respectively combined with said plural memory cell arrays, select memory cells in said memory cell array in accordance with said address data and read data stored therein,amplifiers, which respectively amplify said data and output amplified results as output data,activation circuits, which respectively output activation signals for activating said amplifiers, andan output circuit for outputting said output data to an external circuit,wherein said plural memory cell arrays, said address buffer, said address decoders, said amplifiers, said activation circuits and said output circuit are respectively formed on a same semiconductor chip; and a length of a wiring between said address decoder combined with said memory cell array remote from said output circuit and said address buffer is shorter than that between said address decoder combined with said memory cell array near said output circuit and said address buffer.