Patent ID: 6751745
Filing Date: 2004-06-15
Classification: H04L

Abstract:
A digital synchronization circuit comprising:a clock generation circuit for generating a plurality of clock signals having substantially a same frequency and having different phases; a selection circuit for selectively outputting corresponding one of said plurality of clock signals in accordance with a first selection signal; a clock determination circuit for sampling an input data signal using said plurality of clock signals and selecting one of said plurality of clock signals based on said sampled result for outputting a second selection signal indicating the selection result; and a selection control circuit for adjusting a timing of said second selection signal changes for outputting said first selection signal, said selection control circuit changing a value of said first selection signal from a first value to a second value in a period in which a potential of a clock signal represented by said first value and a potential of a clock signal represented by said second value are the same in response to a change in value of said second selection signal from said first value to said second value, wherein said selection control circuit includes: a clock selection circuit for selectively outputting said clock signal represented by the value of said second selection signal of said plurality of clock signals, and a latch circuit for latching said second selection signal for outputting said first selection signal in accordance with an output from said clock selection circuit.