Patent ID: 8417889
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A method implemented by a processing node comprising: identifying a disabled processing core and an active processing core from a plurality of processing cores included in the processing node, wherein each of the plurality of processing cores is assigned a cache memory; extending a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core, wherein the cache memory assigned to the active processing core is a first level cache tier in a plurality of cache tiers and the cache memory assigned to the disabled processing core is a second level cache tier in the plurality of cache tiers; storing a first plurality of data processed by the active processing core to the cache memory assigned to the active processing core; and using the extended memory map, storing a second plurality of data processed by the active processing core to the cache memory assigned to the inactive processing core, wherein the second plurality of data is different than the first plurality of data.