Patent ID: 7283391
Filing Date: 2007-10-16
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance regulating circuit for changing a resistance value to reduce or eliminate a difference in bit line load resistance depending on a position of the memory element; wherein the load resistance regulating circuit is a load resistance switching circuit having a plurality of resistance elements and a resistance element selecting means for selecting at least one of the plurality of resistance elements, the bit line is one of a plurality of bit lines arranged in parallel to one another, each of the bit lines comprises a first bit line, a second bit line connected to the first bit line, and a third bit line connected to an end of the second bit line via a bit line selecting element, and the third bit line connected to the load resistance regulating circuit, and each of the plurality of memory elements has two driving terminals connected to corresponding first bit lines adjacently located.