Patent ID: 7012313
Filing Date: 2006-03-14
Classification: H01L

Abstract:
1. A MOS transistor in a single-transistor memory cell, comprising: a semiconductor substrate having a substrate surface, a first conductive region and a second conductive region; a gate oxide disposed on said substrate surface; a gate disposed on said gate oxide over an area between said first conductive region and said second conductive region and having side walls adjacent respective ones of said conductive regions and forming a vertical portion of a step said gate including a tungsten silicide layer and a polysilicon layer; a silicon oxide passivation layer disposed on said side walls of said gate; and an insulating silicon nitride spacer disposed on said silicon oxide passivation layer as a substantially straight vertical layer lining said vertical portion of said step said spacer acting as an oxidation barrier; said gate oxide insulating said gate from said semiconductor substrate and having a thickened area in a region below at least one of said side walls adjacent said conductive regions.