Patent ID: 6925534
Filing Date: 2005-08-02
Classification: G06F

Abstract:
1. An apparatus, comprising: an array of tag address storage locations; and a command sequencer and serializer unit coupled to the array of tag address storage locations, the command sequencer and serializer unit to control a data cache located on a memory module via a plurality of command lines and address lines over an interconnect, the command sequencer and serializer unit to cause a current line of data to be read out from a first location of a memory module memory device and to load a next line of data from a second location of the memory module memory device to the data cache, in response to a single command having a plurality of segments serialized and sequentially transmitted via the plurality of address lines and command lines over the interconnect within a single memory access transaction, wherein the single command includes at least one of memory module destination information, cache way information, address strobe state information, cache hit information, column address information, and memory device bank information, wherein the single command is delivered over a plurality of transfer periods within a single memory access transaction, and wherein the cache hit information and cache way information is transferred during a last transfer period of the transfer periods.