Patent ID: 6741195
Filing Date: 2004-05-25
Classification: H03M

Abstract:
A DAC circuit comprising:a reference input transistor; a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output; and an output current mirror having an input coupled to the combined current source output, the output mirror comprising: an input transistor having a first gate electrode, a first drain coupled to the first gate electrode, and a first source; a first output transistor having a second gate electrode coupled to the first gate electrode and to the combined current source output, a second drain, and a second source coupled to the first source, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion of an input current passed between the first drain and the first source; a third transistor scaled to match the input transistor and having a third gate electrode coupled to the first gate electrode, a third drain, and a third source coupled to the first source; a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain, and a fourth source; a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode coupled to the fourth gate electrode and to the fourth drain, a fifth drain and a fifth source coupled to the fourth source; a sixth transistor having a sixth gate electrode coupled to the second drain, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source; a second output transistor having a seventh gate electrode coupled to the sixth drain, a seventh drain and a seventh source coupled to the second drain.