Patent ID: 8095718
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. A bridge for connecting a processor unit and a peripheral device, comprising: a downstream port connected to the peripheral device; and a router operative to route access from the peripheral device to a memory of the processor unit via the downstream port, to upstream channels each assigned a memory bandwidth available for access to the memory of the processor unit, the upstream channels being virtual channels supported by the processor unit, wherein the downstream port supports a plurality of downstream channels used for the access by the peripheral device, the downstream channels being virtual channels provided for interfacing with the peripheral device, and the router is provided with a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other, and refers to the table so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.