Patent ID: 6436747
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of fabricating a semiconductor device having a silicidation region and a non-silicidation region, wherein a MOS transistor comprising a gate electrode and heavily doped source/drain regions each having a silicided upper portion is disposed in the silicidation region, while an element comprising a polysilicon member having a non-silicided upper portion is disposed in the non-silicidation region, the method comprising the steps of:(a) forming a gate insulating film and a polysilicon film on a semiconductor substrate; (b) implanting ions of an n-type impurity for resistance reduction into a portion of the polysilicon film by using a mask having an opening corresponding to an n-type impurity implantation region; (c) performing a first heat treatment for activating the n-type impurity; (d) after the step (c), implanting ions of a p-type impurity for resistance reduction into another portion of the polysilicon film by using a mask having an opening corresponding to a p-type impurity implantation region; (e) after the step (d), patterning the polysilicon film to form a gate electrode of the MOS transistor in the silicidation region and the polysilicon member in the non-silicidation region; (f) implanting impurity ions for forming the heavily doped source/drain regions of the MOS transistor; (g) after the step (f), forming an insulating film on the substrate; (h) forming a selective etching mask on the insulating film; (i) patterning the insulating film by using the selective etching mask to form a silicidation mask, the mask covering the non-silicidation region and having an opening over the silicidation region; (j) after the step (i), performing a second heat treatment for activating the p-type impurity; (k) after the step (j), implanting impurity ions for promoting silicidation into the gate electrode and heavily doped source/drain regions of the MOS transistor in the silicidation region; and (l) after the step (k), siliciding the respective upper portions of the gate electrode and heavily doped source/drain regions of the MOS transistor in the silicidation region.