Patent ID: 6901529
Filing Date: 2005-05-31
Classification: G06F

Abstract:
1. A timer apparatus comprising: a counter; a register, provided in correspondence to said counter, for writing an operation command to said counter, and a distribution writing circuit for writing said operation command at a bit position corresponding to said counter of a bit train into said register and for simultaneously writing an operation command into a further register of at least one further timer apparatus that additionally includes a further counter corresponding to the further register, in order to control operations of said counters when receiving said bit train, which consist of a plurality of continuous bits to which one address information has been added and in which each of said bits indicates the operation command to said counter corresponding to each bit position, wherein operation commands to said timer apparatus and said at least one further timer apparatus can be simultaneously written into the register of each timer apparatus, and additionally, operation commands to the counters to which address information peculiar to each timer apparatus has been given can be sequentially written into the register of each timer apparatus.