Patent ID: 7102359
Filing Date: 2006-09-05
Classification: G01R

Abstract:
1. A fault detector circuit comprising: a high current switch having a first and second terminals; a floating current source; a first current mirror configuration, the first current mirror configuration and the floating current source being coupled in series between the first and second terminals of the high current switch; a second current mirror configuration coupled to the first current mirror configuration, wherein a current flowing through the floating current source is mirrored by the first current mirror configuration to the second current mirror configuration, further wherein the current contains information concerning one of a normal load, an open load, or a shorted load condition on the high current switch; and a Schmitt trigger having an input and an output, wherein the second current mirror configuration is coupled to the input of the Schmitt trigger and wherein the Schmitt trigger output is representative of one of a faulted state or an un-faulted state, as a function of one of the normal load condition, the open load condition, or the shorted load condition on the high current switch.