Patent ID: 8975739
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. An electronic device package structure, comprising: a substrate; an electronic chip positioned on the substrate; a boding pad sandwiched between the substrate and the electronic chip, and electrically connected to the electronic chip; a first passivation layer sandwiched between the substrate and the bonding pad; a conductive layer positioned on a sidewall of the electronic chip and electrically connected to the bonding pad, the conductive layer comprising a first side end and a second side end opposite to the first side end, wherein the bottom surface of the second side end contacts the first passivation layer; a second passivation layer positioned on the conductive layer, exposing the first side end of the conductive layer and covering the second side end of the conductive layer, wherein the second passivation layer simultaneously contacts the top surface and a sidewall of the conductive layer, and completely covers the second side end of the conductive layer with the first passivation layer; and a solder ball positioned on the exposed first side end of the conductive layer.