Patent ID: 8101951
Filing Date: 2012-01-24
Classification: G02F,H01L

Abstract:
1. A pixel structure comprising: a substrate with a thin film transistor region, a scanning line region, a data line region, a pixel region and a capacitance region; an active layer, wherein a portion thereof is formed on the substrate in the thin film transistor region; an insulating layer formed on the substrate; a first patterned dielectric layer formed above the substrate and having a plurality of first openings being adapted to individually expose the insulating layer in portions of the thin film transistor region, the scanning line region and the capacitance region; a first patterned conductor structure formed on the exposed insulating layer in the thin film transistor region, the scanning line region, and the capacitance region; a second patterned dielectric layer formed above the substrate; a second patterned conductor structure formed on the second patterned dielectric layer in the data line region, on the second patterned dielectric layer in a portion of the thin film transistor region, and on the second patterned dielectric layer connecting to the active layer and the capacitance region; a patterned protective layer formed above the substrate; and a patterned pixel electrode formed on the patterned protective layer in the pixel region, and connecting to the second patterned conductor structure in the thin film transistor region.