Patent ID: 7118952
Filing Date: 2006-10-10
Classification: H01L

Abstract:
1. A method of fabricating a transistor, comprising the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing; forming a first spacer adjacent to the gate electrode; forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed-after forming the first spacer; epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing to fill the recesses up to a surface of the substrate, wherein the transistor is a PMOS transistor, the PMOS transistor is a component in a CMOS device, and an NMOS transistor of the CMOS device is formed without growing the second semiconductor material in source and drain regions of the NMOS device; implanting a dopant in the second semiconductor material after the growing step; and removing the first spacer after the implantation step.