Patent ID: 6548374
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A method for self-aligned shallow trench isolation comprising:forming a first oxide layer on a semiconductor substrate; forming a first conductive layer on said first oxide layer; forming a nitride layer on said first conductive layer; forming a second oxide layer on said nitride layer; forming an anti-reflective layer on said second oxide layer; etching said anti-reflective layer, said second oxide layer, said nitride layer, said first conductive layer and said first oxide layer using a single mask, to thereby form a first oxide layer pattern, a first conductive layer pattern, a nitride layer pattern, a second oxide layer pattern and an anti-reflective layer pattern; etching the upper portion of said substrate adjacent to said first conductive layer pattern by using said mask, to thereby form a trench and to simultaneously remove said anti-reflective layer pattern; forming a trench inner-wall oxide layer on the inner surface of said trench by chemical vapor deposition (CVD) to prevent the formation of a positive profile at sidewalls of said first conductive layer pattern; annealing said trench inner-wall oxide layer in one of an N2O and NO atmosphere to form an oxynitride layer at the interface between said substrate and said trench inner-wall oxide layer; and forming a field oxide layer for filling up the trench.