Patent ID: 6035118
Filing Date: 2000-03-07
Classification: G06F

Abstract:
A system for reducing the time delay associated with executing a computed jump instruction in a pipelined microprocessor, where the computed jump instruction redirects instruction fetching to a computed target instruction address computed by a target instruction address computation instruction executed prior to the computed jump instruction, and where the computed target instruction address, calculated by the target address calculation instruction, is stored in an addressable storage location, said system comprising:a return address stack, having a top location for holding a return address;an execution pipeline having a plurality of stages including:an instruction cache for storing instructions to be fetched by an instruction execution pipeline, with the identity of an instruction stored indicated by an instruction address provided to the instruction cache;an instruction fetch stage for fetching an instruction from said instruction cache, where the identity of an instruction to be fetched is indicated by an instruction address provided to said instruction cache by said instruction fetch stage, and where said instruction fetch stage always provides an address stored at the top of the return address stack to fetch a next instruction after a computed jump instruction is fetched; andan execution unit for executing said instruction address computation instruction to compute a computed target instruction address and store the computed target instruction address in the first addressable storage location, with the execution unit for executing a designated instruction for moving said computed target instruction address from the first addressable storage location to the to the top of the return address stack and to assert a signal indicating that the computed target instruction address has been stored, and for subsequently executing a computed jump instruction to redirect program execution as indicated by said computed target instruction address stored at the top of the return address stack, so that bubbles in the pipeline subsequent to the computed jump instruction are eliminated.