Patent ID: 7800417
Filing Date: 2010-09-21
Classification: H03K

Abstract:
1. A method of dividing a frequency of a clock signal, comprising: generating a first frequency divided signal based on the clock signal; detecting one of rising edges or falling edges in the first frequency divided signal; generating an edge detection signal with an edge detector that comprises a D flip-flop having a data input, a clock input, and a complement output by providing the first frequency divided signal to a data input of the D-flip-flop and logically AND-ing the complement output of the D flip-flop with the first frequency divided signal to output a pulse for one of each rising edge or each falling edge in the first frequency divided signal in response to one of each rising edge or each falling edge in the first frequency divided signal at the data input of the edge detector; and generating a second frequency divided signal based on the clock signal and the edge detection signal.