Patent ID: 6916685
Filing Date: 2005-07-12
Classification: H01L,H05K

Abstract:
1. A method of plating a metal layer over isolated pads arranged in a ring array on a semiconductor package substrate, comprising: preparing a substrate having a plurality of conductive blind vias electrically connected with internal circuits thereof, and a plurality of isolated pads formed on a substrate thereof, wherein each of the isolated pads has a plating line that extends towards one of the conductive blind vias and is electrically insulated from the conductive blind via such that an electrically insulating region exists between terminals of the plating lines and the conductive blind vias; applying a conductive film over the surface of the substrate, for electrically interconnecting the conductive blind vias and the plating lines; applying a photoresist layer over the conductive film, wherein the photoresist layer is formed with at least one opening for exposing a portion of the conductive film covering the isolated pads; removing the portion of the conductive film exposed through the opening of the photoresist layer, allowing the isolated pads to be electrically connected with the conductive blind vias by the conductive film; electrifying the substrate to plate a metal layer on the isolated pads respectively; and removing the photoresist layer and the remainder of the conductive film covered by the photoresist layer, to restore the electrical insulation between the isolated pads and the conductive blind vias.