Patent ID: 7411187
Filing Date: 2008-08-12
Classification: B82Y,G04F,G06N,H01J

Abstract:
1. An ion trap device, comprising: a semiconductor chip, including: a second substrate portion spaced and opposed to the first substrate portion so as to define a first aperture formed therebetween; a second insulator layer disposed on the second substrate portion spaced and opposed to the first insulator layer so as to define a second aperture formed therebetween; a second electrode layer disposed on the second insulator layer, wherein a second electrode system is formed on a surface thereof, wherein the second electrode layer is spaced and opposed to the first electrode layer so as to define a third aperture formed therebetween; a third insulator layer disposed on the first electrode layer; a third electrode layer disposed on the third insulator layer, wherein a third electrode system is formed on a surface thereof; a fourth insulator layer disposed on the second electrode layer spaced and opposed to the third insulator layer so as to define a fourth aperture formed therebetween; and a fourth electrode layer disposed on the fourth insulator layer, wherein a fourth electrode system is formed on a surface thereof, wherein the fourth electrode layer is spaced and opposed to the third electrode layer so as to define a fifth aperture formed therebetween; wherein the first, second, third, fourth, and fifth apertures are substantially axially aligned so as to define the at least one ion trapping region selectively operable to receive at least one ion introduced therein; wherein the first, second, third and fourth electrode systems are selectively operable to form the ion trap in the ion trapping region when a voltage is selectively applied to the first, second, third and fourth electrode systems.