Patent ID: 6731698
Filing Date: 2004-05-04
Classification: H04L

Abstract:
A quadrature demodulation circuit for demodulating a pair of baseband signals from a digital modulation signal, comprising:a quasi synchronous detection circuit for providing quasi synchronous detection of said baseband signals from said digital modulation signal; AD converters each converting each of said baseband signals into digital data; adders each adding output data from each of said AD converters with a DC offset signal; and a PLL circuit for generating a reproduction clock synchronized with at least one of said baseband signals; wherein said PLL circuit generates said DC offset signal based on a phase relation between said baseband signals and said reproduction clock, and supplies said DC offset signal to said adder; and wherein said PLL circuit includes a phase comparator for comparing phases between said baseband signal and said reproduction clock, said phase comparator detecting the level of the baseband signal at the time of rise or fall of said reproduction clock to output the detected level as said DC offset signal.