Patent ID: 6656764
Filing Date: 2003-12-02
Classification: H01L,Y10S

Abstract:
A method of forming a metal oxide semiconductor field effect transistor (MOSFET) device, with a gate insulator layer comprised of a high dielectric constant (high k), dielectric layer, on a semiconductor substrate, comprising the steps of:forming a well region in a top portion of said semiconductor substrate, forming a hard mask on a portion of top surface of said semiconductor substrate; performing a first dry etch procedure to remove a top portion of said semiconductor substrate not covered by said hard mask, resulting in recessed regions in said semiconductor substrate, and a non-recessed portion of said semiconductor substrate covered by said hard mask; forming a heavily doped source/drain region in a top portion of said recessed regions; depositing a polysilicon layer; performing a second dry etch procedure to form lightly doped source/drain (LDD), polysilicon spacers on the sides of said non-recessed portion of said semiconductor substrate; forming a metal silicide region in a top portion of said heavily doped source/drain region; forming a planarized first insulator layer, exposing top surface of said hard mask; removing said hard mask resulting in space located between LDD polysilicon spacers, exposing top surface of underlying said non-recessed portion of said semiconductor substrate; forming said gate insulator layer, comprised of said high k dielectric layer, in said space; and forming a conductive metal structure on said gate insulator layer.