Patent ID: 6515538
Filing Date: 2003-02-04
Classification: G05F

Abstract:
An active bias circuit comprising:(a) a first transistor with a diode connection; the first transistor being supplied with a reference current by way of a first resistor; the first transistor having a control terminal; (b) a second transistor connected in cascode to the first transistor; the second transistor having a control terminal; (c) a third transistor having a control terminal connected to the control terminal of the first transistor; a constant current with a specific ratio with respect to the reference current flowing through the third transistor; (d) a fourth transistor with a diode connection; the fourth transistor being connected in cascode to the third transistor; the fourth transistor having a control terminal connected to the control terminal of the second transistor; (e) an output terminal formed between the third and fourth transistors connected in cascode; an output bias voltage being derived from the output terminal, the output bias voltage varying according to a reference voltage applied across the first and second transistors connected in cascode; and (f) a second resistor connected between the control terminal of the first transistor and the control terminal of the third transistor; wherein an absolute value of the output bias voltage is decreased with a voltage drop of the second resistor that is generated by a current flowing through the second resistor.