Patent ID: 8493044
Filing Date: 2013-07-23
Classification: H02M,Y02B

Abstract:
1. A circuit comprising: a first node having an analog supply voltage; a second node having a high-side voltage; a third node having a low-side voltage; a functional unit to sample a master clock signal having a sequence of pulses based on a phase of the master clock signal to provide an internal clock signal, wherein the phase is determined by the ratio of numerator and a denominator, wherein the numerator is the difference between the analog supply voltage and the high-side voltage, and the denominator is the difference between the high-side voltage and the low-side voltage; a pulse width modulation generator to provide a pulse width modulation signal clocked by the internal clock signal; and a high-side power transistor and a low-side power transistor coupled to the pulse width modulation generator to switch on and off in response to the pulse width modulation signal, so that the high-side power transistor is on only if the pulse width modulation signal is in a first logical state, and the low-side power transistor is on only if the pulse width modulation signal is in a second logical state complementary to the first logical state, such that both the high-side and low-side power transistors are not simultaneously on.