Patent ID: 6904551
Filing Date: 2005-06-07
Classification: G11C

Abstract:
1. In a microelectronic device with n memory cells at an input stage, a circuit for testing said microelectronic device, said circuit comprising: a) n first components for comparing data at an input of each of said memory cells to an output of each of said memory cells respectively wherein a first array of n test vectors comprising said data is applied, one said test vector to each said input, said data generated externally to said microelectronic device, and wherein said circuit performs said testing without writing said data back into said memory cells, for detecting any difference between said data at said input of each of said memory cells to said output of each of said memory cells, and for converting said difference into a difference signal; b) a second component for combining said difference signals for all of said memory cells into an error signal; and c) a third component for processing said error signal and transferring said error signal to an external test system, wherein a second array of n test vectors comprising said data is then applied, one said test vector to each said input, and wherein said test vectors of said second array have a value different from said test vectors of said fist array, and wherein said first components, said second component and said third component repeat their respective functions thereon.