Patent ID: 6996792
Filing Date: 2006-02-07
Classification: G06F

Abstract:
1. A method for making an integrated circuit model for an integrated circuit comprising the steps of: dividing the integrated circuit into a plurality of connected blocks, each block having a plurality of latches each having an on state defined between a latch start time and a latch end time, at least one of said latches in each of said blocks having a global path connected to a latch from a second of said plurality of blocks, at least a first of said latches being connected to an incoming global path; and compressing each of said blocks by assigning a first latch signal arrival time for an incoming global signal equal to said first latch end time, determining a signal arrival time for others of said latches as said signal propagates through said block, comparing said signal arrival time for respective of said latches with said latch start times for said respective of said latches until a final latch is found having a latch start time later than a latch arrival time for said final latch, and removing all latches from said block downstream of said final latch except for latches connected to a global path.