Patent ID: 6882003
Filing Date: 2005-04-19
Classification: H01L

Abstract:
1. An in-process semiconductor device comprising: at least two columns of transistors within a single sector of a memory device, each transistor having a source region; a dielectric layer having an opening therein, said opening defined by first and second cross sectional sidewalls of said dielectric layer, wherein each said first and second sidewall overlies one said column of transistors; first and second dielectric spacers, wherein each said first and second spacer covers one said sidewall of said dielectric layer; and a conductive line partially formed between said two columns of transistors and partially formed in said opening in said dielectric layer between said first and second dielectric sidewalls, wherein said spacers separate said conductive line from physical contact with said dielectric layer, and wherein said conductive line electrically couples each said source region of each said transistor in each of said two columns of transistors.