Patent ID: 8021966
Filing Date: 2011-09-20
Classification: G11C,H01L

Abstract:
1. A method of fabricating a nonvolatile memory device, the method comprising: forming a lower dielectric layer on a word line; forming a first sacrificial layer pattern on the lower dielectric layer, the first sacrificial layer pattern including a first open area having a first width and separating adjacent first sacrificial layer pattern elements that extend in a first direction on the lower dielectric layer; forming a pre-lower dielectric layer pattern from the lower dielectric layer by partially etching portions the lower dielectric layer exposed in the first open area using the first sacrificial layer pattern as an etching mask, the first open area being deepened into a recess having the first width and separating adjacent pre-lower dielectric layer pattern elements; forming a second sacrificial layer pattern on the pre-lower dielectric layer pattern and overlapping the first sacrificial layer pattern, the second sacrificial layer pattern including a second open area having a second width and separating adjacent second sacrificial layer pattern elements that extend in a second direction on the pre-lower dielectric layer pattern, wherein the second open area intersects the recess; forming a lower dielectric layer pattern from the pre-lower dielectric layer pattern by completely etching portions of the pre-lower dielectric layer pattern exposed in the intersection between the second open area and the recess to form a contact hole through the lower dielectric layer pattern exposing an upper surface of the word line; before forming a bottom electrode in the contact hole, forming a vertical cell diode in the contact hole, such that a lower surface of the bottom electrode is formed in electrical contact with the vertical cell diode; and forming the bottom electrode in the contact hole by