Patent ID: 7330518
Filing Date: 2008-02-12
Classification: H03F

Abstract:
1. A distortion compensation circuit for generating a predistortion signal to perform distortion compensation of a power amplifier comprising: A/D converter means for digitizing a voltage value of a signal after quadrature modulating a baseband signal; subtractor means supplied with the output data of the A/D converter means; voltage value data output means for outputting a voltage value data corresponding to the output data of the subtractor means by selecting from a plurality of pieces of previously stored voltage value data; amplitude impulse response accumulation adding means for outputting an accumulation adding value of multiplication values obtained by multiplying the signal voltage value after quadrature modulation by impulse response values corresponding to amplitude characteristic of the power amplifier in accordance with the voltage value data from the signal voltage value data outputting means and supplying to the subtractor means; and D/A converter means for converting the voltage value data from the voltage value data outputting means into an analog signal as an output predistortion signal regarding the amplitude component of the power amplifier, wherein said amplitude impulse response accumulation adding means comprises: N of first table blocks each having a first table storing M of said multiplication values corresponding to each of said voltage value data and a first adder for adding M of said multiplication values outputted from said first table; a delay block formed by serially connecting N−1 of delays for delaying the voltage value data outputted from said voltage value data output means by a predetermined time; and a second adder for outputting said accumulation adding values obtained by adding respective output values from respective first adder in said N of first table blocks to said subtractor means, and N of points comprising input point of said delay at a first stage, each of connecting points among delays, and output point of said delay at final stage in the delay block are connected to each of input point in said N of first table block, and at least a part of the voltage value data outputted from said voltage value data output means is defined as address data for accessing each of said first table in said first table block, wherein said M and N are natural numbers.