Patent ID: 8260994
Filing Date: 2012-09-04
Classification: G06F

Abstract:
1. An integrated circuit, comprising: an on-chip communication path connected to a plurality of on-chip functional modules, wherein at least one of the on-chip functional modules is capable of issuing packets; and an interface implemented on-chip and having at least one chip-side port connected to the communication path and configured to transmit the packets in parallel across a plurality of pins, the interface further having first and second circuit-side ports each with a reduced number of pins configured to communicate the packets off-chip via the reduced number of pins, the interface including wherein the interface further comprises circuitry configured to chop a packet transmitted from the communication path on the plurality of pins on the at least one chip-side port so as to be transmitted in a plurality of cycles on the reduced number of pins on the first circuit-side port.