Patent ID: 6289429
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A memory device, comprising:a first single-port memory;a second single-port memory;a first processor for generating a first address for defining a location to be accessed in the first single-port memory, a first control signal for activating the first single-port memory, a second address for defining a location to be accessed in the second single-port memory, and a second control signal for activating the second single-port memory;a second processor for generating a third address not compatible with the first and second single-port memories; anda memory control section for controlling access to the first single-port memory and access to the second single-port memory, the memory control section including an address conversion section for converting the third address so as to represent either one of the first address and the second address, and for generating either one of the first control signal and the second control signal based on at least a portion of the third address.