Patent ID: 6440780
Filing Date: 2002-08-27
Classification: G06F

Abstract:
A semiconductor integrated circuit device layout method for designing a layout of a semiconductor integrated circuit device, said semiconductor integrated circuit device including a gated clock circuit, said gated clock circuit having one gated circuit comprising a gated cell connected to a clock and a first element group connected to a clock source via said gated cell and having a second element group directly connected to said clock source, said method comprising:a net list change step of changing a net list of said gated clock circuit to a net structure wherein a cell for correcting a stage number is added between said clock source and said second element group in order to handle said second element group as another gated circuit, a gated circuit division information generation step of determining a division number of each of said respective gated circuits so that delay values become equal and of allocating a driving ability of a cell for circuit division for said each respective gated circuit by selecting the driving ability of the cell for circuit division in accordance with the total load capacitance of said each respective gated circuit based on the result of carrying out at least one of an arrangement and an appropriate wiring in accordance with a net list after a change, a gated circuit division step of forming a plurality of clusters by dividing said each respective gated circuit through clustering based on information generated in said gated circuit division information generation step and of respectively inserting cells for circuit division having the driving ability allocated in said gated circuit division information generation step in the positions wherein the load capacitance of said respective clusters becomes equal, a gated cell division step of allocating the same number of gated cells for circuit division as the number of said clusters in said each respective gated circuits, of selecting the driving ability of said gated cell for circuit division so that delay values become equal in accordance with input capacitance of said cells for circuit division and of inserting said each respective gated circuit for circuit division, and a gated cell front stage CTS step for generating a hierarchical tree between said clock source and said respective gated cell for circuit division according to a clock tree system.