Patent ID: 7853824
Filing Date: 2010-12-14
Classification: G06F

Abstract:
1. A computer for backup and being fault-tolerant comprising: a CPU for controlling components of the computer and performing arithmetic and logical operations; an I/O port connected to the CPU and adapted to transfer and communicate data; a memory address decoder connected to the CPU and adapted to decode a memory address to be assessed by the CPU; a dual-port memory adapted to store operation data and including a first receiving terminal connected to a first transmitting terminal of the memory address decoder for receiving a memory address decoded by the memory address decoder, and first and second ports wherein the first port is connected to the CPU such that the CPU is adapted to access data of the dual-port memory via the first port; a bus tri-state buffer having one terminal connected to the CPU and the first port of the dual-port memory respectively, and the other terminal connected to the second port of the dual-port memory; a system bus connected to the other terminal of the bus tri-state buffer and the second port of the dual-port memory; an arbitration circuit including a first input connected to the CPU for receiving a control signal sent therefrom, a third input, and an output connected to an enable terminal of the bus tri-state buffer such that a control signal sent from the CPU is adapted to control an output value of the arbitration circuit for causing the bus tri-state buffer to enter a bi-directional communication state or a high impedance disconnected state; and a switch having an output connected to the third input of the arbitration circuit, wherein a reset signal is generated when the switch is pressed for controlling the output value of the arbitration circuit and causing the bus tri-state buffer to enter a bi-directional communication state or a high impedance disconnected state.