Patent ID: 6363003
Filing Date: 2002-03-26
Classification: G11C

Abstract:
A ferroelectric memory device comprising:a matrix of memory cells each including a semiconductor transistor and a ferroelectric capacitor; a plurality of word lines and a plurality of bit lines provided so as to intersect each other; and a plurality of plate lines provided substantially in parallel to the word lines, at least two plate lines corresponding to each of the word lines, wherein a drain of the semiconductor transistor is coupled to a first electrode of the ferroelectric capacitor; a source of the semiconductor transistor is coupled to a corresponding one of the plurality of bit lines; a gate of the semiconductor transistor is coupled to a corresponding one of the plurality of word lines; and a second electrode of the ferroelectric capacitor is coupled to a corresponding one of the plurality of plate lines, the ferroelectric memory device further comprising: a selection/driving circuit being coupled to the plurality of word lines and the plurality of plate lines and receiving a ROW address, the ROW address being divided into a first portion and a second portion, wherein the first portion of the ROW address is used to select and activate at least one of the plurality of word lines, the at least one word line defining a broader area than is designated by the ROW address, and wherein the second portion of the ROW address is used to select and activate at least one of the plurality of plate lines, thereby selecting at least one of the plurality of memory cells whose corresponding word line and whose corresponding plate line are both activated.