Patent ID: 7612417
Filing Date: 2009-11-03
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor memory device comprising: first and second bit lines; a plurality of word lines; a memory array having a plurality of memory cells, each of the memory cells having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of said second inverter being coupled to an output terminal of said first inverter and with an output terminal of said second inverter being coupled to an input terminal of said first inverter, a third N-channel MOS transistor having a source/drain path coupled between the output terminal of said first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path coupled between the output terminal of said second inverter and the second bit line, a gate of each of said third and fourth N-channel MOS transistors being connected to one of said plurality of word lines; a first P-type well region in which said first and third N-channel MOS transistors are formed and which is formed commonly throughout said plurality of memory cells, said first P-type well region lying parallel to said first and second bit lines; a second P-type well region in which said second and fourth N-channel MOS transistors are formed and which is formed commonly throughout said plurality of memory cells, said second P-type well region lying parallel to said first and second bit lines; an N-type well region in which said first and second P-channel MOS transistors are formed and which is formed commonly throughout said plurality of memory cells, said N-type well region lying between said first and second P-type well regions; a first electrical lead to supply a first voltage to said first and second P-type well regions; a second electrical lead to supply a second voltage to said N-type well region; and wherein with respect to a plan view of a principal plane of said semiconductor memory device, wherein said first P-type well region in said first area is supplied with said first voltage from said second area and said first area has no contacts to supply said first voltage to said first P-type well region, wherein said second P-type well region in said first area is supplied with said first voltage from said third area and said first area has no contacts to supply said first voltage to said second P-type well region, and wherein said N-type well region in said first area is supplied with said second voltage from said fourth area and said first area has no contacts to supply said second voltage to said N-type well region.