Patent ID: 8576649
Filing Date: 2013-11-05
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a sense amplifier coupled to a first bitline and a second bitline of a memory array; wherein the sense amplifier includes: wherein the read-precharge-reference circuit includes: a first bit voltage select circuit coupled between the first sense amplifier node and the first bitline; a second bit voltage select circuit coupled between the second sense amplifier node and the second bitline; wherein the first bit voltage select circuit includes a third transistor coupled between the first sense amplifier node and the first bitline for pass gating; wherein the first bit voltage select circuit further includes a fourth transistor commonly gated with the third transistor to receive a first select signal, the fourth transistor having a first source/drain node coupled to receive a bit voltage and a second source/drain node coupled to the first bitline; wherein the second bit voltage select circuit includes a fifth transistor coupled between the second sense amplifier node and the second bitline for pass gating; and wherein the second bit voltage select circuit further includes a sixth transistor commonly gated with the fifth transistor to receive a second select signal, the sixth transistor having a first source/drain node coupled to receive the bit voltage and a second source/drain node coupled to the second bitline.