Patent ID: 6496887
Filing Date: 2002-12-17
Classification: C07K,H03K

Abstract:
A component architecture for a plurality of dedicated SRAM blocks associated with a plurality of multi-level architecture groupings of logic modules (MLA) in an FPGA comprising:a first column and a second column adjacent to said first column wherein each of said first and second columns comprises: a first MLA, a first SRAM block, a second SRAM block, a second MLA, a plurality of pass-through interconnector conductors vertically spanning each of said first and second SRAM blocks, SRAM address, data and control signal lines all horizontally traversing each said SRAM block and forming intersections with said plurality of pass-through interconnector conductors, a first edge of each of said first and second SRAM blocks, wherein each said first edge is adjacent to a one of said first MLA and said second MLA, at least two edges of each of said first and said second SRAM blocks, each said at least two edges being adjacent to another SRAM block, a first plurality of user-programmable interconnectors of each first edge connecting conductors of a routing channel in said one MLA adjacent said first edge and said plurality of pass-through interconnector conductors, and a second plurality of user-programmable interconnectors on each said at least two edges selectively connecting said SRAM address, data and control signal lines and said plurality of pass-through interconnector conductors spanning each of said first and said second SRAM blocks.