Patent ID: 6396109
Filing Date: 2002-05-28
Classification: H01L

Abstract:
BiCMOS integrated circuit having an NMOS transistor non-oxide isolated from the remainder of said BiCMOS integrated circuit, comprising:a P-type semiconductor substrate region; an N conductivity type buried layer region disposed in and contacting said P-type semiconductor substrate region; contiguous alternate N and P conductivity type buried layers disposed over and contacting said N conductivity type buried layer region, said N type buried layer also contacting said substrate; N and P conductivity type wells, said P type wells contacting said P conductivity type buried layer and said N type wells contacting said P and N conductivity type buried layers to isolate each said P conductivity type well region from said substrate by said N conductivity type buried layer region, said N conductivity type buried layers, and said N conductivity type wells; and NMOS source/drain regions in said isolated P conductivity type well region providing a portion of at least one said NMOS transistor.