Patent ID: 6150213
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method for manufacturing dynamic random access memory cells, the method comprising the steps of:forming transistors and word lines on a semiconductor substrate;forming a first isolation layer over the transistors;forming polysilicon plugs in the first isolation layer over the transistors, the polysilicon plugs formed between said transistors and the word lines;forming a polysilicon layer on the first isolation layer;forming a cap layer over said polysilicon layer;etching said cap layer, said polysilicon layer and said first isolation layer to expose the polysilicon plugs formed between the word lines and the transistors;forming oxide spacers on sidewalls of the etched polysilicon layer and the etched cap layer;forming a silicon nitride layer on the surface of the oxide spacers, the etched cap layer and the polysilicon plugs;forming a second isolation layer on the silicon nitride layer;etching the second isolation layer to form storage node contact holes over the polysilicon plugs formed between the transistors and the word lines;etching the silicon nitride layer exposed by the storage node contact holes to form nitride spacers on the oxide spacers;forming a first conductive layer on a surface of the storage node contact holes, and on the second isolation layer;removing a portion of the first conductive layer on the second isolation layer;removing the second isolation layer, thereby forming crown shaped first storage nodes;forming a dielectric film on the surface of the crown shaped first storage nodes; andforming a second conductive layer over said dielectric film to act as a second storage node.