Patent ID: 7499511
Filing Date: 2009-03-03
Classification: H03L,H04L

Abstract:
1. A clock recovery system, comprising: a sampler that is configured to sample an input data signal in synchronization with a modulated clock signal to generate a sample of the input data signal; a phase comparator that is configured to compute a position of a transition edge of the input data signal using the sample data signal, and to compare the computed position with a position of an edge of the modulated clock signal to generate a comparison result; an edge counter that is configured to count transition edges of the sample data signal; a controller that is configured to generate first and second control signals based on the comparison result and the count of the transition edges; and a clock phase modulator that is configured to generate the modulated clock signal by adjusting a phase of an input clock signal responsive to the first and second control signals, such that the phase is increased in response to the first control signal and reduced in response to the second control signal.