Patent ID: 6320786
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A method of controlling a multi-state NROM having a substrate, a drain terminal and source terminal in the substrate, and a gate electrode above the substrate between the drain terminal and the source terminal, wherein the gate electrode is a multi-layered stack that includes, from bottom to top, a first oxide layer, a nitride layer, a second oxide layer and a polysilicon layer, and the nitride layer is able to trap a plurality of electric charges and hence can serve as a charge storage region, comprising the steps of:performing a programming operation to inject electric charges and trap inside the nitride layer, and controlling the amount of stored inside the nitride layer so that the memory cell can have a plurality of different threshold voltages;applying a first variable voltage to the gate electrode to initiate a reading step;setting three different potential levels that includes, from the smallest to the largest, a first potential level, a second potential level and a third potential level according to the range of a second variable voltage applied to the drain terminal;adjusting the second variable voltage to the first potential level, assuming a first storage state if a large current is sensed;adjusting the second variable voltage to the second potential level if no large current is detected, assuming a second storage state if a large current is sensed after the adjustment; andadjusting the second variable voltage to the third potential level if no large current is detected, assuming a third storage state if a large current is sensed after the adjustment and assuming a fourth storage state if no large current is sense after the adjustment.