Patent ID: 8346833
Filing Date: 2013-01-01
Classification: G06F

Abstract:
1. A filter, comprising: a storage unit comprising a first register and a second register, said first register comprising a first group of source operands, said second register comprising a second group of source operands; vector arithmetic logic means for performing a filtering process on the first and second group of source operands to obtain m results of interpolation, said m being an integer not less than 1, wherein the vector arithmetic logic means comprises: wherein the filter further comprises a first multiplex array and a second multiplex array; wherein the first multiplex array is configured to shift left the first group of source operands and fill the rightmost data of the first group of source operands with zero, and the second multiplex array is configured to shift right the second group of source operands and fill the leftmost data of the second group of source operands with zero, thereby effecting a self-modification on the first and second groups of source operands, and enabling the shifted first group of source operands and the shifted second group of source operands to be the next first and second groups of source operands subject to a next filtering process; and wherein the filter further comprises: (i) first writeback means for writing back the shifted and self-modified first group of source operands to the first register in preparation for the next filtering process and (ii) second writeback means for writing back the shifted and self-modified second group of source operands to the second register in preparation for the next filtering process.