Patent ID: 6541815
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A 2F2 flash memory cell structure comprising:a Si-containing substrate having a plurality of trenches formed therein, each trench having sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment, each memory cell element comprising (i) a floating gate region having L-shaped gates formed on a lower portion and not on an upper portion of each trench sidewall; (ii) a program line overlapping one side of said L-shaped gates present at said bottom wall of each trench and extending along said entire length of said plurality of trenches; and (iii) a control gate region overlying said floating gate region, said control gate region including gates formed on the upper portions and not on the lower portions of said sidewalls of said trenches, said gates are coupled to said floating gate regions; bitline diffusion regions formed in said Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to said trenches, said wordlines being in contact with a top surface of each control gate region.