Patent ID: 6175891
Filing Date: 2001-01-16
Classification: G06F

Abstract:
A memory system comprising:a plurality of memory devices, with each memory device comprising(a) an array of memory cells;(b) an addressing circuitry operatively coupled to the array of the memory cells, wherein the addressing circuitry is capable of providing addresses to the array of the memory cells;(c) a bus interface;(d) a command decoder which decodes commands at the bus interface, including an address assign command; and(e) a local address storage circuitry which stores a local address for the associated memory device once the address assign command is decoded by the command decoder; anda memory controller having a bus interface coupled to the bus interface of the memory device, with the memory controller providing the local address to be stored in the local address storage circuitry of the memory device of the memory system together with the address assign command,wherein the bus interface of the memory controller is coupled to the bus interface of the memory device by a system bus,wherein the memory controller transfers the local address to the memory devices over the system bus and the address assign command over the system bus,wherein the memory controller has a select signal output and each of the memory devices has a select signal input and a select signal output, with the select signal output of the memory controller being coupled to the select signal input of a first one of the memory devices by a first select signal line and wherein the select signal output of the first memory device is coupled to the select signal input of a second one of the memory devices by a second select signal line.