Patent ID: 6560686
Filing Date: 2003-05-06
Classification: G11C

Abstract:
A memory device with variable bank partition architecture comprising:a memory address space that is divided by a bank unit; a plurality of bank level terminals each of which receives a bank level signal for specifying a number of divided banks; a plurality of address terminals each of which receives a bank specification address signal for specifying one of divided banks; a plurality of data input/output terminals each of which receives a data to be input into a memory address in said memory address space or each of which outputs a data stored at a memory address in said memory address space; and a control terminal which receives a control signal for specifying either input or output of the data, wherein a memory address area corresponding to a bank specified based on a bank specification address signal of those obtained by dividing a memory address space according to a number specified by the bank level signal is identified based on a bank level signal input from said bank level terminal as well as on the bank specification address signal input from said address terminal, data input from said data input/output terminal is written in a storage area indicated by a memory address in said identified memory address area when a control signal input from said control terminal specifies input of data, and data stored in said identified memory address area is output from said data input/output terminal when a control signal input from said control terminal specifies output of data.