Patent ID: 8392776
Filing Date: 2013-03-05
Classification: G01R

Abstract:
1. A fault diagnosis method, comprising: providing a semiconductor integrated circuit device, the semiconductor integrated circuit device having first and second flip flops on an output side, a first scan chain in which the first and second flip flops are connected in series, input-side flip flops on an input side, a second scan chain in which the input-side flip flops are connected in series, and logic circuitry serving as test targets and obtained by connecting and combining a plurality of logic circuit elements, at least a portion of the logic circuitry being connected between corresponding input-side flip flops and the first and second flip flops, the logic circuitry being operated by supply of a test clock; inputting a test pattern from a tester to the second scan chain through a scan chain input terminal provided in the semiconductor integrated circuit device; outputting a test result to the tester from the first scan chain through a scan chain output terminal provided in the semiconductor integrated circuit device; transmitting the test result to an information processing device from the tester; reading out an expected value from a database by the information processing device, determining one of a complete match, a complete mismatch, and a partial match and partial mismatch between the test result and the expected value for each of the first and second flip flops in the first scan chain, and storing determination results thereof in the database; reading out net list information stored in the database by the information processing device, setting a fault assumption where malfunction of the semiconductor integrated circuit device is assumed at a predetermined point in the logic circuitry, and extracting a plurality of first propagation routes each including the predetermined point in the route and the first flip flop as a finish-point and a plurality of second propagation routes each including the predetermined point in the route and the second flip-flop as a finish-point from signal propagation routes between the first and second flip flops and the input-side flip flops; and reading out delay information of wiring and the logic circuit elements stored in the database by the information processing device, determining a propagation time of the first propagation routes by adding up the delay information of the wiring and the logic circuit elements of the first propagation routes, determining a first delay margin for each of the first propagation routes by subtracting the propagation time from a time interval of the test clock, determining a propagation time of the second propagation routes by adding up the delay information of the wiring and the logic circuit elements of the second propagation routes, and determining a second delay margin for each of the second propagation routes by subtracting the propagation time from the time interval of the test clock, wherein a first transition time of a logic level of a signal at the predetermined point is determined to be shorter than a longest one of the first delay margins by the information processing device when the determination result associated with the first flip-flop is complete match, wherein the first transition time of the logic level of the signal at the predetermined point is determined to be longer than a shortest one of the first delay margins by the information processing device when the determination result associated with the first flip flop is complete mismatch, wherein the first transition time of the logic level of the signal at the predetermined point is determined to be shorter than the longest one of the first delay margins and the first transition time of the logic level of the signal at the predetermined point is determined to be longer than the shortest one of the first delay margins by the information processing device when the determination result associated with the first flip flop is partial match and partial mismatch, wherein a second transition time of the logic level of the signal at the predetermined point is determined to be shorter than a longest one of the second delay margins by the information processing device when the determination result associated with the second flip flop is complete match, wherein the second transition time of the logic level of the signal at the predetermined point is determined to be longer than a shortest one of the second delay margins by the information processing device when the determination result associated with the second flip flop is complete mismatch, wherein the second transition time of the logic level of the signal at the predetermined point is determined to be shorter than the longest one of the second delay margins and the second transition time of the logic level of the signal at the predetermined point is determined to be longer than the shortest one of the second delay margins by the information processing device when the determination result associated with the second flip flop is partial match and partial mismatch, and wherein it is determined that existence of a delay fault in one of the logic circuit elements associated with the predetermined point by the information processing device when there is a common range value of the first transition time and the second transition time, and it is determined no existence of delay fault in the one logic circuit element associated with the predetermined point by the information processing device when there is no common range value therebetween.