Patent ID: 6590255
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a peripheral circuit section and a memory cell section both formed on a semiconductor substrate; said peripheral circuit section comprising: a first element region formed in said semiconductor substrate; a first element isolating region extending into said semiconductor substrate for electrically isolating said first element region, said first element isolating region having a recessed portion and a non-recessed portion; a first conductive layer formed above said first element region with a first insulating film interposed therebetween; a second conductive layer having a first section and a second section, the first section being on and in contact with said first conductive layer, and the second section being on and in contact with said recessed portion of said first element isolating region and extending from the first section to said non-recessed portion of said first element isolating region, wherein said first and second conductive layers form a first gate electrode; a third conductive layer formed on said second conductive layer with a second insulating film interposed therebetween; and an electrical interconnection region formed on and in contact with said second section of said second conductive layer, said interconnection region being adjacent to said third conductive layer and said second insulating film; said memory cell section comprising: a second element region formed in said semiconductor substrate; a second element isolating region extending into said semiconductor substrate for electrically isolating said second element region; a fourth conductive layer formed above said second element region with a third insulating film interposed therebetween, said fourth conductive layer being at an equal level with said first conductive layer; a fifth conductive layer formed on said fourth conductive layer, said fifth conductive layer being at an equal level with said second conductive layer; and said fourth and fifth conductive layers forming a floating gate; and a sixth conductive layer formed on said fifth conductive layer and said second element isolating region with a fourth insulating film interposed therebetween, said sixth conductive layer forming a control gate and being at an equal level with said third conductive layer, wherein top surfaces of said second conductive layer, said fifth conductive layer, said second element isolating region and said non-recessed portion of said first element isolating region are flat and comprised in a planar surface.