Patent ID: 6768687
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A memory array including a plurality of pairs of first and second bit lines whose complementary logic voltages are interchanged during data writing; a plurality of pairs of first and second word lines; a common cell plate voltage line; a first memory cell connected to said first bit line, said first word line and said common cell plate voltage line; a second memory cell connected to said second bit line, said second word line and said common cell plate voltage line; and a sense amplifier connected between said first and second bit lines, wherein a plurality of said first and second memory cells are arranged in a matrix form, the memory array comprising:first and second dummy word lines; a first dummy memory cell connected to said first bit line, said first dummy word line and said common cell plate voltage line; and a second dummy memory cell connected to said second bit line, said second dummy word line and said common cell plate voltage line, wherein second dummy data having opposite polarity to polarity of first data are written in said second dummy memory cell so as to write the first data in said first memory cell, and first dummy data having opposite polarity to polarity of second data are written in said first dummy memory cell so as to write the second data in said second memory cell, thereby canceling coupling noise on said common cell plate voltage line.