Patent ID: 6473017
Filing Date: 2002-10-29
Classification: H03M

Abstract:
A circuit for determining an amplitude of a set of samples xk comprising:a digital to analog converter in a negative feedback loop connected to supply a first integrator input; a first integrator acting upon the first integrator input and the set of samples xk, to produce a corresponding set of first integrated signals uk; a second integrator acting upon the set of first integrated signals uk to produce a corresponding set of second integrated signals vk; timing elements included in a signal, path of the first and second integrated signals uk and vk to provide a delayed first integrated signal ukâˆ’i and a delayed second integrated signal vkâˆ’1 that are one sample delayed in time relative to the sample xk; and a vector quantizer Q(xk, ukâˆ’1, vkâˆ’1) configured to provide a binary output qk in response to the set of samples xk, the delayed first integrated signal ukâˆ’1, and the delayed second integrated signal vkâˆ’1 inputs wherein the vector quantizer Q(xk, ukâˆ’1, vkâˆ’1) further comprises a quadratic operator acting upon the set of samples xk and the first delayed first integrated signal ukâˆ’1 and the delayed second integrated signal vkâˆ’1 to produce a summed output yk; a set of coefficient boxes acting upon the output zk, the set of samples xk, the delayed first integrated signal ukâˆ’1 and the delayed second integrated signal vkâˆ’1 to produce a summed output yk, and a comparator receiving the summed output yk as the first comparator input and outputting the binary output qk.