Patent ID: 8949659
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. A computer implemented method for scheduling workloads based on detected hardware errors, the computer implemented method comprising: responsive to a data processing system determining that a hardware error is detected in hardware of the data processing system, determining, by the data processing system, whether the hardware error is a cache error; responsive to the data processing system determining that the hardware error is a cache error, determining, by the data processing system, whether execution of a workload on a processor is changing contents of a cache associated with the cache error more than a cache usage threshold value; responsive to the data processing system determining that the execution of the workload on the processor is changing the contents of the cache associated with the cache error more than the cache usage threshold value, determining, by the data processing system, whether the cache associated with the cache error is private to a particular core in the processor; and responsive to the data processing system determining that the cache associated with the cache error is private to a particular core in the processor, scheduling, by the data processing system, the execution of the workload on a different core of the processor so that the cache associated with the cache error that is private to the particular core is not used.