Patent ID: 7187204
Filing Date: 2007-03-06
Classification: G01R,G09G

Abstract:
1. An inspecting circuit of a semiconductor device comprising: at least first, second, and third signal lines; at least first and second inverters; at least first, second, and third NANDs, each of the first, second, and third NANDs having first and second input terminals; and an output terminal electrically connected to outputs of the first, second, and third NANDs; wherein an output of the first NAND is electrically connected to the first input terminal of the second NAND through the first inverter, wherein an output of the second NAND is electrically connected to the first input terminal of the third NAND through the second inverter, wherein the second input terminals of the first, second, and third NANDs are connected to first, second, and third signal lines, respectively, and wherein a determination of whether the semiconductor device is normally operated or not is based on at least a signal obtained at the output terminal.