Patent ID: 9035373
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; a first gate structure of an input/output (I/O) device formed on the semiconductor substrate, wherein the first gate structure includes a first oxide layer, a nitride layer on the first oxide layer, and a high-k dielectric layer on the nitride layer; a second gate structure of a low-power device formed on the semiconductor device, wherein the second gate structure includes a second oxide layer, the nitride layer on the second oxide layer, and the high-k dielectric layer disposed directly on the nitride layer, wherein the first oxide layer is thicker than the second oxide layer; a third gate structure formed on the semiconductor substrate, wherein the third gate structure includes an interfacial layer and the high-k dielectric layer disposed on the interfacial layer, wherein the first oxide layer is thicker than the interfacial layer; and a first isolation structure disposed in the semiconductor substrate and interposing the first and second gate structures and a second isolation structure disposed in the semiconductor substrate and interposing the second and third gate structures.