Patent ID: 8884402
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A circuit layout structure comprising: a wafer having at least a cell region and a scribe line region defined thereon; at least a metal pattern formed in a first insulating layer in the scribe line region; a second insulating layer and a hard mask layer formed on the metal pattern and the first insulating layer; a trench or a via pattern formed in the second insulating layer in the cell region, the trench or via pattern comprising a rectangular shape; and a plurality of dummy patterns formed in the second insulating layer and the hard mask layer in the scribe line region, the plurality of dummy patterns having a transmission rate between 0% and 1%, and the plurality of dummy patterns being arranged to form only one column along an axial line of the scribe line region, the plurality of dummy patterns comprising a rectangular shape, and long sides of the plurality of dummy patterns are parallel with a long side of the trench or via pattern in the plan view, wherein a distance between margins of the scribe line region and the plurality of dummy patterns is larger than 0.