Patent ID: 8391072
Filing Date: 2013-03-05
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells associated with columns and capable of storing data; a plurality of latch circuits associated with the columns and capable of storing write data and/or read data for the columns; and a comparator which performs a comparison operation based on a first threshold and a second threshold different from the first threshold, wherein the latch circuits are selectively activated, and activated latch circuits are capable of receiving and/or outputting data, the columns include a first column and a second column, the latch circuits include a first latch circuit associated with the first column and a second latch circuit associated with the second column, and the comparator performs the comparison operation based on the first threshold when the first latch circuit is activated, and performs the comparison operation based on the second threshold when the second latch circuit is activated while the first latch circuit is inactivated.