Patent ID: 6578126
Filing Date: 2003-06-10
Classification: G06F

Abstract:
A memory system, comprising:a first logic section that may cause a respective assertion of a first signal; a second logic section that may cause a respective assertion, in response to the respective assertion of the first signal, of a second signal; the first logic section being configured to provide to the second logic section, contemporaneously with the respective assertion of the first signal, information related to a requested memory operation to be performed by the memory system, the information specifying the requested memory operation to be performed and one or more memory locations in the memory system upon which the requested memory operation is to operate; wherein the first logic section and the second logic section are configured such that: if the requested memory operation comprises a first type of memory operation, the first logic section may transmit, in response to the respective assertion of the second signal, one or more data words to the second logic section to be used in the memory operation, and also may cause, contemporaneously with transmission of the one or more data words to the second logic section, a respective assertion of a third signal; if the requested memory operation comprises a second type of memory operation, the second logic section may transmit one or more other data words to the first logic section related to the memory operation, and also may cause, contemporaneously with transmission of the one or more other data words to the first logic section, a respective assertion of a fourth signal.