Patent ID: 7286400
Filing Date: 2007-10-23
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to read data of the memory cell array; and a pass/fail detection circuit configured to detect write or erase completion based on verify-read data stored in the sense amplifier circuit in data write or erase mode, wherein the pass/fail detection circuit comprises a data latch, into which a defective column isolation data is writable in accordance with a command input, and wherein the pass/fail detection circuit comprises: a plurality of first detection lines disposed for the respective columns in the sense amplifier circuit to be changeable in level in a pass/fail detection mode; a plurality of completion detection circuits each configured to flow a certain current in response to the level change of the corresponding first detection line for detecting write or erase completion; a second detection line coupled common to output nodes of the completion detection circuits, on which a sum of currents of the completion detection circuits flows; a permissible fail number setting circuit configured to output a reference current, which is settable in response to a permissible fail number with a plurality of current sources; a comparator circuit configured to compare the current of the second detection line with the reference current set with the permissible fail number setting circuit, and output a pass/fail signal; and data latches connected to the completion detection circuits, respectively, for storing defective column isolation data, into which defective column isolation data are writable in accordance with a command input.