Patent ID: 6628546
Filing Date: 2003-09-30
Classification: G11C

Abstract:
A method to program verify of a dual storage site MONOS memory cell using capacitance coupling of control gate lines, comprising:a) programming a selected storage site of a dual storage site MONOS memory cell using bit line capacitance to provide charge during a CHE program operation thereafter a first control gate is left floating with a first charged voltage, a second control gate is left floating with a second charged voltage, a first diffusion is left floating with a third charged voltage and a second diffusion is left floating with a fourth charged voltage, b) increasing a word gate voltage of said memory cell from a program voltage level to a high voltage, then c) equalizing said third and fourth charged voltages, then d) biasing said second diffusion to a voltage below said equalized third and fourth charged voltages, then e) measuring said first diffusion voltage with a sense amplifier to determine whether said selected storage site is programmed.