Patent ID: 7212438
Filing Date: 2007-05-01
Classification: G11C

Abstract:
1. A non-volatile memory cell comprising: a first floating gate transistor comprising a first floating gate and a first control gate; a second floating gate transistor comprising a second floating gate and a second control gate, the second floating gate transistor being coupled in series with the first floating gate transistor; an output coupled between the first floating gate transistor and the second floating gate transistor, such that the output receives an output voltage from either the first floating gate transistor or the second floating gate transistor; and programming circuitry coupled to the first floating gate transistor and the second floating gate transistor, the programming circuitry being operable to place a first selected electrical charge within the first floating gate and to place less than a second electrical charge within the second floating gate or being operable to place less than the first selected electrical charge within the first floating gate and to place the second selected electrical charge within the second floating gate, wherein the programming circuitry provides a data signal and an inverse data signal, the data signal being coupled to the first control gate and the inverse data signal being coupled to the second control gate.