Patent ID: 8121239
Filing Date: 2012-02-21
Classification: H03L,H04L

Abstract:
1. A method comprising: resetting a first register set of a first phase interpolator (PI) of a receiver and resetting a second register set of a second PI of the receiver to correspond to a predetermined delay lock loop (DLL) clock position; shifting the first and second PIs in common beginning from the predetermined DLL clock position to provide sampling signals until a predetermined logic value of an input signal received by the receiver is sampled in a first sampler and a second sampler, the predetermined value indicative of a baseline position of a track pre-tuning operation; and shifting the first and second PIs in common to provide sampling signals until a solid logic value having an opposite value from the predetermined value is sampled in the first and second samplers, and recording an offset value corresponding to a first occurrence of said solid logic value in the first register set and the second register set.