Patent ID: 7062726
Filing Date: 2006-06-13
Classification: G06F

Abstract:
1. A method for generating a tech-library for a logic function, comprising: (a) categorizing a first group of tech-descriptions for primitive physical circuits into a first group of tech-libraries using negation indices; (b) providing logic circuits realizing different representations of a logic function in said tech-library; (c) decomposing each of said logic circuits into a combination of instances; (d) selecting a second group of tech-libraries from among said first group of tech-libraries so that each of said second group of tech-libraries corresponds to each of said instances; (e) calculating a second group of tech-descriptions from a combination of tech-descriptions from said second group of tech-libraries, said second group of tech-descriptions describing said logic function; (f) adding a tech-description from said second group of tech-descriptions to said tech-library for said logic function when said tech-description has at least one marked parameter smaller than that of all existing elements of said tech-library for said logic function within a first precision; and (g) reducing an actual number real_numb of elements in said tech-library for said logic function when said actual number real_numb is at least twice larger than a limit max_numb; wherein said tech-library for said logic function is optimized over said at least one marked parameter and is used for mapping said logic function.