Patent ID: 6551846
Filing Date: 2003-04-22
Classification: H01L,Y10S

Abstract:
A semiconductor memory device comprising:a plurality of memory cells arranged in rows and columns; a plurality of pairs of bit lines arranged corresponding to said columns and each connected to memory cells of a corresponding column, each of the pair of bit lines including first and second bit lines transmitting data signals complementary to each other in a normal access mode, each memory cell of each of said columns being connected to one of said first and second bit lines of a corresponding pair of bit lines; a plurality of word lines arranged corresponding to said rows and each connected to memory cells of a corresponding row, the word lines including a first word line connected to a memory cell connected to the first bit line and a second word line connected to a memory cell connected to the second bit line; a plurality of sense amplifier circuits arranged corresponding to said columns and activated to sense and amplify data in memory cells on corresponding columns; a plurality of bit line precharge circuits arranged corresponding to said columns, coupled to a voltage transmission line, and each activated to transmit voltage on said voltage transmission line to a pair of bit lines of a corresponding column; and a test control circuit for activating the bit line precharge circuits and driving simultaneously, into selected state, a first predetermined number of word lines among said plurality of word lines in a first test mode operation, and inactivating said plurality of bit line precharge circuits, driving simultaneously, into selected state, said plurality of word lines and activating said plurality of sense amplifier circuits in a second test mode operation following the first test mode operation, wherein said test control circuit further comprises means configured for driving the first word lines into the selected state when a first test instruction signal is activated in said first test mode operation, means configured for setting the voltage on said voltage transmission line at voltage of a first logic level when said first test instruction signal is activated, and means configured to be responsive to activation of a second test instruction signal for simultaneously selecting said plurality of word lines and setting the voltage on said voltage transmission line at voltage of a second logic level in said first test mode operation, said second test instruction signal being activated prior to activation of said first test instruction signal.