Patent ID: 6532581
Filing Date: 2003-03-11
Classification: G06F

Abstract:
A method for designing a layout of a semiconductor device, comprising the steps of:a) preparing a first layout corresponding to a first netlist and including a component layout and a number n of, or first to nth (where n&gE;2), interconnection planar layouts to be sequentially stacked on the component layout; b) receiving a second netlist, which is different from the first netlist; c) selecting at least one of the interconnection planar layouts from the first layout, the number of the interconnection planar layouts selected being equal to or smaller than nâˆ’1; and d) producing a second layout, corresponding to the second netlist, by changing the physical arrangement of the at least one interconnection planar layout selected, the second layout including the component layout, the at least one interconnection planar layout with the changed arrangement, and the other interconnection planar layouts that have not been selected from the first layout.