Patent ID: 6624664
Filing Date: 2003-09-23
Classification: H03K

Abstract:
A cascaded chain of modified full-rail differential logic circuits comprising:a first supply voltage; a second supply voltage; a first modified full-rail differential logic circuit, said first modified full-rail differential logic circuit comprising: a first modified full-rail differential logic circuit out terminal; a first modified full-rail differential logic circuit outBar terminal; a first modified full-rail differential logic circuit first node, said first modified full-rail differential logic circuit first node being coupled to said first supply voltage; a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first modified full-rail differential logic circuit first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said first modified full-rail differential logic circuit out terminal; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first modified full-rail differential logic circuit first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first modified full-rail differential logic circuit outBar terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said first modified full-rail differential logic circuit outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said first modified full-rail differential logic circuit out terminal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; said fourth transistor first flow electrode being coupled to said first modified full-rail differential logic circuit first node, said fourth transistor second flow electrode being coupled to said first modified full-rail differential logic circuit out terminal, said fourth transistor control electrode being coupled to a first clock signal; a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; said fifth transistor first flow electrode being coupled to said first modified full-rail differential logic circuit first node, said fifth transistor second flow electrode being coupled to said first modified full-rail differential logic circuit outBar terminal, said fifth transistor control electrode being coupled to said first clock signal; a first modified full-rail differential logic circuit sense amplifier circuit coupled between said first modified full-rail differential logic circuit out terminal and said first modified full-rail differential logic circuit outBar terminal, said first modified full-rail differential logic circuit sense amplifier circuit having an input terminal coupled to a second clock signal; a logic block, said logic block comprising: at least one logic block input terminal; a logic block out terminal; and a logic block outBar terminal, said logic block out terminal being coupled to said first modified full-rail differential logic circuit out terminal and said logic block outBar terminal being coupled to said first modified full-rail differential logic circuit outBar terminal; a second modified full-rail differential logic circuit, said second modified full-rail differential logic circuit comprising: a second modified full-rail differential logic circuit out terminal; a second modified full-rail differential logic circuit outBar terminal; a second modified full-rail differential logic circuit first node, said second modified full-rail differential logic circuit first node being coupled to said first supply voltage; a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said second modified full-rail differential logic circuit first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said second modified full-rail differential logic circuit out terminal; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second modified full-rail differential logic circuit first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said second modified full-rail differential logic circuit outBar terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said second modified full-rail differential logic circuit outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said second modified full-rail differential logic circuit out terminal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; said fourth transistor first flow electrode being coupled to said second modified full-rail differential logic circuit first node, said fourth transistor second flow electrode being coupled to said second modified full-rail differential logic circuit out terminal, said fourth transistor control electrode being coupled to said second clock signal; a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; said fifth transistor first flow electrode being coupled to said second modified full-rail differential logic circuit first node, said fifth transistor second flow electrode being coupled to said second modified full-rail differential logic circuit outBar terminal, said fifth transistor control electrode being coupled to said second clock signal; a second modified full-rail differential logic circuit sense amplifier circuit coupled between said second modified full-rail differential logic circuit out terminal and said second modified full-rail differential logic circuit outbar terminal, said second modified full-rail differential logic circuit sense amplifier circuit having an input terminal coupled to a third clock signal; a logic block, said logic block comprising: at least one logic block input terminal; a logic block out terminal; and a logic block outBar terminal, said logic block out terminal being coupled to said second modified full-rail differential logic circuit out terminal and said logic block outBar terminal being coupled to said second modified full-rail differential logic circuit outBar terminal, wherein; said second clock signal is delayed with respect to said first clock signal by a predetermined delay time and said third clock signal is delayed with respect to said second clock signal by a predetermined delay time.