Patent ID: 6408356
Filing Date: 2002-06-18
Classification: G11C

Abstract:
A method of controlling the operation of memory in a computer system with signals from a memory controller which outputs Y row address signals and first and second address control signals, and wherein said memory is comprised of DRAM chips having Y+1 bit row addresses and is actuated by a single address control signal, said method comprising the steps of:providing said first address control signal in combination with at least one of said address signals from said computer system as the high order bit of said Y+1 address, forming a master address control signal which becomes active responsive to either of said first or second address control signals becoming active, said method being further characterized by said system performing refresh operations on each row address individually, sequentially based on both said first and second address control signals becoming active at the same time, and controlling the application of said first address control signal as said high order bit of said address during a refresh cycle to provide refresh to each row after a given number of refresh cycles.