Patent ID: 8615702
Filing Date: 2013-12-24
Classification: G06F

Abstract:
1. A memory controller, comprising: a control unit that analyzes read data received from a memory device and first error correction code (ECC) data of the read data, and generates multiple units of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than the number of error bits that can be corrected by using the first ECC data, wherein the multiple units of sub-data are generated by dividing the write data into multiple sub-units and padding each of the sub-units of write data with additional bits to produce a corresponding one of the units of sub-data; and an ECC block that generates the first ECC data and second ECC data by using the same algorithm to correct errors in different units of the sub-data, wherein the control unit transmits each of the units of sub-data, the first ECC data and the second ECC data to the memory device.