Patent ID: 6728871
Filing Date: 2004-04-27
Classification: B01J,C01B,G06F,Y02D,Y10S

Abstract:
A directly addressable configurable unit that can be reconfigured at run time controlled by a primary logic unit (PLU) for processing arithmetic and logic operations (PAE) for use in central processing units (CPUs), multi-processor systems, data flow processors (DFPs), digital signal processors (DSPs), systolic processors and field programmable gate arrays (FPGAs), characterized in thata. a programmable arithmetic and logic unit (EALU) is provided for performing the basic mathematical and logic functions, b. the function and interconnection of the central processor are programmed in directly addressable registers and various data can be processed without reprogramming the PAE, c. there is a state machine (SM UNIT) for controlling the arithmetic and logic unit (EALU), d. registers are provided for each operand (O-REG) and the result (R-REG), some of the registers being designed as shift registers, e. there is feedback of the data of the result register to an input of the EALU over a multiplexer (R2O-MUX), f. a bus unit (BM UNIT) permits pick-up of data from a bus system and feeding the result to a bus system, the bus unit being capable of sending data to multiple receivers and the synchronization of multiple receivers taking place automatically, g. the bus access from the data processing in the EALU is decoupled via the registers and thus each PAE can be regarded as an independent unit, in particular the configuration and reconfiguration of a PAE have no interfering effect on the data transmitters and receivers or on the independent PAEs, h. the sequence of bus transfers is controlled automatically using a state machine (sync UNIT), for which purpose handshake lines oRDY, oACK, rRDY and rACK are available, and i. feedback is sent to the PLU for detection of the processing status and reconfigurability of the PAE (state-back UNIT).