Patent ID: 6492208
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method of providing an intrinsic parasitic SCR protection device for an output and input pad of transistor circuit, comprising the steps of:forming an n-well in a p-substrate; placing gates, one each, to either side of said n-well; implanting, on either side of said gates, sources and drains for a first and a second n-channel transistor, such that each of said drains straddles halfway either edge of said n-well and said sources are implanted in said p-substrate; implanting a p+ diffusion between said drains of said first and said second n-channel transistor, said drains in close proximity to said p+ diffusion; connecting said gates and said sources to a voltage reference; connecting said p+ diffusion and said drains to a chip pad; and utilizing said intrinsic parasitic SCR to protect said transistor circuit from electrostatic discharge (ESD).