Patent ID: 6078546
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A data input circuit for a synchronous semiconductor memory device having a memory cell array, comprising:a first edge detector for generating a first internal strobe signal and a second internal strobe signal responsive to an external data strobe signal;a second edge detector for generating a first internal clock signal and a second internal clock signal responsive to an external clock signal;a selector for selecting either the first and second internal strobe signals or the first and second internal clock signals in response to a selection control signal;a register circuit having first and second registers, the first register for storing odd-numbered data of an externally applied data string responsive to the selected signals and the second register for storing even-numbered data of the data string responsive to the selected signals;a delay circuit for generating a delayed clock signal by delaying one of the internal clock signals; anda data write driver having first and second write drivers, the first write driver for writing the odd-numbered data from the first register into the memory cell array responsive to the delayed clock signal and the second write driver for writing the even-numbered data from the second register into the memory cell array responsive to the delayed clock signal.