Patent ID: 6499093
Filing Date: 2002-12-24
Classification: G06F

Abstract:
A memory control unit coupled during use to a system bus for receiving memory addresses therefrom, said memory control unit further being coupled during use to one or more memory units by a second bus, the second bus including a plurality of signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units, each of said one or more memory units being comprised of a plurality of semiconductor memory devices having a plurality of addressable memory storage locations, said memory control unit further comprising means, based on a signal asserted by one of the memory units selected by a transmitted memory unit select address, the asserted signal indicating an access speed of the selected memory unit, for specifying a duration of the memory access cycle so as to make a duration of the memory access cycle compatible with the access speed of at least the semiconductor memory devices of the selected memory unit.