Patent ID: 6841983
Filing Date: 2005-01-11
Classification: G05F,H02J,H02M,H03M,H05B,Y02B

Abstract:
1. A digital signal to pulse converter, comprising: a spectral spreader for receiving a first clock signal and providing an adjusted clock signal, wherein the adjusted clock signal cycles according to the first clock signal except for selected cycles of the first clock signal, and wherein the adjusted clock signal does not cycle during these selected cycles; a counter configured to cyclically count through N counts responsive to the adjusted clock signal and provide the current count as an output signal; and a content addressable memory having at least a write port and a read port, wherein the write port is used to write a first set of data into the content addressable memory as stored data, and the read port is used to receive the current count, with the content addressable memory comparing the stored data with current count and, if a match occurs, providing output signals that determine a beginning or an end of a pulse, whereby each pulse is defined in a frame having a frame rate of the count rate divided by N; wherein the spectral spreader is configured to vary the number of selected cycles to adjust the frame rate as desired.