Patent ID: 9184749
Filing Date: 2015-11-10
Classification: G11C,H03K,H04L

Abstract:
1. An impedance calibration circuit comprising: a first logic unit suitable for generating a first reset signal enabled when at least one of an external command signal and an operation delay signal is enabled; a latch pulse generator suitable for generating a latch pulse signal enabled when temperature code signals having a logic combination corresponding to a second temperature are inputted thereto after the temperature code signals haying a logic combination corresponding to a first temperature are inputted thereto; a control signal generator suitable for generating the operation control signal which is initialized in response to the first reset signal and which is enabled in response to the latch pulse signal; a first delay unit suitable for retarding the operation control signal by a predetermined delay time to generate the operation delay signal; and an impedance calibrator suitable for receiving the external command signal or the operation control signal to generate pull-up code signals for pulling up an output signal and pull-down code signals for pulling down the output signal according to an external resistor.