Patent ID: 6178214
Filing Date: 2001-01-23
Classification: H04L

Abstract:
A synchronizing system comprising:demodulating means receiving a received signal for demodulating said received signal to produce a demodulated signal having a CRC bit;CRC bit end judging means connected to said demodulating means for judging an end of said CRC bit of said demodulated signal to produce a CRC bit end signal;received signal level detecting means receiving said received signal for detecting a level of said received signal to produce a detected level signal having a detected level;level comparing means connected to said received signal level detecting means for comparing said detected level of said detected level signal with a predetermined threshold level to produce a level compared result signal when said detected level is greater than said predetermined threshold level;masking means connected to said CRC bit end judging means and to said level comparing means for masking, in a predetermined time interval, said level compared result signal when said masking means is supplied with both of said CRC bit end signal and said level compared result signal, said masking means producing a trigger signal when said masking means is supplied with said level compared result signal after said predetermined time interval; andsynchronizing means connected to said demodulating means and to said masking means for synchronizing said demodulated signal with said received signal by producing and supplying, in response to said trigger signal, a bit synchronous signal to said demodulating means.