Patent ID: 8539290
Filing Date: 2013-09-17
Classification: G11C

Abstract:
1. An integrated circuit, comprising: A. a memory array arranged in separate memory array banks, each bank having separate bank data, bank address, and bank control leads; B. wrapper and control circuitry having memory leads for the bank data, bank address, and bank control leads of each bank of the memory array and having interface address and data leads; C. test controller circuitry having test leads for the bank data, bank address, and bank control leads of each bank of the memory array; and D. isolation logic arranged in separate banks, one isolation logic bank for each memory array bank, each isolation logic bank having memory leads connected to the memory leads of the wrapper and control circuitry, having test leads connected to the test leads of the test controller circuitry, and having bank leads connected only to the bank address and bank control leads of one memory array bank, each isolation logic bank including gating and multiplexer circuits and having a separate test enable input lead.