Patent ID: 8673782
Filing Date: 2014-03-18
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a NAND flash memory device, the method comprising: forming a conductive layer on a semiconductor substrate; forming a plurality of first mask patterns on the substrate, the first mask patterns comprising first linear portions extending in parallel along a first direction and second linear portions extending in parallel from respective ends of the first linear portions along a second direction; forming sidewall spacers on sidewalls of the mask patterns; forming second mask patterns covering portions of the first mask patterns and the sidewall spacers proximate corners at which the first linear portions and the second linear portions of the first mask patterns meet; etching the first mask patterns using the second mask patterns as an etching mask to remove portions of the first mask patterns not covered by the second mask patterns and to leave the sidewall spacers and portions of the first mask patterns underlying the second mask patterns; etching the conductive layer using the sidewall spacers and the remaining portions of the first mask patterns as etching masks to form a plurality of continuous conductors comprising respective conductive lines extending in parallel along the first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along the second direction.