Patent ID: 7560775
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A transistor comprising: a device formation region provided on a semiconductor substrate; a device isolation film comprising a dielectric film and which defines the device formation region; a gate insulator formed in the device formation region; and a gate electrode which is formed on the gate insulator and which extends over the whole surface of the device isolation film, wherein a surface of the device isolation film on which the gate electrode extends is formed higher in a thickness direction than a surface of the gate insulator, and a thickness of the gate electrode at a boundary between the device isolation film and the gate insulator is larger than a thickness of the gate electrode at a position away from the boundary toward the gate insulator side, wherein the device isolation film has a flat portion provided inner than a boundary at which the device isolation film adjoins the gate insulator as viewed in a plan view, the flat portion being formed higher in a thickness direction than at the boundary and extending in a planar direction of the semiconductor substrate, and a height difference A between a surface of the device isolation film, on which the gate electrode extends, and a surface of the gate insulator, a widthwise distance B from an end of the flat portion of the device isolation film to the boundary, and a thickness D of the gate electrode of the device formation region satisfy following Equations (1) and (2):