Patent ID: 7308564
Filing Date: 2007-12-11
Classification: G06F

Abstract:
1. In an integrated circuit comprising a programmable logic portion and a processor core, a method comprising: configuring a first portion of the programmable logic portion to realize a performance monitor for monitoring the processor core; configuring a second portion of the programmable logic portion to realize a first portion of a user-specific circuit comprising a portion of the user-specific circuit selected to interact with the processor core; executing software code on the processor core to interact with the first portion of the user-specific circuit; using the performance monitor to monitor the processor core; wherein the performance monitor comprises a counter that monitors speed of the processor core interacting with the first portion of the user-specific circuit, the counter having a higher speed portion and a lower speed portion, wherein the higher speed portion is implemented in hardwired circuitry, and the lower speed portion is implemented in the programmable logic portion; and reconfiguring the first portion of the programmable logic portion with a second portion of the user-specific circuit, wherein the lower speed portion of the performance monitor is removed and the integrated circuit comprises a complete user-specific circuit.