Patent ID: 8686489
Filing Date: 2014-04-01
Classification: H01L

Abstract:
1. A memory cell comprising: a transistor comprising a pair of source/drain regions in a substrate and a floating gate wherein a first source/drain region is coupled to a read data line; a first metal-insulator metal capacitor coupled between the floating gate and a wordline; and a second metal-insulator-metal capacitor coupled between the floating gate and a write/erase data line wherein the write/erase data line is separate from the source/drain regions in the substrate and physically separated from a vertical stack of the floating gate and the wordline over the substrate by the second metal-insulator-metal capacitor and further wherein the write/erase data line is only in a vertical plane and the floating gate is only in a horizontal plane such that no portion of the write/erase data line overlies the floating gate.