Patent ID: 6112267
Filing Date: 2000-08-29
Classification: G06F

Abstract:
An apparatus for buffering data transmitted by a processor and received by an I/O device via a memory and buses, the memory arranged at a plurality of levels, a lower level of the memory operating faster than a higher level of the memory, comprising:a plurality of buffers allocated at different levels of the memory, the buffers being coupled to the processor and the I/O device such that the processor and the I/O device can simultaneously access the same buffer;means for selecting an available buffer of the plurality of buffers at a lowest possible level of the memory as a write buffer, the write buffer storing data transmitted by the processor; andmeans for selecting a buffer of the plurality of buffers as a read buffer, the read buffer storing data to be received by the I/O device,wherein at least a portion of the data transmitted by the processor to the write buffer and at least a portion of the data received by the I/O device from the read buffer are simultaneously directed at different buffers located at different levels in the memory.