Patent ID: 9000599
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A package assembly comprising: a package substrate with a plurality of build-up layers; a first die embedded in the package substrate, the first die having a first side with one or more transistors, a second side opposite to the first side, a first through silicon via (TSV), and an electrical routing feature disposed on a first portion of the second side, wherein the electrical routing feature is electrically coupled with at least one transistor of the one or more transistors by the first TSV; an adhesive layer disposed on a second portion of the second side of the first die; and a second die coupled with the adhesive layer, the second die having a second TSV, wherein: the second TSV is electrically coupled with the first TSV; the second die is a memory die; the electrical routing feature is a TSV pad; the first TSV is one of a first plurality of TSVs of the first die; and the second TSV is one of a second plurality of TSVs of the second die that correspond with and are arranged in vertical alignment with the first plurality of TSVs.