Patent ID: 6532524
Filing Date: 2003-03-11
Classification: G06F

Abstract:
An apparatus comprising:a first compare circuit configured to present a first match signal in response to a first address and a second address; a second compare circuit configured to present a second match signal in response to said first match signal, a first write enable signal and a second write enable signal; and a memory configured to (i) store and retrieve data in response to said second match signal and (ii) present said first and second write enable signals, wherein (a) said memory comprises (i) a first read/write control circuit, (ii) a second read/write control circuit, and (iii) a core configured to read and write data and (b) said first read/write control circuit is configured to control a first portion of said core and said second read/write control circuit is configured to control a second portion of said is core.