Patent ID: 8242808
Filing Date: 2012-08-14
Classification: G11C,H03K

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing information; a plurality of word lines associated with said plurality of rows, respectively; and a word line driving circuit defines selection/non-selection of said plurality of word lines, wherein the plurality of word lines includes a first word line and a second word line being adjacent to each other in a column direction, wherein the word line driving circuit includes: the first output signal driving portion has a first inverter circuit comprised a first transistor of a first conductive type and a second transistor of a second conductive type, wherein the second output signal driving portion has a second inverter circuit comprised a third transistor of the first conductive type and a fourth transistor of the second conductive type, wherein the first transistor is arranged in a first formation region, the second transistor and the fourth transistor are arranged in a second formation region, the third transistor is arranged in a third formation region, wherein the second formation region is between the first formation region and the third formation region in a row direction crossing the column direction, wherein the first high voltage imparting portion imparts the high voltage via each of first and second switching elements coupled in series and has a third switching element set to an ON state in a predetermined initial period after initiation of a non-selected state to impart the high voltage to the first potential setting node, wherein the second high voltage imparting portion imparts the high voltage via each of fourth and fifth switching elements coupled in series and has a sixth switching element set to an ON state in a predetermined initial period after initiation of a non-selected state to impart the high voltage to the second potential setting node.