Patent ID: 8049259
Filing Date: 2011-11-01
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: element regions each of which is surrounded by an element isolation region, the element regions having transistor regions and capacitor regions; MOS transistors each of which is formed on one of the transistor regions, each of the MOS transistors having a source, a drain, and a gate; capacitor elements each of which is formed on one of the capacitor regions; a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to one of the MOS transistors via either of the source and the drain thereof, the voltage generating circuit outputting a voltage from a first MOS transistor in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second MOS transistor in a previous stage in the series connection; a first impurity-doped region which is formed on at least either of the source and the drain; a contact plug which is formed on the first impurity-doped region to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance between the gate and the first impurity-doped region for the first MOS transistor being larger than that for the second MOS transistor; and a memory cell which is capable of holding data, the voltage output by the voltage generating circuit being applied to the memory cell.