Patent ID: 6605511
Filing Date: 2003-08-12
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor chip having a plurality of flash memory devices, comprising:providing a silicon semiconductor substrate; forming at least one periphery stack, comprising forming a thin gate oxide layer and forming at least one polysilicon (poly-Si) layer, on a periphery region only of said substrate, said thin gate oxide layer forming comprising forming said thin gate oxide layer as an un-nitridated thin gate oxide layer; forming at least one periphery stack, comprising forming a thick gate oxide layer and forming at least one polysilicon (poly-Si) layer, on the periphery region only of said substrate, said thick gate oxide layer forming comprising forming said thick gate oxide layer as an un-nitridated thick gate oxide layer; forming at least one core stack, comprising forming a nitridated tunnel oxide barrier layer, forming at least two polysilicon (poly-Si) layers, and forming an interpoly dielectric layer, on a core region only of said substrate; forming at least one shallow trench isolation (STI) in the periphery region only of said substrate; and forming at least one local oxidation of silicon (LOCOS) isolation in the core region only of said substrate, said thick gate oxide layer forming step comprising forming said thick gate oxide layer to have a thickness distinct from that of said thin gate oxide layer in said thin gate oxide layer forming step.