Patent ID: 6111712
Filing Date: 2000-08-29
Classification: G11B,H03L

Abstract:
A data channel circuit for processing data of a data storage medium, comprising:at least a first circuit coupled to at least a first clock signal, the first circuit processing data to be read from or written to the data storage medium;at least a second circuit coupled to at least a second clock signal, the second circuit processing data to be read from or written to the data storage medium; anda frequency synthesizer generating the first clock signal and the second clock signal, the frequency synthesizer comprising,a first phase locked loop circuit, the first phase locked loop circuit receiving a reference clock signal and having a first phase locked loop output signal,a second phase locked loop circuit, the second phase locked loop circuit receiving as an input the first phase locked loop output signal and the second phase locked loop providing as an output the first clock signal; anda third phase locked loop circuit, the third phase locked loop circuit receiving as an input the first phase locked loop output signal and providing as an output the second clock signal,wherein the first clock signal is at least one of a read clock signal, a write clock signal or a servo clock signal, and the second clock is at least one of a read clock signal, a write clock signal or a servo clock signal, and wherein both the read clock signal and the write clock are provided from either the second or third phase locked loop circuits.