Patent ID: 6259650
Filing Date: 2001-07-10
Classification: G06F,G11C

Abstract:
A plurality of signals suitable for use in the control of a memory, comprising:a first clock signal having a first period;a second clock signal having a second period, wherein the second clock signal is asynchronous to the first clock signal;a first address signal identifying a memory location in a memory, wherein the first address signal operates based upon the first clock signal;a first synchronization signal that indicates when the first address signal identifies a new memory location, wherein the first synchronization signal operates based upon the first clock signal;a second synchronization signal that indicates when the first address signal identifies the new memory location, wherein the second synchronization signal operates based upon the second clock signal; anda second address signal identifying a memory location in the memory, wherein the second address signal operates based upon the second clock signal and the second address signal identifies the new memory location after the second synchronization signal indicates that the first address signal identifies the new memory location.