Patent ID: 6987775
Filing Date: 2006-01-17
Classification: G06F,H04L

Abstract:
1. A variable size first in first out (FIFO) memory comprising: a head FIFO memory including a sequential sprinkler engine for sequentially delivering data packets as delivered data packets to a plurality of switching elements at a slow rate relative to the head FIFO memory whereby some latency occurs between said delivered data packets, the switching elements operating at the slow rate; a tail FIFO memory for storing an overflow of said data packets from said head FIFO memory and for receiving incoming data packets; both said head FIFO memory and said tail FIFO memory operating at a relatively high data rate equivalent to a rate of the incoming data packets; a large capacity buffer memory having an effectively lower clock rate than said head FIFO memory and said tail FIFO memory, the large capacity buffer memory for temporarily storing data overflow from said tail FIFO memory; said head FIFO memory and said tail FIFO memory in combination with said buffer memory forming the variable size FIFO memory.