Patent ID: 6607935
Filing Date: 2003-08-19
Classification: H01L

Abstract:
A method of fabricating an array substrate, comprising:forming a gate line, having a gate electrode and a gate pad, on a substrate; forming a first insulation layer on the gate line, on the gate electrode, on the gate pad and on the substrate; forming an active layer and an ohmic contact layer on the first insulation layer and over the gate electrode; forming source and drain electrodes, a data line and a ground line, wherein the source and drain electrodes extend over the active layer, wherein the data line is electrically connected to the source electrode, wherein the data line and the source line define a pixel region, and wherein the ground line crosses the pixel region; etching a portion of the ohmic contact layer on the active layer so as to form a channel region using the source and drain electrode as masks; forming a first capacitor electrode and a first etching stopper, wherein the first capacitor electrode is in the pixel region and electrically contacts the ground line, and wherein the first etching stopper is formed parallel to the data line near the gate pad and crosses the gate line to cover a portion of the gate line; forming a protection layer on the source and drain electrodes, on the first capacitor electrode, and on the first etching stopper; forming a second capacitor electrode on the protection layer and over the first capacitor electrode, wherein the second capacitor electrode corresponds in size to the first capacitor electrode; forming a second insulation layer on the protection layer and on the second capacitor electrode; and forming a cutting furrow to the first etching stopper by etching the second insulation layer and the protection layer, wherein the cutting furrow has the same shape as the first etching stopper; depositing a conductive material on the second insulation layer and in the cutting furrow; and removing at least a portion of the conductive material in the cutting furrow, at least a portion of the first etch stopping layer, and a portion of the first insulation layer so as to expose a portion of the gate line.