Patent ID: 8179159
Filing Date: 2012-05-15
Classification: H01L,H03K

Abstract:
1. A method of configuring a stacked integrated circuit (“IC”) comprising: providing a frame having configuration frame data and a configuration frame address in a frame header to a first integrated circuit die of the stacked IC, wherein the first integrated circuit die includes configurable logic; storing the configuration frame data in a frame data register of the first integrated circuit die; processing the frame header to determine whether a frame destination is for configurable logic in the first integrated circuit die or is in a second integrated circuit die that is stacked on the first integrated circuit die and electrically coupled to the first integrated circuit die through an array of inter-chip contacts; in response to determining that the frame destination is in the second integrated circuit die, providing the configuration frame address to the second integrated circuit die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the configuration frame data from the frame data register of the first integrated circuit die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.