Patent ID: 7030643
Filing Date: 2006-04-18
Classification: H03K

Abstract:
1. A buffer circuit comprising; an output terminal; a pull-up transistor connected between the output terminal and a supply voltage, wherein the pull-up transistor pulls the output terminal up to the supply voltage responsive to a pull-up control signal; a pull-down transistor connected between the output terminal and a reference voltage, wherein the pull-down transistor pulls the output terminal down to the reference voltage responsive to a pull-down control signal; a first logic gate configured to generate the pull-up control signal at a first output node responsive to a control signal and a data signal, and wherein the first logic gate includes a plurality of serially connected transistors in an electrical path between the supply voltage and the first output node; and a second logic gate configured to generate the pull-down control signal at a second output node responsive to the data signal and an inverse of the control signal and wherein the second logic gate includes a plurality of serially connected transistors in a path between the supply voltage and the second output node; wherein the number of serially connected transistors in the path between the supply voltage and the first output node is equivalent to the number of serially connected transistors in the path between the supply voltage and the second output node; wherein the plurality of serially connected transistors in the electrical path between the supply voltage and the first output node comprises a first transistor having a first control electrode connected to the data signal and a second transistor coupled in series between the supply voltage and the first transistor, the first logic gate further comprising a third transistor connected in parallel with the first transistor between the second transistor and the first output node, wherein the third transistor has a third control electrode connected to the control signal.