Patent ID: 6076150
Filing Date: 2000-06-13
Classification: G06F

Abstract:
A computer system comprising:a CPU;a cache memory connected to said CPU;a main memory; anda cache controller unit coupled to said CPU, the cache controller unit coupled to said main memory by a first data bus and to said cache memory with a second data bus, said cache controller unit having circuit means for generating first control signals for transferring a line of information from said main memory to the cache controller through the first data bus and from the cache controller to said cache memory through the second data bus when a first word of information is requested by said CPU, said cache controller unit also having circuit means generating second control signals for said CPU is found anywhere within said cache memory, whereby said second word of information is received by said CPU prior to completion of said transfer of said line of information;wherein said second control signals generating circuit means comprises a matching circuit for comparing an address of said word of information requested by said CPU and an address of a word of information in said line of information being transferred to said cache memory from said main memory, said matching circuit generating said second control signal when said addresses match; andwherein said matching circuit comprises a first register for holding an address of said second word of information requested by said CPU, a second register for holding an address of a word of information in said line of information being transferred to said cache memory from said main memory, and a comparison circuit connected to said first and second registers for generating said control signal when said addresses match.