Patent ID: 6058439
Filing Date: 2000-05-02
Classification: G06F

Abstract:
Apparatus for data processing comprising:(i) a first circuit block operating under control of a first clock signal at a first clock frequency;(ii) an asynchronous first-in-first-out buffer circuit coupled to said first circuit block for receiving data words from said first circuit block, said asynchronous first-in-first-out buffer circuit comprising a plurality of buffer stages; and(iii) a second circuit block operating under control of a second clock signal at a second clock frequency and coupled to said first-in-first-out buffer circuit for receiving data words from said first-in-first-out buffer circuit, said second clock signal having no fixed phase relationship with said first clock signal and said second clock frequency being equal to or less than said first clock frequency; wherein(iv) said first circuit block loads data words into said asynchronous first-in-first-out buffer circuit in a burst mode in which a data word is loaded into said asynchronous first-in-first-out buffer circuit with each cycle of said first clock signal without a determination always being available as to whether said data word is a last data word in a burst;(v) said first circuit block loads a burst marker into said asynchronous first-in-first-out buffer circuit with each data word, said burst marker having a first value when accompanying one of a first data word in a burst of data words or an empty buffer stage and said burst marker having a second value when accompanying a second or subsequent data word in a burst of data words; and(vi) said second circuit block is responsive to said burst markers to identify an end of a burst of data words.