Patent ID: 7312137
Filing Date: 2007-12-25
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a transistor, the method comprising: providing a workpiece, the workpiece having a top surface; implanting germanium into the top surface of the workpiece so that the highest concentration of germanium is at the top surface of the workpiece with the concentration gradually decreasing as the distance from the top surface increases, said implanting further forming a first germanium-containing region extending from the top surface of the workpiece, said forming a first germanium-containing region comprises forming an amorphous germanium-containing region, and forming a second germanium-containing region beneath the first germanium-containing region, said forming a second germanium-containing region comprises forming a first crystalline germanium-containing region, the first germanium-containing region extending a first depth beneath the workpiece top surface, the second germanium-containing region having a second depth extending below the first depth, the first and second depth comprising about 100 Å or less below the top surface of the workpiece; depositing a gate dielectric material over the first germanium-containing region; depositing a gate material over the gate dielectric material; patterning the gate material and gate dielectric material to form a gate and a gate dielectric over the first germanium-containing region; and forming a source region and a drain region in at least the first germanium-containing region.