Patent ID: 7162612
Filing Date: 2007-01-09
Classification: G06F

Abstract:
1. An apparatus in a microprocessor for executing native instructions that are provided directly to the microprocessor via an external instruction bus, the apparatus comprising: instruction translation logic, configured to retrieve macro instructions provided via the external instruction bus, and configured to translate each of said macro instructions into associated native instructions for execution, wherein, if a first form of a first macro instruction is retrieved, said instruction translation logic directs the microprocessor to enable a native bypass mode and indicates such by asserting a first bit within a control register; and bypass logic, coupled to said instruction translation logic, configured to access said first bit within said control register to determine if said native bypass mode has been enabled, and to detect wrapper macro instructions and, upon detection of said wrapper macro instructions, to disable said instruction translation logic, and to provide the native instructions for execution by the microprocessor, thereby bypassing said instruction translation logic; wherein said wrapper macro instructions are existing macro instructions which are translated by said instruction translation logic according to architectural specifications if said native bypass mode has not been enabled.