Patent ID: 8253458
Filing Date: 2012-08-28
Classification: H03L

Abstract:
1. A method for operating a digital phase locked loop (DPLL), the DPLL including a binary controller, a thermometric controller, a current controlled oscillator (CCO), and first and second sets of current sources, the method comprising: generating an output signal by the CCO based on a magnitude of a current signal provided by the first and the second sets of current sources; reducing a frequency of the output signal by a predetermined factor to generate a feedback signal; comparing the frequency and phase of an externally generated reference signal with the feedback signal to generate an error signal; generating first and second control words using the error signal, wherein the first and second control words have at least one bit; generating binary current control word bits and thermometric current control word bits based on the first and second control words respectively; controlling switching of the first set of current sources prior to a frequency lock using the binary current control word bits, wherein the thermometric current control word bits are fixed at a predetermined value, wherein the frequency lock represents a condition in which the frequency of the reference signal is equal to the frequency of the feedback signal; and controlling switching of the second set of current sources subsequent to the frequency lock based on the thermometric current control word bits, wherein the binary current control word bits are fixed when the frequency lock is achieved.