Patent ID: 8102030
Filing Date: 2012-01-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having an n-channel type transistor region and a p-channel type transistor region; an element isolation region formed in a surface portion of said semiconductor substrate, said element isolation region defining an n-MOS active region in said n-channel type transistor region and a p-MOS active region in said p-channel type transistor region; an n-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said n-MOS active region and defining an n-MOS channel region under said n-MOS gate electrode structure; a p-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said p-MOS active region and defining an p-MOS channel region under said p-MOS gate electrode structure; a contact etch stopper film having a compressive stress, formed above said semiconductor substrate and covering said n-MOS gate electrode structure and said p-MOS gate electrode structure; and a stress released region selectively formed in said contact etch stopper film above a whole portion of said n-MOS active region and above said element isolation region surrounding said p-MOS active region, said stress released region releasing stress in said contact etch stopper film, wherein said contact etch stopper film maintains compressive stress only above said p-MOS active region, and exerts compressive stress along gate length direction and tensile stress along gate width direction to said p-MOS channel region.