Patent ID: 7760001
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. A signal processing apparatus comprising: a storage section to store preset positive integers A, B and C, a k-number of offset values Fi (i=1 to k) and the number of additions Ei of each offset value Fi; a real number counter being an integer addition ring counter to subtract the positive integer C if a count value is equal to or larger than 0 and to add a difference (B−C) of the positive integer B and the positive integer C and output a Carry if the count value is negative, at each input clock; a first integer counter being an integer addition ring counter to add its count value IC a first pulse generation circuit to generate a first clock with one cycle corresponding to a period for the first integer counter to return to its initial state according to the count value IC a correction circuit to repeatedly output the offset value Fi stored in the storage section in each correction period having the same length as a cycle D (D is a positive integer) of the first clock and output one of the offset values Fi whose number of outputs in the correction period is equal to or smaller than the number of additions Ei in synchronization with the input clock in each correction period; a second integer counter being an integer addition ring counter to add its count value IC a second pulse generation circuit to generate a second clock with one cycle corresponding to a period for the second integer counter to return to its initial state according to the count value IC a frequency of the second clock is a multiple G (G>0) of a frequency of the first clock, the positive integer D is the number of cycles of the first clock indicating a synchronization cycle length of the first clock and the second clock, the positive integers A, B and C are set to satisfy Expression 1, and the offset value Fi and the number of additions Ei are set to satisfy Expression 2 and Expression 3: where f where D is a synchronization cycle length (a positive integer) of the first clock and the second clock represented by the number of cycles of the first clock, and where D is a synchronization cycle length (a positive integer)