Patent ID: 6097042
Filing Date: 2000-08-01
Classification: H01L

Abstract:
An integrated circuit gate array structure comprising:a semiconductor substrate including a plurality of first columns of semiconductor material of a first conductivity type and a plurality of second columns of semiconductor material of a second conductivity type;first active regions formed within the columns, which includes contacts to which conductive material can be connected;second active regions formed within the columns, which includes contacts to which conductive material can be connected;gate connection regions, each controlling a flow of current between a source and a drain which are formed in each of the active regions, wherein each gate connection region of said gate connection regions has a single gate connection pad region; andtap regions formed outside of the columns, each of the tap regions being associated with one pair of the columns, the tap regions being doped with an opposite conductivity type than columns which are adjacent to the tap regions thereby allowing current and voltage characteristics of the columns to be controlled, wherein the single gate connection pad region is formed at one end of the each gate connection region and the each gate connection region includes a poly end cap formed between the other end of the each gate connection region and each of the tap regions.