Patent ID: 6723601
Filing Date: 2004-04-20
Classification: H01L,Y10S

Abstract:
A method for manufacturing a semiconductor device, the method comprising the steps of:(a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistor and a first insulating layer formed around the conductive plugs; (b) forming a sacrificial layer on top of the active matrix and patterning said sacrificial layer into a predetermined configuration, thereby obtaining a patterned sacrificial layer; (c) forming spacers on sides of the patterned sacrificial layer; (d) forming a conductive layer on top of the patterned sacrificial layer, the spacers and the active matrix; (e) forming a photoresist layer on top of the conductive layer; (f) planarizing portions of the photoresist layer and the conductive layer placed on top of the patterned sacrificial layer until the patterned sacrificial layer is exposed, thereby opening portions of the conductive layer; (g) carrying out a carbon treatment on the opening portions of the conductive layer; (h) removing the sacrificial layer and the photoresist layer, thereby obtaining bottom electrode structures; and (i) forming hemispherical grained (HSG) silicon on side and bottom surfaces of the bottom electrode structures.