Patent ID: 7259415
Filing Date: 2007-08-21
Classification: H01L

Abstract:
1. A memory cell comprising: a substrate comprising silicon carbide of a first conductivity type; a pillar comprising silicon carbide of the first conductivity type extending vertically upward from the substrate; a source region comprising silicon carbide of a second conductivity type formed in the substrate adjacent a base of the pillar; a drain region comprising silicon carbide of the second conductivity type formed in an upper region of the pillar; a gate dielectric and conductor arranged along a first side of the pillar; and a capacitor dielectric and body capacitor plate arranged along an opposite, second side of only the same associated pillar wherein a depletion region is defined around the source region so to define a floating body region in the pillar between the drain and source regions and wherein a transistor structure is defined by the source region, the floating body region, the drain region, and the gate dielectric and conductor and wherein a capacitor structure is defined by the floating body and the capacitor dielectric and body capacitor plate.