Patent ID: 6333241
Filing Date: 2001-12-25
Classification: H01L

Abstract:
A method of fabricating a capacitor for a semiconductor memory device, comprising:forming a first insulating layer on a semiconductor substrate;forming an etch stopper on the first insulating layer;forming a contact plug in the etch stopper and the first insulating layer to be electrically connected to the semiconductor substrate;forming a second insulating layer on the etch stopper and the contact plug;etching the second insulating layer to form a trench which exposes the contact plug and a portion of the etch stopper outside the contact plug;forming conductive spacers for a storage node, on both sidewalls of the trench, the exposed etch stopper and a portion of the exposed contact plug,wherein the conductive spacers having a first sidewall surface being exposed and a second sidewall surface directly contacted with the second surface insulating layer; thenselectively forming an HSG (hemispherical grain) layer on the first sidewall surface of the conductive spacers and a remainder of the exposed contact plug, to increase an area of the capacitor, thereby completing a storage node; thenremoving a remainder of the second insulating layer until the etch stopper and the second sidewall surface of the conductive spacers are exposed;forming a dielectric film on at least the HSG layer and the second sidewall surface of the conductive spacers; and forming a plate node to complete the capacitor.