Patent ID: 8071456
Filing Date: 2011-12-06
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: a field effect transistor provided on a semiconductor substrate; a first interlayer insulating film for covering said field effect transistor; a second interlayer insulating film for covering said first interlayer insulating film; a phase change element having a phase change film capable of carrying out a phase change into a crystalline state and an amorphous state by a main current of said field effect transistor; and a multilayer wiring layer provided on said semiconductor substrate, said method comprising the steps of: (a) forming said first interlayer insulating film and then forming a plurality of first layer contact plugs which penetrates said first interlayer insulating film and is provided in contact with first and second diffusion layers of said field effect transistor; (b) forming a multilayer film constituting said phase change element over a whole surface of said first interlayer insulating film after said step (a); (c) forming a hard mask material over a whole surface of said multilayer film; (d) patterning said hard mask material to form a hard mask in a corresponding portion to a region on said multilayer film where said phase change element is formed; (e) patterning said multilayer film by using said hard mask, thereby forming said phase change element in a region including a first plug in said plurality of first layer contact plugs which reaches said first diffusion layer; (f) forming an etching stopper film over said whole surface of said first interlayer insulating film in a state in which said hard mask is left on said phase change element; (g) forming said second interlayer insulating film on said first interlayer insulating film after said step (f); (h) forming a plurality of contact holes reaching said etching stopper film on said phase change element and a second plug reaching said second diffusion layer in said plurality of first layer contact plugs through said second interlayer insulating film; (i) removing said etching stopper film in bottom parts of said plurality of contact holes, exposing an end face over said second plug and removing said hard mask in said phase change element together, thereby exposing an uppermost surface of said phase change element; (j) filling said plurality of contact holes with a conductor layer, thereby forming a plurality of second layer contact plugs; and (k) patterning a lowermost layer wiring of said multilayer wiring layer over said second interlayer insulating film after said step (j).