Patent ID: 6342410
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A method for fabricating a field effect transistor, the method including the steps of:A. forming a semiconductor pillar on a layer of insulating material, wherein a top surface and first and second side surfaces of said semiconductor pillar are exposed; B. forming a layer of dielectric material on said top surface and said first and second side surfaces of said semiconductor pillar; C. forming a layer of conductive material on said layer of dielectric material on said top surface and said first and second side surfaces of said semiconductor pillar; D. forming a dummy dielectric structure that covers a portion of said layer of conductive material such that a remaining portion of said layer of conductive material on said semiconductor pillar is exposed, said dummy dielectric structure having a predetermined sidewall on said layer of conductive material on said semiconductor pillar; E. depositing a layer of hardmask dielectric on top and on said predetermined sidewall of said dummy dielectric structure and on said remaining portion of said layer of conductive material that is exposed; F. anisotropically etching said layer of hardmask dielectric such that said hardmask dielectric remains at said predetermined sidewall of said dummy dielectric structure to form a spacer of hardmask dielectric; G. etching away said dummy dielectric structure such that said spacer of hardmask dielectric remains, said spacer of hardmask dielectric covering said layer of conductive material on said top surface and said first and second side surfaces of said semiconductor pillar at a gate portion of said semiconductor pillar; and H. etching away any exposed region of said layer of conductive material and said layer of dielectric material not covered by said spacer of hardmask dielectric such that said conductive material and said dielectric material remain on said top surface and said first and second side surfaces at said gate portion of said semiconductor pillar, wherein said conductive material that remains on said top surface and said first and second side surfaces at said gate portion of said semiconductor pillar forms a three-sided gate structure of said field effect transistor; and wherein said dielectric material that remains on said top surface and said first and second side surfaces at said gate portion of said semiconductor pillar forms a three-sided gate dielectric of said field effect transistor.