Patent ID: 6807502
Filing Date: 2004-10-19
Classification: G01R

Abstract:
A method for measure the effects of on-chip noise on signal propagation within an integrated circuit, said integrated circuit having a core logic area with a plurality of components therein, the method comprising:measuring an inactive operating frequency of a first test circuit, said first test circuit having a first plurality of elements connected by a first plurality of traces, said first test circuit being constructed to mimic a data path within said core logic area, said inactive operating frequency representing an operating reference signal; measuring an inactive operating frequency of a second test circuit, said second test circuit having a second plurality of elements connected by a second plurality of traces, said second plurality of traces being routed within said core logic area; measuring an inactive operating frequency of a third test circuit, said third test circuit having a third plurality of elements connected by a third plurality of traces, said third plurality of elements being randomly located within said core logic area; and measuring an inactive operating frequency of a fourth test circuit, said fourth test circuit having a fourth plurality of elements connected by a fourth plurality of traces, said fourth test circuit being constructed to mimic a data path within said core logic area, said fourth test circuit sharing a power source with at least one of said plurality of components within said core logic area, wherein said inactive operating frequencies of said first, second, third, and fourth test circuits represent one or more effects of on-chip noise on signal propagation.