Patent ID: 6509761
Filing Date: 2003-01-21
Classification: G06F,H03K

Abstract:
A logical circuit using a pair of signal lines different from power source lines for propagating a logical value, the pair of signal lines using an effective value and a halt value as signal values, the signal lines in the pair having mutually exclusive signal values if the signal value of the pair is the effective value and having an equal signal value if the signal value of the pair is the halt value, the signal value of said pair of signal lines changing from the halt value to the effective value and returning again from the effective value to the halt value if the one logical value is propagated, whereina basic logical gate realizing a feature of a logical function has not less than one pair of signal lines (20) as inputs and one pair of signal lines (21, 22) as outputs the basic logical gate outputs the halt value if the halt value is included in the inputs and outputs the effective value according to the feature of the logical function if all the inputs of the basic logical gate have the effective values and delay time generated until the signal values of the outputs change according to changes of the signal values of the inputs in the logical gate is constituted asymmetrically so that the delay time generated when the output of the basic logical gate changes from the halt value to the effective value is short and the delay time generated when the output of the basic logical gate changes from the effective value to the halt value is long.