Patent ID: 8243534
Filing Date: 2012-08-14
Classification: G11C

Abstract:
1. A semiconductor device comprising: a clock terminal to which a clock signal is supplied; a data strobe terminal to which a data strobe signal that indicates an input timing of write data is supplied; a mode register which can be set as a normal operation mode of receiving the write data synchronously with the data strobe signal and as a write leveling mode of measuring askew between the clock signal and the data strobe signal; a terminating resistance circuit connected to the data strobe terminal; a command terminal to which an ODT (On-Die Termination) signal that designates whether to activate the terminating resistance circuit is supplied; a skew detecting circuit that is activated in the write leveling mode, measures a skew between the clock signal and the data strobe signal, and outputs a result of measuring; and an ODT control circuit that activates the terminating resistance circuit based on the ODT signal, wherein the mode register has a register that designates whether to use a dynamic ODT function that dynamically changes a resistance of the terminating resistance circuit, the terminating resistance circuit has a first resistance mode set as a first resistance, and a second resistance mode set as a second resistance different from the first resistance, and the ODT control circuit selects the first resistance mode when the dynamic ODT function is in an unused state in the write leveling mode, and selects the second resistance mode when the dynamic ODT function is in a used state in the write leveling mode.