Patent ID: 6512264
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A flash memory semiconductor apparatus, said apparatus comprising:a. a semiconductor substrate; b. at least one region on said substrate member having a silicon dioxide layer; c. a silicon material deposited over said silicon dioxide layer, said silicon material and said silicon dioxide layer being formed into at least one partial stack portion of a flash memory element, said silicon material formed into said at least one stack portion comprising a first polysilicon layer of said flash memory element; d. a pre-interpoly dielectric treatment layer, said pre-interpoly dielectric treatment layer being formed over said first polysilicon layer; e. an interpoly dielectric member, said interpoly dielectric member being formed over said pre-interpoly dielectric treatment layer; and f. a second polysilicon layer, said second polysilicon layer being formed over said interpoly dielectric member and forming another fabricated stage of said flash memory element.