Patent ID: 8729617
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a lower pillar formed on a substrate extending in a first direction and having a lower pillar height in the second direction, wherein a trench is formed along a sidewall of the lower pillar in the first direction of the substrate; a buried bit line junction region disposed on one sidewall of a first portion of the lower pillar; an upper pillar having an upper pillar height in the second direction and formed on the second portion of the lower pillar; a buried bit line formed in the trench to contact the buried bit line junction region and; an etch stop film disposed on a surface of the buried bit line exposed over the trench; a first interlayer dielectric film having a height less than the upper pillar height and formed contiguous to the upper pillar on a portion of the etch stop film; a second interlayer dielectric film formed on the first interlayer dielectric film; and a gate formed adjacent to a sidewall portion of the upper pillar and over the buried bit line to extend in a third direction.