Patent ID: 8143150
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate, wherein the lower impurity region has a different conductivity type from a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region; etching the semiconductor substrate to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns, wherein the upper semiconductor patterns have sidewalls vertically arranged with facing sidewalls of the lower semiconductor patterns and facing each other, a first space between the upper semiconductor patterns projecting from the lower semiconductor patterns, and a second space between the lower semiconductor patterns having a bottom surface disposed at a lower level than the lower impurity region, and wherein top surfaces of the lower semiconductor patterns disposed between the upper semiconductor patterns are disposed at a lower level than the upper impurity region and disposed at a higher level than a bottom surface of the lower impurity region; and forming an isolation layer filling the first and the second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively.