Patent ID: 6706579
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which comprises a memory area having a non-volatile memory device and a logic circuit area having a peripheral circuit of the non-volatile memory device, the manufacturing method comprising the steps of:forming an element separating region on surface of a semiconductor layer to attain insulation between semiconductor elements; forming a first insulating layer above the semiconductor layer; forming a first conductive layer above the first insulating layer; forming a stopper layer above the first conductive layer; patterning the stopper layer and the first conductive layer in the memory area, while patterning the stopper layer and the first conductive layer in the logic circuit area to create a dummy gate layer on the element separating region in the logic circuit area; forming an ONO membrane over whole surface of the memory area and the logic circuit area; forming a second conductive layer above the ONO membrane; carrying out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area; patterning the first conductive layer in the logic circuit area other than the element separating region to create a gate electrode of an insulated gate field effect transistor in the logic circuit area; forming a second insulating layer over whole surface of the memory area and the logic circuit area; and polishing the second insulating layer to make the stopper layer in the memory area exposed.