Patent ID: 6482705
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, having an amorphous-silicon-germanium (&agr;-SiGe) gate electrode and a raised crystalline silicon-germanium (c-SiGe) source/drain structure, comprising:depositing an amorphous silicon-germanium (&agr;-SiGe) layer on a gate dielectric, at least one spacer, and at least one exposed portion of a substrate; polishing the &agr;-SiGe layer, thereby forming an &agr;-SiGe raised source/drain (S/D) structure and an &agr;-SiGe gate electrode; annealing the &agr;-SiGe raised S/D structure under solid-phase epitaxy in a low temperature range of approximately 500Â° C. to approximately 550Â° C., thereby recrystallizing the &agr;-SiGe raised S/D structure, and thereby forming a raised c-SiGe S/D structure; and completing fabrication of the device.