Patent ID: 6184906
Filing Date: 2001-02-06
Classification: G06F,G09G

Abstract:
A memory controller for servicing real time data comprising:at least a first input port for receiving a real time request signal in a pipeline fashion;at least a second input port for receiving a non-real time request signal in a pipe line fashion;first pipeline processor, operatively coupled to the first input port, to separately process the real time request signal in a pipeline fashion wherein the first pipeline processor is a dual stage pipeline processor with a first stage addressing unit having addressing logic with first memory row/column address determination logic and first memory page fault detection logic;second pipeline processor, operatively coupled to the second input port, to separately process the non-real time request signal in a pipeline fashion; andwherein the first and second pipeline processors include an arbitrator to selectively determine which of the real time and non-real time request signals is to be output to memory.