Patent ID: 6985917
Filing Date: 2006-01-10
Classification: G06F

Abstract:
1. A calculating unit comprising: a first calculating unit block comprising a first plurality of elementary cells including an LSB elementary cell for a least significant bit of a first operand and an MSB elementary cell for a most significant bit of the first operand, each elementary cell of the first calculating unit block comprising at least one register cell for storing a bit of the first operand or a result bit calculated by the elementary cell, the first calculating unit block comprising at least four partial calculating unit blocks; a second calculating unit block comprising a second plurality of elementary cells including an LSB elementary cell for a least significant bit of a second operand and an MSB elementary cell for a most significant bit of the second operand, each elementary cell of the second calculating unit block comprising a register cell for storing a bit of the second operand or a result bit calculated by the elementary cell, the second calculating unit block comprising at least four partial calculating unit blocks, wherein the first and second calculating unit blocks are arranged with respect to each other in space such that a spacial distance between an elementary cell of the first calculating unit block and a same significance elementary cell of the second calculating unit block is smaller than a mean distance between the elementary cell of the first calculating unit block and different significance elementary cells of the second calculating unit block, wherein a partial calculating unit block of the second calculating unit block is arranged between two partial calculating unit blocks of the first calculating unit block, and wherein a direction from a least significant elementary cell to a most significant elementary cell of the partial calculating unit block of the second calculating unit block is the same direction as a least significant elementary cell to a most significant elementary cell of a neighboring partial calculating unit block of the first calculating unit block, wherein the direction from the least significant elementary cell to a most significant elementary cell of the partial calculating unit block of the second calculating unit block is opposite to a direction from a least significant elementary cell to a most significant elementary cell of the other neighboring partial calculating unit block of the first calculating unit, and connector having a number of connecting lines equaling the number of elementary cells in a calculating unit block, wherein a connecting line connects the at least one register cell of an elementary cell having a significance of the first calculating unit block to a register cell of an elementary cell having the same significance of the second calculating unit block, wherein the connecting lines are arranged between the two partial calculating unit blocks having the same direction from the least significant elementary cell to the most significant elementary cell of the partial calculating unit blocks; and controller for loading contents of the register cells of a calculating unit block via the number of connecting lines into the register cells of the other calculating unit block.