Patent ID: 8729663
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a p-type semiconductor substrate; a field oxide film embedded in said p-type semiconductor substrate; a fuse provided on said field oxide film; a single n-type well provided directly below said fuse in said p-type semiconductor substrate, wherein said single n-type well is provided only below a lowest most surface of the field oxide film and completely within a vertical boundary defined by each end of said field oxide film; a p-type well provided in such a manner as to surround a region directly under said fuse in said p-type semiconductor substrate and having a larger impurity concentration than an impurity concentration of said p-type semiconductor substrate; a first insulating layer and a second insulating layer in this order stacked over said p-type semiconductor substrate and said field oxide film; a seal ring embedded in said first insulating layer and said second insulating layer so as to surround said fuse; and an opening provided over said single n-type well so as to expose the first insulating layer, wherein said first insulating layer covers an upper surface of said fuse, wherein said p-type well is in contact with a lower surface of said seal ring, and said single n-type well and said p-type well being free of an impurity layer therebetween.