Patent ID: 6803796
Filing Date: 2004-10-12
Classification: H04L

Abstract:
A multiple-phase switching circuit comprising:a finite state machine for generating an alternative signal according to a switching signal; a synchronizer, coupled to said finite state machine, for receiving the alternative signal and synchronously outputting the alternative signal according to a target clock signal; and a multiplexer coupled to said synchronizer, for receiving a plurality of input clock signals and outputting the target clock signal according to the alternative signal; wherein Phases of the input clock signals are different; wherein, the finite state machine generates a plurality of alternative signals, only one of the alternative signals is in a first logic level, while the others are in a second logic level; and wherein, the finite state machine changes the logic level of the alternative signal having the first logic level into the second logic level, and also changes the logic level of another alternative signal which is adjacent to that changed alternative signal into the first logic level according to the switching signal.