Patent ID: 7091623
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A multi-chip semiconductor package, comprising: a substrate having an upper surface and a lower surface opposed to the upper surface; at least a first chip mounted on the upper surface of the substrate; a non-conductive material applied over predetermined area on the first chip and the upper surface of the substrate, wherein the non-conductive material is an elastic adhesive; at least a second chip mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, the non-conductive material having a chip contact portion formed on an upper surface of the first chip and at least a substrate contact portion formed on the upper surface of the substrate, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported directly on the substrate contact portion of the non-conductive material; and an encapsulant formed on the upper surface of the substrate for encapsulating the first and second chips.