Patent ID: 6751135
Filing Date: 2004-06-15
Classification: G11C

Abstract:
In a dynamic semiconductor memory having memory cells configured in a cell field, a circuit configuration for driving the memory cells, the circuit configuration comprising:a master word line having a first part, a second part, and a third part; at least one segmented word line connected to the memory cells; a word line driver having an output connected to said segmented word line and through said segmented word line to the memory cells, said word line driver connected to and driven exclusively by said master word line, said word line driver disposed in the cell field; a first control device connected to said first part of said master word line and disposed outside of the cell field, said first control device having an output connected to said second part of said master word line; and a second control device connected to said second part of said master word line, said second control device disposed in a region of said word line driver and connected to said word line driver through said third part of said master word line, said segmented word line through said word line driver being connectible to one of a supply voltage and a ground potential in dependence on a signal on said master word line, said master word line being switchable to a high logic state for activating said word line driver.