Patent ID: 7886134
Filing Date: 2011-02-08
Classification: G06F

Abstract:
1. A digital data processor operable to execute conditional branch instructions to branch to a branch address upon satisfaction of branch condition and a block repeat instruction specifying a number of times to execute a block of instructions from a block start address to a block end address comprising: an instruction fetch unit including an instruction execution unit connected to said instruction fetch unit performing data processing operations corresponding to instructions fetched by said instruction fetch unit, that executes the instructions obtained by said instruction fetch unit, a loop control unit including said controller further operable to said loop control unit supplying a pseudo branch instruction to said instruction execution unit when said comparator indicates a match and said block repeat count register is not zero upon a first execution of a loop; and a branch prediction unit connected to said instruction fetch unit and said instruction execution unit, said branch prediction unit, said branch prediction unit storing a branch address, a target address and prediction data for conditional branch instructions executed by said instruction execution unit, said branch prediction unit supplying said target address for a current conditional branch instruction to said third input of said selector and supplying a control signal to said control input of said selector dependent upon said prediction data for a current conditional branch instruction and said branch prediction unit storing a branch address, a target address and prediction data corresponding said pseudo branch instruction.