Patent ID: 8404549
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A method of fabricating a charge trapping component of a memory, comprising the steps of: forming a layered stack on a substrate such that the layered stack comprises an polysilicon layer, a charge trapping layer positioned between the polysilicon layer and the substrate, and a tunneling layer positioned between the charge trapping layer and the substrate; patterning the layered stack to form a charge trapping element that includes a portion of the layered stack and another charge trapping element that includes another portion of the layered stack; and forming a gate oxide layer by oxidizing a portion of the substrate between the charge trapping element and the other charge trapping element such that the polysilicon layer is converted into a polyoxide, wherein forming the layered stack is done such that the polysilicon layer is abutting the charge trapping layer.