Patent ID: 7369636
Filing Date: 2008-05-06
Classification: H04L

Abstract:
1. An asynchronous communication circuit for transmitting and receiving data at arbitrary timing, comprising: a clock generator circuit which outputs a clock signal a start bit decision circuit which reads a start bit of receive data and outputs a start bit decision signal during reception of data a divider counter which divides the clock signal and counts a number of clock cycles of the clock signal in response to an input of the start bit decision signal a comparator which compares the number of counted clocks cycles and an externally generated timing instruction data and outputs a matching signal when a match occurs and a data reception shift register which receives data inputted from a data receiving terminal with the matching signal serving as a data reception shift clock, wherein the data reception shift clock is used to read data, and the receive data is read accounting for a fluctuation in a duty ratio of the receive data, the fluctuation being caused by a variation in delay on a communication path.