Patent ID: 6114900
Filing Date: 2000-09-05
Classification: G05F,H03K

Abstract:
A semiconductor integrated circuit comprising:an nMOS transistor having its source and gate connected to a low magnitude side power source terminal and to a first control terminal, respectively;a first current mirror circuit, mirror-reflecting the current flowing in said nMOS transistor;a pMOS transistor having its source and gate connected to a high magnitude side power source terminal and to a second control terminal, respectively; anda second current mirror circuit, mirror-reflecting the current flowing in said pMOS transistor;wherein high and low potentials are provided to serve as a power source to a load circuit by connection of said load circuit across an output terminal of said first current mirror circuit and an output terminal of said second current mirror circuit, respectively;wherein during a normal operation of the semiconductor integrated circuit, said pMOS transistor and said nMOS transistor each operate in a saturated ranges wherein said nMOS transistor and said pMOS transistor are integrated on a first semiconductor substrate; andwherein the first and second current mirror circuits are integrated together on a semiconductor substrate other than said first semiconductor substrate.