Patent ID: 7534674
Filing Date: 2009-05-19
Classification: H01L

Abstract:
1. A method comprising: providing a substrate; forming a P-channel transistor and an N-channel transistor using the substrate, each of the P-channel transistor and the N-channel transistor comprising a source, a drain and a gate having a first sidewall spacer; removing the first sidewall spacer of the P-channel transistor and the N-channel transistor; forming a stressor layer having a stress characteristic and overlying the P-channel transistor and the N-channel transistor; modifying the stress characteristic of the stressor layer overlying the P-channel transistor to form a modified stress characteristic differing from a portion overlying the N-channel transistor; transferring the stress characteristic of an overlying portion of the stressor layer to a channel of each of the N-channel transistor and the P-channel transistor by annealing; forming a second sidewall spacer adjacent the gate of each of the P-channel transistor and the N-channel transistor from the stressor layer; and forming silicided electrical contacts to each of the source, the drain and the gate of the P-channel transistor and the N-channel transistor while using the second sidewall spacer adjacent the gate of each of the P-channel transistor and the N-channel transistor for determining a physical boundary of the silicided electrical contacts to the source and drain of the P-channel transistor and N-channel transistor.