Patent ID: 7428567
Filing Date: 2008-09-23
Classification: G06F

Abstract:
1. An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, the arithmetic unit comprising: first arithmetic circuitry configured to process the first portions of the input operands; second arithmetic circuitry configured to process the second portions of the input operands, the second arithmetic circuitry being further configured to perform preliminary saturation detection utilizing one or more temporary sums computed therein from the second portions of the input operands; selection circuitry configured to select one or more of a plurality of outputs of the second arithmetic circuitry based on a carry output of the first arithmetic circuitry; and saturation circuitry having inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, the saturation circuitry being configured to generate a result of the arithmetic operation.