Patent ID: 8976273
Filing Date: 2015-03-10
Classification: H04N

Abstract:
1. An electronic imager having a plurality of rows and columns of pixels comprising: a pixel offset line for each column of pixels receiving a pixel offset of a selected row of a corresponding column of pixels; a pixel offset capacitor for each column of pixels connected to a corresponding pixel offset line; a pixel offset bus; a pixel offset transistor for each column of pixels having a source-drain path connected between a corresponding pixel offset line and said pixel offset bus and a gate; a pixel signal line for each column of pixels receiving a pixel signal of a selected row of a corresponding column of pixels; a pixel signal capacitor for each column of pixels connected to a corresponding pixel signal line; a pixel signal bus; a pixel signal transistor for each column of pixels having a source-drain path connected between a corresponding pixel signal line and said pixel signal bus and a gate; an output buffer having an input and an output; a pixel offset output transistor having a source-drain path connected between said pixel offset bus and said input of said output buffer; and a pixel signal output transistor having a source-drain path connected between said pixel signal bus and said input of said output buffer.