Patent ID: 6150857
Filing Date: 2000-11-21
Classification: H03L

Abstract:
A phase locked loop comprising:a controlled oscillator that is responsive to a control signal to generate an output signal;a divider that divides the output signal to produce a divided output signal;a phase detector that is responsive to a reference frequency input signal and to the divided output signal to produce an error signal;a loop filter; andan analog multiplier network that equalizes the loop bandwidth of the phase locked loop as a function of frequency, wherein the loop filter and the analog multiplier network are serially connected between the phase detector and the controlled oscillator, and wherein the analog multiplier network comprises:an analog multiplier network input node;an analog multiplier network output node;first, second and third multipliers, the first multiplier including a first multiplier output terminal; andfirst, second, third, fourth and fifth resistors;wherein the first resistor is connected between a supply voltage and the analog multiplier network output node;wherein the second resistor is connected between the analog multiplier network input node and the analog multiplier network output node;wherein the first multiplier and the third resistor are serially connected between the analog multiplier network input node and the analog multiplier network output node;wherein the second multiplier and the fourth resistor are serially connected between the analog multiplier network input node and the analog multiplier network output node;wherein the third multiplier and the fifth resistor are serially connected between the first multiplier output terminal and the analog multiplier network output node; andwherein the first multiplier output terminal also is connected to the second multiplier.