Patent ID: 6373308
Filing Date: 2002-04-16
Classification: H03K,H03L

Abstract:
A delay-lock loop (DLL) circuit coupled to a clock network, the DLL circuit comprising:an input clock terminal providing an input clock signal; a feedback clock terminal providing a feedback clock signal from the clock network; an output clock terminal providing an output clock signal to the clock network; a delay line driven by the feedback clock signal in a first mode and by the input clock signal in a second mode; a decoder circuit driven by the delay line; a clock multiplexer circuit driven by the delay line and controlled by the decoder circuit, the clock multiplexer circuit providing the output clock signal to the output clock terminal; and a control circuit, wherein: the control circuit controls a mode of the DLL circuit, in the first mode the delay line provides to the decoder circuit a plurality of first intermediate clock signals delayed from the feedback clock signal by incremental unit delays, and in the second mode the delay line provides to the clock multiplexer circuit a plurality of second intermediate clock signals delayed from the input clock signal by the incremental unit delays.