Patent ID: 9083280
Filing Date: 2015-07-14
Classification: H03D,H03L

Abstract:
1. A circuit comprising: a phase detector input circuit to receive first and second periodic signals and to generate phase detector input signals, the phase detector input signals comprising the first periodic signal and a delayed second periodic signal when a clock signal is in a first logic state, and the phase detector input signals comprising the second periodic signal and a delayed first periodic signal when the clock signal is in a second logic state; a phase detector to receive the phase detector input signals and to generate a phase comparison signal indicative of a phase difference between the first and second periodic signals, wherein the phase comparison signal has a non-zero value in response to the phase detector input signals being aligned in phase; and an output circuit to receive the phase comparison signal and to generate based on the phase comparison signal, an output signal having a zero value when the first and the second periodic signals are aligned in phase.