Patent ID: 6576550
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A method for forming over a semiconductive wafer, which contains therein and/or thereon devices having conductive contact regions, an interconnection pattern that uses copper in at least some vias and some trenches through insulating layers overlying a top surface of the semiconductor wafer, the method comprising the steps of:forming a first insulating layer over the device; forming vias from a top surface of the first insulating layer therethrough with the vias being in communication with the contact regions of the device; filling the vias with a conductor; forming a second insulating layer over the first insulating layer; forming vias through the second insulating layer which are in communication with the conductor filled vias in the first insulating layer; filling the vias through the second insulating layer with copper; forming a third insulating layer over a top surface of the second insulating layer; forming a fourth insulating layer over a top surface of the third insulating layer, the fourth insulating layer having a different etch characteristic than the third insulating layer; patterning and etching the fourth insulating layer to form vias therethrough which are separated from the copper-filled vias through the second insulating layer by the third insulating layer but are aligned with the vias through the second insulating layer; forming an anti-reflective layer over a top surface of the fourth insulating layer and filling the vias therethrough with anti-reflective material; patterning the anti-relective layer and material to define trenches in the fourth insulating layer; removing the layer of anti-reflective layer and a portion of the fourth insulating layer to form trenches in the fourth insulating layer which are in communication with top portions of the vias through the fourth insulating layer, and removing the anti-reflective material in the vias through the fourth insulating layer and a portion of the third insulating layer between the vias of the second and fourth insulating layers; filling the trenches and vias in the fourth insulating layer and portions of the third insulating layer which were removed with copper.