Patent ID: 6225178
Filing Date: 2001-05-01
Classification: H01L

Abstract:
A method for fabricating hardened isolation for devices in Metal oxide semiconductor circuitry, comprising:depositing a pad oxide layer on a silicon substrate;depositing a polysilicon layer on the pad oxide layer;depositing a silicon nitride layer on the polysilicon layer;cutting an opening in the silicon nitride layer and polysilicon layer to expose a portion of the pad oxide layer;implanting a dopant into the opening at a high tilt angle in a rotating fashion to project the dopant into the silicon layer beneath polysilicon edges of the opening bordering the pad oxide layer;annealing the opening in nitrogen at about 850 or more degrees Centigrade for about 20 or more minutes;oxidizing the exposed portion of the pad oxide layer under high pressure thereby causing the silicon beneath the exposed pad oxide layer to grow into a field oxide having expansion encroaching like a bird's beak betweenthe silicon substrate and the polysilicon and silicon nitride layers at the polysilicon edges;removing the silicon nitride layers;removing the polysilicon layer;removing the remaining pad oxide layer; andreducing size and lateral extension of the field oxide.