Patent ID: 6025740
Filing Date: 2000-02-15
Classification: H03K

Abstract:
An integrated circuit formed as a semi-custom-made LSI device having a conductive pattern, the integrated circuit comprising:a plurality of logic circuit regions, each region havinga plurality of logic circuits,an input circuit for receiving a clock signal and providing the received clock signal to each of said plurality of logic circuits, andinterconnections formed by the conductive pattern, the interconnections electrically connecting said plurality of logic circuits and said input circuit, so that a clock skew of the clock signal is minimized among said plurality of logic circuits;a clock source for feeding said clock signal to said regions; anda plurality of adjusting circuits, each adjusting circuit disposed between said clock source and a respective one of said regions, each adjusting circuit delaying transmission of the clock signal to the respective region, said each adjusting circuit including a predetermined number of delay elements selectively connected between said clock source and the respective one of said regions with the conductive pattern so as to adjust the amount of the delay of the clock signal.