Patent ID: 7821821
Filing Date: 2010-10-26
Classification: B82Y,G11C,H01L

Abstract:
1. A memory device comprising: a substrate having a flat face; a bit line formed in a first direction on the substrate; a lower word line insulated from the bit line and formed in a second direction intersecting the first direction; a pad electrode electrically isolated from a sidewall of the lower word line and connected to the bit line; a cantilever electrode expending in the first direction, suspended over the lower word line with a lower void therebetween, and connected to the pad electrode, the cantilever electrode curved in a third direction that is vertical with respect to the first and second direction by an electrical field induced by a first charge applied to the lower word line; a trap site expending in the second direction and suspended over the cantilever electrode with an upper void therebetween; and an upper word line to which a charge to curve the cantilever electrode in a direction of the trap site is applied, the upper word line positioned on the trap site.