Patent ID: 9213344
Filing Date: 2015-12-15
Classification: G05F,H02M

Abstract:
1. A ripple suppressor circuit comprising: a first input configured to receive a first signal that is a pulse width modulated signal having a duty cycle that is representative of a requested output voltage value; a second input configured to receive a second signal that is a filtered value of the first signal; a first storage element; a second storage element; a first switch configured to store a first value of the second signal on the first storage element responsively to a first transition of the first signal; a second switch configured to store a second value of the second signal on she second storage element responsively to a second transition of the first signal; and an averaging circuit configured to receive the first value of the second signal from the first storage element and to receive the second value of the second signal from the second storage element and form a reference signal having a value that is an average value of the first value and the second value.