Patent ID: 6351724
Filing Date: 2002-02-26
Classification: G06F

Abstract:
A microprocessor, comprising:a bus monitor configured to provide one or more indications in response to one or more occurrences of one or more events within the microprocessor; a memory configured to store data about the occurrences of the one or more events within the microprocessor; and a control unit coupled to the bus monitor and the memory, wherein the control unit is configured to detect the one or more indications provided by the bus monitor and, in response, to control the memory to store data indicating a number of the occurrences of each of the one or more events during each of a plurality of consecutive time periods; wherein the memory comprises a different storage location per event per time period, so that each storage location is configured to store a number of occurrences of a respective one of the one or more events during a respective one of the plurality of consecutive time periods.