Patent ID: 7779412
Filing Date: 2010-08-17
Classification: G06F,Y02D

Abstract:
1. A task scheduling method for scheduling tasks on a system chip that includes a plurality of processing elements and a plurality of non-processing elements on which the tasks are to be executed, said task scheduling method comprising the steps of: a) performing initial scheduling of the tasks on the processing elements under a condition that the non-processing elements operate at full power states; b) establishing an analytical model for the processing and non-processing elements, and estimating time parameters of the tasks on the processing and non-processing elements from the analytical model, wherein the time parameters correspond to the processing times of the tasks on assigned ones of the processing and non-processing elements; c) determining lowest possible power dissipation and timing sequence of the tasks on the non-processing elements according to the analytical model established in step b); d) generating task scheduling results for the processing elements with reference to values obtained in step c); and e) repeating steps c) and d) until the task scheduling results converge to an invariable scheduling result.