Patent ID: 6388296
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A CMOS strap interconnection for interconnecting CMOS transistors on a substrate, comprising:a CMOS transistor on a substrate, including a gate electrode having sidewalls, and including source/drain regions; field oxide regions surrounding said source/drain regions; a semiconductor film overlying the source/drain regions and the surrounding field oxide regions, said semiconductor film extending to the sidewalls of the gate electrode; a silicide film formed overlying selected areas of said semiconductor film and adjoining areas of field oxide; said silicide film not extending to said gate electrode sidewalls such that, overlying the source/drain regions, the semiconductor film extends to the gate electrode sidewalls and the silicide film does not extend to the gate electrode sidewalls; said silicide film providing a strap interconnection that permits electrical communication from a selected source/drain region of said CMOS transistor over the surrounding field oxide region adjacent said selected source/drain region to a source/drain region of another CMOS transistor on the substrate, whereby a strapped interconnection of silicide is provided between CMOS transistors; and in which the interconnection extends between a first and a second CMOS transistor, each transistor having first and second electrodes in contact, respectively, with a selected source/drain region of each transistor, and in which said silicide film interconnects at least a first electrode of the second transistor and at least a second electrode of the first transistor.