Patent ID: 6642586
Filing Date: 2003-11-04
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a gate insulating film formed on a partial area of a surface of said semiconductor substrate; a gate electrode formed on said gate insulating film; a lamination film formed on a side wall of said gate electrode and on the surface of said semiconductor substrate on both sides of said gate electrode, conformable to the side walls and the surface, said lamination film having a structure of at least three layers, each of the three layers being made of insulating material, and a middle layer being made of material easier to trap carriers than other two layers; a side wall spacer made of conductive material and facing the side wall of said gate electrode and the surface of said semiconductor substrate via said lamination film; a conductive connection member electrically connecting said side wall spacer and said gate electrode; and impurity doped regions formed in a surface layer of said semiconductor substrate in areas sandwiching said gate electrode along a first direction parallel to the surface of said semiconductor substrate, edges of said impurity doped regions being disposed under said lamination film to some depth and not reaching boundaries of said gate electrode.