Patent ID: 6198265
Filing Date: 2001-03-06
Classification: G05F

Abstract:
A fixed frequency switching regulator device interconnected for driving an output switch for enabling an input voltage level at an output terminal, the device comprising: a current source, a comparator, a discharge switch, a timing capacitor and a hysteresis circuit interconnected for; charging the timing capacitor from the current source until a timing capacitor voltage level exceeds the input voltage level, so as to enable the comparator to turn on the discharge switch for draining the timing capacitor so as to drive the comparator into a low state thereby enabling the hysteresis circuit to develop hysteresis; the device further including a reset dominant pulse-width modulated latching device having a set and a reset input terminals, the latching device driving an output terminal to a low state when both the set and reset input terminals are driven to a low state; the latching device being switched by the comparator so that at the start of a timing cycle, the set input terminal of the latching device assumes a low state when the comparator moves to a low state momentarily so that the output terminal of the latching device moves to a high state thereby turning on the output switch and enabling feedback from the timing capacitor to an error comparator so that the output switch remains in an on state until a portion of the output voltage, determined by a voltage divider, exceeds a reference voltage at the error comparator so that the latching device turns the output switch off and disables feedback from the timing capacitor, the voltage divider being coupled to a feedback switch device for enabling a feedback signal from the timing capacitor at the error comparator for providing slope compensation so as to stabilize operation of the device.