Patent ID: 8266411
Filing Date: 2012-09-11
Classification: G06F

Abstract:
1. A method, comprising: providing a processor; and causing the processor to execute an instruction that operates on an operand in at least one register, wherein the instruction includes at least one characteristic bit that conditionally influences the execution of the instruction by the processor in that the processor changes a number of registers in an explicit or implicit freelist that are operated on in executing the instruction with respect to a number of registers that would be operated on in executing the instruction if the at least one characteristic bit were not present, wherein the at least one characteristic bit indicates a result of an operation on the operand in the at least one register operated on by the processor when executing the instruction, wherein the indicated result of the operation on the operand in the at least one register comprises a not of architectural importance result of an intermediate type; wherein in response to the characteristic bit being set and a signal indicating that one of a direct bypass or forwarding is available, at least one write to a register by the processor is avoided; and wherein in response to the characteristic bit being set and the signal indicating that direct bypass and forwarding are not available, the result of the operation is written to the register.