Patent ID: 6043101
Filing Date: 2000-03-28
Classification: G01R

Abstract:
A method for reducing rejects during in-situ testing of semiconductor circuit chips on a substrate wafer prior to separation of said chips comprising the steps of:a) positioning a multiprobe in contact with leads of a first semiconductor circuit chip on a wafer;b) performing a predetermined series of tests once on the first semiconductor circuit chip;c) determining whether said first semiconductor circuit chip failed one of the tests in the series of tests; andd) performing the predetermined series of tests a second time on the first chip if said first circuit chip failed one of said tests;e) flagging the chip as a reject only if the chip fails one of the tests performed for the second time; andf) repositioning the multiprobe to another chip on the wafer and repeating steps b) through e) until all chips on the wafer have been tested.