Patent ID: 7615865
Filing Date: 2009-11-10
Classification: H01L,H05K,Y02P

Abstract:
1. A semiconductor device, comprising: a substrate containing a conductive layer; a solder resist film laminate layer disposed over the substrate and conductive layer; an opening formed in the solder resist film laminate layer to expose the conductive layer, the solder resist film laminate layer being cured after the opening is formed; an under bump metallization (UBM) layer formed over the conductive layer; a plurality of first solder bumps formed over the UBM layer to promote reflow of the first solder bumps at a eutectic temperature; a plurality of standoff solder bumps formed directly on the solder resist film laminate layer around a perimeter of the substrate, the solder resist film laminate layer preventing reflow of the standoff solder bumps at the eutectic temperature; a semiconductor die; and a plurality of second solder bumps disposed between the semiconductor die and the first solder bumps of the substrate, the second solder bumps being ref lowed to electrically connect the semiconductor die to the first solder bumps of the substrate, wherein after reflow of the second solder bumps the standoff solder bumps have a height 70-90% of a height of the second solder bumps prior to reflow to maintain a predetermined separation between the semiconductor die and substrate.