Patent ID: 8745363
Filing Date: 2014-06-03
Classification: G06F

Abstract:
1. A bootable volatile memory device comprising: a volatile memory area configured to be written to and read from by a host processor; a boot code area configured to store bootstrap code before a boot procedure is performed by the host processor; a first chip select terminal configured to receive a signal used as a chip select signal where the host processor performs the boot procedure by reading the bootstrap code from the boot code area; and a second chip select terminal configured to receive a signal used as a chip select signal where the host processor writes and reads data to and from the volatile memory area; wherein the bootstrap code is copied from a nonvolatile memory to the boot code area by a control unit before the boot procedure starts; and wherein the control unit causes a power-on reset to be performed on the host processor after the bootstrap code is copied from the nonvolatile memory to the boot code area.