Patent ID: 6349097
Filing Date: 2002-02-19
Classification: H04L,H04Q

Abstract:
A data unit, for receiving data packets and delivering them to packet switching circuitry, the received data packets including unicast packets belonging to just one of predetermined first and second categories of the data packets and also including multicast packets belonging to both said first and second categories, said data unit comprising:a packet storage section to cause the received data packets to be stored in a memory; a packet registration section having first and second registers to store entries, the packet registration section operating when each unicast data packet belonging to said first category is received, to make an entry corresponding to the packet concerned in a storage location of the first register and also operating when each unicast data packet belonging to said second category is received, to make an entry corresponding to the packet concerned in a storage location of the second register; a multicast handling section operating when each said multicast packet belonging to both said first and second categories is received, to cause the packet registration section to make respective entries corresponding to the multicast packet concerned directly in respective storage locations of both the first and second registers; and a packet output section operating for each of said first and second registers, to read the entries in the register concerned in the order in which they were made and, for each entry read, to read out the corresponding data packet from the memory and output it to said packet switching circuitry; wherein, within each register, each said entry is maintained in the storage location in which it was originally stored by said packet registration section when the corresponding packet was received until that packet is read out and output by said packet output section.