Patent ID: 6556504
Filing Date: 2003-04-29
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device including a memory and a memory controller, in which the memory has a memory cell array having a matrix of rows and columns; and a plurality of latch groups for storing data to be written/read in/from the memory cell array, the nonvolatile semiconductor memory device further comprising:an address buffer circuit for receiving and storing external addresses from a first input/output pins; a column address register for receiving an address of the external addresses stored in the address buffer circuit as a column address, and sequentially increasing the column address; a selection circuit for selecting a latch group of the plurality of latch groups in response to the column address sequentially outputted from the column address register; a data input/output circuit for transferring data inputted through a second input/output pins to the selected latch group by being synchronized with a data input signal provided from the memory controller, and transferring the stored data in the selected latch group to the second input/output pins by being synchronized with a data output signal provided from the memory controller; and a controller for controlling the address buffer circuit and the column address register to store the column address of the external addresses in the column address register when the external addresses are applied to the first input/output pins, while the stored data in the selected latch group is transferred to the second input/output pins or the data inputted through the second input/output pins is transferred to the selected latch group.