Patent ID: 9059004
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A Chip Scale Package (CSP) structure, comprising: a semiconductor substrate having a plurality of contact bonding pads formed thereon, the contact bonding pads electrically connected with semiconductor devices; and a plurality of bumps respectively attached to each of the contact bonding pads, wherein the semiconductor substrate is divided into several regions comprising a first region, a second region, and a third region according to different distances from a central point, and wherein the central point makes the first region, and the second region is between the first region and the third region, and wherein a contact bonding pad and a bump in the first region are positioned directly on top of the central point and are the smallest, while the contact bonding pads and a bumps in the third region which is farthest to the central point are the largest, and sizes of the contact bonding pads and bumps in the several regions are determined based on a likeliness of peeling-off and bridging of the bumps such that the bumps in the several regions are less likely to peel-off and to bridge with neighboring bumps.