Patent ID: 8698556
Filing Date: 2014-04-15
Classification: H03F

Abstract:
1. An auto-zero offset buffer amplifier, comprising: a main amplifier having differential inputs, an auxiliary nulling input and an output; a nulling amplifier having differential inputs, an auxiliary nulling input and an output; a first field effect transistor (FET) switch coupled to the differential inputs of the main and nulling amplifiers; a second FET switch coupled to the output of the nulling amplifier and the auxiliary nulling inputs of the main and nulling amplifiers; a first storage capacitor coupled to the second FET switch and the auxiliary nulling input of the nulling amplifier; a second storage capacitor coupled to the second FET switch and the auxiliary nulling input of the main amplifier; an oscillator having a clock output; a level shifting circuit having an input coupled to the clock output of the oscillator and an output coupled to and controlling the first and second switches; and a voltage regulator coupled to the level shifting circuit; the level shifting circuit provides a control signal to the first and second FET switches, wherein the control signal has a voltage amplitude that is slightly greater than a gate-source turn-on voltage of the first and second FET switches.