Patent ID: 8110468
Filing Date: 2012-02-07
Classification: H01L

Abstract:
1. A method for forming a DMOS-transistor comprising: providing a substrate; forming a first well region and a second well region by CMOS compatible processes in said substrate, said first and second well regions having complementary types of doping; forming a highly doped region with the same type of doping as the second well region, said highly doped region being at least adjacent to said second well region, wherein a lateral extension of the highly doped region is less than a lateral extension of the first well region for increasing an electric strength of a highly doped source region to be formed; and thereafter forming an isolation structure; forming a gate electrode and a gate insulation layer for forming a transistor channel on a surface of said first well region; forming a highly doped source region located in said first well region and complementarily doped thereto and forming a highly doped drain doping region located in said second well region; and forming a highly doped bulk connection region located in said first well region and having the same type of doping as said first well region.