Patent ID: 6512858
Filing Date: 2003-01-28
Classification: H04N

Abstract:
A scanning circuit integrated onto a semiconductor substrate with an active pixel sensor array, comprising:a row-address generator configured to generate row addresses starting from a row-start address and incrementing by a row-increment value, wherein said row-start address and said row-increment value are stored within said row-address generator; a column-address generator configured to generate column addresses starting from a column-start address and incrementing by a column-increment value, wherein said column-start address and said column-increment value are stored within said column-address generator; row-address generator data loading circuitry coupled to said row-address generator and configured to load said row-start address and said row-increment value into said row-address generator; column-address generator data loading circuitry coupled to said column-address generator and configured to load said column-start address and said column-increment value into said column-address generator; a row decoder coupled to said row-address generator; a column selector coupled to said column-address generator; a plurality of row select lines coupled to said row decoder, each one of said row select lines associated with a different row in said active pixel sensor array; and a plurality of column output lines coupled to said column selector, each one of said column output lines associated with a different column in said active pixel sensor array.