Patent ID: 6782515
Filing Date: 2004-08-24
Classification: G01R

Abstract:
A method for analyzing an integrated circuit (IC) under test and for identifying and inserting test points in order to improve the testability of the IC, the method comprising:a) determining a measure of testability for the IC; b) selecting test point candidates to be evaluated for insertion in said IC and arranging said test point candidates into a first plurality of pairs of sets; c) evaluating said first plurality of pairs of sets and forming a second plurality of pairs of sets from said first plurality of pairs of sets, said evaluation being based on the respective testability improvement achieved by each plurality of said pairs of sets, and recombining said first and second plurality of pairs of sets based on results from said evaluation; d) repeating step c) until said first and second pairs of sets converge to form a best set, said best set providing the test points to be inserted into the IC; and e) repeating steps a) through d) until all the test points to be inserted have been incorporated into the IC, wherein in step a) the measure of testability for the IC is determined by a combination of fault simulation and fault detection probability.