Patent ID: 6809969
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:first, second and third bit lines arranged to extend in a direction of a column; a plurality of memory cells configuring first and second memory cell columns adjacent to each other, each memory cell being configured of a transistor having an electric charge trapping film; a plurality of word lines provided to correspond respectively to rows of said plurality of memory cells, said first memory cell column being connected between said first bit line and said second bit line, said second memory cell column being connected between said second bit line and said third bit line; an erase control portion controlling an erase operation effected for said plurality of memory cells; and a weak write control portion controlling a weak write operation effected for said plurality of memory cells, said erase control portion subjecting all of said plurality of memory cells simultaneously to an erase operation allowing a memory cell to transition to an overerased condition, said weak write control portion subjecting all of said plurality of memory cells simultaneously to a weak write operation using a channel hot electron.