Patent ID: 8930752
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A method for performing operations in a multiprocessing system comprising a plurality of processor cores, said method comprising: dynamically configuring a selective pairing facility to communicate with at least two processor cores for performing one of: independent parallel operation or highly-reliable fault tolerant operations; scheduling, by a scheduler device operatively connected with said selective pairing facility, software-resilient threads to said at least two processor cores when the selective pairing facility is configured for said independent operation of said at least two cores, said scheduler device generating first configuration signals for receipt at said selective pairing facility to configure a first operating mode wherein processor cores connected to said selective pairing facility execute independent threads; scheduling, by said scheduler device, hardware-resilient threads to said at least two processor cores connected to said selective pairing facility when the selective pairing facility is configured for said highly-reliable fault tolerant operations, said selective pairing facility providing simultaneous pairwise execution of a thread at paired first and second processor cores, said scheduler device generating second configuration signals for receipt at said selective pairing facility to configure a second operating mode wherein said first and second processor cores connected to said selective pairing facility are configured to operate on the same instruction and data for a single thread, and the selective pairing facility is configured to perform error checking by checking execution results generated by said paired first and a second processor cores in order to detect incorrect execution sequences; and reconfiguring said selective pairing facility operating in said first operating mode to operate in said second mode by migrating a software-resilient thread from a first processor core running at a first selective pairing facility configured in said first operating mode to a second processor core corresponding to a second selective pairing facility configured to operate in said first operating mode thereby rendering a pair of processor cores available to receive a thread for said highly reliable fault tolerant operations at said first selective pairing facility.