Patent ID: 6287914
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device, said method comprising the steps of:(a) forming on the main surface of a semiconductor substrate a MISFET for selecting a memory cell which is provided with a gate electrode integrally formed with a word line extending in a first direction and then forming a first insulating film over the MISFET for selecting a memory cell;(b) etching the first insulating film to form a second contact hole extending to the other of a pair of source and drain of the MISFET for selecting a memory cell and then forming a plug in the second contact hole;(c) forming over the first insulating film a third insulating film which is different in an etching rate from the first insulating film and then forming over the third insulating film a fourth insulating film which is different in an etching rate from the third insulating film;(d) etching the fourth insulating film by using the third insulating film as an etching stopper to form a wiring trench extending in a second direction intersecting the first direction;(e) forming a second insulating film having a thickness smaller than half the width of the wiring trench over the fourth insulating film including the inside of the wiring trench;(f) sequentially etching the second insulating film inside the wiring trench, the third insulating film below it and the first insulating film to form a first contact hole extending to one of the pair of source and drain of the MISFET for selecting a memory cell; and(g) depositing a first conductive film to be the material of a bit line over the second insulating film including the inside of the first contact hole and then polishing the first conductive film, and the second insulating film over the fourth insulating film by a chemical mechanical polishing method to form a bit line in each of the wiring trench and the first contact hole.