Patent ID: 6188934
Filing Date: 2001-02-13
Classification: G06F

Abstract:
A register correspondence method in a logic equivalence verifying system for first and second sequential circuit information, comprising the steps of:collecting input cone information for each register of said first and second sequential circuit information, said input cone information being represented by external input terminals, determined registers, a number of undetermined registers and self-feedback information showing presence or absence of a self-feedback loop;selecting a first register having unique input cone information from said first sequential circuit information;selecting a second register having unique input cone information from said second sequential circuit information;said unique cone information for said first and second registers defined as input cone information which is not identical to the input cone information of each of the other registers in said first and second sequential circuit information respectively;comparing the input cone information of said first register with that of said second register,thus establishing a register correspondence between said first and second registers, when the input cone information of said first register is equal to that of said second register,each of said determined registers being one where said register correspondence has been established,each of said undetermined registers being one where said register correspondence has not been established.