Patent ID: 6747896
Filing Date: 2004-06-08
Classification: G11C,H01L

Abstract:
A device containing an array of memory transistors, wherein each memory transistor comprises:a first source/drain region, a second source/drain region, and a channel in a substrate, the channel regions extending from the first source/drain region to the second source/drain region; a first floating gate overlying and insulated from a first portion of the channel adjacent the first source/drain region; a second floating gate overlying and insulated from a second portion of the channel adjacent the second source/drain region, wherein a gap between the second floating gate and the first floating gate overlies a central portion of the channel between the first and second portions of the channel; and a control gate overlying and insulated from the first and second floating gates, the control gate extending into the gap between the first and second floating gates and modulating the central portion of the channel.