Patent ID: 6928494
Filing Date: 2005-08-09
Classification: G11C

Abstract:
1. An apparatus, comprising: a buffer having a buffer input and a buffer output; a scheduler coupled to the buffer input to place a first command and a second command into the buffer; and control logic coupled to the buffer output to control execution of the first and second commands; wherein the second command includes timing data defining a timing relationship between the execution of the first command and the execution of the second command; wherein the buffer includes a first FIFO having a first input and a first output and further includes a second FIFO having a second input and a second output; the scheduler is coupled to the first input to place the first command into the first FIFO and coupled to the second input to place the second command into the second FIFO; and the control logic includes first logic coupled to the first output to control execution of the first command and includes second logic coupled to the first logic and coupled to the second output to control execution of the second command.