Patent ID: 6528386
Filing Date: 2003-03-04
Classification: H01L

Abstract:
A method of forming an FeRAM capacitor over one or more transistors associated with a semiconductor substrate, comprising:forming a dielectric layer over the one or more transistors; forming a contact via and an alignment mark via in the dielectric layer, wherein the contact via extends down to a portion of one of the one or more transistors; forming a tungsten layer over the dielectric layer, wherein the tungsten layer fills the contact via and is substantially conformal with respect to the alignment mark via, wherein a sidewall surface of a portion of the tungsten layer within the alignment mark via has a roughness associated therewith; reducing the sidewall surface roughness of the tungsten layer within the alignment mark via; patterning the tungsten layer, thereby electrically isolating the contact via and the alignment mark via, respectively; forming capacitor stack layers over the dielectric layer, the contact via and the alignment mark via, respectively, wherein the capacitor stack layers are substantially conformal with respect to the alignment mark via thereunder, thereby resulting in a topology variation in a top portion of the capacitor stack layers associated with the alignment mark via; using the topology difference in the capacitor stack layers as an alignment mark to position a patterned hard mask over the capacitor stack layers; and patterning the capacitor stack layers using the patterned hard mask, thereby defining a capacitor stack structure.