Patent ID: 7336549
Filing Date: 2008-02-26
Classification: G11C

Abstract:
1. A redundancy circuit of a semiconductor memory device, comprising: a plurality of address storage and comparison units, each one of the address storage and comparison units being configured to store an address of the semiconductor memory device and to output a match signal if a first internal address matches the stored address; wherein each address storage and comparison unit comprises a master cell having non-volatile ferroelectric storage cells for storing bits of enabling or disabling information for enabling or disabling an output of the corresponding address storage and comparison unit, wherein each address storage and comparison unit further comprises a plurality of address bit storage and comparison cells having non-volatile ferroelectric storage cells for storing bits of a failed memory address of the semiconductor memory device and configured to compare each of the stored bit with the first internal address and to output the match signal as the comparison result, and wherein the match signal and the output of the master cell are fed to a logic unit to enable the output of the address storage and comparison unit.