Patent ID: 7892923
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate able to withstand a breakdown voltage BV higher than 600 V, and having a wide band gap superficial semiconductor layer formed on the substrate, the method comprising the steps of: forming a screening structure on a surface of the superficial semiconductor layer that leaves a plurality of areas of said superficial semiconductor layer exposed, carrying out a plurality of ion implantation steps of the first type of dopant in said superficial semiconductor substrate, through said screening structure, to form a plurality of deep implanted regions that terminate at a distance greater than 2.0 μm and no greater than 2.5 μm from the surface of the superficial semiconductor layer; carrying out at least a second ion implantation of the first type of dopant in said superficial semiconductor layer to form at least one implanted body region of said MOS transistor aligned with said deep implanted regions, carrying out at least one ion implantation of a second type of dopant in said superficial semiconductor layer to form at least an implanted source region of said MOS transistor inside said at least an implanted body region, and said method comprising an activation thermal process at temperatures lower than 1600° C. of the first type and second type of dopant suitable to complete said formation of said at least one body region, of said at least one source region, and of said deep implanted regions.