Patent ID: 6222895
Filing Date: 2001-04-24
Classification: H03D,H03L,H04L

Abstract:
A phase-locked loop (PLL) circuit for generating an oscillator output signal having a clock cycle, comprising:a sampled phase detector having a reference input, a feedback input and an output, the reference input being the input of said PLL, wherein an error signal is generated at the output of said sampled phase detector corresponding to the difference in phase of the signals at said first and second inputs, wherein said error signal consists of current pulses applied only for a portion of said clock cycle;a loop filter having an input and an output, the input being connected to the error signal generated by the sampled phase detector; anda governable oscillator having a control terminal and an output, the control terminal being connected to the filtered error signal and the oscillator output being the output of the PLL and connected to said feedback input of said sampled phase detector, said oscillator output tracking the phase of the reference signal.