Patent ID: 7387933
Filing Date: 2008-06-17
Classification: H01L

Abstract:
1. A method of fabricating an EEPROM device, comprising: forming a first insulating film on a semiconductor substrate on which an active region and an inactive region are defined; forming a dopant region with a first doping concentration on the semiconductor substrate on which a floating junction region is to be formed; forming a thin tunnel insulating film on the dopant region with the first doping concentration; forming a select transistor gate and a memory transistor gate on the first insulating film, the select transistor gate separated from the memory transistor gate; forming a floating junction region by forming a first high voltage dopant region with a second doping concentration, the second doping concentration being lower concentration than the first doping concentration and being adjacent to the dopant region with the first doping concentration, and forming a second high voltage dopant region with a second doping concentration for forming a bit line junction region on a side of the select transistor separated from the first high voltage dopant region; forming the bit line junction region by forming a doping region with a third doping concentration on the second high voltage dopant region with the second doping concentration; and forming a common source region including a dopant region having only the third doping concentration, without the second doping concentration, and being adjacent to the memory transistor and separated from the dopant region with the first doping concentration, wherein the third doping concentration is higher than the second doping concentration.