Patent ID: 8084801
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of active regions of a substrate, each of the active regions having a first area at both end portions and a second area at a central portion; a bit-line contact pad of which a first portion is positioned on the second area of the plurality of active regions, and a second portion is positioned on a third area of the substrate that does not overlap with the plurality of active regions; and a bit line electrically connected with the bit-line contact pad at the third area of the substrate, so that the bit line does not overlap with the plurality of active regions, wherein the plurality of active regions includes an elliptical shape having a major axis and a minor axis and the plurality of active regions being repeatedly positioned in a direction of the major axis to thereby form an active row, and being repeatedly positioned in a direction of the minor axis in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row to thereby form an active column, and wherein the bit-line contact pad has an elliptical shape in such a structure that a major axis of the bit-line contact pad is inclined with respect to the minor axis of the plurality of active regions.