Patent ID: 6594812
Filing Date: 2003-07-15
Classification: G11C,H01L,H03K

Abstract:
A method for forming a programmable logic array from a plurality of read only memory cells, said method comprising the steps of:initially establishing a first metal layer comprising a plurality of first metal lines and a second metal layer comprising a plurality of second metal lines; thereafter interconnecting said first metal layer with said second metal layer to thereby form a plurality of read only memory cells therebetween, wherein at least one read only memory cell of said plurality of read only memory cells is formed through the interconnection of said first metal layer and said second metal layer; thereafter forming a programmable logic array from said plurality of read only memory cells; and thereafter programming said at least one read only memory cell of said plurality of read only memory cells of said programmable logic array utilizing contact via programming, thereby resulting in a shortened turn-around-time, reduced read only memory cell size, and a reduction in the necessity of requiring additional masks for read only memory logical processes associated with said programmable logic array.