Patent ID: 6323510
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A semiconductor memory device having memory cells formed on a semiconductor substrate;each of said memory cells including a select transistor formed on said substrate and a storage capacitor for electric-charge storing formed over said substrate through a first interlayer insulating layer;each of said storage capacitors having a lower electrode, an upper electrode, and a dielectric sandwiched by said lower and upper electrodes;said semiconductor memory device comprising:(a) said lower electrodes being formed by a patterned, common electrically-conductive layer formed on said first interlayer insulating layer;(b) said common electrically-conductive layer having a first plurality of windows arranged regularly in rows and columns of a matrix array;(c) said dielectric being formed by a patterned, common ferroelectric layer formed on said common electrically-conductive layer;said common ferroelectric layer being entirely overlapped with said common electrically-conductive layer;said common ferroelectric layer having a second plurality of windows overlapped with said first plurality of windows of said common electrically-conductive layer;(d) all of said upper electrodes being regularly arranged on said common ferroelectric layer;said upper electrodes being located at positions obliquely shifted by an angle of 45.degree. with respect to the corresponding windows in said rows and columns of said matrix array in which said first plurality of windows of said common electrically-conductive layer and said second plurality of windows of said common ferroelectric layer are aligned; and(e) wiring lines formed over said upper electrodes through a second interlayer insulating layer covering said storage capacitors;all of said wiring lines being arranged in a common layer at a 45.degree. angle with respect to said matrix array and substantially in the same plane as said first and second windows and being electrically connected to said upper electrodes through a first plurality of contact holes penetrating said second interlayer insulating layer;said wiring lines being electrically connected to said select transistors through said second plurality of windows of said common ferroelectric layer, said first plurality of windows of said common electrically-conductive layer, and a second plurality of contact holes penetrating said second and first interlayer insulating layers.