Patent ID: 6199154
Filing Date: 2001-03-06
Classification: G06F

Abstract:
A processor comprising:a first instruction cache configured to store instructions;a second instruction cache configured to store instructions; anda fetch unit coupled to said first instruction cache and said second instruction cache, wherein said fetch unit is configured to generate a fetch address from a plurality of fetch address sources, and wherein said fetch unit is configured to select one of said first instruction cache and said second instruction cache from which to fetch instructions stored at said fetch address, and wherein said fetch unit is configured to select said one of said first instruction cache and said second instruction cache dependent upon which one of said plurality of fetch address sources is a source of said fetch address, and wherein said fetch unit is configured to generate a prefetch address for said second instruction cache if said first instruction cache is selected for fetching said instructions stored at said fetch address, and wherein said first instruction cache is coupled to receive second instructions prefetched from said second instruction cache in response to said prefetch address, and wherein said first instruction cache is configured to store said second instructions if said second instructions are not already stored in said first instruction cache.