Patent ID: 8200901
Filing Date: 2012-06-12
Classification: G06F,H04L

Abstract:
1. An apparatus, comprising: a plurality of processor cores, each comprising a computation unit and a memory; and an interconnection network to transmit data among the processor cores; with two or more of the memories in respective cores having a portion thereof configured as a cache for storing cached data from a memory that is external to the processor cores, and with one or more of the processor cores configured to transmit a message over the interconnection network to another one of the processor cores, in response to a request to access cached data, to access the cached data stored in the portion of the memory configured as a cache in the other processor core receiving the message, with the processor core that transmits the message configured to maintain information sufficient to identify a cache location to be accessed and is not required to access directory information stored external to the processor core to identify the cache location, with the processor core that transmits the message further including a buffer to store the maintained information.