Patent ID: 6145065
Filing Date: 2000-11-07
Classification: G06F

Abstract:
A multiple address holding memory apparatus which is shared by a plurality of processes or a plurality of processors and which transfers data with said plurality of processes or said plurality of processors, said apparatus comprising:a main memory part having an address input terminal;an address bus for inputting addresses which are used for accessing said main memory part from said plurality of processes or said plurality of processors in accordance with a first order, and for inputting control signals which control said main memory part;a data bus for transferring data between said plurality of processes or said plurality of processors and said main memory part;an address temporary part which is disposed at said address input terminal of said main memory part, said address temporary memory part holding a plurality of addresses which are inputted through said address bus and a plurality of control signals which correspond to said plurality of addresses, and said address temporary memory part supplying said addresses which are held therein to said main memory part while supplying said control signals to said main memory part; anda permutation part which permutes said plurality of addresses held in said address temporary memory part into a second order which realizes high-speed accessing of said main memory part regardless of said first order in which addresses are input in said address temporary memory part for accessing said main memory part, said address temporary memory part supplying said addresses and said control signals to said main memory part sequentially in accordance with said second order, wherein said second order gives higher priority to permutation in accordance with priority ranks of accesses than to permutation in accordance with an order which realizes high-speed accessing.