Patent ID: 6635538
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:(a) preparing a semiconductor substrate having a major surface of a first conductivity type; (b) forming a first insulating film on said major surface; (c) forming a gate electrode on said first insulating film; (d) selectively introducing an impurity into said major surface with said gate electrode as a mask to selectively form a pair of low-concentration semiconductor layers in said major surface that are separated from each other with at least a portion of a region immediately below said gate electrode interposed therebetween; (e) forming a second insulating film for covering said gate electrode and said first insulating film at least after said step (c); (f) depositing a material whose main component is different from that of said second insulating film so as to entirely cover an exposed surface above said major surface after said steps (d) and (e); (g) anisotropically etching said material deposited in said step (f) to form sidewalls for covering sides of said gate electrode and a portion of said first insulating film adjacent to said gate electrode; (h) performing a selective etching to selectively remove a portion of said second second insulating film existing along said first insulating film and uncovered by said sidewalls; (i) selectively introducing an impurity into said major surface with said gate electrode, said second insulating film, and said sidewalls as a mask to selectively form a pair of high-concentration semiconductor layers of a second conductivity type having opposed edges recessed from opposed edges of said pair of low-concentration semiconductor layers, being deeper and higher in concentration than said pair of low-concentration semiconductor layers, in said major surface at least after said step (g); and (j) connecting a pair of main electrodes to said pair of high-concentration semiconductor layers, respectively, wherein said sidewall formed in step (g) remains after step (j) is carried out.