Patent ID: 6639446
Filing Date: 2003-10-28
Classification: H03D

Abstract:
A mixer circuit including a first mixer circuit comprising:a first impedance element that has a DC path and is connected to a first fixed bias point; a first MOS transistor having its drain connected to said first impedance element; a second MOS transistor having its drain connected to a source of said first MOS transistor; a second fixed bias point connected to a source of said second MOS transistor; a first signal input terminal that is connected to a gate of said first MOS transistor, the first signal input terminal being supplied with an RF signal; a second signal input terminal that is connected to a gate of said second MOS transistor, the second signal input terminal being supplied with a local signal; an output terminal connected to a connecting point of said first impedance element and said first MOS transistor; a first bias circuit for applying a bias voltage VG1 to the gate of said first MOS transistor, the bias voltage VG1 being defined with respect to said second fixed bias point; and a second bias circuit for applying a bias voltage VGS2 to the gate of said second MOS transistor, the bias voltage VGS2 being defined with respect to said second fixed bias point, wherein a relationship (VG1âˆ’VGS2)GS2âˆ’VT1) is established, where VT1 is a threshold voltage of said first MOS transistor.