Patent ID: 8954632
Filing Date: 2015-02-10
Classification: G06F,H02M

Abstract:
1. An apparatus comprising: an input/output (I/O) interface circuit comprising a controller and a memory; wherein the memory is adapted to store a plurality of commands to regulate the I/O interface circuit, the commands indicate I/O states of the I/O interface circuit and time durations associated with the I/O states, and at least one of the commands has a format comprising at least one of a first field to control whether an associated I/O terminal of the I/O interface circuit is driven and used for sampling during the time duration and a second field to control whether a data direction for an associated I/O terminal of the I/O interface circuit is inverted; and wherein the controller is adapted to execute the commands to place the I/O interface circuit in the I/O states in a predetermined sequence.