Patent ID: 7813447
Filing Date: 2010-10-12
Classification: H04L

Abstract:
1. An apparatus for dynamic phase equalization, the apparatus comprising: a transmitter history module configured to store a plurality of bits from a data stream that is transmitted through a communication channel; a transmitter detection module configured to detect a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value; a driver module configured to transmit the data stream by driving the communication channel with a drive signal at a first voltage for a bit time interval in response to a bit with the first value and driving the communication channel with the drive signal at a second voltage for the bit time interval in response to a bit of the second value; and a transition module configured to pre-drive the communication channel to the second voltage of the transition bit for a pre-drive time interval during the bit time interval of the pre-transition bit, the pre-drive time interval ending concurrently with an end of the bit time interval, wherein the pre-drive time interval is in a range of ten to seventy percent of the bit time interval; wherein the transmitter history module, the transmitter detection module, the driver module, and the transition module comprise one or more of logic hardware and executable code, the executable code stored on a non-transitory computer readable medium.