Patent ID: 8399316
Filing Date: 2013-03-19
Classification: G11C,H01L

Abstract:
1. A method for fabricating a microelectronic device with one or plural double-gate transistors, comprising: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form a second gate of the double-gate, the first block and the second block being located on opposite sides of a channel semiconducting zone and separated from the channel semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, the first block being supported on the substrate, the channel semiconducting zone being superposed on said first block and the second block being superposed on the channel semiconducting zone; and b) doping at least one semiconducting zone in the second block of at least one given structure among structures, using at least a first implantation selective relative to the first block, the first implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to a principal plane of the substrate passing through the semiconducting zone not being implanted, said principal plane being defined by a surface of the substrate on which the one or plural structures is formed.