Patent ID: 6028931
Filing Date: 2000-02-22
Classification: G11C

Abstract:
An encryption code decoding prevention circuit for a semiconductor memory device, comprising:a plurality of encryption code cells, each storing an encryption data on each bit line and outputting a corresponding encryption code data in accordance with selectively enabled multiple encryption word lines;an encryption word line operator for enabling a corresponding encryption word line by incrementing an internal count value by one each time an output detecting signal turns to a first prescribed level, stopping further counting when all ready-set values are counted, and continuously outputting a carry value to an output buffer;a word line operator for operating a corresponding word line selected from a plurality of word lines in accordance with an input address signal;a plurality of read data encrypting processors for encrypting data output from memory cells by using the encryption code data output from the encryption code data cells;an output data detector for enabling the output detecting signal when all bit lines are judged not to have data thereon, by checking an n-bit output applied from the read data encrypting processors to the output buffer; andthe output buffer for amplifying the n-bit data output from the read data encrypting processors and outputting an output data of ""1"" each time the carry value is applied thereto from the encryption word line operator.