Patent ID: 6847369
Filing Date: 2005-01-25
Classification: G06T,G09G

Abstract:
1. A graphics system comprising: a data bus having a width of n words of b bits, wherein the data bus is configured to convey data words in a series of sequential bus cycles, wherein the number of data words conveyed in each bus cycle is less than or equal to n, wherein n and b are positive integers, wherein n is greater than or equal to two; a data queue coupled to the data bus, and configured to receive and store the data words, wherein the data queue is subdivided into n independent FIFO memories, and wherein no more than one data word of b bits is stored in each FIFO memory in a bus cycle; and a state machine coupled to the data queue, and configured to detect and retrieve data words stored in the FIFO memories, wherein the state machine maintains the sequence of the data words as part of retrieving the data words from the FIFO devices; wherein the data queue further comprises n input multiplexers, wherein each input multiplexer selects one data word and conveys the selected data word to one FIFO memory in response to external control signals, wherein the control signals are generated to form a regular, continuous and repeating pattern of FIFO memory usage, wherein each FIFO memory stores one data word for every n data words received by the data queue.