Patent ID: 6696713
Filing Date: 2004-02-24
Classification: H01L

Abstract:
A semiconductor memory which comprises:an element isolation region constituted by an element isolating insulation film and selectively formed in a semiconductor substrate, thereby isolating an element region by said element isolation region; a first diffusion region of a first conductivity type, which is formed on a surface of said element region; a plurality of electrodes formed selectively on a surface of said semiconductor substrate; a gate insulating film formed on the side wall and bottom face of said electrodes; a monocrystalline silicon layer of a second conductivity type which is located between said electrodes, opposite sidewalls of said monocrystalline silicon layer being contacted with said gate insulating film, and a bottom face of said monocrystalline silicon layer being contacted with said first diffusion region; a second diffusion region of a first conductivity type, which is formed on a surface of said monoctystalline silicon layer, said second diffusion region continuously extending from one of each pair of adjacent ones of said electrodes to the other of said each pair; and an insulating film formed on said electrodes, a top surface of said insulating film being flush with a top surface of said second diffusion region.