Patent ID: 8468482
Filing Date: 2013-06-18
Classification: G06F,Y02P

Abstract:
1. A method comprising: providing an extraction of an integrated circuit design; using the extraction, compiling an interconnect model, comprising a via cell represented by a first via cell model comprising at least X resistance values, wherein X is an integer 1 or greater; using the extraction, compiling a plurality of second via cell models, each comprising a via cell represented by at least Y resistance values, wherein Y is an integer greater than X; indicating a selected net of the integrated circuit design; using at least one processor, performing a circuit simulation on the integrated circuit design using cells of the interconnect model and second via cell models comprising: for at least one via with the selected net, substituting a first via model associated of the interconnect model corresponding to the at least one via with one of the second via models, while other via cells not associated with the selected net continue to be represented using the first via model; calculating simulation results for a first block of the integrated circuit design using a substituted second via model; and calculating simulation results for a second block of the integrated circuit design, wherein in a tree of the integrated circuit design, the second block is linked to the first block, and the second block is hierarchically above the first block.