Patent ID: 6768196
Filing Date: 2004-07-27
Classification: B81B,H01L

Abstract:
A packaged microchip comprising:a stress sensitive microchip having a microchip coefficient of thermal expansion; a package having a package coefficient of thermal expansion; and an isolator having an isolator coefficient of thermal expansion, the isolator being connected between the stress sensitive microchip and the package, the microchip coefficient of thermal expansion being closer to the isolator coefficient of thermal expansion than it is to the package coefficient of thermal expansion, wherein the stress sensitive microchip has a bottom microchip surface, the isolator also having an isolator surface that both faces and is connected to the bottom microchip surface, the isolator surface having a surface area that is smaller than the area of the bottom microchip surface, the isolator forming a space between at least a portion of the bottom microchip surface and the package, the space being free of the isolator.