Patent ID: 6707404
Filing Date: 2004-03-16
Classification: H03M

Abstract:
An M+N bit DAC comprising:an N-bit main interpolation circuit for interpolating, in response to an N-bit portion of an M+N bit input word, between a first and second voltages that have been produced on first and second conductors, respectively, in response to an M-bit portion of the M+N bit input word; a calibration interpolation circuit; a memory circuit for storing digital error correction information corresponding to various values of the first voltage and the second voltage; conversion circuitry responsive to the M-bit portion of the M+N bit input word to convert digital error correction information from the memory to analog correction signals applied to inputs of the calibration interpolation circuit; and outputs of the N-bit interpolation circuit and the calibration interpolation circuit being coupled to inputs of an output amplifier so as to correct integral nonlinearity errors associated with the first and second voltages.