Patent ID: 6534348
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A method of fabricating a transistor which comprises the steps of:(a) providing a first monocrystalline silicon layer; (b) epitaxially depositing a first layer of dielectric over said first silicon layer which is substantially lattice matched with said first silicon layer and substantially monocrystalline; (c) epitaxially depositing and forming a first electrically conductive gate electrode over said first layer of dielectric which is substantially lattice matched with said first silicon layer and said first layer of dielectric; (d) epitaxially depositing a second layer of dielectric conformally over said first gate electrode and exposed portions of said first layer of dielectric which is substantially lattice matched with said first silicon layer and substantially monocrystalline; (e) epitaxially depositing a second monocrystalline silicon layer over said second layer of dielectric; (f) epitaxially depositing a third layer of dielectric over said second silicon layer which is substantially lattice matched with said first silicon layer and substantially monocrystalline; (g) epitaxially depositing and forming a second electrically conductive gate electrode over said third layer of dielectric which is substantially lattice matched with said first silicon layer and said first layer of dielectric; and (h) forming source and drain regions in said second silicon layer, wherein said first and second monocrystalline silicon layers have a (111) crystallographic orientation.