Patent ID: 6075934
Filing Date: 2000-06-13
Classification: G06F,H01L

Abstract:
A method for optimizing a semiconductor circuit based upon a netlist and component placement information, the method comprising:identifying a first net of a plurality of nets associated with a first circuit region having at least a first contact pin associated with a first contact pin region;identifying a second contact pin associated with a second contact pin region when the first net comprises a plurality of contact pins;determining a net class for the first net based upon the first contact pin region and the second contact pin region, whereinthe first net has a first net class if the first contact pin region and the second contact pin region are the same,the first net has a second net class if the first contact pin region and the second contact pin region are different;the first net has a third net class if the first contact pin region is defined by the netlist to be connected to a power supply;placing the first net if the first net has a third net class;placing the first net if the first net has a first net class; andplacing the first net if the first net has a second net class.