Patent ID: 6833753
Filing Date: 2004-12-21
Classification: H02M

Abstract:
A system for signal boosting, comprising:a capacitance boosting component, including: a first transistor operable to receive a supply voltage at a gate and a drain; a second transistor operable to receive a clock signal at a gate; a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor; a third transistor operable to receive the clock signal at a gate and further operable to receive the supply voltage at a source, wherein a drain of the third transistor is electrically connected to the positive terminal of the capacitor; and a fourth transistor operable to receive an inverse of the clock signal at a gate and further operable to receive the supply voltage at a source, wherein a drain of the fourth transistor is electrically connected to the positive terminal of the first capacitor; and a boost component electrically connected to the capacitance boosting component, wherein an output of the boost component is within a selected boost voltage range.