Patent ID: 9042149
Filing Date: 2015-05-26
Classification: G11C

Abstract:
1. A method, comprising: configuring a plurality of static random access memory cells in rows and columns, wherein a first pair of memory cells is situated in a first row of the memory array, the first pair of memory cells including first and second memory cells that couple to a first single intra-pair bitline between the first and second cells to share the first single intra-pair bitline, the first and second memory cells also coupling to first and second opposed inter-pair bitlines, respectively; sharing the first single intra-pair bitline for writing and reading operations of the first pair of memory cells; sharing the first opposed inter-pair bitline with a second pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the second pair of memory cells; and sharing the second opposed inter-pair bitline with a third pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the third pair of memory cells.