Patent ID: 7606106
Filing Date: 2009-10-20
Classification: G11C

Abstract:
1. A semiconductor memory device which operates by using a fixed power and a variable power, comprising: a plurality of word lines which select rows of a memory cell array; a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate; a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode; a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode; a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode; and a row decoder to which the variable power is applied and which is connected to the plurality of word line drivers and selects a word line on the basis of an address signal.