Patent ID: 9164858
Filing Date: 2015-10-20
Classification: G01R,G06F

Abstract:
1. A system for optimized board test and configuration, the system comprising: a JTAG (Joint Test Action Group) control system; and an electronic assembly, wherein the electronic assembly comprises a programmable logic device with pins and a device under test connected to the pins of the programmable logic device, a fixed part of the programmable logic device comprises an internal JTAG interface which comprises an instruction register, JTAG scan-cells that are connected with the pins of the programmable logic device, a multiplexer, a de-multiplexer, a test data input (TDI), and a test data output (TDO), a reprogrammable part of the programmable logic device comprises a Variable-Length Shift Register with an accumulating buffer (VLSR(B)) architecture connected with the pins, a JTAG interface comprises a group of separate scan-chains, and the VLSR(B) comprises scan-cells connected to the pins and form one or more scan-path, wherein each or part of cells are supplemented with bypassing circuits.