Patent ID: 8604962
Filing Date: 2013-12-10
Classification: H03M

Abstract:
1. An sample-and-hold-plus-amplifier (SHA)-less first-stage circuit in an analog-to-digital converter (ADC) having circuitry for both tracking an input signal and sampling and holding that input signal on a plurality of sampling capacitors to perform an analog-to-digital conversion of the sampled input signal in a HOLD mode, the SHA-less first-stage ADC circuit comprising: a duplicate single SHA-less ADC first-stage circuit forming a combined SHA-less first stage ADC circuit including a first single SHA-less ADC first-stage circuit having a first residue amplifier and a second single SHA-less ADC first-stage circuit having a second residue amplifier, in which an analog input of the first single SHA-less ADC first-stage circuit and an analog input of the second single SHA-less ADC first-stage circuit are connected to an analog input of the combined SHA-less first stage ADC circuit; the analog output a first single SHA-less ADC first-stage circuit and the analog output of the second single SHA-less ADC first-stage circuit are connected to the analog output of the combined SHA-less first stage ADC circuit; the input and output of the plurality of sampling capacitors are switchably connected to first fixed-voltage references during a portion of the time when the plurality of sampling capacitors of the second single SHA-less ADC first stage is connected to the combined first stage SHA-less ADC input, whereby the plurality of sampling capacitors of the first single SHA-less ADC first stage is reset; the plurality of sampling capacitors of the first single SHA-less ADC first stage is switchably connected to the combined SHA-less first stage ADC input for a period of time which begins before the HOLD period of the second single SHA-less ADC first stage; the input and output of the plurality of sampling capacitors is switchably connected to second fixed-voltage references during a portion of the time when the plurality of sampling capacitors of the first single SHA-less ADC first stage is connected to the combined first stage SHA-less ADC input, whereby the plurality of sampling capacitors of the second single SHA-less ADC first single stage is reset; and the plurality of sampling capacitors of the second single SHA-less ADC first single stage is switchably connected to the combined SHA-less first stage ADC input for a period of time which begins before the HOLD period of the first single SHA-less ADC first stage.