Patent ID: 8558599
Filing Date: 2013-10-15
Classification: G06F,H03K

Abstract:
1. A clock network, comprising: a first plurality of shield wires associated with a first plurality of clock lines connected to a clock signal, wherein the first plurality of clock lines is shielded by only the first plurality of shield wires; a second plurality of shield wires associated with a second plurality of clock lines connected to the clock signal, wherein the second plurality of clock lines are shielded by only the second plurality of shield wires; a first plurality of clock activity program circuits coupled to receive said clock signal, wherein each clock activity program circuit of the first plurality of clock activity program circuits is coupled to one clock line of the first plurality of clock lines, and wherein the first plurality of clock activity program circuits delivers an active high clock signal on the first plurality of clock lines to a first plurality of components; and a second plurality of clock activity program circuits coupled to receive said clock signal, wherein each clock activity program circuit of the second plurality of clock activity program circuits is coupled to one clock line of the second plurality of clock lines, wherein the second plurality of clock activity program circuits delivers an active low clock signal on the second plurality of clock lines to a second plurality of components, and wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes generated by the clock network.