Patent ID: 8417890
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A computer-implemented method for managing cache coherency for self-modifying code in an out-of-order execution system having a separate first level instruction cache (I-Cache) and first level data cache (D-Cache), the out-of-order execution system executing a plurality of instructions in an execution pipeline, the method comprising: processing, by a load store unit (LSU), a store operation of a to-be-stored operand of an instruction being executed, wherein the LSU is configured to perform loads from the D-Cache and stores to the D-Cache of operands of instructions being executed, wherein the to-be-stored operand is to be stored at an operand address; determining, by the LSU, whether a store target cache line associated with the to-be-stored operand is currently exclusive in the D-Cache; sending, by the LSU, a request for an exclusive ownership of the store target cache line based on the store target cache line failing to be exclusively owned by the D-Cache, wherein the request initiates a retrieval of the store target cache line into the D-Cache; reserving, by the LSU based on the sending, a program-store-compare (PSC) tracking resource comprising a fetch address register (FAR) maintained within the LSU, the FAR comprising the operand address; releasing, by the LSU, the reserved PSC tracking resource, based on determining, by a PSC tracking manager, that instruction addresses of instructions being executed in the execution pipeline do not match the operand address in the FAR; and maintaining by the LSU, the reserved PSC tracking resource, based on determining, by a PSC tracking manager, that instruction addresses of instructions being executed in the execution pipeline match the operand address in the FAR.