Patent ID: 8375346
Filing Date: 2013-02-12
Classification: G06F

Abstract:
1. A method of using a processing device for laying out a power wiring of a semiconductor device, the method comprising: modeling the power wiring as an analysis model comprising a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor, wherein inverse ratios of the current and an allowable current of each of the plurality of element resistors included in the path are obtained, the bottleneck element resistor is selected in a critical path that is a path having a minimum sum of the inverse ratios, and one or more of the operations of modeling the power wiring, obtaining the voltage values, searching the path of the current, selecting the bottleneck element resistor, and changing the resistance value of the bottleneck element resistor are performed using the processing device.