Patent ID: 8049544
Filing Date: 2011-11-01
Classification: G11C,H03L

Abstract:
1. A delay locked loop (DLL) circuit, comprising: a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal; a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock; a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal; and a delay replica model unit configured to reflect a delay condition of the reference clock on the delay locked clock and to output the feedback clock.