Patent ID: 9135980
Filing Date: 2015-09-15
Classification: G06F,G11C

Abstract:
1. A memory control circuit, for controlling a data reading process of a memory module, during which the memory module transmitting a data signal and a data strobe signal that is used to recover the data signal to the memory control circuit, the data strobe signal comprising a preamble part, and the memory control circuit comprising: a clock generating circuit for generating a clock; a control unit coupled to the memory module and the clock generating circuit for controlling an impedance matching circuit of the memory module and generating an enabling signal according to the clock; and a sampling circuit coupled to the control unit for sampling the data strobe signal according to the enabling signal to generate a sampling result; wherein, the control unit first control the impedance matching circuit to make the data strobe signal keep at a fixed level before the preamble part and then controls the sampling circuit to sample the data strobe signal according to the enabling signal, and adjusts an enabling time of the enabling signal according to the sampling result and starts the process of recovering the data signal according to the enabling signal.