Patent ID: 6741499
Filing Date: 2004-05-25
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising:a memory cell array having electrically erasable and programmable non-volatile memory cells, a part of said memory cell array being defined as a initial set-up data region for storing a plurality of initial set-up data that define memory operation conditions; a plurality of data latch circuits for holding the respective initial set-up data read out from said initial set-up data region; a controller for controlling data program and erase operations for said memory cell array; and a clock generator for generating a clock signal that is used to define an operation timing of said controller, wherein said controller is configured to perform such an initial set-up operation that sequentially reads out said plurality of initial set-up data stored in said initial set-up data region and transfers them to the respective data latch circuits on receipt of power-on or a command input, said initial set-up operation being so performed as to read out a clock cycle adjustment data within said plurality of initial set-up data stored in said initial set-up data region in the beginning, thereby adjusting a clock cycle of said clock signal output from said clock generator by use of said clock cycle adjustment data, and then reads out the remaining initial set-up data by use of the adjusted clock signal.