Patent ID: 6657908
Filing Date: 2003-12-02
Classification: G11C

Abstract:
A global input/output precharge apparatus for use in semiconductor memory, comprising;a latch configured to latch data on a global input/output line and a complementary global input/output line, a global input/output line delay configured to delay the data on the global input/output line and the complementary global input/output line by a predetermined time delay; a plurality of global input/output line precharge logics for pre-charging the global input/output line in response to a feedback signal from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is fed back on the output of the global input/output line precharge logics and applying a ground voltage to the global input/output line when a second logic state is fed back on the output of the global input/output line precharge logics; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is fed back on the output of the global input/output line precharge logics and applying the ground voltage to the complementary global input/output line when the second logic state is fed back on the output of the global input/output line precharge logics, wherein one of the global input/output precharge logics includes a pulse generating logic coupled to receive a write enable signal to generate a pulse when the write enable signal falls; and a NOR gate coupled to receive the output of the pulse generating logic and the output of the global input/output line delay.