Patent ID: 7518176
Filing Date: 2009-04-14
Classification: G11C,H01L

Abstract:
1. A programmable nonvolatile memory, comprising: a memory cell including a memory cell transistor having first and second impurity regions formed at a surface of a substrate region and a charge accumulation region arranged on the substrate region between the first and second impurity regions for storing data in a nonvolatile manner according to an amount of charges accumulated in said charge accumulation region; a first conductive line arranged corresponding to said memory cell transistor; a first contact for electrically connecting the first impurity region with said first conductive line; a peripheral transistor arranged in a region different from a region for arranging said memory cell on a common semiconductor substrate with said memory cell and used in other function than data storage, said peripheral transistor having third and fourth impurity regions formed at a surface of said semiconductor substrate and a control gate formed above the semiconductor substrate between the third and fourth impurity regions for receiving a signal for setting an on and off state thereof; a second conductive line arranged corresponding to said peripheral transistor; and a second contact for electrically connecting the third impurity region with said second conductive line, a distance between said first contact and said charge accumulation region along a direction connecting the first and second impurity regions being set according to a design rule different from a design rule for determining a distance between said control gate of said peripheral transistor and said second contact along a direction connecting the third and fourth impurity regions, wherein said charge accumulation region is a floating gate formed of a conductive material and a distance between said floating gate and said first contact is set to be greater than a distance between said second contact and said control gate.