Patent ID: 6383866
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:forming a gate insulating film and a gate electrode on a semiconductor substrate; forming an insulative protection layer on an upper portion of said gate electrode and along a side wall thereof; forming an inter-layer insulating layer over said semiconductor substrate including over said insulative protection layer; flattening an upper surface of said inter-layer insulating layer by effecting a flow; forming an opening portion in said flattened inter-layer insulating layer, the opening portion extending to said insulative protection layer and to said semiconductor substrate, by selectively etching said inter-layer insulating layer; and after said forming an opening portion, forming a first conductive layer so as to extend from the upper surface to an interior surface of the opening portion, and forming a recess which is defined by the first conductive layer, wherein a peripheral edge of said first conductive layer is disposed directly on the upper surface of the inter-layer insulating layer; forming a capacitor insulating film on the first conductive layer; and forming a second conductive layer on the capacitor insulating film, said second conductive layer being formed in said recess so as to completely fill said recess and said opening portion.