Patent ID: 6787843
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A nonvolatile semiconductor memory cell, comprising:a substrate; an active region formed in said substrate and serving to define source/drain regions; a first insulating layer formed on said substrate; a charge-storing layer formed on said first insulating layer; a second insulating layer formed on said charge-storing layer; a control layer formed on said second insulating layer and defining word line stacks; an insulating protective layer surrounding at least said word line stacks; a third insulating layer formed over a whole area on said substrate and said word line stacks, said third insulating layer having openings formed therein; and at least one insulating web having sidewalls formed on said third insulating layer and serving to define at least one bit line with a source line and a drain line at at least one of said sidewalls, said source and drain lines each directly making contact with said source/drain regions through said openings in said third insulating layer.