Patent ID: 6772268
Filing Date: 2004-08-03
Classification: H04L

Abstract:
A memory access device for storing and retrieving data packet information in a plurality of memory addresses, said memory access device comprising:a first interface port for receiving control signals and address signals from a host information system; a plurality of second interfaces, each said second interface coupled to a processor, said second interfaces receiving request for data signals from said processors; a plurality of third interfaces, each said third interface having a plurality of memory address allocations, said third interfaces configured to access said memory address allocations; a lookup controller coupled to said second interfaces and said third interfaces for receiving each said information request signal from said second interfaces, looking up the information at said third interfaces and returning the information to said second interfaces; and a timing source for synchronizing said first, second and third interfaces with said lookup controller; wherein said first interface arbitrates which of said third interfaces said lookup controller accesses during each synchronizing timing cycle.