Patent ID: 6035410
Filing Date: 2000-03-07
Classification: G06F,H03L,Y02D

Abstract:
A microprocessor with reduced power consumption in accordance with its usage condition, comprising:a PLL section to generate and output an internal clock signal based on an external clock signal, said PLL section begin operated in accordance with said internal clock signal;a processor to execute an instruction in accordance with said internal clock signal output by said PLL section;an instructing section to latch data output from said processor by the execution of said instruction, to output a frequency multiplication rate instructing signal corresponding to said latched data and, to output an enable signal to indicate whether a multiplication rate of the internal clock signal should be changed;a data selecting section to selectively output said frequency multiplication rate instructing signal or an external clock selecting signal in accordance with said enable signal;an inhibiting section to inhibit said internal clock signal output by said PLL section from being supplied to said processor for a predetermined period from a time of the output of said enable signal to a time when the frequency of said internal clock signal in said PLL section becomes stable; anda frequency changing unit, provided in said PLL section, to change the frequency of said internal clock signal in response to the data selectively output from said data selecting section.