Patent ID: 6611269
Filing Date: 2003-08-26
Classification: G09G,H04N

Abstract:
A video display unit comprising:a frame memory storing display data; a display timing generation means for generating a display timing; a memory control means for reading out display data from said frame memory by synchronizing to said display timing generation means; an output buffer means for temporarily storing display data read out by said memory control means; an arithmetic unit for generating display data by carrying out at least one operation within one period of a pixel clock; a data selection means for reading out display data from said output buffer means by synchronizing to the pixel clock and for selection data inputted to said arithmetic unit; and an instruction sequencer for controlling said data selection means and said arithmetic unit by synchronizing to the timing of said display timing generation means, said instruction sequencer having: an instruction memory for storing control information to control said arithmetic unit and said data selection means; an instruction execution control means for reading out at least one or more instructions within one period of the pixel clock; and an instruction decoder means for decoding said read out instructions and for controlling data inputted to said arithmetic unit by said data selection means.