Patent ID: 7303956
Filing Date: 2007-12-04
Classification: G11C,H01L

Abstract:
1. A method of forming an array of non-volatile memory cells on a semiconductor substrate, comprising: forming a layer of conductive material across the substrate with a first layer of dielectric therebetween and a second layer of a first type of dielectric thereover, removing portions of at least the conductive material and second layer of dielectric in strips having widths in a first direction and having lengths extending across the substrate in a second direction, the first and second directions being perpendicular to each other, removing portions of the second layer of dielectric through masking elements having dimensions in the second direction according to a minimum resolvable element size in order to form grooves in the second layer of dielectric between masking elements, including removing portions of the second layer of dielectric under the masking elements to reduce the dimensions of remaining islands of the second layer of dielectric in the second direction between opposing sidewalls thereof, forming spacers of a second type of dielectric along the sidewalls of the islands of the second layer of dielectric with a first set of gaps between the spacers in the second direction, removing the remaining portions of the second layer of dielectric from between the spacers, thereby forming a second set of gaps between the spacers in the second direction, and thereafter removing portions of the layer of conductive material exposed in the first and second set of gaps between the spacers, thereby to leave floating gates under the spacers with spaces therebetween in the second direction.