Patent ID: 6795954
Filing Date: 2004-09-21
Classification: G06F

Abstract:
A method of calculating skews for memory cells and flip-flops in a circuit design to reduce peak power comprising:receiving a circuit design containing memory cells and other clocked cells; constructing a first graph that includes a union of all inputs, vertices representative of the memory cells and the other clocked cells, a union of all outputs, and edges between the vertices each having a length equal to a delay between corresponding vertices minus a clock period; constructing a second graph having vertices representative of only the memory cells and corresponding edges such that the maximum length between any two corresponding vertices is less than zero; calculating a skew for each of the memory cells from the second graph; constructing a third graph from the first graph by merging the vertices of the memory cells into a single vertex; calculating a skew for each of the other clocked cells from the third graph; normalizing each skew calculated for the other clocked cells; recalculating the skew for each of the memory cells from the normalized skew calculated for the other clocked cells; and generating as output the recalculated skew for each of the memory cells.