Patent ID: 7972929
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. A method for manufacturing a SONOS semiconductor device comprising: simultaneously forming a device isolation layer in a semiconductor substrate to define a memory region and a logic region, and also forming device isolation layers to define the logic region into an ultra-high voltage region, a high voltage region and a low voltage region; and then forming an ONO layer in the logic region and the memory region by sequentially forming a first oxide layer, a nitride layer and a second oxide layer over the entire surface of the semiconductor substrate; and then forming a first photoresist pattern in the memory region and the high voltage region; and then forming an ONO layer pattern in the memory region and the high voltage region by implementing a first etching process using the first photoresist pattern as a mask; and then removing the first photoresist pattern; and then depositing a first silicon oxide material over the entire surface of the semiconductor substrate; and then forming a second photoresist pattern in the memory region and the ultra-high voltage region; and then simultaneously removing the second oxide layer of the ONO layer pattern in the high voltage region while forming a first gate oxide layer pattern composed of the first silicon oxide material in the memory region and the ultra-high voltage region by implementing a second etching process using the second photoresist pattern as a mask; and then removing the nitride layer of the ONO layer pattern in the high voltage region by implementing a third etching process on the semiconductor substrate; and then removing the second photoresist pattern; and then forming a second gate oxide layer pattern over the entire surface of the semiconductor substrate semiconductor substrate including the low voltage region.