Patent ID: 6326806
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A circuit arrangement for reconfiguration of an FPGA over a communications channel, comprising:a physical interface circuit arranged for connection to a communications channel;a storage element;an FPGA coupled to the storage element and to the physical interface circuit;a configuration control circuit coupled to the FPGA and to the storage element, the configuration control circuit being configured and arranged to load the FPGA with an initial configuration bitstream that implements both a communications protocol and a control function, wherein the control function writes configuration bits received by the FPGA from the physical interface circuit to the storage element and generates a reconfiguration signal responsive to a first predetermined condition, the configuration control circuit being further configured and arranged to load a second configuration bitstream from the storage element into the FPGA responsive to the reconfiguration signal from the FPGA.