Patent ID: 6693833
Filing Date: 2004-02-17
Classification: G11C

Abstract:
A portion of a random access memory comprising:a first sub-array and a second sub-array located adjacent each other forming a portion of a random access memory for a semiconductor die; and circuitry coupled to the first sub-array and second sub-array for storing row addresses of defective rows in the first sub-array and second sub-array and activating a redundant row in one sub-array of the first sub-array and second sub-array of random access memory when receiving a row address matching one of the stored row addresses of defective rows while disabling a redundant row arranged in the other sub-array of the first sub-array and second sub-array of random access memory in an order complementary to that of the activated redundant row, the circuitry comprising: a plurality of fuse banks to store the row addresses of defective rows and output a match signal in response to receiving the row address matching the one of the stored row addresses of defective rows; at least a first row decoder and at least a second row decoder connected to the respective first sub-array and second sub-array for activating redundant rows in the one sub-array of the first sub-array and second sub-array in response to receiving the match signal; and a plurality of enable fuses connected between the plurality of fuse banks and the at least a first row decoder and the at least a second row decoder for conducting the match signal to the at least a first row decoder and isolate the match signal from the at least a second row decoder to disable activation of the redundant row in the other sub-array of the first sub-array and second sub-array of said random access memory of said semiconductor die.