Patent ID: 6215692
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A non-volatile ferroelectric memory comprising:a cell array having a plurality of sub cell arrays, a plurality of global bitlines and at least one pair of reference global bitlines extending in a first direction to cross the sub cell arrays, local bitlines and reference local bitlines respectively corresponding to the global bitlines and the reference global bitlines that also extend in the first direction, wherein the local bitlines are located within a single corresponding sub cell array and are selectively coupled to corresponding global bitlines;a wordline driver on a first side of the cell array that provides a first driving signal for selecting a cell;a plateline driver on a second side of the cell array opposite from the first side of the wordline driver that provides a second driving signal for selecting the cell; anda reference bitline controller having a reference sense amplifier that senses a signal provided through one of the at least one pair of reference global bitlines and outputs a reference voltage.