Patent ID: 6072346
Filing Date: 2000-06-06
Classification: H03K

Abstract:
An apparatus, comprising:a first network for providing an asynchronous data signal to a second network that is synchronized with a system clock;means for synchronizing said asynchronous data signal with said system clock to convert said asynchronous data signal to a synchronized data signal;means for causing said synchronized data signal to be one of a first definite value or a second definite value independent of whether said asynchronous data signal and said system clock each transition substantially at the same point in time, wherein said means for causing comprises:an input node for receiving said synchronized data signal;an output node;means for switching said synchronized data signal to one of said first definite value or said second definite value, wherein said switching means comprises:at least two P type transistors connected in series and forming a first node therebetween;at least two N type transistors connected in series and forming a second node therebetween;wherein each of said at least two P type transistors and said at least two N type transistors have their gate connected to said input node; andfeedback means for controlling said means for switching based upon a voltage level present on the output node; andmeans for outputting said synchronized data signal only when said synchronized data signal is at one of said first or said second definite value.