Patent ID: 8929467
Filing Date: 2015-01-06
Classification: H04L

Abstract:
1. A system for one-wire communication bus of using pulse-edge for clock and pulse-duty-cycle for data, comprising: a reference clock signal input for receiving a reference clock signal; a data signal input for receiving a sequence of digital data; an electrical connection having a first end and a second end, for transferring an Edge-for-Clock-Duty-cycle-for-Data (ECDD) signal, said ECDD signal is an electrical pulse train wherein each pulse consists of a portion of level-high and a portion of level-low, a transition from level-low to level-high is defined as rising edge and a transition from level-high to level-low is defined as falling edge, the rising and falling edges are pulse-edges, a ratio of time used by level-high to time used by level-low is pulse-duty-cycle; a transmitter circuit for generating and outputting said ECDD signal, comprising: a receiver circuit for receiving and decoding said ECDD signal, comprising: wherein said data output of the transmitter is connected to the first end of said electrical connection; wherein said data input of the receiver is connected to the second end of said electrical connection.