Patent ID: 6051850
Filing Date: 2000-04-18
Classification: H01L,Y10S

Abstract:
An integrated power semiconductor device containing interleaved arrays of vertical insulated-gate bipolar transistor cells and vertical diode cells connected in antiparallel, comprising:a semiconductor substrate having first and second opposing faces;a cathode region of first conductivity type in said semiconductor substrate, at the first face;a first array of emitter regions of second conductivity type in said cathode region;a base region of first conductivity type extending from said cathode region to the second face and forming respective P-N junctions with the emitter regions in said first array;a second array of collector regions of second conductivity type in said base region, at the second face, said second array of collector regions disposed diametrically opposite said first array of emitter regions to thereby define an array of spaced vertical bipolar transistor cells;a third array of anode regions of second conductivity type in said base region, at the second face, interleaved within said second array to thereby define an array of spaced vertical diode cells between respective anode regions and said cathode region;a fourth array of source regions of first conductivity type in said second array of collector regions, but not in said third array of anode regions;insulated gate electrode means adjacent the second face for electrically connecting said fourth array of source regions to said base region in response to application of a predetermined forward bias thereto;an electrode at the first face, in ohmic contact with said cathode region and said first array of emitter regions; andan electrode at the second face, in ohmic and physical contact with said second, third and fourth arrays.