Patent ID: 6571364
Filing Date: 2003-05-27
Classification: G01R,G11C

Abstract:
A semiconductor integrated circuit device with fault analysis function, comprising:a memory circuit comprising a plurality of memory cells that are divided into a plurality of memory cell groups in which data stored in said memory cells addressed by address signals are read and then output; a scan path comprising a plurality of scan flip flops placed corresponding to said plurality of memory cell groups, each scan flip flop including a comparator for comparing said data read from said memory cells with expected values that have been previously prepared and then outputting a comparison result; and a comparison control circuit for inputting control signals and said address signal, generating a comparison control signal in order to initiate comparison operation between said data and said expected values by said comparators when said memory cells addressed by said address signals are equal to memory cells of at least one or more in each memory cell group within a range specified by said control signals which can be less than all memory cells within respective memory cell groups, and outputting said comparison control signal to each of said plurality of scan flip flops.