Patent ID: 6707096
Filing Date: 2004-03-16
Classification: H01L,Y10S

Abstract:
A memory cell comprising one of a plurality of laterally adjacent memory cells forming a memory array, the memory cell comprising:a substrate; a plurality of vertically upstanding storage poly node portions mutually separated by a plurality of recesses and disposed over the substrate, the storage poly node portions together forming a fork-like upper surface; a capacitor dielectric layer disposed substantially conformally over the fork-like upper surface of the storage poly node portions; and a plate electrode layer extending substantially conformally over the fork-like upper surface of the storage poly node portions with the capacitor dielectric layer disposed therebetween, the storage poly node portions, the capacitor dielectric layer and the plate electrode layer together forming a fork-like structure so that an upper surface of the plate electrode layer substantially conformally mimics the fork-like upper surface of the plurality of vertically upstanding storage poly node portions, the plurality of vertically upstanding storage poly node portions of the memory cell being laterally spaced from storage poly node portions of any adjacent memory cells of the plurality of laterally adjacent memory cells forming the memory array by a peripheral boundary, wherein each recess of the plurality of recesses is of lesser lateral extent between the storage poly node portions of the memory cell than a smallest lateral distance from any storage poly node portion of the memory cell across the peripheral boundary to any storage poly node portion of any laterally adjacent memory cell of the plurality of laterally adjacent memory cells forming the memory array.