Patent ID: 7013369
Filing Date: 2006-03-14
Classification: G11C

Abstract:
1. A memory control circuit for controlling writing and reading of data in and from a memory to be controlled based on an address signal and a control signal given from a central processing unit, comprising: a control register having a memory capacity of m bits or smaller for setting information necessary for controlling said memory; a plurality of input pins to which m-bit test data is input in parallel; an extension circuit for extending said data input to said input pins to n-bit data; a first selection circuit for selectively inputting n-bit data supplied from said extension circuit or said central processing unit based on a mode signal to switch between a test mode and a normal mode; a degeneration circuit for compressing n-bit data to be output in parallel to said central processing unit to m-bit data; a second selection circuit for selecting m-bit data compressed by said degeneration circuit or lower m-bit data in n-bit data to be output to said central processing unit based on a switch signal; and a plurality of output pins for outputting the m-bit data selected by said second selection circuit in parallel, wherein m<n.