Patent ID: 6867097
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. A method of making a flash memory cell including a substrate and a tunnel oxide layer formed on the substrate and a floating gate, the method comprising: depositing an insulator layer comprising a high temperature oxide directly on exposed portions of the tunnel oxide layer and the floating gate, the insulator layer being deposited to a thickness greater than a thickness of the floating gate, wherein the insulator layer is in contact with vertical surfaces of the floating gate to prevent charge leaking from the floating gate, and wherein the insulator layer is formed by a LPCVD process; polishing the insulator layer immediately after the step of depositing the insulator layer to reduce the thickness of the insulator layer and to provide a planar surface that exposes a top surface of the floating gate and the insulator layer; and depositing an ONO layer on the planar surface directly over the exposed top surface of the floating gate and the insulator layer.