Patent ID: 8600722
Filing Date: 2013-12-03
Classification: G06F

Abstract:
1. A method of hardware co-simulation of a circuit design, comprising: implementing the circuit design for programmable logic to establish a design under test (DUT); executing a user-specified sequence of scripting instructions with a scripting interface, each scripting instruction defined by an application programming interface (API); wherein at least one of the scripting instructions in the sequence specifies a write function, references a port of the DUT, and specifies a value to write to the port; wherein at least one of the scripting instructions in the sequence specifies a number of clock cycles for running the DUT; wherein the sequence of scripting instructions includes respective scripting instructions that specify: simulating the circuit design by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the sequence of scripting instructions that write to the port of the DUT and that read from and write to the shared memory instance; and outputting results of simulating the circuit design.