Patent ID: 6557022
Filing Date: 2003-04-29
Classification: G06F

Abstract:
An electronic circuit, characterized in that it includes:(a) a register file having first and second inputs and first through sixth outputs; (b) a first shifter receiving the first output of the register file; (c) a first multiplier receiving the second and third outputs of the register file and having an output; (d) a second multiplier receiving the fourth and fifth outputs of the register file and having an output; (e) a second shifter receiving the output of the first multiplier and having an output; (f) a third shifter receiving the output of the second multiplier and having an output; (g) a rounding multiplexer receiving the output of the first shifter and having an output; (h) a first adder receiving, at a first input, the output of the second shifter and having an output; (i) a multiplexer receiving either a zero or the output of the third shifter, and applying an output to a second input of the first adder; (j) a second adder receiving the outputs of the rounding multiplexer and the first adder, and having an output which is fed back to the first input of the register file; and (k) a third adder receiving the outputs of the third shifter and the sixth register output, and having an output which is fed back to the second input of the register file.