Patent ID: 6711648
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A method of substantially increasing the data bandwidth of a dynamic memory device, the dynamic memory device including at least one storage cell, a column decoder and an internal read/write data bus, the column decoder decoding a column address upon receipt thereof such that data stored in the at least one storage cell corresponding to the decoded column address is placed on the internal read/write data bus in response to receipt of an address transition detection (ATD) pulse generated by the dynamic memory device, the method comprising the step of temporarily suppressing the generation of the ATD pulse such that data selected from the at least one storage cell is not placed on the internal read/write bus until after a delayed generation of the ATD pulse, such that a first pipeline stage is thereby substantially defined; andfurther comprising the step of generating the delayed ATD pulse in response to a column address strobe (CAS) signal.