Patent ID: 6683473
Filing Date: 2004-01-27
Classification: H03K

Abstract:
An input termination circuit comprising:a first transistor coupled between a first terminal and a second terminal; a control circuit configured to monitor voltages on the first and second terminals and on a first voltage source, the control circuit being configured to couple the gate of the first transistor to a voltage that will keep the first transistor off during power off conditions; a second transistor and a third transistor, wherein during power off conditions, the second and third transistors are configured to couple the gate of the first transistor to the its acting source; a control circuit comprising a first circuit and a second circuit that operate without power from the first voltage source and that operate from power coming from the terminal having the higher voltage level; wherein the first circuit comprises: a fourth transistor and a fifth transistor coupled in series between the first terminal and the second voltage source, the gates of the fourth and fifth transistors being coupled to the first voltage source; a sixth transistor and a seventh transistor coupled in series between the first voltage source and the first terminal voltage, the gate of the seventh transistor being coupled to the first voltage source; an eight transistor coupled between the gate of the sixth transistor and a first common n-well node, the first common n-well node being coupled between the sixth and seventh transistors, the gate of the eight transistor being coupled to the first voltage source; and a ninth transistor coupled between the gate of the sixth transistor and the second voltage source, the gate of the ninth transistor being coupled to the first voltage source.