Patent ID: 7003630
Filing Date: 2006-02-21
Classification: G06F

Abstract:
1. An apparatus for proxy management of a plurality of intermediate memories associated with a plurality of heterogeneous processing elements executing different instruction sets, the plurality of heterogeneous processing elements not utilizing their own coherency mechanisms, the processing elements sharing a unified memory, the apparatus comprising: a proxy processor, independent from the plurality of heterogeneous processing elements, said proxy processor coupled to the plurality of intermediate memories, for executing proxy management instructions upon a TLB miss in one of the plurality of intermediate memories, to manage the plurality of intermediate memories and insure coherency between the plurality of intermediate memories associated with the plurality of heterogeneous processing elements; and a first plurality of intermediate memories associated with a first plurality of processing elements, the first plurality of intermediate memories being designed to interface to said proxy processor; at least one intermediate memory which is not designed to interface to said proxy processor; and an interface between said at least one intermediate memory and said proxy processor; wherein said proxy processor monitors memory use among said first plurality of processing elements, and said at least one intermediate memory, and executes said proxy management instructions to effect transparency between the plurality of processing elements and the unified memory.