Patent ID: 6826243
Filing Date: 2004-11-30
Classification: G06F

Abstract:
A circuit arrangement for the processing of binary signals which includes:a first, second and third stage arranged in a sequential fashion, wherein the first and third stages comprise: at least one logic arrangement for outputting each time at least one binary output signal, and for each logic arrangement at least one storage arrangement for storing the binary output signal, or the binary output signals, at instants which are defined by a clock signal which exhibits state transitions which occur in a cyclical sequence, at least one of the storage arrangements including a number of storage cells, each of which includes a respective output and stores, at the instant of an associated state transition within each of the cycles of the clock signal, the instantaneous value of each time one of the binary output signals and outputs it via its output, the outputs of the storage cells of each time one of the storage arrangements being connected to a common output of the relevant storage arrangement via a switching stage whereby the output of each storage cell is connected, in the time interval which commences with the associated state transition of the clock signal and terminates with the next state transition of the clock signal in the cyclical sequence, to the common output of the relevant storage arrangement, wherein at least one of the storage arrangements includes two storage cells which are constructed as D-flipflops and whose clock inputs can be supplied with a clock signal in the form of an at least approximately square-wave signal, a first one of the D-flipflops of the at least one storage arrangement being driven by the ascending edge for the purpose of storage whereas the second one of the D-flipflops is driven by the descending edge, the switching stage being controlled in conformity with the levels of the clock signal between state transitions.