Patent ID: 6770934
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A flash memory device structure, comprising:a first conductive type substrate having an opening therein; a second conductive type first well region formed within the first conductive type substrate; a tunnel dielectric layer formed on the sidewall and bottom section of the opening; a first floating gate and a second floating gate formed on the tunnel dielectric layer on each side of the opening; an inter-gate dielectric layer formed over the first floating gate and the second floating gate; a first control gate and a second control gate formed over the substrate, wherein the first control gate extends to cover the sidewall of the first floating gate and the second control gate extends to cover the sidewall of the second floating gate; an insulating layer formed in the space between the first control gate and the second control gate; a spacer formed on the sidewalls of the first control gate and the second control gate; a source region formed in the first conductive type substrate at the bottom section of the opening; a drain region formed in the first conductive type substrate underneath the spacer; a first conductive type second well region formed within the second conductive type first well region, wherein the junction between the first conductive type second well region and the second conductive type first well region is at a level higher than the bottom section of the opening; and a first conductive type pocket doping region formed within the first conductive type substrate on the sidewall of the opening, wherein the first conductive type pocket doping region connects the first conductive type second well region with the source region.