Patent ID: 6745219
Filing Date: 2004-06-01
Classification: G06F,G06N

Abstract:
An arithmetic unit having a first, second and third n-bit input operands, said arithmetic unit comprising:an n-bit pseudorandom number generator for generating M-sequences; a digital-to-analog converter connected to said pseudorandom number generator, said digital-to-analog converter receiving the M-sequences and providing a stochastic analog signal; an analog comparator connected to said digital-to-analog converter, said analog comparator receiving the stochastic analog signal and having a stochastic sequence output; a first and second logic unit connected to said pseudorandom number generator, said first and second logic units receiving the M-sequences from said pseudorandom number generator and respectively generating a first and second incompatible pseudorandom sequences; a data-to-sequence converter having inputs connected to the first n-bit input operand and to the said first logic unit, the data-to-sequence converter generating pseudorandom sequence of the first input operand using the pseudorandom sequence generated by the first logic units; a stochastic multiplier connected to the second and third n-bit input operands, said stochastic multiplier multiplying the second and third n-bit input operands to provide a multiplied operand output; and, a stochastic adder connected to said analog comparator, to said data-to-sequence converter and to said stochastic multiplier, said stochastic adder adding the stochastic sequence outputted by the analog comparator the pseudorandom sequence generated by the data-to-sequence converter and the multiplied operand output.