Patent ID: 6274433
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method for forming a floating gate in a non-volatile memory device, the method comprising:forming at least two isolating regions, separated by an isolated region, within a substrate, a tunnel oxide being formed on the substrate in the isolated region between the at least two isolating regions;forming a polysilicon layer on the tunnel oxide and the at least two isolating regions;selectively patterning the layer of polysilicon layer to form at least two adjacent floating gates, the at least two adjacent floating gates each having a respective end wall formed over one of the isolating regions and being spaced apart from each other about 2,600 .ANG.;forming a dielectric layer on the at least two adjacent floating gates and on the at least two isolating regions in a region where the respective end walls of the at least two adjacent floating gates are spaced apart;forming a control gate on at least a portion of the dielectric layer and at least partially located directly over at least a portion of each of the at least two adjacent floating gates, the control gate having a thickness of about 1,200 .ANG.; andforming a silicide on at least a portion of the control gate, whereinthe polysilicon layer is between approximately 100 and 700 .ANG. thick, substantially reducing cracking of the silicide.