Patent ID: 6562636
Filing Date: 2003-05-13
Classification: G01R,H05K

Abstract:
A method for burn-in testing integrated circuits in wafer form, which comprises:(a) providing a plurality of semiconductor wafers, each wafer including integrated circuits; (b) providing a plurality of cartridges, each cartridge comprising, a semiconductor wafer from among the plurality of semiconductor wafers, and a probe for contacting integrated circuits included by the semiconductor wafer; (c) providing a temperature controlled zone configured to receive the plurality of cartridges; (d) receiving the plurality of cartridges in the temperature controlled zone; (e) contacting the integrated circuits included by the semiconductor wafer with the probe; (f) in each cartridge, testing the contacting integrated circuits with test electronics positioned in a cool zone; (g) providing power to the integrated circuits with power electronics positioned in the cool zone; and (h) separating the test and power electronics from the temperature controlled zone with a transition zone between the temperature controlled zone and the cool zone.