Patent ID: 7797598
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. A method of evaluating a design under test, the method comprising: executing a testcase involving a device under test; wherein the testcase includes at least one variable; resolving a respective random value for the at least one variable of the testcase at runtime of the testcase; estimating, at runtime of the testcase, an amount of time needed to perform one or more transactions with the device under test, wherein the amount of time needed to perform the one or more transactions depends upon the respective random value resolved for the at least one variable; identifying whether a transaction task to be performed comprises overlapping transactions or in-sequence transactions, wherein the transaction task comprises the one or more transactions; setting a timer with the estimated amount of time needed to perform the one or more transactions; wherein setting the timer comprises: invoking the one or more transactions with the device under test; and indicating, responsive to expiration of the timer, whether the one or more transactions completed execution.