Patent ID: 6025226
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method for manufacturing an integrated circuit including a capacitor, comprising the steps of:(a) forming a first conductive interconnect and a second conductive interconnect upon a first interlevel dielectric;(b) depositing a second interlevel dielectric upon the first conductive interconnect, upon the second conductive interconnect, and upon the first interlevel dielectric;(c) forming a first opening corresponding to the first conductive interconnect, the first opening having sidewalls and a bottom and extending through the second interlevel dielectric to the first conductive interconnect, and a second opening corresponding to the second conductive interconnect, the second opening having sidewalls, a bottom, a second opening width, and a second opening depth and extending through the second interlevel dielectric to the second conductive interconnect;(d) depositing a third conductor in the second opening;(e) depositing an insulator upon the second interlevel dielectric, upon the sidewalls and bottom of the first opening, upon the sidewalls of the second opening, and upon the third conductor in the second opening;(f) forming a trench in the second interlevel dielectric through the insulator, the trench corresponding to the second opening wherein the insulator upon the third conductor in the second opening is simultaneously removed while forming the trench; and(g) depositing a first conductor upon the insulator and filling the first opening, the second opening, and the trench with the first conductor.