Patent ID: 6804808
Filing Date: 2004-10-12
Classification: G06F

Abstract:
A method for testing enclosure of vias by geometries of a design layout, said vias connecting geometries of a first layer to geometries of a second layer, said method comprising the steps of:representing geometries on the first layer by a w0 set of objects; for i=1, n: deriving a wide class wi object set; identifying Wi connection areas between the first layer and the second layer, each having at least one via located within a wi object of the first layer; performing a wi redundant via test on each identified w1 connection area, said, wi redundant via test performed relative to a base class wi object set containing the identified wi connection area, said base class w1 formed by extending virtual edges of wi objects inside of w0 objects; and marking vias that fail the wi redundant via test as a violation.