Patent ID: 7971042
Filing Date: 2011-06-28
Classification: G06F,G06T,H04N

Abstract:
1. A microprocessor architecture having decoupled fetch-execution cycles for at least two instruction pipelines, comprising: a main instruction pipeline operating at a first clock frequency; and an extended instruction pipeline, wherein the main instruction pipeline is configured to issue: wherein the single instruction or the begin record instruction causes the extended instruction pipeline to switch to an autonomous mode of operation from a main instruction pipeline controlled mode of operation, wherein operating in the autonomous mode of operation comprises fetching and executing instructions from the sequence of recorded instructions independent from the main instruction pipeline, through a front end portion of the extended instruction pipeline, the front end portion of the extended instruction pipeline operating at a second clock frequency that is different from the first clock frequency, thereby decoupling the fetch-execution cycles of the main instruction pipeline from the extended instruction pipeline.