Patent ID: 8300002
Filing Date: 2012-10-30
Classification: G09G,G11C

Abstract:
1. A gate driving circuit, the gate driving circuit receiving a plurality of sequential clock signals and comprising a plurality of cascaded drive units sequentially outputting an output signal, each of the cascaded drive units, comprising: a first switch, comprising a control terminal receiving a first clock signal, a first terminal receiving a first input signal, and a second terminal coupled to a node; a second switch, comprising a control terminal receiving a second clock signal, a first terminal coupled to the node, and a second terminal receiving a second input signal; and a third switch, comprising a control terminal coupled to the node, a first terminal receiving a third clock signal, and a second terminal outputting the output signal; wherein the first input signal and the second input signal are output signals of cascaded drive units adjacent to an nth cascaded drive unit, and the first clock signal, the third clock signal and the second clock signal are three successive clock signals following a sequence of first, third and second clock signals; wherein a first-stage cascaded drive unit of the gate driving circuit receives a scan start signal and a last-stage cascaded drive unit of the gate driving circuit receives a scan end signal, or the first-stage cascaded drive unit receives the scan end signal and the last-stage cascaded drive unit receives the scan start signal; wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal.