Patent ID: 6426984
Filing Date: 2002-07-30
Classification: G06F,H03L,H04L

Abstract:
A digital system, comprising:a clock generator to generate a first clock signal; a clock driver to drive a second clock signal; a master device; a plurality of slave devices; a transmission channel with a clock-to-master path extending from said clock generator, through said plurality of slave devices, to said master device, and a clock-from-master path extending from said clock driver through said master device, through said plurality of slave devices to a last slave device of said plurality of slave devices, said transmission channel including a slave-to-master path positioned between a first slave device of said plurality of slave devices and said master device and a master-to-slave path positioned between said master device and said first slave device, the cumulative length of said slave-to-master path and said master-to-slave path creating a master routing phase shift between said first clock signal on said clock-to-master path and said second clock signal on said clock-from-master path; a first lead to sample said first clock signal on said slave-to-master path; a second lead to sample said second clock signal on said master-to-slave path; and a clock latency adjustment circuit connected to said first lead and said second lead to produce an adjusted clock signal on said master-to-slave path to compensate for said master routing phase shift.