Patent ID: 8250347
Filing Date: 2012-08-21
Classification: G06F

Abstract:
1. A digital data processing device, comprising: a processor for executing threads including threads of a special class and threads not belonging to said special class, said processor containing a plurality of register sets for supporting the maintenance of thread state and concurrent execution of a plurality of threads, each register set of said plurality of register sets corresponding to a respective thread; a memory for storing instructions executable by said processor; a cache having a plurality of cache lines for temporarily storing selective contents of said memory for use by threads executing on said processor, each cache line of said plurality of cache lines for temporarily storing respective selective contents of said memory on behalf of a respective thread executing on said processor; and a limiting mechanism which constrains the selection of a cache line of said cache into which to load data on behalf of a thread of said special class executing on said processor, the selection being constrained to select a cache line of said cache which will not cause the eviction, from said cache, of valid data originally stored in a cache line of said cache on behalf of a thread not belonging to said special class, and to prevent a thread of said special class from filling more than a predetermined limit of the cache lines of said cache with data stored on behalf of said threads of said special class, said predetermined limit being fewer than all of the cache lines of said cache.