Patent ID: 8933731
Filing Date: 2015-01-13
Classification: G06F

Abstract:
1. A multiplier circuit for multiplying a multiplier and a multiplicand, comprising: a multiplexer having an input terminal for receiving the multiplier, wherein the multiplier includes first and second partial multipliers, a select input terminal for receiving a select signal, and an output terminal for providing at least one of the first and second partial multipliers based on the select signal; an encoder connected to the output terminal of the multiplexer for receiving the at least one of the first and second partial multipliers, setting a most significant bit (MSB) of the at least one of the first and second partial multipliers to binary one, detecting a least significant set bit (LSB) in the at least one of the first and second partial multipliers, generating a position difference value that includes a difference between positions of first and second LSBs detected in current and previous multiplication cycles, respectively, and generating a result acknowledgement signal when the multiplication of the multiplier and the multiplicand is finished; a shifter circuit connected to the encoder for receiving the position difference value and a first intermediate product, and generating a second intermediate product by right-shifting the first intermediate product by a count equal to the position difference value, wherein the second intermediate product includes a second MSB intermediate product and a second LSB intermediate product; and an accumulator connected to the shifter circuit for receiving the second MSB intermediate product and the multiplicand, adding the multiplicand to the second MSB intermediate product to generate a first MSB intermediate product, appending the first MSB intermediate product to the second LSB intermediate product to generate a third intermediate product, and transmitting the third intermediate product to the shifter circuit, wherein the accumulator generates the first intermediate product in the previous multiplication cycle, wherein a final product of the multiplier and the multiplicand is generated subsequent to the encoder detecting each set bit in the at least one of the first and second partial multipliers.