Patent ID: 7759234
Filing Date: 2010-07-20
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming a sacrificial layer having a stack structure of a first insulation layer, a first conductive layer and a second insulation layer over a substrate; forming a recess by etching the sacrificial layers and the substrate; forming a gate insulation layer over a surface of the recess; filling a second conductive layer in the recess and a region between etched sacrificial layers; forming a gate electrode metal layer and a gate mask pattern over a resultant substrate filled with the second conductive layer; etching layers formed below the gate mask pattern by using the gate mask pattern until the first conductive layer is exposed, thereby forming an initial gate pattern; forming a capping layer on a sidewall and a top portion of the initial gate pattern; and etching an exposed portion by using the capping layer as a mask until the first insulation layer is exposed, thereby forming a final gate pattern.