Patent ID: 6847089
Filing Date: 2005-01-25
Classification: H01L

Abstract:
1. An integrated circuit comprising: a semiconductor substrate; a gate coupled to said semiconductor substrate; a source region within said semiconductor substrate, said source region electrically coupled to said gate; a drain region within said semiconductor substrate, said drain region electrically coupled to said gate; a source extension region within said semiconductor substrate, said source extension region coupled to said source region; a drain extension region within said semiconductor substrate, said drain extension region coupled to said drain region; a channel region within said semiconductor substrate, said channel region coupled to said gate, said source extension region, and said drain extension region; halo atoms within said channel region, said halo atoms being more concentrated at a gate side of said channel region, and said halo atoms being less concentrated at a source extension region side and a drain extension region side of said channel region; and impurity atoms within said integrated circuit.