Patent ID: 6314033
Filing Date: 2001-11-06
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of input/output data lines;a plurality of data bus lines;at least one redundancy data bus line;a plurality of shift switches for switching connections of the plurality of input/output data lines and a first group of the plurality of data bus lines to connections of the plurality of input/output data lines and a second group of the data bus lines, which exclude at least one defective data bus line, and the at least one redundancy data bus line in response to a plurality of changeover signals; anda changeover signal generating circuit, connected to the plurality of shift switches, for generating the plurality of changeover signals including a first group of changeover signals and a second group of changeover signals in response to a redundancy address signal, the changeover signal generating circuit having a plurality of signal generating blocks including a first signal generating block for generating the first group of changeover signals and a second signal generating block for generating the second group of changeover signals.