Patent ID: 6425080
Filing Date: 2002-07-23
Classification: H04L,H04Q

Abstract:
An asynchronous transfer mode (ATM) cell descrambling circuit for detecting a header portion and a payload portion of each cell of a scrambled ATM cell sequence in the state that each cell pre- or fully-synchronizes, descrambling the payload portion, and outputting a descrambled ATM cell sequence, the circuit comprising:means for determining whether each ATM cell comprises an unnecessary ATM cell that is not used in a higher layer of an ATM communication so as to stop a cell descrambling operation for a predetermined period, wherein said unnecessary cell comprises one of an idle cell and an unassigned cell, wherein said descrambling operation is performed for a payload portion of each necessary ATM cell and a last portion of a payload portion of each said unnecessary ATM cell, and wherein said determining means generates input data for said cell descrambling operation and generates a signal for stopping said cell descrambling operation, said input data and said signal both having a same delay period.