Patent ID: 6147916
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory cells;a plurality of bit line pairs connected to the memory cells, wherein each bit line pair includes a first bit line and a second bit line;a precharge circuit connected to the bit line pairs to selectively provide the bit line pairs with a reference power supply voltage, wherein the precharge circuit stops providing the bit line pairs with the reference power supply voltage when the memory cells are accessed to transmit a data signal to one of the memory cells via a corresponding one of the bit line pairs, and provides the bit line pairs with the reference power supply voltage as a precharge voltage when the memory cells are not being accessed, the precharge circuit providing the precharge voltage in response to one of first and second precharge control signals, the first precharge control signal being in sync with a semiconductor memory operation cycle, and the second precharge control signal being independent from the semiconductor memory operation cycle; anda correction circuit for adjusting the precharge voltage in accordance with a difference between the precharge voltage of the bit line pairs and the reference power supply voltage so that the precharge voltage of the bit line pairs becomes substantially equal to the reference power supply voltage.