Patent ID: 6107659
Filing Date: 2000-08-22
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device being formed on a semiconductor substrate, comprising:a memory cell array including a plurality of memory cells being arranged in rows and columns;a plurality of bit lines being provided in correspondence to said columns of said memory cells respectively;a plurality of word lines being provided in correspondence to said rows of said memory cells respectively; anda plurality of first cell selector lines being provided in correspondence to said rows of said memory cells,each said memory cell including a memory cell transistor having:a second conductivity type source region and a drain region of said second conductivity type being formed on a first conductivity type major surface of said semiconductor substrate,a channel region being held between said source region and said drain region,a charge storage electrode being formed on said channel region with an oxide film therebetween, anda control electrode being formed above said charge storage electrode with an insulating film therebetween,said drain region being coupled with corresponding said bit line,the potential of said control electrode being controlled by corresponding said word line,said nonvolatile semiconductor memory device further comprising:memory cell selector means for selecting corresponding said word line and providing a potential difference between selected said bit line and selected said first cell selector line in response to an external address signal in a read operation of said nonvolatile semiconductor memory device;a plurality of bipolar transistors each being provided between said source region of corresponding said memory cell transistor and corresponding said first cell selector line and so coupled as to amplify a current flowing between said source region and said drain region of selected said memory cell transistor as a base current for controlling the quantity of a current flowing through said selected first cell selector line; anddata read means for reading data being held in selected said memory cell in response to the value of said current flowing through said selected first cell selector line; wherein:said memory cell selector means includes write means for injecting/extracting electrons into/from said charge storage electrodes of said memory cell transistors to write data into said memory cell transistors in a write operation, andsaid write means hasrow selector means for keeping the potential level of the selected word line higher than that of the semiconductor substrate according to an address signal during the write operation, andcolumn selector means for keeping the potential level of the selected bit line lower than that of the semiconductor substrate according to said address signal during the write operation.