Patent ID: 7978512
Filing Date: 2011-07-12
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor memory system comprising: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data, the memory cells that share one of word lines and can be written or read at a time being configured to store multiple pages of data therein, a total amount of data stored in the multiple pages being set to a power-of-two number of bits, and the redundant data being stored in a residual portion of the multiple pages.