Patent ID: 6559694
Filing Date: 2003-05-06
Classification: G11C,H03L

Abstract:
A timing signal occurrence circuit, comprising:a plurality of signal output circuits configured to output a timing signal; a plurality of selecting circuits configured to select whether or not to operate the corresponding signal output circuit; and a plurality of delay elements connected in series, a calculator configured to fetch operands on an operand bus and to carry out the fetched operands, in sync with a delay clock on a delay clock line; a clock delay adjustment circuit configured to adjust delay of the delay clock on said delay clock line, and an operand delay adjustment circuit configured to adjust delay of the operands on said operand bus, wherein the respective outputs of said plurality of signal output circuits are connected to input terminals different from each other of said plurality of delay elements, said plurality of selecting circuits operates at least one of said signal output circuits, said clock delay adjustment circuit is provided with said signal output circuit configured to output said delay clock with timing different from each other, said operand delay adjustment circuit is provided with said signal output circuits configured to output the operands with timing different from each other, and each of said clock delay adjustment circuit and said operand control circuit selects either of said signal output circuit, so that said calculator fetches the operands after the operand on said operand bus is settled.