Patent ID: 8036260
Filing Date: 2011-10-11
Classification: H04L

Abstract:
1. An equalizer, comprising: a feedback combiner configured to combine an input signal and a single feedback signal to produce a first interim signal; a delay line configured to delay the first interim signal to produce a second interim signal; a feed-forward combiner configured to combine the second interim signal and a single feed-forward signal to produce an output signal; an interim decision circuit configured to extract a value of a sign bit from the first interim signal, the sign bit having one of a first or a second value; first through N first through M wherein a 0 wherein an (M+1) wherein M is an integer greater than one, wherein N is an integer greater than one, wherein i is an index value that ranges from 1 to N, wherein j is an index value that ranges from 1 to M, wherein the single feedback signal is equal to the N wherein the single feed-forward signal is equal to the first feed-forward sum value.