Patent ID: 6412030
Filing Date: 2002-06-25
Classification: G06F

Abstract:
A peripheral component interconnect (PCI) read/write optimizing circuit comprising:a first address register adapted to store a target address; a write address register coupled to said first address register, said write address register adapted to store said target address during inhibited write transactions; a multiplexer coupled to said first address register and said write address register, said multiplexer adapted to select whether a target address in said first address register or said write address register is forwarded; a second address register coupled to said multiplexer, said second address register adapted to store said target address forwarded by said multiplexer, and said second address register stores a pending read transaction target address associated with a pending read transaction and said write address register stores an inhibited write transaction target address associated with an inhibited write transaction if said inhibited write transaction target address is not within a range of said pending read transaction target address; and a PCI target control component coupled to said multiplexer, said PCI target control component adapted to direct communication operations in accordance with PCI protocols and control loading of said target address in said second address register via said multiplexer.