Patent ID: 8026537
Filing Date: 2011-09-27
Classification: G06F,H01L

Abstract:
1. A semiconductor integrated circuit comprising: a function block arranged on a substrate; a plurality of buffering cells arranged regularly in the function block at an appointed interval, the plurality of buffering cells including a first buffering cell type and a second buffering cell type fabricated via an insulated gate field effect transistor (IGFET) fabrication process, wherein, by changing gate width of transistors as between the first buffering cell type and the second buffering cell type during the IGFET fabrication process, a second drive ability of the second buffering cell type is set higher than a first drive ability of the first buffering cell type; and a signal wiring extending obliquely relative to a side of the function block, the signal wiring being connected between adjacent buffering cells selected from among the plurality of buffering cells with the signal wiring being driven to a subsequent cell by either a first buffering cell or a second buffering cell, wherein the signal wiring is arranged substantially in an entire area on the substrate and passes over the function block; wherein use of either the first buffering cell or the second buffering cell to drive the signal wiring is determined as a function of distance to the subsequent cell, with the first buffering cell type being used to drive the signal wiring over a distance correlated to nearby cells and the second buffering cell type being used to drive the signal wiring to cells at distances further away than the distance to the nearby cells.