Patent ID: 6732252
Filing Date: 2004-05-04
Classification: G06F,H04N

Abstract:
A memory address generation device for generating a plurality of addresses for accessing a memory, the memory address generation device comprising:an address update section for updating N addresses (where N is a natural number) at a predetermined timing based on a predetermined relationship among the N addresses, wherein the address update circuit comprises: a control signal generation circuit for receiving (i) a pointer identification signal corresponding to one of a plurality of address pointers, and (ii) an address generation timing signal, a first selector for receiving an address register selection signal generated by the control signal generation circuit and selecting and outputting one of the N addresses corresponding to the one of the plurality of address pointers signal, an address register for receiving the selected address and storing the selected address as a reference address and outputting the address to the memory, and an arithmetic unit for receiving the selected address from the selector and adding an increment so as to allow subsequent addresses to be sequentially allocated based on the reference address, thereby updating the address register, wherein: the predetermined relationship among the N addresses is a relationship between at least one reference address and the other addresses of the N addresses, the predetermined relationship among the N addresses is represented by K predetermined values (where K is a natural number); and wherein the address update section further comprises a second selector for selecting one of the K predetermined values corresponding to one of the N addresses, the arithmetic unit updates the address of the address register corresponding to the one of the K predetermined values.