Patent ID: 6225188
Filing Date: 2001-05-01
Classification: H01L

Abstract:
A semiconductor fabrication process comprising:providing a semiconductor substrate;forming a patterned isolation masking layer on an upper surface of said semiconductor substrate, wherein said isolation masking layer exposes at least one isolation region of said semiconductor substrate;forming an isolation structure in said isolation region, wherein an upper surface of said isolation structure is substantially coplanar with or below said upper surface of said semiconductor substrate;with said isolation masking layer in place, introducing an oxygen bearing species into an upper portion of said semiconductor substrate proximal to said isolation dielectric; andafter removing said isolation masking layer, forming a gate dielectric by thermally oxidizing said upper surface of said semiconductor substrate, wherein an oxidation rate of said semiconductor substrate proximal to said isolation structure is greater than an oxidation rate of said semiconductor substrate distal from said isolation region, whereby a thickness of said gate dielectric proximal to said isolation structure is greater than a thickness of said gate dielectric distal from said isolation structure after said forming a gate dielectric.