Patent ID: 6272049
Filing Date: 2001-08-07
Classification: G11C

Abstract:
An electrically erasable and programmable non-volatile semiconductor memory device comprising:first, second and third memory cells, each of which has a control gate, a floating gate, a drain and a source, and is set either to an erase state having a low threshold voltage or to a program state where more electrons than in said erase state are stored in the floating gate for attaining a threshold voltage higher than the threshold voltage attained in said erase state, the threshold voltage attained in said program state being lower than a maximum read voltage applied between the control gate and the source;a first bit line connected to the drain of said first memory cell;a second bit line connected to the drain of said second memory cell;a third bit line connected to the drain of said third memory cell;means for setting one of said second and third memory cells to said erase state and the other to said program state;means for connecting said second bit line to said third bit line in a given read cycle;means for setting said first, second and third bit lines to a predetermined precharge potential at an initial stage of said read cycle; andsensing means for sensing a state of said first memory cell in said read cycle by comparing a potential of said first bit line that is lowered from said precharge potential by a drain current drained from said first bit line by said first memory cell with a potential of said second and third bit lines, connected to each other, that is lowered from said precharge potential by a drain current drained from said second and third bit lines by said second and third memory cells.