Patent ID: 6365938
Filing Date: 2002-04-02
Classification: H01L

Abstract:
An integrated circuit comprising:an integrated circuit substrate including therein a first well of first conductivity type and a second well of second conductivity type at a face thereof; spaced apart source and drain regions in the first well, at the face; an insulated gate electrode on the face between the spaced apart source and drain regions; a first region of second conductivity type in the first well, the first region and the first well defining a first junction diode; a second region of first conductivity type in the second well, the second region and the second well defining a second junction diode; an interlayer insulating layer on the first and second wells and on the insulated gate electrode; first, second and third conductive plugs that extend through the interlayer insulating layer to electrically contact the insulated gate electrode, the first region and the second region, respectively; and a metallization line on the interlayer insulating layer and electrically connecting the first, second and third conductive plugs, the metallization line between the second and third conductive plugs including a narrow portion relative to the metallization line between the first and second conductive plugs; wherein the first and second wells are adjacent one another to define a boundary therebetween and wherein the narrow portion extends across the boundary.