Patent ID: 7923365
Filing Date: 2011-04-12
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, comprising: forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions, on a semiconductor substrate; depositing a mask layer to expose at least a portion of the sacrificial spacer on the semiconductor substrate; removing the sacrificial spacer by selectively dry etching the exposed sacrificial spacer using the mask layer as an etching mask, said dry etching performed using an etching gas having higher etch rate for the sacrificial spacer relative to the mask layer; and forming a stress-inducing electrically insulating layer that is configured to induce a net tensile or compressive stress in a channel region of the field effect transistor, on the sidewall of the gate electrode.