Patent ID: 6228714
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method for manufacturing a nonvolatile memory device having a cell array and a peripheral circuit region, the cell array region including a cell array having a plurality of cell transistors and the peripheral circuit region including a resistor region having at least one resistor and a MOS transistor region having a MOS transistors for driving the cell transistors, the method comprising:forming a first conductive layer on a semiconductor substrate;forming a first conductive layer pattern and an isolated resistor pattern in the resistor region by patterning the first conductive layer;sequentially forming a dielectric layer and a second conductive layer on the substrate;forming a second conductive layer pattern exposing a portion of the dielectric layer in the MOS transistor region and the entire are of the dielectric layer in the resistor region by patterning the second conductive layer; andforming a gate pattern of each cell transistor and a gate pattern of the MOS transistor in the cell array region and in the MOS transistor region, respectively, by sequentially patterning the second conductive layer pattern, the dielectric layer, and the first conductive layer pattern;wherein the gate pattern of the each cell transistor includes a sequentially stacked floating gate, dielectric layer, and control gate; andwherein the gate pattern of the MOS transistor includes a sequentially stacked gate electrode, dielectric layer, and dummy gate electrode, the dummy gate electrode including the exposed region of the dielectric layer of the MOS transistor region.