Patent ID: 8467217
Filing Date: 2013-06-18
Classification: G11C

Abstract:
1. A semiconductor device comprising: first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first amplifier connected to the first bit line; a second amplifier connected to the second bit line; a local input/output line; a first transistor coupled to the first amplifier at a first electrode thereof and the local input/output line at a second electrode thereof; a second transistor coupled to the second amplifier at a third electrode thereof and the local input/output line at a fourth electrode thereof; a first column selection line; a third transistor coupled between the first column selection line and a gate electrode of the first transistor, the third transistor connecting, when rendered conductive in response to a first selection signal, the first column selection line with the gate electrode of the first transistor; and a fourth transistor coupled between the first column selection line and a gate electrode of the second transistor, the fourth transistor connecting, when rendered conductive in response to a second selection signal, the first column selection line with the gate electrode of the second transistor.