Patent ID: 6321186
Filing Date: 2001-11-20
Classification: G06F

Abstract:
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for verifying a design of an integrated circuit, the integrated circuit having a set of functional constraints, the method comprising:generating a logic data structure based on the set of functional constraints, the logic data structure comprising a plurality of nodes, each of the plurality of nodes having at least one branch, wherein each of the plurality of nodes represents an input signal used in the integrated circuit, wherein each input signal has an associated weight;assigning a node weight to each of the plurality of nodes based on the associated weight;assigning a branching probability to each branch of each of the plurality of nodes based on the logic data structure and the associated weight;generating a first set of simulation inputs based on the logic data structure and branching probabilities;generating a simulation control program using the first set of simulation inputs to control simulation of the design of the integrated circuit;initializing simulation of the design of the integrated circuit;simulating the design of the integrated circuit;determining at least one state condition of the design of the integrated circuit; andadjusting branching probabilities in response to the at least one state condition.