Patent ID: 6990642
Filing Date: 2006-01-24
Classification: G01R,G06F

Abstract:
1. A design method for an integrated circuit having a logic circuit, comprising: a first step of converting a first netlist, which has connection data for a logic circuit in which a plurality of standard cells including at least a first flip flop are connected, into a second netlist by converting the first flip flops into second flip flops equipped with a scan function and adding scan chain interconnects that connect the second flip flops; a second step of generating a third netlist by substituting the second flip flops in the second netlist for a plurality of standard cells that constitute the second flip flops, and generating scan-chain interconnect data; a third step of performing layout of the standard cells and interconnects thereof which are contained in the third netlist, in accordance with the third netlist, optimizing an order of the scan chain interconnects on the basis of the scan chain interconnect data, and generating scan-chain interconnect order data; a fourth step of generating a fifth netlist, from a fourth netlist that includes the second flip flops, and scan chain interconnects that depend on the scan-chain interconnect order data, by substituting the second flip flops for a plurality of standard cells, and of performing layout of the standard cells and interconnects thereof which are contained in the fifth netlist, in accordance with the fifth netlist; and a step of generating logic circuit test patterns on the basis of the fourth netlist, wherein: the standard cells are registered in a layout library as hard macros that contain layout information, and the layout of the standard cells is performed in the fourth step with reference to the layout library, and the second flip flop having the scan function is not registered in the layout library as a hard macro that contains layout information.