Patent ID: 7858458
Filing Date: 2010-12-28
Classification: H01L

Abstract:
1. A process for forming a memory device, the process comprising: patterning gates in nMOS and pMOS regions for CMOS circuits; forming first disposable spacers surrounding the gates in the nMOS regions and second disposable spacers surrounding the gates in the pMOS regions, wherein the first disposable spacers are smaller than the second disposable spacers; masking the pMOS regions with a first mask; conducting source/drain doping with the first disposable spacers surrounding the gates in the nMOS regions; removing the first disposable spacers and subsequently conducting supplemental doping between source/drain regions and the gates in the nMOS regions while the pMOS regions remain masked with the first mask; masking the nMOS regions with a second mask; conducting source/drain doping with the second disposable spacers surrounding the gates in the pMOS regions; and removing the second disposable spacers and subsequently conducting supplemental doping between source drain regions and the gates in the pMOS regions while the nMOS regions remain masked with the second mask; wherein the gates have a thickness greater than or equal to a source/drain junction depth.