Patent ID: 7489169
Filing Date: 2009-02-10
Classification: G11C,H03L

Abstract:
1. A delay lock loop comprising: a fine delay control configured to receive a shift command; a fine delay block configured to receive an input signal and to produce a shifted input signal and configured to receive an enable signal from the fine delay control, wherein the fine delay block comprises a plurality of fine delay units, wherein each of the plurality of fine delay units is configured to shift the input signal by a first time delay; and a coarse delay block configured to receive the shifted input signal from the fine delay block and further configured to be controlled by the fine delay control when the delay lock loop is in a fine tuning mode of operation, wherein the coarse delay block comprises a plurality of coarse delay units, wherein each of the plurality of coarse delay units is configured to shift a signal by a second time delay, wherein the second time delay is greater than the first time delay, wherein the fine delay control is configured to reset each of the fine delay block and the coarse delay block when the shifted input signal is shifted by the first time delay.