Patent ID: 6303965
Filing Date: 2001-10-16
Classification: H01L,Y10S

Abstract:
An SRAM comprising:a semiconductive material substrate;a node location having a potential of Vcc;a pulldown transistor supported by the semiconductive substrate and comprising:a transistor gate structure which includes a gate oxide layer, polysilicon layer, silicide layer and insulative cap; anda pair of source/drain regions adjacent the transistor gate structure;an insulative material over the substrate and transistor gate structure, and having a pair of openings extending therethrough to the source/drain regions, the insulative material having an upper surface over the transistor gate structure;a resistor extending into one of the openings in the insulative material, and comprising:a first conductive layer in electrical connection with one of the source/drain regions of the pulldown transistor;a dielectric material over the first conductive layer and having a thickness of no greater than about 60 Angstroms;a second conductive layer over the dielectric material and in electrical connection with the node location; andwherein the first conductive layer, dielectric material, and second conductive layer only partially fill said one of the openings in the insulative material, and further wherein the first conductive layer, dielectric material and second conductive layer extend out of said one of the openings and over the upper surface of the insulative material; andthe pull-down transistor being electrically connected to the node location having the potential of Vcc through the resistor.