Patent ID: 6790724
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method of fabrication of a 1T DRAM used in a system which simulates the behavior of a Static Random Access Memory, comprising the steps of:a) forming a word line structure and a capacitor plate structure on a substrate; (1) said capacitor plate structure comprised of a capacitor dielectric on said substrate and a conductive plate layer on said capacitor dielectric; said capacitor plate structure overlying a plate region of said substrate; said plate region and said conductive plate layer acting as plates of a capacitor; b) implanting ions of a first conductivity type into said substrate forming a cell node region in said substrate between said word line structure and said capacitor plate structure, and forming a first bit line region in said substrate adjacent to said word line structure; c) forming dielectric spacers on the sidewalls of said word line structure and said capacitor plate structure; d) forming a mask pattern over said cell node region; e) implanting ions of a first conductivity type into said substrate to form a second bitline region; and not implanting ions into said cell node region; f) removing the mask pattern; g) forming a dielectric layer over said substrate; and h) forming a bitline contact to said second bitline region.