Patent ID: 6154077
Filing Date: 2000-11-28
Classification: H03K

Abstract:
Bistable flip-flop with a first inverter stage (1) driven by an input signal (D) and capable of being switched into a disabling state by a clock signal (CLK), with a second inverter stage (2) which is driven by the clock signal (CLK) and which can be switched into a disabling state by an output signal (INV1) of the first inverter stage (1), and with a third inverter stage (3) which is driven by an output signal (INV2) of the second inverter stage (2) and which can be switched into a disabling state by the clock signal (CLK), wherein the third inverter stage (3) can be switched into a non-disabling state by a first set signal (SET) and the second inverter stage (2) can be switched into the disabled state by a second set signal (SETN) at a specific signal level of the clock signal (CLK).