Patent ID: 7208785
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A self-aligned Schottky-barrier clamped planar DMOS transistor structure, comprising: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a lightly-doped epitaxial semiconductor layer being formed on a heavily-doped semiconductor substrate; a self-aligned source region being defined to be surrounded by a planar gate region, wherein the self-aligned source region comprises a moderately-doped base diffusion ring of a second conductivity type being formed in the lightly-doped epitaxial semiconductor layer through an implantation window, a heavily-doped source diffusion ring of the first conductivity type being formed in a surface portion of the moderately-doped base diffusion ring through the implantation window, and a self-aligned source contact window being formed on a semiconductor surface of the lightly-doped epitaxial semiconductor layer surrounded by the moderately-doped base diffusion ring, the moderately-doped base diffusion ring surrounded by the heavily-doped source diffusion ring, and the heavily-doped source diffusion ring surrounded by a sidewall dielectric spacer being formed over a sidewall of a protection dielectric layer and on a side surface portion of the protection dielectric layer; the planar gate region being formed on a gate dielectric layer outside of the self-aligned source region, wherein the planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on the gate dielectric layer and a patterned capping dielectric layer being formed on the patterned heavily-doped polycrystalline-silicon gate layer; and a source metal layer at least formed over the self-aligned source contact window.