Patent ID: 7346716
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. In a controller of a computing device, the computing device comprising a system memory and a codec, a method being implemented by the controller comprising: receiving a buffer descriptor list from a buffer descriptor list controller, the buffer descriptor list defining a plurality of buffer segments of a buffer to be read, reading data from the buffer of the system memory via a first interface of the controller based, at least in part, on the buffer descriptor list, transferring the data to the codec via a second interface of the controller, tracking a position in the buffer from which the controller has read the data, and writing a value to a direct memory access position-in-buffer (DPIB) structure located in the system memory via the first interface to indicate the position in the buffer, wherein the first interface is an isochronous interface that supports relaxed ordering rules.