Patent ID: 8952721
Filing Date: 2015-02-10
Classification: G11C,H03K

Abstract:
1. A semiconductor device, comprising: a first logic section and a second logic section each including a plurality of storage sections, each storage section including (i) an address decoder which decodes a memory operation address inputted from a first address line or a logic operation address inputted from a second address line and outputs a word selection signal to a word line, and (ii) a plurality of storage elements being connected to the word line and a data line, which store data configuring a truth table defining a logic operation or connection relation, and are connected to the data line inputting and outputting the data by the word selection signal inputted from the word line; and an arithmetic processing section which includes (i) a first input/output section connecting the first address line of the storage sections included in the first logic section and the data line, (ii) a second input/output section connecting the second address line of the storage sections included in the second logic section, and (iii) a control section which performs control to output the memory operation address and data to the first input/output section and performs control to output the logic operation address and receive the data to and from the second input/output section.