Patent ID: 8184501
Filing Date: 2012-05-22
Classification: G11C

Abstract:
1. A local clock buffer for memory cell accesses comprising: a first set of components that form a first signal path and a second set of components that form a second signal path; an external clock input configured to receive an external clock signal and to provide the external clock signal to the first and second signal paths; and an internal clock output configured to receive signals from the first and second signal paths and to provide an internal clock signal to components of a memory cell macro; wherein the first signal path includes one or more faster-than-nominal components; wherein the local clock buffer generates a clock cycle of the internal clock signal which has a first half-period that is greater than a corresponding first half-period of a clock cycle of the external clock signal; and wherein the first signal path generates an initial edge of the clock cycle of the internal clock signal and the second signal path generates a final edge of the clock cycle of the internal clock signal.