Patent ID: 6812149
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method forming junction isolation to isolate active elements, comprising the steps of:providing a semiconductor substrate having a plurality of active areas and at least one isolation area between any two active areas; forming a first gate structure on part of the substrate located in the active areas and a second gate structure on the substrate located in the isolation area; forming a first doped region in the substrate located at two sides of the first gate structure and two sides of the second gate structure; forming a bottom anti-reflection layer on the substrate, the first gate structure and the second gate structure; anisotropic etching back part of the bottom anti-reflection layer to expose the second gate structure; removing the second gate structure to expose the surface of the substrate; forming a second doped region in the substrate located in the isolation area, wherein a type of dopant in the first doped region is opposite to that in the second doped region; and removing the bottom anti-reflection layer.