Patent ID: 6972484
Filing Date: 2005-12-06
Classification: H01L

Abstract:
1. A semiconductor device having an additional conductor network on the chip surface, wherein the power distribution of the integrated circuit is combined with the power distribution of the leadframe, comprising: a semiconductor chip having first and second surfaces; an integrated circuit fabricated on said first chip surface, said circuit having active components, contact pads, at least one metal layer, and a mechanically strong, electrically insulating overcoat having a plurality of metal-filled vias to contact said at least one metal layer; electrically conductive substantially coplanar, laterally disposed films deposited on said overcoat and patterned into a network of lines substantially vertically over said active components, said films in contact with said vias and having an electrically conductive seed metal layer attached to said electrically insulating overcoat and said metal-filled vias, at least one stress-absorbing film over said seed metal layer of sufficient thickness to reliably absorb mechanical, thermal and inpact stresses and an outermost non-corrodible and metallurgically attachable electrically conductive layer; said network patterned to distribute power current and ground potential; a leadframe having a chip mount pad, a first plurality of segments providing electrical signals, and a second plurality of segments providing electrical power and ground; said second chip surface attached to said chip mount pad; electrical conductors connecting said contact pads with said first plurality of segments; and electrical conductors connecting said network lines with said second plurality of segments.