Patent ID: 7236409
Filing Date: 2007-06-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell unit including at least one semiconductor memory cell; a voltage generating circuit which produces an operating voltage to which reference is made in performing a predetermined operation on the memory cell unit; and a constant-current circuit capable of a current trimming operation and adapted to supply a constant current to the voltage generating circuit, wherein the constant-current circuit comprises: a current source generating circuit unit which includes a first variable resistor whose resistance is varied in response to bits being switched; a first p-channel metal oxide semiconductor (MOS) transistor connected in series to the first variable resistor; and a first operational amplifier adapted to control the gate voltage of the first p-channel MOS transistor; wherein the constant-current circuit further comprises: a current conversion circuit unit which includes a second p-channel MOS transistor connected to the first p-channel MOS transistor in a current mirror configuration, and adapted to mirror the output of the first operational amplifier, and a first n-channel MOS transistor adapted for diode operation and connected in series to the second p-channel MOS transistor; and a current measurement circuit unit which includes the first n-channel MOS transistor, a second n-channel MOS transistor connected to the first n-channel MOS transistor in a current mirror configuration, and an external pad to control a current flowing through the second n-channel MOS transistor from the outside of the chip, wherein the current trimming operation is to change the resistance of the first variable resistor so that, when a desired voltage is applied to the external pad, the current flowing through the second n-channel MOS transistor may have a value to be set by the desired voltage.