Patent ID: 6397300
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A method of storing data in a memory hierarchy of a computer system, said memory hierarchy including a lower latency upper level cache and a higher latency lower level cache, said method comprising:in response to receipt at the memory hierarchy of a store operation from a processor of the computer system, said store operation including data and a target address, passing the store operation to the lower level cache and storing said data in the lower level cache; determining at said memory hierarchy whether or not said upper level cache is busy; in response to a determination that said upper level cache is not busy, allocating a cache line in the upper level cache to receive the data from the store operation if the store operation misses the upper level cache and writing the data into the upper level cache, such that said data is cached in both said upper and lower level caches; and in response to a determination that said upper level cache is busy, refraining from writing said data into said upper level cache and, in response to said store operation hitting in said upper level cache, invalidating a cache line in said upper level cache associated with said target address, such that said data is cached in said lower level cache but not said upper level cache.