Patent ID: 8423834
Filing Date: 2013-04-16
Classification: G06F

Abstract:
1. A computer system, comprising: a CPU; a memory circuit storing at least instruction codes; an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from the CPU; a code storing circuit storing data, which makes the CPU execute an exception handling, to be outputted to the CPU instead of data from the memory when an error occurs; a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, selectively outputting an instruction code read from the memory circuit when an error is not detected by the error checking circuit, and selectively outputting data from the code storing circuit to execute the exception handling when an error is detected by the error checking circuit; a bus connecting the selection circuit to the CPU; and an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit, and wherein the CPU is configured to output a signal indicating that an instruction is not executed when the instruction fetched through the bus is not executed, to execute the exception handling when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is not output and not to decode the instruction in a decode cycle based on the signal when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is output, and the instruction error register is set to a state of storing a value indicating that an error does not occur in response to the signal indicating that the instruction is not executed.