Patent ID: 8510493
Filing Date: 2013-08-13
Classification: G06F

Abstract:
1. A controller, comprising: a command and control processing subsystem; a bus interface, the bus interface configured for being communicatively coupled with the command and control processing subsystem; an array interface, the array interface configured for being communicatively coupled with the command and control processing subsystem; and a memory controller interface, the memory controller interface configured for being communicatively coupled with the command and control processing subsystem, wherein the command and control processing subsystem includes: a Write Address Control (WAC) partition, a Read Address Control (RAC) partition, a Write Data Flow (WDF) partition, and a Read Data Flow (RDF) partition, the RAC partition is configured for generating read requests for the memory controller interface and for providing said generated read requests to the memory controller interface, the WAC partition is configured for generating write requests for the memory controller interface and for providing said generated write requests to the memory controller interface, the WAC partition is configured for receiving: write requests from the bus interface, cache maintenance operations from a Device Control Register (DCR) partition, and cache push requests from the array interface.