Patent ID: 6670835
Filing Date: 2003-12-30
Classification: H03L

Abstract:
A delay locked loop receiving a reference clock signal and synchronizing a phase of the reference clock signal with a phase of a feedback clock signal, the delay locked loop comprising:a phase detector configured to compare the phase of the reference clock signal with the phase of the feedback clock signal and outputting a value corresponding to a difference between the phase of the reference clock signal and the phase of the feedback clock signal as an error control signal; a delay line including a plurality of first delay devices having a fixed delay time, selectively connected in series, and configured to adjust the number of first delay devices connected in series in response to a shift signal and to generate an output clock signal in response to an input clock signal; and a delay time adjuster configured to receive the reference clock signal and variably delay the reference clock signal in response to the error control signal to generate the input clock signal and the shift signal.