Patent ID: 9218872
Filing Date: 2015-12-22
Classification: G11C,H01L

Abstract:
1. An embedded synchronous random access memory (SRAM) chip, comprising: a first single-port (SP) SRAM macro, wherein the first macro comprises: a first periphery circuit, and a plurality of first SRAM cells, wherein each cell of the plurality of first SRAM cells comprises: a first cross-coupled inverter comprising a data storage node, and a second cross-coupled inverter comprising a data bar storage node; wherein each inverter comprises: a P-type single FinFET transistor (PU); an N-type single FinFET transistor (PD); a first pass-gate (PG) transistor; a second PG transistor, wherein each PG transistor is an N-type single FinFET transistor; a CVdd line; a CVss line; a bit-line; a bit-line bar; a word-line; and a shape of each cell of the plurality of first SRAM cells is a first rectangular cell shape comprising: a first X-pitch (X a first Y-pitch (Y a second SP SRAM macro, wherein the second SP SRAM macro comprises: a second periphery circuit, and a plurality of second SRAM cells, wherein each cell of the plurality of second SRAM cells comprises: a third cross-coupled inverter comprising a data storage node; and a fourth cross-coupled inverter comprising a data bar storage node; wherein each inverter comprises: a P-type single FinFET transistor (PU), and an N-type (PD) transistor, wherein the PD transistor comprises at least two FinFET transistors electrically connected in a parallel configuration; a third PG transistor, and a fourth PG transistor; wherein each of the third PG transistor and the fourth PG transistor comprise at least two FinFET transistors electrically connected in a parallel configuration; a CVdd line; a CVss line; a bit-line; a bit-line bar; a word-line; and a shape of each cell of the plurality of second SRAM cells is a second rectangular cell shape comprising: a second X-pitch (X a second Y-pitch (Y wherein each cell of the plurality of first SRAM cells is electrically connected to a write assist circuitry, wherein the write assist circuitry is configured to assist the write cycle capability of each cell of the plurality of first SRAM cells; wherein at least one cell of the plurality of second SRAM cells is not electrically connected to the write assist circuitry; and wherein a length ratio of X