Patent ID: 6841881
Filing Date: 2005-01-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a wiring substrate with plural wires and plural bonding pads electrically connected to said wires, formed on a main surface thereof, said bonding pads being arranged in a first pitch; a first semiconductor chip having an integrated circuit and a pluraltiy of first terminals formed on a main surface thereof, said first semiconductor chip being mounted on the main surface of the wiring substrate such that said main surface of said first semiconductor chip is facing said main surface of said wiring substrate and said first terminals of said first semiconductor chip are connected to a first set of the bonding pads through plural bump electrodes, said first terminals of said first semiconductor chip being arranged in said first pitch in a manner similar to that of said bonding pads of said wiring substrate; and a second semiconductor chip having an integrated circuit and a plurality of second terminals formed on a main surface thereof, said second semiconductor chip being stacked on the first semiconductor chip such that a rear surface of said second semiconductor chip, opposite to the main surface of said second semiconductor chip, is facing a rear surface of said first semiconductor chip, which is opposite the main surface of the first semiconductor chip, and said second terminals of said second semiconductor chip are connected to a second set of the bonding pads electrically through plural bonding wires, the second set of bonding pads being different from the first set of bonding pads, wherein said second terminals of said second semiconductor chip are arranged in a second pitch narrower than said first pitch, and wherein said first pitch is a pitch of adjacent bonding pads and adjacent first terminals, and said second pitch is a pitch of adjacent second terminals.