Patent ID: 7260708
Filing Date: 2007-08-21
Classification: G06F

Abstract:
1. A programmable processor comprising: an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying both a shift amount and a register having a register width, the register containing a first plurality of data elements having an elemental width smaller than the register width, the number of data elements in the first plurality of data elements being inversely related to the elemental width, the shift amount configurable to an amount inclusively between zero and one less than the elemental width, the execution unit is operable to: (i) shift a subfield of each of the first plurality of data elements by the shift amount to produce a second plurality of data elements; and (ii) provide the second plurality of data elements as a catenated result.