Patent ID: 7051227
Filing Date: 2006-05-23
Classification: G06F,Y02D

Abstract:
1. A circuit comprising: a finite state machine (FSM) having a first state and a second state, the FSM to operate in the second state when a first set of selected conditions are satisfied in an integrated circuit (IC), and to operate in the first state when a second set of selected conditions satisfied in the IC, the first set of selected conditions indicative of a low workload period in the IC; a clock signal generator to generate a first clock signal having a first frequency; and a gating circuit coupled to the FSM and the clock signal generator, the gating circuit to output a second clock signal having the first frequency when the FSM is in the first state, and to output the second clock signal having a second frequency that is less than the first frequency when the FSM is in the second state, the gating circuit including a mask generator coupled to the FSM and the clock signal generator to generate a mask signal used to mask selected clock cycles of the first clock signal, the mask generator comprising: