Patent ID: 6031762
Filing Date: 2000-02-29
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array comprising a first memory region in which rewriting can be freely executed, and a second memory region which is provided for detecting threshold voltages;an erasing means for erasing data stored in memory cells of said memory cell array;a writing means for writing data to be stored in the memory cells of said memory cell array;a reading means for reading data stored in said memory cell array;a time calculating means for calculating and outputting an erasing time and a writing time as a result of calculations by calculating the times required to detect the threshold voltages for writing and erasing data in the second memory region; anda voltage conversion means for outputting a voltage as a reading voltage after converting a voltage supplied by a voltage generating circuit corresponding to said erasing time and for outputting a voltage as a writing voltage after converting a voltage supplied by the voltage generating circuit corresponding to the writing time;wherein said reading means reads data stored in the memory cells of the first memory region by said reading voltage, and said writing means writes data to be stored in the memory cells of the memory cell array by said writing voltage.