Patent ID: 6087253
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method for forming tungsten plugs on a substrate, wherein said substrate includes a cell area for forming semiconductor devices, a peripheral area for manufacturing peripheral circuits, said method comprising:forming a dielectric layer on said substrate and said semiconductor devices;forming contact holes in said dielectric layer;forming an undoped polysilicon layer on a surface of said contact holes;patterning a first photoresist over said substrate to cover a region for forming a first conductivity type impurity region having a first conductivity type dopants in said peripheral area;performing a first ion implantation containing second conductivity type dopants using said first photoresist as a mask, thereby forming second conductivity impurity regions in said peripheral area and in said cell area, respectively, said first conductivity type dopants being of an opposite conductivity type than said second conductivity type dopants;removing said first photoresist;forming a second photoresist over said substrate to cover said second conductivity type impurity regions in said peripheral area and in said cell area;performing a second ion implantation containing said first conductivity type dopants using said second photoresist as a mask, thereby forming said first conductivity type impurity regions in said peripheral area;removing said second photoresist;forming a titanium layer on said doped polysilicon layer and along said surface of said contact holes;forming a titanium nitride layer on said titanium layer;forming a tungsten layer into said contact holes and on said titanium layer; andremoving a portion of said tungsten layer, thereby forming a plurality of tungsten plugs in said contact holes for serving as a bitline landing, a node landing , a first conductivity type impurity contact and a second conductive impurity contact.