Patent ID: 6247146
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A method for verifying trace data corresponding to a sequence of instructions, wherein said trace data includes a plurality of entries including one or more address entries and one or more bitmap entries, each bitmap entry corresponding to one or more conditional branches, the method comprising(a) scanning a last section of said trace data in reverse chronological order from a last address entry containing a last address to a prior address entry containing a prior address, wherein said last section comprises a last portion of said bitmap entries;(b) identifying a first number of said conditional branches indicated by said last portion of said bitmap entries;(c) scanning said sequence of instructions in execution order beginning at said prior address and ending at a last instruction corresponding to said last address entry;(d) counting a second number of said conditional branches which are scanned in execution order between said prior address and said last instruction corresponding to said last address entry; and(e) verifying that said first number is equal to said second number, wherein said trace data is determined to be invalid if said first number is not equal to said second number.