Patent ID: 8533641
Filing Date: 2013-09-10
Classification: G06F,H01L

Abstract:
1. A custom integrated circuit, comprising: a first fixed, non-programmable region comprising at least one non-mask-customizable layer, wherein the first fixed region comprises a plurality of base cells, each base cell comprising a plurality of transistors and at least a first interconnect layer comprising a first plurality of parallel traces; and a programmable region above the first fixed region comprising at least one mask-customizable layer, wherein at least one layer in the programmable region is coupled to the first interconnect layer so as to provide electrical access to all transistor nodes of the base cells, and wherein the programmable region comprises a at least a second interconnect layer coupled to the mask-customizable layer for customizing the integrated circuit, the second interconnect layer consisting essentially of a second plurality of traces orthogonal to the first plurality of traces and spaced apart according to a regular arrangement of routing tracks; wherein, for each base cell: the first plurality of parallel traces comprises, for each of the plurality of transistors, at least one trace corresponding to that transistor only and extending for a length of at least three adjacent routing tracks; and the first plurality of parallel traces are positioned such that a single routing track passes through a plurality of traces comprising at least one trace corresponding to each of the plurality of transistors.