Patent ID: 7863725
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A power device package comprising: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip stacked in order on the first die attach region; at least one die attach paddle disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip; and a plurality of first leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip; and wherein the die attach paddle comprises an adhesive layer attached to a top surface of the first power semiconductor chip, an interlayer member disposed on the adhesive layer, and a conductive pattern disposed on the interlayer member, wherein the conductive pattern comprises a second die attach region and a wire bonding region, wherein the second power semiconductor chip is mounted on and electrically connected to the second die attach region, and wherein the wire bonding region is electrically connected to the second die attach region.