Patent ID: 6559029
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising the steps of:forming a hard mask layer on a semiconductor substrate having a cell array region and a peripheral circuit region; patterning the hard mask layer and exposing the semiconductor substrate to form a hard mask pattern defining a first isolation region at the cell array region and simultaneously defining a second isolation region at the peripheral circuit region; forming a sacrificial material layer that fills a gap region between the hard mask patterns of the cell array region and is conformally formed over the entire surface of the second isolation region and the hard mask pattern of the peripheral circuit region; and sequentially etching the sacrificial material layer and the semiconductor substrate to form the first and second trench regions at the cell array region and the peripheral circuit region, respectively, wherein the first trench region is shallower than the second trench region.