Patent ID: 6943441
Filing Date: 2005-09-13
Classification: H01L,H03F,H03H,H05K

Abstract:
1. A semiconductor device comprising: a semiconductor chip having a square surface; a mounting substrate having a main surface thereof for mounting said semiconductor chip; a first electrode formed on a first area of a main surface of said semiconductor chip; a second electrode formed also on said first area of said main surface of said semiconductor chip; a first amplifier, formed also on said first area of said main surface of said semiconductor chip, having an input port electrically coupled with said first electrode and an output port electrically coupled with said second electrode; a third electrode formed on a second area of said main surface of said semiconductor chip, the second area being another area which is different from the first area on said main surface of said semiconductor chip; a fourth electrode formed also on said second area of said main surface of said semiconductor chip; a second amplifier, formed also on said second area of said main surface of said semiconductor chip, having an input port electrically coupled with said third electrode and an output port electrically coupled with said fourth electrode; a first bonding wire connecting said first electrode which is coupled with said input port of said first amplifier to said mounting substrate; a second bonding wire connecting said second electrode which is coupled with said output port of said first amplifier to said mounting substrate; a third bonding wire connecting said third electrode which is coupled with said input port of said second amplifier to said mounting substrate, said third bonding wire being electrically coupled with said second bonding wire which is coupled with said output port of said first amplifier; and a fourth bonding wire connecting said fourth electrode which is coupled with said output port of said second amplifier to said mounting substrate, wherein a length of said second bonding wire which is coupled with said output port of said first amplifier is made to be shorter than that of said first bonding wire which is coupled with said input port of said first amplifier so that a value of a series impedance of said second bonding wire which is coupled with said output port of said first amplifier is smaller than that of said first bonding wire which is coupled with said input port of said first amplifier, and wherein a length of said fourth bonding wire which is coupled with said output port of said second amplifier is made to be shorter than that of said third bonding wire which is coupled with said input port of said first amplifier so that a value of a series impedance of said fourth bonding wire which is coupled with said output port of said second amplifier is smaller than that of said third bonding wire which is coupled with said input port of said second amplifier.