Patent ID: 7907386
Filing Date: 2011-03-15
Classification: H01G

Abstract:
1. A multilayer capacitor comprising: a laminate in which a plurality of internal electrodes are laminated together with a dielectric layer in between; a first external electrode and a second external electrode formed on one end face and on the other end face, respectively, of the laminate; and a first terminal conductor and a second terminal conductor formed on respective side faces intersecting with each of the end faces of the laminate, so as to be opposed to each other, wherein the laminate has: a capacitance section in which a first internal electrode connected to a first polarity and a second internal electrode connected to a second polarity are alternated with at least one layer of the dielectric layer in between; and an ESR control section having a third internal electrode arranged on one side in a laminate direction of the capacitance section and connected to the first polarity, and a fourth internal electrode arranged on the other side in the laminate direction of the capacitance section and connected to the second polarity, wherein in the capacitance section, the first internal electrode is connected through a first lead conductor to the first terminal conductor only and the second internal electrode is connected through a second lead conductor to the second terminal conductor only, wherein in the ESR control section, the third internal electrode is connected through a third lead conductor to the first terminal conductor and through a fourth lead conductor to the first external electrode, and the fourth internal electrode is connected through a fifth lead conductor to the second terminal conductor and through a sixth lead conductor to the second external electrode, and wherein widths of the third to sixth lead conductors are smaller than widths of the first internal electrode and the second internal electrode and larger than widths of the first lead conductor and the second lead conductor.