Patent ID: 6968442
Filing Date: 2005-11-22
Classification: G06T

Abstract:
1. A parallel computer comprising: a plurality of memory elements configured to store data; a plurality of processing elements configured to process the data of the memory elements; and means for connecting each of said processing elements to a group of said memory elements which are adjacent to each other, wherein said processing elements are arranged in a two-dimensional matrix form, said memory elements are arranged in a two-dimensional matrix form, a matrix of said memory elements is offset with a deviation of half a pitch with respect to a matrix of said processing elements, and said means for connecting connects each of said processing elements to said group of memory elements that are adjacent to each of said processing elements, wherein an image frame buffer is constructed by said memory elements which are adjacent and continuous to one another in said two-dimensional matrix, and wherein image data obtained by an image pickup device are input into said parallel computer and stored in said image frame buffer.