Patent ID: 7771604
Filing Date: 2010-08-10
Classification: H01L

Abstract:
1. A method of semiconductor fabrication, comprising the steps of: forming a sidewall image transfer (SIT) loop on a substrate such that the SIT loop forms a hard mask having a width substantially equal to a critical width of a narrow section of a target shape, wherein the narrow section of the target shape corresponds to a pair of critical edges of the hard mask formed by the SIT loop; protecting the pair of critical edges of the hard mask on the substrate with a first portion of a follow-on mask, wherein a width of the first portion of the follow-on mask exceeds the critical width by an amount of overlap, and a width of a wide section of the follow-on mask exceeds a width of a wide section of the target shape; removing an exposed portion of the hard mask that is not covered by the follow-on mask; and exposing the pair of critical edges of the hard mask by etching the follow-on mask to reduce the width of the first portion of the follow-on mask to less than the critical width.