Patent ID: 8681525
Filing Date: 2014-03-25
Classification: G06F,G11C,H01L

Abstract:
1. A device comprising: a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals; and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection, wherein the third terminals are smaller in number than the first terminals, wherein the first semiconductor chip further includes a mode register temporarily storing mode information, and the first circuit is configured to electrically connect selected ones of the first terminals respectively to the second terminals in response to a content of the mode information, and wherein the mode information takes a selected one of first and second modes, and the first circuit is configured to electrically connect first selected ones of the first terminals respectively to the second terminals in response to the mode information taking the first mode and second selected ones of the first terminals respectively to the second terminals in response to the mode information taking the second mode, the first selected ones being different from the second selected ones.