Patent ID: 7822948
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A processor, the processor comprising: a plurality of rename registers each configured to store data and to assume the address of an architecturally visible (AV) register; an assignment unit configured to assign a plurality of blocks of instruction (instruction blocks) to a plurality of issue units, wherein a branch instruction ends an instruction block and each instruction block does not exceed a specified number of instructions in length, track dependencies between the instruction blocks, and assign a pointer linking a predecessor instruction block with a successor instruction block when a dependency is identified between the predecessor and successor instruction blocks, the linked instruction blocks forming a chain and instructions of the instruction blocks referencing AV registers; the plurality of issue units each comprising a renaming map that maps each AV register address to a rename register and comprises a valid flag for each AV register address and a plurality of register placeholders and configured to each receive predecessor mapping information from the renaming map of the issue unit's predecessor issue unit in response to the assignment unit identifying a relationship with the predecessor issue unit and final mapping information being available from the predecessor issue unit and issue an instruction block to a dependency resolution/execution unit after all register placeholders in all pre-issued instructions have been changed to point to rename registers; and a dependency resolution/execution unit configured to receive instruction blocks from the plurality of issue units.