Patent ID: 7404054
Filing Date: 2008-07-22
Classification: G06F

Abstract:
1. An information processing device comprising: a first bus master device, a first slave device which accepts a request via a request control line in a system bus and sends back responses to the system bus, and the system bus connected between the first bus master device and the first slave device, wherein the system bus comprises the request control line, a read/write enable signal line, an address line, a write data line, and a read data line; the first bus master device comprises a first illegal address access blocking circuit to detect and permanently block/extinguish, during an attempted access of the first slave device, a “request” level signal of an illegal address access of the first bus master device to an address assigned as normally inaccessible to the bus master device, wherein: when the value of the address line is within a predetermined allowable address access range, the first illegal address access blocking circuit outputs an output signal of the request control line in the first bus master device to the first slave circuit via the request control line in the system bus without changing the signal level of the output signal; and when the value of the address line is outside the predetermined allowable address access range, the first illegal address access blocking circuit outputs a “no request” level signal to the first slave circuit via the request control line in the system bus, even if the output from the request control line in the first bus master device is a “request” level signal to permanently extinguish such occurrence of the “request” level signal.