Patent ID: 6765841
Filing Date: 2004-07-20
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array; a plurality of main word lines extending along a first direction in the memory cell array; a row decoder which selects one of the main word lines; a plurality of memory blocks formed by dividing the memory cell array in a first direction; a plurality of sub word lines disposed in each of the plurality of memory blocks and subordinate to each of the main word lines; a plurality of sub row decoders respectively provided for the memory blocks, each of the sub row decoders having a plurality of sub word select signal lines extending along a second direction which intersects the first direction to select one of the sub word lines; a first signal supply section which is disposed on one end in the second direction and supplies a plurality of sub word select signals to the sub word select signal lines in each of the sub row decoders; and a second signal supply section which is disposed on the other end in the second direction and supplies the sub word select signals to the sub word select signal lines in each of the sub row decoders.