Patent ID: 7723210
Filing Date: 2010-05-25
Classification: H01L

Abstract:
1. A method for packaging an electronic component comprising: providing a silicon wafer, the silicon wafer having a silicon wafer first surface and a silicon wafer second surface, opposite the silicon wafer first surface; forming a first bonding location, the first bonding location being formed on the silicon wafer second surface, the first bonding location having a first bonding location centerpoint corresponding to a center of the first bonding location; applying a first dielectric layer, the first dielectric layer having a first dielectric layer first surface and a first dielectric layer second surface, opposite the first dielectric layer first surface, the first dielectric layer first surface being applied to the silicon wafer second surface; ablating a first conductive structure portion pattern in the first dielectric layer; applying a first conductive layer, the first conductive layer having a first conductive layer first surface and a first conductive layer second surface, opposite the first conductive layer first surface, the first conductive layer first surface being applied to the first dielectric layer second surface, the first conductive layer filling the first conductive structure portion pattern ablated in the first dielectric layer to create a first conductive structure portion, the first conductive structure portion having a first conductive structure portion first surface and a first conductive structure portion second surface, opposite the first conductive structure portion first surface, at least part of the first conductive structure portion first surface being electrically coupled to at least part of the first bonding location; applying a second dielectric layer, the second dielectric layer having a second dielectric layer first surface and a second dielectric layer second surface, opposite the second dielectric layer first surface, the second dielectric layer first surface being applied to the first conductive layer second surface; ablating a second conductive structure portion pattern in the second dielectric layer, the second conductive structure portion pattern extending from the second dielectric layer second surface to at least a portion of the first conductive structure portion second surface; and applying a second conductive layer, the second conductive layer having a second conductive layer first surface and a second conductive layer second surface, opposite the second conductive layer first surface, the second conductive layer first surface being applied to the second dielectric layer second surface, the second conductive layer filling the second conductive structure portion pattern ablated in the second dielectric layer to create a second conductive structure portion, the second conductive structure portion having a second conductive structure portion first surface and a second conductive structure portion second surface, opposite the second conductive structure portion first surface, the second conductive structure portion second surface having a second conductive structure portion second surface centerpoint corresponding to a center of the second conductive structure portion second surface, wherein; the second conductive structure portion second surface centerpoint is offset from the first bonding location centerpoint to form an offset conductive structure, the offset conductive structure providing a conductive path from the first bonding location to the second conductive structure portion second surface.