Patent ID: 7227768
Filing Date: 2007-06-05
Classification: H01L

Abstract:
1. A semiconductor die comprising: a memory core array situated over a substrate, said memory core array comprising a plurality of bitlines, said plurality of bitlines being situated in a first interconnect metal layer in said semiconductor die; an interconnect structure situated over said memory core array, said interconnect structure being situated in a second interconnect metal layer in said semiconductor die; wherein said interconnect structure is situated over each of said plurality of bitlines, wherein said interconnect structure forms one of a plurality of capacitances with each of said plurality of bitlines, wherein each of said plurality of capacitances is substantially equal in value to each other of said plurality of capacitances, and wherein said at least one interconnect line forms an angle with respect to said plurality of bitlines, wherein said angle is greater than 0.0 degrees and less than or equal to 90.0 degrees.