Patent ID: 6378032
Filing Date: 2002-04-23
Classification: G06F,G11C

Abstract:
A method of controlling a data transfer involving a multi-bank DRAM having a shared sense amplifier architecture, comprising:providing a plurality of logical addresses that define a logical address sequence to be used in the data transfer; mapping the logical addresses of the logical address sequence into respective physical addresses that define a physical address sequence that corresponds to the logical address sequence and includes a plurality of pairs of first and second physical addresses that are mutually adjacent addresses in the physical address sequence, said mapping step including assigning the first and second physical addresses in each of said pairs such that the first physical address points to a first location in a first bank of the DRAM and the second physical address points to a second location in a second bank of the DRAM that differs from and does not share sense amplifiers with the first bank; and performing the data transfer according to the physical address sequence, including using the physical addresses of the physical address sequence to access sequentially locations of the DRAM that are respectively pointed to by the physical addresses of the physical address sequence.