Patent ID: 6629162
Filing Date: 2003-09-30
Classification: G06F

Abstract:
A logically partitioned data processing system, comprising:a plurality of logical partitions; a plurality of operating systems, each assigned to one of the plurality of logical partitions; a plurality of memory locations, each location assigned to one of the plurality of logical partitions; a plurality of input/output adapters, each associated to one of the plurality of logical partitions; and a hypervisor, wherein the hypervisor prevents transmission of data between an input/output adapter associated with a first one of the plurality of logical partitions and ones of the plurality of memory locations unassigned to the first one of the plurality of logical partitions by determining whether an address included in a direct memory access request to be accessed is within a range of DMA addresses associated with said input/output adapter, and said hypervisor for preventing said direct memory access request from accessing said address in response to a determination by said hypervisor that said address is not within said range, wherein said hypervisor makes a determination to prevent a transmission based on an address included within said DMA request.