Patent ID: 6515911
Filing Date: 2003-02-04
Classification: G11C

Abstract:
A hierarchic semiconductor memory device of the non-volatile type, comprisinga matrix of memory cells with sectors organized into columns, wherein each sector has a specific group of local word lines, the matrix further including a main word line running through all of the matrix sectors which have rows in common; a first circuit device that includes a first transistor of a first type having first and second conduction terminals connected, respectively, to the main word line and to a first one of the local word lines, and a second transistor of a second type having first and second conduction terminals connected, respectively, to the first local word line and to a reference voltage; and a second circuit device that includes a first transistor of the first type having first and second conduction terminals connected, respectively, to the main word line and to a second one of the local word lines, and a second transistor of the second type having first and second conduction terminals connected, respectively, to the second local word line and to the reference voltage, wherein the first circuit device further includes: a first additional transistor of the second type having first and second conduction terminals connected, respectively, to the main word line and the first local word line; and a charge transistor having first and second conduction terminals connected between the main word line and the first local word line and structured to reduce the charging time for the first local word line, the charge transistor including a control terminal coupled to a control terminal of the first transistor of the first circuit device.