Patent ID: 6518669
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate including semiconductor elements; an underlying wiring layer formed over said semiconductor substrate, said underlying wiring layer including a wiring pattern; an underlying insulating layer formed on said semiconductor substrate, said underlying insulating layer covering said underlying wiring layer; a plurality of via holes extending through said underlying insulating layer and reaching said underlying wiring layer; a plurality of via conductors embedded respectively in said via holes; an insulating stack layer formed on said underlying insulating layer, said insulating stack layer covering said via conductors, said insulating stack layer including a first insulating layer having an etching characteristic and a second insulating layer having an etching characteristic different from that of said first insulating layer; a pad groove formed through said insulating stack layer, said pad groove defining a pad region in which said via conductors are exposed, said pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in said pad groove.