Patent ID: 6756295
Filing Date: 2004-06-29
Classification: H01L

Abstract:
The process for fabricating a chip structure, comprising:Step 1: providing a wafer with a plurality of electric devices, an interconnection scheme and a passivation layer, both the electric devices and the interconnection scheme arranged inside the wafer, the interconnection scheme electrically connected with the electric devices, the passivation layer disposed on a surface layer of the wafer, the passivation layer having at least one opening exposing the interconnection scheme; Step 2: forming a conductive layer over the passivation layer of the wafer and the conductive layer electrically connected with the interconnection scheme; Step 3: forming a photoresist onto the conductive layer, and the photoresist having at least one opening exposing the conductive layer; Step 4: filling at least one conductive metal over the conductive layer; Step 5: removing the photoresist; and Step 6: removing the conductive layer not covered with the conductive metal, wherein a signal is transmitted from one of the electric devices to the interconnection scheme, then passes through the passivation layer, and finally is transmitted to the conductive metal, and further, the signal is transmitted from the conductive metal to the interconnection scheme with passing through the passivation layer, and finally is transmitted to the other one or more of the electric devices.