Patent ID: 6437619
Filing Date: 2002-08-20
Classification: G11C,H03L

Abstract:
A clock generation circuit comprising:a fixed delay circuit which provides a predetermined delay; a variable delay circuit including a plurality of variable delay elements and delay time control terminals; a phase detector which detects a phase difference between a first clock signal inputted to said variable delay circuit and a second clock signal corresponding to a signal delayed by said variable delay circuit and said fixed delay circuit; a delay amount control circuit which controls a delay amount of said variable delay circuit according to the phase difference detected by said phase detector; and a number-of-cycles determining circuit which determines the number of clock cycles from the input of the first clock signal to said variable delay circuit to the execution of a phase comparison by said phase detector, according to a start sequence, wherein said delay amount control circuit controls the delay amount of said variable delay circuit according to the number of the clock cycles determined by said number-of-cycles determining circuit.