Patent ID: 7115462
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. A method of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages, said method comprising: forming n-doped regions in a p-type substrate at first locations where NMOS devices will be formed, said n-doped regions corresponding to source and drain regions for said NMOS devices; forming n-wells in said p-type substrate at second locations where PMOS devices will be formed; forming p-doped regions within said n-wells, said p-doped regions corresponding to source and drain regions for said PMOS devices; and adding a same amount of p-type dopant at selected locations chosen from said first and said second locations, wherein said adding of p-type dopant is performed in a single threshold adjust process step; wherein by adding said same amount, concentrations of p-type dopant at said first and second locations and concentrations at said selected locations correspond to specific threshold voltages for said NMOS and PMOS devices, wherein NMOS devices at said first locations without said amount of p-type dopant added have a first threshold voltage, NMOS devices at said selected locations with said amount of p-type dopant added have a second threshold voltage, PMOS devices at said second locations without said amount of p-type dopant added have a third threshold voltage, and PMOS devices at said selected locations with said amount of p-type dopant added have a fourth threshold voltage, wherein the absolute values of said second and third threshold voltages are substantially equal, and wherein said first and fourth threshold voltages are substantially equal.