Patent ID: 6074921
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method of manufacture, comprising:(a) providing a device having a number of transistor gates spaced apart from each other along a semiconductor substrate, the gates extending away from the substrate, the device including a number of silicided source and drain regions along the substrate;(b) establishing a dielectric layer on the substrate and the gates after said providing;(c) chemically-mechanically polishing the device to provide self-aligned exposure of a polysilicon member of each of the gates, a portion of the dielectric layer that is positioned between the gates remaining on the substrate after said polishing and covering the silicided source and drain regions;(d) removing a portion of the polysilicon member of each gates to form a corresponding number of recesses therein, the gates each having a polysilicon layer below a respective one of the recesses after said removing; and(e) depositing metal in each of the recesses.