Patent ID: 6392267
Filing Date: 2002-05-21
Classification: G11C,H01L

Abstract:
A non-volatile memory array, comprising:a plurality of memory cells formed in a semiconductor substrate and arranged in rows and columns in said substrate, each memory cell including a drain region, a source region, a channel region disposed between the drain region and the source region, a floating gate disposed over at least the channel region, and a control gate disposed over the floating gate, and wherein the source regions of memory cells in adjacent columns of said array are electrically isolated by dielectric isolation regions formed in said substrate; and for each row of memory cells of said array, a conductive member disposed along at least a portion of said row, said conductive member making electrical contact with the source regions of the memory cells of the portion of said row, said conductive member being self-aligned with the memory cells of said portion of said row.