Patent ID: 7919387
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A method of forming a memory device comprising: forming at least two floating gate structures on a semiconductor substrate; forming a conformal dielectric layer on the floating gate structures, wherein the conformal dielectric layer is present on an upper surface and sidewall surface of each of the at least two floating gate structures; forming a sacrificial material atop the conformal dielectric layer that is present between adjacent floating gate conductors of the floating gate structures; forming a control gate conductor overlying each of the at least two floating gate structures, wherein the control gate conductor is separated from the each of the at least two floating gate structures by the conformal dielectric layer; etching the sacrificial material to provide voids between the adjacent floating gate conductors; depositing a low-k dielectric material within the voids; etching the low-k dielectric material to have an upper surface substantially co-planar with the upper surface of the adjacent floating gate conductors, wherein the low-k dielectric material is present along a first direction separating the adjacent floating gate conductors; and forming a source region and the drain region in the semiconducting substrate that are adjacent to each portion of the semiconducting substrate that is underlying the at least two floating gate structures, wherein the first direction separating the adjacent floating gate conductors is perpendicular to the length of the channel.