Patent ID: 6953960
Filing Date: 2005-10-11
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells arranged in rows and columns; a plurality of sub word lines, provided corresponding to the respective memory cell rows, each having memory cells on a corresponding row connected thereto; a plurality of main word lines, each provided corresponding to a prescribed number of sub word lines in said plurality of sub word lines and disposed in a first conductive layer, for transmitting a row select signal; a plurality of shunting interconnection lines, provided corresponding to the respective sub word lines in a second conductive layer formed under said first conductive layer, each shunting interconnection line for electrically connecting to a corresponding sub word line at a prescribed interval and allowing signal transmission between said each shunting interconnection line and said corresponding sub word line; and a plurality of sub word drivers, provided corresponding to the sub word lines, each for driving a corresponding sub word line and a corresponding shunting interconnection line into a selected state according to at least a row select signal on a corresponding main word line.