Patent ID: 6677665
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A dual semiconductor die integrated circuit package, which comprises:a first leadframe having a die pad and a plurality of leads disposed along one side of the die pad; a second leadframe having a die pad and a plurality of leads disposed along one side of the die pad, wherein the die pads of the first and second leadframes are laterally positioned between the leads of the first leadframe and the leads of the second leadframe, and the die pad of the second leadframe is arranged in a staggered and laterally offset manner with respect to the die pad of the first leadframe; a first semiconductor die having an active surface formed with a plurality of bonding pads thereon, and an inactive surface opposed to the active surface, the inactive surface having a portion thereof being adhered to the die pad of the first leadframe, and a non-adhered portion being positioned away from the leads of the first leadframe; a second semiconductor die having an active surface formed with a plurality of bonding pads thereon, and an inactive surface opposed to the active surface, the inactive surface having a portion thereof being adhered to the die pad of the second leadframe, and a non-adhered portion being positioned away from the leads of the second leadframe, wherein the non-adhered portion of the second semiconductor die is separated from the die pad of the first leadframe, and the non-adhered portion of the first semiconductor die is separated from the die pad of the second leadframe, and wherein the die pads of first and second leadframes are each positioned in elevation between the first semiconductor die and the second semiconductor die; a first set of electrical connection means for electrically coupling the bonding pads on the active surface of the first semiconductor die to the corresponding leads of the first leadframe; a second set of electrical connection means for electrically coupling the bonding pads on the active surface of the second semiconductor die to the corresponding leads of the second leadframe; and an encapsulant for encapsulating the first and second semiconductor dies, the die pads of the first and second leadframes, and a part of the leads of the first and second leadframes.