Patent ID: 7384844
Filing Date: 2008-06-10
Classification: H01L

Abstract:
1. A method of fabricating a flash memory device, the method comprising: defining a high voltage region and a low voltage region on a substrate, the high voltage region providing an area for one or more first transistors configured to operation at a first voltage, the low voltage region providing an area for one or more second transistors configured to operation at a second voltage that is lower than the first voltage, each first transistor having a gate and a source/drain region on each side of the gate; forming a first impurity region as part of the source/drain region, the first impurity region having a first depth from an upper surface of the substrate, the first impurity region being of first conductivity having a first impurity concentration; forming a second impurity region as part of the source/drain region, the second impurity region having a second depth from the upper surface of the substrate that is less than first depth, the second impurity region being of the first conductivity and having a second impurity concentration that is greater than the first impurity concentration; and implanting impurities of second conductivity into the source/drain region, wherein the second conductivity is contrary to the first conductivity.