Patent ID: 8681558
Filing Date: 2014-03-25
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a parallel bitline semiconductor architecture comprising a plurality of wordlines, and a plurality of transistors, each of the plurality of transistors having a gate that is electrically connected to respective ones of the plurality of wordlines a source node that is electrically connected directly to a local source line and a drain node that is electrically connected directly to a local bitline, wherein the local source line is connected to a common source line via a select transistor and the local bitline is connected to a common bit line by a second select transistor; and a channel-based processing component configured to ground the local source line and the local bitline to program one transistor of the plurality of transistors, wherein the channel-based processing component inhibits programming of a non-program transistor sharing a common wordline with the one transistor by floating a second local source line and a second local bitline connected to the non-program transistor.