Patent ID: 6258648
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of forming MOSFET semiconductor devices on a semiconductor substrate using a selective salicide process for logic devices and not on memory devices comprising:providing a semiconductor silicon substrate having field oxide regions for MOSFET device isolation;forming gate oxide and polysilicon gate structures on both said logic devices and memory devices;thermally oxidizing said polysilicon gate structures to form silicon oxide on said polysilicon gate structures; depositing a first conformal dielectric layer over said substrate;masking and anisotropically reactive ion etching (RIE) said dielectric layer to form gate sidewall spacers on said polysilicon gate structures;patterning source/drain regions whereby said polysilicon gates are self-aligned;forming by implantation source/drain regions associated with said polysilicon gate structures;removing said dielectric sidewall spacers; depositing a second conformal dielectric layer over said substrate;forming a salicide blockout mask over said memory devices, while exposing logic FET devices using said second conformal dielectric layer;etching anisotropically said second dielectric layer to form second sidewall spacers on said logic devices;removing said salicide blockout mask;applying a salicide process of metal deposition and forming self-aligned silicide structures on exposed said logic FET devices, whereby there is formed low electrical resistance lines and contacts on polysilicon gates and source/drain regions, while silicide formation is blocked on memory FET devices, by said second dielectric layer.