Patent ID: 7490190
Filing Date: 2009-02-10
Classification: G06F

Abstract:
1. A single instruction, multiple data computer system (“SIMD”) including at least one memory device having a plurality of memory arrays, each of the arrays having memory cells arranged in rows and columns, the SIMD system comprising: a central control unit having an address bus, the central control unit applying an address signal to the address bus; an address steering circuit having a row address bus and a column address bus, and configured to receive the addressing signal from the central control unit, the address steering circuit operable to generate in response to the addressing signal a control signal indicative of the number of bits in the word to be accessed, the control signal having a granularity mode corresponding to a storage format for selecting a column of the memory cells for accessing a word having a predetermined number of bits, and further operable to generate a row address to apply to the row address bus and a column address to apply to the column address bus in response to the control signal; a plurality of processing elements each having a data bus and an address bus coupled to a respective memory array of the at least one memory device, each processing element operable to generate and provide a local column address to apply to the respective address bus, the local column address being generated without the assistance of the address steering circuit; and a plurality of select circuits each coupled to a respective data bus coupled to a memory array of the at least one memory device, each of the select circuits configured to receive the column address from the column address bus of the address steering circuit and the localized column address from the data bus of a respective processing element, each of the select circuits operable to select either the column address or the local column address to access a column of memory cells from the respective memory array.