Patent ID: 6765231
Filing Date: 2004-07-20
Classification: G02F,H01L

Abstract:
A semiconductor device comprising:a substrate; a gate line provided over said substrate; a first semiconductor film provided over said gate line; a first insulating layer provided between said gate line and said first semiconductor film; a second semiconductor film provided over said substrate and in a same layer as said first semiconductor film; a source region and a drain region and a channel region provided in said first semiconductor film; a gate electrode provided over said channel region with a gate insulating film therebetween, said gate electrode connected with said gate line; a second insulating film provided over said second semiconductor film and in a same layer as said gate insulating film; a capacity electrode provided over said second insulating film; a data line provided in a same layer as said gate electrode; an interlayer insulating film provided over said gate electrode and said capacity electrode and said data line; a pixel electrode provided over said interlayer insulating film and connected with one of said source region and said drain region; and a connecting electrode provided over said interlayer insulating film, wherein said data line is connected to the other of said source region and said drain region through said connecting electrode, and wherein a capacitor is formed by said second semiconductor film and said second insulating film and said capacity electrode.