Patent ID: 6650521
Filing Date: 2003-11-18
Classification: H02H,H03K

Abstract:
A protection circuit for protecting an electronic system under a load dump condition; said system containing at least one power MOSFET which has first and second main power terminals; the protection circuit adapted to be coupled to a load dump test circuit, the load dump test circuit having a source of d-c voltage; a capacitor connected to said source of d-c voltage; a first switch; a first resistor; and the protection circuit comprising a controllably conductive device and a second resistor; said capacitor, said first switch, said first resistor and said first and second main power terminals connected in a closed series circuit when the load dump test circuit is connected during a load dump test; said second resistor and said controllably conductive device being connected in closed series relation across said first and second main power terminals; the protection circuit further comprising a control circuit for said controllably conductive device; said control circuit being connected across said first and second main power terminals and being operable to turn on said controllably conductive device when the voltage across said first and second main power terminals exceeds a predetermined value whereby the voltage drop across said first resistor is increased and a voltage across the first and second main power terminals is reduced.