Patent ID: 9224482
Filing Date: 2015-12-29
Classification: G11C,H01L

Abstract:
1. An integrated circuit memory, comprising: at least one word line that includes a row of split gate memory cells, each split gate memory cell including a selection transistor section, having an embedded vertical selection gate, and a floating-gate transistor section having a horizontal floating gate and a horizontal control gate; a selection line configured to apply a selection voltage to the selection gates of the memory cells of the row; a control gate line configured to apply a gate voltage to the control gates of the memory cells of the row; bit lines configured to individually apply a programming current to the memory cells; a source plane embedded beneath the memory cells and common to the memory cells of the word line, the source plane being configured to collect programming currents for programming the memory cells, wherein the selection transistor sections of the memory cells are electrically coupled to the source plane and the floating-gate transistor sections of the memory cells are electrically coupled to the bit lines; and a programming control circuit configured to control production of hot electrons in a vertical channel region of the selection transistor second and thereby simultaneously control hot electron injection into the floating gate of the memory cell by controlling the voltage applied to the vertical selection gate.