Patent ID: 6647334
Filing Date: 2003-11-11
Classification: B60T,G06F

Abstract:
An arithmetic and control unit comprising,a monitor unit which counts a cycle time by receiving diagnostic pulses and generates an overflow bit which takes on a prescribed state value when it is decided that the cycle time is larger than a prescribed overflow decision time and outputs the bit after a lapse of a prescribed time, and outputs a pulse-form reset signal at an active level during said prescribed time when the overflow bit is said prescribed state value, and a control unit which generates said diagnostic pulse at each execution of a unit control during control operation, is reactivated when receives the active level of said reset signal and, after an activation including a reactivation, receives and stores an overflow bit, and when the stored overflow bit is not said prescribed state value, it is decided to be an initial activation and stops the output of said diagnostic pulse to said monitor unit during a monitor unit inspection time which is larger than said overflow decision time, generates a failure warning signal if the reset signal is not received within said monitor unit inspection time, and when said stored overflow bit is said prescribed state value, it is decided to be a reactivation and outputs said failure warning signal as well when the updated number of times of overflow occurrence obtained by adding 1 (one) to the number of times of overflow occurrence which is stored in a nonvolatile memory exceeds a prescribed allowable number of times.