Patent ID: 9190535
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A device comprising: a buried well region of a first conductivity type; a first High-Voltage Well (HVW) region of the first conductivity type over the buried well region; a first well region of a second conductivity type opposite to the first conductivity type, wherein the first well region comprises an edge contacting an edge of the first HVW region; a drain region of the first conductivity type in a surface portion of the first HVW region; a first source region of the first conductivity type in a surface portion of the first well region; a first gate electrode over the first HVW region and the first well region, with the drain region and the first source region on opposite sides of the first gate electrode; a plurality of buried regions of the second conductivity type, wherein the plurality of buried regions is parallel to each other, and is over and contacting a top surface of the buried well region; and a plurality of HVW regions of the first conductivity type separating the plurality of buried regions from each other, wherein the plurality of buried regions and the plurality of HVW regions are spaced apart from the first source region by the first well region.