Patent ID: 7960732
Filing Date: 2011-06-14
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate line disposed on the substrate; a first insulating layer disposed on the gate line; a semiconductor member disposed on the first insulating layer; a plurality of ohmic contacts disposed on the semiconductor member; a source electrode and a drain electrode disposed on the ohmic contacts, each of the source electrode and the drain electrode comprising a first film and a second film disposed on the first film; a second insulating layer that is disposed on the source electrode and the drain electrode and has a first contact hole exposing a portion of the drain electrode and a portion of the first insulating layer adjacent thereto and an opening exposing a portion of the semiconductor member; a pixel electrode disposed on the second insulating layer and contacting the first film of the drain electrode through the first contact hole; and a columnar spacer disposed on the exposed portion of the semiconductor member.