Patent ID: 6515361
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A cavity down ball grid array (CDBGA) package comprising:a thermal dissipating substrate having a chip region located at a center and a circuit substrate region located at a periphery of the chip region; a circuit substrate comprising an insulating layer and a patterned trace layer, wherein a plurality of vias are formed in the insulating layer which is adhered on the circuit substrate region, and a plurality of ground pads, ball pads and nodes are formed on the patterned trace layer, wherein the ground pads correspond to the vias, and a hole is formed at the center of each ground pad corresponds to each via, the circuit substrate further comprising a solder mask layer covering the patterned trace layer and exposing the ground pads, ball pads and the nodes; a plurality of conductive bumps located within the respective vias, wherein the conductive bumps does not fill the via; a chip having an active surface and a corresponding back surface, wherein the back surface of the chip is adhered on the chip region, and a plurality of bonding pads are formed on the active surface, wherein the bonding pads are electrically connected to the nodes; a molding compound encapsulating the chip, the nodes and the connecting parts of the bonding pads and the nodes; and a plurality of solder balls located on the ground pads, the ball pads and the respective conductive bumps to completely fill the vias and respectively connect the conductive bumps.