Patent ID: 6333665
Filing Date: 2001-12-25
Classification: H03K

Abstract:
A gate circuit for controlling an insulated gate semiconductor device having a gate terminal, comprising:positive and negative control power source terminals;first and second semiconductor device groups, in which a plurality of semiconductor devices are connected in series between said positive and negative control power source terminals;a switching signal source for supplying ON/OFF control signals to said semiconductor devices of the first and second semiconductor device groups; anddelay circuits for delaying said ON/OFF control signals supplied from said switching signal source to one or other of said first or second semiconductor device groups during a predetermined time,wherein a mid-point of said first semiconductor device group is connected to said gate terminal of said insulated gate semiconductor device,respective collectors of said first semiconductor device group are connected to said positive and negative control power source terminals via respective resistors, anda central connecting point of said second semiconductor device group is connected to said gate terminal of said insulated gate semiconductor device.