Patent ID: 8643520
Filing Date: 2014-02-04
Classification: H03M

Abstract:
1. A shadowed current cell comprising: a first primary differential transistor having a gate receiving a true input, with a conducting channel between a tail node and a true output node; a first shadow differential transistor having a gate receiving a complement input, with a conducting channel between the tail node and the true output node; a second primary differential transistor having a gate receiving the complement input, with a conducting channel between the tail node and a complement output node; a second shadow differential transistor having a gate receiving the true input, with a conducting channel between the tail node and the complement output node; a first load device coupled between the true output node and a first supply node; a second load device coupled between the complement output node and the first supply node; a cascode transistor having a channel between the tail node and a cascode node; and a tail transistor having a channel between the cascode node and a second supply node, wherein during an OFF state when the first primary differential transistor is turned off, the first shadow differential transistor conducts a shadow current to the true output node and contributes a shadow ON impedance to the true output node, and the first primary differential transistor contributes a primary OFF impedance to the true output node; wherein during an ON state when the first primary differential transistor is turned on, the first primary differential transistor conducts a primary current to the true output node and contributes a primary ON impedance to the true output node, and the first shadow differential transistor contributes a shadow OFF impedance to the true output node, whereby the shadow OFF impedance is contributed to the true output node during the ON state, and the shadow ON impedance is contributed to the true output node during the OFF state.