Patent ID: 6476443
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A MOSgated device comprising:a semiconductor substrate of one of the conductivity types and having an upper planar surface; a channel diffusion region of the other of the conductivity types which extends into said upper planar surface of said substrate and to a first depth below said surface; a source diffusion of said one of the conductivity types which extends into said substrate to a second depth which is less than said first depth; a plurality of rows of spaced, longitudinally parallel trenches formed into said substrate and into said upper planar surface to a third depth below said substrate surface which is greater than said first depth, said rows being separated by untrenched areas not lateral to said longitudinal sides of said trenches; an insulation gate layer formed on the walls of said plurality of trenches at least in the areas between said first and second depths; a conductive gate material disposed atop said insulation gate layer and within the interior of said trench; a gate electrode connected to said conductive gate; and a drain contact connected to said substrate; and at least one source contact disposed in an untrenched area and connected to said source diffusion region.