Patent ID: 6881640
Filing Date: 2005-04-19
Classification: H01L

Abstract:
1. A fabrication method for heterojunction bipolar transistor, said method comprising: providing a substrate having a collector therein, a base layer over said substrate, an oxide layer over said base layer, and a polysilicon layer over said oxide layer; forming a first photoresist layer over said polysilicon layer; transferring a line pattern into said first photoresist layer by a photo mask with said line pattern to form a emitter window pattern; etching said polysilicon layer to expose said oxide layer by using said emitter window pattern as an etching mask; performing a first ion implantation process into said base layer to form a first extrinsic base region therein; removing said emitter window pattern; forming a dielectric layer over said polysilicon layer and said oxide layer; thinning said dielectric layer to expose said polysilicon layer; removing said polysilicon layer to expose said oxide layer; etching said exposed oxide layer to expose said base layer; forming an emitter layer over said base layer and said dielectric layer; forming a second photoresist layer over said emitter layer; transferring an emitter pattern into said second photoresist layer; etching said emitter layer to form an emitter and expose said oxide layer by using said emitter pattern as an etching mask; and performing a second ion implantation process to form a second extrinsic base region.