Patent ID: 6122196
Filing Date: 2000-09-19
Classification: G11C

Abstract:
A non-volatile semiconductor storage comprising:a plurality of main bit lines;a plurality of sub bit lines;a plurality of memory cells each comprising a control gate, a drain terminal and a source terminal, wherein said drain terminals of said memory cells are connected to said sub bit lines;a plurality of first transistors, each comprising a control gate, a drain terminal and a source terminal, wherein a source-drain path of each of said first transistors is disposed between one of said main bit lines and one of said sub bit lines; anda plurality of second transistors each comprising a control gate, a drain terminal and source terminal, wherein said drain terminal of said second transistor is connected to said one of said sub bit lines;wherein a gate signal of said first transistor is deactivated while a gate signal of said second transistor is activated;wherein said memory cells are connected so that the source terminal of said second transistor is connected to the source terminal of a memory cell group.