Patent ID: 6525426
Filing Date: 2003-02-25
Classification: H01L

Abstract:
In combination, an integrated circuit having at least two separated regions, said combination comprising:a semiconductor substrate having a surface; a plurality of substantially parallel conductive strips disposed on said substrate surface, each conductive strip of said plurality of substantially parallel conductive strips having a length; a layer of dielectric material deposited on at least a portion of said substrate surface and around said plurality of substantially parallel conductive strips, said layer of dielectric material forming at least one set of contoured dielectric surfaces overhanging said substrate surface at a location between at least two of said plurality of substantially parallel conductive strips to define an elongated passageway located therein, said elongated passageway being substantially enclosed within said layer of dielectric material along said length of said plurality of substantially parallel conductive strips in a direction substantially parallel to said plurality of substantially parallel conductive strips, said elongated passageway having at least one opening leading thereinto; a conductive material substantially filling said elongated passageway through said at least one opening; and at least one electrical interconnect formed between said at least two separated regions of said integrated circuit by said conductive material substantially filling said elongated passageway through said at least one opening.