Patent ID: 6262890
Filing Date: 2001-07-17
Classification: G06F,H05K,Y02P

Abstract:
A data processing system, comprising:a system planar having a first surface and an opposite second surface;first and second processor complexes, each having at least one microprocessor, a control logic chip for controlling data flow among the microprocessors, and a memory set associated with the control logic chip;the first processor complex being affixed to the first surface of the system planar and the second processor complex being affixed to the second surface of the system planar, such that the control logic chips of each of the processor complexes are located on opposite surfaces of the system planar, and adjacent edges of the control logic chips essentially align with one another on the opposite surfaces of the system planar to define an axis; and whereinan airflow traveling axially across both of the processor complexes in the same direction cools the processor complexes simultaneously on both surfaces of the system planar.