Patent ID: 6463057
Filing Date: 2002-10-08
Classification: H04J,H04L,H04Q

Abstract:
A band control method of a packet switching system including a buffer memory for storing fixed-length packets, an idle address memory for storing information corresponding to idle addresses of said buffer memory, and a control circuit for controlling said buffer memory and said idle address memory based on identifiers of said fixed-length packets, and which switches fixed-length packets input from a plurality of input lines into any lines of a plurality of output lines, comprising the steps of:temporarily storing information from said idle address memory for each of said identifiers when fixed-length packets are stored in said buffer memory based on said information from said idle address memory; designating an order of outputting fixed-length packets to said output lines for each of said identifiers of said fixed-length packets; and reading information stored temporarily in said order in accordance with said identifiers for each of said identifiers, reading fixed-length packets from said buffer memory in accordance with said information and storing said information to said idle address memory.