Patent ID: 7694109
Filing Date: 2010-04-06
Classification: G06F

Abstract:
1. A data processing apparatus comprising: an instruction memory in which an instruction is stored; a data memory in which data is stored; an instruction decoder decoding a fetched instruction; a memory operation unit coupled to said instruction memory, said data memory and said instruction decoder, fetching an instruction stored in said instruction memory, and accessing said data memory according to a decoded result of said instruction decoder; an integer operation unit carrying out an integer operation according to a decoded result of said instruction decoder; wherein; said instruction memory includes a plurality of instruction memory banks, wherein said instruction memory has a throughout of one clock cycle and a latency of two clock cycles; said memory operation unit generates a first pipeline cycle corresponding to selection of an instruction memory bank to be accessed in the immediate succeeding second pipeline cycle of fetching an instruction and the second pipeline cycle corresponding to an access to the instruction memory bank for fetching an instruction selected in the first pipeline cycle without any accesses to other instruction memory banks when a plurality of instructions are fetched continuously, wherein only the selected instruction memory bank is precharged to allow reduction of power consumption and wherein a precharging operation of the selected instruction memory bank is carried out in the first half of the first clock cycle; said memory operation unit reads out data from said data memory via a data input bus, and writes data into said data memory via a data output bus differing from said data input bus for executing a data read instruction and data store instruction continuously.