Patent ID: 6976127
Filing Date: 2005-12-13
Classification: G06F

Abstract:
1. A memory system, comprising: a memory cache responsive to a single processing unit, the memory cache arrangeable to comprise: a first independently cached area assigned to store a first number of data packets based on a first processing unit context; and a second independently cached area assigned to store a second number of data packets based on a second processing unit context; and a memory control system coupled to the memory cache, the memory control system configured to arrange the first independently cached area and the second independently cached area in such a manner that the first number of data packets and the second number of data packets coexist in the memory cache and are available for transfer between the memory cache and the single processing unit, wherein the single processing unit comprises a central processing unit (CPU), wherein the first processing unit context comprises a first CPU process and the second processing unit context comprises a second CPU process, and wherein the first independently cached area is configurable in such a manner that at least some of the first number of data packets are transferable from the first independently cached area in response to execution of the first CPU process by the single processing unit, and wherein the second independently cached area is configurable in such a manner that at least some of the second number of data packets are transferable from the second independently cached area in response to execution of the second CPU process by the single processing unit.