Patent ID: 9142320
Filing Date: 2015-09-22
Classification: G11C

Abstract:
1. A memory element comprising: a first inverter; a second inverter; a first capacitor comprising a first electrode and a second electrode; a first transistor; a second transistor; and a second capacitor, wherein an output terminal of the first inverter is electrically connected to an input terminal of the second inverter, wherein an output terminal of the second inverter is electrically connected to an input terminal of the first inverter, wherein one of a source and a drain region of the first transistor is electrically connected to the input terminal of the first inverter, wherein the other of the source and the drain region of the first transistor is electrically connected to the first electrode of the first capacitor, wherein the first transistor includes a first semiconductor region with at least one hollow portion in a first channel formation region, wherein the first transistor controls writing of data to the first capacitor, wherein one of a source and a drain region of the second transistor is electrically connected to the input terminal of the second inverter, and wherein the other of the source and the drain region of the second transistor is electrically connected to the second capacitor.