Patent ID: 7871872
Filing Date: 2011-01-18
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor, the method comprising: forming an amorphous silicon layer on a substrate; forming a polysilicon layer by crystallizing the amorphous silicon layer; forming an insulation layer on the polysilicon layer; forming a mask structure masking a portion of the polysilicon layer, wherein the mask structure comprises a gate mask and a photoresist layer which are sequentially deposited on the insulation layer; forming a source region and a drain region and a channel region interposed therebetween by injecting impurities having a first concentration using an ion beam implantation process into both end portions of the polysilicon layer which are not covered by the mask structure; exposing both end portions of the gate mask by shrinking the photoresist layer by shooting an ion beam to the photoresist layer using an ion beam implantation process; forming a gate electrode and a gate insulation layer having the same width as the shrunk photoresist layer by etching the gate mask and the insulation layer using the shrunk photoresist layer as an etch mask; and forming lightly doped drain (LDD) regions by injecting impurities having a second concentration lower than the first concentration using an ion beam implantation process into both end portions of the channel region which is exposed by the gate electrode and the gate insulation layer, wherein the forming of the source region and the drain region is performed prior to the exposing of the both end portions of the gate mask.