Patent ID: 6092116
Filing Date: 2000-07-18
Classification: G06F

Abstract:
A direct memory access (DMA) controller for transmitting and receiving formatted data frames having frame headers in a communications subsystem, the DMA controller comprising:a transmit data input and a transmit data output;transmit circuitry receiving transmit data frames on the transmit data input and applying the transmit data frames on the transmit data output through a transmit data path;a receive data input and a receive data output;receive circuitry receiving receive data frames on the receive data input and applying the receive data frames on the receive data output through a receive data path; anda response message table having an address input coupled to the receive circuitry, a data output coupled to the transmit data path of the transmit circuitry and a plurality of addressable memory locations for storing predetermined response data frames associated with particular ones of the receive data frames.