Patent ID: 7620462
Filing Date: 2009-11-17
Classification: G05B,H02M

Abstract:
1. A designing device of a robust digital controller, wherein said designing device realizes an integral type control system that is obtained by equivalently converting a system and is connected with a control target satisfying the following state equation 5 when an input h, a controlled variable y, a first equivalent disturbance q v , a second equivalent disturbance q v and a time-lag ξ 1 are given respectively: wherein aid system converted is formed by approximating a transfer function W ry (z) between a target value r and said controlled variable y when a state feedback rule and a feedforward rule are applied to said control target to determine a quadratic approximate model transfer function W m (z) shown in the following equation 6: (where z=exp (jωt); n 0 , n 1 , n 2 are zeros; and H 1 , H 2 , H 3 , H 4 are poles.) and then by combining the model transfer function W m (z), an inverse function W m (z) −1 of said model transfer function W m (z) and a dynamic compensator K(z) with characteristics, shown in the equation 7, for realizing the inverse function W m (z) −1 : said integral type control system, further comprising: a first feedback means configured to output a product of said controlled variable y and parameter k a second feedback means configured to output a product of said controlled variable y and parameter k a third feedback means configured to output a product of a first time-lag output ξ a fourth feedback configured to output a product of a second time-lag output ξ a fifth feedback means configured to output a product of a third time-lag output ξ a sixth feedback means configured to output a product of said controlled variable y and parameter k a first arithmetic means configured to calculate a difference between said controlled variable y and said target value r, an integrating means configured to integrate the calculated value from the first arithmetic means to covert the integrated value into a fourth time-lag output ξ a first accumulating means configured to output a product of a fourth time-lag output ξ a first adding means configured to add an output from said first accumulating means, an output from said fifth feedback means and an output from said sixth feedback means, a first time-lag means configured to output said third time-lag output ξ a second accumulating means configured to output a product of a third time-lag output ξ a third accumulating means configured to output a product of a third time-lag output ξ a second adding means configured to add said second equivalent disturbance q a second time-lag means configured to output said second time-lag output ξ a third adding means configured to add an output from said second time-lag means, an output from said third accumulating means and an output from said second feedback means to produce an input h to said control target, wherein each parameter is expressed as equation 8 when said state feedback rule F=[F(1,1) F(1,2) F(1,3) F(1,4)] and said feedforward rule G have been applied: wherein said designing device comprises: a parameter specifying means configured to specify pole values H an undetermined value calculating means configured to calculate each of undetermined values of a zero n a controller parameter determining means configured to calculate each of parameter values k a controller parameter outputting means configured to output each of the parameter values calculated by said controller parameter determining means to said robust digital controller.