Patent ID: 6034434
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A semiconductor wafer, having at least one integrated circuit, comprising:a substrate;a multiplicity of active conductive traces on the substrate of the wafer, the active conductive traces each being arranged to electrically couple associated elements of an associated integrated circuit on the wafer, there being gaps between adjacent ones of the traces;a multiplicity of additional elements on the substrate, wherein the additional elements are not arranged to electrically couple any elements in the integrated circuit, wherein the additional elements have at least one narrow surface dimension, the narrow surface dimension being in the range of approximately 1 to 5 micrometers; and,an insulating layer formed over the active conductive traces and the additional elements, the insulating layer having a multiplicity of sharp peaks formed therein, the insulating layer having a density of sharp peaks in the range of up to approximately 500,000 to 10 million sharp peaks per square centimeter.