Patent ID: 6573560
Filing Date: 2003-06-03
Classification: H01L

Abstract:
A trench MOS-gated device comprising:a substrate including an upper layer having an upper surface, said substrate comprising doped monocrystalline semiconductor material of a first conduction type; a gate trench in said upper layer, said trench having sidewalls and a floor lined with a first dielectric material and a centrally disposed core comprising a second dielectric material and extending upwardly from said first dielectric material on said trench floor to an interlevel dielectric layer disposed on said upper layer and overlying said gate trench, the remainder of said trench being substantially filled with a conductive material that encompasses and contacts said core of second dielectric material; a doped well region of a second conduction type overlying a drain zone of said first conduction type in said upper layer; a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type disposed in said well region at said upper surface, said source region being contiguous to said gate trench, said interlevel dielectric layer overlying said source region and said gate trench; and a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions.