Patent ID: 7719870
Filing Date: 2010-05-18
Classification: G11C,H01L

Abstract:
1. A storage device comprising: a first wiring layer formed above a substrate; a second wiring layer formed above the first wiring layer; a plurality of first lines formed in the first wiring layer; a plurality of second lines formed in the second wiring layer; and a plurality of memory cells formed between the first and second lines; wherein each of the plurality of memory cells includes a storage element and a selection element, wherein both of the storage element and the selection element in each of the memory cells are formed between a corresponding one of the first lines and a corresponding one of the second lines, wherein a current flows in a direction perpendicular to the substrate through the selection element of each of the memory cells, wherein a width, which is in a direction parallel to a surface of the substrate and parallel to an extending direction of the second lines, of the selection element is substantially the same as a width, which is in the direction parallel to the surface of the substrate and parallel to the extending direction of the second lines, of the storage element, wherein the selection element includes polysilicon, and the storage element includes chalcogenide.