Patent ID: 6930036
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A method for forming a multi-level interconnection structure in a semiconductor device, said method comprising the steps of: forming first level interconnections overlying a substrate; consecutively forming first and second dielectric films on said first level interconnections; consecutively forming first through third hard mask films on said second dielectric film, said first through third hard mask films being insulating films; selectively etching said second and third hard mask films to form a through-hole pattern on said second and third hard mask films; selectively etching said third hard mask film to form a trench pattern on said third hard mask film, said trench pattern partially overlapping said through-hole pattern; selectively etching said first hard mask film by using said second hard mask film as an etching mask to form said through-hole pattern on said first hard mask film; selectively etching said second dielectric film by using said first hard mask film as an etching mask to form first through-holes in said second dielectric film based on said through-hole pattern; selectively etching said first and second hard mask films and a top portion of said first dielectric film by using said third hard mask film as an etching mask to form trenches in said first and second bard mask films and said top portion of said second dielectric film based on said trench pattern; and selectively etching said first dielectric film to form therein second through-holes communicated with respective said first through-holes for exposing part of said first level interconnections through said first and second through-holes.