Patent ID: 6507925
Filing Date: 2003-01-14
Classification: G01R

Abstract:
A method for analyzing a scan dump, wherein said scan dump comprises contents of a shift register scan chain at a clock cycle within a plurality of clock cycles, said method comprising:assigning a first latch at a first register to a first defined value, said latch being within a chain of latches, wherein the shift register scan chain can receive the scan dump from said chain of latches, wherein a first scan in the shift register scan chain corresponds to said first register; comparing said first scan to said first defined value for determining equality or inequality in a comparison result; assigning a second latch at a second register to one of either a second defined value or a third defined value, said second latch corresponding to said second defined value prior to an event within the plurality of clock cycles, said second latch corresponding to said third defined value after said event, wherein a second scan in the shift register scan chain corresponds to said second register; and comparing said second scan to said third defined value to determine the clock cycle.