Patent ID: 7013321
Filing Date: 2006-03-14
Classification: G06F

Abstract:
1. A processing core that executes a parallel multiply accumulate operation, the processing core comprising: a first input operand register comprising a plurality of first input operands; a second input operand register comprising a plurality of second input operands; a third input operand register comprising a plurality of third input operands; a plurality of functional blocks that each perform a multiply accumulate operation, wherein an instruction for the multiply accumulate operation indicates a rounding algorithm to use, and the rounding algorithm is one of a plurality that can be indicated by various multiply accumulate instructions; an output operand register comprising a plurality of output operands, wherein each of the plurality of output operands is related to one of the plurality of first input operands, one of the plurality of second input operands and one of the plurality of third input operands.