Patent ID: 7773418
Filing Date: 2010-08-10
Classification: G11C

Abstract:
1. A memory array, comprising: a number of single level memory cells; a number of multiple level memory cells; and a first select gate directly coupled to a first single level memory cell, the first single level memory cell being directly coupled in series to a first multiple level memory cell of a continuous number of series coupled multiple level memory cells; a second select gate directly coupled to a second single level memory cell, the second single level memory cell being directly coupled in series to a second multiple level memory cell of the continuous number of series coupled multiple level memory cells; wherein the first and the second multiple level memory cells are located at opposite ends of the continuous number of series coupled multiple level memory cells; and wherein the second single level memory cell is programmed subsequent to programming a lower page and an upper page for each of the continuous number of series coupled multiple level memory cells.