Patent ID: 8610465
Filing Date: 2013-12-17
Classification: H03F

Abstract:
1. A comparator circuit, comprising: a fully differential main amplifier unit having a positive input terminal and a negative input terminal for receiving a differential input signal of the comparator circuit and a positive output terminal associated with a first branch of the main amplifier unit and a negative output terminal associated with a second branch of the main amplifier unit for outputting a differential output signal of the comparator circuit, the main amplifier unit comprising a control port adapted to control a bias current of the first branch of the main amplifier unit and/or a bias current of the second branch of the main amplifier unit in response to one or more control voltages supplied to the control port of the main amplifier unit; circuitry for balancing the voltages at the positive and negative input terminals of the main amplifier unit during a first clock phase of the comparator circuit; and a switched-capacitor accumulator unit with a differential input operatively connected to the positive and negative output terminals of the main amplifier unit for sampling voltages at the positive and negative output terminals of the main amplifier unit during the first clock phase, and operatively connected to the control port of the main amplifier unit for supplying said one or more control voltages; wherein the control port of the main amplifier unit comprises a first control terminal and a second control terminal, and the switched-capacitor accumulator unit has a first output terminal operatively connected to the first control terminal of the main amplifier unit and a second output terminal operatively connected to the second control terminal of the main amplifier unit; wherein the main amplifier unit comprises a differential input-transistor pair comprising a first input transistor in the second branch of the main amplifier unit connected to the positive input terminal of the main amplifier unit with its gate terminal and a second input transistor in the first branch of the main amplifier unit connected to the negative input terminal of the main amplifier unit with its gate terminal; and a differential control-transistor pair comprising a first control transistor connected to the first control terminal of the main amplifier unit with its gate terminal and operatively connected to one of the first and second branches of the main amplifier unit for controlling a bias current of the one of the first and the second branches of the main amplifier unit, and a second control transistor connected to the second control terminal of the main amplifier unit with its gate terminal and operatively connected to the other one of the first and second branches of the main amplifier unit for controlling a bias current of the other one of the first and the second branches of the main amplifier unit; wherein the differential control-transistor pair is arranged to receive a control current at a common node of the first control transistor and the second control transistor; wherein the switched capacitor accumulator unit comprises a regulator amplifier unit having a positive input terminal, a negative input terminal, a positive output terminal operatively connected to the first control terminal of the main amplifier unit, and a negative output terminal operatively connected to the second control terminal of the main amplifier unit; a first capacitor operatively connected between the positive input terminal and the negative output terminal of the regulator amplifier unit; a second capacitor operatively connected between the negative input terminal and the positive output terminal of the regulator amplifier unit; a third capacitor operatively connected to a reference voltage node at a first terminal of the third capacitor; a fourth capacitor operatively connected to the reference voltage node at a first terminal of the fourth capacitor; a first switch device operatively connected between the positive output terminal of the main amplifier unit and a second terminal of the third capacitor; a second switch device operatively connected between the negative output terminal of the main amplifier unit and a second terminal of the fourth capacitor; a third switch device operatively connected between the positive input terminal of the regulator amplifier unit and the second terminal of the third capacitor; a fourth switch device operatively connected between the negative input terminal of the regulator amplifier unit and the second terminal of the fourth capacitor; wherein the first and second switch devices are arranged to be closed during the first clock phase and open during a second clock phase, wherein the first clock phase and the second clock phase do not overlap; and wherein the third and fourth switch devices are arranged to be closed during the second clock phase and open during the first clock phase.