Patent ID: 8555124
Filing Date: 2013-10-08
Classification: G01R

Abstract:
1. A data processing apparatus comprising: combinatorial circuitry configured to receive at least one input signal and to perform a processing operation to generate an output signal; a first sequential storage structure, controlled by a first clock signal, and configured to provide said at least one input signal to the combinatorial circuitry; a second sequential storage structure, controlled by a second clock signal, and configured to latch the output signal generated by the combinatorial circuitry; the second sequential storage structure comprising a main storage element configured to latch a value of the output signal and to provide said value of the output signal to a subsequent combinatorial circuitry; and transition detection circuitry configured to detect a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct; the second sequential storage structure is configured to operate in one of a first mode of operation and a second mode of operation, wherein; the transition detection circuitry of the second sequential storage structure comprises a shadow storage element configured to latch a value of the output signal at a timing different to the main storage element, and state difference detection circuitry configured to determine, from a difference in the values latched by the main storage element and the shadow storage element, said approaching error condition whilst the value stored in the main storage element is still correct, wherein; in said first mode of operation, the shadow storage element is operated by the second clock signal and the main storage element is operated by a delayed version of the second clock signal, to cause the shadow storage element to operate ahead of the main storage element such that the approaching error condition detected by the state difference detection circuitry is said approaching setup timing error due to a propagation delay within the combinatorial circuitry; and in said second mode of operation, the main storage element is operated by the second clock signal and the shadow storage element is operated by the delayed version of the second clock signal, to cause the main storage element to operate ahead of the shadow storage element such that the approaching error condition detected by the state difference detection circuitry is said approaching hold timing error due to an increase in a skew between the first and second clock signals.