Patent ID: 6412099
Filing Date: 2002-06-25
Classification: G06F

Abstract:
An apparatus for converting logical connection information of a circuit comprising a clock tree synthesis, said apparatus comprising:a specific sequential circuit element detector which inputs first logical connection information in which connections among logical elements are described, a logical element library in which information as to whether each logical element is a sequential circuit element or a combinational circuit, information as to whether each terminal of each logical element is an input terminal or an output terminal, and information as to whether each terminal is a clock control terminal or not are included, and an output terminal list in which specific output terminals are described, and detects sequential circuit elements by using said first logical connection information, said logical element library, and said output terminal list, each of which has a clock control terminal connected to an output node of said clock tree synthesis, and an output terminal which is, directly or via a combinational circuit, connected to one of said specific output terminals; and a clock signal replacer which replaces an output node of said clock synthesis tree which is connected to the clock control terminal of each of the detected sequential circuit elements by an input node of said clock synthesis tree, and outputs second logical connection information of the circuit which is logically equivalent to said first logical connection information of the circuit.