Patent ID: 6753252
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method for fabricating a semiconductor device comprising the steps of:providing parallel gate structures formed on a substrate with spaces between the gate structures; blanket depositing a conductive material to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material; patterning a mask to remain over active area regions, the mask remaining over the spaces; removing the conductive material in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas; depositing a dielectric layer over the gate structures and over the contacts; forming holes down to the contacts; and connecting a conductive region to the contacts through the holes, wherein the conductive material includes polysilicon and the gate structures include dielectric caps and spacers formed from an oxide, and wherein the step of removing the conductive material includes etching polysilicon selective to the oxide of the caps and spacers of the gate structures.