Patent ID: 7995377
Filing Date: 2011-08-09
Classification: G11C

Abstract:
1. A semiconductor memory device functioning as a static memory cell, said semiconductor memory device comprising: a plurality of SOI transistors each including a well layer made up of a conductive layer and formed on a semiconductor substrate, a BOX layer made up of an insulation layer and formed on said well layer, a source layer and a drain layer that are formed on said BOX layer, a channel layer sandwiched between said source and drain layers, and a gate electrode formed on said channel layer with a gate insulation layer therebetween; a pair of drive transistors each made up of one of said plurality of SOI transistors and including a channel of a first conductive type and a source electrode that is connected to a ground line; a pair of load transistors each made up of one of said plurality of SOI transistors and including a channel of a second conductive type, a source electrode, and a drain electrode, said source electrode being connected to a first power supply line higher in potential than said ground line, said drain electrode being connected to one of said pair of drive transistors; and a pair of transfer transistors each made up of one of said plurality of SOI transistors and including a channel of said first conductive type, each transfer transistor being connected between a bit line for accessing said memory cell and a storage node for storing information; wherein a well layer in which one of said pair of drive transistors is formed and a well layer in which one of said pair of transfer transistors is formed are provided on a first common well layer; wherein said pair of load transistors are provided on a second common well layer; and wherein said first and second common well layers are electrically isolated from each other.