Patent ID: 6275430
Filing Date: 2001-08-14
Classification: G11C

Abstract:
A semiconductor memory device having a precharge structure, comprising:a global I/O line pair having a global I/O line and a complementary global I/O line;a data I/O buffer means, coupled to the global I/O line pair, for transmitting data inputted from an external circuit via the global I/O line pair and for outputting data transmitted via the global I/O line pair to the external circuit;a plurality of banks, coupled to the global I/O line pair, for storing data, said banks including:a first bank coupled to the global I/O line pair; anda second bank coupled to the global I/O line pair, wherein the second bank is located closer to the data I/O buffer means than the first bank is;a control signal generating means for generating a control signal, said control signal has a first level and a second level in a read operation and a write operation, respectively;a first precharge means located closely to said first bank, said first precharge means sensing a level transition of the global I/O line pair, to precharge the global I/O line pair in response to the control signal of the second level in the write operation; anda second precharge means located closely to said second bank, said second precharge means sensing a level transition of the global I/O line pair and precharging the global I/O line pair in response to an inverted signal of the control signal in the read operation.