Patent ID: 9184182
Filing Date: 2015-11-10
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: at least one data line, at least one scanning line, and a pixel cell defined by the data line and the scanning line, the pixel cell comprises an Indium Tin Oxide (ITO) thin film and at least one metallic layer below the ITO thin film, the ITO thin film electrically connects to the metallic layer via a through hole, the metallic layer comprises a gate metallic layer and a common-electrode metallic layer, the ITO thin film comprises a slit arranged between the ITO thin film and the through hole; a drain metallic layer; a slot arranged in the semiconductor layer and the doped semiconductor layer; wherein the slot passes through the drain metallic layer, the doped semiconductor, and a portion of the semiconductor layer; the pixel cell further comprises a passivating layer and an insulation layer being arranged above the common-electrode metallic layer in turn, and the common-electrode metallic layer and the gate metallic layer are arranged on the same layer; and