Patent ID: 6541824
Filing Date: 2003-04-01
Classification: H01L

Abstract:
An ESD protection circuit connected to a connection pad and to internal circuitry on a highly dense integrated circuit formed on a semiconductor substrate to improve protection from extreme voltage levels applied by an ESD voltage source to said integrated circuit chip through said connection pad, comprising:a plurality of MOS FET's, whereby each MOS FET has a source connected to a ground reference potential and a drain connected to the connection pad, whereby the sources of a pair of the MOS FET's are isolated by an isolating diffusion means having a conductivity opposite said sources, and said isolating diffusion means is electrically floating; a plurality of parasitic bipolar junction transistors, whereby each bipolar junction transistor comprises an emitter, a base, and a collector, wherein the source of the MOS FET's is the emitter, the drain of the one MOS FET is the collector and the channel region between the source and the drain is the base; a plurality of first bulk resistors, whereby each first bulk resistor is formed of the bulk resistance of the semiconductor substrate in proximity to the base of each MOS FET, wherein each of the first bulk resistors has a first terminal connected to the base of one of the parasitic bipolar junction transistors and a second terminal; and a plurality of second bulk resistors, whereby each second bulk resistor is formed of the bulk resistance of the semiconductor substrate not in proximity with the base of each MOS FET, and whereby each second bulk resistor has a first terminal connected to a junction of two of the second terminals of the first bulk resistors and a second terminal connected to the ground reference potential.