Patent ID: 8996812
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A computer implemented method for temporarily holding cache lines, the computer implemented method comprising: configuring a write-back cache between different processors and a main memory in a symmetric multiprocessor platform system, wherein the write-back cache is located in a memory controller and is associated with a coherency directory; storing and retaining, by the memory controller, responsive to a cache line in a cache of one of the different processors being ready to be written back to the main memory from the cache, the cache line in the write-back cache to delay writing the cache line back to the main memory for a designated period of time and associating the cache line with a “write back (W)” state in the coherency directory to indicate that writing back to main memory of the cache line is delayed for the designated period of time and the cache line is present in the write back cache; prior to the expiration of the designated period of time, receiving an access request from a requesting processor for the cache line; checking, responsive to receiving the access request prior to the expiration of the designated period of time and to determining that the cache line is not in any data caches of the different processors, checking the coherency directory to determine if the “write back (W)” state in the coherency directory indicates that writing back of the cache line to main memory is delayed and that the cache line is present in the write back cache; removing, responsive to a determination that the “write back (W)” state of the cache line indicates that writing back of the cache line to the main memory is being delayed and the cache line is present in the write-back cache the cache line from the write-back cache and forwarding the cache line to the requesting processor; and updating the cache coherency state of the cache line in the coherency directory based on the requesting processor's intended use of the cache line to form an updated cache coherency state of the cache line.