Patent ID: 6117691
Filing Date: 2000-09-12
Classification: G11C,H01L

Abstract:
A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate, comprising:incorporating doping impurities of a first type into the substrate to form a conductive substrate of a first conductivity type;implanting doping impurities of a second type in the conductive substrate of the first type to form a conductive channel of a second conductivity type;implanting doping impurities of said first type in the conductive channel of the second conductivity type to form a conductive channel of said first conductivity type for use as a gate junction region;implanting doping impurities of said second type on either side of the gate junction region to form plural conductive channels of said second conductivity type for use as a source junction region and a drain junction region; anddepositing an FEM gate unit over the gate junction region, including depositing a lower metal layer, a FE layer and an upper metal layer, wherein the FEM gate unit is sized on the gate junction region such that any edge of the FEM gate unit is a distance ""D"" from the edges of the source junction region and the drain junction region, where ""D"" is between about 50 nm and 300 nm.