Patent ID: 6098156
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A method of accessing data in a multiprocessor system including a plurality of processors and a memory, wherein the memory includes a plurality of memory locations, and wherein at least a first processor and a second processor each include a reservation indicator and a cache, each cache having a plurality of cache memory locations corresponding to the memory locations, the method comprising the steps of:(a) providing a Load And Reserve request from the first processor for at least one of the plurality of memory locations;(b) determining whether the second processor includes at least one of the plurality of cache memory locations corresponding with the at least one of the memory locations;(c) determining whether the second processor's reservation indicator is set, this determination being in response to the second processor including the at least one of the cache memory locations corresponding with the at least one of the memory locations; and(d) providing a first state indicating that the at least one of the cache memory locations of the second processor corresponding with the at least one of the memory locations is invalid, responsive to the reservation indicator of the second processor not being set.