Patent ID: 7181703
Filing Date: 2007-02-20
Classification: G06F

Abstract:
1. A method in a computer system for compiling a design for an integrated circuit, the method comprising: performing multiple compilations of the design using a series of values for each input parameter in a set of input parameters for the design, each input parameter corresponding to a controllable aspect of the design, to generate output values for one or more output metrics based on the series of values, each output metric corresponding to a variable parameter of the integrated circuit to be tracked or optimized during the compiling, the series of values including random values that are automatically selected for the multiple compilations, wherein performing multiple compilations includes using a static schedule pre-calculated by a tool to select the series of values for each input parameter to be used in the compilations; concluding the performing of multiple compilations when an output value for at least one of the output metrics reaches a pre-selected stopping criteria; and determining optimal values for the input parameters based on the multiple compilations, the optimal values operable to be used to synthesize the design.