Patent ID: 6255702
Filing Date: 2001-07-03
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a silicon semiconductor substrate having a gate electrode formed thereon through a gate dielectric film, the gate electrode containing at least polysilicon having a thickness of 100-200 nm;a titanium silicide film formed on the gate electrode;side wall spacers formed to a thickness of 150-200 nm on side walls of the gate electrode;source and drain regions formed to a depth of 120-200 nm in the surface layer on respective sides of the side wall spacers, the source and drain regions being of a conductivity type opposite to that of a channel region provided therebetween;regions formed to a depth of 50-70 nm having a junction shallower than that of the source and drain regions respectively formed in the surface layer beneath the side wall spacers; andtitanium silicide films respectively formed on the source and drain regions.