Patent ID: 9087779
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A wafer-level package device comprising: an integrated circuit chip having a surface; a pillar extending from the surface of the integrated circuit chip, the pillar having an end distal from the surface of the integrated circuit chip, the distal end of the pillar being located at a first height above the surface of the integrated circuit chip, the pillar configured to provide an electrical interconnection to the integrated circuit chip; an integrated circuit chip device, the integrated circuit chip device being configured upon the surface of the integrated circuit chip, the integrated circuit chip device having a surface distal from the surface of the integrated circuit chip, the distal surface of the integrated circuit chip device being located at a second height above the surface of the integrated circuit chip; a first solder contact and a second solder contact disposed upon the distal end of the pillar through a first solder mask opening and a second solder mask opening, respectively, the first and second solder contacts being located at a third height above the surface of the integrated circuit chip; and an encapsulation structure disposed over the surface of the integrated circuit chip, the encapsulation structure enclosing the pillar except for portions of the pillar underlying the first solder mask opening and the second solder mask opening, wherein the second height is less than at least one of: the first height and the third height.