Patent ID: 8981476
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a p-type semiconductor substrate; a first n-type well formed in the p-type semiconductor substrate with a first depth from a surface of the p-type semiconductor substrate; a second n-type well formed in the p-type semiconductor substrate with a second depth from the surface of the p-type semiconductor substrate, the second depth being smaller than the first depth; a first and a second p-type backgate regions formed in the first and the second n-type wells, respectively; a first and a second n-type source regions formed in the first and the second p-type backgate regions, respectively; a first and a second n-type drain regions formed in the first and the second n-type wells, respectively, at positions opposing to the first and the second n-type source regions, with the first and the second p-type backgate regions located in between; and field insulation films formed on the p-type semiconductor substrate, at positions between the first and the second p-type backgate regions and the first and the second n-type drain regions, respectively; wherein a first transistor with a low reverse voltage durability is formed in the first n-type well and a second transistor with a reverse voltage durability higher than that of the first transistor is formed in the second n-type well.