Patent ID: 6835971
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a semiconductor substrate; circuit elements which are formed on said semiconductor substrate to constitute an electrical circuit; a wiring layer which is formed on said semiconductor substrate and connected electrically to said circuit elements; an organic insulation film which is formed to cover said electrical circuit, while having an opening; a conductor layer which is formed by lamination on said organic insulation film and connected electrically to said wiring layer through said opening; and a bump electrode which is connected to said wiring layer by said conductor layer, wherein said electrical circuit includes a plurality of limiter circuits which are laid out by being scattered across said semiconductor substrate to produce an internal power voltage of a prescribed voltage, wherein each of said limiter circuits includes a transistor which operates to lower the voltage level of a power voltage which is put in from the outside through said bump electrode, and wherein at least part of said transistor is formed so as to be located just beneath the formation area of said bump electrode which is used in taking the power voltage.