Patent ID: 6340909
Filing Date: 2002-01-22
Classification: H03K,H03L

Abstract:
A method of operation in a phase interpolator circuit, the method comprising:generating a first current in relation to a control voltage using a current switch; generating a second current in relation to the first current using a first current mirror circuit; selectively steering the second current to a first selected node of first and second nodes to generate a first voltage transition at the first selected node, the second current being steered to the first node when a first input signal is in a first state and the second current being steered to the second node when the first input signal is in a second state; generating a third current in relation to a second control voltage, wherein the second control voltage is complementary to the first control voltage; generating a fourth current in relation to the third current using a second current mirror circuit; and, selectively steering the fourth current to a second selected node of the first and second nodes to generate a second voltage transition at the second selected node, the fourth current being steered to the first node when a second input signal is in the first state and the fourth current being steered to the second node when the second input signal is in the second state, wherein the second input signal is phase offset from the first input signal by a first phase angle.