Patent ID: 6800558
Filing Date: 2004-10-05
Classification: H01L

Abstract:
A method of forming a dual damascene structure for copper dual damascene processes, comprising:providing a substrate, said substrate having been provided with semiconductor devices structures, at least one point of electrical contact having been provided in said substrate, a layer of Inter Metal Dielectric (IMD) having been deposited over said substrate, at least one opening having been created through said layer of IMD, said at least one opening being aligned with said at least one point of electrical contact; depositing a layer of first material over said layer of IMD, filling said at least one opening; removing said layer of first material from said layer of IMD, thereby partially removing said first material from said at least one opening, creating at least one partial opening through said layer of IMD, said at least one partial opening having a first and a second cross section; baking said substrate for a period of time by applying an elevated temperature in a gaseous environment and under a pressure to said substrate; depositing a layer of second material over said layer of IMD, thereby filling said second cross section of said at least one partial opening; and patterning and etching said layer of second material, creating an opening through said layer of second material that aligns with said at least one partial opening created through said layer of IMD, removing said layer of second material from said second cross section of said at least one partial opening created through said layer of IMD.