Patent ID: 8539321
Filing Date: 2013-09-17
Classification: H03M

Abstract:
1. Apparatus for correcting at least one bit error within a coded bit sequence, the apparatus comprising: an error syndrome generator configured to determine an error syndrome of a coded bit sequence, wherein the error syndrome is derived by a multiplication of a check matrix (H) with the coded bit sequence, wherein the check matrix (H) comprises a first sub-matrix (H wherein at least a first predefined component or a second predefined component of each line of the first sub-matrix (H wherein the second sub-matrix (H wherein the third sub-matrix (H wherein either an XOR-sum of the first predefined components of all lines of the first sub-matrix (H wherein a result of a multiplication of the check matrix (H) and a test vector is equal to a result of a multiplication of the second sub-matrix and a resulting vector, wherein at least one component of the resulting vector comprises the second bit value; and a bit error corrector configured to correct a bit error within the coded bit sequence based on the determined error syndrome of the coded bit sequence.