Patent ID: 6775294
Filing Date: 2004-08-10
Classification: H04L

Abstract:
A time slot assigner for a communication system comprising:(a) means for receiving serial data on an input bus divided into frames of time slots; (b) means for converting the data of each time slot into parallel bytes corresponding to data channels; (c) means for storing each byte in a cycling frame memory at locations related to channel numbers of said data; and (d) means for subsequently reading selectable ones of said locations corresponding to time slot numbers of data on an output bus, assignment of said data being determined by (i) connecting the time slots from the input bus to the time slots on the output bus in order beginning with the first slot of each frame on the input bus, (ii) in the event step (i) does not result in constant delay of time slots within a frame of data between the input and the output bus, connecting the time slots from the input bus to the time slots on the output bus shifted one time slot later in time, and (iii) repeating step (ii) until there is constant delay of time slots within a frame of data between the input and the output bus.