Patent ID: 7683685
Filing Date: 2010-03-23
Classification: H03L

Abstract:
1. An apparatus for implementing a phase-locked loop, comprising: a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control means; detection means that generates counter control signals to indicate a current relationship between said primary clock signal and a reference signal, said detection means including a phase/frequency detector that generates either an up signal or a down signal based upon said counter control signals, said detection means also including a detector module that receives said up signal and said down signal and responsively generates either a count up signal or a count-down signal to said up/down counter; an up/down counter that updates a counter value in response to said counter control signals, said counter value being converted into said VCO control means for adjusting said voltage-controlled oscillator; and a digital-to-analog converter that transforms said counter value into said VCO control means for adjusting an operating frequency of said voltage-controlled oscillator.