Patent ID: 7038481
Filing Date: 2006-05-02
Classification: G01R,G11C

Abstract:
1. A method for generating a wafer level burn-in reliability curve, comprising: detecting a signal indicating a transition associated with one of a number m of cycles of burn-in testing of a wafer; storing a time stamp associated with the transition in nonvolatile memory in each integrated circuit (IC) die on the wafer; performing a built-in self test (BIST) to determine a current number of failures in the each IC die associated with the time stamp; storing the current number of failures in the each IC die associated with the time stamp in the nonvolatile memory in the each IC die; repeating the foregoing for at least one additional cycle of burn-in testing; and reading each time stamp and the current number of failures associated with the time stamp for each at least one additional cycle.