Patent ID: 8171222
Filing Date: 2012-05-01
Classification: G06F

Abstract:
1. A memory control apparatus disposed in a memory access system having a bus, a single storage unit with a bank structure, and a bus arbitrating unit which arbitrates data write requests to the storage unit from a plurality of data processing units connected to the bus, or a data read request from the storage unit does not cause contention, the memory control apparatus comprising: an access-request accepting means; and an access-request rearranging means, wherein the access-request accepting means accepts the access-request rearranging means rearranges at least sequential access requests accepted by the access-request accepting means in an order of banks of the storage unit within a range of access requests relating to either a data write request output from one of the data processing units or a data read request output therefrom to control an access control of the storage unit.