Patent ID: 9087584
Filing Date: 2015-07-21
Classification: G06F,G11C

Abstract:
1. A system comprising: system main memory, the system main memory including a first memory level of volatile memory and a second memory level comprising non-volatile memory, the first memory level being a near memory comprising one or more Dynamic Random Access Memory (DRAM) devices and the first memory level to include a cached subset of the second memory level, the second memory level being a far memory that is larger and slower in comparison with the near memory, wherein the system main memory is to be communicatively coupled to a processor separate from the system main memory, and wherein a size of the system main memory to be presented to an operating system (OS) is a size of the second memory level; and a two-level memory (2LM) controller to transfer data between the second memory level and the first memory level of the system main memory and the processor based on one or more OS requests.