Patent ID: 6313498
Filing Date: 2001-11-06
Classification: H01L

Abstract:
In a memory cell: a substrate having source and drain regions separated by a channel region, a floating gate having a thickness on the order of 100-1000 .ANG. and a rounded lateral edge positioned above portions of the source and channel regions with the rounded edge about midway between the source and drain regions, a control gate having a lower portion which is spaced laterally from the rounded edge of the floating gate and overlies a second portion of the channel region and an upper portion which overlies at least a portion of the floating gate, a gate oxide beneath the floating gate and the control gate, a tunnel oxide between the rounded edge of the floating gate and the lower portion of the control gate, an erase path between the rounded edge of the floating gate and the lower portion of the control gate with high voltage coupling between the source region and the floating gate, and a programming path between the channel region and the floating gate.