Patent ID: 6928003
Filing Date: 2005-08-09
Classification: G06F,G11C,Y02D

Abstract:
1. A semiconductor device comprising: a memory controller receiving commands from a CPU, and controlling a memory, wherein said memory, that is to be controlled, by said memory controller, has a memory bank and a plurality of cache memories, wherein said plurality of cache memories are allocated against said memory bank, wherein one of said plurality of cache memories is operated so as to not be subjected to a hit check operation from said memory controller, wherein when the hit check operation from said memory controller is a miss and data stored in one of said plurality of cache memories operated so as to be subjected to the hit check operation is written back to said memory bank, data is readout from said memory bank to said one of said plurality of cache memories operated so as to be not subjected to the hit check operation and the data stored in said one of said plurality of cache memories operated so as to be subjected to the hit check operation is written back to said memory bank.