Patent ID: 6507533
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including an array of memory cell blocks arranged in a matrix, each of said memory cell blocks including a plurality of memory cells arranged in a matrix, a plurality of subword lines each for specifying a row of said memory cells, and a plurality of data lines for specifying a column of said memory cells; a column address decoder block including a plurality of column address decoders each responding to a column address signal to specify a corresponding one of said data lines; a row address decoder block including a plurality of row address decoders each for responding to significant bits of a row address signal to generate a main word signal; a plurality of main word lines disposed corresponding to said address decoders for transferring said main word signal; a plurality of word line activation blocks including a plurality of word line activation decoders each for responding to a less-significant bit of said row address signal to generate a subword signal; a plurality of word line activation lines each disposed for a corresponding one of said word line activation decoders to transfer said subword signal; and a subword driver block for responding to said main word signal and said subword signal to specify one of said subword lines, wherein at least some of said word line activation blocks are disposed within the area of at least some of said row address decoder blocks.