Patent ID: 6704240
Filing Date: 2004-03-09
Classification: G11C

Abstract:
A predecoder control circuit comprising:a first inversion delay means for inverting and delaying a first control signal as much as a predetermined time; a first latch means for determining potential of a first node by inverting and latching an output signal of the first inversion delay means; a second inversion delay means for inverting and delaying the potential of the first node; a third inversion delay means for logically combining a second control signal and a third control signal and delaying the logically combined signal as much as a predetermined time; a second latch means for determining potential of a second node by inverting and latching an output signal of the third inversion delay means; a fourth inversion delay means for inverting and delaying potential of the second node; a switching means for adjusting potential of a third node in response to a fourth control signal and a clock signal; a third latch means for latching potential of the third node; a first logic means for logically combining an output signal of the second inversion delay means and an output signal of the third latch means and outputting a first predecoder control signal; and a second logic means for logically combining an output signal of the fourth inversion delay means and an output signal of the third latch means and outputting a second predecoder control signal.