Patent ID: 6258641
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of preventing latchup in complementary metal-oxide semiconductor (CMOS) transistors, comprising:providing a semiconductor wafer having a p-substrate;etching shallow trench isolation (STI) structures for isolation;forming an n-well on top of said p-substrate;forming, simultaneously with the previous step, a deep n-well on top of said p-substrate, said deep n-well touching said n-well;forming a p-well within said deep n-well;forming, simultaneously with the previous, step a buried p-well below one of said STI structures, said buried p-well located where said n-well and said deep n-well touch;creating P-MOS transistors in said n-well;creating N-MOS transistors in said p-well;implanting a p.sup.+ ground tab in said STI structure;implanting an n.sup.+ region in said deep n-well;contacting said p.sup.+ ground tab with said buried p-well;connecting said n.sup.+ region to a supply voltage; andconnecting said p.sup.+ ground tab to a reference voltage.