Patent ID: 8943449
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. A method of maintaining memory coherency in a memory subsystem of a functional verification system using a plurality of design abstractions, wherein the memory subsystem comprises a plurality of memory pages and a plurality of shadow memory pages, wherein each memory page of the plurality of memory pages is modeled in the first design abstraction used by the functional verification system, wherein each shadow memory page is an image of one of the plurality of memory pages and is modeled in the second design abstraction used by the functional verification system, and wherein each memory page of the plurality of memory cages is accessible to an agent in the first design abstraction using a first method and a second method, comprising: enabling a first method for the agent in the first design abstraction within a host workstation of the functional verification system to access the memory page; receiving an access request from an agent in the second design abstraction within an emulation hardware device of the functional verification system to access the shadow memory page; disabling the first method for the agent in the first design abstraction upon receipt of the access request; and enabling a second method for the agent in the first design abstraction to access the memory page upon receipt of the request.