Patent ID: 6597222
Filing Date: 2003-07-22
Classification: H03K

Abstract:
In an output driver circuit having a PMOS drive transistor and an NMOS drive transistor connected to an output line, a circuit for limiting conduction to an n-well of said PMOS drive transistor in the event of a power supply failure while said output line is connected to another circuit driving said output line, said circuit comprising:a first transistor connected between said power supply and said n-well to charge a parasitic capacitance of said PMOS drive transistor; a plurality of transistors connected to couple said n-well and a gate of said PMOS drive transistor to a voltage level of said output line, including: a first circuit for disconnecting a signal line input to said PMOS drive transistor; a second circuit coupled to the output line for controlling the signal line input to the gate of said PMOS drive transistor; wherein said plurality of transistors further includes: a second PMOS transistor having a gate connected to said power supply, a source connected to said n-well and a drain connected to said output line; a third PMOS transistor having a gate connected to said power supply, a source connected to said gate of said PMOS drive transistor, and a drain connected to said output line; wherein said first circuit comprises: a transfer gate transistor connected between the gate of said PMOS drive transistor and said signal line input for said PMOS drive transistor; and a fourth transistor (NMOS), connected to a gate of said transfer gate transistor and having a gate connected to said power supply, for turning off said transfer gate transistor upon a failure of said power supply.