Patent ID: 7662676
Filing Date: 2010-02-16
Classification: H01L

Abstract:
1. A manufacturing method of a thin film transistor array panel comprising: forming a gate line having a gate electrode on an insulating substrate; depositing a gate insulating layer and a semiconductor layer on the gate line in sequence; forming a drain electrode and a data line having a source electrode on the gate insulating layer and the semiconductor layer, the drain electrode being separate from the source electrode; and forming a pixel electrode connected to the drain electrode, wherein at least one step of the forming a gate line and the forming a data line and drain electrode comprises depositing a first conductive layer of a Mo-containing conductor, a second conductive layer of a Cu-containing conductor, and a third conductive layer of a Mo—N-containing conductor and patterning the first to third conductive layers, wherein the second conductive layer is disposed on the first conductive layer and the third conductive layer is disposed on the second conductive layer.