Patent ID: 6563760
Filing Date: 2003-05-13
Classification: G11C

Abstract:
A circuit for generating an internal command signal in a semiconductor memory device, the circuit comprising:a buffer for generating a plurality of internal control signals and internal address signals in response to external clock signal of a test equipment, a plurality of external control signals, and a plurality of address signals; a command signal decoder for composing the plurality of internal control signals and then generating a test mode enable signal and a reversed test mode enable signal in response to a flag signal for precharging all the bank of the plurality of internal address signals, and composing the reversed test mode enable signal and the plurality of internal control signals and then generating internal command signals of the semiconductor memory device; and an internal clock generating means for generating a first and second internal clocks when the test mode enable signal is enabled, and composing the test mode enable signal and one of the internal command signals of the semiconductor memory device and then generating a plurality of internal command control signals which synchronously respond to the first and second internal clock signals; wherein the command signal decoder compose the plurality of internal control signals and the reversed test mode enable signal and then generates the internal command signals of the semiconductor memory device, in response to the plurality of internal command control signals.