Patent ID: 6510976
Filing Date: 2003-01-28
Classification: B23K,H01L

Abstract:
A method for forming a flip chip semiconductor package, the method comprising the steps of:a) providing a patterned layer of metal conductors having a first surface, wherein the first surface has a pattern of interconnect locations thereon; b) forming a layer of passivation on the first surface of the patterned layer of metal conductors; c) providing a semiconductor die having a first surface with a pattern of pads thereon, wherein reflowable conductive deposits are disposed on the pads; d) selectively disposing a passivation cleaner; e) placing the semiconductor die on the patterned layer of metal conductors to form an assembly, wherein the reflowable conductive deposits abut portions of the layer of passivation, wherein the reflowable conductive deposits are adjacent the pattern of interconnect locations, and wherein the passivation cleaner adheres to the reflowable conductive deposits and the portions of the layer of passivation; and f) reflowing the assembly, wherein the passivation cleaner substantially removes the portions of the layer of passivation from the patterned layer of metal conductors, and wherein the reflowable conductive deposits form conductive interconnects between the pads on the semiconductor die and the interconnect locations on the patterned layer of metal conductors.