Patent ID: 7138818
Filing Date: 2006-11-21
Classification: G01R

Abstract:
1. An apparatus for coupling an integrated circuit tester to at least one integrated circuit die on a semiconductor wafer comprising: a substrate having a probe surface and a connector surface, said probe surface having an plurality of spring probes for making electrical connections to said die, and a plurality of electrical connections extending through said substrate between each of said plurality of said spring probes and said connector surface, wherein said spring probes provide vertical planarity compliance between approximately 4 mils and approximately 10 mils to accommodate differences in planarity between said substrate and one or more integrated circuit dice on said semiconductor wafer; a system board having a top surface and a bottom surface, and a plurality of electrical conductors extending between said top surface and said bottom surface, said conductors on said bottom surface for making an electrical connection to said electrical connections on said connector surface of said substrate; and an interface module providing circuitry for processing electrical signals passing between said integrated circuit tester and said at least one integrated circuit die, said interface module comprising means for establishing electrical connections between said circuitry and said electrical conductors on said top surface of said system board.