Patent ID: 6593177
Filing Date: 2003-07-15
Classification: H01L

Abstract:
A self-aligned method of forming a semiconductor memory array of memory cells in a semiconductor substrate, each memory cell including a floating gate having a sharp tip, said method including the steps of:forming a plurality of spaced apart isolation regions on said substrate, substantially parallel to one another in a first direction with an active region between each pair of adjacent isolation regions, each of said active regions comprising a first layer of insulating material on said semiconductor substrate, and a first layer of conductive material on said first layer of insulating material; forming a plurality of spaced apart masking regions of a masking material substantially parallel to one another in a second direction on said active regions and said isolation regions, said second direction being substantially perpendicular to said first direction; forming undercuts below said masking material along said second direction; forming a plurality of spaced apart first spacers of an insulating material, substantially parallel to one another in said second direction, each first spacer being adjacent and contiguous to one of said masking regions with a first region between each pair of adjacent first spacers, each first spacer crossing a plurality of alternating active and isolation regions; etching between pairs of first spacers in said first region, and through said conductive material; removing said masking material; and anisotropically etching said conductive material, effective to form a plurality of spaced apart floating gates, each of said floating gates having a sharp tip.