Patent ID: 6170032
Filing Date: 2001-01-02
Classification: G06F

Abstract:
A priority encoder circuit comprising: a plurality of inputs, each input receiving one of a signal of a first type that indicates the input has been selected and a signal of a second type that indicates the input has not been selected; a plurality of outputs, where the number of inputs equals the number of outputs and each input corresponds to one output; first circuitry electrically coupled to the inputs and outputs and operable to generate a predetermined signal at the output that corresponds to the input with a selected priority that is receiving the signal of the first type; wherein the first circuitry further comprises a plurality of bitslice circuits, wherein the number of bitslice circuits equals the number of inputs, each bitslice circuit electrically coupled to one of the plurality of inputs and one of the plurality of outputs; and wherein each bitslice circuit further comprises: a carry input; a carry output; and second circuitry coupled to the carry input, the carry output, the one of the plurality of inputs, and the one of the plurality of outputs, the second circuitry operable to generate the signal of the first type at the carry output and the one of the plurality of outputs when the one of the plurality of inputs receives the signal of the first type and the carry input receives the signal of the second type.