Patent ID: 6144224
Filing Date: 2000-11-07
Classification: G06F,H03K

Abstract:
A clock distribution network for very large scale integrated (VLSI) circuit comprising:a clock source generating a clock signal;first singly driven propagating means for routing the clock signal from the clock source, comprising:a first wire emanating from the clock source and carrying signals in a first direction, anda second wire proximate to said first wire and carrying signals in a direction opposite to said first direction and connected to an end of the first wire distal from the clock source;second symmetrically driven propagating means for receiving from the first propagating means the clock signal and propagating the clock signal to tapping points near circuit components, the second propagating means comprising:a third wire emanating from the first wire and carrying signals in a third direction, anda fourth wire proximate to said third wire and emanating from the second wire and carrying signals in a direction opposite to said third direction; anda two-input logic gate at each tapping point, each point being connected to the third and fourth wires of the second routing means, the clock signal being fed through the two-input logic gates at each tapping point to clock pins, the clock signal arrival time at the clock pins being approximately equal, minimizing clock skews.