Patent ID: 7301192
Filing Date: 2007-11-27
Classification: G11C,H01L

Abstract:
1. A DRAM cell pair, comprising: a trench memory cell comprising: a stack memory cell comprising: wherein the select transistors each have an active area; a first source/drain region coupled to a storage electrode of the respectively associated storage capacitor and formed as a doped region of a first conductivity type; a second source/drain region coupled to a bit line for transmitting an electric charge from/to the storage electrode and formed as a doped region of the first conductivity type; and a channel region configured to space the two source/drain regions apart from one another, and formed as a region that is not doped by the first conductivity type, and the dimensions of which define a channel length and a channel width of the select transistor; wherein the two active areas are formed in a semiconductor fin, which is formed as a section of the semiconductor substrate, which is delimited by trench isolator structures at two parallel sides, and at one end of which the trench capacitor is arranged; and wherein the two active areas are arranged one behind the other along a longitudinal axis of the semiconductor fin and are formed in mirror-image fashion with respect to one another, the two source/drain regions of the two select transistors forming a cohesive bit contact terminal region.