Patent ID: 6590809
Filing Date: 2003-07-08
Classification: G11C

Abstract:
A non-volatile semiconductor memory device in which memory cells, each having a memory transistor storing information of two bits by using two edges of a dielectric layer positioned between a gate and a channel as two trapping storage regions, arranged in columns and rows in a matrix, comprising:a plurality of word lines; a plurality of first bit lines; and a plurality of second bit lines, wherein the memory transistors of the memory cells in each row have gates connected to an associated word line, the memory transistors of the memory cells in each column have first diffusion regions connected to an associated first bit line and second diffusion regions connected to an associated second bit line, the memory cells in an m-th column (m: odd number) and the memory cells of an (m+1)th column are connected to a same second bit line, a sense amplifier which detects a voltage is connected to said first bit line, information of a bit stored at the edge of said dielectric layer on said second bit line side is read by using said second bit line as a source, using said first bit line as a drain, and detecting a drain voltage, and information of a bit stored at the edge of said dielectric layer on said first bit line side is read by using said second bit line as a drain, using said first bit line as a source, and detecting a source voltage.