Patent ID: 6511883
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A method of fabricating a CMOS sensor wherein the CMOS sensor comprises a diode and a NMOS transistor, the method comprising:forming an isolation region in a substrate to form a diode region and a NMOS region; forming a P-well extending into the substrate; forming a stacked polysilicon structure over the substrate and the isolation region; forming a mask layer having an opening thereon on the stacked polysilicon structure; implanting ions into the P-well to form an N-doped region in the diode region extending shallowly into the substrate, the stacked polysilicon structure serving as an implantation buffer layer; removing the mask layer; patterning and etching the stacked polysilicon structure to form a stacked polysilicon ring surrounding the N-doped region partially covering the isolation region and edges of the N-doped region adjacent to the isolation region; forming the NMOS transistor on the NMOS region; and forming a metal line for electrically connecting the stacked polysilicon ring with a gate of the NMOS transistor.