Patent ID: 6163875
Filing Date: 2000-12-19
Classification: G01R

Abstract:
Semiconductor testing equipment for testing integrated circuits, the testing equipment comprising:a timer that is set to a specified time interval;comparison circuits that compare previously-stored data with data output from a respective one of a plurality of integrated circuits, and output a comparison signal based on the comparison;a decision timing circuit that determines when a specified time interval has elapsed or when all the comparison signals indicate acceptable products before the specified time interval has elapsed, and provides a timing signal when at least one of those events occurs;a decision circuit that performs data processing of the comparison signals in response to the timing signal;a changing circuit that is interposed between said comparison circuits and said decision timing circuit, and that outputs a signal indicating a defective semiconductor device to the decision timing circuit, wherein the signal output by the changing circuit is interpreted as an acceptable product signal; anda mask control circuit that, during subsequent testing, outputs a comparison signal corresponding to the defective semiconductor device as a dummy signal, and based on the dummy signal, said changing circuit outputs to said decision timing circuit a comparison signal for the defective semiconductor device that is interpreted as an acceptable product signal.