Patent ID: 8084768
Filing Date: 2011-12-27
Classification: G11C,H01L,H03K

Abstract:
1. A memory device comprising: a semiconductor substrate; a variable electrical conductivity switch element comprising a via connecting a wire in a first interconnection layer to a wire in a second interconnection layer, the via including a member having a variable value of electrical conductivity, wherein the wire of the first interconnection layer is a first terminal of said switch element and the wire in the second interconnection layer is a second terminal of said switch element, and wherein a connection between said first and second terminals is variably set to a shorted state, an open circuit state, and a state between said shorted and open circuit states; and at least a memory cell including said switch element and a transistor arranged on the semiconductor substrate, wherein one of said first and second terminals of said switch element is connected to one of the source and the drain of said transistor, the other of said first and second terminals is connected to one of a bit line and a plate line, the other of the source and the drain of said transistor is connected to the other of said bit line and the plate line, and the gate terminal of said transistor is connected to a word line, and wherein said switch element is arranged above said transistor, wherein said variable electrical switching element includes an electrolyte material, said electrolyte material includes a sulfide of one or more elements selected from the group consisting of copper, silver, chromium, tantalum, tungsten and mixtures thereof.