Patent ID: 6836148
Filing Date: 2004-12-28
Classification: H03K

Abstract:
An output buffer apparatus, comprising:an input for receiving input signaling having an input voltage swing between a reference voltage and an input voltage; an output for providing output signaling having an output voltage swing between said reference voltage and an output voltage that is greater than said input voltage; a level shifter coupled to said input for receiving said input voltage signaling, said level shifter including an input for receiving an intermediate voltage having a predetermined relationship relative to said output voltage, said level shifter responsive to said intermediate voltage for translating said input signaling into intermediate signaling having an intermediate voltage swing between said intermediate voltage and said output voltage; an intermediate voltage generator having an input for receiving said output voltage, said intermediate voltage generator coupled to said level shifter and responsive to said output voltage for providing said intermediate voltage to said level shifter, said intermediate voltage generator responsive to a change in said output voltage for automatically adjusting said intermediate voltage to maintain said predetermined relationship thereof relative to said output voltage; and an output stage coupled between said level shifter and said output for translating said intermediate signaling into said output signaling.