Patent ID: 6174803
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A method of integrated circuit manufacture, comprising:providing a number of electronic components along a semiconductor substrate, and a first connection layer comprised of a first dielectric and a first number of conductors in selective electrical contact with the components;forming a first insulative layer on the first connection layer with a first pattern of openings therethrough;establishing a second connection layer comprised of a second dielectric and a second number of conductors selectively interconnecting the first conductors through the first pattern of openings;forming a second insulative layer on the second connection layer with a second pattern of openings therethrough; andestablishing a third connection layer on the second insulative layer comprised of a third dielectric and a third number of conductors selectively interconnecting the second conductors, the third dielectric being etch selective to the second insulative layer, the second and third conductors being in contact with the second insulative layer, and at least one of the second conductors crossing at least one of the third conductors and being electrically isolated therefrom by the second insulative layer.