Patent ID: 8835250
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: depositing a dielectric layer on an interior surface of a cavity in a silicon-on-insulator structure, wherein the silicon-on-insulator structure comprises a first silicon layer, an insulator layer disposed on the first silicon layer; a second silicon layer disposed on the insulator layer, and a nitride layer disposed on the second silicon layer; forming a capacitor electrode in a lower portion of the cavity; forming a polysilicon plug on the capacitor electrode, wherein the polysilicon plug is in direct physical contact with both sides of the cavity; forming a first oxide region on the polysilicon plug; planarizing the first oxide region to the nitride layer; removing the nitride layer; forming a second oxide region, wherein the second oxide region is disposed over, and in direct physical contact with the first oxide region and in direct physical contact with the second silicon layer; and forming a finFET, said finFET comprising a plurality of fins and a gate electrode, said gate electrode disposed over a portion of the plurality of fins, wherein the gate electrode of the finFET is in direct physical contact with the first oxide region in an upper portion of the cavity.