Patent ID: 9000572
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A semiconductor package comprising: a package substrate; a first semiconductor chip stacked on the package substrate, the first semiconductor chip including a first region and a second region and having a top surface and bottom surface; at least a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a first region and a second region and having a bottom surface facing the top surface of the first semiconductor chip; a first plurality of conductive plugs disposed in the first region of the first semiconductor chip; and a first plurality of conductive connectors disposed between the first plurality of conductive plugs and the second semiconductor chip to electrically connect the first semiconductor chip with circuitry of the second semiconductor chip, wherein the first region of the first semiconductor chip corresponds to a respective first region of the second semiconductor chip and the second region of the first semiconductor chip corresponds to a respective second region of the second semiconductor chip, wherein circuitry of the second region of the second semiconductor chip is electrically connected to the first semiconductor chip only through conductive connectors corresponding to the first region of the first semiconductor chip and the first region of the second semiconductor chip, and wherein the second region of the second semiconductor chip is warped such that the bottom surface of a second semiconductor chip portion at the first region of the second semiconductor chip between at least two of the conductive connectors is substantially parallel to the top surface of the first semiconductor chip at the first region of the first semiconductor chip, and the bottom surface of a second semiconductor chip portion at the second region of the second semiconductor chip is not substantially parallel to the top surface of the first semiconductor chip at the second region of the first semiconductor chip; and wherein the circuitry of the second region is not electrically connected to terminals at a bottom surface of the second semiconductor chip in the second region of the second semiconductor chip.