Patent ID: 6725341
Filing Date: 2004-04-20
Classification: G06F

Abstract:
A shared memory multiprocessor computer system, comprising:a plurality of processors; a bus linking the plurality of processors; a plurality of local caches; a cache invalidation history table associated with each local cache; and a cache controller associated with each local cache, each cache controller operable to track invalidated cache lines by recording the line addresses of invalidated cache lines and an indicator indicating whether each of the invalidated cache lines recorded was invalidated via a clean-invalidate or a dirty-invalidate in the invalidation history table, and further operable to revalidate only those invalidated cache lines recorded in the invalidation history table as having been clean-invalidate invalidated by monitoring the bus for cache line addresses of clean-invalidate invalidated cache lines recorded in the invalidation history table and for associated cache line data and by updating the invalidated cache line data with the cache line data associated with the recorded cache line addresses.