Patent ID: 6542016
Filing Date: 2003-04-01
Classification: H03K

Abstract:
A binary digital logic level sensitive latch including:a first inverter providing an output (O1) and having at least one input signal (I1) and an activation signal (Clk) both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter and the capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal: O1={overscore (I1+Clk)}a second inverter providing an output (O2) and having as capacitively coupled inputs the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) and a switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of: O2={overscore ((ClkÃ—P)+O1)}; and a third inverter the input of which is the output (O2) of the second inverter, and the output of the third inverter is the inverted pervious output signal (P).