Patent ID: 6157560
Filing Date: 2000-12-05
Classification: G11C

Abstract:
An interconnection structure for an integrated circuit that includes at least one memory array, wherein each memory array is partitioned into a plurality of segments, and wherein each segment is associated with at least one bit line, the structure comprising:N local data lines associated with each memory array, wherein at least one local data line is associated with each segment of the memory array, and wherein each local data line operatively couples to one or more of the at least one bit line;N global data lines operatively coupled to the N local data lines of each of the at least one memory array;M global I/O lines; anddatapath coupled to the M global I/O lines and the N global data lines, wherein the datapath includes a plurality of multiplexer circuits operative to selectively interconnect the M global I/O lines to the N global data lines in accordance with a set of control signals.