Patent ID: 8102688
Filing Date: 2012-01-24
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: first through mth substrates, wherein m is a natural number greater than 1; first through nth stacked memories spaced apart and connected to each of the first through mth substrates, each of the first through nth stacked memories including an interface chip that is connected to the respective substrate and further including a plurality of memory chips stacked on the interface chip, wherein n is a natural number; and a controller for controlling the first through nth stacked memories connected to each of the first through mth substrates, wherein each interface chip of the first through nth stacked memories is connected to a neighboring one of the interface chips of the first through nth stacked memories, wherein the controller is connected to the interface chip of the first stacked memory of the first substrate, and the controller is connected to the interface chip of the nth stacked memory of the first substrate, wherein a kth one of the interface chips transmits a signal including at least one of command and data to a k+1th interface chip connected to the same substrate, wherein k is a natural number that is equal to or greater than 1 and is less than or equal to n−1, and wherein the controller transmits the signal to the first one of the interface chips connected to the first substrate and receives read data from the nth interface chip connected to the first substrate.