Patent ID: 7536589
Filing Date: 2009-05-19
Classification: G06F

Abstract:
1. A processing apparatus comprising: a plurality of operation units having a same operating function, each of which performs a given operation for an input operand in accordance with an operating instruction and outputs an exception flag when a result of the operation is false; a storage unit which stores the operand; a first network which connects the storage unit and the operation units and supplies the operand to the operation units; a second network which connects the operation units and the storage unit to write the result of the operation of each of the operation units back to the storage unit; a defect sensor which receives the exception flag from each of the operation units to sense an operation unit from which the exception flag is generated with high frequency, wherein the defect sensor includes a logic unit controller which controls the first network and the second network to disconnect the operation unit sensed by the defect sensor from a system, and causes another operation unit to perform an operation assigned to the disconnected operation unit again.