Patent ID: 6740978
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A semiconductor chip package comprising:at least a semiconductor chip; at least a chip carrier having a front surface to which said chip is attached, and having a back surface, at least a via, and a plurality of edges; at least a bonding finger formed on the front surface of said chip carrier to electrically connect said chip; at least a metal pad attached to the back surface of said chip carrier; at least a first conduction line formed on the front surface of said chip carrier to connect said bonding finger and said metal pad through said via; and at least a second conduction line formed on the front surface of said chip carrier, with a first end thereof on an edge of said chip carrier, and a second end thereof connecting said first conduction line and electrically connecting to said bonding finger through at least a part of said first conduction line, wherein said at least a part of said first conduction line is between said bonding finger and the second end of said second conduction line, said second conduction line and said at least a part of said first conduction line are for conducting to said bonding finger the electrical current applied to the first end of said second conduction line for plating material on said bonding finger.