Patent ID: 6807120
Filing Date: 2004-10-19
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a first region having a plurality of first bit lines, a plurality of first word lines and a plurality of first memory cells; a second region having a plurality of second bit lines, a plurality of second word lines and a plurality of second memory cells; a third region having a plurality of sense amplifiers placed between said first region and said second region; a first conductive layer being over said first region; a second conductive layer being over said second region; and a connecting layer, being over said third region, which electrically connects said first conductive layer with said second conductive layer, wherein said sense amplifiers amplify differences in voltage between said first bit lines and said second bit lines, wherein each of said first memory cells includes a first storage capacitor having an electrode connected to said first conductive layer, and wherein each of said second memory cells includes a second storage capacitor having an electrode connected to said second conductive layer.