Patent ID: 8161428
Filing Date: 2012-04-17
Classification: G06F,Y02P

Abstract:
1. A method for predicting a reliability of a semiconductor device in which an early-life failure of the semiconductor device is predicted, the method comprising: calculating a defect density for each of wiring patterns, by using a computer; extracting a critical area for each of library elements including the wiring patterns based on the defect density for each of the wiring patterns; calculating a critical area value for each of the library elements from the critical area for each of the library elements; calculating an expected value of a defect occurrence for each of the wiring patterns from the defect density for each of the wiring patterns; determining a failure probability for each of the wiring patterns from a result of a reliability test for each of the wiring patterns; forming a model based on the failure probability for each of the wiring patterns and the expected value of defect occurrence for each of the wiring patterns; calculating a failure probability for each of the library elements from the critical area value for each of the library elements and a function of the model; designing a layout of the semiconductor device with a plurality of the library elements combined together; and calculating a reliability of the semiconductor device based on the failure probability for each of the library elements combined together, wherein the reliability test of each of the wiring patterns as time elapses is conducted by using a test structure for forming the result of the reliability test, and wherein the model is represented by a function γ (t) in equation where F(t) is the failure probability for each the wiring patterns, and λ is the expected value of the defect occurrence.