Patent ID: 7919991
Filing Date: 2011-04-05
Classification: H03K

Abstract:
1. A comparator circuit for comparing first and second binary numbers A and B each having a number N of bits, comprising: a single-bit comparison stage having a plurality of input pairs each for receiving a corresponding bit A a resolution stage having a plurality of first inputs to receive the single-bit equality signals, a plurality of second inputs to receive the single-bit greater than signals, having a first output to generate an output equality signal EQ a first PMOS transistor coupled between a voltage supply and a first output node and having a gate to receive a clock signal; a second PMOS transistor coupled between the voltage supply and a second output node and having a gate to receive the clock signal; first and second NMOS transistors coupled in series between the first output node and a discharge node and having gates to receive the corresponding bits A third and fourth NMOS transistors coupled in series between the first output node and the discharge node and having gates to receive the corresponding bits !A a fifth NMOS transistor coupled between the second output node and an intermediate node between the first and second NMOS transistors having a gate to receive !B