Patent ID: 7890843
Filing Date: 2011-02-15
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising an error detection and correction system with an error correcting code over Galois field GF(2 n ), wherein the error detection and correction system includes an operation circuit configured to execute addition/subtraction with modulo 2 the operation circuit includes a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where M and N are integers, which are prime with each other as being obtained by factorizing 2 the first and second operation parts each comprises an adder circuit, which is configured to output a sum of two numbers to-be-added as a remainder of modulus thereof, and wherein the adder circuit includes a correction circuit for adding a complement to the sum when it becomes modulus number thereof or more.