Patent ID: 9189394
Filing Date: 2015-11-17
Classification: G06F,H04N

Abstract:
1. An accelerator processing unit comprising: a plurality of computational elements each adapted to execute instructions on input data to provide output data; a plurality of memory elements storing compressed data and inter-communicating with a first set of the computational elements through associated memory channels to provide input data thereto and receive output data therefrom wherein the memory elements include blocks storing input data and output data; a compressor/decompressor associated with each memory channel between a memory element and a connected computational element to decompress the compressed data stored in the memory element for reading by the computational element and to compress data written by the computational element for storage in the memory element as the compressed data; a compression table storing for each block, compression data providing an indication of whether the data of the block is compressed and an amount of compression; wherein the compressor/decompressor uses the compression data to determine an amount of data to read from the block being different from a size of the block; further including at least one memory cache associated with each memory channel for caching a compression table; and wherein the compressor/decompressor uses compression data from the cache and, in an event of a cache miss of compression data for a given block, reads an entire given block while waiting for the cache miss to be resolved.