Patent ID: 6156594
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A method for fabricating an integrated circuit including complementary MOS transistors and a bipolar transistor of NPN type, including the following steps:forming an N-type epitaxial layer on a P-type substrate, a buried layer being provided at least at a location where the bipolar transistor is formed,forming a thick oxide layer at locations other than locations of the MOS transistors, a collector region of the bipolar transistor and a base-emitter region of the bipolar transistor,forming parts of the MOS transistors,covering an entire structure with a protection layer including a first layer of silicon oxide and a first layer of silicon nitride,forming an opening in the protection layer at a base-emitter region of the bipolar transistor,depositing a first P-type doped layer of polysilicon or amorphous silicon, a second layer of silicon nitride and a second layer of oxide in the opening,forming an opening in the first p-type doped polysilicon layer or the silicon layer, second layer of silicon nitride, and second layer of oxide at a center of the emitter-base region,diffusing dopants contained in the first silicon layer in the underlying epitaxial layer to form an extrinsic base of the bipolar transistor,forming an N-type collector by implantation,implanting a P-type dopant to form an intrinsic base of the bipolar transistor,depositing a third silicon nitride layer, depositing a second layer of polysilicon, anisotropically etching the second polysilicon layer to form spacers over vertical portions of the base-emitter region and to expose a part of the third nitride layer, and removing the exposed part,depositing a third N-type doped polysilicon layer in the base-emitter region and diffusing dopants to form an emitter region of the bipolar transistor,depositing a planarized insulating layer, andperforming metallizations.