Patent ID: 9058130
Filing Date: 2015-06-16
Classification: G06F,Y02D

Abstract:
1. A wide bandwidth resonant clock distribution comprising: a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit; and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, wherein the tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode, wherein the tunable sector buffer receives an enable signal and the clock signal, wherein the tunable sector buffer comprises a NOR gate that receives the clock signal and an inverted enable signal and provides output to a first inverter, wherein the tunable sector buffer further comprises a NAND gate that receives the clock signal and the enable signal and provides output to a second inverter, wherein the tunable sector buffer further comprises a first transistor and a second transistor connected in series, wherein a gate node of the first transistor connects to an output of the first inverter and a source node of the first transistor connects to a first reference voltage, wherein a gate node of the second transistor connects to an output of the second inverter and a drain node of the second transistor connects to a second reference voltage, and wherein a drain node of the first transistor connects to a source node of the second transistor, wherein the source node of the second transistor provides an output of the tunable sector buffer; and wherein the tunable sector buffer further comprises a plurality of first transistor fingers of the first transistor and a plurality of second transistor fingers of the second transistor.