Patent ID: 6958275
Filing Date: 2005-10-25
Classification: H01L

Abstract:
1. A method of forming a power MOSFET comprising: (a) providing a layer of a second conductivity type on a first surface of a substrate of a first conductivity type with a pn junction there between; (b) forming pedestals in the first surface by masking and directionally etching between pedestals through the layer of the second conductivity type and into the substrate, the pedestals having source regions of the first conductivity type in the sides of the pedestals in the layer of the second conductivity type; (c) forming a thin oxide layer on the surfaces of the pedestals and on the substrate between pedestals; (d) forming gate regions on the sides of the pedestals spanning the pn junction and a part of the adjacent source regions of the pedestals; (e) forming a first interconnect layer in the regions between pedestals in electrical contact with the gate regions and isolated from electrical contact with the source regions, the second conductivity type regions of the pedestals and the substrate by the thin oxide layer; (f) forming an electrically insulative layer over the first interconnect layer, the insulative layer leaving a part of the source regions on the pedestals, and the thin oxide layer thereon, exposed; (g) removing the thin oxide layer left exposed in (f); and, (h) forming a second interconnect layer over the insulative layer and in electrical contact with the source regions left exposed in (g); (c) through (h) being performed without masking to form the power MOSFET in accordance with the method claimed.