Patent ID: 7538569
Filing Date: 2009-05-26
Classification: G01R,G06F,G11C

Abstract:
1. A method for testing an integrated circuit, the integrated circuit including two or more operational blocks fabricated in a substrate, comprising: (a) determining a maximum operating speed of each of the operational blocks at a minimum supply voltage and no well bias; (b) selecting an operational block that has a slower operating speed than at least one other operational block; (c) selecting a well bias to speed up the selected operational block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power with the selected well bias applied to the selected operational block and the selected supply voltage applied to the integrated circuit; (e) repeating acts (b)-(d) while the measured power is less than a baseline power that meets the target operating frequency with no well bias applied to the operational blocks; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.