Patent ID: 9165669
Filing Date: 2015-10-20
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: a memory cell array comprising a memory block having a plurality of strings and a plurality of word lines, wherein the plurality of strings include a corresponding plurality of pillars that are tapered in a direction of the plurality of strings, and a plurality of memory cells are formed at intersections of the tapered pillars and the word lines, respectively, such that electrical characteristics of the plurality of memory cells vary according to structural locations of the memory cells with respect to the tapered pillars; a voltage generating circuit configured to generate a selection voltage and a plurality of zone voltages, the selection voltage being applied to a selected word line of the plurality of word lines in the memory block during a program operation or a read operation, and the plurality of zone voltages being applied to a plurality of zones, each zone comprising at least one unselected word line; and an address decoder configured to transfer the selection voltage to the selected word line and the zone voltages to the zones of the unselected word lines, respectively, wherein the zones are determined, at least in part, according to the structural locations of the memory cells of each of the unselected word lines, respectively, with respect to the tapered pillars, wherein the plurality of zone voltages generate optimal program pass voltages or optimal read pass voltages respectively corresponding to the plurality of zones, and wherein the optimal program pass voltages and the optimal read pass voltages are determined, at least in part, by proximity of the at least one unselected word line in each zone to the selected word line.