Patent ID: 6094375
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of memory cell arrays in rows and columns, synchronized with an external clock, comprising:a core portion for inputting and outputting data to and from the memory cell arrays according to a group of column addresses in a single data rate (SDR) mode, and inputting and outputting first data and second data to and from the memory cell arrays and first and second global data lines, respectively, according to the group of column addresses excluding a predetermined column address in a double data rate (DDR) mode;first and second data lines for outputting and receiving data to and from the outside;a transferring portion for controlling the transferring of data between the core portion and the first and second data lines in response to the predetermined column address; andan input and output controller for, in the DDR mode, transforming data of the first and second data lines into serial data and outputting the serial data to the outside, and transmitting data serially received from the outside to the first and second data lines in response to rising and falling edges of the external clock signal.