Patent ID: 8003504
Filing Date: 2011-08-23
Classification: H01L

Abstract:
1. A method for providing a field effect transistor with an integrally formed field plate in a process that preserves a critical gate dimension to increase the transistor output power, comprising the steps of: protecting an upper surface of a field effect transistor at a gate region from a subsequent etching step by overlying the gate region with a precisely patterned metal gate layer having a critical gate dimension on the upper surface at the gate region thereof such that device performance is uniform and consistent regardless of the subsequent etching step, the metal gate layer being formed using a first lithographical pattern, with thin metal gate layer defining the critical gate, dimension including gate lengths; depositing a dielectric passivation layer over a semiconductor surface and the metal gate layer; defining a second lithographical pattern on the dielectric passivation layer coincident with or slightly inset from the boundaries of the metal layer; etching the dielectric passivation layer using a dry or wet etching technique to open up a window above the thin metal gate layer without disturbing the critical gate dimension on the upper surface of the gate region; providing a third lithographical pattern over the etched dielectric passivation layer to define a thick metal gate and a field plate integral thereto; and, depositing metal in the window to form a gate and field plate, whereby the field effect transistor is provided with the advantage of an integrally formed field plate, whereby the critical gate dimension of the portion of the gate contacting the semiconductor surface is preserved by the original precise patterning of the thin metal gate layer, and whereby the semiconductor surface at the gate is protected from the etching step.