Patent ID: 6147919
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory cells arranged in arrays;a plurality of direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed;a plurality of column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed;a plurality of write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto; andlocal drivers, wherein:the sense amplifiers are grouped, in each row, into sense amplifier blocks;the write-only column selection lines include first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write, and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks; andthe local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines.