Patent ID: 8027420
Filing Date: 2011-09-27
Classification: G06F,H04L

Abstract:
1. A circuit for transferring a signal from a fast clock domain to a slow clock domain comprising: a fast clock domain configured to receive an input signal and, responsively, transfer an intermediate signal, a slow clock domain configured to receive the transferred intermediate signal from the fast clock domain and, responsively, generate an output signal, and a first synchronizer disposed in the slow clock domain, and a second synchronizer disposed in the fast clock domain, wherein the first synchronizer, operating with a slow clock, is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal, the second synchronizer, operating with a fast clock, is configured to receive a feedback signal from the first synchronizer for acknowledging synchronization of the output signal to the input signal, and the second synchronizer is configured to provide an Acknowledge Out signal to an external circuit, which is separate from the fast and slow clock domains, and the external circuit is configured to disable the input signal unless the Acknowledge Out signal is received by the external circuit.