Patent ID: 6064101
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A read-only memory cell arrangement, comprising:a semiconductor substrate;a plurality of longitudinal trenches formed in a main area of the semiconductor substrate, the plurality of longitudinal trenches being substantially parallel to each other;a plurality of individual memory cells formed in the semiconductor substrate, the plurality of individual memory cells arranged in rows which run substantially parallel to the plurality of longitudinal trenches and which are alternately positioned on the main area between adjacent longitudinal trenches and on respective bottoms of the longitudinal trenches, each of the plurality of individual memory cells including at least one MOS transistor;a plurality of bit lines running transversely to the rows, each of the plurality of bit lines connected to source/drain regions of MOS transistors respectively arranged along different rows; anda plurality of word lines positioned above the rows, each of the plurality of word lines connected to gate electrodes of MOS transistors arranged along a single row.