Patent ID: 6253298
Filing Date: 2001-06-26
Classification: G11C

Abstract:
An SRAM device comprising:an SRAM core having a memory array, write drivers, sense amplifiers, and output buffers;a plurality of write registers coupled to the write drivers;an address register configured to receive addresses for the memory array in the SRAM core;an input configured to receive an external address signal indicating that an external address is ready to be loaded into the address register;chip enable inputs configured to receive chip enable signals;chip enable and select logic coupled to the chip enable inputs to selectively enable or disable the SRAM device and selectively permit access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean function of the chip enable signals;an enable register having an input coupled to the chip enable and select logic for temporarily storing the SRAM core enable signal, and having an output;pipelined enable circuitry coupled between the enable register and the SRAM core, the pipelined enable circuitry including a pipelined enable register that has an input coupled to the output of the enable register, and that has an output, the pipelined enable circuitry further including a first AND gate having an input coupled to the output of the pipelined enable register, having an input adapted to be coupled via an inverter to an output enable signal, and having an output; and the pipelined enable circuitry further including a second AND gate having an input coupled to the output of first AND gate, having an input coupled via an inverter to the logical OR of all the outputs of the write registers, and having an output coupled to the output buffers; andpipelining logic coupled to at least one of the chip enable inputs to block the external address when a chip enable signal received at the one chip enable input is at a selected asserted logic level.