Patent ID: 6449759
Filing Date: 2002-09-10
Classification: G06F

Abstract:
An automated system for placement of at least one repeater buffer on a floor plan of an integrated circuit chip design, said system comprising:a computer aided design tool; netlist data of said chip design, said netlist data being accessible by said tool and including a location of at least one driver and at least one receiver, said netlist data comprising net propagation time delay data indicating need for optimization to further decrease a propagation delay in the chip design; and an algorithm for manipulating said netlist data, said algorithm comprising: a first set of software for geometrically and recursively placing at least one repeater on a group of nets between a software-generated driver placement and a software-generated receiver placement, said at least one repeater comprising: an optimized first approximation repeater placement; and first approximation netlist data; a second set of software for manipulating said first approximation netlist data and for generating a heuristically-improved configuration of said repeater placement; and a third set of software for assigning a type designation to each said at least one repeater via at least one rule with user-defined parameters in said heuristically-improved configuration of said repeater placement, wherein said group of nets comprises a geometric grouping, by said first set of software, such that said repeater placement is grouped with respect to an angular proximity in relation to said software-generated driver placement.