Patent ID: 6032246
Filing Date: 2000-02-29
Classification: G06F

Abstract:
A data processing device comprising:m (m.gtoreq.2) operation portions;m memory portions; andan interconnection for coupling said m operation portions and said m memory portions;wherein said m operation portions comprise m CPUs, respectively,said m memory portions comprise m semiconductor memories, respectively,said m semiconductor memories can store a sequence of data signals of N (N.gtoreq.2) bit width including a program defining operation of said m CPUs, said data signals being bit-sliced into m sliced signals respectively having bit widths L1, L2, . . . , Lm (L1, L2, . . . , Lm.gtoreq.1; L1+L2+ . . . +Lm=N) and said m sliced signals being respectively allocatable to said m semiconductor memories, andsaid m CPUs sequentially read said data signals of N bit width stored in the entirety of said m semiconductor memories and sequentially execute processings based on said data signals of N bit width,and wherein m pairs of which includes one of said m operation portions and one of said m memory portions are, respectively, formed in m single semiconductor chips which are separated from each other.