Patent ID: 6553484
Filing Date: 2003-04-22
Classification: G06F

Abstract:
An instruction-issuing circuit comprising:an instruction out-of-order buffer which has a plurality of entries and in which an instruction waiting to be issued is stored in any of said plurality of entries; an entry management circuit which instructs into which entry of said plurality of entries of the instruction out-of-order buffer a new instruction will be stored; a reference relation setting circuit which, when said new instruction is stored, determines whether said new instruction will reference, as an operand, an execution result of a preceding instruction already stored in said instruction out-of-order buffer and, when it is determined that said new instruction will reference said execution result, sets an entry position into the entry in which said preceding instruction is stored, said entry position indicating the entry in which said new instruction is stored, and a ready flag setting circuit which, when said preceding instruction is issued, updates an issue condition for the instruction stored in said instruction out-of-order buffer according to the entry position set by said reference relation setting circuit.