Patent ID: 6236617
Filing Date: 2001-05-22
Classification: G11C

Abstract:
An integrated circuit including a memory array having a set of memory cells controlled by a set of wordlines that are arranged in n groups of m wordlines, each of said set of wordlines being driven by a wordline driver circuit for supplying a boosted wordline high voltage and a negative wordline low voltage, said wordline high voltage being greater than a circuit high voltage supplied to other circuits within said integrated circuit, whereby said selected wordline has a wordline voltage swing that is greater than a standard voltage swing between ground and said circuit high voltage;a voltage supply selector circuit for exposing one wordline driver circuit in each group to said boosted wordline high voltage;a group decoder circuit for driving all of the wordline driver circuits in a decoded group with a group selection signal having a reduced voltage swing less than said wordline voltage swing, whereby a selected wordline driver circuit supplies said boosted wordline high voltage to a selected wordline connected to said selected wordline driver circuit;said wordline driver circuit has an output stage comprising an nfet connected between said negative wordline low voltage and said wordline and a pfet, having a pfet threshold voltage that is greater in magnitude than a standard pfet threshold voltage, connected between said wordline and said voltage supply selector circuit, whereby n-1 unselected wordline driver circuits exposed to said boosted wordline high voltage have low leakage and reduced gate stress and whereby a selected wordline driver circuit has an nfet having a gate-to-source voltage greater than zero and a non-selected wordline circuit has reduced gate stress.