Patent ID: 6317163
Filing Date: 2001-11-13
Classification: H04N

Abstract:
A video signal processing apparatus, comprising:a receiver receiving an incoming video signal, said receiver further producing an output video signal in response thereto;a limit setup unit setting up at least one of an upper limit value and a lower limit value for said output video signal; anda limiter supplied with said output video signal from said receiver and further with at least one of said upper limit value and said lower limit value from said limit setup unit, said limiter limiting a level of said output video signal produced by said receiver, by comparing said level of said output video signal according to any of said upper limit value and lower limit value;wherein said video signal processing apparatus is supplied with said video signal in the form of an analog composite signal and wherein said limit setup unit includes an upper limit setup unit setting up said upper limit value,said limiter including: an inverter supplied with said video signal in the form of the analog composite signal, an adder supplied with an output of said inverter and adding thereto said upper limit value; a rectifier rectifying an output of said adder, said rectifier outputting a positive half-cycle of said analog composite signal after a polarity inversion; and an offset circuit adding an offset value to an output of said rectifier.