Patent ID: 6700167
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate; a first insulating layer formed on the semiconductor substrate; a gate electrode structure formed on the first insulating layer, the gate electrode structure having a lower gate electrode layer and a cap gate layer formed on the lower gate electrode layer; a side wall structure which includes a nitride side wall spacer, and includes a CVD oxide layer formed between the semiconductor substrate and the nitride side wall spacer and between the lower gate electrode layer and the nitride side wall spacer; a second insulating layer covering the gate electrode and the side wall structure, the second insulating layer having a first contact hole exposing the source region and a second contact hole exposing the drain region; and a conductive material embedded in the first and second contact holes, wherein a thickness of the CVD oxide layer is greater than a thickness of the first insulating layer so as to prevent diffusion of nitrogen from the side wall spacer to the semiconductor substrate, and wherein a thickness of the gate electrode structure including the cap gate layer is substantially equal to a height of the side wall structure after completion of the semiconductor device.