Patent ID: 7126855
Filing Date: 2006-10-24
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device which has the arrangement of a plurality of cores comprising a set of electrically rewriteable nonvolatile memory cells and which is capable of reading data in an optional core of said plurality of cores while rewriting/erasing data in another optional core of said plurality of cores, said nonvolatile semiconductor memory device comprising: a first data comparator circuit for comparing current of a first data line, which is selected in a verify read operation for data write/erase in one core of said plurality of cores, with current of a first reference signal line; a second data comparator circuit for comparing current of a second data line, which is selected in a usual data read operation in the other core of said plurality of cores, with current of a second reference signal line; first and second current source transistors for allowing a constant current to pass through each of said first and second reference signal lines; and a reference constant current source circuit for driving said first and second current sources in parallel.