Patent ID: 6380030
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method of forming nitride spacers in split-gate flash memory cells employing ion implantation, comprising the steps of:providing a substrate having a plurality of active and field regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; etching said first polysilicon layer to define floating gate structure of said split-gate flash memory cells; forming an oxide layer over said substrate including said floating gate; forming a nitride layer over said oxide layer; vertically ion implanting said nitride layer; performing a high selectivity etch of said nitride layer to form spacers on the sidewalls of said floating gate; forming an intergate dielectric layer over said substrate; forming a second polysilicon layer over said intergate dielectric layer; and patterning said second polysilicon layer to form control gate structure of said split-gate flash memory cells.