Patent ID: 6499334
Filing Date: 2002-12-31
Classification: G01R,H03K

Abstract:
A variable delay element test circuit comprising:a variable delay element having an input node and an output node, a delay time amount to output by delaying an input pulse signal input to the input node is set arbitrarily; a loop control circuit having a loop circuit, said variable delay element being included in this loop circuit, for controlling so that the positive/negative logic of said input pulse signal input to the input node of said variable delay element is always constant; a count control circuit for receiving an output pulse signal output from the output node of said variable delay element, counting the number of receptions of this output pulse signal, detecting agreement of that count value and a predetermined set value, and for generating an agreement detection signal when the agreement is detected; and an output control circuit connected to said count control circuit for controlling the transmission of said output pulse signal output from said variable delay element to following circuits of said variable delay element, based on the agreement detection signal generated by said count control circuit.