Patent ID: 6741498
Filing Date: 2004-05-25
Classification: G11C

Abstract:
A non-volatile memory positioned on a substrate of a semiconductor wafer, the non-volatile memory comprising:a main memory array region comprising: at least one main memory cell, the main memory cell comprising a main source and a main drain positioned in the substrate of the semiconductor wafer; at least one main bit line, the main bit line being electrically connected to the main drain of the main memory cell; and at least one main ground line, the main ground line being electrically connected to the main source of the main memory cell; a redundant memory array region connected to the main memory array region, the redundant memory array region comprising: at least one redundant memory cell, the redundant memory cell comprising a redundant source and a redundant drain positioned in the substrate of the semiconductor wafer; at least one redundant bit line, the redundant bit line being electrically connected to the redundant drain of the redundant memory cell; and at least one redundant ground line, the redundant ground line being electrically connected to the redundant source of the redundant memory cell; and a common source used as the main source and the redundant source formed between the main memory array region and the redundant memory array region.