Patent ID: 8930931
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. An information processing apparatus capable of updating system settings information by executing firmware, the information processing apparatus comprising: a first processor to execute firmware and instructions for data processing; a second processor connected to the first processor via a first bus to conduct management of at least firmware updating and system settings; a first memory and a second memory capable of storing current firmware and updated firmware; a third memory connected to the second processor to store the system settings information defining information for use in conjunction with firmware and its modification; and a switch to change connections of the first memory and the second memory under control of the second processor, to connect one of the first and second memories to a second bus connected to the first processor and to connect the other one of the first and second memories to the second processor, wherein the second processor stores firmware for update into the second memory through control of the switch; after the updated firmware is stored in the second memory, the second processor connects the second memory to the second bus through control of the switch; the first processor executes the updated firmware obtained from the second memory via the second bus; during the execution of the updated firmware by the first processor, the second processor reads the system settings information from the third memory and provides this information to the first processor via the first bus; the first processor reflects the system settings information in firmware data of the updated firmware stored in the second memory; the first processor provides the reflected system settings information which is reflected in updated firmware data to the second processor via the first bus; and the second processor stores the reflected system settings information which is reflected in updated firmware data into the third memory; wherein the third memory stores switch settings information specifying the first or second memory as current and subsequent destinations of connections of the second bus and the switch; and the second processor refers to the switch settings information read from the third memory and controls the switch to update the subsequent destination of connection of the switch and change the connection of the first or second memory to the second bus.