Patent ID: 8588009
Filing Date: 2013-11-19
Classification: G11C

Abstract:
1. A method for extending lifetime reliability of a memory cell, the method comprising: providing a first and second read and write (R/W) path connecting a memory cell to a sense amplifier, wherein one of the first and second R/W paths comprises a first conductive path connecting a first node of the memory cell to a first node of the sense amplifier and a second conductive path connecting a second node of the memory cell to a second node of the sense amplifier, and an other of the first and second R/W paths comprises a first conductive path connecting the first node of the memory cell to the second node of the sense amplifier and a second conductive path connecting the second node of the memory cell to the first node of the sense amplifier, wherein the respective first and second nodes of the memory cell and the sense amplifier are each capable of storing a bit value; activating the first R/W path and precharging the first and second conductive paths of the first R/W path; activating a word line corresponding to the memory cell to read the bit values of the first and second node of the memory cell onto the first and second conductive paths of the first R/W path; providing a voltage to the sense amplifier to latch the bit values on the first and second conductive paths of the first R/W path into the first and second nodes of the sense amplifier; deactivating the word line; deactivating the first R/W path; activating the second R/W path and reading the bit values in the first and second nodes of the sense amplifier onto the first and second conductive paths of the second R/W path; and activating the word line to write the bit values on the first and second conductive paths of the second R/W path into the respective first and second nodes of the memory cell to enter a recovery state.