Patent ID: 8238168
Filing Date: 2012-08-07
Classification: G11C

Abstract:
1. A method comprising: determining whether a memory array is in one of an inactive period and an active period, said memory array including a plurality of dynamic random access memory (DRAM) cells connected to a plurality of bit-lines, and a plurality of inverters connected between pairs of said DRAM cells by said bit-lines; maintaining a bit-line voltage level of said memory array at a first voltage level during inactive periods by connecting said bit-lines to a first independently gated power supply through said inverters; and maintaining said bit-line voltage level of said memory array at a second voltage level during active periods by connecting said bit-lines to a second independently gated power supply through said inverters, said inactive periods comprising times when said memory array is not being sensed, said active periods comprising times when said memory array is being sensed, said first voltage level comprising a voltage level that is optimized to reduce memory cell leakage, and said second voltage level comprising a voltage level that is optimized for signal sensing.