Patent ID: 6069069
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit device comprising:providing semiconductor device structures in and on a semiconductor substrate;depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines wherein a gap is formed between said conducting lines;depositing a first dielectric layer over the surfaces of said conducting lines wherein said first dielectric layer contains an etch stop layer wherein said gap remains between said conducting lines;depositing a second dielectric layer overlying said first dielectric layer wherein said gap is filled by said second dielectric layer;etching back said second dielectric layer so that said second dielectric layer remains only within said gap wherein said etch stop layer preserves the integrity of said underlying conducting lines;depositing a third dielectric layer over said first and second dielectric layers; andplanarizing said third dielectric layer completing the fabrication of said integrated circuit device.