Patent ID: 7500084
Filing Date: 2009-03-03
Classification: G06F

Abstract:
1. A computer process for performing combinations of multiply, add, and subtract operations in an environment supporting both Binary Floating Point (BFP) operations and non-BFP floating point operations, wherein the non-BFP floating point operations comprise Hexadecimal Floating Point (HFP) operations, the computer process comprising: providing three operands of a combination multiply add/subtract instruction to a main fraction dataflow element of a floating point element, each of said operands comprising BFP floating point format values or non-BFP floating point format values, said non-BFP floating point format values comprising floating point format values other than Binary Floating Point (BFP) format values, and said main fraction dataflow element configured to process both BFP floating point format values and non-BFP floating point format values for said operands; responsive to the combined multiply add/subtract instruction being a non-BFP floating point multiply add/subtract instruction, the main fraction dataflow element performing a non-BFP floating point operation on the provided three operands to produce a non-BFP main fraction result, said operands comprising said non-BFP floating point format values, the operation specified by the combination multiply add/subtract instruction, the non-BFP main fraction result comprising non-BFP floating point format fraction values; and responsive to the combined multiply add/subtract instruction being a non-BFP multiply add/subtract instruction, storing the non-BFP main fraction result; and responsive to the combined multiply add/subtract instruction being a BFP multiply add/subtract instruction, the main fraction dataflow element performing a BFP operation on the provided three operands to produce a BFP main fraction result, said operands comprising said BFP floating point format values, the operation specified by the combination multiply add/subtract instruction, the BFP main fraction result comprising BFP format fraction values; and responsive to the combined multiply add/subtract instruction being a BFP multiply add/subtract instruction, storing the BFP main fraction result.