Patent ID: 6466988
Filing Date: 2002-10-15
Classification: G06F

Abstract:
A multiprocessor system comprising:a plurality of processors each of which has a cache memory; a main memory shared by said plurality of processors; a cache coherence controller for managing address information of data held in said cache memory of each of said processors and performing cache coherence control among said processors; each of said processors generating a synchronization transaction when executing an instruction for taking synchronization between processors; a main memory access sequence guaranteeing mechanism for stopping, when said synchronization transaction is received from one of said processors, main memory accesses resulting from said one of said processors and restarting said main memory accesses when all of said processors output the synchronization transaction; and a coherence completion guaranteeing mechanism for notifying each of said processors of completion of the coherence control when all of cache coherence control requests resulting from instructions executed by said plurality of processors before the instruction for taking said synchronization are output from said cache coherence controller to a corresponding one of said plurality of processors; wherein, each of said plurality of processors stops execution of succeeding instructions during a term after executing the instruction for taking synchronization and until said notice from said coherence completion guaranteeing mechanism is received.