Patent ID: 6791387
Filing Date: 2004-09-14
Classification: H03K

Abstract:
A feedback latch circuit comprising:a first logic OR gate having a clock input terminal for receiving a clock input signal, a data input terminal, and an output terminal; a first logic AND gate having a first data input terminal coupled to said output terminal of said first logic OR gate, a second data input terminal for receiving a data input signal, and an output terminal; a second logic AND gate having a data input terminal coupled to said data input terminal of said first logic OR gate, a clock input terminal for receiving a complementary clock input signal that complements the clock input signal, and an output terminal; and a second logic OR gate having a first data input terminal coupled to said output terminal of said first logic AND gate, a second data input terminal coupled to said output terminal of said second logic AND gate, and an output terminal coupled to said data input terminals of said first logic OR gate and said second logic AND gate; wherein a latch output of said feedback latch circuit is obtained from said output terminal of said second logic OR gate.