Patent ID: 8259524
Filing Date: 2012-09-04
Classification: G11C

Abstract:
1. A semiconductor device having a dual-port memory circuit, wherein the dual-port memory circuit comprises: wherein the memory cell array includes: first complementary bit lines and first word lines coupled to the first peripheral circuits; second complementary bit lines and second word lines coupled to the second peripheral circuits; a plurality of memory cells coupled to the first complementary bit lines, the first word lines, the second complementary bit lines, and the second word lines; a first replica bit line and a first replica word line coupled to the first peripheral circuits; a second replica bit line and a second replica word line coupled to the second peripheral circuits; a plurality of replica cells having transistor placement equivalent to transistor placement of the memory cells and coupled to the first replica bit line and the first replica word line; and a plurality of replica cells having transistor placement equivalent to transistor placement of the memory cells and coupled to the second replica bit line and the second replica word line, wherein the first replica bit line has a wiring structure that parallel lines having length obtained by cutting an inversion bit line and a non-inversion bit line of the first complementary bit lines in half are mutually short-circuited, and wherein the second replica bit line has a wiring structure that parallel lines having length obtained by cutting an inversion bit line and a non-inversion bit line of the second complementary bit lines in half are mutually short-circuited.