Patent ID: 6577523
Filing Date: 2003-06-10
Classification: G11C

Abstract:
A memory device comprising:a first array of memory cells arranged in rows and columns, each of the memory cells having a transistor with source and drain regions having a first size; an second array of memory cells arranged in rows and columns; a first plurality of bit lines coupled to the memory cells in the first array, the bit lines in the first plurality being provided for respective columns in the first array; a second plurality of bit lines coupled to the memory cells in the second array, the bit lines in the second plurality being provided for respective columns in the second array; a first plurality of word lines coupled to the memory cells in the first array; a second plurality of word lines coupled to the memory cells in the second array; a plurality of sense amplifiers positioned between the first array and the second array, each of the sense amplifiers having transistors with source and drain regions having a second size, the second size being larger than the first size; a first plurality of isolation transistors located in the first memory array, each of the isolation transistors in the first plurality being coupled between one of the sense amplifiers and a respective one of the bit lines in the first array; and a second plurality of isolation transistors located in the second memory array, each of the isolation transistors in the second plurality being coupled between one of the sense amplifiers and a respective one of the bit lines in the second array.