Patent ID: 8713216
Filing Date: 2014-04-29
Classification: G06F

Abstract:
1. A processor comprising: a plurality of processing sections that outputs a first request and a second request; a first memory controller that receives the first request from the plurality of processing sections; a second memory controller that receives the second request from the plurality of processing sections; a first memory that is connected to the first memory controller and controlled by the first memory controller to output first data via a first bus associated with the first request; a second memory that is connected to the second memory controller and controlled by the second memory controller to output second data via a second bus associated with the second request; and a buffer controller that includes a buffer and is connected to the first memory via the first bus and the second memory via the second bus, and transfers the first data or the second data which is transferred over a greater distance than the other data to a processing section, stores the first data or the second data which is not transferred in the buffer, and transfers the first data or the second data stored in the buffer to the processing section after termination of transferring the first data or the second data which is greater in data transfer distance than the other data, when outputting of the first data from the first memory and outputting of the second data from the second memory are performed simultaneously; wherein: during transfer of data outputted via one of the first bus and the second bus to a processing section, the buffer controller stores data outputted via the other of the first and second bus; and the first and second busses connect to the plurality of processing sections, respectively, and when one of the first and second memory controllers receives an associated one of the first and second requests from one of the plurality of processing sections, the one of the first and second memory controller terminates receiving a request from any of the processing sections connected to a same bus as one of the first and second buses connected to the one of the plurality of processing sections which has outputted the request for a predetermined time period.