Patent ID: 6546480
Filing Date: 2003-04-08
Classification: G06F

Abstract:
A method of operating a processing core to effectuate multiplication comprising steps of:receiving an integer multiply instruction; decoding the integer multiply instruction to produce first control signals, some of the first control signals being applied to a multiplication unit; in response to the first control signals, providing contents of first and second registers to the multiplication unit and producing a first product term therefrom, the first product term representative of a product of the contents of the first and second registers; receiving a fixed-point multiply instruction; decoding the fixed-point multiply instruction to produce second control signals, some of the second control signals being applied to the multiplication unit; and in response to the second control signals, providing contents of third and fourth registers to the multiplication unit and producing a second product term therefrom, the second product term representative of a combination of one or more operations performed on the contents of the third and fourth registers, including a multiplication operation, a saturation operation, and a shifting operation, wherein the first and second registers each comprises packed integer data and the first product term comprises packed integer product terms, wherein the third and.fourth registers each comprises packed fractional format data and the second product term comprises packed fractional format product terms.