Patent ID: 6106565
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A computer system for emulating a processor under development, the computer system comprising:a first terminal for receiving an interrupt signal wherein said interrupt signal is activated by a first switch controllable by a user;a second terminal for receiving a halt signal;a main memory;a first processor receiving said interrupt signal, wherein said first processor is a processor to be emulated, and wherein said first processor, in response to said interrupt signal, (i) saves the states of a program executing in said first processor in said main memory system; and then (ii) halts operation of said first processor;a second processor receiving said interrupt signal and said halt signal, wherein said second processor comprises a logic circuit emulating said first processor, and wherein said second processor, in response to said interrupt signal, (i) waits until said halt signal is deasserted; (ii) restores said states of said program form said main memory into said second processor; and (iii) resumes execution of said program from said restored states.