Patent ID: 6253305
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A microprocessor for supporting reduction of program codes in size, comprising:a decoder for decoding instructions which are ""w"" in length represented by expressionw=a+nb,wherein ""a"" represents a minimum length of the instructions decoded by said decoder, ""n"" an integer of 0 or larger and includes at least 0 and 1, and ""b"" a positive integer smaller than ""a,"" wherein an instruction is divided into one or more codes, and wherein said instructions include at least an instruction which is ""a"" in length and an instruction which is ""(a+b)"" in length;an executing means for processing data based on information obtained from said instructions decoded by said decoder, a program decoded and executed by the microprocessor including the instruction which is ""a"" in length and an instruction which is ""(a+b)"" in length.