Patent ID: 8835306
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising: providing a substrate including a protecting layer over an oxide layer, wherein the oxide layer has an upper surface defining an oxide layer plane; etching a recess through the protecting layer and into the oxide layer; depositing a barrier material over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess; depositing a conductive material over the barrier layer and forming an embedded electrical interconnect in the recess and an overburden region outside the recess; removing the overburden region of the conductive material; recessing a portion of the embedded electrical interconnect to a recessed surface defining an electrical interconnect plane, wherein the electrical interconnect plane is beneath the oxide layer plane; after recessing the portion of the embedded electrical interconnect, etching the barrier layer to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer; and after etching the barrier layer, removing the protecting layer from the oxide layer.