Patent ID: 8975705
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first planar silicon layer formed on a substrate; first and second pillar-shaped silicon layers formed on the first planar silicon layer; a first gate insulating film formed around the first pillar-shaped silicon layer; a first gate electrode formed around the first gate insulating film; a second gate insulating film formed around the second pillar-shaped silicon layer; a second gate electrode formed around the second gate insulating film; a first gate line connected to the first and second gate electrodes; a first second-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer; a second second-conductivity-type diffusion layer formed over a lower portion of the first pillar-shaped silicon layer and an upper portion of the first planar silicon layer; a first first-conductivity-type diffusion layer formed in an upper portion of the second pillar-shaped silicon layer; and a second first-conductivity-type diffusion layer formed over a lower portion of the second pillar-shaped silicon layer and an upper portion of the first planar silicon layer, wherein the first gate line has a width with a center, the first gate line has a center line that extends along the center of the width, and the center line extends from the first pillar-shaped silicon layer to the second pillar-shaped silicon layer; and wherein the center line of the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped silicon layer and a center of the second pillar-shaped silicon layer.