Patent ID: 7368796
Filing Date: 2008-05-06
Classification: H01L

Abstract:
1. Complimentary semiconductor devices comprising: a semiconductive substrate; complimentary NMOS and PMOS doped regions formed in the semiconductive substrate; a dielectric layer comprising silicon oxide positioned on the semiconductive substrate; and an interconnecting layer positioned on the dielectric layer so as to define gate stacks over the NMOS and PMOS regions wherein the interconnecting layer comprises a metal silicide wherein a metal of the metal silicide is matched with the metal silicide such that the metal is inhibited from reacting with the dielectric layer and wherein the interconnecting layer adjacent the NMOS doped regions is selectively nitrided such that the interconnecting layer adjacent the NMOS regions comprises nitrided metal silicide such that a work function of the nitrided metal silicide is reduced with respect to the metal silicide adjacent the PMOS regions such that Fermi levels of the gate stacks overlying the NMOS and PMOS regions are more evenly mid-gap.