Patent ID: 6941428
Filing Date: 2005-09-06
Classification: G06F

Abstract:
1. A method of actively optimizing an internal memory controller of a chip, the internal memory controller having a plurality of pending requests for a memory bus from a plurality of requestors, the method comprising the steps of: monitoring memory bus activity; re-prioritizing pending memory requests based on memory bus activity and an acceptable wait time for a requestor; and repeating the above steps, wherein the step of monitoring includes collecting memory bus performance factors, and wherein each requestor includes an evaluation time period register, a requestor minimum throughput register and an efficiency register, and each pending request includes a weight factor, wherein the step of re-prioritizing includes: determining a throughput of the memory bus; determining an estimated wait time that a requestor will have to wait to gain access to the bus; calculating an acceptable wait time for a requestor based on the respective requestor evaluation time period, the requestor minimum throughput, the efficiency and a bus width; assigning a new weight factor to each pending request having an acceptable wait time that is less than an estimated wait time; and re-prioritizing a prioritized queue of pending requests.