Patent ID: 8601302
Filing Date: 2013-12-03
Classification: G06F,Y02D

Abstract:
1. A computer-implemented method of placing a system including a processor into a low power mode, the method comprising: stopping running user-space processes and kernel threads executing on the processor; saving state of the user-space processes and kernel threads in memory; placing an input/output device coupled to the processor into a suspend mode; configuring a wakeup source coupled to the processor to generate interrupts; gating a clock defined in a clock gating register of the processor; placing a linear regulator on a power management integrated circuit (PMIC) of the system into an off state; placing a switching regulator on the PMIC into low power state; preparing the PMIC to enter a low power mode; setting a processor state retention mode in a clock control module coupled to the processor; flushing a cache coupled to the processor; disabling interrupt requests to the processor except for interrupts from the wakeup sources; disabling processor scaling in the processor; executing a wait for interrupt instruction configured to receive the wakeup interrupt from the wakeup source; gating a main clock of the processor; and placing the PMIC in the low power mode.