Patent ID: 6518124
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method of fabricating a semiconductor device including:a memory region which has nonvolatile memory devices; and a logic circuit region which has a peripheral circuit for the nonvolatile memory devices, the method comprising the following steps in this order: a step of forming a first insulating layer over a semiconductor layer; a step of forming a first conductive layer over the first insulating layer; a step of forming a mask insulating layer over part of the first conductive layer disposed within the logic circuit region; a step of forming a stopper layer over the first conductive layer and the mask insulating layer; a step of etching part of the stopper layer, the mask insulating layer and the first conductive layer to form word gate layers in the memory region and to form gate electrodes of insulated-gate field-effect transistors in the logic circuit region; a step of forming an ONO film over the entire surface of the memory region and the logic circuit region; a step of forming a second conductive layer over the ONO film; a step of anisotropically etching the second conductive layer to form control gates in the shape of sidewalls at least on both sides of each of the word gate layers in the memory region with the ONO film interposed; a step of forming first impurity layers each of which forms a source region or a drain region of the nonvolatile memory devices, and forming second impurity layers each of which forms a source region or a drain region of the insulated-gate field-effect transistors; a step of forming sidewall insulating layers at least on both sides of the gate electrodes; a step of forming silicide layers on the surfaces of the first impurity layers and the second impurity layers; a step of forming a second insulating layer over the entire surface of the memory region and the logic circuit region; a step of polishing the second insulating layer to expose the stopper layer; a step of removing the stopper layer; and a step of patterning the word gate layers in the memory region to form word gates of the nonvolatile memory devices in the memory region.