Patent ID: 7488639
Filing Date: 2009-02-10
Classification: H01L

Abstract:
1. A method of manufacturing semiconductor integrated circuit device including memory cells each having a pair of inverters comprising a driver MISFET and a load MISFET, respectively, and a pair of transfer MISFETs, the driver MISFETs having gate electrodes and drains cross-connected to one another, respectively, the method comprising the steps of: forming an interlayer insulating film over the driver MISFETs, load MISFETs and transfer MISFETs; forming a pair of trenches in the interlayer insulating film; forming a pair of conductive layers in the pair of trenches, respectively, such that one of the conductive layers is electrically connected to the gate electrode of one of the driver MISFETS and the drain of the other one of the driver MISFETs and such that said other one of the conductive layers is electrically connected to the gate electrode of said other one of the driver MISFETs and the drain of said one of the driver MISFETs; removing a part of the insulating film so as to expose side surfaces of the conductive layers; forming a capacitive insulating film over the side surfaces and upper surfaces of the conductive layers; and forming an upper electrode over the capacitive insulating film and the conductive layers.