Patent ID: 7383629
Filing Date: 2008-06-10
Classification: H01L,H05K,Y10S,Y10T

Abstract:
1. A method of making a circuitized substrate comprising: providing at least one dielectric layer; providing first and second electrically conductive layers each having a first side of a first, relatively low roughness and a second side of a second roughness greater than said first, relatively low roughness of said first sides; treating said first and second sides of said first and second electrically conductive layers with a first chemical treatment so as to etch said first and second sides and thereby minimally increase said first relatively low roughness of said first sides to a first greater roughness and also minimally increase said second roughness of said second sides to a second greater roughness greater than said first greater roughness, said first chemical treatment including depositing a thin organic layer on said first and second sides of said first and second electrically conductive layers; bonding said first sides of said first and second electrically conductive layers having said thin organic layer thereon following said treating of said first and second sides to said dielectric layer such that said dielectric layer is positioned substantially between said first and second electrically conductive layers; treating said second sides of said first and second electrically conductive layers after said bonding of said first sides of said first and second electrically conductive layers to said dielectric layer with a second chemical treatment different from said first chemical treatment so as to etch said second sides but not to include a thin organic layer thereon, said second chemical treatment reducing both said second greater roughness of said second sides and the thickness of said first and second electrically conductive layers such that said second greater roughness of said second sides is substantially similar to said first greater roughness of said first sides during said bonding of said first sides to said dielectric layer; and forming a circuit pattern within at least one of said electrically conductive layers.