Patent ID: 6274471
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method for making high-aspect-ratio contact openings in an insulating layer on a semiconductor substrate for integrated circuits comprising the steps of:providing said semiconductor substrate having device areas surrounded by field oxide areas;depositing a polycide layer and a hard-mask layer on said substrate;patterning said hard-mask layer and said polycide layer to form portions of devices over said device areas and interconnections over said field oxide areas, said devices having diffused areas in said device areas of said substrate;depositing an anti-reflective coating layer on said substrate;coating a photoresist layer on said substrate and patterning to form openings over said interconnections;etching said anti-reflective coating exposed in said openings to said hard mask;etching said hard-mask layer in said openings to said polycide layer that forms said interconnections while said anti-reflective coating protects said diffused areas;removing said photoresist layer and said anti-reflective coating;depositing an insulating layer on said substrate;etching contact openings in said insulating layer to said diffused areas and concurrently etching openings to said polycide layer that forms said inter-connections.