Patent ID: 6581120
Filing Date: 2003-06-17
Classification: G06F

Abstract:
An interrupt controller comprising:an interrupt mask register that receives and stores an interrupt on/off instruction from a CPU; an interrupt priority register that receives and stores an interrupt priority instruction from the CPU; an interrupt mask circuit unit that selectively receives, and provides interrupt generating signals from a peripheral device in response to the interrupt on/off instruction from the interrupt mask register; a priority determining circuit unit that receives the interrupt generating signals from the interrupt mask circuit unit, determines priorities of the interrupt generating signals in response to the interrupt priority instruction from the interrupt priority register, and forwards an interrupt priority signal to an interrupt terminal at the CPU; an interrupt status register that stores information related to a peripheral device from the interrupt priority signal, and provides a register selection signal corresponding to the information; a buffer unit that buffers a data signal between the CPU and the interrupt controller; an interrupt instruction register that stores a branch instruction received from the CPU for processing an interrupt, and provides an interrupt instruction to the CPU via the buffer unit in response to the register selection signal output from the interrupt status register; and a bus interface circuit unit that transfers an address signal between the CPU and the interrupt controller, transfers, prior to an occurrence of the interrupt and upon an initialization of a CPU, the branch instruction from the CPU to the interrupt instruction register for storage, and provides a read/write control signal to the interrupt instruction register.