Patent ID: 6121116
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method for forming isolation regions in a flash memory integrated circuit device, said method comprising:providing a silicon substrate, said substrate comprising a core memory region and a high voltage region, said silicon substrate having a silicon dioxide layer thereon and said high voltage region comprising a high voltage device;forming a nitride mask layer overlying said silicon dioxide layer in said core memory region and said high voltage region, said nitride mask layer exposing a first isolation region coupled to said high voltage region;oxidizing said first isolation region to form a first isolation structure having a first thickness;patterning said nitride mask layer to expose a second isolation region coupled to said core memory region; andoxidizing said exposed second isolation region to form a second isolation structure having a second thickness and simultaneously oxidizing said first isolation structure to a third thickness, said third thickness being greater than said first thicknesswherein said high voltage region is for a high voltage, and said core memory cell region is for a switching voltage, wherein the high voltage is at least about fifty percent higher than the switching voltage.