Patent ID: 7161208
Filing Date: 2007-01-09
Classification: H01L

Abstract:
1. A MOS-gated device comprising: a substrate of a first conductivity type; a trench receiving layer which includes a common conduction region of said first conductivity type, and a base region of a second conductivity type formed over said common conduction region; a plurality of trenches formed to extend below said base region, each trench including a gate insulation layer disposed on at least one side wall thereof and filled with a conductive gate material; a plurality of source regions each adjacent a respective trench; a plurality of highly conductive contact regions formed in said base region; and a plurality of field relief regions of said second conductivity formed in said common conduction region and extending to a depth below said base region; wherein each said field relief region is lightly doped, spaced from said base region and said trenches, and aligned with a respective highly conductive contact region, and wherein each of said highly conductive contact regions is formed at the bottom of a respective recess in said base region, and wherein a source region is located at a respective sidewall of each recess.