Patent ID: 7992077
Filing Date: 2011-08-02
Classification: H04L

Abstract:
1. A data slicer having an error correction device, comprising: a first subtractor, for subtracting a first level signal from a first data signal to generate a second data signal; a first serial to parallel converter, coupled to the first subtractor, for generating a first byte according to a sign bit of the second data signal; a level compensator, coupled to the first subtractor, for adjusting an offset of the first level signal according to the second data signal to generate a second level signal; a first comparator, coupled to the level compensator, for comparing the second level signal with the first data signal to generate a first comparing signal; a second serial to parallel converter, coupled to the first comparator, for converting the first comparing signal to a second byte; a co-channel detector, coupled to the level compensator, for determining co-channel interference according to a difference between a maximum and a minimum of the second level signal to generate a first indication signal; an error bit predictor, coupled to the first subtractor, for indicating an error bit of the first byte to generate a second indication signal; and an output device, for outputting the first byte or the second byte according to the first indication signal, a parity check of the first byte, and a parity check of the second byte, or outputting a corrected first byte according to the second indication signal.