Patent ID: 7116662
Filing Date: 2006-10-03
Classification: H04L,H04Q

Abstract:
1. A multi-layered packet processing device, comprising: an interface of a public network for transmitting a data packet to a node and receiving the data packet from the node through a public network; and a plurality of packet processing portions for sequentially processing the data packet in a pipeline pattern, according to a header of the data packet transferred from the interface of the public network, wherein the plurality of packet processing portions comprise: a packet separating processor for outputting a packet to be analyzed, by sequentially including a tag in part of the data packet transferred from the interface, the packet separating processor for storing a remainder of the packet to be analyzed, which is left after the packet to be analyzed is output; a plurality of header analyzing processors for sequentially analyzing the packet to be analyzed transferred from the packet separating processor, according to a header encapsulated in the packet to be analyzed, and then reflecting an analyzed result in the tag of the packet to be analyzed, and outputting an analyzed packet; a packet reassembling processor for requesting the remainder of the packet to be analyzed stored in the packet separating processor, when the packet reassembling processor receives the analyzed packet output from the plurality of header analyzing processors, and outputting the analyzed packet together with the requested remainder of the packet to be analyzed, as a complete data packet; and an output processor for determining an output route of the complete data packet by analyzing output route information reflected in the tag of the complete data packet transferred from the packet reassembling processor, and outputting the complete data packet according to the determined output route.