Patent ID: 6327206
Filing Date: 2001-12-04
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells arranged in a matrix-like manner;an address decoder connected to the memory cell array for selectively activating a certain memory cell in the memory cell array based on parallel address data;a sense amplifier for generating parallel read data from data stored in the activated memory cell;an input/output circuit for receiving serial address data and outputting serial read data;a first serial/parallel converter connected between the address decoder and the input/output circuit for converting the serial address data received from the input/output circuit to parallel address data and providing the parallel address data to the address decoder, wherein the first serial/parallel converter is adjacent to the address decoder; anda parallel/serial converter connected between the sense amplifier and the input/output circuit for converting the parallel read data received from the sense amplifier to the serial read data and providing the serial read data to the input/output circuit, wherein the parallel/serial converter is adjacent to the sense amplifier.