Patent ID: 6353919
Filing Date: 2002-03-05
Classification: G06F

Abstract:
A method of mapping a logical expression to a logic circuit, comprising:placing a first-type multiple-input logic gate having input terminals and an output terminal, a multiplexer having input terminals, at least one control terminal and an output terminal, and a second-type multiple-input logic gate having input terminals and an output terminal in the logic circuit; and non-invertingly connecting one of the input terminals of the multiplexer to the output terminal of the first-type multiple-input logic gate, and one of the input terminals of the second-type multiple-input logic gate to the output terminal of the multiplexer, wherein the first-type multiple-input logic gate is one of a NAND and a NOR gate and the second-type multiple-input logic gate is the other one of a NAND and a NOR gate.