Patent ID: 7522459
Filing Date: 2009-04-21
Classification: G11C

Abstract:
1. An input circuit for N-bit prefetch in a semiconductor memory device, the input circuit comprising: a control signal generating unit for generating a plurality of control signals in response to a clock signal and a data strobe signal, wherein external data are input in synchronism with the data strobe signal; and a synchronizing unit for aligning the input data into N-bit data in parallel by performing a data alignment operation at least three times, N being a positive integer larger than one, wherein the synchronizing unit includes: a first synchronizing unit for aligning the input data into first aligned data in response to a first control signal and a second control signal in synchronism with the data strobe signal; a second synchronizing unit for aligning an output of the first synchronizing unit into second aligned data in response to a third control signal in synchronism with the clock signal, and a third synchronizing unit for aligning an output of the first synchronizing unit and the second synchronizing unit into the N-bit data in parallel in response to a fourth control signal.