Patent ID: 6277710
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method to form shallow trench isolations in the manufacture of an integrated circuit device comprising:providing a semiconductor substrate;depositing a polysilicon layer overlying said semiconductor substrate;ion implanting said polysilicon layer to increase the oxidation rate of said polysilicon layer;depositing a silicon nitride layer overlying said polysilicon layer;patterning said silicon nitride layer, said polysilicon layer, and said semiconductor substrate to form trenches for planned shallow trench isolations;growing a liner oxidation layer overlying said semiconductor substrate and said polysilicon layer inside said trenches wherein a portion of said polysilicon layer adjacent to said inside of said trenches is oxidized;depositing a trench oxide layer overlying said silicon nitride layer and filling said trenches;polishing down said trench oxide layer to said silicon nitride layer;etching away said silicon nitride layer wherein said liner oxidation layer and oxidized said polysilicon layer protect said trench oxide layer during said etching away; andetching away said polysilicon layer to complete said shallow trench isolations in the manufacture of said integrated circuit wherein said liner oxidation layer and said oxidized polysilicon layer protect said trench oxide layer during said etching away.