Patent ID: 6021482
Filing Date: 2000-02-01
Classification: G06F

Abstract:
A method for mapping each of a plurality of logical addresses to a physical address identifying a location in a memory device, wherein the memory device has a plurality of columns and rows, wherein each row has a plurality of data paragraphs including data and at least one parity paragraph including parity data, wherein each paragraph is comprised of a plurality of contiguous columns, and wherein a physical address identifies a location of a paragraph in the memory device, comprising the steps of:(a) for each logical address, determining whether the row and column portions of a logical address identify a physical address location including parity data;(b) upon determining that a logical address identifies a physical address location in the memory device including parity data, incrementing the logical address until the row and column portions of the logical address identify a physical address location not including parity data; and(c) setting the column and row portions of the physical address to the column and row portions of one of the: (i) logical address upon determining that the logical address does not identify a physical address location including parity data and (ii) the incremented logical address upon determining that the logical address identifies a physical address location including parity data.