Patent ID: 7873133
Filing Date: 2011-01-18
Classification: H03L,H04J

Abstract:
1. A phase-locked loop system comprising: a phase frequency detector configured to receive a reference frequency and compare the reference frequency to a feedback frequency and generate an error signal based on the comparison; a filter configured to receive the error signal and remove frequencies above a threshold value that are present in the error signal and output a frequency control signal; an oscillator configured to receive the frequency control signal and generate an output frequency signal representative of a first phase offset between the reference frequency and the feedback frequency; and a phase shifter configured to use a ninety degree phase shift to generate an in-phase clock and a quadrature-phase clock, the phase shifter further configured to receive the output frequency signal and adjust the output frequency signal relative to a second phase offset that is associated with an average phase error across a plurality of frames, each of the plurality of frames including a payload, the phase shifter including a digital-to-analog converter such that the phase shifter provides a minimum phase shift step smaller than a clock period of a clock rate of the payload.