Patent ID: 7272810
Filing Date: 2007-09-18
Classification: G06F,H01L

Abstract:
1. A computer-aided design method of multilevel interconnection including first- and second-potential-level power supply wirings for supplying power to a plurality of logic elements in an integrated circuit, the method comprising: calculating current dissipation consumed by the logic elements, in a ladder network comprising a plurality of current paths flowing through each of the logic elements, the current paths are connected in parallel between a subject first-potential-level power supply wiring and a subject second-potential-level power supply wiring; analyzing a tolerable electro-migration current of the subject first-potential-level power supply wiring; analyzing an interval voltage drop between a control point and a specific position on the subject first-potential-level power supply wiring; and comparing a summation of through-currents flowing through the logic elements, which are arranged in a region from the control point to the specific point, with the tolerable electro-migration current, and further comparing the interval voltage drop with a tolerable voltage drop so as to determine an optimum location of a via configured to supply power from the subject first-potential-level power supply wiring to the logic elements.