Patent ID: 6635951
Filing Date: 2003-10-21
Classification: H01L,Y10S

Abstract:
A chalcogenide memory cell comprising:a conductive substrate; a layer of a insulative material including an electrode formed on the conductive substrate, the electrode fabricated by a process comprising: onto the conductive substrate material; forming an edge feature in the layer of the first material; applying a layer of the insulative material onto the edge feature of the layer of the first material and the conductive substrate; applying a layer of a third material onto the layer of the insulative material; removing a portion of the layer of the third material; and removing a portion of the layer of the insulative material to define a pore in the layer of the insulative material; applying a layer of a first conductive material into the pore to define an electrode in the layer of the insulative material; a layer of a chalcogenide material formed on the electrode; and a layer of a second conductive material formed on the layer of the chalcogenide material.