Patent ID: 6764896
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device which comprises a capacitor having a lower electrode selectively formed on an underlying layer, a dielectric film covering said lower electrode and an upper electrode opposed to said lower electrode with said dielectric film interposed therebetween, comprising the steps of:(a) forming first and second etching stopper films of silicon nitride and silicon oxide, respectively, in this order as said underlying layer on an interlayer insulating film, and forming a contact plug penetrating said first and second etching stopper films and said interlayer insulating film; (b) forming a conductive film which is to become said lower electrode on said second etching stopper film; (c) forming a hardmask having a pattern corresponding to a plane pattern of said lower electrode on said conductive film; (d) patterning at least said conductive film with said hardmask used as an etching mask and said second etching stopper film as an etching stopper to form said lower electrode; (e) completely removing at least said second etching stopper film other than a portion below said lower electrode with said first etching stopper film used as an etching stopper; and (f) forming said dielectric film and said upper electrode so as to cover said lower electrode and said second etching stopper film remaining below said lower electrode.