Patent ID: 8486831
Filing Date: 2013-07-16
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device, comprising: forming a wiring layer including a plurality of wiring lines, the plurality of wiring lines being arranged in a first direction, each of the plurality of wiring lines extending in a second direction perpendicular to the first direction; forming a first interlayer insulation film to cover the wiring layer; forming a plurality of dummy insulation films above the first interlayer insulation film, such that each of said plurality of dummy insulation films is aligned with a corresponding one of the plurality of wiring lines; forming a second interlayer insulation film over top surfaces of the plurality of dummy insulation films to cover the plurality of dummy insulation films and the first interlayer insulation film; forming a slit groove in the second interlayer insulation film while leaving a portion of the second interlayer insulation film over the top surfaces of the dummy insulation films so that the slit groove continuously extends over the plurality of dummy insulation films in the first direction to expose the plurality of dummy insulation films; forming a plurality of via holes passing through the first and second interlayer insulation films from the slit groove by using the second interlayer insulation film and the plurality of dummy insulation films as a mask; and forming a plurality of via plugs within the via holes.