Patent ID: 6831579
Filing Date: 2004-12-14
Classification: H03K

Abstract:
A latch that transitions from an acquire mode to a latch mode in response to a latch command signal, the latch comprising:cross-coupled first and second isolation transistors that have first and second current terminals with said first current terminals coupled to receive a differential input signal; cross-coupled first and second latch transistors that provide collectors; at least one switch coupled to provide currents to said first current terminals in response to said latch command signal; first and second current-limiting transistors that are each coupled between a respective one of said second current terminals and a respective one of said collectors and that each provide an impedance that transitions from an acquire impedance to a greater latch impedance in response to a corresponding one of control signals Scntrl; and first and second control transistors that each provides one of said control signals Scntrl to a respective one of said current-limiting transistors in response to the one of said collectors that is coupled to that current-limiting transistor.