Patent ID: 8525583
Filing Date: 2013-09-03
Classification: G11C

Abstract:
1. A circuit comprising: a CMOS circuit having NMOS field-effect transistors and having PMOS field-effect transistors; a first load device, wherein source terminals of the NMOS field-effect transistors of the CMOS circuit are connectable via the first load device to a first supply voltage; a second load device, wherein source terminals of the PMOS field-effect transistors of the CMOS circuit are connectable via the second load device to a second supply voltage; and an evaluation circuit configured to: adjust, when a determination is made that the leakage current is predominately due to the PMOS field-effect transistors, a first voltage drop across the first load device; and adjust, when a determination is made that the leakage current is predominately due to the NMOS field-effect transistors, a second voltage drop across the second load device.