Patent ID: 6724646
Filing Date: 2004-04-20
Classification: G11C

Abstract:
A method of sensing an FeRAM 1T1C cell in a read operation requiring only 1 dummy cell for 4 bitlines, comprising:precharging to Â½VCC, a bitline & a bitline-bar associated with a target memory cell and a sense amplifier; initializing to 0 volts, the plate line of an FeRAM dummy cell associated with the target memory cell, and the plate line of the target memory cell; accessing & coupling the charge of the target memory cell to the bitline or the bitline-bar of the sense amplifier associated with the target memory cell; shorting together two bitlines or two bitline-bars associated with the target memory cell and the FeRAM dummy cell, to create a shorted pair of bitlines or bitline-bars; selectively coupling the dummy cell to a select one of the two shorted bitlines or the two shorted bitline-bars associated with the target memory cell and the FeRAM dummy cell, wherein the FeRAM dummy cell comprises a â€œ0â€  state FeCap associated therewith, thereby generating a reference voltage with a reference circuit, which is a function of a charge shared to and divided between the two shorted bitlines or the two shorted bitline-bars; de-coupling the short between the bitlines or bitline-bars associated with the target memory cell; sensing the bitline inputs of the sense amplifier associated with the target memory cell; comparing with the sense amplifier, a sense signal from the target memory cell on one bitline input, to the reference voltage on the other bitline input, wherein the reference voltage is substantially centered between a â€œ0â€  or â€œ1â€  state of an FeRAM memory cell, thereby yielding an accurate sensing of the FeRAM 1T1C cell in a read operation; determining if the target memory cell is a â€œ0â€  or a â€œ1â€  state based on the comparison; applying Â½VCC to the plate line of the FeRAM dummy cell associated with the target memory cell, and the plate line of the target memory cell; accessing the target memory cell via a word line, and the FeRAM dummy cell associated with the target memory cell via a transistor coupled to VSS; recharging the FeRAM dummy cell which is associated with the target memory cell, and the target memory cell via the bitlines associated with the target memory cell, wherein the FeRAM dummy cell recharges to a â€œ0â€  state, and the target memory cell recharges to its former â€œ0â€  or â€œ1â€  state; de-coupling the target memory cell and the FeRAM dummy cell from the associated bitlines so that the capacitance states are maintained; reinitializing to 0 volts, the plate line of the FeRAM dummy cell associated with the target memory cell, and the plate line of the target memory cell.