Patent ID: 9190138
Filing Date: 2015-11-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of bank groups, wherein each of the plurality of bank groups comprises: a first bank; a second bank disposed separately from the first bank along a first direction; a third bank disposed separately from the first bank along a second direction substantially perpendicular to the first direction; a fourth bank disposed separately from the second bank along the second direction and from the third bank along the first direction; a first row control region, which is disposed between the first bank and the second bank, suitable for controlling a row decoding operation of the first bank and the second bank; a second row control region, which is disposed between the third bank and the fourth bank, suitable for controlling a row decoding operation of the third bank and the fourth bank; a peripheral circuit region disposed between the first row control region and the second row control region; a refresh control unit, which is disposed in the peripheral circuit region, suitable for controlling a refresh operation of the first to fourth banks in response to a plurality of control signals; and a target row refresh main control unit suitable for controlling the refresh control unit by providing the plurality of control signals to the refresh control unit.