Patent ID: 8935599
Filing Date: 2015-01-13
Classification: G06F,G11C,H03M

Abstract:
1. A memory system comprising: a flash subsystem grouped into pages of data, the pages of data including error correcting code (ECC) and being identified by page numbers, at least some of the pages of data having a lower page of data and an upper page of data, wherein the lower and upper pages of data form a pair; a flash controller coupled to the flash subsystem, the flash controller configured to split the ECC; and a buffer including a page of data from the at least some of the page of data, the page of data having an upper page of data and a lower page of data and to be programmed into the flash subsystem, wherein at least a segment of the upper page of data or at least a segment of the lower page of data is concatenated with a split ECC.