Patent ID: 7358559
Filing Date: 2008-04-15
Classification: H01L

Abstract:
1. An array of non-volatile memory cells, arranged in a plurality of rows and columns, said array comprising: a substantially single crystalline semiconductive substrate material having a planar surface of a first conductivity type; a plurality of non-volatile memory cells arranged in a plurality of rows and columns in said semiconductive substrate material with each cell for storing a plurality of bits, and with each cell comprising: wherein said cells in the same row have said gate electrode in common, and cells in adjacent rows are separated from one another by said semiconductive substrate material without any isolation material in the substrate between cells in different rows to electrically separate them; wherein said first region extends continuously across a plurality of rows through the semiconductive substrate material and connects to cells in the same column in common, said second region extends continuously across a plurality of rows through the semiconductive substrate material and connects to cells in the same column in common, said first gate electrode extends continuously across a plurality of rows and connects to cells in the same column in common, and said second gate electrode extends continuously across a plurality of rows and connects to cells in the same column in common; and wherein said cell in adjacent columns have said first region in common and said first gate electrode in common.