Patent ID: 6137713
Filing Date: 2000-10-24
Classification: G11C,H01L

Abstract:
A semiconductor storage device comprising:a plurality of memory cells, each said memory cell including first and second switching transistors and a capacitor, the first and second transistors sharing a portion of an active region on a substrate, the capacitor disposed over the shared portion and having a storage node for storing data thereon;a first word line extending over the first switching transistor and functioning as a gate electrode in a first region of the shared portion over the active region in each said memory cell;a second word line extending over the second switching transistor and functioning as a gate electrode in a second region of the shared portion over the active region in each said memory cell;a capacitor contact disposed between the shared portion and the storage node and electrically connecting the shared portion to the storage node in each said memory cell;a first bit line contact disposed over the first switching transistor on the opposite side to the capacitor contact across the first word line and electrically connected to the first region in each said memory cell;a second bit line contact disposed over the second switching transistor on the opposite side to the capacitor contact across the second word line and electrically connected to the second region in each said memory cell;a first bit line disposed over, and electrically connected to, the first bit line contact and crossing the first and second word lines in each said memory cell; anda second bit line disposed over, and electrically connected to, the second bit line contact and crossing the first and second word lines in each said memory cell,wherein the first and second bit line contacts are provided substantially symmetrically about the center of each said memory cell, and wherein in two of the memory cells that are adjacent to each other in a direction parallel to the bit lines, one end of the active region in one of the memory cells is continuous with an associated end of the active region in the other memory cell, andwherein each of the first and second bit line contacts is shared between the adjacent pair of memory cells.