Patent ID: 7512000
Filing Date: 2009-03-31
Classification: G11C,H01L

Abstract:
1. A memory unit, comprising: a first load unit, having a first end coupled to a first voltage, and a second end coupled to a first contact; a second load unit, having a first end coupled to the first voltage, and a second end coupled to a second contact; a first metal-oxide-semiconductor (MOS) transistor, having a first end coupled to the first contact, a second end coupled to a second voltage, and a gate coupled to the second contact; a second MOS transistor, having a first end coupled to the second contact, a second end coupled to a third voltage, and a gate coupled to the first contact; a first non-volatile device having a split-gate structure, and having a control gate coupled to a first control bias voltage, a select gate coupled to a first select bias voltage, a first end coupled to the first contact, and a second end coupled to a first bit line; and a second non-volatile device having a split-gate structure, and having a control gate coupled to a second control bias voltage, a select gate coupled to a second select bias voltage, a first end coupled to the second contact, and a second end coupled to a second bit line.