Patent ID: 8555141
Filing Date: 2013-10-08
Classification: G06F,G11C

Abstract:
1. A flash-memory system comprising: a plurality of blocks and a plurality of pages in each block, at least one page having 2N data memory locations and K spare memory locations; wherein the at least one page is configured to have 2M user data sectors for storing user data, each data sector having 2N−M+L memory locations therein, wherein error-correction code (ECC) data segments are related to and stored adjacent to the corresponding data sectors, wherein metadata is divided up and placed into the ECC data segments, wherein the spare memory locations include a remainder segment configured to be allocated to store additional ECC data or metadata, wherein M, N, L, and K are positive integers, N>M, M≧1, and 1≦L<2N−M.