Patent ID: 7351634
Filing Date: 2008-04-01
Classification: H01L

Abstract:
1. A method for fabricating a dual-trench capacitor of a dynamic random access memory (DRAM) device, comprising: providing a semiconductor substrate having a first pad layer; embedding a shallow trench isolation (STI) structure into the first pad layer and the semiconductor substrate; forming a second pad layer over the first pad layer and the STI structure; etching two adjacent trenches into the first, second pad layers, the STI structure and the semiconductor substrate, wherein the STI structure is between the two adjacent trenches; etching away the second pad layer and a portion of the STI structure between the two adjacent trenches to form a ridge between the two adjacent trenches, wherein the ridge's top is lower than a main surface of the semiconductor substrate; forming an insulation liner on interior surface of the two adjacent trenches including surface of the ridge; forming a first polysilicon layer on the insulation liner within the two adjacent trenches, the first polysilicon layer overlying the ridge; forming a capacitor dielectric layer on the first polysilicon layer; filling the two adjacent trenches with a second polysilicon layer on the capacitor dielectric layer; and etching the second polysilicon layer until the capacitor dielectric layer that is directly above the ridge is exposed.