Patent ID: 9070569
Filing Date: 2015-06-30
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of semiconductor dies that are stacked, each semiconductor die including a plurality of memory cell arrays; and a plurality of input-output bump pad parts respectively located at a central region of each semiconductor die, the input-output bump pad parts providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices, wherein each of the input-output bump pad parts includes a plurality of channel bump pad parts associated with the memory cell arrays, respectively, each of the channel bump pad parts includes a plurality of bump pads that are arranged in a matrix of rows and columns, and the bump pads of each of the channel bump parts include power bump pads dedicated to receive power supply voltages.