Patent ID: 8051349
Filing Date: 2011-11-01
Classification: G01R

Abstract:
1. A link instruction register comprising: A. instruction register circuitry having a serial test data input, a serial output, parallel link control and enable outputs, and control inputs, the instruction register circuitry including a shift register having an input connected to the serial test data input, an output connected to the serial output, and parallel outputs, the instruction register circuitry including an update register and decode logic connected between the parallel outputs of the shift register and the parallel link control and enable outputs; B. multiplexer circuitry having a first data input connected to the serial data input of the instruction register, a second data input connected to the serial output of the instruction register, a control input, and a serial output: and C. AND gate circuitry having a clock input, a shift input, an update input, and a select input, the select input also being connected to the control input of the multiplexer circuitry, the AND gate circuitry having a clock output, a shift output, and an update output connected to the control inputs of the instruction register circuitry.