Patent ID: 6636448
Filing Date: 2003-10-21
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array divided into a plurality of memory cell plates, each memory cell plate having a sub-word driver coupled to a sub-word line disposed in the row direction of the memory cell plate; a main word line disposed in the row direction of the memory cell array and coupled to the sub-word driver in a row of said memory cell plates; each memory cell plate having a plurality of bit lines, each bit line coupled to a sense amplifier; a normal mode of operation in which a sub-word line is selected in each of a plurality of memory cell plates in the row of the memory cell plates and sense amplifiers are activated to receive data provided; and a test mode of operation in which fewer memory cell plates in the row of memory cell plates have selected sub-word lines and activated sense amplifiers than in the normal mode of operation.