Patent ID: 9134628
Filing Date: 2015-09-15
Classification: G03F

Abstract:
1. A method of checking alignment accuracy between a former layer and a later layer on a wafer, comprising: providing an overlay mark, the overlay mark comprises: determining, along a direction perpendicular to the parallel opposite edges of the at least one later pattern, a shift ΔL of the at least one later pattern from a predetermined position where the at least one later pattern would be if no overlay error is present; and calculating, from the shift ΔL, an x-directional overlay error as ΔL·sinα and a y-directional overlay error as ΔL·cosα, wherein the at least one former pattern comprises two former patterns that comprise a first pattern and a second pattern, the at least one later pattern comprises two later patterns that comprises a third pattern and a fourth pattern, the first pattern and the third pattern are disposed in a pair, the second pattern and the fourth pattern are disposed in a pair, and the third pattern and the fourth pattern are disposed between the first pattern and the second pattern.