Patent ID: 6323676
Filing Date: 2001-11-27
Classification: H04L

Abstract:
An ESD protection circuit for providing protection for a node against an electrostatic discharge, comprising:a bottom ESD protection transistor having a first node coupled to a first potential and a bottom ESD protection transistor intrinsic diode reverse biasedly coupling said node to a first reference voltage supply;a bottom threshold reference transistor coupled to the first reference voltage supply wherein the bottom threshold reference transistor provides a first bias voltage to said bottom ESD protection transistor gate that biases said bottom clamping transistor gate at about a first threshold voltage from said first reference voltage, said first threshold voltage representing a threshold voltage of said bottom ESD protection transistor;a top ESD protection transistor having a second node coupled to a second potential and a top ESD protection transistor intrinsic diode reverse biasedly coupling said node to a second reference voltage supply; anda top threshold reference transistor coupled to the second reference voltage supply wherein the top threshold reference transistor provides a second bias voltage to said top ESD protection transistor gate that biases said top clamping transistor gate at about a second threshold voltage below said second reference voltage, said second threshold voltage representing a threshold voltage of said top ESD protection transistor, wherein during an electrostatic discharge event having an associated ESD voltage, the top and the bottom intrinsic diodes provide a bypass current path to the second and the first reference voltages, respectively, such that a node voltage transient is substantially reduced over the ESD voltage.