Patent ID: 7669041
Filing Date: 2010-02-23
Classification: G06F

Abstract:
1. A processor comprising: a plurality of execution units with more than one output port to execute instructions in parallel where some of the supported instructions produce results on all of the output ports and some of the instructions produce results only on a subset of the output ports; a plurality of register files each associated with one or more of the execution units; and selection circuitry to select an instruction execution result from a first one of the execution units when an instruction on the first one of the execution units produces results on all of the output ports associated with the first one of the execution units or to select the content of a register within a first one of the register files associated with the first one of the execution units to be stored within a register within a second one of the register files when an instruction on the first one of the execution unit produces results only on a subset of the output ports associated with the first one of the execution units.