Patent ID: 8782579
Filing Date: 2014-07-15
Classification: G06F

Abstract:
1. A connection verification method performed in a computer, the method comprising: verifying, by the computer, a connection between a first node and a second node by starting from the first node in a designed integrated circuit in a logical path search, based on connection information stored in a storage part; detecting, by the computer, whether a module connected to the second node is a predetermined module which has a logic condition for continuing the logical path search and is set as a logical path origin; conducting, by the computer, a connection verification starting the module to verify a connection between the module and a third node, by setting the module as the logical path origin when the module is the predetermined module; setting, by the computer, a loop detection flag for the module when a passage flag is set for the module; detecting, by the computer, the module where the loop detection flag is not set in a group of circuits which operate by the same power source; and determining, by the computer, a path from the module to a next node to be a power domain boundary, when the next node to be connected by starting from the module is a node other than an external terminal.