Patent ID: 8542529
Filing Date: 2013-09-24
Classification: G11C

Abstract:
1. In an array of nonvolatile memory cells, wherein each memory cell is programmable relative to one of a series of demarcation threshold voltages that corresponds to one of multiple memory states, a method of sensing in parallel via associated bit lines a group of the memory cells, comprising: (a) selecting a previously unselected demarcation threshold voltage in the series, as a selected demarcation threshold voltage relative to which cycles of alternate program and verify phases are to be performed; (b) setting up the memory cells to be program-inhibited in the group of memory cells by setting the bit lines of the memory cells to be program-inhibited to a first predetermined voltage while setting up the memory cells to be programmed in the group of memory cells by setting the bit lines of the memory cells to be programmed a second predetermined voltage at a beginning of the program phase; (c) programming the group of memory cells in parallel with a programming pulse; (d) discharging the bit lines of the memory cells that have not been program-inhibited; (e) sensing the group of memory cells in parallel to determine if each of the memory cells has been program-verified; (f) repeating (b) to (e) until all the memory cells have been programmed beyond the selected demarcation threshold voltage; (g) repeating (a) to (f) until all demarcation threshold voltage in the series have been selected.