Patent ID: 8561001
Filing Date: 2013-10-15
Classification: G06F,G11B,G11C,H03K

Abstract:
1. A system for compensating for a delay defect in a die stack having a first and a second die, the system comprising: said first die comprising: a first data storage circuit; a first path for passing information to said first data storage circuit, said first path having a first path slack value and said first path having a known defect value; and a repair circuit operatively connected to said first data storage circuit; and said second die operatively connected to said first die, said second die comprising: a second data storage circuit; and a second path for passing information from said first data storage circuit to said second data storage circuit, said second path having a second path slack value, wherein said repair circuit delays a clock signal to said first data storage circuit by a predetermined amount if said defect value is greater than said first path slack value and if said defect value is less than or equal to said second path slack value.