Patent ID: 9129708
Filing Date: 2015-09-08
Classification: G11C,H03K

Abstract:
1. An integrated circuit comprising: at least one logic circuit in a first voltage domain corresponding to a first supply voltage provided to the integrated circuit; and at least one memory circuit coupled to the logic circuit, wherein the at least one memory circuit comprises a plurality of static random access memory (SRAM) cells in a second voltage domain corresponding to a second supply voltage provided to the integrated circuit, and wherein the memory circuit is configured to be read and written responsive to the logic circuit even in the case that a first supply voltage magnitude of the first supply voltage is less than a second supply voltage magnitude of the second supply voltage during use, and wherein the second supply voltage is greater than or equal to a third supply voltage magnitude during use, wherein the third power supply voltage magnitude is at least a supply voltage magnitude that is required for robust operation of the memory circuit.