Patent ID: 7196909
Filing Date: 2007-03-27
Classification: H01L,H01P,H05K,Y02P

Abstract:
1. A coupling circuit for connecting a co-planar line provided on a ceramic substrate to an integrated circuit in a bare chip shape, said coupling circuit comprising: a die capacitor connecting said co-planar line to said integrated circuit, said die capacitor having a first electrode facing to and being in contact with said co-planar line and a second electrode wire-bonded to said integrated circuit; and a chip capacitor connecting said co-planar line to said integrated circuit, said chip capacitor having a first electrode in direct contact with said co-planar line and a second electrode in direct contact with said second electrode of said die capacitor, wherein said die capacitor is mounted in an end portion of said co-planar line such that an edge of said die capacitor sticks out from an edge of said co-planar line.