Patent ID: 9214187
Filing Date: 2015-12-15
Classification: G11B

Abstract:
1. A system for cycle-slip resilient iterative read channel operation, the system comprising a processor and logic integrated with and/or executable by the processor, the logic being adapted to: execute cycle-slip detection on a block of signal samples to detect one or more cycle-slip events employing a set of decisions provided by a detector executing a detection algorithm to produce one or more cycle-slip pointers indicating a cycle-slip event; execute one or more additional digital front-end (DFE) functions on the block of signal samples employing the set of decisions provided by the detector executing the detection algorithm; execute a decoding algorithm of an error correcting code (ECC) on the signal samples using a decoder employing the set of decisions provided by the detector to generate a set of decisions provided by the decoder; store the signal samples, the set of decisions provided by the detector, and the set of decisions provided by the decoder; and in an iterative process until a maximum number of iterations has been reached or a valid codeword is produced: