Patent ID: 6946696
Filing Date: 2005-09-20
Classification: H01L

Abstract:
1. A double-gate field effect transistor (DGFET) comprising: a doped back plane region comprising P-polysilicon or N-polysilicon and having, isolation regions located adjacent to portions of said doped back-plane region; a back-gate dielectric located atop a surface portion of said doped back-plane region not containing said isolation regions; a Si-containing layer having ledges located atop back-gate dielectric, each of said ledges including a source/drain extension region; a front gate dielectric located atop portions of said Si-containing layer; a front gate comprising a NFET or PFET located atop said front gate dielectric, said front gate having spacers on sidewalls thereof; and source/drain regions located adjacent to said front gate and over said isolation regions, said source/drain regions are in contact with source/drain extension regions, wherein when said doped back-plane region comprises P-polysilicon, said front gate is said NFET or when said doped back-plane region comprises N-polysilicon, said front gate is said PFET.