Patent ID: 9118314
Filing Date: 2015-08-25
Classification: H03K

Abstract:
1. A semiconductor integrated circuit (IC) comprising: first through fourth logic blocks each comprising at least one adaptive body bias (ABB) circuit; a plurality of main clock signal lines through which a clock signal is transmitted to the first through fourth logic blocks; and a plurality of main bias lines that are arranged in pairs with the plurality of main clock signal lines and at a predetermined distance from the plurality of main clock signal lines, and shield the main clock signals from crosstalk due to other adjacent signal lines, wherein a bias voltage is applied to the first through fourth logic blocks through the plurality of main bias lines, wherein the ABB circuit comprises: a logic circuit performing logic calculations; a local clock signal line that is connected to the main clock signal lines to transmit the clock signal to the logic circuit; and at least one local bias line that is connected to the main bias lines to apply the bias voltage to the logic circuit, and is arranged at a predetermined distance from the local clock signal line, and shields the local clock signal from crosstalk due to other adjacent signal lines, wherein the bias voltage is a voltage applied to a body of a MOS transistor constituting the logic circuit.