Patent ID: 6654303
Filing Date: 2003-11-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory block including a plurality of memory cells each including a transistor and a capacitor and storing information based on the presence of charges in the capacitor, the charges in the capacitor being held by a refresh operation, the memory block being divided into a plurality of memory banks such that the number of the memory banks is greater than a usually-prescribed number and the plurality of memory banks are not simultaneously accessed, the plurality of memory banks individually receiving access and refresh operations with respect to the memory cells; a time measurement section for measuring a critical amount of time for the memory cells to hold data; a plurality of memory circuits each storing refresh information which indicates that a corresponding memory bank is refreshed; a refresh address designation section for designating a refresh address in the corresponding memory bank; and a refresh control section for controlling the refresh operation with respect to each of the memory banks according to the designated refresh address and determining an unrefreshed memory bank based on the refresh information so as to perform the refresh operation with respect to the determined unrefreshed memory bank.