Patent ID: 7148565
Filing Date: 2006-12-12
Classification: H01L

Abstract:
1. A three-dimensional (3-D) vertically stacked wafer structure, comprising: a first wafer including an active device layer comprised of silicon to support one or more integrated circuit (IC) devices; a second wafer including an active layer to support one or more integrated circuit (IC) devices; metallic lines deposited on opposing surfaces of the first and second wafers at designated areas to establish metal bonding between the first and second wafers in a stack and electrical connections between active IC devices on the first and second wafers in the stack; and one or more interwafer vias formed within the first wafer through the silicon active device layer, to provide electrical connections between active IC devices on the first and second wafers in the stack and an external interconnect, wherein each of the interwafer vias comprises: