Patent ID: 9153496
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit comprising: forming a plurality of silicon fin structures on a semiconductor substrate; epitaxially growing a silicon material on the fin structures and forming a merged source/drain region on the fin structures as a result of said epitaxial growing, the merged source/drain region being defined as epitaxial growths on two neighboring fins structures of the plurality of fins structures joining together to form a contiguous epitaxial growth; and anisotropically etching the merged source drain region and forming an un-merged source/drain region as a result of said anisotropic etching, the un-merged source/drain regions being defined as the epitaxial growths on two neighboring fin structures of the plurality of fin structures that are noncontiguous and have open space between the epitaxial growths.