Patent ID: 6542099
Filing Date: 2003-04-01
Classification: H03M

Abstract:
A digital to analog interface with equalized total signal delay comprising:a plurality of unit digital to analog converter cells, each having a clock input and an analog output; a clock input distribution network for propagating a clock input to said unit cells tapped along said distribution network; an analog output network for summing the analog outputs from each unit cell and propagating the sum signal along the network to a first termination; said analog outputs being delayed from cell to cell by a first predetermined time interval defined by the combination of said analog output network and said first termination; and a second termination connected to said clock input distribution network for establishing said clock input distribution network as a transmission line and defining in combination with said clock input distribution network a second predetermined time interval delay between the clock inputs to said unit cells equal to said first predetermined time interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.