Patent ID: 6674093
Filing Date: 2004-01-06
Classification: G02F,H01L

Abstract:
An active matrix substrate comprising:(a) a gate electrode layer, a gate insulating layer and an amorphous silicon semiconductor layer deposited in a substantially stacked fashion on a transparent insulating substrate, viewed from a direction normal to said transparent insulating substrate, to form a layered structure including a gate electrode, a gate wiring and a thin-film transistor area; (b) a drain wiring formed on a first passivation film disposed on said substrate so as to cover said layered structure; (c) a second passivation film formed as a layer overlying said drain wiring and said first passivation film; (d) source/drain openings passing through said first passivation film and said second passivation film to reach said amorphous silicon semiconductor layer; (e) an opening passing through said second passivation film to reach said drain wiring; and (f) a wiring layer formed by a pixel electrode film disposed on said second passivation film, said wiring layer extending through said opening and openings for connection.