Patent ID: 8934281
Filing Date: 2015-01-13
Classification: G11C

Abstract:
1. A data storage device, comprising: an array of memory cells arranged into rows and columns, each memory cell comprising a switching device in series with a resistive random access memory (RRAM) element; and a controller configured to execute a first bit set operation comprising placing a first group of the memory cells in a lowest resistance state and to subsequently direct a writing of first user data from the host device to the array by overwriting the lowest resistance state of at least one and less than all of the first group of the memory cells, and to execute a second bit set operation comprising placing a second group of the memory cells in a highest resistance state and to subsequently direct a writing of second user data from the host device to the array by overwriting the highest resistance state of at least one and less than all of the second group of the memory cells.