Patent ID: 7283538
Filing Date: 2007-10-16
Classification: H04L

Abstract:
1. A scalable network gateway processor architecture comprising: a) a scalable array of compute processors implementing a protocol processing function to convert inbound data packets to outbound data packets; b) an ingress processor coupleable to a first network to receive said inbound data packets and coupled to provide said inbound data packets to said scalable array of compute processors, said ingress processor distributing said inbound data packets to said scalable array of compute processors based on a least load value selected from current load values determined for the respective compute processors of said scalable array of compute processors; and c) an egress processor coupleable to a second network and coupled to said scalable array of compute processors to collect outbound data packets from said scalable array of compute processors and send said outbound data packets to said second network, wherein said current load values represent estimated processing completion times for the respective compute processors of said scalable array of compute processors, wherein said current load values are of said inbound data packets to outbound data packets from said ingress processor to said egress processor through said scalable array of compute processors, wherein said ingress processor updates a predetermined one of said current load values on distribution of a predetermined data packet based on the size of said predetermined data packet and the performance data accumulated with respect to a distribution corresponding one of said scalable array of compute processors, and wherein the update of said predetermined one of said current load values is based on an interpolation of the performance data accumulated with respect to a distribution corresponding one of said scalable array of compute processors.