Patent ID: 7969507
Filing Date: 2011-06-28
Classification: G09G,H03L,H04N

Abstract:
1. A video signal receiver comprising: a video processor for converting an input analog video signal into a digital signal; a display processor for scaling the video signal converted at the video processor with an output resolution; a displaying unit for displaying the video signal scaled by the display processor; a detecting unit for detecting whether an input vertical synchronization signal (In V-sync) and an output vertical synchronization signal (Out V-sync) of the analog video signal match; a PLL (Phase Locked Loop) for adjusting a pixel clock according to a detection result of the detecting unit; wherein the detection result adjusts the pixel clock according to a control signal by affecting a scaling coefficient in the PLL; and a timing generating unit for generating an output horizontal synchronization signal and the output vertical synchronization signal by use of the pixel clock adjusted by the PLL, and providing the generated output horizontal and output vertical synchronization signals to the display processor and the detecting unit.