Patent ID: 7003541
Filing Date: 2006-02-21
Classification: H04L

Abstract:
1. A system comprising a first mechanism for proving equality or inequality of two discrete logarithms and a second mechanism for verifying said equality or inequality, wherein the first mechanism comprises: a first public information memory storing a designated operation scheme, two input numbers (hereinafter, denoted by α and β), and two predetermined bases (hereinafter, denoted by g and h); a private information memory storing private information (hereafter, denoted by x) which is a discrete logarithm of α to the base g; a random number generator for generating a first random number (hereafter, denoted by r); a converter for converting the input number α, the input number β and the base h to produce α′, β′ and γ′ using the first random number r and the private information x as follows:  wherein said α′, β′ and γ′ are sent to the second mechanism; and a proving section for proving equality of a discrete logarithm of α′ to base α and a discrete logarithm of β′ to base β and equality of a discrete logarithm of α′ to the base g and a discrete logarithm of γ′ to the base h, and the second mechanism comprises: a second public information memory storing the designated operation scheme, the two input numbers α and β, and the two predetermined bases g and h; a verifying section corresponding to the proving section, for verifying equality of a discrete logarithm of the received α′ to base α and a discrete logarithm of the received β′ to base β, and equality of a discrete logarithm of the received α′ to the base g and a discrete logarithm of the received γ′ to the base h; a checking section for checking the received β′ and γ′ to determine equality of inequality thereof; and a decision section for deciding whether proof of the first mechanism is acceptable, depending on results of the verifying section and the checking section.