Patent ID: 6370162
Filing Date: 2002-04-09
Classification: H04J,H04Q

Abstract:
A frame aligner comprising:a serial/parallel converter for receiving an input serial data signal and converting said input serial data signal into a first parallel data signal; a first buffer, connected to said serial/parallel converter, for receiving said first parallel data signal to generate a first parallel data signal; a second buffer, connected to said first buffer, for receiving said first parallel data signal to generate a second parallel data signal; a selector, connected to said first and second buffers, for selecting one of said first and second parallel data signals to generate a third parallel data signal; a parallel/serial converter, connected to said selector, for receiving said third parallel data signal and converting said third parallel data signal into an output serial data signal; a buffer control circuit, connected to said first and second buffers, for operating said first and second buffers at different phase timings in accordance with an input frame phase signal; and a selector control circuit, connected to said selector, for operating said selector in accordance with a difference in phase between said input frame phase signal and an output frame phase signal.