Patent ID: 7239546
Filing Date: 2007-07-03
Classification: G11C

Abstract:
1. A semiconductor device, comprising: a semiconductor memory circuit arranged in a central area of a chip; a plurality of IO blocks which are arranged in a periphery of the chip, each inputting and outputting a signal, a supply potential or a ground potential; and a nonvolatile semiconductor memory circuit which is arranged in the periphery of the chip used for a redundant repair function of said semiconductor memory circuit, wherein said nonvolatile semiconductor memory circuit comprises a nonvolatile memory device constituted of an electrically readable and writable CMOS device, a control circuit for producing a control signal which controls writing to said nonvolatile memory device according to an address signal, an address signal line for supplying said address signal to said control circuit, an input data line for supplying data written to said nonvolatile memory device synchronizing with said control signal, an output data line for outputting data having been written to said nonvolatile memory device to said semiconductor memory circuit, wherein; said plurality of IO blocks is arranged in a ring shape along the periphery of the chip, and said nonvolatile semiconductor memory circuit is arranged between adjacent IO blocks of said plurality of IO blocks.