Patent ID: 6175532
Filing Date: 2001-01-16
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of memory blocks each including a word line, bit line pairs and memory cells connected to the bit line pairs;a plurality of sense amplifier bands provided corresponding to said plurality of memory blocks, each of said plurality of sense amplifier bands including a plurality of sense amplifiers each coupled to a bit line pair in a corresponding memory block;a plurality of local data buses provided corresponding to said plurality of sense amplifier bands respectively;a plurality of selectors provided corresponding to said plurality of local data buses respectively, each of said plurality of selectors including a plurality of column selection circuits each for providing data amplified by a sense amplifier in a corresponding sense amplifier band to a corresponding local data bus in response to a column selection signal transmitted by a column select line extending along a direction of extension of the word line;a plurality of column decoders provided corresponding to said plurality of selectors respectively, each for providing the column selection signal to a corresponding selector; anda global data bus coupled in common to said plurality of local data buses.