Patent ID: 8793632
Filing Date: 2014-07-29
Classification: G06F

Abstract:
1. A method, comprising: generating, using a data processing system, a directed graph that represents an interconnect segment of an integrated circuit design; determining, using the data processing system, a highest potential node of nodes of the directed graph that represents the interconnect segment; determining, using the data processing system, a lowest potential node of the nodes of the directed graph that represents the interconnect segment; calculating, using the data processing system, a potential difference between a first potential associated with the highest potential node and a second potential associated with the lowest potential node; determining, using the data processing system, if the potential difference is less than one half of a critical potential difference; and if the potential difference is less than one half of the critical potential difference, indicating, using the data processing system, that the interconnect segment of the integrated circuit design passes.