Patent ID: 8122197
Filing Date: 2012-02-21
Classification: F04D,F24F,G06F,G09G,H04L,H05K,Y02B

Abstract:
1. Hardware apparatus configured to clean data from a cache and configured to assist achieving cache coherence in a message passing parallel computer including a multitude of processing nodes, each of the processing nodes including first and second non-coherent processing elements, where the first processing element is principally performing calculations, while the second processing element is performing message passing activities, and each of said first and second processing elements having a respective cache memory area, the hardware apparatus comprising: a memory controller configured to create, in a physical memory address space of one of the processing nodes, an area of virtual memory that (a) does not actually exist, and (b) is therefore configured to respond instantly to read and write requests from the processing elements; and said memory controller displacing modified data in the cache memory areas of the first and the second processing elements with garbage data that the first and the second processing elements will not use.