Patent ID: 6862676
Filing Date: 2005-03-01
Classification: G06F

Abstract:
1. A superscalar processor for performing out of order processing on an instruction set having a plurality of instructions and a plurality of architectural registers associated therewith, the superscalar processor comprising: at least one execution unit for executing a plurality of in-flight instructions of the instruction set; a plurality of registers; a fetch unit for fetching the instructions from the instruction set; an instruction renaming unit (IRU) for renaming architectural registers to physical registers during the processing of the instruction set wherein the instruction set comprises one or more instructions whose data sources and destinations are registers; an instruction scheduling unit (ISU) for scheduling the in-flight instructions for execution, the ISU including a dependency matrix for storing dependency data of all the in-flight instructions and an instruction wait buffer (IWB) for storing physical address data and operation codes necessary to execute the in-flight instructions when the dependency matrix indicates that the dependencies of the in-flight instructions have been removed; and a content addressable memory (CAM) structure having a comparator section mapped to an array section, the CAM structure transmitting a first output signal for generating the dependency data stored in the dependency matrix and a second output signal for generating the physical register address data stored in the IWB.