Patent ID: 6323713
Filing Date: 2001-11-27
Classification: G06F,H03L

Abstract:
A clock signal generating circuit for generating a clock signal of a frequency lower than a constant signal frequency of a constant frequency signal, obtained by division of the constant signal frequency, comprising:a memory in which a plurality of frequency division data has been stored, the plurality of frequency division data representing an amount of the division of the frequency of the constant frequency signal;a memory control circuit for controlling sequential and repetitive read out of each of said frequency division data stored in said memory;a frequency dividing counter for obtaining a count value by counting the number of pulses of said constant frequency signal and resetting said count value to an initial value when said count value coincides with said frequency division data read out from said memory; anda circuit for forming a signal whose logic level is inverted each time said frequency division data read out from said memory and said count value coincide, and generating it as said clock signal.