Patent ID: 7409530
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. A method of processing a compressed-length VLIW instruction on a processor having a very long instruction word architecture, the processor comprising a plurality of clusters, each one cluster of the plurality of clusters comprising a plurality of functional processing units, a VLIW instruction including at least one subinstruction and a set of control bits including a first prescribed condition which designates a respective one of the functional processing units for each subinstruction, the method comprising the steps of: i. identifying a identical subinstructions appearing in a plurality of fields of a given VLIW instruction and further identifying functional processing units corresponding to the plurality of fields in which the identical subinstructions appear; ii. preparing a compressed-length VLIW instruction by reducing the identified identical subinstructions to a single identified subinstruction in the given VLIW instruction and modifying the set of control bits of the compressed-length VLIW instruction to include a subinstruction sharing condition which designates the corresponding functional processing units for the single identified subinstruction; iii. loading the compressed-length VLIW instruction into a cache; iv. testing the set of control bits of the compressed-length VLIW instruction in the cache to determine one or more functional processing units that are configure to execute each of the at least one subinstruction included in the compressed-length VLIW, wherein each one functional processing unit of the plurality of functional processing units of each cluster receives one of a no-operation subinstruction or a subinstruction expressly included among the at least one subinstruction; v. routing at least one expressly included subinstruction to non-corresponding functional processing units as determined by the first prescribed condition of the set of control bits; vi. routing at least one expressly included subinstruction to multiple functional processing units as determined by a second prescribed condition of the set of control bits, wherein the routing for the second prescribed condition is different than for the first prescribed condition; and vii. executing the compressed-length VLIW instruction as distributed among the plurality of functional units of each cluster by concurrently executing the subinstructions received at the plurality of functional processing units of each cluster.