Patent ID: 7636077
Filing Date: 2009-12-22
Classification: G02F,G09G,G11C,H01L

Abstract:
1. A gateline driver for use in a display panel, comprising: a main shift register module having a plurality of N shift registers, where N is an integer greater than one, each register having an input and an output and wherein the shift registers are interconnected in a cascade link such that the input of a shift register k is connected to the output of a shift register k−1 with k being a positive integer smaller than N; and a backup shift register module having at least a first backup shift register and at least a second backup shift register, wherein for each shift register i among the N shift registers, a normally open connectable link is positioned between the input of the shift register i and the input of the first backup shift register, and a normally open connectable link is positioned between the input of the shift register i+1 and the output of the first backup shift register, where i is a positive odd integer from 1 to N if N is odd and from 1 to N−1 if N is even; and for each shift register j among the N shift registers, a normally open connectable link is positioned between the input of the shift register i and the input of the second backup shift register, and a normally open connectable link is positioned between the input of the shift register j+1 and the output of the second backup shift register, where j is a positive even integer from 2 to N if N is even and from 2 to N−1 if N is odd, so that if the shift register i is defective, the link between the input of the shift register i and the input of the first backup register is connected, the link between the input of the shift register i+1 and the output of the first backup register is connected, and the input and the output of the shift register i are disconnected from the cascade link, and if the shift register j is defective, the link between the input of the shift register j and the input of the second backup register is connected, the link between the input of the shift register j+1 and the output of the second backup register is connected, and the input and the output of the shift register j are disconnected from the cascade link.