Patent ID: 9141299
Filing Date: 2015-09-22
Classification: G06F,Y02D

Abstract:
1. A method of reducing power consumption in a solid-state storage device, comprising: providing a storage controller and a plurality of non-volatile memory packages, the storage controller and zero or more of the non-volatile memory packages being arranged on a first power island, and at least one of the non-volatile memory packages being arranged on a second power island; upon entering a predetermined reduced power state of the solid-state storage device, storing, by the storage controller, context information for the solid-state storage device in at least one memory buffer within the non-volatile memory package on the second power island, and removing power from at least the non-volatile memory packages on the first power island; and once the context information is stored in the memory buffer within the non-volatile memory package on the second power island, placing the non-volatile memory package on the second power island in a standby mode, and placing the storage controller on the first power island in a predefined low power mode.