Patent ID: 6440844
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device comprising the steps of:forming a first insulating layer on a semiconductor substrate; forming a first trench in a surface of said first insulating layer; forming a first wiring layer, including a main wiring layer essentially consisting of copper, in said first trench, the first wiring layer having a top surface recessed from that of said first insulating layer; forming an interlayer insulating film on said first insulating layer, covering said first wiring layer, said interlayer insulating film having planarizing function for forming a substantially planar surface on a stepped surface; forming a connection hole through said interlayer insulating film, exposing said first wiring layer; filling said connection hole with a conductive plug including a buried conductor essentially consisting of tungsten; and forming a second wiring layer connected to said conductive plug, the second wiring layer including a main wiring layer essentially consisting of copper, wherein each of said steps of forming said first wiring layer and said second wiring layer includes sputtering a barrier layer made of at least one material selected from the group consisting of TiN, TaN, WN, TiSiN, TiSi and TiW, and sputtering a copper or copper alloy on the barrier layer.