Patent ID: 7012842
Filing Date: 2006-03-14
Classification: G11C

Abstract:
1. A method of operating a memory cell comprising a storage node coupled between a pull-up element and a pull-down element, the method comprising: applying a first bias signal to at least one of the pull-up element and the pull-down element to attenuate an NDR operational characteristic of the at least one of the pull-up element and the pull-down element and set the storage node to an intermediate voltage; writing a data value to the memory cell by adjusting the storage node from the intermediate voltage to one of an upper voltage and a lower voltage; and applying a second bias signal to the at least one of the pull-up element and the pull-down element to enable the NDR operational characteristic of the at least one of the pull-up element and the pull-down element to latch the data value into the memory cell.