Patent ID: 6730974
Filing Date: 2004-05-04
Classification: H01L,Y10S

Abstract:
A semiconductor device equipped with a memory cell including a first load transistor, a second load transistor, a first driver transistor, a second driver transistor, a first transfer transistor, and a second transfer transistor, comprising:a first conductivity type well region extending along a first direction; a word line extending along the first direction over the first conductivity type well; and a first element-forming region provided in the first conductivity type well region, wherein the first element-forming region includes a first active region, a second active region, a third active region, a fourth active region, and a fifth active region, wherein the third active region, the fourth active region and the fifth active region are provided between the first active region and the second active region, and wherein the first active region and the second active region are continuous with the third active region, the fourth active region and the fifth active region, respectively, a first driver transistor in the first memory cell and a second driver transistor in the second memory cell formed in the first active region, a second driver transistor in the third memory cell and a first driver transistor in the fourth memory cell formed in the second active region, a second transfer transistor in the second memory cell and a second transfer transistor in the third memory cell formed in the third active region, and a first transfer transistor in the first memory cell and a first transfer transistor in the fourth memory cell formed in the fifth active region.