Patent ID: 8949757
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. A method to design a circuit, the method comprising: selecting a target clock for a design of the circuit; determining a plurality of latencies for a portion of the circuit; representing the portion of the circuit by a data flow graph comprising a first node connected with a second node by an edge, the edge connecting the first node and second node representing paths that start from and end in registers in the portion of the circuit, the first node connecting to a third node representing paths between a first input of the portion of the circuit and an input of a register of the portion of the circuit, wherein the second node connects to a fourth node that represents signal delay which is not smaller than signal delay on any path that contains no registers and that is between a first output of the portion of the circuit and an output of a register of the portion of the circuit; determining a number of extra delays on the edge of the data flow graph using the target clock for the circuit according to the plurality of latencies for the portion of the circuit, the circuit being greater than the portion; and retiming the design for the circuit to operate at the target clock using the representation of the data flow graph, wherein at least one of the selecting, determining, and retiming is performed by a processor.