Patent ID: 6226765
Filing Date: 2001-05-01
Classification: G01R

Abstract:
An event based test system for testing an electronics device under test (DUT), comprising:a clock count memory for storing clock count data of each event which is an integer multiple of a reference clock period (integral part data), said clock count data being formed of one or more data words depending on the value of the integral part data, and at least one data word including a flag to indicate whether the next word being needed, a number of vernier data attached to a current event, and at least a part of the integral part data;a vernier data memory for storing vernier data of each event which is a fraction of the reference clock period (fractional part data), said vernier data memory storing vernier data for two or more events in the same memory location;an address sequencer for generating address data for accessing said clock count memory and said vernier data memory to read out said clock count data and said vernier data therefrom; anda decompressor for reproducing the clock count data from the clock count memory and the vernier data from the vernier data memory corresponding to each event.