Patent ID: 7275146
Filing Date: 2007-09-25
Classification: G06F

Abstract:
1. An instruction control method for an information processor which includes a reservation station for registering a plurality of decoded instructions and a plurality of update buffers for register renaming, comprising: when a decoded preceding instruction is a store instruction which stores data, reserved in a first register or a first update register allocated to said first register for register renaming, into a first memory address, preserving said first memory address, a number of said first register and a number of said first update buffer, separate from said reservation station; when a subsequent instruction is an operational instruction which uses data read out from a second memory address, detecting a coincidence between said first memory address and said second memory address, upon execution of said subsequent instruction; substituting a number of a second update buffer, which is specified in an entry of said subsequent instruction registered in said reservation station for storing data read out from said second memory address, with said preserved number of said first update buffer; substituting a number of a second register, which is specified in said entry of said subsequent instruction registered in said reservation station, with said preserved number of said first register, upon detecting said coincidence; and executing operation of said subsequent instruction using data preserved in said first update buffer or in said first register, instead of said data in said second memory address, upon said substitution.