Patent ID: 6426951
Filing Date: 2002-07-30
Classification: H04Q

Abstract:
A device (SRS) for switching input data frames (IDF) from a plurality of N input lines (i1, i2, . . . in, iN) to output data frames (ODF) on a plurality of M output lines (o1, o2, . . . on, oM), comprising:a) a frame memory (FSB) for storing input data frames; b) a switch pattern memory (SPM) for storing a predetermined switch pattern (SP); and c) a control means (CU) for selecting bits from bit positions (0-255) in said stored input data frames and for assigning said selected bits to bit positions (0-255) on output data frames according to said stored predetermined switch pattern (SP); wherein d) said frame memory (FSB) comprises a number j=2 to K of frame memories (FSB1, FSBj, FSBK) each storing all input data frames of all input lines; e) said switch pattern memory (SPM) comprises a number of j=2 to K of switch pattern units (SPM1, SPMj, SPMK) each storing a predetermined switch pattern (SP) associated with a respective one of said frame memories; and f) said control means (CU) is provided for sequentially selecting a respective number of M/K bits from input data frames stored in a j-th frame memory, with j=1 to K, according to a respective switch pattern stored in an associated j-th switch pattern unit (SPMj), and for assigning said selected bits to bit positions simultaneously on output data frames on a predetermined output line sub-group including M/K output lines.