Patent ID: 7170327
Filing Date: 2007-01-30
Classification: H01L

Abstract:
1. A data-retention circuit fabricated on a semiconductor die comprising: data-retention subcircuits; a supply-switching subcircuit to decouple the data-retention subcircuits from a regular voltage supply during standby mode; and an isolation subcircuit to isolate the data-retention subcircuits from a pass-gate subcircuit in response to a sleep signal, wherein the supply-switching subcircuit has a well tap coupled to the data retention subcircuits and the semiconductor die has a resistive n-well coupling a supplemental supply voltage to the well tap, wherein during standby mode, the supplemental supply voltage biases the resistive n-well allowing leakage current to flow from the supplemental supply voltage through the resistive n-well to the well tap to bias the data-retention subcircuits to allow the data-retention subcircuits to remain powered and retain their state, wherein the data-retention subcircuits, the supply-switching subcircuit and the isolation subcircuit comprise lower-leakage semiconductor devices, and wherein the pass-gate subcircuit comprises higher-leakage semiconductor devices, the lower-leakage devices having at least one of a longer channel length, a thicker gate-oxide layer or a higher threshold voltage than the higher-leakage semiconductor devices.