Patent ID: 6021066
Filing Date: 2000-02-01
Classification: G11C

Abstract:
A non-volatile random access memory (NVRAM) comprising:an array including a plurality of sub-arrays, each of said sub-arrays including a plurality of pairs of NVRAM cells, each of said pairs of NVRAM cells comprising:a pair of word line select devices connected at a first conduction terminal to a bit line and gated by a word line,a pair floating gate devices, each of said pair of floating gate devices connected at a first conduction terminal to a second conduction terminal of one of said pair of word line devices,a first control gate capacitively coupled to a floating gate of a first of said pair of floating gate devices and a second control gate capacitively coupled to a floating gate of the second of said pair of floating gate devices, anda pair of source devices each having a first conduction terminal connected to a second conduction terminal of one of said pair of floating gate devices; anda pair of source lines connected to each of said sub-arrays, a first of each said pair of source lines gating first ones of said pair of source devices in each of said plurality of pairs of NVRAM cells in said sub-array and the second of said pair of source lines gating second ones of said pair of source devices in each of said plurality of pairs of NVRAM cells in said sub-array.