Patent ID: 8934277
Filing Date: 2015-01-13
Classification: H01L,H02M

Abstract:
1. A semiconductor system comprising: a first semiconductor device, a second semiconductor device, a third semiconductor device and a fourth semiconductor device, the semiconductor devices being at least four devices forming at least one of three-level electric power inverter circuits; a plurality of insulating substrates on each of which at least one each of the first semiconductor device to the fourth semiconductor devices is mounted; and a base plate on the surface of which a plurality of the insulating substrates are arranged, wherein the surface of the base plate on which a plurality of the insulating substrates are arranged has four regions established into which the surface is divided in grid-like, wherein a plurality of the insulating substrates are arranged so that at least one each of the first semiconductor devices to the fourth semiconductor devices is arranged in each of the four regions to thereby disperse heat generated in the first to fourth semiconductor devices, wherein the three-level electric power inverter circuit formed on a plurality of the insulating substrates arranged on the surface of the base plate comprises: a first insulated gate bipolar transistor as the first semiconductor device the collector of which is connected to a positive side potential of a direct current circuit; a second insulated gate bipolar transistor as the second semiconductor device the emitter of which is connected to a negative side potential of the direct current circuit and the collector of which is connected to the emitter of the first insulated gate bipolar transistor; a bidirectional switching device one end of which is connected to the connection point of the emitter of the first insulated gate bipolar transistor and the collector of the second insulated gate bipolar transistor: a first external connection terminal connected to the collector of the first insulated gate bipolar transistor for connecting the collector to the positive side electric potential of the direct current circuit; a second external connection terminal connected to the other end of the bidirectional switching device: a third external connection terminal connected to the second external connection terminal to be at the same potential as the potential thereof; a fourth external connection terminal connected to the emitter of the second insulated gate bipolar transistor for connecting the emitter to the negative side electric potential of the direct current circuit: and a fifth external connection terminal connected to the connection point of the emitter of the first insulated gate bipolar transistor and the collector of the second insulated gate bipolar transistor, and wherein the three-level electric power inverter circuit formed on a plurality of the insulating substrates arranged on the surface of the base plate further comprises a case of a mold of resin covering the base plate from which case the first external connection terminal, second external connection terminal, third external connection terminal, fourth external connection terminal and fifth external connection terminal are drawn out while being arranged in a straight line in the longitudinal direction, the case comprising: a pair of auxiliary terminals for the gate and emitter, respectively, of the first insulated gate bipolar transistor arranged on one of the opposing two sides of the case with the first to the fifth external connection terminals arranged in a straight line put in between; a pair of auxiliary terminals for the gate and emitter, respectively, of the second insulated gate bipolar transistor arranged on the one of the opposing two sides; a pair of auxiliary terminals for the gate and emitter, respectively, of the third insulated gate bipolar transistor arranged on the other one of the opposing two sides; and a pair of auxiliary terminals for the gate and emitter, respectively, of the fourth insulated gate bipolar transistor arranged on the other one of the opposing two sides, a pair of the auxiliary terminals for the gate and emitter of the third insulated gate bipolar transistor and a pair of the auxiliary terminals for the gate and emitter of the fourth insulated gate bipolar transistor being arranged at specified positions regardless of the connections and the arrangements of the semiconductor devices of the three-level electric power inverter circuits.