Patent ID: 6147534
Filing Date: 2000-11-14
Classification: H03K

Abstract:
A circuit implementing an OR logic function with a first and second input signal, comprising:a first switching device having a gate receiving a reset signal, a source coupled to a supply line of the circuit, and a drain;a second switching device having a gate receiving said first input signal, a drain coupled to the drain of said first switching device at a first node, and a source, said first node providing an output signal;a third switching device having a gate receiving said second input signal, a drain coupled to said first node, and a source;a fourth switching device having a gate, a drain coupled to the source of said second switching device and to the source of said third switching device, and a source coupled to ground;a first logic gate having a first input receiving said output signal, a second input, and an output;a second logic gate having a first input coupled to the output of said first logic gate, a second input, and an output;an inverter coupling the gate of said fourth switching device to the output of said second logic gate and to the second input of said first logic gate;a third logic gate having a first input coupled to the first input signal, a second input coupled to said second input signal, and an output coupled to said second input of said second logic gate, whereby said output signal is active when either the first or second input signals are active.