Patent ID: 6373744
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A ferroelectric memory, in which data is stored by allowing an internal control signal produced based on an external input control signal to conform electrical polarization of a ferroelectric capacitor to a logical state of data, comprising a memory control section including:a divided potential generating circuit for generating a divided potential, which is divided based on a source voltage with a constant ratio; a reference potential generating circuit for generating a constant reference potential, which is independent of the source voltage, the constant reference potential being in accordance with a predetermined detection level for the source voltage; a differential amplifier circuit for outputting logical voltage according to a potential difference between the reference potential and the divided potential; and control signal producing means for producing the internal control signal based on the external input control signal and a logical voltage from the differential amplifier circuit, wherein the memory control section is configured such that when the source voltage is detected as being lower than the detection level based on a logical voltage from the differential amplifier circuit, regardless of the state of said external input control signal, the stored data is protected with the internal control signal produced based on a logical voltage from the differential amplifier circuit.