Patent ID: 7834663
Filing Date: 2010-11-16
Classification: G11C,H03K

Abstract:
1. A register receiving an input signal and providing output signals that represent true complementary logic values of the input signal, comprising: a first stage circuit receiving the input signal and feedback signals, and providing true and complementary intermediate signals derived from the logic value of the input signal when the feedback signals are deactivated, wherein the input signal is independent of a clocking signal, wherein the input signal is independent of a clocking signal; and a second stage circuit receiving the clocking signal, the true and complementary intermediate signals, and the feedback signals, wherein (a) during a first phase of the clocking signal, the second stage circuit deactivates the feedback signals and precharges the output signals; and (b) during a second phase of the clocking signal, the second stage circuit derives the output signals from the true and complementary intermediate signals and thereafter activates the feedback signals to block further propagation of the logic value of the input signal by the first stage circuit to the second stage circuit.