Patent ID: 6764954
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of applying alignment marks to a semiconductor wafer, the method comprising:producing a non-metal intricate structure in a large-area metal layer in at least one area of the semiconductor wafer by forming depressions in a surface area of the semiconductor wafer, lands being formed between the depressions, and subsequent deposition of the metal layer over the entire surface area; and planarizing the area of the semiconductor wafer having the large-area metal layer by means of chemical-mechanical polishing, so that the non-metal intricate structure stands out from the large-area metal layer after the polishing process; an additional intermediate layer being applied between the semiconductor surface and the metal layer; the planarization being carried out in two stages by means of chemical-mechanical polishing, in the first stage the metal layer being removed and being stopped on the intermediate layer lying underneath and, in the second stage, the intermediate layer being removed and stopped in the lands lying underneath; and the first stage being designed in such a way that overpolishing of the metal surfaces between the projecting lands is carried out, the intermediate layer on the projecting lands also being partly removed at the same time, and the second stage being designed in such a way that intensive overpolishing of the intermediate layer is carried out, in which erosion of the lands lying underneath takes place, so that trenches result between the metal surfaces.