Patent ID: 8759968
Filing Date: 2014-06-24
Classification: G11C,H01L

Abstract:
1. A multi-chip package, comprising: a plurality of semiconductor memory apparatuses stacked on a substrate in stair-type configuration, each having a plurality of pads exposed along first edges thereof; a plurality of bonding wires, each electrically connecting the plurality of pads to the substrate; an encapsulant material formed on the substrate and molding the semiconductor memory apparatuses and the bonding wires; and a pad control section configured in each of the plurality of semiconductor memory apparatuses to control signal transmission between the plurality of pads and a corresponding one of the plurality of semiconductor memory apparatuses, wherein each of the plurality of semiconductor memory apparatuses includes first and second pad groups provided along opposing edges when viewed along a direction in which the substrate extends, the first and second pad groups receive signals from the plurality of pads, and the second pad group performs substantially same function as the first pad group, and wherein the pad control section is configured to provide first and second bonding signals for controlling signals from the first and second pad groups to be selectively employed in response to a test mode signal and a bonding option signal.