Patent ID: 8435865
Filing Date: 2013-05-07
Classification: H01L

Abstract:
1. A method of manufacturing a super-junction semiconductor device, the method comprising: forming an alignment mark in a semiconductor substrate comprising a major surface coinciding with an (001) plane, the alignment mark comprising a trench having a side wall perpendicular to the substrate major surface; growing an epitaxial layer above the semiconductor substrate; patterning a resist using the alignment mark transferred to a surface of the epitaxial layer; implanting p-type ions and n-type ions; repeating a cycle comprising the growing, the patterning, and the implanting multiple times; and conducting a thermal treatment for forming an alternating conductivity type layer comprising a p-type column and an n-type column, both extending in perpendicular to the substrate major surface, the p-type column and the n-type column being arranged alternately and repeatedly in parallel to the substrate major surface such that the p-type column and the n-type column are adjoining to each other, the forming comprising: providing the alignment mark with a trench structure comprising parallel linear planar patterns, forming the alignment marks used in the multiple times of the cycles collectively at different positions, and setting a mesa region width between adjacent trenches in the trench structure used for the alignment mark in each cycle to be at least one-fourth of a designed total epitaxial layer thickness at an end of the growing in said each cycle.