Patent ID: 8045414
Filing Date: 2011-10-25
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines intersecting each other, each of the memory cells comprising an antifuse element comprising a MOS transistor, the MOS transistor including a first terminal, a second terminal, and a gate electrode formed on a gate insulating film, and a select transistor connected between the second terminal and one of the bit lines, and being selectively turned on; a row decoder configured to receive a writing instruction signal and a reading instruction signal to selectively activate one of the word lines according to an input state of a row address signal; a data buffer configured to receive a data input signal and drive corresponding one of the bit lines when the writing instruction signal is received, and amplify a minute reading signal transmitted to one of the bit lines to output a data output signal when the reading instruction signal is received; and a power supply circuit configured to supply a certain voltage to the first terminal of the memory cell, wherein the data buffer drives the corresponding one of the bit lines to a first voltage while the power supply circuit supplies a second voltage higher than the first voltage to the first terminal when the writing instruction signal is received, whereas the data buffer drives the corresponding one of the bit lines to a third voltage while the power supply circuit supplies a fourth voltage lower than the third voltage to the first terminal when the reading instruction signal is received.