Patent ID: 7601586
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method of forming buried bit line DRAM circuitry comprising: forming an insulative mass over a semiconductor substrate; in a first masking step, forming a plurality of via openings through the insulative mass to conductive node locations, at least one of the conductive node locations being a memory array bit line node, at least one of the conductive node locations being a memory array storage node; after forming the plurality of via openings, in a second masking step forming at least one buried bit line-forming trench within the insulative mass, the buried bit line-forming trench overlying the one via to the memory array bit line node; depositing conductive material to within the buried bit line-forming trench, the one via to the memory array bit line node, and the one via to the memory array storage node effective to form a conductively interconnected mass of conductive material which comprises a bit line in the buried bit line-forming trench, a contact to the memory array storage node, and a contact to the bit line node; the depositing comprising depositing conductive elemental titanium, a conductive nitrogen-containing compound, and conductive elemental tungsten into said buried bit line-forming trench, said one via to the memory array bit line node, and said one via to the memory array storage node, said conductively interconnected mass having an outer region comprising the elemental titanium, nitrogen-containing compound, and elemental tungsten; and removing a quantity of the outer region including some of each of the conductive elemental tungsten, the conductive nitrogen-containing compound, and the conductive elemental titanium of the conductively interconnected mass of conductive material at least to the insulative mass effective to electrically isolate the bit line from the contact to the memory array storage node.