Patent ID: 6377507
Filing Date: 2002-04-23
Classification: G11C

Abstract:
An integrated circuit non-volatile memory device comprising:a page of non-volatile memory cells arranged in a plurality of sub-pages of non-volatile memory cells electrically coupled to a respective plurality of word lines, and a plurality of bit lines; a first multiplexer/de-multiplexer circuit electrically coupled to said plurality of bit lines and for interfacing with a plurality of first multiplexed lines; a plurality of current sensing amplifiers, each having an input line and an output line with said input line coupled to a first multiplexed line; each current sensing amplifier, having a pitch corresponding to a first plurality of bit lines, for sharing the sensing of memory cells from said first plurality of bit lines; said plurality of current sensing amplifiers for generating a plurality of sensed signals supplied along said plurality of output lines; a second multiplexer/de-multiplexer circuit electrically coupled to said plurality of output lines, and for interfacing with a plurality of second multiplexed lines; a plurality of page latches electrically, each having a latch input line and a latch output line with said latch input line coupled to a second multiplexed line; each page latch having a pitch corresponding to a second plurality of bit lines for sharing the storage of data to or from non-volatile memory cells of said second plurality of bit lines; said plurality of page latches for storing a plurality of data; an I/O data buffer coupled to said latch output lines of said plurality of page latches; and read controller circuit for initiating a read operation to read data from said page of non-volatile memory cells by said plurality of current sense amplifiers, while simultaneously for transferring data from said page latches to said I/O data buffer.