Patent ID: 6723603
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method utilizing a fabrication process of poly-Si spacers to build a flash memory with two bits/cell, comprising the steps of:a. forming a pad oxide layer on a semiconductor substrate and a patterned silicon nitride layer on said pad oxide layer; b. performing ion implantation to said substrate to form doped regions using said patterned silicon nitride layer of step a as a mask; c. subsequent to step b, depositing an oxide on said substrate then planarizing said oxide to remove a sufficient portion of said oxide to expose said patterned silicon nitride layer; d. substantially removing said patterned silicon nitride layer, using said planarized oxide to define a floating gate device region, and then removing an underlying portion of said pad oxide layer to expose surface portions of said substrate; e. depositing a tunnel dielectric layer on said surface portions of said substrate exposed in step d; f. depositing a first poly-Si layer on said substrate to cover said planarized oxide and said tunnel dielectric layer; g. performing an anisotropic etch to said first poly-Si layer to form poly-Si spacers at two sides of said planarized oxide; and h. subsequent to step g, depositing an insulating dielectric layer on said substrate and then forming a patterned second poly-Si layer on said insulating dielectric layer to define a control gate.