Patent ID: 6728667
Filing Date: 2004-04-27
Classification: G06F

Abstract:
A method of verifying functionality of an integrated circuit design prior to manufacture by simultaneously conducting simulation testing of a plurality of simulated electronic device designs using cycle-based simulation software which is capable of simultaneously executing a plurality of simulation tests along separate test pathways for each said simulated device, in which the simulated device designs each comprise essentially identical sequences of instructions, the method comprising:providing a memory device which holds a matrix of memory bits, in which each row of said matrix holds a plurality of data words each made up of a plurality of bits; designating a single bit location of said data words of said memory device for each said test of each said simulated device; grouping said designated bit locations into a number of groups equal to the number of simulated electronic device designs being tested; conducing said simulation tests on each said simulated device design for each group at substantially the same time; and during the conduct of said simulation tests, storing test results for each said test in said designated bit location for said test, to allow testing to simultaneously occur along one or more test pathways for each said simulated electronic device design, with the quantity of such simultaneous tests equal to no more than the number of bits in a row of said matrix of memory bits of said memory device.