Patent ID: 8473873
Filing Date: 2013-06-25
Classification: G03F,G06F

Abstract:
1. A method comprising: (a) receiving data representing a layout of a multi-patterned layer (DPT-layer) of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving an identification of a first one of the plurality of polygons that is to be formed using a first photomask and a second one of the plurality of polygons that is to be formed using second photomask; (c) identifying any intervening polygons of the plurality of polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path; (d) counting the separator regions; and (e) identifying a multi-patterning conflict if the count of separator regions along the first path is even, prior to assigning all remaining ones of the plurality of polygons to the first or second photomasks.