Patent ID: 9189591
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. In an electronic design automation (EDA) tool, a method for computing a timing effort metric, the method comprising: upon receipt of a circuit design layout that includes two circuit objects, computing a physical distance between the two circuit objects; computing a timing distance of a timing path between the two circuit objects, wherein the timing distance of the timing path is equal to an intrinsic path slack of the timing path multiplied by a scaling factor, wherein the intrinsic path slack is based on an intrinsic delay of the timing path between the two circuit objects, wherein the intrinsic delay of the timing path is a sum of intrinsic delays of circuit elements along the timing path, and wherein the scaling factor is based on a physical distance that corresponds to a unit delay; and computing, by using one or more processors, the timing effort metric based on the physical distance and the timing distance, wherein the timing effort metric indicates a level of difficulty of fixing a timing violation associated with the timing path between the two circuit objects in the circuit design layout.