Patent ID: 8797073
Filing Date: 2014-08-05
Classification: H03L

Abstract:
1. A delay locked loop (DLL) circuit comprising: a timing pulse generating unit configured to generate a plurality of timing pulses pulsed sequentially for delay shifting update periods in response to a source clock, wherein the number of the generated timing pulses changes according to a change in a frequency of the source clock during an operation of the DLL circuit; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay duplication modeling unit configured to delay an output clock of the clock delay unit by an actual delay of the internal clock path, and to output the delayed clock as the feedback clock.