Patent ID: 8816403
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A device layout for a semiconductor device comprising: a plurality of cells, at least a first cell of said cells comprising: a first metal interconnect level including a plurality of parallel signal lines and power mesh leads formed of a lowermost metal level that extends between and couples said cells, wherein each of said plurality of parallel signal lines and power mesh lines extend and couple said cells along a longitudinal cell direction; a polysilicon level subjacent said first metal interconnect level and including polysilicon features therein and a void area void of polysilicon and including therein, local conductive lines connecting said parallel signal lines to active device regions formed at a level below said polysilicon level, said local conductive lines disposed beneath said first metal interconnect level and completely contained within said void area, wherein said cells each have a length defining said longitudinal direction and a cell width being less than said length, said local conductive lines each have a length longer than a line width thereof and couple laterally spaced apart features.