Patent ID: 6088288
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A CMOS memory device with reduced ground bounce comprising:A. bitcells arranged in an array of rows and columns with one bitcell at the intersection of each row and column;B. column write enable signal terminals receiving column write enable signals;C. a write driver circuit for each column of bitcells, the write driver circuits being connected in series to the column write enable signal terminals, and each write driver circuit driving one column of bitcells in response to receiving the column write enable signals;D. column delay circuits connected in series with the write driver circuits connection to the column write enable signal terminals selectively delaying the applying the column write enable signals to the write driver circuits;E. row enable signal terminals receiving a row write enable signal for each row of bitcells;F. a series connection of the bitcells in each row to one row enable signal terminal to apply the row write enable signal to all of the bitcells in that row; andG. row delay circuits connected in series with the bitcells in that row selectively delaying the applying the row write enable signals along the serial connection to the bitcells.