Patent ID: 6172633
Filing Date: 2001-01-09
Classification: H03M

Abstract:
An apparatus comprising:a first circuit configured to generate a first control signal and a second control signal in response to (i) a digital input signal and (ii) a clock signal;a second circuit configured to generate a third control signal by scrambling said first control signal; anda third circuit comprising (a) a tristate inverting buffer configured to generate a pulse modulated output signal in response to (i) a most significant bit of said second control signal and (ii) an enable signal, (b) an enable circuit configured to generate said enable signal in response to the result of a logical combination of (i) a pulse signal and (ii) said most significant bit of said second control signal and (c) a comparator configured to generate said pulse signal in response to (i) said second control signal and (ii) said third control signal.