Patent ID: 6304962
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A method for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution, comprising the steps of:(a) controlling the fetch mechanism to begin fetching at a starting address of a current superblock, wherein a superblock includes a set of instructions in consecutive address locations terminated by a branch instruction known to have been taken;(b) supplying a Superblock Target Buffer (Swith the starting address of the current superblock, the STB having a plurality of entries each indexed by a starting address of a superblock and including a run length of the superblock and a target address of the terminating branch of the superblock, the run length corresponding to a sum of a length of the terminating branch and a difference between a starting address of the terminating branch of the superblock and the starting address of the superblock;(c) determining whether the starting address of the current superblock supplied to the STB matches a starting address indexing an STB entry;(d) determining a starting address of a next sequential superblock by summing the starting address of the current superblock and the run length specified in the STB entry, when the starting address of the current superblock supplied to the STB matches the starting address indexing the STB entry; and(e) controlling the fetch mechanism to end fetching at the starting address of the next sequential superblock.