Patent ID: 6458697
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device having at least two via holes which vertically meet each other, said method comprising:forming a first via hole in a first interlayer insulating film; forming a barrier metal on a surface of the first interlayer insulating film and a side wall and bottom of the first via hole; filling the first via hole with a first conductive material, by depositing the first conductive material on the barrier metal; filling, with a filling material, a void, which is formed inside the first via hole by filling the via hole with the first conductive material; etching said barrier metal which is formed on the surface of the first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film; forming a second via hole and removing the filling material from the void, by etching an area above the first via hole of the second interlayer insulating film; and filling the second via hole and the void with a second conductive material.