Patent ID: 6058470
Filing Date: 2000-05-02
Classification: G06F

Abstract:
A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode method for setting and testing conditions with specialized update and branch instructions comprising the steps of: storing in an internal code array milli-mode routines as said set of millicode simple instructions, and when milli-mode detection logic coupled to instruction registers of said processor detects that a macro-instruction, which is being decoded, is of a type that is to be interpreted in said milli-mode architected operating state then said milli-mode architected state is enabled with a milli-mode recognition signal and macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers, whereupon a milli-mode entry point address is generated to address the millicode stored in said internal code array which are fetched from said internal code array and sent to said processor instruction registers whereupon the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode, and whereupon on entry to a milli-mode millicode routine one or more Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and this Translate Fetch instruction uses information in general registers, the condition code, and the millicode flags to generate the required values and to update the processor's general register 1, general register 2, and the condition code, as required by ESA/390 architecture; andwherein said Translate Fetch (TRFET) instruction is employed for the contents of MGR pairs (R&sub1., R&sub1.+1) and (R&sub2., R&sub2.+1), the condition code, and millicode flags are used to form the result values (program GR1, program GR2, and program condition code) for an ESA/390 Translate and Test (TRT) instruction, whereupon the MGR pair (R&sub1., R&sub1.+1) must contain the result of a Translate Fetch (TRFET) millicode instruction in which a non-zero result byte was found (i.e. CC&ne.0); MGR R&sub2. must contain the current value of program GR2; and MGR R&sub2.+1 must contain the address of the byte of operand 1 (from the TRT instruction) which was translated to the leftmost byte of MGR R&sub1. by TRFET.