Patent ID: 7075852
Filing Date: 2006-07-11
Classification: G11C

Abstract:
1. A sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, comprising: a first NMOS transistor and a first PMOS transistor which are connected in series; and a second NMOS transistor which is connected with a node between said first PMOS transistor and said first NMOS transistor, wherein a source of said first PMOS transistor is connected with a sub word line inverted signal obtained by inverting said sub word line signal, and a source of said first NMOS transistor is connected with a first negative voltage, a single main word line signal is connected to a gate of said first PMOS transistor and a gate of said first NMOS transistor, and said sub word line signal is connected with a gate of said second NMOS transistor; wherein: a source of said second NMOS transistor is connected with said first negative voltage; said first PMOS transistor and said first NMOS transistor have a first threshold voltage and a second threshold voltage, respectively, and said second NMOS transistor has a third threshold voltage which is higher than said second threshold voltage.