Patent ID: 8555143
Filing Date: 2013-10-08
Classification: G06F

Abstract:
1. A flash memory controller, comprising: a flash memory interface controller, configured to store information data, error correction code (ECC) segments, and linked-lists to a flash memory and read information data, ECC segments, and the linked-lists from the flash memory; a host interface controller, configured to forward information data to a host and to receive information data from the host; a random-access memory (RAM) interface controller, configured to store the linked-lists to a RAM device and read the linked-lists from the RAM device; an ECC encoder, configured to receive a write information datum from the host interface controller and generate an ECC datum, of which the length is variable, in response to the write information datum to be stored in the flash memory when operated in a write mode; an ECC divider, configured to divide the generated ECC datum into a plurality of ECC segments according to the length of the generated ECC datum and forward the divided ECC segments to the flash memory interface controller when operated in a write mode; an ECC constructor configured to receive a plurality of ECC segments from the flash memory interface controller and construct an ECC datum by combining the received ECC segments for a read information datum received from the flash memory when operated in a read mode; and an ECC decoder configured to correct errors of the read information datum based on the read information datum and the constructed ECC datum and forward the corrected read information datum to the host interface controller when operated in a read mode; wherein the link relation of the ECC segments in the flash memory is indicated by the linked-lists.