Patent ID: 7269084
Filing Date: 2007-09-11
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: memory cells that store data by accumulating or discharging an electric charge; a memory cell array that has a plurality of the memory cells disposed in a matrix; a plurality of word lines that are connected to the memory cells arrayed in rows of the memory cell arrays; a plurality of bit lines that are connected to the memory cells arrayed in columns of the memory cell arrays; a plurality of dummy cells that are arrayed in a row direction of the memory cell arrays and are connected to the bit lines; sense amplifiers that detect data within the memory cells by using an average value of voltages of the dummy cells as a reference signal, the dummy cells storing mutually different digital data; and a plurality of switching elements that electrically connect four or more of the bit lines in order to generate the reference signal, wherein the switching elements are provided to correspond to each of the bit lines, one end of each switching element is connected to a corresponding bit line, and the other ends of the switching elements are connected together.