Patent ID: 8030205
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and in the openings; performing a first etching process to etch the first conductive layer to form interconnection layers in the openings, wherein the interconnection layers are formed inside the openings and at a depth from a top of the openings; performing a second etching process on portions of the metal barrier layer exposed after the first etching process to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings, wherein the second etching process removes the metal barrier layer throughout the top of the inter-layer insulation layer to expose the inter-layer insulation layer underneath and the sloped profile of the metal barrier layer has a rounded cusp; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers, and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines, wherein the second etching process comprises a dry etching process using a main etch gas for physicochemically etching the metal barrier layer and an additional gas for chemically etching the metal barrier layer and, in the dry etching process, a flow of the additional gas is controlled to be approximately one tenth a flow of the main etch gas or approximately one twentieth the flow of the main etch gas.