Patent ID: 6756299
Filing Date: 2004-06-29
Classification: H01L

Abstract:
A process for fabricating a semiconductor device, said process comprising:forming, above a lower wiring, an interlayer dielectric comprised of a low dielectric-constant insulating material, forming on said interlayer dielectric, a photosensitive insulating film; exposing and developing said photosensitive insulating film to form a hard mask comprised of said photosensitive insulating film on said interlayer dielectric, wherein said hard mask defines a wiring pattern for an upper wiring and a position of a via hole for said lower wiring; depositing a resist film above said interlayer dielectric having thereon said hard mask to form a resist mask having a via hole pattern for said lower wiring using a photolithography technique; subjecting part of said interlayer dielectric to anisotropic etching using said resist mask to form part of a via hole; and removing said resist mask, and then subjecting said interlayer dielectric to anisotropic etching using said hard mask to allow said via hole to reach said lower wiring so that said lower wiring is exposed, and to form a wiring trench for said upper wiring above said via hole so as to be in communication with said via hole.