Patent ID: 8835225
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method for fabricating a quad flat non-leaded (QFN) semiconductor package, comprising the steps of: providing a copper carrier and forming thereon a die pad and a plurality of I/O connections disposed at a periphery of the die pad; applying energy to the copper carrier, the die pad, and the I/O connections so as for copper atoms to migrate and diffuse to bottom surface of the I/O connections and a bottom surface of the die pad to thereby form a surface layer; mounting a chip on a top surface of the die pad; electrically connecting the chip and the I/O connections through a plurality of bonding wires; forming an encapsulant on the copper carrier to encapsulate the die pad, the I/O connections, the chip, and the bonding wires; removing the copper carrier to expose the surface layer; and forming a dielectric layer on a bottom surface of the encapsulant, and the surface layer, the dielectric layer having a plurality of openings for exposing the surface layer.