Patent ID: 9070758
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A CMOS compatible method for manufacturing a Group III-nitride HEMT having a gate electrode and Au-free source and drain ohmic contacts, comprising: a) providing a substrate; b) forming a stack of Group III-nitride layers on the substrate; c) forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of Group III-nitride layers, wherein the first passivation layer is deposited at a temperature between 900° C. and 1250° C. by a first chemical vapor deposition technique, and wherein the first passivation layer is deposited in-situ with the stack of Group III-nitride layers; d) forming a dielectric layer overlying and in contact with the first passivation layer, the dielectric layer comprising a high-k dielectric material; e) forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer, wherein the second passivation layer is deposited at a temperature higher than 450° C. by a second chemical vapor deposition technique; and thereafter f) forming source and drain ohmic contacts, and a gate electrode in such a way that a gate dielectric is formed comprising the first passivation layer and at least part of the dielectric layer, wherein forming source and drain ohmic contacts comprises patterning source and drain ohmic contact regions by selectively etching the second passivation layer, the dielectric layer, and the first passivation layer, and forming ohmic contacts by deposition of an Au-free metal layer, patterning the metal layer, and forming an ohmic alloy at a temperature between 500° C. and 850° C. and below a crystallization temperature of the high-k material of the gate dielectric, wherein forming the gate electrode comprises patterning a gate trench by selective etching of the second passivation layer towards the dielectric layer and forming the gate electrode in the gate trench by deposition of a metal gate layer and patterning the metal gate layer such that the second passivation layer is thinner in an exposed region between an edge of the gate electrode and the source and drain contacts when compared to an original thickness as-deposited in regions covered by the gate electrode.