Patent ID: 6455377
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A method of fabricating a vertical channel transistor, comprising the steps of:a) providing a semiconductor substrate having an upper surface; b) forming a high doped N-type lower epitaxial silicon layer on said semiconductor substrate; c) forming a low doped P-type middle epitaxial silicon layer on said lower epitaxial silicon layer; d) forming a high doped N-type upper epitaxial silicon layer on said middle epitaxial silicon layer; e) etching said lower, middle, and upper epitaxial silicon layers to form a epitaxial layer stack defined by isolation trenches; f) forming oxide within said isolation trenches; g) etching said oxide to form a gate trench within one of said trenches exposing a sidewall of said epitaxial layer stack facing said gate trench; h) forming multi-quantum wells or a strained-layer super lattice on said exposed epitaxial layer stack sidewall; i) forming a gate dielectric layer on said multi-quantum wells or said strained layer super lattice and within said gate trench; and j) forming a gate conductor layer on said gate dielectric layer, filling said gate trench.