Patent ID: 6074917
Filing Date: 2000-06-13
Classification: H01L,Y10S

Abstract:
A method of forming a flash memory cell, comprising:forming a tunnel oxide on a substrate;forming a first polysilicon layer over the tunnel oxide;forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by low pressure chemical vapor deposition at a temperature from about 600.degree. C. to about 850.degree. C. using SiH.sub.4 and N.sub.2 O, and annealing in an N.sub.2 O atmosphere at a temperature from about 700.degree. C. to about 950.degree. C.;forming a second polysilicon layer over the insulating layer;etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; andforming a source region and a drain region in the substrate, thereby forming at least one memory cell.