Patent ID: 8001356
Filing Date: 2011-08-16
Classification: G06F

Abstract:
1. An integrated circuit system, comprising: a memory processor configured to receive logical memory addresses from a host and output physical addresses in response thereto; and a non-volatile memory in communication with the memory processor to receive the physical addresses from memory processor to access memory locations of the non-volatile memory corresponding to respective ones of the physical addresses, wherein the integrated circuit system is responsive to a user selecting a value to adjust a user useable capacity, as viewed by the host, of the non-volatile memory, based upon a likelihood of a frequency of write operations to the integrated circuit system; and configured to store, in the non-volatile memory system, an updated partitioning parameter in response to the selected value, wherein the memory processor is configured to receive a command by a host to adjust the user usable capacity, as viewed by the host, of the non-volatile memory, and wherein the integrated circuit system is responsive to the stored updated partitioning parameter to adjust a partitioning ratio of the user usable capacity and a capacity of a reserved memory, modifying the reserved memory capacity of the non volatile memory in response to the partitioning parameter, the reserved memory including replacement memory for defective blocks.