Patent ID: 6060909
Filing Date: 2000-05-09
Classification: H03K

Abstract:
A compound domino logic circuit for providing a logical output based upon at least two input signals comprising:a dynamic logic section including a clock source providing a clock signal defining an evaluate mode during each high clock cycle and a precharge mode during each low clock cycle, said dynamic logic section including at least two input nodes for receiving at least two input signals during each said evaluate mode, said dynamic logic section including an output driver input node for providing an dynamic output signal during each said evaluate mode, said dynamic logic section including a clocked field effect transistor coupled to said output driver input node for isolating said dynamic logic section from an output driver section, andsaid output driver section receiving said dynamic output signal and providing said logical output signal, said output driver section including a first inverter having an input connected to said output driver input node and a second inverter connected in series with said first inverter; said second inverter having an input connected to an output of said first inverter and having an output providing said logical output signal; and said output driver section including a latch for maintaining said output signal during a next precharge mode of said dynamic logic section;wherein said output driver section latch is provided by a tristate feedback device connected across said first inverter, an input of said tristate feedback device connected to said output of said first inverter and an output of said tristate feedback device connected to said input of said first inverter.