Patent ID: 9202921
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A semiconductor device having a dual channel transistor, comprising: a semiconductor island isolated by at least a first shallow trench isolation extending along a first direction and a second shallow trench isolation extending along a second direction, wherein the first shallow trench isolation intersects the second shallow trench isolation; a gate trench extending along the second direction and recessed into the semiconductor island; a gate extending along the second direction and disposed at the gate trench; a first dielectric layer encapsulating the gate in the gate trench; a first source/drain regions disposed along the second direction and disposed with respect to a top surface of the semiconductor island; a second dielectric layer whose bottom is higher than that of the gate trench, embedded in the semiconductor island and disposed between the first source/drain regions; a first U-shaped channel region disposed around the second dielectric layer and between the first source/drain regions; a second source/drain regions disposed along the second direction and disposed with respect to the top surface of the semiconductor island; a third dielectric layer embedded in the semiconductor island and between the second source/drain regions; and a second U-shaped channel region disposed around the third dielectric layer and between the second source/drain regions.