Patent ID: 7629827
Filing Date: 2009-12-08
Classification: G06F

Abstract:
1. A semiconductor integrated circuit having a clock distribution circuit including a plurality of subordinate clock trees, comprising: a first subordinate clock tree; a second subordinate clock tree; a phase-locked loop for comparing a reference clock and an output clock of a first end clock driver contained in the first subordinate clock tree; a first phase comparator for comparing an output clock of the first end clock driver with an output clock of a second end clock driver contained in the second subordinate clock tree; and a first variable delay circuit provided for corresponding to the second subordinate clock tree, wherein a clock with a phase adjusted by the phase-locked loop is inputted to the clock distribution circuit, a clock delayed by the first variable delay circuit is inputted to the second sub block tree, an amount of delay of the first variable delay circuit is controlled by the first phase comparator so that a phase of an output clock of the first end clock driver becomes equal to a phase of an output clock of the second end clock driver, and a relative position of the second end clock driver in the end clock driver of the second subordinate clock tree equals to a relative position of the first end clock driver in the end clock driver of the first subordinate clock tree.