Patent ID: 7820517
Filing Date: 2010-10-26
Classification: H01L

Abstract:
1. In a metal-oxide semiconductor device comprising first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device, the method comprising the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation subject to a constraint that a breakdown voltage in the device be greater than or equal to a prescribed value wherein the shielding structure is spaced laterally from the gate and is configured to overlap at least an edge of the gate.