Patent ID: 8446011
Filing Date: 2013-05-21
Classification: H01L

Abstract:
1. A semiconductor device comprising: first bit lines, wherein each of the first bit lines has an upper surface and a lower surface, with the upper surface being more outwardly located over a surface of a semiconductor than the lower surface; and a second bit line, wherein the second bit line has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the surface of the semiconductor than the lower surface, and wherein the upper surface of the second bit line is more outwardly located over the surface of the semiconductor than the upper surfaces of the first bit lines, wherein the first bit lines are each adjacent to the second bit line, the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled, and the second bit line does not overlap any of the first bit lines.