Patent ID: 7522611
Filing Date: 2009-04-21
Classification: H04L

Abstract:
1. A packet switch for receiving and transmitting datagrams, the datagrams including binary message data and binary service data, the binary service data having routing directives, comprising: input ports for respectively receiving incoming datagrams traveling along physical transmission links outside the packet switch, the input ports each having maximum transmission rates prescribed for incoming datagrams, each input port comprising: output ports for respectively transmitting datagrams to second physical transmission links outside the packet switch, the output ports each having maximum transmission rates prescribed for outgoing datagrams, each output port comprising: a buffer memory having: a sequencer paced by a clock, for performing managements including managing the addressing, data and read-write control buses of the buffer memory, and managing accesses of the demodulation and the send management circuits to the buffer memory, said managements including the operations of: a routing automaton for analyzing the binary service data included in the datagrams that are stored temporarily in the buffer memory, so as to extract from the routing directives, a broadcasting profile determining which output ports a datagram is to be dispatched to, and executing said dispatching through the send management circuits of the output ports identified by the broadcasting profile, wherein the sequencer performs management of the accesses of the input ports and of the output ports to the buffer memory, including: