Patent ID: 6180994
Filing Date: 2001-01-30
Classification: H01L

Abstract:
An antifuse array formed on a semiconductor material of a first conductivity type, the array comprising:a plurality of spaced-apart bit lines formed in the semiconductor material that extend across the array, the bit lines having a second conductivity type;a layer of insulation material formed on the semiconductor material over the bit lines, the layer of insulation material having a plurality of openings that expose a plurality of bit line regions on each bit line, the openings being arranged in rows and columns;a plurality of spaced-apart contacts formed on the bit line regions such that each contact is connected to an exposed bit line region;a layer of isolation material formed over the layer of insulation material and the contacts such that each contact has an exposed region;a plurality of dielectric lines formed on the isolation material and the contacts so that a dielectric line is formed on the exposed region of each contact in a row of contacts, the dielectric lines extending across the array in a direction perpendicular to the bit lines; anda plurality of conductive word lines formed on the plurality of dielectric lines to contact the dielectric lines so that a word line is formed on each dielectric line.