Patent ID: 9190161
Filing Date: 2015-11-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell configured to stores n levels, where n is a natural number of two or greater, a bit line connected to the memory cell; a word line connected to the memory cell; a sense amplifier connected to the bit line to detect a voltage of the bit line; and a control circuit configured to control potentials of the word line and the bit line, wherein, in a read of k−1 levels stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on a first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and a second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing, where k is a natural number, and k≦n.