Patent ID: 7085153
Filing Date: 2006-08-01
Classification: G11C,H01L

Abstract:
1. A semiconductor dynamic random access memory cell for storing a first data state and a second data state, the memory cell comprising: first and second transistors, wherein each transistor includes: wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region; wherein the memory cell is in: (1) the first data state when the first transistor is in the first state and the second transistor is in the second state, and (2) the second data state when the first transistor is in the second state and the second transistor is in the first state; and wherein the memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein: