Patent ID: 7194711
Filing Date: 2007-03-20
Classification: G06F

Abstract:
1. A method for performing thermal analysis of a semiconductor chip design, the semiconductor chip design including one or more semiconductor devices and one or more interconnects connecting the one or more semiconductor devices, the method comprising: receiving at least one semiconductor chip design parameter; calculating power dissipated by at least one of the one or more semiconductor devices and the one or more interconnects, in accordance with the at least one semiconductor chip design parameter; distributing power dissipated by at least one of said one or more interconnects, said one or more semiconductor devices, and between said one or more interconnects and said one or more semiconductor devices; and constructing a three-dimensional full-chip thermal model of said semiconductor chip design, that is adaptively partitioned in response to volumes of steep thermal gradients over the semiconductor chip design, in accordance with said distributed power, said thermal model depicting computed temperatures for all of said one or more semiconductor devices and all of said one or more interconnects wherein said method is implemented to account for interdependent heat fields between said one or more semiconductor devices and said one or more interconnects wherein said method is implemented to account for interdependent heat fields between said one or more semiconductor devices and said one or more interconnects.