Patent ID: 6995413
Filing Date: 2006-02-07
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a memory cell transistor having first and second regions selectively formed in said semiconductor substrate; a peripheral transistor having a third region selectively formed in said semiconductor substrate; first, second and third silicide layers formed at respective surface portions of said first, second and third regions; a first insulating layer covering said semiconductor substrate and said first, second and third silicide layers, said first insulating layer having first, second and third holes that expose respective parts of said first, second and third silicide layers; a first conductive layer filling said first hole in contact with said first silicide layer, said first conductive layer being made of a metal; a second conductive layer filling said second hole in contact with said second silicide layer, said second conductive layer being made of a metal; a third conductive layer filling said third hole in contact with said third silicide layer, said third conductive layer being made of a metal; a second insulating layer covering said first insulating layer and said first, second and third conductive layers, said second insulating layer having a fourth hole that exposes at least one part of said first conductive layer, a fourth conductive layer filling said fourth hole in contact with said first conductive layer, said fourth conductive layer being made of a metal; a bit line formed on said second insulating layer in contact with said fourth conductive layer; a third insulating layer covering said bit line and said second insulating layer; a fifth hole formed to penetrate said third and second insulating layers to expose at least one part of said second conductive layer; a sixth hole formed to penetrate said third and second insulating layers to expose at least one part of said third conductive layer; a fifth conductive layer filling said fifth hole in contact with said second conductive layer, said fifth conductive layer being made of a metal; a sixth conductive layer filling said sixth hole in contact with said third conductive layer, said sixth conductive layer being made of a metal; a capacitor formed on said third insulating layer in contact with said fifth conductive layer; a fourth insulating layer covering said capacitor, said third insulating layer and said sixth conductive layers, said fourth insulating layer having a seventh hole that exposes at least one part of said sixth conductive layer; a seventh conductive layer filling said seventh hole in contact with said sixth conductive layer, said seventh conductive layer being made of a metal; and a wiring layer formed on said fourth insulating layer in contact with said seventh conductive layer.