Patent ID: 6011713
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A semiconductor memory circuit device comprising:a semiconductor memory cell for receiving and holding data;potential control means for controlling a potential of a ground side terminal connected to said semiconductor memory cell;connection control means for controlling connection of said semiconductor memory cell and a power supply potential terminal; andtransfer control means for controlling transfer of data from a bit line to said semiconductor memory cell,wherein, after said potential control means raises the potential of said ground side terminal to be higher than a ground potential by a predetermined potential in writing data, said connection control means disconnects said semiconductor memory cell from said power supply potential terminal, and said transfer control means transfers data having a potential difference smaller than a potential difference between a power supply potential and the ground potential from said bit line to said semiconductor memory cell, said potential control means decreases the potential of said ground side terminal to the ground potential, and amplifies the written small potential difference so that the data written in said semiconductor memory cell is not destroyed even if the potential of said ground side terminal is decreased to the ground potential, and said connection control means connects said semiconductor memory cell and said power supply potential terminal.