Patent ID: 6548388
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising:forming an insulating layer within a plurality of trenches and over a polishing stop layer, wherein the plurality of trenches are formed in a semiconductor substrate and define respective field regions of the semiconductor substrate, wherein the polishing stop layer is formed over active regions of the semiconductor substrate which are defined between the field regions, and wherein a pad oxide layer is interposed between the polishing stop layer and the semiconductor substrate; chemical/mechanical polishing the insulating layer so as to remove the insulating layer down to a level of the polishing stop layer, removing the polishing stop layer and the pad oxide layer on the active regions such that a level of the insulating layer within the field regions protrudes above a level of the active regions of the semiconductor substrate, and thereafter forming a gate oxide layer over the active regions and the field regions; depositing a gate electrode conductive layer over the gate oxide layer; chemical mechanical polishing the gate electrode conductive layer down to a level of the field regions to define a damascene structure of the gate electrode conductive layer; stacking and patterning a silicide layer and an upper gate insulation layer on the semiconductor substrate, to form gate stacks on the active regions and the field regions; forming gate lines in which spacers are formed on sidewalls of each of the gate stacks, and growing a polysilicon layer from a bottom of the active regions using selective epitaxial growth to obtain a resultant structure; forming an etching stop over the resultant structure; forming an interlayer insulation layer over the etching stop; and planarizing the interlayer insulation layer using an etch back process.