Patent ID: 8524595
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. A semiconductor method, comprising: forming a plurality of solder balls or solder bumps over a first substrate; forming a planar layer of encapsulation material over the first substrate, partially covering the solder balls or solder bumps, the planar layer extending an entire distance between a first one of the solder balls or solder bumps and a second one of the solder balls or solder bumps; flowing the planar layer of encapsulation material along at least one side wall of at least the first and second ones of the solder balls or solder bumps, to form a first encapsulation material portion around the first solder ball or solder bump and a second encapsulation material portion around the second solder ball or solder bump, wherein the first and second solder balls or solder bumps are near to each other and a gap is formed between the first and second encapsulation material portions.