Patent ID: 6016063
Filing Date: 2000-01-18
Classification: H03K

Abstract:
A circuit implemented in a programmable logic device, comprising:an array of configurable logic blocks (CLBs);an array of lines distributed across said circuit and comprising a first line and a second line, each of said first and second lines being configured to be resistively coupled to a voltage supply;an array of tristate buffers distributed about said circuit to couple each of said CLBs to an adjacent line, said array of tristate buffers comprising a first plurality of tristate buffers and a second plurality of tristate buffers, said first plurality of tristate buffers being configured to have open-drain interconnections with said first line, said second plurality of tristate buffers being configured to have open-drain interconnections with said second line; andmeans for combining a first input signal and a second input signal to form a combined logic function, said first input signal being provided by said first line and said second input signal being provided by said second line.