Patent ID: 8673699
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: (a) obtaining an extra thin semiconductor on insulator (ETSOI) wafer having a PFET portion where a p-type field effect transistor (PFET) will be formed and an NFET portion where an n-type field effect transistor (NFET) will be formed; (b) forming at least one gate structure in the PFET portion and at least one gate structure in the NFET portion; (c) depositing a high quality nitride over the PFET portion and the NFET portion, the high quality nitride being unetchable in dilute hydrofluoric acid (HF); (d) depositing a low quality nitride over the high quality nitride, the low quality nitride being etchable in dilute HF; (e) etching the PFET portion to remove the high quality nitride and low quality nitride except for high quality nitride and low quality nitride adjacent to the at least one gate structure in the PFET portion; (f) etching the PFET portion and the NFET portion to remove the low quality nitride; (g) forming a doped faceted epitaxial silicon/germanium (SiGe) on the ETSOI adjacent to the high quality nitride and the at least one gate structure in the PFET portion to form a faceted raised source/drain (RSD) in the PFET portion and an amorphous portion on the high quality nitride; (h) depositing a low quality nitride over the PFET portion and the NFET portion; (i) etching the PFET portion to remove the low quality nitride while maintaining the low quality nitride adjacent to the high quality nitride and at least one gate structure to form disposable spacers from the low quality nitride adjacent to the high quality nitride and etching the NFET portion to remove the low quality nitride and high quality nitride except for high quality nitride and low quality nitride adjacent to the at least one gate structure in the NFET portion, the low quality nitride adjacent to the at least one gate structure in the NFET portion forming disposable spacers; (j) ion implanting into the RSD in the PFET portion to render amorphous a top portion of the RSD in the PFET portion; (k) etching the disposable spacers adjacent the at least one gate structure in the NFET portion and the PFET portion to leave at least the high quality nitride adjacent to the at least one gate structure in the PFET portion and at least the high quality nitride adjacent to the at least one gate structure in the NFET portion; (l) forming a faceted epitaxial silicon RSD on the ETSOI adjacent to the at least one gate structure in the NFET portion; (m) performing a rapid thermal anneal; (n) ion implanting extensions into the ETSOI underneath the at least one gate structure in the NFET portion; and (o) performing a short time scale anneal to activate the NFET extension implants but not diffuse them.