Patent ID: 8281297
Filing Date: 2012-10-02
Classification: G06F,Y02D

Abstract:
1. A method, comprising: deriving, by a computing device, control flow graphs for selected multiple program operations of a source code; identifying, by the computing device, blocks of the control flow graphs; developing, by the computing device, data flow graphs for two or more of the blocks; identifying, by the computing device, a common subgraph shared by at least a pair of the blocks; scheduling, by the computing device, shared processes represented by the common subgraph; scheduling, by the computing device, the shared processes for operation in each of the multiple program operations; and scheduling, by the computing device, processing units to carry out the shared processes represented by the common subgraph; wherein scheduling of common operations represented by the common subgraph includes providing switching of differing delays among processes of the common subgraph to effect subgraphs operating each of the selected multiple program operations, wherein said providing switching of different delays includes configuring multiplexers operative to apply alternative delays between processes of the common subgraph; and wherein said scheduling of processing units to carry out the common subgraph includes clustering the shared processes into a macroblock having nodes representing the shared processes and at least a plurality of unconditional, conditional, and reconfiguration edges running between nodes, and determining a relative delay among possible paths through the common subgraph for an implementation using processing units formed on an integrated circuit.