Patent ID: 6482738
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method of locally forming metal silicide layers, said method comprising the steps of:providing a silicon substrate, and said silicon substrate is divided into at least two regions: one is an array region, the other is a periphery region; forming a first dielectric layer on said silicon substrate in said array region and a plurality of first transistors on said first dielectric layer, wherein there is a first spaced region between any two neighboring gates of said plurality of first transistors; forming a plurality of second transistors on said silicon substrate in said periphery region, wherein there is a second spaced region between any two neighboring gates of said plurality of second transistors, and said second spaced region is larger than said first spaced region; conformally depositing a second dielectric layer to cover said silicon substrate, said array region, and said periphery region; depositing a third dielectric layer on said second dielectric layer, wherein the thickness of those third dielectric layer within said first spaced region is larger than that of third dielectric layer in any other region; performing a first selective etching process to remove a partial said third dielectric layer, so that a part of said second dielectric layer on said gates of said plurality of first transistors is exposed, wherein a part of the remaining said third dielectric layer is within said first spaced region; depositing a photoresist layer to cover said third dielectric layer and said second dielectric layer; removing a part of said photoresist layer within said periphery region; performing a second selective etching process to completely remove said remaining third dielectric layer within said periphery region by using said photoresist layer as a mask; removing said photoresist layer; performing a third selective etching process to remove a part of said second dielectric layer to expose a partial surface of said silicon substrate within said periphery region and to expose the top surface of each gate of said plurality of first transistors and said plurality of second transistors, so a sidewall of each gate of said plurality of first transistors and said plurality of second transistors is formed, wherein a part of said third dielectric layer in said first spaced region is used as a mask, therefore, a part of said second dielectric layer within said first spaced region remains; depositing a metal layer to cover said silicon substrate, said array region, and said periphery region; performing a heating process to form metal silicide; and removing said metal layer.