Patent ID: 6519103
Filing Date: 2003-02-11
Classification: G11B

Abstract:
A partial response, maximum likelihood (â€œPRMLâ€ ) read/write channel, comprising:an analog front circuit including electronic components configured to process analog information received from a magnetic data storage medium; a view digital-to-analog converter (â€œDACâ€ ) circuit having a first input coupled with an internal PRML digital port having high-speed digital signals, the view DAC circuit being configured to convert the digital signals to an analog signal associated with the digital signals, the analog signal provided at a view DAC output node; and a view DAC feedback circuit coupled with the view DAC output node and being configured to selectively couple the view DAC output to an input path of the electronics of the analog front circuit during a calibration procedure to optimize performance of the PRML read/write channel.