Patent ID: 6459643
Filing Date: 2002-10-01
Classification: G11C

Abstract:
A semiconductor integrated circuit comprising:a plurality of boosting circuits operating in synchronization with a memory activation signal; an auxiliary boosting circuit operating asynchronously to a memory activation signal with smaller capability of supplying electric charge than that of said boosting circuit; a timing control circuit for producing a control signal of a plurality of said boosting circuits in response to a memory activation signal; an oscillator performing self-induced oscillation for said auxiliary boosting circuit; and a detection circuit for detecting a potential of boosted power source and controlling operations of said timing control circuit and said oscillator, wherein said timing control circuit distributes operations of said plurality of boosting circuits, said boosting circuit including a charge pump circuit and a control signal producing circuit for producing a control signal for said charge pump circuit, said charge pump circuit includes an electric charge transfer gate, first boosting means for doubling source voltage relative to said source voltage, and second boosting means for tripling said source voltage relative to said source voltage and said first boosted potential, and said electric charge transfer gate has a source electrode connected to an output terminal and a drain electrode connected to said first boosted potential, and said second boosted potential is connected to a gate electrode of said electric charge transfer gate, thereby to supply said first boosted potential to said output terminal.