Patent ID: 9171843
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit device, the method comprising: providing a precursor, the precursor including: laterally exposing the semiconductor layer stack in the first gate region; epitaxially growing a third semiconductor material to form source/drain features adjacent the semiconductor layer stack in the first MOS region, wherein the third semiconductor material is different from the first and second semiconductor materials; after epitaxially growing the third semiconductor material to form source/drain features adjacent the semiconductor layer stack in the first region, oxidizing the first, second, and third layers of the semiconductor layer stack in the first gate region to form a first outer oxide layer and a first inner nanowire set, a first nanowire in the first inner nanowire set extending from the first source region to the corresponding first drain region; removing the first outer oxide layer to expose the first inner nanowire set in the first gate region; forming a first high-k/metal gate (HK/MG) stack wrapping around the first inner nanowire set; laterally exposing the semiconductor layer stack in the second gate region; oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, a second nanowire in the second inner nanowire set extending from the second source region to the corresponding second drain region; removing the second outer oxide layer to expose the second inner nanowire set in the second gate region; and forming a second HK/MG stack wrapping around the second inner nanowire set.