Patent ID: 6625073
Filing Date: 2003-09-23
Classification: G11C

Abstract:
A method of testing a packaged semiconductor device having a semiconductor memory circuit, a voltage boosting circuit and a plurality of pads formed on a die, the semiconductor memory circuit having an array of memory cells addressable by electrically conductive row and column lines, the voltage boosting circuit providing a boosted voltage signal to the semiconductor memory circuit, a first set of pads being coupled to and providing power signals to the semiconductor memory circuit, a second set of pads being coupled to and providing address signals to access memory cells in the semiconductor memory circuit through the row and column lines, and a third set of pads being coupled to and providing input signals to and output signals from the semiconductor memory circuit, the packaged semiconductor device also having a plurality of electrically conductive leads each having a pin end and a free end, the free ends of first, second and third sets of leads being electrically connected to at least some of the pads in the first, second and third sets of pads, respectively, the method comprising the steps of:providing the packaged semiconductor memory device, the packaged semiconductor device having at least one superfluous lead having a free end coupled to one of the pads in the first set of pads; applying a predetermined voltage to at least one of the plurality of leads; applying a predetermined combination of signals to the leads in the first or second sets of leads; providing external supplementary power to the superfluous lead as the boosted voltage signal; simultaneously applying the boosted voltage signal for a predetermined period of time to a selected number of row lines; analyzing values stored in non-selected memory cells of the array of memory cells; and determining that the packaged semiconductor device is defective if a non-selected memory cell has a voltage value written thereto.