Patent ID: 6094701
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:first and second memory cell arrays each of which has a plurality of banks and in which memory cells are arranged in a matrix pattern;a column address generation circuit, supplied with a read start address, for generating a column address having a plurality of bits, which sequentially counts up from the read start address;a bank selection circuit for selecting the banks on the basis of at least one bit more significant than a predetermined intervening bit of the column address generated by the column address generation circuit;a determination circuit for determining which memory cell array includes a bank of a designated memory cell;an address adder circuit, operating when the determination circuit determines that the second memory cell array includes the bank of the designated memory cell, for adding ""1"" to at least one bit not more significant than the predetermined intervening bit of the column address which is generated by the column address generation circuit and which are supplied to the first memory cell array;a first column selection circuit for selecting memory cell columns of the banks of the first memory cell array on the basis of at least one bit not more significant than the predetermined intervening bit of the column address generated by the column address generation circuit when the determination circuit determines that the first memory cell array includes the bank of the memory cell designated by the read start address, and for selecting memory cell columns of the banks of the first memory cell array on the basis of a ""1""-incremented column address output from the address adder circuit when the determination circuit determines that the second memory cell array includes the bank of the memory cell designated by the read start address;a second column selection circuit for selecting memory cell columns of the banks of the second memory cell array on the basis of said at least one bit not significant than the predetermined intervening bit of the column address generated by the column address generation circuit;a sense amplifier circuit for amplifying data read out from the memory cells in units of one bank;a latch circuit for latching the data which are read out from the memory cells and which are amplified by the sense amplifier circuit in unit s of one bank; andan output circuit for sequentially outputting the data latched in the latch circuit, beginning with data corresponding to a bank selected by the bank selection circuit.