Patent ID: 8276105
Filing Date: 2012-09-25
Classification: G06F

Abstract:
1. An automated method for positioning gate array circuits in an integrated circuit design, the method comprising: providing an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells; receiving a gate array logic element design to be placed in the integrated circuit design; automatically determining an initial placement position for the gate array logic element at any position between adjacent logic cells in alignment with the single step size grid based on at least one circuit design consideration; after automatically determining the initial placement position for the gate array logic element: when the initial placement position is not aligned with the least common multiple step size grid, automatically positioning the gate array logic element in a final position aligned with the least common multiple step size grid, wherein the final position is different from the initial position by a multiple of single step size grid cells; and automatically positioning gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element.