Patent ID: 6426660
Filing Date: 2002-07-30
Classification: H03K

Abstract:
A duty-cycle correction circuit providing an accurate 50% duty cycle clock signal from an input clock signal having a frequency fc and a non-50% duty cycle, said circuit comprising:a divide-by-two frequency divider receiving the input clock signal and outputting a signal having a frequency fc/2 with a 50% duty cycle; a current controlled delay block receiving the output signal from the divide-by-two frequency divider and outputting a signal having a frequency fc/2 with a 50% duty cycle delayed by a time proportional to a current control signal; an exclusive OR gate receiving the output signals of the divide-by-two frequency divider and the current controlled delay block and outputting a signal having a frequency fc and a 50% duty cycle; a first low pass filter receiving the output signal of the exclusive OR gate and producing a first d.c. voltage signal; a second low pass filter receiving the output signal from the divide-by-two frequency divider and outputting a second d.c. voltage signal; an operational amplifier receiving the first and second d.c. voltages and outputting a voltage signal proportional to a difference between the first and second d.c. voltages; and a voltage controlled current source responsive to the output voltage signal of the operational amplifier for generating the current control signal to the current controlled delay block.