Patent ID: 7275200
Filing Date: 2007-09-25
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a memory array including a plurality of memory cells arranged in rows and columns, a plurality of word lines coupled to corresponding rows of memory cells, a plurality of bit lines coupled to corresponding columns of memory cells, a plurality of sense amplifiers coupled to the bit lines, and a plurality of column switches coupled to the sense amplifiers, wherein the memory cells are configured to store a plurality of error correction code (ECC) words, each including a data value and associated error correction bits; a data bus, wherein the column switches are coupled between the data bus and the sense amplifiers; a memory interface coupled to the data bus, wherein the memory interface is configured to support a partial word write operation to the memory array by implementing a read operation from the memory array followed by a write operation to the memory array; and a memory sequencer configured to continuously activate the word line and sense amplifiers during the read and write operations of the partial word write operation.