Patent ID: 7281198
Filing Date: 2007-10-09
Classification: H03M,H04L

Abstract:
1. A data processor for decoding data based on information bits and check bits to be referred for performing error correction processing on the information bits, the data processor comprising: a memory apparatus for temprarily storing information bits and check bits, wherein said memory apparatus temporarily stores first check bits and second check bits, which are reliability information of the information bits; a first processor for performing for performing processing predetermined for check bits supplied from the memory apparatus, wherein said first processor is a first rate dematch apparatus for performing first rate dematch processing defined by High-Speed Downlink Packet Access (HSDPA) on the first check bits and the second check bits; a decoder for performing decoding processing based on information bits and check bits; and a switch for switching an output of the memory apparatus to one of the first processor and the decoder, wherein, in synchronism with the supply of an output of the first processor to the decoder, information bits are supplied from the memory apparatus to the decoder without the first processor in the middle.