Patent ID: 9159268
Filing Date: 2015-10-13
Classification: G09G

Abstract:
1. An organic light emitting diode display comprising: a panel including a plurality of pixels formed by crossings of a plurality of gate lines and a plurality of data lines, each pixel including an organic light emitting diode and a plurality of transistors; a timing controller configured to generate a gate shift clock; and a gate driver configured to receive the gate shift clock and output a plurality of gate signals to the plurality of transistors of each of the pixels based on the gate shift clock, the plurality of transistors turned on or turned off based on the plurality of gate signals, the gate driver outputting at least one of the gate signals to a corresponding one of the plurality of transistors shifted by a time interval of one half of a period of the gate shift clock, wherein the gate driver includes a plurality of stages, each stage is coupled to a corresponding pixel and transmits a plurality of gate signals to corresponding transistors of the corresponding pixel, each stage of the gate driver including an inverter unit that inverts the gate shift clock and outputs the gate shift clock and the inverted gate shift clock and each stage further includes a plurality of selectors, each selector coupled to the inverter unit and one of the plurality of transistors of a pixel, at least one selector outputting a gate signal to a gate of one of the transistors coupled to the selector based on the gate shift clock and at least another selector outputting a gate signal to a gate of another one of the plurality transistors of the pixel based on the inverted gate shift clock, each of the plurality of selectors receiving an inverted signal output from the inverter, the gate shift clock, a selection signal SEL, and an input signal, and if the selection signal SEL corresponds to high level H, each of the plurality of selectors synchronizes the input signal at the time of rising of the gate shift clock and outputs the synchronized input signal as the gate signal, and if the selection signal SEL corresponds to low level L, each of the plurality of selectors synchronizes the input signal at the time of falling of the gate shift clock and outputs the synchronized input signal as another gate signal.