Patent ID: 7161950
Filing Date: 2007-01-09
Classification: H04L

Abstract:
1. A switching apparatus comprising: an input port, an output port, and a bus that connects said input and output ports; a first memory, coupled to said bus, and configured to store an input data frame, wherein the first memory includes channels and segments, where each segment defines a logical time portion of a channel and each location in the first memory is designated by a channel and a segment; a first logic circuit coupled to receive an input data frame, coupled to the first memory and configured to determine if multiple items of data on said bus will be produced on the same segment, and if so, stopping said multiple items from being output, to prevent collisions, and to allow one or more locations in the first memory that can store the input data frame; and a second logic circuit coupled to the first memory and configured to determine when to read the input data frame from the first memory.