Patent ID: 8970644
Filing Date: 2015-03-03
Classification: G09G

Abstract:
1. An AMOLED driving and compensating circuit comprising: several driving circuits set inside several pixel regions used for driving several AMOLEDs, wherein one AMOLED and one corresponding driving circuit are set inside each of the pixel regions, and one driving circuit is used for driving one corresponding AMOLED; an external compensating circuit set outside the pixel regions used for eliminating an effect of threshold voltage of driving thin film transistors in the several driving circuits set inside the several pixel regions on driving currents passing through the driving thin film transistors, wherein, the external compensating circuit set outside the pixel regions comprises: a second thin film transistor, a third thin film transistor, a compensating capacitor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor and a seventh thin film transistor; the second thin film transistor has a source connected to ground, a gate connected to a second clock signal output terminal, and a drain connected to a second terminal of the driving capacitor; the third thin film transistor has a source connected to the drain of the second thin film transistor, and a gate connected to the second clock signal output terminal; the compensating capacitor has a first terminal connected to a drain of the third thin film transistor; the fourth thin film transistor has a source connected to a second terminal of the compensating capacitor, a gate connected to the second clock signal output terminal, and a drain connected to a source of the driving thin film transistor; the fifth thin film transistor has a source connected to ground, a gate connected to a first clock signal output terminal, and a drain connected to the source of the fourth thin film transistor; the sixth thin film transistor has a source connected to a reference voltage output terminal, a gate connected to the first clock signal output terminal, and a drain connected to the drain of the second thin film transistor; the seventh thin film transistor has a source connected to the reference voltage output terminal, a gate connected to the first clock signal output terminal, and a drain connected to the gate of the driving thin film transistor; and a gate of the first thin film transistor is connected to the second clock signal output terminal, wherein the second thin film transistor, the sixth thin film transistor and the seventh thin film transistor are n-channel thin film transistors; the third thin film transistor, the fourth thin film transistor and the fifth thin film transistor are p-channel thin film transistors.