Patent ID: 9121903
Filing Date: 2015-09-01
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a semiconductor substrate; B. functional circuits formed on the substrate; C. bond pads formed on the substrate and coupled to the functional circuits; D. parallel scan paths circuits formed on the substrate and coupled to the functional circuits, each of the parallel scan path circuits having a serial input, a serial output, a scan path shift input, and a scan path capture input; E. a scan distributor circuit having a serial input coupled to a first bond pad, a distributor shift input, and parallel outputs, each parallel output being coupled to a serial input of a parallel scan path circuit; F. a scan collector circuit having a serial output coupled to a second bond pad separate from the first bond pad, a collector shift input, a collector capture input, and parallel inputs, each parallel input being coupled to a serial output of a parallel scan path circuit; and G. controller circuitry having a serial input and control inputs coupled to bond pads separate from the first and second bond pads, the controller circuitry having a scan path shift output coupled to the scan path shift input of each parallel scan path circuit, the controller circuitry having a scan path capture output coupled to the scan path capture input of each parallel scan path circuit, the controller circuitry having a distributor and collector shift output coupled to the distributor shift input of the scan distributor circuit and to the collector shift input of the scan collector circuit, and the controller circuitry having a collector capture output coupled to the collector capture input of the scan collector circuit.