Patent ID: 6591389
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A circuit pack having self-testing capability, said circuit pack comprising:a processor for executing program instructions; a memory for storing data; a program resident in said circuit pack for running a test suite for self-testing components on said circuit pack, said test suite comprising a plurality of test portions wherein; said program examines a first designated memory location prior to beginning the test suite to determine whether a previously executed test suite ran to completion; said program creates a record in a second designated memory location located in said memory if said examination reveals that the previously executed test suite did not run to completion, said record indicating the failure which occurred during the previously executed test suite; said program initializes said first designated memory location in said memory prior to running the first one of said test portions; and each test portion of the test suite stores testing results in said first designated location.