Patent ID: 7893724
Filing Date: 2011-02-22
Classification: H03K

Abstract:
1. A circuit for aligning two or more signals including a first and a shifted copy of a second signal, the circuit comprising: a first gate coupled to a first delay block, the first gate configured for receiving the first signal and a power down signal; a second gate coupled to a second delay block, the second gate configured for receiving a shifted copy of the second signal and the power down signal; a first flip-flop configured for receiving the first signal and an output from the second delay block; a second flip-flop configured for receiving the shifted copy of the second signal and an output from the first delay block; a third gate configured for receiving an output from the first flip-flop and an output from the second flip-flop; and a fourth gate configured for receiving an output from the third gate and the power down signal and providing a circuit output signal.