Patent ID: 8711679
Filing Date: 2014-04-29
Classification: H04L

Abstract:
1. A method to identify a failure in a logical circuit, the method comprising: receiving non-requested trap data from a plurality of switches forming a logical circuit, the logical circuit spanning first, second, and third logical networks; polling first and second switches of the logical circuit exclusive of others of the plurality of switches of the logical circuit, the first switch forming a first network-to-network interface between the first logical network and the second logical network, the second switch forming a second network-to-network interface between the second logical network and the third logical network, the first logical network being in a first local access and transport area, the second logical network being an inter-exchange carrier network, the third logical network being in a second local access and transport area, and the first and second switches selected for polling based on the trap data indicating a problem at the first and second switches; and identifying a failure of the logical circuit without manual intervention based on the polling.