Patent ID: 7781823
Filing Date: 2010-08-24
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a semiconductor substrate including a memory cell array region having a plurality of device regions located on an upper surface of the semiconductor substrate, each of the device regions extending along a first direction, respectively; a plurality of memory cell units located on the device region, each of the memory cell units including a first select gate transistor, a second select gate transistor and a plurality of memory cell transistors located between the first and second select gate transistors along the first direction, the memory cell units arranged along the first direction and a second direction which is perpendicular to the first direction in the memory cell array region; a first source line located at one end of each memory cell unit, the first source line extending along the second direction and electrically connected to the first select gate transistor of each memory cell unit; a plurality of bit lines located above the memory cell unit and the first source line, each bit line extending along the first direction and corresponding to one of the device regions, respectively, each bit line electrically connected to the second select gate transistor of each memory cell unit; and a second source line located above the bit lines, the second source line including a plurality of first line portions extending along the first direction and a plurality of second line portions extending along the second direction so as to connect the first line portions, respectively.