Patent ID: 7549138
Filing Date: 2009-06-16
Classification: G06F,G11C,H03K

Abstract:
1. In a FPGA having a plurality of individually programmable tiles of logic modules, each logic module including a plurality of antifuses, a method for programming selected antifuses in each of the tiles comprising: loading for each tile address data identifying ones of the plurality of antifuses designated for programming; selecting for each tile the address of one of the antifuses designated for programming; programming concurrently in each tile the antifuse identified by the selected address; determining whether all of the selected antifuses designated for programming have been programmed; continuing to program any ones of the antifuses designated for programming that have not been programmed; soaking the programmed antifuses in each tile; determining whether the antifuse designated for programming in each tile has been programmed; determining whether all antifuses designated for programming have been programmed; and repeating the selecting, programming, determining and the soaking if all antifuses designated for programming have not been programmed.