Patent ID: 7812408
Filing Date: 2010-10-12
Classification: H01L

Abstract:
1. An integrated circuit comprising: a first plurality of n-channel transistors each having a gate that includes a first gate oxide with a first gate oxide layer thickness and that includes a first gate conductor with a first gate conductor doping concentration; a second plurality of n-channel transistors each having a gate that includes a second gate oxide with a second gate oxide layer thickness and that includes a second gate conductor with a second gate conductor doping concentration, wherein the second gate conductor doping concentration is less than the first gate conductor doping concentration and wherein the first gate oxide layer thickness and the second gate oxide layer thickness are equal; a third plurality of n-channel transistors; and a fourth plurality of n-channel transistors, wherein the first plurality of n-channel transistors handle voltages up to a first maximum voltage, wherein the second plurality of n-channel transistors handle voltages up to a second maximum voltage that is greater than the first maximum voltage, wherein the third plurality of n-channel transistors handle voltages up to a third maximum voltage that is less than the first maximum voltage, wherein the fourth plurality of n-channel transistors handle voltages up to a fourth maximum voltage that is less than the third maximum voltage, wherein the third plurality of n-channel transistors each have a gate with a gate oxide of a third gate oxide layer thickness, wherein the fourth plurality of n-channel transistors each have a gate with a gate oxide of a fourth gate oxide layer thickness, wherein the fourth gate oxide layer thickness is less than the third gate oxide layer thickness, and wherein the third gate oxide layer thickness is less than the first gate oxide layer thickness.