Patent ID: 8237478
Filing Date: 2012-08-07
Classification: H03L

Abstract:
1. A delay locked loop (DLL) circuit, comprising: a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal such that the delay control signal sets a delay value of the delay line to any one of a minimum value and an intermediate value, wherein the delay value is set according to an initial value of the phase detection signal, wherein the delay control unit is configured to set a logic value of the delay control signal to a minimum total delay amount of the delay line in an initial operation.