Patent ID: 7924053
Filing Date: 2011-04-12
Classification: H03K

Abstract:
1. A logic cluster for a field programmable gate array integrated circuit device, comprising: (a) a plurality of functional blocks each having a plurality of inputs and at least one output; (b) a first level of multiplexers, each multiplexer having: (c) a second level of multiplexers, each multiplexer having: (d) a third level of multiplexers, each multiplexer having: (e) a plurality of external interconnects, each interconnect being coupled to at least one third level multiplexer data channel; (f) a first plurality of internal interconnects, each interconnect being coupled between one second level multiplexer output and at least one first level multiplexer data channel; (g) a second plurality of internal interconnects, each interconnect being coupled between one third level multiplexer output and at least one second level multiplexer data channel; (h) a first plurality of feedback interconnects, each interconnect being coupled between one functional block output and at least one second level multiplexer data channel; and (i) a second plurality of feedback interconnects, each interconnect being coupled between one functional block output and at least one third level multiplexer data channel associated with a fastest one of the first level of multiplexers.