Patent ID: 7287145
Filing Date: 2007-10-23
Classification: G06F

Abstract:
1. A memory controller for redirecting a linear address associated with a range of addresses to access a reclaimed memory hole comprising: an address translator configured to determine an amount of restricted addresses that are unusable by a processor as system memory and to establish a baseline address identified as a first number being a first integer power of 2 for defining a region of memory, said range of addresses being located at another address identified as a second number being a second integer power of 2, wherein said address translator translates said linear address into a translated address associated with said reclaimed memory hole based on said baseline address; wherein said region of memory is disposed within a main memory composed of a number of symmetrically-arranged memory devices, each of said memory devices having a memory device size that is the same as the others; said amount of restricted addresses referring to a quantity of addresses reserved for memory-mapped devices other than said processor and said region is bounded by a top of physical memory (“TOPM”) address identified as a third number being a third integer power of 2; said address translator forming said translated address by concatenating subsets of bits; and wherein said address translator forms said translated address by concatenating: a first subset of bits, a second subset of bits and a third subset of bits, said first subset of bits being from said baseline address, said second subset of bits being from an inverted linear address and said third subset of bits being from said linear address.