Patent ID: 6449201
Filing Date: 2002-09-10
Classification: G11C

Abstract:
A semiconductor memory device comprising:a differential sense amplifier having a first input node and a second input node for sensing a difference between a voltage on the first input node and a voltage on the second input node: an information read section for supplying a voltage varying in accordance with information which is read from a memory cell, the voltage being supplied to the first input node; a reference section for supplying a reference voltage to the second input node: and a control section for controlling the differential sense amplifier, the information read section, and the reference section, wherein the information read section includes: a main bit line coupled to the first input node; a select gate: a sub-bit line which is coupled to the main bit line via the select gate; a memory cell which is coupled to the sub-bit line and which is selectively activated in accordance with a voltage on a word line; a precharge section for precharging the first input node and the main bit line to a first voltage; and a reset section for resetting the sub-bit line to a second voltage which is lower than the first voltage, wherein the control section controls the precharge section, the reset section, and the select gate so that a portion of a charge which is precharged in the first input node and the main bit line is redistributed to the sub-bit line after precharging the first input node and the main bit line to the first voltage and resetting the sub-bit line to the second voltage.