Patent ID: 7741676
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A semiconductor apparatus comprising: a cell section including at least two transistors, said cell section including: a gate contact section including; a layer interval insulation coat formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon; a source electrode metal coat formed overlying the semiconductor substrate, said source electrode metal coat being insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and being electrically connected to the body diffusion layer and the source diffusion layer; a gate use connection hole formed on the layer interval insulation coat overlying the gate contact use polysilicon, said gate use connection hole having a width larger than that of the trench; and a gate electrode metal coat formed on the rate use connection hole and the layer interval insulation coat; wherein the gate contact use polysilicon is formed one of at the same level with and lower than the surface of the semiconductor substrate, and wherein the upper surfaces of the gate electrode use polysilicon and the gate contact use polysilicon are lower than the surface of the semiconductor substrate, further comprising a silicon oxide coat formed between the gate contact use polysilicon and the layer interval insulation coat and being separated with an interval from a sidewall of the gate contact use concave section, the upper surface of said silicon oxide coat being the same level with the surface of the semiconductor substrate.