Patent ID: 6487109
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A magnetoresistive memory, comprising:magnetoresistive memory cells having respective first poles and second poles and being disposed in an array formed by rows and columns; bit lines assigned to said columns, said bit lines being connected to said first poles of said magnetoresistive memory cells disposed in associated ones of the columns, said bit lines having first ends and second ends; word lines assigned to said rows, said word lines being connected to said second poles of said magnetoresistive memory cells disposed in associated ones of the rows, said word lines having first ends and second ends; a read voltage source; first switching elements connected such that said read voltage source is separately connectable to said first ends of said word lines via said first switching elements; an evaluation line; second switching elements; a voltage evaluator having at least one input, said at least one input being separately connectable, via said evaluation line, to said first ends of said bit lines by said second switching elements; a first terminating resistor branching from said evaluation line; third switching elements; and an impedance converter having an input connected to said evaluation line and having an output separately connectable to said second ends of said bit lines and said word lines with said third switching elements.