Patent ID: 6400182
Filing Date: 2002-06-04
Classification: H01L,H03K

Abstract:
A semiconductor integrated circuit device comprising:a semiconductor integrated circuit having a core region including a plurality of clock driver regions, a plurality of circuit cell regions disposed between respective pairs of the clock driver regions, and a plurality of cells non-uniformly distributed in the circuit cell regions, each cell including at least one circuit receiving a clock signal; a plurality of clock signal supply lines located in the core region and connected in a mesh for distributing the clock signal to the cells; and a plurality of clock driver circuits located within respective clock driver regions and including rows of MOS transistors forming the clock driver circuits for supplying the clock signal to the cells proximate a respective clock driver circuit, wherein respective clock driver circuits comprise different numbers of the MOS transistors connected to form the respective clock driver circuits in accordance with the number of the cells supplied with the clock signal by the respective clock driver circuit, whereby clock skew is reduced.