Patent ID: 8643076
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: a substrate including a cell region and a peripheral circuit region; a first insulation layer formed over the substrate to cover the peripheral circuit region thereof; interlayer dielectric patterns and first conductive patterns alternately formed over the substrate of the cell region, wherein each of the interlayer dielectric patterns and the first conductive patterns includes a horizontal part extending along a surface of the substrate and a vertical part extending along a sidewall of the first insulation layer; a first contact connected to the substrate of the peripheral circuit region and penetrating through the first insulation layer; a second insulation layer formed over the first insulation layer, the interlayer dielectric patterns, and the first conductive patterns; a second contact connected to the vertical parts of the first conductive patterns and penetrating through the second insulation layer; a third contact connected to the first contact and penetrating through the second insulation layer; and an interconnection line arranged over the second insulation layer to connect the second contact to the third contact.