Patent ID: 8643987
Filing Date: 2014-02-04
Classification: H02H

Abstract:
1. An electrostatic discharge (ESD) protection device for an integrated circuit (IC), comprising: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply to pass to the trigger circuit, such that the trigger circuit generates a trigger pulse to select the negative bias voltage supply and to turn off the ESD clamp during normal operation.