Patent ID: 7391093
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. A semiconductor device having a semiconductor device chip with upper and lower terminal electrodes, and upper and lower frames bonded to the upper and lower terminal electrodes, respectively, with solder material, wherein said semiconductor device chip comprises: a semiconductor layer of a first conductivity type; a diffusion layer of a second conductivity type, which is selectively formed in said semiconductor layer; a plurality of guard-ring layers of the second conductivity type, which are formed outside of said diffusion layer in said semiconductor layer; an insulating film formed on said semiconductor layer over said guard ring layers; and a field plate being formed of a poly-crystalline silicon film embedded in said insulating film, said field plate formed over said guard-ring layers except an innermost one of the guard-ring layers; said upper terminal electrode being formed to extend from said diffusion layer over a part of said insulating film and over the innermost one of the guard-ring layers; and an upper surface of said upper terminal electrode is externally exposed, with no passivation film thereon.