Patent ID: 7569444
Filing Date: 2009-08-04
Classification: H01L

Abstract:
1. A method for manufacturing a transistor, the method comprising: sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching a predetermined portion of the second insulating layer; implanting impurity ions into the semiconductor substrate; depositing a layer of spacer material, and forming first spacers on sidewalls of the second insulating layer by etching the layer of spacer material; removing a first portion of the first insulating layer exposed between the first spacers and under a portion of the first spacers by a wet etching process; depositing a gate insulating layer in a region where the first portion of the first insulating layer is removed; forming a gate conductive plug on the gate insulating layer; etching the second insulating layer; forming second spacers on sidewalls of the gate conductive plug having the first spacers formed thereon; and forming a silicide layer on an upper surface of the gate conductive plug, wherein a thickness ratio between the first insulating layer and the silicide layer is in a range of 1:4 to 1:6.