Patent ID: 9214951
Filing Date: 2015-12-15
Classification: H03M

Abstract:
1. A circuit comprising: an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal, where N is an integer greater than two; N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively; an output dispatch unit for receiving the N refined data and outputting an output data in accordance with the selection signal; a calibration controller for receiving the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code; and a DAC (digital-to-analog converter) for receiving the digital code and outputting the calibration signal, wherein the selection signal has N possible values, and one of the N dispatched signals as specified by the selection signal is from the calibration signal while the other N−1 dispatched signals are from the input signal.