Patent ID: 7463742
Filing Date: 2008-12-09
Classification: H03F

Abstract:
1. A signal output circuit for controlling output of an input signal, comprising: an internal circuit; a digital delay circuit configured to delay, by digital processing, a control signal for controlling an operation of the internal circuit; a switch configured to mute the input signal in accordance with an output of the digital delay circuit, wherein the control signal is a shutdown signal shutting down the internal circuit; an amplifier circuit configured to amplify the input signal by comparing the input signal with a reference voltage; a reference voltage generator circuit configured to generate the reference voltage, the reference voltage gradually increasing in response to cancellation of the shutting down of the internal circuit; and a circuit configured to bypass a resistor of the reference voltage generator circuit in response to the cancellation of the shutting down of the internal circuit until the output of the digital delay circuit cancels the muting of the input signal, so as to accelerate the gradual increase of the reference voltage.