Patent ID: 6808980
Filing Date: 2004-10-26
Classification: H01L

Abstract:
A method for the creation of a 1T RAM cell, comprising:providing a substrate, the substrate having been provided with at least one trench filled with isolation material having a first surface area surrounded by a trench etch blocking mask comprising a layer of pad oxide over the substrate and a layer of etch stop material over the pad oxide to a height of the first surface area; removing the isolation material from the at least one trench to a depth over a second surface area being smaller than the first surface area and being adjacent to a perimeter of the at least one opening created through the trench etch blocking mask, creating at least one third surface area of the layer of isolation material exposed by the removal of the layer of isolation material and being larger than the second surface area; forming at least one capacitor over the at least one third surface area by: (i) forming at least one layer of lower capacitor plate material over the at least one third surface area, said forming at least one layer of lower capacitor plate material comprising: (1) depositing a layer of lower capacitor plate material over the trench etch blocking mask, including the layer of isolation material and the at least one third surface area; (2) creating a protective layer over the layer of lower capacitor plate material aligned with the third surface area; (3) removing the layer of lower capacitor plate material from the trench etch blocking mask and the at least one layer of isolation material; and (4) removing the trench etch blocking mask and the protective layer, exposing the at least layer of lower capacitor plate material; (ii) forming at least one layer of capacitor dielectric material over the at least one layer of lower capacitor material; and (iii) forming at least one layer of upper capacitor plate material over the at least one layer of capacitor dielectric material.