Patent ID: 6794893
Filing Date: 2004-09-21
Classification: H03K

Abstract:
A pad circuit for use in an integrated circuit chip including a core logic circuit, comprising:a gain-adjustable output buffer coupled between said core logic circuit and an input/output pin for amplifying an energy of an output signal from said core logic circuit and then outputting said output signal to an external device via said input/output pin; an input buffer coupled between said input/output pin and said core logic circuit for receiving an input signal from said external device via said input/output pin and then outputting said input signal to said core logic circuit; and a signal feature detector coupled to an output end of said input buffer and said gain-adjustable output buffer, receiving a feedback test signal from said external device via said input buffer after a test signal being manipulated by said gain-adjustable output buffer and outputted to said external device via said input/output pin, and realizing a test result in response to a waveform feature of said feedback test signal, said gain-adjustable output buffer adjusting gain according to said test result.