Patent ID: 8275089
Filing Date: 2012-09-25
Classification: G09G,G11C,H03K

Abstract:
1. A shift register, comprising: a first thin film transistor, whose gate is connected to a first node as a pull-up node, a source thereof is connected to a clock signal terminal, a drain thereof is connected to a output terminal of the present stage; a second thin film transistor, whose gate is connected to a feedback signal terminal of the next stage, a source thereof is connected to said first node, a drain thereof is connected to a low level signal terminal; a third thin film transistor, whose gate is connected to a feedback signal terminal of the next stage, a source thereof is connected to a second node as a pull-down node, a drain thereof is connected to the low level signal terminal, wherein the second node is connected with the output terminal of the present stage; a capacitor, connected between said first node and the output terminal of the present stage; a feedback module, connected between the trigger signal terminal of the previous stage, the clock signal terminal and said first node, and connected to the feedback signal terminal of the present stage and the trigger signal terminal of the present stage; and a switch module, connected with the clock signal terminal, said feedback module and the output terminal of the present stage, and connected to the low level signal terminal; wherein said feedback module is used to receive a trigger signal of the feedback module of the previous stage and the clock signal, in order to pull up the level of the first node, and to output feedback signal to the shift register of the previous stage and output the trigger signal to the feedback module of the next stage, said switch module is used to maintain the output terminal of the shift register of the present stage at a low level when the shift register of the present stage does not operate.