Patent ID: 8981786
Filing Date: 2015-03-17
Classification: G01R,G11C

Abstract:
1. A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising: a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to a sampling clock corresponding to the clock signal output by the device under test or a timing of a timing signal corresponding to a test period of the test apparatus; a judging section that judges pass/fail of the device under test, based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value; and a designating section that designates whether the data acquiring section acquires the data signal at the timing corresponding to the sampling clock or at the timing corresponding to the timing signal, wherein the data acquiring section includes: a first acquiring section that acquires the data signal output by the device under test, at the timing corresponding to the sampling clock; a second acquiring section that acquires the data signal output by the device under test, at the timing corresponding to the timing signal; and a buffer section that includes a plurality of entries, buffers the data signal acquired at the timing corresponding to whichever of the sampling clock or the timing signal is designated by the designating section sequentially in the entries, and outputs the data signal buffered in the entries at the timing of the timing signal.