Patent ID: 8890333
Filing Date: 2014-11-18
Classification: H01L

Abstract:
1. A stacked structure of semiconductor chips comprising: semiconductor chips stacked in one direction; and an interconnection member electrically connecting the semiconductor chips to each other in the one direction, wherein each of the semiconductor chips comprises: a first surface and a second surface opposite to each other and a sidewall connecting the first and second surfaces; a bonding pad disposed on the first surface; a passivation layer disposed on the first surface, the passivation layer including a first opening to expose the bonding pad; a sidewall-insulating layer disposed on the sidewall; and a first adhesion layer disposed on the passivation layer and the sidewall-insulating layer and having a second opening, wherein the second opening exposes the bonding pad and extends from the bonding pad to the sidewall-insulating layer to expose a portion of the passivation layer and a portion of the sidewall-insulating layer; and wherein the interconnection member is disposed on the exposed bonding pad, the exposed portion of the passivation layer, and the exposed portion of the sidewall-insulating layer and extends on the sidewall-insulating layer in the one direction to connect to an interconnection member of another semiconductor chip.