Patent ID: 6124183
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a plurality of trenches formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises:forming a pad oxide layer on a main surface of the substrate or epitaxial layer;forming a polish stop layer having an upper surface on the pad oxide layer;forming a large trench and a small trench, the large trench having a width at the main surface greater than a width at the main surface of the small trench;depositing an insulating material to fill the plurality of trenches and cover the polish stop layer, whereby the insulating material has a seam above the small trench and has a step in its upper surface above the large trench;performing a first polish to substantially planarize a portion of the insulating material above the small trench;heating to increase the density of the insulating material after performing the first polishing step, thereby strengthening the seam;providing a planarization mask on the insulating material above the large trench;etching to remove a portion of the insulating material above the polish stop layer and the small trench;removing the planarization mask; andperforming a second polish to planarize such that the upper surface of the insulating material is substantially flush with the upper surface of the polish stop layer.