Patent ID: 6108773
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A microprocessor for executing conditional branch instructions, comprising:translation logic, configured to receive a conditional branch macro instruction having an associated displacement and to translate said conditional branch macro instruction into a conditional branch micro instruction, said translation logic comprising:a translator, configured to detect said conditional branch macro instruction;a target address calculator, coupled to said translator, configured to receive said associated displacement and to arithmetically compute a target address for said conditional branch macro instruction, said target address being used to fetch subsequent macro instructions, if it is predicted that a corresponding branch will be taken; andpotential overflow/underflow detection logic, coupled to said target address calculator, configured to provide a signal to a subsequent pipeline stage within the pipeline microprocessor indicating whether said target address is within a current code segment;wherein said subsequent pipeline stage within the microprocessor compares said signal with a sign of said associated displacement to determine whether said target address was accurately computed, and if said target address was not accurately computed, said subsequent pipeline stage provides an accurate target address to the microprocessor, said accurate target address being used to fetch correct subsequent macro instructions; andwherein by calculating said target address within said translation logic, the microprocessor begins fetching macro instructions from said target address prior to said subsequent pipeline stage determining whether said target address was accurately computed.