Patent ID: 6219821
Filing Date: 2001-04-17
Classification: G06F,Y10S

Abstract:
In a digital processing system having a memory that stores a map entry, a first hierarchy of elements, and a second hierarchy of elements, the first hierarchy being a first representation of a circuit design, the second hierarchy being a second representation of the circuit design, the elements representing module instances and signals, a method for verifying whether the first representation matches the second representation, the method comprising the steps of:reading the map entry from the memory, the map entry identifying a correspondence between an element of the first hierarchy and an element of the second hierarchy;using mapping rules directed to match elements in said hierarchies of elements where any given mapping rule spans plural levels of said hierarchies, generating other map entries according to the read map entry, and storing the generated other map entries in the memory such that the map entry and the generated other map entries together form a set of map entries stored in the memory, the generated other map entries identifying other correspondences between the elements of the first hierarchy and the elements of the second hierarchy; andcomparing the first representation with the second representation according to the set of map entries, a result of a comparison between the first and second representations indicating whether the first representation matches with the second representation.