Patent ID: 6551886
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A method of incorporating a high-k dielectric gate insulator after silicide formation within a MOSFET transistor fabrication process on an SOI wafer that provides extended silicide depth, comprising:forming a silicon-insulator stack wherein a segment from a deposited layer of insulator is positioned over a segment of silicon from the SOI wafer; forming a second silicon layer from amorphous silicon (a-Si), wherein the second silicon layer has a planar upper surface which does not cover the segment of insulation; implanting source-drain dopants beneath the segment of insulation; annealing the substrate; forming silicide on the upper portion of the second silicon layer; removing of the segment of insulation to create a gate cavity; forming a gate stack within the gate cavity, having a gate electrode insulated from the substrate by a high-k dielectric whereupon the remainder of the MOSFET transistor may be fabricated utilizing conventional process steps.