Patent ID: 7183159
Filing Date: 2007-02-27
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of forming an integrated circuit, comprising: providing a substrate; identifying a first region overlying the substrate for locating a first plurality of transistors; identifying a second region overlying the substrate for locating a second plurality of transistors; identifying a third region overlying the substrate for locating a third plurality of transistors; forming a plurality of gate insulators of the first plurality of transistors in the first region of the integrated circuit, the plurality of gate insulators of the first plurality of transistors having a first average gate insulator thickness; subsequent to forming the plurality of gate insulators of the first plurality of transistors, forming a plurality of gate insulators of the second plurality of transistors and forming a layer of nanoclusters overlying the plurality of gate insulators of the second plurality of transistors, the plurality of gate insulators of the second plurality of transistors having a second average gate insulator thickness; subsequent to forming the layer of nanoclusters, forming in the third region of the integrated circuit a plurality of gate insulators of the third plurality of transistors having a third average gate insulator thickness, wherein the third average gate insulator thickness is substantially less than the first average gate insulator thickness; and completing formation of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors.