Patent ID: 9178036
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A method of forming replacement gate structures for first and second transistor devices, comprising: performing at least one etching process to remove sacrificial gate structures for said first and second transistor devices to thereby define first and second gate cavities for said first and second transistor devices, respectively, said first and second gate cavities being laterally defined by sidewall spacers; forming a high-k oxide gate insulation layer in said first and second gate cavities; forming a conformal patterned masking layer that covers said high-k oxide gate insulation layer in said second gate cavity while exposing said high-k oxide gate insulation layer in said first gate cavity; forming a metal oxide material layer on said high-k oxide gate insulation layer in said first gate cavity and on said conformal patterned masking layer that is positioned within said second gate cavity; performing at least one recess etching process such that a first portion of said high-k oxide gate insulation layer and a first portion of said metal oxide layer is positioned entirely within said first gate cavity and a second portion of said high-k oxide gate insulation layer, said conformal patterned masking layer and a second portion of said metal oxide layer is positioned entirely within said second gate cavity; forming a conformal capping layer above materials within said first and second gate cavities; performing at least one heating process to drive metal material from said metal oxide layer into said first portion of said high-k oxide gate insulation layer in said first cavity to thereby form a composite metal-high-k oxide alloy gate insulation layer in said first gate cavity, while preventing metal from said metal oxide material from being driven into said second portion of said high-k oxide gate insulation layer in said second gate cavity during said at least one heating process; removing said conformal capping layer; removing at least said conformal patterned masking layer from within said second gate cavity; and performing at least one process operation to form a first gate electrode structure above said metal-high-k oxide alloy gate insulation layer in said first gate cavity and a second gate electrode structure above said high-k oxide gate insulation layer in said second gate cavity.