Patent ID: 6764892
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of fabricating into the surface of a n-well, having first and second side-walls in a p-tank, a pnpn SCR integrated with a drain-extended nMOS transistor for multi-voltage operation having built-in ESD protection, said surface having a layer of insulating material suitable as gate dielectric and a poly-silicon gate deposited on said insulating layer at the location where said first side-wall intersects said surface, comprising the steps of:depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said p-tank area adjacent said poly-silicon gate and covering said n-well and said p-tank adjacent said second side-wall; implanting, at low energy and low dose, n-doping ions into said exposed surface area, thereby creating shallow, lightly n-doped layers under said surface and leaving the area under the photoresist unimplanted; removing said first photoresist layer; depositing a conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface; forming a second patterned photoresist layer to protect portions of said dielectric layer defining the bases of the pnp and the npn portions of said SCR; directional plasma etching said dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor; removing said second photoresist layer; forming a third patterned photoresist layer to protect a portion of said surface defining the anode of said SCR; implanting, at medium energy, n-doping ions into said surface, thereby creating n-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and as npn portion of said SCR, the junction of one of said SCR n-regions partially formed with said p-tank and partially with said n-well; removing said third photoresist layer; depositing a fourth photoresist layer and opening a window therein, thereby exposing the surface of said anode of said pnp portion of said SCR; implanting, at medium energy and high dose, p-doping ions into said window, thereby creating a p-doped region at medium depth, suitable as anode of said SCR; and removing said fourth photoresist layer.