Patent ID: 6678795
Filing Date: 2004-01-13
Classification: G06F

Abstract:
An apparatus for fetching at least one of instructions and operand data from a second memory into a first memory of a computer system having at least one processor, the apparatus comprising:a table, associated with the first memory, adapted to store a plurality of entries, wherein each entry is associated with a memory page that includes a plurality of storage elements in the second memory, and comprises information of prior access by the at least one processor to each of the plurality of storage elements; an engine, associated with the first memory, adapted to search the table for a given entry associated with a given page that includes a target of a request, and to generate at least one prefetch request to fetch at least one storage element included in the given page from the second memory to the first memory based upon given information comprised in the given entry if the given entry is found, the request corresponding to a miss to the first memory from the at least one processor; a controller, associated with the first memory, adapted to analyze the at least one prefetch request with respect to other prefetch requests and fetch requests, if any, to determine which of the at least one prefetch request and the other prefetch requests are to be satisfied, prior to satisfying the at least one prefetch request, wherein the apparatus prefetches arbitrary lines within the given page based upon prior access information of the given page, wherein said controller is further adapted to prioritize an order of the at least one prefetch request the other prefetch requests, and the fetch requests with respect to other operations being handled by the second memory.