Patent ID: 9100233
Filing Date: 2015-08-04
Classification: H03G,H03M,H04L

Abstract:
1. An apparatus comprising: a linear equalizer for receiving an input signal and outputting a partly equalized signal; a VGA (variable gain amplifier) for receiving the partly equalized signal and outputting an amplitude-adjusted signal in accordance with a gain control signal; a non-uniform ADC for receiving the amplitude-adjusted signal and outputting a digitized signal, the digitized signal comprising digitized levels that are non-uniformly displaced; and a DSP (digital signal processing) circuit for receiving the digitized signal and outputting a recovered bit stream by performing a signal detection and establishing the gain control signal by performing automatic gain control, wherein the non-uniform ADC has a lower precision when a level of the amplitude-adjusted signal is sufficiently close to an ideal level corresponding to a logical “1” datum, sufficiently close to an ideal level corresponding to a logical “0” datum, or sufficiently different from a middle level of an ideal level corresponding to a logical “1” datum and an ideal level corresponding to a logical “0” datum, and the non-uniform ADC has a higher precision when the level of the amplitude-adjusted signal is sufficiently close to the middle level.