Patent ID: 6061273
Filing Date: 2000-05-09
Classification: G11C

Abstract:
A pre-charge step determining circuit of a generic bit line of a memory device, particularly for non-volatile memories, including a plurality of bit lines wherein fewer than all of the plurality of bit lines can be selected for pre-charging during a given pre-charge interval, the circuit comprising:means for simulating selection/deselection of the generic bit line of the memory device which is to be pre-charged during a pre-charge interval of the memory device, the generic bit line being selected/deselected from among the plurality of bit lines;means for simulating pre-charging of a bit line, said pre-charging simulation means being activated by said selection/deselection means; andmeans for determining when a working point of said bit line is reached, said working point determining means being activated by said pre-charging simulation means and generating a pre-charge end signal so as to define a minimal duration of pre-charging that is closely correlated with characteristics of actual selection/deselection and pre-charge circuits of the memory device, with supply conditions, and with propagation of a generic bit line in the memory device, said pre-charge simulation means and said working point determining means being activated synchronously with respect to a new reading cycle of the memory device.