Patent ID: 7504327
Filing Date: 2009-03-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: forming an amorphous semiconductor film over an insulating surface; forming a crystalline semiconductor film by irradiating the amorphous semiconductor film with laser light; forming a semiconductor layer by patterning the crystalline semiconductor film; forming a gate insulating layer over the semiconductor layer; forming a first conductive layer over the gate insulating layer; forming a second conductive layer over the first conductive layer; etching the second conductive layer to form a first gate layer; forming first impurity regions by doping the semiconductor layer from one direction obliquely to the surface thereof with a first impurity element for imparting first one conductive type, using the first gate layer as a mask, wherein a portion of one of the first impurity regions is covered with the first gate layer; forming a third impurity region and a fourth impurity region by doping the semiconductor layer perpendicularly to the surface thereof with a second impurity element for imparting second one conductive type, using the first gate layer as a mask, thereby defining a channel forming region and a second impurity region between the third and fourth impurity regions, wherein the second impurity region is the portion of the one of the first impurity regions covered with the first gate layer and wherein the third and fourth impurity regions and the first impurity regions are partially overlapped; forming an insulating layer on side surfaces of the first gate layer over the first conductive layer; etching the first conductive layer to form a second gate layer using the insulating layer and the first gate layer as a mask; and forming source and drain regions in the third and fourth impurity regions, respectively, by doping the semiconductor layer perpendicularly to the surface thereof with a third impurity element for imparting the second one conductive type, using the first and second gate layers and the insulating layer as a mask, thereby defining fifth and sixth impurity regions in the third and fourth impurity regions, respectively, wherein the fifth and sixth impurity regions are adjacent to the source and drain regions and covered with the insulating layer and the second gate layer, wherein each concentration of the second and third impurity elements for imparting the second one conductive type in the fifth impurity region and the sixth impurity region is lower than that of the second and third impurity elements for imparting the second one conductive type in the source and drain regions, wherein the second impurity region is formed between the channel formation region and the fifth impurity region and covered with the first and second gate layers, and wherein the sixth impurity region is formed in contact with the channel formation region.