Patent ID: 6867626
Filing Date: 2005-03-15
Classification: G11C

Abstract:
1. A clock synchronization circuit comprising: first and second bidirectional delay circuit strings, each circuit string having an input terminal and an output terminal, in which an edge of a clock signal received at said input terminal proceeds in one direction and then is reversed in the proceeding direction thereof, based on a turn control signal generated on the basis of an edge of a clock signal next following said input clock signal, said clock edge proceeding in the direction reverse to said one direction, over a time equal to the time during which said clock edge proceeded in said one direction, so as to be output at said output terminal; a first pre-stage delay circuit and a first post-stage delay circuit, delay times thereof being able to be variably set, arranged at a pre-stage and at a post-stage of said first bidirectional delay circuit string, respectively; a second pre-stage delay circuit and a second post-stage delay circuit, delay times thereof being able to be variably set, arranged at a pre-stage and at a post-stage of said second bidirectional delay circuit string, respectively; a multiplexing circuit receiving output signals of said first and second post-stage delay circuits to output a multiplexed signal of said output signals of said first and second post-stage delay circuits; and a delay time setting circuit for performing control for variably setting the delay time of said first and second pre-stage delay circuits and the delay time of said first and second post-stage delay circuits, wherein said delay time setting circuit variably controls the delay times of said pre-stage and post-stage delay circuits according to a relationship between a minimum delay time for circuit operation and a period of said clock signal received by the clock synchronization circuit; wherein the clock signal received by the clock synchronization circuit is supplied in common to the input terminals of said first and second pre-stage delay circuits; and wherein the clock synchronization circuit further comprises phase selection controlling means for alternately selecting a first path including said first pre-stage delay circuit, said first bi-directional delay circuit string and said first post-stage delay circuit and a second path including said second pre-stage delay circuit, said second bi-directional delay circuit string and said second post-stage delay circuit, in an interval of a preset cycle of said clock signal.