Patent ID: 7078347
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A method for forming a MOS transistor, comprising: forming a gate structure of a first height over a semiconductor body; forming a first sidewall structure layer over the gate structure and over source/drain regions in the semiconductor body adjacent to the gate structure; forming a second sidewall structure layer over the first sidewall structure layer; patterning the second sidewall structure layer, thereby removing the second sidewall structure layer over the first sidewall structure layer on a top portion of the gate structure and over the source/drain regions, and thereby defining an aggregate sidewall structure having a first width and a first height; and patterning the first sidewall structure layer and a portion of the remaining second sidewall structure layer in the aggregate sidewall structure, thereby exposing the top portion of the gate structure and reducing a width of the aggregate sidewall structure to a second width, and reducing a height of the aggregate sidewall structure to a second height.