Patent ID: 6292044
Filing Date: 2001-09-18
Classification: G06F,H03L

Abstract:
A clock switch circuit for providing a clock output signal selectable from a plurality of clock signals, comprising:at least three sets of clock drivers wherein two sets of the at least three sets of clock drivers receive clock inputs, a first one of the at least three sets of clock drivers is associated with a currently selected clock, a second one of the at least three sets of clock drivers is associated with a clock to next be selected, and a third one of the at least three sets of clock drivers is associated with a clock output signal;a plurality of edge detectors which receive a plurality of input signals for selecting clock inputs for turning on each one of the at least three sets of clock drivers in response to a change in a logic value in one of a plurality of clock select signals;a synchronization means for synchronizing the input select signals to the output clock, and then synchronizing these synchronized signals to each input clock signal;a first plurality of logic gates for receiving the synchronized clock select signals and the input clock signals and for switching a clock output signal from the currently selected clock to the clock to next be selected synchronously;a clock driver for receiving the output of the first plurality of logic gates and for outputting the final clock output signal;a reset means for turning off the at least three sets of clock drivers once the clock output signal has been switched from the currently selected clock to the clock to next be selected, whereby the at least three sets of clock drivers are inactive until a logic value in a second one of the plurality of clock select signals changes, thereby preserving power when the circuit is not switching; anda means for pulling the final clock to the desirable logic level when the clock is not stable during switching.