Patent ID: 7844991
Filing Date: 2010-11-30
Classification: H04N

Abstract:
1. A digital signal processing apparatus, comprising: a plurality of digital signal processing blocks connected to a common bus, each digital signal processing block including at least a signal processing block for decoding and processing high speed streams of data, each of at least some of said digital signal processing blocks being operative to control hardware associated with said block and having (a) a hardware driver performing a predetermined function assigned to said block for driving the hardware associated with said block and (b) a processing unit for activating said hardware driver to control said associated hardware in response to a high layer command supplied to said processing unit; a host processing block for controlling said digital processing apparatus by outputting to the processing unit in a respective digital signal processing block said high layer command, said high layer command being independent of the particular structure of the hardware coupled to said digital processing block, said high layer command being free of those functionality instructions that control individual ones of said predetermined functions of the hardware driver in said respective digital signal processing block, said high layer command being a general-purpose script type command that is interpreted by the processing unit in the digital signal processing block to which said high layer command is supplied to perform the function generally described by said high layer command, and said high layer command not being on a real time basis, said high layer command instructing the processing unit in said digital signal processing block to activate said hardware driver of said digital signal processing block to perform the predetermined function assigned to said respective digital signal processing block; and a common bus for connecting said host processing block and said plurality of digital signal processing blocks together for transferring via said common bus both said high layer command that is not on a real time basis and said high speed streams of data, wherein said processing unit of each of said digital signal processing blocks interprets and executes said high layer command to produce driver control instructions for said hardware driver to operate said hardware of particular structure associated with said digital signal processing block in accordance with said high layer command.