Patent ID: 9117893
Filing Date: 2015-08-25
Classification: B82Y,H01L

Abstract:
1. A tunneling transistor comprising: a heterostructure comprising a first material and a second material; a source region formed in the heterostructure such that the source region is formed in the first material and the second material; a drain region extending below an upper surface of the heterostructure and consisting of a metallic drain region or a drain region having a conductivity type opposite a conductivity type of the source region; a channel region formed between the source region and the drain region; and a gate stack formed in association with the channel region, the gate stack comprising a gate electrode and a gate dielectric, wherein the first material and the second material of the heterostructure extend on opposite sides of the gate stack; and wherein a metallurgical junction of the first and second materials in the heterostructure is substantially parallel with an interface between the gate electrode and the gate dielectric, the second material is closer to the gate stack than the first material, and the first and second materials in the heterostructure have an Ec/Ev offset at the metallurgical junction that lowers the height and width of a tunnel barrier of the tunneling transistor as compared to a tunnel barrier of a homogeneous tunneling transistor using the first material.