Patent ID: 7047461
Filing Date: 2006-05-16
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: test data output nodes arranged in a width of a plurality of bits; an internal data bus, greater in bit width than said test data output nodes, for transferring internal data; and test circuitry for comparing a predetermined number of bits of the internal data on said internal data bus with bits of test expected value data equal in bit width to said test data output nodes for each bit, and outputting data indicating respective comparison results to said test data output nodes in parallel, wherein said test circuitry includes: a select circuit for selecting the predetermined number of bits of said internal data in accordance with a test address signal; and a comparison circuit for comparing the bits selected by said select circuit with the respective bits of said test expected value data, and transmitting data signals indicating the respective comparison results to said test data output nodes, in parallel.