Patent ID: 9225504
Filing Date: 2015-12-29
Classification: H04L

Abstract:
1. A clock data recovery circuit for sampling an input signal according to a reference clock to generate a plurality of sampling results, comprising: a clock generation circuit, for generating a first sampling clock and a second sampling clock according to the reference clock, wherein a phase difference between the first sampling clock and the second sampling clock is larger than 0 and smaller than half a UI (unit interval) of the input signal, and each UI corresponds to an input data; a sampling circuit, coupled to the clock generation circuit and receiving the input signal, for sampling successive UIs of the input signal according to the first sampling clock and the second sampling clock, wherein a first sampling result and a second sampling result corresponding respectively to the first sampling clock and the second sampling clock are generated in each UI; a comparing circuit, coupled to the sampling circuit, for comparing the first sampling result and the second sampling result to generate a comparison result; and a determination circuit, coupled to the comparing circuit, for generating an adjusting signal according to the comparison result and the input data; wherein the clock generation circuit adjusts the first sampling clock and the second sampling clock according to the adjusting signal to make at least one of the two sampling results of each UI substantially correspond to a peak value at the UI of the input signal.