Patent ID: 8400343
Filing Date: 2013-03-19
Classification: H03M

Abstract:
1. A stage of a pipeline analog-to-digital converter (ADC), comprising: a successive-approximation-register (SAR) ADC including a capacitor array, for converting an input analog signal to a digital code and accordingly generating a first residual signal from an output of the capacitor array, wherein the capacitor array is controlled by the digital code; a sub capacitor array, for generating a second residual signal from an output of the sub capacitor array by the digital code, wherein the capacitor array and the sub capacitor array samples the input analog signal before the digital code is obtained; an estimate amplifier, for generating an estimate signal according to the second residual signal; an output amplifier, for generating an third residual signal according to the first residual signal and the second residual signal; and a feedback circuit, for storing the estimate signal during an estimate phase and generating an output residual signal during a level-shifting phase according to the first residual signal, the second residual signal, and the third residual signal.