Patent ID: 6448661
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A three-dimensional, multi-chip package formed by stacking a number (N) of semiconductor integrated circuit chips, each chip comprising:an integrated circuit die having an upper surface and a lower surface; a chip selection terminal formed on the upper surface of said die; a number (Nâˆ’1) of chip selection pads formed on the upper surface of said die proximate to said chip selection terminal; an insulation layer formed on the upper surface; a number (Nâˆ’1) of first metal wirings formed within said insulation layer, each of said first metal wirings connected to a corresponding one of said chip selection pads; upper connection terminals formed on said insulation layer and connected to said first metal wirings; lower connection terminals formed on the lower surface of said die corresponding to said upper connection terminals; and trench wirings formed through said die, said trench wirings connecting said chip selection terminal or said chip selection pads to said lower connection terminals, wherein among said chip selection pads, a first chip selection pad next to said chip selection terminal is connected to the upper connection terminal formed above said chip selection terminal, and the (Nâˆ’1)th chip selection pad is connected to the upper connection terminal formed above the (Nâˆ’2)th chip selection pad, and wherein said chips are stacked by attaching said upper connection terminals of a lower chip to said lower connection terminals of an upper chip, and said chip selection terminal of each chip is connected to a corresponding one of said lower connection terminals of a lowermost chip.