Patent ID: 7120052
Filing Date: 2006-10-10
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of an 2 a plurality of bit lines connected to said plurality of memory cells arranged in the column direction; a plurality of word lines connected to said plurality of memory cells arranged in the row direction; a first and a second flag cell which are selected at the same time when the memory cells are selected by the word lines; a write circuit which divides an n number of pages composed of an n number of bits stored in a plurality of memory cells selected by one of the word lines, into a first and a second area and, when writing data into the first area on a k-th page (2<=k<=n), writes the data into also the first flag cell and, when writing data into the second area on the k-th page, writes the data into also the second flag cell.