Patent ID: 7605622
Filing Date: 2009-10-20
Classification: G06F,H03L

Abstract:
1. A delay locked loop (DLL) of a memory device having a normal mode and a power down mode, comprising: a clock buffer for buffering an external clock signal to output an internal clock signal; a power down mode controller for generating a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal; a source clock generation unit for receiving the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal; and a phase update unit for performing a phase update operation based on the DLL source clock signal to output a DLL clock signal, wherein the source clock generation unit generates the DLL source clock signal for performing the phase update operation at least one time during the power down mode, and wherein the source clock generation unit includes a first clock divider for generating a first division clock signal to set a duration of the phase update operation in the normal mode by dividing the internal clock signal and a second clock divider for generating a second division clock signal to set a duration of the phase update operation in the power down mode by dividing the first division clock signal.