Patent ID: 6138228
Filing Date: 2000-10-24
Classification: G06F

Abstract:
An internal BUS link system between the different constituent components of a micro-controller, these components clocked by a clock signal exchanging during a transaction on each clock cycle at least one useful data word encoded on N bits between a request generator component, denoted the master component, and an addressee receiver component, denoted the slave component, wherein said link is made by means of at least one N+p bits BUS link, each link enabling the generation of instruction messages encoded on N+p bits comprising, at least, on a same current clock cycle:a main field comprising a useful data word encoded on N bits communicated by the master component to the slave component;an auxiliary field encoded on p bits, this auxiliary field comprising at least one operation code field enabling identification of the instruction message and a signature field enabling identification of the master component and the slave component addressee of this instruction message as well as the transaction occurring between said master component and said slave component, and, on a clock cycle following said current clock cycle:a proof of transmission message field from the master component to said slave component and an acknowledgement message field from said slave component to said master component, the true value of said proof of transmission message and the true value of said acknowledgement message enabling validation of a partial transaction between said master component and said slave component, thereby allowing to ensure from each master or slave component the successive transmission of instruction messages on successive instruction cycles to an addressee slave or master component, in accordance with a succession of partial transactions constituent of one transaction.