Patent ID: 8130567
Filing Date: 2012-03-06
Classification: G11C

Abstract:
1. A memory architecture comprising: a plurality of local input and output circuitries (LIOCs), each LIOC coupled to at least one memory bank; and a global input and output circuitry (GIOC) coupled to the plurality of LIOCs, the GIOC comprising a plurality of global sub-write circuitries, wherein one global sub-write circuitry out of the plurality of global sub-write circuitries is enabled to provide a write-data to a selected LIOC from the plurality of LIOCs, wherein the memory architecture comprises a level sensitive triggering circuit coupled to each of the plurality of LIOCs and the GIOC to indicate storage of the write-data in a storage element of the selected LIOC, and wherein the GIOC comprises an odd-delay circuit coupled to the level sensitive triggering circuit, and wherein the odd-delay circuit provides a feedback signal to reset the GIOC based on the indication.