Patent ID: 8760908
Filing Date: 2014-06-24
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array which comprises a plurality of first lines, a plurality of second lines intersecting the plurality of first lines and a plurality of memory cells which are arranged at each intersection part of the plurality of first and second lines and which store an electrically rewritable resistance value as data in a non-volatile manner; a first decoder which is connected to one ends of the plurality of first lines and selects the first lines; a second decoder which is connected to one ends of the plurality of second lines and selects the second lines; and a voltage applying circuit which is connected to one of the first decoder and the second decoder and which applies a predetermined voltage between the first lines and the second lines selected by the first decoder and the second decoder, the second decoder sequentially selecting the second lines in a direction from the other ends of the first lines to the one ends of the first lines.