Patent ID: 7771892
Filing Date: 2010-08-10
Classification: G03F

Abstract:
1. A double exposure method for a fabricating a semiconductor integrated circuit, the method comprising: providing a cell region and a peripheral circuit region on a substrate; performing a primary exposure using a photomask and a modified illuminating system as a light source; and performing a secondary exposure using the photomask and a general illuminating system as a light source, wherein the photomask comprises a halftone phase shift mask disposed in a first region of a substrate and an alternating phase shift mask disposed in a second region of the substrate, the first region allowing a cell pattern to transfer to the cell region on a semiconductor wafer and the second region allowing a peripheral circuit pattern to transfer to the peripheral circuit region on the semiconductor wafer, wherein the halftone phase shift mask comprises a first halftone layer pattern: wherein the alternating phase shift mask comprises: