Patent ID: 9207704
Filing Date: 2015-12-08
Classification: G06F,H03K

Abstract:
1. A method comprising: generating an output clock signal using one of a first clock signal and a second clock signal; receiving a transition of a select signal indicating to switch from generating the output clock signal using the one of the first clock signal and the second clock signal to generating the output clock signal using another of the first clock signal and the second clock signal; generating a first reset signal responsive to a direction of the transition of the select signal being in a first direction; generating a second reset signal responsive to the direction of the transition of the select signal being in a second direction; supplying the first reset signal to reset a first circuit forming a first path used by the first clock signal if the direction of the transition is in the first direction; and supplying the second reset signal to reset a second circuit forming a second path used by the second clock signal if the direction of the transition is in the second direction.