Patent ID: 8586873
Filing Date: 2013-11-19
Classification: H05K,Y10T

Abstract:
1. A test point design comprising: a. a circuit board comprising a plurality of layers including a power plane, a ground plane, and a dielectric plane between the power plane and the ground plane, the circuit board further comprises a differential pair of signal lines including a first signal line and a second signal line; and b. a pair of test point pads including a first test point pad connected to the first signal line and a second test point pad connected to second signal line, wherein a first portion of the power plane and a first portion of the ground plane below the first test point pad are removed, and a first portion of the dielectric plane below the first test point is not removed, and a second portion of the power plane and a second portion of the ground plane below the second test point pad are removed, and a second portion of the dielectric plane below the second test point is not removed, wherein the first portions of the power plane and the ground plane that are removed, and the first portion of the dielectric plane that is not removed are the portions of the power plane, dielectric plane and the ground plane that are aligned underneath the first test point pad, and the second portions of the power plane and the ground plane that are removed, and the second portion of the dielectric plane that is not removed are the portions of the power plane, dielectric plane and the ground plane that are aligned underneath the second test point pad, and wherein the removed portions remain void of any material.