Patent ID: 6165831
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method of fabricating a static random access memory, comprising the steps of:providing a substrate:forming an oxide layer and a first conductive layer on the substrate;patterning the first conductive layer and the oxide layer to form a gate having sidewalls;performing a first ion implantation to form a lightly doped region in the portion of the substrate beside the gate;forming spacers on the sidewalls of the gate;performing a second ion implantation to form a heavily doped region in the portion of the substrate beside the spacers wherein the lightly doped region and the heavily doped region compose a source/drain region;forming a metallic layer over the substrate;performing a thermal treatment to convert a portion of the metallic layer into a metal silicide layer on the gate and the source/drain region;removing remaining portion of the metallic layer without forming the metal silicide layer;forming a second conductive layer over the substrate;patterning the second conductive layer to form a conductive line, being electrically coupled to the metal silicide layer on the source/drain region;forming a dielectric layer having a via exposing the conductive line by the via over the substrate;forming a polysilicon layer conformal to the dielectric layer and the via;patterning the polysilicon layer to form a polysilicon conductive line wherein the polysilicon conductive line is electrically coupled to the conductive line; andperforming a third ion implantation to form a poly loan over the via.