Patent ID: 8082426
Filing Date: 2011-12-20
Classification: G06F

Abstract:
1. A system for supporting a plurality of Graphics Processing Units (GPUs), comprising: a context status register configured to send data related to a status of at least one context; a context switch configuration register configured to send instructions related to at least one event for the at least one context; a context status management logic coupled to the context status register and the context switch configuration register, the context status management logic configured to receive the data related to a status of at least one context, the context status management logic further configured to receive the instructions from the context switch configuration register and perform an action according to the received instructions; and a memory access unit configured to send a snoop event signal to and receive control data from the context status management logic; a bus interface unit, the bus interface unit including logic for decoding an address of a context register and generate a register update event signal; and an encoder configured to generate a related context number to be sent to the context status management logic, wherein the encoder is further configured to define a context number subsequent to execution of a memory write operation.