Patent ID: 7999397
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A microelectronic package comprising: a substrate having a top surface and a bottom surface; a microelectronic element overlying the top surface of said substrate, said microelectronic element having an outer perimeter, faces and contacts accessible at one or more of the faces; a plurality of conductive traces extending along at least one of the top or bottom surfaces of said substrate and conductively connected with said microelectronic element; a plurality of substantially rigid conductive posts exposed at the bottom surface of said substrate, said conductive posts including outermost ones disposed closest to said outer perimeter of said substrate, said conductive traces and said posts being formed integrally by subtractively patterning a layered metal structure into said conductive traces and said posts; and a protective layer in contact with said microelectronic element and overlying said substrate, wherein said protective layer extends outwardly beyond outermost ones of said conductive posts.