Patent ID: 7345929
Filing Date: 2008-03-18
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device formed on a semiconductor chip comprising: a plurality of first memory arrays; a plurality of second memory arrays; a first voltage generator; and a plurality of first bonding pads; wherein the semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region, wherein the third rectangle region is arranged between the first rectangle region and the second rectangle region, wherein the plurality of first memory arrays are formed in the first rectangle region, wherein the plurality of second memory arrays are formed in the second rectangle region, wherein the voltage generator and the plurality of first bonding pads are arranged in the third rectangle region, wherein the plurality of first bonding pads are arranged between the first rectangle region and the voltage generator; wherein no bonding pads are arranged between the first voltage generator and the plurality of second memory arrays, and wherein the first voltage generator is provided at a center portion between the plurality of first memory arrays and the plurality of second memory arrays.