Patent ID: 7508053
Filing Date: 2009-03-24
Classification: H01L

Abstract:
1. A metal-oxide-semiconductor (MOS) transistor device, comprising: a semiconductor substrate having thereon an active area; a shallow trench isolation (STI) region isolating the active area, wherein a step height h is formed between the STI region and the active area; a gate dielectric layer on the active area; a gate electrode on the gate dielectric layer, wherein the gate electrode has vertical sidewalls and a top surface; a liner on the vertical sidewalls of the gate electrode; a source region in the active area; a drain region separated from the source region by a channel region under the gate electrode; a silicide layer formed on the top surface of the gate electrode, on the source region and on the drain region; and a stressed cap layer covering the liner and the silicide layer and extending to the STI region, wherein the stressed cap layer has a specific stress status.