Patent ID: 6376308
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A process for fabricating an EEPROM device comprising the steps of:forming an ONO layer of the EEPROM device over a semiconductor substrate; forming a masking pattern overlying the ONO layer, the masking pattern having a first lateral dimension; etching the ONO layer using the masking pattern as an etching mask to form a patterned ONO layer, the first lateral dimension transferred to the patterned ONO layer; doping the semiconductor substrate to form buried bit-line regions in the semiconductor substrate; performing a plasma resist trimming process for reducing the first lateral dimension of the masking pattern to a second lateral dimension and exposing a surface portion of the patterned ONO layer, wherein the second lateral dimension is less than the first lateral dimension; doping the semiconductor substrate by ion implantation at an angle of incidence normal to a principle surface of the semiconductor substrate, using the patterned ONO layer as a doping mask, the dopant penetrating the exposed portion of the patterned ONO layer to form pocket regions in the semiconductor substrate; and oxidizing the semiconductor substrate to form bit-line oxide regions.