Patent ID: 6077743
Filing Date: 2000-06-20
Classification: H01L

Abstract:
A method for fabricating an array of brush-shaped stacked capacitors on dynamic random access memory (DRAM) devices comprising the steps of:forming field oxide areas on a semiconductor substrate while leaving device areas for fabrication of semiconductor devices;forming said semiconductor device structures in and on said device areas of said semiconductor substrate;depositing a first insulating layer over said device areas and said field oxide areas;planarizing said first insulating layer;forming first openings in said first insulating layer to said device areas where electrical contacts are desired for said array of stacked capacitors;depositing a first polysilicon layer on said first insulating layer and filling said first openings;depositing a silicide layer on said first polysilicon layer to form a polycide layer;patterning by photoresist masking and selective anisotropic plasma etching said polycide layer to said first insulating layer to form bit lines while leaving portions of said first polysilicon layer in said first openings to provide node contacts to said device areas for said stacked capacitors, and to serve as landing pads;depositing a second insulating layer over said bit lines and over said first polysilicon layer in said first openings;planarizing said second insulating layer;forming second openings in said second insulating layer to said first polysilicon layer in said first openings;depositing a second polysilicon layer and filling said second openings;depositing an etch endpoint detect layer on said second polysilicon layer;depositing a thick third polysilicon layer on said etch endpoint detect layer;depositing a third insulating layer on said third polysilicon layer;patterning said third insulating layer, said third polysilicon layer, said etch endpoint detect layer, and said second polysilicon layer to said second insulating layer thereby leaving portions over said second openings for bottom electrodes of said stacked capacitors;forming a layer of hemispherical-shaped grains (HSGs) from a conformal fourth polysilicon layer sufficiently thin to leave openings between said hemispherical-shaped grains, and further said hemispherical-shaped grains formed on the sidewalls of said bottom electrodes;plasma etching said third insulating layer between said hemispherical-shaped grains to said third polysilicon layer on top surface of said bottom electrodes while retaining said hemispherical-shaped grains on said sidewalls;anisotropic plasma etching said third polysilicon layer to said etch endpoint detect layer using said third insulating layer as a hard mask, and further removing said hemispherical-shaped grains between said bottom electrodes and forming an array of said bottom electrodes for said array of brush-shaped stacked capacitors;forming an interelectrode dielectric layer on said bottom electrodes;depositing and patterning a fifth polysilicon layer to form top electrodes thereby completing said array of brush-shaped stacked capacitors for said DRAM devices.