Patent ID: 6233188
Filing Date: 2001-05-15
Classification: G11C

Abstract:
A precharge control signal generating circuit in a precharge control circuit of a semiconductor memory, comprising:a complementary amplifier for receiving a precharge generation signal and outputting a precharge control signal;an operation power source supplying circuit for supplying an operation power source to the complementary amplifier, the circuit having a first electrode connected to a power source voltage of a device and a second electrode connected to a first electrode of the complementary amplifier;a level shifter for receiving a part of the precharge generation signal, raising its level to a value higher than the power source voltage of the device by a predetermined value, and transmitting it to the operation power source supplying circuit; anda capacitor for receiving a part of an output of the level shifter, supplying it to the first electrode of the complementary amplifier, and pumping the operation power source of the complementary amplifier by a predetermined value.