Patent ID: 8301871
Filing Date: 2012-10-30
Classification: G06F

Abstract:
1. A method of executing instructions, comprising: receiving a branch instruction along with one or more additional instructions scheduled to issue before the branch instruction in a cascaded delayed execution pipeline comprising at least a first pipeline and a second pipeline, wherein beginning of execution of instructions in the second pipeline is delayed with respect to beginning of execution instructions in the first pipeline, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between the branch instruction and the target instruction; determining if the branch instruction is preresolvable, wherein the branch instruction is preresolvable when one or more instructions preceding the branch instruction do not modify an outcome of the branch instruction; upon determining that the branch instruction is preresolvable: upon determining that the branch instruction is not preresolvable: