Patent ID: 6445615
Filing Date: 2002-09-03
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising a plurality of banks each including a plurality of word lines, a plurality of bit lines which are arranged to intersect the word lines, a memory cell array made up of non-volatile memory cells located at the intersections of the word lines and bit lines, and a data register which temporarily holds data to be written which enters from the outside, each of said banks operating to select a word line in accordance with an input command and the combination of input address signals and write data which is held in the data register to all or part of memory cells connected to the selected word line, wherein each of said banks has an independent write operation of data from the data register to memory cells, enabling the transfer of data from the outside to the data register of said bank even during the write operation of another bank from the data register to memory cells thereof; and further comprising a bank selection register which can hold more states than the number of said banks, thereby producing a signal for pointing one of said banks depending on the state, said bank selection register having its state established by an input signal from the outside.