Patent ID: 8228752
Filing Date: 2012-07-24
Classification: G11C

Abstract:
1. A memory circuit, comprising: a first memory array, comprising a first node and a second node, wherein the first node is coupled to a first supply voltage; a second memory array, comprising a third node and a fourth node, wherein the fourth node is coupled to a second supply voltage smaller than the first supply voltage; and a switch module, coupled to the second node of the first memory array, the third node of the second memory array, the first supply voltage and the second supply voltage; wherein when the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage to make the first memory array not directly supplied by the second supply voltage, and electrically disconnects the third node from the first supply voltage to make the second memory array not directly supplied by the first supply voltage.