Patent ID: 6754688
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A computer system comprising:a processor; a storage device coupled to the processor and having stored therein at least one instruction, which when executed by the processor, causes the processor to perform a floating point calculation; and a floating point unit included within the processor to perform the floating point calculation, the floating point unit comprises: a normalization detecting unit to determine an exponent difference, being a difference between exponents of two floating point numbers, and to bypass a complex normalization performed on a result produced by the floating point calculation if the exponent difference between the two floating point numbers is not less than two, a normalization execution unit to perform the complex normalization if the complex normalization is not bypassed, and a denormalization detecting unit to determine to bypass denormalization if the exponent difference is equal to or greater than a predetermined shift value, the denormalization detecting unit comprises: a less-than-two detector to determine if a predetermined number of most significant bits (MSB) of the exponent difference is less than two, and a selecting unit determining to bypass denormalization if the predetermined number of MSB of the exponent difference is not less than two.