Patent ID: 7498622
Filing Date: 2009-03-03
Classification: H01L

Abstract:
1. A structure, comprising: a P-well and an N-well formed in a semiconductor substrate, said P-well extending from a top surface of said substrate into said substrate a first distance, said N-well extending from said top surface of said substrate into said substrate a second distance; dielectric isolation extending from said top surface of said substrate into said substrate a third distance, said first, second and third distances less than a whole distance between said top and bottom surfaces of said substrate, said first and second distances greater than said third distances, said P-well abutting a bottom surface of said dielectric isolation and said N-well abutting said bottom surface of said dielectric isolation where said dielectric isolation extends into said N-well and said P-well; an array of spaced apart first gate electrodes positioned over said P-well, a first set of source/drains formed in said P-well between said first gate electrodes; an array of spaced apart second gate electrodes positioned over said N-well, a set of second source/drains formed in said N-well between said second gate electrodes; and an electrically conductive through via extending from said bottom surface of said substrate into said substrate a fourth distance, said fourth distance less than said whole distance, said through via contacting said P-well and abutting said bottom surface of shallow trench isolation that extends into said P-well.