Patent ID: 8024548
Filing Date: 2011-09-20
Classification: G06F

Abstract:
1. An integrated circuit microprocessor that configures integrated finite state machines, that are dedicated to executing particular computer algorithms, by utilizing both integrated re-configurable logic and configuration bit map codes that are generated by the integrated circuit microprocessor itself by decoding, re-ordering, parsing, and then converting, at run time, pre-compiled or pre-assembled sequences of binary encoded Complex Instruction Set Computer (CISC) type or Reduced Instruction Set Computer (RISC) type machine code instructions into said configuration bit map codes that are used by the integrated circuit microprocessor to configure, at run time, said integrated re-configurable logic into said integrated finite state machines in order to execute said particular computer algorithms at a faster rate than the rate at which said conventional CISC type or RISC type microprocessor can execute the same said particular computer algorithms; Wherein the pre-compiled or pre-assembled sequences are composed of members of a conventional CISC type or RISC type microprocessor's machine code instruction set; Wherein the pre-compiled or pre-assembled sequences represent said particular computer algorithms; and Wherein the integrated circuit microprocessor comprises: