Patent ID: 6154158
Filing Date: 2000-11-28
Classification: H03C,H03M

Abstract:
A D.C. offset correction circuit for removing D.C. offset errors from baseband transmission signals in a communications device, the device receiving digital baseband input signals, wherein the input signals are converted to analog signal by transmit digital-to-analog converters, and wherein the analog signals are filtered by reconstruction filters to produce the baseband transmission signals, comprising:a) an analog-to-digital (A/D) converter, comprising a 1-bit differential comparator disposed to convert the transmission signals to digital feedback signals by generating digitized representations of the signs of the transmission signals.b) a D.C. offset correction digital signal processing block having at least one input operatively coupled to the A/D converter, wherein the offset correction block processes the digital feedback signals to produce D.C. offset correction signals nominally equal to the D.C. offset errors, said processing block comprising:i) a decision block for generating an error signal responsive to the input signals and the transmission signals, wherein the error signal is indicative of the relative signs of the input signals and the transmission signals at any given time instance; andii) integrator means for integrating the error signal; andc) an adder, operatively coupled to the offset correction block, the adder having a first input for receiving the input signals and a second input for receiving the offset correction signals, wherein the correction signals are added to the input signals thereby removing the D.C. offset errors from the transmission signals.