Patent ID: 6812731
Filing Date: 2004-11-02
Classification: G06F,H03K

Abstract:
A structure implementing a user circuit in a programmable logic device (PLD), the PLD including programmable logic blocks, programmable interconnect lines, and programmable interconnect points (PIPs) interconnecting the logic blocks and interconnect lines, the structure comprising:N copies of the user circuit implemented using the logic blocks, interconnect lines, and PIPS, each copy having an output terminal, wherein N is an odd integer greater than three; a voting circuit having an output terminal and N input terminals, wherein the voting circuit provides a value common to at least (N+1)/2 of the voting circuit input terminals at the voting circuit output terminal; and programmable interconnections coupling the output terminals of the N copies of the user circuit to the N input terminals of the voting circuit via the interconnect lines and PIPs.