Patent ID: 8168452
Filing Date: 2012-05-01
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, the semiconductor device including an integrated circuit having a plurality of connection terminals arranged on a predetermined local region of the integrated circuit, a plurality of metal bumps, and a wiring layer connected to at least a portion of the connection terminals via the plural metal bumps, the method comprising: measuring an impedance value of a pair of connection terminals provided in the predetermined local region of the integrated circuit; determining whether the difference between the measured impedance value and a design specification value corresponding to the predetermined local region is within a permissible range; determining positions of the plural metal bumps on the integrated circuit in accordance with the determining of the difference between the measured impedance value and the design specification value; forming the plural metal bumps on the determined positions of the integrated circuit; forming an insulating layer above the integrated circuit after the forming of the plural metal bumps; and forming one or more wirings on the Insulating layer; wherein when the difference between the measured impedance value and the design specification value exceeds the permissible range, the measured impedance value is converted to a predetermined impedance value and at least one of the positions of the plural metal bumps is determined in correspondence with the conversion of the measured impedance value so that the predetermined impedance value is within the permissible range in a case where the plural metal bumps are formed on the determined positions.