Patent ID: 6125440
Filing Date: 2000-09-26
Classification: G06T

Abstract:
A digital processor control comprising:a memory adapted to store execution instructions to be executed, wherein such execution instructions may include at least one sequence of execution instructions that are to be executed more than one time, and said memory is responsive to a first control signal to produce ones of the stored execution instructions in accordance with said first control signal;a register having at least N stages where N is a positive integer, wherein said register is coupled to said memory to store the ones of the stored execution instructions produced by said memory, and said register is responsive to a second control signal to produce ones of the N most-recently produced execution instructions stored therein;whereby the N most-recently produced execution instructions are stored in said register without any special instruction therefor;a control device for detecting each of the execution instructions produced by said memory and said register that is a jump-back instruction that initiates repetition of the sequence of execution instructions that are to be executed more than one time; anda state machine responsive to said control device for generating said second control signal when an execution jump-back instruction is detected and for generating said first control signal when execution instructions to be executed more than one time are not detected,whereby the sequence of instructions that are to be executed more than one time are produced for execution from said register following the jump-back instruction.