Patent ID: 6342452
Filing Date: 2002-01-29
Classification: H01L

Abstract:
Method of fabricating a gate stack structure comprising:providing a structure comprising a semiconductor substrate underlying a gate dielectric layer, a doped polysilicon layer, a refractory metal layer and a top silicon nitride capping layer in sequence, said refractory metal and doped polysilicon layers forming a polycide layer under subsequent thermal treatments; depositing a layer of dielectric material onto said structure, said dielectric material being impervious to ultraviolet radiation and having a good conformal property; photolithographically patterning said layer of dielectric material to form an in-situ hardmask; using said in-situ hardmask, anisotropically etching said structure down to said semiconductor substrate to form a gate stack; conformally depositing silicon nitride over said gate stack; and with said in-situ hardmask still in place, anisotropically etching said conformally deposited silicon nitride to form spacers on sidewalls of said gate stack.