Patent ID: 6567426
Filing Date: 2003-05-20
Classification: G06F

Abstract:
In a computer system, a method for sharing access to a data memory among processors comprising, the steps of:receiving an active signal for accessing the data memory from a plurality of processors, one active signal per processor, wherein the data memory is accessible to the processor for transferring an N-bit wide data to or from the data memory; selecting a processor as a memory master among the processors asserting the active signals to the data memory; the processors further including: a signal processor; a plurality of co-processors, wherein the co-processors include a direct memory access (DMA) processor; selecting the DMA processor as a bus master if the DMA processor is active; selecting a co-processor as the bus master from the plurality of co-processors if the DMA processor is not active; selecting the signal processor as the bus master if neither the DMA processor nor any of the co-processors is active; and transferring the N-bit wide data between the selected processor and the data memory in a time slot defined by a clock; the transferring step further comprises the steps of: a) loading the N-bit wide data into an N-bit wide register; b) reading, by the selected processor, a subset of N-bit wide data during the clock cycle through a multiplexer until all N-bits have been read from the register over a plurality of clock cycles.