Patent ID: 9047439
Filing Date: 2015-06-02
Classification: B01J,C01B,C10G,G16C

Abstract:
1. A computing device for modeling a reverse-flow reactor, wherein the reactor comprises: a) a reverse-flow reactor having a reactor body; b) a first head engaged with said reactor body; c) a first conduit extending from outside said head to at least partially through said head; d) a first valve in flow communication with said first conduit controlling fluid flow along a flow path extending from the first valve and through the reactor body; wherein said first valve has a substantially open position when fluid flow in the flow path is in a first flow direction and a substantially closed position when fluid flow in the flow path is in a second, opposite flow direction; e) an optional second head engaged with said reactor body; f) a second conduit extending from outside the first head or the second head to at least partially through said respective head; and g) a second valve in flow communication with said second conduit controlling fluid flow along the flow path including a portion extended from the reactor body to the second valve, wherein the first and second valves are each in a substantially open position when fluid flow in the flow path is in a first flow direction and a substantially closed position when fluid flow in the flow path is in a second, opposite flow direction; h) a third conduit extending from outside the first head or the second head to at least partially through said respective head; i) a third valve in flow communication with said third conduit controlling fluid flow along the flow path including a portion extended from the reactor body to the third valve; j) a fourth conduit extending from outside the first head or the second head to at least partially through said respective head; and k) a fourth valve in flow communication with said fourth conduit controlling fluid flow along the flow path including a portion extended from the reactor body to the fourth valve; the computing device comprising: a processor; a memory coupled to the processor; and instructions provided to the memory, wherein the instructions are executable by the processor to: