Patent ID: 7512004
Filing Date: 2009-03-31
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell which has a first MOS transistor including a charge accumulation layer and a control gate formed on the charge accumulation layer; a word line which is connected to the control gate of the first MOS transistor and is set in a non-selected state at a test operation time of the memory cell; a bit line which is connected to a drain of the first MOS transistor and is applied with first voltage at the test operation time and at a data program operation time with respect to the memory cell; a source line which is connected to a source of the first MOS transistor and is set at potential lower than that of the bit line at the test operation time; a column gate including a second MOS transistor having current path connected to the bit line to transfer the first voltage to the bit line at the test operation time; and a power supply decode circuit which applies a second voltage to a gate of the second MOS transistor at the program operation time and applies a third voltage lower than the second voltage at the test operation time.