Patent ID: 6473727
Filing Date: 2002-10-29
Classification: G01R,G06F

Abstract:
A processor comprising:a memory; an address register coupled to said memory; and an in-circuit emulation subsystem coupled to said memory, said in-circuit emulation subsystem including: a plurality of scan chains each including a plurality of serially connected registers, wherein each or said plurality of scan chains is coupled to a scan input connection and a scan output connection; and a memory scan interface including a data register, wherein said data register is coupled to a first one of said plurality of scan-chains and configured to receive read data from said memory via a read data bus in response to activation of a system clock and to serially unload said read data via said first one of said plurality of scan-chains in response to activation of a scan clock; wherein said address register is further coupled to a second one of said plurality of scan-chains and configured to be serially loaded with an address value of a location in said memory, wherein said address register is configured to increment said address value in response to activation of said system clock; a microcode register coupled to be serially loaded with a microcode instruction via said second one of said plurality of scan-chains and configured to provide memory control signals in response to said microcode instruction being serially loaded; and a decode multiplexer coupled to said microcode register and configured to prevent disruption of the contents of said microcode register.