Patent ID: 7304375
Filing Date: 2007-12-04
Classification: H01L

Abstract:
1. Stackable castellation wafer level packages for packaging integrated circuit chips, said packages comprising: a first integrated circuit chip having active circuit areas; a second integrated circuit chip having active circuit areas; at least one first active circuit area contact coupled to the active circuit areas of the first integrated circuit chip; at least one second active circuit area contact coupled to the active circuit areas of the second integrated circuit chip; at least one first castellation contact, each at least one first castellation contact (a) coupled to respective at least one first active circuit area contacts, (b) having a thickness greater than a thickness of the first active circuit area contact, and (c) encapsulated at least in part by an encapsulant; at least one second castellation contact, each at least one second castellation contact (1) coupled to respective at least one second active circuit area contacts, (2) having a thickness greater than a thickness or the second active circuit area contact, and (3) encapsulated at least in part by an encapsulant; and at least one coupling contact that couples at least one of the at least one first castellation contacts to at least one of the at least one second castellation contacts wherein the coupling contact is on the inside face of a printed circuit board which is in a plane substantially perpendicular to the plane of the active circuit area of the first integrated circuit chip.