Patent ID: 6258680
Filing Date: 2001-07-10
Classification: H01L,Y10S

Abstract:
A method for forming an integrated circuit, comprising:providing a semiconductor topography upon which a gate conductor having opposed sidewall surfaces is formed;forming a first dielectric layer upon the opposed sidewall surfaces and an upper surface of the gate conductor;forming a second dielectric layer spaced from each of the opposed sidewall surfaces by the first dielectric layer and having dissimilar etch characteristics from the first dielectric layer;forming a third dielectric layer spaced from each of the opposed sidewall surfaces by the first and second dielectric layers, spaced from the upper surface of the gate conductor from the first dielectric layer, and having dissimilar etch characteristics from the second dielectric layer;implanting a first dopant into the semiconductor topography while the first dielectric layer is arranged upon the opposed sidewall surfaces and the upper surface of the gate conductor and the third dielectric layer is spaced from each of the opposed sidewall surfaces by the first and second dielectric layers;first annealing the semiconductor topography to activate the implanted first dopant;removing the third dielectric layer from said sequence of dielectric layers, said layer having dissimilar etch characteristics from an immediately adjacent layer within the sequence of dielectric layers;implanting, subsequent to said annealing, a second dopant into the semiconductor topography while the first dielectric layer is arranged upon the opposed sidewall surfaces and the upper surface of the gate conductor and the second dielectric layer is spaced from each of the opposed sidewall surfaces by the first dielectric layer;second annealing the semiconductor topography at a temperature lower than the first annealing to activate the implanted second dopant;removing the second dielectric layer;implanting a third dopant into the semiconductor topography while the first dielectric layer is arranged upon the opposed sidewall surfaces and an upper surface of the gate conductor; andthird annealing the semiconductor topography at a temperature lower than the first and second annealing to activate the implanted third dopant.