Patent ID: 8421071
Filing Date: 2013-04-16
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a NAND cell unit including a plurality of memory cells connected in series; a first selection transistor connected to a first terminal of the NAND cell unit; a second selection transistor connected to a second terminal of the NAND cell unit; a source line connected to the first selection transistor; and a bit line connected to the second selection transistor, wherein each of the first selection transistor and the second selection transistor comprises an oxide semiconductor layer including a channel region, wherein the first selection transistor overlaps with the NAND cell unit with an insulating layer interposed between the first selection transistor and the NAND cell unit, and wherein the second selection transistor overlaps with the NAND cell unit with the insulating layer interposed between the second selection transistor and the NAND cell unit.