Patent ID: 9189442
Filing Date: 2015-11-17
Classification: G06F,G11C,H01L,Y02D

Abstract:
1. An apparatus, comprising: NAND flash memory; random access memory; additional memory; a first circuit for receiving DDR signals and outputting SATA signals, the first circuit communicatively coupled to the additional memory, and further capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said apparatus configured such that: