Patent ID: 6269385
Filing Date: 2001-07-31
Classification: G06F

Abstract:
An apparatus for performing rounding and addition in parallel in a floating point multiplier, the apparatus comprising:an adder that receives a 2n bit sum S and a 2n bit carry C generated by multiplying fraction portions of first and second n bit floating point numbers, wherein the adder has an n bit half adder and an 1 bit full adder to respectively add upper n+1 bits from the carry C and the sum S and a 1 bit prediction signal to generate an added carry and an added sum;a C.sup.in.sub.n-2 carry overflow generator for generating an overflow carry C.sup.in.sub.n-2 to add to an n-2 bit of the carry C and an n-2 bit of the sum S;a predictor that provides the 1 bit prediction signal of 0 or 1 to the 1 bit full adder for generating the added carry and added sum;a carry select adder that adds each of 0 and 1 to an upper n bit value generated by adding the added carry with the added sum to generate both corresponding output values i0 and i1;a selector that outputs a control signal of 0 or 1 based on a rounding mode of the floating point multiplier selected from one of a round-to-nearest mode, a round-to-zero mode, and a round-to-infinity mode to select an AR value obtained by addition and rounding from the two output values i0 and i1 of the carry select adder;a first multiplexer that multiplexes the output values i0 and i1 in response to the control signal of the selector; anda result LSBNS q.sup.NS.sub.0 logic circuit that generates a least significant bit LSB of the AR value according to the rounding mode during no shift (NS).