Patent ID: 6493407
Filing Date: 2002-12-10
Classification: G06F

Abstract:
In a digital system including three or more modules, which are configured for sending and receiving address and data information using one or more respective inputs and outputs, a bus arrangement comprising:a) an input arrangement including a plurality of first, input latches each of which includes an input terminal and an output terminal such that each module input is connected with the output terminal of an associated input latch; b) an output arrangement having a plurality of second, output latches each of which includes an input terminal and an output terminal such that each module output is connected with the input terminal of an associated output latch; and c) an interconnection arrangement made up solely of electrical conductors for electrically interconnecting the output terminals of certain output latches with the input terminals of certain input latches in a specific way for transferring said address and data information between said modules such that said address and data information does not encounter logic circuitry between the input and output arrangements.