Patent ID: 9177870
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; an NMOS gate disposed over the substrate, wherein the NMOS gate includes: a high-k gate dielectric, a first capping layer disposed over the high-k gate dielectric, and a second capping layer disposed over the first capping layer, and wherein the first and second capping layers are configured to collectively tune a work function of the NMOS gate, wherein the second capping layer includes a bottom surface facing the substrate and a top surface facing away from the substrate such that a sidewall surface of the second capping layer extends from the bottom surface to the top surface of the second capping layer, wherein the first capping layer includes a bottom surface facing the substrate and a top surface facing away from the substrate such that a sidewall surface of the first capping layer extends from the bottom surface to the top surface of the first capping layer; and a PMOS gate disposed over the substrate, wherein the PMOS gate includes: a high-k gate dielectric, a third capping layer disposed over the high-k gate dielectric, and a first metal gate electrode disposed over the third capping layer, and wherein the third capping layer is configured to tune a work function of the PMOS gate, wherein the PMOS gate is free of the second capping layer, wherein the third capping layer of the PMOS gate physically contacts the first capping layer of the NMOS gate, wherein the first metal gate electrode of the PMOS gate physically cantacts the sidewall surface of the second capping layer of the NMOS gate, wherein the third capping layer of the PMOS gate physically contacts the entire sidewall surface of the first capping layer of the NMOS gate.