Patent ID: 8357573
Filing Date: 2013-01-22
Classification: H01L

Abstract:
1. A method, comprising: forming a gate electrode structure above a semiconductor region, said gate electrode structure comprising a high-k dielectric material, a metal-containing cap layer formed above said high-k dielectric material, a semiconductor material formed above said metal-containing cap layer and a dielectric cap material formed above said semiconductor material, said gate electrode structure having a tapered bottom portion with a reduced length; forming a spacer on sidewalls of said gate electrode structure, said spacer having a first spacer portion adhering to said tapered bottom portion and having a second spacer portion adhering to a substantially non-tapered portion of said gate electrode structure; forming an embedded strain-inducing semiconductor material in said semiconductor region with a lateral offset determined by said first spacer portion; and forming drain and source regions of a transistor in at least a portion of said strain-inducing semiconductor alloy.