Patent ID: 9053788
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A cross-point variable resistance nonvolatile memory device comprising: a cross-point memory cell array including memory cells each including: (i) a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state when different voltages are applied to the variable resistance element; and (ii) a current steering element that is connected in series to the variable resistance element and has nonlinear current-voltage characteristics, the memory cells being placed at respective cross-points of a plurality of bit lines and a plurality of word lines; a reference voltage generation circuit which generates a reference voltage by applying a current to a reference circuit which includes a current steering element formed in a manufacturing process that is the same as a manufacturing process of the current steering elements included in the memory cells; a differential amplifier circuit which performs current amplification on the reference voltage generated in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which applies a first current to a selected bit line until a voltage of a selected bit line reaches a voltage determined with reference to an output voltage of the differential amplifier circuit, the one selected bit line being one bit line selected from the bit lines; and a sense amplifier circuit which determines, according to an amount of current flowing through a selected memory cell after the first current is applied, whether the variable resistance element in the selected memory cell is in the low resistance state or the high resistance state, the selected memory cell being one memory cell connected to the selected bit line and selected from the memory cells, wherein the feedback controlled bit line voltage clamp circuit includes: a first transistor having a source terminal connected to an output of the differential amplifier circuit, and having a gate terminal connected to the selected bit line; and a second transistor which provides and stops providing a current to the selected bit line according to a voltage of a drain terminal of the first transistor.