Patent ID: 8877650
Filing Date: 2014-11-04
Classification: G03F,H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: providing a design for a layout for a lithography mask, the layout defining a pattern for a material layer of the semiconductor device, wherein the layout for the lithography mask comprises a first region comprising a first feature having a first width and a second region comprising a second feature having a second width, the second width being greater than the first width; determining an optical proximity correction (OPC) based on a reactive ion etch (RIE) lag of a RIE process for the material layer; altering the design for the layout for the lithography mask by the OPC determined, wherein altering the design for the layout for the lithography mask comprises decreasing the width of the second feature from the second width to a third width along an entire major side of the second feature; fabricating the lithography mask with the altered design; and patterning the material layer of the semiconductor device using the lithography mask.