Patent ID: 6205531
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A system for translating virtual addresses to physical addresses, the system comprising:a TLB partitioned as a series of logically grouped TLB segments, each TLB segment associated with a particular use of a system memory and including one or more TLB entries, with each TLB entry including a mapping between a virtual memory page and a physical page address, wherein the particular use of a system memory is selected from the group consisting of frame buffering, texture mapping, color indexing, and linear addressing of memory;means for selecting a TLB segment using a descriptor ID received from a processor; andmeans for locating a TLB entry within the selected TLB segment, the located TLB entry including a mapping between the virtual memory page of a virtual address received from a processor and a corresponding page address.