Patent ID: 8446202
Filing Date: 2013-05-21
Classification: H03F,H04B

Abstract:
1. A power limiting circuit for outputting an input signal by limiting a maximum instantaneous power value of the input signal to a predetermined power value or less, comprising: a maximum value prediction filter section that interpolates one of branched input signals obtained by branching the input signal, which is quantized at a first sampling rate, at a second sampling rate higher than the first sampling rate; a maximum value detection section that outputs a maximum value of the signal interpolated by the maximum value prediction filter section and a time detection position thereof every constant period corresponding to the first sampling rate; a first subtraction section that outputs, as a peak signal, a result obtained by subtracting a preset threshold from the maximum value, the peak signal being 0 (zero) when the subtraction result is negative; a coefficient selection section that weights the peak signal according to the time detection position; a complex filter section that imposes a band limitation on the weighted peak signal output from the coefficient selection section; a filter coefficient calculation section that calculates coefficients of the complex filter section; a delay adjustment section that delays another of the branched input signals by a delay of processing from the maximum value prediction filter section to the complex filter section; and a second subtraction section that subtracts the band-limited peak signal, which is an output of the complex filter section, from the another of the branched input signals which is subjected to delay adjustment by the delay adjustment section.