Patent ID: 6038172
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell transistor having an electrically isolated floating gate electrode varying an on resistance which depends on an amount of charge stored on the floating gate electrode;a bit line connected to said memory cell transistor;a current controlling element connected between said bit line and a first potential;a dummy cell transistor connected between said bit line and a second potential; anda decoder connected to said memory cell transistor and said dummy cell transistor for controlling each of them, the decoder being operative during a first interval to turn said dummy cell transistor on to apply the second potential to said bit line which connected to the first potential via said current controlling element and operative during a second interval to turn said memory cell transistor on to allow the second potential to be applied to said bit line via said memory cell transistor, thereby allowing a write-in current to pass via said memory cell transistor.