Patent ID: 6463488
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A data processing apparatus, comprising:one or more master logic units for accessing a bus in order to generate processing requests; a test controller for testing said master logic units of the data processing apparatus; an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller; in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested; and in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request.