Patent ID: 6813207
Filing Date: 2004-11-02
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of sense amplifiers divided into a plurality of groups, each of the groups being a unit of a page readout operation; a sense amplifier control signal generation circuit which outputs a sense amplifier control signal for enabling the sense amplifiers of each group and disabling the sense amplifiers of each group, wherein the sense amplifier control signal enables and disables the sense amplifiers of a part of the groups at different timing from the sense amplifiers of other group's; and a plurality of memory cells connected to the sense amplifiers via data lines, wherein the sense amplifier control signal generation circuit outputs the sense amplifier control signal so as to enable the sense amplifiers of each group at different timing and disable the sense amplifiers of each group at different timing, wherein a period from enabling the sense amplifiers to disabling them in accordance with the sense amplifier control signal is a time necessary for precharging the data lines connected to the memory cells, determining data read out from the memory cells via the data lines, and latching the data, wherein the sense amplifier control signal generation circuit comprises sense amplifier enable signal generation circuits for every group, and each of the sense amplifier enable signal generation circuits outputs the sense amplifier control signal, wherein each of the sense amplifier enable signal generation circuits comprises: a first generation circuit which generates a data line precharge signal for precharging the data lines in accordance with an inputted trigger signal; a second generation circuit which generates a sense signal for reading out data from the memory cells via the data lines and determining the data in accordance with the data line precharge signal; a third generation circuit which generates a data latch signal for latching the determined data in accordance with the sense signal; and a fourth generation circuit which generates the sense amplifier control signal of an enable state while the data line precharge signal, the sense signal and the data latch signal are outputted.