Patent ID: 6458692
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method of forming contact plugs of a semiconductor device comprising:forming bit lines over a semiconductor substrate in which a predetermined lower layer is formed and a cell area and a core area are defined; forming an interlayer dielectric layer over the semiconductor substrate over which the bit lines are formed; wet etching the interlayer dielectric layer until the interlayer dielectric layer is recessed from the upper surfaces of the bit lines to a predetermined depth; forming a dielectric layer for forming spacers over the semiconductor substrate, the dielectric layer having a step difference formed due to the wet etching of the interlayer dielectric layer; leaving the dielectric layer in the core area and etching the dielectric layer in the cell area by an anisotropic method to form spacers of the dielectric layer in the cell area; etching the interlayer dielectric layer using the spacers and the dielectric layer as a mask to form contact holes; and depositing a conductive layer over the semiconductor substrate where the contact holes are formed to fill the contact holes.