Patent ID: 8117572
Filing Date: 2012-02-14
Classification: G06F

Abstract:
1. A data processing device comprising: a behavioral level description receiving unit that receives input of a behavioral level description describing behavior of an electronic circuit to be mounted on a semiconductor integrated circuit; a synthesis constraint information receiving unit that receives input of synthesis constraint information constituting constraints to be satisfied while generating a register transfer level description based on the behavioral level description, the constraints indicates the type and number of circuit configuration elements that are describable in the register transfer level description; an intermediate level description generating unit that generates an intermediate level description that describes a plurality of processes running on the data processing device and indicated by the behavioral level description and data passed over during the plurality of processes based on the behavioral level description and the received synthesis constraint information; a path information acquiring unit that acquires path information indicating a data path and at least one process executed on the data path based on the intermediate level description; and a synthesis constraint information generating unit that generates new synthesis constraint information that improves prescribed circuit performance of the electronic circuit based on library information specifying circuit configuration elements that are describable in the register transfer level description and the path information.