Patent ID: 8941418
Filing Date: 2015-01-27
Classification: H02H,H03K

Abstract:
1. A driving circuit for driving a load coupled to an output node of the driving circuit, comprising: an output-stage element coupled between an operation voltage source and the output node; a first N-type metal-oxide-semiconductor (NMOS) transistor having a gate, a drain coupled to the output node, and a source coupled to a ground and controlled according to a first driving signal; and a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a drain coupled to the ground, and a source coupled to the output node and controlled according to a control signal, wherein at a first time point, the first driving signal switches from a first high voltage to a first low voltage level, and the control signal is at a second low voltage, and wherein during a time period from the first time point to a second time point which is later than the first time point, the first driving signal remains at the first low voltage level, and the control signal changes from the second low voltage level to a second high voltage level gradually.