Patent ID: 8200912
Filing Date: 2012-06-12
Classification: G06F,Y02D

Abstract:
1. A multi-core device comprising: at least two cores each operable to execute instructions embodied as software stored on a persistent memory means, wherein at least one of said at least two cores is associated with a primary memory of said memory means, said primary memory being random access memory (“RAM”), a first software portion stored in said primary memory to be executed by said at least one of said at least two cores once said first software portion has been transferred from said primary memory along with data associated with said first software portion, and a memory interface interposed between and coupled to said RAM and to at least one of said at least two cores, for allowing said at least one of said at least two cores to execute said first software portion stored in said primary memory and to access the data associated with said first software portion, wherein another one of said at least two cores is associated with a secondary memory that is a part of said memory means and is operable to persistently store software to be executed by each of said at least two cores and wherein said another one of said at least two cores is operable to transfer a software portion stored in the secondary memory to be stored in the primary memory wherein transferring said first software portion to the primary memory is conducted through a first memory interface, a first core, a second core and a second memory interface, in turn.