Patent ID: 9159589
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A method of forming a chip package, comprising: providing a chip with a plurality of first copper post bumps, wherein the plurality of first copper post bumps have a first height of copper post; providing a substrate with a plurality of second copper post bumps, wherein the plurality of second copper post bumps have a second height of copper post; bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package, wherein the first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1.