Patent ID: 8379427
Filing Date: 2013-02-19
Classification: G06F,G11C

Abstract:
1. A semiconductor device comprising: a substrate having a multi-layer structure with a wiring pattern formed therein, and having a substantially rectangular shape in a plan view; a connector provided on a short side of the substrate to be connectable to a host device; a volatile semiconductor memory element provided on a front surface layer side of the substrate; a plurality of nonvolatile semiconductor memory elements provided on the front surface layer side of the substrate; and a controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements, wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, and wherein the plurality of nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the signal line.