Patent ID: 6426562
Filing Date: 2002-07-30
Classification: H01L

Abstract:
A semiconductor device, said semiconductor device comprising:a semiconductor substrate including a plurality of circuits thereon, each circuit of said plurality of circuits connected to a bond pad, a first passivation layer thereon covering said plurality of circuits and having an aperture therethrough at each said bond pad, a plurality of solder wettable conductive traces, each trace of said plurality of solder wettable conductive traces having a portion thereof connected to said bond pad and having said portion thereof located on a portion of said first passivation layer, a second insulative passivation layer comprising a polyamide material covering said plurality of solder wettable conductive traces and said portion of said first passivation layer, said second insulative passivation layer including a plurality of sloped-wall vias therethrough located over said portion of said each of said plurality of solder wettable conductive traces, and a solder material located in each sloped-wall via of said plurality of sloped-wall vias in said second insulative passivation layer, said solder material directly contacting said portion of at least one solder wettable conductive trace of said plurality of solder wettable conductive traces, said at least one sloped wall via of said plurality of sloped-wall vias including: said portion of said at least one solder wettable conductive trace of said plurality of solder wettable conductive traces directly contacting said solder material, said at least one solder wettable conductive trace of said plurality of solder wettable conductive traces in electrical communication with integrated circuitry carried by said semiconductor substrate connected to at least one circuit of said plurality of circuits.