Patent ID: 8330234
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an isolation region formed within a semiconductor substrate; an N-type region and a P-type region formed within the semiconductor substrate such that the N-type region and the P-type region are isolated by the isolation region; a line electrode extending from a region over the N-type region through a region over the isolation region to a region over the P-type region; a PMOS transistor comprising a first gate insulating film formed over the N-type region and a first gate electrode which is the line electrode over the N-type region; and an NMOS transistor comprising a second gate insulating film formed over the P-type region and a second gate electrode which is the line electrode over the P-type region, wherein the line electrode comprises an electrode section (A) comprising the first gate electrode, an electrode section (B) comprising the second gate electrode and a diffusion barrier region formed for preventing contact of the electrode sections (A) and (B) over the isolation region, wherein the diffusion barrier region contains an element different from elements in the electrode sections (A) and (B), and the electrode sections (A) and (B) are made of materials containing mutually different elements or of materials containing the same elements in a different composition, wherein the diffusion barrier region meets the following conditions (1) and (2): (1) a diffusion coefficient D (2) a diffusion coefficient D wherein the electrode sections (A) and (B) as well as the diffusion barrier region are made of a silicide, and wherein the silicide constituting the diffusion barrier region is a silicide containing a metal element which becomes a diffusing species to silicon during a siliciding reaction.