Patent ID: 6475860
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A method for manufacturing a ferroelectric random access memory (FeRAM) device, the method comprising the steps of:a) preparing a substrate on which a first insulating layer is formed; b) forming a ferroelectric capacitor structure comprising a buffer formed on the first insulating layer, a bottom electrode formed on the buffer, a capacitor thin film formed on the bottom electrode, and a top electrode formed on the capacitor thin film; c) forming a second insulating layer on the top electrode, the capacitor thin film and the first insulating layer; d) forming a photoresist pattern on the second insulating layer that exposes a first portion of the second insulating layer above the top electrode and exposes a second portion of the second insulating layer above the bottom electrode; e) etching the first portion of the second insulating layer with a first set of etch parameters to expose a portion of the top electrode, thereby forming a storage node contact hole and etching the second portion of the second insulating layer to expose a portion of the capacitor thin film; f) etching the exposed portion of the capacitor thin film with a second set of etch parameters to form a cell plate contact hole, wherein the second set of etch parameters is different from the first set of etch parameters; and g) forming a metal interconnection pattern over the second insulating layer and into the storage node contact hole and the cell plate contact hole.