Patent ID: 8015364
Filing Date: 2011-09-06
Classification: G06F,Y02D

Abstract:
1. A snoop filter apparatus associated with a single processing unit of a computing environment having multiple processing units, each processing unit having one or more cache memories associated therewith, said snoop filter apparatus comprising: a first scoreboard data structure having bit locations for tracking data that have been loaded into a cache memory of its associated processing unit in response to a cache miss; means for setting said bit locations in said first scoreboard data structure to indicate possibility of data located in said cache memory at a particular address; means for receiving snoop requests from one or more memory writing sources and decoding an address of the received snoop request; means for comparing said decoded address against corresponding bits set in said first scoreboard data structure; means for forwarding said received snoop request to said processor in response to matching of a bit set in said first scoreboard data structure, or otherwise discarding said snoop request; a cache wrap detection means for tracking whether every cache line has been overwritten with new cache line content in said cache memory since a prior detected cache wrap condition; and, a second scoreboard data structure having corresponding bit locations as said first scoreboard data structure, said second scoreboard data structure receiving a copy of content from said first scoreboard data structure upon detection of a cache wrap condition indicating all cache lines have been overwritten with new cache line content.