Patent ID: 8946851
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A power transistor comprising: a doped substrate comprising a source and a channel region within a first doped region, a drain, a fill region, a transition region, and a trench within a second doped region, wherein the trench is formed in a first surface of the substrate and the trench is filled with insulating material, further wherein the fill region is positioned adjacent to the trench, the channel region is positioned between the source and the transition region, the transition region is positioned between the channel region and the fill region, and the trench is positioned between the fill region and the drain, the fill region having a fill region depth and the trench having a trench depth, wherein the fill region depth is less than the trench region depth; a gate oxide layer positioned on the first surface of the substrate; a gate positioned on the gate oxide layer and over the channel region and the transition region; and a field plate positioned entirely over the trench, wherein the gate is separated from the field plate by a gap positioned over the fill region, further wherein the field plate is electrically coupled to the source via a conductive trace.