Patent ID: 9035468
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A device, comprising: a semiconductor substrate; a metal pad on the semiconductor substrate; a first polymer insulating layer overlying the semiconductor substrate and covering a portion of the metal pad; a monolithic copper-containing structure over the metal pad and the first polymer insulating layer, and electrically connected to the metal pad, the monolithic copper-containing structure comprising: a via portion contacting the metal pad embedded in the first polymer insulating layer; a bottom portion having a first thickness and a first width, wherein the bottom portion comprises a post-passivation interconnect (PPI) line; and a top portion adjoining the bottom portion and having a second thickness and a second width, the monolithic copper-containing structure having an undercut structure between the top portion and the bottom portion, wherein the second thickness is greater than the first thickness, and the first width is greater than the second width; and a conductive bump over the top portion of the monolithic copper-containing structure.