Patent ID: 6996659
Filing Date: 2006-02-07
Classification: G06F

Abstract:
1. An apparatus comprising: a plurality of first sequencers each configured to translate attributes and data between a first predetermined format and a second predetermined format; a plurality of second sequencers each configured to translate attributes and data between a third predetermined format and said second predetermined format; a logic circuit configured to route said attributes and data in said second predetermined format from one of said first and said second sequencers to another of said first and said second sequencers; a plurality of first memories, each (i) coupled between one of the first and second sequencers and said logic circuit and (ii) configured to store the attributes of one or more completed transactions of the sequencer to which the first memory is coupled; and a plurality of second memories, each (i) coupled between one of the first and second sequencers and said logic circuit and (ii) configured to store the attributes of one or more pending transactions of the sequencer to which the second memory is coupled.