Patent ID: 7721039
Filing Date: 2010-05-18
Classification: G06F

Abstract:
1. A system bus control apparatus comprising: a system bus that is a path of data transferred from a bus master; a bus condition monitoring section that monitors a used condition or unused condition of the system bus; a bus allocating section that allocates a bus width permitted to be transferred by the bus master based on the used condition or unused condition of the system bus monitored by the bus condition monitoring section, when the bus master issues a transfer request; and a bus width variable section that changes the bus width of the data transferred from the bus master in accordance with the allocated bus width, wherein the bus width variable section has a function of dividing the data from the bus master in accordance with the allocated bus width when the bus width of the data requested to be transferred by the bus master is greater than the bus width allocated by the bus allocating section, and of combining the data from the bus master in accordance with the allocated bus width when the bus width of the data requested to be transferred by the bus master is smaller than the bus width allocated by the bus allocating section.