Patent ID: 6674105
Filing Date: 2004-01-06
Classification: H01L,Y10S

Abstract:
A static random access memory including:a first n-channel MOS field effect transistor being connected in series between a first node and a ground line and said first n-channel MOS field effect transistor having a gate connected to a second node, and said first node having a voltage supplied by only said ground line or a first bit line; a second n-channel MOS field effect transistor being connected in series between a second node and the ground line and said second n-channel MOS field effect transistor having a gate connected to the first node, and said second node having a voltage supplied by only said ground line or a second bit line; a first p-channel MOS field effect being connected in series between the first node and said first bit line and said first p-channel MOS field effect transistor having a gate connected to a word line; and a second p-channel MOS field effect being connected in series between the second node and said second bit line adjacent to said first bit line and said second p-channel MOS field effect transistor having a gate connected to said word line, wherein said first and second n-channel MOS field effect transistors have gate insulation films that are thicker than gate insulation films of said first and second p-channel MOS field effect transistors to suppress a leakage of gate tunneling current and wherein said gates of said first and second n-channel MOS field effect transistors are doped with an n-type impurity and said gates of said first and second p-channel MOS field effect transistors are doped with an p-type impurity.