Patent ID: 8665405
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A thin film transistor array panel, comprising: an insulating substrate; a plurality of pixel electrodes arranged on the insulating substrate in rows extending in a row direction, and columns extending in a column direction; a plurality of thin film transistors connected with the plurality of pixel electrodes, respectively; and a plurality of gate lines, and one data line connected with the plurality of thin film transistors, wherein two first thin film transistors among the plurality of thin film transistors connected with the one data line, in two first adjacent rows, are connected to two first pixel electrodes in a first column, two second thin film transistors among the plurality of thin film transistors connected with the one data line, in two second adjacent rows adjacent to the two first adjacent rows, are connected to two second pixel electrodes in a second column adjacent to the first column, the two first thin film transistors and the two second thin film transistors connected with the one data line, are repeated in the column direction, and two boundary lines opposite to each other in the column direction, of the two first pixel electrodes in the first column and the two second pixel electrodes in the second column, are overlapped with the one data line.