Patent ID: 6069831
Filing Date: 2000-05-30
Classification: G11C

Abstract:
A semiconductor read-only memory, comprising:a main memory cell array having a plurality of memory cells for storing data, the memory cell array comprising a plurality of main bit lines for transferring data into and out of the main memory cell array;a dummy cell array for generating dummy cell data, said dummy cell data including a reference potential for comparison to data stored in a cell of the main memory cell array;a sense amplifier circuit having a sense input and a reference input, said sense amplifier circuit comparing data on the sense input from a memory cell to dummy cell data from a dummy cell, said dummy cell data being received on the reference input of the sense amplifier circuit; anda selection circuit for coupling the dummy cell to one of the main bit lines of the main memory cell array, said first main bit line being coupled to the reference input of the sense amplifier circuit.