Patent ID: 9166012
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor substrate including a first trench that defines active regions in a first region and a second trench in a second region around the first region; a gate electrode on the first region that crosses the active regions; a data storing pattern that is between the gate electrode and the active regions; a blocking insulating layer that is between the gate electrode and the data storing pattern and that extends over the first trench to define a first air gap in the first trench; and an insulating pattern that is spaced apart from a bottom surface of the second trench to define a second air gap in the second trench; wherein the first and second trenches have substantially a same depth, wherein the first air gap includes a first vertical height and the second air gap includes a second vertical height, and wherein the first vertical height is greater than the second vertical height.