Patent ID: 8102196
Filing Date: 2012-01-24
Classification: G06F,H03L

Abstract:
1. An apparatus including integrated clock signal generator circuitry, comprising: a first electrode to convey an off-chip control signal for off-chip voltage-controlled oscillator (VCO) circuitry; a second electrode to convey from said off-chip VCO circuitry an off-chip VCO signal having a first frequency related to said off-chip control signal; first phase detection circuitry coupled to said first and second electrodes and responsive to an input reference signal and a phase lock loop (PLL) signal by providing said off-chip control signal; frequency alteration circuitry coupled to said second electrode and responsive to said off-chip VCO signal by providing an intermediate signal having a second frequency related to said first frequency; and PLL circuitry coupled to said frequency alteration circuitry and responsive to said intermediate signal by providing said PLL signal, wherein said PLL signal has a third frequency related to said second frequency and is synchronized with said input reference signal.