Patent ID: 6232625
Filing Date: 2001-05-15
Classification: H01L,H02H

Abstract:
A semiconductor configuration, comprising:a first semiconductor region having a first surface and at least one contact region disposed at said first surface;at least one second semiconductor region forming a first p-n junction with said first semiconductor region and said first p-n junction having a depletion zone;at least one third semiconductor region disposed at said first surface of said first semiconductor region forming a second p-n junction with said first semiconductor region and said second p-n junction having a depletion zone, said at least one third semiconductor region having a second surface not adjoining said first semiconductor region;a first electrode making contact with both said at least one contact region of said first semiconductor region and with said at least one third semiconductor region at said second surface; anda second electrode making contact with said first semiconductor region, said first semiconductor region having at least one channel region lying in a current path between said first electrode and said second electrode, said at least one said channel region being pinched off by said depletion zone of said first p-n junction and said depletion zone of said second p-n junction if a predetermined saturation current is reached between said first electrode and said second electrode, after which a current is limited to a limit current below the predetermined saturation current.