Patent ID: 6158025
Filing Date: 2000-12-05
Classification: G06F,G11C

Abstract:
A system for detecting and reporting bit errors in error correcting code memory in a computer system, the system comprising:error correcting code memory;a motherboard having two or more memory interface slots, the error correcting code memory situated in at least one slot, each memory interface slot having a memory interface slot number;a chipset coupled to the motherboard, the error correcting code memory, in conjunction with the chipset for creating an error detection signal when a bit error is corrected by the chipset, the chipset having at least one register which receives the error detection signal and stores the error detection signal in the at least one register creating a register signal; anda driver coupled to the chipset for reading the register signal in the at least one register, calculating and reporting the memory interface slot number of the error correcting code memory based at least on the register signal.