Patent ID: 9052360
Filing Date: 2015-06-09
Classification: G01R

Abstract:
1. An integrated circuit containing a test circuit, the test circuit comprising: an oscillator having an oscillator output node; a calibration divider circuit having a calibration divider input node and a calibration divider output node, such that said calibration divider input node is connected to said oscillator output node; a starter divider circuit having a starter divider input node and a starter divider output node, such that said starter divider input node is connected to said oscillator output node; a test gate chain containing a number, N a reference gate chain containing a number, N a start/stop decoder circuit including a test input, a reference input, a start output and a stop output, wherein said test input is connected to said test gate chain output of, wherein said reference input is connected to said reference gate chain output; and a counter circuit including a start input, a stop input, a clock input and a plurality of count outputs, wherein said start input is connected to said start output of said start/stop decoder circuit, said stop input is connected to said stop output of said start/stop decoder circuit, said clock input is connected to said oscillator output node.