Patent ID: 8441277
Filing Date: 2013-05-14
Classification: G01R

Abstract:
1. A semiconductor device comprising: a test unit having a plurality of semiconductor test apparatuses, wherein each semiconductor test apparatus comprises: a flip-flop provided with a first input terminal, a second input terminal, a mode terminal configured to accept a mode signal that indicates either a first mode or a second mode, a clock terminal configured to accept a clock signal, and an output terminal; said flip-flop being configured to select said first input terminal when said mode signal indicates said first mode, select said second input terminal when said mode signal indicates said second mode, and hold information that is being received by the input terminal that was selected based on said mode signal in synchronization with said clock signal and supply said information from said output terminal; and wherein each semiconductor test apparatus further comprises a hold unit configured to hold a set value and provide the set value to said first input terminal; wherein the second input terminal of each semiconductor test apparatus being connected to an output terminal in a test-object logic circuit corresponding to the second input terminal, and the output terminal of each semiconductor test apparatus being connected to an input terminal in the test-object logic circuit corresponding to the output terminal; and a memory unit configured to store information for comparison; and a comparison-determination unit configured to compare information for comparison stored in said memory unit with output from each output terminal in said test unit and configured to supply the result of the comparison as output.