Patent ID: 8673688
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor package, the method comprising: forming a circuit substrate including a base substrate, a substrate connection terminal on the base substrate, and a substrate insulation layer covering the base substrate and exposing the substrate connection terminal; forming a mixture layer on the circuit substrate, the mixture layer including an adhesive resin and a plurality of solder particles; providing a first semiconductor chip on the mixture layer, the first semiconductor chip including a chip connection terminal and a chip insulation layer exposing the chip connection terminal; forming an inner solder ball between the substrate connection terminal and the chip connection terminal; and forming a dummy solder in a dummy opening, the dummy opening being in one of the substrate insulation layer and the chip insulation layer, the dummy solder configured to be physically spaced apart from one of the circuit substrate and the first semiconductor chip.