Patent ID: 6033948
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A method for manufacturing the high voltage MOSFET, comprising a process forming the first and second conductive wells in a semiconductor substrate; process forming drift areas in the said first and second conductive wells; process growing an isolation membrane on the substrate surface between the said first and second conductive wells; process forming a gate insulation film; process forming a gate on the gate insulation film above the said first and second conductive wells; process forming low concentration n-and p-type dopant areas in the drift areas of the part adjacent to the said gate; process forming a buried diffusion area in the said first and second conductive wells; process forming source/drain having a body contact on a side on the buried diffusion area in the said first and second conductive wells; process forming the insulation film having a contact formed in such way that the source/drain surface is exposed, on the entire surface of the substrate including the said gate and isolation membrane; process forming a metal film on the said insulation film; and process forming source/drain electrodes and metal field plates by etching the said metal film using a mask.