Patent ID: 7282401
Filing Date: 2007-10-16
Classification: H01L

Abstract:
1. A method for use in fabrication of a semiconductor device, comprising: forming a dielectric vertical spacing layer over a semiconductor wafer; etching the dielectric vertical spacing layer and the semiconductor wafer to form a trench in the semiconductor wafer; forming a gate oxide layer within the trench over a surface of the semiconductor wafer; forming a conductive transistor gate layer on the gate oxide layer and over the vertical spacing layer; etching the conductive transistor gate layer to at least expose the dielectric vertical spacing layer, to pattern the conductive transistor gate layer, and to form first and second vertically oriented sidewalls from the conductive transistor gate layer; forming a dielectric spacer layer on the first and second vertically oriented sidewalls of the conductive transistor gate layer and over a horizontally oriented surface of the vertical spacing layer; and etching the dielectric spacer layer and the dielectric vertical spacing layer to form a first spacer along the first vertically oriented sidewall of the conductive transistor gate layer and a second spacer along the second vertically oriented sidewall of the conductive transistor gate layer wherein a vertical surface of the dielectric vertical spacing layer remains exposed.