Patent ID: 6728797
Filing Date: 2004-04-27
Classification: G06F

Abstract:
A DMA controller comprising:a cycle register to which a number of data transfer cycles to be performed in response to a single DMA transfer request is written; a cycle counter for counting a number of data transfer cycles actually performed; a transfer counter to which a number of DMA transfer requests made is written; an arbitration circuit that, on receiving a DMA transfer request, requests access to an external system bus and that, if permitted access to the external system bus, issues a DMA transfer start command; and a sequencer that controls DMA transfer according to instructions from the arbitration circuit, wherein when the sequencer is permitted DMA transfer while the sequencer is in a state waiting for a DMA transfer permission, the sequencer updates the value held in the cycle counter with the value held in the cycle register and then enters into a state waiting for a DMA transfer start command, when a DMA transfer start command is issued while the sequencer is in the state waiting for a DMA transfer start command, the sequencer starts data transfer, thereafter the sequencer continues data transfer, while updating the value held in the cycle counter every time a data transfer cycle is performed, until the cycle counter enters into a predetermined state, and when the cycle counter enters into the predetermined state, the sequencer updates the value held in the transfer counter so that, as a result if the transfer counter enters into a predetermined state, the sequencer enters into the state waiting for a DMA transfer permission and, if the transfer counter does not enter into the predetermined state, the sequencer updates the value held in the cycle counter with the value held in the cycle register and enters into the state waiting for a DMA transfer start command.