Patent ID: 6751749
Filing Date: 2004-06-15
Classification: G06F

Abstract:
A method for multiprocessing comprising the steps of:a) computing results by a first processor responsive to instructions having a certain instruction sequence, wherein the processor has first register for storing one of the processor's results, and wherein the first register is associated with a first stack of shadow registers with at least a top shadow register and a next shadow register; b) computing results by a second processor responsive to the instructions, wherein the second processor has a second resister for storing one of the second processor's results, and wherein the second register is associated with a second stack of shadow registers with at least a top shadow register and a next shadow register, wherein the first and second processors compute first and second results and store the results in the first and second registers, respectively; c) shifting the first result from the first register into the first register's top shadow register responsive to a checkpoint, wherein the first result that is shifted into the first register's top shadow register is for a first sequence ending instruction at the end of a first sequence of the instructions; d) shifting the second result from the second register into the second register's top shadow register responsive to the checkpoint, wherein the second result that is shifted into the second reaister's ton shadow register is for a second sequence ending instruction at the end of a second sequence of the instructions, the first and second sequence ending instructions being a same one instruction wherein the checkpoint arises in correspondence with the first and second sequence ending instructions; e) checking for matching of cumulative results for the first sequence of the instructions and the second second sequence of the instructions, wherein the checking is responsive to the checkpoint, wherein the first and second results are shifted to the next shadow registers of the respective first and second registers responsive to a match indication from the checking; and f) computing respective results by the first and second processors for at least one of the instructions subsequent to the sequence ending instruction, wherein the shifting of the results permits the computing of step f) to proceed concurrently with the checking in step e).