Patent ID: 6281826
Filing Date: 2001-08-28
Classification: G09G,H03M

Abstract:
A D/A converter comprising:a plurality of conversion capacitors having capacitance values defined by factors depending on input bits, each of the conversion capacitors having a first end and a second end;a coupling capacitor having a first end and a second end; anda plurality of switches having a common node and disposed between the second end of each of the conversion capacitors and the second end of said coupling capacitor, each of the switches being opened or closed in accordance with said input bits;wherein an analog voltage corresponding to a digital input value is obtained between the second end of said coupling capacitor and the common node of said switches, such that the designed capacitance values of said plurality of conversion capacitors satisfies equation (1) described below:Coj-dCj>.SIGMA..sub.(i<j) (Coi+dCi) (for all j) (1)whereCi: ith conversion capacitance,Coi: designed value of the ith conversion capacitance,dCi: dispersion of the ith conversion capacitance,Cj: jth conversion capacitance,Coj: designed value of the jth conversion capacitance,dCj: dispersion of the jth conversion capacitance,.SIGMA..sub.(i<j) : sum for all i smaller than j, andfor all j: indicating that the equation should be satisfied for all j.