Patent ID: 6792109
Filing Date: 2004-09-14
Classification: H04L

Abstract:
A bit generator composed of an electronic circuit comprising:an input to which an input signal is applied comprising a group of n reference system bits, where n is an integer equal to at least 1, an output on which an output signal is produced composed of a group of n measurement bits, a memory with n memorization cells each memorizing k bits, where k is an integer equal to at least 2, with reference system bits and measurement bits, each cell thus being in a logical state defined by its k bits, this state not being readable from outside the electronic circuit, this memory being connected to the output (S) of the generator and outputting measurement bits from the n. cells, calculation means for provoking a transition for each cell in said memory, said calculation means being connected to said memory arid having a control input connected to said input of said bit generator into which reference system bits are input, wherein said calculation means is configured -to provoke a random transition for each cell between an initial state read on reception of the reference system bit corresponding to the cell and a final state, the probability of this transition depending on the initial state, the received reference system bit and pre-determined probability equations defined in the calculation means, said bit generator is configured to generate a secret encryption key, and said bit generator is configured to decipher a received secret encryption key.