Patent ID: 6370615
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A method for accelerating access to data on a network having at least one computer using an n-bit architecture and at least one computer using an m-bit architecture, where m and n are unequal integers, said method comprising:creating caches in RAMs of a plurality of the computers connected to the network including at least one of the n-bit architecture computers and at least one of the m-bit architecture computers, each cache being associated with an I/O device connected to the network; receiving, from an application, a write instruction to a given one of the I/O devices connected to the network; sending the write instruction to the given I/O device; communicating over the network to invalidate data in any caches on the network associated with the given I/O device; and sending a write I/O completion signal to the application after completing the invalidation of data in the step of communicating over the network.