Patent ID: 7863139
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A method of fabricating a double gate field effect transistor structure comprising the following steps performed in any convenient order: providing a single crystal silicon substrate; epitaxially growing a lower gate layer of single crystal rare earth electrically conductive silicide material on the silicon substrate; epitaxially growing a lower gate electrically insulating layer of single crystal rare earth electrically insulating material on the lower gate layer of single crystal rare earth electrically conductive silicide material; epitaxially growing an active layer of single crystal semiconductor material on the lower gate layer of single crystal rare earth electrically insulating material; epitaxially growing an upper gate insulating layer of single crystal rare earth electrically insulating material on the active layer of single crystal semiconductor material; epitaxially growing an upper gate layer of single crystal rare earth electrically conductive material on the upper gate electrically insulating layer; etching the upper gate layer and the upper gate electrically insulating layer and depositing a metal contact on the upper gate layer to define an upper gate structure; implanting an impurity into the lower gate layer of single crystal rare earth electrically conductive silicide material to define a lower gate area aligned with the upper gate structure; forming a source area and drain area in the active layer; and depositing metal source and drain contacts on the source area and drain area, respectively.