Patent ID: 8089493
Filing Date: 2012-01-03
Classification: G06T

Abstract:
1. An image processing circuit comprising: a storage unit that stores positions of respective pixels, and pixel values of the pixels, the pixels forming a plurality of shape-images which are to be laid out in an array; a first multiplication unit that multiplies a pixel value from among the pixel values stored in the storage unit, by a pixel value from among pixel values included in input image data, for each of the respectively corresponding positions to both the positions stored and positions of pixels included in the input image data, the input image data expressing the pixel values; a subtraction value output unit that outputs a pixel value which is obtained by subtracting a pixel value at each of the positions in the input image data, from a maximum pixel value in the input image data; a second multiplication unit that multiplies a pixel value from among the pixel values included in the input image data or a pixel value included in background image data, by the pixel value output from the subtraction value output unit, for each of the respectively corresponding positions, the background image data being a background of an image based on the input image data; and an adder unit that adds up a multiplication result of the first multiplication unit and a multiplication result of the second multiplication unit, for each of the respectively corresponding positions, and outputs addition results as output image data.