Patent ID: 6721206
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A method of reading a floating-gate memory cell, comprising:applying a first potential to a control gate of the floating-gate memory cell, wherein the first potential is greater than a threshold voltage of the memory cell in a first programmed state and less than a threshold voltage of the memory cell in a second programmed state, wherein the floating-gate memory cell has a drain region and a source region in a first well region having a first conductivity type, and wherein the first well region is in a second well region having a second conductivity type different from the first conductivity type; applying a second potential to the second well region, wherein the second well region is coupled to the source region; applying a precharge potential to a bit line coupled to the drain region; and sensing a current between the drain region and the source region after isolating the bit line from the precharge potential and while the second potential is applied to the second well region, wherein a level of the current is indicative of the programmed state of the memory cell.