Patent ID: 9140864
Filing Date: 2015-09-22
Classification: G02B

Abstract:
1. A method of coupling light into a power semiconductor device having a semiconductor structure with two or more layers, including multiple cells of identical units, and having a patterned electrode layer that is disposed on the surface of the semiconductor structure, comprising: illuminating the power semiconductor device by directing a light from a light source through the aperture openings in the patterned electrode layer to form an enhanced light coupling with the semiconductor structure, wherein the patterned electrode layer is configured to have a micron scaled grid pattern having multiple metal grids and aperture openings based on a distributed resistance model having characteristic current decay lengths for the metal grids and the aperture openings, wherein the width of the metal grids is configured according to λ wherein the aperture openings between the metal grids are configured according to λ where λ