Patent ID: 6680625
Filing Date: 2004-01-20
Classification: H03K

Abstract:
A system for providing a selected logical function, the system comprising:a first differential transistor pair, having first and second drains connected across respective first and second selected resistors to a reference voltage source; a second differential transistor pair, having third and fourth drains connected across the respective first and second selected resistors to the reference voltage source; a third differential transistor pair, having fifth and sixth drains connected across the respective second and first selected resistors to a reference voltage source; a fourth differential transistor pair, having seventh and eighth drains connected across the respective first and second selected resistors to a reference voltage source; a fifth differential transistor pair, having ninth and tenth drains connected to a common source of the first differential pair and the second differential pair, respectively; a sixth differential transistor pair, having eleventh and twelfth drains connected to a common source of the third differential pair and the fourth differential pair, respectively; a seventh differential transistor pair, having thirteenth and fourteenth drains connected to a common source of the fifth differential pair and the sixth differential pair, respectively; first and second input terminals, connected to respective first and second gates of the first differential pair, and to respective first and second gates of the sixth differential pair; third and fourth input terminals, connected to respective first and second gates of the fourth differential pair, and to respective first and second gates of the fifth differential pair; a fifth grounded input voltage source, connected across a third resistor to a first gate of the second differential pair and to a second gate of the third differential pair and connected to a common source of the seventh differential pair; a fourth resistor connecting the second gate of the second differential pair and the first gate of the third differential pair to the first gate of the second differential pair; a sixth selected input voltage source, connected to the first and second gates of the seventh differential pair; and first and second output terminals, connected to the first and second drains of at least one of the first differential pair, the second differential pair, the third differential pair and the fourth differential pair, whereby a difference of first and second output terminal voltages provides at least one of the logical functions AND, NAND, OR and NOR in response to receipt of a first selected voltage difference at the first and second input terminals and to receipt of a second selected voltage difference at the third and fourth input terminals.