Patent ID: 8699286
Filing Date: 2014-04-15
Classification: G11C,H03L

Abstract:
1. A semiconductor device comprising a delay circuit that comprises: a first delay unit that includes a plurality of differential first delay elements which are respectively connected in series, a plurality pairs of first contacts which are respectively provided between said plurality of first delay elements, and a first output circuit that outputs a first delayed signal corresponding to a pair of first contacts selected from among said plurality pairs of first contacts on receiving a first selection signal; a second delay unit that receives said first delayed signal, and that includes a plurality of single-ended second delay elements which are respectively connected in series, a plurality of second contacts which are respectively provided between said plurality of second delay elements, and a second output circuit that outputs a second delayed signal corresponding to a second contact selected from among said plurality of second contacts on receiving a second selection signal; and a control circuit that outputs each of said first and second selection signals, wherein each of said plurality of first delay elements is a delay element of differential input and differential output type, which receives a pair of differential signals, amplifies a potential difference between said pair of differential signals, and outputs a pair of differential signals that are delayed, and wherein each of said plurality of second delay elements is a delay element of single-ended input and single-ended output type, which receives a single-ended signal, determines a logic level of said single-ended signal, and outputs a delayed single-ended signal.