Patent ID: 6307860
Filing Date: 2001-10-23
Classification: H04L,H04Q

Abstract:
A network processor system comprising:a circuit C1 for receiving network data units flowing sequentially between a network port and a network switch, writing the network data units into a first queue, and for generating requests to process the data units, wherein each data unit has first address information specifying the data unit's destination;a first circuit operable to execute computer instructions to (i) receive said requests, (ii) read portions of the data units corresponding to the requests, (iii) determine based on said portions whether and how the data units are to be transformed, (iv) generate commands specifying how the data units are to be transformed, and (v) write the commands to a memory, wherein the first circuit is programmable with said computer instructions to read at least portions of the first address information from the data units, to determine second address information, and generate commands specifying that the second address information is to be supplied for the data units when the data units are transferred to the network port or the network switch; anda second circuit for reading the commands from the memory and executing the commands to transfer the data units to the network port or the network switch, wherein the memory is operable to contain a plurality of commands which have been written to the memory by the first circuit but have not yet been executed by the second circuit;wherein the circuit C1 is operable to write a data unit into the first queue in parallel with the first circuit executing said computer instructions and in parallel with the second circuit executing said commands.