Patent ID: 6559548
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A wiring structure of a semiconductor device comprising:a first insulating layer disposed on or above a substrate and having a relative dielectric constant of 3.0 or less, and a Young's modulus of less than 50 GPa, the first insulating layer including a first recess formed in a surface of the first insulating layer and a first via hole formed therein; a wiring layer and a first via plug disposed in the first recess and the first via hole, respectively; a second insulating layer disposed on or above the first insulating layer and having a Young's modulus of 50 GPa or more, the second insulating layer including a second recess formed in a surface of the second insulating layer and a second via hole formed therein, the second recess and the second via hole being connected to each other at a second connecting portion disposed in the second insulating layer, the second recess having a width larger than that of the second via hole at the second connecting portion in a cross section; and an electrode pad and a second via plug disposed in the second recess and the second via hole, respectively, the electrode pad and the wiring layer being electrically connected to each other by the second via plug, the electrode pad being arranged to be electrically connected to a connecting member by bonding with applied pressure.