Patent ID: 8103938
Filing Date: 2012-01-24
Classification: G06F,G11C

Abstract:
1. A memory system, comprising: an array of re-programmable, non-volatile EEPROM memory cells, wherein digital data are stored in individual memory cells as an analog value in one of a plurality of defined non-overlapping ranges of analog values, a controller operably connected with the memory cell array to perform specified functions that include: storing an error correction code that is generated from the digital data that are stored, reading the stored digital data from the individual memory cells by identifying the one of the plurality of the defined ranges in which the analog level lies, concurrently reading data from the individual memory cells that are representative of a position of the analog value within the identified one of the plurality of the defined ranges, whereby the position data are an indication of the quality of the stored digital data read from the individual memory cells, and correcting errors in the read digital data by utilizing both the error correction code and the read quality indication.