Patent ID: 7876619
Filing Date: 2011-01-25
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of memory cells holding data and arranged in an array; a plurality of bit lines to which a write voltage for executing a write of the data to the memory cells is applied; a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage, the write circuit configured to supply the write voltage to the bit lines; and a write state machine controlling the first voltage and the second voltage, the first voltage being changed from a first value to a second value that is lower than the first value on writing data to the memory cells, the second voltage being changed from the second value to a third value that is lower than the second value when writing data to the memory cells, and the write state machine being configured to control the first voltage and the second voltage to lower the second voltage to an intermediate value between the second value and the third value and, while maintaining this intermediate value for a certain time, lower the first voltage from the first value to the second value.