Patent ID: 6133958
Filing Date: 2000-10-17
Classification: H04J

Abstract:
An arrangement for desynchronizing video signals transported in virtual containers in frames and received from a synchronous network, each virtual container being identified within a said frame by a pointer introduced by the synchronous transport process, the arrangement comprising means for demapping input video information from said frames so as to recover video information bytes, a phase locked control loop system having a bandwidth sufficiently narrow to effectively ignore phase noise created by the pointers and incorporating a first-in-first-out (FIFO) buffer store into which the demapped video information bytes are written, said store having a first write input for storing the demapped information at the rate at which that information is demapped, a second read input and an output, an amplifier coupled to the output of the buffer store, a voltage controlled oscillator having an output and having a control input coupled to the output of the amplifier via a transfer function circuit and said output controlling via a feedback path incorporating an integrator to said read input of said buffer store the rate at which stored video information is read from the buffer store such that the rate of information flow around the feedback control loop is substantially uniform, said oscillator being arranged to provide a video line clock from the read video information, and wherein the fill depth of the FIFO buffer store, provides an error reference for the voltage controlled oscillator frequency so as to increase or decrease that frequency as said fill depth increases or decreases respectively.