Patent ID: 6566910
Filing Date: 2003-05-20
Classification: H03K

Abstract:
An input buffer comprising:a first inverter, wherein the first inverter is associated with a first switching threshold value; a second inverter, wherein the second inverter is associated with a second switching threshold value, the second switching threshold value different from the first switching threshold value; a tri-state inverter; a third inverter, wherein the first inverter, the second inverter, the third inverter and the tri-state inverter are implemented utilizing CMOS (â€œComplimentary Metal Oxide Semiconductorâ€ ) technology, wherein the first inverter and the second inverter receive an input signal, an output of the first inverter is coupled to a first input of the tri-state inverter, an output of the second inverter is coupled to a second input of the tri-state inverter and an output of the tri-state inverter is coupled to an input of the third inverter, the third inverter generating an output of the input buffer.