Patent ID: 6094704
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A pipelined address path for a memory device receiving a signal including a first address comprising:a first address capture circuit adapted to capture the first address, the first address capture circuit having a first expected address capture interval;a first address latch having a first latch input coupled to the first address capture circuit, a first latch control input, and a first address output, the first address latch being responsive to a first latch signal at the first latch control input to latch the first address from the first address capture circuit;a first address decoder having a first address input coupled to the first address output and a decoder output adapted for coupling to a memory bank; anda timing control circuit having a first timing signal output coupled to the first latch control input and a timing input adapted to receive the signal including the first address, the timing control circuit being responsive to the signal including the first address to produce the first latch signal after the first expected address capture interval.