Patent ID: 9223543
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A circuit comprising: one or more processors operable to: receive floating-point type object data to which a sign, which represents a negative or positive value, is to be added and condition data comprising a condition based on which the sign is added; extract the condition included in the condition data; generate sign data for adding the sign to the floating-point type object data based on the extracted condition; align positions of the sign in the sign data and a sign in the floating-point type object data with each other when the condition data and the floating-point type object data have different bit lengths; and perform an integer arithmetic operation while the floating-point type object data is being treated as integer-type data to add the sign in the sign data to the floating-point type object data based on the sign data, wherein the positions of the sign in the sign data and the sign in the floating-point type object data are aligned with each other by shifting a sign bit extracted from the condition data, and wherein a number of bits by which the sign bit is shifted is based on a bit length of the condition data and a bit length of the floating-point type object data, wherein the one or more processors perform inverse quantization when decoding Moving Pictures Experts Group (MPEG) 1 audio layer