Patent ID: 7495959
Filing Date: 2009-02-24
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a memory cell array comprising a plurality of memory blocks, each memory block including a plurality of cell strings, where each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor connected in series between the first and second selection transistors; and a voltage controller which applies a first selection voltage to first selection lines connected to the first selection transistors, a second selection voltage to second selection lines connected to the second selection transistors, and a word line voltage to word lines connected to the memory cell transistors, in response to a plurality of block selection signals corresponding to the memory blocks, wherein the voltage controller precharges the second selection lines to the second selection voltage, regardless of a state of the block selection signals, in a standby state.