Patent ID: 6721198
Filing Date: 2004-04-13
Classification: G11C

Abstract:
A nonvolatile ferroelectric memory device comprising:a plurality of sense amplifiers; a top cell array unit disposed at an upper section, and a bottom cell array unit disposed at a lower section, the top and bottom cell array units each including a plurality of unit cells, and the top and bottom cell array units being disposed symmetrically about the sense amplifiers; at least one top reference array unit in a vicinity of the top cell array unit, and at least one bottom reference array unit in a vicinity of the bottom cell array unit; a plurality of main bit lines connected to the unit cells of the top or bottom cell array unit; and a plurality of reference bit lines of the bottom or top cell array unit, wherein reference bit lines of the bottom cell array unit correspond to main bit lines of the top cell array unit disposed symmetrically about the sense amplifiers, and reference bit lines of the top cell array unit correspond to main bit lines of the bottom cell array unit disposed symmetrically about the sense amplifiers.