Patent ID: 7092404
Filing Date: 2006-08-15
Classification: H04L

Abstract:
1. An interposer chip, having a first side and a second side, the first side having Unilink ports and the second side having DASL ports, the chip comprising: means for translating data divided into a plurality of data cells from DASL protocol received at DASL ports into Unilink protocol at Unilink ports, and translating data from Unilink protocol received at Unilink ports to DASL protocol at DASL ports, data received in DASL and Unilink protocols being a plurality of data cells in corresponding protocols; means providing compatibility of Unilink ports with PRIZMA-EQ switch fabric; means for sub-port flow control; means providing a capability for DASL ports to support individual ports and link parallel ports; wherein the means for translating comprises means for providing operation of the chip in one of a line card mode and switch card mode; and wherein the means for providing operation in the line card mode comprises a first block providing data translation from DASL protocol to Unilink protocol, including: