Patent ID: 6130729
Filing Date: 2000-10-10
Classification: G02F

Abstract:
A method of fabricating an AMLCD comprising the steps of:providing a first conductive layer on a substrate surface;patterning said first conductive layer to form a gate line extending in a first direction on said substrate surface and having a first region corresponding to a gate electrode region, a second region corresponding to a non gate electrode region, and a contact hole adjacent to said first region and said second region, said gate line exposing a portion of said substrate;forming an insulating layer on said first conductive layer and said exposed portion of said surface of said substrate;forming an amorphous silicon layer on said insulating layer;patterning said amorphous silicon layer to form a semiconductor active layer overlapping said first region and a portion of said contact hole of said gate line, and exposing a portion of said first insulating layer;forming an insulating layer on an exposed surface of said first insulating layer and on said semiconductor active layer;patterning said insulating layer to form an etch stopper having the same shape as said gate line;exposing a portion of said semiconductor active layer;forming a second conductive layer on said substrate; and, patterning said second conductive layer to form a data line on said substrate.