Patent ID: 6165052
Filing Date: 2000-12-26
Classification: B24B,H01L

Abstract:
A method to planarize a surface of a semiconductor substrate while forming shallow trench isolation to prevent dishing of a wide trench shallow trench isolation and erosion of small silicon nitride areas on the surface of said semiconductor substrate, comprising the steps of:chemical/mechanical planarization polishing at a first product of platen pressure and platen speed to planarize said semiconductor substrate at a high rate of material removal with low selectivity to increase production throughput;determining an end point exposure of the silicon nitride areas;reaching said end point exposure of the silicon nitride areas; andwhen the end point exposure is reached, chemical/mechanical planarization polishing at a second product of platen pressure and platen speed to planarize said semiconductor substrate with a slow over polish to control thickness of a trench oxide of the shallow trench isolation to reduce dishing and minimize erosion.