Patent ID: 6425064
Filing Date: 2002-07-23
Classification: G06F

Abstract:
A memory structure for storing memory vectors comprising:a plurality of blocks containing a plurality of storage locations for storing memory vectors, each block being organized as a plurality of memory planes with data memory fields, where like numbered planes of each memory block constitute said storage locations such that all storage locations each have a part in each memory block, the storage locations being arranged parallel to each other and extending from a memory input deeper into the memory such that each memory vector is arranged to be undividedly stored in sequential order with a beginning of a vector at the memory input; addressing means for individually addressing each of said storage locations for storing and reading each memory vector to and from said plurality of memory blocks; input buffers arranged to input the memory vectors unbroken sequence according to the addressing, the input buffers being cascade coupled with each other and the vectors being inputted in a buffer-by-buffer manner in the memory fields; output buffers arranged to output the memory vectors in unbroken sequence according to the addressing in a buffer-by-buffer manner; and control logic arranged in each memory block for controlling inputting of information into the memory fields via the input buffers, and wherein the control logic in each memory block is arranged to inform the control logic in next memory block when the memory fields in the next memory block can take over reading in of the information into the memory fields in the next memory block.