Patent ID: 7634644
Filing Date: 2009-12-15
Classification: G06F

Abstract:
1. A computing apparatus configured to execute an instruction set that includes at least one delayed control transfer type instruction (DCTI), the computing apparatus comprising: a pipeline front-end for fetching instructions from an instruction store without regard to an architecturally-defined special branching behavior for program sequences that include a second DCTI in a delay slot of a first DCTI, wherein the pipeline front-end lacks capability to determine proper execution order for nested DCTIs within fetched groups of instructions; and a downstream pipeline section configured (i) to identify in a speculatively executed instruction sequence including at least one subsequence that is inconsistent with the architecturally-defined special branching behavior, the at least one subsequence containing the second DCTI in the delay slot of the first DCTI, and (ii) to enforce the architecturally-defined special branching behavior wherein said downstream pipeline section is located in the pipeline after an execution section.