Patent ID: 6200821
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method for fabricating a ferroelectric random access memory (FeRAM) device, comprising the steps of:forming an interlayer insulating layer on a ferroelectric capacitor and a transistor;forming a first opening through the interlayer insulating layer in order to expose a top electrode of the ferroelectric capacitor;forming a barrier metal layer on the resulting structure on which the first opening is formed, wherein the barrier metal layer is in contact with the top electrode of the ferroelectric capacitor;selectively etching the barrier metal and interlayer insulating layer and forming a second opening in order to expose a junction layer of the transistor;forming a polysilicon layer on the resulting structure and doping impurity ions into the polysilicon layer, wherein the doped polysilicon layer is in contact with the junction layer of the transistor; andselectively etching the polysilicon and barrier metal layer, thereby patterning an interconnection layer for interconnecting the transistor and the ferroelectric capacitor, wherein the capacitor is electrically in contact with the interconnection layer via the barrier metal layer and the transistor is electrically in contact with the interconnection layer.