Patent ID: 6380629
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A wafer level stack package comprising:upper and lower semiconductor chips each having a first face and an opposite second face, wherein the first face has a plurality of bond pads formed thereon, and wherein the first faces of the upper and lower semiconductor chips confront each other with a selected distance; first insulating layers formed respectively on the first faces of the upper and lower semiconductor chips so that their bond pads are exposed therefrom; upper and lower metal patterns formed respectively on the first insulating layers, wherein each metal pattern has a first end electrically connected to the bond pad and a second end laterally extended toward a boundary of the semiconductor chip; second insulating layers formed respectively on the first insulating layers and attached to each other; through holes formed at the boundary of the upper semiconductor chip so that the second ends of the upper and the lower metal patterns are exposed in the through holes; medium patterns each formed on an inside wall of each through hole, wherein the second ends of the upper and the lower metal patterns in each through hole are electrically connected by each medium pattern; a pattern film adhered on a second face of the upper semiconductor chip, and having a plurality of ball lands formed thereon, wherein each medium patterns are electrically connected to each ball land; a molding compound filled inside the through holes; and solder balls each formed on each ball land of the pattern film.