Patent ID: 8633888
Filing Date: 2014-01-21
Classification: G09G,G11C

Abstract:
1. A shift register comprising a plurality of stages for sequentially driving gate lines to which pixels for display of an image are connected, wherein each of the stages comprises: a plurality of nodes; a scan pulse output unit controlled according to voltages at the nodes for outputting a scan pulse and supplying the scan pulse to a corresponding one of the gate lines through a scan output terminal; a carry pulse output unit controlled according to the voltages at the nodes for outputting a carry pulse and supplying the carry pulse to an upstream one of the stages and a downstream one of the stages through a carry output terminal; a node controller for controlling voltage states of the nodes in response to a carry pulse from the upstream stage and a carry pulse from the downstream stage; and a discharging unit connected to any one of a plurality of clock transfer lines and the scan output terminal for discharging a spike voltage of the scan output terminal, the clock transfer lines transferring a plurality of clock pulses with different phases, respectively; wherein the discharging unit comprises a discharging switching device turned on or off in response to the spike voltage of the scan output terminal, the discharging switching device interconnecting the scan output terminal and any one of the clock transfer lines when turned on.