Patent ID: 6704609
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A process of manufacturing a multi-chip semiconductor module, comprising the steps of:(a) providing a chip-mounting member including first and second substrates, said first substrate having opposite first and second surfaces, a plurality of first conductive vias that extend through said first and second surfaces, a first circuit layout patterned on said second surface and connected electrically to said first conductive vias, and a plurality of first testing points disposed on said second surface and connected electrically to said first circuit layout, said second substrate having opposite first and second surfaces, a plurality of second conductive vias that extend through said first and second surfaces of said second substrate, a second circuit layout patterned on said second surface of said second substrate and connected electrically to said second conductive vias, a plurality of second testing points disposed on said second surface of said second substrate and connected electrically to said second circuit layout, and a first chip-receiving opening formed therein; (b) mounting a first contact pad surface of a first semiconductor chip on said second surface of said first substrate, and connecting electrically a plurality of first contact pads on said first contact pad surface to said first circuit layout; (c) testing said first semiconductor chip through said first testing points of said first substrate so that replacement of said first semiconductor chip can be conducted if said first semiconductor chip is found to be defective; (d) bonding said first surface of said second substrate on said second surface of said first substrate such that said first semiconductor chip is disposed in said first chip-receiving opening and such that said second circuit layout is connected electrically to said first circuit layout through said first and second conductive vias; (e) mounting a second contact pad surface of a second semiconductor chip on said second surface of said second substrate, and connecting electrically a plurality of second contact pads on said second contact pad surface to said second circuit layout; and (f) testing said second semiconductor chip through said second testing points of said second substrate so that replacement of said second semiconductor chip can be conducted if said second semiconductor chip is found to be defective.