Patent ID: 8686560
Filing Date: 2014-04-01
Classification: H01L

Abstract:
1. A wafer-level chip-scale package device comprising: an integrated circuit chip, the integrated circuit chip comprising a first area in which bump assemblies are disposed and a second area in which bump assemblies are disposed, wherein bump assemblies disposed in the second area experience elevated levels of stress due to mechanical or thermal forces compared to bump assemblies disposed in the first area when the integrated circuit chip is mounted to a printed circuit board via the bump assemblies, where the first area is proximate to a center area of the integrated circuit chip and the second area is proximate to the perimeter of the integrated circuit chip: at least one array of first bump assemblies disposed on the integrated circuit chip within the first area, the first bump assemblies including solder bumps; and at least one array of second bump assemblies disposed on the integrated circuit chip within the second area, the second bump assemblies including solder bumps and at least one copper pillar, wherein the solder bumps of the second bump assemblies are larger than the solder bumps of the first bump assemblies to resist failure due to the elevated levels of stress, and the at least one array of second bump assemblies is configured to furnish only mechanical attachment of the wafer-level chip-scale package device to a printed circuit board.