Patent ID: 6184080
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method for manufacturing a dynamic random access memory (DRAM) device sad method comprising the steps of:(a) providing a substrate of semiconductor material having a main outer surface;(b) forming, of said semiconductor material, a plurality of active regions extending outwardly from said main outer surface of said substrate, each of said active regions having an outer surface and having a longer and a shorter dimension when viewed in plan;(c) forming a plurality of isolation regions, of an insulating material, between said active regions;(d) forming a plurality of substantially parallel word lines located outwardly from said active regions in a direction substantially parallel to said shorter dimension of said active regions and substantially perpendicular to said longer dimension of said active regions, two of said word lines being associated with each of said active regions and two of said word lines being positioned between adjacent active regions;(e) depositing a first word line insulation material to surround both said word lines and portions of said DRAM device where periphery circuit gate wiring is to be formed;(f) filling spaces between said word lines with a second word line insulation material which is selectively etchable with respect to said first word line insulation material;(g) applying a special pattern mask over portions of said second insulation material where the periphery circuit wiring is to be formed;(h) selectively etching said second word line insulation material to create a plurality of doped polysilicon receiving cavities;(i) depositing doped polysilicon in said doped polysilicon receiving cavities to form:a plurality of unitary bit line contacts having outer surfaces and extending inwardly to corresponding ones of said active regions, one each for each of said active regions; anda plurality of unitary storage node contacts having outer surfaces and extending inwardly to corresponding ones of said active regions, two each for each of said active regions;(j) simultaneously forming a plurality of inwardly-projecting bit line portions, one for each of said bit line contacts, and a plurality of inwardly-projecting storage node portions, one for each of said storage node contacts;(k) forming a plurality of substantially parallel bit lines located outwardly from said word lines and being substantially perpendicular thereto, said bit lines being located between adjacent ones of said active regions when viewed in plan, said bit lines being electrically isolated from each other, each of said bit lines being electrically interconnected with corresponding ones of said inwardly-projecting bit line portions; and(l) forming a plurality of storage nodes extending outwardly of said bit lines, each of said storage nodes having a longer and a shorter dimension when viewed in plan, said longer dimension of said storage nodes being generally parallel to said longer dimension of said active regions and said shorter dimension of said storage nodes being generally parallel to said shorter dimension of said active regions, at least substantial portions of said storage nodes being located substantially directly outwardly of said active regions when viewed in plan and being located between said bit lines when viewed in plan, said storage nodes being electrically interconnected with corresponding ones of said inwardly-projecting storage node portions.