Patent ID: 7146456
Filing Date: 2006-12-05
Classification: G11C

Abstract:
1. A dynamic random access memory device capable of converting from a full density memory device to a reduced density memory device to compensate for cell failures in a plurality of cell blocks, the memory device comprising: a row address mapping fuse for selectively determining row address combinations void of cell failures and capable of storing data bits; row address mapping logic coupled to the row address mapping fuse for receiving a row address mapping signal from the row address mapping fuse and receiving row address signals and for routing specific data bits to the row address combinations void of cell failures and capable of storing the data bits; a reduced density enable signal for switching the memory device between a full density mode and a reduced density mode; a logic value setting signal; a multiplexer having a first input coupled to the reduced density enable signal, a second input coupled to the logic value setting signal, and a third input coupled to a row address; and wherein an output signal of the multiplexer is coupled to an input of the row address mapping logic.