Patent ID: 6744126
Filing Date: 2004-06-01
Classification: H01L,Y10S

Abstract:
A multichip semiconductor package device, comprising:a first device that includes: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, wherein the bottom surface includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity; a first semiconductor chip within the insulative housing and outside the cavity, wherein the first chip includes an upper surface and a lower surface, and the upper surface includes a conductive pad; and a conductive trace that includes a terminal and a lead, wherein the terminal extends through the central portion, the lead protrudes laterally from and extends through the side surface, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another and to the pad; a second device that includes a second semiconductor chip, wherein the second device extends into the cavity and is positioned within and does not extend outside a periphery of the cavity; and a conductive bond inside the cavity and on the terminal that contacts and electrically connects the first and second devices.