Patent ID: 6137168
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A semiconductor device package comprising:a substrate with opposed upper and underside surfaces:a die disposed upon the upper surface of the substrate, the die having a plurality of bond pads:a first signal layer adjacent to the upper surface of the substrate comprising:a plurality of bonding fingers;a plurality of first signal traces separated from one another, each of the plurality of first signal traces connected to a corresponding one of the bonding fingers, at least a portion of each of the first signal traces extending along the upper surface ol the substrate underneath the die;a plurality of bonding wires, each of the plurality of bonding wires connecting a corresponding one of the plurality of bond pads to a corresponding one of the plurality of bonding fingers, wherein a first one of the plurality of bonding wires is connected to a first one of the plurality of bond pads, wherein the first one of the plurality of bond pads corresponds to an input/output signal that is not a power or ground signal;a second signal layer, comprising a plurality of second signal traces;a plurality of vias, each connecting a corresponding one of the plurality of first signal traces to a corresponding one of the second signal traces such that a signal path is formed between the bonding fingers and the second signal traces;a conductive ring disposed on the upper surface of the substrate, wherein the bonding fingers are disposed between the die and the conductive ring;a conductive ground plane positioned between the first and second signal layers; anda combined power and ground plane positioned between the ground plane and the second signal layer.