Patent ID: 7192876
Filing Date: 2007-03-20
Classification: G11C,H01L

Abstract:
1. A method of making a semiconductor device, comprising: providing a substrate and a semiconductor structure over the substrate, the semiconductor structure having a first sidewall, a second sidewall, and a top surface; depositing at least one substantially conformal layer over the substrate, wherein the at least one substantially conformal layer comprises at least a layer of gate material, forming a substantially planar layer over the substrate below the height of the top surface of the at least one substantially conformal layer over the semiconductor structure; and non-abrasive etching through the layer of gate material over the top surface of the semiconductor structure, wherein the non-abrasive etching further comprises non-abrasive etching through the layer of gate material over a channel region of the semiconductor structure, wherein the non-abrasive etching through the layer of gate material further comprises etching the layer of gate material to leave a first portion of gate material located adjacent to the first sidewall and a second portion of gate material located adjacent to the second sidewall; forming a first current terminal region in the semiconductor structure; forming a second current terminal region in the semiconductor structure; wherein a first gate of a first functional transistor includes material of the first portion of gate material, the first functional transistor has a first channel region between the first current terminal region and the second current terminal region, the first channel region including at least a portion of the semiconductor structure located alone the first sidewall adjacent to the first gate; wherein a second gate of a second functional transistor includes material of the second portion of gate material, the second functional transistor has a second channel region between the first current terminal region and the second current terminal region, the second channel region including at least a portion of the semiconductor structure located along the second sidewall adjacent to the second gate.