Patent ID: 7238570
Filing Date: 2007-07-03
Classification: B82Y,G11C,H01L

Abstract:
1. A method for producing a semiconductor memory device having a memory array structure comprising: a plurality of charge storage regions formed on a main surface of a first conductor type semiconductor substrate through a first insulator; a plurality of word lines formed on said plurality of charge storage regions through a second insulator; wherein said method includes the following steps: (a) forming a first conductor film for said plurality of word lines on said second insulator, then forming a third insulator on said first conductor film; (b) patterning said third insulator and said first conductor film, thereby forming a plurality of first word lines within a space therebetween; (c) subjecting said semiconductor substrate to a thermal oxidation process to form a side spacer on a side face of each of said plurality of first word lines; and (d) embedding a second conductor film for word lines in each of said space regions after said step (c) so as to form a plurality of second word lines in each of said plurality of space regions.