Patent ID: 7675110
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an active region that is surrounded by an isolation region, the active region having source/drain diffusion regions and a gate trench formed between the source/drain diffusion regions; a gate electrode at least a part of which is buried in the gate trench; and contact plugs connected to the source/drain diffusion regions, wherein the isolation region and the gate trench are arranged along a first direction, a periphery of the contact plugs at an isolation region side extends from a boundary between the isolation region and the active region in a second direction crossing the first direction so as to be aligned with the boundary, and another periphery of the contact plugs at a side opposed to the isolation region side extends from an opening edge of the gate trench in the second direction so as to be aligned with an inner surface of the gate trench; a cap provided on the gate electrode, wherein an upper surface of the contact plugs and an upper surface of the cap are coplanar.