Patent ID: 7741670
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A semiconductor capacitor, comprising: a first plurality and a second plurality of overlapping metal layers that create a first capacitance between the first and second plurality of metal layers, wherein each layer of the first and second plurality of metal layers includes at least one inter-digital capacitor; and a field-effect transistor (FET) having a source, a drain, and a gate, wherein a bias of said FET is controlled by biasing said source, drain, and gate with respect to each other; wherein a second capacitance is created between the gate and a conductive path between the source and the drain when the FET is in conduction mode; and wherein the semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first plurality of metal layers and coupling the gate to the second plurality of metal layers.