Patent ID: 8987794
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having a top surface with a first lattice constant; embedded epi source and drain regions disposed on the top surface of the substrate, said embedded epi source and drain regions having a second lattice constant that is different from the first lattice constant; a plurality of channel nanowires having a third lattice constant that is different from the first lattice constant, wherein the third lattice constant is the same as the second lattice constant, said plurality of channel nanowires coupled to the embedded epi source and drain regions, and said plurality of channel nanowires including a bottom-most channel nanowire; a gate dielectric layer disposed on and all-around each channel nanowire; and, a gate electrode disposed on the gate dielectric layer and surrounding each channel nanowire.