Patent ID: 7582534
Filing Date: 2009-09-01
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of forming a field effect transistor (FET), comprising: (a) providing a gate; (b) forming a gate dielectric on the gate; (c) forming a channel comprising a nano-component on the gate dielectric; (d) forming a source over a first region of the nano-component; (e) forming a drain over a second region of the nano-component; and (f) exposing at least one portion of the nano-component to a dopant selected from the group of hydrazine, mono-, di-, tri- or tetra-kis trimethylsilylhydrazine, a hydrazine derivative, diazobicycloundecane and polyaniline and further comprising, prior to the step (f), the steps of: (g) providing a dielectric layer on the nano-component; (h) providing a gate material layer on the dielectric layer; (i) patterning the gate material layer to form a top gate; and (j) patterning the dielectric layer by using the top gate as a mask.