Patent ID: 6372572
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of planarizing a peripheral circuit region of dynamic random access memory (DRAM), comprising:providing a substrate, forming a first oxide layer over the substrate; forming a stopping layer over the first oxide layer; forming a plurality of polysilicon plugs that pass through the first oxide layer and the stopping layer; depositing a second oxide layer over the stopping layer and the polysilicon plugs; patterning the second oxide layer to form openings that expose the polysilicon plugs and a portion of the stopping layer around the plug, thereby forming a crown-shaped capacitor region and a peripheral circuit region; forming a conformal doped amorphous silicon layer over the exposed polysilicon plug, the stopping layer and the second oxide layer; depositing photoresist material to form a photoresist layer over the crown-shaped capacitor region; implanting nitrogen into the peripheral circuit region to form a silicon oxy-nitride layer over the second oxide layer; performing a chemical-mechanical polishing to expose a portion of the doped amorphous silicon layer so that a plurality of lower electrodes are separated from each other; removing a portion of the second oxide layer and a portion of the photoresist layer within the crown-shaped capacitor region; growing hemispherical silicon grains over the exposed surface of the lower electrodes; forming a dielectric layer over the hemispherical grain-covered lower electrodes and the silicon oxy-nitride layer; and depositing a conductive material over the dielectric layer to form an upper electrode.