Patent ID: 7498642
Filing Date: 2009-03-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate with a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; a lightly doped source/drain (LDD) region substantially aligned with an edge of the gate electrode, the LDD region comprising an n-type impurity; a heavily doped source/drain (N+ S/D) region in the semiconductor substrate, the N+ S/D region comprising an n-type impurity and being further away from the channel region than the LDD region; a p-type pocket/halo region substantially along a border of the N+ S/D region, the border being on a side close to the channel region; and a diffusion-retarding region in the semiconductor substrate substantially aligned with an edge of the gate electrode, wherein the diffusion-retarding region comprises fluorine, and wherein the diffusion-retarding region is substantially deeper than the N+ S/D region, and wherein the diffusion-retarding region extends into a region underlying the gate electrode.