Patent ID: 8819612
Filing Date: 2014-08-26
Classification: G06F

Abstract:
1. A computer-implemented method for analyzing timing requirements of a hierarchical integrated circuit design having a plurality of child units, the method comprising: accessing a netlist having a plurality of logic gates of a child unit from the plurality of child units; determining a set of logic gates are members of both the plurality of logic gates of the child unit and a plurality of logic gates of an abstract model of the child unit; marking the set of logic gates, based on the determination, such that an integrated circuit modification process recognizes the set of logic gates; executing the integrated circuit modification process on the child unit, such that at least one logic gate from the child unit is changed; preserving the set of marked logic gates, in response to the marking, such that the set of logic gates are unchanged by the integrated circuit modification process; and generating a new child unit in response to the integrated circuit modification process.