Patent ID: 6826522
Filing Date: 2004-11-30
Classification: G06F

Abstract:
A method of simulation of a multi-parallel-stage pipelined processor resulting in greatly reduced memory requirements and reduction of stage state data copying, the method comprising the steps of:reordering a chronological sequence of a plurality of pipeline stages as a reverse order of execution of software models of the plurality of pipeline stages with respect to the actual instruction-flow sequence implemented by a processor performing the software simulation, wherein said multi-parallel-stage pipelined processor comprises a plurality of execution units, each execution unit modeled as a stage in the plurality of pipeline stages, the plurality of execution units having execution priorities ranging from highest to lowest, said software simulation of the execution units performed in order of lowest priority to highest priority; and taking advantage of independence of stages within a cycle to be simulated or emulated to make results computed by a previous stage directly available to a subsequent stage without using additional data space or data copying than is required for pipeline stage processing.