Patent ID: 8536922
Filing Date: 2013-09-17
Classification: G06F,H03K

Abstract:
1. An apparatus comprising: a first component configured to receive a first clock signal to generate second clock signals, wherein the first component includes a current-mode logic component to receive the first clock signal; and a second component configured to convert the second clock signals into third clock signals used to transfer data, the second component configured such that a signal swing from one final level to another signal level of the third clock signals is greater than a signal swing from one signal level to another signal level of the second clock signals, wherein the second component includes complementary-metal-oxide semiconductor (CMOS) inverters having input nodes responsive to the second clock signals to provide the third clock signals at output nodes of the CMOS inverters, and the first component is configured such that the second clock signals have a frequency a lower than a frequency of the first clock signal.