Patent ID: 8218352
Filing Date: 2012-07-10
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a memory cell which includes a first inverter and a second inverter, said first inverter comprising a first drive transistor and a first load transistor, said second inverter including a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter; a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair; a second transmission transistor provided between the output terminal of the second inverter and another line of the first bit line pair; a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair; a fourth transmission transistor provided between the output terminal of the second inverter and another line of the second bit line pair; a first isolation transistor which isolates the second drive transistor and the first transmission transistor, a second isolation transistor which isolates the first drive transistor and the fourth transmission transistor.