Patent ID: 7039834
Filing Date: 2006-05-02
Classification: G06F

Abstract:
1. An apparatus for collecting high-speed processor interconnect signals over a period of time sufficient for steady state effects to become manifest in as system under test, said apparatus comprising: an input channel circuit for receiving all activity on a high speed processor interconnect in a system under test, a preview pipeline circuit connected to monitor said input channel for capturing all occurrences of said high-speed processor interconnect signals at processor speed, a trigger circuit maintaining a predetermined trigger value to compare against said all occurrences, and to trigger identification of all of said high-speed processor interconnect signals associated with each appearance of a trigger signal equivalent to said predetermined trigger value in said occurrences captured by said pipeline circuit and to pass each instance of said occurrences which are associated with a said appearance of a trigger signal as a word on to a compaction circuit, wherein said trigger may be set to at least one trigger value as desired by a user and wherein said trigger values correspond to processor ID values in said system under test, a time stamp generating circuit for generating a time stamp value signal for each said occurrence and associating a one of said time stamp values associated with a one of said each occurrences, said compaction circuit for eliminating any wasted space within said word and passing compacted sets of such words as an entry signal on to a high speed FIFO memory at said high speed processor interconnect speed, each of said worms in said compacted set of words being passed with an associated time stamp value signal, said high speed FIFO memory operating at said high-speed processor interconnect speed for receiving said entry signals at said high-speed processor interconnect speed and for providing that each of said entry signals is associated with a said associated one of said time stamp value signals, and for providing a said entry and its said associated time stamp value signals to an output channel.