Patent ID: 9036754
Filing Date: 2015-05-19
Classification: G04G,G04R,G06F,H04W,Y02D

Abstract:
1. A circuit comprising: a system clock generator operable to receive a symbol frequency, the system clock generator operating at a frequency that is an integer multiple of the symbol frequency and having a frequency divider configured to output symbols that are to be counted in an operating mode by dividing the frequency; a sleep clock generator having an output frequency of an output clock signal of the sleep clock generator being a non-integer multiple of the symbol frequency; a switch configured to produce the symbols to be counted by blanking the output clock signal of the sleep clock generator in a sleep mode; a modulo divider connectable to an output of the sleep clock generator and switchable between at least two integer divisor values, an output of the modulo divider being connectable to a control input of the switch to blank out the output clock signal via the modulo divider; and a logic element connectable to a control input of the modulo divider, the logic element configured to control a division factor of the modulo divider by changing a division factor of the modulo divider.