Patent ID: 6055192
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A method for operatively controlling a dynamic random access memory device incorporating a memory array comprising rows and columns of memory cells, each of said memory cells including an access transistor and associated capacitor, a first terminal of said access transistor being coupled to a bit line selectively couplable to either of first and second supply voltage sources and a second terminal of said access transistor being coupled to one terminal of said associated capacitor, said associated capacitor having an opposite terminal thereof coupled to a fixed voltage source, said access transistor further having a control terminal coupled to a word line, said method comprising:causing said bit line to approach a bit-line precharge voltage to precharge said bit line;subsequently coupling said word line to a read-state voltage source to read a state of said associated capacitor;boosting said word line beyond a level of said read-state voltage source to restore said state of said associated capacitor; andadditionally boosting said word line beyond said level of said read-state voltage source prior to, during, or following, each write operation or group of write operations to said memory cell.