Patent ID: 7638839
Filing Date: 2009-12-29
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a pair of main surfaces, wherein said semiconductor substrate comprises: a first semiconductor region of a first conduction type adjacent to one of the main surfaces of the semiconductor substrate and positioned within the semiconductor substrate; a second semiconductor region of a second conduction type adjacent to the first semiconductor region and having a carrier concentration lower than a carrier concentration of the first semiconductor region; a plurality of MOS type trench gates having at least two sorts of intervals thereof extended from the other main surface into the second semiconductor region; a third semiconductor region of the first conduction type provided between the MOS type trench gates and having a carrier concentration higher than a carrier concentration of the second semiconductor region; a fourth semiconductor region of the second conduction type provided between the adjacent MOS type trench gates having a narrow interval therebetween to be positioned within the third semiconductor region and to be contacted with the MOS type trench gate and having a carrier concentration higher than a carrier concentration of the third semiconductor region; a fifth semiconductor region of the second conduction type provided between the adjacent MOS type trench gates having a broad interval therebetween to be positioned within the third semiconductor region and to be contacted with the MOS type trench gates and having a carrier concentration higher than a carrier concentration of the third semiconductor region; a first electrode provided between the adjacent MOS type trench gates having the narrow interval to be contacted with the third and fourth semiconductor regions: and a second electrode contacted with the first semiconductor region, wherein a ratio Y/X of a width X between the adjacent trench gates including the fourth semiconductor region with respect to a width Y between the adjacent trench gates including the fifth semiconductor region is made equal to or larger than two.