Patent ID: 7506017
Filing Date: 2009-03-17
Classification: G06F

Abstract:
1. Duplex multiplier circuitry that is configurable to operate as either a single multiplier or at least two smaller multipliers, comprising: partial product generation circuitry; first and second circuits that receive partial product signals from the partial product generation circuitry; carry look-ahead adder circuitry that receives carry and sum signals from the first and second circuits; and carry blocking circuitry connected between the first and second circuits that prevents carry signals from the first circuit from propagating to the second circuit when the duplex multiplier operates as two smaller multipliers, wherein the first and second circuits are Wallace tree circuits, wherein the Wallace tree circuits have a plurality of slices of circuitry, wherein each slice of circuitry corresponds to a different bit position, wherein at least one of the slices of circuitry comprises seven full adders, wherein the partial product generation circuitry produces a given signal at its output that is received by one of the slices of circuitry in the Wallace tree circuits, and wherein: