Patent ID: 7917706
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. A memory controller for accessing a memory, the memory controller comprising: at least one first input port connected with a first bus line, wherein multiple bus masters are each connected with the first bus line; an arbiter, for forming a queue of memory access requests from memory access requests received on the at least one first input port, wherein the arbiter receives a bus master identifier and an address of the memory included in each memory access request received on the at least one first input port, the bus master identifier indicating which of the multiple bus masters each said memory access request originates, and wherein the arbiter prioritizes memory access requests among the multiple bus masters within said queue based on a priority level of the associated bus master identifiers and based on the addresses received in the memory access requests, wherein the arbiter gives a higher priority to memory access requests which relate to a page in the SDRAM which is closed, but which can be opened as a background process, than a priority given to a portion of other memory access requests of the same type, wherein read access requests are of a first type and write access requests are of a second type.