Patent ID: 7187617
Filing Date: 2007-03-06
Classification: G11C

Abstract:
1. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus to allow data to be output from the computer system; a data storage device coupled to the processor through the processor bus to allow data to be read from a mass storage device; a memory controller coupled to the processor through the processor bus, the memory controller comprising a first strobe generator circuit operable to generate a first strobe signal and a second strobe signal, the second strobe signal having signal transitions that are offset from signal transitions of the first strobe signal by 90 degrees, the second strobe signal being coupled to a strobe signal output terminal of the memory controller; a data path circuit operable to couple read data signals to the processor from data bus terminals of the memory controller and to coupled write data signals to the data bus terminals of the memory controller from the processor, the data path circuit comprising: a first output latch having an input terminal coupled to the processor, an output terminal coupled to the data bus terminals of the memory controller, and a clock terminal coupled to receive the first strobe signal from the strobe generator circuit, the first output latch being operable to couple read data bits from the output latch to the data bus terminals responsive to a transition of the first strobe signal; and a first input latch having an input terminal coupled to the data bus terminals, an output terminal coupled to the processor, and a clock terminal coupled to a strobe signal input terminal of the memory controller; and a memory device coupled to the memory controller, the memory device comprising: a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device; a column address circuit operable to receive and decode column address signals applied to the external address terminals; a memory cell array operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals; a second strobe generator circuit operable to generate a periodic third strobe signal and a periodic fourth strobe signal, the fourth strobe signal having signal transitions that are offset from signal transitions of the third strobe signal by 90 degrees, the fourth strobe signal being coupled to the strobe signal input terminal of the memory controller; a data path circuit operable to couple data signals corresponding to the data between the array and data bus terminals of the memory device, the data path circuit comprising: a second output latch having an input terminal coupled to the array, an output terminal coupled to the data bus terminals, and a clock terminal coupled to receive the third strobe signal from the second strobe generator circuit and to couple read data bits from the output latch to the data bus terminals responsive to a transition of the third strobe signal; and a second input latch having an input terminal coupled to the data bus terminals, an output terminal coupled to the array, and a clock terminal coupled to receive the second strobe signal from the strobe signal output terminal of the memory controller; and a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.