Patent ID: 7834433
Filing Date: 2010-11-16
Classification: H01L

Abstract:
1. A packaged power semiconductor device, comprising: a single gauge lead frame comprising: a semiconductor die attached to an upper surface of said second level of said single gauge lead frame; a heat sink, having an upper surface attached to a lower surface of said second level of said single gauge lead frame, and a portion of a lower surface of the heat sink includes a recess from a first edge of the heat sink to define an extended portion having a wall portion and a ceiling portion, wherein the first level of the single gauge lead frame projects from a second edge of the heat sink that is coupled to the first edge of the heat sink at a corner; and a molding compound that encapsulates said semiconductor die and a portion of said single gauge lead frame, wherein the lower surface of said heat sink below the single gauge lead frame is outside of said molding compound, wherein the heat sink is exposed from the molding compound on portions of the upper surface and the lower surface of the heat sink in a region that is not directly below the single gauge lead frame; wherein a third edge of the second level of the single gauge lead frame and the first edge of the heat sink are in line with each other, and wherein a first distance from the third edge of the second level of the single gauge lead frame to the die is greater than a second distance from the wall portion of the extended portion to the die.