Patent ID: 6016019
Filing Date: 2000-01-18
Classification: H01L,H03M

Abstract:
A capacitor array layout technique for improving capacitor array matching comprising the steps of:providing a capacitor array;laying said capacitor array in a geometrical configuration wherein said geometrical configuration has a centerpoint;dividing said geometrical configuration into a plurality of first sections wherein each of said plurality of first sections has a corresponding second section diagonally located from said first section and at an approximately equal distance from said centerpoint as said first section;dividing at least one of said plurality of first sections into a plurality of first sub-sections;dividing said corresponding second section of said at least one of said plurality of first sections into a plurality of second sub-sections wherein each of said plurality of first sub-sections has a corresponding second sub-section diagonally located from and at an approximately equal distance from said centerpoint;housing in each of said first and second sections which are not divided into a plurality of sub-sections a capacitor set of a predetermined value wherein each of said plurality of first sections which are not divided into a plurality of sub-sections house a capacitor set of an equal value as said corresponding second section; andhousing in each of said plurality of first and second sub-sections a sub-capacitor set of a predetermined value wherein each of said plurality of first sub-sections house a sub-capacitor set of an equal value as said corresponding second sub-section and wherein the sub-capacitor sets of a divided section are of non-equal value.