Patent ID: 6523055
Filing Date: 2003-02-18
Classification: G06F

Abstract:
A multiplication accumulation circuit comprising:a plurality of control lines, an output bus and at least five input buses, wherein: a first input bus carries a first operand A, a second input bus carries a second operand B, a third input bus carries a third operand C, a fourth input bus carries a fourth operand D, and a fifth input bus carries a fifth operand E; a first multiplier unit coupled to each of the first input bus, the second input bus, and the fourth input bus, the first multiplier unit having a plurality of first output terminals and a first control terminal, the first control terminal being coupled to a first control line in the plurality of control lines, wherein: the first multiplier unit multiplies the second operand and the fourth operand and supplies on the first output terminals a first signal indicative of the value B*D in response to an active signal on the first control terminal; a second multiplier unit coupled to the first input bus, the second input bus, and the third input bus, the second multiplier unit having a plurality of second output terminals and a second control terminal, the second control terminal being coupled to a second control line in the plurality of control lines, wherein: the second multiplier unit multiplies the first operand and the third operand simultaneous with the multiplication by the first multiplier unit and supplies on the second output terminals a second signal of the value A*C in response to an active signal on the second control terminal; a shifting circuit coupled to a selected one of the first multiplier unit and the second multiplier unit to receive a selected one of the first signal and the second signal as a shift input signal, the shifting circuit having a plurality of shift output terminals and a shift enable terminal, the shift enable terminal being coupled to a third control line in the plurality of control lines wherein: the shift input signal has a plurality of bits and the shifting circuit shifts all bits in the shift input signal by a predetermined number of positions and supplies a shifted signal on the shift output terminals in response to an active signal on the shift enable terminal; and an adding circuit having a plurality of first group of adding input lines, a plurality of second group of adding input lines, a plurality of adding output terminals, a plurality of accumulate input lines, and an accumulate enable terminal, the accumulate enable terminal being coupled to a fourth control line in the plurality of control lines, the adding input lines in one of the first group and the second group being coupled to the shift output terminals, and the adding input lines in the other of the first group and the second group being coupled to the unselected multiplier unit, the accumulate input lines being coupled to the fifth input bus and the adding output terminals being coupled to the output bus, wherein: the adding circuit adds values of the signals received on the first adding input lines, on the second adding input lines, and on the accumulate input lines, and supplies on the adding output terminals a signal of the value A*C+B*D+E in response to an active signal on the accumulate enable terminal.