Patent ID: 8561003
Filing Date: 2013-10-15
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a substrate; a first block including a first set of semiconductor fins in a first region of the substrate, the first block including outer fins on opposing outside edges of the first block, and inner fins between the outer fins, the first block being arranged for devices having channels with a first conductivity type; a second block including a second set of semiconductor fins in a second region of the substrate, the second block including outer fins on opposing outside edges of the second block, and inner fins between the outer fins, the second block being arranged for devices having channels with a second conductivity type; an inter-block insulator in a third region of the substrate between outer fins of the first and second blocks; a patterned gate conductor layer including a first plurality of gate traces in the first block extending across the first set of semiconductor fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces in the second block extending across the second set of semiconductor fins in the second block without crossing the inter-block insulator; at least one patterned conductor layer in a level above the gate conductor layer, including an inter-block trace crossing over the inter-block insulator, and arranged to connect a gate trace in the first plurality of gate traces to a gate trace in the second plurality of gate traces; and a plurality of inter-layer connectors that connect semiconductor fins, gate traces, the inter-block trace and traces in the at least one patterned conductor layer.