Patent ID: 7823111
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A computer implemented semiconductor integrated circuit design method comprising: a step (l) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (p) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in said classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact, implemented by a central processing unit.