Patent ID: 6466267
Filing Date: 2002-10-15
Classification: H04N

Abstract:
A peak hold circuit comprising:peak detecting means for detecting and holding a peak value of an input signal supplied to an input thereof; switch means coupled to said input of said peak detecting means, for selectively supplying a section of the input signal as a peak hold section to said peak detecting means; peak hold control means for controlling said switch means to select said peak hold section causing said peak detecting means to detect the peak value for said peak hold section and to ignore other sections of the input signal; a first buffer which receives a solid-state imaging signal and generates the input signal therefrom; a second buffer circuit which receives said peak value for said peak hold section and generates a buffered peak value therefrom; a first voltage follower circuit coupled to said first buffer circuit for maintaining the input signal equal to the solid-state imaging signal; and a second voltage follower circuit coupled to said second buffer circuit for maintaining the buffered peak value equal to the peak value for said peak hold section.