Patent ID: 6121123
Filing Date: 2000-09-19
Classification: G03F,H01L,Y10S

Abstract:
A method for forming a gate structure from a semiconductor wafer stack comprising a substrate, a dielectric layer over the substrate, a conductive layer over the dielectric layer, a deposited dual-purpose bottom anti-reflective coating/hardmask material over the conductive layer, and a resist mask on the dual-purpose bottom anti-reflective coating/hardmask material, the method comprising:etching through selected portions of the dual-purpose bottom anti-reflective coating/hardmask material as defined by one or more etch windows in the resist mask;etching through selected portions of the gate conductive layer as defined by the extended etch windows in the dual-purpose bottom anti-reflective coating/hardmask material; andetching away the remaining portion of the dual-purpose bottom anti-reflective coating/hardmask material.