Patent ID: 6781439
Filing Date: 2004-08-24
Classification: G11C,H02M

Abstract:
A memory device comprising:a row decoder which selects a word line in accordance with an address signal; a column decoder which selects a bit line in accordance with the address signal; and a pump circuit having an output node connected to the row decoder, the pump circuit including a first booster circuit configured to boost a first voltage in response to a first signal and to generate a first boost voltage, the first booster circuit outputting the first boost voltage to the output node; a first detector connected to the output node, configured to compare a first divided voltage divided out of the first boost voltage and a reference voltage, and to generate the first signal for operating the first booster circuit when the first divided voltage is lower than the reference voltage; a second booster circuit configured to boost the first voltage in response to a second signal and to generate a second boost voltage, the second booster circuit outputting the second boost voltage to the output node; and a second detector connected to the output node and operating in response to an active signal generated in response to a change in the address signal, the second detector being configured to compare a second divided voltage divided out of the second boost voltage and the reference voltage, and to generate the second signal for operating the second booster circuit when the second divided voltage is lower than the reference voltage, wherein the row decoder selects the word line after the second detector is activated in response to the active signal.