Patent ID: 8938605
Filing Date: 2015-01-20
Classification: G06F

Abstract:
1. A method for managing instruction execution based on a current machine state, the method comprising: receiving at least one macroinstruction; decoding, by an instruction decode unit of a processor core, the at least one macroinstruction; based on the decoding, determining, a current machine state by the instruction decode unit; based on the current machine state that has been determined, directly cracking, by the instruction decode unit, the at least one macroinstruction directly into a set of unit of operations for a fixed size queue, each of the set of unit of operations being executable by at least one execution unit, the cracking reducing at least one of execution steps performed by an execution unit and execution pipes, wherein the instruction decode unit directly cracks the at least one macroinstruction for a plurality of unit of operation lengths, wherein the plurality of unit of operation lengths comprises at least a length of two unit of operations and a length of three unit of operations; and executing the at least one macroinstruction, wherein the executing comprises executing the set of unit of operations by one or more execution units.