Patent ID: 6271563
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A MOS transistor comprising:a source well and a drain well formed in a semiconductor substrate and defining a channel therebetween;a gate stack including a gate oxide formed on a surface of the semiconductor substrate over a portion of the channel and a gate on the gate stack; anda first spacer positioned on the surface of the semiconductor substrate on a source side of the gate stack over a source extension region in the channel between the source well and the gate stack in the semiconductor substrate and a second spacer positioned on the surface of the semiconductor substrate on a drain side of the gate stack over a drain extension region in the channel between the drain well and the gate stack in the semiconductor substrate, the first spacer and the second spacer being formed of a relatively high-K dielectric material to invert the surface of the semiconductor substrate in the source extension region and the drain extension region even when no voltage is applied to the gate stack of the MOS transistor,wherein said gate is on said high-K dielectric material on said source side and said drain side.