Patent ID: 7664218
Filing Date: 2010-02-16
Classification: G09G,G11C

Abstract:
1. A shift register comprising: an input terminal, an output terminal, a reset terminal and a first clock terminal; a first transistor configured to supply a first clock signal received at said first clock terminal to said output terminal; a second transistor configured to discharge said output terminal; a third transistor having a control electrode connected to said input terminal and configured to charge a first node connected to a control electrode of said first transistor; a fourth transistor having a control electrode connected to said reset terminal and configured to discharge said first node; a fifth transistor having a control electrode connected to a predetermined second node and configured to discharge said first node; a first buffer circuit configured to receive an output from a first inverter circuit and output a signal to said predetermined second node; and said first inverter circuit in which said first node serves as an input node, wherein said first inverter circuit includes: