Patent ID: 6128758
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A bus architecture for a computer system, said computer system having a first, a second, a third and a fourth module coupled together, each module having disposed within configuration registers and memory units, the bus architecture comprising:an input bus coupled to input terminals of said first module;a first multiplexer having a first set of input terminals coupled to output terminals of said first module, and output terminals coupled to input terminals of said second module;a first bus connecting output terminals of said second module to input terminals of said third module;a bi-directional test bus coupled to a second set of input terminals of said first multiplexer;a first buffer having input terminals coupled to said output terminals of said first module, and output terminals coupled to said test bus;a second multiplexer having a first set of input terminals coupled to said test bus, a second set of input terminals coupled to address output terminals of said fourth module;an address bus connecting output terminals of said second multiplexer to address input terminals of configuration registers and memory units of said second and third modules;a third multiplexer having a first set of input terminals coupled to input data terminals of said fourth module;a data-in bus connecting output terminals of said third multiplexer to input data terminals of said configuration registers and memory units of said second and third modules;a bi-directional data bus coupled to a second set of input terminals of said third multiplexer;a fourth multiplexer having a first set of input terminals coupled to output terminals of said third module;a data-out bus connecting output data terminals of said configuration registers and memory units of said second and third modules to a second set of input terminals of said fourth multiplexer, and to output data terminals of said fourth module; anda second buffer having input terminals coupled to output terminals of said fourth multiplexer, and output terminals coupled to said data bus.