Patent ID: 8357963
Filing Date: 2013-01-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a source line; a bit line; (m+1) word lines (m is a natural number greater than or equal to 2); a selection line; a first to an m-th memory cells connected in series between the source line and the bit line; and a selection transistor including a gate terminal which is electrically connected to the selection line, wherein each of the first to the m-th memory cells comprises: the second transistor includes an oxide semiconductor layer, a channel of the second transistor is formed in the oxide semiconductor layer, the source line is electrically connected to the first source terminal of the m-th memory cell through the selection transistor, the bit line is electrically connected to the second drain terminal of the first memory cell and the first drain terminal of the first memory cell, a k-th word line (k is a natural number greater than or equal to 1 and less than or equal to m) is electrically connected to the second gate terminal of a k-th memory cell, a (k+1)-th word line is electrically connected to one of terminals of the capacitor of the k-th memory cell, the second drain terminal of a j-th memory cell (j is a natural number greater than or equal to 2 and less than or equal to m) is electrically connected to the first gate terminal of a (j−1)-th memory cell, the second source terminal of the (j−1)-th memory cell, and the other of the terminals of the capacitor of the (j−1)-th memory cell, the first gate terminal of the m-th memory cell, the second source terminal of the m-th memory cell, and the other of the terminals of the capacitor of the m-th memory cell are electrically connected to one another, and the first drain terminal of the j-th memory cell is electrically connected to the first source terminal of the (j−1)-th memory cell.