Patent ID: 6043164
Filing Date: 2000-03-28
Classification: H01L

Abstract:
In an integrated circuit wafer including levels of integrated circuit material having a surface, a method of forming electrical interconnects from the surface to a plurality of interlevels in the integrated circuit material, comprising the steps of:a) forming a single bi-level resist profile over the surface, the resist profile having a plurality of thicknesses and openings, with one thickness an opening to form an interconnect line, and a second thickness an opening through the resist profile to reveal an integrated circuit material surface area to form a via, the opening for the interconnect line intersecting the opening for the via;b) removing integrated circuit material underlying the opening in the resist profile formed in step a);c) after Step b), removing a portion of the resist profile to form an opening revealing a second integrated circuit surface area; andd) removing integrated circuit material underlying the opening formed in step c), whereby integrated circuit material is removed to generally reproduce the shape of the overlying resist profile.