Patent ID: 6962827
Filing Date: 2005-11-08
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: collectively forming a plurality of semiconductor integrated circuits on a main surface of a substrate; forming a plurality of first test circuit formation regions provided correspondingly to said semiconductor integrated circuits, simultaneously with formation of said plurality of semiconductor integrated circuits, while providing an isolation margin region to be able to isolate said plurality of semiconductor integrated circuits and said plurality of first test circuit formation regions from each other, said step of forming said first test circuit formation regions including the step of forming a first self operational test circuit in such a region of said first test circuit formation region that faces an adjacent one of said semiconductor integrated circuits across said isolation margin region; performing an in-line test for a manufacturing process of said semiconductor integrated circuit by using a plurality of first test elements included in each of said first test circuit formation regions; generating and supplying a test signal to a corresponding semiconductor integrated circuit and determining, according to an output signal from said corresponding semiconductor integrated circuit, whether said corresponding semiconductor integrated circuit operates well by using a first self operational test circuit included in each of said first test circuit formation regions; and isolating said plurality of semiconductor integrated circuits into chips by cutting said isolation margin region.