Patent ID: 6555433
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A process comprising steps in the sequence as follows:forming a conductive sublayer in contact with a plurality of conductive plugs formed in a planarizing glass insulating layer, forming a a stack of silicon dioxide layers which are alternatingly doped with a dopant and undoped on the conductive sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack with the plurality of layers having a mold top, forming a mask over the stack of silicon dioxide layers, etching through the mask to form the stack of doped and undoped silicon dioxide layers into a plurality of molds, comprising capacitor-core-shaping cavities in the stack of silicon dioxide layers reaching down to the conductive sublayer at the bottom of the stack, differentially etching the silicon dioxide layers in the plurality of cavities forming undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stack into the cavities to complete the plurality of molds, depositing a conductive material into the cavities forming solid capacitor cores with counterpart cantilevered ribs with a complementary pattern to the plurality of molds and each capacitor core each having a top surface with no inner cavity, polishing the plurality of molds and the solid capacitor cores to remove the mold top and the top surface of the capacitor cores, removing the plurality of molds, and then, after removal of the molds, etching the sublayer to separate the monolithic capacitor cores from adjacent monolithic capacitor cores thereby exposing the planarizing glass insulating layer.