Patent ID: 6759316
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:providing a semiconductor chip having a top surface and a bottom surface opposite the top surface, wherein the top surface includes a circuit formation area and an electrode formation area, wherein the circuit formation area includes an integrated circuit, and wherein the electrode formation area includes a plurality of pad electrodes; forming a first insulation layer on an entirety of the circuit formation area; forming a first circuit pattern on the first insulation layer so as to overlap the entirety of the circuit formation area; electrically connecting the first circuit pattern to one of the pad electrodes; forming a second insulation layer on the first circuit pattern, the second insulation layer having a through hole for exposing the first circuit pattern; forming a plurality of second circuit patterns on the second insulation layer, electrically connecting each of the second circuit patterns to a respective one of the pad electrodes; forming a first external electrode on the first circuit pattern through the through hole; and forming a plurality of second external electrodes on the second insulation layer so as to electrically connect to one of the second circuit patterns, respectively.