Patent ID: 8681084
Filing Date: 2014-03-25
Classification: G09G

Abstract:
1. A semiconductor device comprising: a latch circuit that amplifies a voltage given by a voltage source via a pair of bit lines to a level required for a signal, and outputs the amplified signal via the pair of bit lines; the latch circuit constructed by cross-linking corresponding gates and drains of first and second MOS transistors between a first terminal and a second terminal, the first and second MOS transistor including, as channels, semiconductor layers having boundaries provided on insulating layers; a first voltage applying section connected to the first terminal and gives, between a gate and a source of the second MOS transistor, a first step waveform voltage not less than a threshold voltage of the second MOS transistor for a predetermined number of times; a second voltage applying section connected to the second terminal and gives, between a gate and a source of the first MOS transistor, a second step waveform voltage not less than a threshold voltage of the first MOS transistor for a predetermined number of times: a first switch that lies between one bit line of the pair of bit lines and the first terminal; and a second switch that lies between the other one bit line of the pair of bit lines and the second terminal; wherein the semiconductor device executes, when the first and second terminals are each disconnected from the pair of bit lines by the first and second switches, respectively, a first process in which the first voltage applying section gives, between the gate and the source of the second MOS transistor, the first step waveform voltage for the predetermined number of times, and the second voltage applying section then gives, between the gate and the source of the first MOS transistor, the second step waveform voltage for the predetermined number of times, subsequently, executes, when the first and second terminals are each connected to each bit line of the pair of bit lines by the first and second switches, respectively, a second process in which the voltage source gives the voltage to the first and second terminals of the latch circuit via the pair of bit lines, subsequently, executes a third process in which the latch circuit amplifies the given voltage to be a required signal, subsequently, executes a fourth process in which the latch circuit outputs the amplified signal via the pair of bit lines, and subsequently returns to the first process again and repeats the first to the fourth process.