Patent ID: 6529406
Filing Date: 2003-03-04
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a plurality of basic unit blocks arranged in a first direction, each basic unit block including: 1) a memory cell array having a plurality of memory cells arranged in a matrix, 2) a first selecting line, arranged in a second direction orthogonal with the first direction and configured to select a memory cell from the memory cells, 3) a plurality of first data lines arranged in the first direction, each of said first data lines transmitting data from said selected memory cell, and 4) sense amplifiers connected to said first data lines; second data lines, a number of which is smaller than a number of the plurality of the first data lines, formed in an upper layer of basic unit blocks of said plurality of basic unit blocks except a basic unit block which is positioned on one end, each of said second data lines being arranged in the first direction and being selectively connected to each of said first data lines; a first wiring arranged in an upper layer of the plurality of basic unit blocks, said first wiring being arranged in the first direction; and a second wiring arranged in an upper layer of the basic unit block of the plurality of basic unit blocks positioned on the one end, said second wiring being arranged in the second direction.