Patent ID: 7222263
Filing Date: 2007-05-22
Classification: G06F

Abstract:
1. A program-controlled unit, comprising: a plurality of cores for executing a program; a plurality of watchdog timers, each watchdog timer being configured to put one or more of the plurality of cores into a specific state if a specific condition is reached; on-chip debug resources, located on the same chip as the program-controlled unit and said plurality of cores, said on-chip debug resources including a plurality of on-chip debug module components, each on-chip debug module component connected to one of said plurality of cores for tracking and influencing operations proceeding within said one of said plurality of cores; said on-chip debug resources altering at least one setting that defines whether a particular one of said plurality of watchdog timers can reset a particular one of said plurality of cores; other components connected to at least one of said on-chip debug resources and at least one of said plurality of cores; and said on-chip debug resources influencing at least one of: