Patent ID: 8227867
Filing Date: 2012-07-24
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a semiconductor fin having a first sidewall, a second sidewall, a first end wall, a second end wall, a substantially horizontal top surface, and a substantially horizontal bottom surface contacting a top surface of an insulator layer located on a substrate, wherein said first and second sidewalls are substantially parallel to each other and substantially vertical, said first end wall is adjoined to one end of each of said first sidewall and said second sidewall, and said second end wall is adjoined to the other end of said first sidewall and said second sidewall and is substantially parallel to said first end wall; a gate dielectric that does not contact said substantially horizontal top surface, and contacts each of a portion of said first sidewall and a portion of said second sidewall between said substantially horizontal top surface and said top surface of said insulator layer; a stack of a body region and a semiconductor region located within said semiconductor fin and having an interface at said first end wall, wherein said body region is located within said semiconductor fin and has a doping of a first conductivity type and vertically abuts said insulator layer and contacts said gate dielectric, and said semiconductor region is located within said semiconductor fin and directly underneath a portion of said substantially horizontal top surface and an upper portion of said first end wall and above a horizontal surface of said body region, and has a doping of said first conductivity type at a dopant concentration greater than a dopant concentration of said body region; a first p-n junction that is located between said stack and a first source region having a doping of a second conductivity type that is the opposite of said first conductivity type, vertically extends from said substantially horizontal top surface to said top surface of said insulator layer, and laterally extends from said first sidewall to said first end wall; and a second p-n junction that is located between said stack and a second source region having a doping of said second conductivity type, vertically extends from said substantially horizontal top surface to said top surface of said insulator layer, and laterally extends from said second sidewall to said first end wall, wherein said first p-n junction and said second p-n junction are not contiguous to each other, and are laterally spaced from each other by said stack, wherein an entirety of said first sidewall and an entirety of said second sidewall that are located between a gate spacer and said substantially vertical end wall are surfaces of said first source region and said second source region.