Patent ID: 6424590
Filing Date: 2002-07-23
Classification: G11C

Abstract:
A semiconductor device, comprising:a plurality of address input terminals; a plurality of address input buffers provided in association with the plurality of address input terminals; a clock terminal which receives a clock signal therein; a plurality of memory cells each having a select terminal connected to each of word lines and a data input/output terminal connected to each of bit lines; and a control circuit which controls the operation of writing data into the memory cells and the operation of reading data from the memory cells in synchronism with the clock signal; and said control circuit provides instructions for a word line selecting operation based on a row address according to a bank active command, provides instructions for a data reading operation having specified each bit line bases a column address according to a read command, provides instructions for a data write operation having specified each bit line based on a column address according to a write command and provides instructions for the initialization of each word line according to a precharge command, and changes said address input buffer from an inactive state to an state after the reception of the bank active command, the read command or the write command and thereafter changes said address input buffer from the active state to the inactive state when writing for the elapse of a predetermined cycle period synchronized with the clock signal.