Patent ID: 6411140
Filing Date: 2002-06-25
Classification: G06F,G11C,H03K

Abstract:
An input path circuit for use in an integrated circuit, said input path circuit comprising:a first input path having a first input buffer for inputting a first signal selected from a group consisting of an address signal or a control path signal; a second input path for inputting a clock signal; a circuit connected to the first and second input paths for receiving signals therefrom, said circuit including a register and a decode unit coupled to said register, the output of said decode unit coupled to said register, said register operable upon receiving the clock signal to generate an output; and circuitry, within the first input buffer, for reducing skew between the input path delays, the circuitry having reduced current leakage and the circuitry not substantially affecting the relative delay of signals provided along the first and second input paths said circuitry including a first inverting stage having a pair of NMOS devices in series, a second inverting stage including an inverter, and a feedback path from an output of the inverter to an input of the inverter, with the feedback path including a PMOS device having a source connected to a power supply, a drain connected to the input of the inverter, and a gate connected to an output of the inverter.