Patent ID: 6762969
Filing Date: 2004-07-13
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit formed on a semiconductor substrate, comprising:a plurality of circuit modules; a first wiring which connects the plurality of circuit modules; a fuse circuit which has a plurality of nonvolatile memory cells respectively storing control information for defect relief, trimming of circuit characteristics or function switching with respect to the plurality of circuit modules and which allows memory information to be electrically read therefrom; a plurality of volatile register circuits which are respectively provided in association with the plurality, of circuit modules and store the control information therein; a second wiring for connecting the fuse circuit with the plurality of register circuits and transferring the control information; and a control circuit which controls application of an operating voltage to each of the nonvolatile memory cells to enable reading of memory information from the fuse circuit, controls a transfer of the control information read from the fuse circuit to each of the register circuits through the second wiring, and performs control for releasing application of the operating voltage to each of the nonvolatile memory cells after reading of the control information from the fuse circuit to the second wiring.