Patent ID: 9170878
Filing Date: 2015-10-27
Classification: G06F,G11C

Abstract:
1. A method for operating a Dynamic Random Access Memory (DRAM) device, the method comprising: receiving in a first memory buffer in a memory module comprising a first Dual Inline Memory Module (DIMM) hosted by a computing system, a first request to store a data word; in response to the first request, the first memory buffer striping the data word across the first DIMM and a second Dual Inline Memory Module (DIMM), such that loading on any byte lane of the first DIMM is limited to two electrical loads; receiving in the first memory buffer a second request for the data word stored in part in a Random Access Memory (RAM) of the memory module from a host controller of the computing system, the request comprising address signals; the first memory buffer decoding the address signals and initiating a first rank decode function in response to a single chip select signal received from host controller; a second memory buffer of the second DIMM initiating a second rank decode function in response to the single chip select signal; receiving with the first memory buffer, part of the data word associated with a second RAM of the second DIMM, in response to the request; formatting with the first memory buffer, the data word into a scrambled data word in response to a pseudo-random process; and initiating with the memory buffer, transfer of the scrambled data word into an interface device.