Patent ID: 6934732
Filing Date: 2005-08-23
Classification: G06F

Abstract:
1. A correlator system used to calculate a correlation between a short binary sequence and a signal sequence, said correlator comprising: a first shift register operative to receive said signal sequence, wherein said first shift register comprises a plurality of first register blocks and each of said first register blocks is operative to store a successive value of said signal sequence; a second shift register comprising a plurality of second register blocks, wherein each of said second register blocks is operative to store a successive value of said short binary sequence; a first subtractor operative to calculate a difference between a next value of said signal sequence and a last value of said signal sequence; a first adder operative to calculate the sum of the result of said first subtractor calculation and an output of a sum holding register, wherein said sum holding register is operative to store the output of said first adder; a second adder operative to calculate the sum of a selected one of said successive values of said signal sequence and the output of an accumulator, wherein said accumulator is operative to accumulate successive results of said second adder; a second subtractor operative to calculate the difference between the output of said sum holding register and the output of said accumulator.