Patent ID: 6232203
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A process for silicon nitride spacer formation as part of shallow trench isolation (STI) formation in a device-containing semiconductor substrate, comprising steps of:forming a pad oxide layer on the substrate;depositing a layer of silicon nitride on the pad oxide layer;patterning the silicon nitride and pad oxide layers to form an etching mask having openings with a tapered or a stepped side wall profile;etching the semiconductor substrate exposed by the etching mask openings to form trenches in the semiconductor substrate;overfilling the trenches and the profiled silicon nitride mask openings with a dielectric material;planarizing the surfaces of the dielectric material and the silicon nitride layer;forming silicon nitride spacers, conformal to the stepped or tapered dielectric material, by anisotropically etching the silicon nitride layer away from the surface of the pad oxide layer;removing the pad oxide layer and at least a portion of the dielectric material, wherein the silicon nitride spacers protect the corners of the dielectric material in the trenches.