Patent ID: 8176352
Filing Date: 2012-05-08
Classification: G06F

Abstract:
1. A method, comprising: receiving a first clock signal at a first synchronous logic module of a device; receiving a second clock signal at a second synchronous logic module of the device; asserting an enable signal at a first time based on a first transition of the first clock signal substantially corresponding to a second transition of the second clock signal; transferring data from the first synchronous logic module to the second synchronous logic module in response to assertion of the enable signal; asserting the enable signal at a second time based on a third transition of the first clock signal substantially corresponding to a fourth transition of the second clock signal; and transferring data from the first synchronous logic module to the second synchronous logic module in response to assertion of the enable signal at the second time, a frequency relationship between the first clock signal and the second clock signal at the first time different from a frequency relationship between the first clock signal and the second clock signal at the second time.