Patent ID: 6754856
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A computer system for executing a sequence of instructions in at least one pipelined execution unit, said system including instruction fetch circuitry for obtaining instructions from a program memory in accordance with a program count, instruction dispatch circuitry for dispatching fetched instructions to said pipelined execution unit, data memory for use in load and store operations, data memory access circuitry for effecting data memory access operations in response to execution of instructions in said pipelined execution unit, and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.