Patent ID: 6087690
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A single polysilicon DRAM cell comprising:a deep n-well in a silicon substrate;a p-well within said deep n-well;a gate structure formed onto the surface of said silicon substrate and atop said deep n-well said gate structure positioned such that said p-well terminates underneath said gate structure, said gate structure being a stack of a thin gate oxide layer and a conductive layer;a n+ region within said p-well and adjacent to a sidewall of said gate structure; anda conductive reset p+ junction attached to said p-well, said conductive reset p+ junction attached to said p-well through a transistor switch;wherein said p-well is adapted to store a body bias voltage that serves to modulate the threshold voltage of a n-MOS transistor formed by said n+ region, said p-well, said deep n-well, and said gate structure, said conductive reset p+ junction selectively biasing said p-well to a predetermined voltage through said transistor switch.