Patent ID: 9159403
Filing Date: 2015-10-13
Classification: G11C

Abstract:
1. A control circuit of SRAM, comprising: a memory array having a plurality of memory cells, each said memory cell having a plurality of transistors: a word-line driver for activating a word-line of said memory array for cell storage data accessing; a boost circuit coupled to said word-line driver and a first operating voltage, wherein the boost circuit provides a higher voltage source than the first operating voltage by boosting the first operating voltage to a second operating voltage; and a voltage level detecting circuit coupled with said first operating voltage and a detecting-trigger signal line, a predetermined voltage and said first operating voltage controlling the operation of said boost circuit, wherein: the voltage level detecting circuit comprises a reference unit coupled with the first operating voltage and a detecting unit, the voltage level detecting circuit further comprises a first inverter and a first transistor, a first inverter is coupled with said detecting-trigger signal line, a first transistor is coupled with the output terminal of said first inverter, a ground terminal, and said detecting unit, said detecting unit comprises a second inverter and a third inverter, and said detecting unit is coupled with said reference unit, said detecting-trigger signal line, and a fourth inverter, wherein if said first operating voltage is greater than said predetermined voltage, said voltage level detecting circuit controls said boost circuit for stopping a boost treatment of said first operating voltage, and if said first operating voltage is smaller than said predetermined voltage, said voltage level detecting circuit activates said boost circuit, wherein said reference unit includes a resistor connected between a source of said first operating voltage and a second transistor, and a first node being located between said resistor and said second transistor, said second transistor being connected to said first inverter and said first transistor, and said detecting unit including a second node located between a first transistor pair and a second transistor pair, wherein a first node voltage of said first node equals a second node voltage of said second node when said detecting-trigger signal line is low, and wherein said detecting unit latches a detecting unit output of said detecting unit when said detecting-trigger signal line becomes high.