Patent ID: 8250386
Filing Date: 2012-08-21
Classification: G06F,G11B,Y02D

Abstract:
1. A processor having reduced power consumption, comprising: an analog front end operative to receive an analog signal supplied to the processor and to generate a digital signal indicative of the analog signal; a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end; a buffer coupled between the analog front end and the digital back end; and a controller coupled to the buffer and operative to turn on at least a portion of the digital back end when the buffer is full and to turn off at least the portion of the digital back end when a content of the buffer is below a prescribed threshold where the buffer is not full; wherein in a first mode of operation, the digital back end operates at a substantially same data rate as the analog front end and the buffer is bypassed, and in a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.