Patent ID: 8947940
Filing Date: 2015-02-03
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: an array of memory cells, wherein each of the memory cells includes a tunnel dielectric, a well region including a first current electrode, a second current electrode, and a channel region between the first current electrode and the second current electrode, a floating gate wherein the tunnel dielectric is over the channel region and the floating gate is over the tunnel dielectric, an interface dielectric over the floating gate, and a control gate over the interface dielectric; and a controller coupled to the memory cells, wherein the controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric, wherein the first voltage is sufficient to draw at least some of the trapped electrons out of the tunnel dielectric.