Patent ID: 6590798
Filing Date: 2003-07-08
Classification: G11C

Abstract:
A memory device, comprising:a ferroelectric data cell connected to one of first and second complimentary data bitlines, the ferroelectric data cell comprising a ferroelectric capacitor and a MOS transistor operable to selectively connect the ferroelectric capacitor between a plateline and one of the complimentary data bitlines according to a corresponding wordline, the ferroelectric data cell being operable to store a data cell data bit associated with a corresponding data word; a data sense amp circuit comprising first and second terminals, the data sense amp circuit being operable to sense a differential voltage at the first and second terminals; and a data bitline select circuit connected to the complimentary data bitlines and to the data sense amp, the data bitline select circuit being operable to connect the first terminal with the first complimentary bitline and the second terminal with the second complimentary bitline during a read operation and to connect the first terminal with the second complimentary bitline and the second terminal with the first complimentary bitline during a restore operation.