Patent ID: 8694710
Filing Date: 2014-04-08
Classification: G06F

Abstract:
1. A method of conversion by at least one interface circuit connected between a first bus comprising at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling reading or writing, originating from the master circuit, wherein the speculative read command triggers a read operation by the slave circuit, independent of the state of the bit for controlling reading or writing, and transmission of speculative read data from the slave circuit to the interface circuit, wherein the speculative read data is transmitted by the interface circuit to the master circuit when the state of the bit for controlling reading or writing indicates reading, and otherwise the speculative read data is discarded.