Patent ID: 6272604
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A contingent response arrangement for a first processor which shares a pipelined address bus with at least one other processor, the contingent response arrangement comprising:(a) a pending operation unit for identifying a matched operation, the matched operation comprising a first processor operation which is pending on the pipelined address bus and which specifies an address which matches a snoop address;(b) a snoop pipeline having a plurality of pipeline stages, each pipeline stage including a contingent response flag location and an identifier location, each contingent response flag location for storing a contingent response flag and each identifier location for storing an identifier associated with a particular matched operation; and(c) a contingent response flag control arrangement associated with the snoop pipeline, the contingent response flag control arrangement (i) for setting the response flag in one snoop pipeline stage in response to the matched operation identified by the pending operation unit and (ii) for clearing the response flag of any critical snoop pipeline stage which contains an identifier which matches an identifier for an unsuccessful finishing operation from the first processor.