Patent ID: 6407586
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A fusible link configuration in or on integrated circuits, comprising:a memory field segment; at least one bank of fusible links defining a total number of said fusible links and configured beside and associated with said memory field segment, said at least one bank of said fusible links divided into units of said fusible links, each one of said units of said fusible links including a smaller number of said fusible links than said total number of said fusible links, said units of said fusible links being grouped to define a width of said at least one bank of said fusible links and being grouped such that at least some of said fusible links are disposed adjacently in a direction that is transverse with respect to a direction of said width of said at least one bank of said fusible links; and an evaluation logic unit electrically connected to said fusible links for determining whether one or more of said fusible links is severed.