Patent ID: 6100141
Filing Date: 2000-08-08
Classification: H01L,Y10S

Abstract:
A dual gate oxide process for forming a gate oxide layer of a transistor in an electrostatic discharge (ESD) protection circuit, the dual date oxide process comprising:providing a substrate consisting of a region of an internal circuit and a region of the ESD protection circuit;forming a pad oxide layer on the substrate;forming a silicon nitride layer on the pad oxide layer;patterning the silicon nitride layer and the pad oxide layer to exposes a portion of the substrate;performing an oxidation process to form an isolation, wherein the isolation defines an active region of the internal circuit within the region of the internal circuit, and an active region of the ESD protection circuit within the region of the ESD protection circuit;removing the silicon nitride layer and the pad oxide layer located within the region of the ESD protection circuit;performing an oxidation process to form a thick gate oxide layer on the substrate within the active region of the ESD protection circuit;removing the silicon nitride layer and the pad oxide layer located within the region of the internal circuit;performing an oxidation process to form a thin gate oxide layer on the substrate within the active region of the internal circuit;forming a patterned conducting layer on the substrate;performing an implantation process to form a plurality of source/drain regions on the substrate within the region of the internal circuit, wherein the implantation process does not penetrate through the thick gate oxide layer;forming spacers on the patterned conducting layer;etching a portion of the thick gate oxide layer and spacers by using the substrate as an etching end point within the region of the ESD protection circuit; andperforming an implantation process to form a plurality of sources/drain regions on the substrate within the region of the ESD protection circuit.