Patent ID: 6925569
Filing Date: 2005-08-02
Classification: G06F

Abstract:
1. A secured microprocessor device comprising: a microprocessor, an address bus, and a memory array connected to said microprocessor by said address bus, said memory array divided into a plurality of memory zones; and a rights allocation system cooperating with said microprocessor and said memory array for allocating, to programs executable by said microprocessor, permanent rights of access to at least one memory zone, said rights allocation system including a rights allocation table having first and second inputs and receiving, at the first input, an identification code of a program or of a sub-program and, at the second input, an identification code of memory zones designated by a current address on said address bus; said rights allocation system being arranged to confer, on a sub-program shared by at least two programs, temporary rights of access to at least one memory zone when the sub-program is called by one of the at least two programs, and said rights allocation system comprising first input means for applying, to the first input of the rights allocation table, during execution of the sub-program, an identification code of the program having called the sub-program.