Patent ID: 6764884
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of forming a gate in a FinFET device, comprising:depositing a first dielectric layer over a silicon on insulator (SOI) wafer, the SOI wafer comprising a silicon layer on an insulating layer; forming a resist mask over a portion of the first dielectric layer; etching portions of the first dielectric layer and silicon layer not covered by the resist mask to form a fin and a dielectric cap covering a top surface of the fin; depositing a gate layer over the dielectric cap; depositing a second dielectric layer over the gate layer; etching the gate layer and second dielectric layer to form a gate structure; forming sidewall spacers adjacent the gate structure; forming a third dielectric layer over the FinFET device; planarizing the third dielectric layer to expose a top surface of the second dielectric layer; removing the second dielectric layer and the gate layer in the gate structure; etching the fin to reduce a width of the fin in a channel region of the semiconductor device; and depositing a gate material to replace the removed gate layer.