Patent ID: 6187643
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method for use in the fabrication of a circuit on a substrate, comprising the steps of:after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes;implanting source/drain extensions of p-type devices through openings in a first mask;implanting source/drain regions of the p-type devices through the openings in said first mask;implanting source/drain extensions of n-type devices through openings in a second mask;implanting source/drain regions of the n-type devices through the openings in said second mask,the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, andthe steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; andimplanting an n-well for the p-type devices through the openings in said first mask, implanting a channel stop for the p-type devices through the openings in said first mask, and implanting a V.sub.tp threshold adjust for the p-type devices through the openings in said first mask, the steps of implanting said n-well, said channel stop and said V.sub.tp threshold adjust for the p-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.