Patent ID: 8418180
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A method in a simultaneous multi-threading (SMT) microprocessor that executes multiple threads concurrently during each clock cycle, said method comprising: assigning a clock cycle priority to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles, wherein said clock cycle priority assignment is temporary and designed to change automatically after said expected number of clock cycles have been executed; assigning said clock cycle priority according to a standard selection definition during said standard selection state by selecting said first thread to be a primary thread and selecting said second thread to be a secondary thread for processing during said standard selection state; determining whether a condition exists that requires overriding said standard selection definition; in response to determining that said condition exists, executing an override state for an override period of time, wherein said second thread is selected to be said primary thread and said first thread is selected to be said secondary thread for processing during said override state, wherein said override state lasts longer than said selection state, and further wherein said second thread is processed and accomplishes work during said override period of time; forcing said override state to be executed for said override period of time, wherein said override period of time equals said expected number of clock cycles plus a forced predefined number of a plurality of consecutive clock cycles; counting said forced predefined number of the plurality of consecutive clock cycles that were executed during said override period of time; granting said expected number of clock cycles plus said forced predefined number of said plurality of consecutive clock cycles to said first thread a next time said first thread becomes said primary thread, wherein said expected number of clock cycles are consecutive to said forced predefined number of the plurality of consecutive clock cycles, and wherein said expected number of clock cycles is less than the combination of said expected number of clock cycles and said forced predefined number of the plurality of consecutive clock cycles; assigning a first priority level to said first thread; assigning a second priority level to said second thread, wherein said first priority level is higher than said second priority level, wherein said first thread is granted a larger ratio of clock cycles as compared to said second thread during processing of said first and second threads, wherein said first thread is granted a first number of clock cycles and said second thread is granted a second number of clock cycles; processing said first thread as said primary thread; preventing said second thread from processing for a particular number of clock cycles; assigning said first thread as said secondary thread and said second thread as said primary thread; attempting to process said second thread as said primary thread; preventing, by said first thread, said second thread from processing; forcing said second thread to remain as said primary thread regardless of a wait number of clock cycles that are executed while said second thread is prevented from processing; and in response to said first thread no longer preventing said second thread from processing, processing said second thread for a total number of clock cycles that equal said second number of clock cycles plus said wait number of clock cycles.