Patent ID: 6687151
Filing Date: 2004-02-03
Classification: G05F

Abstract:
A voltage generation circuit for selectively generating a low voltage lower than a first power supply voltage and a high voltage higher than a second power supply voltage on an output node on the basis of the first and second power supply voltages, the second power supply voltage being higher than the first power supply voltage, the voltage generation circuit comprising:a first PMOS transistor, having a current path and a control gate, a first end of the current path being connected to the output node, a back gate thereof being connected to a second end of the current path; a first NMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the second end of the current path of the first PMOS transistor, a second end of the current path thereof being connected to the first power supply voltage; a first capacitor, having first and second electrodes, the first electrode being connected to the output node; a second PMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the output node, a back gate thereof being connected to a second end of the current path thereof, the control gate thereof being connected to the first power supply voltage; a second NMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the second end of the current path of the second PMOS transistor; and a control circuit configured to: raise the second electrode of the first capacitor to the second power supply voltage to step up the output node to the high voltage from a first state where the first and second NMOS transistors are OFF and where the output node and the second electrode of the first capacitor are at the second and first power supply voltages, respectively; and lower the second electrode of the first capacitor to the first power supply voltage to step down the output node to the low voltage from a second state where the first and second NMOS transistors are OFF, where a voltage between the control gate and the second end of the current path of each of the first and second PMOS transistors is equal to an absolute value of a threshold voltage thereof, and where the output node and the second electrode of the first capacitor are at the first and second power supply voltages, respectively.