Patent ID: 7488648
Filing Date: 2009-02-10
Classification: G11C,H01L

Abstract:
1. A method of forming a scalable two-transistor memory (STTM) device, comprising: forming a vertical transistor structure including a storage node on a semiconductor substrate and a tunnel junction structure on the storage node; forming a metal layer on a surface of the substrate adjacent respective opposite sides of the storage node; performing a silicidation process on the substrate including the metal layer on the surface thereof to form spaced apart metal silicide source/drain regions without prior formation of implanted diffusion regions in the substrate adjacent the respective opposite sides of the storage node to define a planar transistor including the storage node of the vertical transistor structure as a floating gate electrode that controls a channel region of the planar transistor; removing unreacted portions of the metal layer from the metal silicide source/drain regions at the surface of the substrate after performing the silicidation process; and then forming a control gate electrode on opposing sidewalls of the tunnel junction structure to define a vertical transistor, wherein the control gate electrode controls a channel region of the vertical transistor.