Patent ID: 6288614
Filing Date: 2001-09-11
Classification: H03L

Abstract:
A phase-locked loop for generating an output signal of a predetermined frequency and a locked phase relative to a reference signal of a predetermined reference frequency, comprising:a) a first divider for frequency dividing said reference signal;b) a second divider for frequency dividing said output signal;c) a phase detection means for detecting a phase deviation between said divided reference signal and said divided output signal and for outputting a corresponding phase deviation signal;d) an oscillator means for outputting said output signal with a frequency corresponding to said phase deviation indicated by said phase deviation signal; whereine) said first divider has two different selectable frequency division factors a and b;f) said second divider has two different selectable frequency division factors c and d; andg) control means are providedg1) for respectively selecting a frequency division factor pair consisting of frequency division factors a and c or a frequency division factor pair consisting of frequency division factors b and d, respectively of said first and second divider,g2) for switching between said two different frequency division factor pairs a,c and b,d according to a predetermined switching pattern of a predetermined length; characterized in thath) a reference division factor p is defined for said first divider and a reference division factor q is defined for said second divider, wherein the following equation (1) is satisfiedf2=p/q*f1 (1)with f2 being said output frequency and f1 being said reference frequency, p, q, a, b, c, d being natural numbers, p and q being without common dividers, and p, q, a, b, c, d are selected such that the following relations are satisfied: p<q, c<a, d<b and a, b, c, d<p and a, b, c, d<q; and whereini) in said switching pattern a number x of divisions using a selection of said first pair equalsx=(ap-cq)/(ad-bc) (10)and a number y of divisions using a selection of said second pair equalsy=(dq-bp)/(ad-bc) (11)wherein x, y both are greater than 0.