Patent ID: 6346837
Filing Date: 2002-02-12
Classification: H03L

Abstract:
A digital delay-locked loop circuit, comprising:a variable delay circuit for delaying an input signal and generating an output signal, said variable delay circuit including a first variable delay circuit for at least indirectly delaying said input signal with a first delay time changed at first intervals and a second variable delay circuit, connected in series to said first variable delay circuit, for at least indirectly delaying said input signal with a second delay time changed at second intervals smaller than said first intervals; a phase comparator for comparing a phase of a feedback signal derived from said output signal with a phase of a reference signal; and a counter circuit, connected between said phase comparator and said first and second variable delay circuits, for controlling said first and second delay times in accordance with a difference in phase between said feedback signal and said reference signal so that said difference in phase is brought close to zero, wherein said phase comparator includes: a first phase comparator for comparing the phase of said feedback signal with the phase of said reference signal when said difference in phase is larger than a predetermined value; and a second phase comparator for comparing the phase of said feedback signal with the phase of said reference signal when said difference in phase is not larger than said predetermined value, wherein said counter circuit comprises: a first ring counter with a decoding function, connected between said first phase comparator and said first delay circuit, for changing said first delay time in accordance with an output of said first phase comparator; and a second ring counter with a decoding function, connected between said second phase comparator and said second delay circuit, for changing said second delay time in accordance with an output of said second phase comparator, and wherein said phase comparator further comprises: a first pulse selection circuit for receiving said reference signal, numbering pulses of said reference signal with reference signal pulse numbers and generating the pulses of said reference signal having a predetermined number of said reference signal pulse numbers; and a second pulse selection circuit for receiving said feedback signal, numbering pulses of said feedback signal with feedback signal pulse numbers and generating the pulses of said feedback signal, including pulses of said feedback signal with said predetermined number of said feedback signal pulse numbers, said first phase comparator being connected to said first and second pulse selection circuits for comparing the pulses of said feedback signal other than the pulses of said feedback signal having said predetermined number with the pulses of said reference signal having said predetermined number to generate a first phase comparison signal, said first phase comparison signal being transmitted to said counter circuit, said second phase comparator being connected to said first and second pulse selection circuits for comparing the pulses of said feedback signal having said predetermined number with the pulses of said reference signal having said predetermined number to generate a second phase comparison signal, said second phase comparison signal being transmitted to said counter circuit.