Patent ID: 8008125
Filing Date: 2011-08-30
Classification: H01L,H05K

Abstract:
1. An embedded chip package comprising: a plurality of polymer laminate re-distribution layers joined together in a vertical direction to form a lamination stack, wherein each polymer laminate re-distribution layer includes a plurality of vias formed therein; a first chip embedded in the lamination stack and comprising a plurality of chip pads; a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, the second chip comprising a plurality of chip pads; an input/output (I/O) system positioned on an outer-most polymer laminate re-distribution layer of the lamination stack; and a plurality of metal interconnects electrically coupled to the I/O system and configured to electrically connect the first chip and the second chip to the I/O system, wherein each of the plurality of metal interconnects extends through a respective via and is metalized directly to one of a metal interconnect on a neighboring polymer laminate re-distribution layer and a chip pad on the first or second chip.