Patent ID: 6738880
Filing Date: 2004-05-18
Classification: G11C

Abstract:
A buffer for varying data access speed, coupled to a high bit memory module, a low bit memory module and a control chip set, wherein the high bit memory module and the low bit memory module receive a memory clock signal, the buffer comprising:a memory data input/output interface, coupled to the high bit memory module and the low bit memory module; a control chip set data input/output interface, coupled to the control chip set; a first first-in-first-out memory, coupled to the control chip set data input/output interface and the memory data input/output interface; a second first-in-first-out memory, coupled to the control chip set data input/output interface and the memory data input/output interface; and a control signal generator, coupled to the memory data input/output interface, the control chip set data input/output interface, the first first-in-first-out memory, the second first-in-first-out memory and the control chip set, the control signal generator receiving a buffer clock signal and a multiple buffer clock signal, the buffer clock signal having a frequency equal to the frequency of the memory clock signal, and the multiple buffer clock signal having a frequency which is a predetermined multiple of the frequency of the memory clock signal, the control signal generator decoding a read/write instruction from the control chip set and generating a read/write control signal; wherein the control chip set data input/output interface has a data transmission rate which is the predetermined multiple of a data transmission rate of the memory data input/output interface, the first and second first-in-first-out memories function as temporary storage units between different data transmission rates, the read/write control signal controls the first and the second first-in-first-out memories, so that the first-in-first-out memory receives a write data from the control chip set and outputs the write data to the memory data input/output interface, and the second first-in-first-out memory receives a read data from the memory data input/output interface and outputs the read data to the control chip set data input/output interface.