Patent ID: 7642812
Filing Date: 2010-01-05
Classification: G06F,H03K

Abstract:
1. A clock signal network in an electronic device comprising: a divided clock signal source coupled to derive a divided clock signal from a full-speed clock signal; a first register in a series of registers, the first register including a data input, a clock input, and a data output wherein the data input is coupled to the divided clock signal source, the clock input is coupled to a source of the full-speed clock signal and the data output is coupled to a data input of a next register in the series; and succeeding registers of the series, a succeeding (and non-final) register including a data input, a clock input, and a data output wherein the data input is coupled to the data output of a prior register in the series, the clock input is coupled to the source of the full-speed clock signal and the data output is coupled to a data input of a next register in the series; wherein: the data input of the first register in the series is coupled to the divided clock signal source via an inverter and the data output of the first register is coupled to an input of a next register in the series via an inverter; the data output of a succeeding (and non-final) register in the series is coupled to the data input of a next register in the series via an inverter; and data outputs of registers in the series are coupled to divided clock signal destination circuitry.