Patent ID: 6222406
Filing Date: 2001-04-24
Classification: G11C,H03K

Abstract:
A semiconductor integrated circuit device comprising:a delay circuit including,M signal lines for receiving a first input signal to successively-delayed M (M=2, 3, 4, . . . )th input signals therein; andM logic gate circuit groups extending from a first logic gate circuit group corresponding to the first input signal to an Mth logic gate circuit group corresponding to the Mth input signal, andwherein said each individual logic gate circuit groups have N logic gate circuits extending from a first logic gate circuit to an N (N=3, 4, 5, . . . )th logic gate circuit, said each logic gate circuit having a first input terminal, a second input terminal and an output terminal,coupling elements are provided between the first and second input terminals of the logic gate circuits respectively,said first to Nth logic gate circuits in said each logic gate circuit group are tandem-connected to the output terminals through the first input terminals respectively,said M signal lines are connected to the first input terminals of the first logic gate circuits in their corresponding logic gate circuit groups,first input terminals of L (L=1, 2, 3, . . . )th logic gate circuits in each of said first logic gate circuit group to M-1th logic gate circuit group are connected to second input terminals of Lth logic gate circuits in the next logic gate circuit group, wherein the Lth logic gate circuits are ones of said N logic gate circuits,first input terminals of predetermined logic gate circuits in said Mth logic gate circuit group are connected to second input terminals of predetermined logic gate circuits in said first logic gate circuit group, and successively-delayed output signals are respectively obtained from the output terminals of a plurality of the Nth logic gate circuits.