Patent ID: 9040951
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A memory structure comprising: a conductive structure; a first dielectric layer over the conductive structure, the first dielectric layer having a first top surface and being substantially oxygen-free; a first opening in the first dielectric layer extending to an area of the conductive structure, the first opening having an interior sidewall surface; a first electrode structure having a first portion and an integrally connected second portion, wherein the first portion is over the exposed area of the conductive structure, and the second portion extends upwardly along the interior sidewall surface of the first opening; a resistance variable layer disposed over the first electrode structure; a second electrode structure over the resistance variable layer, the second electrode structure having a third portion and an integrally connected fourth portion, wherein the third portion has a second top surface below the first top surface of the first dielectric layer, and the fourth portion extends upwardly along the resistance variable layer; a second opening defined by the third portion and the fourth portion of the second electrode structure; and at least a part of a second dielectric layer disposed in the second opening, the second dielectric layer being substantially oxygen-free.