Patent ID: 7365751
Filing Date: 2008-04-29
Classification: G06T

Abstract:
1. A texture processor comprising: first, second, third and fourth texture memories for storing texture data; a memory write section for controlling writing of supplied texture data in the first through fourth texture memories; a memory read section for controlling reading of texture data at four points close to texture coordinates from the first through fourth texture memories; and a bilinear filtering calculating section for performing bilinear filtering calculation using the texture data at four points read out from the first through fourth texture memories by the memory read section, wherein in a single write operation, the memory write section writes texture data in a number capable of being transferred at a time and being written in one address, in one of the first through fourth texture memories, and if V coordinate of texture data to be written is an even number, the texture data is written in the first, second, third and fourth texture memories in this order whereas if the V coordinate is an odd number, the texture data is written in the third, fourth, first and second texture memories in this order, wherein the memory write section comprises: a control counter for generating a write count value; and a write enable generator for generating write enable for the first through fourth texture memories respectively, by determining whether the V coordinate of texture data to be written is an even number or an odd number based on a number of bits per pixel and a width of the texture data and the write count value generated by the control counter.