Patent ID: 8000138
Filing Date: 2011-08-16
Classification: G11C

Abstract:
1. A memory device, comprising: memory circuit fabricated on a substrate die and including at least one memory bank including a plurality of two-terminal memory arrays fabricated directly above and in contact with the substrate die, the plurality of two-terminal memory arrays are electrically coupled with the memory circuitry and wherein the plurality of memory arrays are non-volatile so that stored data is retained in the absence of power; an embedded controller fabricated on the substrate die with the memory circuitry and operative to control which data access requests received by the input port are passed through the bus to the at least one memory bank and which data access requests received by the incoming bus logic are passed through to the bus to the output port; and a controller enable node coupled with the embedded controller and operative to allow internal control of the incoming bus logic by the embedded controller when enabled and to allow external control of the incoming bus logic when disabled.