Patent ID: 6794225
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A method for interconnecting electronic components, comprising:providing an array of spaced-apart microelectronic dice interconnected with a carrier substrate panel having a surface suitable for underfill material wetting and capillary filling, the array patterned to define an inter-die surface of the carrier substrate panel not covered by a microelectronic die; exposing the inter-die surface to a treatment suitable to reduce surface free energy of the inter-die surface to below that of an underfill material; dispensing the underfill material to the space between the microelectronic die and carrier substrate panel; and applying a layer of mold compound having a surface free energy below that of the inter-die surface to cover and encapsulate the array of spaced-apart microelectronic dice and adhering the mold compound to the inter-die surface.