Patent ID: 7653853
Filing Date: 2010-01-26
Classification: G01R

Abstract:
1. A test circuit in an integrated circuit, comprising: a test pattern generator to provide a test pattern; a reference circuit including a first sequential circuit coupled in series with a second sequential circuit; programmable interconnects for selectively coupling a circuit under test into and out of the test circuit, the circuit under test having non-sequential logic coupled in series between a source sequential circuit and a destination sequential circuit; the source sequential circuit and the first sequential circuit coupled to the test pattern generator to receive the test pattern; a comparison circuit coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit; the first sequential circuit, the second sequential circuit, the source sequential circuit, and the destination sequential circuit clocked responsive to a test clock signal; the comparison circuit configured to compare the first output with the second output to provide a signature output; and the signature output indicating whether the test data passes through the circuit under test within a cycle of the test clock signal.