Patent ID: 7868648
Filing Date: 2011-01-11
Classification: G11C,H03K

Abstract:
1. An on-die termination (ODT) circuit, comprising: an ODT synchronous buffer configured to receive a first clock signal delay-locked to an external clock signal and configured to generate a synchronous ODT command from an external ODT command in synchronization with the first clock signal; and an ODT gate configured to receive a second clock signal delay-locked to the external clock signal and the synchronous ODT command and configured to generate signals for controlling the ODT based on the second clock signal and the synchronous ODT command, wherein the ODT synchronous buffer includes, the delay unit is configured generate a first delayed clock signal of the plurality of delayed clock signals by delaying the first clock signal, a latch unit configured to latch the external ODT command in response to the first delayed clock signal and output the latched external ODT command as the synchronous ODT command, the delay unit includes, the latch unit includes,