Patent ID: 7371592
Filing Date: 2008-05-13
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line on a substrate; forming a first insulating layer on the gate line; forming a semiconductor layer on the first insulating layer; forming a data line, a drain electrode, and a storage capacitor conductor on the semiconductor layer; depositing a second insulating layer on the data line, the drain electrode, and the storage capacitor conductor; forming a photoresist including a first portion and a second portion to be thinner than the first portion on the second insulating layer by exposing it to light through a photo mask and developing; etching the second and first insulating layers using the photoresist as a mask to expose portions of the drain electrode and the storage capacitor conductor and to leave a first portion of the second insulating layer under the second portion of the photoresist; removing the second portion of the photoresist; depositing a conductive film; and removing the second portion of the photoresist to form a pixel electrode connected to the drain electrode and the storage capacitor conductor, wherein the photo mask include a light blocking area, a transmitting area, and a translucent area, and wherein the translucent area includes a plurality of light blocking portions having a plurality of areas at which amounts of light blocked are different from each other.