Patent ID: 6081558
Filing Date: 2000-06-27
Classification: H03F,H03G

Abstract:
A receiver circuit, the circuit comprising:an input terminal configured to receive an input data current signal;an output terminal;an input amplifier having input, output and gain control terminals, the input terminal of the input amplifier being coupled to the input terminal of the receiver circuit, and wherein the input amplifier is configured to receive a gain value of the input amplifier, and further wherein the input amplifier is a current mode device which has an inverse relationship between the gain of the input amplifier and the gain control signal;an automatic gain control circuit having input and output terminals, the input terminal being coupled to the output terminal of the input amplifier and the output terminal being coupled to the gain control terminal of the input amplifier, wherein the automatic gain control circuit is configured to generate the gain control signal;a comparator having first and second input terminals and an output terminal, the first input terminal being coupled to the output terminal of the input amplifier, the second input terminal being configured to receive a detect threshold voltage and the output terminal of the comparator being coupled to the output terminal of the receiver circuit; andan offset cancelling circuit having input and output terminals, the input terminal of the offset cancelling circuit being coupled to the output terminal of the input amplifier and the output terminal being coupled to the input terminal of the input amplifier, wherein the offset cancelling circuit is configured to generate a DC offset current; andwherein the input amplifier includes:a first diode having anode and cathode terminals, the anode terminal being coupled to the output terminal of the offset cancelling circuit and cathode terminal being coupled to the input terminal of the input amplifier;a first current source having first and second current terminals and a control terminal, the first current terminal being coupled to the input terminal of the input amplifier, the second current terminal being coupled to a ground potential terminal, and the control terminal of the first current source being coupled to the gain control terminal of the input amplifier;a second diode having anode and cathode terminals, the anode terminal of the second diode being coupled to the output terminal of the offset cancelling circuit;a second current source having first and second current terminals and a control terminal, the first current terminal of the second current source being coupled to the cathode terminal of the second diode, the second current terminal of the second current source being coupled to the ground potential terminal, and the control terminal of the second current source being coupled to the gain control terminal of the input amplifier;a constant current source having first and second current terminals, the second current terminal of the constant current source being coupled to the ground potential terminal;a first transistor having emitter, collector and base terminals, the emitter terminal of the first transistor being coupled to the first current terminal of the constant current source and the base terminal of the first transistor being coupled to the first current terminal of the second current source;a second transistor having emitter, collector and base terminals, the emitter terminal of the second transistor being coupled to the first current terminal of the constant current source and the base terminal of the second transistor being coupled to the first current terminal of the first current source; anda differential transconductance circuit having first and second input terminals and an output terminal, the first input terminal of the differential transconductance amplifier being coupled to the collector terminal of the first transistor, the second input terminal of the differential transconductance amplifier being coupled to the collector terminal of the second transistor, and the output terminal being coupled to the output terminal of the input amplifier.