Patent ID: 7668278
Filing Date: 2010-02-23
Classification: H03D,H03L

Abstract:
1. Phase lock loop, comprising a controlled oscillator to deliver a high frequency signal, a frequency divider to convert the high frequency signal into a divided frequency signal, a phase comparator to receive the divided frequency signal and a reference signal and produce a signal measuring a phase difference between the divided frequency signal and the reference signal, and a low-pass filter to control the oscillator on the basis of the measurement signal, wherein it also comprises means for generating a measurement window, of a duration defined by counting cycles of the high frequency signal, in response to each active edge of the divided frequency signal, and the phase comparator is built to activate the measurement signal during the measurement window in response to each active edge of the divided frequency signal, so that the measurement signal comprises, when an active edge of the reference signal falls within the measurement window, a first pulse between the start of the measurement window and said active edge of the reference signal and a second pulse opposite to the first pulse between said active edge of the reference signal and the end of the measurement window; wherein the phase comparator is designed to produce the measurement signal in the form of two components, each having a respective activation duration, the difference between said activation durations of the components being a piecewise linear function of a time offset between the divided frequency signal and the reference signal.