Patent ID: 6751113
Filing Date: 2004-06-15
Classification: H05K,Y02P

Abstract:
A memory module comprising:a generally planar printed circuit board having a line of bilateral symmetry which bisects the printed circuit board into a first lateral half and a second lateral half; a first row of memory integrated circuits identical to one another, the first row positioned on a first side of the printed circuit board, the first row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the first row having a first orientation direction; a second row of memory integrated circuits identical to the integrated circuits of the first row, the second row positioned on the first side of the printed circuit board, the second row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the second row having a second orientation direction rotated in a plane parallel to the printed circuit board by approximately 180 decrees from the first orientation direction; a first addressing register coupled to the integrated circuits of the first row on the first lateral half and to the integrated circuits of the second row on the first lateral half; and a second addressing register coupled to the integrated circuits of the first row of the second lateral half and to the integrated circuits of the second row of the second lateral half, wherein the first addressing register addresses a first range of data bits and a second range of data bits non-contiguous with the first range of data bits, and wherein the second addressing register addresses a third range of data bits and a fourth range of data bits non-contiguous with the third range of data bits, the first range, the second range, the third range, and the fourth range having the same number of data bits.