Patent ID: 6548318
Filing Date: 2003-04-15
Classification: G02F,Y10S

Abstract:
A fabrication method for a multi-layered thin film protective layer, which is applicable to a substrate comprising a peripheral circuit area and a pixel cell area, wherein the peripheral circuit area comprises a plurality of metal layers and the pixel cell area comprises a plurality of pixel cells, the fabrication method comprising the steps of:filling an insulation material between the pixel cells and the metal layers; forming sequentially a first oxide layer, a silicon nitride layer and a second oxide layer to cover the pixel cells and the metal layers; patterning the second oxide layer to define a pre-determined position for a spacer; defining the silicon nitride layer and the first oxide layer to form a first protective layer and a first spacer in the peripheral circuit area and to form a second spacer in the pixel cell area exposing the pixel cells, wherein the first protective layer is formed with the silicon nitride layer and the first oxide layer, the first spacer and the second spacer are formed with the second oxide material, the silicon nitride layer and the first oxide material, and the first and the second spacers are higher than the first protective layer; and forming a second protective layer in the substrate covering the pixel cell area.