Patent ID: 7557024
Filing Date: 2009-07-07
Classification: H01L

Abstract:
1. A process for fabricating a semiconductor device comprising: forming a conductive layer over a substrate; forming a resist layer directly on the conductive layer; patterning the resist layer according to a desired arrangement of gates to be formed from the conductive layer, leaving a portion of the conductive layer exposed through the patterned resist layer; partially etching the conductive layer using the patterned resist layer as masks to form a plurality of conductive structures, each conductive structure having a first width and being separated from each adjacent conductive structure by a first gap width; removing remnants of the patterned resist layer, such that the plurality of conductive structures consist substantially entirely of conductive material from the conductive layer; forming spacers on sidewalls of the conductive structures; and etching the exposed conductive layer, such that the exposed conductive layer other than the plurality of conductive structures is substantially removed.