Patent ID: 8640069
Filing Date: 2014-01-28
Classification: G06F

Abstract:
1. A noise analysis model stored in a non-transitory storage device and executed by a computer, the noise analysis model comprising: a first resistor that serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor; a second resistor that serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor; and a third resistor that serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential, wherein element level noise analysis and substrate level noise analysis are independently performed from each other through the first point set as a common node to pass propagation noise, and the noise analysis model is used for the element level noise analysis.