Patent ID: 6490211
Filing Date: 2002-12-03
Classification: G11C

Abstract:
A random access memory device comprising:a memory cell array for storing data; a plurality of bit line pairs coupled to the memory cell array; a plurality of sense amplifier circuits coupled to correspond to the respective bit line pairs, wherein each of the sense amplifier circuits senses a voltage difference between bit lines of a corresponding pair and amplifies the voltage difference in response to first and second sense amplification activation signals; and a sense amplification activation signal generating circuit that generates the first and second sense amplification activation signals in response to a row active command signal, wherein the sense amplification activation signal generating circuit includes: a voltage comparator that compares a power supply voltage with a reference voltage to generate a comparison signal; a signal generator that generates first and second signals in response to the row active command signal; a first delay that adjusts rise/fall time of the first signal according to a logic level of the comparison signal, to output the first signal thus adjusted as the first sense amplification activation signal; and a second delay that adjusts rise/fall time of the second signal according to the logic level of the comparison signal to output the second signal thus adjusted as the second sense amplification activation signal.