Patent ID: 6023492
Filing Date: 2000-02-08
Classification: H03M

Abstract:
A circuit used to conditionally combine a plurality of bit metrics used in decoding a received information signal, said circuit comprising:at least one adder having a plurality of input nodes each of which receives one of said plurality of bit metrics, said at least one adder providing as an output a sum of said plurality of bit metrics;a multiplexor having a plurality of inputs, at least one each for: zero, each of said plurality of bit metrics individually, and said output sum of said at least one adder, said multiplexor also having a selection input which is operable to select one of said plurality of inputs; anda controller for providing said selection input to said multiplexor, wherein for each plurality of bit metrics supplied to said adder said controller provides a sequence of selection inputs to said multiplexor, such that said plurality of bit metrics are relatively constant as compared with said selection inputs.