Patent ID: 7126374
Filing Date: 2006-10-24
Classification: H03K

Abstract:
1. A field programmable gate array (FPGA) comprising: a plurality of logic clusters arranged in rows and columns, each logic cluster comprising: a first-level routing architecture comprising vertical channels and horizontal channels programmably coupled to said logic clusters; a second-level routing architecture comprising vertical channels and horizontal channels programmably coupled to the first-level routing architecture through at least one of said transmitter modules and at least one of said receiver modules, wherein at least one of said plurality of receiver modules comprises a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture, and at least one of said plurality of receiver modules can receive signals from said second-level routing architecture and transmit said signals to said first-level routing architecture, wherein at least one of said plurality of transmitter modules comprises: wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routine architecture and can transmit signals from a vertical channel of said second-level routing architecture to a plurality of horizontal channels of said second-level routing architecture, and wherein said transmitter modules are coupled to every other second-level vertical channel within the same logic cluster column.