Patent ID: 6236604
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A row address circuit of a semiconductor memory device, comprising:a refresh address counter that generates a refresh address signal in response to a refresh count signal;an input circuit that selectively inputs the refresh address signal in a refresh mode and an external address signal in a normal mode;a predecoder that receives an address signal from the input circuit;a signal generator that produces an enable signal including a active region with a leading edge delayed relative to a leading edge of an active region of the refresh count signal and a trailing edge prior to a trailing edge of the active region of the refresh count signal, the signal generator generating the active region in the enable signal in response to the refresh count signal in the refresh mode; andan output circuit that outputs the predecoded row address signal, wherein the active region of the enable signal enables the output circuit to change the predecoded row address signal.