Patent ID: 8514235
Filing Date: 2013-08-20
Classification: G06F,G06T

Abstract:
1. A graphics processing apparatus comprising: an execution unit for processing programmed shader operations, wherein the execution unit is configured for processing operations of a plurality of threads; memory forming a register file that accommodates all register operations for all the threads executed by the execution unit, the memory being organized in a plurality of banks, with a first plurality of banks being allocated to a first plurality of the threads and a second plurality of banks being allocated to the remaining threads; allocation logic configured to allocate and release registers within the register file in response to requests for logical registers by one of the plurality of threads; and translation logic configured to translate logical register identifiers into physical register addresses, wherein a logical register identifier includes a thread identifier identifying a thread executed within the execution unit and a register index identifying a location within the register file; and wherein the allocation logic is configured to pair instructions such that successive accesses of the memory may be performed by different threads, so that processing of a register operation of one thread may be performed at the same time that a register access from another thread takes place.