Patent ID: 6350625
Filing Date: 2002-02-26
Classification: H01L,H01S

Abstract:
A method for concurrently fabricating a plurality of optoelectronic packaging submounts providing for 90Â° C. electrical conductor turns; comprising:(a) providing a wafer having a surface initially defining a plurality of undiced semiconductor chips; (b) delineating conductive traces and associated electroplating pads on each of said undiced chips; (c) delineating conductors in kerf regions intermediate selective rows of said chips; (d) covering said chips with a photoresist mask while leaving windows open over the traces proximate at least one edge of each of said chips; (e) immersing said wafer in an electroplating bath so as to form contacts to the traces in said kerf regions and plating the regions of said windows; and (f) removing said resist and dicing said wafer into individual said chips to provide said submounts.