Patent ID: 7296196
Filing Date: 2007-11-13
Classification: G11C

Abstract:
1. A memory device comprising: a bit memory array, said bit memory array having a plurality of bit memory locations; a redundant bit memory array, said redundant bit memory array having a plurality of redundant bit memory locations; a bit reading register configured to be coupled to said bit memory array and to said redundant bit memory array; a controller configured to address certain ones of said plurality of bit memory locations and certain ones of said redundant bit memory locations, said controller being further configured to selectively couple said bit memory array and said redundant bit memory array to said bit reading register and substitute a content of one or more of said redundant bit memory locations for an existing content of one or more of said plurality of bit memory locations, said controller coupled to said bit memory array, said redundant bit memory array, and said bit reading register; and wherein said controller is further configured to: receive a sequence of address bits within a succession of input data bits, address one or more redundant bit memory locations based on a first portion of said sequence of address bits received, couple said bit reading register to a first portion of redundant bit memory positions of said one or more redundant bit memory locations addressed, read a first portion of redundant memory bits from said first portion of redundant bit memory positions, and transfer out said first portion of redundant memory bits read.