Patent ID: 6501702
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A semiconductor memory integrated circuit comprising:a memory cell array; a clock buffer for receiving a clock signal to generate an internal clock signal; an address buffer for receiving an address signal in accordance with said internal clock signal generated by said clock buffer; an address decoding circuit including a first stage decoder for decoding an internal address signal outputted from said address buffer to select a word line of said memory cell array, and a second stage decoder for further decoding an output of said first decoder to drive a selected word line; and a pulse generating circuit for generating a timing pulse for controlling an activation timing of said second decoder of said address decoding circuit based on the internal clock signal outputted from said clock buffer; wherein said address buffer includes a first latch circuit for temporally holding the received address signal, and said second stage decoder of said address decoding circuit includes a second latch circuit for temporally holding a decoded output transferred from said first stage decoder.