Patent ID: 7861041
Filing Date: 2010-12-28
Classification: G06F

Abstract:
1. A cache memory system comprising: a cache memory including a plurality of sets, each set including a plurality of block storage locations; and a block replacement controller coupled to the cache memory and configured to maintain a separate count value corresponding to each set of the cache memory, wherein the separate count value corresponding to a given set points to an eligible block storage location within the given set to store replacement data; wherein the block replacement controller is further configured to maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed since a last time the separate count value pointed to the corresponding block storage location, wherein the recent access bit is separate from the separate count value for a given set; and wherein the block replacement controller is further configured to store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular one of the recent access bits corresponding to the eligible block storage location indicates that the eligible block storage location was recently accessed.