Patent ID: 8673657
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising; forming a circuit area, a first monitor area, and a second monitor area on a chip which a semiconductor wafer is diced into; forming a first layer composing a semiconductor integrated circuit within said circuit area, a first monitor layer within said first monitor area, and a second monitor layer within said second monitor area; forming at least five first monitor patterns of substantially the same shape in the first monitor layer, the at least five first monitor patterns being disposed at a first pitch between each other; forming at least five second monitor patterns of substantially the same shape in the second monitor layer, the at least five second monitor patterns being disposed at the first pitch between each other; forming a second layer composing said semiconductor integrated circuit on or above said first layer, a third monitor layer on or above said first monitor layer, and a fourth monitor layer on or above said second monitor layer; forming at least five third monitor patterns of substantially the same shape in the third monitor layer, the at least five third monitor patterns being disposed at a second pitch between each other; and forming at least five fourth monitor patterns of substantially the same shape in the fourth monitor layer, the at least five fourth monitor patterns being disposed at the second pitch between each other, wherein all of the first monitor patterns and the third monitor patterns formed within said first monitor area extend in a first direction, and all of the second monitor patterns and the fourth monitor patterns formed within said second monitor area extend in a second direction perpendicular to the first direction.