Patent ID: 9001959
Filing Date: 2015-04-07
Classification: G09G,H01L

Abstract:
1. A semiconductor device comprising: a first wiring configured to be supplied with a first potential; a second wiring configured to be supplied with a second potential that is different from the first potential; a third wiring configured to be supplied with a third potential higher than the first potential and the second potential; a fourth wiring configured to be supplied with a first clock signal; a first transistor comprising a first terminal, a second terminal, and a gate; a second transistor comprising a first terminal, a second terminal, and a gate; a third transistor comprising a first terminal, a second terminal, and a gate; a fourth transistor comprising a first terminal, a second terminal, and a gate; a fifth transistor comprising a first terminal, a second terminal, and a gate; a sixth transistor comprising a first terminal, a second terminal, and a gate; and a seventh transistor comprising a first terminal, a second terminal, and a gate, wherein the gate of the first transistor is electrically connected to the gate of the third transistor, wherein the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, wherein the gate of the second transistor is electrically connected to the gate of the fourth transistor, wherein the second terminal of the second transistor is electrically connected to the first wiring, wherein the second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, and wherein the second terminal of the fourth transistor is electrically connected to the second wiring, wherein the first terminal of the fifth transistor is electrically connected to the gate of the second transistor and the gate of the fourth transistor, wherein the second terminal of the fifth transistor is electrically connected to the second wiring, wherein the first terminal of the sixth transistor is electrically connected to the third wiring, wherein the second terminal of the sixth transistor is electrically connected to the gate of the second transistor and the gate of the fourth transistor, wherein the first terminal of the seventh transistor is electrically connected to the third wiring, wherein the second terminal of the seventh transistor is electrically connected to the first terminal of the fifth transistor, and wherein the fourth wiring is electrically connected to the first terminal of the first transistor and the first terminal of the third transistor.