Patent ID: 6385758
Filing Date: 2002-05-07
Classification: G06F

Abstract:
A graphic layout compaction system for compacting a layout represented by layout data supplied thereto and including (a) a pattern of at least a single layer having routes, component terminals, via holes, and polygonal conductor configurations arranged in a two-dimensional space and (b) components of a printed-circuit board or semiconductor cells, said system comprising:constraint graph data generating means supplied with said layout data for preparing constraint graph data representative of a constraint graph connecting any ones of said component terminals, said via holes, said semiconductor cells, said routes, and component contours; terminal constraint graph generating means for preparing terminal constraint graph data representative of a terminal constraint graph having as opposite nodes any ones of said component terminals, said via holes, said semiconductor cells, and said component contours, and for calculating a movement limit distance within which one of said opposite nodes coupled by said terminal constraint graph data can move in a compaction direction towards the other node with a routing zone interposed therebetween, said routing zone having a width equal to a sum of the width of any route or routes interposed between said opposite nodes and a necessary gap; component compacting means for moving each component or each via hole as the other node within said movement limit distance to compact the layout; and rerouting means for shaping said routes into route configurations including diagonal parts and rerouting said routes in a space between said component and said via hole.