Patent ID: 8954640
Filing Date: 2015-02-10
Classification: G06F

Abstract:
1. An integrated circuit, comprising: an interface configured to receive packetized data specifying a programming instruction for a memory external to the integrated circuit over a first communication channel; wherein the first communication channel is an in-band signaling channel also used by the integrated circuit when performing a function independent of programming the memory and the memory is a programmable read-only memory external to the integrated circuit; a buffer comprising a first port coupled to the interface and a second port; wherein the buffer is configured to store the programming instruction extracted from the packetized data; a programmer coupled to the second port; wherein the programmer reads the programming instruction from the buffer through the second port; wherein the programmer is configured to program the memory over a second communication channel different from the first communication channel responsive to interpretation of the programming instruction from the buffer; user-specified circuitry implemented within the integrated circuit and coupled to the interface; wherein the user-specified circuitry is configured to communicate over the first communication channel for performing a function independent of programming the memory; and a memory interface coupled to the programmer and the user-specified circuitry; wherein the memory interface communicatively links one of the programmer or the user-specified circuitry with the memory at a time.