Patent ID: 9142650
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A method for fabrication of fin devices for an integrated circuit, comprising: forming fin structures in a semiconductor material, the fin structures including sidewalls and tops; providing conformal masking substantially over a first set of fin structures; at a fin recess stage, performing a first channel implantation at a tilt angle to form a doped region along the sidewalls and the tops of un-masked second set of fin structures, the semiconductor material being maintained at an elevated temperature during the channel implantation; removing a mask from the first set of fin structures; and respectively forming at least one field effect transistor from the first set of fin structures and the second set of fin structures, wherein a conductivity type of the field effect transistor formed from the first set of fin structures differs from a conductivity type of the field effect transistor formed from the second set of fin structures, and wherein the field effect transistors formed from the second set of fin structures have a threshold voltage that is based on the channel implantation.