Patent ID: 6555870
Filing Date: 2003-04-29
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of memory cell transistors which are arranged in column and row directions; and a semiconductor substrate of a first conductive type, in which a plurality of grooves are formed so as to extend in column direction on the side of the surface thereof, each of said memory cell transistors comprising, a first region of a second conductive type formed in the surface portion of the semiconductor substrate on the bottom of each of said grooves, a second region of said second conductive type formed in the surface portion of the semiconductor substrate other than said grooves, a charge storage layer formed on the semiconductor substrate, and a conductive layer formed on said charge storage layer; wherein said second region is shared between two of said memory cell transistors adjacent to each other in said row direction, said charge storage layer is continuously formed in said row direction for said memory cell transistors in said row direction, when electrons are injected into said charge storage layer of a selected one of said memory cell transistors, a first voltage is applied to said first region of said selected memory cell transistor, a second voltage is applied to said second region of said selected memory cell transistor, and a third voltage is applied to said first region of a second memory cell transistor which shares its second region with said selected memory cell transistor, and said second voltage is higher than said first voltage and said third voltage has a value such that electrons are not injected into said charge storage layer of said second memory cell transistor.