Patent ID: 8250337
Filing Date: 2012-08-21
Classification: G06F

Abstract:
1. An array processor apparatus comprising: at least one opcode control element configured to generate a first opcode portion and a second opcode portion in accordance with a received opcode to obtain elements of a matrix to transmit a result to an owner resource; a plurality of multiplexers configured to selectively output data to a plurality of multipliers in response to the first opcode portion, the plurality of multipliers configured to operate on the data received from the plurality of multiplexers; a plurality of arithmetic logic units (ALUs) configured to operate on data received from the plurality of multipliers, the data being received in response to the second opcode portion, a register that outputs at least a third opcode portion of the received opcode to indicate whether or not the value output by the plurality of ALUs corresponds to a completed valid operation.