Patent ID: 7365753
Filing Date: 2008-04-29
Classification: G06T

Abstract:
1. A computer system, comprising: a processor coupled to a bus; a memory in communication with the bus; a graphics unit in communication with the bus, the graphics unit comprising a graphics controller and a plurality of parallel texture pipelines; wherein each parallel texture pipeline includes a state variable queue, each state variable queue comprising an accumulation register for accumulating a set of state variables for a polygon, a latching register coupled to the accumulation register, and a state variable FIFO buffer coupled to the latching register; and wherein the graphics controller includes a data output coupled to the plurality of accumulation registers, the graphics controller having a first control output to trigger advancement of the set of state variables from the plurality of accumulation registers to their corresponding latching registers, and the controller having a second control output to trigger advancement of the set of state variables from a number of the latching registers to their corresponding state variable FIFO buffers, said number representing a number of parallel textures indicated by the set of state variables.