Patent ID: 6185331
Filing Date: 2001-02-06
Classification: G06K,G06N

Abstract:
A switched-current fuzzy processor, which comprises:means for decoding a feature input into a set of binary feature signals;an array of MFGs, coupled to said decoding means, for obtaining a set of current outputs whose magnitudes are proportional to the values of the feature signals respectively;weight-adjusting means, coupled to said MFG array, for applying a predetermined weight factor in binary form to the output currents from said MFG array, wherein the weight-adjusting means comprising a plurality of proportional current mirrors, each being associated with one of the bits in the binary-coded weighted factor and having an output connected to a common current output line;summing means, coupled to said weight-adjusting means, for summing up each set of currents from each column of the MFGs in said MFG array to thereby obtain a total value for the currents therefrom; anda maximum-value determination circuit, coupled to said summing means, capable of obtaining the one of the currents with the maximum magnitude from said summing means.