Patent ID: 6207484
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A method for fabricating a BiCDMOS device where bipolar, MOS and double diffused MOS devices are formed on a single semiconductor substrate, comprising the steps of:(a) forming a semiconductor region of a second conductivity type on the semiconductor substrate of a first conductivity type;(b) forming buried layers of the first conductivity type and buried layers of the second conductivity type corresponding to the predefined arrangement of the well regions, and then forming well regions of the first conductivity type and well regions of the second conductivity type within the semiconductor region in a predefined arrangement;(c) forming an oxidation passivation layer pattern overlying the well regions, the passivation layer pattern defining a field oxide region where a field oxide layer will subsequently be formed;(d) implanting impurity ions of the first conductivity type into the entire surface of the field oxide region, using the oxidation passivation layer pattern as an ion implantation mask;(e) forming an ion implantation mask pattern defining a field region of the second conductivity type overlying the oxidation passivation layer pattern;(f) implanting impurity ions of the second conductivity type, using the ion implantation mask pattern;(g) removing the ion implantation mask pattern; and(h) forming a field oxide layer by annealing, using the oxidation passivation layer pattern and simultaneously forming a field region of the first conductivity type and a field region of the second conductivity type,wherein the step of forming the buried layers of the first and the second conductivity types comprises the substeps of:forming buried layers of the second conductivity type within the semiconductor substrate in a first predefined pattern;implanting impurities of the first conductivity type into the semiconductor substrate in a second predefined pattern, the second pattern including areas of the semiconductor region adjacent the first predefined pattern and areas of the semiconductor region corresponding to a region where a double diffused MOS transistor is to be formed; anddiffusing the impurities of the first conductivity type to form buried layers of the first conductivity type, wherein one of the buried layers of the first conductivity type, formed in the area corresponding to the region where the double diffused MOS transistor is to be formed, is located below one of the buried layers of the second conductivity type.