Patent ID: 7414483
Filing Date: 2008-08-19
Classification: G01R,H03L

Abstract:
1. A test circuit configured to evaluate timing accuracy of a clock signal comprising: a delay circuit whose delay is controllable, a phase comparator circuit configured to compare the phases between the clock signal to be examined and a delay clock signal delayed from the clock signal by the delay circuit, a measuring counter configured to count a number of outputs of the prescribed comparison result from the phase comparator circuit, a signal switching circuit configured to switch an input signal to be received by the delay circuit from the clock signal to a delay signal which satisfies an oscillation condition in which the delay signal is received from the delay circuit thus to develop a ring oscillator, and a frequency measuring circuit configured to measure an oscillation frequency when the ring oscillator has been developed by the signal switching circuit, wherein the delay circuit includes a variable delay circuit comprising a plurality of variable delay units connected in series, wherein all said variable delay units are part of the signal flow at all times during operation, and the delay in each of the variable delay units is controllable independently.