Patent ID: 6806126
Filing Date: 2004-10-19
Classification: H01L,Y10S

Abstract:
A method for manufacturing a semiconductor component, comprising:providing a semiconductor material of a first conductivity type having a major surface; forming a gate structure on the major surface, the gate structure having first and second sides and a top surface; forming first and second spacers adjacent the first and second sides of the gate structure, respectively, the first and second spacers comprising a first dielectric material; forming source and drain extension regions in the semiconductor material, the source extension region aligned to the first spacer and the drain extension region aligned to the second spacer; forming third and fourth spacers adjacent the first and second spacers, respectively, the third and fourth spacers comprising the first dielectric material; exposing portions of the first and second sides of the gate structure; and forming source and drain regions in the semiconductor material, the source region aligned to the third spacer and the drain region aligned to the fourth spacer.