Patent ID: 6173436
Filing Date: 2001-01-09
Classification: H03K

Abstract:
A digital integrated circuit (IC) layout comprising:a first layout area in said IC layout corresponding to a power-on-reset circuit having an input coupled to a power supply input of said IC layout and having an output for generating a reset signal, said first layout area being implemented using standardized digital cells and routed using a standarized routing technique;a second layout area in said IC layout corresponding to the remainder of the digital IC, said second layout area being coupled to said reset signal and said power supply signal, said second layout area being implemented using standardized digital cells and routed using a standardized routing technique;wherein said first layout area is essentially non-discernible from said second layout area;wherein high current and high voltage devices in said power-on-reset circuit are implemented within said first layout by device layouts having essentially the same layout dimensions as digital device layouts in said second layout area.