Patent ID: 8427203
Filing Date: 2013-04-23
Classification: G11C,H03K

Abstract:
1. Reconfigurable computing logic, comprising: a decoder having at least one input and at least two outputs; at least one power/reconfigure block; at least two programmable resistance blocks; and at least one logic output block; wherein a signal applied to said at least one input of said decoder is decoded and applied as an input to any of said at least two programmable resistance blocks according to a decoding scheme; a signal output from any of said at least two programmable resistance blocks in response to said applied signal into any of said at least two programmable resistance blocks, is input into said at least one output block; said at least one logic block corrects the voltage and logic state of said reconfigurable computing logic output; and wherein said at least one power/reconfigure block powers said reconfigurable computing logic; and selectively directs a voltage and current to reprogram any of said at least two programmable resistance blocks.