Patent ID: 9117777
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A method for reducing defects in an active layer of a semiconductor in a semiconductor device, wherein the active layer (i) comprises one of silicon, germanium, or silicon germanium, (ii) has a crystal orientation direction, (iii) is at least laterally defined by an isolation structure, and (iv) is physically in contact with the isolation structure at a contact interface that is oriented along the crystal orientation direction of the active layer, wherein the isolation structure and the active layer abut on a common planar surface, wherein the method comprises: providing a patterned stress-inducing layer on the common planar surface, wherein (i) the stress-inducing layer is adapted for inducing a stress field in the active layer, (ii) providing the patterned stress-inducing layer defines features on the common planar surface, wherein the features are defined laterally by parallel longitudinal boundaries forming an angle with the contact interface between the active layer and the isolation structure and the angle is within a range of about 8.43° to about 28.43°, and (iii) the induced stress field results in a shear stress on a defect in the active layer; performing an anneal step after providing the patterned stress-inducing layer on the common planar surface; and removing the patterned stress-inducing layer from the common planar surface.