Patent ID: 7225349
Filing Date: 2007-05-29
Classification: G06F

Abstract:
1. A circuit, comprising: a trigger control that adjusts rise and fall time settings of a clock; a first register coupled to the trigger control, the first register to contain default rise and fall settings of the clock, the trigger control using the rise and fall settings to adjust the clock; m registers coupled to the first register with “m” being an integer greater than or equal to one, each of the m registers having rise and fall settings that increase a period of the clock, the trigger control accessing the m registers if a power supply voltage is detected to be less than a reference voltage; and n registers coupled to the in registers with “n” being an integer greater than or equal to one, the n registers having rise and fall settings that allow the clock to recover a period increase from the m registers and a total decrease in clock period caused by the rise and fall settings of the n registers is less than a frequency guard band.