Patent ID: 6311255
Filing Date: 2001-10-30
Classification: G06F

Abstract:
An apparatus for selectively restricting access to protected shared memory in a computer network system, the system having a processor, and a first bus for electrically connecting one or more adapter units to the shared memory, the apparatus comprising:a program accessable store comprising a predetermined address range for enabling a range of said shared memory accessable by one or more adapters, and further comprising predetermined associated identities of said one or more adapters that are enabled to access said range of said shared memory;a receiver circuit in processing communication with said first bus, said receiver circuit receiving a first adapter unit address for shared memory from a first adapter unit;an identity determining circuit in processing communication with said first adapter unit by way of said first bus, said identity determining circuit associating said first adapter unit address to a first adapter unit identity;an address authorizing checker circuit for comparing said first adapter unit address and said first adapter unit identity with said predetermined address range and said predetermined associated identities; andan error generator circuit responsive to said address authorizing checker circuit, said error generator circuit enabling access to said shared memory when said address authorizing checker circuit comparing function determines said first adapter unit address is within said predetermined address range and said predetermined associated identities in said program accessable store, and said error generator circuit preventing access to said shared memory when said first adapter unit address and said first adapter unit identity is not within said predetermined address range and said predetermined associated identities in said program accessable store.