Patent ID: 6367042
Filing Date: 2002-04-02
Classification: G01R

Abstract:
A method for testing an integrated circuit having an identification circuit and a built-in self test circuit, comprising the steps of:providing an identification number to the identification circuit, the identification number differentiating the integrated circuit from other integrated circuits; applying a first stress factor(s) to the integrated circuit; performing a first built-in self test analysis to detect faults in a predetermined portion of the integrated circuit; generating first fault information pertaining to any faults detected by the first built-in self test analysis; correlating the identification number with first fault information; applying a second stress factor(s) to the integrated circuit; performing a second built-in self test analysis on the predetermined portion of the integrated circuit; generating second fault information pertaining to any faults detected by the second built-in self test analysis; correlating the identification number with second fault information; and comparing the first fault information with the second fault information to ascertain any differences, wherein the comparison step utilizes the identification number.