Patent ID: 8072830
Filing Date: 2011-12-06
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a plurality of memory macros having memory cells which store data; a nonvolatile storage circuit which stores a plurality of data items for tuning operations of the plurality of memory macros; a macro-common register block provided outside the plurality of memory macros and having macro-common registers which sequentially distribute memory macro operation specifying signals for tuning operations of the plurality of memory macros, to the plurality of memory macros, the macro-common registers being connected in serial to the nonvolatile storage circuit to serially store, upon power on, the plurality of data items for tuning operations of the plurality of memory macros and stored in the nonvolatile storage circuit; and memory macro operation setting circuits which are respectively provided in the plurality of memory macros and configured to set operating states of the plurality of memory macros according to the memory macro operation specifying signals supplied from the macro-common registers.