Patent ID: 8122233
Filing Date: 2012-02-21
Classification: G06F,Y02D

Abstract:
1. An information processing device, comprising: a processing unit; a peripheral circuit module; a bus coupled to said processing unit and said peripheral circuit module; and a boot address register coupled to said bus, wherein said information processing device includes a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode wherein said boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein said address is output from said boot address register to the processing unit when said information processing device shifts from said second operation mode to said first operation mode, wherein said boot address register is able to be written from said bus to replace said address held by said boot address register with another address, an information holding circuit that holds a value of a register contained in said peripheral circuit module, wherein said information holding circuit holds, in said second operation mode, information about the register contained in said peripheral circuit module, and, transfers information held in said information holding circuit to the register contained in said peripheral circuit module when the information holding circuit shifts from said second operation mode to said first operation mode, and wherein when an interrupt request is posted from the outside of said information processing device in said second operation mode, said information processing device performs interrupt processing corresponding to said interrupt request.