Patent ID: 6246275
Filing Date: 2001-06-12
Classification: H03K

Abstract:
A multi-phase programmable clock generator having at least one data select line for a data select signal, at least one data signal line for a data-string, a clock signal line for a clock signal, and at least one data feedback line for a data feedback signal, each phase of said clock generator comprising:a multiplexer coupled to said data select line, said data feedback line, and said data line, said multiplexer selecting between the data-string and the data feedback signal based on the status of the data select signal; anda plurality of registers serially coupled together and having a first register and a last register, the first register being coupled to said multiplexer and the last register being coupled to said feedback line, said plurality of registers latching data from said multiplexer on a first-in-first-out basis, each register being coupled to said clock signal line, said plurality of registers latching data from the data-string during each clock cycle of the clock signal, each register comprising a single-bit register, said data-string comprising a respective data bit for each single-bit register;said multiplexer selecting between a program state and a repeat state, the program state enabling programming of each respective data bit of said data-string into a respective register, the repeat state enabling the data-string to be cycled through the registers, such that the multiplexer provides an output clock generator signal having a waveform shape determined by the respective data bit values of the data-string.