Patent ID: 7443937
Filing Date: 2008-10-28
Classification: B65H

Abstract:
1. A clock synthesizer for generating a desired clock signal from an input clock signal, comprising: an exclusive OR gate, having a first input, a second input and an output, the first input coupled to receive a reset signal; a delay string buffer having an input, a control input and an output, the delay string buffer input coupled to the output of the exclusive OR gate, wherein; a fine tuning unit, having an input, a control input and an output, the fine tuning unit input coupled to the output of the delay string buffer, the fine tuning unit output coupled to the second input of the exclusive OR gate; and a control unit, having a first input, a second input and an output, the first input of the control unit coupled to receive the input clock signal and the second input of the control unit coupled to the output of the exclusive OR gate to generate a control signal at the output; wherein the control input of the delay string buffer is coupled to receive the control signal to provide a coarse adjustment of the input clock signal corresponding to the desired clock signal, and wherein the control input of the fine tuning unit is coupled to receive the control signal to provide a fine adjustment of the input clock signal corresponding to the desired clock signal.