Patent ID: 7675340
Filing Date: 2010-03-09
Classification: G06F,H03K

Abstract:
1. A multiphase clock generator circuit for generating a plurality of output clock pulses that differ in phase on the basis of a reference clock pulse, having a first divider circuit, having a plurality of latch circuits connected in the form of a ring, for dividing a first reference clock pulse to generate a plurality of first output clock pulses that differ in phase; a second divider circuit having a plurality of latch circuits connected in the form of a ring, for dividing a second reference clock pulse to generate a plurality of second output clock pulses that differ in phase, wherein said first and second reference clock pulses have different phases from each other; and a switch for forming an intermittent short between predetermined nodes of the first and second divider circuits, wherein the switch forms a short between the predetermined nodes with timing in which the predetermined nodes are brought to the same level in a normal operating state, wherein the switch has a first switch for forming a short between the first nodes of the first and second divider circuits in response to the first reference clock pulse, and a second switch for forming a short between the second nodes of the first and second divider circuits in response to the second reference clock pulse.