Patent ID: 7472325
Filing Date: 2008-12-30
Classification: G01R,G11C

Abstract:
1. A method of testing embedded memory arrays in functional circuitry within an integrated circuit using a built-in self test (BIST) architecture, said method comprising: performing, by a BIST logic controller, test functions common to all of said embedded memory arrays said BIST logic controller being remote from said embedded memory arrays and operating at a lower frequency than said embedded memory arrays; sending, by said BIST logic controller, instructions to a plurality of blocks of test logic, each one of said blocks being incorporated into a corresponding one of said embedded memory arrays and operating at a same frequency as said corresponding one of said embedded memory array, said same frequency comprising a higher frequency relative to said lower frequency of said BIST logic controller; and performing, by said each one of said blocks, test functions unique to said corresponding one of said embedded memory arrays, said performing comprising: