Patent ID: 6522600
Filing Date: 2003-02-18
Classification: G11C

Abstract:
A semiconductor memory device in which first and second commands are input to effect a read/write operation of random data with respect to a memory cell array in synchronism with a clock signal and a row access command and a column access command for data readout are supplied as one packet in two successive clock cycles, comprising:a first pin supplied with a signal which distinguishes a read command and a write command; second pins supplied with upper-side and lower-side decode addresses; a controller to which a signal indicating that the read command is input and a signal indicating that the write command is input based on the signal input to said first pin are supplied; a first command decoder controlled by an output signal of said controller, which defines the readout/write operation by use of the first command, fetches an upper-side decode address of a memory cell array via said second pin and decodes the first command; and a lower-side command decoder controlled by an output signal of said controller, which fetches a lower-side decode address of the memory cell array via the control pin in response to the second command, decodes the lower-side command and outputs a lower address latch command, mode register set command and auto-refresh command.