Patent ID: 6028443
Filing Date: 2000-02-22
Classification: G01R

Abstract:
A semiconductor integrated logic circuit including:a tri-state output buffer having three different output conditions of a logical high level, a logical low level and a high impedance condition;an internal control circuit generating a control signal for controlling said tri-state output buffer;a first selector having a first input receiving a data signal outputted from an internal logic circuit, a second input connected to receive said control signal, and an output connected to an data input of said tri-state output buffer; anda second selector having a first input connected to receive said control signal, and a second input connected to a predetermined logic level which brings said tri-state buffer into an output enable condition in which said tri-state output buffer outputs either the logical high level or the logical low level, an output of said second selector being connected to a control input of said tri-state output buffer.a selection control input of each of said first and second selectors being controlled by a common switch signal, so that when said common switch signal is indicative of a normal mode, said first selector selects and outputs said data signal to the data input of said tri-state output buffer and said second selector selects and outputs said control signal to said control input of said tri-state output buffer, and when said common switch signal is indicative of a test mode, said first selector selects and outputs said control signal to the data input of the tri-state output buffer and said second selector selects and outputs said logic level to said control input of said tri-state output buffer so that said tri-state buffer is brought in said output enable condition so as to output said control signal.