Patent ID: 7484046
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A cache, comprising: a first unit configured to receive a snoop request, wherein said first unit is further configured to store information about said snoop request in said first unit for up to a maximum number of n clock cycles thereby expanding a time to respond to said snoop request, wherein said first unit is further configured to dispatch said snoop request, wherein said first unit is further configured to remove information about said snoop request upon a successful dispatch of said snoop request; a selector coupled to said first unit, wherein said selector is configured to receive said dispatched snoop request and a request from a processor; an arbitration mechanism coupled to said selector, wherein said arbitration mechanism is configured to select one of said request from said processor and said snoop request; and a second unit coupled to said first unit, wherein said second unit is configured to receive a result of said dispatched snoop request along with a counter value indicating a number of clock cycles said information about said snoop request resided in said first unit; wherein said second unit is further configured to examine said counter value, wherein said second unit is further configured to store said result in said second unit for a period of n clock cycles less said number of clock cycles said information about said snoop request resided in said first unit, wherein said second unit is further configured to send said result to said interconnect after said period of n clock cycles less said number of clock cycles said information about said snoop request resided in said first unit has transpired.