Patent ID: 7119017
Filing Date: 2006-10-10
Classification: F28C,F28D,F28F

Abstract:
1. A method for forming an interlevel dielectric layer with improved gap filling comprising the sequential steps of: providing a semiconductor substrate having closely spaced gate electrodes, with said closely spaced gate electrodes defining gaps therebetween; forming lightly doped source and drain regions adjacent to said gate electrodes; forming sidewall spacers on said gate electrodes; forming source/drain contact areas adjacent to said sidewall spacers; forming a metal silicide layer on said gate electrodes and on said source/drain contact areas; removing said sidewall spacers; and forming said interlevel dielectric layer over and between said gate electrodes and filling said gaps between said gate electrodes on said substrate, wherein said removal of the sidewall spacers increases the gaps between the gate electrodes.