Patent ID: 6573853
Filing Date: 2003-06-03
Classification: H03K,H03M

Abstract:
An analog to digital converter comprising:a reference ladder; a clock having phases &psgr;1 and &psgr;2; a track-and-hold amplifier tracking an input signal with its output signal during the phase &psgr;1 and holding a sampled value during the phase &psgr;2; a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal; a plurality of fine amplifiers inputting corresponding taps from the reference ladder and a signal corresponding to the output signal, the taps selected based on outputs of the coarse amplifiers; a circuit responsive to the clock that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the corresponding taps to the fine amplifiers during the phase &psgr;2 and substantially rejecting the signal corresponding to the output signal during the phase &psgr;1; and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.