Patent ID: 6309931
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory device, comprising the steps of:forming a gate electrode layer on a main surface of semiconductor substrate with a gate insulating layer posed therebetween;forming a pair of source/drain regions at the main surface of said semiconductor substrate and sandwiching that region of said semiconductor substrate which is positioned under said gate electrode layer;forming a first insulating layer on the main surface of said semiconductor substrate to cover said gate electrode layer;forming in said first insulating layer a first hole reaching one of said paired source/drain regions;forming a conductive layer for a bit line, electrically connected to one of said paired source/drain regions through said first hole and extending on said first insulating layer;forming above said first insulating layer a second insulating layer covering said conductive layer for the bit line;forming a second hole penetrating said conductive layer for the bit line to reach the other of said paired source/drain regions by forming on said second insulating layer a resist pattern having a predetermined pattern and etching said second insulating layer, said conductive layer for the bit line and said first insulating layer using said resist pattern as a mask;forming a sidewall insulating layer covering a sidewall of said second hole; andforming a conductive layer for a storage node of a capacitor electrically connected to the other of said paired source/drain regions through said second hole.