Patent ID: 6359487
Filing Date: 2002-03-19
Classification: H03K,H03L,Y10S

Abstract:
A circuit comprising:a voltage controlled delay line configured to receive a system clock signal and to output a synchronization clock signal by applying a delay to said system clock signal; and a delay voltage control circuit for supplying a first and a second control voltage to said voltage controlled delay line to control said applying a delay by said voltage controlled delay line, said delay voltage control circuit including a correction magnitude circuit operative to control a level of said first control voltage such that a difference between successive levels in said first control voltage level increases as said first control voltage levels become greater and decreases as said first control voltage levels become lower; wherein the correction magnitude circuit is configured to control the level of the first control voltage and the difference between the successive levels based on a magnitude of current flowing through a correction portion including a control element for controlling the magnitude of the current flowing therethrough and wherein the control element operates in response to a feedback signal comprising the level of the first control voltage to decrease the magnitude of the current flowing as the level of the first control voltage decreases and to increase the magnitude of the current flowing as the level of the first control voltage increases, thereby controlling the difference as a function of the level of the first control voltage.