Patent ID: 6040596
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A dynamic random access memory (DRAM) device having a memory cell array region and a peripheral circuit region at spaced apart locations in a semiconductor substrate, comprising:an interlayer insulating layer having a planarized upper surface, on the semiconductor substrate;a lower DRAM capacitor electrode on a first portion of the planarized upper surface of said interlayer insulating layer extending opposite the memory cell array region;a capacitor dielectric layer having a first region therein that extends on said lower DRAM capacitor electrode and a second region therein that extends on a second portion of the planarized upper surface of said interlayer insulating layer;an upper DRAM capacitor electrode on the first region of said capacitor dielectric layer, opposite said lower DRAM capacitor electrode; anda resistor comprising the same material as said upper DRAM capacitor electrode and having a planar upper surface that extends opposite the second region of said capacitor dielectric layer.