Patent ID: 6611051
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, a primary side circuit being provided on said first semiconductor substrate, a secondary side circuit as provided on said second semiconductor substrate, first capacitive insulation means provided on said first semiconductor substrate for electrically insulating and isolating between said primary side circuit and said secondary side circuit while permitting signal transmission between said primary side circuit and said secondary side circuit, second capacitive insulation means provided on said second semiconductor substrate for electrically isolating between said primary side circuit and said secondary side circuit while permitting signal transmission therebetween, a first lead frame for input and output of a signal to and from said primary side circuit, a second lead frame for signal input and output to and from said secondary side circuits, a third lead frame supporting thereover said first semiconductor substrate, and a fourth lead frame supporting said second semiconductor substrate, whereinan external electrode of said first capacitive insulation means and an external electrode of said second capacitive insulation means are connected together by a bonding wire while letting said first semiconductor substrate and said second semiconductor substrate plus the first to fourth lead frames be sealed by a dielectric resin.