Patent ID: 7892912
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method for forming a vertical channel transistor of a semiconductor device, comprising: forming island-type hard mask patterns over a substrate; forming a plurality of pillar patterns to form a resultant pillar pattern structure with gap regions between neighboring pillar patterns, by etching the substrate using the island-type hard mask patterns as etch barriers; forming a gate insulation layer encapsulating the resultant pillar pattern structure; forming a surrounding gate electrode conduction layer surrounding only the sidewalls of the pillar patterns including the gate insulation layer, the surrounding gate electrode conduction layer not covering the gate insulation layer formed on a bottom of the gap regions between neighboring pillar patterns; filling a sacrificial layer to a predetermined height of a surrounding gate electrode in the gap regions between neighboring pillar patterns having the surrounding gate electrode conduction layer; and forming a surrounding gate electrode by removing a portion of the surrounding gate electrode conduction layer exposed by the sacrificial layer.