Patent ID: 8035127
Filing Date: 2011-10-11
Classification: H01L

Abstract:
1. A packaging substrate structure with a semiconductor chip embedded therein, comprising: a carrier board having a first surface, an opposed second surface, and at least a through cavity, wherein the semiconductor chip is received in the through cavity and has an active surface and an opposed inactive surface, the active surface has a plurality of electrode pads, and the semiconductor chip has a passivation layer with openings from which the electrode pads are exposed, and metal pads are disposed on the electrode pads; a buffer layer disposed on the first surface of the carrier board and on surfaces of the passivation layer formed on the active surface and the metal pads of the semiconductor chip; a first dielectric layer disposed on the buffer layer; and a first circuit layer disposed on the first dielectric layer, the first circuit layer being electrically connected to the metal pads of the semiconductor chip through first conductive vias disposed continuously through the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the semiconductor chip and the CTE of the dielectric layer, and the CTE of the buffer layer is 3-20 ppm/° C.