Patent ID: 8832393
Filing Date: 2014-09-09
Classification: G06F

Abstract:
1. Apparatus for aligning data write and read operations between different buffers, the apparatus comprising: a master logic circuit configured to, based on a control signal, assert a read clock stop signal and generate a write reset enable signal from the read clock stop signal; a plurality of first-in, first-out (FIFO) buffers coupled to the master logic circuit, wherein each of the plurality of FIFO buffers comprises: wherein, when the master logic circuit asserts the read clock stop signal, each of the plurality of FIFO buffers suspends movement of each write pointer and each read pointer, and, when the master logic circuit de-asserts the read clock signal, each of the plurality of FIFO buffers enables movement of each write pointer, then the read pointer to align data write and read operations of the plurality of FIFO buffers.