Patent ID: 6944078
Filing Date: 2005-09-13
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of word lines, a plurality of data lines, and a plurality of DRAM memory cells; a plurality of sense amplifiers coupled to said plurality of data lines and each receiving operating voltage from first and second nodes; a first line connected to said first nodes; a second line connected to said second nodes; and a third line coupled to said second nodes, wherein each of said plurality of sense amplifiers includes a first NMISFET pair arranged in a cross-coupled form and a first PMISFET pair arranged in a cross-coupled form, wherein said first NMISFET pair has said first node and said first PMISFET pair has said second node, wherein said first line supplies a first potential to said first nodes, wherein said second line supplies a second potential larger than the first potential to said second nodes, wherein said third line supplies a third potential larger than the second potential to said second nodes, and wherein said third line is arranged between said first and second lines.