Patent ID: 6468848
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method of fabricating a double-gate-driven FET, comprising the steps of:(a.) providing a semiconductor substrate biased to a reference voltage; (b.) forming a first well diffusion layer of first conductivity type in said substrate biased to a supply voltage; (c.) forming a second well diffusion layer of opposite conductivity type in said first n-type well diffusion layer electrically isolated from said substrate; (d.) forming a third well diffusion layer of first conductivity type in said second well diffusion layer; (e.) forming two source/drain diffusion layers in said third well diffusion layer of opposite conductivity type defining a channel therebetween; (f.) forming a gate coupled to said third diffusion layer to control inversion of said channel; (g.) forming a diode and an additional coupling capacitance; and (h.) jointly controlling the back-bias of said channel with said diode and additional coupling capacitance; (i.) said second well diffusion layer being biased to a value greater than or equal to the magnitude of the supply voltage minus the magnitude of a cut-in voltage of said diode.