Patent ID: 7193940
Filing Date: 2007-03-20
Classification: G11B

Abstract:
1. A pre-pit signal decoder, comprising: a shift register for receiving serial pre-pit bits and converting them into a parallel pre-pit byte; a pattern comparator for generating an odd sync bit, an even sync bit, a low bit, and a high bit according to the parallel pre-pit byte, the pattern comparator further receiving a disable signal and operating when the disable signal is not enabled; a counting unit for generating a counting value according to the odd sync bit, the even sync bit, the low bit, and the high bit, and marking evenness or oddness of frames of the pre-pit bit and sequence of wobble signals in the frames; an in-sync signal generating unit for generating an in-sync signal according to the odd sync bit, the even sync bit, the low bit, and the high bit; and a protection unit for receiving the counting value and the in-sync signal, and enabling the disable signal at positions where the pre-pit bits do not exist according to the counting value of the counting unit when the in-sync signal is enabled.