Patent ID: 6653827
Filing Date: 2003-11-25
Classification: G01R

Abstract:
An integrated circuit comprising:a test controller for providing a digital reference signal, an enable signal on an enable bus and a power-up signal on a power-up line; a digital-to-analog converter to convert the digital reference signal to an analog reference signal; a de-multiplex circuit coupled the digital-to-analog converter to selectively couple an output of the digital-to-analog converter to one of a plurality of reference signal points; a first analog test cell coupled to the enable bus and the power-up line, the first analog test cell comprises a first comparator to compare a first analog signal to a first analog range and provide a first digital output indicating if the first analog signal has a value within the first analog range; a second analog test cell coupled to the enable bus and the power-up line, the second analog test cell comprises a second comparator to compare a second analog signal selected from a plurality of analog signals to a second analog range, the second analog test cell provides a second digital output indicating if the second analog signal has a value within the second analog range; and a multiplex circuit coupled to the first and second analog test cells to selectively couple the first or second digital output signal to the test controller.