Patent ID: 8481380
Filing Date: 2013-07-09
Classification: G06F,H01L

Abstract:
1. A method of forming a junction field effect transistor (JFET), the method comprising: forming a trench in the substrate, the trench having a substantially horizontal bottom surface, a substantially vertical first side and a substantially vertical second side; forming a quasi-buried upper gate below the trench; filling the trench with an insulator material to create a shallow trench isolation (STI) region, wherein the quasi-buried upper gate is disposed such that only a portion of the quasi-buried upper gate is positioned under a portion of the STI region such that the quasi-buried upper gate does not extend along a portion of the STI region proximate to the second side of the trench; forming a lower gate region below the STI region; forming a channel region disposed between the lower gate and the STI region; forming a source region adjacent to the first side of the STI region; and forming a drain region adjacent to the second side of the STI region.