Patent ID: 6111756
Filing Date: 2000-08-29
Classification: H01L,H05K

Abstract:
A multichip module for constructing an electronic system from separate integrated circuit chips, said electronic system having at least a first group of circuits, a second group of circuits, a third group of circuits, and a set of electrical connections which interconnect the groups of circuits together, said module comprising:a first chip carrier having a plurality of first pads formed in a central area of said surface and for coupling to an IC chip, a plurality of second pads formed at the periphery of said surface, and a wiring pattern comprising a set of X-signal lines and a set of Y-signal lines, said X-signal and Y-signal lines being coupled between pads in said central area and said periphery area;a second chip carrier which comprises the pad and wiring construction of said first chip carrier;a third chip carrier which comprises the pad and wiring construction of said first chip carrier;a first interconnect means for electrically coupling a number of said second pads of said first carrier to a corresponding number of second pads of said second carrier with a corresponding number of electrical traces, said first interconnect means providing more electrical traces between said first and second carriers than that required by the electronic system;a second interconnect means for electrically coupling a number of said second pads of said first carrier to a corresponding number of second pads of said third carrier with a corresponding number of electrical traces, said second interconnect means providing more electrical traces between said first and third carriers than that required by the electronic system;a first integrated circuit chip comprising the first group of circuits of the electronic system, said first chip having a plurality of input signals and output signals routed to corresponding interconnect pads formed at the chip's top surface, said interconnect pads being positioned so as to coupled to selected ones of said first pads of said first carrier;a second integrated circuit chip comprising the second group of circuits of the electronic system, said second chip having a plurality of input signals and output signals routed to corresponding interconnect pads formed at the chip's top surface, said interconnect pads being positioned so as to coupled to selected ones of said first pads of said second carrier;a third integrated circuit chip comprising the third group of circuits of the electronic system, said third chip having a plurality of input signals and output signals routed to corresponding interconnect pads formed at the chip's top surface, said interconnect pads being positioned so as to coupled to selected ones of said first pads of said third carrier;wherein the routing of the signals of each said integrated circuit chip to the chip's interconnect pads and the positioning of each chip's interconnect pads are selected to form the electrical connections of the electronic system.