Patent ID: 7284172
Filing Date: 2007-10-16
Classification: G01R

Abstract:
1. An integrated circuit structure comprising: a chip-level test access port (TAP) controller having a chip-level TAP instruction register; and a plurality of embedded TAPs connected to said chip-level TAP controller, wherein said embedded TAPs have instruction register lengths that differ from said chip-level TAP instruction register, wherein said chip-level TAP instruction register comprises a flexible length instruction register, wherein said flexible length instruction register comprises a plurality of instruction register segments, wherein at least two of said instruction register segments comprise multiple bits, wherein said flexible length instruction register is adapted to accommodate different length instruction registers of said embedded TAPs, wherein said flexible length instruction register is longer than a longest embedded TAP instruction register, wherein said flexible length instruction register further comprises additional bit segments, wherein all of said instruction register segments combined are as long as said longest embedded TAP instruction register, wherein said additional bit segments make said flexible length instruction register longer than said longest embedded TAP instruction register, and wherein said additional bit segments comprise bits that are adapted to choose an effective length of said flexible length instruction register.