Patent ID: 6316992
Filing Date: 2001-11-13
Classification: G06J,H03F,H03H

Abstract:
An offset voltage calibration and compensation circuit for use with a digital switching amplifier comprising a frequency selective network and a comparator, the circuit comprising:a memory for storing digital offset data and outputting the digital offset data in response to output level data representative of an output level of the digital switching amplifier, the digital offset data corresponding to a DC offset voltage which corresponds to the output level;a digital-to-analog converter coupled to the memory for receiving the digital offset data and generating an offset compensation voltage for applying to an input port of the digital switching amplifier thereby canceling at least a portion of the DC offset voltage; anda successive approximation register which is used in conjunction with the frequency selective network, the comparator, and the digital-to-analog converter in a calibration mode to generate the digital offset data.