Patent ID: 8873283
Filing Date: 2014-10-28
Classification: G11C,H01L

Abstract:
1. An integrated circuit device comprising: a three-terminal memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor consists essentially of: wherein: data sense circuitry, coupled to the drain region of the electrically floating body transistor of the memory cell via the associated bit line, to sense the first data state and the second data state stored in the memory cell; wherein, in response to voltage transitions in read control signals applied to the gate and source region of the electrically floating body transistor of the memory cell via the associated word line and source line, respectively, when the first data state is stored in the memory cell, the electrically floating body transistor generates a read bipolar transistor current which is representative of the first data state, and wherein the data sense circuitry determines the first data state at least substantially based on the read bipolar transistor current generated by the electrically floating body transistor and represented on the associated bit line.