Patent ID: 6518173
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method of manufacturing a multi-metallization level semiconductor device, which method comprises the sequential steps of:(a) providing a substrate comprising a semiconductor body and an electrically conductive metal region at a surface of said substrate; (b) forming a layer of a dielectric material over said substrate surface and covering said metal region; (c) selectively forming a recess extending through said dielectric layer by use of a dielectric material removal process which is free of fluorine, said recess including interior wall surfaces and a bottom, said bottom exposing a surface portion of said electrically conductive metal region; (d) forming an electrically conductive adhesion/barrier layer lining said interior wall surfaces and said bottom of said recess; and (e) filling said recess with an electrically conductive metal material formed over said adhesion/barrier layer and in electrical contact with said exposed surface portion of said electrically conductive metal region, thereby substantially preventing deleterious effects on the adhesion/barrier layer due to presence of fluorine or fluorine-containing contaminant(s) at said exposed surface portion.