Patent ID: 6040220
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A method for forming a transistor, comprising:forming a gate dielectric upon a semiconductor substrate;patterning a gate conductor extending upon the gate dielectric along an axis, wherein the gate conductor comprises a pair of sidewall surfaces spaced an equal distance from and parallel to said axis;removing an upper portion of the gate conductor laterally bounded by said axis and one of said pair of sidewall surfaces to form a partially retained area of the gate conductor extending along the axis adjacent a fully retained area of the gate conductor, wherein a thickness of the gate conductor adjacent to the one of said pair of sidewall surfaces is less than a thickness of the gate conductor adjacent to the other of said pair of sidewall surfaces; andforwarding a plurality of ionized atoms toward the gate conductor at an energy level which allows a portion of said plurality of atoms to extend through the partially retained areas of the gate conductor and form a lightly doped drain (LDD) region within the substrate directly beneath the partially retained area.