Patent ID: 6680981
Filing Date: 2004-01-20
Classification: H04L

Abstract:
A &pgr;/4 shift QPSK modulator comprising:phase information computing means for computing a QPSK modulation signal according to an input signal, and outputting a signal representing phase information of the modulation signal; impulse response computing means for computing and outputting impulse response data corresponding to a signal representing the phase information derived from the phase information computing means; and impulse response cumulating means for cumulating the impulse response data derived from the impulse response computing means, and outputting the modulation signal based on a result of the cumulation, wherein the impulse response computing means comprises: shift registers of an even number of stages for delaying signals representing the phase information derived from the phase information computing means one after another in every symbol cycle; a plurality of impulse response storage sections for previously storing therein divided impulse response data in every symbol interval, the divided impulse response data being obtained through steps of determining impulse response data by oversampling a one-side waveform of a bilaterally symmetrical impulse response waveform corresponding to a magnitude â€œ1â€  of I component and Q component of a signal representing the phase information, and a one-side waveform of a bilaterally symmetrical impulse response waveform corresponding to a magnitude â€œ1/{square root over (2)}â€  of I component and Q component of a signal representing the phase information, respectively, based on a clock having a cycle which is a multiple of the symbol cycle, and dividing the individual impulse response data into symbol intervals which counts a half of the number of stages of the shift registers; a read address control section for outputting a read address signal to each of the impulse response storage sections so that for a symbol interval of impulse response data that has been stored in the impulse response storage sections, impulse response data of the symbol interval is read out in a forward direction, while for a symbol interval of impulse response data that has not been stored in the impulse response storage sections, impulse response data of a symbol interval that is bilaterally symmetrical with the symbol interval is read out in a reverse order, based on the magnitude â€œ1â€  or â€œ1/{square root over (2)}â€  of I component and Q component of signals representing phase information of the stages delayed by the shift registers; and a numerical value conversion section for performing sign inversion and zero replacement of impulse response data read out from the impulse response storage sections according to signals representing phase information of the stages delayed by the shift registers.