Patent ID: 6509232
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A method for forming STI (shallow trench isolation) structures of a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein, the method including the steps of:A. forming tunnel dielectric material on said core area and said periphery area of said semiconductor substrate; B. forming a first floating gate material on said tunnel dielectric material of said core area and said periphery area of said semiconductor substrate; C. patterning a first hardmask material to etch a first set of STI (shallow trench isolation) openings through said first floating gate material, said tunnel dielectric material, and said semiconductor substrate within said core area, and to etch a second set of STI (shallow trench isolation) openings through said first floating gate material, said tunnel dielectric material, and said semiconductor substrate within said periphery area; wherein a core active device area of said semiconductor substrate within said core area is surrounded by said first set of STI openings, and wherein a periphery active device area of said semiconductor substrate within said periphery area is surrounded by said second set of STI openings; D. forming a dielectric liner at sidewalls of said first and second sets of STI openings with reaction of said semiconductor substrate at said sidewalls of said STI openings such that corners of said semiconductor substrate of said core and periphery active device areas adjacent said STI openings are rounded; E. depositing a trench dielectric material to fill said STI openings; F. etching away said first hardmask material; G. forming a second floating gate material over any remaining portion of said first floating gate material and on said trench dielectric material within said core area and said periphery area; H. patterning a second hardmask material to remain on said second floating gate material over said core active device area and over said whole periphery area; and I. etching away said second floating gate material exposed through said second hardmask material on said trench dielectric material within said core active device area.