Patent ID: 6350674
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A manufacturing method for a semiconductor device having a plurality of wiring layers and an insulation layer present between said wiring layers, said manufacturing method comprising:(A) forming an insulation layer on a first wiring layer; (B) forming in a top part of said insulation layer a wiring trench in an area where a second wiring layer will be formed, and forming in a bottom part of said insulation layer a through-hole in an area where a contact layer for electrically connecting said second wiring layer and said first wiring layer will be formed; and (C) filling a conductive material into said wiring trench and said through-hole to integrally form said second wiring layer in said wiring trench with said contact layer in said through-hole; and wherein said step (B) comprises: (a1) forming a first resist layer with a first photosensitivity characteristic on said insulation layer, said first resist layer having a first opening above an area where said through-hole is to be formed, and (a2) forming a second resist layer on said first resist layer, said second resist layer having a second photosensitivity characteristic that is different from said first photosensitivity characteristic of said first resist layer, and said second resist layer having a second opening above an area where said wiring trench is to be formed; and (b) etching said insulation layer and removing said first and second resist layers during the etching of said insulation layer.