Patent ID: 8900996
Filing Date: 2014-12-02
Classification: H01L

Abstract:
1. A method of fabricating a through silicon via structure, comprising: providing a substrate; forming a first dielectric layer on the substrate; patterning the first dielectric layer to have a plurality of first openings, wherein a bottom of the plurality of first openings is located lower than an original surface of the substrate; forming a via hole in the first dielectric layer and the substrate, wherein the via hole not overlapping for all of the plurality of first openings; forming a second dielectric layer on the first dielectric layer in compliance with a shape of the first dielectric layer while filling the plurality of first openings, the second dielectric layer having a plurality of second openings corresponding to the plurality of first openings, the second dielectric layer covering a sidewall of the via hole; forming a conductive material layer to fill the via hole and the plurality of second openings; and planarizing the conductive material layer to form a through silicon via within the via hole.