Patent ID: 8481381
Filing Date: 2013-07-09
Classification: H01L,Y02P

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: determining a degree of exposure of an end portion of a gate electrode structure of a first N-channel transistor upon forming a first resist mask above said gate electrode structure, said end portion being formed above an isolation region separating an active region of said first N-channel transistor from an active region of a first P-channel transistor, said first N-channel and P-channel transistors being formed above a first substrate according to a predefined transistor design; and forming a second N-channel transistor and a second P-channel transistor according to said predefined transistor design above one or more second substrates by taking into consideration said determined degree of exposure so as to substantially avoid exposure of an end portion of a gate electrode structure of said second N-channel transistor formed above said one or more second substrates when forming a second resist mask for covering said gate electrode structure of said second N-channel transistor.