Patent ID: 6745120
Filing Date: 2004-06-01
Classification: F02D

Abstract:
A vehicle-mounted electronic control apparatus comprising:a microprocessor in which a program memory, an operational RAM, an interface circuit providing a connection to a first vehicle-mounted sensor group, an interface circuit providing a connection to a first electrical load group, and a serial-parallel converter for master station are bus-connected; and a common control circuit in which a serial-parallel converter for substation that is serial-connected to said serial-parallel converter for master station, an interface circuit providing a connection to a second vehicle-mounted sensor group, and an interface circuit providing a connection to a second electrical load group are bus-connected, the common control circuit being provided with first storage means, second storage means, abnormality determination means, distribution storage means, reply packet generation means, and reply packet composing means; wherein said first storage means stores in sequential order command data, address data, write data, sum check collation data received by said serial-parallel converter for substation via said serial-parallel converter for master station; said abnormality determination means monitors lack or mixing of any bit information in the data stored in said first storage means; said distribution storage means transfers said write data to a device memory of a specified address based on said stored address data and said write data when said command data stored in said first storage means is a write/setting command accompanied by said write data; said reply packet generation means selects reply data based on the result determined by said abnormality determination means and said command data, combines said reply data with said address data to synthesize reply information, and said reply information generated by said reply packet generation means is stored in sequential order into said second storage means and read out on the basis of a preceding input/preceding output while evacuating a delay in replying; and said reply packet composing means composes in a predetermined order plural reply information to be supplied to said serial-parallel converter for substation based on said reply information read out from said second storage means, and generates additional data based on the latest information and adds those data to said delayed and held reply information to send back resultant reply information.