Patent ID: 7838977
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. An electronic package for containing a vertical semiconductor chip comprising: a laminated board having a via connector and conductive traces distributed on multiple layers of said laminated board connected to said via connector and a top and bottom patterned metal plates functioning as a conductive plate and a solder mask respectively wherein said solder mask covering over an extensive area of a soldering surface of said laminated board for face-to-face soldering and attaching to a flat-surface electrode of said semiconductor chip and wherein said solder mask extends laterally to an area equal to or smaller than said flat-surface electrode for face-to-face soldering to said solder mask; said electronic package further includes a plurality of ball grid array (BGA) solder pads disposed at outer edges of said soldering surface separated from said solder mask and a plurality of solder balls soldered onto said BGA solder pads disposed on the outer edges of the soldering surface; and said vertical semiconductor chip further includes solder bumps extend vertically from a top surface opposite said flat-surface electrode of said semiconductor chip and extended vertically upward to substantially a same vertical level as said solder balls for conveniently mounting together, with said solder balls onto terminals disposed on a top-mounting print circuit board.