Patent ID: 6088602
Filing Date: 2000-07-11
Classification: H04W,Y02D

Abstract:
A high resolution calibrator for calibrating a sleep mode clock in a wireless communications mobile station to a chip rate clock operating at a chip rate and which can be turned off during sleep mode, wherein data is segmented into frames having a duration T0, and the mobile station includes a super chip rate clock which operates at a frequency S which is N times the chip rate, and a frame counter which contains a value FRMS at the end of a calibration period, said calibrator comprising:a first counter which counts T0*S cycles of the super chip rate clock through one data frame, then rolls over to zero;a second counter which counts cycles of the sleep mode clock;a first register which stores a first value CNTSLP which is input from the second counter at the end of a calibration period and subsequently at wake up time;a second register which stores a second value SYSTIME1 which is input from the first counter at the beginning of a calibration period;a third register which stores a third value SYSTIME2 which is input from the first counter at the end of a calibration period,wherein wake up time is calculated using a relative frequency which is equal to[SYSTIME2-SYSTIME1+(T0*S)(FRMS)]/CNTSLP.