Patent ID: 8837570
Filing Date: 2014-09-16
Classification: H04L

Abstract:
1. An apparatus for equalizing an input signal to a receiver, comprising: an analog-to-digital converter configured to digitize the input signal to form digitized symbols; a parallelizer assembling the digitized symbols from the analog-to-digital converter into a parallel sets of M digitized symbols, where M is an integer greater than one; N serial buffers, each buffer having C slots of M locations per slot, each buffer configured to store one of the sets of M digitized symbols from the parallelizer in a slot therein, where C is an integer greater than zero and N is an integer greater than one; and N decision feedback equalizers responsive to tap weight coefficients and configured to produce parallel sets of M recovered data bits, each decision feedback equalizer coupled to a corresponding one of the N serial buffers and configured to process digitized symbols stored in the corresponding one of the N serial buffers.