Patent ID: 6711081
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A memory device comprising:a memory cell array having a plurality of memory cells, first and second bitlines, and first and second wordlines, each of said memory cells being coupled to one of said first bitlines, one of said second bitlines, one of said first wordlines and one of said second wordlines; a first wordline decoder being coupled to said multitude of first wordlines to activate one of said wordlines; a second wordline decoder being coupled to said multitude of wordlines to activate one of said second wordlines; wherein each of said first and second wordline decoders is designed to perform an access to one of said memory cells by enabling one of the multitude of said wordlines; a refresh control circuit arrangement including a contention circuit that allocates a refresh to one of said wordline decoders, whereby said one of said wordline decoders is currently not used for an external access to one of the memory cells of said memory cell array; and wherein said contention circuit is designed to select said one of said first and second wordline decoders to perform a refresh operation to said memory cells conected to said multitude of worklines coupled to said one of said first and second wordline decoders and is designed to select another one of said first and second wordline decoders to perform an external access and to issue a wait cycle for said one of said first and second decoders when said one wordline decoder receives an external request for an access.