Patent ID: 6124735
Filing Date: 2000-09-26
Classification: G06F,G11C,H03K

Abstract:
A logic device with improved capacitance isolation, comprising:an output signal having a first internal evaluate node and a second internal evaluate node;a first input signal having a first input wire and a second input wire, the first input wire corresponding to a first possible value of the first input signal and the second input wire corresponding to a second possible value of the first input signal;a first plurality of intermediate nodes including a first intermediate node;a first plurality of transistors, includinga first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal; anda second transistor coupling the second internal evaluate node to the first intermediate node and being gated by the second wire of the first input signal, wherein at most one of the first internal evaluate node and the second internal evaluate node is electrically coupled to the first intermediate node, the second transistor substantially preventing residual charge on the second internal evaluate node from being passed to the first intermediate node when the first input value corresponds to the first possible value.