Patent ID: 6566919
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A power reset signal generator comprising:a first voltage divider having an output for providing a first reference signal in response to an applied power signal having a ramp time, the first reference signal being substantially equal to the voltage of the applied power signal for at least a portion of the ramp time in the event that the voltage of the applied power signal is less than a threshold voltage and being substantially proportional to the voltage of the applied power signal in the event that the voltage of the applied power signal is greater than the threshold voltage; an inverter coupled to the output of the first voltage divider; a second voltage divider having a first input coupled to an output of the first voltage divider, having a second input coupled to the output of the inverter, and having an output for providing a second reference signal; and a NAND gate having a first input coupled to the output of the first voltage divider, having a second input coupled to the output of the second voltage divider, and having an output for providing a power reset signal in response to the first and second reference signals.