Patent ID: 9143780
Filing Date: 2015-09-22
Classification: G06T,G09G,H04N

Abstract:
1. An apparatus comprising: a central processing unit; a graphics processing unit comprising an array of software-configurable general purpose parallel processors and a globally shared memory, wherein each of the software-configurable general purpose parallel processors in said array of software-configurable general purpose parallel processors has access to said globally shared memory; and a memory accessible by said central processing unit, said memory storing computer executable instructions, said computer executable instructions when executed by said central processing unit configuring said graphics processing unit to (i) store a current frame, at least one reference frame, and a reconstructed frame in said globally shared memory of the graphics processing unit and (ii) perform a decimation routine configured to receive pixel data of an input frame and pixel data of a reference frame as inputs, produce a plurality of decimated versions of the input and the reference frames, and store the decimated versions of the frames in said globally shared memory of the graphics processing unit.