Patent ID: 6287899
Filing Date: 2001-09-11
Classification: G03F,H01L

Abstract:
A method for manufacturing a thin film transistor array panel for a liquid crystal display, comprising steps of:forming a gate wire including a plurality of gate lines, gate electrodes and gate pads, and a common wire including common signal line and common electrodes on a substrate having a display area and a peripheral area, wherein the gate lines, and the gate electrodes, and the common wire are located substantially in the display area and the gate pads are located substantially in the peripheral area;forming a gate insulating layer pattern covering portions of the gate wire and the substrate in the display area and exposing at least a part of each gate pad;forming a semiconductor pattern on the gate insulating layer pattern;forming an ohmic contact layer pattern on the semiconductor pattern;forming a data wire including a plurality of data lines, source electrodes, and drain electrodes located substantially in the display area and a plurality of data pads located substantially in the peripheral area on the ohmic contact layer pattern;forming a passivation layer pattern; andforming a pixel wire including a plurality of pixel electrodes and pixel signal lines and which is connected to the drain electrodes,wherein the gate insulating layer pattern is formed along with at least the semiconductor pattern and the passivation layer pattern through a single photolithography process using a photoresist pattern having a thickness that varies depending on position.