Patent ID: 6393529
Filing Date: 2002-05-21
Classification: G06F

Abstract:
A multiprocessing computer system comprising:a plurality of processing nodes interconnected through an interconnect structure, wherein said plurality of processing nodes includes: a first processing node with a cache memory, wherein said first processing node is configured to identify a dirty cache line in said cache memory that is to be written into a designated memory location and to generate a first memory write operation to transfer said dirty cache line to said designated memory location; and a second processing node configured to receive said dirty cache line and to responsively initiate a second memory write operation to write said dirty cache line received from said first processing node into said designated memory location, wherein said second processing node is further configured to transmit a target done message to said first processing node upon receiving said dirty cache line, wherein said first processing node is configured to transmit a memory cancel response to said second processing node when said first processing node receives an invalidating probe prior to receiving said target done message, and wherein said memory cancel response causes said second processing node to abort further execution of said second memory write operation.