Patent ID: 8957843
Filing Date: 2015-02-17
Classification: G09G

Abstract:
1. A gate selection circuit comprising: a clock generation circuit generating an enable clock signal generated by frequency-dividing a predetermined horizontal synchronization signal synchronized with an image signal corresponding to an image to be displayed on an active matrix liquid crystal panel that includes a plurality of pixels arranged in a matrix format and has a thin film transistor switch, a liquid crystal capacitor, and an accumulating capacitor at a plurality of regions intersected by a plurality of gate lines and a plurality of accumulating capacity driving lines disposed in a horizontal direction and a plurality of source lines disposed in a vertical direction, the clock generation circuit generating a plurality of clock signals independence upon a predetermined vertical synchronization clock signal and the enable clock signal, the plurality of clock signals differing in phase from one another, and a frequency of the enable clock signal being less than a frequency of the predetermined horizontal synchronization signal; a plurality of first latch circuits at least including a previous first latch circuit, a current first latch circuit, and a next first latch circuit and connected in series so as to form a shift register, the current first latch circuit receiving a signal output from the previous first latch circuit and outputting another signal to the next first latch circuit for shifting hold information in synchronization with the enable clock signal; and a first switch circuit installed in correspondence to the gate lines, and wherein, when supplying a clock signal to each gate line as a gate selection signal for a pixel, said first switch circuit sequentially providing the gate selection signal according to an output signal from the first latch circuit, and wherein the gate selection signal is not applied to the first latch circuits.