Patent ID: 6081864
Filing Date: 2000-06-27
Classification: G06F

Abstract:
A verification system for dynamic verification of functionality of an HDL design of a computer system component configured to interface between a first bus and a second bus, said verification system being executable by a computer system having a memory and a CPU, said verification system comprising:a simulated model of said HDL design of said computer system component which receives a designated stimulus and responds according to said HDL design;a configuration interpretation mechanism stored in said memory to provide a test configuration for said simulated model of said HDL design, wherein said test configuration is selected based on a plurality of user-supplied parameters, and wherein said test configuration is simulated at run-time;a stimulus file stored in said memory which specifies said designated stimulus to be applied to a simulation of said first bus, wherein operation of said stimulus file is independent of the test configuration selected for said simulated model of said HDL design; anda transaction checker stored in said memory and coupled to receive information relating to bus cycles initiated on a simulation of said second bus by said simulated model in response to said designated stimulus, wherein operation of said transaction checker is independent of the test configuration selected for said simulated model.