Patent ID: 6486702
Filing Date: 2002-11-26
Classification: G11C,H03K

Abstract:
A programmable logic integrated circuit comprising:a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; a plurality of embedded array blocks arranged in a row, programmably coupled to the programmable interconnect lines, wherein each embedded array block includes a RAM block, a first embedded array block is in a column j, and a second embedded array block is in a column j+1, wherein j is an integer; and a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks, wherein the output control signals are coupled to the embedded array blocks via the programmable interconnected lines.