Patent ID: 8473657
Filing Date: 2013-06-25
Classification: H04L

Abstract:
1. A first-in, first-out (FIFO) buffer system for packet switching in a crossbar switch with a speedup factor of m, where m is an integer greater than one, the FIFO buffer system comprising: an arbitration and control module configured to control the flow, through a first logic module, of m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words corresponding to one or more data packets; a staging register to buffer a received data portion; a plurality of one-port memory banks configured to store the received data portions of the one or more data packets, each one-port memory bank having a width W and each being segmented into S portions each having a width W/S, W/S related to the width of the N-bit data word; and a second logic module configured to provide one or more N-bit data words, read from the plurality of one-port memory banks, corresponding to the received m N-bit data portions, wherein in a sequence of clock cycles, the one or more data portions are alternately transferred from corresponding selected segments of the plurality of one-port memory banks in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the plurality of one-port memory banks.