Patent ID: 7321649
Filing Date: 2008-01-22
Classification: H03L,H04N

Abstract:
1. A phase locked loop (PLL) which generates a clock pulse signal at a frequency from a synchronization signal of a cathode ray tube (CRT) monitor, the PLL comprising: a phase frequency detector (PFD) which compares a phase and frequency of the synchronization signal to that of a reference signal, and outputs an up signal or a down signal; a charge pump which outputs a pumping current in response to the up or down signal; a loop filter which outputs a control voltage according to the pumping current; a voltage controlled oscillator (VCO) which outputs a clock pulse signal having a frequency determined by the control voltage; a divider which divides the clock pulse signal by a division ratio and outputs the reference signal; a phase unlock detection circuit which detects an initial phase unlock from the up or down signal for outputting a first detection signal, and outputs a first internal control signal according to the up or down signal; a phase lock/unlock detection circuit which outputs a second detection signal in response to the first internal control signal and the first detection signal; and an output circuit which performs a logic operation on the first detection signal and the second detection signal, and outputs a third detection signal.