Patent ID: 9142549
Filing Date: 2015-09-22
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a first wiring; a second wiring; a third wiring; a fourth wiring; and a memory cell, wherein the first to third wirings intersect with the fourth wiring, wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein one of a source and a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor, wherein a gate of the first transistor is connected to the first wiring, wherein the other electrode of the first capacitor is connected to the second wiring, wherein the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor are connected to the fourth wiring, wherein the other of the source and the drain of the second transistor is connected to the third wiring, wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor, and wherein it is configured that at least three different potentials are applied to the third wiring.