Patent ID: 6391755
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method of fabricating an integrated circuit having both a dynamic random access memory (DRAM) cell and an electrically reprogrammable transistor, the method comprising the steps of:forming active regions on a semiconductor substrate; forming field-effect transistor (FET) source/drain regions in the active regions; forming FET gate regions in the active regions and extending at least partially outside the active region; forming a first insulating layer on the semiconductor substrate; forming a buried contact opening through the first insulating layer and over at least a portion of an electrically programmable transistor gate region outside the active region, thereby exposing at least a portion of the underlying gate region; forming a buried contact opening simultaneously with the forming of the forming of the buried contact layer over the electrically programmable transistor gate region through the first insulating layer and over at least a portion of the source drain region in the DRAM cell, thereby exposing at least a portion of the underlying source/drain region; forming a conductive bottom plate layer within the buried contact openings and on the first insulating layer, thereby physically and electrically contacting the exposed portion of the underlying electrically reprogrammable transistor gate region and the DRAM cell source/drain region; forming a dielectric layer on the conductive bottom plate layer and over the entire substrate to form an interpoly dielectric layer in the electrically reprogrammable transistor while simultaneously form a memory cell dielectric in the DRAM cell; and forming a conductive top plate layer on the dielectric layer to form a control gate electrode in the electrically reprogrammable transistor, and simultaneously form a memory cell capacitor top plate electrode in the DRAM cell.