Patent ID: 6217357
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A semiconductor device manufacturing method comprising:the first step of forming a plurality of isolation regions in a semiconductor substrate, and thereafter forming a first p-type well region for a low power supply voltage compatible n-type MOSFET, a first n-type well region for a low power supply voltage compatible p-type MOSFET, a second p-type well region for a high power supply voltage compatible n-type MOSFET, and a second n-type well region for a high power supply voltage compatible p-type MOSFET that are isolated by said isolation regions;after the first step, the second step of forming a gate oxide film to cover upper surfaces of said first n- and p-type well regions and said second n- and p-type well regions, depositing a polysilicon film on an upper surface of said gate oxide film, and forming gate electrodes by dry etching;after the second step, the third step of ion-implanting a p-type impurity to an entire surface of said semiconductor substrate to form p-type impurity regions in said first n- and p-type well regions and in said second n- and p-type well regions to serve as a prospective low power supply voltage compatible n-type MOSFET formation region, a prospective low power supply voltage compatible p-type MOSFET formation region, a prospective high power supply voltage compatible n-type MOSFET formation region, and a prospective high power supply voltage compatible p-type MOSFET formation region, respectively, and ion-implanting an n-type impurity to said entire surface of said semiconductor substrate to form n-type impurity regions under said p-type impurity regions;after the third step, the fourth step of masking said prospective low power supply voltage compatible p-type MOSFET formation region and said prospective high power supply voltage compatible p-type MOSFET formation region with resists by a first photolithography step, ion-implanting an n-type impurity to invert said p-type impurity region in said prospective low power supply voltage compatible n-type MOSFET formation region and said p-type impurity region in said prospective high power supply voltage compatible n-type MOSFET formation region to n-type impurity regions, and ion-implanting a p-type impurity to invert said n-type impurity region in said prospective low power supply voltage compatible n-type MOSFET formation region and said n-type impurity region in said prospective high power supply voltage compatible n-type MOSFET formation region to p-type impurity regions;after the fourth step, the fifth step of removing said resists formed in the fourth step, and forming double side walls, each constituted by first and second side walls, at said prospective low power supply voltage compatible n-type MOSFET formation region, said prospective low power supply voltage compatible p-type MOSFET formation region, said prospective high power supply voltage compatible n-type MOSFET formation region, and said prospective high power supply voltage compatible p-type MOSFET formation region;after the fifth step, the sixth step of masking said prospective low power supply voltage compatible p-type MOSFET formation region and said prospective low power supply voltage compatible n-type MOSFET formation region with resists by a second photolithography step, and removing said second side walls on said prospective high power supply voltage compatible n-type MOSFET formation region and said prospective high power supply voltage compatible p-type MOSFET formation region by wet etching;after the sixth step, the seventh step of removing said resists formed in said sixth step, masking said prospective low power supply voltage compatible p-type MOSFET formation region and said prospective high power supply voltage compatible p-type MOSFET formation region with resists by a third photolithography step, and forming a DDD structure composed of an n.sup.- -type impurity region and an n.sup.+ -type impurity region in said prospective high power supply voltage compatible n-type MOSFET formation region by impurity ion implantation, while forming a structure, in which said n- and p-type impurity regions formed in the fourth step exist near a gate end in said prospective low power supply voltage compatible n-type MOSFET formation region;after the seventh step, the eighth step of removing said resists formed in the seventh step, masking said prospective low power supply voltage compatible n-type MOSFET formation region and said prospective high power supply voltage compatible n-type MOSFET formation region with resists by a fourth photolithography step, forming p-type source/drain regions in said prospective low power supply voltage compatible p-type MOSFET formation region and in said prospective high power supply voltage compatible p-type MOSFET formation region, and a single drain structure in said prospective high power supply voltage compatible p-type MOSFET formation region, by impurity ion implantation, while forming a structure, in which said p- and n-type impurity regions formed in the third step exist near said gate end in said prospective low power supply voltage compatible p-type MOSFET formation region; andafter the eighth step, the ninth step of removing said resists formed in the eighth step, and performing annealing for activation.