Patent ID: 7006401
Filing Date: 2006-02-28
Classification: G11C

Abstract:
1. A semiconductor memory device having a memory cell array comprised of memory cells requiring refresh, in which a read request or write request is asynchronously given for an access address, wherein the semiconductor memory device comprises: a refresh timer periodically outputting a refresh request signal for said memory cell array; a late write writing control circuit that writes, for said write request, an access address and write data for a write request given in a memory cycle before a memory cycle for the write request by a late write operation; and a refresh control circuit performing a refresh operation for said memory cell array in response to the refresh request signal from said refresh timer, and delaying performance of said refresh operation until a read operation or the late write operation for a memory cell for the read request or the write request is completed when said refresh request signal collides with said read request or said write request, wherein said refresh control circuit includes circuitry that generates a control signal for said refresh operation and a control signal for said read operation or said late write operation based on (i) said refresh request signal and (ii) a delay signal responsive to the colliding of said read request or said write request with said refresh request signal.