Patent ID: 6844587
Filing Date: 2005-01-18
Classification: H01L

Abstract:
1. A method of fabricating a non-volatile memory device, comprising: forming a lower oxide layer on a substrate; forming a sacrificial layer on the lower oxide layer and patterning the sacrificial layer to form an opening; forming a charge trapping layer shaped like at least two spacers along an inner wall of the opening; forming an upper oxide layer covering the sacrificial layer and the charge trapping layer, the upper oxide layer fills a portion of the opening; forming a polysilicon layer on the upper oxide layer for filling a remaining portion of the opening; planarizing an upper surface of the polysilicon layer until the sacrificial layer is exposed to form a self-aligned control gate in the opening; removing the sacrificial layer and the lower oxide layer formed below the sacrificial layer; and forming a source junction region and a drain junction region in the substrate at opposite sides of the control gate.