Patent ID: 7598788
Filing Date: 2009-10-06
Classification: H03K

Abstract:
1. A current-controlled CMOS (C3MOS) wideband variable delay cell circuit, the circuit comprising: a first differential transistor having a first source, a first gate, and a first drain; a second differential transistor having a second source that is directly coupled to the first source of the first differential transistor, a second gate, and a second drain; a first variable current source transistor such that a drain of the first variable current source transistor is directly coupled to the directly coupled first source and second source and a source of the first variable current source transistor is grounded; a first lumped input impedance component that is directly coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor; a second lumped input impedance component that is directly coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor; a first output impedance, having a first output resistor and a first shunt peaking inductor connected in series, that is directly coupled between the first drain of the first differential transistor and a supply voltage; a second output impedance, having a second output resistor and a second shunt peaking inductor connected in series, that is directly coupled between the second drain of the second differential transistor and the supply voltage; a third differential transistor having a third source, a third gate, and a third drain; a fourth differential transistor having a fourth source that is directly coupled to the third source of the third differential transistor, a fourth gate, and a fourth drain; a second variable current source transistor such that a drain of the second variable current source transistor is directly coupled to the directly coupled third source and fourth source and a source of the second variable current source transistor is grounded; and a control module that: the first lumped input impedance component and the second lumped input impedance component operate to perform bandwidth expansion of the wideband differential transistor pair; the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are directly coupled at a first node that is a first differential output of the C3MOS wideband variable delay cell circuit; and the second drain of the second differential transistor, the fourth drain of the fourth differential transistor, and the third gate of the third differential transistor are directly coupled at a second node that is a second differential output of the C3MOS wideband variable delay cell circuit.