Patent ID: 8673755
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device having metal gate, comprising: providing a substrate having a first semiconductor device, a second semiconductor device, a contact etch stop layer (CESL) covering the first semiconductor device and the second semiconductor device, formed thereon, and a first insulating layer covering the CESL, the first semiconductor device and the second semiconductor device respectively having a dummy gate; performing an etching process to remove portions of the first insulating layer to expose a portion of the CESL, a portion of the first semiconductor device and a portion of the second semiconductor device; forming a second insulating layer covering the first semiconductor device and the second semiconductor device on the substrate; performing a first planarization process to remove a portion of the CESL and a portion of the second insulating layer to expose the dummy gates of the first semiconductor device and the second semiconductor device; removing the dummy gates to form a first gate trench in the first semiconductor device and a second gate trench in the second semiconductor device; and forming a first metal gate in the first gate trench and a second metal gate in the second metal gate.