Patent ID: 8893066
Filing Date: 2014-11-18
Classification: G06F

Abstract:
1. A method for semiconductor device circuit design using a single circuit schematic for simulation, parasitic verification, and comparison to a layout, said method comprising: providing a circuit schematic without parasitic effects to a computer; inserting some but not all parasitic effects into said circuit schematic at identified circuit paths through dynamic extraction, using said computer; simulating operation of said circuit using said circuit schematic with said inserted some but not all parasitic effects using said computer; generating a complete layout of said semiconductor device circuit using said circuit schematic with said inserted some but not all parasitic effects if said circuit schematic with said inserted some but not all parasitic effects, operates according to specification in said simulating, using said computer; comparing said complete layout to said circuit schematic with said inserted some but not all parasitic effects by performing an LVS (Layout Versus Schematic) check using said computer; inserting all said parasitic effects of said complete layout, into said circuit schematic thereby providing a netlist of a parasitic effects containing circuit; and carrying out a post-layout circuit simulation of said parasitic effects containing circuit using said netlist of said parasitic effects containing circuit.