Patent ID: 8135890
Filing Date: 2012-03-13
Classification: E04B,E04C,G06F

Abstract:
1. A system, comprising: a memory controller that includes control logic; a first memory device; a second memory device; and a memory bus having a first bus segment coupled to the memory controller and the first memory device, a second bus segment coupled to the second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic, wherein the control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate; and wherein the control logic outputs control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.