Patent ID: 6166945
Filing Date: 2000-12-26
Classification: G11C

Abstract:
In a memory cell construction comprising a plurality of memory cells each having an NMOS transistor provided with a gate and a drain which are connected to a word line and a bit line, respectively, and a cell capacitor of which an electrode is connected to a source of the NMOS transistor and the other electrode is connected to an input terminal of a cell plate voltage, and a sense amplifier connected to a pair of bit lines for amplifying a datum, a method for controlling a memory cell, the method comprising:maintaining a voltage of the cell capacitor at a Vdd level that is the same as a voltage level on the bit line, in accordance with a word line signal of a Vpp level and the cell plate voltage of V1 during a first interval;maintaining the voltage of the cell capacitor at a Vdd level in accordance with the cell plate voltage of a Vss level and a word line signal of a Vdd level during a second interval; andraising the voltage of the cell capacitor up to Vdd+.DELTA.V in accordance with the word line signal of the Vdd level and the cell plate voltage of V1 during a third interval.