Patent ID: 7024605
Filing Date: 2006-04-04
Classification: G01R

Abstract:
1. A flip-flop for receiving and latching a data signal from a data terminal in a normal operation, and receiving and latching a signal from a scan input terminal in a scan path test operation, said flip-flop comprising: a control terminal for receiving a control signal, which controls mode changeover between a scan path test mode and a normal operation mode; a set terminal for receiving a set signal, which sets the state of said flip-flop; a reset terminal for receiving a reset signal, which resets the state of said flip-flop; a first logic circuit, which receives the control signal and set signal from said control terminal and said set terminal, respectively, for exercising control so as to inhibit transmission of the set signal, which has been entered from said set terminal, when the control signal indicates the scan path test mode, thereby not allowing the state of said flip-flop to be set by the entered set signal; and a second logic circuit, which receives the control signal and reset signal from said control terminal and said reset terminal, respectively, for exercising control so as to inhibit transmission of the reset signal, which has been entered from said reset terminal, when the control signal indicates the scan path test mode, thereby not allowing the state of said flip-flop to be reset by the entered reset signal; wherein said flip-flop is comprised of a master/slave-type flip-flop including first and second logic gates having input and output terminals electrically connected to each other to compose a master latch, and third and fourth logic gates having input and output terminals electrically connected to each other to compose a slave latch; wherein an output of said first logic circuit is connected to an input terminal of said first logic gate of said master latch, an output of said first logic gate fed to said second logic gate and to an input terminal of said fourth logic gate, which composes said slave latch, via a first switch and a second switch; wherein said first switch and said second switch are provided in series, said first switch maintaining an ON state during a normal operation and being turned ON/OFF by a scan clock during scan path test, said second switch being turned ON/OFF by the clock during the normal operation and maintaining the ON state during scan test; and wherein an output of said second logic circuit is connected to an input terminal of said second logic gate that composes said master latch and to an input terminal of said third logic gate that composes said slave latch.