Patent ID: 6703665
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A transistor comprising:a semiconductor substrate having a drain layer of a first conductivity type and a withstand voltage region of a second conductivity type disposed on said drain layer; a conductive region of the first conductivity type formed by an impurity partly diffused into the semiconductor substrate from the side of said withstand voltage region, said conductive region having a bottom connected to the drain layer of the first conductivity type; a base region of the second conductivity type formed by an impurity partly diffused into the semiconductor substrate from a surface of said withstand voltage region; a source region of the first conductivity type formed in said base region; a gate insulating film having a central region positioned on said base region, an end positioned on said conductive region, and an opposite end positioned on said source region; a gate electrode film disposed on said gate insulating film; a channel region positioned between said source region and said conductive region and including a surface of said base region below said gate insulating film; a source electrode electrically connected to said source region and said base region; and a drain electrode electrically connected to said drain layer, wherein said base region is spaced from said conductive region, said gate insulating film and said gate electrode film are disposed on the surfaces of said source regions, said base region, said withstand voltage region and said conductive regions, said gate insulating film being in direct contact with said base region and said withstand voltage region, said base region being in contact with said source electrode, and said withstand voltage region is sandwiched between said base region and said conductive region, wherein said channel region includes the surface of said withstand voltage region below said gate insulating film.