Patent ID: 7760317
Filing Date: 2010-07-20
Classification: G02F

Abstract:
1. A thin film transistor array substrate, comprising: a gate line provided on a substrate; a data line crossing the gate line to define a pixel area; a thin film transistor at the crossing of the gate and data lines; a pixel electrode at the pixel area, which is contacted directly on the substrate and connected to a drain electrode of the thin film transistor; a gate pad connected to the gate line; and a data pad connected to the data line, wherein the gate pad and the data pad contacts the substrate and includes an exposed transparent conductive material, wherein a portion of the drain electrode is on a portion of the pixel electrode, and the pixel electrode includes the transparent conductive material at the same layer, wherein the gate pad includes the transparent conductive material, the thin film transistor array substrate further including a gate metal material on the transparent conductive material of the gate pad, wherein at least a portion of the transparent conductive material of the gate pad is exposed by a contact hole, and wherein the transparent conductive materials of the gate pad and data pad are contacted on the substrate, wherein a gate insulating patterns are formed only on the gate pad, the gate line and a gate electrode respectively.