Patent ID: 7378867
Filing Date: 2008-05-27
Classification: H03K

Abstract:
1. A differential input/output cell for a field programmable gate array comprising: a first input line; a second input line; a first output line; a second output line; a first input/output line coupled to a first input/output pad; a second input/output line coupled to a second input/output pad; a first differential amplifier having a non-inverting input coupled to the first input/output line, an inverting input coupled to one of a reference voltage and the second input/output line, and an output; a first input multiplexer having a first data input coupled to the first input/output line, a second data input coupled to the output of the first differential amplifier, a control input, and an output; a first input delay multiplexer having a first data input coupled to the output of the first input multiplexer, a second data input coupled to the output of the first input multiplexer through a delay element, a control input, and an output coupled to the first input line; a second differential amplifier having a non-inverting input coupled to the second input/output line, an inverting input coupled to the reference voltage, and an output; a second input multiplexer having a first data input coupled to the second input/output line, a second data input coupled to the output of the second differential amplifier, a control input, and an output; a second input delay multiplexer having a first data input coupled to the output of the second input multiplexer, a second data input coupled to the output of the second input multiplexer through a delay element, a control input, and an output coupled to the second input line; a first output buffer; a second output buffer; a first output multiplexer having a first data input connected to the first output line, a second input connected to the first output line through a delay element, a control input, and an output coupled to the input of the first output buffer; a second output multiplexer having a first data input connected to the second output line, a second input connected to the first output line through an inverter, a control input, and an output coupled to the input of the second output buffer; and programmable elements coupled to the control inputs of the first and second input multiplexers, the first and second input delay multiplexers, and the first and second output multiplexers to select between signals at the first data inputs and the second data inputs of the first and second input multiplexers, the first and second input delay multiplexers, and the first and second output multiplexers.