Patent ID: 6750678
Filing Date: 2004-06-15
Classification: H03K

Abstract:
A method for increasing the load capacity of clocked half-rail differential logic circuits comprising:providing a first synchronous modified clocked half-rail differential logic circuit, said first synchronous modified clocked half-rail differential logic circuit comprising: a first synchronous modified clocked half-rail differential logic circuit first clock input terminal; a first synchronous modified clocked half-rail differential logic circuit second clock input terminal; at least one first synchronous modified clocked half-rail differential logic circuit data input terminal; and at least one first synchronous modified clocked half-rail differential logic circuit data output terminal; providing a second synchronous modified clocked half-rail differential logic circuit, said second synchronous modified clocked half-rail differential logic circuit comprising: a second synchronous modified clocked half-rail differential logic circuit first clock input terminal; a second synchronous modified clocked half-rail differential logic circuit second clock input terminal; at least one second synchronous modified clocked half-rail differential logic circuit data input terminal; and at least one second synchronous modified clocked half-rail differential logic circuit data output terminal; coupling a first clock signal to said first synchronous modified clocked half-rail differential logic circuit first clock input terminal; coupling a second clock signal to said second synchronous modified clocked half-rail differential logic circuit first clock input terminal and said first synchronous modified clocked half-rail differential logic circuit second clock input terminal; coupling said at least one first synchronous modified clocked half-rail differential logic circuit data output terminal to said at least one second synchronous modified clocked half-rail differential logic circuit data input terminal; and delaying said second clock signal with respect to said first clock signal such that said second clock signal is said first clock signal delayed by a predetermined fixed delay time so that said second synchronous clocked half-rail differential logic circuit is switched only after it has received an input from said first second synchronous clocked half-rail differential logic circuit.