Patent ID: 9064942
Filing Date: 2015-06-23
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of fabricating an electronic device, comprising: providing a SOI wafer having an SOI layer over a BOX; etching at least one first set of nanowires and first set of pads in the SOI layer and at least one second set of nanowires and second set of pads in the SOI layer, wherein the first set of pads are attached at opposite ends of the at least one first set of nanowires in a ladder-like configuration and wherein the second set of pads are attached at opposite ends of the at least one second set of nanowires in another a ladder-like configuration; forming a first gate stack that surrounds at least a portion of each of the at least one first set of nanowires that serves as a channel region of a capacitor device, wherein portions of the at least one first set of nanowires extending out from the first gate stack and the first set of pads serve as source and drain regions of the capacitor device; forming a second gate stack that surrounds at least a portion of each of the at least one second set of nanowires that serves as a channel region of a field effect transistor (FET) device, wherein portions of the at least one second set of nanowires extending out from the second gate stack and the second set of pads serve as source and drain regions of the FET device; selectively doping the source and drain regions of the FET device; performing a first deposition of at least one metal selectively on only the source and drain regions of the capacitor device; performing a second deposition of the at least one metal concurrently on both i) the source and drain regions of the capacitor device and ii) the source and drain regions of the FET device such that the at least one metal is deposited on the source and drain regions of the capacitor device in multiple deposition steps; forming a first silicide with the at least one metal on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack; and forming a second silicide with the at least one metal on the source and drain regions of the FET device.