Patent ID: 6951773
Filing Date: 2005-10-04
Classification: H01L

Abstract:
1. A chip packaging process, comprising: (a) providing a base substrate; (b) forming an isolating layer on the base substrate; (c) forming a multi-layered interconnection structure on the isolating layer, wherein the multi-layered interconnection structure includes inner electrical circuits that are electrically connected to a plurality of contact pads formed on a bottom surface of the multi-layered interconnection structure; (d) mounting at least one chip on the top surface of the multi-layered interconnection structure, the chip being electrically connected to the inner electrical circuits; (e) attaching a heat sink on the top surface of the multi-layered interconnection structure, wherein the heat sink having at least one cavity that receives the chip therein; (f) removing the base substrate; and (g) forming a plurality of openings through the isolating layer to respectively expose the contact pads.