Patent ID: 6365459
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method for fabricating split gate flash memory cells comprising the steps of:(a) forming a floating gate with an overlaying poly oxide layer on a substrate, wherein said floating gate and said poly oxide layer are both etched to have a reentrant angle such that the width of said floating gate and said poly oxide layer generally increases with a distance from said substrate; (b) forming a CVD nitride sidewall spacer around said floating gate and said poly oxide layer by performing a CVD nitride deposition, followed by anisotropic etching of said CVD nitride to form a nitride sidewall spacer adjacent to said floating gate and said poly oxide layer and cause a sharp angle to be preserved in said floating gate; (c) forming a control gate on the floating gate wherein said control gate and said floating gate are separated by said poly oxide and said nitride spacer; and (d) forming a source and drain in said substrate using a source and drain implantation.