Patent ID: 8721390
Filing Date: 2014-05-13
Classification: B24B,H01L

Abstract:
1. A method for double-side polishing of a semiconductor wafer comprising: situating the semiconductor wafer in a cutout of a carrier that is disposed in a working gap between an upper polishing plate covered by a first polishing pad and a lower polishing plate covered by a second polishing pad, each of the first and second polishing pads including a regular arrangement of channels having a width and a depth in a range of 0.5 to 2 mm, the channels forming a tiled arrangement of square segments on the respective polishing pads, the square segments of the first polishing pad being greater than 20 mm×20 mm and the square segments of the second polishing pad being less than or equal to 20 mm×20 mm, the square segments of each of first and second polishing pads including abrasives of oxides of an element selected from the group consisting of silicon, aluminum and cerium having an average grain size in a range of 0.1 to 1.0 μm; simultaneous double-side polishing the semiconductor wafer situated in the cutout and guiding the carrier such that a portion of the semiconductor wafer temporarily projects laterally outside of the working gap between the upper and lower polishing plates during the polishing; and supplying a polishing agent solution during the polishing, the polishing agent solution having a pH that is variable in a range of 11 to 13.5 in accordance with a corresponding supply of an alkaline component, the supplying of the polishing agent solution including: