Patent ID: 8966192
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. A memory control system, comprising: a first queue unit for temporarily storing one or more first request instructions corresponding to a line-by-line access to a memory; a second queue unit for temporarily storing one or more second request instructions corresponding to a block access to the memory; a first transforming unit for selectively re-assigning memory addresses corresponding to the one or more first request instructions; a second transforming unit for selectively re-assigning memory addresses corresponding to the one or more second request instructions; an arbiter, coupled to the first transforming unit and the second transforming unit, for performing immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory; and a control unit for comparing bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controlling the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.