Patent ID: 8674869
Filing Date: 2014-03-18
Classification: H03M

Abstract:
1. An A/D conversion circuit comprising cascade-connected N stages (N being a predetermined positive integer not less than two) of one-bit A/D converters, each of the one-bit A/D converters, performing analog-to-digital conversion of an input voltage supplied thereto into one bit, the input voltage received in an initial one of the N stages of the one-bit A/D converters being amplified, output, and then sequentially transferred to subsequent ones of the N stages of the one-bit A/D converters to perform A/D conversion in each of the subsequent stages, the A/D conversion circuit performing N-bit A/D conversion as a whole, the one-bit A/D converter being configured to have a direct-current transfer characteristic folded with respect to a center voltage of the input voltage to be analog-to-digital converted, wherein the one-bit A/D converter comprises: first and second amplifier circuits that respectively receive first and second input signals as the input analog voltage of the one-bit A/D converter; a third amplifier circuit that receives an intermediate value between the first input signal and the second input signal; a comparator that receives an output of the third amplifier circuit to output a binary signal according to a polarity of the output of the third amplifier circuit; and a selector that selects a first set of two outputs comprising the output of the third amplifier circuit and one of outputs of the first and second amplifier circuits, or a second set of two outputs comprising the output of the third amplifier circuit and the other of the outputs of the first and second amplifier circuits, from among the three outputs of the first to third amplifier circuits, using the output of the comparator as a selection control signal and outputs the two outputs of the selected set, as first and second output signals, the first and second output signals output from the selector being supplied to the one-bit A/D converter in a subsequent one of the N stages as first and second input signals;