Patent ID: 6707326
Filing Date: 2004-03-16
Classification: G06F,H03K

Abstract:
A frequency divider configured to provide an output signal having a period equal to a period of a clock signal multiplied by a division ratio, the frequency divider comprising:a plurality of edge-triggered storage elements arranged in at least one loop, wherein each storage element has a state, and a clock input, wherein the state of each storage element is determined responsive to a transition of the clock input, the state, or the inverse thereof, of one or more previous storage element in the loop, a characteristic of the division ratio, and the previous state, or the inverse thereof, of said each storage element, and the output signal is derived from the state, or the inverse thereof, of at least one of the other storage elements in the loop, wherein each storage element is configured to normally trigger on a first edge of the clock signal, and to trigger on a second edge of the clock signal when a control signal indicative of the characteristic of the division ratio is in a first predetermined state and the data output of said each storage element is in a second predetermined state, wherein the first edge is selected from a group comprising a positive edge and a negative edge, and the second edge is selected from the group comprising a positive edge and a negative edge, and is other than that of the first edge.