Patent ID: 6620638
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit chip, comprising:forming a plurality of devices on a semiconductor substrate; testing device properties to determine if the devices are functional; forming a first plurality of conductors, wherein the conductors interconnect at least some of the devices; forming a temporary member and a second plurality of conductors adjacent the substrate, wherein the temporary member supports at least some of the second conductors, wherein the temporary member alters at least some of the properties of at least some of the devices; testing the devices at a speed substantially slower that the rated speed of the devices to determine whether the devices are electrically interconnected, wherein the result of the slow speed test is substantially unaffected by the changes in device property brought about by the temporary member; completing formation of the integrated circuit chip; removing the temporary member from the integrated circuit chip; testing the functionality and connectivity of the chip by exercising the chip at its rated speed.