Patent ID: 6069510
Filing Date: 2000-05-30
Classification: H03K

Abstract:
A method of generating first and second complementary signals at first and second output terminals, respectively, responsive to a clock signal, the method comprising:inverting the clock signal to provide an inverted clock signal, the inverted clock signal having transitions that are delayed in time relative to transitions of the clock signal;providing first and second reference voltages;coupling the first output terminal to the first and second reference voltages through first and second switches, respectively;coupling the second output terminal to the first and second reference voltages through third and fourth switches, respectively;rendering the first switch conductive and the fourth switch conductive during a first operational state responsive to a first logic level of the clock signal;rendering the second switch non-conductive and the third switch non-conductive during the first operational state responsive to a second logic level of the inverted clock signal;rendering the first switch nonconductive and the fourth switch nonconductive during a second operational state responsive to the second logic level of the clock signal;rendering the second switch conductive and the third switch conductive during the second operational state responsive to the first logic level of the inverted clock signal; andalternating between the first and second operational states responsive to the clock signal switching between the first logic level and a second logic level.