Patent ID: 6378011
Filing Date: 2002-04-23
Classification: G06F

Abstract:
A serial data apparatus for converting parallel data generated by a digital signal processor (DSP) into asynchronous serial data bytes according to an asynchronous protocol specified by the DSP and in a separate pipeline converting asynchronous serial data to synchronous parallel data, the apparatus comprising:a register module; a receive data FIFO digitally connected to the register module; a transmit data FIFO digitally connected to the register module; a DSP interface digitally connected to the register module comprising a bidirectional control signal bus, a bidirectional DSP data bus, and a read only status bus; a timing control interface digitally connected to the register module, the receive data FIFO, and the transmit FIFO; a asynchronous serial data out (ASDO) pin digitally connected to the timing control interface; and a asynchronous serial data in (ASDI) pin digitally connected to the timing control interface.