Patent ID: 7907429
Filing Date: 2011-03-15
Classification: H02M

Abstract:
1. A voltage regulator circuit, comprising: a load capacitor coupled between an output terminal and a reference potential; a switch matrix comprising a plurality of segmented switched capacitors coupled between a voltage input and the output terminal to provide a transfer capacitor; a feedback circuit for producing a feedback voltage representative of a voltage at the output terminal; clocking circuitry for producing a first clock signal to operate first switches in the plurality of segmented switched capacitors to couple the capacitors between the voltage input and the reference potential during a first clocking phase, and for producing a second clock signal to operate second switches in the plurality of segmented switched capacitors to couple at least one of the segmented switched capacitors between the reference potential and the output terminal during a second clocking phase, the first clock signal and the second clock signal being non-overlapping clock signals having a fixed frequency; and control circuitry for selectively coupling at least one of the segmented switched capacitors to the output terminal during the second clocking phase and for increasing and decreasing a number of segmented switched capacitors coupled to the output terminal during the second clocking phase responsive to the feedback voltage in order to regulate an output voltage; wherein the plurality of segmented switched capacitors further comprises a plurality of stages of switched capacitor circuits, each stage comprising a first gain selection input coupled to first switches to operate a pair of equally weighted capacitors in series during the second clocking phase and a second gain selection input coupled to second switches to operate the pair of equally weighted capacitors in parallel during the second clocking phase, to selectively provide a first and a second gain, each gain being a fractional gain.