Patent ID: 6178122
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:a semiconductor substrate;a booster circuit externally receiving a first power supply potential and a second power supply potential higher than said first power supply potential and generating a boosted potential higher than said second power supply potential;a memory cell array including a plurality of memory cells arranged in rows and columns;a plurality of sub word lines each provided for a first plurality of memory cells along a row of said memory cell array, for selecting said memory cell;a plurality of main word lines corresponding to the rows of said memory cell array;a plurality of sub decode lines for selecting any of said plurality of sub word lines;a sub word line driver circuit provided for said sub word lines, selectively driving a potential level of said sub word line to said boosted potential in response to an activation of a selected main word line and a boost in a potential level of a selected sub decode line;a main row select circuit selectively activating said main word line in response to an address signal; anda sub decode circuit selectively driving the potential level of said selected sub decode line to said boosted potential in response to an address signal, said sub decode circuit includinga pull-up transistor for selectively charging said sub decode line to a level of said boosted potential,a plurality of pull-down transistors for selectively discharging said sub decode line to a level of said first power supply potential, anda substrate current limit circuit limiting a substrate current flowing through said semiconductor substrate to reduce an average in said substrate current for a plurality of discharging operations of said sub decode line per said pull-down transistor.