Patent ID: 8643988
Filing Date: 2014-02-04
Classification: H02H

Abstract:
1. A mixed-voltage electro-static-discharge (ESD) protection circuit comprising: a high-voltage core having high-voltage transistors that have a high snap-back breakdown voltage, the high-voltage transistors being powered by a high-voltage power supply; a low-voltage core having low-voltage transistors that have a lower snap-back breakdown voltage than the high snap-back breakdown voltage; the low-voltage transistors being powered by a low-voltage power supply that has a lower voltage than the high-voltage power supply; a first trigger circuit coupled to the high-voltage power supply that drives high-voltage transistors in the high-voltage core, the first trigger circuit activating a first gate when an ESD pulse is detected on the high-voltage power supply; a second trigger circuit coupled to the high-voltage power supply, the second trigger circuit activating a second gate when the ESD pulse is detected on the high-voltage power supply; a clamp transistor that is connected to shunt current from a drain node to a ground node in response to the first gate, wherein the clamp transistor is a low-voltage transistor having the lower snap-back breakdown voltage; an initial shunt bypass that is activated by the second gate to shunt current from the high-voltage power supply to the drain node in response to the second trigger circuit; and a low-voltage transistor protector coupled between the high-voltage power supply and the drain node, for generating a voltage drop to the drain node, wherein the voltage drop is sufficient to prevent the drain node from reaching the lower snap-back breakdown voltage when no ESD pulse is detected; whereby the clamp transistor is biased to the lower snap-back breakdown voltage by the initial shunt bypass to protect low-voltage transistors in the low-voltage core, and the clamp transistor is protected by the low-voltage transistor protector during normal operation.