Patent ID: 6772368
Filing Date: 2004-08-03
Classification: G06F

Abstract:
A multiprocessing system comprising:a first processor having a first set of architected registers and a first execution pipeline; a second processor having a second set of architected registers and a second execution pipeline; mode control logic, wherein in a first mode the processors independently execute separate instruction streams, and in a second mode both processors execute one instruction stream, wherein in the second mode!for ones of the instructions in the stream each processor computes corresponding versions of a result; compare logic for indicating whether the respective versions of an instruction match; first commit logic and first state recovery means for the first processor; and second commit logic and second state recovery means for the second processor, wherein such a state recovery means for one of the processors operates in both the first and second modes and is for preserving state information and for restoring the state information to the processor; and architected registers, the restoring being responsive to a faulting instruction causing instructions to be aborted in the processor's pipeline, wherein such a faulting instruction includes an instruction causing an arithmetic calculation overflow or underflow wherein responsive to the compare unit indicating a disparity between the versions of one of the results the compare unit signals the first and second commit logics that the corresponding instruction has faulted, and the commit logics permit instructions prior to the faulting instruction in program order to continue execution, but initiate: i) flushing of instructions, and results of the flushed instructions, for instructions following the faulting instruction in program order and ii) the restoring of the state information by the state recovery means.