Patent ID: 6691277
Filing Date: 2004-02-10
Classification: H03M

Abstract:
A system for evaluating an error locator polynomial in a Reed Solomon (RS) decoder for decoding a RS code having a codeword length of x bytes, said error locator polynomial having an associated set of expanded error locator polynomials, said system comprising:a plurality of polynomial evaluating circuit branches connected in parallel, each of the branches corresponding to one of a plurality of p-bit polynomial root coefficient values and each branch having: a first stage for performing logic operations between p-bit values corresponding to polynomial roots and p-bit values corresponding to polynomial coefficients to generate, in each of x clock cycles p-bit values corresponding to partial resultants, said first stage including: a logical pre-computing stage activated by a logical signal during a first clock cycle for performing logical operations between p-bit coefficient values and p-bit root values thus generating a first set of p-bit values corresponding to a first set of partial resultants associated with a first solution of said expanded error-locator polynomials where said first set of partial resultants are stored in registers and said pre-computing stage is deactivated after said first clock cycle, and wherein said logical pre-computing stage includes parallel logic gates having first inputs coupled to one of said polynomial root bit values and second inputs coupled to one of said polynomial coefficient bit values; a second stage for, in each subsequent xâˆ’1 clock cycles, generating a subsequent set of p-bit values corresponding to a subsequent set of partial p-bit resultants associated with a remaining solution of said expanded error locator polynomials where each of said subsequent resultant values is obtained by multiplying a stored partial resultant calculated during a previous clock cycle to an initial condition value of the second stage; wherein said second stage includes a critical timing path and a feedback path and wherein said critical timing path is absent any logical operations; and a summation stage interconnecting said plurality of parallel connected polynomial evaluating circuit branches for performing logic operations on said resultant p-bit values to provide, in each of said x clock cycles, a multiple bit value representing a solution to one of said set of expanded error locator polynomials.