Patent ID: 6260101
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A device, comprising:a bus interface unit configured to provide internal address signals for an execution unit to access one or more memory devices;a direct memory access (DMA) unit configured to provide DMA address signals to access the one or more memory devices; anda memory control unit coupled to said bus interface unit and said DMA unit, wherein said memory control unit is configured to provide memory address signals to the one or more memory devices, said memory control unit comprising:a first banking register configured to provide one or more first bank address signals for selecting one of a plurality of memory banks within the one or more memory devices; andan address generator configured to receive said internal address signals, said DMA address signals, and said first bank address signals;wherein said address generator is configured to generate said memory address signals from said internal address signals and said first bank address signals for accesses to the one or more memory devices from the execution unit, and from said DMA address signals for accesses to the one or more memory devices from the DMA unit.