Patent ID: 8977869
Filing Date: 2015-03-10
Classification: G06F

Abstract:
1. A method for controlling power of an integrated circuit (IC) chip that includes a pulse detector, a latch circuit, and an ON/OFF logic circuit, the method comprising: detecting, by the pulse detector, a signal pulse generated by a partner chip while the IC chip is in an idle mode; amplifying, by the pulse detector, the detected signal pulse by level shifting with a DC bias voltage; generating, by the pulse detector, a latch signal to turn on the latch circuit; decreasing, by the latch circuit, a control signal from a high voltage to a low voltage so as to turn on a power switch that powers on the IC chip; maintaining, by the latch circuit, the control signal at the low voltage for a predetermined time period during the powering on of the IC chip; and decreasing, by the ON/OFF logic circuit, the control signal from the low voltage to a zero voltage until IC chip is fully powered on.