Patent ID: 7157366
Filing Date: 2007-01-02
Classification: H01L

Abstract:
1. A method for forming a metal interconnection layer of a semiconductor device, comprising: forming an interlayer dielectric layer on a substrate; forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer; depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer; forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask; removing the first photoresist pattern; depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole; etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern; completely removing the second photoresist pattern and the photoresist material in the partial via hole; etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole; and filling the full via hole and the trench interconnection area with a conductive material.