Patent ID: 6693319
Filing Date: 2004-02-17
Classification: H01L,Y10S

Abstract:
A portion of a memory array having memory cells operatively coupled to row lines and column lines, the portion of the memory array comprising:a plurality of contacts; a plurality of container capacitors proximal to the contacts, each of the container capacitors having a bottom electrode, a dielectric, and a top electrode; wherein each bottom electrode has a cup-shape; wherein the dielectric is disposed on and in each container capacitor and further disposed between at least one pair of bottom electrodes of the plurality of container capacitors; and wherein the top electrode is disposed on the dielectric, in each container capacitor, and between the at least one pair of bottom electrodes on a first horizontal plane between the at least one pair of bottom electrodes, wherein the first horizontal plane is below a top vertical height of the bottom electrode to provide capacitive coupling between an external surface of the bottom electrode and the top electrode; and an insulating layer disposed between the contacts and bottom electrodes such that the top electrode does not vertically descend below the top vertical height of the bottom electrode in a region between the bottom electrodes and the contacts.