Patent ID: 6759702
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A memory cell structure, comprising:a semiconductor substrate, a deep trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down a sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down the sidewall of the deep trench opposite the storage capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, a bitline extending above the surface plane of the substrate having a contact to the source diffusion between the shallow trench isolation regions, and a buried strap along the sidewall of the deep trench, wherein the deep trench has a perimeter in a direction normal to its depth, said buried strap extends a distance along said perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter and being less than one lithographic feature size, and wherein the buried strap is disposed along only one corner of the perimeter.