Patent ID: 8017488
Filing Date: 2011-09-13
Classification: H01L,Y10S

Abstract:
1. A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations, comprising the steps of: forming a gate structure on a semiconductor substrate; performing a heavily doped source ion implantation process to form a heavily doped first source area in the semiconductor substrate on a side of the gate structure; performing a lightly doped drain ion implantation process to form a lightly doped first drain area in the semiconductor substrate on another side of the gate structure, and the first drain area and the first source area being disposed in the semiconductor substrate on different sides of the gate structure respectively; forming an insulation layer spacer individually on the semiconductor substrate on both sides of the gate structure; and performing a heavily doped drain ion implantation process to form a heavily doped second drain area in the semiconductor substrate on a side of the gate structure, wherein the first drain area is superimposed onto the second drain area, and the heavily doped drain ion implantation process includes two times of implantation process, and a first-time heavily doped drain ion implantation process uses arsenic ions, and a second-time heavily doped drain ion implantation process uses phosphorous ions, wherein the second-time heavily doped drain ion implantation process is performed before the first-time heavily doped drain ion implantation process.