Patent ID: 7047271
Filing Date: 2006-05-16
Classification: G06F

Abstract:
1. A system comprising: a bus; and a digital signal processor comprising: a first multiplexer and a second multiplexer operative to receive a plurality of n-bit data sets from the bus and to select a single n-bit data set from the plurality of n-bit data sets to be processed; a multiplier having a first structure and a second structure, the first structure processing data up to n-bits and the second structure processing data up to (n/2)-bits; and a data size selector which configures the multiplier into the first structure of a single n-bit multiplier when the selected data set is greater than (n/2)-bits and configures the multiplier into the second structure of two (n/2)-bit multipliers when the selected data set is (n/2)-bits or less.