Patent ID: 8120968
Filing Date: 2012-02-21
Classification: G11C

Abstract:
1. A word line driver circuit adapted for connection to a corresponding word line in a memory circuit, the word line driver circuit comprising: a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit; a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal; a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal; wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies.