Patent ID: 6838901
Filing Date: 2005-01-04
Classification: G11C,H03K

Abstract:
1. A semiconductor integrated circuit device comprising; a first CMOS logic circuit block capable of being set in one of an active mode and a standby mode; and a second CMOS logic circuit block capable of being set in one of the active mode and the standby mode; wherein each of the first and the second CMOS logic circuit blocks includes a first MOS transistor of first conductivity type and a second MOS transistor of second conductivity type serially coupled to the first MOS transistor, wherein, in the active mode, active current flows through source-drain paths of the first MOS transistor and the second MOS transistor, wherein, in the standby mode, subthreshold leakage current, which flows through source-drain paths of the first MOS transistor and the second MOS transistor even when a gate-source voltage of one of the first MOS transistor and the second MOS transistor is 0 volts, is reduced, and wherein both the first circuit block and the second circuit block are set in the standby mode in a first state, and one of the first circuit block and the second circuit block is set in the active mode and another of the first circuit block and the second circuit block is set in the standby node in a second state.