Patent ID: 7024518
Filing Date: 2006-04-04
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a primary memory controller; a point-to-point memory data bus, having an effective bit-width m, coupled to the primary memory controller; at least one memory module directly connected to the primary controller via a segment of the memory data bus, the memory module having a module data bus with an effective bit-width N=R×m, where R is an integer value greater than one, the memory module comprising an interface circuit coupled between the memory data bus and the module data bus, the interface circuit capable of performing m-bit-wide data transfers on the memory data bus, the interface circuit capable of performing N-bit-wide data transfers on the module data bus, said interface circuit comprising: one additional segment of the memory data bus for each additional memory module, the additional segment directly connecting the additional memory module to the module immediately preceding it.