Patent ID: 6256243
Filing Date: 2001-07-03
Classification: G11C

Abstract:
In combination with a digital semiconductor circuit configuration formed on a semiconductor chip and having a large number of elements to be tested, a monolithically integrated test circuit for testing the elements to be tested and formed on the semiconductor chip, the test circuit comprising:a read and write circuit for writing and reading a test data pattern having a given width to and from the elements to be tested;a test data pattern register for temporarily storing the test data pattern;a pattern variation circuit receiving and activated by an activation signal and connected to said test data pattern register and to said read and write circuit, said pattern variation circuit varying the test data pattern received from said test data pattern register before writing into the elements to be tested; anda comparison circuit connected to said read and write circuit and to said pattern variation circuit, said comparison circuit testing for a difference between a written data and a read data of the elements to be tested.