Patent ID: 6418062
Filing Date: 2002-07-09
Classification: G11C

Abstract:
A method of erasing a non-volatile memory wherein a memory cell of said non-volatile memory comprises:a first channel forming semiconductor region in a surface of a substrate; an opposite conductivity type region adjacent to said first channel forming semiconductor region and in said surface of said substrate; a first gate insulator on said first channel forming semiconductor region; a first conductive gate on said first gate insulator wherein carrier trap sites lie within said first gate insulator; a second channel forming semiconductor region contacting said first channel forming semiconductor region in said surface of said substrate; a second gate insulator on said second channel forming semiconductor region; and a second conductive gate on said second gate insulator wherein said second conductive gate is separated and insulated from said first conductive gate by an insulator; wherein said method of erasing said non-volatile memory comprises: injecting hot holes into said first gate insulator while negatively or zero biasing said first conductive gate and positively biasing said opposite conductivity region whereby hot holes are generated in a surface of said opposite conductivity region, wherein said positively biasing of said opposite conductivity region with respect to said first channel forming semiconductor region is larger in value than an electric barrier height against said hot holes wherein said electric barrier is formed at an interface between said first gate insulator and said opposite conductivity region; and positively biasing said first conductive gate to a voltage which generates an average electric field of more than 5 MV/cm in said first gate insulator.