Patent ID: 7030449
Filing Date: 2006-04-18
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor integrated circuit device, comprising: a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate; said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate, said first n-channel MISFET being arranged in a first direction adjacent to said first p-channel MISFET such that said gate electrode of said first n-channel MISFET is integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode extending in said first direction, and said second n-channel MISFET being arranged in said first direction adjacent to said second p-channel MISFET such that said gate electrode of said second n-channel MISFET is integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode extending in said first direction; a nitride film containing silicon and nitrogen and formed so as to cover said first common gate electrode and said second common gate electrode and said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs; a first insulating film formed on said nitride film to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said nitride film as an etching stopper to form a first opening and a second opening and such that said nitride film within said openings is etched so as to expose said drain region of said second n-channel MISFET in said first opening and to expose said second common gate electrode and said drain region of said first p-channel MISFET in said second opening; a first conductive film filled in said first opening so as to electrically connect to said drain region of said second n-channel MISFET; and a second conductive film filled in said second opening so as to electrically connect said second common gate electrode and said drain region of said first p-channel MISFET, wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other.