Patent ID: 6642132
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method for manufacturing a complementary metal oxide semiconductor (CMOS) device, comprising:forming a first metal layer on a p-well region of a cell region and a n-well region of a peripheral circuit region of a semiconductor substrate including a gate insulation film; sequentially forming a polysilicon layer and a second metal layer on the entire upper surface of the semiconductor substrate; and forming a first gate electrode having a stacked structure of a first metal layer pattern, a polysilicon layer pattern, and a second metal layer pattern on the p-well of the cell region and the n-well of the peripheral circuit region, and simultaneously forming a second gate electrode having a stacked structure of the polysilicon layer pattern and the second metal layer pattern on a p-well of a peripheral circuit region by etching the first metal layer, the second metal layer and the polysilicon layer via a photolithography process using a gate electrode mask.