Patent ID: 8077536
Filing Date: 2011-12-13
Classification: G11C,H01L

Abstract:
1. A semiconductor memory array, including: a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell including: a substrate having a top surface, said substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type, said first region being formed in said substrate and exposed at said top surface; a second region having said second conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface; a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type; a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type; and a gate positioned between said first and second regions and above said top surface; a source line terminal electrically connected to one of said first and second regions; a bit line terminal electrically connected to the other of said first and second regions; a word line terminal connected to said gate; a buried well terminal electrically connected to said buried layer; and a substrate terminal electrically connected to said substrate below said buried layer; wherein each said memory cell further includes a first data state which corresponds to a first charge in the body region, and a second data state which corresponds to a second charge in the body region; wherein each of said terminals is controlled to perform operations on each said cell; and wherein said terminals are controlled to perform a refresh operation by a non-algorithmic process.