Patent ID: 6289477
Filing Date: 2001-09-11
Classification: G01R

Abstract:
A scan-flop having input terminals and adapted for use in testing integrity of an integrated circuit's core logic, comprising:(a) a synchronous flip-flop having at least one input adapted to receive selected input data from said input terminals and an NQ output operative in response to presence of a clocked enable signal to exhibit a logic state as determined by the selected input data, said NQ output defining a data output terminal for said scan-flop;(b) a logic circuit configured to receive an input lead having a length that is less than about ten (10) microns, said input lead of said logic circuit being electrically coupled to said NQ output, the logic circuit having an output node which defines a scan output terminal for said scan-flop, said scan output terminal being directly coupled to a serial input terminal of a succeeding scan-flop; and(c) a multiplexer operative in response to a select signal to transmit the selected input data to the input of said flip-flop.