Patent ID: 7673268
Filing Date: 2010-03-02
Classification: G06F

Abstract:
1. A method of conducting timing analysis on an integrated circuit design, comprising: performing physical synthesis on the integrated circuit design; performing a first routing operation on the synthesized design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database; performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database; performing extractions on the first and second designs using the first and second design databases to generate first and second extraction files using a system for performing timing analysis; performing first and second delay calculations on the first and second extractions files; comparing the first and second delay calculations to determine a delay difference between the first and second designs; and performing timing analysis using the delay difference.