Patent ID: 6583459
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A random access memory cell, comprising:a first transistor having a control terminal, a first conduction terminal connected to a reference voltage supply and a second conduction terminal; a second transistor having a control terminal connected to the second conduction terminal of the first transistor, a first conduction terminal connected to the reference voltage supply and a second conduction terminal connected to the control terminal of the first transistor; a first transmission gate transistor having a control terminal capable of being connected to a word line, a first conduction terminal capable of being connected to a first bit line of a bit line pair, and a second conduction terminal connected to the second conduction terminal of the first transistor; and a second transmission gate transistor having a control terminal capable of being connected to the word line, a first conduction terminal capable of being connected to a second bit line of the bit line pair, and a second conduction terminal connected to the second conduction terminal of the second transistor; the first transmission gate transistor having a threshold voltage such that a subthreshold leakage current from the first transmission gate transistor maintains the second conduction terminal of the first transistor at a voltage representative of a logic level when the first transistor is turned off, the second transmission gate transistor having a threshold voltage such that a subthreshold leakage current from the second transmission gate transistor maintains the second conduction terminal of the second transistor at a voltage representative of the logic level when the second transistor is turned off, the first and second transistors comprising first and second pull-up transistors, and the random access memory cell being free of cross-coupled pull-down transistors.