Patent ID: 7290226
Filing Date: 2007-10-30
Classification: G06F

Abstract:
1. A method of adding via redundancy within an integrated circuit (IC) design, the method comprising: identifying a plurality of target vias by determining which vias in the IC design do not have a redundant via; prioritizing each target via based on at least one of the following: subnet timing information, a distance of a target via along a path from a driving source and a target via net/subnet characteristic; and adding a redundant via to a target via based on a result of the prioritization; wherein the prioritizing includes: determining a slack amount for a plurality of subnets; prioritizing the respective plurality of subnets according to their respective slack amounts; and assigning a weight to each target via based on the priority of the respective subnet to which each target via belongs and the distance of a respective target via along the path from the driving source.