Patent ID: 7855915
Filing Date: 2010-12-21
Classification: G11C

Abstract:
1. A nonvolatile semiconductor storage device comprising: a memory cell array including a plurality of memory cells in each of which a plurality of bits are stored, the memory cells being arranged in the row direction and in the column direction in a matrix form; a voltage generation circuit configured to generate control voltages including a write voltage for writing data to the memory cell; a sense amplifier configured to detect data read from a memory cell selected from the memory cell array; and a data control circuit configured to control data to be supplied to the sense amplifier, and data read by the sense amplifier, wherein at the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control circuit converts write data to be written to the memory cell into data of a number of times indicating a remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation.