Patent ID: 6614070
Filing Date: 2003-09-02
Classification: G11C

Abstract:
A non-volatile semiconductor device comprising:a semiconductor substrate; data transmission bit lines arranged on said substrate; a memory cell block including a plurality of memory stack units, each connected on a first end to one of said bit lines and on a second end to a common reference node, each of said memory stacks comprising series connected addressable memory transistors and at least one series connected selection transistor on said second end to selectively connect said memory stack unit to a reference potential node, each said memory transistors having a source node, a drain node, a gate, and a charge storage layer that has programmable memory states that produce a first threshold voltage of an absolute magnitude less than an absolute magnitude of a supply voltage when the memory transistor is programmed and a second threshold voltage of absolute magnitude greater than the absolute magnitude of the first threshold voltage when the memory transistor is erased; biasing circuitry for applying selected read biasing voltages to said memory stack units including a reference voltage of magnitude no greater than the magnitude of said supply voltage and greater than the magnitude of said first threshold voltage, the reference voltage being applied to said reference potential node, and a voltage greater than said reference voltage applied to said first end of said memory stack; and sensing circuitry for sensing a current generated at said first end of said memory stack in accordance with the programmable state of said charge storage layer of said addressable memory transistor.