Patent ID: 7581154
Filing Date: 2009-08-25
Classification: G11C

Abstract:
1. A memory apparatus comprising: a memory array with at least one input to receive data; first circuitry coupled with the input and the memory array to run an error correcting code (ECC) on the data to be input to the memory array; second circuitry coupled with an output of the memory array, the second circuitry to receive data from the memory array and run the error correcting code on the data; a comparator to compare the results from the first circuitry and the second circuitry; and an error corrector, coupled with the memory array, to correct the data when errors are detected based on the results of the comparator, wherein an operating voltage of the memory apparatus is adjusted, by increasing or decreasing the operating voltage of the memory apparatus, to reach a threshold error level based on results of the error detection.