Patent ID: 7557560
Filing Date: 2009-07-07
Classification: G01R

Abstract:
1. A timing generator for generating a timing signal based on a given reference clock, comprising: a delaying circuit section for outputting each pulse of said reference clock by delaying by a value of delay given per each of said pulse; a pulse selecting and outputting section for passing and outputting only pulses to be outputted as said timing signal among the pulses outputted out of said delaying circuit section; and a delay control section for incorporating delay setting data for controlling a value of delay in said delaying circuit section corresponding to the pulse outputted out of said delaying circuit section and for controlling the value of delay in said delaying circuit section based on said incorporated delay setting data, wherein said delaying circuit section has a plurality of cascade-connected delay elements; said delay control section has a plurality of delay setting flip-flops provided corresponding to said plurality of delay elements; and each of said delay setting flip-flops incorporates said delay setting data corresponding to the pulse outputted out of the corresponding delay element and controls the value of delay of said corresponding delay element based on said incorporated delay setting data, the timing generator further comprising a pulse selection control section that receives a pulse selecting signal that indicates a logical value H in passing the pulse in said pulse selecting and outputting section and indicates a logical value L in passing no pulse in synchronism with the pulse of the reference clock given to said delaying circuit section to feed said pulse selecting signal to said pulse selecting and outputting section, wherein said pulse selection control section has a plurality of pulse selecting flip-flops cascade-connected and provided corresponding to said plurality of delay elements to sequentially incorporate and output said pulse selecting signal corresponding to the pulse outputted out of said corresponding delay element, and wherein each of said delay setting flip-flops does not newly incorporate said delay setting data during when said corresponding pulse selecting flip-flop outputs the logical value L.