Patent ID: 6061418
Filing Date: 2000-05-09
Classification: H03K

Abstract:
A variable clock divider circuit for generating an output clock signal from an input clock signal, the variable clock divider circuit comprising:a controller coupled to receive the input clock signal and configured to generate a rising-edge control signal having a plurality of active edges, and a falling-edge control signal having a plurality of active edges, the controller having:a first flip-flop having an input terminal, an output terminal, a set terminal, and a clock input terminal coupled to receive the input clock signal;a second flip-flop having an input terminal coupled to the output terminal of the first flip-flop, a reset terminal, an output terminal and a clock input terminal coupled to receive the input clock signal;a third flip-flop having an input terminal coupled to the output terminal of the second flip-flop, a reset terminal, an output terminal, and a clock input terminal coupled to receive the input clock signal;a first multiplexer having an output terminal coupled to the input terminal of the first flip-flop, a first input terminal coupled to the input terminal of the second flip-flop, and a second input terminal coupled to the input terminal of the third flip-flop; anda power-on/reset line coupled to the set terminal of the first flip-flop, the reset terminal of the second flip-flop, and the reset terminal of the third flip-flop; andan output generator coupled to the controller and providing the output clock signal, the output generator driving a rising edge on the output clock signal in response to active edges of the rising-edge control signal and driving a falling edge on the output clock signal in response to active edges of the falling-edge control signal.