Patent ID: 7302623
Filing Date: 2007-11-27
Classification: G01R,G11C

Abstract:
1. An algorithm pattern generator for testing a memory device, comprising: an instruction memory for receiving from an external console PC and storing a test program including an instruction for performing a test; a sequence control unit for sequentially fetching the instruction included in the test program from the instruction memory when performing the test; an interface unit for interfacing to an external device; a phase lock loop (PLL) for providing a clock signal having an identical phase; a command generating unit for generating a command necessary for the test with respect to each of cycles provided by the PLL; an address generating unit for generating a logical address with respect to each of the cycles and converting the logical address to a physical address necessary for the test via an address scrambling; data generating unit for generating a logical data based on the logical address with respect to each of the cycles and converting the logical data to a physical data necessary for the test via a data scrambling; and a data comparing unit for comparing a data generated in the data generating unit and a test data for each of the cycles and storing an information on a failed memory.