Patent ID: 7491610
Filing Date: 2009-02-17
Classification: H01L

Abstract:
1. A process for fabricating an integrated circuit structure comprising: forming a first device region selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate; forming a multilayer stack comprising at least three layers of material over the first device region in the semiconductor substrate, wherein the second layer is interposed between the first and the third layers, and wherein the first layer is adjacent the first device region; forming a window in the at least three layers of material, wherein the window terminates at the first device region formed; forming a doped semiconductor plug in the window, wherein the semiconductor plug has a first end and a second end, and wherein the first end is in contact with the first device region; forming a second device region selected from the group consisting of a source region and a drain region in the second end of the semiconductor plug, wherein one of the first and second device regions is a source region and the other is a drain region; removing the second layer, thereby exposing a portion of the semiconductor plug; forming gate dielectric material on the exposed portion of the semiconductor plug; forming a conductive layer comprising a horizontal capacitor segment and a vertical gate segment, wherein the vertical gate segment contacts the gate dielectric material to form a gate of a MOSFET device, and the horizontal capacitor segment forms a first capacitor plate; forming a capacitor dielectric layer over the first capacitor plate; and forming a second capacitor plate over the capacitor dielectric layer.