Patent ID: 6547356
Filing Date: 2003-04-15
Classification: B41J

Abstract:
A print data loading circuit for receiving at least N bits of serial data on a serial input data line, at least some of the bits of serial data describing an image to be formed on a print medium by a printing device, the loading circuit for providing the print data to a data bus in an addressing circuit, where the addressing circuit addresses one or more image-forming elements in the printing device, the circuit comprising:an N-bit serial shift register including: a first single-bit storage register having: a first-register data input coupled to the serial input data line; a first-register data output; and a first-register clock input coupled to a clock line; an Nth single-bit storage register having: an Nth-register data input; an Nth-register data output; and an Nth-register clock input coupled to the clock line; and Nâˆ’2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers, each having a data input and a data output; a first buffer circuit having an input and an output, the input of the first buffer circuit connected to the Nth register data output; Nâˆ’1 number of data latches having: data-latch inputs coupled to the data outputs of the first single-bit storage register and the Nâˆ’2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers; data-latch outputs coupled to Nâˆ’1 number of selection lines that are coupled to the data bus; and data-latch clock inputs coupled to the output of the first buffer circuit, a clear input line; a logic circuit having a first input connected to the clear input line, a second input connected to the output of the first buffer circuit, and a logic circuit output; the Nâˆ’1 number of data latches each including a data-latch clear input coupled to the clear input line; and the single-bit storage registers of the N-bit serial shift register each including a storage register clear input coupled to the logic circuit output, where a bit provided from the Nth-register data output, through the first buffer circuit, and to the data-latch clock inputs causes at least some of the other data bits in the first and the Nâˆ’2 number of single-bit storage registers to be transferred from their data outputs to the data-latch inputs of corresponding ones of the Nâˆ’1 number of data latches, the first buffer circuit providing a time delay between the Nth-register data output and the data-latch clock inputs.