Patent ID: 7404126
Filing Date: 2008-07-22
Classification: G01R

Abstract:
1. A method of testing an electronic circuit comprising a plurality of scan chains, wherein each of said plurality of scan chains contains a corresponding plurality of memory elements, said method comprising: scanning-in a corresponding one of a plurality of scan in vectors to a respective one of a plurality of scan chains; placing said integrated circuit in an evaluation mode to cause each of said plurality of scan chains to store a corresponding one of a plurality of scan out vectors; forming a plurality of output vectors in a corresponding plurality of scan out cycles in which said scan out vectors are scanned out from said plurality of scan chains, wherein each bit of said plurality of output vectors is formed from either a bit from a corresponding one of said plurality of scan out vectors or a masked value in case said bit from said corresponding one of said plurality of scan out vectors corresponds to an indeterminate state; and processing said plurality of output vectors through a signature generator circuit which generates a signature corresponding to said plurality of output vectors, whereby indeterminate values are avoided in said processing.