Patent ID: 6114194
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method for fabricating a field device transistor, comprising:forming a pad oxide layer on a substrate;forming a silicon nitride layer on the pad oxide layer;patterning the silicon nitride layer and the pad oxide layer to form an opening exposing the substrate;performing a field oxidation process to form a field oxide layer on the substrate within the opening;forming a mask layer on the silicon nitride layer, wherein the mask layer exposes the field oxide layer;performing an etching process to remove the field oxide layer from the substrate;removing the mask layer;performing a thermal oxidation process to form an oxide layer on the substrate within the opening;removing the silicon nitride layer and the pad oxide layer;forming a thin gate oxide layer and a gate conducting layer on the substrate and patterning the thin gate oxide layer and the gate conducting layer over the oxide layer, wherein the thin gate oxide layer and the gate conducting layer compose a gate;performing an implantation process to form a source region and a drain region on the substrate, wherein the source region and the drain region are located on two opposite sides of the gate conducting layer;forming a patterned insulator over the substrate, wherein the insulator comprises a first contact window exposing the source region, and a second contact window exposing the drain region and the gate conducting layer;forming a conducting layer on the first insulator, wherein the conducting layer fills the first contact window and the second contact window; andpatterning the conducting layer to form a first conducting wire and a second conducting wire, wherein the first conducting wire is electrically connected to the source region, and the second conducting wire is electrically connected to the drain region and the gate conducting layer.