Patent ID: 6933563
Filing Date: 2005-08-23
Classification: H01L

Abstract:
1. A metal oxide semiconductor (MOS) integrated device comprising: a substrate of a first conductivity type, said substrate including a plurality of active zones and inactive zones, said active zones including elementary MOS cells alternating with a plurality of separation zones, each one of said elementary MOS cells including at least one source region, at least one drain region and at least one gate structure, said at least one gate structure including at least one first conductor material finger; first metal stripes for contacting said source regions of the active zones; second metal stripes for contacting the drain regions; and third metal stripes placed on the inactive zones and for contacting said at least one conductor material finger of each elementary cell by forming a contact point formed by a first prolongation of said at least one finger for connecting with one of said third stripes, said first metal stripes, said second metal stripes and said third metal stripes being placed on the substrate substantially at the same level, wherein at least one of said third metal stripes includes at least one fourth metal stripe placed on one of said separation zones, at least one conductor material finger of each elementary cell having at least one second prolongation and said at least one fourth metal stripe having at least one first prolongation for being placed on said at least one second prolongation of said at least one material conductor finger to form at least another contact point.