Patent ID: 7224618
Filing Date: 2007-05-29
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array divided into sectors; a sector selecting circuit for, when one of the memory cell arrays is to be erased collectively, sequentially selecting a predetermined number of the sectors at a time from the memory cell array to be erased; and an erase voltage applying circuit for, when the collective erasing is carried out, applying a predetermined level of erasing voltage to the sectors selected by the sector selecting circuit, wherein the memory cell array has a plurality of a memory cells arranged in rows and columns, each memory cell comprises a gate electrode over a semiconductor layer with an intervening gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional element on both or one side of the gate electrode and having a function of retaining charge; and a current supplying capacity detecting circuit for measuring a current supplying capacity of the erase voltage applying circuit, wherein the sector selecting circuit is arranged so that a maximum number of the sectors selectable at a time is variable corresponding to the current supplying capacity measured by the current supplying capacity detecting circuit.