Patent ID: 6657953
Filing Date: 2003-12-02
Classification: H04L

Abstract:
A signal loopback device comprising:a multiplexing/demultiplexing unit to carry out multiplexing/demultiplexing between a DS3 signal serving as a digital signal conforming to a DS3 C-bit parity system and a DS1 signal serving as a digital signal having a lower speed than that of the DS3 signal; a DS1 signal loopback storage unit mounted on the side of DS1 signal input-output of the multiplexing/demultiplexing unit to temporarily contain the DS1 signal, and read the stored DS1 signal, thereby returning the DS1 signal; a DS3 signal loopback storage unit mounted on the side of DS3 signal input-output of the multiplexing/demultiplexing unit to temporarily contain the DS3 signal, and read the stored DS3 signal, thereby returning the DS3 signal in an original input signal format; a selecting unit to select any one of DS3 signal output from the multiplexing/demultiplexing unit and a DS3 loopback signal from the DS3 signal loopback storage unit; a protected detecting unit to output, when detecting loopback execution/cancellation information from a C-bit in the DS3 signal plurality of times, a result of detection showing that loopback is to be executed or canceled; and a loopback control unit to make a control for loopback execution or loopback cancellation to the DS1 signal loopback storage unit, the DS3 signal loopback storage unit, and the selecting unit depending upon the result of detection in the protected detecting unit.