Patent ID: 6720653
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A metal layer in a semiconductor device, the semiconductor device having a transistor and a capacitor electrode formed on a region of a semiconductor substrate, the metal layer comprising:a planar protection film on an entire surface of the semiconductor substrate inclusive of the transistor and the capacitor electrode; an absorber layer over the planar protection film inclusive of a region over the transistor; an insulating film on an entire surface, with a width of projection in a relievo form in a region over the absorber layer; a via hole through the planar protection film and the insulating film, to expose a region of the capacitor electrode; a tungsten plug and a planar stuffed layer in the via hole; a mirror metal layer on the insulating film on both sides of the projection of the insulating film, inclusive of the planar stuffed layer; and, an insulating film spacer on the projection of the insulating film and the mirror metal in the vicinity of the projection, wherein the plug and the planar stuffed layer comprise different materials.