Patent ID: 8637375
Filing Date: 2014-01-28
Classification: B82Y,H01L

Abstract:
1. A method of manufacturing a tunnel field effect transistor, comprising: forming a two-step profile in a silicon substrate using a patterned hard mask covering a higher steps of said profile; forming a gate stack against a side wall of the higher step; forming spacers on two sides of the gate stack; and implanting a first type impurity in the higher step and an opposite type impurity in a neighboring lower step, such that at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask wherein forming said gate stack comprises: depositing a gate dielectric layer over the substrate and the patterned hard mask, depositing a further layer for forming a conductive gate over the gate dielectric layer; and etching the gate dielectric layer and the further layer to form the gate stack against the side walls of the higher step and the hard mask; wherein the opposite type impurity is implanted into the lower step after said gate stack formation; and