Patent ID: 6470463
Filing Date: 2002-10-22
Classification: G06F

Abstract:
A hardware testing module for testing integrity of a hardware, comprising:a hardware to be tested; a communication buffer for receiving and providing a status of said hardware and data transferred by said hardware; a main application program for detecting and reading said data written in said communication buffer and processing the same to obtain a test result; and an interruption service program, controlled by said main application program, for writing said data transferred by said hardware into a buffer zone of said communication buffer; wherein said main application program first stops said interruption service program when reading said communication buffer, and continues said interruption service program after finishing reading; and further wherein said main application program is structured such that said interruption service program is still writing said data into said communication buffer when said main application program is processing said data, and said data transferred by said hardware and said test result obtained from said main application program are compared to determine the integrity of said hardware.