Patent ID: 6404767
Filing Date: 2002-06-11
Classification: H04L

Abstract:
An ABR (available bit rate) processing method for implementation by an APS (ABR processing subsystem) forming part of an ATM (asynchronous transfer mode) switch which assigns an ingress cell an internal connection number and a buffer address in cell memory, the method comprising the steps of:receiving a plurality of cell ingress input messages each containing a respective internal connection number, a buffer address, and an ingress cell; for each cell ingress input message received, outputting a cell ingress output message containing the internal connection number, the buffer address and the ingress cell, and then conditionally performing ingress cell measurements; receiving a plurality of cell egress input messages each containing a respective internal connection number and buffer address; for each cell ingress message received, outputting a cell egress output message containing the internal connection number and buffer address, and then conditionally performing egress cell measurements; for each ingress cell received in an ingress cell input message, if the ingress cell contained in one of said ingress input messages is a BRM (backward resource management) cell having ER (explicit rate), CI (congestion indication) and NI (no increase) fields, an internal connection number and a buffer address for the BRM cell, then calculating new ER,CI,NI values, and updating these in the BRM cell and outputting a cell ingress output message containing the updated BRM cell, ICN (internal connection number) and buffer address for storage in cell memory and subsequent queueing.