Patent ID: 6775754
Filing Date: 2004-08-10
Classification: G06F

Abstract:
A memory apparatus, composed of comprising:a reversibly non-writable memory, including: a designated data area operable to store state data, the state data being an initial data value when said memory is in a predetermined state, a hidden data area operable to store hidden data, and a setup data area operable to store a memory-used value, the memory-used value being a setup state value when said memory is in the predetermined state; and a control circuit, including: an initial state detector operable to permit access to said designated data area and said hidden data area when the stored state data is the initial data value, and a used state detector operable, stored state data is different than the initial data value, to permit access to said designated data area and said hidden data area when the memory-used value is the setup state value, and to deny access to said designated data area and said hidden data area when the memory-used value is different than the setup state value.