Patent ID: 7397724
Filing Date: 2008-07-08
Classification: G11C

Abstract:
1. A word line decoder for generating a block word line driving signal in a flash memory device, comprising: a first inverter receiving a block selection signal; a second inverter receiving an output of the first inverter; first and second serially connected transistors having gates connected to a supply voltage, receiving an output of the second inverter and outputting the block word line driving signal; a third transistor having a source connected to a high voltage terminal and a gate connected to a line transmitting the block word line driving signal; a fourth transistor connected between a drain of the third transistor and the block word line driving signal line; a fifth transistor connected between a drain of the third transistor and a gate of the fourth transistor and having a gate connected to the block word line driving signal line; and a sixth transistor connected between the output of the first inverter and the gate of the second transistor and having a gate connected to the supply voltage terminal.