Patent ID: 6359807
Filing Date: 2002-03-19
Classification: G11C,H01L

Abstract:
A method of reading a flash memory cell, wherein the flash memory cell comprises:a word gate on the surface of a semiconductor substrate; floating gates on the sidewalls of said word gates separated from said word gates by an insulating layer; a control gate adjacent to each of said floating gates and separated from each said floating gate by an insulating layer; and bit line diffusions within said semiconductor substrate and under each of said control gates; wherein one of said floating gates is a selected floating gate, and the other of said floating gates is an unselected floating gate, and wherein said bit line diffusion near said selected floating gate is a bit diffusion, and said bit line diffusion near said unselected floating gate is a source diffusion, wherein said method of reading the cell comprises the steps of: over-riding said unselected floating gate; providing a voltage on said word gate having a sum of the word gate threshold voltage, an overdrive voltage, and the voltage on said source diffusion; providing a voltage on said control gate adjacent to said selected floating gate sufficient to allow for reading of the selected floating gate; and reading said cell by measuring the voltage level on said bit diffusion.