Patent ID: 7556954
Filing Date: 2009-07-07
Classification: H01L

Abstract:
1. A method of manufacturing a MOS transistor, the method comprising the steps of: forming a gate oxide layer, a gate electrode, and a spacer on a silicon substrate; forming a silicon carbide layer on an entire surface of the silicon substrate and the gate electrode; removing the silicon carbide layer except for predetermined portions corresponding to source-drain regions of the substrate and the gate electrode; implanting dopants into the source-drain regions, thereby forming source-drain diffusion regions; forming a metal layer comprising nickel on the entire surface of the silicon substrate, the silicon carbide layer, and the spacer; performing a heat-treatment process, thereby forming a multiple layer structure on the gate electrode and the source-drain diffusion regions, the multiple layer structure including the silicon carbide layer, a graphite layer and a nickel salicide layer; and removing the remaining metal layer.