Patent ID: 7739474
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A method for unifying access to a physical memory, the method comprising: detecting a first read or write operation directed to the physical memory, wherein the first operation provides a virtual address and is generated by a central processing unit (CPU) or an input/output (I/O) device; translating the virtual address to a physical address, wherein the CPU and the I/O device share a same virtual address space such that the virtual address is translated using a same set of page tables regardless of whether the first operation is generated by the CPU or the I/O device; accessing the physical memory according to the physical address, wherein address translation and memory protection are performed atomically for both the CPU and the I/O device such that registering or pinning of memory pages accessed by the CPU or the I/O device is not required to prevent data corruption or performance delays; determining whether the first operation violates any access rights, wherein translation of the virtual address to the physical address is not performed due to determining that a translation of the virtual address is not available or that the first operation violates an access right; triggering a first interrupt at the CPU, in response to failing to translate the virtual address to the physical address, wherein a first interrupt handling routine is invoked at the CPU, and wherein the first interrupt handling routine manages the first interrupt for failing to translate the virtual address to the physical address, wherein the first operation is generated by the I/O device; and triggering a second interrupt at the I/O device, in response to failing to translate the virtual address to the physical address, wherein a second interrupt handling routine is invoked at the I/O device, and wherein the second interrupt handling routine saves the virtual address and a reason for failing to translate the virtual address to the physical address in one or more registers of the I/O device from memory controller registers.