Patent ID: 6284593
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A process of forming a memory cell array comprising the steps of:(a) forming at least one deep trench capacitor in a Si-containing substrate, said at least one deep trench capacitor including at least a deep trench polysilicon material, a trench oxide formed on said deep trench polysilicon material, a liner formed on said trench oxide and interior walls of a collar oxide region, and a polysilicon placeholder material formed on said liner;(b) patterning said polysilicon placeholder material using at least a hardmask to cover a middle portion of said deep trench capacitor and selectively etching exposed portions of said polysilicon placeholder material stopping on said liner;(c) removing exposed portions of said liner stopping on said trench oxide so as to expose portions of said trench oxide and removing said exposed portions of said trench oxide stopping on said deep trench polysilicon material;(d) oxidizing any exposed sidewalls and providing a planarized layer of oxide in said etched areas so as to form shallow isolation trench regions which have a depth that is substantially above a buried-strap outdiffusion region to be subsequently formed thereby not cutting into said buried-strap outdiffusion region, yet being deep enough to isolate adjacent bitline diffusion regions to be subsequently formed;(e) removing said hard mask from said middle portion of the deep trench capacitor, and selectively etching through said remaining polysilicon placeholder material, liner and trench oxide so as to expose a portion of said deep trench polysilicon material;(f) providing a strap opening in said deep trench capacitor and forming a one-sided buried-strap outdiffusion region through said strap opening, said one-sided buried strap outdiffusion region being confined to a substantially center portion of the deep trench capacitor;(g) forming bitline diffusion regions about said deep trench capacitor; and(h) forming a new trench oxide on said exposed portion of said deep trench polysilicon and forming a gate conductor on said trench oxide.