Patent ID: 7479439
Filing Date: 2009-01-20
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor structure comprising: forming a doped single crystalline semiconductor region in a semiconductor substrate; forming a patterned stack of a salicide mask dielectric layer and a thin silicon containing layer on said semiconductor substrate; metallizing said thin silicon containing layer to form a suicide alloy layer directly on said salicide mask dielectric layer; forming a semiconductor silicide directly on said doped single crystalline semiconductor region; forming a gate dielectric directly on said doped single crystalline semiconductor region; forming a first doped polycrystalline silicon containing layer directly on said gate dielectric prior to forming said salicide mask dielectric layer; forming a first polysilicon silicide directly on said first doped polycrystalline silicon containing layer; forming an isolation dielectric layer on said first doped polycrystalline silicon containing layer; forming a second doped polycrystalline silicon containing layer directly on said isolation dielectric layer prior to forming said salicide mask dielectric layer; and forming a second polysilicon suicide directly on said second doped polycrystalline silicon containing layer.