Patent ID: 6134140
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a NAND cell unit comprising a plurality of memory cells connected in series;an erase circuit for applying an erase voltage to all memory cells of said NAND cell unit, thereby to erase data from all memory cells of said NAND cell unit;a soft-programming circuit for applying a soft-program voltage to all memory cells of said NAND cell unit, said soft-program voltage being of a polarity opposite to the polarity of the erase voltage; anda programming circuit for applying a program voltage to any selected one of the memory cells, applying a first voltage to at least one of two memory cells adjacent to said any selected one of the memory cells, and applying a second voltage to the remaining memory cells of said NAND cell unit, thereby to program data into said any selected one of the memory cells.