Patent ID: 7396727
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A method for fabricating a transistor comprising: forming a first source or drain region by a first ion implantation process on a semiconductor substrate; depositing a first sacrificial layer over the semiconductor substrate, and dry etching a portion of the sacrificial layer to form a hole which exposes the first source or drain region; depositing and flattening a first conducting layer over the first sacrificial layer to form a channel region filling the hole; removing the first sacrificial layer; forming a second sacrificial layer over the first source and drain region and the channel region; performing a second ion implanting process on the channel region; removing the second sacrificial layer; forming a gate insulation layer over the channel region forming a gate conducting layer; dry etching the gate conducting layer to form a gate conductor extending over an upper portion and one side of the channel region; implanting ions to form a second source and drain region over the channel region; forming an intercalary insulation layer over the semiconductor substrate; etching the intercalary insulation layer to form contact holes exposing a portion of the first and second source and drain regions and the gate conductor; and depositing and patterning a second conducting layer over the intercalary insulation layer to fill the contact holes.