Patent ID: 6268746
Filing Date: 2001-07-31
Classification: G06F,G11C,H03K

Abstract:
An integrated circuit (IC) with synchronized logic, comprising:a global clock signal with a global phase and an approximately 50% duty cycle;a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate, said first local clock signal is generated from said global clock signal;one or more intermediate local clock signals with one or more intermediate phases, each said intermediate local clock signal with an approximately 50% duty cycle that couple to one or more intermediate dynamic logic gates, said intermediate local clock signals are generated from said global clock signal;an end local clock signal with an end phase and an approximately 50% duty cycle that couples to an end dynamic logic gate, said end local clock signal is generated from said global clock signal;the phase of an individual local clock signal overlaps an earlier phase local clock signal by an amount approximately equal to the overlap of the phase of the next individual local clock signal; andsaid first dynamic logic gate, intermediate dynamic logic gate(s), and last dynamic logic gates couple such that an individual dynamic logic gate with said individual local clock signal and phase may only provide a signal to the next individual dynamic logic gate that uses a next phase local clock signal wherein the gates may couple together in series, in a feed back loop, or a feed forward loop, and said first, intermediate, or end dynamic logic gates couple to each other or to other dynamic logic gates without additional buffers, registers, latches, or static circuits.