Patent ID: 7952933
Filing Date: 2011-05-31
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having memory cells or memory cell units including at least one memory cell, the memory cells or the memory cell units being arranged in an array form; a bitline connected to at least one of the memory cells or the memory cell units; a read circuit; a first transistor; and a second transistor, wherein a source of the first transistor is connected to the bitline, a drain of the first transistor is connected to the read circuit, the drain of the first transistor is connected to one of a source of the second transistor and a drain of the second transistor, a first voltage is applied to a gate of the first transistor during a first period, a second voltage is applied to the drain of the first transistor via the second transistor during the first period, the bitline is charged to a third voltage via the first transistor during the first period, the second voltage is higher than the third voltage, and wherein a fourth voltage is applied to the gate of the first transistor during a second period after the first period, the first transistor is non-conductive independently of a data stored in a corresponding selected memory cell during the second period, and wherein a fifth voltage is applied to the gate of the first transistor during a third period after the second period, the second transistor is non-conductive during the third period, the first transistor is non-conductive during the third period when the corresponding selected memory cell stores a first data, the first transistor is conductive during the third period when the corresponding selected memory cell stores a second data which is different from the first data, the read circuit senses a change in a voltage of the bitline during the third period or after the third period, and the first voltage, the fourth voltage and the fifth voltage are different from one another.