Patent ID: 6453381
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A data read circuit to allow data coherence for a double data rate DRAM, comprising:a) stored data read in a burst of data using both edges of a clock to read said data twice each clock cycle, b) CAS (column address strobe) latency determined by BIOS (basic input output subsystem) at power up, c) said stored data read on a RAS (row address strobe) cycle into even and odd bit line sense amplifiers, d) data read from said bit line sense amplifiers organized into positive clock edge data and negative clock edge data, e) said CAS latency and a starting address of stored data in said burst of data determines which edge of said clock is used to read first data of said stored data, f) said stored data clocked to an output of a multiplexer with a positive clock edge when said starting address is even and said CAS latency is an integer, g) said stored data clocked to the output of the multiplexer with a negative clock edge when said starting address is odd and said CAS latency is a non-integer, h) said stored data clocked to the output of the multiplexer with the negative clock edge when said starting address is even and said CAS latency is said non-integer, i) said stored data clocked to the output of the multiplexer with the positive clock edge when said starting address is odd and said CAS latency is said integer.