Patent ID: 7209534
Filing Date: 2007-04-24
Classification: H03K

Abstract:
1. A fractional divider system for a low-power timer with reduced timing error at wake-up from a low power mode, comprising: a fractional divider circuit configured to produce an output signal with a frequency F wherein P DIV is a period of the fractional divider circuit, M is an integer part of a division ratio associated therewith, and N is the magnitude of a fractional part of the division ratio; a high speed crystal oscillator circuit connected to the fractional divider circuit and configured to start and generate a high speed clock signal based on a wake-up from the low power mode; a high speed clock divider circuit connected to the fractional divider circuit and to the high speed crystal oscillator circuit, wherein the high speed crystal oscillator circuit is further configured to sample the output signal and a current state of a total timing error associated with the fractional divider circuit using the high speed clock signal, and wherein the sampled output signal triggers the high speed clock divider circuit, and the sampled current state of the total timing error preloads the high speed clock divider circuit, and wherein the high speed clock divider circuit is further configured to synchronize a first pulse of the output clock signal to an ideal clock timing associated with an external reference clock to an accuracy within 1.5 periods of the high speed clock signal using the preloaded total timing signal.