Patent ID: 6369420
Filing Date: 2002-04-09
Classification: H01L

Abstract:
An array of electrically erasable programmable memory cells comprising: a semiconductor substrate;a plurality of electrically erasable programmable memory cells arranged in a plurality of rows and columns in said substrate; each of said memory cells comprising: a first region in said substrate; a second region in said substrate, spaced apart from said first region in the column direction, with a channel therebetween; a first layer of insulating material over said channel; a floating gate on said first layer of insulating material and over a first portion of said channel and overlapping a portion of said second region; a second layer of insulating material continuous in the row direction and extending over said floating gate of one memory cell and over said floating gate of an adjacent memory cell in the same row; and an electrically conductive spacer on said first layer of insulating material, immediately laterally adjacent to and contiguous with said second layer of insulating material and being continuous in said row and having substantially the same shape in said row, said spacer being a control gate, over a second portion of said channel and spaced apart from said floating gate of each memory cell in said row and overlapping a portion of said first region and electrically connecting said control gates of adjacent memory cells in the same row.