Patent ID: 7546491
Filing Date: 2009-06-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first line for receiving a power voltage; a plurality of repair units, each of the plurality of repair units comprising an array of memory cells arranged in rows and columns; a selection circuit for outpitting selection signals for selecting for testing the rows in one of the repair units in response to a row address; second power lines, each of the second power lines common-connected to the memory cells of a corresponding repair unit; and a switch circuit for connecting one of the second power lines to the first power line in response to the selection signals, in a test operation mode such that power is turned off from the rows of memory cells not selected for testing and in a normal operation mode, power is restored to the memory cells not selected for testing, wherein the switch circuit comprises switches, each of the switches connected to a corresponding second power line, wherein each of the switches comprises: a NOR gate for receiving the control signal and a corresponding selection signal, and a PMOS transistor for connecting the first power line with a corresponding second power line in response to an output signal of the NOR gate.