Patent ID: 8671244
Filing Date: 2014-03-11
Classification: G06F,G11C,Y02D

Abstract:
1. An apparatus comprising: a plurality of first memory circuits, each first memory circuit of the plurality of first memory circuits being associated with a first memory standard, where the first memory standard defines a behavior and timing of a first set of control signals that each first memory circuit is operable to accept; and an interface circuit coupled to the plurality of first memory circuits, the interface circuit being operable to emulate a second set of control signals that at least one second memory circuit associated with a second different memory standard is operable to accept, such that the plurality of first memory circuits appear to a host system as the at least one second memory circuit, wherein a behavior and timing of the second set of control signals are defined by the second different memory standard, the first memory standard further defines a first version of a protocol, and the second different memory standard further defines a second different version of the protocol, and both of the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.