Patent ID: 6904480
Filing Date: 2005-06-07
Classification: G06F

Abstract:
1. A system comprising: a connector to a bus; an instruction memory to store a bus stimuli instruction, the instruction having a predefined length, the instruction containing a plurality of segments, the plurality of segments including at least a flow segment and a data segment; a logic device coupled with the instruction memory to receive the bus stimuli instruction and generate digital logic based on the bus stimuli instruction, the logic device comprising a flow portion, a request portion, and a data portion, the flow portion to receive at least the flow segment from the instruction memory, and the data portion to receive at least the data segment from the instruction memory, the flow portion, the request portion, and the data portion each comprising a device selected from the group consisting of a field programmable gate array and an application specific integrated circuit; a plurality of phase engines coupled between the logic device and the connector to translate the digital logic into signals and provide the signals to the bus, the plurality of phase engines including a system phase engine, an arbitration phase engine, a request phase engine, a snoop/error phase engine, and a data phase engine, the system phase engine, the arbitration phase engine, and the request phase engine coupled with the flow portion, the snoop/error phase engine coupled with the request portion, the data phase engine coupled with the data portion; further comprising a response memory coupled with the flow portion and the request portion to store response information; and further comprising a data memory coupled with the data portion to store data.