Patent ID: 6344998
Filing Date: 2002-02-05
Classification: G11C

Abstract:
For an electrically alterable non-volatile multi-level semiconductor memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a bit line and a reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, a method of operating the electrically alterable non-volatile multi-level semiconductor memory device, comprising:setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, when one of the first third states is selected, verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, the operation of setting the parameter being conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the parameter of the one non-volatile multi-level memory cell, with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter of the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter, and wherein the plurality of non-volatile multi-level memory cells of the matrix of the rows and the columns are disposed in substantially a rectangle that has a first side, a second side, a third side and a fourth side, the first side and the second side intersect with each other substantially perpendicularly, a plurality of word lines coupled with gate electrodes of floating gate FET's of the multi-level memory cells and the first side of the rectangle intersect with each other substantially perpendicularly, a plurality of bit lines coupled with drains of floating gate FET's of the multi-level memory cells and the second side of the rectangle intersect with each other substantially perpendicularly, a row select circuit is disposed at the first side of the rectangle for coupling with the plurality of word lines, and peripheral circuitry, including a column select circuit, sense circuits, a data conversion circuit and latches, is disposed at the second side of the rectangle.