Patent ID: 8909833
Filing Date: 2014-12-09
Classification: G06F,H04L

Abstract:
1. A data communication system, comprising: a plurality of hardware compiled device modules, wherein each hardware compiled device module in said plurality of hardware compiled device modules has a two clock delay; a uni-directional serial data and address bus structure adapted to operably receive said plurality of hardware compiled device modules and to serially clock a plurality of dynamic words of a dynamic stream of data from a ring controller through said plurality of hardware compiled device modules without returning said plurality of dynamic words to said ring controller until said plurality of dynamic words has been clocked through all of said plurality of hardware compiled device modules; wherein said plurality of dynamic words includes at least one operation instruction word and at least one address indicator word indicating at least one binary address on which said at least one operation instruction word instructs action to be taken; wherein at initialization, said plurality of hardware compiled device modules are configured and assigned an associated address value, said ring controller having no a priori knowledge of said associated address value; wherein each of said plurality of hardware compiled device modules is adapted to: analyze said at least one binary address clocked through the hardware compiled device module and determine whether said at least one binary address as clocked through the hardware compiled device module is within one of a plurality of binary addresses associated with the hardware compiled device module; append a stored word from the hardware compiled device module to said dynamic stream of data as output by the hardware compiled device module using the hardware compiled device module when the hardware compiled device module determines that said at least one binary address is within said plurality of binary addresses associated with the hardware compiled device module and has a corresponding of said at least one operation instruction that is a read instruction in response to determining that said at least one binary address is within said plurality of binary addresses associated with the hardware compiled device module and has said corresponding of said at least one operation instruction that is said read instruction; write a streamed word from said plurality of dynamic words clocked through the hardware compiled device module to the hardware compiled device module when the hardware compiled device module determines that said at least one binary address is within said plurality of binary addresses associated with said hardware compiled device module and said at least one binary address has a corresponding of said at least one operation instruction that is a write instruction in response to determining that said at least one binary address is within said plurality of binary addresses associated with said hardware compiled device module and has said corresponding of said at least one operation instruction that is said write instruction; and output an output data stream, wherein, when said reading step is performed, said output data stream output by the hardware compiled device module includes said stored word.