Patent ID: 6157990
Filing Date: 2000-12-05
Classification: G06F,G11C

Abstract:
A memory device comprising on a single chip:at least one external data port for providing data input and output,a main memory for storing data,a cache memory coupled between said data port and said main memory for providing data transfer between said data port and said main memory, and having smaller storage capacity than said main memory,a first chip select line for receiving a first chip select signal to prevent said main memory from executing external commands when said first chip select signal is in a first logic state and to enable said main memory to execute said external commands when said first chip select signal is in a second logic state,a second memory chip select line for receiving a second chip select signal independent of said first memory chip select signal to prevent said cache memory from executing said external commands when said second chip select signal is in a first logic state and to enable said cache memory to execute the external commands when said second chip select signal is in a second logic state, anda clock generator coupled to the first and second chip select lines for receiving the first and second chip select signals,wherein the clock generator is prevented from producing a main memory internal clock signal when the first chin select signal is in the first logic state, and is enabled to produce the main memory internal clock signal when the first chip select signal is in the second logic state, and the clock generator is prevented from producing a cache memory internal clock signal when the second chip select signal is in said first logic state, and is enabled to produce the cache memory internal clock signal when the second chip select signal is in the second logic state.