Patent ID: 7989850
Filing Date: 2011-08-02
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: a substrate including a switching region and a driving region; first and second gate electrodes positioned on the substrate and in the switching region and the driving region, respectively; a gate insulating layer on the first and second gate electrodes and including a first gate contact hole exposing a portion of the first gate electrode and a second gate contact hole exposing a portion of the second gate electrode; first and second active layers on the gate insulating layer and corresponding to the first and second gate electrodes, respectively; an interlayer insulating layer on the first and second active layers, the interlayer insulating layer including first to fourth active contact holes and the first and second gate contact holes, the first and second active contact holes respectively exposing both sides of the first active layer, the third and fourth active contact holes respectively exposing both sides of the second active layer; first and second ohmic contact layers respectively contacting both sides of the first active layer through the first and second active contact holes; third and fourth ohmic contact layers respectively contacting both sides of the second active layer through the third and fourth active contact holes; first source electrode and first drain electrode respectively on the first and second ohmic contact layers; second source electrode and second drain electrode respectively on the third and fourth ohmic contact layers; a data line on the interlayer insulating layer and connected to the first source electrode; a first passivation layer on the data line, the first and second source electrodes and the first and second drain electrodes and including the first and second gate contact holes, a first drain contact hole exposing a portion of the first drain electrode and a second drain contact hole exposing a portion of the second drain electrode; a gate line on the first passivation layer and connected to the first gate electrode through the first gate contact hole, the gate line crossing the data line; a power line on the first passivation layer and parallel to and spaced apart from the gate line; a connection electrode on the first passivation layer, one end of the connection electrode connected to the first drain electrode through the first drain contact hole, the other end of the connection electrode connected to the second gate electrode through the second gate contact hole; a second passivation layer on the gate line, the power line and the connection electrode and including the second drain contact hole; and a pixel electrode on the second passivation layer and connected to the second drain electrode through the second drain contact hole.