Patent ID: 7746128
Filing Date: 2010-06-29
Classification: H03K,H03L

Abstract:
1. A clock multiplier comprising: a plurality of variable delay cells, each of the variable delay cells configured to generate a triangular wave voltage based on an input clock signal, and configured to generate a square wave voltage based on the triangular wave voltage; and a duty ratio control circuit configured to modify the duty ratio of the input clock signal based on control signals output by a phase-frequency detector, wherein the duty ratio control circuit includes a capacitor, and the duty ratio control circuit is configured to generate an internal logic signal by charging the capacitor through a third variable resistance device based on the control signals output by the phase-frequency detector while the input clock signal corresponds to a first logic level and by discharging the capacitor through a fourth variable resistance device based on the control signals output by the phase-frequency detector while the input clock signal corresponds to a second logic level, and configured to perform a logical OR operation upon the internal logic signal and the input clock signal.