Patent ID: 7897447
Filing Date: 2011-03-01
Classification: H01L

Abstract:
1. A method for forming a semiconductor device, comprising: providing a direct silicon bond (DSB) wafer comprising a cleaved silicon wafer layer having one of a <100> or <110> crystallographic orientation over a semiconductor wafer having the other of a <100> of <110> crystallographic orientation; forming a patterned photoresist layer over the cleaved wafer layer to cover a first portion of the cleaved wafer layer with the photoresist and to leave a second portion of the cleaved semiconductor wafer layer exposed; dosing the second portion of the cleaved wafer layer with silicon to convert the second portion of the cleaved wafer layer to amorphous silicon and to leave the first portion of the cleaved wafer layer to have the one of the <100> or <110> crystallographic orientation; in an epitaxial reaction chamber, exposing the amorphous silicon to an epitaxy process to convert the amorphous silicon to have the other of the <100> or <110> crystallographic orientation and to form a crystal defect at an interface border region of the first portion and the converted amorphous silicon; in situ in the epitaxial reaction chamber, annealing at a temperature of about 1200° C. or less to provide an initial reduction in residual crystal defect damage resulting during recrystallization at the interface border region; in situ in the epitaxial reaction chamber, exposing the interface border region to a hydrochloric acid etch process to remove a portion of an upper surface of the first and second portions, including at least a portion of any defect damage remaining at the interface border region after the initial reduction; following the hydrochloric acid etch process, forming a shallow trench isolation region at the interface border region, wherein a width of the shallow trench isolation is narrower than a width of the crystal defect; following the hydrochloric acid etch process, forming an NMOS transistor on the first portion or converted amorphous silicon second portion having the <100> crystallographic orientation; and following the hydrochloric acid etch process, forming a PMOS transistor on the first portion converted amorphous silicon second portion having the <110> crystallographic orientation.