Patent ID: 6201835
Filing Date: 2001-03-13
Classification: H03M

Abstract:
A method of reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation therein, comprising:(a) applying a pseudo-random sequence signal to a first input of a first adder;(b) applying an error feedback signal to a second input of the first adder and a first input of a second adder;(c) producing a quantization signal in response to the first adder and applying the quantization signal to an MSB of a second input of the second adder;(d) producing an error signal representing the difference between the quantization signal and the error feedback signal by means of the second adder;(e) delaying the error signal a predetermined amount to produce the error feedback signal, wherein energy of the quantization signal is spread over a broad frequency spectrum between DC and a chopping frequency; and(f) producing a pair of out-of-phase, non-overlapping chopping signals from the quantization signal and applying the chopping signals to corresponding chopper switches of the chopper stabilized amplifier.