Patent ID: 6780695
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A method of fabricating a BiCMOS integrated circuit comprising the steps of forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate, said substrate having a device area for forming at least one bipolar transistor and a device area for forming at least one complementary metal oxide semiconductor (CMOS) transistor;patterning said polysilicon layer to provide a sacrificial polysilicon layer over said device area for forming the at least one bipolar transistor, while simultaneously providing at least one gate conductor in said device area for forming at least one CMOS transistor; forming at least one pair of spacers about each of the at least one gate conductor to provide said at least one CMOS transistor; selectively removing a portion of said sacrificial polysilicon layer over said device area for forming the at least one bipolar transistor to provide at least one opening; and forming the at least one bipolar transistor having a raised extrinsic base in the at least one opening.