Patent ID: 6462578
Filing Date: 2002-10-08
Classification: H03K

Abstract:
A programmable logic circuit comprising:a first set, a second set, a third set and a fourth set of routing lines said first or second, third and fourth sets of routing lines having at least three different spans; a first set of switches selectively coupling the second set of routing lines to the third and the fourth sets of routing lines, a first switch of the first set of switches selectively coupling a first routing line of said second set of routing liens to a second routing line of the third set of routing lines to form a first signal path wherein said second routing line drives said first routing line through said first switch, a second switch of the first set of switches selectively coupling the first routing line to a third routing line of the fourth set of routing lines to form a second signal path wherein said third routing line drives said first routing line through said second switch; and a second set of switches selectively coupling the second set of routing lines to said first set of routing lines wherein a third switch of said second set of switches selectively coupling the first routing line to drive a fourth routing line of said first set of routing lines through said third switch.