Patent ID: 7633101
Filing Date: 2009-12-15
Classification: H01L

Abstract:
1. An integrated junction field-effect transistor (JFET) comprising: a substrate having at least a top layer of semiconductor and an active area in a well region doped with conduction enhancing impurities of a first conductivity type, said active area defined by insulating material formed in said substrate; a channel region of doped semiconductor within said active area; a dielectric layer formed on top of said substrate and having openings formed at least partially over said active area for source and drain contacts and an opening over said active area for a gate contact to be located between said source and drain contacts; a gate region formed in said active area within said channel region and under said gate contact opening so as to form a gate-channel junction; source and drain regions formed in said active area under said source and drain openings; and metal source, drain and gate contacts formed in said source, drain and gate openings, respectively, with the tops of said source, drain and gate contacts polished down to be approximately flush with the top of said dielectric layer; wherein said source, drain and gate openings are lined with a thin layer of sputtered amorphous silicon to act as a barrier layer between the metal of the source, drain and gate contacts and the underlying active area.