Patent ID: 6819583
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A ferroelectric thin film resistor memory array formed on a substrate comprising:plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein said drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column; wherein, said memory cells are programmed using a programming voltage; and wherein the ferroelectric resistor is non-destructively read by sensing taken from the group of sensing consisting of constant voltage sensing and constant current sensing.