Patent ID: 6549000
Filing Date: 2003-04-15
Classification: G01R

Abstract:
A semiconductor device testing apparatus comprising:a signal read circuit for reading therein a logical value of a response signal outputted from a semiconductor device under test; a strobe pulse supply path through which a strobe pulse is supplied to said signal read circuit, said strobe pulse giving to said signal read circuit a timing at which the signal read circuit reads therein the logical value; a variable delay element for adjusting signal propagation delay time of said strobe pulse supply path; a register for setting a delay time of said variable delay element; a non-volatile memory; delay correcting data setting means for causing delay correcting data to be stored in said non-volatile memory, said delay correcting data correcting the signal propagation delay time of said strobe pulse supply path to a prescribed value; and data transfer means for causing the delay correcting data stored in said non-volatile memory to be transferred to said register.