Patent ID: 9123656
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A process of forming an integrated circuit device, comprising: forming a hard mask layer over a substrate; forming a mandrel layer stack over the hard mask layer, wherein an uppermost layer of the mandrel layer stack is an organosilicate polymer; forming a first lithographic mask over mandrel layer stack; etching the mandrel layer stack through the first lithographic mask to form a mandrel; removing the first lithographic mask; depositing a spacer material over the mandrel; etching the spacer material to form spacers on sides of the mandrel; forming a second lithographic mask over mandrel and spacers; etching through the mandrel where the mandrel is exposed through the second lithographic mask to form a reduced mandrel; removing the second lithographic mask; etching the hard mask layer through a mask that is provided by the spacers and the reduced mandrel, wherein etching the hard mask layer forms the hard mask layer into a hard mask; and treating the substrate using the hard mask.