Patent ID: 7555625
Filing Date: 2009-06-30
Classification: G06F

Abstract:
1. A data transfer method for a multi-memory chip, the multi-memory chip having a first memory device and a second memory device that can independently operate in synchronization with clock signals from an external system and that can transmit and receive data to and from the external system while sharing a data transmission bus, the method comprising: controlling, at an external system, the multi-memory chip to operate in an internal transfer mode, permitting an exchange of data directly between the first and second memory devices, the internal transfer mode driving the second memory device to operate in a writable state while driving the first memory device to operate in a readable state; providing an enabled waiting indication signal from the first memory device to the second memory device in the internal transfer mode, the waiting indication signal being generated by the first memory device and providing notice of the reading of data from the first memory device; and receiving the data provided through the data transmission bus from the first memory device at the second memory device after the second memory device has received the activated waiting indication signal; wherein the data are provided to the second memory device from the first memory device through the data transmission bus directly without passing through the external system.