Patent ID: 9111605
Filing Date: 2015-08-18
Classification: G11C

Abstract:
1. A semiconductor storage apparatus comprising: a first memory region; and wherein the first memory region includes: a first and a second memory plane containing a plurality of memory cells arranged in a matrix; a first and a second block of pairs of sense-latch and write driver to read and to write the information in the first and the second memory planes; and a first memory region control circuit to respectively generate: a first write enable signal output to the first block of pairs of sense-latch and write driver, a second write enable signal output to the second block of sense-latch and write driver, and a first readout enable signal output to the first block of pairs of sense-latch and write driver, and a second readout enable signal output to the second block of pairs of sense-latch and write driver, according to the input internal address and the read/write control signals; wherein the first block of pairs of sense-latch and write driver performs the first rewrite operation on the first memory plane by activating the first write enable signal, and performs the first verify read on the first memory plane by activating the first readout enable signal; wherein the second block of pairs of sense-latch and write driver performs the second rewrite operation on the second memory plane by activating the second write enable signal, and performs the second verify read on the second memory plane by activating the second readout enable signal; wherein the first verify read operation is started in a first time-division slot which is a subsequent slot of a second time-division slot in which the first rewrite operation is completed; wherein the second verify read operation is started in a third time-division slot which is a subsequent slot of a fourth time-division slot in which the second rewrite operation is completed; and wherein slot intervals between the first time-division slot and the second time-division slot and slot intervals between the third time-division slot and the fourth time-division slot are the same.