Patent ID: 6567950
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A method of replacing one of a plurality of operating DRAM chips in a memory circuit or a given I/O failure of DRAM chips with a spare DRAM chip on a memory module, in which a plurality of operating DRAM chips constitutes a multiple byte word, and which memory module includes error correction code (ECC) for detecting and correcting all single bit errors and detecting and correcting all multi bit errors in a single DRAM chip, and which ECC includes detecting and flagging in which chip any error occurs, said method comprising the steps of;providing at least one spare DRAM chip, said ECC setting a flag to identify a chip having a first preselected error profile, and entering a chip kill or I/O kill mode upon generation of said flag to deactivate the chip or an I/O on said chip that caused said flag, activating said spare chip or the I/O on said spare chip corresponding to the chip or I/O deactivated; and thereafter operating said ECC in the normal operating mode without interruption of operation on all of the chips except the deactivated chip or I/O deactivated and on the activated chip or activated I/O.