Patent ID: 6813212
Filing Date: 2004-11-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells which need refresh; an access circuit for making an access to a memory cell designated by an access address externally supplied; a refresh clock signal generating circuit for generating a refresh clock signal which provides a reference to a time interval of refresh operations; an address transition detecting circuit for detecting a transition of said access address and generating an access address transition detecting signal; and a control circuit for activating a refresh enable signal for enabling a refresh operation based on a generation of said access address transition detecting signal by triggering said refresh clock signal, and for executing a refresh to a memory cell corresponding to a refresh address by triggering the generation of said access address transition detecting signal, prior to executing an access to a memory cell designated by said access address, wherein said control circuit executes a refresh operation by triggering an input of a write instruction signal, independently from said refresh enable signal, before said control circuit executes a write operation to a memory cell designated by said access address.