Patent ID: 9048123
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first fin on a semiconductor base, the first fin having first and second source/drain areas and a first gate body area between the first and second source/drain areas, the first fin having a top side opposite the semiconductor base and a bottom side contacting the semiconductor base, the first fin having first sides of the first and second source/drain areas contacting a first dielectric spacer; a second fin on the semiconductor base, the second fin having third and fourth source/drain areas and a second gate body area between the third and fourth source/drain areas, the second fin having a top side opposite the semiconductor base and a bottom side contacting the semiconductor base, the second fin having first sides of the third and fourth source/drain areas opposite the first sides of the first and second source/drain areas contacting a second dielectric spacer, the second fin being substantially parallel to and spaced away from the first fin, the first and second fins defining a span therebetween; a third fin on the semiconductor base between the first and second fins, the third fin having fifth and sixth source/drain areas and a third gate body area between the fifth and sixth source/drain areas, the third fin having a top side opposite the semiconductor base and a bottom side contacting the semiconductor base in the fifth and sixth source/drain areas, first sides of the fifth and sixth source/drain areas contacting the first dielectric spacer and second sides of the fifth and sixth source/drain areas contacting the second dielectric spacer, a gate electrode substantially perpendicular to the first, second and third fins, the gate electrode having an electrode layer between first and second dielectric layers, the first dielectric layer contacting the semiconductor base in the span, the first dielectric layer contacting the top side of the first fin in the first gate body area, the first dielectric layer contacting the top side of the second fin in the second gate body area, and the second dielectric layer contacting the bottom side of the third fin in the third gate body area in the span.