Patent ID: 7402535
Filing Date: 2008-07-22
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising: forming source/drain regions in a substrate of a semiconductor wafer adjacent a gate structure located on a front side of the semiconductor wafer, the source/drain regions having a channel region located therebetween; placing a first stress-inducing layer on a backside of the semiconductor wafer, wherein the first stress-inducing layer is a first layer deposited on the backside of the semiconductor wafer such that the first stress-inducing layer resides only on the backside of the semiconductor wafer; subjecting the first stress-inducing layer to a thermal anneal to cause a stress to form in the channel region; and placing a second stress-inducing layer over the gate and source/drain regions wherein the second stress-inducing layer imparts a tensile stress to channel region.