Patent ID: 6372651
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of etching a semiconductor wafer having a plurality of layers to form a memory gate stack, the method comprising:forming a resist mask pattern containing pattern lines having a minimum resist line width of about 0.25 microns, overlying on an antireflective coating layer formed on the semiconductor wafer; first etching sidewalls of the resist mask pattern lines to a first prescribed reduced width of about 0.20 microns or less, without etching the antireflective coating layer; second etching the antireflective coating layer, based on the etched resist mask pattern lines, to form etched antireflective coating layer pattern lines having a second prescribed reduced width less than or equal to about 0.18 microns, and smaller than achievable by conventional deep ultraviolet photoexposure techniques; and third etching the plurality of layers underlying the antireflective coating layer based on the etched antireflective coating layer pattern lines.