Patent ID: 8289056
Filing Date: 2012-10-16
Classification: H03D,H03L

Abstract:
1. A circuit for controlling the delay of a clock signal in a system, comprising: a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal; a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, wherein the phase detector is an edge-triggered phase detector that locks when there is a substantially 270 degree phase difference between the rising edges of the system clock input and the substantially 270 degree phase shifted clock input; a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto; and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.