Patent ID: 7205194
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A method of fabricating a flash memory cell comprising the steps of: sequentially forming a first gate insulating layer, a floating gate layer, and a sacrificial layer on a semiconductor substrate; patterning the sacrificial layer to form a sacrificial layer pattern having an opening to expose a portion of the floating gate layer; forming a gate interlayer insulating layer in the opening and on a top surface of the sacrificial layer pattern; removing the gate interlayer insulating layer from the top surface of the sacrificial layer pattern to form a gate interlayer insulating layer pattern in the opening; removing the sacrificial layer pattern; etching the floating gate layer by using the gate interlayer insulating layer pattern as an etch mask so as to form a floating gate under the gate interlayer insulating layer pattern; forming a second gate insulating layer on the semiconductor substrate having the floating gate; and forming a control gate on the second gate insulating layer, overlapping a portion of the floating gate.