Patent ID: 7398368
Filing Date: 2008-07-08
Classification: G06F

Abstract:
1. In processor system having two or more processors including a main memory, a power processor element (PPE) and a synergistic processor element (SPE) that have different sized memory transfer capabilities, a method for atomic operation, the method comprising the steps of: a) dividing a main memory address containing a primitive into a parity byte and two or more portions, wherein the parity byte includes at least one bit, wherein a value of the parity byte determines which of the two or more portions is a valid portion and which of the two or more portions is an invalid portion, wherein the primitive is of a memory size that is larger than a maximum size for a memory transfer operation with the PPE and less than or equal to a maximum size for a memory transfer operation with the SPE; b) with the SPE, performing a read with reservation on a value of the parity byte and at least the valid portion; c) with the SPE, updating the valid portion to produce an updated valid portion; and d) with the SPE, conditionally writing back the value of the parity byte without changing it and writing the updated valid portion to the address containing the primitive, whereby the SPE writes the updated valid portion to the address containing the primitive if the reservation has not been lost; and e) if the reservation has been lost, repeating steps b), c) and d) with the SPE until the conditional write is successful.