Patent ID: 9214539
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A III-N (tri nitride) semiconductor device, comprising: a buffer layer disposed above a substrate; a crystalline or poly crystalline III-N layer disposed above the buffer layer; a source region located at a first location in or on the crystalline or poly crystalline III-N layer; a drain region located at a second location in or on the crystalline or poly crystalline III-N layer, wherein the second location is laterally disposed and separated from the source region; a gate region located at a third location on the crystalline or poly crystalline III-N layer, wherein the third location is laterally disposed between the source region and the drain region; and a hybrid gate dielectric layer disposed directly above the crystalline or poly crystalline III-N layer in the gate region, wherein the hybrid gate dielectric layer comprises a first dielectric layer and a second dielectric layer arranged over the first dielectric layer, the first dielectric layer having a first hydrogen to hydroxide ratio and the second dielectric layer having a second hydrogen to hydroxide ratio, the first hydrogen to hydroxide ratio being different than the second hydrogen to hydroxide ratio.