Patent ID: 6065141
Filing Date: 2000-05-16
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a normal memory portion having a memory cell matrix which is formed of a plurality of memory cells arranged at intersections of word lines and bit lines;a redundant circuit portion having memory cell arrays and operably coupled to said normal memory portion for replacing a defective memory cell in said normal memory portion in a form such that all memory cells connected to the word line or the bit line to which said defective memory cell is connected are replaced;a self-diagnostic circuit, operably coupled to said normal memory portion, for testing whether or not all memory cells operate normally;a defective cell position storage circuit, operably coupled to said self-diagnostic circuit, for storing a position of either a word line or a bit line connected to said defective memory cell when said self-diagnostic circuit detects said defective memory cell; andan output circuit, operably coupled to said defective cell position storage circuit, for converting, within said semiconductor memory device, position information indicating said position of said word line or bit line connected to said defective memory cell stored in said defective cell position storage circuit into serial data and for outputting converted position information out of said semiconductor memory device so that said position of said word line or bit line connected to said defective memory cell can be determined and thereafter replaced.