Patent ID: 6538466
Filing Date: 2003-03-25
Classification: H03K

Abstract:
A buffer circuit, comprising:an input stage, comprising at least one input node receiving a first signal, a first pull-up transistor, a first pull-down transistor, and an output node; a control circuit configured to (i) couple said first pull-up transistor to a first supply voltage and/or decouple said first pull-up transistor from said first supply voltage, (ii) couple said output node to a second supply voltage and/or decouple said output node from said second supply voltage, or (iii) both (i) and (ii); a stabilizing circuit comprising (i) a first p-channel transistor in a pull-up path and (ii) a first n-channel transistor in a pull-down path, each being independently coupled to at least one source/drain terminal of at least one of said first pull-up transistor and said first pull-down transistor, wherein said stabilizing circuit is configured to (i) increase a pull down current through said source/drain terminal of said first pull-down transistor in response to a reference signal, (ii) decrease a pull down current through said source/drain terminals of said pull-down transistor in response to said reference signal, or (iii) both (i) and (ii); and a reference voltage generating circuit configured to (a) generate said reference voltage and (b) compensate for at least (i) variations in said first supply voltage and/or said second supply voltage, (ii) variations caused by process skew, or (iii) both (i) and (ii), by varying said reference voltage in response thereto.