Patent ID: 6190179
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method for forming an integrated circuit device, comprising the steps of:forming a region in a substrate which is doped with impurities at a level which controls short channel device effects;forming a thin layer of monocrystalline silicon over the substrate adjacent the region, to a thickness of between approximately 500 and 1000 angstroms at a temperature of less than 850.degree. C.;forming a gate insulating layer over the monocrystalline silicon layer;forming a gate electrode over the gate insulating layer; andforming source/drain regions in the monocrystalline silicon layer on either side of the gate electrode and extending into but not through the region in the substrate, leaving a channel region underneath the gate electrode in the monocrystalline silicon layer having a length of less than one half micron.