Patent ID: 9099404
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. An array substrate, comprising: a plurality of sub-pixel units defined by gate lines and data lines that cross with each other on a substrate, each of the sub-pixel units comprising a first thin film transistor (TFT), a second TFT and a pixel electrode, a gate electrode of the first TFT being connected to the gate line, a source electrode of the first TFT being connected to the data line, and a drain electrode of the second TFT being connected to the pixel electrode, wherein, the source electrode and a drain electrode of the first TFT are formed on a same layer as a gate electrode of the second TFT, and the drain electrode of the first TFT is directly connected to the gate electrode of the second TFT, wherein one of the first TFT and the second TFT is a TFT with a top-gate structure, and the other of the first TFT and the second TFT is a TFT with a bottom-gate structure, and wherein the TFT with the top-gate structure comprises: a source electrode and a drain electrode that are formed on a surface of the substrate and separated from each other, an active layer formed between the source electrode and the drain electrode, a first insulating layer located directly above the source electrode and the drain electrode, a second insulating layer that covers the first insulating layer and the active layer, and a gate electrode located over the second insulating layer; and the TFT with the bottom-gate structure comprises: a gate electrode formed on the surface of the substrate, a first insulating layer formed over the gate electrode, an active layer formed over the first insulating layer, a second insulating layer which is formed over the active layer and by which a part of the active layer is exposed, and a source electrode and a drain electrode that are formed over the second insulating layer and contact with the exposed active layer.