Patent ID: 6624017
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A process for fabricating a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, having a collector region located at a lower portion of the substrate, the process comprising the steps of:defining a window above the substrate; providing a first implantation of germanium atoms through said window into the substrate; providing a second implantation of acceptor dopants through said window to define a base region in the substrate; applying an RTA treatment, or treatment in an oven, to re-construct a crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy; forming by chemical vapor deposition a first thin dielectric layer of silicon dioxide on the substrate; depositing a second dielectric layer onto said first dielectric layer; depositing a polysilicon layer onto said second dielectric layer; etching away, within the window region, said first and second dielectric layers, and the polysilicon layer, to expose the base region and form isolation spacers at edges of the window; and forming an N-doped emitter in the base and window regions.