Patent ID: 7894269
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. A method of programming a group of memory cells in parallel with reduced error due to perturbing electric fields from neighboring memory cells, comprising: (a) selecting a group of memory cells to be programmed in parallel to a given target state; (b) applying a predetermined dose of programming waveform voltage to the group of memory cells in parallel to increase a threshold voltage of each memory cell under programming; (c) verifying the programmed states of the group of memory cells relative to the given target state by determining the threshold voltage of the memory cell being verified relative to a predetermined verify level, the predetermined verify level being a function of the given target state and the target states of memory cells neighboring the memory cell being verified; (d) inhibiting from further programming memory cells in the group that have been verified; and repeating (b) to (d) until the memory cells of the group have all been verified to the given target memory state.