Patent ID: 8971094
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A memory interface device, the device comprising: an address input(s) configured to receive address information from an address stream of a host controller; an address output(s) configured to drive address information, the address output(s) being coupled to a plurality of memory devices wherein the plurality of memory devices comprise a plurality of DRAM devices; an address match table comprising at least a revised address corresponding to a spare memory location, the address match table further comprising a Row Address Match Table (RAMT) and a Column Address Match Table (CAMT); a control module configured to determine address information from an address stream from an address command bus coupled to a host controller during a run time operation, the control module being configured to compare each address from the address stream and configured to determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location, wherein a row address is sent to the RAMT, and for a row address match a column address associated with the row address populates the CAMT; and a multiplexer coupled to the address input and coupled to the address output.