Patent ID: 8285971
Filing Date: 2012-10-09
Classification: G06F

Abstract:
1. A processor, comprising: an instruction sequencing unit that sequences processing of compiled program code by the processor, wherein the compiled program code includes executable instructions, an operand data structure describing a plurality of sequentially processed computation blocks, and block computation commands invoking processing of the computation blocks, wherein the instruction sequencing unit asserts an initiation signal in response to detecting a block computation command in the compiled program code; at least one execution unit that, responsive to receipt of executable instructions of the complied program code from the instruction sequencing unit, executes the executable instructions; at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit; data storage that buffers the operand data structure of the compiled program code, wherein the operand data structure describes the plurality of sequentially processed computation blocks of the compiled program code not executed by the at least one execution unit, and wherein the operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and specifies a different second relationship between addresses of sequential accesses within a second address region; and a programmable address generation accelerator programmed by the operand data structure, wherein the address generation accelerator, responsive to receipt of the initiation signal from the instruction sequencing unit, computes and outputs, to a memory hierarchy including at least one memory external to the processor, first and second effective addresses of operands of an operation in one of the plurality of computation blocks by reference to the first and second relationships specified by the operand data structure.