Patent ID: 6711057
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a first memory cell array including a plurality of electrically re-programmable MOS type main memory cells arranged in a matrix form, the plurality of main memory cells being selected according to an input address; a second memory cell array including a plurality of electrically data-programmable MOS type redundancy memory cells arranged in at least row or column of the matrix form, the plurality of redundancy memory cells being selected according to a redundancy address; a first storage configured to be write-controlled by a first write control signal in a specified mode, which stores a specified code inputted from outside; a first comparator configured to compare a selected code inputted from outside in the specified mode with the specified code stored in the first storage to generate an activating signal when the selected code coincides with the specified code; a faulty address latch circuit configured to be activated by the activating signal generated by the first comparator, the defective address latch circuit being controlled by a latch control signal when a fault is generated in the first memory cell array in the specified mode, to temporarily latch a fault address corresponding to the fault; a second storage configured to be write-controlled by a second write control signal in the specified mode, which stores the faulty address latched by the latch circuit; a second comparator configured to compare the input address with the faulty address storing in the second storage to generate a replacement control signal when the input address coincides with the faulty address; and a replacing circuit configured to be controlled by the replacement control signal to replace an output of the first memory cell array with an output of the second memory cell array.