Patent ID: 6114231
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method for forming a bonding pad in a pad area of an IC chip, comprising:(1) preparing a substrate on which at least a pad area and an active region are defined;(2) forming a first insulating layer in the pad area;(3) forming a gate oxide layer over the first insulating layer;(4) forming a polysilicon gate layer over the gate oxide layer;(5) forming a second insulating layer over the polysilicon gate layer;(6) forming a third insulating layer over the second insulating layer in the pad area, wherein after said third insulating layer is formed, the active region is free of the third insulating layer;(7) conducting a dry etch process on the third insulating layer and the second insulating layer in sequence in the pad area to form a plurality of first openings through the third insulating layer and a plurality of second openings through the second insulating layer, the first openings being positioned directly above, and being in communication with, the respective second openings in the pad area, wherein the second openings expose the surface of the polysilicon gate layer in the pad area;(8) conducting a wet etch process through the first openings and on the second insulating layer to widen the second openings in the pad area, so that the second openings are wider than the corresponding first openings thereabove;(9) forming a first conformal metallization layer over the third insulating layer and the entire inner wall surfaces of the first openings and the second openings;(10) forming a second metallization layer which fills up the first openings and the second openings, wherein the second metalization layer directly connects with the polysilicon gate layer in the pad area;(11) planarizing the second metallization layer and the third insulating layer to form a plug, the plug being firmly affixed within both the second opening and the corresponding first opening;(12) forming a third metallization layer over the second metallization layer and the third insulating layer; and(13) completing the fabrication of the IC chip in which the third metallization layer in the pad area serves as a bonding pad.