Patent ID: 6184082
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of fabricating a dynamic random access memory, comprising:providing a substrate;forming a gate on the substrate, the gate comprising a cap layer and a spacer;forming a first source/drain and a second source/drain in the substrate;forming a first dielectric layer over the substrate;patterning the first dielectric layer to form a capacitor opening therein, which exposes the cap layer, the spacer and the first source/drain;forming a conformal first stop layer covering the first dielectric layer and the capacitor opening;removing a part of the conformal first stop layer on the first source/drain to form a self-aligned node contact opening;forming a first conducting layer covering the capacitor opening, the self-aligned node contact opening and the conformal first stop layer;forming a second dielectric layer covering the first conducting layer and filling the capacitor opening and the self-aligned node contact opening;performing a chemical mechanical polishing process to remove the second dielectric layer and the first conducting layer that are formed over the first stop layer while using the first stop layer as a polish stop layer, so that remaining first conducting layer is used as a bottom plate of a capacitor;removing the remained second dielectric layer;forming a capacitor dielectric layer on the substrate;forming a second conducting layer on the capacitor dielectric layer;pattering the second conducting layer and the capacitor dielectric layer to expose a part of the first stop layer over the second source/drain, wherein the patterned second conducting layer is used as a top plate of the capacitor;forming a conformal second stop layer over the substrate;forming a third dielectric layer over the conformal second stop layer;removing a part of the third dielectric layer over the second source/drain, the conformal second stop layer, the first stop layer and the first dielectric layer underneath to form a self-aligned bit line contact opening, which exposes the second source/drain;forming a third conducting layer covering the third dielectric layer and filling the self-aligned bit line contact opening to connect to the second source/drain; andpatterning the third conducting layer to form a bit line.