Patent ID: 6414892
Filing Date: 2002-07-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:a row decoder selecting a row; word lines that extend from the row decoder and are connected to memory cells; a dummy word line that extends from starting ends of the word lines substantially in parallel therewith and returns to the starting ends in which the dummy word line is folded back in a predetermined position of a total length of the word lines; a sense amplifier that amplifies data read from a memory cell coupled to a selected one of the word lines at a timing defined by a signal propagated along the dummy word line; bit lines that supply the sense amplifier with the data read from the memory cell coupled to said selected one of the word lines; a timing control signal generating part generating a timing control signal that controls a drive timing of the sense amplifier; and a dummy bit line that has a length approximately equal to a total length of the bit lines and extend approximately in parallel with the bit lines, the dummy bit line being connected to the timing control signal, dummy data obtained from the signal propagated along the dummy word line being supplied to the timing control signal generating part, which generates the timing control signal based on the dummy data.