Patent ID: 8815691
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A method of fabricating a device, the method comprising: forming a fin in a wafer substrate, wherein the fin includes a fin base, and at least one pair of a first fin layer and a second fin layer alternatively disposed on the fin base wherein the second fin layer has a significantly different etching rate compared to the first fin layer; forming an isolation feature over the wafer substrate and around the fin; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes forming a bottom sacrificial layer, a middle sacrificial layer over the bottom sacrificial layer and a top sacrificial layer over the middle sacrificial layer; depositing a spacer along sidewall of the dummy gate stack; after depositing the spacer, removing the top sacrificial layer, the middle sacrificial layer and the bottom sacrificial layer; removing the first fin layer to form a cavity around the second fin layer; and forming a gate stack in the cavity and around the second fin layer to form a gate all around (GAA) in the second fin layer.