Patent ID: 6500765
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A method of manufacturing a field effect transistor with a dual-spacer structure, comprising the steps of:providing a substrate having a first device region and a second device region, wherein the first device region comprises a first gate formed over the substrate and the second device region comprises a second gate formed over the substrate; forming a first dielectric layer over the substrate; forming a second dielectric layer on the first dielectric layer; removing a portion of the second dielectric layer to expose a portion of the first dielectric layer in the second device region; removing a portion of the remaining second dielectric layer to form a first spacer on the second dielectric layer on the sidewall of the first gate; and removing a portion of the first dielectric layer to form a second spacer on the sidewall of the second gate, wherein the first spacer and the remaining second dielectric layer between the first spacer and the first gate together form a third spacer.