Patent ID: 9201097
Filing Date: 2015-12-01
Classification: G01R,H01L

Abstract:
1. An apparatus for electrically testing an IC die, comprising: a partially completed and validated module including: an IC package substrate, one or more known good IC dice attached on a first surface of the IC package substrate at first regions, and package pads on the first surface of the IC package substrate at a second region; a pick and place tool for positioning a test subject IC die on the second region of the IC package substrate such that interconnection bumps of the test subject IC die are facing and aligned with the package pads of the module, the positioned test subject IC die and the module forming a multi-die flip-chip test assembly; and test circuitry electrically connected with the module for electrically testing the multi-die flip-chip test assembly without the test subject IC die being attached to the module.