Patent ID: 8707113
Filing Date: 2014-04-22
Classification: G01R,G06F

Abstract:
1. A method for operating a data processing system to generate a test for a device under test (DUT), said method comprising: providing a model of said DUT comprising a plurality of blocks connected by wires and a set of control inputs, each block comprising a plurality of ports, each port being either active or inactive, each block being characterized by a set of constraints that limit which ports are active, each constraint in said set of constraints comprising an equation or inequality involving variables representing whether each port is active or inactive, at least one of said constraints in said set of constraints characterizing one of said plurality of blocks involving a variable representing one of said control inputs in said set of control inputs; defining a test vector having one component for each port of each block of said plurality of blocks and one component for each control input in said set of control inputs; and causing said data processing system to determine a valid test for said DUT by determining each component of said test vector such that each set of constraints for each block of said plurality of blocks is satisfied.