Patent ID: 9176863
Filing Date: 2015-11-03
Classification: G06F

Abstract:
1. A memory controller interfacing with a host and a nonvolatile memory, comprising: a buffer unit configured to store an input address table and a first hot address table; and a processing unit configured to judge whether an address from the host coincides with an address stored in the input address table and to store the address from the host in the first hot address table according to the judgment, the processing unit storing the address from the host in the input address table according to a first-in first-out (FIFO) manner, wherein the buffer unit further includes a second hot address table, wherein the processing unit stores the address from the host in the second hot address table when the address from the host coincides with at least one address stored in the first hot address table, wherein the processing unit determines a type of the address from the host based upon the first and second hot address tables, wherein if the address from the host coincides with at least one address stored in the second hot address table, the processing unit determines the type of the address from the host by determining whether the address from the host is a first hot address, wherein if the address from the host coincides with at least one address stored in the first hot address table while not coinciding with at least one address stored in the second hot address table, the processing unit determines the type of the address from the host by determining the address from the host as a second hot address, and wherein if the address from the host does not coincide with at least one address stored in either of the first and second hot address tables, the processing unit determines the type of the address from the host by determining the address from the host as a cold address.