Patent ID: 7091616
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; an electrode pad formed on said semiconductor substrate; a first insulation layer formed on said semiconductor substrate except for the area having the electrode pad; an external connecting terminal; a leading wiring layer connecting said external connecting terminal to said electrode pad and formed on a surface, opposite to the semiconductor substrate, of said first insulation layer, said leading wiring layer including a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer, and the first barrier metal layer and the second barrier metal layer cover entire surroundings including the side, bottom and top surfaces of the main conductor layer, and the main conductor layer including a base layer and a main layer, which is formed by plating; a second insulation layer, formed on said first insulation layer, covering side surfaces of the leading wiring layer substantially to the top surface of the main conductor layer; and a third insulation layer formed on said second insulation layer and said leading wiring layer.