Patent ID: 6066865
Filing Date: 2000-05-23
Classification: H01L

Abstract:
A periodic table group III-V semiconductor material enhancement mode field-effect transistor comprising the combination of:a plurality of undoped periodic table group III-V semiconductor material layers received on a substrate member;a masking inorganic dielectric material layer covering an outermost of said semiconductor material layers and having selected mask apertures therein;said masking dielectric material layer-covered semiconductor material layers including a buried, charge carrier-communicating, field-effect transistor channel layer;a gate window aperture through at least one semiconductor layer covering said channel layer, said gate window aperture being in registration with one of said masking inorganic dielectric material layer mask apertures;a Schottky barrier gate element received in charge carrier flow-controlling proximity of said channel layer in said gate window aperture;source and drain current conductor elements located on charge carrier flow upstream and downstream sides of said gate window aperture and each comprising aligned stacks of locally doped successive layer semiconductor material extending between stack ends at said outermost semiconductor material layer and said channel layer;source and drain ohmic contact elements received on said outermost semiconductor material layer each in registration with other non-gate of said mask apertures and in electrical connection therein with one of said current conductor outermost semiconductor material layer stack ends;said gate element and said source and drain ohmic contact elements being comprised of a same metallic common composition.