Patent ID: 7295679
Filing Date: 2007-11-13
Classification: G06T,H04N

Abstract:
1. An encoding apparatus comprising: a first memory configured to store therein block data; a counter configured to define a position of the block data; a second memory connected to the first memory and configured to store therein lower bit-plane data of the block data; a third memory connected to the first memory and configured to store therein upper bit-plane data of the block data, which is obtained by subtracting the lower bit-plane data from the block data; a polynomial generator configured to generate a generator polynomial; a code calculator connected to the third memory and to the polynomial generator, and configured to generate redundant code data based on the upper bit-plane data, using the generator polynomial; a fourth memory connected to the code calculator and configured to store therein the redundant code data; an encoder connected to the second memory and to the fourth memory, and configured to embed the redundant code data into the lower bit-plane data to form encoded lower bit-plane data; and a data generator connected to the third memory and to the encoder, and configured to add the encoded lower bit-plane data to the upper bit-plane data to form encoded block data.