Patent ID: 6150215
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method for ensuring no capacitor peeling at the edge of a wafer in the fabrication of an integrated circuit device comprising:providing a substrate having a semiconductor structure formed thereon;forming an insulating layer overlying said semiconductor structure;patterning said insulating layer to define a contact window;depositing a conductive layer over said insulating layer and filling up said contact window;coating a photoresist layer overlying said conductive layer;removing a first portion of said photoresist in between said edge of said wafer and a first distance inwardly away from said edge of said wafer;removing a second portion of said photoresist in between said edge of said wafer and a second distance inwardly away from said edge of said wafer, said second distance is greater than said first distance;carrying out a photolithography process against said photoresist layer to form a photoresist mask;etching said conductive layer where it is not covered by said photoresist mask to form a lower capacitor electrode; andremoving said photoresist mask.