Patent ID: 6263032
Filing Date: 2001-07-17
Classification: G11B,H03L,H04L

Abstract:
A phase detector for a timing control loop provided in a signal sampling system to control acquisitions of samples, separated from one another by corresponding sampling intervals, of magnitudes of input signals provided at an input of said signal sampling system by a sampler that forms sequences of said samples of those input signals at an output thereof which are supplied to a data output of said signal sampling system, said phase detector comprising:a slope estimator having a slope indication output and having a first signal input coupled to said signal sampling system input, said slope estimator being capable of determining magnitude values of said input signals provided at said signal sampling system input during said sampling intervals to provide therefrom estimates of slopes of such signals for corresponding said sampling intervals, and of providing indications of said slope estimates at said slope indication output thereof;an error determiner having a signal input coupled to said sampler output to receive said samples and having a magnitude error output, said error determiner being capable of providing indications of error magnitudes at said output thereof corresponding to those said samples received thereby based on differences in magnitude occurring between such said samples and expected values therefor;a phase error estimation combiner having an output, and having a slope indication input coupled to said slope estimator slope indication output and an error indication input coupled to said error determiner magnitude error output, said phase error estimation combiner being capable of providing phase error estimates at said output thereof for corresponding said sampling intervals based on signals occurring at said error indication input thereof as selectively modified by signals provided at said slope input thereof;a first signal delayer having an input coupled to said phase error estimation combiner output and having an output, said first signal delayer being capable of delaying signals provided at said input thereof for transmission therethrough to said output thereof for a said sampling interval; anda summer having an output, a first input coupled to said phase error estimation combiner output and a second input coupled to said first signal delayer output, said summer being capable of providing an output signal at said output thereof which is an algebraic sum of corresponding signals provided on said first and second inputs thereof.