Patent ID: 6424196
Filing Date: 2002-07-23
Classification: G06K,H03K

Abstract:
A master-slave D type flip-flop circuit comprising:a master stage; a slave stage connected to said master stage and having a substantially identical structure thereto, said slave stage comprising an internal node, a first pass gate for providing an input data element on the internal node, and a storage loop comprising at least one inverter connected to the internal node and supplying output data at an output, and a second pass gate for providing data complementary to the output-data on the internal node; and a power consumption masking circuit comprising a respective reference stage in parallel with each of said master and slave stages and having a substantially identical structure except that the at least one inverter of each reference stage is disconnected from the output of its respective master stage or slave stage and that the second pass gate of the storage loop of each reference stage is connected between the output of its respective master stage or slave stage and the internal node of said reference stage.