Patent ID: 6806540
Filing Date: 2004-10-19
Classification: H01L,Y10S

Abstract:
A semiconductor device, comprising:a first transistor including a first gate formed on a semiconductor substrate, a first low impurity concentration diffusion layer formed on the surface of said semiconductor substrate in a manner to surround said first gate, a first high impurity concentration diffusion layer formed on the surface of the semiconductor substrate in a manner to surround said first low impurity concentration diffusion layer and to have a shallower diffusion depth than a diffusion depth of said first low impurity concentration diffusion layer, and a first gate side wall formed to surround the first gate with a top surface of the first gate being exposed from an upper end of the first gate side wall, and an interface between the first low impurity concentration diffusion layer and the first high impurity concentration diffusion layer corresponding to a lower end of an outer surface of the first gate side wall; and a second transistor including a second gate formed on the semiconductor substrate, a second low impurity concentration diffusion layer formed on the surface of the semiconductor substrate in a manner to surround said second gate, a second high impurity concentration diffusion layer formed on the surface of the semiconductor substrate in a manner to surround said second low impurity concentration diffusion layer and to have a shallower diffusion death than a diffusion depth of said second low impurity concentration diffusion layer, and a second gate side wall formed to surround said second gate and having a thickness equal to that of the first gate side wall of said first transistor, a top surface of the second gate being. exposed from an upper end of the second gate side wall; wherein the size of said second low impurity concentration diffusion layer formed on the surface of the semiconductor substrate, which extends from said first gate to reach said first high impurity concentration diffusion layer, is larger than the size of said first low impurity concentration diffusion layer formed on the surface of the semiconductor substrate, which extends from said first gate to reach said first high impurity concentration diffusion layer, an effective lower end of an outer surface of the second gate side wall being positioned within a surface region of the second low impurity concentration diffusion layer and outside of a surface region of the second high impurity concentration diffusion layer, said first low impurity concentration diffusion layer is an N-type diffusion layer having a low impurity concentration, said first high impurity concentration diffusion layer is an N-type diffusion layer having a high impurity concentration said first transistor is an N-type transistor, said second low impurity concentration diffusion layer is a P-type diffusion layer having a low impurity concentration, said second low impurity concentration diffusion layer is A P-type diffusion layer having a low impurity concentration, and said second transistor is a P-type transistor.