Patent ID: 9064751
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A thin film transistor array substrate comprising a cell array corresponding to a display area, and a Gate driver In Panel (GIP) corresponding to a partial area of a non-display area around the display area, wherein the GIP includes: a first wiring formed on a substrate; a first insulating film formed over the substrate to cover the first wiring; a second wiring formed on the first insulating film; a second insulating film formed over the first insulating film to cover the second wiring; a third insulating film formed over the second insulating film; a first contact hole perforated through the first, second, and third insulating films to expose a part of the first wiring; a second contact hole perforated through the second and third insulating films to expose a part of the second wiring; and a third wiring formed on the third insulating film to connect the first and second wirings to each other through the first and second contact holes, wherein, in the partial area of the non-display area, the third insulating film includes a first area, a second area and a third area, the first area where the third insulating film is removed to correspond to the first and second contact holes, the second area corresponding to a gap region between the first and second contact holes, the second area being within a first thickness range, and the third area as a remaining area except for the first and second areas, the third area being within a second thickness range different from the first thickness range, and wherein the minimum value of the first thickness range is greater than the maximum value of the second thickness range.