Patent ID: 8760930
Filing Date: 2014-06-24
Classification: G11C

Abstract:
1. A circuit arrangement for sensing a state of one or two bits in a plurality of non-volatile memory cells in non-volatile memory devices comprising: a first memory cell comprising a first bit of said one or two bits having a first side connected through a first bit line to a drain bias circuit and a second side connected through a second bit line to a source driver circuit; a second memory cell having a first side connected to said second bit line and a second side connected through a third bit line to a source driver circuit; a third memory cell having a first side connected to said third bit line and a second side connected through a fourth bit line to a source driver circuit; a fourth memory cell having a first side connected to said fourth source bit line and a second side connected through a fifth bit line to a source driver circuit; a fifth memory cell having a first side connected to said fifth bit line and a second side connected through a sixth bit line to a source driver circuit; a sixth memory cell having a first side connected to said sixth bit line and a second side connected through a seventh bit line to a source driver circuit; and a seventh memory cell comprising a second bit of said one or two bits having a first side connected through said seventh bit line to a source driver circuit and a second side connected through an eight bit line to a drain bias circuit.