Patent ID: 6074910
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method for fabricating an array of memory cells for a dynamic random access memory, each memory cell having an associated capacitor, comprising:forming an array of memory cell transistors, one for each memory cell, each having a source, a drain coupled to a bit line, and a gate coupled to a word line;forming a lower conductive layer over the array of memory cell transistors, the lower conductive layer being electrically coupled to the source of each of the memory cell transistors;patterning and forming a protective layer over a predetermined portion of the lower conductive layer to define an isolation region, the protective layer being continuous over the isolation region, the protective layer having a gap to define an interior portion of a bottom electrode of the capacitor;removing a portion of the lower conductive layer under the protective layer to define the shape of the interior portion of the bottom electrode;removing the protective layer;forming an insulation layer adjacent the lower conductive layer;removing a portion of the insulation layer to expose a portion of the lower conductive layer;removing the exposed portion of the lower conductive layer so as to form an electrically separate bottom plate of the capacitor associated with each memory cell;removing the insulation layer;forming a capacitor dielectric adjacent the lower conductive layer; andforming an upper conductive layer adjacent the capacitor dielectric so as to form a top plate of the capacitor associated with each memory cell.