Patent ID: 7169654
Filing Date: 2007-01-30
Classification: H01L

Abstract:
1. A method for integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate, comprising: providing a semiconductor substrate having an active semiconductor layer; forming openings within the active semiconductor layer in a first region of the semiconductor substrate and openings within the active semiconductor layer in a second region of the semiconductor substrate, wherein the first region corresponds to a non-MOS transistor device portion of the semiconductor substrate and the second region corresponds to a CMOS electronic device portion of the semiconductor substrate, wherein forming includes using a dual trench process that includes forming the openings in the non-MOS transistor device portion to a first depth, and forming the openings in the CMOS electronic device portion to a second depth, the second depth being greater than the first depth; forming a non-MOS transistor device liner on sidewalls, as well as on a bottom surface, of the openings of the first depth within the active semiconductor layer in the non-MOS transistor device portion of the semiconductor substrate; forming a trench liner on sidewalls within the openings of the active semiconductor layer in the CMOS electronic device portion of the semiconductor substrate; forming first and second non-MOS transistor device implant regions within portions of the active semiconductor layer underlying the first and second openings of the first depth, respectively, in the non-MOS transistor device portion, wherein the first and second openings of the first depth comprise respective first and second shallow trenches; filling the openings of the active semiconductor layer in the non-MOS transistor device portion of the semiconductor substrate and the openings of the active semiconductor layer in the CMOS electronic device portion of the semiconductor substrate with a fill material and planarizing the fill material; exposing a top surface portion of the active semiconductor layer disposed in-between the first and second shallow trenches in the non-MOS transistor device portion of the semiconductor substrate; forming first and second low dose non-MOS transistor device well regions in respective first and second portions of the active semiconductor layer disposed in-between the first and second shallow trenches in the non-MOS transistor device portion of the semiconductor substrate; forming first and second high dose non-MOS transistor device connectivity regions in respective third and fourth portions of the active semiconductor layer in the non-MOS transistor device portion of the semiconductor substrate; forming at least a portion of a CMOS electronic device on the active semiconductor layer within the CMOS electronic device portion of the semiconductor substrate; forming a salicide blocking layer overlying at least the first and second low dose non-MOS transistor device well regions in the non-MOS transistor device portion of the semiconductor substrate; forming first and second non-MOS transistor device contact regions in top portions of respective third and fourth portions of the semiconductor layer in the non-MOS transistor device portion of the semiconductor substrate; saliciding the electronic device portion and a portion of the non-MOS transistor device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the first and second low dose non-MOS transistor device well regions in the non-MOS transistor device portion of the semiconductor substrate; and forming an interlevel dielectric layer overlying the non-MOS transistor device portion and the CMOS electronic device portion of the semiconductor substrate.