Patent ID: 6503807
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A method of forming a MOS transistor comprising:forming a silicon nitride layer on a surface of a semiconductor wafer; forming a vertical trench on the silicon nitride layer which is down to the surface of the semiconductor wafer, the trench having a trench bottom and two trench side walls; forming a first silicon oxide layer on the surface of the trench; forming two spacers at two corners between the trench bottom and the two trench side walls; removing the first silicon oxide layer positioned over the trench bottom between the two spacers and forming an insulation layer in an area where the first silicon oxide layer was removed; forming a conductive layer to cover the surface of the silicon nitride layer and the trench; removing the conductive layer and the first silicon oxide layer on the surface of the silicon nitride layer outside the trench by using a chemical mechanical polishing (CMP) method to form a gate of the transistor; removing the silicon nitride layer from the surface of the semiconductor wafer; performing ion implantation in two predetermined areas on the surface of the semiconductor wafer next to the two trench side walls to form a drain and a source of the transistor; removing the first silicon oxide layer positioned over the two trench side walls; removing the two spacers; performing ion implantation over the two spots on the trench bottom which are previously occupied by the two spacers to extend the drain and the source; and forming two empty slots in the positions previously occupied by the two spacers by covering the surfaces of the gate, drain, and source with a dielectric layer, thus reducing parasitic capacitances between the gate and the drain, and, between the gate and the source.