Patent ID: 6075392
Filing Date: 2000-06-13
Classification: G06F,H03K,H03L,H04L

Abstract:
A circuit for the glitch-free changeover of digital signals, comprising:a multiplexer having a multiplicity of signal input terminals, signal select terminals, and a signal output terminal;a circuit output connected to said multiplexer for outputting a circuit output signal;a counter logic unit connected to said multiplexer for counting pulses in an output signal of said multiplexer and for outputting a count signal when a specific count value has been reached;a delay logic unit connected to said multiplexer for delaying a multiplexer select signal and for outputting a switching signal after a change of the multiplexer select signal and for outputting a delayed multiplexer select signal; and an OR gate connected to said multiplexer for masking the output signal with the switching signal, wherein said counter logic unit is activated during a set switching signal.