Patent ID: 6754777
Filing Date: 2004-06-22
Classification: G06F,G11C

Abstract:
A method of operating a first-in first-out (FIFO) memory device having a multi-port cache memory device and an embedded memory device therein, comprising the steps of:activating a first embedded memory path within the multi-port cache memory device that supports operations to transfer a first page of data from an input port of the multi-port cache memory device to the embedded memory device during FIFO write operations; activating a second embedded memory path within the multi-port cache memory device that supports operations to transfer the first page of data from the embedded memory device to an output port of the multi-port cache memory device during FIFO read operations that occur when a number of next-to-read pages of data in the FIFO memory device is greater than a threshold number of pages of data; and activating a direct path within the multi-port cache memory device that supports operations to bypass the embedded memory device by transferring a second page of data directly from the input port of the multi-port cache memory device to the output port of the multi-port cache memory device during FIFO read operations that occur when the number of next-to-read pages of data in the FIFO memory device is less than the threshold number of pages of data.