Patent ID: 6127207
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A fabrication method of a semiconductor integrated circuit comprising a plurality of input/output control circuits, a plurality of pad driver cells, wherein each pad driver cell is connectable to respective lead frames, and a wiring region formed between the plurality of input/output control circuits and the plurality of pad driver cells, the fabrication method comprising:a step of forming the plurality of pad driver cells whose number is equal to or more than the number of input/output control circuits;a step of forming wirings connected to input and output terminals in each of the plurality of input/output control circuits and wirings connected to input and output terminals in each of the plurality of pad driver cells in the wiring region, the wirings having an inherent length, respectively;a step of connecting, in the wiring region, the wirings connected to the plurality of input/output control circuits and the wirings connected to the plurality of pad driver cells by using wirings made up of another material different from the wirings connected to the plurality of input/output control circuits and different from the wirings connected to the plurality of pad driver cells;a step of not connecting specified input/output control circuits to pad driver cells;a step of not connecting specified pad driver cells to input/output control circuits; anda step of connecting selected pad driver cells to the lead frames by using wirings.