Patent ID: 7440417
Filing Date: 2008-10-21
Classification: H04L

Abstract:
1. An apparatus, comprising: a semiconductor substrate; N substantially identical processing units fabricated on the substrate, where N>1, any one or more of the processing units capable of receiving from a classifier a starting instruction of a set of instructions to be followed to process a frame according to a frame protocol and encapsulation technique; first internal data memory fabricated on said substrate, said data memory for storing instruction sets accessible to said N processing units, wherein an instruction set is unique for a specific protocol and encapsulation technique a dispatcher operatively coupled to the N processing units for receiving and transmitting to one of the N processing units a frame; a classifier implemented by function-specific circuitry coupled to the dispatcher, said classifier fabricated on the substrate to determine from the frame a protocol by which the frame is formatted, an encapsulation technique employed in the frame, and to determine within two clock cycles a starting address of an instruction set to process the frame by one of the N processing units assigned to process the frame, the starting address depending upon the protocol and encapsulation technique of the frame; and a completion unit carried on the semiconductor substrate and operatively connected to the N processing units to receive a frame processed by the one of the N processing units.