Patent ID: 8063664
Filing Date: 2011-11-22
Classification: G06F,Y02D

Abstract:
1. An apparatus comprising: means for using a state machine to assert a first enable signal, wherein the state machine, a first supply current switch circuit (SCSC) and a chain of SCSCs are parts of a single integrated circuit; means for propagating the first enable signal through the first SCSC, wherein the first SCSC includes a switch having a control terminal, and wherein when the first enable signal is on the control terminal, the switch couples a local supply bus to a global supply bus through the first SCSC; means for using the state machine to assert a second enable signal, wherein the second enable signal is asserted a programmable number of clock cycles after a first clock cycle is asserted; and means for propagating the second enable signal through the chain of SCSCs, wherein each SCSC in the chain includes a switch having a control terminal, wherein when the second enable signal is present on the control terminal of a switch in an SCSC in the chain, then the switch couples the local supply bus to the global supply bus through the SCSC, and wherein the second enable signal is made to propagate through the control terminal of the switch of each SCSC in the chain.