Patent ID: 7485519
Filing Date: 2009-02-03
Classification: H01L

Abstract:
1. A method of fabricating a field effect transistor (“FET”) having a channel region in a silicon-on-insulator (“SOI”) layer of an SOI substrate, the SOI substrate including (i) the SOI layer separated from (ii) a bulk semiconductor layer by (iii) a buried dielectric layer including a flowable dielectric material, the method comprising: a) forming trench isolation regions adjacent to peripheral edges of an active semiconductor region of the SOI layer, the trench isolation regions extending from a major surface of the SOI layer towards the buried dielectric layer; b) forming a gate overlying the active semiconductor region between the peripheral edges; c) forming a sacrificial stressed layer overlying the gate and the active semiconductor region; d) heating the SOI substrate to cause the flowable dielectric material to soften, causing the sacrificial stressed layer to induce a stress in a portion of the active semiconductor region underlying the gate; e) removing the sacrificial stressed layer; and f) forming a source region and a drain region after removing the sacrificial stressed layer.