Patent ID: 9224637
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method of forming a transistor comprising: forming a gate electrode; subsequently forming a first etch-stop layer over the gate electrode; subsequently forming source and drain areas in the substrate on either side of the gate electrode; subsequently forming a gate electrode insulation layer over the gate electrode, the gate electrode insulation layer formed of a low etch rate material; subsequently forming a second etch-stop layer, the second etch-stop layer lying in contact with the gate electrode insulation layer and in contact with the source and drain areas; subsequently forming a layer of high etch rate material over the second etch-stop layer; subsequently forming an etch mask that defines a first opening over the gate electrode, a second opening over the source area, and a third opening over the drain area; subsequently performing a first etch step that extends the first opening to the second etch-stop layer and extends the second and third openings into the layer of high etch rate material; and subsequently performing a second etch step that extends the first opening through the gate insulation layer to the first etch-stop layer and extends the second and third openings through the layer of high etch rate material to the second etch-stop layer, the second etch step having a very low etch rate for the first and second etch-stop layers.