Patent ID: 6515925
Filing Date: 2003-02-04
Classification: G11C

Abstract:
A sense amplifier control circuit for a memory device comprising:a first logic gate having a first input coupled to a source of a global control signal, a second input coupled to a source of a first section signal, and an output; a second logic gate having a first input coupled to said source of said global control signal, a second input coupled to a source of a second section signal, and an output; a third logic gate having a first input coupled to said source of said global control signal, a second input coupled to said source of said second section signal, and an output; a fourth logic gate having a first input coupled to said source of said global control signal, a second input coupled to a source of a third section signal, and an output; said first, second, third and fourth logic gates substantially electrically equidistant from said source of said global control signal; a fifth logic gate having a first input coupled to said output of said first logic gate, a second input coupled to said output of said second logic gate, and an output coupled to a sense amplifier on a first side of a section of said memory; and a sixth logic gate having a first input coupled to said output of said third logic gate, a second input coupled to said output of said fourth logic gate, and an output coupled to a sense amplifier on a second side of a section of said memory, wherein when said global control signal and said second section signal are active, said fifth and sixth logic gates provide a sense amplifier control signal to said sense amplifiers on said first and second sides of said section of said memory, respectively, to activate said sense amplifiers on said first and second sides of said section of said memory substantially simultaneously.