Patent ID: 6396744
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A non-volatile memory comprising:a plurality of memory cells; erase, write, and read circuitry coupled to the memory cells; a refresh timer; a memory management unit coupled to control the erase, write, and read circuitry, wherein in response to a signal from the refresh timer, the memory management unit directs the erase, write, and read circuitry to perform a refresh operation that includes reading data without generating a data signal for output from the non-volatile memory and writing the data to refresh threshold voltages of memory cells storing the data; and an address mapping circuit, wherein: the refresh operation reads the data from a first set of the memory cells and writes the data to a second set of memory cells; before the refresh operation, the address mapping circuits converts an virtual address signal corresponding to the data to a first physical address that corresponds to the first set of memory cells; and after the refresh operation, the address mapping circuit converts the virtual address signal corresponding to the data to a second physical address that corresponds to the second set of memory cells.