Patent ID: 9190006
Filing Date: 2015-11-17
Classification: G09G,G11C

Abstract:
1. A display device comprising: a plurality of pixel circuits each of which includes a transistor, a pixel electrode connected to the transistor, and a reference electrode disposed so as to be opposite to the pixel electrode, wherein the plurality of pixel circuits are arranged in a matrix; a plurality of data lines respectively connected to the plurality of corresponding pixel circuits; a plurality of gate lines respectively connected to the plurality of corresponding pixel circuits; a data circuit configured to output data signals to the plurality of data lines; a plurality of gate circuits each of which sequentially outputs a gate signal, which is in a high voltage level during two or more horizontal periods in a first order or in a second order that is reverse to the first order, wherein the number of the plurality of gate circuits is based on horizontal periods when the gate signals are output; and a gate signal control circuit that controls each of the gate circuits and scans the plurality of gate lines, wherein the gate signal control circuit controls each of the gate circuits to start to output the gate signals so as not to overlap periods when the gate signals are output to the adjacent gate lines, wherein a first gate circuit is configured to output an i-th gate signal to an i-th gate line, and a second gate circuit is configured to output an (i+1)-th gate signal to an (i+1)-th gate line after at least 3 horizontal periods from a time when the first gate circuit stops outputting the i-th gate signal, wherein the data circuit is configured to output data signals corresponding to the (i+1)-th gate line after at least one horizontal period after the second gate circuit starts to output the (i+1)-th gate signal to the (i+1)-th gate line, and wherein the first gate circuit is configured to output an (i+2)-th gate signal to an (i+2)-th gate line between the time when the first gate circuit stops outputting the i-th gate signal and the second gate circuit starts outputting the (i+1)-th gate signal such that the first gate circuit stops outputting the (i+2)-th gate signal at a time before the second circuit starts outputting the (i+1)-th gate signal.