Patent ID: 6392433
Filing Date: 2002-05-21
Classification: G01R

Abstract:
A method of testing semiconductor devices comprising the steps of:a) adhering either a packaged semiconductor device collective body constructed by a plurality of packaged semiconductor devices integrated together or a plurality of individual packaged semiconductor devices onto an adhesive tape provided on a tape-holding member, in a case of said packaged semiconductor device collective body, first, said semiconductor device collective body is adhered on the adhesive tape and then diced into individual packaged semiconductor devices, and in case of said plurality of individual packaged semiconductor devices, first, said packaged semiconductor device collective body is diced into individualized packaged semiconductor devices, and then, said individual packaged semiconductor devices are adhered onto the adhesive tape, b) correcting postions of the packaged semiconductor devices by mounting the tape-holding member on a position correction unit and, using an image processing technique, impementing position recognition and position correction of the packaged adhesive tape adhesive tape; and c) implementing an electrical characteristic test on the packaged semiconductor devices positioned in step b) by connecting the packaged semiconductor devices to a testing conductor.