Patent ID: 9135112
Filing Date: 2015-09-15
Classification: G06F,G11C

Abstract:
1. An apparatus comprising: a non-volatile memory; and a controller operatively coupled to the non-volatile memory and comprising an error correction engine configured to perform error correction on codewords read from the non-volatile memory and, upon error correction failure, to perform one or more retry procedures, wherein the controller is configured to (i) perform read and write operations on the non-volatile memory using the codewords as a unit of read access, (ii) in response to the error correction failure or one or more of the retry procedures not being successful, perform one or more background procedures configured to determine a cause of the error correction failure, (iii) in response to determining the error correction failure is due to transient noise, eliminate the transient noise by recycling on a block or R-block granularity, and (iv) in response to all of the retry procedures not being successful, send an error message.