Patent ID: 6774028
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method of forming a wiring structure by using a dual damascene process comprising:forming a first interlayer insulating film on a lower conductive layer; forming a second interlayer insulating film on the first interlayer insulating film; forming a first photo resist film on the second interlayer insulating film, the first photo resist film having an opening for forming a via hole; etching the first and second interlayer insulating films by using the first photo resist film as a mask to form a via hole; forming an anti-reflective coating on the second interlayer insulating film such that a portion of the via hole is also filled with the material of the anti-reflective coating; forming a second photo resist film on the anti-reflective coating such that a remaining portion of the via hole is also filled with the material of the second photo resist film, a development rate of an exposed portion of the second photo resist film being 250-700 nm/second; exposing and developing the second photo resist film by using a photolithography technology and thereby forming an opening for forming a wiring trench in the second photo resist film; etching the anti-reflective coating and the second interlayer insulating film by using the second photo resist film as a mask to form a wiring trench; removing the second photo resist film and the anti-reflective coating; and filling the via hole and the wiring trench with a conductive material to form a via portion which is coupled with the lower conductive layer and a wiring conductor portion which is coupled with the via portion.