Patent ID: 8069337
Filing Date: 2011-11-29
Classification: G06F

Abstract:
1. An apparatus comprising: two register files, each register file operable to hold a plurality of entries of a first bit width; three execution units, each execution unit configurable to operate on an entry of the first bit width and two of the three execution units configurable to operate as a combined execution unit on an entry of a second bit width, wherein the second bit width is greater than the first bit width; and a control unit receiving a first instruction and a second instruction for parallel execution, wherein the control unit in response to the first instruction accesses one entry from the plurality of entries at one at the two register files to be operated on by one of the three execution units as a first input value, and wherein the control unit in response to the second instruction accesses two entries, one from each of the two register files, and wherein the control unit combines the two entries into a second input value of the second bit width to be operated on by the combined execution unit.