Patent ID: 6240036
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A semi conductor memory device comprising:a plurality of memory cell arrays, each memory cell array including a plurality of word lines, a plurality of p airs of bit lines, each including a first bit line and a second bit line intersecting the word lines, and a plurality of memory cells located at intersections of the word lines and the first bit lines, said memory cells storing data therein;a plurality of sense amplifier arrays which are respectively located between the memory cell arrays, each sense amplifier array including a plurality of sense amplifier circuits, each sense amplifier circuit connected to one of the pair of bit lines and setting a voltage of the first bit line to a first voltage and a voltage of the second bit line to a second voltage which is lower than the first voltage in response to a sense amplifier active signal during a sensing period;a power supply conductive layer which receives a power supply; anda voltage supply circuit which supplies the first voltage to the plurality of sense amplifier arrays, and which includes a plurality of MOS transistors and a control circuit which outputs a control signal and controls the plurality of MOS transistors, wherein each MOS transistor is arranged between the power supply conductive layer and one of the sense amplifiers, wherein each MOS transistor has a gate electrode which receives the control signal, and wherein the control circuit outputs the control signal in response to a reference voltage and a voltage of a connection point between the MOS transistor and the sense amplifier array.