Patent ID: 8724423
Filing Date: 2014-05-13
Classification: G11C

Abstract:
1. A memory operative to provide concurrent two-port read and two-port write access functionality, the memory comprising: a memory array, the memory array comprising a first plurality of single-port memory cells, a second plurality of single-port memory cells operative as spare memory banks, and a plurality of checksum modules, the first and second pluralities of single-port memory cells being organized into a plurality of rows of memory banks, each of the plurality of checksum modules being associated with a corresponding one of the plurality of rows of memory banks; a first controller coupled with the memory array, the first controller and at least a subset of the first and second pluralities of single-port memory cells being operative to enable the memory array to support two-port read or single-port write operations; a plurality of mapping tables; and a second controller operative to receive read and write access requests supplied to the memory, and to map a logical memory bank identifier and a spare memory bank identifier to corresponding physical memory bank identifiers via the mapping tables for resolving access conflicts in the memory to thereby emulate concurrent two-port read and two-port write access functionality in the memory.