Patent ID: 7619918
Filing Date: 2009-11-17
Classification: G11C

Abstract:
1. An apparatus comprising: a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; and a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page from the any one of the plurality of multiple level memory cell that includes the first logical memory page and the second logical memory page, wherein N is an integer equal to the number of data bits the plurality of multiple level memory cells are operable to store.