Patent ID: 6195673
Filing Date: 2001-02-27
Classification: G06F

Abstract:
A FOD (First-One-Detector) circuit for detecting the number of leading zeros counted from a most significant bit to a first one (""1"") in a binary number input, wherein the FOD circuit includes a plurality of unit blocks connected in cascade depending on the number of fraction input bits and each respectively provided with a plurality of transmission transistors, each said unit block, comprising:a first transmission transistor for transmitting a fraction input in accordance with a control signal outputted in accordance with a previous bit;an inverter for inverting the fraction input bit and outputting a control signal with regard to a corresponding transmission transistor for a subsequent input bit;a second transmission transistor for fixing an output signal of the first transmission transistor to a high level in accordance with the control signal outputted in accordance with the previous input bit; anda logic gate for ANDing the fraction input bit and the control signal outputted in accordance with the previous input bit and outputting the number of leading zeros counted from the most significant bit of the fraction input.