Patent ID: 6211014
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method for manufacturing a three-dimensional, deep-trench, high-density ROM, the method comprising the steps of:performing ion implantation to form a plurality of parallel bit lines on a surface of a silicon substrate;forming a photoresist layer to expose a plurality of channel regions of the substrate where non-conducting memory cells are desired;performing an etching operation, using the photoresist layer as a mask, to form a trench in each of the channel regions, each trench having a trench depth larger than a depth of each of the bit lines;forming a second photoresist layer to expose a plurality of channel regions of the substrate where conducting memory cells are desiredusing the second photoresist layer as a mask, performing an etching operation to form a plurality of shallow trenches, each shallow trench having a depth approximately equal to the depth of each of the bit linessequentially forming a gate oxide layer and a polysilicon layer on the surface of the silicon substrate; anddefining the gate oxide and polysilicon layers to form a plurality of word lines that are perpendicular to the plurality of bit lines.