Patent ID: 9218975
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A method of forming replacement gate structures for first and second transistors, comprising: forming first and second sacrificial gate structures above a semiconducting substrate, each of said first and second sacrificial gate structures comprising at least a sacrificial gate electrode; performing at least one first etching process to remove at least said sacrificial gate electrode structure from each of said first and second sacrificial gate structures so as to define a first gate cavity and a second gate cavity, said first and second gate cavities being defined by first and second spaced-apart sidewall spacers, respectively, positioned in a layer of insulating material formed above said substrate; forming a gate insulation layer in said first and second gate cavities; performing a first deposition process to deposit a first intermetallic compound material in said first and second gate cavities on and in contact with said gate insulation layer so as to over-fill said first and second gate cavities with said first intermetallic compound material; performing at least one second etching process to remove portions of said first intermetallic compound material that are positioned in said second gate cavity; performing a second deposition process to deposit a second intermetallic compound material in said second gate cavity on and in contact with said layer of insulating material so as to over-fill said second gate cavity with said second intermetallic compound material and form said second intermetallic compound above said first intermetallic compound material, wherein said first intermetallic compound material and said second intermetallic compound material are different materials; and performing at least one planarization process operation to remove portions of said first and second intermetallic compound materials positioned outside of said first and second gate cavities so as to define: