Patent ID: 6794898
Filing Date: 2004-09-21
Classification: G01R

Abstract:
A scan flip-flop circuit for receiving a first signal and a second signal, passing the first signal in a first operation, and passing the second signal in a second operation, comprising:a selecting section having a first input terminal for receiving a first signal, a second input terminal for receiving a second signal, and a third input terminal for receiving a control signal instructing one of a first operation and a second operation to be performed, for outputting a signal based on the first signal when the control signal instructs a first operation and outputting a signal based on the second signal when the control signal instructs a second operation; a latch section for latching a signal based on an output signal of the selecting section synchronously with a clock and outputting the signal; a first output terminal for outputting an output signal of the latch section; and a second output terminal provided separately from the first output terminal, for outputting a fixed signal in a first operation and outputting a signal based on a second signal in a second operation, wherein the selecting section has a 2-1 OR-AND-INVERTER configuration which outputs inversion of AND of an input signal to the second input terminal and OR of the input signal to the first input terminal and the input signal to the third input terminal.