Patent ID: 8710510
Filing Date: 2014-04-29
Classification: H01L

Abstract:
1. A transistor, comprising: a drift layer having a first conductivity type; a heavily doped well region in the drift layer and having a second conductivity type opposite the first conductivity type; an epitaxial channel adjustment layer on the drift layer and having the first conductivity type; an emitter region adjacent the epitaxial channel adjustment layer and extending through the epitaxial channel adjustment layer and into the well region, the emitter region having the first conductivity type and at least partially defining a channel region in the well region adjacent to the emitter region; a gate oxide layer on the channel region; and a gate on the gate oxide layer; wherein the drift layer comprises a JFET region adjacent to the well region, and wherein the emitter region is spaced apart from the JFET region and defines the channel region between the emitter region and the JFET region, and wherein the JFET region has a higher dopant concentration than a remaining portion of the drift layer.