Patent ID: 6087209
Filing Date: 2000-07-11
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming a surface amorphous region extending from and below a major surface of a semiconductor substrate, the amorphous region having a peak impurity concentration at a first depth from the major substrate surface;ion implanting a P-type impurity to form a dopant impurity region and generate an interstitial-rich region, a major portion of which is within the amorphous region, the dopant impurity region having a peak impurity concentration at a second depth from the major substrate surface;ion implanting to form a sub-surface, non-amorphous impurity region extending below, but not extending from, the major surface of the semiconductor substrate, and a vacancy-rich region substantially overlapping the interstitial-rich region generated when forming the dopant impurity region, wherein the non-amorphous impurity region has a peak impurity concentration at a third depth from the major substrate surface greater than the first and second depths; andactivation annealing to form lightly doped source/drain regions extending below the major surface of the semiconductor surface and having a junction depth (X.sub.J).