Patent ID: 6476630
Filing Date: 2002-11-05
Classification: G01R

Abstract:
An apparatus for providing signal paths between ports of an integrated circuit (IC) tester and first test points arranged on an IC wafer when the IC tester is testing the IC wafer, and for enabling the IC tester to measure resistance of the signal paths when it is not testing the IC wafer, the apparatus comprising:an interconnect structure comprising contacts arranged to contact the first test points of the IC wafer when the IC tester is testing the IC wafer, and comprising conductors interconnecting the ports of the IC tester to the contacts, wherein the conductors and contacts form said signal paths; and a reference wafer similar in size and shape to said IC wafer to be tested, said reference wafer having thereon a plurality of second test points in an arrangement substantially similar to an arrangement of said first test points on said IC wafer, said contacts contacting the first test points when the IC tester is testing the IC wafer, and contacting the second test points when the IC tester is measuring the resistance of said signal paths.