Patent ID: 7184446
Filing Date: 2007-02-27
Classification: H04L

Abstract:
1. An apparatus comprising: set of input ports; a FIFO storage buffer; request logic coupling said set of input ports to said FIFO storage buffer; a memory in communication with said request logic, wherein said memory concurrently maintains a plurality of pointers, wherein each pointer in said plurality of pointers corresponds to a different location in said FIFO storage buffer for storing data from an input port in said set of input ports, wherein the request logic simultaneously writes data to the FIFO storage buffer for at least two of the input ports; a set of data rings in communication with said set of input ports; a ring interface coupled to said set of data rings to accent data from a plurality of sources and supoly said data on a plurality of outputs, said FIFO storage buffer in communication with said ring interface to receive and store said data from said ring interface; and an output port coupled to said FIFO storage buffer to receive data from said FIFO storage buffer and transmit said data from said FIFO storage buffer on a communications link.