Patent ID: 7287155
Filing Date: 2007-10-23
Classification: G06F

Abstract:
1. A storage control system connected to an external device, comprising: a plurality of storage devices that store data; a cache memory that temporarily stores data that is exchanged between said storage devices and said external device; and a control device that controls the exchange of data performed between said storage devices and said external device through said cache memory; wherein said control device comprises: a processor that controls said exchange; a start-up memory region that stores start-up data required for starting up said processor and protection data including start-up protection code constituting protection code for said start-up data; and data checking hardware; wherein: said start-up data includes a start-up data most significant element constituting the element on the most significant side of said start-up data, and a start up-data least significant element constituting the element on the least significant side of said start-up data; said protection data includes most significant protection data constituting the element on the most significant side of said protection data, and least significant protection data constituting the element on the least significant side of said protection data; said start-up protection code includes start-up most significant protection code constituting the protection code of the most significant element of said start-up data, and start-up least significant protection code constituting the protection code of the least significant element of said start-up data; said start-up memory region comprises a first start-up sub-memory region and a second start-up sub-memory region; said first start-up sub-memory region stores said start-up data most significant element and said least significant protection data; said least significant protection data includes a second address representing an address in said second start-up sub-memory region, a second address protection code constituting the protection code of the second address, and said start-up data least significant element; said second start-up sub-memory region stores said start-up data least significant element and said most significant protection data; said most significant protection data includes a first address representing an address in said first start-up sub-memory region, a first address protection code constituting the protection code of the first address, and said start-up data most significant element; said data checking hardware; reads said least significant protection data and said start-up data most significant element from said first start-up sub-memory region; reads said most significant protection data and said start-up data least significant element from said second start-up sub-memory region; performs a first sub-check that checks the validity of said start-up data most significant element by using said start-up most significant protection code in said most significant protection data, and a second sub-check that checks the validity of said start-up data least significant element by using said start-up least significant protection code in said least significant protection data; and if a negative check result is obtained in at least one of said first sub-check and said second sub-check, resets said processor and, if a positive check result is obtained in both of said first sub-check and said second sub-check, inputs said start-up data most significant element and said start-up data least significant element to said processor.