Patent ID: 8117517
Filing Date: 2012-02-14
Classification: G06F,G11C,H03M,Y02D

Abstract:
1. A semiconductor memory device comprising: a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively; a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks comprising one of the data items and a corresponding detecting code; a second correcting code generator configured to generate a second correcting code to correct errors in a second data block, the second data block comprising the first data blocks; and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code, wherein an error correction capability of the second correcting code generator is higher than error correction capabilities of the first correcting code generators.