Patent ID: 6806161
Filing Date: 2004-10-19
Classification: H01L,Y10S

Abstract:
A process for preparing a porous wiring interlayer insulating film having very low dielectric constant for a semiconductor comprising the steps of:a) preparing a mixed complex of matrix resin and pore-forming material, the matrix resin is selected from the group consisting essentially of: organosilane of Chemical Formula 1: R1mR2nSiX4-m-n (where each of R1 and R2 which may be the same or different, is a non-hydrolysable group selected from hydrogen, alkyl, fluorine-containing alkyl or aryl group; X is a hydrolysable group selected from halide, alkoxy or acyloxy; and m and n are integers of from 0 to 3 satisfying 0&lE;m+n&lE;3) or a partially hydrolyzed condensate thereof; organic bridged silane of Chemical Formula 2: R3pY3-pSiâ€”Mâ€”SiR4qZ3-q (where each of R3 and R4 which may be the same or different, is a non-hydrolysable group selected from hydrogen, alkyl, fluorine-containing alkyl, alkenyl or aryl; each of Y and Z which may be the same or different, is a hydrolysable group selected from halide, alkoxy or acyloxy; M is alkylene or arylene group; and p and q are integers of from 0 to 2) or a cyclic oligomer with organic bridge unit (Siâ€”Mâ€”Si) or a partially hydrolyzed condensate thereof; and a mixture thereof; and the pore-forming material containing an organic part having one or more thermally decomposable organic linkage groups, and at least one silyl functional group at the terminal of the pore-forming material so that the pore-forming material can be connected by covalent bonding with the matrix resin; b) coating the mixed complex on a substrate; and c) heating the mixed complex to remove the organic part of the pore-forming material, thereby forming pores inside the complex.