Patent ID: 7872310
Filing Date: 2011-01-18
Classification: H01L

Abstract:
1. A semiconductor structure, comprising; a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure comprises a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between and in direct mechanical contact with the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, wherein the thick mesa structure comprises a semiconductor mesa in direct mechanical contact with the surface of the buried oxide layer, wherein the thick mesa structure comprises a source region and a drain region, wherein the source region and drain regions are each on and in direct mechanical contact with the semiconductor mesa structure, wherein the semiconductor mesa is disposed between the surface of the buried oxide layer and both the source region and the drain region, and wherein the semiconductor structure further comprises: