Patent ID: 6687175
Filing Date: 2004-02-03
Classification: G11C

Abstract:
A semiconductor device, comprising a word line, a first bit line pair, a memory cell provided at an intersection of said word line and said first bit line pair, a second bit line pair, a switch circuit for coupling said first bit line pair and said second bit line pair, a sense amplifier including a first circuit connected to said first bit line pair and a second circuit connected to said second bit line pair, a first precharge circuit for precharging said first bit line pair to a first precharge potential and a second precharge circuit for precharging said second bit line pair to a second precharge potential, whereinsaid second circuit amplifies one of said first and second bit line pairs to a first potential and the other to a second potential from a storage signal of said memory cell, said first precharge potential is ranged between said first and second potentials, said second precharge potential is said second potential, and thickness of a gate oxide film of a MOSFET included in said switch circuit is thicker than a gate oxide film of a MOSFET included in said sense amplifier.