Patent ID: 7099226
Filing Date: 2006-08-29
Classification: G11C

Abstract:
1. In a multiple plane memory having a common address space and capable of multiple types of memory access operations, each memory plane having independent address decoding logic dedicated to the address space for that plane, a functional register decoding system for routing of command and address information to designated planes, the decoding system comprising: a plurality of functional registers dedicated to distinct memory access operations, each register configured to receive an input address, and to provide at least one address output in accord with its dedicated memory access operation; a plurality of plane selector blocks, each plane selector block dedicated to a distinct one of the memory planes, each plane selector block configured to receive as inputs the address outputs from all of the plurality of functional registers, the plane selector blocks routing a selected one of its inputs as an output to its dedicated plane in accord with a control signal input; and plane function select means configured to receive decoded plane and command information for providing control signals to the plurality of plane selector blocks in accord with the decoded information such that command information for a particular memory access operation and plane information for a particular one of the memory planes are used to route address outputs from the functional register dedicated to that memory access operation to that particular memory plane.