Patent ID: 8217460
Filing Date: 2012-07-10
Classification: H01L

Abstract:
1. A semiconductor device having an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film, said semiconductor device comprising: at least two of first, second, third and fourth PN-junction elements, wherein said first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of said P-channel FET and said N-channel FET, respectively, wherein said second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in said P-channel FET, respectively, wherein said third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in said N-channel FET, respectively, wherein said fourth PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the channel regions of said N-channel FET and said P-channel FET, respectively, and wherein said at least two PN-junction elements are connected in series in a forward bias between two different terminals to form an electrostatic protection device.