Patent ID: 6291978
Filing Date: 2001-09-18
Classification: G01R

Abstract:
A method for testing node interconnection on a circuit board having a plurality of nodes using an automated test system comprising at least one test channel, each of the at least one test channel comprising a digital driver having a first input and a first output, a digital receiver having a second output and a second input, the second input being coupled to the first output, and a test probe, the test probe being coupled to the first output and the second input, and the test probe being configured to couple the first output and second input to one of the plurality of nodes, the method comprising:(a) said digital driver of a first test channel applying a test signal to a selected node of the plurality of nodes;(b) a predetermined amount of time after said application of said test signal, said digital receiver of the first test channel reading a node voltage of said selected node;(c) comparing said node voltage to a predetermined threshold voltage of said digital receiver of the first test channel; and(d) indicating whether said selected node is coupled to ground based on said comparison of said node voltage to said threshold voltage.