Patent ID: 8878828
Filing Date: 2014-11-04
Classification: G09G

Abstract:
1. A display driver circuit, comprising: a first multi-function driver configured to support a first mode of operation in response to a first control signal through a single line by driving a bus with a first output signal having a value that indicates a locked or unlocked status of a first clock signal therein and further configured to support a second mode of operation in response to a second control signal through a single line by driving the bus with first data unrelated to the locked or unlocked status of the first clock signal, said first data formatted to include, in sequence, a start-data header, read-out data and an end-data footer having an alternating bit signature: and a timing controller configured to provide a first training clock to said first multi-function driver in response to receiving the first output signal having a value that indicates an unlocked status of the first clock signal, said unlocked status reflected by a missing end-data footer following detection by said timing controller of a start-data header associated with the first data.