Patent ID: 6150721
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A multilevel interconnect structure, comprising:first interconnects arranged within a first elevational plane, said first interconnects being at least partially arranged upon an underlying dielectric layer arranged above a semiconductor substrate;a first dielectric layer arranged above said first interconnects;a second dielectric layer arranged upon said first dielectric layer;a third interconnect arranged within a third elevational plane and upon said second dielectric layer;a second interconnect arranged within a second elevational plane and electrically coupled to a first contact, wherein said first contact extends through said first dielectric layer from a first one of said first interconnects to said second interconnect, wherein said second interconnect extends to an upper surface of said second dielectric layer a diagonally spaced distance away from said third interconnect;a second contact extending through said pair of dielectric layers between a second one of said first interconnects and said third interconnect; andwherein said first interconnects, said first contact, said second interconnect, said second contact, and said third interconnect are arranged within a same cross-sectional plane.