Patent ID: 7616516
Filing Date: 2009-11-10
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array including plural static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines, wherein the static memory cell includes: first and second CMOS inverter circuits whose inputs and outputs are cross-connected to each other; and selection switch MOSFETs provided between input terminals of the first and second CMOS inverter circuits and corresponding complementary bit lines, gates of the selection switch MOSFETs being connected to corresponding word lines, the memory cell array includes: first and second source lines to which sources of N-channel MOSFETs and P-channel MOSFETs constituting the first and second CMOS inverter circuits constituting the plural static memory cells are connected; a switch MOSFET provided between the first source line and a first power supply line corresponding to the first source line, turned to an OFF state in a first operation mode, and turned to an ON state in a second operation mode which is different from the first operation mode; an N-channel MOSFET provided between the first source line and the first power supply line and having a source connected to a P well on which the N-channel MOSFET is formed, a drain and a gate of the N-channel MOSFET being connected to each other to have a diode configuration; and a P-channel MOSFET provided between the first source line and the first power supply line and having a source connected to an N well on which the P-channel MOSFET is formed, a drain and a gate of the P-channel MOSFET being connected to each other to have a diode configuration, and the second source line is connected to the second power supply line corresponding to the second source line.