Patent ID: 8859979
Filing Date: 2014-10-14
Classification: H04N

Abstract:
1. Matrix microelectronic device comprising: a plurality of elementary cells laid out according to a matrix, each elementary cell of said plurality of elementary cells comprising at least one current source formed by at least one current source transistor, a source electrode of said current source transistor being connected to a source biasing conductor line, wherein the matrix microelectronic device comprises a plurality of source biasing conductor lines each connecting source electrodes of current source transistors of a respective given row of cells of the matrix, a gate electrode of said current source transistor being connected to a gate biasing conductor line, wherein the matrix microelectronic device comprises a plurality of gate biasing conductor lines each connecting gate electrodes of current source transistors of a respective different row of cells of the matrix that is orthogonal to said given row, wherein the matrix microelectronic device further comprises: a biasing device for biasing the gate biasing conductor lines, said biasing device comprising: at least one first connection line that is connected to at least several of said gate biasing conductor lines, and a voltage generator comprising a first device for applying a first potential to a first end of said first connection line and a second device for applying a second potential to a second end of said first connection line, opposite the first end, wherein said first connection line is provided with a linear resistance that is identical or substantially equal to or proportional to a respective linear resistance of said source biasing conductor lines and said voltage generator causes a decrease of potentials along said first connection line thereby compensating a corresponding decrease of potentials along the source biasing conductor lines.