Patent ID: 7657805
Filing Date: 2010-02-02
Classification: G06F

Abstract:
1. An integrated circuit, comprising: state logic configured to store operating state of said integrated circuit; a test control unit configured to coordinate access by external circuitry to operating state of said state logic during a test mode of operation of said integrated circuit; a plurality of interface pins configured to couple said integrated circuit to said external circuitry, wherein members of a subset of said interface pins are configured as shared interface pins; wherein each of said shared interface pins is operable to provide a respective input signal to said test control unit during said test mode of operation and is further operable, during a normal mode of operation of said integrated circuit, to perform a respective integrated circuit input/output (I/O) function distinct from its function during said test mode of operation; wherein said plurality of interface pins includes a blocking pin that, when asserted by said external circuitry during said normal mode of operation, is configured to force test signals derived from at least a portion of said shared interface pins by said test control unit into respective quiescent states, such that subsequent to assertion of said blocking pin, said integrated circuit is operable to enter said test mode of operation from said normal mode of operation without resetting operating state of said state logic.