Patent ID: 7433240
Filing Date: 2008-10-07
Classification: G11C

Abstract:
1. A non-volatile memory device including a page buffer circuit coupled to at least one pair of first bit lines and at least one pair of second bit lines, the pair of first bit lines coupled to first memory cells of a first memory cell block, the pair of second bit lines coupled to second memory cells of a second memory cell block, the page buffer circuit comprising: a first bit line select circuit configured to select one of the first bit lines in response to first discharge signals and first bit line select signals and to couple the selected first bit line to a sensing node; a second bit line select circuit configured to select one of the second bit lines in response to second discharge signals and second bit line select signals and to couple the selected second bit line to the sensing node; a sensing circuit configured to sense a voltage of the sensing node in response to a latch control signal and to generate sensing data to a first node according to the sensing result; a latch circuit configured to latch the sensing data received in a read operation or input data received in a program operation, or both; a program control circuit configured to output the input data received from the latch circuit to the first or second bit line coupled to the sensing node in response to a first program control signal; a verify circuit configured to generate verify data in response to a verify control signal and the sensing data received from the latch circuit; a first voltage sustain circuit configured to maintain one voltage level selected by the first bit line select circuit of the first bit lines to a voltage level of the input data in response to a second program control signal during one program operation of the first memory cells, wherein the first voltage sustain circuit comprises: a second voltage sustain circuit configured to maintain one voltage level selected by the second bit line select circuit of the second bit lines to a voltage level of the input data in response to a third program control signal during one program operation of the second memory cells, wherein during one program operation of the first memory cells, a logic value of the input data output to the first bit line by the program control circuit and a logic value of the input data output to the second bit line by the program control circuit are substantially the same, and wherein when the first bit line select circuit couples one of the first bit lines to the sensing node, the second bit line select circuit separates the second bit lines from the sensing node.