Patent ID: 6351363
Filing Date: 2002-02-26
Classification: H01L,H02H

Abstract:
An ESD protection circuit provided between a bonding pad and the internal circuit of an IC device for the purpose of protecting the internal circuit of the IC device against any ESD voltage applied to the bonding pad; the 2-stage polydiode-based ESD protection circuit comprising:a first stage of polydiode circuit including a first polydiode and a second polydiode, the first polydiode having a positive end connected to a first node connected to the bonding pad and a negative end connected to a first system voltage, and the second polydiode having a positive end connected to a second system voltage lower in level than the first system voltage and a negative end connected to the first node, wherein the first polydiode and the second polydiode each include a P+ part, an N+ part, and an Nâˆ’ part disposed between the P+ part and the N+ part; a resistor having a first end connected to the first node and a second end connected to a second node; a second stage of polydiode circuit including a first polydiode and a second polydiode, the first polydiode having a positive end connected to the second node and a negative end connected to the first system voltage, and the second polydiode having a positive end connected to the second system voltage and a negative end connected to the second node, wherein the first polydiode and the second polydiode each include a P+ part, an N+ part, and an Nâˆ’ part disposed between the P+ part and the N+ part; and a power protection circuit, connected between the first system voltage line and the second system voltage line, for draining ESD current on the first system voltage line to the second system voltage line wherein a width of the Nâˆ’ part of the first stage of polydiode is larger than a width of the Nâˆ’ part of the second stage of polydiode.