Patent ID: 7022568
Filing Date: 2006-04-04
Classification: G11C,H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising steps of: providing a semiconductor substrate with a memory cell including a first first-channel MISFET, a second first-channel MISFET, a first second-channel MISFET and a second second-channel MISFET, each having a gate electrode formed over said substrate and each having a source region and a drain region formed in said substrate, wherein a first insulating film is formed on said gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs; forming a first conductive film and a second conductive film on said first insulating film such that said first conductive film is electrically connected to said drain region of said first first-channel MISFET, said drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET, and such that said second conductive film is electrically connected to said drain region of said second first-channel MISFET, said drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET; forming a dielectric film on said first conductive film and said second conductive film; and forming a third conductive film on said dielectric film so as to cover substantially all over said first conductive film and said second conductive film such that said first conductive film, said dielectric film, and said third conductive film form a capacitor element and such that said second conductive film, said dielectric film, and said third conductive film form a capacitor element.