Patent ID: 7443032
Filing Date: 2008-10-28
Classification: C23C,H01L,Y10S,Y10T

Abstract:
1. A memory device, comprising: a memory array, including a control circuit and an I/O circuit operatively coupled to the memory array; and wherein at least one of the memory array, control circuit and I/O circuit further comprises: a layer of a titanium alloy formed overlying walls of a contact hole, wherein the titanium alloy comprises titanium and an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony; and a titanium silicide contact having a composition that is different from the layer of titanium alloy, the contact being directly coupled to the layer of titanium alloy wherein the titanium alloy comprises titanium and zinc.