Patent ID: 6100162
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method of forming a circuitry isolation region within a semiconductive wafer comprising:masking an active area region over a semiconductive wafer, the active area region being provided with an impurity doping of a first conductivity type;ion implanting an impurity of a second conductivity type within the semiconductive wafer proximate the masked active area region to a dose greater than or equal to 1.times.10.sup.14 ions/cm.sup.2 ;annealing the wafer at a temperature of at least about 800.degree. C.;after the annealing, substantially selectively wet etching second conductivity type provided semiconductive wafer material relative to first conductivity type provided semiconductive wafer material forming a trench proximate the active area region, the wet etching using a solution comprising HNO.sub.3 and HF in a volumetric ratio of at least 15:1 of one to the other, the wet etching achieving a selectivity of at least 10:1; andforming electrically insulating material within the trench.