Patent ID: 6407333
Filing Date: 2002-06-18
Classification: H01L,Y10T

Abstract:
An integrated circuit device made by the process comprising:providing a semiconductor wafer having a plurality of integrated circuits formed on a first side thereof; disposing a strip of lead frames having a plurality of lead frames on said first side of said wafer so that each lead frame is aligned with one of said plurality of integrated circuits, each lead frame being entirely within a periphery of an area of said wafer along which said wafer will be separated to form a respective integrated circuit device; electrically coupling each lead frame to said respective integrated circuit; encapsulating said semiconductor wafer, with said lead frames attached, in its entirety, said encapsulant covering said first side and having an upper side which is opposite said first side but not in contact thereto, a portion of each of said lead frames being exposed along said upper side; separating said wafer along said periphery to produce individual integrated circuit devices, side walls of said integrated circuit devices produced by said separation step being substantially perpendicular to said first side of said wafer, whereby no portion of said lead frame protrudes beyond said side walls of said individual integrated circuit devices.