Patent ID: 6271136
Filing Date: 2001-08-07
Classification: C23C,H01L

Abstract:
A method comprising:providing a substrate or wafer having an insulator layer deposited upon said substrate;providing a first level of conducting wiring over said insulator layer;depositing a first and second dielectric layer over said first level of conducting wiring;patterning and etching the dielectric layers forming dual damascene trench/via openings;heating up said substrate or wafer;depositing by metal-organic chemical vapor deposition (MOCVD), a diffusion barrier layer over said dielectric layers covering and lining said trench/via;exposing the said diffusion barrier layer to a N.sub.2, H.sub.2 gas plasma forming a nitride diffusion barrier layer;exposing the said diffusion barrier layer to a silane gas plasma injecting silicon into said barrier layer;pumping and purging out unwanted byproducts from said barrier layer and from said substrate or wafer;depositing by chemical vapor deposition a copper seed layer over said diffusion barrier layer;depositing by electrochemical deposition (ECD) copper conducting material over said copper seed layer and removing the excess material layers to from conducting copper dual inlaid structures.