Patent ID: 6225208
Filing Date: 2001-05-01
Classification: H01L,Y10S

Abstract:
A method of fabricating interconnections on a substrate, the method comprising:covering multiple surface structures on the substrate with a first isolation layer;etching a portion of the first isolation layer to expose portions of the multiple surface structures and portions of the substrate between the multiple surface structures;depositing a first conductive material to cover the multiple surface structures and portions of the substrate between the multiple surface structures;forming a second isolation layer on the first conductive material;etching a portion of the second isolation layer and a portion of the first conductive material above portions of an adjacent pair of the multiple surface structures until the portion of the first conductive material is beneath and in between the adjacent pair, and is isolated from portions of the first conductive material covered part of top surfaces of the adjacent pair;forming spacers between the portion of the first conductive material beneath and in between the adjacent pair and the portions of the first conductive material covered part of top surfaces of the adjacent pair;forming a second conductive material on the first conductive material beneath and in between the adjacent pair;covering second conductive material and the second isolation layer with a third isolation layer; andforming a contact opening to one of the portions of the first conductive material covered part of top surfaces of the adjacent pair.