Patent ID: 9142572
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. An array substrate, comprising: a substrate; a plurality of gate lines disposed on the substrate and substantially extended along a first direction; a plurality of first data lines and a plurality of second data lines disposed on the substrate and substantially extended along a second direction, wherein the first data lines and the second data lines are arranged sequentially and alternately in the first direction, each of the first data lines has a plurality of first data line segments respectively disposed between two adjacent ones of the gate lines, and each of the second data lines has a plurality of second data line segments respectively disposed between the two adjacent ones of the gate lines; a plurality of first thin film transistors, disposed on the substrate, wherein each of the first thin film transistors comprises: a plurality of second thin film transistors disposed on the substrate, wherein each of the second thin film transistors comprises: wherein: the first data line segment, the second data line segment and the next first data line segment arranged sequentially in the first direction define a first gap and a second gap; the second gap is greater than the first gap; the first source electrode, the second source electrode and the next first source electrode arranged sequentially in the first direction are respectively corresponding to the first data line segment, the second data line segment and the next first data line segment to define a third gap and a fourth gap; the third gap is greater than the first gap; and the fourth gap is smaller than the second gap.