Patent ID: 6981176
Filing Date: 2005-12-27
Classification: G06F

Abstract:
1. A controller, comprising: a primary processing unit; a secondary processing unit coupled to the primary processing unit; a common memory coupled to the primary and secondary processing units, the common memory containing a control algorithm, wherein the primary and secondary processing units are adapted to run the control algorithm; a functional compare module coupled to the primary, processing unit and the secondary processing unit for comparing a primary output of the primary processing unit and a secondary output of the secondary processing units after the control algorithm has been run by the primary and secondary processing units; and, at least one bus, wherein the common memory, primary and secondary processing units, and function compare module are coupled to the at least one bus, wherein the functional compare module is adapted to read signals on the at least one bus, generate a signature of the signals, compare the generated signature with a reference signal and detect a fault if the signals are not the same.