Patent ID: 6144583
Filing Date: 2000-11-07
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit device comprising:a first bit line;a first selection MISFET having one of a source and a drain region electrically connected to said first bit line;a second selection MISFET having one of a source and a drain region electrically connected to said first bit line;a second bit line electrically connected to another of said source and said drain region of said first selection MISFET and electrically connected to another of said source and said drain region of said second selection MISFET; anda plurality of memory cells each arranged at points of intersection between said second bit line and one of a plurality of word lines,wherein said first selection MISFET has a gate insulating film thinner than a gate insulating film of said second selection MISFET,wherein, in a write operation, a first voltage supplied to a gate electrode of said second MISFET is higher than a second voltage supplied to a gate electrode of said first MISFET.