Patent ID: 7256628
Filing Date: 2007-08-14
Classification: G06F

Abstract:
1. A method for matching speeds of asynchronous operation between a local chip and a neighboring chip, the method comprising: deriving an internal frequency signal from an internal oscillator on the local chip; receiving an external frequency signal from a neighboring chip; comparing the internal frequency signal with the external frequency signal to generate a control signal; and adjusting the operating speed of the local chip by applying the control signal to the internal oscillator; wherein if the internal frequency signal is faster than the external frequency signal, the control signal causes the internal frequency signal to slow down; wherein the neighboring chip similarly adjusts the external frequency signal with respect to the internal frequency signal so that the local chip and the neighboring chip operate at a substantially maximum common frequency; wherein the local chip and the neighboring chip are coupled together in an asynchronous control loop, which determines the substantially maximum common frequency without reference to an external synchronous clock signal; wherein comparing the internal frequency signal with the external frequency signal involves applying the internal frequency signal to a first edge detector circuit which is used to gate a first current source; wherein comparing the internal frequency signal with the external frequency signal involves applying the external frequency signal to a second edge detector circuit which is used to gate a second current source; and wherein an integrating capacitor and an offset current source are used to ensure that the frequency signal with the higher maximum frequency will operate at just above the maximum frequency of the frequency signal with the lower maximum frequency.