Patent ID: 7439979
Filing Date: 2008-10-21
Classification: G06T

Abstract:
1. A shader, for processing rasterized pixel data, comprising: a plurality of programmable shader pipelines, each programmable shader pipeline including a texture unit; a scheduler operatively coupled to each programmable shader pipeline in said plurality of programmable shader pipelines; a fully associative cache memory operatively coupled to said scheduler and each of the plurality of programmable shader pipelines and configured to store programming instructions, wherein the scheduler is configured to: retrieve a second VLIW stored in the cache memory for configuring the first programmable shader pipeline, if there are programming instructions stored in the cache memory for configuring the first programmable shader pipeline, and convert the programming instructions into the second VLIW; and transmit the first or second VLIW from the cache memory to one or more of the programmable shader pipelines in addition to the first pipeline; and a gatekeeper associated with each of the programmable shader pipelines and cooperating with the scheduler to transmit a VLIW to the associated programmable shader pipeline followed by a segment to be processed by the associated programmable shader pipeline, whereby the same VLIW is used by one or more programmable shader pipelines to simultaneously process the segment and a different VLIW is simultaneously used by a different one of the programmable shader pipelines to process a different segment.