Patent ID: 6144542
Filing Date: 2000-11-07
Classification: H01L

Abstract:
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), wherein said apparatus comprises:a plurality of internal circuits, each of said internal circuits having an input pad and an output pad, input signals being input to said plurality of internal circuits from said input pads and output signals being output from said plurality of internal circuits from said output pad, each of said plurality of internal circuits being coupled with a first power line and a second power line;a plurality of first ESD bi-directional connection devices;a plurality of second ESD bi-directional connection devices;a first ESD bus coupled with said plurality of first ESD bi-directional connection devices;a second ESD bus coupled with said plurality of second ESD bi-directional connection devices; andan ESD clamp device, coupled with said first ESD bus and said second ESD bus for discharging a current caused by said plurality of internal circuits through said plurality of first ESD bi-directional connection device to said first ESD bus, through said plurality of second ESD bi-directional connection to said second ESD bus.