Patent ID: 7054705
Filing Date: 2006-05-30
Classification: H01L

Abstract:
1. A semiconductor device manufacturing method comprising the steps of: manufacturing wafers in a manufacturing line using predetermined manufacturing processed, each of said wafers having a plurality of semiconductor chips provided therein in a grid-like arrangement; testing said plurality of semiconductor chips for electric characteristics thereof; writing into each of said plurality of semiconductor chips, information of a chip position on said wafer associated with said testing; storing a first test result from said testing step and storing said chip position information that is associated with said first test result; dividing said wafer into respective ones of said semiconductor chips to produce semiconductor devices each sealed in a package; testing each of said semiconductor devices for its electric characteristics to produce second test results; detecting stored position information of each of said semiconductor devices associated with said second test results after said semiconductor device has been sealed in a package; storing said second test results and said associated information of said semiconductor device position; and mapping the distribution of failures corresponding to a wafer by combining position information of those chips determined to be faulty in said semiconductor chip testing step and position information of those semiconductor devices determined to be faulty in said semiconductor devices testing step, based on said first test result, said second test result and said information of chip position and semiconductor device position; determining a cause of failures based on said distribution of failures.