Patent ID: 7222286
Filing Date: 2007-05-22
Classification: H03M

Abstract:
1. A decoding apparatus comprising: a turbo decoder which decodes an input signal in a predetermined first fashion and outputs a decoded result; an RS decoder which further decodes the decoded result in a predetermined second fashion, and outputs a completion signal if an error correction is completed by the RS decoder; a controller which controls the turbo decoder to iterate the decoding of the input signal as many times as a predetermined iteration number, to cease the decoding of the input signal if the RS decoder outputs the completion signal, and to adjust the predetermined iteration number as needed after the first iteration, wherein the controller further sets the iteration number to be greater than the predefined maximum value if a predetermined memory has storage capacity available to receive input data corresponding to the input signal to the turbo decoder, and sets the iteration number to be greater than the predefined maximum value if another predetermined memory does not have storage capacity available to store the RS-decoded signal.