Patent ID: 7378290
Filing Date: 2008-05-27
Classification: G01R

Abstract:
1. A method of making an isolation circuit, comprising: forming a first probe pad in one or more scribe lines of a wafer, the first probe pad adapted to receive a control signal from a probe of a test system; forming a second probe pad in the one or more scribe lines of the wafer and coupled to each of a plurality of microelectronic dice on the wafer, the second probe pad adapted to receive a test signal from another probe of the test system; forming a third pad coupled to a component formed in a first microelectronic die of the plurality of microelectronic dice on the wafer; and forming a device in the one or more scribe lines of the wafer, the device coupled to the first probe pad, the second probe pad, and the third pad, the device adapted to selectively transfer the test signal from the second probe pad individually to only the third pad coupled to the component formed in the first microelectronic die in response to the device receiving the control signal from the first probe pad.