Patent ID: 6160734
Filing Date: 2000-12-12
Classification: G06F,G11C

Abstract:
An integrated circuit comprising:program memory;a security register for storing a section boundary address corresponding to a boundary between first and second portions of said program memory;a programmable processor, coupled to said program memory, for executing instructions stored in the first portion of said program memory, and instructions stored in the second portion of said program memory, the instructions including accesses to the program memory at an address corresponding to the contents of a data pointer;a program counter, for storing a program memory address corresponding to an instruction being executed by the programmable processor; andsecurity logic, coupled to the programmable processor and the security register, and comprising boundary logic for disabling execution of an instruction responsive to the contents of the data pointer indicating a memory address in one of the portions of the program memory in combination with the program memory address corresponding to an address in another one of the portions of the program memory.