Patent ID: 6247086
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A PCI bridge chip configured to communicate command data and large burst data between a primary PCI bus and a secondary PCI bus, comprising:primary command transaction logic comprising a plurality of primary buffers and configured to receive the command data and buffer the command data in the plurality of primary buffers for selective application of command data transactions on the secondary PCI bus;large burst data logic configured to receive the large burst data and buffer the large burst data for access by the primary PCI bus and the secondary PCI bus; anda primary interface configured to receive the command data and the large burst data from the primary PCI bus, route the command data to the primary command transaction logic based on a first PCI address associated with the command data, and route the large burst data to the large burst data logic based on a second PCI address associated with the large burst data.