Patent ID: 6563365
Filing Date: 2003-05-13
Classification: G06G

Abstract:
A method of reducing noise in a four-quadrant multiplier having first and second cross-coupled pairs of differential transistors, differential input current terminals connected with a first pair of common junctions of the respective pairs of differential transistors and differential output current terminals cross coupled to form a second pair of common junctions of the respective pairs of differential transistors, the method comprising:providing a noise current path from the differential input current terminals to a bias voltage, said noise current path substantially bypassing the differential output current terminals when the gain of the multiplier is substantially zero; said transistors being bipolar transistors and said first pair of common junctions are common emitter junctions and said second pair of common junctions are common collector junctions, wherein said providing is of a third pair of transistors having respective emitters connected to the common emitter junctions of the respective pairs of differential transistors, common collectors connected to a bias voltage without intervening elements, and common bases connected to a control voltage.