Patent ID: 8453098
Filing Date: 2013-05-28
Classification: G01R

Abstract:
1. A method for reducing leakage currents in a circuit, comprising: providing a plurality of scan chain flip-flops coupled to circuit elements of the circuit, the scan chain flip-flops each comprising an input that alternatively configures the scan chain flip-flops in a first mode in which one or more test vectors may be loaded into the flip-flops and a second mode in which a stored vector may be loaded into the flip-flops; determining, while the flip-flops are in the first mode, one test vector having first states which if applied to the circuit elements of said circuit results in lower leakage currents than the leakage currents of second states, the vector determined based on heuristic data associated with the circuit; setting the one test vector to be the stored vector; detecting an operating mode of said circuit; and clocking, while the flip-flops are in the second mode, said stored vector into scan chain elements of said circuit for application thereby to said circuit elements when said operating mode is detected.