Patent ID: 7081783
Filing Date: 2006-07-25
Classification: G06F,H03K,H03L

Abstract:
1. A multiphase clock generating apparatus comprising: a multiplexer selecting one of a generated dock and a gated generated clock as an M-clock in accordance with a halt multiplexer control, wherein the M-clock has a frequency M times that of a reference clock; divider circuitry coupled to provide an alignment signal having a frequency 1/M that of the M-clock; a recovery circuit for recovering up to M distinct clocks from the M-clock in accordance with the alignment signal, wherein the recovered clocks have substantially a 180°/M phase difference from each other; and a halt circuit controlling the halt multiplexer control to select the gated generated clock when a selected recovered clock matches a pre-determined clock level, wherein the halt multiplexer control is clocked by the generated clock.