Patent ID: 9111619
Filing Date: 2015-08-18
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a common bit line; a first cell string being connected to the common bit line, the first cell string including a first selecting transistor, a second selecting transistor and first cell transistors; and a second cell string being connected to the common bit line, the second cell string including a third selecting transistor, a fourth selecting transistor and second cell transistors, wherein the first and third selecting transistors are electrically connected to a first selecting line, wherein the second and fourth selecting transistors are electrically connected to a second selecting line, wherein one of the first to fourth selecting transistors has a depletion mode, and the others of the first to fourth selecting transistors have an enhancement mode, wherein the first cell transistors are connected to the second selecting transistor in series and the second cell transistors are connected to the fourth selecting transistor in series, wherein each of the first and second cell transistors includes a charge storage layer, and wherein the second and fourth selecting transistors have the same integrated structure as the first and second cell transistors.