Patent ID: 6477552
Filing Date: 2002-11-05
Classification: G06F

Abstract:
A device for performing a consecutive clear bits count on an operand with an offset, the device comprising:a plurality of logic circuits, each associated with a prioritized portion of the operand, and each for activating an all-zero signal when its respective portion of the operand consists of all zeros, for performing a leading zero count on its respective portion of the operand, and for generating a leading zero signal by offsetting its leading zero count with a first portion of the offset; a priority encoder coupled to the logic circuits for generating a signal encoding the priority of the highest priority inactive all-zero signal; circuitry coupled to the priority encoder for selecting first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal; and circuitry coupled to the priority encoder and the selecting circuitry for generating a no-carryout signal by offsetting the priority encoded signal with a second portion of the offset, for generating a carryout signal by offsetting the priority encoded signal with the second portion of the offset and adding one, and for selecting one of the no-carryout and carryout signals as a second portion of the consecutive clear bits count in accordance with the carryout selector signal.