Patent ID: 6404249
Filing Date: 2002-06-11
Classification: H03L,Y10S

Abstract:
A phase-locked loop circuit comprising:an oscillator which outputs a pulse signal; and a frequency divider for frequency-dividing said pulse signal, said frequency divider having a dividing factor switching circuit which switches a dividing factor before a phase of said pulse signal is locked to that of a reference clock signal, said dividing factor switching circuit including a first input signal that is a modulation frequency signal used in determining a frequency of a waveform, a second input signal that is a modulation scaling signal to determine a frequency range for said waveform, wherein a control signal for switching said dividing factor is determined in accordance with said first input signal and said second input signal, and wherein said dividing factor switching circuit periodically switches dividing factors using said modulation frequency signal and said modulation scaling signal to prevent a phase of said pulse signal from being locked, said dividing factor switching circuit further comprising: a multiplexer which selects one dividing factor from among two or more dividing factors supplied thereto; a control signal generating circuit which generates said control signal for controlling an order of dividing-factor selection in said multiplexer association with a frequency of said reference clock signal; and a counter which generates an output signal upon receiving a member of pulses of said pulse signal from said oscillator, the number corresponding to the dividing factor selected by said multiplexer.