Patent ID: 6661701
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A three-transistor DRAM cell, comprising:a memory transistor for dynamically storing information; a write transistor connected for writing information to said memory transistor; and a read transistor connected for reading information from said memory transistor; said memory transistor being a field-effect transistor having a substrate area, a first insulating layer above said substrate area, a gate layer above said insulating layer formed with a short-channel section and a long-channel section, a second insulating layer and a conductive layer; and said second insulating layer formed directly on said gate layer; and said conductive layer formed on said second insulating layer; said conductive layer connected to a potential and said substrate area connected to a potential such that a potential difference between the potential on said conductive layer and the potential on said substrate area is substantially constant.