Patent ID: 7050520
Filing Date: 2006-05-23
Classification: H03L

Abstract:
1. A Phase locked loop (PLL) circuit comprising: a phase comparator for detecting a phase difference between a synchronizing source signal and a comparison signal; a selector for, when the detected phase difference is higher than a first lower limit, selecting the detected phase difference and, when the phase difference is not higher than the first lower limit, selecting the first lower limit; a control voltage generator for generating a control voltage based on the phase difference selected by the selector; a voltage-controlled oscillator (VCO) for outputting an output clock signal having a frequency which is proportional to the control voltage; and a comparison signal generator for outputting to the phase comparator the comparison signal based on the output clock signal, to change a phase of the comparison signal so that when the detected phase difference is not higher than a second lower limit lower than the first lower limit, the detected phase difference will become the first lower limit.