Patent ID: 7643576
Filing Date: 2010-01-05
Classification: H03K,H04L

Abstract:
1. A data signal recovery circuit in a receiver, comprising: a data signal conditioner configured to alter a parameter of an input data signal; a first sampling flip-flop configured to receive the conditioned data signal and, in response to a sample clock signal, configured to generate a recovered digital signal having a first level if the conditioned data signal is above a first threshold provided by the first threshold circuit and having a second level if the conditioned data signal is below the first threshold; a second sampling flip-flop comprising a second threshold circuit, the second sampling flip-flop being configured to receive the conditioned data signal, and, in response to the sample clock signal, being configured to generate a test digital signal having a third level if the conditioned data signal is above a second threshold provided by the second threshold circuit and having a fourth level if the conditioned data signal is below the second threshold; and a controller coupled to the data signal conditioner and to the first and second sampling flip-flops and configured to monitor the parameter of the data signal and to control the altering of the parameter in response to the recovered digital signal and test digital signal; wherein the first threshold circuit is integrated into and forms a portion of the first sampling flip-flop and the second threshold circuit is integrated into and forms a portion of the second sampling flip-flop such that delays and phase shifts occurring between the first threshold circuit and the first flip-flop, and between the second threshold circuit and the second flip-flop, are minimized, and such that the data signal recovery signal circuit can operate in the receiver at high weed with little or no delay, little or no phase shifts, and low amplitude distortion.