Patent ID: 6503828
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A process for selectively polishing, on an integrated circuit structure containing one or more openings in a layer of dielectric material, a main electrically conductive layer of said integrated circuit structure and a diffusion barrier layer lining lying adjacent to said layer of dielectric material, wherein said diffusion barrier layer lining and said main electrically conductive layer fill said one or more openings such that said depressed regions of said main electrically conductive layer overlie said one or more openings, said process comprising the steps of:(a) using a photoresist mask and etching process, forming, over depressed regions of said main electrically conductive layer, a polishing barrier layer selected from the group consisting of silicon carbide, silicon nitride, silicon oxynitride, tantalum, tantalum nitride, titanium, and titanium nitride; (b) polishing the portion of said main electrically conductive layer not covered by said polishing barrier layer; and (c) then, in a second polishing step, removing portions of said diffusion barrier layer overlying the upper surface of said dielectric layer.