Patent ID: 8421790
Filing Date: 2013-04-16
Classification: G09G

Abstract:
1. A driving circuit, adapted for a liquid crystal display, wherein the liquid crystal display has memory in pixel, the driving circuit comprising: a least significant bit (LSB) static random access memory (SRAM) array, including a plurality of word lines and a plurality of bit lines respectively disposed along a first axis direction and a second axis direction, wherein along the first axis direction, the LSB SRAM array further comprises a plurality of first common voltage lines, electrically connected to a common voltage, interlacing and disposing with the word lines, wherein when the number of the word lines reach a first amount, a first N-well pick-up power connecting line and a P-well pick-up power connecting line are disposed, and the P-well pick-up power connecting line is electrically connected to the common voltage; and wherein along the second axis direction, the LSB SRAM array further comprises a plurality of bit bar lines and a plurality of first power voltage lines, wherein the bit lines, the first power voltage lines, and the bit bar lines are disposed in turn of the bit line, the first power voltage line, the bit bar line, the bit bar line, the first power voltage line, the bit line along the second axis direction of the LSB SRAM, and a second common voltage line is disposed when the number of the bit lines reach a second amount; a pad, electrically connected to a power voltage; a power transistor, comprising a gate terminal, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is coupled to the pad, the gate terminal receives a standby signal, and the second source/drain terminal is coupled to the first N-well pick-up power connecting lines and the first power voltage lines; and a most significant bit (MSB) static random access memory (SRAM) array, comprising a plurality of second N-well pick-up power connecting lines and a plurality of second power voltage lines, wherein the second N-well pick-up power connecting lines and the second power voltage lines are respectively coupled to the power voltage, wherein the MSB SRAM array and the LSB SRAM share the word lines, the first common voltage lines and the P-well pick-up power connecting lines; wherein when the standby signal enables, the power transistor is cut off the electrical connection between the first source/drain terminal and the second source/drain terminal.