Patent ID: 6204184
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a memory mat region, comprising the steps of:forming a gate insulating film on an active region of a semiconductor substrate;depositing a gate electrode material film on said gate insulating film on said active region of said semiconductor substrate;depositing a polishing stopper film on said gate electrode material film;forming a plurality of gate electrodes by patterning a laminated film of said gate electrode material film and said polishing stopper film;forming source-drain regions on both sides of each said gate electrode in said active region;forming side wall films on side surfaces of each said gate electrode;depositing an interlayer insulator so as to fill a space between said gate electrodes;partially removing said interlayer insulator from said memory mat region by etching; andchemically mechanically polishing said interlayer insulator until said polishing stopper film is exposed.