Patent ID: 7767546
Filing Date: 2010-08-03
Classification: H01L

Abstract:
1. A method of forming a semiconductor wafer structure for integrated circuit devices, the method comprising: forming a first substrate portion having a first bulk substrate, a sacrificial layer formed on the first bulk substrate, a semiconductor layer formed on the sacrificial layer, a first insulating layer formed on the semiconductor layer, and an electrically conductive layer formed over the first insulating layer; patterning the electrically conductive layer so as to form shallow trench isolation (STI) regions therein; forming a second insulating layer, suitable for bonding to another insulating layer, on the electrically conductive layer; forming a second substrate portion having a second bulk substrate and a third insulating layer formed on the second bulk substrate; bonding the second substrate portion to the first substrate portion so as to define a bonding interface between the second and third insulating layers; separating the resulting bonded structure at a location within the first bulk substrate or the sacrificial layer and removing any remaining portion of the first bulk substrate; and removing any remaining portion of the sacrificial layer so as to define a double buried insulator back gate semiconductor-on-insulator wafer structure, wherein the first insulator layer comprises an upper insulating layer, the bonded second and third insulator layers together comprise a lower insulating layer, the semiconductor layer comprises a semiconductor-on-insulator layer, the patterned electrically conducting layer comprises dielectrically isolated back gate regions, and the second bulk substrate comprises a bulk substrate of the double buried insulator back gate semiconductor-on-insulator wafer structure.