Patent ID: 6191991
Filing Date: 2001-02-20
Classification: G11C

Abstract:
A data rate converter, wherein input data received in series synchronously with an input clock signal having a stream of clock pulses is converted into parallel data per given bits so as to be written into a memory, and the written parallel data is read from the memory per said given bits and converted into serial data synchronously with an output clock signal having a stream of clock pulses so as to be outputted, said data rate converter comprising:first counting means for counting the clock pulses of said input clock signal to output an input count value;write control means for producing a write enable signal based on said input count value for writing the parallel data into said memory per said given bits;read starting means for producing a ready signal based on said input count value for allowing the start of reading the parallel data from said memory, said ready signal having a pulse width greater than two periods of said output clock signal;read control means, responsive to said ready signal, for producing a trigger signal upon detection of a leading or trailing edge of a second or subsequent occurrence of said output clock signal within said pulse width of the ready signal;second counting means, responsive to said trigger signal, for counting the clock pulses of said output clock signal to output an output count value; andread signal generating means for producing a read signal based on said output count value for reading the parallel data from said memory per said given bits.