Patent ID: 8352096
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. A semiconductor data processing device comprising: a plurality of central processing units; an internal bus for coupling the central processing units; a plurality of resource units sharable by the central processing units via the internal bus; and a plurality of access management circuits for managing access from the central processing units to the resource units, wherein each of the access management circuits performs permission/inhibition control for access from the central processing units to the resource units according to a setting state of a domain setup register, and wherein, among the resource units, specific resource units selectively recognized by the access management circuits as sharable resources to be accessed from the central processing units include: a priority control register for which a write of priority control data is enabled by a predetermined one of the central processing units; and a plurality of control circuits for performing priority access permission control whereunder access from one of the central processing units that is identified by priority control data written in the priority control register is given higher priority than access from the other central processing units.