Patent ID: 8947924
Filing Date: 2015-02-03
Classification: G11C

Abstract:
1. A data readout circuit of phase change memory, wherein said phase change memory comprises one or more phase change memory cells and each phase change memory cell is connected to the control circuit by bit line and word line; characterized in that said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line of said memory cells under the control of said clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep said bit line at clamped state under the control of said clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on said clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the clamped current operated by said clamped current operation circuit and a reference current and output a readout result; said clamp voltage generating circuit comprises a current source, a first nMOS transistor connected in the form of a diode, and a second nMOS transistor connected in series to the first nMOS transistor, wherein the drain of the first nMOS transistor is connected to the current output terminal of said current source, the gate of the first nMOS transistor is connected to the gate of the second nMOS transistor, the source of the first nMOS transistor is connected to the drain of the second nMOS transistor, and the source of the second nMOS transistor is connected to the ground.