Patent ID: 6052802
Filing Date: 2000-04-18
Classification: G06F

Abstract:
A performance monitor for use in parallel to a main processor pipeline, said pipeline providing a plurality of delay reason signals comprising:at least two silos, each to receive one of a plurality of delay reason signals provided by the pipeline, said at least two silos including:a first silo to receive a first delay reason signal which is one of said plurality of delay reason signals and to output a first staged signal; anda second silo to receive a second delay reason signal which is another one of said plurality of delay reason signals and to output a second staged signal;a prioritizer, coupled to said first silo and said second silo, to receive said first and second staged signals and to output a plurality of prioritized signals; anda combiner, coupled to said prioritizer to receive said plurality of prioritized signals and to output at least one combined signal.