Patent ID: 6110767
Filing Date: 2000-08-29
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing an active area in a semiconductor substrate separated from other active areas by isolation regions;forming a dielectric layer on the surface of said semiconductor substrate in said active area;depositing a polysilicon layer overlying said dielectric layer and patterning said polysilicon layer;forming a mask over a portion of said polysilicon layer in said active area; andimplanting ions into said polysilicon layer not covered by said mask to form implanted regions within said polysilicon layer and simultaneously form implanted regions within said semiconductor substrate adjacent to said polysilicon layer wherein said implanted regions within said polysilicon layer form source and drain regions and wherein said polysilicon layer covered by said mask forms a channel region and wherein said implanted regions within said substrate diffuse together to form a gate electrode underlying said channel region.