Patent ID: 6781196
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A trench DMOS transistor structure that includes a plurality of individual trench DMOS transistor cells formed on a substrate of a first conductivity type, each of said individual trench DMOS transistor cells comprising:a body region on the substrate, said body region having a second conductivity type; at least one trench extending through the body region and the substrate; an insulating layer that lines the trench; a conductive electrode in the trench overlying the insulating layer; a source region of the first conductivity type in the body region adjacent to the trench; a plurality of polysilicon contacts respectively connected to transistor cells located along the periphery of the structure; and a polysilicon trench guard ring coupling together said plurality of polysilicon contacts, wherein said trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees, and wherein the sidewalls comprise at least a first pair of parallel sidewalls and a second pair of parallel sidewalls, the first pair of parallel sidewalls lying in a first plane, and the second pair of parallel sidewalls lying in a second plane, the first and second planes at right angles to each another, wherein the first pair of parallel sidewalls and the second pair of parallel sidewalls do not directly contact one another.