Patent ID: 7750705
Filing Date: 2010-07-06
Classification: H03K

Abstract:
1. An interface circuit including a high-voltage terminal and a low-voltage terminal forming a pair of power source terminals and an external input terminal, the interface circuit stabilizing a logic level of the external input terminal at an H or L level potential, and the interface circuit comprising: a first inverter circuit that is configured with a transistor to invert the logic level of an input signal given to the external input terminal and output a logic level that is obtained by inverting the logic level of the input signal; a second inverter circuit that is configured with a transistor to generate an output signal having a potential in which the logic level outputted from the first inverter circuit is inverted, wherein the output signal is generated so that the potential of the output signal is always higher or always lower than a potential of the external input terminal when no input signal is applied to the external input terminal or the external input terminal is in a virtually open state; and a feedback path through which the output signal of the second inverter circuit is positive-feedbacked to the external input terminal.