Patent ID: 7184322
Filing Date: 2007-02-27
Classification: G11C

Abstract:
1. A semiconductor memory device for receiving an address signal of (n+m) bits and making access to a memory cell array, n and m being predetermined positive integers, wherein said semiconductor memory device comprises: n common terminals shared between a part or all of address terminals for receiving the n bits of the address signal and data terminals for outputting a data signal with a bit width thereof being n bits or less; m dedicated address terminals for receiving the m bits of the address signal, wherein at a time of a read, after the n bits of the address signal have been input from said common terminals, a plurality of data signals within a page are consecutively read out through said common terminals, based on the m bits of the address signal input from said dedicated address terminals; a control circuit for receiving a control signal indicating that the address signal supplied to said semiconductor memory device from an outside of said semiconductor memory device is valid and generating a latch timing signal responsive to the control signal; a latch circuit for sampling the address signal input from said common terminals based on the latch timing signal and supplying the sampled address signal to a decoder for decoding the address signal; and a multiplexer circuit for receiving the plurality of data signals within the page read out from said memory cell array in parallel and performing control so that the plurality of data signals are multiplexed into a stream of data signals and sequentially output from said common terminals based on the m bits of the address signal input from said dedicated address terminal, at the time of the read.