Patent ID: 7486702
Filing Date: 2009-02-03
Classification: G11C

Abstract:
1. A system comprising: a transmit side having a double-data rate (DDR) interface adapted to transfer data on both the rising and falling edges of a source clock signal, with data signals transferred on N single-ended data lines and a source clock signal transferred on a single-ended clock line, with the transmit side including: a Tx phase-shifting block having N clock signal outputs, with the Tx phase-shifting block adapted to receive a 2× clock signal having double the frequency of the source clock signal, adapted to generate a plurality of phase-shifted Tx clock signals, with each phase-shifted Tx clock signal output by a corresponding clock signal output, and with successive phase-shifted Tx clock signals shifted in time by a different multiple of Δt relative to the received 2× clock signal; a plurality of N output signal switching blocks, each coupled to a corresponding one of the N single-ended data lines and directly coupled to a clock signal output of the Tx phase-shifting block, adapted to receive a phase-shifted Tx clock signal output by the directly coupled clock signal output as a phase-shifted data-out Tx clock signal, where each output signal switching block is adapted to switch a single-ended phase-shifted DDR data signal onto the corresponding data line in synchronism with a coupled phase-shifted data-out Tx clock signal with switching of successive single-ended phase-shifted DDR data signals shifted in time by a different multiple of Δt relative to the 2× clock signal; and a clock signal switching block, coupled to the Tx phase-shifting block and adapted to receive a single-ended phase-shifted Tx clock signal as a phase-shifted Tx clock signal, adapted to switch a single-ended Tx source clock signal onto the source clock line in synchronism with a received phase-shifted Tx clock signal; a receive side, having a DDR interface, comprising: a plurality of N input sampling blocks, each coupled to a corresponding one of the N single-ended signal lines, each sampling block adapted to sample a single-ended phase-shifted data signal from the corresponding data line in synchronism with a coupled compensated Rx clock signal; and an Rx dynamic adjustment circuit, coupled to the N input sampling blocks, adapted to receive the single-ended phase-shifted Tx source clock signal and to generate a plurality of compensated Rx clock signals adjusted in phase to compensate for phase shifts introduced into corresponding single-ended phase-shifted DDR data signals at the transmit side, and adapted to couple a compensated Rx clock signal to each input latch to sample a corresponding single-ended phase-shifted DDR data signal.