Patent ID: 8498141
Filing Date: 2013-07-30
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array including memory cells, the memory cells each including a variable resistance element and disposed between a plurality of first wirings and a plurality of second wirings, respectively; a column decoder configured to select any one of the first wirings; a row decoder configured to select any one of the second wirings; a control circuit configured to provide selected one of the first wirings with a first voltage and provide selected one of the second wirings with a second voltage having a lower voltage value than the first voltage so as to apply a certain potential difference to a selected memory cell disposed between one of the first wirings selected by the column decoder and one of the second wirings selected by the row decoder, and a current limitation circuit configured to control a cell current flowing through the selected memory cell not to exceed a first current, the current limitation circuit comprising: a first current generation circuit configured to store a cell current at a first point of time as a stored current and generating a first current having a current value of a times the current value of the stored current; a second current generation circuit configured to generate a second current having a current value of (β/α)(α>β) times the current value of a cell current at a second point of time after the first point of time; and a determination circuit for outputting a control signal when it is determined that the current value of the second current exceeds the current value of the stored current, the first current generation circuit newly storing a stored current at a timing according to the control signal.