Patent ID: 6236236
Filing Date: 2001-05-22
Classification: H03K

Abstract:
An apparatus including a buffer circuit for communicating signals between an internal circuit having a low power supply voltage and an external circuit having a power supply voltage above that of said internal circuit, comprising:a P-well control circuit configured to receive a P-well control signal and an external signal, and in accordance therewith selectively generate a P-well voltage; anda plurality of NMOS transistors, coupled to said P-well control circuit, at least one of said plurality of NMOS transistors having a bulk region configured to receive said P-well voltage;wherein said plurality of NMOS transistors is further configured to receive said external signal having a first potential, and in accordance therewith to selectively generate an internal signal having a second potential less than said first potential, andwherein said plurality of NMOS transistors is still further configured to receive said external signal having a third potential, and in accordance therewith to selectively generate said internal signal having said second potential, wherein said third potential is between said first potential and said second potential.