Patent ID: 6396323
Filing Date: 2002-05-28
Classification: G06F,G11C,H03L

Abstract:
A semiconductor integrated circuit device comprising:first latches; second latches; a clock generator receiving a reference clock signal and outputting a first clock signal; a phase adjusting circuit outputting a second clock signal; first clock distribution lines distributing the first clock signal to said first latches, said clock generator and said phase adjusting circuit so that the first clock signals distributed to said first latches, said clock generator and said phase adjusting circuit have identical phases; and second clock distribution lines distributing the second clock signal to said second latches and said phase adjusting circuit so that the second clock signals distributed to said second latches and said phase adjusting circuit have identical phases; wherein said clock generator adjusts a phase of the first clock signal so that the reference clock signal and the first clock signal distributed via said first clock distribution lines have identical phases, and wherein said phase adjusting circuit adjusts a phase of the second clock signal so that the first clock signal distributed via said first clock distribution lines and the second clock signal distributed via said second clock distribution lines have identical phases.