Patent ID: 8580675
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps of: providing a semiconductor substrate; forming a first dielectric layer over said substrate; forming a first interconnect pattern over said first dielectric layer, said first interconnect pattern including first exposed areas for metal interconnects in a first plurality of parallel route tracks, said first interconnect pattern including a first lead pattern in a first route track of said first plurality of parallel route tracks; performing a first trench etch process to form a first plurality of trenches; after forming said first interconnect pattern and performing said first trench etch process, forming a second interconnect pattern over said first dielectric layer, said second interconnect pattern including second exposed areas for metal interconnects in a second plurality of parallel route tracks, in which said second plurality of route tracks are alternated with said first plurality of route tracks, said second interconnect pattern including a second lead pattern in a second route track of said second plurality of parallel route tracks, such that said first route track is immediately adjacent to said second route track; performing a second trench etch process to form a second plurality of trenches; forming metal interconnect lines in said first plurality of trenches and said second plurality of trenches, such that a first lead is formed in an area defined by the first lead pattern and a second lead is formed in an area defined by said second lead pattern; forming a stretch crossconnect in exactly one of a second dielectric layer disposed above said metal interconnect lines and a third dielectric layer disposed below said metal interconnect lines, so that said stretch crossconnect is electrically connected to said first lead and said second lead, and such that said stretch crossconnect is free of electrical connection to other interconnect elements other than said first lead and said second lead; and forming other vertical interconnect elements in said integrated circuit concurrently with said stretch crossconnect.