Patent ID: 6654938
Filing Date: 2003-11-25
Classification: G06F

Abstract:
A delay characteristic analyzing method comprising:reading a net list that indicates an arrangement of and a connection between transistors and circuit elements equivalent to transistors; dividing a circuit to be analyzed, which is indicated by the net list, into unit cells each being a minimum of which can operate as a logic circuit; forming a plurality of circuit blocks by coupling together said unit cells according to a predetermined condition and the connection that is indicated by the net list; performing a dynamic timing analysis on each of said circuit blocks by performing an electrical circuit simulation under a condition of inputting a combination of proper input signals to the circuit blocks; generating a delay characteristic library including delay characteristics of said circuit blocks, based on results of said electrical circuit simulations on each of the circuit blocks; and performing a transmission delay analysis on a desired signal path by performing a static timing analysis based on said delay characteristic library by considering the circuit to be analyzed, which is indicated by the net list, and to be structured by the circuit blocks.