Patent ID: 8883622
Filing Date: 2014-11-11
Classification: G11C,H01L

Abstract:
1. A method of fabricating a semiconductor memory device, the method comprising: preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region and which comprises a lower layer where a cell array lower signal line and buried contact are formed in the cell array region; forming an insulation layer on the lower layer; forming a core and peripheral upper signal line which is electrically connected to the cell array lower signal line via a contact plug formed through the insulation layer of the core and peripheral region; forming and patterning a capping insulation film on the insulation layer to form sidewall spacers around the upper signal lines; and forming and patterning a stopper layer to cover upper signal lines and spacers and to stop etching above lower signal lines and allow etching to open buried contacts in the cell region.