Patent ID: 6436761
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method for manufacturing semiconductor memory devices having a memory-cell selecting transistor and a capacitive element, which is connected to one operating region of the memory-cell selecting transistor, comprising:forming the memory-cell selecting transistor on the semiconductor substrate; forming a first inter-layer insulator film having at least one contact hole with a conductive plug and covering the memory-cell selecting transistor and the semiconductor substrate; forming a second inter-layer insulator film having a contact hole overlying the at least one contact hole with a conductive plug of the first inter-layer insulator film; forming a lower electrode of the capacitive element that is electrically connected to the one operating region of the memory-cell selecting transistor, wherein a process of forming the lower electrode includes: forming a first amorphous silicon film in the contact hole of the second inter-layer insulator film; forming a second amorphous silicon film containing microcrystal above the first amorphous silicon film, to form a hemispherical grain (HSG) by using as a nucleus the microcrystal contained in the second amorphous silicon film; diffusing an impurity into the HSG; removing a surface layer of the HSG; and removing a chemical oxide film formed on a HSG surface; forming a capacitive insulator film of the capacitive element above the lower electrode; and forming an upper electrode of the capacitive element above the capacitive insulator film.