Patent ID: 6158029
Filing Date: 2000-12-05
Classification: G11C

Abstract:
A method of testing an integrated circuit having a memory, an external terminal, and a test circuit connected to the memory through data lines, address lines, and control lines, which comprises:providing a switching device with inputs, outputs, and a control input for causing the switching device to switch through;connecting at least one of the control lines to the switching device such that a signal impressed on the at least one of the control lines during a testing operation is received at an input of the switching device and cannot be transferred to an output of the switching device until the switching device switches through;connecting the control input to an external terminal of the integrated circuit;testing the memory with the test circuit by impressing with the test circuit appropriate test signals on the data lines, address lines, and control lines; andduring the testing step, influencing a signal characteristic on the corresponding control line, and a resultant timing of the test, through the external terminal of the circuit.