Patent ID: 6346444
Filing Date: 2002-02-12
Classification: H01L

Abstract:
A method of fabricating a power semiconductor device, comprising:(a) forming a collector region of a first conductivity type in a semiconductor substrate; (b) forming a first insulative film for exposing a region of the semiconductor substrate in which a base region is to be formed, on the semiconductor substrate in which the collector region is formed; (c) forming a base region of a second conductivity type formed in the collector region and simultaneously forming a second insulative film on an entire principal surface of the semiconductor substrate; (d) exposing a region of the semiconductor substrate in which an emitter region and a channel stop are to be formed; (e) forming an emitter region of the first conductivity type and a channel stop region by implanting impurities into the semiconductor substrate, and simultaneously forming a third insulative film on the entire principal surface of the semiconductor substrate; (f) etching the insulative films by a predetermined thickness; (g) forming an SIPOS film and a nitride film on the principal surface of the semiconductor substrate, and exposing parts of the base region, emitter region and channel stop region; and (h) forming a base electrode, an emitter electrode, and an equipotential electrode connected respectively to the base region, the emitter region, and the channel stop region.