Patent ID: 6378109
Filing Date: 2002-04-23
Classification: G06F

Abstract:
A method for designing an integrated circuit which contains a plurality of signal lines in close proximity, such that capacitive coupling among the signal lines is operable to induce crosstalk on at least one of the signal lines, wherein parasitics are extracted from a trial layout of the integrated circuit, the method comprising the steps of:grouping the plurality of signal lines into a plurality of aggressor groups; pruning the plurality of signal lines to form a plurality of victim signal lines; building a minimum region network for each victim signal line of the plurality of victim signal lines comprising the respective victim signal line, aggressor signal lines associated with the respective victim signal line, and associated parasitics; simulating the operation of each minimum region network to determine an amount of noise induced on each respective victim signal line by the aggressor signal lines associated with the respective victim signal line; and analyzing the simulation results of each minimum region network to determine if a gate oxide integrity (GOI) violation exists.