Patent ID: 6304958
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A microcomputer comprising:a central processing unit including an address generating unit;a first memory and a second memory adapted to be individually fed with a common address from said address generating unit;a first execution unit coupled to said first memory and said second memory; anda second execution unit coupled to said first memory and said second memory and mounted together with said central processing unit, said first memory, said second memory and said first execution unit on a common semiconductor substrate,wherein said microcomputer is provided with:a first operating mode, in which data are fed from one of said first and second memories to said first execution unit and in which said first execution unit executes the operations whereas said second execution unit interrupts the operations; anda second operating mode, in which the data are fed from said first memory to said first execution unit and fed from said second memory to said second execution unit and in which said first execution unit and said second execution unit execute the operations.