Patent ID: 7206954
Filing Date: 2007-04-17
Classification: G06F,Y02D

Abstract:
1. An embedded processor system, comprising: at least one gated power unit; said at least one gated power unit including an embedded non-volatile memory array; a power controller, receiving power via a system power signal, that provides at least one gated power signal to selectively provide power to said at least one gated power unit; isolation circuitry coupled to at least one input and to at least one output of each of said at least one gated power unit that is operative to minimize current flow into each of said at least one gated power unit when powered down, wherein said isolation circuitry comprises: an input clamp circuit that selectively clamps said at least one input when said at least one gated power unit is powered down; and an output isolation circuit that selectively isolates said at least one output when said at least one gated power unit is powered down.