Patent ID: 6728810
Filing Date: 2004-04-27
Classification: G06F,H04L

Abstract:
A data processing apparatus comprising:an internal bus for which a band-guaranteed cycle, in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time, and an asynchronous transfer cycle for executing a transfer cycle in a period other than the reserved band in accordance with a bus access request from a bus master, are defined as transfer modes; a plurality of devices connected to the internal bus and capable of transmitting/receiving data by using the band-guaranteed cycle or the asynchronous transfer cycle; and a controller configured to execute at least the band-guaranteed cycle for each cycle time, the controller being capable of inserting the asynchronous transfer cycle in the reserved band cycle in the band-guaranteed cycle while the band-guaranteed cycle is being executed on the internal bus, wherein the controller is capable of executing a stream access in the asynchronous transfer cycle by designating a same channel number as that of the reserved band cycle.