Patent ID: 7902029
Filing Date: 2011-03-08
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: forming a first material stack having edge boundaries aligned with boundaries of an underlying semiconductor structure; filling a region beyond the edge boundaries of the first material stack with an insulating field material; forming a second material stack having edge boundaries that determine an edge of a gate conductor of the transistor; removing a portion of the first material stack where the first material stack is not covered by the second material stack; forming a recess in the underlying semiconductor structure, self-aligned to exposed edges of the first material stack; depositing a source/drain metal within the recess in the underlying semiconductor structure; removing at least some of the insulating field material, leaving an opening, subsequently filling the opening with an insulating material to a height beyond the height of the first material stack, and planarizing the insulating material using chemo-mechanical polishing to the height aligned to that the first material stack so as to leave an insulator in a field region of the transistor to a height aligned to that of the first material stack.