Patent ID: 7187530
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. An ESD protection circuit, comprising: a first line to carry a supply signal; a second line to carry another supply signal different from that of the first line; a gateable channel disposed between the first and second lines, the gateable channel comprising a N channel MOSFET having its channel disposed between the first and the second lines, and a gate to receive a voltage bias to affect a conductivity of the channel; a first filter of a low-pass frequency response of given cut-off frequency to receive a signal of the first line and to filter the signal to establish a first output signal; a second filter of a high-pass frequency response of a corner frequency greater than the given cut-off frequency for the low-pass frequency of the first filter, the second filter to receive and filter the signal of the first line to establish a second output signal; and logic circuitry to enable the gateable channel based on the first output signal and the second output signal; wherein the first and the second filters of the respective high-pass and the low-pass frequency responses in combination with the logic circuitry to distinguish different slew-rate transients operable to wherein the logic circuitry comprises: