Patent ID: 9093455
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A method of fabricating an interconnect structure on a wafer, the method comprising: providing a dielectric layer on the wafer, the dielectric layer having a recess therein; depositing a silicon (Si) layer in the recess; forming an interconnect by providing a barrier layer and a conductive layer in the recess over the Si layer, wherein the Si layer has a density that substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure; planarizing the interconnect structure to cause portions of the Si layer, the barrier layer, and the conductive layer to be coplanar with a top surface of the dielectric layer; forming a nitride layer in a first portion of the Si layer that is adjacent to the top surface; and forming an oxide layer in a second portion of the Si layer that is adjacent to the first portion.