Patent ID: 6313672
Filing Date: 2001-11-06
Classification: H03K

Abstract:
An integrated circuit buffer comprising:a first driver circuit for sourcing current to an input/output node, the first driver circuit being coupled to a VDD voltage source;a second driver circuit for sinking current from the input/output node, the second driver circuit being coupled to a VSS voltage source;a first pre-driver circuit configured for providing a first pre-driver control signal to the first driver circuit, the first pre-driver circuit being coupled to the VDD and VSS voltage sources; anda second pre-driver circuit configured for providing a second pre-driver control signal to the second driver circuit, the second pre-driver circuit being coupled to the VDD and VSS voltage sources;wherein the first pre-driver circuit comprises:a pull-up circuit comprising a plurality of PMOS transistors coupled in parallel, the transistors having their source nodes coupled to the VDD voltage source and their control nodes configured to receive at least a first input signal;a PMOS switch transistor coupled between the pull-up circuit and a signal node, and having a control node;a biasing circuit comprising a PMOS first biasing transistor coupled between the control node of the PMOS switch transistor and the input voltage source, a control node of the PMOS first biasing transistor being coupled to the VDD voltage source; anda pull-down circuit comprising a plurality of NMOS transistors coupled in series between the input voltage source and the VSS voltage source;wherein the biasing circuit responds to an input voltage from the input voltage source such that when an input voltage from the input voltage source exceeds the VDD voltage by a threshold voltage, the biasing circuit causes the switch transistor to decouple the pull-up circuit from the signal node.