Patent ID: 7716404
Filing Date: 2010-05-11
Classification: G06F,H04L

Abstract:
1. A system comprising: a master, the master including a first processor, a first logic circuit connected to the first processor, a first buffer memory accessible by the first processor and the first logic circuit, and a first transceiver device connected to the first logic circuit, wherein the first transceiver device is adapted for connecting to a communication link, wherein the first processor is operable to store into the first buffer memory first data to be transferred over the communication link, and to retrieve from the first buffer memory second data received over the communication link, wherein the first logic circuit is operable, without intervention of the first processor, to transmit the first data in the first buffer memory over the communication link using the first transceiver device, and to receive the second data over the communication link using the first transceiver device and store it in the first buffer memory, wherein the first logic circuit is operable to transmit initial requests over the communication link, to receive acknowledgements over the communication link, and to transmit either acknowledgements alone or acknowledgements with at least a portion of the first data from the first buffer memory over the communication link in response to the received acknowledgements, wherein the initial requests transmitted by the first logic circuit includes a first request indicating that data is being transmitted with the request and a second request indicating that no data is being transmitted with the request, wherein the first logic circuit determines whether the first buffer memory contains the first data to be transferred over the communication link, and transmits either the first request with at least a portion of the first the data or the second request based on the determination, wherein the acknowledgements transmitted by the first logic circuit includes a first acknowledgement which indicates that the first logic circuit successfully received a last transmission over the communication link and that data is being transmitted with the acknowledgement, a second acknowledgement which indicates that the first logic circuit successfully received a last transmission over the communication link and that no data is being transmitted with the acknowledgement, a first negative acknowledgement which indicates that the first logic circuit failed to successfully receive a last transmission over the communication link and that data is being transmitted with the acknowledgement, and a second negative acknowledgement which indicates that the first logic circuit failed to successfully receive a last transmission over the communication link and that no data is being transmitted with the acknowledgement, wherein the first logic circuit determines whether it successfully received a last transmission over the communication link and determines whether the first buffer memory contains the first data to be transferred over the communication link, and transmits one of the first acknowledgement, the second acknowledgement, the first negative acknowledgement and the second negative acknowledgement based on the determinations, and wherein the first logic circuit transmits at least a portion of the first data in the first buffer memory following the first acknowledgement and the first negative acknowledgement.