Patent ID: 6104647
Filing Date: 2000-08-15
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory mats, each having a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells;a plurality of bit line selection lines, each provided for respective ones of the plurality of bit lines of said plurality of memory mats;a spare bit line selection line provided for the spare bit lines of said plurality of memory mats; anda redundancy circuit having an output node coupled to said spare bit line selection line and input nodes to which a first information indicating one of said plurality of bit line selection lines and a second information indicating one of said plurality of memory mats are supplied,wherein said redundancy circuit includes a comparing circuit having first input nodes coupled to the input nodes of said redundancy circuit, programmable elements, and a first output node coupled to the output node of said redundancy circuit,wherein one of said plurality of memory mats is selected and one of said plurality of word lines of the selected memory mat is activated at a memory access, andwherein the programmable elements can be programmed for one of a first defect mode and a second defect mode, the first defect mode being associated with a defect in one of said plurality memory mats and the programmable elements can be programmed so as to activate said spare bit line selection line depending on an access of the corresponding one of said plurality of memory mats, and the second defect mode being associated with a defect related to one of said plurality of bit line selection lines and the programmable elements can be programmed so as to activate said spare bit line selection line for an access of any one of said plurality of memory mats.