Patent ID: 6189093
Filing Date: 2001-02-13
Classification: G06F

Abstract:
In a microprocessor configured to execute instructions, a method of initiating an exception routine in response to a memory access exception caused by a speculative load instruction for loading a register of a plurality of registers with data from the memory, the method comprising:generating exception information responsive to the memory access exception;storing the exception information within the register, the register configured to store either data from the memory or exception information and an exception bit;setting the exception bit of the register to indicate that the register contains exception information;receiving and decoding an instruction for operating on the data stored in the register;checking the register to determine whether the register contains exception information or valid data from the memory, in response to receiving and decoding the instruction, by accessing the register bit of the register, and;initiating the exception routine if the register contains exception information, or executing the instruction if the register contains the valid data from the memory.