Patent ID: 8650383
Filing Date: 2014-02-11
Classification: G06F

Abstract:
1. A method for executing a vector instruction in a processor, comprising: receiving an input vector and optionally receiving a predicate vector, wherein each vector includes N elements; determining a key element position, wherein, if the predicate vector is received, the key element position is the rightmost active element of the input vector where a corresponding element of the predicate vector is active, otherwise, the key element position is the rightmost active element of the input vector; generating a result vector, wherein generating the result vector comprises: if the predicate vector is received, for each element in the result vector for which a corresponding element of the predicate vector is active, otherwise, for each element of the result vector, setting each element of the result vector to the right of the key element to a first predetermined value and setting each element of the result vector at or to the left of the key element to a second predetermined value; and setting one or more processor status flags to indicate positions in the result vector that are set to the first predetermined value.