Patent ID: 7285838
Filing Date: 2007-10-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first gate insulating film formed in a high-voltage transistor forming region of a semiconductor substrate; a second gate insulating film formed in a low-voltage transistor forming region of the semiconductor substrate; first and second gate electrodes which are formed on the second gate insulating film mutually at an interval and into which an impurity having a different conductivity type is introduced respectively; third and fourth gate electrodes which are formed on the first gate insulating film mutually at an interval, an impurity being introduced in an all portion of the third and fourth gate electrodes; first and second source/drain extensions of first conductivity type formed on the semiconductor substrate beside the first and third gate electrodes respectively; third and fourth source/drain extensions of second conductivity type formed on the semiconductor substrate beside the second and fourth gate electrodes respectively; first and second conductivity type source/drain regions for low-voltage formed on the semiconductor substrate at a distance from side surfaces of the first and second gate electrodes with a first interval respectively; first or second conductivity type source/drain regions for high-voltage formed on the semiconductor substrate at a distance from side surfaces of the third or fourth gate electrodes with a second interval that is wider than the first interval, respectively; first and second insulating sidewalls formed respectively beside the first and second gate electrodes; a third insulating sidewall extending from an edge of an upper surface of the third gate electrode to the first conductivity type source/drain extension beside the third gate electrode; and a fourth insulating sidewall extending from an edge of an upper surface of the forth gate electrode to the second conductivity type source/drain extension beside the fourth gate electrode.