Patent ID: 7470968
Filing Date: 2008-12-30
Classification: G01R

Abstract:
1. A capacitance-compensated integrated circuit package to facilitate test of a device under test (DUT), comprising: a substrate, a semiconductor circuit layer configured over said substrate to form a signal driver and at least one comparator wherein said driver and said comparator have an associated capacitance, a dielectric layer over said semiconductor circuit layer a conductive T-coil circuit arranged over said dielectric layer to form interleaved first and second inductors that join at a common node and respectively extend from said common node to terminate in respective first and second ends, and electrically conductive vias extending through said dielectric layer to connect said signal driver to said first end and connect said comparator to said common node; said second end thus provided to receive said DUT wherein said driver provides signals to said first end and said comparator compares responses at said common node to a threshold and said T-coil circuit at least partially compensates said capacitance.