Patent ID: 7964930
Filing Date: 2011-06-21
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a PN diode; a trench MOS barrier Schottky diode having a p region and an n region, together which form the PN diode; an n+ substrate; an n-layer disposed on the n+ substrate, the n+ substrate and the n-layer including contact layers, the contact layers separated from the n-layer in an area of walls of the trenches by an oxide layer; and trenches arranged in the n-layer, the trenches filled with a p region up to at most a portion of their depth, wherein the p regions are disposed in the bottom of the trenches in contact with the n-layer; wherein the PN diode is configured as a clamping element, and wherein a breakdown voltage of the PN diode is lower than breakdown voltages of the Schottky diode and a MOS structure.