Patent ID: 7275227
Filing Date: 2007-09-25
Classification: G03F

Abstract:
1. A method for checking optical proximity correction data, the method comprising: (a) dividing a chip region into at least first and second regions; (b) selecting the first region from the divided regions; (c) providing a first layout database of an integrated circuit design corresponding to the first region, wherein the first layout database is obtained before optical proximity correction treatment; (d) providing a second layout database of the integrated circuit design corresponding to the first region, wherein the second database is obtained after optical proximity correction treatment; (e) finding a location of a first structure in the first layout database; (f) simulating a resulting layout output for the first structure using the second layout database; (g) measuring a first critical dimension of the first structure from the resulting layout output for the first structure; (h) comparing the first critical dimension of the first structure to a drawn dimension of the first structure from the first database; (i) flagging the first structure in the second database if the first critical dimension is less than the first drawn dimension of the first database; (j) repeating the steps (a) to (i) to generate a defect report at least on the first and second regions; (k) analyzing the defect report to identify one or more problematic patterns; and (l) identifying unique patterns from the one or more problematic patterns.