Patent ID: 6784674
Filing Date: 2004-08-31
Classification: G01R

Abstract:
An apparatus for providing signal paths between an integrated circuit (IC) tester and a plurality of IC terminals so that a driver within the IC tester can concurrently transmit a test signal to the IC terminals, said test signal exhibiting high and low voltage levels representing logic states, wherein a fault at any one of the IC terminals conductively linking that IC terminal to a source of potential can drive that IC terminal near either of said high and low voltage levels, the apparatus comprising:a first signal path having a first characteristic impedance for conveying the test signal away from the driver; a plurality of probes, each for conveying the test signal to a separate one of the plurality of IC terminals; and a network comprising resistors for conveying the test signal from the first signal path to each of the probes, wherein the resistors isolate the IC terminals from one another by an amount of resistance that is substantially larger than the first characteristic impedance of the first signal path and sufficiently large to prevent the fault at any one of the IC terminals from affecting a logic state represented by the test signal at any other of the IC terminals.