Patent ID: 7206337
Filing Date: 2007-04-17
Classification: G11B,H04J,H04L

Abstract:
1. A high-speed serial bit stream interface that communicatively couples a line side media to a communication Application Specific Integrate Circuit (ASIC), the high-speed serial bit stream interface comprising: a line side interface that communicatively couples to the line side media, that receives an RX signal therefrom, and that transmits a TX signal thereto; a board side interface that communicatively couples to the communication ASIC, that receives the TX signal therefrom, and that transmits the RX signal thereto; an RX signal conditioning circuit communicatively coupled between an RX portion of the line side interface and an RX portion of the board side interface; a TX signal conditioning circuit communicatively coupled between a TX portion of the line side interface and a TX portion of the board side interface; wherein the RX signal conditioning circuit and the TX signal conditioning circuit each includes: wherein the output pre-emphasis circuit servicing the RX signal and the output pre-emphasis circuit servicing the TX signal are separately controlled to produce differing pre-compensation operations of the RX signal and for the TX signal.