Patent ID: 6710727
Filing Date: 2004-03-23
Classification: H03M

Abstract:
A correction system of Successive Approximation Analog-to-Digital Converter (SA-ADC), the converter being used for converting an analog signal to a digital data, the digital data being a series of logic numbers Di (i=1ËœN) and having the same M logic numbers (DNâˆ’M+1ËœDN,1&lE;Ma detection module for if the M logic numbers all are logic number [1], proceeding the digital data and a correction data with a first logic operation to generate a first detection digital data; and if the M logic numbers all are logic number [0], using the digital data to detect directly; a D/A converter for inputting the first detection digital data or the digital data, and correspondingly converting to a first detection signal or a second detection signal; and a comparator for using the first detection signal or the second detection signal as a reference signal of the comparison module to compare with the analog signal; wherein when the reference signal is the first detection signal, if the analog signal is higher than the first detection signal, the detection module outputs the first detection digital data to replace the digital data; and if the analog signal is lower than the first detection signal, the detection module outputs the digital data; and wherein when the reference signal is the second detection signal, if the analog signal is higher than the second detection signal, the detection module outputs the digital data; and if the analog signal is lower than the second detection signal, the detection module proceeds the digital data and the correction data with a second logic operation to output a second detection digital data to replace the digital data.