Patent ID: 9094238
Filing Date: 2015-07-28
Classification: H04L,H04W,Y02D

Abstract:
1. A first integrated circuit, comprising: a linear equalizer to receive a digital bit stream from a second integrated circuit over a signal path and to equalize the digital bit stream and generate an output; and a decision feedback equalizer having a tap, the tap driven based on a historical data value conveyed by the digital bit stream, the decision feedback equalizer to equalize the output; where the first integrated circuit has two equalization modes, including a first mode where the tap is used to equalize data received from the second integrated circuit, and a second mode where the tap is disabled and is not used to equalize the data received from the second integrated circuit; and where a selection between the first and the second modes is made based on a relative circuit power parameter between the first and the second modes and irrespective of characteristics of the signal path.