Patent ID: 8108571
Filing Date: 2012-01-31
Classification: G06F

Abstract:
1. A method for multithreaded communications with a direct memory access (DMA) controller, the method comprising: accepting a plurality of DMA command messages directed to a fixed port address, the plurality of DMA command messages comprising a first DMA command message and a second DMA command message, each DMA command message including a completion notification field, with a notification address embedded in the completion notification field, and a set of control descriptors (CDs), where the CDs are instruction sequences to be performed by a DMA completion engine; arranging the plurality of DMA command messages in a non-virtual first-in first-out (FIFO) queue, implemented as a fixed number plurality of parallel non-virtual FIFO sub-queues, each non-virtual FIFO sub-queue loading corresponding DMA command messages in an order in which they are received; storing a plurality of CD sets in a plurality of context memories, the plurality of CD sets comprising a first CD set and a second CD set, where each CD set is associated with a corresponding DMA command message, where each context memory is associated with a corresponding one of the fixed number plurality of parallel non-virtual FIFO sub-queues; fetching the first DMA command message from a first non-virtual FIFO sub-queue; storing the first set of CDs associated with the first DMA command message in a first context memory; fetching the second DMA command message from a second non-virtual FIFO sub-queue; storing the second set of CDs associated with the second DMA command message in a second context memory; loading a completion engine with the first and second CD sets, respectively from the first and the second context memories to initiate transactions with the first set of CDs and the second set of CDs; completing transactions with the second set of CDs prior to finishing transactions with the first set of CDs by the completion engine; and, sending a transfer complete message to the notification address embedded in the second DMA command message, indicating completion of a data transfer operation associated with the second set of CDs by the completion engine.