Patent ID: 7326997
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a first MOSFET device of a first type including a first gate conductor stack of first height over a first channel region, said first channel region under stress of a first type, wherein said first gate stack is overlain by a first stressing layer causing said stress of a first type; and a second MOSFET device of a second type including a second gate conductor stack over a second channel region, said second gate stack having a height less than said first height, and a second channel region under said second gate stack under stress of a second type, wherein said second gate stack is overlain by a second stressing layer causing a stress of a second type different than said stress of said first type, wherein said second stressing layer is delimited by at least one discontinuity in said second stressing layer adjacent said second gate conductor, said discontinuity separating said second stressing layer from said first stressing layer, and wherein said first stressing layer and said second stressing layer are non-overlapping and wherein said at least one discontinuity comprises an opening between said first stressing layer and said second stressing layer, said opening formed completely around the perimeter of said second gate stack.