Patent ID: 6757282
Filing Date: 2004-06-29
Classification: H04Q

Abstract:
A method of scheduling and controlling switching of data packets, each comprising a header portion and a payload portion, from an input source to an output destination, through a switch having a plurality of addressable input ports and a plurality of addressable output ports, the method comprising:scheduling on a time slot assignment basis, wherein a provided common time reference (CIR) is divided into a plurality of contiguous periodic super-cycles each comprised of at least one contiguous time cycle each comprised of at least one contiguous time frame each comprised of at least one contiguous time slot; providing a plurality of queues in a first memory wherein each of the plurality of queues is associated with a particular one of the output ports for each one of the plurality of input ports; wherein each time frame is associated with a respective one of the plurality of queues that are associated with a particular one of the output ports in said first memory; analyzing the header portion of a respective one of the data packets; selecting one of the plurality of queues as a selected queue for a particular one of the output ports responsive to the analyzing; storing the data packets in the selected queue; partitioning each of the data packets into data units, wherein each of the data units can be communicated from the input port to the output port within the duration of one of the time slots; storing information, in a second memory, defining coupling for a selected subset of the time slots, in each of the time frames in each of the time cycles, and in each of the super-cycles, of each of the respective data units from a respective one of the queues to a respective one of the output ports; and scheduling for each of the data units of each of the respective data packets, from the respective input port to the respective output port, responsive to at least one of retrieving a stored value from the second memory defining the time slot in which said data unit will be switched to the output port, and computing the time slot in which said data unit will be switched to the output port.