Patent ID: 8310059
Filing Date: 2012-11-13
Classification: H01L

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of IO (Input/Output) buffers arrayed in line; a plurality of pad coupling wirings respectively arrayed in correspondence with the IO buffers and set in a layer different from the layer of the IO buffers; and a plurality of IO buffer switching wirings respectively arrayed in line in correspondence with the IO buffers and the pad coupling wirings, set in a layer different from the layers of the IO buffers and the pad coupling wirings so that the IO buffer switching wirings overlap with part of their corresponding pad coupling wirings, and extended to one or more other pad coupling wirings set adjacently to the corresponding pad coupling wirings, wherein each of the IO buffer switching wirings is formed in an identical shape so that the IO buffer switching wiring is not short-circuited to adjacent other IO buffer switching wirings, and wherein each of the IO buffers is electrically coupled with its corresponding IO buffer switching wiring in an identical position.