Patent ID: 7442591
Filing Date: 2008-10-28
Classification: H01L

Abstract:
1. A method of forming a planar double gate device comprising: forming a first bottom gate stack on a semiconductor substrate in a first-type transistor region; forming a second bottom gate stack on the semiconductor substrate in a second-type transistor region; forming a channel layer from the semiconductor substrate; forming a first top gate stack on a top dielectric layer surface in one selected from a group consisting of the first-type transistor region and the second-type transistor region; forming a second top gate stack over the channel layer in the other of the first-type transistor region or second-type transistor region, different from the transistor region of the first top gate stack; patterning the first top gate stack and the second top gate stack to form a patterned first top gate stack and a patterned second top gate stack in respective ones of the first-type transistor region or the second-type transistor region; forming initial sidewall spacers on the patterned first top gate stack and on the patterned second top gate stack; patterning the channel layer (i) in a region corresponding to the region of the patterned first top gate stack, using the patterned first top gate stack with initial sidewall spacers as a mask to leave a patterned first channel layer and (ii) in a region corresponding to a region of the patterned second top gate stack, using the patterned second top gate stack with initial sidewall spacers as a mask to leave a patterned second channel layer; forming second sidewall spacers on (i) the patterned semiconductor channel layer and the patterned first top gate stack with initial sidewall spacers and (ii) the patterned semiconductor channel layer and the patterned second top gate stack with initial sidewall spacers; patterning (i) one of (a) a first bottom gate stack or (b) a second bottom gate stack in a region corresponding to the region of the patterned first top gate stack, using the patterned semiconductor channel layer with second sidewall spacers and the patterned first top gate stack with initial sidewall spacers as a mask and (ii) the other one of (a) the first bottom gate stack or (b) the second bottom gate stack in a region corresponding to the region of the patterned second top gate stack, using the patterned semiconductor channel layer with second sidewall spacers and the patterned second top gate stack with initial sidewall spacers as a mask; defining (i) a first bottom gate dimension in the first bottom gate stack in the first-type transistor region, wherein defining the bottom gate dimension in the first bottom gate stack corresponds to patterning the first bottom gate stack and (ii) a second bottom gate dimension in the second bottom gate stack in the second-type transistor region, wherein defining the second bottom gate dimension in the second bottom gate stack corresponds to patterning the second bottom gate stack; depositing a dielectric fill material into void regions proximate to the patterned first and second bottom gate stacks and the patterned first and second top gate stacks, wherein the void regions comprise voids created during the patterning of the first and second bottom gate stacks in respective first-type and second-type transistor regions; forming source/drain cavities in the dielectric fill material within filling the source/drain cavities within (i) the first-type transistor region with a first source/drain material and (ii) the second-type transistor region with a second source/drain material.