Patent ID: 6795372
Filing Date: 2004-09-21
Classification: G11C

Abstract:
A bit line sense amplifier driving control circuit for a synchronous dynamic random access memory having a memory cell array including at least two column blocks divided according to column address and having a plurality of bit line sense amplifiers to sense data that is output from the memory cell array to a bit line, the bit line sense amplifier driving control circuit comprising:a main control circuit which is responsive to a bit line sense amplifier sensing start signal and a predetermined row block information signal to output a main control signal that controls the sensing operation of the bit line sense amplifiers; a plurality of sub control circuits which are responsive to a plurality of column block information signals, including first and second column block information signals and a sensing-securing delay signal to output a plurality of sub control signals; a main driving circuit which drives the bit line sense amplifiers in response to the main control signal; and a plurality of sub driving circuits which drive the bit line sense amplifiers in response to the sub control signals.