Patent ID: 6166941
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A memory cell structure, comprising:a plurality of bit lines extending in substantially a parallel fashion relative to one another along a surface of an integrated circuit;a plurality of word lines, extending along the surface of the integrated circuit substantially perpendicularly to the plurality of bit lines;a plurality of storage nodes disposed along and in contact with an associated one of the plurality of bit lines in such a manner that two of the plurality of word lines are disposed between each pair of adjacent storage nodes along a common bit line; anda plurality of bit line contacts, disposed along associated ones of the plurality of bit lines in such a manner that two of the plurality of storage nodes are disposed between each pair of adjacent bit line contacts along a common bit line, each bit line contact for making contact between its associated bit line and an access transistor defined by one of the plurality of word lines and coupled to an associated storage node;wherein the storage nodes along each of the bit lines are shifted with respect to storage nodes along an adjacent bit line, so that each of the bit line contacts along each of the plurality of bit lines is substantially aligned with one of the plurality of storage nodes along an adjacent bit line.