Patent ID: 8281205
Filing Date: 2012-10-02
Classification: H03M

Abstract:
1. A decoding apparatus for decoding an LDPC (Low density parity check) code wherein said LDPC code is expressed by an original parity check matrix having a first structure obtained by combining a plurality of first configuration matrixes including a P×P unit matrix, a P×P semi unit matrix obtained by setting the value of each of one or more matrix elements of said P×P unit matrix from 1 to 0, a P×P shift matrix obtained as a result of carrying out a cyclic shift operation on said P×P unit matrix or said P×P semi unit matrix, a P×P sum matrix obtained by carrying out a matrix addition operation on at least two of said P×P unit matrix, said P×P semi unit matrix and said P×P shift matrix and a P×P zero matrix or expressed by a matrix obtained by rearranging at least one row and one column in said original parity check matrix as a matrix having said first structure where notation P denotes an integer, said decoding apparatus comprising: message computation means for carrying out a process of decoding received values each obtained as a result of receiving said LDPC code by concurrently performing F check-node processes or F variable-node processes, where notation F denotes a non-unity measure of said integer P, and outputting F messages obtained as a result of said F check-node processes or said F variable-node processes; shift means for carrying out F×F cyclic shift operations on said F messages generated by said message computation means and outputting F messages as a result of said F×F cyclic shift operations; storage means for storing said F messages generated by said shift means and allowing said stored F messages to be read out or storing F received values cited above and allowing said stored F received values to be read out; and control means for controlling an operation to supply a unit composed of said F received values corresponding to second configuration matrixes, which are included in a matrix having a second structure as second configuration matrixes derived from said first configuration matrixes, to said message computation means as an operation to supply said received values to said message computation means by carrying out at least a column rearrangement process or a process equivalent to said column rearrangement process on said received values expressed by said parity check matrix having said first structure where said second structure is a structure obtained by combining a plurality of said second configuration matrixes including an F×F unit matrix, an F×F semi unit matrix obtained by setting said value of each of one or more matrix elements of said F×F unit matrix from 1 to 0, an F×F shift matrix obtained as a result of carrying out a cyclic shift operation on said F×F unit matrix or said F×F semi unit matrix, an F×F sum matrix obtained by carrying out a matrix addition operation on at least two of said F×F unit matrix, said F×F semi unit matrix and said F×F shift matrix and an F×F zero matrix.