Patent ID: 7404041
Filing Date: 2008-07-22
Classification: G06F

Abstract:
1. A method for implementing a thread-level speculation system on a chip multiprocessor having multiple processing units and an associated cache memory hierarchy, wherein programming threads in speculative and non-speculative modes are assigned to said multiple processing units for parallel execution, said method comprising: providing an additional private local cache dedicated to a respective processing unit for use only in thread-level speculation mode, each said private local cache for storing speculative results and state associated with an executing thread; providing a dedicated bus interconnecting said dedicated private local caches for enabling data forwarding between parallel executing threads to detect data dependency conditions; receiving, at a processing unit, a thread identifier for executing a speculative or non-speculative programming thread; starting, at said processing unit, a current thread execution in response to receiving a thread identifier; implementing, at a processing unit, logic for performing: wherein said bus interconnected dedicated private local caches and implemented logic for tracking speculative access between multiple processing units enables coherent speculative multithreading without modification to a processing unit core.