Patent ID: 9147442
Filing Date: 2015-09-29
Classification: G06F,G11C,H01L

Abstract:
1. An electronic device comprising a semiconductor memory, the semiconductor memory including: a mat region configured to include a plurality of memory cells coupled with first wires; and a switching region configured to control coupling between the first wires and an external region in transfer of data stored in the memory cells, wherein the switching region includes: a substrate configured to include second active regions arranged in a first direction and extended in a second direction crossing the first direction; second gates extended in the first direction across the second active regions; second lower contacts disposed over the substrate on both sides of each second gate, each second lower contact configured to couple the second active regions arranged in the first direction; second upper contacts disposed over the second lower contacts, each second upper contact overlapping with a corresponding second active region on a first side of each second gate and overlapping with every second active regions on a second side of each second gate; second wires coupled with the second upper contacts on the first side of each second gate and the first wires and extended in the second direction; and third wires coupled with the second upper contacts on the second side of each second gate and an external region and extended in the second direction.