Patent ID: 6172773
Filing Date: 2001-01-09
Classification: H04N

Abstract:
An apparatus comprising:a memory device having locations corresponding to M rows and N columns of elements, said elements having a binary bit pattern of M rows and N columns comprising, said binary bit pattern first type bit elements and second type bit elements, with the type bit element with the greatest number of elements in said pattern array being a majority type element, and the type bit element of least number of elements in said pattern being a minority type element;means for iteratively selecting and moving said minority type elements and said majority type elements between element locations within said pattern memory device, said minority type elements selected in relation to neighboring minority type elements according to a first spatial characteristic, and said majority type elements selected in relation to neighboring minority type elements according to a second, different spatial characteristic, until said minority type elements and said majority type elements have been uniformly distributed to locations within said pattern memory device to provide a modified pattern of first and second type bit elements having homogeneous attributes; andmeans for providing a modified convolution result for each element of said pattern, including:multiplication means for multiplying the binary element value of said neighboring elements by a spatial domain function to generate a filter result; andsumming means for adding said filter result of each of said neighboring elements to produce said modified convolution result for said element.