Patent ID: 6528722
Filing Date: 2003-03-04
Classification: H01L,H05K

Abstract:
A BGA semiconductor package, which comprises:a base layer having an opening portion and formed with a plurality of holes about the opening portion, wherein the base layer has a first surface and a second opposed surface; a lead frame having a plurality of leads, wherein each of the leads has a lower surface and an upper opposed surface attached to the second surface of the base layer in a manner that, inner end portions of said leads extend to the opening portion of the base layer and the upper surface of each of the leads is connected to the corresponding hole in the base layer; a semiconductor chip attached to the lower surfaces of the leads; a plurality of bonding wires for electrically connecting the semiconductor chip and the inner end portions of the leads; an encapsulant for encapsulating the semiconductor chip, the bonding wires, and the leads, wherein the first surface of the base layer and a peripheral portion of the lower surface of each of the leads are exposed to the encapsulant; and a plurality of solder balls electrically connected to the upper surfaces of the leads through the holes in the base layer, in a manner that the solder balls are aligned in position with the exposed peripheral portions of the leads.