Patent ID: 6862247
Filing Date: 2005-03-01
Classification: G11C

Abstract:
1. A synchronous semiconductor memory device operating like a static memory, comprising: a plurality of dynamic memory cells arranged in rows and columns; signal input circuitry taking in an external operation control signal in synchronization with a basic clock signal, and producing an internal operation instructing signal; row select circuitry for selecting, when activated, a row of the memory cells in accordance with an external row address signal; column-related circuitry for selecting, when activated, a column of the memory cells in accordance with an external column address signal, and performing data access to a selected column; and control circuitry operating for activating and deactivating sequentially said row select circuitry and said column-related circuitry in a predetermined sequence in accordance with a first internal operation instructing signal provided from said signal-input circuitry, for inhibiting deactivation of said row select circuitry to maintain said row select circuitry in an active state in accordance with a second internal operation instructing signal provided from said signal input circuitry, and for deactivating said row select circuitry maintained in the active state in accordance with a third internal operation instructing signal provided from said signal input circuitry.