Patent ID: 6622287
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A method of optimizing a system for power usage, said system having a set of cores, with each of said set of cores having a plurality of functional units, comprising the steps of:calculating a utilization rate of each of said functional units and each of said cores, where the utilization rate of each of said functional units is defined as a number of clock cycles said functional unit is actually performing an operation in relationship to all clock cycles this functional unit is switched on, and the utilization rate of each of said cores is defined as the average utilization rate of all of said functional units; selecting cores from said set of cores that have a low utilization rate and dividing functions of those selected cores into partitioning objects; executing said partitioning objects and calculating utilization rates for said executed partitioning objects; comparing the utilization rates of the partitioning objects with the utilization rates of the selected cores from which the partitioning objects were extracted; synthesizing said partitioning objects for which the utilization rates of the partitioning objects is lower than the utilization rates of the selected cores from which the partitioning objects were extracted, where said synthesized partitioning objects represent new cores to be added to the system as small ASICs; and building said system using said new cores and some of said cores from said set of cores.