Patent ID: 6310911
Filing Date: 2001-10-30
Classification: H04J,H04L,H04Q

Abstract:
A method of detecting signal degradation conditions in synchronous digital signals, comprising the steps of:polling said synchronous digital signals to obtain a first set of sample parity error counts at predetermined intervals;integrating a set of sample parity error counts in a first bit error rate monitor over a predetermined number of samples to determine a first bit error rate;generating an output from said first bit error rate monitor when a first bit error rate condition is present;creating a subset of sample parity error counts from said first set of sample parity error counts by selecting samples from said first set at specific intervals;integrating said subset of sample parity counts over a predetermined number of samples of said subset in a second bit error rate monitor to determine a second bit error rate;generating an output from said second bit error rate monitor when a second bit error rate condition is present; andreacting to said outputs from said bit error rate monitors that said first or second bit error rate conditions are present to take a predetermined action that depends on the state of both the bit error rate monitors.