Patent ID: 8924817
Filing Date: 2014-12-30
Classification: G06F,H03M

Abstract:
1. A method, comprising: responsive to a change in a first subset of a plurality of data bits, calculating a first subset of a plurality of error correction code bits, wherein the plurality of error correction code bits represent an error correction code value for the entirety of the plurality of data bits, wherein the first subset of the plurality of error correction code bits is less than all of the plurality of error correction code bits, wherein the plurality of data bits comprises lines of a tag array associated with a cache memory, each line comprising at least one state bit and a plurality of address bits, and wherein calculating the first subset of the plurality of error correction code bits comprises modifying the first subset of the plurality of error correction code bits of a line of the tag array in response to a change in the at least one state bit of the line without modifying a second subset of the plurality of error correction code bits; responsive to a change in at least one data bit outside of the first subset of data bits, calculating the first and second subsets of the plurality of error correction code bits; and determining the error correction code value for the entirety of the plurality of data bits.