Patent ID: 6725353
Filing Date: 2004-04-20
Classification: G06F

Abstract:
An input/output register programming system that uses a set transmission value and is suitable for a system having a write address and an input command for inputting data and a plurality of input/output registers, comprising:an address decoder for decoding the write address to determine if the input command is an input/output register write command or a transmission setting (TS) register write command and issue an input/output register write enable signal or TS register write enable signal accordingly; a TS register for importing input data to become the set transmission value when the TS register write enable signal is true, wherein the set transmission value are used to represent the target region address of the input command, and the target region address is output when the TS register write enable signal is false; a partitioning device dividing the input data into an auxiliary address and a stored data when the TS register write enable signal is false; an internal address generator for combining the auxiliay address and the target region address to produce an internal address; and a transmission space for data storage, wherein the transmission space includes the input/output registers specified by the internal address.