Patent ID: 6376876
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A NAND-type flash memory device, comprising:a plurality of isolation layers formed at predetermined regions of a semiconductor substrate, the plurality of isolation layers running parallel with each other; a string selection line pattern and a ground selection line pattern crossing over active regions between the plurality of isolation layers, the string selection line pattern and the ground selection line pattern running parallel with each other; a plurality of word line patterns disposed between the string selection line pattern and the ground selection line pattern; source regions formed at the active regions adjacent to the ground selection line patterns, the source regions being located opposite the string selection line pattern; drain regions formed at the active regions adjacent to the string selection line patterns, the drain regions being located opposite the ground selection line pattern; and a common source line disposed on the source regions and the isolation layers between the source regions, the common source line running parallel with the ground selection line pattern, being electrically connected to the source regions, and being in direct contact with the isolation layers.