Patent ID: 6414873
Filing Date: 2002-07-02
Classification: G11C

Abstract:
A non-volatile, static random access memory (nvSRAM) with the ability to store multiple bits of data for each static random access memory cell comprising:a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining a bit of data, and transmitting a bit of data to the exterior environment; wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory; a non-volatile memory, operatively connected to said static random access memory, that includes a first non-volatile memory cell capable of being programmed with a differentially represented bit of data received from said static random access memory and a second nonvolatile memory cell that is also capable of being programmed with a differentially represented bit of data received from said static random access memory; wherein said first non-volatile memory cell is in series with said second non-volatile memory cell and located between said second non-volatile memory cell and said static random access memory; and a controller, operatively connected to said static random access memory and said nonvolatile memory, that is capable of causing said non-volatile memory to be programmed with a first differentially represented bit of data stored in said static random access memory at a first time and a second differentially represented bit of data stored in said static random access memory at a second time that is different than said first time.