Patent ID: 8207052
Filing Date: 2012-06-26
Classification: H01L

Abstract:
1. A method of fabrication an integrated circuit comprising: providing a substrate with a bond pad formed thereover, the bondpad having a top surface for the formation of bonding connections; providing a passivation layer over the bondpad; forming a masking layer over the passivation layer, the masking layer comprising photoresist; etching the passivation layer in accordance with the masking layer to form a patterned passivation layer with an opening that exposes a portion of the top surface of the bond pad; removing the masking layer to expose the passivation layer by a plasma strip process, wherein the plasma strip process comprises a fluorine-based chemistry for removing etching residues arising from the step of etching the passivation layer; cleaning the substrate after removing the masking layer by a wet solvent clean process to remove etching residues and residual fluorine; and forming a bond pad protective layer on the exposed top surface portion of the bond pad after the wet solvent clean process.