Patent ID: 8984245
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A memory protection unit for use in a system with multiple processing devices connected to a memory device, the memory protection unit being associated with one of the multiple processing devices such that the associated processing device can only access the memory device through the memory protection unit, the memory protection unit comprising: at least a first access control unit and a second access control unit, the first access control unit and the second access control unit being programmed for controlling access to the memory device by the associated processing device, each of the first access control unit and the second access control unit including programming that defines addresses of the memory device that are designated for access by the associated processing device, the first and the second access control unit each being configured to reject access to addresses of the memory device that are not designated for access by the associated processing device; wherein access to a particular address of the memory device by said associated processing device is approved if the first access control unit and the second access control unit approve the access and access is rejected if the first access control unit or the second access control unit rejects the access; wherein the first access control unit is configured to be programmed by the associated processing device alone; and wherein the second access control unit is configured to be programmed with the programming only after a reset, the second access control unit being programmable a single time and/or within a predefined time period after the reset, and wherein the programming of the second access control unit is readable by an additional processing device of the multiple processing devices other than the associated processing device for checking correctness of the programming of the second access control unit.