Patent ID: 9124417
Filing Date: 2015-09-01
Classification: H04L

Abstract:
1. An apparatus, comprising: a first pair of input keys on a first garbled gate input wire; a second pair of input keys on a second garbled gate input wire; and a computer readable non-transitory medium having instructions located thereon which when executed by a processor: receive a Pseudo-Random Function Generator (PRFG) circuit from a secure token configured to generate the PRFG circuit and to transmit the PRFG circuit from a first network device to a second network device, the PRFG circuit including a number of gate tables and wire encryptions, each gate for the number of garbled gates including a first key ki and a second key kj; and implement the PRFG circuit, the PRFG circuit being configured to generate a random permutation of four garbled table entries, each garbled table entry being formed by a single encryption operation applied to a corresponding output key, each single encryption operation including encrypting each corresponding output key with a key formed from an exclusive OR function (XOR) of one of the four possible combinations of one key of the first pair of input keys and one key of the second pair of input keys, wherein the encrypted output key for each garbled gate is selected from the domain of the PRFG circuit.