Patent ID: 6239626
Filing Date: 2001-05-29
Classification: G06F,H03L

Abstract:
A clock selector for selecting between a first and a second clock source, said first and second clock source being phase and frequency synchronous and having a period T.sub.cyc, said selector comprising:a multiplexer having a first input for receiving said first clock source, a second input for receiving said second clock source, a control input, and an output, said multiplexer coupling said first input to said output when said control input is inactive, and coupling said second input to said output when said control input is active, said coupling from input to output occurring within a time T.sub.mux after said control input changes value;a first synchronizer coupled to said first clock source and accepting as an input a first clock quality signal, and producing as output a synchronized first clock quality signal within a time T.sub.sync1 after the occurrence of an edge on said first clock source;a second synchronizer coupled to said second clock source and accepting as an input a second clock quality signal, and producing as output a synchronized second clock quality signal within a time T.sub.syn2 after the occurrence of an edge on said second clock source;an asynchronous state machine (ASM) having a first input, a second input, memory, and an output coupled to said memory, said output changing within a time T.sub.asm after application of said input,said ASM output coupled to said multiplexer control input,said ASM first input coupled to said first synchronizer output,said ASM second input coupled to said second synchronizer output,when said memory value is inactive, said memory value changes to active only when said first synchronizer output indicates said first clock quality is bad and said second synchronizer output indicates said second clock quality is good, said memory maintaining an inactive value at all other times,when said memory value is active, said memory value changes to inactive only when said first synchronizer output indicates said first clock quality is good and said second synchronizer output indicates said second clock quality is bad, said memory maintaining an active value at all other times.