Patent ID: 6263423
Filing Date: 2001-07-17
Classification: G06F

Abstract:
A computer system, comprising:a processor;a memory; anda bus connecting said processor and said memory,wherein said processor can translate a stream of non-native instructions to native instructions, said processor includinga hardware based instruction translator to convert said stream of non-native instructions into native instructions, wherein non-native instructions are converted into less than a predetermined number of native instructions;a latch to store at least two groups of said native instructions in at least two intermediate buffers, wherein said at least two intermediate buffers can each store up to said predetermined number of native instructions; anda selector to combine a subset of said at least two groups of said native instructions into a final buffer, so as to allow issuing of said subset of said native instructions of said final buffer in said processor, wherein said final buffer has a maximum capacity of said predetermined number of native instructions.