Patent ID: 9191006
Filing Date: 2015-11-17
Classification: H03K

Abstract:
1. A current-limited level shift circuit, comprising: a first PMOS transistor, a source of the first PMOS transistor connected to a first voltage level, a drain of the first PMOS transistor connected to a first output terminal; a second PMOS transistor, a source of the second PMOS transistor connected to the first voltage level, a drain of the second PMOS transistor connected to a second output terminal, wherein the first output terminal and the second output terminal are in pairs; a third PMOS transistor, a source of the third PMOS transistor connected to the drain of the first PMOS transistor, a drain of the third PMOS transistor connected to a third output terminal; a fourth PMOS transistor, a source of the fourth PMOS transistor connected to the drain of the second PMOS transistor, a drain of the fourth PMOS transistor connected to a fourth output terminal, wherein the third output terminal and the fourth output terminal are in pairs; a first current-limiting unit, a first terminal of the first current-limiting unit connected to the drain of the third PMOS transistor; a second current-limiting unit, a first terminal of the second current-limiting unit connected to the drain of the fourth PMOS transistor; a first NMOS transistor, a source of the first NMOS transistor connected to a second voltage level, a gate of the first NMOS transistor connected to a first input terminal, a drain of the first NMOS transistor connected to a fifth output terminal and a second terminal of the first current-limiting unit; and a second NMOS transistor, a source of the second NMOS transistor connected to the second voltage level, a gate of the second NMOS transistor connected to a second input terminal, a drain of the second NMOS transistor connected to a sixth output terminal and a second terminal of the second current-limiting unit, wherein the fifth output terminal and the sixth output terminal are in pairs; wherein a gate of the first PMOS transistor and a gate of the second PMOS transistor are respectively connected to the pair of the fourth output terminal and the third output terminal or the pair of the sixth output terminal and the fifth output terminal, a gate of the third PMOS transistor and a gate of the fourth PMOS transistor are respectively connected to the pair of the third output terminal and the fourth output terminal or the pair of the fifth output terminal and the sixth output terminal; wherein the pair of the first output terminal and the second output terminal, the pair of the third output terminal and the fourth terminal, and the pair of the fifth output terminal and the sixth output terminal are for selectively connecting to a second stage circuit.