Patent ID: 8081017
Filing Date: 2011-12-20
Classification: G06F,H03K

Abstract:
1. A clock signal frequency dividing circuit in which a frequency dividing ratio is defined as N/M being a ratio of two integers N and M, comprising: a clock selecting circuit for selecting only one of three situations: an input clock signal is output as has been inputted, the input clock signal is inverted and output, and the input clock signal is not output; and a control unit for generating a control signal to control the selection by the clock selecting circuit; wherein the control unit controls the selection by the clock selecting circuit at every cycle of the input clock signal, wherein the control unit includes: a unit for calculating the phase of an ideal frequency-divided clock signal in which the frequency dividing ratio is N/M and the cycle time is constant with respect to the input clock signal; a unit for judging whether to output the input clock signal as an output clock signal with reference to the calculation result by the unit for calculating the phase; and a unit for judging the phase being closer to the phase of the ideal frequency-divided clock signal, out of the phase of the output clock signal in the case of outputting the input clock signal and the phase of the output clock signal in the case of inverting and outputting the input clock signal, with reference to the calculation result by the unit for calculating the phase.