Patent ID: 6284657
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method for forming a dual-damascene type conducting interconnect within a microelectronics fabrication, comprising:providing a layered structure such as is used in a microelectronics fabrication, said structure comprising a conducting layer, on which has been formed a passivating layer, on which has been formed a first dielectric layer, on which has been formed an etch-stop layer, on which has been formed a second dielectric layer and on which has been formed a capping layer;patterning and etching a trench and via structure that passes through said capping layer, said second dielectric layer, said etch-stop layer and said first dielectric layer and extends, thereby, to said passivating layer;forming a non-metallic layer of fluorine diffusion resistant material over all surfaces of said trench and via formation such that said non-metallic layer conformally covers said surfaces;etching away portions of said non-metallic layer of fluorine diffusion resistant material to form a fluorine diffusion resistant barrier ""spacer"" over the side-walls of said trench and via formation;etching away the exposed portion of said passivation layer to expose the conducting layer;forming a metallic barrier layer over all surfaces of said trench and via formation such that said metallic barrier layer conformally covers said surfaces;depositing copper over all surfaces of said trench and via formation.