Patent ID: 6143593
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A method of fabricating on a wafer a semiconductor device having source and drain junctions, a well, a channel, a gate, and isolation zones wherein said isolation zones physically and electrically separate said wafer into at least one device area, said method comprising the following steps:a. forming a sacrificial gate structure above said device area;b. implanting junctions within said device area;c. forming a silicide on top of said junctions;d. depositing an insulating layer on top of said silicide wherein said insulating layer provides electrical and physical isolation between said silicide and said sacrificial gate structure;e. removing said sacrificial gate structure;f. implanting a well within said device area;g. annealing and electrically activating said well and said junctions;h. depositing a channel above said device area;i. depositing a gate insulator upon said channel;j. depositing a gate electrode upon said gate insulator; andk. planarizing the structure resulting from the implementation of steps a-k.