Patent ID: 8335909
Filing Date: 2012-12-18
Classification: G06F

Abstract:
1. A system comprising a plurality of interconnected nodes, each node comprising: a first motherboard; at least two first processors integrated onto the first motherboard and configured to communicate with each other via a direct link between them; and a first switch integrated onto the first motherboard, the first processors communicably coupled to the first switch, the first switch configured to communicably couple the first processors to at least six second motherboards that each comprise at least two second processors integrated onto the second motherboard and a second switch integrated onto the second motherboard configured to communicably couple the second processors to the first motherboard and at least five third motherboards that each comprise at least two third processors integrated onto the third motherboard and a third switch integrated onto the third motherboard; the first processors configured to communicate with particular second processors on a particular second motherboard via the first switch and the second switch on the particular second motherboard; the first processors configured to communicate with particular third processors on a particular third motherboard via the first switch, the second switch on an intermediate second motherboard between the first motherboard and the particular third motherboard, and the third switch on the particular third motherboard without communicating via either of the second processors on the intermediate second motherboard.