Patent ID: 8930956
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A method of utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer, the compute node comprising a kernel processing core and a plurality of parallel application processing cores, the kernel processing core comprising a plurality of kernel administration hardware threads, each application processing core comprising a plurality of hardware threads, wherein the plurality of kernel administration hardware threads and the plurality of hardware threads are implemented using identical hardware, the method comprising: assigning to the kernel administration hardware thread when the kernel administration hardware thread is not being utilized at a particular time, by a kernel executing on the kernel processing core, a memory space of a hardware thread of one of the application processing cores; in response to the assignment of the kernel administration hardware thread to the memory space of the hardware thread of one of the application processing cores, advancing, by the kernel administration hardware thread, the hardware thread to a next memory space associated with the hardware thread, wherein the advancing of the hardware thread to the next memory space is carried out by updating a register value such that the hardware thread does not execute within the assigned memory space and instead executes next instruction within the next memory space; and wherein the hardware thread of the one of the application processing cores is advanced without advancing code corresponding to an instruction that the one of the application processing cores is currently executing so that the hardware thread of the one of the application processing cores is not disrupted; and executing, by the kernel administration hardware thread, an instruction previously assigned to be executed by the hardware thread within the assigned memory space.