Patent ID: 6287922
Filing Date: 2001-09-11
Classification: H01L,Y10S

Abstract:
A method for manufacturing an MOS structure on a semiconductor substrate comprising:forming a gate oxide layer over the semiconductor substrate;forming a polysilicon layer over said gate oxide layer;forming a first mask layer over said polysilicon layer;patterning and etching said first mask layer to form a first gate mask;anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions in the semiconductor substrate under said first polysilicon gate;anisotropically etching said first polysilicon gate to form a second polysilicon gate using said first gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles; andremoving said first gate mask.