Patent ID: 7480015
Filing Date: 2009-01-20
Classification: G02F

Abstract:
1. A method for manufacturing an array substrate of a translucent LCD comprising the steps of: forming an ITO layer and a gate metal layer successively on a glass substrate, the pixel unit of the glass substrate being divided into a TFT region, a reflective region, and a transmissive region; performing a first mask process using half-tone exposure technology and an etching process to the gate metal layer and the ITO layer to form a gate line, a common electrode line, a plate-type counter electrode of ITO, and an embossing pattern, the gate line including a gate electrode, the counter electrode being positioned in the transmissive region, and the embossing pattern being positioned in the reflective region; forming a gate insulation layer, an amorphous silicon layer, and a doped amorphous silicon layer successively on a front surface of the glass substrate having the gate line including the gate electrode, the common electrode line, the counter electrode, and the embossing pattern formed thereon; performing a second mask process using half-tone exposure technology and an etching process to the doped amorphous silicon layer, the amorphous silicon layer, and the gate insulation layer to form a first via hole and an active pattern, the first via hole exposing the common electrode line, and the active pattern being positioned in the TFT region; forming a triple layer on the gate insulation layer including the first via hole and the active pattern by successively forming a bottom Mo layer, an Al layer, and a top Mo; performing a third mask process using half-tone exposure technology and an etching process to the triple layer to form a data line and a reflective electrode, the data line constituting a TFT and including a source/drain electrode configured as a triple layer having a bottom Mo layer, an Al layer, and a top Mo layer, and the reflective electrode being configured as a double layer having a bottom Mo layer and an Al layer and positioned in the reflective region; forming a protective layer on a front surface of a resultant having the source/drain electrode and the reflective electrode formed thereon; performing a fourth mask process and an etching process to the protective layer to form a second via hole exposing the source/drain electrode; forming an ITO layer on the protective layer including the second via hole; and performing a fifth mask process and an etching process to the ITO layer to form a slit-type pixel electrode positioned in both the transmissive and reflective regions while contacting the source/drain electrode.