Patent ID: 6261895
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A process for forming a three plated capacitor in a semiconductor device comprising the steps of:(a) forming a first insulating layer on the semiconductor device;(b) forming a trench defined by an interior surface in the insulating layer;(c) forming a first low resistance metal layer covering the interior surface of the trench;(d) forming a first polysilicon layer directly over and in contact with the first low resistance metal layer;(e) forming a first dielectric layer directly over and in contact with the first polysilicon layer;(f) forming a second polysilicon layer directly over and in contact with the first dielectric layer;(g) forming a second low resistance metal layer over the second polysilicon layer;(h) forming a third polysilicon layer directly over and in contact with the second low resistance metal layer;(i) forming a second dielectric layer directly over and in contact with the third polysilicon layer;(j) forming a fourth polysilicon layer directly over and in contact with the second dielectric layer;(k) forming a third low resistance metal layer over the fourth polysilicon layer until the trench is filled;(l) planarizing the semiconductor device wherein the first, second, and third low resistance metal layers are exposed above the trench; and(m) forming capacitor leads to the first, second, and third low resistance metal layers.