Patent ID: 7846834
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure comprising: providing an initial interconnect structure that includes a lower interconnect level comprising a first dielectric material having at least one conductive feature embedded therein, an upper interconnect level comprising a second dielectric material having at least one via opening that exposes a portion of said at least one conductive feature located atop said lower interconnect level, said lower and upper interconnect levels are separated in part by a dielectric capping layer, and a patterned hard mask on a surface of the said upper interconnect level and wherein sidewalls of said second dielectric material within said via are bare; forming a punch-through gouging feature in said at least one conductive feature that is located at the bottom of said via opening, wherein said sidewalls of said second dielectric material within said via remain bare during said forming the punch-through gouging feature; forming at least one line opening in said second dielectric material that extends above said at least one via opening; forming a single continuous diffusion barrier layer within said at least one line and via openings; and filling said at least one line opening and at least one via opening with a conductive material.