Patent ID: 6272603
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A method of maintaining cache coherency in a data processing system including a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect, said method comprising:in a first cache among said plurality of caches, storing a first data item in association with an address tag indicating an address of said first data item and setting a coherency indicator in said first cache to a first state that indicates that said address tag is valid and that said first data item is invalid in said first cache; andin response to said first cache receiving a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, said data transfer including a second data item that is modified with respect to a corresponding data item in said system memory, storing said second data item in said first cache in association with said address tag in place of said first data item and updating said coherency indicator to a second state indicating that said second data item is valid and modified with respect to said corresponding data item in system memory and that said first cache is responsible, among all of said plurality of caches, for writing back said second data item to said system memory.