Patent ID: 8187961
Filing Date: 2012-05-29
Classification: H01L,Y10S

Abstract:
1. A method for processing a CMOS structure, comprising: in a first type Field Effect Transistor (FET) device, implementing a first gate insulator comprising a first high-k dielectric, and fabricating a temporary liner; in said first type FET device, removing completely said temporary liner by etching; in said first type FET device, depositing a chemical oxide liner in place of said temporary liner with a first thickness of between about 0.2 nm and 1.2 nm; in a second type FET device, implementing a second gate insulator comprising a second high-k dielectric, and fabricating a second liner consisting essentially of oxide and having a second thickness, wherein said second thickness is selected to be at least three times larger than said first thickness; and exposing said first type FET device and said second type FET device to oxygen, wherein oxygen penetrates through said second liner reaching said second high-k dielectric of said second gate insulator, and causing a predetermined shift in the threshold voltage of said second type FET device, while due to said first thickness oxygen is substantially prevented from penetrating to said first high-k dielectric of said first gate insulator, whereby the threshold voltage of said first type FET device stays unchanged.