Patent ID: 6413821
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A method of fabricating a semiconductor device including a memory region including nonvolatile memory devices and a logic circuit region including a peripheral circuit for the nonvolatile memory devices, the method comprising the following steps in that order:a step of forming a first insulating layer over a semiconductor layer, a step of forming a first conductive layer over the first insulating layer, a step of forming a stopper layer over the first conductive layer, a step of removing the stopper layer in the logic circuit region, a step of patterning the first conductive layer in the logic circuit region, thereby forming gate electrodes of insulated gate field effect transistors in the logic circuit region, a step of forming sidewall insulating layers at least on both sides of the gate electrodes, a step of forming a protective insulating layer in the logic circuit region so as to cover at least the gate electrodes, a step of patterning the stopper layer and the first conductive layer in the memory region, a step of forming an ONO film over the entire surface of the memory region and the logic circuit region, a step of forming a second conductive layer over the ONO film, a step of anisotropically etching the second conductive layer, thereby forming control gates in the shape of sidewalls at least on both sides of the first conductive layer in the memory region with the ONO film interposed, a step of removing the protective insulating layer in the logic circuit region, a step of forming first impurity layers which form either a source region or a drain region of the nonvolatile memory devices and second impurity layers which form either a source region or a drain region of the insulated gate field effect transistors, a step of forming silicide layers on the surfaces of the first impurity layers, the second impurity layers and the gate electrodes, a step of forming a second insulating layer over the entire surface of the memory region and the logic circuit region, a step of polishing the second insulating layer so that the stopper layer is exposed in the memory region and the gate electrodes are not exposed in the logic circuit region, a step of removing the stopper layer in the memory region, and a step of patterning the first conductive layer in the memory region, thereby forming word gates of the nonvolatile memory devices in the memory region.