Patent ID: 9012995
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. An apparatus, comprising, comprising: a memory element having two terminals; a source line, extending in a first direction above the surface of a substrate; a pair of fins, extending in parallel in a second direction above the surface of the substrate, each of the fins being partially wrapped around by the source line; a local interconnect extending in the first direction above the surface of the substrate, contacting one terminal of the memory element, and partially wrapping around the pair of fine; a gate line extending in the first direction above the surface of the substrate, arranged between the source line and the local interconnect, and partially wrapping around the pair of the fins; and a bit line coupled to another terminal of the memory element, and extending in the second direction above the substrate, but not in contact with the source line and the gate line.