Patent ID: 6148004
Filing Date: 2000-11-14
Classification: H04L

Abstract:
A port module comprising:a plurality of link controllers, each of said link controllers coupled to one of a plurality of data ports;a plurality of buffer memories, each of said buffer memories coupled to one of said link controllers;a data channel; anda front end portion of said port module coupled to said data channel and operative in association with a matrix controller for identifying a start up exchange for a first of a plurality of data frames on said data channel, said front end portion directing said first of said plurality of data frames to a first portion of one of said plurality of buffer memories and directing all subsequent ones of said plurality of data frames to a second portion said one of said plurality of buffer memories, said one of said plurality of buffer memories being associated with one of said link controllers, and said one of said link controllers being associated with a selected one of said plurality of data ports as specified by said matrix controller.