Patent ID: 7849291
Filing Date: 2010-12-07
Classification: G06F,H04N,Y02D

Abstract:
1. A programmable processor comprising: an instruction path and a data path; a register file comprising a plurality of registers coupled to the data path; and an execution unit coupled to the instruction and data paths, that is operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis, dynamically partition data from an operand register in the plurality of registers into multiple data elements having the same elemental width such that a total aggregate width of the multiple data elements equals a width of the operand register; wherein the execution unit is capable of executing a first group operation that operates on data elements having a first elemental width and, immediately following execution of the first group operation, execute a second group operation that operates on data elements having a second elemental width twice as large as the first elemental width; and wherein the execution unit is also capable of executing both group integer arithmetic operations and group floating-point arithmetic operations, wherein for the group integer arithmetic operations multiple pairs of integer data elements from a pair of operand registers are operated on in parallel to produce a catenated result comprising a plurality of individual integer results and for the group floating-point arithmetic operations multiple pairs of floating-point data elements from a pair of operand registers are arithmetically operated on in parallel to produce a catenated result comprising a plurality of individual floating-point results.