Patent ID: 8363766
Filing Date: 2013-01-29
Classification: G06F,H04L

Abstract:
1. A method comprising: receiving a first input signal at a data input of a first synchronizer, the first input signal to be synchronized to a clock; receiving a second input signal at a data input of second synchronizer, the second input signal to be synchronized to the clock; preventing a transitioning third signal based upon preventing the clock from being received at a clock input of the first synchronizer and from being received at a clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having a same logic value as a second output signal at an output of the second synchronizer; asserting an enable signal in response to determining that the first input signal has changed logic state or that the second input signal has changed logic state, wherein the first input signal has changed logic state when the first input signal has a different logic value than the first output signal at the output of the first synchronizer, and the second input signal has changed logic state when the second input signal has a different logic value than the second output signal at the output of the second synchronizer, wherein the first output signal is based upon a value of the first input signal at a previous time and the second output signal is based upon a value of the second input signal at the previous time, and wherein the enable signal is asynchronous to the clock; and synchronizing the enable signal to the clock to generate a synchronized enable signal; wherein preventing includes preventing transitioning of the third signal based upon the synchronized enable signal.