Patent ID: 6470418
Filing Date: 2002-10-22
Classification: G06F,G11C

Abstract:
A content addressable memory (CAM) system comprising:a first CAM array configured to provide a first plurality of match control signals in response to an input data value during a first memory cycle; a first match detector configured to receive the first plurality of match control signals and assert a first hit control signal if any one of the first plurality of match control signals is asserted; a first priority encoder configured to receive the first plurality of match control signals and the first hit control signal, wherein the first priority encoder is only enabled to process the first plurality of match control signals if the first hit control signal is asserted; a second CAM array configured to provide a second plurality of match control signals in response to the input data value during a second memory cycle, only if the first hit control signal is not asserted during the first memory cycle, the first plurality of match control signals having a higher priority than the second plurality of match control signals; a second match detector configured to receive the second plurality of match control signals and assert a second hit control signal if any one of the second plurality of match control signals is asserted; and a second priority encoder configured to receive the second plurality of match control signals and the second hit control signal, wherein the second priority encoder is only enabled to process the second plurality of match control signals if the second hit control signal is asserted.