Patent ID: 6813331
Filing Date: 2004-11-02
Classification: G11C

Abstract:
A bi-directional shift-register circuit for outputting data in different turns according to a low-voltage clock signal, a first directional signal and a second directional signal, comprising:a first shift-register unit having a first-stage input terminal, a first-stage output terminal, and a first-stage clock input terminal for receiving the low-voltage clock signal; a second shift-register unit having a second-stage input terminal, a second-stage output terminal, and a second-stage clock input terminal for receiving the low-voltage clock signal; a third shift-register unit having a third-stage input terminal, a third-stage output terminal and a third-stage clock input terminal for receiving the low-voltage clock signal; a first bi-directional control circuit having a first input terminal coupled to the first-stage output terminal, a second input terminal coupled to the third-stage output terminal, and a first control terminal; the first bi-directional control circuit outputs a signal of the first-stage output terminal to the second-stage input terminal when the first control terminal receives the first directional signal and outputs a signal of the third-stage output terminal to the second-stage input terminal when the first control terminal receives the second directional signal; a first level shifter coupled to the first-stage output terminal to amplify the signal of the first-stage output terminal; a second level shifter coupled to the second-stage output terminal to amplify the signal of the second-stage output terminal; and a third level shifter coupled to the third-stage output terminal to amplify the signal of the third-stage output terminal; wherein the second shift-register unit outputs the signal of the second-stage output terminal to the third-stage input terminal when the second-stage input terminal receives the signal of the first-stage output terminal and the second shift-register unit outputs the signal of the second-stage output terminal to the first-stage input terminal when the second-stage input terminal receives the signal of the third-stage output terminal.