Patent ID: 7149950
Filing Date: 2006-12-12
Classification: G06F

Abstract:
1. A device, comprising: a memory array in which a plurality of codewords is stored, each codeword comprising an error correction code and a data block comprising a plurality of units of data; and an error code correction module coupled to the memory array; wherein when multiple units of data are to be read from the device for an address, a codeword stored in a location associated with the address is fetched from the memory array, the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block; wherein when a single unit of data is to be read from the device for the address, the codeword stored in a location associated with the address is fetched from the memory array, the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the single unit of data to be read for the address is read from the corrected data block.