Patent ID: 8949539
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. A method of implementing conditional memory reservations in a multi-processor computing system to maintain memory consistency in a shared memory, the computing system including a multitude of processor units and a shared memory, wherein all of the processor units have access to the shared memory, and the processor units make load-reserve requests to reserve an address in the shared memory and make store-conditional requests to store data to the reserved address in the shared memory, the method comprising: including in the shared memory a series of reservation registers to support load-reserve/store conditional locks, each of the reservation registers including an address field and a valid bit; using the shared memory to maintain consistency in the shared memory, including: in response to one of the processor units making a load-reserve request, storing in one of said reservation registers an address in the shared memory to lock said address for said one of the processor units to maintain consistency of data in the shared memory, and setting the valid bit in the one of the registers to indicate that the address stored in said one of the registers is reserved for said one of the processor units, wherein in response to defined events, the valid bit in said one of the registers is reset to indicate that the address stored in said one of the registers is not reserved for said one of the processor units, including when one of the other processor units stores data at said address in the shared memory, the valid bit in said one of the registers is invalidated to indicate that the address stored in said one of the registers is not reserved for said one of the processor units; in response to said one of the processor units making a store-conditional request to store data at said address in the shared memory, checking the valid bit in said one of the reservation registers to determine if said address in the shared memory is reserved for said one of the processor units; if the valid bit in said one of the reservation registers shows that said address in the shared memory is reserved for said one of the processor units, storing the data of said store-conditional request at said address in the shared memory; and if the valid bit in said one of the reservation registers shows that said address in the shared memory is not reserved for said one of the processor units, not storing the data of said store-conditional request at said address in the shared memory.