Patent ID: 8912865
Filing Date: 2014-12-16
Classification: H01L,H03F,H03H,H05K

Abstract:
1. A power combiner comprising: a primary wiring unit formed on one surface of a printed circuit board, receiving a plurality of balance signals having a plurality of positive balance signals and a plurality of negative balance signals, and including a plurality of positive primary wirings each provided to correspond to the plurality of positive balance signals and a plurality of negative primary wirings each provided to correspond to the plurality of negative balance signals, wherein the plurality of positive primary wirings are spaced apart from each other by a predetermined interval, the plurality of negative primary wirings are spaced apart from each other by a predetermined interval, one end of each of the plurality of positive primary wirings is connected in common to the one end of each of the other positive primary wirings to thereby receive the plurality of positive balance signals, one end of each of the plurality of negative primary wirings is connected in common to the one end of each of the other negative primary wirings to thereby receive the plurality of negative balance signals, and the other end of each of the plurality of positive primary wirings and of each of the plurality of negative primary wirings is connected to the other end of each of the other positive primary wirings and negative primary wirings to thereby form a loop; and a secondary wiring unit formed on the other surface of the printed circuit board, the other surface being different from the one surface having the primary wiring unit formed thereon, and including a secondary wiring combining powers of the plurality of balance signals from the primary wirings forming the loop to thereby output a single end signal.