Patent ID: 7145370
Filing Date: 2006-12-05
Classification: H03K

Abstract:
1. A circuit for providing a switched high-voltage signal in response to an input logic-level state, comprising: a first pFET having a source, drain, well and gate terminal, the source and well coupled to a source of a high-voltage signal, the drain coupled to an intermediate node and the gate coupled to a control node; a second pFET having a source, drain, well and gate terminal, the source and well coupled to the intermediate node, the drain coupled to a voltage output node and providing the switched high-voltage signal, the gate coupled to a source of a first intermediate voltage, said first intermediate voltage being intermediate said high-voltage and a ground; a diode having its anode coupled to a source of a second intermediate voltage, said second intermediate voltage being intermediate said high-voltage and the ground, and its cathode coupled to the intermediate node; and a high-voltage MOS nFET having a source, drain and gate terminal, the source coupled to the ground, the drain coupled to the voltage output node and the gate coupled to a source of the input logic-level state.