Patent ID: 9147090
Filing Date: 2015-09-29
Classification: G06F,G09C,H04L

Abstract:
1. A grid protection system in an integrated circuit chip, the grid protection system comprising: a first sector including a first set of grid lines; a second sector including a second set of grid lines at a lower layer of the integrated circuit chip than the first set of grid lines; assertion logic configured to transmit a first set of signals on the first set of grid lines and the second set of grid lines; transformation logic, coupled to the first and the second sets of grid lines, the transformation logic configured to transform the first set of signals to a second set of signals, to transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines, and to transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines; and verification logic, coupled to the transformation logic, configured to compare the second set of signals on the third and the fourth sets of grid lines to an expected set of signals.