Patent ID: 6452850
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A sense amplifier subcircuit for a DRAM memory for amplifying voltage signals read from a bit line, comprising:a lead; at least one bit line; at least one reference bit line; at least two evaluation transistors, each one of said evaluation transistors having a gate, a drain, and a source; said gate of one of said evaluation transistors configured in a manner selected from the group consisting of being connected to said at least one bit line and being connectable to said at least one bit line; said gate of another one of said evaluation transistors being configured in a manner selected from the group consisting of being connected to said at least one reference bit line and being connectable to said at least one reference bit line; said drain of said one of said evaluation transistors being configured in a manner selected from the group consisting of being connected to said at least one bit line and being connectable to said at least one bit line; said drain of said one of said evaluation transistors being configured in a manner selected from the group consisting of being connected to said at least one bit line and being connectable to said at least one bit line; said source of said one of said evaluation transistors and said source of said other one of said evaluation transistors being configured in a manner selected from the group consisting of being connected to said lead and being connectable to said lead; and at least one of said evaluation transistors designed to have a threshold voltage that changes dynamically during an evaluation operation by virtue of a change in a gate voltage being coupled to a change in a bulk voltage.