Patent ID: 6542411
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A nonvolatile memory comprising:a memory array having a plurality of nonvolatile memory elements which store data according to magnitudes of threshold voltages thereof; a booster circuit which generates a voltage applied to each of the nonvolatile memory elements upon writing or erasing of the data; a boosted voltage detecting circuit which detects the level of the voltage boosted by the booster circuit; a write/erase control circuit which starts the writing or erasing based on the detection of the voltage by the boosted voltage detecting circuit; a write/erase end detecting circuit which detects the completion of the writing or erasing started by the write/erase control circuit; and an end flag indicative of the completion of the writing or erasing started by the write/erase control circuit; further including a control register having control bits each indicative of an entry into an operation for the writing or erasing, wherein the booster circuit starts boosting according to the control bit set thereto.