Patent ID: 6801203
Filing Date: 2004-10-05
Classification: G06T

Abstract:
A computer system comprising:a processor for issuing commands; a memory sub-system coupled to said processor for storing information including graphics data; a graphics sub-system coupled to said processor and operates according to said commands from said processor, said graphics sub-system comprising: a rasterizer for traversing graphics primitives of said graphics data to generate pixel coordinates for pixels corresponding to said graphics primitives; a graphics pipeline coupled to said rasterizer for processing said graphics data, said graphics pipeline comprising: a color pipeline; a stencil z-buffer pipeline in parallel with the color pipeline; and a texture pipeline in parallel with the color pipeline and the stencil z-buffer pipeline; and a pixel cache coupled to said graphics pipeline for caching said graphics data, said pixel cache comprising: a color cache coupled to the color pipeline for caching color data; a stencil z-buffer cache coupled to the stencil z-buffer pipeline for caching stencil z-buffer data; and a texture cache coupled to the texture pipeline for caching texture data; and wherein said graphics sub-system masks latency of said memory sub-system by pre-fetching said graphics data and storing said graphics data within said pixel cache.