Patent ID: 6037669
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A semiconductor die assembly comprising:a semiconductor die having at least one surface edge including an outer row of bond pads which are substantially evenly spaced and positioned near said surface edge of said semiconductor die, said outer row of bond pads having n bond pads in said outer row, and an inner row of substantially evenly spaced bond pads parallel to said outer row of bond pads, said inner row of bond pads having n+1 bond pads in said inner row, said inner row of bond pads is substantially equal in length to said outer row of bond pads; wherein individual bond pads of said inner row of bond pads are positioned such that individual bond wires that provide an electrical connection between an individual lead and a bond pad of the inner row of bond pads passes substantially medially between adjacent bond pads of said outer row of bond pads;a radially arrayed pattern of individual leads associated with said edge of said semiconductor die and including at least one individual lead being at least 20.degree. offset from a line perpendicular to the edge of said semiconductor die; anda plurality of bond wires wherein each wire provides an electrical connection between a single bond pad and an individual lead.