Patent ID: 6218881
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:an output circuit of a CMOS composed of a P-channel MOS transistor that has its gate connected to an input terminal, has its source connected to a power source line, and has its drain connected to an output terminal and an N-channel MOS transistor that has its gate connected to said input terminal, has its source connected to ground, and has its drain connected to said output terminal;a first protection diode formed in parallel with a source-drain channel of said P-channel MOS transistor;a first NPN-type transistorformed so that its base is connected to ground and its collector-emitter path is connected in parallel with the source-drain channel of said P-channel MOS transistor;a second protection diode formed in parallel with a source-drain channel of said N-channel MOS transistor; anda thyristor circuit formed in parallel with the source-drain channel of said N-channel MOS transistor and operating only when abnormal electrostatic charge is applied to said output terminal;wherein said thyristor circuit is composed of a PNP-type transistor that has its base connected directly to said power source line, has its emitter connected to said output terminal, and has its collector connected through a resistor to ground and a second NPN-type transistor that has its base connected to said resistor, has its collector connected to the base of said PNP-type transistor, and has its emitter connected to ground.