Patent ID: 8559240
Filing Date: 2013-10-15
Classification: G11C

Abstract:
1. A CMOS latch-type sense amplifying circuit, comprising: a CMOS differential amplifier including PMOS and NMOS transistors, the CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair; a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair; and a first common node configured to connect to a high supply voltage or a low supply voltage based on a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.