Patent ID: 9223519
Filing Date: 2015-12-29
Classification: G06F,G11C,H01L

Abstract:
1. An electronic device comprising a semiconductor memory unit that includes: a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer that are configured so that the tunnel barrier layer is between the free magnetic layer and the pinned magnetic layer; a first electrical contact layer that is in electrical contact with the resistance variable element under the resistance variable element; a second electrical contact layer that is in electrical contact with the resistance variable element over the resistance variable element, wherein the first and second electrical contacts collectively apply an electrical signal to the resistance variable element; and a magnetic correction layer located over the second electrical contact so that the second electrical contact is between the magnetic correction layer and the resistance variable element, wherein the magnetic correction layer is electrically insulated from the second electrical contact and is configured to exhibit a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer to offset an influence of a magnetic field of the pinned magnetic layer to the free magnetic layer, and wherein the magnetic correction layer is in a floating state in which no voltage is applied when the electronic device is powered on.