Patent ID: 8410828
Filing Date: 2013-04-02
Classification: H03K

Abstract:
1. A driver circuit comprising: first and second output terminals for connection across a load; a pair of first switches of a first polarity, the first switches coupled in parallel between a first current node and respective ones of the first and second output terminals, the first current node enabling a current of a first value to flow between the first current node and the first or second output terminal; a first current source coupled between a supply voltage source and the first current node for supplying the current of the first value; a plurality of pairs of second switches of a second polarity, each pair coupled in parallel between a respective second current node and the first and second output terminals to enable a current portion to flow between the second current node and the first or second output terminal, the current portions summing to the first value; a plurality of second current sources coupled between the respective second current node and ground for supplying each of the current portions summing to the first value; and timing circuitry arranged to apply a first input signal to one of the pair of first switches and a first inverse input signal to the other switch of the first pair, said first input and inverse input signals remaining applied while successive second input signals are applied to each of the pairs of second switches whereby the current enabled to flow through the load successively changes to develop a staggered voltage across the load.