Patent ID: 6184745
Filing Date: 2001-02-06
Classification: G05F

Abstract:
A reference voltage generating circuit, comprising:a reference voltage generating unit for generating a first reference voltage with respect to a power supply voltage; anda level converting unit for converting said first reference voltage outputted from said reference voltage generating unit to a second reference voltage with respect to a ground voltage, andwherein the second reference voltage remains constant regardless of changes in a back-bias voltage,wherein said reference voltage generating unit comprises:a first PMOS transistor having a source and a bulk which receive the power supply voltage over a resistor;a second PMOS transistor having a source and a bulk which receive the power supply voltage, and a gate which is connected with a gate of said first PMOS transistor and a first output node; andfirst and second NMOS transistors each having a bulk for receiving the back-bias voltage, the first NMOS transistor being connected between a drain of the first PMOS transistor and a ground, and the second NMOS transistor being connected between a drain of the second PMOS transistor and the ground, thereby constituting a current mirror.