Patent ID: 7382847
Filing Date: 2008-06-03
Classification: H03L

Abstract:
1. A sync pulse generator operable in a clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising: phase detection circuitry operable to sample said first clock signal with said second clock signal to determine coincident edges of said first and second clock signals: validation circuitry operable to validate said coincident edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto; and sync generation circuitry, responsive to said valid edge signal, operable to generate synchronization pulses in said first clock domain and synchronization pulses in said second clock domain when said first and second clock signals have one of a coincident rising edge and a coincident falling edge.