Patent ID: 8462907
Filing Date: 2013-06-11
Classification: H04J,H04L

Abstract:
1. A network component comprising: a first adaptation component comprising a first input for a first internal timing reference; a second adaptation component comprising a second input for a second internal timing reference; a system Phase-Locked-Loop (PLL) coupled to the first adaptation component; a comparison and voting logic component coupled to the first adaptation component and the system PLL component; a compensation logic component coupled to the comparison and voting logic component; a positive/negative delay component coupled to the second adaptation component and the compensation logic component; a first ingress component coupled to the first adaptation component; a second ingress component coupled to the second adaptation component; an output PLL component coupled to the system PLL component; and an egress component coupled to the positive/negative delay component and the output PLL component, wherein the comparison and voting logic comprises a memory for storing a plurality of predefined timing reference values.