Patent ID: 7554180
Filing Date: 2009-06-30
Classification: H01L

Abstract:
1. An integrated circuit device package, comprising: an integrated circuit device having an electrically active surface and an opposing backside surface and sides extending therebetween, said electrically active surface having a plurality of electrically active circuit traces formed thereon and metallized bumps extending from selected sites on said circuit traces, and said sides including at least one feature that is effective to limit the ingress of moisture along an interface between said integrated circuit device and a dielectric molding resin, mechanically lock said integrated circuit device to said dielectric molding resin and cause said backside surface area to be less than said electrically active surface area; a plurality of electrically conductive leads each having respective first surfaces and opposing second surfaces; a plurality of electrical contacts extending outward from said respective first surfaces; and a solder electrically and mechanically bonding said metallized bumps to said second surfaces; wherein said dielectric molding resin is formed into a package at least partially encapsulating said integrated circuit device and said plurality of electrically conductive leads, said backside surface and said plurality of electrical contacts are exposed on opposing sides of said package, said interface has an end portion between said integrated circuit device at the exposed backside surface and the dielectric molding resin adjacent thereto, and an interior portion substantially parallel to the backside surface, and said electrically active surface includes a central region and a peripheral region, said metallized bumps disposed in the peripheral region and said dielectric molding resin covering the central region.