Patent ID: 7982496
Filing Date: 2011-07-19
Classification: H03K

Abstract:
1. A logic block having multi-bit first and second inputs and a multi-bit output, the logic block comprising: a multi-bit first multiplexer circuit having a multi-bit first input coupled to a multi-bit first input of the logic block, a multi-bit second input, and a multi-bit output; a multi-bit programmable logic circuit having a multi-bit first input coupled to the output of the first multiplexer circuit, and further having a multi-bit output; a plurality of memory cells having outputs coupled to the second input of the first multiplexer circuit and programmable with a constant value; a multi-bit second multiplexer circuit having a multi-bit first input coupled to the outputs of the plurality of memory cells, a multi-bit second input coupled to a multi-bit second input of the logic block, and a multi-bit output coupled to a second input of the programmable logic circuit.