Patent ID: 6775286
Filing Date: 2004-08-10
Classification: H04L

Abstract:
A router comprising a number (n) of inputs (9, 19, 29, 39) and a number (n) of outputs (49, 59, 69, 79) for routing data packets from the inputs (9, 19, 29, 39) to the outputs (49, 59, 69, 79), comprising:a reticular routing switch constituted by a number (n) of first incoming lines (5, 6, 7, 8), a number (n) of second incoming lines (1, 2, 3, 4), a number (n) of first outgoing lines (50, 60, 70, 80) and a number (n) of second outgoing lines (10, 20, 30, 40), each of the first incoming lines (5, 6, 7, 8) being respectively connected to an input (9, 19, 29, 39) and each of the first outgoing lines (50, 60, 70, 80) being respectively connected to an output (49, 59, 69, 79) and switchable to any of the incoming lines (1, 2, 3, 4, 5, 6, 7, 8); a memory (89) comprising a number (n) of write lines (101, 102, 103, 104), each connected to one of the second outgoing lines (10, 20, 30, 40), a number (n) of read lines (110, 120, 130, 140), each connected to one of the second incoming lines (1, 2, 3, 4,) and a number (n) of groups (n) of cells (111, 112, 113, 114), (121, 122, 123, 124), (131, 132, 133, 134), (141, 142, 143, 144); each read line (110) configured to allow an extraction of a packet contained in a group of (n) cells (111 through 114); and each write line (101) configured to allow an insertion of a packet into one of the cells (111, 121, 131, 141) of each group of (n) cells.