Patent ID: 6434062
Filing Date: 2002-08-13
Classification: G11C,H03K,H03L

Abstract:
A delay locked loop for use in a semiconductor memory device, comprising:an input means for receiving a clock signal and a non-clock signal and comparing the received signals and producing an internal timing signal; a control means for receiving the internal timing signal and producing a control signal; a bi-directional oscillating means, responsive to the control signal from the control means, for performing a ring oscillation in a first or second direction and performing an additiona and subtraction adjustment function for a time delay; a counting means for counting ring oscillations in each of the first and second directions and generating a match signal when a match condition of the counter ring oscillations is satisfied; and an output means for performing a combination operation on the respective outputs of the bi-directional oscillating means and the counting means and providing the result as a final internal clock signal.