Patent ID: 9065449
Filing Date: 2015-06-23
Classification: H03K

Abstract:
1. A divide-by-1.5 circuit, comprising: a divide-by-3 circuit having an input coupleable to a source of an input signal; and a frequency doubler circuit comprising phase-locked loop (PLL) circuitry, the frequency doubler circuit having an input coupled to an output of the divide-by-3 circuit and having an output defining an output of the divide-by-1.5 circuit, the PLL circuitry having a comparison circuit, a loop filter, a voltage-controlled oscillator (VCO), and a loop divider circuit, the comparison circuit having a first input defining the input of the frequency doubler circuit, the loop divider circuit having an input coupled to an output of the VCO and an output coupled to a second input of the comparison circuit, an output of the VCO defining an output of the frequency doubler circuit, the loop filter connected to an output of the comparison circuit and an input of the VCO, the frequency doubler circuit coupled to a pre-divide-by-2 circuit having an output coupled to the first input of the comparison circuit, wherein the loop divider circuit comprises a loop divide-by-4 circuit including two loop divide-by-2 circuits in series with each other, and wherein each of the two loop divide-by-2 circuits consists of a D flip-flop.