Patent ID: 6166673
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A data acquisition system for sampling and storing analog data at a selectable clock frequency, the data acquisition system comprising:an analog-to-digital converter (ADC) configured to receive the analog data and a first clock signal having a first clock frequency F1, wherein said ADC is operable to sample the analog data at said first clock frequency F1 and convert samples of the analog data into digital data samples;a decelerator including an input coupled to said ADC and configured to receive said digital data samples, wherein said decelerator is operable to receive and store N digital data samples, wherein said decelerator includes N outputs, wherein said decelerator is operable to output said N digital data samples on said N outputs in a parallel fashion, wherein said decelerator is operable to output said N digital data samples at a second clock frequency F2 equal to F1/N, and wherein said decelerator repetitively operates to receive and store N digital data samples and output said N digital data samples in said parallel fashion;a memory comprising a plurality N of memory partitions, wherein each of said N memory partitions is coupled to one of said N outputs of said decelerator and wherein each of said N memory partitions is configured to receive digital data samples from said decelerator;a control logic unit configured to receive a second clock signal having said second frequency F2, wherein said control logic unit generates a sequence of N store-enable signals at said second frequency F2, wherein each of said N store enable signals is provided to one of said N memory partitions; wherein said N store-enable signals are generated with a pattern of enable and non-enable bits to selectively store data in said N memory partitions, and wherein said pattern is configured to generate a sample rate for said analog data.