Patent ID: 6055206
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock signal and sending and receiving storage data, comprising:a memory cell array having a plurality of memory cells arranged in rows and columns, and divided into a plurality of memory cell blocks;a plurality of word lines provided corresponding to respective rows of said memory cells;a control circuit responsive to said address signal and said control signal for selectively instructing at least one of said plurality of memory cell blocks to perform a prescribed operation; anda plurality of row select circuits each provided for a corresponding one of said memory cell blocks for selecting at least one of said rows of said memory cell block in response to said address signal, each of said row select circuits includinga row select signal generating circuit for generating a pulse-wise row select signal according to said address signal,a hierarchical power supply circuit, activated in response to the selection of said corresponding memory cell block and supplying voltage power to said row select signal generating circuit at least during an active period of said pulse-wise row select signal, and changing voltage power level to reduce a leakage current through said row select signal generating circuit during a stand-by state,a plurality of row select signal lines each for transmitting said pulse-wise row select signal to said corresponding memory cell block, anda plurality of row drive circuits each coupled to one of said row select signal lines in response to the selection of said memory cell block for latching a state of said pulse-wise row select signal and driving the potential level of a corresponding one of said word lines.