Patent ID: 6047352
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A memory system, including:an array of memory cells organized in rows and columns;array interface circuitry coupled to the array and configured to select one or more of the cells in response to selection bits;a predecoding circuit, coupled to the array interface circuitry, and operable to assert multiblock selection bits to the array interface circuitry in response to control signals, to cause the array interface circuitry to select simultaneously at least one cell in each of a selected combination of blocks of the cells in response to the multiblock selection bits; andat least one register coupled to the predecoding circuit for storing at least one of the multiblock selection bits, wherein the predecoding circuit is operable to receive said at least one of the multiblock selection bits from said at least one register and assert said at least one of the multiblock selection bits to the array interface circuitry.