Patent ID: 8675681
Filing Date: 2014-03-18
Classification: H03K

Abstract:
1. An integrated circuit comprising: an array of interconnected programmable logic elements, each logic element performing data processing controlled by a configuration stored after manufacture into said logic element; one or more shared communication channels providing intra-array communication within said array; and a plurality of dedicated communication interface circuits distributed within said array, said dedicated communication interface circuits providing access to said one or more shared communication channels; wherein said logic elements are configured to provide a plurality of functional units, each of said plurality of functional units emulating a macrocell communicating using a transaction protocol with other macrocells and each of said plurality of functional units having an interconnect interface for transferring multi-bit communication transactions having said transaction protocol and coupled to one of said plurality of dedicated communication interface circuits; said plurality of dedicated communication interface circuits and said one or more shared communication channels are controlled by said configuration to emulate an interconnect circuit configured to transfer said multi-bit communication transactions having said transaction protocol between said plurality of functional units via a plurality of interconnect channels; and each of said one or more shared communication channels has a communication bandwidth greater than required to emulate one of said plurality of interconnect channels such that a plurality of interconnect channels share one of said one or more a shared communication channels, said integrated circuit further comprising: arbiter circuitry within said array arbitrating access to said one or more shared communication channels by said plurality of dedicated communication interface circuits to control contention between said multi-bit communication transactions such that said multi-bit communication transactions complete in times that vary in dependence upon said contention controlled by said arbiter circuitry.