Patent ID: 7917880
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. A method for reducing power consumption for an integrated circuit on a substrate, comprising the steps of: providing a clock tree and a gate-signal control logic circuit on a substrate, wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes; recursively determining a merging segment set containing merging segments for each node and computing switched capacitance of a subtree rooted at each node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each node; and recursively determining a location for each node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each node is minimum; wherein the switched capacitance of a subtree rooted at a node is a sum of switched capacitance of a first portion of the subtree having a first child node of the node and switched capacitance of a second portion of the substree having a second child node of the node, wherein if a masking gate is placed on an edge connecting the node and the first child node, the switched capacitance of the first portion of the subtree having a first child node of the node is a function related to capacitance of the gate, capacitance of the edge, and capacitance between the node and the gating-signal control logic circuit, a signal probability of the gating-signal control logic circuit to the first child node, and a transition probability of the gating-signal control logic circuit to the first child node.