Patent ID: 7113438
Filing Date: 2006-09-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of word lines connected respectively to a plurality of memory cell blocks, each of which is composed of a plurality of memory cells, in a row direction of the memory cells, and a plurality of pairs of bit lines connected respectively to the plurality of memory cell blocks in a column direction of the memory cells; and a plurality of sense amplifier arrays, each of which includes a plurality of sense amplifiers, each of which is connected to bit lines and complementary bit lines of the plurality of pairs of bit lines, for sensing a potential difference between the bit lines and the complementary bit lines, wherein each of the plurality of sense amplifiers is connected to a first pair of bit lines of an upper memory cell block adjacent to the sense amplifier, a second pair of bit lines of a lower memory cell block adjacent to the sense amplifier, a pair of bit lines of at least one upper memory cell block not adjacent to the sense amplifier, and a pair of bit lines of at least one lower memory cell block not adjacent to the sense amplifier, and wherein each sense amplifier array is disposed between two memory cell blocks adjacent to each other, and sense amplifiers of a sense amplifier array are disposed in zigzags with sense amplifiers of another sense amplifier array adjacent thereto.