Patent ID: 7685455
Filing Date: 2010-03-23
Classification: G06F,G11C

Abstract:
1. A semiconductor integrated circuit comprising: a clock input terminal inputted with a clock signal which repeats a cycle having a first level, a second level, and two edges; a data input terminal inputted with a data signal; a first internal clock generating circuit for generating a first internal clock signal which changes a signal in a mid-period between a (n+i−j)th edge of said clock signal and a (n+i+j+1)th edge of said clock signal (where i denotes an integer of 1 or larger, j denotes an integer of 0 or larger and n denotes an integer of i+j+2 or larger; and a first latch circuit for latching said data signal input to said data input terminal according to said first internal clock signal, wherein said (n+i−j)th edge is an edge of changing from said first level to said second level, and wherein said (n+i+j1)th edge is an edge of changing from said second level to said first level.