Patent ID: 8065551
Filing Date: 2011-11-22
Classification: G06F,G11C

Abstract:
1. A system, comprising: a module comprising a circuit board having a plurality of circuits thereon, each circuit having at least one data path internal to the circuit, the data paths coupling to module outputs on the circuit board; a delay circuit in the data path of at least one of the circuits, wherein the delay circuits are programmable; and a connector for coupling the module outputs to a mother board, wherein the connector comprises conductors of different lengths so as to introduce a delay, wherein a call from the mother board to the module for parallel data from the module outputs results in some, but not all, of the data being delayed at the module outputs by the at least one delay circuit so as to compensate for the delay introduced by the conductors in the connector, whereby the data arrives at the mother board at substantially the same time.