Patent ID: 7767492
Filing Date: 2010-08-03
Classification: G06F,H01L,H04L

Abstract:
1. An apparatus for enabling a multi-core/multi-package environment on a bus, the bus requiring active termination impedance control, the apparatus comprising: a first node, disposed within a processor core and configured to receive an external multi-package signal indicating whether a package upon which said processor core is disposed is internal to the bus or at a far end of the bus; a location array, disposed within said processor core and configured to generate a plurality of location signals that indicate locations on the bus of a corresponding plurality of nodes that are coupled to the bus, wherein said locations comprise either an internal location or a bus end location; and a plurality of drivers, coupled to said plurality of location signals, each comprising one of said corresponding plurality of nodes, and each configured to control how said one of said corresponding plurality of nodes is driven responsive to a first state of a corresponding one of said plurality of location signals and a second state of said first node, each of said plurality of drivers comprising: