Patent ID: 6789140
Filing Date: 2004-09-07
Classification: G06F

Abstract:
A data processor for processing operation data stored in a memory connected to an external bus in the order of operations, comprising:an operation memory for storing the operation data transferred; an interface section for holding addresses of the operation data required for transfer of the operation data; and an operation section receiving the operation data from the interface section for processing a command included in the operation data, wherein the interface section sequentially transfers the operation data from the memory connected to the external bus to the operation memory using the address, and sequentially transfers the operation data from the operation memory to the operation section, and wherein the interface section transfers transfer information for transfer of operation data to be next processed to the operation memory, together with the current operation data, and when reading the transfer information from the operation memory, the interface section transfers the operation data to be next to processed corresponding the transfer information from the memory connected to the external bus to the operation memory.