Patent ID: 9190455
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A semiconductor memory device comprising, when two directions crossing one another are referred to as a first direction and a second direction, whereas a direction crossing the first direction and the second direction is referred to as a vertical direction, a memory cell array comprising: a plurality of lower wirings extending in the first direction; an upper wiring extending in the second direction, the upper wiring placed above the lower wirings; a plurality of memory cells provided at crossings of the lower wirings and the upper wiring; and an interlayer insulating film provided between the memory cells, the upper wiring including: an upper wiring first section deposited above the memory cells; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section having an average crystal grain size larger than an average crystal grain size of the upper wiring first section, and a height of a bottom surface of the upper wiring facing a top surface of the memory cells in the vertical direction being lower than a height of the bottom surface of the upper wiring facing a top surface of the interlayer insulating film in the vertical direction.