Patent ID: 8835264
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method for fabricating a power semiconductor device, comprising: providing a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; forming a hard mask layer on the epitaxial layer; forming at least one opening in the hard mask layer; forming a spacer on a sidewall of the opening; etching the epitaxial layer through the opening to thereby form at least one first trench; depositing a dopant source layer on an interior surface of the first trench, on the spacer and on a top surface of the hard mask layer; thermally driving dopants from the dopant source layer into the epitaxial layer to thereby form a doping region in the first trench, the doping region comprising a first region closer to the interior surface of the first trench and a second region deeper into the epitaxial layer; removing the dopant source layer and the spacer to reveal upper corner portions of the first trench; filling the first trench with a sacrificial layer; and performing a dry etching process, using the hard mask layer as an etching hard mask, to completely etch away the sacrificial layer and the epitaxial layer in the first region, thereby forming a second trench.