Patent ID: 6603196
Filing Date: 2003-08-05
Classification: H01L

Abstract:
A semiconductor package, which comprises:(a) a lead frame, which includes: (a1) a supporting bar; (a2) a chip-supporting structure, which is arranged at a downset position in relation to the supporting bar; and (a3) a plurality of leads connected to one side of the supporting bar, each lead including an outer-lead portion and an inner-lead portion smaller in width than the outer-lead portion, making the outer-lead portions relatively more closely arranged than the inner-lead portions; wherein the outer-lead portion of each lead is levelly linked to the supporting bar, while the inner-lead portion is arranged beside the chip-supporting structure and linked to the outer-lead portion via an intermediate-lead portion; (b) a chipset including at least one semiconductor chip mounted over the chip-supporting structure; (c) a set of bonding wires for electrically coupling the semiconductor chip to the inner-lead portions of the leads; and (d) an encapsulation body for encapsulating the semiconductor chip, the chip-supporting structure, the bonding wires, and the inner-lead portions of the leads, while exposing one surface of the outer-lead portion of each of the leads to outside.