Patent ID: 9111845
Filing Date: 2015-08-18
Classification: H01L,H05K

Abstract:
1. An integrated circuit (“IC”) package comprising: an IC die having an upper surface with a plurality of contact pads thereon and a bottom surface; an etched metal signal routing layer positioned below said bottom surface of said die and having a top surface and a bottom surface; a tape substrate positioned below said IC die and said signal routing layer and having a top surface and a bottom surface and having a plurality of vias extending between said top and bottom surfaces thereof; at least one resist layer provided on one of said tape substrate and said signal routing layer; a conductive ink printed circuit layer printed on one of said tape substrate and said resist layer and electrically connected to said signal routing layer; an encapsulation layer encapsulating said IC die, said signal routing layer, said conductive ink printed layer and at least a portion of said tape substrate; and an array positioned below said tape substrate and electrically attached to said signal routing layer through said vias, wherein said die is wire bond attached to said etched metal signal routing layer.