Patent ID: 6465339
Filing Date: 2002-10-15
Classification: H01L

Abstract:
The method of fabricating a conducting layer in an integrated circuit, said conducting layer including at least two conducting paths, said method comprising the steps of:forming said conducting paths; forming a layer of etchable material between and over said conducting paths; forming a removable fill material over and between said conducting paths; forming an oxide layer over said fill material; forming vias through the etchable material, the fill material, and the oxide layer; filling the vias with a conductive material to form conducting plugs in electrical contact with said conducting paths; forming an aperture in said oxide layer at a location between first and second ones of the conducting plugs to provide an entrance to said removable fill material; removing at least a portion of said fill material under the oxide layer and extending away from the location of the aperture, so that at least a portion of the fill material disposed over one of the conducting paths is removed; and depositing a second oxide layer over said conducting plugs and said oxide layer.