Patent ID: 8756546
Filing Date: 2014-06-17
Classification: G06F

Abstract:
1. A computer-implemented method for providing an elastic modulus map of a chip carrier of a flip chip package, said method comprising: loading, by a computer, design data for said chip carrier of said flip chip package that includes x, y, z coordinates of all design elements disposed within each of a number of layers, which are disposed under flip chip (FC) pads, said design elements comprising any of a dielectric, a conductive plane, a conductive signal line, and a conductive via; mapping, by said computer, a uniform square grid of sub-areas onto a plan view of each of said number of layers of said chip carrier, each of said sub-areas being defined by said x, y coordinates; determining, by said computer, a dielectric area and a conductive area for each of said sub-areas of each of said number of layers, based on said design data for any portions of said design elements disposed within each of said sub-areas; determining, by said computer, for each of said sub-areas of each of said number of layers, an equivalent spring constant related to a first spring constant based on a first elastic modulus of said dielectric, said dielectric area, and a dielectric thickness from said z coordinate of said design data, and a second spring constant based on a second elastic modulus of said conductive material, said conductive area, and a conductive material thickness from said z coordinate of said design data; accumulating, by said computer, each equivalent spring constant from each vertically aligned sub-area in each of said number of layers, to provide a combined spring constant for each of said sub-areas of said chip carrier; and mapping, by said computer, each of said combined spring constants onto said uniform square grid of said chip carrier, to provide said elastic modulus map.