Patent ID: 6304493
Filing Date: 2001-10-16
Classification: B82Y,G11C,H01L,Y10S

Abstract:
A method of reading a memory cell including a MOSFET having one or more islands for charge storage, each island surrounded by an insulator having a thickness of less than twenty nanometers, each island and surrounding insulator extending into a pore anodically formed in semiconductor material forming the MOSFET, comprising:selecting a row and a column in a memory array to select the memory cell, the memory cell being located at an intersection of the selected row and column;forming a channel by biasing a gate of the MOSFET more positive than a source of the MOSFET;biasing a drain of the MOSFET;sampling an electrical parameter of the selected memory cell while the bias is applied to the drain;comparing the sample to a threshold to determine if an electron is stored in the island in the selected memory cell;providing an indication of a first logical state when the act of comparing determines that an electron is stored in the island; andproviding an indication of a second logical state when the act of comparing determines that no electron is stored in the island.