Patent ID: 6412039
Filing Date: 2002-06-25
Classification: G06F

Abstract:
A cross memory bank, cross memory page data accessing and controlling unit for coupling to a CPU and a memory cluster such that the memory cluster has a plurality of memory banks and each memory bank has a plurality of memory pages, and the CPU is able to access data in the memory cluster through the data accessing and controlling unit, comprising:a CPU interface circuit that couples to the CPU for receiving a CPU data access request and then sending out an internal data access request signal, such that when the CPU submits consecutive requests for data in different memory banks, the CPU interface circuit submits a cross memory bank signal together with the internal data access request, and when the CPU submits consecutive requests for data in different memory pages, the CPU interface circuit submits a cross memory page signal together with the internal data access request; and a memory controlling circuit that couples to the CPU interface circuit and the memory cluster for receiving the internal data access request and associated controlling signals, such that when a cross memory bank or a cross memory page signal is received along with the internal data access request, the page within the memory bank where the requested data resides is opened immediately.