Patent ID: 6998318
Filing Date: 2006-02-14
Classification: H01L

Abstract:
1. A method for forming short-channel transistors, comprising the steps of: forming a first oxide layer and a sacrificial layer one after another on a semiconductor substrate and etching the sacrificial layer thus forming a residual sacrificial layer pattern; conducting an ion implantation using the residual sacrificial layer pattern as a mask, thus forming an LDD ion-implant layer in the semiconductor substrate; forming first spacers on both side walls of the residual sacrificial layer pattern; conducting an ion implantation using the residual sacrificial layer pattern and the first spacers as a mask, thus forming a source/drain ion-implant layer under the LDD ion-implant layer; forming a nitride layer and a second oxide layer one after another on the whole surface of the former resultant object and conducting an annealing treatment, thus forming source/drain regions; conducting a chemical-mechanical polishing (CMP) process to the extent that an upper surface of the residual sacrificial layer pattern is exposed, and removing the residual sacrificial layer pattern through etching; forming second spacers on side walls of a portion where the residual sacrificial layer pattern is removed; conducting an ion implantation on the substrate between the second spacers and through the first oxide layer, thus forming a punch-stop ion implant layer; etching the first oxide layer under the portion where the residual sacrificial layer pattern is removed, and forming a gate insulation layer having a thickness sufficient to reach the second spacers; and forming a gate on the second spacers and the gate insulation layer where the residual sacrificial layer pattern is removed.