Patent ID: 7170604
Filing Date: 2007-01-30
Classification: G03F,H01L

Abstract:
1. An overlay target for optically measuring the overlay alignment of layers formed on a semiconductor wafer comprising: first and second test patterns, each including an upper grating layer and a lower grating layer, each grating layer including a series of substantially parallel lines, the upper grating lines of each test pattern aligned to be substantially parallel to the lower grating lines of the same test pattern, each test pattern having an associated offset bias defined by a lateral offset of the upper and lower grating layers of the test pattern, where a single line pitch is used for all gratings in all test patterns and where the difference between the offset bias of the first test pattern and the offset bias of the second test pattern is substantially equal to the line pitch divided by four whereby the combined optical response to the measurement of the first and second test patterns is sensitive to all values of overlay alignment.