Patent ID: 7757193
Filing Date: 2010-07-13
Classification: G06F

Abstract:
1. A method for clustering logic elements in a programmable logic integrated circuit, comprising: initializing each logic element in a structural cluster of the programmable logic integrated circuit, the structural cluster including a first logic element and a second logic element; identifying a critical path between the first logic element and the second logic element; generating a plurality of configurations by an Electronic Design Automation (EDA) tool for clustering the first element and the second element to form first-element-and-second-element configurations for the selected critical path, the plurality of configurations being generated based on a plurality of horizontal and vertical orientations of the first element relative to the second element, each first-and-second-element configuration having a logic connection between the first element and the second element that maps to a dedicated point-to-point connection on the programmable logic integrated circuit; wherein the clustering of the first element and the second element comprises clustering a first cluster and a second cluster, respectively, to form cluster-and-cluster configurations, each cluster-and-cluster cluster having a logic connection between the first cluster and the second cluster that maps to a dedicated connection on the programmable logic integrated circuit; reducing the number of the plurality of configurations by the EDA tool according to one or more predetermined multi-dimensional criteria, thereby generating a subset of configurations from the plurality of configurations, each criterion having a set of parameters that are prioritized, each parameter having a predetermined value; and determining whether the subset of configurations meets a critical path timing requirement.