Patent ID: 8975148
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A method of forming a plurality of memory cells, comprising: forming a stack over a semiconductor base; the stack comprising a homogeneous n-type doped region, a p-type doped region, and an ovonic material over the p-type doped region; patterning the stack into rails, with the rails extending along a first direction, the rails being spaced from one another by first trenches; filling the first trenches with first electrically insulative material; patterning the rails into pillars, the patterning into the pillars comprising etching into but not entirely through the homogeneous n-type doped region to form a portion of the homogeneous n-type doped region into segments within the pillars, and to leave some of the homogeneous n-type doped region as first conductive lines interconnecting the pillars along the first direction; the patterning forming second trenches which extend along a second direction that intersects the first direction; filling the second trenches with second electrically insulative material; and forming second electrically conductive lines over the ovonic material, with the second electrically conductive lines extending along the second direction; the second electrically conductive lines interconnecting the pillars along the second direction.