Patent ID: 6614078
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A latchup-immune CMOS I/O structure, comprising:a semiconductor wafer having a first conductivity type-substrate; an second conductivity type-well formed in said first conductivity type-substrate; first heavily-doped conductivity type source and drain regions formed in said second conductivity type-well, said first heavily-doped conductivity type source regions connected to a first voltage supply (VCC); second heavily-doped conductivity type guard-rings surrounding each of said first heavily-doped conductivity type source and drain regions, where said second heavily-doped conductivity type guard-rings are connected to said first voltage supply (VCC); second heavily-doped conductivity type source end drain regions formed in said first conductivity type-substrate, said second heavily-doped conductivity type source regions connected to a second voltage supply (VSS); and first heavily-doped conductivity type guard-rings surrounding each of said second heavily-doped conductivity type source and drain regions, where said first heavily-doped conductivity type guard-rings are connected to said second voltage supply (VSS), and where said second voltage supply (VSS) is more negative than said first voltage supply (VCC).