Patent ID: 6825110
Filing Date: 2004-11-30
Classification: H01L

Abstract:
A method for fabricating a semiconductor component with a cathode and an anode formed on a wafer, comprising treating the wafer first on the cathode side, reducing the thickness of the wafer thereupon on the side opposite to the cathode, and, in a further step, producing the anode on said side opposite to the cathode, introducing a stop layer before the cathodal treatment, and removing the stop layer except for a tail barrier layer zone during the reduction of the wafer thickness,wherein the stop layer is produced in the tail barrier layer zone and the stop layer has a dopant area density which lies between a minimum and a maximum area density, the maximum dopant area density being chosen in a manner dependent on a doping profile decay length in the tail barrier layer zone, and the minimum dopant area density being chosen in a manner dependent on a punch-through degree defined as the ratio of a punch-through voltage and an avalanche breakdown voltage.