Patent ID: 7639090
Filing Date: 2009-12-29
Classification: H03L

Abstract:
1. An delay-lock loop, comprising: a delay circuit coupled to receive an input clock signal, the delay circuit structured to delay the input clock signal by a delay determined by a delay control signal to provide a delayed clock signal; a phase detector receiving at least two input signals, the phase detector being structured to determine a phase difference between the at least two input signals and generate at least one output signal based on the determined phase difference, the at least one output signal being used to generate the delay control signal; a first circuit coupled to receive the at least one output signal from the phase detector, the first circuit being structured to generate a first control signal based upon the at least one output signal; and a second circuit coupled to receive the input clock signal, the delayed clock signal, and the first control signal, the second circuit being structured to modify at least one of the input clock signal and the delayed clock signal based upon the first control signal to provide a modified signal, the second circuit being structured to provide the modified signal and at least one signal to the phase detector as the at least two input signals to the phase detector, the at least one signal provided to the phase detector being based on at least one of the input clock signal and the delayed clock signal.