Patent ID: 6747348
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A semiconductor package, comprising:a first semiconductor chip having an upper surface; a second semiconductor chip having an upper surface and an opposing lower surface, the lower surface of the second chip being positioned on the upper surface of the first chip to define an exposed portion of the upper surface of the first chip, the first chip further including a first plurality of bond pads disposed on the exposed portion, and the second chip further including a second plurality of bond pads disposed on the upper surface of the second chip; a plurality of interconnections that extend from the first plurality of bond pads to the second plurality of bond pads, the interconnections being disposed on selected portions of the first and second chips to electrically couple the first and second chips; and a plurality of castellations disposed on selected portions of the first chip that extend outwardly from the first plurality of bond pads to form leadless input/output locations for the package.