Patent ID: 8665657
Filing Date: 2014-03-04
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells; a pair of first and second local bit lines to which the plurality of memory cells are connected; a pair of first and second write global bit lines; a pair of first and second read global bit lines; a first write transistor having a source connected to a power supply node to which a power supply voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line; a second write transistor having a source connected to the power supply node, a drain connected to the second local bit line, and a gate connected to the first write global bit line; a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied; a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied; a precharge circuit connected to the first and second local bit lines; a write driver configured to control the first and second write global bit lines; and a read circuit connected to the first and second local bit lines and the first and second read global bit lines.