Patent ID: 7498848
Filing Date: 2009-03-03
Classification: G01R,H03K

Abstract:
1. A clock monitor system for monitoring an input clock signal to an integrated circuit(IC), wherein the input clock signal switches alternatively between a first logic level and a second logic level, the clock monitor system comprising: a clock failure detection circuit that generates a control signal based on an input clock signal switching; and a delay circuit connected to the clock failure detection circuit that provides a clock status signal to the IC based on the control signal after a pre-determined number of input clock cycles, wherein the clock status signal indicates a failure of the input clock signal; and wherein the clock failure detection circuit comprises: a plurality of transistors that monitor the input clock signal, wherein at least one of the plurality of transistors is in an OFF state during a first time slot, and wherein each of the plurality of transistors is in an ON state during a second time slot; an energy storage element connected to the plurality of transistors that charges during the second time slot and discharges during the first time slot; and an output circuit connected to the energy storage element that generates the control signal based on a voltage level of the energy storage element, wherein the control signal is provided as an input to the delay circuit.