Patent ID: 7085148
Filing Date: 2006-08-01
Classification: G11C

Abstract:
1. A semiconductor memory device having a semiconductor substrate, comprising: a plurality of memory cells for storing data, arranged in a matrix form in a predetermined region of the semiconductor substrate; a plurality of reference cells for generating predetermined potentials to generate a reference potential for evaluating data stored in a memory cell; and a plurality of bit lines through which potentials of the memory cells and the reference cells are read, the bit lines being arranged in parallel with each other, wherein the reference cells are formed in a region near a centerline of the predetermined region of the semiconductor substrate, the centerline being perpendicular to the bit lines, the bit lines form pairs each composed of two adjacent bit lines, two bit lines in each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state, each pair of bit lines has at least one cross section where one of the pair of bit lines crosses the other, to switch between the first parallel state and the second parallel state; and the cross sections are each provided in the predetermined region of the semiconductor substrate such that a length of a bit line in the first parallel state is equal to a length of the bit line in the second parallel state.