Patent ID: 7215196
Filing Date: 2007-05-08
Classification: H03F

Abstract:
1. A multiplier comprising: first, second, third, fourth, fifth, and sixth transistors each having a first terminal, a second terminal, and a third terminal; and a variable impedance circuit, wherein said first terminal of said first transistor receives a first input signal, said second terminal thereof is connected to a first potential via a first load, and said third terminal thereof is connected to said second terminal of said fifth transistor; said first terminal of said second transistor receives a second input signal, said second terminal thereof is connected, to said first potential via a second load, and said third terminal thereof is connected to said second terminal of said fifth transistor; said first terminal of said third transistor receives said second input signal, said second terminal thereof is connected to said first potential via said first load, and said third terminal thereof is connected to said second terminal of said sixth transistor; said first terminal of said fourth transistor receives said first input signal, said second terminal thereof is connected to said first potential via said second load, and said third terminal thereof is connected to said second terminal of said sixth transistor; said first terminal of said fifth transistor receives a third input signal, and said third terminal thereof is connected to a second potential via a first impedance device; said first terminal of said sixth transistor receives a fourth input signal, and said third terminal thereof is connected to said second potential via a second impedance device, and wherein said variable impedance circuit includes a first resistive element, a variable impedance device, and a second resistive element connected in series between said third terminal of said fifth transistor and said third terminal of said sixth transistor and wherein a control voltage is applied to a control terminal of said variable impedance device.