Patent ID: 6173365
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A cache memory system for use in conjunction with a computer system having a primary memory unit and a CPU of the type having a back-off function that can be activated to temporarily halt the CPU when receiving a back-off signal,wherein the cache memory system is capable of enabling the back-off signal in the event that a data read request signal from the CPU is determined to be a miss so as to temporarily halt the CPU, and is capable of disabling the back-off signal after the requested data have been moved from the primary memory unit to the cache memory system; andwherein if the data read request signal is a miss and if the data currently stored in the cache memory module have not been updated, the cache memory system performs the actions of:moving the requested data from the primary memory unit to the cache memory module; and then disabling the back-off signal.