Patent ID: 6999365
Filing Date: 2006-02-14
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a plurality of sense amps configured to compare a voltage caused on a sense line based on data in a memory cell selected from said array of memory cells with a reference voltage applied to a reference sense line to determine said data; and a reference voltage generator shared by said plurality of sense amps and configured to generate said reference voltage applied to said reference sense line, said reference voltage generator including: a reference cell unit containing a reference cell to flow a reference current as a reference for determination of data in said memory cell, and a first current source load to supply a current to said reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting said reference current, and a second current source load to supply a current to said reference transistor; a control amp having a first input terminal connected to a first connection node between said reference cell and said first current source load, a second input terminal connected to a second connection node between said reference transistor and said second current source load, and an output terminal connected to a gate of said reference transistor to negative feedback control said reference transistor; a current source transistor having a gate commonly connected to said gate of said reference transistor, and a drain connected to said reference sense line from said sense amp; and a third current source load connected to said reference sense line.