Patent ID: 6225162
Filing Date: 2001-05-01
Classification: H01L

Abstract:
A method of forming a stacked-gate flash memory cell having a step-shaped floating Poly-Si gate comprising the steps of:providing a semiconductor substrate;forming a gate-oxide layer over said substrate;forming a first polysilicon layer over said gate-oxide layer;forming a mask layer over said pad-oxide layer;patterning and forming an opening in said mask layer to define a floating gate region in said substrate;forming spacers in said opening and to expose said first polysilicon layer in said opening;performing a partial etch of said first polysilicon layer exposed in said opening to form a step-shaped surface on said first polysilicon layer;removing said spacers and said mask layer;forming a step-shaped inter-poly dielectric layer over said substrate including said floating Poly-Si gate with said step-shaped surface;forming a second polysilicon layer over said step-shaped inter-poly dielectric layer;removing said second polysilicon layer and underlying said inter-poly dielectric layer from said substrate, excluding from regions over floating Poly-Si gate, thus forming a Poly-Si control gate having step-shaped surface corresponding to said floating Poly-Si gate with step-shaped surface; andperforming ion implantation to form source and drain of said stacked-gate flash memory cell.