Patent ID: 8730722
Filing Date: 2014-05-20
Classification: G11C

Abstract:
1. A method of operating a non-volatile memory device, the memory device having an array of non-volatile memory cells formed along a plurality of bit lines and a plurality of word lines and, for each of the bit lines, having a corresponding plurality of data latches connected thereto whereby multi-state can be programmed into a selected word line according to data held in the corresponding data latches, the method comprising: receiving a first page of data; storing the received first page of data in a first of the data latches for each of the corresponding bit lines; writing the first page of data from the first of the data latches into a first word line in a binary format; subsequent to storing the received first page of data in the first of the data latches for each of the corresponding bit lines, receiving a second page of data; subsequent to writing the first page of data into the first word line and receiving the second page of data, reading the first page of data from the first word line into a second of the data latches for each of the corresponding bit lines; subsequent to writing the first page of data into the first word line, storing the received second page of data in a third of the data latches for each of the corresponding bit lines, wherein the third of the data latches is different from the second of the data latches for each of the corresponding bit lines; and writing the second page of data from the third of the data latches into a second word line in a binary format, where the second word line is adjacent to the first word line, whereby, subsequent to writing the second page of data into the second word line, the first page of data is held in the second of the data latches for each of the corresponding bit lines and the second page of data is held in the third of the data latches for each of the corresponding bit lines.