Patent ID: 7444571
Filing Date: 2008-10-28
Classification: G01R,G06F

Abstract:
1. A system for testing a target integrated circuit, comprising: a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the target integrated circuit and that analyzes received data from the target integrated circuit; a first interface module that communicates with said host device and that formats said test instructions and data using a first format; a first serializer that serializes said formatted test instructions and data and that is separate from said first interface module; a first deserializer on said target integrated circuit that communicates with said first serializer and that deserializes said test instructions and data; and a control module on the target integrated circuit that communicates with said first deserializer, that interprets said test instructions and data using said first format, that includes a testing module that receives said interpreted test instructions and data from said control module and that performs testing and debugging of said target integrated circuit.