Patent ID: 6593620
Filing Date: 2003-07-15
Classification: H01L

Abstract:
An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions, said integrated circuit comprising:a substrate of a first conductivity type; an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower doping level than said substrate; a plurality of body regions of a second conductivity type within said epitaxial layer in said transistor regions; a plurality of trenches within said epitaxial layer in both said transistor regions and said rectifier regions; a first insulating layer that lines said trenches; a polysilicon conductor within said trenches and overlying the first insulating layer; a plurality of source regions of said first conductivity type within said body regions adjacent to said trenches; a second insulating layer which is disposed over and is in contact with said polysilicon conductor within said transistor regions; and an electrode layer over both said transistor regions and said rectifier regions and which is in contact with said second insulating layer; wherein said integrated circuit contains an epitaxial layer, and wherein said conductive layer is in contact with a portion of said epitaxial layer, in said rectifier region, which has said first conductivity type, and wherein said first and second conductivity types are diverse.