Patent ID: 6177362
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for fabricating a gate structure having gate dielectric layers of different thicknesses, the method comprising:providing a substrate which is divided into a flash memory region, a high voltage (HV) region, and a low voltage (LV) region;forming a first dielectric layer on the substrate;forming a floating gate on the first dielectric layer in the flash memory region;forming in sequence a second dielectric layer, a first conducting layer, and a first protective layer on the first dielectric layer and the floating gate;partially removing the first protective layer, the first conducting layer, the second dielectric layer, and the first dielectric layer until a surface of the substrate in the HV region and the LV region is exposed;forming a third dielectric layer on the substrate in the HV region and the LV region;forming in sequence a second conducting layer and a second protective layer on the substrate after the third dielectric layer is formed;partially removing the second protective layer, the second conducting layer, and the third dielectric layer until the surface of the substrate in the LV region and the first protective layer in the flash memory region are exposed;forming a fourth dielectric layer on the substrate in the LV region;forming in sequence a third conducting layer and a third protective layer on the substrate;defining the second and the third protective layers, the second and the third conducting layers, and the third and the fourth dielectric layers to form a HV gate structure in the HV region and a LV gate structure in the LV region.