Patent ID: 6327196
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A synchronous memory device comprising:an address bus;a control bus;a data bus;a clock terminal adapted to receive a clock signal;a clock enable terminal adapted to receive a clock enable signal;an address decoder coupled to the address bus;a control logic circuit coupled to the control bus;a read/write circuit coupled to the data bus;a memory-cell array coupled to the address decoder, control circuit, andread/write circuit, includinga plurality of row lines;a plurality of pairs of first and second complementary digit lines;an array of memory cells that each have a control terminal coupled to one of the row lines and a data terminal coupled to one of the first and second complementary digit lines of one of the pairs of complementary column lines; anda data delay circuit comprisingan external clock terminal adapted to receive an external clock signal having a first state and a second state,a data terminal adapted to receive a data signal,an adjustable time delay circuit having one or more control inputs each adapted to receive a control signal, the time delay circuit adapted to receive the external clock signal at a clock input and pass a delayed clock signal to an output terminal, the time between when the external clock signal changes states and when the delayed clock signal changes states determined by the control signals received at the control inputs, anda data passing circuit receiving both the data signal and the delayed clock signal, the data passing circuit adapted to pass the data signal from the data terminal to a data output terminal after the delayed clock signal changes from the first to the second state.