Patent ID: 7443981
Filing Date: 2008-10-28
Classification: H04L

Abstract:
1. An execution unit adapted to perform a given round of the Data Encryption Standard, the execution unit comprising: a) a Left Half input; b) a Key input; c) a Table input; d) a first group of transistors configured to receive the Table input, perform a table look-up, and output data; e) a first exclusive-or operator having two inputs and an output, the first exclusive-or operator configured to receive the Left Half input and the Key input; f) a second exclusive-or operator having two inputs and an output, the second exclusive-or operator configured to receive the data output by the first group of transistors and the output of the first exclusive-or operator; and g) a third exclusive-or operator having two inputs and an output, the third exclusive-or operator configured to receive the Left Half input and the data output by the first group of transistors; h) wherein the output of the second exclusive-or operator is used as the Table input for the next round of the Data Encryption Standard; i) wherein the output of the third exclusive-or operator is used as a Right Half input for the next round of the Data Encryption Standard; and j) wherein a Right Half input from the previous round of the Data Encryption Standard is used as the Left Half input for the next round of the Data Encryption Standard.