Patent ID: 6028983
Filing Date: 2000-02-22
Classification: G01R,G06F

Abstract:
Apparatus for testing a microprocessor chip via scan strings having dedicated and non-dedicated sub-scan test pattern strings using a compatible Joint Task Action Group 1149.1 (JTAG) terminal comprising:a) a plurality of computer functional units contained in the chip for operational or design verification testing through the compatible JTAG terminal;b) the compatible JTAG terminal including a test input terminal for receiving the scan string and coupled to each computer functional unit through a first multiplexer;c) the compatible JTAG terminal further including a test output terminal coupled to each computer functional unit through a second multiplexer;d) an instruction register contained in the compatible JTAG terminal for receiving address bits defining the targeted computer functional unit for testing and providing signals to the first multiplexer for routing dedicated sub-scan test pattern strings to the test output terminal;e) means under control of a programmable options register for supplying a dedicated sub-scan test pattern string to each computer functional unit from the first multiplexer; andf) means for providing test results as a scan train at the test output terminal for a targeted computer functional unit from the dedicated sub-scan test pattern string while the non-dedicated sub-scan test pattern strings for non-targeted computer functional units remain in an inactive state.