Patent ID: 6495419
Filing Date: 2002-12-17
Classification: H01L

Abstract:
In a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the complementary metal oxide semiconductor devices each have a gate electrode, the improvement comprising:(a) exposing only a top surface of the gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer, where the protective material layer has an upper surface at a level, by masking the protective material layer and selectively etching through the protective material layer down to the gate electrodes, (b) depositing a capacitive material layer on the monolithic substrate, the capacitive material layer thereby contacting exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices, (c) depositing a top electrode material layer on the monolithic substrate, the top electrode material layer thereby contacting the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices, (d) removing the top electrode material layer and the capacitive material layer to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices, and thereby forming capacitors comprising the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices, (e) forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and (f) forming logic devices of the complementary metal oxide semiconductor devices not included in the selected portion of the complementary metal oxide semiconductor devices.