Patent ID: 8525597
Filing Date: 2013-09-03
Classification: G06F,H03K,H03L

Abstract:
1. A clock frequency overshoot detection circuit, comprising: a clock gating cell for receiving a first clock signal and generating a gated clock signal based on a count signal; a shift register connected to the clock gating cell and including at least two pairs of flip-flops, wherein each pair of flip-flops includes a set flip-flop and a reset flip-flop, and wherein an input terminal of each flip-flop is connected to an output terminal of a previous flip-flop and an output terminal of a last flip-flop is connected to an input terminal of a first flip-flop, and wherein the gated clock signal is provided to respective clock inputs of each of the flip-flops such that an output of each of the flip-flops toggles at each pulse of the gated clock signal, thereby generating an output bit pattern; a comparator, connected to the output terminals of each of the flip-flops, for generating a comparison signal; a latch circuit, connected to the comparator, and having a clock input for receiving the comparison signal and a data input terminal for receiving a predefined logic value, wherein the latch circuit outputs a frequency overshoot indication signal; and a binary counter, connected to the clock gating cell, for generating and providing the count signal to the clock gating cell.