Patent ID: 7929337
Filing Date: 2011-04-19
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: at least one write global bit line connected to a plurality of local bit lines; and at least one read global bit line connected to the plurality of local bit lines, wherein the at least one write global bit line includes a plurality of write global bit lines, and the at least one read global bit line includes a plurality of read global bit lines, at least one write global bit line among the plurality of write global bit lines and at least one read global bit line among the plurality of read global bit lines being adjacent to one another, and the adjacent write global bit line and read global bit line are separated by a first distance, the first distance being longer than one of a second distance separating adjacent write global bit lines among the plurality of write global bit lines and a third distance separating adjacent read global bit lines among the plurality of read global bit lines.