Patent ID: 6794744
Filing Date: 2004-09-21
Classification: H05K

Abstract:
A layout structure for supporting two different package techniques of the central processing units (CPUs), wherein said layout structure is placed in an area where is between a control chip and said CPU, said layout structure comprising:a top signal layer, used to place a first signal line in said area where said CPU is coupled to the control chip; a reference potential providing layer, located below said top signal later, coupled to a reference potential, wherein said the reference potential providing layer provides a first reference potential to said first signal line; a power layer, located below said reference potential providing layer, comprising: a voltage providing area for providing an operating voltage to the CPU and said control chip; and a reference potential providing area, coupled to the reference potential; and a bottom signal layer, located below said power layer, used to placed a second signal line in said area where said CPU is coupled to the control chip, wherein said reference potential providing area in said power layer provides a second reference potential to said second signal line.