Patent ID: 7791921
Filing Date: 2010-09-07
Classification: G11C,H01L

Abstract:
1. An apparatus comprising: a read only memory having an array of bit-lines arranged such that each bit-line has a shared arrangement with one or more other bit-lines to store a plurality of bits, wherein the array includes a plurality of bit-cells, each bit-cell correlated to a different plurality of the bit-lines, the different plurality of the bit lines including a shared arrangement, and each bit-cell coupled to a word line to access the stored plurality of bits, wherein the array is arranged with each bit-cell as an intersection of a row and a column of bit-cells, each bit-cell including a transistor having a gate coupled to the word line, each word line arranged as one row, the transistor of each bit-cell being structured different from the transistor of an adjacent bit-cell coupled to the same word line.