Patent ID: 6836023
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A semiconductor die package comprising:(a) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side; (b) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture; (c) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad; (d) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer; and (e) a solder structure on the widerbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layers, wherein the vertical transistor comprises a power MOSFET comprising a gate region, a source region, and a drain region, wherein the gate region and the source region are at the first side of the semiconductor die, and the drain region is at the second side of the semiconductor die.