Patent ID: 6400641
Filing Date: 2002-06-04
Classification: G11C,H03K,H03L

Abstract:
A method of producing a substantially synchronized, delayed clock signal in response to an input clock signal, comprising the steps of:buffering the input clock signal to produce a buffered clock signal having a first delay relative to the input clock signal; charging a capacitor bank to a charged voltage in response to a first edge of the buffered clock signal; after charging the capacitor bank, controllably discharging the capacitor bank; monitoring the voltage of the capacitor bank; in response to the monitored voltage falling below a threshold voltage, producing an edge of a feedback clock signal; comparing the edge of the feedback clock signal to a second edge of the buffered clock signal; if the edge of the feedback clock signal leads the second edge of the buffered clock signal, increasing the capacitance of the capacitor bank; and if the edge of the feedback clock signal lags the second edge of the buffered clock signal, decreasing the capacitance of the capacitor bank.