Patent ID: 7012296
Filing Date: 2006-03-14
Classification: G11C

Abstract:
1. A semiconductor integrated circuit having a memory cell array comprising: a semiconductor substrate having a main surface; a plurality of word lines formed over said main surface and extending in a first direction; a plurality of bit lines/source lines formed in said semiconductor substrate and extending in a second direction, perpendicular to said first direction; and a plurality of nonvolatile memory cells each of which is formed between adjacent pairs of said bit lines/source lines and below said word lines, and comprises two diffusion layers connected to the corresponding bit lines/source lines, first and second memory transistors and one switch transistor formed between said first and second memory transistors; wherein said switch transistor includes a switch gate electrode, wherein said first memory transistor includes a first memory gate electrode and a first storage area formed between said first memory gate electrode and said main surface, wherein said second memory transistor includes a second memory gate electrode and a second storage area formed between said second memory gate electrode and said main surface, wherein said first and second memory gate electrodes are connected to the same word line, wherein one nonvolatile memory cell shares one of said bit lines/source lines with another nonvolatile memory cell which is neighboring to said one nonvolatile memory cell in said first direction, and wherein said switch gate electrode of said one nonvolatile memory cell is extended along said bit line/source line and is connected to said switch gate electrode of the other nonvolatile memory cell which is neighboring to said one nonvolatile memory cell in said second direction.