Patent ID: 7362606
Filing Date: 2008-04-22
Classification: G11C,H01L

Abstract:
1. A memory cell for interconnection with true and complementary bit lines and read and write word lines, said memory cell comprising: a plurality of field effect transistors (FETS), said FETS forming: wherein: said first inverter is formed by first and second ones of said FETS; said first FET comprises an n-type FET (NFET) and has: said second FET comprises a p-type FET (PFET) and has an oxide layer with a thickness; and said thickness of said oxide layer of said first FET is thicker than said thickness of said oxide layer of said second FET, so as to make said drive current of said first FET lower than a drive current of a comparable NFET having an oxide layer thickness comparable to said thickness of said oxide layer of said second FET.