Patent ID: 7298180
Filing Date: 2007-11-20
Classification: G11C

Abstract:
1. A latch type sense amplifier comprising: a latch unit having a first PMOS transistor and a second PMOS transistor coupled to a power supply, and a first NMOS transistor and a second NMOS transistor serially coupled to the first and second PMOS transistors, respectively, drains of the first PMOS and NMOS transistors being coupled to gates of the second PMOS and NMOS transistors at a data storage node for storing a value, drains of the second PMOS and NMOS transistors being coupled to gates of the first PMOS and NMOS transistors at a complementary data storage node for storing a complementary value; an amplifying unit coupled between the latch unit and a complementary power supply for controlling the latch unit in response to a bit line signal and a complementary bit line signal; and a circuit module for charging or discharging the data storage node and the complementary data storage node in response to a pass-gate signal for passing the bit line signal and the complementary bit line signal to the data storage node and the complementary data storage node, without using a current path across the first or second NMOS transistor, such that the charging or discharging is not affected by a mismatch of electrical characteristics between the first and second NMOS transistors, and wherein the circuit module comprises a third PMOS transistor coupled between the data storage node and the bit line signal and a fourth PMOS transistor coupled between the complementary data storage node and complementary bit line signal, wherein the circuit module comprises a third PMOS transistor and a fourth PMOS transistor serially coupled between the data storage node and the bit line signal for passing the bit line signal to charge or discharge the data storage node without using the current path across the first NMOS transistor.