Patent ID: 6631391
Filing Date: 2003-10-07
Classification: G06F

Abstract:
A parallel computer system comprising a host processor and at least one processor element connected to the host processor via a bus, wherein the host processor and the at least one processor element respectively share and calculate each floating-point arithmetic operation contained in a specific calculation process,the processor element comprising: a floating-point input/output interface section for inputting/outputting floating-point data having a first form composed of a 1-bit sign part, an exponent part having a bit width of me bits and a mantissa part having a bit width of m0 bits; an input data converting section for converting the floating-point data having the first form inputted from the floating-point input/output interface section into floating-point data having a second form composed of a 1-bit sign part, an exponent part having a bit width of me bits and a mantissa part having a bit width of output of m1 bits which is greater than m0; a floating-point operating section, including multiplying means, for executing the floating-point arithmetic operation for the floating-point data of the second form from the input data converting section; and an output data converting section for converting the floating-point data having the second form computed by the floating-point operating section into the floating-point data having the first form and for supplying it to the floating-point input/output interface section.