Patent ID: 6415362
Filing Date: 2002-07-02
Classification: G06F

Abstract:
A method of performing write-through store operations of valid data of varying sizes in a data processing system, where said data processing system includes a plurality of processors that are coupled to an interconnect through a memory hierarchy, where said memory hierarchy includes a plurality of levels of cache, where at least one lower level of cache of said plurality of levels of cache requires write operations of all valid data of at least a predetermined size, said method comprising the steps of:detecting whether or not a write-through store operation is a cache hit in a higher level of cache of said plurality of levels of cache; merging said write-through store operation with data read from said higher level of cache to provide a merged write-through operation of said all valid data of at least said predetermined size to said lower level of cache, in response to detecting a cache hit in said higher level of cache; and writing said merged write-through operation in said lower level of cache, in response to detecting a cache hit in said lower level of cache for said write-through operation, such that the write-through operations of valid data of varying sizes to said lower level of cache which requires write operations of said all valid data of at least said predetermined size are performed with data merged from said higher level of cache.