Patent ID: 7221058
Filing Date: 2007-05-22
Classification: H01L,H05K

Abstract:
1. A chip assembly comprising: a multilayer substrate with alternate layers of insulation layers and wiring layers, wherein the wiring layers are electrically connected through a via-hole for interlayer continuity, the substrate including a through-hole extending through an outermost insulation layer and a plurality of wires that extend into the through-hole, and wherein the through-hole includes a bottom surface; and a semiconductor chip that is flip chip mounted to the substrate, wherein the semiconductor chip includes a bump, wherein the bump is provided within the through-hole, wherein the wires of the substrate are in abutting contact with the bump and are bent toward an axis of the bump for electrical connection therebetween, and wherein a deformed end of the bump abuts against the bottom surface of the through-hole, wherein a space is defined laterally between the wires, and wherein the deformed end of the bump has a lateral width that is greater than the space defined laterally between the wires.