Patent ID: 6112322
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A method for testing oxide integrity in an EEPROM, comprising the steps of:a) programming a test data pattern into at least a portion of an EEPROM memory array addressed by word lines;b) receiving an initiating signal;c) latching a state control bit in response to the initiating signal;d) loading the latched state control bit into a first bit of a shift register to invert the shift register bit;e) using the newly inverted shift register bit to override one or more of a set of decoders each driving one of the word lines, thereby selecting one or more word lines;f) shifting bit values within the shift register by one bit;g) repeating steps e) and f) until all of the word lines for the test data pattern are selected;h) raising a voltage level on the word lines to stress the oxide;i) lowering the voltage level to a level of a positive voltage supply;j) deselecting the selected word lines; andk) reading the test data pattern from the EEPROM memory array to verify proper functionality of the stressed oxide.