Patent ID: 8236643
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a MOS transistor comprising a gate electrode formed above a semiconductor substrate and current input/output regions formed in said semiconductor substrate on both sides of said gate electrode; (b) forming a lower interlevel insulating film on said semiconductor substrate, covering said MOS transistor; (c) forming a capacitor lower electrode above said lower interlevel insulating film; (d) forming a capacitor dielectric film of oxide ferroelectric material on said capacitor lower electrode; (e) forming a first capacitor upper electrode on said capacitor dielectric film, said first capacitor upper electrode being made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2; (f) forming a second capacitor upper electrode on said first capacitor upper electrode, said second capacitor upper electrode being made of conductive oxide having a stoichiometric composition BO (g) forming a third capacitor upper electrode on said second capacitor upper electrode, said third capacitor upper electrode having a composition containing metal of the platinum group, constituting a ferroelectric capacitor; and (h) forming a multilayer wiring structure above said lower interlevel insulating film, covering said ferroelectric capacitor and including interlevel insulating films and wirings, wherein said step (g) forms conductive oxide having a stoichiometric composition CO