Patent ID: 6389527
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A microprocessor comprising:a load/store instruction executing block for executing a load/store instruction; a RAM (Random Access Memory), from and to which said load/store instruction executing block is able to read and write data, said RAM exchanging data with an external memory through a DMA (Direct Memory Access) transfer, said RAM including at least a first and second data storing areas; and a RAM control block for controlling said RAM so that the DMA read/write transfer of data between said second data storing area and said external memory is executed subtantially at the same time as access to said first data storing area by said load/store instruction executing block, and the DMA transfer of data between said first data storing area and said external memory is executed substantially at the same time as access to said second data storing area by said load/store instruction executing block.