Patent ID: 6366511
Filing Date: 2002-04-02
Classification: G11C

Abstract:
A method for checking a semiconductor memory device integrated on a semiconductor chip, which comprises: providing the semiconductor memory device with:a plurality of memory cells each formed on a semiconductor substrate for one binary information value, data lines for reading and writing in information values, gate transistors connected to the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors; wherein an in-chip reference voltage is set to a predetermined normal value during normal operation of the semiconductor memory and, before data are read out of the memory cells, the data lines are precharged to a data line potential; and carrying out the method for checking the semiconductor memory device integrated on a semiconductor chip by:varying the in-chip reference voltage independently of the data line potential; and detecting and weighting the information values read at the varied reference voltage.