Patent ID: 7406640
Filing Date: 2008-07-29
Classification: G01R

Abstract:
1. A method for loading a ring of non-scan latches for a logic built-in self-test comprising: loading a logic built-in self-test value into a scannable latch from the logic built-in self-test; and responsive to loading the logic built-in self-test value into the scannable latch, asserting an override control signal; responsive to asserting the override control signal, forcing a non-scan latch to load the logic built-in self-test value from the scannable latch; and exercising logic paths in the ring of non-scan latches, wherein the non-scan latch is part of the logical paths; and capturing test results from the logic paths and comparing the test results against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.