Patent ID: 6875648
Filing Date: 2005-04-05
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit comprising: producing a p-well into an uppermost surface of a semiconducting substrate; doping a first source dopant region and a first drain dopant region into the uppermost surface of a semiconducting substrate, the first drain and first source dopant regions being lightly doped donor sites; doping a combination drain/source dopant region into the uppermost surface of a semiconducting substrate, the first combination drain/source dopant region being a lightly doped donor site; doping a gate region, the gate region having a higher concentration of donor sites than either of the dopant regions or the drain/source region; depositing polysilicon over the first source dopant region and the first drain dopant region to form emitter polysilicon regions, the emitter polysilicon regions having a higher donor concentration that either of the dopant regions or the drain/source region; fabricating an NMOS transistor from the first drain and combination drain/source dopant regions, the NMOS transistor configured to serve as a select transistor in a memory cell; fabricating an NMOS transistor from the first source and combination drain/source dopant regions, the NMOS transistor configured to serve as a memory transistor in the memory cell; and fabricating bipolar devices in the integrated circuit, the bipolar devices having a breakdown voltage sufficient to withstand a programming voltage of the memory cell.