Patent ID: 8316169
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. A computer system comprising: a first compute element comprising a north chip; an first input/output element connected to the first compute element via a connection mesh fabric, wherein the first input/output element comprises a south chip that stores a translation of a physical bus number to a hierarchical bus number, wherein the physical bus number and the hierarchical bus number identify a bus with which the first device connects to a bridge in the south chip, receives a message from the first device, wherein the message comprises the physical bus number, wherein in response to the message, the south chip replaces the physical bus number with the hierarchical bus number in the message and sends the message to the north chip; a first service processor connected to the first input/output element, wherein the first service processor comprises an inventory controller that receives a bridge identifier of the bridge and a device identifier of the first device from the south chip and in response determines the physical bus number and sends a configuration write command that comprises the physical bus number to the south chip, wherein the south chip receives the configuration write command that comprises the physical bus number from the inventory controller and sends the configuration write command to the first device via the bus identified by the physical bus number, wherein the first device stores the physical bus number in the first device; a plurality of input/output elements comprising a plurality of south chips connected to a plurality of devices, wherein the device identifier of the first device is not unique across the plurality of devices connected to the plurality of south chips; and a plurality of compute elements, wherein the first compute element assigns the first hierarchical bus number to the bus independently of the plurality of compute elements that assign a plurality of hierarchical bus numbers to the bus.