Patent ID: 9019005
Filing Date: 2015-04-28
Classification: G05F,H03K

Abstract:
1. A circuit comprising: a supply terminal configured to receive a supply voltage; a control transistor which has a body region, a first source/drain region, a second source/drain region, a gate insulating region disposed above the body region and a gate region disposed above the gate insulating region, wherein the first source/drain region is coupled to the supply terminal and wherein the gate insulating region has a first layer thickness; a logic circuit comprising an internal supply terminal and a plurality of transistors, each of the transistors having a gate insulating region of a second layer thickness, wherein the internal supply terminal is coupled to the second source/drain region of the control transistor; an inverter comprising an inverter input and an inverter output, wherein the inverter input is coupled to the internal supply terminal of the logic circuit and the inverter output is coupled to the gate region of the control transistor, wherein the inverter comprises at least one transistor with a gate insulating region having a third layer thickness; wherein the first layer thickness, the second layer thickness and the third layer thickness are substantially equal.