Patent ID: 6941335
Filing Date: 2005-09-06
Classification: G06F

Abstract:
1. A computer-implemented method for adding a first floating-point operand to a second floating-point operand such that a fixed-size mantissa result is produced, said method comprising the computer-implemented steps of: in response to the exponent of said second floating-point operand being greater than the exponent of said first floating-point operand; shifting the mantissa of said first floating-point operand with respect to the mantissa of said second floating-point operand such that said first and second floating-point operand mantissas are exponentially aligned to define a least significant non-overlapped portion of said first floating-point operand mantissa; and adding said first floating-point operand mantissa to said second floating-point operand mantissa using a randomly-generated carry-in bit to replace said least significant non-overlapped portion of said first floating-point operand mantissa.