Patent ID: 6389580
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A computer readable storage medium having logic synthesis code means embodied therein, said logic synthesis code means comprising:standard design means for causing a computer to generate standard circuit information about target circuitry on which a logic synthesis function is to be performed, based on specifications of the target circuitry written in a hardware description language, said standard circuit information logically matching said specifications; timing design means for causing the computer to generate modified circuit information by modifying said standard circuit information so that said standard circuit information satisfies both an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in said target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in said target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more other sequential circuits for latching an output of a tristate buffer, which are included in said target circuitry is asserted; and output means for outputting said modified circuit information from said timing design means.