Patent ID: 6085283
Filing Date: 2000-07-04
Classification: G11C

Abstract:
A selective data memory device comprising:a memory cell array composed of a plurality of memory cells arranged into a matrix pattern and divided into a plurality of column blocks; andselected data transferring means for comparing string data inputted from outside of the memory cell array with data in each of the column blocks, selectively marking the column blocks according to the comparison results, and transferring the data in the marked column blocks in sequence to the outside of the memory cell array,wherein the selected data transferring means compares the string data with data in each of the column blocks and selectively marks the column blocks based on the comparison results to indicate the column blocks whose data matches the string data, andthe selected data transferring means then sequentially transfers the data in the marked column blocks so that data is transferred successively from the marked column blocks, which match the string data, without having to compare the string data to the data in the column blocks,wherein a plurality of column blocks are arranged in order, said selected data transferring means is divided into a plurality of column select units in correspondence to a plurality of the column blocks and provided with a data bus extending over a plurality of the column select units, each of the column blocks is provided with a column data line bundle for transferring read data, the column data line bundle is composed of a predetermined column data line and other column data lines, and each of the column select units is provided with a column gate for selectively connecting the column data line bundle to the data bus and a skip and sequential read circuit for controlling the column gate according to data on the predetermined column data line,wherein the skip and sequential read circuit, when data on the predetermined column data line is at a first level, controls connection of the column gate according to a signal applied from a skip and sequential read circuit in the column block immediately before the column block belonging to the current skip and sequential read circuit, outputs a predetermined level signal to the skip and sequential read circuit in the succeeding column block, and when data on the predetermined column data line is at a second level, outputs a signal applied from the skip and sequential read circuit in the preceding column block to the current skip and sequential read circuit in the column block immediately after the column block belonging to the current skip and sequential read circuit, and opens the column gate.