Patent ID: 6252821
Filing Date: 2001-06-26
Classification: G11C

Abstract:
An apparatus comprising:a plurality of group boundary address registers, each of the plurality of group boundary address registers holding a boundary value representing an uppermost address for one of a plurality of groups of memory devices, each of the memory devices in the group having the same configuration;a plurality of comparators, each comparator coupled to one of the plurality of group boundary address registers, each comparator receiving one of the plurality of group boundary values and a portion of a memory access address, and each comparator generating a comparison signal if the group boundary value is larger than the portion of the memory access address;a priority encoder coupled to the plurality of comparators to receive the plurality of comparison signals and generate a group number that represents an addressed group that contains an addressed memory device that contains the memory access address;a group attribute circuit coupled to the priority encoder that provides an attribute value for the memory devices in the addressed group; anda device selection circuit coupled to the priority encoder and the group attribute circuit that provides a device selection signal responsive to the group number and the attribute value.