Patent ID: 8586432
Filing Date: 2013-11-19
Classification: H01L

Abstract:
1. A method for manufacturing a vertical-channel tunneling transistor, the method comprising: providing a semiconductor substrate; forming a first kind of insulation film on the semiconductor substrate; etching the first kind of insulation film to form a pattern; forming a doping region of a first doping type in the semiconductor substrate; etching the semiconductor substrate to form a groove extending from a surface of the substrate to the doping region; covering the groove and the first kind of insulation film to form a second kind of insulation film; covering the second kind of insulation film to form a first kind of conductive film; etching the first kind of conductive film and the second kind of insulation film to form a device gate structure; covering the gate structure to form a gate protection layer; etching the first kind of insulation film to expose the substrate; etching the substrate exposed to form a region for the subsequent development; developing a layer of narrow band gap material selectively; conducting a second type of doping to the narrow band gap material through ion implantation; etching the gate protection layer to form a gate sidewall; depositing a third kind of insulation film to form a device passivation layer; etching the third kind of insulation film to form a contact hole; depositing a second kind of conductive film; etching the second kind of conductive film to form electrodes.