Patent ID: 8665856
Filing Date: 2014-03-04
Classification: H04J,H04L

Abstract:
1. A data processing apparatus, comprising: a scrambling processing unit, configured to generate a Pseudo-Random Binary Sequence (PRBS), perform a modulo-2 addition on the pseudo-random sequence and data frame data, scramble the data frame data comprising first load data, use one section of a part of the pseudo-random sequence on which the modulo-2 addition is performed with the data frame data as an identification sequence, and carry status information corresponding to the identification sequence in frame header information; and a sending unit, configured to send the frame header information carrying the status information and the scrambled first load data; wherein the scrambling processing unit comprises: a first scrambling unit, configured to generate the PRBS, perform the modulo-2 addition on the pseudo-random sequence and the first load data, so as to scramble the first load data; and a first frame header processing unit, configured to use one section of a part of the pseudo-random sequence on which the modulo-2 addition is performed with the first load data as the identification sequence, and add the status information corresponding to the identification sequence to redundant bytes of the frame header information.