Patent ID: 8248464
Filing Date: 2012-08-21
Classification: A61B,H04N

Abstract:
1. An endoscope signal processor comprising: a phase-locked loop circuit in which a phase comparator compares a phase of a variable clock generated in a voltage controlled oscillation circuit with a phase of a reference clock output from an image pickup device incorporated in a detachably connected endoscope to generate a variable clock phase-synchronized with the reference clock; a gate section configured to open or close an input path from the reference clock to the phase comparator; an operation control signal generation section which generates an operation control signal for setting the phase-locked loop circuit in a closed loop operable state during intermittent periods; a sync timing setting section which synchronizes a timing of starting the generation of the operation control signal with a timing of input of the variable clock to the phase comparator at least within a predetermined time period shorter than half of the cycle T of the variable clock; and a sync detection section which performs detection as to whether or not the variable clock is phase-synchronized with the reference clock, wherein, the sync timing setting section sets the predetermined time period so that the timing of starting the generation of the operation control signal is set within a range from T/4 to less than T/2 from the timing of input of the variable clock to the phase comparator so as to operate, when set to an operation state of the closed loop, in a direction to decrease, in terms of frequency, a relative phase difference of the variable clock with respect to the reference clock before the operation state of the closed loop.