Patent ID: 6748556
Filing Date: 2004-06-08
Classification: G06F,G11C

Abstract:
A method to change the thread capacity of a hardware multithreaded computer processing system capable of executing a plurality of threads, said method comprising the steps of:(a) performing a test capable of isolating a failure of a register/array having a plurality of storage elements accessible by only one of said plurality of threads; (b) detecting the failure of the at least one register/array and recording the thread associated with the storage elements of the at least one failed register/array; (c) disabling access to the plurality of storage elements accessible by the only one of said plurality of threads in all register/arrays having data of the only one of said plurality of threads associated with the at least one failed register/array; and (d) maintaining access to all storage elements in the failed and other registers/arrays accessible by other of said plurality of threads not having a detected failure.