Patent ID: 8569146
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. A method for forming an isolation structure for strained channel transistors comprising: forming a pattern mask over a semiconductor substrate, the semiconductor substrate comprising an oxide layer on a strained silicon layer on a silicon-germanium (SiGe) layer; forming a trench in the semiconductor substrate through the pattern mask and through the oxide layer and the strained silicon layer, and partially through the SiGe layer, the trench having sidewall surfaces and a bottom surface between a bottom surface of the SiGe layer and a top surface of the SiGe layer; forming a single nitrogen-containing liner of a single liner material in the trench in direct contact with the trench sidewall surfaces from a bottom surface of the trench within the SiGe layer, through the strained silicon layer to a top of the oxide layer, wherein the nitrogen-containing liner is formed under tensile stress to induce a vertical compressive strain on the strained silicon; filling the trench with a gap filler material, and removing a top portion of the single nitrogen-containing liner so that a topmost remaining exposed surface of the single nitrogen-containing liner is above a bottom surface of the strained silicon layer and below a top surface of the strained silicon layer.