Patent ID: 6519725
Filing Date: 2003-02-11
Classification: G11C

Abstract:
A method comprising the steps of:a) exercising an embedded memory, including writing to at least a plurality of memory locations in the embedded memory test data followed by reading data from said at least a plurality of memory locations, said writing and reading steps each including a plurality of operations; b) simulating the exercising step to generate expected test read data; c) comparing the data read from the embedded memory with the expected test read data; d) providing miscompare data at each occurrence of a miscompare during the comparing step, the miscompare data including at least one location address of said at least a plurality of memory locations corresponding to the miscompare and an operation of a writing step that wrote test data to said at least one location address of said at least a plurality of memory locations corresponding to the miscompare; and e) diagnosing a cause of the miscompare including correlating the miscompare data with known fault signatures.