Patent ID: 7499349
Filing Date: 2009-03-03
Classification: G11C

Abstract:
1. A memory circuit, comprising: a memory cell having a resistance memory element that can be switched between a high-resistance state and a low-resistance state by means of electrical pulses and being connected between a ground terminal and a capacitor; an evaluation device configured to assess the difference between the electrical potentials of the capacitor and a reference capacitor; and a reference memory cell with a reference resistor and connected between the ground terminal and the reference capacitor; the memory cell and the reference memory cell being switched on during the reading operation in order to charge the capacitor and the reference capacitor to a read voltage or in order to discharge the capacitor and the reference capacitor which have been precharged to the read voltage, and the evaluation device assessing the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell, wherein the reference resistor meets the following condition: C BL being one of the capacitance and the reference capacitance, R ON being the resistance of the memory cell in the low-resistance state, and t being the evaluation instant.