Patent ID: 7084792
Filing Date: 2006-08-01
Classification: H03M

Abstract:
1. A circuit for zero offset auto-calibration, connected between a last stage of a pipeline analog-to-digital converter (pipeline ADC) and a differential signal buffer, comprising: an indicator signal generator, connected with said last stage, in response to the output from a comparator array contained in said last stage outputting an indicator signal to indicate whether the output from said pipeline ADC is too high or too low; a calibration voltage generator, connected between said indicator signal generator and said differential signal buffer, outputting an calibration voltage to said differential signal buffer and in response to said indicator signal regulating said calibration voltage within a calibration period decided by a delay signal; and a timing controller, connected with said calibration voltage generator, outputting said delay signal to control the length of said calibration period so that the compensation speed of said pipeline ADC less than the converting delay speed of said pipeline ADC.