Patent ID: 8274827
Filing Date: 2012-09-25
Classification: G11C

Abstract:
1. A memory device on a substrate, comprising a plurality of semiconductor layers stacked on one another on the substrate, wherein each of the semiconductor layers has a plurality of NAND strings, and each of the NAND strings includes a plurality of memory cells and at least a string selection transistor, and each of the NAND strings has a first end and a second end; a plurality of common word lines configured above the semiconductor layers, wherein each of the common word lines is coupled to the memory cells arranged in a same row of the plurality of semiconductor layers stacked on one another; a plurality of common bit lines configured on the common word lines, wherein each of the common bit lines is coupled to the first ends of the NAND strings arranged in the same column of the semiconductor layers; and a common source line configured on the common word lines, wherein the common source line is coupled to the second ends of the NAND strings of the semiconductor layers.