Patent ID: 6057998
Filing Date: 2000-05-02
Classification: H03K

Abstract:
A semiconductor apparatus comprising:a first transistor including a first impurity region of n-type on a semiconductor substrate, a second impurity region of p-type in contact with the first impurity region, and a third impurity region of n-type covered by the second impurity region;a fourth impurity region of p-type in contact with the first impurity region;a second transistor including fifth and sixth impurity regions of n-type covered by the fourth impurity region;a drain terminal connected to the first impurity region;a gate terminal connected to the fifth impurity region of the second transistor;a source terminal connected to the third impurity region;a first switch circuit provided between the gate terminal and the fourth impurity region; anda second switch circuit provided between the source terminal and the fourth impurity region,wherein when the voltage of the gate terminal is negative relative to the voltage of the source terminal, the second switch circuit is ""off"" and the first switch circuit is ""on"",when the voltage of the gate terminal is positive relative to the voltage of the source terminal, the second switch circuit is ""on"" and the first switch circuit is ""off"", andwhen the voltage of the drain terminal is larger than a predetermined positive voltage relative to the source terminal, the second switch circuit is ""off "" and the first switch circuit is ""on"".