Patent ID: 6573577
Filing Date: 2003-06-03
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region, one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein a portion of a periphery of the contact region is partially connected to the channel region, and a portion of the gate electrode on the contact region is extended to be over the groove type element separation structure.