Patent ID: 7638800
Filing Date: 2009-12-29
Classification: G02F

Abstract:
1. A thin film transistor array panel comprising: a gate wire formed on an insulating substrate and including a gate line and a gate electrode connected to the gate line; a gate insulating film covering the gate wire; a semiconductor layer formed on the gate insulating film; a data wire formed on the gate insulating film or the semiconductor layer and including a data line, a source electrode connected to the data line and located on the semiconductor layer and a drain electrode formed on the semiconductor layer and located opposite the source electrode with respect to the gate electrode; a passivation layer covering the data wire; and a pixel electrode including a transparent conductive material or a reflective conductive material and connected to the drain electrode, wherein the gate wire or the data wire comprises a metal film including a conductive material disposed on the insulating substrate or the gate insulating film and an opaque metal oxide film including an oxide of a conductive material disposed on the metal film, wherein the opaque metal oxide film of the gate wire and the data wire block light, and a side of the metal film is uncovered by the opaque metal oxide film.