Patent ID: 9040316
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A method of making a plurality of semiconductor packages, comprising: forming a panel comprising an encapsulating material disposed around a plurality of semiconductor die; measuring an actual position for each of the plurality of semiconductor die within the panel; forming a conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die; forming a plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages; defining a minimum via area; adjusting a nominal footprint of a plurality of conductive vias to account for a misalignment between each semiconductor die and its corresponding package outline and to connect each of the plurality of conductive vias to one of the plurality of first capture pads and one of the second capture pads; and forming each of the plurality of conductive vias with a footprint comprising an area greater than or equal to the minimum via area.