Patent ID: 6313673
Filing Date: 2001-11-06
Classification: H03K

Abstract:
A frequency-dividing circuit, with a frequency division ratio expressed as 1/(2M+K) with K being an integer and M being a natural number greater than or equal to K, for dividing a clock signal having a cycle period of T, comprising:a first delay stage operating in clock synchronization with said clock signal for delaying a supplied first signal by K cycles, K.multidot.T, of said clock signal for outputting a second signal;a second delay stage operating in synchronization with said clock signal for delaying a supplied third signal M cycles, M.multidot.T, of said clock signal for outputting a fourth signal;a feedback means coupled between the first and second delay stages, for receiving said output fourth signal of said second delay stage and generating a feedback signal for feeding back as said first signal to an input of said first delay stage;a logic circuit, receiving said second signal and said feedback signal of said feedback means, for performing a prescribed logical processing on said received signals for supplying said third signal to said second delay stage, wherein a logical level of said third signal output is different when:(a) said received signals are both at a first logical level, than when(b) at least one of said received signals is at a second logical level; andduty control circuitry coupled to said second delay stage for deriving, from said fourth signal, a fifth signal out of phase with said fourth signal by (K/2) cycles, K.multidot.T/2, of said clock signal, andtaking a logical OR of the derived fifth signal and said fourth signal for outputting.