Patent ID: 6131154
Filing Date: 2000-10-10
Classification: G06F

Abstract:
A CPU, capable of processing instructions in an instruction set comprising:an instruction register fetching an instruction from an instruction memory storing said instructions to be processed by said CPU in said instruction set;decode means being supplied with said instruction fetched in said instruction register and decoding said instruction supplied from said instruction register;an execution unit performing an operation of data;a plurality of general purpose registers, each of said plurality of general purpose registers being selected by the decoding of said decode means,wherein the CPU executes one instruction by performing predetermined stages in order while using at least one general purpose register, and when the CPU executes at least two instructions in sequence, the CPU performs the predetermined stages in a pipeline processing,wherein the CPU further comprises a register conflict check circuit checking a conflict of the general purpose registers being used in the pipeline processing,wherein a bit length of said instruction supplied from said instruction register to said decode means is 16 bits,wherein said instruction set has at least one conditional branch instruction and at least one unconditional branch instruction, each of said conditional and said unconditional branch instructions having an area designating a displacement to a jumped address, a bit width of said displacement of said conditional branch instruction being different from a bit width of said displacement of said unconditional branch instruction, andwherein an instruction in said instruction set has an area for designating two general purpose registers from said plurality of general purpose registers.