Patent ID: 7432905
Filing Date: 2008-10-07
Classification: G09G

Abstract:
1. A display device comprising: a pixel portion, and a signal line driver circuit, wherein said signal line driver circuit comprises, a first holding circuit for holding data having digital values, a second holding circuit for holding the data input from said first holding circuit into said second holding circuit, a first decoder circuit for controlling timing of when said holding circuit accepts the date, a second decoder circuit for selecting potentials to be sent to signal lines according to the data, and an analog switch electrically connected to said second decoder circuit, wherein said first decoder circuit comprises three NAND gates each having three inputs and a NOR gate having three inputs corresponding to each of the signal lines, wherein outputs of said three NAND gates are electrically connected to three inputs of said NOR gate, wherein the data corresponding to each of the signal lines is supplied with a plurality of signals, and wherein each of the first holding circuit and the second holding circuit has a plurality of latch circuits, wherein a number of the latch circuits is equal to a number of the bits included in the data corresponding to each of the signal lines, wherein each of the latch circuits includes a clocked inverter and an inverter, wherein both said pixel portion and said signal line driver circuit are formed over a same substrate, and wherein said potentials are created by dividing a potential by resistors.