Patent ID: 7403198
Filing Date: 2008-07-22
Classification: G09G

Abstract:
1. A driving circuit of a liquid crystal display, comprising: a plurality of gate drivers, for selectively driving a plurality of thin film transistors of the liquid crystal display; a plurality of source drivers, for receiving an image signal, the plurality of source drivers cooperating with the plurality of gate drivers to display an image on the liquid crystal display, each of the source drivers further comprising an adjustable common voltage generating circuit, each adjustable common voltage generating circuit compensating a common voltage output from each adjustable common voltage generating circuit to make each common voltage output from each adjustable common voltage generating circuit the same or to make each common voltage output to an ITO layer of a panel of the liquid crystal display the same based on a common voltage adjustable data and a clock signal; and a timing sequence controller comprising a timing sequence control unit and a common voltage adjustable data generating unit coupled to the timing sequence control unit, for providing a control signal and a data flow provided by the timing sequence control unit to the gate drivers and the source drivers, and providing the common voltage adjustable data generated by the common voltage adjustable data generating unit to each adjustable common voltage generating circuit; wherein the common voltage adjustable data generating unit comprises: a processing unit, for obtaining an optimum common voltage data based on an input data to generate the common voltage adjustable data; a storage unit, coupled to the processing unit, for storing the optimum common voltage data; and an interface unit, coupled to the processing unit, for outputting the common voltage adjustable data to each adjustable common voltage generating circuit.