Patent ID: 7368357
Filing Date: 2008-05-06
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a gate electrode on a gate insulating layer on a semiconductor substrate; forming a pair of lightly doped regions separated from each other in the semiconductor substrate and aligned with the gate electrode; forming a dielectric layer on the semiconductor substrate including the gate electrode and removing the dielectric layer to expose upper surfaces of the semiconductor substrate lateral to the gate electrode, thereby forming a spacer on a sidewall of the gate electrode; implanting ions into the exposed upper surfaces of the semiconductor substrate to form a pair of heavily doped regions separated from each other in the semiconductor substrate and partially overlapped with the lightly doped regions; heavily doping the heavily doped regions by implanting additional dopant into the exposed inner surfaces of the semiconductor substrate using the gate electrode and the spacer as a mask; and diffusing the additional dopant in a lateral direction toward the lightly doped regions to form a pair of diffusion source/drain regions enclosing the pair of the lightly doped regions therein.