Patent ID: 6122716
Filing Date: 2000-09-19
Classification: A63F,G06F

Abstract:
A method of authentication for use in a computer system having a first region of memory mapped to a first addressable memory device device and a second region of memory mapped to a second addressable memory device, said method comprising the steps of:a. scrambling accesses to the second region of memory comprises the step of initializing a lock control circuit to cause a bus line scrambler to scramble at least one bus line of at least one bus by which the second addressable memory device is accessed;b. reading a block of data from an address range in the second region of memory;c. ceasing scrambling accesses to the second region of memory wherein said step of ceasing scrambling accesses to the second region of memory comprises the step of asserting a plurality of bus values onto a bus by which the second addressable memory deive is accessed;d. re-reading data from the address range in the second region of memory;e. comparing the block of data re-read from the address range in the second region of memory to the block of data read from the address range in the second region of memory; andf. executing code from the second memory region of memory responsive to the data re-read from the at least one address in the second region of memory being different than the data read from the at least one address in the second region of memory.