Patent ID: 6350671
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate, comprising:forming, on said semiconductor substrate, a plurality of regions projecting from a substrate surface and aligned to one another; forming a fill layer in gaps between said projecting regions; planarizing said fill layer to expose portions of said projecting regions; removing a surface portion of said projecting regions to form holes at the locations of said projecting regions; forming an insulating layer in said holes; selectively removing the insulating layer to form spacers along edges of said holes; depositing at least one conductive layer over the exposed surface of the substrate; patterning the at least one conductive layer by photolithography with a mask; and etching away the at least one conductive layer to define lines and collimate the lines to the underlying regions.