Patent ID: 6944683
Filing Date: 2005-09-13
Classification: G06F

Abstract:
1. A direct memory access (DMA) controller disposed within a processing system, the DMA controller connected to a system data bus (SDB), the system data bus carrying data to a processor connected to the system data bus, the DMA controller further connected to a core memory within the processing system, the DMA controller operable to read from or write to the core memory, the DMA controller operable to read from or write to the SDB, the DMA controller comprising: a first transfer controller running in its own thread of execution independent of another processor disposed with the processing system to carry out data transfers between the system data bus and the core memory, the first transfer controller having a data queue, a first execution unit for transferring data between the core memory and the data queue, and a second execution unit for transferring data between the SDB and the data queue, the second execution unit having at least active and deactivate states; a first outbound transfer instruction, when executed by the first execution unit, causing the first execution unit to transfer data from the core memory to the data queue; and a second outbound transfer instruction, when executed by the second execution unit in the active state, causing the second execution unit to transfer data from the data queue to the SDB.