Patent ID: 7427880
Filing Date: 2008-09-23
Classification: G11C

Abstract:
1. A data line driver for driving a data line in a liquid crystal display apparatus comprising: a gradation voltage generating circuit adapted to generate a plurality of positive-side voltages and a plurality of negative-side voltages; a positive-side decoder adapted to select one of said positive-side voltages in accordance with a video data signal in response to a first polarity signal; a negative-side decoder adapted to select one of said negative-side voltages in accordance with said video data signal in response to a second polarity signal; a sample/hold circuit connected to said positive-side decoder, said negative-side decoder and said data line, said sample/hold circuit selectively sampling and holding output signals of said positive-side decoder and said negative-side decoder; and an intermediate voltage generating circuit connected to said sample/hold circuit, said intermediate voltage generating circuit being adapted to generate an intermediate voltage among said positive-side voltages and said negative-side voltages; said sample/hold circuit comprising: a first sampling switching element connected to the output of said positive-side decoder, said first sampling switching element being adapted to sample the selected one of said positive-side voltages in response to a first sample/hold signal; a second sampling switching element connected to the output of said negative-side decoder, said second sampling switching element being adapted to sample the selected one of said negative-side voltages in response to a second sample/hold signal; a first capacitor connected between an output of said first sampling switching element and an output of said intermediate voltage generating circuit; a second capacitor connected between an output of said second sampling switching element and the output of said intermediate voltage generating circuit; a first transfer switching element connected between the output of said first sampling switching element and a node, said first transfer switching element being turned ON in response to a first control signal analogous to said second polarity signal; a second transfer switching element connected between the output of said second sampling switching element and said node, said second transfer switching element being turned ON in response to a second control signal analogous to said first polarity signal; and a buffer amplifier connected between said node and said data line.