Patent ID: 8344499
Filing Date: 2013-01-01
Classification: H01L

Abstract:
1. A chip-exposed semiconductor device comprising: a semiconductor chip having a gate electrode and a source electrode disposed on a front face and a drain electrode disposed on a back face opposite to the front face, the gate electrode comprising a first gate metal layer and the source electrode comprising a first source metal layer; a second gate metal layer plated atop of the first gate metal layer and a second source metal layer plated atop of the first source metal layer; a first metal contact finger electrically connected the second gate metal layer, the first metal contact finger connecting to a gate terminal extending from a plane substantially coplanar to an upper face of the gate electrode to a plane substantially coplanar to a bottom surface of the drain electrode via an extending structure of the gate terminal; a plurality of second metal contact fingers electrically connected to the second source metal layer, the second metal contact fingers connecting to a source terminal extending from a plane substantially coplanar to the upper face of the gate electrode to a plane substantially coplanar to the bottom surface of the drain electrode via an extending structure of the source terminal; a molding material encapsulating the semiconductor chip, the first contact metal finger and the second contact metal finger wherein the bottom surface of the drain electrode is exposed through the molding material.