Patent ID: 7948000
Filing Date: 2011-05-24
Classification: G02B,H01L,Y10T

Abstract:
1. A system for hermetically sealing devices, the system comprising: a substrate comprising: a plurality of individual chips, wherein each of the plurality of individual chips includes a plurality of devices and wherein each of the plurality of individual chips is arranged in a spatial manner as a first array configuration, the first array configuration including a first separation region extending in a first direction between each of the plurality of individual chips and a second separation region extending in a second direction between each of the plurality of individual chips, the first direction being oriented at an angle with respect to the second direction; and one or more bond pads located in the first separation region and the second separation region, wherein each of the one or more bond pads are associated with each of the plurality of individual chips and are in electrical communication with the plurality of devices in each of the plurality of individual chips; a transparent member of a predetermined thickness, the transparent member including a plurality of recessed regions within the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array, and wherein each of the plurality of recessed regions are bordered by a standoff region having a thickness defined by a portion of the predetermined thickness; and a hermetically sealed interface between the standoff region and the first separation region and the second separation region, wherein the hermetically sealed interface is adapted to enclose each of the plurality of individual chips within one of the plurality of recessed regions and maintain the one or more bond pads at a location external to the one of the plurality of recessed regions.