Patent ID: 9112631
Filing Date: 2015-08-18
Classification: H04J

Abstract:
1. A method of synchronising the frequency of an oscillator in a slave device to the frequency of a master clock in a master device, the method including the steps of: a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the precise time of sending of said first message and a first correction value which is the cumulative delay encountered by the message during its passage from the master device to the slave device; b) extracting said time-stamp and said correction value from said first message and recording a first value of a counter in the slave device at the time of receipt of the first message; c) receiving in the slave device a further message from said master device having a second time stamp which is a time-stamp of said master clock indicating the precise time of sending of said further message and a second correction value which is the cumulative delay encountered by the message during its passage from the master device to the slave device; d) extracting said time-stamp and said correction value from said further message and recording a further value of the counter in the slave device at the time of receipt of the further message; e) determining an error signal which is representative of the difference between the first time-stamp and the further time-stamp and the first value of the counter and the further value of the counter, adjusted by the difference between the first correction value and the further correction value; and f) adjusting the frequency of the oscillator based on said error signal.