Patent ID: 6406985
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method of fabricating a buried contact, the method comprising:providing semiconductor substrate, the substrate comprising a shallow trench isolation; forming a gate oxide layer on the substrate and a polysilicon layer on the gate oxide layer; patterning the polysilicon layer and the gate oxide layer to expose a portion of the substrate; forming a diffusion region in the exposed substrate; forming an amorphous silicon layer on the polysilicon layer and the diffusion region; forming an anti-reflection coating layer on the amorphous silicon layer; patterning the anti-reflection coating layer and the amorphous silicon layer to expose a portion of the polysilicon layer; forming a spacer on a sidewall of the patterned anti-reflection coating layer and the patterned amorphous silicon layer; forming a gate by etching the exposed polysilicon layer and the underlying gate oxide layer until the substrate is exposed using the remaining anti-reflection coating layer and the spacer as a mask; and forming a source/drain region in the exposed substrate.