Patent ID: 8871587
Filing Date: 2014-10-28
Classification: H01L

Abstract:
1. A process of forming a complementary metal oxide semiconductor (CMOS) integrated circuit, comprising steps: providing a semiconductor substrate; providing a first polarity MOS transistor formed in and on said substrate, said first polarity MOS transistor being an NMOS transistor, including: providing a second polarity MOS transistor formed in and on said substrate in an area separate from said first polarity MOS transistor, said second polarity MOS transistor being a PMOS transistor, including: forming a first stressor layer of silicon nitride over said first polarity MOS transistor and said second polarity MOS transistor, said first stressor layer having a tensile stress level between 1×10 removing a portion of said first stressor layer from over said second polarity MOS transistor using an aqueous phosphoric acid solution so that between one fourth and one half of said first stressor layer remains over said second polarity MOS transistor; forming a second stressor layer over said first polarity MOS transistor and said second polarity MOS transistor, said second stressor layer having a compressive stress level between 1×10 with said first stressor layer over the first MOS gate and said second stressor layer over both the first MOS gate and the second MOS gate, performing an anneal operation on said CMOS integrated circuit using a scanning laser anneal tool, such that: removing said first stressor layer and said second stressor layer from over said first polarity MOS transistor and said second polarity MOS transistor using an aqueous phosphoric acid solution.