Patent ID: 6329693
Filing Date: 2001-12-11
Classification: H01L,Y10S

Abstract:
A semiconductor memory device having a semiconductor substrate defining a main surface, and a peripheral circuit region and an SRAM memory cell region in the main surface, comprising:a first well, a second well of a first conductivity type, a third well of a second conductivity type, a device element isolation structure, an embedded layer of the second conductivity type, a driver transistor, a load transistor and an impurity region of the second conductivity type,wherein the first well is formed in the peripheral circuit region,the second well is formed in the memory cell region,the second well is shallower than the first well,the driver transistor is formed in the second well,the impurity region is formed in the second well,the impurity region is a drain of the driver transistor,the impurity region is an element that composes a cell node,the third well is formed in the memory cell region,the third well is shallower than the first wellthe load transistor is formed in the third well,the device element isolation structure is formed in the memory cell region,the device element isolation structure isolates the driver transistor from the load transistor,the second well and the third well are formed to extend to a location under the device element isolation structure,the embedded layer is formed under the second well and below an area where at least the impurity region is located,the embedded layer forms a junction with the second well, andthe embedded layer is fixed at a potential that prevents carriers of the second conductivity type in the embedded layer from flowing into the second well.