Patent ID: 8847302
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A three dimensional memory device, comprising: a substrate; a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate; at least one charge storage region located adjacent to semiconductor channel; and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; wherein each of the plurality of control gate electrodes comprises: wherein: the semiconductor channel has a pillar shape having a solid or hollow circular cross section when viewed from above; and the entire pillar-shaped semiconductor channel extends substantially perpendicular to the major surface of the substrate; and further comprising: one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above; another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below; a first select gate electrode located adjacent to a top portion of the semiconductor channel below the one of source or drain electrode; and a second select gate electrode located adjacent to a bottom portion of the semiconductor channel above the another one of source or drain electrode.