Patent ID: 6819134
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A decoding circuit for a wafer burn-in test, comprising:an address control unit for buffering a plurality of externally inputted address signals and generating a plurality of internal address signals in order to selectively enable word line driving signals during the wafer burn-in test; a strobe signal generating unit for generating a plurality of delay pulse signals having a predetermined pulse width according to the plurality of address signals, and generating a strobe signal by logically operating the plurality of delay pulse signals wherein each delay pulse signal is enabled when its corresponding address signal inputted externally is transited, and the strobe signal has a pulse when at least one delay pulse signal is enabled; and a decoding unit for decoding the plurality of internal address signals according to the strobe signal from the strobe signal generating unit, and selectively outputting the word line driving signals.