Patent ID: 7120745
Filing Date: 2006-10-10
Classification: G06F

Abstract:
1. A cache memory device comprising: a cache memory that includes a plurality of first memories for storing tags and a second memory for storing data, and employs a set associative scheme having a plurality of ways, the first memories being logically configured in columns and rows, a number of the columns corresponding to a number of the ways, each of the first memories having an entry for storing an allocated tag and an area for storing error correction information; and an allocation unit that, when a number of ways is changed, multiplies a number of indexes in the cache memory by the number of ways to obtain a result of multiplication, defines the result as the total number of entries, and allocates the tags to the respective entries so that the total number of entries is made constant by adjusting the number of indexes depending on the change of the number of ways, wherein logical configuration of the first memories is changed so as to have columns corresponding to the number of the ways changed, keeping a total number of the first memories constant.