Patent ID: 8248852
Filing Date: 2012-08-21
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a first address decoder comprising a plurality of transistors disposed in a first region, wherein the first address decoder is associated with a first memory block; a second address decoder comprising a plurality of transistors disposed in a second region that is electrically isolated from the first region, wherein the second address decoder is associated with a second memory block; a memory cell array including the first and second memory blocks, wherein the memory cell array comprises a plurality of memory cells disposed between the first address decoder and the second address decoder; and a switch circuit comprising a negative voltage line switch circuit configured to provide a negative voltage to one of the first address decoder and the second address decoder based on block address information that specifies an address included in one of the first memory block and the second memory block, wherein the first address decoder comprises a first block selector configured to receive the negative voltage and enable the first memory block based on the block address information, wherein the second address decoder comprises a second block selector configured to receive the negative voltage and enable the second memory block based on the block address information, wherein one of the first block selector and the second block selector is configured to be enabled based on the block address information, and wherein the first block selector comprises: a first block selection switch configured to drive the first memory block in response to a voltage of a first block word line; a first pull-up circuit configured to provide a high voltage to the first block word line in response to a first enable signal; a first pull-down circuit configured to provide the negative voltage to the first block word line in response to a complementary signal of the first enable signal; and a first block address decoder configured to receive the block address information and generate the first enable signal in response thereto.