Patent ID: 7696087
Filing Date: 2010-04-13
Classification: H01L

Abstract:
1. A method of forming a dual damascene pattern of a semiconductor device, the method comprising: forming an insulating layer over a semiconductor substrate on which elements of the semiconductor device are formed; forming a contact hole in the insulating layer; forming a passivation layer over the insulating layer and within the contact hole; forming a hard mask pattern over the passivation layer, wherein the hard mask pattern exposes the contact hole; forming a first trench by etching a portion of the passivation layer and a portion of the insulating layer using a first etch process employing the hard mask pattern as an etch mask; etching the passivation layer using a second etch process employing the hard mask pattern as an etch mask, wherein the passivation layer is gap-filled within the contact hole; forming a second trench by etching a portion of the insulating layer using a third etch process employing the hard mask pattern as an etch mask, thereby forming a third trench comprising the first trench and the second trench; and removing the third hard mask pattern and the passivation layer.