Patent ID: 7425852
Filing Date: 2008-09-16
Classification: H03L

Abstract:
1. A phase-locked loop for frequency synthesis having a phase or phase frequency detector, a controllable oscillator, a loop filter, and a frequency divider, a. the phase-locked loop comprising a reference oscillator or being connectable to a reference oscillator, the reference oscillator being implemented to generate a reference clock signal and output it to a reference input of the phase or phase frequency detector, b. the controllable oscillator: c. the frequency divider being implemented: d. the phase or phase frequency detector being implemented: e. the loop filter being implemented to generate a control signal, by filtering the comparison signal output by the phase or phase frequency detector, and output it to the controllable oscillator, characterized in that: A. the phase-locked loop has a memory for a control value, which is connectable to the control input of the controllable oscillator via a first switch, which is switchable as a function of a first switching signal, and is implemented to output a stored control value, and B. the frequency divider is connectable at its output via a second switch, which is switchable as a function of a second switching signal, to the reference oscillator.