Patent ID: 7191315
Filing Date: 2007-03-13
Classification: G06F

Abstract:
1. In a microprocessor having a plurality of physical registers, a method for managing said plurality of physical registers, said method comprising steps of: providing a first structure for holding information identifying available physical registers that are free to be assigned as a destination operand for instructions executing on the microprocessor, said destination operand identifying where data resulting from an operation is to be stored; storing a physical register assignment in a second structure noting that a selected one of the physical registers is assigned as a destination operand for an architectural register of a selected instruction executing on the microprocessor; transferring said physical register assignment of said selected physical register from said second structure to a third structure after retirement of said selected instruction, the third structure holding information regarding a plurality of physical register assignments; assigning said architectural register as a destination operand for a subsequent instruction; and prior to the retirement of said subsequent instruction, transferring information identifying said selected physical register as soon-to-be available from said third structure to said first structure.