Patent ID: 6166967
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A multi-bank testing apparatus for a synchronous DRAM consisting of a plurality of banks, comprising:a row address strobe generating unit for generating a signal adapted to simultaneously enable all of word lines having a same row address of each bank each bank to transmit data from cells to bit line sense amplifiers in each bank of said synchronous DRAM;a column address strobe generating unit for generating a signal adapted to enable transistors respectively adapted to simultaneously coupled bit lines having a same column address of each bank and carrying data, amplified by said bit line sense amplifiers, to local data bus lines;input/output sense amplifiers for amplifying data on said local data bus lines, respectively;input/output sense amplifiers for amplifying data on said local data bus lines, respectively;a transmission gate unit for controlling transmission of data from said input/output sense amplifiers to global read data bus lines; andan input/output comparing unit for compressing data from said input/output sense amplifiers prior to said transmission thereof to said global read data bus lines.