Patent ID: 6515326
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A semiconductor memory device comprising:(a) a semiconductor substrate with an isolation dielectric; the isolation dielectric defining active regions on the substrate; (b) a memory cell section formed on the substrate; the memory cell section including floating-gate type transistors formed in the active regions; each of the transistors having a first gate dielectric, a floating gate formed on the first gate dielectric, a second gate dielectric formed on the floating gate, and a control gate formed on the second gate dielectric; and (c) a capacitor section formed on the substrate; the capacitor section including capacitors formed on the isolation dielectric of the substrate; each of the capacitors having a lower electrode formed on the isolation dielectric, a capacitor dielectric formed on the lower electrode, and an upper electrode formed on the capacitor dielectric; a first part of the capacitors being designed to be applied with a first voltage and a second part of the capacitors being applied with a second voltage on operation, where the first voltage is lower than the second voltage; each of the first part of the capacitors having a recess formed on the lower electrode, thereby increasing its capacitance.