Patent ID: 7093106
Filing Date: 2006-08-15
Classification: G06F

Abstract:
1. A method for using a single shared rename register (RR) array in a simultaneous multithread (SMT) processor comprising the steps of: configuring said RR array with a separate complete thread bit (CTB) for a thread zero and for a thread one at each register of said RR array corresponding to a pointer address (PTR); assigning a first instruction a first register in said RR array corresponding to a first PTR and setting a corresponding first valid bit at said first PTR to indicate a valid state, said first register also having a first CTB with a current logic state corresponding to a thread of said first instruction; and flipping said current logic state of said first CTB in said RR array to its opposite logic state when said first instruction completes and setting said first valid bit to a not valid state.