Patent ID: 6137745
Filing Date: 2000-10-24
Classification: G11C

Abstract:
An embedded memory control circuit for use on a memory module of a plurality of memory chips partitioned into a plurality of banks of which one or more might be defective for the purpose of controlling the access operation to the memory module; the access operation utilizing a plurality of bank-select signals to select requested banks and a plurality of word-line driving signals to drive a word-line driving unit coupled to the memory module;the embedded memory control circuit comprising:a bank-select unit which is capable of detecting whether each of the banks in the memory module is defective or nondefective to thereby generate a plurality of corresponding bank-status signals each indicative of whether the corresponding bank is defective or nondefective;a bank-suppress unit, responsive to the bank-status signals and the bank-select signal, for generating a plurality of defective-bank suppressing signals which can suppress each defective bank in the memory module, if any;a bank-active unit, responsive to the defective-bank suppressing signals from the bank-suppress unit and the word-line driving signals, for generating a plurality of bank-activation suppressing signals which cause the word-line driving circuit to act in response to the current request; anda data output buffer, responsive to the defective-bank suppressing signals from the bank-suppress unit, for performing an access operation to the memory module with all the defective banks, if any, being suppressed by the defective-bank suppressing signals.