Patent ID: 7743184
Filing Date: 2010-06-22
Classification: G06F

Abstract:
1. A method, comprising: receiving at a first time a first write request comprising a first data and a first address value, wherein the first address value is received at a first set of address nodes; determining if the first address value is associated with one of a plurality of coherent access registers, wherein each one of the plurality of coherent access registers is to receive data from a plurality of write requests simultaneously; storing, in response to determining that the first address value is associated with a first register of the plurality of coherent access registers, the first data at a latch coupled to each of the plurality of coherent access registers; receiving at a second time after the first time a second write request comprising a second data and a second address value, wherein the second address value is received at the first set of address nodes; storing the second data at a second register while maintaining the first data at the latch in response to determining the second address value is not associated with any of the plurality of coherent access registers; receiving at a third time after the second time a third write request comprising a third data and a third address value, wherein the third address value is received at the first set of address nodes; and simultaneously storing, in response to determining that the third address value is associated with the first register of the plurality of coherent access registers, the first data stored at the latch and the third data at the first register of the plurality of coherent access registers.