Patent ID: 6834255
Filing Date: 2004-12-21
Classification: G06F,G11C,H03L,H04L

Abstract:
A timing control device for the compensation of timing errors in multiple channel devices comprising at least one register, the device comprising:a clock for providing a clock signal to each said at least one register; a reference signal generator for providing a reference signal applicable through a reference channel to said register, for deskewing the register's channels with respect to said reference signal; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's channels timing in relation to the reference signal, said feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence of symbols transmitted through the reference channel; and a set of delay means which uses the determined information on deviation from the predetermined level of said probability to generate a feedback signal to compensate timing errors in said register.