Patent ID: 6388318
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A semiconductor device comprising four chips each having on its surface a memory circuit and a plurality of pads including a plurality of address pads for use in inputting address signals of said memory circuit along with a plurality of input/output pads for inputting and outputting input/output data and also having a pair of long sides and a pair of short sides, a substrate supporting thereon said four chips and having on its surface a plurality of pads including address pads and input/output pads as electrically connected to respective ones of the address pads and input/output pads of said four chips, and a plurality of external terminals being electrically connected to the address pads and input/output pads on said substrate and including address terminals and input/output terminals as provided on a bottom surface of said substrate,said four chips are disposed on said substrate in form of an array of rows and columns, the plurality of address pads of each of said four chips are disposed adjacent to one side of said pair of short sides, said plurality of input/output pads are disposed and spaced apart from one side of said pair of short sides toward the other side of said pair of short sides when compared to said plurality of address pads, one of the pair of short sides of each of said four chips is disposed adjacent to one of the pair of short sides of its neighboring chip to permit the plurality of address pads of each of said four chips are placed at central part on a plane of said substrate, corresponding pads in the plurality of address pads of each of said four chips are commonly connected together to said address terminals of said external terminals, and the plurality of input/output pads of each of said four chips are connected to said input/output terminals of said external terminals independently of one another in units of respective chips.