Patent ID: 8089114
Filing Date: 2012-01-03
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: a semiconductor substrate; an isolation layer on the semiconductor substrate wherein the isolation layer defines a first active region of the semiconductor substrate, and wherein the isolation layer defines a second active region of the semiconductor substrate separated from the first active region; a first tunnel insulation layer on the active region of the semiconductor substrate; a first charge storage pattern on the tunnel insulation layer so that the tunnel insulation layer is between the charge storage pattern and the active region of the semiconductor substrate; a first interface layer pattern on the charge storage pattern so that the charge storage pattern is between the tunnel insulation layer and the interface layer pattern; a blocking insulation pattern on the interface layer pattern so that the interface layer pattern is between the charge storage pattern and the blocking insulation pattern, wherein the block insulation pattern comprises a high-k dielectric material and wherein the interface layer pattern and the blocking insulation pattern comprise different materials; a control gate electrode on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode; a second tunnel insulation layer on the second active region of the semiconductor substrate; a second charge storage pattern on the second tunnel insulation layer so that the second tunnel insulation layer is between the second charge storage pattern and the second active region of the semiconductor substrate; and a second interface layer pattern on the second charge storage pattern so that the second charge storage pattern is between the second tunnel insulation layer and the second interface layer pattern, wherein the first and second interface layer patterns each comprise a conductor material and/or a semiconductor material, and wherein the first and second interface layer patterns are separate; wherein the control gate electrode extends continuously across the first and second active regions so that the first charge storage pattern is between the control gate electrode and the first active region of the semiconductor substrate and the second charge storage pattern is between the control gate electrode and the second active region of the semiconductor substrate.