Patent ID: 6344992
Filing Date: 2002-02-05
Classification: G11C

Abstract:
A static random access memory (SRAM) comprising a memory cell array including a plurality of four-transistor memory cells arranged in a matrix, each of aid memory cells operating for reading/writing data in a read/write mode or maintaining data in a precharge mode based on an off-leak current, a plurality of word lines each disposed for a corresponding row of said memory cells, a plurality of pairs of bit lines each disposed for a corresponding column of said memory cells for supplying said off-leak current, a reference voltage generator for generating a reference voltage, an impedance converter for receiving the reference voltage to deliver a precharge voltage having a lower internal impedance compared to the reference voltage, a word line driver disposed for each of said word lines for switching a corresponding one of said word lines between a read/write potential for said read/write mode and a precharge voltage for said precharge mode.