Patent ID: 9219050
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A semiconductor package comprising: (a) a first chip having oppositely-directed front and rear surfaces, left and right edges spaced apart from one another in a lateral direction and bounding the front and rear surfaces; and left and right columns of contacts at the front surface extending in a column direction transverse to the lateral direction; and (b) interconnect pads overlying the front surface of the first chip, the interconnect pads being connected to at least some of the contacts, the interconnect pads and the contacts or the interconnect pads alone forming an array of external connection elements such that a first set of the external connection elements including at least some contacts of the right column or interconnect pads connected to contacts of the right column is disposed to the left of a second set of the external connection elements including at least some contacts of the left column or interconnect pads connected to contacts of the left column; (c) a package substrate, the first chip being disposed above the package substrate with the front surface of the first semiconductor chip facing upwardly away from the package substrate; (d) left leads extending from the first set of the external connection elements over the left edge of the first semiconductor chip to the package substrate; (e) right leads extending from the second set of the external connection elements over the right edge of the first semiconductor chip to the package substrate, the package further comprising a second chip having oppositely-directed front and rear surfaces, left and right edges spaced apart from one another in a lateral direction and bounding the front and rear surfaces; and contacts at the front surface, the first and second chips being disposed in a stack with the rear surfaces of the chips facing one another, the front surface of the second chip facing downwardly toward the package substrate so that the left edge of the first chip and the right edge of the second chip define a left side of the stack and the right edge of the first chip and the left edge of the second chip define a right side of the stack, wherein the package substrate has a plurality of terminals for electrically connecting the package with a component external to the package, the terminals including common terminals, each common terminal being electrically coupled with a contact of the first chip and a contact of the second chip, wherein at least some of the common terminals are electrically coupled with at least some of the contacts on the first chip through the left and right leads, wherein at least some of the electrical connections between the common terminals and contacts of the first chip include the interconnect pads.