Patent ID: 7328418
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. A method of operating a semiconductor processing system comprising: receiving a wafer comprising a soft mask layer and a bottom anti-reflective coating (BARC) layer; receiving reference metrology data for at least one isolated structure on the wafer, at least one nested structure on the wafer, soft mask data, and BARC data; determining a first value comprising measured size data for the at least one isolated structure on the wafer; determining a second value comprising measured size data for the at least one nested structure on the wafer; comparing the first value with the second value; executing an Iso-Greater control strategy when the first value is greater than the second value, wherein the Iso-Greater control strategy comprises an Iso/Nested control plan for controlling an iso/nested etching process and at least one of a Trim Control plan for controlling a trimming process and a BARC open control plan for controlling a BARC etching process, wherein the Iso/Nested control plan for controlling the iso/nested etching process comprises: determining a first desired target value for the iso/nested etching process, the first desired target value comprising a desired feature size after performing the iso/nested etching process, calculating a first iso-trim value using a difference between the first value and the first desired target value, calculating a first dense-trim value using a difference between the second value and the first desired target value, calculating a first ratio using the first iso-trim value and the first dense-trim value, and executing the iso/nested etching process on the wafer, wherein recipe settings for achieving the first desired target value have been determined using the calculated first ratio, determining a first final critical dimension (CD) target, calculating a first trim value using a difference between the first final CD target and the first desired target value, and executing a first trim process, wherein recipe settings for achieving the first final CD target have been determined using the first trim value; and executing a Nes-Greater control strategy when the first value is less than the second value, wherein the Nes-Greater control strategy comprises an Iso/Nested control plan for controlling an iso/nested deposition process and at least one of a Trim Control plan for controlling a trimming process and a BARC open control plan for controlling a BARC etching process, wherein the Iso/Nested control plan for controlling the iso/nested deposition process comprises: determining a second desired target value for the iso/nested deposition process, the second desired target value comprising a desired feature size after performing the iso/nested deposition process, calculating a second iso-trim value using a difference between the first value and the second desired target value, calculating a second dense-trim value using a difference between the second value and the second desired target value, calculating a second ratio using the second iso-trim value and the second dense-trim value, and executing the iso/nested deposition process on the wafer, wherein recipe settings for achieving the second desired target value have been determined using the calculated second ratio, determining a second final critical dimension (CD) target, calculating a second trim value using a difference between the second final CD target and the second desired target value, and executing a second trim process, wherein recipe settings for achieving the second final CD target have been determined using the second trim value.