Patent ID: 7573767
Filing Date: 2009-08-11
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device in which a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines, comprising: a plurality of unit blocks into which the memory cell array is divided; a plurality of rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in said unit block and each including a plurality of sense amplifiers for amplifying data of the memory cells for each bit line pair; switch means for switching a connection state between said unit block and said row of sense amplifiers attached to said unit block; and control means for controlling said switch means so as to form a transfer path from said row of sense amplifiers attached to a predetermined said unit block leading to said row of sense amplifiers as a saving destination not attached to the predetermined said unit block, in a state in which said row of sense amplifiers attached to the predetermined said unit block is controlled to be used as a cache memory, for performing a saving operation so that the stored data in the cache memory is saved in said row of sense amplifiers as the saving destination through the transfer path, and for performing a write back operation so that the stored data is written back into the cache memory through the transfer path in reverse direction.