Patent ID: 6306763
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A semiconductor fabrication process, comprising:forming a conductive gate structure dielectrically spaced over a semiconductor substrate, wherein said semiconductor substrate comprises an active region laterally disposed between a pair of isolation structures, and wherein the conductive gate structure is aligned over a channel region laterally disposed between a pair of source/drain regions within the active region;implanting a silicon bearing species into said conductive gate structure and into said source/drain regions to form amorphous silicon-rich regions proximal to respective upper surfaces of said source/drain regions and said conductive gate structure, wherein an implant energy of said implanting a silicon bearing species is in the range of approximately 10 to 15 keV;implanting a nitrogen bearing species into said conductive gate; andintroducing a source/drain impurity distribution into said source/drain regions, wherein said introducing a source/drain impurity distribution comprises implanting a heavily doped impurity distribution into said source/drain regions.