Patent ID: 6281545
Filing Date: 2001-08-28
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a doped semiconductor substrate including a channel region therein,a tunnel oxide layer formed above said substrate,a doped first polysilicon layer over said tunnel oxide layer, said first polysilicon layer and said tunnel oxide layer patterned into a pair of floating gate stacks of a tunnel oxide layer and said first polysilicon layer formed into floating gate electrodes located over said channel region and above said substrate,said floating gate stacks comprising a pair of spaced apart stacks of floating gate electrodes and tunnel oxide layers with sidewalls, with said floating gate stacks having a hollow gap therebetween,a first thin dielectric layer covering the top and sidewalls of said floating gate electrodes, said tunnel oxide layer and said substrate, leaving said hollow gap between said floating gate electrodes substantially undiminished in depth,a second polysilicon layer over said first thin dielectric layer,a silicide layer over said second polysilicon layer,a dielectric cap layer covering said silicide layer,a control gate electrode spanning across said pair of floating gate electrodes in a control gate electrode stack formed of said silicide layer and said second polysilicon layer, said control gate electrode filling said hollow gap between said floating gate stacks above said channel region,source/drain regions formed in said substrate below the level of said control gate electrode stack, and located aside from said channel and said gate electrode stack and self-aligned with said control gate electrode,said control gate electrode and said floating gate electrodes patterned from said tunnel oxide layer forming a split-gate structure above said channel region in said substrate with two separate floating gate electrode structures under one control gate electrode.