Patent ID: 6127863
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A fractional divider for generating an output frequency that is a ratio M/(2.sup.N +K) of an input clock frequency, comprising:N full-adders, each full-adder having a carry-in input terminal, an addend input terminal, a frequency control input terminal, an output terminal, and a carry-out output terminal, wherein the carry-out output terminal is coupled to the carry-in input terminal of the next full-adder;N first registers, each first register coupled between the output terminal and the addend input terminal of each corresponding N full-adder; anda plurality of second registers, each second register coupled between the carry-out output terminal and the frequency control input terminal of selected ones of the N-full adders to form feedback paths, wherein the output frequency is taken from the output of the last of the N first registers.