Patent ID: 6665774
Filing Date: 2003-12-16
Classification: G06F

Abstract:
A computer system comprising:a common memory, the memory having a plurality of sections; and a scalar/vector processor coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus, the processor having a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word, the processor comprising: a scalar/vector cache unit, the cache unit including: a cache array, and a FIFO unit that tracks an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory, and a destination code that specifies which of the scalar registers and vector registers into which the read-data value is to be loaded when the read-data value is returned from the memory.