Patent ID: 7290118
Filing Date: 2007-10-30
Classification: G11C

Abstract:
1. A memory storage device, comprising: memory cells; an address control system configured to decode a bit number which identifies a number of the memory cells selected in parallel, wherein the number of the memory cells selected in parallel correspond to least significant bits of an address which has a range that includes the memory cells wherein the address control system comprises bit select logic configured to decode the bit number into address select bits wherein the bit select logic includes conversion logic configured to convert the bit number into a bit select number which is equal to a logarithm of the bit number with respect to a base two and select logic configured to enable a number of address select bits which are equal to the bit select number, wherein each address select bit corresponds to a bit of the address, and wherein the number of address select bits enabled correspond to the least significant bits of the address; and a decoder configured to decode the address into column enable outputs, wherein the address select bits enable the column enable outputs which correspond to the least significant bits of the address.