Patent ID: 8977878
Filing Date: 2015-03-10
Classification: G06F,G11C,Y02D

Abstract:
1. A digital computing system comprising: a central processing unit operable to perform data processing operations under program control; a memory mapped register including a sleep mode enable bit having one of a sleep mode enable state and a sleep mode disable state; a L1 program memory connected to said central processing unit storing program code capable of controlling said central processing unit, said central processing unit operable to access said L1 program memory; at least one requestor operable to access said L1 program memory; an arbitrator connected to said central processing unit and said at least one requestor, said arbitrator generating a sleep mode (SM) signal in an active state for a following memory access cycle when neither said central processing unit nor any of said at least one requestor requests access to said L1 program memory; a bias control circuit connected to said L1 program memory and said arbitrator, said bias control circuit supplying a first bias to said L1 program memory for normal operation if said sleep mode (SM) signal is in an inactive state and a second bias to said L1 program memory for reduced power sleep mode operation if said sleep mode (SM) signal is in said active state; an AND gate having a first input connected to said arbitrator and receiving said sleep mode signal, a second input connected to said memory mapped register and receiving a state of said sleep mode enable bit, and an output connected to said bias control circuit; and said bias control circuit disabling said sleep mode and supplying said L1 program memory said first bias if said sleep mode enable bit has said sleep mode disable state.