Patent ID: 6380085
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method of manufacturing a DRAM having a memory mat portion and a peripheral circuit portion, comprising the steps of:forming a thermal oxide film on a semiconductor substrate surface; depositing a silicon nitride film on said thermal oxide film; patterning said silicon nitride film in accordance with an active region; etching said thermal oxide film and said silicon substrate with the patterned silicon nitride film used as a mask to form grooves in a field region; depositing an insulating film; partly etching said insulating film in such a manner that a plurality of pillars of said insulating film are left for said memory mat portion; exposing said patterned silicon nitride film by chemical mechanical polishing; and removing said exposed silicon nitride film; wherein one of said pillars left by said step of partly etching said insulating film has a surface area in plan view that is larger than a surface area in plan view of an active region formed beneath said one of said pillars, and said one of said pillars is over a plurality of active regions formed for said memory mat portion.