Patent ID: 6466508
Filing Date: 2002-10-15
Classification: G11C

Abstract:
A semiconductor memory device for conducting data output in response to K addresses from first to Kth addresses having at least one bit in common (where K is a natural number; K&gE;2), comprising:a data block having a plurality of memory cells arranged in a matrix, said data block being divided into N sub data blocks (where N is a natural number; N&gE;2); N sense amplifier circuits provided corresponding to the respective sub data blocks for amplifying read data transmitted thereto; N first data selection circuits provided corresponding to the respective sub data blocks, each of said first data selection circuits conducting a first data selection for selecting L read data in a corresponding one of said N sub data blocks (where L is a natural number given by K/N); N second data selection circuits provided corresponding to the respective sub data blocks, each of said second data selection circuits conducting a second data selection for selecting one of the L read data in a corresponding one of said N first data selection circuits; a decode circuit for switching said first and second data selection in said N first and second data selection circuits according to the addresses; and a third data selection circuit provided corresponding to said data block, for receiving the N read data respectively amplified by said N sense amplifier circuits, and selected by a combination of said first and second data selection in said N sub data blocks, and for selectively outputting the read data corresponding to the addresses.