Patent ID: 9038883
Filing Date: 2015-05-26
Classification: B23K,H01L,H01S,H05K,Y02P

Abstract:
1. A packaging process comprising the steps of: positioning and aligning a submount in a vacuum soldering apparatus, wherein said submount is a thermal submount, a printed circuit board or a combination thereof; aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the submount such that a plurality of bonding pads on the submount align substantially with corresponding plurality of contact pads on the VCSEL chip; correcting for a curvature of the VCSEL chip surface by applying a pre-determined amount of pressure effected through a structured pad with raised regions to differentially apply controlled pressure on predetermined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature; sealing the vacuum soldering apparatus for enclosing the submount and the VCSEL chip; creating an air free environment in the vacuum soldering apparatus; and heating the submount and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount.