Patent ID: 9190487
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a semiconductor fin on a substrate; depositing a dielectric metal compound liner directly on surfaces of said semiconductor fin; forming a disposable gate structure straddling said semiconductor fin over said dielectric metal compound liner; forming a gate spacer on said dielectric metal compound liner and said disposable gate structure; removing portions of said dielectric metal compound liner after forming said gate spacer, wherein said removing employs said gate spacer and said disposable gate structure as an etch mask, wherein a remaining portion of said dielectric metal compound liner underneath said gate spacer constitutes a dielectric metal compound portion, and wherein semiconductor surfaces of said semiconductor fin are physically exposed after said removing of said portions of said dielectric metal compound liner; depositing a planarization dielectric layer over said disposable gate structure and said gate spacer; forming a gate cavity in said planarization dielectric layer by removing said disposable gate structure selective to said planarization dielectric layer; and forming a replacement gate structure in said gate cavity.