Patent ID: 6670855
Filing Date: 2003-12-30
Classification: H03L,Y10S

Abstract:
A PLL device comprising:a generating means (2, 3, 4, 5) for generating a plurality of reference signals having different phases; a plurality of variable frequency dividers (11, 12, 13, 14) that divide a frequency of an output signal of a voltage-controlled oscillator (15) and output feedback signals; a plurality of phase comparators (7, 8, 9, 10) that compare phases between the reference signals and the output feedback signals; and a control unit (30); wherein the control unit (30), upon deciding that a locked state has been reached in at least one of the phase comparators, allows said one of the phase comparators to keep on delivering an output, and disables outputs of the other phase comparators, and the control unit (30) causes the variable frequency divider connected to the phase comparator that keeps on delivering an output to continue to operate, and stops operations of the other frequency dividers; further comprising detectors (37, 38, 39, 40) connected to the phase comparators respectively for detecting a locked state or a nearly locked state on the basis of outputs of the phase comparators and outputting a detection signal to the control unit, wherein the control unit decides that the locked state is reached when the frequency of the output signal reaches a predetermined percentage between 70% and 95% of an upper limit of frequency bounds after overshoots and down shoots are over.