Patent ID: 7786968
Filing Date: 2010-08-31
Classification: G09G

Abstract:
1. A shift register that sequentially outputs pulses from plural output terminals of the shift register, wherein each stage of the shift register includes a set-reset flip flop corresponding to each of the plural output terminals, said each stage of the shift register produces, as a source pulse of a pulse output from said each of the plural output terminals, a first pulse which includes a pulse output from said set-rest flip flop and which has a terminal end determined by a reset pulse input to said set-reset flip flops, said each stage of the shift register outputs the first pulse from an output terminal of said set-reset flip flop, said each stage of the shift register produces a second pulse, the second pulse having a waveform equal to a waveform obtained by inverting a pulse level of the first pulse from a desired point to a terminal end and setting a desired level and polarity, the inversion is carried out by performing, on the first pulse, calculations including a logic calculation using a reference pulse that occurs earlier than the terminal end of the first pulse by a desired period of time, the setting of the desired level and polarity of the second pulse is carried out by performing power-source-voltage exchange using a level shifter the shift register outputs the second pulse from said each plural output terminals corresponding to said each stage of the shift register, and a terminal end of the second pulse occurs earlier in time than the terminal end of a corresponding first pulse.