Patent ID: 8143924
Filing Date: 2012-03-27
Classification: H03K

Abstract:
1. A semiconductor integrated circuit device in which pulse generating circuits are formed on a semiconductor substrate, each of the pulse generating circuits being configured to receive a plurality of different positive and negative electric potentials at respective first terminals of a plurality of semiconductor switching elements, with second terminals of the plurality of semiconductor switching elements being commonly connected to an output terminal, wherein each pulse generating circuit is operative to generate voltage pulse signals at each of said plurality of positive and negative electric potentials and at a ground potential based on control pulse signals input to corresponding control terminals of the plurality of semiconductor switching elements, wherein each of the plurality of semiconductor switching elements comprises a latch circuit and one of a P-channel analog switching circuit and an N-channel analog switching circuit, wherein each of said P-channel and N-channel analog switching circuits has first and second MOSFETs, source terminals of the first and second MOSFETs being commonly connected to each other, gate terminals of the first and second MOSFETs being commonly connected to each other, and a drain terminal of the first MOSFET being to receive a first potential that is any one of said plurality of different positive and negative potentials, and a drain terminal of the second MOSFET being connected to the output terminal, and wherein each of the latch circuits is operative to control a corresponding one of said P-channel or N-channel analog switching circuits based on a corresponding one of said control pulse signals, and has a reference potential terminal thereof connected to the commonly connected source terminals of the corresponding first and second MOSFETs.