Patent ID: 8499259
Filing Date: 2013-07-30
Classification: G06F,Y02P

Abstract:
1. A polishing estimation/evaluation device comprising: a dividing unit that divides a layout of an integrated circuit, which is to be produced through a deposition process and a polishing process, into a plurality of partial areas; an overpolished area extracting unit that refers to an overpolishing condition indicating whether or not overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by division by the dividing unit; and a dummy modifying unit that modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs, wherein in the overpolishing condition, an average value of wiring densities of partial areas present within a predetermined distance from the partial area is used as the wiring density in the surrounding areas, wherein the predetermined distance is determined depending on a position on a test pattern on which the overpolishing occurs, so as to define the surrounding areas of the partial area.