Patent ID: 6563344
Filing Date: 2003-05-13
Classification: G11C,H03K

Abstract:
An electronic circuit comprising:a memory array; a buffer circuit connected to said memory array and having an input for receiving a clock signal and an output, said buffer circuit comprising transfer means for transferring the clock signal from the input to the output of said buffer circuit, and comprising at least one logic gate connected to the input of said buffer circuit and having a trip point sensitive to a supply voltage of said buffer circuit, delivery means for delivering an inhibit signal having a predetermined duration based upon at least one of a trailing edge and a leading edge of the clock signal, inhibit means for inhibiting said transfer means and for isolating the output of said buffer circuit from the input of said buffer circuit when the inhibit signal is delivered, and storage means for holding a value of the clock signal at the output of said buffer circuit when the inhibit signal is delivered; and data transfer means for sending, in synchronization with the at least one of the trailing edge and the leading edge of the clock signal, data read in said memory array.