Patent ID: 7813171
Filing Date: 2010-10-12
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells which store data in the form of n values (n is a natural number which is not smaller than 2) which are in first and second to nth states are arranged in a matrix form; and a control circuit which performs a soft program operation in a second memory cell exceeding a first threshold voltage when at least one second memory cell adjacent to a first memory cell is in the first state as an erased state and does not reach the first threshold voltage before a write operation of storing data in the first memory cell in the memory cell array, the soft program operation lessening fluctuation in threshold voltage of the second memory cell by narrowing distribution of the threshold voltage of the second memory cell, wherein the first threshold voltage is a threshold voltage of the erased state.