Patent ID: 7186640
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. A method of fabricating at least one damascene opening, comprising steps of: providing a structure having at least one exposed conductive structure; forming a dielectric barrier layer over the structure and the at least one exposed conductive structure; forming a lower low-k dielectric layer over the dielectric barrier layer; the upper low-k dielectric layer being distinct and comprised of different material to the lower low-k dielectric layer; forming an SRO (silicon-rich oxide) hard mask layer on and directly contacting the upper low-k dielectric layer by either a) a reaction of TEOS with O patterning at least the upper and lower low-k dielectric layers and the dielectric barrier layer to form the at least one damascene opening exposing at least a portion of the at least one exposed conductive structure, wherein the at least one SRO (silicon-rich oxide) hard mask layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.