Patent ID: 6472266
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A method of fabricating a bit line for a DRAM device on a semiconductor substrate, wherein a top portion of a bit line contact hole is provided with an air gap, comprising the steps of:providing a semiconductor substrate, an active surface region having been defined and being bounded by Shallow Trench Isolation regions in the surface of said substrate, two gate structures having been provided on the active surface region of the substrate overlying a gate insulation layer, with two source regions and a drain region having been provided in the surface of said substrate self-aligned with and at the sides of and between the two gate structures, said drain region forming a bit line contact in the surface of said substrate, said two source regions forming storage node contacts in the surface of said substrate; depositing a first layer of dielectric over the surface of the substrate, including the surface of said two gate structures provided over the active surface region of the substrate; depositing a layer of etch stop material over the surface of said first layer of dielectric; creating capacitors overlying said storage node contact points provided in the surface of said substrate, said creating capacitors comprising creating a first conductive plug overlying and being in contact with said bit line contact provided in the surface of said substrate; creating a second conductive plug overlying said first conductive plug, said second conductive plug being surrounded by said air gap, said air gap being formed between the second conductive plug and material surrounding the second conductive plug; closing said air gap surrounding said second conductive plug, said closing said air gap comprising: (i) deposition of a layer of oxide; and (ii) polishing the surface of said deposited layer of oxide; and providing interconnect metal to said second conductive plug.