Patent ID: 6272057
Filing Date: 2001-08-07
Classification: G11C

Abstract:
A semiconductor memory device for a memory having a memory cell array comprising a first plurality of normal memory cells associated with a respective first set of word lines and a second plurality of redundant memory cells associated with a respective second set of word lines, said device accessing any of said memory cells by changing, based on an input address data, an associated word line from a standby state to an active state, said semiconductor memory device comprising:a plurality of normal row decoders for changing at least one of said first set of word lines from a standby state to an active state when access is made to any of said memory cellsat least one redundant row decoder for changing at least one of said second set of word lines from a standby state to an active state when access is made to any memory cell which belongs to said plurality of redundant memory cells;a decision device for determining whether or not to select a memory cell belonging to said plurality of redundant memory cells, based on said input row address data; anda controller for changing only said first set of word lines from said active state back to said standby state when said decision device has determined to select a memory cell belonging to said plurality of redundant memory cells.