Patent ID: 6038181
Filing Date: 2000-03-14
Classification: G01R

Abstract:
A static random access memory device comprising:a random access memory array having a plurality of memory storage units therein and an address input line, a set input line, a plurality of output data lines and a dummy bit line output;a self reset circuit coupled to the address input line of said array through an address generator;an external clock having an output and an input coupled to said self reset circuit, said external clock emitting an external clock pulse, having a first half and a second half;a set circuit having an input coupled to the dummy bit line output and having first and second outputs, the first output being coupled to the set input line;address generation means for sending a test cycle to said random access memory array;a data latch having first and second inputs and an output, the first input of said data latch being coupled to said memory array output data lines and the second input of said data latch being coupled to the second output of said set circuit;a look aside latch having first, second and third inputs and an output, the first input of said look aside latch being coupled to the first input of said data latch;a device output coupled to the output of the data latch; andfeedback means coupling the second output of said set circuit to said self reset circuit to cause said self reset circuit to reset a predetermined number of times during said external clock pulse emitted by said external clock.