Patent ID: 6275902
Filing Date: 2001-08-14
Classification: G06F

Abstract:
A data processor comprising:a main memory for storing data and instructions;an instruction processor for processing said data in accordance with said instructions;a cache memory part, connected between said main memory and said instruction processor, including a first cache memory and a second cache memory, said first cache memory having a large storage capacity and said second cache memory having a small storage capacity; anda controller, included in said cache memory part, which in response to an address to be accessed, selects one of said first and second cache memories and stores data into the selected cache memory,wherein said controller includes a storage having stored therein a plurality of addresses and information, each of said addresses being stored in corresponding relation to a portion of said information which indicates one of said first and second cache memories to be accessed, andwherein said controller in response to said address to be accessed refers to said portion of said information stored in said storage of said controller in corresponding relation to said address to be accessed and selects one of said first and second cache memories indicated by said portion of said information.