Patent ID: 6052320
Filing Date: 2000-04-18
Classification: G11C

Abstract:
An integrated circuit memory device, comprising:first and second memory cell arrays in first and second blocks of memory, respectively;a first local input/output line:a first global input/output line;means, electrically coupled to said first and second memory cell arrays, for enabling transfer of data from said first memory cell array to said first global input/output line in response to a first merged data test control signal and enabling transfer of data from said second memory cell array to said first global input/output line in response to a second merged data test control signal, said means for enabling transfer comprising a first switch electrically connected in series between said first local input/output line and said first global input/output line; anda first merged data test circuit having a first input electrically coupled to said first global input/output line and a first output which generates first and second error signals upon detection of a failure in said first and second memory cell arrays, respectively.