Patent ID: 7733728
Filing Date: 2010-06-08
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a main cell array having a plurality of first cells; a reference cell array having a plurality of second cells, said first cells and said second cells having respective resistance values associated therewith, said respective resistance values being related to address signals; a sense amplifier coupled to said memory cell array and said reference cell array to compare one of said first cells and another of said second cells during a read mode; and a decoder coupled to receive said address signals to select said one of said first cells and said another of said second cells such that said respective resistance values of said one and said another cells are a same value with each other during said read mode, wherein said plurality of second cells of said reference cell array have resistance that are symmetrically balanced, so that a resistance corresponding to an arbitrary one of said first cells can be selected from approximately only half of said second cells.