Patent ID: 6043541
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A bipolar/complementary metal-oxide-silicon (BiCMOS) integrated circuit structure including a silicon substrate having N-type buried layers and P-type buried layers therein and an epitaxial layer disposed above the N-type buried layers and P-type buried layers and having different conductivity type wells formed therein; N-channel and P-channel MOS transistors formed in different conductivity type wells in the epitaxial layer and having transistor gate regions formed of a first level of polysilicon; a bipolar transistor formed in yet another well in the epitaxial layer and having collector, base and emitter regions within the well, with the emitter region being connected directly to either a first level or a second level of polysilicon and created by impurities received by out-diffusion from either the first or second levels of polysilicon; a second bipolar transistor formed in still another well within the epitaxial layer and having its emitter region formed by contact to either the first or second levels of polysilicon and out-diffusion of impurities therefrom; and yet a further bipolar transistor formed in a further well within the epitaxial layer and having its emitter region formed by ion implantation into the surface of the epitaxial layer.