Patent ID: 6058045
Filing Date: 2000-05-02
Classification: G11C,H01L

Abstract:
An array of flash memory cells comprising:a plurality of columns of serially connected flash memory cells, each memory cell having a gate terminal;a plurality of bit lines respectively coupled to drain side of said plurality of columns of memory cells via a respective plurality of bit line select transistors, said plurality of bit line select transistors having gate terminals coupled to a bit line select control line;a plurality of word lines, each one coupling to a gate terminal of one memory cell in each of said plurality of columns to from rows of memory cells with common gate terminals; anda plurality of source select transistors respectively coupling a source side of said plurality of columns of memory cells to a logic low voltage, and having gate terminals coupled to a source select control line,wherein, during programming:a logic high voltage is applied to said bit line select control line to turn on bit line select transistors,a logic low voltage is applied to source select control line to turn off source select transistors;a logic low voltage is applied to a selected bit line while a logic high voltage is applied to unselected bit lines, anda logic high voltage is applied to unselected word lines, while a boosted positive voltage is applied to a selected word line.