Patent ID: 6819326
Filing Date: 2004-11-16
Classification: G06F,H04N

Abstract:
A memory address translation device, comprising:a memory bus interface for issuing access requests to a number of banks of memory addressable by their physical memory addresses; a processor bus interface for receiving logical memory address access requests for translation into physical memory address access requests; a lookup table for implementing a mapping of translations of data element logical addresses to data cell physical address, and having its input connected to the processor bus interface and its output connected to the memory bus interface; a data-block analyzer for characterizing the size, location, and type of data stored in blocks in said banks of memory; a memory transfer overhead calculator for computing a memory transfer overhead cost from information gathered by the data-block analyzer, given a set of control parameters, a memory bus width, and an organization and a number of banks of memory that are accessible to the memory bus interface, a minimum cost estimator for providing the memory transfer overhead calculator with control parameter sets, and for comparing alternative memory transfer overhead costs and determining a lowest cost choice, and connected to notify the mapping generator if a current mapping is determined not to be the most optimal mapping; a mapping generator connected to receive calculations from the minimum cost estimator, and for translating an input logical memory address to an output physical memory address, and connected to output data to the lookup table; and an address generator connected to the lockup table and for determining each instance of a logical memory address and its corresponding physical memory address.