Patent ID: 6794708
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A semiconductor memory integrated circuit comprising:a semiconductor substrate; a device isolation insulating film buried in grooves formed into said semiconductor substrate; a cell array having an arrangement of electrically erasable and programmable nonvolatile memory cells made by stacking floating gates and control gates on said semiconductor substrate; and a peripheral circuit disposed around said cell array on said semiconductor substrate, at least a bottom layer of said floating gates of said nonvolatile memory cells and at least a bottom layer of gate electrodes of transistors in said peripheral circuit being formed before said device isolation insulating film is buried, then the bottom layer of said floating gates of said nonvolatile memory cells and the bottom layer of gate electrodes of transistors in said peripheral circuit being maintained in self alignment with said device isolation insulating film, N type impurities being doped into the gate electrodes of NMOS transistors and P type impurities being doped into the gate electrodes of PMOS transistors in said peripheral circuit, and said floating gates of said nonvolatile memory cells comprise a first-layer gate electrode material film in self alignment with said device isolation insulating film and a second-layer gate electrode material film stacked on said first gate electrode material film, said control gates comprise a third-layer electrode material film, and said gate electrodes in said peripheral circuit have a three-layered structure including said first- to third-layer gate electrode material films.