Patent ID: 7355437
Filing Date: 2008-04-08
Classification: H03K

Abstract:
1. An integrated circuit comprising: metal-oxide-semiconductor transistors each of which has a body terminal; input-output pins with which power supply signals are supplied to the integrated circuit; a body bias path that distributes a body bias signal to the body terminals of the metal-oxide-semiconductor transistors; active latch-up prevention circuitry that monitors the power supply signals to detect potential latch-up conditions for the metal-oxide-semiconductor transistors and that holds the body bias path at a safe voltage to prevent latch-up in the metal-oxide-semiconductor transistors while the potential latch-up condition is present; and body bias generation circuitry that generates the body bias signal that is applied to the body bias path, wherein the active latch-up prevention circuitry comprises circuitry that monitors at least one signal from the body bias generation circuitry to determine whether the body bias signal is valid.