Patent ID: 6724929
Filing Date: 2004-04-20
Classification: G06T

Abstract:
A wafer inspecting apparatus comprising:wafer inspecting means for acquiring for a respective chip an image of a face to be inspected of a wafer having formed thereon a circuit pattern based on wiring information of a circuit for the respective chip and generating and outputting coordinate value data representing positions and sizes of defects present on the face of the wafer to be inspected for the respective chip; image data forming means for forming graphic images representing the respective defects based on the respective coordinate value data for the respective chip and generating image data corresponding to the graphic images; analyzing means for inputting the image data, analyzing a state of overlap of a first image corresponding to the image data and a second image representing the circuit pattern based on the wiring information and outputting overlap analysis data; and classifying means for inputting the overlap analysis data and classifying the defects by kind of defect based on the overlap analysis data.