Patent ID: 7696556
Filing Date: 2010-04-13
Classification: H01L

Abstract:
1. A high-voltage MOS transistor comprising: a source region and a drain region provided in a semiconductor substrate; a main gate electrode disposed over the semiconductor substrate between the drain region and the source region and electrically insulated from the semiconductor substrate; an inter-gate dielectric layer disposed on the semiconductor substrate; and a lower drain-side auxiliary gate and an upper drain-side auxiliary gate sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region, wherein the lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate, and wherein the main gate electrode includes a lower main gate electrode and an upper main gate electrode electrically connected to each other through a gate via hole penetrating the inter-gate dielectric layer, and wherein the drain region comprises: