Patent ID: 9124416
Filing Date: 2015-09-01
Classification: H04L

Abstract:
1. A method comprising: for each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases being delayed with respect to the phase of the reference clock, transmitting test parallel data in synchronism with the reference clock, and receiving the test parallel data in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; for each of the plurality of delayed phases, judging whether the parallel data received by the delayed clock has been received correctly or not, and performing a comparison as to whether the parallel data received by the delayed clock matches the parallel data received by the adjacent delayed clock; determining a phase range containing, from among the plurality of delayed phases, a delayed phase with which the test parallel data has been received correctly and for which a result of the comparison indicates a match; and determining, from the determined phase range, a phase of a receive clock to be used for reception of parallel data.