Patent ID: 7816231
Filing Date: 2010-10-19
Classification: G03F,H01L

Abstract:
1. A method comprising: forming a substrate having a front surface and a back surface and one or more alignment structures that are visible at the back surface of the substrate for backside lithographic alignment, said substrate has a semiconductor-on-insulator (SOI) configuration and comprises a front semiconductor device layer, a buried insulator layer, and a back semiconductor substrate layer; forming at least one front semiconductor device at the front surface of the substrate; forming a passivation layer over the front surface of the substrate to cover the at least one front semiconductor device; bonding a supporting wafer to the passivation layer to support the substrate at the front surface thereof; completely removing the back semiconductor layer of the substrate to expose a back surface of the buried insulator layer; forming a patterned resist layer on the back surface of the substrate by lithography, wherein the patterned resist layer defines at least one back contact opening therein that is lithographically aligned with at least one component of said at least one front semiconductor device; etching the substrate through said at least one back contact opening to form at least one back contact via that extends from the back surface through the substrate onto the at least one component of the at least one front semiconductor device; filling the at least one back contact via with a conductive material to form at least one back conductive contact; and forming at least one back metal interconnect level over the exposed back surface of the buried insulator layer so that the at least one conductive back contact electrically connects the at least one front semiconductor device with the at least one back metal interconnect level.