Patent ID: 6664649
Filing Date: 2003-12-16
Classification: H01L,H05K

Abstract:
A semiconductor package, which comprises:(a) a leadframe including an outer-lead portion, an inner-lead portion, and a downset bond-finger portion, the inner-lead portion having a front side and a back side; (b) a semiconductor chip having an active surface and an inactive surface and being formed with a plurality of centrally-located I/O pads on the active surface thereof, the semiconductor chip being arranged on the back side of the inner-lead portion of the leadframe with the active surface thereof being insulatively attached to the downset bond-finger portion of the leadframe; (c) a plurality of bonding wires which are bonded between the respective I/O pads of the semiconductor chip and the downset bond-finger portion of the leadframe; (d) a heat sink attached to the front side of the inner-lead portion of the leadframe by means of an electrically-insulative and thermally-conductive adhesive material, such that a space is formed between the heat sink and the semiconductor chip for receiving the bonding wires, and the space is filled with the electrically-insulative and thermally-conductive adhesive material that encapsulates the bonding wires received in the space and the I/O pads of the semiconductor chip, so as to allow the electrically-insulative and thermally-conductive adhesive material to be directly in contact with both the semiconductor chip and the heat sink that are attached to opposite sides of the leadframe; and (e) an encapsulation body which encapsulates the semiconductor chip, the inner-lead portion of the leadframe, the bonding wires, and the heat sink, while exposing the outer-lead portion of the leadframe to outside.