Patent ID: 8964460
Filing Date: 2015-02-24
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor comprising: an address decoder which decodes an address inputted from address lines, and outputs a word selection signal to a word line; and a memory cell array including a plurality of non-volatile memory cells, each of which being respectively disposed on crossing over points of each word lines and each data lines, the non-volatile memory cells which include a phase-change layer being partially used as a storage element and being connected to an electrode connected to a power-supply voltage at end; a data line voltage control section which writes data on the non-volatile memory cells by decreasing a voltage of the data line being connected to the other end of the phase-change layer and causing partially a phase change in the phase-change layer; and a sheet of electrode which provides the power-supply voltage disposed above the phase-change layer, wherein the word line, the data line, and the data line voltage control section are disposed under the phase-change layer.