Patent ID: 7208371
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A method of fabricating a split gate flash memory device, comprising the steps of: forming a dielectric layer on an active area of a semiconductor substrate; forming a first gate covered with a cap layer on the dielectric layer; forming an insulating layer on a sidewall of the first gate; forming dummy spacers over the sidewall of the first gate, the first gate including the cap layer and the insulating layer; removing the dielectric layer not covered with the dummy spacers and the first gate to form an exposed portion of the semiconductor substrate; forming a gate insulating layer on the exposed portion of the semiconductor substrate; and forming a second gate overlapping one side of the first gate, wherein a split gate is configured with the first and second gates, wherein a dielectric layer pattern remains beneath the dummy spacers and the first gate as a result of the step of removing the dielectric layer not covered with the dummy spacers and the first gate.