Patent ID: 8373955
Filing Date: 2013-02-12
Classification: H01L

Abstract:
1. An electrostatic discharge protection device applied in a chip, comprising: a first transistor, wherein the first transistor includes a first gate, a first drain coupled to an input/output pin of the chip, and a first source coupled to a first voltage pin of the chip; a second transistor coupled to the first transistor, wherein the second transistor includes a second gate, a second drain coupled to the input/output pin, and a second source coupled to a second voltage pin of the chip; and an electrostatic discharge clamp circuit coupled between the first and second voltage pins, wherein the first transistor has a first, a second, a third and a fourth doping regions, the first and third doping regions form the first source of the first transistor, a doping depth of the third doping region is more than a doping depth of the first doping region, and a doping concentration of the third doping region is less than a doping concentration of the first doping region, wherein the second and fourth doping regions form the first drain of the first transistor, a doping depth of the fourth doping region is more than a doping depth of the second doping region, and a doping concentration of the fourth doping region is less than a doping concentration of the second doping region, wherein the doping concentration of the fourth doping region is designed to be less than the doping concentration of the third doping region and the doping depth of the fourth doping region is more than the doping depth of the third doping region to control current path of an electrostatic discharge current.