Patent ID: 7143369
Filing Date: 2006-11-28
Classification: G06F

Abstract:
1. A method for simulating operations of a circuit design that includes high-level components and HDL components, comprising: associating each group of a plurality of groups of HDL components with a co-simulation engine of a plurality of co-simulation engines, wherein each group of the plurality of groups has one or more HDL components; instantiating a plurality of co-simulation engine servers, each co-simulation engine server configured to provide an interface between the high-level components and HDL components being co-simulated on the associated co-simulation engine; generating by a high-level modeling system (HLMS) upon initiation of simulation, an HDL wrapper for each group of HDL components, the HDL wrapper including a clock-and-control component that drives each HDL component in the group during co-simulation; simulating the high-level components of the design in the (HLMS); and co-simulating the HDL components in each group on the associated co-simulation engine.