Patent ID: 6284605
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method for fabricating a semiconductor power integrated circuit, comprising the steps of:a) forming a semiconductor structure having at least one active region, wherein an active region includes a first well region for forming a channel and a source region and a drift region for forming a drain region;b) forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure;c) forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor structure;d) forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer; ande) performing a selective tapered etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a trench isolation layer pattern, a gate oxide layer pattern.