Patent ID: 8878351
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first semiconductor device including a first semiconductor chip and a second semiconductor chip, which are stacked and each of which includes a first power electrode formed on a first surface as well as a second power electrode and a third power electrode, electrically connected inside the first power electrode, formed on a second surface, said first semiconductor device further including a first conductor which is formed between the second power electrode of the first semiconductor chip and the second power electrode of the second semiconductor chip, which are positioned opposite to each other, and between the third power electrode of the first semiconductor chip and the third power electrode of the second semiconductor chip, which are positioned opposite to each other; and a second semiconductor device, having the same configuration as the first semiconductor device and stacked with the first semiconductor device, said second semiconductor device further including a second conductor which connects between the first power electrode of the second semiconductor chip of the first semiconductor device and the first power electrode of the second semiconductor device, which are positioned opposite to each other, wherein the first and second semiconductor chips are exclusively controlled, such that the first semiconductor chip is disabled if the second semiconductor chip is enabled and the second semiconductor chip is disabled if the first semiconductor chip is enabled.