Patent ID: 6121664
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a semiconductor substrate;a plurality of first transistors formed over said semiconductor substrate in a matrix configuration, each of said first transistors having a channel region;a plurality of second transistors formed over said semiconductor substrate in a matrix configuration, each of said second transistors having a channel region;a plurality of word lines formed in parallel in a first direction, said word lines functioning as word lines and gate electrodes for said plurality of first transistors and said plurality of second transistors;whereinat least two channel regions of said plurality of first transistors make contact in a second direction substantially perpendicular with respect to said first direction;at least two channel regions of said plurality of second transistors make contact in said second direction; andthe channel regions of said plurality of first transistors function as source/drain regions for said plurality of second transistors.