Patent ID: 9166154
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A method of fabricating an array of memory pillars on a wafer using a single mask, the method comprising: depositing a stack of layers for the array of memory pillars including a top electrode layer and a bottom electrode layer with magnetic tunnel junction (MTJ) layers interposed therebetween, the MTJ layers further comprising a top magnetic layer and a bottom magnetic layer with a barrier layer interposed therebetween; executing a first etching process to remove areas of at least the top electrode layer and the top magnetic layer not covered by a mask that defines the array of memory pillars; and performing a second etching process using ion beam etching to remove areas of remaining layers not covered by the mask, including the bottom electrode layer, to form the array of memory pillars while rotating the wafer and to clean exposed sidewalls of the array of memory pillars including sidewalls of patterned bottom electrode layer, and wherein at least a portion of the ion beam etching is performed at a selected ion beam incidence angle greater than zero degree.