Patent ID: 6337600
Filing Date: 2002-01-08
Classification: H03J,H03K,H03L

Abstract:
A frequency setting method for a phase locked loop (PLL) circuit that comprises a piezoelectric resonator;an oscillation signal output section which oscillates the piezoelectric resonator and outputs an oscillation signal of a first frequency; an adjustment circuit that finely adjusts the first frequency; a first programmable divider that divides the first frequency by a first frequency dividing number to obtain a reference signal of a second frequency; a second programmable divider that has a second frequency dividing number, that receives a reference signal which has been input from a voltage controlled oscillator, and that is provided in a feedback circuit of a PLL circuit section which outputs a multiplied signal of a third frequency; and a ROM which stores the first frequency dividing number and the second frequency dividing number, the method comprising steps of: measuring an oscillation frequency of the oscillation signal output section before adjusting the oscillation frequency in the adjustment circuit; dividing a frequency range in which a resonance frequency of piezoelectric oscillation is dispersed into a plurality of divisions in a frequency range which can be adjusted in the adjustment circuit; determining the division to which the oscillation frequency of the oscillation signal output section, which has been measured before adjusting the oscillation frequency in the adjustment circuit, belongs; adjusting the oscillation frequency to a desired frequency within the determined division by using the adjustment circuit; and storing the first frequency dividing number and the second frequency dividing number to the ROM when the oscillation frequency becomes the desired frequency within the determined division.