Patent ID: 6463069
Filing Date: 2002-10-08
Classification: H04B

Abstract:
A buffering arrangement (10) receiving redundant signals intended for a terminating unit as signal user, said signals comprising a number of unsynchronized datastreams from a number of different planes (A, B, C) with each a clock-system (CLA, CLB, CLC), said arrangement comprising first buffering means (2) for handling dynamic phase deviation between the planes (A, B, C) and second buffering means (5) for handling static phase deviations between the planes (A, B, C), characterized in,that a register arrangement (8;54) is provided in which is stored information relating to an initial difference between read and write pointer for a plane in the second buffering means (5), and in that further information relating to the current difference between the read and write pointer of the same plane in the second buffering means (5) is stored after a reload operation and in that the initial difference and the current difference are compared providing a control signal (ICO) which is used for the next reload operation of the same plane in the first buffering means (2) which is controlled by said control signal (ICO) to avoid end of buffer in the second buffering means (5) if the difference between the initial and the current differences exceeds a given number of positions.