Patent ID: 7190018
Filing Date: 2007-03-13
Classification: G11C,H01L

Abstract:
1. A non-volatile memory cell for the storage of a plurality of bits, comprising: a substantially single crystalline semiconductive substrate material of a first conductivity type, having a substantially planar surface; a first trench in said substrate; said first trench having a side wall, substantially perpendicular to the planar surface, and a bottom wall; a second trench in said substrate; spaced apart from said first trench, said second trench having a side wall, substantially perpendicular to the planar surface, and a bottom wall; a first region of a second conductivity type, different from said first conductivity type in said material, along the bottom wall of said first trench; a second region of said second conductivity type in said material, spaced apart from said first region, along the bottom wall of said second trench; a channel region, having a first portion, a second portion and a third portion, connecting said first and second regions for the conduction of charges, said first portion being along the side wall of said first trench, said second portion being along the side wall of said second trench; a dielectric on said channel region; a first floating gate on said dielectric, spaced apart from said first portion of said channel region; said first portion of said channel region adjacent to said first region, said first floating gate for the storage of at least one of said plurality of bits; a second floating gate on said dielectric, spaced apart from said second portion of said channel region; said second portion of said channel region adjacent to said second region, said second floating gate for the storage of at least another of said plurality of bits; a gate electrode on said dielectric, spaced apart from said third portion of said channel region, said third portion of said channel region between said first portion and said second portion; a first independently controllable gate electrode, in said first trench, capacitively coupled to said first floating gate and insulated from said first region; and a second independently controllable gate electrode, in said second trench, capacitively coupled to said second floating gate and insulated from said second region.