Patent ID: 6147925
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory sub-blocks each having a plurality of memory cells arranged in rows and columns, and aligned at least in a column direction;a plurality of sense amplifier groups arranged for said plurality of memory sub-blocks such that memory sub-blocks adjacent each other in the column direction share a sense amplifier group, each sense amplifier group activated to sense and amplify data of a selected memory cell in a corresponding memory sub-block;a plurality of isolating gate groups arranged between said plurality of sense amplifier groups and said plurality of memory sub-blocks for selectively isolating corresponding sense amplifier groups from corresponding memory sub-blocks, respectively; andcontrol circuitry responsive to a row select instruction for setting a selected isolating gate group provided for a selected memory sub-block including the selected memory cell to a high-resistance but conductive state, setting an unselected isolating gate group arranged between an unselected memory sub-block sharing the sense amplifier group with said selected memory sub-block and the shared sense amplifier group to a non-conductive state, and holding the conductive state and the non-conductive state while said selected memory sub-block is in a selected state.