Patent ID: 9009369
Filing Date: 2015-04-14
Classification: G06F,G11C

Abstract:
1. A memory comprising: a plurality of entries each configured to store a respective data value and a valid bit set to a first state if its corresponding entry is storing valid data and a second state if its corresponding location is not storing valid data; a priority encoder configured to select one of the plurality of entries to be read based on a first set of valid bits and a second set of valid bits, and wherein the priority encoder is further configured to generate a plurality of control signals corresponding to a selected one of the plurality of entries; and a plurality of selection circuits configured to couple the selected one of the plurality of entries to a read port based on the plurality of control signals; wherein the memory is a circular queue having an associated read pointer configured to advance from a first address to a last address, wherein the first set of valid bits includes all valid bits set to the first state and wherein the second set of valid bits includes all valid bits between a current address of the read pointer and the last address.