Patent ID: 6174767
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A method of forming bit lines and capacitors for a semiconductor memory device comprising the steps as follows:form a gate oxide on a semiconductor substrate;form a conductive gate electrode on a semiconductor substrate;form a cap layer on said conductive gate electrode composed of an etch stop material,pattern and etch said cap layer and said conductive gate electrode material to form a gate electrode stack,form laminated spacer dielectric layers on said semiconductor substrate and said cap layer said laminated spacer dielectric layers including a silicon oxide layer and an external etch stop layer,etch back said spacer dielectric layer to form spacers on the sidewalls of said gate electrode stack,form a glass layer over said semiconductor substrate, said gate electrode stack, and said spacers; planarize said glass layer; form a SAC mask over said glass layer; etch to form plug cavities in said glass layer through said SAC mask stopping on said external etch stop layer; etch away said external etch stop layer stopping on said silicon oxide layer,perform an ion implant for a cell node junction, and deposit lightly doped conductive plugs into said plug cavities, said plugs having a top surface,form a first interpolysilicon layer, form a capacitor-node-and-bit-line-contact mask on said first interpolysilicon layer, etch through said capacitor-node-and- bit-line-contact mask to form bit-line cavities,deposit a metal bit-line material, then form a bit-line mask, then etch said metal bit-line material to form bit-lines and seal said bit-lines with an etch stopping sealant,form a second interpolysilicon layer, planarize said second interpolysilicon layer, form a storage capacity mask with long stripes, and etch stopping on said bit-line spacers to form a self-aligned capacitor cavity in said first and second interpolysilicon layers through said storage capacity mask down to said plugs,deposit a thin bottom electrode layer reaching into said first interpolysilicon layer above said first dielectric material,deposit additional dielectric, deposit a polysilicon top capacitor plate layer, form a top plate mask and pattern said top plate layer by etching through said top plate mask,wherein said bit-line etch stopping sealant comprises a silicon nitride dielectric layer over said bit-lines and on the sidewalls thereof formed to seal said bit-lines, including the steps as follows:form said metal bit-line material of a laminated structure of TiN/W/TiN,form said second interpolysilicon layer composed of silicon oxide dielectric above said bit-lines, and planarize said second interpolysilicon layer by chemical mechanical polishing, andform said thin bottom electrode layer on the top surface of said plugs and planarize said bottom electrode layer, form a capacitor dielectric layer above said thin bottom electrode layer, and form an upper plate of said capacitor above said capacitor dielectric layer.