Patent ID: 6522204
Filing Date: 2003-02-18
Classification: H03L,H04L

Abstract:
A phase-locked loop (PLL) comprising:a voltage-controlled crystal oscillator (VCXO) operative to generate an output clock in response to a control voltage; a charge pump filter operative to generate the control voltage in response to first pulsed input signals during open-loop operation and second pulsed input signals during closed-loop operation; a logic device operative to generate the first pulsed input signals in response to the output clock and further operative to generate the second pulsed input signals in response to the output clock and an external timing reference clock; and the second pulsed input signals comprise logic high and low pulses generated in the vicinity of positive edges of the external timing reference clock to charge the charge pump filter to a voltage sufficient to achieve a desired frequency and phase lock and further comprise a tristate signal when logic pulses are not being generated.