Patent ID: 7385848
Filing Date: 2008-06-10
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device, comprising: a memory cell array composed of a plurality of arrayed memory cells, each memory cell having a first storage region capable of storing information in vicinity of one of opposite ends of a channel region, a second storage region capable of storing information in vicinity of the other end of the channel region, a first input/output terminal, a second input/output terminal, and a control terminal; word lines connected to the control terminals of the memory cells; bit lines connected to the first input/output terminals and/or the second input/output terminals of the memory cells; a bit line charging and discharging circuit for charging or discharging the bit lines; and a readout section for reading information stored in the first storage region of a memory cell based on a first output equivalent to an output current from the memory cell when a current is passed from the first input/output terminal to the second input/output terminal of the memory cell and a second output equivalent to an output current from the memory cell when a current is passed from the second input/output terminal to the first input/output terminal.