Patent ID: 7420873
Filing Date: 2008-09-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first buffer unit outputting a first clock pulse signal by buffering an external clock enable signal inputted when entering a power-down mode; a second buffer unit outputting a second clock pulse signal by buffering an external clock signal; a first latch unit outputting a first clock control signal for controlling internally operating clocks, by latching the first and second clock pulse signals; a control circuit outputting a second clock control signal when a power-down mode entry command is received during an active mode operation, wherein the second clock control signal utilizes a control signal used in the active mode operation for controlling internally operating clocks employed in the active mode operation; and a clock enable generation circuit outputting a first clock enable signal, a second clock enable signal, and a third clock enable signal, all of which are for enabling an entry into a power-down mode by using the first and second clock control signals when the second clock pulse signal is disabled.