Patent ID: 6101141
Filing Date: 2000-08-08
Classification: G11C

Abstract:
An integrated memory, comprising:a data line pair, a bit line pair, and at least one differential amplifier connected between said data line pair and said bit line pair, said at least one differential amplifier having a first operating mode in which data is forwarded from said data line pair to said bit line pair non-inverted, and a second operating mode in which the data is forwarded inverted;memory cells connected to said bit line pair for receiving data in differential signal form from said data line pair via said differential amplifier and via said bit line pair;a control unit connected to said data line pair, said control unit:setting first potential states on said data line pair corresponding to the differential signals of data to be written to said memory cells; andsetting at least one second potential state on said data line pair not corresponding to any datum to be written to the memory cells;a detector unit having two inputs connected to said data line pair, said detector unit initiating a specific control function on occurrence of the second potential state on said data line pair and switching the operating mode of said differential amplifier upon occurrence of the second potential state on said data line pair.