Patent ID: 9111639
Filing Date: 2015-08-18
Classification: G11C

Abstract:
1. A non-volatile memory (NVM) system having a normal mode, a standby mode and an off mode that uses less power than the standby mode, comprising: an NVM array comprising NVM cells and NVM peripheral circuitry, wherein each NVM cell includes a control gate and the NVM peripheral circuitry includes column/data circuitry and word line circuitry; control gate driver circuitry coupled to the control gate of each NVM cell; a controller coupled to the NVM array, that applies a voltage to the control gates through the control gate circuitry and power to the peripheral circuitry during the standby mode and applies an off-mode voltage that is less than an external power supply voltage to the control gates through the control gate driver circuitry and removes power from the NVM peripheral circuitry during the off mode.