Patent ID: 6674683
Filing Date: 2004-01-06
Classification: G11C

Abstract:
A serial access memory comprising:a first memory array including a first memory cell and a pair of first bit lines, said first memory cell being selectively coupled to a corresponding bit line of said pair of first bit lines according to a voltage level of a first word line; a second memory array including a second memory cell and a pair of second bit lines, said second memory cell being selectively coupled to a corresponding bit line of said pair of second bit lines according to a voltage level of a second word line; a pair of first column lines selectively coupled to said pair of first bit lines or said pair of second bit lines, said pairs of first and second bit lines being located between the first column lines of said pair of first column lines; a coupling control circuit that provides control to selectively couple said pair of first column lines to said pair of first bit lines or said pair of second bit lines according to first select information; a first read register selectively coupled to said pair of first column lines; and a read control circuit that provides control to selectively couple said first read register to at least one column line of said pair of first column lines according to a second select information.