Patent ID: 6370054
Filing Date: 2002-04-09
Classification: G11C,H01L

Abstract:
A dynamic RAM, comprising:a plurality of memory mats comprising a plurality of bit lines; a plurality of word lines; and a plurality of memory cells coupled to said plurality of bit lines and said plurality of word lines, said plurality of memory mats being placed in a direction of said bit line, each of said plurality of memory cells comprising a MOSFET comprising a capacitor having first and second electrodes; a gate coupled to corresponding one of said plurality of word lines; and a source-drain path, one of which is coupled to corresponding one of said plurality of bit lines and the other of which is coupled to said first electrode of said capacitor; and a sense amplifier array comprising a plurality of latch circuits being provided in areas between said memory mats placed in said bit line direction, respectively, a pair of input/output nodes of which is connected to a pair of bit lines placed separately in said memory mats on both sides of said area, wherein, for a general memory mat other than both end portions in said bit line direction, word lines in any one of said memory mats are activated while, for end memory mats provided on said both end portions in said bit line direction, word lines of said both memory mats are activated together.