Patent ID: 7515485
Filing Date: 2009-04-07
Classification: G11C

Abstract:
1. A flash memory, including: a first latch including a first latch output and a first latch input to couple to at least one external input to receive at least one command, at least one memory address, and a plurality of data bits; a command decoder including a command decoder input and a command decoder output, the command decoder input to couple to the first latch output; a command latch including a first command latch input, a second command latch input, and a command latch output, the first command latch input to couple to the command decoder output, and the second command latch input to couple to a write command output of an internal clock control generator; and a command register including a first command register input and a second command register input, the first command register input to couple to the command latch output, and the second command register input to couple to an internal latch command output of the internal clock control generator.