Patent ID: 6510076
Filing Date: 2003-01-21
Classification: G11C

Abstract:
A method of reducing susceptibility of a memory bit cell to single event upset effects, said bit cell comprising cross-coupled first and second inverters, each one of said inverters further comprising a pull-up transistor and a pull-down transistor having series-connected terminals defining a storage node, a first pass transistor coupled between a first bit line and a first one of said storage nodes, a second pass transistor coupled between a second bit line and a second one of said storage nodes, said pass transistors further coupled to a word line for controllably switching said pass transistors on or off, each one of said transistors having a drawn width to drawn length W/L ratio, said method comprising:(a) increasing said W/L ratio for each one of said pull-up transistors and for each one of said pass transistors, without increasing said W/L ratio for said pull-down transistors, until said bit cell has a selected write margin value; (b) applying a first logic signal to said word line while writing data into said bit cell, said first logic signal turning said pass transistors fully on during said writing; (c) applying a second logic signal to said word line while reading data from said bit cell, said second logic signal turning said pass transistors partially but not fully on during said reading; and, (d) applying a third logic signal to said word line while neither writing data into said bit cell nor reading data from said bit cell, said third logic signal turning said pass transistors off.