Patent ID: 8154076
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having first and second active regions that are isolated from each other by a device isolation; a first unit transistor disposed in the first active region; a second unit transistor disposed in the second active region; and an interconnection layer extending over the first and second unit transistors and crossing over the device isolation, the first unit transistor comprising a first pillar providing a first channel region, a first gate insulating film formed on a side surface of the first pillar, a first gate electrode formed on the first gate insulating film, a first upper diffusion region disposed near a top part of the first pillar, a first lower diffusion region disposed near a bottom part of the first pillar, a first contact plug provided in contact with the first upper diffusion region, and a second contact plug provided in contact with the first lower diffusion region, the second unit transistor comprising a second pillar providing a second channel region, a second gate insulating film formed on a side surface of the second pillar, a second gate electrode formed on the second gate insulating film, a second upper diffusion region disposed near a top part of the second pillar, a second lower diffusion region disposed near a bottom part of the second pillar, a third contact plug provided in contact with the second upper diffusion region, a fourth contact plug provided in contact with the second lower diffusion region, the interconnection layer having a first end and a second end, the first end being in contact with the fourth contact plug and the second end being in contact with the first contact plug so that the first upper diffusion region and the second lower diffusion region are electrically connected in series to each other.