Patent ID: 6510480
Filing Date: 2003-01-21
Classification: G06F

Abstract:
A data transfer circuit comprising:a first data holding means having a plurality of data holding circuits which have a first bit width; a second data holding means having at least one data holding circuit which has a second bit width different from the first bit width, said second data holding means being connected to some of the data holding circuits in said first data holding means; and a data output selecting means for selecting data held by some of the data holding circuits in said first data holding means, or data held by the at least one data holding circuit in said second data holding means; wherein, when an interruption request signal is asserted to said data transfer circuit, part of the data held by said first data holding means is provided to said second data holding means; and wherein, when the interruption request signal is negated, said data output selecting means selects the data of said second data holding means to output the data.