Patent ID: 6621317
Filing Date: 2003-09-16
Classification: H03K,H03L

Abstract:
A clock control circuit comprising:a control circuit unit comprising: an adding circuit that increments an output on receipt of an input clock by a predetermined unit m, wherein the m is a positive integer and is variable set; and a decoder that decodes the output of the adding circuit to generate a control signal; and a phase adjustment circuit that receives an input signal and the control signal to generate an output clock wherein a phase of said output clock to a corresponding edge of the input clock is incremented by a unit phase differential value m &Dgr;&PHgr;, on each cycle of said input clock, where the &Dgr;&PHgr; is a predetermined value such that n &Dgr;&PHgr; is equal to one clock period (tCK) of said input clock, said n being a positive integer, whereby a frequency of said output clock is 1/(tCK+m &Dgr;&PHgr;).