Patent ID: 8462573
Filing Date: 2013-06-11
Classification: G11C

Abstract:
1. A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, wherein the bitline isolation includes: the sense amplifier being responsive to receipt of at least one sensing activation signal from a controller to initiate a signal amplification process at the first and second input/output nodes; the signal amplification process causes the first input/output node to tend towards a first final electric potential and the second input/output node to tend towards a second final electric potential different from the first final electric potential, wherein said electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node is carried out after said amplification process has been initiated but before the second input/output node has reached the second final electric potential.