Patent ID: 8164948
Filing Date: 2012-04-24
Classification: G11C

Abstract:
1. An SRAM integrated circuit comprising: at least two transistors, each of the transistors having a source terminal, a drain terminal, and a gate terminal; at least two magneto-resistive components (MRCs), each of the MRCs having an upper terminal and a lower terminal, wherein the MRCs can be selectively programmed to a state of high resistance or to a state of low resistance; and wherein the MRCs are coupled in series with the transistors, wherein the upper terminal of a first MRC is connected to a voltage source, wherein the lower terminal of the first MRC is connected to the source terminal of a first transistor, wherein the drain terminal of the first transistor is connected to the drain terminal of a second transistor, wherein the upper terminal of a second MRC is connected to the source terminal of the second transistor, and wherein the lower terminal of the second MRC is connected to a common ground terminal.