Patent ID: 8527676
Filing Date: 2013-09-03
Classification: G11C,H03M,H04J,H04L

Abstract:
1. A method for reducing data latency during deserialization of one or more lanes of serial data, the method comprising: (a) providing a double buffer having an upper buffer half and a lower buffer half, (b) sequentially writing pairs of deserialized bits of the serial data to the upper buffer half at a first clock speed of a first clock signal, (c) when the upper buffer half is full, reading all data from the upper buffer half in parallel into a physical coding sublayer at a second clock speed of a system clock signal, wherein the second clock speed is less than and dependent on the first clock speed, (d) sequentially writing pairs of deserialized bits of the serial data to the lower buffer half at the first clock speed, (e) when the lower buffer half is full, reading all data from the lower buffer half in parallel into the physical coding sublayer at the second clock speed, and (f) aligning the data from the upper buffer half and the lower buffer half in the physical coding sublayer.