Patent ID: 8898529
Filing Date: 2014-11-25
Classification: G01R

Abstract:
1. A circuit arrangement for controlling a masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs, wherein m is <N and wherein the masked test data are compacted by a compactor with N data inputs and n data outputs and m<N applies, the circuit arrangement comprising: a first circuit component for masking the test data, which comprises N data inputs for input of N-digit binary unmasked test data, N control inputs for input of the binary control signals for masking the corresponding digits of the test data and N outputs for outputting the values of the masked test data bits corresponding to the control signals; and a second circuit component with N binary inputs and N binary outputs for providing control signals, such that the N binary outputs are connected to the N control inputs of the first circuit component and wherein the first circuit component has a first serially loadable register with N memory elements, a second loadable register with likewise N memory elements for storing test pattern-dependent masking data and a third serially loadable register likewise with N memory elements for storing test-dependent masking data, wherein the following applies: