Patent ID: 6940754
Filing Date: 2005-09-06
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device having a write operation mode, a read operation mode, and an erase operation mode, the nonvolatile semiconductor memory device comprising: a memory cell array in which a plurality of nonvolatile semiconductor memory cells in which data is electrically erased/written are arranged in a matrix, some of the plurality of memory cells form a normal memory cell group including a normal memory space, remaining memory cells among the plurality of memory cells form a redundancy memory cell group including a redundancy memory space, the plurality of memory cells are divided into a plurality of cell blocks for each unit by which stored data is electrically collectively erased, and the plurality of memory cells in each cell block are formed in a plurality of semiconductor regions electrically isolated from each other; a plurality of normal word lines which are disposed in the respective cell blocks and which are connected to the memory cells in the normal memory cell group and which select the memory cells in the normal memory cell groups; a plurality of redundancy word lines which are disposed in the respective cell blocks and which are connected to the memory cells in the redundancy memory cell group and which are replaced with the normal word lines and used, and which select the memory cells in the redundancy memory cell group; a plurality of bit lines which are disposed in the respective cell blocks and which are connected to the memory cells in the normal memory cell group and the memory cells in the redundancy memory cell group; a well control circuit which is connected to the plurality of semiconductor regions and which applies a first voltage having a positive polarity to the semiconductor region corresponding to at least one cell block among the plurality of cell blocks, at the time of the erase operation mode; and a row decoder which is connected to the plurality of cell blocks and which selects the plurality of cell blocks, the plurality of normal word lines, and the plurality of redundancy word lines and which supplies a second voltage having a negative polarity to the selected normal word line corresponding to a normal memory cell in the selected cell block at the time of the erase operation mode to control the erase operation of the memory cell and which supplies a third voltage having a potential difference from the first voltage is smaller than that between the first voltage and second voltage to the selected normal word line corresponding to a defective memory cell and the redundancy word line which has not been replaced.