Patent ID: 7923818
Filing Date: 2011-04-12
Classification: H01L,H03J

Abstract:
1. A varactor stack circuit arrangement, comprising: two varactor elements each having two terminals and comprising: a junction region, in which the depletion capacitance of the varactor element varies when a reverse bias voltage is applied to the varactor element, wherein the varactor element has an exponential depletion capacitance-voltage relation, in which the junction region comprises a single sided junction; the varactor element is provided with a doping profile substantially defined by: wherein N(x) is the varactor element's doping concentration in one dimension as a function of x (for x>x the junction region comprises a filling layer in an interval of distances lower than x the two varactor elements are connected in an anti-series configuration, such that a control node is provided by two interconnected terminals and two RF connection nodes by the other terminals.