Patent ID: 6745302
Filing Date: 2004-06-01
Classification: G11C

Abstract:
A semiconductor memory enabling a read modify write operation of data, comprising:a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read: a read address decoding means for independently decoding an address of a read memory cell in response to a first designated address; a write address decoding means for independently decoding a write address of a memory cell in response to a second designated address; a data reading means for reading data of a memory cell addressed by said decoded read address in said read address decoding means; a data writing means for writing data to a memory cell addressed by said decoded write address in said write address decoding means; and an address delay means by which said decoded write address decoded by said write address decoding means is delayed by a predetermined time from a read address decoded by said read address decoding means, said predetermined time being set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplished in a pipeline manner by said basic synchronized pulse.