Patent ID: 6040228
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A capacitance-forming method for forming a capacitance having a predetermined capacity, comprising steps of:i) plurally arraying an almost straight plurality of unit capacitor electrodes in a first layer in a semiconductor system;ii) forming common electrodes in a second layer adjacent to said first layer to be faced to said unit capacitor electrodes;iii) forming a plurality of unit capacitances by ii);iv) forming a plurality of first and second conductors respectively connected to said first unit capacitor electrode layer and said common electrode layer in a third layer;v) forming first and second metal terminal-contacting portions penetrating up to said third layer respectively from said unit capacitor electrodes and common electrodes;vi) respectively connecting approximately rectangular first and second metal terminal head portions to said first and second metal terminal-contacting portions in said third layer;vii) connecting said unit capacitor electrodes and common electrodes to said first and second conductors, respectively, through said first and second metal terminal head portions, respectively;viii) connecting unit capacitor electrodes adjacent to each other to differnet first conductors; andix) parallelly connecting a predetermined number of unit capacitances;wherein said first conductor adjacent to said second conductor is curved for detouring around said second metal terminal head portion.