Patent ID: 8330265
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A packaged transistor device, comprising: a transistor die including a plurality of transistor cells, each of the plurality of transistor cells including a single transistor including a single control terminal and a single output terminal; an input lead; and an input matching network coupled between the input lead and the transistor die, the input matching network including a plurality of discrete capacitors having respective input terminals, wherein the input terminals of the discrete capacitors are coupled to the input lead and to the control terminals of respective ones of the transistor cells wherein each transistor cell is connected to a different one of the plurality of discrete capacitors, wherein the plurality of discrete capacitors is provided as a capacitor block between the input lead and transistor die, and wherein the capacitor block comprises a common ground terminal and a plurality of discrete input terminals corresponding to the input terminals of the discrete capacitors.