Patent ID: 6849550
Filing Date: 2005-02-01
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device including a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring, the method comprising the steps of: forming the connection hole by etching part of the interlayer insulation film, through chemical reaction or physical reaction until part of a surface of the lower layer wiring is exposed; etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring to form an etching inhibition film on part of the surface of the lower layer wiring and on a wall of the connection hole; and continuously performing etching under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.