Patent ID: 6990537
Filing Date: 2006-01-24
Classification: G06F

Abstract:
1. A method for controlling communication on a bus connecting a first processor, a second processor, and a device, the method comprising: transmitting a first control signal from the first processor to the second processor via a control signal line to cause the second processor to enter a reset state, wherein, while in the reset state, the second processor ceases to execute instructions and a bus connection of the second processor enters a high-impedance state; transferring data between the device and the first processor via the bus then setting a bus connection of the first processor to the high-impedance state, while the second processor is in the reset state; and transmitting a second control signal from the first processor to the second processor via the control signal line to transition the second processor from the reset state to a release state, wherein, while in the release state, the second processor executes instructions and the bus connection of the second processor exits the high-impedance state.