Patent ID: 8652855
Filing Date: 2014-02-18
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps of: providing a semiconductor substrate; forming a plurality of lower components in and on said substrate, said lower components including transistors; forming a PMD layer over said lower components and said substrate; etching lower contact holes through said PMD layer, said lower contact holes including: forming a layer of metal lower liner in said lower contact holes and over a top surface of said PMD layer; forming a layer of lower contact metal on said lower liner layer, said lower contact metal layer extending into said lower contact holes and over said top surface of said PMD layer, such that a top surface of said lower contact metal layer is above said top surface of said PMD layer; removing said lower contact metal and said lower liner from over said top surface of said PMD layer, thus forming lower contacts in said PMD layer, making electrical connections to said lower components and extending to a top surface of said PMD layer, said lower contacts having said metal lower liner on lateral and lower surfaces of said lower contacts and said lower contact metal on said lower liner, said lower contacts including: forming upper components over said PMD layer, wherein at least a portion of said upper components are disposed over, and make electrical connection to top surfaces of, instances of a portion of said lower contacts; forming an ILD layer over said upper components and said PMD layer; etching upper contact holes through said ILD layer, said upper contact holes including: forming a layer of metal upper liner in said upper contact holes and over a top surface of said ILD layer; forming a layer of upper contact metal on said upper liner layer, said upper contact metal layer extending into said upper contact holes and over said top surface of said ILD layer, such that a top surface of said upper contact metal layer is above said top surface of said ILD layer; removing said upper contact metal and said upper liner from over said top surface of said ILD layer, thus forming upper contacts in said ILD layer, making electrical connections to instances of said lower contacts and instances of said upper components, and extending to a top surface of said ILD layer, said upper contacts having said metal upper liner on lateral and lower surfaces of said upper contacts and said upper contact metal on said upper liner, said upper contacts including: forming a level of metal interconnects over said ILD layer, said metal interconnects having metal interconnect lines which make electrical connections to top surfaces of said conventional stacked contacts and said stacked annular contacts; such that said integrated circuit includes a plurality of annular stacked contacts, an instance of said annular stacked contacts being a combination of an instance of said annular lower contacts electrically connected to a corresponding instance of said annular upper contacts, in which said instance of said annular lower contacts makes electrical connection to an instance of said lower components and said instance of said annular upper contacts makes electrical connection to an instance of said metal interconnect.