Patent ID: 6162684
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method of forming a flash memory cell, comprising:forming a tunnel oxide on a substrate;forming a first polysilicon layer over the tunnel oxide;forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer made by low pressure chemical vapor deposition at a temperature from about 600.degree. C. to about 850.degree. C. using SiH.sub.4 and N.sub.2 O, annealing in an NH.sub.3 atmosphere at a temperature from about 800.degree. C. to about 900.degree. C., and wet oxidizing using O.sub.2 and H.sub.2 at a temperature from about 820.degree. C. to about 880.degree. C.;forming a second polysilicon layer over the insulating layer;etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; andforming a source region and a drain region in the substrate, thereby forming at least one memory cell.