Patent ID: 9183614
Filing Date: 2015-11-10
Classification: G06F,G06T

Abstract:
1. A method of program execution by a master processor coupled to at least two data processors, wherein each data processor includes a data memory partitioned into a number of identical regions, said method comprising: fetching a first instruction from an instruction memory in the master processor; conveying the first instruction to an instruction buffer of a first data processor of the at least two data processors, for execution using data in a first region of the data memory of the first data processor; determining whether execution of the first instruction by the first data processor requires movement of data between the data memory of the first data processor and the data memory of a different data processor; if execution of the first instruction does not require movement of data between the first data processor and a different data processor, continuing to fetch and convey to the instruction buffer subsequent instructions until determining that a conveyed instruction requires said movement of data between data processors; upon determining that execution of the conveyed instruction does require movement of data between the first data processor and a different data processor, retrieving the first instruction, and conveying, the first instruction to the instruction buffer of the first data processor, for execution using data memory in a consecutive adjacent region of the data memory of the first data processor; and repeating, for each adjacent region of the data memory in the first data processor, conveyance of a sequence of instructions ranging from the first instruction through the instruction requiring said movement of data between data processors, for execution using data stored in the respective region.