Patent ID: 7446389
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. An apparatus for reducing voltage noise for an integrated circuit (IC) device, comprising: a package which is configured to be sandwiched between the IC device and a circuit board, wherein the package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device, wherein the package includes: a plurality of bypass capacitors, each including a set of internal planes, integrated into the substrate in the package between the top buildup layers and the bottom buildup layers and coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device, wherein the internal planes of the bypass capacitors extend downward from the top surface of the substrate in the package in a direction that is normal to the top surface of the substrate in the package.