Patent ID: 6524895
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising the steps of:forming a semiconductor layer over a substrate having an insulation surface; patterning said semiconductor layer to form at least a first and a second island semiconductor layers; forming a gate insulation film in contact with said first and second island semiconductor layers; adding an impurity element of one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region; forming a first conductor layer in contact with said gate insulation film after adding the impurity element of the one conductivity type; forming a second gate electrode overlapping with said second island semiconductor layer by patterning said first conductor layer; adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region; forming a first gate electrode overlapping with said first island semiconductor layer by patterning said first conductor layer after adding the impurity element of the conductivity type opposite to said conductivity type; and adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region.