Patent ID: 8754471
Filing Date: 2014-06-17
Classification: H01L,Y02E

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate having a main surface; a source region and a drain region formed apart from each other in the main surface; a gate electrode layer formed over the main surface sandwiched between the source region and the drain region; a gate insulation film formed between the gate electrode layer and the semiconductor substrate; a first conductive layer formed in such a manner as to be in contact with a surface of the source region; a second conductive layer formed in such a manner as to be in contact with a surface of the drain region; and an element isolation film formed in the main surface of the semiconductor substrate, wherein a recess is formed in the main surface in such a manner as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region, the first conductive layer is in contact with a sidewall of the recess and a flat area of the source region above the recess and the second conductive layer is in contact with a sidewall of the recess and a flat area of the drain region above the recess, and the gate electrode layer extends into the semiconductor substrate below a top surface of the element isolation film, and the gate insulation film is located below the top surface of the element isolation film.