Patent ID: 6060357
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A method of manufacturing a flash memory cell on a substrate having a pad oxide layer and a mask layer the method comprising steps of:forming a shallow trench isolation to penetrate through the mask layer and the pad oxide layer and into the substrate;forming a patterned photoresist over the substrate;respectively forming a first opening and a second opening in the shallow trench isolation and the mask layer exposed by the patterned photoresist, wherein the second opening exposes the pad oxide layer and the first and the second openings are adjacent to each other;performing a buried bit line implantation step to form a doped region in the substrate under the pad oxide layer exposed by the second opening;removing the patterned photoresist;removing the mask layer;filling the first opening with a polysilicon material;removing the pad oxide layer; andforming a floating gate and a controlling gate over the substrate, wherein a portion of the floating gate is on the gate oxide layer above the doped region.