Patent ID: 8418159
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. An apparatus, coupled with computer memory storage, for optimizing a transaction comprising an initial sequence of computer operations, comprising: a processing unit configured to identify one or more idempotent operations comprised within the initial sequence, wherein each of the computer operations of the initial sequence has a respective sequence number (sn), a function (k) and a variable (v) that receives the value of the function (k), the identifying comprising: wherein the processing unit is further configured to reorder the initial sequence to form a reordered sequence comprising a first sub-sequence of the computer operations followed by a second sub-sequence of the computer operations, the second sub-sequence comprising only the one or more idempotent operations, wherein the reordered sequence is a computationally efficient representation of the initial sequence that improves efficiency of the transaction in the event of failure.