Patent ID: 8769363
Filing Date: 2014-07-01
Classification: G01R,G11C

Abstract:
1. A test apparatus that tests a device under test based on pattern data, comprising: a plurality of pattern output sections that each output pattern data corresponding to an input pattern input thereto, in synchronization with a predetermined test period, wherein each pattern output section has two operating modes that are a normal mode in which one piece of pattern data is output in each test period and a high-speed mode in which a piece of pattern data is output in each of a plurality of partial periods obtained by dividing the test period, each pattern output section has an input switching section that, in the normal mode, outputs the input pattern input to the pattern output section including the input switching section and, in the high-speed mode, outputs the input pattern input to another pattern output section, and in the high-speed mode, each pattern output section outputs, as the pattern data corresponding to at least one of the partial periods, the pattern data corresponding to the input pattern input to the pattern output section and the pattern data corresponding to the input patterns input to other pattern output sections.