Patent ID: 8098227
Filing Date: 2012-01-17
Classification: G09G,G11C,H03K

Abstract:
1. A gate driving circuit comprising stages, the stages being cascaded with each other and each comprising: a pull-up part which pulls up a gate voltage to an input clock; a carry part which pulls up a carry voltage to the input clock; a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part; a pull-down part receiving a subsequent gate voltage from a subsequent stage to lower the gate voltage to the off-voltage; a holding part which holds the gate voltage at an off-voltage; and an inverter for at least one of turning on the holding part and turning off the holding part based on an inverter clock, wherein a high level of the inverter clock in a given horizontal scanning period (1H) temporally precedes a high level of the input clock by a predetermined time interval in the given horizontal scanning period (1H).