Patent ID: 8611143
Filing Date: 2013-12-17
Classification: G11C

Abstract:
1. A memory circuit comprising: a first transistor which is a spin MOSFET of a first conductivity type, the first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor which is either a spin MOSFET of the first conductivity type or a MOSFET of the first conductivity type, the second transistor including a third source/drain electrode connected to the second source/drain electrode of the first transistor, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor which is either a p-channel spin MOSFET or a p-channel MOSFET, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode of the first transistor, the fourth transistor which is either an n-channel spin MOSFET or an n-channel MOSFET, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode of the third transistor, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode of the first transistor, and at least one of the third transistor and the fourth transistor in the inverter circuit being a spin MOSFET; and an output terminal connected to the sixth source/drain electrode of the third transistor, an output of the inverter circuit being sent from the output terminal.