Patent ID: 7829168
Filing Date: 2010-11-09
Classification: G03F,Y10T

Abstract:
1. An in-process plurality of patterned wafers wherein: (a) each patterned wafer has exposed thereon, a temporary patterns summing layer (TPSL) containing a first set of patterned features composed of a first material and representing a first of overlaid photomask patterns and containing a second set of patterned features composed of a different second material and representing a second of the overlaid photomask patterns, the TPSL being for performing further patterning of the patterned wafer in subsequent processing; and wherein (b) at least one of the in-process patterned wafers has had its exposed TPSL inspected by way of one or more preselected measurement techniques to verify that the first and second sets of patterned features are positioned relative to at least one another in accordance with a predetermined spacing specification.