Patent ID: 6510102
Filing Date: 2003-01-21
Classification: G11C

Abstract:
A method of accessing memory cells in a memory device including a plurality of memory-cell arrays, each memory-cell array including a plurality of memory cells and the arrays collectively forming a primary and a redundant memory space, the method comprising:placing the memory device in a test mode of operation; generating a plurality of memory addresses as row addresses and column addresses from a plurality of row address sources and column address sources, respectively, the memory addresses being generated internal to the memory device and the memory addresses corresponding to memory cells in the primary and redundant memory spaces, wherein the plurality of row address sources comprises a normal row address source defined by a row address applied to the memory device, a refresh row address generation source, and a functional testing row address generation source; selecting one of the plurality of row address sources and column address sources; and accessing the memory cells in the primary and redundant memory spaces corresponding to the selected row and column address sources.