Patent ID: 6208211
Filing Date: 2001-03-27
Classification: H03L

Abstract:
A phase lock loop comprising:a current controlled oscillator, adapted to provide an output signal ICOS having a frequency of Fico, wherein Fico is controlled by a current input signal Idac, the current controlled oscillator having an input resistance Rin; Rin is proportional to Idac;a frequency divider, coupled to the current controlled oscillator, for receiving ICOS and providing a frequency divider output signal FD, the frequency of FD is Ffd and Ffd=(Fico/N), N>0;a phase detector, coupled to the frequency divider and adapted to be coupled to a reference signal for receiving a reference signal REF, REF having a frequency of Fref; wherein the phase detector receives REF and FD and provides an error signal ERS that reflects the phase difference between REF and FD;a loop filter, coupled to the phase detector; for filtering ERS;a sigma delta modulator, coupled to the loop filter, for performing sigma delta modulations upon the output signal of the loop filter, and for providing a digital sigma delta modulated control signal SDO;a digital to analog converter, coupled to the sigma delta modulator and to the current controlled oscillator, for converting SDO to Idac and providing Idac to the current controlled oscillator; anda capacitor, coupled to the current controlled oscillator, the capacitor and Rin generate a pole Fpole in the transfer function of the phase locked loop.