Patent ID: 6681193
Filing Date: 2004-01-20
Classification: G01R

Abstract:
A method for testing an integrated circuit of a plurality of substantially identical integrated circuits having n channel transistors a p channel transistors, the method comprising:forming an n channel measurement transistor and a p channel measurement transistor in each integrated circuit; biasing the measurement transistors in a cut-off zone; measuring sub-threshold currents of the measurement transistors; calculating sub-threshold currents by unit of channel area for the integrated circuit n channel and p channel transistors from the measured sub-threshold current and from channel areas of the measurement transistors; obtaining sums of the channel areas of the integrated circuit n channel and p channel transistors that, with the integrated circuit in an idle condition, are in a cut-off condition; calculating products of the sub-threshold currents by unit of channel area calculated for the sums of the channel areas obtained; calculating current drawn by the integrated circuit an idle condition by adding together the products; adding a predefined current increase to the calculated current drawn to establish a current draw threshold; powering the integrated circuit in an idle condition; measuring a current drawn by the integrated circuit; comparing the current drawn with the current draw threshold; and accepting the integrated circuit if the current drawn is lower than the current draw threshold, and rejecting the integrated circuit if the current drawn is higher than the current draw threshold.