Patent ID: 7782326
Filing Date: 2010-08-24
Classification: G06K

Abstract:
1. An apparatus for videoprocessing comprising: a system bus; and at least one videoprocessing path, each videoprocessing path including: wherein the parallel video processor comprises a series of 3N 2 bits per pixel input registers, wherein N is an integer, N≧1, wherein a lower third series of the input registers is configured to selectively receive a lower half of the set of input pixels or an output from one or more of the series of input registers, wherein a middle third series of the input registers is configured to selectively receive a lower half of the set of input pixels, an upper half of the set of input pixels, or an output from one or more of the series of input registers, and wherein a top third series of the input registers is configured to either receive an upper half of the set of input pixels or have the content of the top third series of the input registers cleared.