Patent ID: 6822920
Filing Date: 2004-11-23
Classification: G11C

Abstract:
A synchronous SRAM-compatible memory device having a DRAM memory array including a plurality of DRAM cells arranged in a matrix form defined by rows and columns, and operating in synchronization with a reference cl signal, the synchronous SRAM-compatible memory device comprising:a data input/output unit for controlling input and output of data to and from the DRAM memory array; a state control unit for controlling an operation of accessing the DRAM memory array and an operation of the data input/output unit, the state control unit receiving a chip enable signal externally provided to enable the synchronous SRAM-compatible memory device; a refresh timer for generating a refresh request signal activated at regular intervals; a clock period modulating unit for providing a pre-control signal to activate a non-executed refresh request signal, the pre-control signal having a logic state transition in response to every n-th clock pulse of the reference clock signal generated during an inactivation interval of the chip enable signal; and a refresh control unit for generating a refresh control signal to control a refresh operation for the DRAM memory array, the refresh control signal being activated in response to the logic state transition of the pre-control signal.