Patent ID: 7388772
Filing Date: 2008-06-17
Classification: G11C

Abstract:
1. A latch circuit comprising first, second, third, fourth, fifth and sixth MOS transistors, each having a source, a drain and a gate, the first and second transistors being connected in series such that a source and drain of the first transistor are connected between a first node and a second node and the source and drain of the second transistor are connected between a third node and the second node, the first transistor having a first conductivity type and the second transistor having a second conductivity type; the third and fourth transistors being connected in series such that a source and drain of the third transistor are connected between the first node and a fourth node and the source and drain of the fourth transistor are connected between the third node and the fourth node, the third transistor having the first conductivity type and the fourth transistor having the second conductivity type; the source and drain of the fifth transistor being connected between the fourth node and the gates of the first and second transistor; and the source and drain of the sixth transistor being connected between the third node and the gates of the third and fourth transistors.