Patent ID: 7928755
Filing Date: 2011-04-19
Classification: G01R

Abstract:
1. Apparatus for testing at least one device under test (DUT), the apparatus comprising: a tester input/output (I/O) node; a plurality of DUT I/O nodes; a plurality of remote pin electronics blocks, each of the remote pin electronics blocks providing a first test function, and each of the remote pin electronics blocks being coupled between the tester I/O node and a respective one of the DUT I/O nodes; a bypass circuit coupled between the tester I/O node and each of the plurality of DUT I/O nodes, the bypass circuit providing signal bypass paths between the tester I/O node and respective ones of the plurality of DUT I/O nodes, and each of the signal bypass paths bypassing the first test function provided by a respective one of the remote pin electronics blocks; and a control system configured to enable and disable the bypass circuit and enable one of the signal bypass paths at a time.