Patent ID: 6329245
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method of forming floating gates and control gates for flash memory transistors, comprising the steps in the sequence as follows:(a) providing a semiconductor substrate;(b) forming Field Oxide isolation regions in the surface of said substrate;(c) forming doped source and drain regions in the surface of said substrate;(d) forming a first half of floating gates for said flash memory transistors, wherein said forming a first half of floating gates for said flash memory transistors is:(i) forming layers of first tunnel oxide on the surface of said substrate;(ii) depositing a first layer of polysilicon 1 over said surface of said substrate thereby including the surface of said Field Oxide regions; and(iii) pattering said first layer of polysilicon 1 whereby said patterning essentially leaves in place said layer of poly 1 above the surface of said substrate between odd numbered pairs of Field Oxide regions thereby partially covering the Field Oxide regions that form said odd numbered pairs of Field Oxide regions whereby furthermore said poly 1 is essentially removed from above the surface of said substrate that is located between Field Oxide regions that form even numbered pairs of Field Oxide regions thereby furthermore partially removing said poly 1 from the Field Oxide regions that form said even numbered pairs of Field Oxide regions;(e) forming a second half of floating gates for said flash memory transistors; and(f) forming control gates for said flash memory transistors.