Patent ID: 6611030
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate having a top surface and a bottom surface and having an active region comprising at least two transistor regions, at least one ground region and at least two field regions; field oxide films formed on the top surface of the substrate within the field regions gate electrodes formed over predetermined portions of the top surface of the substrate corresponding to the transistor regions; and gate oxide films interposed between the substrate and the corresponding gate electrodes; impurity regions doped with first and second conductive impurities, formed on both sides of each of the gate electrodes in the transistor regions; a layer-insulating film having a plurality of contact holes formed over the top surface of the semiconductor substrate, the field oxide films, the gate electrodes and the impurity regions, the layer-insulating film exposing portions of an upper surface of the substrate corresponding to the ground region and the impurity regions; first, second and third wiring layer patterns formed on the layer-insulating film and in the contact holes; a protection film pattern having a plurality of contact holes formed over the top surface of the semiconductor substrate, the field oxide films, the gate electrodes, the impurity regions, the laver-insulating film and the first, second and third wiring layer patterns, the protection film pattern for thereby forming bonding pads corresponding to the first, second and third wiring layer patterns; a hold formed in a portion of the bottom surface of the substrate corresponding to the ground region; and a metal layer formed on the bottom surface of the substrate and on an inner surface of the hole, wherein the second wiring layer pattern is electrically coupled to the ground region and the at least two transistor regions.