Patent ID: 6345381
Filing Date: 2002-02-05
Classification: G06F,G11C,H03K

Abstract:
A design tool to design a logic circuit, comprising:a syntax statement, said syntax statement further comprises encoded information that specifies a logical function of a logic circuit having a plurality of transistors arranged in a configuration that accomplishes said logical function, said configuration further includes a plurality of internal nodes that includes a virtual ground node and one or more evaluate nodes; wherein said encoded information further comprises a gate expression that includes at least one of the following: a first operator that assigns a signal value to control the gate of a specific transistor of said plurality of transistors, a second operator that indicates the position of at least two specific transistors of said plurality of transistors relative to each other within said configuration, or a third operator that either assigns a value to a specific internal node or indicates the position of a specific transistor of said plurality of transistors relative to said virtual ground node; and a compiler that processes and decodes said syntax statement, said compiler produces from said syntax statement a behavioral model of the circuit and a physical circuit description of said logic circuit.