Patent ID: 6303460
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device with trench isolation structure, comprising the steps of:(a) preparing a semiconductor substrate having an alignment mark area and an element formation area;(b) forming first and second trenches at one time in upper portions of said alignment mark area and said element formation area of said semiconductor substrate, respectively, said first and second trenches having almost the same depth at their bottom surfaces from a surface of said semiconductor substrate;(c) forming an insulating film entirely on said surface of said semiconductor substrate;(d) forming a resist pattern at least on said insulating film, corresponding to the peripheral vicinity region external to said first trench in said alignment mark area;(e) removing said insulating film with said resist pattern used as a mask;(f) further removing said insulating film after removing said resist pattern, said step (f) being performed so as to leave a part of said insulating film in said first trench and said insulating film which is buried in said second trench, said first trench after said step (f) being defined as an alignment mark;(g) forming an electrode layer entirely on said semiconductor substrate; and(h) recognizing a position of said alignment mark to pattern said electrode layer on said element formation area,wherein said alignment mark has a height difference between a center portion of said first trench and a peripheral portion other than said center portion.