Patent ID: 8873559
Filing Date: 2014-10-28
Classification: H04L

Abstract:
1. A parallel computing system, comprising: a plurality of nodes each of which comprises at least one processor and at least one adapter; an interconnection network comprising a plurality of crossbar switches comprising at least a first plurality of switches and a second plurality of switches, wherein the plurality of nodes are connected through a plurality of shared links connecting the first plurality of switches and the second plurality of switches, wherein a table specifies each separate single, static route set between each of the plurality of nodes through the plurality of shared links; and a pipelined broadcast manager for scheduling a plurality of broadcast steps for a pipelined broadcast through the plurality of crossbar switches according to each separate, single static route set through at least one of an inter-switch broadcast phase during which at least one packet is passed from at least one switch of the plurality of crossbar switches to another of the plurality of crossbar switches and an intra-switch broadcast phase during which the at least one packet is passed only among a selection of nodes from among the plurality of nodes connected to the another of the plurality of crossbar switches.