Patent ID: 6734507
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A semiconductor device comprising:first and second semiconductor bases; a first memory cell which is formed on the first semiconductor base and is comprised of a first capacitor and a first MOS transistor, wherein the first MOS transistor has a source region, a drain region and a gate electrode; a second memory cell which is formed on the first semiconductor base and is comprised of a second capacitor and a second MOS transistor, wherein the second MOS transistor is formed in a vicinity of the first MOS transistor and has a source region, a drain region and a gate electrode, and wherein one of the source and drain regions of the first MOS transistor and one of the source and drain regions of the second MOS transistor is a shared region, wherein the shared region is connected to a bit line through which data is read out from the first or second memory cells, another one of the source and drain regions of the first MOS transistor is connected to the first capacitor, and another one of the source and drain regions of the second MOS transistor is connected to the second capacitor; and a peripheral circuit which is formed on the second semiconductor base and includes a third MOS transistor, wherein the third MOS transistor has a source region, a drain region and a gate electrode, and the source region or the drain region of the third MOS transistor is wider than the source and drain regions of the first and second MOS transistors, wherein the source region, the drain region and the gate electrode of the third MOS transistor are comprised of refractory metallic suicide, the gate electrodes of the first and second MOS transistors are comprised of refractory metallic silicide, and the source and drain regions of the first and second MOS transistors are not comprised of refractory metallic silicide.