Patent ID: 7188296
Filing Date: 2007-03-06
Classification: H03M

Abstract:
1. An apparatus comprising: a check bit encoder circuit coupled to receive a data block, wherein the check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits; and a check/correct circuit coupled to receive an encoded data block, the check/correct circuit configured to detect an error in data from one of a plurality of components and correct the error using the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block; wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein each of the N columns comprises data bits from a respective one of the plurality of components, and wherein the first plurality of check bits form a first column of the array, and wherein each of the first plurality of check bits covers a row of the array, and wherein the second plurality of check bits form a second column of the array and are defined to cover bits in the array according to a plurality of check vectors, each of the plurality of check vectors corresponding to a different bit in the array, and each of the plurality of check vectors is an element of a Galois Field (GF(2