Patent ID: 7805561
Filing Date: 2010-09-28
Classification: G06F

Abstract:
1. A control subsystem for addressing at least one memory, comprising: a central control unit having an address bus, the central control unit operable to apply an address signal including a plurality of address bits to the address bus, the address signal corresponding to a memory location for a word to be processed; and an address steering unit coupled to the address bus of the central control unit, the address steering unit being operable to receive the address signal and generate a control signal indicative of a granularity mode corresponding to a storage format for accessing a word having a particular number of bits, and further operable to generate a row address and a column address from the address signal in response to the control signal, a plurality of address bits selected by the address steering unit to generate the row address and a plurality of address bits selected by the address steering unit to generate the column address being a function of the number of bits in the word to be processed.