Patent ID: 8383426
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. A method for fabrication of an integrated circuit having Josephson junctions, comprising the steps of: depositing a Josephson junction trilayer comprising an upper superconductor, an insulator, and a lower superconductor, on a substrate; depositing directly on the upper superconductor of an unpatterned Josephson junction trilayer, an adhesion layer having a thickness of at least about 5 nm; depositing a resist directly on top of the adhesion layer, wherein the resist has a higher adhesion to the adhesion layer than to the Josephson junction trilayer; defining a latent pattern in the deposited resist; developing the patterned resist to produce a selective pattern of the adhesion layer exposed through the resist; etching the selective pattern of the exposed adhesion layer and underlying upper superconductor, without etching the patterned resist, reaching the insulator as an etch stop, forming a bilayer mask comprising the patterned resist over a correspondingly patterned adhesion layer, through which portions of the insulator of the Josephson junction trilayer are exposed; and anodizing exposed portions of the Josephson junction trilayer through the bilayer mask to selectively form Josephson junction circuit elements and to oxidize a portion of the lower superconductor corresponding to the exposed portions of the insulator, wherein the anodizing is associated with a volumetric increase in at least a portion of the Josephson junction trilayer substantially without peeling of the adhesion layer or resist.