Patent ID: 8656260
Filing Date: 2014-02-18
Classification: H03M

Abstract:
1. A circuit for processing a data block including a first plurality of bits arranged in a plurality of frames, comprising: a register configured to store a second plurality of bits, wherein the second plurality of bits is iteratively a partial parity for each of the plurality of frames of the data block; a parallel combiner coupled to the register and configured to generate a combination of bits from the second plurality of bits from the register and a third plurality of bits; wherein the third plurality of bits is iteratively those of the first plurality of bits within each of the plurality of frames of the data block; a plurality of respective exclusive-or circuits associated with the second plurality of bits, the plurality of respective exclusive-or circuits being coupled to the parallel combiner and the register; and wherein each respective exclusive-or circuit is configured to generate a bit of the second plurality from the combination of bits.