Patent ID: 6125059
Filing Date: 2000-09-26
Classification: G11C

Abstract:
In an integrated circuit having a plurality of programmable interconnect cells, each cell selectively interconnecting first and second circuit nodes, each cell having a first transistor having a floating gate, a control gate, and first and second source/drain regions connected respectively to said first and second circuit nodes, and a second transistor having a floating gate connected to said floating gate of said first transistor, a control gate connected to said control gate of said first transistor, and first and second source/drain regions, a method of erasing said programmable interconnect cells comprisingasserting a first voltage of a first polarity on said control gates of said first and second transistors;asserting a ground voltage on said first and second source/drain regions of said first transistor; andasserting a second voltage intermediate said first voltage and said ground voltage on said first and second source/drain regions of said second transistor.