Patent ID: 8420466
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A method of making a TFT floating gate memory cell structure, the method comprising: providing a substrate; forming a first insulation layer on the substrate; forming one or more source or drain regions on the first insulation layer, each of the one or more source or drain regions being associated with a first surface and including an n-type polysilicon layer, a barrier layer, and a conductive layer, the n-type polysilicon layer being on the barrier layer, the barrier layer overlying the conductive layer, the first surface consisting of n-type polysilicon, the conductive layer comprising a material containing a metal or a metal alloy; forming a second insulation layer on the first insulation layer, the second insulation layer being located between the one or more source and drain regions and associated with a second surface, the second surface being substantially co-planar with the first surface; forming a first p-type polysilicon layer overlying the first surface and the second surface, the first p-type polysilicon layer being capable of forming a channel from a source region to a drain region; forming a silicon layer sandwiched by an upper silicon dioxide block layer and a bottom silicon dioxide tunnel layer on the first p-type polysilicon layer, the silicon layer being capable of forming a floating gate; forming a second p-type polysilicon layer on the upper silicon dioxide block layer; and forming at least one control gate by patterning the second p-type polysilicon layer, wherein forming the silicon layer comprises: depositing silicon using low-pressure CVD technique with SiH annealing at 520-560° C. after deposition.