Patent ID: 6732204
Filing Date: 2004-05-04
Classification: G06F

Abstract:
A data transfer control device for data transfer over a serial bus, the data transfer control device comprising:a bit insertion circuit which inserts a bit of a second signal level on condition that there is a given number of bits of a first signal level consecutively; and a parallel-serial conversion circuit for converting parallel data into serial data which is transferred over the serial bus, wherein the bit insertion circuit is provided in a stage before the parallel-serial conversion circuit, and wherein the bit insertion circuit receives N-bit parallel input data that has been input at a given clock cycle from a previous-stage circuit and outputs N-bit parallel output data into which a bit has been inserted, and wherein the bit insertion circuit includes: a computation circuit which calculates an insertion position of a bit of the second signal level and number of bits that has overflowed due to the bit insertion; and an accumulated overflow total storage circuit which stores an accumulated overflow total obtained by cumulatively adding or subtracting the calculated number of overflow bits, and wherein the bit insertion circuit determines the parallel output data to be output, based on the accumulated overflow total, while inserting a bit of the second signal level, based on the bit insertion position.