Patent ID: 8284149
Filing Date: 2012-10-09
Classification: G09G

Abstract:
1. A gate driving circuit including a plurality of stages connected to each other, the plurality of stages having a first stage in which a start signal is coupled to an input terminal, the gate driving circuit sequentially outputting output signals of respective stages, an (m)-th stage (‘m’ is a natural number) of the plurality of stages comprising: an output part outputting a high voltage of a first clock signal as a high voltage of an (m)-th gate signal and a low voltage in response to a high voltage of an (m+1)-th gate signal outputted from an (m+1)-th stage; a first maintenance part maintaining a control part of a pull-up part at a low voltage in response to an (m−1)-th node signal or an (m+1)-th node signal lower than a high voltage of a second clock signal having a phase opposite to a phase of the first clock signal received from an (m−1)-th stage or the (m+1)-th stage; and a second maintenance part maintaining an output node of the output part at -the low voltage of the (m)-th gate signal in response to the (m−1)-th node signal or the (m+1)-th node signal, wherein the control parts of the first and second maintenance parts are gate electrodes and the two gate electrodes are directly connected.