Patent ID: 6295562
Filing Date: 2001-09-25
Classification: G06F

Abstract:
A hardware device, comprising:at least one function block circuit for performing a specific set of operations; andcontrol circuitry for controlling the function block to perform one or more operations, comprising:a first circuit for receiving a single operational command for the function block circuit to perform a single operation and for generating one or more first commands from the single operational command, each first command corresponding to a sub-operational step for execution by the function block circuit and not included in the single operational command, a series of the sub-operational steps corresponding to the generated first commands forming the single operation; anda bank of one or more registers coupled to the function block circuit, individual registers in the register bank being individually loadable with the first commands generated by the first circuit, an output of the register bank being coupled to the function block circuit so as to control the function block circuit to perform the single operation corresponding to the received operational command.