Patent ID: 7180891
Filing Date: 2007-02-20
Classification: H04L

Abstract:
1. A digital system that comprises: a plurality of units operating at a first clock rate, each unit configured to independently process a sequence of data items; and a domain crossover element configured to receive a stream of data items at a second clock rate different from the first clock rate and configured to distribute separate sequences of data items through separate ports to the plurality of units, wherein the domain crossover unit includes a plurality of registers including a first subset and a second subset distinct from the first, wherein the domain crossover unit is configured to select one of the plurality of registers at the second clock rate and to store each data item in a selected register as the data items are received, and wherein the domain crossover unit is further configured to sequentially select one of the first subset of the plurality of registers at the first clock rate and one of the second plurality of registers at the first clock rate and concurrently read data items from the selected ones of the first and second subsets at the first clock rate.