Patent ID: 6331960
Filing Date: 2001-12-18
Classification: G11C

Abstract:
A method for using a nonvolatile semiconductor memory device including nonvolatile memory cells which each have a source and a drain both formed on one surface of a semiconductor substrate, and including a floating gate and a control gate which are stacked on the semiconductor substrate above a portion between the source and the drain via insulation films, comprising:when a first level of multi-level data including at least a first level and a second level is to be written, repeating a series of behaviors until writing of said first level is completed, said series of behaviors including: applying a predetermined write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said first level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not;when a second level of said multi-level data is to be written, repeating a series of behaviors until writing of said second level is completed, said series of behaviors including: applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said second level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not.