Patent ID: 6846734
Filing Date: 2005-01-25
Classification: H01L

Abstract:
1. A method of forming a metal-gated CMOS device comprising the steps of: providing a structure which comprises a plurality of patterned gate regions located atop a Si-containing layer, each of said patterned gate regions including at least a patterned polysilicon region; forming a first metal on each of a first predetermined number of said patterned gate regions, said first metal is in contact with said patterned polysilicon region of each of said first predetermined number of said patterned gate regions; forming a second metal on said first metal as well as each of a second predetermined number of said patterned gate regions, wherein said second metal in each of said second predetermined number of said patterned gate region is in contact with said patterned polysilicon region of each of said second predetermined number of said patterned gate regions; and annealing so as to cause reaction between the first and second metals and underlying patterned polysilicon regions and subsequent formation of silicide regions, where each of said first predetermined number of patterned gate regions comprises an alloy silicide of the first and second metals and each of said second predetermined number of patterned gate regions comprises a silicide of said second metal.