Patent ID: 6134160
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A semiconductor memory device architecture, comprising:a plurality of first memory cell arrays, each having a plurality of standard memory cells coupled to standard bit lines and standard local word lines, and a plurality of redundant memory cells coupled to redundant bit lines and redundant local word lines;a plurality of second memory cell arrays, each having a plurality of standard memory cells coupled to standard bit lines and standard local word lines, and a plurality of redundant memory cells coupled to redundant bit lines and redundant local word lines;a first set of input/output (I/O) lines;a first standard select circuit coupled to standard bit lines of the first memory cell arrays and to standard bit lines of the second memory cell arrays, the first standard select circuit coupling selected of its standard bit lines to the first set of I/O lines;a first redundant select circuit coupled to the redundant bit lines of the first memory cell arrays and the second memory cell arrays, the first redundant select circuit coupling selected of its redundant bit lines to the first set of I/O lines;a plurality of standard global word lines coupled to the standard word lines of the first memory cell arrays and the second memory cell arrays;a plurality of redundant global word lines coupled to the redundant local word lines of the first memory cell arrays and the second memory cell arrays;a first data amplifier;a second data amplifier; anda first multiplexer that couples the first set of I/O lines to the first data amplifier and to the second data amplifier.