Patent ID: 9165638
Filing Date: 2015-10-20
Classification: G06F,G11C

Abstract:
1. A memory controller to control the operation of a dynamic random access memory (DRAM), the memory controller comprising: a circuit to transmit a clock signal to the DRAM; a circuit to transmit a strobe signal to the DRAM, the strobe signal to convey phase information to the DRAM for sampling data associated with the strobe signal; and calibration logic to, in a calibration mode of operation, align at the DRAM, arrival of the strobe signal with arrival of the clock signal and calibrate a clock cycle delay between commands received at the DRAM and data corresponding to the commands, wherein the calibration logic delays the strobe signal as a delayed strobe such that it arrives at the DRAM at an edge transition of the clock signal, the calibration logic to set the clock cycle delay for the strobe signal by iteratively writing a first data using the delayed strobe to a specific location in the DRAM, reading back second data from the specific location in which the first data was written, and selectively adjusting the clock cycle delay by an integer number of cycles based on whether the second data matches the first data.