Patent ID: 7649800
Filing Date: 2010-01-19
Classification: G11C

Abstract:
1. A logic circuit, comprising: exactly two transistors, said two transistors being a first transistor and a second transistor, first and second input terminals for receiving different logic input signals supplied thereto respectively from first and second input signal sources, each logic signal changing between a low state and a high state, said first input terminal being connected exclusively to the first input signal source and to said first transistor; said first and second transistors connected in series between said first input terminal and a first power supply, said first and second transistors having control terminals connected in common to said second input terminal; and an output terminal connected to a connection node between said first transistor and said second transistor, said logic circuit structured to have a first operational configuration wherein said output terminal is made to be at a first logic level, the first logic level being less than or equal to the first power supply voltage, when said first and second transistors being both in an off state, responsive to the combination of the signals supplied to said first and second input terminals so that when the signals supplied to both said first and second input terminals are low, a potential at said output terminal becomes the first logic level, and said logic circuit structured to as a CMOS inverter so that when the first input terminal is in a high state, the logic circuit inverting a logic level at the second input terminal and outputting the inverted signal from the output terminal.