Patent ID: 7435657
Filing Date: 2008-10-14
Classification: H01L

Abstract:
1. A method of fabricating a transistor, comprising: sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate; forming a gate pattern including a gate electrode on the top semiconductor layer; forming a sacrificial spacer to cover sidewalls of the gate pattern; growing an elevated semiconductor layer on a portion of the top semiconductor layer adjacent to the sacrificial spacer; removing the sacrificial spacer; forming a recess by etching a portion of the top semiconductor layer from which the sacrificial spacer is removed until the sacrificial layer is exposed, the recess separating the top semiconductor layer into a first top semiconductor layer pattern remaining under the gate pattern and a second top semiconductor layer pattern remaining under the elevated semiconductor layer; selectively removing the sacrificial layer; forming a buried insulating layer to fill a region from which the sacrificial layer is removed; and growing a buried semiconductor layer in the recess, the buried semiconductor layer being in contact with the first top semiconductor layer pattern and the second top semiconductor layer pattern.