Patent ID: 6320525
Filing Date: 2001-11-20
Classification: H03M

Abstract:
An analog-to-digital level error automatic calibration circuit comprising:a calibration switch circuit for receiving a reference voltage and an external sense voltage and transmitting a reference output voltage and a calibration voltage by dividing the reference voltage;an input buffer circuit for receiving one of the reference output voltage, the calibration voltage and the external sense voltage output from the calibration switch circuit;an error differential amplifying circuit for receiving and amplifying the output voltage of the input buffer circuit, and transmitting a first error amplifying voltage when the output voltage is the external sense voltage or a second error amplifying voltage when the output voltage is the calibration voltage;an N-bit analog-to-digital converter electrically coupled to the output terminal of the error differential amplifying circuit for converting the first error amplifying voltage and the second error amplifying voltage into a first digital value and a second digital value;a calibration register electrically coupled to the N-bit analog-to-digital converter for storing the second digital value; anda subtractor for receiving the first digital value and the second digital value, and transmitting a result value obtained by subtracting the second digital value from the first digital value.