Patent ID: 7242255
Filing Date: 2007-07-10
Classification: H03L

Abstract:
1. An apparatus that minimizes phase error and jitter in a phase-locked loop, comprising: a phase/frequency detector; a charge pump; a loop filter; a voltage-controlled oscillator; and a frequency divider; wherein the phase/frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator, and frequency divider are coupled together to form a phase-locked loop; wherein the charge pump contains a pull-up network and a pull-down network which are coupled to each other, a current compensation device, a replica of the pull-up network and a replica of the pull-down network which are coupled to each other, and a replica of the current compensation device; wherein the replica of the pull-up network and the replica of the pull-down network both conduct current continuously; and wherein if the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through one of the pull-up network and through the pull-down network such that the current flowing through the pull-up network and through the pull-down network are substantially equal, so that substantially no current flows into a capacitor of the loop filter, thereby substantially minimizing a build-up of charge on the capacitor which can cause phase error and jitter in the phase-locked loop.