Patent ID: 8222738
Filing Date: 2012-07-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a wiring substrate including an upper surface, a plurality of bonding leads formed on the upper surface, an insulating film formed over the upper surface such that the bonding leads are exposed from an opening formed in the insulating film; (b) mounting a semiconductor chip, including a front surface, a plurality of pads formed on the front surface, and a rear surface opposite to the front surface, over the upper surface of the wiring substrate via a plurality of protruding electrodes such that the front surface faces the upper surface; and (c) sealing between the front surface of the semiconductor chip and the upper surface of the wiring substrate with sealing material; wherein a shape in a plan view of the upper surface of the wiring substrate is comprised of a quadrangle having a first substrate side, a second substrate side faces the first substrate side, a third substrate side located between the first and second substrate sides, and a fourth substrate side faces the third substrate side; wherein the bonding leads are arranged along each of the first, second, third and fourth substrate sides in the plan view; wherein a shape in the plan view of the opening is comprised of a ring having an inner periphery and an outer periphery located closer to a peripheral portion than the inner periphery in the plan view; wherein a shape in the plan view of the front surface of the semiconductor chip is comprised of a quadrangle having a first chip side, a second chip side faces the first chip side, a third chip side located between the first and second chip sides, a fourth chip side faces the third chip side, a first chip corner intersecting the first chip side with the third chip side, a second chip corner opposite to the first chip corner, a third chip corner intersecting the second chip side with the third chip side, and a fourth chip corner opposite to the third corner; wherein in the step (b), the semiconductor chip is mounted over the wiring substrate such that the first, second, third and fourth chip sides are arranged next to the second, first, third and fourth substrate sides, respectively, and such that the first, second, third and fourth chip sides are arranged between the inner and outer peripheries in the plan view, and such that a distance between the first chip corner and a first opening corner of the opening adjacent to the first chip corner along in a first direction extended from the first chip corner to the second chip corner is larger than that between the second chip corner and a second opening corner of the opening adjacent to the second chip corner along in the first direction, and such that a distance between the third and fourth chip corners and third and fourth opening corners of the opening adjacent to the third and fourth chip corners along in a second direction extended from the third chip corner to the fourth chip corner, respectively, are smaller than that between the first chip corner and the first opening corner, and larger than that between the second chip corner and the second opening corner; wherein the outer periphery of the opening has a first opening side extended from the first opening corner and extended along the third substrate side in the plan view, a second opening side extended from the second opening corner and extended along the fourth substrate side in the plan view, a third opening side extended from the first opening corner and extended along the second substrate side in the plan view, and a fourth opening side extended from the second opening corner and extended along the first substrate side in the plan view; wherein a length of the first opening side is smaller than a half the length of the third chip side, a length of the second opening side is smaller than a half the length of the fourth chip side, a length of the third opening side is smaller than a half the length of the first chip side, and a length of the fourth opening side is smaller than a half the length of the second chip side; and wherein in the step (c), the sealing material is supplied to between the semiconductor chip and the wiring substrate from an area surrounded by the first chip corner, the first opening corner, the first opening side and the third opening side in the plan view.