Patent ID: 7700993
Filing Date: 2010-04-20
Classification: G11C,H01L

Abstract:
1. A CMOS device comprising: a substrate; a semiconductor nFET formed in and/or upon said substrate including a first source region, a first channel region, and a first drain region; a thin gate dielectric layer formed above said first channel region and a first gate electrode formed above said thin gate dielectric layer; a semiconductor pFET device formed in and/or upon said substrate juxtaposed with said nFET device and including a second source region, a second channel region, and a second drain region; a thick gate dielectric layer formed above said second channel region and a floating gate electrode formed above said thick gate dielectric layer, with said thick gate dielectric layer being substantially thicker than said thin gate dielectric layer in order to be resistant to unwanted tunneling of charge therethrough; a common drain node connected both to said first drain region and to said second drain region with no external connection to said common drain node in the case of a memory device and with an external connection to said common drain node in the case of an inverter; and external circuit connections to said first source region and to said second source region and to said first gate electrode.