Patent ID: 6529523
Filing Date: 2003-03-04
Classification: H04L,H04Q

Abstract:
A converting circuit for converting a time division multiplexed frame of an STM network, said frame is the result of time division multiplexing n channels in one frame and one byte of data in each channel, to cells of an ATM network, each cell having a header and an m-byte payload, comprising:a time switch memory having, for each destination STM switch, a storage area possessing m consecutive addresses; a control memory for storing a corresponding relationship between time slot numbers in a time division multiplexed frame and addresses of the time switch memory; writing means for writing data of each time slot in the time division multiplexed frame to a storage area of said time switch memory that is specified by the corresponding relationship stored in said control memory; a buffer memory for storing data read out of said time switch memory; reading means for reading data out of said time switch memory successively, storing the data in said buffer memory and reading the data out of said buffer memory successively in m-byte units; and cell generating means for generating a cell in which m bytes of consecutive data read out of said buffer memory is adopted as a payload and a header having an identifier conforming to a destination STM switch is added onto the payload.