Patent ID: 8263924
Filing Date: 2012-09-11
Classification: H01L,H04N

Abstract:
1. An integrated circuit chip comprising: a plurality of power consuming elements, each said power consuming element operating to obtain independent data, said power consuming elements, located in an array at different areas covering a surface of the chip; and a power grid, having a first power connecting portion, which is adapted to be attached to a source of power, and having a first plurality of parallel elements, and a second plurality of parallel elements, which extend substantially orthogonal to said first plurality of elements and are connected to said first plurality of parallel elements, and said power grid extends across an area defined by said plurality of power consuming elements, said chip having multiple different levels, each level having connection parts thereon, and where there is a portion of disconnection on said power grid, where the grid is disconnected in a way that is asymmetric to other portions of the grid.