Patent ID: 7383481
Filing Date: 2008-06-03
Classification: G01R

Abstract:
1. An integrated circuit comprising: functional circuitry; test circuitry connected to said functional circuitry, wherein said test circuitry is arranged to control the testing of said functional circuitry; and functional clock signal generating circuitry configured to produce a functional clock signal for use in the operation of the integrated circuit connected to both said functional circuitry and said test circuitry; wherein said test circuitry is arranged to use said functional clock signal for testing said functional circuitry; wherein said test circuitry comprises a switch, wherein said switch is arranged to receive said functional clock signal from said functional clock signal generating circuitry and is arranged to output said functional clock signal to the functional circuitry dependent on a clock selection signal; said test circuitry further comprises a gated clock buffer, wherein said gated clock buffer is arranged to receive said functional clock signal from said switch and output said functional clock signal in dependence on an enable signal; and wherein said gated clock buffer comprises a further switch and a delay element, said delay unit element being arranged to delay said enable signal and said further switch is arranged to output a switch clock signal in dependence on said delayed enable signal.