Patent ID: 9159439
Filing Date: 2015-10-13
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array that includes multiple memory cells that are stacked above a semiconductor substrate; and a sense amplifier that can retain data read from or to be written to a memory cell, the sense amplifier including a bus that can transmit the data, a first latch circuit that includes a first data retention unit and a first transistor connecting the first data retention unit and the bus, a second latch circuit that includes a second data retention unit and a second transistor connecting the second data retention unit and the bus, and a third transistor, wherein when the data is transmitted from the first latch circuit to the second latch circuit, the third transistor is switched on to charge the bus to an electric potential lower than a power source voltage of the first and second latch circuits, by applying a first voltage lower than the power source voltage to a gate of the third transistor, and after precharging the bus, second and third voltages that are lower than the power source voltage, are applied to gates of the first and second transistors, respectively.