Patent ID: 6282142
Filing Date: 2001-08-28
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first memory cell block including a plurality of bit line pairs, a plurality of word lines which cross the plurality of bit line pairs, a plurality of memory cells, wherein each memory cell is connected to one of the bit line pairs and one of the word lines;a plurality of first signal line pairs, wherein each first signal line pair is connected to a first end of respective ones of the plurality of bit line pairs so as to receive data from the bit line pairs;a plurality of second signal line pairs, wherein each second signal line pair is connected to a second end of respective ones of the plurality of bit line pairs so as to receive data from the bit lines pairs;a plurality of first transfer control circuits, each connecting respective ones of the plurality of first signal line pairs with respective ones of the plurality of bit line pairs in response to a first control signal so as to transfer data;a plurality of second transfer control circuits, each connecting respective ones of the plurality of second signal line pairs with respective ones of the plurality of bit line pairs in response to the first control signal so as to transfer data;a plurality of first sense amplifiers, each connected to respective ones of the first signal line pairs and operating to amplify a voltage difference between the first signal line pair in response to a first activating signal; anda plurality of second sense amplifiers, each connected to respective ones of the second signal line pairs and operating to amplify a voltage difference between the second signal line pair in response to the first activating signal.