Patent ID: 9166045
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A method for controlling a gate dimension in a MOS structure comprising: forming source and drain regions in a semiconductor substrate; forming an insulating layer on an upper surface of the semiconductor substrate; removing portions of the insulating layer to form a hole that exposes the upper surface of the semiconductor substrate between the source and drain regions previously formed in the semiconductor substrate, wherein the portions of the insulating layer are removed without removing portions of the upper surface of the semiconductor substrate; forming a spacer layer on an upper surface of the insulating layer, on sidewalls of the hole in the insulating layer and on the exposed upper surface of the semiconductor substrate in the hole; forming spacers on the sidewalls of the hole by etching at a first rate the spacer layer on the upper surface of the semiconductor substrate in the hole to expose the upper surface of the semiconductor substrate and etching at a second rate the spacer layer on the sidewalls of the hole in the insulating layer to reduce the thickness of the spacer layer on the sidewalls; forming a dielectric layer between the spacers on the exposed upper surface of the semiconductor substrate in the hole; and forming a gate on the dielectric layer formed between the spacers on the exposed upper surface of the semiconductor substrate in the hole.