Patent ID: 6825702
Filing Date: 2004-11-30
Classification: H03L

Abstract:
A digital circuit for detecting and asserting a phase lock condition of a phase locked loop (PLL) circuit, the digital circuit comprising:a pair of counters respectively receiving a digital signal produced by the PLL circuit, and a digital reference signal that is also received by the PLL circuit; a digital comparator connected to said pair of counters for comparing count values contained therein at an end of a counting cycle, and for generating a first logic signal when the count values are the same and a second logic signal when the count values are different; a resettable memory receiving the logic signals generated by said digital comparator and having a capacity sufficient to store a plurality of the logic signals resulting from successive comparisons, said resettable memory comprising logic circuit means comprising a bistable output circuit that outputs a third logic signal for asserting a phase lock condition of the PLL circuit when an uninterrupted sequence of the first logic signals have been input to said resettable memory during the successive comparisons, and outputs a fourth logic signal for asserting a loss of a phase lock condition of the PLL circuit when an uninterrupted sequence of the second logic signals have been input to said resettable memory during the successive comparisons.