Patent ID: 8817519
Filing Date: 2014-08-26
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a high voltage generator configured to generate a high voltage by pumping a power source voltage; a negative voltage generator configured to generate a negative voltage by pumping a ground voltage; a divided voltage generator configured to generate a divided voltage by dividing the power source voltage and supply the divided voltage to a read voltage terminal; a first power gate configured to supply either the high voltage or the divided voltage to a program voltage terminal in response to an idle signal; a second power gate configured to supply either the negative voltage or the ground voltage to a deactivation voltage terminal in response to the idle signal; a third power gate configured to supply either the ground voltage or the divided voltage to an activation voltage terminal in response to the idle signal; and an e-fuse array circuit configured to operate using voltage supplied to the program voltage terminal as a program voltage, using voltage supplied to the divided voltage terminal as a read voltage, using voltage supplied to the activation voltage terminal as an activation voltage, and using voltage supplied to the deactivation voltage terminal as a deactivation voltage.