Patent ID: 7685408
Filing Date: 2010-03-23
Classification: G06F

Abstract:
1. An apparatus for extracting a pattern of data bits and packing the extracted pattern of data bits in a right justified format, the apparatus comprising: a data register; a target register; an adder tree for computing a plurality of count values of a number of asserted mask bits in non-overlapping groups of mask bits within stages of the adder tree; a mask path for combining pairs of adjacent groups of mask bits within stages of the mask path corresponding to the stages of the adder tree by utilizing the plurality of count values within corresponding stages of the mask path to realign within the pairs of adjacent groups of mask bits a left group of mask bits with an adjacent right group of mask bits and to merge the realigned left group of mask bits with the adjacent right group of mask bits to provide a plurality of mask values; and a data path for combining pairs of adjacent groups of data bits within stages of the data path corresponding to the stages of the adder tree and corresponding to stages of the mask path by utilizing the plurality of count values within corresponding stages of the data path to realign within the pairs of adjacent groups of data bits a left group of data bits with an adjacent right group of data bits and to merge the realigned left group of data bits with the adjacent right group of data bits by utilizing the plurality of mask values within corresponding stages of the data path, wherein the pattern of data bits is extracted from the data register and the extracted pattern of data bits is packed in a right justified format in the target register.