Patent ID: 6081458
Filing Date: 2000-06-27
Classification: G11C

Abstract:
A memory system comprising:a plurality of memory cell groups;a plurality of memory cells, at least one of said plurality of memory cells being included in each memory cell group of said plurality of memory cell groups;a plurality of first bitlines, each first bitline of said plurality being coupled to a corresponding one of said plurality of memory cell groups, wherein each said first bitline communicates write data for writing to at least one memory cell in said corresponding one of said plurality of memory cell groups;at least one second bitline coupled to each said first bitline of said plurality of first bitlines, said at least one second bitline communicating read data for reading from one of said plurality of memory cells, and wherein said at least one second bitline is decoupled from each said first bitline during a write to one of said at least one memory cell;a plurality of first precharge units coupled to said plurality of first bitlines for precharging said plurality of first bitlines in response to a first precharge signal; andat least one second precharge unit coupled to said at least one second bitline for precharging said at least one second bitline in response to a second precharge signal.