Patent ID: 6124610
Filing Date: 2000-09-26
Classification: H01L

Abstract:
An integrated circuit comprising:first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate, wherein the first and second gate conductors are interposed between respective first and second opposed sidewall surfaces;first and second pairs of sidewall spacers extending laterally from the respective first and second opposed sidewall surfaces to respective first and second outer edges;third and fourth pairs of sidewall spacers extending laterally from the first and second outer edges, respectively, to respective third and fourth outer edges;a first pair of lightly doped drain areas residing within the first active area, wherein each of the first pair of lightly doped drain areas is formed aligned with one of said first opposed sidewall surfaces of said first gate conductor;first source and drain regions arranged within the first active area laterally adjacent the first lightly doped drain areas, wherein the first source and drain regions are formed aligned at a point between the third outer edges and the first outer edges; anda second pair of lightly doped drain areas residing within the second active area, wherein each of the second pair of lightly doped drain areas is formed aligned with the second outer edge of one of the second pair of sidewall spacers.