Patent ID: 7489742
Filing Date: 2009-02-10
Classification: H04N

Abstract:
1. A system for clock recovery in digital video communication comprising: a delay measurement block for generating Program Clock Reference (PCR) input signals and for continuously determining time interval between successive PCR input signals; a first storage device coupled to the output of said delay measurement block for generating a first PCR signal corresponding to said time interval between arrival of successive PCR input signals; a PCR inter-arrival time computation filtering device coupled at its first input to the output of said storage device and receiving a second PCR signal from said delay measurement block for determining the average time of arrival difference between successive PCR packets; an error correction device coupled to the output of said PCR difference measurement element for minimizing the error in the average PCR difference between successive PCR packets; a controlled system clock generator coupled to the output of said error correction device to generate system clock; a second storage device coupled at the output of said controlled system clock generator for generating a first system clock output; and a controlled clock period difference computation element having one input coupled to the output of said second storage device and receiving a second system clock output from said controlled system clock generator, for computing the clock period difference between said first and second system clock output, wherein said controlled clock period difference computation element is coupled at its output to said error correction device to form a feedback circuit for minimizing the error between said system clock output and successive PCR differences observed.