Patent ID: 6831700
Filing Date: 2004-12-14
Classification: G06T,H04N

Abstract:
A video signal processor comprising:a plurality of line memories, each of which can store one horizontal scanning line of video data series; a controller for causing said plurality of line memories to sequentially store every horizontal scanning line of a video data series in one of said plurality of line memories, and to output the stored data from said plurality of line memories; and an arithmetical unit for receiving two video data series output from two of said plurality of line memories and generating one new horizontal scanning line of video data series based on the received video data series, wherein said controller comprises: means for receiving an arbitrarily selected vertical scaling factor of resolution from a source outside of said controller, means for generating a horizontal scanning synchronizing signal having a period depending on the selected scaling factor, and means for selecting two line memories from said plurality of line memories every time when said one new horizontal scanning line of video data series is generated to cause the selected two line memories to output two video data series stored therein, and wherein said arithmetical unit is triggered by said horizontal scanning synchronizing signal to generate said new horizontal scanning line of video data series.