Patent ID: 7112492
Filing Date: 2006-09-26
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a first field isolation layer, a second field isolation layer and a third field isolation layer on a semiconductor substrate, the first and second field isolation layers defining a first active region therebetween and the second and third field isolation layers defining a second active region therebetween; sequentially forming a gate dielectric layer, a storage node layer, a multiple tunnel junction barrier layer and a source layer on the semiconductor substrate; forming a mask layer directly on the source layer; patterning the mask layer to form a mask pattern; patterning the source layer, the multiple tunnel junction barrier layer, the storage node layer and the gate dielectric layer using the mask pattern as an etch mask to form a first cell gate and a second cell gate, the first and second cell gates each having a gate dielectric region, a storage node, a multiple tunnel junction barrier and a source region that are sequentially stacked on the semiconductor substrate; forming a dielectric layer on the exposed portions of the first and second active regions and on the sidewalls of the first and second cell gates; forming a first control line on at least a portion of each of the sidewalls of the first cell gate; forming a second control line on at least a portion of each of the sidewalls of the second cell gate-, wherein the second control line is parallel to the first control line; and forming a data line perpendicular to the first and second control lines and connecting to the source regions of the first and second cell gates.