Patent ID: 7012021
Filing Date: 2006-03-14
Classification: H01L

Abstract:
1. A method to polish down conductive lines in the manufacture of an integrated circuit device, said method comprising: providing a plurality of conductive lines overlying a substrate; depositing a high density plasma (HDP) oxide layer overlying said substrate and said conductive lines wherein, in the regions between said conductive lines, first planar top surfaces of said HDP oxide layer are formed below the top of said conductive lines; depositing a polish stopping layer overlying said HDP oxide layer; depositing a film layer overlying said polish stopping layer; polishing down said film layer to said polish stopping layer overlying said conductive lines; and polishing down said film layer, said polish stopping layer, said HDP oxide layer and said conductive lines to portions of said polish stopping layer overlying said first planar top surfaces to complete said polishing down of said conductive lines.