Patent ID: 6405331
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A method for performing a BIST procedure on an embedded memory device having a specific word length, comprising the steps of:(1) generating a block of test data; (2) performing a write operation to write the test data into a specified address in the embedded memory; (3) performing a read operation to retrieve the test data from the embedded memory; (4) comparing the retrieved test data with the originally-generated test data in the step (1); and (5) if any bit is mismatched, outputting a sequence of blocks of error bits indicative of the bad memory cells in the embedded memory, if any; the length of each error-bit block being an integer division of the word length of the embedded memory, and the sequence of error-bit blocks being transferred in a time-division multipexed scheme via a plurality of probing pads equal in number to the length of the error-bit block.