Patent ID: 7529857
Filing Date: 2009-05-05
Classification: G06F

Abstract:
1. A data processing apparatus including a processor, a reception-side device which controls K (K≧2) memories which can be operated in parallel, and a transmission-side device which transfers data to the reception-side device in response to a data transfer request from the processor, comprising: a packet forming unit which is provided in the transmission-side device and forms N (N≧2K) packets corresponding to N (N≧2K) data blocks, the N data blocks configuring data to be transferred in a data transfer process specified by the data transfer request, and an end flag and an identifier which identifies the data transfer process being attached to each of the last K (K≧2) packets among the N packets, and the number of the last K packets being equal to the number of the K memories controlled by the reception-side device; K (K≧2) memory control units which are provided in the reception-side device and respectively control the K (K≧2) memories; a packet processing unit which is provided in the reception-side device and distributes the N packets from the transmission-side device to the K memory control units to sequentially allocate the N packets to the K memories in the order of transmission; units which are respectively provided in the memory control units and each perform a process of writing each packet received from the packet processing unit into a memory corresponding to the memory control unit and perform a process of issuing notification of completion relating to the data transfer process corresponding to the identifier attached to the packet having the end flag attached thereto when the packet having the end flag attached thereto is written into the corresponding memory; and a notifying unit which is provided in the reception-side device and notifies completion of the data transfer process to the processor when notification of completion relating to the data transfer process is issued from all of the K memory control units.