Patent ID: 6441691
Filing Date: 2002-08-27
Classification: H03L

Abstract:
A phase detector for use in a PLL comprising:first and second input circuits to generate first and second PLL control signals responsive to clock edges in first and second input signals, respectively; a reset circuit to generate a reset pulse based on said first and second PLL control signals to reset said first and second input circuits, thereby clearing said first and second PLL control signals; a first frequency divider providing said first input signal to said first input circuit, said first frequency divider responsive to a first cycle slip indicator signal to advance a next clock edge in said first input signal; and a second frequency divider providing said second input signal to said second input circuit, said second frequency divider responsive to a second cycle slip indicator signal to advance a next clock edge in said second input signal; wherein said first cycle slip indicator signal indicates that said phase detector missed a clock edge in said first input signal, and said second cycle slip indicator indicates that said phase detector missed a clock edge in said second input signal.