Patent ID: 6157063
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A MOS field effect transistor comprising:a silicon substrate;source/drain diffusion layers having upper regions which comprise metal silicide layers and said source/drain diffusion layers being selectively provided in upper regions of said silicon substrate;lightly-doped diffusion layers having a lower planar surface coplanar with a lower planar surface of said metal silicide layers extending from inside edges of said source/drain diffusion layers toward a channel region of said silicon substrate;a gate insulation film being provided on said channel region of said silicon substrate;a gate electrode being provided on said gate insulation film;side wall insulation films being provided on side walls of said gate electrode so that outside edges of said side wall insulation films are positioned over boundaries between said source/drain diffusion layers and said lightly-doped diffusion layers,wherein side wall spacer layers are further provided on interfaces between said side walls of said gate electrode and said side wall insulation films, and inside edges of said lightly-doped diffusion layers are positioned under said side wall spacer layers so that each of said inside edges of said lightly-doped diffusion layers is positioned inside of said side wall insulation films and outside of said gate electrode.