Patent ID: 6044432
Filing Date: 2000-03-28
Classification: G06F,G11C

Abstract:
In a computer system, a method for latching an address for accessing data in a synchronous static random access memory (SRAM), comprising the steps of:(a) driving a first address status signal active to trigger the SRAM to latch an address on a bus coupled to the SRAM;(b) placing an address on the bus;(c) receiving a second address status signal indicating that a first address that is placed on the bus is valid;(d) determining whether the SRAM needs to be accessed based on the address placed on the bus;if the SRAM needs to be accessed,(e) driving the first address status signal inactive; and(f) maintaining the first address status signal inactive until the SRAM is ready to accept a second address; andif the SRAM does not need to be accessed,(g) driving the first address status signal active.