Patent ID: 6348827
Filing Date: 2002-02-19
Classification: G11C,H03K

Abstract:
A programmable delay device comprising:a plurality of current source field-effect transistors (FETs) for gating a predetermined amount of current; a switch device, coupled to said plurality of current source FETs, for receiving an input signal having a first and second voltage level; a plurality of signal enable switch FETs for receiving said input signal; a plurality of programmed select switch FETS, each of said plurality of signal enable switch FETs coupled to both a corresponding programmed select switch FET and a corresponding current source FET, for receiving programmable inputs, wherein said programmed select switch FETs activate selected current source FETs for determining said predetermined amount of current; and an inverter device, coupled to the drain of said current source FET, for outputting a delayed signal when said input signal is at said first voltage level, a delay of said delayed signal defined by said predetermined amount of current.