Patent ID: 7895430
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. An integrated circuit on a semiconductor substrate, the integrated circuit comprising: on-chip logic analyzer circuitry associated with an on-chip analyzer clock signal and including a triggering circuit configured to receive a source data signal and further including a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression to form a compressed data signal from the uncompressed data signal; and destination buffering circuitry to receive the compressed data signal and to convert a timing of the compressed data signal from a timing of the on-chip analyzer clock signal to a timing of a particular destination clock signal of a particular capture device, wherein the destination buffering circuitry is configured to select one of plural different destination clock signals as the particular clock signal, depending upon which of plural capture devices is selected as the particular capture device to store the compressed data signal.