Patent ID: 6753740
Filing Date: 2004-06-22
Classification: H03L

Abstract:
An integrated circuit, comprising:a clock path for carrying a clock signal; a power supply path for receiving power from a power supply; a phase locked loop connected to the power supply path, comprising: a voltage-controlled oscillator for generating a frequency signal dependent on an input thereto; a phase-frequency detector for detecting a phase difference between the clock signal and the frequency signal; and a bias-generator arranged to output a voltage to an input of the voltage-controlled oscillator responsive to the phase-frequency detector; an adjustment circuit operatively connected to the input of the voltage-controlled oscillator, wherein the adjustment circuit is responsive to control information to adjust the voltage output by the bias-generator; a storage device for storing the control information to which the adjustment circuit is responsive; and a test processor unit operatively coupled to the storage device and the adjustment circuit.