Patent ID: 6281711
Filing Date: 2001-08-28
Classification: G06F,G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit comprising:a first potential point to which a first voltage is supplied;a second potential point to which a second voltage lower than said first voltage is supplied;a first MOS transistor of a first type whose source is coupled to a first node and whose gate is coupled to an input node;a second MOS transistor of a second type whose source is coupled to a second node electrically connected to said second potential point, whose drain is coupled to a drain of said first MOS transistor and whose gate is coupled to said input node;an input control circuit coupled to said input node; anda control circuit connected to receive a control signal, said control circuit being provided between said first node and said first potential point;wherein said control circuit permits a first current to flow between said first potential point and said second node through source/drain paths of said first and second MOS transistors due to a change of level of an input signal inputted to said input node when said control signal is in a first state;wherein said control circuit limits the current flowing between said first potential point and said second node to a second current smaller than said first current in response to said control signal being set to a second state different from said first state, andirrespective of said level of said input signal, said input control circuit controls a level of said input node to a predetermined potential such that said first MOS transistor is in an off state.