Patent ID: 6490657
Filing Date: 2002-12-03
Classification: G06F

Abstract:
A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising:update address storage means having a plurality of regions each of which has one or more entries for storing the address of data held in a dirty block; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address which is equal to the memory address MW and is stored in an entry of the selected region; and flush executing means, in response to a request from said at least one processor, for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory the data of the dirty block indicated by the update address read.