Patent ID: 6238984
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method for integrating high voltage and low voltage device, wherein method comprises:providing a substrate having a low voltage MOS device and a high voltage MOS device;forming a source/drain region on said low voltage MOS device and said high voltage MOS device;annealing said low voltage MOS device and said high voltage MOS device;forming a cap oxide layer on said low voltage MOS device and said high voltage MOS device;forming a photoresist layer to cover said cap oxide layer of said high voltage MOS device;removing said cap oxide layer on said low voltage MOS device by using said photoresist layer as a mask;removing said photoresist layer;forming a metal layer on said cap oxide layer of said high voltage MOS device and on surface of said low voltage MOS device;thermally treating said metal layer by rapidly thermal process, consequently forming a metal silicide layer on surface of said low voltage device; andforming an inter-layer dielectric layer on said cap oxide layer of said high voltage MOS device and on surface of said low voltage MOS device.