Patent ID: 6759911
Filing Date: 2004-07-06
Classification: H03K,H03L

Abstract:
A delay-locked loop, comprising:a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a coarse delay circuit coupled to the ring oscillator and operable to generate a coarse delay count responsive to the oscillator clock signal, the coarse delay circuit further operable to generate a coarse reference count in response to a coarse delay control signal and to activate a coarse delay enable signal responsive to the coarse delay count being equal to the coarse delay reference count, and the coarse delay circuit resetting the coarse delay count responsive to a reset signal; a fine delay circuit coupled to the ring oscillator to receive the tap clock signals and operable responsive to a fine delay control signal to select one of the tap clock signals and output the selected signal as a fine delay enable signal; an output circuit coupled to the coarse and fine delay circuits, the output circuit generating a delayed clock signal responsive to the coarse and fine delay enable signals going active, and the delayed clock signal being applied as the reset signal to the coarse delay circuit to reset the coarse delay count; and a comparison circuit adapted to receive an input clock signal and coupled to the output circuit to receive the delayed clock signal, and the comparison circuit being further coupled to the coarse and fine delay circuits, the comparison circuit operable to generate the coarse and fine delay control signals in response to the relative phases of the delayed and input clock signals.