Patent ID: 6721864
Filing Date: 2004-04-13
Classification: G06F

Abstract:
An apparatus for controlling an array of synchronous memory devices, comprising:a memory controller having: a high speed interface configured to be coupled to an execution unit of a computer system, the high speed interface having a buffer with entries for receiving transactions, wherein said buffer has a valid bit for each entry, said entries store transactions received from a high speed bus; and a low speed interface configured to be coupled to an array of synchronous memory devices, wherein the low speed interface retrieves transactions from said buffer, said high speed interface and said low speed interface each have state machines that use said valid bit for each of said entries to synchronize said high speed interface with respect to said low speed interface; wherein the memory controller is configured to pipeline consecutive accesses between the memory controller and a synchronous dynamic random access memory (SDRAM) to efficiently use a data bus of the SDRAM by overlapping consecutive accesses, the accesses including read and write accesses, the read and write accesses each having an activate phase followed by a command phase.