Patent ID: 8319538
Filing Date: 2012-11-27
Classification: H03K

Abstract:
1. A semiconductor device, comprising: a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal, wherein the delay control code includes a multi-bit common delay control code, a multi-bit first delay control code, and a multi-bit second delay control code, wherein the common delay circuit includes a plurality of common delay units that each operate in response to a corresponding bit of the common delay control code, the first delay circuit includes a plurality of first delay units that each operate in response to a corresponding bit of the first delay control code, and the second delay circuit includes a plurality of second delay units that each operate in response to a corresponding bit of the second delay control code, wherein the plurality of first delay units are each configured to select between delaying a respective one of a plurality of first delay input signals and delaying an output signal of a corresponding one of the plurality of common delay units, and wherein, when a bit among one of the first delay control code, the second delay control code, and the common delay control code is selectively enabled as the highest enabled bit of the code, lower bits of the code are all enabled while higher bits of the code are all disabled.