Patent ID: 8389357
Filing Date: 2013-03-05
Classification: G11C,H01L

Abstract:
1. A method of fabricating a memory device in a semiconductor substrate, the device having a memory array comprising a plurality of memory cell transistors arranged in rows and columns, the method comprising: forming a memory array comprising a plurality of tunneling field effect transistors arranged in rows and columns, each field effect transistor from said plurality of tunneling field effect transistors comprising a first doped region, a second doped region and a floating gate, one of the first and second doped regions being a drain region and the other of the first and second doped regions being a source region, the first doped region having a first doping type and the second doping region having a second doping type different from the first doping type; wherein, within each column of tunneling field effect transistors, each alternating pair of field effect transistors from the plurality of tunneling field effect transistors shares a single source region; forming a first well of the second doping type; forming a second well of the first doping type surrounding the first well, wherein the first well contains the plurality of tunneling field effect transistors arranged in a first column, and the shared single source region and the drain region associated with each of the plurality of tunneling field effect transistors arranged in the first column; forming a first word line connected to a first row of tunneling field effect transistors, wherein the first row of tunneling field effect transistors is formed from a first tunneling field effect transistor in each of the plurality of columns of tunneling field effect transistors; forming a first bit line to control a voltage of doped drain regions of each tunneling field effect transistor from the plurality of tunneling field effect transistors of the first column of tunneling field effect transistors; forming a second bit line parallel to the first bit line, the second bit line to control a voltage of doped source regions of tunneling field effect transistors of the first column of tunneling field effect, wherein the second bit line is not utilized to control a second column of tunneling field effect transistors, and wherein the first tunneling field effect transistor has a first floating gate connected to a control gate of the first word line, a first doped drain region connected to the first bit line, and a first doped source region connected to the second bit line; wherein the first column of tunneling field effect transistors comprises the first tunneling field effect transistor, said first tunneling field effect transistor directly adjacent a second tunneling field effect transistor, and the second tunneling field effect transistor directly adjacent a third tunneling field effect transistor, and wherein a first distance between the floating gate of the first tunneling field effect transistor and the floating gate of the second tunneling field effect transistor is smaller than a second distance between the floating gate of the second tunneling field effect transistor and the floating gate of the third tunneling field effect transistor.