Patent ID: 8536910
Filing Date: 2013-09-17
Classification: H03D,H03L

Abstract:
1. A phased-locked loop (PLL) circuit comprising: a phase-frequency detector (PFD) configured to receive a reference signal; a voltage-controlled oscillator (VCO) configured to produce a VCO signal; a divider configured to divide the VCO signal thereby producing a feedback signal and a frequency lock detector (FLD) configured to determine whether the frequency of the VCO signal is locked to the frequency of the reference signal; wherein, when the feedback signal is not locked to the reference signal, the PFD compares an edge of the reference signal with an edge of the feedback signal such that the PFD produces a first error signal, wherein, when the feedback signal is locked to the reference signal, the PFD compares the edge of the reference signal to an edge of the VCO signal such that the PFD produces a second error signal and the divider is configured to be disabled; wherein after the frequency of the VCO signal is locked to the frequency of the reference signal, the FLD is switched off after a first period of time; wherein after the FLD is switched off, the FLD is switched on after a second period of time.