Patent ID: 6466635
Filing Date: 2002-10-15
Classification: H03L

Abstract:
A method for generating an output clock signal from a main clock signal having a predetermined main frequency and from a secondary clock signal, the method comprising the steps of:selectively generating as the output clock signal a first auxiliary clock signal responsive to a control logic signal having a first state, the first auxiliary clock signal having a first auxiliary frequency equal to the predetermined main frequency plus a predetermined frequency difference greater than a frequency accuracy of the secondary clock signal; selectively generating as the output clock signal a second auxiliary clock signal responsive to the control logic signal having a second state, the second auxiliary signal having a second auxiliary frequency equal to the predetermined main frequency minus the predetermined frequency difference; the first and second states of the control logic signal determining as a function of a phase difference between the output clock signal and the main clock signal, wherein a frequency difference with respect to the predetermined main frequency is below a predetermined threshold dependent upon the frequency difference and on the frequency accuracy of the secondary clock signal, even for a temporary loss of the main clock signal.