Patent ID: 8030196
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures, the method comprising: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form at least one capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; ion-implanting the pFET transistor with a second dopant; and remaining at least or capped gate conductor in the finished CMOS structure, wherein ion-implanting at least one of the transistors substantially dopes its source and drain regions, but not its gate region.