Patent ID: 6545326
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A semiconductor device comprising:a gate electrode of an MISFET, formed over a main surface of a first semiconductor region of a first conductivity type formed in a semiconductor body; a side wall spacer formed on a side surface of said gate electrode; second semiconductor regions having a second conductivity type opposite to said first conductivity type and formed in said first semiconductor region such that a channel forming region of said MISFET is formed between said second semiconductor regions; third semiconductor regions having said second conductivity type and formed in said first semiconductor region such that said second semiconductor regions are formed between said third semiconductor regions, wherein said third semiconductor regions include a first impurity; fourth semiconductor regions having said second conductivity type and formed in said first semiconductor region such that said second semiconductor regions are formed between said fourth semiconductor regions, wherein said fourth semiconductor regions include a second impurity different from said first impurity; and a cobalt silicide layer formed in said third semiconductor regions, wherein said third and fourth semiconductor regions are formed in self-alignment with said side wall spacer such that an impurity concentration of said third semiconductor regions is greater than an impurity concentration of said fourth semiconductor regions and such that a junction depth of said fourth semiconductor regions is greater than a junction depth of said third semiconductor regions, and wherein said cobalt silicide layer has an average thickness t such that a junction depth of said fourth semiconductor regions is greater than 4Ã—t.