Patent ID: 6605927
Filing Date: 2003-08-12
Classification: G11C,H03K

Abstract:
A circuit configuration, comprising:a first capacitor having a first electrode connected to reference-ground potential and a second electrode; a second capacitor having a first electrode connected to reference-ground potential and a second electrode; a first field effect transistor having a source electrode and a drain electrode connected between said second electrode of said first capacitor and said second electrode of said second capacitor; a voltage source having an internal resistance connected in parallel with said second capacitor; a second field effect transistor and a third field effect transistor connected to form a series circuit; a first common node between said source electrode of said first field effect transistor and said first capacitor connected to reference-ground potential via said series circuit formed of said second field effect transistor and said third field effect transistor; a fourth field effect transistor and a fifth field effect transistor connected to form a series circuit; a second common node between said drain electrode of said first field effect transistor, said second capacitor, and said voltage source connected to reference-ground potential via said series circuit formed of said fourth field effect transistor and said fifth field effect transistor; said first, fourth and fifth field effect transistors each having a gate electrode connected to a common node between said second and third field effect transistors; a sixth field effect transistor having a gate electrode and having a path connected between reference-ground potential and a common node between said fourth and fifth field effect transistors, and said second field effect transistor having a gate electrode connected to said common node between said fourth and fifth field effect transistors; an inverter having an input and having an output connected to said gate electrode of said sixth field effect transistor; and a control unit having a control output connected to a gate electrode of said third field effect transistor and to said input of said inverter.