Patent ID: 6819724
Filing Date: 2004-11-16
Classification: G11B,H03M

Abstract:
A Viterbi decoder comprising:a branchmetric operating circuit for conducting branchmetric operation for input data using plural target values which are reference values for the branchmetric operation so as to generate a selection signal; a path memory for outputting decoded data series produced by Viterbi-decoding said input data based on said selection signal outputted from said branchmetric operating circuit; a data estimating circuit for outputting estimation data estimating an input data at a time earlier by a predetermined bit cycle than said input data based on said decoded data series outputted from said path memory; and a target value computing means for correcting the target values with a difference between said estimation data outputted from said data estimating circuit and said input data, as a target value error, and outputting obtained plural first target values to said branchmetric operating circuit as said plural target values.