Patent ID: 6285615
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A multiple output current mirror in an integrated circuit, comprising:a first set of N transistors, where N is greater than two, wherein the drain of each transistor of said first set has its drain connected to its gate, and wherein the drains of all N transistors of said first set are connected together to provide a reference current; anda plurality of second sets of N transistors, wherein the drains of all the transistors within a given one of said second sets are connected together to provide a corresponding plurality of currents,wherein the gates of all of said transistors are connected together and the sources of all of said transistors are at the same voltage level,wherein said transistors are physically arranged in the integrated circuit as N partial current mirrors, each comprising one transistor from said first set and one transistor from each of said second sets, wherein the transistors in each of said partial current mirrors are in a linear arrangement, and wherein the transistors in the linear arrangement of each of said partial current mirrors are ordered in a differing permutation.