Patent ID: 6169438
Filing Date: 2001-01-02
Classification: H03K

Abstract:
A delay circuit for generating a selectable delay comprising: a first delay module having a first delay module signal input adapted to receive an electrical signal to be delayed, a first delay module clock input and a first delay module signal output; a first selector having a first selector first input in electrical communication with the first delay module signal input, a first selector second input in electrical communication with the first delay module signal output, a first selector output and a first selector control input;a second delay module having a second delay module signal input in electrical communication with the first selector output, a second delay module clock input and a second delay module signal output; and a second selector having a second selector first input in electrical communication with the first delay module signal input, a second selector second input in electrical communication with the first delay module signal output, a second selector third input in electrical communication with the second delay module signal output, a second selector output and a second selector control input, wherein a selected pulse delay is generated in response to a first and second control signal received at the first and second selector control inputs, respectively.