Patent ID: 9224503
Filing Date: 2015-12-29
Classification: G11B,G11C

Abstract:
1. A method comprising: applying a first signal in a first state; applying a second signal in a first state that is configured to bypass an error code correction (ECC) logic block; generating a first data pattern using a basic data generator; writing the first data pattern to a memory of a computing system unmodified; generating read memory data from a reading of the first data pattern; testing the memory with the error code correction (ECC) logic block bypassed and the first data pattern applied, wherein the read memory data is passed through the ECC logic block without modification into a data comparator and repair system, and the read memory data is compared against expected data stored in the data comparator and repair system; applying the second signal in a second state that is configured to activate the ECC logic block, wherein the second signal in the second state is applied while the first signal in the first state is still applied; generating a second data pattern using a linear feedback shift register, wherein the second data pattern is generated based on a determination that the memory is operating correctly or is found to be in a repairable state; writing the second data pattern to the memory, wherein modifications are added to the second data pattern by the ECC logic block; generating second read memory data from a reading of the second data pattern; testing the memory with the ECC logic block enabled and the second data pattern applied, wherein the second read memory data is passed into the ECC logic block with the added modifications; applying the first signal in a second state that is configured to enable the ECC logic block for post manufacture in-system testing; applying the second signal in the first state; and testing the memory with the ECC logic block enabled and the first data pattern applied.