Patent ID: 8326565
Filing Date: 2012-12-04
Classification: G01R

Abstract:
1. A chip tester for testing at least two devices under test connected to the chip tester, wherein at least a first terminal of the a first device under test and a first terminal of a second device under test are connected to a first channel of the chip tester via a shared line, wherein a second terminal of the first device under test is connected to a second channel of the chip tester via an unshared line, and wherein a second terminal of the second device under test is connected to a third channel of the chip tester via an unshared line, the chip tester comprising: a timing calculator for generating a timing information for the channels of the chip tester, wherein the timing calculator is adapted to acquire a propagation delay difference information describing a difference between, on the one hand, a propagation delay from a first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the first terminal of the second device under test, and wherein the timing calculator is adapted to provide timing information to adjust a timing shift between timings of the second channel and the third channel on the basis of the propagation time difference information; and a channel module configurator adapted to configure the second channel and/or the third channel of the chip tester on the basis of the timing information.