Patent ID: 8976922
Filing Date: 2015-03-10
Classification: G09G,G11C

Abstract:
1. A shift register unit, wherein, comprising: a capacitor having two electrodes, wherein a first electrode is connected to an output; a first transistor, a gate and a source of which are connected to a signal input, respectively, a drain of which is connected to a second electrode of said capacitor; a second transistor, a gate of which is connected to a reset end, a source of which is connected to the drain of said first transistor, a drain of which is connected to a low-level end; a third transistor, a gate of which is connected to the drain of said first transistor, a source of which is connected to a first clock signal input, a drain of which is connected to said output; a fourth transistor, a gate of which is connected to said reset end, a source of which is connected to said output, a drain of which is connected to said low-level end; a fifth transistor, a source of which is connected to the source of said second transistor, a drain of which is connected to said low-level end; a sixth transistor, a gate of which is connected to the gate of said fifth transistor, a source of which is connected to the source of said fourth transistor, a drain of which is connected to the drain of said fourth transistor; a de-noising model, a first feedback end of which is connected to said output, a low-level input of which is denoted as a second input being connected to said low-level end, a de-noising control end of which is connected to the gate of said fifth transistor, a high-level input of which is denoted as a third input being connected to said first dock signal end or high-level end; wherein said de-noising control model comprises: a seventh transistor, a gate of which is connected to said first clock signal end or high-level end, a source of which is connected to the gate of said seventh transistor, a drain of which is connected to the gate of said fifth transistor; an eighth transistor, a source of which is connected to the gate of said fifth transistor, a drain of which is connected to said low-level end; a ninth transistor, a gate of which is connected to the gate of said seventh transistor, a source of which is connected to the gate of said ninth transistor, a drain of which is connected to the gate of said eighth transistor; a tenth transistor, a gate of which is connected to said output, a source of which is connected to said the drain of the ninth transistor, a drain of which is connected to said low-level end; and an eleventh transistor, a gate of which is connected to said output, a source of which is connected to the gate of said fifth transistor, a drain of which is connected to said low-level end; wherein said fifth transistor and sixth transistor are switched on when the de-noising control end of said de-noising control model is at high-level and switched off when the de-noising control end of said de-noising control model is at low-level, so that said fifth transistor and sixth transistor are switched on when a noise voltage presents and pull down the noise voltage by the low-level end, and said fifth transistor and sixth transistor are switched of when no noise voltage presents and normal operation of said shift register unit is not affected.