Patent ID: 7558431
Filing Date: 2009-07-07
Classification: H04N

Abstract:
1. A method for applying pipeline architecture with a common process module to discrete cosine related transform, comprising: inputting a sequence of numerical data in turn to a first buffer as a first numerical set; performing a first computing phase of said discrete cosine related transform to said first numerical set with said common process module after said first numerical set has been inputted from said first buffer, and then outputting computing result to a second buffer as a second numerical set; performing a second computing phase of said discrete cosine related transform to said second numerical set with said common process module after said second numerical set has been inputted from said second buffer, and then outputting computing result to a third buffer as a third numerical set; performing a third computing phase of said discrete cosine related transform to said third numerical set with said common process module after said third numerical set has been inputted from said third buffer, and then outputting computing result to a fourth buffer as a fourth numerical set; performing a fourth computing phase of said discrete cosine related transform to said fourth numerical set with said common process module after said fourth numerical set has been inputted from said fourth buffer, and then outputting computing result to a fifth buffer as a fifth numerical set; and outputting said fifth numerical set after said fourth computing phase has been finished; wherein said common process module is formed of at least a process element having a plurality of computing abilities listed beneath: adding a first input value and a second input value to output a first output value, and subtracting said second input value from said first input value and then multiplying by a coefficient to output a second output value; bypassing said first input value and said second input value directly to output said first output value and said second output value respectively; multiplying said first input value by said coefficient to output said first output value, and bypassing said second input value to output said second output value; bypassing said first input value to output said first output value, and adding said first input value and said second input value to output said second output value; adding said first input value, a third input value and a fourth input value together to output said first output value, and adding said second input value and a fourth input value to output said second output value; adding said first input value, said second input value, and said third input value together to output said first output value, and bypassing said second input value directly to output said second output value; adding said first input value and the product of said second input value and said coefficient to output said first output value, and subtracting the product of said second input value and said coefficient from said first input value to output said second output value; bypassing said first input value to output said first output value directly, and adding said second input value and said third input value to output said second output value; and adding said first input value and said third input value to output said first output value, and adding said first input value, said second input value, said third input value, and said fourth input value together to output said second output value.