Patent ID: 6133744
Filing Date: 2000-10-17
Classification: G01R

Abstract:
An apparatus for testing a semiconductor wafer, comprising:a substrate;at least one chip mounted on an upper surface of said substrate, said chip functioning as a tester, said chip being electrically connected to a contact formed on a lower surface of said substrate through an internal wiring formed in said substrate;an elastic contact film having at least one first bump formed on an upper surface thereof and at least one second bump formed on a lower surface thereof, said first bump being electrically connected to said second bump through an internal wiring formed throughout said contact film, said contact film disposed between said substrate and a semiconductor wafer to be tested so that said first bump is in electrical contact with said contact of said substrate and said second bump is in electrical contact with said semiconductor wafer to be tested;wherein said at least one first bump formed on an upper surface of said elastic contact film and said at least one second bump formed on a lower surface of said resilient contact film are disposed in non-alignment with respect to one another.