Patent ID: 7863962
Filing Date: 2011-01-04
Classification: H03K

Abstract:
1. An output buffer comprising: a first inverter stage having a first PMOS transistor, the first PMOS transistor having a gate, a source, and a drain, the source being directly connected to a system power supply line; a second inverter stage having a second PMOS transistor, a first voltage drop block directly connected to the second PMOS transistor, and an NMOS transistor directly connected to the first voltage drop block, the second PMOS transistor having a gate, a source, and a drain, the source of the second PMOS transistor being directly connected to the system power supply line, the drain of the second PMOS transistor being directly connected to the gate of the first PMOS transistor; and a third inverter stage having a second voltage drop block directly connected to the system power supply line, a third PMOS transistor directly connected to the second voltage drop block, a third voltage drop block directly connected to the third PMOS transistor, and an NMOS transistor directly connected to the third voltage drop block, the third PMOS transistor having a gate, a source, and a drain, the drain of the third PMOS transistor being directly connected to the gate of the second PMOS transistor.