Patent ID: 6753575
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A transistor, comprising;a substrate; a first buried layer formed of an n-type material on the substrate; a second p-type formed of p-type material formed on the first layer; a drain region formed proximate the second p-type layer; a source region formed proximate the second p-type; a gate formed over at least a part of the source region; a first p-type region formed in the second p-type layer about the source region, the first p-type region having a higher p-type doping than the second p-type layer; a second p-type region formed proximate the second p-type layer and formed proximate the first p-type region; and a deep n-type region formed in the second p-type layer and proximate the first buried layer together forming a guardring about the drain region.