Patent ID: 8923060
Filing Date: 2014-12-30
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory device, comprising: a memory cell array including a plurality of strings, each string including at least one ground select transistor, a plurality of memory cells and at least one string select transistor sequentially stacked on a substrate in a direction perpendicular to the substrate; a word line driver configured to drive a selected word line and unselected word lines among a plurality of word lines connected with the plurality of memory cells of each string respectively and to supply voltages to the plurality of word lines; and a read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of strings respectively, the read/write circuit being configured to adjust levels of the bias voltages applied to the plurality of bit lines according to a location of the selected word line among the plurality of word lines.