Patent ID: 6084295
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A semiconductor device, comprising:a circuit board having a first surface, a second surface opposite to said first surface, a first region for receiving a semiconductor chip, and a second different region for receiving external connecting terminals;a semiconductor chip having a first surface on which electrode terminals are arranged in an area-array manner and a second surface opposite to said first surface, said semiconductor chip being mounted on said circuit board in such a manner that said second surface of the semiconductor chip is in abutting contact with said first surface at the first region of the circuit board;a plurality of bonding pads arranged on said first surface of the circuit board at said second region;a plurality of bonding wires, each including a conductive wire and an electro-insulating coating for covering said conductive wire, for electrically connecting said electrode terminals of the chip to said bonding pads; andexternal connecting terminals arranged on said second surface of the circuit board in an area-array manner at the second region, said external connecting terminals being electrically connected to said bonding pads by conductive vias provided through a thickness direction of said circuit board,wherein connecting portions between said bonding wires and said electrode terminals, and connecting portions between said bonding wires and said bonding pads, are coated with an electro-insulation film,wherein said semiconductor chip, said first surface of the second region of the circuit board, and said bonding wires, are encapsulated by an electro-conductive resin, andwherein an electric potential of said electro-conductive resin is set at ground level.