Patent ID: 8988936
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. A monolithic three-dimensional integrated circuit, comprising: a three-dimensional memory array including a plurality of memory cells, the plurality of memory cells includes a first memory cell and a second memory cell, the first memory cell is formed above the second memory cell, the second memory cell is formed above a substrate, the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate; a plurality of voltage generators, the plurality of voltage generators generates a plurality of bit line voltage options associated with a programming operation; and a first memory cell programming circuit in communication with the first memory cell, the first memory cell programming circuit determines a first state associated with the first memory cell and determines an upper current threshold based on the first state, the first memory cell programming circuit selects a first bit line voltage of the plurality of bit line voltage options based on whether an output current associated with the first memory cell is greater than the upper current threshold, the first memory cell programming circuit causes the first bit line voltage to be applied to the first memory cell during the programming operation.