Patent ID: 7501655
Filing Date: 2009-03-10
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a gate line formed on a substrate; a first insulating layer formed on the gate line; a semiconductor layer formed on the first insulating layer; a data line formed over the first insulating layer and intersecting the gate line; a drain electrode formed at least on the semiconductor layer; a conductor formed at the same layer as the data line, made of the same material as the data line, arranged in parallel to the data line and apart from the data line in a first direction; a second insulating layer formed on the data line, the drain electrode, and the conductor and having a first contact hole exposing a portion of the drain electrode; and a pixel electrode formed on the second insulating layer and connected to the drain electrode through the first contact hole, wherein the pixel electrode covers a width of the data line.