Patent ID: 6425063
Filing Date: 2002-07-23
Classification: G06F

Abstract:
A method of memory management, where a first memory and a second memory operate in parallel, respectively operating as two memories belonging to a first and a second parallel operating processor, where respective memories are accessed for read and/or write instructions through a memory bus and correlated in time slots with instruction cycles belonging to the execution work of said processors, and where said second memory shall contain information corresponding to said first memory, wherein said memory management includes:detecting empty time slots on said memory bus, wherein said memory management is performed solely in said detected empty time slots; and writing of a memory content of said first memory into said second memory during a start-up phase in conjunction with a new start or a re-start of said second processor and therewith said second memory, wherein: a memory content belonging to a first memory address in said first memory is read from said first memory and written to a corresponding memory address in said second memory in a first detected empty time slot, wherein a memory content belonging to a second memory address in said first memory is read from said first memory and written to a corresponding memory address in said second memory in a second detected empty time slot, this procedure being repeated until the memory content of said second memory is the same as the memory content of said first memory; said start-up phase is performed during continuous operation of said first processor; and all write instructions to memory addresses that have already been read and belong to said first memory are also written into said second memory during said start-up phase.