Patent ID: 6631439
Filing Date: 2003-10-07
Classification: G06F,Y02D

Abstract:
A processor chip, comprising:a processing core; at least one bank of DRAM memory; an I/O link configured to communicate with other like processor chips or compatible I/O devices; and a communication and memory controller in electrical communication with said processing core, said at least one bank of DRAM memory, and said I/O link; an external memory interface in electrical communication with said communication and memory controller, said external memory interface configured to connect said processor chip in electrical communication with external memory; said communication and memory controller configured to control the exchange of data between said processor chip and said other processor chips or I/O devices, and said communication and memory controller configured to receive memory requests from said processing core and from said other processor chips via said I/O link, determine whether said memory requests are directed to said at least one bank of DRAM memory on said processor chip or said external memory, and process said memory requests with said at least one bank of DRAM memory on said processor chip or with said external memory through said external memory interface.