Patent ID: 6383912
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A process for producing a microelectronic device which comprises:(a) forming a first dielectric layer on a substrate; (b) forming a second dielectric layer on the first dielectric layer wherein the first dielectric and the second dielectric have substantially different etch resistance properties; (c) forming a sacrificial metal layer on the second dielectric layer; (d) depositing a layer of a photoresist on the sacrificial metal layer and imagewise removing a portion of the photoresist corresponding to at least one via for the first dielectric layer; (e) sequentially removing the portions of the sacrificial metal layer, the second dielectric layer and the first dielectric layer under the removed portion of the photoresist thus forming at least one via through the first dielectric layer; and removing the balance of the photoresist layer; (f) depositing a layer of an additional photoresist on the sacrificial metal layer and in the via, and imagewise removing a portion of the additional photoresist corresponding to at least one trench for the second dielectric layer; (g) sequentially removing the portions of the sacrificial metal layer and the second dielectric layer under the removed portion of the additional photoresist thus forming at least one trench through the second dielectric layer; and removing the balance of the additional, photoresist layer; (h) lining a barrier metal on inside walls and a floor of the trench and on inside walls and a floor the via; (i) filling the trench and via with a fill metal in contact with the lining of the barrier metal.