Patent ID: 7174405
Filing Date: 2007-02-06
Classification: G06F

Abstract:
1. A system for updating register values on a daughtercard connected to a host by a host/daughtercard bus, said system comprising: a host interface configured to issue write commands for writing data from the host to the daughtercard over the host/daughtercard bus, with the write command including an address field specifying a location on the daughtercard where data is to be written, a first field for holding an opcode, and data field holding data to be written to the daughtercard where the host interface inserts a first opcode in the first field if data included in the write command is to be written to a selected register, inserts a second opcode in the first field if data included in the write command is to be used as a mask to set selected bits in a register word held in the selected register, and inserts a third opcode in the first field if the data included in the write command is to be used as a mask to clear selected bits in a register word held in the selected register; and a daughtercard interface for receiving the write commands and decoding the first field in the command to either write the data included in the write command to the selected register if the first opcode is held in the first field, to utilize the data included in the write command as a mask to set selected bits in a word held in the selected register if the second opcode is included in the first field, or to utilize the data included in the write command as a mask to clear selected bits in the word included in the selected register if the third opcode is included in the first field.