Patent ID: 6966018
Filing Date: 2005-11-15
Classification: G01R

Abstract:
1. An automated test equipment (ATE) comprising: a plurality of per-pin testing units, wherein each of said plurality of per-pin testing units has circuitry for at least one of emitting a signal to, or receiving a signal from, a pin of a device under test (DUT) having a plurality of DUT pins, and wherein, during a testing sequence, said DUT is defined as (a) a first DUT core that represents a first functional unit of said DUT and (b) a second DUT core that represents a second functional unit of said DUT; an assigning component that assigns, during said testing sequence, (a) a first subset of said plurality of per-pin testing units to a first ATE-port, for interfacing with said first DUT core via a first subset of said plurality of DUT pins, and (b) a second subset of said plurality of per-pin testing units to a second ATE-port, for interfacing with said second DUT core via a second subset of said plurality of DUT pins; and a programming component that (a) obtains a first specification for testing said first DUT core, prepares a first program based on said first specification, and programs said first ATE-port with said first program, and (b) obtains a second specification for testing said second DUT core, prepares a second program based on said second specification, and programs said second ATE-port with said second program, wherein said first and second ATE-ports are sequenced independently of one another during execution of said first and second programs.