Patent ID: 6445234
Filing Date: 2002-09-03
Classification: G11C,H03L

Abstract:
An apparatus for accelerating an initial lock time of DLL (Delayed Locked Loop) which removes skew between an external synchronization clock signal and an internal clock signal, comprising:means for generating a reference clock signal based on the external synchronization clock signal; means for applying a unit delay time and a multiple unit delay time to the internal clock signal and for comparing phases of the internal clock signal, a unit delayed internal clock signal and a multiple unit delayed internal clock signal with a phase of the reference clock signal; means for selecting an amount of delay time based on a comparison result; means for delaying the internal clock signal by the amount of delay time based on a selected amount of delay time; and means for generating a modeled delay clock signal corresponding to a delayed internal clock signal and for providing the modeled delay clock signal with said means for applying a unit delay and a multiple unit delay time.