Patent ID: 7205189
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A method of fabricating a dual bit flash memory, comprising the steps of: providing a substrate; forming a tunneling dielectric layer over the substrate; forming a patterned mask layer over the tunneling dielectric layer, wherein the patterned mask layer has a trench; forming a conductive layer over the substrate to cover the surface of the trench; removing a portion of the conductive layer to form a pair of conductive spacers on the respective sidewalls of the trench to serve as floating gates; removing the patterned mask layer; forming an inter-gate dielectric layer over the substrate to cover the floating gates and the tunneling dielectric layer; forming a control gate over the inter-gate dielectric layer above the conductive spacers; forming a pair of dielectric spacers on the sidewalls of the control gate; removing portions of the inter-gate dielectric layer and the tunneling dielectric layer by using the dielectric spacers and the control gate as hard masks; and forming source/drain regions in the substrate on each side of the control gate.