Patent ID: 8022381
Filing Date: 2011-09-20
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array including a plurality of memory cells, a plurality of bit lines each commonly connecting one end of the plurality of memory cells arranged in a first direction of the cell array and a word line commonly connecting the other end of the plurality of memory cells arranged in a second direction of the cell array; and a read/write circuit for reading and writing data of said cell arrays, the read/write circuit comprising: a logic pulse generation circuit for generating a first logic pulse and a second logic pulse being controlled to have overlap width therebetween in correspondence with write data; and a write pulse generation circuit for generating a first write pulse and a second write pulse from the first and second logic pulses in correspondence with write data, the second write pulse being boosted by the overlap between the first and second logic pulses to have a peek level higher than that of the first write pulse, and supplying the first and the second write pulse to selected word lines and selected bit lines in each said cell array, wherein each memory cell includes a stack structure of a variable resistance element and a diode serially connected and disposed at the cross portion of the bit line and the word line, the diode having a polarity with the bit line side as a cathode and with the word line side as an anode, and the bit line and the word line are so potentially fixed as to reversely bias the diode in a non-selected mode, while the bit line and the word line are pulse driven in negative and positive directions, respectively, in data read and write modes.