Patent ID: 6834362
Filing Date: 2004-12-21
Classification: G06F,H04L

Abstract:
An apparatus for detecting errors on a source-synchronous bus, comprising:the source-synchronous bus, wherein the source-synchronous bus includes a plurality of data lines and a clock line; a transmitting mechanism coupled to the source-synchronous bus, wherein the transmitting mechanism is configured to transmit data on the source-synchronous bus; a receiving mechanism coupled to the source-synchronous bus, wherein the receiving mechanism is configured to receive data from the source-synchronous bus; an error detecting mechanism coupled to the receiving mechanism that is configured to detect errors on the source-synchronous bus; a grouping mechanism coupled to the transmitting mechanism that is configured to group data bits into an error group, wherein the grouping mechanism is further configured to skew data bits within the error group across time; a detection code generating mechanism coupled to the grouping mechanism that is configured to generate a detection code for the error group; and the transmitting mechanism that is further configured to transmit the detection code on the source-synchronous bus using a clock cycle other than the clock cycles used for transmitting data bits of the error group, wherein at a given instant in time each data line in the plurality of data lines carries a data bit from a different error group; wherein each data bit in the error group is transmitted at a different time so that no two bits associated with the error group are transmitted at the same time; wherein the receiving mechanism is further configured to deskew the data bits in the error group; and wherein the error detecting mechanism can detect errors in the error group including errors that are caused by an error on the clock line.