Patent ID: 6026045
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A semiconductor memory device having a multibank comprising:a memory cell array divided into a plurality of banks, the plurality of banks being alternately arranged, and having a plurality of unit memory cell arrays;a column decoder having a plurality of output ports arranged so that the output ports are alternately connected to the column selection lines of one of the banks, for enabling the column selection lines of one of the banks in response to address decoding signals and bank selection signals;a column address buffer for buffering an externally input column address;a bank selection bit buffer for buffering externally input bank selection bits;a first column predecoder for decoding some of the output signals of the column address buffer and generating the address decoding signals;a second column predecoder for decoding the remaining output signals of the column address buffer in response to output signals of the bank selection bit buffer and a delayed internal clock signal and generating the bank selection signals;a clock buffer for buffering an externally input clock signal and generating an internal clock signal; andfirst and second delays for delaying the internal clock signal and generating the delayed clock signal and reset pulse, respectively.