Patent ID: 8843874
Filing Date: 2014-09-23
Classification: G01R,G06F

Abstract:
1. A method that optimizes power and timing by modifying a voltage supplied to each of a population of integrated circuit (IC) chips, while meeting power consumption and timing delay performances for each of said population of IC chips across lower and higher temperature ranges, said method comprising: conducting a closed timing analysis on an IC chip design, using an IC technology that exhibits temperature inversion, to select said timing delay performance over a multi-dimensional parameterized space, including a higher voltage range being applied across a full temperature range, said full temperature range being divided into a lower temperature range and a higher temperature range, and a lower voltage range being applied across said higher temperature range; segmenting a full range of said timing delay performance into N selective voltage bins, each of said population of IC chips, manufactured to said IC chip design, belonging to one of said N selective voltage bins and each of said N selective bins being associated with a high bin voltage and a low bin voltage; selecting each of said high bin voltages for each of said N selective voltage bins from said higher voltage range to be supplied to each of said population of IC chips in corresponding ones of said N selective voltage bins, each of said high bin voltages for each of said N selective voltage bins meeting said timing delay performance across said full temperature range and said power consumption performance across said lower temperature range and a portion of said higher temperature range extending from a lower bound of said higher temperature range to a temperature cut point within a range of temperature cut points in said higher temperature range; selecting each of said low bin voltages for each of said N selective voltage bins from said lower voltage range to be supplied to each of said population of IC chips in said corresponding ones of said N selective voltage bins, each of said low bin voltages for each of said N selective voltage bins meeting said timing delay performance and said power consumption performance from said temperature cut point to an upper bound of said higher temperature range; powering-on each of said population of IC chips in each of said corresponding ones of said N selective voltage bins at each of said high bin voltages for each of said N selective voltage bins; after said powering-on, monitoring a temperature of each of said population of IC chips; and lowering said high bin voltage supplied to each of said population of IC chips in each of said corresponding ones of said N selective voltage bins to said low bin voltage for each of said corresponding ones of said N selective voltage bins, when said temperature cut point is exceeded for each of said population of IC chips in each of said corresponding ones of said N selective voltage bins, to meet said power consumption performance while meeting said timing delay performance.