Patent ID: 8559210
Filing Date: 2013-10-15
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a transistor array having plural transistors; and plural memory elements provided, one for each of the plural transistors, wherein, the transistor array includes (a) a substrate having diffusion layers of the plural transistors on a surface thereof, (b) plural parallel word lines on the substrate, (c) plural parallel first bit lines provided in a direction perpendicular to the word lines, (d) bit contact electrodes provided between the adjacent two word lines and connecting the first bit lines and the diffusion layers, and (e) node contact electrodes provided at an opposite side to the bit contact electrodes with the respective adjacent two word lines in between and connected to the diffusion layers; the plural memory elements have (a) lower electrodes connected to the node contact electrodes and provided with respect to each of the plural memory elements in positions shifted from immediate above the node contact electrodes closer to the bit contact electrodes within a plane in parallel to the surface of the substrate, (b) memory layers provided on the lower electrodes and having resistance values reversibly changing by voltage application, and (c) plural parallel second bit lines extending in the same direction as that of the first bit lines on the memory layers; and the respective plural second bit lines are superimposed on the lower electrodes connected to the node contact electrodes at both sides of the first bit lines.