Patent ID: 6138223
Filing Date: 2000-10-24
Classification: G06F

Abstract:
A method for use in a computer system having an address adder and an address incremeter generating virtual logical addresses having page number bits and other bits for processing an instruction logical request, having a branch history table (BHT), and having an instruction address AAHT (Absolute Address History Table) for holding the prediction of virtual address to real address translation information which is used for predicting a computer system instruction logical request to access a cache holding instruction data which may be executed which the cache uses to process a physical request indicated by the logical request, comprising the steps of:calculating an index value, for storing into and accessing from a virtual logical address translation to a physical address of a request for an instructions held in said cache for said absolute address history table (AAMT), based on the page number portion of all virtual logical addresses including a base address, an index address and a displacement that are used by the address adder or a register address and incrementer value of the address incrementer to generate instruction logical requests to the cache for said stored instruction data thereby to reduce the number of absolute translation compares that said computer system needs to do in processing instructions and as a result to thereby improve computer system cycle time.