Patent ID: 7315956
Filing Date: 2008-01-01
Classification: G06F,H03L,H04W,Y02D,Y10S

Abstract:
1. A method for generating a calibrated clock, comprising: receiving a free-running fast clock; receiving a free-running slow clock; modifying the free-running slow clock with a fractional-N clock divider which removes clock cycles from the free-running slow clock in response to specified fraction and modulus values, and information obtained by comparing the free-running slow clock to the free-running fast clock, to provide a calibrated slow clock having a specified frequency relationship to the slow clock; providing a phase compensation value that represents a phase error for each clock cycle of the calibrated slow clock, wherein the phase compensation value increases with each slow clock cycle until a clock cycle is removed and then the chase compensation value is decreased accordingly; and deriving event timing from the calibrated slow clock and the phase compensation value to provide event timing with the accuracy of the free-running fast clock.