Patent ID: 6735130
Filing Date: 2004-05-11
Classification: G11C

Abstract:
A memory bus for communications between a memory and circuitry comprising:a first self-timing transmitter associated with said memory for receiving a first input signal from said memory, said first self-timing transmitter operative to output a first differential output signal dependent upon said first input signal, wherein said first self-timing transmitter and comprises: (a) a buffer that receives said first input and outputs a first differential voltage onto a first carrier bus (Busp); (b) an inverter that inverts said first input and outputs a second differential voltage onto a second carrier bus (Busn) that is the inverse of said first input; and (c) timing signal transistors located on said first carrier bus and second carrier bus that in response to a timing signal selectively allow said first differential voltage and second differential onto said first carrier bus and second carrier bus, respectively; a second self-timing receiver associated with said circuitry adapted to receive said first differential output signal and operative to output a first received signal to said circuitry dependent upon said first differential output signal; a second self-timing transmitter associated with said circuitry for receiving a second input signal from said circuitry, said second self-timing transmitter operative to output a second differential output signal dependent upon said second input signal, wherein said second self-timing transmitter and comprises: (a) a buffer that receives said second input and outputs a first differential voltage onto a first carrier bus (Busp) of the second self-timing transmitter; (b) an inverter that inverts said second input and outputs a second differential voltage that is the inverse of said second input onto a second carrier bus (Busn) of the second self-timing transmitter; and (c) timing signal transistors located on said first carrier bus and second carrier bus of that second self-timing transmitter that in response to a timing signal selectively allow said first differential voltage and second differential onto said first carrier bus and second carrier bus of said second self-timing transmitter, respectively; and a first self-timing receiver associated with said memory adapted to receive said second differential output signal and operative to output a second received signal to said memory dependent upon said second differential output signal.