Patent ID: 7804719
Filing Date: 2010-09-28
Classification: H03K

Abstract:
1. An integrated circuit, comprising: a plurality of memory cells implementing a random access memory (RAM), the RAM being coupled to receive a write data input signal and a write enable signal; a multiplexer structure having a plurality of data input terminals, a plurality of select input terminals, and an output terminal, each data input terminal being coupled to an output terminal of a corresponding one of the memory cells; a memory element having a data input terminal; a bypass select multiplexer having a first data input terminal coupled to the output terminal of the multiplexer structure, a second data input terminal coupled to receive the write data input signal, a select input terminal, and an output terminal coupled to the data input terminal of the memory element; and a control circuit having an input terminal coupled to receive the write enable signal, and further having an output terminal coupled to the select input terminal of the bypass select multiplexer.