Patent ID: 8530317
Filing Date: 2013-09-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device with metal gates, the method comprising: providing a substrate; forming a dummy gate stack on the substrate, the dummy gate stack including a high-k dielectric layer, a capping layer above the high-k dielectric layer, and a sacrificial layer above the capping layer; patterning the dummy gate stack to form dummy gates; doping source and drain regions for the gates; forming an inter-level dielectric layer that covers the source and drain regions; over at least a first region of the substrate, removing the sacrificial layer from the dummy gates to form trenches that expose the capping layer; and filling the trenches with metal to form metal gates; wherein removing the sacrificial layer from the dummy gates to form trenches includes sequentially a first stage, a second stage, and a third stage; the first stage begins the trenches, the trenches having entrance corners; the second stage is an etch that rounds the corners; the third stage increases the depth of the trenches down to the capping layer; the third stage increases the depth of the trenches at least twice as much as the second stage; and the second stage increases the trench corner rounding, measured as a radius of curvature, more than the third stage.