Patent ID: 6801468
Filing Date: 2004-10-05
Classification: G11C

Abstract:
A pseudo SRAM capable of performing a page write mode, comprising:a memory cell array composed of cells of a dynamic RAM; a page width setup section for generating a page width select signal according to a set page width, including a plurality of option pads for generating the page width select signal depending on whether the respective pads are connected to a power supply voltage or a ground voltage; a refresh control section for performing a refresh of the memory cell array by generating a refresh request signal at predetermined refresh intervals; and an operation control section for receiving an address signal, a data signal, and a write enable signal from an outside, receiving the page width select signal from the page width setup section, and the refresh request signal from the refresh control section, the operation control section, if the received address signal corresponds to the page width according to the page width select signal, controlling the refresh control section so that the refresh operation is not performed as keeping a specified row of the memory cell array activated by a previous address signal in an activation state, and performing a page write operation for writing the received data signal in columns of the memory cell array corresponding to the address signal according to a transition of the write enable signal.