Patent ID: 7046501
Filing Date: 2006-05-16
Classification: H01G,H01L,H05K

Abstract:
1. A capacitor-embedded substrate disposed between a mount substrate and a semiconductor device, comprising a decoupling capacitor formed between an input side electrode layer and an output side electrode layer via an interlayer insulating layer, the decoupling capacitor having a pair of internal electrode layers composed of a ground layer and a power source layer, and a dielectric layer formed between the pair of internal electrode layers, wherein a plurality of power supply terminals used for power supply to the semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via used for interlayer connection, and wherein the decoupling capacitor is disposed immediately below the plurality of power supply terminals, power is supplied to each of the plurality of power supply terminals from a horizontal direction perpendicular to a thickness direction of the output side electrode layer, and the length of a wiring line of the capacitor via is less than 100 μm.