Patent ID: 7634677
Filing Date: 2009-12-15
Classification: H03K,H04L

Abstract:
1. An output circuit for outputting a parallel data signal aligned with a strobe signal, comprising: a first flip-flop device receiving the parallel data signal and a first clock signal, and outputting a first latched parallel data in response to the first clock signal; and a second flip-flop device electrically connected to the first flip-flop device, receiving the first latched parallel data outputted from the first flip-flop device and the first clock signal, and outputting a second latched parallel data in response to the first clock signal; a detector electrically connected to the first flip-flop device and the second flip-flop device, detecting a level change degree of the first latched parallel data and the second latched parallel data, and outputting a select signal according to the level change degree; a delay adjusting device receiving and differentially delaying the parallel data signal into a first and a second delayed parallel data signals with a first and a second delay time, respectively; and a first multiplexer electrically connected to the detector and the delay adjusting device, and selecting one of the first and the second delayed parallel data signals to be outputted in response to the select signal.