Patent ID: 6399471
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method of fabrication of conductive lines that have supplement lines under the critical path areas of the conductive lines; comprising the steps of:a) providing a semiconductor structure having a top surface comprised of a first dielectric layer; b) forming a plurality of first level conductive lines over said first dielectric layer; said first conductive lines running in a first direction; said first level conductive lines comprised of a first level first conductive line and a first level second conductive line; c) forming a second dielectric layer over said first level conductive lines and said first dielectric layer; d) forming a via opening in said second dielectric layer over a portion of said first level first conductive line; e) forming a plug filling said via opening contacting said first level first conductive line; f) forming a trench pattern in said second dielectric layer; said trench pattern comprised of trenches that are approximately orthogonal to said first level conductive lines; g) filling said trenches with a conductive material to form supplemental second lines; h) forming second level conductive lines over at least said supplemental second lines and said plug; i) said second level conductive lines are aligned parallel to said trenches; said trenches formed in critical path areas of said second level conductive lines; said second level conductive lines have critical path areas; said second level conductive lines are not formed to contact said first level conductive lines where a contact is not desired; whereby in the critical path areas of said second level conductive lines, said supplemental second lines underlie said second level conductive lines in at least portions of the critical path area thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.