Patent ID: 7192829
Filing Date: 2007-03-20
Classification: H01L

Abstract:
1. A method of forming a plurality of floating gate transistors comprising: forming an oxide-comprising layer against and physically contacting a semiconductive substrate; forming a first layer against and physically contacting the oxide-comprising layer, wherein the first layer comprises semiconductive material and a dopant, at least some of the dopant physically contacting the oxide-comprising layer; after forming the first layer, forming a second layer against and physically contacting the first layer, wherein the second layer comprises semiconductive material, the semiconductive material of the second layer being substantially undoped; forming a third layer over the second layer, the third layer comprising dielectric material; forming a fourth layer over the third layer, the fourth layer comprising conductive material; etching the oxide-comprising layer and the first through fourth layers to form a plurality of floating gates; forming source and drain regions laterally proximate the floating gates; forming an oxide layer over the regions and the floating gates; and disposing a plug of conductive contact film operatively adjacent at least one of the drain regions, the plug of conductive material being electrically connected to the at least one of the drain regions.