Patent ID: 8258878
Filing Date: 2012-09-04
Classification: H03C,H03L

Abstract:
1. A phase-locked loop (PLL), comprising: a first phase detecting circuit, for detecting a first phase difference between an input data signal and a first feedback signal, and generating a detection output signal according to the phase difference; a first loop filter, coupled to the first phase detecting circuit, for generating a first voltage-controlled oscillator (VCO) control signal according to the detection output signal; a first voltage-controlled oscillator (VCO), coupled to the first loop filter, for generating an output data signal according to the first VCO control signal; a clock generating circuit, for generating a first clock signal; a first mixer, coupled to the first VCO and the clock generating circuit, for mixing the output data signal and the first clock signal to generate the first feedback signal; and a control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal and calculating a gain of the first VCO according to the first VCO control signal, comprising: