Patent ID: 6157045
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A semiconductor device evaluation pattern for multiple devices disposed on a semiconductor substrate and analyzing manufacturing fluctuations attributable to manufacturing devices, comprising:multiple semiconductor devices to be measured each having a same configuration, area and function, and formed on a same plane of a semiconductor substrate, said devices being arranged in an array in two directions such that nx pieces are aligned linearly in the X-direction, nx being a natural number, and ny pieces that are aligned in the Y-direction, ny being a natural number; andwiring formed on said semiconductor substrate, for measuring the sum of evaluation values to characterize the performance of the devices to be measured in a column in at least one of the array directions in the X and Y directions of the semiconductor devices to be measured, wherein the semiconductor devices to be measured are one of capacitors and resistors, and the evaluation values to characterize the semiconductor device performance are the individual unit capacitance and proximity capacitor relative precision or the individual unit resistance and proximity resistor relative precision.