Patent ID: 6365468
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method for forming a doped p-type gate with removed anti-reflection layer, comprising:providing a semiconductor substrate; etching the semiconductor substrate to form a concave portion for a shallow trench isolation; filling a first oxide layer into the shallow trench isolation; forming a n-type well into the semiconductor substrate; forming a doped p-type layer on the surface of semiconductor substrate and the surface of the shallow trench isolation; forming the anti-reflection layer on the surface of the doped p-type layer; etching portions of the anti-reflection layer and portions of the doped p-type layer to form a gate region; forming a source/drain extension by implantation; depositing a second oxide layer over the surface of the semiconductor substrate and the surface of the anti-reflection layer; etching back the second oxide layer to form a spacer beside the sidewall of the gate region; forming a source/drain region into the semiconductor substrate by implantation using the gate region and the spacer as a mask; removing the anti-reflection layer; and forming salicide regions into the source/drain region and upon the surface of the doped p-type layer.