Patent ID: 6026014
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a plurality of word lines;a plurality of first data lines;a plurality of memory cells, each having a control gate and a floating gate, and each storing data of a plurality of bits as threshold values, each of the memory cells being coupled to a corresponding word line and a corresponding first data line; anda word driver circuit coupled to the word lines to supply a read voltage to a selected word line a plurality of times in a read operation for reading the data of a plurality of bits from memory cells coupled to the selected word line; whereina first read voltage is first applied to the selected word line, and then voltages at levels higher than the first read voltage are successively applied to the word line in order to successively read data starting with data corresponding to a lowest threshold value and ending with data corresponding to a highest threshold value, whereina plurality of sense latch circuits and a plurality of precharge circuits are coupled correspondingly to the first data lines, and the first data lines are coupled to one input/output node of the sense latch circuits.