Patent ID: 7743199
Filing Date: 2010-06-22
Classification: G06F

Abstract:
1. An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip, the integrated chip having one or more peripheral I/O channels for outputting trace information to external sources, the bus architecture comprising: a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit items of trace information in a circular pathway from upstream segments to downstream segments, the plurality of segments including a respective segment for each processor of the plurality of processors, the respective segment for each processor having a coupling unit connected to a trace port of the processor, the coupling unit of the respective segment for each processor being configured to receive items of trace information from the trace port of the processor, to receive items of trace information from the adjacent upstream segment of the segmented bus, and to transmit items of trace information to the adjacent downstream segment of the segmented bus; and one or more trace output circuits each connected to a respective segment of the plurality of segments and each including a switch configured to be dynamically toggled between an enabled state and a disabled state, each trace output circuit being configured to transmit items of trace information being transmitted along the circular pathway to a respective peripheral I/O channel of the one or more peripheral I/O channels when in the enabled state, each trace output circuit being configured to transmit items of trace information being transmitted along the circular pathway to the adjacent downstream segment of the segmented bus when in the disabled state.