Patent ID: 6424192
Filing Date: 2002-07-23
Classification: H03F,H03H,H03K,H03L,H04B

Abstract:
A circuit, comprising:a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency; and a prescaler coupled to the clock generator that receives the plurality of first clock signals to generate a second clock signal based on the reference frequency that is higher than the first frequency, wherein the prescaler comprises, a divider circuit coupled to receive one of the plurality of first clock signals, a sampler circuit that receives an output signal of the divider circuits, wherein the sampler circuit outputs a plurality of third clock signals, a multiplexer coupled to receive the third plurality of clock signals and a selection signal, wherein the multiplexer outputs the second clock signal, and a counter circuit coupled between the divider circuit and the multiplexer.