Patent ID: 7847338
Filing Date: 2010-12-07
Classification: G11C,H01L

Abstract:
1. A semiconductor memory cell comprising: a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from the substrate below the isolation layer.