Patent ID: 6687321
Filing Date: 2004-02-03
Classification: H03L

Abstract:
A digital PLL circuit comprising:a variable-frequency ring oscillator configured to generate an output signal; a frequency divider configured to frequency-divide the output signal of said ring oscillator and generate a frequency-divided output signal; a phase comparator configured to compare the frequency-divided output signal of said frequency divider with a phase reference signal and generate a comparison output signal; a control signal generator configured to generate a control signal corresponding to the comparison output signal of said phase comparator and supply the control signal to said ring oscillator, wherein said ring oscillator includes: a plurality of delay circuits connected in a multistage, a multiplexer configured to select one of output signals of said delay circuits, determine the number of stages of said delay circuits and generate an output signal corresponding to the determined number of stages, an inverting delay circuit configured to invert the output signal of said multiplexer, a variable capacitor including a plurality of capacitor elements selectively connected to chance a value of capacitance, and a control circuit configured to refer to correction information and control said multiplexer for selection of said delay circuits and said variable capacitor for connection of the capacitor elements of said variable capacitor; a logical gate circuit which is connected to an output of said multiplexer and controls a passage of the output signal of the multiplexer according to a correction enable signal; and a correction information creating circuit which controls said control circuit during a time when the correction enable signal is at an active level and which, on the basis of the output signal of said multiplexer, determines an optimum value of the number of capacitors connected for the variable capacitor in association with change of the number of stages of delay circuits and creates said correction information.