Patent ID: 9209270
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method comprising: forming a gate stack over a semiconductor substrate; forming a gate spacer on a sidewall of the gate stack; etching the semiconductor substrate using the gate stack and the gate spacer as an etching mask to form a recess adjacent to the gate stack; performing a first epitaxy to grow a first SiGe region in the recess, and in-situ doping a p-type impurity to a first p-type impurity concentration; performing a second epitaxy to grow a second SiGe region over the first SiGe region, wherein the second SiGe region has a second p-type impurity concentration lower than the first p-type impurity concentration, and wherein at a starting time of the second epitaxy, a top surface of the first SiGe region has an inner end point nearest to a channel region under the gate stack, and wherein the inner end point is substantially level with a bottom surface of the gate spacer; and performing a third epitaxy to grow a third SiGe region over the second SiGe region, and in-situ doping a p-type impurity to a third p-type impurity concentration higher than the first p-type impurity concentration.