Patent ID: 6121096
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method for the formation of an implanted region for use in an MOS transistor, the method comprising the steps of:providing a semiconductor substrate with a gate oxide layer thereon;forming a polysilicon gate layer on the gate oxide layer;forming an additional oxide layer on the polysilicon gate layer, thereby forming an oxide/polysilicon stack;patterning the oxide/polysilicon stack to form a patterned oxide/polysilicon stack layer that includes a patterned additional oxide layer overlying a patterned polysilicon gate layer, and to expose portions of the gate oxide layer;forming a conformal silicon nitride layer over the patterned oxide/polysilicon stack layer and the exposed portions of the gate oxide layer;etching the conformal silicon nitride layer to form silicon nitride spacers on sidewalls of the patterned oxide/polysilicon stack layer;removing the patterned additional oxide layer leaving the silicon nitride spacers extending above the patterned polysilicon gate layer; andimplanting dopant atoms at an angle from the perpendicular to the surface of the semiconductor substrate in the range of from 5 degrees to 50 degrees, through the patterned polysilicon gate layer, into a predetermined region of the semiconductor substrate to create an implanted region while using the silicon nitride spacers as an implant mask.