Patent ID: 7005338
Filing Date: 2006-02-28
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising a first nonvolatile memory cell, the method comprising: forming a first trench in a top surface of a semiconductor substrate; forming a dielectric on a surface of the first trench; forming a conductive floating gate at least partially located in the first trench; wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET; wherein the method further comprises forming in the substrate: wherein the method further comprises forming a conductive member having a portion overlying the first trench, wherein the conductive member provides a gate for the second FET; wherein the first and second source/drain regions of the first FET and the channel region of the first FET curve around the first trench.