Patent ID: 6046936
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A semiconductor device capable of storing information having multi-levels into a single electrically erasable/programable non-volatile memory cell, comprising:a sense latch circuit having one pair of input/output terminals;bit lines provided in correspondence with the respective input/output terminals of said sense latch circuit;a plurality of electrically erasable/programable non-volatile memory cells selectively connected to said bit lines;a data latch circuit coupled to each of said bit lines;input/output means capable of interfacing said data latch circuit with an external device; andcontrol means for controlling data reading/erasing/programing operations with respect to said memory cell; wherein:said control means causes said data latch circuit to save externally supplied program data; produces program control information every time the data programing operation is carried out; and causes said latch circuit to latch the produced program control information for determining that the non-volatile memory cell is brought into any state of different threshold voltages, said non-volatile memory cell being selected to be connected to the bit line based upon the program data having plural bits saved in said data latch circuit.