Patent ID: 9082739
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor device comprising: first, second and third pads disposed on a semiconductor substrate; and a plurality of test structures disposed on the semiconductor substrate, wherein each test structure comprises: an active region having a rounded corner portion; a plurality of active patterns protruding from the semiconductor substrate and extending in parallel in a first direction; a plurality of gate electrodes crossing over the plurality of active patterns in a second direction, wherein one of the plurality of gate electrodes is electrically connected to the first pad; and first and second electrode patterns disposed on the active region, wherein one of the plurality of gate electrodes is interposed between the first and second electrode patterns, wherein the first and second electrode patterns are electrically connected to the second and third pads, respectively, wherein an overlapping area of the second electrode pattern and the plurality of active patterns in each test structure is different from an overlapping area of the second electrode pattern and the plurality of active patterns in other test structures.