Patent ID: 8319274
Filing Date: 2012-11-27
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a non-volatile memory element in which a gate dielectric formed on a main surface of a semiconductor substrate is used as a charge-trapping layer, wherein the gate dielectric has a structure in which a first insulator, a second insulator, a third insulator, and a fourth insulator are laminated in this order from a side of the semiconductor substrate, and the third insulator has a bandgap larger than a bandgap of the second insulator and has an energy barrier to charges, wherein electrons and holes are used as trapped charges for the gate dielectric used as the charge-trapping layer, the electrons are injected into the charge-trapping layer from the semiconductor substrate, and the holes are injected into the charge-trapping layer from a gate electrode formed on the gate dielectric, and wherein the third and fourth insulators have thicknesses such that the injected holes reach the second insulator by tunneling through the fourth and third insulators, the fourth insulator being formed of a silicon oxide film.