Patent ID: 8189691
Filing Date: 2012-05-29
Classification: G06F,H03F,H04L

Abstract:
1. Receiver for a differential data bus, the data bus having two bus lines, with two resistive branches with a differential amplifier with two transistors, each said transistor having an emitter and a collector, with a resistor and with a control logic that controls a switch with which a current from a current source is switchable to either side of the resistor which resistor couples the two transistors and with two operational amplifiers, each said operation amplifier having an output signal, which are coupled to the two transistors of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers whether a value “0” or a value “1” is expected on the bus and which receiver sets the switch accordingly so that a comparison with the received bus signal is made.