Patent ID: 7529130
Filing Date: 2009-05-05
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to read out data of the memory cell array, wherein a plurality of information cells, in each of which one of M(M≧2) threshold levels is written, and at least one reference cell, in which a reference threshold level is written, are defined in the memory cell array, at the data reading, a read voltage applied to the information cell is set to be equal to or near a verify-read voltage for verifying an m-th higher threshold level (m is equal to 1 or a natural number from 1 to M−1) in M threshold levels written into the information cell while a reference read voltage applied to the reference cell is set to be higher than a verify-read voltage for verifying the reference threshold level written into the reference cell by a predetermined level, and the predetermined level is lower than a difference between a verify-read voltage for verifying an m+1-th higher threshold level written into the information cell and the read voltage, and the sense amplifier circuit detects a cell current difference between information cell currents generated by sequentially applying various read voltages to the information cell and a fixed reference current generated by applying the reference read voltage to the reference cell selected simultaneously in the memory cell array to sense data defined by the M threshold levels of the information cell.