Patent ID: 6326298
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A method for forming an interlevel dielectric structure having a substantially planar upper surface, comprising:forming a spaced set of first, second and third conductors upon a semiconductor topography, comprising a first lateral distance between said first and second conductors and a second lateral distance between said second and third conductors, said second lateral distance being greater than said first lateral distance;patterning a first dielectric upon said semiconductor topography to form a dielectric structure solely between said second and third conductors;forming a CVD-sputtered second dielectric upon and between said conductors and dielectric structure, such that said second dielectric comprises elevationally raised regions above said conductors and dielectric structure and elevationally lowered regions between said conductors and dielectric structure, wherein the elevationally lowered regions are at a higher elevation than an upper surface of said conductors; andspin-on depositing a third dielectric predominantly upon the elevationally lowered regions of said second dielectric.