Patent ID: 9103877
Filing Date: 2015-08-11
Classification: G01R

Abstract:
1. A method for conducting IDDQ tests for a plurality of devices under test (DUTs) having a plurality of test sites, each DUT having a test site, comprising: (a) identifying voltage ranges for each of the plurality of test sites; (b) closing a switch in each of a plurality of voltage drop setup circuits, wherein each of the plurality of voltage drop setup circuits includes a resistor parallelly connected to the switch, and a first terminal of each of the plurality of voltage drop setup circuits is connected to a voltage source and a second terminal of each of the plurality of voltage drop setup circuits is connected to respective tester channels of each of the plurality of test sites; (c) setting each of the plurality of test sites to one of a plurality of logic states; (d) opening the switch in each of the plurality of voltage drop setup circuits; (e) measuring a voltage drop across the resistor in each of the plurality of voltage drop setup circuits; (f) determining if an IDDQ test fails for each of the plurality of test sites when a leakage current for each of the plurality of test sites exceeds a pre-determined current value by using the measured voltage drop across the resistor; and (g) repeating operations (b) through (f) until all of the plurality of logic states to be tested for each of the plurality of test sites are tested, wherein the method is executed by a processor.