Patent ID: 6235598
Filing Date: 2001-05-22
Classification: H01L,Y10S

Abstract:
A method comprising:forming an insulative layer over a substrate;forming a gate layer over said insulative layer;forming a gate electrode by patterning said gate layer and said insulative layer;forming a thick first spacer layer over said gate electrode and said substrate;forming a thick second spacer layer over said thick first spacer layer;removing said thick second spacer layer over top of said gate electrode and said substrate, leaving said thick second spacer layer adjacent to said thick first spacer layer to form thick second spacers, said thick second spacers having tops that are about level with top of said gate electrode;removing said thick first spacer layer over top of said gate electrode and said substrate by isotropic etching, leaving said thick first spacer layer adjacent to said gate electrode to form thick first spacers, said thick first spacers having tops that are lower than top of said gate electrode;forming a reactant layer over said gate electrode, said thick first spacers, said thick second spacers, and said substrate;forming a conductive layer where said reactant layer and said gate electrode are in contact, bottom of said conductive layer being approximately flat and about level with tops of said thick first spacers; andremoving any unreacted reactant layer to leave an open space between said conductive layer and said thick second spacers.