Patent ID: 7023721
Filing Date: 2006-04-04
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a plurality of first read data lines; a plurality of second read data lines; a plurality of first write data lines; a plurality of second write data lines; a plurality of first memory cells, each including a first storage transistor whose source and drain are coupled between a first potential and corresponding one of the first read data lines, and a first write transistor whose source and drain are coupled between a gate of the first storage transistor and corresponding one of the plurality of first write data lines; a plurality of second memory cells, each including a second storage transistor whose source and drain are coupled between the first potential and corresponding one of the plurality of second read data lines, and a second write transistor whose source and drain are coupled between a gate of the second storage transistor and corresponding one of the plurality of second write data lines; a pair of common data lines, one of the pair of common data lines being coupled to the plurality of first read data lines and the plurality of first write data lines via the plurality of first switches, and the other of the pair of common data lines being coupled to the plurality of second read data lines and the plurality of second write data lines via a plurality of second switches; and a sense amplifier coupled to the pair of common data lines.