Patent ID: 9130552
Filing Date: 2015-09-08
Classification: H02M,H03K,Y02B

Abstract:
1. An integrated circuit comprising: a detector configured to monitor a high-drive signal and a low-drive signal that drive a high-side switch and a low-side switch, respectively, of a switching regulator that is part of the integrated circuit, wherein the detector monitors both a rising edge and a trailing edge of each of the high-drive and the low-drive signals, respectively, to determine a timing overlap between the signals, and to generate a detection signal having a value proportional to a presence or absence of the timing overlap between the high-drive and the low-drive signals; and an output circuit configured to process the detection signal from the detector to provide an output characterizing at least one of a dead-time or cross-conduction of the switching regulator and to adjust the timing in the next switching cycle to prevent or reduce cross-conduction of the switching regulator, wherein the output circuit further comprises a flip flop that is clocked from the detection signal of the detector to provide a fifty percent duty cycle signal representing the timing overlap between the signals.