Patent ID: 8495471
Filing Date: 2013-07-23
Classification: G06F,G11C

Abstract:
1. A solid-state storage system, comprising: a plurality of integrated circuits for storing data; a controller coupled to the plurality of integrated circuits via one or more of a plurality of channels, the controller operably controls the operations of the plurality of integrated circuits and employs one L-fold interleaved error correction code to provide data reliability and increased endurance and to enable the recovery of data from failed integrated circuits; and one or more spare integrated circuits selectively coupled to one or more of the plurality of channels when one or more of the plurality of integrated circuits coupled thereto fails, the controller storing the recovered data from the failed integrated circuits in at least one spare integrated circuit in response to selecting the one or more spare integrated circuits, wherein the plurality of integrated circuits are organized in a plurality of groups, each of the plurality of groups having one or more of the plurality of integrated circuits each having a plurality of pages comprising fragments of one or more codewords, the plurality of pages from the plurality of integrated circuits form a plurality of large distributed pages, each of the plurality of large distributed pages includes one of the plurality of pages from each one of the plurality of integrated circuits, and wherein each codeword includes data symbols and parity symbols to recover data and to detect and correct errors.