Patent ID: 6239644
Filing Date: 2001-05-29
Classification: G06F,H03K,Y02D

Abstract:
For use with a synchronous bus having a clock line with a first quiescent level and a second active level and a data line, and with a bus device having higher and lower power-consuming states; a clock stretcher comprising first and second analog switches each having a control, said first analog switch controlled by said clock line, an output of the first analog switch being open when said clock line is at its first level and being at a predetermined level for a predetermined interval when said clock line is at its second level; said output of said first analog switch when at its predetermined level causing said bus device to transition from its lower-power-consuming-state to its higher-power-consuming state; said output of said first analog switch when at its predetermined level controlling said second analog switch to maintain said clock line to said second level; said bus device further characterized in having a control output, said control output operatively coupled with said second analog switch so that upon assertion thereof said second analog switch ceases maintaining said clock line to said second level.