Patent ID: 6829681
Filing Date: 2004-12-07
Classification: G06F

Abstract:
A catch system, comprising:a first bus; a second bus; a main memory having a memory section for storing data, said memory being operable to write data inputted from said first bus into said memory section and output data read from said memory section to said first bus; a cache memory; instruction means for outputting to said second bus a command for instruction to write back data of said cache memory into said memory; and a cache memory control section including a directory section for storing information regarding an address of said main memory of data stored in said cache memory and a reset terminal to which a first reset signal is inputted such that, when the first reset signal is asserted, at least an element of said cache memory control section which part in control of said first bus except said directory section is reset, said cache memory control section performing reading and writing of data between said main memory and said cache memory over said first bus, said cache memory control section performing write back processing of the data of said cache memory into said main memory in accordance with the command inputted over said second bus.