Patent ID: 6667643
Filing Date: 2003-12-23
Classification: H03L

Abstract:
A delay locked loop comprising:a delay unit for receiving an input clock signal, generating an output clock signal whose phase lags that of the input clock signal, and generating multiple delay signals having differently delayed phases in response to the input clock signal; a harmonic lock preventing unit for receiving the input clock signal and the multiple delay signals, outputting a 1st signal and a 2nd signal, comparing the phases of the input clock signal and the multiple delay signals, and generating the 1st signal or the 2nd signal depending on the comparison result; an electric charge pump for receiving the 1st signal and the 2nd signal, generating a phase control signal, and making the voltage of the phase control signal higher or lower than a pre-defined voltage in response to the 1st signal and the 2nd signal; a filter for eliminating AC included in the phase control signal and transmitting the filtered signal to the delay unit; and a start-up circuit for feeding a 1st voltage to the electric charge pump in the initial state before the output clock signal is generated and making the electric charge pump provide a 2nd voltage to the delay unit, wherein the delay unit adjusts the phases of the output clock signal and the multiple delay signals in response to the phase control voltage.