Patent ID: 8847282
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a device isolation region formed in the semiconductor substrate; a well, that has a first conductivity type, defined by the device isolation region; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film, the gate electrode including a first side surface and a second side surface facing the first side surface; and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface, wherein the semiconductor substrate includes a mesa structure located below the first side wall insulating film, the gate electrode and the second side wall insulating film, the mesa structure includes a first side surface and a second side surface, a first semiconductor layer, that has the second conductivity type and that forms a source region is formed outside of the first side surface of the mesa structure, with the first semiconductor layer being connected to the semiconductor substrate on the first side surface, a second semiconductor layer, that has second conductivity type and that forms a drain region is formed outside of the second side surface of the mesa structure, with the second semiconductor layer being connected to the semiconductor substrate on the second side surface, a first embedded insulating region, that includes a first insulating film, is formed beneath the first semiconductor layer; a second embedded insulating region, that includes the first insulating film, is formed beneath the second semiconductor layer, and a second insulating film is formed between the first embedded insulating region and the first side surface of the mesa structure; and a third insulating film is formed between the second embedded insulating region and the second side surface of the mesa structure.