Patent ID: 6504239
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A semiconductor device comprising:a base substrate which has four sides, a first major surface and a second major surface opposite to the first major surface; a semiconductor chip which is mounted on the first major surface and has an electrode formed thereon; a bonding pad which is formed on the first major surface; a wiring pattern which is formed on the first major surface and is connected to said bonding pad; a bonding wire which connects the electrode of said semiconductor chip to said bonding pad; a dummy pattern which is formed on the first major surface positioned between a center of one side of said base substrate and said semiconductor chip; and a sealing resin formed on and covering said semiconductor chip, said bonding wire, said bonding pad and a part of said dummy pattern, whereby a portion of said dummy pattern on said base substrate is exposed.