Patent ID: 6105109
Filing Date: 2000-08-15
Classification: G06F

Abstract:
A method which allows a code array of a computer processor system having an instruction unit, execution unit and buffer control element to be written while the system is in normal operation, and having an internal code array storage having a code array lookup mechanism having a range of line addresses specified in the code array's lookup mechanism and an area for storing writeable system subroutines associated with said buffer control element a memory and a bus coupling the said two areas to additional computer systems elements as part of a hierarchical memory system which has at least two levels of memory including a cache array level and said memory, the method providing the steps of:causing with write control code the computer system instruction unit to issue one normal operand fetch for a single dw (double word) for each line of said code array and causing data to be written into said code array; andwhen said write control code controls filling of the code array, said write control code sequentiallya) purges the cache array; and thenb) disables the code array; and thenc) turns on a fill mode with a buffer control element fill mode latch; and then the write control code processd) increments once through a range of line addresses, where the range is at least as wide as any range(s) specified in the code array's lookup mechanism; andthen said write control code:e) turns off fill mode; andf) purges the cache array again; and theng) enables the code array.