Patent ID: 8766699
Filing Date: 2014-07-01
Classification: H03K

Abstract:
1. A switching circuit comprising first to fourth semiconductor switch elements each having an input terminal, an output terminal, and a common terminal, an output terminal of the first semiconductor switch element and an output terminal of the third semiconductor switch element being connected to each other, a common terminal of the second semiconductor switch element and a common terminal of the fourth semiconductor switch element being connected to each other, a common terminal of the first semiconductor switch element and an output terminal of the second semiconductor switch element being connected to each other, a common terminal of the third semiconductor switch element and an output terminal of the fourth semiconductor switch element being connected to each other, and a pulse-like signal being applied to each input terminal of the first to fourth semiconductor switch elements such that the second and third semiconductor switch elements are in an OFF state when the first and fourth semiconductor switch elements are in an ON state and the second and third semiconductor switch elements are in an ON state when the first and fourth semiconductor switch elements are in an OFF state, further comprising a first capacitance element connected between the output terminal of the second semiconductor switch element and the input terminal of the fourth semiconductor switch element, a second capacitance element connected between the input terminal of the second semiconductor switch element and the output terminal of the fourth semiconductor switch element, a first capacitance suppression element section connected between the input terminal and the common terminal of the second semiconductor switch element, and a second capacitance suppression element section connected between the input terminal and the common terminal of the fourth semiconductor switch element, and wherein the first capacitance element has a capacitance to reduce a parasitic capacitance between the input terminal and the output terminal of the fourth semiconductor switch element to less than that obtained when the first capacitance element is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal supplied to the fourth semiconductor switch element, and the second capacitance element has a capacitance to reduce a parasitic capacitance between the input terminal and the output terminal of the second semiconductor switch element to less than that obtained when the second capacitance element is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal supplied to the second semiconductor switch element, the first capacitance suppression element section reduces a first capacitance between the input terminal and the common terminal of the second semiconductor switch element to less than that obtained when the first capacitance suppression element section is not connected, at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal, the first capacitance being two times greater than a parasite capacitance between the input terminal and the output terminal of the second semiconductor switch element, and the second capacitance suppression element section reduces a second capacitance between the input terminal and the common terminal of the fourth semiconductor switch element to less than that obtained when the second capacitance suppression element section is not connected, at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal, the second capacitance being two times greater than a parasite capacitance between the input terminal and the output terminal of the fourth semiconductor switch element.