Patent ID: 7042088
Filing Date: 2006-05-09
Classification: H01L,H05K,Y02P

Abstract:
1. A semiconductor packaging structure comprising: an electrical substrate having a top surface and a bottom surface; a semiconductor die overlaying said top surface; a printed circuit board underlying said bottom surface; a first array comprising a plurality of first solder joints and a plurality of second solder joints mounted on said die surface and projecting downwardly therefrom, said plurality of first solder joints having a higher melting point than said plurality of second solder joints; and a second array comprising a plurality of third solder joints mounted on said top surface, said second array being substantially aligned with said first array to thereby connect said die surface and said top surface, said plurality of third solder joints having a higher melting point than said plurality of second solder joints, said plurality of first solder joints being respectively contacting a corresponding portion of said plurality of third solder joints and said plurality of second solder joints being melted to be integrally joined to a remaining portion of said plurality of third solder joints, said plurality of second solder joints extending between a corresponding one of said remaining portion of said plurality of third solder joints and said die surface.