Patent ID: 7078303
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: preparing a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate; forming a gate electrode layer on the gate insulating layer; patterning the gate electrode layer to form a gate electrode pattern; forming an LDD region on the semiconductor substrate; depositing an oxide layer on the semiconductor substrate, wherein a thickness of the oxide layer is greater than a thickness of the gate insulating layer; forming a nitride layer on the oxide layer; and etching the oxide layer and the nitride layer to form a nitride sidewall spacer on a gate electrode through the oxide layer, wherein a final gate electrode structure includes a lower gate electrode layer and a top gate electrode layer, and wherein a height of the nitride sidewall spacer is substantially equal to or less than a total thickness of the gate electrode structure and more than a thickness of the lower gate electrode layer.