Patent ID: 7853638
Filing Date: 2010-12-14
Classification: G06F

Abstract:
1. A non-transitory computer readable storage medium storing a design structure for at least one of designing, manufacturing, and testing a design, the design structure comprising: a hypertransport switching data processing system comprising: at least two input/output (I/O) bridges, each providing a communications path for data driven to a corresponding peripheral device from the CPU; a flexibly configurable hypertransport switch comprising a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges; and, a basic I/O system (BIOS) configured to set the flexibly configurable hypertransport switch to one of the first configuration and the second configuration based upon detecting either a single CPU coupled to the BIOS or multiple CPUs coupled to the BIOS.