Patent ID: 8279660
Filing Date: 2012-10-02
Classification: G11C

Abstract:
1. Circuitry comprising: address register circuitry operable to generate a word line signal; a word line; a plurality of memory elements coupled to the word line, wherein the word line is operable to convey the word line signal to the plurality of memory elements and wherein each of the memory elements of the plurality of memory elements comprises a power supply terminal; and switching circuitry operable to selectively couple the power supply terminals of the plurality of memory elements to a first power supply line at a first voltage during memory read operations and to selectively couple the power supply terminals of the plurality of memory elements to a second power supply line at a second voltage during memory write operations, wherein the first voltage is different than the second voltage, wherein the switching circuitry comprises a first transistor and a second transistor in each memory element of the plurality of memory elements, and wherein, in each memory element of the plurality of memory elements, the first transistor of that memory element is: