Patent ID: 6207553
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises the sequential steps of:(a) providing a substrate comprising a semiconductor wafer with a surface having a dielectric layer fonned thereover, said dielectric layer comprising a surface including a first in-laid metallization pattern including a plurality of spaced-apait metal features forming electrical contacts, vias, interlevel metallization, and/or interconnect routing of at least one active device region or component of said semiconductor wafer substrate;(b) forming a layer of a preselected metal to a predetermined thickness over said surface of said dielectric layer and in ohmic contact with each of said plurality of spaced-apart metal features of said first in-laid metallization pattern said metal layer including a surface;(c) positioning a patterned exposure mask at a predetermined spacing from said surface of said metal layer, said mask comprising a predetermined pattern of openings formed therethrough, said mask openings being positioned in a predetermined registered relation with the features of said first in-laid metallization pattern;(d) establishing a gas atmosphere in the space between said surface of said metal layer and said patterned exposure mask, said gas atmosphere comprising at least one etchant material for photo-activated anisotropic etching of said metal layer;(e) irradiating the portions of said gas atmosphere exposed through said pattern of mask openings with radiation of predetermined wavelength(s) for effecting photo-activated, selective, anisotropic etching of the portions of said metal layer exposed through said pattern of mask openings; and(f) continuing said photo-activated selective anisotropic etching of step (e) for an interval sufficient to remove the entire thickness of said metal layer at said exposed portions, thereby forming a patterned metal layer having predetermined portions in overlying, ohmic contact with selected features of said first in-laid metallization pattern.