Patent ID: 7414453
Filing Date: 2008-08-19
Classification: H03K

Abstract:
1. A level conversion circuit for receiving an input signal having a first voltage and generating an output signal having a second voltage that is greater than the first voltage, the level conversion circuit comprising: a first NMOS transistor including a drain; a second NMOS transistor including a drain; a first PMOS transistor including a drain, a gate, and a source, the drain of the first PMOS transistor being connected to the drain of the first NMOS transistor, and the gate of the first PMOS transistor being connected to the drain of the second NMOS transistor; a second PMOS transistor including a drain, a gate, and a source, the gate of the second PMOS transistor being connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor being connected to the drain of the second NMOS transistor; a third PMOS transistor including a drain and a gate, the drain of the third PMOS transistor being connected to the source of the first PMOS transistor; a fourth PMOS transistor including a drain and a gate, the drain of the fourth PMOS transistor being connected to the source of the second PMOS transistor; and a bias circuit connected to the gates of the third and fourth PMOS transistors, the bias circuit generating a bias potential that is supplied to the gates of the third and fourth PMOS transistors so that currents flowing to the third and fourth PMOS transistors are respectively proportional to currents flowing to the first and second NMOS transistors and at least the current flowing to the second NMOS transistor is larger than the current flowing to the second PMOS transistor when the first voltage decreases.