Patent ID: 6181176
Filing Date: 2001-01-30
Classification: H03K

Abstract:
An output buffer circuit comprising:a first circuit which inputs an input signal and produces at an output terminal of said first circuit a first signal by adjusting a slew rate of said input signal;a first transistor which includes a control terminal which inputs said input signal, a first terminal connected to a first power supply terminal and a second terminal;a first delay element which includes an input terminal which inputs said input signal and an output terminal which delays said input signal and outputs a first delayed signal;a second transistor which includes a control terminal which inputs said first delayed signal, a first terminal connected to said second terminal of said first transistor and a second terminal connected to an output terminal of said first circuit;a third transistor which includes a control terminal which inputs said input signal, a first terminal connected to a second power supply terminal and a second terminal;a second delay element which includes an input terminal which inputs said input signal and an output terminal which delays said input signal and outputs a second delayed signal;a fourth transistor which includes a control terminal which inputs said second delayed signal, a first terminal connected to said second terminal of said third transistor and a second terminal connected to the output terminal of said first circuit; andan output transistor which includes a control terminal which is connected to said output terminal of said first circuit and a terminal connected to a transfer path.