Patent ID: 7892908
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: providing a substrate comprised of silicon having a first crystal lattice orientation; forming a layer of directly bonded silicon (DSB) having a second crystal lattice orientation to a top surface of said substrate; forming regions of shallow trench isolation (STI) field oxide in said DSB layer extending into said substrate; forming a hard mask layer on a top surface of said DSB layer to define a first region for a first type of MOS transistor, whereby: removing said DSB layer in said first region by etching processes to expose a top surface of said substrate; forming a selective epitaxial growth (SEG) layer of silicon having said first crystal lattice orientation on said top surface of said substrate in said first region by selective epitaxial growth, in a manner that forms substantially no silicon on a top surface of said hard mask layer or said field oxide; forming a first type of well in said SEG layer and said substrate in said first region by ion implanting a first type of dopants; forming a second type of well in a second region in said DSB layer and said substrate that is different than said first region by ion implanting a second type of dopants; forming a first type of MOS transistor on and in said first type of well; forming a second type of MOS transistor in said second type of well; forming a pre-metal dielectric (PMD liner on top surfaces of said first type of MOS transistor, said second type of MOS transistor and said field oxide region; forming a PMD layer on a top surface of said PMD liner; and forming contacts in said PMD layer and said PMD liner to make electrical connections to said first type of MOS transistor and said second type of MOS transistor.