Patent ID: 8837223
Filing Date: 2014-09-16
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array in which a plurality of NAND cell units are arranged in a second direction intersecting a first direction, the NAND cell units including a plurality of memory cells connected in series in the first direction, source line side select gate transistors which are connected between the plurality of memory cells and the source line, and bit line side select gate transistors which are connected between the plurality of memory cells and the bit line, the memory cell including a semiconductor layer, a gate insulating film formed on the semiconductor layer, a charge accumulation layer formed on the gate insulating film, and a control gate which extends in the second direction and which faces the charge accumulation layer via an inter-gate insulating film; and a control circuit for writing data to the memory cell in units of pages, the plurality of memory cells being arranged in the second direction as a page, during write operation to the plurality of memory cells in units of pages, the control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and write data to a memory cell adjacent to each of the memory cells in a page to be written.