Patent ID: 6226223
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A semiconductor memory device comprising a plurality of memory cells, each said memory cell including a charge storage device and first and second transfer devices, the first transfer device being driven by a first word line and connected between the charge storage device and a first data input/output line for transferring charge, the second transfer device being driven by a second word line and connected between the charge storage device and a second data input/output line for transferring charge,wherein the memory device further includes a clock generator for generating first and second mutually complementary clock signals,wherein the clock generator includes control means for suspending the level changes of the first and second clock signals, and for making the first and second signals change into respectively predetermined levels when these signals start changing their levels, andwherein in response to the first and second clock signals, one of the first word lines and one of the second word lines are activated alternately, andwherein the clock generator adaptively changes levels of the first and second clock signals based on a level change of an external reference clock signal.