Patent ID: 6489210
Filing Date: 2002-12-03
Classification: H01L

Abstract:
In forming a gate electrode of embedded DRAM in which DRAM and a logic circuit are on a single chip, a method for forming a dual gate of a semiconductor device comprising the steps of:dividing a semiconductor substrate into a DRAM region and a logic circuit region, and forming a P well region and an N well region in the DRAM region; sequentially forming a gate insulating film, an undoped polysilicon layer, and a low resistance metal layer on the semiconductor substrate; forming first and second gate patterns in the DRAM region and a third gate pattern in the logic circuit region by etching; forming sidewall spacers at sides of each of the first, second and third gate patterns; masking the N well region and second gate pattern, and implanting N-type impurity ions into a surface of the semiconductor substrate thereby doping the undoped polysilicon layer of the first and third gate patterns and forming a first source/drain region; exposing the N well region and second gate pattern; masking the P well region and the first and third gate patterns, and implanting P-type impurity ions into the surface of the semiconductor substrate thereby doping the undoped polysilicon layer of the second gate pattern and forcing a second source/drain region; forming source and drain impurity regions in the semiconductor substrate at sides of the gate patterns by diffusing the impurity ions implanted into the first and second source/drain regions; and masking the DRAM region; and forming a second metal layer of the same material as the low resistance metal layer over the third gate pattern and on the substrate at both sides of the third gate pattern.