Patent ID: 6274424
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method of forming a semiconductor structure, the method comprising the steps of:forming a first dielectric layer;forming a first opening in the first dielectric layer;depositing a first metallic layer in the first opening;planarizing the first metallic layer to form a first conductive plug in the first opening;forming a second dielectric layer over the first conductive plug;forming a second opening in the second dielectric layer, the second opening exposing a top portion of the first conductive plug;depositing a second metallic layer in the second opening;planarizing the second metallic layer to form a second conductive plug in the second opening;forming a third dielectric layer over the second conductive plug;forming a third opening in the third dielectric layer, the third opening exposing a top portion of the second conductive plug;depositing a third metallic layer in the third opening;planarizing the third metallic layer to form a third conductive plug in the third opening; andwherein the first, second, and third conductive plugs collectively form a DRAM storage node between a current electrode of a transistor and a DRAM capacitor dielectric.