Patent ID: 6094432
Filing Date: 2000-07-25
Classification: H04L

Abstract:
An apparatus for segmentation and reassembly of constant bit rate traffic in an asynchronous transfer mode (ATM) network comprising:an ATM cell generating unit for reading a value included in an external T1/E1 frame and generating an ATM cell based on the read value; anda T1/E1 frame generating unit for reading an external ATM cell and generating a T1/E1 frame based on the read ATM cell, wherein the ATM cell generating unit comprises:a state timing generation block for externally receiving clock signals (8K, N*8K and CLK), thereby configuring a finite state machine and a plurality of counters;a serial to parallel converter for externally receiving clock signals (N*8K and N*8*8K) and receiving serial data from a T1/E1 transceiver, the serial to parallel converter serving to convert the received serial data into 8-bit parallel data;a time-slot data to cell block for reading the parallel data from the serial to parallel converter in sync with the clock signal (N*8K) applied thereto via the state timing generation block, extracting time/slot data of the input T1/E1 frame, determining whether or not the extracted data should be discarded, based on control information read from transmit cell buffers, recording the extracted data in an associated transmit cell buffer where the extracted data is effective, and recording an associated cell buffer identification in a complete cell queue when ATM cells are completely accumulated in the associated transmit cell buffer;a transmit cell control block for searching the complete cell queue in response to a signal indicative of the status of the finite state machine configured by the state timing generation block, thereby recording ATM cells (CELL.sub.-- WR and CELL.sub.-- DATA) of the associated transmit cell buffer in an external cell buffer;a CPU access block for controlling a CPU and transmit cell buffer access in response to the signal indicative of the status of the finite state machine configured by the state timing generation block, thereby receiving signals (CPU.sub.-- CS, CPU.sub.-- RW and CPU.sub.-- ADDR) from associated CPU's while exchanging CPU data (CPU.sub.-- DATA) with the associated CPU's; anda transmit cell buffer access block for controlling a transmit cell buffer access among the time-slot data to cell block, transmit cell control block and CPU access block in accordance with the signal indicative of the status of the finite state machine configured by the state timing generation block, thereby applying transmit cell buffer signals (TCB.sub.-- CS, TCB.sub.-- RW and TCB.sub.-- ADDR) to the transmit cell buffer while exchanging transmit cell buffer data (TCB.sub.-- DATA) with the transmit cell buffer.