Patent ID: 6441431
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, said transistor comprising:a well region formed in said semiconductor substrate, said well region of a second conductivity type opposite that of the first conductivity type; a source region formed in said well region in said semiconductor substrate, said source region of said first conductivity type, said source region spaced from an edge of said well region by a portion of said well having a first distance; a drain region formed in said semiconductor substrate and spaced away from said source region by a channel region, and spaced from said well region by a portion of said semiconductor substrate having a second distance, said drain region of said first conductivity type; a conductive gate electrode disposed over said semiconductor substrate and over said channel region, the conductive gate extending over the entire portion of said well having a first distance and the entire portion of said semiconductor substrate having a second distance; a gate insulating layer disposed between said conductive gate electrode and said semiconductor substrate and having a length, said gate insulating layer comprising: a first portion of said gate insulating layer which has a first length and a first thickness; a second portion of said gate insulating layer which has a second length and a second thickness which is substantially thicker than said first thickness, the sum of said first length and said second length equaling the length of said gate insulating layer; and wherein said first portion of said gate insulating layer being situated proximate to said source region and spaced away from said drain region by said second portion of said gate insulating layer; and said well region extends at least from source region towards said drain region so as to completely underlie said first portion of said gate insulating layer and to underlie at least said second portion of said gate insulating layer.