Patent ID: 7126554
Filing Date: 2006-10-24
Classification: H01Q

Abstract:
1. A clock distribution system, comprising: a semiconductor substrate; a first longitudinal conducting plate; a second longitudinal conducting plate, wherein at least one dielectric layer separates the first longitudinal metal plate from the semiconductor substrate and at least one dielectric layer separates the first and second longitudinal metal plates; a first plurality of conducting vias extending from a first side of the first longitudinal conducting plate to a first side of the second longitudinal conducting plate; a second plurality of conducting vias extending from a second side of the first longitudinal conducting plate to a second side of the second longitudinal conducting plate, wherein the combination of the first and second longitudinal conducting plates and the first and second conducting vias forms a rectangular waveguide; a master clock source configured to transmit a global clock through the rectangular waveguide; and a local clock source configured to receive the global clock from the rectangular waveguide and to synchronize a local clock to the received global clock.