Patent ID: 6259393
Filing Date: 2001-07-10
Classification: H03M

Abstract:
A semiconductor integrated circuit comprising:signal amplifying means capable of switching a gain to 1 or 2;arithmetic processing means connected to an input side of the signal amplifying means, said arithmetic processing means carrying out a subtraction process of a reference voltage from a signal input thereto to output a result of the subtraction process, or outputting the signal input thereto without performing the subtraction process;changeover means having one changeover terminal connected to a signal input terminal and having another changeover terminal connected to an output side of sample hold means, and having a common terminal of connected to an input side of said arithmetic processing means;a comparator connected to an output side of said signal amplifying means, said comparator comparing an output from said signal amplifying means with the reference voltage to binarize the output; andswitch means connecting the output side of said signal amplifying means to an input side of said sample hold means;wherein said arithmetic processing means carries out a changeover, based on an output from said comparator, so that the subtraction of the reference voltage from the signal input is performed to output the result when the output from said signal amplifying means is larger than the reference voltage, and the signal input is outputted without performing the subtraction when the output from said signal amplifying means is not larger than the reference voltage, andsaid signal amplifying means amplifies twice the signal resulting from the subtraction of the signal outputted without the subtraction, when the signal inputted into said comparator is not greater than the reference voltage.