Patent ID: 7833859
Filing Date: 2010-11-16
Classification: H01L

Abstract:
1. A method for simultaneously manufacturing semiconductor devices, comprising: forming an isolation layer on a wafer to separate a low-voltage device region and a high-voltage device region from each other; sequentially forming a gate oxide layer and a lower gate poly on a first low-voltage transistor region of the low-voltage device region; forming a first poly oxide layer on a surface of the wafer; forming a nitride layer on the first poly oxide layer; etching the nitride layer and the first poly oxide layer to partially remove the nitride layer and the first poly oxide layer from the high-voltage device region; forming a field oxide layer by selectively oxidizing portions of the high-voltage device region exposed by the etching; forming a second poly oxide layer on a whole surface of the wafer; completing gate patterns of each transistor region by vapor-depositing an upper gate poly on a high-voltage transistor region of the high-voltage device region, the first low-voltage transistor region, and a second low-voltage transistor region of the low-voltage device region; and forming a source and drain region on the wafers of the high-voltage transistor region and the first and the second low-voltage transistor regions.