Patent ID: 6604276
Filing Date: 2003-08-12
Classification: H01C,Y10T

Abstract:
A method for fabricating a chip-type varistor having a glass coating layer, the chip-type varistor fabrication method comprising the steps of:(a) providing a varistor chip with a number of conductive pattern layers stacked between upper and lower portions of a ceramic body, the conductive pattern layers being spaced by a predetermined distance, and stackwise alternating ones of the conductive pattern layers being laterally withdrawn from alternating ends of the ceramic body to respectively form first and second inner electrodes; (b) etching outer surfaces of the ceramic body with a weak acid solution; (c) forming a first outer electrode at each end of the varistor chip so as to be electrically connected to the first and second inner electrodes, respectively; (d) forming a polymeric mask on an outer end of each of the first outer electrodes for preventing glass from penetrating into the first and second inner electrodes, respectively; (e) dipping each of the first outer electrodes into a glass-added paste; (f) forming a uniform glass coating layer by flowing the glass included in the glass-added paste from the dipped first outer electrodes directly onto the surface of the ceramic body by a thermal treatment, the thermal treatment being one of sufficient heat to perform the glass flowing and to simultaneously remove a face portion of the polymeric mask so as to expose the first outer electrodes; and (g) forming a second outer electrode surrounding a corresponding one of the first outer electrodes, at each end of the chip.