Patent ID: 8368198
Filing Date: 2013-02-05
Classification: H01L

Abstract:
1. A stacked package of a semiconductor device, comprising: at least one first semiconductor chip configured to perform a first function, the at least one first semiconductor chip including a first plurality of bonding pads; at least one second semiconductor chip configured to perform a second function, the at least one second semiconductor chip being arranged under the at least one first semiconductor chip and including a second plurality of bonding pads; at least one interposer lead between the at least one first semiconductor chip and the at least one second semiconductor chip; a third semiconductor chip configured to perform a third function which is different from the first and the second functions, the third semiconductor chip being arranged on the first semiconductor chip and including a third plurality of bonding pads; external connection leads configured to electrically connect the third plurality of bonding pads to an outside; and a wire bonding unit electrically connecting the at least one first semiconductor chip, the at least one second semiconductor chip, the third semiconductor chip, the at least one interposer lead, and the external connection leads to each other, wherein the at least one interposer lead is configured to provide an electrical connection media between the at least one first semiconductor chip and the at least one second semiconductor chip, wherein each of the at least one first semiconductor chip, the at least one second semiconductor chip, and the at least one interposer lead is provided in plurality, and the first semiconductor chips and the second semiconductor chips are stacked in an off-set stair type and the interposer leads are electrically separated from each other.