Patent ID: 6541847
Filing Date: 2003-04-01
Classification: H01L

Abstract:
An electrical structure, comprising:a circuitized substrate comprising a dielectric material and at least one metal layer; a first stiffener coupled to a first surface of the substrate, wherein the first stiffener includes a first stiffener material; a second stiffener coupled to a second surface of the substrate, wherein the second stiffener includes a second stiffener material; a semiconductor memory chip; and N semiconductor logic chips such that N is at least 2, wherein each logic chip is electrically coupled to the memory chip by a direct interconnect path that includes a corresponding conductive member, wherein the corresponding conductive member is in electrical and mechanical contact with both an electrically conductive pad on a surface of the corresponding logic chip and a corresponding electrically conductive pad on a surface of the memory chip, wherein at least one chip selected from the group consisting of the memory chip, a first logic chip of the N logic chips, a second logic chip of the N logic chips, . . . , a Nth logic chip of the N logic chips, and combinations thereof, is electrically coupled to the substrate by corresponding solder interconnects, and wherein each solder interconnect of the corresponding solder interconnects is in electrical and mechanical contact with both an electrically conductive pad on a surface of the substrate and an electrically conductive pad on a surface of the corresponding chip of the at least one chip.