Patent ID: 7126857
Filing Date: 2006-10-24
Classification: G06K,G11B,G11C

Abstract:
1. A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising: a solid state non-volatile memory array; a controller that transfers data between a host system and the solid state non-volatile memory array; a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller; and a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of an anomaly in the power signal by causing a busy signal to be asserted to the host system, to thereby block the host system from performing write operations to the memory subsystem during presence of the anomaly; wherein the memory subsystem is configured for pluggable attachment to the host system.