Patent ID: 7816963
Filing Date: 2010-10-19
Classification: H03K,H03L,H04L

Abstract:
1. A clock synchronizer, comprising: a first adjustable delay unit delaying a common clock by a first delay amount; a second adjustable delay unit delaying the common clock by a second delay amount; propagation paths comprising a path which propagates output of the first adjustable delay unit and a path which propagates output of the second adjustable delay unit; feedback paths comprising a first path which feeds back the propagated output of the first adjustable delay unit and a second path which feeds back the propagated output of the second adjustable delay unit, the first path and the second path having an equal delay amount; a difference signal generating unit generating a difference signal obtained by comparing a phase difference between the propagated output of the first adjustable delay unit and a fed back output of the second adjustable delay unit with a phase difference between the propagated output of the second adjustable delay unit and a fed back output of the first adjustable delay unit; and a control unit controlling the first delay amount and the second delay amount to decrease the difference signal.