Patent ID: 7346759
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. A decoder interface for a processor and a coprocessor, the coprocessor instantiated using configurable logic of a programmable logic device, the decoder interface comprising: an input instruction register for storing an input instruction from the processor; configuration instruction registers for storing instructions; and comparison/pointer logic coupled to the input instruction register and the configuration instruction registers, the comparison/pointer logic configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, the comparison/pointer logic configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having an instruction of the instructions matching the input instruction, each of the instructions capable of being executed by the coprocessor without reconfiguration thereof, the pointer having fewer bits than the input instruction; wherein the pointer instead of the input instruction is provided to the coprocessor for decoding to execute the input instruction; and wherein the pointer is encoded in a one-hot format.