Patent ID: 8013421
Filing Date: 2011-09-06
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; an electrical fuse formed on said substrate, having a first interconnect and a second interconnect, respectively formed in different layers, and a via provided in a layer between said first interconnect and said second interconnect, the via being connected to one end of said second interconnect and connected also to said first interconnect; and a guard interconnect portion formed in the same layer with said second interconnect, so as to surround said one end of said second interconnect, wherein, in a plan view, said second interconnect is formed so as to extend from the other end towards said one end, and said guard interconnect portion is formed so as to surround said one end of said second interconnect in three directions, while placing said one end at the center thereof, and wherein a site of disconnection is formed in said via when said electrical fuse is blown.