Patent ID: 7488654
Filing Date: 2009-02-10
Classification: H01L

Abstract:
1. A method of forming FinFETs on a semiconductor substrate comprising: providing a hard mask pattern of a first hard mask material on the substrate to define a plurality of active regions; forming a plurality of active regions separated by a field insulating material, wherein the active regions are arranged along a plurality of parallel longitudinal axes with the active regions arranged along a single longitudinal axis being offset in a longitudinal direction relative to active regions arranged along an adjacent longitudinal axis, wherein each of the active regions arranged along a single longitudinal axis is separated from adjacent active regions by a specific field insulating region and wherein each active region arranged along a first longitudinal axis is separated from adjacent active regions arranged along an adjacent longitudinal axis by a lateral field insulating region; forming a pattern that exposes the specific field insulating regions; removing field insulating material from the exposed specific field insulating regions to form openings in the field insulating material; removing the pattern; depositing a second hard mask material layer to fill the openings; removing an upper portion of the second hard mask material to planarize the surface and expose an upper surface of the lateral field insulating regions; forming a damascene pattern at an angle from 10 to 90 degrees to the parallel longitudinal axes to expose portions of the lateral field insulating regions; removing a partial thickness of the field insulating material from the exposed portions of the lateral field insulating regions to form recessed openings separated by remaining portions of the lateral field insulating regions; removing the damascene pattern; removing the first and second hard mask materials to expose three field insulating material surfaces including forming a gate dielectric on an exposed surface of the active regions; depositing a gate electrode material layer; and patterning and etching the gate electrode material to form gate electrodes.