Patent ID: 7064971
Filing Date: 2006-06-20
Classification: G11C

Abstract:
1. A content addressable memory (CAM) cell comprising: four transistors configured as a back-to-back inverter for forming a bi-stable memory having a first and a second memory nodes for storing a pair of stored complimentary binary bits; a fifth transistor connected to said first memory node and a conductive line connected to said second memory nodes for receiving a pair of input complimentary binary bits therefrom; and an exclusive OR logic circuit comprising four transistors connected to said back-to-back inverter for comparing said input complimentary binary bits with said pair of stored complimentary binary bits for generating a match-mismatch signal; and a gate of said fifth transistor further connected to a wordline driver for controlling different read and write relative wordline voltages for carrying out a single-bit-line-write (SBLW) operation for writing said pair of complimentary binary bits to said first and second memory nodes.