Patent ID: 9100653
Filing Date: 2015-08-04
Classification: H04N

Abstract:
1. A memory transfer controller, comprising: a first bus request module configured to transfer video line data to or from a video pre-processor; a second bus request module configured to transfer macroblock data to or from a video encoder; and a processor configured to control data transfers by the first bus request module and the second bus request module, wherein a size of a unit of the video line data is larger than a size of a unit of the macroblock data and transfers of the macroblock data is effected in a first time period, wherein the memory transfer controller is adapted to divide the video line data into two or more portions for transfer of each of said portions in respective ones of said first time period, and wherein the memory transfer controller is configured to temporally align a transfer of at least some of said portions of the divided video line data and at least some of the macroblock data to a start of the first time period.