Patent ID: 8867301
Filing Date: 2014-10-21
Classification: G11C

Abstract:
1. A semiconductor device comprising: a command decoder generating a first internal command in response to a first internal clock signal; and a latency counter that includes: a gate control signal generation unit generating a plurality of output gate signals in response to a second internal clock signal that is different from the first internal clock signal; a plurality of delay circuits each receiving an associated one of the output gate signals and generating an associated one of a plurality of input gate signals, each of the delay circuits including a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage, the first power supply voltage being different from the second power supply voltage; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command as a second internal command in response to one of the output gate signals.