Patent ID: 9147465
Filing Date: 2015-09-29
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a sense amplifier connected between a first bit line and a second bit line, and configured to amplify a voltage difference between a first bit line and a second bit line during a first operation mode of the semiconductor memory device; a source driver connected between a source node of the sense amplifier and a sense amplifier driving signal line, and configured to provide a first voltage to the source node of the sense amplifier during the first operation mode; a control circuit connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, and configured to control a voltage level of the sense amplifier driving signal line in response to a voltage level of the source node of the sense amplifier during a second operation mode of the semiconductor memory device different from the first operation mode; and a buffer circuit configured to float the sense amplifier driving signal line during the second operation mode of the semiconductor memory device.