Patent ID: 6084455
Filing Date: 2000-07-04
Classification: H03K

Abstract:
A CMOS latch, comprising:a first pair of transistors and second pair of transistors, each of the pairs of transistors including one respective transistor of one conductivity type and another respective transistor of another conductivity type that is opposite to the one conductivity type, each respective pair of transistors being connected to each other at a respective storage node having a respective logic level, the respective transistors of the one conductivity type also being connected to a first logic level, the respective transistors of the another conductivity type also being connected to a second logic level that is complementary to the first logic level, each of the respective gates of the respective transistors of the one conductivity type in each respective pair of transistors being connected to a respective dynamic node of a pair of dynamic nodes, each of the respective gates of the respective transistors of the another conductivity type in each respective pair of transistors being connected to the other respective dynamic node of the pair of dynamic nodes via a respective inverter.