Patent ID: 7562272
Filing Date: 2009-07-14
Classification: H03L

Abstract:
1. A circuit, comprising: a phase-locked loop (PLL) circuit; an electrical fuse (eFuse) array coupled to the PLL circuit; a control unit coupled to the eFuse array, wherein the control unit comprises: a latch coupled to the control unit, wherein the sensed data from the eFuses in the eFuse array are provided to the latch, and wherein the latch provides the sensed data to the PLL circuit; a decoder coupled to the PLL circuit and the latch, and wherein a portion of the sensed data from the eFuses is provided to the decoder which decodes the portion of the sensed data to thereby generate decoded data, and wherein the decoder provides the decoded data to the PLL circuit; a scan latch coupled to the latch and the eFuse array, wherein the scan latch scans- in the sensed data from the eFuse array and provides the sensed data to the latch in response to the latch receiving a control signal from the POR engine; and a clock select multiplexer having a first input for receiving a reference clock and a second input for receiving an output from the PLL circuit, wherein: