Patent ID: 6023079
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A compound semiconductor memory comprising:a substrate;a first semiconductor layer formed on said substrate, a channel being formed by said first semiconductor layer;a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer;a third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer;a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer;a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel;a source electrode electrically connected to said channel; anda drain electrode electrically connected to said channel, said gate electrode being located between said source electrode and said drain electrode;wherein said first semiconductor layer is formed of GaAs, said second semiconductor layer is formed of Al.sub.0.25 Ga.sub.0.75 As, said third semiconductor layer is formed of In.sub.0.25 Ga.sub.0.75 As and said fourth semiconductor layer is formed of Al.sub.0.5 Ga.sub.0.5 As.