Patent ID: 6662351
Filing Date: 2003-12-09
Classification: G06F

Abstract:
A wiring editing method for a semiconductor package, using a CAD system, arranging pads connected to a semiconductor chip, and vias around said pads, on a virtual plane, drawing a wiring pattern for connection said pads and said vias and correcting an offset of said wiring pattern passing between said parts vias, comprising the steps of:assuming virtual circular arcs, by considering a clearance around a predetermined one of said vias, inside a designated area on said virtual plane; drawing a regular polygon circumscribing each of said virtual circular arcs; and when said virtual circular arcs cross any of the vias, drawing a tangent from the crossed via to said crossing virtual circular arc and connecting said regular polygon circumscribing said crossing circular arc to form a wiring patterns; and executing correction, inclusive of movement or omission line segments forming said regular polygon among said wiring pattern, to thereby change a wiring route when an offset occurs in said wiring pattern passing between said vias inside said designated area.