Patent ID: 6175906
Filing Date: 2001-01-16
Classification: G06F

Abstract:
An apparatus comprising:a translation lookaside buffer (TLB) configured to store virtual to physical address translations;a cache having a plurality of entries, each entry capable of storing a data block; anda cache controller coupled to said translation lookaside buffer and said cache, wherein said cache controller is further coupled to receive a virtual request address, said cache controller including:a virtual tag storage configured to store virtual tags, wherein each virtual tag is associated with one of said plurality of entries in said cache, and wherein said virtual tag represents a virtual address of said data block stored in said one of said plurality of entries;a physical tag storage configured to store physical tags, wherein each physical tag is associated with one of said plurality of entries in said cache, and wherein said physical tag represents a physical address of said data block stored in said one of said plurality of entries;a valid storage configured to store current valid bits and previous valid bits, wherein each of said current valid bits indicates that an associated virtual tag in said virtual tag storage is currently valid, and wherein each of said previous valid bits indicates that an associated virtual tag was valid during a previous validation cycle, and wherein a hit is detected in said cache and said data block associated with said a first virtual tag in said virtual tag storage and stored in said cache is used to satisfy a request if said first virtual tag matches said virtual request address and a first current valid bit corresponding to said first virtual tag is set, and wherein each of said current valid bits is reset at a start of a current validation cycle, and wherein a start of said current validation cycle corresponds to a remapping of one or more virtual pages to one or more physical pages;a recovery register configured to store a virtual page number of a recovered data block, wherein a virtual address corresponding to said recovered data block has been translated in said TLB during said current validation cycle; anda valid circuit coupled to said virtual tag storage, said physical tag storage, said valid storage and said recovery register, wherein said valid circuit is configured to assert a second current valid bit associated with a second virtual tag in said virtual tag storage and to inhibit access to said TLB to verify a virtual to physical address translation corresponding to said second virtual tag in response to: (i) access of a data block associated with said second virtual tag in said cache during said current validation cycle, (ii) a page number of said second virtual tag matching said virtual page number stored in said recovery register, and (iii) a second previous valid bit associated with said second virtual tag indicating said virtual tag was valid during said previous validation cycle.