Patent ID: 6529033
Filing Date: 2003-03-04
Classification: G01R,G06F

Abstract:
An integrated circuit comprising:a first plurality of clocked circuits, each clocked circuit of the first plurality including a first data input terminal and a first clock. terminal connected to receive a clot signal; a second plurality of clocked circuits, each clocked circuit of the second plurality including a second data input terminal, and a second clock terminal; and a clock signal inverting circuit including a first input terminal connected to receive a clock signal, a second input terminal connected to receive a mode control signal, and an output signal connected to the second clock terminals of each clocked circuit of the second plurality, wherein one of the first plurality and second plurality are rising edge-triggered circuits, and the other of the first plurality and second plurality are falling edge-triggered circuits, and wherein the clock signal inverting circuit passes the clock signal only to the second plurality of clocked circuits when the mode control signal is in a first state, and inverts the clock signal passed only to the second plurality of clocked circuits when the mode control signal is in a second state.