Patent ID: 8036023
Filing Date: 2011-10-11
Classification: G11C

Abstract:
1. A memory cell disposed in a substrate, comprising: first and second output nodes; a first P-type transistor having a first conduction node connected to a first reference voltage, a control node connected to said first output node, and a second conduction node connected to said second output node; a second P-type transistor having a first conduction node connected to said first reference voltage, a control node connected to said second output node, and a second conduction node connected to said first output node; first and second N-type transistors connected in series between the first output node and a second reference voltage, each of said first and second N-type transistors having a respective control node connected to said second output node; third and fourth N-type transistors connected in series between the second output node and said second reference voltage, each of said third and fourth N-type transistors having a respective control node connected to said first output node, wherein said first and third N-type transistors are physically formed at least two microns distant from each of said first and second P-type transistors and said second and fourth N-type transistors; and a first capacitive element coupled between said second reference voltage and the control nodes of at least the first, second and third N-type transistors.