Patent ID: 6060938
Filing Date: 2000-05-09
Classification: H03K

Abstract:
An output buffer having an input node and an output node, the buffer comprising:a. a pull-up transistor having a control node coupled to the input node, a high-potential node coupled to a high-potential power rail, and a low-potential node coupled to the output node;b. a pull-down transistor having a control node coupled to the input node, a high-potential node coupled to the output node, and a low-potential node coupled to a low-potential power rail;c. a first clamping sub-circuit including a first delay stage, a first diode device, and a first current regulator, wherein said first delay stage includes an input node coupled to the input node of the output buffer, and an output node coupled to a control node of said first current regulator, wherein said first diode device includes a low-potential node coupled to said control node of said pull-up transistor and a high-potential node coupled to a low-potential node of said first current regulator, and wherein said first current regulator includes a high-potential node coupled to said high-potential power rail; andd. a second clamping sub-circuit including a second delay stage, a second diode device, and a second current regulator, wherein said second delay stage includes an input node coupled to the input node of the output buffer, and an output node coupled to a control node of said second current regulator, wherein said second diode device includes a high-potential node coupled to said control node of said pull-down transistor and a low-potential node coupled to a high-potential node of said second current regulator, and wherein said second current regulator includes a low-potential node coupled to said low-potential power rail.