Patent ID: 6597615
Filing Date: 2003-07-22
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of operating modes, comprising:a memory cell array having dynamic memory cells; a refresh controller having a refresh timer for generating a refresh timing signal used to determine timing for performing refresh operations on the memory cell array, the refresh controller performing refresh operations on the memory cell array in response at least to the refresh timing signal; an operating mode input terminal for receiving from an external device an operating mode signal specifying one of the plurality of operating modes of the semiconductor memory device; and an external timing input terminal for receiving from the external device an external timing signal that is to be used together with the refresh timing signal when the refresh controller determines the timing for performing the refresh operations; wherein (i) in an event that the operating mode signal specifies a first operating mode of the plurality of operating modes the refresh controller performs a refresh operation according to a first refresh mode wherein the refresh operation in the first refresh mode on the memory cell array is initiated under timing determined by the external timing signal after the refresh timing signal has been generated; (ii) in an event that the operating mode signal specifies a second operating mode of the plurality of operating modes, the refresh controller performs a refresh operation according to a second refresh mode wherein the refresh operation in the second refresh mode on the memory cell array is initiated in response to generation of the refresh timing signal, regardless of the external timing signal; (iii) the memory cell array is divided into a plurality of blocks; and (iv) when the refresh operation in the first refresh mode is initiated and data is being read from or written to one block from among the plurality of blocks, the refresh controller performs the refresh operation on blocks other than the block from or to which the data is being read or written upon completion of the read or write operation on the block.