Patent ID: 6333202
Filing Date: 2001-12-25
Classification: H01L,Y10S

Abstract:
A method of fabricating an integrated FE/CMOS structure comprising the steps of:(a) forming a CMOS structure in electrical contact with a conductive electrode layer;(b) separately providing a ferroelectric delivery wafer, said ferroelectric delivery wafer comprising a sacrificial release layer formed on a delivery substrate, a conductive layer formed on said sacrificial release layer and a ferroelectric film formed on said conductive layer, said ferroelectric film having an exposed outer surface;(c) placing said exposed outer surface of said ferroelectric film on the CMOS structure of said step (a), wherein said ferroelectric film is in contact with said conductive electrode layer;(d) bonding, at a temperature of less than about 600.degree. C., the exposed outer surface of said ferroelectric film to said CMOS structure; and(e) separating the sacrificial release layer from the bonded structure.