Patent ID: 6060928
Filing Date: 2000-05-09
Classification: G11C

Abstract:
A device for delaying a clock signal comprising:a delay for delaying an external clock signal eCLK up to a delay d1+d2, wherein the delay d1 is a natural delay incurred on reception and the delay d2 is a natural delay incurred on driving an output buffer;a pulse generator for receiving a clock signal from the delay and generating pulse signals synchronous to rising edges;a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signals generated in the pulse generator as well as latching a signal from each unit delay synchronous to a clock signal rCLK received in the device wherein the clock signal rCLK is derived from the external clock signal eCLK plus the delay d1;a first clock signal delay for making a course delay of the clock signal rCLK corresponding to a number of circulation;a second clock signal delay for making a fine delay of the clock signal rCLK delayed by the course delay from the first clock signal delay in response to a latch signal from the ring delay; and,a reset signal generator for resetting the ring delay and the first, and second clock signal delays in response to the clock signal rCLK.