Patent ID: 6309923
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method of forming a capacitor with a self-align structure on a substrate, said substrate comprising two word lines and an active region, said method comprising the steps of:forming a first dielectric layer on said active region and said word line with a planar top surface;creating a contact hole in said first dielectric layer and said self-align structure to expose portions of said active region and said word line;forming a conductive layer on a bottom of said contact hole;forming a polysilicon spacer on a sidewall of said contact hole;forming a dielectric spacer on a sidewall of said polysilicon spacer;filling said contact hole with a polysilicon bar;creating three sub-contact holes by etching back said polysilicon spacer and said polysilicon bar with part of said polysilicon spacer and said polysilicon bar remaining on the bottom of said sub-contact holes;forming a hemispherical grain (HSG) layer on the surface of said sub-contact holes;depositing a second dielectric layer on said hemispherical grain; andforming a top electrode on said second dielectric layer.