Patent ID: 9122106
Filing Date: 2015-09-01
Classification: G02F,G09G,H04N

Abstract:
1. A display apparatus comprising: a display panel comprising a plurality of pixels connected to first gate lines, second gate lines, and data lines, each of the plurality of pixels connected to corresponding first and second gate lines of the first and second gate lines, respectively, each pixel comprising: a first sub-pixel comprising a first transistor connected to a corresponding first gate line of the first gate lines and a corresponding data line of the data lines, and a first pixel electrode connected to the first transistor; a second sub-pixel comprising a second transistor connected to a corresponding second gate line of the second gate lines and the corresponding data line of the data lines, and a second pixel electrode connected to the second transistor; and a third sub-pixel comprising a third transistor connected to the corresponding second gate line and the corresponding data line, a fourth transistor connected to the corresponding second gate line and configured to receive a storage voltage, and a third pixel electrode connected to the third and fourth transistors, wherein: at least the corresponding first gate line is disposed between the first and second pixel electrodes; and an area of the first pixel electrode is less than an area of the second pixel electrode and the area of the second pixel electrode is less than an area of the third pixel electrode.