Patent ID: 6232812
Filing Date: 2001-05-15
Classification: G11C,H03K,H03L

Abstract:
A programmable delay line, comprising:a delay circuit having an input and a plurality of outputs which each provide a respective delayed version of a periodic input signal provided to the input;a delay switch which passes one of the plurality of outputs of said delay circuit to an output thereof, in response to a digital control signal;a phase comparing circuit which compares the input signal against the delayed versions of the input signal at the plurality of outputs and generates a digital phase signal that identifies which of the delayed versions of the input signal is in-phase with the input signal;a pointer which generates the digital control signal in response to the digital phase signal and a plurality of pointer control signals and the input signal; anda first comparator which generates a first equivalence signal if the digital phase signal is equivalent to the digital control signal.