Patent ID: 8373275
Filing Date: 2013-02-12
Classification: H01L

Abstract:
1. A fine pitch solder bump structure for semiconductor chip package interconnects, comprising: a dielectric substrate having electrical connects arranged therein; an electrically conductive pad on said dielectric substrate in communication with said electrical connects, at least one solder bump having an electrically conductive via in electrical contact with said pad; a layer of a polyimide material extending about the via of said at least one solder bump, said polyimide material being of a height comprising a major portion of the height of said at least one solder bump; and a ball limiting metallurgy (BLM) layer between the layer of the polyimide material and the at least one solder bump, the BLM layer defining a perimeter of a trench filled by the via of the at least one solder bump wherein polyimide islands of the layer of the polyimide material are opposite the trench; wherein said layer of polyimide material has a thickness of about 50 μm, and wherein said at least one solder bump has a height extending to about 10-15 μm above the polyimide material layer measured from a top surface of the layer of polyimide material.