Patent ID: 8966320
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. A fault inspection unit provided for a central processing unit connected to a memory management unit, the memory management unit translating a physical address that is an address of a physical memory to a virtual address that is an address of a virtual memory and outputting a first signal indicating an illegal access if the physical memory is inaccessible with the physical address to which the virtual address is translated, the central processing unit outputting the virtual address to the memory management unit, allowing the first signal to be input, and terminating a program being executed if the first signal is input, the fault inspection unit comprising: a changing unit for changing an operating mode of the central processing unit to a test mode in which the central processing unit does not terminate a program being executed even if the memory management unit outputs the first signal; an output unit for outputting a second signal for causing the memory management unit to output the first signal to the memory management unit in the test mode; and a detecting unit for detecting whether or not the first signal is input after the output unit outputs the second signal to the memory management unit.