Patent ID: 6790781
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of:etching a first trench to a first level, into a conductively doped portion of a semiconductor assembly; etching a second trench to a second level, into said conductively doped portion of said semiconductor assembly, including second trench spanning said first trench, said step of etching a second trench simultaneously etching said first trench to a third level that corresponds to said second level; forming isolation material in said first and second trenches; forming first and second conductive wells having a common boundary but having opposite conductivity types within said conductively doped portion, said common boundary consisting of said first conductive well directly bordering said second conductive well, said isolation material interposed directly above said common boundary of said conductive wells.