Patent ID: 7612838
Filing Date: 2009-11-03
Classification: G02F

Abstract:
1. A method of manufacturing a thin film transistor array substrate, comprising: forming a gate pattern on a substrate, the gate pattern including a gate electrode of a thin film transistor and a gate line connected to the gate electrode; forming a gate insulating film on the substrate, covering the gate pattern; forming a source electrode and a drain electrode of the thin film transistor, a data line crossing the gate line to define a pixel region, a source/drain pattern including the data line, and a semiconductor pattern having an active layer overlapped with the source electrode, the drain electrode, and the data line and defining a channel between the source electrode and the drain electrode; forming a passivation film over the substrate having the thin film transistor; patterning the passivation film and the gate insulating film by an etching process using a photo-resist pattern to form passivation film pattern covering an area excluding an area having a transparent electrode pattern and to form at least one protrusion formed directly on the substrate, dividing the pixel region into a plurality of regions, each of the regions having a different liquid crystal alignment from the other regions; depositing a transparent electrode material over the substrate having the thin film transistor, the passivation film pattern and the photo-resist pattern; removing the photo-resist pattern and the transparent electrode material deposited thereon by a lift-off method to form the transparent electrode pattern, wherein the transparent electrode pattern is formed directly on the substrate and covers at least the pixel region; and forming a storage capacitor including the gate line and a storage electrode overlapping the gate line with the gate insulating film and the semiconductor pattern positioned therebetween, wherein forming the transparent electrode pattern includes forming a pixel electrode connected to the drain electrode and the storage electrode of the thin film transistor and covering the pixel region on the substrate excluding the passivation film pattern and the at least one protrusion, and wherein forming at least one protrusion includes forming a first protrusion and a second protrusion being substantially arranged in a first diagonal direction of the pixel region, and a third protrusion and a fourth protrusion being substantially arranged in a second direction crossing the first diagonal direction.