Patent ID: 7623392
Filing Date: 2009-11-24
Classification: G11C

Abstract:
1. A sense amplifier for use in a memory device having a plurality of complementary digit line pairs, the sense amplifier comprising: a pair of cross-coupled PMOS transistors having their drains coupled to respective digit lines in each pair of complementary digit lines and their sources coupled to a first supply voltage; a pair of cross-coupled NMOS transistors having their drains coupled to respective digit lines in each pair of complementary digit lines and their sources coupled to a second supply voltage; a respective source follower transistor coupling each of the digit lines to respective first and second output nodes; a first output transistor having its drain coupled to the first output node, its source connected to a supply voltage node, and its gate connected to the second output node; and a second output transistor having its drain coupled to the second output node, its source connected to the supply voltage node, and its gate connected to the first output node.