Patent ID: 6362974
Filing Date: 2002-03-26
Classification: G06F,H05K

Abstract:
A stacked processor construction apparatus, the stacked processor construction apparatus comprising:a first printed circuit board having a first local bus, the first local bus being comprised of conductive traces; a first processor mounted on the first printed circuit board, the first processor being electrically coupled to the first local bus; a second printed circuit board having a second local bus, the second local bus being comprised of conductive bus traces; a second processor mounted on the second printed circuit board, the second processor being electrically coupled to the second local bus; a first stacking device connected to the first and second printed circuit boards, the first stacking device separating the first and second printed circuit boards a predetermined distance from one another, the first stacking device maintaining the first and second printed circuit boards substantially in first and second planes, the first and second planes being substantially parallel to one another, the predetermined distance being at least great enough to prevent the first processor from being in contact with the second processor; and a first group of conductive elements, the conductive elements electrically coupling the first local bus to the second local bus to enable the first and second processors to communicate with each other.