Patent ID: 7436917
Filing Date: 2008-10-14
Classification: H04L

Abstract:
1. A synchronizer arrangement for effectuating data transfer between a first clock domain and a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising: a first synchronizer for transferring data from said first clock domain to said second clock domain and a second synchronizer for transferring data from said second clock domain to said first clock domain, said first synchronizer comprising first and second transmit circuits clocked by said first clock signal and a receive circuit clocked by said second clock signal, wherein when N/M>1, control signals configure said receive circuit to alternately receive data from said first transmit circuit and said second transmit circuit for output to said second clock domain and when N/M=1, said control signals configure said first transmit circuit to output data directly to said second clock domain; a first clock synchronizer controller portion operating to generate a set of first domain synchronizer control signals of said control signals towards said first and second synchronizers, said first clock synchronizer controller portion operating responsive to a set of clock relationship control signals; and a second clock synchronizer controller portion operating to generate said set of clock relationship control signals responsive to a SYNC pulse indicative of a coincident edge between an inverted first clock signal and said second clock signal, wherein at least a portion of said clock relationship control signals are used in generating a set of second domain synchronizer control signals towards said first and second synchronizers.