Patent ID: 7349231
Filing Date: 2008-03-25
Classification: G11C

Abstract:
1. A semiconductor memory device which includes a CAM portion capable of holding entry data, and can compare input comparison data with the entry data and can output a result of the comparison, wherein the CAM portion is divided into a plurality of blocks capable of comparing the comparison data with the entry data respectively, and each of the blocks is divided into a plurality of subblocks, the subblock including a latch circuit capable of sequentially transmitting the comparison data from a block positioned on one of end sides of the CAM portion toward a block positioned on the other end side of the CAM portion synchronously with a transmitted clock signal, and a control logic for fetching a result of a comparison of a bit of a former stage portion in the entry data with a corresponding bit of the comparison data and prohibiting a comparison of a bit of a latter stage portion in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched.