Patent ID: 8409957
Filing Date: 2013-04-02
Classification: H01L

Abstract:
1. A method for forming a three dimensional integrated circuit, the method including: forming a first source region, a first drain region, and a first gate stack portion on a substrate; forming a first dielectric layer over the first source region, the first drain region, the first gate stack portion and the substrate; forming a first conductive interconnect portion in the first dielectric layer the first conductive interconnect portion including vias; forming a second dielectric layer on the first dielectric layer; forming a second conductive interconnect portion in the second dielectric layer; forming a graphene layer on the second dielectric layer; removing portions of the graphene layer to expose portions of the second dielectric layer; forming a second source region on the second dielectric layer and a second drain region on the second dielectric layer; forming a third dielectric layer on the graphene layer; and forming a metallic gate material on the third dielectric layer.