Patent ID: 6359819
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A ferroelectric memory device, comprising:a memory array of memory cells organized into rows and columns, including a plurality of word lines, plate lines and bit lines, each row of memory cells being coupled to a word line and a plate line and each column of memory cells being coupled to a bit line, each memory cell comprising at least one ferroelectric capacitor and at least one transmission gate transistor connected thereto; address decode circuitry for receiving an address value and asserting a signal appearing on at least one row line to connect at least one row of memory cells to the column lines; and test circuitry for receiving at least one test control signal and in response to the at least one test control signal allowing a voltage differential to be applied between the column lines and the plate lines, so that a stress voltage may be applied across the at least one ferroelectric capacitor of the memory cells.