Patent ID: 6278868
Filing Date: 2001-08-21
Classification: H04J,H04L

Abstract:
A master transceiver circuit meant to be coupled by a telephone line to a slave transceiver circuit, the master circuit including a digital phase-locked loop for reconstructing a clock from an incoming bit flow, a phase difference between the reconstructed clock and an internal clock corresponding to the content of a phase counter of the phase-locked loop, including:a bit counter clocked by the internal clock, initialized upon transmission of a predetermined signal, and stopped upon detection of the return of the predetermined signal transmitted back by the slave transceiver circuit;means for calculating the delay introduced by the telephone line based on the contents of the phase and bit counters; anda FIFO-type memory, in which digital samples corresponding to the received bits are written at the rate of the reconstructed clock and in which the samples are read at the rate of the internal clock to be analyzed by the digital phase-locked loop;the detection of the return of the predetermined signal being performed downstream of the FIFO memory, the delay being corrected according to the difference between the read and write pointers of the FIFO memory.