Patent ID: 6261940
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A semiconductor processing method of making electrical connection between an electrically conductive line and a node location comprising:providing a substrate having an outer dielectric surface and a node location to which electrical connection is to be made;forming a first layer over the outer dielectric surface and the node location;forming a masking layer over the first layer and patterning the masking layer, to overlie a portion of the first layer laterally adjacent the node location and expose other portions of the first layer;forming a second layer over the first layer and the patterned masking layer and in electrical connection with the exposed portions of the first layer;after forming the second layer, patterning the first and second layers to form an electrically conductive line, the second layer of the line having a second layer terminus positioned over the patterned masking layer, the first layer of the line having an extension which extends laterally outward, relative to the second layer terminus, underlying the patterned masking layer to a first layer terminus adjacent the node location; andafter forming the electrically conductive line, electrically connecting the first layer extension, the second layer, and the node location with conductive material formed thereover, the conductive material formed into a silicide bridge for interconnecting the first layer extension, the second layer and the node.