Patent ID: 9118319
Filing Date: 2015-08-25
Classification: G01R,H03F,H03K,H03M,H04B,H04L,H04W

Abstract:
1. A reconfigurable circuit block, comprising: a rate-conversion circuit, configured to convert a first input signal with a first data rate into a first output signal with a second data rate that is different from the first data rate; a processing circuit, configured to perform a predetermined signal processing operation upon a second input signal to generate a second output signal; a first asynchronous interface circuit, configured to receive the first output signal, and output a third output signal asynchronous with the first output signal; a second asynchronous interface circuit, configured to receive the second output signal, and output a fourth output signal asynchronous with the second output signal; and a controllable interconnection circuit, coupled to the rate-conversion circuit, the processing circuit, the first asynchronous interface circuit, and the second asynchronous interface circuit, wherein the controllable interconnection circuit is configured to transmit the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmit the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.