Patent ID: 8674747
Filing Date: 2014-03-18
Classification: H03K,H04L

Abstract:
1. A semiconductor device comprising: first and second output terminals that are coupled with a load resistor, and output a differential signal; a variable resistor that is disposed between the first output terminal and the second output terminal, and has a resistance value thereof as a first resistance value in an emphasis mode, and as a second resistance value smaller than the first resistance value in a de-emphasis mode; a first driver that is disposed between a first supply terminal and the first output terminal, and has an output impedance thereof as a third resistance value in the emphasis mode, and as a fourth resistance value larger than the third resistance value in the de-emphasis mode; a second driver that is disposed between a second supply terminal and the second output terminal, and has an output impedance thereof as a fifth resistance value in the emphasis mode, and as a sixth resistance value larger than the fifth resistance value in the de-emphasis mode; and a controller that controls conductive states of the first and second drivers according to an input signal, and switches the output impedances of the first and second drivers and the resistance value of the variable resistor between the emphasis mode and the de-emphasis mode, wherein the first and second resistance values are set to values so that a ratio between a first differential resistance value that is a combined resistance of the first resistance value and the load resistor, and a second differential resistance value that is a combined resistance of the second resistance value and the load resistor, corresponds to a ratio between an amplitude of the differential signal in the emphasis mode and an amplitude of the differential signal in the de-emphasis mode, and wherein a difference between a first output resistance value indicative of a combined resistance of the third resistance value and the fifth resistance value, and a second output resistance value indicative of a combined resistance of the fourth resistance value and the sixth resistance value is set to a value corresponding to a difference between the first differential resistance value and the second differential resistance value.