Patent ID: 6127232
Filing Date: 2000-10-03
Classification: H01L,Y10S

Abstract:
A method of forming a MOS transistor structure comprising the acts of:supplying a silicon substrate;positioning a first layer of doped epitaxial silicon on the silicon substrate;positioning a layer of gate oxide on the doped epitaxial silicon layer;forming a disposable gate on the gate oxide, the disposable gate having sidewalls;forming sidewall spacers on the disposable gate extending outwardly over the gate oxide;removing the gate oxide from the epitaxial silicon layer except underneath the disposable gate;forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon;forming an interlayer dielectric over the second layer of epitaxial silicon and the gate;removing the dielectric from above the gate;removing the disposable gate to form a recess;removing the gate oxide layer to expose the first layer of doped epitaxial silicon, and undercut the sidewall spacers to form opposing laterally extending notch portions of the recess; anddepositing a permanent gate material in the recess and extending into the opposing laterally extended notches.