Patent ID: 9053284
Filing Date: 2015-06-09
Classification: G01N,G01P,G01R,G03F,G06F,G21K,H01L

Abstract:
1. A method for overlay monitoring and control, the method comprising: forming resist patterns on one or more wafers in a lot by an exposing tool; selecting a group of patterned wafers in the lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming, by a computer, an overlay correction map using the measured overlay errors on the selected wafer; and generating, by the computer, a combined overlay correction map using the overlay correction map of each selected wafer in the lot.