Patent ID: 7190619
Filing Date: 2007-03-13
Classification: G11C

Abstract:
1. A circuit for indicating termination of scan of bits to be programmed in a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including a memory array having a plurality of memory cells arranged between word lines and bit lines in a NOR-type array, the memory cells, the number of which corresponds to the number of set bits, being simultaneously programmed through a single program operation, comprising: a counting unit for counting the number of bits to be programmed and providing a group of counting bit signals that indicates the number of bits to be programmed, the number of bits to be programmed being the number of data bits to be programmed among scanned data bits; a set bit number provision unit for providing a group of set bit signals indicating the number of set bits, the number of set bits being able to be externally controlled; and a comparison unit for comparing the group of counting bit signals with the group of set bit signals to ultimately provide a scan termination signal used to control programming for the memory array, the scan termination signal having a logic level changed when the number of bits to be programmed attains the number of set bits.