Patent ID: 6519722
Filing Date: 2003-02-11
Classification: G06F,H04J

Abstract:
An apparatus for controlling the read clock signal rate of a First-In First-Out (FIFO) data memory, the apparatus comprising:an error detector module, responsive to a change in the quantity of data contained in the FIFO data memory to generate an error signal; an integrator module, for integrating said error signal, scaled by a first scaling parameter, to generate an integrated error signal; a control module, responsive to said error signal and to said integrated error signal, for generating a control signal which includes said error signal, scaled by a second scaling parameter, and said integrated error signal; and a read clock rate adjuster module, responsive to said control signal to adjust the rate of the read clock signal, wherein the control module is arranged to determine a value for at least one of the first and second scaling parameters according to the level of the error signal.