Patent ID: 6660581
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method for providing a bitline contact in an integrated circuit structure, including a substrate with a top surface and a body, a deep trench formed in the body with upper and lower sidewalls, a deep trench capacitor and a gate electrode formed in the deep trench, the gate electrode being separated from the body by gate oxide and the deep trench capacitor being separated from the body by a capacitor dielectric layer; a doped source region juxtaposed with the gate electrode near the top surface aside from the gate oxide; and a drain region formed in the body of the substrate connected to the capacitor, with sidewall spacers between the gate electrode and the upper sidewalls of the deep trench, the method comprising:forming a patterning mask over the device exposing a portion of an upper surface of the gate electrode at the top surface of the substrate, the patterning mask being patterned by the line shaping master mask, etching a divot reaching down into the gate electrode alongside a deep trench sidewall spacer juxtaposed with the source region and filling the divot with a dielectric material, forming a wordline stack with a wordline in contact with the gate electrode, forming a conformal liner which is etch resistant covering the structure, forming at least one dielectric layer covering the conformal liner, planarizing the dielectric layer above the wordline stack, forming a bitline contact mask patterned by the line shaping master mask, a bitline contact therethrough above the source region juxtaposed with the deep trench sidewall spacer, and etching a via hole down to the source region in the pattern of the bitline contact mask.