Patent ID: 6835647
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A method of designing a semiconductor circuit for a semiconductor device including a first interconnection layer having relatively short line length, a first insulator formed to surround said first interconnection layer, a second interconnection layer having a longer line length than said first interconnection layer and a second insulator formed to surround said second interconnection layer, comprising the steps of:preparing a first interconnection structure pattern including a plurality of interconnection layers having a prescribed distance between lines and containing a specific material, and an insulator formed to surround each of said plurality of interconnection layers and containing a specific material; preparing a second interconnection structure pattern including a plurality of interconnection layers having a distance between lines approximately the same as said distance between lines of said plurality of interconnection layers of said first interconnection structure pattern and containing a specific material, and an insulator formed to surround each of said plurality of interconnection layers and containing a specific material; calculating a first parasitic capacitance of each interconnection layer of said first interconnection structure pattern; calculating a second parasitic capacitance of each interconnection layer of said second interconnection structure pattern; selecting the material of said interconnection layer of said first or second interconnection structure pattern having smaller one of said first and second parasitic capacitances, as the material to be contained in said first interconnection layer; and selecting the material of said insulator of said first or second interconnection structure pattern having smaller one of said first and second parasitic capacitances, as the material to be contained in said first insulator.