Patent ID: 6784706
Filing Date: 2004-08-31
Classification: H03L

Abstract:
A phase-locked loop, comprising:a controlled oscillator for generating an output signal; a phase detector for detecting difference in phase between a feedback signal and a reference signal; an integrator including a first register for storing a frequency setting for said controlled oscillator and a second register, said second register having an input connected to an output of said first resister; and a controller for transferring the contents of said first register to said second register during normal operation so that after a phase or frequency jump the contents of said first register prior to said jump can be restored when a phase hit occurs so as to restore the frequency setting of the controlled oscillator prior to the phase or frequency jump; and said integrator further including a multiplexer having a first input receiving an output value from said phase detector, a second input receiving an output value from said second register, and an output connected to an input of said first resister; and wherein said controller selects one of said first and second inputs of said multiplexer to pass the output value of said multiplexer to said input of said first register.