Patent ID: 6300242
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, the method comprising:a first step of depositing a first metal film on an insulating film on a semiconductor substrate;a second step of depositing a first interlayer insulating film on the first metal film;a third step of forming, on the first interlayer insulating film, a first mask pattern having an opening over a region in which a via holes to be formed, etching the first interlayer insulating film by using the first mask pattern as a mask, and thereby forming a via hole in the first interlayer insulating film;a fourth step of growing a second metal film in the via hole to form a via contact composed of the second metal film and forming a recessed portion over the via contact in the via hole;a fifth step of forming, in the recessed portion, a cap layer composed of a material different from a material composing the first metal film;a sixth step of forming, on the first interlayer insulating film, a second mask pattern covering a region in which a lower interconnect is to be formed, etching the first interlayer insulating film by using the second mask pattern and the cap layer as a mask, and thereby patterning the first interlayer insulating film;a seventh step of etching the first metal film by using the cap layer and the patterned first interlayer insulating film as a mask and thereby forming a lower interconnect composed of the first metal film;an eighth step of depositing a second interlayer insulating film over an entire surface of the semiconductor substrate;a ninth step of planarizing the second interlayer insulating film and exposing the via contact or the cap layer; anda tenth step of forming, on the second interlayer insulating film, an upper interconnect to be connected to the via contact or the cap layer.