Patent ID: 7933361
Filing Date: 2011-04-26
Classification: H03D,H03G,H04B,H04L

Abstract:
1. An RF receiver circuit for reducing static and dynamic offsets, comprising: a low noise amplifier (LNA); a plurality of down conversion mixers; a plurality of static compensators coupled to the down conversion mixers; a plurality of constant gain stages coupled to the static compensators; a plurality of channel-select low-pass filters connected to the constant gain stages; a plurality of servo-loop feedback amplifiers connected to the channel-select low pass filters, wherein each of the servo-loop feedback amplifiers comprises a plurality of subtractors, a plurality of variable gain amplifiers, and a plurality of low pass filters, wherein one of the low pass filters is coupled between an output of one of the variable gain amplifiers and a minuend end of one and the plurality of servo-loop feedback amplifiers includes three amplifiers connected in a three-stage configuration, the first amplifier having a maximum gain of G if G<=G if G>G if G>(G wherein the gain mapping block is driving the servo-loop feedback amplifiers, and the gain mapping block assigns the gain for each stage in the servo-loop feedback amplifiers in such a way as to use a maximum gain of an earlier stage before assigning an unsatisfied gain to the remaining stages; a plurality of analog to digital converters; and an automatic gain feedback control block driving the LNA and the gain mapping block.