Patent ID: 6545518
Filing Date: 2003-04-08
Classification: G06F,H03K

Abstract:
A timing difference division circuit comprising:two switches connected in parallel to control a path between an inner node and a power source; one of said switches being turned on based on a first input signal undergoing transition to charge or discharge at least one MOS capacitor device that connects said inner node with a first constant current source; the other said switch being turned on based on a second input signal undergoing transition with a delay with respect to said first input signal, said at least one MOS capacitor device connected to said inner node being charged or discharged through said one switch in the on-state and the other switch in the on-state with a current value corresponding to a sum of said first constant current source and a second constant current source; wherein the output of the circuit is directed through a buffer circuit which has an output logic value that is changed when the voltage of said inner node exceeds or is smaller than a predetermined threshold value; said timing difference division circuit further utilizing a predetermined overlap period (Tovp), during which an on time period of said one switch is overlapped with an on time period of said other switch.