Patent ID: 6138230
Filing Date: 2000-10-24
Classification: G06F

Abstract:
A pipelined processor with a plurality of execution pipelines each with a plurality of pipe stages, where each of the pipe stages has associated with it state information, and where instructions issued into an execution pipeline are processed in each pipe stage, thereby altering the associated state information for that pipe stage, comprising:(a) at least first and second execution pipelines with respective corresponding pipe stages;(b) instruction issue circuitry that issues first and second sequences of instructions respectively into the first and second execution pipelines, with at least some of the instructions in the first sequence of instructions being issued into the first execution pipeline substantially simultaneously with instructions in the second sequence of instructions being issued into the second execution pipeline; and(c) pipe control circuitry that monitors the execution of instructions issued into at least the first and second execution pipelines, including the state information associated with the respective corresponding pipe stages of the first and second execution pipelines;(d) in response to such state information, the pipe control circuitry controlling the flow of the first and second sequences of instructions between the respective corresponding pipe stages of the first and second execution pipelines such that an instruction in the first execution pipeline moves from a current pipe stage to a next pipe stage independent of the movement of instructions in corresponding pipe stages of the second execution pipeline.