Patent ID: 6708305
Filing Date: 2004-03-16
Classification: G01R

Abstract:
A computer chip comprising:a plurality of scan channels; at least one pseudorandom pattern generator (PRPG) coupled to the plurality of scan channels a P clock tree; a P scan gate signal; a P clock gating device coupled to the P clock and the PRPG, the P clock gating device responsive to a P scan gate signal to independently gate at least a portion of the P clock tree, wherein the PRPG is stopped from advancing to a new pattern; at least one Multiple Input Serial Register (MISR) coupled to the plurality of scan channels; an M scan gate signal; an M clock tree; and an M clock gating device coupled to the M clock tree, MISR and scan channels, the M clock gating device responsive to the M scan gate signal to independently gate at least a portion of the M clock tree, wherein the MISR and devices in the scan channels are stopped from shifting.