Patent ID: 6081142
Filing Date: 2000-06-27
Classification: G11C,H03L

Abstract:
An access time adjusting method for a semiconductor device provided with an input circuit for providing a first internal clock in response to an external clock; a variable delay circuit for delaying said first internal clock by a delay time to provide a delayed first internal clock as a second internal clock; and an output circuit for outputting data in synchronization with said second internal clock, said method comprising the steps of:providing a) a dummy circuit, having a dummy loads, for providing a delayed second internal clock in response to said second internal clock as a dummy clock; b) a phase comparator circuit for comparing a phase of said first internal clock with a phase of said dummy clock; and c) a delay adjusting circuit for adjusting said delay time so that a difference between said phases of said first internal clock and said dummy clock becomes a predetermined value;determining a value L2 of said dummy load as a value shifted by a shift value .DELTA.L from a proper value L1 of said dummy load when an access time ta does not depend on a frequency of said data, where said shift value .DELTA.L corresponds to substantially a half of a maximum value of deviations of said access time that varies depending on said frequency of said data; andwhen said dummy load is set to said value L2, activating said phase comparator circuit and said delay adjusting circuit to determine said delay time of said variable delay circuit.