Patent ID: 6148363
Filing Date: 2000-11-14
Classification: G06F,G11C,Y02D

Abstract:
A mass storage system for use with a computer system, comprising:a plurality of solid-state memory chips, each having a large number of memory cells therein that are individually programmable into more than two states in order to store more than one bit of data per cell;a memory chip controller coupled to the computer system for controlling said plurality of memory chips;a device bus for connecting said memory chip controller to each of said plurality of solid-state memory chips, said device bus carrying serialized address, data and command information, thereby substantially reducing the number of connections between said memory chip controller and each of said plurality of memory chips;one or more backplanes each containing a plurality of mounts, each of said plurality of mounts for receiving one of said plurality of memory chips;said device bus being coupled to each of the plurality of mounts for connection to the memory chip thereon;a set of device-select pinouts on each of said memory chips; anda set of pads on each of said mounts for connection to the set of device select pinouts of a memory chip mounted thereon, each set of pads having a predetermined configuration of grounded pads to define a mount address and therefore a unique array address for each of said memory chips mounted on said one or more backplanes.