Patent ID: 8058679
Filing Date: 2011-11-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in said logic formation region; first and second gate structures formed on said upper surface of said semiconductor substrate in said first impurity region and spaced apart at a first distance from each other; a second impurity region formed in an upper surface of said semiconductor substrate in said logic formation region and having a conductivity type same as that of said first impurity region; third and fourth gate structures formed on said upper surface of said semiconductor substrate in said second impurity region and spaced apart at a second distance from each other; a third impurity region formed in an upper surface of said first impurity region between said first and second gate structures and having a conductivity type different from that of said second impurity region; a fourth impurity region formed in an upper surface of said second impurity region between said third and fourth gate structures and having a conductivity type different from that of said second impurity region; a first silicide film formed in an upper surface of said third impurity region; and a second silicide film formed in an upper surface of said fourth impurity region and having a larger thickness than said first silicide film; wherein said first and second silicide films are formed between first and second gate structures and between said third and fourth gate structures respectively, and a first gate aspect ratio defined by the first distance and a height of said first and second gate structures is larger than a second gate aspect ratio defined by the second distance and a height of said third and fourth gate structures.