Patent ID: 6449740
Filing Date: 2002-09-10
Classification: G11C

Abstract:
A single chip microcomputer fabricated on a semiconductor chip and having a data processing mode and a test mode, comprising:a central processing unit executing programmed instructions expressing at least one job in said data processing mode; an electrically erasable and programmable read only memory storing pieces of information used in said data processing mode for said central processing unit, and tested to see whether said pieces of information are properly maintained in said test mode; plural communication pads classified into a first communication pad group used for said job in said data processing mode and a second communication pad group used for said job in said data processing mode and available for a test in said test mode and said communication pads being arranged along an edge of said semiconductor chip; and plural conductive paths selectively connected between said plural communication pads, said central processing unit and said electrically erasable and programmable read only memory, wherein said paths couple said first and second communication pad groups to said central processing unit in response to a control signal being inactive and wherein said paths couple said second communication pad groups to said electrically erasable and programmable read only memory in response to said control signal being active.