Patent ID: 7577188
Filing Date: 2009-08-18
Classification: H03D

Abstract:
1. An apparatus, comprising: a first memory containing a first known pseudorandom sequence; a second memory containing a second known pseudorandom sequence; a third memory containing a third known pseudorandom sequence a receiver for receiving a signal; an analog to digital converter receiving the signal from the receiver and operable to convert the signal to a digital packet having a synchronization preamble; a first correlator comprising a shift register configured receiving the output from the analog to digital converter and storing the output as a plurality of discrete values, and a plurality of multipliers where each multiplier receives one input from the shift register and a second input from the first memory for receiving a corresponding portion of the first known pseudorandom sequence, the first correlator further comprising a summing circuit coupled to outputs of the plurality of multipliers, the summing circuit producing an output indicating whether a correlation was found between the first known pseudorandom sequence and contents of the shift register; and a second correlator comprising a shift register configured for receiving the output from the analog to digital converter and storing the output as a plurality of discrete values, and a plurality of multipliers, where each multiplier receives one input from the shift register and a second input from the second memory for receiving a corresponding portion of the second known pseudorandom sequence, the second correlator further comprising a summing circuit coupled to outputs of the plurality of multipliers, the summing circuit producing an output indicating whether a correlation was found between the second known pseudorandom sequence and contents of the shift register; a third correlator comprising a shift register configured for receiving the output from the analog to digital converter and storing the output as a plurality of discrete values, and a plurality of multipliers, where each multiplier receives one input from the shift register and a second input from the second memory for receiving a corresponding portion of the third known pseudorandom sequence, the third correlator further comprising a summing circuit coupled to outputs of the plurality of multipliers, the summing circuit producing an output indicating whether a correlation was found between the first known sequence and contents of the shift register; wherein the type of node sending the signal is determined to support enhanced Quality of Service (QoS) responsive to the first correlator finding a correlation within the synchronization preamble and the first known pseudorandom sequence while performing packet synchronization; wherein the type of node sending the signal is determined to support enhanced synchronization responsive to the second correlator finding a correlation with the second known pseudorandom sequence within the synchronization preamble while performing packet synchronization; and wherein the type of node sending the signal is determined to support enhanced power savings responsive to the third correlator finding a correlation with the third known pseudorandom sequence within the synchronization preamble while performing synchronization.