Patent ID: 6907385
Filing Date: 2005-06-14
Classification: G11C

Abstract:
1. A method of analyzing and processing a repair of failure that is carried out in a memory testing apparatus which comprises: a failure analysis memory for storing therein failure data representing a failure memory cell or cells of a memory under test having redundancy structure; and a failure repair analyzing and processing apparatus for analyzing as to whether the failure memory cell or cells of the memory under test can be repaired on the basis of the failure data read out from the failure analysis memory after the testing has been completed, said method comprising the steps of: reading out failure data respectively from plural specified data bit memory areas of the failure analysis memory in sequence and distributing them to corresponding plural repair analysis units respectively; and operating concurrently the plural repair analysis units in parallel with each other and causing the units to carry out concurrently their repair analyses and processings for the failure memory cell or cells corresponding to the failure data read out from the failure analysis memory in parallel with each other.