Patent ID: 6265265
Filing Date: 2001-07-24
Classification: H01L,Y10S

Abstract:
A method of fabricating a flash memory cell, the method comprising:implanting a second type impurity into a first portion of a semiconductor substrate of a first type impurity;forming a first gate insulating layer and a buried insulating layer by oxidizing a surface portion of said semiconductor substrate including said first portion;forming a source region by diffusing said second type impurity during said oxidizing process;forming a floating gate on said gate insulating layer, said floating gate having a striped pattern in a first direction, the first direction being defined by a direction between said source region and said drain region;forming a second gate insulating layer on a portion of said floating gate, said second gate insulating layer having a striped pattern in a second direction that is perpendicular to said first direction;forming a control gate on said second gate insulating layer;forming a capping insulating layer on said control gate;forming an insulating sidewall spacer at lateral surfaces of said second insulating layer, said control gate and said capping insulating layer, said lateral surfaces being positioned over said buried insulating layer;patterning said first gate insulating layer and said control gate using said capping insulating layer and said insulating sidewall spacer as a mask;forming a third gate insulating layer at a lateral surface of said floating gate;forming a drain region in an exposed part of said semiconductor substrate, said drain region having a second type impurity, the first direction being defined by a direction between said source region and said drain region; andforming an erasing gate over said buried insulating layer.