Patent ID: 7102230
Filing Date: 2006-09-05
Classification: H01L,H05K,Y02P

Abstract:
1. A circuit carrier adapted for a pin grid array (PGA) package, the circuit carrier comprising: a substrate comprising a surface; at least one pin pad disposed over the surface of the substrate; at least one solder mask layer disposed over the surface of the substrate, and exposing at least a portion of the pin pad; at least one solder layer disposed over the pin pad; at least one pin, one end of the pin connecting to the pin pad through the solder layer; a fixing layer disposed over the solder mask layer, and covering the solder layer and a portion of a side surface of the pin; at least one electrode pad disposed on the surface of the substrate, wherein the solder mask layer exposes at least a portion of the electrode pad; and a patterned barrier layer disposed over the solder mask layer, the patterned barrier layer exposing a first area and a second area of the surface of the substrate, wherein the pin pad is disposed in the first area, the electrode pad is not disposed in the first area, but in the second area, and the fixing layer is disposed in the first area of the surface of the substrate.