Patent ID: 8412144
Filing Date: 2013-04-02
Classification: G06F

Abstract:
1. Architecture for supporting zero intermediate frequency (ZIF) or low intermediate frequency (LIF)/intermediate frequency (IF) systems, comprising: 4N pins, N being a positive integer; 2N analog to digital converters (ADCs), comprising a y-th ADC for converting a differential analog signal, received by a (2y−1)-th pin and a 2y-th pin of the pins, into a y-th digital signal, y being positive integers ranging from 1 to 2N; a determination unit for determining whether the digital signals are ZIF signals, LIF signals or IF signals; and a processing unit for performing an ZIF system processing on the ZIF signals, performing a LIF system processing on the LIF signals, and performing an IF system processing on the IF signals.