Patent ID: 7692966
Filing Date: 2010-04-06
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory array, wherein said memory array comprises a plurality of sub-blocks; each sub-block comprises a plurality of word lines extending in a first direction, a plurality of local bit lines which extend in a second direction crossing said first direction, and a plurality of memory cells each storing information based on a level change of its threshold voltage and each placed so as to correspond to each intersection of a word line and a local bit line; said plurality of sub-blocks are arrayed in said second direction; and said nonvolatile semiconductor memory device further comprising: said selected memory cell is connected to said sense latch via corresponding first and second switching circuits, and said sense latch carries out write-in/read-out of data into/from said selected memory cell in cooperation with said voltage controlling circuit and said decoder.