Patent ID: 7998819
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A method for forming a lateral MOSFET comprising the steps of: growing a first epitaxial layer on a substrate, said first epitaxial layer and said substrate being of a first conductivity type; growing a second epitaxial layer on said first epitaxial layer; forming a gate electrode on a gate dielectric which in turn is formed on a top surface of said second epitaxial layer; forming a drain region of said first conductivity type in said second epitaxial layer which extends to a top surface of said epitaxial layer and is proximate to a first edge of said gate electrode; forming a source region of said first conductivity type in said second epitaxial layer which extends to a top surface of said second epitaxial layer and is proximate to a second edge of said gate electrode; forming a heavily doped body of a second conductivity type in said second epitaxial layer opposite to said first conductivity type under at least a portion of said source region; and forming a lightly doped well of said second conductivity type in said second epitaxial layer under said gate dielectric which extends to said heavily doped body; wherein a PN junction lying between said heavily doped body and said first epitaxial region under said heavily doped body defines a voltage clamping region, and a reverse bias voltage that is slightly less than a breakdown voltage applied to said PN junction in said voltage clamping region creates a depletion region that extends to a region of said first epitaxial layer in which the vertical dopant concentration is substantially constant.