Patent ID: 6391723
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer, the method comprising:implanting a first concentration of a first conductivity type dopant through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer to form a body region of the VDMOS structure; forming a mask on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region; implanting through the apertures of the mask a second conductivity type dopant into the body region to define source regions in a superficial zone; implanting through the apertures of the mask a second concentration of the first conductivity type dopant at a depth below the superficial zone to form regions with a higher dopant concentration within the body region; and annealing to form source and body junctions above the higher dopant concentration regions within the body region.