Patent ID: 7823161
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A computing system comprising: one or more processing elements; a memory having a first interface for connecting to a host processor and a second interface, the memory being divided into a plurality of logical partitions each having a particular size, at least one partition being a system partition that contains information regarding the size of a partition that describes a particular task including a state of the task; and wherein a task partition includes one or more task data registers and task code and the system partition includes a first specifier J giving a number of words per increment, a second specifier M giving a number of increments per data register, and a third specifier N giving a number of data registers offset to a starting location of the task code in the task partition, said first and second specifiers being combined to give a starting location of the one or more task data registers in the task partition, and said first, second and third specifiers being combined to give a starting location of the task code in the task partition, said task partition having a location defining end of the task partition; a multi-task controller (MTC) that includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit, each unit coupled to the other units, wherein the number of processing elements and number of tasks are independent of each other.