Patent ID: 8981809
Filing Date: 2015-03-17
Classification: G01R,H01L,Y10T

Abstract:
1. A compliant printed circuit semiconductor tester interface providing a temporary interconnect between terminals on integrated circuit (IC) devices being tested, the compliant printed circuit semiconductor tester interface comprising: at least one dielectric layer printed with recesses corresponding to a target circuit geometry; a conductive material deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads formed in the at least one dielectric layer, the circuit geometry comprising a plurality of conductive traces electrically coupled to the plurality of first contact pads accessible along a first surface of the compliant printed circuit; at least one dielectric covering layer; a plurality of openings in the dielectric covering layer permitting electrical coupling of the terminals on the IC device and the first contact pads, the circuit geometry extending beyond the openings in the covering layer; one or more compliant layers positioned to elastically bias a plurality of the first contact pads against the terminals on the IC device; and testing electronics electrically coupled to the portion of the circuit geometry that extends beyond the openings in the dielectric layer to test electrical functions of the IC device.