Patent ID: 7532449
Filing Date: 2009-05-12
Classification: H03F

Abstract:
1. An adjusting method for an analog semiconductor integrated circuit, the analog semiconductor integrated circuit including: an input terminal, an output terminal and an internal node, an analog circuit for outputting an analog signal to the internal node in accordance with an input signal supplied to the input terminal, a protective circuit having a first and second diode-connected transistors connected with a reverse bias, the first diode-connected transistor being provided between the input terminal and a supply line, and the second diode-connected transistor being provided between the input terminal and a ground line, an output section having a MOS transistor, a gate of the MOS transistor being connected to the internal node, a source of the MOS transistor being connected to the ground line, and a drain of the MOS transistor being connected to the output terminal, and a bias adjustment circuit having a plurality of fuses for adjusting a bias voltage that is supplied to the internal node by disconnecting an appropriate number of said fuses among from the plurality of fuses,