Patent ID: 6518122
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method to form Flash EEPROM memory cells in the manufacture of an integrated circuit device comprising:providing a semiconductor substrate; forming a tunneling oxide layer overlying said semiconductor substrate; depositing a first polysilicon layer overlying said tunneling oxide layer; depositing an interpoly oxide layer overlying the first polysilicon layer; depositing a second conducting layer overlying said interpoly oxide layer; patterning said second conducting layer, said interpoly oxide layer, said first polysilicon layer, and said tunneling oxide layer to form control gates and floating gates for planned Flash EEPROM memory cells; implanting ions to form drain junctions for said planned Flash EEPROM memory cells in said semiconductor substrate wherein said drain junctions are shallow and abrupt; implanting ions to form angled pocket junctions adjacent to said drain junctions wherein said angled pocket junctions are implanted at a non-perpendicular angle with respect to said semiconductor substrate and are counter-doped to said drain junctions; and implanting ions to form source junctions wherein said source junctions are deeper and less abrupt than said drain junctions.