Patent ID: 6104645
Filing Date: 2000-08-15
Classification: G11C

Abstract:
In a memory device including a plurality of memory sub-arrays, each sub-array including a plurality of primary and redundant memory cells arranged in row and column groupings, a system for enabling one of the redundant memory cell groupings to be accessed in lieu of one of the primary memory cell groupings, the system comprising:a plurality of banks of programmable elements, each bank being operatively associated with only one of the redundant memory cell groupings and being programmable to respond to receiving an address associated with a non-operative primary memory cell in any one of the sub-arrays by outputting a match signal corresponding to the redundant memory cell grouping operatively associated with the bank; andan enabling circuit coupled to each of the banks of programmable elements for receiving the match signal and, in response, enabling redundant memory operations in the redundant memory cell grouping that corresponds to the match signal and disabling primary memory operations in the primary memory cell grouping of the non-operative primary memory cell.