Patent ID: 6479344
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of fabricating a DRAM capacitor over a semiconductor substrate, the semiconductor substrate comprising a MOS transistor having a source/drain region and an insulating layer with an opening over the source/drain region, the method comprising the steps of:forming a doped polysilicon layer to fill the opening and to connect with the source/drain region; patterning the doped polysilicon layer in a manner such that a portion of the doped polysilicon layer over the opening is substantially thicker than the remaining portion of the doped polysilicon layer which cover a top surface of the insulating layer; forming a tungsten silicide barrier layer on the patterned doped polysilicon layer; patterning the tungsten silicide barrier layer and the patterned doped polysilicon layer so that a portion of the doped polysilicon layer between the insulating layer and the tungsten silicide barrier layer is exposed; forming a tungsten nitride layer on the tungsten silicide barrier layer, wherein a rapid thermal annealing in an atmosphere of an ammonia is carried out during the formation of the tungsten nitride layer, wherein the exposed doped polysilicon layer is transformed into a silicon nitride oxide layer, thereby the tungsten nitride layer forms a bottom electrode of the DRAM capacitor, and forming a dielectric layer and an upper electrode on the bottom electrode to finish the structure of the DRAM capacitor.