Patent ID: 8330518
Filing Date: 2012-12-11
Classification: H03K

Abstract:
1. A low consumption flip-flop circuit with data retention, comprising: a first flip-flop having a first input terminal configured to receive a logic state, a first output terminal, a second output terminal, and a supply terminal configured to receive a first supply voltage; a first retention cell having a first input terminal coupled to the second output terminal of the first flip-flop, a second input terminal configured to receive a low consumption command, a first supply terminal configured to receive the first supply voltage, a second supply terminal configured to receive a second supply voltage that is independent of the first supply voltage, a first output terminal, and a second output terminal, wherein the first retention cell is configured to provide to the first output terminal of the first retention cell a logic state from the first input terminal of the first retention cell during a normal operation mode, the first retention cell including: a second flip-flop having a first input terminal and a first output terminal; and a second retention cell having a first input terminal coupled to the first output terminal of the second flip-flop, a second input terminal configured to receive the low consumption command, a third input terminal, and an output terminal, the third input terminal being coupled to the second output terminal of the first retention cell and configured to receive the logic state memorized by the latch circuit of the first retention cell, and the second retention cell is configured to, on return to the normal operation mode, provide on the output terminal of the second retention cell the logic state memorized by the latch circuit and received by the third input terminal of the second retention cell.