Patent ID: 7670927
Filing Date: 2010-03-02
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: fabricating a first wafer including one or more first devices in a silicon-on-insulator first wafer, said first wafer comprising a first buried oxide layer between a first upper silicon layer and a first lower silicon layer and a first dielectric layer on said first upper silicon layer, at least a portion of each first device of said one or more first devices formed in said first upper silicon layer, said first devices interconnected with one or more first wiring levels formed over said first upper silicon layer, each wiring level of said one or more first wiring levels comprising electrically conductive wires in a corresponding dielectric layer, said one or more first wiring levels including electrically conductive wires formed in said first dielectric layer; fabricating a second wafer including one or more second devices in a silicon-on-insulator second wafer, said second wafer comprising a second buried oxide layer between a second upper silicon layer and a second lower silicon layer and a second dielectric layer on said second upper silicon layer, at least a portion of each second device of said one or more second devices formed in said second upper silicon layer; after said fabricating one or more first devices, removing said first lower silicon layer from said first wafer to expose a surface of said first buried oxide layer; after said fabricating one or more second devices, forming a third dielectric layer on said second upper silicon layer; after forming said third dielectric layer; removing said second lower silicon layer from said second wafer to expose a surface of said second buried oxide layer; bonding said surface of said first buried oxide layer to said surface of said second buried oxide layer to form a double wafer having first and second opposite sides, said first wiring levels on said first side of said double wafer; after said bonding, forming electrically conductive first contacts to one or more of said second devices from said second side of said double wafer, said first contacts extending from a top surface of said third dielectric layer through said third dielectric layer to said second devices; after said bonding, forming electrically conductive second contacts to one or more of said first devices from said second side of said double wafer, said second contacts extending from said top surface of said third dielectric layer through said third dielectric layer, through dielectric isolation formed in said second upper silicon layer, and through said first and second buried oxide layers to those portions of said first devices formed in said first upper silicon layer; and after said forming said first and second contacts, interconnecting said first and second contacts with one or more second wiring levels formed on said second side of said double wafer, each wiring level of said one or more second wiring levels comprising electrically conductive wires in a corresponding dielectric layer.