Patent ID: 6404238
Filing Date: 2002-06-11
Classification: H03K

Abstract:
A logic gate comprising a current mirror circuit having a supply node, a first node and a second node wherein application of a first current at said first node causes a second current at said second node, plural input pull-down transistors connected in parallel between a reference node and one of said first and second nodes, and an output pull-down transistor connected between the other of said first and second nodes and said reference node, wherein said supply node has a connection to a supply terminal, said plural input pull-down transistors have respective control terminals connected to a corresponding plurality of input terminals, and said output pull-down transistor has circuitry connected to its control node for biasing it on, wherein said plural input pull-down transistors are mutually substantially identical and wherein said output pull-down transistor is smaller than each of said plural input pull-down transistors.