Patent ID: 6054383
Filing Date: 2000-04-25
Classification: H01L

Abstract:
A fabrication method of a semiconductor device, comprising:(a) preparing a semiconductor substructure;(b) forming a first interlevel dielectric layer on said semiconductor substructure;(c) forming a first wiring layer on said first interlevel dielectric layer; (d) forming a second interlevel dielectric layer on said first interlevel dielectric layer to cover said first wiring layer;(e) forming a first opening in said second interlevel dielectric layer to expose the top of said first wiring layer;(f) forming a first conductive layer on said second interlevel dielectric layer to cover said first opening, said first conductive layer having a first concave part located in said first opening according to the configuration of said first opening;(g) forming a first protection layer on said first conductive layer to cover said first concave part of said first conductive layer, said first protection layer having a first buried part located on said first concave part of said first conductive layer;(h) polishing said first protection layer and said first conductive layer until said second interlevel dielectric layer is exposed, thereby selectively leaving said first concave part of said first conductive layer within said first opening;wherein said first concave part left within said first opening constitutes a first conductor plug for electrically interconnecting said first wiring layer with a second wiring layer which is formed to contact said first conductor plug; and forming a plurality of openings in said second interlevel dielectric layer;wherein said first opening has a minimum diameter size among said first opening and said plurality of openings; andwherein said first conductive layer has a thickness equal to (1/5) to (2/5) of said minimum diameter size of said first opening.