Patent ID: 7039770
Filing Date: 2006-05-02
Classification: G06F

Abstract:
1. A queue comprising: a first queue configured to enqueue and dequeue data units, the first queue including a plurality of parallel sub-queues that queue a plurality of parallel data units; a second queue configured to receive data units from the first queue when the first queue has data units available to be dequeued, the second queue including a first buffer configured to store a first set of the parallel data units and a second buffer configured to store a second set of the parallel data units, the second queue outputting up to a predetermined number of the first set of the parallel data units in a clock cycle and, when a number of data units in the first set of parallel data units is less than the predetermined number, output one or more of the second set of parallel data units in parallel with the first set of the parallel data units; and bypass logic coupled to the second queue, the bypass logic configured to bypass the first queue and to forward data units to the second queue when the second queue is ready to receive data units and the first queue is empty.