Patent ID: 7817457
Filing Date: 2010-10-19
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation; wherein the second data latch stores data read from the given group of memory cells, and wherein the write and erase operations include controlling operations based on prohibition of an additional write and prohibition of an additional erase for a given bit that is identified by a comparison between the data stored in the first data latch and the second data latch.