Patent ID: 6091116
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A CMOS device, comprising:first and second wells formed in respective first and second regions of a semiconductor substrate, said substrate further including a third region outside of said first and second regions;a first impurity layer formed in at least one but not more than two of said first, second, and third regions of said substrate, said first impurity layer being formed to a first depth;a second impurity layer formed in the regions of said substrate in which said first impurity layer is not formed, said second impurity layer being formed to a second depth treater than said first depth; andfirst and second transistors formed in said first and second wells, respectively, and a third transistor formed in said third region;wherein said first death is equal to a corresponding depletion region of said first, second, and/or third regions in which said first impurity layer is formed, and wherein said first and second wells are of opposite conductivity types; andwherein said first well is an N-well, said second well is a P-well, said first impurity layer is formed in said first and second regions, and said second impurity layer is formed in said third region.