Patent ID: 6397306
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A multiprocessor system architecture comprising:a plurality of processors; a plurality of memories for access by at least one of the processors; a bridge coupled between at least two processors, the bridge providing access between the processors and at least one of the memories, the bridge including a bridge controller, said bridge controller being capable of regulating access to a bus shared by said at least two processors to access the memories, and a plurality of lock registers, each lock register retaining a bit mask and each lock register being associated with one of the memories; means for accessing a particular bit mask retained in a particular lock register, the particular lock register being associated with a particular memory; means for determining if the particular bit mask is marked; and initiating means, if the particular bit mask is not marked, for marking the particular bit mask and initiating a memory reference, wherein the memories and the processors are organized as a plurality of segments, each :segment including at least one of the processors and at least one of the memories.