Patent ID: 6584021
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A semiconductor memory, comprising:a memory cell array including dynamic memory cells; an output connection operatively connected to said memory cell array for outputting data values stored in said dynamic memory cells; a state machine selectively having an operating state selected from the group consisting of Read, Write and Refresh and having a signal connection providing a control signal for displaying the operating state Read; a delay locked loop operatively connected to said state machine, said delay locked loop receiving an input clock signal and providing a delayed output clock signal, said delay locked loop having a signal connection for receiving the control signal from said state machine, said delay locked loop being configured to be actuated by the control signal in order to suppress a change in a delay time between the input clock signal and the delayed output clock signal during the operating state Read; and an output driver operatively connected to said delay locked loop, said output driver being configured to be actuated by the delayed output clock signal in order to provide, at said output connection, data values read from said dynamic memory cells in sync with the delayed output clock signal.