Patent ID: 6337817
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory mat having a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells; and a redundancy circuit having an output node coupled to said spare bit line and input nodes to which a first information indicating one of said plurality of bit lines and a second information indicating one of said plurality of word lines are applied, wherein said redundancy circuit includes a first comparing circuit having first input nodes coupled to the input nodes of said redundancy circuit, programmable elements, and a first output node coupled to the output node of said redundancy circuit, and wherein the programmable elements can be programmed for one of a first defect mode and a second defect mode, the first defect mode being associated with a defect in one of said plurality of memory cells and said programmable elements can be programmed to activate said spare bit line on a basis of both said first and second information, and said second defect mode being associated with a defect in one of said plurality of bit lines in said memory mat and said programmable elements can be programmed to activate said spare bit line independently of said second information.