Patent ID: 8587125
Filing Date: 2013-11-19
Classification: H01L

Abstract:
1. A method of manufacturing a plurality of layered chip packages, each of the layered chip packages comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein: the main body includes: a plurality of semiconductor chips stacked, each of the semiconductor chips having a top surface, a bottom surface, and four side surfaces; an insulating portion that covers at least one of the four side surfaces of each of the plurality of semiconductor chips and forms the at least one of the side surfaces of the main body on which the wires are disposed; and a plurality of electrodes that electrically connect at least one of the semiconductor chips to the wires, the method comprising the steps of: fabricating a substructure that includes: an array of a plurality of pre-separation main bodies; and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes of the substructure by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are cut into the wires, wherein: the step of fabricating the substructure includes the steps of: the step of fabricating the initial substructure includes the steps of: wherein the step of forming the plurality of holes in the initial substructure forms the plurality of holes such that each of the plurality of holes penetrates all of the insulating layers of the plurality of chip arrays.