Patent ID: 6324105
Filing Date: 2001-11-27
Classification: G11C

Abstract:
An integrated circuit, comprising:a memory-cell array including a plurality of memory cells arranged in rows and columns, the array including at least one redundant memory cell and each of the memory cells having an associated data topology;a data path circuit coupled between an external data terminal and the memory-cell array, the data path circuit operable to transfer data between the external terminal and the array, the data topology between data on the external terminal and data at the array being adjusted responsive to a data topology signal;an address decoder having an input adapted to receive an address applied on an address bus and having a terminal coupled to receive a matching signal, the address decoder operable when the matching signal is inactive to access memory cells in the memory-cell array corresponding to the applied address, and operable when the matching signal is active to access a redundant memory cell in the array;a programmable data topology element having a programmed state and an unprogrammed state; anda data topology circuit coupled to the address bus, address decoder, data path circuit, and the programmable data topology element, the data topology circuit operable responsive to the address to apply an active matching signal to the decoder to access a redundant memory cell in the array, and operable responsive to the matching signal being active and the state of the programmable topology element to apply the data topology signal to the data path circuit to adjust the data topology of the accessed redundant memory cell.