Patent ID: 8298914
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A method for fabricating a 3D integrated circuit, the method comprising the steps of: providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias; providing a first active circuitry layer wafer including active circuitry and through-silicon vias; bonding the first active circuitry layer wafer face down to the interface wafer; after bonding the first active circuitry layer wafer face down to the interface wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer; after removing the first portion of the first active circuitry layer wafer, fabricating a second wiring layer on the second portion of the first active circuitry layer wafer; providing a second active circuitry layer wafer including active circuitry; bonding the second active circuitry layer wafer face down to the second wiring layer; after bonding the second active circuitry layer wafer face down to the second wiring layer, removing a first portion of the second active circuitry layer wafer such that a second portion of the second active circuitry layer wafer remains attached to the second wring layer; after removing the first portion of the second active circuitry layer wafer, fabricating a third wiring layer on the second portion the second active circuitry layer wafer; providing a base wafer, the base wafer including a fourth wiring layer; bonding the third wiring layer face down to the base wafer; after bonding the third wiring layer face down to the base wafer, thinning the interface wafer so as to form an interface layer, and forming metallizations comprising solder bumps on the interface layer, the solder bumps being coupled through the through-silicon vias in the interface layer to the first wiring layer; and bonding the solder bumps to a package.