Patent ID: 8129236
Filing Date: 2012-03-06
Classification: H01L

Abstract:
1. A method, comprising: forming a first sidewall spacer structure on sidewalls of a gate electrode of an N-channel transistor and a second sidewall spacer structure on sidewalls of a gate electrode of a P-channel transistor in a common patterning sequence, said first and second sidewall spacer structures comprising an etch stop layer and at least one spacer element; forming drain and source regions of said N-channel transistor by using said first sidewall spacer structure as an implantation mask; forming drain and source regions of said P-channel transistor by using said second sidewall spacer structure as an implantation mask; removing said at least one spacer element of each of said first and second sidewall spacer structures selectively to said etch stop layer in a common etch process; forming a material layer above said N-channel transistor and above said P-channel transistor; and selectively removing a first portion of said material layer from above said P-channel transistor, and thereafter performing an anneal process in the presence of a second portion of said material layer to re-crystallize said drain and source regions of the N-channel transistor in a strained state.