Patent ID: 6406968
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method of forming dynamic random access memory, comprising the steps of:providing a substrate having at least a memory cell region and a logic circuit region, wherein the memory cell region and the logic circuit region each has a plurality of gates and a plurality of source/drain regions; forming a first dielectric layer over the substrate; forming a plurality of connective liner pads in the first dielectric layer within the memory cell region; forming a second dielectric layer over the first dielectric layer; forming a bit line contact that connects electrically with a portion of the connective liner pad in the second dielectric layer inside the memory cell region and at the same time forming a plurality of contacts in the second dielectric layer and the first dielectric layer within the logic circuit region; forming a bit line over the second dielectric layer within the memory cell region and at the same time forming a plurality of first metallic layers over the second dielectric layer within the logic circuit region; forming a third dielectric layer over the second dielectric layer; forming a plurality of node contacts that connect electrically with a portion of the respective connective liner pads in the third dielectric layer and the second dielectric layer within the memory cell region and at the same time forming a plurality of first vias that connect electrically with the respective first metallic layer in the third dielectric layer within the logic circuit region; forming a plurality of intermediate dielectric layers stacked over the third dielectric layer, wherein each of the intermediate dielectric layers in the logic circuit region includes a plurality of intermediate metallic layers and a plurality of intermediate vias therein that are placed in a manner to be electrically connected to one another through the intermediate dielectric layers; forming a plurality of openings in the intermediate dielectric layers within the memory cell region such that the openings expose a portion of the respective node contacts; forming a capacitor inside the openings of the intermediate dielectric layers within the memory cell region; forming a fourth dielectric layer over the intermediate dielectric layers; forming a plurality of second vias in the fourth dielectric layer and the intermediate dielectric layers within the logic circuit region for connecting with the respective intermediate metallic layers; forming a plurality of second metallic layers over the fourth dielectric layer; forming a fifth dielectric layer over the fourth dielectric layer; forming a plurality of third vias in the fifth dielectric layer within the logic circuit region; and forming a plurality of third metallic layers over the fifth dielectric layer.