Patent ID: 7012956
Filing Date: 2006-03-14
Classification: G11C,H03K,H04L

Abstract:
1. A method of calibrating a programmable delay line having a plurality of variable delay stages each with a delay set in response to delay adjust signals, comprising the steps of: a) delaying a divided clock signal with a programmable clock delay line by selecting a number K of the variable delay stages in the programmable clock delay line in response to first delay programming signals, thereby generating a toggle clock signal, wherein the divided clock signal is generated by frequency dividing the clock signal by two; b) delaying the divided clock signal with a programmable data delay line by selecting a number N of the variable delay stages in the programmable data delay line in response to second delay programming signals, thereby generating a delayed toggle clock signal; c) delaying the clock signal with a programmable sample delay line by selecting a number P of the variable delay stages in the programmable sample delay line in response to third delay programming signals, thereby generating a sample clock signal; d) setting the numbers K, N, and P to their initial values to equalize initial delays of the programmable clock delay line, the programmable data delay line, and the programmable sample delay line; e) sampling the toggle clock signal and the delayed toggle clock signal with the sample clock signal in a latch circuit and generating a calibrate signal as a logic combination of the toggle clock signal and the delayed toggle clock signal when sampled; and f) calibrating the programmable delay line in response to the calibrate signal.