Patent ID: 6248623
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method of manufacturing an embedded memory with different spacer widths on a substrate having a memory cell region and a logic circuit region, wherein a plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region, the method comprising the steps of:forming a conformal buffer layer and a conformal nitride layer over the substrate in sequence;removing a portion of the nitride layer to form a first spacer on a sidewall of each of the first gate structures and on a sidewall of each of the second gate structures;forming doped regions in the substrate between the first spacer;forming an oxide layer over the substrate, wherein the oxide layer fills spaces between the first gate structures;removing a portion of the oxide layer and a portion of the buffer layer to form a second spacer on each of the first spacers in the logic circuit region and to simultaneously form a silicide block filling spaces between the first gate structures in the memory cell region;forming a source/drain region in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region; andforming a silicide layer on the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.