Patent ID: 6557116
Filing Date: 2003-04-29
Classification: G06F

Abstract:
A digital system comprising a processor, wherein the processor is operable to execute a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit, wherein the processor comprises:system resources including registers and at least one memory circuit; condition circuitry for storing at least one condition; test port circuitry for receiving test commands from a remote test host; emulation circuitry for debug events connected to the test port circuitry, operable to cause the processor to enter a debug suspend state in response to a debug event and to leave the debug suspend state to resume execution of the sequence of instruction in response to a command received by the test port circuitry, wherein execution of the sequence of instructions ceases while the processor is in the debug suspend state; wherein the emulation circuitry is operable to access the system resources in response to an access command received by the test port circuitry if a first condition of the at least one condition is in a first state; and wherein the emulation circuitry is blocked from entering the debug state if the first condition is in a second state.