Patent ID: 6070222
Filing Date: 2000-05-30
Classification: G06F,G11C,Y02D

Abstract:
A synchronous memory device having a memory cell array divided into a plurality of subarrays, wherein each subarray includes a plurality of subarray sections and each subarray section includes a plurality of memory cells, the memory device comprising:clock receiver circuitry to receive at least a first external clock signal from an external bus;clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with the first external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with the first external clock signal;a programmable register to store first identification information wherein the first identification information identifies the memory device;interface circuitry coupled to the external bus to receive a read request and second identification information;a first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;a second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request when the first identification information corresponds to the second identification information; andmultiplexer circuitry, coupled to the output driver circuitry, wherein:the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; andthe multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.