Patent ID: 6782067
Filing Date: 2004-08-24
Classification: G06F

Abstract:
Data reception circuit for receiving a serial input data stream with a high data transfer rate, where the data reception circuit has:(a) a data stream separation circuit for separating the serial input data stream into a plurality of separate data streams with a reduced data transfer rate; (b) a reference clock signal generation circuit for generating a reference clock signal whose clock frequency corresponds to the data transfer rate of the separate data streams; (c) a delay circuit having a delay element chain which comprises a plurality of series-connected delay elements, each delay element having a signal propagation time, the first delay element in the delay element chain receiving the generated reference clock signal, and each delay element outputting a delayed reference clock signal via a signal output in the delay circuit; (d) a first, asynchronously clocked register array which comprises a plurality of register banks, each register bank in the first register array being asynchronously clocked by an associated separate data stream and reading in the delayed reference clock signals from the delay circuit in order to buffer-store a signal change in the separate data stream; (e) a second, synchronously clocked register array which comprises a plurality of register banks, each register bank in the second register array being synchronously clocked by the reference clock signal and reading in and buffer-storing the register content of an associated register bank in the first register array; (f) and a synchronously clocked logic circuit which evaluates the register content buffer-stored in the second register array in order to reconstruct the serial input data stream.