Patent ID: 6538940
Filing Date: 2003-03-25
Classification: G11C

Abstract:
A memory having at least two resistance states, comprising:a memory cell; a first reference memory cell; reference voltage selection circuitry having a first input to receive a first reference voltage, a second input to receive a second reference voltage, a third input to receive a control signal, and an output to provide one of the first reference voltage or the second reference voltage based on the control signal; a first transistor, of a first conductivity type, having a first current electrode coupled to the memory cell, a second current electrode, and a control electrode coupled to the output of the reference voltage selection circuitry for receiving the one of the first reference voltage or the second reference voltage; a second transistor, of a second conductivity type, having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a first voltage terminal, and a control electrode; a third transistor, of the first conductivity type, having a first current electrode coupled to the first reference memory cell, a control electrode coupled to receive the first reference voltage, and a second current electrode; and a fourth transistor, of the second conductivity type, having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the first current electrode of the fourth transistor and to the control electrode of the second transistor, and a second current electrode coupled to the first voltage terminal.