Patent ID: 6677796
Filing Date: 2004-01-13
Classification: H03K,H04B

Abstract:
A system of implementing precision time delays, comprising:a clock input, said clock input being split into at least two separate clock inputs with a specified phase shift therebetween; a delay count providing input to a first lookup table, said first lookup table providing a first output to a first digital to analog converter, the output of said first digital to analog converter being multiplied with at least one of said at least two separate clock inputs thereby providing a first multiplied signal, said first lookup table also providing a second output to a second digital to analog converter, the output of said second digital to analog converter being multiplied with a second of said at least two separate clock inputs to provide a second multiplied signal; an addition and output means to add said first multiplied signal to said second multiplied signal; a variable threshold, said variable threshold receiving as one input the output of said addition and output means; and a second lookup table, said second lookup table's output providing a second input to said variable threshold, thereby enabling a desired delayed output signal from said variable threshold.