Patent ID: 6724220
Filing Date: 2004-04-20
Classification: G06F,G06G,H03B,H03K

Abstract:
A circuit comprising:a plurality of programmable analog circuit blocks configured to provide at least one of a plurality of analog functions; a plurality of programmable digital circuit blocks configured to provide at least one of a plurality of digital functions; a routing matrix configured to couple a subset of said plurality of programmable analog circuit blocks to a first subset of said plurality of programmable circuit blocks, at least a first one of said programmable analog circuit blocks being coupled to at least a first one of said programmable digital circuit blocks; a programmable interconnect structure comprising said routing matrix and a bus independent of said routing matrix coupling said routing matrix to said plurality of programmable analog circuit blocks and said plurality of programmable digital circuit blocks, and; said bus coupling analog input/output data and digital input/output data for said plurality of analog circuit blocks and said plurality of digital circuit blocks whereby said coupling is controlled by at least one system clock.