Patent ID: 8701060
Filing Date: 2014-04-15
Classification: G06F

Abstract:
1. A method for providing information relating to a verification of a digital circuit by using a computer, wherein the formal verification comprises verifying that a plurality of properties (P) is valid for a representation (D) of the digital circuit, the method comprising: a) replacing, at least a first input value (s) relating to the representation of the digital circuit by a first free variable (v); b) determining, by using said computer, when at least one of the plurality of properties is valid or invalid after replacing the first input value by the first variable (v); and c) indicating when the at least one of the plurality of properties is valid or invalid wherein the determining when at least one of the plurality of properties is valid or invalid comprises determining when at least one of the plurality of properties is disproved with the first free variable, and wherein the indicating when the at least one of the plurality of properties is valid or invalid comprises indicating that the first input value (s) is covered if at least one of the plurality of properties is disproved.