Patent ID: 6459150
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A semiconductor package of two electronic substrates electrically connected together by solder bumps comprising:a first electronic substrate having a first plurality of conductive pads formed on a first surface insulated from each other by a first insulating material layer, said first electronic substrate further having a first plurality of apertures through said substrate, said first plurality of conductive pads and said first insulating material layer with one aperture corresponds to each conductive pad wherein said first plurality of apertures each having a sidewall coated with an adhesion promoter that is not a part of the first plurality of conductive pads, a second electronic substrate having a second plurality of conductive pads formed on a second surface insulated from each other by a second insulating material layer, said first plurality being equal to or different than said second plurality, one of said first and second electronic substrates being a silicon wafer while the other being a printed circuit board (PCB), a first plurality of solder bumps mechanically and electrically connecting said first plurality of conductive pads to said second plurality of conductive pads, and wherein said first plurality of solder bumps each filling one of said first plurality of apertures to form a first plurality of conductive plugs.