Patent ID: 8825727
Filing Date: 2014-09-02
Classification: G06F

Abstract:
1. A computer implemented method for driving signals to an adder, the computer implemented method comprising: a target system receiving general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision; the target system setting a first set of input registers to be a target of memory mapped registers; the target system using a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input; the target system writing the adder result to a storage array in memory, wherein the adder result is the sum of the inputs and the adder result is placed in the storage array as indexed by a storage array index; the target system incrementing a first memory address by the broad-based adder size, wherein an increment corresponds to the precision; the target system incrementing the storage array index corresponding to the storage array; the target system determining whether no unsummed addends remain; and responsive to a determination that no unsummed addends remain, the target system summing the storage array in memory to obtain a final sum.