Patent ID: 8823166
Filing Date: 2014-09-02
Classification: H01L

Abstract:
1. An apparatus, comprising: a semiconductor substrate having at least one input/output terminal on a surface thereon, the input/output terminal having a terminal width; a passivation layer overlying the semiconductor substrate and the at least one input/output terminal thereon; an opening in the passivation layer exposing a portion of an upper surface of the at least one input/output terminal; a pillar disposed over the at least one input/output terminal comprising: a bottom portion comprising an under-bump metallization layer having a bottom width less than or equal to the terminal width, the bottom portion overlying the passivation layer and extending into the opening and contacting the input/output terminal; an upper portion having a first width; and a base portion disposed on the bottom portion having a second width greater than the first width, wherein the second width is greater than the bottom width and the terminal width, and the upper portion is disposed on an upper part of the base portion.