Patent ID: 6531330
Filing Date: 2003-03-11
Classification: G02F,H01L

Abstract:
A method of fabricating a thin film transistor (TFT) flat panel display, comprising:(a) providing a substrate which has a first conductive layer, a first insulating layer and a semiconductor layer sequentially formed thereon; (b) patterning the semiconductor layer, the first insulating layer and the first conductive layer to form a scanning line structure, a gate pad structure and a gate structure; wherein the gate pad structure is formed at one end of the scanning line structure and the gate structure is formed at one side of the scanning line structure and extends to the gate structure; (c) forming a passivation layer to cover the scanning line structure, the gate pad structure, the gate structure; (d) patterning the passivation layer so as to form a first opening and a second opening on the gate structure and a third opening on the gate pad structure to expose the semiconductor layer; (e) sequentially forming a doping silicon layer and a second conductive layer on the substrate; (f) patterning the second conductive layer and the doping silicon layer to form a signal line perpendicular to the scanning line structure and a source and a drain over the gate structure; wherein a channel is defined between the source and the drain on the gate, and the patterned doping silicon layers of the source and drain over the gate structure is electrically connected to the semiconductor layer through the first and second openings respectively; (g) patterning the semiconductor layer and the insulating layer on the gate pad structure and removing the semiconductor layer and the insulating layer in the third opening to expose the first conductive layer; (h) forming an electrode layer on the substrate, covering the source, the drain and the gate pad structure; and (i) patterning the electrode layer to form a pixel electrode electrically connected to the drain.