Patent ID: 9059308
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method of forming a structure on a semiconductor substrate comprising: forming on the semiconductor substrate, a first sacrificial gate, a second sacrificial gate, and a third sacrificial gate located between the first sacrificial gate and the second sacrificial gate, wherein a region of the semiconductor substrate between an outer sidewall of the first sacrificial gate and an outer sidewall of the second sacrificial gate does not contain an isolation structure; forming spacers on sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate; forming a first source/drain on the semiconductor substrate between the first sacrificial gate and the third sacrificial gate, and a second source/drain on the semiconductor substrate between the second sacrificial gate and the third sacrificial gate; forming a middle of line (MOL) liner on the first source/drain and the second source/drain, the MOL liner having an upper surface that is substantially flush with an upper surface of the third sacrificial gate; removing the third sacrificial gate to form a dummy recess region; and filling the dummy recess region with insulating material thereby creating an insulating region between the first sacrificial gate and the second sacrificial gate, the insulating region having an upper surface that is substantially flush with the upper surface of the MOL liner; removing the first sacrificial gate and the second sacrificial gate selective to the exposed insulating region, the MOL liner, and the spacers to form gate recesses; and forming metal gates in the gate recesses.