Patent ID: 8010876
Filing Date: 2011-08-30
Classification: G06F,G11C

Abstract:
1. A method of facilitating reliable access of flash memory comprising the steps of: (a) determining whether data is to be read out or write in; (b) if the result of step (a) is to be write-in, coding a number of N write-in data to generate a number of K extra data, generating a first error correction code (ECC) by using an error-correcting operation to the N write-in data and K extra data, and storing the N write-in data and the generated K extra data into a data area of a target flash-memory page and the first ECC into a spare area of the target flash-memory page; and (c) if the result of step (a) is to be read out, allocating a plurality of counters in a main memory; (d) each bit in the data area of the target flash-memory page corresponding to a counter for accumulating a number of differences between the first and a second error correction codes (ECCs) associated to the target flash-memory page; (e) reading data from the data area of the target flash-memory page to generate the second ECC and reading the first ECC from the spare area of the target flash-memory page, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting a number of M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data by using a reverse operation of the original adopted operation of coding in step (b).