Patent ID: 6545311
Filing Date: 2003-04-08
Classification: B82Y,G11C,H01L

Abstract:
A nonvolatile memory element comprising:a semiconductor substrate; a first well region of a first conductivity type formed in the semiconductor substrate; a second well region of a second conductivity type formed in the semiconductor substrate; a source region of the second conductivity type formed in the first well region to be coupled to a source line; a drain region of the second conductivity type formed in the first well region to be coupled to a data line; a first insulating film formed on a part of a principal surface of the first well region between the source region and the drain region; a second insulating film formed on a principal surface of the second well region; a gate electrode formed on the first and second insulating films; a first region formed in the second well region to be coupled to a word line; and a second region formed in the first well region to feed a potential to the first well region; wherein a potential of the source region is set relatively higher than potentials of the first region, the second region and the drain region when electrons accumulated in the gate electrode are to be discharged.