Patent ID: 6038673
Filing Date: 2000-03-14
Classification: G06F,Y02D

Abstract:
A computer system comprising:a central processing unit (CPU);a memory sub-system that includes DRAM devices coupled to the CPU, the CPU selectively accessing information stored in the DRAM devices;logic circuitry that assigns the DRAM devices to active, standby, or nap pools based on temporal access of each device by the CPU, the active, standby, and nap pools corresponding to power consumption states of the DRAM devices; andmeans for storing an active pool size to define a maximum number of devices of the active pool, and a standby pool size to define a maximum number of devices of the standby pool;wherein the logic circuitry includes a stack structure associated with the active and standby pools in which a most recently accessed (MRA) device is placed in the active pool at a top-of-stack (TOS) position, a least-recently accessed (LRA) device in the active pool being evicted to the standby pool when the active pool is full and the CPU accesses another device, which is neither assigned to the standby nor nap pools.