Patent ID: 7890708
Filing Date: 2011-02-15
Classification: G06F

Abstract:
1. An apparatus, comprising: a shared bus configured to support split transactions, the shared bus including a data bus; a plurality of processors coupled to the shared bus, each processor configured to issue read and write requests directed to cache lines in a memory address space, and each processor including a local cache and further configured to snoop read and write requests issued by other processors coupled to the shared bus, wherein each processor is further configured to issue cache-to-cache data transfers to forward data from cache lines that are cached in the local cache of such processor to other processors in response to snooping read requests issued by such other processors and directed to such cache lines, and to issue write requests to write back modified data to a memory; a chipset coupled to the shared bus and configured to forward read requests issued by processors that are directed to cache lines that are not cached in any local cache to a memory, and to issue deferred read data transfers over the data bus to return such cache lines to such processors when such cache lines are provided to the chipset by the memory; a first queue disposed in the chipset and configured to temporarily queue pending cache-to-cache data transfers and write data transfers prior to transmission over the data bus; a second queue disposed in the chipset and configured to temporarily queue pending deferred read data transfers prior to transmission over the data bus; read deferral logic disposed in the chipset and coupled to the first and second queues, the read deferral logic configured to move a read data transfer initially queued in the first queue from the first queue to the second queue upon detecting that the read data transfer is a deferred read data transfer; and data bus scheduling logic disposed in the chipset and coupled to the first and second queues, the data bus scheduling logic configured to schedule the output of pending transfers queued by the first and second queues, the data bus scheduling logic configured to provide uncontested priority to data transfers pending in the second queue over data transfers pending in the first queue such that uncontested priority is provided to a first deferred read data transfer over a second cache-to-cache data transfer that is ready and pending concurrently with the first deferred read data transfer.