Patent ID: 6393594
Filing Date: 2002-05-21
Classification: G01R

Abstract:
A method of testing an integrated circuit, said method comprising the steps of:providing a test substrate which is manufactured by a same particular production technology for which said integrated circuit is designed; embedding a pattern generator for generating test data and a result checker for comparing output data on said test substrate; selectively embedding isolated portions of circuitry of said integrated circuit onto said test substrate; applying test data from said pattern generator to said isolated portions of circuitry under a first operating condition; selectively recording the data output from said isolated portions of circuitry into said result checker; subjecting said isolated portions of circuitry to testing by applying test data from said pattern generator to said isolated portions of circuitry under a second operating condition; detecting errors in said isolated portions of circuitry with said result checker by comparing data output from said isolated portions of circuitry with said selectively recorded data output, such that said integrated circuit is tested by subsets, independently of testing said integrated circuit in its entirety.