Patent ID: 8754679
Filing Date: 2014-06-17
Classification: H03K

Abstract:
1. A power-on reset (POR) circuit comprising: a first transistor having a source coupled to a first supply voltage and a gate coupled to a second supply voltage; a second transistor having a drain coupled to the second supply voltage and a gate coupled to a drain of the first transistor, wherein the second transistor is a depletion mode transistor, and wherein a channel of the second transistor is pinched off when the gate of the second transistor is at a voltage close to the first supply voltage; a resistor having a first terminal coupled to the source of the second transistor and a second terminal coupled to the drain of the first transistor; a discharge capacitor having a terminal coupled to the drain of the first transistor; and a trigger circuit having an input coupled to receive from the second terminal of the first resistor and the terminal of the discharge capacitor, for producing an output voltage representative of a power-on reset signal in response to an interruption of the first supply voltage.