Patent ID: 7016238
Filing Date: 2006-03-21
Classification: G11C

Abstract:
1. A semiconductor memory device in which memory cells arranged in a column direction are divided into a plurality of local blocks, in which data is read or written by the local block, and in which each local block has a write amplifier circuit for writing data into a memory cell, the write amplifier circuit including: a first transistor to an input terminal of which a first write signal line is connected, a first output terminal of which is grounded, and a second output terminal of which is connected to a first terminal of a memory cell included in the local block; a second transistor to an input terminal of which a second write signal line is connected, a first output terminal of which is grounded, and a second output terminal of which is connected to a second terminal of a memory cell included in the local block; a third transistor a first output terminal of which is connected to the second output terminal of the first transistor, a second output terminal of which is connected to power supply, and an input terminal of which is connected to the input terminal of the second transistor; and a fourth transistor a first output terminal of which is connected to the second output terminal of the second transistor, a second output terminal of which is connected to the power supply, and an input terminal of which is connected to the input terminal of the first transistor.