Patent ID: 7626880
Filing Date: 2009-12-01
Classification: G06F,G11C,Y02D

Abstract:
1. A memory device having a memory core, the memory device comprising: a clock receiver circuit to receive an external clock signal; a control interface to receive a command that specifies a read operation to the memory device; a data interface to transfer data between the memory device and an external set of signal lines, including a receiver circuit to receive write data after the memory device receives a command that specifies a write operation; a delay locked loop circuit, coupled to the clock receiver circuit, to generate an internal clock signal using the external clock signal, wherein the memory device is configured to provide the internal clock signal to the receiver circuit in response to receipt of the command that specifies the write operation; a read pipeline circuit to provide read data accessed from the memory core to the data interface in response to receipt of the command that specifies the read operation; and a circuit to provide the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.