Patent ID: 8065645
Filing Date: 2011-11-22
Classification: G06F,H03K

Abstract:
1. A computer implemented sequential logic circuit design method comprising: using a plurality of basic logic circuits to form a pipeline in which flip-flops and latches are inserted between basic logic circuits on the basis of a target cycle time; preparing a circuit description as a net list of the sequential circuit including the flip-flops and latches; inputting the prepared net list; deleting by the computer flip-flop and latch circuits from the prepared net list and inserting for deletions either a signal inversion means for negative logic or a non-inverting logic for positive logic for the sequential logic circuit to be designed to generate a resultant net list; extracting by the computer, from said resultant net list, an optimal point or points whereat skew tolerance of one or more basic logic gates is a maximum; adding by the computer a latch conversion circuit to the one or more basic logic gates for which skew tolerance is determined to be a maximum, the adding step converting a basic logic circuit to a latch conversion circuit; and generating a new net list of the sequential circuit including added latch conversion circuit or circuits to produce a sequential circuit which maximizes skew tolerance and minimizes through delay.