Patent ID: 6327693
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A computer implemented method for optimizing placement and routing of an integrated circuit design comprising:designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region; andautomatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through a logically equivalent component placed at a different location; andselecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.