Patent ID: 9030227
Filing Date: 2015-05-12
Classification: H03K

Abstract:
1. A method comprising: partitioning first and second integrated circuit dies into a plurality of logic regions, the first and second integrated circuit dies each including a spare logic region, wherein corresponding logic regions of the first and second integrated circuit dies are coupled using interconnects on a multi-chip package that includes the first and second integrated circuit dies; forming a plurality of logic groups, each logic group comprising a configurable logic region on the first integrated circuit die that performs a first user logic function and a corresponding configurable logic region on the second integrated circuit die that performs a second user logic function, wherein the logic regions of the logic group are coupled using the interconnects on the multi-chip package; evaluating the plurality of logic groups to identify a defective logic group; and in response to identifying the defective logic group, repairing the defective logic group by configuring the first and second integrated circuit dies to stop using the defective logic group and use a spare logic group comprising the spare logic regions of the first and second integrated circuit dies, wherein the spare logic regions are coupled using spare logic region interconnects on the multi-chip package.