Patent ID: 6400639
Filing Date: 2002-06-04
Classification: G11C

Abstract:
A memory decoder system, comprising:a matrix of memory cells, arranged into rows and columns; a plurality of wordline drivers corresponding to each row in said matrix; a group of wordline driver-decoder blocks, each one of said wordline driver-decoder blocks containing a subset of said plurality of wordline drivers therein; and each of said wordline driver-decoder blocks being separated by a row control block, said row control block including control circuitry for controlling said wordline drivers; wherein, for any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of said given wordline driver-decoder block; and a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of said given wordline driver-decoder block.