Patent ID: 7382672
Filing Date: 2008-06-03
Classification: G11C

Abstract:
1. A sense amplifier circuit for use in a memory circuit including multiple pairs of differential bit lines, the sense amplifier circuit comprising: a read and write port for selectively accessing the sense amplifier circuit in response to a first control signal; a differential load connected between a first voltage source supplying a first voltage and a given pair of differential bit lines, the differential load being selectively activated in response to a second control signal, the differential load comprising first and second PMOS transistor devices, sources of the first and second PMOS transistor devices connecting to the first voltage source, gates of the first and second PMOS transistor devices receiving the second control signal, a drain of the first PMOS transistor device connecting to a first bit line of the given pair of differential bit lines, and a drain of the second PMOS transistor device connecting to a second bit line of the given pair of differential bit lines; a second stage sense amplifier connected to the given pair of differential bit lines, the second stage sense amplifier comprising first and second NMOS transistor devices, a drain of the first NMOS transistor device connecting to the first bit line of the given pair of differential bit lines, a drain of the second NMOS transistor device connecting to the second bit line of the given pair of differential bit lines, a gate of the first NMOS transistor device being connected to the drain of the second NMOS transistor device, a gate of the second NMOS transistor device being connected to the drain of the first NMOS transistor device, and sources of the first and second transistor devices connecting to a second voltage source supplying a second voltage level; a half-state reference generator connected to the given pair of differential bit lines, the half-state reference generator generating a reference current which is selectively pulled from one of the bit lines in the given pair of differential bit lines in response to a third control signal, a magnitude of the reference current generated by the half-state reference generator being controlled as a function of a fourth control signal, the half-state reference generator comprising third, fourth and fifth NMOS transistor devices, a drain of the third NMOS transistor device connecting to the first bit line of the given pair of differential bit lines, a source of the third NMOS transistor device being connected to a source of the fourth NMOS transistor device and a drain of the fifth NMOS transistor device, a gate of the third NMOS transistor device receiving a logical complement the third control signal, a drain of the fourth NMOS transistor device connecting to the second bit line of the given pair of differential bit lines, a gate of the fourth NMOS transistor device receiving the third control signal, a source of the fifth NMOS transistor device connecting to the second voltage source, and a gate of the fifth NMOS transistor device receiving the fourth control signal for controlling a magnitude of the reference current; and a pre-charge circuit connected to the given pair of differential bit lines, the pre-charge circuit being operative to set the given pair of differential bit lines to a known voltage level prior to a read or write operation in the memory circuit; wherein the sense amplifier circuit is operative in conjunction with a first stage sense amplifier in the memory circuit, the sense amplifier circuit being configured such that activation of the second stage sense amplifier is delayed relative to activation of the first stage sense amplifier, the delay in activation of the second stage sense amplifier relative to the first stage sense amplifier being controlled at least in part by adjusting a threshold voltage of at least one transistor device in the second stage sense amplifier relative to a threshold voltage of at least one transistor device in the first stage sense amplifier so as to permit a voltage difference of a desired level to develop across the given pair of differential bit lines.