Patent ID: 6191609
Filing Date: 2001-02-20
Classification: G06F,H03K

Abstract:
A programmable logic device, comprising:a plurality of state elements, each having a clock input terminal provided in first and second regions of said programmable logic device, said first and second regions being non-overlapping;a first conductor provided in said programmable logic device within said first region but not in said second region;a second conductor provided in said programmable logic device within said second region, but not in said first region;a first input terminal, coupled to said first conductor, for receiving a first input signal from outside of said programmable logic device;a second input terminal, coupled to said second conductor, for receiving a second input signal from outside of said programmable logic device; anda programmable circuit for selectably coupling said first input signal from said first conductor to said clock input terminals of said state elements provided in said first region and said second input signal from said second conductor to said clock input terminals of said state elements provided in said second region.