Patent ID: 6215170
Filing Date: 2001-04-10
Classification: H01L,H03K

Abstract:
An integrated circuit comprising:first and second supply terminals coupled to a substrate;a plurality of semiconductor layers formed on said substrate and having a set of integrated circuit components formed therein;a circuit unit of said set of components operable to be configured in one of a number of configurations in response to a signal;a removable link of said set of components having a first link terminal coupled to said first supply terminal, and a second link terminal;a buffer of said set of components having a buffer input terminal coupled to said second link terminal and a buffer output terminal coupled to said circuit unit, said buffer operable to generate said signal at said buffer output terminal;an insulator on a portion of said substrate being patterned to expose first and second direct substrate contacts, said first contact being coupled to said second link terminal and said second contact being coupled to said second supply terminal formed on said insulator between said first and second contacts;a first region of a first conductivity type in a surface area of said substrate under said first contact; anda second region of a second conductivity type formed under said insulator and extending past said second contact, said second region is laterally spaced from said first region, and said first and second regions and insulator form a capacitive element in parallel with a diode within said integrated circuit.