Patent ID: 9170639
Filing Date: 2015-10-27
Classification: G06F,Y02D

Abstract:
1. A computing system for saving power in a memory subsystem that uses memory access idle timer to enable low power mode and memory scrub operation of a memory scrub engine within the memory subsystem of the computing system, the computing system comprising: one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage devices and program instructions which are stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the program instructions comprising: program instructions to determine that the memory subsystem is switched out of low power mode due to a memory scrub operation; and program instructions to bypass an idle timer of the memory subsystem such that the memory subsystem is returned to the low power mode upon completion of the memory scrub operation, wherein the computing system bypasses the low power mode of the idle timer, if the only reason the computing system transitioned to non-idle mode is to perform background scrubbing of memory of the computing system, and wherein, the memory controller of memory maintains a the scrub flag that it clears every time a new non-scrub operation is performed into memory operations queue of the computing system.