Patent ID: 6023739
Filing Date: 2000-02-08
Classification: G06F

Abstract:
An information processing system comprising:a plurality of processors;a plurality of bi-directional buses;a plurality of interconnection nodes, each connection to a different corresponding one of said processors through a corresponding one of said bi-directional buses;a plurality of addressable spaces, each connected, to a different corresponding one of said interconnection nodes through a corresponding one of said bi-directional buses;a common communication bus connected to all of said interconnection nodes for establishing communication paths between all of said processors and all of said addressable spaces through said common bus and said bi-directional buses; each of said interconnection nodes including:a control logic circuit for ensuring priority access by the processor corresponding to said interconnection node to the addressable space corresponding to said interconnection node and for establishing, together with the interconnection nodes corresponding to the other processors through said common communication bus, a hierarchy of priority of access to each of said addressable spaces by processors other than the processor connected to the interconnection node corresponding to the addressable space in question; each said control logic circuit including:a decoder responsive to the content of an address field in instructions programming the corresponding processor for establishing direct access by said corresponding processor to the addressable space corresponding to said interconnection node if the content of said address field designates a location in said addressable space.