Patent ID: 7067431
Filing Date: 2006-06-27
Classification: H01L

Abstract:
1. A method of forming damascene pattern in a semiconductor device, the method comprising: forming an insulating layer on a bottom wiring; forming via holes that expose a part of the bottom wiring by removing the insulating layer selectively; filling insides of the via holes to a prescribed thickness using non-conductive material by forming a non-conductive material layer on the insulating layer in which the via holes are formed and selectively removing the non-conductive material layer to expose the insulating layer and allow the non-conductive material to remain for a prescribed thickness; forming an anti-reflection layer on the via holes and the insulating layer; forming a mask pattern for trench etching in the insulating layer on which the anti-reflection layer is formed; and forming a damascene pattern after forming trenches using the mask pattern.