Patent ID: 6448651
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A semiconductor device having a multi-level metallization, comprising:a semiconductor substrate having an active area; a first insulating layer deposited on the substrate; first and second contact holes formed penetrating the first insulating layer exposing a predetermined surface of the active area; first and second conductive plugs respectively formed on the first and second contact holes; first and second conductive patterns spaced a predetermined distance apart on either side of the second conductive plug, the first conductive pattern being connected to the first conductive plug; an etching prevention layer and a second insulating layer sequentially formed on the first and second conductive patterns and the first insulating layer; a third contact hole formed penetrating the second insulating layer and the etching prevention layer exposing a predetermined surface of the first conductive pattern; a fourth contact hole formed penetrating the second insulating layer and the etching prevention layer exposing the second conductive plug; third and fourth conductive plugs respectively formed on the third and fourth contact holes, the fourth conductive plug directly contacting the second plug; and third and fourth conductive patterns formed on predetermined surfaces of the second insulating layer, the third and fourth conductive patterns being respectively connected to the third and fourth conductive plugs; wherein the fourth conductive plug is narrower than the second conductive plug.