Patent ID: 9166749
Filing Date: 2015-10-20
Classification: H04L

Abstract:
1. A serial data transmission system, comprising: a sending terminal for sending data, a receiving terminal for receiving the data which are sent by said sending terminal, a first connecting capacitor which is connected between said sending terminal and said receiving terminal, and a second connecting capacitor which is connected between said sending terminal and said receiving terminal; wherein, said sending terminal comprises a sending terminal driving unit, and an amplitude detecting unit which is connected to said sending terminal driving unit; said sending terminal driving unit outputs a pair of differential signals according to signals of the received data; said amplitude detecting unit detects changes in amplitudes of the differential signals which are outputted by said sending terminal driving unit, and outputs an indicating signal for indicating whether said sending terminal is properly connected to said receiving terminal; wherein said amplitude detecting unit comprises an amplitude detecting circuit, a reference voltage generating circuit, a reference voltage terminal which is connected to said reference voltage generating circuit and a comparator which is connected to said amplitude detecting circuit and said reference voltage terminal; said amplitude detecting circuit detects the changes in the amplitudes of the differential signals which are outputted by said sending terminal driving unit, and outputs a voltage value into said comparator, wherein said voltage value is directly proportional to the changes in the amplitudes of the differential signals; said comparator compares the voltage value which is outputted by said amplitude detecting circuit with a voltage value of said reference voltage terminal, and outputs the indicating signal for indicating whether said sending terminal is properly connected to said receiving terminal; and said receiving terminal comprises a first resistor which is connected to said first connecting capacitor, and a second resistor which is connected to said second connecting capacitor; and wherein said sending terminal driving unit comprises a first current source, a first FET which is connected to said first current source, a second FET which is connected to said first current source, a third resistor which is connected to said first FET, and a fourth resistor which is connected to said second FET; said amplitude detecting circuit comprises a fourth current source, a fifth current source, a third FET which is connected to said first FET and said third resistor, a fourth FET which is connected to said second FET and said fourth resistor, an eighth FET, a fifth resistor which is connected to said fourth current source, a sixth resistor which is connected to said fifth current source, a seventh resistor which is connected to said fourth FET, an eighth resistor which is connected to said third FET, a ninth resistor which is connected to said third FET, a tenth resistor which is connected to said fourth FET, a third capacitor which is connected to said fifth resistor, and a fourth capacitor which is connected to said sixth resistor; said reference voltage generating circuit comprises a second current source, a third current source, a fifth FET, a sixth FET which is connected to said fifth FET, a seventh FET which is connected to said fifth FET and said sixth FET, an eleventh resistor which is connected to said fifth FET, a twelfth resistor which is connected to said sixth FET, a thirteenth resistor which is connected to said second current source, a fourteenth resistor which is connected to said third current source, a fifteenth resistor which is connected to said thirteenth resistor, a sixteenth resistor which is connected to said fourteenth resistor, a fifth capacitor which is connected to said fifteenth resistor, and a sixth capacitor which is connected to said sixteenth resistor.