Patent ID: 6839786
Filing Date: 2005-01-04
Classification: G11C

Abstract:
1. An information processing system having a plurality of modules of an even number in which each module has at least one semiconductor integrated circuit, and a chipset for controlling the plurality of modules, comprising: a data line having a first termination connected to the chipset and a second termination; a first termination device connected to the second termination of the data line; a clock line divided into a first and a second clock line segments, wherein each clock line segment has a first and a second termination; a second termination device connected commonly to the first terminations of the first and the second clock line segments; and a clock generator connected commonly to the second terminations of the first and the second clock line segments, and for generating a clock signal that is transferred through the first and the second clock line segments, wherein the second termination device and the clock generator are placed such that each of the first and the second clock line segments has a same length as the data line.