Patent ID: 7485954
Filing Date: 2009-02-03
Classification: H01L

Abstract:
1. A stacked dual MOSFET package comprising: a first thermally conductive tab; a high side MOSFET die disposed on the first thermally conductive tab such that a drain of the high side MOSFET die is electrically coupled to the first thermally conductive tab; a second thermally conductive tab disposed in overlaying relationship to the high side MOSFET die and electrically coupled to a source of the high side MOSFET; a low side MOSFET die stacked on the second thermally conductive tab above the high side MOSFET die such that a drain of the low side MOSFET die is electrically coupled to the second thermally conductive tab; a first lead coupled to a gate of the high side MOSFET die; at least one second lead coupled to the first thermally conductive tab; at least one third lead coupled to a source of the low side MOSFET die; a fourth lead coupled to a gate of the low side MOSFET die; and an encapsulant covering portions of the first thermally conductive tab, the high side MOSFET die, portions of the second thermally conductive tab, the low side MOSFET die, and portions of the first lead, the at least one second lead, the at least one third lead, and the fourth lead.