Patent ID: 8098792
Filing Date: 2012-01-17
Classification: G09G,G11C

Abstract:
1. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a first input unit, electrically connected to an (N−1)th shift register stage of the shift register stages for receiving an (N−1)th gate signal of the gate signals, for outputting a first driving control voltage in response to the (N−1)th gate signal; a pull-up unit, electrically connected to the first input unit and an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals in response to the first driving control voltage and a first clock, wherein the Nth gate line is employed to deliver the Nth gate signal; a pull-down circuit, electrically connected to the first input unit and the pull-up unit, for pulling down the first driving control voltage and the Nth gate signal; a second input unit, electrically connected to the (N−1)th shift register stage for receiving the (N−1)th gate signal, for outputting a second driving control voltage in response to the (N−1)th gate signal; a first control unit, electrically connected to the second input unit, for generating a first control signal in response to the second driving control voltage and an auxiliary signal; a waveform-shaping unit, electrically connected to the first control unit and the Nth gate line, for performing a waveform-shaping operation on the Nth gate signal in response to the first control signal; and a first pull-down unit, electrically connected to an (N+1)th shift register stage of the shift register stages for receiving an (N+1)th gate signal of the gate signals, for pulling down the second driving control voltage in response to the (N+1)th gate signal.