Patent ID: 6055659
Filing Date: 2000-04-25
Classification: G01R,H03K

Abstract:
An integrated circuit comprising:A. a semiconductor substrate;B. functional circuitry formed on the substrate for performing normal operating functions of the integrated circuit;C. an output terminal formed on the substrate, coupled to the functional circuitry;D. a test data path formed on the substrate and providing test data;E. memory circuitry formed on the substrate and storing data therein, the memory circuitry having an input selectively connectable to the functional circuitry and to the test data path and having an output;F. test control circuitry formed on the substrate and selectively connecting the memory circuitry input to the functional circuitry and to the test data path; andG. latching output buffer circuitry formed on the substrate and connected between the memory circuitry output and the output terminal, the buffer circuitry including a switch and an output buffer connected in series between the memory circuitry and output terminal and including an input buffer connected in parallel with the output buffer, the input buffer being electrically weaker than the output buffer, the output buffer and input buffer forming a latch circuit.