Patent ID: 6833293
Filing Date: 2004-12-21
Classification: H01L,Y10S

Abstract:
A method for manufacturing a semiconductor device having a buried conductive layer which is connected to one of a source and a drain of a MOS transistor and which extends over a gate electrode of said MOS transistor, said method comprising:forming a first insulating film on a semiconductor substrate; forming a first conductive film as said gate electrode and a second insulating film on said first insulating film, said gate electrode having a width equal to a minimum processing size achievable with a conventional lithographic process technique; forming a third insulating film on the whole surface of said semiconductor substrate having said first insulating film, said first conductive film and said second insulating film formed thereon; selectively etching away said third insulating film so as to form first side wall insulating films including said third insulating film on each of both side faces of said first conductive film and said second insulating film, said selective etching exposing said semiconductor substrate in portions which are not covered with said side wall insulating film and not covered with said first conductive film; diffusing impurities into said exposed portions of said semiconductor substrate so as to form a source and a drain in said semiconductor substrate; forming a second conductive film to be a part of said buried conductive layer on the whole surface of said semiconductor substrate having said first insulating film, said first conductive film, said second insulating film and said side wall insulating film formed thereon; forming a first mask layer on said second conductive film; processing said first mask layer to have a pattern which is separated into both side portions as to said first conductive film; forming a second mask layer on the whole surface of said semiconductor substrate having said first insulating film, said first conductive film, said second insulating film, said side wall insulating film, said second conductive film and said first mask layer formed thereon; selectively etching away said second mask layer so as to leave a pattern of said second mask layer as second side walls on each of both side faces of the pattern of said first mask layer; selectively etching away said second conductive film with the patterns of said first and second mask layers as a mask so as to process said second conductive film into a pattern in which said second conductive film is separated on said second insulating film by an opening between the second side walls smaller than the minimum processing size achievable with the conventional lithographic process technique, and wherein said buried conductive layer includes said second conductive film extending over the gate electrode of the MOS transistor; and ensuring that the opening between the second side walls does not overlap either of the first sidewall insulating films or either of the source and drain.