Patent ID: 6343037
Filing Date: 2002-01-29
Classification: G11C

Abstract:
A column redundancy circuit for a semiconductor memory, comprising:a column decoder for receiving a predecoded column address and an internal clock signal, and for outputting a normal column selecting signal and a redundancy column selecting signal; a column redundancy unit for outputting a redundancy enable signal in accordance with a column address, a row address, and a state of fuse; and a memory array including a plurality of array units having a plurality of normal memory cells and a plurality of redundancy memory cells, and a switch unit selecting and outputting one of a normal data stored in the normal memory cell according to the normal column selecting signal or a redundancy data stored in the redundancy memory cell according to the redundancy column selecting signal, wherein the data selected by the switch unit is outputted to a main amplifier via a global input/output line in accordance with the redundancy enable signal.