Patent ID: 7293221
Filing Date: 2007-11-06
Classification: G06F,G11C

Abstract:
1. A method for detecting transfer errors in an address bus, comprising: generating a first address parity using a memory address; scrambling at least two data error-correction-code (ECC) check bits using the first address parity; and writing the data ECC check bits to a memory, the data ECC check bits enabling detection of transfer errors in the address bus; generating a second address parity using the memory address; reading the data ECC check bits from the memory; and unscrambling the at least two data ECC check bits using the second address parity, the data ECC check bits enabling detection of transfer errors in the address bus; wherein the method operation of unscrambling the at least two data ECC check bits is selected from one of using an exclusive-OR function and using an exclusive-NOR function.