Patent ID: 6768675
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A stack-gate flash memory array, comprising:a plurality of transistors, said transistors being arranged in a plurality of rows and a plurality of columns, every two transistors in a same said row being a pair of transistors, one of the source/drain terminals of said pair of transistors being coupled each other, the other source/drain terminal of one of said pair of transistors being coupled to a first bit line, the other source/drain terminal of the other one of said pair of transistors being coupled to a second bit line; and a plurality of isolated transistors, each said isolated transistor corresponding to one of said pair transistors in a same said row, one of the drain/source terminals of each said isolated transistor being coupled to the drain/source terminal where said pair of transistors is coupled each other, the gate terminal of one of said pair transistor being coupled to a word line, the gate terminal of the other one of said pair transistor being coupled to a word line via the gate terminal of said isolated transistor.