Patent ID: 6259588
Filing Date: 2001-07-10
Classification: H03K

Abstract:
An field programmable gate array for implementing reconfigurable logic comprising:a physical pad which transfers signals out of the field programmable gate array;an output buffer that drives signals at a first logic level or a second logic level and outputting a current;a clocked resetable delay element that determines a threshold amount of time;an overcurrent error detection circuit that compares the voltage level on the pad in the field programmable gate array with the voltage level being driven by the output buffer in order to detect an overcurrent error condition, and when the voltage level on the pad is not the same voltage level as the voltage level being driven by the output buffer for an amount of time greater than the threshold time determined by the clocked resetable delay element, the overcurrent error detection circuit determines that an overcurrent error condition exists;an overcurrent protection circuit responsive to the overcurrent error detection circuit where the overcurrent protection circuit protects the field programmable gate array by limiting the current when the overcurrent error condition exists.