Patent ID: 7254764
Filing Date: 2007-08-07
Classification: G01R,G06F

Abstract:
1. A method of generating a selected test pattern sequence to be used in transient power supply current testing to detect delay faults in a semiconductor integrated circuit, the method comprising: a fault list preparing step that prepares a stored fault list of delay faults that include gate delay faults and open faults in the semiconductor integrated circuit under test; a fault selection step that selects a stored delay fault from the stored fault list; a test pattern sequence generating step that generates by implication operation the selected test pattern sequence including an initializing test pattern and a propagation test pattern to be applied to the semiconductor integrated circuit, wherein the initializing test pattern is generated such that it activates the selected delay fault when applied to the semiconductor integrated circuit to provide an initial value of a transition signal at a location corresponding to the selected delay fault and wherein the propagation test pattern is generated such that it causes the transition signal to propagate to an output of a logic gate having an input connected to the location corresponding to the selected delay fault; and a registering step that registers the selected test pattern sequence in a selected test pattern sequence list.