Patent ID: 7936208
Filing Date: 2011-05-03
Classification: G05F

Abstract:
1. A CMOS circuit comprising: a first bias circuit comprising a diode connected circuit configured to provide a first voltage that tracks process, voltage and temperature variations of a first semiconductor device; and a first current mirror circuit coupled to the first diode connected circuit to generate a first output bias voltage that is coupled to the first semiconductor device and biases the body of one or more first semiconductor devices from the first output bias voltage; the first output bias voltage compensating for the process, voltage and temperature variations; and a second bias circuit coupled to the first bias circuit, the second bias circuit comprising a second diode connected circuit configured to provide a second voltage that tracks process, voltage and temperature variations of one or more second semiconductor devices; and a second current mirror circuit coupled to the second diode connected circuit to generate a second output bias voltage that is coupled to the second semiconductor device and biases the body of the one or more second semiconductor devices from the second output bias voltage; the second output bias voltage compensating for the process, voltage and temperature variations, wherein the one or more first semiconductor devices comprise one or more NMOS devices and the one or more second semiconductor devices comprises a one or more PMOS devices, and wherein the first output bias voltage is provided to the second bias circuit and the second output bias voltage is provided to the first bias circuit to increase sensitivity to process, voltage and temperature variations.