Patent ID: 7490230
Filing Date: 2009-02-10
Classification: G06F

Abstract:
1. An apparatus for selecting one of N fetch addresses associated with N corresponding threads for providing to an instruction cache for fetching instructions therefrom in a multithreading microprocessor that concurrently executes the N threads, wherein a subset of the N threads may request to fetch instructions in a selection cycle, the apparatus comprising: a first input, for receiving a first corresponding N-bit value specifying which of the N threads was last selected to fetch instructions, wherein only one of said N bits of said first value corresponding to said last selected thread is true; a second input, for receiving a second corresponding N-bit value, each of said N bits of said second value being false if said corresponding one of the N threads is requesting to fetch instructions; a barrel incrementer, coupled to said first and second inputs, configured to add said second value to a 1-bit left-rotated version of said first value to generate a sum and a carry-out bit, wherein said barrel incrementer includes said carry-out bit as a carry-in bit of the add to generate the sum; and combinational logic, coupled to said barrel incrementer, configured to generate a third corresponding N-bit value specifying which of the N threads is selected next to fetch instructions, said third value comprising a Boolean AND of said sum and an inverted version of said second value, wherein only one of said N bits of said third value corresponding to said next selected one of the N threads is true.