Patent ID: 6187624
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method for fabricating an array of capacitors on a dynamic random access memory (DRAM) device comprising the steps of:providing a semiconductor substrate having field oxide areas surrounding device areas and said device areas having semiconductor devices;depositing a first insulating layer over said device areas and said field oxide areas;planarizing said first insulating layer;etching first contact openings for bit lines and for an array of capacitor node contacts in said first insulating layer to said device areas;depositing a first polysilicon layer on said first insulating layer sufficiently thick to fill said first openings and etching back said first polysilicon layer to said first insulating layer to form bit-line plugs and capacitor node contact plugs in said first openings;depositing a second insulating layer over said first insulating layer and over said bit-line plugs and said capacitor node contact plugs;etching second openings in said second insulating layer to said bit-line plugs for bit lines;depositing a polycide layer over said second insulating layer and patterning to form said bit lines over said bit-line plugs;forming a planar third insulating layer over said bit lines;depositing an etch-stop layer on said third insulating layer;etching third openings in said etch-stop layer and in said third and said second insulating layers to said capacitor node contact plugs;depositing a second polysilicon layer sufficiently thick to fill said third openings and etching back said second polysilicon layer to said etch-stop layer to form polysilicon plugs to said capacitor node contact plugs;depositing a fourth insulating layer on said etch-stop layer, wherein said fourth insulating layer is a low-dielectric material;forming an array of recesses in said fourth insulating layer aligned over and to said polysilicon plugs that contact said array of capacitor node contacts plugs;depositing a conformal first conducting layer and polishing back to form capacitor bottom electrodes in said recesses;forming an interelectrode dielectric layer on said bottom electrodes;depositing and patterning a second conducting layer to form capacitor top electrodes;depositing a fifth insulating layer to electrically insulate and to complete said array of capacitors on said DRAM device.