Patent ID: 6070227
Filing Date: 2000-05-30
Classification: G06F

Abstract:
A computer system comprising:a processor that generates a logical address to facilitate memory accesses;a main memory unit that includes a plurality of banks, wherein each bank of the plurality of banks includes a page buffer, and the main memory unit is addressed via bank, row and column bits;a cache memory coupled to the processor, the cache memory holding a subset of contents of the main memory unit, wherein the cache memory is organized into sets of cache lines that are addressed by an index portion of the logical address, and a tag portion of the logical address is associated with each cache line;a memory controller coupled between the main memory unit and the cache memory, wherein the memory controller generates from the logical address the bank, row, and column bits required by the main memory unit, and one or more bits from the tag portion of the logical address are used to generate a first set of one or more bank bits, thereby increasing the probability that a cache line cast out and a corresponding cache line read to the same cache line as the cache line cast out access different page buffers of the main memory unit.