Patent ID: 7734974
Filing Date: 2010-06-08
Classification: G01R

Abstract:
1. An integrated circuit comprising: a plurality of circuit blocks; a test controller responsive to test commands received from outside said integrated circuit to perform test operations upon said plurality of circuit blocks; a plurality of serial scan chain loops, each one of said plurality of serial scan chain loops extending from said test controller to a respective one of said plurality of circuit blocks to communicate test signals therewith and back to said test controller, wherein said test controller comprises multiplexing circuitry coupled to said plurality of serial scan chain loops and responsive to configuration commands to link together selected serial scan chain loops of said plurality of serial scan chain loops to form a combined serial scan chain loop having an input connection and an output connection such that test signals can be serially scanned through said combined serial scan chain loop to provide communication of said test signals between a test device external of said integrated circuit and those of said plurality of circuit blocks corresponding to said selected serial scan chain loops; and a power controller coupled to at least some of said plurality of circuit blocks and responsive to power commands to selectively place one or more of said plurality of circuit blocks in a power saving state in which test signals cannot be communicated.