Patent ID: 6351806
Filing Date: 2002-02-26
Classification: G06F

Abstract:
In a processor having a plurality of general purpose registers and an instruction register for holding a currently executed instruction, each of said general purpose registers having a register code, said processor being coupled to a memory, said processor having an instruction set, at least an instruction of said instruction set having an operation code (opcode), a destination field, and a source field, said opcode being unique for said instruction, said destination field selecting the content of a first general purpose register as the destination operand for said instruction, said source field selecting the content of a second general purpose register as the source operand for said instruction, a method of specifying a new source for operands besides said general purpose register for said instruction, said method comprising the steps of:loading said instruction into said instruction register; and upon recognizing a pre-specified bit pattern in said instruction, outside said opcode field, in said instruction register, fetching immediate data from said memory to be used as an operand for said instruction.