Patent ID: 6806577
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A device comprising a memory cell, wherein said memory cell comprises:a semiconductor substrate; a switching device disposed over said semiconductor substrate; a charge storage device in electrical communication with said switching device; a plurality of topographic structures comprising: at least one first topographic structure including conductive lead lines deposited over said semiconductor substrate and in electrical communication with said switching device, said at least one first topographic structure including a top surface; and a plurality of second topographic structures with top surfaces thereon, said top surfaces of said second topographic structures generally co-planar with said top surfaces of said at least one first topographic structure; at least one geometrically simple array comprising at least a portion of said topographic structures such that: a substantially continuous straight-edged periphery around said array is defined by said plurality of topographic structures; and no portion of said plurality of second topographic structures within said array extends laterally beyond said periphery; a gridded valley disposed within said array and including an interconnected series of spaces between adjacent topographic structures, wherein: a lateral distance defining a width of any one of said series of spaces is substantially equal to that of another of said series of spaces within said gridded valley; the longest linear dimension of each of said series of spaces is no longer than the longest dimension of any of said second topographic structures; and no intersection defined by a crossing between any two of said interconnected series of spaces includes uninterrupted linear dimensions; and a planarization layer deposited over said substrate such that it is disposed at least within said gridded valley and laterally surrounds said plurality of topographic structures.