Patent ID: 6967868
Filing Date: 2005-11-22
Classification: G11C

Abstract:
1. A flash memory device comprising: a plurality of main bit lines; a plurality of redundant bit lines; a plurality of first page buffers respectively organized as a plurality of first page buffer groups which are connected to main bit lines; a plurality of second page buffers respectively organized as a plurality of second page buffer groups which are connected to the redundant bit lines; each of the first and second page buffers including an output P/F terminal to provide pass/fail data; a plurality of fuses corresponding to the pluralities of the first and second page buffer groups, respectively, each of the fuses having one end commonly connected to the P/F terminals in a corresponding page buffer group and the other end connected to a signal line; and a pass/fail check circuit to determine an overall pass/fail signal based upon a signal on the signal line.