Patent ID: 9214219
Filing Date: 2015-12-15
Classification: G11C

Abstract:
1. A memory device comprising: a plurality of memory arrays arranged in multiple rows and multiple columns; a plurality of sense-amplifier stripes, a respective one of the sense amplifier stripes arranged between adjacent ones of the rows of memory arrays, each sense-amplifier stripe including collections of sense amplifiers, a respective one of the collections arranged between adjacent ones of the rows of memory arrays on each column of memory arrays; a plurality of wordline-driver stripes, a respective one of the wordline driver stripes arranged between each adjacent pair of the columns of memory arrays, each wordline driver stripe including a plurality of wordline driver sets, a respective one of the wordline driver sets arranged between adjacent ones of the columns of memory arrays on each row of memory arrays, each intersection of a sense-amplifier stripe and a wordline-driver stripe substantially defining an intersection region; a plurality of equalization control circuits arranged, respectively, substantially within individual ones of a first subset of the intersection regions and absent from a second subset of the intersection regions, each equalization control circuit to collectively control a bitline equalization operation of at least one adjacent collection of sense amplifiers; and a plurality of sense control circuits arranged, respectively, substantially within individual ones of the second subset of the intersection regions and absent from the first subset of the intersection regions, each sense control circuit to collectively control a sense operation of at least one adjacent collection of sense amplifiers.