Patent ID: 7113429
Filing Date: 2006-09-26
Classification: G11C,H01L

Abstract:
1. A method for operating a NOR memory array, comprising: programming one or more vertical NOR flash cells extending outwardly from a substrate and separated by trenches, wherein each NOR flash cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a first gate insulator in the trenches along rows of the NOR flash cells, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the NOR flash cells the trench between column adjacent NOR flash cells includes a pair of floating gates, each one opposing the channel regions of the NOR flash cell on a respective side of the trench, wherein the array includes a number of sourcelines formed in a bottom of the trenches between rows of the NOR flash cells and coupled to the source regions of NOR flash cells along rows of the vertical NOR flash cells, wherein along rows of the NOR flash cells, the first source/drain region of each NOR flash cell in column cells couples to the sourceline in a shared trench, such that each NOR flash cell neighboring the shared trench shares a common sourceline, and wherein programming the one or more vertical NOR flash cells includes: wherein applying the first, second and gate potentials to the one or more vertical NOR flash cells includes creating a hot electron injection into the floating gate of the one or more NOR flash cells.