Patent ID: 7468323
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. A process comprising: forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; forming a first recess having a first lateral dimension at a bottom portion of the first dielectric layer in contact with the substrate, and having a second lateral dimension at a top portion of the second dielectric layer; forming a conductive structure in the first recess having vertical sidewalls with the first lateral dimension having a value approximately equal to a value of the second lateral dimension; first wet etching to expose a first portion of the conductive structure by removing at least a portion of the second dielectric layer; first rinsing the conductive structure; and second non-wet etching to expose a second portion of the conductive structure by removing at least a remaining portion of the first dielectric layer and exposing at least a portion of the substrate.