Patent ID: 6741511
Filing Date: 2004-05-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells arranged in rows and columns; a plurality of sense amplifiers arranged corresponding to the columns of the memory cells, and sensing and amplifying data of the memory cells in corresponding columns when activated; column selection control circuitry for holding a column select instruction signal in an active state in accordance with a test operation mode instruction signal, and generating said column select instruction signal in a one-shot pulse form in accordance with a column access instruction signal in a normal operation mode when said test operation mode instruction signal is deactivated; column selection circuitry for connecting the sense amplifier arranged corresponding to a selected column to an internal data bus in response to said column select instruction signal; write circuitry for driving said internal data bus in accordance with a write instruction signal; and write control circuitry for holding said write instruction signal in an inactive state when said test operation mode instruction signal is activated.