Patent ID: 6365445
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method for fabricating a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, the method including the steps of:A. depositing a layer of dielectric material on said buried insulating material; B. patterning said layer of dielectric material to form a dielectric island having a top surface and having a height of a thickness of said layer of dielectric material; C. forming an opening through said buried insulating material at a location away from said dielectric island; D. depositing an amorphous semiconductor material to fill said opening through said buried insulating material and to surround said dielectric island; E. polishing said amorphous semiconductor material until said top surface of said dielectric island is exposed and such that said amorphous semiconductor material surrounds said dielectric island; F. depositing a layer of said amorphous semiconductor material on top of said dielectric island and on top of said amorphous semiconductor material surrounding said dielectric island; G. recrystallizing said amorphous semiconductor material surrounding said dielectric island and said layer of said amorphous semiconductor material to form a substantially single crystal structure of semiconductor material; wherein said semiconductor material disposed on said dielectric island has a thickness that is less than that of said semiconductor material that extends above said height of said dielectric island to the sides of said dielectric island; H. forming a gate dielectric and a gate electrode of said field effect transistor on top of a thinner portion of said semiconductor material disposed on said dielectric island; I. forming a drain extension region and a source extension region by implanting a drain and source dopant into exposed regions of said thinner portion of said semiconductor material disposed on said dielectric island; wherein a channel region of said field effect transistor is formed by said thinner portion of said semiconductor material disposed on said dielectric island between said drain and source extension regions; and J. forming a drain contact region and a source contact region from a thicker portion of said semiconductor material disposed to the sides of said dielectric island.