Patent ID: 6515890
Filing Date: 2003-02-04
Classification: G11C

Abstract:
An integrated semiconductor memory, comprising:a memory cell having a ferroelectric memory property; a memory cell array including a row line for selecting said memory cell and a column line for reading data signals from said memory cell and writing data signals to said memory cell; a charge line; said memory cell being connected between said column line and said charge line; a read amplifier connected to said column line, said read amplifier supplying an output signal; a driver circuit connected to said charge line for providing a given potential to said charge line; a connection for providing a common supply potential; and said column line and said charge line each having an active operation mode and an inactive operation mode, and, when in the inactive operation mode, said column line and said charge line being jointly connected, in one of said read amplifier and said driver circuit, to said connection for providing the common supply potential.