Patent ID: 8076209
Filing Date: 2011-12-13
Classification: H01L

Abstract:
1. A method of fabricating an MOS transistor on and within a silicon-comprising substrate having a first surface, the method comprising: depositing a polysilicon layer overlying the first surface of the silicon-comprising substrate; amorphizing the polysilicon layer; forming a gate stack comprising a gate electrode fabricated from the polysilicon layer and having sidewalls, the gate stack disposed overlying the first surface of the silicon-comprising substrate; forming offset spacers adjacent the sidewalls of the gate electrode; etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate, the recesses exposing second surfaces of the silicon-comprising substrate; depositing a stress-inducing silicon nitride layer overlying the gate stack, the offset spacers, and the second surfaces; annealing the silicon-comprising substrate; removing the stress-inducing silicon nitride layer; and after removing the stress-inducing silicon nitride layer, epitaxially forming impurity-doped, silicon-comprising regions in the recesses.