Patent ID: 7969226
Filing Date: 2011-06-28
Classification: H03K

Abstract:
1. A non-inverting gate driver comprising: (a) an input; (b) an output; (c) a first reference line for receiving a first supply voltage; (d) a second reference line for receiving a second supply voltage; (e) a ground terminal; (f) a first Junction Field-Effect Transistor (JFET) having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the first JFET is electrically coupled to the source terminal of the first JFET, and the drain terminal of the first JFET is electrically coupled to the first reference line for receiving the first supply voltage, respectively; (g) a second JFET having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the second JFET is electrically coupled to the input, the drain terminal of the second JFET is electronically coupled to the gate terminal and the source terminal of the first JFET, and the source terminal of the second JFET is electrically coupled to the second reference line for receiving the second supply voltage, respectively; (h) a third JFET having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the third JFET is electrically coupled to the source terminal of the third JFET, and the drain terminal of the third JFET is electrically coupled to the first reference line for receiving the first supply voltage and the drain terminal of the first JFET, respectively; (i) a fourth JFET having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the fourth JFET is electrically coupled to the source terminal and the gate terminal of the first JFET and the drain terminal of the second JFET, the drain terminal of the fourth JFET is electronically coupled to the gate terminal and the source terminal of the third JFET, and the source terminal of the fourth JFET is electrically coupled to the second reference line for receiving the second supply voltage and the source terminal of the second JFET, respectively; (j) a fifth JFET having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the fifth JFET is electrically coupled to the source terminal and the gate terminal of the third JFET, and the drain terminal of the fourth JFET, the drain terminal of the fifth JFET is electrically coupled to the first reference line for receiving the first supply voltage, the drain terminal of the third JFET, and the drain terminal of the first JFET, and the source terminal of the fifth JFET is electrically coupled to the output, respectively; and (k) a sixth JFET having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the sixth JFET is electrically coupled to the gate terminal and the source terminal of the first JFET, the drain terminal of the second JFET, and the gate terminal of the fourth JFET, the drain terminal of the sixth JFET is electronically coupled to the source terminal of the fifth JFET and the output, and the source terminal of the sixth JFET is electrically coupled to the source terminal of the second JFET, the source terminal of the fourth JFET, and the second reference line for receiving the second supply voltage, respectively.