Patent ID: 8493800
Filing Date: 2013-07-23
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a three-dimensional memory cell array in which memory cells are three-dimensionally arranged; write drivers arranged to be distributed under the three-dimensional memory cell array and configured to apply a first program voltage to the memory cells during writing in the memory cells; a first program voltage control circuit arranged around the three-dimensional memory cell array and configured to perform control for making the write drivers to generate the first program voltage; charge pump circuits arranged to be distributed under the three-dimensional memory cell array and configured to apply a second program voltage to the selected cell during the writing in the memory cells; and a second program voltage control circuit arranged around the three-dimensional memory cell array and configured to perform control for making the charge pump circuits to generate the second program voltage, wherein the first program voltage is applied to an unselected cell during writing in a selected cell, and wherein the write drivers drop the second program voltage to thereby generate the first program voltage.