Patent ID: 7903482
Filing Date: 2011-03-08
Classification: G11C

Abstract:
1. A semiconductor storage device, comprising: a memory section including a plurality of memory cell groups; a redundancy memory section including a plurality of redundancy memory cell groups; a redundancy circuit section configured to stop an access to the memory section when the redundancy circuit section is activated, and to activate one of the plurality of redundancy memory cell groups corresponding to an address signal when the redundancy circuit section is activated and receives the address signal; a redundancy circuit control section external from the redundancy circuit section and configured to produce a redundancy circuit inactivation signal to the redundancy circuit section; a redundancy decoder configured to access one of the plurality of redundancy memory cell groups corresponding to a selection signal in response to the selection signal outputted from the redundancy circuit section; and a decoder configured to access one of the plurality of memory cell groups corresponding to the address signal in response to an input of the address signal, and to stop an access to the plurality of memory cell groups in the memory section in response to the selection signal, wherein the redundancy circuit section has a normal mode in which an access to the redundancy memory section is permitted and a redundancy circuit inactivation mode in which an access to the redundancy memory section is prohibited, and the normal mode and the redundancy circuit inactivation mode are changed to each other in response to a first signal.