Patent ID: 8054117
Filing Date: 2011-11-08
Classification: H03L

Abstract:
1. A wideband delay-locked loop (DLL) circuit, comprising: an internal clock signal generating unit comprising; a path selecting switch receiving the internal clock signal and either (1) passing the zero internal clock signal to generate an internal clock signal or (2) applying the zero internal clock signal to a secondary delay block providing a secondary delay time to the zero internal clock signal to generate the internal clock signal; a clock path delay block receiving the internal clock signal and applying a clock path delay time to the internal clock signal to generate a first internal clock signal; and a phase detection/control circuit receiving and comparing a phase of the first internal clock signal with a phase of the external clock signal, and generating an interpolation control signal controlling the interpolator, a multi-switch control signal controlling the switching block, and a path switch control signal controlling the path selecting switch.