Patent ID: 7605636
Filing Date: 2009-10-20
Classification: H03K

Abstract:
1. A power gating structure configured to control electrical connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes, the structure comprising: a first path configured to control electrical connection between the power supply terminal and the virtual power supply node in response to a first control signal, wherein the first path comprises a first PMOS transistor having a gate to which the first control signal is applied; and a second path configured to control electrical connection between the power supply terminal and the virtual power supply node in response to the first control signal and a second control signal, wherein the second path comprises a plurality of transistors that are serially coupled together between the power supply terminal and the virtual power supply node and configured to receive the first control signal and the second control signal, and the second path includes an NMOS transistor and a second PMOS transistor that are serially coupled with each other, the NMOS transistor having a source directly connected to the virtual power supply node and a gate to which the first control signal is applied, and the second PMOS transistor having a source connected to the power supply terminal and a gate to which the second control signal is applied, wherein the first path and the second path are connected in parallel with respect to each other between the power supply terminal and the virtual power supply node, wherein the power supply terminal correspond to a higher power supply terminal, and wherein the first control signal is a logic “low” when the logic circuit is in an active mode, the first control signal is a logic “high” and the second control signal is a logic “low” when the logic circuit is in a data retention mode, and both the first control signal and the second control signal are a logic “high” when the logic circuit is in a power-down mode.