Patent ID: 8472259
Filing Date: 2013-06-25
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array comprising a plurality of bit-lines, a plurality of word-lines intersecting the bit-lines, a source-line, and a plurality of NAND strings, each NAND string comprising a plurality of memory cells connected in series, each memory cell comprising a control gate connected to one of the word-lines, each NAND string comprising ends connected to the source-line and one of the bit-lines, respectively; and a data write portion configured to repeat a write loop of writing data in units of a page comprising a plurality of memory cells connected to one word-line, the data write portion comprising, in the write loop, a first operation mode of sequentially performing a program operation of recording data to a memory cell and a first verify operation of verifying data record in the memory cell, and a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation of verifying data record in the memory cell, the data write portion comprising, in the first verify operation, precharging a bit-line connected to a predetermined first memory cell of the memory cells and a bit-line connected to a second memory cell in the same page as the first memory cell, the second memory cell being adjacent to the first memory cell, and sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell, then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell, precharging the bit-line connected to the first memory cell, and sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell.