Patent ID: 8767477
Filing Date: 2014-07-01
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array, the memory cell array comprising a memory string including a plurality of memory cells connected in series, a first select transistor connected to one end of the memory string, a second select transistor connected to the other end of the memory string, a bit line connected to the memory string via the first select transistor, a source line connected to the memory string via the second select transistor, and word lines connected to control gate electrodes of the memory cells, respectively; and a control unit configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation, the erase operation being an operation of applying an erase voltage to the memory cells for data erase, the erase verify operation being an operation of determining whether a threshold voltage of the memory cells is not more than a certain voltage, the step-up operation being an operation of raising the erase voltage by a step-up value when the threshold voltage is more than the certain voltage with regard to at least a part of the memory cells, the step-up value being changed in the step-up operation when, in a series of the repeat of the erase operation, the erase verify operation, and the step-up operation, a number of erase operations exceeds a certain number, the control unit being configured to execute the erase verify operation after the erase operation which is performed after the step-up value is changed.