Patent ID: 6300647
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A semiconductor device for characteristic evaluation, comprising:(a) a semiconductor substrate;(b) an interlayer dielectric layer formed on or over said substrate;(c) a first electrode formed on said interlayer dielectric layer;(d) a second electrode formed on said interlayer dielectric layer to be apart from said first electrode;said second electrode being electrically connected to said first electrode through an interconnection line;(e) a first capacitor dielectric formed to cover said first electrode;said first capacitor dielectric being contacted with said first electrode;(f) a second capacitor dielectric formed to cover said second electrode;said second capacitor dielectric being contacted with said second electrode;(g) a third electrode formed on said first capacitor dielectric to be opposite to said first electrode through said first capacitor dielectric;(h) a fourth electrode formed on said second capacitor dielectric to be apart from said third electrode;said fourth electrode being be opposite to said second electrode through said second capacitor dielectric;(i) said first and third electrodes and said first capacitor dielectric constitute a first evaluating capacitor and said second and fourth electrodes and said second capacitor dielectric constitute a second evaluating capacitor; and(j) said third and fourth electrodes constitute a pair of measuring terminals.