Patent ID: 8917548
Filing Date: 2014-12-23
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array which comprises a plurality of bit lines, a plurality of word lines and source lines crossing the bit lines, and a plurality of memory cells which comprise control gates connected to the word lines and which are connected in series, and which comprises a plurality of NAND strings with both ends connected to the bit lines and the source lines; and a reading circuit which executes a reading sequence of reading data from a target memory cell of the plurality of memory cells which is a reading target, when the word line connected to the target memory cell is a selected word line and a word line adjacent to the selected word line is an adjacent word line among the plurality of word lines, in the reading sequence, the reading circuit executing a prereading operation of supplying a first reading voltage to the adjacent word line and supplying a first reading pass voltage for conducting the memory cells, to the selected word line, and after executing the prereading operation, executing a main reading operation of supplying a fixed second reading voltage to the selected word line and supplying a fixed second reading pass voltage for conducting the memory cells, to the adjacent word line while sensing a plurality of electrical physical amounts of the target memory cell which appear in the bit lines.