Patent ID: 6577536
Filing Date: 2003-06-10
Classification: G11C

Abstract:
A flat-cell nonvolatile semiconductor memory including a plurality of word lines disposed in parallel, the semiconductor memory having a plurality of adjacent units, each of the plurality of units comprising:a main bit line which crosses the word lines; a ground line which crosses the word lines; a first sub-bit line, a second sub-bit line, a third sub-bit line, a fourth sub-bit line, and a fifth sub-bit line which are disposed substantially in parallel to the main bit line, each of the first, second, third, fourth and fifth sub-bit lines having a first end and a second end; four memory cell columns, each including a plurality of memory cells connected in parallel between respective adjacent two of the first, second, third, fourth and fifth sub-bit lines; and a plurality of bank-selecting switches for selecting one of the four memory cell columns; wherein, to the main bit line, the first ends of the second sub-bit line and the fourth sub-bit line are connected, and to the ground line, the second ends of the first sub-bit line, the third sub-bit line, and the fifth sub-bit line are connected; wherein the first one of the bank-selecting switches is disposed between the main bit line and the fourth sub-bit line, the second one of the bank-selecting switches is disposed between the main bit line and the second sub-bit line, the third one of the bank-selecting switches is disposed between the ground line and the fifth sub-bit line, the fourth one of the bank-selecting switches is disposed between the ground line and the third sub-bit line, the fifth one of the bank-selecting switches is disposed between the ground line and the third sub-bit line, the sixth one of the bank-selecting switches is disposed between the ground line and the first sub-bit line; wherein the second, third, and fourth ones of the bank-selecting switches are controlled by a first selecting signal, the first, fifth, and sixth ones of the bank-selecting switches are controlled by a second selecting signal; wherein the first sub-bit line is also a fifth sub-bit line of an immediately adjacent unit.