Patent ID: 8227926
Filing Date: 2012-07-24
Classification: H01L

Abstract:
1. A semiconductor die comprising: i) an integrated circuit formed on one surface of a piece of semiconductor wafer; ii) a plurality of input-output (I/O) pads interconnected to said integrated circuit; iii) a routing layer comprising: a dielectric layer formed on said one surface; and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending between one of said I/O pads and one of a plurality of bump-pads formed on said dielectric layer; iv) a plurality of under-bump metallizations (UBMs), each comprising a top surface for attaching a respective one of a plurality of solder bumps; and a bottom contact surface smaller than said top surface, in physical contact with a respective one of said plurality of bump-pads; wherein each one of said bump-pads has at least some of said conductive traces passing proximate thereto and beneath the corresponding UBM with which that one of said bump-pads is in physical contact, without contacting that one of said bump-pads, to mechanically reinforce said routing layer proximate said corresponding UBM.