Patent ID: 6667907
Filing Date: 2003-12-23
Classification: G11C

Abstract:
A semiconductor memory comprising:a semiconductor memory device including a first transistor and a second transistor formed on a well, said first transistor having a tunnel oxide film, a floating gate, a drain, a source connected to a source line and a control gate connected to a control word line, said second transistor having a source, a drain connected to a data line and a gate connected to a select word line, and said drain of said first transistor being connected to said source of said second transistor; a first pulse generation circuit for outputting a pulse signal in injecting electrons into said floating gate of said first transistor; a first delay circuit for receiving said pulse signal from said first pulse generation circuit and outputting a first delay signal by delaying said pulse signal; a second delay circuit for receiving said first delay signal from said first delay circuit and outputting a second delay signal by delaying said first delay signal; a third delay circuit for receiving said second delay signal from said second delay circuit and outputting a third delay signal by delaying said second delay signal; a control word line driver circuit for changing potential of said control word line to a given voltage in response to said first delay signal received from said first delay circuit; a well driver circuit for changing potential of said well to a given voltage in response to said second delay signal received from said second delay circuit; and a source line driver circuit for changing potential of said source line to a given potential in response to said third delay signal received from said third delay circuit.