Patent ID: 8633104
Filing Date: 2014-01-21
Classification: H01L

Abstract:
1. A method of manufacturing a three-dimensional semiconductor device, comprising: forming a peripheral structure on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region in the substrate, forming a stacked layer structure conformally covering the substrate in which the concave region is formed, the stacked layer structure having a lower top surface in the cell array region of the substrate compared to a top surface of the stacked layer structure in the peripheral circuits region of the substrate; forming a planarization stop layer that conformally covers the stacked layer structure; and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.