Patent ID: 6781917
Filing Date: 2004-08-24
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells arrayed in the row direction and column direction, capable of a dual port access, wherein: said memory cell is composed with two driver devices that hold data, two load devices that serve as loads to the driver devices, and two access devices that access said driver devices, a word line is connected to said access devices in the memory cells arrayed in the row direction, a pair of bit lines is connected to said access devices in the memory cells arrayed in the column direction, a load device control line is connected to said load devices in the memory cells arrayed in one of a direction of the row direction and the column direction, a pair of memory cell VCC lines are connected to said load devices in the memory cells arrayed in the other direction of the row direction and the column direction, in the data read, said word line makes said access devices conductive to read out data held in said driver devices to said pair of bit lines, and in the data write, said load device control line brings said load devices into low resistance to write data into said driver devices from said pair of memory cell VCC lines.