Patent ID: 7526739
Filing Date: 2009-04-28
Classification: G06F

Abstract:
1. A method for defining a 3-D technology file structure, the method comprising the steps of: providing an identifier for each one of at least two circuit levels, constituting at least two circuit level identifiers; providing for each one of said at least two circuit levels, an identifier for a 2-D technology file corresponding to said one of said at least two circuit levels; said identifier for the 2-D technology file comprising a pointer to the 2-D technology file; and providing a file structure comprising providing, an identifier for the bond layer disposed between said at least two circuit levels; and providing a list comprising said at least two circuit level identifiers and said identifier for said bond layer said at least two circuit level identifiers and said identifier for a bond layer being located in an order in which said at least two circuit levels and said bond layer are located in a 3-D device; the 3-D technology file structure being stored in a computer usable medium and being accessible by executing computer readable code on at least one processor; whereby the 3-D technology file structure is utilized in generating and verifying circuit layout for 3-D integrated circuits.