Patent ID: 6521487
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A method for forming a thyristor, the method comprising:providing a semiconductor substrate, a surface of the semiconductor substrate comprising at least one active area and a shallow trench isolation (STI) structure surrounding the active area; forming an N-well, and a P-well adjacent to the N-well, in the active area on the surface of the semiconductorsubstrate. forming agate oxide layer and a polysilicon layer in sequence on the semiconductor substrate; performing a photo-etching-process (PEP) to etch a portion of the polysilicon layer and the gate oxide layer to fore a dummy gate atop a border of the N-well and the P-well. forming a spacer on either side of the dummy gate; forming a first patterned photoresist layer exposing the P-well between the shallow trench isolation structure and the dummy gate; performing a first ion implantation process; removing the first patterned photoresist layer; forming a second patterned photoresist layer exposing the N-well between the shallow trench isolation and the dummy gate; performing a second ion implantation process; and removing the second patterned photoresist layer; wherein the dummy gate is used to avoid the surface of the semiconductor substrate atop the border of the N-well and the P-well from being affected by a subsequent process so as to prevent unwanted leakage current and a breakdown decrease of the thyristor.