Patent ID: 6188636
Filing Date: 2001-02-13
Classification: G11C,H03K

Abstract:
A circuit configuration, comprising:an input terminal for receiving data;an output terminal for outputting data;a first memory device for storing data and having an output and an input;a second memory device for storing data and having an output and an input;a first input switch having one side connected to said input terminal and another side connected to said input of said first memory device, said first input switch responsive to an applied clock signal for connecting said input of said first memory device to said input terminal during a first logic state of the clock signal;a second input switch having one side connected to said input terminal and another side connected to said input of said second memory device, said second input switch responsive to the clock signal for connecting said input of said second memory device to said input terminal during a second logic state of the clock signal;a first output transistor including a drain-source path with one side connected to said output of said first memory device and another side connected to said output terminal, said first output transistor configured to connect said output of said first memory device to said output terminal during the second logic state of the clock signal; anda second output transistor including a drain-source path with one side connected to said output of said second memory device and another side connected to said output terminal, said second output transistor configured to connect said output of said second memory device to said output terminal during the first logic state of the clock signal.