Patent ID: 6239603
Filing Date: 2001-05-29
Classification: G01R

Abstract:
A test circuit for a plurality of monitor test element groups (TEGs), which are formed on a semiconductor chip together with a semiconductor device and placed in selected positions scattered in the chip, wherein the test circuit selectively tests the monitor TEGs to thereby monitor variations in process parameters within the chip, the test circuit comprising:a TEG control circuit responsive to externally applied test signals T.sub.0 and T.sub.1 to T.sub.n for outputting control signals G.sub.1 to G.sub.n to control the monitor TEGs, respectively; andat least one data output terminal of the semiconductor device which is diverted by an enable signal to an input terminal for one of the test signals T.sub.0 to T.sub.n,wherein the at least one data output terminal of the semiconductor device is connected to an input of the TEG control circuit.