Patent ID: 6754740
Filing Date: 2004-06-22
Classification: G06F

Abstract:
An apparatus for transferring data between a first device and a memory area of memory means of a second device, the memory area being determined by an address, within a system which comprises at least one system clock and in which the first device provides at least a first signal indicating data transfer and a second signal indicating the direction of data transfer, the apparatus comprising:buffer registers for temporarily storing the data to be transferred and the address of the memory area to and/or from which the data are to be transferred; and a control means for controlling said buffer registers to temporarily store said data and address to be transferred in response to the first signal indicating that data transfer being active and the second signal indicating the direction of data transfer between the first device and the second device, the first and second signals thereby instructing either a write operation or a read operation, wherein at least two groups of buffer registers for storing data and associated addresses transmitted in consecutive data transfer operations, and wherein said control means is adapted to generate a control signal for alternately switching between a first group of buffer registers and a second group of buffer registers of said at least two groups of buffer registers after each of a respective one of consecutive data transfer operations.