Patent ID: 6661044
Filing Date: 2003-12-09
Classification: H01L,Y10S

Abstract:
A MOSFET, comprising:a substrate having a trench and a shallow trench isolation region enclosing the trench; a doped semiconductive layer disposed over the trench and on the substrate, wherein the doped semiconductive layer partially covers the trench, and the shallow trench isolation region encloses the trench and the doped semiconductive layer; a gate dielectric layer comprising a first portion and a second portion, wherein the first portion is disposed on a top surface of the doped semiconductive layer so as to fully cover the top surface of the doped semiconductive layer, and the second portion is disposed on all surfaces of the trench and covers a bottom surface of the doped semiconductive layer that is above the trench and exposed by the trench; a conductive layer comprising a first portion and a second portion, wherein the first portion is disposed on the first portion of the gate dielectric layer and covers the top surface of the doped semiconductive layer, and the second portion is disposed on the second portion of the gate dielectric layer and covers the bottom surface of the doped semiconductive layer that is above the trench and exposed by the trench, so that the second portion of the conductive layer is disposed in the trench and a the first portion of the conductive layer is disposed above the gate dielectric layer, wherein the first portion of the conductive layer is patterned to form a gate on the gate dielectric layer, so that the gate overlies a portion of the doped semiconductive layer that is over the trench, and wherein the doped semiconductive layer below the gate forms a channel region; and a source/drain region disposed partially within the substrate on either side of the gate and to the channel region, wherein the shallow trench isolation region abuts the source/drain region.