Patent ID: 6621982
Filing Date: 2003-09-16
Classification: G11B,H04N

Abstract:
An error correction apparatus which performs an error correction in units of an error correction code block composed of information data, an inner code parity indicating the error correction code for every row of the information data and an outer code parity indicating an error correction code for every column of the information data when a plurality of bit data forming the information data is arranged in matrix,said error correction apparatus comprising: a memory means for storing said error correction code block included in a signal read from a memory medium by inputting the error correction code block as units of said row of the information data and the inner code parity corresponding to the row; an error correction means for reading the row of said information data and the inner code parity corresponding to the row among the error correction code block stored in said memory means and performing an error correction of the read row of said information data by using the read inner code parity data at the timing before all of the data constituting said error correction code block has been stored in said memory means, in parallel with the operation of storing in said memory means the remaining data constituting the error correction code block, wherein the error correction means is adapted to begin performing the error correction of the read row of said information data when a predetermined amount of data is stored in the memory means, wherein the predetermined amount of data is less than the error correction code block; and wherein the error correction means reads said read row of said information data from the memory means.