Patent ID: 6525964
Filing Date: 2003-02-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell unit having a plurality of memory cells connected in series and having a first end and a second end; a first select transistor connected to the first end of said memory unit; a second select transistor connected to the second end of said memory unit; and a programming circuit which programs a selected memory cell among said plurality of memory cells, wherein said programming circuit applies, at a time of programming, a first voltage to a gate electrode of the selected memory cell, applies a second voltage to a gate electrode of a memory cell positioned between the selected memory cell and the second end and adjacent to said selected memory cell, the second voltage being lower than the first voltage, applies a third voltage to a gate electrode of at least one memory cell between the memory cell, to which the second voltage is applied, and the second end, the third voltage being lower than the first voltage but higher than the second voltage, and applies a fourth voltage to a gate electrode of a memory cell positioned between a memory cell adjacent to said selected memory cell and the first end, the fourth voltage being lower than the first voltage but higher than the second voltage.