Patent ID: 6067615
Filing Date: 2000-05-23
Classification: G06F,Y02D

Abstract:
A digital processor with reconfigurable architecture comprising:a processor input;a processor output;library means for storing a plurality of function sequences;memory means for storing data; andconfigurable means, connected to said library means, and said memory means and between said processor input and said processor output, for executing a processor operation, including first, second and third function sequences, by sequentially loading said first function sequence from said library means into a programmable gate array configurable by said first function sequence, said first function sequence generating a data result wherein said configurable means thereafter reconfigures said programmable gate array,means for replacing said first function sequence by selectively choosing between said second and said third function sequence from said library means during the processor operation based upon said generated data result, said programmable gate array being reconfigured with said chosen function sequence so as to contain one and only one functional sequence from said library means,wherein said configurable means stores and retrieves data from said memory means during at least one of said function sequences during said processor operation, and wherein said first function sequence includes a plurality of sub-functions, and at least one of said sub-functions loads either said second or said third function sequence from said library means based upon said generated data result into said configurable means to reconfigure said programmable gate array,said memory means being external to said programmable gate array so that said generated data result is stored in said external memory means while said programmable gate array is being fully reconfigured with said one and only one functional sequence, said memory means being connected to said library means and to said configurable means.