Patent ID: 8780599
Filing Date: 2014-07-15
Classification: G11C

Abstract:
1. A contents addressable memory comprising: a first memory array including a plurality of first match lines, a plurality of first search lines, a plurality of first contents addressable memory cells, and a first control logic; a second memory array including a plurality of second match lines, a plurality of second search lines, a plurality of second contents addressable memory cells, and a second control logic; and a clock supply circuit, which is used for generating and supplying clock signals to the first memory array and the second memory array, wherein the first control logic controls a first search function in the first memory array, and each of the first match lines outputs a result of the first search function to the second memory array when at least one of the first contents addressable memory cells coupled with corresponding first match line is mismatched with a search data provided from corresponding first search line, and wherein the second control logic controls a second search function in the second memory array, wherein when at least one of the first match lines indicates a hit result for the first search function, the second control logic makes activate the second match lines and the second search lines for starting the second search function, and when all of the first match lines indicate a miss result for the first search function, the second control logic makes inactivate the second match lines and the second search lines for stopping the second search function.