Patent ID: 8724399
Filing Date: 2014-05-13
Classification: G11C,H01L

Abstract:
1. A split-gate non-volatile memory (NVM) system, comprising: a plurality of split-gate non-volatile memory (NVM) cells, each split-gate NVM cell comprising: control gate driver circuitry configured to provide at least one of a positive control-gate erase voltage or a negative control-gate erase voltage to the control gates during erase operations; and select gate driver circuitry configured to provide a select-gate read voltage to the select gates during read operations and configured to provide a select-gate erase voltage to the select gates during erase operations, wherein the select-gate erase voltage is a positive voltage that is greater than the select-gate read voltage if the control gate driver circuitry is configured to provide a positive control-gate erase voltage, and wherein the select-gate erase voltage is a negative voltage that is less than the select-gate read voltage if the control gate driver circuitry is configured to provide a negative control-gate erase voltage.