Patent ID: 6061777
Filing Date: 2000-05-09
Classification: G06F

Abstract:
A method for operating a processor, the method comprising:dispatching an instruction;determining a presently architected rename register map (""RMAP"") entry for an architectural register targeted by the dispatched instruction, each RMAP entry having an architected register field, an architectural indicator field, a historical indicator field, and a use indicator field;selecting RMAP entries which are associated with physical registers that contain source operands for the dispatched instruction;updating the use indicator in the selected RMAP entries, the updated use indicator in the respective selected RMAP entry indicating that the respective entry is required by the dispatched instruction;determining whether the dispatched instruction is interruptible; andupdating the architectural indicator and the historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.