Patent ID: 7440322
Filing Date: 2008-10-21
Classification: G11C

Abstract:
1. A memory system, comprising: a plurality of non-volatile storage elements connected in a string between a source side element and a drain side element; a plurality of bit lines, wherein each bit line is connected to a plurality of non-volatile storage elements; and a plurality of word lines, the plurality of word lines include a dummy word line and a plurality of data word lines, the dummy word line is between a source side select line and a first word line of the data word lines, the first word line is connected to a first non-volatile storage element to be programmed, wherein a program voltage is applied to the first word line and a cut-off voltage is applied to the dummy word line while the program voltage is applied to the first word line, a boost voltage is applied to at least some of the data word lines while the program voltage is applied to the first word line and the cut-off voltage is applied to the dummy word line.