Patent ID: 9136457
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. An integrated circuit having Josephson junctions, comprising: a Josephson junction trilayer comprising an upper superconductor, an insulating layer, and a lower superconductor, the insulating layer being between the upper superconductor and the lower superconductor; an adhesion layer formed directly on top of the upper superconductor; and a resist layer formed directly on top of the adhesion layer, the resist being patterned and developed, exposing portions of the adhesion layer through the patterned and developed resist layer, and the exposed portions of the adhesion layer being etched through the upper superconductor layer to expose the insulating layer; and portions of the lower superconducting layer under the exposed portions of the insulating layer being anodized to selectively form Josephson junction circuit elements having submicron feature sizes under remaining portions of the adhesion layer and the resist layer, wherein the anodized portions of the lower superconductor form a layer of anodized superconductor on all sidewalls of the upper superconductor and insulating layer, and undergo a volumetric increase with respect to the non-anodized portions under remaining portions of the resist layer, the volumetric increase causing local stresses which are insufficient to cause substantial peeling of the resist layer on the adhesion layer and are sufficient to cause peeling of at least a portion of the resist layer directly on the upper superconductor adjacent to the anodized portions of the lower superconductor layer.