Patent ID: 7531446
Filing Date: 2009-05-12
Classification: H01L

Abstract:
1. A method comprising: providing a first insulation layer pattern on a substrate, the first insulation layer pattern including a first contact hole through which a first region of the substrate is exposed, the first contact hole having increased width versus height from the substrate; providing a spacer on a sidewall of the first insulation layer pattern; providing a conductive layer pattern in the first contact hole such that a top surface of the conductive layer pattern is lower than a top surface of the first insulation layer pattern; providing a second insulation layer pattern on the conductive layer pattern in the first contact hole; providing a second contact hole on the substrate by etching the first insulation layer pattern using the second insulation layer pattern and the spacer as a self-aligning mask, so that a portion of the first insulation layer pattern remains on a sidewall of the spacer, the second contact hole exposing a second region of the substrate; and providing a wiring in the second contact hole by filling the second contact hole with a conductive material, the wiring being electrically connected to the substrate.