Patent ID: 9099188
Filing Date: 2015-08-04
Classification: G11C,H01F,H01L

Abstract:
1. A spin-transfer torque magnetoresistive memory comprising a control circuitry and at least one memory cell comprising: a digital line provided on a surface of a substrate serving as a bottom electrode; a dielectric functional layer provided on the top surface of the digital line layer; a first recording layer provided on the top surface of the dielectric functional layer having magnetic anisotropy in a direction perpendicular to a film surface and having a variable magnetization direction; a first tunnel barrier layer provided on the top surface of the first recording layer; a reference layer provided on the top surface of the first tunnel barrier layer having magnetic anisotropy in a direction perpendicular to a film surface and having an invariable magnetization direction; a second tunnel barrier layer provided on the top surface of the reference layer; a second recording layer provided on the top surface of the second tunnel barrier layer having magnetic anisotropy in a direction perpendicular to a film surface and having a variable magnetization direction; a cap layer provided on the top surface of the second recording layer as an upper electric electrode; a middle electrode provided on sides of the first recording layer and electrically connected to the first recording layer; a bit line provided on the top surface of the cap layer; a CMOS transistor coupled the plurality of magnetoresistive memory elements through the middle electrode; and there is further provided circuitry connected to the bit line, the digital line and the select transistor of each magnetoresistive memory cell; and the control circuitry further configured to provide a first spin-transfer recording current having a first voltage magnitude along a first direction and a second spin transfer current having a second voltage magnitude along a second direction subsequently between the bit line and the select transistor and to provide a positive voltage on the digital line to generate an electric field on the dielectric functional layer and pointing upwards along the thickness direction to reduce the perpendicular anisotropy in the first recording layer in a recording operation; and the control circuitry further configured to provide a reading current between the bit line and the select transistor in a reading operation.