Patent ID: 8039894
Filing Date: 2011-10-18
Classification: H01L

Abstract:
1. A method for fabricating a trench transistor, comprising the following steps: (a) providing an epitaxial layer disposed above a substrate, the substrate having a first conductivity type and the epitaxial layer defining a surface reference plane; (b) providing a trench and, within the trench, a gate dielectric and a gate electrode; (c) providing a body region of a second conductivity type adjoining the trench; (d) providing a source region of the first conductivity type disposed within the body region; and (e) forming a drift region of the first conductivity type at the end of a junction between the substrate and the epitaxial layer using one or more high-energy implantations, a lower end of the trench extending at least through a part of said drift region, said drift region separating said body region from said substrate; wherein: the step (c) of providing the body region, the step (d) of providing the source region, and the step (e) of forming the drift region by said one or more high-energy implantations are each carried out from and through said surface reference plane, so that each of said steps (c), (d), and (e) are carried out from one and the same surface reference plane, the step (e) of forming the drift region, the step (c) of providing the body region, and the step (d) of providing the source region occur prior to the step (b) of providing the trench, so that the one or more high-energy implantations are performed through the epitaxial layer; and the step (b) is carried out such that the lower end of the trench completely extends through the drift region.