Patent ID: 6275077
Filing Date: 2001-08-14
Classification: H03H,H03K

Abstract:
A bus driver that accepts data in response to a first clock signal and introduces a propagation delay of a programmable duration determined by a programmable digital signal provided to the driver prior to transmission of the data over a bus, the bus driver comprising:A) an input stage for accepting and delaying the data for transmission over a bus, the input stage comprising(i) a first storage element for receiving and storing the data responsive to the first clock signal; and(ii) a second storage element for receiving and storing data stored in the first storage element responsive to a second clock signal so that data is transferred from the first storage element to the second storage element;B) an output stage coupled with the input stage and including a driver circuit for transmitting data stored in the second storage element over the bus; andC) a programmable delay module coupled with the second storage element for delaying the second clock signal with respect to the first clock signal by a time duration that is responsive to the programmable digital signal .