Patent ID: 7408244
Filing Date: 2008-08-05
Classification: H01L

Abstract:
1. A semiconductor package having opposing upper and lower surfaces comprising: a semiconductor chip having a plurality of bonding pads formed thereon; a chip-supporting member for receiving the semiconductor chip, the chip-supporting member having a wall erected around the semiconductor chip with a height taller than the height of the semiconductor chip; a lead frame including a plurality of leads molded integrally with the chip-supporting member, the leads being electrically connected to the bonding pads of the semiconductor chip, respectively; and a cover sealed over the top of the wall of the chip-supporting member, the cover having an inner surface facing the semiconductor chip and an opposing outer surface, wherein each of the leads has a first portion having a generally planar top surface exposed from the upper surface of the semiconductor package, a second portion having a generally planar bottom surface exposed from the lower surface of the semiconductor package for making external electrical connection, and a middle portion extending between the first and second portions wherein the middle portion of each lead is embedded inside the wall of the chip-supporting member, wherein the wall of the chip-supporting member has a notch for receiving the cover such that the outer surface of the cover is substantially flush with or below the top surface of the first portion of each lead.