Patent ID: 6730572
Filing Date: 2004-05-04
Classification: H01L

Abstract:
A method of forming a gate electrode comprising:forming a gate insulating layer on a semiconductor substrate; forming a polysilicon layer comprising grains on the semiconductor substrate; doping the polysilicon layer with p-type impurity ions; doping the p-doped polysilicon layer with n-type impurity ions for increasing the size of the grains; forming a metal layer on the twice-doped polysilicon layer; reacting the metal layer and the twice-doped polysilicon layer to obtain a silicon-metal compound layer on the twice-doped polysilicon layer to obtain a silicon-metal compound layer on the twice-doped polysilicon layer; and patterning the silicon-metal compound layer, the twice-doped polysilicon layer, and the gate insulating layer to obtain a gate electrode having a gate insulating layer interposed between the gate electrode and the semiconductor substrate.