Patent ID: 8557701
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a first group of conductive lines extending from a first region to a plurality of second regions over a substrate having the first region and the plurality of second regions; forming a second group of conductive lines that alternate with the first group of lines and extend from the first region to the plurality of second regions over the substrate; forming interlayer insulating layers over the substrate; forming open regions partially exposing the first and second groups of conductive lines by selectively etching the interlayer insulating layers in the plurality of second regions; forming an extended open region by removing a portion of each conductive line in the first group of conductive lines exposed by the open regions; forming insulating layers in the extended open regions; and forming contact plugs by gap-filling the open regions.