Patent ID: 6287920
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method of fabricating a multiple threshold voltage integrated circuit, comprising the steps of:providing a semiconductor substrate region of a first conductivity type;forming a gate dielectric film on said semiconductor substrate region;forming a conductive layer on said gate dielectric;etching said conductive layer to form at least two gate structures over said semiconductor region;implanting said semiconductor region adjacent to said gate structures with a first dopant species of a second conductivity type to form drain extension regions;implanting said semiconductor region adjacent to said gate structures with an angled implant of a second dopant species of a first conductivity type such that said second dopant species impinge on a first side of said gate structures and are shadowed from impinging on a second side of said gate structures said second side of said gate structures being opposite said first side of said gate structures;forming sidewall structures adjacent said first side of said gate structures and said second side of said gate structures;implanting said semiconductor regions adjacent to said sidewall structures with a third dopant species of a second conductivity type to form source and drain regions for at least two transistors; andinterconnecting said source and drain regions such that on a first transistor the source region is adjacent to said first side of said gate structure and the drain region is adjacent to said second side of said gate structure and on a second transistor the source region is adjacent to said second side of said gate structure and the drain region is adjacent to said first side of said gate structure.