Patent ID: 6396119
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A semiconductor substrate having a spacing between at least two adjacent wiring lines, comprising:at least two adjacent wiring lines each including a base layer, a middle layer, and a top layer, the base layer and the top layer each having a width greater than a width of the middle layer so that a cross section of each of said at least two adjacent wiring lines exhibits an I-shaped configuration, said I-shaped configuration extending substantially continuous along a longitudinal extent of each of said at least two adjacent wiring lines, wherein said at least two adjacent wiring lines are spaced less than 0.5 microns; and a dielectric material layer formed over said at least two adjacent wiring lines and between top layers thereof to define a void therebetween, said void elongated and substantially coextensive with an adjacent extent of said at least two adjacent wiring lines such that said substantially coextensive elongated void is substantially between said middle layers and below a top portion of said top layers of said at least two adjacent wiring lines.