Patent ID: 6263396
Filing Date: 2001-07-17
Classification: G09G,H04L,H04N

Abstract:
A programmable interrupt controller for a single interrupt architecture processor, comprising:a plurality of interrupt sources each operable to generate an interrupt;a dynamically alterable interrupt mask operable to selectively mask interrupts for the interrupt sources;an interrupt handler for the single interrupt architecture processor, the interrupt handler operable to process interrupts permitted by the interrupt mask in order of priority and to interrupt processing for a lower priority interrupt in order to process a later-received higher priority interrupt permitted by the dynamically alterable interrupt mask;an interrupt set/reset register disposed between the interrupt sources and the dynamically alterable interrupt mask, the interrupt set/reset register operable to store an interrupt for each of the interrupt sources;wherein the interrupt sources include hardware and firmware devices and the firmware devices are operable to control interrupts for the hardware devices in the set/reset register; andwherein the interrupt handler is further operable to save processing context for the lower priority interrupt prior to processing the higher priority interrupt and to restore processing context for further processing of the lower priority interrupt after completion of processing for the higher priority interrupt.