Patent ID: 6330237
Filing Date: 2001-12-11
Classification: H04J,H04L,H04Q

Abstract:
A time slot assignment circuit comprising:a pair of single time switch and single space switch, where said time switch is provided with a transmission data memory into which transmission data is sequentially written and performs switching in a time domain with respect to the transmission data and said space switch performs switching in a space domain with respect to the output from said time switch;an address control memory for outputting a channel setting address for controlling both said time switch and said space switch; anda channel setting information converting unit for converting a channel setting information from the outside to said channel setting address and an accessing address for said address control memory,further, said address control memory comprises a RAM (random access memory), andsaid channel setting address from said channel setting information converting unit for,first, reading second transmission data from said transmission data memory, which second transmission data is obtained by multiplexing a plurality of the first transmission data of the first multiplex level written into said transmission data memory as said transmission data and for,second, selecting one of said first transmission data, in said space switch, from among outputs from said time switch,is written into the address control memory at random by the accessing address, from said channel setting information converting unit, for said address control memory and further serially read out to said time switch and said space switch.