Patent ID: 6674813
Filing Date: 2004-01-06
Classification: H03J

Abstract:
In combination with a microprocessor, an integrated circuit for detecting a received signal, comprising:at least one detection circuit input terminal for receiving a field-strength setpoint value and a given multipath setpoint value as a serial data word, and a given range for an intermediate frequency; an intermediate frequency detector configured to detect the intermediate frequency and supplying a first search run stop signal if the intermediate frequency is within the given range; a field-strength comparator configured to supply a second search run stop signal if a field-strength of the received signal exceeds the field-strength setpoint value; a multipath comparator configured to supply a third search run stop signal if a multipath signal exceeds the given multipath setpoint value; a logic component operatively connected to said intermediate frequency detector, said field-strength comparator, and said multipath comparator, said logic component logically combining the first, second and third search run stop signals with one another and forming a binary stop signal, said logic component having an output and providing the binary stop signal as a statically present signal at said output of said logic component, and the microprocessor receiving, as an input signal, the binary stop signal provided at said output of said logic component; a first analog/digital converter connected upstream of said field-strength comparator, said first analog/digital converter digitizing a field-strength signal; a first serial/parallel converter connected between said first analog/digital converter and said field-strength comparator; a second analog/digital converter connected upstream of said multipath comparator, said second analog/digital converter digitizing the multipath signal; a second serial/parallel converter connected between said second analog/digital converter and said multipath comparator; and a third serial/parallel converter having a first portion of output bits connected to said multipath comparator for providing the multipath setpoint value and a second portion of output bits connected to said field-strength comparator for providing the field-strength setpoint value.