Patent ID: 9190988
Filing Date: 2015-11-17
Classification: G05F,H03K

Abstract:
1. A power management system for an integrated circuit (IC) operable in a low power mode and a high power mode, the system comprising: a low-power bandgap generator that is powered on when the IC enters the high power mode after a power-on-reset (POR), and provides a first reference voltage signal when the IC is in either of the high and low power modes; a full-power bandgap generator that is powered on when the IC enters the high power mode, and provides a second reference voltage signal when the IC is in the high power mode, and is powered off when the IC is in the low power mode; a reset mode controller, connected to the low-power and full-power bandgap generators, that stabilizes the first and second reference voltage signals when the IC enters the high power mode after the POR, and generates a stabilization complete signal when the first reference voltage signal is stabilized, wherein the first reference voltage signal is stabilized in a first predetermined time period after the POR; a first multiplexer that has a first input terminal connected to the low-power bandgap generator for receiving the first reference voltage signal, a second input terminal connected to the full-power bandgap generator for receiving the second reference voltage signal, a select input terminal connected to the reset mode controller for receiving the stabilization complete signal, and an output terminal for outputting one of the first and second reference voltage signals; and first circuitry, connected to the first multiplexer output terminal, for receiving the second reference voltage signal during the first predetermined time period and the first reference voltage signal when the stabilization complete signal is generated.