Patent ID: 9171962
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A semiconductor device having a nonvolatile memory cell selectively formed on a semiconductor substrate, comprising: a gate insulating film disposed on the semiconductor substrate; a floating gate selectively formed on the gate insulating film in a region for the nonvolatile memory cell; a control gate disposed on the floating gate and having a side coplanar with a side of the floating gate; a select gate selectively formed on the gate insulating film in the region for the nonvolatile memory cell and having a mono-layered structure of a conductive film flush with the floating gate; a tunnel diffusion layer facing a portion of the floating gate in the semiconductor substrate; a tunnel window disposed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window configured to be thinner than a remaining peripheral portion of the gate insulating film; a drain low concentration layer disposed in the semiconductor substrate, the drain low concentration layer self-aligned with a first side of the select gate opposite to the tunnel diffusion layer; a drain region disposed in the drain low concentration layer, the drain region self-aligned with a side wall covering the first side of the select gate, the drain low concentration layer being widened to a region that is deeper than the drain region and having an impurity concentration that is lower than that of the drain region; and a tunnel low concentration layer disposed to overlap a portion of the tunnel diffusion layer in the semiconductor substrate, the tunnel low concentration layer being self-aligned with a second side of the select gate facing the floating gate and a side of the floating gate facing the select gate.