Patent ID: 7565737
Filing Date: 2009-07-28
Classification: H01L,H05K,Y10T

Abstract:
1. A method of fabricating a package substrate for carrying a chip having a plurality of bumps thereon, the method comprising: providing a first substrate and a second substrate, wherein the first substrate has at least a first circuit layer disposed on a surface thereof; forming a second circuit layer on the second substrate such that the second circuit layer and the second substrate form an interposer, wherein the second circuit layer comprises a plurality of bonding pads and a plurality of traces such that each trace is electrically connected to one of the bonding pads and the bonding pads are disposed in locations corresponding to the bumps on the chip; disposing the interposer on the first substrate; after disposing the interposer, forming at least a dielectric layer over the first substrate and in a periphery of the interposer; and forming a third circuit layer over a portion of the dielectric layer such that the third circuit layer is electrically connected to the second circuit layer of the interposer and the first circuit layer of the first substrate.