Patent ID: 6957327
Filing Date: 2005-10-18
Classification: G06F

Abstract:
1. A method for performing branch prediction in a pipelined processor, said method comprising the steps of: detecting a control transfer resulting from execution of a control transfer instruction; recording a set of information about the control transfer instruction in a block entry of a fetch-block branch target buffer, said set of information including a fetch-block address of a first fetch-block containing a plurality of instructions and including said control transfer instruction, a target address of said control transfer instruction, and a length value representing an amount of memory needed to contain the plurality of instructions in the first fetch-block; determining that said plurality of instructions from said first fetch-block will again be fetched; predicting whether said control transfer will occur when said control transfer instruction is again executed using the fetch-block address of the first fetch-block; and fetching a second fetch block, responsive to the step of predicting, for execution after execution of said control transfer instruction.