Patent ID: 7683866
Filing Date: 2010-03-23
Classification: G09G

Abstract:
1. A display comprising: a plurality of drain lines and a plurality of gate lines arranged to intersect with each other; a first pixel portion and a second pixel portion each including subsidiary capacitors having first electrodes connected to pixel electrodes and second electrodes respectively; a first subsidiary capacitance line connected to said second electrodes of said subsidiary capacitors of said first pixel portion and not connected to said second electrodes of said subsidiary capacitors of said second pixel portion and a second subsidiary capacitance line connected to said second electrodes of said subsidiary capacitors of said second pixel portion and not connected to said second electrodes of said subsidiary capacitors of said first pixel portion; a gate line driving circuit including a shift register for sequentially driving said plurality of gate lines and consisting of only a plurality of transistors of the same conductive type; and a signal supply circuit supplying a first signal having a first voltage and a second signal having a second voltage to said first subsidiary capacitance line of said first pixel portion and said second subsidiary capacitance line of said second pixel portion respectively and including a plurality of signal supply circuit portions each formed by a plurality of transistors of the same conductive type as said transistors constituting said gate line driving circuit, wherein said signal supply circuit portions include: a signal switching circuit portion for switching said first signal having said first voltage and said second signal having said second voltage supplied to said first subsidiary capacitance line and said second subsidiary capacitance line respectively, wherein said first pixel portion and said second pixel portion are arranged along the direction in which said gate lines extend, and wherein said first signal is provided to said first subsidiary capacitance line and said second signal is provided to said second subsidiary capacitance line in one frame period, and said second signal is provided to said first subsidiary capacitance line and said first signal is provided to said second subsidiary capacitance line in the next one frame period.