Patent ID: 7870367
Filing Date: 2011-01-11
Classification: G06F

Abstract:
1. A method for executing processor instructions, the method comprising: receiving a complex parallel instruction including an operation code in a first field, control information in a second field distinct from the first field, and input data, the complex parallel instruction received at an arithmetic logic unit in a processor, the processor and the arithmetic logic unit supporting a conventional instruction set and a complex parallel instruction set, wherein control information directs control circuitry to determine whether a data value should be loaded into an input buffer or unloaded from an output buffer; executing the complex parallel instruction in the arithmetic logic unit using the input data, the execution state of the complex parallel instruction determined by the control information included in the complex parallel instruction, wherein the arithmetic logic unit is operable to run a conventional instruction set instruction simultaneously in the arithmetic logic unit while the complex parallel instruction is being run in the arithmetic logic unit.