Patent ID: 7038255
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. An integrated circuit arrangement ( 100 ), having at least one npn transistor ( 104 ) containing, in the following order in a manner adjoining one another, a first n-doped edge region ( 182 ), a p-doped base region ( 184 ) and a further n-doped edge region ( 186 ), and having at least one pnp transistor ( 102 ) containing, in the following order in a manner adjoining one another, a first p-doped edge region ( 114 ), an n-doped base region ( 116 ) and a further p-doped edge region 118 , the integrated circuit arrangement comprising a monocrystalline substrate ( a base terminal region ( at least one cutout ( a first edge terminal region ( and the first edge terminal region (