Patent ID: 7067370
Filing Date: 2006-06-27
Classification: H01L

Abstract:
1. A method of forming a transistor of a semiconductor device comprising: forming an N type gate pattern and a P type gate pattern on an N type transistor area and a P type transistor area, respectively, of a semiconductor substrate; selectively implanting N type impurities into the N type transistor area; forming an insulation layer on the substrate including the N type gate pattern and the P type gate pattern; forming a first spacer on sidewalls of the P type gate pattern by forming a photoresist pattern on the substrate to selectively expose the P type transistor area, using the photoresist pattern as an etching mask, and anisotropically etching a portion of the insulation layer in the P type transistor area while a portion of the insulation layer remains in the N type transistor area; and forming a P type impurity region having a low impurity concentration and a P type conductive gate pattern by selectively implanting P type impurities into the P type gate pattern including the first spacer and into the P type transistor area using the photoresist pattern as a mask.