Patent ID: 7705362
Filing Date: 2010-04-27
Classification: H01L,Y10S

Abstract:
1. A vertical silicon carbide MOSFET comprising: a hybrid p-type silicon carbide well region on a silicon carbide substrate; an n-type silicon carbide source region in the hybrid p-type silicon carbide well region; an n-type silicon carbide channel region adjacent and spaced apart from the n-type silicon carbide source region, wherein a channel region of the MOSFET has both n-type and p-type portions; a gate dielectric on the n-type silicon carbide channel region and at least a portion of the n-type silicon carbide source region; a gate contact on the gate dielectric; a first contact adjacent a portion of the hybrid p-type silicon carbide well region and the n-type silicon carbide source region; and a second contact on the substrate, wherein the hybrid p-type silicon carbide well region comprises: an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer; and an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends into the p-type epitaxial layer.