Patent ID: 9099492
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: forming a sacrificial gate structure above a layer of silicon; forming a first sidewall spacer adjacent said sacrificial gate structure; removing said sacrificial gate structure to thereby define an initial gate opening having sidewalls defined by said first sidewall spacer and to expose a surface of said layer of silicon; performing an etching process on said exposed surface of said layer of silicon to define a recessed channel in said layer of silicon, wherein said etching process undercuts a region beneath said first sidewall spacer; after performing said etching process, forming a second sidewall spacer within said region beneath said first sidewall spacer and within said initial gate opening on said sidewalls of said initial gate opening to thereby define a final gate opening narrower than said initial gate opening and expose said layer of silicon; and forming a replacement gate structure in said final gate opening.