Patent ID: 8341301
Filing Date: 2012-12-25
Classification: G06F

Abstract:
1. A device having direct memory access (DMA) controller testing capabilities, the device comprises: a DMA controller, the DMA controller comprises a first data transfer path and a second data transfer path, the first data transfer path and the second data transfer path are mutually independent; a test unit coupled to the first and second data transfer paths, the test unit is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking, from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data; and a processor adapted to send to the test unit a test mode indicator and further adapted to send a read command to one data transfer path and a write command to another data transfer path of the DMA controller to be substantially simultaneously executed during the test mode.