Patent ID: 7332949
Filing Date: 2008-02-19
Classification: G01R,H03K

Abstract:
1. A multi-threshold CMOS (MTCMOS) flip-flop for latching a data input signal in response to a clock signal and converting the latched signal to a data output signal, the flip-flop comprising: a latch unit receiving the data input signal in a normal mode, latching the data input signal based on pulse signals and internal clock signals, transferring the latched data to an output terminal of the latch unit, outputting the transferred data as the data output signal, and performing a scan function by latching a scan signal; a pulse generator generating the pulse signals based on the clock signal and a scan enable signal, the pulse signals including a pulse signal and an inverted pulse signal; and a scan and retention latch unit generating the internal clock signals based on the clock signal and the scan enable signal, the internal clock signals including an internal clock signal and an inverted clock signal, storing data last input to the latch unit during the normal mode in a sleep mode in response to a control signal for controlling the sleep mode and the normal mode, performing a data retention function by transferring the stored data to the latch unit when the flip-flip returns to the normal mode from the sleep mode, performing the scan function by latching the scan signal, and transferring the scan signal to the latch unit, wherein the latch unit is connected to the scan and retention latch unit via a signal transfer line.