Patent ID: 6292028
Filing Date: 2001-09-18
Classification: H04L

Abstract:
An output circuit, comprising:an input terminal receiving an input logical signal;a first output terminal outputting a first output logical signal having a logic corresponding to a logic of the input logical signal;a second output terminal outputting a second output logical signal having a logic corresponding to an inverted logic of the input logical signal;a first constant voltage supply circuit generating a first voltage level;a second constant voltage supply circuit generating a second voltage level; andan output logic formation circuit connected to said first and second constant voltage supply circuits, said output logic formation circuit generating the first and second output logical signals having either the first voltage level or second voltage level based on the logic of the input logical signal, said output logic formation circuit including:an inverter having an input receiving the input logical signal and an output,a first NMOS transistor having a gate receiving the input logical signal, a source connected to said first constant voltage supply circuit and a drain connected to said second output terminal,a first PMOS transistor having a gate receiving the input logical signal, a source connected to said second constant voltage supply circuit and a drain connected to said second output terminal,a second NMOS transistor having a gate connected to the output of said inverter, a source connected to said first constant voltage supply circuit and a drain connected to said first output terminal, anda second PMOS transistor having a gate connected to the output of said inverter, a source connected to said second constant voltage supply circuit and a drain connected to said first output terminal.