Patent ID: 8111091
Filing Date: 2012-02-07
Classification: G11C

Abstract:
1. A track-and-hold circuit comprising: an input amplifier circuit configured to produce a pair of differential voltage outputs responsive to a pair of differential voltage inputs, the input amplifier circuit comprising a pair of bipolar junction transistors in a common emitter configuration; a switching circuit configured, in response to a clock signal, to couple the input amplifier circuit to an output circuit or to decouple the input amplifier circuit from the output circuit; a grounding circuit configured to couple the input amplifier circuit to an electrical ground; and the output circuit configured to track values of the pair of differential voltage outputs when the switching circuit is in a closed position and to hold the values of the pair of differential voltage outputs constant when the switching circuit is in an open position, wherein: the pair of bipolar junction transistors (BJTs) comprises a first BJT and a second BJT; the switching circuit comprises a third BJT, a fourth BJT, a fifth BJT, a sixth BJT, a seventh BJT and an eighth BJT; the emitter of the first BJT is coupled to the emitter of the second BJT; the gate of the first BJT is coupled to one input of the pair of differential voltage inputs, and the gate of the second BJT is coupled to the other input of the pair of differential voltage inputs; the collector of the first BJT is coupled to the emitter of the third BJT, and the collector of the second BJT is coupled to the emitter of the fourth BJT; the collectors of the third and the fourth BJTs are coupled to a power supply; the base of the third BJT is coupled to the collector of the first BJT, and the base of the fourth BJT is coupled to the collector of the second BJT; the bases of the fifth and the sixth BJTs are coupled to the clock signal; the collector of the fifth BJT is coupled to one output of the pair of differential voltage outputs and the collector of the sixth BJT is coupled to the other output of the pair of differential voltage outputs; the bases of the seventh and the eighth BJTs are coupled to a complementary clock signal; the emitter of the seventh BJT is coupled to the collector of the first BJT, and the emitter of the eighth BJT is coupled to the collector of the second BJT; the collector of the seventh BJT is coupled to the base of the third BJT, and the collector of the eighth BJT is coupled to the base of the fourth BJT; and the emitter of the fifth BJT is coupled to the collector of the first BJT, and the emitter of the sixth BJT is coupled to the collector of the second BJT.