Patent ID: 7172961
Filing Date: 2007-02-06
Classification: H01L

Abstract:
1. A method of fabricating an interconnect structure having reduced internal stress, comprising the steps of: providing a semiconductor substrate having a base dielectric layer thereon; forming a damascened interconnect structure in the base dielectric layer; capping the damascened interconnect structure and the base dielectric layer with a first dielectric barrier; executing a first chemical vapor deposition (CVD) process within a CVD reactor to deposit a first low-k dielectric film having a pre-selected thickness onto the first dielectric barrier; executing a first cooling process within the CVD reactor for cooling down the first low-k dielectric film; executing a second CVD process within the CVD reactor to deposit a second low-k dielectric film having the pre-selected thickness onto the first low-k dielectric film; executing a second cooling process within the CVD reactor for cooling down the first and second low-k dielectric films, wherein the first and second low-k dielectric films constitute a low-k film stack having reduced internal stress; and capping the low-k film stack with a second dielectric barrier.