Patent ID: 9006001
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit, comprising: forming a MOS transistor gate structure over a substrate, the gate structure having a lateral dimension; forming an etch blocking element over the substrate, the etch blocking element having a lateral dimension substantially equal to the lateral dimension of the gate structure; etching regions of the substrate adjacent to the gate structure to define first etched regions for silicon-germanium epitaxial layer formation etching regions of the substrate adjacent to the etch blocking element to define second etched regions similar to the first etched regions in depth and sidewall profile to represent the first region for a scatterometry measurement, wherein the etched regions adjacent the substrate for the scatterometry measurement correspond to at least one element less than a MOS transistor of the MOS transistor gate; and performing the scatterometry measurement of sidewalls of the second etched regions, wherein the etched regions adjacent the substrate for the scatterometry measurement correspond to at least one element less than a MOS transistor of the MOS transistor gate; to compute a profile representative of a corresponding profile of sidewalls of the first etched regions.