Patent ID: 7925867
Filing Date: 2011-04-12
Classification: G06F

Abstract:
1. A data processing apparatus comprising: processing circuitry configured to execute a sequence of instructions fetched from memory; pre-decoding circuitry configured to receive said instructions fetched from memory and to perform a pre-decoding operation to generate corresponding pre-decoded instructions; and a cache configured to store said pre-decoded instructions for access by said processing circuitry, said cache having a plurality of cache lines; wherein for a first set of instructions, each instruction comprises a plurality of instruction portions, and said pre-decoding circuitry generates a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions; and further comprising: checking circuitry coupled to said cache memory and responsive to a pre-decoded instruction read from said cache memory: to identify if said pre-decoded instruction crosses a cache line boundary between a first cache line storing a first pre-decoded instruction portion of said pre-decoded instruction and a second cache line contiguous with said first cache line and storing a second pre-decoded instruction portion of said pre-decoded instruction; if said pre-decoded instruction is one of one or more predetermined types of pre-decoded instruction, then to check said first pre-decoded instruction portion is consistent with said second pre-decoded instruction portion; and if one of said pre-decoded instruction is not one of said one or more predetermined type of pre-decoded instruction and said first pre-decoded portion is not consistent with said second pre-decoded portion, then to trigger re-generation of said pre-decoded instruction by said pre-decoding circuitry.