Patent ID: 6589821
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A method for forming a thin film transistor comprising:providing a substrate; forming a first dielectric layer on the substrate; forming a conductive layer on the first dielectric layer; forming a second dielectric layer on the conductive layer; forming an opening through the first dielectric layer, the conductive layer and second dielectric layer to expose a surface portion of the substrate and sidewall portions of the first dielectric layer, the conductive layer and the second dielectric layer; forming a conductive node adjacent the opening and the exposed surface portion of the substrate; depositing a third dielectric layer over the exposed surface portion of the substrate and the sidewall portions of the first dielectric layer, the conductive layer and the second dielectric layer; depositing a layer of semiconductive material over a portion of the third dielectric layer, the semiconductive material layer filling the opening and extending laterally outward from the opening over the upper surface of the second dielectric layer; after forming the semiconductive material layer, conductively doping the semiconductive material that is disposed elevationally above the conductive layer, such conductively doped semiconductive material provides one of a source region or a drain region for the thin film transistor, and wherein the conductive layer provides a gate electrode for the thin film transistor, the third dielectric layer laterally adjacent the conductive layer provides a gate dielectric layer, the semiconductive material layer laterally adjacent the gate dielectric layer provides a channel region and the conductive node provides the other of the source or drain region; and wherein a portion of the channel region is formed intermediate an entirety of the sidewall portions of the first dielectric layer.