Patent ID: 6121129
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method of forming a semiconductor structure having features of differing sizes, the method comprising the steps:forming a first layer of a dielectric material on a semiconductor substrate;patterning only a first plurality of features of a first feature size on the first layer;removing portions of the first layer, the portions corresponding to the first plurality of features, thus forming in the first layer a first plurality of openings corresponding to the first plurality of patterned features;filling the first plurality of openings with a conductive material;forming a second layer of a dielectric material, the second layer overlying the first layer and the filled openings;patterning a second plurality of features of a second feature size on the second layer, the second feature size being smaller than the first feature size;removing portions of the first layer and the second layer, the portions corresponding to the second plurality of features, thus forming in the second layer and in the first layer a second plurality of openings corresponding to the second plurality of patterned features, the second plurality of openings extending through the first and second layers;filling the second plurality of openings with a conductive material.