Patent ID: 8751852
Filing Date: 2014-06-10
Classification: G06F

Abstract:
1. An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising: a receiving device, comprising: a synchronous bus optimizer, configured to receive said control information, and configured to develop a value on a first ratio bus that indicates said first amount; and a delay-locked loop (DLL), coupled to said first ratio bus, configured generate a delayed data bit signal, wherein said DLL adds said first amount of delay to said data bit signal to generate said delayed data bit signal; and a transmitting device, coupled to said receiving device, said transmitting device comprising: a synchronous strobe driver, configured to receive said data strobe clock signal, and configured to employ said data strobe clock signal to generate said synchronous data strobe signal, wherein said synchronous data strobe signal, when enabled, is advanced also by said second amount.