Patent ID: 6559695
Filing Date: 2003-05-06
Classification: G09G

Abstract:
A semiconductor circuit apparatus including a selector apparatus selecting and outputting a first serially generated binary signal depending on data held by a first holder, comprising:a second holder for holding said first signal in synchronization with a second signal; a counter circuit for performing a count operation in synchronization with said second signal; a comparator for comparing an output signal of said counter circuit with the data held by said first holder; a selector circuit for selecting and outputting either a signal held by said second holder or another, predetermined timing signal depending on the binary level of a timing signal indicating timing when a match is detected by said comparator; a third holder for holding an output signal of said selector circuit in synchronization with a third signal; and a fourth holder for holding data held in said third holder in synchronization with a fourth signal; wherein data held in said third holder is provided as said predetermined timing signal to said selector circuit and a signal held by said fourth holder is provided as an output signal.