Patent ID: 8120384
Filing Date: 2012-02-21
Classification: G06F,H03K

Abstract:
1. An apparatus, comprising: a first input terminal, a second input terminal, and an output terminal, a first supply voltage line and a second supply voltage line, a first complementary pair of first and second output transistors operationally connected between the first and second supply voltage lines, a second complementary pair of third and fourth output transistors operationally connected between the first and second supply voltage lines, a first current mirror and a second complementary current mirror operationally connected in series between the input terminals and the first supply voltage line to provide control signals for control electrodes of the first output transistor and the third output transistor, a third current mirror and a fourth complementary current mirror operationally connected in series between the input terminals and the second supply voltage line to provide control signals for control electrodes of the second output transistor and the fourth output transistor, and at least one first resistive device operationally connected between a first intermediate node in the first complementary output transistor pair and the output terminal, and at least one second resistive device operationally connected between a second intermediate node in the second complementary output transistor pair and the output terminal.