Patent ID: 9153542
Filing Date: 2015-10-06
Classification: H01L,H01Q

Abstract:
1. A semiconductor package comprising: a first substrate including a ground layer; an interposer disposed on an upper surface of the first substrate and having at least one opening; a first die disposed in the at least one opening and coupled to the first substrate; a second substrate coupled to the interposer, disposed over the first substrate and having an area less than an area of the first substrate; a second die disposed on a lower surface of the second substrate; a third die embedded within the second substrate; an inductor disposed on an upper surface of the second substrate wherein the inductor is electrically connected to the second die and the third die; a package body encapsulating portions of the first substrate, the interposer, the second substrate, the first die and the second die, the package body having a lateral surface and an upper surface; and a metal layer disposed on the lateral surface and the upper surface of the package body wherein the metal layer is electrically connected to the first substrate and wherein the metal layer has voids that overlie the inductor.