Patent ID: 8344452
Filing Date: 2013-01-01
Classification: H01L,Y10S

Abstract:
1. A PMOS transistor comprising: a monocrystalline silicon substrate comprising a heavily doped upper region; an un-doped or lightly doped monocrystalline silicon channel region disposed directly on an uppermost surface of the monocrystalline silicon substrate and having a top surface; a pair of source and drain regions, each source and drain region comprising an epitaxial silicon germanium first portion disposed directly on the uppermost surface of the monocrystalline silicon substrate, directly adjacent to the un-doped or lightly doped monocrystalline silicon channel region and extending upwards directly from the uppermost surface of the monocrystalline silicon substrate to above the top surface of the un-doped or lightly doped monocrystalline silicon channel region, and each source and drain region further comprising a second portion extending only partially into the monocrystalline silicon substrate, the second portion directly below the first portion; and a metal gate insulated from and disposed above and over the un-doped or lightly doped monocrystalline silicon channel region, and above and over at least a part of the first portion of each of the source and drain regions, wherein the first portion of each of the source and drain regions comprises an angled faceted profile between the epitaxial silicon germanium and the un-doped or lightly doped monocrystalline silicon channel region underneath the metal gate, and wherein the second portion of each of the source and drain regions comprises only one rounded diffusion corner profile, the one rounded diffusion corner profile below, but not underneath, the metal gate.