Patent ID: 6753561
Filing Date: 2004-06-22
Classification: G11C,H01L

Abstract:
A cross point memory array comprising:a first group of substantially parallel conductive array lines; a second group of substantially parallel conductive array lines, oriented substantially perpendicular to the first group of parallel conductive lines; and a plurality of memory plugs located at the intersections of the first group of parallel conductive array lines and the second group of parallel conductive array lines, wherein each memory plug includes multiple layers of thin films including a thin film layer of a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage pulse to the memory element and reversibly switches from the second resistance state back to the first resistance state upon application of a second write voltage pulse to the memory element having opposite polarity of the first write voltage pulse; and at least one thin film layer constituting a non-ohmic device that, upon application of low magnitude voltages to the non-ohmic device, imparts a relatively high resistance to the memory plug.