Patent ID: 6130449
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A semiconductor memory device having a memory cell array region and a peripheral circuit region, comprising:a semiconductor substrate;a plurality of first transistors formed on a main surface of said semiconductor substrate in said memory cell array region;a plurality of second transistors formed on the main surface of said semiconductor substrate in said peripheral circuit region;a first interlayer insulating film covering said plurality of first transistors, said plurality of second transistors and the main surface of said semiconductor substrate;a plurality of first interconnect lines formed on said first interlayer insulating film;a second interlayer insulating film covering said plurality of first interconnect lines and the surface of said first interlayer insulating film;a third interlayer insulating film only covering the surface of said second interlayer insulating film over said peripheral circuit region;a plurality of storage capacitors formed on the surface of said second interlayer insulating film of said memory cell array region and inside a recess formed by said third interlayer insulating film;a fourth interlayer insulating film covering said plurality of storage capacitors and an upper surface of said third interlayer insulating film;a plurality of second interconnect lines formed on said fourth interlayer insulating film;a first plug formed in a first contact hole which penetrates said third interlayer insulating film; anda second plug formed in a second contact hole which penetrates said fourth interlayer insulating film;wherein one of said second interconnect lines in said peripheral circuit region is electrically connected to one of said first interconnect lines in said peripheral circuit region via a plurality of plugs which include said first plug and said second plug.