Patent ID: 8732638
Filing Date: 2014-05-20
Classification: G06F

Abstract:
1. A non-transitory computer readable medium having instructions stored thereon that, when executed by a processor, causes the processor to verify that device fingers of a semiconductor circuit have been properly represented by a corresponding layout diagram, the verifying comprising: parsing a netlist file describing the circuit to determine a minimum list of a plurality of sub-circuits to be verified, wherein each sub-circuit of the plurality of sub-circuits includes one or more instances of a multi-finger device, and at least one sub-circuit comprises two or more multi-finger devices; wherein a sub-circuit is on the minimum list when it includes at least one device with an nf parameter set to a value greater than one, or references an instantiation of at least one sub-circuit that includes the nf parameter set to the value that is greater than one; determining a first total number of fingers included in the plurality of sub-circuits as represented by the schematic diagram; determining a second total number of fingers included in the plurality of sub-circuits as represented by the corresponding layout diagram; comparing the first total number of fingers against the second total number of fingers; and reporting an error when the first total number of fingers does not correspond to the second total number of fingers; when the first total number of fingers corresponds to the second total number of fingers, further determining, for each multi-finger device, whether a first number of device fingers for the multi-finger device as represented by the schematic diagram equals a second number of device fingers for the multi-finger device as represented by the corresponding layout diagram.