Patent ID: 7024519
Filing Date: 2006-04-04
Classification: G06F

Abstract:
1. An apparatus, comprising: a first level cache memory including a plurality of M1 cache lines, each cache line being operable to store an address tag and data; a next lower level N-way set associative unified cache memory, each of the N-way sets including a plurality of M2 cache lines, each cache line being operable to store an address tag, status flags, and data, and M2 being greater than M1; and an additional memory associated with the next lower level cache memory and including a plurality of M1 memory lines, each memory line including respective L-flags for multiple cache lines of each N way set of the next lower level cache memory, each L-bit flag indicating whether any of the cache lines of the first level cache memory contain a copy of the data stored in the given cache line of the next lower level cache memory, wherein the number of L-flags in each memory line of the additional memory is equal to M2 /M1*N.