Patent ID: 6714059
Filing Date: 2004-03-30
Classification: H03K

Abstract:
An improved high-speed domino logic circuit comprising:a first supply voltage; a second supply voltage; a first clock signal; a second clock signal; an inverted second clock signal being approximately 180 degrees out of phase with said second clock signal; a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode, said first clock signal being coupled to said first transistor control electrode, said first transistor second flow electrode being coupled to a first node; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first supply voltage being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first node, said second transistor control electrode being coupled to a second node; a logic block coupled to said first node, said logic comprising at least one logic block input terminal and a logic block output terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said third transistor first flow electrode being coupled to said logic block output terminal, said third transistor second flow electrode being coupled to said second supply voltage, said third transistor control electrode being coupled to said first clock signal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said first supply voltage being coupled to said fourth transistor first flow electrode, said fourth transistor second flow electrode being coupled to said second node, said fourth transistor control electrode being coupled to said second clock signal; a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode, said fifth transistor first flow electrode being coupled to said second node, said fifth transistor second flow electrode being coupled to a third node which is an output terminal of said improved high-speed domino logic circuit, said fifth transistor control electrode being coupled to said second clock signal; a sixth transistor, said sixth transistor comprising a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode, said sixth transistor first flow electrode being coupled to said second node, said sixth transistor second flow electrode being coupled to said third node which is said output terminal of said improved high-speed domino logic circuit, said sixth transistor control electrode being coupled to said inverted second clock signal; and an inverter, said inverter comprising an inverter input terminal and an inverter output terminal, said inverter input terminal being coupled to said first node, said inverter output terminal being coupled to said third node which is said output terminal of said improved high-speed domino logic circuit, wherein said second clock signal is delayed with respect to said first clock signal.