Patent ID: 6829316
Filing Date: 2004-12-07
Classification: G11C

Abstract:
An input circuit comprising:delay means for defining a delay time for at least one logical state of a data signal and thereby delaying a clock signal for the delay time defined; and a holding circuit for holding the data signal responsive to the delayed clock signal; wherein the delay means comprises: a comparator for comparing an edge of the clock signal, on which the data signal is intended to be latched, to one of a leading edge and a trailing edge of the data signal; and a delay circuit for defining the delay time based on a result of comparison performed by the comparator, and wherein the delay means defines the delay time such that an edge of the clock signal, on which the data signal is intended to be latched and which is included within a transition interval of the data signal, is delayed to a point in time after the transition interval of the data signal is over.