Patent ID: 9130521
Filing Date: 2015-09-08
Classification: H03F

Abstract:
1. An operational amplifier circuit comprising: an N-MOS differential pair composed of a pair of N-channel type MOS-FETs connected to a pair of voltage input terminals; an active load for the N-MOS differential pair connected to the N-MOS differential pair and a current source for the N-MOS differential pair connected to the N-MOS differential pair; a P-MOS differential pair composed of a pair of P-channel type MOS-FETs connected to the voltage input terminals and arranged in parallel to the N-MOS differential pair; an active load for the P-MOS differential pair connected to the P-MOS differential pair and a current source for the P-MOS differential pair connected to the P-MOS differential pair; a comparator that obtains an H level when an common mode input voltage given to the pair of voltage input terminals is higher than a half of a power supply voltage for driving the N-MOS differential pair and the P-MOS differential pair, and obtains an L level when the common mode input voltage is lower than a half of the power supply voltage; a switch for the N-MOS differential pair, the switch delivering a current to the active load for the N-MOS differential pair and the current source for the N-MOS differential pair and makes the N-MOS differential pair operate solely when the output of the comparator is the H level; a switch for the P-MOS differential pair, the switch delivering a current to the active load for the P-MOS differential pair and the current source for the P-MOS differential pair and makes the P-MOS differential pair operate solely when the output of the comparator is the L level; a trimming means for the N-MOS differential pair that adjusts a driving capability of the current source for the N-MOS differential pair to minimize an offset voltage in operation of the N-MOS differential pair; and a trimming means for the P-MOS differential pair that adjusts a driving capability of the current source for the P-MOS differential pair to minimize an offset voltage in operation of the P-MOS differential pair.