Patent ID: 7474587
Filing Date: 2009-01-06
Classification: G11C

Abstract:
1. A flash memory device comprising: a memory cell array; an address buffer circuit including a plurality of address buffers, each address buffer configured to store an address for a random read operation, wherein the address buffer circuit is configured to store an address in one of the address buffers during a sensing section of each random read operation; a read circuit configured to sense data from the memory cell array in response to an address output from the address buffer circuit; an output data latch circuit configured to receive data sensed by the read circuit; and a control logic coupled to the address buffer circuit, the read circuit, and the output data latch circuit, and configured to control the output data latch circuit and the read circuit such that the output data latch circuit outputs first data read from the memory cell array substantially simultaneously as the read circuit senses second data from the memory cell array.