Patent ID: 8241975
Filing Date: 2012-08-14
Classification: H01L

Abstract:
1. A method for manufacturing a memory cell, the method comprising: implanting a source in a substrate; implanting a first drain in the substrate to create a first channel between the first drain and the source; implanting a second drain in the substrate to create a second channel between the second drain and the source; placing a first layer of oxide material over the first drain, the first channel, the source, the second channel, and the second drain; placing a first layer of polysilicon material over the first layer of oxide material; etching the first layer of polysilicon material to form a first floating gate overlying the first channel, the first floating gate having a first curved upper surface and a first sharp tip; and etching the first layer of polysilicon material to form a second floating gate overlying the second channel, the second floating gate having a second curved upper surface and a second sharp tip.