Patent ID: 6081144
Filing Date: 2000-06-27
Classification: H03K

Abstract:
A signal change detection circuit comprising:an input signal terminal,a set/reset flip-flop means designating one terminal among a set input terminal and a rest input terminal as a priority input terminal,a delaying means with an input terminal which is coupled with an output of the set/reset flip-flop, anda signal transfer controlling means having a control terminal, holding an input signal in response to a control signal of a first level input to the control terminal, transferring the input signal in response to a control signal of a second level input to the control terminal, and selectively transferring only the input signal having either level of the first level or second level to a signal holding means for holding one of the first level or second level of the output signal of the signal transfer controlling means,said signal change detection circuit being constituted so that the output terminal of the signal change detection circuit is connected to the input of the signal transfer controlling means via the delaying means,the input signal terminal being connected to the priority input terminal of the set/reset flip-flop means and the control terminal of the signal transfer controlling means,the output of the signal transfer controlling means connected to the other input terminal of the set/reset flip-flop means, andsaid signal change detection circuit generating a pulse signal having a predetermined width in accordance with the change of the input signal from the first level to the second level and suppressing the generation of the pulse signal with respect to a change of the input signal from the second level to the first level.