Patent ID: 6073215
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A data processing system, comprising:instruction dispatch means for providing a plurality of instructions;an instruction execution unit for receiving at least one of the plurality of instructions from the instruction dispatch means;a data cache coupled to the instruction execution unit, the data cache receiving address information;a cache miss queue unit coupled to the data cache, the cache miss queue unit comprising a plurality of entries for storing information corresponding to cache misses, the cache miss queue unit fetching data for use in the data cache in response to a request from the data cache; anda data stream touch (DST) controller, the data stream touch controller receiving an available entry indicator from the cache miss queue unit, wherein if the available entry indicator is above a predetermined threshold value, the data stream touch controller providing a prefetch address to the data cache else the data stream touch controller withholding the prefetch address from the data cache.