Patent ID: 7516264
Filing Date: 2009-04-07
Classification: G06F,G11C,Y02D

Abstract:
1. In a memory subsystem having a memory controller connected to memory devices divided internally into ranks and banks for addressing data in blocks, a method comprising: determining when the number of banks within the memory subsystem is larger than N, where N represents a total number of available bank control logic components within the memory controller; when the number of banks within the memory subsystem is not larger than N, allocating an individual one of the available bank control logic components to each of the banks within the memory subsystem; when the number of banks is larger than N, folding multiple ones of the banks within a memory device into a set to be addressed by a single one of the available bank control logic components, wherein said folding includes virtually combining the multiple banks into the set such that access to each of the multiple banks of the set are controlled by a same bank control logic component; and when a memory access operation is received addressed to a first bank: wherein said folding multiple ones of the banks comprises: