Patent ID: 6466290
Filing Date: 2002-10-15
Classification: G02F

Abstract:
A fringe field switching mode liquid crystal display comprising a front substrate, a back substrate facing the front substrate, a liquid crystal cell interposed between the front and back substrates, a plurality of gate bus lines and a plurality of data bus lines arranged on the back substrate in a matrix form to define a plurality of unit pixels, a plurality of counter electrodes each formed at an associated one of the unit pixels and made of a transparent material, the counter electrodes to which desired common signal is applied, respectively, a plurality of pixel electrodes each formed in a region adjacent to an associated one of the counter electrodes to produce a fringe field having horizontal components in cooperation with the associated counter electrode, the pixel electrodes being made of a transparent material, a plurality of thin film transistors each connected to an associated one of the gate bus lines, an associated one of the data bus lines, and an associated one of the pixel electrodes and adapted to charge the associated pixel electrode based on an input signal from the associated gate bus line and an input signal from the associated data bus line, a front horizontal alignment film formed between the liquid crystal cell and the front substrate to have a rubbing axis of a desired direction, a back horizontal alignment film formed between the liquid crystal cell and the back substrate to have a rubbing axis of a desired direction, a back polarization plate formed at a back surface of the back substrate to have a polarization axis of a desired direction, and a front polarization plate formed at a front surface of the front substrate to have a polarization axis of a desired direction,wherein: the counter electrodes and the pixel electrodes are arranged on the back substrate such that the horizontal components of the fringe field produced at one of the unit pixels is orthogonal to the horizontal components of the fringe field produced at each of the unit pixels longitudinally and laterally adjacent to the one unit pixel, and the counter electrodes and the pixel electrodes are arranged on the back substrate such that the horizontal components of the fringe field produced at the one unit pixel is parallel to the data bus lines while the horizontal components of respective fringe fields of the adjacent unit pixels being parallel to the gate bus lines.