Patent ID: 6177813
Filing Date: 2001-01-23
Classification: H03K

Abstract:
A low frequency detection circuit, comprising:a negative delay signal generator for receiving an input signal (CK) and outputting a negative delay signal (CK1) and a plurality of low frequency detection signals (NDAS1-NDAS7);a low frequency detector for receiving the plurality of low frequency detection signals (NDAS1-NDAS7) and outputting a flag signal (SF); anda signal selector for outputting one selected from the input signal (CK) and the negative delay signal (CK1) in accordance with the flag signal (SF), wherein the negative delay signal generator comprises,a first delay unit for receiving the input signal (CK) and outputting a plurality of one shot pulse signals (AS2-AS10) respectively having a predetermined pulse width,a latch unit for receiving and latching the plurality of one shot pulse signals (AS1-AS10) in accordance with the input signal (CK),a first circuit for logically operating output signals of the latch unit and outputting the low frequency detection signals (NDAS1-NDAS7),a second circuit for receiving the low frequency detection signals (NDAS1-NDAS7) and outputting inverted low frequency detection signals (IAS1-IAS7) and wherein the second circuit further processes the inverted low frequency detection signals (IAS1-IAS7) and one shot pulse signals (AS4-AS10) to generate and delay first locking signals,a third circuit for logically operating the inverted low frequency detection signals (IAS1-IAS7) and the delayed one shot pulse signals (AS4, AS3, AS3, AS2 AS2, AS1, AS1), respectively to generate and delay second locking signals, anda fourth circuit for receiving and logically operating delayed locking signals of the second circuit and the third circuit, and outputting the negative delay signal.