Patent ID: 8932922
Filing Date: 2015-01-13
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device having a dual gate, the method comprising: forming, sequentially, a gate insulation layer, a first capping layer, and a barrier layer each across NMOS and PMOS regions on a substrate; removing the first capping layer and the barrier layer from the NMOS region to expose the gate insulation layer in the NMOS region; forming a second capping layer on the gate insulation layer in the NMOS region and on the barrier layer in the PMOS region; thermally processing the substrate while the barrier layer remains on the first capping layer in the PMOS region and the second capping layer remains on the barrier layer in the PMOS region and on the gate insulation layer in the NMOS region, such that material of the second capping layer spreads into the gate insulation layer in the NMOS region to form a NMOS gate insulation layer, and material of the first capping layer spreads into the gate insulation layer in the PMOS region to form a PMOS gate insulation layer, wherein the barrier layer is formed of material that prevents material of the second capping layer from spreading into the gate insulation layer in the PMOS region during the thermal processing; removing the second capping layer from the PMOS region after the thermal processing of the substrate has been carried out; forming a gate electrode layer on the NMOS gate insulation layer in the NMOS region and the barrier layer in the PMOS region; etching the gate electrode layer and the NMOS gate insulation layer to form a first gate in the NMOS region; and etching the gate electrode layer, the barrier layer and the PMOS gate insulation layer to form a second gate in the PMOS region.