Patent ID: 8014440
Filing Date: 2011-09-06
Classification: H04L

Abstract:
1. A frequency adjusting method of a clock/data recovery (CDR) circuit, applied to a receiver apparatus connected to an outer apparatus, the receiver apparatus comprising a phase-lock loop (PLL) and a CDR circuit, the PLL outputting a transmitter clock according to an operational frequency of the receiver apparatus, the CDR circuit generating a receiver clock according to an outer data signal of the outer apparatus, the frequency adjusting method comprising: (a) setting the CDR circuit in a phase mode such that the receiver clock follows frequency of the outer data signal; (b) checking whether a difference between frequencies of the receiver clock and the transmitter clock is larger than a threshold value; and (c) when the difference is larger than the threshold value, sending a reset signal from the receiver apparatus to restart the CDR circuit and switching the operational frequency of the outer apparatus according to the operational frequency of the receiver apparatus, and setting an operational frequency of the outer apparatus equal to the operational frequency of the receiver apparatus.