Patent ID: 8785262
Filing Date: 2014-07-22
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of forming a transistor device, comprising: forming a gate electrode in an insulating layer; forming a dielectric deposition-prohibiting layer on a surface of the insulating layer surrounding the gate electrode; selectively forming a gate dielectric layer on the gate electrode by depositing a first dielectric material using the dielectric deposition-prohibiting layer to prevent deposition of the first dielectric material on exposed portions of the dielectric deposition-prohibiting layer covering the surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric layer by chemical reactive deposition of the first dielectric material; forming a channel structure comprising a carbon nanostructure disposed on the gate dielectric layer; selectively forming a passivation layer on the gate dielectric layer by depositing a second dielectric material to cover a portion of the channel structure that is disposed on the gate dielectric layer, wherein the dielectric deposition-prohibiting layer prevents deposition of the second dielectric material on exposed portions of the dielectric deposition-prohibiting layer covering the surface of the insulating layer surrounding the gate electrode when selectively forming the passivation layer by chemical reactive deposition of the second dielectric material; and forming source and drain contacts on opposing sides of the passivation layer in contact with the channel structure.