Patent ID: 6995420
Filing Date: 2006-02-07
Classification: H01L

Abstract:
1. A semiconductor device including a memory cell array in which nonvolatile memory devices are arranged in a matrix of a plurality of rows and columns, wherein each of the nonvolatile memory devices comprises: a word gate which is formed over a semiconductor layer with a first gate insulating layer interposed therebetween; an impurity layer which is formed in the semiconductor layer and forms at least one of a source region and a drain region; and first and second control gates in the shape of sidewalls which are formed along two opposing sides of the word gate, respectively, wherein the first control gate is disposed over the semiconductor layer with a second gate insulating layer interposed therebetween, a first side insulating layer being interposed between the first control gate and the word gate, wherein the second control gate is disposed over the semiconductor layer with a second gate insulating layer interposed therebetween, a first side insulating layer being interposed between the first control gate and the word gate, wherein each of the first and second control gates extends in a first direction, wherein the first and second control gates are disposed so as to be adjacent to each other in a second direction, which intersects the first direction, with the impurity layer interposed therebetween, wherein each of the first and second control gates has one of rectangular and square cross-sectional shapes in a plane perpendicular to said semiconductor layer, and wherein each of the second gate insulating layer and the first side insulating layer is formed of a stacked film including a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.