Patent ID: 7206984
Filing Date: 2007-04-17
Classification: G01R,G11C

Abstract:
1. A built-in self test circuit monolithically integrated on a chip with a memory device under test comprising: a capture register configured to store data transmitted from the memory device; an operation controller configured to control operation of the memory device and the capture register; a hold controller configured to execute a hold operation to stop a read operation and a write operation of the memory device by transmitting a hold signal to the operation controller when a fault is detected at the memory device; a test control circuit configured to control the operation controller to transmit a capture signal so that the capture register stores the data to the capture register; a data generator configured to generate data to be written to the memory device and to generate an expected value of the data to be written to the memory device; a comparator configured to compare data stored in the capture register with an expected value of the data, and to transmit a signal when the data fails to match the expected value; a result transmitter configured to accept the signal from the comparator; an address register configured to store an address signal transmitted to the memory device; and an address generator configured to generate the address signal.