Patent ID: 6577013
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A chip size semiconductor package (â€œCSPâ€ ) with stacked dies, the CSP comprising:two or more semiconductor dies mounted on top of one another in a stack, each die having opposite first and second surfaces, an electronic IC device in the first surface thereof, a plurality of input-output terminal pads on the first surface thereof and in electrical connection with the electronic device therein, and a plurality of vias, with each said via extending through the die and a respective one of the terminal pads thereon, each said via having walls with a dielectric coating thereon and being coaxially aligned with a corresponding said via in the other dies; and, a plurality of electrically conductive pins each inserted through the coaxially aligned vias of the dies of the stack and electrically connected to corresponding ones of the terminal pads on each said die in the stack, each said pin having a portion protruding below a lower surface of a lowermost said die in the stack or an upper surface of an uppermost said die in the stack and comprising an input-output terminal of the CSP.