Patent ID: 9136157
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A structure in a semiconductor die comprising: a P substrate; an epitaxial layer situated above said P substrate; at least one P substrate contact situated in said epitaxial layer, said at least one P substrate contact allowing a bias voltage to be applied to said P substrate; a deep N well situated in said P substrate, said deep N well being situated at a depth below a top surface of said P substrate such that a portion of said P substrate is situated between said deep N well and said epitaxial layer; a lateral isolation N well situated in said P substrate and said epitaxial layer, said lateral isolation N well being a lightly doped N type region extending from a top surface of said epitaxial layer to said deep N well; an isolated P well situated over said deep N well, said isolated P well being laterally surrounded by said lateral isolation N well, said isolated P well extending completely through said epitaxial layer; said isolated P well being electrically isolated from said P substrate by said deep N well and said lateral isolation N well.