Patent ID: 7925999
Filing Date: 2011-04-12
Classification: G06F,H05K

Abstract:
1. A design method for a printed circuit board (PCB), the method comprising of: running a first simulation of a PCB comprising a plurality of power layers, and a plurality of vias connected to the power layers; changing connections of the vias that tend to draw too much current to be connected to fewer power layers, than the vias that tend to draw less current; running subsequent simulations; repeatedly adjusting connections of the vias until all vias draw a current that falls within a predetermined range so that no via draws more current than an upper limit the vias are designed for, and obtaining the proper number of the power layers to be electrically connected to each of the vias; and according to the proper number of the power layers electrically connected to each of the vias, design/fabricate the PCB with vias free from contact with the power layers that have been determined should not connected to the individual vias.