Patent ID: 7613905
Filing Date: 2009-11-03
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a register file comprising a plurality of registers, each of said plurality of registers having a corresponding register number; a plurality of functional units connected to said register file, said plurality of functional units including a critical functional unit subset of at least one and not all said plurality of functional units, each functional unit responsive within a single clock cycle to an instruction to a number of pipeline registers equal in number to said critical functional units, each pipeline register receiving and storing output data from a corresponding one of said critical functional units; a comparator receiving an indication of said operand register number of a current instruction of each of said plurality of functional units and an indication of said destination register number of an immediately preceding instruction of each critical functional unit, said comparator indicating whether an operand register number of said current instruction matches a destination register number of said immediately preceding instruction; and a plurality of register file bypass multiplexers equal in number to said plurality of functional units, each register file bypass multiplexer having a first input receiving data from said register corresponding to said operand register number of said current instruction, a number of second inputs equal to a number of said pipeline registers each connected to a corresponding one of said pipeline registers receiving data from said corresponding critical functional unit and an output supplying an operand to said operand input of said corresponding functional unit, said multiplexer selecting said data from said register corresponding to said operand number of said current instruction if said comparator fails to indicate a match and selecting a corresponding one of said second outputs from a pipeline register if said comparator indicates a match.