Patent ID: 8887019
Filing Date: 2014-11-11
Classification: G01R

Abstract:
1. A computer-implemented method, comprising: receiving a base clock signal having a frequency for testing a plurality of clock domains; receiving a programming instruction from an automated test equipment (ATE) for a first clock domain and a second clock domain of the plurality of clock domains; generating a first clock signal for driving the first clock domain and a second clock signal for driving the second clock domain of the plurality of clock domains from the base clock signal based on the programming instruction; determining a first delay for the first clock signal and a second delay for the second clock signal from the programming instruction, wherein the second delay is longer than the first delay, and wherein the second delay allows the first clock domain and the second clock domain to be tested in a single test sequence according to the first clock signal and the second clock signal respectively; and providing a test sequence comprising the first clock signal delayed by the first delay and the second clock signal delayed by the second delay; serially loading the programming instruction into programmable registers; receiving a trigger signal from the ATE; resetting operational registers to values copied from the programmable registers; and running the test sequence to test the first clock domain and the second clock domain.