Patent ID: 6990025
Filing Date: 2006-01-24
Classification: G11C

Abstract:
1. A memory array that simultaneously reads and writes different addresses of the same memory array, comprising: a plurality of memory cells arranged in two equally sized blocks, each memory cell having a separate read and write port, wherein each port is coupled to a wordline that activates the memory cells, and a bitline that transfers data to or from said memory cells; read bitlines and write bitlines respectively connected to a read and write port of each memory cell along a column of each of said blocks; read wordlines and write wordlines respectively connected to the read and write ports of each memory cell along a row of each of said blocks; a row of differential sense amplifiers located between the two blocks wherein one sense amplifier is provided for each column of said blocks, and wherein each bitline from the first block being respectively attached to a first input terminal of the corresponding differential sense amplifier, and each read bitline from the second block being respectively attached to a second input terminal of the corresponding differential sense amplifier; each write bitline in the first block connecting to the write bitline in the second block in the same column, enabling a simultaneous read and write by activating the read wordline from the first block, the write wordline from either the first or the second block, and the write bitlines traversing both blocks, said arrangement resulting in transforming noise coupling from the write bitline to the read bitlines into common mode noise that is rejected by said differential sense amplifiers, and a means for driving a write bitline in said first block and a write bitline in said second block in the same direction to create said common mode noise in a read bitline in said first block and a read bitline in said second block.