Patent ID: 6697443
Filing Date: 2004-02-24
Classification: H03M,H04L

Abstract:
A decoder comprising:a branch metric calculating circuit (BMC) for calculating 2k branch metrics (BMs) upon response to k input values at a time, where k is the same number of a encoder memory; an add-compare-select circuit (ACS) for receiving the BMs and previous path metrics (PMs) and generating 2k LLRs (Log Likelihood Ratio), each LLR including corresponding path selection bit and reliability information; a maximum likelihood (ML) state searcher for sequentially receiving series of path selection bits from the ACS, searching a ML state according to the path selection bits with a predetermined initial values for Ds clock period, and outputting one of the initial value as the ML state; a delay for receiving the LLRs from the ACS at a clock period, delaying the LLRs for the Ds clock period; a LLR updater for receiving the LLRs from the delay period and updating the LLRs by using sequentially being received corresponding path selection bits and reliability information for DL clock period; and a selector for selecting one of the updated LLR values according to the ML state value.