Patent ID: 6602768
Filing Date: 2003-08-05
Classification: H01L,Y10S

Abstract:
A process for forming an MOS-gated power device comprising:providing a substrate having an upper layer, said substrate comprising in said upper layer doped monocrystalline silicon of a first conduction type and including a doped well region of a second conduction type, said substrate further comprising at least one heavily doped source region of said first conduction type disposed in said well region at an upper surface of said upper layer, a gate region comprising a conductive material electrically insulated from said source region by a dielectric material, a heavily doped drain region of said first conduction type, and a patterned interlevel dielectric layer on said upper surface overlying said gate and source regions; forming a body mask on said substrate, and selectively removing portions of said source region and underlying well region remotely disposed from said gate region, thereby forming at least one body hollow in said substrate; removing said body mask, and forming a blanket layer of heavily doped polysilicon of said second conduction type over said substrate and said interlevel dielectric layer, said polysilicon filling said body hollow; selectively removing portions of said polysilicon blanket layer from said source region and said interlevel dielectric layer, leaving polysilicon filling said body hollow, said hollow filled with heavily doped polysilicon comprising a body region; depositing over said upper surface and interlevel dielectric layer a source metal layer in electrical contact with said source and body regions; and forming a drain metal layer in contact with said drain region in said substrate.