Patent ID: 6202180
Filing Date: 2001-03-13
Classification: G11C

Abstract:
A memory for a display comprising:a memory cell array;an external address input section;a first memory circuit which stores an address corresponding to a specified portion of a display;a second memory circuit which stores an address proved to be faulty as a result of a test for said memory cell array; andan address converting circuit coupled to said external address input section and said first and second memory circuits,wherein said address converting circuit outputs the address stored in said second memory circuit when an address supplied from said external address input section coincides with the address stored in said first memory circuit and outputs the address stored in said first memory circuit when the address supplied from said external address input section coincides with the address stored in said second memory circuit, andmemory cells corresponding to the address stored in the first and second memory circuit are both used according to the converted address.