Patent ID: 8823626
Filing Date: 2014-09-02
Classification: G09G

Abstract:
1. A matrix display device, comprising: a matrix board in which a plurality of pixels surrounded by m scanning lines and n video signal lines are arranged in matrix, for controlling a plurality of pixel transistors connected to said pixels on conduction by a gate signal supplied through said scanning lines and supplying a pixel writing voltage supplied through said video signal lines to said pixels through said pixel transistors; a scanning line drive circuit for supplying said gate signal to said scanning lines; a plurality of video signal line drive circuits for supplying said pixel writing voltage to said video signal lines; and a timing controller for outputting a display control data signal including a shift start pulse to said video signal line drive circuits and outputting a horizontal scan control signal including a vertical clock to said scanning line drive circuit, wherein each of unit start pulses inputted/outputted to/from said plurality of video signal line drive circuits is cascaded between an ante-stage video signal line drive circuit and a post-stage video signal line drive circuit in said plurality of video signal line drive circuits, said shift start pulse outputted from said timing controller is inputted to a first-stage video signal line drive circuit, the duty ratio of said vertical clock is controlled by one of said plurality of cascaded unit start pulses, and the duty ratio of said vertical clock that is controlled by said one of said plurality of cascaded unit start pulses is fixed during a vertical display period.