Patent ID: 7315968
Filing Date: 2008-01-01
Classification: G11B,H03L,H04N

Abstract:
1. A digital phase-locked loop system comprising: clock generating means for generating a reference clock based on a frequency of an input signal and a frequency of run-length data so as to generate N phase clocks by using the reference clock; pulse-length measuring means for measuring a pulse length of a playback signal, which is generated by binarizing the input signal, by using the N phase clocks so as to output pulse-length data; run-length extracting means for extracting run-length data by counting the pulse-length data with a virtual channel clock; input selection means for selecting a signal asynchronous with the N phase clocks or a signal synchronized with the N phase clocks as the input signal; and changing-point detection means for detecting changing points of the input signal selected by said input selection means in relation to each clock of the N phase clocks.