Patent ID: 7187236
Filing Date: 2007-03-06
Classification: H03F

Abstract:
1. A differential input amplification stage, comprising: a main input differential pair of transistors coupled at a first common node having first and second inputs for receiving a first and second input signal from an external source; a first current source coupled to said first common node, said main input differential pair of transistors biased by current flowing though said first current source, said main input differential pair of transistors coupled via first signal paths to first and second outputs of said amplification stage; a surrogate input differential pair of transistors coupled at a second common node, said surrogate input differential pair of transistors coupled to said first and second outputs of said amplification stage through second signal paths, said second signal paths independent from said first signal paths; a second current source coupled to said surrogate differential pair of transistors at said second common node, said surrogate differential pair of transistors biased by said second current source; a level shifting circuit coupled between a base or gate of said main input differential pair of transistors and a base or gate of said surrogate input differential pair of transistors; a tracking circuit for sensing and supplying a tracking current, said tracking current being proportional to said current provided by said first current source; a current mirror for replicating said tracking current to supply a mirror current, said mirror current coupled to said second common node, wherein reductions in said mirror current result in an increase in current flowing in said surrogate differential pair of transistors.