Patent ID: 6653697
Filing Date: 2003-11-25
Classification: H03K,H04B

Abstract:
A high frequency switch circuit comprising:first, second, third, fourth, fifth, and sixth signal terminals; a first field effect transistor circuit inserted in a first signal path connecting between the first signal terminal and the second signal terminal; a second field effect transistor circuit inserted in a second signal path connecting between the second signal terminal and the third signal terminal; a third field effect transistor circuit inserted in a third signal path connecting between the second signal terminal and the fourth signal terminal; a fourth field effect transistor circuit inserted in a fourth signal path connecting between the fourth signal terminal and the fifth signal terminal; a fifth field effect transistor circuit inserted in a fifth signal path connecting between the fifth signal terminal and the sixth signal terminal; a sixth field effect transistor circuit inserted in a sixth signal path connecting between the second signal terminal and the sixth signal terminal; a seventh field effect transistor circuit connected between the sixth signal terminal and a reference potential; an eighth field effect transistor circuit connected between the first signal terminal and the reference potential; a ninth field effect transistor circuit connected between the fourth signal terminal and the reference potential; a tenth field effect transistor circuit connected between the third signal terminal and the reference potential; first to tenth control lines for applying first to tenth control bias voltages to the control terminals of the first to tenth field effect transistor circuits; and a logic circuit for generating the control bias voltages to be applied to the first to tenth field effect transistor circuits, wherein each of the seventh, eighth, ninth, and tenth field effect transistor circuits, when ON, exhibits a characteristic impedance that satisfies a matching condition to the characteristic impedance of an associated one of first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively.