Patent ID: 9159650
Filing Date: 2015-10-13
Classification: G02F,H01L

Abstract:
1. A semiconductor device comprising: (a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges; (b) a plurality of semiconductor elements formed over the semiconductor substrate; (c) a first insulating film formed over the semiconductor substrate to cover the semiconductor elements; (d) a plurality of pad electrodes formed over the first insulating film and formed of a conductive layer; (e) a first wiring formed over the first insulating film and formed at a same level conductive layer as that of the conductive layer of the pad electrodes; (f) a second insulating film formed over the pad electrodes and the first wiring, the second insulating film having openings at upper sides of corresponding ones of the pad electrodes; and (g) a plurality of bump electrodes of substantially rectangular shape formed over the second insulating film and being electrically connected to the pad electrodes via the openings of the second insulating film respectively, wherein the bump electrodes and the pad electrodes are respectively arranged at predetermined intervals in a first direction along one of the long edges of the semiconductor substrate, wherein each of the bump electrodes has a pair of short edges and a pair of long edges, the pair of long edges extending in a second direction along one of the pair of short edges of the semiconductor substrate, wherein the bump electrodes are stacked on the pad electrodes respectively such that one of the pair of short edges of the bump electrodes is positioned inside a peripheral edge of the respective pad electrode in a plan view, and wherein the first wiring is disposed to intersect with the long edges of the bump electrodes in a plan view and is disposed under the bump electrodes.