Patent ID: 6046633
Filing Date: 2000-04-04
Classification: G09G

Abstract:
An output circuit comprising:a first operational amplifier including a first output node, a first non-inverted node supplied with a positive potential level with respect to a reference voltage and a first inverted node connected to said first output node, regulating the potential level at said first output node to the potential level at said first non-inverted node through a differential amplification between said first inverted node and said first non-inverted node, and having first voltage regulating characteristics fast in potential rise at said first output node and slow in potential decay at said first output node;a second operational amplifier including a second output node, a second non-inverted node supplied with a negative voltage with respect to said reference voltage and a second inverted node connected to said second output node, regulating the potential level at said second output node to the potential level at said second non-inverted node through a differential amplification between said second inverted node and said second non-inverted node, and having second voltage regulating characteristics fast in potential decay at said second output node and slow in potential rise at said second output node;a first switching unit having first input nodes respectively connectable to said first output node and said second output node, a third output node and a fourth output node, and alternately connecting each of said first input nodes to said third output node and said fourth output node; anda reset circuit provided for said first operational amplifier and said second operational amplifier, and forcibly resetting said first non-inverted node, said second non-inverted node, said first output node and said second output node to said reference voltage when said first switching unit changes the connections between said first input nodes and said third and fourth output nodes.