Patent ID: 6236240
Filing Date: 2001-05-22
Classification: H03K

Abstract:
A single-rail to dual-rail logical conversion circuit for domino logic comprising:a first P-channel precharge transistor having a source-drain path connected between a supply voltage and a first precharge node and a gate connected to receive a clock signal, said first precharge node being a first output of said single-rail to dual-rail logical conversion circuit;a first N-channel logic transistor having a source-drain path connected between said first precharge node and a first intermediate node and a gate connected to receive a single-rail input signal;a first N-channel discharge transistor having a source-drain path connected between said first intermediate node and ground and a gate connected to receive the clock signal;an input signal inverter having a input connected to receive the single-rail input signal and an output;a second P-channel precharge transistor having a source-drain path connected between a supply voltage and a second precharge node and a gate connected to receive the clock signal, said second precharge node being a second output of said single-rail to dual-rail logical conversion circuit;a second N-channel logic transistor having a source-drain path connected between said second precharge node and a second intermediate node and a gate connected to said first precharge node;a third N-channel logic transistor having a source-drain path connected between said second intermediate node and a third intermediate node and a gate connected to said output of said inverter; anda second N-channel discharge transistor having a source-drain path connected between said third intermediate node and ground and a gate connected to receive the clock signal.