Patent ID: 6232145
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device assembly, said method comprising the steps of: providing a semiconductor device having a first surface and a second active interiorsurface having electrical interconnection structure formed thereon extendingoutwardly therefrom; providing a substrate having a metallized surface pattern of electrical circuits for contactwith said electrical interconnection structure of said semiconductor device, saidsubstrate having an exterior surface spaced from said metallized surface pattern ofelectrical circuits and a plurality of thermal vias extending through said metallizedsurface pattern of electrical circuits to said exterior surface; positioning said semiconductor device proximate said substrate with said interconnectionstructure in contact with a portion of the metallized surface pattern of electricalcircuits of said substrate thereby forming a gap between said semiconductordevice and said substrate, said gap having a perimeter; connecting a portion of said electrical interconnection structure of said semiconductordevice to a portion of the metallized surface pattern of electrical circuits of saidsubstrate thereby forming an electrical circuit; placing fill material proximate the perimeter of said gap; providing a source of vacuum; and positioning the exterior surface of said substrate relative to said source of vacuum to drawa vacuum through at least one of said thermal vias and to urge said fill materialfrom said perimeter into said gap.