Patent ID: 8263433
Filing Date: 2012-09-11
Classification: H01L

Abstract:
1. A method of fabricating an active device array, the active device array comprising at least one first transistor and at least one second transistor, and the method of fabricating the active device array comprising: forming a first patterned metal layer over a substrate, the first patterned metal layer comprising a first source of the first transistor, a first drain of the first transistor, and a second gate of the second transistor, wherein the first drain and the first source are separated from each other; forming an oxide semiconductor layer over the substrate entirely; forming a first insulation layer on the substrate entirely to cover the oxide semiconductor layer and the first patterned metal layer; forming a second patterned metal layer on the first insulation layer, wherein the second patterned metal layer defines a first gate of the first transistor located between the first source and the first drain; patterning the oxide semiconductor layer and the first insulation layer by using the second patterned metal layer as a mask to form a first patterned oxide semiconductor layer and a first patterned insulation layer, wherein the first patterned oxide semiconductor layer comprises a first channel layer of the first transistor; forming a second insulation layer on the substrate entirely to cover the first transistor and the second gate; forming a second patterned oxide semiconductor layer over the second insulation layer, the second patterned oxide semiconductor layer comprising a second channel layer located above the second gate; and forming a third patterned metal layer over the second insulation layer, the third patterned metal layer comprising a second source of the second transistor and a second drain of the second transistor, wherein the second source and the second drain are respectively located at two opposite sides of the second gate.