Patent ID: 6979862
Filing Date: 2005-12-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor region of first conductivity formed over a semiconductor substrate of said first conductivity; a semiconductor trench receiving region formed over said semiconductor region of said first conductivity; a plurality of trenches in said trench receiving region, each trench including a bottom surface and opposing sidewalls; a channel region of a second conductivity adjacent said trenches; a conductive column of said first conductivity directly under the bottom surface of a respective trench and reaching said semiconductor region of said first conductivity; a region of said second conductivity adjacent and lateral to each conductive column, said region being in charge balance with said conductive columns, and adjacent said channel region; conductive regions of said first conductivity adjacent each trench and in said channel region; a gate insulation layer on said sidewalls of said trenches; a gate electrode in each of said trenches; and an electrical contact layer over said trench receiving region and in contact with said conductive regions of said first conductivity.