Patent ID: 6096639
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A method of forming a semiconductor integrated circuit comprising:forming a semiconductor device in a semiconductor substrate, the semiconductor device having a first doped region and a second doped region;forming a first silicided region and a second silicided region in the first doped region and the second doped region, respectively, the first and second silicide regions forming a uniform contact region for the respective first and second doped regions;forming a first insulating layer overlying the first and second silicide regions of the semiconductor substrate;forming a conductive layer having an uniform thickness, the conductive layer overlying the first insulating layer, the semiconductor substrate and a portion of the first and second silicide regions;forming a second insulating layer overlying the conductive layer; andpatterning the conductive layer and the second insulating layer, the conductive layer being patterned to define a local interconnect that electrically couples the first silicide region to the second silicide region.