Patent ID: 6894571
Filing Date: 2005-05-17
Classification: H03L

Abstract:
1. A PLL circuit comprising: a reference signal generator that produces a plurality of reference signals; a first variable frequency divider that divides an output signal of a voltage-controlled oscillator by a division factor of N equal to a value obtained by dividing a preset frequency by a reference frequency of the reference signals to output a feedback signal corresponding to one of the reference signals; a second variable frequency divider that divides the output signal of the voltage-controlled oscillator by a division factor of N/n (where n is an integer equal to or greater than 3) to produce a plurality of feedback signals corresponding to the rest of the reference signals; and a phase comparator that performs phase comparison between the feedback signals and the reference signals respectively, wherein, when the output signal of the voltage-controlled oscillator is exactly or almost in synchronism with the preset signal, error signals produced by the phase comparator are not passed to the voltage-controlled oscillator.