Patent ID: 8093645
Filing Date: 2012-01-10
Classification: H01L,Y10S

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell region including a plurality of bit lines formed of a diffusion layer formed in an upper portion of a semiconductor substrate, and spaced from each other and extending in a column direction, a plurality of word lines formed on the semiconductor substrate, and spaced from each other and extending in a row direction, and intersecting the plurality of bit lines, and a first insulating film interposed between the semiconductor substrate and each of the plurality of word lines and located in a region between any two adjacent ones of the plurality of bit lines, and having a function of holding electric charge; a bit line contact region including bit line contacts connected to the plurality of bit lines extended from the memory cell region, and a bit line isolation portion electrically separating the plurality of bit lines from each other; a first UV light shielding film formed on the semiconductor substrate and covering at least a portion of the bit line isolation portion or a portion of the semiconductor substrate in the bit line contact region; an interlayer insulating film provided on the word lines and the first UV light shielding film; and a second UV light shielding film formed on the interlayer insulating film and covering the semiconductor substrate in the memory cell region, wherein in the memory cell region, a plurality of memory cells are provided, each of which has a source region and a drain region which are regions where the corresponding two bit lines intersect the corresponding word line, a gate insulating film which is the first insulating film interposed between the source region and the drain region, and a gate electrode which is a portion formed on a region of the corresponding word line located on the gate insulating film.