Patent ID: 8977807
Filing Date: 2015-03-10
Classification: G06F

Abstract:
1. A system controller for a non-volatile storage system comprising: system communication bus interfaces, each system communication bus interface configured to allow communication from the system controller to one or more non-volatile memory chips, each non-volatile memory chip comprising a plurality of blocks, each block comprising a plurality of pages, each page representing an addressable memory location to which data may be written; and a programmable memory within the system controller, the programmable memory programmed with a program for causing the system controller to write data to the non-volatile memory chips in the form of page stripes, each page stripe comprising a number of data pages, each data page of a page stripe being written to a different non-volatile memory chip from other data pages of the page stripe, and each data page having a logical address associated therewith; wherein the system controller performs encryption on the data pages of the page stripes and the logical addresses associated therewith before writing the page stripes and the logical addresses associated therewith to the non-volatile memory chips, the system controller performing the encryption by: