Patent ID: 9165655
Filing Date: 2015-10-20
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory string including a plurality of first and second groups of serially coupled memory cells, and a first transistor serially coupled between the first and second groups of serially coupled memory cells; a plurality of word lines, each word line being coupled to a control gate of a different memory cell in each of the memory strings; a first line coupled to the control gate of the first transistor; a voltage generating circuit configured to generate first, second, and third control voltages of different voltage levels, the first control voltage having a higher voltage level than the second control voltage and the second control voltage having a higher voltage level than the third control voltage; and a control circuit configured to control application of control voltages to the word lines and the first line, wherein the first control voltage is applied to a first word line selected from the word lines, the second control voltage is applied to a second word line that is adjacent to the first word line, and the third control voltage is applied to the first line.