Patent ID: 6448112
Filing Date: 2002-09-10
Classification: G11C,H01L,Y10S

Abstract:
A method for forming a cell array region of a NOR-type mask ROM device, the method comprising the steps of:forming a gate insulating layer on a semiconductor substrate; forming a plurality of word line patterns parallel to one another on the gate insulating layer; forming a plurality of sub-bit line patterns which intersect a top portion of the plurality of word line patterns at right angles and contact the semiconductor substrate between the word line patterns; etching the semiconductor substrate using the plurality of word line patterns and the plurality of sub-bit line patterns as a self-aligned etching mask to form a plurality of trench regions; forming an interlayer insulating layer on the entire surface of the semiconductor substrate on which the plurality of trench regions have been formed; patterning the interlayer insulating layer to form bit line contact holes each of which exposes an active region which is connected with a sub bit line forming a sub-bit line pattern; and forming bit lines which are parallel to each sub-bit line pattern and are electrically connected with each sub-bit line through each bit line contact hole.