Patent ID: 8284598
Filing Date: 2012-10-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array provided with a plurality of memory cells in a matrix; and a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of said plurality of memory cells, wherein said power supply circuit comprises: a first intermediate voltage generating circuit configured to generate a first intermediate voltage between said power supply voltage and said ground voltage; a second intermediate voltage generating circuit configured to generate a second intermediate voltage between said power supply voltage and said ground voltage; a first output node to which said first intermediate voltage is supplied; a second output node to which said second intermediate voltage is supplied; and a connection control circuit provided between said first output node and said second output node, wherein said first intermediate voltage generating circuit supplies said first intermediate voltage in response to a first control signal, and said second intermediate voltage generating circuit stops its operation in response to said first control signal, and wherein said connection control circuit connects said first output node and said second output node when said second intermediate voltage generating circuit stops its operation.