Patent ID: 6362035
Filing Date: 2002-03-26
Classification: H01L,Y10S

Abstract:
A method for forming a channel stop in a twin well CMOS structure with planarized shallow trench field isolation comprising;(a) providing a silicon wafer; (b) forming a region of planarized shallow trench field isolation in said wafer; (c) blanket implanting a first dose of boron ions into said wafer whereby the centroid of said first dose is placed at a distance below the base of said field isolation forming a channel stop layer, (d) patterning a first ion implantation mask to expose a p-well region on a first side of said field isolation, said p-well region overlapping a first portion of sa id field isolation; (e) implanting a second dose of boron ions into said wafer, thereby forming a p-well; (f) patterning a second ion implantation mask to expose an n-well region on a second side of said field isolation, said exposed n-well region overlapping a second portion of said field isolation; and (g) implanting a dose of n-type impurity ions into said wafer, thereby forming an n-well, which extends deeper than, and overcompensates, said channel stop layer in said n-well.