Patent ID: 7710372
Filing Date: 2010-05-04
Classification: G09G

Abstract:
1. A PDP data driver for driving data electrodes of a PDP in accordance with display data, the data driver comprising a plurality of data driver ICs that are sequentially arranged; wherein each of the data driver ICs includes an output control circuit; input and output terminals of the output control circuit are sequentially arranged in an order of display cells of a plurality of primary colors forming a screen of the PDP and divided into a plurality of groups corresponding to the plurality of primary colors, respectively; the output control circuit includes a first array of gates and a second array of gates in such a manner that the gates of each of the first array and the second array correspond to the input and output terminals, respectively; the output control circuit controls the first array of the gates to output input data without change or to set said input data to a high level in accordance with a first control input for a first group and to set a setting timing of the high level in accordance with a first timing adjustment input; the output control circuit controls the second array of the gates to transfer outputs of the corresponding first array of the gates without change or to set said outputs to a low level in accordance with a second control input for the first group, and to set a setting timing of the low level in accordance with the first timing adjustment input; the output control circuit controls the first array of the gates to output input data without change or to set said input data to the high level in accordance with the first control input for a second group, and to set the setting timing of the high level in accordance with a second timing adjustment input; the output control circuit controls the second array of the gates to transfer outputs of the corresponding first array of the gates without change or to set said outputs to the low level in accordance with the second control input for the second group, and to set the setting timing of the low level in accordance with the second timing adjustment input; the output control circuit controls the first array of the gates to output input data without change or to set said input data to the high level in accordance with the first control input for a third group, and to set the setting timing of the high level in accordance with a third timing adjustment input; the output control circuit controls the second array of the gates to transfer outputs of the corresponding first array of the gates without change or to set said outputs to the low level in accordance with the second control input for the third group, and to set the setting timing of the low level in accordance with the third timing adjustment input.