Patent ID: 6890821
Filing Date: 2005-05-10
Classification: H01L

Abstract:
1. A method for manufacturing a memory device, comprising: forming a first oxide layer on top of a substrate; forming a gate layer on top of the first oxide layer; forming a second oxide layer over the gate layer; removing a portion of the second oxide layer and the gate layer to form a first opening in the second oxide layer and a second opening in the gate layer, the first and second openings exposing a portion of the first oxide underneath the gate layer, a width of the second opening being bigger than a width of a narrowest region of the first opening in the second oxide layer so that the gate layer is pulled back horizontally underneath the second oxide layer; forming a source region in the substrate underneath the first oxide layer; forming a third oxide layer in the first and second openings, the third oxide layer conforming to a contour thereof; removing a portion of the third oxide layer and the first oxide layer to make a third opening; and depositing a control gate material in the third opening.