Patent ID: 6288970
Filing Date: 2001-09-11
Classification: G11C

Abstract:
A programmable logic device memory array circuit comprising:a first combinable single-port memory array having a plurality of rows and columns of memory cells for storing data and having a maximum data width;a second combinable single-port memory array having a plurality of rows and columns of memory cells for storing data and having a maximum data width; andcircuitry for combining the first and second combinable single-port memory arrays to form a dual-port memory array having a maximum data width that is greater than the maximum data width of either the first combinable single-port memory array or the second combinable single-port memory array taken alone, wherein the circuitry for combining includes circuitry from the first combinable single-port memory array for performing writing operations and circuitry from the second combinable single-port memory array for performing concurrent reading operations.