Patent ID: 7610497
Filing Date: 2009-10-27
Classification: G06F,Y02D

Abstract:
1. A bridge logic for managing power consumption of a processor and a main memory, wherein the processor accesses the main memory through the bridge logic, the bridge logic comprising: a first buffer space for temporarily storing data from the processor; a second buffer space for temporarily storing data from the main memory; a first analyzer for monitoring data quantity of the first buffer space in a first period of time to determine if the data quantity of the first buffer space exceeds a first threshold value; a second analyzer for monitoring data quantity of the second buffer space in a second period of time to determine if the data quantity of the second buffer space exceeds a second threshold value; and a power management unit, coupled to the first analyzer and the second analyzer, for modifying an operating clock and an operating voltage of the processor and an operating clock and an operating voltage of the main memory based on information from the first analyzer and the second analyzer.