Patent ID: 7132896
Filing Date: 2006-11-07
Classification: H03L

Abstract:
1. An apparatus for minimizing filter capacitor leakage-induced jitter in a phased locked loop (PLL), comprising: a voltage controlled oscillator (VCO); at least one charge pump (CP); a low pass filter (LPF); a dummy filter comprised of a plurality of capacitors in series; a first switch and a second switch, wherein the second switch is at least configured to be coupled to the dummy filter, and wherein the first switch is at least configured to be coupled to the LPF; a first unity gain buffer (UGB) and a first UGB, wherein the first UGB is at least configured to be interconnected between the second switch and the LPF, and wherein the second UGB is at least configured to be interconnected between the first switch and the second switch; a lock detector having a lock detect output signal having a first and a second state; the first and the second switches are responsive to the output signal to alternatively interconnect the first UGB to the dummy filter and the second UGB to the LPF during the first state, and to disconnect the first UGB from the dummy filter in order to interconnect the second UGB and the dummy filter during the second state.