Patent ID: 7298648
Filing Date: 2007-11-20
Classification: G11C

Abstract:
1. A multi-bit nonvolatile semiconductor memory device, comprising: a memory cell array including a bit line connected to a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are programmable in more than two threshold voltage states in order to store more than one bit of data; a page buffer circuit which stores a logic value as main latch data and which is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line; and a sub-latch circuit which stores a logic value as sub-latch data and which is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line; wherein the memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode through the bit line.