Patent ID: 6131131
Filing Date: 2000-10-10
Classification: G06F

Abstract:
A computer system comprising:a processor;a host bus coupled to the processor;an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic that is capable of controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte;a local bus coupled to the embedded controller;a device coupled to the embedded controller via the local bus;an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer; andan extended control logic coupled to the embedded controller, the extended control logic capable of controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit,the processor being capable of loading data into the multiple-byte buffer, sending a transaction command to the extended control logic, and waiting for the commanded transaction to complete, the extended control logic controlling execution of the transaction.