Patent ID: 7551493
Filing Date: 2009-06-23
Classification: G11C

Abstract:
1. A data processing device comprising: a nonvolatile memory provided with a memory array; and a controller, wherein the memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor, the first MOS transistor, which is used for data storage, having a charge retention layer and a memory gate, and the second MOS transistor having a control gate to selectively connect the first MOS transistor to a bit line, and wherein the controller controls the bit line potential level in accordance with whether to supply electric current between a drain and a source of a nonvolatile memory cell of the plurality of nonvolatile memory cells, and controls the polarity of high voltage applied to the memory gate to select either emission of electrons from, or injection of electrons into, the charge retention layer of the nonvolatile memory cell to which the current is supplied.