Patent ID: 6476847
Filing Date: 2002-11-05
Classification: G06K

Abstract:
A pulse width modulation system comprising a pulse width modulation circuit for outputting a necessary pulse width modulation signal in response to an input signal, and control means for controlling the pulse width modulation circuit,wherein the control means has means for outputting a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and the pulse width modulation circuit comprises: switch control means for executing a control to generate a clock start signal, an EVEN-side data signal, an ODD-side data signal, an EVEN-side pulse start position signal, an ODD-side pulse start position signal and an EVEN/ODD switch signal, on the basis of a clock signal, a data signal and a pulse start position signal which are input; delay setting means for providing predetermined amounts of delay to the clock start signal from the switch control means, on the basis of the delay setting signal from the control means, and generating a plurality of pulse width modulation signals; phase select means for selecting one of the plurality of pulse width modulation signals generated by the delay setting means, on the basis of the division number setting signal from the control means, and outputting the selected signal as a clock end signal; comparison means for comparing the clock end signal from the phase select means with the clock start signal and outputting the phase comparison result signal to the control means; first select means for selecting an EVEN-side pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting means, on the basis of the EVEN-side data signal and the EVEN-side pulse start position signal generated from the switch control means; second select means, provided in parallel to the first select means, for selecting an ODD-side pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting means, on the basis of the ODD-side data signal and the ODD-side pulse start position signal generated from the switch control means; and switch means for receiving the EVEN-side pulse width modulation signal candidate selected by the first select means and the ODD-side pulse width modulation signal candidate selected by the second select means, selecting either the EVEN-side pulse width modulation signal candidate or the ODD-side pulse width modulation signal candidate in accordance with the EVEN/ODD switch signal from the switch control means, and outputting the selected candidate as the pulse width modulation signal.