Patent ID: 6140666
Filing Date: 2000-10-31
Classification: H01L,Y02E,Y02P,Y10S

Abstract:
A semiconductor apparatus comprising an arrangement of plural semiconductor devices in column, comprising:a substrate;an insulating layer provided on said substrate;a semiconductor layer having a laminating portion of i-type semiconductor and n-type semiconductor provided on said insulating layer, wherein said semiconductor layer comprises, in this order from a side of said insulating layer, (i) an i-type layer including crystals whose average grain size is within a range of 50-350 .ANG. and including no impurity controlling the conductivity, (ii) an amorphous layer, including no impurity controlling the conductivity, said amorphous layer being arranged adjacent to said layer including the crystals, and (iii) n-type ohmic contact layers arranged in a spaced relation to each other on said amorphous layer; andan electrode provided on said ohmic contact layer.