Patent ID: 7305600
Filing Date: 2007-12-04
Classification: G01R,G11C

Abstract:
1. An integrated circuit, comprising: a multiplicity of identical macro-circuits, each macro-circuit of said multiplicity of identical macro-circuits being a logic circuit having the same function; a fuse bank containing a multiplicity of fuses, a state of said fuses storing test data indicating at least which macro-circuits failed a test; a scan multiplexer and control circuit connected to scan-in I/O pads and scan-out I/O pads and connected to each of said identical macro-circuits, said scan multiplexer and control circuit including means for selectively connecting said scan-in I/O pads and scan-out I/O pads to and disconnecting said scan-in I/O pads and scan-out I/O pads from each of said macro-circuits of said multiplicity of identical macro-circuits during testing of said multiplicity of identical macro-circuits; means for isolating each macro-circuit of said multiplicity of macro-circuits from any other logic circuits of said integrated circuit chip and means for connecting scan-in and scan-out pins dedicated to each macro-circuit of said multiplicity of macro-circuits to respective pads of said scan-in I/O pads and scan-out I/O pads; means for permanently preventing utilization of those macro-circuits during operation of said integrated circuit that did not pass said test during operation of said integrated circuit, said means for permanently preventing responsive to said state of fuses in said fuse bank.