Patent ID: 7424506
Filing Date: 2008-09-09
Classification: G06F

Abstract:
1. A method comprising: analyzing input terms on a bit-wise basis to segment each level of bit significance of input terms into one or more groups of three bits, and/or one or more groups of two bits and/or one or more groups of one bit; designing a hyperpipelined series of Boolean function generators, based at least in part on the analyzing, to implement a Wallace-architecture of full-adders to receive at least a portion of the one or more groups of three bits, half-adders to receive at least a portion of the one or more of the groups of two bits, associated registers to receive at least a portion of the one or more the groups of one bit in the selected resources, and a multi-input adder to combine the input terms to produce intermediate summation results; selecting atomic elements of a dedicated logic device in which to implement the Wallace-architecture of full-adders, half-adders, and associated registers; selecting atomic elements to implement control logic, the control logic configured to dynamically reallocate the atomic elements implementing the Wallace-architecture of full-adders, half-adders, and associated registers in response to a subsequent analysis of the input terms on a bit-wise basis; selecting atomic elements to implement a first combinatorial module, the first combinatorial module to generate partial products of real components of a plurality of complex numbers; and selecting atomic elements to implement a second combinatorial module, the second combinatorial module to generate partial products of imaginary components of the complex numbers; wherein the partial products of the combinatorial modules form the input terms.