Patent ID: 6683604
Filing Date: 2004-01-27
Classification: G09G,H04N

Abstract:
A display system adapted to display input imaged data received one frame at a time at an input frame rate and an input resolution on a display having an output frame rate and an output resolution comprising:a pixel packing circuit adapted to generate coded image data, the coded image data being a compressed representation of the input image data and including a plurality of pixel bits and a palette bit, the palette bit selecting a palette for representing the plurality of pixel bits; and a pixel unpacking circuit adapted to generate output image data capable of being displayed on the display, the output image data generated by manipulating the plurality of pixel bits and the palette bit; where the pixel packing circuit includes: an input terminal adapted to receive the input image data; and a logic circuit adapted to generate the coded image data by logically manipulating the input image data; and where the input image data includes a plurality of digital image signals and wherein the logic circuit includes: a first adder adapted to generate a first adder signal by adding the plurality of digital image signals; a second adder adapted to generate a second adder signal by adding the first and second portions of the first adder signal; a plurality of registers coupled to the second adder and each adapted to store sequential second adder signals; and a first plurality of comparators adapted to generate a plurality of pixel bits by comparing the second adder signal to a first threshold limit; a second plurality of comparators adapted to compare the second adder signal to a second threshold limit; and a logic gate adapted to generate a palette bit by logically manipulating signals output from the second plurality of comparators.