Patent ID: 8001448
Filing Date: 2011-08-16
Classification: G06F,H03M

Abstract:
1. A semiconductor memory device comprising an error detecting and correcting system for detecting and correcting an error bit of read out data with a BCH code, wherein the error detecting and correcting system includes: a 3EC system and a 2EC system configured to be able to detect and correct 3-bit errors and up to 2-bit errors, respectively, either solution results of the 3EC system or 2EC system being selected in accordance with an error situation; and a warning signal generating circuit configured to generate a warning signal designating that there are 4-bit or more errors in case syndromes are not in an all “0” state, and in case no error location is searched with whichever of the 3EC system and 2EC system, the 2EC system is configured to perform variable transformation on a 2-degree error searching equation using one parameter to divide it into a first part containing only an unknown number and a second part calculative with syndromes, and compares previously nominated solution indexes collected in a table and syndrome indexes with syndrome indexes to determine error position, and wherein, in the calculation of congruences defined by the nominated indexes and syndrome indexes in both of the 3EC system and 2EC system, each congruence with mod 2