Patent ID: 6825053
Filing Date: 2004-11-30
Classification: G11C,H01L

Abstract:
A method for validating the position of a word line overlaying a trench capacitor, comprising the steps of:providing a wafer having at least one scribe line region and a memory cell region; forming a test key in the scribe line region and a plurality of memory cells in the memory cell region, wherein the test key comprises: a trench capacitor deposited in the scribe line region and has a buried plate; a rectangular word line deposited in the scribe line region and covers a portion of the trench capacitor; a first and second passing word line deposited above the trench capacitor; a first and second doping region respectively deposited between the rectangular word line and the first passing word line, and the rectangular word line and the second passing word line; a first plug coupled to the first doping region; a second plug coupled to the second doping region; and a third plug coupled to the buried plate; measuring a first current between the first and third plug resulting from applying a predetermined voltage difference between the first and third plug, applying a predetermined voltage level on the rectangular word line and floating the second plug, and a second current between the second and third plug resulting from applying the predetermined voltage difference between the second and third plug, applying the predetermined voltage level on the rectangular word line and floating the first plug; and validating the position of the rectangular word line by the measured first and second currents.