Patent ID: 6080626
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A process for fabricating an EEPROM memory device formed on a semiconductor material substrate of a first conductivity type having a first and second memory cell formed symmetrically to each other, said process comprising the steps of:forming a sacrificial oxide layer on the semiconductor substrate;depositing a first layer of a light-sensitive material having a first window on a first portion of the sacrificial oxide layer to produce a first capacitive implant mask;implanting, at a predetermined first inclination angle, a single dopant of a second conductivity type through the first window to form a first region of electrical continuity;depositing a second layer of a light-sensitive material having a second window, on a second portion of the sacrificial oxide layer to produce a second capacitive implant mask;implanting, at a predetermined second inclination angle, the single dopant through the second window to form a second region of electrical continuity;removing the light-sensitive material and the sacrificial oxide layer;forming a first gate oxide region on the semiconductor substrate over the first region of electrical continuity and a second gate oxide region on the semiconductor substrate over the second region of electrical continuity;etching a first window from the first gate oxide region relative to the first region of electrical continuity and a second window from the second gate oxide region relative to the second region of electrical continuity;growing a first tunnel oxide region in the first window and a second tunnel oxide region in the second widow, a thickness of the first and second tunnel oxide regions being less than the thickness of the first and second gate oxide regions;forming a first floating gate region over the first gate oxide region and a second floating gate region over the second gate oxide region;forming a first control gate region over the first floating gate region and a second control gate region over the second floating gate region; andforming source/drain diffusion regions of the second conductivity type in the semiconductor substrate relative to the first and second gate oxide regions.