Patent ID: 6570410
Filing Date: 2003-05-27
Classification: G11C,H03K,H03M

Abstract:
A double-sampled sample and hold system, comprising:a double-sampled sample and hold circuit operable to sample an analog signal using both a rising and falling edge of a sampling clock signal, wherein the double-sampled sample and hold circuit comprises two generally parallel sampling circuits which are selectively coupled to an operational amplifier via a switching network, wherein each of the sampling circuits comprises a sampling capacitor which is operable to sample the analog signal in accordance with one portion of the sampling clock signal, and wherein each sampling circuit is further operable to hold a previous sample value from the respective sampling capacitor in a feedback connection with the operational amplifier, and further wherein the switching network is operable to coordinate a sampling of the analog signal by the generally parallel sampling circuits in an alternating fashion via a plurality of clock phase signals; and a clock phase signal generator circuit operably coupled to the doublesampled sample and hold circuit, and operable to generate four clock phase signals, wherein two of the clock phase signals dictate a timing by which the switching network switches an operation of a respective one of the generally parallel sampling circuits between a sample mode and a hold mode, and wherein another two of the clock phase signals comprise pre-phase signals which define a sampling instant for a respective one of the generally parallel sampling circuits, and wherein a falling edge signal transition of each of the pre-phase signals occurs before a falling edge signal transition of a respective clock phase signal which dictates the switching network timing, and wherein a falling edge of each of the pre-phase signals is dictated by a global clock signal, wherein the clock phase generator subcircuit comprises: a latch circuit operable to generate two output signals which are complimentary to one another, and wherein a logic state of the two output signals change at a rate dictated by the global clock signal; a first clock signal path circuit, comprising: a NAND gate having an input coupled to one of the output signals of the latch circuit, and an output; a first inverter having an input coupled to the output of the NAND gate, and having an output; a second inverter having an input coupled to the output of the first inverter, and an output; a third inverter having an input coupled to the output of the second inverter, and an output; a pull-up circuit coupled to the output of the third inverter and the output of the NAND gate, and operable to pull the output of the third inverter to a high logic state when the output of the NAND gate transitions to a low logic state; a fourth inverter having an input coupled to the output of the third inverter, and an output; and a fifth inverter having an input coupled to the output of the fourth inverter, and an output which produces one of the two clock signals used for sampling; a second clock signal path circuit, comprising: a NAND gate having an input coupled to the other one of the output signals of the latch circuit, another input coupled to the output of the fourth inverter of the first clock signal path circuit, and an output; a first inverter having an input coupled to the output of the NAND gate, and having an output; a second inverter having an input coupled to the output of the first inverter, and an output; a third inverter having an input coupled to the output of the second inverter, and an output; a pull-up circuit coupled to the output of the third inverter and the output of the NAND gate, and operable to pull the output of the third inverter to a high logic state when the output of the NAND gate transitions to a low logic state; a fourth inverter having an input coupled to the output of the third inverter, and an output coupled to another input of the NAND gate of the first clock signal path circuit; and a fifth inverter having an input coupled to the output of the fourth inverter, and an output which produces the other one of the two clock signals used for sampling.