Patent ID: 8413127
Filing Date: 2013-04-02
Classification: G06F

Abstract:
1. An apparatus for minimizing effective memory latency, the apparatus comprising: a bus; a main memory connected to the bus, wherein the main memory having computer executable program code stored therein; a processor connected to the bus, wherein the processor executes the computer executable program code to direct the apparatus to: analyze a portion of code that contains one or more loops, to form a loop table; identify at least one candidate loop within the one or more loops of the loop table for prefetch efficiency optimization; insert prefetch control instructions and directives to optimize the at least one candidate loop, wherein the prefetch control instructions and directives are inserted at selected locations in an instruction stream, in advance of data use, according to a stream type, and wherein a stream is a sequence of addresses which depend upon an induction variable of the at least one candidate loop; determine whether pipelining is available; responsive to a determination that pipelining is not available, adjust prefetch addresses in the prefetch control instructions forward to fetch cache lines in advance of data use; gather memory references of the at least one loop; and perform at least one of data dependency analysis and reuse analysis on the at least one candidate loop to identify unique streams within the at least one candidate loop.