Patent ID: 6489224
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A method for engineering the threshold voltage of a device, said method comprising:providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first NFET transistor in said substrate, said first NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region, wherein; said first NFET has a first threshold voltage; and forming a second NFET transistor in said substrate, said second NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a buried platform well formed below said second active region, wherein; said buried platform well is specifically formed such that a portion of dopant comprising said buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second NFET transistor with respect to said first threshold voltage of said first NFET transistor.