Patent ID: 7633316
Filing Date: 2009-12-15
Classification: H03K

Abstract:
1. A multiplexer, comprising: first NAND gates each including a first input configured to receive a first group select signal and a second input configured to receive a respective first data signal; first transmission gates each including an input coupled to an output of one of the first NAND gates and a first select input configured to receive a respective first select signal; second NAND gates each including a first input configured to receive a second group select signal and a second input configured to receive a respective second data signal; second transmission gates each including an input coupled to an output of one of the second NAND gates and a second select input configured to receive a respective second select signal; and a third NAND gate including a first input coupled to an output of each of the first transmission gates and a second input coupled to an output of each of the second transmission gates.