Patent ID: 9142290
Filing Date: 2015-09-22
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a memory cell array including first wirings each extending in a first direction, second wirings each extending in a second direction crossing the first direction, and a memory cell connected between the first wirings and the second wirings; and a control circuit unit configured to select a selected memory cell from the memory cells, perform a first operation of changing a resistance state of the selected memory cell between a first resistance state and a second resistance state different from the first state, determine whether the first operation has been properly performed or not, and perform retry operation of applying a retry pulse when the first operation has not been properly performed, wherein the control circuit unit is configured to inhibit use of the selected memory cell in accordance with the number of times of excessive retry operation, the excessive retry operation is an operation when the number of times of the retry operation for the selected memory cell is over k times (k being an integer of 1 or more).