Patent ID: 6069502
Filing Date: 2000-05-30
Classification: G11C

Abstract:
An integrated sample-and-hold (S/H) circuit for an input signal and comprising:a substrate;a sampling capacitor formed on said substrate;a first field-effect transistor (FET) formed on said substrate and having a first conduction terminal for receiving the input signal, a second conduction terminal connected to said sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to said sampling capacitor during a sampling time and for disconnecting the input signal from said sampling capacitor during a holding time, said first FET further comprising a body creating a parasitic diode connected to said sampling capacitor;a buffer amplifier having an input connected to said sampling capacitor and an output connected to the body of said first FET during the holding time for applying a holding voltage from said sampling capacitor to the body of said first FET to thereby reduce undesired effects from the parasitic diode; andsubthreshold conduction current compensation means connected to said first FET for reducing undesired effects of subthreshold conduction current in said first FET during the holding time.