Patent ID: 6320236
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A logic gate semiconductor apparatus, said apparatus comprising:a silicon semiconductor substrate member;at least one pair of opposing, spaced apart isolation trench regions fabricated on said semiconductor substrate member; anda logic gate comprising of at least two, spaced apart transistors disposed between said trench regions, each said transistor being fabricated as a MOS semiconducting device, said MOS semiconducting device comprising a polysilicon-oxide MOS gate structure having a channel region, a source region, and a drain region fabricated beneath said polysilicon-oxide MOS gate structure, each said polysilicon-oxide MOS gate structure being spaced apart from an adjacent polysilicon-oxide MOS gate structure by a distance Ls,each said transistor having an optimized asymmetric channel region whose impurity profile comprises a higher dopant concentration on a drain side than on a source side, said dopant concentration being optimally implanted according to said transistor's functional characteristic in said logic gate,said dopant concentration being implanted at a fabrication implanting step utilizing a criss-cross form of implanting technique,wherein, said MOS gate structure comprises a channel length in a range of 50-200 nm; and having said dopant concentration optimized to achieve a gate delay time in the range of 20-50 pico-seconds for a 4 input Nand gate device having a load of 50 fF, andwherein said dopant concentration comprises boron implanted at a first tilt angle a1 ranging from 7.degree. to 25.degree. in magnitude, said boron being implanted at an implant energy ranging from 15 to 25 KeV, and at a first concentration level ranging from 1.0 to 2.5 10.sup.13 atom/cm.sup.3 ; andwherein said dopant concentration also comprises boron implanted at a second tilt angle a2 ranging from 7.degree. to 35.degree. in magnitude, said boron implanted at said second tilt angle being implanted at an implant energy ranging from 70 to 100 KeV, and at a second concentration level ranging from 1.0 to 2.5 10.sup.13 atom/cm.sup.3 to obtain identical operating characteristics between logic gate inputs.