Patent ID: 7345528
Filing Date: 2008-03-18
Classification: H03F

Abstract:
1. A digital signal processing system comprising a clock signal preamplifier that converts an input signal to an output signal, the clock signal preamplifier comprising: first and second transistors of first conductivity type, each having first and second primary terminals and a control terminal, differentially coupled relative to each other, with their first terminals commonly coupled to a first circuit voltage node; third and fourth transistors of second conductivity type, opposite the first conductivity type, each having first and second primary terminals and a control terminal, differentially coupled relatively to each other, with their first terminals commonly coupled to a second circuit voltage node; and complementarily coupled to the first and second transistors, with the second terminals of the first and third transistors commonly coupled to provide a first component of a differential output signal and the second terminals of the second and fourth transistors commonly coupled to provide a second component of the differential output signal; phase splitter circuitry connected and configured for receiving and splitting the phase of respective first and second components of a differential input signal, and for providing first and second phase split outputs corresponding to the first and second components to the control inputs of the first, third, second and fourth transistors, respectively; and clamper circuitry coupled to a reference voltage node, and connected and configured for clamping voltages of the first and second components of the differential output signal, respectively.