Patent ID: 6140224
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method of forming an electrically conducting structure over a semiconductor wafer, said method comprising the steps of:forming a dielectric layer over said semiconductor wafer for isolation;forming a polishing stop layer on said dielectric layer;etching said polishing stop layer and said dielectric layer to form an opening aligned to an underlying conductive region;forming a titanium (Ti) layer on said polishing stop layer and on a surface of said opening to act as an adhesive layer;forming a titanium-nitride (TiN) layer on said Ti layer to act as a barrier layer;forming a tungsten layer on said TiN layer;performing an etching back process to etch said tungsten layer to a surface of said titaniun nitride layer, tungsten residules being formed on a surface of said titanium nitride layer;polishing said titanium nitride layer, said titanium layer by using a chemical mechanical polishing (CMP) with a slury for removing dielectric, thereby removing said tungsten residules and said CMP being stop on said polishing stop layer.