Patent ID: 7709931
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A trenched semiconductor device characterized by comprising: a substrate of semiconducting material having a first and a second opposite major surface; there being a plurality of inside trenches formed in said substrate, each inside trench extending from said first major surface of said substrate toward said second major surface thereof; there being an outside trench formed in said substrate outwardly of said inside trenches and extending from said first major surface of said substrate toward said second major surface thereof; a first semiconductor region of a first conductivity type formed in said substrate contiguous to said inside trenches and exposed at said first major surface of said substrate; a second semiconductor region of a second conductivity type formed in said substrate and contiguously underlying said first semiconductor region, said second semiconductor region being contiguous to both of said inside trenches and said outside trench and being exposed in part at said first major surface of said substrate; a third semiconductor region of said first conductivity type formed in said substrate contiguous to both of said second semiconductor region and said inside trenches, said third semiconductor region being buried deeper in said substrate from said first major surface thereof than said inside trenches; a fourth semiconductor region of said first conductivity type formed in said substrate contiguous to all of said second and said third semiconductor region and said outside trench and partly exposed at said first major surface of said substrate on the outside of said outside trench, said fourth semiconductor region being less in impurity concentration than said third semiconductor region; an insulating film in each of said inside trenches and said outside trench; a plurality of trench conductors received one in each of said inside trenches and said outside trench via said insulating film; a first primary electrode electrically coupled to said first semiconductor region; a second primary electrode electrically coupled to said fourth semiconductor region; and a gate electrode electrically coupled to said trench conductors.