Patent ID: 7761662
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. A cache memory device connected to a processor and a main memory, comprising: a cache memory having a plurality of cache lines, each cache line including a data storage area for storing data read out from the main memory, a tag storage area for storing all or part of an address where the data is stored in the main memory, and a capacity storage area for storing a capacity value of the data storage area; a comparison operation unit configured to generate comparisons of the addresses stored in the tag storage areas with a requested address contained in a read request from the processor, the comparisons using the capacity values stored in the capacity storage areas, and, if a comparison indicates an address in an identified tag storage area coincides with the requested address, to instruct an identified data storage area corresponding to the identified tag storage area to read data; and a capacity value determination unit configured to determine the capacity values for the capacity storage areas and to store the determined capacity values in the capacity storage areas.