Patent ID: 6664836
Filing Date: 2003-12-16
Classification: H03K

Abstract:
A phase splitter circuit, comprising:a clock delay section adapted to receive a clock signal and configured to produce a first delayed clock signal and a second delayed clock signal, wherein the first and second delayed clock signals are time delayed versions of the received clock signal, and wherein the second delayed clock signal is delayed in time to a greater extent than the first delayed clock signal; a signal converter section adapted to receive a static logic signal, the clock signal, and the first delayed clock signal, and configured to convert the static logic signal to a dynamic logic signal dependent upon the clock signal and the first delayed clock signal; and a signal generator section adapted to receive the dynamic logic signal, the first delayed clock signal, and the second delayed clock signal, and configured to produce a pair of complementary dynamic logic output signals dependent upon the dynamic logic signal, the first delayed clock signal, and the second delayed clock signal, wherein one of the complementary dynamic logic output signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal.