Patent ID: 6477675
Filing Date: 2002-11-05
Classification: G11C

Abstract:
An integrated circuit having a plurality of external terminals adapted to receive respective signals, comprising:electronic circuitry having inputs coupled to at least some of the external terminals and outputs coupled to at least some of the external terminals, the electronic circuitry generating signals on its outputs responsive to signals on its inputs to execute a desired function; a clock terminal adapted to receive an external clock signal; a clock generator circuit having an input coupled to the clock terminal, and developing an internal clock signal having a phase relative to the external clock signal in response to a phase command; a latch coupled to at least some of the external terminals and the clock generator circuit, the latch storing digital signals applied on the external terminals responsive to the internal clock signal; a pattern generator that generates expect data for a repeating bit sequence applied on the external terminals, comprising, a register having a plurality of inputs and outputs, and a clock terminal adapted to receive a clock signal, the register shifting data applied on each of its inputs to a corresponding output responsive to the clock signals; a switch circuit having a plurality of first signal terminals coupled to receive latched digital signals from the latch, a plurality of second signal terminals coupled to corresponding inputs of the register, and a control terminal adapted to receive a seed signal, the switch circuit coupling each first signal terminal to a corresponding second signal terminal responsive to the seed signal being active; a logic circuit coupled between the register inputs and outputs, and having a terminal adapted to receive the seed signal, the logic circuit generating, when the seed signal is inactive, new expect digital signals on the register inputs responsive to current expect digital signals provided on the register outputs; and a synchronization circuit coupled to the latch, clock generator, and pattern generator, the synchronization circuit, during a synchronization mode of the integrated circuit, activating the seed signal to seed the pattern generator with a data pattern captured by the latch, and thereafter deactivating the seed signals, sequentially adjusting the phase command, and comparing the digital signals stored by the latch to expected values developed by the pattern generator, the synchronization circuit determining an optimum phase command from the results of the comparisons and applying that phase command to the clock generator during normal operation of the electronic circuitry.