Patent ID: 7550339
Filing Date: 2009-06-23
Classification: H01L

Abstract:
1. A method for fabricating an array of memory cells, the method comprising: forming in a substrate, in a column direction, a plurality of source and drain regions, each memory cell comprising a pair of source and drain regions in the column direction; forming a plurality of low dielectric constant oxide isolation areas in the substrate and extending in the column direction, each isolation area formed between adjacent source and drain regions in a row direction; forming a tunnel insulator over the substrate, in the column direction, between each isolation area and over each source and drain region; forming a metal floating gate over each tunnel insulator in the column direction; forming a metal oxide inter-gate insulator over each floating gate and isolation area in a row direction; and forming a control gate over each inter-gate insulator in the row direction wherein the tunnel insulator, the metal floating gate, and the metal oxide inter-gate insulator comprise a composite gate insulator that is taken from a list of structures, the list of structures comprising: Ta