Patent ID: 6363019
Filing Date: 2002-03-26
Classification: G11C

Abstract:
An integrated circuit (IC) device comprising:a plurality of write lines for transmitting configuration data values; a plurality of read lines; a plurality of first volatile memory cells, each first volatile memory cell including a first terminal, a second terminal, and a latch selectively connected to an associated write line of the plurality of write lines through the first terminal, and to an associated read line of the plurality of read lines through the second terminal; a comparator having a plurality of first input terminals connected to the plurality of write lines, a plurality of second input terminals connected to the plurality of read lines, wherein, when first configuration signals are transmitted on the plurality of write lines, in response to a first address signal, each first volatile memory cell passes a first configuration data value from its associated write line to its latch through its first terminal, and transmits a first stored data value from its latch to its associated read line through its second terminal, and wherein the comparator generates a control signal only when the first configuration data values transmitted on the plurality of write lines are equal to the first stored data values transmitted on the plurality of read lines.