Patent ID: 8958245
Filing Date: 2015-02-17
Classification: G11C,H01L

Abstract:
1. A non-volatile memory cell comprising: a coupling device formed in a first conductivity region; a first select transistor serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region; a control line electrically connected to the coupling device; a word line electrically connected to a gate of the first select transistor; a select gate electrically connected to a gate of the second select transistor; a bit line electrically connected to a drain region of the second select transistor; and a source line electrically connected to a source region of the first select transistor; wherein an electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.