Patent ID: 6566739
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A semiconductor package, comprising:a lead frame including: a die pad having a lower surface and an upper surface; a plurality of inner leads extending inwardly toward the die pad; and a plurality of outer leads integrated with the inner leads and extending outwardly; a lower chip attached to the lower surface of the die pad, said lower chip comprising an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad; an upper chip attached to an upper surface of the die pad, said upper chip comprising an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the upper surface of the die pad; an upper and lower tape wiring boards each including: a polymeric tape having windows patterned therein, the polymeric tape having a lower and upper surfaces; metal patterns formed on the lower surface of the polymeric tape at either side of said windows, said metal patterns having pad connection portions exposed from the windows, and lead connection portions extruding from the polymeric tape; and an adhesive layer formed overlying the metal patterns on each of the upper tape wiring board and the lower tape wiring board, the adhesive layer being attached to a respective one of the active surfaces of the upper chip and the lower chip, wherein the windows of the lower and upper tape wiring boards expose the electrode pads of the lower and upper chips, respectively; each of the pad connection portions electrically connected to a respective one of the electrode pads; and each of the lead connection portions electrically connected to a respective one of the inner leads.