Patent ID: 7596196
Filing Date: 2009-09-29
Classification: G11B,H04L

Abstract:
1. A timing recovery system for use in data block error recovery operations, the system including: an analog-to-digital converter that produces digital values associated with samples of an analog signal that corresponds to the data block; a fast detector that produces first bit values that correspond to the digital values by decoding respective portions of the sampled signal; an iterative detector that produces second bits values that correspond to the digital values by iteratively decoding the entire data block; a timing sub-system for producing a clocking signal that sets a sampling rate for the analog-to-digital converter, the timing sub-system producing the clocking signal based in part on detected phase errors between a bit rate of the signal and the sampling rate, the timing sub-system operating during error recovery rereads to a loss of lock detector that determines for each decoding of the data block if a loss of lock has occurred in the timing sub-system, and a controller for providing the first and second bit values to the timing sub-system, the controller providing the second bit values after an error recovery reread occurs without a loss of lock.