Patent ID: 6742065
Filing Date: 2004-05-25
Classification: G06F

Abstract:
An interrupt controller, comprising:first storing unit for storing an interrupt request received from one or more of a plurality of interrupt sources; a priority determination unit which is operatively coupled to the first storing unit, wherein the priority determination unit (i) determines a priority level of the interrupt sources to determine which interrupt request in the first storing unit has a highest priority, (ii) generates indexes based on a determined priority level of the interrupt sources and (iii) generates and outputs a non-vectored signal to a CPU to inform the CPU of an interrupt request; a vector generator for generating a vector based on indexes output from the priority determination unit, wherein the vector corresponds to an interrupt source having a highest priority; second storing unit for storing the vector output from the priority determination unit; an instruction generator that converts the vector into a branch instruction that addresses an interrupt service routine, wherein the instruction register outputs the branch instruction or a CPU instruction to a CPU; and a control logic for controlling overall operations of the interrupt controller.