Patent ID: 6393592
Filing Date: 2002-05-21
Classification: G01R

Abstract:
A scan flop cell, comprising:a D flip-flop; a scan multiplexer; a clock multiplexer, the clock multiplexer being configured to receive a functional clock and a scan clock; and asynchronous reset blocking circuitry, the asynchronous reset blocking circuitry including, a multiplexer being connected to an output of the scan multiplexer and to the data terminal D, the multiplexer having an output that connects to a data node of the D flip-flop; an AND gate having an input connected to the data terminal D and another input connected to a Not Reset (NR) terminal of the scan flop cell, an output of the AND gate connects to the scan multiplexer; and an OR gate having one input connected to the scan mode terminal and another input connected to the Not Reset (NR) terminal, an output of the OR gate being coupled to a reset terminal of the D flip flop.