Patent ID: 6713357
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having reduced parasitic capacitance, comprising sequential steps of:(a) providing a semiconductor substrate including a surface with at least one MOS transistor structure therein or thereon, including a spaced-apart pair of shallow depth source and drain regions and an electrically conductive gate electrode having first and second opposing side surfaces and a top surface; (b) forming a thin, L-shaped sidewall spacer of a high dielectric constant (high-k) insulator material on each of said first and second opposing side surfaces of said gate electrode, each said thin, L-shaped sidewall spacer having a vertical portion extending for about 1,000-1,500 Ã¥ along e a respective side surface of said gate electrode to said top surface of said gate electrode and a horizontal portion extending on said substrate surface for a distance of about 500-800Ã¥; and (c) forming a layer of a low dielectric constant (low-k) insulator material over at least said vertical and horizontal portions of each of said thin, L-shaped sidewall spacers, whereby parasitic capacitance between said gate electrode and each of said source and drain regions is reduced.