Patent ID: 6711668
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A prefetch buffer for holding instructions in a processor having a memory and an instruction decode unit, the prefetch buffer comprising:a plurality of storage locations, each having the same bit capacity and arranged in groups with the same number of storage locations in each group; a write port for selectively writing words having a bit length corresponding to the bit capacity of each storage location multiplied by the number of storage locations in each group from the memory into respective groups of the prefetch buffer; read circuitry for reading instructions out of the prefetch buffer in dependence on an instruction mode of the processor, said instruction mode controlling a number of storage locations which are read during a machine cycle; and means for indicating when all storage locations in a group have been read so that a fetch signal can be issued to fetch a next word from the memory into the storage locations of that group.