Patent ID: 6285614
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A memory device, comprising:a memory cell having first and second terminals, the second terminal being coupled to a voltage reference;a decoder having input and output nodes, the output node being coupled to the first terminal of the memory cell; anda voltage regulator coupled to the first terminal of the memory cell via the decoder, the voltage regulator being structured to provide a regulated voltage to the decoder input node in such a manner that self-limits a current to the memory cell and provides the memory device with a loop gain that is independent of how many programmed memory cells are supplied by the regulated voltage of the voltage regulator, wherein the voltage regulator includes:a differential stage having first and second input terminals and an output terminal, the output terminal providing a differential voltage based on voltages at the input terminals; anda connecting transistor configured as a source follower and having a control terminal coupled to the output terminal of the differential stage and an output terminal coupled to the input node of the decoder, wherein the connecting transistor is an NMOS triple-well transistor.