Patent ID: 6487706
Filing Date: 2002-11-26
Classification: G06F

Abstract:
A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, comprising the steps of:defining a size for the chip of a hierarchical design, removing blocked areas, including clock and power grid areas, leaving the wiring channels available for interconnecting the individual elements of the VLSI chip, from said available area, allocating a percentage of wiring levels for global and local wiring as parallel iterations for the global and local wiring; and as the parallel iterations for the global and local wiring progress, modifying the percentage to be allocated for global and local wiring, and during the parallel iterative process increasing the number of wires for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire; and defining a vertical slice of wiring resources used for the space above a macro entity, and checking the macro entity with the context of the VLSI chip physical design above it; and implementating a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools and wherein said blockage modeling tool keeps any adjacent wire at a spacing value greater than a minimum spacing away from a wire when the width of a wire is greater than a rule defined width.