Patent ID: 8202775
Filing Date: 2012-06-19
Classification: H01L

Abstract:
1. A process of forming an electronic device comprising: providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region; forming a vertically-oriented conductive region extending from the primary surface towards the underlying doped region, wherein the vertically-oriented conductive region includes a semiconductor material having a dopant concentration of at least 10 forming a horizontally-oriented doped region adjacent to the primary surface; forming a conductive electrode over the horizontally-oriented doped region, wherein the conductive electrode is spaced-apart from and electrically insulated from the vertically-oriented conductive region; and forming a gate electrode after forming the conductive electrode, wherein the electronic device includes a transistor that includes the underlying doped region, the vertically-oriented conductive region, the horizontally-oriented doped region, and the gate electrode.