Patent ID: 9083333
Filing Date: 2015-07-14
Classification: H02M,H03K

Abstract:
1. A switching circuit comprising: a plurality of insulated gate transistors connected in parallel between a high voltage line and a low voltage line; gate resistors, each being connected to one of the plurality of insulated gate transistors, wherein each of the gate resistors includes a first terminal and a second terminal, the first terminal of each of the gate resistors being connected to the respective gate electrode of each of the plurality of insulated gate transistors; a gate voltage application unit configured to apply pulsing gate voltage to the gate electrode of each of the plurality of insulated gate transistors, the gate voltage application unit being connected to the second terminal of each of the gate resistor via a gate voltage apply line; and a single fixed-value capacitor connected to a single location between the gate voltage apply line before or at the second terminal of one of the gate resistors and the high voltage line, wherein the single fixed-value capacitor substantially suppresses a surge voltage that is generated when the plurality of insulated gate transistors is synchronously turned off.