Patent ID: 6813732
Filing Date: 2004-11-02
Classification: G06F,H04B

Abstract:
A trace circuit built into a debugging circuit that is, in turn, built into a microcomputer for program debugging, said trace circuit tracing data on a bus of the microcomputer according to a bus clock signal and outputting a result to an emulator, said trace circuit comprising:a plurality of trace butter memories in which the data on the bus of the microcomputer is stored according to the bus clock signal; a control circuit storing the data on the bus in said trace buffer memories, cyclically and in a predetermined order, outputting the data stored in said trace buffer memories, cyclically and in a predetermined order, wherein the storage of data in and output of data from said trace buffer memories is synchronized with the bus clock signal, and said control circuit checks the number of bits of the data on said bus, and, if the number of bits of the data on said bus is no larger than a predetermined value, said control circuit stores the data on the bus in only some of said trace buffer memories, and outputs the data stored in said trace buffer memories, cyclically and in predetermined order; and an output terminal through which the data stored in said trace buffer memories is output to the emulator.