Patent ID: 6069033
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising a semiconductor body one surface of which is provided with a pair of transistors in the form of an n-channel MOST in a first active region and a p-channel MOST in a second active region, in combination with a non-volatile memory cell in the form of a MOST having a floating gate in a third active region, characterized by the following steps:providing a gate dielectric onto the surface of the semiconductor body in the first, second and third active regions;forming a semiconductor layer with a relatively weak dopant concentration on the dielectric layer;providing a mask which defines the floating gate in the semiconductor layer and which masks the parts of the semiconductor layer of the first and the second active region;etching of unmasked parts of the semiconductor layer thereby providing the floating gate with a pattern and removing the semiconductor layer situated above surface parts of the third active region next to the floating gate, while the first and the second active region remain completely covered by the semiconductor layer;providing a dopant having a relatively high dopant concentration in the uncovered parts of the third active region so as to obtain source and drain zones of a specific conductivity type for the MOST having a floating gate, during this doping step, at least portions of the semiconductor layer situated above the first and the second active region being masked against doping;forming the gates of the n-channel MOST and the p-channel MOST, and providing the n-type source and drain zones of the n-channel MOST and the p-type source and drain zones of the p-channel MOST by locally providing (a) dopant(s);providing the semiconductor layer situated above the first active region with an n-type dopant and the semiconductor layer situated above the second active region with a p-type dopant.