Patent ID: 6423594
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A method of fabricating a trench capacitor, the method comprising:providing a substrate; forming a patterned mask layer to expose a portion of the substrate; etching the exposed portion of the substrate to form a deep trench; forming a conductive diffusion region in the substrate, the conductive diffusion region surrounding a lower portion of the deep trench; forming a dielectric layer along with an inner surface of the deep trench; filling the trench with a first doped polysilicon layer; etching back the first doped polysilicon layer and the dielectric layer to a first depth, so that a first recess is formed on the first doped polysilicon layer to expose an upper portion of the inner sidewall of the deep trench; forming a collar dielectric layer on the exposed inner sidewall of the deep trench; filling the first recess with a second doped polysilicon layer; etching back the second doped polysilicon layer to a second depth, so that a second recess is formed on the second doped polysilicon layer to expose a part of the upper portion of the inner sidewall of the trench; etching the collar dielectric layer until a surface level thereof is lower than a surface level of the second doped polysilicon layer, so that a gap is formed on the collar dielectric layer between the exposed inner sidewall of the trench and the second doped polysilicon layer; filling the gap with a third polysilicon layer which will become doped and conductive after dopant diffused from the second polysilicon underneath; removing the patterned mask layer; and forming a drain region adjacent to the third polysilicon layer.