Patent ID: 6594176
Filing Date: 2003-07-15
Classification: B82Y,G11C,H01L,Y10S

Abstract:
A memory device, comprising:a plurality of memory cells arranged in an array; a plurality of first conductive lines disposed beneath the memory cells, the first conductive lines being positioned in a first direction; a plurality of second conductive lines disposed above the memory cells, the second conductive lines being positioned in a second direction, the memory cells being located at cross-points of the first and second conductive lines; and a plurality of current/voltage control (CVC) circuits including a current source and a current drain, the CVC circuits being coupled at each end of the first and second conductive lines, wherein the memory cells are addressable by applying a current from one of the CVC circuits to a CVC circuit at the opposite end of the first and second conductive lines, wherein the CVC circuits are arranged so that the length of the first and second conductive lines between each current source and drain is substantially the same for each memory cell addressed.