Patent ID: 6355563
Filing Date: 2002-03-12
Classification: H01L

Abstract:
A method of copper metallization in the fabrication of an integrated circuit device comprising:providing a metal line overlying a semiconductor substrate and having a nitride capping layer thereover; depositing a polysilicon layer over said nitride layer and patterning said polysilicon layer to form dummy vias; conformally depositing a dielectric liner layer overlying said nitride layer and said dummy vias; spinning-on a dielectric layer having a low dielectric constant overlying said dielectric liner layer and covering said dummy vias; polishing down said dielectric layer whereby said dummy vias are exposed; thereafter curing said dielectric layer whereby a cross-linked surface layer is formed in said dielectric layer; removing said dummy vias thereby exposing a portion of said nitride layer within via openings; thereafter removing said nitride layer exposed within said via openings; and filling said via openings with a copper layer and planarizing said copper layer to complete said copper metallization in said fabrication of said integrated circuit device.