Patent ID: 6556489
Filing Date: 2003-04-29
Classification: G11C

Abstract:
A system comprising:a processor; and a memory device coupled to the processor and comprising: a delay locked loop (DLL) circuit, wherein the DLL circuit comprises: a digital delay line comprising a plurality of delay elements and configured to receive an input signal and to produce an output signal, and wherein the input signal has a first phase and the output signal has a second phase; a phase detector configured to receive the input signal and the output signal and further configured to compare the first phase and the second phase and to produce a shift command output based on the comparison between the first phase and the second phase; and a shift register coupled between the phase detector and the digital delay line and configured to shift the input signal by an amount of time equivalent to one delay element in response to the shift command output from the phase detector; and a counter coupled to the DLL circuit and configured to track an amount of delay in the DLL circuit.