Patent ID: 6876353
Filing Date: 2005-04-05
Classification: G11C

Abstract:
1. A shift register comprising a plurality of stages, wherein an output signal having a predetermined level is successively output from each stage of the plurality of stages, each said stage comprising: a first transistor which includes a control terminal, a first terminal, and a second terminal, wherein a previous stage output signal is inputted into the first terminal from one of a stage which is one stage before the stage, an external controller and a final stage, and is output via the second terminal if the previous stage output signal has a predetermined level; a second transistor which includes a control terminal connected to the second terminal of said first transistor by wiring, a first terminal and a second terminal, wherein the second transistor accumulates charges in a capacity having the wiring connected with the control terminal of said second transistor as one pole by a clock signal inputted into the first terminal of said second transistor and outputs the clock signal as a first output signal of the stage via the second terminal of said second transistor; and a potential holding section (i) to displace a potential of said wiring to a predetermined level when a subsequent stage output signal having the predetermined level is inputted from one of a stage which is one stage after the stage, an external controller, and a first stage, and (ii) to hold the potential of said wiring, at the predetermined level until the previous stage output signal having the predetermined level is inputted; wherein the potential holding section comprises: