Patent ID: 7793127
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. A system comprising: a plurality of processors on a platform; a chipset coupled to the plurality of processors, the chipset to identify when a first processor of the plurality of processors is to be put into a low power state or raised from a low power state to a normal state; a volatile memory store coupled to the first processor to store machine context associated with the first processor in a portion of the volatile memory, wherein the portion of volatile memory is reserved for firmware use and inaccessible to an operating system on the platform; a system management interrupt handler operating on the first processor on the platform to save machine context in the volatile memory store, in response to a request to put the first processor into a low power state, and to restore machine context in response to a request to raise the first processor from a low power state to a normal state, wherein the system is further configured to identify when a second and/or subsequent processor on the platform is to be put into a low power state or raised from a low power state to a normal state, and further configured to save machine context for the second and/or subsequent processors to volatile memory in response to a request to put the second and/or subsequent processor into a low power state, and to restore machine context from volatile memory in response to a request to raise the second and/or subsequent processor from a low power state to a normal state.