Patent ID: 6499044
Filing Date: 2002-12-24
Classification: G06F

Abstract:
A leading zero/leading one anticipator that can operate in parallel with a floating point adder, comprising:a first logic level that generates a first plurality of PGZ patterns that correspond to a first plurality of dit positions of the adder result, and a second plurality of carry out signals that correspond to a second plurality of dit positions of the adder result; a second logic level that combines said PGZ patterns with said carry-out signals to produce a find-zero and a find-one output signal for a third plurality of two-dit groups of the adder result; a third logic level that combines said find-zero and find-one output signals for said third plurality of two-dit groups to produce a find-one coarse shift select signal, a find-zero coarse shift select signal, a plurality of find-one medium shift select signals, and a plurality of find-zero medium shift select signals.