Patent ID: 6484271
Filing Date: 2002-11-19
Classification: G11C

Abstract:
An apparatus, comprising:an address bus; a random access memory including a number of addressable memory locations each accessed by a different one of a number of addresses provided by the address bus, wherein the random access memory has a tristate output coupled to the data bus and the tristate output is disabled when any one of the match signal lines is activated; a content addressable memory operable to store a number of defective location addresses each corresponding to a defective addressable memory location of the random access memory, the content addressable memory being responsive to a match between an address provided by the address bus and one of the defective location addresses to activate a corresponding one of a number of match signal lines; a replacement memory coupled to the content addressable memory by the match signal lines, the replacement memory including a number of replacement memory locations each accessed by activating a different one of the match signal lines; and a data bus coupled to the random access memory and the replacement memory, the random access memory being operable to output memory information on the data bus when addressed by one of the addresses other than one of the defective location addresses for a first read operation, the replacement memory being operable to output replacement information in the data bus in response to activation of a respective one of the match signal lines for a second read operation, defective information in the random access memory being accessed in response to the second read operation and output of the defective information on the data bus being prevented in response to the activation of the respective one of the match signal lines.