Patent ID: 7495976
Filing Date: 2009-02-24
Classification: G11C

Abstract:
1. An integrated circuit comprising: at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of memory cells; a plurality of bit lines, each of said plurality of bit lines being coupled to a respective column of said memory cells; a plurality of word lines carrying respective word line signals, each of said plurality of word lines being coupled to a respective row of said memory cells to control coupling of said respective row of memory cells to said plurality of bit lines so as to provide access to data bits stored therein; an address decoder responsive to input memory addresses to generate said word line signals; and repair control circuitry responsive to a repair signal to control said address decoder during a memory access operation to an memory input address such that: a plurality of arrays of memory cells, said repair control circuitry independently controlling different ones of said plurality of arrays of memory cells to operate in said normal mode or said repair mode.