Patent ID: 7470630
Filing Date: 2008-12-30
Classification: H01L

Abstract:
1. A method of forming conductive lines in a first dielectric layer on top of a second dielectric layer on a semiconductor substrate, comprising: forming a mask on the first dielectric layer, the mask exposing a first set and a second set of locations on the first dielectric layer to an etchant, the mask including structure in regions adjacent one set of locations such that there are different etching rates at the first and second sets of locations; forming a first plurality of trenches at the first set of locations in the first dielectric layer; forming a second plurality of trenches at the second set of locations in the first dielectric layer, the second plurality of trenches being shallower than the first plurality of trenches and located over a interconnect metal line in the second dielectric layer; forming a plurality of interconnect metal lines in the first plurality of trenches; forming a plurality of dummy metals in the second plurality of trenches; and planarizing the plurality of interconnect metal lines and the plurality of dummy metals with the first dielectric layer so that at least one dummy metal is formed in the first dielectric layer that is thinner than the interconnect metal lines and has a distance to an interconnect metal line in the second dielectric layer that is greater than it otherwise would be, thereby reducing parasitic capacitance.