Patent ID: 8697526
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A semiconductor device manufacturing method comprising: forming a device isolation region for defining a plurality of active regions in a semiconductor substrate and forming a first alignment mark in the semiconductor substrate; forming a first gate interconnection which is formed, crossing over one of said plurality of active regions and which is linear and includes a gate electrode of a first transistor, and a second gate interconnection which is formed, crossing over the other of said plurality of active regions and which is linear, in parallel with the first gate interconnection over the semiconductor substrate with a gate insulation film formed therebetween and includes a gate electrode of a second transistor, and forming a second alignment mark over the semiconductor substrate; forming source/drain diffused layers of the first transistor and the second transistor respectively in the active regions; forming an insulation film over the semiconductor substrate and over the first gate interconnection and the second gate interconnection; forming a photoresist film over the insulation film; making alignment by using the second alignment mark and exposing on the photoresist film a first partial pattern for forming a first contact hole in the insulation film, overlapping at least a part of the first gate interconnection; making alignment by using the first alignment mark and exposing on the photoresist film a second partial pattern for forming the first contact hole in the insulation film, overlapping at least a part of the source/drain diffused layer of the second transistor; developing the photoresist film to form a first opening in the photoresist film at a portion where the first partial pattern and the second partial pattern have been exposed; etching the insulation film with the photoresist film as a mask to form in the insulation film the first contact hole down to the first gate interconnection and the source/drain diffused layer of the second transistor; and burying a first contact layer in the first contact hole.