Patent ID: 6253360
Filing Date: 2001-06-26
Classification: G01R,G06F

Abstract:
A timing generator means comprising a plurality of N timing generators, N being an integer of 2 or greater than 2, each of the N timing generators including a clock generator, a period generator and a clock data processing circuit, said timing generator means being arranged such that a timing of generation of a clock outputted from each of said clock generators is controlled based on data previously set in a memory provided in each of said clock generators, thereby to generate a clock at a desired timing from each of the clock generators, each of said clock data processing circuits including:a multiplier for multiplying by N a value of period data read out of period data memory of the associated clock data processing circuit; anda subtracter for performing a subtraction between the period data multiplied by N by said multiplier or the period data read out of the period data memory and clock data supplied from the outside,said timing generator means further including:means for supplying, only in the case that N or more period data are in succession, the period of each of said period data being a constant, period data read out of said period data memory to each of said multipliers to multiply the period data by N, thereby providing a control signal to each of said clock data processing circuits, said control signal enabling a subtraction value outputted from an output terminal of each of said subtracters and a next flag outputted from a carry signal output terminal of each of said subtracters when a value of the clock data is greater than that of the period data multiplied by N to be stored in the memory of each of said clock generators, said next flag representing that a clock is to be generated in the next cycle, andwhereby in the case of operating each timing generator in N way system, when clock data for generating a clock at a desired timing point in the next cycle is supplied together with period data read out of the associated period data memory, a next flag outputted from the carry signal output terminal of the associated subtracter and the subtraction value outputted from the output terminal of the associated subtracter can be stored in the memory of the associated clock generator.