Patent ID: 6107674
Filing Date: 2000-08-22
Classification: H01L,Y10T

Abstract:
A semiconductor device structure, comprising:a power semiconductor device having a top surface, the power semiconductor device being a substrate for the structure;a first metallization layer deposited over the top surface of the power semiconductor device;a first passivation layer deposited over the first metallization layer;a second passivation layer deposited over the first passivation layer, the second passivation layer comprising a polymer and having a thickness greater than one micron;a second metallization layer deposited over the second passivation layer; andat least one electronic component disposed above and connected to the second metallization layer; andwherein the polymer has a characteristic capability of withstanding high voltages, the second passivation layer thus providing a selected degree of galvanic isolation between the top surface of the power semiconductor device and the electronic component according to the polymer's capability of withstanding high voltages and the thickness of the second passivation layer.