Patent ID: 6992506
Filing Date: 2006-01-31
Classification: H03K

Abstract:
1. An integrated circuit device, comprising: a data inversion circuit that is configured to evaluate bit differences between first and second ordered groups of data received in parallel at inputs thereof by performing bit-to-bit comparisons between corresponding bits in the first and second ordered groups of data and is further configured to generate versions of the first and second ordered groups of data in parallel at outputs thereof, wherein the version of the second ordered group of data is an inverted version of the second ordered group of data when a number of bit differences between the version of the first ordered group of data and the second ordered group of data is greater than one-half the number of bits of data within the second ordered group of data, said data inversion circuit comprising an XOR circuit that is configured to receive the first and second ordered groups of data, a comparator that is configured to generate a first internal parity signal in response to signals generated by said XOR circuit and a parity signal generator that is configured to generate a second external parity signal in response to a first external parity signal and the first internal parity signal.