Patent ID: 6505287
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A virtual channel memory access controlling circuit for controlling accesses from a plurality of memory masters to a virtual channel memory having a plurality of channels, comprising:a channel information storing portion having a plurality of storage areas, each of said storage areas being assigned to any of said memory masters, each of said storage areas corresponding to each of said channels, each of said storage areas having a channel number and a memory address, said channel number identifying a channel, and said memory address being sent to said virtual channel memory; detecting means for detecting necessity of a change of assignment of storage area between said memory masters; changing means for dynamically changing the assignment of the storage area between said memory masters; and a plurality of idle counters, each of which corresponds to each of said memory masters, for increasing an idle count when the corresponding memory master is in an idle state and for clearing the idle count, when the corresponding memory master accesses said virtual channel memory, wherein the idle count is used as information for determining whether or not the corresponding memory master has not accessed said virtual channel memory for a predetermined time.