Patent ID: 6608514
Filing Date: 2003-08-19
Classification: G11C,H03K

Abstract:
A clock signal generator circuit comprising:an off-chip driver which has a specific signal delay time from when a control signal is inputted until it outputs data and which outputs data on the basis of the control signal; a first clock control circuit which receives a first clock signal and outputs a second clock signal synchronizing with the first clock signal and advanced in phase with respect to the first clock signal by at least the signal delay time in the off-chip driver; a second clock control circuit which receives a third clock signal and outputs a fourth clock signal synchronizing with the third clock signal, advanced in phase with respect to the third clock signal by at least the signal delay time in the off-chip driver, and having the same frequency as the second clock signal, and different in phase from the second signal; and an OR circuit which receives the second clock signal and the fourth clock signal and outputs the control signal for controlling the data output operation of the off-chip driver.