Patent ID: 6539439
Filing Date: 2003-03-25
Classification: G06F

Abstract:
An interface between a bus and a plurality of input/output (I/O) devices, the interface comprises:memory that includes a plurality of buffer sections; a gate coupled to the memory and the bus, wherein the gate, when active, operably couples the bus to the memory for transferring information therebetween at a rate of the bus; a first I/O controller operably coupled to a first buffer section of the plurality of buffer sections, wherein the first I/O controller controls, at a first data rate, first transactions of the information within the first buffer section for a first I/O device; a second I/O controller operably coupled to a second buffer section of the plurality of buffer sections, wherein the second I/O controller controls, at a second data rate, second transactions of the information within the second buffer section for a second I/O device; an arbitrator operably coupled to activate the gate to couple at least one line of the first buffer section and the second buffer section to the bus based on priority of at least one of: an ordering of the first and second I/O devices and the information, such that particular information is transferred between the line of the first or second buffer section and the bus; and device transactions, control transactions, and component transactions such that the first transactions are at least one of the device transactions and the control transactions, the second transactions are at least one of the device transactions, the control transactions, and the component transactions such that a component that provides the component transactions is directly coupled to the bus.