Patent ID: 6094727
Filing Date: 2000-07-25
Classification: G06F,G11C

Abstract:
A data rate control circuit, comprising:a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase;a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase;a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; anda clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.