Patent ID: 8181145
Filing Date: 2012-05-15
Classification: G06F

Abstract:
1. A method for generating a floorplan for a hierarchical circuit design, wherein the hierarchical circuit design is represented using a set of blocks, and wherein the floorplan specifies an arrangement for the set of blocks which satisfies a set of design constraints, the method comprising: receiving a non-reduced netlist for the hierarchical circuit design, which includes a description of circuit elements in the set of blocks; generating, by computer, a reduced netlist from the non-reduced netlist, wherein for a block in the set of blocks, the reduced netlist includes a description of only those circuit elements in the block that are part of the block's interface logic; and using the reduced netlist to generate the floorplan for the hierarchical circuit design which satisfies the set of design constraints, wherein generating the floorplan comprises: