Patent ID: 6789172
Filing Date: 2004-09-07
Classification: G06F,Y02D

Abstract:
A digital system comprising:at least one data processor operable to generate data fetch requests for data at corresponding addresses; a memory subsystem including: a plurality of data arrays for storing data, each data array consisting of at least one data line, each data line consisting of a plurality of data segments; a plurality of cache tag arrays, each cache tag array corresponding to one data array and the number of cache tag arrays being less than the number of data arrays, each cache tag array including a plurality of tag lines associated with a corresponding data line of a corresponding data array, each tag line storing a predetermined number of most significant bits of a cached address for said corresponding data line, and a valid bit for each data segment of said corresponding data line, each valid bit having a first state indicating the corresponding data segment is valid and a second state indicating the corresponding data segment is invalid; at least one RAM-set tag array, each RAM-set tag array corresponding to one data array and a sum of the number of cache tag arrays and the number of RAM-set tag arrays equaling the number of data arrays, each RAM-set tag array including: a global valid bit having a first state indicating at least some data in said corresponding data array is valid and a second state indicating all data in said corresponding data array is invalid, a base address register storing a base address for said corresponding data array, and a valid bit for each data segment of a corresponding data line of said corresponding data array, each valid bit having a first state indicating the corresponding data segment is valid and a second state indicating the corresponding data segment is invalid; cache control logic connected to each RAM-set tag array for selectively configuring each RAM-set tag array and said corresponding data arrays as cache extension or as directly addressable memory; a first set of comparators, each having a first input connected to said data processor to receive data fetch addresses and a second input connected to a corresponding one of said plurality of tag lines for detecting a match between a data fetch address and one of said predetermined number of most significant bits of a cached address of one of said plurality of tag lines; a second set of comparators, each having a first input connected to said data processor to receive data fetch addresses and a second input connected to a corresponding one of said at least one base address register for detecting a match between a data fetch address and said at least one base address; hit/miss logic connected to said plurality of data arrays and said first and second set of comparators, said hit/miss logic operative to indicate a RAM-set hit-hit if a RAM-set tag array and a corresponding data array are configured as cache extension, a predetermined number of bits of said data fetch address matches said at least one base address, a corresponding global valid bit indicates valid and a valid bit of a corresponding data segment indicates valid, indicate a RAM-set hit-miss if said RAM-set tag array and said corresponding data array are configured as cache extension, a predetermined number of bits of said data fetch address matches said at least one base address, said corresponding global valid bit indicates valid and said valid bit of said corresponding data segment indicates invalid, indicate a cache hit if a predetermined number of bits of said data fetch address matches a cached address of one of said plurality of tag lines and said valid bit of said corresponding data segment indicates valid, and grant said data processor access to a corresponding data segment on a RAM-set hit-hit or a cache hit.