Patent ID: 7187607
Filing Date: 2007-03-06
Classification: G11C

Abstract:
1. A semiconductor memory device having memory cells arranged in the form of an array, wherein a refresh period of a failed cell among said memory cells is shorter than that of a normal memory cell, said semiconductor memory device comprising: a control signal generated based on a refresh command for the purpose of performing a refresh of said memory cells; a counter for updating an internal row address generated by said counter in accordance with the control signal; a refresh redundancy ROM having a plurality of switches and fuses arranged in the form of a matrix, and a judgment circuit, in which, of a plurality of fuses, a fuse corresponding to an internal row address of a memory cell having poor refresh characteristics is not cut; and a row pre-decoder, wherein when said row pre-decoder receives said internal row address generated by said counter, if said row pre-decoder receives a coincidence signal from said judgment circuit indicating that said fuse corresponding to said internal row address of said memory cell is not cut, said row pre-decoder sets the MSB of said internal row address generated by said counter to be prescribed data.