Patent ID: 6581119
Filing Date: 2003-06-17
Classification: G06F

Abstract:
An interrupt controller provided between a CPU and at least one peripheral circuit, whereinsaid interrupt controller is responsive to an interrupt request entered from said peripheral circuit, said interrupt controller compares a priority of said interrupt request with a priority of interrupt processing presently running in said CPU, said interrupt controller outputs an interrupt request signal to said CPU when the priority of said interrupt request is higher than the priority of said interrupt processing presently running in said CPU, said interrupt controller receives a response signal from said CPU after said interrupt request signal is produced, said response signal representing completion of interrupt preparation in said CPU, said interrupt controller outputs interrupt identification data to said CPU so as to cause said CPU to execute interrupt processing designated by said interrupt request, said interrupt controller comprises a level information storing/renewing means which is responsive to said interrupt request signal to store level information representing the priority of said interrupt processing presently running in said CPU, said level information storing/renewing means temporarily transfers the level information of said suspended interrupt processing to a predetermined area of a storage medium when said interrupt processing presently running in said CPU is suspended in response to said interrupt request signal, said level information storing/renewing means reads said level information of said suspended interrupt processing from said storage medium and renews presently stored level information by the readout level information when said CPU restarts said suspended interrupt processing, said level information storing/renewing means comprises a level information storing section which stores the level information of said interrupt processing presently running in said CPU, and an information amount storable in said level information storing section is determined in accordance with a data length of the level information being set in accordance with each interrupt request generated from said peripheral circuit.