Patent ID: 6038629
Filing Date: 2000-03-14
Classification: G06F

Abstract:
A processing system, comprising:(a) a processor;(b) a memory circuit in circuit communication with said processor(c) a first bridge circuit in circuit communication with said memory circuit and a bus, said first bridge circuit interfacing between said memory circuit and said bus;(d) at least one peripheral circuit in circuit communication with said bus, said at least one peripheral circuit for receiving data from an external circuit, said at least one peripheral circuit transmitting the received data across said bus to said memory circuit via at least said first bridge circuit, said at least one peripheral circuit transmitting said received data across said bus in at least one portion including a final portion, said at least one peripheral circuit transmitting a predetermined interrupt data signal onto said bus after transmitting the final portion of the received data onto said bus;(e) an interrupt circuit in circuit communication with said processor via an interrupt bus; and(f) a second bridge circuit in circuit communication with said interrupt circuit and said bus, said second bridge circuit interfacing between said interrupt circuit and said bus; andwherein said interrupt circuit generates an interrupt signal to said processor across said interrupt bus responsive to receiving the predetermined interrupt data signal from said bus via said second bridge circuit, thereby assuring that said processor is interrupted after the final portion of the received data is stored in said memory circuit.