Patent ID: 6393531
Filing Date: 2002-05-21
Classification: G06F

Abstract:
An apparatus for completing memory requests between a memory controller and a computer memory, said apparatus comprising:a queue controller coupled to said memory controller and operative to detect when said memory controller initiates a memory request to said computer memory and further operative to generate memory control data for completing said memory request; at least one queue comprising: at least one top portion coupled to said queue controller and operative to receive said memory control data; a bottom portion coupled to said computer memory and operative to provide said memory control data to control the transfer of data between said memory controller and said computer memory; and a shift mechanism coupled between said at least one top portion and said bottom portion and operative to shift said memory control data from said at least one top portion to said bottom portion, wherein said at least one queue comprises a queue depth corresponding to the number of timing pulses required to complete said at least one memory request, and wherein said at least one queue comprises a valid read queue, a valid write queue, a no_ack queue, a first read quadword queue, a data quadword mask queue, an ID queue, a chip select queue and a bank queue, and wherein said apparatus is responsive to a system clock, said system clock providing a timing pulse and wherein said at least one top portion shifts said memory control data to said bottom portion in response to said timing pulse.