Patent ID: 6128721
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A processor, comprising:a first execution pipeline to execute a first instruction and including a first stage to generate a first result and a last stage to generate a final result;a register file to store the first result and the final result, the register file including a temporary register to store the first result of the first stage, a primary register to store the final result, and a multiplexer;a controller to make available the first result stored in the register file in the event that the first result is needed for the execution of a subsequent instruction, the multiplexer being controlled by the controller to select between the temporary and primary registers; andat least one additional execution pipeline to execute at least one additional instruction, the first instruction preceding a second instruction in program order and if the first result generated from execution of the first instruction is needed for the execution of the second instruction, the controller directs the needed first result to the execution pipeline of the second instruction, wherein only a most recently stored needed first result is directed by the controller to the execution pipeline of the second instruction.