Patent ID: 9015541
Filing Date: 2015-04-21
Classification: G01R

Abstract:
1. A device for performing timing analysis used in a programmable logic array system comprising: a plurality of first basic I/O circuits to receive a plurality of under-test signals from an under-test unit; a plurality of second basic I/O circuits; a channel multiplexer to receive the under-test signals from the first basic I/O circuits to select at least a group of the under-test signals to be outputted to the second basic I/O circuits; a plurality of high-speed I/O circuits having a logic level analyzing speed higher than that of the first and second basic I/O circuit, wherein the high-speed I/O circuits are connected to the second basic I/O circuits; a sampling module to receive the group of under-test signals outputted from the second basic I/O circuits through the high-speed I/O circuits and to sample the group of under-test signals to generate a sample result; and a timing analysis module to perform a timing analysis and measurement according to the sample result.