Patent ID: 8289770
Filing Date: 2012-10-16
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory core including a memory cell array having a plurality of memory cells, the memory core configured to program write test data received from an external host into the respective plurality of memory cells, and to output read test data from the respective plurality of memory cells; and a fail detection circuit, which is separate from the memory core and functions independently from a data program and read function of the memory core, configured to receive the read test data from the memory core, and to compare the read test data with the write test data for each of the plurality of memory cells, and to generate a comparison signal indicative of whether each of the memory cells has failed, the fail detection circuit further configured to accumulate and store fail information of the memory cells corresponding to a plurality of addresses based on the comparison signal, and to output accumulated fail information, wherein the fail detection circuit includes a fail bit indicator configured to store temporary accumulated fail information and output the accumulated fail information, the temporary accumulated fail information including a plurality of bits, each of the bits indicating whether at least one of memory cells included in each column of the memory cell array has a defect.