Patent ID: 6504774
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines, the synchronous memory device comprising:a circuit configured to precharge the global I/O lines when a read command signal interrupts a write operation, and to disable the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit, wherein the circuit includes a plurality of pull-up units for precharging the global I/O lines and a plurality of first logic circuits for controlling the plurality of pull-up units in order to precharge the global I/O lines and wherein the circuit further includes a plurality of pull-down units for discharging the global I/O lines and a plurality of second ligic circuits for controlling the plurality of pull-down units in order to discharge the global I/O lines.