Patent ID: 7876639
Filing Date: 2011-01-25
Classification: G11C

Abstract:
1. An apparatus, comprising: a memory array including a sub-array that includes a first number of columns of regular memory cells; one or more global input/output (I/O) lines shared by the first number of columns for carrying of data to or from the sub-array; one or more multiplexers/demultiplexers, each of the multiplexers/demultiplexers being electrically coupled to one or more, but not all, of the global I/O lines; and a plurality of local I/O lines, wherein each of the local I/O lines is configured to provide a data path between one of the multiplexers/demultiplexers and one or more, but less than the first number, of the columns in the sub-array, wherein two or more of the local I/O lines are multiplexed to one of the global I/O lines via one of the multiplexers/demultiplexers, and wherein one of the global I/O lines is demultiplexed to two or more of the local I/O lines via one of the multiplexers/demultiplexers.