Patent ID: 6151259
Filing Date: 2000-11-21
Classification: G11C

Abstract:
A semiconductor memory device comprising:multiple memory-cell columns each having two or more memory cells;input-output lines the number of which is smaller than that of said memory-cell columns;switches mounted so as to correspond to said input-output lines and to connect, in response to a control voltage, either of said memory-cell columns adjacent to each other to corresponding input-output lines;more than one defective-position setting means connected in series, one terminal of which is held at a ""high"" level potential and the other terminal of which is held at a ""high"" or ""low"" level potential, and wherein a voltage of a point of connection between these means is supplied, as said control voltage, to said two or more switches; and at least one control voltage holding circuit to hold the control voltage supplied to said two or more switches at a ""high"" or ""low"" level.