Patent ID: 9202559
Filing Date: 2015-12-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells that have a threshold voltage included in any of four or more kinds of threshold voltage distributions including an erase state, and that are configured to be capable of storing four or more levels of data; a word line commonly connected to the plurality of memory cells; a plurality of first bit lines and a plurality of second bit lines that are electrically connected respectively to the plurality of memory cells and that are disposed alternately corresponding to arrangement of the plurality of memory cells; and a control circuit capable of executing a first write operation that selects the first bit line and does not select the second bit line and performs write of data to the memory cell connected to the first bit line and does not perform write of data to the memory cell connected to the second bit line, and a second write operation that selects the second bit line and does not select the first bit line and performs write of data to the memory cell connected to the second bit line and does not perform write of data to the memory cell connected to the first bit line, the control circuit being capable of executing: a determining operation that determines whether the memory cell which is to be a write-target includes an erase-target cell whose threshold voltage is to be the erase state, or not; and an inverting operation that inverts selection or unselection of the bit line connected to one of the two memory cells adjacent to the erase-target cell, in the first write operation and in the second write operation.