Patent ID: 8301816
Filing Date: 2012-10-30
Classification: G06F

Abstract:
1. A memory access controller comprising: a command analysis unit configured to receive write access requests for a memory and command data from a plurality of bus masters to analyze access to the memory; a command execution unit configured to output a command control signal and a data control signal to the memory based on write data input from the plurality of bus masters and an analysis result provided by the command analysis unit; a mode setting unit configured to switch operation mode between a first operation mode in which a write access request from a bus master is issued to the command analysis unit when both the command data and the corresponding write data are available and a second operation mode in which a write access request from a bus master is issued to the command analysis unit when the command data is available independently of availability of the write data corresponding to the command data; and a timing arbitration unit provided for each bus master and configured to output the write access request and command data to the command analysis unit and output the write data to the command execution unit at a timing fit for the mode set by the mode setting unit.