Patent ID: 8873330
Filing Date: 2014-10-28
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device, comprising: a memory region including a plurality of memory cores, the memory region including bit lines, word lines, and a plurality of memory cells in each of the memory cores; a row decoder configured to select a word line of the memory cores in accordance with an address signal; a column control circuit configured to control input and output of data into the plurality of memory cells through the bit lines; a control circuit configured to control the row decoder and the column control circuit; and a plurality of address conversion circuits provided for the memory cores respectively, and configured to convert logical address data supplied from outside to physical address data, the control circuit being configured to be capable of executing an interleave operation, the interleave operation alternately executing: while executing a first operation in a first memory core of the plurality of memory cores, a second operation in a second memory core different from the first memory core; and while executing the second operation in the first memory core, the first operation in the second memory core, the address conversion circuits being configured to output the physical address data corresponding to the logical address data without converting the logical address data when the first memory core is to be accessed earlier than the second memory core, whereas output address data obtained by adding a first value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.