Patent ID: 6718422
Filing Date: 2004-04-06
Classification: G06F

Abstract:
A computer system comprising:a microprocessor; a local bus coupled to said microprocessor through a bus bridge, wherein said bus bridge is configured to accommodate data transfers between said microprocessor and said local bus; and a bus arbiter within said bus bridge for controlling and prioritizing bus request signals from a plurality of bus devices coupled to said bus wherein said bus arbiter contains logic to grant control of said bus to a first bus device of said plurality of bus devices based on a predetermined priority of said first bus device relative to other bus devices and said first bus device's prior access to said bus within a fairness cycle, wherein said bus arbiter further contains logic wherein said control is granted in response to a bus device's prior unsuccessful access to said bus within said fairness cycle, and if each bus device is successful within said fairness cycle then in response to said predetermined priority of said first bus device relative to other bus devices.