Patent ID: 6041405
Filing Date: 2000-03-21
Classification: G06F

Abstract:
A microprocessor configured to execute variable length instructions comprising:a cache array configured to receive a fetch address and in response output a corresponding plurality of instruction bytes;an instruction length calculation unit coupled to said cache array and configured to receive said plurality of instruction bytes, wherein said calculation unit is configured to generate a particular instruction length corresponding to a particular instruction within said plurality of instruction bytes; anda pattern detector coupled to said cache array and said calculation unit, wherein said pattern detector is configured to store a plurality of instruction length sequences, wherein each of said plurality of instruction length sequences comprises an initial sequence and a final sequence, wherein said pattern detector is configured to receive a particular initial sequence corresponding to a particular portion of code from said calculation unit and in response output a corresponding final sequence, wherein said corresponding final sequence is usable to predict the lengths of instructions following the particular portion of code.