Patent ID: 7010774
Filing Date: 2006-03-07
Classification: G06F

Abstract:
1. A method of synthesizing a register transfer level (RTL) based design of a system comprising the steps of: determining a plurality of sub-modules of a top level system; determining individual time budgets for each sub-module based on timing requirements of the top-level system; synthesizing a gate-level design of said each sub-module based on the determined time budgets for said each sub-module; testing the gate-level design of said each sub-module for conformance with design requirements of said each sub-module; generating a netlist for said each sub-module when the gate level design of said each sub-module conforms to said design requirements of said each sub-module, then integrating the netlist of said each sub-module to form an integrated top level design netlist; testing the integrated top-level design netlist for conformance with top-level design requirements; and generating a top-level netlist when the integrated top-level design netlist conforms to the top-level design requirements.