Patent ID: 7037774
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. For a structure that includes adjacent gate film stacks that include gate electrodes, a barrier layer that overlies said adjacent gate film stacks, and a first dielectric film that extends over said barrier layer, a process for forming a CMOS device comprising: forming adjacent metal lines that extend over said first dielectric film; forming spacers that extend on opposite sides of said metal lines; forming a second dielectric film that extends over said spacers and over said adjacent metal lines; forming an opening so as to expose a portion of said semiconductor substrate, said opening extending between adjacent metal lines and between said adjacent gate film stacks, portions of said adjacent metal lines aligned with said adjacent gate film stacks so as to align said opening between said adjacent gate film stacks; and filling said opening with conductive material so as to form a self-aligned contact that is electrically coupled to said semiconductor substrate.