Patent ID: 7397696
Filing Date: 2008-07-08
Classification: G11C

Abstract:
1. A circuit for sensing a core current flowing through a bitline path and a memory cell in response to voltages applied to a gate of the cell and an acting drain of the cell, the magnitude of the core current also being a function of the amount of charge stored within the cell, the circuit comprising: a differential amplifier component operatively coupled to the bitline path and configured to provide a substantially constant desired voltage to a desired voltage node on the bitline path where the bitline path is operatively coupled to the acting drain of the cell; and a post processing circuit component operatively coupled to the bitline path and configured to receive an Rsense voltage that is a function of the core current and further configured to output an output voltage (SAIN) that is indicative of the core current, but is an amplification of the Rsense voltage,