Patent ID: 6842378
Filing Date: 2005-01-11
Classification: G11C

Abstract:
1. A flash memory device, comprising: a plurality of sector units including a plurality of memory cells; a sense amplifier control unit for generating a plurality of sense amplifier enable signals; a plurality of sense amplifier units driven by the sense amplifier enable signals and having a plurality of sense amplifiers, wherein the sense amplifiers operate in an automatic verify program mode to automatically perform program and verify operations for corresponding cells, upon pre-program and post-program operations of the memory cells, and operate in an iterative program and verify mode to iteratively perform erase and verify operations for corresponding cells, upon the erase operation; and a plurality of connection switching units for transferring a bias voltage applied from a sense amplifier unit of the plurality of the sense amplifier units to the corresponding memory cells of the sector, depending on a plurality of control signals.