Patent ID: 8648453
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first wiring substrate, the first wiring substrate comprising a first substrate main surface having a first chip mounting region with a plurality of first bonding leads formed therein, a plurality of first substrate main surface-side lands disposed around the first chip mounting region over the first substrate main surface and coupled electrically to the first bonding leads, respectively, a first substrate back surface positioned on the side opposite to the first substrate main surface, and a plurality of first substrate back surface-side lands disposed on the first substrate back surface and coupled electrically to the first bonding leads, respectively; a first semiconductor chip mounted over the first chip mounting region of the first wiring substrate, the first semiconductor chip comprising a first chip main surface, a plurality of first electrode pads formed on the first chip main surface, and a first chip back surface positioned on the side opposite to the first chip main surface; a plurality of first conductive members for coupling the first electrode pads of the first semiconductor chip and the first bonding leads of the first wiring substrate electrically with each other; a first sealing body for sealing the first semiconductor chip, the first conductive members and the first substrate main surface of the first wiring substrate such that the first substrate main surface-side lands are exposed; a plurality of first external terminals formed over the first substrate back surface-side lands, respectively, of the first wiring substrate; a second wiring substrate, the second wiring substrate comprising a second substrate main surface having a second chip mounting region with a plurality of second bonding leads formed therein, a second substrate back surface positioned on the side opposite to the second substrate main surface, and a plurality of second substrate back surface-side lands disposed on the second substrate back surface and coupled electrically to the second bonding leads, respectively; a second semiconductor chip mounted over the second chip mounting region of the second wiring substrate, the second semiconductor chip comprising a second chip main surface, a plurality of second electrode pads formed over the second chip main surface, and a second chip back surface positioned on the side opposite to the second chip main surface; a plurality of second conductive members for coupling the second electrode pads of the second semiconductor chip and the second bonding leads of the second wiring substrate electrically with each other; a second sealing body for sealing the second semiconductor chip, the second conductive members and the second substrate main surface; and a plurality of second external terminals formed over the second substrate back surface-side lands, respectively, of the second wiring substrate to couple the second substrate back surface-side lands and the first substrate main surface-side lands electrically with each other, wherein the first substrate main surface of the first wiring substrate has a planar quadrangular shape having a pair of first sides and a pair of second sides intersecting the first sides, wherein the first sealing body has a pair of third sides parallel to the second sides and the third sides are overlapped by a part of the second sides in a plan view, wherein the first sealing body is disposed from a central part of one of the second sides of the first wiring substrate toward a central part of the other one of the second sides of the first wiring substrate, and wherein the first substrate main surface-side lands are disposed between the first sealing body and the first sides of the first wiring substrate.