Patent ID: 7838356
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A method comprising: forming a gate dielectric layer on PMOS regions for PMOS devices and NMOS regions for NMOS devices; forming an original gate electrode layer on the gate dielectric layer in both the PMOS regions and the NMOS regions, wherein the original gate electrode layer is doped with material of a first conductivity type; applying a gate masking layer on the gate electrode layer; etching to pattern the original gate electrode layer to simultaneously form original gate electrodes for PMOS devices and NMOS devices; forming source/drain regions for the PMOS devices and the NMOS devices; removing the original gate electrodes for at least one of the PMOS devices and the NMOS devices to form trenches using an wet etch process with a wet etch solution, wherein the wet etch solution is more reactive with layers doped with the first conductivity type than layers doped with a second conductivity type, and wherein the wet etch solution is generally nonreactive with the gate dielectric layer, and wherein at least a portion of the gate dielectric layer is preserved; and forming replacement gates in the trenches.