Patent ID: 9001604
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A memory device, comprising: an array of memory cells; a plurality of sense amplifiers coupled with the array; a plurality of output data lines between outputs of corresponding sense amplifiers in the plurality of sense amplifiers and inputs of data output multiplexers; a plurality of precharge circuits configured to apply a precharge voltage on the output data lines, wherein the precharge circuits precharge the output data lines before the sense amplifiers drive output data signals to the output data lines; and a controller that provides control signals to the sense amplifiers in the plurality of sense amplifiers and to the precharge circuits in the plurality of precharge circuits, wherein the controller enables the sense amplifiers to sense data at data inputs of the sense amplifiers during a sensing interval starting at a first time and ending at a second time subsequent to the first time, to output sensed data to the output data lines at the second time, and enables the precharge circuits to precharge the output data lines during a precharge interval starting at or after the first time and ending prior to the second time.