Patent ID: 6018813
Filing Date: 2000-01-25
Classification: G01R

Abstract:
A method for identifying and testing primitive faults occurring in a combinational circuit, said combinational circuit comprising a plurality of gates, said circuit having a plurality of paths through said plurality of gates, a subset of said paths being functional senzitizable paths, a further subset of said subset of functional sensitizable paths being controlling-value functional senzitizable paths, said method comprising the steps of:a) identifying a subset of gates in the combinational circuit wherein said subset of gates do not have paths involved in any primitive fault merge, said identifying being performed by using information about a number of the functional sensitizable paths that go through each of said plurality of gates in the circuit;b) examining each of said subset of functional sensitizable paths (FS) and determining primitive faults which include said each of said functional sensitizable paths;c) updating said further subset of controlling value-functional sensitizable (cv-FS) paths through each gate by eliminating from testing a second subset of paths wherein said second subset of paths do not have any co-sensitizing gate, wherein said updating is done by using information about functional paths which do not require testing; andd) repeating step c through multiple iterations.