Patent ID: 8940591
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming a gate stack on an active region in a n-type field effect transistor (nFET) portion of a silicon-on-insulator (SOI) substrate, wherein the silicon-on-insulator substrate comprises a p-type field effect transistor (pFET) portion; forming a gate spacer over the gate stack; forming, while maintaining exposed a first region reserved for a source region and a second region reserved for a drain region in each of the nFET portion and the pFET portion of the SOI substrate, a first trench in the first region of the nFET portion reserved for the source region, a second trench in the second region of the nFET portion reserved for the drain region, a third trench in the first region of the pFET portion, and a fourth trench in the second region of the pFET portion wherein the first trench in the first region of the nFET portion and the second trench in the second region of the nFET portion each has a dimension d″, and wherein the third trench in the first region of the pFET portion and the fourth trench in the second region of the pFET portion each has a dimension d′″, wherein each of the dimensions d″ and d′″ are different from each other; and epitaxially growing, while maintaining exposed the first and second regions of the nFET portion reserved for the source and drain regions, respectively, silicon germanium within the first trench and the second trench.