Patent ID: 8990648
Filing Date: 2015-03-24
Classification: G01R,G06F,G11C

Abstract:
1. A synchronous active high reset scan flip flop comprising: a data input; a serial input; a test enable input; a reset input; a clock input; a device output; an AND gate configured to receive the serial input and the test enable input, and output a first output signal; a multiplexer configured to receive the data input, the first output signal, and the reset input, and output a second output signal comprising one of the data input or the first output signal in response to the reset input being de-asserted or asserted, respectively, the reset input is used to reset the flip flop in a function mode, and permit scan test in a test mode; and a storage element configured to receive the second output signal, and output a device output upon receipt of an active edge of a clock signal.