Patent ID: 6195788
Filing Date: 2001-02-27
Classification: G06F

Abstract:
A method of mapping an electronic design to a target hardware device using a plurality of heterogeneous logic elements, the target hardware device including first type logic elements and second type logic elements interconnected by way of programmable connectors, comprising:(a) forming a first logical region using the first type logic element;(b) forming a second logical region using the second type logic element, wherein the first logical region and the second logical region perform logically equivalent sub-functions of the electronic design;(c) comparing the first and the second logical regions;(d) choosing either the first logical region or the second logical region based upon the comparing (c);(e) adding the chosen logical region from operation (d) to a final mapping list; and(f) repeating operations (a)-(e) until the electronic design is fully mapped.