Patent ID: 7795643
Filing Date: 2010-09-14
Classification: G11C,H01L

Abstract:
1. A cell array of a semiconductor memory device, comprising: a semiconductor substratum including an active region comprising a first region, a second region, and a transition region interposed between the first region and the second region, wherein the first region has a substantially planar top surface, the second region has a substantially planar top surface, the top surface of the second region is disposed at a different level than the top surface of the first region, and the transition region has a top surface that is inclined relative to each of the top surfaces of the first and second regions; a plurality of word lines crossing over the top surface of the first region; and a selection line crossing over the active region, at least a portion of the selection line being located over the inclined top surface of the transition region, and wherein the selection line has opposite sidewalls, one of the sidewalls extending upright on the top surface of one of said regions of the active region, the other of the sidewalls extending upright on the top surface of another of said regions of the active region, and the sidewalls having different vertical dimensions such that one of the sidewalls is taller than the other.