Patent ID: 6378090
Filing Date: 2002-04-23
Classification: G01R

Abstract:
An electronic circuit comprising:a first test access port including a predetermined set of input and output lines adapted for controlling electronic test of the electronic circuit; a first testable embedded core circuit including a second test access port including said predetermined set of input and output lines adapted for controlling electronic test of said first testable embedded core, at least one second testable embedded core circuit each having a third test access port including said predetermined set of input and output lines adapted for controlling electronic test of said second testable embedded core circuit, a first test access port controller connected to said second test access port and having a first internal test state dependent upon inputs received from input lines of said predetermined set of input and output lines of said second test access port, and a first programmable switch coupled to said second test access port, said third test access port of each of said at least one second testable embedded core circuit and said first test access port controller, said first programmable switch selectively connecting said second test access port to said third test access port of one of said at least one second testable embedded core circuit for controlling test of said second embedded core circuit dependent upon said first internal test state of said first test access port controller; at least one third testable embedded core circuit each having a fourth test access port including said predetermined set of input and output lines adapted for controlling electronic test of said third testable embedded core circuit; a second test access port controller connected to said first test access port and having a second internal test state dependent upon inputs received from input lines of said predetermined set of input and output lines of said first test access port; and a second programmable switch coupled to said first test access port, said second test access port and said fourth test access port of each of said at least one third testable embedded core circuit and said first test access port controller, said second programmable switch selectively connecting said first test access port to said second test access port or to a selected one of said fourth test access port of one of said at least one third testable embedded core circuit for controlling test of said embedded core circuit dependent upon said test state of said second internal test access port controller.