Patent ID: 6734712
Filing Date: 2004-05-11
Classification: G06G

Abstract:
A logarithmic amplifier receiving an input voltage, comprising:a high gain section having plural gain paths, each gain path including an amplifier and a signal limiter in series, and each gain path being connected to a common input such that the paths are in parallel, each of the gain paths having an output and a gain; the outputs of the plural gain paths being connected to a signal summation circuit and summed to form an output signal; a low gain section connected between the common input and the signal summation circuit; delay elements in plural gain paths of the high gain section and the low gain section, the delays of the delay elements being selected to compensate for variation between group and phase delay of the plural gain paths, the delay elements of at least two of the plural gain paths of the high gain section sharing a common amplifier such that signals in the at least two of the plural gain paths are amplified by the common amplifier; and the gain of each of the low gain section and the plural gain paths of the high gain section being selected so that the output signal varies logarithmically with the input voltage. 2.The logarithmic amplifier of claim 1 in which each delay element comprises a buffer amplifier.