Patent ID: 7109578
Filing Date: 2006-09-19
Classification: H01L,H05K

Abstract:
1. A semiconductor device in which a high frequency use semiconductor integrated circuit chip, which comprises a plurality of ball grid array terminals disposed in a lattice arrangement in one surface, and a plurality of peripheral circuit components are mounted on a multi-layer board which comprises a plurality of front-layer wire patterns, which are formed in one surface and connected with said ball grid array terminals and terminals of said peripheral circuit components, and a plurality layers of inner-layer wire patterns, wherein: said plurality of ball grid array terminals of said high frequency use semiconductor integrated circuit chip which are disposed in a lattice arrangement include at least one first non-grounding ball grid array terminal disposed outer-most in the lattice arrangement, at least one first grounding ball grid array terminal disposed on the inner side to said first non-grounding ball grid array terminal, and at least one second non-grounding ball grid array terminal disposed on the inner side to said first grounding ball grid array terminal, said first non-grounding ball grid array terminal is a high-frequency signal terminal and/or a power supply terminal while said second non-grounding ball grid array terminal is a logic control terminal, said plurality layers of inner-layer wire patterns of said multilayer board include at least one inner-layer grounding wire pattern and at least one inner-layer non-grounding wire pattern which is formed at least one layer below said inner-layer grounding wire pattern from said front layer, the first one of said front-layer wire patterns which is connected with said first non-grounding ball grid array terminal is connected with the terminal of the first one of said peripheral circuit components which is disposed right close to said semiconductor integrated circuit chip, the second one of said front-layer wire patterns which is connected with said first grounding ball grid array terminal is connected with said inner-layer grounding wire pattern via a first through hole, the third one of said front-layer wire patterns which is connected with said second non-grounding ball grid array terminal is connected with one end of said inner-layer non-grounding wire pattern via a second through hole, and the fourth one of said front-layer wire patterns which is connected with the terminal of the second one of said peripheral circuit components not located right close to said semiconductor integrated circuit chip is connected with the other end of said inner-layer non-grounding wire pattern via a third through hole.