Patent ID: 7927993
Filing Date: 2011-04-19
Classification: H01L

Abstract:
1. A method for fabricating a CMOS integrated circuit (IC), comprising: providing a semiconductor comprising wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface; forming a gate dielectric layer on at least said topside semiconductor surface; depositing a metal comprising gate electrode material including at least a first metal on said dielectric layer on said topside semiconductor surface and on at least a portion of said bevel semiconductor surface and at least a portion of said backside semiconductor surface; selectively removing said metal comprising gate electrode material on said bevel semiconductor surface and said backside semiconductor surface to form substantially first metal free bevel and backside surfaces while protecting said metal comprising gate electrode material on said topside semiconductor surface, said selective removing comprising: a first wet etch that etches said metal comprising gate electrode material highly selectively as compared to said bevel semiconductor surface and said backside semiconductor surface, said first wet etch comprising a strong oxidizing acid, a weak acid and a fluoride, and completing fabrication of said IC including forming at least one metal interconnect layer after said selectively removing step.