Patent ID: 8405089
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: an active region formed with a gate trench having mutually opposite first and second side surfaces and a bottom surface, the active region having first and second diffusion layers positioned at both sides of the gate trench and a third diffusion layer formed on the bottom surface of the gate trench; a first storage electrode connecting electrically to the first diffusion layer; a second storage electrode connecting electrically to the second diffusion layer; a capacitance dielectric film covering the first and second storage electrodes; a plate electrode covering the capacitance dielectric film; a bit line electrically connected to the third diffusion layer; a first gate electrode that covers the first side surface of the gate trench via a first gate dielectric film, the first gate electrode producing a channel between the first diffusion layer and the third diffusion layer; and a second gate electrode that covers the second side surface of the gate trench via a second gate dielectric film, the second gate electrode producing a channel between the second diffusion layer and the third diffusion layer, wherein the plate electrode extends downwardly beyond a bottom surface of the bit line wherein the bit line is disposed above the first and second diffusion layers, the semiconductor memory device further comprising: wherein the plate electrode covers the first and second side surfaces of the bit line cap dielectric film.