Patent ID: 6496559
Filing Date: 2002-12-17
Classification: G01N

Abstract:
A method for performing inspection and/or analysis of raised electrical contacts and respective underlying vias of an electrical or electronic device or component, comprising the sequential steps of:(a) providing an electrical or electronic device or component having opposing first and second major surfaces, said first major surface including an array of closely spaced-apart raised electrical contacts with respective underlying vias, wherein said electrical or electronic device or component is a semiconductor integrated circuit (â€œICâ€ ) device package or a package substrate having a two-dimensional, row-and-column, grid-shaped array of raised, ball-grid array (â€œBGAâ€ ) or flip-chip contacts on said first major surface thereof and adjacent rows and columns of said two-dimensional, grid-shaped arrays of raised contacts are spaced apart from about 200 to about 600 &mgr;m; (b) selecting an area-of-interest (â€œAOIâ€ ) of said first major surface, said AOI including at least one said raised electrical contact with its respective underlying via; (c) cutting through said electrical or electronic device or component from said first major surface to said second major surface along two substantially parallel lines to separate therefrom an elongated strip including said AOI, wherein said elongated strip has a narrow width of from about 5 to about 15 mils; (d) mounting said elongated strip on a surface of a substrate; and (e) inspecting and/or analyzing said AOI including said at least one raised electrical contact with respective underlying via for presence of any misalignment, voids, and delaminations.