Patent ID: 7454662
Filing Date: 2008-11-18
Classification: G11C

Abstract:
1. An integrated memory having a function test for the integrated memory, comprising: a memory cell array having memory cells for storing test data; a plurality of circuit components for reading the test data from the memory cells; a plurality of circuit components for ascertaining addresses for the memory cells from which the test data have been read; a compression module connected to the circuit components for reading the test data from the memory cells, the compression module receiving the test data from the memory cells, the compression module performing a nominal/actual data comparison with the received test data from the memory cells and producing an associated error data item at the output for a test data item from the test data from one of the memory cells if the one test data item from the test data from the one of the memory cells differs from a nominal data item which is associated with the one of the memory cells; a register circuit for storing a bit combination, which can be used to divide an address space in the memory into address regions having a respective plurality of associated memory cells; a compression unit receiving error data which have been produced by the output of the compression module, the compression unit being actuated by the register circuit, the compression unit generating a compressed address from the address of a received error data item from the error data, the compressed address flagging an address for one of the address regions from which the test data item associated with the received error data item has been read; a memory unit for storing a plurality of bits, each of the bits being associated with one of the address regions, and the bit associated with one of the address regions being set if the error data item produced by the compression module belongs to a test data item from the test data which is associated with the one of the address regions; a decoder circuit connected to the compression unit and to the memory unit, the decoder circuit receiving the compressed address and accessing that bit in the memory unit, which is associated with the respective address region based on the compressed address; a long-term memory unit, the long-term memory unit being connected to the memory unit, the long-term memory unit for long-term storage of the bits in the memory unit in corresponding bits in the long-term memory unit; and a combinational logic circuit to combine each of the bits in the memory unit with a corresponding bit in the long-term memory unit.