Patent ID: 7058866
Filing Date: 2006-06-06
Classification: G01R

Abstract:
1. A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation, the system comprising: said system clock; and self-test circuitry including: an AC self-test controller; a first and second test register for capturing and launching test data in response to a sequence of data pulses; a logic circuit to be tested; a clock splitter, wherein input to said clock splitter includes said system clock and said AC self-test controller and the clock splitter generates then sequence of data pulses, the sequence including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse; and circuitry to implement a method comprising: applying the long data capture pules to said first test register in response to said system clock; applying the at speed data launch pulse to said first test register in response to said system clock, wherein data from said first test register is input to a logic path in said logic circuit in response to said applying an at speed data launch pulse; applying the at speed data capture pulse to said second test register in response to said system clock, wherein output data from said logic path is input to said second test register in response to said applying an at speed data capture pulse; applying the long data launch pulse to said second test register in response to said system clock; comparing the data value in said second test register to an expected value; and detecting an error in response to said comparing, wherein the cause of said error includes one or more of said logic path not completing until after said at speed capture pulse has ended, said logic being executed twice before said at speed capture pulse has ended, said long data launch pulse starting before said at speed data capture pule ends and said at speed data capture pulse ends after said long data launch pulse begins, register for in response to the sequence; and a logic circuit to be tested, wherein input to said logic circuit includes data form said firsts test register and output from said logic circuit is stored in said second test register.