Patent ID: 6108254
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A dynamic random access memory comprising:an array of rows and columns of memory cells;parallel word lines associated with the rows of said memory cells;parallel bit lines transverse to said word lines and associated with the columns of said memory cells;a sense amplifier coupled to said array of memory cells to read out data directly from said memory cells;row decoder means, coupled to said word lines, for receiving a row address signal, and for selecting a corresponding one of said word lines;column decoder means, coupled to said bit lines and said sense amplifier, for receiving a column address signal to select a corresponding one of said bit lines;first data lines coupled to said bit lines by transfer gates which are selectively controlled by said column decoder means whereby readout data output from said sense amplifier is transferred to said first data lines;a data input/output buffer coupled to said first data lines and including a CMOS current mirror differential amplifier activated in a ready mode to amplify the readout data on said first data lines;second data lines connected to said first data lines through said data input/output buffer and passing data amplified by said differential amplifier thereof;address transition detecting means for detecting transition of the row and column address signals, and for generating an address transition detection signal;equalizing means, coupled to said second data lines and said address transition detecting means, for resetting said second data lines, to which the amplified data from said differential amplifier is supplied, at a preselected potential level, said equalizing means including switching means for connecting said second data lines to said preselected potential level in response to the address transition detection signal, said preselected potential level being an intermediate potential between a power source voltage and a ground voltage of said memory; anddata latch means connected to said differential amplifier through said second data lines for latching the amplified data.