Patent ID: 6768685
Filing Date: 2004-07-27
Classification: G11C

Abstract:
In an integrated circuit having a fully-decoded array of memory cells, each memory cell associated with one of a plurality of X-lines and one of a plurality of Y-lines, a method of operating the memory array comprising the steps of:selecting at least a first Y-line; in a first mode of operation, selecting an X-line associated with the first selected Y-line to impress a read bias across a corresponding memory cell coupled between the selected X-line and the first selected Y-line; in a second mode of operation: selecting a first plurality of X-lines associated with the first selected Y-line to impress a read bias across each of a corresponding first plurality of selected memory cells respectively coupled between the first plurality of selected X-lines and the first selected Y-line; enabling a first read circuit having an input coupled to the first selected Y-line; and generating a first read signal on an output of the first read circuit having a first value if an aggregate read current of the first plurality of selected memory cells exceeds a second mode threshold level.