Patent ID: 6618306
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A digital circuit configuration, comprising:an information memory having cells forming a memory matrix (50) with: M rows; N columns; P additional rows; and Q additional columns, where: PQP has K&lE;(Zâˆ’2) bits for addressing P elements; and Q has L&lE;(Sâˆ’2) bits for addressing Q elements; an addressing device having: an address decoding device having inputs; an input circuit having: address connection contacts for receiving externally applied row and column address bits, a number of said address connection contacts being equal to a sum Z+S, where Z is a number of bits required for addressing M elements and S is a number of bits required for addressing N elements; a control bit connection contact for receiving an externally applied first control bit; and a changeover device receiving: the first control bit; and second and third control bits respectively applied to two dedicated contacts of said address connection contacts; a device for transferring at least some of said applied address bits to said inputs of said address decoding device; and said changeover device: only when the first control bit has a given first binary value, setting a first operating state in which said address decoding device uses bits of all of said address connection contacts for addressing M selected rows and N selected columns in said memory matrix; and otherwise, depending on a given combination of values of the second and third control bits, selectively setting one of a second operating state, a third operating state, and a fourth operating state in which said address decoding device, respectively, uses bits from contacts of ones of said address connection contacts not dedicated to the second and third control bits for addressing: M selected rows and a remaining set of Q columns; a remaining set of P rows and N selected columns; and a remaining set of P rows and a remaining set of Q columns.