Patent ID: 7414893
Filing Date: 2008-08-19
Classification: G11C

Abstract:
1. An electrically erasable and programmable memory comprising: memory cells wherein each memory cell comprises a floating gate transistor arranged in series with an access transistor, and the memory cells are arranged according to word lines; a plurality of common selection lines each connected to gate terminals of the access transistors of the memory cells of a respective one of the word lines; bit lines extending transversely to the word lines and linked to the memory cells, the bit lines being gathered into individually selectable columns; a plurality of common control gate lines each connected to control gates of the floating gate transistors of the memory cells of a respective one of the word lines; a plurality of common source lines each individually connected to the memory cells of a respective one of the columns; a plurality of column control units each controlling a respective one of the common source lines; a line decoder unit structured to apply simultaneously, during a programming phase of the memory cells of a selected word line of the word lines: a double well embedded in a semiconductor substrate, into which the memory cells are formed; and means for polarizing the double well at a positive supply voltage during the programming phase of the memory cells and simultaneously with the first reference voltage being applied to the control gate line of the non-selected word line, the second reference voltage being applied to the control gate line of the selected word line, and the positive programming voltage being applied to the selection line of the selected word line, the first reference voltage being a positive voltage inferior to the positive programming voltage, and the second reference voltage being equal to zero.