Patent ID: 6119150
Filing Date: 2000-09-12
Classification: G06F

Abstract:
A message passing parallel processor system with distributed memory, comprising:a plurality of processor elements, each having an instruction processor, a main memory which performs memory access in response to a memory access request informed thereto, a cache memory used to improve efficiency of access to the main memory, wherein data is written into said cache memory and when a copy back is requested data in said cache memory is written into said main memory, and wherein said instruction processor performs cache purge processing in response to a cache coherence control request informed thereto; anda inter-processor network which interconnects said processor elements;wherein, each of said processor elements further includes:an address register which stores main memory addresses, copies of memory data thereof having being purged from said cache memory due to cache coherence control requests previously issued,a coherence control request issue circuit which issues a cache coherent control request to said instruction processor when a local processor element receives through said inter-processor network a message including data to be stored in said main memory through said inter-processor network and when a destination address of said data is not included in said main memory addresses stored in said address register, anda memory access request issue circuit which issues a write request to the main memory when the local processor element receive the message including the data to be stored in said main memory.