Patent ID: 9134374
Filing Date: 2015-09-15
Classification: G01R

Abstract:
1. A circuit for measuring a signal delay between an edge of a first alternating signal supplied to a first node of a circuit-under-test (CUT) and an edge of a second alternating signal supplied to a second node of the CUT, the first and second alternating signals being synchronous to a first clock, the circuit comprising: means for capturing, controlled by a first capture clock, first samples of signals associated with the first and second alternating signals, the first capture clock's sampling instants being synchronous to a second clock and having a timing skew included in a signal delay measurement, the second clock being coherent to the first clock; means for capturing, controlled by a second capture clock, second samples of the first samples, the second capture clock's sampling instants being synchronous to the second clock and having a timing skew not included in the signal delay measurement; and means for conveying the second samples via a shift register to a plurality of modulo counters.