Patent ID: 9128143
Filing Date: 2015-09-08
Classification: G01R,G06F,G11C

Abstract:
1. A semiconductor device failure analysis system comprising: a memory configured to be capable of retaining an initial display information and an image generation master, the initial display information indicating a type of an initially displaying image data, and the image generation master indicating a type of a generating image data with respect to a semiconductor device including a three-dimensional memory cell array; a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, and to compare the image generation master and the initial display information to determine a second image, the second image being a type of an image data common to the image generation master and the initial display information and corresponding to part of the plurality of fail bit information; and a display configured to be capable of initially displaying the second image.