Patent ID: 6418057
Filing Date: 2002-07-09
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first memory array having a plurality of memory cells disposed in rows and columns; a plurality of bit lines provided corresponding to respective memory cell columns of said first memory array, and each for transferring a data of a memory cell on a corresponding column; a plurality of latch circuits provided corresponding to respective bit lines, each for latching a received data when made active; a plurality of transfer gates each provided between the latch circuit and a corresponding bit line and connecting said latch circuit and said corresponding bit line in response to a transfer instructing signal; a latch drive signal line for transmitting a latch drive signal to said plurality of latch circuits, said latch drive signal line supplying an operating power supply voltage to power supply nodes of the latch circuits to activate each of the latch circuits; and a plurality of reverse current preventing elements each provided corresponding to the power supply node of the latch circuit and said latch drive signal line and for preventing a current from flowing from a corresponding power supply node to said latch drive signal line while allowing the current to flow from the latch drive signal line to the corresponding power supply node.