Patent ID: 6495425
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method for fabricating a memory cell structure comprising:providing a semiconductor substrate; forming within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a polysilicon gate electrode formed upon the gate dielectric layer, a sacrificial capping layer formed upon the polysilicon gate electrode, a pair of source/drain regions formed within the semiconductor substrate and separated by the gate electrode and a pair of spacer layers adjoining a pair of opposite edges of the gate electrode, said layer separates the polysilicon gate electrode from the conductor stud layer by a horizontal distance of from about 0.03 to about 0.09 microns; forming over the semiconductor substrate and passivating the field effect transistor (FET) device a passivating layer; forming through the passivating layer, while employing the pair of spacer layers and the sacrificial capping layer as a mask, at least one self aligned contact via accessing at least one of the pair of source/drain regions; forming into the self aligned contact via a conductor stud layer; stripping from over the substrate the passivating layer and the sacrificial capping layer to leave exposed a top surface of the polysilicon gate electrode separated from the conductor stud layer by one of the pair of spacer layers; and forming upon the exposed top surface of the gate electrode a silicide layer while employing a salicide method.