Patent ID: 7673095
Filing Date: 2010-03-02
Classification: G06F,G11C

Abstract:
1. A memory circuit, comprising: a first level memory core operable to store data; a first level load circuit coupled to the memory core and operable, without using an address pointer, to, a first level unload circuit operable, without using an address pointer, to, wherein the first level memory core comprises: a second level memory core operable to store the data; a second level load circuit coupled to the second level memory core and operable to, receive the data from the first level load circuit in the order and at the second rate, and load the data into the second level memory core in the order and at a fifth rate that is less than the second rate; and a second level unload circuit operable to, unload the data from the second level memory core in the order and at a sixth rate that is less than the third rate, and provide the unloaded data to the first level unload circuit in the order and at the third rate.