Patent ID: 6693336
Filing Date: 2004-02-17
Classification: H01L

Abstract:
In the fabrication of an integrated circuit having stress-sensitive circuitry sites, a method for reducing stress-induced effects on the performance of the integrated circuit, compromising the steps of:a. forming a diffusion area in a base substrate; b. forming a first insulating layer over said base substrate and said diffusion area; c. forming an electrically conductive layer over said first insulating layer and establishing a stress sensitive electrical connection at said diffusion area; d. removing select portions of said conductive layer to establish a circuitry pattern; e. forming a first protection layer over said circuitry pattern and said first insulating layer; f. forming a second protection layer over said first protection layer; g. forming an opening in said second protection layer positioned vertically at a stress sensitive electrical connection within the margins thereof; h. removing in processing through said opening in said second protection layer portions discrete portions of said first protection layer to establish a buffer chamber vertically bounded by said second protection layer and said connection and outwardly bounded by a peripheral wall within the margins of said connection and outwardly of the margins of said opening; i. encapsulating said second layer with a viscous molding compound, said opening and the viscosity of said compound being interrelated to limit inward penetration of said compound into said chamber, thereby providing a stress relieving void limiting induced thermal and mechanical stresses at said connection.