Patent ID: 6728256
Filing Date: 2004-04-27
Classification: H04L

Abstract:
A control device for a shared buffer comprising:a plurality of shared sub-buffers; a write selector circuit for writing therein data blocks from inputs; a read selector circuit for reading said data blocks therein afterwards and directing them to at least one output, said two selector circuits including arbitration means for writing and reading data blocks in accordance with periodic cycles, each cycle including time slots during each of which a data block received at an input can be written into one of said shared sub-buffers and during which a data block previously written can be read and sent to a particular output; simultaneously writing a data block from an input in one shared sub-buffer and reading from a different shared sub-buffer a data block to be sent to an output, the whole of said time slot being allocated to said simultaneous reading of said data block and said writing of said data block, wherein selecting a sub-buffer for reading takes priority over selecting the same sub-buffer for writing; and wherein said arbitration means include means for arbitrating a single write access vis a vis a single read access during each time slot.