Patent ID: 7895412
Filing Date: 2011-02-22
Classification: G06F

Abstract:
1. A programmable processing engine in an intermediate network device to process transient data, said programmable processing engine comprising: a plurality of processing elements that each include a central processing unit (CPU), a memory manager, and at least one context memory configured to temporarily hold transient data, the plurality of processing elements arrayed as a plurality of parallel pipelines, each pipeline having a plurality of processing elements arrayed as stages in the pipeline with the plurality of processing elements in the pipeline coupled sequentially to each other, the processing elements of each pipeline to execute operations on the transient data, and each pipeline of said plurality of parallel pipelines to process a different portion of said transient data; and a plurality of external memory resources located external to said plurality of processing elements arrayed as the plurality of parallel pipelines, each of said external memory resources coupled to each processing element of a particular stage of processing elements and designated for exclusive access by the processing elements of the particular stage, and to store non-transient data used in processing said transient data in the particular stage.