Patent ID: 6266759
Filing Date: 2001-07-24
Classification: G06F

Abstract:
A method of overlapping the execution of multiple instructions in a virtual-address vector computer having architectural registers holding multiple vector elements, and a control unit for reading and writing said vector elements in said registers in accordance with a sequence of instructions, the method comprising:executing a plurality of the instructions overlapped in time with each other, at least one of the instructions being a vector memory reference instruction (VMRI);repeating the following operations for each of the overlapped instructions;If the instruction is a VMRI, assigning a column of indicators to the VMRI, the indicators in the column corresponding to respective ones of the registers and setting all of the indicators in the column to an ""unused"" state;identifying one of the registers as a source register for the overlapped instructions;if the indicator corresponding to the source register is in the ""unused"" state, setting said indicator corresponding to the source register to a ""live"" state;identifying one of the registers as a target register for the overlapped instruction;if the indicator corresponding to the target register is in the ""unused"" state, setting said indicator corresponding to the target register to a ""dead"" state;if the indicator corresponding to the target register is in the ""live"" state, stalling the overlapped instructions.