Patent ID: 7932605
Filing Date: 2011-04-26
Classification: H01L

Abstract:
1. A semiconductor device comprising: a chip mounting base having a first interconnection on a first major surface thereof, a second interconnection exposed to a second major surface thereof, the second interconnection being electrically connected to the first interconnection and extending through a base body of the chip mounting base; a semiconductor element mounted on the first major surface of the chip mounting base and electrically connected to the first interconnection; a sealing member provided on the first major surface of the chip mounting base, covering the semiconductor element and the first interconnection, and having a hole; a third interconnection provided on a surface of the sealing member; and a fourth interconnection provided in the sealing member, electrically connected to the first interconnection and the third interconnection, and extending through the hole of the sealing member, wherein the third interconnection and the fourth interconnection are integral with each other and form one layer.