Patent ID: 7919865
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a third internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit and to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said third internal circuit; a passivation layer over said dielectric layer; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, and wherein said second internal circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.