Patent ID: 6646467
Filing Date: 2003-11-11
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of input/output pins, each of which is configurable for use as an output pin or an input pin, and includes an associated tri-state driver with a data input terminal and an output enable terminal; a plurality of regions of programmable logic, each of which includes a register having a clock signal input terminal, a data signal input terminal, and a data signal output terminal and configured to respond to a clock signal applied to the clock signal input terminal by applying to the data signal output terminal a data output signal indicative of the signal concurrently applied to the data signal input terminal; a clock signal input pin connected to the clock signal input terminals of the registers; and programmable logic connector circuitry configured to selectively couple a data signal output terminal of a selected register to the data input terminals of the associated tri-state drivers of a subset of the input/output pins with fast conductors so that delay between application of a clock signal to the clock signal input pin and application of a data output signal from each input/output pin in the subset of the input/output pins indicative of the signal applied to the data signal input terminal of the selected register is within the PCI TCO time interval.