Patent ID: 9177646
Filing Date: 2015-11-03
Classification: G06F,G11C

Abstract:
1. A computational memory device, comprising: an array of content addressable memory (CAM) cells arranged in rows and columns; a pair of search lines associated with each column of the array; and a match line associated with each row of the array; wherein the array is configured to implement, for a given cycle, either a read operation of data contained in a single selected column, or one of a plurality of different bitwise logical operations on data contained in multiple selected columns, all of the pairs of search lines in the columns of the array configured to a certain state to implement the read operation or the one of the plurality of different bitwise logical operations, a result of the read operation or the one of the plurality of different bitwise logical operations outputted onto all of the match lines in the array, wherein the configuring comprises a data bit and a bit enable assignable to each pair of search lines associated with the columns in the array of the CAM, the data bit determining whether each search line in the pair of search lines is activated or deactivated, and the bit enable determining whether the column in the array of the CAM is masked from performing the read operation or the one of the plurality of different bitwise operations.