Patent ID: 6835622
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A method for fabricating a semiconductor fabrication comprising:providing a semiconductor substrate; forming laterally adjacent upon the semiconductor substrate a minimum of a first gate dielectric layer and a second gate dielectric layer each formed of a single thickness; and forming a minimum of a first doped polysilicon containing gate electrode upon the first gate dielectric layer and a second doped polysilicon containing gate electrode upon the second gate dielectric layer, wherein the first gate electrode has a first dopant distribution profile different in comparison with a second dopant distribution profile of the second gate electrode, to provide an apparent difference in thickness of the first gate dielectric layer with respect to the first gate electrode and the second gate dielectric layer with respect to the second gate electrode when each of the first gate electrode and the second gate electrode is employed within a field effect device within the semiconductor fabrication, further wherein the first dopant distribution profile and the second dopant distribution profile are effected incident to selective ion implantation of a blanket undoped polysilicon containing gate electrode material layer prior to patterning thereof to form the first doped polysilicon containing gate electrode and the second doped polysilicon containing gate electrode.