Patent ID: 6459310
Filing Date: 2002-10-01
Classification: H03K,H03L

Abstract:
A clock divider circuit comprising:(a) an input port for receiving an input clock; (b) a linear shift register having a plurality of stages including a first-stage and a last stage, each of said stages comprising a flip flop device having a data input port, a data output port, and a clock input port, said clock input ports being coupled to said input port, and said stages being connected in series with the data output port of said previous stage being coupled to the data input port of the subsequent stage, at least one of said flip flops being negative-edge triggered and at least one of said flip flops being positive-edge triggered; (c) a feedback loop coupling the data output port of said last stage to the data input port of said first stage, and said feedback loop including a logic gate having an output connected to the data input port of said first stage and a first input connected to the data output port of said last stage and a second input connected to the data output port of said second last stage in said linear shift register; (d) said stages in said linear shift register being operable to shift data at said data input ports to said data output ports and in said feedback loop in response to said input clock; (e) an output port coupled to said last stage and said second last stage for receiving data and outputting an output clock signal.