Patent ID: 9083361
Filing Date: 2015-07-14
Classification: H03J,H03L

Abstract:
1. An ADPLL comprising: a digital controlled oscillator; a first counter configured to count a number of clocks fed back from the digital controlled oscillator; a second counter configured to count a multiplication number representing a number of the clocks included in a reference clock; a TDC configured to detect a delayed amount of a phase of the clocks fed back from the digital controlled oscillator with respect to a phase of the reference clock; an adder configured to add the delayed amount detected by the TDC to a difference between the multiplication number counted by the second counter and the number of clocks counted by the first counter, and output the added result; a slew rate setting part configured to receive the clocks fed back from the digital controlled oscillator to set a slew rate of the fed back clocks; an ADC connected to an output side of the slew rate setting part and configured to receive the clocks to which the slew rate is set by the slew rate setting part; a switching part configured to selectively switch between an output of the adder and an output of the ADC as an input into the digital controlled oscillator; and a controller configured to control the slew rate in the slew rate setting part while shifting a phase of the clocks input from the TDC to the digital controlled oscillator to set a slew rate that realizes a lock point in the ADC in a status where the ADLL is locked by utilizing the TDC when the input of the digital controlled oscillator is switched from the output of the adder to the output of the ADC.