Patent ID: 8735251
Filing Date: 2014-05-27
Classification: H01L

Abstract:
1. A method, comprising: (a) forming an oxidation barrier layer on a top surface of a silicon substrate and forming an opening in said barrier layer, a region of said top surface of said substrate exposed in a bottom of said opening; (b) forming a trench in said silicon substrate where said substrate is not protected by said barrier layer, said trench open to a top surface of said substrate; (c) forming a silicon dioxide layer on sidewalls of said trench, said silicon dioxide layer not filling said trench; (d) removing said oxidation barrier layer; (e) forming a hardmask layer on said top surface of said substrate and all exposed surfaces of said silicon dioxide layer; (f) filling remaining space in said trench with polysilicon after which a top surface of said polysilicon is coplanar with a top surface of said hardmask layer; after (f), (g) forming a source, drain and channel region of a field effect transistor in said substrate, a gate dielectric on said channel region and a gate electrode on said gate dielectric; (h) forming a passivation layer over said hardmask layer and said field effect transistor; (i) forming metal contacts to respective said source, said drain and said gate electrode of said field effect transistor through said passivation layer, top surfaces of said metal contacts coplanar with a top surface of said passivation layer; (j) forming an opening in said passivation layer over said trench and completely removing said polysilicon from said trench, said dielectric layer and said hardmask layer remaining on said sidewalls of said trench; (k) re-filling said trench with an electrically conductive core, said electrically conductive core extending above a top surface of said substrate, said dielectric layer and said hardmask layer remaining on said sidewalls of said trench, a top surface of said core coplanar with said top surface of said passivation layer; and after (k), (l) forming a stack of two or more damascene wiring levels from a first wiring level to a last wiring level over said passivation layer, a wire of a wiring level said first wiring level contacting said top surface of said conductive core.