Patent ID: 6370076
Filing Date: 2002-04-09
Classification: G11C

Abstract:
In a memory device including at least a first block containing a first number of memory cells and a second block containing a second number of memory cells, the memory cells organized in rows and columns such that the rows span the first and second blocks, and such that each column is in either the first or the second block, the first and second blocks being coupled to a word decoder that selects, based on a first address, one of the rows, the first block also being coupled to a first selection circuit in a column decoder that selects, based on a second address, at least one of the columns in the first block, and the second block being coupled to a second selection circuit in the column decoder that selects, based on a third address, at least one of the columns in the second block, a method comprising:accepting a fourth address at an input address circuit; determining whether the fourth address represents a group of cells in the first block or in the second block; passing a first portion of the fourth address to the word decoder as the first address; passing a second portion of the fourth address to the first selection circuit in the column decoder as the second address; passing a third portion of the fourth address to the second selection circuit in the column decoder as the third address; sensing first data stored in memory cells located at the selected row and in the selected columns of the first block and concurrently sensing second data stored in memory cells located at the selected row and in the selected columns of the second block; and selecting through a third selection circuit coupled to the first and second selection circuits either the first or the second data as the group of data specified by the fourth address.