Patent ID: 6125075
Filing Date: 2000-09-26
Classification: G11C,H03K

Abstract:
A semiconductor memory in a chip, comprising:a plurality of dynamic memory cells, each cell including a transfer MOS transistor;a plurality of word lines, each word line coupled to gate electrodes of the transfer MOS transistors of a subset of said plurality of dynamic memory cells;an X-decoder driver coupled to said plurality of word lines; anda voltage generator circuit providing a first voltage to said X-decoder driver and including a first circuit and a second circuit;wherein the first circuit receives an operating voltage and generates the first voltage when said X-decoder driver selects one of said plurality of word lines;wherein the second circuit receives the operating voltage and generates the first voltage when said X-decoder driver selects none of said plurality of word lines;wherein the amplitude of the first voltage is larger than that of the operating voltage, andwherein said X-decoder driver receives address signals and the first voltage and provides a selecting signal whose amplitude is larger than the amplitude of the address signals to a selected one of said plurality of word lines.