Patent ID: 6064713
Filing Date: 2000-05-16
Classification: G09G,G11C

Abstract:
Shift register containing a plurality of cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first terminal connected to a first clock signal and a second terminal connected to a second clock signal, the said stage containing a first semiconductor device switching the output of said stage between high and low values of the first clock signal, the first semiconductor device being controlled by the potential of a second node, itself connected:to the output of the preceding stage across a second semiconductor device controlled by the output of the preceding stage;to a first negative voltage across a third semiconductor device controlled by the output of the next stage;to the second terminal connected to the second clock signal across a first capacitance,wherein a second capacitance is mounted between the second node and the output of the next stage.