Patent ID: 9061885
Filing Date: 2015-06-23
Classification: B81B,H01L

Abstract:
1. A semiconductor device comprising: a device wafer portion having a first set of inactive regions and a second inactive region; a semiconductor die positioned on a side of said device wafer portion, said semiconductor die including a microelectronic device and multiple conductive lines in physical and electrical contact with said microelectronic device, wherein each inactive region of said first set of inactive regions is located between every two adjacent conductive lines of said semiconductor die; bond pads, one each of said bond pads being in electrical communication with one each of said multiple conductive lines, wherein said bond pads are adjacent to said second inactive region; a first set of barriers positioned in said first set of inactive regions by having one barrier of said first set of barriers in each of said inactive regions of said first set of inactive regions, wherein said barriers do not contact said multiple conductive lines; a second barrier positioned in said second active region; and a cap wafer section coupled to said device wafer portion and covering said microelectronic device, said cap wafer section not covering said bond pads such that said bond pads are exposed.