Patent ID: 6842047
Filing Date: 2005-01-11
Classification: B82Y,G06N,H03K

Abstract:
1. A method for deriving an output data wavetrain within an electronic or logic gate wherein zero and one are represented, respectively, by sinusoidal voltages of null and unity amplitude, comprising: (a) providing a pair of or input terminals to receive input data wavetrains, an or output terminal to transmit said output data wavetrain, and a ground voltage supply terminal, (b) providing a first inverting voltage adder and a node terminal to which said adder transmits the negative sum of said or input terminal voltages, (c) providing a second inverting voltage adder whose output is conveyed to said or output terminal and a plurality of parallel filtering paths for isolating different frequency components and connecting said node terminal and said second adder, wherein each of said parallel filter paths comprises a cascade of two identical RLC series filters each having one end of its resistor grounded and the other end serving as filter output, connected by an intervening clipper for truncating voltages of absolute value greater than some predetermined level, (d) applying input data wavetrains of the same phase and frequency as said sinusoidal voltage representing one to said or input terminals and causing, as a result of above provisions, said first adder's output voltage to flow through one of said parallel filtering paths unmodified if at least one of said input wavetrains has null amplitude or otherwise to be reduced to one half amplitude, and, after passing through said second inverting adder, to constitute said output data wavetrain, whereby said gate will permit combination into the same logic devices as standard two level or gates, and whereby said devices' will be able to parallel process input data wavetrains from different frequency information channels.