Patent ID: 6977858
Filing Date: 2005-12-20
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of bit-line pairs; a plurality of word lines; a plurality of memory cells provided at intersection points formed by the plurality of bit-line pairs and the plurality of word lines; a plurality of sense amplifiers, each of which is provided for each given number of bit-line pairs from among the plurality of bit-line pairs; a plurality of write amplifiers, each of which is provided for said each given number of bit-line pairs; a control circuit that selectively connects one of the given number of bit-line pairs to the sense amplifier, and that selectively connects one of the given number of bit-line pairs to the write amplifier; an error-correction circuit; a data storing circuit for storing data to write; and an address storing circuit for storing an address corresponding to the data to write; wherein: said error-correction circuit corrects an error of data read out corresponding to a first writing address, and then generates first data to write; said data storing circuit stores the first data to write; and after a second writing address is inputted into the address storing circuit, said write amplifier writes the first data to write to the memory cell.