Patent ID: 6952813
Filing Date: 2005-10-04
Classification: G06F

Abstract:
1. A method for reducing clock skew, comprising: obtaining a placed and routed design; generating a routing tree for a clock signal of the placed and routed design, the routing tree having at least one route and a plurality of clock pin nodes, the clock signal being divided into a plurality of clock signals responsive to the clock pin nodes; determining delays of the plurality of clock signals to the plurality of clock pin nodes; balancing the routing tree to a target clock skew; and selectively adding programmable interconnect circuits to the routing tree to reduce clock skews of the plurality of clock signals, the clock skews being reduced at the plurality of clock pin nodes for at least a portion of the plurality of clock pin nodes; wherein the determining delays of the plurality of clock signals comprises: initializing delay parameters for at least some wires which are part of the routing tree; calculating delays to the plurality of clock pin nodes for the at least one route; traversing the routing tree for at least part of the at least one route from the plurality of clock pin nodes toward a clock source node; and determining delay differences for at least some wires of the at least one route.