Patent ID: 7605066
Filing Date: 2009-10-20
Classification: B82B,B82Y,G03F,G11C,H01L,Y10S

Abstract:
1. A method for realizing an electric connection in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components, the method comprising the steps of: a) providing, above a semiconductor substrate, a seed layer having at least a notched wall substantially perpendicular to said substrate, said wall defining n vertical recesses having a height equal to a thickness of said seed layer, said recesses being placed at a distance b b) realizing, by Multi-Spacer Patterning Technology (S c) realizing, above said nanometric circuit architecture, an insulating layer; d) opening, in said insulating layer, n windows, each window being open substantially in correspondence with a respective one of the recesses, with exposure of at least part of the elbow-like portion of a respective one of the conductive nanowires present in said recess; and e) realizing, above said insulating layer, n conductive dies addressed towards said standard electronic components, the conductive dies respectively overlapping in correspondence with the respective windows to respective exposed parts of the respective elbow-like portions of the respective conductive nanowires with obtainment of n contacts realizing said electric connection.