Patent ID: 8796130
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A method comprising: patterning a polysilicon gate over two immediately adjacent, opposite polarity transistor devices; removing a portion of said polysilicon gate from a location where said opposite polarity transistor devices abut one another to form a recess in said polysilicon gate, said recess separating said polysilicon gate into a first polysilicon gate and a second polysilicon gate, said recess being positioned between said first polysilicon gate and said second polysilicon gate, and said recess having a reduced thickness relative to said first polysilicon gate and said second polysilicon gate; after forming said recess, doping said first polysilicon gate using a first polarity dopant; and after forming said recess, doping said second polysilicon gate using a second polarity dopant having an opposite polarity of said first polarity dopant.