Patent ID: 7183630
Filing Date: 2007-02-27
Classification: H01L,H05K,Y02P

Abstract:
1. A semiconductor package comprising: a die pad defining a bottom surface; a plurality of leads extending at least partially about the die pad in spaced relation thereto, each of the leads defining: a semiconductor chip attached to the die pad and electrically connected to at least one of the leads; a package body defining a generally planar bottom surface and partially encapsulating the die pad, the leads and the semiconductor chip such that at least a portion of the bottom surface of each of the leads is exposed in and substantially flush with the bottom surface of the package body; and means formed on the exposed portion of the bottom surface of each of the leads for increasing a stand-off height of the semiconductor package from an underlying substrate and providing an increased solderable area to create a solder fillet when solder is used to attach the semiconductor package to the substrate, the stand-off means being formed of a conductive material having a melting point higher than that of solder; and a solder plate disposed on the stand-off means.