Patent ID: 6262622
Filing Date: 2001-07-17
Classification: G05F

Abstract:
A high voltage input circuit comprising:a PMOS having a gate coupled to a bias voltage, a drain, and a source;a resistor having a first end connected to the drain of said PMOS and a second end connected to ground;a first inverter having an input connected to the drain of said PMOS, and an output;a first NMOS connected in series with said PMOS, said first NMOS having a gate, a drain, a source and a P-well, the drain and gate of said first NMOS being connected together to a high voltage input terminal for receiving a high voltage; anda P-well voltage control device having an input connected to the output of said first inverter and an output connected to said P-well of said first NMOS, said P-well voltage control device being an inverter.