Patent ID: 7705395
Filing Date: 2010-04-27
Classification: G11C,H01L

Abstract:
1. A flash memory cell, comprising: a first tunnel oxide film formed at a given region of a semiconductor substrate; a first floating gate formed on the first tunnel oxide film; a second tunnel oxide film having first and second portions wherein the first portion of the second tunnel oxide film is formed over the semiconductor substrate and the second portion of the second tunnel oxide film is formed on a sidewall of the first floating gate; a second floating gate formed in contact with the second tunnel oxide film and isolated from the first floating gate through the second tunnel oxide film, wherein the second floating gate is thinner than the first floating gate and comprises silicon nitride; a dielectric film having an Oxide/Nitride/Oxide (ONO) structure formed on the first floating gate, a top of the second portion of the second tunnel oxide film and the second floating gate; a control gate formed on the dielectric film; a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film; and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film.