Patent ID: 8278981
Filing Date: 2012-10-02
Classification: G11C

Abstract:
1. A variable delay circuit comprising: X number of fixed delay parts having a fixed delay, each delaying an inputted signal, where X is a positive integer; X number of first selection parts, each receiving an input signal and one of the X number of fixed delay parts' output signal, and each selecting and outputting one of received signals in response to one of X number of first selection signals, wherein the X number of fixed delay parts and the X number of first selection parts are connected in series in an alternative manner; a variable delay part having a delay receiving an output signal of the last one of the X number of first selection parts, delaying the output signal of the last one of the X number of first selection parts by a delay value determined by one or more of second selection signals; a second selection part, receiving the input signal and an output signal of the variable delay part, selecting and outputting one of received signals in response to a third selection signal.