Patent ID: 6734749
Filing Date: 2004-05-11
Classification: H03C

Abstract:
In a PLL circuit comprising an adjustable frequency divider, a phase comparator, and a VCO disposed to provide an output signal of specified frequency, apparatus for selectively modulating said VCO output signal comprising:a counter coupled to directly receive a digital modulation signal comprising a train of digital symbols, said counter being driven by said digital modulation signal to produce an output corresponding thereto, and to generate a divider adjustment signal each time said counter output reaches a specified value; a first path for coupling a signal representing said digital modulation signal as an input to said VCO; a second path for injecting a compensation signal into said PLL circuit; a control device for adjusting said frequency divider to divide said VCO output signal by a selected divisor, said control device disposed to adjust said divisor by an increment of one in response to each said divider adjustment signal, and to additionally adjust said divisor in response to a divider control signal; and a third path for coupling each of said divider adjustment signals directly to said control device from said counter.