Patent ID: 6046092
Filing Date: 2000-04-04
Classification: H01L

Abstract:
A method for manufacturing a capacitor applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, comprising steps of:a) forming a first sacrificial layer over said first conducting layer;b) partially removing said first sacrificial layer, said first conducting layer, and said dielectric layer to form a contact window;c) forming a second conducting layer over said first sacrificial layer and in said contact window;d) forming a second sacrificial layer over said second conducting layer;e) partially removing said second sacrificial layer, said second conducting layer, and said first sacrificial layer to expose a portion of said first sacrificial layer;f) forming a third conducting layer alongside said second sacrificial layer, said second conducting layer, and said portion of said first sacrificial layer;g) removing said first and second sacrificial layers to expose said first conducting layer; andh) partially removing said first conducting layer while retaining a portion of said first conducting layer under said second and third conducting layers to construct a capacitor plate.