Patent ID: 6908826
Filing Date: 2005-06-21
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a first metal wiring on a semiconductor substrate and a dielectric film pattern on the first metal wiring, the first metal wiring serving as a first electrode of a metal-insulator-metal (MIM) capacitor; forming a stacked structure comprising a first interlayer insulation film and a second interlayer insulation film; forming a photosensitive film pattern defining a first via-contact region and a plurality of second via-contact regions on the stacked structure, wherein the photosensitive film pattern exposes the first via-contact region at a first side of the first metal wiring, defines the plurality of second via-contact regions in a parallel array structure at a second side of the first metal wiring, and defines a width of each of the plurality of second via-contact regions smaller than a width of the first via-contact region; etching the first and second interlayer insulation films and the dielectric film pattern on the first metal wiring using the photosensitive film pattern as an etching mask to form a first via-contact hole exposing the first metal wiring and to form a plurality of second via-contact holes exposing the dielectric film pattern; removing the photosensitive film pattern; filling the first second via-contact hole and the plurality of second via-contact holes to form a first contact-plug and a plurality of second via-contact plugs, the plurality of second via-contact plugs serving as a second electrode of the MIM capacitor; and forming a second metal wiring contacting the first via-contact plug and the plurality of second via-contact plugs.