Patent ID: 9148166
Filing Date: 2015-09-29
Classification: H03M

Abstract:
1. A successive approximation register analog to digital converter (SAR ADC), configured to receive an input voltage and a set of reference voltages, comprising: a charge sharing DAC comprising an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors; a zero crossing detector coupled to the charge sharing DAC, the zero crossing detector configured to generate a digital output; a coarse ADC (analog to digital converter) configured to receive the input voltage and configured to generate a coarse output, wherein a predefined offset is added to a residue of the coarse ADC; and a successive approximation register (SAR) state machine, coupled to the coarse ADC and the zero crossing detector and, configured to generate a plurality of control signals, wherein the plurality of control signals is configured to operate the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.