Patent ID: 6121079
Filing Date: 2000-09-19
Classification: G11C,H01L,Y10S

Abstract:
A method for manufacturing a semiconductor memory device comprising the steps of:(a) providing a substrate having a first active region of a first conductivity type and a second active region of said first conductivity type, the first and second active regions being isolated from each other;(b) forming a depletion region of a second conductivity type on a part of said first active region;(c) forming a first pass transistor and a storage transistor on the first active region, forming a second pass transistor on the second active region and forming on said depletion region a supply transistor, providing a substrate voltage for the storage transistor;(d) forming an insulating layer said first and said pass transistor, said second pass transistor, said storage transistor and said supply transistor;(e) etching a part of said insulating layer, thereby forming a first contact hole exposing a portion of said first pass transistor, a second contact hole exposing a portion of said second pass transistor and a third contact hole exposing another portion of the second pass transistor together with a portion of said storage transistor; and(f) after step (e) forming a first metal wire, a second metal wire and a third metal wire filling said first contact hole, said second contact hole and said third contact hole respectively.