Patent ID: 7590764
Filing Date: 2009-09-15
Classification: G06F

Abstract:
1. A method for providing data transfers between a processor and a component, the method comprising: routing requests originating from a processor to a component through a target controller and handling requests originating from the processor to the component by; buffering a first address with a first address buffer in response to a deferred read request originating from the processor to the component, and associating a first bi-directional data buffer with the first address wherein the first bi-directional data buffer is configured to hold a first data value associated with the deferred read request; setting status information to indicate that the first address buffer is associated with the deferred read request; buffering a second address with a second address buffer in response to a write request originating from the processor to the component, and associating a second bi-directional data buffer with the second address wherein the second bi-directional data buffer is configured to hold a second data value associated with the write request, the first and second address buffers being in communication with the processor and the component; setting status information to indicate that the second address buffer is associated with the write request; buffering the first data value requested by the processor with the first bi-directional data buffer when the data is obtained with the deferred read request from the component and buffering the second data value associated with the write request written by the processor with the second bi-directional data buffer, the first and second bi-directional data buffers being in communication with the processor and the component, wherein the first and second address buffers are separate from the first and second data buffers; monitoring the first and second address buffers and the first and second data buffers to determine when the data buffers have obtained the first data value associated with the deferred read request and the second data value associated with the write request; controlling the first address buffer and the first bi-directional data buffer as a matched pair such that the first address held in the first address buffer corresponds to the first data value associated with the deferred read request; controlling the second address buffer and the second bi-directional data buffer as a matched pair such that the second address held in the second address buffer corresponds to the second data value associated with the write request; reading the status information from the first address buffer to determine the status of the first data value associated with the deferred read request; reading status information from the second address buffer to determine the status of the second data value associated with the write request; and controlling the order of bi-directional data flow through the first and second bi-directional data buffers such that data flows between the processor and the component while the processor is processing other instructions and, wherein controlling the order of the bi-directional data flow through the first and second bi-directional data buffers is variable and based on the status information of the first and second data values such that the bi-directional data flow does not occur in a first-in-first out manner.