Patent ID: 6138227
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A device for jump-like addressing of specific lines of a serially operating digital memory, comprising:two control devices which are jointly assigned to the specific lines, wherein each of said two control devices has a plurality of outputs and, at said outputs, chronologically successively generates a specific binary information item assigned to a respective one of said two control devices and decisive for addressing one of said specific lines,a plurality of linking elements, each of said linking elements being assigned to one of said specific lines and having an output assigned to respective ones of said specific lines, said linking elements each having an input assigned to one of the two control devices as well as an input assigned to an other one of said two control devices,each of said linking elements addressing the one of said specific lines assigned to that respective linking element alone via its output precisely when there is present at its input assigned to the one control device the specific binary information item assigned to that control device and, simultaneously, there is present at its input assigned to the other control device the specific binary information item assigned to the other control device,the linking elements being subdivided into groups which do not share the same elements and in each case have a plurality of linking elements, the groups together yielding all the linking elements inputs, assigned to the one of the two control devices, of the linking elements being connected to the outputs of the corresponding control device in such a way that each of said outputs is connected to only one of said inputs of each of said groups andinputs, assigned to the other control device, of the linking elements being connected in groups to the outputs of the other control device in such a way that the inputs of each of said groups are jointly connected to one of the outputs assigned to this group alone.