Patent ID: 6504186
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A semiconductor device comprising:a standard cell formed on a substrate and having at least a MOS transistor and an input line for the MOS transistor; and a plurality of independent standard cells disposed near said standard cell, each of the independent standard cells having: at least one metal wiring line, at least one contact hole; and a diffused region protecting a gate of the MOS transistor by dissipating surplus electrons into the substrate, the electrons flowing into said metal wiring line during the processing, wherein the input line of said standard cell and said at least one metal wiring line of one of said plurality of independent standard cells are connected when an area or a circumferential length of the metal wiring line of said one of the plurality of independent standard cells connected to the input line of the standard cell is damaged by a plasma.