Patent ID: 8330702
Filing Date: 2012-12-11
Classification: G09G,G11C,H01L,H03K

Abstract:
1. A pulse output circuit comprising: a first thin film transistor to an eleventh thin film transistor, a first signal line to a seventh signal line, a first power supply line and a second power supply line, wherein a first terminal of the first thin film transistor is electrically connected to the first power supply line, wherein a second terminal of the first thin film transistor is electrically connected to a gate of the third thin film transistor, a gate of the fourth thin film transistor, a gate of the fifth thin film transistor, a second terminal of the ninth thin film transistor, and a first terminal of the tenth thin film transistor, wherein a gate of the first thin film transistor is electrically connected to the second signal line, wherein a first terminal of the second thin film transistor is electrically connected to a first terminal of the third thin film transistor and a second terminal of the eighth thin film transistor, wherein a second terminal of the second thin film transistor is electrically connected to a gate of the sixth thin film transistor and a gate of the seventh thin film transistor, wherein a gate of the second thin film transistor is electrically connected to the first power supply line, wherein a second terminal of the third thin film transistor is electrically connected to the second power supply line, wherein a first terminal of the fourth thin film transistor is electrically connected to the seventh signal line and a second terminal of the sixth thin film transistor, wherein a second terminal of the fourth thin film transistor is electrically connected to the second power supply line, wherein a first terminal of the fifth thin film transistor is electrically connected to the sixth signal line, a second terminal of the seventh thin film transistor, and a first terminal of the eleventh thin film transistor, wherein a second terminal of the fifth thin film transistor is electrically connected to the second power supply line, wherein a first terminal of the sixth thin film transistor is electrically connected to the first signal line, wherein a first terminal of the seventh thin film transistor is electrically connected to the first signal line, wherein a first terminal of the eighth thin film transistor is electrically connected to the first power supply line, wherein a gate of the eighth thin film transistor is electrically connected to the fourth signal line, wherein a first terminal of the ninth thin film transistor is electrically connected to the first power supply line, wherein a gate of the ninth thin film transistor is electrically connected to the fifth signal line, wherein a second terminal of the tenth thin film transistor is electrically connected to the second power supply line, wherein a gate of the tenth thin film transistor is electrically connected to the fourth signal line, wherein a second terminal of the eleventh thin film transistor is electrically connected to the second power supply line, and wherein a gate of the eleventh thin film transistor is electrically connected to the third signal line.