Patent ID: 7365025
Filing Date: 2008-04-29
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, comprising the steps of: forming an electrically insulating layer on a substrate; forming at least one via hole extending at least partially through the electrically insulating layer; filling the at least one via hole with a first electrically insulating material having a first porosity; covering the filled at least one via hole with a second electrically insulating material layer having a second porosity lower than the first porosity; selectively etching back the second electrically insulating material layer to expose a first portion of the first electrically insulating material in the at least one via hole; selectively etching back the electrically insulating layer, using the etched second electrically insulating material layer as an etching mask, to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole; and then removing the first electrically insulating material from the at least one via hole and the second electrically insulating material layer.