Patent ID: 6667665
Filing Date: 2003-12-23
Classification: G06F,G06Q,G07F,H03K,H04L

Abstract:
A circuit configuration, comprising:an integrated circuit; a random number generator configuration provided on said integrated circuit; said random number generator configuration including a first clock generator circuit for generating a first signal having one of a first frequency and a first frequency range with a first mean value, and said random number generator configuration including a second clock generator circuit for generating a second signal having one of a second frequency and a second frequency range with a second mean value, said first and second clock generator circuits generating said first and second signals such that one of said second frequency and said second mean value is smaller than one of said first frequency and said first mean value; said first clock generator circuit having a first voltage supply, said second clock generator circuit having a second voltage supply; said random number generator configuration including a generator configured to sample said first signal with said second signal and configured to generate at least one random number in dependence of a sampling result; and said first clock generator circuit and said second clock generator circuit being spaced apart from one another by a maximum spacing distance on said integrated circuit, and said first voltage supply and said second voltage supply being isolated from one another.