Patent ID: 6690046
Filing Date: 2004-02-10
Classification: H01L,Y10S

Abstract:
A semiconductor assembly, comprising:a semiconductor substrate having a first region and a second region defined therein; a first oxide region on the substrate and covering the first region of the substrate, the first oxide region having nitrogen provided therein, substantially all of the nitrogen being at least 10 Ã¥ above the semiconductor substrate; a first conductive layer over the first oxide region and defining a first transistor gate; first source/drain regions proximate the first transistor gate and gatedly connected to one another by the first transistor gate; a second oxide region covering the second region of the substrate; a second conductive layer over the second oxide region and defining a second transistor gate; and second source/drain regions proximate the second transistor gate and gatedly connected to one another by the second transistor gate.