Patent ID: 6546498
Filing Date: 2003-04-08
Classification: H04L

Abstract:
A system for detecting and eliminating a faulty port in a fiber channel-arbitrated loop, comprising:a plurality of nodes, each node comprising a first and a second port, the first ports of said nodes being connected to a first hub to form a first loop, and the second ports of said nodes being connected to a second hub to form a second loop; means for determining whether a port that has detected a loop fault is a bypass/enable instruction issuing port having a bypass/enable instruction right; means for issuing an instruction to bypass all ports other than said port that has detected a loop fault from a normal port if said port that has detected the loop fault is said instruction issuing port; means for bypassing nodes that have received the bypass instruction by terminating transmission of light through ports of said nodes connected with said faulty loop, such that said loop consists of only a hub and said port that has detected the loop fault when the bypassing is completed; means for registering said port that has detected a loop fault as a faulty port if the fault continues once said faulty loop consists of only the hub and the port that has detected the loop fault; means for bypassing the port that detected the loop fault as a faulty port such that the faulty loop consists of only said hub, and for assigning the bypass/enable instruction right to another port through a normal loop other than the faulty loop and transferring the registration information of the faulty port if the port that detected the loop fault is a faulty port; and means for registering all ports as faulty ports if said hub is faulty when the port to which the bypass/enable instruction right has been assigned detects a loop fault, to thereby close said faulty loop.