Patent ID: 8001504
Filing Date: 2011-08-16
Classification: G06F

Abstract:
1. A processor-implemented method of determining a clock skew between first and second nodes of a plurality of nodes of an integrated circuit, comprising: generating and storing a set of respective first delay values for paths from a clock source through a clock tree of the integrated circuit to the plurality of nodes; generating and storing a set of respective second delay values for the paths from the clock source through the clock tree to the plurality of nodes, wherein each of the first delay values corresponds to one of the second delay values for a given one of the plurality of nodes, and each of the first delay values is greater than the corresponding one of the second delay values; generating and storing a set of common delay values, each of the common delay values being a delay for a shared portion of the paths from the clock source through the clock tree to two of the plurality of nodes; determining the clock skew based on the first delay value for the first node, the second delay value for the second node, and the common delay value for the shared portion of the paths from the clock source through the clock tree to the first and second nodes; and outputting data indicative of the clock skew, wherein the determining and the outputting are performed by a processor.