Patent ID: 6429522
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A multi-layer semiconductor circuit comprising:a first layer comprising a plurality of encapsulated conductive lines on a substrate and a plurality of voids, one void between each adjacent pair of encapsulated conductive lines, each encapsulated line having a top, a bottom, and opposite sides encapsulated by a conductive barrier layer on top of an adhesion-promotion layer; and a structurally supportive, non-metal cap layer comprising a first solid material at least partially covering the top of the encapsulated conductive lines in the first layer and separating the voids and encapsulated conductive lines in the first layer from any subsequent layers, each void defined by the sidewalls of the adjacent encapsulated conductive lines, an upper surface of the substrate, and a lower surface of the cap layer; wherein each void comprises air as a dielectric and is completely free of the first solid material therein.