Patent ID: 6111803
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A circuit using a reduced cell voltage comprising:a cell which stores a charge at a first voltage, the charge representing either a logical ""1"" or a logical ""0"";a first digit line initially biased to a second voltage, the first digit line being coupled to the cell, the first voltage being substantially equal to the second voltage when a logical ""1"" is stored in the cell;a second digit line biased to a third voltage;a logic detector which transfers the charge on the cell to the first digit line, the charge on the cell decreasing the second voltage when a logical ""0"" is stored in the cell and the charge on the cell not substantially changing the second voltage when a logical ""1"" is stored in the cell; anda sense amplifier in electrical communication with the first digit line and the second digit line, the sense amplifier comparing the second voltage to the third voltage to determine the charge stored in the cell.