Patent ID: 6567286
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A contents addressable memory that compares stored data and input data, and outputs address information in which matching data is stored, comprising:memory cells arranged in a matrix at positions where word lines extending along a row cross bit lines extending along a column; search buses extending along the column and match lines extending along the row; a comparison circuit provided in each memory cell and which compares data in said search bus and data stored in memory cell and outputs comparison result to the match line; and transfer units each provided between a pair of said memory cells arranged along the column and each comprising a first transfer gate, a transfer cell for temporarily storing data from said memory cell, and a second transfer gate; wherein data from one of said pair of memory cells is stored in said transfer cell via said first or second transfer gate, then the data thus stored in the transfer cell is stored in other of said pair of memory cells via said second or first transfer gate.