Patent ID: 7298357
Filing Date: 2007-11-20
Classification: G09G

Abstract:
1. A circuit for an active matrix display device, comprising: a shift register comprising n stages, each stage comprising an inverter, a first clocked inverter and a second clocked inverter wherein, in each stage, an output of said first clocked inverter and an output of said second clocked inverter are input to said inverter and an output of said inverter is input to said second clocked inverter; and (n−1) three-input NAND circuits, wherein an output of said inverter of an m-th stage of said shift register is input to said first clocked inverter of an (m+1)-th stage of the shift register where m is a natural number and satisfies 1≦m≦n−1, wherein the output of the inverter of the m-th stage of the shift register and the output of the (m+1)-th stage of the shift register are input to an m-th three-input NAND circuit of said (n−1) three-input NAND circuits, wherein mask signals are input to said (n−1) three-input NAND circuits for mask periods, respectively, and wherein said mask periods correspond to a timing when a level of the output of said inverter of the respective stages changes from a high level to a low level and from a low level to a high level.