Patent ID: 6449199
Filing Date: 2002-09-10
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of first memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns; a plurality of second memory blocks provided alternately with said plurality of first memory blocks along a column direction, each having a plurality of normal memory cells arranged in a matrix of rows and columns; a plurality of third memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns; a plurality of fourth memory blocks provided alternately with said plurality of third memory blocks in the column direction each having a plurality of normal memory cells; a first spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of first memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in the third memory blocks; a second spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said second memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective normal memory cell in said plurality of fourth memory blocks; a third spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said third memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in said plurality of first memory blocks; a fourth spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of fourth memory block, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in said plurality of second memory blocks; and control circuitry for selectively driving one of the first to fourth memory blocks into a selected state in a normal operation mode, and selecting one of first and second memory blocks and one of the third and fourth memory blocks to drive selected memory blocks into a selected state in a particular operation mode.