Patent ID: 7948407
Filing Date: 2011-05-24
Classification: H04L

Abstract:
1. A serial interface circuit comprising: a data receiver circuit that receives differential-signal serial data transferred through differential data signal lines, and outputs received serial data; a clock signal receiver circuit that receives differential clock signals transferred through differential clock signal lines, and outputs a received clock signal; a logic circuit block that includes a serial/parallel conversion circuit and receives the received serial data from the data receiver circuit and the received clock signal from the clock signal receiver circuit, the serial/parallel conversion circuit sampling the received serial data based on a sampling clock signal generated using the received clock signal, and converting the received serial data into parallel data; a clock signal generation circuit that generates an internal clock signal, and output the internal clock signal; a clock signal detection circuit that compares the received clock signal with the internal clock signal to detect whether or not the differential clock signals are transferred through the differential clock signal lines; and an output mask circuit that masks the parallel data from the logic circuit block to prevent the parallel data from being transmitted to a circuit in a subsequent stage of the output mask circuit when the clock signal detection circuit has detected the differential clock signals are not transferred through the differential clock signal lines.