Patent ID: 7989310
Filing Date: 2011-08-02
Classification: H01L

Abstract:
1. A method of forming at least one dielectrically insulating isolation trench for dielectric isolation of regions of different potential of device structures formed above an SOI wafer including an active semiconductor layer, by forming at least one void in said at least one isolation trench, thereafter forming a hermetically tight seal of the at least one void with respect to the semiconductor wafer surface, the method comprising: performing a first fill in the form of a controlled deposition adapted to trench geometry with an aspect ratio of 15 to 1 or higher to thereby form oxide layers at trench walls, said oxide layers having an increasing thickness towards upper trench edges and forming a first bottleneck; subsequently anisotropically RIE etching the oxide layers in a first step until the oxide layers are removed from the wafer surface and subsequently continuing the RIE etching process in a second step for removing the oxide layers in an upper trench portion to a defined depth for defining a later sealing portion of the at least one void by displacing downwardly the first bottleneck to form a further bottleneck.