Patent ID: 6333235
Filing Date: 2001-12-25
Classification: H01L

Abstract:
A Method for fabricating bipolar transistor, said method comprising the steps of:forming a first oxide layer on a substrate having a first conductivity;developing a first photoresist pattern on said first oxide layer;forming a first doped region in said substrate without coverage from said first photoresist pattern by a first implanting step, said first doped region compose a buried layer having a second conductivity;striping said first photoresist pattern;annealing said first doped region to enlarge depth of said first doped region;removing said first oxide layer to expose said first doped region and a portion of said substrate;growing a first epitaxial layer on said first doped region and said exposed portion of said substrate, said first epitaxial layer being made of epitaxial silicon having said second conductivity;growing a second epitaxial layer on said first epitaxial layer, said second epitaxial layer being made of epitaxial SiGe having said first conductivity, said second epitaxial layer being formed insitu with said first epitaxial layer;forming a plurality of first trenches to expose a portion of said substrate;filling a first insulating material in said plurality of first trenches to form a plurality of first trench isolation;forming a plurality of second trenches in said first epitaxial layer, said first epitaxial layer and said second epitaxial layer being etched to be divided into a first area and a second area, said first area and said second area being divided by one of said plurality of second trenches locating between every two of said plurality of first trench isolation;filling a second insulating material in said plurality of second trenches to form a plurality of second trench isolation;forming a gate oxide layer on said second epitaxial layer and said plurality of first trench isolation;developing a base photoresist pattern on a first portion of said gate oxide layer to expose a second portion of said gate oxide layer;forming a first extrinsic base region and a second extrinsic base region in said second epitaxial layer by a second implanting step using said base photoresist pattern as a mask, a first portion of said second epitaxial layer remaining undoped between said first extrinsic base region and said second extrinsic base region being in said first area, a second portion of said second epitaxial layer remaining undoped being in said second area;removing said base photoresist pattern;developing an emitter window photoresist pattern on said plurality of second trench isolation and on a first portion of said gate oxide layer, a second portion of said gate oxide layer covering said undoped first portion of said second epitaxial layer in said first area being exposed after developing said emitter window photoresist pattern;etching said second portion of said gate oxide layer to expose said undoped first portion of said second epitaxial layer in said first area;implanting a plurality of charges into said first doped region to form a selective implant collector having said second conductivity;removing said emitter window photoresist pattern;forming a first polysilicon layer on said exposed first portion of said second epitaxial layer in said first area, on a portion of said second portion of said gate oxide layer, and on said plurality of second trench isolation;patterning said first polysilicon layer to form an emitter pattern coupling to said exposed first portion of said second epitaxial layer in said first area;developing a collector photoresist pattern on said emitter pattern, on said plurality of second trench isolation, and on said second portion of said gate oxide layer, said first portion of said gate oxide layer covering said undoped second portion of said second epitaxial layer in said second area being exposed after developing said collector photoresist pattern;using said collector photoresist pattern as a mask to etch an exposed portion of said first portion of said gate oxide layer and underlying said undoped second portion of said second epitaxial layer in said second area to expose a portion of said first doped region;forming a metal silicide layer on said exposed portion of said first doped region; andremoving said collector photoresist pattern, said metal silicide layer being collector of said bipolar transistor, said emitter pattern being emitter of said bipolar transistor, said first extrinsic base region, said second extrinsic base region, and said undoped first portion of said second epitaxial layer in said first area composing base of said bipolar transistor.