Patent ID: 6172567
Filing Date: 2001-01-09
Classification: H03G

Abstract:
A semiconductor amplifier circuit comprising:a plurality of semiconductor amplifying elements each having a first terminal, a second terminal and a control terminal;an input terminal;an output terminal;a first power supply terminal;a second power supply terminal;a bias supply terminal:an output control circuit; andan output mode instruction terminal; whereinsaid plurality of semiconductor amplifying elements comprise a first semiconductor amplifying element and a second semiconductor amplifying element;said semiconductor elements having a configuration in which said first semiconductor amplifying element is supplied with a signal in response to a signal supplied to said input terminal and supplied with a bias at a predetermined level from said bias supply terminal at the control terminal thereof, is connected to said first power supply terminal at the first terminal thereof and is connected to said second power supply terminal at the second terminal thereof, in which said second semiconductor amplifying element is electrically connected to the first terminal of said first semiconductor amplifying element and connected to said bias supply terminal at the control terminal thereof, is connected to said first power supply terminal and said output terminal at the first terminal thereof and is connected to said second power supply terminal at the second terminal thereof such that a current flowing between the first and second terminals of said first semiconductor amplifying element is smaller than a current flowing between the first and second terminals of said second semiconductor amplifying element; and whereinsaid output control circuit is connected between the control terminal of said second semiconductor amplifying element and said bias supply terminal for controlling the level of the bias supplied to the control terminal of said second semiconductor amplifying element to limit the output of said semiconductor amplifier circuit to a predetermined level in a first output mode and for controlling the level of the bias supplied to the control terminal of said second semiconductor amplifying element in accordance with the output of said semiconductor amplifier circuit in a second output mode.