Patent ID: 6762950
Filing Date: 2004-07-13
Classification: G11C,H01L

Abstract:
A ferroelectric or electret volumetric memory device, wherein a ferroelectric or electret memory material is provided in sandwich between first and second electrode layers respectively comprising first and second parallel stripe-like electrodes forming word lines and bit lines of a matrix-addressable memory array, wherein word lines and bit lines of the matrix-addressable memory array are oriented substantially at right angles to each other, wherein memory cells are defined in volumes of memory material sandwiched between respective crossing word lines and bit lines, and wherein a plurality of memory arrays are provided in at least one stack such that the at least one stack of memory arrays realizes the memory device with a volumetric configuration,wherein a stack of memory arrays is formed with two or more ribbon-like structures being folded and/or braided into each other, each ribbon-like structure comprising a flexible substrate of non-conducting material, where first and second electrode layers respectively, are provided on each surface of the substrate, such that the first and second electrode layers each comprise parallel stripe-like electrodes provided extending along the ribbon-like structure, and a layer of memory material covers one of the electrode layers thereof and extends uninterrupted between the edges of the ribbon-like structure, that each memory array of the stack is formed by overlapping portions of a pair of adjacent ribbon-like structures folded and/or braided such that they cross in substantially orthogonal relationship, and that the word lines and memory layer of the memory array in the stack are contained in the first ribbon-like structure of a pair of adjacent structures of this kind and the bit lines contained in the second ribbon-like structure thereof.