Patent ID: 6518131
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method for fabricating a mask ROM comprising the steps of:providing a substrate where a memory cell array region and a peripheral region are defined; forming a buried layer on the substrate; forming a gate material layer by positioning a gate insulating film on the substrate having the buried layer; forming first gates in the memory cell array region, by covering the peripheral region, and etching the gate material layer according to a photolithography process; forming an insulating pattern on the substrate to fill up a space between the first gates and expose the surfaces of the first gates; forming second gates in the peripheral region, by covering the memory cell array region, and etching the gate material layer according to the photolithography process; and forming a low resistance layer on the first gates, and simultaneously forming a source/drain at both sides of the second gates, by doping an impurity to the substrate having the first and second gates.