Patent ID: 7144774
Filing Date: 2006-12-05
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a non-volatile memory, the method comprising: providing a substrate; forming a composite dielectric layer over the substrate, the composite dielectric layer comprising a bottom dielectric layer, a charge-storage layer and a top dielectric layer; forming a sacrificial layer over the composite dielectric layer; forming a mask layer over the sacrificial layer; patterning the mask layer to form a plurality of openings that expose the sacrificial layer; removing a portion of the sacrificial layer exposed by the first openings; forming a plurality of first gates in the first openings, wherein the first gates and the composite dielectric layer underneath the first gates form a plurality of first memory cells; removing the mask layer to form a plurality of second openings between the first gates; removing the sacrificial layer exposed by the second openings; forming an insulation layer at tops and sidewalls of the first gates; forming a plurality of second gates in the second openings, wherein the second gates and the composite dielectric layer underneath the second gates form a plurality of second memory cells, and the second memory cells and the first memory cells form a memory cell column; and forming a source/drain region in the substrate beside two sides of the memory cell column.