Patent ID: 7363097
Filing Date: 2008-04-22
Classification: G05B

Abstract:
1. An automatic design apparatus for a digital control system circuit including a control target circuit and a control apparatus circuit, the apparatus automatically designing a model of the control apparatus circuit in the case where a model of the control target circuit and a specification model of the digital control system circuit are given, the apparatus comprising: a control target input unit configured-to receive a first control target model written in a predetermined design description language, the first control target model being the model of the control target circuit; a control target model generating unit configured to generate a second control target model represented by a finite state machine model from the first control target model; a control target model storage unit configured to store the generated second control target model; a control specification input unit configured to receive at least a first control specification model written in a predetermined design description language, the first control specification model being the specification model of the control system circuit; a control specification model generating unit configured to generate a second control specification model represented by a finite state machine model from at least the first control specification model; a control specification model storage unit configured to store the second control specification model; a model composing unit configured to generate a control apparatus synthesis model by computing a logical AND of the second control target model stored in the control target model storage unit and the second control specification model stored in the control specification model storage unit, the control apparatus synthesis model being a synthesis model of the control apparatus circuit; a controllable simulation relation computing unit configured to compute controllable simulation relation representing a constraint condition imposed on the control apparatus synthesis model from the second control target model and the second control specification model; a controllable simulation relation storage unit configured to store the computed controllable simulation relation; a controllability determining unit configured to determine whether the control apparatus synthesis model is a model capable of providing control for satisfying the specification of the control system circuit on the basis of the controllable simulation relation; a permissible operation model generating unit configured to generate a permissible operation model from the control apparatus synthesis model and the controllable simulation relation, the permissible operation model being a model obtained by reducing the scale of the control apparatus synthesis model; a permissible operation model storage unit configured to store the generated permissible operation model; a control rule determining unit configured to determine a control rule capable of further reducing the scale of the permissible operation model; and a control apparatus model generating unit configured to generate a control apparatus model represented by a finite state machine model by computing a logical AND of the permissible operation model and the control rule.