Patent ID: 7666779
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A fabrication method of a semiconductor device, comprising the steps of: providing a semiconductor substrate having a plurality of bonding pads; forming a first passivation layer and a second passivation layer in a stack manner on the semiconductor substrate, and exposing the bonding pads of the semiconductor substrate from the first and second passivation layers; forming a metallic layer on each of the bonding pads, wherein a portion of the second passivation layer surrounding each of the bonding pads is covered by the metallic layer; applying a third passivation layer on the second passivation layer, and forming a plurality of openings in the third passivation layer to expose a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the corresponding one of the bonding pads; and forming a plurality of solder bumps on the portion of the metallic layer exposed via the openings.