Patent ID: 8261008
Filing Date: 2012-09-04
Classification: G06F,G11C

Abstract:
1. A NAND flash controller, comprising a bus timing interface, a flash timing generator, a DMA data transmission channel, a command and address data transmission channel, a channel selector, a data buffer region, a control register and a logic controller, wherein, the command and address data transmission channel is adapted to connect the bus timing interface with the channel selector and transmit command and address data; the data buffer region is adapted to receive message data sent from the bus timing interface through a system bus; the control register is adapted to receive an operation parameter configured through the system bus via the bus timing interface; the DMA data transmission channel is adapted to connect the logic controller with the channel selector and transmit the message data; the logic controller is adapted to write the message data into or read the message data from the data buffer region according to the operation parameter received from the control register, and generate a logic control signal and send the logic control signal through the DMA data transmission channel to the channel selector; and the channel selector is adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the logic control signal received from the logic controller for transmitting data.