Patent ID: 6154387
Filing Date: 2000-11-28
Classification: G11C

Abstract:
A semiconductor memory device comprising a capacitor, a first transistor, a second transistor, a word line, a bit line, a bit bar line, and a plurality of column selection plate driving lines,wherein the capacitor includes a first electrode, a second electrode opposing the first electrode, and a ferroelectric film sandwiched by the first and second electrodes, and stores and holds binary information utilizing a polarizing state of the ferroelectric film,the first transistor includes a first electrode, a second electrode, and a gate electrode, the second electrode being connected to the first electrode of the capacitor, the first electrode is connected to one of the bit line and the bit bar line, the gate electrode is connected to the word line, andthe second transistor includes a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the second electrode of the capacitor, the second electrode is connected to one of the plurality of column selection plate driving lines, the gate electrode is connected to the word line.