Patent ID: 6303944
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor wafer partitioned into a plurality of chip regions by a scribe line area;at least one device formation region formed in said plurality of chip regions;a device pattern formed in said at least one device formation region;a monitor pattern having planar dimensions of at least 5 .mu.m on a shorter side and 150 .mu.m or less on a longer side, said monitor pattern being formed simultaneously with said device pattern in said plurality of chip regions; andan interlayer insulating film formed on said semiconductor wafer so as to cover said device pattern and said monitor pattern;wherein the thickness of said interlayer insulating film is measurable using said monitor pattern, and wherein the measured thickness of said interlayer insulating film is used for controlling a chemical mechanical polishing process to reduce over polishing and under polishing.