Patent ID: 7939936
Filing Date: 2011-05-10
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a wiring board having a first surface and a second surface, said wiring board being provided with a plurality of first electrode pads exposed on the first surface, thereof, and a plurality of second electrode pads exposed on the second surface thereof, said first electrode pads being electrically connected to said second electrode pads, respectively; a semiconductor device mounted on the first surface of said wiring board, said semiconductor device including an endless ring-shaped resistance circuit formed in an interior of said semiconductor device along a periphery thereof, and a plurality of third electrode pads provided inside said endless ring-shaped resistance circuit and electrically connected to said endless ring-shaped resistance circuit, said third electrode pads being electrically connected to said first electrode pads, respectively; and a sealing resin layer formed over the first surface of said wiring board so that said semiconductor device and said first electrode pads are sealed and protected by said sealing resin layer, wherein said semiconductor device further comprises a multi-layered insulating structure, said endless ring-shaped resistance circuit being formed in said multi-layered insulating structure along a periphery thereof, said third electrode pads being formed on a top surface of said multi-layered insulating structure.