Patent ID: 7760715
Filing Date: 2010-07-20
Classification: H04L

Abstract:
1. A circuit to schedule between and rate-limit a plurality of flows comprising: (a) a first scheduling circuit, (b) a second scheduling circuit, (c) a first logic device, (d) a second logic device, (e) said first scheduling circuit arbitrates between a plurality of in-profile flows, (f) said second scheduling circuit arbitrates between a plurality of out-of-profile flows, (g) said first logic device detects when a scheduled flow of the first scheduling circuit is out-of-profile, (h) said first logic device, upon the out-of-profile detection, removes the scheduled flow from said plurality of in-profile flows over which the first scheduler arbitrates and adds said scheduled flow of the first scheduling circuit to said plurality of out-of-profile flows over which the second scheduler arbitrates, (i) said second logic device detects when a scheduled flow of the second scheduling circuit is in-profile, (j) said second logic device, upon the in-profile detection, removes the scheduled flow from said plurality of out-of-profile flows over which the second scheduler arbitrates and adds said scheduled flow of the second scheduling circuit to said plurality of in-profile flows over which the first scheduler arbitrates, (k) the scheduled flow of the first scheduling circuit signals a rate-limited arbitration between said plurality of in-profile flows and said plurality of out-of-profile flows.