Patent ID: 6842886
Filing Date: 2005-01-11
Classification: G06F,H01L

Abstract:
1. A basic cell of a gate array semiconductor device comprising: first and second p-channel MOS transistors and first and second n-channel MOS transistors, wherein the first p-channel MOS transistor and the first n-channel MOS transistor are disposed so as to share or divide a first gate, the second p-channel MOS transistor and the second n-channel MOS transistor are disposed to share or divide a second gate, the first gate has a first linear portion, a first bent portion that is bent toward the second gate at about 45 degrees with respect to a lengthwise direction, a second linear portion, a second bent portion that is bent away from the second gate at about 45 degrees with respect to the lengthwise direction, and a third linear portion located sequentially in order, and the second gate has a first linear portion, a first bent portion that is bent toward the first gate at about 45 degrees with respect to the lengthwise direction, a second linear portion, a second bent portion that is bent away from the first gate at about 45 degrees with respect to the lengthwise direction, and a third linear portion located sequentially in order.