Patent ID: 6800874
Filing Date: 2004-10-05
Classification: H01L

Abstract:
A CMOS of double vertical channel thin film transistor, comprising:a gate layer formed on a substrate; a first insulator layer formed on the substrate and the gate layer, wherein the first insulator layer has a flat part and two vertical walls, the flat part being formed between the two vertical walls; a semiconductor layer formed on the first insulator layer, wherein the semiconductor layer has two channels formed on the two vertical walls, and a first doped area and a second doped area formed to connect with two ends of the two channels respectively, and an intrinsic area formed on the flat part between the first doped area and the second doped area; a second insulator layer formed on the semiconductor layer, exposing two sides of the semiconductor layer to form an exposed pattern of the semiconductor layer; and a metal layer formed on the exposed pattern of the semiconductor layer.