Patent ID: 6275088
Filing Date: 2001-08-14
Classification: H03K

Abstract:
A clamping circuit, comprising:a first delay circuit to receive an input signal delivered over a transmission line and to deliver a second signal after a first preselected delay;a first transistor having a first enable input and coupled between a first supply voltage and the transmission line;a first driver circuit to receive the input signal and the second signal and to provide a first enable signal to the first enable input for a period of time corresponding to the preselected delay;an inverter having an input and an output, the input of the inverter electrically connected to the transmission line; anda second transistor electrically coupled between the first supply voltage and the transmission line, the second transistor having a second enable input that is electrically connected to the output of the inverter to enable the second transistor when the inverter outputs a predetermined first voltage level.