Patent ID: 7372085
Filing Date: 2008-05-13
Classification: H01L,Y10T

Abstract:
1. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a first pad having a top surface with a first region and a second region surrounding said first region, and wherein said metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and a metal trace over said passivation layer and over said first region, wherein said metal trace comprises electroplated copper, and wherein said metal trace is connected to said first pad through said first opening.