Patent ID: 8830731
Filing Date: 2014-09-09
Classification: G11C

Abstract:
1. A phase change memory device, comprising: an array of phase change memory cells; a data lookup table; a write component, configured to determine which of several transformations of a data chunk is optimal to write to said array; determine a write address in said data lookup table where the transformed data chunk is to be written to said array; write a selection symbol corresponding to the optimal transformation to a location in said data lookup table associated with said write address; and write the optimal transformation to the array at said write address; a read component, configured to retrieve a read address, and a selection symbol corresponding to a data chunk, from a data lookup table; read the data chunk from the array according to the read address; use the selection symbol to apply an appropriate inverse transformation to the data chunk, to thereby retrieve a corrected data chunk; and return said corrected data chunk.