Patent ID: 8302068
Filing Date: 2012-10-30
Classification: G03F,G06F

Abstract:
1. A method of designing a lithographic mask comprising the steps of: providing an integrated circuit design comprising a device layer of shapes to be printed and an initial on-wafer target layout corresponding to said device layer; providing an electrical metric for said integrated circuit design, said electrical metric having a functional relationship to a first dimension that is represented in said initial on-wafer target layout; providing a yield metric having a functional relationship to said first dimension that is represented in said initial on-wafer target layout; and improving said electrical metric, within a predetermined electrical criterion, in said initial on-wafer target layout by using a computer in modifying said first dimension to form a modified target layout such that a computed yield metric based on said modified target layout satisfies a predetermined yield constraint, wherein order of device modification is sorted based on electrical characteristic to be improved or based on value of said yield metric.