Patent ID: 6215147
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A flash memory device, which comprises:a semiconductor substrate;a tunneling oxide layer formed over the substrate;a plurality of floating gates formed at predefined locations over the tunneling oxide layer;a plurality of sidewall spacers, each being formed on the sidewall of one of the floating gates, wherein a portion of the substrate between the sidewall spacers is still exposed;a plurality of selective polysilicon blocks on the exposed portion of the substrate, each being formed between one neighboring pair of the floating gates, and the selective polysilicon blocks having a top surface lower than a top surface of the floating gates;a plurality of impurity-doped regions in the substrate, each being formed beneath one of the selective polysilicon blocks to serve as a plurality of buried bit line for the flash memory device;a plurality of insulating layers, each being formed on one of the selective polysilicon blocks and between the sidewall spacers;a dielectric layer covering all of the floating gates and the insulating layers; anda plurality of control gates formed over the dielectric layer, each being located above the floating gates.