Patent ID: 7126223
Filing Date: 2006-10-24
Classification: H01L

Abstract:
1. A device comprising: a first metallization layer patterned within a first dielectric layer; a second metallization layer patterned within a second dielectric layer; an interconnect patterned within the second dielectric layer and an etch stop layer (ESL) to couple the first metallization layer to the second metallization layer, the interconnect being exclusively bordered on at least two sides by spacers formed by portions of the second dielectric layer and the ESL remaining after removal of the ESL and the second dielectric layer to assist in supporting the second metallization layer; a third metallization layer patterned within the second dielectric layer, said third metallization layer is laterally spaced apart from said second metallization layer; a sacrificial inter layer dielectric (ILD) situated between said second and third metallization layers; and a diffusion layer extending from over said second metallization layer, said sacrificial ILD and said third metallization layer with said sacrificial ILD subsequently being removed to form an air gap between said second metallization layer and said third metallization layer.