Patent ID: 9218987
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A method of packaging a top-side cooled semiconductor package of a semiconductor die interconnected with a plurality of elevation-adaptive conductive intimate interconnection plates and elevation-adaptive conductive stacked interconnection plates, the method comprising the steps of: a) providing a circuit substrate having a plurality of terminal leads for external electrical connection; b) providing the semiconductor die and attaching it atop the circuit substrate; c) providing and attaching one or more intimate interconnection plates to top contact areas of said semiconductor die and said circuit substrate for electrical connection between said top contact areas and said terminal leads; d) providing and attaching a number of stacked interconnection plates atop a selected intimate interconnection plate; e1) placing a detachable mask over a top surface of the number of stacked interconnection plates to be ultimately exposed; e2) molding an encapsulant over the circuit substrate, the semiconductor die and the one or more intimate interconnection plates and enclosing a majority portion of each of the number of stacked interconnection plates; and e3) removing the detachable mask to expose the top surface of the number of stacked interconnection plates to maintain effective top-side cooling.