Patent ID: 6157999
Filing Date: 2000-12-05
Classification: G06F

Abstract:
A data processor comprising:a return memory location having a return address storage portion coupled to receive an update signal;a link stack havinga plurality of return address storage portions, wherein a first one of the plurality of return address storage portions is a current storage portion;a comparator portion coupled to the plurality of return address storage portions for receiving values stored in the plurality of return address storage portions and for providing a match indicator;an update portion coupled for receiving the match indicator from the comparator portion and coupled to the plurality of return address storage portions of the link stack;an enable node; anda prediction verifier coupled to a second one of the plurality of return address storage portions of the link stack and to the return address storage portion of the return memory location, and having an output coupled to the enable node of the link stack for enabling a synchronization of the link stack when the return address storage portion of the return memory location and a predicted address from the link stack do not compare, wherein synchronization of the link stack includes:determining if a match occurs between a value stored in the plurality of return address storage portions and a value stored in the return memory location; and providing the match indicator if the match occurs.