Patent ID: 6041003
Filing Date: 2000-03-21
Classification: G11C

Abstract:
A memory device comprising:an array of word lines and complementary bit line pairs;a number of memory cells that are each addressably coupled to a word line and a bit line of a complementary bit line pair;a row decoder and a column decoder that are coupled to the array so as to select a memory cell;a number of sense amplifiers, each coupled to a complementary bit line pair;an equilibration voltage source; andwherein each complementary bit line pair includes:an equilibration circuit that is coupled to the bit lines of the complementary bit line pair,a depletion mode transistor that couples the equilibration voltage source to the equilibration circuit; andwherein a gate of the depletion mode transistor is coupled to receive a control signal from the column decoder that selectively applies a negative voltage to the depletion mode transistor to isolate the equilibration voltage source from the equilibration circuit.