Patent ID: 6091629
Filing Date: 2000-07-18
Classification: G06F,G11C

Abstract:
A semiconductor memory apparatus comprising:a memory array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections between said word lines and said bit lines;at least a first global bit line connected to a sense amplifier;at least a second global bit line connected to a write amplifier; anda selection circuit for connecting a plurality of pairs of said bit lines selectively to said first global bit line and said second global bit line;wherein said first and second global bit lines are arranged on said memory array, andwhen reading data from said memory array, said bit lines are connected electrically to said first global bit line and data are output through said sense amplifier, andwhen writing data into said memory array, data are input to said second global bit line through said write amplifier, and said bit lines are connected electrically to said second global bit line, anda circuit for subjecting said second global bit line to at least one of a charge and discharge operation to Prepare the second global bit line for writing data into said memory array concurrently with a read operation for reading data from said memory array using said first global bit line.