Patent ID: 7534647
Filing Date: 2009-05-19
Classification: G11C,H01L

Abstract:
1. A method for manufacturing a memory device, comprising: forming an electrode layer having a top surface, the electrode layer including a first electrode member and a second electrode member and an insulating member between the first and second electrode members, such that the first and second electrode members and the insulating member extend to the top surface of the electrode layer, the insulating member having a width between the first and second electrode members at the top surface; forming a trench in a film of material on the electrode layer, wherein the trench extends over the insulating member between the first and second electrode members; depositing a layer of memory material in the trench to form a damascene patch of memory material on the top surface of the electrode layer across the insulating member, the damascene patch comprising a film of memory material having a first side and a second side and contacting the first and second electrode members on the first side, the patch defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the width of the insulating member, wherein the memory material has at least two solid phases; and forming a patterned conductive layer electrically coupled to the first electrode member and arranged so that the patch and the first electrode member are in electrical series between the second electrode member and the patterned conductive layer.