Patent ID: 6953734
Filing Date: 2005-10-11
Classification: H01L

Abstract:
1. A method for manufacturing a shallow trench isolation (STI) in a semiconductor device, the method comprising the steps of: a) preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; b) forming an isolation trench with a predetermined depth in the semiconductor substrate; c) forming a wall oxide on the trench; d) forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; e) carrying out a nitridation process for forming a nitrided oxide; f) forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and g) planarizing a top face of the insulating layer, wherein the step e) is carried out in an annealing furnace or a rapid thermal process (RTP) by using a nitrogen-containing gas selected from the group consisting of N