Patent ID: 6566696
Filing Date: 2003-05-20
Classification: H01L

Abstract:
An integrated circuit, comprising:a substrate; and a plurality of transistors positioned on a plurality of active areas of the substrate, each of the transistors having a gate insulating layer, a gate electrode positioned on the gate insulating layer, a doped region of a first conductivity type and having a first horizontal junction, a first source/drain region of the first conductivity type and having a second horizontal junction, and a second source/drain region of the first conductivity type and having a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region, the second and third horizontal junctions being positioned substantially at the first horizontal junction, and the portion of the doped region positioned in the channel region being doped with an impurity of a second conductivity type that is opposite to the first conductivity type.