Patent ID: 9036482
Filing Date: 2015-05-19
Classification: H04L

Abstract:
1. A system, comprising: core processors that are communicatively coupled together at a substrate via routing nodes based on a set of nonblocking processes; a network component configured to route data packets through the routing nodes and the core processors via communication links, wherein the data packets comprise information relating to a path of communication links for a routing of the data packets; a bufferless crossbar switch configured to facilitate communication of the data packets via the communication links; wherein a communication link of the communication links comprises a set of channels that include a data sub-channel configured to communicate the data packets, an acknowledgement sub-channel configured to communicate an acknowledgement message, and a release sub-channel configured to communicate a release message, and wherein the network component is further configured to route the data packets to an intended destination, absent network blocking, via a pathway of the set of channels and a set of sub-channels comprising at least a sub-channel based on information stored in a head flit of the data packets, wherein the information specifies the pathway based on at least one idle channel being determined to correspond to an outgoing link.