Patent ID: 7786778
Filing Date: 2010-08-31
Classification: H03K,H03M

Abstract:
1. A driver circuit configured to generate an output signal Vout having a controlled slew rate, the output signal Vout being generated at an output node of the driver circuit, the driver circuit comprising: a first transistor having (i) a first node coupled to a high supply voltage and (ii) a second node coupled to the output node of the driver circuit, the first transistor to pass the high supply voltage to the output node based on a first gate voltage on a gate of the first transistor; a second transistor having (i) a first node coupled to a low supply voltage and (ii) a second node coupled to the output node of the driver circuit, the second transistor to pass the low voltage to the output node based on a second gate voltage on a gate of the second transistor; and a logic block configured to control the slew rate of the output signal Vout by (i) controlling a slew rate of the first gate voltage on the gate of the first transistor during a first intermediate voltage period, and (ii) controlling a slew rate of the second gate voltage on the gate of the second transistor during a second intermediate voltage period, wherein the logic block comprises wherein the logic block receives a single pulse-width modulated signal as an input, and generates the first gate voltage and the second gate voltage based on the single pulse-width modulated signal.