Patent ID: 7793022
Filing Date: 2010-09-07
Classification: H04L

Abstract:
1. A digital repeater for repeating bidirectional signals between a host side wired-AND bus connected to a master device, the host side wired-AND bus comprising a host side serial clock line (SCLH) and a host side serial data line (SDAH), and a remote side wired-AND bus connected to a slave device, the remote side wired-AND bus comprising a remote side serial clock line (SCLR) and a remote side serial data line (SDAR), the digital repeater comprising: an internal repeater logic circuitry; two host side serial line interface cells for interfacing between the internal repeater logic circuitry and the host side serial clock and data lines; two remote side serial line interface cells for interfacing between the internal repeater logic circuitry and the remote side serial clock and data lines; a START/STOP detector for receiving signals from the host side serial clock and data lines and determining start and stop flags indicating START and STOP conditions respectively on the wired-AND bus; a protocol sequencer for receiving signals from the remote side serial clock and data lines, determining whether the master device on the host side wired-AND bus or the slave device on the remote side wired-AND bus is transmitting, and asserting a “slaveData” flag to indicate that the slave device is transmitting; and a state machine for receiving clock signals arriving on the host and remote side serial clock lines, receiving the start, stop, and “slaveData” flags, and sending clock signals on the host and remote side serial clock lines and determining whether to pass, hold, or force serial data signals on the host and remote side serial data lines, wherein to pass is to pass a signal through the repeater, to hold is to hold a signal at a previous value, and to force is to set a signal on one side of the repeater to a logical zero LO or a logical one HI regardless of the signal on the other side of the repeater.