Patent ID: 9129887
Filing Date: 2015-09-08
Classification: G11C,H01L

Abstract:
1. A method of forming a memory device, comprising: providing a semiconductor substrate having a surface region; forming a first dielectric material overlying the surface region of the semiconductor substrate; forming a first electrode material layer overlying the first dielectric material; forming a resistive material layer overlying the first electrode material; forming a metal material layer overlying the resistive material; forming a resistive switching material layer overlying the metal material layer, wherein such resistive switching material layer comprises an amorphous silicon material; forming an interface layer between and in ohmic contact with both the metal material layer and the resistive switching material layer, wherein such interface layer comprises conductive polycrystalline silicon; subjecting the layers of the first electrode material, the resistive material, the metal material, the interface and the resistive switching material to a first pattern and etch process to form a first structure and a first electrode structure, the first structure and the first electrode structure being elongated in shape and extending in a first direction; subjecting the first structure to a second pattern and etch process to form a second structure comprising one or more switching elements and one or more resistors associated with the one or more switching elements, respectively; forming a second electrode structure extending in a second direction spatially perpendicular to the first electrode structure, overlying and in ohmic contact with at least the second structure; and forming one or more switching devices from at least the first electrode structure, the one or more switching elements, the one or more resistors associated with the one or more switching elements, respectively, and the second electrode structure, wherein a resistor from the one or more resistors limits a programming current in a respective switching element from the one or more switching elements to be no greater than a predetermined current upon application of a programming voltage to an electrode from the second electrode structure that is coupled to the respective switching element, and wherein the resistor is characterized by a resistance substantially similar to the on state resistance of the respective switching element, such that an erase voltage of the switching element is increased to about a write voltage of the switching element.