Patent ID: 6040729
Filing Date: 2000-03-21
Classification: H03K

Abstract:
A digital output buffer for a multiple voltage system, comprising:a first voltage limiting logic circuit having a first power supply terminal for receiving a first voltage, a second power supply terminal for receiving a second voltage, an input terminal for receiving a digital input signal, a first output terminal for providing a first predrive signal, and a second output terminal for providing a second predrive signal;said digital input signal characterized as having logic levels corresponding to said second voltage and a third voltage;said first predrive signal having logic levels corresponding to either said first voltage or a first intermediate voltage;said second predrive signal having logic levels corresponding to either a second intermediate voltage or said second voltage;a first transistor having a first current electrode for receiving said first voltage, a control electrode for receiving said first predrive signal, and a second current electrode coupled to an output terminal of the digital output buffer; anda second transistor having a first current electrode coupled to said output terminal of the digital output buffer, a control electrode for receiving said second predrive signal, and a second current electrode for receiving said second voltage,a difference between said first voltage and said first intermediate voltage being less than a dielectric breakdown voltage of said first transistor,said first voltage limiting logic circuit comprising:a first bias element having a first terminal for receiving said first voltage, and a second terminal for providing said first predrive signal;a voltage dropping element having a first terminal coupled to said second terminal of said first bias element, and a second terminal for providing said second predrive signal; andswitching means coupled between said second output terminal of said first voltage limiting logic circuit and said second power supply terminal for providing either said first voltage or said first intermediate voltage to said first output terminal of said first voltage limiting logic circuit in response to said digital input signal.