Patent ID: 7199014
Filing Date: 2007-04-03
Classification: H01L

Abstract:
1. A method of manufacturing a field effect transistor, comprising the steps of: forming a buffer layer on a semi-insulating substrate; forming a channel layer on said buffer layer; forming a first semiconductor layer consisting of InGaP on said channel layer; forming a second semiconductor layer consisting of AlGaAs on said first semiconductor layer; forming a cap layer on the second semiconductor layer; forming a first photoresist pattern having an opening on said cap layer; forming a first opening in said cap layer by removing said cap layer by means of performing a selective dry or wet etching process to said second semiconductor layer using said first photoresist pattern as a mask; forming an opening in said second semiconductor layer by selectively etching said second semiconductor layer to said first semiconductor layer through the first opening of said cap layer; forming on said cap layer a second photoresist pattern having an opening wider than the opening of said first photoresist pattern; forming a second opening in said cap layer by selectively etching only said cap layer using said second photoresist pattern as a mask; and forming a gate electrode which is arranged on said second semiconductor layer inside the second opening of said cap layer, and embeds the opening of said second semiconductor layer.