Patent ID: 6352893
Filing Date: 2002-03-05
Classification: C25D,H01L

Abstract:
A method for fabricating a semiconductor device comprising the steps of:providing a semiconductor wafer having exposed p-doped silicon regions and exposed n-doped silicon regions; and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions selective to the n-doped silicon regions when a potential difference is provided between the wafer and the solution, wherein the step of placing the wafer in an electrochemical cell further includes the steps of: placing the wafer in an electrochemical cell such that the wafer has an exposed surface area including the exposed p-doped silicon regions thereon; and providing a counter electrode in the solution having a substantially same exposed surface area as the exposed surface area of the wafer.