Patent ID: 6501187
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A semiconductor package structure having central leads, comprising:a substrate having an upper surface, a lower surface, and a long slot penetrating from the upper surface to the lower surface, the lower surface being formed with a plurality of signal output terminals; a semiconductor device on which are formed of a plurality of bonding pads, the semiconductor device being mounted on the upper surface of the substrate, the plurality of bonding pads on the semiconductor device being exposed via the long slot of the substrate, and the length of the semiconductor device being smaller than that of the long slot of the substrate so that a channel is formed at one side of the long slot when the semiconductor device is mounted on the substrate; a plurality of wires within the long slot of the substrate for electrically connecting the plurality of bonding pads on the semiconductor device to the plurality of signal output terminals on the substrate; and glue for sealing the upper surface of the substrate and the semiconductor device to protect the semiconductor device, the glue being poured into the lower surface of the substrate via the channel formed by the long slot of the substrate, for covering the plurality of wires.