Patent ID: 6346442
Filing Date: 2002-02-12
Classification: H01L,Y10S

Abstract:
A method for forming a fieldless array of floating gate transistors on a semiconductor region having a first conductivity type and a first surface, the method comprising the steps of:forming a first dielectric layer over the first surface of said semiconductor region having the first conductivity type; forming a floating gate layer over the first dielectric layer; forming a second dielectric layer over the floating gate layer; forming a mask over the second dielectric layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the semiconductor region; and implanting a first impurity having the first conductivity type into the bit line regions of the semiconductor region, wherein the first impurity is implanted through the openings of the mask, the first dielectric layer, the floating gate layer, and the second dielectric layer.