Patent ID: 8603846
Filing Date: 2013-12-10
Classification: B81C,H01L

Abstract:
1. A method for planarizing topographies on a surface of a semiconductor substrate including at least one cavity or channel ranging from several microns to several mils in depth, said method comprising: providing a planarizing material atop said surface including filling said at least one cavity or channel with said planarizing material to produce a planarized surface, patterning a feature over said filled at least one cavity or channel using a mask structure; etching away the planarizing fill material from said cavity or channel according to said patterned feature to produce an overhang structure including an opening atop said cavity or channel; and, depositing a material on a lower surface of said cavity or channel through said opening, wherein said step of filling said at least one cavity or channel with said planarizing material includes implementing a screening technique.