Patent ID: 6757284
Filing Date: 2004-06-29
Classification: H04L

Abstract:
A packet switch element of a packet switch comprising:a resequencer to resequence a plurality of sets of streams of packets received from one or more interconnection networks of the packet switch, the resequencer including: a plurality of buffers for storing the plurality of sets of streams of packets; a plurality of input queues to receive packets from an input set of streams of packets from the plurality of buffers, the input queues aggregated into a plurality of input groups; control logic to control packets of which one of the plurality of sets of streams of packets are currently received by the plurality of input queues, and to context switch to a next set of the plurality of sets of streams of packets every predetermined duration; a plurality of group comparators, each of the plurality of group comparators coupled to the input queues within one of the plurality of input groups to determine a first group packet from packets at the head of its respective one of the plurality of input groups; a plurality of group output queues, each of the plurality of group output queues coupled to one of the plurality of group comparators and one of the plurality of input groups to receive one of the first group packets; and an output comparator coupled to the plurality of group output queues to determine a first output packet from packets at the head of the plurality of output queues.