Patent ID: 6869826
Filing Date: 2005-03-22
Classification: G11C,H01L,Y10T

Abstract:
1. A method of stacking a first integrated circuit die and a second integrated circuit die on a base having a surface comprising: forming a plurality of flip-chip pads on the surface of the base; forming a plurality of wire bond pads on the surface of the base; connecting at least one pad of the plurality of flip-chip pads to at least one pad of the plurality of wire bond pads; providing a first integrated circuit die having a front-side surface having a plurality of flip-chip bumps thereon and having a back-side surface; positioning the front-side surface of the first integrated circuit die facing the surface of the base; aligning at least one flip-chip bump of the plurality of flip-chip bumps on the front-side surface of the first integrated circuit die with at least one pad of the plurality of flip-chip pads on the surface of the base; connecting the at least one flip-chip bump of the plurality of flip-chip bumps on the front-side surface of the first integrated circuit die to the at least one pad of the flip-chip pads on the surface of the base; providing a second integrated circuit die having a front-side surface having a plurality of bond pads thereon and having a back-side surface; positioning the back-side surface of the second integrated circuit die facing the back-side surface of the first integrated circuit die; attaching the back-side surface of the second integrated circuit die to the back-side surface of the first integrated circuit die; connecting at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die to at least one pad of the plurality of wire bond pads on the surface of the base; and sealing between at least a portion of the front-side surface of the first integrated circuit die and the surface of the base.