Patent ID: 6180443
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method of fabricating a semiconductor device having first and second transistors connected in series in a semiconductor substrate, the method comprising the steps of:forming an insulating film pattern on the semiconductor substrate such that a first region of the semiconductor substrate is exposed and a second region of the semiconductor substrate is covered;forming a punch-through stop layer by implanting impurity ions in the first region of the semiconductor substrate, the second region of the semiconductor substrate being masked from the impurity ions by the insulating film pattern;forming first and second gate electrodes respectively on the first and second regions of the semiconductor substrate, the first gate electrode located over the punch-through stop layer; andforming first, second, and third heavily doped impurity regions in the semiconductor substrate at sides of the first and second gate electrodes, wherein the first and second transistors are both one of NMOS and PMOS transistors.