Patent ID: 6654875
Filing Date: 2003-11-25
Classification: G06F

Abstract:
A circuit arrangement in a computer system for dual-mode execution of instructions having functions specified in operation codes, comprising:a control word RAM having an address port and an output port, the control word RAM arranged for storage of a plurality of control words associated with the operation codes, respectively, wherein predetermined ones of the control words contain a first address referencing microcode for performing the function in a first mode and a second address referencing microcode for performing the function in a second mode, and predetermined ones of the words in the control word RAM include an alternative-mode-present bit indicating presence of the second address; a selector having an output port and input ports coupled to the output port of the control word RAM, the selector arranged to receive and select between the first and second addresses responsive to a control signal; a microcode RAM having an address port coupled to the output port of the selector and configured with a first set of microcode instructions associated with the first mode and a second set of microcode instructions associated with the second mode; a register having an input port and an output port; a logic circuit for driving a state of the control signal to the selector responsive to states of the altemative-mode-present bit and an alternative-mode-enable bit in the register; and instruction-execution circuitry coupled to the microcode RAM.