Patent ID: 6917652
Filing Date: 2005-07-12
Classification: H04N

Abstract:
1. A video decoder comprising: a memory having a bitstream buffer area and a frame memory area, with each area divided again according to a number of video bitstreams to be decoded, for storing a plurality of received video bitstreams to respective areas; a single video decoding part for time multiplexing the plurality of video bitstreams received through the memory in fixed units, to decode the bitstreams, and storing respective areas of the memory; multi-display controlling part for assigning a display number to every display frame of the video bitstream according to a frame rate and a film mode, reading a data decoded in synchronization to a display synchronization signal from the memory and forwarding in a time multiplexing fashion, and reducing the display number after the data is forwarded; and, a multi-decoding controlling part for determining a video bitstream to be decoded at the present time among the plurality of video bitstreams according to a display state of the multi-display controlling part, and forwarding the video bitstream to the single video decoding part.