Patent ID: 6526573
Filing Date: 2003-02-25
Classification: G06F

Abstract:
A compiler optimization method for optimizing a scheduled block of instructions having a condition resolution instruction included on a critical path, said method comprising the acts of:identifying a scheduled critical path including a condition resolving operation, a merge operation where selection of inputs from two predecessor operations is predicated by the resolution of the condition, and a first successor operation receiving a result selected by the merge operation when the condition is resolved; scheduling unzipped duplicate first successor operations of the first successor operation prior to the merge operation so that said unzipped duplicate first successor operations can be executed while the condition is being resolved, with each unzipped duplicate first successor operation receiving a result from a respective one of said predecessor operations; determining a first time of termination of a first set of operations, including a first unzipped duplicate first successor operation, which outputs a first result selected by said merge operation when said condition resolves to a first value; determining a second time of termination of a second set of operations, including a second unzipped duplicate first successor operation, which outputs a second result selected by said merge operation when said condition resolves to a second value; and inserting a conditional branch operation in place of said merge operation to control selection of said first or second outputs to transfer to a subsequent scheduled block so that selection is performed when said condition is resolved.