Patent ID: 7998821
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A method of manufacturing complementary metal oxide semiconductor transistor (CMOS), comprising: providing a substrate comprising at least a first well, at least a second well, and an insulation between the first well and the second well; forming at least a first gate structure having at least one sidewall on the first well, a second gate structure on the second well; depositing a first dielectric layer on the first gate structure and the second gate structure and performing one etching process to form the first dielectric layer into a first block layer on the second well and at least a first spacer along the sidewall of the first gate structure and expose the other substrate surface on the first well; forming a plurality of first dopant regions in the substrate around the first gate structure by implanting dopant after forming the first block layer on the second well; utilizing the first block layer formed with the first spacer as mask to form a plurality of first recesses in the substrate outside the first spacer around the first gate structure by an etching process; forming a plurality of first epitaxial layers in the first recesses; and forming a plurality of second dopant regions in the substrate outside the first spacer around the first gate structure by implanting dopant after the first epitaxial layer.