Patent ID: 6351149
Filing Date: 2002-02-26
Classification: H03K

Abstract:
A MOS transistor output circuit comprising:a first p-channel MOS transistor having a drain; a first n-channel MOS transistor having a drain connected with the drain of said first p-channel MOS transistor to form a first common drain; a second p-channel MOS transistor having a drain; a second n-channel MOS transistor having a drain connected with the drain of said second p-channel MOS transistor to form a second common drain; an output terminal formed across said first and second common drains such that an output signal having a rising edge and a falling edge appears at said output terminal; said first p-channel MOS transistor and said first n-channel MOS transistor having gates to which a certain signal corresponding to an input signal or an inversion of said input signal is applied, said input signal having a rising edge and a falling edge; a first signal generation means for detecting the falling edge or the rising edge of said input signal and producing a first signal if said certain signal corresponds to said input signal or said inversion, respectively, said first signal being supplied to the gate of said second p-channel MOS transistor; a second signal generation means for detecting the rising edge or the falling edge of said input signal and producing a second signal if said certain signal corresponds to said input signal or said inversion, respectively, said second signal being supplied to the gate of said second n-channel MOS transistor; wherein said second p-channel MOS transistor is held in conduction during a first period beginning with the rising edge of said output signal and ending with an instant when the output signal can be regarded as having logic H level; and said second n-channel MOS transistor is held in conduction during a second period beginning with the falling edge of said output signal and ending with an instant when the output signal can be regarded as having logic L level.