Patent ID: 9224479
Filing Date: 2015-12-29
Classification: G11C

Abstract:
1. A controller-implemented method for adjusting a threshold voltage for a NAND flash memory having a plurality of cells, the method comprising: a) obtaining, at a NAND flash memory controller, a first probability that a read state of a selected cell in the plurality of cells is different from a write state of the selected cell, the read state being a first bit value and the write state being a second bit value; b) obtaining, at the NAND flash memory controller, a second probability that the write state of the selected cell is the first bit value and the read state is the second bit value; c) providing, at the NAND flash memory controller, an error signal to an iterative optimization method, the error signal comprising a difference between the first and second probabilities; and d) adjusting, at the NAND flash memory controller and using the iterative optimization method, a cell read threshold voltage for the selected cell based on the difference between the first and second probabilities, to generate an adjusted cell read threshold voltage, the method further comprising: reading, at the NAND flash memory controller, all pages in a block of the NAND flash memory; using an error correction code (ECC) at the NAND flash memory controller to determine error locations upon which the first and second probabilities are based; mapping, at the NAND flash memory controller, the error locations with respect to cell read threshold voltages; and accumulating, at the NAND flash memory controller, the error locations with respect to the cell read threshold voltages over the block and generating a voltage transition matrix.