Patent ID: 8819100
Filing Date: 2014-08-26
Classification: G06F

Abstract:
1. A multiply accumulate (MAC) unit, comprising: an adder having first and second adder inputs and an adder output; an accumulation register configured to store a value equal to a sum of a current input to the adder and a preceding output of the adder previously stored in the accumulation register, wherein the accumulation register comprises an output and an input coupled to the adder output; a bit-shift element having an input coupled to the output of the accumulation register; a feedback path that includes an arithmetic element disposed thereon, wherein the feedback path has a first end, which branches off a path connecting the output of the accumulation register and the input of the bit-shift element, and has a second end, which is coupled to the second adder input; and a switch disposed between the arithmetic element and the second adder input, wherein the switch has a first input terminal coupled to the arithmetic element, a second input terminal coupled to another data path, and an output terminal coupled to the second adder input, wherein the switch selectively couples the arithmetic element and the another data path to the second adder input.