Patent ID: 6093617
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method for fabricating a stacked capacitor structure, for a DRAM device, on a semiconductor substrate, wherein a surface area of the stacked capacitor structure is increased by using HSG polysilicon for the top layer of a storage node electrode, with said storage node electrode featuring a hemispherical grain silicon surface, obtained from a combination of materials and process steps that include an intrinsic amorphous silicon layer, deposited at a first temperature, deposited on an underlying doped polysilicon layer, then followed by an in situ anneal procedure, performed at a second temperature, greater than said first temperature, used for deposition of said amorphous silicon layer, and with said in situ anneal procedure performed at a low pressure, comprising the steps of:providing a transfer gate transistor, including a storage node contact hole, opened in an insulator layer, exposing a source and drain region, in said semiconductor substrate;depositing a thin first polysilicon layer, between about 500 to 600 Angstroms, on sides of, and on bottom of said storage node contact hole, contacting said source and drain region, located on bottom of said storage node contact hole, with said thin first polysilicon layer not completely filling said storage node contact hole;depositing said intrinsic amorphous silicon layer, at a thickness between about 600 to 1500 Angstroms, at said first temperature, between about 490 to 550.degree. C., on said thin first polysilicon layer, with said intrinsic amorphous silicon layer not completely filling said storage node contact hole;in situ annealing, performed at said second temperature, between about 600 to 650.degree. C., and at a pressure between about 0.5 to 1.5 mtorr, to convert said intrinsic amorphous silicon layer to a hemispherical grain, (HSG), polysilicon layer;patterning of said HSG polysilicon layer, and of underlying, said thin first polysilicon layer, to create storage node electrode, for a stacked capacitor, (STC), structure;forming a composite dielectric layer on the top surface of said HSG polysilicon layer;depositing a second polysilicon layer; andpatterning of said second polysilicon layer to create an upper electrode, for said STC structure.