Patent ID: 6828833
Filing Date: 2004-12-07
Classification: H03K

Abstract:
A complementary metal-oxide semiconductor (CMOS) output buffer comprising:a pre-driver logic, comprising a clock input, an enable input, a first output, a second output, a positive power input, and a negative power input; a first inverter, comprising a first inverter input and a first inverter output; a second inverter, comprising a second inverter input and a second inverter output; a nand gate, comprising a first nand gate input, a second nand gate input, and a nand gate output; a nor gate, comprising a first nor gate input, a second nor gate input, and a nor gate output; a first comparator, comprising a first comparator positive input, a first comparator negative input, and a first comparator output; a second comparator, comprising a second comparator positive input, a second comparator negative input, and a second comparator output; a resistor, comprising a first end and a second end; a p-channel metal-oxide semiconductor (PMOS), comprising a PMOS gate, a PMOS source, and a PMOS drain; and an n-channel metal oxide semiconductor (NMOS), comprising an NMOS gate, an NMOS source, and an NMOS drain; whereby, the first output of the pre-driver logic is coupled to the first inverter input and the first inverter output is coupled to the first nand gate input and the second output of the pre-driver logic is coupled to the second inverter input and the second inverter output is coupled to the first nor gate input; whereby, the second nand gate input is coupled to the first comparator output and the second nor gate input is coupled to the second comparator output; whereby, the nand gate output is coupled to the PMOS gate and the nor gate output is coupled to the NMOS gate; whereby, the PMOS source and the positive power input are coupled to a first positive power supply and the NMOS source and the negative power input are coupled to a first negative power supply; whereby, the PMOS drain, NMOS drain, and the first end of the resistor are coupled together; whereby, the second end of the resistor, the first comparator negative input, and the second comparator negative input are coupled together; whereby, the first comparator positive input is coupled to a second positive power supply and the second comparator positive input is coupled to a second negative power supply; and whereby, the second positive power supply is less than the first positive power supply and the second negative power supply is greater than the first negative power supply.