Patent ID: 8822300
Filing Date: 2014-09-02
Classification: H01L

Abstract:
1. A method for manufacturing a transient voltage suppressor (TVS) device, comprising: a) forming a first epitaxial layer of a first conductivity type on top of an n-type semiconductor substrate; b) forming a buried layer of an n-type semiconductor material within a top surface of the first epitaxial layer; c) forming an implant layer of a p-type semiconductor material within the first epitaxial layer, wherein the implant layer is located below the buried layer and a length of the implant layer extends beyond a length of the buried layer; d) forming a second epitaxial layer of a p-type semiconductor material type on top of the first epitaxial layer; e) forming a set of trenches in the second epitaxial layer and the first epitaxial layer, the set of trenches include a first trench at an edge of the buried layer and an edge of the implant layer, a second trench at another edge of the buried layer and extending into the implant layer, and a third trench at another edge of the implant layer; f) lining each trench with a dielectric material; g) filling a remaining portion of each trench with dielectric material or polysilicon; h) forming a set of source regions of a n-type semiconductor material within a top surface of the second epitaxial layer, the set of source regions including first and second source regions located between the first and second trenches a third source region located between the second and third trenches and a fourth source region located such that the third trench is between the third and fourth source regions; i)) forming a pair of implant regions of a p-type semiconductor material within the top surface of the second epitaxial layer, the pair of implant regions including a first implant region located between the first source region and the second source region, and a second implant region located between the third trench and the third source region adjacent a sidewall of the third trench, a vertical PN junction being formed by the buried layer, second epitaxial layer and first implant region, a lateral PN junction being formed by the third source region, second epitaxial layer and second implant region.