Patent ID: 6921700
Filing Date: 2005-07-26
Classification: H01L

Abstract:
1. A method of fabricating a vertical multiple-channel FET device comprising: providing an integrated circuit substrate; providing at least two layers of a first composition having a first etch property; providing at least one layer of a second composition having a second etch property, wherein the at least two layers of the first composition and the at least one layer of the second composition are formed to have a substantially homogenous crystallinity and wherein the at least two layers of the first composition are separated by the at least one layer of the second composition; forming a blocking layer over the at least two layers of the first composition and the at least one layer of the second composition; patterning the blocking layer to define placement of a first current electrode region, a second current electrode region and a plurality of channels; etching exposed portions of the at least two layers of the first composition and the at least one layer of the second composition to form the first current electrode region, the second current electrode region and channel regions extending from the integrated circuit substrate; further etching the at least one layer of the second composition to remove said at least one layer of the second composition and form the plurality of channels comprised of the first composition and located above and below any removed portion of the at least one layer of the second composition; depositing a control electrode dielectric around each of the plurality of channels; depositing control electrode material around the control electrode dielectric; selectively masking and etching the control electrode material to form a control electrode on top, bottom and sidewall surfaces of at least one of the plurality of channels; and forming a spacer to isolate the control electrode material from the first current electrode region and the second current electrode region.