Patent ID: 7189621
Filing Date: 2007-03-13
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device including a plurality of trench-gate type MISFETs, comprising the steps of: (a) preparing a semiconductor substrate having a main surface including a first region and a second region; (b) forming an insulating film over the main surface of the semiconductor substrate; (c) forming first openings and a second opening in the insulating film in the first and second regions respectively; (d) etching the main surface of the semiconductor substrate using the insulating film as a mask to form first trenches and a second trench in the semiconductor substrate; (e) etching side surfaces of the first and second openings of the insulating film to enlarge the first and second openings, thereby exposing the main surface of the semiconductor substrate at the periphery of the first and second trenches, (f) after the step (e), forming oxide films over surfaces inside and at peripheries of the first and second trenches of the semiconductor substrate, with the insulating film remaining over the main surface of the semiconductor substrate; (g) after the step (f), forming a conductive layer over the insulating film and the oxide film inside and at the periphery of the trench in the first and second regions; (h) patterning the conductive layer to form gate electrodes of the plurality of MISFETs and a gate wiring in the first and second regions respectively, with the insulating film remaining over the main surface of the semiconductor substrate, (i) after the step (h), removing a portion of the insulating film in the first region, (j) introducing first impurities into the semiconductor substrate to form channel-forming regions of the plurality of MISFETs in the first region; and (k) introducing second impurities into the semiconductor substrate to form source regions of the plurality of MISFETs over the channel-forming regions in the first region, wherein the gate electrodes and gate wiring are connected, wherein the source regions of the plurality MISFETs are electrically connected; the channel-forming regions of the plurality MISFETs are electrically connected; and the plurality of MISFETs comprise a power MOSFET.