Patent ID: 6081136
Filing Date: 2000-06-27
Classification: H03K

Abstract:
A NOR gate pair comprising:a first NOR gate having a plurality of inputs and an output;a second NOR gate having a plurality of inputs and an output;a first NAND gate having a first input, a second input, and an output, the first input being coupled to the output of the first NOR gate, the second input being coupled to the output of the second NOR gate through a first input inverter;a second NAND gate having a first input, a second input, and an output, the first input being coupled to the output of the second NOR gate, the second input being coupled to the output of the first NOR gate through a second input inverter;a first output inverter coupled to the output of the first NAND gate; anda second output inverter coupled to the output of the second NAND gate, wherein each of the plurality of inputs of the first NOR gate receives a respective signal and each of the plurality of inputs of the second NOR gate receives a respective signal, and wherein all but one of the signals received by the first NOR gate are among the signals received by the second NOR gate.