Patent ID: 6477593
Filing Date: 2002-11-05
Classification: G06F,H01R,H05K

Abstract:
A fault tolerant stacked 1/O bus bridge system, comprising:a motherboard comprising: a first bus; and a second bus; and an interconnected stack of daughterboards configured to couple to said first bus and said second bus of said motherboard and comprising: a first daughterboard configured to couple to said first bus and said second bus of said motherboard and comprising: a first connector that couples said first daughterboard to said first bus and said second bus of said motherboard regardless of the position of said first daughterboard in said interconnected stack of daughterboards: a first bus interface; and a first bus bridge configured to connect said first bus interface with only said first bus responsive to the order of said first daughterboard from said motherboard in said interconnected stack: and a second daughterboard configured to couple to said first bus and said second bus of said motherboard and comprising: a second connector that couples said second daughterboard to said first bus and said second bus of said motherboard regardless of the position of said second daughterboard in said interconnected stack of daughterboards; a second bus interface; and a second bus bridge configured to connect said second bus interface with only said second bus responsive to the order of said second daughterboard from said motherboard in said interconnected stack; whereby if said first bus bridge fails, said motherboard can be connected to said first bus interface by stacking said daughterboards in a different order.