Patent ID: 7324366
Filing Date: 2008-01-29
Classification: G11C

Abstract:
1. A nonvolatile memory array, comprising: a plurality of word lines; a plurality of bit lines; a plurality of source lines; and a plurality of nonvolatile memory cells, each of at least a subset of the plurality of memory cells having a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines, at least one of the memory cells comprising: a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a first line of a corresponding bit line/source line pair; and a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a second line of the corresponding bit line/source line pair, and the gate connecting to a corresponding one of the word lines; wherein for any subset of at least four memory cells connected to a same bit line, each of the four memory cells being adjacent to one another, at least two adjacent memory cells in the subset share a same word line and at least two adjacent memory cells in the subset share a same source line.