Patent ID: 8912995
Filing Date: 2014-12-16
Classification: G09G,G11C

Abstract:
1. A gate driver comprising a gate integrated circuit chip including a plurality of shift registers respectively and sequentially connected to a plurality of gate lines that are arranged in a direction, the gate integrated chip receiving at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, wherein timings of the at least two scanning start signals are independent of each other, timings of the at least two clock control signals based on the one scanning start signal are independent of each other, and the first shift register and another shift register after the second shift register among the plurality of shift registers commonly receives one of the at least two scanning start signals, and the second shift register and another shift register after the third shift register among the plurality of shift registers commonly receives another one of the at least two scanning start signals.