Patent ID: 7586802
Filing Date: 2009-09-08
Classification: G11C

Abstract:
1. A memory, comprising: a memory cell; a clamp transistor having a first end, a second end and a control end, the second end being coupled to the memory cell; a first inverter having an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor; a bit line electrically connected to the second end of the clamp transistor and the input end of the first inverter and having a bit-line voltage thereon; a pre-charge path electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon; and a detector and controller circuit electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a first low level and close the pre-charge path when the sensing voltage is at a first high level.