Patent ID: 6215351
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A fuse-latch circuit for a fuse, comprising:a first MOS transistor having a source-drain path, a gate and formed of a first conductivity type;a second MOS transistor having a source-drain path, a gate and formed of a said first conductivity type, and the fuse provided in series between said source-drain path of said first MOS transistor and said source-drain path of said second MOS transistor;a third MOS transistor having a source-drain path, a gate and formed of a second conductivity type;a latch element connected to said source-drain path of said second MOS transistor and to a node between said source-drain path of said first MOS transistor and said source-drain path of said third MOS transistor, said gate of said third MOS transistor being connected to said gate of said second MOS transistor and receiving only one first global initialization control signal; anda delay element connected to said gate said first MOS transistor, said delay element receiving the first global initialization control signal and generating a second local control signal being staggered over time with respect to the first global initialization control signal, the second local control signal being supplied to said gate of said first MOS transistor, and the first global initialization control signal and the second local control signal used for reading information corresponding to a state of the fuse and said information stored in said latch element.