Patent ID: 6880143
Filing Date: 2005-04-12
Classification: G06F

Abstract:
1. A method for processing an integrated circuit (IC) design indicating positions of cells of an IC within rows occupying a horizontal plane and extending in a horizontal first direction, and indicating positions of conductors residing above the horizontal plane and extending in a horizontal second direction transverse to the first direction, wherein a plurality of the cells include I/O terminals, wherein each cell of the plurality of cells occupies a plurality of contiguous via spaces in the first direction, each via space being of dimension in the first direction sufficient to contain a via extending upward from any of the I/O terminals, and wherein each I/O terminal of the plurality of cells occupies at least one via space in the first direction, the method comprising the steps of: a. choosing one of the plurality of cells as a selected cell; b. processing the design to generate a separate first data word corresponding to each I/O terminal of the selected cell, wherein each bit of the first data word corresponds to a separate one of the via spaces occupied by the selected cell and indicates whether that via space is also occupied by the I/O terminal corresponding to that first data word; c. processing the design to generate a second data word, wherein each bit of the second data word corresponds to a separate one of the via spaces occupied by the selected cell in the first direction and indicates whether that via space is also occupied by any one of the conductors; and d. for each first data word generated at step b, generating a third data word having bits of states that are logical function of states of bits of that first data word and of bits of the second data word, wherein the states of the bits the third data word indicate whether the conductors occupy all via spaces also occupied by the I/O terminal corresponding to that first data word.