Patent ID: 6801422
Filing Date: 2004-10-05
Classification: H01G,H01L,H05K,Y10T

Abstract:
A capacitor comprising:at least four conductive layers embedded in a dielectric, wherein the at least four conductive layers includes a first plurality of conductive layers interlaced with a second plurality of conductive layers; and a plurality of vias coupling the at least four conductive layers to a plurality of connection sites on at least two surfaces of the capacitor, wherein the plurality of vias includes a first set of vias and a second set of vias, and the first set of vias couples the first plurality of conductive layers to a first plurality of connection sites on the at least two surfaces of the capacitor, and the first set of vias extends through openings in and is electrically isolated from the second plurality of conductive layers, and the second set of vias couples the second plurality of conductive layers to a second plurality of connection sites on the at least two surfaces, and the second set of vias extends through openings in and is electrically isolated from the first plurality of conductive layers, and wherein the plurality of vias are plated through holes.