Patent ID: 8258860
Filing Date: 2012-09-04
Classification: G11C

Abstract:
1. A circuit comprising: a digital CMOS circuit having NMOS field-effect transistors and having PMOS field-effect transistors: a first load device, wherein source terminals of the NMOS field-effect transistors of the digital CMOS circuit are connectable via the first load device to a first supply voltage: a second load device, wherein source terminals of the PMOS field-effect transistors of the digital CMOS circuit are connectable via the second load device to a second supply voltage; and an evaluation circuit configured to evaluate a first source voltage at the source terminals of the NMOS field-effect transistors, the evaluation circuit being connectable to the source terminals of the NMOS field-effect transistors, the evaluation circuit configured to evaluate a second source voltage at the source terminals of the PMOS field-effect transistors, the evaluation circuit being connectable to source terminals of the PMOS field-effect transistors; wherein the evaluation circuit is configured to adjust a first voltage drop across the first load device and is connectable to a first control input of the first load device; wherein the evaluation circuit is configured to adjust a second voltage drop across the second load device and is connectable to a second control input of the second load device; and wherein one or more of the following is true: