Patent ID: 6557132
Filing Date: 2003-04-29
Classification: G01R

Abstract:
A method for determining common failure modes of an integrated circuit device under test, the method comprising:applying a test pattern to a series of inputs of the device under test; comparing a set of output data generated by the device under test to a set of expected output data, said set of output data generated by the device under test in response to said test pattern; determining whether said set of output data generated by the device under test has passed the test, said set of output data passing the test if said set of output data matches said set of expected data being pass data if said output data does not match said set of expected data being fail data; and if said set of output data has not passed the test, then: determining whether an output signature corresponding to said set of output data matches a previously stored output signature; and storing fail data corresponding to said output signature if said output signature matches a previously stored output signature.