Patent ID: 6224667
Filing Date: 2001-05-01
Classification: B82Y,H01L,H01S

Abstract:
A method for fabricating a semiconductor photonic integrated circuit, comprising the steps of:(a) providing a growth preventing mask on a semiconductor substrate, said growth preventing mask being shaped with a first portion of a first width and a second portion of a second width wider than said first width, said first and second portions having a non-masked stripe aperture extending through said second portion and part of said first portion;(b) selectively growing a light waveguide layer on said non-masked stripe aperture of said semiconductor substrate by an epitaxial growth technique using a first growth pressure which is below a minimum growth pressure required to cause d/d.sub.o to increase as the mask width is increased, where d is the thickness of a selectively grown layer in said non-masked stripe aperture, and d.sub.o is the thickness of said selectively grown layer outside of said mask;(c) increasing a growth pressure to a second growth pressure above said minimum growth pressure;(d) selectively growing a multiple quantum well structure layer on said light waveguide layer by an epitaxial growth technique using the second growth pressure;(e) decreasing said growth pressure to a pressure below said minimum growth pressure; and(f) selectively growing a clad layer on said multiple quantum well structure layer by the epitaxial growth technique using said first growth pressure below said minimum growth pressure,wherein said steps a) to f) are successively carried out in a depressurized MOVPE (Metalorganic Vapor Phase Epitaxy) apparatus.