Patent ID: 9035397
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A method for manufacturing a gate structure, the method comprising: providing a first stack on a semiconductor substrate, the first stack including a dummy layer, a first TiN layer disposed between the dummy layer and the semiconductor substrate, a TaN layer disposed between the first TiN layer and the semiconductor substrate, a second TiN layer disposed between the TaN layer and the semiconductor substrate, a first dielectric layer disposed between the second TiN layer and the semiconductor substrate, and an interfacial layer disposed between the first dielectric layer and the semiconductor substrate, wherein a dielectric constant of the first dielectric layer is greater than a dielectric constant of a silicon oxide material; etching the first stack to result in a remaining stack that includes a remaining dummy layer, a first remaining TiN layer disposed between the remaining dummy layer and the semiconductor substrate, a remaining TaN layer disposed between the first remaining TiN layer and the semiconductor substrate, a second remaining TiN layer disposed between the remaining TaN layer and the semiconductor substrate, a first remaining dielectric layer disposed between the second remaining TiN layer and the semiconductor substrate, and a remaining interfacial layer disposed between the first remaining dielectric layer and the semiconductor substrate; providing a contact etching stop layer on the remaining stack and the semiconductor substrate, wherein the remaining stack is disposed between the semiconductor substrate and a first portion of the contact etching stop layer; providing a second dielectric layer on the contact etching stop layer, wherein each of a second portion of the contact etching stop layer and a third portion of the contact etching stop layer is disposed between the semiconductor substrate and the second dielectric layer; after the providing the second dielectric layer, performing planarization according to the remaining dummy layer; after the planarization, removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer with the remaining TaN layer being disposed between the second remaining TiN layer and the metal gate layer.