Patent ID: 7619298
Filing Date: 2009-11-17
Classification: H01L

Abstract:
1. A device, comprising: a blocked portion; wherein formation of a P-well is prevented in the blocked portion of a substrate of an integrated circuit; a P-well formed around the blocked portion; and wherein a resistivity of the blocked portion of the substrate is higher than a resistivity of the P-well; wherein the resistivity of the blocked portion of the substrate is equal to a resistivity of the substrate; an electronic device formed above the blocked portion, wherein the blocked portion includes a series resistance to substrate ground to reduce parasitic capacitance of the electronic device; wherein the electronic device is a signal coupling capacitor, and the blocked portion includes a portion extending beyond a periphery of the signal coupling capacitor and a dimension of the portion is selected to provide a predetermined series resistance between a ground terminal at the substrate and the parasitic capacitance of the signal coupling capacitor.