Patent ID: 6673695
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A method of creating regions of Shallow Trench Isolation (STI) in the surface of a substrate, comprising the steps of:providing a substrate, the substrate is provided with an objective of creating semiconductor devices over the surface thereof; creating a layer of pad oxide over the surface of said substrate; depositing a layer of etch stop material over the surface of said layer of pad oxide; patterning and etching said layer of etch stop material and said layer of pad oxide using a first exposure mask, creating at least one opening through said layers of etch stop material and said layer of pad oxide, said at least one opening being aligned with at least one surface area over the surface of said substrate where at least one region of Shallow Trench Isolation is to be created; creating at least one STI trench in the surface of said substrate in accordance with said at least one opening created through said layers of etch stop material and said layer of pad oxide; blanket depositing a layer of STI dielectric over the surface of said patterned and etched layer of etch stop material, filling said at least one opening created through said layers of etch stop material and said layer of pad oxide, further filling said at least one STI trench created in the surface of said substrate; creating an impurity ion implantation blocking mask over the surface of said layer of STI dielectric using a second exposure mask, said second exposure mask being a reverse mask of said first exposure mask, blocking the surface of said layer of STI dielectric where said layer of STI dielectric overlies said at least one STI trench created in the surface of said substrate; performing an impurity ion implantation into the exposed surface of said layer of STI dielectric in accordance with said ion implantation blocking mask, creating at least two first layers of doped STI dielectric overlying said patterned and etched layer of etch stop material, said at least two first layers of doped STI dielectric surrounding at least one second layer of undoped STI dielectric overlying said at least one STI trench created in the surface of said substrate, increasing an etch rate of said at least two first layers of doped STI dielectric by a measurable amount; removing said impurity ion implantation blocking mask from the surface of said layer of STI dielectric; etching said at least two first doped and said at least one second undoped layers of STI dielectric to where said layer of STI dielectric overlies the surface of said patterned and etched layer of etch stop material to a measurable height; and removing said layer of STI dielectric from the surface of said patterned and etched layer of etch stop material.