Patent ID: 8796783
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A semiconductor structure comprising: at least one gate structure located on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric; a second etch stop layer located on said at least one gate structure; a first contact-level dielectric layer and a second contact-level dielectric layer located over said second etch stop layer; at least one gate contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one gate contact via structure extends through said first and second contact-level dielectric layers, said second etch stop layer, one of said at least one gate cap dielectric, and one of said at least one first etch stop layer; and at least one source/drain contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one source/drain contact via structure extends through said first and second contact-level dielectric layers and said second etch stop layer.