Patent ID: 7751402
Filing Date: 2010-07-06
Classification: H04L

Abstract:
1. A system comprising: a first port to receive a network packet; a second port in communication with the first port, the second port to transmit the network packet after processing; a first circuitry to associate first control information with a first portion of the network packet and to associate second control information with a second portion of the network packet; a second circuitry to process the first portion of the network packet and to process the second portion of the network packet at least partially in parallel with processing the first portion of the network packet; and a third circuitry to enqueue the first portion and the second portion for transmission to the second port in the same order in which the first portion and the second portion were received at the first port, comprising: one or more peripheral buses; a memory system; and a processor coupled to the one or more peripheral buses and the memory system, the processor adapted to forward data from the first port to the second port and comprising one or more microengines to execute program threads, the threads including receive schedule program threads to assign the first portion of the network packet from the first port to a first receive processing program thread and the second portion of the network packet to a second receive processing program thread.