Patent ID: 6900539
Filing Date: 2005-05-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: a lower interconnect layer formed of copper or copper alloy; an interlayer insulation film covering said lower interconnect layer; a via hole formed in said interlayer insulation film to expose a part of said lower interconnect layer; a copper via formed by forming copper or copper alloy within said via hole and connected to said lower interconnect layer; a first barrier film and a second barrier film, both being formed on a side surface of said copper via and laminated relatively to each other, said second barrier film being formed on a bottom surface of said copper via and said first barrier film not being formed on said bottom surface, wherein said first barrier film is on a side of said interlayer insulation film and adherence between said first barrier film and said interlayer insulation film is stronger than adherence between said first barrier film and said copper via, and said second barrier film is on a side of said copper via and adherence between said second barrier film and said copper via is stronger than adherence between said second barrier film and said interlayer insulation film, an upper interconnect trench formed in said interlayer insulation film on said copper via; and an upper interconnect layer made of copper formed within said upper interconnect trench, wherein said upper interconnect layer and said lower interconnect layer are connected together through said copper via, and wherein both said first and second barrier films are laminated on sides and a bottom of said upper interconnect layer other than where said upper interconnect layer contacts said copper via, wherein an aspect ratio of said via hole ranges from 1.5 to 5.