Patent ID: 6107146
Filing Date: 2000-08-22
Classification: H01L

Abstract:
In a CMOS semiconductor fabrication process, a method of utilizing a non-epitaxial starting material without degrading latchup immunity, said method comprising:non-selectively introducing a bulk impurity distribution into said starting material, said starting material comprised of a substantially uniformly doped wafer with a sheet resistivity in the range of approximately 5 to 25 .OMEGA.-cm, wherein an upper boundary of said bulk impurity distribution is displaced below an upper surface of said wafer by a first depth and wherein a peak impurity concentration of said bulk impurity distribution is greater than approximately 1.times.10.sup.19 atoms/cm.sup.3 ; andintroducing a nitrogen bearing barrier impurity distribution into said wafer, wherein a peak concentration of said barrier impurity distribution is displaced below said upper surface of said wafer by a second depth, and wherein said first depth is greater than said second depth and wherein said barrier impurity distribution substantially prevents said bulk impurity distribution from migrating into an upper region of said wafer, whereby said wafer comprises a lightly doped upper region over a heavily doped bulk layer, wherein said bulk layer improves a latchup immunity of said CMOS process by providing a conductive path below said upper region.