Patent ID: 6311315
Filing Date: 2001-10-30
Classification: G06F,H01L

Abstract:
A design method for a semiconductor integrated circuit having components formed in a semiconductor substrate, a plurality of interlayer dielectric films and a plurality of interconnection layers alternately formed over said semiconductor substrate, and plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film wherein said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component, said semiconductor integrated circuit design method comprising:(a) a first step including:selecting, as a parameter which affects electromigration resistance at the interface between an interconnection line and a plugging member, a specific parameter including at least one of an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line capacity, an interconnection line thickness, and an overlap margin;dividing, according to a working condition relative to said specific parameter, the permissive current amount of a plugging member into a plurality of zones; andperforming the setting of a representative value common in each of said zones; and(b) a second step including:determining the representative value of one of said zones to the value of said specific parameter as the permissible current amount of said plugging member; anddetermining the total opening area of each said connecting window or the plane form of each said interconnection line according to said permissible current amount.