Patent ID: 8051390
Filing Date: 2011-11-01
Classification: G06F,Y02P

Abstract:
1. A method of designing a standard cell, said method implemented on a computer, said standard cell comprising a circuit formed of a plurality of layers on a substrate, wherein manufacture of said standard cell comprises use of a plurality of patterned masks each mask creating a separate one of said layers, wherein said method comprises the steps of: generating an initial representation of at least one of said masks, wherein said representation comprises a plurality of strips and said strips are arranged in a substantially uniform pattern; analyzing said initial representation; identifying a non-uniformity in a boundary condition of said initial representation of said standard cell affecting a characteristic of a neighbouring standard cell, said characteristic comprising at least one of electrical performance or cell yield, said non-uniformity comprising a break in said uniform pattern adjacent a boundary of said standard cell; and amending said initial representation by introducing a further non-uniformity into said uniform pattern to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell.