Patent ID: 6733933
Filing Date: 2004-05-11
Classification: G03F,Y10S

Abstract:
A semiconductor integrated circuit device fabrication method, comprising the steps of:(i) irradiating a mask, having an enlarged circuit pattern over a transparent mask substrate, with an exposure light flux, said exposure light flux being at least partially coherent in an ultraviolet domain; and (ii) reducing and projecting the exposure light flux passing through the mask, by an optical reducing projection exposure system, so that a reduced circuit pattern corresponding to the enlarged circuit pattern can be focused onto a photosensitive resist film overlying a major surface of a wafer, whereby the reduced circuit pattern corresponding to the enlarged circuit pattern is transferred onto the wafer, said mask comprising: (a) a phase shifting film covering region, over the transparent mask substrate; (b) an opening region, in the phase shifting film covering region, there being no phase shifting film in the opening region; and (c) a shifter edge region of the phase shifting film covering region, which shifter edge region borders on and is adjacent to the opening region, the shifter edge region having a phase shifting film over the transparent mask substrate, wherein a phase of the transmitted exposure light flux transmitted through the shifter edge region is inverted with respect to that of the transmitted exposure light flux transmitted through the opening region, due to only said transmission through said phase shifting film, and whereby resolution is improved due to destructive interference between exposure light fluxes transmitted through the opening region and the shifter edge region.