Patent ID: 6906554
Filing Date: 2005-06-14
Classification: G06F,Y02D

Abstract:
1. A pipeline-based circuit comprising: a plurality of processing units cascaded to establish at least a pipeline, each processing unit comprising: a logic unit for performing a predetermined logic operation; a first buffer unit electrically connected to the logic unit for piping an output data of the logic unit to a logic unit of a next processing unit according to a clock signal, the clock signal cyclically transitioning between a first logic value and a second logic value; a clock-gating unit electrically connected to the first buffer unit for determining if the clock signal inputted into the first buffer unit is gated according to a control value for making the clock signal correspond to the first logic value when the processing unit starts working; and a second buffer unit electrically connected to the clock-gating unit for storing the control value; a pipeline control unit for generating at least a control signal to each processing unit for controlling if an output data associated with a processing unit is piped to a next processing unit; and a control value generator for setting the control value of each processing unit according to a plurality of control signals outputted from the pipeline control unit.