Patent ID: 6260056
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A squaring circuit comprising:an input terminal configured to carry a k-bit input bit group representing a k-bit input value, the input bit group having a left hand m-bit portion and a right hand (k-m)-bit portion representing respective left and right hand values;a left hand squaring circuit configured to receive the left hand m-bit portion and generate a first term bit group representing a square of the left hand value;a multiplier configured to multiply the left hand m-bit portion and the right hand (k-m)-bit portion and generate a second term bit group representing a product of the left and right hand values;a right hand squaring circuit configured to receive the right hand (k-m)-bit portion and generate a third term bit group representing a square of the right hand value; andan adder configured to add the second term bit group, left shifted by k-m+1 bit positions, to a concatenation of the first and third term bit groups.