Patent ID: 6204517
Filing Date: 2001-03-20
Classification: B82Y,H01L,Y10S

Abstract:
A single-electron-transistor memory array, comprising:a silicon substrate;a buried oxide layer in a thickness about 0.3.about.0.5 micrometers formed in said silicon substrate, wherein said silicon substrate has a thickness over said buried oxide layer;a plurality of silicon wires arranged on said buried oxide layer, each of said silicon wires having a pair of ends and said silicon wires being separated from each other, wherein the silicon wires are formed in accordance with a process comprising:thermal oxidizing said silicon substrate to reduce the thickness of said silicon substrate on said buried oxide layer;removing said thermal oxide layer; andpatterning said silicon substrate on said buried oxide layer;an oxynitride layer having a thickness about 10.about.100 angstroms formed on the surface of said silicon wires for isolation; anda polysilicon layer partially covering said oxynitride layers for perpendicularly bridging across said buried oxide layer and connecting to a gate electrode.