Patent ID: 7428161
Filing Date: 2008-09-23
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cell arrays in which memory cells are arranged in a matrix; word lines which are commonly connected to gates of the memory cells in a same row in the memory cell arrays; bit lines which are commonly connected to drains of the memory cells in a same column in the memory cell arrays, the bit lines representing addresses of the memory cells; column gates each of which is provided on a memory cell array basis, the column gates selecting the bit lines in the memory cell arrays; sense amplifiers each of which is provided on a memory cell array basis, the sense amplifiers amplifying data read out from the memory cells selected by the column gates; and an error correcting circuit which performs error correction of the read-out data, the memory cell arrays including: first regions including first element isolating regions which have stripe shapes along the bit lines and which are cyclically repeated in a semiconductor substrate, and the memory cells being formed on an element region between the adjacent element isolating regions, the first regions being arranged in plurality along the word line direction; and a second region provided adjacent to the first region in a direction along the word lines, the second region including a second element isolating region whose width along the word line direction is greater than that of the first element isolating region, connections of the bit lines to the memory cells adjacent to the second region being different from one another among the memory cell arrays.