Patent ID: 7447879
Filing Date: 2008-11-04
Classification: G06F

Abstract:
1. A method of scheduling execution of an instruction in a processor, comprising: receiving an issue group of instructions in a cascaded delayed execution pipeline unit having two or more execution pipelines that begin execution of instructions in a common issue group in a delayed manner relative to each other; determining whether the issue group includes a load instruction; upon determining that the issue group includes a load instruction, scheduling the load instruction to be executed in a first pipeline of the two or more execution pipelines, and scheduling each remaining instruction in the issue group to be executed in remaining pipelines of the two or more pipelines, wherein execution of the load instruction in the first pipeline begins prior to beginning execution of the remaining instructions in the remaining pipelines; issuing the issue group to the cascaded delayed execution pipeline; determining whether the load instruction results in a cache miss; and upon determining that the load instruction results in a cache miss in a level one cache: