Patent ID: 8122402
Filing Date: 2012-02-21
Classification: G06F

Abstract:
1. An equivalence checking method of a model to be verified using a sample model a circuit of which has been described in a predetermined language and a sample model test vector generation model for the sample model, as processes to be executed by a computer, respectively, the method comprising: a first process in which the sample model inputs/outputs a signal from/to the sample model test vector generation model with cycle accuracy; a second process for controlling writing an output from the sample model test vector generation model into an input FIFO group for each signal of the sample model with a timing same as that of the sample model; a third process for reading data from the input FIFO group with the same operation timing as that of the model to be verified and outputting the data to the model to be verified; a fourth process for writing an output of the sample model and an output of the model to be verified into an output FIFO pair group for each corresponding signal name; and a fifth process for carrying out coincidence judgment for a pair output for each signal name of the output FIFO pair group.