Patent ID: 9147440
Filing Date: 2015-09-29
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of functional bit lines including an outermost bit line; at least one dummy bit line adjacent the outermost bit line of the functional bit lines; a dummy bit line selection unit that activates the at least one dummy bit line in response to a selection control signal of one of the functional bit lines that is not adjacent the at least one dummy bit line; a cell block including a word line strapping region at a center area thereof, the cell block being divided into right and left regions about the word line strapping region, wherein the plurality of functional bit lines comprise first functional bit lines aligned at a predetermined space in the right region, a number of the first functional bit lines being even, and second functional bit lines aligned at a predetermined space in the left region, a number of the second functional bit lines being even; an odd functional hit line selection unit disposed above the cell block and configured to select odd functional bit lines aligned in the right and left regions in response to a first corresponding selection control signal; and an even functional bit line selection unit disposed under the cell block and configured to select even functional bit lines aligned in the right and left regions in response to a second corresponding selection control signal.