Patent ID: 9201753
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. An integrated circuit, comprising: a processor, a host bus, multiple branch buses, multiple status detectors, a top layer monitor, and an interface; wherein the multiple branch buses are coupled to the processor through the host bus; the host bus is configured to transmit data from the multiple branch buses to the processor; the processor is configured to perform data processing; each status detector in the multiple status detectors is coupled to a respective, corresponding branch bus in the multiple branch buses, and is configured to read status data on the corresponding branch bus that is coupled to the status detector, and upload the status data to the top layer monitor; and the top layer monitor is configured to collect the status data from each status detector, and output the status data through the interface, wherein the status data collected by each status detector reflects a status condition of the corresponding branch bus, the status condition corresponding to a volume of data that the corresponding branch bus bears.