Patent ID: 6405286
Filing Date: 2002-06-11
Classification: G06F

Abstract:
A method of assigning bank bits to memory interleaving schemes in a computer system that supports multi-cache line interleaving and DRAM page interleaving, wherein the computer system includes a memory organization having a plurality memory busses, wherein two or more memory busses can each perform independent memory transactions simultaneously, with each memory bus coupled to one or more memory bus segments, wherein only a single memory transaction can be active on a single memory bus segment at any given time, and each memory bus segment is coupled to one or more memory banks, the method comprising:assigning one or more bank bits that differentiate between memory banks coupled to different memory busses to multi-cache line interleaving; and assigning one or more bank bits that differentiate between memory banks coupled to a common memory bus segment to DRAM page interleaving.