Patent ID: 9135965
Filing Date: 2015-09-15
Classification: G06F,G11C

Abstract:
1. A memory system comprising: an address bus; a memory comprising: a memory controller coupled to the address bus, wherein the memory controller is configured to provide an address for an activate operation to the first portion and the third portion over the address bus and initiate the activate operation for the address in both the first portion and the third portion simultaneously, wherein the activate operation reads a page of data corresponding to the address from each of the first portion and the third portion and stores the data in local data store latches for subsequent read and write operations, the memory controller coupled to the volatile memory banks and the at least one non-volatile memory bank and configured to queue memory access commands and issue volatile memory access commands to the first portion after completion of the activate operation in the first portion and before completion of the activate operation in the third portion.