Patent ID: 6353520
Filing Date: 2002-03-05
Classification: H01L

Abstract:
An integrated circuit, comprising:a semiconductor substrate connected to a bond pad for a reference supply voltage; a first bus for a first supply voltage, and a second bus for a second supply voltage, wherein the second supply voltage is higher than the first supply voltage; internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness suitable for the first supply voltage but not for the second supply voltage; a plurality of signal bond pads for connecting to a respective plurality of external signals, wherein the plurality of external signals are operable at approximately the second supply voltage, with local ESD protection circuitry having a respective diode connected between each of the plurality of signal bond pads and the second bus; and shared ESD circuitry connected between the second bus and the semiconductor substrate, wherein the shared ESD circuitry comprises: at least one parasitic bipolar transistor with an emitter connected to the second bus and a collector connected to the semiconductor substrate with a base connected to a control circuit, wherein the control circuit comprises a plurality of MOS transistors each having gate oxide only of the first thickness such that the control circuit is operable to turn on the parasitic bipolar transistor in response to an ESD zap applied to any of the plurality of signal bond pads; and wherein the control circuit further comprises an R/C timing circuit responsive to the ESD zap connected to the plurality of MOS transistors, operable to turn off the parasitic transistor after a selected period of time, whereby the energy of the ESD zap is expended.