Patent ID: 8557646
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A method for fabricating a vertical transistor, comprising the steps of: Step S1: defining at least one trench region and at least one insulation region in a substrate, and forming a first trench in each trench region; Step S2: sequentially epitaxially growing a first polarity layer and a channel layer inside each first trench, and forming a first retard layer on the channel layer; Step S3: etching the insulation region with the first retard layer being a mask until a top of the insulation region is lower than a top of the first polarity layer by an etch depth so as to form a connection portion connected with the first polarity layer, and defining a combination of the connection portion, the first polarity layer, the channel layer and the first retard layer which stack together as an integration layer, wherein the integration layer has two opposite side faces; Step S4: forming a first insulation layer on each side face; Step S5: forming a plurality of second trenches in the integration layers to form at least one pillar each having a first sidewall and a second sidewall, wherein the integration layer is etched until the channel layer is completely removed with the first polarity layer being preserved to form the second trenches, and wherein a lengthwise direction of the second trenches is vertical to that of the first trenches; Step S6: respectively forming a gate on the first sidewall and the second sidewall; Step S7: removing the first retard layer on the pillar; and Step S8: epitaxially growing a second polarity layer on the pillar.