Patent ID: 9141753
Filing Date: 2015-09-22
Classification: G06F,Y02E,Y04S

Abstract:
1. A method comprising: initially placing a plurality of operational cells of a semiconductor device within a semiconductor physical layout; determining timing data for each of the plurality of operational cells; determining, by a computer, switching activity from a logic description or design constraints for each of the plurality of operational cells; determining power grid switch locations relative to each of the plurality of operational cells; deriving a cost function based upon the determined timing data, switching activity and power grid switch locations; initially, by the computer, placing the plurality of operational cells at positions which are dependent on the derived cost function; determining an estimated power loss (IR drop) value for each of the plurality of operational cells when the semiconductor device will be in use, wherein the estimated IR drop is based on a number of the plurality of operational cells that switch simultaneously; identifying operational cells having an estimated IR drop value above a predetermined threshold; and re-placing identified operational cells within the semiconductor layout to reduce IR drop.