Patent ID: 6046473
Filing Date: 2000-04-04
Classification: H01L

Abstract:
A solid-state power device, comprising:a substrate which includes substantially monolithic semiconductor material having a first conductivity type at a first surface thereof;a source diffusion, in proximity to said first surface, which is shallow and heavily doped with said first conductivity type;a body diffusion, in proximity to said first surface, which is deeper than said source diffusion and doped with a second conductivity type;a deep-body diffusion, in proximity to said first surface, which is doped with said second conductivity type and has a depth which is more than the depth of said source diffusion, said source diffusion being surrounded by the combination of said body and deep-body diffusions;an insulated conductive gate which is capacitively coupled to a portion of said body diffusion, at said first surface, to define a channel region therein, said channel region being located in lateral proximity to a drain conduction region which extends downward to connect to a drain contact diffusion which is heavily doped with said first conductivity type;an additional concentration of dopants of said first conductivity type at said first surface, overlying said source and channel regions and at least part of the surface of said drain conduction region to provide reduced resistance to lateral current flow between said channel region and said drain conduction region;an oxide, encroaching into said first surface over said drain conduction region, which is thicker than the insulation over said channel region; and a further additional concentration of dopants of said first conductivity type, underlying and self-aligned to said oxide, the further additional concentration of dopants shallower than said deep-body diffusion and providing additional reduced resistance to current flow in said drain conduction region.