Patent ID: 8397033
Filing Date: 2013-03-12
Classification: G06F

Abstract:
1. A parallel processing processor system that includes multiple processors and performs parallel processing on data read out from a main memory using the multiple processors, the system comprising: multiple processor elements, each processor element including a processor and an instruction cache that holds an instruction corresponding to at least part of a program executed by the processor; a shared memory, whose latency with the processors is less than the latency between the main memory and the processors, that stores the program transferred from the main memory and is shared by the multiple processor elements; an update unit that updates the instruction in the instruction cache with an instruction in the program stored in the shared memory in the case where a cache miss has occurred in the instruction cache; a transfer control unit that controls transfers between the main memory and the shared memory; and a synchronization control unit that, in the case where the entirety of the program cannot be stored in the shared memory, requests the transfer control unit to rewrite the program in the shared memory in response to a synchronizing signal outputted by the processor.