Patent ID: 6995415
Filing Date: 2006-02-07
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a recess formed in the semiconductor substrate; a memory cell transistor including a gate electrode and a gate dielectric provided on the semiconductor substrate and source and drain diffusion layers provided at either side of the gate electrode in the semiconductor substrate; a capacitor including a plate electrode formed of a conductor film in common with the gate electrode of the memory cell transistor so as to lie over the top surface of the semiconductor substrate and at least a part of the surface of the recess, and a capacitance dielectric provided below the plate electrode; and logic transistors each including a gate electrode and a gate dielectric provided on the semiconductor substrate and source and drain diffusion layers formed in the semiconductor substrate, wherein the plate electrode of the capacitor, the gate electrode of the memory cell transistor and the gate electrodes of the transistors located in the logic circuit are all formed of a common conductor film.