Patent ID: 7816268
Filing Date: 2010-10-19
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device comprising: (A) a step of forming a first copper alloy wiring containing a predetermined additive element in a main component Cu, the first copper alloy wiring formed in a first interlayer insulation film; (B) a step of forming a second interlayer insulation film over the first interlayer insulation film; (C) a step of forming a trench and a via hole in the second interlayer insulation film, a bottom of the trench connecting with a top of the via hole, and a bottom of the via hole exposing a top surface of the first copper alloy wiring; (D) a step of forming a first barrier metal which includes nitrogen, and is arranged along a side wall of the trench, a bottom surface of the trench, a side wall of the via hole and the bottom of the via hole; (E) a step of removing the first barrier metal on the bottom of the via hole and a part of the first copper alloy wiring below the bottom of the via hole by physically etching; (F) a step of forming a second barrier metal arranged along the side wall of the trench, the bottom surface of the trench, the side wall of the via hole, and the bottom of the via hole, after the step (E); and (G) a step of forming a second copper alloy wiring which contains the predetermined additive element in a main component Cu, and fills in the trench and the via hole, after the step (F), wherein a first concentration of nitrogen of the first barrier metal is more than a second concentration of nitrogen of the second barrier metal.