Patent ID: 9196613
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, the method comprising: forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate; forming a gate structure covering a first portion of the first plurality of fins and a first portion of the second plurality of fins, the gate structure not covering a second portion of the first plurality of fins and a second portion of the second plurality of fins; growing a first epitaxial layer surrounding the second portion of the first plurality of fins after forming the gate structure, wherein the first epitaxial layer is unmerged; growing a second epitaxial layer surrounding the second portion of the second plurality of fins after forming the gate structure, wherein the second epitaxial layer is merged and completely fills a space between one fin in the second region and an adjacent fin in the second region; depositing an interlayer dielectric (ILD) layer above the semiconductor substrate; etching the ILD layer to remove the ILD layer in the second portion of the first region, thereby forming a first contact hole, and the ILD layer in the second portion of the second region, thereby forming a second contact hole, wherein the first contact hole is not in contact with the first epitaxial layer, and wherein the second contact hole is in direct physical contact with a top portion of the second epitaxial layer; and depositing a metal layer, wherein the metal layer is disposed around the first epitaxial layer and above the top portion of the second epitaxial layer.