Patent ID: 8354313
Filing Date: 2013-01-15
Classification: H01L

Abstract:
1. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising: providing a semiconductor substrate comprising a first device region and a second device region; forming a first gate stack in the first device region and a second gate stack in the second device region, wherein each of the first gate stack and the second gate stack includes a gate dielectric that is present on the semiconductor substrate, an n-type work function metal layer that is present on the gate dielectric, and a semiconductor-containing material that is present on the n-type work function metal layer; forming source regions and drain regions of an n-type dopant in the first device region adjacent to the first gate stack, and source and drain regions of a p-type dopant in the second device region adjacent to the second stack; forming at least one dielectric layer atop the first device region and the second device region, wherein the at least one dielectric layer has an upper surface that is coplanar with an upper surface of the first gate stack and the second gate stack; removing the semiconductor-containing material and the n-type work function metal layer from the second gate stack to expose the gate dielectric in the second device region, wherein the semiconductor-containing material and the n-type work function metal layer remain in the first gate stack that is present in the first device region; and forming a p-type work function metal layer on the gate dielectric that is present in the second device region, wherein the first gate stack comprising the n-type work function metal layer and the gate dielectric is the gate structure to an n-type semiconductor device, and the second gate stack comprising the p-type work function metal layer and the gate dielectric is the gate structure to a p-type semiconductor device.