Patent ID: 6187675
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with said gate having low resistivity, said MOSFET having a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and said MOSFET initially having a gate comprised of a first metal silicide on polysilicon disposed on a gate dielectric over said channel region, the method including steps of:A. depositing a first dielectric layer over said drain region, said source region, and said gate;B. etching away a portion of said first dielectric layer by patterning a photoresist layer deposited on said first dielectric layer to form additional peaks in said first dielectric layer from said etching away of said portion of said first dielectric layer near said gate, and then polishing down said first dielectric layer over said drain region and said source region, and polishing down said first dielectric layer over said gate until one of said first metal silicide on said polysilicon and said polysilicon of said gate is exposed;C. depositing a metal on said first metal silicide if said first metal silicide is exposed in said step B, and depositing said metal on said polysilicon if said polysilicon is exposed in said step B;D. performing a silicidation anneal to react said metal with said polysilicon to form a predetermined thickness of a second metal silicide over a remaining portion of said polysilicon, said predetermined thickness of said second metal silicide being greater than a thickness of said first metal silicide; andE. removing any portion of said metal that is not reacted during said silicidation anneal of said step D.