Patent ID: 6611063
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor chip having a plurality of chip electrodes thereon; a metallic interconnect pattern having a top surface connected to said plural chip electrodes and supporting said semiconductor chip, at least a top portion of said metallic interconnect pattern being formed by an electrolytic plating technique; an insulating film covering a bottom surface of said metallic interconnect pattern and having through-holes therein; a plurality of external terminals formed on said bottom surface of said interconnect pattern in said through-holes; a mold resin encapsulating said semiconductor chip on said top surface of said metallic interconnect pattern and said insulating film; another semiconductor chip mounted on said bottom surface of said metallic interconnect pattern; and another mold resin encapsulating said another semiconductor chip on said bottom surface of said metallic interconnect pattern.