Patent ID: 6411378
Filing Date: 2002-06-25
Classification: G01N

Abstract:
An on-wafer method for calibrating the sensitivity of a patterned wafer defect inspection tool during set-up which is used to detect defects on the surface of a semiconductor wafer during the stages of a fabrication process, said method comprising the steps of:providing a semiconductor wafer which is to be inspected for defects; introducing a calibration structure having a plurality of intentionally-introduced defects each being of a progressively smaller size dimension on a selected area of the semiconductor wafer which is to be inspected for defects prior to the inspection; loading the semiconductor wafer with the calibration structure in to the defect inspection tool; aligning the semiconductor wafer with respect to the defect inspection tool; determining areas o f the semiconductor wafer to be inspected; adjusting the sensitivity of the defect inspection tool to a desired scanning sensitivity setting; and calibrating the sensitivity of the defect inspection tool by scanning the semiconductor wafer with the calibration structure in order to determine the defect size from one of the plurality of intentionally-introduced defects that can be detected by the defection inspection tool.