Patent ID: 8473904
Filing Date: 2013-06-25
Classification: G06F

Abstract:
1. A method for generating an architecture for a circuit, comprising: obtaining a description of an application written in a high-level programming language; generating a data flow representation from the description suitable for providing an implementation in hardware; the generating including: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to locally cacheable data in the memory do not have one or more data dependencies for data referenced by any other of the accesses; compiling with a compiler the description for the identifying of the accesses to memory and the determining of the portion of the accesses to memory; producing an assembly language representation from the compiling; the assembly language representation indicating a distributed cache for a circuit implementation of the application; the assembly language representation indicating the accesses to memory as being either reads or writes; the assembly language representation indicating the distributed cache as having separate cache memory spaces for each of the accesses to memory of the portion; and assigning the portion of the accesses to memory to the distributed cache; assigning values to parameters that parameterize the distributed cache; and converting the data flow representation of the description and the distributed cache with the assigned parameter values into a hardware description language representation of the circuit.