Patent ID: 7420844
Filing Date: 2008-09-02
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array in which a group of memory cells are arranged in a matrix shape; a group of word lines; a group of bit lines; and a differential detector, wherein the group of memory cells can retain two-bit information, and each of the memory cells has a pair of transistors having a charge storage region and arranged along a row direction of the memory cell array; the word lines are provided between the memory cells adjacent to each other along a column direction of the memory cell array and extend along the row direction, the respective bit lines are provided between the transistors adjacent to each other along the row direction and extend along the column direction, gates of the pair of transistors constituting the respective memory cells are connected to each other and further connected to the word line corresponding to the relevant memory cell, sources of the pair of transistors are connected to each other and further connected to the bit lines provided between the relevant pair of transistors, drains of the transistors facing each other between the memory cells adjacent to each other along the row direction are connected to each other and further connected to the bit line provided between the relevant adjacent memory cells, a pair of the bit lines connected to the both drains of the pair of transistors included in all of the memory cells are connected to a comparison input terminal of the differential detector, and an information retained in the memory cell is read based on a comparison result of current amounts inputted to the differential detector via the pair of bit lines obtained by the differential detector in a state where memory cell currents are simultaneously and independently supplied to the pair of transistors.