Patent ID: 6235557
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method of forming a fuse in a second-to-the-last metal interconnect layer, the second-to-the-last metal interconnect layer of a semiconductor device substrate having at least two metal interconnect layers comprising:forming the fuse in the second-to-the-last metal interconnect layer;forming a first oxide layer over the fuse;depositing a last metal interconnect layer on the first oxide layer and forming a bonding pad therefrom;forming a second oxide layer over the bonding pad and the first oxide layer;forming a nitride layer over the second oxide layer;masking the nitride layer to define a first region over the fuse and a second region over the bonding pad; andetching the nitride layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second oxide layer in the first and second region until the bonding pad is exposed.