Patent ID: 6506670
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A method for making a gate in an integrated circuit, the method comprising the steps of:forming a gate layer on a substrate, forming a blocking layer on the gate layer, masking the blocking layer with a negative photoresist layer and exposing the negative photoresist layer using a positive photoresist mask, where the positive photoresist mask is typically used to expose a positive photoresist layer prior to a gate etch process, developing the photoresist layer to define an exposed gate area, etching the blocking layer in the gate area to expose the gate layer in the gate area, removing the photoresist layer, forming a metal layer on the blocking layer and on the gate layer in the gate area, selectively reacting the metal layer with the gate layer in the gate area to form a hard mask over the gate layer in the gate area, removing the metal layer from the blocking layer, selectively etching the blocking layer without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area, and etching the exposed gate layer to define a gate in the gate area, where the hard mask remains on the gate and functions as an electrical contact to the gate.