Patent ID: 6633621
Filing Date: 2003-10-14
Classification: G04G,H03L

Abstract:
A method for synchronizing a clock using a phase-locked loop circuit which includes an adjustable oscillator and a feedback loop, the method comprising:receiving multiple timing errors, wherein each timing error is based on timing information from one of multiple timing sources; combining the multiple timing errors, resulting in a loop time error; generating an input to the adjustable oscillator based on the loop time error, wherein the adjustable oscillator adjusts an oscillator frequency based on the input, and the oscillator frequency is fed back through the feedback loop, causing the loop time error to approach zero; monitoring the multiple timing errors; applying a weighting factor to each of the multiple timing errors, prior to combining the multiple timing errors; when a particular timing error of the multiple timing errors is out of tolerance, reducing an impact of the particular timing error; determining whether all of the multiple timing errors are out of tolerance; and when all of the multiple timing errors are out of tolerance, suspending oscillator frequency adjustments.