Patent ID: 8051399
Filing Date: 2011-11-01
Classification: G06F

Abstract:
1. A non-transitory computer readable medium carrying one or more sequences of instructions for causing a digital processing system to facilitate designing of an integrated circuit, wherein execution of said one or more sequences of instructions by one or more processors contained in said digital processing system for designing said integrated circuit causes said digital processing system to perform the actions of: forming a set of data indicating cells and connection paths in said integrated circuit: identifying a timing window for each cell in said integrated circuit, with said timing window representing a time interval during which an output of the cell is expected to switch: selecting a maximum voltage in a first sub-interval and a minimum voltage in a second sub-interval, wherein at least a portion of said first sub-interval is earlier than said second sub-interval, said first sub-interval and said second sub-interval are contained in said timing window and have at least some non-overlapping duration, wherein said maximum voltage represents a maximum value of power supply voltage provided at said cell in said first sub-interval, and said minimum voltage represents a minimum value of power supply voltage provided at said cell in said second sub-interval; and performing a timing analysis for said integrated circuit based on said maximum voltage and said minimum voltage for said cell; wherein an end time instance of said second sub-interval coincides with an end time instance of said timing window, wherein a start time instance of said first sub-interval coincides with a start time instance of said timing window; wherein said cell is in a launch path of a clocked element, said timing analysis is designed to perform setup timing analysis using said minimum voltage and to perform hold timing analysis using said maximum voltage.