Patent ID: 6251713
Filing Date: 2001-06-26
Classification: G11C,H01L,Y10S

Abstract:
A method of producing a an n-channel bulk pull-down transistor and an n-channel pull-up thin film transistor for an SRAM cell, comprising the steps of:forming an active and a field isolation region over a semiconductor substrate;forming a first gate oxide layer and a first polysilicon layer over the semiconductor substrate, the first polysilicon layer defining a gate electrode for the n-channel bulk pull-down transistor;forming source/drain transistor regions for the n-channel bulk pull-down transistor;forming an isolation layer over the first polysilicon layer and over the active region;depositing a second polysilicon layer;patterning and etching the second poly silicon layer to form a gate electrode for the n-channel pull-up thin film transistor over the n-channel bulk pull-down transistor and electrically connected to a drain region of the n-channel bulk pull-down transistor;depositing and patterning a dielectric over the second polysilicon layer to form a gate dielectric for the n-channel pull-up thin film transistor;depositing a third polysilicon layer;patterning and etching the third polysilicon layer to form channel, source and drain regions of the n-channel pull-up thin film transistor;implanting dopants into the channel region of the n-channel pull-up thin film transistor so that the n-channel pull-up thin film transistor is a depletion mode transistor;implanting dopants into the source-drain regions of the n-channel pull-up thin film transistor; anddepositing a dielectric layer.