Patent ID: 8238172
Filing Date: 2012-08-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array which includes memory cells associated with columns and capable of storing data; first latch circuits associated with the columns and holding information as to whether an associated column is defective; second latch circuits in which a pointer is set, the second latch circuits being associated with the columns; and third latch circuits associated with the columns and holding write data or read data for an associated column, one of the third latch circuits being activated at a time the pointer is set to an associated one of the second latch circuits when an associated one of the first latch circuits holds the information indicating that the associated column is not defective, wherein the pointer is sequentially shifted among the second latch circuits in synchronization with a clock, and in shifting the pointer, the pointer skips one of the second latch circuits associated with one of the first latch circuits which holds the information indicating that the associated column is defective.