Patent ID: 6915469
Filing Date: 2005-07-05
Classification: G11C

Abstract:
1. A method for fetching test patterns from a pattern memory at an operating frequency of a device under test (DUT) which is higher than an operating frequency of the pattern memory, comprising: determining a DUT/pattern memory speed ratio by dividing the DUT operating frequency by an operating frequency of the pattern memory, and rounding up to a higher integer if the ratio contains a fractional part; organizing the pattern memory into m modules, where m is an integer equal to or greater than the DUT/memory speed ratio; inserting one address delay circuit in a portion of an address line unique to each of the m modules for delaying an address for the qth module by (q−1) delay units, where q varies from one to m and one delay unit represents approximately one DUT clock cycle; storing n test patterns into the m modules in a fixed repeating module order according to [n mod m], the storing of test patterns into any one module for each of the m modules following a fixed address sequence; and simultaneously applying identical addresses to the address delay circuits of the m modules according to the fixed address sequence at a rate f equal to or slower than the operating frequency of the pattern memory, such that a period of f is equal to or greater than (m−1) delay units; wherein the address delay circuits cause the identical addresses to be applied to the address lines of the m modules in a time-staggered manner, resulting in fetching of m test patterns in each period of f, one test pattern at a time, at the DUT operating frequency.