Patent ID: 7071981
Filing Date: 2006-07-04
Classification: H04N

Abstract:
1. A system for high-speed image capture, comprising: a first clock; a plurality of pixels being arranged in a plurality of pixel groups, the plurality of pixel groups having a first pixel group, each pixel in the plurality of pixels having a photo sensitive element and a storage element, the photo sensitive element producing an output indicative of incoming light; and a control element coupled to the plurality of pixels, the control element resetting the plurality of pixel groups iteratively and at the rate of one pixel group in the plurality of pixel groups per one c clock cycle of the first clock, and the control element transferring the outputs of a plurality of photo sensitive elements in the first pixel group to a plurality of storage elements in the first pixel group, the transferring proceeding at the rate of one pixel group in the plurality of pixel groups per one c′ clock cycle of the first clock and occurring simultaneously for all pixels in the first pixel group, wherein the first clock generates a first clock signal at a first rate, the first clock signal generating a second clock signal at a second rate, the second clock signal triggering an analog-to-digital converter (ADC).