Patent ID: 6735123
Filing Date: 2004-05-11
Classification: G11C,H01L,Y10S

Abstract:
A method of storing data in dual bit dielectric memory cell that includes a tunnel dielectric layer having a tunnel dielectric layer with a thickness in a central region positioned between a source lateral region and a drain lateral region that is greater than a thickness in each of the source lateral region and the drain lateral region, and a continuous charge trapping layer overlying the tunnel dielectric layer, the method comprising:a) utilizing a source-to-drain bias in the presence of a control gate field to induce hot electron injection through a tunnel dielectric thickness greater than the thickness in the source lateral region and less than the thickness in the central region to inject a charge into a source charge trapping region within the charge trapping layer; and b) utilizing a drain-to-source bias in the presence of a control gate field to induce hot electron injection through a tunnel dielectric thickness greater than the thickness in the drain lateral region and less than the thickness in the central region to inject a charge into a drain charge trapping region within the charge trapping layer.