Patent ID: 6097256
Filing Date: 2000-08-01
Classification: H03K

Abstract:
A ring oscillator of the type including a plurality of cascaded stages of delay circuits for generating an oscillating signal in response to a control voltage, wherein each of the delay circuits comprises:a CMOS CSL inverter having a positive input port, a negative input port, a positive output port, and a negative output port, which also serves as the input/output ports of the delay circuits; anda positive-feedback gate structure for providing a positive feedback to the CMOS CSL inverter, the positive-feedback gate structure including:a first CMOS transistor whose drain is connected to the negative input port of the CMOS CSL inverter and whose gate is connected to the positive output port of the CMOS CSL inverter;a second CMOS transistor whose drain is connected to the positive input port of the CMOS CSL inverter and whose gate is connected to the negative output port of the CMOS CSL inverter; anda third CMOS transistor whose drain is connected to both the source of the first CMOS transistor and the source of the second CMOS transistor, whose source is connected to the ground, and whose drain is connected to the control voltage.