Patent ID: 7719874
Filing Date: 2010-05-18
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a plurality of first array lines; a plurality of second array lines substantially perpendicular to said plurality of first array lines; a plurality of non-volatile memory cells including a steering element in series with a state change element, each arranged between one of said first array lines and one of said second array lines, said plurality of memory cells including a subset of memory cells, each arranged between selected first array lines and selected second array lines and subjected to a bias during an operation to switch said subset of memory cells from a first resistance state to a second resistance state, said operation including at least one voltage pulse having an amplitude that changes to increase said bias for said subset of memory cells; and control circuitry in communication with said plurality of first array lines and said plurality of second array lines, said control circuitry switches a first non-volatile memory cell of said subset of memory cells from said first resistance state to said second resistance state by: