Patent ID: 7680874
Filing Date: 2010-03-16
Classification: G06F

Abstract:
1. An adder having an overflow output indicating when a sum of a first input number and a second input number overflows comprising: a logic operation circuit receiving respective bits of said first input number and said second input number and generating a carry propagate signal and a carry generate signal for each i-th bit of said first input number and said second input number; a first carry look ahead adder receiving a least significant bit carry input signal, carry propagate signals and carry generate signals for a first predetermined number of least significant bits, said first carry look ahead adder generating a carry output for a most significant of said first predetermined number of least significant bits; a second carry look ahead adder receiving said carry output for said most significant of said first predetermined number of least significant bits, carry propagate signals and carry generate signals for a second predetermined number of more significant bits, said second carry look ahead adder generating a carry output for a most significant of said second predetermined number of more significant bits; a first carry increment adder receiving said least significant bit carry input signal, carry propagate signals and carry generate signals for said first predetermined number of least significant bits, said first carry increment adder generating a sum output for each of said first predetermined number of least significant bits by propagating local carry signals; a second carry increment adder receiving said carry output for a most significant of said first predetermined number of least significant bits, carry propagate signals and carry generate signals for said second predetermined number of more significant bits, said second carry increment adder generating a sum output for each of said second predetermined number of least significant bits by propagating local carry signals; a carry select adder receiving said carry output for a most significant of said second predetermined number of more significant bits, carry propagate signals and carry generate signals for a third predetermined number of most significant bits, said carry save adder including: