Patent ID: 7560348
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A method for manufacturing an integrated circuit including at least one PMOS device having a gate, a body, an extended drain region formed in the body, a drain junction breakdown point, and a maximum impact ionization point, wherein the extended drain region includes a drain, a deep drain implant, and a lightly doped drain implant between the deep drain implant and the gate, and at least a portion of the lightly doped drain implant is located between the drain and the gate, said method including the step of: (a) producing the gate, the body, and the extended drain region such that at least a portion of the deep drain implant is located below the drain, and the maximum impact ionization point is located below the lightly doped drain implant within at least one of the body and the extended drain region so as to reduce any drain breakdown voltage walk-in exhibited by the device below a predetermined value.