Patent ID: 6503794
Filing Date: 2003-01-07
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor integrated circuit having memory cells, in each of which a first MISFET and a capacity element are connected serially; and a peripheral circuit comprised of second MISFETS, comprising the steps of:(a) preparing a semiconductor substrate having a first area for forming said memory cells and a second area for forming said peripheral circuit; (b) forming a first conductor layer on said semiconductor substrate and a first insulating film on said a first conductor layer; (c) forming first MISFET gate electrodes in said first area and second MISFET gate electrodes in said second area by patterning said first conductor layer and first insulating film; (d) implanting first conduction type impurity to form a first semiconductor area in a self-matching manner with respect to said second gate electrodes in said second area; (e) depositing a second insulating film covering said first and second gate electrodes; (f) forming first side wall spacers on side surfaces of said second gate electrodes in said second area by performing anisotropic etching of said second insulating film; (g) depositing a third insulating film in said second area so as to cover said second gate electrodes and first side wall spacers; (h) forming second side wall spacers on side surfaces of said first side wall spacers in said second area by performing anisotropic etching of said third insulating film; (i) implanting a first conduction type impurity to form a second semiconductor area in the second area in a self-matching manner with respect to said second side wall spacers; (j) depositing a fourth insulating film in said first area; (k) forming openings in said first area so as to overlap said first gate electrodes at some of said openings and expose the main surface of said semiconductor substrate; and (l) forming a second conductor layer in each of said openings in said first area, wherein said second conductor layer and said first gate electrodes are isolated electrically by said second insulating film from each other.