Patent ID: 8433874
Filing Date: 2013-04-30
Classification: G06F,G11C

Abstract:
1. A method for use in a system comprising a memory controller and at least one serial interconnection configuration including a plurality of memory devices of mixed device type serially interconnected, each of the plurality of memory devices including a memory for storing data, a signal input, a signal output, an enable input and an enable output, the enable output of one memo device being coupled to the enable input of a subsequent memo device the output of the one memo device being coupled to the input of the subsequent memory device, the method comprising: holding a device type identification in each of the plurality of serially interconnected memory devices of mixed device type, the device type identification of each of the serially interconnected devices indicating a device type of the memory included therein; holding an assigned device address identifying an address in each of the serially interconnected memory devices; providing a first input signal to the signal input of a first memory device of the serially interconnected memory devices by the memory controller, the first input signal comprising a device type read message and a first target device address; providing a first input enable signal having a predetermined logic level to the enable input of the first memory device of the serially interconnected memory devices by the memory controller, a first output enable signal derived from the first input enable signal being outputted from the enable output of the first memory device, the first output enable signal being provided to the enable input of the subsequent memory device, the first input enable signal being propagated through the remaining memory devices of the serially interconnected memory devices; in one memory device of the serially interconnected memory devices receiving a first read output signal from a last memory device of the serially interconnected memory devices, the first read output signal containing the first read device type identification of the one memory device; providing a second input signal to the signal input of the first memory device of the serially interconnected memory devices by the memory controller, the second input signal comprising the device type read message and a second target device address that is different from the first target device address; providing a second input enable signal having a predetermined logic level to the enable input of the first memory device of the serially interconnected memory devices by the memory controller, a second output enable signal derived from the second input enable signal being outputted from the enable output of the first memory device, the second output enable signal being forwarded to the enable input of the subsequent memory device, the second input enable signal being propagated through the remaining memory devices of the serially interconnected memory devices; in another memory device of the serially interconnected memory devices receiving a second read output signal from the last memory device of the serially interconnected memory devices, the second read output signal containing the second read device type identification of the another memory device; identifying a target memory device of the serially interconnected memory devices to be accessed based on the first and second read device type identifications of the received first and second read output signals; providing a third input enable signal having a redetermined logic level to the enable input of the first memo device of the serial interconnected memo devices by the memory controller a third output enable signal derived from the third input enable signal being outputted from the enable output of the first memory device, the third output enable signal being provided to the enable input of the subsequent memory device, the third input enable signal being propagated through the remaining memory devices of the serially interconnected memory devices; providing a third input signal to the signal input of the first memory device of the serially interconnected memory devices by the memory controller, the third input signal comprising an access operation message and a device address of the identified target memory device of the serially interconnected memory devices; and selecting a memory device of the serially interconnected memory devices in accordance with the device address of the identified target memory device comprised in the third input signal propagated in response to the propagated third input enable signal, the selected memory device being configured to perform an operation to the memory included in the selected memory device in accordance with the access operation message of the third input signal.