Patent ID: 6710399
Filing Date: 2004-03-23
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor storage device comprising:a memory cell array region in which a plurality of memory cells are arranged in a first direction and a second direction intersecting with each other, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates; a plurality of sub control gate lines which extend in the first direction and are respectively disposed in a plurality of block areas formed by dividing the memory cell array region in the first direction, each of the sub control gate lines being connected with the first nonvolatile memory element of one of two the memory cells adjacent to each other in the second direction and the second nonvolatile memory element of the other of the two memory cells; a plurality of main control gate lines each of which is formed extending over the block areas arranged in the first direction, and connected in common to corresponding sub control gate lines in each of the block areas arranged in the first direction; a plurality of control-gate-line selection switching elements which are respectively disposed at connection points between the main control gate lines and the sub control gate lines, and each of the control-gate-line selection switching elements selecting connection or non-connection based on a control voltage; and a control-gate-line selection driver which supplies the control voltage to the control-gate-line selection switching elements, wherein each of the plurality of sub control gate lines is connected to the first control gate of one of two the memory cells adjacent to each other in the second direction, and to the second control gate of the other of the two memory cells, wherein the plurality of control-gate-line selection switching elements include a first group of control-gate-line selection switching elements and a second group of control-gate-line selection switching elements respectively connected to every second line among the sub control gate lines arranged in the second direction, wherein the control-gate-line selection driver includes a first control-gate-line selection driver which supplies a first control voltage to the first group of control-gate-line selection switching elements, and a second control-gate-line selection driver which supplies a second control voltage to the second group of control-gate-line selection switching elements, wherein the first control-gate-line selection driver supplies the first group of control-gate-line selection switching elements with the first control voltage that is set to be higher than the second control voltage when data is read out of one of the first and second nonvolatile memory elements, and the control-gate-line selection switching elements connected to the sub control gate lines to which an override voltage is applied is included in the first group of control-gate-line selection switching elements, and wherein the second control-gate-line selection driver supplies the second group of control-gate-line selection switching elements with the second control voltage that is set to be higher than the first control voltage when data is read out of the other of the first and second nonvolatile memory elements, and the control-gate-line selection switching elements connected to the sub control gate lines to which the override voltage is applied is included in the second group of control-gate-line selection switching elements.