Patent ID: 8014202
Filing Date: 2011-09-06
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory array which includes: the memory array includes one or more usable regions which can store data, and one or more isolation regions which cannot store data, the one or more isolation regions are arranged in parallel to a bit-line direction, isolating the one or more usable regions from each other, the plurality of bit lines and the plurality of main bit lines are provided in the one or more usable regions, each of the plurality of bit lines is connected via a first select transistor to a corresponding one of the plurality of main bit lines, a first isolation region bit line is provided in the one or more isolation regions, and at least a first main bit line of the plurality of main bit lines is connected via a corresponding first select transistor to the first isolation region bit line in addition to a corresponding one of the plurality of bit lines provided in the one or more usable regions.