Patent ID: 7932729
Filing Date: 2011-04-26
Classification: G01R,H03K

Abstract:
1. A test apparatus that tests a device under test, comprising: a pattern generating section that generates a test pattern; a timing signal generating section that generates a timing signal indicating a timing for supplying the test signal to the device under test; a digital filter that receives the test pattern from the pattern generating section and filters the test pattern to output a jitter control signal representing jitter corresponding to the test pattern, the digital filter increasing the amplitude of the output jitter control signal when the test pattern designates a low-frequency waveform and decreasing the amplitude of the output jitter control signal when the test pattern designates a high-frequency waveform; a jitter injecting section that receives the timing signal from the timing signal generating section and injects the timing signal with jitter by delaying the timing signal according to the jitter control signal; and a waveform shaping section that receives the test pattern from the pattern generating section and receives the timing signal injected with jitter by the jitter injecting section, and generates the test signal formed according to the test pattern, with the timing signal into which the jitter is injected as a reference.