Patent ID: 8354867
Filing Date: 2013-01-15
Classification: H03L

Abstract:
1. A phase-locked loop (PLL) circuit comprising: a delay locked loop (DLL) receiving a clock signal and generating a reference signal based on the clock signal; a phase-frequency detector (PFD) receiving the reference signal and a feedback signal and generating a control voltage based on the difference between the received reference signal and the feedback signal, wherein the reference signal and the feedback signal are both sine waves and each signal comprises an in-phase component and an out-of-phase component; a loop filter being a low-pass filter and filtering out high frequency components of the control voltage; a voltage controlled oscillator (VCO) receiving the filtered control voltage from the loop filter and generating an oscillating signal based on the control voltage; and a frequency divider being connected to the VCO, dividing the frequency of the oscillating signal and then transmitting the divided oscillating signal to the PFD as the feedback signal; wherein the PFD comprises: wherein the dominator comprises: