Patent ID: 8826202
Filing Date: 2014-09-02
Classification: G06F

Abstract:
1. A method for verifying a functionality of a chip design, the method performed by at least one processor and comprising: (a) receiving a chip design having a plurality of design blocks; (b) functionally testing the plurality of design blocks on a test bench using a verification tool; (c) receiving coverage files corresponding to the plurality of design blocks from the verification tool; (d) receiving a design exclusion list, a coverage basis and a defined coverage; (e) for the coverage basis and each of non-excluded design blocks in the plurality of design blocks but not in the design exclusion list, calculating coverage impact and new overall coverage using the defined coverage and the coverage files; (f) ranking each of the non-excluded design blocks according to the calculated coverage impact and new overall coverage; and (g) generating a ranked candidate list based on said ranking.