Patent ID: 7675582
Filing Date: 2010-03-09
Classification: G02F,H01L

Abstract:
1. A stacked storage capacitor structure for a thin film transistor liquid crystal display having a plurality of pixels, each pixel having a pixel area, wherein at least some of the pixels have a storage capacitor formed substantially within the pixel area and associated with the stacked storage capacitor structure, the stacked storage capacitor structure comprising: a first storage capacitor having a first plate formed by a first electrically conductive layer, a second plate formed by a second electrically conductive layer and a dielectric formed by a first insulator layer positioned between the first electrically conductive layer and the second electrically conductive layer; and a second storage capacitor having a first plate formed by a third electrically conductive transparent layer, a second plate formed by the second electrically conductive layer and a dielectric formed by a second insulator layer positioned between the first and second plates, wherein the first electrically conductive layer and the third electrically conductive layer are electrically connected to each other through a single via so that the first and second storage capacitors are electrically connected in parallel, and wherein the second electrically conductive layer is positioned between the first electrically conductive layer and the third electrically conductive layer, wherein each of said at least some of the pixels further comprises: a semiconductor switching element; a gate line disposed at one edge section of the pixel area for controlling the switching element; a common line disposed in a pixel section spaced from the gate line for controlling electric charges in the storage capacitor, and wherein the stacked storage capacitor structure is formed substantially in said pixel section; and a pixel electrode having a first pixel electrode segment and a second pixel electrode segment located within the pixel area separated by said pixel section in a non-overlapping manner, the first pixel electrode segment and the second pixel electrode segment electrically connected to the second electrically conductive layer, wherein the first electrically conducting layer is electrically connected to the common line.