Patent ID: 7473999
Filing Date: 2009-01-06
Classification: H01L

Abstract:
1. A semiconductor chip comprising: a semiconductor substrate; a first MOS device in and over said semiconductor substrate; a second MOS device in and over said semiconductor substrate; a first metallization structure over said semiconductor substrate, wherein said first metallization structure is connected to a diffusion layer of said first MOS device, and wherein said first metallization structure comprises a first portion and a second portion over said first portion, wherein said first portion is connected to said second portion; a second metallization structure over said semiconductor substrate, wherein said second metallization structure is connected to a gate of said second MOS device, and wherein said second metallization structure comprises a third portion and a fourth portion over said third portion, wherein said third portion is connected to said fourth portion, and wherein said first and third portions are provided by a first metal layer, and said second and fourth portions are provided by a second metal layer over said first metal layer; an insulating layer between said first and second metal layers; a passivation layer over said first and second metal layers and over said insulating layer, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers; and a third metallization structure over said passivation layer, wherein said third metallization structure is connected to said first metallization structure through a first opening in said passivation layer, and to said second metallization structure through a second opening in said passivation layer, and wherein said diffusion layer is connected to said gate through, in sequence, said first metallization structure, said third metallization structure and said second metallization structure.