Patent ID: 7041605
Filing Date: 2006-05-09
Classification: H01L

Abstract:
1. A method of forming structure of a semiconductor device, said method comprising: providing a semiconductor substrate having conductive material thereon; forming an interlayer dielectric on the semiconductor substrate including directly against an uppermost surface of the conductive material; patterning the interlayer dielectric to form a contact hole exposing the uppermost surface of the conductive material on the semiconductor substrate; subsequently isotropically etching the exposed conductive material to form a recess therein that is open at said uppermost surface to the interlayer dielectric and is wider at said uppermost surface than the contact hole as taken laterally in a direction extending along the upper surface of said substrate, wherein said recess undercuts sidewalls that define the sides of said contact hole; filling said recess and said contact hole with conductive material to thereby form a contact plug having a lower portion that rests directly on said conductive material and forms an interface with said interlayer dielectric, and an upper portion that extends through said contact hole, wherein the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop the substrate; and subsequently subjecting the substrate having the contact plug formed thereon to a process conducted at a temperature that causes the interlayer dielectric to reflow, whereby the contact plug remains in position atop said conductive material on the substrate during the reflowing of the interlayer dielectric.