Patent ID: 8179734
Filing Date: 2012-05-15
Classification: G11C

Abstract:
1. A semiconductor device comprising: a charge pump circuit whose output is connected to a first node and that starts a boosting operation after start of a test period; a load current application circuit configured to supply a load current to said first node during said test period and to stop supply of said load current to said first node after end of said test period, wherein a voltage of said first node is a write voltage; a memory circuit comprising a memory cell and configured to stop application of said write voltage to said memory cell during said test period and to apply said write voltage to said memory cell after end of said test period; and a high voltage detection unit configured to make a comparison between said write voltage and a predetermined voltage to determine whether or not said write voltage is increased to said predetermined voltage, wherein if said write voltage is less than said predetermined voltage at the end of said test period, said high voltage detection unit activates a disable signal, wherein said charge pump circuit stops said boosting operation if said disable signal is activated, and otherwise said charge pump circuit continues said boosting operation.