Patent ID: 6835986
Filing Date: 2004-12-28
Classification: G02F,H01L

Abstract:
A semiconductor device comprising:at least one p-channel thin film transistor and at least one n-channel thin film transistor, each comprising: an active layer comprising a pair of impurity regions and a channel region between the pair of impurity regions over an insulating surface; a gate insulating film over the active layer; and a gate electrode over the gate insulating film, a first insulating film over the thin film transistor; first and second wirings connected to the active region through contact holes in the first insulating film, a second insulating film over the first insulating film; wherein a part of an edge portion of at least one of first and second wirings is aligned with at least one edge portion of the active layer, wherein the gate insulating film is in contact with the first and second wirings and not in contact with the at least one edge portion of the active layer, and wherein a concentration of a catalyst element in the active layer of the at least one p-channel thin film transistor is lower than that of the at least one n-channel thin film transistor.