Patent ID: 8497709
Filing Date: 2013-07-30
Classification: H03K

Abstract:
1. An input/output circuit, comprising: a first load having one end coupled to a first standard voltage line; a first MOS transistor having a drain electrode coupled to another end of the first load; a second load having one end coupled to the first standard voltage line; a second MOS transistor having a drain electrode coupled to another end of the second load; a third MOS transistor having a source electrode coupled to one of a source electrode of the first MOS transistor and a source electrode of the second MOS transistor, a drain electrode coupled to another of the source electrode of the first MOS transistor and the source electrode of the second MOS transistor, and a gate electrode configured to receive a control signal indicating one of a differential mode and a single mode, a gate electrode of the first MOS transistor and a gate electrode of the second MOS transistor receiving a differential signal in the differential mode, at least at one of the gate electrode of the first MOS transistor and the gate electrode of the second MOS transistor receiving a single-ended signal in the single mode, the third MOS transistor being configured to couple the source electrode of the first MOS transistor and the source electrode of the second MOS transistor in the differential mode and to decouple the source electrode of the first MOS transistor and the source electrode of the second MOS transistor in the single mode; a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line; and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line.