Patent ID: 7663185
Filing Date: 2010-02-16
Classification: H01L

Abstract:
1. A fin-FET structure comprising: a bulk semiconductor substrate having a fin and an adjoining trough wherein said fin consists of a single width; a first dielectric layer filling the trough to a first height, said first dielectric layer being a substantially planar layer directly contacting the fin to provide an exposed fin region above said first height and an unexposed fin region below said first height; a second dielectric layer over the first dielectric layer such as to define an aperture, said aperture comprising a apace extending horizontally between the second dielectric layer and a sidewall of the exposed fin region; a gate dielectric layer upon the exposed fin region extending to said first dielectric layer and partially filling the aperture, said gate dielectric layer not upon said unexposed fin region; and a gate electrode upon the gate dielectric layer and completely filling the aperture.