Patent ID: 6448177
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method of forming a semiconductor device comprising:forming a support structure on a substrate, the support structure having a first dielectric constant; forming adjacent to the support structure a low-k insulating layer, the low-k insulating layer having a second dielectric constant, the second dielectric constant being less than the first dielectric constant; removing a first part of the low-k insulating layer to form a via; removing a second part of the low-k insulating layer to form a trench; and filling the trench and the via with a conductive material, generating a dual damascene interconnect comprising a conductive line, wherein the conductive line is spaced from the support structure; wherein the support structure is formed by: forming a barrier layer on the substrate; forming a first insulating layer on the barrier layer; forming on the first insulating layer a layer of photoresist and then patterning the photoresist layer to define the support structure; and removing a first part of the first insulating layer to form the support structure; wherein the low-k insulating layer is formed on the remaining portion of the first insulating layer; wherein the via and trench are formed by removing a first part of the low-k insulating layer and a second part of the first insulating layer to form the via, and by removing a second part of the low-k insulating layer to form the trench; and wherein the trench and the via are filled with the conductive material such that the conductive line contacts the remaining portion of the first insulating layer; and further comprising removing a substantial part of the remaining portion of the low-k insulating layer to create a gap between the conductive line and the support structure.