Patent ID: 8669604
Filing Date: 2014-03-11
Classification: G11C,H01L

Abstract:
1. An electronic device including a nonvolatile memory cell comprising: a capacitor having a first electrode and a second electrode, wherein a control gate terminal is coupled to the first electrode, and the second electrode has a first conductivity type; a tunnel structure having a first electrode and a second electrode, wherein an erase terminal is coupled to the first electrode, and at least a portion of the second electrode has a second conductivity type opposite the first conductivity type; a state transistor including a source region, a drain region, and a gate electrode, wherein a floating gate electrode for the nonvolatile memory cell includes the gate electrode, the second electrode of the capacitor, and the second electrode of the tunnel structure; an access transistor including a source region, a drain region, and a gate electrode, wherein the source region of the access transistor is coupled to the drain region of the state transistor; and a field isolation region, wherein the first electrode of the capacitor includes a first n-well region, wherein the first electrode of the tunnel structure includes a second n-well region, wherein the source and drain regions of the state and access transistors are disposed within a first p-type region, wherein portions of the field isolation region are disposed between the first n-well region, the second n-well region, and the first p-type region, and wherein the first n-well region, the second n-well region, and the first p-type region are electrically isolated from one another.