Patent ID: 6042999
Filing Date: 2000-03-28
Classification: G03F,H01L

Abstract:
A method of forming a dual damascene structure with a protective coating in hole openings comprising the steps of:providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;forming a lower level dielectric (LLD) layer over said substrate;forming an etch-stop layer over said LLD layer;forming an upper level dielectric (ULD) layer over said etch-stop layer;forming a first photoresist layer over said ULD layer;patterning said first photoresist layer with a hole pattern;etching through said hole pattern in said first photoresist layer into said ULD layer;etching further said hole pattern into said etch-stop layer;etching further said hole pattern into said LLD layer until a lower level said substructure of said substrate is reached;removing said first photoresist layer from said substrate;forming a bottom-anti-reflective coating (BARC) over said substrate and filling said hole opening with said BARC;forming a second photoresist layer over said BARC over said substrate including said hole opening;patterning said second photoresist layer with a conductive line opening pattern;performing a timed-etch through said conductive line opening in said second photoresist layer to remove said BARC from said hole opening in said ULD layer and partially from said hole opening in said LLD layer;etching through said conductive line opening in said second photoresist layer into said ULD layer until etch-stop layer is reached;removing said second photoresist layer;removing remaining said BARC from said hole opening in said LLD layer;forming metal in said conductive line opening in said ULD layer and hole opening through said etch-stop layer and in said LLD layer; andremoving said metal from the surface of said substrate for subsequent process steps to complete the fabrication of a semiconductor substrate.