Patent ID: 6636518
Filing Date: 2003-10-21
Classification: H04J,H04L,H04Q

Abstract:
A synchronization circuit for synchronizing components operating isochronously that are coupled by a plurality of independent links, comprising:a first and second buffer, each including an input port coupled to an external link of the plurality of independent links, an output port, a read pointer and a write pointer, the read pointer indicating a next location in a respective buffer to be read in transferring data out on the output port, the write pointer indicating a next location in the respective buffer to be written when receiving data on the input port and configured to automatically increment upon receipt of a first data bit on a respective external link; a trigger circuit coupled to each link of the plurality of independent links for receiving external trigger signals, each external trigger signal included along with data transmitted on a respective link and indicating when data is present on the respective link; and a counter coupled to the trigger circuit, the counter including a trigger input and a predefined delay period, only after receipt of a first of the external trigger signals on the trigger input the counter being operable to output a read enable signal to each of the read pointers after the delay period has expired.