Patent ID: 6731149
Filing Date: 2004-05-04
Classification: H03K,H03L

Abstract:
A delay circuit applied to a synchronizing circuit comprising:a first delay line which includes unit delay elements and transfers a forward pulse signal; a second delay line which includes unit delay elements and transfers a backward pulse signal; and a state holding section which is brought into a set state or a reset state according to a transfer position of the forward pulse signal transferred along said first delay line and said backward pulse signal transferred along said second delay line in the set state and a clock signal along said second delay line in the reset state, wherein each of said unit delay elements constituting said first and second delay lines includes: a clocked inverter circuit to which a first pulse signal corresponding to one of said forward and backward pulse signals output from a preceding delay unit is supplied, said clocked inverter circuit outputting a second pulse signal having one of a first pulse width and a second pulse width, the first pulse width being greater than a pulse width of the first pulse signal and the second pulse width being smaller than the pulse width of the first pulse signal; and a logic circuit to which the second pulse signal output from the clocked inverter circuit and an inverted signal of said first pulse signal are supplied, wherein said logic circuit outputs a third pulse signal, the third pulse signal having the other one of the first pulse width and the second pulse width.