Patent ID: 6420097
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method of forming circuit structures having linewidths which are smaller than what is achievable by conventional UV lithographic techniques on ultra-thin resist layers, said method comprising the steps of:providing a semiconductor wafer stack formed of a substrate and a device layer above the substrate; depositing a hardmask layer over the device layer; depositing an ultra-thin resist layer over the hardmask layer; forming a resist mask having an initial linewidth; anisotropically etching exposed portions of the hardmask layer; isotropically etching subsequently the hardmask layer underneath the resist mask to form a hardmask having a final linewidth which is narrower than the initial line width of the resist mask and corresponds to a desired structure linewidth; and anisotropically etching the device layer as defined by the hardmask to form a structure having a width substantially equal to the final linewidth of the hardmask.