Patent ID: 7504890
Filing Date: 2009-03-17
Classification: H03L,H04L

Abstract:
1. A frequency acquisition and phase-lock loop having a symbol rate, comprising: a voltage controller oscillator that provides an I output and Q output; a first multiplier that receives the first input and the I and Q outputs, and provides I′ and Q′ outputs; a second multiplier that multiplies the I′ and Q′ outputs by a first fixed frequency to produce I″ and Q″ outputs; a third multiplier that receives the I″ and Q″ outputs and convolves them to produce I′″ and Q′″ outputs; a fourth multiplier that receives the I′″ and Q′″ outputs and multiplies them by a second fixed frequency to produce first I″″ and Q″″ outputs; a fifth multiplier that receives the I′″ and Q′″ outputs and multiplies them by a third fixed frequency to produce second I″″ and Q″″ outputs; first and second low-pass filters that receive the first and second I″″ outputs respectively, to produce first and second filtered I″″ outputs, respectively; a sixth and seventh multipliers that receive the first and second Q″″ outputs, respectively, and the first and second filtered I″″ outputs, respectively, to produce first and second response outputs, respectively; a summer that receives the first and second response outputs to produce a combined response signal; a third low-pass filter that receives the combined response signal to produce a filtered combined response signal; wherein the filtered combined response signal is fed back to the voltage controlled oscillator.