Patent ID: 8077492
Filing Date: 2011-12-13
Classification: G11C

Abstract:
1. A semiconductor signal processing device comprising: a first processing unit; an internal bus; and a plurality of operation units each comprising a memory unit, an operational block, an interface circuit, and an operational control unit, wherein said first processing unit issues an instruction to said operation units via said internal bus, wherein said memory unit includes a data rearranging memory mat, and receives data from said interface circuit, stores said data to said data rearranging memory mat in a first direction, reads rearranged data from said data rearranging memory mat in a second direction crossing said first direction, and provides said rearranged data to said operational block, and comprising: a first word line; a second word line arranged crossing said first word line; a bit line pair arranged crossing said first word line; a search line pair arranged parallel to said bit line pair; a match line pair arranged crossing said bit line pair; and a memory cell including a data storage portion for storing data and a search/read portion for driving said match line pair in accordance with signals on said search line pair and the data stored in said data storage portion, said data storage portion communicating data with said bit line pair when said first word line is selected, and said search/read portion reading the data stored in said data storage portion to said match line pair when said search line pair is selected; wherein said operational block includes a memory array for storing said rearranged data provided from said memory unit and divided into plural entries, and a plurality of processing elements each of which corresponds to an entry of said memory array, and wherein plural processing elements perform an operation instructed by said operational control unit using data provided from a first selected memory cell in corresponding entries in parallel and a stores result of said operation into a second selected memory cell in said corresponding entries in parallel, wherein said memory array selects a first word line for activating said first selected memory cell of all entries, and selects a second word line for activating said second selected memory cell of all entries.