Patent ID: 7952414
Filing Date: 2011-05-31
Classification: G06F,H03K

Abstract:
1. A phase clock generator comprising: Transistors arranged in a 4×N matrix, where N is a number of columns, wherein transistors of a first row and a second row of the 4×N matrix are arranged as PMOS transistor pairs, wherein transistors of a third row and a fourth row of the 4×N matrix are arranged as NMOS transistor pairs, wherein the transistors of the 4×N matrix receive a plurality of phase-delayed signals through respective gate terminals, wherein first row transistors connect to a power line and fourth mw transistors connect to a ground line; and a buffer connected to a line that is connected to a drain node of second row transistors and third row transistors, wherein the buffer transmits a clock signal, wherein the gate terminals of the transistors forming “first row×each column” receive different types of phase-delayed signals based on an equation P[2(n−1)], where n is a positive integer, wherein a first column receives the phase-delayed signal initially where n=2, and each consecutive column to an N