Patent ID: 6160752
Filing Date: 2000-12-12
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of bit lines arranged in a bit line direction, a plurality of word lines arranged in a word line direction intersecting the bit line direction and a plurality of memory cells arranged in matrix form and connected to the plurality of bit lines and the plurality of word lines;a boosting voltage generating circuit region having a voltage boosting circuit boosts a potential to a constant boosted potential;a word line driving circuit array having a plurality of word line driving circuits connected to the plurality of word lines and driving the plurality of word lines, the word line driving circuit array being provided in the word line direction;a row decoder array having an output terminal which outputs a decode signal to the word line driving circuit array, an input terminal which inputs address signals for selecting at least one word line driving circuit, and a P-channel transistor having a gate terminal and a current path, the gate terminal being supplied with a boosted precharge signal using a constant boosted potential, a first end of the current path being supplied with the constant boosted potential and a second end of the current path being connected to the output terminal of the row decoder array, the row decoder array being provided in the word line direction and in an area other than an area between the memory cell array and the word line driving circuit array; anda level-shifting circuit region being supplied the constant boosted potential and a precharge signal using a power-supply potential and converting the precharge signal using a power-supply potential to the boosted precharge signal using the constant boosted potential and outputting the boosted precharge signal, the level-shifting circuit region being provided in an area which is other than the area between the memory cell array and the word line driving circuit array and which is also other than an area between the word line driving circuit array and the row decoder array.