Patent ID: 7079983
Filing Date: 2006-07-18
Classification: G01R

Abstract:
1. A method for implementing physical interconnect fault source identification comprising the steps of: providing a net naming algorithm for assigning unique patterned names for all system nets; said unique patterned names for all system nets including embedded data identifying each connected chip for each assigned unique patterned name; running an interconnect test for a system under test; checking for faults; responsive to detecting faults, processing interconnect test data from said interconnect test for the system under test and identifying unique failing chip combinations by eliminating redundant failing chip combinations using said net naming algorithm; providing a respective count value for each identified unique connected chip, wherein said count value is defined as the number of said identified unique failing chip combinations in which the respective chip appears; and reporting a high probability failure for each said identified common failing chip having said count value above a set threshold.