Patent ID: 6831320
Filing Date: 2004-12-14
Classification: H01L

Abstract:
A memory cell configuration, comprising:a semiconductor material having active regions; word lines and bit lines; memory cells each having a trench capacitor and a selection transistor; said trench capacitor: being at least partly introduced into said semiconductor material; and being electrically conductively connected to a bit line through said selection transistor; each of said selection transistors of said memory cells having: a control terminal formed by a word line; first and second terminal regions formed in an active region of said semiconductor material, said first terminal region being conductively connected to a respective one of said trench capacitors; said trench capacitors of said memory cells being disposed in rows; said active regions being disposed respectively between two of said trench capacitors of said memory cells; a connecting line electrically conductively connecting two second terminal regions of two of said selection transistors of adjacent ones of said rows to one another and forming a common terminal region for two of said trench capacitors of different rows; and a contact bit terminal: being electrically conductively connected to said common terminal region; and being electrically conductively connected to a bit line.