Patent ID: 6061358
Filing Date: 2000-05-09
Classification: G06F,H04L

Abstract:
A memory controller comprising:a dual port memory coupled to a time division multiplexed input bus for receiving data frames from a plurality of system ports, said dual port memory also being coupled to a time division multiplexed output bus for delivering said data frames to other ones of said plurality of system ports, said dual port memory comprising a plurality of N-byte buffers; anda switch controller coupled to said dual port memory for establishing a number of data queues therein comprising dynamically designated subsets of said plurality of N-byte buffers sufficient to store said data frames from a number of transmitting ones of said plurality of system ports having at least one data frame intended for a designated receiving one of said other ones of said system ports, wherein at least some of the subset of buffers comprise more than one N-byte buffer;said switch controller designating whether each of said N-byte buffers is an only, first, middle or last buffer for said at least one data frame.