Patent ID: 6639435
Filing Date: 2003-10-28
Classification: H03K

Abstract:
A frequency divider, comprising:an input terminal for receiving an input signal with a first clock frequency and an output terminal for an output signal; a state register, encompassing n bits, for storing a register state from a multiplicity of register states; a decoder connected to said state register, said decoder assigning to the register states in each case an m-bit word, a plurality of second n-bit words, and state-dependent variables; a loading device connected to said state register and configured to write, depending on an adjustable divider ratio and the state-dependent variables, one of the n-bit words to said state register at a second clock frequency corresponding to the frequency of the input signal divided by m; and a parallel-serial converter connected to said loading device for reading in the m-bit words in parallel at the second clock frequency and outputting the m-bit words serially as the output signal.