Patent ID: 7595229
Filing Date: 2009-09-29
Classification: H01G,H01L

Abstract:
1. A method of forming a combined capacitor device, comprising: forming an array of individual capacitors divided into capacitor tiles, each capacitor tile comprising at least one capacitor; forming a first plurality of first metal routing tracks over the at least one capacitor of each capacitor tile, the first metal routing tracks having an orientation that is alternated from one capacitor tile to the next; connecting said at least one capacitor of each capacitor tile to a first of said first metal routing tracks and also to a second of said first metal routing tracks; forming a second plurality of second metal routing tracks over the at least one capacitor of each capacitor tile, the second metal routing tracks crossing over the first metal routing tracks of each capacitor tile, the second metal routing tracks having an orientation that is alternated from one capacitor tile to the next; wherein some of the second metal routing tracks are connected to some of the first metal routing tracks by a plurality of vias, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor; and wherein at least some of said plurality of vias are formed where the second metal routing tracks cross over the first metal routing tracks.