Patent ID: 7995369
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: bit lines extending in a first direction; word lines extending in a second direction crossing the first direction; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part out of the surface region of the semiconductor layer, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data, wherein the semiconductor layer includes a first semiconductor region of a first conductivity type beneath the first surface region and a second semiconductor region of a second conductivity type beneath the second surface region, the first semiconductor region and the second semiconductor region form therebetween a pn junction, one of the bit line contacts is connected to the first semiconductor region, and the word-line insulating film is formed on the second semiconductor region, the semiconductor memory device further comprises a field relaxation layer arranged in the semiconductor layer between the first semiconductor region and the second semiconductor region, an impurity concentration of the field relaxation layer being lower than that of the first semiconductor region.