Patent ID: 6627971
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A device with a plurality of structures with different resistance values comprising:a silicon oxide layer formed over the substrate, a polysilicon layer formed over the silicon oxide layer, a hard masking layer formed upon the polysilicon layer, the hard masking layer including a full thickness portion of the hard masking layer and a thinner portion of the hard masking layer, the polysilicon layer having a lightly doped high resistance region with N-type or P-type dopant located beneath the full thickness portion of the hard masking layer, the polysilicon layer having a heavily doped low resistance region with N-type or P-type dopant located beneath the thinner portion of the hard masking layer, and with the high resistance region of the polysilicon layer and the low resistance region of the polysilicon layer having the same thickness and the same dopant type.