Patent ID: 8286161
Filing Date: 2012-10-09
Classification: G06F

Abstract:
1. An information processing apparatus for controlling an allocation relationship between a physical processor having a physical address and a logical processor comprising: a control operating system executing a process for allocating a plurality of logical processors to a physical processor in a time division manner; and a guest operating system for which a logical partition, having a logical partition address and one or more virtual address spaces, is set as an application entity of the logical processor, wherein the control operating system sets and updates, in computer memory, the allocation relationship between the logical processor and the physical processor, by setting and updating two address conversion tables, a first conversion table with record comprising an index for the logical partition address and the physical address of the physical processor and a second conversion table with record comprising an index for one of the one or more virtual address spaces in the guest operating system and the physical address of the physical processor, so that that a physical address acquired from an index of the first conversion table corresponding to the logical processor and a physical address acquired from an index of the second conversion table corresponding to the logical processor are the same address corresponding to the same physical processor.