Patent ID: 7355544
Filing Date: 2008-04-08
Classification: H03M

Abstract:
1. An A/D (analog-to-digital) converter comprising a pulse delay circuit controllable for being activated to commence transferring a pulse signal therethrough, comprising a plurality of delay units connected in series as successive delay stages in a ring delay line configuration, each of said delay units applying to said pulse signal an identical amount of delay with said delay amount varying in accordance with a voltage level of an analog input signal, a circulation number counter circuit for counting a number of complete circulations of said pulse signal around said pulse delay circuit, and a latch and encoder circuit controlled by an externally supplied sampling clock signal having a predetermined sampling period, for registering respective output signals produced from said delay units of said pulse delay circuit and from said circulation number counter circuit at each of respective sampling time points defined by said sampling clock signal, to thereby derive a total number of said delay units traversed by said pulse signal since a commencement of activation of said pulse delay circuit, and for producing an output A/D (analog-to-digital) converted value in accordance with said total number; wherein said A/D converter comprises a control signal generating circuit for generating, based on said sampling clock signal: an activation control signal synchronized with said sampling clock signal, for periodically inhibiting circulation of said pulse signal around said pulse delay circuit during a pause interval having a duration that is longer than a circulation period of said pulse signal and is shorter than said sampling period, and for activating said pulse delay circuit upon termination of said pause interval, and an initialization signal for initializing said circulation number counter circuit during each of said pause intervals.