Patent ID: 8420537
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A method for forming an electrical interconnect structure, comprising: providing a dielectric substrate with a trench; conformally forming an interconnect layer of Cu on said substrate and in said trench with said layer of Cu having small multiple grain size structure providing multiple grain boundaries that act as fast diffusion paths during electromigration; forming a stress locking layer directly on said layer of Cu on said substrate and in said trench to lock stress and extend an elastic region of said layer of Cu during annealing so that relaxation by surface diffusion is reduced; then annealing said layer of Cu with said stress locking layer at a temperature between 150° C. and 400° C. for between five to sixty minutes to form an interconnect layer of Cu exhibiting low tensile stress and high fiber texture structure having larger grain and columnar microstructure boundaries with said columnar microstructure boundaries oriented substantially perpendicular to the conductive path of said interconnect layer of Cu; and