Patent ID: 8242819
Filing Date: 2012-08-14
Classification: G11C,H03L

Abstract:
1. A semiconductor memory apparatus configured to employ a data clock signal that has a different frequency than a main clock signal, the semiconductor memory apparatus comprising: a clock signal receiver configured to receive the main clock signal and the data clock signal; and a phase tuner configured to: generate a frequency-divided clock signal having a same frequency as the main clock signal by dividing a frequency of the data clock signal, generate from the frequency-divided clock signal at least four multiphase frequency-divided clock signals having the same frequency as the frequency-divided clock signal and different phases from one another, compare each phase of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, and output a phase detection signal, and compare a phase of a signal selected, based on the phase detection signal, from the at least four multiphase frequency-divided clock signals with the phase of the main clock signal and output a comparison result.