Patent ID: 7989953
Filing Date: 2011-08-02
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a semiconductor substrate having source and drain regions formed therein; an intermediate routing structure to provide electrical interconnects to the source and drain regions, the intermediate routing structure including an outermost conductive layer; a passivation layer formed over the intermediate routing structure, the passivation layer having a plurality of openings positioned over a portion of the intermediate layer routing structure; an under-bump-metallization (UBM) stack including a conductive bump positioned on and directly contacting the UBM stack and laterally spaced from an opening of the plurality of openings in the passivation layer such that at least one opening of the plurality of openings is not directly under a region of contact between the conductive bump and the UBM stack and at least another opening of the plurality of openings is directly under the region of contact between the conductive bump and the UBM stack.