Patent ID: 6799233
Filing Date: 2004-09-28
Classification: G06F

Abstract:
A device comprising:a function element that is configured to provide or accept data to and from an I2C bus, and an interface, operably coupled to the function element and the I2C bus, that is configured to facilitate communication of data between the function element and the I2C bus; the interface comprising a state machine that is configured to control the interface that includes: a plurality of states including: an idle state, an address state, a load-data state, a send-data state, a clear-data state, an accept-data state, and a start state; wherein, the state machine is configured to: asynchronously enter the start state upon detection of a start signal on the I2C bus, asynchronously enter the idle state upon detection of a reset signal on the I2C bus, and upon receipt of each of a plurality of clock signals on the I2C bus: enter the address state if the state machine is in the start state, enter the load-data state if the state machine is in the address state and a read command is received from the I2C bus, enter the send-data state if the state machine is in the load-data state, enter the clear-data state if the state machine is in the address state and a write command is received from the I2C bus, and enter the accept-data state if the state machine is in the clear-data state.