Patent ID: 6746883
Filing Date: 2004-06-08
Classification: G01R

Abstract:
A method for determining interface traps in a semiconductor/oxide interface of a MOS transistor comprising a bulk substrate, a source, a drain, a gate, and a silicon oxide layer beneath the gate, the method comprising:grounding the bulk substrate, source, and drain; applying a first gate pulse having a fixed low-level gate voltage (Vgl) and an increasing high-level gate voltage (Vgh) at a high gate pulse frequency on the gate so as to obtain a first charge-pumping current ICPâˆ’Vgh curve; applying a second gate pulse having the same low-level gate voltage (Vgl) and the same increasing high-level gate voltage (Vgh) as the first gate pulse at a low gate pulse frequency on the gate so as to obtain a second ICPâˆ’Vgh curve; and subtracting the second ICPâˆ’Vgh curve from the first ICPâˆ’Vgh, curve.