Patent ID: 7606957
Filing Date: 2009-10-20
Classification: G06F

Abstract:
1. A bus system comprising: a shared resource; a shared bus; a plurality of requesters; and a bus arbiter for arbitrating access requests made by the plurality of requesters to access the shared resource through the shared bus, wherein at least one of the plurality of requesters has a cache memory and outputs, according to a cache hit rate of the cache memory, an internal state signal indicating that the priority of an access request made by that requester needs to be changed, the bus arbiter arbitrates the access requests in accordance with the internal state signal, and if a second cache hit rate, measured after an already measured first cache hit rate, is lower than a first value, which is lower than the first cache hit rate by a predetermined value, the requester having the cache memory makes the internal state signal indicate that the priority needs to be raised.