Patent ID: 8564057
Filing Date: 2013-10-22
Classification: H01L,H03K

Abstract:
1. A semiconductor device comprising: an n-type source region; a p-type body region interposed between said source region and a p-type semiconductor further region; a gate electrode which is capacitively coupled to controllably invert a portion of said body region, to controllably form therein a channel which connects said source region to said further region; wherein said further region is laterally interposed between said body region and an n-type drain region; permanent positive charge, which is embedded in at least one insulating region which adjoins said further region, and which inverts a layer of said further region in proximity to said insulating region; a shield electrode not overlapping with said gate electrode, which is at least partly interposed between said gate electrode and said drain to reduce capacitive coupling between said gate and said drain; and a dielectric-filled trench which is within said further region and vertically extends beyond said further region, and which lies at least partly beneath said gate electrode; and wherein said gate electrode and said shield electrode both have a minimum width which is more than a respective maximum vertical thickness thereof.