Patent ID: 6886093
Filing Date: 2005-04-26
Classification: G06F

Abstract:
1. A branch apparatus within a microprocessor that utilizes a fetch address to select a cache line in an instruction cache, the apparatus also using the fetch address to speculatively predict whether a branch instruction will be taken or not taken, the branch instruction potentially being present in the instruction cache line, the apparatus comprising: a first predictor, coupled to the fetch address, for predicting whether the branch instruction will be taken or not taken based on the fetch address; logic, coupled to the fetch address, for providing a binary function of the fetch address and a global branch history on an output of said logic; a second predictor, coupled to said logic output, for predicting, in parallel with said first predictor, whether the branch instruction will be taken or not taken based on said output; and a selector, coupled to the fetch address, for selecting one of said first and second predictors based on the fetch address.