Patent ID: 6697917
Filing Date: 2004-02-24
Classification: G06F

Abstract:
A processor having a prefetch function and performing processing in a plurality of modes, with which information to be decoded varies, and having an instruction to dynamically switch the plurality of modes, the processor comprising:a register storing data that contains a bit indicating a current mode; a cache memory storing cache data that represents a prefetched instruction; a purge decision circuit referring to a result of decoding in a decoding cycle, and outputting a cache purge signal to the cache memory when the result of decoding is information represented by a mode switching signal and when a signal input to the register is a write signal, thereby causing the cache memory to perform a cache purge operation of purging the prefetched instruction therefrom; and an issue circuit reading the cache data from the cache memory, checking the read cache data, and issuing output data according to a result of checking, wherein the purge decision circuit comprises a circuit outputting the cache purge signal with timing determined according to the write signal when the output data of the issue circuit includes data represented by the mode switching signal.