Patent ID: 6731553
Filing Date: 2004-05-04
Classification: G11C

Abstract:
A memory circuit with a multi-bit output configuration comprising:a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from said memory core; an output circuit provided between said output terminals and memory core, which detects whether each L-bit output of the N-bit output (N=LÃ—M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match, while becomes a third state in the event of a non-match, to a first output terminal of said N output terminals; and a test control circuit which, responding to each of a plurality of test commands, enters each one of test modes which cause said output circuit to output said compressed output for the L-bit output of a group corresponding to the test command among said M-groups of L-bit output; wherein M blocks of compressed output are outputted in time-shared from said output control circuit.