Patent ID: 6577317
Filing Date: 2003-06-10
Classification: G06T

Abstract:
A geometry processing device comprising:(A) a packet controller comprising: (1) registers receiving: data; and commands encoding the type and quantity of the received data; and (2) an interface state machine, receiving the commands, comprising: (a) logic decoding the commands to determine the number of pipeline cycles needed to execute each of the commands, each of the pipeline cycles being a specific number of clock cycles; and (b) logic generating a signal indicating the boundary between the pipeline cycles; (B) one or more instruction controllers connected in a first pipeline fashion, each instruction controller comprising: (1) a register receiving one of the commands from the previous instruction controller in the first pipeline fashion, a first of the instruction controllers receiving one of the commands from the packet controller; (2) logic decoding the received one of the commands, the decoding being specific to the particular instruction controller of the one or more instruction controllers such that the same command is decoded differently by other of the instruction controllers; (3) a jump table generating a first address; (4) a program counter comprising: (a) logic for receiving the generated first address as a current address; and (b) logic for incrementing the current address; (5) a micro-code instruction memory receiving the current address and outputting a first plurality of control bits; and (6) logic receiving the signal indicating the boundary between the pipeline cycles to determine when a new one of the command is to be received; and (C) one or more datapath units connected in a second pipeline fashion, each datapath unit corresponding to one of the pipelined instruction controllers, each datapath unit comprising: (1) one or more multiported memories receiving input data from the previous datapath unit in the second pipeline fashion, a first of the datapath units receiving the input data from the packet controller; and (2) one or more arithmetic units receiving second control bits derived at least in part from the first control bits from the corresponding instruction controller and computing output data based on the input data.