Patent ID: 6285216
Filing Date: 2001-09-04
Classification: G11C

Abstract:
An output enable circuit for an integrated circuit device, said circuit comprising:a clock buffer for receiving an external clock signal and producing an internal clock signal displaced from said external clock signal by a delay imposed by said clock buffer circuit;a reset circuit coupled to said clock buffer circuit for producing a reset clock signal displaced from said internal clock signal by a delay imposed by said reset circuit;at least one output enable logic circuit coupled to receive said internal clock signal and said reset clock signal, said output enable logic circuit producing an output enable clock signal having a first state thereof initiated on a first logic level transition of said internal clock signal and a second state thereof initiated on an opposite second logic level transition of said reset clock signal; andat least one pass gate coupled to receive said output enable clock signal and a data signal, said pass gate operative to provide said data signal to an output node when said output enable clock signal is in said first state thereof.