Patent ID: 7482661
Filing Date: 2009-01-27
Classification: G03F,Y10S

Abstract:
1. A semiconductor device comprising: a first gate wiring pattern formed on a first element region; a second gate wiring pattern formed on a second element region different from said first element region and arranged with a first space with respect to said first gate wiring pattern; a wiring pattern arranged between said first and second gate wiring patterns and formed on an element isolation region disposed between said first and second element regions; a third gate wiring pattern formed on a third element region different from said first and second element regions; a fourth gate wiring pattern formed on a fourth element region different from said first to third element regions and arranged with a second space with respect to said third gate wiring pattern, said second space being smaller than said first space, said first to fourth gate wiring patterns and said wiring pattern being formed from a same layer; a contact arranged on said wiring pattern and electrically connected to the wiring pattern; and a metal layer arranged above said wiring pattern and connected to said contact to fix a potential of said wiring pattern.