Patent ID: 6512401
Filing Date: 2003-01-28
Classification: H03K

Abstract:
A multiple drive voltage level output buffer comprising:a plurality of thick gate MOS transistors coupled in a circuit configuration; said plurality including as pull-up transistors, at least a thick gate P-channel MOS (PMOS) transistor and a thick gate N-channel MOS (NMOS) transistor, both respectively coupled between separate voltage supply voltage level ports and an output port of said output buffer; said plurality further including as pull-down transistors, at least two more thick gate NMOS transistors, both respectively coupled between ground and said output port; wherein at least one of said pull-up transistors and one of said pull-down transistors being coupled in said circuit configuration to be driven on hard and provide a high voltage swing; and wherein another of said pull-up transistors and one of said pull-down transistors being coupled in said circuit configuration to be driven on less hard and provide a reduced voltage swing.