Patent ID: 7824963
Filing Date: 2010-11-02
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit device, comprising: designing a layout for an electrical interconnect pattern adapted to connect external components with said integrated circuit device; communicating said layout for said electrical interconnect pattern to an inkjet printer; positioning a thin substrate proximate to a printing component of said inkjet printer; printing a metallic nanoink from said inkjet printer onto said thin substrate in the form of said layout for said electrical interconnect pattern; and curing said metallic nanoink such that a substantially metallic residual remains on said thin substrate, wherein said electrical interconnect pattern is part of a panel containing multiple and separate arrays covered by a molded cap and having multiple packages each, wherein said molded cap is of substantially uniform thickness over each separate array of multiple packages, and wherein said molded cap extends between each separate array of multiple packages.