Patent ID: 6797566
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A process for producing a nonvolatile semiconductor memory device, which comprises a step of forming a first conduction type well in a silicon substrate; a step of forming third gates on a first insulator film disposed on the silicon substrate; a step of forming second conduction type semiconductor regions to act as sources/drains in the well; a step of forming a second insulator film covering the third gates; a step of forming a first pattern to act as floating first gates in gaps formed between the third gates; and a step of forming control second gates on the upper surfaces of the floating first gates and the third gates, the height of the upper surfaces of the third gates thus formed being made lower than that of the upper surface of the first pattern, wherein(a) in the step of forming the third gates, a plurality of third gates are formed in a stripe shape and are formed parallel to each other; (b) in the step of forming the second conduction type semiconductor regions, the second conduction type semiconductor regions are formed on the well surface under one end of the third gates by tilted ion implantation using a plurality of stripe-shaped third gates as a mask; and (c) the step of forming the first pattern is conducted after the step of forming the second conduction type semiconductor regions.