Patent ID: 6177839
Filing Date: 2001-01-23
Classification: H03G

Abstract:
A variable gain amplifier circuit provided with an input differential circuit, a gain control differential circuit, a first load resistor, and a second load resistor, while being connected between a first power supply terminal and a first constant-current source, thus differential amplifying to be outputted a first and a second input signals in accordance with a gain control signal from a first and a second gain control terminals characterized in that:said input differential circuit provided with a first transistor whose base is connected to a first input terminal, and a second transistor whose base is connected to a second input terminal, in which respective emitters of said first and said second transistors are connected commonly to said first constant-current source;said gain control differential circuit provided with a third and a fourth transistors whose respective bases are connected to said first gain control terminal and whose respective collectors are connected to a first and a second output terminals, and a fifth, a sixth, a seventh, and a eighth transistors whose respective bases are connected commonly to said second gain control terminal, in which respective emitters of said third, fifth, and sixth transistors are connected commonly to collector of said first transistor, and respective emitters of said seventh, eighth, and fourth transistors are connected commonly to collector of said second transistor, and respective collectors of said fifth and seventh transistors are connected commonly to said first output terminal, and respective collectors of said sixth and eighth transistors are connected commonly to said second output terminal;said first load resistor is connected between said collector of said third, fifth, and seventh transistors and said first power supply terminal;said second load resistor is connected between said collector of said sixth, eighth, and fourth transistors and said first power supply terminals;respective areas of emitter region among said third and fourth transistors, said fifth and eighth transistors, and said sixth and seventh transistors are equally established mutually; andarea of emitter region of said fifth or eighth transistor is larger than area of emitter region of said sixth or seventh transistor;wherein the area of emitter region of the third transistor is equal to the sum of the areas of the emitter regions of the fifth and sixth transistors, and the area of the emitter region of the fourth transistor is equal to the sum of the areas of the emitter regions of the seventh and eighth transistors.