Patent ID: 6329244
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method of manufacturing a dynamic random access memory cell, comprising the steps of:providing a substrate having a transistor thereon;forming a first dielectric layer over the substrate;forming a plurality of bit lines over the first dielectric layer, wherein each bit line has a cap layer on top;forming a protective layer over the first dielectric layer covering the bit lines;forming a second dielectric layer over the protective layer;etching the second dielectric layer in a self-aligned process, continuing the etching through the protective layer and the first dielectric layer until the substrate is exposed so that a node contact opening and a lower electrode opening for a capacitor are formed simultaneously;depositing conductive material into the node contact opening and the lower electrode opening to form a conductive layer, wherein an upper surface of the conductive layer is slightly below an upper end of the lower electrode opening;forming spacers on interior sidewalls of the lower electrode opening above the conductive layer;etching back the conductive layer using the spacers as a mask to form a lower electrode having a recess groove above the node contact opening;removing the second dielectric layer and the spacers;forming a third dielectric layer over the lower electrode; andforming an upper electrode over the third dielectric layer.