Patent ID: 8450200
Filing Date: 2013-05-28
Classification: H01L

Abstract:
1. A method for forming an integrated circuit structure, the method comprising: providing a semiconductor substrate; forming a first dielectric layer having a first thickness over the semiconductor substrate; forming a lower portion of a contact plug substantially in the first dielectric layer; forming an etch stop layer having a second thickness over the first dielectric layer; forming a second dielectric layer over the first dielectric layer and over the etch stop layer, the second dielectric layer having a third thickness, the third thickness is between about one half and about two-thirds the sum of the first thickness, the second thickness and the third thickness; forming an upper portion of the contact plug substantially in the second dielectric layer, wherein the upper portion comprises a via filled with a first conductor material and the lower portion of the contact plug comprises a contact formed of a material different from the first conductor material, and the upper portion and the lower portion are physically connected and the contact plug is discontinuous at an interface between the upper portion and the lower portion; and forming a metallization layer over the second dielectric layer, wherein the metallization layer comprises a metal line electrically connected to the upper portion of the contact plug.