Patent ID: 8716833
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first upper electrode on an insulating interlayer through which a capacitor contact is interposed, the first upper electrode having an opening that exposes the capacitor contact; forming a first dielectric layer pattern on an inner wall of the first upper electrode that at least partly defines the opening; forming a lower electrode on the first dielectric layer pattern and on the capacitor contact; forming a second dielectric layer pattern on the lower electrode and on the first dielectric layer pattern, wherein at least a portion of the second dielectric layer pattern is within the opening; and forming a second upper electrode on a portion of the second dielectric layer pattern and on the first upper electrode, wherein the portion of the second dielectric layer pattern is within the opening, and the second upper electrode contacts the first upper electrode.