Patent ID: 6141741
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A computer system, comprising:a shared address/data bus;an input/output device address bus;a memory system directly connected to said shared address/data bus;an input/output device directly connected to said shared address/data bus and, said input/output device address bus; anda bus controller to generate;an address transfer sequence including a first cycle with high order address bits that are launched on said shared address/data bus and said input/output device address bus and a second cycle with low order address bits that are launched on said shared address/data bus and mask bits that are launched on said input/output device address bus, said mask bits specifying one of a predetermined set of data field formats, wherein said bus controller generates a sequence of write requests during said address transfer sequence before receiving a write acknowledgment, anda data transfer sequence executed after a latency period following said address transfer sequence, said data transfer sequence including the launch of a plurality of data bits on said shared address/data bus for selective processing by said memory system or said input/output device.