Patent ID: 6510094
Filing Date: 2003-01-21
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks; a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks; a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed, said conjunction areas comprising: one or more LA drivers adapted to drive block sense amplifiers; one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers; and one or more BSYD circuits adapted to selectively enable LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining block column and row address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.