Patent ID: 7186618
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. A method for fabricating a power transistor arrangement, comprising: providing a cell array in a semiconductor substrate including a substrate surface; providing a plurality of cell array trenches and at least one connecting trench connected to the plurality of cell array trenches within the cell array, wherein the width of each of the plurality of cell array trenches is greater than the width of the at least one connecting trench, and wherein the plurality of cell array trenches and at least one connecting trench extend below the substrate surface; providing an insulating layer on the substrate surface and in the plurality of cell array trenches and at least one connecting trench; applying a first conductive layer to the insulating layer; at least partially removing the first conductive layer, wherein the first conductive layer forms a field electrode structure; applying a conductive auxiliary layer to the insulating layer and the first conductive layer, wherein the at least one connecting trench is filled with the conductive auxiliary layer and the plurality of cell array trenches are lined with the conductive auxiliary layer; removing the conductive auxiliary layer from the plurality of cell array trenches and at least partially removing the conductive auxiliary layer in the at least one connecting trench; and forming a gate electrode structure in the plurality of cell array trenches; wherein the field electrode structure contacts a region of the at least one connecting trench, and wherein the at least one connecting trench connects the plurality of cell array trenches.