Patent ID: 6587982
Filing Date: 2003-07-01
Classification: G01R,G11C

Abstract:
A tester interface circuit for use with a BIST state machine so as to enable cycling through a BIST test comprising:memory means for storing data inputted by a user and for generating output register signals corresponding to which tests are to be executed by the BIST state machine; logic decoding means responsive to status signals from the BIST state machine for determining which particular register in a shift register is to be set or cleared; a set/clear mechanism responsive to a completed signal indicating that a particular has been completed, a failed signal indicating that a particular test has failed, and a pass signal indicating that a particular test is to be bypassed for generating a set/clear signal; said shift register formed of a plurality of registers and being responsive to said logic decoding means and said set/clear signal for storing the results of the test currently being executed; and polling logic means responsive to a busy signal for indicating that a test is currently being executed and that the BIST state machine is busy.