Patent ID: 6765261
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A semiconductor device comprising a semiconductor body having a surface region of a first conductivity type which borders on a surface and which is provided with a non-volatile memory in the form of a matrix of memory cells which are arranged in rows and columns, each memory cell comprising a MOS transistor having a source, a drain, a channel region situated between the source and the drain, and a gate which is situated above the channel region and which is electrically insulated from said channel region by an intermediate gate dielectric which is provided with a charge-storage region wherein data in the form of electric charge can be stored, each column comprising two zones of the opposite, second, conductivity type, which extend throughout the length of the column and which form a common source and drain for the memory cells in the column such that one memory cell is formed between every pair of source and drain lines in each row of memory cells, and the surface being covered with a number of adjacent word lines in the form of conductor tracks extending over the surface in a direction parallel to the rows, and each word line being coupled to the gates of row of memory cells, characterized in that the channel regions of memory cells in two adjacent rows are separated from each other only by intermediate parts of the surface region of the first conductivity type, the distance between these channel regions as well as the distance between the associated word lines being small in comparison with the width of the channel region and the width of the word line which has a minimum photolithographic dimension F, respectively, wherein at a minimum photolithographic dimension F, the minimum size of a cell is approximately 2F2.