Patent ID: 6320230
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method of protecting a circuit during an ESD event, the circuit including an MOS transistor of an output buffer on a semiconductor substrate, the MOS transistor being of a first conductivity type while said semiconductor substrate is of a second conductivity type, said method comprising the steps of:providing a plurality of wells formed in said semiconductor substrate, said plurality of wells being of said first conductivity type;forming a first doped region in said semiconductor substrate connected to a circuit node, said first doped region being of said first conductivity type;forming a plurality of doped regions in said wells, the doped regions in the wells being of said second conductivity type;forming a second doped region spaced apart from said wells, wherein the wells are formed in said semiconductor substrate such that they are symmetrical with reference to said second doped region and wherein the doped regions in the wells and the second doped region are connected to an output pad; andforming a gate structure overlaying a portion of said semiconductor substrate between said first doped region and said second doped region and being coupled to an internal circuit;wherein said first doped region, said plurality of wells, the semiconductor substrate, and said first doped region constitute a silicon-controlled rectifier, and said first and second doped regions and said gate structure constitute said MOS transistor, andsaid MOS transistor is configured with a T-shape layout.