Patent ID: 7299343
Filing Date: 2007-11-20
Classification: G06F

Abstract:
1. A processor, comprising: an instruction unit configured to process a conditional execution instruction and at least one target instruction, wherein the conditional execution instruction specifies the at least one target instruction, a register, and a condition within the register; an execution unit operably coupled to the instruction unit and configured to execute the conditional execution instruction and unconditionally execute the at least one target instruction, but to save a result of the at least one target instruction only if the result of the at least one target instruction is qualified by the existence of the specified condition in the specified register during execution of the conditional execution instruction; and wherein in the event the conditional execution instruction specifies a first flag register, the execution unit is configured to copy a value of a plurality of flag bits in the first flag register to a corresponding second plurality of flag bits in a second flag register, and to save a result of the at least one target instruction dependent upon the specified condition in the first flag register during execution of the conditional execution instruction, wherein the first flag and second flag registers are dedicated flag registers.