Patent ID: 7242628
Filing Date: 2007-07-10
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a memory cell array that is provided with a plurality of memory cells; sense amplifiers for reading data that have been stored in said memory cells; bit lines for connecting said memory cells and said sense amplifiers; and transfer gates that are inserted on said bit lines for turning on/off connections between said memory cells and said sense amplifiers; wherein sense-amplifier-interior bit lines, which comprise the bit lines that are on the side of said sense amplifiers from said transfer gates, are arranged at positions interposed between exterior bit lines, which are the bit lines that comprise on the side of said memory cells from said transfer gates, and wherein a sense-amplifier-interior bit line connected to one sense amplifier is arranged at a position interposed between said exterior bit lines each connected to a different sense amplifier.