Patent ID: 8081719
Filing Date: 2011-12-20
Classification: H03M,H04L

Abstract:
1. A method for signal processing, the method comprising: determining a plurality of candidate bit sequences based on a decoded portion of a bit sequence; generating a candidate decoded bit sequence based on said decoded portion of said bit sequence for each of said plurality of candidate bit sequences; computing a verification parameter value for each of said plurality of candidate decoded bit sequences; comparing each of said computed verification parameter values to a received verification parameter value; selecting at least a portion of said plurality of candidate decoded bit sequences based on said comparing; selecting one of said at least a portion of said plurality of candidate decoded bit sequences based on one or more physical constraint tests; generating a frame bit sequence based on said decoded portion of said bit sequence and said selected one of said at least a portion of said plurality of candidate decoded bit sequences; and selecting said one of said plurality of candidate decoded bit sequences for inclusion among said selected at least a portion of said plurality of candidate decoded bit sequences when a corresponding one of said plurality of computed verification parameter values is equal to said received verification parameter value.