Patent ID: 6510501
Filing Date: 2003-01-21
Classification: G06F

Abstract:
A memory system, comprising:a programmable non-volatile memory to contain a security indication and program instructions; a register; memory interface logic circuitry responsive to the contents of the register to selectively allow access by a processor to the memory; security indication copying circuitry that receives a reset signal for the memory system and, in response to the reset signal, causes the security indication to be copied into the register as the contents thereof, and wherein the security indication includes a first indication for security of write access to the memory and a second indication for security of read access to the memory, and wherein the first indication and the second indication are independently controllable, and wherein the memory interface logic circuitry allows erase access to the security indication in the memory only if the first indication ad the second indication are such that both write access and read access to the memory are enabled.