Patent ID: 6465354
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device comprising the steps of:forming an insulation layer on a semiconductor substrate, wherein said insulation layer comprises a first portion having a plurality of trench-parts before forming a metal plating layer on the whole surface of the insulation layer including the trench-parts so as to embed a metal in said plurality of trench-parts and wherein the formation of said metal plating layer is implemented according to an electrolytic plating method in which a pulse power source is employed, and whose current value is in a range of about 2 to about 5 A/dm2, wherein said first portion comprises a dense pattern of trench-parts; annealing so as to cause a grain-size of the metal embedded in the trench-parts and the metal plating layer of said first portion to be smaller than a grain-size of the metal plating layer not in said first portion; and polishing the metal plating layer and the insulation layer to produce a flattened surface.