Patent ID: 6239011
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method for forming a self-aligned contact to a semiconductor element adjacent to a gate electrode of a MOSFET comprising:(a) providing a silicon wafer having a vertical walled gate stack with a silicon nitride insulative cap, a silicon nitride sidewall, and an active semiconductor element within the surface of said silicon wafer adjacent to said sidewall;(b) depositing a first insulative layer over said silicon wafer;(c) depositing a second insulative layer on said first insulative layer;(d) planarizing said second insulative layer;(e) depositing a photoresist layer over said second insulative layer;(f) patterning said photoresist layer to define a contact opening which extends over said sidewall and partially over said cap;(g) etching said second insulative layer and said first insulative layer in an RIE etching tool in an rf plasma containing an etchant mixture of octafluorocyclobutane and CH.sub.3 F, in an argon carrier gas, at a flow rate to maintain a chamber pressure of between about 2 and 10 millitorr, while adding a flow of O.sub.2 to said etchant mixture to maintain and control a sufficient steady state thickness of a polymer, which forms on surfaces of said cap and said sidewall exposed by said etching, to achieve a silicon oxide/silicon nitride etch rate ratio of about 20:1, while not obstructing said etching by polymer bridging, thereby forming a contact opening which is self-aligned to said sidewall;(h) removing residual said polymer and said photoresist layer; and(i) depositing a conductive material into said contact opening, thereby forming a self-aligned contact.