Patent ID: 8872301
Filing Date: 2014-10-28
Classification: H01L

Abstract:
1. A semiconductor device utilizing shallow trench isolation (STI), comprising: a semiconductor substrate having a first semiconductor device, a second semiconductor device and a third semiconductor device disposed thereon; an active area disposed on the semiconductor substrate, and having at least the first semiconductor device disposed therein; a periphery area disposed on the semiconductor substrate separate from the active area, and having at least the second semiconductor device disposed therein, the second semiconductor device connected to and controlling the first semiconductor device; a first STI trench bounding at least a portion of the active area, a portion of the first STI trench disposed between the first semiconductor device and the second semiconductor device, the first STI trench at least partially isolating the first semiconductor device from at least the second semiconductor device and third semiconductor device; and a second STI trench bounding at least a portion of the periphery area, a portion of the second STI trench disposed between the first semiconductor device and the second semiconductor device, wherein the second STI trench has a depth substantially deeper than the first STI trench and wherein the second STI trench isolates the second semiconductor device from at least the third semiconductor device.