Patent ID: 8237649
Filing Date: 2012-08-07
Classification: G09G

Abstract:
1. A liquid crystal driving device comprising: a scanning line driving circuit employed in conjunction with a data line driving circuit, the scanning line driving circuit being configured to supply switching elements included in respective pixels corresponding respectively to intersections of a plurality of scanning lines and a plurality of data lines of a liquid crystal panel with signals for performing switching control of the switching elements through the plurality of scanning lines, the data line driving circuit being a circuit configured to supply the switching elements with signals corresponding to tones of the pixels through the plurality of data lines, the scanning line driving circuit including, for each of the plurality of scanning lines, a first series circuit having a first PMOSFET and a first NMOSFET connected in series, both ends thereof being connected respectively to a point of first potential and a point of second potential, the first series circuit being configured to receive at a gate of the first PMOSFET a binary signal having two levels not higher than a level of the first potential and higher than a level of the second potential, a second series circuit having a second PMOSFET and a second NMOSFET connected in series, both ends thereof being connected respectively to a point of third potential higher than the first potential and a point of the second potential, a gate of the second NMOSFET being connected to a connection point of the first PMOSFET and the first NMOSFET, and a CMOS inverter circuit, the CMOS inverter circuit being applied with a voltage between the second potential and the third potential as a power supply voltage and configured to receive a voltage of a connection point of the second PMOSFET and the second NMOSFET, a gate of the first NMOSFET being applied with a predetermined first bias voltage adapted such that the second NMOSFET is turned ON or turned OFF in response to a level of the binary signal, and a gate of the second PMOSFET being applied with a predetermined second bias voltage adapted such that the second PMOSFET becomes higher in on-resistance than the second NMOSFET.