Patent ID: 7138676
Filing Date: 2006-11-21
Classification: H01L

Abstract:
1. A semiconductor device in which a plurality of rows are set along an X direction and a plurality of columns are set along a Y direction orthogonal to the X direction, comprising: a first element region including a first trench disposed in a first column at one end thereof and a second trench disposed in a second column parallel to the first column at the other end thereof; a second element region including a third trench disposed at a position closer to the second trench than the first trench in the first column at one end thereof and a fourth trench disposed in the second column at the other end thereof; a third element region including a fifth trench disposed at a position closer to the fourth trench than the third trench in the first column at one end thereof and a sixth trench disposed in the second column at the other end thereof; first to sixth trench capacitors are formed in the first to sixth trenches, respectively; a first memory cell which includes the first trench capacitor and is disposed in the first column; a second memory cell which includes the second trench capacitor and is disposed in the second column; a first bit line contact which is provided in the first element region and shared by the first and second memory cells; a third memory cell which includes the third trench capacitor and is disposed in the first column; a fourth memory cell which includes the fourth trench capacitor and is disposed in the second column; a second bit line contact which is provided in the second element region and shared by the third and fourth memory cells; a fifth memory cell which includes the fifth trench capacitor and is disposed in the first column; a sixth memory cell which includes the sixth trench capacitor and is disposed in the second column; a third bit line contact which is provided in the third element region and shared by the fifth and sixth memory cells; a first bit line connected mutually to the first and second bit line contacts; and a second bit line connected to the third bit line contact, wherein the first element region includes an oblique portion obliquely crossing toward the second column from the first column between the first and second memory cells, the second element region includes an oblique portion obliquely crossing toward the second column from the first column between the third and fourth memory cells, the third element region includes an oblique portion obliquely crossing toward the second column from the first column between the fifth and sixth memory cells, the first bit line contact is in the oblique portion of the first element region, the second bit line contact is in the oblique portion of the second element region, the third bit line contact is in the oblique portion of the third element region, the first to third bit line contacts are disposed in a straight line along the Y direction between the first and second columns, the first bit line is one of a folded and twisted bit line pair, the second bit line is the other of folded and twisted bit line pair, and the first bit line intersects with the second bit line between the second and third bit line contacts.