Patent ID: 7334065
Filing Date: 2008-02-19
Classification: G06F,H04L

Abstract:
1. A method comprising: a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second n-bit parallel data buses, respectively, coupled thereto; the receiving circuit comparing first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion; the receiving circuit storing into a first FIFO buffer, all first-stream multibit data portions that follow the identified first-stream multibit data portion; the receiving circuit comparing second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion; the receiving circuit storing into a second FIFO buffer, all second-stream multibit data portions that follow the identified second-stream multibit data portion; concatenating second-stream multibit data portions stored in the second FIFO buffer with respective first-stream multibit data portions stored in the first FIFO buffer to form multibit data lines; transmitting the multibit data lines via a 2n-bit parallel data bus.