Patent ID: 7187581
Filing Date: 2007-03-06
Classification: G11C,H01L

Abstract:
1. A semiconductor memory array, comprising: a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes at least one transistor having: wherein the body region is electrically floating; and wherein each memory cell includes (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and wherein the source region of the transistor of each memory cell corresponding to a first row of semiconductor dynamic random access memory cells and a second row of semiconductor dynamic random access memory cells is connected to a first source line, and wherein the first and second rows of memory cells are adjacent rows and the gate of the transistor of each memory cell corresponding to the first row of semiconductor dynamic random access memory cells is connected to a first word line and the gate of the transistor of each memory cell corresponding to the second row of semiconductor dynamic random access memory cells is connected to a second word line; and wherein one or more predetermined memory cells of the first row are programmed to the second data state by programming each memory cell of the first row to the first data state and thereafter programming the one or more predetermined memory cells of the first row to the second data state.