Patent ID: 8357568
Filing Date: 2013-01-22
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit package, the method comprising: attaching a first surface of a die to a conductive substrate, the die having at least one side surface; forming at least one die connector on a second surface of the die, the second surface opposing the first surface; encapsulating the at least one side surface of the die and a portion of the second surface of the die with an encapsulant material, wherein the encapsulant material comprises a single continuously disposed unitary material; planarizing an area of the encapsulant material greater than an area of a surface of the at least one die connector to expose the surface of the at least one die connector while the at least one side surface of the die and the portion of the second surface of the die remain encapsulated; forming at least one conductive trace on the planarized area, wherein the at least one conductive trace is characterized by a first portion in electrical communication with one of the at least one die connector and a second portion in electrical communication with a package connector; forming an insulating layer over the planarized area; and forming at least one second-level conductive trace on the insulating layer, the at least one second-level conductive trace being insulated from the at least one conductive trace and in communication with at least one die connector, thereby forming an integrated circuit package with multi-layer routing.