Patent ID: 8432755
Filing Date: 2013-04-30
Classification: G11C

Abstract:
1. An integrated circuit memory device, comprising: an array of memory cells electrically coupled to a plurality of word lines; a word line driver circuit electrically coupled to the plurality of word lines, said word line driver circuit comprising a variable-width pulse generator containing a first delay unit therein, said word line driver circuit configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit and further configured to drive the selected one of the plurality of word lines with a second word line signal having a leading edge synchronized with the leading edge of a clock signal and a trailing edge synchronized with an edge of a signal generated by the first delay unit when the one-half period of the clock signal is less than the length of the delay provided by the first delay unit.