Patent ID: 6501114
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A structure of memory array and peripheral circuitry, comprising:a substrate having a memory array region and a peripheral circuitry region; a pair of adjacent memory transistor gates associated with the memory array region of the substrate; a pair of adjacent peripheral transistor gates associated with the peripheral region of the substrate, the adjacent peripheral transistor gates being further apart than the adjacent memory transistor gates, a plurality of spacers comprising a layer of silicon oxide between a pair of silicon nitride layers, some of the spacers being between the adjacent memory transistor gates, and others of the spacers being between the adjacent peripheral transistor gates; individual spacers between the adjacent memory transistor gates comprising a same composition and lateral width as one another, and as individual spacers between the adjacent peripheral transistor gates; and source/drain regions proximate the peripheral transistor gates and spaced from the peripheral transistor gates by more than the lateral width of the spacers between the peripheral transistor gates. 2.The structure of claim 1 wherein the layer of silicon dioxide comprises a thickness of about 600 angstroms.