Patent ID: 8566774
Filing Date: 2013-10-22
Classification: G06F

Abstract:
1. A method for optimized buffer placement based on timing and capacitance assertions in a functional chip unit comprising a single source and multiple macros, each having a sink, wherein the placement of the source and the macros with the sinks is pre-designed and the buffers are placed in branches connecting the source with the multiple sinks, the method comprising: calculating, by a processor, an estimated slack for each branch of the branches, arranging the branches according to the calculated slack to evaluate at least one most critical branch of the branches, inserting decoupling buffers in each branch of the branches except for the at least one most critical branch, wherein the inserted decoupling buffers are placed close to the source, globally routing the at least one most critical branch and fixing slew conditions within this branch, subsequently, globally routing at least one next branch of the branches as arranged according to the calculated slack and fixing slew conditions within this at least one next branch, wherein globally routing the at least one next branch comprises: routing at least one remaining branch of the branches.