Patent ID: 8929156
Filing Date: 2015-01-06
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a logic stage configured to perform an ANDing operation on a read command and a external clock and output an output signal; a driving stage configured to drive a first node in response to the output signal of the logic stage; a latch stage configured to latch a signal of the first node and output a clock control signal; a reset stage configured to pull-up drive the first node in response to a reset signal; a clock generating section configured to buffer the external clock during a period when the clock control signal is enabled in response to a test mode signal and generate an internal clock; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode, wherein the internal clock is generated as period pulses at a time when the read command is inputted after the test mode is entered.