Patent ID: 8130777
Filing Date: 2012-03-06
Classification: H04J,H04L

Abstract:
1. A link layer device configured for processing data associated with a plurality of links including a plurality of ingress links and a plurality of egress links, the device comprising: an ingress data clock processor configured to generate ingress clock signals for processing data associated with respective ones of said ingress links; an egress data clock processor configured to generate egress clock signals for processing data associated with respective ones of said egress links; and a control and configuration unit shared by the ingress data clock processor and the egress data clock processor; wherein the control and configuration unit comprises a scheduler configured to control update operations for multiple phase-locked loops in each of the ingress and egress data clock processors; and wherein the scheduler in controlling the update operations for the multiple phase-locked loops in each of the ingress and egress data clock processors controls a plurality of arithmetic logic units each of which implements at least respective portions of a plurality of the phase-locked loops in one of the ingress and egress data clock processors, said arithmetic logic units each processing respective assigned ones of the plurality of ingress links and the plurality of egress links for its associated plurality of phase-locked loops in a sequential fashion under control of the scheduler.