Patent ID: 8901968
Filing Date: 2014-12-02
Classification: H02J,H03K

Abstract:
1. An active circuit comprising a first terminal and a second terminal, the first terminal and the second terminal to receive corresponding voltages for operation of the active circuit, the circuit comprising: a first MOS transistor having a first current terminal coupled to the second terminal, a second current terminal coupled to the first terminal, and a control terminal coupled to the first terminal; a second MOS transistor having a first current terminal coupled to the second terminal and a control terminal coupled to the control terminal of the first MOS transistor; a third MOS transistor having a first current terminal coupled to a second current terminal of the second MOS transistor, a control terminal coupled to the first current terminal of the third MOS transistor, and a second current terminal coupled to a constant reference potential node; and a fourth MOS transistor having a first current terminal coupled to the constant reference potential node, a control terminal coupled to the control terminal of the third MOS transistor, and a second current terminal; wherein the second terminal is coupled to receive a power supply voltage generated by a first supply, wherein the first terminal is coupled to receive a chip-enable signal generated by a component powered by a second supply, wherein the second current terminal of the fourth MOS transistor is coupled to a path on which the chip-enable signal is generated.