Patent ID: 6043680
Filing Date: 2000-03-28
Classification: H03K

Abstract:
A method of providing a high impedance at an output node of a tristate input/output buffer, comprising:providing, in series with a power supply and a first p-channel transistor and an output node of said input/output buffer, a second p-channel transistor;back-biasing a parasitic diode of said second p-channel transistor by connecting a source and substrate of said second p-channel transistor to said output node; andproviding means to turn on/off said second p-channel transistor when said input/output buffer is enabled/not enabled, by the steps of:forcing a third p-channel transistor off when said input/output buffer is enabled and thus turning on a second n-channel transistor, thereby pulling down the gate of said second p-channel transistor, causing said second p-channel transistor to turn on; andforcing said third p-channel transistor on when said input/output buffer is not enabled, thereby shorting said gate and the source of said second p-channel transistor, causing said second -channel transistor to turn off.