Patent ID: 9070667
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A semiconductor die package, comprising: a first semiconductor die with a first device region, a first major surface, a second major surface, and a sidewall surface connecting the first major surface and the second major surface, and a first through sidewall via (TsV) formed therein, wherein the first TsV is separated from the device region, and wherein the first TsV has a first end at the first major surface of the first semiconductor die that is laterally displaced from the sidewall surface of the first semiconductor die and has a second end at the second major surface of the first semiconductor die that is laterally immediately adjacent the sidewall surface of the first semiconductor die; a first conductive structure formed over the first semiconductor die, wherein the first conductive structure is electrically connected to devices in the first device region and physically contacts the first end of the first TsV of the first semiconductor die; and a second conductive structure formed over a surface on the opposite side of the first semiconductor die from the first conductive structure, wherein the second conductive structure contacts the second end of the first TsV of the first semiconductor die.