Patent ID: 8952435
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A memory cell transistor structure, comprising: a substrate, said substrate comprising a trench structure, said trench structure comprising an oxide layer formed on an inner surface of said trench structure and a conductive member which at least partially occupies the inner space of said trench structure; one or more dielectric layers formed on top of said substrate, said dielectric layers covering said trench structure and said conductive member therein; one or more first conductive layers formed on top of said dielectric layers; and one or more second conductive layers formed on top of said first conductive layers, wherein material of said one or more second conductive layers are different to material of said one or more first conductive layers; wherein said first and second conductive layers function as a bit line associated with said memory cell transistor structure, and said bit line is composed of said first and second conductive layers; a hole structure is formed from a top surface of said first conductive layer, extending only through said first conductive layer and said dielectric layers, and reaching a surface of said substrate, but said hole structure does not extend through said bit line completely; and wherein said material of said second conductive layer fills said hole structure.