Patent ID: 7956403
Filing Date: 2011-06-07
Classification: H01L

Abstract:
1. A flash memory comprising: a substrate having a protrusion extending from a top face of the substrate; a control gate, formed on the protrusion of the substrate and extendedly covering two opposite sidewalls of the protrusion; two floating gates, formed on top of the protrusion and being on two opposite sides of the control gate respectively; a dielectric layer, sandwiched by the control gate and each of the two floating gates; a source and a drain, formed on two opposite sides of the protrusion respectively and each being adjacent to one of the two floating gates; and a plurality of isolation structures, formed on two opposite sides of the protrusion to sandwich therebetween the source and the drain, wherein a top surface of the isolation structures is coplanar with that of the two floating gates.