Patent ID: 6091633
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A memory system formed on a substrate, comprising:a plurality of elongated source and drain diffusions spaced apart in a first direction across the substrate and with lengths extending in a second direction across the substrate, the first and second directions being orthogonal with each other,a plurality of memory cells arranged in a plurality of columns extending in the first direction across source and drain diffusions that are a part of the cells, the columns of memory cells being spaced apart in the second direction,a plurality of elongated word lines having their lengths extending in the second direction and individually spaced apart in the first direction to overlay individual rows of memory cells to enable their selection,a plurality of elongated bit selection lines having their lengths extending in the first direction and individually spaced apart in the second direction to overlay a column of memory cells to enable their selection,a plurality of elongated global bit lines having their lengths extending in the first direction and being spaced apart in the second direction with a plurality of columns of memory cells therebetween,wherein the source and drain diffusions are segmented along their lengths to individually extend between two global bit lines and be connectable to only one of said two global bit lines through at least one pass transistor having a control terminal connected with at least one of the word lines,a plurality of memory cell reading sense amplifiers connectable to the global bit lines, anddecoder circuits connected to apply voltages to the word and bit selection lines to read at least one memory cell at a time between said two global bit lines or to simultaneously program a plurality of memory cells extending along a selected row across multiple global bit lines.