Patent ID: 7372161
Filing Date: 2008-05-13
Classification: H01L

Abstract:
1. An integrated circuit chip comprising: a silicon substrate; an ESD circuit in or on said silicon substrate; an internal circuit in or on said silicon substrate, wherein said internal circuit comprises a MOS device; a dielectric layer over said silicon substrate; a first metallization structure over said silicon substrate and in said dielectric layer, wherein said first metallization structure is connected to said ESD circuit; a second metallization structure over said silicon substrate and in said dielectric layer, wherein said second metallization structure is connected to said internal circuit; a passivation layer over said dielectric layer; a first via in said passivation layer, wherein said first via is connected to said first metallization structure; a second via in said passivation layer, wherein said second via is connected to said second metallization structure; and a third metallization structure over said passivation layer, wherein said third metallization structure is connected to said first and second vias, wherein said ESD circuit is connected to said internal circuit through, in sequence, said first metallization structure, said first via, said third metallization structure, said second via and said second metallization structure, and wherein said third metallization structure comprises a metal line having a sheet resistance of smaller than 7 milliohms per square, said metal line comprising an adhesion/barrier layer, a seed layer on said adhesion/barrier layer and an electroplated metal layer on said seed layer, wherein the material of said electroplated metal layer is the same as that of said seed layer, wherein an undercut with an edge of said adhesion/barrier layer recessed from an edge of said electroplated metal layer is between 0.03 and 2 micrometers.