Patent ID: 8395430
Filing Date: 2013-03-12
Classification: H03L

Abstract:
1. A digital phase locking loop, comprising a trigger and a delay line, wherein the delay line comprises a first delay element and a second delay element; the trigger, configured to sample a signal of a selection end of the first delay element by using a delayed clock signal, and output the sampled signal to a selection end of the second delay element, wherein the selection end of the first delay element is in a gating state before triggering of the trigger, the selection end of the second delay element is in the gating state after triggering of the trigger, a trigger end of the trigger is connected to an output end of the delay line, an input end of the trigger is connected to the selection end of the first delay element, and an output end of the trigger is connected to the selection end of the second delay element; and the delay line, configured to receive a clock input signal, and output the delayed clock signal according to an order of delay; before triggering of the trigger delay, delay the clock input signal according to the order of the delay corresponding to the first delay element, to obtain the delayed clock signal; and, after triggering of the trigger, delay the clock input signal according to the order of the delay corresponding to the second delay element, to obtain the delayed clock signal.