Patent ID: 9009554
Filing Date: 2015-04-14
Classification: G01R,G06F,H04L

Abstract:
1. An integrated circuit comprising: (A) a first test clock lead, a second test clock lead, a test mode select lead, a test data in lead, and a test data out lead; (B) a first test access port having a clock input connected to the first test clock lead and being free of the second test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the first test access port having class T0-T2 capabilities and being free of any topology selection logic; and (C) a second test access port having a clock input connected to the second test clock lead and being free of the first test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the second test access port having class T0-T2 capabilities and including topology selection logic.