Patent ID: 6214630
Filing Date: 2001-04-10
Classification: G01R,H01L

Abstract:
A wafer level IC structure, which comprises:a semiconductor wafer;a plurality of discrete IC blocks defined on the wafer, each IC block including:a plurality of IC components and backup components;a multi-layer interconnect structure for electrically interconnecting the IC components in the associated IC block;a first set of bonding pads which are electrically connected to the multilayer interconnect structure and serve as external connecting points for the IC components in the associated IC block and for use during testing;a first set of fuses which are electrically connected to the IC components and the multi-layer interconnect structure for use to selectively disconnect the associated IC components from active use if the associated IC components are determined to be inoperative during testing;a redistribution line structure including a plurality of redistribution lines which are electrically connected to the first set of bonding pads of each of the IC blocks in a predefined manner so as to functionally combine the discrete IC blocks into an integral functional unit;a second set of bonding pads which are electrically connected to the IC blocks and the redistribution line structure for use to apply test signals to the IC blocks during testing; anda second set of fuses which are electrically connected to the redistribution line structure for use to selectively disconnect the associated IC blocks if the associated IC blocks are determined to be inoperative during testing.