Patent ID: 9214469
Filing Date: 2015-12-15
Classification: G11C,H01L

Abstract:
1. A semiconductor memory circuit comprising: a first transistor element composed of an insulated gate FET having a gate electrode connected to a memory node, a drain electrode connected to an intermediate node, and a source electrode connected to a data I/O terminal; a second transistor element composed of an oxide semiconductor insulated gate FET having a gate electrode connected to a first control terminal, a drain electrode connected to the intermediate node, and a source electrode connected to the memory node; a capacitive element having one end connected to a first voltage terminal, and the other end connected to the memory node; and a switching element for controlling a conducting state between one of a second control terminal, a second voltage terminal, and the first voltage terminal, and the intermediate node, based on a voltage level of at least the second control terminal; wherein, the switching element is one of: a third transistor element composed of an insulated gate FET having a gate electrode connected to the second control terminal, a drain electrode connected to one of the second voltage terminal and the first voltage terminal, and a source electrode connected to the intermediate node; a fourth transistor element composed of an insulated gate FET having a gate electrode and a drain electrode each connected to the second control terminal, and a source electrode connected to the intermediate node; and a diode element in which one of an anode terminal and a cathode terminal is connected to the second control terminal, and the other is connected to the intermediate node.