Patent ID: 6148318
Filing Date: 2000-11-14
Classification: G06F

Abstract:
A square root extraction circuit for calculating binary input data (0.a(1) a(2) a(3) . . . a(n)) using a square root extraction algorithm to output binary square root data (0.q(1) q(2) q(3) . . . q(m)), said square root extraction algorithm including an algorithm for determining said square root data on the basis of said input data by only additions of square root partial data q(1) to q(m) in q(1) to q(m) order, said algorithm having preceding digit based operation portions for performing operations to output said square root partial data q(2) to q(m) by using said square root partial data q(1) to q(m-1) provided in their preceding digit positions as operation parameters, said square root extraction circuit comprising:first to mth digit calculating portions including at least first to mth adder groups, respectively, each of said first to mth adder groups including a plurality of adders connected in series so that carries are propagated therethrough, wherein respective ones of said adders which are connected in the last position in said first to (p-1)th digit calculating portions (2.ltoreq.p.ltoreq.m) provide carry outputs serving as said square root partial data q(1) to q(p-1), respectively, in accordance with said square root extraction algorithm, and wherein said preceding digit based operation portions of said pth to mth digit calculating portions include carry output prediction circuits for performing logic operations based on the carry outputs from respective ones of said adders which are connected in the last position in the adder groups thereof and said square root partial data q(p-1) to q(m-1) provided in their preceding digit positions to output said square root partial data q(p) to q(m), respectively.