Patent ID: 9026961
Filing Date: 2015-05-05
Classification: G06F

Abstract:
1. A computer-implemented method for performing race logic synthesis on an ESL (electronic system level)-based IC (integrated circuit) design, comprises using a computer to perform one or more of the following steps: (a) Compiling, by computer, an IC design source files, coded in any one or a combination of ESL and any HDL (hardware description language) description languages, into a design database; (b) Performing static and/or dynamic race logic analysis of the IC design, either by a host application, or by an external race logic audit tool, or the combination of both; (c) Determining the execution order of process blocks of the IC design in the design database, using the default process block execution order by the host application and/or obtaining that order from user; (d) Executing the race logic synthesis functions to get rid of all race logic involving ESL IPC (inter-process communication) and IPS (inter-process synchronization) objects, as detected in (b), in the compiled IC design database; (e) As a user-specified option or a default action of the host application, generating updated ESL/HDL source files for the IC design, where race logic has been remedied by the race logic synthesis functions in (d); wherein step (d) comprises: (f) Analyzing all ESL IPC objects, including but not limited to FIFO (first-in-first-out) buffers, mailboxes and dynamic queues, in the IC design that have been determined to be involved in concurrent assignment (write) race logic, and re-synthesizing the driving process blocks of these IPC objects, to eliminate the race logic while retaining the original logic functions of the IC design; (g) Analyzing all ESL IPC objects, including but not limited to dynamic queues, in the IC design that have been determined to be involved in concurrent assignment (write) and reference (read) race logic, and re-synthesizing all the driving and driven process blocks of these IPC objects, to eliminate the race logic while retaining the original logic functions of the IC design; (h) Analyzing all ESL IPC objects, including but not limited to dynamic queues, in the IC design that have been determined to be involved in concurrent delete race logic, and re-synthesizing all the driving process blocks of these IPC objects, to eliminate the race logic while retaining the original logic functions of the IC design; (i) Analyzing all ESL IPC objects, including but not limited to FIFO buffers and mailboxes, in the IC design that have been determined to be involved in concurrent reference (read) race logic, and re-synthesizing the driven process blocks of these IPC objects, to eliminate the race logic while retaining the original logic functions of the IC design; (j) Analyzing all ESL IPS objects, including but not limited to semaphores and mutexes (mutually exclusive locks), in the IC design that have been determined to be involved in concurrent locking race logic, and re-synthesizing the driving process blocks of these IPS objects, to eliminate the race logic while retaining the original logic functions of the IC design.