Patent ID: 7405129
Filing Date: 2008-07-29
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of forming a FET, comprising: (a) providing a gate on a substrate; (b) forming a gate dielectric on the gate: (c) forming a source over a first portion of the gate dielectric; (d) forming a drain over a second portion of the gate dielectric; (e) providing a channel between the source and the drain, the channel comprising a semiconductor nano-component, wherein the semiconductor nano-component comprises PbSe nanowire; and (f) exposing at least a portion of the semiconductor nano-component to a dopant selected from the group of hydrazine, mono-, di-, tri- or tetra-kis trimethylsilylhydrazine, a hydrazine derivative, diazobicycloundecane and polyaniline, and wherein the channel comprises at least one PbSe nanowire formed by a method comprising: (e1) providing a first solution having a Pb-containing species and a selenium-containing species at a first temperature; (e2) providing a second solution at a second temperature; (e3) injecting the first solution into the second solution to form a third solution, thereby forming PbSe nanocrystals; and (e4) maintaining the third solution at a third temperature for a predetermined time; and wherein the second temperature is higher than the first temperature, and the third temperature is sufficiently high to allow PbSe nanocrystals formed in the step (e3) to assemble into PbSe nanowires.