Patent ID: 8365119
Filing Date: 2013-01-29
Classification: G06F,G11C,H03K,H04L

Abstract:
1. A circuit comprising: a processor to implement control of interface operations; a bus coupled to said processor; and a plurality of interface control circuits coupled to said bus, a respective interface control circuit comprising a respective processing element, wherein the respective interface control circuit is configured to receive one or more respective signals from one or more respective devices external to the circuit; wherein the respective interface control circuit is further configured to process the one or more respective received signals to generate one or more respective interface adjustment signals based on results of operations performed by at least one of: the respective processing element and the processor, said operations using information derived from the one or more respective received signals, and wherein the circuit is operable in at least two modes, including a first mode in which said interface control circuits are operable to generate one or more interface adjustment signals based on the results of operations performed by said processing elements in response to one or more opcodes transmitted by said processor, and a second mode in which said interface control circuits are operable to generate one or more interface adjustment signals based on the results of operations performed by said processor using said information derived from the one or more respective received signals.