Patent ID: 6052738
Filing Date: 2000-04-18
Classification: G06F

Abstract:
An apparatus for controlling access to a shared memory in a network system, comprising:at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width, each fast input port interface comprising:a fast interface register configured to temporarily store the data and address information; anda command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory; andat least one slow port interface circuit, each configured to receive data, address, and command information from a network client at a second data rate in segments of the first width and transmit the data, address, and command information to a storage circuit that is shared among the slow port interface circuits, the shared storage circuit comprising a plurality of slow interface registers, wherein the segments of data are sequentially stored in one of the slow interface registers at the same time the contents of another slow interface register are read out in parallel to the shared memory.