Patent ID: 7778288
Filing Date: 2010-08-17
Classification: H04J,H04L

Abstract:
1. A high speed bit stream data conversion circuit comprising: a plurality of data conversion circuits that receive a first plurality of bit streams at a first bit rate and that produce at least one second bit stream at a second bit rate, wherein a number and the bit rate of the first plurality of bit streams and the at least one second bit stream differ; a plurality of symmetrical data circuit pathways that include pairs of circuit pathways, and that transport the first plurality of bit streams to the plurality of data conversion circuits, wherein transmission times for the first plurality of bit streams on the plurality of symmetrical data circuit pathways are substantially equal; a clock distribution circuit that receives a data clock signal and symmetrically distributes the data clock signal to the plurality of data conversion circuits along a plurality of symmetrical clock circuit pathways, wherein the symmetrical clock circuit pathways further include a central trunk located between a first pair of circuit pathways, and symmetrical pairs of branches that extend from the central trunk and couple to the plurality of data conversion circuits, and wherein clock transmission times associated with each symmetrical clock circuit pathway are substantially equal, and wherein the distributed data clock signal latches data in the plurality of data conversion circuits from the first plurality of bit streams to the at least one second bit stream at the second bit rate, and wherein the pairs of circuit pathways include a first pathway located on a first side of the central trunk and a second pathway located on a second side of the central trunk, wherein the second side is opposite the first side.