Patent ID: 7397687
Filing Date: 2008-07-08
Classification: G11C

Abstract:
1. A ferroelectric memory device comprising: a cell block including a ferroelectric capacitor and a transistor switch, the ferroelectric capacitor storing binary data by a direction of polarization of the ferroelectric capacitor; a bit line which is connected to the cell block and applies a voltage to one electrode of the ferroelectric capacitor; a plate line which is connected to the cell block and applies a voltage to the other electrode of the ferroelectric capacitor; a word line connected to a gate electrode of the transistor switch; and a differential amplifier connected to the bit line, a first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a change in voltage of the bit line when the transistor switch is activated being detected by the differential amplifier to read the data, and a second fixed voltage different from the first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a voltage which is higher than the second voltage or lower than the second voltage being applied to the bit line to write data in the ferroelectric capacitor.