Patent ID: 7279115
Filing Date: 2007-10-09
Classification: H01L,Y10S

Abstract:
1. A method of preparing a substrate for reducing stacking fault nucleation and reducing forward voltage (V f ) drift in silicon carbide-based bipolar devices, the method comprising: conducting a selective etch on the surface of a silicon carbide substrate sufficient to delineate the basal plane dislocations with the wafer surface and that will thereafter tend to terminate or to propagate as threading defects while avoiding creating beta (3C) inclusions and carrot defects; growing a conductive epitaxial layer on the selectively etched substrate surface with a sufficient thickness to support additional polishing and etching steps above the substrate; polishing away a sufficient portion of the conductive epitaxial layer to remove the material containing the etched pits to thereby provide a surface with fewer etched pits than the surface of the selectively-etched substrate; and thereafter conducting a non-selective etch of the epilayer sufficient to remove subsurface damage from the step of polishing the epitaxial layer but without reaching the underlying substrate, to thereby reduce the number of subsurface defects that can propagate stacking faults under forward voltage in a device formed on the substrate and the polished epilayer.