Patent ID: 8105906
Filing Date: 2012-01-31
Classification: G11C,H01L

Abstract:
1. A method for fabricating a microelectronic device with one or plural double-gate transistors, comprising: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one channel semiconducting zone and separated from the at least one channel semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, the first gate dielectric zone and the second gate dielectric zone, the at least one channel semiconducting zone, and the second block supported on the first block, the one or plural structures being made such that the first block and the second block have a critical dimension less than a critical dimension of the second gate dielectric zone and the first gate dielectric zone, wherein the critical dimension is defined as a width measured in a direction parallel to a principal plane defined by a surface of the substrate on which the one or plural structures is formed; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the one or plural structures, using at least first implantation selective relative to the first block, the first dielectric zone and the second dielectric zone configured to protect at least part of the first block during the at least first implantation.