Patent ID: 6312983
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A method for forming a bit line of a DRAM memory array, the method comprising the steps of:forming an interlayer dielectric over the DRAM memory array;etching said interlayer dielectric to form trenches in said interlayer dielectric, said trenches collectively forming a bit line pattern, said trenches having tapered side walls; anddepositing a conductive material into said trenches to form said bit line; wherein said etching step to form said trenches is performed at substantially the following process parameters:a pressure of 130 millitorr;a power of 1000 watts;a flow rate of CHF.sub.3 of 50 sccm;a flow rate of CF.sub.4 of 10 sccm; anda flow rate of Ar of 150 sccm.