Patent ID: 6388314
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A memory, comprising:a semiconductor die having at least 224 single-bit memory cells and sized to fit within an industry standard package, the package having a maximum width of approximately 300 mils and a maximum length of approximately 675 mils, the die comprising: layers of interconnection circuity on the substrate consisting of; a single highly conductive interconnect layer having a sheet resistance of less than one ohm per square interconnecting portions of a plurality of the single-bit memory cells, portions of a plurality of signal bonding pads, portions of a plurality of power bonding pads, portions of a plurality of row address decoders, portions of a plurality of column address decoders, and portions of a plurality of sense amplifiers; and one semiconductor interconnect layer interconnecting other portions of the single-bit memory cells, other portions of the plurality of row address decoders, other portions of the plurality of column address decoders and other portions of the sense amplifiers.