Patent ID: 7551617
Filing Date: 2009-06-23
Classification: H04L

Abstract:
1. A packet processor, comprising: an external interface to receive external packets from a network; a recirculation interface to receive recirculated packets; a plurality of packet processor elements each operating one or more threads; a packet memory coupled to the external interface to store the external packets, coupled to the recirculation interface to store the recirculated packets, and coupled to the packet processing elements to enable the packet processor elements to process both the external packets and the recirculated packets; a distributor distributing ones of the external packets in the packet memory to free ones of the threads according to a bounded time arrival processing required for the external packets, and distributing ones of the recirculated packets in the packet memory to free ones of the threads according to a variable time main processing required for the recirculated packets; and wherein the arrival processing of the external packets by the packet processor elements is used, at least in part, to produce the recirculated packets.