Patent ID: 8674735
Filing Date: 2014-03-18
Classification: H03K,H03L,H04N

Abstract:
1. A phase adjusting apparatus comprising: an output section outputting a first serial transfer data including a head code indicating a head of a serial transfer data, a first data, and a first padding data; a first setting section setting a first delay amount to adjust a phase of the first serial transfer data being output from the output section; a first delay section outputting a first output which is the first serial transfer data being output from the output section in which a phase thereof is delayed by a phase equivalent to a first time based on the first delay amount set by the first setting section; a second setting section setting a second delay amount to adjust a phase of the first output being output from the first delay section; a second delay section outputting a second output which is the first output being delayed by a phase equivalent to a second time based on the second delay amount set by the second setting section. a third output which is the second output being delayed by a phase equivalent to the second time based on the second delay amount set by the second setting section. and a fourth output which is the third output being delayed by a phase equivalent to the second time based on the second delay amount set by the second setting section; a calculating section calculating a delay amount for the first delay section to adjust a phase of a second serial transfer data being output from the output section following the first serial transfer data based on a first comparison result and a second comparison result. the first comparison result comparing the head code included in the third output being output from the second delay section with the head code included in the second output being output from the second delay section in a predetermined timing. and the second comparison result comparing the head code included in the third output being output from the second delay section with the head code included in the fourth output being output from the second delay section in a predetermined timing, wherein the first setting section sets the delay amount calculated by the calculating section; and the delay section outputs a fifth output which is the second serial transfer data being delayed by a phase equivalent to the delay amount set by the first setting section.