Patent ID: 6279101
Filing Date: 2001-08-21
Classification: G06F

Abstract:
An instruction decoder for use in a processor, the processor including a source of instructions and a plurality of functional units for executing said instructions, said instruction decoder comprising:input means coupled to said source of instructions for receiving a block of said instructions from said source of instructions, said block of instructions containing a plurality of said instructions;decoding means for decoding selected ones of said instructions of said received block of instructions, said decoding means including dispatch control means for applying a dispatch criteria to said selected ones of said instructions of said received block of instructions; andoutput means coupled to said plurality of functional units and responsive to said dispatch control means for dispatching all of said selected instructions of said received block of instructions satisfying said dispatch criteria in parallel to said functional units, wherein said input means receiving a next block of said instructions from said source of instructions after all of said received block of instructions have been dispatched by said output means.