Patent ID: 8086883
Filing Date: 2011-12-27
Classification: G06F,Y02D

Abstract:
1. A data processing apparatus comprising: (i) a processor for processing data, said processor comprising memory interface logic for controlling transfer of data to a memory, said processor being powered in a first power domain; (ii) a memory for storing data processed by said processor said memory being powered in a second power domain; (iii) a system bus coupled to said processor and said memory and operable to transfer data between said processor and said memory in response to memory transfer requests issued upon said system bus by said memory interface logic during normal processing operation of said processor and said memory; wherein (iv) said processor is responsive to a low power request indicating said data processing apparatus should enter a low power mode to: (v) control transfer of state data indicating a current state of said processor to said memory via said system bus using said memory interface logic, said state data being sufficient data to restore said processor to an equivalent program state following exit from said low power mode; (vi) store said state data in said memory; and (vii) power down said first power domain, wherein said processor is configured to store said state data on a stack within said memory in response to said low power request, said processor comprising stack/unstack logic for stacking said state data to said stack in response to said low power request and for unstacking said state from said stack in response to a subsequent power up signal.