Patent ID: 6782520
Filing Date: 2004-08-24
Classification: G06F

Abstract:
A method for designing a layout for an integrated circuit (IC) comprising cells having terminals interconnected by nets, wherein the layout includes a placement plan and a routing plan, wherein the placement plan specifies where each cell in to be placed in a semiconductor substrate, and wherein the routing plan specifies in detail a route each net is to follow between the cell terminals it is to interconnect, the method comprising the steps of:a. generating a placement plan for the IC specifying a position within the semiconductor substrate for each of the cells, b. generating a trial routing plan specifying an approximate route each net is to follow, c. iteratively modifying the placement plan generated at step a and the trial routing plan generated at step b to reposition at least one cell, to reroute at least one net, and to insert at least one additional buffer into at least one of the nets, until the placement and routing plans satisfy first constraints, including constraints on signal path delays through the nets, d. converting the trial routing plan iteratively modified at step c into a detailed routing plan specifying a detailed route each net is to follow between the cell terminals it interconnects, and e. iteratively modifying the placement plan and the detailed routing plan until they satisfy second constraints.