Patent ID: 6292405
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A data output buffer comprising:an output node;a first CMOS stage connected to the output node for providing a first control signal for precharging the output node to an intermediate voltage with respect to a voltage for switching the output node from a current logic state to a different logic state;a second CMOS stage connected to said first CMOS stage and to the output node, said first and second CMOS stages being responsive to a second control signal for enabling output of new data, and said first and second CMOS stages being responsive to a third control signal for driving said first and second CMOS stages to a tristate condition when the output node is being precharged;a control latch connected to said first and second CMOS stages and to the output node, said control latch being responsive to the first control signal for latching data present on the output node and for providing a signal corresponding to data last output from the output node;a first comparator for comparing the data present on the output node to a first intermediate reference voltage, and outputting a first reset signal;a second comparator for comparing the data present on the output node to a second intermediate reference voltage, and outputting a second reset signal; anda first pair of set and reset latches connected between said first CMOS stage and said first comparator, and a second pair of set and reset latches connected between said first CMOS stage and said second comparator, said first and second pairs of set and reset latches for driving said first CMOS stage so that the output node is precharged as a function of the signal corresponding to the data last output and as a function of the first and second reset signals until a rising and falling edge of the data last output respectively crosses the intermediate voltage.