Patent ID: 8350605
Filing Date: 2013-01-08
Classification: H03L

Abstract:
1. A phase-locked loop (PLL) with novel phase detection mechanism, comprising: a phase frequency detector (PFD), having a first input and a second input and generating a signal based on relative frequencies of said first input and said second input by comparing and analyzing a plurality of observed signal levels of said second input and at least a delayed version of said second input to indicate whether frequency of said second input is faster or slower than half of the frequency of said first input, said plurality of observed signal levels being obtained by sampling signal levels of said second input and said at least a delayed version of said second input when said first input changes from a first level to a second level, and said delayed version of said second input being formed by delaying said second input with a phase delay; a controller, connected to said PFD for receiving said signal from said PFD and generating a control signal; a digital-to-analog (D2A) module, connected to said controller for receiving said control signal and generating an analog voltage/current output; and a voltage-controlled oscillator (VCO), connected to said D2A module for receiving said analog voltage/current output to adjust an output signal accordingly; wherein said second input of said PFD is connected to a reference signal and said first input of said PFD is connected to said output signal of said VCO.