Patent ID: 7757070
Filing Date: 2010-07-13
Classification: G06F

Abstract:
1. A multithreading apparatus comprising: an instruction dispatch block to fetch and issue instructions of a plurality of instruction execution threads for execution by an execution block; a first thread-control register associated with a first instruction execution thread operatively coupled to the instruction dispatch block, the first thread-control register including a first thread-control bit for selectively disabling the first instruction execution thread; a second thread-control register associated with a second instruction execution thread operatively coupled to the instruction dispatch block, the second thread control register including a second thread-control bit for selectively disabling the second instruction execution thread; and a thread-operation register including a first thread-operation bit for selectively providing a first lock to the first instruction execution thread to prevent the second instruction execution thread from disabling the first instruction execution thread while the first instruction execution thread has the first lock; wherein the first thread-operation bit is configured to engage the first lock to the first instruction execution thread, in response to an instruction to disable the first instruction execution thread; wherein the first thread-control bit is configured to disable the first instruction execution thread, in response to the request to disable the first instruction thread; and wherein the first-thread-operation bit is further configured to release the first lock concurrently with or after disabling the first instruction thread.