Patent ID: 7203105
Filing Date: 2007-04-10
Classification: G06F

Abstract:
1. A semiconductor memory device comprising a plurality of nonvolatile memories and a controller which controls read/write operations for said plurality of nonvolatile memories through a first memory bus and a second memory bus in accordance with read/write commands from a host apparatus, wherein when a case where a nonvolatile memory F said controller comprises: a selection section which selects one of said two-memory configuration and said four-memory configuration; a sequential number conversion section which divides each nonvolatile memory into two regions to form a first half region and last half region, and converts a consecutive logical address specified by said host apparatus to a logic sequential number of a predetermined size; a modulo number generation section which generates a logic sequential modulo number of system of residues of 4 with respect to said logic sequential number; and a write control section which performs a write operation in a format that selectively and repeatedly circulates through the nonvolatile memories F