Patent ID: 8600049
Filing Date: 2013-12-03
Classification: G06F,H04L

Abstract:
1. A method of performing an Advanced Encryption Standard (AES) operation on a plurality of fixed size data blocks using a mode of operation that operates on a block independently of other blocks, comprising: storing, by a processor, a set of k consecutive data blocks of the plurality of fixed sized data blocks in k registers, k greater or equal to the latency (L) of an AES round instruction, the AES round instruction to perform a sequence of AES round operations for an AES round on the set of k consecutive data blocks; and performing, by one or more processors, the sequence of AES round operations on the set of k consecutive data blocks in parallel during the AES round by dispatching the AES round instruction to each of the set of k consecutive data blocks in a pipelined fashion at a rate of one data block per processor cycle.