Patent ID: 7577019
Filing Date: 2009-08-18
Classification: G11C,Y10S

Abstract:
1. A multi-bit magnetic memory cell in a stacked structure controlled by at least a read bit line and a read word line, comprising: at least two magnetic memory units, wherein each one of the at least two magnetic memory units respectively has a magneto-resistance value and the at least two magnetic memory units are in a stacked structure and connected in parallel or in series to form a circuit, and the circuit is connected to the read bit line; and a switching device electrically connected to the circuit, wherein the switching device is controlled by the read word line to be conducting or non-conducting so as to connect the circuit to a ground voltage, wherein a stored data corresponds to a total magneto-resistance value state of the circuit formed by the magnetic memory units with the magneto-resistance value of each magnetic memory unit capable of switching between two stable states, wherein the read bit line is divided into a plurality of branch lines for connecting with the respective magnetic memory units when the circuit is a parallel connection, wherein the read bit line is connected to the magnetic memory units in serial connection when the circuit is a serial connection.