Patent ID: 8375233
Filing Date: 2013-02-12
Classification: G06F,Y02D

Abstract:
1. A method for managing power consumed in a processor executing an application, the application comprising at least a first processing phase of unpredictable duration and a second processing phase, successive to the first processing phase and having a predictable beginning, the first phase being associated with a first computational load, the second phase being associated with a second computational load larger than the first computational load, the method comprising the following steps: defining a first nominal mode of consumption for which the power level consumed in the processor is compatible with the execution of the second phase, defining at least a secondary mode of low consumption for which the power level consumed in the processor is compatible with the execution of the first phase, and determining execution of the first phase with said secondary mode of low consumption only if a duration between an estimated termination of the first phase and a predictable beginning of the second phase is larger than a maximum latency induced by switching from the secondary mode of low consumption to the first nominal mode of consumption, so as to guarantee a correct execution of the second phase, otherwise executing the whole application with the first nominal mode of consumption.