Patent ID: 6562677
Filing Date: 2003-05-13
Classification: H01L,Y10S

Abstract:
A method of manufacturing a capacitance element, comprising:a first step of sequentially forming a conductor film and a dielectric film on a substrate; second step of patterning said conductor film and said dielectric film to form a lower electrode and a capacitance insulating film; a third step of forming a metal film for an upper electrode on the substrate so that said metal film for an upper electrode is not in contact with said conductor film for said lower electrode; a fourth step of patterning said metal film for an upper electrode to form an upper electrode having a first partial film which is in contact with a top surface of said capacitance insulating film and a second partial film which is not in contact with said capacitance insulating film; a fifth step of forming an interlayer insulating film on the substrate; a sixth step of forming a contact hole extending through said interlayer insulating film and reaching the second partial film of said upper electrode; and a seventh step of depositing a metal film for a wire on the substrate and patterning the metal film for a wire to form an electrode wire provided in said contact hole and connected to said second partial film of said upper electrode.