Patent ID: 7875885
Filing Date: 2011-01-25
Classification: H01L

Abstract:
1. A display element structure being formed on a substrate and comprising: a gate disposed on the substrate; a dielectric layer covering the gate and the substrate; a patterned semiconductor layer disposed on the dielectric layer, wherein the patterned semiconductor layer includes a channel region above the gate, and a source and a drain lied on the opposite sides of the channel region; a barrier layer completely covering the patterned semiconductor layer, but substantially not covering the dielectric layer, except for an area approximately equal to a thickness of the barrier layer and located at endpoints of the barrier layer; and a second patterned conducting layer covering portions of the barrier layer above the source and the drain and covering portions of the dielectric layer adjacent to the source and the drain, wherein the barrier layer only exists between the patterned semiconductor layer and the second patterned conducting layer.