Patent ID: 8363498
Filing Date: 2013-01-29
Classification: G11C

Abstract:
1. A non-volatile memory device comprising: a cell array comprising a plurality of unit cells configured to be coupled to a plurality of word lines and a plurality of bit lines; a column switching unit configured to select one of the plurality of bit lines; and a discharge unit configured to discharge bit lines other than the selected bit line among the plurality of bit lines in response to a bit line discharge signal in an active mode in which a read or write operation is performed, wherein the plurality of bit lines are shared by a plurality of mats, each mat including a cell array, wherein mats that share the selected bit line among the plurality of mats are activated, and bit lines other than the selected bit line in the activated mats are discharged in the active mode, and wherein mats that do not share the selected bit line among the plurality of mats are deactivated, and a plurality of bit lines corresponding to the deactivated mats is in a floating state in the active mode.