Patent ID: 6829697
Filing Date: 2004-12-07
Classification: G06F

Abstract:
In the operation of an embedded processor complex for controlling the progammability of a network processor, the processor complex including a plurality of protocol processor units (PPUs), each PPU containing multiple core language processors (CLPs), each CLP having at least two code threads, each PPU utilizing a plurality of coprocessors useful for executing specific tasks for the PPU, multiple logical coprocessor interfaces to provide access between each CLP and the coprocessors, and two arbiters between the CLPs and the coprocessors, wherein the coprocessors are selected from the group including a tree search coprocessor, a checksum coprocessor, a stringcopy coprocessor, an enqueue coprocessor, a datastore coprocessor, a CAB coprocessor, a counter coprocessor and a policy coprocessor, and wherein one of the arbiters is a coprocessor execution interface arbiter to determine the priority between multiple code threads.