Patent ID: 8970050
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a first semiconductor chip including a first region and a second region wherein the second region is positioned in an edge of the first semiconductor chip; a second semiconductor chip including a third region corresponding to the first region and a fourth region, wherein the fourth region is positioned in an edge of the second semiconductor chip which corresponds to the second region, and stacked on top of the first semiconductor chip; a first plurality of through-silicon vias (TSVs) formed in the first region of the first semiconductor chip and the third region of the second semiconductor chip so as to be electrically connected between the first and second semiconductor chips; and alignment keys formed in the second region of the first semiconductor chip and the fourth region of the second semiconductor chip, wherein the alignment keys are provided for aligning the first and second semiconductor chips, and the alignment keys of the first semiconductor chip are electrically connected to that of the second semiconductor chip by via patterns.