Patent ID: 6570788
Filing Date: 2003-05-27
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a memory transistor formed by stacking a gate electrode above a semiconductor substrate or a well with an insulating film therebetween and further including a charge storing means; and a write and erase circuit for supplying a write voltage or an erase voltage between said gate electrode and said semiconductor substrate or well for performing a write or erase operation on the memory transistor; wherein said write and erase circuit comprises; a means for dividing an applied voltage to a first and a second voltage and supplying the first voltage to said gate electrode a write operation and for generating third and a fourth voltages and supplying the third voltage at an opposite polarity from said first voltage to said gate electrode for performing an erase operation; and a means for applying said second voltage at an opposite polarity from the time of applying said first voltage to said semiconductor substrate or well during a write operation and applying said fourth voltage at an opposite polarity from the time of applying said third voltage to said semiconductor substrate or well during an erase operation.