Patent ID: 6546440
Filing Date: 2003-04-08
Classification: G06F,G11B

Abstract:
An apparatus comprising:a host interface in an optical drive controller, said host interface operable to be directly connected to a host computer via an IDE/ATA bus, said host interface including, a multi-byte command buffer operable, per command, to store sequentially contiguous multiple command bytes received from said host computer in a single command transfer, the multi-byte command buffer addressed by one of a plurality of ATA command block register addresses, a drive/head register addressed by another of said plurality of ATA command block register addresses, said drive/head register including a DRV bit, wherein said host interface uses said DRV bit to determine whether to store commands in said multi-byte command buffer, a status register addressed by yet another of said plurality of ATA command block register addresses, said status register including a BSY bit, circuitry operable to alter said BSY bit, responsive to command events initiated by the host computer, to indicate said host computer is precluded from accessing said plurality of ATA command block register addresses, circuitry operable to carry out initial signal transitions on DASP, PDIAG, and HIRQ lines of said IDE/ATA bus in response to soft reset and execute drive diagnostic command events, and circuitry operable to clear the signal on the HIRQ line responsive to said host computer reading said status register; and a path in said optical drive controller operable to allow a microcontroller, which controls reading of information from optical media, to read from said multi-byte command buffer, to cause said BSY bit to be altered, to read said DRV bit, and to cause certain transitions of signals on said DASP, PDIAG, and HIRQ lines of said IDE/ATA bus.