Patent ID: 6605842
Filing Date: 2003-08-12
Classification: H01L

Abstract:
An insulated gate type field effect semiconductor power device having a drain offset region, in which an N type source region and an N type drain region having an offset region are formed, being spaced apart from each other, to a P type silicon semiconductor layer, a gate electrode is formed by way of a gate insulation film to the surface of the P type silicon semiconductor layer as a channel region between the N type source region and the offset region, and the gate electrode comprises a silicon semiconductor layer containing P type impurities and wherein,a metal plug is connected with the main surface of each of the drain regions and each of the source regions, a first metal conductor layer is connected with each of the metal plugs, an interlayer insulation film is covered on the first metal conductor layer, a second metal conductor layer for the drain is connected in common with each of the first metal conductor layers for the drain of the first metal conductor layers through openings in the interlayer insulation film being situated on the metal plug connected with the drain region, a second metal conductor layer for the source is connected in common with each of the first metal conductor layers for the source of the first metal conductor layers through source connecting openings in the interlayer insulation film, a second metal conductor layer for the gate is connected in common with each of the first metal conductor layers for the gate of the first metal conductor layers through gate connecting openings in the interlayer insulation film, the second metal conductor layer for the drain has a drain bonding pad, and the second metal conductor layer for the gate has a gate bonding pad.