Patent ID: 6037262
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A process for respectively forming vias and trenches in two separate dielectric layers consisting of:a) forming a first dielectric layer over an integrated circuit structure on a semiconductor substrate;b) forming over said first dielectric layer a first mask, said first mask having one or more openings therein corresponding to one or more vias to be formed in said first dielectric layer;c) etching said first dielectric layer through said first mask to form one or more vias extending through said first dielectric layer;d) removing said first mask;e) forming a second dielectric layer over said first dielectric layer, said second dielectric layer having different etch characteristics than said first dielectric layer;f) forming over said second dielectric layer a second mask, said second mask having one or more mask openings therein for forming one or more trenches in said second dielectric layer in registry with said one or more vias;g) etching said second dielectric layer through said openings in said second mask down to said first dielectric layer to form one or more trenches in said second dielectric layer, while also removing any material from said second dielectric layer deposited in said previously formed one or more vias in said first dielectric layers, said first dielectric layer providing an etch stop for said etching of said second dielectric layer to form said one or more trenches.