Patent ID: 9128633
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A method of controlling an order of executing commands of a plurality of master groups including a first master group and a second master group in a semiconductor system including a memory controller, comprising: generating a first timeout index signal, by a first master in the first master group, based on a result of comparing a residual memory capacity of a first data buffer in the first master with a first threshold value; generating a second timeout index signal, by a second master in the second master group, based on a result of comparing a residual memory capacity of a second data buffer in the second master with a second threshold value; selecting a first timeout value, by the memory controller, among a plurality of timeout values associated with the first master group in response to the first timeout index signal; selecting a second timeout value, by the memory controller, among a plurality of timeout values associated with the second master group in response to the second timeout index signal; and determining, by the memory controller, the order of executing the commands based on the selected timeout values including the first timeout value and the second timeout value.