Patent ID: 8518802
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A process for fabricating integrated-circuit chips, comprising: producing a plurality of separate encircling weak portions of porous silicon in a silicon substrate wafer, said separate encircling porous silicon weak portions surrounding a plurality of first locations, the plurality of encircling porous silicon weak portions being spaced apart from one another by transition regions and each encircling porous silicon weak portion surrounding one first location; producing a plurality of integrated-circuit chips in said first locations, including respectively portions of said substrate wafer corresponding to said first locations; fixing a support wafer to a front-side of said silicon substrate wafer, said fixing occurring by way of regions of holding adhesive fixing said support wafer to the front-side at said transition regions; and destroying said porous silicon weak portions so as to singulate said integrated-circuit chips.