Patent ID: 8334565
Filing Date: 2012-12-18
Classification: H01L

Abstract:
1. A vertical and trench type insulated gate MOS semiconductor device comprising: a semiconductor substrate of a first conductivity type; a base region of a second conductivity type selectively formed on one of the principal surfaces of the semiconductor substrate of the first conductivity type; an emitter region of the first conductivity type selectivity formed on the surface of the base region of the second conductivity type; a body region of the second conductivity type formed on the surface of the base region of the second conductivity type while being in contact with the emitter region of the first conductivity type, the body region having an impurity concentration higher than that of the base region; a plurality of straight-line-like trenches arranged in parallel to form a surface pattern of a plurality of parallel straight lines, each trench being formed from the surface of the emitter region of the first conductivity type to a depth reaching the semiconductor substrate of the first conductivity type while penetrating the base region of the second conductivity type; a gate electrode buried in each of the trenches with a gate insulator film interposed between; and an emitter electrode making common conductive contact with both of the surfaces of the emitter region of the first conductivity type and the body region of the second conductivity type; wherein, in a plurality of regions on the surface of the semiconductor substrate each being provided between adjacent ones of a plurality of the straight-line-like trenches arranged in parallel and forming a surface pattern of a plurality of the straight lines, there are included: a plurality of first inter-trench surface regions in each of which the surfaces of (i) the base regions of the second conductivity type, each with the emitter region of the first conductivity type and the body region of the second conductivity type formed thereon, are alternately arranged with (ii) the surfaces of regions of the semiconductor substrate of the first conductivity type along the trench in the longitudinal direction thereof, with the emitter electrode being in common contact with both of the surfaces of the emitter region of the first conductivity type and the body region of the second conductivity type; and a plurality of second inter-trench surface regions each of which is formed along the trench in the longitudinal direction thereof comprising the surface of the base region of the second conductivity type.