Patent ID: 9037838
Filing Date: 2015-05-19
Classification: G06F

Abstract:
1. A multiprocessor system comprising: a first microprocessor; a second microprocessor; a first signaling pathway for sending message transmission coordination signals from the first microprocessor to the second microprocessor, wherein the first signaling pathway is coupled to at least two flag registers associated with the second microprocessor; a second signaling pathway for sending message transmission coordination signals from the second microprocessor to the first microprocessor, wherein the second signaling pathway is coupled to at least two flag registers associated with the first microprocessor; and an external memory system coupled to the first and second microprocessors, wherein the external memory system includes a first portion compartmentalized into a temporary storage area and a prioritized storage area, wherein the external memory system is configured to: wherein the first signaling pathway is independent of the second signaling pathway.