Patent ID: 6037662
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A chip scale package comprising:a semiconductor chip including a bonding pad formed on a surface thereof;a tape attached to said semiconductor chip using an adhesive material in such a manner that said bonding pad is exposed, said tape including a conductive pattern formed therein, said conductive pattern extending as a beam lead outwardly over said bonding pad; anda plurality of solder balls electrically connected to said conductive pattern of said tape,wherein said beam lead includes:an inner portion that extends in a first direction;a first connecting portion that extends from said inner portion in a second direction that at an angle with said first direction;a central portion that is narrower than the inner portion and extends from said first connecting portion in said first direction;a second connecting portion that extends from said central portion in said second direction; andan outer portion that is narrower than the central portion and extends from said second connecting portion in said first direction,wherein said central portion contacts said bonding pad to form an electrical connection.