Patent ID: 7062734
Filing Date: 2006-06-13
Classification: G06F

Abstract:
1. A method for determining a slack time for a node in a circuit design comprising: determining a starting point and an ending point for a path going through at least one latch; determining a set of required times for each node in the path by working upstream from the ending point, determining a respective set of arrival times for the one or more nodes in the path by working downstream from the starting point; and calculating the slack time for the one or more nodes in the path from the respective set of required times and the respective set of arrival times at each respective node, wherein the required times in the respective set of required times and the arrival times in the respective set of arrival times are associated with different clock relationships between the respective node and a downstream node, the different clock relationships resulting from the respective node and the downstream node being driven by different respective clock signals, at least one of the respective clock signals having a varying pulse width.