Patent ID: 7549098
Filing Date: 2009-06-16
Classification: G11C

Abstract:
1. A method of implementing redundancy programming in an integrated circuit chip having one or more memory macros and an automatic built-in self-test circuit, said method comprising: (a) sending a test pattern to a memory array of a memory macro of said one or more memory macros from said automatic built-in self-test circuit; (b) sending an expected test pattern based on said test pattern to a fail register and writing said test pattern into said memory array of said memory macro of said one or more memory macros; (c) in a standard mode, reading out a resultant pattern from said memory array and sending said resultant pattern from said memory array to said fail register, said fail register comparing said resultant pattern with said expected pattern and generating a current fail record based on said comparison in said fail register if said resultant pattern does not match said expected pattern, said current fail record comprising a type of fail field, a wordline address field and a data field as wide as the number of columns in said memory array and indicating which bits of said test pattern failed; (d) storing said current fail record in said fail register if another fail record in said fail register does not have a same wordline address as said current fail record and writing said type of fail field of said current fail record as a wordline fail; (e) if all bits in said data field of said current fail record match all bits of a data field of any other fail record in said fail register and the number of failing bits is less than a preset number of bits but at least equal to one, then changing said type of fail field of said current fail record to a bitline fail; (f) repeating steps (a) through (e) until said fail register is full or no more test patterns are to be sent to said memory array; (g) sending a fail record from said fail register to a repair register of said memory macro; (h) generating and storing in said repair register a wordline repair record based on said fail record and sending a wordline repair command to said memory array if said fail type field of said fail record indicates wordline fail, or generating and storing a bitline repair record and sending a bitline repair command to said memory array if said fail type field indicates a bitline fail, said bitline repair record based on said data field of said fail record; (i) replacing defective wordlines and bitlines of said memory array of said memory macro of said one or more memory macros with redundant wordlines and bitlines of said memory array based on said wordline and bitline repair commands; and (j) repeating steps (a) through (i) until no more test patterns are to be sent to said memory array.