Patent ID: 7427540
Filing Date: 2008-09-23
Classification: H01L

Abstract:
1. A method for fabricating a thin film transistor (TFT) array substrate, comprising: forming a first metal layer over a substrate; patterning the first metal layer by a first photolithography to form a gate line continuously extending along a first direction and a plurality of data line sections extending along a second direction, wherein the first direction is different form the second direction and the data line sections are separated from the gate line at a intersection; forming an insulating layer, a semiconductor layer and an ohmic contact layer over the substrate; patterning the ohmic contact layer, the semiconductor layer, and the insulating layer by a second photolithography, forming a plurality of semiconductor structures and a plurality of stacked structures crossing over the gate line and the data line sections at intersections thereof; forming a second metal layer over the substrate; patterning the second metal layer by a third photolithography to form a plurality of source/drain electrodes over the semiconductor structures and a plurality of continuous data lines extending over the stacked structures to electrically connect the data line sections; forming a passiviation layer over the substrate; patterning the passivation layer by a fourth photolithography to form a plurality of via holes, exposing a plurality of pads for the data and gate lines and for the source/drain electrodes; forming a transparent conductive layer over the substrate, filling the via holes; and patterning the transparent conductive layer by a fifth photolithography to form a plurality of pixel electrodes and storage capacitors, wherein the storage capacitors partially overlap the gate lines.