Patent ID: 7508048
Filing Date: 2009-03-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a low voltage region and a high voltage region; a first trench region formed in the low voltage region to define a first active region having a top surface, the first active region having a protruded edge portion that extends above the top surface; a first sloped region interposed between the first trench region and the first active region, the first sloped region having a first incline that is downwardly extended from the protruded edge portion of the first active region; a second trench region formed in the high voltage region to define a second active region, the second active region having a relatively flat top surface; a second sloped region interposed between the second active region and the second trench region, the second sloped region having a second incline that is downwardly extended from the edge corner of the second active region; a first isolation layer filling the first trench region and covering the first incline; a second isolation layer filling the second trench region and covering the second incline; a low voltage gate insulation layer formed on the first active region, the low voltage gate insulation layer having a top surface lower than a top surface of the first isolation layer; and a high voltage gate insulation layer formed on the second active region, the high voltage gate insulation layer having a flat top surface lower than a top surface of the second isolation layer and being thicker than the low voltage gate insulation layer.