Patent ID: 7710774
Filing Date: 2010-05-04
Classification: G11C,H01L

Abstract:
1. A memory, comprising: a first memory string and a second memory string, each of the first memory string and the second memory string including one or more memory cells being connected in series to form a memory cell string, each of the memory cells comprising a layer for storing a charge localized at one side, the memory cells further comprising two adjacent bits belonging to the first memory string and the second memory string respectively; a first select transistor connected in series to a first end of each of the first and second memory cell strings; a second select transistor connected in series to a second end of each of the first and second memory cell strings; a shared bit line connected with the first memory string and the second memory string through a first contact, the shared bit line being applied a voltage for programming simultaneously the two adjacent bits belonging to two memory cells; a first bit line connected with a first end of the first memory string through a second contact; and a second bit line connected with a second end of the second memory string through a third contact, wherein the first select transistor of each of the first memory string and the second memory string is controlled by a first select transistor control line, and the second select transistor of each of the first memory string and the second memory string is controlled by a second select transistor control line.