Patent ID: 6446173
Filing Date: 2002-09-03
Classification: H04L

Abstract:
A memory controller for providing an interface between a memory device and a communication bus in a multi-port bridge for a local area network wherein the communication bus interconnects a plurality of ports of the multi-port bridge, the memory controller comprising:a. a command decoder coupled to the communication bus for receiving bus commands from the communication bus and for forming an operation control signal indicative of a type of bus command received; b. a memory control finite state machine coupled to receive the operation control signal from the command decoder, the memory control finite state machine having a plurality of states; c. means for forming a plurality of memory control signals according to a current state of the memory control finite state machine wherein the memory control signals are coupled to control inputs of the memory device; and d. means for forming row and column addresses according to memory address data received from the communication bus, the row and column addresses for coupling to address inputs of the memory device.