Patent ID: 6292397
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A nonvolatile memory sensing circuit, including a main cell part and at least one reference cell part, comprising:a main cell array having a plurality of main cells to each of which a word line driving signal is applied respectively;a plurality of main cell switches receiving a plurality of main cell selection signals YG0 to YGn which switch to select one of the main cells, respectively, wherein the main cell switches are connected to the main cell array in series;a main cell bit line voltage controller maintaining a drain voltage of the main cell at a fixed level by receiving a program bias voltage PRBIAS, wherein the main cell bit line voltage controller is connected to the plurality of main cell switches;a main cell path transistor connected between an output of the main cell bit line voltage controller and an internal power supply voltage, wherein the main cell path transistor outputs a state of the main cell; andat least one sense amplifier producing a comparison output SAOUT by receiving at least one reference voltage RDREF and an output SENSE of the main cell path transistor,wherein the at least one reference cell part comprises a program reference cell part and a read reference cell part which share a voltage controlling means for regulating drain or source voltages of a program reference cell and a read reference cell to a predetermined level on programming or reading.