Patent ID: 7310397
Filing Date: 2007-12-18
Classification: H04L

Abstract:
1. A data recovery circuit, comprising: a clock generator for generating a first group of sampling clock pulses and a second group of sampling clock pulses for sampling an incoming data stream, each sampling edge of said first group of sampling clock pulses and each sampling edge of said second group of sampling clock pulses being arranged alternatively and being separated from each other for an interval equal to half the period of said incoming data stream, said clock generator being controlled in response to a phase control signal to adjust phases of said first group of sampling clock pulses and said second group of sampling clock pulses; a data and phase sampling circuit for receiving said incoming data stream, said first group of sampling clock pulses and said second group of sampting clock pulses, said data and phase sampling circuit taking samples of said incoming data stream in accordance with said first group of sampling clock pulses to produce a first sampled data stream while taking samples of said incoming data stream in accordance with said second group of sampling clock pulses to produce a second sampled data stream; and a phase detection and correction circuit coupled to said data and phase sampling circuit, for determining resemblances of each bit in said second sampled data stream to the corresponding two bits in said first sampled data stream, the associated sampling edge of said bit in said second sampled data stream being adjacent to the associated sampling edges of said two bits in said first sampled data stream, said phase detection and correction circuit producing said phase control signal on the basis of the resemblance determination result; wherein said first group of sampling clock pulses includes a first clock signal and said second group of sampling clock pulses includes a second clock signal, said first clock signal and said second clock signal are 90 degrees out of phase with each other, and both rising edges and falling edges of said first clock signal and said second clock signal are used as said sampling edges.