Patent ID: 6614688
Filing Date: 2003-09-02
Classification: G11C

Abstract:
A method of programming a non-volatile semiconductor memory device including a semiconductor substrate of a first conductive type; a first well area of a second conductive type formed in the semiconductor substrate of the first conductive type; a second well area of the first conductive type formed in the first well area; a memory cell array including a plurality strings, the memory cell array being formed in the second well area, wherein each of the strings is made of a first select transistor having a drain coupled to a corresponding bitline, a second select transistor having a source coupled to a common source line, and a plurality of memory cells serially connected between a source of the first select transistor and a drain of the second select transistor; a first select line commonly connected to first select transistors of the strings; a second select line commonly connected to second select transistors of the strings; a plurality of wordlines each being coupled to memory cells of the respective strings; and page buffers for temporarily storing data bits to be programmed in the memory cell array, the page buffers each being coupled to the bitlines corresponding to the respective bitlines, the method comprising:supplying one of a first supply voltage and a second supply voltage respectively to the bitlines according to data bits stored in the page buffers, the first supply voltage being lower than the second supply voltage; biasing the second well area with the first supply voltage; cutting off the first supply voltage applied to the second well area in order to make the second well area retain a floating state; biasing the second well area with a coupling voltage lower than the first supply voltage through a coupling capacitance between the second well area and the common source line, and a coupling capacitance between the second well area and the first well area; and supplying a program voltage to one of the plurality of wordlines, while the floating second well area is biased with the coupling voltage.