Patent ID: 6779125
Filing Date: 2004-08-17
Classification: H03K

Abstract:
A clock generator for generating a plurality of clock signals differing in frequency from a base signal having a predetermined frequency comprising:a first phase-locked loop (PLL) sequentially and changeably selected as a first PLL stage among a set of symmetrically selectable phase-locked loops for multiplying said frequency of said base signal by a first factor to generate a first signal having a first selected frequency; a divider selectively coupled to said first phase locked-loop for dividing said first frequency of said first signal by a second factor to generate a second signal having a second selected frequency; a second phase-locked loop sequentially and changeably selected as a second PLL stage among said set of symmetrically selectable phase-locked loops for multiplying said second frequency of said second signal by said first factor to generate a third signal having a third selected frequency; and a plurality of dividers for selectively dividing said first and third frequencies of said first and third signals to generate said plurality of clock signals.