Patent ID: 6707719
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell having n states including state â€œ0â€ , state â€œ1â€ , and state â€œnâˆ’1â€ (2a first data storage circuit which stores input data, said data are of a first logic level or of a second logic level; a write circuit which modifies the state of the memory cell from state â€œiâˆ’1â€  to state â€œiâ€  when the data of said first data storage circuit is the first logic level and which holds the state of the memory cell when the data of said first data storage circuit is of the second logic level; a write verify circuit which verifies the state of said memory cell modified by the write circuit, said write verify circuit being set a threshold voltage higher than a voltage corresponding to the modified state when the state of the memory cell is verified; and a second data storage circuit, connected to said first data storage circuit which stores data of one of the first and second logic level when the voltage of the memory cell is higher than the threshold voltage verified by the write verify circuit.