Patent ID: 6882202
Filing Date: 2005-04-19
Classification: G11C

Abstract:
1. An integrated circuit for providing a multiple trip point latch device for evaluating the state of a fuse link comprising: the fuse link having a first terminal and a second terminal; a first FET (field effect transistor) having a first one of its source and drain coupled in the first terminal of the fuse link, and a second on of its source and drain coupled to a data in node; a first read input control signal coupled to a control input of the FET for switching said first FET to one of an ON state and an OFF state during a selected read time period; a second FET having its source and drain connected in parallel with said first FET; a second read input signal coupled to a control input of the second FET for switching said second FET to one of an ON state and an OFF state during the selected read time period; a latch circuit having an input terminal coupled to the data in node, and having a data out terminal; a first electrical path extending from said second terminal of said fuse link, through said fuse link and through said FET to said data in node when said first read input control signal switches said first FET to said ON state and second read input control signal switches said second FET to said OFF state, said first electrical path defining a first resistance value and setting a first trip point; and a second electrical path extending from said terminal of said fuse link, through said fuse link and through both said first and said second FETs connected in parallel said data in node when said first read input control signal switches said first FET to said ON state and said second read input control switches said second FET to said ON state, said second electrical path defining a second resistance value and setting a second trip point.