Patent ID: 6473356
Filing Date: 2002-10-29
Classification: G11C

Abstract:
A low power read operation method for a memory circuit, comprising the steps:enabling a wordline pursuant to commencing a memory read cycle with respect to a particular cell in said memory circuit based on a plurality of address signals; waiting for a first selected period of time until a voltage level on a bitline of a pair of complementary bitlines associated with said particular cell substantially reaches a predetermined sense level responsive to said wordline being driven high; disabling said wordline so as to stop driving said pair of complementary bitlines; waiting for a second selected period of time until a sense amplifier operable with said pair of complementary bitlines substantially reaches said predetermined sense level by a charge redistribution between said sense amplifier and said bitline; enabling said sense amplifier for sensing a data value based on said predetermined sense level developed thereon; and commencing a precharging operation to precharge said bitline substantially at the same time when said sense amplifier is enabled.