Patent ID: 6352741
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A method of fabricating a planar integrated circuit having a superconductive via contact between different superconducting layers in a single high temperature superconducting oxide film, said method comprising:depositing a layer of oxide superconducting film on a substrate; forming a first interconnect layer in lower portions of the film including the step of bombarding selected portions of the film with ions at a first energy level to transform said portions into non-superconducting regions, said first interconnect layer having a superconducting contact of given width and adjacent non-conducting regions; forming a second layer in the same film by bombarding selected portions of the film with ions at a second energy level, less than said first energy level, to transform portions of the film above said first layer into non-superconducting regions, said second layer having a second superconducting contact overlying the first superconducting contact in the first layer, said second superconducting contact having adjacent non-superconducting regions; thereafter, forming a third interconnect layer including the step of bombarding selected portions of the same film with ions at a third energy level, less than the second energy level, to transform portions of the film above the second layer into non-superconducting regions, said third layer having a third superconducting contact overlying the second superconducting contact, and said third superconducting contact having adjacent non-superconducting regions; and whereby the second superconducting contact serves as a via between the first and second superconducting contacts, the integrated circuit having substantially the same crystal lattice structure throughout the film.