Patent ID: 6091304
Filing Date: 2000-07-18
Classification: H03J,H03L

Abstract:
A phase lock loop (PLL) device, comprising:a phase and frequency detector coupled to a frequency reference signal having a first frequency and to a second input frequency signal for generating an output error signal based on frequency and phase information contained in the frequency reference signal and the second input frequency signal;a filter and compensation circuit coupled to the output error signal of the phase and frequency detector, the filter and compensation circuit including a first low-pass filter for generating a first feedback signal, and a second low-pass filter for generating a second feedback signal based on the error signal;a controller coupled to the second feedback signal for generating a frequency adjust signal; anda voltage controlled oscillator (VCO) coupled to the first feedback signal and to the frequency adjust signal for generating an output frequency signal to be provided to the phase and frequency detector as its second input frequency signal, the output frequency signal having a second frequency which is controlled by both the first feedback signal and the frequency adjust signal;whereby the phase and frequency detector, the filter and compensation circuit and the voltage controlled oscillator form a phase lock loop to lock the second frequency to the first frequency.