Patent ID: 6180426
Filing Date: 2001-01-30
Classification: G01R,H01L

Abstract:
A method of forming a multiple integrated circuit chip structure comprising the steps of:simultaneously but separately forming internal circuits on a first semiconductor wafer containing plural first integrated circuit chips and a second semiconductor wafer containing plural second integrated circuit chips;simultaneously forming test circuits on the first wafer and the second wafer;simultaneously forming interchip interface circuits on the first wafer and the second wafer, whereby forming said interchip interface circuit comprises the steps of:forming an internal interface circuit for transferring electrical signals between a second integrated circuit chip to a first integrated circuit chip;forming a mode select switch having a first terminal connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry of the first integrated circuit chip;forming a mode selector to selectively connect the output of the internal interface circuit to the internal circuitry of the first integrated circuit chip during normal operation and the output of the internal interface circuit to the test circuitry during test and burn-in;forming input/output interface circuits on said second wafer;contacting, stimulating, and examining a response of the test circuits on the first wafer and the test circuits and input/output interface circuits on the second wafer;separating the first wafer into a plurality of separated first integrated circuit chips;contacting with sockets, stimulating and burning-in the plurality of separated first integrated circuit chips for an extended period of time;contacting, stimulating, and examining the plurality of separated first integrated circuit chips;discarding defective first integrated circuit chips;attaching each functioning chip of the first integrated circuit chips to a functioning second integrated circuit chip on the second wafer;separating the second wafer into the plurality of second integrated circuit chips; andcontacting the input/output interface circuits, stimulating, and examining the response of the formed multiple integrated circuit chip structure.