Patent ID: 6785188
Filing Date: 2004-08-31
Classification: G11C

Abstract:
A memory structure, comprising:a memory array; at least one address register, the at least one address register latching an address on a rising edge of a clock signal; at least one data register, the at least one data register latching a data word on the rising edge of the clock signal; a logic circuit coupled to the memory array, the at least one address register, and the at least one data register, wherein, the logic circuit operates in a write operation such that a write address is presented to the at least one address register in a first write clock cycle and a write data word is presented to the at least one data register in a second clock cycle following the first write clock cycle by a predetermined number of clock cycles; and wherein the logic circuit operates in a read operation such that a read address is presented in a first read clock cycle and a read data word corresponding to the read address is presented to an output buffer in a second read clock cycle following the first read clock cycle by the predetermined number of clock cycles.