Patent ID: 7548463
Filing Date: 2009-06-16
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory array configured to include a plurality of nonvolatile memory cells arranged in a matrix form and a plurality of word lines; and an X-decode section configured to select a selected word line selected from said plurality of word lines, supply a negative voltage to said selected word line, and supply a positive voltage to unselected word lines which are not said selected word line, at the time of an erase operation, wherein said X-decode section includes: a plurality of output drivers configured to be provided corresponding to said plurality of word lines, each of said plurality of output drivers outputs at least one of said negative voltage and said positive voltage, a negative voltage decoder configured to supply said negative voltage to said plurality of output drivers, and a positive voltage decoder configured to supply said positive voltage to said plurality of output drivers, wherein each of said plurality of output drivers, based on a word line selection signal for selecting one of said plurality of word lines and a voltage selection signal for selecting one of said negative voltage and said positive voltage, supplies voltage corresponding to said voltage selection signal to corresponding one of said plurality of word lines, wherein said voltage selection signal includes a negative-voltage selection signal for selecting said negative voltage and a positive-voltage selection signal for selecting said positive voltage, wherein said each of the plurality of output drivers includes: a first transistor configured to receive said word line selection signal at a gate, be connected to a first node at one terminal and a second node at another terminal, and be a first conductive type, a second transistor configured to receive said positive-voltage selection signal at a gate, be connected to said first node at one terminal and said second node at another terminal, and be said first conductive type, a third transistor configured to receive said word line selection signal at a gate, be connected to said second node at one terminal and a third node at another terminal, and be a second conductive type, and a fourth transistor configured to receive said negative-voltage selection signal at a gate, be connected to said second node at one terminal and said third node at another terminal, and be said second conductive type, wherein said first node receives said positive voltage, said third node receives said negative voltage, and said second node is connected to corresponding one of said plurality of word lines.