Patent ID: 6207554
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A method for fabricating multilevel metal interconnections having low dielectric constant insulators on a substrate comprising the steps of:providing a semiconductor substrate having semiconductor devices in and on said substrate;depositing a first insulating layer over said devices, and further having contact openings in said first insulating layer for electrical contacts to said devices;forming a metal barrier layer on said insulating layer and in said contact openings;depositing a first conductive layer for contacting said contact openings;patterning said first conductive layer and said metal barrier layer to form first metal lines as interconnections for said devices;coating a layer of low dielectric constant insulating material on and in between said patterned interconnect metal lines;curing the low dielectric constant material;depositing thin layer of an adhesion promoter and stabilizing material on the low dielectric constant material;depositing a silicon oxide cap layer on the adhesion promoter and over the low dielectric constant material;planarizing the oxide surface with chemical mechanical polish (CMP);defining via openings and etching to open electrical contacts to the underlying interconnect metal;depositing conductive metal over the via openings;removing the excess said conductive metal by CMP;patterning of said conductive layer to form the next level of metal interconnections.