Patent ID: 7312663
Filing Date: 2007-12-25
Classification: H03L

Abstract:
1. An integrated circuit including a phase-locked loop (PLL) circuit, the PLL circuit having a loop bandwidth, comprising: a phase/frequency detector (PFD) configured to generate an error signal that is proportional to the difference between the phase of a PLL input signal and the phase of a signal coupled to a feedback input; a feedback path, through which the PLL output clock is coupled to the feedback input of the PFD; a charge pump coupled to the output of the PFD that generates a current that is proportional to the error signal output by the PFD; a loop filter coupled to the output of the charge pump, which filters the charge pump current and generates a loop filter voltage; a voltage-controlled oscillator (VCO), which is coupled to the loop filter output, and which generates a PLL output clock, wherein the frequency of the PLL output clock is proportional to a non-zero real power of a VCO bias current; and wherein the VCO includes a current scaling block for scaling the sum of a VCO control current, which is proportional to the loop filter voltage, and a fixed reference current by a scaling factor to generate the VCO bias current, wherein the current scaling block has a center frequency control input for selecting the scaling factor; and wherein the VCO has a characteristic gain from the loop filter voltage to the frequency of the PLL output clock; and wherein said VCO bias current adjusts the frequency of the PLL output clock in such a way that the gain of the VCO is proportional to the PLL output frequency and the loop bandwidth of the PLL circuit is proportional to the frequency of the PLL input signal.