Patent ID: 6441491
Filing Date: 2002-08-27
Classification: C23C,H01L

Abstract:
An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising:a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material; a first region of conductor embedded in a second layer of insulating material formed of an ultralow-k material, said ultralow-k material comprising Si, C, O and H, and a multiplicity of nanometer-sized pores, said ultralow-k material having a dielectric constant of not more than about 2.8, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal; and a second region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material comprising said ultralow-k material, said third layer of insulating material being in intimate contact with said second layer of insulating material.