Patent ID: 6010931
Filing Date: 2000-01-04
Classification: H01L

Abstract:
A method of forming a DRAM, comprising the steps of:providing a substrate having device isolation structures formed thereon, wherein an active device region is defined between the device isolation structures;providing a gate oxide layer on the substrate over the active device region;providing first and second transfer transistors in the active device region, whereinthe first transfer transistor includes a first gate electrode disposed over the gate oxide layer, first spacers on sidewalls of the first gate electrode, and first and second source/drain regions,the second transfer transistor includes a second gate electrode disposed over the gate oxide layer, second spacers on sidewalls of the second gate electrode, the second source/drain region, and a third source/drain region,such that the first transfer transistor and the second transfer transistor share the second source/drain region, andsurfaces of the first, second, and third source/drain regions are exposed;forming an etch stop layer on the first and second gate electrodes, the first and second spacers, and the exposed surfaces of the first, second, and third source/drain regions;forming a dielectric layer over the etch stop layer, wherein the dielectric layer has a composition that is different than a composition of the etch stop layer;planarizing a surface of the dielectric layer;etching through the dielectric layer above the first and third source/drain regions, stopping the etching process on the etch stop layer, performing a further etching process to etch through the etch stop layer, and then forming a lower electrode in contact with the first and third source/drain regions, having a rugged surface; andsequentially forming a high dielectric constant dielectric layer and an upper electrode on the lower electrode to form a charge storage capacitor.