Patent ID: 6801072
Filing Date: 2004-10-05
Classification: H03L

Abstract:
A circuit for generating a digital output signal locked to a phase of an input signal, comprising:control logic having a first input for receiving the input signal; a first register containing a first value coupled to an output of the control logic; a second register containing a second value coupled to the output of said control logic; a plurality of serially-coupled delay cells; a plurality of flip-flop devices; a demultipexer having an input coupled to an output of the first register and an output coupled to an input of each of the flip-flop devices, the demultiplexer receiving a control signal from said control logic; a plurality of adder nodes having a first input coupled to an output of a corresponding flip-flop device, a second input coupled to an output of said second register, and an output coupled to an input of a corresponding delay cell; a phase detector having a first input coupled to one of the delay cells and a second input for receiving the input signal; a digital filter having an input coupled to an output of the phase detector and an output coupled to a second input of the control logic; and an output coupled to an output of one of the delay cells for generating an output signal.