Patent ID: 7282960
Filing Date: 2007-10-16
Classification: H03K

Abstract:
1. A dynamic logic gate, comprising: a clock signal input for receiving a clock of said dynamic logic gate, said clock signal having a voltage swing between voltage states substantially equal to voltages of a first and second power supply rail of said dynamic logic gate; a control signal input for receiving a control signal having edges substantially synchronous with edges of said clock signal and a control voltage swing between an asserted voltage state substantially equal to said voltage of said first power supply rail and a de-asserted voltage state substantially differing from said voltage of said second power supply rail in a direction of said first power supply rail; a dynamic logic tree for discharging said summing node in response to a predetermined states of one or more logical input signals connected to inputs of said dynamic logic tree; a pre-charge circuit connected to said summing node and a second power supply rail for setting said summing node to a pre-charge voltage level corresponding to a second logical state opposite from said first logical state, said pre-charge circuit having an input connected to said control signal, whereby said summing node is held in said second logical state while said control signal is de-asserted and retained in said second logical state until altered by conduction through said dynamic logic tree due to predetermined states of said one or more logical input signals; and an inverter having an input coupled to said summing node and an output providing an output signal of said dynamic logic gate.