Patent ID: 6892365
Filing Date: 2005-05-10
Classification: G06F

Abstract:
1. A method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer comprising: providing design configurations for circuit portions to be lithographically produced on layers of a semiconductor wafer; predicting shape and alignment for each design configuration for the circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error during lithographic manufacturing of the circuit portions on the adjacent layers of the semiconductor wafer; determining dimension of overlap of the predicted shape and alignment of the circuit portions on the adjacent layers of the semiconductor wafer; comparing the determined dimension of overlap of the predicted shape and alignment of the circuit portions to a theoretical minimum required dimension of overlap of the circuit portions to determine whether the dimension of overlap of the predicted shape and alignment of the circuit portions fails; using different process fluctuation values and misalignment error values, iteratively repeating the aforementioned steps on the provided design configurations for the circuit portions to determine whether the dimension of overlap of the predicted shape and alignment of the circuit portions fails; and reporting a measure of failures of dimension of overlap for the predicted shape and alignment of the provided design configurations for circuit portions.