Patent ID: 6493818
Filing Date: 2002-12-10
Classification: G06F

Abstract:
An apparatus for synchronization of a signal in a first clock domain to a second clock domain asynchronous with said first clock domain, said apparatus comprising:a plurality of synchronizer stages, each synchronizer stage having a first clock input receiving a first clock signal of said first clock domain, a second clock input receiving a second clock signal of said second clock domain, a first domain input for receiving a first domain input signal synchronous with said first clock signal and a second domain output supplying a second domain output signal responsive to said first domain input signal and synchronous with second clock signal; a write pointer storing therein an indication of one of said plurality of synchronizer stages as a write stage, said write pointer enabling said one of said plurality of synchronizer stages to input a first domain input signal upon receipt of said first domain input signal and thereafter incrementing said stored indication of said write stage to indicate a next synchronizer stage in a circular sequence of said plurality of synchronizer stages; and a read pointer storing therein an indication of one of said plurality of synchronizer stages as a read stage, said read pointer enabling said one of said synchronizer stages to output said second domain output signal upon synchronization with said second clock signal and thereafter incrementing said stored indication of said read stage to indicate said next synchronizer stage in said circular sequence of said plurality of synchronizer stages; whereby plural first domain input signals may simultaneously be in various states of synchronization with said second clock signal in corresponding ones of said synchronization stages.