Patent ID: 6526536
Filing Date: 2003-02-25
Classification: G01R,G06F

Abstract:
An integrated circuit comprising a test mode detection circuit, the test mode detection circuit comprising:a test triggering signal input terminal for receiving a test triggering signal; a data input terminal for receiving test data signals; a memory for storing a test data pattern; a comparator coupled to the memory and the data input terminal for comparing the test data signal and the test data pattern to produce a comparison signal; a first AND gate coupled to the data input terminal and the comparator for generating the comparison signal; a D-type flip flop having a D input and coupled to the first AND gate for delaying the comparison signal and for reproducing the comparison signal at its Q output after a predetermined time period; and a second AND rate coupled to the Q output of the flip flop for generating a test mode start-up signal to cause the integrated circuit to enter a test mode.