Patent ID: 7109558
Filing Date: 2006-09-19
Classification: H01L,Y10S

Abstract:
1. A power MOS transistor formed as an array of source cells having respective source electrodes thereof connected in common and drain cells having respective drain electrodes thereof connected in common, and an array of gate electrodes which are connected in common, within a transistor formation area on a substrate, said power MOS transistor including a substrate region of a first conduction type extending within said substrate from an upper face of said substrate, a channel region of a second conduction type, formed in said substrate region, extending from said upper face, a plurality of source regions of the first conduction type, formed in said channel region and corresponding to said source cells, a plurality of drain regions of the first conduction type, respectively corresponding to said drain cells and extending from said upper face, said gate electrodes, each formed above said upper face, covering at least a part of said channel region and separated therefrom by a gate insulation film, and said source electrodes, each formed above said upper face, disposed in contact with said source regions through respective ones of said contact holes; wherein said power MOS transistor comprises a plurality of substrate contact cells, a plurality of body contact regions respectively corresponding to said substrate contact cells, and respective substrate potential-setting electrodes for use in setting a substrate potential of said channel region through said respective body contact regions, wherein each said body contact region is located separate from said areas occupied by said source regions, wherein each potential-setting electrode is separate from said source electrodes, and wherein said channel region is disposed surrounding each of said source regions and spaced apart from each of said drain regions.