Patent ID: 6775760
Filing Date: 2004-08-10
Classification: G06F

Abstract:
An integrated circuit, comprising:a field programmable gate array and a memory device; and logic data for effecting functions of a CPU core and peripheral circuits connected thereto being stored into said memory device such that said field programmable gate array performs functions as said CPU core and peripheral circuits based on contents stored in said memory device, wherein arithmetic processing executed by said CPU core has a structure that a dummy step is incorporated into steps of fetch, decode, execution, memory and write-back, wherein said steps are divided into three stages: a first stage for carrying out in order of fetch and decode, a second stage for carrying out in order of execution and memory, and a third stage for carrying out in order of dummy and write-back, wherein the processing is carried out in order of first, second and third stages, and wherein, every time one stage is completed, another arithmetic processing is started, and simultaneous operations of different arithmetic processing are executed parallel in the three-stage pipeline construction.