Patent ID: 9034753
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A method, comprising: forming a conductive logic contact in a logic area of a semiconductor device; forming a bit line contact and a capacitor contact in a memory array of said semiconductor device; performing at least one common process to form a conductive line in said logic area that is conductively coupled to said conductive logic contact and to form a bit line in said memory array that is conductively coupled to said bit line contact, said conductive line and said bit line being positioned at least partially within a first layer of insulating material; forming at least one additional layer of insulating material above said conductive line in said logic area and above said bit line in said memory array; performing at least one etching process to define an opening that extends through said at least one additional layer of insulating material and said first layer of insulating material and exposes said capacitor contact in said memory array; and forming a conductive structure in said opening that is conductively coupled to said capacitor contact.