Patent ID: 7580497
Filing Date: 2009-08-25
Classification: H03B,H03K,H03L,H04L

Abstract:
1. A loop circuit for clock data recovery over a wide range of data rates, said loop circuit comprising: a signal generator for generating an output of said loop circuit; a phase detector accepting as inputs said output and a data signal, and providing at least one phase error signal; a charge pump responsive to said at least one phase error signal; a loop filter charged up by said charge pump and comprising a resistor and a capacitor and providing a loop filter output for input to said signal generator; a bypass circuit for controllably bypassing said resistor in a first range of data rates; and an alternate path, separate from said bypass circuit, for controllably conducting said phase error signal to said signal generator when said resistor is bypassed, said alternate path bypassing said charge pump and said loop filter; whereby: in a second range of data rates lower than said first range of data rates said resistor is not bypassed and serves as a proportional path of said loop circuit; and in said first range of data rates said alternate path serves as a separate proportional path.