Patent ID: 6349374
Filing Date: 2002-02-19
Classification: G06F

Abstract:
A memory control apparatus for a digital signal processor (DSP) having a pipeline structure, comprising:a ROM (Read Only Memory) for storing an execution program therein; a data storing block composed of a plurality of RAMs (Random Access Memories) for storing data therein; a decoder for decoding an instruction and associated data and outputting a control code, an address and the associated data; a memory management unit; a judging unit for comparing the control code and the address outputted from the decoder with a previously stored control code and address, respectively, outputting an enable signal if the compared addresses are the same based on the comparison, and outputting the previously stored control code and address to the memory management unit if the compared addresses are not the same; and a cache memory for storing the associated data from the decoder, outputting the stored data to the outside through a data bus in accordance with a logic state of the enable signal and outputting the stored data to the memory management unit; wherein the memory management unit receives the previously stored control code and address from the judging unit and the stored data from the cache memory and controls data transfer to and from the data storing block and ROM.