Patent ID: 6310501
Filing Date: 2001-10-30
Classification: H03K

Abstract:
A latch circuit comprising:a delaying inverter circuit for inverting a clock signal with a predetermined delay;a precharging circuit for precharging first and second nodes of said latch circuit to a predetermined potential during a time period in which the clock signal is at a first logic level;a first amplifier circuit for providing a potential difference between said first and second nodes in response to an input signal during a first time period in which the clock signal and an output signal of said delaying inverter circuit are at a second logic level, wherein said first amplifier means comprises a first transistor group and a second transistor group for pulling out one of charges of said first and second nodes during the first time period;second amplifier circuit for amplifying the potential difference between said first node and said second node during a second time period; anda flip-flop circuit adapted to be set and reset according to the potentials at the first and second nodes,wherein said first amplifier circuit comprises:a first transistor group including a first transistor having a gate supplied with the input signal, a second transistor having a gate supplied with the clock signal and a third transistor having a gate supplied with an output of said delaying inverter circuit, said first, second and third transistors being connected in series between said first node and a power source; anda second transistor group including a fourth transistor having a gate supplied with an inverted signal of the input signal, a fifth transistor having a gate supplied with the clock signal and a sixth transistor having a gate supplied with the output signal of said delaying inverter circuit, said fourth, fifth and sixth transistors being connected in series between said second node and said power source.