Patent ID: 6221733
Filing Date: 2001-04-24
Classification: H01L,Y10S

Abstract:
A method for minimizing mechanical stress in a standard shallow trench isolation process, comprising the steps of:providing a semiconductor substrate;forming an epitaxial layer on a top surface of said semiconductor substrate;forming a pad oxide layer on a top surface of said epitaxial layer;depositing a nitride layer on a top surface of said pad oxide layer;etching a plurality of trenches through said nitride layer and said oxide layer and into said epitaxial layer so as to create isolation regions in order to electrically isolate active regions in said epitaxial layer;forming a liner oxide layer on sidewalls and bottom of said trenches to enhance isolation;filling completely said trenches with a trench-filling material having a less volume shrinkage coefficient than an ozone-TEOS film to form an oxide layer;polishing away said trench-filling oxide layer down to the top surface of said nitride layer; andperforming a thermal annealing on said substrate subsequent to the step of polishing away said trench-filling oxide layer.