Patent ID: 8650386
Filing Date: 2014-02-11
Classification: G06F

Abstract:
1. A data processor, comprising: a first register file including a plurality of registers; a second register file including a plurality of registers, a number of which is larger than that of the registers of the first register file; an instruction decoder; and an operation unit, wherein: the instruction decoder is configured to decode an instruction described in first and second instruction formats which are different from each other, the first instruction format includes a first register-addressing field for designating the first register file, the second instruction format includes a second register-addressing field for designating the second register file, a size of which is larger than that of the first register-addressing field, the operation unit is configured to execute an instruction described in the first and second instruction formats using operand data stored in the first and second register files, respectively, in accordance with the instruction decoder, and the operation unit is configured to execute one or more operations in parallel, a number of which is determined by a certain field included in the second instruction format.