Patent ID: 8699550
Filing Date: 2014-04-15
Classification: H04L

Abstract:
1. An integrated circuit comprising at least one of (A) transmit (TX) circuitry in a TX clock domain having a TX clock signal and (B) receive (RX) circuitry in an RX clock domain (i) different from the TX clock domain and (ii) having an RX clock signal, wherein: the TX circuitry comprises: TX logic configured to generate a TX data signal; a pattern generator configured to generate a TX pattern signal; and one or more TX registers configured to transmit the TX data signal and the TX pattern signal based on the TX clock signal to the RX circuitry; and the RX circuitry comprises: one or more RX registers configured to receive the TX data signal and the TX pattern signal transmitted from the TX circuitry and output an RX data signal and an RX pattern signal based on a selected RX clock signal of the RX clock domain; receive logic configured to process the RX data signal; a pattern checker configured to determine whether the RX pattern signal represents a valid pattern; a multi-phase clock source configured to generate a plurality of phase-shifted versions of the RX clock signal; a clock multiplexer (mux) configured to receive the plurality of phase-shifted versions of the RX clock signal and output the selected RX clock signal based on a clock mux control signal; and a controller configured to receive the determinations of the pattern checker for different phase-shifted versions of the RX clock signal and generate the clock mux control signal.