Patent ID: 7928950
Filing Date: 2011-04-19
Classification: G09G,H03K

Abstract:
1. A data latch circuit comprising: a first n-channel transistor; a second n-channel transistor connected in series to the first n-channel transistor; a first p-channel transistor; a second p-channel transistor; a first analog switch; a second analog switch; a third analog switch; and an inverter, wherein a gate electrode of the second n-channel transistor and a gate electrode of the first p-channel transistor are connected to each other; wherein a first electrode of the first p-channel transistor and a first electrode of the second p-channel transistor are connected to a first power source, wherein a first electrode of the second n-channel transistor is connected to a second power source, wherein a second electrode of the second n-channel transistor is connected to a first electrode of the first n-channel transistor, wherein a second electrode of the first n-channel transistor, a second electrode of the first p-channel transistor, an input terminal of the inverter, and a second electrode of the second p-channel transistor are connected to each other, wherein one of an input terminal or an output terminal of the second analog switch and one of an input terminal or an output terminal of the third analog switch are connected to an output terminal of the inverter, wherein the other of the input terminal or the output terminal of the second analog switch and the other of the input terminal or the output terminal of the third analog switch are respectively connected to the gate electrodes of the second p-channel transistor and the gate electrode of the first n-channel transistor, wherein the gate electrode of the first n-channel transistor is connected to one of an input terminal or an output terminal of the first analog switch, and wherein an input signal is inputted to the other of the input terminal or the output terminal of the first analog switch.