Patent ID: 7495990
Filing Date: 2009-02-24
Classification: G11C

Abstract:
1. A semiconductor dynamic random access memory device comprising: a first memory block that includes a plurality of word lines and at least a pair of first bit-lines coupled to a plurality of dynamic memory cells that require a refresh operation to restore data; a second memory block that includes a plurality of word lines and at least a pair of second bit-lines coupled to a plurality of dynamic memory cells that require a refresh operation to restore data; a sense amplifier coupled to a pair of sense amplifier active lines, the pair of sense amplifier active lines being initialized to a third voltage level of a third signal; a first separation gate coupled between the sense amplifier and the pair of first bit-lines; a second separation gate coupled between the sense amplifier and the pair of second bit-lines; and a first equalizing unit coupled to the pair of first bit-lines and configured to equalize the pair of first bit-lines in response to a first signal having a first voltage level; a second equalizing unit coupled to the pair of second bit-lines and configured to equalize the pair of second bit-lines in response to the first signal; and a third equalizing unit coupled to the pair of sense amplifier active lines and configured to equalize the pair of sense amplifier active lines in response to a second signal having a second voltage level the second voltage level being different from the first voltage level.