Patent ID: 8468434
Filing Date: 2013-06-18
Classification: H03M

Abstract:
1. An error detection and correction system, comprising: an encoding unit configured to generate a check bit based on an information bit, wherein the check bit and the information bit are stored in a memory cell array; a syndrome calculating unit configured to calculate a syndrome based on read data from the memory cell array; a syndrome element calculating unit configured to perform a calculation for expressing coefficients of an error search equation corresponding to the read data by Galois field elements; an error search unit configured to solve the error search equation based on a calculation result of the syndrome element calculating unit, and thereby obtain an error bit position; and an error correction unit configured to perform an error bit correction of the read data, reading and writing of the memory cell array being performed concurrently for m bits, and error detection and correction being performed in data units of M bits (where M is an integer multiple of m), and the encoding unit and the syndrome calculating unit sharing a time-division decoder for performing data bit selection according to respective tables of check bit generation and syndrome generation, the time-division decoder being configured to repeat multiple cycles of m bit concurrent data input.