Patent ID: 6146962
Filing Date: 2000-11-14
Classification: H01L

Abstract:
A method for forming a dynamic random-access-memory (DRAM) cell with a stacked capacitor in a substrate of a first conductivity type, the cell including:an access transistor having:spaced-apart source and drain regions of a second conductivity type formed in the substrate,a channel region defined in the substrate between the source and drain regions,a layer of gate oxide formed above the channel region, anda gate formed on the layer of gate oxide from a first layer of polysilicon (poly-1); anda layer of insulation material formed to contact the gate and the source and drain regions, the layer of insulation material being free of a layer of silicon nitride;the method comprising the steps of:forming a second layer of polysilicon (poly-2) on the layer of insulation material to contact the layer of insulation material;forming a first layer of sacrificial material on the layer of poly-2;forming a third layer of polysilicon (poly-3) on the first layer of sacrificial material;forming a second layer of sacrificial material on the layer of poly-3;selectively etching the second layer of sacrificial material, the layer of poly-3, the first layer of sacrificial material, the layer of poly-2, and the layer of insulation material to form a contact opening that exposes a contact area on the surface of the drain region, the contact opening having sidewalls; andforming a fourth layer of polysilicon (poly-4) on the second layer of sacrificial material, the sidewalls of the contact opening, and the contact area.