Patent ID: 6087202
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A process for manufacturing semiconductor packages comprising: a substrate, a chip comprising an integrated circuit attached to at least one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulating encasement, the process comprising the steps of:producing, in a matrix configuration, a plurality of groups of connection regions on a common substrate plate, each group corresponding to a chip attachment region;attaching a chip to each attachment region of the common substrate plate;electrically connecting each chip to the associated electrical connection regions, so as to obtain an assembly consisting of the substrate plate and the connected chips;placing the assembly in an injection mold and injecting an encasement material into the mold so as to obtain, in a single molding operation, a parallelepipedal block, the mold having a cavity for receiving the common substrate plate and a cavity surrounding the connected chips on the substrate plate;depositing balls or beads of a soldering material on the connection regions;adhesively bonding that face of the parallelepipedal block which is free of connection regions to a peelable self-adhesive strip; andcutting the parallelepipedal block into units by engaging a saw across the block through its thickness, each unit constituting a semiconductor package,wherein the cutting step is performed while the parallelepipedal block is bonded to the strip.