Patent ID: 8463834
Filing Date: 2013-06-11
Classification: G06F

Abstract:
1. Apparatus for performing a floating point multiply operation whereby a first floating point operand A is multiplied by a second floating point operand B to generate a floating point result C, said apparatus comprising: partial product generation circuitry configured to receive said operand A and said operand B and to generate from said operand A and said operand B a plurality of partial products representing said result C; reduction circuitry configured to receive said plurality of partial products and to reduce said plurality of partial products to a first partial product and a second partial product; shifting circuitry configured to receive said first partial product and said second partial product and to shift said first partial product and said second partial product by a shift amount to an alignment matching said result C; adder circuitry configured to receive said first partial product and said second partial product as shifted by said shift circuitry and to add said first partial product, said second partial product and a rounding value to round to a predetermined bit position to generate said result C; and wherein said shifting circuitry comprises a first shifter configured to receive said first partial product and to shift said first partial product by said shift amount and a second shifter configured to receive said second partial product and to shift said second partial product by said shift amount.