Patent ID: 8913419
Filing Date: 2014-12-16
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a bit line; four or more word lines; a first sub bit line; a second sub bit line; a first transistor; a second transistor; a third transistor; a fourth transistor; a first inverter, wherein an output terminal of the first inverter is electrically connected to the bit line through the first transistor; a second inverter, wherein an output terminal of the second inverter is electrically connected to the bit line through the second transistor; and a first memory block and a second memory block each including two or more memory cells, wherein the first memory block is electrically connected to the first sub bit line and the second memory block is electrically connected to the second sub bit line, wherein the first sub bit line is electrically connected to an input terminal of the first inverter and the third transistor, wherein the output terminal of the first inverter is electrically connected to the second sub bit line through the fourth transistor, wherein the second sub bit line electrically connected to the second memory block is electrically connected to an input terminal of the second inverter, and wherein the output terminal of the second inverter is electrically connected to the first sub bit line through the third transistor.