Patent ID: 8467220
Filing Date: 2013-06-18
Classification: H01L

Abstract:
1. A DRAM device comprising: plural word lines arranged parallel to each other in one direction; plural bit lines arranged parallel to each other and in an intersecting manner to the word line; and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor in which a gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells, and the gate terminal is connected electrically to the word line and a drain terminal of the transistor is connected electrically to the bit line wherein the gate terminal connected to one word line is arranged alternately to the gate terminal connected to an adjoining word line, and the drain terminal connected to one bit line is arranged alternately to the drain terminal connected to an adjoining bit line, and the gate terminal of the transistor of two adjoining memory cells in a direction of bit line is connected electrically with respect to the word line, and the drain terminal of the transistor of two adjoining memory cells in a direction of the word line is connected electrically with respect to one bit line, wherein an interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.