Patent ID: 7916554
Filing Date: 2011-03-29
Classification: G06F,G11C

Abstract:
1. A method for performing successive read and write accesses in a memory device comprising: receiving data and an address for a write access; pipelining said address and said data of said write access to delay the processing of said address and said data by the memory device; receiving an address for a read access; comparing said address of said read access with said pipelined address of said write address to determine if there is a match; and in response to determining a match between said address of said read access with said address of said write address, providing said pipelined data of said write access as data for said read access, wherein said pipelining includes adding a same number of clock cycles between said address and said data of said write access as the number of clock cycles between said receipt of said address of said read access and said providing data.