Patent ID: 6711068
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A memory, comprising:a first sub-array having a first portion and a second portion; a second sub-array having a first portion and a second portion; a first column decoder adjacent to the first sub-array having a first data line adjacent to the first portion of the first sub-array and a second data line adjacent to the second portion of the first sub-array; a second column decoder adjacent to the second sub-array having a first data line adjacent to the first portion of the second sub-array and a second data line adjacent to the second portion of the second sub-array; a first reference line in the first portion of the first sub-array for carrying a first reference type and for being coupled to the first data line of the second column decoder; a second reference line in the second portion of the first sub-array for carrying a second reference type and for being coupled to the second data line of the second column decoder; a third reference line in the first portion of the second sub-array for carrying the first reference type and for being coupled to the first data line of the first column decoder; a fourth reference line in the second portion of the second sub-array for carrying the second reference type and for being coupled to the second data line of the first column decoder; a first sense amplifier; and a multiplexer having inputs coupled to the first and second data lines of the first column decoder and the first and second data lines of the second column decoder, a first reference output coupled to the first sense amplifier, and a first data output coupled to the first sense amplifier.