Patent ID: 8300753
Filing Date: 2012-10-30
Classification: H03L,H04L

Abstract:
1. A method comprising: at a clock and data recovery (CDR) circuit comprising a digital control circuit and an analog control circuit, accessing a reference clock having a reference clock frequency and a reference clock phase, the reference clock frequency being within a first predetermined frequency range of an input data bit frequency of an input data bit stream; generating an output clock having an output clock frequency and an output clock phase, the output clock frequency being a function of an analog control voltage setting and a frequency gain curve, there being a plurality of frequency gain curves over a predetermined analog control voltage range that do not intersect; fixing the analog control voltage setting to a predetermined analog control voltage within the predetermined analog control voltage range; using the digital control circuit to select one of the frequency gain curves within a second predetermined frequency range of the reference clock frequency at the analog control voltage setting fixed to the predetermined analog control voltage; using the analog control circuit to adjust the analog control voltage setting from the predetermined analog control voltage to adjust the output clock frequency to be within a third predetermined frequency range of the reference clock frequency, the third predetermined frequency range being smaller than the second predetermined frequency range; sampling the input data bit stream; and adjusting the output clock phase to be within a predetermined phase range of an input data bit phase of the input data stream.