Patent ID: 7164328
Filing Date: 2007-01-16
Classification: H03C,H04L

Abstract:
1. A direct digital amplitude modulator (DDAM) for generating an amplitude modulated signal; comprising: an n-bit digital input with n parallel inputs, an analog input, a clock input and an output; and an n-bit digital input signal fed to the n-bit digital input for direct digital amplitude modulation; and an analog input signal fed to the analog input to be modulated which can be an RF, IF or DC signal; and a clock input signal fed to the clock input synchronized with the digital input signal; and a clock delay line to produce delayed clock signals from the clock input signal with equal or unequal intervals in one period of the digital input signal; and a number of sub-switched current source units to be switched on or off according to the combinations of the digital input signal and the delayed clock signals to produce or to cancel quantized RF, IF or DC currents and/or voltages at the times precisely controlled by the delayed clock signals respectively; and a circuitry to combine the outputs of the sub-switched current source units, and in the simplest case the outputs of sub-switched current source units are just connected together to the output; and the said sub-switched current source units are grouped into n groups controlled by n-bit digital input signals respectively; and the values of currents and/or voltages generated by the said groups calculated by the lumped current and/or voltage values of the sub-switched current source units in every groups have binary weights in normal case but can be other weights if necessary; and the values of currents and/or voltages generated by the said sub-switched current source units in each group can be equal in the case of linear interpolation or unequal in the case of nonlinear interpolation depending on the interpolation function; and the effective clock frequency of the DDAM can be greatly increased by the above arrangement when the number of sub-switched current source units and also the number of delayed clocks increases to reduce alias signal components.