Patent ID: 8361856
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. A method of forming a memory cell, comprising: forming a pair of trenches in semiconductive material, the semiconductive material between the trenches comprising an elevationally inner source/drain portion, an elevationally outer source/drain portion, and an elevationally mid channel portion between the inner and outer source/drain portions; forming a pair of conductive data/sense lines within the trenches laterally over and electrically coupled to opposing sides of the inner source/drain portion of the semiconductive material; forming an access gate line elevationally outward of and spaced from the pair of conductive data/sense lines and laterally adjacent the mid channel portion of the semiconductive material, a gate dielectric being provided laterally between the access gate line and the mid channel portion of the semiconductive material; and forming a charge storage device electrically coupled to the outer source/drain portion.