Patent ID: 8264846
Filing Date: 2012-09-11
Classification: H01L,H05K

Abstract:
1. A device, comprising: a first integrated circuit die; a package substrate, the package substrate including: a top surface coupled to the first integrated circuit die; a bottom surface; multiple matrix layers comprising a ceramic material; recess side walls extending up from the bottom surface of the package substrate and a recessed surface, the recess side walls and recessed surface defining a cavity in the bottom of the package substrate; and electrically conductive traces and vias through the matrix layers, to provide an electrically conductive pathway from the top surface to the recessed surface in the cavity; and a first electrical device in the cavity, the first electrical device chosen from the group consisting of an array capacitor, and an in-silicon voltage regulator, the first electrical device being electrically connected to the first integrated circuit die by at least some of the electrically conductive traces and vias.