Patent ID: 8890191
Filing Date: 2014-11-18
Classification: H01L

Abstract:
1. A chip package, comprising: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a through-hole extending from the second surface to the first surface; a conducting layer disposed on the substrate; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer, and wherein there is no solder resist material contacting with the conducting layer and the light shielding layer on the second surface; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate, wherein the through-hole is partially filled with the light shielding layer such that a void is formed between a bottom of the through-hole and the light shielding layer in the through-hole, and wherein a portion of the conducting layer, which overlies both sidewalls and the bottom of the through-hole, directly contacts the void.