Patent ID: 7957497
Filing Date: 2011-06-07
Classification: H04L

Abstract:
1. A clock and data recovery (CDR) circuit comprising: a data sampling unit which latches serial data input in response to data clock signals, and outputs a plurality of sampling data, the data clock signals maintaining a constant phase difference and having mutually different phases; an edge sampling unit which outputs an edge sampling signal generated by sampling edge information of the serial data in response to a selection edge clock signal, the selection edge clock signal being randomly selected from among a plurality of edge clock signals, the plurality of edge clock signals maintaining a constant phase difference, having mutually different phases, and having phases individually different from the data clock signals; a data selection unit which selects at least two consecutive sampling data from among the plurality of sampling data, the at least two selected sampling data corresponding to the edge sampling signal output from the edge sampling unit; a decoding unit which performs a logical operation of the sampling data selected by the data selection unit and the edge sampling signal, and outputs a transition information signal of the sampling data selected by the data selection unit and a phase control signal; and a random edge clock generating unit which generates the selection edge clock signal based on a random selection from among the plurality of edge clock signals.