Patent ID: 6297101
Filing Date: 2001-10-02
Classification: H01L,Y10S

Abstract:
A method for producing an MOS transistor structure, comprising the steps of:providing a substrate layer of a first conductivity type;forming a body region of a second conductivity type adjoining said substrate layer, said body region of a second conductivity defining a primary surface;forming source regions of said first conductivity type at said primary surface and extending into said body region and thereby defining at least one channel region between two of said source regions and said substrate layer;forming a gate trench in said channel region proceeding from said primary surface to said substrate layer, said gate trench having a sidewall;obliquely implanting dopant of said first conductivity type into said channel region to dope at least an upper portion of said sidewall of said gate trench, and using an implantation dosage so that substantially no redoping of said body region, other than at said upper portion of said sidewall, into said first conductivity type occurs, other than at said upper portion of said sidewall, and said body region retains said second conductivity type; andforming a gate oxide and a gate electrode in said gate trench.