Patent ID: 6790771
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method for forming bitlines for DRAM, comprising:providing a semiconductor substrate having a first dielectric layer formed thereon through which a contact hole is formed; filling the contact hole with conductive material to form a first conductive layer and etching back the first conductive layer to below the first dielectric layer; widening the opening of the contact hole by isotropic etching to form a first opening; filling the first opening with conductive layer to form a bitline contact landing; forming a second dielectric layer on the first dielectric layer to cover the bitline contact landing; forming a peripheral contact hole and defining a first bitline trench to expose the bitline contact landing simultaneously; defining a second bitline trench in the second dielectric layer to expose the peripheral contact hole; and filling the peripheral contact hole, the first bitline trench and the second bitline trench with a second conductive layer to form a contact to a peripheral, a first bitline and a second bitline.