Patent ID: 8451373
Filing Date: 2013-05-28
Classification: H04N

Abstract:
1. A frame rate converter, comprising: an input unit configured to write, into a memory unit, frames successively input from the outside; an interpolated frame generating unit configured to retrieve a plurality of original frames from the memory unit, generate an interpolated frame between the original frames, and write the interpolated frame into the memory unit; and an output unit configured to retrieve original frames and an interpolated frame from the memory unit and output to the outside the frames in the order in which the frames are to be displayed, wherein: the input unit, the interpolated frame generating unit, and the output unit operate in parallel to perform pipeline processing, operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit, and within the period between the termination of the input period of a target frame, in which the target frame is input to the input unit and written into the memory unit, and the initiation of the input period of the next frame, the interpolated frame generating unit completes the processing of retrieving at least the target frame, generating the interpolated frame with reference to at least the target frame, and writing the interpolated frame.