Patent ID: 6759180
Filing Date: 2004-07-06
Classification: B82Y,G03F,H01L

Abstract:
A method of fabricating sub-lithographic sized line and space patterns, comprising:depositing a first polysilicon layer on a surface of a base layer; depositing a photoresist layer on a surface of the first polysilicon layer; patterning and then etching the photoresist layer to define a line and space pattern therein; transferring the line and space pattern to the first polysilicon layer by etching the first polysilicon layer to define a plurality of polysilicon line features including an initial dimension and a plurality of space features including an initial width, the initial dimension and the initial width including a minimum feature size that is greater than or equal to a lithography limit of a lithographic system used for the patterning; removing the photoresist layer from the polysilicon line features; oxidizing the polysilicon line features in a plasma comprising an oxygen gas, and continuing the oxidizing until the polysilicon line features are reduced to a final dimension and an oxidized mantel of the polysilicon line features has expanded and reduced the space features to a final width, the final dimension and the final width including a sub-lithographic feature size that is less than the lithography limit; depositing a second polysilicon layer that completely covers the oxidized mantel of the polysilicon line features and completely fills in the space features; planarizing the second polysilicon layer to form a planar layer of alternating and sub-lithographic sized polysilicon and oxidized polysilicon line features; and etching the planar layer to selectively remove a selected one of the polysilicon line features or the oxidized polysilicon line features.