Patent ID: 6356150
Filing Date: 2002-03-12
Classification: H03G

Abstract:
A high efficiency multiple power level power amplifier comprising:at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal; and an inverter network in electrical communication with the PIN diode network and configured to generate the second input signal to selectively enable and disable the PIN diode network such that the PIN diode network is capable of controlling the interstage impedance between the at least one input and the at least one output amplifier stages to establish a desired AC load line for the high efficiency multiple power level power amplifier.