Patent ID: 6667645
Filing Date: 2003-12-23
Classification: G06F,H03K

Abstract:
A signal transfer clocking circuit comprising:a first stage including a static latch and a first non-clocking circuit in series therewith, said static latch having a data input and being opened in response to a first level of a pulse clock signal applied thereto to effect transfer of incoming data through said first stage in a first phase of operation of said signal transfer clocking circuit; and a second stage including a dynamic latch and at least a second circuit in series therewith, said dynamic latch consisting of a non-gate delay switching circuit and having a data input, coupled to an output of the first circuit, and being opened in response to a second level of a same or different pulse clock signal applied thereto as that applied to said static latch to enable a substantially race-free transfer of data generated by said first stage, through said second stage, to at least one succeeding circuit, in a second, successive phase of operation of said signal transfer clocking circuit, said succeeding circuit being opened and closed by a clock signal having phase and frequency characteristics linked to the pulse clock signal applied to said dynamic latch, wherein said signal transfer clocking circuit is provided in a processor, wherein said processor is provided with plural ones of said signal transfer clocking circuit, each said pulse clock signal having a phase and frequency based on a domain phase clock signal, generated by a clock distribution network of said processor, associated with that signal transfer clocking circuit, and wherein, in each said signal transfer clocking circuit of said processor, said pulse clock signal associated with said dynamic latch is provided either by a same local clock generator as that of said static latch or by a different local clock generator than that of said static latch, different local clock generators being associated with the same or respectively different domain phase clock signals.