Patent ID: 6365325
Filing Date: 2002-04-02
Classification: G03F

Abstract:
A method for fabricating a microelectronic layer comprising:providing a substrate; forming over the substrate a blanket target layer; forming upon the blanket target layer a patterned photoresist layer which defines a first aperture, the first aperture having a first aperture width which exposes a first portion of the blanket target layer; reflowing thermally the patterned photoresist layer at from about 100 to 150Â° C. for from about 50 to 180 seconds to form a reflowed patterned photoresist layer which defines a substantially straight sided second aperture, the straight sides being substantially vertical with a slope greater than about 85Â° the second aperture having a second aperture width less than the first aperture width, the second aperture thus exposing a second portion of the blanket target layer of areal dimension less than the first portion of the blanket target layer; and fabricating the target layer to form a fabricated target layer while employing the reflowed patterned photoresist layer as a mask layer.