Patent ID: 7568189
Filing Date: 2009-07-28
Classification: G06F

Abstract:
1. A method of executing an application of a target computer using a host computer, the host computer including instructions to utilize valid cached translated code to emulate functionality of the target computer when available, the method comprising: in response to a first instruction received from an emulation environment to translate target application code into code blocks executable by the host computer, partitioning the target application code into a plurality of target application code blocks of related instructions; chaining together related target application code blocks to form a plurality of target application code block groups, each target application code block group being identified at least in part by selecting a block group start point in the target application code and tracing a control flow of the target application code from the block group start point to each block end point corresponding to the block group start point, each target application block end point including a control flow instruction of the target application code, each target block group being analyzed to ensure that the target block code does not include a conflict or exceed a determined size limit based at least in part upon a potential destination address for at each branch or control flow instruction of the target block group; translating each target application code block group into a format capable of being executed by the host computer, and storing each translated block group to a translated code cache along with a first cache tag for the translated code block group, the first cache tag for each translated code block group representing a checksum or memory address derived from an effective memory address or source memory address of the block group boundaries for a respective code block group, wherein the checksum supports identification matching of an untranslated block group and a corresponding and previously-cached block group, and wherein the derived effective or source memory address supports determination of a potential violation upon a branch by an instruction within an untranslated block group outside the predetermined size limit, or upon address relocation of the untranslated code block with respect to the fixed location of a corresponding and previously cached block group; in response to a second instruction from an emulation environment, identifying at least one target application code block group to be executed by the host computer emulating operation of the target computer, determining a second cache tag for each identified target application code block group to be executed, each second cache tag representing a checksum or memory address derived from an effective memory address or source memory address of block group boundaries for a respective identified target block group; comparing the determined second cache tag to the first cache tag associated with each translated code block group in the translated code cache to determine whether the translated code cache includes a valid translated block group corresponding to each target application code block group, wherein the host computer is operable to select the valid translated block group from the translated code cache when available for execution in response to the second instruction; and in response to a determination that the translated code cache includes a valid translated block group corresponding to the target application code block group, executing the valid translated block group at the host computer, wherein a target translated code block group does not need to be retranslated if a valid version of the target translated code block group exists in the translated code cache on the host computer.