Patent ID: 7545828
Filing Date: 2009-06-09
Classification: H04L

Abstract:
1. A digital telecommunication apparatus comprising: a host network processor configured to be coupled to data terminal equipment; a multi-protocol communication interface, which is operative to execute diverse types of digital communication signaling interface functions with a plurality of communication ports, under the control of supervisory control signals supplied by said host network processor, said plurality of communication ports including a first port configured to interface ATM cell-based voice and data traffic with a digital communication network, a second port configured to interface TDM voice communication signals with a time division multiplexed (TDM) digitized voice communication link, and a third port configured to be coupled with a dual PHY ATM cell-based communication path over which ATM cell-based communications containing communication signals interfaced at said first and second ports are conducted between said multi-protocol communication interface and said host network processor; said multi-protocol communication interface includes a bidirectional digital cross-connect switch coupled to said second port, and providing TDM voice signaling connectivity between said second port and an internal TDM bus, said internal TDM bus being coupled with said dual PHY ATM cell-based communication path in such a manner as to interface TDM voice signals at said second port as ATM cell-based voice communications over said dual PHY ATM cell-based communication path with said host network processor; said bidirectional digital cross-connect switch is further coupled to said first port, and wherein said multi-protocol communication interface is configured to interface ATM cell-based voice communications received over said dual PHY ATM cell-based communication path from said host network processor through said bidirectional digital cross-connect switch with said first port for application to said digital communication network; and a cell encapsulation logic unit configured to perform header prepending operations.