Patent ID: 7225377
Filing Date: 2007-05-29
Classification: G01R,G06F

Abstract:
1. A method of obtaining selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in a semiconductor integrated circuit, the method comprising: a fault list preparing step that prepares a stored fault list of path delay faults in the semiconductor integrated circuit under test; a test pattern sequence generating step that generates a test pattern sequence including two or more test patterns to be applied to the semiconductor integrated circuit; a transition signal values calculating step that performs a simulation of transitions that occur in the semiconductor integrated circuit when the test pattern sequence is applied to the semiconductor integrated circuit, thereby obtaining a train of transition signal values that occur on signal lines within the semiconductor integrated circuit; a detectable fault list preparing step that prepares a detectable fault list of detectable path delay faults that are is capable of being detected by the transient power supply current testing, wherein the testing uses transition signal values obtained from the simulation of transitions when the test pattern sequence is applied to the semiconductor integrated circuit; a deletion step that deletes from the stored fault list those existing detectable faults that exist in the stored fault list; and a registering step that registers in a test pattern sequence list those test pattern sequences that are used to detect the existing detectable faults, thereby obtaining the selected test pattern sequences.