Patent ID: 6430647
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A data processing system comprising:a data processing device that reads process data from an external device at a first bit width per one cycle; a connection device that connects the data processing device with a storage device when the storage device is mounted in the connection device, wherein the storage device is detachably mounted and has a reduced bus size with which process data is read at a second bit width that is smaller than the first bit width; and an address specifying data control device that outputs via the connection device at least a portion of data specifying an address for a storage area in the storage device, based on prescribed instruction data from the data processing device; wherein the data processing device comprises: address specifying data output means for outputting data that specifies an address of a standard storage area, in which at least process data of the first bit width is stored within the storage device, the data of the first bit width being read per one cycle; valid process data extraction means for extracting valid process data of the second bit width based on process data read in one cycle at the first bit width corresponding to data specifying an address, when specifying an address in the standard storage area equivalent to an area of the reduced bus size; and partial storage area selection means for selecting a desired partial storage area in the standard storage area equivalent to an area of the reduced bus size in which data of the second bit width is stored, and outputs selection instruction data, and wherein the address specifying data control device generates at least one part of the data for specifying the address of a partial storage area based on the selection instruction and outputs to the storage device via the connection device.