Patent ID: 6083828
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method for forming a self-aligned contact (SAC), the method suitable for a gate structure that is formed on a semiconductor substrate and is covered by a cap layer on the top, a liner oxide layer on each sidewall of both the gate and the cap layer, and a spacer on the liner oxide layer, in which an interchangeable source/drain region is formed in the substrate at each side of the gate structure, the method comprising:forming a dielectric layer over the substrate;patterning the dielectric layer to form a SAC opening, which exposes the interchangeable source/drain region and may expose the cap layer, the liner layer, and the spacer, due to a misalignment property of the SAC opening, wherein since the liner layer is exposed, a portion of the liner layer is also removed to leave a clearance that exposes the gate structure;forming an insulating plug to fill the clearance so as to isolate the gate structure; andforming a SAC conductive plug to fill the SAC opening so as to form the SAC contact.