Patent ID: 6711661
Filing Date: 2004-03-23
Classification: H04L,Y10S

Abstract:
A device for translating a hierarchical address, the device is adapted to receive a destination address, to search an array of sorted binary string being associated with a group of addresses reachable through the device, and to provide a best matching address, the device comprising:a content addressable memory module; a fast memory module; a memory module; a search engine, coupled to the content addressable memory unit module, the fast memory module and the memory module, configured to receive a destination address, to access at least the fast memory unit and the memory unit and to find the best matching address; and a host processor, being coupled to the fast memory the content addressable memory module and the memory module, the host processor is adapted to receive a plurality of trinary prefixes, to generate the array of sorted binary strings and to store a first portion of the array of the sorted binary strings in the content addressable memory module; to store a second portion of the array of sorted binary strings in the fast memory module and to store a third portion of the array in the memory module.