Patent ID: 6453388
Filing Date: 2002-09-17
Classification: G06F

Abstract:
A computer system comprising:a bus; a memory device coupled to said bus; a central processing unit generating a first memory access request for first information, the first information associated with a first address of said memory device; and a bus interface unit, coupled between said central processing unit and said bus, including a transmitting sub-unit and a receiving sub-unit; said transmitting sub-unit receives said first memory access request to generate a request packet for said first information and second information, the second information being prefetch information associated with a speculative address and places said request packet onto said bus, the speculative address being produced by incrementing the first address using an increment address circuit; said receiving sub-unit comprising: an output buffer for temporarily storing at least said first information before outputting said first information to said central processing unit; at least one input buffer for storing said second information; a select element, coupled to said output buffer and said at least one input buffer, for outputting one of said first information and said second information into said output buffer; a control logic circuit, coupled to said select element, for controlling said select element to output one of said first and second information into said output buffer; a de-select clement, coupled to said select element and said at least one input buffer, for receiving in series said first information and said second information from said memory device and outputting said first information to said select element and said second information to said at least one input buffer, and an address length select circuit, coupled to said de-select element, for controlling said de-select element to output said first information into said select element and to output said second information into said at least one input buffer; said receiving sub-unit receives said first information and said second information and transfers at least said first information to said central processing unit.