Patent ID: 6747891
Filing Date: 2004-06-08
Classification: G11C

Abstract:
In combination with MRAM memory cells, a circuit for non-destructive, self-normalizing reading-out of the MRAM memory cells, the circuit deriving a normal resistance value Rnorm of a memory cell using a first voltage at which a resistance value of the memory cell being independent of a cell content, and an actual resistance value R(0) or R(1) of the memory cell using a second voltage at which the resistance value of the memory cell depends on the cell content, the actual resistance value is then normalized by use of the normal resistance value in the equationRnorm(0)=R(0)/Rnorm and, Rnorm(1)=R(1)/Rnorm and Rnorm(0) and Rnorm(1) are compared with a reference value, and, the memory cell content is detected as a 0 or 1 on a basis of a comparison result, the circuit comprising:a branch having at least one capacitor; a switch connected to said capacitor; a main output; and a balanced circuit connected to the memory cell, said branch and said output, said balanced circuit having a transistor and mirrors a current flowing during a determination of the normal resistance value Rnorm into said branch having said capacitor, so that after said switch has been opened, the normal resistance value Rnorm can be buffered by said capacitor and said transistor, said balance circuit permits a current Icell(0, 1) flowing during a determination of the actual resistance value to flow in said branch, so that a normalized output voltage Uout(0,1)=RnormÂ·Icell(0,1) is obtained at said main output.