Patent ID: 7692451
Filing Date: 2010-04-06
Classification: H03K

Abstract:
1. An output circuit comprising: an input node configured to receive an input signal; an output node configured to output an output signal; a main output section configured to output a high level signal to said output node in response to a first level of said input node, to output a low level signal to said output node in response to a second level of said input node until a level of said output node becomes said low level, and to deactivate the outputting of the low level signal to said output node when a level of said output node becomes said low level; and a low-level holding section configured to maintain said output node at said low level in response to said second level of said input node, wherein said main output section includes a terminating resistor connected between a high-potential power source line and said output node, and an output transistor connected between said output node and a low-potential power source line and controlled for ON or OFF depending on the level of said input signal, and wherein said main output section further includes a first cut-off transistor connected between said terminating resistor and said high-potential power source line, and a second cut-off transistor connected between said output transistor and said low-potential power source line, and wherein said first and second cut-off transistors are ON until a level of said output node becomes said low level, and OFF when a level of said output node becomes said low level.