Patent ID: 6492068
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method for forming a gate electrode of a semiconductor device, comprising:providing a semiconductor substrate having a stack of a resist mask layer, an organic coating layer, a conductive material layer, and a gate dielectric layer, the resist mask layer including a resist mask pattern partially masking the organic coating layer; etching the organic coating layer through the resist mask layer using an etching gas atmosphere including O2, Cl2, and HBr to form a pattern of the organic coating corresponding with the resist mask pattern, the etching including controllably reducing a width of the resist mask pattern such that a width of the pattern of the organic coating is determined by the reduced width of the resist mask pattern; and patterning the conductive material layer by etching through the pattern of the organic material, wherein: the mask pattern includes an isolated mask pattern having a first lateral mask dimension before the etching and a densely arranged mask pattern having a second lateral mask dimension before the etching; the pattern of the organic coating includes an isolated pattern corresponding with the isolated mask pattern and a densely arranged pattern corresponding with the densely arranged mask pattern; and the etching is performed such that the isolated pattern has a first lateral dimension, the densely arranged pattern has a second lateral dimension, and a first difference between the first lateral dimension of the pattern and the first lateral dimension of the mask pattern is substantially identical to a second difference between the second lateral dimension of the pattern and the second lateral dimension of the mask pattern.