Patent ID: 6178124
Filing Date: 2001-01-23
Classification: G11C

Abstract:
An integrated memory of an integrated circuit, comprising:a plurality of memory cells combined to form individually addressable standard units;a redundant unit for replacing one of said standard units on an address basis;a self-test unit adapted to perform a function test on said memory cells and to analyze which of said standard units is to be replaced with said redundant unit;a first memory unit for storing an address, determined by said self-test unit, of said standard unit to be replaced by said redundant unit;an address bus; anda comparison unit connected to said address bus and to outputs of said first memory unit, for comparing an address present on said address bus with the address stored in the first memory unit and for activating said redundant unit if the addresses match;said first memory unit having at least one output connected to an output of the integrated circuit for outputting the address stored in the first memory unit.