Patent ID: 8082418
Filing Date: 2011-12-20
Classification: G06F

Abstract:
1. An apparatus comprising: an accelerator device to be electrically coupled in a processor socket of a multi-processor socket computer system, wherein the accelerator device is to interface with a system memory in the computer system through a host bus, and wherein the accelerator device is capable of being dynamically re-configured during runtime of the computer system from accelerating a first processing task to accelerating a second processing task, and wherein the accelerator device is to receive a set of inter-processor interrupts (IPIs) from at least a processor in the computer system to initialize an acceleration configuration space within memory, the set of IPIs comprising: an initialization IPI to begin initialization of the accelerator device; a first plurality of base address IPIs to indicate a physical base address for the acceleration configuration space; and a second plurality of size IPIs to indicate a size of the acceleration configuration space.