Patent ID: 7955919
Filing Date: 2011-06-07
Classification: H01L

Abstract:
1. A method of forming an integrated circuit transistor comprising: providing a substrate with a doped well transistor region, the well having formed thereon a lightly doped diffusion (LDD) layer having an underlying and immediately adjacent punch through stop layer, the LDD layer defining a top plane for the substrate; selectively forming gate, source, and drain regions from the LDD layer such that that the gate region is formed in the LDD layer; depositing a first dielectric layer on the substrate including said gate, source, and drain regions; etching a gate electrode trench in the first dielectric layer such that said trench exposes the gate region, said etching comprises etching through the first dielectric layer and removing material from the underlying gate region of the LDD layer to form an opening that extends below the top plane of the substrate; replacing the material removed from the opening in the gate electrode trench with an epitaxially grown channel; depositing a conformal gate dielectric film to line the trench such that it includes forming the conformal gate dielectric film on the epitaxially grown channel; and depositing a gate electrode conductor in the trench to cover the gate dielectric film and fill the trench.