Patent ID: 7605433
Filing Date: 2009-10-20
Classification: H01L

Abstract:
1. A CMOS arrangement of transistors formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said CMOS arrangement comprising a first CMOS pair, said first CMOS pair comprising a first PMOS and a first NMOS, and a second CMOS pair, said second CMOS pair comprising a second PMOS and a second NMOS: said first PMOS comprising: said first NMOS comprising: said second PMOS comprising: said second NMOS comprising: wherein a sidewall oxide spacer is attached to each sidewall of said fourth gate, and wherein said second N-type drain region is separated from said channel region underlying said fourth gate by a distance greater than the lateral thickness of said sidewall oxide spacer.