Patent ID: 7663910
Filing Date: 2010-02-16
Classification: G11C

Abstract:
1. A phase change memory device comprising: a plurality of word lines arranged in a row direction; a plurality of bit lines arranged in a column direction; a reference bit line arranged in the column direction; a plurality of clamp bit lines arranged in the column direction; a cell array block comprising a plurality of phase change resistance cells each of which is formed at the intersection of one of the word lines and one of the bit lines, wherein the cell array block is configured to output a data current; a reference cell array block comprising a plurality of reference cells each of which is formed at the intersection of one of the word lines and the reference bit line, wherein the reference cell array block is configured to output a reference current; a clamp cell array block comprising a plurality of clamp cells each of which is formed at the intersection of a word line and the clamp bit line, wherein the clamp cell array block is configured to output a plurality of clamp currents; and a sense amplifier connected to the bit lines to receive the data current and performing amplification in response to a clamp voltage corresponding to the plurality of clamp currents and a reference voltage corresponding to the reference current.