Patent ID: 6566907
Filing Date: 2003-05-20
Classification: G06F,H03K

Abstract:
A sequencer circuit, comprising:a triggering input terminal providing a triggering input signal; a first sequencer output terminal providing a first sequencer output signal derived from the triggering input signal; a second sequencer output terminal providing a second sequencer output signal derived from the triggering input signal; a first dual-input latch having a first input terminal on which only leading edges are detected, a second input terminal on which only trailing edges are detected, a third input terminal coupled to the triggering input terminal, and an output terminal coupled to the first sequencer output terminal; a second dual-input latch having a first input terminal on which only leading edges are detected, a second input terminal on which only trailing edges are detected, a third input terminal coupled to the triggering input terminal, and an output terminal coupled to the second sequencer output terminal; a delay line having an input terminal coupled to the triggering input terminal and a plurality of output terminals providing signals delayed from the triggering input signal; and a plurality of interconnections coupling each of the first and second input terminals of the first and second dual-input latches to one of the output terminals of the delay line.