Patent ID: 8644097
Filing Date: 2014-02-04
Classification: G11C

Abstract:
1. A memory device comprising: a plurality of memory cell blocks, the memory cell blocks include a plurality of memory cells, a redundancy memory cell, and a selector switching a defective memory cell among the plurality of memory cells to the redundancy memory cell; and a control circuit configured to output control signals of the selectors of the plurality of memory cell blocks, based on defect information of whether or not each of the plurality of memory cell blocks has a defective memory cell and on specification information for specifying the defective memory cell in the memory cell block having the defective memory cell, wherein the control circuit has: a plurality of flip-flops provided in correspondence with respective bit lines of the control signals of the selectors of the plurality of memory cell blocks and configured to shift the specification information serially; a bypath circuit configured to bypath the flip-flop corresponding to the memory cell block which corresponds to the defect information if the defect information is information of not having the defective memory cell, and configured to shift the specification information serially in relation to the flip-flop corresponding to the memory cell block which corresponds to the defect information if the defect information is information of having the defective memory cell; a reset circuit configured to make the flip-flop corresponding to the memory cell block which corresponds to the defect information store the control signal indicating nonexistence of the defective memory cell, if the defect information is information of not having the defective memory cell; and a clock generating unit configured to output a clock signal to make the plurality of flip-flops shift the specification information to the plurality of flip-flops, wherein the plurality of flip-flops, after being synchronized with the clock signal and shifting the specification information, outputs the control signals of the selectors of the plurality of memory cell blocks, and wherein the selector of the memory cell block switches the defective memory cell to the redundancy memory cell in correspondence with the control signal.