Patent ID: 7468929
Filing Date: 2008-12-23
Classification: G11C

Abstract:
1. A memory array, comprising: a plurality of memory cells arranged in an array configuration having at least one row of memory cells; logic that identifies a polarity of a row of memory cells whose data values are to be read from the memory array to generate a polarity signal, wherein the polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values, wherein if the polarity of the row of memory cells indicates that a majority of the data values stored in the row of memory cells are logic 1 data values, then the selection logic selects the true data values of the memory cells in the row of memory cells for output by the memory array, wherein if the polarity of the row of memory cells indicates that a majority of the data values stored in the row of memory cells are logic 0 data values, then the selection logic selects the complement data values of the memory cells in the row of memory cells for output by the memory array; selection logic that selects whether to output true data values from the memory cells of the row of memory cells or complement data values from the memory cells of the row of memory cells based on the identified polarity; and output logic that outputs one of the true data values or the complement data values from the memory cells of the row of memory cells as the data read from the memory array based on the selection, wherein each of the plurality of memory cells comprises: