Patent ID: 7164603
Filing Date: 2007-01-16
Classification: G11C

Abstract:
1. An integrated circuit device comprising: a substrate; a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells having a threshold voltage and comprising a gate, and source and drain regions in the substrate, and including a top dielectric, a charge trapping structure, and a bottom dielectric between the gate and the channel, wherein the gate comprises a material having a work function higher than n-type polysilicon; and controller circuitry coupled to the plurality of memory cells, including logic to apply a first bias arrangement for establishing a low threshold state in memory cells in the plurality of memory cells, to apply a second bias arrangement for establishing a high threshold state in memory cells in the plurality of memory cells, and to apply a charge balancing bias arrangement which is different from the first and second bias arrangements, and wherein the top dielectric, the charge trapping structure, and the bottom dielectric have a combined effective oxide thickness, and the bottom dielectric has an effective oxide thickness greater than 3 nanometers, and the charge balancing bias arrangement includes a negative voltage from the gate of the memory cell to the substrate in the region of the channel having a magnitude of about 0.7 or higher volts per nanometer of the combined effective oxide thickness.