Patent ID: 8693265
Filing Date: 2014-04-08
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: first and second memory storage latches each including first and second ports; a first pair of bit lines coupled to the first ports of the first and second memory storage latches; a second pair of bit lines coupled to the second ports of the first and second memory storage latches, the first and second pairs of bit lines being twisted between the first and second memory storage latches; a first sense amplifier coupled to the first pair of bit lines for outputting data based on a voltage difference between the first pair of bit lines; a second sense amplifier coupled to the second pair of bit lines for outputting an intermediate data signal based on a voltage difference between the second pair of bit lines; and output logic circuitry coupled to an output of the second sense amplifier, the output logic circuitry configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.