Patent ID: 8471803
Filing Date: 2013-06-25
Classification: G09G,H03K

Abstract:
1. A level shifter comprising: a first circuit that is configured to block a supply of a source voltage to a first node when a signal input to an input terminal is maintained at a logic high level, and to supply the source voltage to the first node when the signal input to the input terminal transitions from a logic high level to a logic low level; a second circuit that is configured to supply the source voltage to the first node only when a voltage of an output terminal is maintained at a logic low level; a first inverter that uses the voltage supplied from the first node to generate a first output signal by reversing a logical level of the signal input to the input terminal and outputs the first output signal to a second node; and a second inverter that uses the source voltage to generate a second output signal by reversing the logical level of the first output signal that is output to the second node and outputs the second output signal to the output terminal, wherein the first circuit comprises: a first P-channel transistor comprising a source terminal connected to a source voltage terminal, a drain terminal connected to a third node, and a gate terminal connected to a terminal that is maintained at a logic low state; a second P-channel transistor comprising a source terminal connected to the source voltage terminal, a drain terminal connected to the first node, and a gate terminal connected to the third node; and a first capacitor comprising a first terminal connected to the input terminal, and a second terminal connected to the third node.