Patent ID: 7425874
Filing Date: 2008-09-16
Classification: H03L

Abstract:
1. A digital phase-locked loop, comprising: phase measurement circuitry, for generating a digital phase error signal corresponding to a phase delay between a reference clock and a feedback signal; a loop filter, having an input coupled to the phase measurement circuitry; a digitally controlled oscillator, comprising: digital control logic, having an input coupled to the loop filter, for generating a delay control word; a sampling circuit, for sampling the delay control word; the sampling circuit including a first latch, having an input coupled to the digital control logic, having an output, and having a clock input; and a second latch, having an input coupled to the output of the first latch, having an output, and having a clock input; an oscillator comprised of first and second delays that are controllable responsive to successive samples of the delay control word; and a feedback circuit, having an input coupled to the oscillator, for generating the feedback signal to the phase measurement circuitry, and having an output coupled to the clock inputs of the first and second latches of the sampling circuit; wherein the digital control logic generates values of the digital control word at a first frequency; and wherein the feedback circuit clocks the first and second latches at substantially twice the first frequency.