Patent ID: 9082644
Filing Date: 2015-07-14
Classification: G01R,H01L

Abstract:
1. A method of producing and testing a chip package, the method comprises: producing the chip package, wherein the chip package comprises a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip, wherein the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which a first group of external terminal pads of the chip package and a second group of external terminal pads of the chip package are arranged, wherein a pad size of an external terminal pad of the first group of external terminal pads is greater than a pad size of an external terminal pad of the second group of external terminal pads; and after producing the chip package, performing a functional test of the chip package on package-level; and performing a package-level burn-in test.