Patent ID: 6112292
Filing Date: 2000-08-29
Classification: G06F

Abstract:
In a processor including a register stack (RS) having first and second portions, said processor including a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between said second portion and a storage area, a computer-implemented process for switching from an interrupted to an interrupting context, the process comprising:preserving a state of said RSE of said interrupted context;issuing a COVER instruction, said cover instruction causing the processor to perform determining whether an interrupt handler needs to access said RS, and if so,validating a first register;copying content of a second register to the first register;causing the RSE to exchange information between a first portion and a second portion of the RS;preserving a first pointer that points to a location in said storage area, of said interrupted context, where a next register of said second portion is to be written;writing said first pointer with a value corresponding to said interrupting context; andpreserving a second pointer, said first and second pointers defining said storage area in the interrupting context.