Patent ID: 7840827
Filing Date: 2010-11-23
Classification: G09G

Abstract:
1. An apparatus, comprising: a display controller including a display buffer, a system interface unit for transferring information to the display buffer, and a power saving interface unit coupled to the display buffer and the system interface unit, wherein the power saving interface unit detects when frame information in the display buffer is above a threshold level and provides a first signal indicating that the display controller may enter a standby mode and detects when frame information in the display buffer is below a threshold level and provides a second signal indicating the display controller should exit the standby mode; a memory storage device coupled to an interconnect module; the interconnect module coupled to the system interface unit and memory storage device for transmitting information from the memory storage device to the system interface unit; and a control module coupled to the display controller, the interconnect module, and the memory storage device to provide power and a clock signal to the power saving interface unit, the interconnect module, and the memory storage device, wherein the control module is responsive to the first signal to enter the standby mode by limiting the power and clock signal to the display controller and responsive to the second signal to exit the standby mode by restoring the power and clock signal to the display controller.