Patent ID: 8923076
Filing Date: 2014-12-30
Classification: G11C,H01L

Abstract:
1. A memory circuit comprising: a transistor; a capacitor; a first arithmetic circuit; a second arithmetic circuit; a third arithmetic circuit; and a switch, wherein an output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit, wherein an output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit, wherein the input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor, wherein the other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit, wherein an output terminal of the third arithmetic circuit is electrically connected to the input terminal of the first arithmetic circuit via the switch, and wherein the transistor comprises an oxide semiconductor layer.