Patent ID: 6159780
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:providing a SOI substrate including a handling wafer, a buried insulating layer formed on the handling wafer and a silicon layer of a first conductivity type, formed on the buried insulating layer;selectively etching a selected portion of the silicon layer to a selected depth, to divide the silicon layer into two portions of a first and second portions, wherein the first portion is thicker than the second portion so that the silicon layer has a stepped portion between the first and second portions;forming a gate insulating layer on a selected portion of the silicon layer including the stepped portion;forming a gate electrode on the gate insulating layer;implanting impurities into selected portions of the silicon layer placed in both sides of the gate electrode, to form source/drain regions, wherein the source region is formed on the first portion of the silicon layer, the drain region is formed on the second portion of the silicon layer;forming an intermediate insulating layer on the overall surface of the SOI substrate including the gate electrode, and the source/drain regions;forming contact holes to expose selected portions of the source/drain regions; andforming a conduction line to be contact with the exposed source/drain regions,wherein the contact hole formed in the first portion of the silicon layer is extended to the bottom face of the source region, and the contact hole formed on the second portion of the silicon layer is extended to the surface of the drain region.