Patent ID: 7436055
Filing Date: 2008-10-14
Classification: H01L

Abstract:
1. A package structure with a plurality of chips stacked on each other comprising: a substrate comprising a dielectric layer, a metal layer, and a solder mask, wherein the metal layer comprises a conducting trace area and a shielding area formed on the dielectric layer, the solder mask formed on the conducting trace area of the metal layer; at least a first chip with a package body, electrically connected to the conducting trace area, wherein the first chip is positioned on the solder mask and the package body of the first chip is connected to a surface of the metal layer to position the first chip between the solder mask and the shielding area of the metal layer; and at least a second chip with a package body, electrically connected to the conducting trace area, wherein the second chip is positioned on the solder mask and the package body of the second chip is connected to another surface of the metal layer to position the second chip between the solder mask and the shielding area of the metal layer.