Patent ID: 6405024
Filing Date: 2002-06-11
Classification: H03L,H04B

Abstract:
A frequency synthesizer for a radio terminal, comprising:a clock outputting a clock signal; a first phase-locked loop for generating a high-frequency signal, including: a first frequency divider receiving the high-frequency signal; a second frequency divider receiving the clock signal; and a memory connected to said first frequency divider and storing divider ratios; a second phase-locked loop for generating an intermediate-frequency signal, including: a first frequency divider receiving the intermediate frequency signal; a second frequency divider receiving the clock signal; and memory connected to said first frequency divider and storing further divider ratios; and said memory of said first phase-locked loop coupled to said memory of said second phase-locked loop; said second phase-locked loop having a selection device with input terminals for selecting the further divider ratios from said memory of said second phase-locked loop, and said selection device being coupled to said memory of said first phase-locked loop; said memory of said first phase-locked loop having a register for storing the divider ratios having additional control bit positions, the control bits written in said control bit positions of said register being received by said input terminals of said selection device for selecting further divider ratios from said memory of said second phase-locked loop.