Patent ID: 8743515
Filing Date: 2014-06-03
Classification: H02H

Abstract:
1. An integrated chip, comprising: an electrostatic discharge (ESD) susceptible circuit electrically connected to a first circuit node having a first voltage and a second circuit node having a second voltage; and an ESD protection device, configured to act as an interface between the ESD susceptible circuit and external integrated chip pins, comprising a first electrical path that is configured to divert an ESD event received at the first circuit node to the second circuit node and including an RC trigger circuit configured to selectively assert one or more trigger signals; wherein the RC trigger circuit comprises: a resistive element connected between the first circuit node and an intermediary node; and a MOS capacitor having a gate physically connected to the intermediary node, a source and drain connected to an intermediate supply voltage node having an intermediate supply voltage between the first and second voltages, and a body connected to the second circuit node.