Patent ID: 6333954
Filing Date: 2001-12-25
Classification: H03M

Abstract:
A method of performing an add-compare-select butterfly operation for a Viterbi algorithm implementation, said method comprising:reading, during even clock cycles, a plurality of source state metrics from a first storage element corresponding to a first set of received symbols;calculating a target state metric for each of said source state metrics;temporarily storing said target state metrics into a second storage element;determining which one of said target state metric contains a lowest value;storing a predetermined logic bit corresponding to said lowest value target state metric in a third storage element;reading, during odd clock cycles, said target state metrics from said second storage element and using said read target state metrics as a plurality of intermediate source states metrics corresponding to a second set of received symbols;calculating an intermediate target state metric for each of said intermediate source states metrics;determining which one of said intermediate target state metric contains a lowest value;storing a predetermined logic bit corresponding to said lowest value intermediate target state metric in said third storage element.