Patent ID: 6169685
Filing Date: 2001-01-02
Classification: G11C

Abstract:
Memory addressable through its content, for storing data words whose bits can have a don't care logical value in addition to two complementary values and comprising of: at least one matrix of memory cells organized to form an array of M data words of N bits each, where each bit stored in a cell of a line of the array is allocated individually to one bit if this bit can only have two complementary logical values or to pairs of the same bit if a logical don't care value condition is admitted for it; means for presenting the matrix a data word to be searched in the memory by comparing jointly with a mask word the means for presenting connected to matrix cells through presentation lines common to all column cells of the matrix, first comparison means associated to each cell for executing a comparison between a comparand bit and the bit stored in the cell, comparison means outputs being associated to lines cells of the matrix combined with one another to generate the signals indicating positive or negative comparison between the comparand and the word stored in the line on a match line; encoding means connected to the match lines for emitting signals indicating whether or not a match was found between the comparand and the words stored and in the affirmative whether a match was found with one or more stored words; and control means for controlling access to the matrix for executing comparisons or reading/writing data by direct addressing, the entire array of words stored in the matrix forming a data structure accessible by direct addressing, with an address supplied by a user device or consisting of the signal emitted by the encoding means to indicate that a match was found between the comparand and one stored word; said matrix includes a supplementary line of cells for storing dummy data organized so that a comparison with a comparand will always give a match on a dummy match line, and a supplementary column of cells not allocated to memory data and including a cell corresponding to said supplementary line, and the encoding means including a supplementary section connected to the supplementary line of the memory matrix for outputting a dummy address signal; said control means are suitable to always address said supplementary line during direct addressing memory operation, and; said supplementary memory matrix line forming with the supplementary section of the encoding means and a first unit of the control means a first resetting loop used during memory operation for executing comparison between a comparand and stored data to control said first control unit so as to disable said means for presenting as soon as a comparand and its mask have been presented to the memory matrix and said supplementary line and column forming with a unit to generate a resetting signal belonging to said control means, a second resetting loop used during direct access memory use to control the control means so as to disable an address means and a data reading means as soon as an item is read.