Patent ID: 6184090
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A fabrication method for a vertical metal oxide semiconductor transistor, the method comprising the steps of:forming an isolation structure in a substrate to define an active region;conducting a first doping process to form a first doped layer in the active region;conducting a second doping process to form a second doped layer in the active region, wherein the second doped layer is formed on the first doped layer;conducting a third doping process to form a third doped layer in the active region, wherein the third doped layer is formed on the second doped layer, and a surface of the third doped layer is exposed on a surface of the substrate, and wherein the conductive type of a doped layer is different from the conductive type of a dopant for the first doped layer and the third doped layer;removing a portion of the isolation structure down to a surface level of the first doped layer, exposing a surface of the third doped layer and sidewalls of the second doped layer and third doped layer, but concealing the first doped layerforming a gate oxide layer on exposed sidewalls and surface of the second doped layer and the third doped layer, respectively; andforming a conductive layer at the sidewalls of the second doped layer and on the substrate to cover the isolation structure, wherein the second doped layer and the conductive layer are isolated by the gate oxide layer.