Patent ID: 6202130
Filing Date: 2001-03-13
Classification: G06F

Abstract:
In a data processing system having a first memory and a second memory at a lower hierarchical level than the first memory, a data processor for prefetching into the first memory a vector stored in the second memory, the vector comprising n units distributed in the second memory at a stride s relative to a base address ba with an ith unit of the vector stored in the second memory at an effective address ea, where ea=(ba+(s*i)), and i is an index having a value from 0 to (n-1), the data processor comprising:a first register for storing n;a second register for storing s;a third register for storing ea;an arithmetic unit having a first input coupled to the second register, a second input coupled to the third register, and an output terminal, for calculating the effective address ea of each unit i of the n units of the vector and for providing a fetch address to the output terminal thereof corresponding to the effective address ea when enabled;a load unit coupled to the first memory and to the second memory and having an input terminal for receiving the fetch address, for prefetching a data element located at the fetch address from the second memory into the first memory; anda state machine having an input coupled to the first register, for enabling the arithmetic unit in response to the data processor receiving a predetermined instruction, and for enabling the arithmetic unit repetitively until an nth unit of the vector has been prefetched.