Patent ID: 8578224
Filing Date: 2013-11-05
Classification: G01R,H03K

Abstract:
1. A master/slave latch, comprising: an input stage that is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal that is gated by an asynchronous clear signal such that the gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted and the gated clock signal is not active when the asynchronous clear signal is asserted; a master latch coupled to receive and to latch the passed data signal in a latched state, arranged to maintain the latched state at a node of the master latch in response to a feedback path internal to the master latch and to clear the latched state in response to the asynchronous clear signal being asserted, and is arranged to generate a master latch output signal at a pass gate in response to the latched state of the master latch; and a slave latch coupled to receive and to latch the master latch output signal in a latched state and wherein the pass gate is arranged to pass a cleared latched state to the slave latch in response to the asynchronous clear signal being asserted.