Patent ID: 6963964
Filing Date: 2005-11-08
Classification: G06F

Abstract:
1. A computer system, comprising: a memory addressable using real addresses, each said real address having M+L including an M-bit high-order address portion and an L-bit low-order address portion; address generation logic which generates virtual addresses for computer processing operations, each said virtual address having K+L bits, including a K-bit high-order address portion and an L-bit low-order address portion; an N-way translation lookaside buffer for translating virtual addresses to real addresses, said N-way translation lookaside buffer translating a K-bit high-order portion of a source virtual address to an M-bit high order portion of a target real address, the L-bit low-order portions of the source virtual address and the target real address being identical, said N-way translation lookaside buffer containing a plurality of lines, each line selected using said virtual address and containing N M-bit portions of respective target real addresses, said -way translation lookaside buffer further containing selection logic for selecting one of said N M-bit portions of respective target real addresses from a selected line; a pipeline mechanism; and a pipeline address conflict mechanism which detects an address conflict between a first operation in said pipeline and a second operation in said pipeline, said pipeline address conflict mechanism comparing at least part of each M-bit portion of a respective target real address of the N M-bit portions of respective target real addresses in the line of the translation lookaside buffer selected by a virtual address for said first operation in said pipeline mechanism with a corresponding part of the M-bit portion of a real address for said second operation in said pipeline mechanism, and taking an address conflict resolution action according to the results of said comparison.