Patent ID: 7398450
Filing Date: 2008-07-08
Classification: H04L

Abstract:
1. A parallel precoder circuit that executes an exclusive-OR operation on an n-row parallel input, and outputs an n-row parallel output, where n is an integer equal to or larger than two, the parallel precoder circuit comprising: an nth-row delay circuit that delays an output of an exclusive-OR circuit having a largest column number from among exclusive-OR circuits disposed in nth row; a zeroth-column exclusive-OR circuit that executes the exclusive-OR operation of an output of the nth-row delay circuit and a first-row parallel input; a (2k)th-row first-column exclusive-OR circuit that executes the exclusive-OR operation of a (2k)th-row parallel input and an output of the zeroth-column exclusive-OR circuit when k is one or a (2k−1)th-row parallel signal when k is larger than one, where k is an integer equal to or larger than one and equal to or smaller than n/2; a (2k)th-row mth-column exclusive-OR circuit that executes the exclusive-OR operation of an output of a (2k)th-row (m−1)th-column exclusive-OR circuit, when 2k−2^(m−1) is equal to or larger than one, and an output of a (2k−2^(m−1))th-row (m−1)th-column exclusive-OR circuit when an exclusive-OR circuit is disposed in (2k−2^(m−1))th-row (m−1)th-column or an output of an exclusive-OR circuit having a largest column number from among exclusive-OR circuits disposed in (2k−2^(m−1))th row when no exclusive-OR circuit is disposed in (2k−2^(m−1))th-row (m−1)th-column, where m is an integer equal to or larger than two and equal to or smaller than h−1, and h is a smallest integer equal to or larger than log a (2k−1)th-row hth-column exclusive-OR circuit that executes the exclusive-OR operation of a (2k−1)th-row parallel signal and an output of an exclusive-OR circuit having a largest column number from among exclusive-OR circuits disposed in (2k−2)th row, wherein outputs of exclusive-OR circuits each of which having a largest column number from among exclusive-OR circuits disposed in first to (n−1)th rows become first-row to (n−1)th-row parallel outputs, respectively, and the output of the nth-row delay circuit becomes an nth-row parallel output.