Patent ID: 8223559
Filing Date: 2012-07-17
Classification: G11C

Abstract:
1. A method of programming a memory, the memory including a plurality of memory regions each including a first bit line, a second bit line, a data buffer and a protecting unit, wherein the first bit line is coupled to a first column of multi-level cells, the second bit line is coupled to a second column of multi-level cells, the data buffer is coupled to the first bit line and the second bit line and is for storing data to be programmed into the multi-level cells, and the protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error, the programming method comprising the steps of: (a) respectively inputting corresponding data to the data buffers; (b) programming the data corresponding to an nth phase into the targeted multi-level cells, wherein n is a positive integer; (c) judging whether the targeted multi-level cells pass a programming verification process or not according to an nth programming verification voltage; (d) modifying data corresponding to an (n+1)th phase to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass the programming verification process; and (e) repeating steps (b) to (d) until n is equal to a maximum, wherein the step (d) is not performed when n is equal to the maximum, wherein programming operations of each of the phases are the same.