Patent ID: 6239609
Filing Date: 2001-05-29
Classification: G01R

Abstract:
A method for reducing transistor leakage currents in an integrated circuit to improve the accuracy of quiescent current testing, comprising:applying a first power supply voltage to the integrated circuit;placing the integrated circuit into a static DC state;measuring a first quiescent current consumed by the integrated circuit at the first power supply voltage;applying a second power supply voltage to the integrated circuit;measuring a second quiescent current consumed by the integrated circuit at the second power supply voltage;applying a third power supply voltage to the integrated circuit, the first, second and third power supply voltages having differing values;measuring a third quiescent current consumed by the integrated circuit at the third power supply voltage; andexamining the relative values of the first, second and third quiescent current values to determine the manner in which the quiescent current is changing with changing power supply voltage.