Patent ID: 8866280
Filing Date: 2014-10-21
Classification: H01L

Abstract:
1. A chip package, comprising: a carrier, including a carrying surface, a back surface opposite to the carrying surface, and a first side surface surrounding and connected between the carrying surface and the back surface, the carrier further including a plurality of common contacts adjacent to the periphery of the carrying surface; a chip, disposed adjacent to the carrying surface and electrically connected to the carrier; a plurality of conductive elements, disposed adjacent to and connected to the common contacts respectively; an encapsulation, covering the carrying surface and encapsulating the chip and the conductive elements; and a conductive film, provided with a second side surface and directly attached on a top surface of the encapsulation to cover and connect with the conductive elements, wherein the first side surface of the carrier is coplanar with the second side surface of the conductive film, and wherein the carrier further comprises at least one extending contact adjacent to the carrying surface, the extending contact is electrically connected with the common contacts via interconnections in the carrier, and the chip is electrically connected with the extending contact to attain a common voltage from the common contacts.