Patent ID: 6664163
Filing Date: 2003-12-16
Classification: H01L

Abstract:
A method of manufacturing a MISFET comprising the steps of:a) forming a trench in a substrate of first conductive type; b) forming a first region of the first conductivity type and a second region of the second conductivity type into the substrate through portions of the trench; c) depositing an oxide layer on portions of sidewalls of the trench, wherein said oxide layer extends from the top of the trench; d) then forming an extended trench while retaining said oxide layer on the portions of the sidewalls of said trench; e) forming a gate oxide layer on the sidewalls of said extended trench; f) forming a gate layer on the gate oxide layer; selectively etching the gate layer, and the gate oxide layer so that the surface of the substrate is exposed in regions adjacent to the trench and residual films of the gate layer and the gate oxide layer are left on the sidewalls of the trench;g) forming a base of the first conductivity type and a source of the second conductivity type at the bottom of the trench; h) forming a second oxide layer inside the trench and on the surface of the substrate over a drain by a method where oxide growth rate is slower inside the trench than at the surface of the substrate, wherein the thickness of the second oxide layer within the trench is less than the thickness of the second oxide layer on the surface of the substrate; i) etching the oxide layer at the bottom of the trench to form a contact hole that extends to the substrate while maintaining a thickness of the second oxide layer on the sidewalls of the trench and surface of the substrate using a directional etching method; and j) forming an electrical interconnection material in the trench that extends through the contact hole.