Patent ID: 8637353
Filing Date: 2014-01-28
Classification: H01L,Y10T

Abstract:
1. A method of repairing a wiring path in a stacked chip structure, the wiring path including a through silicon via (TSV) and a landing pad coupled with the TSV, the method comprising: determining a first numerical value for an electrical resistance of the wiring path; comparing the first numerical value for the electrical resistance of the wiring path to a target electrical resistance value ranging from 10 ohms to 1000 ohms; if the first numerical value for the electrical resistance of the wiring path is between 10 ohms and 1000 ohms, capacitively charging the stacked chip structure to a voltage in a range of 100 volts to 500 volts; and contacting the TSV with a grounded probe to discharge the voltage from the stacked chip structure through the TSV and the landing pad to the grounded probe so that a portion of the wiring path having a defect is heated to a temperature exceeding a melting point of a metal comprising the wiring path.