Patent ID: 6815801
Filing Date: 2004-11-09
Classification: H01L

Abstract:
An integrated circuit, comprising:a first epitaxial layer containing a buried layer; a second epitaxial layer located over said first epitaxial layer, wherein said second epitaxial layer includes at least two dopant profiles wherein said at least one of said two dopant profiles in contained within said buried layer; a vertical PNP bipolar transistor located over or within said second epitaxial layer, wherein said vertical PNP bipolar transistor includes a vertical PNP bipolar transistor collector, a vertical PNP bipolar transistor base and a vertical PNP bipolar transistor emitter; an NPN bipolar transistor located over or within said second epitaxial layer and proximate said vertical PNP bipolar transistor, wherein said NPN bipolar transistor includes an NPN bipolar transistor collector, an NPN bipolar transistor base and an NPN bipolar transistor emitter; and interconnects contacting said vertical PNP bipolar transistor and said NPN bipolar transistor to form an operative integrated circuit.