Patent ID: 7825715
Filing Date: 2010-11-02
Classification: H03B,H03J

Abstract:
1. A device, comprising: a first switchable capacitor having a first capacitance; a second switchable capacitor having a second capacitance, the second switchable capacitor being connected in a parallel circuit with the first switchable capacitor, the parallel circuit having a tunable capacitance; and a switch controller that is coupled to the first and second switchable capacitors, the switch controller being configured to switch the first and second switchable capacitors to adjust the tunable capacitance based on first and second (M+1)-ary pulse width modulated signals, (M being a positive integer), respectively, with each of the first and second (M+1)-ary pulse width modulated signals supplied by the switch controller; and an offset switchable capacitor having an offset capacitance, the offset switchable capacitor being coupled to the switch controller and in parallel with the first switchable capacitor, wherein the switch controller generates an offset pulse width modulation signal to turn on the offset switchable capacitor for a full modulation period.