Patent ID: 6180454
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method of forming a flash memory device, comprising:forming a gate oxide layer on a substrate;forming a first poly layer over the gate oxide layer;forming an insulating layer over the first poly layer, the insulating layer comprising a first oxide layer over the first poly layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer;forming a second poly layer over the insulating layer;forming a tungsten silicide layer over the second poly layer;etching a portion of the tungsten silicide layer and the second poly layer, wherein in the etched portion at least about 20% of the second poly is not etched, thereby partially defining at least one stacked gate structure;etching at least a portion of the insulating layer and the unetched portion of the second poly layer thereby defining at least one select gate transistor structure;forming an interlayer dielectric layer over the select gate transistor structure and substrate;etching a contact hole through the interlayer dielectric layer to the first poly layer; andfilling the contact hole with a conductive material to thereby form a flash memory device.