Patent ID: 6252441
Filing Date: 2001-06-26
Classification: G11C

Abstract:
A synchronous data sampling circuit for sampling data items sequentially input through an input port and outputting the sampled data items to an output port, the synchronous data sampling circuit comprising:a first pulse signal generator for receiving a clock signal and generating a first pulse signal during a logic ""low"" interval of the clock signal;a second pulse signal generator for receiving the clock signal and generating a second pulse signal during a logic ""high"" interval of the clock signal;first sampling unit for sampling first data input through the input port and outputting the sampled first data to the output port in response to the falling edge of the clock signal;second sampling unit for sampling second data input through the input port and outputting the sampled second data to the output port in response to an edge of the first pulse signal;third sampling unit for sampling third data input through the input port and outputting the sampled third data to the output port in response to the rising edge of the clock signal; andfourth sampling unit for sampling fourth data input through the input port and outputting the sampled fourth data to the output port, in response to the edge of the second pulse signal.