Patent ID: 7696552
Filing Date: 2010-04-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a tunnel oxide layer formed in a cell area of a semiconductor substrate, the cell area including at least a main cell region and a peripheral cell region; a floating gate on the tunnel oxide layer, the floating gate having a first conductive layer including polysilicon doped with N-type impurities; a dielectric layer on the floating gate, the dielectric layer including a high-k material; and a control gate on the dielectric layer, the control gate including a second conductive layer including polysilicon doped with P-type impurities, and a third conductive layer including a metal; wherein the tunnel oxide layer, the floating gate and the third conductive layer form a device structure in the peripheral cell region outside the main cell region, and wherein the dielectric layer and the second conductive layer of the device structure have widths substantially smaller than a width of the floating gate of the device structure.