Patent ID: 6621294
Filing Date: 2003-09-16
Classification: H03K

Abstract:
A pad system for an integrated circuit or device, said pad system comprising:logic circuitry having at least one pad input terminal for connecting to at least one pad; and at least two output terminals for connecting to at least one circuit system of said integrated circuit or device; wherein said logic circuitry comprises: a first signal path circuitry for outputting a logic high signal when a logic high signal or no signal is applied to the pad input terminal, a second signal path circuitry for outputting a logic low signal when a logic low signal or no signal is applied to the pad input terminal, and an output signal path circuitry for receiving the output signals from the first and second signal path circuitry and outputting at least one of a logic high and a logic low signal; wherein said logic circuitry is configurable to selectively connect said pad between at least two points of said circuit system, wherein said first signal path circuitry comprises a bleed-high buffer and first inverter circuitry connected to an output of the bleed-high buffer inverter, wherein said second signal path circuitry comprises a bleed-low buffer and second inverter circuitry connected to an output of the bleed-low buffer inverter, wherein the output signal path circuitry comprises: a first, second and third logic AND gate, each having two inputs and an output, one input of the first logic AND gate connected to an output of the bleed-high buffer and the other input of the first logic AND gate connected to an output of the bleed-low buffer, one input of the second logic AND gate connected to an output of the bleed-high buffer and the other input of the second logic AND gate connected to an output of the second inverter circuitry, one input of the third logic AND gate connected to an output of the first inverter circuitry and the other input of the third logic AND gate connected to the output of the second inverter circuitry, and each output of the first, second and third logic AND gates connected to at least one output terminal of the at least two output terminals.