Patent ID: 6297525
Filing Date: 2001-10-02
Classification: H01L,Y10S

Abstract:
A DRAM cell comprising:a capacitor comprising:a storage node comprising a top and in lateral cross-section comprising a pair of opposing lateral surfaces;an insulative layer beneath the storage node;laterally opposing cavities between the storage node and the insulative layer, the cavities having portions extending below an upper surface of the insulative layer;the storage node in lateral cross-section comprising an outer surface extending over the top of the storage node, along the pair of opposing lateral surfaces of the storage node, and within the laterally opposing cavities beneath the storage node;a dielectric layer against the storage node outer surface;a cell plate layer against the dielectric layer;a bitline disposed elevationally coextensive with the dielectric layer; anda transistor gate electrically connecting the bitline to the capacitor.