Patent ID: 6306749
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method for fabricating a bond pad structure for use in an integrated circuit comprising the steps of:(a) forming a bottom dielectric layer on a wafer;(b) forming an underlying layer on top of said bottom dielectric layer;(c) forming a middle dielectric layer on top of said underlying layer, wherein said middle dielectric layer contains at least one first through-hole away from an area intended to form a metal bond pad layer;(d) filling said at least one first through-hole with a hole-fill material, and, either simultaneously or subsequently with respect thereof, forming said metal bond pad layer and an island element in said middle dielectric layer, said island element being spaced apart from said metal bond pad layer and in contact with said underlying layer through said filled first through-hole;(e) forming a top dielectric layer on top of said metal bond layer, wherein said top dielectric layer contains at least one second through-hole which is connected to said island element;(f) filling said at least one second through-hole, and, either simultaneously or subsequently with respect thereof, forming at least one frame element on top of said top dielectric vertically above said island element, wherein said island element and said frame element are substantially smaller than said metal bond pad layer, said frame element is formed to contain a portion whose vertical projection overlaps a portion of said metal bond pad layer, and said frame element is connected to said island element through said filled second through-hole.