Patent ID: 7674683
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A method comprising: providing a substrate having a doped region formed in a bulk region of the substrate; disposing a dielectric material over the doped region of the substrate; forming a first hole and a second hole in the dielectric material, the first hole and the second hole exposing the doped region; depositing a first polysilicon plug and a second polysilicon plug over the doped region, the first polysilicon plug being disposed in the first hole and the second polysilicon plug being disposed in the second hole, wherein the second polysilicon plug is doped opposite the first polysilicon plug such that a PN junction is formed between the first or second polysilicon plug and the doped region of the substrate, the PN junction having a cross-sectional area generally defined by the first or second hole adjacent the PN junction, wherein the interface of the PN junction is formed between the polysilicon plug in the first or second hole and the doped region formed in the bulk region of the substrate, and wherein the interface of the PN junction is substantially coplanar with an upper surface of the substrate; and depositing a first conductive material over the first polysilicon plug and a second conductive material over the second polysilicon plug such that the first and second conductive materials are in electrical communication with the first and second polysilicon plugs, respectively.