Patent ID: 9179137
Filing Date: 2015-11-03
Classification: G09G,H04N

Abstract:
1. A gate driver comprising: a shift register block including a plurality of cascade-connected shift registers, each of the plurality of shift registers configured to sequentially output a scan pulse, whose phase is shifted by one horizontal period, in response to a start voltage, a first clock, a second clock, and a third clock; a selection block including a plurality of selection units, the selection units respectively connected to the plurality of shift registers, wherein the plurality of selection units are configured to receive the scan pulse and the third clock as input, and each selection unit from the plurality of selection units is configured to: a buffer block including a plurality of buffers, the buffers respectively connected to the plurality of selection units, wherein the buffer block is configured to generate emission pulses for a sequential light emission in the 2D mode and a simultaneous light emission in the 3D mode by: