Patent ID: 6725443
Filing Date: 2004-04-20
Classification: G06F,H01L

Abstract:
In an integrated circuit (IC) having an input/output (I/O) surface with a plurality of cells, in which each cell is rectangular with a first side, a second side parallel to the first side, a third side adjacent the first and second sides, and a fourth side parallel to the third side, a method for forming a cell interconnection template, the method comprising:forming a first bus line pattern in the plurality of cells by forming a plurality of parallel bus lines extending from the first side to the second side of each cell in the plurality of cells; forming a second bus line pattern underlying the first bus line pattern in the plurality of cells by forming a plurality of parallel bus lines extending from the third side to the fourth side of each cell in the plurality of cells; forming a routing channel pattern underlying the second bus line pattern in the plurality of cells, the routing channel including a plurality of signal trace lines, the routing channel adjoining the first, second, third, and fourth sides of each cell in the plurality of cells; abutting the plurality of cells; and in response to abutting the plurality of cells, interconnecting the first and second bus line patterns and interconnecting the routing channel pattern across the plurality of cells.