Patent ID: 8178961
Filing Date: 2012-05-15
Classification: G01L,H01L

Abstract:
1. A semiconductor package structure, comprising: a leadframe, having a die pad and a plurality of first and second leads arranged around the die pad; a first chip, disposed on an upper surface of the die pad, the first chip being electrically connected to the first and second leads; a first encapsulant, encapsulating the first chip, the upper surface of the die pad and at least a portion of each of the first and second leads, the first encapsulant exposing a lower surface of the die pad, the first encapsulant having a cavity exposing a first bonding area of each of the second leads, and the first encapsulant further encapsulating an end portion of each of the second leads extending toward the die pad; a second chip, disposed in the cavity of the first encapsulant and electrically connected to the first bonding areas of the second leads; and a cover, disposed over the cavity of the first encapsulant.