Patent ID: 8446774
Filing Date: 2013-05-21
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: N (N is a natural number of at least two) memory cell transistors formed on a semiconductor substrate and each having a stacked gate including a charge accumulation layer and a control gate, the memory cell transistors each being configured to hold data of at least two levels; a memory cell group in which the N memory cell transistors are connected together in series and in which the data is erased from the memory cell transistors at a time, a threshold voltage for an erased state of the memory cell transistors in the memory cell group being set by a soft programming operation performed after a data erasure operation; N word lines each connected to a gate of a corresponding one of the memory cell transistors in the memory cell group; a bit line electrically connected to a drain of the memory cell transistor positioned at one end of the memory cell group; a source line electrically connected to a source of the memory cell transistor positioned at the other end of the memory cell group; and a row decoder which, during the soft programming operation, simultaneously selects M (M is a natural number of at least two, M<N) word lines to perform first programming on every M memory cell transistors.