Patent ID: 8928150
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method of manufacturing a multi-chip package, the method comprising: arranging a second semiconductor chip having a second bonding pad over a first semiconductor chip having a first bonding pad; forming an insulating layer structure to cover side surfaces and upper surfaces of the first semiconductor chip and the second semiconductor chip; and forming a plug structure in the insulating layer structure by a plating process, the plug structure being spaced apart from the side surfaces of the first semiconductor chip and the second semiconductor chip to electrically connect the first bonding pad with the second bonding pad; wherein the forming the insulating layer structure and forming the plug structure further comprise: forming a first seed layer on a supporting substrate; attaching the first semiconductor chip to the first seed layer; forming a first insulating layer pattern on the first seed layer to cover the first semiconductor chip; forming a first opening in the first insulating layer pattern; exposing the first bonding pad; forming a first via hole in the first insulating layer pattern; exposing the first seed layer; performing a first planting process on the first seed layer; forming a first plug on the first via hole; forming a second seed layer from the first plug to the first bonding pad; performing a second planting process on the second seed layer to form a first redistribution layer connected between the first plug and the first bonding pad; forming a second insulating layer pattern on the first insulating pattern; attaching the second semiconductor chip to the second insulating layer pattern; forming a third insulating layer pattern on the second insulatin layer pattern to cover the second semiconductor chip; forming a second via hole in the third insulatin layer pattern; exposing the first redistribution layer; forming a second opening in the third insulating pattern; exposing the second bonding pad; performing a third plating process on the first redistribution layer to form a second plug in the second via hole; forming a third seed layer from the second plug to the second bonding pad; performing a fourth plating process on the third seed layer to form a second redistribution layer connected between the second plug and the second bonding pad; and forming a fourth insulating layer pattern on the third insulating layer pattern to expose the second redistribution layer; the method further comprising: arranging a third semiconductor chip having a third bonding pad over the second semiconductor chip having the second bonding pad; wherein forming an insulating layer structure further comprises forming an insulating layer structure to cover side surfaces and an upper surface of the third semiconductor chip; and wherein electrically connecting further comprises electrically connecting the second bonding pad with the third bonding pad; wherein forming the insulating layer structure and forming the plug structure further comprise: attaching the third semiconductor chip the fourth insulating layer pattern to cover the third semiconductor chip; forming a third via hole in the fifth insulating layer pattern; exposing the second redistribution layer; forming a third opening in the fifth insulating layer pattern; exposing the third bonding pad; performing a fifth plating process on the second redistribution ayer; forming a third plug in the third via hole; forming a fourth seed layer from the third plug to the third bonding pad; performing a sixth plating process on the fourth seed layer; forming a third redistribution layer connected between the third plug and the third bonding pad; and forming a sixth insulating layer pattern on the fifth insulating layer pattern.