Patent ID: 6636955
Filing Date: 2003-10-21
Classification: G06F

Abstract:
A memory controller, comprising:a plurality of multi-entry read buffers each adapted to be coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command; a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded; a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; and each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers; wherein all of said load pointer logic circuits couple to a data bus which couples to at least some of the memory modules and during initialization when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus causes its load pointer to be released and begin incrementing; wherein each load pointer logic circuit increments its load pointer using a clock to master clock that is provided and routed by the memory controller to the memory modules and back to the memory controller.