Patent ID: 7470978
Filing Date: 2008-12-30
Classification: H01L

Abstract:
1. A method of packaging an integrated circuit die, comprising: receiving a lead-frame having a two-dimensional array of device areas arranged in rows and columns, each device area configured for use in an inline semiconductor die package and having a first side, a second side, leads, and a die attach pad, wherein all of the leads of each particular device area extend from the first side of the particular device area, and wherein the die attach pad of each particular device area extends from the second side of the particular device area; electrically connecting ones of the semiconductor power dies each to an associated plurality of leads; applying encapsulant material to each of the columns so as to expose at least a portion of the leads associated with each column; and sawing the device areas apart from each other so as to generate a plurality of singulated inline packages.