Patent ID: 8518759
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A method for fabricating a field-effect transistor the method comprising the following steps without restriction by the order specified: forming a substrate region, wherein the substrate region is surrounded by two terminal regions, two electrically insulating layers, two electrically insulating regions, and an electrically conductive connection region; forming the two terminal regions, one terminal region being a source region and the other terminal region being a drain region, the source region being arranged at a first side of the substrate region and the drain region being arranged at a second side of the substrate region, the first and the second sides being opposite sides of the substrate region; forming the two electrically insulating layers and two control regions arranged at a third and fourth side of the substrate region, the third and fourth sides being mutually opposite sides of the substrate region and the two electrically insulating layers being adjoined by control regions, the control regions being located along the third and fourth sides with an insulating layer of the two electrically insulating layers between each of the control regions and the substrate region, the first and second sides being narrower than the third and fourth sides; forming the two electrically insulating regions, the two electrically insulating regions being arranged at mutually opposite sides of the substrate region, a first insulating region of the two electrically insulating regions being arranged at a fifth side of the substrate region and a second insulating region of the two electrically insulating regions being arranged at a sixth side of the substrate region; forming the electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region, the electrically conductive connecting region comprising a metal-semiconductor compound, part of the substrate region being covered by the electrically conductive connecting region and the electrically conductive connecting region also covering a covered area of the source region such that the electrically conductive connecting region extends across the first side of the substrate region to the source region, the part of the substrate region being covered by the electrically conductive connecting region being located between the two electrically insulating layers and between the control regions; leveling a surface by chemical mechanical polishing after forming the control regions; etching-back the control regions after polishing; and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.