Patent ID: 7403424
Filing Date: 2008-07-22
Classification: G11C

Abstract:
1. A method of erasing non-volatile memory, comprising: enabling erasing of a set of non-volatile storage elements, said enabling includes enabling erasing of a first and second subset of said set of non-volatile storage elements; applying one or more erase voltage pulses to said set while said first and second subset of non-volatile storage elements are enabled for erasing until said first subset is verified as erased; verifying, in between applying each of said one or more erase voltage pulses, whether said first subset of non-volatile storage elements is erased, said verifying includes excluding said second subset of non-volatile storage elements from verification; after said first subset is verified as erased, inhibiting said first subset from further erasing while enabling erasing of said second subset; and applying one or more additional erase voltage pulses to said set while said first subset is inhibited and said second subset in enabled until said second subset is verified as erased.