Patent ID: 9214464
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A semiconductor device including a first n-type MISFET formed in a first region of a semiconductor substrate, a first p-type MISFET formed in a second region of the semiconductor substrate, a second n-type MISFET formed in a third region of the semiconductor substrate and having a thicker gate insulating film than the first n-type MISFET, and a second p-type MISFET formed in a fourth region of the semiconductor substrate and having a thicker gate insulating film than the first p-type MISFET, comprising: a first gate insulating film formed over the first region; a second gate insulating film formed over the second region; a first gate electrode formed over the first gate insulating film; a second gate electrode formed over the second gate insulating film; a first n-type impurity region formed in the first region; a second n-type impurity region formed in the first region and having a higher impurity concentration than the first n-type impurity region; a first p-type impurity region formed in the second region; and a second p-type impurity region formed in the second region and having a higher impurity concentration than the first p-type impurity region, wherein first insulating films are formed over a side surface of the first gate electrode and over a side surface of the second gate electrode; wherein second insulating films are formed over the side surface of the first gate electrode and over the side surface of the second gate electrode through the first insulating films; wherein third insulating films are formed over the side surface of the first gate electrode and over the side surface of the second gate electrode through the first and second insulating films; wherein the first n-type impurity region is formed by introducing first impurities self aligned with the first insulating film formed in the first region, wherein the first p-type impurity region is formed by introducing second impurities self aligned with the second insulating film formed in the second region, wherein the second n-type impurity region is formed by introducing third impurities self aligned with the third insulating film formed in the first region, and wherein the second p-type impurity region is formed by introducing fourth impurities self aligned with the third insulating film formed in the second region.