Patent ID: 9136187
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, comprising: forming a first transistor and a second transistor on a substrate, wherein forming the first transistor and the second transistor comprises: forming a device isolation layer on or in the substrate to define a first active region corresponding to a first column and a second active region corresponding to a second column; performing a channel ion implantation process on the first and second active regions; forming a first gate pattern and a second gate pattern on the first active region and the second active region, respectively; performing a low-concentration dopant ion implantation process to form a first low-concentration dopant region in the substrate at first and second sides of the first gate pattern and a second low-concentration dopant region in the substrate at first and second sides of the second gate pattern; and performing a halo ion implantation process to form a first halo region and a second halo region contacting the first low-concentration dopant region and the second low-concentration dopant region under the first gate pattern and the second gate pattern respectively; monitoring processes of forming the first and second transistors to find an error, wherein the error is found by determining a mask misalignment in the low-concentration dopant ion implantation process or the halo ion implantation process; using back data to determine a variation degree of a threshold voltage corresponding to the mask misalignment, wherein the back data includes a plurality of threshold voltage variation degrees corresponding to different misalignment degrees; and performing an additional ion implantation process to adjust a threshold voltage of the low-concentration dopant region or the halo region on the first transistor or the second transistor corresponding to the determined variation degree.