Patent ID: 7370312
Filing Date: 2008-05-06
Classification: G06F

Abstract:
1. A method for simulating the operation of a digital circuit comprising: describing the digital circuit, at least partially, with one or more Term Rewriting System (TRS) rules, wherein each TRS rule includes a predicate and an action body; creating one or more subroutines, each subroutine corresponding to a TRS rule and adapted to perform functions equivalent to functions of the action body of the TRS rule, each subroutine corresponding to one or more simulation values; scheduling one or more TRS rules to execute on a given clock cycle of the simulation; and computing, in response to the scheduling, the one or more simulation values corresponding to a subroutine corresponding to a TRS rule scheduled to execute, wherein the simulation values are not computed where the predicate of the corresponding TRS rule is not true; and selecting a first TRS rule to execute that is in conflict with a second TRS rule on a given clock cycle; preventing the second TRS rule from executing on the given clock cycle.