Patent ID: 6326812
Filing Date: 2001-12-04
Classification: G06F,H03K,H03L

Abstract:
An integrated circuit device comprising:a clock signal generator which produces a first clock signal;an array of respective programmable logic elements which respectively include multiple logic inputs and at least one logic output and which produce at least one logic output signal from one or more logic input signals received at one or more of the multiple logic inputs and wherein respective programmable logic elements include respective storage elements which can temporarily store logic signals and which are responsive to clock signals;a network of logic signal conductors for programmably connecting respective logic outputs of respective programmable logic elements with respective logic inputs of respective programmable logic elements;a network of clock signal conductors which distributes the first clock signal to respective programmable logic elements;a plurality of respective first phase shift elements which respectively are disposed locally within the array of respective programmable logic elements and which receive the first clock signal and which provide respective second clock signals which are respective phase-shifted versions of the first clock signal, shifted in phase by an amount which compensates for prescribed delay in logic signal transmission between storage elements; anda plurality of respective programmable connection circuits, each respectively programmable to provide a respective storage element with at least one of the first clock signal or a respective second clock signal.