Patent ID: 6829700
Filing Date: 2004-12-07
Classification: G06F

Abstract:
A data processor comprising:an instruction execution pipeline comprising N processing stages capable of executing a load instruction; a status register capable of storing a modifiable configuration value, said modifiable configuration value having a first value indicating said data processor is capable of executing a misaligned access handling routine and a second value indicating said data processor is not capable of executing a misaligned access handling routine; a misalignment detection circuit capable of determining if said load instruction performs a misaligned access to a target address of said load instruction and, in response to a determination that said load instruction does perform a misaligned access, generating a misalignment flag; a data protection unit capable of determining if said load instruction access a restricted area of memory and, in response to a determination that said load instruction accesses a restricted area of memory, determining if said load instruction is speculative; and exception control circuitry capable of detecting said misalignment flag and in response thereto determining if said modifiable configuration value is equal to said first value, wherein said exception control circuitry is further capable of, in response to a determination that said load instruction is speculative, causing said data processor to dismiss said load instruction.