Patent ID: 6917380
Filing Date: 2005-07-12
Classification: H04N

Abstract:
1. A one time programmable solid-state device comprising: a programmable memory unit embedded in a die within the one time programmable solid-state device; a driver circuit that programs the programmable memory unit with locations of defective pixels by programming memory cells within the programmable memory unit with a first logic value or a second logic value, wherein each of the memory cells is associated with a corresponding pixel location, and wherein the first logic value represents a good pixel at the corresponding pixel location and the second logic value represents a defective pixel at the corresponding pixel location, wherein the memory cells have a number of rows of memory cells and a number of columns of memory cells; and an access circuit that enables access to the programmable memory unit, wherein the access circuit is configured to drive one of the rows of the memory cells presently being read out to ground while tristating the columns of the memory cells and the other rows of the memory cells.