Patent ID: 9136382
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A transistor fabricated as a native device, comprising: an inner marker region; an active outer region which surrounds the inner marker region; a gate structure having a central portion over the inner marker region and a first end portion and a second end portion projecting from the inner marker region over the active outer region, the gate structure extending in a longitudinal direction; a first medium doped drain implant having a first orientation that is different with respect to the longitudinal direction; a second medium doped drain implant having a second orientation that is different with respect to the longitudinal direction; a first low concentration pocket implant located within the active outer region; a second low concentration pocket implant located within in the active outer region; a first source/drain implant located within the active outer region; and a second source/drain implant located within the active outer region, wherein the gate structure is interposed between the first source/drain implant and the second source/drain implant.