Patent ID: 8241959
Filing Date: 2012-08-14
Classification: H01L

Abstract:
1. A method of making microelectronic packages comprising: making a subassembly including after making said subassembly, juxtaposing said plate with a semiconductor wafer having a top surface and contacts accessible at the top surface; attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer; electrically interconnecting at least some of the electrically conductive features on said dielectric compliant layer and the contacts on said semiconductor wafer; and then dicing the semiconductor wafer and the attached subassembly into a plurality of microelectronic packages, each package including one or more semiconductor die being a severed portion of the semiconductor wafer and including a severed portion of the subassembly.