Patent ID: 6329238
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A semiconductor memory device fabricating method comprising the steps of:forming a groove in a semiconductor substrate at a predetermined location;forming an insulating film all over a resultant surface of said semiconductor substrate;forming selectively a conductive film on a portion of said insulating film, said portion being formed on inner side walls of said groove;forming a separation region by filling said groove with a second insulating film;forming a metal oxide semiconductor transistor on the surface of a desired region other than said separation region on said semiconductor substrate;forming a lower electrode of a storage capacitor, said lower electrode being electrically connected to one of a pair of diffused layers of said metal oxide semiconductor transistor having a conductor type reverse to that of said semiconductor substrate and to said conductive film, said lower electrode extending over said metal oxide semiconductor transistor and said separation region; andforming a dielectric film of said storage capacitor and an upper electrode of said storage capacitor on said lower electrode in a stacked manner.