Patent ID: 6389091
Filing Date: 2002-05-14
Classification: H03K,H03L

Abstract:
A digital phase locked loop for keeping an output signal exactly in phase and frequency with a reference signal, said digital phase locked loop comprising:a phase comparator for comparing a feedback signal with the reference signal in phase and frequency to produce an error signal representative of frequency difference between the feedback signal and the reference signal; a controller connected to said phase comparator for producing a plurality of digital control signal sets in response to the error signal, at least one of the plurality of digital control signal sets comprising a plurality of digital control signals; an oscillator having a plurality of delay elements which are connected to said controller and connected to one another in a loop, each of said delay elements having a delay controlled by one of the digital control signal sets, said oscillator producing the output signal having a frequency decided by a total delay of said delay elements; and feedback means connected between said oscillator and said phase comparator for feeding back the output signal to said phase comparator as the feedback signal; wherein said controller is operative to change said delay of each of said plurality of delay elements to change said total delay.