Patent ID: 6784054
Filing Date: 2004-08-31
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device including a memory cell transistor having stack cell electrodes, said method comprising:a step (a) of forming on a semiconductor substrate in turn from bottom to top, a gate insulating film, a first conductor film, an intermediate insulating film, and a second conductor film; a step (b) of implanting ions of an impurity in the second conductor film; a step (c) of depositing a protective insulating film on the second conductor film after said step (b); a step (d) of performing, after said step (c), a heat treatment for activating the impurity implanted in the second conductor film; a step (e) of performing, after said step (d), patterning in turn the protective insulating film, the second conductor film, the intermediate insulating film and the first conductor film to form the stack cell electrodes consisting of a floating gate electrode, an interlayer capacitor film and a control gate electrode, and an on-gate protective film in turn from bottom to top; a step (f) of forming an impurity diffusion layer in the semiconductor substrate by implantation of ions of an impurity with the stack cell gate electrode used as a mask; a step (g) of depositing an insulating film for a sidewall on the substrate and then performing anisotropic etching on the insulating film to form the sidewall on side surfaces of the stack cell electrode and the topside protective film; and a step (h) of forming a conductor contact adjacent to the sidewall, the contact reaching the impurity diffusion layer.