Patent ID: 7450438
Filing Date: 2008-11-11
Classification: H04L

Abstract:
1. A programmable crossbar for dynamically coupling a plurality of stages of an execution unit to one or more portions of a memory, comprising: a set of address lines coupled with each stage of said plurality of stages for receiving an address signal from at least one stage; and logic for selectively coupling one of said plurality of stages to a portion of the memory, said logic receiving said set of address lines from each stage, said logic comparing a portion of said address signal to one or more hardwired addresses associated with each portion of the memory, said logic receiving a plurality of programmable enable signals corresponding to each stage of said plurality of stages; wherein when the portion of said address signal from one stage of said plurality of stages matches one of the hardwired addresses associated with one portion of the memory, then the one stage of said plurality of stages is coupled with the one portion of memory if the programmable enable signal associated with the one stage is active; wherein the memory includes an on-chip memory and an off-chip memory, and wherein the plurality of stages of the execution unit and the on-chip memory are placed on a same chip.