Patent ID: 7456097
Filing Date: 2008-11-25
Classification: H01L

Abstract:
1. A method for forming a via in a semiconductor device of a type that comprises a silicon substrate and a first dielectric layer on which a bottom conductor layer is located, said first dielectric layer and said bottom conductor layer covered with a second dielectric layer, and said second dielectric layer covered with a resist mask having portions that form an aperture through said resist mask, said method comprising the steps of: applying a first vertical anisotropic dry etch process through said aperture in said resist mask to said second dielectric layer; etching a via cavity though said second dielectric layer down to said bottom conductor layer with said vertical anisotropic dry etch process; removing said resist mask from said second dielectric layer; and applying a second etch process to said second dielectric layer to etch away corner portions of said second dielectric layer.