Patent ID: 8971143
Filing Date: 2015-03-03
Classification: G11C,H03K

Abstract:
1. A semiconductor device comprising: a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal; a first circuit controlled based on the first clock signal; a second circuit controlled based on the second clock signal; and a storage unit storing a first code indicating the first clock cycle and a second code indicating the second clock cycle, wherein the control circuit generates the first clock signal based on the first code when the first command signal is supplied, the control circuit generates the second clock signal based on the second code when the second command signal is supplied, the control circuit includes an oscillator circuit that generates an oscillating signal, each of the first and second codes specifies an oscillating cycle of the oscillating signal, the control circuit generates the first clock signal based on the oscillating signal having an oscillating cycle corresponding to the first code when the first command signal is supplied, and the control circuit generates the second clock signal based on the oscillating signal having an oscillating cycle corresponding to the second code when the second command signal is supplied.