Patent ID: 6912149
Filing Date: 2005-06-28
Classification: G11C

Abstract:
1. A ferroelectric memory device comprising: a plurality of bit line pairs each of which is composed of first and second bit lines; a plurality of sense amplifiers each for amplifying a potential difference across the corresponding bit line pair; a plurality of memory cells provided for the bit line pairs, respectively, each of the memory cells being composed of a first ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the first ferroelectric capacitor and whose drain is connected to the first bit line; a plurality of reference cells provided for the bit line pairs, respectively, each of the reference cells being composed of a second ferroelectric capacitor for retaining data and a transistor whose source is connected to a first electrode of the second ferroelectric capacitor and whose drain is connected to the second bit line; a word line connecting sates of the transistors of the memory cells; a reference word line connecting gates of the transistors of the reference cells; a cell plate line connecting second electrodes of the ferroelectric capacitors of the memory cells; a reference cell plate line connecting second electrodes of the ferroelectric capacitors of the reference cells; a control circuit for controlling operations of the memory cells, the reference cells, and the sense amplifiers; and a switch circuit connecting the second bit lines included in adjacent bit line pairs of the plurality of bit line pairs, wherein the control circuit inactivates the reference word line during the drive of the sense amplifiers, wherein the control circuit stops the drive of the switch circuit during the drive of the sense amplifiers, and wherein the control circuit performs successive actions of: driving the switch circuit and activating the word line, the cell plate line, the reference word line and the reference cell plate line; inactivating the cell plate line and the reference cell plate line; inactivating the reference word line; stopping the drive of the switch circuit; and driving the sense amplifiers.