Patent ID: 6298436
Filing Date: 2001-10-02
Classification: G06F

Abstract:
A method for atomic memory accesses in a processor system, wherein said processor system is able to issue and execute a plurality of instructions out of order with respect to a particular program order, said method comprising the steps of:speculatively issuing a first reservation instruction to an execution unit of a processor system;flushing instructions queued for said execution unit which occur after said first reservation instruction in said program order, in response to detecting any previously executed reservation instructions in said execution unit which occur after said first reservation instruction in said program order; andspeculatively executing said first reservation instruction by placing a reservation for a particular data address of said first reservation instruction, in response to completion of instructions queued for said execution unit which occur prior to said first reservation instruction in said program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.