Patent ID: 7054203
Filing Date: 2006-05-30
Classification: H03K

Abstract:
1. A triple redundant latch for reducing soft errors comprising: a) a first settable memory element; b) a second settable memory element; c) a voting structure/settable memory element; d) wherein an identical logic value is set in each settable memory element and the voting structure/settable memory element; e) wherein the voting structure/settable memory element determines a logical value held on the voting structure/settable memory element after the first settable memory element, the second settable memory element, and the voting structure/settable memory element are set; f) wherein inputs to the voting structure/settable memory element are provided by the first settable memory element, the second settable memory element, and control signals used to set the settable memory elements and the voting structure/settable memory element; g) wherein a propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.