Patent ID: 6306745
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method of routing power and ground for integrated circuit chips, comprising:providing an integrated circuit chip, wherein said integrated circuit chip has a circuit region;partitioning said circuit region of said integrated circuit chip into a number of sub-block regions having spaces therebetween;providing a first power wiring layer and a second power wiring layer;providing first vias between said first power wiring layer and said second power wiring layer;providing second vias between said first power wiring layer and said second power wiring layer;forming a first power bus electrode in said first power wiring layer wherein said first power bus electrode surrounds said circuit region and each of said sub-block regions;forming a second power bus electrode in said second power wiring layer wherein said second power bus electrode is directly under said first power bus electrode, surrounds said circuit region, and surrounds each of said sub-block regions;forming first distribution electrodes in said first power wiring layer electrically connected to said first power bus electrode wherein said first distribution electrodes supply the voltage on said first power bus electrode to each of said sub-block regions;forming second distribution electrodes in said second power wiring layer electrically connected to said first power bus electrode and said first distribution electrodes by means of said first vias wherein said second distribution electrodes supply the voltage on said first power bus electrode to each of said sub-block regions;forming third distribution electrodes in said second power wiring layer electrically connected to said second power bus electrode wherein said third distribution electrodes supply the voltage on said second power bus electrode to each of said sub-block regions; andforming fourth distribution electrodes in said first power wiring layer electrically connected to said second power bus electrode and said third distribution electrodes by means of said second vias wherein said fourth distribution electrodes supply the voltage on said second power bus electrode to each of said sub-block regions.