Patent ID: 7694257
Filing Date: 2010-04-06
Classification: H01L

Abstract:
1. A method for adding filler metal polygons in metal layers of an integrated circuit (IC) design in a chip area comprising the following acts executed by a computer system: computing a size of a filler metal polygon using chip design layout data; identifying one or more regions on the metal layers of the IC design that do not meet a metal density requirement set by a chip manufacturer; filling an entire area of a current one of the identified one or more regions with the computed filler metal polygons; computing available chip area for filling with the computed filler metal polygons by subtracting the entire area of the current one of the identified one or more regions with associated overlapping metal route areas; reducing the computed available chip area by a predetermined shrink factor as a function of the design layout data to form a reduced available chip area; comparing the reduced available chip area with the available chip area of the current one of the identified one or more regions and removing filler metal polygons that fall outside the reduced available chip area; computing a metal density of the reduced available chip area including remaining filler metal polygons; determining whether the computed metal density of the reduced available chip area is less than the metal density requirement; if so, then repeating the reducing, comparing, computing, and determining steps by further reducing the reduced available chip area with the predetermined shrink factor until the computed metal density of the reduced available chip area is equal to or less than the metal density requirement; and if not, then repeating the filling, computing available chip area, reducing, comparing, computing the metal density, and determining steps for a next one of the identified one or more regions until all of the identified one or more regions are filled with filler metal polygons that meet the metal density requirement.