Patent ID: 6066965
Filing Date: 2000-05-23
Classification: G06F,G11C,H03K

Abstract:
A logic circuit that uses 1 of 4 signals, comprising:a shared logic tree circuit that evaluates one or more input signals and produces an output signal;a first input 1 of 4 signal coupled to said shared logic tree circuit wherein said first input 1 of 4 signal comprises a first bundle of 4 wires routed together between different cells and use a 1 of 4 encoding to indicate multiple values of information conveyed by said first bundle of 4 wires and where at most one and only one wire of said first bundle of 4 wires is true during an evaluation cycle:a second input 1 of 4 signal coupled to said shared logic tree circuit wherein said second input 1 of 4 signal comprises a second bundle of 4 wires routed together between different cells and use a 1 of 4 encoding to indicate multiple values of information conveyed by said second bundle of wires and where at most one and only one wire of said second bundle of 4 wires is true during said evaluation cycle;an output 1 of 4 signal coupled to said shared logic free circuit wherein said output 1 of 4 signal comprises a third bundle of 4 wires routed together between different cells and use a 1 of 4 encoding to indicate multiple values of information conveyed by said third bundle of 4 wires and where at most one and only one wire of said third bundle of 4 wires is true during said evaluation cycle.