Patent ID: 6134161
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A logic IC comprising:an embedded memory;a memory array;a memory testing input pin;a memory testing switching pin;a memory testing output pin;a plurality of selectors, each selector corresponding to an input bit of said embedded memory provided between a logic circuit and the input of said embedded memory, wherein each of said selectors receives a signal from said logic circuit and a signal from said memory test input pin for memory-test purposes and forwards either the signal from said logic circuit or the signal from said input pin for memory-test purposes to said embedded memory according to a switching signal supplied to said selector from said switching pin for memory-test purposes; anda memory test data compressing circuit for receiving a read-back signal outputted by said memory array and converting said read-back signal into an output signal through said output pin for memory-test purposes.