Patent ID: 9018969
Filing Date: 2015-04-28
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a first chip including a first plurality of first bumps on a first surface and a plurality of first wirings; and a second chip including a plurality of second bumps and a plurality of second wirings, and being stacked with the first chip such that each of the plurality of second bumps is coupled to a corresponding one of the first plurality of first bumps of the first chip; wherein the first wirings, the first bumps, the second wirings, and the second bumps constitute a single electrical path, and the first wirings, the first bumps, the second wirings and the second bumps are arranged in series with one another in the single electrical path, and the first chip further includes a second plurality of first bumps on a second surface opposed to the first surface, the second plurality of first bumps being respectively aligned with the first plurality of first bumps in a direction perpendicular to the first and second surfaces and being electrically disconnected from the first plurality of first bumps.