Patent ID: 7795903
Filing Date: 2010-09-14
Classification: H03K

Abstract:
1. An output buffer, comprising: a final driver powered by a power supply voltage, the final driver being operable to generate a first value of a data output signal responsive to receiving a first digital signal and to generate a second value of the data output signal responsive to receiving a second digital signal, the rate at which the final driver transitions the data output signal to at least one of the first and second values responsive to the digital signals varying with the magnitude of the power supply voltage, the final driver being operable to generate the first value of the data output signal responsive to receiving a first value of the first digital signal and a first value of the second digital signal, and to generate the second value of the data output signal responsive to receiving a second value of the first digital signal and a second value of the second digital signal, the final driver comprising: a pre-driver receiving the power supply voltage and generating the first and second digital signals responsive to a data input signal, the pre-driver being operable to delay the first digital signal relative to the second digital signal, the magnitude of the delay being a function of the magnitude of the supply voltage and being adjusted to allow the pre-driver to compensate for the variations in the rate at which the final driver transitions the data output signal responsive to variations in the magnitude of the power supply voltage.