Patent ID: 9147449
Filing Date: 2015-09-29
Classification: G11C

Abstract:
1. A multi-level cell (MLC) memory, comprising: a memory cell; a first reference circuit generating a first reference current, a first reference voltage and a first clamp voltage; a second reference circuit generating a second reference current, a second reference voltage and a second clamp voltage; a current supplying circuit comprising a first current source, and receiving the first clamp voltage to develop a first cell current passing through the memory cell to form a first cell voltage; a first multiplexer (MUX); a second MUX; and a sense amplifier, wherein the first cell voltage is used for incorporating with the first reference voltage to determine an information stored in the memory, the first clamp voltage and the second clamp voltage are provided to the current supplying circuit through the first MUX to develop a second cell current passing through the memory cell to develop a second cell voltage, one of the first and the second reference voltages is provided to the sense amplifier through the second MUX to be respectively compared with one of the first and the second cell voltages to determine the information stored in the memory.