Patent ID: 9153696
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including an NMOS region and a PMOS region; a first fin active region protruding from the substrate in the NMOS region, the first fin active region including an upper surface and a sidewall; a second fin active region protruding from the substrate in the PMOS region, the second fin active region including an upper surface and a sidewall; a gate dielectric layer on the upper surfaces and the sidewalls of the first and second fin active regions; a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the first fin active region, a second thickness at the sidewall of the first fin active region, a third thickness at the upper surface of the second fin active region, and a fourth thickness at the sidewall of the second fin active region; and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a fifth thickness at the upper surface of the first fin active region, a sixth thickness at the sidewall of the first fin active region, a seventh thickness at the upper surface of the second fin active region, and an eighth thickness at the sidewall of the second fin active region, wherein the third thickness is less than the fourth thickness, and/or wherein the fifth thickness is less than the sixth thickness.