Patent ID: 6479403
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of patterning a gate electrode layer having an underlying high-k dielectric layer, comprising the sequential steps of:providing a substrate; forming a high-k dielectric layer over the substrate; forming a gate electrode layer over the high-k dielectric layer; patterning the gate electrode layer to form a patterned gate electrode layer, the patterned gate electrode layer having exposed side walls and a top; forming sidewall spacers over the exposed side walls of the patterned gate electrode layer, the sidewall spacers having tops; etching the patterned gate electrode layer to pull the top of the patterned gate electrode layer down from the tops of the sidewall spacers; and removing exposed portions of the high-k dielectric layer not under the sidewall spacers and the pulled-down patterned gate electrode layer.