Patent ID: 6243829
Filing Date: 2001-06-05
Classification: G06F

Abstract:
An apparatus for controlling a data transfer between a data processor and a data unit, comprising:a first control unit having a capability to control the data transfer between the data processor and the data unit, comprising:a first memory controller generating a first address signal, a first control signal, and a first switch control signal;a first memory device coupled to the first memory controller, the first memory device receives the first address signal, the first control signal, and a first data signal to perform a memory access; anda first switch control unit that allows the first control unit to receive data values for the first address signal, the first control signal, and the first data signal, the first switch control unit coupled to the first switch control signal, and the first address signal, the first control signal, and the first data signal;a second control unit that controls the data transfer between the data processor and the data unit, comprising:a second memory controller generating a second address signal, a second control signal, and a second switch control signal;a second memory device coupled to the second memory controller, the second memory device receives the second address signal, the second control signal, and a second data signal, to perform a memory access; anda second signal switch control unit that allows the second control unit to transmit data values from the second address signal to the first address signal, from the second control signal to the first control signal, and from the second data signal to the first data signal, the second signal switch control unit coupled to the second switch control signal, the second address signal, the second control signal, and the second data signal.