Patent ID: 6738836
Filing Date: 2004-05-18
Classification: G06F

Abstract:
A method comprising:performing direct memory accesses from an I/O bridge device to a memory coupled to a processor in a system having multiple processors, each processor having an attached memory that is accessible by other processors, and wherein memory coherency is maintained by a directory based coherence protocol; and maintaining coherency between the memories of the multiple processors and a cache of the I/O bridge device that caches data blocks from at least one of the memories, the maintaining using the directory based coherence protocol; and performing speculative prefetching of data blocks from the memory by the I/O bridge device, the speculative prefetching comprising: issuing a command to invalidate the data blocks in the memory, obtaining exclusive ownership of the blocks by the I/O bridge device, but not obtaining a copy; writing the blocks if the speculation was correct; and issuing a command by the I/O bridge device to release exclusive ownership of the data blocks if the speculation was incorrect.