Patent ID: 8126955
Filing Date: 2012-02-28
Classification: G06F

Abstract:
1. An n-bit adder of a first and second binary number, comprising: a first calculation means with 2n inputs for receiving the n values of bits of said first and second binary numbers and an additional input for receiving an input carry (z an estimation means able to perform a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, taking the complementary of the value of the bit of corresponding rank of the first number, a second calculation means connected to the first calculation means and able to produce a set of correction signals from the propagation signals and diagonal-generation signals, and a correction block comprising n outputs and able to apply, to each estimated bit value of rank k of said sum, k+1 corrections by means of said correction signals, and to deliver as an output the n bits of the sum of the first and second numbers.