Patent ID: 6732280
Filing Date: 2004-05-04
Classification: G06F

Abstract:
A computer system comprising:a host processor under control of an operating system and a basic input/output system having a plurality of states, said states comprising an operating and at least one low power state; a memory device storing the basic input/output system and the operating system for the host processor, the basic input/output systems containing code to cause the host processor to transition on request to a different state; a first power management control register to receive the state of the host processor; a bridge coupled to the host processor; an I/O chip for connecting selected inputs to the bridge; a microcontroller in the I/O chip for providing signals to the bridge from the selected inputs during operation of the computer system; a second power management control register to store the state of the input/output chip microcontroller; the basic input/output system for the first host processor containing code to notify the input/output chip microcontroller when the processor is to transition to a different power state.