Patent ID: 6427159
Filing Date: 2002-07-30
Classification: G06F

Abstract:
An arithmetic unit configured to perform multiply and add operations on three operands A, B and C, A being a multiplicand, B being a multiplier and C being an addend, the arithmetic unit comprising:a multiplier unit including an input stage configured to receive operands A and B from a data pump, the multiplier unit being configured to multiply A with B to provide a product AB, the multiplier unit including an output to provide the product AB; a product register having an input coupled to the multiplier unit output, and having an output; a multiplexer having a first data input coupled to the multiplier unit output, a second data input coupled to the product register output, a toggle command input and a data output; a bypass decision block including an input stage configured to receive the operands A and B, and including an output coupled to a scheduler and to the toggle command input, the bypass decision block being configured to toggle the multiplexer to couple the first data input to the multiplexer data output when the operands A and B have values below a multiplier threshold; and an adder having a first data input coupled to the multiplexer data output and configured to receive the product AB, having a second data input configured to receive the addend C, the adder being configured to add the product AB to C, and the adder having an output to provide a sum AB+C.