Patent ID: 9128748
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A method of simulating a VLSI design in a simulator that controls multiple co-simulators, the method comprising: accepting a simulation task, which includes execution of a VLSI design comprising a hierarchical tree structure partitioned into a plurality of multi-node partitions, over a sequence of a plurality of time slots; assigning each of the co-simulators such that a root node of each partition has a parent node that is not assigned to any of the co-simulators to simulate a respective subset of the partitions; and executing the simulation task by invoking each co- simulator to execute, for each partition and for each time slot of the plurality of simulation time slots: receiving values of input signals of the partition from the simulator; and simulating the partition based on the input signals and a respective database of internal signals which includes an internal state of signals of the partition managed continuously and updated over the sequence of time slots but not shared with the simulator, and providing, to the simulator, signals from the simulation which are required for simulation of other partitions, but not the states of the internal signals such that the simulator does not have full state information with respect to co-simulation states.