Patent ID: 8345873
Filing Date: 2013-01-01
Classification: G06F,H04L

Abstract:
1. A method for scrambling with a scrambler a sequence of p n-state symbols not generated by the scrambler with n equal to or greater than 2 and with p>1, each n-state symbol able to assume one of n states, into a sequence of p scrambled n-state symbols, comprising: inputting an n-state symbol in the sequence of p n-state symbols on a first input of a reversible n-state logic function; receiving on a second input of the reversible n-state logic function an n-state symbol provided by an output of an n-state shift register that is part of an n-state Linear Feedback Shift Register (LFSR) based scrambler in Galois configuration with a shift register of k n-state shift register elements with k<p; providing on an input of the n-state shift register an n-state symbol that is available on an output of the reversible n-state logic function; providing on a tap into the n-state shift register the n-state symbol that is available on the output of the reversible n-state logic function; and providing an n-state symbol in the sequence of p scrambled n-state symbols on an output of the n-state Linear Feedback Shift Register (LFSR) based scrambler in Galois configuration.