Patent ID: 7885097
Filing Date: 2011-02-08
Classification: G11C

Abstract:
1. An apparatus comprising an array of non-volatile memory cells arranged into a plurality of rows and a plurality of columns, each memory cell in the array comprising a switching device and a resistive sense element (RSE), wherein each of the memory cells in a selected column along a bit line direction are connected to a first control line supplied with a variable voltage and a second control line maintained at a fixed reference voltage, and wherein a plural number of the memory cells in the selected column less than all of the memory cells in the selected column are simultaneously programmed to a first resistive state by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line and flowing respective body-drain currents through the associated switching devices of said plural number of memory cells, a remaining plural number of the memory cells along the selected column remaining at a different, second resistive state.