Patent ID: 6680982
Filing Date: 2004-01-20
Classification: H03K,H04L

Abstract:
A jitter-tolerant signal receiver, for receiving an input signal of a first clock domain and output a third event signal of a second clock domain in a communication system, which comprising:a first D flip-flop for receiving the input signal at a first input terminal and a first clock of the first clock domain at a first clock terminal and outputting a first event signal at a first output terminal; a second D flip-flop for receiving a high level signal at a second input terminal and the first event signal at a second clock terminal and outputting a second event signal at a second output terminal; and a third D flip-flop for receiving the second event signal at a third input terminal and a second clock of the second domain at a third clock terminal, and outputting the third event signal at a third output terminal; wherein the second D flip-flop further comprises a reset terminal for receiving the third event signal.