Patent ID: 6618298
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory array comprised of a plurality of memory cells, a plurality of selection lines connected to selection terminals of the plurality of memory cells disposed in a first direction, and a plurality of signal lines connected to data input/output terminals of the plurality of memory cells disposed in a second direction, said semiconductor memory device being formed as a semiconductor integrated circuit on a semiconductor chip, wherein said semiconductor chip is provided with an external terminal in addition to a power supply terminal via which a supply voltage is supplied for the operations of all the circuits disposed thereon, said external terminal being enabled to supply a first voltage to said memory array at the time of a test performance, said first voltage being different from said supply voltage, and wherein a first switching element is provided at a halfway of a path that transmits said first voltage from said external terminal to said memory array, said first switching element comprised of an N-channel or P-channel MOS transistor.