Patent ID: 7404125
Filing Date: 2008-07-22
Classification: G11C

Abstract:
1. A memory structure configured for supporting multiple test methodologies, comprising: a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith; a second multiplexer configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, said memory logic connection coupled to said at least one data input path, with an output of said test latch defining a data out customer connection; and flush logic configured to direct data from said memory logic connection to said data out customer connection during a test of logic associated with a customer chip, thereby facilitating observation of said memory logic connection at said customer chip; wherein test elements of the memory structure comprise a scan architecture of a first type and test elements of said customer chip comprise a scan architecture of a second type.