Patent ID: 8085104
Filing Date: 2011-12-27
Classification: H03K,H03L

Abstract:
1. A driving circuit adapted to trigger an oscillator to oscillate, the driving circuit comprising: a control unit; a first input end, coupled to the control unit, adapted to receive a first enable signal; a second input end, coupled to the control unit, adapted to receive an output signal of the oscillator; and an output end coupled to the control unit and an enable end of the oscillator to transmit a second enable signal generated by the control unit to the oscillator, wherein the control unit generates the second enable signal according to the first enable signal and the output signal, and when a number of waves of the output signal within a predetermined period is smaller than a predetermined value, the control unit adjusts a voltage level of the second enable signal: wherein the control unit comprises: a first logic circuit having two input ends and one output end, wherein one of the two input ends of the first logic circuit receives the first enable signal, the other one of the two input ends of the first logic circuit receives a pulse width signal, and the first logic circuit performs a logic operation according to the first enable signal and the pulse width signal to output the second enable signal from the output end of the first logic circuit; a regulating circuit having two input ends and one output end, wherein one of the two input ends of the regulating circuit is coupled to the output end of the first logic circuit to receive the second enable signal, the other one of the two input ends of the regulating circuit is coupled to the oscillator to receive the output signal, and the regulating circuit generates and outputs a regulating signal according to the output signal and the second enable signal; and a pulse width circuit adapted to convert the regulating signal to the pulse width signal, wherein an input end of the pulse width circuit is coupled to the output end of the regulating circuit, and an output end of the pulse width circuit outputs the pulse width signal to the first logic circuit; wherein the first logic circuit is an AND gate.