Patent ID: 7215172
Filing Date: 2007-05-08
Classification: H03K

Abstract:
1. A clamping circuit comprising: a current mirror circuit including transistors constituting a mirror pair disposed at ground side, each of the transistors being connected to a power source through a resistance element; a plurality of adjusting transistors connected in parallel to a first transistor as one transistor of the current mirror circuit at a side for determining mirror current flowing in the current mirror circuit; a plurality of switch circuits that are respectively connected to conduction control terminals of the plural adjusting transistors in connection with one another and control the conduction states of the corresponding adjusting transistors; and a clamping transistor that has a conduction control terminal connected to a power source side terminal of a second transistor as the other transistor of the mirror pair, and clamps a voltage applied to a clamp terminal with the potential of the conduction control terminal as a reference.