Patent ID: 8421142
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a substrate; a well region formed in the substrate; device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction; isolation insulators buried in the isolation trenches to isolate the device regions from one another; floating gates disposed on the device regions via gate insulators; a control gate disposed on the floating gates via an intergate insulator; first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region; and second diffusion suppressing layers formed on side surfaces of the respective upper device regions, the side surfaces being perpendicular to the second direction.