Patent ID: 6709918
Filing Date: 2004-03-23
Classification: H01L,Y10S

Abstract:
A method for making metal-insulator-metal (MIM) capacitors on a substrate comprising the steps of:providing said substrate having partially completed semiconductor circuits including at least one level of metal interconnections embedded in a first insulating layer; forming consecutively a first etch-stop layer, a second insulating layer, a second etch-stop layer, and a third insulating layer, and using a dual-damascene process to form first and second recesses in said third insulating layer, and to for first via holes in said second insulating layer, and depositing a first barrier layer and a first copper layer, and polishing to form contacts in said first via holes and to form copper capacitor bottom plates in said first recesses and interlevel electrical interconnections in said second recesses coplanar with said third insulating layer; depositing a capacitor dielectric layer, a metal layer, and a third etch-stop layer on said second insulating layer and over said capacitor bottom plates; forming a photoresist mask and plasma etching said third etch-stop layer and said metal layer and partially etching into said capacitor dielectric layer to form capacitor top plates aligned over said capacitor bottom plates, and concurrently using said photoresist mask and said plasma etching to form metal resistors; depositing a blanket fourth insulating layer on said substrate; etching second via holes in said fourth insulating layer to said third etch-stop layer on said capacitor top plates and on said metal resistors, and selectively removing said third etch-stop layer in said second via holes; depositing a second barrier layer and a second seed layer, and electroplating a second copper layer and polishing back to form interlevel contacts in said second via holes; and, using a standard copper metal-line-and-interconnect process to form the remaining electrical interconnections.