Patent ID: 6270307
Filing Date: 2001-08-07
Classification: H01L,Y10S,Y10T

Abstract:
A method for orienting a plurality of semiconductor wafers each of which has a v-notch formed on the outer periphery, comprising the steps of:providing a cassette means for supporting said plurality of wafers in parallel supporting slots, said cassette means engaging the periphery of each wafer for supporting each wafer in individual slots with side edges of all wafers in alignment to each other and having and opened end;appending a cover assembly to the top end of said cassette means and inverting said cassette means to allow wafers to be gravitationally biased against a plurality of orienting mechanisms fixidly attached to said cover assembly, said orienting mechanisms are arranged to correspond to each wafer position of said cassette means, each of said orienting mechanisms comprising a v-block disposed substantially normal to and in vertical alignment below said wafer axis, said v-block having one degree of vertical freedom relative to said cassette means, a spring means for biasing the apex of said v-block towards the peripheral edge of its wafer, said v-block is linked to and disposed between a pair of elbow members each having a friction drive roller in a first position for engaging the periphery of its wafer, driving means for rotatively driving said drive rollers to impart rotation to said wafer for aligning said notch with said v-block, said apex of said v-block is urged into notch when notch is aligned, therein imparting vertical movement of said v-block to effect said drive rollers to move to a second position away from the periphery of said wafer.