Patent ID: 7429854
Filing Date: 2008-09-30
Classification: G05F

Abstract:
1. A CMOS current mirror circuit comprising: a first MOS transistor and a second MOS transistor constituting a current mirror; and a third MOS transistor with a gate terminal thereof biased to a predetermined potential, inserted between a source of said first or second MOS transistor in an input side or an output side of said current mirror and the ground to accommodate a predetermined nonlinear input-output characteristic, wherein: gates of said first and second MOS transistors are connected in common; a source of said first MOS transistor is grounded through said third MOS transistor; a source of said second MOS transistor is directly grounded; a source of said third MOS transistor is directly grounded, a drain of said third MOS transistor is connected to said source of said first MOS transistor and the gate of said third MOS transistor is connected to a bias voltage source; the gate and a drain of said first MOS transistor is connected in common for current input; and an output current is supplied from a drain of said second MOS transistor.