Patent ID: 8048713
Filing Date: 2011-11-01
Classification: H01L

Abstract:
1. A process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode and a cathode, wherein the process comprises: a) providing, on a semiconductor support, an insulating layer, b) providing, in said insulating layer a set of first contacts, the set of first contacts comprising at least first contact and a second contact that is electrically insulated from the first contact by the insulating layer, wherein each of the first and second contacts forms a portion of a separate memory point, c) providing, over said insulating layer and said first and second contacts, a sublayer made of a high thermal conductivity material, higher than 1.3 W/m/K, wherein said sublayer extends over the insulating layer from the first contact to the second contact to cover at least a portion of each of the first and second contacts and the insulating layer separating the first and second contacts to form: (i) a continuous electrically-conductive path that electrically connects the first and second contacts separated by the insulating layer, and (ii) an exposed surface formed uniformly of the high thermal conductivity material that extends over an extent of the insulating layer that extends between the first and second contacts, d) providing, on said uniform exposed surface of the sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer of second contact, and e) etching between areas located above the first and second contacts to remove at least a portion of the high thermal conductivity material forming the electrically-conductive path over the insulating layer electrically connecting the first and contacts to provide individual memory points that are electrically insulated from each other.