Patent ID: 8835291
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, the method comprising: providing a substrate; forming a gate dielectric layer over the substrate; forming a gate electrode layer over the gate dielectric layer, the gate electrode layer being crystalline or polycrystalline; amorphizing, after the forming the gate electrode layer, only an upper portion of the gate electrode layer, thereby creating an amorphized gate electrode layer, a lower portion of the gate electrode layer remaining crystalline or polycrystalline, the lower portion of the gate electrode having a first grain structure, the lower portion of the gate electrode layer being interposed between the upper portion of the gate electrode layer and the substrate; recrystallizing the upper portion of the gate electrode layer such that the upper portion has a second grain structure after the recrystallizing, the second grain structure being a different grain structure than the first grain structure of the lower portion; and after the amorphizing, patterning the gate electrode layer to form a gate electrode.