Patent ID: 8977915
Filing Date: 2015-03-10
Classification: G11C

Abstract:
1. An embedded memory test system comprising of: a programmable Built In Self Test (pBIST) engine, said pBIST engine generating a 4 bit data word wdata[3:0] and a 3 bit control signal ctl[2:0]; a plurality of distributed data logging circuits communicating with the pBIST engine; a plurality of bus expanders, each of said bus expanders connected to a corresponding distributed data logger, each of said bus expanders connected to said pBIST engine to receive said 4 bits of data and said 3 bit control signal, each of said bus expanders expanding said 4 bit data word wdata[3:0] into a 32 bit expanded data word wdata[31:0] as follows one or more memory blocks operable with each distributed data logger.