Patent ID: 6037620
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A semiconductor memory cell, comprising:a storage capacitor formed in a trench etched into a substrate;a transfer device formed in a substantially electrically isolated semiconductor region lying entirely outside said trench, said transfer device having a conduction path extending in a direction of a perimeter of said trench, said semiconductor region having a buried strap electrical interconnection with said trench, said transfer device comprising an insulated gate field effect transistor (IGFET) having a channel region located at a position of said perimeter which is removed from said electrical interconnection, wherein said buried strap is located at a position which does not present a straight line conduction path to said channel region, said IGFET including a pair of source drain regions connected to said buried strap and to a bitline contact, respectively, and said bitline contact is located at a position across said trench from said buried strap.