Patent ID: 8640008
Filing Date: 2014-01-28
Classification: G06F

Abstract:
1. A data processing apparatus configured to perform data processing operations in response to a sequence of instructions, said data processing apparatus comprising: a plurality of error detection units, each error detection unit configured to generate a first sample of a signal associated with execution of an instruction, configured to generate a second sample of said signal after a delay period, and configured to generate an error signal if said first sample and said second sample differ; error value generation circuitry configured to generate an error value indicative of whether any of said plurality of error detection units have generated said error signal; error value stabilisation circuitry configured to receive said error value and to perform a stabilisation procedure on said error value, said stabilisation procedure comprising re-sampling said error value to remove metastability from said error value resulting from metastability of said error signal generated by at least one of said error detection units; error recovery circuitry configured to receive said error value from said error value stabilisation circuitry and to initiate re-execution of said instruction if said error value indicates that said error signal was generated by at least one of said error detection units; count circuitry configured to hold a counter value in association with said error value, said counter value being set to a predetermined value when said error value is generated, and said count circuitry configured to decrement said counter value each time said error value is re-sampled prior to reaching said error value stabilisation circuitry; and bypass circuitry configured to pass said error value to said error recovery circuitry directly without being subjected to said stabilisation procedure if said counter value is zero before said error value reaches said error value stabilisation circuitry.