Patent ID: 6624685
Filing Date: 2003-09-23
Classification: G06F,G11C,H03K

Abstract:
A circuit, comprising:a first transistor having a current path coupled between a supply terminal and a first output terminal, the first transistor current path having a width and a length; a second transistor having a current path coupled between the first output terminal and a reference terminal, the second transistor current path having a width and a length; a comparator circuit having first and second input terminals and having a second output terminal, the first input terminal coupled to the first output terminal, wherein the comparator circuit is enabled in response to a first logic state of a control signal and disabled in response to a second logic stale of the control signal; a first load transistor having a current path coupled to the comparator circuit and having a control gate coupled to receive a control voltage; a feedback transistor having a control gate coupled to the second output terminal and having a current path coupled to the second input terminal; a plurality of resistors connected in series to a reference voltage terminal between the current path of the feedback transistor and the reference terminal; and a second load transistor having a current path coupled between the plurality of resistors and the reference terminal, wherein a reference voltage at the reference voltage terminal is equal to a difference between a voltage at the first output terminal and a voltage that is a product of a current through the load transistor and a resistance of at least one resistor of the plurality of resistors.