Patent ID: 7554364
Filing Date: 2009-06-30
Classification: H03F

Abstract:
1. An input stage comprising: (a) differentially coupled first and second input JFETs (junction field-effect transistors), a gate of the first input JFET being coupled to receive a first input signal and a gate of the second input JFET being coupled to receive a second input signal; (b) a first active current source transistor coupled between a first reference voltage and a drain of the first input JFET, and a second active current source transistor coupled between the first reference voltage and a drain of the second input JFET; (c) a separator JFET having a drain coupled to a source of the first input JFET and a source coupled to a source of the second input JFET; (d) a control circuit having a first input coupled to the drain of the first input JFET, a second input coupled to the drain of the second input JFET, and an output coupled to a gate of the separator JFET for controlling the separator JFET in response to the first and second input signals so as to limit a reverse bias voltage across a gate-source junction of one of the first and second input JFETs; and (e) bias current circuitry coupled to bias the first and second input JFETs, respectively.