Patent ID: 8580631
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps: providing a substrate; forming a gate dielectric layer on said substrate; forming a gate polysilicon layer over said substrate and said gate dielectric layer; etching said gate polysilicon layer to form: forming sidewall spacers abutting said NMOS gate and abutting said PMOS gate; forming an NSD implant mask over said substrate which: performing an NSD implant operation which implants n-type dopants into said substrate adjacent to said NMOS gate to form NSD layers and into said body region of said resistor layer; forming a PSD implant mask over said substrate which: performing a PSD implant operation which implants p-type dopants into said substrate adjacent to said PMOS gate to form PSD layers and into said body region of said resistor layer; forming a resistor silicide block layer over said body region of said resistor layer, such that said resistor silicide block layer includes different dielectric material than said sidewall spacers; forming metal silicide layers on said head regions of said resistor layer, on said NSD layers adjacent to said NMOS gate, and on said PSD layers adjacent to said PMOS gate; forming a PMD layer over said silicide layers and over said resistor silicide block layer; and forming contacts through said PMD layer, said contacts making electrical connection to said silicide layers on said NSD layers and to said silicide layers on said PSD layers.