Patent ID: 8634248
Filing Date: 2014-01-21
Classification: G11C

Abstract:
1. A method of operating a non-volatile array of a NAND architecture, the array having NAND strings formed along bit lines and spanned by word lines, where the bit lines span a plurality of the blocks and are each connected to a corresponding set of latches, the method comprising: reading a first page of data from a first word line of the array; storing the first page of data in a first of the latches for each of the bit lines of the array; reading a second page of data from a second word line of the array, the first and second of the word lines being different; storing the second page of data in a second of the latches for each of the bit lines of the array, wherein the first and second latches for each of the bit lines are different; performing within said sets of latches one or more arithmetical/logical operations upon the contents of the first and second latches; subsequently to performing said one or more arithmetical/logical operations, writing the result thereof from the sets of latches along a third word line of the array.