Patent ID: 6937684
Filing Date: 2005-08-30
Classification: H03L,H04L

Abstract:
1. A phase compensation circuit in a digital phase lock loop, comprising: a first computation unit for computing the absolute value of the real part of a frequency domain signal sample; a second computation unit for computing the absolute value of the imaginary part of said frequency domain signal sample; an adder for computing the sum of the absolute value of the real part of said frequency domain signal sample and the absolute value of the imaginary part of said frequency domain signal sample; a weighting circuit for multiplying the output of said adder with a ratio adjustment factor to generate a weighting factor; a subtracter for computing the difference between the absolute value of the imaginary part of said frequency domain signal sample and the absolute value of the real part of said frequency domain signal sample to form a phase correction term; and a multiplier for multiplying said weighting factor with said phase correction term to form a phase compensation value.