Patent ID: 6023099
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A semiconductor integrated circuit device fabricated on a substrate having a major surface containing a central area assigned to memory cells forming a part of an integrated circuit and a peripheral area assigned to a peripheral circuit forming another part of said integrated circuit, comprising:a plurality of conductive lines respectively disposed over said central area and over said peripheral area;a multiple-layered inter-level insulating structure formed on said major surface so as to cover said plurality of conductive lines, and having at least one inter-level insulating layer spaced from said major surface and a plurality of contact holes to which upper surfaces of said plurality of conductive lines are exposed, wherein said at least one inter-level insulating layer includes a first layer;a wiring pattern formed on said at least one inter-level insulating layer so as to provide conductive paths in said integrated circuit, and located over a certain conductive line selected from said plurality of conductive lines and located over said central area;a dummy pattern formed of a conductive material identical with that for said wiring pattern on said at least one inter-level insulating layer, located over another conductive line selected from said plurality of conductive lines and located over said peripheral area, and isolated from functioning elements of said integrated circuit; anda conductive means formed on said multiple-layered inter-level insulating structure so as to provide conductive paths in said integrated circuit, and held in contact with said plurality of conductive lines through said plurality of contact holes;wherein said dummy pattern is formed so that said conductive means is approximately the same distance from the substrate over the central area as over the peripheral area.