Patent ID: 6424567
Filing Date: 2002-07-23
Classification: H03K

Abstract:
A programmable device, comprising:a plurality of programmable cells, each programmable cell of said plurality of programmable cells including a first memory element including an electrically erasable transistor that is configured to receive a first logic value from an external source to form a first stored logic value, a second memory element coupled that is configured to receive the first stored logic value from the first memory element to form a second stored logic value, and a transfer device, operably coupled to the first memory element and the second memory element, having a control input that is common to the plurality of programmable cells that effects a transfer of the first stored logic value to the second memory element; and a system, operably coupled to said plurality of programmable cells, having an output that depends upon the second stored logic value, wherein said system is inoperative during a reception of the first stored logic value by the second memory element.