Patent ID: 8189396
Filing Date: 2012-05-29
Classification: G11C

Abstract:
1. A memory device of the non-volatile type comprising: a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line being coupled to the main word line by a respective two-transistor-only local word line driver circuit, each of the two-transistor-only local word line driver circuits having a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal; wherein during a programming operation of a selected sector the first biasing terminal is set at a negative voltage; wherein during the programming operation of the selected sector the transistors of the two-transistor-only local word line driver circuits of the selected sector are biased such that de-selected local word lines from the selected sector are biased at said negative voltage; and wherein the transistors are biased such that during an erase operation, local word lines of a non-selected sector are biased at a positive voltage.