Patent ID: 8315103
Filing Date: 2012-11-20
Classification: G11C

Abstract:
1. An integrated circuit flash memory device comprising: an array of regular flash memory cells; an array of dummy flash memory cells; an array of selection transistors, wherein a plurality of regular flash memory cells, at least one dummy flash memory cell and at least one selection transistor are serially connected to provide a NAND flash memory device; and an erase controller that is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device; wherein the erase controller is configured to apply a read bias voltage, a pass bias voltage, a string selector line bias voltage, a bit line bias voltage or a predetermined bias voltage that is less than a floating voltage, to the dummy flash memory cells and to concurrently apply a bias voltage that is less than the read bias voltage, the pass bias voltage, the string selector line bias voltage, the bit line bias voltage or the predetermined bias voltage that is less than the floating voltage, respectively, to the regular flash memory cells during the erase operation.