Patent ID: 7275201
Filing Date: 2007-09-25
Classification: G06F,H03M

Abstract:
1. A memory system, comprising: a memory having a plurality of memory modules, each one of the memory modules having a plurality of memory chips, each one of the chips storing a corresponding one of a plurality of nibbles of a word stored in such memory module, such nibbles having an error correction and detection code; a memory controller operating in response to clock pulses, for producing a read command and memory module select signal to the plurality of memory modules to thereby select for reading from the memory, the nibbles of a selected one of the memory modules; an expected read strobe window detection section, responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each one of a plurality of read strobes associated with a corresponding one of the memory chips is expected and is responsive to each one of the read strobes and the produced time window for producing, for one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals, each one of the NIBBLE ERROR signals indicating whether the corresponding one of the read strobes is within the produced window or is absent from such window; and an error corrector and detector, response to each one of the produced NIBBLE ERROR signals, for correcting the word if only one of the NIBBLE ERROR signals indicates the read strobe is absent from the window and for indicating that the word has an error if more than one of the NIBBLE ERROR signals indicates the read strobe are absent from the window.