Patent ID: 8320210
Filing Date: 2012-11-27
Classification: G11C

Abstract:
1. A tracking circuit comprising: a dummy bit line; a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal, wherein the wordline activation signal causes activation of a memory cell; and a second circuit responsive to discharge of the dummy bit line to enable access to the memory cell; wherein the first circuit comprises: a third circuit to detect activation of a wordline and to generate the wordline activation signal in response to detection; and a plurality of transistors in series connection to discharge the dummy bit line in response to the first signal and the wordline activation signal; wherein the third circuit comprises: an electrical line; a first n-type metal oxide semiconductor (NMOS) transistor, having a gate coupled to the wordline and a drain coupled to the electrical line, to discharge the electrical line in response to the activation of the wordline; and a fourth circuit to generate the wordline activation signal in response to the discharge of the electrical line.