Patent ID: 8110911
Filing Date: 2012-02-07
Classification: H01L,H05K

Abstract:
1. A semiconductor chip package in which a substrate provided on a front face side, a semiconductor chip mounted on the substrate, and external electrodes located on a back face side opposite the substrate and connected to the semiconductor chip are integrally packaged, wherein the substrate has a first wiring pattern formed on a surface thereof; the semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions; post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by an insulation tape affixed to the entire surface of a support plate are connected to the first wiring pattern formed on the substrate at predetermined positions; and holes are formed in the insulation tape on the back face side from which the support plate has been separated; and the external electrodes connected to the second wiring pattern exposed through openings of the holes are formed.