Patent ID: 6720227
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A method of forming source/drain regions in a semiconductor device, comprising:forming a gate electrode above a semiconducting substrate; forming source/drain regions in said substrate adjacent said gate electrode by performing at least the following steps: performing a first ion implantation process using arsenic at a dopant concentration level ranging from approximately 1Ã—1015 to 1Ã—1016 ions/cm2 and at an energy level ranging from approximately 100 eV-3 keV to partially form source/drain extensions for the device; performing a second ion implantation process using arsenic at a dopant concentration level ranging from approximately 1Ã—1014 to 9Ã—1014 ions/cm2 and at an energy level ranging from approximately 3-7 keV to partially form source/drain extensions for the device; and performing a third ion implantation process to further form source/drain regions for the device using dopant atoms comprised of at least one of arsenic and phosphorous.