Patent ID: 8458532
Filing Date: 2013-06-04
Classification: G06F,Y02D

Abstract:
1. Apparatus for processing data comprising: a plurality processing circuits, each of said circuits including a cache memory configured to store data values from a main memory; and coherency control circuitry coupled to said plurality of processing circuits and configured to control coherency of data values stored within said plurality of processing circuits; wherein said coherency control circuitry includes: (i) a TAG memory storing address values indicative of memory addresses within said main memory of data values stored within said plurality of processing circuits; and (ii) error detection circuitry coupled to said TAG memory, said error detection circuitry configured to detect an error within an entry of said TAG memory corresponding to a storage location within a cache memory of a processing circuit of said plurality of processing circuits and upon detection of said error to force a hit operation within said storage location, wherein said error detection circuitry is triggered by an access request to a target memory address received from one of said plurality of processing circuits to read said entry within said TAG memory and to detect said error, wherein said access request triggers reading of a plurality of entries within said TAG memory, each of said plurality of entries corresponding to a candidate storage location for data corresponding to said target memory address within a respective cache memory of said plurality of processing circuits.