Patent ID: 8044741
Filing Date: 2011-10-25
Classification: H03B,H03L

Abstract:
1. A digitally controlled oscillator circuit, the circuit comprising: an oscillator circuit providing a frequency programmable output, and including: a phase detector circuit receiving a frequency reference and a derivative of the output, and operable to compare the frequency reference with a derivative of the output, and to provide a control word based at least in part on the comparison of the frequency reference and the derivative of the output that governs switching of the first flicker noise reducing switch and the second flicker noise reducing switch, wherein the first flicker noise reducing switch includes: a first N-type transistor; a second N-type transistor; a third N-type transistor; a first P-type transistor; a second P-type transistor; a resistor; and wherein a source of the first P-type transistor and a source of the second P-type transistor are electrically coupled to an upper voltage threshold via the resistor; wherein a source of the first N-type transistor and a source of the second N-type transistor are electrically coupled to a lower voltage threshold; wherein a drain of the first P-type transistor is electrically coupled to a drain of the first N-type transistor, and a drain of the second P-type transistor is electrically coupled to a drain of the second N-type transistor; wherein a drain of the third N-type transistor is electrically coupled to a first portion of the first capacitance and to the drain of the first N-type transistor; wherein a source of the third N-type transistor is electrically coupled to a second portion of the first capacitance and to the drain of the second N-type transistor; and wherein the control word is electrically coupled to gates of the first N-type transistor, the second N-type transistor, the third N-type transistor, the first P-type transistor and the second P-type transistor; and wherein the second flicker noise reducing switch includes: a fourth N-type transistor; a fifth N-type transistor; a sixth N-type transistor; a third P-type transistor; a fourth P-type transistor; and wherein a source of the third P-type transistor and a source of the fourth P-type transistor are electrically coupled to the upper voltage threshold via the resistor, wherein a source of the fourth N-type transistor and the fifth N-type transistor are electrically coupled to a lower voltage threshold; wherein the drain of the third P-type transistor is electrically coupled to the drain of the fourth N-type transistor, and the drain of the fourth P-type transistor is electrically coupled to the drain of the fifth N-type transistor; wherein a drain of the sixth N-type transistor is electrically coupled to a first portion of the second capacitance and to the drain of the fourth N-type transistor; wherein a source of the sixth N-type transistor is electrically coupled to a second portion of the second capacitance and to the drain of the fifth N-type transistor; and wherein the control word is electrically coupled to gates of the fourth N-type transistor, the fifth N-type transistor, the sixth N-type transistor, the third P-type transistor and the fourth P-type transistor.