Patent ID: 9136270
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A memory device comprising: a substrate having an active region and a field region defining the active region, the field region having a device isolation trench; a device isolation layer in the device isolation trench of the substrate, the device isolation layer including, a first insulation layer in a lower portion of the device isolation trench, the first insulation layer having a first conductive filler in a first void, a second insulation layer in an upper portion of the device isolation trench, the second insulation layer having a second conductive filler in a second void, and a separation layer between the first insulation layer and the second insulation layer; a gate structure on the active region of the substrate, the gate structure including a buried gate conductive layer; an impurity layer on the active region and adjacent to the gate structure; and a conductive interconnector contacting the impurity layer, wherein the first and the second conductive fillers include a same material as the buried gate conductive layer.