Patent ID: 6214680
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing an active area in a semiconductor substrate separated from other active areas by isolation regions;forming a first oxide layer overlying said semiconductor substrate and said isolation regions;patterning and etching away said first oxide layer in two distinct areas and within said active area to form two openings to said semiconductor substrate;growing intrinsic silicon regions to fill each of said openings;etching away said first oxide layer in said active area between said intrinsic silicon regions forming a gate opening to said semiconductor substrate;conformally depositing a gate oxide layer within said gate opening and overlying said oxide layer and said intrinsic silicon regions;depositing a conducting layer overlying said gate oxide and filling said gate opening;planarizing said conducting layer to form a gate electrode within said gate opening;growing a second oxide layer whereby portions of said conducting layer and said intrinsic regions are consumed such that more of said consumption occurs near the upper surfaces of said conducting layer and said intrinsic regions than in the lower portions;etching away said second oxide layer and a portion of said first oxide layer and said gate oxide layer thus forming a V-shaped trench between said conducting layer and said intrinsic regions;implanting first dopant ions into said substrate under said V-shaped trench to form source/drain extensions;depositing a third oxide layer filling said V-shaped trench and overlying said conducting layer and said intrinsic regions;implanting second dopant ions into said gate electrode and into said intrinsic regions to form source/drain regions; andsiliciding said gate electrode and said source/drain regions completing fabrication of said integrated circuit device.