Patent ID: 6247138
Filing Date: 2001-06-12
Classification: G11C,H03K,H04L

Abstract:
A semiconductor integrated circuit device having a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying said control command, set active for a predetermined period, as a DRAM control signal to said DRAM core, whereinsaid timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates said DRAM control signal by setting said control command active in a prescribed operation cycle only for a period starting at a first predetermined clock pulse of a first clock of said n clocks and ending at a second predetermined clock pulse of a second clock of said n clocks, wherein said timing adiusting circuit includes:a first counter for counting said first clock;a second counter for counting said second clock; anda timing buffer circuit for generating said DRAM control signal by setting said control command active for a period starting from the time that the count value of said first counter reaches a first value and lasting until the time that the count value of said second counter reaches a second value.