Patent ID: 8027218
Filing Date: 2011-09-27
Classification: G06F,G11C,Y02D

Abstract:
1. A processor comprising: a cache memory that comprises: an array; word lines; bit lines; a control module that accesses cells of said array during access cycles to access instructions stored in said cache memory; and a row decoder, wherein said control module selectively performs one of a first sequential read and a first discrete read to access instructions in a first set of cells of said array that are connected to a first word line and that selectively performs one of a second sequential read and a second discrete read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line, and wherein said control module generates a word line signal via said row decoder to access said first set of cells, wherein said word line signal defines an extended period to increase bit line separation, wherein said extended period is based on a predetermined number of read cycles, and wherein said second word line is different than said first word line.