Patent ID: 8045674
Filing Date: 2011-10-25
Classification: H03D,H03K,H03L

Abstract:
1. A method for signal processing, the method comprising: in a fractional-N phase-locked-loop (PLL) synthesizer that comprises a divider and a VCO, generating a divider signal in said divider from an output reference signal generated from said VCO, wherein said divider comprises at least one divider stage that utilizes true single phase clock (TSPC) logic D flip-flops for dividing said VCO output reference signal, wherein said TSPC logic D flip-flops comprise a NAND gate coupled to a D input of said D flip-flops; re-synchronizing said VCO output reference signal and said divider signal, wherein said divider comprises at least two re-synchronization stages that utilize a TSPC logic D flip-flop; and feeding back said generated divider signal within said fractional-N PLL synthesizer to produce said VCO output reference signal.