Patent ID: 7598571
Filing Date: 2009-10-06
Classification: H01L

Abstract:
1. A semiconductor device having vertical channels, the device comprising: a plurality of active regions protruded from a top surface of the semiconductor substrate; first element isolation layers which separate adjacent active regions, the first isolation layers extending in a first direction and having top surfaces that are higher than at least the top surfaces of the active regions; second element isolation layers which extend at a predetermined angle with respect to the first direction, separate the adjacent active regions, and have top surfaces lower than the top surfaces of the active regions so as to expose at least a portion of the sidewalls of the active regions such that vertical channels can be formed; a gate insulation aver formed on the plurality of active regions; and gate electrodes formed on the first element isolation layers and the gate insulation layer, wherein the gate insulation layer and the gate electrodes cover the sidewalls and top surfaces of the exposed portion of the active regions.