Patent ID: 6407640
Filing Date: 2002-06-18
Classification: H03F

Abstract:
A method for designing a low noise amplifier (LNA), wherein:(a) the LNA comprises a first stage and a second stage; and (b) the method comprises the steps of (1) simulating a plurality of source impedances ZS2 for the second stage; (2) choosing a desirable first stage load impedance, ZL1opt, in an IIP3 contour plot; (3) recording a corresponding first stage output impedance, ZC1(4) sweeping through all the source impedances ZS2 that were simulated for the second stage; (5) for each source impedance, calculating an inter-stage network that: (A) transforms ZC1 into ZS2; and (B) transforms the corresponding second stage input impedance, ZB2, into a load impedance to the first stage, ZL1; (6) calculating ZL1; (7) recording the relative deviation from the simultaneous matching condition, given as Zdev=|(ZL1âˆ’ZL1opt)ZL1opt|; (8) plotting a contour plot of Zdev versus second stage source impedance; (9) on top of this contour plot, overlaying an IIP3 contour plot for the second stage; and (10) based on this plot overlay, choosing a suitable compromise between good second stage IIP3 and fulfilling the optimum load requirements of the first stage.