Patent ID: 6710404
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A high voltage device comprising:a semiconductor substrate having first, second and third regions, the first region having sidewalls at both sides, and the second and third regions located at a height higher than that of the first region and at both sides of the first region; a channel region formed within a surface of the substrate belonging to the first region including at least one of the sidewalls; a first insulating film formed on a surface of the first region including at least one of the sidewalls; buffer conductive films formed to be adjacent to the sidewalls of the first region and isolated from each other; a second insulating film formed between the buffer conductive films to have a recess portion; a third insulating film formed on an entire surface including the buffer conductive films; a gate electrode insulated from lower layers by the third insulating film to fill the recess portion and formed to partially overlap the buffer conductive films; drift regions respectively formed in the second and third regions to have a first depth; and source and drain regions formed in the second and third regions to have a second depth less than the first depth.