Patent ID: 7919415
Filing Date: 2011-04-05
Classification: H01L,H01S

Abstract:
1. A process of manufacturing a semiconductor device, comprising the steps of: a) forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In, said second III-V compound semiconductor layer being formed directly on said first III-V compound semiconductor layer, where said second III-V compound semiconductor layer is disposed above said first III-V compound semiconductor layer; b) growing an InP layer at regions adjacent said stacked structure to form a stepped structure of InP, said stepped structure and said stacked structure together forming a composite structure; c) wet-etching said composite structure using an etchant containing hydrochloric acid and acetic acid, to produce an etched structure, wherein said etchant has a composition tailored such that, in said step c), an etching rate of said stepped structure is greater than an etching rate of said second III-V compound semiconductor layer of said composite structure; and d) second wet-etching said etched structure using a second etchant containing hydrochloric acid and acetic acid to obtain a planarized structure, said second etchant having a composition tailored such that an etching rate of said stepped structure is smaller than an etching rate of said second III-V compound semiconductor layer, of said etched structure, wherein the relationship between an etching time T where V V V V