Patent ID: 6911695
Filing Date: 2005-06-28
Classification: H01L

Abstract:
1. A transistor comprising: a gate; an insulator; a channel beneath the gate and separated from the gate by the insulator; a source adjacent to the channel on a first side of the gate; a drain adjacent to the channel on a second side of the gate; extension regions into the channel from the source and the drain that underlap the gate; insulating spacers abutting sidewalls of the gate that overlap the extension regions, wherein amounts of underlap between the extension regions and the gate are based at least in part on a thickness of the insulating spacers, and wherein the thickness of the insulating spacers is from 10-200 Angstroms; liners abutting the insulating spacers, wherein a thickness of the liners is from 10-300 Angstroms; and source/drain spacers abutting the liners, wherein a thickness of the source/drain spacers is from 500-3000 Angstroms, and wherein a material of the liners is more adhesive to a material of the insulating spacers than a material of the source/drain spacers.