Patent ID: 6391716
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for forming a non-volatile memory, said method comprising:providing a substrate; forming a gate oxide layer on said substrate; depositing a first polysilicon layer on said gate oxide layer; removing a portion of said first polysilicon layer to form polysilicon holes, no border of said polysilicon holes being vertical and parallel to the border of an active region from top view; depositing a first dielectric layer on said first polysilicon layer; depositing a second polysilicon layer on said first dielectric layer; performing photolithography and etching processes to form a stacking gate electrode which comprising a first gate electrode having corners and a second gate electrode, wherein a first gate electrode is formed by said first polysilicon layer, and a second gate electrode is formed by said second polysilicon layer; forming a source/drain region in said substrate; depositing conformally a second dielectric layer over said substrate; depositing conformally a third polysilicon layer on said second dielectric layer; blanket etching said third polysilicon layer to form a polysilicon spacer by using said second dielectric layer as a stop layer; and blanket etching said second dielectric layer by using said polysilicon spacer as a mask, whereby each said corner has an acute angle such that electrons stored in said first gate electrode can be emitted easily into said polysilicon spacer.