Patent ID: 9196727
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A semiconductor transistor comprising: a gate having a gate dielectric extending over a defined area, the gate having an effective gate length; an epitaxial layer positioned on a semiconductor substrate below the defined area of the gate, the epitaxial layer containing a substantially undoped channel positioned below the gate dielectric and extending between a source and a drain, the substantially undoped channel having a preselected thickness; and a screen layer formed at least in part in the semiconductor substrate with a depth of the screen layer set a preselected distance below the defined area of the gate such that the distance is a fraction of the effective gate length of the transistor and varying no more than one nanometer in uniformity across the substantially undoped channel, the screen layer having a defined thickness preselected such that the bottom of the screen layer is above the bottom of the source and drain and wherein the screen layer extends laterally to and contacts both the source and the drain.