Patent ID: 8760960
Filing Date: 2014-06-24
Classification: G11C

Abstract:
1. A semiconductor memory apparatus comprising: a shared column decoding unit configured to simultaneously enable a column selection line of first and second memory banks in response to a column address signal and a main strobe signal; an input/output switching unit configured to selectively electrically connect the first and second memory banks to a shared local input/output line in response to a bank selection signal; a shared input/output driving unit configured to amplify data transferred via the shared local input/output line and transfer the amplified data onto a global input/output line in a data read operation, and to amplify data transferred via the global input/output line and transfer the amplified data onto the shared local input/output line in a data write operation, in response to the main strobe signal; and a control unit configured to generate the bank selection signal and the main strobe signal in response to a read/write command and a bank address signal.