Patent ID: 6326271
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A process for the manufacturing of a MOS technology power device, comprising the steps of:forming a semiconductor layer of a first conductivity type over a semiconductor substrate;forming an insulated gate layer over the semiconductor layer;forming a plurality of substantially rectilinear elongated openings parallel to each other in said insulated gate layer;forming a respective plurality of elongated body stripes of a second conductivity type in said semiconductor layer under said elongated openings;forming source regions of the first conductivity type inside said body stripes, and covering the insulated gate layer with a metal layer which contacts the body stripes and the source regions through said elongated openings, wherein said body stripes are formed in such a way as to comprise first portions substantially aligned with a first edge of the respective elongated openings and extending under a second edge of said elongated opening to form a channel region, each first portion including a source region extending substantially from a longitudinal axis of symmetry of said respective elongated opening to said second edge of the elongated opening, and second portions, longitudinally intercalated with said first portions, substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from said longitudinal axis of symmetry to said first edge of the elongated opening, said first portions and second portions of the body stripes being respectively aligned in a direction transversal to said longitudinal axis.