Patent ID: 6324104
Filing Date: 2001-11-27
Classification: G06F,G11C

Abstract:
A semiconductor integrated circuit device having a main storage portion, and an auxiliary storage portion functioning as a cache memory, constructed such that two way data transfer is possible between said main storage portion and said auxiliary storage portion, said auxiliary storage portion comprising:a normal memory cell array with memory cells which are alternatively selected based on a selection signal, arranged in matrix form, anda redundant memory cell array provided so as to be adjacent to said memory cell array with the positions of rows matching, and with redundant memory cells which are alternatively selected based on a redundant selection signal, arranged in matrix form, whereina plurality of auxiliary data lines, to which memory cell groups of each row are connected, are separately provided for said normal memory cell array and for said redundant memory cell array,wherein said semiconductor integrated circuit device comprises:a data line connecting said main storage portion to said auxiliary storage portion,a plurality of redundant auxiliary data lines provided along rows of said redundant memory cell array, to which redundant memory cell groups belonging to each row of said redundant memory cell array are connected, anda plurality of redundant switch circuits respectively provided in said plurality of redundant auxiliary data lines, and alternatively conducting controlled based on a predetermined redundant address signal.