Patent ID: 7830714
Filing Date: 2010-11-09
Classification: G11C

Abstract:
1. A non-volatile memory system comprising: a set of bit lines; a set of non-volatile memory cells, each coupled to a common source and each including: a word line coupled to the gate of each access transistor in the set of non-volatile memory cells; a control gate line coupled to the control gate of each non-volatile memory transistor in the set of non-volatile memory cells; a source select line coupled to the gate of each source select transistor in the set of non-volatile memory cells; and means for performing a two-phase write operation to the set of non-volatile memory cells, wherein the two-phase write operation includes an erase phase and a program phase, wherein the means for performing the two-phase write operation comprise means for applying a first bit line voltage to a first subset of the set of bit lines during both the erase phase and the program phase, and means for applying a second bit line voltage, different than the first bit line voltage, to a second subset of the set of bit lines during both the erase phase and the program phase.