Patent ID: 6516420
Filing Date: 2003-02-04
Classification: G06F,H04L

Abstract:
A data synchronizer in a first system having a first clock which interfaces with a second system having a second clock which differs in frequency from the first clock, comprising:a plurality of parallel information registers, each of the plurality of information registers storing received information from the second system and having a valid bit associated therewith; a plurality of validity indicator registers, each of the plurality of validity indicator registers being coupled to a predetermined one of the valid bits and being set in response to the predetermined one of the valid bits being set; interface logic coupled to the plurality of validity indicator registers, the interface logic detecting when any of the valid data registers have been set and causing an acknowledge signal to be generated and sent to respective parallel information registers in response, the interface logic also providing a control signal; and an output multiplexor coupled to each of the plurality of parallel information registers for selectively providing the information synchronous to the first clock in response to the control signal.