Patent ID: 8599634
Filing Date: 2013-12-03
Classification: G11C

Abstract:
1. A circuit comprising: a first set of signal lines configured to be operatively coupled to a plurality of memory devices arranged into one or more logical ranks, each logical rank corresponding to a set of at least two physical ranks; a second set of signal lines configured to be operatively coupled to a memory controller of a computer system to receive, for a logical rank of the one or more logical ranks, a logical rank refresh command generated by the memory controller, wherein the circuit is configured to initiate, in response to the logical rank refresh command, a first refresh operation for one or more first physical ranks of the set of at least two physical ranks and a second refresh operation for one or more second physical ranks of the set of at least two physical ranks, wherein the second refresh operation is initiated after the first refresh operation; and wherein the circuit is further configured to cause a refresh time (tRFC) value to be stored in a memory location accessible by the memory controller, the tRFC value being based at least in part on a calculated maximum amount of time for refreshing the logical rank.