Patent ID: 6466580
Filing Date: 2002-10-15
Classification: H04L

Abstract:
A multiport data communication system for switching data packets between ports, the data communication system comprising:a plurality of receive ports for receiving data packets; a plurality of transmit ports for transmitting data packets; circuitry deciding whether each received data packet is one of high priority and low priority; a common memory for storing each received data packet, the common memory including an overflow area; circuitry providing a memory location designator for each data packet indicating where the corresponding data packet is stored in the common memory; a plurality of queuing devices corresponding to the plurality of transmit ports, each queuing device having a high priority queue queuing memory location designators corresponding to data packets of high priority to be transmitted by the respective transmit port and a low priority queue queuing memory location designators corresponding to data packets of low priority to be transmitted by the respective transmit port, and each high priority queue and low priority queue including a write side and a read side configured to hold a predetermined number of memory location designators; and transferring circuitry transferring the data packets from the common memory to a respective transmit port, the transferring circuitry including a common transmit queue for each transmit port and all data packets of high priority for a respective transmit port being transferred from the common memory and placed in the corresponding transmit queue prior to transferring any data packet of low priority for the respective transmit port, each data packet in each corresponding transmit queue being read from said each corresponding transmit queue without regard as to the priority of said each data packet, wherein when a number of memory location designators held in a respective read side is less than the predetermined number, memory location designators are passed from the corresponding write side to said respective read side of each high priority queue and each low priority queue of each queuing device, and when the number of memory location designators held in said respective read side of either the high priority queue and the low priority queue of said each of the queuing devices is equal to the predetermined number, memory location designators are passed from the corresponding write side to the overflow area of the common memory and then passed from the respective overflow area of the memory to the respective read side of the corresponding queuing device when the number of memory location designators held in the respective read side becomes less than the predetermined number.