Patent ID: 7237089
Filing Date: 2007-06-26
Classification: G06F

Abstract:
1. An operation method for having an operation apparatus execute (a) an existing operation that applies a predetermined type of operation to one N*M-bit first-bit-length operand, to obtain one N*M-bit first-bit length operation result, and (b) an SIMD (Single Instruction Multiple Data) operation used for applying N parallel operations that applies the predetermined type of operation in parallel to N M-bit second-bit-length operands to obtain N M-bit second-bit-length operation results, N being an integer equal to or greater than 2 and M being an integer equal to or greater than 1, the operation apparatus implementing: an operation instruction for instructing application of the predetermined type of operation on one of (c) the first-bit-length operand, and (d) the plurality of second-bit-length operands concatenated and considered to be a first-bit-length operand; and an SIMD correction instruction for instructing correction of an operation result of the operation instruction to an operation result of the SIMD operation, the operation apparatus comprising: a storage unit storing the first-bit-length operation result, and correction information that is used in the correction: the operation method comprising: a decoding step of decoding the operation instruction and the SIMD correction instruction used for applying N parallel operations; and an execution step of, (e) when the operation instruction is decoded, applying the predetermined type of operation to one of (i) the first-bit-length operand, and (ii) the N second-bit length operands concatenated and considered to be a first-bit-length operand, to obtain one first-bit-length operation result, storing the obtained first-bit-length operation result in the storage unit, and generating correction information based on an effect had, by applying the predetermined type of operation, on each M bits of the first-bit-length operation result from a bit that neighbors the M bits, and storing the generated correction information in the storage unit, and (f) when the SIMD correction instruction used for applying N parallel operations is decoded, correcting the stored first-bit-length operation result in M-bit units using the stored correction information, to obtain the N second-bit-length operation results, wherein when executing the existing instruction, the operation instruction is decoded and an obtained first-bit-length operation result is considered to be an operation result of the existing operation, and when executing the SIMD operation, the operation instruction is decoded, an obtained first-bit-length operation result is considered to be a provisional operation result, the SIMD operation is then decoded, and N second-bit-length operation results obtained by correcting the provisional operation result are considered to be an operation result of the SIMD operation.