Patent ID: 8847873
Filing Date: 2014-09-30
Classification: G02F,G09G

Abstract:
1. A gate line driving module for a liquid crystal display, the gate line driving module comprising: a plurality of odd-pixel gate line driving circuits; a plurality of even-pixel gate line driving circuits; and an auxiliary gate line driving circuit; wherein a signal input source is coupled to a signal input end of a first-stage odd-pixel gate line driving circuit of the odd-pixel gate line driving circuits or a signal input end of a first-stage even-pixel gate line driving circuit of the even-pixel gate line driving circuits, and the signal input source is also coupled to a signal feedback end of the auxiliary gate line driving circuit; wherein a first clock signal source is coupled to a first clock signal input end of each of the odd-pixel gate line driving circuits, a first clock signal input end of each of the even-pixel gate line driving circuits, and a first clock signal input end of the auxiliary gate line driving circuit, and a second clock signal source is coupled to a second clock signal input end of each of the odd-pixel gate line driving circuits, a second clock signal input end of each of the even-pixel gate line driving circuits, and a second clock signal input end of the auxiliary gate line driving circuit, the first clock signal source and the second clock signal source are inverted from each other, and the first clock signal source and the second clock signal source serve as a high level gate power source of the odd-pixel gate line driving circuits, the even-pixel gate line driving circuits, or the auxiliary gate line driving circuit; wherein transistors of the odd-pixel gate line driving circuits, the even-pixel gate line driving circuits, and the auxiliary gate line driving circuit are N-type thin film transistors; wherein the gate line driving module is fabricated with a liquid crystal panel of the liquid crystal display in an identical amorphous silicon process, and wherein each of the odd-pixel gate line driving circuits comprises: a 1 wherein a low level gate power source is coupled to the low level gate power source input end of each of the odd-pixel gate line driving circuits, a low level gate power source input end of each of the even-pixel gate line driving circuits, and a low level gate power source input end of the auxiliary gate line driving circuit; wherein the signal output end of each of the odd-pixel gate line driving circuits is coupled to a signal input end of the even-pixel gate line driving circuit of a next stage of the odd-pixel gate line driving circuit or a signal input end of the auxiliary gate line driving circuit, and a signal output end of each of the even-pixel gate line driving circuits is coupled to a signal input end of the odd-pixel gate line driving circuit of a next stage of the even-pixel gate line driving circuit or the signal input end of the auxiliary gate line driving circuit; wherein the signal output end of each of the odd-pixel gate line driving circuits is coupled to a signal feedback end of the even-pixel gate line driving circuit of a previous stage of the odd-pixel gate line driving circuit, and the signal output end of each of the even-pixel gate line driving circuits is coupled to a signal feedback end of the odd-pixel gate line driving circuit of a previous stage of the even-pixel gate line driving circuit; wherein each of the odd-pixel gate line driving circuits further comprises: a 3 a 4 a 5 a 6 a 7 an 8 a capacitor, wherein a first end of the capacitor is coupled to the gate of the 8 wherein a gate of the 1 wherein a drain of the 2 wherein a width to length (W/L) ratio of the 6