Patent ID: 6633060
Filing Date: 2003-10-14
Classification: H01L

Abstract:
A contact structure for a ferroelectric memory device integrated in a semiconductor substrate and including an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor; said MOS device having first and second conduction terminals and being covered with an insulating layer; and said ferroelectric capacitor having a lower plate formed on said insulating layer above said first conduction terminal and coupled to said first conduction terminal, and said lower plate being covered with a layer of a ferroelectric material and coupled capacitively to an upper plate, the contact structure comprising:a first plurality of plugs filled with a non-conductive material coupled to said first conduction terminals and said ferroelectric capacitor; and a second plurality of plugs filled with a conductive material and coupled to said second conduction terminal or said control circuitry.