Patent ID: 9054082
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor chip including a first main surface and a second main surface, which is opposite to the first main surface, wherein electrode pads are formed on the first main surface; a core substrate embedding at least the second main surface of the semiconductor chip, wherein the core substrate includes a first surface and a second surface respectively corresponding to the first main surface and the second main surface of the semiconductor chip, and a hole wall surface that defines a first through hole extending through the core substrate in a thickness direction; a first insulating layer that covers the hole wall surface of the first through hole, wherein the first insulating layer in the first through hole includes a hole wall surface that defines a second through hole extending through the core substrate in the thickness direction; a second insulating layer that covers the first surface of the core substrate; a third insulating layer that covers the second surface of the core substrate; a first wiring layer stacked on the second insulating layer and electrically connected to the electrodes pads; a second wiring layer stacked on the third insulating layer; and a through via that covers the hole wall surface of the second through hole, extends in the thickness direction traversing the first insulating layer, the second insulating layer, and the third insulating layer, and electrically connects the first wiring layer and the second wiring layer, wherein adhesiveness of the first to third insulating layers to a metal of the through via is higher than adhesiveness of the core substrate to the metal.