Patent ID: 6041388
Filing Date: 2000-03-21
Classification: G11C

Abstract:
A circuit for controlling a memory depth, comprising:a memory array having (i) a fixed physical depth and (ii) a variable array depth selected from at least two members of the group consisting of xN bits, x(N+1) bits, 2x(N+1) bits, and (2x)N bits, where x and N are integers; andcontrol logic configured to (a) control read and/or write operations in said memory array and (b) recognize a first one of said array depths in response to one or more read and/or write control signal(s) and a first address comprising m bits, and a second one of said array depths in response to said one or more read and/or write control signal(s) and a second address comprising (m+1) bits, wherein (m+1)<2N and m is an integer.