Patent ID: 6014756
Filing Date: 2000-01-11
Classification: G06F

Abstract:
A high availability shared cache in a multiprocessor system having at least two processing units, for storing information as congruence classes to be utilized by the processing units, wherein the multiprocessor system comprises:cache means associated with each of said processing units for storing information to be utilized by the processing units;main memory means for storing information to be utilized by the processing units, which are managed by arbitration means;bus means for transferring information between the processing units, the shared cache, and the main memory means;shared cache directory means for managing the shared cache, comprising entries of all the information stored in the shared cache, a Valid bit for the status of the information stored in the shared cache, and a Parity bit for indicating errors in the shared cache; anderror status register means for recording error events, which are provided by the shared cache;wherein a request for information is transmitted to the shared cache and the main memory means, in parallel, and in case of the error status register means recording an error in any entry of a congruence class in the shared cache directory means, self-recovery of the shared cache is accomplished by invalidating all the entries in the shared cache directory means of the accessed congruence class by resetting the Valid bits to ""0"" and by setting the Parity bit to a correct value; and the request for information to the main memory means is not cancelled.