Patent ID: 6461923
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises the sequential steps of:(a) providing a semiconductor substrate of a first conductivity type and having a surface; (b) forming a thin gate insulator layer in contact with said substrate surface; (c) forming a gate electrode on a portion of said gate insulator layer, said gate electrode comprising first and second opposing side surfaces and a top surface; (d) forming a blanket layer of an insulative material on exposed portions of said gate insulator layer on said substrate surface and on said first and second opposing side surfaces and said top surface of said gate electrode; (e) selectively removing, by anisotropically etching for a preselected interval, a major amount of the thickness of said blanket layer of insulative material from said substrate surface portions and from said top surface of said gate electrode, thereby (1) forming a tapered width insulative sidewall spacer on each of said first and second opposing side surfaces of said gate electrode and (2) leaving a residual thickness of said blanket layer of insulative material on portions of said substrate surface adjacent said sidewall spacers and on said top surface of said gate electrode; (f) introducing dopant impurities of a second, opposite conductivity type into said residual thickness portions of said layer of insulative material on said portions of said substrate surface adjacent said sidewall spacers to thereby form a pair of spaced-apart, shallow depth, source/drain regions in said substrate, each of said pair of source and drain regions extending to just beneath a respective proximal edge of said gate electrode; and (g) removing said residual thickness portions of said layer of insulative material to expose substantially undamaged portions of said substrate surface adjacent said sidewall spacers and to expose said top surface of said gate electrode.