Patent ID: 6352868
Filing Date: 2002-03-05
Classification: G01R

Abstract:
An apparatus for wafer level burn-in of a memory array having a plurality of memory cells, a plurality of word lines connected to an X-decoder, and a plurality of bit lines connected to a Y-decoder through a plurality of sense amplifiers, said apparatus comprising:an X-counter connected to said X-decoder; a Y-counter connected to said Y-decoder; a row address strobe connected to said X-decoder; a column address strobe connected to said Y-decoder; a number of input address pads connected to said row address strobe and said column address strobe; a word line burn-in control circuit connected to said X-decoder for turning on all word lines in said memory array simultaneously in a burn-in mode; a bit line burn-in control circuit connected to said Y-decoder for setting all bit lines in said memory array simultaneously in a burn-in mode; an input buffer connected to said Y-decoder; an output buffer connected to said Y-decoder; an input/output interface connected to said input and output buffers; and a main burn-in control circuit for controlling said word line burn-in control circuit, said bit line burn-in control circuit, said X-counter, and said Y-counter.