Patent ID: 6716710
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, said method comprising:receiving a substrate comprising a stacked gate and a shallow trench adjacent to said stacked gate, said substrate further comprising a first layer comprising a first material disposed over said stacked gate and said shallow trench and a second layer comprising a second material disposed over said first layer, wherein said first layer has a substantially uniform first thickness along a sidewall of said stacked gate, wherein said first material comprises TEOS (tetraethylorthosilicate) and wherein said first thickness is between approximately 300 and 500 Angstroms; and etching said second layer, said second layer reduced to a second thickness, said first thickness unchanged by said etching, said first layer and said second layer in combination forming a spacer along said sidewall of said stacked gate, said spacer having a thickness corresponding to said first thickness and said second thickness; wherein said spacer is formed using a single etch.