Patent ID: 9213665
Filing Date: 2015-12-15
Classification: G06F

Abstract:
1. A method of operating a data processing system including a processor, a split-transaction system interconnect that utilizes a split-transaction protocol for transferring operands, and a memory device, wherein the processor and the memory device are operably coupled to the split-transaction system interconnect, the method comprising: performing by a memory device, a first memory operation in response to a first split-transaction on the split-transaction system interconnect from the processor, the first split-transaction including an address phase using an address bus and a data phase using a data bus of the split-transaction system; performing by the memory device a second memory operation in response to an address-only transaction on the split-transaction system interconnect from the processor, wherein the address-only transaction on the split-transaction system interconnect has a decoration value indicated by a notify instruction comprising a read-modify-write operation and the memory device detects the decoration value and performs the read-modify-write operation using an address phase using the address bus and no subsequent data phase on the split-transaction system interconnect and thereby does not use the data bus; and performing by the memory device a third memory operation in response to a second split-transaction on the split-transaction system interconnect from the processor which uses the data bus and the address bus; wherein the performing the second memory operation by the memory device includes performing the read-modify-write operation of a storage location of the memory device for the address-only transaction so that the third memory operation can use the data bus during a time the second memory operation would have used the data bus if the second memory operation had been a split-transaction with an address phase and a data phase.