Patent ID: 6417093
Filing Date: 2002-07-09
Classification: H01L

Abstract:
In a process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and said structure is then planarized to remove said first and second electrically conductive material from the upper surface of said dielectric layer, the improvements which comprise:a) before said planarizing step, forming over said second electrically conductive material a layer of a planarizable material, wherein the thickness of said layer of planarizable material above said second electrically conductive material in said trenches and/or vias is at least equal to the thickness of said barrier layer above said upper surface of said dielectric layer; and b) planarizing said structure to remove: i) said planarizable material; ii) said second electrically conductive material; and iii) said first electrically conductive material; above said upper surface of said dielectric layer; whereby said planarizable material above said second electrically conductive material in said trenches and/or vias protects said second electrically conductive material in said trenches and/or vias while said first electrically conductive material is being removed from said upper surface of said dielectric layer by said planarizing step to prevent erosion of the upper surface of said second electrically conductive layer in said trenches and/or vias.