Patent ID: 6297681
Filing Date: 2001-10-02
Classification: H03K

Abstract:
A digital delay generator device based on a series arrangement of cells, wherein each cell has a first input for receiving a single-phase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay, and an output for a so-delayed signal, each cell comprising a series of stack transistors, and wherein furthermore various cells comprise further transistor means for receiving a bypass control signal, said further transistor means being arranged for under control of a bypass control signal effectively bypassing one or more cells to thereby effect a quantized overall delay shortening,characterized in that such various cells form a contiguous pair in said string, wherein each cell of a said pair comprises only five transistors and only six nodes, and the transistor means effectively form respective transistor bypasses over clock-signal-controlled transistor in the associated series stack at mutually opposite sides of the respective stack.