Patent ID: 6809951
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A ferroelectric semiconductor memory comprising:a cell array in which a plurality of ferroelectric memory cells are arranged in a matrix format, each memory cell including a field-effect transistor and a capacitor formed as a gate electrode section of the field-effect transistor and having a stacked structure of metal film/ferroelectric film/metal film; a circuit section which selectively executes a read mode, program mode, and erase mode configured to perform data read, programming, and erase to the memory cells, and a rewrite mode configured to refresh data stored in each memory cell, by rewriting; said ferroelectric memory cells comprising a gate, a drain, and a source; said circuit section comprising, word lines disposed in one-to-one correspondence with rows of the matrix format of the memory cells, each word line being connected to gates of a plurality of memory cells in the same row, bit lines disposed in one-to-one correspondence with columns of the matrix format of the memory cells, each bit line being connected to drains of a plurality of memory cells in the same column, and source lines disposed in one-to-one correspondence with rows of the matrix format of the memory cells, each source line being connected to sources of a plurality of memory cells in the same row; the circuit section comprising a sense circuit connected to the bit lines; the sense circuit comprising a high-breakdown-voltage sense amplifier; and in the rewrite mode, the circuit section is configured to successively apply a program voltage and erase voltage to a word line corresponding to a selected memory cell and, in parallel with this voltage application, causes the high-breakdown-voltage sense amplifier to amplify a voltage read out to a bit line corresponding to the selected memory cell, and feeds the amplified voltage back to the corresponding bit line.