Patent ID: 8867294
Filing Date: 2014-10-21
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array configured to comprise a plurality of memory cells each respectively arranged at an intersection of one of a plurality of word lines and one of a plurality of bit lines; a register circuit configured to store state information related to at least one of the plurality of word lines; an first comparison circuit configured to determine if a relief originating address matches a refresh address; a first selector configured to select a first address between an array address and a relief destination array address in response to the determination of the first comparison circuit; a second comparison circuit configured to determine if the first address, selected by the first selector, is related to the at least one of the plurality of word lines; a second selector configured to select a second address between the relief destination address and the array address in response to the determination of the second comparison circuit; and a control circuit configured to perform a refresh operation on a memory cell, wherein the refresh operation determines an address of the memory cell by at least the second address.