Patent ID: 7747889
Filing Date: 2010-06-29
Classification: H04L

Abstract:
1. A system comprising: an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path; a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path; a system bus interconnected between the initiator device and the target device within the signaling path; and a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting an at least one clock cycle delay within the signaling path and (ii) not inserting the at least one clock cycle delay within the signaling path, wherein the dynamic timing bridge includes a bus input, a clock input, a control signal input, and an output, and further comprises a sequential logic block and a multiplexer, and wherein (a) the bus input is coupled to (i) an input of the sequential logic block and (ii) an input of the multiplexer, (b) the clock input is coupled to a clock input of the sequential logic block, (c) an output of the sequential logic block is coupled to another input of the multiplexer, (d) the control signal input is coupled to a select input of the multiplexer, and (e) an output of the multiplexer is coupled to the output of the dynamic timing bridge, wherein responsive to the control signal input, the multiplexer multiplexes one of the bus input or the sequential logic block output onto the dynamic timing bridge output.