Patent ID: 6391689
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method of forming a self-aligned thyristor, the method comprising:providing a semiconductor substrate comprising a doped well region, the doped well region being of a first conductivity type; forming a gate stacked structure on the doped well region, the gate stacked structure comprising an insulation layer formed on the semiconductor substrate, a conductive layer deposited on the insulation layer, and a passivation layer deposited on the conductive layer, the gate stacked structure dividing the doped well region into a first area and a second area; masking the second area, and performing a first ion implantation process of a second conductivity type to form a first doped area in the first area; masking the first area, and performing a second ion implantation process of a second conductivity type to form a second doped area in the second area, a doping concentration of the second doped area being higher than a doping concentration of the first doped area; forming a spacer on each wall of the gate stacked structure; forming a dielectric layer on the semiconductor substrate to cover the gate stacked structure, the spacers, the first doped area, and the second doped area; forming a via on the dielectric layer above the first doped area; forming an in-situ doped poly-silicon layer of the first conductivity type on the dielectric layer; and thermally driving in the first conductivity type dopant of the poly-silicon layer to form a third doped area in the first doped area, a doping concentration of the third doped area being higher than a doping concentration of the semiconductor substrate.