Patent ID: 8659084
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A complementary metal-oxide semiconductor (CMOS) device, comprising: a semiconductor-on-insulator (SOI) wafer comprising a SOI layer over a buried oxide (BOX); active areas formed in the SOI layer in which field-effect transistor (FET) devices are formed, the FET devices comprising an interfacial oxide on the SOI layer and gate stacks on the interfacial oxide layer, each of the gate stacks having (i) a conformal gate dielectric layer present on a bottom and sides of each of the gate stacks, wherein the conformal gate dielectric layer comprises a high-k dielectric material (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer, that is configured to act as a doping source to change a workfunction of the gate stacks, lining the conformal gate metal layer, wherein at least a first given one of the gate stacks which corresponds to at least a first given one of the FET devices has at least one first length and at least a second given one of the gate stacks which corresponds to at least a second given one of the FET devices has at least one second length, wherein one or more of an amount of the gate metal layer and an amount of the workfunction setting metal layer present in the gate stacks varies proportionally to a length of the gate stacks since the conformal gate dielectric layer which is present on the bottom and sides of each of the gate stacks provides, based on the length of the gate stacks, different size gaps for the gate metal layer and the workfunction setting metal layer to fill in, and wherein variations in the amount of the workfunction setting metal layer in the gate stacks alters a threshold voltage of the FET devices, and thus by having the gate stacks with the at least one first length and the at least one second length the amount of the workfunction setting metal layer is varied by having the different size gaps for the workfunction setting metal layer to fill in as a function of the length of the gate stacks so as to configure the at least a first given one of the FET devices to have a threshold voltage that is different from a threshold voltage of the at least a second given one of the FET devices.