Patent ID: 6969895
Filing Date: 2005-11-29
Classification: H01L

Abstract:
1. A method of forming an MRAM cell structure in which the overall topography is flat and in which the distance between a bit line and a magnetic free layer is well controlled, comprising: providing a substrate; forming a layered configuration on said substrate, the formation of said configuration further comprising patterning said layered configuration; forming a first layer of insulation covering at least all exposed surfaces of said patterned layered configuration, said layer of insulation extending laterally therefrom over said substrate; removing, by a method of CMP, an upper portion of said first layer of insulation, said CMP removing all of the insulation covering said sacrifical layer and an upper portion of said sacrificial layer and exposing, thereby, a remaining portion of said sacrificial layer having an upper surface which is substantially coplanar with an upper surface of the remaining portion of said insulating layer; removing, by a plasma or reactive ion etching process, the remaining portion of said sacrificial layer, exposing thereby an upper surface of said capping layer, said capping layer surface and said insulating layer surface forming a common surface having a flat topography; forming a bit line on said common surface, said bit line covering at least said capping layer and contacting said capping layer, the distance (vertical separation) between said bit line and said magnetic free layer being well controlled; and forming a second layer of insulation on said common surface, said second layer being laterally disposed about said bit line and the upper surface of said second layer and the supper surface of said bit line forming a substantially coplanar surface.