Patent ID: 7511584
Filing Date: 2009-03-31
Classification: H03K,H03L

Abstract:
1. A voltage controlled oscillator, comprising: a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN; a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP; a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor; a fourth NMOS transistor coupled between the output node OUTN and VSS, wherein the fourth NMOS transistor includes a base terminal configured to receive a voltage control signal VCTRL; a first capacitor connected between the fourth NMOS transistor and VSS; a first PMOS transistor having a base terminal connected to the output node OUTP and a drain terminal connected to the output node OUTN; and a second PMOS transistor having a base terminal connected to the output node OUTN and a drain terminal connected to the output node OUTP, wherein the output node OUTN and the output node OUTP are configured to output at least one oscillation signal.