Patent ID: 7380018
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A processing device comprising: one or more resources within a node; a plurality of peripheral bus interfaces coupled to the one or more resources and coupled to a peripheral bus fabric to support resource sharing with a plurality of other processing devices of other nodes when the other processing devices are coupled to the peripheral bus fabric; a node identification (ID) register including primary routing resources programmable with a plurality of addresses to determine a primary routing for a plurality of peripheral bus transactions among the plurality of peripheral bus interfaces based upon a destination address for each respective peripheral bus transaction, the plurality of peripheral bus transactions including transactions of different types, the different types of transactions including packet data transfer transactions, input/output transactions with input/output devices and cache coherency transactions to maintain cache coherency with other nodes; and the node ID register also including a node routing table containing one or more override indications to determine an alternate override routing for a particular peripheral bus transaction over the primary routing, in which the primary routing for the particular peripheral bus transaction is overridden by the alternate override routing when the destination address and a type of transaction for the particular peripheral bus transaction is identified by one or more override indications in the node routing table for alternate routing, wherein when the particular peripheral bus transaction is a cache coherency peripheral bus transaction, a first override routing indication is used to route the particular cache coherency peripheral bus transaction through a first alternate route instead of a primary route, and when the particular peripheral bus transaction is an input/output peripheral bus transaction, a second override routing indication is used to route the particular input/output peripheral bus transaction through a second alternate route instead of the primary route.