Patent ID: 6177719
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A fabricating process of a chip scale package of semiconductor comprising:providing a chip, having a first surface and a second surface wherein the first surface of the chip has a set-up of a gate and a first source/drain region while the second surface of the chip has a set-up of a second source/drain region;providing a first conductive plate, disposed on the first surface of the chip wherein the first conductive plate further comprises a substrate on which a first bump and a second bump are disposed on the same side to make the first bump and the gate as well as the second bump and the first source/drain region electrically couple respectively by using a conductive bond;providing a second conductive plate, disposed on the second surface of the chip and is electrically coupled with the second source/drain region by a conductive bond;filling an insulating material between the chip and the substrate as well as between the chip and the second conductive plate;removing the first conductive plate to expose a portion of the insulating material disposed on the area excluding that covered by the first bump and the second bump on the first surface; andperforming a scribing process to expose at least a side surface of the first bump, the second bump, the second conductive plate, and the chip to form the chip scale package.