Patent ID: 8102199
Filing Date: 2012-01-24
Classification: H03K

Abstract:
1. A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH), the voltage level shifting circuit comprising: a first and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to an output node of the voltage level shifting circuit, the output node producing an output signal (OUT) and a drain of the second PMOS transistor being connected to the output node, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor; a first NMOS transistor with a source connected to a ground (VSS), a drain coupled to the drain of the first PMOS transistor and a gate connected to an input node receiving an input signal (IN) swinging between the VCCL and the VSS; and a first pull-up device coupled between the VCCH and the drain of the first NMOS transistor, the first pull-up device being a PMOS transistor with its gate connected to an output terminal of a first NAND gate, wherein the first NAND gate has its first input receiving the output signal (OUT) and its second input receiving a complementary input signal (INB) such that the first pull-up device is turned off when the input signal is in static state or transitions from a logic LOW to a logic HIGH, and is turned on when the input signal transitions from the logic HIGH to the logic LOW.