Patent ID: 6215728
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A data storage device which stores plural bits of data, comprising:clock generating means for generating a reference clock signal having a predetermined reference cycle and at least one divided clock signal having a cycle which is (1/2).sup.n (n: natural number) times said reference cycle;decoding means for selecting one of periods, based on contents of data inputted thereto, said periods being obtained by dividing said reference cycle and in each of which a signal level of said divided clock signal is constant;storage means for generating a cyclic pulse having the same cycle as said reference cycle, and for starting to generate said cyclic pulse at a trigger timing, said trigger timing being a predetermined timing within the period selected by said decoding means; andoutput means for specifying output data based on a signal level of said reference clock signal and a signal level of said divided clock signal at the same phase timing as said trigger timing in terms of a cycle of said cyclic pulse.