Patent ID: 8062911
Filing Date: 2011-11-22
Classification: G01R

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) supplying a semiconductor wafer having a plurality of chip formation regions each having a semiconductor integrated circuit and a plurality of electrodes electrically coupled to the corresponding semiconductor integrated circuit; (b) supplying a wiring substrate, a thin film probe sheet connected to the wiring substrate and having a plurality of contact terminals which can be brought into contact with the plurality of electrodes of the semiconductor wafer, and a pressing mechanism constructed to bring the contact terminals of the thin film probe sheet into contact with the electrodes of the semiconductor wafer; and (c) carrying out, by the aid of the pressing mechanism, electrical testing of the semiconductor integrated circuit by bringing tips of the contact terminals of the thin film probe sheet into contact with the electrodes of the semiconductor wafer, wherein the thin film probe sheet has a plurality of first interconnects and an insulating film, which is formed over the contact terminals and has a plurality of through-holes therein, the plurality of first interconnects being formed over the insulating film and being electrically connected to the corresponding contact terminals via the through-holes, wherein each contact terminal includes a first metal film and a second metal film stacked over the first metal film, the first metal film having an inclined surface portion extending toward the contact terminal tip and a side surface portion extending from the inclined surface portion to a back surface portion of the insulating film, and the second metal film having a first portion surrounded by the inclined surface portion and the side surface portion of the first metal film and a second portion protruding into the insulating film such that an upper surface and a side surface of the second portion contact the insulating film, each through-hole in the insulating film being arranged over the corresponding second portion of the second metal film such that the corresponding first interconnect is directly contacted with said second portion via the respective through-hole, wherein the side surface portion of the first metal film has an upper surface in contact with the back surface portion of the insulating film, wherein the first portion of the second metal film has peripheral portions of an upper surface thereof in contact with the back surface portion of the insulating film, and wherein the electrical testing is carried out while maintaining a height between the semiconductor wafer and the back surface portion of the insulating film.