Patent ID: 7342964
Filing Date: 2008-03-11
Classification: H04N

Abstract:
1. An apparatus comprising: a first circuit configured to generate a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously; a second circuit configured to generate a plurality of sum values by adding said difference values; and a third circuit configured to generate (i) a mode signal identifying a best mode among at least four partition modes, (ii) a motion signal conveying at least one motion vector associated with said best mode and (iii) a score signal conveying a score value associated with said best mode all in response to said sum values, wherein said third circuit comprises (i) an adder circuit configured to generate a plurality of first intermediate values from said sum values, (ii) a storage circuit configured to generate a plurality of second intermediate values from said first intermediate values as said current block is moved through a search window, (iii) a select circuit configured to generate (a) said mode signal, (b) said motion signal and (c) said score signal all from said second intermediate values, and (iv) a first bias circuit configured to generate a cost value based on all of (a) a quantization parameter and (b) a motion vector magnitude and wherein said storage circuit is further configured to add said cost value to each of said first intermediate values.