Patent ID: 8013454
Filing Date: 2011-09-06
Classification: G02F,H01L,H05K

Abstract:
1. A wiring substrate, comprising: a substrate including a plurality of wirings extending substantially in parallel with each other and each including a terminal portion; an integrated circuit chip including a plurality of bump electrodes arranged to correspond to respective terminal portions so as to face the respective terminal portions; an anisotropic electrically conductive layer located between the substrate and the integrated circuit chip and made of an insulating resin including electrically conductive fine particles dispersed therein to electrically connect the terminal portions to the plurality of bump electrodes; and at least one insulating member arranged to isolate a first one of the plurality of bump electrodes and a facing first terminal portion from a second one of the plurality of bump electrodes and a facing second terminal portion that are adjacent to the first one of the plurality of bump electrodes and the facing first terminal portion; wherein adjacent ones of the terminal portions are offset relative to each other; and a portion of the at least one insulating member is arranged to overlap and cover an upper portion of only alternating ones of the plurality of wirings such that similarly positioned upper portions of directly adjacent ones of the plurality of wirings are not both overlapped and covered by the at least one insulating member.