Patent ID: 6240095
Filing Date: 2001-05-29
Classification: H04L

Abstract:
A buffer memory interface circuit communicating data between a network device and a host device, the buffer memory interface circuit comprising:an output buffer memory;a command buffer memory;a host interface circuit writing data received from the host device in a first transmission protocol to the output buffer memory;a microprocessor controlling the host interface circuit and writing transmission instructions to the command buffer memory related to the data; anda network interface circuit reading the transmission instructions from the command buffer memory and in response to those transmission instructions reading the data from the output buffer memory and transmitting the data to the network device according to a network transmission protocol;wherein the transmission instructions are selected from the group consisting of word count of the data, whether a connection according to the network transmission protocol with the network device should be maintained after conclusion of the transmission of the data; whether an address of a destination of the data at the network device should be maintained after the conclusion of the transmission of the data, the address of the data at the network device, and a flag indicating whether the transmission instructions have been executed by the network interface circuit.