Patent ID: 8022457
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: an active region including a first side surface having a predetermined depth from a first surface of a semiconductor substrate, the active region being defined by a device isolation layer and having predetermined width and length; a first impurity implantation region formed in upper portions of the active region; a second impurity implantation region formed at a bottom of the active region so that the first impurity implantation region is over the second impurity implantation region; a first channel region formed between the first impurity implantation region and the second impurity implantation region along the first side surface of the active region; a first gate insulating layer formed on the first channel region along the first side surface; a first gate electrode vertically formed on the first gate insulating layer, the first gate electrode being formed directly connected to and over the device isolation layer along the first side surface; a first word line connected to an upper portion of the first gate electrode and horizontally extending in a first direction on the first surface of the semiconductor substrate; a first contact plug formed to contact the second impurity implantation region while vertically passing a portion of the active region; a bit line connected to the first contact plug, extending across the active region and horizontally extending in a second direction; a second contact plug vertically extending while contacting an upper surface of the first impurity implantation region; a second side surface of the active region facing a first side surface of an adjacent active region separated from the active region by the device isolation layer and having a predetermined depth from the first surface of the semiconductor substrate; a third impurity implantation region spaced apart by a predetermined gap from the first impurity implantation region formed in upper portions of the active region; and a second channel region formed between the third impurity implantation region and the second impurity implantation region along the second side surface of the active region.