Patent ID: 7755176
Filing Date: 2010-07-13
Classification: H01L

Abstract:
1. A substrate for mounting a semiconductor die, comprising: a substantially planar insulating layer comprising a side edge; a conductive metal pattern formed on a top side of the insulating layer including signal traces terminating in bond fingers outside of a die mounting area, the bond fingers having a width greater than a width of the signal traces, wherein at least some of the signal traces extend within the die mounting area, and further including a plurality of electrically isolated dummy traces disposed between the signal traces in otherwise empty regions defined by at least some of the signal traces within the die mounting area, thereby filling the otherwise empty regions with a fill pattern that improves planarity of an upper surface of the die mounting area, wherein the dummy traces have substantially the same width as the signal traces and extend from within the die mounting area to the side edge of the insulating layer; and a solder mask coating disposed over the insulating layer and the conductive metal pattern exclusive of the bond fingers, whereby the dummy traces and signal traces provide corresponding variations in an upper surface of the solder mask coating such that a plurality of channels are formed in the solder mask coating, the plurality of channels extending from within the die mounting area to the side edge of the insulating layer, the plurality of channels allowing for the escape of air toward the side edge of the insulating layer during attachment of the semiconductor die.