Patent ID: 8004092
Filing Date: 2011-08-23
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; a MOS device in or on said silicon substrate; a first metal layer over said silicon substrate; a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a passivation layer over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer; a first metal interconnect having a first contact point at a bottom of a first opening in said passivation layer, wherein said first opening is over said first contact point; a second metal interconnect having a second contact point at a bottom of a second opening in said passivation layer, wherein said second opening is over said second contact point; a third metal interconnect having a third contact point at a bottom of a third opening in said passivation layer, wherein said third opening is over said third contact point, wherein said first, second and third metal interconnects comprise electroplated copper, wherein said first, second and third contact points are aligned in a first line, wherein said second contact point is between said first and third contact points; a patterned metal layer on said first, second and third contact points and over said passivation layer, wherein said patterned metal layer comprises a first copper layer having a thickness between 1 and 10 micrometers, wherein said patterned metal layer comprises a metal trace over said passivation layer, and a fourth contact point connected to said second contact point through said metal trace, wherein said fourth contact point is not vertically over said second contact point; a first metal bump on said patterned metal layer and vertically over said first contact point; a second metal bump on said fourth contact point; and a third metal bump on said patterned metal layer and vertically over said third contact point, wherein said first and third metal bumps are aligned in a second line substantially parallel with said first line, wherein said third metal bump comprises a second copper layer directly on said first copper layer, wherein said third metal bump is configured to be connected to a contact pad on a flexible substrate.