Patent ID: 7373454
Filing Date: 2008-05-13
Classification: G11C,H03M,H04J

Abstract:
1. A method comprising: receiving a serial stream of data bits; deserializing the serial stream of data bits into parallel bits; inputting the parallel bits into a content addressable memory and a first register during a single clock cycle; inputting an output of the first register into a second register; inputting outputs of the first and second registers to the content addressable memory, wherein the parallel bits, output of the first register, and output of the second register are combined and stored as a first parallel word in a first row of the content addressable memory; providing a bus configured to receive the parallel bits and output of the first register, wherein the data lines forming the bus are grouped into a plurality of overlapping subsets of the bus that each contain at least one common data line; providing the parallel bits and the output of the first register in a plurality of parallel bit outputs onto the bus; providing a set of parallel words stored in the content addressable memory, wherein at least one of the set of parallel words includes a fixed frame alignment detection pattern having a data position; simultaneously comparing the first parallel word to the set of parallel words stored in the content addressable memory to detect a frame alignment pattern in the first parallel word; and when the frame alignment pattern is detected in the first parallel word, selecting one of the subsets and associated parallel bit outputs based on match flag outputs from the content addressable memory, wherein each of the match flag outputs are associated with a respective one of the set of parallel words that includes the matching frame alignment pattern and the matching data position with respect to the frame alignment pattern of the first parallel word.