Patent ID: 6157376
Filing Date: 2000-12-05
Classification: G09G,H03L

Abstract:
A method of generating a target clock signal having a frequency of (X/Y) times the frequency of a reference clock signal, said method comprising the steps of:(a) selecting the desired approximate duration of a comparison cycle period;(b) determining a divisors set of {E11, E12, E13, . . . , E1m} and a weight elements set of {W11, W12, . . . , W1m} for X, whereinX/L=((E1i*W1i)/(W1i)), for i=1 to m,wherein `*` represents multiplication, wherein L is a number determining said desired duration of comparison period, and wherein i, L and m are integers;(c) determining a divisors set of {E21, E22, E23, . . . , E1n} and a weight elements set of {W21, W22, . . . , W2n}, whereinY/L=((E2j*W2j)/(W2j)), for j=1 to n,wherein at least one of said divisor sets contains a plurality of divisors, wherein j and n are integers, and * represents multiplication operation;(d) dividing said reference clock signal at a present comparison cycle by each of said divisor elements E2j, wherein each of said divisor elements E2j is used proportionate to the associated weight W2j;(e) dividing said target clock signal at said present comparison cycle by each of said divisor elements E1i, wherein each of said divisor elements E1i is used proportionate to the associated weigh E1i; and(f) generating a phase difference of said divided clock signals generated in (d) and (e), and adjusting the phase of said target clock signal by using said phase difference,wherein said target clock signal for a future comparison cycle is generated by the adjusting performed using said phase difference in step (f), andwherein said target clock signal is generated by iteratively performing steps (d), (e) and (f), wherein said target clock signal of a future comparison cycle generated in one iteration is used as said target clock signal for a present comparison cycle for a subsequent iteration.