Patent ID: 8698296
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a wiring substrate including an upper surface, a lower surface opposite the upper surface, a plurality of bonding leads formed over the upper surface, and a plurality of lands formed over the lower surface; a semiconductor chip including a main surface, a back surface opposite the main surface, and a plurality of pads formed over the main surface, the semiconductor chip being mounted over the wiring substrate such that the main surface of the semiconductor chip faces the upper surface of the wiring substrate, a plan view shape of the main surface of the semiconductor chip being quadrangular; a plurality of protruding electrodes respectively arranged between the pads of the semiconductor chip and the bonding leads of the wiring substrate; and a plurality of solder portions respectively arranged between the protruding electrodes and the bonding leads of the wiring substrate, wherein the plurality of pads is disposed at a peripheral portion of the main surface in the plan view, and is arranged along a side of the main surface of the semiconductor chip, wherein the plurality of pads includes a first pad and a second pad arranged next to the first pad in a first direction substantially parallel to the side of the semiconductor chip in the plan view, wherein the first and second pads are arranged such that the first pad is configured to pass a unique electric current therethrough, and the second pad is configured to not pass the unique electric current therethrough, wherein a first protruding electrode of the protruding electrodes is located between the first pad and a first bonding lead of the bonding leads, wherein a second protruding electrode of the protruding electrodes is located between the second pad and a second bonding lead of the bonding leads, wherein the plurality of pads is arranged in two rows including an outer row and an inner row, wherein the first pad is electrically connected to a circuit section formed in the semiconductor chip via a wiring, wherein a third pad of the plurality of pads is included in the inner row and is arranged next to the first pad in a second direction perpendicular to the first direction, and wherein the third pad is comprised of a part of the wiring.