Patent ID: 6690057
Filing Date: 2004-02-10
Classification: H01L

Abstract:
An EPROM structure for a nonvolatile semiconductor memory, with a plurality of memory cells each memory cell comprising:a substrate; an access transistor formed in said substrate; a floating gate transistor formed in said substrate adjacent to said access transistor, wherein said floating gate transistor has a floating gate and can be programmed by hot electrons and erased by UV light; a first dielectric layer disposed over said access transistor and said floating gate transistor; and a common gate disposed over said portion of said dielectric layer disposed over said floating gate transistor so as to be located above at least the floating gate of said floating gate transistor to form a common gate capacitance, wherein each of said common gates of said memory cells are connected to a common programming conductor, wherein said common gate is structured and arranged over said portion of said dielectric layer over said floating gate transistor to provide said common gate capacitance so the potential at said floating gate transistor required for writing to each memory cell is substantially greater than the potential to read and erase the memory cell, and said common gate pulls hot electrons created on a drain side of said floating gate when a positive voltage potential is applied to said common gate.