Patent ID: 6987406
Filing Date: 2006-01-17
Classification: H03K,H03L

Abstract:
1. A phase-locked loop circuit, comprising: a phase-frequency detector circuit that is arranged to provide a phase-frequency detection output signal in response to an input clock signal and a feedback signal that is based, in part, on a multiplexer output signal; a phase detector circuit that is arranged to provide a phase detection output signal in response to the input signal and the feedback signal; a frequency comparator circuit that is arranged to provide a status signal such that the status signal corresponds to a first logic level if a frequency that is associated with the input clock signal and a frequency that is associated with the feedback signal are within a tolerance window, and such that the status signal corresponds to a second logic level if the frequency that is associated with the input clock signal and the frequency that is associated with the feedback signal are outside of the tolerance window; and a multiplexer circuit that is arranged to provide the multiplexer output signal such that the phase-frequency detection output signal is selected as the multiplexer output signal if the status signal corresponds to the first logic level, and such that the phase detection output signal is selected as the multiplexer output signal if the status signal corresponds to the second logic level.