Patent ID: 6393266
Filing Date: 2002-05-21
Classification: H03D

Abstract:
A circuit comprising:a first comparator having a first input and a second input and a first output node and a second output node, wherein said first comparator outputs a first value on said first output node and a second value on said second output node if a signal on said first input is greater than a signal on said second input and said first comparator outputs a second value on said first output node and a first value on said second output node if a signal on said first input is less than a signal said second input; a second comparator having a third input and a fourth input and a third output node and a fourth output node, wherein said second comparator outputs a first value on said third output node and a second value on said fourth output node if a signal on said third input is greater than a signal on said fourth input and said second comparator outputs a second value on said third output node and a first value on said fourth output node if a signal on said third input is less than a signal on said fourth input; and an arithmetic unit connected to said first, second, third, and fourth output nodes and having a fifth output, a sixth output, a seventh output and an eighth output, wherein said arithmetic unit combines signals at said first, second, third and fourth output nodes in the following fashion: the fifth output signal is derived from the first output node signal plus the third output node signal; the sixth output signal is derived from the first node output signal plus the fourth node output signal; the seventh output signal is derived from the second node output signal plus the third node output signal; and the eighth output signal is derived from the second node output signal plus the fourth node output signal.