Patent ID: 6130836
Filing Date: 2000-10-10
Classification: G06F,G11C,H01L,Y02D

Abstract:
A semiconductor integrated circuit device on a semiconductor substrate, comprising:a processing unit;an address bus coupled to said processing unit;a data bus coupled to said processing unit;an electrically erasable and programmable nonvolatile memory coupled to said address bus and to said data bus, the nonvolatile memory including memory blocks each operating as a simultaneously erasable unit of data stored therein, each memory block including memory cells each having a floating gate; anda control register having bits to provide for information designating a memory block to be erased;wherein said processing unit provides an address for selecting the control register and information to be set to the bits to said address bus and to said data bus, respectively, so that data stored in said memory block, which is designated by the information in the bits, is erased in an erasing operation.