Patent ID: 6484272
Filing Date: 2002-11-19
Classification: G06F

Abstract:
A method of closing a gate in a data processing system having a plurality of processors in a plurality of processor modules, said method comprising:(A) testing whether a processor in a subject processor module opened the gate by: 1) selecting a first processor in the subject processor module as a selected processor; 2) testing an address of the gate against the contents of a gate opened location in a memory associated with a selected processor in the subject processor module; and 3) repeating substep (2) as a loop while the address of the gate does not match the selected gate opened location and another processor in the subject processor module as the selected processor has not been tested in substep (2); (B) balking a specified period of time when the address of the gate matches the contents of the selected gate opened location; and (C) attempting to close the gate after balking in step (B).