Patent ID: 6681311
Filing Date: 2004-01-20
Classification: G06F

Abstract:
A translation lookaside buffer (TLB) for caching memory types, comprising:an input, for receiving a virtual address; a tag array, coupled to said input, for caching virtual addresses; a data array, coupled to said input, for caching physical addresses translated from corresponding ones of said virtual addresses cached in said tag array, and for caching a memory type associated with each of said physical addresses; an output, coupled to said data array, for providing said memory type associated with one of said physical addresses from said data array selected by said virtual address received on said input; and a flush input, coupled to said tag array, configured to receive a signal indicating that a memory type unit (MTU) has been updated, said MTU configured to provide said memory type cached in said data array, wherein said virtual addresses cached in said tag array are invalidated in response to said signal indicating said MTU has been updated.