Patent ID: 6338032
Filing Date: 2002-01-08
Classification: H03F

Abstract:
A system for trimming and simulating the effect of trimming integrated circuit (IC) parameters, comprising:an input circuit arranged to receive a digital bit pattern, a plurality of digital to analog converters (DACs), each of which produces a respective trim signal at an output in response to a digital bit pattern received at an input, said trim signals connected to affect respective parameters of electronic circuitry within an IC, said IC having a plurality of input/output (I/O) pins, and an interface circuit connected between said input circuit and said DACs arranged to receive a parameter select signal that selects one of said parameters to be trimmed and to apply the digital bit pattern received by said input circuit to said selected parameter's respective DAC upon receipt of a simulation bit, and to permanently apply said digital bit pattern to said DAC upon receipt of a trim bit, said input circuit, said DACs, and said interface circuit packaged together within said IC and operable via said IC's I/O pins, thereby enabling said parameters to be trimmed post-assembly.