Patent ID: 6636447
Filing Date: 2003-10-21
Classification: G11C

Abstract:
A memory module, comprising:a plurality of memory cells and a predetermined number of redundant memory cells for repairing defective memory cells; a first address circuit configured for activating a predeterminable number of memory cells via address lines in dependence on a predetermined address; a second address circuit connected to said redundant memory cells via second address lines; said second address circuit, upon receiving a defect address of at least one defective memory cell, activating redundant memory cells assigned to the defect address; and a selection circuit connected to said first address circuit and to said second address circuit, said selection circuit defining the predeterminable number of memory cells to be activated by said first address circuit in event of an address being supplied, and said selection circuit prescribing for said second address circuit how many redundant memory cells are to be activated under a defect address.