Patent ID: 7106625
Filing Date: 2006-09-12
Classification: G11C,H01L

Abstract:
1. An integrated circuit memory device, comprising: a semiconductor body; a plurality of gates arranged in series on the semiconductor body, the plurality of gates including a first gate in the series and a last gate in the series, with insulating members isolating gates in the series from adjacent gates in the series; a charge storage structure on the semiconductor body, the charge storage structure including charge trapping locations beneath more than one of the plurality of gates in the series; circuitry to conduct source and drain bias voltages to the semiconductor body near the first gate and near the last gate in the series; and circuitry to conduct gate bias voltages to the plurality of gates; wherein the semiconductor body includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, the multiple-gate channel region having one of n-type and p-type conductivity; and including a controller which controls the circuitry to conduct source and drain bias voltages and the circuitry to conduct gate bias voltages to establish bias arrangements for storing data in two charge trapping locations beneath each of said more than one of the plurality of gates in the series.