Patent ID: 7919367
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A method of fabricating a non-volatile memory cell comprising: forming a plurality of active regions in a semiconductor substrate; forming a floating gate electrode over first portions of the active regions, the floating gate electrode connecting various elements of the non-volatile memory cell; forming a patterned silicide-blocking layer over the floating gate electrode, whereby the patterned silicide-blocking layer fully covers and prevents silicide formation on the portions of the floating gate electrode located over the active regions; forming the silicide, wherein the patterned silicide-blocking layer prevents silicide formation on the portions of the floating gate electrode located over the active semiconductor regions; then forming a pre-metal dielectric over the silicide and the patterned silicide-blocking layer; forming a first mask over the pre-metal dielectric, wherein the first mask includes openings where contacts are to be formed through the patterned silicide-blocking layer; performing a partial etch of the pre-metal dielectric through the openings in the first mask; forming a second mask over the pre-metal dielectric, wherein the second mask includes openings where all contacts are to be formed; and then performing a contact etch through the openings of the second mask, wherein the contact etch extends through the patterned silicide-blocking layer.