Patent ID: 8352528
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. An apparatus for efficient and parallel implementation of digital signal processing algorithms in a single-instruction multiple-data (SIMD) processor, the apparatus comprising: a vector register file for containing vector registers, wherein each vector register holds a plurality of vector elements of a predetermined size, said vector register file storing a first source vector, a second source vector, and a control vector; a vector operation unit including a plurality of computing elements for performing a plurality of arithmetic/logical operations in parallel, each of said plurality of computing elements having a first input and a second input; a first select logic for each vector element position coupled to respective said first input for selecting from a first list including but not limited to elements of said first source vector in accordance with said control vector; a second select logic for each vector element position coupled to respective said second input for selecting from a second list including but not limited to elements of said second source vector in accordance with said control vector; wherein said first list further includes elements of said second source vector and wherein said second list further includes elements of said first source vector; and wherein each vector element stores a fixed-point or a floating-point number.