Patent ID: 8754464
Filing Date: 2014-06-17
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: a base gate, a metal gate, and a hard mask pattern sequentially stacked on a semiconductor layer, a first width of a lower portion of the metal gate and a second width of an upper portion of the base gate being less than a third width of the hard mask pattern; a first protection spacer on a first sidewall of the metal gate and a first sidewall of the upper portion of the base gate; a second protection, spacer on a second sidewall of the metal gate and a second sidewall of the upper portion of the base gate; and a tunnel dielectric layer, a charge storage layer and a blocking dielectric layer sequentially stacked between the semiconductor layer and the base gate; wherein the first and second sidewalls of the metal gate and the upper portion of the base gate define respective first and second undercut regions, wherein the first and second protection spacers are in the first and second undercut regions; and wherein the first and second undercut regions extend into the base gate and the metal gate beneath overhanging portions of the metal gate that have a fourth width that is greater than the second width.