Patent ID: 7428716
Filing Date: 2008-09-23
Classification: G06F

Abstract:
1. A system for determining timing in an electrical circuit comprising: a. a netlist input for receiving a circuit netlist representing a topology of the electrical circuit to be timed; b. an assertion input for receiving a set of one or more assertions representing boundary timing conditions; c. a delay variability input for receiving a list of one or more sources of delay variation that contain variability information of one or more of the sources of variation; d. a model input for receiving parameterized delay models, each parameterized delay model containing one or more models for a delay of one or more components of the electrical circuit, each model being a function of one or more of the sources of delay variation; and e. a process that determines and outputs a statistical arrival time of one or more nodes of the electrical circuit, the statistical arrival time being in a form of a weighted sum of probability distributions of one or more of the sources of variation.