Patent ID: 7569475
Filing Date: 2009-08-04
Classification: H01L

Abstract:
1. A method of fabricating an interconnect structure comprising: providing at least one opening in a dielectric material, said at least one opening is lined with a diffusion baffler and said dielectric material is comprised of SiO forming a first conductive region comprising Cu or a Cu alloy utilizing a bottom-up deposition fill process within said at least one opening; forming an electromigration (EM) preventing liner comprising Ta, TaN, Ti, TiN, Ru, RuN, RuTaN, RuTaN, Ir, IrCu or Co(W,B,P,Mo,Re) and having a thickness from about 2 to about 8 nm by a non-selective deposition process on at least a surface of said first conductive region, said EM preventing liner is U-shaped and abuts said diffusion barrier; and forming a second conductive region comprised of Cu or a Cu alloy on said EM preventing liner, said first and second conductive regions from a conductive feature within said dielectric material.