Patent ID: 7786776
Filing Date: 2010-08-31
Classification: H03L

Abstract:
1. A semiconductor integrated circuit comprising a clock generating section having a digital control oscillator operable to generate an oscillation clock signal, and wherein the clock generating section has a comparator, a counter and a control register, when the oscillation clock signal generated by the digital control oscillator is supplied to an input terminal of the counter, an output signal arises from an output terminal of the counter, a reference signal is supplied to one input terminal of the comparator, and the output signal arising from the output terminal of the counter is supplied to the other input terminal of the comparator, when the control register is supplied with an output signal of the comparator, the control register stores two or larger bits of digital control information for controlling the digital control oscillator, the comparator, control register, digital control oscillator and counter constitute a locked loop making at least one of a phase locked loop and frequency locked loop, when the control register stores digital control information having a predetermined value, at least one of a phase and frequency of the output signal at the other input terminal of the comparator is locked to at least one of a phase and frequency of the reference signal at the one input terminal of the comparator, the locked loop can work in two or more operation conditions by setting two or more frequencies for the reference signal or setting two or more multiplication ratios for the counter, the locked loop works in one operation condition selected from among the two or more operation conditions by setting one frequency selected from among the two or more frequencies for the reference signal, or setting one multiplication ratio selected among the two or more multiplication ratios for the counter, the clock generating section further includes a control data storing circuit connected with the control register, sets of initial set data for operation by the locked loop in the two or more operation conditions can be stored in advance in the control data storing circuit, operation select information for selecting the one operation condition is supplied to the control data storing circuit prior to an operation by the locked loop in the one operation condition, and in response to the operation select information, initial set data for the operation in the one operation condition is stored at an upper bit of the control register from the control data storing circuit.