Patent ID: 6716643
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method for fabricating a contact hole for a semiconductor memory component, having a silicon substrate, an intermediate dielectric layer arranged on said substrate, and an upper layer arranged on said intermediate dielectric layer, said upper layer being made of a material selected from the group consisting of a ferroelectric material and a material having a high dielectric constant the method comprising:forming a perforated mask on the upper layer, the mask including a material which exhibits temperature stability during a later deposition process; etching the upper layer and a depression into the intermediate dielectric layer as far as a residual thickness using the perforated mask; depositing a layer including O3/TEOS-SiO2 onto a structure thus obtained including the perforated mask; removing the layer including O3MEOS-SiO2 from a bottom of the depression by etching; and thereupon lowering the depression by etching in order to produce the contact hole as far as an interface with the silicon substrate, the silicon substrate being uncovered, the layer including O3/TEOS-SiO2 serving as a lateral seal of the upper layer during the lowering of the depression; after the uncovering of the silicon substrate at the bottom of the contact hole, the silicon substrate being spared, depositing a second layer including O3/TEOS-SiO2 into the second hole and onto a top surface proximate to the contact hole; wherein the perforated mask material is stripped prior to deposition of the second layer including O3/TEOS-SiO2.