Patent ID: 7284217
Filing Date: 2007-10-16
Classification: G06F

Abstract:
1. An LSI designing method comprising: preparing a timing model configured to be used under a first mode and a second mode; performing a functional design of functional elements each including one or more functional blocks having at least two flip flops; conducting logic composition using said timing model of said one or more functional blocks under said first mode with respect to said functional elements obtained by said functional design; performing a first timing analysis using said timing model under said first mode with respect to said functional elements on which said logic composition of said timing model of said one or more functional blocks was conducted; performing a layout based on a result of said logic composition and said first timing analysis; and performing a second timing analysis using said timing model under said second mode subsequent to performing said layout, wherein said timing model contains an independently defined clock delay time used only by said second mode, and wherein said clock delay time is defined as an average delay time of all of said flip flops concerning timing information calculation of said one or more functional blocks.