Patent ID: 8610219
Filing Date: 2013-12-17
Classification: H01L

Abstract:
1. A DRAM-incorporated semiconductor device comprising: a DRAM section comprising: a logic section formed on the same substrate as said DRAM section; plural transistors formed in the memory cell section and the decoder and sense amplifier of the adjacent circuit section of said DRAM, and in the logic section, said transistors comprising source-drain regions including a lightly-doped region and a highly-doped region having a higher impurity density than said lightly-doped region; a silicide layer which comprises one of cobalt silicide and nickel silicide and is formed, at least, on substantially an entire surface of said highly-doped region of said source-drain regions of said transistors in the memory cell section and the decoder and sense amplifier of the adjacent circuit section of the DRAM section and the transistors in the logic section, such that an interface between said silicide layer and said highly-doped region is located under a main surface of said substrate, wherein a P-N junction between said highly-doped region and a well in said substrate is deeper than a P-N junction between said lightly-doped region and said well, and wherein the plural transistors comprise: