Patent ID: 8315100
Filing Date: 2012-11-20
Classification: G11C

Abstract:
1. A method of reading a single bit in a memory cell of a memory array, the method comprising: providing a memory array comprising: applying a first voltage to a bit line, in the second set of bit lines, connected to the memory transistor in the memory cell to be read; applying a second voltage to a word line, in the first set of word lines, connected to the capacitor in the memory cell to be read, the second voltage being greater than the first voltage; grounding a word line, in the second set of word lines, connected to the access transistor in the memory cell to be read; grounding word lines, in the first set of word lines, not connected to the memory cell to be read; grounding word lines, in the second set of word lines, not connected to the memory cell to be read; and activating a column address transistor in a column supporting the memory cell to be read.