Patent ID: 6114872
Filing Date: 2000-09-05
Classification: H03K

Abstract:
A differential input circuit comprising:a first differential circuit of a current mirror type for generating a first differential voltage by using an input voltage and a reference voltage;a second differential circuit of a current mirror type for generating a second differential voltage having a phase opposite to that of said first differential voltage by using said input voltage and said reference voltage;a third differential circuit for generating an output voltage corresponding to a difference voltage between said first differential voltage and said second differential voltage by using said first and second differential voltages;a first clamping circuit, provided between said first differential circuit and said third differential circuit, for clamping said first differential voltage, said first clamping circuit includes a first MOS transistor having a first drain to which said first differential voltage is inputted, a first gate connected to said first drain, and a first source connected to a ground; anda second clamping circuit, provided between said second differential circuit and said third differential circuit, for clamping said second differential voltage, said second clamping circuit includes a second MOS transistor having a second drain to which said second differential voltage is inputted, a second gate connected to said second drain, and a second source connected to the ground wherein said first source of said first MOS transistor and said second source of said second MOS transistor are connected to the ground through a third MOS transistor having a third gate to which a first mirror voltage generated in said first differential circuit or a second mirror voltage generated in said second differential circuit is inputted.