Patent ID: 8775838
Filing Date: 2014-07-08
Classification: G06F,Y02D

Abstract:
1. A method for dynamically reducing power consumption by a processor in a computer system, the method comprising: determining a maximum number of times that the processor can incur a start-up delay after being placed into a low-power mode during a token period of time when executing a task for the token period of time; assigning a token count for the task in accordance with the determined maximum number of times that the processor can incur a start-up delay for the task; executing the task until a reaching an idle point; placing the processor into the low-power mode while executing the task in response to an idle indicator only if a current value of the token count assigned to the task is greater than zero; resuming execution of the task by waking the processor out of the low-power mode; decrementing the current value of the token count of the task each time the processor incurs a start-up delay in response to being awakened from the low-power mode; and resetting the current token count to match the assigned token count at the end of each token period; asserting a wake-up interrupt signal to wake the processor out of the low power mode when the processor is in a low-power mode; creating a histogram of wake-up interrupt occurrences during the token period for a plurality of time slots; determining for each time slot of the histogram a potential energy-saving that may be achieved by saving a token for later use; and wherein while the processor is in a low-power mode, a time slot is selected as a preemptive wake-up time slot and a preemptive wakeup request is asserted by a dynamic sleep controller if the histogram indicates it is likely that the processor will be awakened by a wake-up interrupt during the time-slot and if it is probable that a potential energy-saving that can be achieved by saving a token for later use is higher than an energy-saving that might be achieved by continuing the sleep at the time-slot.