Patent ID: 6287902
Filing Date: 2001-09-11
Classification: H01L,Y10S

Abstract:
A method for forming a contact hole for a microelectronic structure, said method comprising the steps of:defining adjacent active and field regions on a substrate, and circuits thereon;forming a field isolation layer on said field region;forming a first patterned conductive layer on said active region of said substrate spaced apart from said field region;forming an etch inhibiting layer on said field isolation layer adjacent said active region of said substrate, the active region including the first patterned conductive layer wherein said etch inhibiting layer comprises a second patterned conductive layer and an insulating spacer along a sidewall of the second patterned conductive layer, wherein the second patterned conductive layer does not extend over the active region of the substrate, and wherein the second patterned conductive layer is a dummy pattern electrically isolated from the substrate and circuits thereon;forming an insulating layer on said substrate, said field isolation layer, said first patterned conductive layer, and said etch inhibiting layer; andforming a contact hole in said insulating layer exposing a portion of said active region between said etch inhibiting layer and said first patterned conductive layer.