Patent ID: 7589369
Filing Date: 2009-09-15
Classification: H01L

Abstract:
1. A semiconductor construction, comprising: a semiconductor substrate having a substantially planar semiconductor surface; paired transistors having gates recessed into the substantially planar surface, sharing a source/drain region, and having other source/drain regions besides the shared source/drain region; a silicon nitride-containing layer over at least a portion of each of the paired transistors, and over part of the shared source/drain region; a bitline contact extending through the silicon nitride-containing layer to electrically couple with the shared source/drain region; a bitline over the silicon nitride-containing layer and electrically coupled with the bitline contact; and a pair of capacitors over and in electrical connection with said other source/drain regions; at least one of the capacitors having an electrically conductive storage node material that directly contacts the silicon nitride-containing layer.