Patent ID: 6137137
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A CMOS semiconductor device having N- and P-channel transistors, the N-channel transistor comprising:a gate electrode overlying a substrate with a gate dielectric layer therebetween;a channel region in the substrate under the gate electrode moderately or heavily doped source/drain region extending to a first depth from a surface of a semiconductor substrate; anda lightly doped drain (N-LDD) region adjoining the source/drain region and comprising:a first N-LDD portion, containing a first N-type impurity, extending to a second depth less than the first depth; anda second N-LDD portion, containing a second N-type impurity different from and having a greater diffusion coefficient than the first N-type impurity, extending to a third depth greater than the second depth, wherein the second N-type impurity does not extend to the channel region.