Patent ID: 8013333
Filing Date: 2011-09-06
Classification: H01L

Abstract:
1. A test pad interconnect structure for testing a plurality of integrated circuit dies formed in a semiconductor wafer, the interconnect structure comprising: a plurality of vertically stacked metal layers, each metal layer including a metallic test pad electrically connected to a die and an inter-metal dielectric material, the test pads each having a first longitudinal side and a second opposite longitudinal side; and at least a first metallic via bar embedded into the interconnect structure and being configured and arranged to electrically interconnect the test pads in the plurality of metal layers, the via bar engaging each of the test pads near the first side of each test pad and forming a continuous metallic structure extending horizontally in a longitudinal direction along substantially an entire length of each first side of each test pad and vertically along at least all of the test pads in the stacked interconnect structure; the test pad interconnect structure being disposed in a sacrificial scribe band formed between a pair of adjacent dies for separating the dies from the wafer; wherein the via bar forms a monolithic wall-shaped protective barrier that has a vertical height that is at least coextensive with a vertical height of the plurality of metal layers and a horizontal length that extends for substantially the entire longitudinal side of each test pad.