Patent ID: 6125058
Filing Date: 2000-09-26
Classification: G11C

Abstract:
An electrical circuit for optimizing an equalization pulse of a read sense amplifier in a memory chip comprising:(a) a memory chip(b) one or more capacitor circuits;(c) one or more capacitor circuit controls corresponding to each of said one or more capacitor circuits;(d) at least one input corresponding to each of said one or more capacitor circuits;(e) at least one attribute cell corresponding to each of said one or more capacitor circuits;(f) a switching device for alternately coupling each of said inputs and each of said attribute cells to said corresponding controls; and(g) an equalization pulse circuit, wherein(i) each of said one or more capacitor circuits are coupled to said equalization pulse circuit when said corresponding capacitor circuit control is asserted, and(ii) each of said one or more capacitor circuits are decoupled from said equalization pulse circuit when said capacitor circuit control is deasserted.