Patent ID: 8929158
Filing Date: 2015-01-06
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a reference voltage source formed on the integrated circuit configured to receive a power supply voltage and to generate a reference voltage, the reference voltage being adjusted in accordance with on one or more trim bits provided to the reference voltage source; a non-volatile memory formed on the integrated circuit configured to store a trim code to be applied to the one or more trim bits; and a trim circuit formed on the integrated circuit configured to receive the power supply voltage and to generate a target voltage using the power supply voltage, the trim circuit further configured to compare the reference voltage to the target voltage and to generate a latch signal for the non-volatile memory, wherein in response to the integrated circuit being configured in a test mode, the reference voltage source and the trim circuit receives the power supply voltage provided by a precision reference voltage source external to the integrated circuit and the reference voltage source receives a trim code sequence applied to the one or more trim bits; the reference voltage source generates the reference voltage based on one or more trim codes in the trim code sequence; the trim circuit compares the target voltage to the reference voltage being generated based on the trim code sequence; the trim circuit asserts the latch signal in response to a determination that the reference voltage generated based on a first trim code is equal to the target voltage; and the non-volatile memory stores the first trim code in response to the latch signal being asserted.