Patent ID: 7315601
Filing Date: 2008-01-01
Classification: H03L

Abstract:
1. A method of clocking a sample-and-hold (SAH) phase detector (PD), the method comprising the steps of: precharging a ramp node to a supply voltage in response to a first clock; discharging the precharged ramp node via a linear current source in response to a second clock; and sampling the discharging precharged ramp node in response to a third clock such that the ramp node is maintained at a desired output voltage level during the third clock, wherein the second clock commences in response to a voltage controlled oscillator (VCO) clock edge, and further wherein the third clock commences in response to a reference clock edge, such that quantization noise folding associated with the SAH PD is substantially reduced below levels achievable using charge pump based phase detectors.