Patent ID: 6867099
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. A method of fabricating a split-gate flash memory, comprising the steps of: providing a substrate; forming a patterned mask layer over the substrate; forming a trench in the substrate using the patterned mask layer as an etching mask; forming a tunnel oxide layer over the interior surface of the trench; forming a first conductive layer inside the trench, wherein the upper surface of the first conductive layer is lower than the upper surface of the substrate; removing the mask layer; removing the exposed tunnel oxide layer; forming a gate dielectric layer over the first conductive layer; forming a conformal first dielectric layer over the substrate; forming a second conductive layer over the substrate, wherein the second conductive layer completely fills the trench; and forming a source/drain region in the substrate on each side of the second conductive layer.