Patent ID: 6399469
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method for fabricating a field effect transistor within an active device area of a semiconductor substrate, the method including the steps of:A. depositing a gate dielectric layer on said semiconductor substrate; B. depositing a first semiconductor layer on said gate dielectric layer, said first semiconductor layer being comprised of a first semiconductor material; C. depositing a second semiconductor layer on said first semiconductor layer, said second semiconductor layer being comprised of a second semiconductor material; D. patterning a photoresist layer deposited on said second semiconductor layer to form a gate photoresist structure on said second semiconductor layer, wherein said gate photoresist structure is disposed over said active device area of said semiconductor substrate; and E. etching exposed regions of said second semiconductor layer and said first semiconductor layer continuously using a predetermined etch process to form a first gate structure from etching of said first semiconductor layer and to form a second gate structure from etching of said second semiconductor layer, wherein said second gate structure is disposed on said first gate structure; and wherein said first semiconductor material is different from said second semiconductor material, and wherein a first etch rate of said first semiconductor material in said predetermined etch process is faster than a second etch rate of said second semiconductor material in said predetermined etch process such that a first length of said first gate structure is smaller than a second length of said second gate structure after said predetermined etch process, and wherein sidewalls of said first gate structure are disposed inward from sidewalls of said second gate structure by a predetermined notch distance such that said first gate structure and said second gate structure form a notched gate structure of said field effect transistor; and wherein said first semiconductor material is comprised of polysilicon and germanium with a germanium content in a range of from about 30% to about 50%, and wherein said second semiconductor material is comprised of polysilicon.