Patent ID: 6778120
Filing Date: 2004-08-17
Classification: H03M

Abstract:
A D/A converter circuit, comprising:a first D/A converter for generating a first reference voltage and a second reference voltage different to each other in voltage level according to upper m bit of digital input data of (m+n) bits; a second D/A converter of R-2R ladder resistor type for converting the digital input data to an analog voltage value by using information of lower n bit of the digital input data and the first and second reference voltages so that the analog voltage value is within a range whose upper limit is a higher voltage level of the first reference voltage an the second reference voltage, and whose lower limit is a lower voltage level of the first reference voltage an the second reference voltage, the first reference voltage being supplied to respective input terminals on digital data input side of a ladder resistor-net in the second D/A converter when each bit of digital data of the lower bit inputted to the second D/A converter has a first value, and the second reference voltage being inputted to the respective input terminals on the digital data input side of the ladder resistor-net in the second D/A converter when each bit of the digital data of the lower n bit supplied to the second D/A converter has a second value, controlling means for generating a control signal according to which of voltage levels of the first reference voltage and the second reference voltage is higher; inverting means for inputting the digital data of the lower n bit as such to the second D/A converter when the control signal shows that the first reference voltage is higher in voltage level than the second reference voltage, and inputting the digital data of the lower n bit to the second D/A converter by exchanging the first value and the second value of the digital data of the lower n bit when the control signal shows that the first reference voltage is lower in voltage level than the second reference voltage, wherein the second D/A converter includes switching means for witching a voltage inputted to an input terminal of an offset level control resistor, wherein the switching means includes switches of a CMOS transistor structure corresponding to a plurality of connection terminals different in voltage level so as to switch the voltage inputted to the input terminal of the offset level control resistor by carrying out connection and disconnection between the input terminal of the offset level control resistor and the connection terminals, wherein the switches are operated in a complemented manner of P-type and N-type; and dummy switches made up of an N-type MOS transistor and a P-type MOS transistor having respective polarities that are provided parallel with each other, the dummy switches being provided parallel with a signal line having the switches and between the switches and the input terminal of the offset level control resistor, the P-type MOS transistor and the N-type MOS transistor each receiving a gate signal that is completely out of phase with a gate signal that is supplied to the MOS transistor of the switches having the same polarity.