Patent ID: 6259139
Filing Date: 2001-07-10
Classification: H01L

Abstract:
An MOS ESD protection circuit with embedded well diode, said circuit comprising:a well in a substrate, wherein electricity of said well is equal to said substrate;a plurality of transistors in and on said well, wherein a plurality of gates of said transistors are located on said well, a plurality of drains of said transistors being located in said well and a plurality of drains of said transistors being located in said well, wherein each said drain is located between two adjacent said sources, electricity of both said sources and said drains is different to electricity of said well;a pair of embedded wells that are adjacent to said well and are in contact with opposite sides of said well, wherein electricity of said embedded wells is different to electricity of well, depth of each said embedded well is larger than depth of any said source and depth of any said drain;a guard ring in said substrate, wherein said guard ring surrounds said well and passes through said embedded wells, electricity of said guard ring being different to electricity of embedded wells;a pair of auxiliary doped regions in said embedded wells, wherein each said auxiliary doped region locates in one said embedded well, each said auxiliary doped region and said guard ring is separated by an additional isolation, electricity of said auxiliary doped regions being equal to electricity of said embedded wells;a plurality of first conductive lines that couple said drains and said auxiliary doped regions with a terminal; anda plurality of second conductive lines that couple gates with a relative ground point, wherein said second conductive lines also couple said guard ring and said sources with said relative ground point.