Patent ID: 6384661
Filing Date: 2002-05-07
Classification: H04L

Abstract:
A method for decreasing jitter present at a receiver input of a high speed data link which comprises the steps of:coupling a driver circuit for input from said high speed data link of high speed data at a data input pin (A) of said driver circuit, which said driver circuit comprises a logic circuit consisting of: a first section (1) which provides data latches and a second section (2) which provides compensation for a pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in said driver circuit, and, after coupling said driver circuit to said high speed data link to receive said data at said data input pin, then controling jitter on the driver circuit by using a bit time derived from a clock splitter (SPLTR) in said driver circuit for cycling bits of data through said driver circuit by: storing in said first section (1) the said high speed data that is being sent and also storing a history of two bits of said high speed data which have just preceeded the said high speed data that is being sent through said driver circuit using a bit time derived from said clock splitter (SPLTR) in said fourth section (4) of said driver circuit; and skewing said stored history of two bits of said high speed data which have just preceeded the said high speed data by one half of the cycle of the bit time derived from said clock splitter (SPLTR) of said driver circuit; and then passing the said high speed data to the third section (3) which provides a muxing circuit and serializing the data by passing the said high speed data through said muxing circuit with the timing for the stored two bits of said high speed data history being skewed as well as that of the said high speed data serialized through the muxing circuit being provided by said fourth section; and after said skewing and serialization steps, using the second section to sample the information in the first section and then adjusting the timing derived from said clock splitter in said circuit for cycling more bits of high speed data through said said forth section to compensate the serialization of the third section for jitter.