Patent ID: 6335214
Filing Date: 2002-01-01
Classification: H01L

Abstract:
A method of forming an integrated circuit having dual-gate transistors in an SOI semiconductor wafer having a device layer disposed above a buried insulator layer that in turn is disposed above a bulk substrate, comprising the steps of:forming a set of transistor gate stacks on said device layer, each such gate stack being disposed over a transistor body; forming etch resistant gate sidewalls and cap layers on said gate stacks; forming a set of spacer sidewalls adjacent said gate sidewalls; defining a set of etch windows disposed about said gate stacks; etching a set of alignment apertures through said device layer and said buried insulator layer, said set of alignment apertures being disposed within said set of etch windows and adjacent to said spacer sidewalls; depositing an alignment layer of etch-resistant material in the bottom of said alignment apertures; depositing a layer of conductive material in said alignment apertures above said alignment layer and in contact with said semiconductor device layer; forming interconnection members above said device layer to connect said set of transistors to define said integrated circuit; bonding a top surface of said wafer to a support member; removing said bulk substrate; etching said buried insulator layer within a set of backside apertures below said set of transistors and defined by said alignment layers, thereby exposing a backside surface of said transistor body; depositing a backside gate insulator layer on said backside surface of said transistor body; and depositing a backside gate conductor on said backside gate insulator layer.