Patent ID: 7894268
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. A semiconductor memory device having a memory cell array configured by arranging a plurality of NAND cell units, said NAND cell unit comprises: a plurality of electrically erasable programmable nonvolatile memory cells connected serially; a first and a second selection transistor provided to connect both ends of said memory cells to a bit line and a source line, respectively; and dummy cells inserted in said NAND cell unit adjacent to said first and second selection transistors, respectively, wherein said memory cells and said dummy cells have respective control gates which are connected to regular word lines and dummy word lines, respectively, and said first and second selection transistors have respective gates which are connected to first and second selection gate lines, respectively, wherein a plurality of said NAND cell units sharing said regular word lines, dummy word lines and selection gate lines configures an erase unit, and wherein said memory cells and dummy cells in said erase unit are erased simultaneously by applying an erase voltage to a well region including said memory cell array formed therein, applying a first voltage of just or near 0V to said regular word lines in said erase unit, and applying a second voltage higher than said first voltage to said dummy word lines in said erase unit.