Patent ID: 6258658
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of fabricating a memory cell configuration, which comprises:providing a semiconductor substrate;forming mutually parallel insulation trenches in a main surface of the semiconductor substrate;forming bit line trenches with a bottom, side walls, and a crown in the main surface of the semiconductor substrate;forming bit lines on the bottom of each of the bit line trenches and source/drain regions on the crowns;changing a doping of one of the side walls of each one of a plurality of the bit line trenches and depositing a gate insulator such that a respective vertical selection transistor formed at the one of the side walls of each one of the plurality of the bit lines has a threshold voltage that is higher than a threshold voltage of a respective vertical selection transistor formed at another one of the side walls of each one of the plurality of bit line trenches; andforming word lines transverse to the bit line trenches and capacitors.