Patent ID: 6524916
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of manufacturing a CMOS semiconductor comprising:providing a substrate; forming first and second gate dielectrics on the substrate; forming first and second trapezoidal semiconductor gates respectively disposed on the first and second gate dielectrics, the first and second trapezoidal semiconductor gate dielectrics respectively having thickness T1 and T2, first and second top widths, and bottom widths W3 and W4 where W3 and W4 are respectively smaller than the first and second top widths wherein: the first and second top widths are respectively directly proportional to T1 and T2 when W3 and W4 are equal dimensions, W3 and W4 are respectively inversely proportional to T1 and T2 when the first and second top widths are equal dimensions, and the first and second top widths are equal and W3 and W4 are equal when T1 and T2 are equal dimensions; forming gate spacers around the first and second trapezoidal semiconductor gates; forming source/drain junction regions in the substrate under the gate spacers and self-aligned with the gate dielectrics; forming contact areas on a source/drain junction regions adjacent to and coplanar with the gate spacers; forming secondary spacers adjacent the gate spacers; and forming deep source/drain junction regions in the substrate under the contact areas adjacent the secondary spacers and self-aligned with the secondary spacers.