Patent ID: 6011447
Filing Date: 2000-01-04
Classification: H03K

Abstract:
A power-on reset circuit including:an oscillation circuit;an oscillation end detection circuit for confirming whether an oscillation is carried out properly;a voltage stabilizer for generating a predetermined voltage from a power-supply voltage and supplying the predetermined voltage to the oscillation circuit;a start-up circuit for initializing the voltage stabilizer; anda latch circuit for receiving an oscillation end detection signal from the oscillation end detection circuit and for receiving a switch signal from the start-up circuit, wherein said latch circuit outputs a reset cancel signal for canceling an initial state to an internal circuit of an integrated circuit,wherein at a time of power supply and a time subsequent to said power supply while the power is increasing, said oscillation end detection circuit outputs an oscillation end detection signal indicating that the oscillation at the oscillation circuit is inactive,wherein said switch signal indicates that the start-up circuit is operating so as to set said latch circuit to an initial state, and a signal from said latch circuit is input to said integrated circuit to set a power-on reset state,wherein during a time period when a value of the power-supply voltage exceeds a value of the predetermined voltage, by which the predetermined voltage outputted from the voltage stabilizer becomes stable, said start-up circuit outputs a switch signal indicating that the start-up circuit has stopped so as to cancel the initial state of the latch circuit, andwherein during a time period when the power-supply voltage is stable and the oscillation circuit starts the oscillation, said oscillation end detection circuit outputs an oscillation end detection signal indicating that an oscillation at the oscillation circuit is active such that the latch circuit has a set state, and said latch circuit outputs a signal to the integrated circuit for canceling the power-on reset state.