Patent ID: 6629257
Filing Date: 2003-09-30
Classification: G06F

Abstract:
Apparatus configured to automatically reset and initialize a clocking subsystem within an input/output (I/O) interface of a data processing system, the apparatus receiving clock signals from a clock source of the system, the apparatus comprising:a phase locked loop (PLL) circuit having a plurality of inputs including a reference clock input for receiving clock signals from the clock source and a reset input for receiving a PLL reset signal that resets the PLL, the PLL further having an output that delivers phased-aligned clock signals to logic of the I/O interface; a counter coupled to the PLL and having a plurality of inputs including a clock input that receives the clock signals and a first reset input configured to receive first reset signals, the counter further having a plurality of outputs including a first reset output for delivering global reset signals to the I/O interface and a second reset output for delivering the PLL reset signal to the PLL; a first timer circuit having an input that receives the clock signals, the first timer circuit generating a first timer signal in response to receiving the clock signals, and not generating the first timer signal in response to not receiving the clock signals; and a second timer circuit coupled to the first timer circuit and having an input for receiving the first timer signal, the second timer further having an output configured to deliver the first reset signal to the first reset input of the counter in response to detecting an absence of the first timer signal, thereby enabling the counter to reset the clocking subsystem in the absence of the clock signals.