Patent ID: 8270237
Filing Date: 2012-09-18
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array that includes a plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines; a first terminal that is supplied with a string of first signals, the string of first signals being serially supplied to the first terminal from an outside of the device; a relief-address generating circuit that is coupled to the first terminal to generate a relief address in response to the string of first signals, the relief address comprising a plurality of bits that correspond to the first signals, respectively, and being used to identify at least one of a failed one of the word lines and a failed one of the bit lines; a fuse set; and a programming circuit that programs the relief address into the fuse set so that the fuse set retains and provides the relief address to identify the at least one of a failed one of the word lines and a failed one of the bit lines.