Patent ID: 8014482
Filing Date: 2011-09-06
Classification: H04L

Abstract:
1. A signal receiving circuit, comprising: a sampler, for receiving an analog signal and for sampling the analog signal to generate a sampling signal according to a sampling clock; an ADC, coupled to the sampler, for transferring the sampling signal to a digital signal; an equalizer, coupled to the ADC, for equalizing the digital signal to generate an equalized digital signal; a quantizer, coupled to the equalizer, for quantizing the equalized digital signal to generate a processed digital signal; and a timing recovery circuit, directly coupled to an output terminal of the sampler and coupled to the equalizer, for adjusting timing of the sampling clock according to the processed digital signal and the digital signal, wherein the timing recovery circuit includes a timing recovery parameter generating circuit and a loop filter, and the timing recovery parameter generating circuit comprises: