Patent ID: 7804127
Filing Date: 2010-09-28
Classification: H01L

Abstract:
1. A semiconductor non-volatile memory comprising: a memory cell region having a semiconductor non-volatile memory cell; a peripheral region having a peripheral transistor; and a dummy region having a dummy activation region, wherein said semiconductor non-volatile memory cell includes, an Si (silicon) layer containing substrate; a first activation region having a ridge shape arranged in a stripe pattern, said first activation region including a ridge portion; a first element separation region embedded in both sides of the first activation region so that the ridge portion protrudes from the first element separation region; a first gate insulation film; a first gate electrode disposed on the first gate insulation film and extending in a direction perpendicular to a longitudinal direction of the ridge portion, said first gate electrode formed over an upper surface of the ridge portion for covering at least a part of both side surfaces of the ridge portion and an upper surface of the first element separation region; a first channel forming region formed in a surface layer region of the ridge portion at a position facing the first gate electrode; a first extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a first sidewall sequentially formed on the first extension region and one or both of side surfaces of the first gate electrode facing with each other in the longitudinal direction, said peripheral transistor includes a second activation region having a ridge shape and arranged on the Si layer containing substrate in a stripe pattern; a second element separation region formed on the Si layer containing substrate and embedded in the second activation region so that the second element separation region has a height same as an upper surface of the second activation region; a second gate insulation film disposed on the second activation region and the second element separation region and having a flat shape; a second gate electrode formed on the second gate insulation film and extending in a direction perpendicular to a longitudinal direction of the second activation region for covering the second activation region and at least a part of the second element separation region; a second channel forming region formed in a surface layer region of the second activation region at a position facing the second gate electrode; a second extension region formed on both sides of the second channel forming region in the longitudinal direction; and a laminated layer film and a second sidewall sequentially formed on the second extension region and one or both of side surfaces of the second gate electrode facing with each other in the longitudinal direction, and said dummy activation region is formed in the dummy region as an intermediate region between the memory cell region and the peripheral region on the Si layer containing substrate, said dummy activation region being arranged in parallel to the second element separation region and the second activation region on a plane same as that of the second element separation region and the second activation region.