Patent ID: 7064059
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method of forming a dual damascene metal interconnection comprising: a) preparing a semiconductor substrate; b) forming an interlayer insulating layer on the semiconductor substrate; c) patterning the interlayer insulating layer to form a preliminary via hole; d) forming a sacrificial via protecting layer, a first portion of the sacrificial via protecting layer filling the preliminary via hole and a second portion of the sacrificial via protecting layer covering an upper surface of the interlayer insulating layer at the outside of the preliminary via hole on the semiconductor substrate having the preliminary via hole; e) forming a sacrificial metal oxide layer on both the first and second portions of the sacrificial via protecting layer; f) patterning the sacrificial metal oxide layer to form a sacrificial metal oxide pattern having an opening exposing the first portion and a portion of the second portion of the sacrificial via protecting layer; and g) etching the sacrificial via protecting layer and the interlayer insulating layer using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.