Patent ID: 8990655
Filing Date: 2015-03-24
Classification: H03M

Abstract:
1. An apparatus comprising: a processor circuit; a single error component arranged for execution by the processor circuit to receive error correction code (ECC) information for ECC encoded data indicating one or more errors in the ECC encoded data, the ECC encoded data encoded using a Reed-Solomon (RS) code, the single error component to also determine whether the ECC encoded data includes a single error, identify a location of the single error in the ECC encoded data when the ECC encoded data was determined to have the single error or generate a flag to indicate the ECC encoded data has multiple errors, the single error component configured to identify an error value associated with the location of the single error and identify the location of the single error based on implementing an algorithm that includes  where e is the identified error value, j is the identified location of the single error, S represents partial syndromes included in the ECC information for the ECC encoded data and n represents any positive integer; a multiple error component arranged for execution by the processor circuit to receive the ECC information for the ECC encoded data indicating one or more errors and separately identify a given location for each error, the multiple error component configured to identify an error value associated with each separately identified given location; and a corrector component arranged for execution by the processor circuit to receive either the identified location of the single error with the identified error value associated with the location of the single error or if multiple errors, receive the separately identified given location for each error of the multiple errors and identified error value associated with each separately identified given location and correct the one or more errors in the ECC encoded data.