Patent ID: 8233309
Filing Date: 2012-07-31
Classification: G11C

Abstract:
1. A memory array comprising: first and second word lines; a first plurality M of data lines substantially orthogonal to the first and second word lines; a first transistor string comprising a first plurality M+1 of series-connected transistors, each such transistor having a gate terminal coupled to the first word line, said first transistor string having respective first and second end nodes and having a first plurality M of common source/drain nodes between and shared by adjacent transistors of the first transistor string; a first plurality M of resistive elements, each respective resistive element coupled between a respective one of the first plurality M of common source/drain nodes and a respective one of the first plurality M of data lines; a second transistor string comprising a second plurality M+1 of series-connected transistors, each such transistor having a gate terminal coupled to the second word line, said second transistor string having respective first and second end nodes, and having a second plurality M of common source/drain nodes between and shared by adjacent transistors of the second transistor string; and a second plurality M of resistive elements, each respective resistive element coupled between a respective one of the second plurality M of common source/drain nodes and a respective one of the first plurality M of data lines; wherein each respective common source/drain node within the first and second transistor strings is shared only by the respective adjacent transistors and the respective resistive element coupled thereto.