Patent ID: 9194912
Filing Date: 2015-11-24
Classification: G01R

Abstract:
1. A method for testing one or more semiconductor structures for a three-dimensional structure stack, comprising: controlling a logic signal of a first circuit which includes a first electrical element, the first circuit being part of a first semiconductor structure connected to a supply voltage, the first circuit configured to indicate a first state during pre-assembly testing of the first semiconductor structure, the supply voltage being part of the first circuit at the pre-assembly testing; and controlling the logic signal using the supply voltage of the first circuit to indicate a second state in response to the first circuit being connected to a second circuit which includes a second electrical element, the second circuit being part of a second semiconductor structure and the connection of the first and second circuits resulting in a combined circuit, the combined circuit being in a three-dimensional semiconductor structure stack comprising the first and second semiconductor structures during post-assembly testing of the three-dimensional semiconductor structure stack.