Patent ID: 6865106
Filing Date: 2005-03-08
Classification: G11C

Abstract:
1. A latching circuit that senses and latches the magnetic states of a first bit line and a second bit line in a magnetoresistive random access memory (MRAM), the latching circuit comprising: a first output and a second output; a reset circuit having a first terminal, a second terminal, and a third terminal, the reset circuit responsive to a first state of an input signal applied to the first terminal to couple the second terminal to the third terminal, and responsive to a second state of the input signal applied to the first terminal to decouple the second terminal from the third terminal; a first switch having a first switching terminal, a second switching terminal and a control terminal, the first switching terminal of the first switch coupled to a first portion of the first bit line; a second switch having a first switching terminal, a second switching terminal and a control terminal, the first switching terminal of the second switch coupled to a first portion of the second bit line; a third switch having a first switching terminal, a second switching terminal and a control terminal, the first switching terminal of the third switch coupled to a second portion of the second bit line; a fourth switch having a first switching terminal, a second switching terminal and a control terminal, wherein: