Patent ID: 9164839
Filing Date: 2015-10-20
Classification: G06F,H03M

Abstract:
1. An apparatus to correct data errors, comprising: a processor configured to use an error correcting code (ECC); and a memory configured to store data, the data including ECC data; wherein the ECC is used by the processor to identify a number of error bits in the data read from the memory and to correct the identified error bits; a counter that stores the number of identified error bits by using the ECC; a first limit of error bits that can be corrected by using the ECC; a second limit of error bits that can be identified by using the ECC but cannot be corrected by using the ECC; wherein the processor is configured to invert the identified error bits identified by using the ECC when the ECC is unable to be used to correct the identified error bits; and wherein the processor is further configured to invert the error bits identified by using the ECC when the number of identified error bits is more than the first limit and less than the second limit; and subsequently, the ECC is used to correct the data with the inverted bits.