Patent ID: 6657893
Filing Date: 2003-12-02
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device having an array of memory cells arranged in columns and rows over a well region of a semiconductor substrate, each said memory cell comprising:a memory transistor including: a first gate insulating film, which is formed on said semiconductor substrate; a floating gate electrode, which is formed on said first gate insulating film; an interelectrode insulating film formed on said floating gate electrode; and a control gate electrode formed on said interelectrode insulating film; a select transistor including: a second gate insulating film formed on said semiconductor substrate and a select gate electrode formed over said second gate insulating film; and an intermediate diffusion layer formed in a region of said semiconductor substrate and located between said memory transistor and said select transistor; source/drain diffusion layers formed in said semiconductor substrate to interpose a region underlying said memory transistor, a region underlying said select transistor and the intermediate diffusion layer therebetween; wherein a tunneling current, allowing electrons to pass through said first gate insulating film, is used while said electrons are ejected out of said floating gate electrode and while said electrons are injected into said floating gate electrode; and wherein a voltage is applied to said select gate electrode of said select transistor so as to weaken the electric field applied to said second gate insulating film of said select transistor, while said electrons are ejected out of said floating gate electrode.