Patent ID: 7493095
Filing Date: 2009-02-17
Classification: H03L,H04L

Abstract:
1. A transceiver for processing high data rate serial data, comprising: transceiver circuitry for transmitting and receiving the high data rate serial data; phase-locked loop circuitry further including a selectable coarse loop PLL and a selectable fine loop PLL, wherein: the selectable coarse loop PLL for producing a coarse error signal reflecting a difference between a reference signal and a coarse loop feedback signal; and the selectable fine loop PLL for producing a fine loop error adjustment signal based upon a difference in a recovered clock and the high data rate serial data; a loop filter for producing an error signal based on at least one of the fine loop error adjustment signal from a fine loop charge pump and the coarse error signal from a coarse loop charge pump; a controlled oscillation module for producing a receiver clock in the form of an oscillating signal based on the error signal produced by the loop filter; a divider for dividing the oscillating signal to produce the recovered clock to a phase detector; a selectable coarse loop selection switch coupled between the coarse loop charge pump and the loop filter; coarse loop logic circuitry for providing control commands to couple the selectable coarse loop PLL to the loop filter based upon one of a sample mode signal or a detected difference between a reference clock and the coarse loop feedback signal; a selectable fine loop selection switch coupled between the fine loop charge pump and the loop filter; and mode determination logic external to the fine loop PLL and coarse loop PLL coupled to produce mode switching signals to selectively switch the selectable coarse loop PLL and selectable fine loop PLL into and out of coupling according to defined operational logic within the mode determination logic.