Patent ID: 8188531
Filing Date: 2012-05-29
Classification: H01L

Abstract:
1. A dual gate of a semiconductor device, comprising: a semiconductor substrate comprising a cell region and a peripheral region, the cell region having a recessed gate forming area and the peripheral region having PMOS and NMOS forming areas; a first conductive type SiGe layer formed over the cell region and the PMOS forming area of the peripheral region; a second conductive type SiGe layer formed over the NMOS forming area of the peripheral region; a first conductive type polysilicon layer formed over the first conductive type SiGe layer; a second conductive type polysilicon layer formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers, wherein each of the first and second conductive type SiGe layers includes a layer having a Ge mole fraction of 10˜20% within the SiGe layer.