Patent ID: 7133853
Filing Date: 2006-11-07
Classification: G06N,H03M

Abstract:
1. An apparatus for performing parity check message passing decoding operations, the apparatus comprising: a message source for supplying at least one set of Z K-bit messages from any of at least L sets of Z K-bit messages, where Z is a positive integer greater than one and K and L are non-zero positive integers; a node processor including a plurality of node processing units, each node processing unit for performing at least one of a parity check constraint node processing operation and a parity check variable node processing operation; and a switching device coupled to the message source and to the node processing unit, the switching device for passing sets of Z K-bit messages between said message source and said node processor and for re-ordering the messages in at least one of said passed sets of messages in response to switch control information.