Patent ID: 8860479
Filing Date: 2014-10-14
Classification: G06F,H03L

Abstract:
1. An apparatus comprising: a first phase locked loop (PLL) circuit having a first clocking ratio coupled to receive an input differential clock signal, the first PLL circuit to generate a first reference clock signal; a second PLL circuit having a second clocking ratio coupled to receive the input differential clock signal, the second PLL circuit to generate a second reference clock signal; a first set of clock signal output buffers coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal; a second set of clock signal output buffers coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal; wherein the first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.