Patent ID: 7032200
Filing Date: 2006-04-18
Classification: G06F

Abstract:
1. A method for use in connection with an integrated circuit design, the method comprising: determining timing differences for respective ones of a plurality of paths, an individual timing difference being between an individual path of the plurality of paths including a low threshold variant of a gate instance and the individual path including a standard threshold variant of the gate instance, the individual path including at least one low threshold variant of a gate instance; determining a first set of path cycle times for respective ones of at least a subset of the plurality of paths, the subset corresponding to individual paths of the plurality of paths, the individual paths including a particular low threshold variant of a gate instance, a timing difference corresponding to at least one of the individual paths of the subset being a slowdown; determining a second set of path cycle times for respective ones of the subset of the plurality of paths, the individual paths including a standard threshold variant corresponding to the particular low threshold variant, thereby removing the timing difference from the individual paths; selecting a subset of low threshold voltage variants of gate instances for substitution with respective standard threshold voltage variants thereof based on at least a maximum of the first set of path cycle times and a maximum of the second set of path cycle times for a corresponding low threshold voltage variant.