Patent ID: 6808951
Filing Date: 2004-10-26
Classification: H01L

Abstract:
A method for manufacturing a semiconductor integrated circuit device including a MIS transistor structure, the method comprising the steps of:(a) forming a first gate insulating film for forming the MIS transistor structure on a main surface of a semiconductor substrate; (b) forming at least one pair of laminated structure bodies each including two layers of a first gate electrode covering a part of said first gate insulating film and a first insulating film covering said first gate electrode, an etching prevention film being formed on a sidewall portion of said first insulating film but so as not to cover sidewall portions of said first gate electrode; (c) introducing impurities into said semiconductor substrate through said first gate insulating film located in a region not covered with said laminated structure bodies, and thereby forming a first impurity introduced region self-aligned with said laminated structure bodies on the main surface of said semiconductor substrate; (d) removing said first gate insulating film in the region not covered with said laminated structure bodies after said step (c); and (e) forming a second insulating film covering upper portions and sidewall portions of said laminated structure bodies after said step (d).