Patent ID: 6753231
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device including a memory cell of an SRAM having a first p-channel MISFET and a first n-channel MISFET, and a logic circuit for a microprocessor having a second p-channel MISFET and a second n-channel MISFET,wherein said first p-channel MISFET is formed at a first p-channel MISFET forming region of a semiconductor substrate, wherein said first n-channel MISFET is formed at a first n-channel MISFET forming region of said substrate, wherein said second p-channel MISFET is formed at a second p-channel MISFET forming region of said substrate, wherein said second n-channel MISFET is formed at a second n-channel MISFET forming region of said substrate, said method comprising: selectively introducing a first impurity into said first p-channel MISFET forming region and said second p-channel MISFET forming region for controlling a threshold voltage; selectively introducing a second impurity into said first n-channel MISFET forming region and said second n-channel MISFET forming region for controlling a threshold voltage; selectively introducing a third impurity into said first p-channel MISFET forming region by using a mask covering said second p-channel MISFET forming region for controlling a threshold voltage such that a threshold voltage of said first p-channel MISFET is higher than a threshold voltage of said second p-channel MISFET; and selectively introducing a fourth impurity into said first n-channel MISFET forming region by using a mask covering said second n-channel MISFET forming region for controlling a threshold voltage such that a threshold voltage of said first n-channel MISFET is higher than a threshold voltage of said second n-channel MISFET; forming a groove in said substrate for defining said first p-channel MISFET forming region, said first n-channel MISFET forming region, said second p-channel MISFET forming region and said second n-channel MISFET forming region; and burying said groove with an insulating film by polishing an insulating film formed over said substrate having said groove.