Patent ID: 9219139
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: at least two fin structures present on a substrate surface; a gate structure present on the at least two fin structures, wherein the gate structure includes at least one high-k gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one high-k gate dielectric; a dielectric spacer having a dielectric constant that is less than the dielectric constant of the high-k gate dielectric, the dielectric spacer extends from a first fin structure to an adjacent fin structure and has an upper surface that is substantially coplanar with an upper surface of the at least two fin structures, wherein an entirety of a first sidewall surface of the dielectric spacer is in direct contact with the at least one high-k gate dielectric of the gate structure; and an epitaxial semiconductor material in direct contact with the at least two fin structures and separated from the gate structure by the dielectric spacer, wherein an entirety of a second sidewall surface of the dielectric spacer that is opposite the first sidewall surface directly contacts a sidewall surface of the epitaxial semiconductor material and wherein a bottommost surface of the dielectric spacer is coplanar with a bottommost surface of the high-k gate dielectric.