Patent ID: 8094677
Filing Date: 2012-01-10
Classification: H04L

Abstract:
1. A serial buffer comprising: a plurality of queues; a plurality of configuration registers; a parser coupled to receive incoming packets; a first processing path coupled to receive packets of a first packet type from the parser, wherein the first processing path comprises slave read circuitry for performing slave read accesses on read ports of the plurality of queues in response to packets of the first packet type; and a second processing path coupled to receive packets of a second packet type from the parser, wherein the second processing path comprises register access circuitry for accessing the configuration registers in response to packets of the second packet type; a memory access engine that implements bus master read accesses on the read ports of the plurality of queues in response to fullness levels of the plurality of queues; and egress control logic that routes data read from the configuration registers in response to packets of the second packet type with a higher priority than data read from the plurality of queues by the slave read accesses and the bus master read accesses.