Patent ID: 6330658
Filing Date: 2001-12-11
Classification: G06F

Abstract:
A circuit arrangement, comprising:a system memory;a slave processor arrangement coupled to the system memory and including,a control unit configured to process instructions of a first set retrieved from the system memory by the slave processor, wherein the first set of instructions is native to the slave processor arrangement,state means for providing at least one of several operational states for the slave processor arrangement,a program counter register in the state means configured to point to an address of a next instruction to be processed by the control unit, anda control register access port coupled to the state means to provide external access thereto; anda master processor arrangement coupled to the system memory and coupled to the slave processor arrangement, the master processor arrangement configured to process instructions of a second set retrieved from the system memory and to selectively start execution of the slave processor arrangement with a predetermined operational state by writing data into the state means through the control register access port to modify the program counter register, wherein the second set of instructions is native to the master processor arrangement and different from the first set.