Patent ID: 6521485
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A method for manufacturing wafer level chip size package at least comprising the steps of:providing a wafer having a plurality of chips, each chip having a plurality of connecting pads on its active surface; providing a metal plate consisting of a first layer and a second layer, wherein a plurality of conductive circuits are formed on the first layer of the metal plate by selectively etching, the plurality of conductive circuits are fixed on the second layer of the metal plate, and each conductive circuit has at least a first end and a second end, and the first ends of the conductive circuits are corresponding to the connecting pads of the chips in the wafer; securing the active surfaces of the chips onto the first layer of the metal plate, when the wafer and the metal plate being secured, connecting pads of the chips and the first ends of the conductive circuits being in vertical position to each other; drilling a plurality of blind holes on the plurality of first ends, wherein the blind holes pass through the metal plate and extend until exposing the connecting pads of the wafer; filling conductive material on the plurality of blind holes until the connecting pads of chip and the first ends of the conductive circuits becoming electrical connection; removing the second layer of the metal plate; and dicing the packed wafer to form a plurality of chip size packages.