Patent ID: 6406953
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method for fabricating an integrated circuit comprising one or more dynamic random access memory cells, the method comprising:introducing a dopant of a first conductivity type into a semiconductor substrate to form one or more well W1 of the first conductivity type; introducing a dopant of a second conductivity type into the well(s) W1 to form a second-conductivity-type well W2 in each well W1, wherein each well W2 is for containing electrodes of one or more transistors of the DRAM cell(s); introducing a dopant of the first conductivity type to form one more wells W3 of the first conductivity type, wherein each well W3 is for holding second-conductivity-type electrodes of one or more transistors, and wherein each well W3 does not overlap with any well W1; introducing a dopant D1 of the second conductivity type into one or more substrate regions which are for containing first-conductivity-type electrodes of transistors, the dopant D1 being blocked from: (1) each well W3, and (2) at least a portion of each well W1 which portion is for containing a low-resistance contact region LC1 for contacting the well W1.