Patent ID: 8837205
Filing Date: 2014-09-16
Classification: G11C

Abstract:
1. A semiconductor memory storage device, comprising: an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices; a first plurality of write ports; a write select signal coupled to the first plurality of write ports; a plurality of write port address lines coupled as input to each write port of the first plurality of write ports; a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each write port of the first plurality of write ports and to provide a single selected write word line signal to a respective one of the rows of the plurality of rows of the storage devices for one write port of the first plurality of write ports activated by the write select signal; a plurality of second select circuits; and a plurality of data lines coupled as inputs to the plurality of second select circuits, wherein respective ones of the data lines and a respective one of the write select signal lines are coupled as an input to each second select circuit of the plurality of second select circuits, and the plurality of second select circuits output data from a selected one of the data lines, wherein the first select circuit is an OR gate and the second select circuits are multiplexers.