Patent ID: 7622337
Filing Date: 2009-11-24
Classification: H01L

Abstract:
1. A method comprising: forming a first gate conductive layer pattern, a gate insulation layer pattern, and a silicon layer pattern over an SOI substrate comprising a substrate layer, a middle insulation layer formed over the substrate layer and a silicon layer formed over the middle insulation layer, wherein the silicon layer pattern is formed by etching the silicon layer; forming device isolation insulation layers over and contacting the middle insulation layer; forming a gate by forming a second gate conductive layer over the first gate conductive layer pattern and then etching the first gate conductive layer pattern and the second gate conductive layer to also form first gate conductive layer spacers on and contacting the gate insulating layer pattern and a sidewall of the device isolation insulation layers; forming insulating layer spacers spaced apart from a respective first gate conductive layer spacer and on and contacting sidewalls of the gate; forming a source and drain conductive layer adjacent to and contacting the first gate conductive layer spacers and the insulating layer spacers and over and contacting an exposed portion of the SOI substrate; forming a salicide layer over each of the gate and the source and drain conductive layer.