Patent ID: 6715117
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A method for testing a semiconductor memory device, wherein said method tests a semiconductor memory device having a wide data bus of an (mÃ—n)-bit width and includes a first process and a second process,said first process comprising the steps of: inputting (mÃ—n)-bit data; writing the (mÃ—n)-bit data into each address of the semiconductor memory device; reading out (mÃ—n)-bit data written into each address of said semiconductor memory device; comparing the read-out (mÃ—n)-bit data with the input (mÃ—n)-bit data of its before-written state to determine whether the read-out (mÃ—n)-bit data is correct; obtaining, if it is determined that the read-out (mÃ—n)-bit data is erroneous, an address corresponding to the erroneous data as a defective address; and ending testing of the semiconductor memory device if it is determined that the read-out (mÃ—n)-bit data from all addresses of said semiconductor memory device is correct; and said second process comprising the steps of: writing (mÃ—n)-bit data into said obtained defective address and then reading out the written (mÃ—n)-bit data; and comparing each m-bit data constituting the read-out (mÃ—n)-bit data with an expected value of a predetermined m-bit data to determine whether the each m-bit data constituting the read-out (mÃ—n)-bit data is correct.