Patent ID: 6598212
Filing Date: 2003-07-22
Classification: G01R,H03K

Abstract:
A testing apparatus which supplies a test signal to an electronic device and tests said electronic device, comprising:a pattern generating unit which generates a pattern that corresponds to said test signal; a wave form shaping unit having a delay circuit for generating a delay signal that corresponds to an operation characteristic of said electronic device, which shapes said pattern and outputs said test signal; a signal input output unit which supplies said test signal to said electronic device and receives an output signal from said electronic device; and a judging unit which judges whether said electronic device is acceptable or not based on said output signal, wherein said delay circuit has: a buffer which shapes a wave form of an input signal and outputs a shaped signal; a field effect transistor including a source region, a drain region, a gate electrode, and a substrate on which said source region and said drain region are installed; and an impressed voltage control unit which impresses a desired voltage to said gate electrode, and wherein said source region and said drain region are connected to a path through which an output signal transmits, and said delay signal is generated by controlling a capacitance between said source region, said drain region, and said substrate by impressing said desired voltage to said gate electrode.