Patent ID: 6054876
Filing Date: 2000-04-25
Classification: H03F,H03K

Abstract:
A buffer circuit comprising:a signal input terminal;a signal output terminal;a first operational amplifier including a differential amplifier circuit having an input transistor of an N-channel MOS type, the first operational amplifier having an inverting input terminal and an output terminal connected to each other, the first operational amplifier having a non-inverting input terminal connected to the signal input terminal;a second operational amplifier including a differential amplifier circuit having an input transistor of a P-channel MOS type, the second operational amplifier having an inverting input terminal and an output terminal connected to each other, the second operational amplifier having a non-inverting input terminal connected to the signal input terminal;first switching means for connecting the output terminal of the first operational amplifier to the signal output terminal when a voltage of an input signal applied to the signal input terminal is in a range where the first operational amplifier is operative; andsecond switching means for connecting the output terminal of the second operational amplifier to the signal output terminal when the voltage of the input signal applied to the signal input terminal is in a range where the second operational amplifier is operative.