Patent ID: 6122747
Filing Date: 2000-09-19
Classification: G06F,Y02D

Abstract:
A single chip integrated circuit computing system comprising:(a) a microprocessor;(b) an operand bus coupled to said microprocessor;(c) a serial interface circuit, in communication with said microprocessor;(d) an instruction bus, coupled to said microprocessor, which operates independently of said operand bus, whereby said microprocessor can simultaneously access instructions and operands;(e) a clock circuit for providing a clock signal to said microprocessor;(f) a shared bus;(g) means for coupling said shared bus to said operand bus and to said serial interface; said means for coupling comprising an arbitration circuit which provides access to said shared bus by only one of said operand bus and said serial interface at a time;(h) a low power logic circuit coupled to said microprocessor and coupled to said clock circuit which functions by blocking the transmission of said clock signal to said microprocessor;(i) a sleep mode activation circuit coupled to said microprocessor and to said low power logic circuit whereby said microprocessor can activate the low power mode; and(j) a sleep mode termination circuit coupled to said serial interface and to said low power logic circuit whereby said serial interface can terminate the low power mode; and(k) plural communication devices, coupled to said operand bus, each of said communication devices coupled to plural external interface terminals;wherein said communication between said microprocessor and said serial interface comprises communication over said operand bus.