Patent ID: 7324183
Filing Date: 2008-01-29
Classification: G02F

Abstract:
1. A thin film transistor array substrate, comprising: a substrate; a plurality of scan lines disposed on the substrate; a plurality of data lines disposed on the substrate, wherein the scan lines and the data lines define a plurality of pixel areas on the substrate; a plurality of thin film transistors, each of the thin film transistors being disposed in one of the pixel areas; a plurality of pixel electrodes, each of the pixel electrodes being disposed in one of the pixel areas and coupled to one of the thin film transistor corresponding thereto, and each of the pixel electrodes having a first opening; a plurality of common lines disposed on the substrate, a portion area of each pixel electrode being located over one of the common lines, each of the common lines having a second opening in the first opening; a plurality of capacitor electrodes having a third opening located in the first opening, each of the capacitor electrodes being disposed between one of the pixel electrodes and one of the common lines, wherein the third opening and the second opening are partially overlapped and a portion area of one of the common lines is exposed by the third opening; and a plurality of connecting conductive layers, each of the connecting conductive layers being disposed in the first opening, wherein each of the connecting conductive layers is coupled to one of the capacitor electrodes and one of the common lines.