Patent ID: 7952931
Filing Date: 2011-05-31
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cell units, each of the memory cell units having a first select gate transistor connected to a bit line, a second select gate transistor connected to a source line, a first memory cell transistor located between the first and second select gate transistors and adjacent to the second select gate transistor, and a second memory cell transistor located between the first select gate transistor and the first memory cell transistor; and a voltage control circuit controlling an initial charging voltage of a channel, wherein the voltage control circuit turns on the first select gate transistor without turning on the second select gate transistor so as to precharge the channel when a first write operation is performed for the second memory cell transistor, and turns on the first and second select gate transistors so as not to perform an initial charging operation for the channel when a second write operation is performed for the first memory cell transistor.