Patent ID: 8587119
Filing Date: 2013-11-19
Classification: H01L

Abstract:
1. A semiconductor die, comprising: a substrate; a bond pad over the substrate, the bond pad having a first width; a polyimide layer over the substrate and the bond pad, the polyimide layer having a first opening over the bond pad with a second width; a silicon-based protection layer overlying the polyimide layer, the silicon-based protection layer having a second opening over the bond pad with a third width, wherein the first opening and the second opening form a combined opening having sidewalls to expose a portion of the bond pad; an under bump metallurgy (UBM) layer over the sidewalls of the combined opening and contacting the exposed portion of the bond pad; and a conductive feature overlying the UBM layer; wherein a ratio of the third width to the first width is between about 0.15 to about 0.6, and the second width is smaller than the third width.