Patent ID: 6118693
Filing Date: 2000-09-12
Classification: G11C

Abstract:
An electrically erasable non-volatile memory cell, comprising:a bit line;a word line;a storage cell including a floating gate transistor for storing a logic value;an input transistor controlled by a first control signal at said word line, said input transistor coupling said bit line to said storage cell to allow, when said first control signal is in an asserted state, a logic voltage on said bit line to be written into said storage cell as said logic value;a pass transistor controlled by a second control signal, said pass transistor, when activated by an asserted state of said second control signal, provides said logic value to be read out from said storage cell; anda latch coupled to receive at an input terminal said logic value alternatively read from said storage cell or said bit line, and providing said logic value thus received on an output terminal of said electrically erasable non-volatile memory cell.