Patent ID: 6855641
Filing Date: 2005-02-15
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a gate oxide layer on a semiconductor substrate, a device isolation region being formed on the substrate to define an NMOS region and a PMOS region; sequentially forming a silicon germanium layer and an amorphous conductive layer on the gate oxide layer; removing the amorphous conductive layer and the silicon germanium layer in the NMOS region; forming a polysilicon layer in the NMOS and PMOS regions; and patterning the polysilicon layer in the NMOS region until the gate insulating layer is exposed and patterning the polysilicon layer, the amorphous conductive layer and the silicon germanium layer in the PMOS region until the gate insulating layer is exposed to form gate electrodes in the NMOS and PMOS regions.