Patent ID: 6181569
Filing Date: 2001-01-30
Classification: H01L,H05K,Y02P

Abstract:
A semiconductor chip package comprising:a semiconductor chip having a plurality of contact pads;a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads;a conductive trace extending from a location inside the hole along a surface of the first dielectric layer, the conductive trace being in electrical contact with the pad;a second dielectric layer overlying the first dielectric layer and conductive trace and containing a second hole, the second hole overlying the trace;a first conductive bump formed in the second hole and extending above the second dielectric layer;an encapsulant layer overlying the second dielectric layer, the first conductive bump extending through the encapsulant layer; anda second conductive bump on top of and in electric contact with the first conductive bump.