Patent ID: 8946033
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A method, comprising: (a) forming two or more fins on a top surface of an insulating layer on semiconductor substrate, each fin of said two or more fins being a solid rectangular block of single-crystal semiconductor material, each fin of said two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of said two or more fins are (100) surfaces and the longitudinal axes of said two or more fins aligned with a [100] direction; after (a), (b) forming a gate dielectric layer on each fin of said two or more fins; after (b), (c) forming an electrically conductive gate over said gate dielectric layer over said central region of each fin of said of two or more fins; after (c), (d) removing said gate dielectric layer from at least one end region of each fin of said two or more fins to form exposed end regions of each fin of said two or more fins, said exposed end regions on the same side of said conductive gate; and after (d), (e) growing an epitaxial semiconductor material on said exposed ends of each fin of said two or more fins to form a merged source/drain comprising said exposed ends of said two or more fins and said epitaxial semiconductor material, wherein said a top surface of said merged source/drain has no (111) facets formed during said growing of said epitaxial semiconductor material.