Patent ID: 6563894
Filing Date: 2003-05-13
Classification: H04L

Abstract:
An apparatus for providing an optimized sampling phase to a received signal in a given channel, the received signal including inter-symbol interference, the apparatus comprising:a voltage controlled clock (VCC) to provide a VCC sampling phase; a first signal detector, connected to said VCC, to sample said signal according to an advanced sampling phase which is advanced by a predetermined value &dgr; with respect to said VCC sampling phase to produce a first sampled signal; a second signal detector, connected to said VCC, to sample said signal according to a delayed sampling phase which is delayed by the predetermined value &dgr; with respect to said VCC sampling phase to produce a second sampled signal; a first channel metric estimating unit, connected to said first signal detector, to determine first estimates of characteristics of said channel and to obtain a first estimated metric value from said first sampled signal and said first estimates; a second channel metric estimating unit, connected to said second signal detector, to determine second estimates of characteristics of said channel and to obtain a second estimated metric value from said second sampled signal and said second estimates; and a subtracting unit, connected to said first channel estimating unit and to said second channel estimating unit, to subtract said first estimated metric value from said second estimated metric value to obtain a phase correction signal according to which said VCC sampling phase is to be corrected.