Patent ID: 8112729
Filing Date: 2012-02-07
Classification: G06F

Abstract:
1. A method for modeling an integrated circuit having devices, comprising: (a) converting, by processors of one or more computer systems, a representation of said integrated circuit into design shapes of design levels of a design of said integrated circuit; (b) adding, by said processors of said one or more computer systems, control shapes to said design, said control shapes not defining any physical part of said integrated circuit; (c) extracting, by said processors of said one or more computer systems, layout-dependent stress parameters of said devices from said design levels of said design based on said control shapes and said design shapes, said devices including one or more engineered stress elements; (d) converting, by said processors of said one or more computer systems, said layout-dependent stress parameters to stress parameters using a stress algorithm; (e) generating, by said processors of said one or more computer systems, stressed device parameters from said stress parameters using a compact model; and (f) simulating, by said processors of said one or more computer systems, performance of said integrated circuit using said stressed device parameters in a simulation model of said integrated circuit design.