Patent ID: 7483823
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A method of designing an integrated circuit, comprising: receiving an input of source code defining the integrated circuit written in a high-level language, wherein the high-level language is configured to specify programmable logical units (PLUs) and customizable logical units (CLUs); generating a first tree representation of the integrated circuit based on the source code, wherein the first tree representation includes components corresponding to the PLUs and CLUs, wherein the CLUs include a representation of interfaces to and from the CLUs; generating a second tree representation of the integrated circuit based on a parsing of the PLUs and CLUs of the first tree representation, wherein the second tree representation is not clock accurate and is not dependent on a type of model being produced; generating a third tree representation of the integrated circuit by combining the second tree representation with default timing information, wherein the third tree representation is clock accurate and corresponds to a model of the integrated circuit; generating a target model of the integrated circuit, by: obtaining target model information for the target model of the integrated circuit to be generated: selecting a target specific optimizer based on the target model information; and processing the third tree representation of the integrated circuit using the selected target specific optimizer.