Patent ID: 8307195
Filing Date: 2012-11-06
Classification: G06F

Abstract:
1. An information processing device comprising: an instruction fetch unit that supplies a fetch address to an instruction memory; an instruction buffer that stores an instruction read out from the instruction memory based on an address specified by the fetch address; an instruction executing unit that decodes and executes the instruction supplied from the instruction buffer; an instruction fetch control unit that stops supply of the fetch address to the instruction memory by the instruction fetch unit when the fetch address corresponds to a first address or an address after the first address while the instruction executing unit executes loop processing, the loop processing being executed based on a loop instruction in accordance with decoding of the loop instruction by the instruction executing unit; and an address determination circuit that determines the first address, wherein the address determination circuit obtains an end address of a data block read out from the instruction memory when at least one loop based on the loop instruction is executed and determines the end address or an address after the end address as the first address.