Patent ID: 6219300
Filing Date: 2001-04-17
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array including a plurality of memory cells;a first readout circuit reading and outputting a signal which is held in a specified memory cell among said plurality of memory cells;a second readout circuit reading and outputting a signal which is held in a specified memory cell among said plurality of memory cells,said second readout circuit having a lower operating speed than said first readout circuit, whereinsaid first and second readout circuits operate exclusively;a CPU operating in synchronization with a clock signal and having access to said memory cell array;a frequency divider dividing an external clock signal fed from outside by a plurality of ratios to generate signals having a plurality of periods, and selectively supplying one of said signals to said CPU as said clock signal; anda comparator for comparing a divisional ratio of said clock signal to said external clock signal with a reference value,wherein if said divisional ratio is not smaller than said reference value according to a comparison result of said comparator, said second readout circuit exclusively operates among said first and second readout circuits, and if said divisional ratio is smaller than said reference value, said first readout circuit exclusively operates.