Patent ID: 7184323
Filing Date: 2007-02-27
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a control circuit for generating first and second control signals, different in the timing phase of activation, based on a signal obtained on frequency dividing a clock signal supplied to the semiconductor integrated circuit device from outside the semiconductor integrated circuit device; and an amplifier circuit stage including four amplifier circuits, and first and second selection circuits, and first and second latch circuits; said four amplifier circuits being arranged and configured to receive read data signals from a memory cell array corresponding to four addresses, receiving said first control signal in common, and amplifying and outputting data signals corresponding to said four addresses, responsive to said first control signal; said first selection circuit being arranged and configured to receive data signals of two even addresses of said four addresses, changing over a signal transmitting path of the output destination depending on which of said data signals of two even addresses is output first and on which of said data signals of two even addresses is output later, responsive to a read start address; said first latch circuit being arranged and configured to receive the one of said data signals of two even addresses, output later, outputting a latch output to a corresponding signal transmitting path responsive to said second control signal; said second selection circuit being arranged and configured to receive data signals of two odd addresses of said four addresses, changing over a signal transmitting path of the output destination depending on which of said data signals of two odd addresses is output first and on which of said data signals of two odd addresses is output later, responsive to said read start address; said second latch circuit being arranged and configured to receive the one of said data signals of two odd addresses, output later, outputting a latch output to a corresponding signal transmitting path responsive to said second control signal; wherein said semiconductor integrated circuit device further comprises: a third selection circuit arranged and configured to receive the data signal of the even address, output first, and transmitted from said amplifier circuit stage to said signal transmitting path, and the data signal of the odd address, output first, and transmitted from said amplifier circuit stage to said signal transmitting path, to send said data signals to two outputs of a first output register in accordance with a readout sequence; a fourth selection circuit arranged and configured to receive the data signal of the even address, output later, and transmitted from said amplifier circuit stage to said signal transmitting path, and the data signal of the odd address, output later, and transmitted from said amplifier circuit stage to said signal transmitting path, to send said data signals to two outputs of a second output register in accordance with the readout sequence; and a fifth selection circuit arranged and configured to receive two outputs of said first output register and two outputs of said second output register, totaling at four outputs, to output the four outputs as serial data output signals in a read address sequence responsive to rising and falling edges of an input synchronizing clock signal.