Patent ID: 6182203
Filing Date: 2001-01-30
Classification: G06F

Abstract:
A microprocessor comprising:fetch circuitry for fetching a sequence of execution packets, wherein each execution packet comprises up to a first number of instructions;a first set of functional units connected to receive instructions from the fetch circuitry, the first set of functional units operable to execute a first plurality of instruction types;a second set of functional units connected to receive instructions from the fetch circuitry; wherein the second set of functional units is operable to execute the first plurality of instruction types;dispatch circuitry connected between the fetch circuitry and the first set of functional units and the second set of functional units, the dispatch circuitry operable to dispatch each instruction of each execution packet to both the first set of functional units and to the second set of functional units, such that all instructions of a given execution packet are executed in parallel; andwherein the dispatch circuitry selectively dispatches each instruction of each execution packet to either the first set of functional units or to the second set of functional units in response to a bit in each instruction.