Patent ID: 8907993
Filing Date: 2014-12-09
Classification: G09G

Abstract:
1. A display device comprising: a plurality of pixels each of which has a transistor, a pixel electrode connected to the transistor, and a reference electrode disposed so as to be opposite to the pixel electrode, wherein the plurality of pixels are arranged in a matrix; a plurality of gate lines that are respectively connected to the plurality of pixels; a plurality of data lines that are respectively connected to the plurality of pixels; a gate circuit that sequentially outputs gate signals to the plurality of gate lines; a driver that includes a data circuit generating data signals, which have different polarities, according to grayscale values, for each predetermined horizontal period; and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel, wherein the data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines via the switch groups respectively connected to the data lines; wherein each of the time division switches and the timing adjustment switches is an NMOS transistor; wherein the driver turns on the timing adjustment switches, which are included in the switch groups connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches, which are included in the switch groups connected to the data lines to which negative output signals are output from the driver, by a predetermined period, among the plurality of data lines; wherein during a first horizontal period, the driver applies the precharge voltages having one of positive and negative polarities to the respective data lines, and applies data signals having the other polarity after applying a reference voltage, wherein during a second horizontal period after the first horizontal period, the driver applies data signals which have the same polarity as the data signals which have been applied during the first horizontal period, to the respective data lines, and wherein during the second horizontal period, the driver turns off the timing adjustment switches included in the respective switch groups.