Patent ID: 6448833
Filing Date: 2002-09-10
Classification: H03K

Abstract:
A delay circuit comprising:a P-type MOS transistor for load capacitance whose gate electrode is connected to a signal line and source and drain electrodes are connected to each other; an N-type MOS transistor for load capacitance whose gate electrode is connected to said signal line and source and drain electrodes are connected to each other; first power supply means for applying a boosted voltage higher than a supply voltage VDD to the connection of source and drain of said P-type MOS transistor for load capacitance; second power supply means for applying a substrate voltage lower than a ground voltage to the connection of source and drain of said N-type MOS transistor for load capacitance; means for switching between said boosted voltage higher than said supply voltage VDD and a voltage equal to or lower than said ground voltage as a voltage applied by said first power supply means to said connection of source and drain of said P-type MOS transistor for load capacitance; and means for switching between a voltage equal to or higher than said supply voltage VDD and said substrate voltage lower than said ground voltage as a voltage applied by said second power supply means to said connection of source and drain of said N-type MOS transistor for load capacitance.