Patent ID: 6483751
Filing Date: 2002-11-19
Classification: G11C

Abstract:
A method of making a flash memory integrated circuit, said method including the steps of:(a) providing an array of flash memory cells in said integrated circuit, each of said cells having a conduction threshold voltage, a control gate, a floating gate, a source and a drain; and (b) providing a control circuit coupled to said array for adjusting the threshold voltages of the flash memory cells prior to an erase operation, the control circuit being configured such that: i) electrical charge on floating gates of the flash memory cells is modified by applying one or more partial erase signals having a magnitude and duration configured to affect substantially less electrical charge on said floating gates than that electrical charge required to place such flash memory cells into a fully erased state; and ii) the modification of said charge during step (i) can be repeated as desired to substantially equalize electrical field intensities across tunnel oxides associated with said floating gates of the flash memory cells; iii) one or more full strength erase signals, separate from said one or more partial erase signals, can be applied to such flash memory cells so as to place such cells in said fully erased state; wherein said one or more partial erase signals reduces cell over-erasures caused by said one or more separate full strength erase signals.