Patent ID: 6794916
Filing Date: 2004-09-21
Classification: H03K

Abstract:
A static, double-edged triggered flip-flop comprising:an input terminal; an output terminal; a first switch passing data from the input terminal to a first intermediate node on a clock signal; a first data loop connected between said first intermediate node and said output terminal, wherein said first data loop includes: (a) a first forward path having a circuit which operates based on a complementary clock signal; (b) a shared path connected from an output of said first forward path to said output terminal; and (c) a first bi-directional feedback path connected from said output terminal to said first intermediate node and having a third switch which operates on a skewed clock signal; a second switch passing data from the input terminal to a second intermediate node on said complementary clock signal; and a second data loop connected between said second intermediate node and said output terminal, wherein said second data loop includes: (a) a second forward path having a circuit which operates based on said clock signal; (b) said shared path also connected an output of said second forward path; and (c) a second bi-directional feedback path connected from said output terminal to said second intermediate node and having a fourth switch which operates on a complementary skewed clock signal.