Patent ID: 8916437
Filing Date: 2014-12-23
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a transistor, comprising: forming an insulated gate structure on a p-type substrate; forming a channel beneath the insulated gate structure such that the channel and the insulated gate structure define a first and a second undercut void region that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively; forming a passivation layer on at least one exposed sidewall surface of the channel, wherein forming the passivation layer includes forming a separation layer between the at least one exposed sidewall surface of the channel and a passivating material included in the passivation layer, the separation layer comprising a material different than the passivating material; and forming a metal source and a metal drain terminal on a first and a second side of the channel, respectively, including on the passivation layer and within the undercut void regions beneath the insulated gate stricture, at least one of the metal source and drain terminals comprising a metal that has a work function near a valence band of the p-type substrate.