Patent ID: 6918024
Filing Date: 2005-07-12
Classification: G06F

Abstract:
1. An address generating circuit, which generates an address for accessing cyclically to a memory area by a modulo addition, comprising: in case that said address is 2N bits, a renewing step is N bits, and the size of a modulo area is N bits, a two input adder that adds said address of 2N bits and said renewing step of N bits, and outputs its added result of 2N bits; a three input adder and subtracter that adds lower N bits of said address of 2N bits and said renewing step of N bits, and adds the size of said modulo area of N bits to an added result of said lower N bits of said address of 2N bits and said renewing step of N bits, or subtracts the size of said modulo area of N bits from said added result of said lower N bits of said address of 2N bits and said renewing step of N bits, and outputs an added result or an added and subtracted result of N bits; a concatenating means that concatenates upper N bits of said address of 2N bits to said output of N bits from said three input adder and subtracter from the side of the most significant bit of said three input adder and subtracter output, and outputs a concatenated result of 2N bits; a selection judging circuit that generates a selection signal for selecting one of outputs from said two input adder and said concatenating means based on said lower N bits of said address of 2N bits, said renewing step of N bits, and the size of said modulo area of N bits; and a multiplexer that outputs an address after renewed as a circuit output by selecting one of said output of 2N bits from said two input adder and said output of 2N bits from said concatenating means based on said selection signal from said selection judging circuit, wherein: said two input adder, said three input adder and subtracter, and said selection judging circuit are worked in parallel and independently.