Patent ID: 6018254
Filing Date: 2000-01-25
Classification: H03K

Abstract:
A circuit for providing clock phases to a plurality of n dynamic logic gates, the plurality of dynamic logic gates being connected in series with a first dynamic logic gate connected to a second dynamic logic, the second dynamic logic gate being connected to a third dynamic logic gate and so on until the nth dynamic logic gate, n being an integer greater than one, the circuit comprising:a plurality of n delay circuits connected in series, a first delay circuit of said plurality being coupled to receive a primary clock signal and configured to provide a first clock phase delayed relative to the primary clock signal, a second delay circuit coupled to receive the first clock phase and configured to provide a second clock phase delayed relative to the first clock phase and so on, with said nth delay circuit being coupled to receive an (n-1) th clock phase and configured to provide an nth clock phase delayed relative to the (n-1) th clock phase,wherein the first dynamic logic gate is coupled to receive the first clock phase, the second dynamic logic gate is coupled to receive the second clock phase and so on with the nth dynamic logic gate being coupled to receive the nth clock phase.