Patent ID: 6700582
Filing Date: 2004-03-02
Classification: G06F

Abstract:
A system for buffer management, comprising:a central processing unit (CPU), which accesses a memory through a chipset; a multimedia chip coupled to the chipset via a bus; a buffer for storing a plurality of command data associated with a plurality of multimedia commands that the CPU is to send to the multimedia chip, wherein the multimedia chip reads the command data from the buffer and executes the command data; a beginning register for storing a beginning address of the buffer; an ending register for storing an ending address of the buffer or a buffer length; and a pause storage unit, content of which includes a data address associated with the command data, wherein the pause storage unit has a pause state indicating a next operation to be executed when the multimedia chip has read the command data stored in the buffer with the data address stored in the pause storage unit: wherein when there are command data left to be written into the buffer: the pause storage unit stores a data address which is associated with a portion of the command data in the buffer when a portion of the command data is written into the buffer, and the multimedia chip is triggered to begin command data reading from the buffer.