Patent ID: 7634602
Filing Date: 2009-12-15
Classification: G06F

Abstract:
1. A bus system, comprising: an interface bus having at least one data line on which data are transmitted; first and second bus interfaces connected by the interface bus; and first and second bus control devices, where the first bus control device is allocated to the first bus interface and the second bus control device is allocated to the second bus interface; where the interface bus includes first and second signaling lines that signal a respective state of each of the first and second bus control devices, a third signaling line that signals an exchange of data on the at least one data line, and a clock line that synchronizes the bus system by a clock; where the first and second bus control devices each generate a control word having control information that relates to the data transmitted on the at least one data line, and where one of the first and second bus control devices transmits the control word on the at least one data line and where the other one of the first and second bus control devices receives the transmitted control word and relays the received data on the at least one data line based on the control information contained in the control word to at least one additional connected device and where the first and second signaling lines are unidirectional in opposite directions, and where the first signaling line is allocated to the first bus control device and the second signaling line is allocated to the second bus control device, where the first and second bus control devices access the bus system at different clock states of the clock and self-arbitrate access of the first and second bus interfaces to the bus.