Patent ID: 7631170
Filing Date: 2009-12-08
Classification: G06F

Abstract:
1. An embedded-DRAM (dynamic random access memory) processor comprising: an embedded DRAM array comprising a plurality of random access memory cells arranged in rows and columns; a row address register that holds a pointer that points to a row of the DRAM array; first and second registers files, each of said register files capable of loading or storing an entire row of the DRAM array in response to a single latch signal; and an embedded processor comprising first and second functional units, said first and second functional units having respective first and second instruction sets and capable of accessing said first and second register files; wherein said first and second register files comprise a parallel access port operative to parallely transfer contents of one of said register files between a DRAM row as selected by said row-address register, said first and second register files further comprising at least a second access port operative to transfer data between a selected one of said register files and said second functional unit; wherein said first instruction set comprises at least: wherein said second instruction set comprises at least: