Patent ID: 6504408
Filing Date: 2003-01-07
Classification: H03L

Abstract:
A delay locked loop (DLL) circuit comprising:a delay line configured to delay the transitions of a reference clock signal; a counter coupled to the delay line, wherein the counter provides a count to the delay line, wherein the amount of delay provided by the delay is determined by the count, a phase detector coupled to the delay line and a counter control circuit, wherein the phase detector is configured to receive an output clock signal from the delay line and the reference clock signal, and wherein the phase detector is configured to produce one or more output signals dependent upon the phase relationship between the reference clock signal and the output clock signal; and the counter control circuit coupled to receive the one or more output signals from the phase detector, wherein the counter control circuit is configured, responsive to a reset of the DLL circuit, to cause the counter to count in a predetermined direction even in an event that the one or more output signals of the phase detector indicate counting in an opposite direction to the predetermined direction.