Patent ID: 8988263
Filing Date: 2015-03-24
Classification: H03M

Abstract:
1. A system comprising: a variable impedance controllable by a manual tuning mechanism to provide an analog signal; and an analog-to-digital converter (ADC) coupled to the variable impedance to receive the analog signal, the ADC including: a comparator to compare the analog signal received at a first input with a feedback signal received at a second input; a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of an N-bit output based on the comparison; a delta-sigma modulator (DSM) coupled to the SAR to receive the N-bit output of the SAR and to generate an output; and a digital-to-analog converter (DAC) coupled to the DSM to convert the output to the feedback signal; and a low pass filter (LPF) to filter and output the feedback signal to the second input of the comparator.