Patent ID: 8949750
Filing Date: 2015-02-03
Classification: G03F,G06F,H01J

Abstract:
1. A method for fracturing or mask data preparation of a semiconductor device layout design to be formed on a wafer using a lithographic process with a reticle, the layout design comprising a diagonal pattern, wherein a portion of the diagonal pattern comprises a constant-width or nearly constant-width track on the wafer, and wherein an inner transition region of the diagonal pattern is adjoined on one side by an outer transition region and on the other side by a central core region, the method comprising the steps of: determining a set of at least three non-overlapping variable-shaped beam (VSB) outer transition shots, wherein the VSB outer transition shots form on the reticle the portion of the diagonal pattern in the outer transition region; determining a set of VSB core shots, wherein the VSB core shots form on the reticle the portion of the diagonal pattern in the central core region, wherein each shot in the set of core shots overlaps another shot in the set of core shots; determining a series of at least three VSB inner transition shots, wherein the VSB inner transition shots form on the reticle the portion of the diagonal pattern in the inner transition region, wherein the portion of the diagonal pattern in the inner transition region comprises an inner transition pattern characteristic, and wherein the inner transition pattern characteristic smoothly transitions between the pattern defined by the outer transition shots and the pattern defined by the core shots; and comparing a reticle pattern determined by the inner transition shots to a conventional reticle pattern in which non-overlapping VSB shots are used to form the diagonal pattern in the inner transition region, wherein the step of determining the series of inner transition shots is performed using a computing hardware device.