Patent ID: 6071763
Filing Date: 2000-06-06
Classification: H01L

Abstract:
A method of fabricating a layered integrated circuit, the method comprising:providing a semiconductor substrate;forming a first oxide layer over the substrate;forming a silicon nitride layer over the first oxide layer;removing a portion of the silicon nitride layer to form a junction area;forming a plurality of junction devices in the semiconductor substrate;removing the silicon nitride layer and the first oxide layer;forming a second oxide layer over the semiconductor substrate;implanting oxygen into a region below the semiconductor substrate surface;performing thermal oxidation operation to form a buried oxide insulation layer below the substrate surface, wherein the junction area is underneath the buried oxide insulation layer;removing the second oxide layer;growing an epitaxial silicon layer over the buried oxide insulation layer;forming a plurality of trench isolation structures in the epitaxial silicon layer; andforming a plurality of metal-oxide-semiconductor (MOS) devices above the epitaxial silicon layer.