Patent ID: 6665757
Filing Date: 2003-12-16
Classification: G06F,Y02D

Abstract:
A communication interface, comprising a clock signal line, a first signal line, a second signal line and one or more data signal lines as communication signal lines between a master system and a slave system, wherein:the master system transmits a clock signal to the clock signal line after the slave system has activated the first signal line; the master system stops transmitting the signal to the clock signal line after the slave system stops activation of the first signal line; after a predetermined period of time has passed after the master system has stopped transmitting the clock signal to the clock signal line, the master system activates the first signal line and transmits the clock signal to the clock signal line; the master system and the slave system communicate with each other via the one or more data signal lines in synchronism with the clock signal on the clock signal line; and after the communication is completed, the master system stops activation of the first signal line while simultaneously stopping transmission of the clock signal to the clock signal line.