Patent ID: 6492210
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method of forming a field-effect transistor in an integrated circuit comprising the steps of:(a) providing a semiconductor substrate having a surface, a buried insulating layer, and an electrically conductive layer doped with impurities between said surface and said buried insulating layer; (b) forming a gate electrode over said surface, said gate electrode having a gate width, a gate length that corresponds to a final critical dimension of said gate electrode, and sidewalls along its width direction; (c) forming first sidewall spacers having a first lateral extension along said sidewalls of said gate electrode; and (d) removing portions of said semiconductor substrate above said buried insulating layer and adjacent said first sidewall spacers until said buried insulating layer is exposed, using said first sidewall spacers as a masking material for defining an active region.