Patent ID: 9217774
Filing Date: 2015-12-22
Classification: G01R,G06F

Abstract:
1. A method for analyzing a hardware circuit implemented in a field-programmable gate array (FPGA), the method comprising: determining, by the FPGA, a plurality of events that occur in the FPGA; associating, by the FPGA, a timestamp with each of the determined events; creating, by the FPGA, a log of the events and respective timestamps; receiving, by a computer, the log; utilizing, by the computer, the log to replay a prior FPGA execution in a simulation, wherein the replay is based upon non-deterministic input data and timing information in the log, and wherein the replay is performed using a hardware description language (HDL) code which is the same as that used to configure the FPGA after synthesis; and outputting, by the computer, the simulation.