Patent ID: 6346729
Filing Date: 2002-02-12
Classification: H01L

Abstract:
A MOSFET device structure, on a semiconductor substrate, comprising:insulator filled shallow trench, isolation regions, in said semiconductor substrate; a device region located between insulator filled shallow trench, isolation regions; a polysilicon gate structure, on an underlying silicon dioxide gate insulator layer, in the center of said device region; a capping, insulator layer on the top of said polysilicon gate structure; insulator spacers on the sides of said polysilicon gate structure; a lightly doped source/drain segment, in a region of said semiconductor substrate, located completely underlying said insulator spacers; an L shaped, thin silicon oxide layer, comprised of a vertical shape, extending vertically downward from the bottom of said lightly doped source/drain segment, and a horizontal shape, extending horizontally from the bottom of said vertical shape, of said L shaped thin silicon oxide layer, to the side of an insulator filled shallow trench, isolation region; and a heavily doped source/drain region, in single crystalline silicon, bounded by said L shaped, thin silicon oxide layer, and by said insulator filled shallow trench, isolation region, and interfacing and contacting, the side of said lightly doped source/drain segment, located under said insulator spacer.