Patent ID: 8699985
Filing Date: 2014-04-15
Classification: G06F

Abstract:
1. A device, comprising: an input port configured to receive an input signal; a programmable first frequency generator including a direct digital synthesizer (DDS) configured to receive a sampling clock signal having a variable sampling clock frequency and in response thereto to generate a first local oscillator (LO) signal having a variable first LO frequency; a first intermediate frequency (IF) mixer configured to mix the input signal and the first LO signal to produce a first IF signal; a second local oscillator configured to generate a second LO signal having a second LO frequency; a second intermediate frequency (IF) mixer configured to mix the first IF signal and the second LO signal to produce a second IF signal, wherein the sampling clock signal is synchronously derived from the second LO signal; a first programmable frequency divider configured to receive the second LO signal and to divide the second LO frequency by a first programmable frequency divider value to produce a first reference signal having a first reference frequency; a second programmable frequency divider configured to receive the second LO signal and to divide the second LO frequency by a second programmable frequency divider value to produce a second reference signal having a second reference frequency; and a reference frequency mixer configured to mix the first and second reference signals, and to output the sampling clock signal.