Patent ID: 6391707
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for forming an integrated circuit capacitor, comprising the steps of:forming a first electrically conductive layer over a substrate; patterning the first electrically conductive layer, thereby defining a capacitor region; forming a first electrically insulating layer over the first electrically conductive layer; patterning the first electrically insulating layer, thereby defining a standard via and a primary enlarged via therein; forming an electrically conductive first electrode layer over the patterned first electrically insulating layer and first electrically conductive layer, thereby filling the standard via and overlying the primary enlarged via in a generally conformal manner; forming a dielectric layer over the first electrode layer; forming an electrically conductive second electrode layer over the dielectric layer; and planarizing the second electrode layer, the dielectric layer, and the first electrode layer a predetermined amount, thereby defining and laterally electrically isolating a capacitor in the capacitor region.