Patent ID: 6567834
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein an input for the first number and an input for the second number are connected to said processing devices, and said processing devices are connected to each other by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device:the value received at the instruction input is determined by two bits of the first number; data inputs are provided by m bits of the second number, a summation input for a sum of partial products of the same significance, and, if appropriate, a carry input to add a carry from a less significant partial product; data outputs are provided as a summation output containing the least significant m bits of the partial product and a carry output containing any more significant bits of the partial product; and a plurality of instructions provided each cause to be passed to the data outputs values representative of 0, 1, 2, and 3 times the m bits of the second number, in accordance with the values of the two bits of the first number.