Patent ID: 6032261
Filing Date: 2000-02-29
Classification: G06F,H04J,H04L

Abstract:
A bus bridge for interconnecting a plurality of buses, comprising:a plurality of bridge portals, each bridge portal being coupled to a respective one of the buses;a plurality of switching subsystems, each coupled to a respective one of the bridge portals and which collectively form a switching system which interconnects the plurality of bridge portals; anda plurality of cycle clock subsystems, each operatively associated with a respective one of the bridge portals and the respective switching subsystem coupled to the associated bridge portal;wherein each cycle clock subsystem comprises:a cycle clock generator for generating a cycle clock; anda cycle counter which receives the cycle clock at a reset input thereof, and which produces a cycle count output which constitutes a common timing reference for the respective switching subsystem and the respective bridge portal;and further wherein the cycle count output generated in one of said subsystems is distributed to the cycle counters of all other of said subsystems to provide a common timing reference for the bridge portals of all of said buses, the bridge portal associated with said one subsystem being a cycle monster portal.