Patent ID: 6566187
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method for fabricating a DRAM cell arrangementin which first trenches running essentially parallel to one another are produced in a substrate, in which the first trenches are filled with isolating structures, in which, by etching, with the aid of a strip-shaped photresist mask whose strips run transversely with respect to the first trenches, the substrate is etched selectively with respect to the isolating structures, with the result that depressions are produced, in which areas of lower regions of the depressions are provided with a capacitor dielectric, in which a storage node of a storage capacitor is in each case produced in the lower regions of the depressions, in which upper source/drain regions of the transistors are produced in a manner adjoining a main area of the substrate in such a way that they are in each case arranged between two mutually adjacent depressions of the depressions and between two mutually adjacent isolating structures of the isolating structures, in which at least first side walls of the depressions are provided with a gate dielectric in upper regions of the depressions, in which lower source/drain regions of the transistors are formed in the substrate in such a way that they are electrically connected to the storage nodes, with the result that in each case one of the transistors and one of the storage capacitors are connected in series and form a memory cell, in which, by depositing and patterning conductive material, word lines are produced, which run transversely with respect to the isolating structures and above the known area, and, adjoining them, gate electrodes of vertical transistors are produced, which are each arranged in one of the depressions and are electrically insulated from the storage nodes, in which insulating spacers are produced on the word lines by depositing material and etching it back, in which, with the aid of a strip-shaped photoresist mask whose strips run essentially parallel to the isolating structures, etching is effected selectively with respect to the insulation layer and the spacers until the upper source/drain regions are uncovered, in which bit lines are produced which mark contact with the upper source/drain regions, characterized in that firstly the upper region of the depressions is produced using a strip-shaped photoresist mask, whose strips run transversely with respect to the first trenches, in such a way that it has an essentially rectangular horizontal cross section, in which rounded auxiliary spacers are produced in the depressions by depositing material and anisotropically etching it back, in which the auxiliary spacers are rounded by an isotropic etching process, with the result that uncovered parts of bottoms of the depressions have a circumference without corners, in which the lower regions of the depressions are produced by anisotropic etching selectively with respect to the rounded auxiliary spacers.