Patent ID: 6104214
Filing Date: 2000-08-15
Classification: H03K

Abstract:
A current mode logic circuit comprising:a first NMOS transistor and a second NMOS transistor;a data input terminal connected to a gate of the first NMOS transistor to which data is inputted;a reference voltage input terminal connected to a gate of the second NMOS transistor to which a reference voltage is supplied;an output terminal connected to a drain of the first NMOS transistor or the second NMOS transistor; anda constant current source connected to both of sources of the first NMOS transistor and the second NMOS transistor,wherein a body terminal of the fist NMOS transistor is connected to the data input terminal and a body terminal of the second NMOS transistor is connected to the reference voltage input terminal so that a level of a body voltage of each of the first NMOS transistor and the second NMOS transistor is controlled.