Patent ID: 7359256
Filing Date: 2008-04-15
Classification: G11C

Abstract:
1. A semiconductor memory device for reducing a current consumption, comprising: a global data latch unit for latching a global data loaded on a global data line in response to a first write enable signal to thereby generate a global latch data; a local data write driving unit for receiving the global latch data to output a local data to a local data line in response to a second write enable signal; and a write driver control unit for generating the first write enable signal and the second write enable signal, wherein the first write enable signal is inactivated when a write operation is not performed, wherein the write driver control unit includes: an intermediate enable signal output unit for combining a bank flag signal to enable a bank for performing the write operation, a write flag signal activated if the write command is inputted, and a driver select signal for activating a selected write driver to generate an intermediate enable signal; a first write enable signal output unit for combining the intermediate enable signal and a write control signal for performing the write operation to generate the first write enable signal; and a second write enable signal output unit for combining the driver select signal and the write control signal to generate the second write enable signal.