Patent ID: 8508199
Filing Date: 2013-08-13
Classification: G05F

Abstract:
1. A circuit to limit the output load current of a current driven LDO voltage regulator, wherein said LDO voltage regulator comprises at least an error amplifier, a first pass transistor, a means to control said pass transistor using the output of said error amplifier and a feedback mechanism to feed a measure of the output voltage back to said error amplifier, is comprising: a second PMOS pass transistor, wherein its drain is connected to the drain of said first pass transistor, its gate is connected to the gate of said first pass transistor and to the gate of a first PMOS transistor in a diode configuration, and its source is connected to a first means providing resistance and to the source of a second PMOS transistor; said first means providing resistance, wherein its first terminal is connected to VDD voltage and a second terminal is connected to the source of said second PMOS pass transistor; said first PMOS transistor in a diode configuration, wherein its source is connected to V said second PMOS transistor in a diode configuration, wherein its gate is connected to its drain and to the gate of a third PMOS transistor, its source is connected to a second terminal of a second means providing resistance, and its drain is connected to a first terminal of a first current source; said first current source wherein its second terminal is connected to V said third PMOS transistor wherein its source is connected to the source of said second pass transistor and its drain is connected to a first terminal of a second current source and to a gate of a first NMOS transistor; said first NMOS transistor, wherein its source is connected to VSS voltage and its drain is connected to a second terminal of said means to control said first pass transistor; said second means providing resistance, wherein its first terminal is connected to VDD voltage; and said second current source wherein its second terminal is connected to V