Patent ID: 6238975
Filing Date: 2001-05-29
Classification: H01L

Abstract:
In a non-volatile memory comprising a region for core memory cells and a peripheral region on a substrate, the peripheral region including source and drain regions of at least one transistor, the source and drain regions of said at least one transistor separated by a channel region, a method for improving electrostatic discharge (ESD) robustness of the non-volatile memory comprising the steps of:(a) lightly doping the source and drain regions with a first dopant;(b) providing a double diffusion implant mask having an opening over the region for the core memory cells and an opening over the peripheral region; and(c) performing a double diffusion implantation through the opening over the peripheral region, the step of performing the double diffusion implantation comprising the steps of:(i) implanting a second dopant into the source and drain regions; and(ii) implanting a third dopant into the source and drain regions subsequent to the step of implanting the second dopant.