Patent ID: 8214662
Filing Date: 2012-07-03
Classification: G06F,Y02D

Abstract:
1. A multiprocessor control unit for controlling a power supply to a plurality of processors, which perform parallel execution of a plurality of first blocks obtained by dividing a first program block included in a program while performing barrier synchronization of the plurality of first blocks, and then perform parallel execution of a plurality of second blocks obtained by dividing a second program block continued from the first program block while performing barrier synchronization of the plurality of second blocks, the multiprocessor control unit comprising: an acquisition means for acquiring first non processing time information on a first non processing time represented for each processor, wherein the first non processing time represents a time in which a first block is not executed in a first barrier establishment time from barrier synchronization start until barrier synchronization establishment of the first program block, and acquiring second non processing time information on a second non processing time represented for each processor, wherein the second non processing time represents a time in which a second block is not processed in a second barrier establishment time from barrier synchronization start until barrier synchronization establishment of the second program block; and a power control means for controlling the power supply to the plurality of processors while the first and second program blocks are consecutively executed in parallel, using the first and second non processing time information acquired by the acquisition means, the power control means being operatively coupled to the acquisition means for receiving the first and second non processing time information, wherein the power control means controls execution start timing of the first and second blocks for each processor such that execution states of the first and second blocks are the same before and after the barrier synchronization start of the second program block, using the first and second non processing time information acquired by the acquisition means, and controls the power supply to the plurality of processors such that a processor not executing the first block or the second block is in a sleep state and a processor executing the first block or the second block is in an operation state before and after the barrier synchronization start of the second program block, and the power control means comprises: a power mode control means, in which a normal operation mode representing power for placing a processor into a normal operation state and a sleep mode representing power for placing the processor into a sleep state are preset, for setting a power mode of each processor to the normal operation mode or the sleep mode; and a transfer means for controlling supply of a clock signal or a supply voltage to each processor to transfer the power mode of each processor to the power mode set by the power mode control means, and regarding a processor which has completed the execution of the first block before the barrier synchronization establishment of the first program block, the power mode control means delays the execution start timing of the second block by the time represented by the second non processing time information from the barrier synchronization start of the second program block, and sets the power mode from the execution completion of the first block until the execution start of the second block to the sleep mode.