Patent ID: 8549368
Filing Date: 2013-10-01
Classification: G01R,G06F,G11C

Abstract:
1. A multi-core integrated circuit, comprising: a plurality of processor cores including first and second sets of processor cores, wherein the first and second sets of processor cores include: first and second TAP controllers connected to the first and second sets of processor cores respectively, and wherein the first and second TAP controllers connect the corresponding first and second sets of TAPs to corresponding first and second debug ports of the multi-core integrated circuit; and a control circuit, connected to the first and second debug ports and the plurality of processor cores, wherein the control circuit includes first and second configuration registers for receiving a configuration signal from at least one of the first and second debug ports, and wherein the first configuration register configures the first and second TAP controllers in a predetermined test mode and the second configuration register configures connection between the first and second debug ports and the first and second sets of processor cores.