Patent ID: 6124865
Filing Date: 2000-09-26
Classification: G06F,G09G

Abstract:
A computer system comprising:a main memory having memory locations identified by main memory addresses;a processor unit, coupled to the main memory, including a CPU for processing data stored in the memory locations;a CPU cache memory for storing the processed data; anda CPU cache tag store containing the main memory addresses of the processed data stored in the CPU cache memory;an input/output bus, coupled to the processor unit;a plurality of input/output devices connected to the input/output bus for issuing memory requests containing main memory addresses;a duplicate tag store, coupled directly to the input/output bus, having duplicates of the main memory addresses contained in the CPU cache tag store;means for comparing an address in one of the memory requests with the addresses in the duplicate tag store; andmeans, responsive to an address in said one of the memory requests matching an address in the duplicate tag store, for issuing an invalidate request to ensure that the most current value of the data is accessed.