Patent ID: 6097049
Filing Date: 2000-08-01
Classification: H01L,Y10S

Abstract:
A DRAM cell arrangement, comprising:a projection-like semiconductor structure, the semiconductor structure laterally limited by at least one first sidewall and one second sidewall lying opposite the first sidewall;a first source/drain zone arranged in the semiconductor structure;at least one vertical MOS transistor of a memory cell, a channel zone of the least one vertical MOS transistor arranged under the first source/drain zone and adjoining at least the first sidewall of the semiconductor structure;a gate dielectric provided in at least the first sidewall of the semiconductor structure at least in a region of the channel zone of the MOS transistor;a gate electrode that is electrically connected to a first word line adjoining the gate dielectric;an element arranged between the channel zone and a second word line, the element preventing the drive of the MOS transistor by the second word line and adjoining the second sidewall of the semiconductor structure;a first capacitor electrode of a capacitor electrically connected to the first source/drain zone of the MOS transistor; anda capacitor dielectric arranged above the first capacitor electrode and a second capacitor electrode of the capacitor arranged above the capacitor dielectric and being electrically connected to a bit line that proceeds transverse to the first word line.