Patent ID: 7913216
Filing Date: 2011-03-22
Classification: G06F

Abstract:
1. A method of estimating interconnect wire parasitics in integrated circuits comprising the steps of: obtaining a circuit layout having a plurality of circuit components placed thereon including a plurality of source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy; bubbling up of I/O pins until all I/O pins are on a same level of the circuit hierarchy, wherein bubbling up of I/O pins comprises: traversing the layout locating I/O pins on every net; determining a first I/O pin on a first level of the circuit hierarchy; determining all second I/O pins on a second level of the circuit hierarchy that electrically, connect to the first I/O pin: modifying the first I/O pin to be a plurality of first I/O pins equal to the number of second I/O pins; and moving the second I/O pins to the first level of the circuit hierarchy so that the second I/O pins and their connectivity to the first I/O pins are on the first level of the circuit hierarchy; and estimating by a computer processor interconnect segments to be employed in interconnecting at least some circuit components of the plurality of placed circuit components of the circuit layout.