Patent ID: 6678191
Filing Date: 2004-01-13
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device, comprising:a main memory cell array formed of a plurality of NAND cell strings, each cell string formed of a number of memory cell transistors; a sub memory cell array, separate from the main memory cell array, and having a plurality of NAND cell strings each formed from a number of memory cell transistors, the number of the memory cell transistors in the cell strings of the sub memory cell array less than the number of memory cell transistors in the NAND cell strings of the main memory cell array, the sub memory cell array being operationally connected to main bit lines of the main memory cell array during program and erase operations, the sub memory cell array being electrically disconnected from the main bit lines during a read operation, and the sub memory array having a separate read path that is independent from a read path of the main memory cell array.