Patent ID: 8825924
Filing Date: 2014-09-02
Classification: G06F,H04L

Abstract:
1. A computer array, comprising: a plurality of computers, each of said computers including a processor for executing instructions and a memory; and a plurality of bidirectional data paths connecting said computers, each of said data paths dedicated between a pair of said computers and including a read line, a write line, and a plurality of data lines; and wherein one of said data paths connects a first computer and a second computer; said first computer is configured to indicate its readiness to communicate with said second computer by asserting a first signal on one of said read line and said write line of said data path connecting said first computer and said second computer; said second computer is configured to indicate its readiness to communicate with said first computer by asserting a second signal on the other of said read line and said write line; said first computer and said second computer being configured such that when both said read line and said write line have signals asserted thereon, then data is transferred between said first computer and said second computer via said data lines of said data path connecting said first computer and said second computer; and further such that when said data is transferred between said first computer and said second computer, then said first signal and said second signal change; and the changing of said first signal and said second signal is an acknowledgement to at least one of said first computer and said second computer that said data has been successfully transferred between said first computer and said second computer.