Patent ID: 6546501
Filing Date: 2003-04-08
Classification: G06F

Abstract:
A cache memory apparatus comprising:a primary cache memory having at least one way, which way having at least one entry; an error detection unit which detects an error in an entry of the way; a secondary cache memory which holds data, a registration position information and a status information of data in said first cache memory; a replace prohibition unit which, when error is detected in an entry of a way by said error detection unit, prohibits that particular way from being replaced; a write back unit which, when an error is detected in an entry of a way by said error detection unit, writes back the data held in that particular entry of the way in said primary cache memory to an entry of said secondary cache memory; a release unit which releases the prohibition of replacement of that particular way of said primary cache memory upon completion of the write back operation by said write back unit; and a write unit which, when the entry of said secondary cache memory is accessed, writes the data which is written back in the entry in said primary cache memory.