Patent ID: 6240503
Filing Date: 2001-05-29
Classification: G06F

Abstract:
A processor comprising:a lookahead unit configured to detect a first instruction specifying a first register as storing an operand of said first instruction, wherein said look ahead unit is configured to generate a constant corresponding to said first instruction, and wherein said constant is indicative of a modification of a value stored into said first register in response to executing a previous instruction, said lookahead unit being configured to generate said constant as a sum of at least: (i) a cumulative offset stored in a storage location within said look ahead unit, said cumulative offset reflecting a cumulative modification of said value due to each instruction between said previous instruction and said first instruction and excluding said value, wherein at least one of said instructions between said previous instruction and said first instruction is dispatched at a first time previous to a second time at which said first instruction is dispatched; and (ii) a modification due to said first instruction, if said modification occurs prior to use of said operand by said first instruction; anda second unit coupled to said look ahead unit, wherein said second unit is configured to combine said constant with said value to generate said operand.