Patent ID: 6388283
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A semiconductor memory configuration, comprising:a substrate with a substrate surface and a trench formed therein; a plurality of memory cells in said substrate, each of said memory cells including a selection transistor, a trench capacitor, and a storage elecrode formed by a substrate region along a trench wall of said trench, said plurality of said memory cells configured in cell rows running in a first direction; a conductive layer inside said trench defining a cell plate forming a common opposing electrode for a number of said plurality of memory cells, said cell plate having a plurality of strips on said surface of said substrate said plurality of said strips being not connected to each other; a gap defined by a region between two neighboring pairs of said plurality of said memory cells; and a respective bit line contact being provided for two adjacent cells of two neighboring pairs of said plurality of said memory cells running in said first direction; said plurality of strips of said cell plate running in a second direction that is at a non-zero angle with respect to said first direction; said memory cells arranged in cell rows in a first direction, parallel to a bit line direction, said cell plate strips running in the first direction, said cell plate strips each connecting respective capacitors of two adjacent cell rows; and said memory cells having a given length, two respectively adjacent memory cells arranged with mirror-image symmetry with respect to one another in each cell row, mutually adjacent cell rows being offset from one another by the given length of a memory cell.