Patent ID: 6165656
Filing Date: 2000-12-26
Classification: G03F,Y10S

Abstract:
An overlay error determination mark comprising:a semiconductor device formation region provided for forming at different layers on a semiconductor substrate a plurality of patterns of predetermined configurations forming a semiconductor device;an overlay error determination mark formation region for determining an overlay error between said different layers forming said semiconductor device;a first semiconductor device component member located in said semiconductor device formation region and formed at a first layer;a first determination mark located in said overlay error determination mark formation region and formed at said overlay error determination mark formation region in the same manufacturing step as said first semiconductor device component member;a second semiconductor device component member located in said semiconductor device formation region and formed at a second layer on said first layer; anda second determination mark located in said overlay error determination mark formation region and formed in the same manufacturing step as said second semiconductor device component member for determining an overlay error between said first semiconductor device component member and said second semiconductor device component member, whereinsaid first determination mark has a pattern receiving the same influence of aberration as that exerted by irradiation of light to said first semiconductor device component member, andsaid second determination mark has a pattern receiving the same influence of aberration as that exerted by irradiation of light to said second semiconductor device component member.