Patent ID: 8298919
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a principal surface, a back surface opposite the principal surface; a device region formed on the principal surface; and a scribe region disposed around the device region, wherein the device region includes a plurality of semiconductor elements formed on the principal surface, a first insulating layer formed so as to cover the semiconductor elements, an uppermost wiring layer formed over the first insulating layer, a plurality of terminals formed on the uppermost wiring layer and electrically coupled to the semiconductor elements, and a second insulating layer formed so as to cover the uppermost wiring layer and having a plurality of openings from which each of the terminals is exposed, wherein the scribe region includes the first insulating layer formed over the principal surface, a first metal pattern formed on the uppermost wiring layer, and the second insulating layer formed so as to expose a side surface of the first metal pattern at an end of the semiconductor substrate and to cover the entire upper surface of the first metal pattern, wherein a plurality of wiring layers is formed between the principal surface and the uppermost wiring layer, wherein the device region includes a second metal pattern formed by connecting respective wiring layers from the principal surface to the uppermost wiring layer so as to surround a region in which the terminals are formed, wherein the second insulating layer is formed over the second metal pattern so as to cover the upper surface of the second metal pattern, wherein the first metal pattern and the second metal pattern are electrically spaced apart from each other, wherein a trench is formed between the second insulating layer of the device region and the second insulating layer of the scribe region, wherein the second insulating layer of the device region is separated from the second insulating layer of the scribe region, and wherein an interval from an end of the trench on a scribe region side to an end of the first metal pattern is shorter than an interval from an end of the trench on a device region side to an end of the second metal pattern.