Patent ID: 6687851
Filing Date: 2004-02-03
Classification: G06F

Abstract:
A fault-tolerant computer system including:A. an on-line CPU; B. an off-line CPU; C. an I/O subsystem that communicates with the on-line and off-line CPUs; and D. an I/O subsystem manager that controls a synchronization operation in which the off-line CPU is synchronized to on-line CPU, the I/O system manager directing i. the on-line CPU to provide component state information to the I/O subsystem, ii. the I/O subsystem to provide the component state information to the off-line CPU, and iii. the off-line CPU to set corresponding components to the specified states, the I/O system manager controlling the time at which the off-line CPU is brought on-line to operate in lock-step with the on-line CPU by directing each of the CPUs to a known operating state before bringing the off-line CPU on-line.