Patent ID: 7817476
Filing Date: 2010-10-19
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: an array of memory cells; a set of read/write circuit stacks for operating on a group of memory cells of said array in parallel; each stack of read/write circuits operating on a subgroup of memory cells in parallel, comprising: a subgroup of sense amplifiers and data latches cooperating with a processor; said data latches latching input or output data of said subgroup of sense amplifiers; each sense amplifier having at least one node with sense amplifier data; said processor coupled to said at least one node with sense amplifier data and said data latches for processing data therebetween; and wherein said processor further comprising: an input logic selectively coupled to either said at least one node with sense amplifier data or said data latches to retrieve data therefrom, and responsive to a first set of control signals to generate first resultant data; and an output logic responsive to a second set of control signals and said first resultant data to generate second resultant data, said processor selectively coupled to either said at least one node with sense amplifier data or said data latches to store said second resultant data thereto.