Patent ID: 7747908
Filing Date: 2010-06-29
Classification: G06F

Abstract:
1. A computer-implemented method comprising: performing a first execution round, wherein the first execution round includes executing a first test pattern on a first processor and executing a second test pattern on a second processor, resulting in a first set of bus contentions; performing a second execution round, wherein the second execution round includes executing the second test pattern on the first processor and executing the first test pattern on the second processor, resulting in a second set of bus contentions; and testing a bus coupled to the first processor and the second processor based upon the first set of bus contentions and the second set of bus contentions, wherein the first set of bus contentions are different than the second set of bus contentions; and determining, based upon the testing, whether a bus arbitrator resolved the first set of bus contentions and the second set of bus contentions; and setting an error flag in response to determining that the bus arbitrator did not resolve the first set of bus contentions and the second set of bus contentions.