Patent ID: 6140171
Filing Date: 2000-10-31
Classification: H01L,Y10S

Abstract:
A method for fabricating a FET device which comprises providing a semiconductor substrate; forming source and drain diffusion regions in said semiconductor substrate; forming a gate electrode on said semiconductor substrate overlapping said source and drain diffusion regions; providing a gate insulating layer located between said gate and said substrate; forming a first dielectric layer on at least one sidewall of said gate and a second and different sidewall spacer layer on the first dielectric layer wherein the second spacer layer is a parylene coating; forming a barrier layer, on at least one of the diffusion layers, abutting the second dielectric layer; removing the second spacer layer including exposing a portion of said at least one of the diffusion regions beneath said second dielectric layer; and forming a sidewall spacer conductor on the first dielectric layer contacting the exposed portion of said at least one of the diffusion regions.