Patent ID: 6272615
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A data processing device, comprising:a central processing unit (CPU) with an instruction register operable to hold an instruction, wherein the CPU is operable to process a data word in response to the instruction;an index register connected to the CPU and operable to provide a first address in response to the instruction; andaddress circuitry connected to the CPU and operable to form a memory address of the data word by selecting a first portion of the first address from the index register and combining the first portion of the first address with a first portion of an immediate field selected from the instruction, such that the first portion of the immediate field is a most significant address portion with the first portion of the first address as a least significant address portion, wherein the first portion of the immediate field has a first width and the first portion of the first address has a second width.