Patent ID: 7250628
Filing Date: 2007-07-31
Classification: H01L

Abstract:
1. A memory device comprising: a transistor having a gate supported by a crystalline layer and having a pair of source/drain regions proximate the gate; the crystalline layer comprising a material which includes silicon and germanium; the transistor having an active region; at least a portion of the active region being within the material; the active region within the material being contained within a single crystal of the material, the transistor being an NFET device, and the source/drain regions comprising n+ implant regions extending into the crystalline layer; a thyristor electrically connected with one of the source/drain regions; the thyristor having a cathode which electrically contacts and is directly over the n+ implant region of said one of the source/drain regions; the thyristor being a p+/n/p/n+ thyristor; the cathode being a vertically-extending n+ pillar; the p+/n/p portion of the thyristor having no region directly over the n a thyristor gate over the p portion of the p+/n/p/n+ thyristor.