Patent ID: 6098154
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A central processing unit of a computer, comprising:a data cache for storing data specified by an address request of a first instruction;a prefetch cache for generating a prefetch cache hit signal in response to said address request; anda prefetch engine for deriving in response to said prefetch cache hit signal, a prefetch address which specifies data predicted to be requested in one or more instructions subsequent to said first instruction, wherein said prefetch engine includes:an adder to add a stride to a physical address of said data specified by said address request;first and second input ports coupled to simultaneously receive from said prefetch cache first and second physical addresses, respectively; andfirst and second output ports for providing first and second prefetch addresses to a memory external to said central processing unit, said first and second prefetch addresses derived from said first and second physical addresses, respectively.