Patent ID: 6376298
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing a pair of gate electrodes and associated source and drain regions overlying a semiconductor substrate wherein nitride spacers are formed on sidewalls of said gate electrodes; depositing a poly-cap layer overlying said gate electrodes and source and drain regions; selectively removing said poly-cap layer overlying one of said source and drain regions between said gate electrode pair where a self-aligned contact is to be formed and removing said poly-cap layer over a first one of said gate electrode pair; depositing an insulating layer over the surface of said semiconductor substrate; forming said planned self-aligned contact opening through said insulating layer to said one of said source and drain regions wherein said contact opening partially overlies said poly-cap layer over a second one of said pair of gate electrodes; and filling said self-aligned contact opening with a conducting layer to complete the fabrication of said integrated circuit device.