Patent ID: 6425054
Filing Date: 2002-07-23
Classification: G06F

Abstract:
An integrated digital signal processor comprising:a processing core that includes a first processor and a cache system having a cache control, wherein the first processor accesses an address space via the cache system; a first plurality of different types of devices coupled to at least a first interface for accessing a first device that is external to the integrated digital signal processor; a first bus that directly connects the cache system to the first plurality of different types of devices, wherein the first interface and the first bus operate at a first clock frequency; a second plurality of different types of devices coupled to at least a second interface for accessing a second device that is external to the integrated digital signal processor; and a second bus that directly connects the cache system to the second plurality of different types of devices, the second interface and the second bus operating at a second clock frequency that differs from the first clock frequency, wherein the cache control of the cache system serves as a switchboard for communication between the first processor and any of the first plurality of different types of devices and between the first processor and any of the second plurality of different types of devices.