Patent ID: 6542956
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays, comprising:a plurality of address latches, a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays, means for storing subarray addresses into selected ones of said plurality of address latches, and storing data to be written into subarray locations indicated by said subarray addresses, into selected ones of said plurality of data registers, and means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches; wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides, and said storing means includes means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits.