Patent ID: 8981482
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A device used as an ESD protection structure, comprising: a P-type substrate ( 10 ); a P-type well ( 12 ), formed in the P-type substrate ( 10 ); a gate ( 14 ), formed on the P-type well ( 12 ); an N-type lightly doped region ( 11 ) formed in the P-type well ( 12 ), the N-type lightly doped region ( 11 ) having a first end under the gate ( 14 ); a source and a drain, respectively formed by a first N-type heavily doped region ( 162 ) in the P-type well ( 12 ) at a first end of the gate and a second N-type heavily doped region ( 23 ) in the N-type lightly doped region ( 11 ) between a second end of the gate and a second end of the N-type lightly doped region ( 11 ); a first isolation structure ( 131 ), formed in the P-type well ( 12 ) and on one side of the source away from the gate; a first P-type heavily doped region ( 161 ), formed between the first isolation structure ( 131 ) and the first N-type heavily doped region ( 162 ); a second isolation structure ( 133 ), formed in the N-type lightly doped region ( 11 ) and under the second end of the gate ( 14 ); a third isolation structure ( 134 ), partly or entirely formed in the N-type lightly doped region ( 11 ) and on one side of the drain away from the gate ( 14 ); a third N-type heavily doped region ( 21 ) and a second P-type heavily doped region ( 22 ), formed in the N-type lightly doped region ( 11 ) and between the second end of the gate and the drain, wherein the second P-type heavily doped region ( 22 ) is formed between the third N-type heavily doped region ( 21 ) and the drain, and the first P-type heavily doped region ( 161 ) and the first N-type heavily doped region ( 162 ) are grounded, the gate ( 14 ) is connected to an interior circuit, and the second P-type heavily doped region ( 22 ) and the second N-type heavily doped region ( 23 ) are connected to an input/output bonding pad.