Patent ID: 7337260
Filing Date: 2008-02-26
Classification: G06F

Abstract:
1. A bus system comprising: a common control command bus commonly connecting control command lines of a plurality of buses having data lines of different bit widths, said common control command bus transmitting the same command data as a portion of the command data transmitted by the control command lines of the plurality of buses; and data converting means to which data lines of said plurality of buses are connected, for performing conversion of bit width between said data lines of different bit widths, for performing conversion of bit width between a plurality of buses having different bit widths in the same bus cycle, the common control command bus bypassing the data converting means, which further comprises a master side interface means including: a bus command buffer holding address indicative of the bus slave unit and command from the external master unit; first multiplexer means for controlling output of address and command from said bus command buffer and identification information indicative of the master side interface means to the common control command bus; a bus write data buffer holding a part or all of write data from said external master unit; second multiplexer means for controlling output of write data from said bus write data buffer to the bus; a bus read data buffer for holding a part or all of read data from the bus; timing control means for outputting a transfer start signal in response to a transfer request signal from the external master unit and outputting a completion signal to said external master unit; comparing means for detecting matching of identification information indicative of said master side interface means and identification information from the bus; and a bus master control circuit responsive to detection of matching in said comparing means to output the arbitration request signal, upon reception of the arbitration grant signal, controlling said first multiplexer means for outputting to the common control command bus and outputting a write permission signal to permit writing of the read data from the but to said bus read data buffer, responsive to said transfer start signal from said timing control circuit, to permit said second multiplexer to read the write data from said bus write data buffer to the bus.