Patent ID: 6462998
Filing Date: 2002-10-08
Classification: G11C,H01L

Abstract:
In an integrated circuit including a latch circuit for sensing and latching, at a particular time when enabled by a latch enable signal, a differential signal that increases in magnitude over a period of time, a latch timing circuit comprising:an input terminal for receiving an input timing signal; an output terminal for conveying an output timing signal for controlling the timing of the latch enable signal; a delay circuit coupled between the input terminal and the output terminal, said delay circuit providing a plurality of different delay times through the delay circuit; at least one configuration input terminal for receiving an electrical configuration signal for selecting one of the plurality of different delay times through the delay circuit, such that the latch enable signal is electrically configurable to occur, after receiving the input timing signal, at one of a plurality of various times corresponding to various magnitudes of the differential signal; and at least one programmable device responsive to a programming stimulus for selecting one of the plurality of different delay times through the delay circuit, such that the latch enable signal is programmable to occur, after receiving the input timing signal, at one of the plurality of various times corresponding to various magnitudes of the differential signal.