Patent ID: 9196365
Filing Date: 2015-11-24
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a string wherein the string comprises a first dummy memory cell and a second dummy memory cell, wherein the string comprises a drain select transistor, first and second drain side dummy memory cells, a plurality of memory cells, first and second source side dummy memory cells, and a source select transistor; a circuit configured to provide a program voltage and one or more operation voltages to the string during a program operation; and control logic configured to control the circuit to increase a first threshold voltage of the first dummy memory cell and to increase a second threshold voltage of the second dummy memory cell, wherein the circuit turns off the first drain side dummy memory cell and the first source side dummy memory cell adjacent to the plurality of memory cells and generates a gate-induced drain leakage current after channels of the string are precharged, wherein the first threshold voltage and a second threshold voltage increase by a hot carrier injection mechanism.