Patent ID: 6665208
Filing Date: 2003-12-16
Classification: G11C

Abstract:
A semiconductor integrated circuit device, characterized in that said device comprises a memory circuit including:a plurality of word lines and plurality of pairs of complementary bit lines: a plurality of memory cells which are provided at the intersections between said plurality of word lines and said plurality of pairs of the bit lines; a first select switch circuit for connecting said pairs of the complementary bit lines to pairs of complementary writing signal lines; a second select switch circuit for connecting said pairs of complementary bit lines to pairs of complementary reading signal lines; a sense amplifier including a latch circuit having an input and output coupled to one of said pairs of complementary reading signal lines, which is activated in response to an operation timing signal; and a comparing circuit for comparing the read signal which is amplified by said sense amplifier with a signal to be written which is transmitted to one of said pairs of complementary writing signal lines; in which a signal to be written is transmitted to said one of said pairs of complementary writing signal lines in parallel with an address input operation for the selection of a word line which is connected to one of said memory cells; information stored in the memory cell selected in response to the selection operation of said word line being transmitted to said pair of complementary reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier; and the amplified output of said sense amplifier being compared with the signal to be written on said pair of complementary writing signal lines so that the signal to be written which is transmitted to said pair of complementary writing signal lines is written into said selected memory cell by selectively turning on said first selecting switch circuit in response to a result of said comparison.