Patent ID: 6535415
Filing Date: 2003-03-18
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a plurality of word lines, a plurality of data lines, and a plurality of DRAM memory cells; a plurality of sense amplifiers coupled to said plurality of data lines and each receiving operating voltage from first and second nodes; a first line connected to said first nodes; a second line connected to said second nodes; a first drive for coupling said first line with a first potential; and a second drive for coupling said second line with a second potential; wherein said first drive sets up a connection between the first potential and said first line at a first impedance in a first operation mode and a connection between the first potential and said first line at a second impedance higher than the first impedance in a second operation mode, wherein said second drive sets up a connection between the second potential and said second line at a third impedance in the first operation mode and a connection between the second potential and said second line at a fourth impedance higher than the third impedance in the second operation mode, wherein a change from the first operation mode to the second operation mode occurs after a first time from a row active command.