Patent ID: 8432201
Filing Date: 2013-04-30
Classification: H03L

Abstract:
1. A phase-locked loop (PLL) for generating an oscillator signal, comprising: a phase-frequency detector (PFD) for generating an error signal based on an input reference signal and a feedback signal; a charge pump, connected to the PFD, for generating a charge pump current based on the error signal; a low pass filter having an input terminal connected to the charge pump, for generating a control voltage based on the charge pump current; a voltage-controlled oscillator (VCO), connected to an output terminal of the low pass filter, for generating the oscillator signal based on the control voltage; a frequency divider, connected between the VCO and the PFD, for generating the feedback signal by adjusting a frequency of the oscillator signal; a capacitor having a first terminal connected to the output terminal of the low pass filter and a second terminal connected to ground, wherein the capacitor is charged to about a voltage level of the control voltage by the low pass filter; and a buffer amplifier having an input terminal connected to the first terminal of the capacitor and an output terminal connected to the input terminal of the low pass filter, for buffering a voltage across the capacitor; wherein, the voltage across the capacitor is provided to the low pass filter when the PLL transitions from a STOP mode to a RUN mode, to reduce time taken by the VCO to generate the oscillator signal.