Patent ID: 7016984
Filing Date: 2006-03-21
Classification: G06F

Abstract:
1. A transfer controller which is connected to a plurality of CPUs and a plurality of memory devices or IO devices, said controller, comprising: transfer means for transferring an instruction from a CPU to a destination device and for transferring read data from the destination device to the CPU when the instruction is a read instruction, the read data being transferred at time separate from the time of transferring the corresponding read instruction; holding means for holding information associated with a CPU which issues a new instruction and information associated with a destination device of the new instruction, and for holding information associated with a CPU which issues an instruction which is suspended and information associated with a destination device of the suspended instruction; and order control means for controlling said transfer means to transfer a plurality of read data in accordance with an order of transferring the corresponding read instructions based on held contents of said holding means.