Patent ID: 6111444
Filing Date: 2000-08-29
Classification: H03K

Abstract:
A latch having first and second pre-chargeable nodes and receiving inputted data and a complement of said inputted data comprising:circuitry, coupled to said first pre-chargeable node, for selectively evaluating said inputted data in response to a first binary signal and a voltage level on said second pre-chargeable node, wherein the circuitry for selectively evaluating said inputted data comprises:a first NFET, said first NFET comprising a gate electrode coupled to said second pre-chargeable node, a first electrode coupled to a voltage potential and a second electrode;a second NFET, said second NFET comprising a gate electrode receiving said first binary signal, a third electrode coupled to said second electrode and a fourth electrode; anda third NFET, said third NFET comprising a gate electrode receiving said inputted data, a fifth electrode coupled to said fourth electrode and a sixth electrode coupled to said first pre-chargeable node.