Patent ID: 6060758
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A device for suppressing parasitic effects in an integrated circuit formed on a substrate of semiconductor material of a first conductivity type, said device comprising:junction isolation regions;at least one region of a second conductivity type opposite the first conductivity type, delimited by first portions of a first major surface of the substrate and by said junction-isolation regions;first electrical contact means with the substrate on second portions of the first major surface outside of said junction-isolation regions;second electrical contact means on the at least one region of second conductivity type; anda reference terminal for the integrated circuit;third electrical contact means on a second major surface of the substrate opposite the first major surface, being connected to the reference terminal of the integrated circuit;first circuit means connected to said second electrical contact means for monitoring a potential thereof and for detecting if this potential departs from a potential of the reference terminal by an amount greater than a predetermined threshold value; andsecond circuit means connected to the first and second contact means and to the first circuit means for connecting the first electrical contact means to the reference terminal if the detected potential is within the predetermined threshold value, and connecting the first electrical contact means to the second electrical contact means if the detected potential is greater than or equal to the predetermined threshold value.