Patent ID: 6723645
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method of forming a metal wiring in a semiconductor device, the method comprising:providing a substrate with a lower metal layer overlying the substrate and an interlayer insulating film comprising first, second and third insulating films formed on the lower metal layer; forming a damascene pattern comprising a trench and a via on the interlayer insulating film, a portion of the second insulating film forming a bottom of the trench, a portion of the lower metal layer forming a bottom of the via, the trench and the via each comprising a sidewall; forming diffusion prevention film spacers on the sidewalls of the trench and the via; selectively forming chemical enhancer layer on the portion of the second insulating film forming the bottom of the trench and on the portion of the lower metal layer forming the bottom of the via; forming a copper layer on the diffusion prevention film spacer and chemical enhancer layers by means of chemical vapor deposition method; and performing a hydrogen reduction annealing and a chemical mechanical polishing process to form a copper metal wiring from the copper layer.