Patent ID: 6412087
Filing Date: 2002-06-25
Classification: G01R

Abstract:
A pattern data transfer circuit having tester channels and pattern data for measurement assigned to respective pins of a device under test, said tester channels being divided into pin groups for every attribute, common pin groups having a common pattern in which all the pattern data of all the pins in the pin group are common, pattern memories provided for each of the tester channels to which the respective pattern data corresponding to the respective tester channels is transferred, said pattern data transfer circuit further comprising:pin group data generating means for generating pin group data representing all the tester channels assigned to the respective pins in the common pin groups on the basis of the assignment of the respective tester channels relative to the pins; and transfer means for extracting the common patterns among the pattern data assigned to the common pin group, and in parallel and simultaneously transferring the extracted common patterns to all the pattern memories corresponding to the respective tester channels represented by the pin group data.