Patent ID: 7392447
Filing Date: 2008-06-24
Classification: G01R,G06F,Y02D

Abstract:
1. A method of using scan chains and boundary scan for power saving, in a synchronous logic ASIC having scan chains and boundary scan circuits wherein a controller is embedded for letting org_s_mode, org_s_enable, org_bs_mode, org_bs_enable, power_off, clock and reset signals of the scan chains and boundary scan circuits to be inputted into the controller and generate a new set of control signals of s_mode, s_enable, bs_mode, bs_enable, pw_switch, scan_clock, bs_clock, mem_if to control the scan chains and boundary scan circuits, the method comprising: (a) during power-off of the synchronous logic ASIC: (b) during power-on of the synchronous logic ASIC: