Patent ID: 7648880
Filing Date: 2010-01-19
Classification: H01L

Abstract:
1. A method of fabricating a double-gate field effect transistor comprising the steps of: providing a structure which includes at least a doped back-plane region, a back-gate dielectric stack including at least a bottom back-gate nitride formed atop said doped back-plane region, a Si-containing layer having edges formed atop said back-gate dielectric stack, a front gate dielectric formed atop said Si-containing layer, and a front gate formed atop said front gate dielectric, said structure having isolation trench regions adjacent to at least said doped back-plane region; forming insulating spacers on exposed vertical sidewalls of said front gate; forming protective spacers on said structure about said insulating spacers and coveting said edges of said Si-containing layer; forming isolation regions in regions of said structure which are adjacent to, and overlaying a portion of said doped back-plane region, whereby said protective spacers and said bottom back-gate nitride protect said Si-containing layer from oxidizing; removing said protective spacers exposing said edges of said Si-containing layer; and selectively growing Si-containing regions above and in contact with said edges.