Patent ID: 6660598
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method of forming a sub-0.05 &mgr;m channel length fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device comprising the steps of:forming at least one dummy gate region atop a silicon-on-insulator (SOI) layer, said dummy gate region comprising at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of said sacrificial polysilicon region; forming an oxide layer that is coplanar with an upper surface of said dummy gate region; removing said sacrificial polysilicon region to expose a portion of the SOI layer; forming a thinned device channel region by utilizing at least an etching step in said exposed portion of the SOI layer, said etching step comprising chemical down stream etching, reactive ion etching or thermal oxidation and reactive-ion etching; forming inner nitride spacers on exposed walls of said first nitride spacers; forming a gate region over said thinned device channel region; and removing said oxide layer so as to expose thicker portions of said SOI layer than said device channel region.