Patent ID: 6741517
Filing Date: 2004-05-25
Classification: G11C

Abstract:
A RAM array comprising:a RAM cell including a first access transistor driven by a first word line, said first access transistor coupling said RAM cell to a first bit line, said first bit line being connected to a first single-ended sense amplifier, said first access transistor being connected to a first node of said RAM cell; said RAM cell including a second access transistor driven by a second word line, said second access transistor coupling said RAM cell to a second bit line, said second bit line being connected to a second single-ended sense amplifier, said second access transistor being connected to said first node of said RAM cell; said RAM cell including a third access transistor driven by a third word line, said third access transistor coupling said RAM cell to a third bit line, said third bit line being connected to a third single-ended sense amplifier, said third access transistor being connected to a second node of said RAM cell; said RAM cell including a fourth access transistor driven by a fourth word line, said fourth access transistor coupling said RAM cell to a fourth bit line, said fourth bit line being connected to a fourth single-ended sense amplifier, said fourth access transistor being connected to said second node of said RAM cell; wherein said first, second, third, and fourth word lines are coupled only to respectively said first, second, third, and fourth access transistors in said RAM cell, wherein data can be read simultaneously at respective outputs of said first, second, third, and fourth single-ended sense amplifiers by enabling respectively said first, second, third, and fourth access transistors.