Patent ID: 6240505
Filing Date: 2001-05-29
Classification: G01R,G06F

Abstract:
A system comprising:A. a first memory device having address leads and data leads, the first memory device producing data signals on the data leads in a first time after occurrence of address signals received on the address leads;B. a second memory device having address leads and data leads, the second memory device producing data signals on the data leads in a second time after occurrence of address signals received on the address leads;C. a microprocessor having address leads sending address signals and having data leads at least receiving data signals, the microprocessor being capable of receiving data signals on the data leads in a third time after the occurrence of address signals on the address leads, the third time being less than at least the first time, and the microprocessor including a first register connected to the data leads and containing a first number received from the data leads indicating a first number of wait states to be inserted between the occurrence of the address signals on the microprocessor address leads and the third time to result in a fourth time that is greater than the first time; andD. address leads connecting the address leads of the first and second memory devices to the address leads of the microprocessor and data leads connecting the data leads of the first and second memory devices to the data leads of the microprocessor.