Patent ID: 9214565
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a source electrode layer and a drain electrode layer; an oxide semiconductor layer comprising a first impurity region, a second impurity region, and a channel formation region sandwiched between the first impurity region and the second impurity region, wherein a side surface of the first impurity region is in contact with and under the source electrode layer in a channel-length direction and a side surface of the second impurity region is in contact with and under the drain electrode layer in the channel-length direction; a gate insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the channel formation region; a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer, wherein at least part of the second portion overlaps with one of the source electrode layer and the drain electrode layer; and a sidewall insulating layer in contact with an outer side surface of the first portion and an upper surface of the second portion, wherein the sidewall insulating layer is not in contact with the gate electrode layer.