Patent ID: 6678786
Filing Date: 2004-01-13
Classification: G11C

Abstract:
A synchronous content addressable memory (CAM) device comprising:a CAM array having a plurality of first CAM cells and a second CAM cell; a comparand storage element coupled to the CAM array and configured to receive comparand data; an instruction decoder coupled to the CAM array and configured to receive a compare instruction, wherein the instruction instructs the CAM device to compare the comparand data with the plurality of first CAM cells; a sensing circuit coupled to the CAM array and configured to sense data from the second CAM cell, wherein the second CAM cell corresponds to one of the plurality of first CAM cells storing data matching the comparand data; an output port coupled to the sensing circuit; a clock input coupled to the instruction decoder and configured to receive a clock signal; and timing means, responsive to the clock signal and the compare instruction, for timing execution of the compare instruction and causing the sensed data to be output from the output port.