Patent ID: 6774700
Filing Date: 2004-08-10
Classification: H04L

Abstract:
An electrical circuit for generating a differential data signal and a squelch state over a differential signal pair, the differential signal pair having a positive signal line and a negative signal line, the circuit comprising:a current-mode logic (CML) buffer having a true data input, a true data output and a complementary data output, the true data output driving the positive signal line, the complementary data output driving the negative signal line, the data input being driven by a data input signal; and a CML multiplexer having a first and second true data inputs, an input selector, a true data output and a complementary data output, the first true data input being driven by the data input signal, the second true data input being driven by a logical inversion of the data input signal, the input selector being driven by a squelch state signal, the true data output being coupled with the true data output of the CML buffer, and the complementary data output being coupled with the complementary data output of the CML buffer.