Patent ID: 8288847
Filing Date: 2012-10-16
Classification: H01L

Abstract:
1. A dual die semiconductor package, comprising: a substrate with a grid array of electrical contacts on a bottom surface thereof; a first semiconductor die with a base surface mounted to an upper surface of the substrate, the first semiconductor die having a plurality of first die upper surface external electrical connection pads on an upper surface thereof that are electrically connected to respective ones of said electrical contacts of the grid array; a lead frame including a flag and a plurality of leads; a second semiconductor die with a base surface mounted to an upper surface of the lead frame flag, the second semiconductor die having second die upper surface external electrical connection pads on an upper surface thereof; wherein at least one of the leads of the plurality of leads is electrically connected to at least one of said second die upper surface external electrical connection pads; wherein the substrate is mounted to the lead frame flag, and the lead frame flag has a slot therein for allowing the electrical contacts of the grid array to pass therethrough; and a package body at least partially enclosing the first semiconductor die and the second semiconductor die, wherein the electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections, and wherein at least part of a base surface of the lead frame flag is left exposed by the package body.