Patent ID: 6349372
Filing Date: 2002-02-19
Classification: G06F,Y10S

Abstract:
A system for reducing data access time in a computer system with main memory compression, in which the unit of compression is a memory segment, the system comprising:a common memory area for storing uncompressed data and compressed data segments, said common memory area including a virtual uncompressed cache for storing data segments recently accessed by said computer system in uncompressed form at random locations in said common memory; directory structure stored in main memory having entries for locating both uncompressed data segments and compressed data segments in response to cache miss operations, wherein CPU generated real memory addresses are translated into one or more physical memory locations using said directory structure, each said directory entry including a first bit flag for indicating compressed or uncompressed status of said data segment, and for each uncompressed data segment, said directory entry further including a second bit flag for indicating membership of said uncompressed data segment in said virtual uncompressed cache; control means for accessing said directory entries and checking status and membership indication of a data segment to be accessed for said cache miss operation, and enabling processing of said data segment from said common memory area according to said status and membership indication, said control means for checking status and membership including means for maintaining a set of directory indexes, each index corresponding to a previously accessed uncompressed data segment currently stored in said virtual uncompressed cache, said control means checking said first and second bit flags to determine membership of an uncompressed data segment in said set of indexes and access status of said uncompressed data segment, whereby latency of data retrieval is reduced by storing said recently accessed data segments once in uncompressed form in said virtual uncompressed cache.