Patent ID: 6624057
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A method of making gate structures on a substrate assembly, the method comprising:forming a gate oxide layer on a substrate assembly; forming a first barrier layer on said gate oxide layer; forming a second barrier layer on said first barrier layer; forming a first silicon layer on said second barrier layer; forming a gate stack from the first silicon layer and said first and second barrier layers including a portion of each of said first silicon layer and said first and second barrier layers, each said portion having a width parallel to the width of each other portion, the width of the portion of the first silicon layer in the gate stack being equal to the width of the first barrier layer in the gate stack, and the width of the portion of the second barrier layer in the gate stack being less than the widths of each said portion of the first silicon layer and the first barrier layer in the gate stack; forming a silicon spacer upon the gate oxide layer in the gate stack, said silicon spacer being in contact with laterally exposed surfaces of the first silicon layer and the first and second barrier layers in the gate stack; forming a contact to an exposed surface on the first barrier layer in the gate stack through the first silicon layer leaving a first and second gate top of said first silicon layer in said gate stack, each of the first and second gate tops projecting from the silicon spacer toward the other parallel to the plane of the substrate assembly and being separated at least by the width of the portion of the second barrier layer within said gate stack; removing all of each said portion of the first and second barrier layers within the gate stack so as to expose the gate oxide layer on the substrate assembly and leaving a first and second gate bottom of said silicon spacer in said gate stack, each said first and second gate bottom projecting towards the other upon the gate oxide layer and being separated at least by the width of the portion of the second barrier layer removed from within said gate stack; forming a refractory metal silicide layer in contact with exposed surfaces of the silicon spacer, the first and second gate tops, and the first and second gate bottoms; forming active regions within the substrate assembly between the first and second gate bottoms and adjacent thereto; forming a passivation layer over the substrate assembly; forming an electrically conductive contact plug extending through said passivation layer, above said first and second gate tops, and to the gate oxide layer between the first and second gate bottoms on the substrate assembly, said electrically conductive contact plug being electrically insulated by said passivation layer from the first and second gate bottoms and the first and second gate tops; and forming an electrically conductive metallization line over and in electrical contact with the electrically conductive contact plug.