Patent ID: 7358590
Filing Date: 2008-04-15
Classification: B82Y,G11C,H01L,Y10S

Abstract:
1. A semiconductor device comprising: a plurality of memory elements; and a partition formed between adjacent memory elements, wherein the memory elements each have a stacked structure of a first conductive layer, a layer including an organic compound and a second conductive layer, wherein the memory elements each have a bubble generation area, wherein the layer is formed over the first conductive layer and the partition, wherein the second conductive layer is formed over the layer and the partition, and wherein a bubble is generated between the first conductive layer and the second conductive layer from the bubble generation area, by applying a voltage to the first conductive layer and the second conductive layer, and short-circuiting is caused between the first conductive layer and the second conductive layer by a pressure caused by the generated bubble to write data in the memory element.