Patent ID: 8169839
Filing Date: 2012-05-01
Classification: G06F,G11C,Y02D

Abstract:
1. A memory device for use with a host processor and a primary power source, the memory device comprising: non-volatile memory; volatile memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; an isolation circuit for controlling access to the volatile memory by the host processor, said isolation circuit having a first mode during which the isolation circuit provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation circuit electrically disconnects the volatile memory from the host processor; and a controller controlling the isolation circuit, said controller programmed to place the isolation circuit in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation circuit in the second mode and transfer data from the volatile memory to the non-volatile memory, wherein the isolation circuit comprises a first multiplexer arranged to multiplex address and control signals and a second multiplexer arranged to multiplex data signals.