Patent ID: 9147676
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. An Electro-Static Discharge (ESD) protection circuit comprising: a plurality of groups of p-type heavily doped semiconductor strips (p+ strips); a plurality of groups of n-type heavily doped semiconductor strips (n+ strips), wherein the plurality of groups of p+ strips and the plurality of groups of n+ strips form an array having a plurality of rows and columns, and wherein in each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout; a plurality of gate stacks, each comprising: a conductor electrically connecting a first one of the plurality of groups of p+ strips to a second one of the plurality of groups of n+ strips, wherein the first one and the second one are in a same semiconductor strip column.