Patent ID: 7368376
Filing Date: 2008-05-06
Classification: H01L,Y10T

Abstract:
1. A method for fabricating an integrated circuit chip comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first interconnecting structure over said first dielectric layer, wherein said first interconnecting structure is connected to said multiple devices, wherein said first interconnecting structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first interconnecting structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said first interconnecting structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first interconnecting structure and exposes said first contact point, and a second opening in said passivation layer is over a second contact point of said first interconnecting structure and exposes said second contact point, wherein said first and second contact points are separate from each other, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and forming a second interconnecting structure over said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second interconnecting structure, and wherein said forming said second interconnecting structure comprises a copper electroplating process.