Patent ID: 8916394
Filing Date: 2014-12-23
Classification: B82Y,H01J,H01L,Y10S

Abstract:
1. A semiconductor process applied to a wafer, the wafer comprising a silicon substrate; a first insulator layer on the silicon substrate; a first silicon layer on the first insulator layer; a second insulator layer on the first silicon layer; and a second silicon layer on the second insulator layer; the semiconductor process comprising: etching through the second silicon layer, through the second insulator layer, and through the first silicon layer to the first insulator layer to define a hole; lateral etching in the first silicon layer to laterally enlarge the hole at the first silicon layer; etching through the first insulator layer to the substrate, so that the hole has a bottom that includes the substrate; depositing a removable material on the wafer; and forming an array of carbon nanotubes at the bottom of the hole on the substrate.