Patent ID: 6329863
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A semiconductor memory device having a first semiconductor chip and a second semiconductor chip arranged in a stack,the first semiconductor chip comprising:a first pad electrically connected to an external pin;a first internal circuit;a first transmission line electrically connected between the first pad and the first internal circuit;a first protective element, connected between a first power supply voltage and a first node, for protecting the first internal circuit from excessive electrical signals input to the first pad;a first fuse connected between the first node and the first transmission line;a second protective element, connected between a ground voltage and a second node, for protecting the first internal circuit form excessive electrical signals input to the first pad; anda second fuse connected between the second node and the first transmission line,and the second semiconductor chip comprising:a second pad electrically connected to the external pin;a second internal circuit;a second transmission line electrically connected between the second pad and the second internal circuit;a third protective element, connected between the first power supply voltage and a third node, for protecting the second internal circuit from excessive electrical signals input to the second pad;a third fuse connected between the third node and the second transmission line;a fourth protective element, connected between the ground voltage and a fourth node, for protecting the second internal circuit from excessive electrical signals input to the second pad; anda fourth fuse connected between the fourth node and the second transmission line.