Patent ID: 7724579
Filing Date: 2010-05-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a control signal generation unit configured to generate a plurality of control signals in response to a bias current; a reference current generation unit configured to generate a reference current in response to the plurality of control signals; and a sense amplifier configured to sense and amplify data stored in a given memory cell based on the reference current and a current on a bit line connected to the memory cell, wherein the control signal generation unit includes wherein the sense amplifier is positioned between the first control signal generation unit and the second control signal generation unit, wherein the first control signal generation unit includes a first current mirror that is connected to inputs for a first enable signal and a second enable signal and mirrors the bias current in response to one of the first enable signal and the second enable signal, and wherein the second control signal generation unit includes a second current mirror that is connected to the inputs for the first enable signal and the second enable signal and mirrors the bias current in response to one of the first enable signal and the second enable signal, wherein the first enable signal and the second enable signal are independent and exclusively enabled.