Patent ID: 6551859
Filing Date: 2003-04-22
Classification: H01L,Y10T

Abstract:
A method for patterning a conductive substrate, which is utilized to form a packaged semiconductor device, the method comprising:providing a conductive leadframe; applying a photo resist layer to a surface of the conductive leadframe and patterning the photo resist layer to expose stud regions of the leadframe; plating the exposed stud regions on the conductive leadframe with a metallic barrier layer over the stud regions; plating the stud regions on the conductive leadframe with a second metallic material to form a second metallic layer over the barrier layer in the stud regions; stripping the photo resist from the surface of the conductive leadframe; and etching the conductive leadframe areas surrounding the metallic barrier layers and second metallic layers to form depressed regions and a plurality of studs by using the metallic barrier layers and second metallic layers as an etching resist, whereby the depressed regions define the plurality of studs and each of the plurality of studs support the metallic barrier layers and second metallic layers, wherein at least some of the studs are formed with locking grooves that are configured to allow a molding material to securely adhere to the studs.