Patent ID: 6727722
Filing Date: 2004-04-27
Classification: G01R,H01L

Abstract:
A process of testing a semiconductor wafer of integrated circuit dies, each of the integrated circuit dies being formed in a rectangular portion of the wafer and the dies being formed in rows and columns with the sides of each die aligned parallel with the sides of adjacent dies, the sides of the dies being separated from one another by scribe lanes between the dies that will be scribed and broken to separate the dies from one another, each die having at least two groups of bond pads with each group of bond pads adjacent opposite sides of the die, each die including functional circuitry for performing normal operating functions, test circuitry for performing testing of the die, and by-pass circuitry for selectively by-passing the functional and test circuitry of the die, the functional circuitry, test circuitry and by-pass circuitry being connected to the groups of bond pads with the by-pass circuitry selectively connecting bond pads on one side of the die with bond pads on the opposite side of the die without activating the functional and testing circuitry, and the wafer including electrical leads formed on the wafer and extending across the scribe lanes to connect a group of bond pads on one side of one die with a group of bond pads on an adjacent side of an adjacent die, the process comprising:applying a control signal to a first bond pad of a first die; B. applying test signals to a first group of bond pads of the first die; C. selectively conducting the test signals received at the first group of bond pads to a second group of bond pads located on an opposite side of the first die to by-pass the functional and test circuitry on the first die; and D. applying the test to a second die by conveying, on the electrical leads, the test signals at the second group of bond pads on the first die to a first group of bond pads on the second die.