Patent ID: 8803131
Filing Date: 2014-08-12
Classification: B82Y,H01L

Abstract:
1. An integrated circuit comprising: a graphene layer disposed on a substrate, the graphene layer comprising a region of undoped graphene and a region of doped graphene adjacent the region of undoped graphene, the undoped graphene comprising a channel of a transistor, and the region of doped graphene comprising a contact of the transistor; a gate of the transistor disposed over the channel, the gate comprising a first portion of a carbon nanotube film; a dielectric layer located on top of the graphene layer and underneath the gate of the transistor, such that the first portion of the etched carbon nanotube film is isolated from the undoped graphene channel by the dielectric layer; a via formed through the dielectric layer, and filled with a second portion of the carbon nanotube film; and a top level interconnect formed on top of the dielectric layer and in contact with the via, the top level interconnect comprising a third portion of the carbon nanotube film.