Patent ID: 6578071
Filing Date: 2003-06-10
Classification: G06F

Abstract:
A repeater for use in a first node of a plurality of symmetric multiprocessing (SMP) nodes coupled via a global bus in a shared memory computing system, said first node including a plurality of physical memory locations configured to be accessed by said plurality of SMP nodes, wherein each of said locations are mapped to a plurality of address partitions and are addressable by a plurality of address aliases, said repeater comprising:a first interface configured to receive a first transaction via a first bus of said first node, wherein said first bus couples a plurality of processors and a memory comprising said memory locations in said first node, and wherein transactions conveyed via said first bus are visible to each of said plurality of processors; and a second interface configured to transmit said first transaction via a second bus; wherein said repeater is configured to transmit said received first transaction via said second interface in response to detecting said first transaction is addressed to a first partition of said partitions; and wherein said repeater is configured to inhibit transmission of said first transaction via said second interface in response to detecting said first transaction is addressed to a second partition of said partitions.