Patent ID: 6463557
Filing Date: 2002-10-08
Classification: G11C

Abstract:
A method for testing a semiconductor memory cell that includes first and second transistors in cross-coupled arrangement to form a bistable latch, drains of the first and second transistors respectively representing first and second nodes each for storing a high or low potential state, the first and second nodes being respectively connected to first and second semiconductor arrangements for replacing charge leaked from the first and second nodes, respectively, and to first and second switching means, activatable by a word-line, for coupling the first and second nodes to respective first and second bit-lines, the method comprising the steps of:connecting the first and second bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards a potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test operation of the first semiconductor arrangement.