Patent ID: 6987705
Filing Date: 2006-01-17
Classification: G11C

Abstract:
1. A memory device configured to generate a data output enable signal corresponding to a set CAS latency mode, the memory device comprising: a control clock generator for generating an A-type first control clock and a B-type first control clock, the A-type first control clock being supplied by dividing DLL clock by two, the B-type first control clock being an inversed A-type first control clock; a first redundancy enable signal generator for shifting an internal read signal by a predetermined interval in synchronization with one of the A-type first control clock and the B-type first control clock and generating a plurality of first redundancy enable signals, the internal read signal being generated corresponding to a read command; a second redundancy enable signal generator for synchronizing the plurality of first redundancy enable signals with the DLL clock and generating a plurality of second redundancy enable signals; and an output enable signal generator for selecting one redundancy enable signal corresponding to the set CAS latency mode among the first redundancy enable signals and the second redundancy enable signals and generating the selected redundancy enable signal as the data output enable signal.