Patent ID: 9159822
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A method comprising: forming a pair of inner spacers along a vertical sidewall of a gate trench, the gate trench extending from a top surface of a first dielectric layer down to a channel layer of a III-V compound semiconductor-containing heterostructure, the first dielectric layer is above the III-V compound semiconductor-containing heterostructure; forming a gate conductor within the gate trench; removing a portion of the first dielectric layer selective to the gate conductor, the pair of inner spacers, and the III-V compound semiconductor-containing heterostructure; forming a pair of outer spacers adjacent to the pair of inner spacers and above the III-V compound semiconductor-containing heterostructure, the outer spacers are in direct contact with and self-aligned to the inner spacers; and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.