Patent ID: 6732210
Filing Date: 2004-05-04
Classification: G06F

Abstract:
An a synchronous low latency method of communicating data packets between a number of processing units that includes a first processing unit and a second processing unit over a communication bus such that the first and the second processor communicate directly with each other, comprising:sending a communication bus request to a bus arbiter by a first processing unit; if the communication bus is open for communication, then granting the first processing unit access to the bus by the bus arbiter; sending a header packet to the bus arbiter by the first processing unit then wherein the header packet includes a target ID; determining if a second processing unit associated with the target ID is able to receive data from the first processing unit by the bus arbiter; if the second processing unit is able to receive data then, sending a data packet to the bus arbiter by the first processor; and sending the data packet to the second processing unit by the bus arbiter.