Patent ID: 7009879
Filing Date: 2006-03-07
Classification: G01R

Abstract:
1. A test terminal negation circuit comprising: a switch circuit which receives a test signal from one or more test terminals and outputs it in an asserted state as it is or in a predetermined negated state to a test object circuit; a test signal control circuit which controls an output signal of the switch circuit to be in the asserted state or in the negated state; a test mode signal generation circuit which generates a test mode signal which asserts the output signal of the switch circuit and outputs it to the test signal control circuit at the time of a test mode; and a negating signal generation circuit which can output a negating signal for forcing the output signal of the switch circuit into the negated state to the test signal control circuit and comprises an electrically rewritable nonvolatile memory element, wherein when the negating signal is outputted from the negating signal generation circuit, the test signal control circuit negates the output signal of the switch circuit even when the test mode signal is outputted from the test mode signal generation circuit.