Patent ID: 7912997
Filing Date: 2011-03-22
Classification: G06F

Abstract:
1. A direct memory access engine, comprising: a transmit channel coupled to a transmit interface; a receive channel coupled to a receive interface; an arbiter coupled to both the transmit channel and the receive channel; a set of queues coupled to the arbiter; the set of queues including command buffers, transmit buffers, and receive buffers; a direct memory access-to-processor bus interface coupled to the set of queues; the transmit buffers configured to store first separate read and write requests; and the receive buffers configured to store second separate read and write requests which are independent of the first separate read and write requests, wherein the transmit channel is configured to perform data management including first residual transfers and first byte alignments for packet payload reads, first descriptor reads, and first descriptor writes performed via the transmit channel.