Patent ID: 7923292
Filing Date: 2011-04-12
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising the steps of: (a) providing a substrate including a front surface, a plurality of first electrodes, a plurality of second electrodes, and a rear surface opposed to said front surface; (b) mounting a first semiconductor chip including a first main surface, a plurality of first bonding pads formed on said first main surface and a first back surface opposed to said first main surface, over said front surface of said substrate via a first insulating film including a first upper surface and a first lower surface opposed to said first upper surface such that said first back surface of said first semiconductor chip faces said front surface of said substrate, and such that said first upper surface of the first insulating film is attached directly to said first back surface of said first semiconductor chip, and such that said first lower surface of said first insulating film is attached directly to said front surface of said substrate; (c) mounting a second semiconductor chip, including a second main surface, a plurality of second bonding pads formed on said second main surface and a second back surface opposed to said second main surface, over said first main surface of said first semiconductor chip via a second insulating film including a second upper surface and a second lower surface opposed to said second upper surface such that said second back surface of said second semiconductor chip faces said first main surface of said first semiconductor chip, and such that said second upper surface of said second insulating film is attached directly to said second back surface of the second semiconductor chip, and such that said second lower surface of said second insulating film is attached directly to said first main surface of said first semiconductor chip; (d) electrically connecting said first bonding pads with said first electrodes; and (e) electrically connecting said second bonding pads with said second electrodes via a plurality of bonding wires, wherein a size in a plan view of said first semiconductor chip is larger than that of said second semiconductor chip, wherein a thickness of said second insulating film is larger than that of said first insulating film, and wherein in said step (e), said second bonding pads are electrically connected with said second electrodes via said bonding wires, respectively, by following steps (e1)-(e2), (e1) electrically connecting a part of one of said bonding wires with one of said second bonding pads; and (e2) after said step (e1), electrically connecting another part of said one of said bonding wires with one of said second electrodes.