Patent ID: 9196691
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A method of fabricating a metal gate electrode of a field effect transistor comprising: forming a dielectric layer over a substrate comprising an isolation region surrounding an active region, wherein the dielectric layer is over the active region; forming an opening in the dielectric layer; partially filling the opening with a high-dielectric-constant material; partially filling the opening with a conformal first metal material over the high-dielectric-constant material; filling the opening with a capping layer over the first metal material; planarizing the capping layer to the high-dielectric-constant material; partially removing the first metal material and capping layer in the opening using a wet etching process in a solution comprising H fully removing the remaining capping layer in the opening using a wet etching process in a solution comprising NH depositing a second metal material in the opening over the remaining first metal material; and planarizing the second metal material.