Patent ID: 8318560
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A method of forming a capacitor of an integrated circuit device, comprising: forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode; forming a supporting conductor coupling the lower electrode to the contact plug after forming the lower electrode; forming a capacitor dielectric layer on the lower electrode; and forming an upper electrode of the capacitor on the capacitor dielectric layer, wherein forming the capacitor dielectric layer is preceded by forming an additional lower electrode portion covering an upper surface of the supporting conductor, the additional lower electrode portion comprising a different material from the supporting conductor, and wherein forming the capacitor dielectric layer includes forming the capacitor dielectric layer on the additional lower electrode portion, and wherein the lower electrode includes a conductive material and wherein the lower electrode comprises a noble metal, a conductive oxide of a noble metal and/or a perovskite structure conductive oxide deposited in an oxidative ambient and wherein the supporting conductor comprises a refractory metal and/or a conductive nitride deposited in a reductive ambient.