Patent ID: 7682900
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A method of fabricating a flash memory device, the method comprising: providing a semiconductor substrate comprising a select transistor and memory cells having junctions, wherein a width between of the memory cells is smaller than a width between the select transistor and a memory cell that is adjacent to the select transistor; forming a hard mask pattern on a surface of the select transistor, the memory cells, and the semiconductor substrate to generate an overhang, wherein voids are formed between the memory cells due to the overhang; performing a first etch process to remove a portion of the hard mask pattern formed on a bottom between the select transistor and the memory cells, thus exposing the junctions; performing a second etch process to remove a portion of the junction formed between the select transistor and the memory cells, without removing the voids between the memory cells; and forming an insulating layer to gap-fill regions between the adjacent select transistor and memory cells.