Patent ID: 8084788
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A transistor formed within a substrate, the transistor comprising: a source region; a drain region; a channel region disposed between the source region and the drain region; and a gate disposed above the channel region; wherein the source region and the drain region comprise a base layer of low flow hydrogen embedded silicon germanium (eSiGe) deposited by a first hydrogen carrier gas flow of 5 to 10 standard liters per minute (slm) and a top layer of high flow hydrogen eSiGe deposited by a hydrogen gas flow of 11 to 50 slm on the base layer; wherein a device width of the transistor is such that the source region is equal to, or less than, the combined height of the base layer and top layer of embedded silicon germanium; and wherein the base layer extends to a level below a bottom of the gate and the top layer induces a pinned morphology, wherein the top layer at a position between another transistor is above the base of the gate and is below the base of the gate at the point where the top layer is adjacent to the gate.