Patent ID: 6119204
Filing Date: 2000-09-12
Classification: G06F

Abstract:
A method for maintaining translation lookaside buffer (TLB) coherency in a data processing system having at least a first processor and a second processor, said method comprising:in response to detection by said second processor of a TLB entry invalidation request, marking at least one memory referent instruction being processed by said second processor and invalidating a TLB entry in said second processor;in response to receipt of a synchronization request at said second processor, indicating to said first processor that said second processor has invalidated said TLB entry if said second processor has completed processing said marked instruction; andcontinuing to process instructions in said second processor during an interval between receipt of said synchronization request and indicating to said first processor that said second processor has invalidated said TLB entry, wherein continuing to process instructions includes fetching instructions for processing.