Patent ID: 6570809
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A flash memory device comprising:a control logic for controlling programming, erasing, and reading operations of the flash memory device; a data input buffer for storing an input data; a first data bus electrically connected to the data input buffer for transferring the input data received from the data input buffer; and a plurality of memory banks, each memory bank comprising a plurality of memory cells arranged in a matrix format for storing the input data; a page buffer for temporarily storing the input data which will be written into a corresponding memory cell; and a data multiplexer electrically connected to the page buffer, the first data bus and a second data bus for selecting a transmitting path between the page buffer and the first data bus or between the page buffer and the second data bus; wherein when the input data stored in one of the memory banks is to be duplicated into another one of the memory banks, the two data multiplexers respectively corresponding to the two memory banks select a transmitting path between a corresponding page buffer and the second data bus to allow the input data to be duplicated through the second data bus.