Patent ID: 7903469
Filing Date: 2011-03-08
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a drain side selection transistor and a source side selection transistor which are connected to both ends of said plurality of memory cells respectively; a plurality of word lines which are connected to said plurality of memory cells and a plurality of bit lines which are connected to said plurality of NAND cell units; and a data read control part wherein when at least one of said plurality of memory cells is selected and data is read from the selected memory cell, a first voltage is applied to a control gate of said source side selection transistor, a second voltage is applied to a selected bit line, a ground voltage is applied to a plurality of non-selected bit lines and a common source line, when said first voltage is applied to said control gate of said source side selection transistor a voltage which is applied to said plurality of word lines is 0 volts, predetermined voltages are applied to said plurality of word lines after said first voltage is applied to said control gate of said source side selection transistor, and a third voltage is applied to a control gate of said drain side selection transistor after said predetermined voltages are applied to said plurality of word lines, and when reading of said selected memory cell coupled to a selected word line, a read pass voltage which is applied to at least one of said plurality of word lines which is connected to a non-selected one of the plurality of memory cells which is adjacent to said drain side selection transistor, is made lower than a read pass voltage which is applied to other word lines of said plurality of word lines which are connected to other non-selected memory cells of the plurality of memory cells.