Patent ID: 8041759
Filing Date: 2011-10-18
Classification: H03K

Abstract:
1. A specialized processing block for a programmable logic device, said specialized processing block being adaptable to form a finite impulse response (FIR) filter, said specialized processing block comprising: a plurality of fundamental processing units, each of said fundamental processing units including: a plurality of partial product generators, each respective one of said partial product generators providing a respective plurality of vectors representing a respective partial product; compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product; and circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; a first plurality of input registers for inputting coefficients of said FIR filter as inputs to said plurality of partial product generators; a second plurality of input registers for inputting data to said FIR filter, said registers being chained for inputting data seriatim to each said plurality of partial product generators; and an output stage, said output stage including: a plurality of adders, said plurality of adders being adaptable to provide as an output a sum of (1) a multiplication operation involving two of said fundamental processing units and (2) a corresponding output cascaded from another said plurality of adders in a first other output stage in a first other one of said specialized processing blocks, and an output cascade register for registering said output for cascading to a second other output stage in a second other one of said specialized processing blocks; wherein: said second plurality of input registers comprises a delay register to compensate for said output cascade register when said second plurality of input registers are chained to a corresponding second plurality of input registers in said second other one of said specialized processing blocks.