Patent ID: 8861302
Filing Date: 2014-10-14
Classification: G11C

Abstract:
1. A decoder for decoding an address having a plurality of bits ranging from a first address bit a 1 to a last address bit a N , each address bit being either true or false, comprising: a pre-charge circuit configured to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float, wherein the pre-charge circuit allows the pre-charged dynamic NOR node and the pre-charged dynamic OR node to float upon assertion of a clock signal; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a a (n+1)th switch coupling the dynamic NOR node to the ground; a (n+2)th switch coupled between the dynamic NOR node and the ground and arranged in parallel with the plurality of switches, the (n+2)th switch being driven by a delayed version of the clock signal; an odd plurality of three or more word line inverters coupled in series with the dynamic OR node, one of the three or more word line inverters being further arranged with a cross-coupled inverter; and a word line driven by the odd plurality of inverters.