Patent ID: 7470620
Filing Date: 2008-12-30
Classification: B82Y,H01L

Abstract:
1. A method for fabricating transistors, comprising: forming a first dielectric layer having one or more first vias with one or more first conductive pads correspondingly disposed therein; depositing a second dielectric layer defining one or more second vias and one or more third vias, each second via in communication with each first conductive pad, and each of the one or more third vias being coaxial with each of the one or more first via of the first dielectric layer and not in communication with a first conductive pad; depositing a catalyst on each of the one or more first conductive pads; depositing a carbon nanotube extending from each catalyst through said one or more second vias; depositing a conductive material in each of the third vias, the one or more third vias being electrically insulated to complementary second vias forming one or more ring gate electrodes, respectively; depositing a third dielectric layer comprising one or more second conductive pads, each of the one or more second conductive pads being in communication with the carbon nanotubes in the one or more second vias correspondingly, or the conductive material within the one or more third vias correspondingly.