Patent ID: 6202195
Filing Date: 2001-03-13
Classification: G06F

Abstract:
A method for the layout of a semiconductor integrated circuit, said layout method comprising:(a) a layout step of laying out, in conformance with a predetermined design limitation, wires for interconnecting components which together form a circuit;(b) a delay judging step of checking, on the basis of information representing a layout result obtained in said layout step, each of said laid-out wires for the presence of a violation of a predetermined delay limitation for the limitation of a signal propagation delay time; and(c) a design limitation modifying step of calculating an amount of change to be made in said predetermined design limitation based on a result of said judging step and making a change in said predetermined design limitation based on said calculated amount of change and said layout result information,wherein said delay judging step (b) includes a delay limitation violating wire extracting step (b-1) of extracting, from among said laid-out wires, a violational wire in violation of said predetermined delay limitation,wherein said design limitation modifying step (c) includes a delay limitation violation canceling step (c-1) including:(c-1-1) calculating an amount of change to be made in said predetermined design limitation imposed on said violational wire based on an amount of violation of said predetermined delay limitation caused by said extracted violational wire, said amount of violation being a time by which a signal propagation delay time on the violational wire exceeds said signal propagation delay time defined by said predetermined delay limitation; and(c-1-2) making a change in said design limitation imposed on said violational wire based on said amount of violation, to cancel said delay limitation violation caused by said violational wire, andwherein said layout method further comprises a design limitation violation canceling step (d) including (d-1) receiving layout information representing a result of modification of said predetermined design limitation in said step (c); and (d-2) when a distance of separation defined between said violational wire as re-laid out so as to meet said modified design limitation and a component laid out so as to meet said predetermined design limitation, does not meet a design limitation imposed on said distance of separation, displacing said component to meet said design limitation.