Patent ID: 6169437
Filing Date: 2001-01-02
Classification: H03L

Abstract:
A variable delay module comprising: a clock generator having a clock reference input, a plurality of control line inputs, a computer bus port, a first clock output, and a second clock output; an input means having an input, a digital output, and a clock input coupled to said first clock output for controlling timing of said digital output; a buffering circuit having an digital input coupled to said digital output of said input means and a digital output, said buffering circuit having a first clock input coupled to said first clock output and a second clock input coupled to said second clock output; and an output means having a digital input coupled to said digital output of said buffering circuit, an output, and a clock input coupled to said second clock output for controlling timing of said output, wherein said clock generator further comprises: a digital phase lock loop (DPLL) coupled to said clock reference input, coupled to said first clock output, and coupled to said second clock output; a controller coupled to said DPLL coupled to said plurality of control inputs, and said computer bus port; and a delay control circuit coupled to said DPLL and to said controller.