Patent ID: 6350690
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A process for CMP polishing of a surface of a Damascene semiconductor device to achieve both global and local planarization, said device comprising a silicon substrate, a primary low-k dielectric layer having a dielectric constant of substantially 3.5 or less disposed on top of said silicon substrate, a dielectric capping layer formed on top of said primary dielectric layer, a barrier layer formed on top of said dielectric capping layer and comprising upper horizontal segments, and a metallic top layer formed on the upper surfaces of said barrier layer, said metallic top layer having global and local topographic features on its upper surface, said process comprising the steps of:using a first slurry, effecting a bulk CMP removal, at a rate of from 4,000 to 10,000 Angstroms per minute, of substantially 80% to 90% of said metallic top layer without penetrating to said barrier or dielectric capping layers, to form a first surface on said metallic top layer; using a second slurry having substantially 1:1:1 removal rate ratios with regard to the materials comprising said metallic top layer, said barrier layer and said dielectric capping layer, in sequence effecting further CMP removal, at a rate of from 1,000 to 3,000 Angstrom units per minute, of said metallic top layer, removal of said upper horizontal segments of said barrier layer and removal of a minimal amount of said dielectric capping layer, and terminating CMP removal before contacting said primary low-k dielectric layer.