Patent ID: 6441769
Filing Date: 2002-08-27
Classification: H03M

Abstract:
A pipelined analog-to-digital converter comprising:a plurality of stages, each stage having a stage input and a stage output, the stage input receiving a stage input signal and the output providing a residue output signal; each stage including: an analog-to-digital converter having an input and an output, the input coupled to the stage input and the analog-to-digital converter configured and arranged to provide as an output an N-bit digital output signal representative of the input signal; a digital-to-analog converter having an input and an output, the input sampling the N-bit to digital output signal, the digital-to-analog converter configured and arranged to provide as an output an analog output signal representative of the digital output signal; a subtraction module configured and arranged to subtract the analog output signal from the input signal and to provide a subtracted analog signal; an amplifier assembly having a gain factor of 2N, the amplifier assembly having an input coupled to the subtracted analog signal, and the amplifier assembly configured and arranged to provide as an output signal the residue output signal output of the stage that is equal to the amplified subtracted analog signal; a sampling network including a sampled signal input coupled to the input of the amplifier assembly, and an output, and the sampling network configured and arranged to provide a feed-forward error correction signal that is the negative of the sampled signal to the subtraction module of a subsequent stage.