Patent ID: 8429135
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. A method comprising: in a processor device that includes software instructions, storing contents of a translation lookaside buffer in a memory that is protected by an error correction code to provide an error correction code protected backup copy of the contents of the translation lookaside buffer; setting a trigger for a miss exception for the contents of the translation lookaside buffer to determine whether an address translation of the contents of the translation lookaside buffer returns an invalid address; determining whether a first instance of the trigger for the miss exception has occurred; performing a translation lookaside buffer miss handler function when the first instance of the trigger for the miss exception has occurred in order to refresh the contents of the translation lookaside buffer with the error correction code protected backup copy such that the contents of the translation lookaside buffer comprise the error correction code protected backup copy of the contents of the translation lookaside buffer; re-executing the translation lookaside buffer miss handler function using the error correction code protected backup copy in the translation lookaside buffer; determining whether a second instance of the trigger for the miss exception has occurred; storing an indication indicating that the address translation of the contents of the translation lookaside buffer is unrecoverable and returns the invalid address due to an uncorrectable problem in response to determining that the second instance of the trigger has occurred; and storing an indication that the miss exception was an error and that the invalid address of the address translation of the contents of the translation lookaside buffer was successfully corrected by refreshing the contents with the error correction code protected backup copy in response to determining that the second instance of the trigger has not occurred.