Patent ID: 7107391
Filing Date: 2006-09-12
Classification: G06F,G11C

Abstract:
1. A content addressable memory, comprising: a plurality of memory storage locations, each having an associated indicator for indicating that the memory storage location is available for data storage and an associated match line for indicating if a search word matches a word stored in the memory storage location; a first selection circuit for selecting the match lines associated with each of said plurality of memory storage locations during a first mode and for selecting the indicators associated with each of said plurality of memory storage locations during a second mode; a priority encoder having a plurality of inputs and operable in the first mode where said first selection circuit respectively couples said match lines to said plurality of inputs to indicate a priority match on said match lines and in the second mode where said first selection circuit respectively couples said indicators to said plurality of inputs to indicate a priority storage location available for data storage, wherein said priority encoder comprises a highest priority indicator circuit having said plurality of inputs and a plurality of outputs, one of said outputs being active at a time to indicate a highest priority of signals present at said inputs; a second selection circuit for selecting one of said memory storage locations for a memory operation in response to a selected first selection signal associated with an output of the priority encoder or a second selection signal associated with a read/write address; and a plurality of latch circuits respectively coupled to the outputs of said highest priority indicator circuit, said plurality of latch circuits being selectively operable when said priority encoder is in said second mode to latch an indication of a highest priority memory storage location which is available for data storage, said latches respectively supplying said first selection signals for the associated memory storage locations.