Patent ID: 6256753
Filing Date: 2001-07-03
Classification: G06F

Abstract:
An I/O monitor for a computer system, the monitor comprising an I/O interface connectable between at least one processor and an I/O bus to control the passage of I/O operations to the I/O bus and the receipt of I/O operations and bus exceptions from the I/O bus, wherein the I/O interface is operable:during an I/O read cycle, to respond to a bus error signal from the bus by substituting a predetermined data value for the bus error signal and passing the predetermined data value to said at least one processor, to determine a resource that forms the source of the bus error and to label the resource forming the source of the bus error as being defective; andduring an I/O write cycle, to respond to a bus error signal by discarding the write and terminating the I/O cycle by returning an acknowledgement to said at least one processor, to determine a resource that forms the source of the bus error and to label the resource forming the source of the bus error as being defective.