Patent ID: 6071808
Filing Date: 2000-06-06
Classification: H01L

Abstract:
A method of passivating copper interconnects in a semiconductor comprising the steps of:depositing a first oxide layer over a semiconductor substrate;forming an etch stop layer over the oxide layer;forming a second oxide layer over the etch stop layer;etching a first set of trench openings within the second oxide layer and then etching through the etch stop layer;etching a second set of openings in the first oxide layer within the bounds defined by the first set of openings to form vias for interconnects;electrodepositing a copper layer over selected portions of the second oxide layer such that copper is deposited within the first and second sets of openings and forming exposed copper interconnects;exposing the electrodeposited copper interconnects to a chemical reaction containing vapors of tungsten alkoxide and chromium alkoxide in an MOCVD reactor to form respectively copper tungstates and copper chromates as a passivating surface on the exposed copper interconnects; and thenchemically mechanically polishing the copper interconnects having the passivating surface.