Patent ID: 7535452
Filing Date: 2009-05-19
Classification: G09G

Abstract:
1. A timing controller of a liquid crystal display driver for controlling the timing of each of a scan line driving circuit and a data line driving circuit, the timing controller comprising: an n-bit counter counting a number of pulses of a vertical synchronous signal clocked at the vertical synchronous signal and generating an n-bit count signal; a determination circuit for receiving the n-bit count signal, comparing the n-bit count signal with a predetermined n-bit reference signal, and outputting the result of comparison; a first NAND gate NANDing a signal output from the determination circuit and a data enable signal; a second NAND gate NANDing a signal output from the first NAND gate and a clock signal; and a memory device receiving and storing first display data in response to the signal output from the second NAND gate, wherein the timing controller controls the timing of each of the data line driving circuit and the scan line driving circuit in response to input display data and control signals including the vertical synchronous signal and the data enable signal and generates an internal data enable signal in response to the control signals, and the memory device receives and stores the input display data in response to the internal data enable signal having a period that is a plural integral multiple of the period of the data enable signal.