Patent ID: 9088497
Filing Date: 2015-07-21
Classification: H04L

Abstract:
1. A packet switching device, comprising: a packet processor configured to process data packets received from a network; a plurality of egress ports disposed downstream of the packet processor, the egress ports configured to transmit processed data packets over selected network links; a dynamically configurable memory unit comprising memory blocks that are selectably allocatable to one or more egress ports such that a size of a memory space that is available to a particular egress port is a function of a quantity of memory blocks allocated to the particular egress port; a controller configured to dynamically allocate memory blocks among the egress ports that are coupled to the active network links based on respective congestion levels of the egress ports so that egress ports having a greater congestion level are allocated more memory blocks than egress ports having a less congestion level; a plurality of interfaces connected to a subset of the egress ports; and a register configured to control a number of the memory blocks allocated for each of the interfaces; a counter configured to keep a count of the interfaces; an allocation table configured to periodically fetch an entry of the allocation table, which is accessed by a dynamic pointer derived based on the count; and the register further configured to copy values of the entry into the register and control the number of the memory blocks based on the copied values.