Patent ID: 6012108
Filing Date: 2000-01-04
Classification: H04L,H04Q

Abstract:
A device for dualizing main processors in an asynchronous transfer mode switch, comprising:dualization controllers, each of which is in an active mode and a standby mode and connected with memories of each of corresponding modes by way of a main bus (MBUS), each of said dualization controller is comprised of:a first-in first-out;a write buffer connected between said MBUS in said active mode and said first-in first-out;a write controller for storing data stored at said write buffer at said first-in first-out;a read buffer connected between said MBUS in said standby mode and said first-in first-out;a read controller for simultaneously storing data stored at said first-in first-out, at said read buffer, checking status of said MBUS in said standby mode, and outputting the data stored at said read buffer to said MBUS in said standby mode.