Patent ID: 8001450
Filing Date: 2011-08-16
Classification: G06F

Abstract:
1. A semiconductor memory device having an error correction function, comprising: a data memory cell array which includes a plurality of memory cells and inputs and outputs data of 2 a parity memory cell array which includes a plurality of memory cells and inputs and outputs parity bits of a number of bits which corresponds to the 2 a data I/O terminal; a parity generation circuit which generates the parity bits from write data of 2 a syndrome generation circuit which generates, from the parity bits which are read from the parity memory cell array to the parity bus and read data of 2 an error correction circuit which corrects errors in the read data on the basis of the syndrome bit, wherein the parity generation circuit and the syndrome generation circuit are constituted so as to be capable of switching to either a first ECC having 2