Patent ID: 6219023
Filing Date: 2001-04-17
Classification: G06T,G09G,H04N

Abstract:
A liquid crystal display (LCD) device for receiving horizontal and vertical synchronization signals and at least one analog video signal synchronized with said horizontal video signal from a host and displaying an image on a screen thereof, said LCD device comprising:a display mode discriminating means for discriminating a display mode supported by said host in response to said horizontal and vertical synchronization signals to generate first and second mode signals and first, second, third, fourth and fifth data signals related to said discriminated display mode;a clock generator for generating first and second pixel clock signals in synchronization with said horizontal synchronization signal, said first and second pixel clock signals respectively having frequencies corresponding to said first and second data signals, a number of pulses of said first pixel clock signal corresponding to one horizontal line being equal to a value of said first data signal, and a number of pulses of said second pixel clock signal corresponding to one horizontal line being equal to a value of said second data signal;an analog-to-digital converter (ADC) for converting said at least one analog video signal into a digital video signal in synchronism with said first pixel clock signal;a memory for storing said digital video signal;a horizontal output generator for receiving said third and fourth data signals in response to said vertical synchronization signal and generating a horizontal output signal, said digital video signal being read from said memory in synchronism with said horizontal output signal, a number of pixels per cycle of said horizontal output signal being equal to a value of said third data signal, and a number of pixels per pulse width of said horizontal output signal being equal to a value of said fourth data signal; anda memory controller for controlling reading and storing operations of said memory in accordance with said horizontal synchronization signal, said horizontal output signal, said third and fifth data signals, and said first and second pixel clock signals, said reading operation being delayed from a rising edge of said horizontal synchronization signal to a period corresponding to a value of said fifth data signal and then activated, whereby said reading and storing operations are not simultaneously activated.