Patent ID: 7519778
Filing Date: 2009-04-14
Classification: G06F

Abstract:
1. A cache coherence system comprising: a memory apparatus which is to provide data access function; a plurality of access-consumers, at least one of the plurality of access-consumers is a processor having a cache, wherein the cache stores part of data of the memory apparatus, and, the processor issues a read second data request first followed by a write-back first data request and registers the read second data request and the write-back first data request in a command queue register when the processor replaces a first data in the cache with a second data read from the memory apparatus; a detector coupled to the processor, which is used to provide a detecting signal after the processor issues the read second data request, and to cancel the provided detecting signal when the processor issues the write-back first data request; and a plurality of pass-gates, each of the plurality of pass-gates is coupled between a corresponding access-consumer and the memory apparatus, and is used to decide whether to pass a third access request outputting from the corresponding access-consumer to the memory apparatus according to the detecting signal provided by the detector, wherein the addresses of the first data and the second data in the memory apparatus have a same first address characteristic when both the first data and the second data are in the memory apparatus; when the processor issues the read second data request, the detector registers and provides the first address characteristic as the detecting signal; and when the processor issues the write-back first data request, the detector erases the registered first address characteristic, so that cancels the provided detecting signal, wherein the number of bits of the first address characteristic is determined by the rate of the processor and the size of one cache line in the cache.