Patent ID: 7292572
Filing Date: 2007-11-06
Classification: H04L

Abstract:
1. An apparatus comprising: a memory configured to store a plurality of pattern sets, each of said pattern sets respectively comprising an index value and a data value; a first pattern matching circuit configured to (i) generate a first pointer to read a first set of said pattern sets and (ii) assert a first of a plurality of match signals in response to both a first position and a first content of a first unit of an incoming data signal matching both said index value and said data value of said first set; a second pattern matching circuit configured to (i) generate a second pointer to read a second set of said pattern sets and (ii) assert a second of said match signals in response to both a second position and a second content of a second unit of said incoming data signal matching both said index value and said data value of said second set; and a results circuit configured to assert a protocol indication signal in response to assertion of at least one of said match signals.