Patent ID: 6373774
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory macro including: a memory cell array region including a plurality of memory cells disposed in a matrix arrangement, a plurality of word lines disposed in correspondence to a plurality of rows, and a plurality of bit lines disposed in correspondence to a plurality of columns; and a select circuit for selecting a memory cell, a layout of said memory macro being determined according to a memory capacity; a logic circuit specifying operation of said memory macro; and A an address connection line for transmitting an address to select a memory cell to said memory macro from said logic circuit, disposed between said logic circuit and said memory macro, wherein said address connection line is interconnected according to a bank configuration of said memory cell array region such that consecutiveness of an address space in a bank is maintained, and wherein said plurality of memory cells are grouped into a plurality of memory blocks, said address comprises: a word line select address, and a block select address having a plurality of bits; said select circuit selects not only a memory block according to said block select address but also a specific word line included in said selected memory block according to said word line select address, and said address connection line is interconnected such that higher order bits of said block select address output from said logic circuit are assigned to lower order bits of said block select address in said memory macro, while lower order bits of said block select address output from said logic circuit are assigned to higher order bits of said block select address in said memory macro.