Patent ID: 6172565
Filing Date: 2001-01-09
Classification: H03F

Abstract:
A feedforward linearizer for amplifying an input signal comprises:a signal cancellation circuit having a first signal cancellation branch and a second signal cancellation branch;a signal cancellation delay circuit within said first signal cancellation branch configured to receive said input signal, said delay circuit having a plurality of tap delay elements connected in series, wherein each of said tap delay elements provides a delayed version of said input signal, said delay circuit further comprising a plurality of tap coefficient multipliers each coupled to a corresponding tap delay element so as to receive a corresponding one of said delayed versions of said input signal and to multiply each of said delayed versions of said input signal with a corresponding tap coefficient, said delay circuit further comprising a delay circuit adder coupled to an output port of each one of said multipliers so as to add output signals provided by said multipliers;a first amplifier provided in said first signal cancellation branch, said amplifier configured to receive an output signal of said delay circuit adder intended to be amplified;a signal cancellation adder coupled to an output port of said first amplifier via an attenuator and to said input signal via said second signal cancellation branch so as to provide an error signal;an error cancellation circuit having a first error cancellation branch and a second error cancellation branch;an error cancellation delay circuit having a plurality of tap delay elements connected in series, wherein each of said tap delay elements provides a delayed version of said error signal, said delay circuit further comprising a plurality of tap coefficient multipliers each coupled to a corresponding tap delay element so as to multiply each of said delayed versions of said error signal with a tap coefficient, said delay circuit further comprising a delay circuit adder coupled to an output port of each one of said multipliers;a second amplifier provided in said first error cancellation branch, said amplifier configured to receive an output signal provided by said delay circuit adderan error cancellation adder in said first error cancellation branch, said error cancellation adder configured to receive the output signal provided by said second amplifier;also to receive the output signal of the signal cancellation adder;provide the final linearization output; anda digital signal processor configured to provide said signal cancellation delay adjustment coefficients .alpha..sub.i, to said tap coefficient multipliers an error signal cancellation delay adjustment coefficients, .beta..sub.i, to said tap coefficient multipliers such that the delay in said upper and lower branches of said both cancellation circuits is substantially aligned, and the output signal of said first amplifier is substantially equalized.