Patent ID: 9048877
Filing Date: 2015-06-02
Classification: H03M

Abstract:
1. A Turbo code parallel interleaver, comprising a hardware processor configured to execute program units stored on a non-transitory computer readable medium, the program units comprising: an interleaving unit configured to generate a column address for parallel-reading data and a row address of each row for row-interleaving the parallel-reading data, input the column address to a Code Block (CB) matrix unit as a read address, input the column address after delay to the CB matrix unit as a write address, input the row address of each row to a switching output unit, and input the row address of each row after delay to a switching input unit; the switching output unit configured to receive data of each row output by the CB matrix unit, perform inter-row interleaving for the received data of each row according to the row address of each row, and input the interleaved data to a parallel Maximum A Posteriori (MAP) unit for MAP computing, wherein the data of each row is read by the CB matrix unit according to the read address; and the switching input unit configured to receive the row address of each row after delay from the interleaving unit, perform the inter-row interleaving for the data of each row output by the parallel MAP unit after the MAP computing according to the row address after delay, and write the interleaved data of each row into the CB matrix unit as prior information according to the write address.