Patent ID: 6624019
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A memory merged with logic (MML) semiconductor device comprising:a memory area having a self-aligned contact structure and a logic area having a dual gate structure including an n-type metal oxide semiconductor (NMOS) and a p-type metal oxide semiconductor (PMOS) being integrated together; the memory area including: a polycide gate electrode; a hard mask pattern formed on the polycide gate electrode and comprised of nitride materials; a spacer formed along the sidewall of the polycide gate electrode and comprised of nitride materials; a gate poly oxide layer interposed between the sidewall of the polycide gate electrode and the spacer; and a self-aligned contact formed between adjacent spacers and being electrically connected with an impurity implantation region formed on a semiconductor substrate; the logic area including: salicided NMOS and PMOS gate electrodes; and salicided source/drain regions; and wherein a height of the polycide gate electrode is smaller than a height of the NMOS and PMOS gate electrodes.