Patent ID: 7259978
Filing Date: 2007-08-21
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array including a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to signals transmitted to the sub word lines and column selecting signal lines, a bit line sense amplifier configured to sense and amplify data of the bit line pairs, and a sub word line driver configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines, wherein the memory cell array is configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs; and an electrode on the memory cell array and configured to apply a voltage for the memory cells, wherein the local data line pairs, the word selecting signal lines, and the main word lines are arranged in a same direction as the sub word lines, wherein the column selecting signal lines and the global data line pairs are arranged in a same direction as the bit line pairs, and wherein at least one of the column selecting signal lines and/or at least one of the global data lines is between at least one of the word selecting signal lines and the electrode at an intersection of at least one of the word selecting signal lines and at least one of the column selecting signal lines and/or at least one of the global data lines.