Patent ID: 8149985
Filing Date: 2012-04-03
Classification: G09G,G11C,H03K

Abstract:
1. A shift register comprising a plurality of shift register stages {S N }, N=1, 2, . . . , M, M being a nonzero positive integer, wherein each of the plurality of shift register stages, S N , comprises: (a) a first input; (b) a second input; (c) a third input for receiving a first clock signal, CK; (d) a fourth input for receiving a second clock signal, XCK; (e) a fifth input for receiving a first supply voltage, VDD; (f) a sixth input for receiving a second supply voltage, VSS; (g) an output for providing an output signal, OUT(N), therefrom; (h) a first transistor T (i) a second transistor T (j) a third transistor T (k) a fourth transistor T (l) a fifth transistor T (m) a sixth transistor T (n) a seventh transistor T (o) an eighth transistor T (p) a first capacitor C (q) a second capacitor C