Patent ID: 6903590
Filing Date: 2005-06-07
Classification: H03K

Abstract:
1. A pulse generating circuit comprising: a reset pulse generation circuit configured to output a reset pulse based on changes of an input signal from a first state to a second state; a set pulse generation circuit configured to output a set pulse based on changes of said input signal from said second state to said first state; said reset pulse generation circuit comprising: a first inverter circuit including a pair of transistors as complementarily connected between a power supply line and a ground line; and a first delay unit including a first capacitor connected between an output end of said first inverter circuit and said power supply line, and configured to output a delayed output signal with a delayed state change of said input signal, said set pulse generation circuit comprising: a second inverter circuit including a pair of transistors as complementarily connected between a power supply line and a ground line; and a second delay unit including a second capacitor connected between an output end of said second inverter circuit and said ground line and configured to output a delayed output signal with a delayed state change of said input signal, said first inverter circuit being operable to output a signal at a level of said power supply line when said input signal is in the first state and to output a signal at a level of said ground line when said input signal is in the second state.