Patent ID: 8588005
Filing Date: 2013-11-19
Classification: G11C

Abstract:
1. A buffering system for embedded non-FLASH vertically stacked non-volatile memory, comprising: a semiconductor die including a logic layer having circuitry fabricated on the logic layer, the circuitry including a plurality of write buffers, each write buffer electrically coupled with the partition selector and a control signal from the NOR-type interface, the buffer controller loading write data into one of the plurality of write buffers and writing data to another one of the plurality of write buffers, and the buffer controller operative to synchronize the loading and the writing within an interval; and a memory plane in direct contact with and vertically fabricated directly above the die, the memory plane including at least one re-writeable non-volatile two-terminal cross-point memory array embedded therein and having a plurality of first conductive array lines electrically coupled with the array line driver and a plurality of second conductive array lines electrically coupled with the partition selector.