Patent ID: 7235839
Filing Date: 2007-06-26
Classification: G11C,H01L

Abstract:
1. A flash memory cell, comprising: a substrate; a first conductive type deep well disposed in the substrate; a second conductive type well disposed within the first conductive type deep well; a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a tunneling layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the substrate; a second conductive type source region and a second conductive type drain region disposed in the substrate on each side of the stacked gate structure respectively; a select gate disposed between the stacked gate structure and the second conductive type source region; a first gate dielectric layer disposed between the select gate and the stacked gate structure; a second gate dielectric layer disposed between the select gate and the substrate; a first conductive type shallow doped region disposed in the second conductive type well underneath the stacked gate structure and the select gate, wherein the second conductive type source region is disposed in the first conductive type shallow doped region; a first conductive type deep doped region disposed in the second conductive type well on one side of the stacked gate structure hut adjacent to the first conductive type shallow doped region, wherein the second conductive type drain region is within the first conductive type deep doped region; and a conductive plug disposed in the substrate passing downward through the second conductive type drain region with a portion buried within the first conductive type deep doped region.