Patent ID: 6709933
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A method of fabricating a mask ROM, the method comprising the steps of:preparing a substrate defined by a memory cell array region and a peripheral region; forming a device isolation film between the memory cell array region and the peripheral region; forming a gate-forming material layer on the entire surface of the substrate having the device isolation film; covering the memory cell array region and selectively etching the gate-forming material layer in the peripheral region to form a first gate; forming an insulation spacer in a lateral portion of the gate in the peripheral region; injecting ions to the substrate in the peripheral region to form a source/drain region using the gate and the insulation spacer as a mask; forming salicide on the gate-forming material layer of the memory cell array region and the gate and in the source/drain region of the peripheral region; covering the peripheral region and selectively etching the gate-forming material layer in the memory cell array region to form a second gate; and forming a protective film on the resultant substrate.