Patent ID: 8697560
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A process of forming an electronic device comprising: providing a semiconductor layer overlying a substrate, wherein the semiconductor layer has a primary surface; patterning the semiconductor layer to define a first trench, a second trench, and a third trench that extend from the primary surface towards the substrate, wherein the first, second and third trenches are within an active region, and the third region is disposed between the first and second trenches; forming a first conductive structure within the first trench; forming a second conductive structure within the second trench; forming a third conductive structure within the third trench; forming a first insulating layer within the first trench after forming the first conductive structure; forming a second insulating layer within the second trench after forming the second conductive layer; forming a first gate electrode within the first trench, wherein the first insulating layer is disposed between the gate electrode and the first conductive structure; and forming a second gate electrode within the second trench, wherein the second insulating layer is disposed between the gate electrode and the first conductive structure, wherein in a finished electronic device, no gate electrode is disposed above the third conductive structure.