Patent ID: 6656844
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A method of fabricating a capacitor structure on a semiconductor substrate, comprising the steps of:providing a transfer gate transistor comprised of a gate structure on an underlying gate insulator layer, with source/drain regions located in regions of said semiconductor substrate not covered by said gate structure; forming capacitor openings in an insulator layer with each capacitor opening exposing a portion of a top surface of a source/drain region; forming storage node structures in said capacitor openings, with each storage node structure comprised with tall, vertical features; using an overlying photoresist shape as an etch mask to selectively remove exposed portions of said insulator layer from a first group of surfaces of a storage node structure array, while leaving portions of insulator layer located underlying said photoresist shape, still butting a second group of surfaces of said storage node structure array; forming a capacitor dielectric layer on said storage node structure array; and forming a top plate structure on said capacitor dielectric layer, resulting in said capacitor structure comprised of overlying, said top plate structure, said capacitor dielectric layer, and underlying, said storage node structure array.