Patent ID: 7023731
Filing Date: 2006-04-04
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix; a plurality of terminals for accepting commands at least including commands related to programming and erasing operations on the memory cell array issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations on the memory cell array; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the write state machine generates a ready signal indicating that the write state machine is not operating when the ready signal is active and indicating that the write state machine is operating when the ready signal is inactive, and an idle signal indicating that the write state machine is suspending the erasing operation when the idle signal is active, and includes a status register indicative of a status of the write state machine, the command interface circuit includes a user state machine for controlling an operation of the write state machine via control signals including a program control signal and an erase control signal, the user state machine analyzes a command accepted via the plurality of terminals, makes the program control signal active in the case where the command is a program command, makes the erase control signal active in the case where the command is an erase command, and makes the program control signal and the erase control signal inactive in the case where the command is not a valid command, thereby preventing an unexpected influence on the write state machine, the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges, the memory functional element is formed by at least any one of an insulating film including an insulator having the function of retaining charges, an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film of which inner charge is polarized by an electric field and in which the polarized state is held, and the programming or erasing operation to selected one of the memory functional elements formed on both sides of the gate electrode can be executed independently from the other unselected one by controlling each voltage applied to the diffusion regions and the gate electrode.