Patent ID: 7991945
Filing Date: 2011-08-02
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; data read out from the second region is output successively after completion of the operation of outputting data read out from the first region; the operation of outputting data read out from the first region is performed in synchronism with a first edge of an output control signal for controlling the operation of outputting data read out from the first region; and an address specifying the second region is latched in synchronism with a second edge of the output control signal, and wherein the first edge is the next edge of the output control signal subsequent to the second edge.