Patent ID: 6069400
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A semiconductor device having a multi-level interconnection structure comprising:a metal interconnect wire formed on an insulation film serving as a base;a first interlayer dielectric film formed to cover said metal interconnect wire;a second interlayer dielectric film formed on said first interlayer dielectric film;a third interlayer dielectric film formed on said second interlayer dielectric film; anda contact hole extending through said first, second, and third interlayer dielectric films to a surface of said metal interconnect wire,said first and third interlayer dielectric films having different stresses, and one of the first and third interlayer dielectric films being a relative low stress film having a higher etching rate and lower dielectric breakdown voltage than the other of the first and third interlayer dielectric films.