Patent ID: 6834376
Filing Date: 2004-12-21
Classification: G06F

Abstract:
A logic optimization device comprising:a decider for referring to hierarchical circuit-design descriptions representing multiple layers of an integrated circuit, and for deciding whether or not each output terminal at each lower layer is connected with its upper layer; a modifier for deleting from the hierarchical circuit-design descriptions an information part describing an output terminal at a lower layer that has been decided to be unconnected with its upper layer by the decider, and for deleting from the hierarchical circuit-design descriptions an information cart describing an element at the lower layer connected with the output terminal, thereby producing a gate-level net-list of an integrated circuit; and a second decider for deciding whether or not each output terminal, which has been decided to be unconnected with its upper layer by the decider, corresponds to the most significant or the least significant bit of a bus port having a name and a bus width, wherein the modifier deletes an information part describing an output terminal and produces a gate-level net-list where the name of the bus port is not changed, but the bus width is decreased for the deleted output terminal if the second decider has decided the output terminal corresponds to the most significant or the least significant bit of a bus port.