Patent ID: 7949933
Filing Date: 2011-05-24
Classification: G11C,H03M

Abstract:
1. A semiconductor integrated circuit device, comprising: a first word line and a second word line, which are selected on the basis of an address; a pair of complementary bit lines for information bits; a pair of complementary bit lines for parity bits; a first memory cell coupled to the first word line and one of the pair of complementary bit lines for information bits; a second memory cell coupled to the first word line and one of the pair of complementary bit lines for parity bits; a third memory cell coupled to the second word line and another of the pair of complementary bit lines for information bits; a fourth memory cell coupled to the second word line and another of the pair of complementary bit lines for parity bits; column switches which connect the pair of complementary bit lines for information bits to a pair of data lines for information bits and the pair of complementary bit lines for parity bits to a pair of data lines for parity bits; and a logic correction circuit connected to one of the pair of data lines for parity bits, the logic correction circuit executing a parity bit rewrite operation in which, on the basis of the address, a logic of data read out from the data lines for parity bits is inverted in a data read operation, and a logic of data to be written in the data lines for parity bits is inverted in a data write operation.