Patent ID: 6686270
Filing Date: 2004-02-03
Classification: H01L

Abstract:
A method of dual damascene processing, comprising:providing a semiconductor substrate with an insulation structure on an upper surface thereof, the insulation structure consisting essentially of a single layer of a dielectric material; forming a plurality of via openings in the insulation structure, wherein groups of via openings are positioned in a substantially straight line; simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system by generating a signature associated with forming the trenches, comparing the signature to a signature library to determine trench depth, and terminating forming the trenches when a desired trench depth is attained; and filling the trenches and via openings with a conductive metal.