Patent ID: 7162557
Filing Date: 2007-01-09
Classification: G06F

Abstract:
1. A competition arbitration system comprising: a predetermined resource (bus N devices ( an arbitrating apparatus ( N control means (bus masters (a) wherein the arbitrating apparatus includes N gate circuits ( a pulse generating circuit ( an inhibiting circuit ( (b) wherein each control means outputs a request signal (RQ) to a corresponding one of the gate circuits when one of the devices corresponding thereto needs to use the predetermined resource; receives a grant signal (GR-i, i=1, . . . ,N) from the corresponding gate circuit for controlling the corresponding device to use the predetermined resource; and outputs an acknowledgment signal (AK-i, i=1, . . . , N) to the inhibiting circuit during a time interval in which the corresponding device uses the predetermined resource; and (c) wherein, the inhibiting circuit, while receiving the acknowledgment signal (AK-i) from any of the control means, outputs an inhibition signal (IG) to all of the gate circuits, and each gate circuit, when simultaneously receiving the corresponding request signal (RQ) outputted from the corresponding control means and the corresponding pulses (GP) outputted from the pulse generating circuit but not receiving the inhibition signal (IG), outputs the corresponding grant signal (GR-i, i=1, . . . , N) to the control means; and (d) wherein the system does not use fixed priorities.