Patent ID: 8053842
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A semiconductor storage device comprising a static type memory cell in which four MOS transistors are arrayed on a dielectric film formed on a substrate, wherein: the four MOS transistors function as first and second PMOS access transistors each operable to supply electric charges to hold data in the memory cell, and allow access to the memory cell, and first and second PMOS driver transistors each operable to drive a storage node to write and read data in the memory cell, and further wherein: the first and second NMOS access transistors comprise a first diffusion layer of P-type conduction, a first pillar-shaped semiconductor layer and a second diffusion layer of P-type conduction arranged on a dielectric film formed on the substrate, hierarchically in a vertical direction; the first pillar-shaped semiconductor layer is arranged between the first diffusion layer formed on the bottom of the first pillar-shaped semiconductor layer and the second diffusion layer formed on the top of the first pillar-shaped semiconductor layer; and a gate is formed along a sidewall of the first pillar-shaped semiconductor layer; the first and second NMOS driver transistors comprise a third diffusion layer of N-type conduction, a second pillar-shaped semiconductor layer and a fourth diffusion layer of N-type conduction arranged on the dielectric film formed on the substrate, hierarchically in a vertical direction; the second pillar-shaped semiconductor layer is arranged between the third diffusion layer formed on the bottom of the second pillar-shaped semiconductor layer and the fourth diffusion layer formed on the top of the second pillar-shaped semiconductor layer; and a gate is formed along a sidewall of the second pillar-shaped semiconductor layer; the first PMOS access transistor and the first NMOS driver transistor are arrayed in adjacent relation to each other; the second PMOS access transistor and the second NMOS driver transistor are arrayed in adjacent relation to each other; the first diffusion layer of P-type conduction formed on the bottom of the first PMOS access transistor and the third diffusion layer of N-type conduction formed on the bottom of the first NMOS driver transistor, are arranged on the dielectric film to serve as a first storage node for holding data therein, wherein the first diffusion layer and the third diffusion layer serving as the first storage node are connected to each other through a first silicide layer formed on respective surfaces of the first and third diffusion layers serving as the first storage node; and the first diffusion layer of P-type conduction formed on the bottom of the second PMOS access transistor and the third diffusion layer of N-type conduction formed on the bottom of the second NMOS driver transistor, are arranged on the dielectric film to serve as a second storage node for holding data therein, wherein the first diffusion layer and the third diffusion layer serving as the second storage node are connected to each other through a second silicide layer formed on respective surfaces of the first and third diffusion layers serving as the second storage node.