Patent ID: 9172334
Filing Date: 2015-10-27
Classification: H03F,H04B

Abstract:
1. A digital predistortion system with extended correction bandwidth, comprising: a dynamic nonlinear predistorter block having an input accepting an input signal to be predistorted, and an output; a memoryless, offline determinable, nonlinear predistorter block having an input, an output, and a select input, the dynamic nonlinear predistorter block output being connected to the input of the memoryless, offline determinable, nonlinear predistorter block; a memoryless nonlinearity selector block having an input and an output, the dynamic nonlinear predistorter block output being connected to the memoryless nonlinearity selector block's input, output of the selector block being connected to the select input of the memoryless, offline determinable, nonlinear predistorter block, the selector block selecting a single memoryless predistortion function based on the input signal's average power, the output of the memoryless nonlinear predistorter block comprising a digital output signal derived from the selected memoryless predistortion function; a digital-to-analog converter (DAC) having an analog output, and an input that accepts the digital output signal of the memoryless nonlinear predistorter block; a frequency up-conversion stage (UCS) having an output, and an input that accepts the DAC output; a power amplifier (PA) having an output, and an input that accepts the UCS output; a feedback path carrying signal characteristics of the power amplifier output, wherein said feedback path has a reduced bandwidth due to application of the memoryless DPD function to the PA; a down-conversion stage (DCS) having an input accepting a portion of the power amplifier output signal characteristics, and an output; an analog-to-digital-converter (ADC) having an input connected to the DCS output; a processor running a DPD coefficients identification algorithm, the processor accepting output from the dynamic nonlinear block and output of the ADC for processing by the DPD coefficients identification algorithm, the processor outputting DPD coefficients, as determined by the DPD coefficients identification algorithm, to the dynamic nonlinear block, wherein a function of the dynamic nonlinear digital predistorter based on the identified DPD coefficients is applied to the input signal being transmitted, the PA being linearized by the memoryless DPD function and the dynamic nonlinear DPD function.