Patent ID: 9209196
Filing Date: 2015-12-08
Classification: G09G,G11C,H01L

Abstract:
1. A memory circuit comprising a memory transistor having a transistor structure, the transistor structure including a source electrode, a drain electrode, and a gate electrode; and a source region, a drain region and a channel region each configured by a metal oxide semiconductor, wherein the memory transistor holds either one of a first state and a second state in a non-volatile manner, the first state indicating that a current flows depending upon a voltage application state of the source electrode and the drain electrode of the transistor structure with a current-voltage characteristic depending upon a voltage application state of the gate electrode of the transistor structure, and the second state indicating an ohmic resistance property relative to a voltage applied to the source electrode and the drain electrode, regardless of the voltage application state of the gate electrode, the resistance property between the source and the drain region transitions to a lower resistance, and the state of the memory transistor is changed from the first state to the second state by the current flowing between the source region and the drain region of the transistor structure, and a channel length of the transistor structure is smaller than the width of the gate electrode extending at an outside of the channel region.