Patent ID: 8110928
Filing Date: 2012-02-07
Classification: H01L

Abstract:
1. A stacked-type chip package structure, comprising: a first package structure, comprising: a first substrate having a first surface and a second surface; and a first chip disposed on the first surface of the first substrate and electrically connected to the first substrate; and a second package structure stacked on the first package structure, comprising: a second substrate having a third surface and a fourth surface and electrically connected to the first substrate; a second chip disposed on the third surface of the second substrate and electrically connected to the second substrate, wherein an adhesive layer is in direct contact with the first chip and the second chip; and a plurality of solder blocks disposed on the fourth surface of the second substrate; and a first molding compound disposed on the first substrate and encapsulating the first package structure and the second package structure, wherein the first molding compound has a recess and a bottom surface of the recess is coplanar with top surfaces of the solder blocks, and the first molding compound that encloses and fills between the solder blocks is located between the top surfaces of the solder blocks and the fourth surface of the second substrate.