Patent ID: 7362635
Filing Date: 2008-04-22
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a control signal generator for combining externally supplied command signals to generate a test signal; a set/reset signal generator for receiving an externally supplied mode setting signal in response to the test signal and generating a first set/reset signal when the mode setting signal is a signal that designates an individual set/reset; a test logic portion for storing and subsequently outputting the mode setting signal in response to the test signal; a set/reset master signal generator for receiving the first set/reset signal to output a set/reset master signal for commonly controlling a test mode of internal blocks of the semiconductor memory device; and a test control signal generator for processing an output signal of the test logic portion to generate a plurality of control signals and generating a plurality of test control signals as the set/reset master signal in response to the plurality of control signals.