Patent ID: 7846815
Filing Date: 2010-12-07
Classification: B81C,H01L

Abstract:
1. A semiconductor fabrication process, comprising: forming a first bonding structure on a first surface of a cap wafer; forming a device cavity in the first surface of the cap wafer; forming a second bonding structure on a first surface of a device wafer; forming a device structure on the device wafer; forming a eutectic flow containment structure on at least one of the cap wafer and the device wafer, the eutectic flow containment structure comprising an exterior flow containment micro-levee (FCML), the exterior FCML comprising an elongated ridge overlying the first surface of the device wafer and extending substantially parallel to the second bonding structure, wherein a perimeter of the exterior FCML encloses a perimeter of the second bonding structure; and bringing the first and second bonding structures into contact while maintaining at least one of the cap wafer and the device wafer at a predetermined temperature to create a eutectic bond from the first and second bonding structures.