Patent ID: 6463110
Filing Date: 2002-10-08
Classification: H03H,H04L

Abstract:
A method for performing timing synchronization between digital input data and a system clock in a communication device, the method comprising the steps of:(a) providing a system clock rate that is higher than a data clock rate, the system clock providing a plurality of system clock periods per one data clock period; (b) sampling the input data at intervals in the system clock periods within the data clock period; (c) adjusting the timing between the digital input data and the system clock such that (d) advancing the timing of the input data in relation to the system clock includes the substeps of: (d1) shortening the number of system clock periods in relation to the data clock period, and shortening the sampling intervals; (d2) sampling the input data at the shortened intervals defined in the previous step, and (e) delaying the timing of the input data in relation to the system clock includes the substeps of: (e1) lengthening the number of system clock periods in relation to the data clock period; (e2) sampling the input data at normal intervals and performing an extra data insertion to fill one of the extra system clock periods, such that more samples are provided in the data clock period; and (f) outputting the sampled input data for the data clock period.