Patent ID: 6477105
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory cells arranged in rows and columns; and a plurality of sub-word lines provided corresponding to the rows of memory cells and having the memory cells of corresponding rows connected thereto, said plurality of sub-word lines divided into a plurality of blocks along a row direction and divided into groups by a prescribed number along a column direction; a plurality of main word lines provided in common to said plurality of blocks, extending in the row direction and corresponding to the respective groups of the sub-word lines; a main word line selecting circuit for driving an addressed main word line to a selected state according to a first address bit of a multi-bit address signal; a sub-decode circuit for generating complementary decode fast signals for designating a sub-word line within each group of said sub-word lines according to the multi-bit address signal excluding said first address bit; a sub-word line selecting circuit for generating complementary sub-word line select signals individually according to respective complementary decode fast signals from said sub-decode circuit, said complementary sub-word line select signals formed via separate paths; and a plurality of sub-word line drive circuits provided corresponding to the sub-word lines for driving corresponding sub-word lines to a selected state according to signals on corresponding main word lines and said complementary sub-word line select signals.