Patent ID: 6459647
Filing Date: 2002-10-01
Classification: G11C

Abstract:
A memory device, comprising:a plurality of input/outputs (I/Os); and a memory core coupled to the plurality of I/Os arranged to store data as at least a first data word and a second data word, wherein the memory core includes, a first bank segment in close proximity to a first one of the plurality of I/Os, wherein the first bank segment is arranged to store a first portion of the first data word, a second bank segment in close proximity to a second one of the plurality of I/Os wherein the second bank segment is arranged to store a second portion of the first data word, and wherein the second bank segment is logically coupled to the first bank segment to form a first virtual memory bank such that in response to a first bank select signal the first bank segment and the second bank segment respectively output the first portion and the second portions of the first data word, and wherein a first signal path from the first bank segment and the first one of the plurality of I/Os and a second signal path from the second bank segment and the second one of the plurality of I/Os are substantially equal such that a first delay time between the first bank segment and the first one of the plurality of I/Os and a second delay time between the second bank segment and the second one of the plurality of I/Os are substantially equal.