Patent ID: 6649479
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method for fabricating a MOSFET device, comprising the steps of:providing a substrate having a first surface; providing first and second insulation layers in the substrate to divide the substrate into a first active region between the first and second insulation layers and an isolation region outside of the first active region; etching an area of the first active region of the substrate to form a second surface in parallel with and below the first surface and a third surface extending from the second surface to the first surface; implanting a first conductivity type punch through stopper impurity into the first, second, and third surfaces of the substrate; forming a first gate on the third surface of the substrate; forming source/drain regions by implanting a second conductivity type impurity into the first and second surfaces of the substrate in areas laterally adjacent to the first gate; exposing portions of the source/drain regions; forming first contacts on an upper surface of the exposed portions of the source/drain regions; forming a second active region on the substrate; etching an area of the second active region to form a fourth surface parallel with and below the first surface and a fifth surface extending from the fourth surface to the first surface of the substrate in the second active region; forming a second gate integrally connected with the first gate on the fifth surface of the substrate; exposing a region of the second gate; and forming a second contact on the exposed region of the second gate.