Patent ID: 8849226
Filing Date: 2014-09-30
Classification: H04B

Abstract:
1. A receiver operable according to a standard to decode digital data from an analog signal, comprising an analog front-end and a digital decoder, wherein the analog front-end comprises a plurality of analog components including an analog signal input for receiving the analog signal, at least one amplifier arranged to amplify the analog signal, and an analog-to digital converter (ADC) arranged to convert the amplified analog signal into a digital signal, and wherein the digital decoder comprises a digital signal input connected to the output of the ADC and a demodulator comprising a plurality of digital components connected to be driven by a clock signal having a chip frequency, the digital components including: a sampler operable to sample the digital signal at a sampling frequency which is a multiple of the chip frequency; a correlation unit operable to process a set of bits, referred to as a symbol, in the sampled digitized signal using a double correlation function and output therefrom a set of correlation values, wherein the set of correlation values is an indicator of likely mapping between the symbol that has been processed and a set of possible symbols defined according to the standard; a symbol selection unit having the function of deciding which symbol has been received based on an analysis of each set of correlation values; and a frequency correction unit operable to output a frequency control signal for momentary adjustment of the chip frequency dependent upon the correlation values output from the correlation unit.