Patent ID: 6316302
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method for forming an integrated circuit, comprising:providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor;subsequent to said implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor, forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors;implanting the first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; andimplanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness.