Patent ID: 6919226
Filing Date: 2005-07-19
Classification: H01L,H05K

Abstract:
1. A method for producing a multi-chip circuit module comprising: forming a first release layer over a surface of a planarized first base substrate; a first-layer forming step of forming a first wiring layer, obtained by forming an insulating layer over said first release layer, forming a predetermined circuit pattern over or in said insulating layer; applying metal plating over the predetermined circuit pattern, and planarizing a surface of said first-layer wiring layer circuit pattern, said first layer forming step is repeated one or more times to form a multi-layer wiring section wherein each layer is connected to the next via interlayer interfaces; a first semiconductor chip mounting step of mounting one or more semiconductor chips over a surface of the uppermost wiring layer of said multi-layer wiring section; a first connection terminal forming step of forming a first connection terminal on a surface of said uppermost wiring layer, a first sealing resin layer forming step of forming a sealing resin layer for sealing said semiconductor chip and said connection terminal over the surface of said uppermost wiring layer; a first polishing step of performing polishing processing on said sealing resin layer for reducing the size of said semiconductor chip, connection terminal, and said sealing resin layer; and a first peel-off step of peeling the multi-layer wiring section from said first base substrate via said first release layer.