Patent ID: 6219687
Filing Date: 2001-04-17
Classification: G06F,G11C,H03K

Abstract:
A sum/HPG adder that adds two N-NARY addends that comprise 1 of N signals to produce an N-NARY sum that comprises a 1 of N signal and an N-NARY HPG indicator that comprises a 1 of N signal, comprising:a 1-of-P first addend input configured to receive the first addend wherein said 1 of P first addend input comprises a 1 of N signal where N is greater than 2;a 1-of-Q second addend input configured to receive the second addend wherein said 1 of Q second addend input comprises a 1 of N signal where N is greater than 2;a sum/HPG circuit that adds the first and second addends to produce the sum and that performs carry propagate logic to produce the HPG indicator; andsaid sum/HPG circuit is coupled to said first addend input and said second addend input, said sum/HPG circuit is further coupled to a 1-of-R sum output that is configured to produce the sum wherein said 1 of R sum output comprises a 1 of N signal where N is greater than 2, and said sum/HPG circuit is further coupled to a 1-of-S HPG output that is configured to produce the HPG indicator wherein said 1 of S HPG output comprises a 1 of N signal where N is greater than 2.