Patent ID: 7781859
Filing Date: 2010-08-24
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a semiconductor substrate of p-type; an n-type well region over the semiconductor substrate; a metal-containing layer on the n-type well region, wherein the metal-containing layer and the n-type well region form a Schottky barrier; a shallow trench isolation (STI) ring encircling and contacting the metal-containing layer; a p-type ring in the n-type well region, wherein the p-type ring overlaps outer portions of the metal-containing layer and inner portions of the STI ring; and a deep p-well region under the metal-containing layer, wherein the deep p-well region comprises a solid p-well plate vertically overlapping an entirety of the metal-containing layer, wherein the n-type well region adjoins the metal-containing layer and the deep p-well region, and wherein the deep p-well region has an impurity concentration higher than impurity concentrations of the semiconductor substrate, the n-type well region, and the p-type ring.