Patent ID: 7626236
Filing Date: 2009-12-01
Classification: H01L,Y10S

Abstract:
1. A transistor device comprising: a first semiconductor region, a first ferromagnetic member electrically contacting the first semiconductor region and having a first coercivity, a second semiconductor region, a second ferromagnetic member electrically contacting the second semiconductor region and having a second coercivity that is smaller than the first coercivity, a third semiconductor region separating the first and second semiconductor regions, an electrically conductive gate positioned over the third semiconductor region, an electrically insulating layer disposed between the gate and the third semiconductor region, the electrically insulating layer including a number of paramagnetic impurities each having two spin states such that electrons interacting with the paramagnetic impurities cause the paramagnetic impurities to flip between the two spin states, a first voltage source configured to apply a first voltage to the gate, the first voltage configured to induce an electrically conductive channel in the third semiconductor region, and a second voltage source configured to apply a second voltage across the first and second semiconductor regions, the second voltage configured to cause the number of paramagnetic impurities to become spin polarized.