Patent ID: 6829701
Filing Date: 2004-12-07
Classification: G06F

Abstract:
An apparatus comprising:a watchpoint register adapted to store a watchpoint address; a comparator to compare the watchpoint address to program addresses associated with instructions submitted in a first stage of a processor pipeline; a watchpoint generator to generate a watchpoint match when a program address equals the watchpoint address, wherein the watchpoint register includes a first watchpoint register to be loaded with a first watchpoint address, and a second watchpoint register to be loaded with a second watchpoint address, the comparator being configured to compare the first and second watchpoint addresses to program addresses associated with instructions to be submitted to the processor pipeline, and the watchpoint generator being configured to generate a watchpoint match when the program address is to be in a range defined by the first and second watchpoint addresses; a counter to generate a count value in a second stage of the processor pipeline, the count value to represent the number of watchpoint matches; a trigger circuit to trigger a request when the count value exceeds a trigger threshold; and a controller to adjust the count value when one of the instructions associated with one of the watchpoint matches is to be killed or stalled at a later stage in the pipeline, wherein the range is to be an inclusive range that is to extend between the first and second watchpoint addresses, or an exclusive range outside a range that is to extend between the first and second watchpoint addresses.