Patent ID: 9040404
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A method of fabricating a replacement metal gate structure for a CMOS device on a semiconductor substrate comprising: forming a high dielectric constant (high-k) dielectric on an nFET portion of the CMOS device and on a pFET portion of the CMOS device; forming a dummy gate structure on the high-k dielectric of the nFET portion of the CMOS device and on the high-k dielectric of the pFET portion of the CMOS device, each of the dummy gate structures comprising a layer of nitride, a layer of polysilicon or amorphous silicon and a nitride hard mask; forming spacers on the dummy gate structures; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess bounded by the spacers on the nFET portion and a recess bounded by the spacers on the pFET portion, the recesses having high-k dielectric only on a bottom of each of the recesses; depositing a first layer of titanium nitride into the recesses in contact with the high-k dielectric on the nFET portion and pFET portion, the first layer of titanium nitride being present only the high-k dielectric in the nFET portion and pFET portion; removing the first layer of titanium nitride from the nFET portion only to expose the high-k dielectric; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion, the second layer of titanium nitride being in direct contact with the high-k dielectric in the nFET portion and in direct contact with the first layer of titanium nitride in the pFET portion; depositing titanium aluminum onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion; and filling the remainder of the cavity on the nFET portion and pFET portion with a metal different from titanium aluminum.