Patent ID: 7277332
Filing Date: 2007-10-02
Classification: G11C

Abstract:
1. An I/O interface including a buffer circuit comprising: a memory including a plurality of registers; a write register selector configured to operate in synchronism with a write clock signal and to output a plurality of write enable signals corresponding to said plurality of registers, respectively, and enabling a first selected one of the plurality of registers, one at a time and in a first predetermined sequence, to be written with data; a read register selector configured to operate in synchronism with a read clock signal and to output a plurality of read enable signals corresponding to said plurality of registers, respectively, and enabling a second selected one of the plurality of registers, one at a time and in a second predetermined sequence, to be read; and an address proximity detector configured to detect an event in which a difference in position between a register write-enabled by one of the write enable signals and a different register read-enabled by one of the read enable signals among the plurality of registers is equal to a predetermined value and to output a reset signal upon detecting such event.