Patent ID: 6847564
Filing Date: 2005-01-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells each of which is connected between a bit line and a word line and which store cell data; a plurality of sense amplifiers which are connected to the plurality of memory cells, respectively and which read cell data from the memory cells and write cell data to the memory cells, respectively; a plurality of sense amplifier write circuits which are connected to the plurality of sense amplifiers, respectively and which write cell data to the sense amplifiers, respectively; a plurality of data lines which are connected to the plurality of sense amplifier write circuits, respectively and to which the cell data to be written to the sense amplifiers is written; a data line shift circuit which shifts an arbitrary one of the data lines and replaces the arbitrary one with a data line adjacent thereto; a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively; and a plurality of mask circuits which are provided for a given number of data mask lines of the plurality of data mask lines and which supply a mask signal, which invalidates write of the cell data to a given number of data lines, to the sense amplifier write circuits connected to the given number of data mask lines, wherein the plurality of mask circuits each include at least one shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to a same mask circuit as that before the data line is shifted, not through the shift switch circuit.