Patent ID: 8836374
Filing Date: 2014-09-16
Classification: H03F,H03K

Abstract:
1. A buffer for use in a communications system, said buffer comprising: first and second differential blocks; each of said first and second differential blocks including at least one driving transistor for generating a driving current for a load, a gate of said at least one driving transistor receiving a first common mode bias voltage depending at least in part on a threshold voltage of said at least one driving transistor; a first feedback path configured to adjust an operation of said at least one driving transistor of said first differential block and including a first feedback transistor that receives a second common mode bias voltage of said first feedback path depending at least in part on a threshold voltage of said first feedback transistor; and a second feedback path configured to adjust an operation of said at least one driving transistor of said second differential block and including a second feedback transistor that receives a second common mode bias voltage of said second feedback path depending at least in part on a threshold voltage of said second feedback transistor, wherein the first feedback path is separate from the second feedback path, and the first feedback path includes a voltage divider that provides a divided voltage to a capacitor, and the divided voltage stored on the capacitor controls a control transistor that adjusts the operation of the at least one driving transistor of the first differential block.