Patent ID: 8773168
Filing Date: 2014-07-08
Classification: G01R

Abstract:
1. A sub-selection circuit, comprising an enable mode circuit and a disable mode circuit, wherein the enable mode circuit includes a comparator, and is configured to operate when an operating mode signal is an enable signal, and to set itself to an output enable state, set other sub-selection circuits to an output disable state, and output its input voltage as a maximum voltage through a P-type metal oxide semiconductor field effect transistor (PMOS transistor) when its input voltage is larger than a reference voltage, and wherein the disable mode circuit includes a power latch, and is configured to operate when the operating mode signal is a disable signal, and to set itself to the output enable state, set other sub-selection circuits to the output disable state, and output its input voltage as the maximum voltage through the PMOS transistor when its input voltage is larger than the reference voltage.