Patent ID: 6112307
Filing Date: 2000-08-29
Classification: G06F,H04L

Abstract:
In a data processing system having a fast clock and a slow clock, wherein the slow clock has a frequency that is an integer submultiple of the fast clock, a method for synchronizing a data signal in the slow clock domain with the fast clock, wherein the data signal in the slow clock domain is stable at a time displaced from a change of state of the slow clock, said method comprising the steps of:(a) generating a clock base signal at a frequency that is an integer submultiple of the slow clock and that is phase synchronized with the fast clock;(b) generating a sync pulse signal responsive to the clock base signal, said sync pulse signal having a frequency that is an integer multiple of the clock base signal and that is phase synchronized with the fast clock for any of a range of stable phase relationships between the fast clock and the slow clock, so as to be displaced by a predetermined time from the clock base signal;(c) generating a data signal in the fast clock domain by gating the slow clock domain data signal with the sync pulse signal while both the fast and slow clocks remain unchanged.