Patent ID: 9064894
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method of forming a device comprising: providing a substrate having a device region surrounded by a device isolation region, wherein the device region comprises a source region, a gate region and a drain region defined thereon; forming a gate in the gate region, a source in the source region and a drain in the drain region to form a transistor; forming an internal isolation region which comprises isolation material, wherein the internal isolation region displaces the drain from a drain side of the gate and underlaps a portion of the gate on the drain side of the gate; partially recessing the isolation material of the internal isolation region to form a first secondary trench in the internal isolation region, wherein a width of the first secondary trench is smaller than a width of the internal isolation region; forming an etch stop (ES) stressor layer over the substrate, wherein the ES stressor layer lines the transistor and first secondary trench without filling the first secondary trench to leave a trench gap; and forming a dielectric layer on the substrate, the dielectric layer covering the transistor and filling the trench gap over the ES stressor layer.