Patent ID: 6549047
Filing Date: 2003-04-15
Classification: H03K,H03L

Abstract:
A semiconductor integrated circuit device comprising:a first variable delay circuit receiving an input clock signal and having first delay circuits each capable of delaying an input signal, the first variable delay circuit having a plurality of stages of said first delay circuits; a second variable delay circuit, coupled to the first delay circuit and outputting an output clock signal, wherein the second delay circuit has second delay circuits, each having a signal delay function having a precision higher than that of the first variable delay circuit, the second variable delay circuit having a plurality of stages of said second delay circuits; first and second phase comparator circuits respectively performing phase comparing operations on the input clock signal and the output clock signal with respective precisions of the first and second variable delay circuits; first and second delay control circuits respectively controlling delay times of the first and second variable delay circuits on the basis of results of the phase comparing operations; and a number-of-stages setting circuit determining a number of stages of the second variable delay circuit on the basis of a first delay time obtained when the input clock signal passes through n stages of the second variable delay circuit and a second delay time obtained when the input clock signal passes through n+1 stages thereof.