Patent ID: 6260107
Filing Date: 2001-07-10
Classification: G11C,H04N

Abstract:
A processor system comprising:a memory having a plurality of memory banks formed on a single chip, wherein said memory operates in synchronism with a clock signal generated externally from said memory; anda data processor formed on a single chip,wherein said data processor includes:a microprocessor; anda controller coupled to said microprocessor via an address bus and coupled to said memory;wherein said controller includes:an address register for latching an access address received from said address bus;a comparator for comparing a bank field information part of an access address of a preceding bus cycle latched in said address register and a bank field information part of an access address of a succeeding bus cycle; anda memory access control unit for delivering a bank operation start signal to said memory for requesting parallel operations of two accesses in respective memory banks corresponding to said access addresses, in response to an output of said comparator, when said bank field information parts are different from each other.