Patent ID: 6744664
Filing Date: 2004-06-01
Classification: G11C,H01L

Abstract:
A dual-bit floating-gate flash cell structure, comprising:a semiconductor substrate of a first conductivity type; a cell region being formed on said semiconductor substrate, wherein said cell region comprises a gate region being formed between a common-source region and a common-drain region; said gate region comprising a pair of floating-gates being defined by a pair of second sidewall dielectric spacers and a select-gate dielectric layer being formed between said pair of floating-gates, wherein a first portion of a tunneling dielectric layer is formed under each of said pair of floating-gates and an implant region of said first conductivity type is formed in a surface portion of said semiconductor substrate under said select-gate dielectric layer; said common-source/drain region comprising a common-source/drain diffusion region of said second conductivity type being formed in a surface portion of said semiconductor substrate, a pair of etched-back first sidewall dielectric spacers being formed over a second portion of the tunneling dielectric layer, and an etched-back first planarized thick-oxide layer being formed between said pair of etched-back first sidewall dielectric spacers; a word line over an intergate dielectric layer being formed over said pair of floating-gates and said select-gate dielectric layer in said gate region and over said etched back first planarized thick-oxide layer and said pair of etched-back first sidewall dielectric spacers in each of said common-source/drain regions; and two cell isolation regions being separately formed outside of said word line and between said common-source/drain regions.