Patent ID: 6366973
Filing Date: 2002-04-02
Classification: G06F

Abstract:
A pipelined interface circuit comprising:an input latch circuit for receiving and holding address and size signals from a first bus domain; a hold circuit for receiving and holding outputs from said input latch circuit and for receiving and holding data signals from said first bus domain wherein said data signals arrive one clock cycle after said address and size signals; a first data translate and replicate circuit coupled to said hold circuit and for reformatting said data signals into first formatted data signals which are formatted for a second bus domain; and a request circuit for receiving outputs from said first data translate and replicate circuit and for receiving outputs from said hold circuit, said request circuit for generating a request to said second bus domain and for simultaneously providing said second bus domain with said address signals, said first reformatted data signals and byte enable signals and wherein said input latch circuit, said hold circuit and said request circuit are all clocked by a clock signal of said first bus domain.