Patent ID: 7962730
Filing Date: 2011-06-14
Classification: G06F

Abstract:
1. A processor comprising: a scheduling unit configured to schedule a first memory operation to be executed; and a load/store unit coupled to receive first state corresponding to the first memory operation in response to execution of the first memory operation, and the load/store unit comprises a queue including a first entry that is assigned to the first memory operation prior to the first memory operation being written to the scheduling unit, and the load/store unit is configured to detect whether or not the first entry is occupied by second store state corresponding to a previously retired store memory operation that has not been completed, and the scheduling unit is configured to delete the previously retired store memory operation to retire the previously retired store memory operation responsive to the processor having processed the previously retired store memory operation at least to a point at which precise exceptions are reported for the previously retired store memory operation but prior to store data corresponding to the previously retired store operation being committed to memory, and the load/store unit is configured to signal a replay of the first memory operation responsive to detecting that the first entry is occupied by the second store state to preserve the second store state in the first entry, and the load/store unit is configured to write the first state to the first entry responsive to detecting that the first entry is not occupied by the second store state.