Patent ID: 7767494
Filing Date: 2010-08-03
Classification: H01L

Abstract:
1. A method of manufacturing a layered chip package, the layered chip package comprising: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes: a semiconductor chip having a top surface, a bottom surface and four side surfaces; an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and a plurality of electrodes connected to the semiconductor chip; the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, the method comprising the steps of: fabricating a layered substructure by stacking a plurality of substructures in correspondence with the order of stacking of the plurality of layer portions of the layered chip package, wherein the plurality of substructures respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and fabricating a plurality of layered chip packages by using the layered substructure, wherein: the step of fabricating the layered substructure includes: a step of fabricating a first pre-polishing substructure by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the first pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device; a step of fabricating a second pre-polishing substructure by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the second pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device; a step of bonding the first pre-polishing substructure to a jig such that the first surface of the first pre-polishing substructure faces the jig; a first polishing step for polishing the second surface of the first pre-polishing substructure bonded to the jig so that the first pre-polishing substructure is thinned by the polishing forming a polished surface and thereby a first substructure is formed in a state of being bonded to the jig; a step of bonding the second pre-polishing substructure to the first substructure such that the first surface of the second pre-polishing substructure comes in direct contact with the first substructure at its intact polished surface; and a second polishing step for polishing the second surface of the second pre-polishing substructure so that the second pre-polishing substructure is thinned by the polishing and thereby a second substructure is formed in a state of being stacked on the first substructure.