Patent ID: 6200905
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method to form sidewall capacitors while forming MOS transistor gates in the manufacture of an integrated circuit device comprising:forming conductive lines overlying a semiconductor substrate wherein some of said conductive lines form the bottom plates for said sidewall capacitors and wherein others of said conductive lines form said MOS transistor gates;depositing a silicon dioxide layer overlying said conductive lines;depositing a dielectric layer overlying said silicon dioxide layer;depositing a conductive layer overlying said dielectric layer;etching down said conductive layer to form conductive sidewall spacers on said dielectric layer of said MOS transistor gates and to form the top plates between each two of said bottom plates for said sidewall capacitors; andetching away said conductive sidewall spacers while protecting said top plate with a protective mask to complete formation of said sidewall capacitors while forming said MOS transistor gates in the manufacture of said integrated circuit device.