Patent ID: 8719827
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A processor for executing a plurality of tasks by switching a timeslot, the processor comprising: a first table in which tasks are defined in correspondence with a plurality of timeslots, each timeslot of the plurality of timeslots corresponding to a plurality of the tasks as candidate tasks to be executed in the timeslot, the first table including option information comprising sleep option for at least one of the plurality of timeslots; a second table in which states are shown in correspondence with the tasks in the plurality of timeslots, and a scheduling control unit configured to select a task by referring to the first table and the second table in correspondence with switching of timeslot; wherein a timeslot is switched every time a predetermined period elapses, and at a time when a certain timeslot starts, the scheduling control unit selects the sleep option for the certain timeslot based upon the option information defined in the first table for the certain timeslot, even if the second table shows a ready task exists during the certain timeslot, and then the processor is put into a sleep mode instead of executing the ready task.