Patent ID: 6873565
Filing Date: 2005-03-29
Classification: G11C

Abstract:
1. A dual-port read SRAM cell for reducing soft errors comprising: a) a cross-coupled latch, the cross-coupled latch having an input/output, and an input; b) a first transfer device, the first transfer device having an input, a control input, and a output; c) a second transfer device, the second transfer device having an input, a control input, and a output; d) a third transfer device, the third transfer device having an input, a control input, and a output; e) a fourth transfer device, the fourth transfer device having an input, a control input, and a output; f) a first pull-down device, the first pull-down device having an input, a control input, and a output; g) a second pull-down device, the second pull-down device having an input, a control input, and a output; h) a third pull-down device, the third pull-down device having an input, a control input, and a output; i) wherein the input/output of the cross-coupled latch is connected to the input of the fourth transfer device, the control input of the fourth transfer device is connected to a third bitline, and the output of the fourth transfer device is connect to the output of the third pull-down device; j) wherein the control input of the third pull-down device is connected to a third wordline, and the input of the third pull-down device is connected to ground; k) wherein the input of the cross-coupled latch is connected to the output of the first transfer device, the control input of the first transfer device is connected to a first wordline, and the input of the first transfer device is connected to a first bitline; l) wherein the input/output of the cross-coupled latch is connected to the control inputs of the first and second pull-down devices; m) wherein the output of the first pull-down device is connected to the input of the second transfer device, the control input of the second transfer device is connected to a second wordline, and the output of the second transfer device is connected to a second bitline; n) wherein the output of the second pull-down device is connected to the input of the third transfer device, the control input of the third transfer device is connected to the first wordline, and the output of the third transfer device is connected to the first bitline; o) wherein the inputs of the first and second pull-down devices connected to ground.