Patent ID: 6479332
Filing Date: 2002-11-12
Classification: H01L,Y10S

Abstract:
A method of fabricating an integrated circuit, comprising:forming a lower conductive layer over a semiconductive substrate; forming a first insulative material over the lower conductive layer; forming a middle conductive layer over the first insulative material, the middle conductive layer having a side surface; forming a second insulative material over the middle conductive layer, the second insulative material having a side surface, and wherein the side surfaces of the middle conductive layer and the second insulative material define a common lateral sidewall; forming an upper conductive layer over the second insulative material, the middle conductive layer being electrically insulated from the lower and upper conductive layers by the first and second insulative layers; forming an electrically insulating material against the common lateral sidewall to cover the side surfaces of the middle conductive layer and the second insulative material; forming an electrically conductive link electrically interconnecting the upper conductive layer and the lower conductive layer, the electrically conductive link being electrically insulated from the middle conductive layer by the electrically insulating material against the side surface of the middle conductive layer, the electrically conductive link joining the upper conductive layer at a location above the side surface of the middle conductive layer, and joining the lower conductive layer at a location below the side surface of the middle conductive layer; and wherein each of the upper, lower and middle conductive layers comprises polysilicon.