Patent ID: 6954379
Filing Date: 2005-10-11
Classification: G11C

Abstract:
1. A power-on reset circuit in a flash EPROM memory comprising: a first capacitor with one terminal grounded and the other terminal connected to a first node; a first resistor with one terminal tied to V a plurality of inverters wherein the input of said plurality of said inverters is connected to said first node and the output of said plurality of inverters is connected to the circuit output; a latch comprised of a first and second inverter wherein the input of said first inverter and the output of said second inverter are connected to said first node and the input of said second inverter and the output of said first inverter are connected to a second node; a second capacitor with one terminal connected to V a first MOSFET with the drain terminal connected to said second node, the source terminal connected to ground and the gate terminal connected to a third node; a second resistor with one terminal connected to said third node and the other terminal connected to ground; a third resistor with one terminal connected to said third node and the other terminal connected to a fourth node; and a second MOSFET with the drain terminal connected to V