Patent ID: 8373235
Filing Date: 2013-02-12
Classification: H01L

Abstract:
1. A semiconductor memory device comprising multiple static memory cells, each of the multiple static memory cells including six MOS transistors arranged on a substrate, wherein the six MOS transistors serve as first and second NMOS access transistors for accessing the memory, first and second NMOS driver transistors for driving a memory node in order to retain data in the memory cells, and first and second PMOS load transistors for supplying electric charge in order to retain data in the memory cells, respectively; each of the first and second NMOS access transistors comprise a first diffusion layer, a first columnar semiconductor layer and a second diffusion layer of each of the first and second NMOS access transistors for accessing the memory are arranged on the substrate in layers in a vertical direction, the first columnar semiconductor layer being arranged between the first diffusion layer and the second diffusion layer, and an access transistor gate resides on a side wall of the columnar semiconductor layer; each of the first and second NMOS drive transistors comprise a third diffusion layer, a second columnar semiconductor layer, and a fourth diffusion layer of each of the first and second NMOS driver transistors for driving a memory node in order to retain data in the memory cells are arranged on the substrate in layers in the vertical direction, the columnar semiconductor layer being arranged between the third diffusion layer and the fourth diffusion layer, and a drive transistor gate resides on a side wall of the columnar semiconductor layer; each of the first and second PMOS load transistors comprise a fifth diffusion layer, a third columnar semiconductor layer, and a sixth diffusion layer of each of the first and arranged on the substrate in layers in the vertical direction, where the third columnar semiconductor layer is between the fifth diffusion layer and the sixth diffusion layer, and a load transistor gate resides on a side wall of the columnar semiconductor layer; the first NMOS access transistor, the first NMOS driver transistor, and the first PMOS load transistor are arranged mutually adjacent; the second NMOS access transistor, the second NMOS driver transistor, and the second PMOS load transistor are arranged mutually adjacent; a first well in the substrate, the first well shared by the multiple memory cells for giving a potential to the substrate; wherein the first diffusion layer of the first NMOS access transistor resides at a bottom of the first NMOS access transistor and has an N-type conductivity, the third diffusion layer of the first NMOS driver transistor resides at a bottom of the first NMOS driver transistor and has an N-type conductivity, and the fifth diffusion layer of the first PMOS load transistor resides at a bottom of the first PMOS load transistor are mutually connected via a first silicide layer and form a first memory node for retaining data stored in the memory cells; first anti-leak diffusion layer layers having a conductive type different from the first well between the first well and first selected diffusion layers having the same conductive type as the first well among the first diffusion layer of the first NMOS access transistor, the third diffusion layer of the first NMOS driver transistor, and the fifth diffusion layers layer of the first PMOS load transistor and serving as the first memory node in order to prevent leaking between the first well and the first selected diffusion layer layers the first anti-leak diffusion is layers are directly connected to second selected diffusion layers having the same conductive type as the first anti-leak diffusion layers among the first diffusion layer of the first NMOS access transistor, third diffusion layer of the first NMOS driver transistor, and fifth diffusion layer of the first PMOS load transistor serving as the first memory node; wherein the first diffusion layer of the second NMOS access transistor resides at a bottom of the second NMOS access transistor and has an N-type conductivity, the third diffusion layer of the second NMOS driver transistor resides at a bottom of the second NMOS driver transistor and has an N type conductivity, and the fifth diffusion layer of the second PMOS load transistor resides at a bottom of the second PMOS load transistor and has a P-type conductivity and are mutually connected via a second silicide layer and form a second memory node for retaining data stored in the memory cells; and second anti-leak diffusion layers having a conductive type different from the first well and is formed between the first well and third selected diffusion layers having the same conductive type as the first well among the first diffusion layer of the second NMOS access transistor, the third diffusion layer of the second NMOS driver transistor, and the fifth diffusion layer of the second PMOS load transistor serving as the second memory node in order to prevent leaking between the first well and the third selected diffusion layers the second anti-leak diffusion layer are directly connected to fourth selected diffusion layers having the same conductive type as the second anti-leak diffusion layers among the first diffusion layer of the second NMOS access transistor, the third diffusion layer of the second NMOS driver transistor, and the fifth diffusion layer of the second PMOS load transistor serving as the second memory node.