Patent ID: 7187028
Filing Date: 2007-03-06
Classification: G11C

Abstract:
1. In a silicon on insulator (SOI) based memory device having three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising: at least one of the first NDR element and the second NDR element being implemented as a SOI-based NDR-capable FET, wherein a contact is provided to a body region of the SOI-based NDR capable FET so as to provide a bias signal and operate the SOI based memory device in a non-floating body effect mode, wherein said SOI-based NDR capable FET includes a charge trap region adapted for rapidly trapping and de-trapping charge to effectuate an NDR characteristic.