Patent ID: 6469400
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A semiconductor memory device comprising,a memory cell which is provided with a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor, and a second transfer transistor, wherein: the memory cell has a first gate electrode layer, a second gate electrode layer, a first drain-drain connecting layer, a second drain-drain connecting layer, a first drain-gate connecting layer, a second drain-gate connecting layer, a first contact-conductive section, a second contact-conductive section, a first interlayer dielectric, and a second interlayer dielectric; the first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor; the second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor; the first interlayer dielectric is located so as to cover the first and second gate electrode layers; the first and second drain-drain connecting layers are located over the first interlayer dielectric; the first and second gate electrode layers are located between the first and second drain-drain connecting layers; the first drain-drain connecting layer is used to connect a drain region of the first driver transistor to a drain region of the first load transistor; the second drain-drain connecting layer is used to connect a drain region of the second driver transistor to a drain region of the second load transistor; the second interlayer dielectric is located so as to cover the first drain-drain connecting layer and the second drain-drain connecting layer; the first and second drain-gate connecting layers are located over the second interlayer dielectric; the first drain-gate connecting layer is used to connect the first drain-drain connecting layer to the second gate electrode layer; the second drain-gate connecting layer is used to connect the second drain-drain connecting layer to the first gate electrode layer; the first contact-conductive section is located in a first hole formed in a region from the first interlayer dielectric to the second interlayer dielectric; the second contact-conductive section is located in a second hole formed in a region from the first interlayer dielectric to the second interlayer dielectric; the first drain-gate connecting layer is connected to the second gate electrode layer with the first contact-conductive section interposed; and the second drain-gate connecting layer is connected to the first gate electrode layer with the second contact-conductive section interposed.