Patent ID: 7911060
Filing Date: 2011-03-22
Classification: H01L

Abstract:
1. A wiring structure of a semiconductor device comprising: a wiring layer having an upper surface and a lower surface; an upper plug formed in a first insulating layer above the upper surface of the wiring layer; a lower plug formed in a second insulating layer below the lower surface of the wiring layer and opposite to the upper plug with the wiring layer interposed; and at least one cap layer interposed between the wiring layer and any one of the upper plug and the lower plug and positioned below any one of a plane defined by a substantial portion of the upper surface and a plane defined by a substantial portion of the lower surface, respectively, wherein, in a case that there is a single grain in a first region of the wiring layer between the upper plug and the lower plug, a size of the grain in the first region is substantially equal to a single grain in a second region of the wiring layer not between the upper plug and the lower plug and, in case that there are a number of grains in the first region, average size of the grains in the first region is substantially equal to the single grain in the second region.