Patent ID: 8344440
Filing Date: 2013-01-01
Classification: G11C,H01L

Abstract:
1. A complimentary metal-oxide-silicon (CMOS) integrated circuit (IC) comprising: a substrate; and a multi-terminal non-volatile memory (NVM) cell including: a first source region and a second source region, each including a first dopant diffused into the substrate such that the first source region is electrically isolated from the second source region; a drain region including a second dopant diffused into the substrate and disposed such that the drain region is separated from the first source region by a first channel region and separated from the second source region by a second channel region; and a polycrystalline silicon (polysilicon) floating gate including a first portion that is at least partially disposed over the first channel region, a second portion that is at least partially disposed over the second channel region, and a third portion that is at least partially disposed over the drain region; wherein the polycrystalline silicon floating gate, the first and second source regions and the drain region are formed such that a gate-drain capacitance between said polycrystalline silicon floating gate and said drain region is substantially higher than both a first gate-source capacitance between said polycrystalline silicon floating gate and said first source region, and a second gate-source capacitance between said polycrystalline silicon floating gate and said second source region, and wherein a first diffusion region extending from said drain region into the second channel region has a first doping concentration and a second diffusion region extending from said second source region into the second channel region includes a second doping concentration, the second doping concentration being different from the first doping concentration, wherein the first doping concentration of the first diffusion region is less than the second doping concentration of the second diffusion region.