Patent ID: 8853088
Filing Date: 2014-10-07
Classification: H01L

Abstract:
1. A method of forming a gate in a gate-last process, comprising: performing a first chemical mechanical polishing (CMP) on a first interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates comprising a gate mask in an upper portion thereof and spacers on opposing sidewalls thereof, and the first CMP exposing a surface of the gate mask; removing the gate mask by etching the gate mask, wherein etching the gate mask comprises partially recessing the spacers to provide partially-recessed top surfaces of the spacers; depositing a second ILD on the plurality of dummy gates and on the partially-recessed top surfaces of the spacers after removing the gate mask; and performing a second CMP on the second ILD, wherein a top surface of the second ILD is substantially coplanar with top surfaces of the plurality of dummy gates after performing the second CMP, and wherein the second ILD is on the partially-recessed top surfaces of the spacers after performing the second CMP.