Patent ID: 6014741
Filing Date: 2000-01-11
Classification: G06F

Abstract:
A microprocessor comprising:a microcode unit coupled to an instruction cache to receive a string instruction specifying a first register storing a string count, wherein said microcode unit is configured to dispatch a microcode routine in response to said string instruction, and wherein said microcode routine includes a first microcode instruction having said first register as an operand, said microcode routine further including one or more additional microcode instructions forming a loop iteration;an issue position coupled to a decode unit to receive said first microcode instruction from said microcode unit, wherein said issue position is configured to execute said first microcode instruction;wherein said microcode unit is coupled to said issue position to monitor information transmitted to and transmitted by said issue position to capture said string count, and wherein said microcode unit is configured to dispatch a number of said loop iterations specified by said string count; andwherein said first register is a source operand of said first microcode instruction, and wherein said microcode unit is configured to capture said string count concurrent with said issue position receiving said string count as said source operand of said first microcode instruction.