Patent ID: 6201725
Filing Date: 2001-03-13
Classification: G11C,H01L

Abstract:
A nonvolatile memory cell, comprising:a semiconductor substrate;a first well portion formed in and adjacent to a top surface of said semiconductor substrate;first and second impurity regions formed in the first well portion;a first gate electrode, formed above and between said first and second impurity regions of the first well portion;a control line for selecting said memory cell, connected to said first gate electrode;a bit line for reading data stored in said nonvolatile memory cell connected to said first impurity region of the first well portion;a second well portion formed in and adjacent to the top surface of said semiconductor substrate outside of said first well portion;first and second impurity regions formed in the second well portion, said first impurity region of said second well connected with a voltage supply line;a second gate electrode, formed above and between said first and second impurity regions of the second well portion; anda metalization layer connecting the second impurity region of the first well portion and the second impurity region of the second well portion.