Patent ID: 9071246
Filing Date: 2015-06-30
Classification: G06F,G11C,H03K,Y02D

Abstract:
1. A system comprising: a configurable memory controller including a plurality of configuration bits configured to indicate at least one of memory type, address, data width, and operating frequency; wherein the configurable memory controller comprise a configuration registers to store the plurality of the configuration bits and a mode register bits; a dedicated interface coupled to the configuration registers by a mode register data bus, wherein the dedicated interface is used by the user for setting the values in the configuration registers; a memory interface; and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array wherein each of the plurality of interconnect stations includes a first set of connectors and a second set of connectors wherein the first set of connectors is configured to couple to an adjacent interconnect station via a plurality of pipelined buses, wherein the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, wherein the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, wherein the second set of connectors is configured to connect to a programmable logic block (“PLB”).