Patent ID: 8320202
Filing Date: 2012-11-27
Classification: G11C

Abstract:
1. A system comprising: a first memory device and a second memory device; a first signal line coupled to the first memory device, the first signal line to provide first data, associated with a write command, to the first memory device; a second signal line coupled to the second memory device, the second signal line to provide second data, associated with the write command, to the second memory device; a termination component; a control signal path coupled to the first memory device, the second memory device, and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component; and a third signal line to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first memory device, wherein the clock signal also indicates when the write command propagating on the control signal path is to be sampled by the second memory device.