Patent ID: 6538489
Filing Date: 2003-03-25
Classification: H03K

Abstract:
A clock distributing circuit in a programmable logic device (PLD), which, through programming, can select one clock from a plurality of clocks and feed the selected clock to a plurality of logic circuits, said clock distributing circuit comprising:a selector which selects one clock from the plurality of input clocks through the programming and outputs the selected clock; a plurality of buffer circuits for distributing the clock sent from the selector to a plurality of clock lines to which the plurality of logic circuits are distributively connected; a plurality of first programmable connector elements for connecting a logic circuit as a connect object in the plurality of logic circuits to one of the plurality of clock lines according to the programming; a plurality of regulation loads connectable to the plurality of clock lines; and a plurality of second programmable connector elements for connecting the plurality of regulation loads to one of the plurality of clock lines according to the number of logic circuits, in the plurality of logic circuits, connected to the plurality of clock lines.