Patent ID: 7372758
Filing Date: 2008-05-13
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device comprising: a memory cell array employing a memory element as a memory cell wherein the memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies that are formed on both sides of the gate electrode and have a function to retain electric charges; and a lockout circuit that inhibits a command to a memory circuit including the memory cell array when a power voltage supplied from outside is lower than a prescribed voltage; wherein the power voltage supplied from the outside is comprised of at least a first power voltage supplied to the memory circuit including the memory cell array and a second power voltage supplied to an output circuit, and the lockout circuit comprises: a voltage detector that outputs a first lockout signal for inhibiting the command to the memory circuit including the memory cell array when the first power voltage is not higher than a first prescribed voltage; and a power voltage confirmation circuit that outputs a second lockout signal for inhibiting the command to the memory circuit including the memory cell array when the second power voltage is lower than a second prescribed voltage.