Patent ID: 6716743
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having wiring formed thereon, said method comprising:forming a conductor pattern having narrow and wide protuberances and recesses, by forming wiring grooves on an insulating film; forming a first barrier metal layer and then a wiring material layer on said conductor pattern wherein said wiring material layer comprises a first layer and a second layer; forming a second barrier metal layer on said wiring material so that a height of a surface of said first barrier metal layer at protuberances of said conductor pattern is made equal to a height of a surface of said second barrier metal layer at recesses of said conductor pattern; removing said second barrier metal layer at the protuberances of said conductor pattern; removing said wiring material layer at the protuberances of said conductor pattern; and removing said first barrier metal layer at the protuberances of said conductor pattern and said second barrier metal layer at the recesses of said conductor pattern.