Patent ID: 6633059
Filing Date: 2003-10-14
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate; a gate insulating layer formed on said semiconductor substrate; a conductive gate electrode formed on said gate insulating layer; insulating mask layers formed apart from said gate electrode on both sides of said gate electrode; an exposed source node region and an exposed drain node region formed in said semiconductor substrate between said gate electrode and said insulating mask layers; an exposed source contact region and an exposed drain contact region formed in said semiconductor substrate on outer sides of said insulating mask layers; a source region and a drain region formed in said semiconductor substrate, respectively connecting said source node region and said source contact region, and said drain node region and said drain contact region; and low resistively layers formed on and contacting said source node region and said source contact region, and said drain node region and said drain contact region.