Patent ID: 7851383
Filing Date: 2010-12-14
Classification: H01L

Abstract:
1. A method for manufacturing an integrated circuit comprising: providing a semiconductor substrate including silicon material; defining a source region and a drain region within the semiconductor substrate; defining a gate region within the semiconductor substrate, the gate region being positioned between the source region and the drain region; forming a first layer overlaying the gate region, the first layer including silicon nitride and/or silicon oxynitride material; oxidizing the semiconductor substrate overlaid with the first layer at a predetermined temperature range for a period of time to form a second layer overlaying the gate region, the second layer being characterized by a thickness less than 20 angstroms, the second layer including at least silicon oxide material; and forming a gate structure overlaying the second layer on the gate region, wherein the first layer decelerates the oxidizing of the semiconductor substrate overlaid with the first layer.