Patent ID: 7512854
Filing Date: 2009-03-31
Classification: G06F

Abstract:
1. A digital data processing system, comprising: a first integrated circuit module having an expansion port; a second integrated circuit module having an expansion port; a serial link comprising at least one intermodule communication line connecting the expansion ports of the first and second integrated circuit modules; a data driver circuit in the first module for transmitting data from the first module to the second module across the at least one intermodule communication line; a data receiver circuit in the second module for receiving the data transmitted across the at least one intermodule communication line and transmitting the data across a primary data path and a secondary data path; a first latch in the second module for latching the data transmitted across the primary data path based on a first clock signal; a second latch in the second module for latching the data transmitted across the secondary data path based on a second clock signal, the second clock signal being skewed relative to the first clock signal; comparison logic in the second module that compares the data latched from the primary data path with the data latched from the secondary data path; logging logic in the second module that records the occurrence of any miscompares in the comparison logic; wherein the primary and secondary data paths each include a programmable delay line and a fixed delay line having a plurality of taps, wherein the plurality of taps of the fixed delay line in the primary data path respectively provide the data transmitted across the primary data path at a plurality of fixed delays to a plurality of master/slave latches for latching the data transmitted across the primary data path, wherein the plurality of taps of the fixed delay line in the secondary data path respectively provide the data transmitted across the secondary data path at a plurality of fixed delays to a plurality of master/slave latches for latching the data transmitted across the secondary data path, wherein each of the master/slave latches for latching the data transmitted across the primary data path is clocked by the first clock signal and each of the master/slave latches for latching the data transmitted across the secondary data path is clocked by the second clock signal, wherein the programmable delay line and a tap selection of the fixed delay line in at least the primary data path are tuned during normal operation, wherein the programmable delay line and the tap selection of the fixed delay line in the primary and secondary data paths are equalized and frozen during a test cycle to monitor an error rate while data associated with an application program is transmitted across the at least one intermodule communication line, wherein the first latch is one of the master/slave latches for latching the data transmitted across the primary data path, and wherein the second latch is one of the master/slave latches for latching the data transmitted across the secondary data path.