Patent ID: 8866507
Filing Date: 2014-10-21
Classification: G01R,H01L

Abstract:
1. A method for testing trap density of a gate dielectric layer in a semiconductor device having no substrate contact, wherein a source and a drain terminal of the semiconductor device form a bilateral symmetric structure with respect to a central line of a channel, and probes of a semiconductor parameter test instrument are connected to the gate, the source and the drain terminal of the semiconductor device respectively, and the probes and cable connection lines of the semiconductor parameter test instrument used to connect the test instrument with the source and the drain terminal are bilateral symmetric with each other; firstly, bias settings at the gate, the source and the drain terminal are controlled so that the semiconductor device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges; after that, the following steps 1), 2) and 3) are repeated sequentially to form a loop and DC currents are measured at the source and the drain terminal: 1) changing the bias settings and holding for a period of T1, so that majority carriers are entered into the channel through the source and the drain terminal to form an inversion layer in the channel, and a portion of carriers of the inversion layer are confined by the traps in the gate dielectric layer; 2) changing the bias settings and holding for a period of T2, so that carriers of the inversion layer flow back to the source and the drain terminal respectively, whereas carriers confined by the traps in the gate dielectric layer do not flow back to the channel; 3) changing the bias settings and holding for a period of T3, so that the carriers confined by the traps in the gate dielectric layer flow out through the drain terminal only; and finally, trap density Qt of the gate dielectric layer is calculated by the following equation: wherein, Is is DC current at the source terminal; Id is DC current at the drain terminal; W is a channel width of the semiconductor device; L is a channel length of the semiconductor device; q is electrical quantity of charges per unit, and q=1.62×10 wherein, in the initial state, the bias settings at the gate, the source and the drain terminal are Vg0, Vs0 and Vd1 respectively, wherein Vg0=Vs0; Vg0 and Vs0 are in a range from 0 to 0.1×VDD; and Vd1 is in a range from 0.5×VDD to 0.75×VDD, wherein VDD is an on-state operation voltage of the semiconductor device.