Patent ID: 7464315
Filing Date: 2008-12-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory array including a plurality of memory cells, each requiring a refresh operation for data retention; and an ECC (Error Correction Circuit) for performing calculation of parity information on data of said memory cells and for performing error correction of said memory cells; said semiconductor memory device entering from a normal operation state into a data retention operating mode upon receipt of a command to enter into the data retention operating mode and for returning to the normal operation state upon receipt of a command to exit from the data retention operating mode; wherein the data retention operating mode includes: encode processing for performing calculation of parity information on data of said memory cells by said ECC when said semiconductor memory device enters into the data retention operating mode; self-refresh processing including a burst self-refresh state for intensively performing a self refresh on said memory cell array, a power-off state for turning off a part of an internal power supply circuit of said semiconductor memory device for a predetermined period, and a power-on state for returning said internal power supply circuit in an off state to an on state; and decode processing for performing error correction of said memory cells by said ECC upon receipt of the command to exit from the data retention operating mode; said semiconductor memory device further comprising a circuit for outpuffing flag information indicating an internal state of said semiconductor memory device from a predetermined output terminal.