Patent ID: 7707366
Filing Date: 2010-04-27
Classification: G06F

Abstract:
1. A memory-control device that is located between a processor and a plurality of memory ranks and that controls access to the memory ranks, comprising: a memory-management unit that receives and buffers an access request from the processor to any of the memory ranks, and issues an access request based on scheduling for memory management; and a rank-management unit that connects the plurality of ranks, receives and buffers said access request from said memory-management unit, and gives said access request to any one concerned of the memory ranks based on scheduling for rank management; wherein said memory-management unit comprises: a first counter that performs counting for a data bus that is connected with said rank-management unit, and counts the time from occupation start of said data bus used for execution of said access request to end of the occupation; and a first controller that performs said scheduling for memory management according to contents of said first counter; and wherein said rank-management unit comprises: a second counter that counts the time from occupation start of said data bus used for execution of said access request to end of the occupation; and a second controller that performs said scheduling for rank management according to contents of said second counter.