Patent ID: 7024326
Filing Date: 2006-04-04
Classification: H03K

Abstract:
1. Method of optimizing the timing between signals to be latched and a respective latching clock signal with respect to a given circuitry arrangement, (a) receiving and providing target timing data (TTD), which are descriptive for a target timing between said signals to be latched and said latching clock signal, (b) receiving and providing test timings (TT), which are descriptive for test timings of said latching clock signal, (c) receiving and providing a test input signal (I), as a test signal to be latched, (d) for each of said test timings (TT): (e) comparing the obtained phase differences to said target timing data (TTD), and (f) choosing and setting a distinct delay test value as a delay value for said clock delay line (CDL) for operating for which the respective phase difference fits best to the target timing data (TTD);