Patent ID: 6459626
Filing Date: 2002-10-01
Classification: G11C

Abstract:
An integrated memory configuration, comprising:a plurality of word lines; four reference word lines; bit lines including two bit line pairs; memory cells provided at crossover points between each of said word lines with a respective one of said bit lines of each of said two bit line pairs; reference cells provided at crossover points between each of said four reference word lines and a respective one of said bit lines; two differential sense amplifiers connected to a respective one of said two bit line pairs; two first switching elements connecting a respective one of said bit lines of a first one of said two bit line pairs to a respective one of said bit lines of a second one of said two bit line pairs; and two second switching elements respectively connecting one of said reference cells of one of said two bit line pairs to a given one of said bit lines of another one of said two bit line pairs, said given one of said bit lines of said another one of said two bit line pairs not being connected, via a corresponding one of said two first switching elements, to one of said bit lines assigned to said one of said reference cells of said one of said two bit line pairs.