Patent ID: 8458633
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A semiconductor integrated circuit design apparatus, comprising: a delay analysis unit which analyzes a static delay based on chip information on a semiconductor integrated circuit, said semiconductor integrated circuit including flip-flops, said static delay being analyzed on respective paths between said flip-flops; a noise generation unit which generates, based on a predetermined noise definition, noise information on a noise to be applied to said semiconductor integrated circuit; a voltage fluctuation level analysis unit which analyzes, based on said chip information on said semiconductor integrated circuit, a voltage fluctuation level of said semiconductor integrated circuit, said voltage fluctuation level being analyzed when said noise is applied to a predetermined location of said semiconductor integrated circuit based on said noise information; a timing verification unit which makes said delay analysis unit analyze said static delay based on said voltage fluctuation level analyzed by said voltage fluctuation level analysis unit, said timing verification unit verifying timing for operation of said semiconductor integrated circuit based on a result of analysis on said static delay in respective paths of said semiconductor integrated circuit, said timing verification unit repeatedly verifying said timing on said semiconductor integrated circuit while varying intervals of a predetermined application timing of the noise within a clock cycle; and a control unit which reduces a number of times the timing verification is repeated by said timing verification unit, said number of times being reduced based on the result of analysis on said static delay in said respective paths of said semiconductor integrated circuit, wherein said noise generation unit generates noise information on said noise to be applied at said predetermined application timing, and said timing verification unit verifies said timing with respect to each noise that is applied at said predetermined application timing, wherein said control unit calculates a total time of a first delay time and a second delay time based on the result of said analysis on said static delay in said respective paths, said first delay time being time taken to transmit a signal from a clock source to one flip-flop of said respective paths, said second delay time being time taken to transmit a signal to the other flip-flop from said one flip-flop, and said control unit reduces said number of times the timing verification is repeated so as to make said timing verification unit repeatedly verify said timing within said total time from the start of said clock cycle, and wherein the predetermined application timing is independent of a clock cycle.