Patent ID: 9128834
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A method for implementing ECC (Error Correction Codes) memory module communications with a host processor in multi-ported memory configuration in a computer system comprising: providing a memory controller coupled to the host processor and each of multiple memory modules, each of said multiple memory modules being assigned a module-specific pre-determined address range, said memory controller comprising an ECC generator and ECC decoder; enabling each of said multiple memory modules operating in unison to identify one memory module required to communicate module specific information back to the host processor; generating back to the host processor a valid ECC word with all of said multiple memory modules operating in unison, while other multiple memory modules individually being unaware of data contents of said one memory module required to communicate back to the host processor; the host processor making a request in a particular module-specific pre-determined address range; and one of said multiple memory modules being assigned the particular module-specific pre-determined address range for the request communicating module specific information back to the host processor, said pre-agreed constant including a pattern combination of zeros and ones.