Patent ID: 8994119
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each of the plurality of the gate stack structures, a plurality of source and drain regions in the substrate on both sides of each of the plurality of the gate spacer structures, the plurality of gate stack structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the plurality of the first gate stack structures consists of a first gate insulating layer, a first work function metal layer formed directly on the first gate insulating layer, a second work function metal diffusion blocking layer formed on the first work function metal layer, and a gate filling layer formed on and in direct contact with the second work function metal diffusion blocking layer, each of the plurality of the second gate stack structures comprises a second gate insulating layer, the first work function metal layer formed directly on the second gate insulating layer, a second work function metal layer formed on the first work function metal layer, and the gate filling layer formed on and in direct contact with both the first work function metal layer and the second work function metal layer of each of the plurality of the second gate stack structures, and the second work function metal diffusion blocking layer has a first stress, the gate filling layer has a second stress, and the first stress is opposite to the second stress.