Patent ID: 7224614
Filing Date: 2007-05-29
Classification: G11C

Abstract:
1. A method of programming in parallel a group of memory cells relative to a demarcation threshold voltage, comprising: (a) applying a programming pulse to the group of memory cells; (b) verifying the cells of the group relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage; (c) repeating (a) to (b) until one of the cells has been verified relative to the first reference threshold voltage; (d) modifying a programming setup for a memory cell that has been verified to the first reference threshold voltage to slow down subsequent programming for those cells; (e) applying a programming pulse to the group of memory cells; (f) verifying the cells of the group relative to the first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage; (g) modifying the programming setup for a memory cell that has been verified to the first reference threshold voltage to slow down subsequent programming for those cells; (h) verifying the cells of the group relative to the demarcation threshold voltage; (i) inhibiting a memory cell that has been verified relative to the demarcation threshold voltage from further programming; and (j) repeating (e) to (i) until all cells in the group has been program verified relative to the demarcation threshold voltage.