Patent ID: 8493578
Filing Date: 2013-07-23
Classification: G02B,G03G,G06K,H04N

Abstract:
1. A pixel clock generator comprising: a high frequency clock generating unit that generates a high frequency clock; a pixel clock generating unit that generates a pixel clock based on the high frequency clock; an error calculating unit that detects a first synchronization signal and a second synchronization signal, and calculates an error between a first time period starting from a time when the first synchronization signal is detected until a time when the second synchronization signal is detected and a second time period obtained by integrating a cycle of the pixel clock for a target number of times; and a frequency setting unit that sets a frequency of the pixel clock to be generated by the pixel clock generating unit based on the error calculated by the error calculating unit, wherein the frequency setting unit includes the frequency setting unit circularly selects the N pieces of offset values calculated by the pixel clock frequency offset value calculating unit, and calculates the frequency of the pixel clock generated by the pixel clock generating unit based on a result obtained by adding selected offset values and the average of the frequency of the pixel clock calculated by the pixel clock frequency average calculating unit.