Patent ID: 7355288
Filing Date: 2008-04-08
Classification: H01L,H04B,H05K

Abstract:
1. An integrated circuit device comprising: a silicon substrate; a contact pad over said silicon substrate; a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said contact pad; a metal trace over said passivation layer and over said contact pad; and a bump on said metal trace, wherein said bump comprises a copper layer directly on said metal trace, a nickel layer over said copper layer, and a solder layer directly on a top surface of said nickel layer, wherein said copper layer has a first transverse dimension smaller than a second transverse dimension of said nickel layer and has a thickness greater than said first transverse dimension, wherein said copper layer has a sidewall recessed from that of said nickel layer, and wherein said nickel layer has a first portion over said copper layer and a second portion overhanging said copper layer.