Patent ID: 6084800
Filing Date: 2000-07-04
Classification: G11C

Abstract:
A voltage booster circuit for generating at a word line supply node a boosted supply voltage higher than a power supply voltage for driving word lines via row decoder circuits in an array of flash EEPROM memory cells during read and program modes of operation, comprising:a precharge circuit for selectively connecting the power supply voltage to the word line supply node in response to a precharge signal;a charge pump circuit for pumping up the word line supply node to the boosted supply voltage during the program mode of operation in response to an enable signal;a booster capacitor having a first terminal connected to the word line supply node and a second terminal; anda driver circuit responsive to the enable signal, to a kick bar signal, and receiving the boosted voltage, for selectively generating a 3-state output voltage at an output node for driving the second terminal of the booster capacitor,wherein the 3-state output voltage is at a low state during a precharge mode of operation, at a power supply voltage during the read mode of operation, and at a boosted supply voltage state during the program mode of operation.