Patent ID: 6437429
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A semiconductor package comprising:at least a die, each die having a topside surface, a downside surface, and a plurality of bonding pads on the topside surface; a plurality of leads having a topside surface, a downside surface and a cutting surface; a plurality of electrical connecting devices electrically connecting the bonding pads of the die to the topside surfaces of the corresponding leads; and a package body sealing the topside surface of the die, the electrical connecting devices and the topside surfaces of leads, and exposing some partial downside surfaces of the leads on a same plane to form a plurality of metal pads and the cutting surfaces of the leads, wherein there is an interval between the cutting surface and the plane of forming the metal pads, the downside surface of each lead between the corresponding metal pad and the cutting surface is covered by the package body.