Patent ID: 9201448
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A system on a chip (SoC) comprising: first and second clock domains that are unequal to one another; a first node to receive a first signal, which originates within the SoC and is synchronous with the first clock domain, and output the first signal from the SoC; a second node to receive a second signal, which originates within the SoC and is asynchronous to the first clock domain and synchronous to the second clock domain, and output the first signal from the SoC; a processor core and a core clock, corresponding to the processor core and the first clock domain, to produce a core clock signal; and a logic module and a logic module clock, corresponding to the logic module and the second clock domain, to produce a logic module clock signal; wherein (a) the first and second nodes are to concurrently receive the first and second signals, (b) the first signal is not forwarded, within the SoC, concurrently with the core clock signal, and (c) the second signal is forwarded, within the SoC, concurrently with the logic module clock signal.