Patent ID: 8026883
Filing Date: 2011-09-27
Classification: G09G

Abstract:
1. A liquid crystal display comprising: a liquid crystal panel comprising a plurality of gate lines parallel to each other, a plurality of data lines parallel to each other and intersecting the gate lines, each gate line comprising a front end and a tail end; a plurality of first thin film transistors arranged at each intersection of the gate line and the data line; a scanning driver configured for providing a plurality of scanning signals to the gate lines in sequence, the scanning driver being connected to the front ends of the gate lines; a data driver configured for providing a plurality of gray scale voltages to the data lines; and a compensator configured for compensating the scanning signals, wherein the compensator comprises a plurality of switching elements connected to the tail ends of the lines respectively, when one gate line is scanned, a high compensating voltage being applied to the tail end of the one gate line through a corresponding switching element to accelerate to turn on the first thin film transistors adjacent to the tail end, and at an end of the scanning time of the one gate line, a low compensating voltage being applied to the tail end of the one gate line through the corresponding switching element to accelerate to turn off the first thin film transistors adjacent to the tail end, wherein the high compensating voltage and the low compensating voltage are provided to the tail end of the one gate line through the same switching element which is connected to the tail end of the one gate line; wherein each switching element comprises a second thin film transistor, and the switching elements have a lower turn on threshold voltage than the first thin film transistors arranged at each intersection of the gate line and the data line; wherein the compensator further comprises a first input configured to output the high compensating voltage and the low compensating voltage to the tail ends of the odd-numbered gate lines and a second input configured to output the high compensating voltage and the low compensating voltage to the tail ends of the even-numbered gate lines, the second thin film transistor further comprises a gate electrode, a source electrode directly connected to the gate electrode and a drain electrode, the source electrode and the gate electrode of the second thin film transistor being connected to the tail end of the corresponding gate line, the first input being connected to the drain electrodes of the second thin film transistors connected to the odd-numbered gate lines respectively, and the second input being connected to the drain electrodes of the second thin film transistors connected to the even-numbered gate lines respectively.