Patent ID: 7061802
Filing Date: 2006-06-13
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a global bit line; a first section bit line; a first section selection transistor which connects the global bit line with the first section bit line; a first nonvolatile semiconductor memory cell in which data is erasable/programmable and which is connected with the first section bit line; a second section bit line; a second section selection transistor which connects the global bit line with the second section bit line; a second nonvolatile semiconductor memory cell in which data is erasable/programmable and which is connected with the second section bit line; a section selecting circuit which selects one of the first and the second section selection transistors; and a data latch circuit which receives potential from the global bit line and supplies potential to the global bit line; wherein the data latch circuit includes a data amplifier circuit which amplifies a first readout data read out from the first nonvolatile semiconductor memory cell and a second readout data read out from the second nonvolatile semiconductor memory cell, a first data holding circuit which holds a first programming data to be programmed into the first nonvolatile semiconductor memory cell and the first readout data, and a second data holding circuit which holds a second programming data to be programmed into the second nonvolatile semiconductor memory cell and the second readout data.