Patent ID: 8981446
Filing Date: 2015-03-17
Classification: G11C,H01L

Abstract:
1. A magnetic memory comprising: a semiconductor substrate; an isolation region formed in a surface of the semiconductor substrate, the isolation region including an insulator filling a trench formed in the surface of the semiconductor substrate, the isolation region defining a plurality of active areas extending in a first direction on the surface of the semiconductor substrate, wherein the plurality of active areas include a first active area and a second active area, and the isolation region extending in a second direction, which is perpendicular to the first direction, is present between the first active area and the second active area; a first word line which is buried in the surface of the semiconductor substrate including the first active area, and extends in the second direction; a second word line which is next to the first word line, is buried in the surface of the semiconductor substrate including the first active area at a first predetermined distance from the first word line, and extends in the second direction; a third word line which is next to the second word line, is buried in the surface of the semiconductor substrate including the second active area at a second predetermined distance from the second word line, and extends in the second direction, wherein the second predetermined distance is larger than the first predetermined distance; a first select transistor provided on the first active area, with the first word line being used as a gate electrode thereof; a second select transistor provided on the first active area, with the second word line being used as a gate electrode thereof, wherein the first and second select transistors share a source region; a first variable resistance element provided on the first active area, the first variable resistance element having one end connected to a drain region of the first select transistor; and a second variable resistance element provided on the first active area, the second variable resistance element having one end connected to a drain region of the second select transistor.