Patent ID: 6157574
Filing Date: 2000-12-05
Classification: G11C,H01L

Abstract:
A method for programming a memory transistor formed in a semiconductor material of a first conductivity type to store one of a plurality of logic states, the plurality of logic states corresponding with a plurality of charge ranges, the plurality of charge ranges having a first charge range and a plurality of remaining charge ranges, the memory transistor having:spaced-apart source and a drain regions of a second conductivity type formed in the semiconductor material,a channel region defined between the source and drain regions,a floating gate formed over the channel region and an adjacent isolation region,a layer of interpoly dielectric connected to the floating gate over the adjacent isolation region, anda plurality of plates connected to the interpoly dielectric over the adjacent isolation region, each of the plurality of plates being connectable to a first voltage, each remaining charge range being associated with a different combination of plates,the method comprising the steps of:placing a charge on the floating gate of the memory transistor, the charge falling within the first charge range and representing a first logic state; andif the transistor is to be programmed to store a logic state other than the first logic state, reducing the charge on the floating gate to fall within a remaining charge range that corresponds with the logic state by applying a second voltage to the semiconductor material, and connecting the plates that are associated with the remaining charge range to the first voltage.