Patent ID: 8421160
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate structure on a channel region of a semiconductor substrate, wherein a first source region and a first drain region are present in the semiconductor substrate on opposing sides of the gate structure; at least one spacer present on the sidewalls of the gate structure, the at least one spacer comprising a first spacer and a second spacer, wherein the first spacer of the at least one spacer is in direct contact with the sidewall of the gate structure and is present over an entire width of the first source region and the first drain region, the second spacer of the at least one spacer extends from the first spacer of the at least one spacer and has a length that covers an entire length of a first source region and a first drain region; and a second source region and a second drain region in direct contact with a portion of the first source region and the first drain region that is not underlying the at least one spacer, wherein the second source region and the second drain region are raised relative to the channel region of the semiconductor substrate.