Patent ID: 6510082
Filing Date: 2003-01-21
Classification: G11C

Abstract:
A system for producing an indication of the logical state of a flash memory cell for a virtual ground flash memory architecture, comprising:a virtual ground flash memory array configured with columns of cells associated with bit lines, and rows of cells of the array associated with word lines for selection of core cells of the array, wherein the drain and source terminals of cells associated with a given word line are coupled in series between respective bit lines, and the gates of the cells are coupled to respective word lines; a core cell sensing circuit which is operable to generate a bit line voltage and sense a core cell current at a bit line associated with a drain terminal of a selected memory cell to be sensed, and produce an indication of the flash memory cell logical state; a bit line charge and hold circuit configured to apply and maintain a drain terminal voltage to a bit line associated with a drain terminal of a cell adjacent to the selected cell to be sensed during a read operation, wherein the applied drain terminal voltage is substantially the same as the bit line voltage applied to the drain terminal bit line of the selected memory cell to be sensed; and a selective bit line decode circuit which is operable to select the bit lines of the selected memory cell to be sensed and the bit line of the adjacent cell during memory read operations, wherein applying a voltage to the bit line of the cell adjacent to the cell being sensed, eliminates the charge sharing leakage current which is typically lost to the adjacent memory cell.