Patent ID: 6979620
Filing Date: 2005-12-27
Classification: H01L

Abstract:
1. A method for fabricating a flash memory cell, comprising: providing a semiconductor substrate with a first conductivity; forming a tunnel oxide layer on said semiconductor substrate; forming a first conductive layer on said tunnel oxide layer; forming an insulating layer on said first conductive layer; forming a second conductive layer on said insulating layer; patterning said second conductive layer to form a periphery region on an exposed portion of said semiconductor substrate and a memory cell region on said second conductive layer left on said semiconductor substrate; forming a gate oxide layer on the exposed portion of said semiconductor substrate of said periphery region and on said second conductive layer of said memory cell region; forming a third conductive layer on said gate oxide layer; patterning said third conductive layer to form a first gate electrode on said gate oxide layer of said periphery region and expose said gate oxide layer of said memory cell region; forming a pair of lightly doped drain regions with a second conductivity opposite to said first conductivity beside the sidewall of said first gate electrode in said semiconductor substrate of said periphery region; forming a dielectric layer on said first gate electrode of said periphery region and on said gate oxide layer of said memory cell region; anisotropically etching said dielectric layer until exposing said second conductive layer of said memory cell region to form a spacer on the sidewall of said first gate electrode of said periphery region; forming a source/drain region with said second conductivity adjacent to said lightly doped drain region; and patterning said second conductive layer, said insulating layer, said first conductive layer and said tunnel oxide layer of said memory cell region to form a second gate electrode.