Patent ID: 6643722
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A data storage system wherein a host computer is coupled to a bank of disk drives through an interface, such interface comprising:(A) a plurality of director printed circuit boards; (B) a plurality of ESCON adapter printed circuit boards; (C) a plurality of buses; and (D) at least one memory printed circuit board; (E) a backplane printed circuit board having: (a) the director boards and memory boards plugged into one side of such backplane printed circuit board and the adapter boards plugged into an opposite side of the backplane printed circuit board; (b) wherein such backplane printed circuit board has the plurality of busses therein to electrically interconnect directors on the director printed circuit boards, ESCON adapters on the adapter printed circuit boards and at least one memory on the at least one memory printed circuit board with the directors controlling data transfer between the host computer and the bank of disk drives as such data passes through the memory; (c) wherein a front end portion of the directors are coupled between the host computer and the busses through a front end portion of such ESCON adapters and a back end portion of the directors are between the bank of disk drives and the busses through the back end portion of the adapters; and (E) wherein each one of such adapter boards comprises: (a) a plurality of adapter ports each one being coupled to a corresponding port of the host computer; (b) a plurality of adapter board gate arrays; (c) a plurality of optic interfaces, each one being coupled between a corresponding one of the adapter port and a corresponding one of the adapter board gate arrays, wherein each coupled optic interfaces and gate array provides a corresponding one of a plurality of channels for the data; (d) a plurality of adapter board CPUs, each one of the adapter board CPUs being coupled to the adapter board gate arrays and the optic interface of a corresponding one of the channels, each one of the CPUs controlling the initiation and termination of the data passing through said corresponding one of the channels; (F) wherein each one of the front end portion of the director boards comprises: (a) a plurality of director board gate arrays; (b) a plurality of EDACs; (c) wherein each pair of the director board gate arrays being coupled between a corresponding pair of the adapter board gate arrays and a corresponding one of the EDACs; (d) a plurality of director board CPUs, each one being coupled to a corresponding one of the adapter board CPUs, each one of the director board CPUs being coupled to a corresponding one of the director board gate arrays to control the initiation and termination of a data transfer through such coupled one of the director gate arrays; (e) a common state machine coupled to the plurality of director gate arrays and the plurality of EDACs for arbitrating between the pair of director gate arrays coupled to the corresponding one of the EDACs for access to such corresponding one of the EDACs.