Patent ID: 6185411
Filing Date: 2001-02-06
Classification: H03L

Abstract:
In a phase locked loop (PLL) having a plurality of elements including a first element and a second element, each of the first element and the second element having an input terminal and an output terminal, the output terminal of the first element being coupled to the input terminal of the second element and the output terminal of the second element being coupled to the input terminal of the first element to form a feedback signal arrangement in the PLL, each element having a response time defined by a difference in time between a first time at which the element is enabled and a second time, occurring after the first time, at which the output signal of the element reaches a steady state condition, the PLL having a response time defined by a difference in time between a time when a disabled element of the plurality of elements is enabled and a time when an output frequency signal of the PLL reaches a steady state condition, a method for minimizing the response time of the PLL while minimizing power consumption of the PLL comprising the steps of:enabling the first element, having a first response time, responsive to a first control signal;monitoring, directly from the first element, an indication of when an output signal of the first element has substantially reached its steady state frequency condition;controlling a second control signal responsive to the monitored indication; andenabling the second element, having a second response time less than the first response time, responsive to the second control signal.