Patent ID: 7716613
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. A method for classifying errors in a layout of a semiconductor circuit, which comprises the steps of: examining, via a data processing installation, the layout of the semiconductor circuit for infringement of predetermined design rules for establishing errors; marking, via the data processing installation, each error in the layout; extracting, via the data processing installation, information about the error and about the layout of the semiconductor circuit in an area surrounding the error resulting in extracted information; comparing, via the data processing installation, the extracted information with prestored information within a multiplicity of classes resulting in compared information, the comparing step including considering at least one transformation of the extracted information; and assigning, via the data processing installation, the error to a respective class on a basis of the compared information, wherein the extracted information represents the error and the layout of the semiconductor circuit in the area surrounding the error as a geometric pattern, wherein the transformation includes at least one of a rotation, a mirroring, and a normalizing of the extracted information; and wherein the comparing step includes: comparing the geometrical pattern with the prestored information within the multiplicity of classes resulting in the compared information, the prestored information in each of the classes representing a different geometrical pattern being compared with at least one transformation of the geometrical pattern of the extracted information for geometrical identity.