Patent ID: 7721075
Filing Date: 2010-05-18
Classification: G06F

Abstract:
1. A load/store architecture processing system, comprising: a hardware processor that includes a buffer coupled to the hardware processor, the processor system being configured such that: following execution of a write-tie instruction that associates a memory address of the buffer with a register address of a first software accessible register, the data moving engine causes the execution unit to write data to the buffer in response to instructions that specify writing data to the first software accessible register, following execution of an untie instruction that disassociates the memory address of the buffer from the register address of the first software accessible register, the data moving engine causes the execution unit to write data only to the first software accessible register in response to instructions that specify writing data to the first software accessible register, and prior to execution of the write-tie instruction a first value corresponding to a number of elements to be written to the buffer is stored in a location, and a conditional branch instruction following the write-tie instruction accesses the location based on the memory address of the buffer, wherein the location is not part of the buffer.