Patent ID: 6032282
Filing Date: 2000-02-29
Classification: G01R

Abstract:
A timing edge forming circuit for use in a semiconductor IC test system for testing an IC device by supplying test signals through a plurality of test signal paths corresponding to input pins of said IC device, said timing edge forming circuit producing a plurality of timing edges of a test signal within a test cycle for each test signal path, said timing edge forming circuit comprising:a pattern generator for generating test pattern information to produce a test signal to be supplied to the semiconductor device wherein the test pattern information includes address data and a rate signal which is synchronizing with a clock signal;a plurality of first logic delay circuits (10) receiving the rate signal and the address data from the pattern generator wherein a first delay time data is generated by a data memory accessed by the address data wherein the first delay time data includes a first multiple delay time which is an integer multiple of one cycle of the clock signal and a first fractional delay time which is smaller than one cycle of the clock signal, and each of the first logic delay circuit generates an enable signal in synchronism with the clock signal which is delayed by the first multiple delay time and the first fractional delay time;a logic delay control circuit for receiving the first fractional delay time from a first logic delay circuit wherein the logic delay control circuit stores skew data for adjusting a skew which is a difference in signal propagation delay times between the signal paths and adds the first fractional delay time and the skew data to form second delay time data;a plurality of second logic delay circuits (80) receiving the second delay time data from the logic delay control circuit wherein each of the second logic delay circuits provides a second multiple delay time in the second delay time data which is an integer multiple of one cycle of the clock signal to the enable signal to form a delayed enable signal, and produces a second fractional delay time which is smaller than one cycle of the clock signal, and each of the second logic delay circuits transmits the delayed enable signal and the second fractional delay time; anda variable delay circuits (12) for providing a high resolution delay time to the delayed enable signal based on the second fractional delay time.