Patent ID: 6504236
Filing Date: 2003-01-07
Classification: H01L,Y10S

Abstract:
A semiconductor die assembly comprising:a semiconductor die having at least one integrated circuit therein, having a first active surface having, in turn, at least one contact pad arranged thereon, and having a second surface, an upper conductive planar leadframe member having an upper surface attached to at least a portion of said second surface of said semiconductor die using an electrically insulative adhesive, and having a lower surface, said upper conductive planar leadframe member subdivided into a plurality of portions, at least one portion of said plurality of portions having an exposed tab connected to said at least one integrated circuit of said semiconductor die; a lower conductive planar leadframe member having an upper surface mounting said upper conductive planar leadframe member using a thin intervening layer of dielectric material for capacitance therebetween, said lower conductive planar leadframe member subdivided into a plurality of portions for matching corresponding said plurality of upper conductive planar leadframe portions, said lower conductive planar leadframe member cooperating with said upper conductive planar leadframe member for capacitance purposes; at least one lead of a plurality of leads connecting said at least one contact pad to at least one lead finger; at least one other lead of said plurality of leads connected to at least one said exposed tab of said at least one portion of said upper conductive planar leadframe member; and material encapsulating said semiconductor die.