Patent ID: 6995999
Filing Date: 2006-02-07
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory array in which a plurality of memory cells are arranged in a row direction and a column direction, each of the memory cells being formed by connecting one end of a variable resistive element for storing information according to a change in electric resistance caused by an electric stress and a drain of a selection transistor to each other on a semiconductor substrate; a word line connected to gates of the selection transistors of the plurality of memory cells in the same row; a source line connected to sources of the selection transistors of the plurality of memory cells in the same row or the same column; a bit line connected to the other ends of the variable resistive elements of the plurality of memory cells in the same column; a control circuit for executing controls of programming, erasing and reading of information to/from the memory cell; a voltage switch circuit for switching among a program voltage, an erase voltage and a read voltage to be applied to the source line and the bit line; a read circuit for reading information from the memory cell; and a pulse voltage applying circuit for applying a voltage pulse for programming or erasing to the word line connected to the memory cell in the state where the program voltage or erase voltage corresponding to the bit line and the source line is applied to the bit line and the source line connected to the memory cell to be programmed or erased in the memory array via the voltage switch circuit.