Patent ID: 8565032
Filing Date: 2013-10-22
Classification: G11C,H03K

Abstract:
1. A semiconductor device comprising: a clock generation circuit that generates a first internal clock signal based on an external clock signal; a clock division circuit that generates a second internal clock signal and a third internal clock signal based on the first internal clock signal, the clock division circuit including an edge adjustment circuit that adjusts a timing of at least one of a rising edge and a falling edge of the third internal clock signal based on an edge adjustment signal; an adjustment information holding section that supplies the edge adjustment signal to the edge adjustment circuit; a data strobe output circuit that receives the second and third internal clock signals to generate a first data strobe signal in response to the second internal clock signal, and to generate a second data strobe signal with a phase different from that of the first data strobe signal, in response to the third internal clock signal.