Patent ID: 6665229
Filing Date: 2003-12-16
Classification: G11C

Abstract:
A local row decoder structure of a nonvolatile semiconductor memory device to erase memory cells coupled to a single bitline, comprising:a single bias driver; a plurality of local level converters coupled with the bias driver, wherein one of the local level converters includes: a PMOS transistor having a source for receiving a high voltage and a gate for receiving a bias voltage from the bias driver, a first NMOS transistor having a drain coupled to a drain of the PMOS transistor and a gate for receiving a sector select signal, and a second NMOS transistor having a drain coupled to a source of the first NMOS transistor and a gate coupled to the global word line; and at least one word line driver coupled to each local level converter to erase at least one of the memory cells, the word line driver being coupled to the local level converter and to a global word line.