Patent ID: 9013930
Filing Date: 2015-04-21
Classification: G06F,G11C

Abstract:
1. A memory device, comprising: a first memory cell array, comprising a plurality of first word lines and a plurality of first bit lines, wherein a plurality of first data are stored in the first memory cell array; a second memory cell array, separated from the first memory cell array, and comprising a plurality of second word lines and a plurality of second bit lines, wherein a plurality of second data are stored in the second memory cell array; a control logic circuit, allowed to select one of the first word lines and one of the second word lines at a same time or an overlapping time, and alternately selecting a first address of the first memory cell array and a second address of the second memory cell array such that a first corresponding portion of the first data and a second corresponding portion of the second data are alternately read from the first memory cell array and the second memory cell array; a first sense amplifier, coupled via the first bit lines to the first memory cell array, and amplifying the first corresponding portion of the first data; a second sense amplifier, coupled via the second bit lines to the second memory cell array, and amplifying the second corresponding portion of the second data; a data multiplexer; and a shift register, wherein the data multiplexer is coupled to the first sense amplifier and the second sense amplifier, and the data multiplexer selectively transmits the first corresponding portion and the second corresponding portion to the shift register, and the shift register sequentially generates a plurality of output data according to the first corresponding portion and the second corresponding portion.