Patent ID: 7908450
Filing Date: 2011-03-15
Classification: G06F

Abstract:
1. A memory management unit that manages a memory that stores a code, and sets that the memory that stores the code to be executed is valid to make a processor execute the code, comprising: a page table that includes a plurality of entries prepared for each page of the memory, wherein at least one of the entries stores an effective bit indicating whether a corresponding page for which the entry was prepared is valid and an execution bit indicating that the corresponding page stores a code; a verification-key storing unit that stores a verification key used to verify a validity of the code; a verifying unit that verifies, when the processor stores the code in a code storing page of the memory and issues an instruction to set the effective bit of the code storing page just before executing the code, the validity of the code using the verification key stored in the verification-key storing unit and verification information assigned to the code stored in the code storing page of the memory; and a control unit that sets that the code storing page is valid in an entry of the page table corresponding to the code storing page when the validity is verified by the verifying unit.