Patent ID: 6833592
Filing Date: 2004-12-21
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; field oxide regions formed on a surface of the first well; and a first heavily doped region of buried layer having the second conductivity type formed in the first well at a distance away from the first contact region and the field oxide regions, wherein the distance is greater than 0, wherein the first heavily doped region prevents latch-up, wherein the first heavily doped region does not extend under the first MOS transistor, and is not below a field oxide layer, and wherein said field oxide layer separates the first well and a second well.