Patent ID: 6559013
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A fabrication method for a mask ROM device, comprising:forming a buried drain region in a substrate; forming a first dielectric layer on the substrate; forming a bar-shaped second dielectric layer on the first dielectric layer, the bar-shaped second dielectric layer is perpendicular to a direction of the buried drain region; removing a portion of the first dielectric layer to expose the substrate; forming a gate oxide layer on the exposed substrate surface; forming a conductive layer on the substrate to cover the bar-shaped second dielectric layer; removing a portion of the conductive layer until the bar-shaped second dielectric layer is exposed to form a plurality of coded memory cells, wherein the coded memory cells that comprise the gate oxide layer correspond to a logic state of â€œ1â€  while the coded memory cells that comprise the first dielectric layer correspond to a logic state of â€œ0â€ ; and removing the bar-shaped second dielectric layer.