Patent ID: 7045435
Filing Date: 2006-05-16
Classification: H01L

Abstract:
1. A method for electrically isolating shallow trenches between components on the surface of a semiconductor wafer comprising: (a) forming a plurality of first-type trenches and second-type trenches on a semiconductor substrate, each of the first-type trenches having a width greater than a predetermined size that is greater than a width of each of the second-type trenches; (b) performing a photolithographic process to form at least one photoresist pattern in each of the first-type trenches; (c) performing an etching process to form at least one dummy and a plurality of third-type trenches in each of the first-type trenches with the photoresist patterns as masks, and to deepen each of the second-type trenches; (d) stripping the photoresist patterns; (e) forming a dielectric layer over the surface of the semiconductor wafer, wherein the dielectric material of the dielectric layer fills the first-type trenches, the second-type trenches, and the third-type trenches on the surface of the semiconductor wafer; (f) condensing the dielectric layer; and (g) performing a planarization process to polish the surface of the semiconductor wafer for aligning the surface of the dielectric layer inside each of the first-type trenches and the second-type trenches with the surface of each component on the semiconductor wafer.