Patent ID: 6636434
Filing Date: 2003-10-21
Classification: G11C

Abstract:
A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2, wherein:each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2N connections from among the set of the 22N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2Nâˆ’1 first lines, connect the 2Nâˆ’1 other lines to a reference voltage, select a memory point, reading the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.