Patent ID: 8219836
Filing Date: 2012-07-10
Classification: G06F,Y02D

Abstract:
1. A processor comprising: an instruction classifier logic to identify an instruction type of an instruction in response to receiving the instruction, wherein the instruction classifier is to include an opcode parser and a type detector, wherein the opcode parser is to determine an opcode component of the instruction and the type decoder is to generate a signal representative of a type of the instruction in response to receiving the opcode component; a tracking state machine coupled to the instruction classifier, wherein the tracking state machine is to include a tracking counter and a tracking comparator, wherein a counter value in the tracking counter is set to a maximum count value if the type of the instruction received is the same as a type being tracked by the tracking state machine, wherein the tracking comparator is to generate control signals, a power controller coupled to the tracking state machine, wherein the power controller is to enable or disable one or more processing logic based on the control signals; a processing logic, of the one or more processing logic, to be enabled or disabled by the power controller; and an instruction retirement unit to determine the maximum count value based on a maximum number of instructions that can be tracked by the instruction retirement unit.