Patent ID: 8179360
Filing Date: 2012-05-15
Classification: G09G,G11C

Abstract:
1. A gate driving circuit, comprising: M shift registers, configured to sequentially shift a starting signal to generate M gate driving signals according to a plurality of clock signals, wherein M is a positive integer; a detecting unit, configured to switch a detecting voltage to a specific level when a specific driving signal among the gate driving signals is invalid; a control unit, configured to accumulate a counter value according to the starting signal and the clock signals, generate a set signal when the control unit receives the detecting voltage having the specific level, and generate a first auxiliary signal and a second auxiliary signal according to the counter value, wherein the first auxiliary signal and the second auxiliary signal are synchronous with two gate driving signals which are before and after the specific driving signal; a repair starting unit, configured to set a repair starting signal to be valid when the repair starting unit receives the set signal; a signal repairing device, enabled according to the valid repair starting signal, the signal repairing device set to generate a repairing signal according to the first auxiliary signal, and the signal repairing device stopping operating according to the second auxiliary signal; and a signal replacing unit, configured to replace the specific driving signal with the repairing signal according to the clock signals.