Patent ID: 6745357
Filing Date: 2004-06-01
Classification: H03K

Abstract:
A scannable logic circuit, comprising:a clocked precharge logic circuit that includes a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers, said logic circuit receives one or more input signals and a clock signal having an evaluate phase and a precharge phase, and produces one or more output signals; a scan control circuit that generates scan control signals, said scan control signals further comprise a scan enable signal; one or more scan registers; one or more read/write drivers coupled to said scan registers; and one or more scan circuits, each said scan circuit couples to one of said output buffers and to one of said scan registers through one of said read/write drivers, each said scan circuit receives said scan control signals from said scan control circuit, provides the state of said output signal to said scan register, and forces said output signal to a state specified by information in said scan register.