Patent ID: 6625066
Filing Date: 2003-09-23
Classification: G11C

Abstract:
An integrated circuit device including a memory array having a data path comprising:N column lines; first and second groups of N sense amplifiers respectively couplable to first and second pairs of complementary local data lines in response to signals on said N column lines; first and second local read/write circuits respectively coupled to said first and second pairs of complementary local data lines; and complementary global data lines selectively couplable to either of said first and second pairs of complementary local data lines in response to first and second enable signals applied to said first and second local read/write circuits, wherein said first and second local read/write circuits comprise first and second switching devices for selectively coupling said first and second pairs of complementary local data lines to said complementary global data lines in response to said first and second enable signals, and a third switching device for selectively shorting together said first or said second pairs of complementary local data lines when an opposite one of said first and second local read/write circuits couples a corresponding one of said first or second pairs of local data lines to said global data lines.