Patent ID: 6762431
Filing Date: 2004-07-13
Classification: G01R,H01L

Abstract:
A wafer level package comprising:a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal; at least one external connection terminal electrically connected to said at least one non-test chip terminal; at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out of said semiconductor chip circuit forming region to a position offset from said one of said test chip terminals; at least one testing member provided in an outer region of said semiconductor chip circuit forming region of said semiconductor wafer, said second end of said redistribution trace being connected to said at least one testing member; an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material, and a sealing resin provided on said insulating material such that top parts of said external connection terminals and said at least one testing member are exposed from said sealing resin.