Patent ID: 9123726
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A method of forming a wiring structure for an integrated circuit device, the method comprising: forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; forming a sacrificial hardmask layer over the ILD layer and first and second metal lines; patterning and removing portions of the sacrificial hardmask layer, thereby masking selected regions of the first and second metal lines such that first portions of the first and second copper lines are covered and second portions of the first and second copper lines are not covered so as to define exposed regions; selectively plating metal cap regions over only the exposed regions of the first and second metal lines at periodic intervals such that the metal cap regions are not initially plated over the covered portions of the one or more copper lines, and such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis; and following the plating of the metal cap regions over the exposed regions of the first and second metal lines, removing remaining portions of the sacrificial hardmask layer and forming a conformal insulator layer over the metal cap regions, uncapped regions of the first and second metal lines, and the ILD layer.