Patent ID: 7916819
Filing Date: 2011-03-29
Classification: H03L

Abstract:
1. A receiver system, comprising: a control unit for outputting a control signal and a selective signal; a phase locked loop (PLL) unit for generating M PLL clock signals based on an initial clock signal, wherein the i a phase select unit for selecting one of the M PLL clock signals as a base clock signal according to the selective signal; a delay locked loop (DLL) unit for generating N DLL clock signals based on the base clock signal, wherein the j a sampling clock unit for generating N left clock signals, N right clock signals based on each DLL clock signal, the k a data latch unit for sampling N bit data in one period of the initial clock according to N left clock signals, N DLL clock signals, and N right clock signals to respectively obtain N left data, N middle data and N right data, wherein the k wherein the middle, the left and the right data are fed back to the control unit for outputting the control signal and the selective signal to adjust the phase differences between the left clock signal, the DLL clock signal and the right clock signal, or select the base clock signal for next N bit data.