Patent ID: 9214238
Filing Date: 2015-12-15
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: first and second memory cells that are stacked above a semiconductor substrate; third and fourth memory cells that are stacked above the first and second memory cells; first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively; and a row decoder configured to apply voltages to the first to fourth word lines, wherein the row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell and applies the first programming voltage to the second word line during a write operation performed on the second memory cell, and the row decoder applies a second programming voltage that is higher than the first programming voltage to the third word line during a write operation performed on the third memory cell and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell.