Patent ID: 6411128
Filing Date: 2002-06-25
Classification: G11C,H03M

Abstract:
A logical circuit comprising:even input bit lines; a first latch circuit group which comprises a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating said even input bit lines, respectively, in a first timing; a second latch circuit group which comprises a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating said even input bit lines, respectively, in a second timing; a first node to which the output ends of a plurality of latch circuits are wired-OR, said plurality of latch circuits latching signal bits which propagate one half of said even input bit lines; a second node to which the output ends of a plurality of latch circuits are wired-OR, said plurality of latch circuits latching signal bits which propagate remaining one half of said even input bit lines; a third node to which said first and the second nodes are wired-OR; a first control system, said first control system successively outputting signal bits latched to one latch circuit group of said first and second latch circuit groups to said first node and then successively outputting signal bits latched to the other latch circuit group to said second node before latching the next signal bits; and a second control system which alternately outputs signal bits successively inputted to said first and second nodes from said first and second nodes to said third node.