Patent ID: 9076798
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. A semiconductor wafer comprising: a first chip disposed in a substrate; a second chip disposed adjacent the first chip and disposed in the substrate; a dicing street disposed between the first and the second chip; a first and a second metal level disposed over the dicing street, the first metal level and the second metal level each comprising at least a dielectric layer, the second metal level disposed on the first metal level; at least one first alignment mark disposed in the first metal level above a first portion of the dicing street, the at least one first alignment mark having a substantially flat uppermost surface extending contiguously between lateral boundaries of the at least one first alignment mark, the uppermost surface of the at least one alignment mark substantially level with the uppermost surface of the dielectric layer of the first metal level; first metal features disposed in the second metal level above the first portion of the dicing street, a plurality of the first metal features laterally separated by first distances and a portion of each of at least two of the first metal features aligned over and within the lateral boundaries of a same one of the at least one first alignment mark, the plurality of the first metal features disposed in a plurality of rows; and a third metal level comprising a third dielectric material extending contiguously from an uppermost surface to a bottommost surface of the third metal level, and having a bottommost surface in direct physical contact with an uppermost surface of the at least a dielectric layer of the second metal level, wherein a portion of each of a plurality of second metal features of the third metal level is aligned directly over and within lateral boundaries of the first alignment mark.