Patent ID: 7346763
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. A computer system comprising: a decode unit for decoding instructions having dual operations, wherein said instructions are supplied to the decode unit from a program memory, wherein an instruction has at least one bit sequence defining a register address and at least one repeated execution bit; a register file having a plurality of registers each having the same predetermined bit capacity and addressable via at least two register address ports, one of the ports being associated with a first execution channel of the computer system and the other of the ports being associated with a second execution channel of the computer system, wherein the first execution channel executes a first operation of the instruction and the second execution channel executes a second operation of the instruction in parallel with the first operation; a first register address supply path for supplying the at least one bit sequence with the repeated execution bit in the instruction to the one register address port; and at least the first execution channel executing the first operation once, twice or more times in dependence of the logical value of the repeated execution bit.