Patent ID: 8969944
Filing Date: 2015-03-03
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit in which a plurality of memory cells are serially-connected in an axial direction, comprising: a semiconductor pillar provided in the axial direction that serves as a channel; a floating gate that circumferentially covers the side face of the semiconductor pillar or covers a part of the semiconductor pillar to have an interval from the outer circumference of the semiconductor pillar; a control gate that circumferentially covers the side face of the semiconductor pillar or covers a part of the semiconductor pillar to have an interval from the outer circumference of the semiconductor pillar and that circumferentially covers the side face of the floating gate or covers a part of the floating gate to have an interval from the outer circumference of the floating gate; a first insulating layer provided between the semiconductor pillar and the floating gate; a second insulating layer provided between the floating gate and the control gate; and a third insulating layer provided between the semiconductor pillar and the control gate, wherein the floating gate and the control gate are provided to correspond to the each memory cell along the semiconductor pillar, and a side section of the semiconductor pillar opposed to the control gate has an inversion layer when a voltage is applied to the control gate to reduce the interference due to the parasitic capacitance caused between neighboring memory cells.