Patent ID: 6976194
Filing Date: 2005-12-13
Classification: G11C

Abstract:
1. A memory controller comprising: a check bit encoder circuit coupled to receive a data block to be written to memory, the memory comprising a plurality of memory devices arranged on a plurality of memory modules, each of the plurality of memory modules includes a plurality of the plurality of memory devices, wherein the check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block, wherein the plurality of check bits are defined to provide at least detection of a failure of one of the plurality of memory modules, and wherein the plurality of check bits are further defined to provide probabilistic correction of the failure of one of the plurality of memory modules; and a check/correct circuit coupled to receive the encoded data block from the memory, wherein the check/correct circuit is configured to detect the failure of one of the plurality of memory modules responsive to decoding the encoded data block and to correct the data for the failure.