Patent ID: 6670841
Filing Date: 2003-12-30
Classification: H03K

Abstract:
A level shifting circuit comprising:a discharging circuit to perform a discharge of a first node and a second node with a complementary input signal using a first voltage source as a power supply; and a charging circuit to perform a charge of said first node according to a logical level of said second node and to perform a charge of said second node according to a logical level of said first node, wherein said discharging circuit comprises: a first high-voltage N-type transistor and a second high-voltage N-type transistor whose gates are biased respectively in a predetermined voltage and whose drains are connected to said first and second nodes respectively; and a first low-voltage N-type transistor and a second low-voltage N-type transistor whose drains are connected to sources of said first and second high-voltage N-type transistors respectively, whose gates are connected to said complementary input signal and whose sources are grounded respectively, wherein said charging circuit comprises: a first high-voltage P-type transistor whose drain is connected to said first node, whose gate is connected to said second node and whose source is connected to a second voltage source; a second high-voltage P-type transistor whose drain is connected to said second node, whose gate is connected to said first node and whose source is connected to said second voltage source; a first switching circuit and a second switching circuit connected in parallel to said first and second high-voltage P-type transistors respectively, to keep an OFF state at a stationary state when an input signal does not change; and a charging regulator circuit which charges said second node to the logic â€œHâ€  by setting said second switching circuit to an ON state and thereafter brings back said second switching circuit to an OFF state when said first node is changed from the logic â€œHâ€  to the logic â€œLâ€  by a change of said input signal, and which charges said first node to the logic â€œHâ€  by setting said first switching circuit to an ON state and thereafter brings back said first switching circuit to an OFF state when said second node is changed from the logic â€œHâ€  to the logic â€œLâ€  by the change of said input signal; and wherein said predetermined voltage is set to an intermediate voltage between a threshold voltage of said first and second high-voltage N-type transistors and a breakdown voltage of said first and second low-voltage N-type transistors.