Patent ID: 6378113
Filing Date: 2002-04-23
Classification: G06F

Abstract:
A method for modeling latch transparency using setup time in a circuit timing model having an interface data input pin, an interface data output pin, and a plurality of latches with each latch receiving a data signal and a clock signal, said method comprising the steps of:a) for each of said plurality of latches, calculating an arrival time from a latch clock pin to said interface data output pin; b) identifying a maximum arrival time from said step a); c) calculating a setup time for each of said plurality of latches; d) calculating a setup time associated with said interface data output pin using said maximum arrival time; e) identifying a worst-case setup time from said step c) and said step d); and f) implementing said worst-case setup time at said interface data input pin, wherein satisfaction of said worst-case setup time causes said maximum arrival time to also be satisfied and introduces latch transparency in said circuit timing model.