Patent ID: 6938128
Filing Date: 2005-08-30
Classification: G06F

Abstract:
1. A method for reducing memory latency during read requests, comprising: issuing a single read request for data from a first one of a plurality of processors on a local bus; forwarding the single read request to a memory directory associated with a home memory for the data, the home memory being either remote from or associated with the plurality of processors on the local bus according to a location of the data; determining whether the data is located at another one of the plurality of processors on the local bus; determining whether the data has been modified; providing the data to the first one of the plurality of processors according to the single read request in response to whether or not the data is located in another one of the plurality of processors on the local bus and the data is modified without re-issuing the single read request from the first one of the plurality of processors.