Patent ID: 6121124
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A process for device fabrication comprising:forming a layer of dielectric material on a silicon substrate with n-type and p-type regions therein wherein the n-type and p-type regions are separated by a region of oxidized silicon at the surface of the substrate;forming a silicon layer of amorphous or polysilicon over the dielectric layer;forming a refractory metal silicide layer over said amorphous or polysilicon layer;forming a mask over the refractory metal silicide layer to define a first portion in the refractory metal silicide layer, wherein the first portion is defined as a region that overlies the region of oxidized silicon and wherein the mask is configured so that only the first region is exposed through the mask;directing a nitrogen dopant at the first portion of the refractory metal silicide layer thereby causing the nitrogen dopant species to implant in the refractory metal silicide;removing the mask;directing an n-type dopant species at a second portion of the refractory metal silicide layer thereby causing the n-type dopant species to implant in the silicide;directing a p-type dopant at a third portion of the refractory metal silicide layer thereby causing the p-type dopant species to implant in the silicide; andperforming an anneal at a temperature that is sufficient to cause at least some of both the n-type dopant and the p-type dopant to migrate from the silicide layer to the underlying silicon layer.