Patent ID: 6799278
Filing Date: 2004-09-28
Classification: G06F,Y02D

Abstract:
A computer system having a peer bus architecture and operable to enter a powered down state comprising:a plurality of buses operable to couple the computer system to a plurality of devices, wherein each device is operable to send a power management signal, and wherein each bus is configured in a peer bus arrangement and is associated with a power management signal line operable to transmit power management signals; a power state management device operable for waking the computer system from a powered down state upon receiving a power management signal, comprising a dedicated power management signal input operable to receive a combined power management signal, wherein the combined power management signal is representative of the power management signal lines associated with each of the buses; and a plurality of general purpose inputs, wherein each general purpose input is coupled to a single power management signal line, and is operable to record whether that power management signal line transmitted a power management signal; a logic circuit operable to logically combine the power management signal lines to produce a combined power management signal as an input to the dedicated power management signal input, such that the power management device may wake the computer system if any device sends a power management signal that is transmitted across a power management signal line; a first software agent operable to review the general purpose inputs to determine which power management signal line transmitted a power management signal, and store the identity of the general purpose input in a memory location; and a second software agent operable to access the memory location to determine which general purpose input received the power management signal and thereby identify the bus that is associated with the power management signal line that transmitted a power management signal.