Patent ID: 6404935
Filing Date: 2002-06-11
Classification: G06F,G06T

Abstract:
A two-stage correction circuit for processing digital representations of an image attribute, the circuit comprising:a data bus configured to provide an input data signal; a memory having an address input coupled to the data bus, a data output, and a plurality of memory locations, each memory location including an approximation of a mathematical function of a first portion of the input data signal, at least one first stage delta signal, and at least one second stage delta signal; random logic, coupled to the memory to receive the first stage delta signal and the second stage delta signal, and coupled to a portion of said data bus to receive a second portion of the input data signal on an input, and based on the values of the second portion and the first and second stage delta signals, provides an incrementing or decrementing signal; and an incrementor coupled to the random logic that increments or decrements the approximation of the mathematical function according to the incrementing or decrementing signal.