Patent ID: 9099445
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. An electronic device comprising: a substrate having a primary surface; a first interconnect at a first elevation above the primary surface; a plurality of insulating layers over the first interconnect to define a plurality of sealed cavities extending through the plurality of insulating layers toward the first interconnect and spaced apart from each other horizontally, the plurality of sealed cavities spaced vertically apart from the first interconnect and having sidewalls defined by the plurality of insulating layers; an upper insulating layer disposed over the plurality of insulating layers to seal the plurality of cavities; and a second interconnect at a second elevation above the primary surface, the first interconnect, and the plurality of insulating layers, a portion of the second interconnect overlying a portion of the first interconnect at an overlap region, the second interconnect not exposed to the plurality of sealed cavities; wherein along a direction substantially perpendicular to the primary surface, the plurality of sealed cavities is disposed between the first interconnect and the second interconnect at the overlap region and a via located below and electrically connected to the first interconnect and is not exposed within the plurality of sealed cavities.