Patent ID: 7560375
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A method of forming a gas dielectric structure for a semiconductor structure, the method comprising: forming an opening for semiconductor structure in a dielectric layer on a substrate, wherein the opening includes both a wiring opening and a via opening, wherein the via provides a vertical connection to an interconnect line; depositing a non-conductive liner, wherein the non-conductive liner includes one of the group consisting of: silicon nitride (Si after depositing the non-conductive liner, depositing a sacrificial layer over the opening such that the sacrificial layer fails to substantially fill the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening after depositing the sacrificial layer; depositing a conductive liner over the opening after performing the directional etch; depositing a metal in the opening after depositing the conductive liner to form a wire and a contact via; planarizing the metal and the conductive liner after depositing the metal; removing the sacrificial layer sidewall using a dry etching process, after the metal and the conductive liner are planarized, forming a void, wherein the void extends along a side of the contact via and the wire; and depositing a cap layer over the void to form the gas dielectric structure.