Patent ID: 6421085
Filing Date: 2002-07-16
Classification: H04N

Abstract:
A CMOS imager having a correlated double sampling unit comprising:an image sensor having a plurality of photodetectors arranged in a series of rows and columns; a row addressing circuit; a column addressing circuit; a first sample and hold circuit allocated for each of the columns; a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns; a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits; a linear gain amplifier contained in each of the first sample and hold circuits; and an enabling circuit that enables the linear gain amplifiers for the column that is currently being readout and the column that is to be readout after the column currently being readout; wherein the enabling circuit enables the linear gain amplifier for the column to be read next after the column that is currently being read to precharge conductive lines connecting the second sample and hold circuit to the first sample and hold circuit within the column to be read out next.