Patent ID: 6948158
Filing Date: 2005-09-20
Classification: G06F

Abstract:
1. A compiling method for generating a sequence of program instructions for use in a processing architecture with architecture resources executing instructions from a corresponding instruction set, said method comprising the steps of: inputting a source file comprising a plurality of source code instruction statements including at least a first kind of instruction statements and a second kind of instruction statements; selecting at least a first instruction set and a second instruction set for said first kind of instruction statements and said second kind of instruction statements, respectively; and compiling said first kind of instruction statements using said first instruction set (VLIW format) and compiling said second kind of instruction statements using said second instruction set, characterized in that said first and second instruction sets are adapted to be used in the same processing architecture, and said second instruction set (Compact Instruction Format) is a compact instruction set designed to support only a subset of the architecture resources supported by the first instruction set; whereby a single compiler is used to generate both VLIW format and Compact Instruction Format programs used in the same processing architecture.