Patent ID: 6475069
Filing Date: 2002-11-05
Classification: B24B

Abstract:
A method for polishing a semiconductor substrate having a metal layer, an underlying barrier film and an underlying dielectric layer with metal interconnect structures, comprising-the steps of:removing the metal layer by CMP first step polishing using a first step slurry that is highly selective to the metal of the metal layer and less selective to the barrier film to remove the metal of the metal layer with a maximized rate of metal removal by polishing, and to minimize removal of the barrier film, and removing the barrier film by CMP second step polishing using a second step slurry that is highly selective to the barrier film to remove the barrier film with a maximized rate of metal removal by polishing, while minimizing removal of either the metal layer or the dielectric layer to which said slurry is least selective, which provides the height of the dielectric layer at a surface level of the metal interconnect structures, and further, wherein the step of removing the barrier film by CMP second step polishing uses a second step slurry having a pH greater than 7.