Patent ID: 8748938
Filing Date: 2014-06-10
Classification: H01L

Abstract:
1. A solid-state imaging device including a pixel region having a plurality of pixels in a two-dimensional array, each of the plurality of pixels comprising: a first semiconductor region on a substrate; a second semiconductor region on the first semiconductor region; a third semiconductor region on an upper side surface of the second semiconductor region; a fourth semiconductor region on a side surface of the third semiconductor region, in which the side surface is not facing the side surface of the second semiconductor region, the fourth semiconductor region having a conductivity opposite to a conductivity of the third semiconductor region; and a fifth semiconductor region above the second semiconductor region, the fifth semiconductor region having a conductivity opposite to the conductivity of the third semiconductor region, wherein the second semiconductor region comprises a semiconductor having a conductivity opposite to the conductivity of the third semiconductor region or an intrinsic semiconductor, wherein at least an upper portion of the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region define an island-shaped semiconductor, wherein the second semiconductor region and the third semiconductor region comprise a photodiode, wherein signal charges generated by an electromagnetic energy wave that is incident on a region of the photodiode accumulate in the third semiconductor region, wherein one of the first semiconductor region and the fifth semiconductor region, the other one of the first semiconductor region and the fifth semiconductor region, and the third semiconductor region, respectively define a drain, a source, and a gate of a junction field effect transistor, wherein current that flows between the source and the drain of the junction field-effect transistor in accordance with an amount of signal charges accumulated in the third semiconductor region comprises a signal output, wherein a low voltage impinging on the fourth semiconductor region and the fifth semiconductor region and a high voltage impinging on the first semiconductor region higher than the low voltage removes a potential barrier in the second semiconductor region located between the first semiconductor region and the third semiconductor region, and signal charges accumulated in the third semiconductor region are discharged from the third semiconductor region to the first semiconductor region via the second semiconductor region, wherein signal currents of the plurality of pixels in at least one row simultaneously flow to a row pixel signal loading circuit outside the pixel region via signal lines in columns of the plurality of pixels connected to the first semiconductor region, and signal outputs from the plurality of pixels in the at least one row impinge on an output circuit included in the row pixel signal loading circuit wherein during signal discharging, the low-level voltage impinges on a pixel selection line connected to the fifth semiconductor regions of the plurality of pixels arranged in the at least one row and the high-level voltage impinges on pixel selection lines connected to the plurality of pixels arranged in the other rows, and wherein the high-level voltage impinges on the signal lines connected to the columns of the plurality of pixels.