Patent ID: 6751700
Filing Date: 2004-06-15
Classification: G06F

Abstract:
A data processing and storage system comprising:a data processor for processing data items received by the data processor; a set-associative cache memory coupled to the data processor for storing the data items which are received by the data processor and for providing to said data processor data items in response to addressing by the data processor, said set associative cache memory having a plurality of similar associative memory sets addressed by means of a tag and a cache index such that addresses having the same cache index identify corresponding lines in the associative sets; a round-robin allocator for controlling the storage of data items in the cache such that successive data items are stored in different ones of the associative memory sets of the cache in cyclic sequence; a main memory comprising a multiplicity of addressable buffers, said main memory having an address decoder which causes a data item sent to the main memory to be aliased, the number of aliases being greater than N, and the address spacing of the aliases being such that the aliases have the same cache index; and a direct memory access device for storing data items in the main memory; and wherein: (a) the data processor reads data items from the main memory by means of an address pointer; and (b) the direct memory access device, on storing a data item in the main memory, provides to the data processor an incremental address pointer which identifies the next alias of that data item.