Patent ID: 6368908
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A method of fabricating a capacitor, comprising the steps of:providing a substrate with a transistor having a source/drain region on the substrate; forming a dielectric layer over the substrate; forming an etching stop layer over the substrate; forming a stacked layer on the etching stop layer, wherein the stacked layer is formed by alternately forming at least a first conductive layer, a first isolation layer, a second conductive layer, and a second isolation layer in sequence; using the etching stop layer as etching stop point and patterning the stacked layer to form an opening above the source/drain region exposing the etching stop layer; forming a first conductive spacer on the sidewall of the stacked layer exposed by the opening; using the first conductive spacer as a mask to remove a portion of the etching stop layer and the dielectric layer exposed by the opening to form a contact hole exposing the source/drain region; removing the second isolation layer; forming a third conductive layer over the substrate and the first conductive spacer forming a raised region, wherein the third conductive layer fills the contact hole and is electrically coupled with the source/drain region; forming a stacked spacer on a sidewall of the raised regions, wherein the stacked spacer is formed by at least forming a first isolation spacer and a second conductive spacer in sequence; pattern the third conductive layer and the stacked layer; removing the first isolation spacer and the first isolation layer to form a storage electrode defined by the first conductive layer, the second conductive layer, the third conductive layer, the first conductive spacer, and the second conductive spacer; and forming a dielectric film and a fourth conductive layer in sequence over the storage electrode.