Patent ID: 6727141
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A method of making a DRAM array having cells containing trench capacitors and vertical access transistors comprising the steps of:preparing a semiconductor substrate; forming a set of trenches in said substrate; forming a set of capacitors within said set of trenches, members of said set of capacitors having an interior electrode with a top surface; recessing a first subset of said interior electrodes in a first subset of cells with a top surface to a first depth; recessing a second subset of said interior electrodes in a second subset of cells with a top surface to a second depth greater than said first depth by an offset amount, individual members of said second subset being located adjacent to individual members of said first subset; forming vertical transistors in each of said first subset and said second subset, whereby the distance between adjacent top surfaces in adjacent ones of said first and second subsets is increased by an amount dependent on said offset amount; and connecting said first and second subsets of cells to form said DRAM array.