Patent ID: 6696334
Filing Date: 2004-02-24
Classification: H01L

Abstract:
A method of fabricating an integrated circuit, said method comprising:forming a first insulative layer overlying a plurality of gate structures; forming a second insulative layer overlying the first insulative layer; forming a first masking layer to expose a first portion of the second insulative layer which overlies a gate structure of a first transistor type and to protect a second portion of the second insulative layer which overlies a gate structure of a second transistor type within the plurality of gate structures; and etching the exposed first portion of the second insulative layer overlying the gate structure of the first transistor type; halting etching of the exposed first portion of the second insulative layer upon reaching the first insulative layer; removing the first masking layer to expose the second portion of the second insulative layer which overlies the gate structure of the second transistor type; and anisotropically etching the exposed second portion of the second insulative layer and the first insulative layer to form a first spacer abutting the gate structure of the first transistor type and a second spacer abutting the gate structure of the second type.