Patent ID: 7570506
Filing Date: 2009-08-04
Classification: G11C

Abstract:
1. A ferroelectric memory device comprising: a first p-channel type MISFET connected between a first bit line and a first node; a second p-channel type MISFET connected between a second bit line and a second node; a first negative potential generation circuit connected to the first node; a second negative potential generation circuit connected to the second node; and a charge supply circuit connected to the first node and the second node, wherein a gate terminal of the first p-channel type MISFET and the second node are connected to each other, and a gate terminal of the second p-channel type MISFET and the first node are connected to each other, wherein the charge supply circuit is composed of a third p-channel type MISFET and a fourth p-channel type MISFET, wherein the third p-channel type MISFET has one end connected to the first node, another end connected to a first potential, and a gate terminal connected to the second node, and wherein the fourth p-channel type MISFET has one end connected to the second node, another end connected to the first potential, and a gate terminal connected to the first node.