Patent ID: 6551877
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A method of manufacturing a memory device, comprising the steps of:providing a substrate having an active region thereon, wherein the active region includes a plurality of gate structures and a plurality of source/drain regions; forming a liner layer, for covering the gate structures and the source/drain regions; forming an inter-layer dielectric layer over the liner layer, wherein an etching rate of the liner layer is different from that of the inter-layer dielectric layer; etching the inter-layer dielectric layer until a portion of the liner layer is exposed to form a global opening in the inter-layer dielectric layer; etching the liner layer until the source/drain regions are exposed; forming a conductive layer over the substrate that complete fills the global opening; and removing a portion of the conductive layer and the inter-layer dielectric layer to form contacts that connect electrically with the source/drain regions.