Patent ID: 6133091
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method of fabricating a lower electrode of a capacitor adapted for a semiconductor substrate, wherein the substrate has a conductive plug electrically connected to a conductive region, the method comprising:forming a first polysilicon layer on the semiconductor substrate;forming a sacrificial multi-layer on the first polysilicon layer, wherein the sacrificial multi-layer is a stack of alternating first and second sacrificial layers;forming a second polysilicon layer on the sacrificial multi-layer;patterning the second polysilicon layer to form a first opening therein above the conductive plug;forming a planar spacer on a sidewall of the first opening;forming a third polysilicon layer to fill the first opening;anisotropically etching the planar spacer and the sacrificial multi-layer thereunder until exposing the first polysilicon layer to form a second opening while using the second polysilicon layer and the third polysilicon layer as a mask;isotropically etching the first sacrificial layer exposed by the second opening to form a plurality of recesses thereon;forming a fourth polysilicon layer to fill the second opening and the recesses;removing the second polysilicon layer and third polysilicon layer;removing the sacrificial multi-layer; andremoving the exposed part of the first polysilicon layer.