Patent ID: 6199139
Filing Date: 2001-03-06
Classification: G06F,G11C,Y02D

Abstract:
An apparatus for controlling a refresh period of a memory device in a sleep mode in which there is no read and write access to said memory device, said memory device requiring a refresh operation for maintaining stored data, said apparatus comprising:an encoding circuit for encoding data to obtain code that can be used to correct errors equal to or more than dual errors;a decoding circuit for correcting errors and decoding the corrected code; anda refresh period controller for, following a transition to the sleep mode, changing a refresh period by using data, which is stored in said memory device and encoded by said encoding circuit, until the refresh period becomes longest in a condition where there is no error that can not be corrected by said decoding circuit and the number of correctable errors does not exceed a predetermined count, and where a refresh execution circuit for performing the refresh operation to the memory device can deal with the changed refresh period, and for, following the first end of the change of said refresh period, setting said refresh execution circuit so as to perform the refresh operation to said memory device by said refresh period at the first end of the change of said refresh period.