Patent ID: 7888768
Filing Date: 2011-02-15
Classification: H01L

Abstract:
1. A power integrated circuit device, comprising: a semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a first drain area formed in an upper portion of the epitaxial layer; a first body area formed in the upper portion of the epitaxial layer apart from the first drain area; a first gate area formed in an upper portion of the first body area; a first source area formed in the upper portion of the epitaxial layer apart from the first body area; a second body area having a low concentration of p-type dopant and formed in the epitaxial layer and apart from the first body area; a buried layer having a high concentration of n-type dopant and formed between the second body area and the semiconductor substrate in a vertical direction; a second drain area formed in an upper portion of the second body area; a second source area formed in the upper portion of the second body area apart from the second drain area; a gate electrode formed in an upper portion between the second drain area and the second source area; a first metal line formed on an upper surface of the epitaxial layer and electrically connecting the first gate area to the second source area; and a second metal line formed on the upper surface of the epitaxial layer and electrically connecting the first source area to the second drain area.