Patent ID: 7415554
Filing Date: 2008-08-19
Classification: G06F

Abstract:
1. A system for parallel data transmission, comprising: a master device comprising a first I/O port for outputting a read signal and a second I/O port for outputting a write signal; and a slave device comprising a third I/O port electrically coupled to the first I/O port for receiving the read signal and a fourth I/O port electrically coupled to the second I/O port for receiving the write signal, wherein after the master device outputs the read signal instructing that the master device reads data from the slave device or outputs the write signal instructing that the master device writes data to the slave device, the slave device transmits status information of the slave device to the master device through the third and the fourth I/O ports during the duty cycle of an address latch enable signal which is transmitted by the master device, wherein the master device, wherein the master device transmits an address signal after the address latch enable signal is enabled, and the slave device has latched the address signal for the addressing for reading or writing data after the address latch enable signal is disabled.