Patent ID: 6773972
Filing Date: 2004-08-10
Classification: G11C,H01L

Abstract:
A method of forming a semiconductor circuit, comprising the steps of:forming a first transistor, comprising the steps of: forming a first source/drain region as a first doped region in a fixed relationship to a semiconductor substrate; forming a second source/drain region as a second doped region in a fixed relationship to the semiconductor substrate, wherein the second doped region and the first doped region are of a same conductivity type; and forming a first gate in a fixed relationship to the first source/drain region and the second drain region; and forming a second transistor, comprising the steps of: forming a third source/drain region as a third doped region in a fixed relationship to the semiconductor substrate; forming a fourth source/drain region as a fourth doped region in a fixed relationship to the semiconductor substrate, wherein the fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions; forming a second gate in a fixed relationship to the third source/drain region and the fourth drain region; and wherein the steps of forming the first gate and the second gate comprise forming the first gate to comprise a first dopant concentration and forming the second gate to comprise a second dopant concentration different from the first dopant concentration.