Patent ID: 7466177
Filing Date: 2008-12-16
Classification: H03K

Abstract:
1. A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range, comprising: an input control stage, for receiving an input clock and a feedback signal, and changing the pulse-width ratio of the input clock according to the feedback signal so as to generate a modulating signal; a buffer module, for buffering and reversing the modulating signal, thereby generating an output clock and a complementary signal, wherein the phases of the output clock and the complementary signal are opposite to each other; a programmable charge pump, comprising: at least one 2-stage LPF, for filtering the first and the second comparative signals; and a transconductor, for comparing the first and the second comparative signals, thereby adjusting the feedback signal to be fed back the input control stage.