Patent ID: 6031473
Filing Date: 2000-02-29
Classification: H03M

Abstract:
A data transmission system comprising:a first integrated circuit including a first circuit having an input for receiving input data and an output pin for transmitting corresponding serial output data;a second integrated circuit including an input pin and a second circuit for receiving the serial output data from the first circuit; anda serial bus coupled to the output pin of the first integrated circuit and the input pin of the second integrated circuit;the first circuit further including:an input register for latching parallel data;a bit serializer coupled to the input register and having a data line for each parallel bit of data, the bit serializer for providing the serial output data;a detection delay line having a plurality of taps coupled to the bit serializer, and comprising serially connected delay units;a clock signal source; anda clock multiplier coupled to the detection delay line and configured to receive the clock signal, the clock multiplier operative for multiplying the frequency of the clock signal in order to increase the rate at which the serial output data is transmitted;wherein the second circuit includes a bit deserializer for converting input data from the serial bus into parallel data for use within the second circuit.