Patent ID: 7315603
Filing Date: 2008-01-01
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor storage device comprising: a memory cell array having a plurality of memory elements whose addresses can be designated; a write state machine which is connected to the memory cell array, controls operations to be performed on the memory cell array, receives control signals that represent one operation or a sequence of operations to be performed at at least one block of at least one address in the memory cell array, receives predetermined bits of an identification of a block of addresses, further receives a protect signal, generates an active lock signal if the predetermined bit of the identification of the block of the addresses and the protect signal are in predetermined states, responds to the lock signal by failing to perform the operation identified, and responds to an absence of the lock signal by performing each operation identified on every address within the block; and a command state machine which is connected so as to receive data including commands and generates control signals for controlling the write state machine and the protect signal, each memory element of the memory cell array comprising: a gate electrode formed on a semiconductor layer via a gate insulator; a channel region disposed below the gate electrode via the gate insulator; diffusion regions which are disposed on both sides of the channel region and have a conductive type opposite to a conductive type of the channel region; and memory function bodies which are formed on both sides of the gate electrode and have a function to retain electric charge or polarization, wherein the write state machine comprises: an address counter which receives and buffers control signals to be applied to addresses within a given block of the memory cell array from the command state machine, and iteratively outputs signals to address memory elements in the memory cell array corresponding to the block of the addresses, and which further comprises a protected address detector which detects protected memory address and which senses a state of the protect signal by detecting a protected memory address, wherein the address counter outputs an active lock signal if the predetermined bits of an address are in predetermined states indicating that the address is to be protected and the protect signal is in a predetermined state indicating that the address is to be protected, a state controller connected so as to receive the identification of the operation to be performed and the lock signal, wherein the state controller determines a state of the write state machine, and indicates that the state of the write state machine is a state in which the operation is not performed if the operation is an identified operation and the lock signal is active.