Patent ID: 8697456
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method for wafer testing, comprising: providing a wafer having a plurality of integrated circuits and a patterned passivation layer over the integrated circuits, wherein the patterned passivation layer has openings therethrough, and wherein individual openings expose at least a portion of corresponding individual pads of the integrated circuits; forming conductive lines individually having a first end and a second end, an individual conductive line being connected to a corresponding integrated circuit pad toward the first end; and forming conductive contact pads over the passivation layer with an individual contact pad connected to the corresponding individual conductive line toward the second end of the individual conductive line, the individual contact pad having a surface area that is greater than a surface area of the corresponding integrated circuit pad, wherein forming the conductive lines and the contact pads includes printing the conductive lines and pads with a material that is removable by a solvent that does not substantially remove the integrated circuit pad.