Patent ID: 6389521
Filing Date: 2002-05-14
Classification: G11C

Abstract:
A memory comprising:a memory array, partitioned into N (N=2n, n is an integer; N is an integer of 2 or greater) divisional memory areas, each of said divisional memory areas including a plurality of memory cells arranged in a matrix, cells at the same row of the matrix in a divisional memory area being accessed simultaneously; a serial access memory (SAM) array partitioned into M (M=2m, m is an integer greater than or equal to 2; M is an integer of 4 or greater) divisional SAM areas serially accessed asynchronously with said memory array, each of said divisional SAM areas corresponding to one of said divisional memory areas and temporarily storing data from cells of one row of said matrix of the divisional memory areas; and a data transfer unit to transfer data between one divisional memory area of said memory array and its corresponding divisional SAM area of said serial access memory array; wherein if data corresponding to a boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a divisional SAM area being serially accessed, a data transfer timing from one of the divisional memory areas to the divisional SAM area and an output timing from the divisional SAM area are synchronized.