Patent ID: 7102662
Filing Date: 2006-09-05
Classification: G06K

Abstract:
1. A data sequence conversion circuit which takes as an input any one of a plurality of input data sequences having different data widths, and which converts said input data sequence into an output data sequence having a prescribed data width for output, said circuit comprising: a first parallel shift register that receives parallel input data having a first data width, wherein the first parallel shift register receives a sequence of data elements respectively having the first data width and holds the sequence of data elements together in the first parallel shift register; a switch matrix receiving the data held in said first parallel shift register as input data, and outputting said input data in a distributed fashion in accordance with a rule selected by a control signal from a plurality of predetermined rules; and a second parallel shift register receiving the data output from said switch matrix as input data, and outputting said input data as parallel output data having a second data width different from the first data width, wherein the second parallel shift register outputs said input data as a sequence of data elements respectively having the second data width.