Patent ID: 8473764
Filing Date: 2013-06-25
Classification: G06F,Y02D

Abstract:
1. A data processing system comprising: a processing unit; at least one bus coupled to the processing unit; at least one subsystem coupled to the at least one bus; a power controller coupled to the processing unit and to the at least one subsystem, the power controller being configured to reduce power consumed by the at least one subsystem in response to a first state of an instruction queue in memory for the at least one subsystem, the instruction queue being accessible to a software driver for the at least one subsystem which communicates a status of the first state to the processing unit which in response reduces power, through the power controller, to the at least one subsystem, wherein the first state represents an instruction queue having only instructions for future events or actions, and wherein, over a period of time, the power for the processing unit is reduced after a first period of time and the power for the subsystem is turned on such that it is on for a second period of time after the first period of time and then power to the processing unit is turned on to allow the processing unit to reduce power for the subsystem after the second period of time.