Patent ID: 6358803
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A method of fabricating a source/drain region in a substrate, comprising:forming a stack on the substrate having a gate electrode and an insulating layer positioned on the gate electrode, the insulating layer having an etch selectivity to the gate electrode; forming a first doped region in the substrate adjacent to the stack and with a first horizontal junction; forming a second doped region in the substrate overlapping the first doped region with a second horizontal junction positioned beneath the first horizontal junction; performing an implant of impurity ions into the substrate to establish a third doped region overlapping the second doped region and with a third horizontal junction positioned beneath the second horizontal junction, the insulating layer substantially preventing impurity ions from penetrating through the gate electrode; removing the insulating layer by etching selectively to the gate electrode after performing the implant of impurity ions to establish the third doped region; and heating the substrate to activate the first, the second and the third doped regions.