Patent ID: 7932176
Filing Date: 2011-04-26
Classification: C23C,H01L

Abstract:
1. A process for forming an integrated circuit interconnect structure, said process comprising: a) providing a partially-completed interconnect structure comprising an electrically insulating region and an electrically conductive copper-containing region, said partially-completed interconnect structure having a substantially planar surface; b) depositing a metal (M) selected from the group consisting of manganese, chromium and vanadium on or into at least a portion of the electrically conductive copper-containing regions; c) depositing an insulating film on at least a part of the deposited metal, wherein the region of the deposited insulating film in contact with said at least a part of the deposited metal is substantially free of oxygen; d) reacting at least a part of the deposited metal with the insulating film to form a barrier layer, wherein the electrically conductive copper-containing region is substantially free of elemental metal (M).