Patent ID: 7661051
Filing Date: 2010-02-09
Classification: G01R

Abstract:
1. An apparatus comprising: a comparator circuit configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal; a reference circuit configured to generate said reference signal in response to a first control signal; a plurality of elements each configured to generate an intermediate test signal, wherein one of said intermediate test signals is presented as said test signal by activating one of said elements, in response to a second control signal; and a logic circuit configured to generate (i) said first control signal and (ii) said second control signal, each in response to said difference signal, wherein (A) said plurality of elements are sequentially tested until each of said plurality of elements have been tested, (B) said comparator circuit generates an individual difference signal for each of said plurality of elements, (C) said logic circuit generates an output signal in response to each of said individual difference signals, (D) said output signal comprises an average of said individual difference signals, and (E) said output signal comprises an error signal.