Patent ID: 6496610
Filing Date: 2002-12-17
Classification: G06F,G11C

Abstract:
A semiconductor integrated device comprising on one semiconductor substrate an image processor in which logic circuits are integrated, a first dynamic RAM in which command and source data are stored and a second dynamic RAM in which drawing information is stored, whereinsaid first dynamic RAM and said second dynamic RAM are arranged at opposite ends of said image processor, wherein said image processor includes: a drawing command fetch section for fetching a command from said first dynamic RAM and outputting an edge operation start signal after completion of fetching; an edge operating section for performing an operation of coordinates of a start point and an end point after conversion when an original picture to be converted is divided into predetermined lines; a line operating section for performing an operation of filling up a space between said start and end points of the line into a straight line and addressing it; a dot operating section for taking in dot data from said dynamic RAM and starting a memory access to said second dynamic RAM to write a drawing address and the dot data therein; and a display controller for outputting display data of said second dynamic RAM to the exterior.