Patent ID: 9208893
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A method of measuring read margin of one or more programmable non-volatile memory cells, comprising the steps of: precharging a sense node in a memory cell, the memory cell including a programmable floating-gate transistor in a non-conductive state having its source/drain path connected between the sense node and a first array voltage by a select transistor; after the precharging step, energizing a word line coupled to a gate of a select transistor, the select transistor having a source/drain path connected in series with the source/drain path of the floating-gate transistor between the sense node and the array voltage; advancing a counter responsive to a periodic clock signal; and responsive to a transition at an output of a read circuit coupled to the sense node of the memory cell, storing the contents of the counter.