Patent ID: 6110782
Filing Date: 2000-08-29
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:forming isolation areas on a semiconductor substrate surrounding and electrically isolating device areas, said device areas being a low voltage device area and a high voltage device area;providing a gate oxide layer in said device areas;depositing a polysilicon layer overlying said gate oxide layer and said isolation areas;forming a first photomask over a portion of said high voltage device area wherein said first photomask also completely covers said low voltage device area;etching away said polysilicon layer not covered by said first photomask to form said high voltage device;thereafter implanting first ions to form lightly doped source and drain regions within said semiconductor substrate adjacent to said high voltage device wherein said first photomask protects said polysilicon layer in said low voltage device area from said ions;removing said first photomask;forming a second photomask over a portion of said low voltage device area where a gate electrode is to be formed wherein said second photomask also completely covers said high voltage device area;etching away said polysilicon layer not covered by said second photomask to form said gate electrode;removing said second photomask; andcompleting the fabrication of said integrated circuit device.