Patent ID: 6328572
Filing Date: 2001-12-11
Classification: G06F,H05K

Abstract:
A motherboard comprising a board, a plurality of connector elements installed on said board, and a bus line which is formed on said board for interconnecting said plurality of connector elements, so as to allow interconnection of a plurality of daughter boards connected to said plurality of connector elements via said bus line, whereina termination board having a terminating resistance to decrease reflection noise of said bus line is connected to a connector element at the last stage of said bus line among said plurality of connector elements;one of said plurality of daughterboards being comprised of a CPU board for performing high-speed arithmetic processing and transmitting reference clock signals to each other daughter board, is connected at the most upstream position in said bus line among said plurality of connector elements;all said plurality of connector elements to which said daughter boards are connected are installed in a row on the front face of said board and said connector element at the last stage to which said termination board is connected is installed on the rear face of said board and back-to-back on the rear side of said connector element positioned at the last part of said bus line out of said plurality of connector elements installed in a row on the front face of said board.