Patent ID: 6482698
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method for manufacturing an integrated circuit comprising a memory device and a logic circuit, the method comprising:forming a first gate oxide layer having a first thickness on first and second portions of a semiconductor substrate which are intended, respectively, for a plurality of first transistors of the logic circuit operating at a first voltage and for a plurality of second transistors of the logic circuit operating at a second voltage less than the first voltage; forming a second gate oxide layer having a second thickness on third portions of the semiconductor substrate for a plurality of memory cells of the memory device; forming a first conducting layer on the first, second and third portions of the semiconductor substrate; selectively removing the first conducting layer from the first and third portions of the semiconductor substrate to define gate electrodes for the plurality of first transistors and floating gate electrodes for the plurality of memory cells, and removing the first conducting layer from the second portions of the substrate; forming a first dielectric layer on the first, second and third portions of the semiconductor substrate; selectively removing the first dielectric layer from the first and third portions of the substrate so that the first dielectric layer remains on the gate electrodes of the plurality of first transistors and on the floating gate electrodes of the plurality of memory cells, and removing the first dielectric layer and the first gate oxide layer from the second portions of the semiconductor substrate; forming a third gate oxide layer on the second portions of the semiconductor substrate having a third thickness less than the first thickness of the first gate oxide layer; forming a second conducting layer on the first, second and third portions of the semiconductor substrate; selectively removing the second conducting layer from the third portion of the semiconductor substrate to define the floating gate electrodes for the plurality of memory cells; and selectively removing the second conducting layer from the first and second portions of the semiconductor substrate to define the gate electrodes for the plurality of second transistors and to form conducting covers for the gate electrodes for the plurality of first transistors.