Patent ID: 9019760
Filing Date: 2015-04-28
Classification: B82Y,H01L

Abstract:
1. A memory device, comprising: a back gate including at least a first portion of electrically conductive material; a first portion of dielectric material arranged on the back gate; a semiconductor nanobeam configured to receive electrons and holes, arranged on the first portion of dielectric material; a second portion of dielectric material covering at least the semiconductor nanobeam, the second portion being connected to the first portion of dielectric material at a first side of the semiconductor nanobeam and at a second side of the semiconductor nanobeam, and extending along the first side, the second side, and an upper surface of the semiconductor nanobeam; a portion of material configured to store electrical charges, and covering the second portion of dielectric material; a third portion of dielectric material covering the portion of material configured to store electrical charges; and a front gate having at least a second portion of electrically conductive material covering the third portion of dielectric material.