Patent ID: 7202719
Filing Date: 2007-04-10
Classification: H03K,H03L

Abstract:
1. A digital-to-phase converter (DPC) comprising: a frequency source for providing a clock signal having a first frequency; at least a first delay-locked loop configured to receive the clock signal for generating a first plurality of phase-shifted clock signals, each phase-shifted clock signal having substantially the first frequency and being shifted in phase with respect to the clock signal and with respect to the other phase-shifted clock signals in the first plurality; a control device coupled to the frequency source and configured for receiving an input signal identifying a desired frequency for a synthesized signal; at least a first selection circuit for receiving the first plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the control device, at least one sequence of the phase-shifted clock signals in the first plurality and outputting a corresponding coarse synthesized signal based on each sequence; and at least a first variable delay cell having a first input coupled to the selection circuit to receive the corresponding coarse synthesized signal and a second input coupled to the control device, wherein the control device further generates at least one fine tune adjustment signal used by the first variable delay cell to modify the corresponding coarse synthesized signal using a plurality of different delay amounts to generate at an output of the first variable delay cell a first fine synthesized signal.