Patent ID: 7382674
Filing Date: 2008-06-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells each of which is of a static type and includes a driving MIS (Metal Insulator Semiconductor) transistor and a load MIS transistor; a source terminal which supplies a source potential to the memory cells; a first switching element which electrically connects the source terminal and a first power supply potential in an operation mode of the memory cells, and electrically disconnects the source terminal and the first power supply potential in a standby mode of the memory cells; a clamp MIS transistor which is series-connected between the source terminal and the first power supply potential, and clamps the source potential in the standby mode; a bias generation circuit which supplies a first bias potential to a gate terminal of the clamp MIS transistor; and a switching circuit which switches a potential of a back gate terminal of the clamp MIS transistor between a test mode and a non-test mode.