Patent ID: 6069824
Filing Date: 2000-05-30
Classification: G11C

Abstract:
An electrically erasable and programmable semiconductor memory device comprising:a plurality of nonvolatile memory cells, each said memory cell including a control gate, a floating gate for the storage of charges thereon, a drain and a source;a word line connected to the respective control gates of the nonvolatile memory cells;a source line connected to the respective sources of the nonvolatile memory cells;a plurality of bit lines, each said bit line being connected to the drain of associated one of the nonvolatile memory cells;a driver for applying a positive potential and a ground potential to the word and source lines, respectively, during a read cycle;means for applying another positive potential to the respective bit lines during the read cycle; anda plurality of switching devices for grounding the source line at a plurality of discrete positions in order that current, flowing from the bit lines through some of the nonvolatile memory cells having lower threshold voltages into the source line, is not concentrated at the driver during the read cycle.