Patent ID: 6060401
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A method of forming a dual cylindrical capacitor on a semiconductor substrate having at least a device isolation structure and a transistor, wherein the transistor includes at least a gate and a source/drain region, the method comprising:forming a first insulation layer on the substrate;forming a contact window penetrating through the first insulation layer to expose the source/drain region;forming a first conductive layer on the first insulation layer to fill the contact window and to couple with the source/drain region;removing a part of the first conductive layer to form a protrusion aligned over a perimeter of the contact window;forming a second insulation layer to cover an inner side wall and an outer side wall of the protrusion;etching the first conductive layer with the second insulation layer as a mask, the first conductive layer encompassed by the protrusion being etched along the inner side wall of the protrusion and self stopped while the inner side wall merge at a point;removing the second insulation layer;forming a dielectric layer to cover the first conductive layer; andforming a second conductive layer on the dielectric layer.