Patent ID: 6660570
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method for fabricating a high voltage semiconductor device, comprising the steps of:forming an oxide layer on a semiconductor substrate of a first conductivity type used as a collector region such that the surface of the semiconductor substrate is partially exposed, the semiconductor substrate having an active region and a field region; forming a base region of a second conductivity type by ion-implantation; forming an emitter region of a first conductivity type in the base region and a channel stopper of the first conductivity type in the field region to be separated from the base region by a predetermined distance, using the oxide layer as an ion-implantation mask; sequentially forming a semi-insulating polycrystalline silicon layer and a thermal oxide layer by a thermal oxidation process on the oxide layer; partially exposing the surfaces of the emitter region, the base region and the channel stopper by patterning the thermal oxide layer, the semi-insulating polycrystalline silicon layer and the oxide layer; and forming an emitter electrode, a base electrode, an equipotential electrode and a collector electrode to be electrically connected to the emitter region, the base region, the channel stopper and the semiconductor substrate, respectively.