Patent ID: 7569481
Filing Date: 2009-08-04
Classification: H01L

Abstract:
1. A method for forming a via-hole, comprising the steps of: (a) forming a mask on an insulating layer on a semiconductor substrate, including a lower metallization or wiring layer, wherein the mask comprises a photo-resist pattern and the insulating layer comprises at least one of the following: silicon dioxide silicon nitride, silicon oxynitride, or silicon-rich oxide; (b) using the mask, dry etching the insulating layer in a chamber to form a via-hole in the insulating layer, wherein a polymer residue from the photo-resist pattern remains in the via-hole; and (c) simultaneously etching a top portion of the insulating layer, etching a portion of the mask in the vicinity of the via-hole, and removing the polymer residue, in situ in the etching chamber, with an etchant comprising oxygen and argon.