Patent ID: 8748264
Filing Date: 2014-06-10
Classification: H01L

Abstract:
1. A process comprising: forming a shallow trench isolation (STI) in a semiconductive substrate, wherein the STI includes a prominence with a sidewall, the prominence having a top width wider than a bottom width of the prominence, and wherein forming the STI includes forming the STI through a sacrificial film and a repaired gate oxide layer; depositing a discrete storage element film upon a tunnel dielectric film, wherein depositing the discrete storage element film is carried out with exposure to, and laterally adjacent to, a reentrant undercut form factor of the sidewall of the STI, and wherein depositing the discrete storage element film is carried out without completely covering the reentrant undercut form factor of the sidewall of the STI; forming a gate dielectric above the discrete storage element film, wherein the gate dielectric is a non-continuous film having portions above the STI and above the semiconductive substrate but not along the sidewall of the prominence of the STI; forming a wordline above the gate dielectric; and forming an active area in the semiconductive substrate, adjacent to and below the discrete storage element film.