Patent ID: 8086776
Filing Date: 2011-12-27
Classification: G06F

Abstract:
1. An arbiter configured to receive access requests for a bus with identifiers of access modules which issue the access requests and arbitrate the access requests, the arbiter comprising: a register configured to store an identifier of a next-previous access module which made a next-previous access to the bus; and a counter unit configured to count a number of consecutive accesses to the bus made by the next-previous access module and reset the number of consecutive accesses to zero if an access made by an access module other than the next-previous access module is permitted, or one or fewer bus masters transmit the bus-access request, wherein the arbiter is configured to suppress the access request from the next-previous access module if the number of consecutive accesses matches a predetermined number; the arbiter is configured to determine whether pending access requests include an access request issued from the next-previous access module by comparing identifiers of the pending access requests with the identifier of the next-previous access module stored in the register; and the arbiter is configured to control priority of access request for the bus by the plurality of access modules so that the priority is given to the next-previous access module if it is determined that the pending access requests include the access request issued from the next-previous access module.