Patent ID: 6738302
Filing Date: 2004-05-18
Classification: G11C

Abstract:
An integrated circuit device including a read data amplifier coupled to first and second complementary read data lines and an intermediate data output, the read data amplifier comprising:first upper and lower series connected transistors defining a first circuit node therebetween coupling said first of said complementary read data lines to a tail node; second upper and lower series connected transistors defining a second circuit node therebetween to form said intermediate data output and coupling said second of said complementary read data lines to said tail node, control terminals of said first and second upper transistors being coupled to said first circuit node, a control terminal of said second lower transistor being coupled to said first data read line and a control terminal of said first lower transistor being coupled to said second data read line; a tail transistor coupling said tail node to a first voltage source; first and second precharge transistors respectively coupling said first and second circuit nodes to a second voltage source; first and second pull up transistors respectively coupling said first and second complementary read data lines to said second voltage source; and an enable input coupled to a control terminal of said tail transistor and said first and second precharge transistors for enabling said read data amplifier.