Patent ID: 8316191
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. A processor chip, comprising: multiple programmable units integrated in the processor chip, wherein at least some of the multiple programmable units integrated in the processor chip comprise multi-threaded programmable units having multiple program counters corresponding to multiple threads of program execution; a first random access memory controller integrated in the processor chip to couple to a first off-chip random access memory, the first random access memory controller coupled to the multiple programmable units integrated in the processor chip, the first random access memory controller comprising logic to enqueue entries for memory reference requests received from the multiple programmable units into one of a first set of multiple queues and select from the enqueued entries to initiate a memory access operation of the first off-chip random access memory; and a second random access memory controller integrated in the processor chip to couple to a second off-chip random access memory, the second random access memory controller coupled to the multiple programmable units integrated in the processor chip, the second random access memory controller comprising logic to enqueue entries for memory reference requests received from the multiple programmable units into one of a second set of multiple queues and select from the enqueued entries to initiate a memory access operation of the second off-chip random access memory, wherein the first random access memory controller implements a first arbitration policy for the first set of multiple queues and the second random access memory controller implements a second arbitration policy for the second set of multiple queues, wherein the first arbitration policy and the second arbitration policy are different.