Patent ID: 8392739
Filing Date: 2013-03-05
Classification: G06F,Y02D

Abstract:
1. A multi-core processor comprising a plurality of processor cores among which a synchronous communication is performed, characterized in that each processor core includes a frequency conversion device, which comprises a multiple selector and further comprises a state changing means, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit, wherein: the state changing means is adapted to output data of a plurality of frequency conversion coefficients to the multiple selector, an output of the state changing means being connected to a data input of the multiple selector; the frequency conversion coefficient register is adapted to store the current frequency conversion coefficient of the processor core, and its output is connected to a selection input of the multiple selector; the multi-input OR gate is adapted to receive the output obtained by the multiple selector according to the state changing means and the frequency conversion coefficient register and receive data valid bits which are sent from other processor cores to the processor core, and to change its output state into a valid state and send a gating signal to the clock-gating circuit unit; and the clock-gating circuit unit is adapted to receive a common original clock of the processor core as its clock input and receive the gating signal output by the multi-input OR gate as its gating enable input, the output clock being the common original clock.