Patent ID: 8039284
Filing Date: 2011-10-18
Classification: H01L

Abstract:
1. A method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate; forming a first source/drain region of an NMOS device, wherein the first source/drain region has at least a portion in the semiconductor substrate; forming a second source/drain region of a PMOS device, wherein the second source/drain region has at least a portion in the semiconductor substrate, and wherein at least one of the first source/drain region and the second source/drain region has an internal stress material; masking the PMOS device by forming a first stressed film having a first intrinsic stress over the PMOS device; forming a first source/drain electrode on the first source/drain region while the first stressed film is over the PMOS device, the first source/drain electrode having a first barrier height less than about 0.4eV, wherein the forming the first source/drain electrode comprises using a selective electroless plating process; masking the NMOS device; forming a second source/drain electrode having a second barrier height greater than about 0.7eV on the second source/drain region using an additional electroless plating process; and forming a second stressed film having a second intrinsic stress over the NMOS device and over and adjoining the first stressed film, wherein the second intrinsic stress is more tensile than the first intrinsic stress.