Patent ID: 6187669
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method of forming a node contact on a semiconductor wafer, the semiconductor wafer comprising a substrate, a dielectric layer positioned on the substrate, and a first bit line and a second bit line positioned on the dielectric layer, each of the two bit lines having two vertical side walls and a rectangular cross section, and comprising a conductive layer on the dielectric layer with an overlying first insulating layer wherein a first side wall of the first bit line is adjacent to a second side wall of the second bit line and the first side wall comprises a first region and two second regions adjacent to the first region, the distance between the first region and the second side wall being greater than a predetermined value and the distance between the two second regions and the second side wall being less than the predetermined value; the method comprising:forming a second insulating layer on the dielectric layer and the two bit lines which fills the gap between each of the two second regions and the second side wall and partially fills the gap between the first region and the second side wall which forms a groove over the gap between the first region and the second side wall;performing a first anisotropic etching process to completely remove the second insulating layer above the two bit lines and to extend the bottom of the groove between the first region and the second side wall down to the dielectric layer, the remaining second insulating layer around the groove forming a spacer for covering and isolating the conductive layer in each of the two bit lines around the groove, the remaining second insulating layer in the gaps between the two second regions and the second side wall still completely covering the surface of the two gaps; andperforming a second anisotropic etching process to remove the dielectric layer at the bottom of the groove in a vertical direction down to the substrate so as to form the node contact.