Patent ID: 7221205
Filing Date: 2007-05-22
Classification: H03K

Abstract:
1. A circuit for storing a signal value, said circuit comprising: an operational clock signal source operable in an operational mode to provide an operational clock signal; an operational data path operable to store an operational signal value and including: a diagnostic clock signal source operable in a diagnostic mode to provide a diagnostic clock signal; a diagnostic data path operable to store a diagnostic signal value and including: a sleep mode control signal source operable to provide a sleep mode control signal; a sleep mode path selectively connected under control of said sleep mode control signal to allow transfer of said operational signal value between one of said operational data path master latch or said operational data path slave latch and one of said diagnostic data path master latch or said diagnostic data path slave latch, whereby said diagnostic data path serves to store said operational signal value whilst said operational path is powered down during said sleep mode, wherein a fastest signal path through said operational data path is a primary path and said sleep mode path connects to a point in said operational data path which is decoupled from said primary path.