Patent ID: 6650566
Filing Date: 2003-11-18
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a memory cell array formed of a plurality of memory cell strings each connected to a plurality of bitlines; a plurality of page buffers each connected to a corresponding one of the bitlines; a plurality of transistors connected between the bitlines and the page buffers, each of the plurality of transistors operative when turned off to electrically isolate each of the plurality of page buffers from the corresponding one of the plurality of bitlines; and a bitline voltage controller applying a bitline control voltage to gates of the transistors selectively to turn the transistors off thus to effect electrical isolation between each of the plurality of page buffers from the corresponding one of the plurality of bitlines; wherein the bitline control voltage is charged to a first voltage during a first bitline setup period and charged to a second voltage during a second bitline setup period subsequent to the first bitline setup period, the second voltage being lower than the first voltage.