Patent ID: 7570509
Filing Date: 2009-08-04
Classification: H01L,H03K

Abstract:
1. A semiconductor device comprising: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film; b) a first inverter having a first n-channel type MISFET and a first p-channel type MISFET connected in series each other, being formed on a first region in the multiple layered substrate; c) a second inverter having a second n-channel type MISFET and a second p-channel type MISFET connected in series each other, being formed on a second region; d) a first wiring connecting the output of the first inverter to the input of the second inverter; e) a second wiring connecting the output of the second inverter to the input of the first inverter; f) a first back gate region formed on the first region in the semiconductor substrate; g) a second back gate region formed on the second region in the semiconductor substrate; (h) a first connecting portion between the first wiring and the second back gate region; and (i) a second connecting portion between the second wiring and the first back gate region.