Patent ID: 8426907
Filing Date: 2013-04-23
Classification: H01L

Abstract:
1. A nonvolatile memory device comprising: a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer, wherein the charge trapping layer comprises a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap, the first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer, and wherein the first charge trapping layer comprises a silicon nitride layer and the second charge trapping layer comprises a silicon oxynitride layer.