Patent ID: 6323089
Filing Date: 2001-11-27
Classification: G11C,H01L

Abstract:
A method for forming a gate electrode for a semiconductor device, comprising the steps of:a) providing a substrate having a top surface;b) forming a first insulator layer over said top surface of said substrate;c) forming a first electrode layer over said first insulator layer;d) forming a second insulator layer over said first electrode layer;e) placing a mask of predefined size and shape over said second insulator layer;f) removing an unmasked portion of said second insulator layer, and leaving a remaining portion of said second insulator layer having at least two exposed opposite outer walls;g) removing a predefined amount of an unmasked portion of said first electrode layer, and leaving a remaining portion of said first electrode layer, said remaining portion of said first electrode layer including an unetched portion and a partially etched portion that overlies less than all of said unetched portion;h) removing said mask to expose a top surface of said second insulator layer;i) depositing a second electrode layer over said exposed top surface and over said exposed outer walls of said second insulator layer and also over said remaining portion of said first electrode layer; andj) removing a predefined amount of said second electrode layer to expose a top surface of said second insulator layer, whereby a remaining portion of said second electrode layer forms at least a portion of the gate electrode, and wherein a remaining portion of said second electrode layer disposed over said outer walls of said second insulating layer forms edges of the gate electrode, said edges having opposing inner walls that are substantially vertical to the plane of said substrate, each of said edges also having a sharp edge formed on a top surface thereof, said edges for facilitating electron tunneling.