Patent ID: 6747309
Filing Date: 2004-06-08
Classification: H01L

Abstract:
An integrated semiconductor device comprising at least one logic transistor, at least one high voltage transistor and at least one nonvolatile floating gate memory cell,said memory cell comprising a first gate oxide layer over a silicon substrate, source and drain regions in said silicon substrate, a floating gate over said first gate oxide layer, a control gate superimposed on said floating gate, and a dielectric layer interposed between said floating gate and said control gate and electrically insulating said floating gate and said control gate, said logic transistor comprising a second gate oxide layer over said silicon substrate, a gate superimposed on said second gate oxide layer said second gate oxide layer has a different thickness than said first gate oxide layer; said high voltage transistor comprising a gate oxide superimposed on said silicon substrate and constituted by said first gate oxide layer, a lower gate superimposed on said gate oxide and constituted by a first polysilicon layer, and an intermediate dielectric layer superimposed on said lower gate and constituted by said dielectric layer.