Patent ID: 9157961
Filing Date: 2015-10-13
Classification: G01R

Abstract:
1. A scan test system for testing a design implemented in an integrated circuit (IC), the design including a plurality of blocks and a plurality of scan chains, the system comprising: a plurality of compressor and decompressor structures (CODECs); an instruction decode unit (IDU) configured to receive scan inputs from a tester, to determine whether a seed extracted from the scan inputs is broadcast loaded in the plurality of CODECs, multicast loaded in a subset of the plurality of CODECs, or individual loaded in a single CODEC, and to transmit one or more CODEC enable signals to said the plurality of CODECs, wherein said plurality of CODECs are connected in parallel to the tester such that each said CODEC receives said seed, and wherein said block includes at least one CODEC, each CODEC including: