Patent ID: 6614448
Filing Date: 2003-09-02
Classification: G06T

Abstract:
A circuit comprising:a memory including a first storage circuit and a second storage circuit, wherein: the first storage circuit has a plurality of first storage output terminals coupled to a first storage output bus, the first storage output bus having a first number of lines; and the second storage circuit has a plurality of second storage output terminals coupled to a second storage output bus, the second storage output bus having a second number of lines, the second number being less than the first number; and a resolution enhancer having a first enhancer output bus and a second enhancer output bus, wherein each of the first enhancer output bus and the second enhancer output bus has the second number of most significant lines and a third number of least significant lines, the third number being the difference between the second number and the first number, and the resolution enhancer includes: a plurality of first enhancer lines, each first enhancer line being coupled to a line in the first enhancer output bus and to a line in the first storage output bus; and a supplementor having: a plurality of second enhancer lines, each second enhancer line being coupled to a least significant line in the second enhancer output bus and to a least significant line in the first storage output bus; and a plurality of third enhancer lines, each third enhancer line being coupled to a most significant line in the second enhancer output bus and to a most significant line in the second storage output bus.