Patent ID: 6121799
Filing Date: 2000-09-19
Classification: G01R,G06J

Abstract:
An interleaved digital peak detector comprising:a plurality of acquisition pipes coupled to receive an input signal, each acquisition pipe comprising:an analog-to-digital converter receiving and digitizing the input signal and a sampling clock signal with the sampling clock signal for each pipe being coupled through a delay circuit to selectively delay the sampling of the input signal for each acquisition pipe;a peak detector receiving the output from the analog-to-digital converter and accumulating maximum and minimum values of the digitized input signal;an acquisition circuit receiving an acquisition clock signal derived by decimating the sampling clock signal as a function of a decimation value for triggering a latch circuit that stores the accumulated maximum and minimum values from the peak detector; andmeans for comparing the accumulated maximum and minimum values from each of the acquisition circuits over an acquisition interval for generating a maximum and a minimum peak detector value over the acquisition interval for the plurality of acquisition pipes.