Patent ID: 6011722
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A process for changing the charge on the floating gate of a plurality of stacked-gate memory devices in a NOR array comprising:verifying whether a V.sub.TH of at least one device on a selected word line in an array of devices is above or below a target threshold voltage, wherein the at least one device is the selected device in an array of devices and wherein the devices other than the selected device in the array are the deselected devices, by applying, to an n-channel device, a V.sub.BS that is equal to or less than zero to the selected and deselected devices and a V.sub.CS that is less than or equal to zero to the deselected devices and wherein at least one of V.sub.BS and V.sub.CS is less than zero, and, to a p-channel device, a V.sub.BS that is equal to or greater than zero to the selected and deselected devices and a V.sub.CS that is greater than or equal to zero to the deselected devices and wherein at least one of V.sub.BS and V.sub.CS is greater than zero; andif the V.sub.TH of the device is less than or greater than the target threshold voltage, subjecting the selected device to conditions that change the charge on the floating gate.