Patent ID: 6561706
Filing Date: 2003-05-13
Classification: G03F

Abstract:
A system for analyzing a latent image exposed in a photo resist and for generating information to facilitate controlling a post exposure developing process in semiconductor manufacturing, comprising:an exposing system adapted to expose one or more patterns on one or more photo resist layers on a wafer; a developing system adapted to develop a photo resist; a developing driving system adapted to control the developing system; a post exposure baking system adapted to harden the photo resist; a baking driving system adapted to control the post exposure baking system; one or more light sources adapted to direct light to at least one portion of the wafer; one or more light collectors adapted to collect a light reflected from the at least one portion of the wafer; a signature system adapted to produce a signature from the light reflected from the at least one portion of the wafer; and a processor operatively coupled to the signature system, the developing system, and the post exposure baking system, the processor receiving one or more signatures from the signature system and the processor adapted to employ the one or more signatures to control the developing system and the post exposure baking system.