Patent ID: 6487653
Filing Date: 2002-11-26
Classification: G06F

Abstract:
A microprocessor configured to execute floating point instructions, the microprocessor comprising:a classification unit configured to receive floating point data from floating point load operations and classify the floating point data according to data type, wherein the classification unit is configured to assert a denormal control signal for floating point data that is denormal; and a conversion unit configured to receive the floating point data and convert the floating point data to a predetermined format, wherein the conversion unit is configured to convert normal floating point data to the predetermined format in a first number of clock cycles, wherein the conversion unit is configured to convert denormal floating point data to the predetermined format in a second number of clock cycles, wherein the first number of clock cycles is less than the second number of clock cycles; and a reissue buffer configured to temporarily store floating point instructions for at least one clock cycle, wherein the reissue buffer is configured to replay the stored floating point instructions in response to receiving the asserted denormal control signal; wherein in response to receiving the denormal floating point data, the conversion unit is further configured to convert normal floating point data and denormal floating point data using the second number of clock cycles until the conversion unit experiences an idle clock cycle.