Patent ID: 6262591
Filing Date: 2001-07-17
Classification: H04L

Abstract:
A CMOS terminator circuit for connection to a network carrying small logic level signals from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit, comprising:a terminator circuit (21) including a terminator reference circuit (30) generating logic `1` and logic `0` reference voltage levels and being coupled to a terminator input circuit (31) in said terminator circuit having a first and a second control device, and wherein said terminator circuit is coupled to a differential receiver (24), said terminator input circuit being coupled to said network input terminal (10) for connecting the network's first circuit to the network's second circuit, said terminator reference circuit (30) having back to back source coupled CMOS-SOI devices coupled to each other for a tuned center reference voltage node, with their bodies connected to upper and lower level power supplies for the reference circuit respectively,said reference circuit being tuned to a voltage level equal to the center of the incoming voltage swing between said logic `1` and `0` voltage levels of a reference circuit and coupled to one input of said differential receiver circuit (24) to provide to said differential receiver circuit a stable and well centered threshold voltage such that the terminator impedance matches its net impedance in its network, said differential receiver having receiver devices also having their bodies connected to upper and low level power supplies of the reference circuit and having another differential receiver input which is coupled to the network input terminal for connecting the network's first circuit to the network's second circuit.