Patent ID: 6507939
Filing Date: 2003-01-14
Classification: G06F

Abstract:
A method for reduction of net delays and insertion of buffers in a logic tree having nodes, a root, and a plurality of leaves, the method comprising the steps of:inserting a plurality of auxiliary nodes into the tree so that none of the nodes is a greater distance removed from an adjacent one of the nodes than a predetermined value, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffer chains for insertion into the net tree from a library set of buffers, for each node on the tree, determining a tradeoff function relating ramp time, departure time, and load at the node, for each node on the tree, removing combinations of the tradeoff function and the buffer chains, which when such buffer chains are inserted into the tradeoff function, produce a ramp time that exceeds a predetermined maximum allowable ramp time, for each node on the tree, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.