Patent ID: 6463576
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A method for designing an ASIC comprising the steps of:a first step of generating circuit data that includes a large-scale hardware macro made up of primitive macros; a second step of extracting, from said circuit data generated in said first step, wiring data of an external terminal of said large-scale hardware macro, an output of which is in an open state or an input of which is clamped; a third step of performing circuit tracing using said wiring data of said external terminal extracted in said second step; a fourth step of removing wiring data of a redundant primitive macro and redundant wiring data connected to said redundant primitive macros using said wiring data of said external terminal extracted in said second step, wherein said fourth step including a step of setting removal prohibition information within said library, so as to impart a limitation on a removal of wiring data of a redundant primitive macro and redundant wiring data connected to said redundant primitive macros; a fifth step of generating a temporary library in which a delay time within said macro is adjusted, based on removal results obtained in said fourth step; and a sixth step of performing layout and wiring, and of performing a delay simulation, using said temporary library generated in said fifth step.