Patent ID: 7256600
Filing Date: 2007-08-14
Classification: G01R

Abstract:
1. A semiconductor device tester, comprising: a PMU stage configured to provide a DC test signal, the DC test signal comprising one of plural test signals, at least two of the plural test signals having different current levels; a PE stage configured to produce an AC test signal; a driver circuit configured to provide, in a first mode, a version of the DC test signal in a case that the DC test signal is for producing a test signal having a higher current level than others of the plural test signals and, in a second mode, to provide a version of the AC test signal; and an output stage through which test signals pass on a path to a semiconductor device; wherein, in a case that the DC test signal is for producing a test signal having less than the higher current level, the DC test signal passes to the output stage through circuitry that bypasses the driver.