Patent ID: 6760392
Filing Date: 2004-07-06
Classification: H04L

Abstract:
A system comprising:a first device in a first clock domain, wherein said first clock domain has a first clock signal having a first clock rate; and a second device in a second clock domain, wherein said second clock domain has a second clock signal having a second clock rate; wherein the system is configured to perform clock skipping in transferring data from said first device to said second device; wherein said first device is configured to transmit an early response signal to said second device for a duration of k pulses of said first clock signal before transmitting said data; wherein said second device is configured to determine a number n, wherein n is the number of skipped pulses which will occur in said second clock domain prior to the occurrence of k valid pulses, and to receive said data k+n pulses of said second clock signal after receiving said early response signal; and wherein said second device includes a skip pattern generator configured to generate a pattern of valid and skipped pulses of said second clock signal.