Patent ID: 6767790
Filing Date: 2004-07-27
Classification: G11C,H01L

Abstract:
A method of writing of a nonvolatile semiconductor storage device, said nonvolatile semiconductor storage device comprising:a semiconductor substrate, at least the surface of which is of a first conductivity type; a plurality of floating gates and a plurality of access gates formed on an insulating film provided on the surface of said semiconductor substrate, said plurality of floating gates and said plurality of access gates being alternately formed adjacent to one another, with an insulating film sandwiched between each of said gates; a plurality of diffusion regions of a second conductivity type selectively formed in the surface of said semiconductor substrate, said plurality of diffusion regions each being formed under a corresponding one of said plurality of floating gates and a corresponding one of said plurality of access gates to extend thereacross; and a control gate formed on an insulating film provided on said plurality of floating gates and said plurality of access gates, wherein one memory transistor consists essentially of said control gate, a pair of adjacent ones of said plurality of diffusion regions, one of said plurality of floating gates which is formed on one of said pair of diffusion regions, and one of said plurality of access gates which is formed on the other one of said pair of diffusion regions, said method comprising the steps of: (a) setting said semiconductor substrate at a substrate potential; (b) setting said control gate at a first potential higher than said substrate potential; (c) setting said plurality of access gates at a second potential at which the surface of said semiconductor substrate under said plurality of access gates is not reversed to said second conductivity type; and (d) writing onto at least a pair of adjacent ones of said memory transistors under said control gate, in a first write mode, to set said one of said pair of diffusion regions in said one memory transistor at a third potential and in a second write mode, to set said one of said pair of diffusion regions at a fourth potential that is shifted from said third potential toward said first potential, wherein said first and third potentials include a potential at which electrons move from said one of said pair of diffusion regions to said one of said plurality of floating gates by a tunneling effect, and said first and fourth potentials include a potential at which substantially no electrons move from said one of said pair of diffusion regions to said one of said plurality of floating gates by the tunneling effect.