Patent ID: 6564284
Filing Date: 2003-05-13
Classification: G06F

Abstract:
A computer system, comprising:a processor; a memory operable to store data and having a plurality of banks; and a memory controller coupling the processor with the memory, the memory controller operable to initiate a first data transfer request directed to a first of the banks, to temporarily store a second data transfer request that is a page hit to the first bank, and to initiate a third data transfer request directed to a second of the banks prior to initiation of the second data transfer request, the memory controller including: a request queue operable to receive a plurality of memory access requests; a timing chain circuitry having a plurality of rank registers sequentially coupled between the request queue and the memory; and a page hit register coupled to the request queue and to at least some of the plurality of rank registers, the page hit register being operable to store a page hit write request in a write rank register based on a write latency of the memory, and being operable to store a page hit read request in a read rank register based on a read latency of the memory.