Patent ID: 7872503
Filing Date: 2011-01-18
Classification: H03K

Abstract:
1. A combinatorial logic circuit comprising: a first logic block coupled to a supply terminal via a first resistor means and via a second resistor means for receiving respective first and second currents; a second logic block coupled to the supply terminal via at least one of the first resistor means and the second resistor means for receiving at least one of respective third and fourth currents; a first output terminal coupled to the first block and to the first resistor means; a second output terminal coupled to the second logic block and to the second resistor means; and a first current source coupled to at least one of the first output terminal and/or second output terminal for providing a first supply current through the first resistor means which is substantially equal to a second supply current through the second resistor means, wherein each logic block comprises a first transistor coupled in parallel to a second transistor and a third transistor, each of the first, second and third transistors including first, second and control terminals, the first and second transistors being connected such that the first terminals of the first and second transistors are directly connected to each other and the second terminals of the first and second transistors are also directly connected to each other, the control terminals of the first and second transistors being used to receive logical signals, and the third transistor being controlled by a bias voltage applied to the control terminal of the third transistor.