Patent ID: 8558840
Filing Date: 2013-10-15
Classification: G09G

Abstract:
1. An integrated circuit device comprising: a memory controller that carries out a process of interfacing with an image memory that stores first image data; a read-modify-write circuit that rewrites the first image data stored in the image memory based on second image data and write enable signals, the read-modify-write circuit includes a first buffer that buffers the second image data; and a second buffer in which stream image data are input as one of the first image data and the second image data, the second buffer converting the format of each set of pixel data of the stream image data into a format of pixel data to be stored in the image memory, and storing the pixel data, the second buffer is formed from a second FIFO in which input data including a plurality of sets of pixel data are written as the stream image data, and that sequentially shifts the input data in series, when the input data includes pixel data at an end of a horizontal scanning line, the second FIFO shifts the input data until pixel data at a start of a next horizontal scanning line come to an end of the second FIFO, thereby cutting the stream image data at each horizontal scanning line, and when the number of bits of each pixel of the first image data is N (N is a natural number), the number of rewrite unit bits of the first image data is M (M is a natural number of M≧N), and the number of bits for which the memory controller can access the image memory at one time is L (L is a natural number of two or more that fulfills L>M), the read-modify-write circuit rewriting L bits of pixel data of the first image data corresponding to active write enable signals for every L/M bits (L and M are each a natural number multiple of N) of the write enable signals.