Patent ID: 8839178
Filing Date: 2014-09-16
Classification: G06F

Abstract:
1. A system for generating a clock tree network of an integrated circuit, the integrated circuit including a clock source for generating a clock signal and a plurality of clocked components, comprising: means for measuring a first duration of propagation of the clock signal to a first transmitting clocked component of the plurality of clocked components; means for measuring a second duration corresponding to the interval between initiating transmission of a data signal from the first transmitting clocked component and receipt of the data signal by a receiving clocked component, wherein the data signal transmission is initiated in response to receipt of the clock signal by the first transmitting clocked component; means for measuring a third duration of propagation of the clock signal to the receiving clocked component; means for comparing the third duration to the combined first and second durations; and means for optimizing the clock tree network based on a result of the comparison means, wherein optimizing the clock tree network comprises evaluating predetermined criteria for selection of a second transmitting clocked component having a slower data signal propagation path relative to the first transmitting clocked component, the second transmitting clocked component being selected from a library having a plurality of clocked components.