Patent ID: 6630405
Filing Date: 2003-10-07
Classification: H01L

Abstract:
A method of gate patterning, including the sequential steps of:providing a semiconductor structure having an upper silicon layer; said semiconductor structure having a gate conductor region; forming a first gate oxide layer over said semiconductor structure; forming a gate conductor layer on said first gate oxide layer; forming a patterned oxide mask and photoresist layer over said gate conductor layer within said gate conductor region leaving unmasked gate conductor layer portions and unmasked first gate oxide layer portions; conducting a oxygen implant within said unmasked gate conductor layer portions proximate said unmasked first gate oxide layer portions; removing said patterned photoresist mask; annealing the structure to form second gate oxide portions within said unmasked gate conductor layer portions over said unmasked first gate oxide layer portions; and using said second gate oxide portions as an etch stop, etching and removing said unmasked gate conductor layer portions to said second gate oxide portions forming a gate conductor within said gate conductor region.