Patent ID: 6259131
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A split-gate flash memory cell comprising:providing a semiconductor substrate having active and passive regions defined;a shallow trench isolation;a floating gate structure further comprising a first polysilicon layer, a silicon nitride layer and an oxide layer;said floating gate structure having oxidized side-walls, a poly tip and a partially etched nitride layer thereover;said etched nitride layer having a notched recess formed inwards from the outer edge of and contiguous with the underlying said floating gate having said poly-tip;said floating gate structure, including said notched recess and said poly-tip, covered with a high temperature oxide (HTO) layer;a control gate;oxide spacers;a self-aligned source line;source and drain regions; anda metal plug in a contact hole contacting said source region.