Patent ID: 6504747
Filing Date: 2003-01-07
Classification: G11C

Abstract:
An integrated memory, comprising:word lines, bit lines and plate line segments configured to define crossover points at which said word lines, bit lines, and plate line segments crossover, said bit lines combined to form columns; memory cells configured at said crossover points, each one of said memory cells including at least one storage capacitor and a selection transistor, said storage capacitor including a first electrode connected to one of said plate line segments, said storage capacitor including a second electrode connected to one of said bit lines by said selection transistor, said selection transistor including a control terminal connected to one of said word lines; column select lines for selecting said columns of said bit lines; a column decoder for driving said column select lines as a function of column addresses; a row decoder for driving said word lines as a function of word addresses; driver units for connecting said column select lines to said plate line segments, said driver units generating potentials on said plate line segments, said driver units generating said potentials with defined values in specific operating states as a function of a potential of an associated one of said column select lines and as a function of the word addresses.