Patent ID: 7839374
Filing Date: 2010-11-23
Classification: G09G,G11C

Abstract:
1. A liquid crystal display device comprising: a substrate, including a plurality of data lines, a plurality of gate lines for receiving gate signals, a pixel array comprising a first group of a plurality of pixels and a second group of a plurality of pixels that the first group of a plurality of pixels and the second group of a plurality of pixels are alternatively arranged, such that the pixel array is configured in a plurality of rows and a plurality of columns across the substrate; a first gate drive circuit including a first to an nth shift registers that output first gate signals; and a second gate drive circuit including a first to an nth shift registers that output a second gate signals, wherein a first pixel selected from the first group of a plurality of pixels and a second pixel selected from the second group of a plurality of pixels share one data line, and the first and second pixel are horizontally adjacent to each other, wherein the first gate drive circuit and the second gate drive circuit are arranged on the substrate and operate independently of one another, wherein the first and second gate drive output odd gate output signals and even gate output signals at time intervals of H/2 respectively to odd-numbered gate lines and even-numbered gate lines of the pixel array independently, and wherein each signal output by the first date drive circuit and the second drive gate circuit has a time duration of about one-half period, wherein each pixel included within the pixel array is connected to a switching element for applying a data signal thereto, a drain electrode of the switching element is connected to a data line, and a source electrode thereof is connected to each pixel electrode, where in the first gate drive circuit are applied a scan start signal, clock signals of two phases C1 and C1B, and the second gate drive circuit are applied a scan start signal, clock signals of two phases C2 and C2B, wherein the time interval between the scan start signal and the C1 signal is H/2, wherein the time interval between the C1 signal and the C1B signal is H, and the time interval between the scan start signal and the C2 signal is H, wherein the time interval between the C2 signal and the C2B signal is H, where in the C1, C1B, C2, C2B are inputted at time intervals of H/2 into the first and second gate drive circuits and respectively, which thereby generate gate output signals having a time interval of H/2, wherein the pair of pixels connected to the same data line are connected to different gate lines among pairs of gate lines, wherein the pair of pixels are concurrently driven for a period of H/2, wherein the odd-numbered pixels of the first line are driven according to the gate output signal of the first gate drive circuit, and the even-numbered pixels of the first line are driven for a period of H/2 according to the gate output signal from the second gate drive circuit a period of H/2 later, wherein the pair of pixels are concurrently driven for a period of H/2, then odd-numbered pixels of the first line are non driven and the even-numbered pixels are driven for other period of H/2.