Patent ID: 6376307
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method for fabricating NOR type memory cells of a non-volatile memory device, comprising the steps of:forming a floating gate insulating film, a floating gate electrode, a control gate insulating film, a control gate electrode, and an insulating film sequentially on each of memory cell regions of a semiconductor substrate defined by an isolation film; forming a source electrode and a drain electrode in portions of the semiconductor substrate exposed at both sides of the gate electrode, respectively; forming a first etching barrier film on a resulting structure; forming a first interlayer insulating film on the first etching barrier film in a planarized fashion; etching a desired portion of the first interlayer insulating film so as to form a first contact hole exposing the source and drain electrodes, respectively; removing portions of the first etching barrier film exposed due to the step of etching the desired portion of the first interlayer insulating film; forming a first conductive film in a planarized fashion on a resulting structure so as to bury the first contact hole; etching the first conductive film so as to form a source electrode line contacting the source electrode and a contact plug contacting the drain electrode; forming a second etching barrier film on a resulting structure; forming a second interlayer insulating film in a planarized fashion on the second etching barrier film; etching a desired portion of the second insulating film so as to form a second contact hole exposing the contact plug; and forming a bit line connected to the contact plug via the second contact hole on the second interlayer insulating film.