Patent ID: 7901994
Filing Date: 2011-03-08
Classification: H01L

Abstract:
1. A method of fabricating a transistor, the method comprising: providing a first Group III nitride layer on a substrate in a reactor; providing a second Group III nitride layer that is undoped or doped with an n-type dopant on the first Group III nitride layer in-situ in the reactor; providing an insulating layer directly on the second Group III nitride layer in-situ in the reactor; removing the substrate including the first Group III nitride layer, the second Group III nitride layer and the insulating layer from the reactor; patterning the insulating layer to form at least a first contact hole that exposes a first contact region of the second Group III nitride layer while leaving a portion of the insulating layer on the second Group III nitride layer; and providing a first contact on the first contact region of the second Group III nitride layer.