Patent ID: 6930019
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A MOS transistor formation method comprising the steps of: forming a gate oxide film and a gate electrode on a device region of a silicon substrate; forming a nitride film spacer on one side surface of the gate electrode; forming an interlayer dielectric layer on an upper surface of overall structure inclusive of the nitride film spacer; forming a landing plug contact hole by over-etching the interlayer dielectric layer and an active region of the silicon substrate; forming an oxide film on an upper surface of overall structure inclusive of the landing plug contact hole; forming a side wall oxide film spacer by selectively eliminating the oxide film so that the oxide film remains only on a side wall of the landing plug contact hole; forming a first landing plug pattern in a lower portion of the landing plug contact hole; eliminating exposed side wall oxide film spacer and etching inside of a first landing plug pattern, thereby forming an auxiliary groove which expands area of the landing plug contact hole; and forming a second landing plug pattern in the landing plug contact hole including the first landing plug pattern and the auxiliary groove.