Patent ID: 6441766
Filing Date: 2002-08-27
Classification: H03M

Abstract:
A charge integration algorithmic analog-to-digital converter for performing an analog to digital conversion to a signal voltage and a reset voltage by referencing a top reference, a bottom reference and a middle reference, the converter comprising an operational amplifier, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, wherein:in a correlated double sampling phase, the signal voltage is sampled and charged to the first capacitor, and then the reset voltage is sampled and the charge of the first capacitor is transferred to the second capacitor, so as to determine an output voltage and an output bit, based on the reset voltage, the signal voltage, and the top reference, by the operational amplifier using a ratio of the first capacitor to the second capacitor as a gain, the output voltage being held in the third and fourth capacitors; in a first operating cycle, the third capacitor charges the fourth capacitor whose charge is further transferred to the output voltage, so as to determine an output voltage and an output bit, based on the previous output voltage, middle reference, top reference and bottom reference, by the operational amplifier using a ratio of the third capacitor to the fourth capacitor as a gain, the output voltage being held in the first and second capacitors; and in a second operating cycle, the first capacitor charges the second capacitor whose charge is further transferred to the output voltage, so as to determine an output voltage and an output bit, based on the previous output voltage, middle reference, top reference and bottom reference, by the operational amplifier using a ratio of the first capacitor to the second capacitor as a gain, the output voltage being held in the third and fourth capacitors, the first and second operating cycles being alternately and cyclically executed, wherein, in the correlated double sampling phase, the output voltage is determined by VO=VX=âˆ’(C1/C2)*(VRâˆ’VS)+VRT, where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, VR is the reset voltage, VS is the signal voltage, and VRT is the top reference.