Patent ID: 7085797
Filing Date: 2006-08-01
Classification: G06F

Abstract:
1. An addition circuit for producing a sum of four redundant binary numbers, wherein each number includes an operand field and a sparse carry-save field, comprising; a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom; a 4:3 compression adder for receiving each of the sparse carry-save fields of the four redundant binary numbers, and producing a second sum field therefrom; a 3:2 compression adder for receiving the first sum field, the first carry field and the second sum field, and producing a third sum field and a second carry field therefrom; wherein the third sum field and the second carry field are the sum of the four redundant binary numbers.