Patent ID: 7791919
Filing Date: 2010-09-07
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device including a plurality of memory chips each using a resistance-change memory element as a memory cell, and having a pad part having a through silicon via structure (TSV) including a chip top electrode of a chip surface and a chip bottom electrode of a chip backside, comprising: the memory chips each including: a first memory position detection pad provided at the pad part; a second memory position detection pad provided at the pad part; at least one variable resistance element provided corresponding to the first memory position detection pad, the variable resistance element having one terminal connected to the chip top electrode of the first memory position detection pad, and the other terminal connected to the chip bottom electrode of the first memory position detection pad; and a comparator having one input terminal connected with the chip top electrode of the first memory position detection pad, and the other input terminal supplied with a chip position detection signal, the memory chips being configured so that the first and second memory position detection pads are connected via the chip top and bottom electrodes facing each other, of the vertically stacked memory chips, the chip bottom electrode of the first memory position detection pad and the chip bottom electrode of the second memory position detection pad provided on the lowermost memory chip being connected, the memory chips each controlling the variable resistance element, and in a state that the first memory position detection pad has a higher resistance than the second memory position detection pad, comparing a voltage applied to the first memory position detection pad with the chip position detection signal using the comparator when a voltage is applied between the first and second memory position detection pads provided on the uppermost layer memory chip, and thereby, detecting a stacked position of the memory chip in the package and recognizing a chip address in accordance with the stacked position from the comparison result.