Patent ID: 6040609
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A process for integrating in a same MOS technology devices with different threshold voltages, comprising:simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density per unit area; andselectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions, and said two MOS devices consequently have respective threshold voltages that depend on the corner density per unit area and on the aperture angles of the corner of the respective gate electrodes.