Patent ID: 6541359
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A method of fabricating an integrated circuit on a laminate comprising a gate dielectric layer between a gate electrode layer and a substrate, said method comprising the steps of:a) doping a first portion of said gate electrode layer with a first dopant material, said first portion substantially corresponding to a location at which a gate of said integrated circuit is to be formed; b) doping a second portion of said gate electrode layer with a second dopant material, wherein more of said gate electrode layer is doped with said second dopant material than with said first dopant material and wherein said gate electrode layer doped with said second dopant material is etched away at a faster rate than said gate electrode layer doped with said first dopant material; c) applying a gate mask over said gate electrode layer; and d) removing unmasked portions of said gate electrode layer using an etchant, said etchant inducing a detectable endpoint signal upon reaching said gate dielectric layer.