Patent ID: 6211024
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method of forming a source/drain region, in a semiconductor substrate, comprising the steps of:providing a gate structure, on an underlying gate insulator layer, on said semiconductor substrate;providing a lightly doped source/drain region, in a region of said semiconductor substrate, not covered by said gate structure;providing insulator spacers on sides of said gate structure;performing a first ion implantation procedure, creating a first ion implant region, with a first concentration and first energy of ion implanted species, located in a first region of said semiconductor substrate, not covered by said gate structure, or by said insulator spacers;performing a second ion implantation procedure, creating a second ion implant region, with a second concentration and second energy of ion implanted species, located in a second region of said semiconductor substrate, not covered by said gate structure, or by said insulator spacers, wherein the second concentration and the second energy are lower than said first concentration and said first energy respectively;performing a third ion implantation procedure, creating a third ion implant region, with a third concentration and third energy of ion implanted species, located in a third region of said semiconductor substrate, not covered by said gate structure, or by said insulator spacers, wherein the third concentration and the third energy are lower than said second concentration and said second energy respectively; andperforming an anneal procedure, activating, and distributing ion implant species of said first ion implant region, of said second ion implant region, and of said third ion implant region, forming said source/drain region.