Patent ID: 7207014
Filing Date: 2007-04-17
Classification: G06F,Y02D

Abstract:
1. A method for modular design of a computer system-on-a-chip comprising steps of: (a) selecting a modular architecture frame from a frame library; (b) configuring said architecture frame to have a new module wherein a clock rate is adjusted in accordance with the task performance factors associated with a task type so that a task completes within a desired time socket, the rest of module sockets being modules from the library; (c) configuring memory and I/O system decode map on host bridge unit; (d) configuring said new module modular bus architecture interface (MBA I/F) logic, as one of a master or slave type, and as one of a single-edge or dual-edge type so as to allow for data transfer on a single edge or both edges of a clock cycle presented to said MBA I/F; (e) if the new module is a master module then configuring new module task performance factors for managing the power consumed by said new module; and (f) configuring new module register I/O space and memory space.