Patent ID: 7924078
Filing Date: 2011-04-12
Classification: H03K

Abstract:
1. Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item and including a path of nMos transistors connected in series between the pre-charge means and a ground of the circuit, making it possible to discharge the intermediate node for the duration of said time window, wherein the delay means include means for temporally adjusting the duration of the time window to the time for discharging the intermediate node through said discharge means, wherein said time adjustment means are integrated at the level of an inverter of the inverter chain, in the form of a path of nMos transistors replicating the transistor path of the discharge means, connected in series with a pMos transistor of said inverter.