Patent ID: 6098144
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A data processor comprising:a. a central processing unit;b. an interrupt handler;c. multiple interrupt sources;d. at least one daisy chain for coupling the multiple interrupt sources to the interrupt handler, for enabling the multiple interrupt sources and the interrupt handler to exchange interrupt request and acknowledge signals; ande. a bus coupling the central processing unit, the interrupt handler, and the multiple interrupt sources,wherein,the interrupt handler is adapted to communicate a read vector command to all the multiple interrupt sources via the at least one daisy chain;at least one of the multiple interrupt sources is adapted to supply at least a respective portion of an interrupt address vector to the interrupt handler, in response to the read vector command;the interrupt handler is further adapted to selectively communicate the interrupt address vector to the CPU, including at least the respective portion of the interrupt address vector.