Patent ID: 6614066
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A ferroelectric transistor, comprising:a substrate having a main surface; a first source-drain region, a channel region, and a second source-drain region adjoining said main surface of said semiconductor substrate, with said channel region arranged between said first and second source-drain regions, said channel region having a first area adjacent said second source-drain-region and a second area adjacent said first source-drain-region; a dielectric layer covering at least said channel region and overlapping said first source-drain region, said dielectric layer having a first thickness above said first area of said channel region, having a second thickness above said second area of said channel region, and having a third thickness above said first source-drain-region, said first thickness being less than said third thickness and said third thickness being less than said second thickness; a ferroelectric layer disposed on said dielectric layer and covering at least a part of said first source-drain region adjacent said channel region; a first polarization electrode; a second polarization electrode and a gate electrode adjoining one another and forming a common electrode, said second polarization electrode disposed above said second area and said gate electrode disposed above said first area of said channel region; said first polarization electrode and said common electrode disposed on said dielectric layer, with said ferroelectric layer arranged between said first and second polarization electrodes; and said third thickness of said dielectric layer being dimensioned such that a remanent polarization of said ferroelectric layer, aligned parallel to said main surface of said substrate, produces compensation charges in said second area of said channel region.