Patent ID: 8871312
Filing Date: 2014-10-28
Classification: C04B,Y10T

Abstract:
1. A method of reducing plasma arcing within a semiconductor processing chamber while simultaneously providing plasma erosion resistance of plasma processing components to fluorine-containing plasmas, said method comprising: forming at least one surface which is exposed said plasma from a ceramic-comprising material which comprises at least one solid solution, wherein said solid solution is formed from more than two precursor oxides, where a first precursor oxide is yttrium oxide, present at a concentration ranging from about 55 molar % to about 80 molar %, a second precursor oxide is zirconium oxide, present over a range from about 5 molar about % to about 25 molar %, and an additional precursor oxide, hafnium oxide, is present over a range from about 5 molar % up to about 25 molar %, so that an erosion rate at said surface of said article when normalized with respect to a ceramic surface formed from yttrium oxide is about 1 and an electrical resistivity at said surface of said article is in the range of about 10 7 to 10 15 Ω·cm at a temperature ranging from about 350° C. to room temperature, respectively.