Patent ID: 7274047
Filing Date: 2007-09-25
Classification: H01L

Abstract:
1. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, the ESD protection circuit comprising: a silicon controlled rectifier (SCR) having at least one first type high dopant region formed in a second type low dopant region coupled to a first reference potential of the protected circuitry and at least one second type high dopant region coupled to a second reference potential of said IC; at least one trigger tap disposed outside of a surface area between the first type high dopant region and the second type high dopant region, said trigger tap formed in said second type low dopant region; and a MOS transistor located outside of the surface area between the first type high dopant region and the second type high dopant region of the SCR, said transistor adapted for injecting a trigger current via said trigger tap into at least one gate of said SCR.