Patent ID: 7843734
Filing Date: 2010-11-30
Classification: G11C

Abstract:
1. A non-volatile memory device comprising: a memory cell array including a plurality of memory banks, the plurality of memory banks including first and second memory banks; an input buffer unit that receives external address signals, first input data and second input data from an external device; a first data handling unit that receives the first input data from the input buffer; a second data handling unit that receives the second input data from the input buffer; a first page buffer unit that receives the first input data transmitted from the first data handling unit and transmits the first input data to the first memory bank; and a second page buffer unit that receives the second input data transmitted from the second data handling unit and transmits the second input data to the second memory bank, wherein while the second data handling unit latches the second input data, the first data handling unit transfers the first input data to the first page buffer unit, and while the first data handling unit latches the first input data, the second data handling unit transfers the second input data to the second page buffer unit.