Patent ID: 8145831
Filing Date: 2012-03-27
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a nonvolatile semiconductor memory; a memory interface coupled to the nonvolatile semiconductor memory; a host interface configured to receive a mode change command and at least one of a logical address and a physical address of the nonvolatile flash memory; a ROM (Read Only Memory) storing firmware configured to control the memory system; a RAM (Random Access Memory) configured to store at least one part of the firmware and a logical to physical address translation table; a buffer memory configured to store data transferred between the host interface and the memory interface; an access path setting circuit configured to couple the host interface with the memory interface through the buffer memory in a first mode, and directly couple the host interface with the memory interface in a second mode; and a processor configured to control the access path setting circuit, and switch the first mode to the second mode or the second mode to the first mode according to the mode change command, wherein in the first mode, the processor translates the logical address into the physical address according to the address translation table, and transfers data between the host interface and the memory interface through the buffer memory, and in the second mode, the physical address received by the host interface is supplied to the memory interface, and data is transferred between the host interface and the memory interface without passing through the buffer memory.