Patent ID: 8402398
Filing Date: 2013-03-19
Classification: G03F

Abstract:
1. A method, in a data processing system, for reducing delay variation in metal wires, the method comprising: receiving a design comprising a plurality of metal wires; performing retargeting on the design to form target shapes based on one or more retargeting rules; performing resolution enhancement on the target shapes to form one or more corrected images; performing lithographic simulation on the one or more corrected images to form a simulated design; determining whether electrical properties of the simulated design meet predefined specifications; and responsive to the electrical properties of the simulated design not meeting the predefined specifications, modifying the one or more retargeting rules based on the electrical properties of the simulated design, wherein performing resolution enhancement comprises: performing decomposition on the target shapes into two separate components for different exposures for double exposure lithography; and performing optical proximity correction on the two components to generate two masks for the different exposures.