Patent ID: 9147472
Filing Date: 2015-09-29
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array that stores data; and a control circuit that controls write and read of data to/from the memory cell array, the memory cell array including a plurality of memory cell layers that are stacked, each memory cell layer comprising a plurality of memory cells being arranged and formed on a semiconductor layer, each memory cell comprising: a channel, a source, and a drain that are formed in the semiconductor layer; a gate insulating layer formed on the channel; a charge accumulation layer formed on the gate insulating layer; an inter-layer insulating layer formed on the charge accumulation layer; and a control gate formed on the inter-layer insulating layer, and adjacent memory cells being connected in series sharing each other's source and drain to form a plurality of NAND strings in each memory cell layer, the plurality of memory cell layers including: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon, the control circuit, when writing data in the memory cell, performing a write operation that repeats a write cycle until the data is written in the memory cell, the write cycle applying a write voltage between the semiconductor layer and the control gate and performing a verify read that confirms whether the data has been written in the memory cell or not, the write voltage being set to a write start voltage in the write cycle immediately after start of the write operation, and in a second or later time of the write cycle after start of the write operation, being set to a voltage that is the write voltage in the write cycle one previous increased by an amount of a step voltage portion, and when controlling write of data to a memory cell belonging to the first memory cell layer, the step voltage portion being a first step voltage, and when controlling write of data to a memory cell belonging to the second memory cell layer, the step voltage portion being a second step voltage which is smaller than the first step voltage.