Patent ID: 9029263
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: providing a layer of material for linear structures; forming a plurality of mandrels over the layer of material for the linear structures, the mandrels having pitch distances which are twice as long as desired pitch distances of the linear structures; shortening a first set of mandrels of the plurality of the mandrels in an area for a first plurality of the linear structures, so that a second set of mandrels of the plurality of the mandrels in an area for a second plurality of the linear structures are not substantially shortened; forming a layer of spacer material conformally over the first set of the mandrels, the second set of the mandrels, and the layer of material for the linear structures; anisotropically etching back the layer of spacer material to form a first plurality of spacers on the first set of the mandrels in the area for the first plurality of the linear structures and form a second plurality of spacers on the second set of the mandrels in the area for the second plurality of the linear structures, so that a horizontal thickness of the first plurality of spacers is less than a horizontal thickness of the second plurality of spacers; removing the mandrels, leaving the first plurality of spacers and the second plurality of spacers in place to form a spacer-based etch mask; and etching the layer of material for the linear structures using the spacer-based etch mask to form the linear structures including the first plurality of the linear structures and the second plurality of the linear structures, wherein a width of the first plurality of linear structures is less than a width of the second plurality of linear structures.