Patent ID: 8566528
Filing Date: 2013-10-22
Classification: G06F

Abstract:
1. An apparatus comprising: a cache; a write buffer coupled to the cache and configured to buffer write operations that have previously updated the cache, wherein the write buffer comprises a plurality of entries, each entry configured to store combined write operations on a cache block granularity; and a control circuit coupled to the write buffer, wherein the control circuit is configured to cause the write buffer to transmit the combined write operations from one or more entries of the plurality of entries to a next level of memory below the cache responsive to one or more flush metrics applied by the control circuit and responsive to a fullness of the write buffer, and wherein the control circuit is configured to dynamically modify the one or more flush metrics responsive to activity in the write buffer, wherein dynamically modifying the one or more flush metrics causes transmission of the combined write operations from the write buffer to the next level of memory at different times than would occur responsive to unmodified flush metrics.