Patent ID: 6574746
Filing Date: 2003-06-03
Classification: G06F

Abstract:
A computer system comprising:a central processing unit (CPU); a memory controller coupled to said CPU and a memory bus, said memory controller including an error correction subsystem, said error correction subsystem configured to generate a plurality of check words corresponding to a plurality of data blocks; a memory module coupled to said memory bus including a plurality of memory chips for storing said plurality of check words and said plurality of data blocks, wherein each of said plurality of memory chips includes an array of memory cells, and wherein each check bit forming a given check word is stored at a vertically, horizontally and diagonally non-adjacent memory cell of said plurality of memory chips with respect to every of the check bit of said given check word; whereby no two check bits of any one of said plurality of check words are stored at physically adjacent memory cells of any array of said plurality of memory chips.