Patent ID: 6185726
Filing Date: 2001-02-06
Classification: G06F

Abstract:
A system for creating an electrical circuit design, comprising:a verification manager configured to verify said electrical circuit design, wherein said verification manager corrects at least one electrical circuit design defect, generates new design code as a result of the correction, simulates operation of said electrical circuit design, and performs a plurality of regression tests on said electrical circuit design, wherein said plurality of regression tests are comprised of a plurality of regression checkpoints that check a regression log for an error indication, update a design defect report, update a test vector matrix, check whether at least one source code is stored in a memory, and check whether a regression test was passed;a synthesis manager configured to synthesize said electrical circuit design, wherein said synthesis manager performs a synthesis procedure on said electrical circuit design, performs at least one timing test, modifies at least one constraint script when said electrical circuit design fails a timing test, and generates a first net list for said electrical circuit design, wherein said at least one timing test is comprised of a plurality of timing checkpoints that check whether at least one source code and at least one script are stored in a memory, check a timing log and at least one warning indicator for at least one error indication, check said electrical circuit design for unconnected points, check timing for said electrical circuit design, check at least one fanout parameter for said electrical circuit design, and check at least one clock timing, at least one reset buffer, and at least one fanout buffer;a backend manager configured to implement said electrical circuit design, wherein said backend manager creates a layout for said electrical circuit design, generates a second net list, generates an estimated standard delay format annotated to said second net list, generates an actual standard delay format, and performs a final regression test utilizing said actual standard delay format; anda processor, coupled to said system, to control said verification manager, said synthesis manager, and said backend manager and create said electrical circuit design.