Patent ID: 6303953
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A DRAM memory cell capacitor, comprising:a hemispherically-grained container-shaped bottom electrode in direct contact with an active area of a semiconductor substrate, said bottom electrode having a sidewall which, except for said hemispherical grain, has a substantially uniform thickness throughout the region;gate electrodes on each side of the active area of the semiconductor substrate, the gate electrodes having side spacers, one of which spacers on each electrode is covered by the hemispherically-grained electrode, another of which spacers on each electrode is covered by an etch stop layer that extends also over a portion of the semiconductor substrate, the bottom electrode sidewall extending vertically above the gate electrode from a junction with the etch stop layer, the bottom electrode defining a container for the capacitor;a cell dielectric overlying and in direct contact with the bottom electrode and conforming to inside and outside surfaces of the bottom electrode, the cell dielectric extending over the etch stop layer; anda top electrode overlying and in direct contact with the cell dielectric and adjacent to inside and outside surfaces of the bottom electrode.