Patent ID: 6593645
Filing Date: 2003-07-15
Classification: H01L

Abstract:
A three-dimensional system-on-chip structure, comprising:a plurality of chips stacked on top of each other, each of the chips having a periphery circuitry region and a plurality of contact pads disposed in each of the periphery circuitry regions; and a plurality of plugs respectively disposed in the periphery circuitry regions of the chips, and passing through the corresponding chips and connecting the contact pads of the corresponding chips so that the corresponding chips are electrically connected to each other, wherein two of the chips adjacent to each other are electrically connected through the plugs and the contact pads, wherein at least one plug that electrically connects the two adjacent chips, including an underlying chip and an overlying chip stacked on the underlying chip, penetrates the corresponding contact pad on the overlying chip and the overlying chip; and by means of the plugs and the contact pads two of the chips which are not adjacent to each other are electrically connected as well.