Patent ID: 8331159
Filing Date: 2012-12-11
Classification: G11C

Abstract:
1. A discharge circuit for a floating gate type MOS memory cell transistor having a source, a drain and a control gate connected to a word line, the floating gate type MOS memory cell transistor being disposed in a memory array region of a nonvolatile semiconductor memory device, the memory cell region being formed in P-well, the P-well being formed in an N-well, and the N-well being formed in a P-type semiconductor substrate, the discharge circuit comprising: a word line discharge circuit including a series connection of a first constant current transistor, a first switching transistor, and a second switching transistor connected between a first power supply voltage and the word line; a bulk discharge circuit including a series connection of a second constant current transistor and a third switching transistor connected between and a second power supply voltage and the P-well, wherein each one of the first constant transistor, the second constant transistor, the first switching transistor, the second switching transistor, and the third switching transistor are simultaneously turned ON during at least a portion of a discharge operation.