Patent ID: 6806760
Filing Date: 2004-10-19
Classification: H02M,H03K

Abstract:
A voltage booster circuit, comprising:first and second capacitors; a switch circuit coupled to the first and second capacitors and operative to apply a power supply across the first and second capacitors in series responsive to a first signal to thereby charge the first and second capacitors and to couple the first and second capacitors in parallel between an output terminal and a power supply node of the power supply responsive to deassertion of the first signal and assertion of a second signal to thereby boost a voltage at the output terminal; and a third capacitor having a first terminal configured to receive the first signal; wherein the first capacitor has a first terminal configured to receive the second signal; and wherein the switch circuit comprises: a first transistor having a current path that is coupled between a second terminal of the first capacitor and a first terminal of the second capacitor and that is controlled responsive to the first signal; a second transistor having a current path that is coupled between the second terminal of the first capacitor and the output terminal and that is controlled responsive to the second signal; a third transistor having a current path that is coupled between a second terminal of the second capacitor and the output terminal and that is controlled responsive to the second signal; a fourth transistor having a current path that is coupled between the second terminal of the second capacitor and the power supply node and that is controlled responsive to the first signal; a fifth transistor having a current path that is coupled between a second terminal of the third capacitor and the power supply node and that is controlled responsive to a voltage at the second terminal of the first capacitor; and a sixth transistor having a current path that is coupled between the first terminal of the second capacitor and the power supply node and that is controlled responsive to a third signal that is a logical complement of the second signal.