Patent ID: 6027969
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method of fabricating a stacked capacitor structure for a DRAM device, comprising the steps of:providing a transfer gate transistor, on a semiconductor substrate, comprised of a polysilicon gate structure, on a gate insulator layer, with a source/drain region in said semiconductor substrate, in a region of said semiconductor substrate, not covered by said polysilicon gate structure;depositing a composite insulator layer;depositing a first insulator layer;patterning of said first insulator layer to form insulator mesas, leaving a thinned first insulator layer remaining between said insulator mesas;depositing a first polysilicon layer;depositing a second insulator layer;forming a storage node opening, between said insulator mesas, in said second insulator layer, in said first polysilicon layer, in said thinned first insulator layer, and in said composite insulator layer, exposing said source/drain region;depositing a second polysilicon layer on said second insulator layer, and on exposed sides of said storage node opening, with said second polysilicon layer contacting an edge of said first polysilicon layer, exposed on the sides of said storage node opening;depositing a third insulator layer on said second polysilicon layer, completely filling said storage node opening;planarizing said third insulator layer, exposing a horizontal portion of said second polysilicon layer, in a region in which said second polysilicon layer overlays a top surface of said insulator mesas;removing exposed, horizontal portion of said second polysilicon layer, exposing a horizontal portion of underlying, said second insulator layer, and creating a first polysilicon branch, comprised of a segment of said second polysilicon layer, on the sides of said storage node opening, contacting the edge of said first polysilicon layer, exposed on the sides of said storage node opening;removing exposed, horizontal portion of said second insulator layer, exposing a horizontal portion of said first polysilicon layer, in a region in which said first polysilicon layer directly overlays the top surface of said insulator mesas;removing exposed, horizontal portion of said first polysilicon layer, creating a second polysilicon branch, and forming said storage node electrode comprised of said first polysilicon branch, contacting said second polysilicon branch, on the sides of said storage node opening;performing a wet etch procedure, comprised of removing said third insulator layer, removing insulator mesas, removing a portion of said second insulator layer, leaving a segment of said second insulator layer between said first polysilicon branch and said second polysilicon branch, and removing a portion of said thinned first insulator layer, leaving a segment of said thinned first insulator layer between said second polysilicon branch and said composite insulator layer;forming a capacitor dielectric layer on exposed surfaces of said first polysilicon branch, and on exposed surfaces of said second polysilicon branch; andforming a capacitor plate electrode, on said capacitor dielectric layer.