Patent ID: 6171896
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit device comprising:providing a pad oxide layer over the surface of a semiconductor substrate;depositing a nitride layer overlying said pad oxide layer;etching a plurality of isolation trenches through said nitride layer and pad oxide layer into said semiconductor substrate wherein there is at least one first region having a wide nitride area between two of said isolation trenches and at least one second region having a narrow nitride area between another two of said isolation trenches;depositing a high density plasma oxide layer over said nitride layer and within said isolation trenches wherein said high density plasma oxide layer fills said isolation trenches and wherein said high density plasma oxide layer has a first thickness in said first region over said wide nitride area and a second thickness in said second region over said narrow nitride area wherein said first thickness is larger than said second thickness;forming a photoresist mask over said high density plasma oxide layer and exposing said substrate to actinic light wherein a central portion of said first region is exposed;etching away said high density plasma oxide layer within said central portion of said first region wherein said central portion is about 80% of the width of said first region thereby leaving only said second thickness of said high density plasma oxide layer to be planarized;polishing away said high density plasma oxide layer remaining wherein said substrate is planarized; and completing the fabrication of said integrated circuit device.