Patent ID: 8994586
Filing Date: 2015-03-31
Classification: G01S,H03F

Abstract:
1. An apparatus for detecting a target in near field, comprising: a transmitting and receiving antenna unit; a radio frequency (RF) transceiver configured to both up convert and down convert and transmit a transmitting signal of a frequency modulated continuous wave (FMCW) generated by using a direct digital frequency synthesis scheme to a target through the antenna unit and perform time delay processing on a signal received by being reflected from the target as much as a preset time to provide a beat frequency offset; an analog-to-digital (A/D) converter configured to convert the transmitted signal from the RF transceiver and the received signal which is time delayed into digital information; a fast Fourier transform (FFT) processor configured to perform fast Fourier transform on the converted digital information; and a digital signal processing (DSP) unit configured to extract a range or a velocity of the target using the fast Fourier transformed information, wherein a path for the up conversion is provided with a power amplifier to amplify the transmitting signal and a first local signal amplifier to amplify a local oscillation signal and provide the amplified local oscillation signal to an up frequency mixer, a path for the down conversion is provided with a second local signal amplifier to provide the amplified local oscillation signal to a down frequency mixer, and a reverse isolation apparatus including the first and second local signal amplifiers is used so that a leakage noise signal inside the RF transceiver appearing due to a mismatch of a plurality of TX antennas may be minimized, and the path for the down conversion is further provided with a variable amplifier to compensate for a gain change depending on a temperature of a receiving terminal, and wherein the RF transceiver comprises: a voltage controlled oscillator phase locked loop configured to perform phase locking by comparing a feed-backed voltage controlled oscillator signal with an input signal from a direct digital frequency synthesizer (DDFS); a local oscillator phase locked loop configured separately to perform phase locking by comparing a reference clock signal and a feed-backed local oscillator signal; and a multiplier configured to multiply a signal from the local oscillator phase locked loop.