Patent ID: 6577014
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having a chip-mounting surface provided with a plurality of contact pads and a plurality of first conductive bumps formed respectively on said contact pads; a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads and a plurality of second conductive bumps formed respectively on said bonding pads, said semiconductor chip being mounted on said substrate to confine therebetween a gap, said second conductive bumps being respectively registered with and being bonded to said first conductive bumps, said second conductive bumps each including an adhesive layer that covers a central area of a respective one of said bond pads, a ball body that is laid on and that is bonded to said adhesive layer, and a conductive layer that encapsulates and that is bonded to said ball body and said adhesive layer and that covers a remaining area of the respective one of said bonding pads around said central area, said ball body having a lower half with a lower hemisphere surface that curves upwardly from an upper surface of said adhesive layer and that cooperates with said upper surface of said adhesive layer to define a groove therebetween, said conductive layer filling said groove; a plurality of spaced apart dielectric supporting pads disposed in said gap at positions offset from said first and second bumps, said supporting pads interconnected said chip-mounting surface of said substrate and said pad-mounting surface of said semiconductor chip; and an insulating layer that fills in said gap and that encapsulates said supporting pads and said first and second conductive bumps.