Patent ID: 8618665
Filing Date: 2013-12-31
Classification: G03F,G11C,H01L

Abstract:
1. A semiconductor device having a pattern layout comprising: a first power supply line which extends in one direction and to which a first voltage is supplied; second and third power supply lines which extend in the one direction and are arranged to sandwich the first power supply line therebetween and to which a second voltage is supplied; a first signal line which is arranged between the first power supply line and the second power supply line and to which data read from memory cells is transmitted; a second signal line which is arranged between the first power supply line and the third power supply line and to which data read from the memory cells is transmitted; a first contact pad which is connected to the second power supply line and electrically connected to an upper interconnect line arranged on the second power supply line; and a second contact pad which is connected to the third power supply line and electrically connected to an upper interconnect line arranged on the third power supply line.