Patent ID: 6359301
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A semiconductor device, comprising:a bit line connected to a transistor formed on a semiconductor layer and an electrode of a storage node of a capacitor are stacked above said transistor via an inter-layer insulating layer, a first connecting plug for bit contact and a second connecting plug for storage node contact buried in a first inter-layer insulating layer covering said transistor and projecting from said transistor, said bit line being buried in a second inter-layer insulating layer formed on said first inter-layer insulating layer and connected on said first connecting plug, and said electrode of the storage node being partially buried in said second inter-layer insulating layer, connected on said second connecting plug, and projecting above said second inter-layer insulating layer, wherein: a groove for a storage node is formed in said second inter-layer insulating layer and opens over said second connecting plug, and said electrode of the storage node comprises: a conductive side wall surrounding said groove for the storage node, projecting from said second inter-layer insulating layer, and shaped like a frame when viewed from the top, and a conductive layer extending from the inner face of said conductive said wall to the inside of said groove for the storage node and electrically connecting said conductive side wall with said second connecting plug.