Patent ID: 6178113
Filing Date: 2001-01-23
Classification: G11C,H01L

Abstract:
A memory cell comprising:a word line;first and second digit lines;a transistor comprising a control gate region connected to said word line, active doped regions respectively connected to said first and second digit lines, and at least first and second floating gate regions located beneath said control gate region;at least one of said floating gate regions being capacitively coupled to a respective active doped region through a dielectric region located below said at least one floating gate region and through a dielectric region located on a sidewall of said at least one floating gate region; andan electrically conductive material extending from at least a first one of said active doped regions to a position adjacent to said at least one floating gate region such that said electrically conductive material is coupled to said dielectric region located on a sidewall of said at least one floating gate region.