Patent ID: 8713298
Filing Date: 2014-04-29
Classification: G06F,Y02D

Abstract:
1. A processing system comprising: at least one processor coupled to a bus; at least one memory controller coupled to the bus; at least one primary bus bridge coupled to the bus; wherein the memory controller is coupled to at least one memory bus and the primary bus bridge is coupled to at least one peripheral bus; wherein at least one of the processor, memory controller or primary bus bridge comprises a bus inversion circuit further comprising: an advantage function circuit, adapted to input bits to be transmitted over a bus, the advantage function circuit adapted to calculate an advantage of inversion and an advantage of non-inversion for each input bit and being adapted to calculate an advantage of inversion and an advantage of non-inversion for at least one inversion bit to be transmitted over the bus; and a majority voter circuit for determining whether a plurality of bits to be transmitted over a bus should be inverted before being transmitted based on advantages received from the advantage function circuit; wherein the majority voter circuit provides two outputs, a first output corresponding to advantages of inversion and a second output corresponding to advantages of non-inversion.