Patent ID: 8943447
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. A machine-implemented method for deriving an Register Transfer Language (RTL) representation of a logic circuit for performing a sum of addends operation with faithful rounding, comprising: a) determining, in a computing system, a number of bits to discard from a result of the sum of addends to produce a faithfully rounded result; b) determining, in the computing system, a value of bits which may be discarded prior to performing the sum of addends operation and a constant to include in the sum of addends operation; c) determining, in the computing system, how many least significant whole columns of bits may be discarded from the sum of addends operation; d) discarding, in the computing system, those said columns; e) determining, in the computing system, how many bits of a next least significant column can be discarded from the sum of addends operation; f) discarding, in the computing system, those said bits from said next least significant column; and g) deriving, in the computing system, an RTL representation of the sum of addends operation with said truncated columns and bits, and including said constant.