Patent ID: 8379448
Filing Date: 2013-02-19
Classification: G11C

Abstract:
1. A memory device comprising: a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells electrically coupled to the bit line, the plurality of columns comprising: wherein the memory device is configured to perform an n-way interleaved read scheme when the number of defective regular columns in each of the regular interleave groups is not greater than the number of redundant columns in its corresponding redundant interleave group, wherein n equals the number of regular interleaved groups, and wherein the memory device is configured to perform an m-way interleaved read scheme when the number of defective regular columns in any of the regular interleave groups is greater than the number of redundant columns in its corresponding redundant interleave group, wherein m is less than the number of regular interleaved groups.