Patent ID: 8433322
Filing Date: 2013-04-30
Classification: H04B,H04J,H04W

Abstract:
1. A processor for a base station control unit, the base station control unit being associated with a plurality of antennas, the processor comprising: a first interface for receiving a plurality of processing streams, each stream being suitable for generating signals for at least one user in a plurality of users, wherein a processing stream of the plurality of processing streams can generate the signals for any user in the plurality of users and for transmission by any antenna in the plurality of antennas; a code memory for storing a code block, the code block comprising a first set of codes having a corresponding first length; and a processing unit for retrieving the code block from the code memory, and for forming a second set of codes having a corresponding second length by generating a first square grid comprising a plurality of copies of the code block, wherein the values of the codes in the copy of the code block in the bottom right corner of the first square grid are inverted.