Patent ID: 6425102
Filing Date: 2002-07-23
Classification: G06F

Abstract:
Digital signal processor comprising:a processor for processing digital signals; a memory that holds data for self-testing the processor; a data transfer circuit connected to receive self-test control data output by the processor; a data hold circuit connected to receive self-test result information output from the processor; an operation controller connected to receive control signals from the processor, and having an output for providing a restart signal after a specified time has elapsed; a first switching circuit with inputs connected to a first external input terminal and the data transfer circuit and an output connected to a data input terminal of the processor, for selecting either data from the first external input terminal or self-test control data from the data transfer circuit; and a second switching circuit with inputs connected to receive signals from a second external input terminal, the data transfer circuit, and the operation controller and having an output connected to a halt terminal of the processor, wherein during self-test, the processor is operable to halt in response to a halt signal selected by the second switching circuit from the data transfer circuit responsive to the self-test control data output by the processor, and to resume operation after the specified time has elapsed in response to the restart signal selected by the second switching circuit from the operation controller; and wherein the processor provides internal state information during self-testing to the data hold circuit and provides halt state information after resuming operation in response to the restart signal.