Patent ID: 7557643
Filing Date: 2009-07-07
Classification: H03K

Abstract:
1. A de-glitch circuit having an input and an output, comprising: a 3-input majority circuit having first, second and third inputs and having an output connected to the output of the de-glitch circuit; a first Set-Reset flip-flop having a first Set input, a first Reset input, and a first flip-flop output, wherein the first flip-flop output is connected to the first input of the majority circuit, and wherein the first Set input is connected to the input of the de-glitch circuit; a second Set-Reset flip-flop having a second Set input, a second Reset input, and a second flip-flop output, wherein the second flip-flop output is connected to the second input of the majority circuit, and wherein the second Set input is connected to the input of the de-glitch circuit; a first delay circuit having an output and having an input connected to the input of the de-glitch circuit; a second delay circuit having an input connected to the output of the first delay circuit and having an output connected to the third input of the majority circuit; and a one-shot circuit having an input connected to the output of the first delay circuit and having an output connected to the first Reset input and the second Reset input.