Patent ID: 7511753
Filing Date: 2009-03-31
Classification: G11C

Abstract:
1. A readout circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, characterized in that the readout circuit is adapted for use with an imaging array and further comprises a shift register associated with each decoder, each decoder being arranged to load the shift register associated therewith at any point along the length of the shift register, and further wherein each decoder circuit element has associated therewith an adder, with said adders connected in series, with each adder adapted to add a value to its input and provide its output to an input of the next adder if present, wherein each output provides a unique address for its associated decoder circuit.