Patent ID: 8713293
Filing Date: 2014-04-29
Classification: G06F

Abstract:
1. A processor for electronic computing comprising: an instruction register; an instruction decoder having a decoded instruction output with an instruction operand output, said instruction decoder operable to successively decode a repeat instruction and a repeated instruction having an operand; a pipeline having pipestages including a particular pipestage coupled to said decoded instruction output; and a repeating instruction circuit coupled between said instruction decoder and said particular pipestage, said repeating instruction circuit responsive to said repeat instruction to program an operand value range for causing execution of said repeated instruction a plurality of times in response to the operand value range while causing execution of the repeat instruction less than the plurality of times and also responsive to said repeated instruction and an operand of said repeated instruction to vary the value of said repeated instruction operand over said operand value range and deliver the varying value of said repeated instruction operand to said particular pipestage, wherein the repeating instruction circuit is for causing execution of said repeated instruction a plurality of times in response to the operand value range while causing execution of the repeat instruction only a single time corresponding to the execution of said repeated instruction a plurality of times.