Patent ID: 6490210
Filing Date: 2002-12-03
Classification: G11C

Abstract:
A semiconductor memory integrated circuit comprising:a memory cell array in which a plurality of normal signal lines for selecting a memory cell are arranged; a redundant cell array in which three or more of odd number of spare signal lines for compensating for defectiveness in said memory cell array are arranged; a decoder for decoding an address signal to select a normal signal line; a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line; and a test control circuit for controlling said decoder and said spare decoder to carry out a test of applying a voltage between adjacent lines in said normal signal lines and said spare signal lines, at the time of performing the test, said test control circuit setting potential levels in a signal line group including said normal signal lines and said spare signal lines so that a plurality of signal lines included in said signal line group are turned active simultaneously and potential levels of two adjacent signal lines are opposite to each other.