Patent ID: 6314042
Filing Date: 2001-11-06
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory array having a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns and aligned in row and column directions;a plurality of column selection lines arranged in said column direction in each of a region outside said memory array and an inter-block region between adjacent memory blocks for transmitting column selection signals, each of said column selection signals designating a column in corresponding memory blocks aligned in the column direction along the column selection line when activated;a plurality of internal data lines ranged extending in the column direction over said plurality of memory blocks and grouped into groups corresponding to column blocks each including memory blocks aligned in the column direction of said plurality of memory blocks; andcolumn selection circuits arranged corresponding to said memory blocks, each of the column selection circuits selecting a column of memory cells in a corresponding memory block for connection to one of the internal data lines of a corresponding group in accordance with the column selection signal on a corresponding column selection line, each of said column selection circuits including a decoding circuit arranged in said region outside the memory array or said inter-block region for generating a local column selection signal for a corresponding memory block in accordance with a row block designation signal designating the memory blocks aligned in the row direction and with the column selection signal on the column selection line arranged in a corresponding region.