Patent ID: 8472264
Filing Date: 2013-06-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines; a sense amplifier; a clamping transistor connected between the sense amplifier and the bit lines and a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit generating the clamp voltage when data is read out from a selected memory cell; wherein the memory cell array is divided into a plurality of blocks in a direction in which the bit lines extend, and m groups (m>2) include two or more of the plurality of blocks, each of said m groups are adjacent to each other in a direction of the bit lines, and the clamp voltage generation circuit determines the clamp voltage on the basis of said m groups to which the selected memory cell belongs.