Patent ID: 6888201
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. An integrated multiple vertical npn transistor ESD protection structure on a semiconductor substrate, functionally connected between an integrated circuit input or output pin and ground which will prevent electrostatic discharge damage to said integrated circuit comprising: a first semiconductor layer having a first conductivity dopant dopent type; a second semiconductor layer overlying said first semiconductor layer, having a similar conductivity type as said first layer, but a different dopant concentration; a third semiconductor layer having a second conductivity dopant type opposite that of said first semiconductor layer, disposed in overlying relation to said second semiconductor layer; a plurality of first regions of said first conductivity type electrically connecting with said first semiconductor layer, having a top element making electrical contact to said first regions and said first semiconductor layer; a plurality of second regions of said second conductivity dopant type laterally spaced from said first regions, being electrically connected to said third semiconductor layer having a top element making electrical contact to said second regions and said second semiconductor layer; and a plurality of third regions of said first semiconductor layer conductivity dopant type laterally spaced and interposed between said second regions, wherein said third regions form multiple emitter elements, said multiple emitter elements being electrically connected by a conductor element with “N” horizontal stripe conductor elements connected in a contiguous comb like manner by a vertical contact conductor element at one end of said horizontal stripe conductor elements.