Patent ID: 6931508
Filing Date: 2005-08-16
Classification: G06F

Abstract:
1. An information processing device provided with a memory consisting of N memory areas with a M-bit width and having a M×N-bit write width where M and N are natural numbers, the information processing device comprising: a first register that stores first data to generate addresses; a second register that stores second data to generate addresses; a third register that stores data sizes to be written; a first address adder that generates a first address, based on the data stored in the first register and the data stored in the second register; a second address adder that generates a second address by adding N to the first address; a write control circuit that generates write control signals for the N memory areas, based on the first address and the data sizes to be written; (N−1) selectors that select either the first address or the second address; (N−1)th memory areas into which data is written, based on the addresses supplied from the selectors and the write control signals; and the Nth memory area into which data is written, based on the first address and the write control signals, wherein, when integers represented by low-order 3 bits in the first address are K in the case of N=8,