Patent ID: 6819151
Filing Date: 2004-11-16
Classification: G11C,H03L

Abstract:
A memory device, comprising:an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a clock synchronization circuit coupled at least to the read/write circuit and configured to receive an input clock signal, the clock synchronization circuit comprising, a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal that is a function of a delay control signal; a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed clock signal and the input clock signal; an output mode circuit configured to receive a output drive strength signal and coupled to the variable delay line and the comparison circuit, the mode circuit operable to adjust the value of the delay control signal to provide a delayed clock signal having a first delay responsive to the output drive strength signal having a first state, and operable to adjust the value of the delay control signal to provide a delayed clock signal having a second delay responsive to the output drive strength signal having a second state; and an output circuit coupled to the variable delay line and the output mode circuit, the output circuit operable in a first output drive strength mode responsive to the output drive strength signal having the first state to generate an output signal responsive to the delayed clock signal having the first delay, and operable in a second output drive strength mode responsive to the output drive strength signal having the second state to generate the output signal responsive to the delayed clock signal having the second delay.