Patent ID: 8627169
Filing Date: 2014-01-07
Classification: G06F,H03M

Abstract:
1. A method for providing dynamically configurable error correction, comprising: receiving a first signal, wherein the first signal indicates a particular level of error detection that comprises a number of detectable bits in a set of data; dynamically configuring a check code generator based on the received first signal to generate a variable amount of check codes capable of detecting errors in the set of data, wherein the check code generator includes a plurality of check code logic modules that each include logic to produce a particular number of check bits and logic for selecting a particular check code logic module output to provide the particular level of error detection; receiving a second signal, wherein the second signal indicates a particular level of error addressing that comprises a number of calculable error location addresses associated with the number of detectable bits in the set of data, wherein the particular level of error addressing is variable with respect to the particular level of error detection; and dynamically configuring an error locator based on the received second signal to calculate error location addresses capable of locating errors in the set of data, wherein the error locator includes hardware designed to detect a maximum level of error addressing and a particular amount of the hardware is utilized based on the particular level of error addressing.