Patent ID: 8879295
Filing Date: 2014-11-04
Classification: G11C

Abstract:
1. An integrated circuit structure, comprising: a memory under repair having variable size blocks of failed memory addresses; a first memory operatively connected to a virtual address line, said first memory comprising cells storing data values comprising ranges of said failed memory addresses in said memory under repair; a second memory operatively connected to said first memory, matchlines of said first memory driving wordlines in said second memory, each entry in said first memory corresponding to one entry in said second memory and each entry representing a single block of failed memory addresses; and a gate having two inputs, a first input being operatively connected to said second memory and a second input being operatively connected to said virtual address line, responsive to a virtual address being an address in one of said ranges of said failed memory addresses in said memory under repair, said gate calculating a physical memory address redirecting said virtual address to an unused good memory location in place of said failed memory address in said memory under repair.