Patent ID: 8581624
Filing Date: 2013-11-12
Classification: H03K

Abstract:
1. A programmable logic region on a programmable integrated circuit, comprising: a first set of look-up tables operable to receive programmable logic region input signals for the programmable logic region; a second set of look-up tables operable to provide programmable logic region output signals for the programmable logic region; multiplexer circuitry coupled between the first set of look-up tables and the second set of look-up tables, wherein the multiplexer circuitry is operable to receive the programmable logic region input signals and output signals from the first set of look-up tables and is further operable to provide corresponding selected signals to the second set of look-up tables; and a plurality of inputs at which the programmable logic region input signals are received by the programmable logic region, wherein at least one input of the plurality of inputs is coupled in parallel to the first and second sets of look-up tables.