Patent ID: 6413817
Filing Date: 2002-07-02
Classification: H01L,Y10S

Abstract:
A method of forming a self-aligned stacked capacitor, comprising the steps of:providing a substrate having a first insulation layer thereon; forming a bit line contact and a first section node contact through the first insulation layer and a bit line structure above the first insulation layer, wherein the bit line structure includes a bit line, a cap layer and spacers, the bit line connects electrically with the bit line contact, the cap layer is above the bit line and the spacers are on sidewalls of the bit line and the cap layer; sequentially forming a second insulation layer, an etching stop layer and a third insulation layer over the substrate; forming an opening through the second insulation layer, the etching stop layer and the third insulation layer to expose a portion of the bit line structure and the first section node contact; forming a conformal first conductive layer over an interior surface of the opening to form a second section node contact, wherein a bottom portion of the first conductive layer forms a bottom section of a lower electrode and an upper portion of the first conductive layer forms a crown-shaped section of the lower electrode; and sequentially forming a conformal dielectric layer and a second conductive layer over the substrate, wherein the second conductive layer forms an upper electrode of the stacked capacitor.