Patent ID: 6121090
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method for fabricating a self-aligned silicided MOS transistor with an extended S/D junction in a functional device and an ESD protective device on a silicon substrate which has a defined gate structure, a defined source/drain and each device separated by an isolated region, said method comprising the steps of:1. forming a pad oxide, and poly-oxide layer on said defined source/drain and on all surfaces of a poly-SI of said defined gate structure, respectively;2. forming a first mask on said functional device of said substrate;3. performing a first stage ion implantation so that said defined source/drain in said ESD protective device is doped;4. removing said first mask;5. forming a first insulating layer on all exposed surfaces of said substrate;6. forming a second mask on said ESD protective device of said substrate;7. performing an anisotropic etching back said first insulating layer of exposed areas to form spacers on sidewalls of said defined gate structure in said functional device;8. removing said second mask;9. forming a metal layer on all exposed surfaces of said substrate;10. performing a first thermal annealing said substrate, so that a silicide layer and a polycide layer are formed, respectively, on said defined source/drain and said defined gate structure of functional device;11. removing unreacted metal layer on said isolation region, and said spacers;12. performing a second stage ion implantation into and/or through said silicide layer and said polycide layer of said substrate, so that said silicide layer and polycide layer on said defined source/drain and on said defined gate structure are doped respectively;13. a performing a second thermal annealing said substrate, so that an ultra-shallow source/drain junction in the functional device is formed;14. removing said first insulating layer of said ESD protective device and spacers of sidewalls of said defined gate structure in said functional device;15. performing a third stage ion implantation so that an extended source/drain is formed in said functional device, and dopants in said protective device are enhanced;16. performing a second insulating layer deposition on entire surfaces of said substrate; and17. performing a third thermal annealing said substrate so that said second insulating layer is condensed.