Patent ID: 6557138
Filing Date: 2003-04-29
Classification: G06F,G11C

Abstract:
Method for correction of errors in a binary word stored in multi-level memory cells, each of which contains a set of n bits, using a minimum number of correction bits, wherein for each set of bits in said binary word stored in a single memory cell, the method comprises the following steps:a) associating, with a single error in each bit in said set of bits, a respective error code which is not associated with other errors in said binary word and is indicative of a position of the incorrect bit in the binary word; b) for each sub-set of multiple errors in bits in said set of bits, carrying out the following steps: b1) associating, with said sub-set of multiple errors, a respective error code which is dependent on the error codes associated with the single errors in the bits in the sub-set; b2) checking whether the error code associated with said sub-set of multiple errors has already been associated with other errors in said binary word; b3) if the error code associated with said sub-set of multiple errors has already been associated with other errors in said binary word, carrying out the following steps: b31) rejecting said error code associated with said sub-set of multiple errors and at least one of the error codes associated with the single errors in the bits in the sub-set; b32) associating, with the single error associated with the error code rejected, a new error code which is not associated with other errors in said binary word; and b33) repeating said steps from b1) to b3) until the error code associated with said sub-set of multiple errors is not associated with other errors in said binary word.