Patent ID: 6774413
Filing Date: 2004-08-10
Classification: H01L

Abstract:
An integrated circuit structure for MOS-type devices comprising:a silicon substrate of a first conductivity type; first gate insulating regions selectively placed over the silicon substrate of the first conductivity type; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulated therefrom.