Patent ID: 6803276
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of fabricating a non-volatile semiconductor memory device comprising:forming a charge storage layer on a substrate; forming a control gate layer on the charge storage layer; forming a gate mask in the shape of a spacer on the control gate layer; removing the charge storage layer and the control gate layer to expose a top portion of the substrate, wherein the gate mask protects a portion of the charge storage layer and the control gate layer to form a control gate and a charge storage region; forming a conductive region in the top portion of the substrate; forming a source-side insulative spacer on the top portion of the substrate adjacent a sidewall of the control gate and the charge storage region; and forming a source electrode on the conductive region, wherein the source electrode is electrically isolated from the control gate and the charge storage region by the source-side insulative spacer, and wherein a top of the source electrode is at the same level as, or below, a top portion of the gate mask.