Patent ID: 7400524
Filing Date: 2008-07-15
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a flip-flop which is formed by cross-coupling inputs and outputs of two inverters, the flip-flop including a first storage node at one terminal and a second storage node at the other terminal; a first MOS transistor of first conductivity type which has a gate connected to the first storage node of the flip-flop; a second MOS transistor of first conductivity type which has a gate connected to the second storage node of the flip-flop; a first transfer gate which has a current path with one end connected to one end of a current path of the first MOS transistor; a second transfer gate which has a current path with one end connected to one end of a current path of the second MOS transistor; a first diode which has an anode connected to the first storage node of the flip-flop and a cathode connected to said one end of the current path of the second transfer gate; and a second diode which has an anode connected to the second storage node of the flip-flop and a cathode connected to said one end of the current path of the first transfer gate.