Patent ID: 7437597
Filing Date: 2008-10-14
Classification: G06F

Abstract:
1. An error-correcting write-back cache comprising: a plurality of cache lines, a cache line being selected for access by a cache hit that matches a tag portion of an address input to a store tag for the cache line; a data field in the cache line for storing data; an error-code field in the cache line for storing error code for the data in the cache line; a cache-state field for the cache line, the cache-state field indicating a clean state and a dirty state, wherein the cache line in the clean state has a back-up copy of the data in an external memory, wherein the cache line in the dirty state has no back-up copy of the data in the external memory; a syndrome generator, receiving the data from the data field and the error code from the error-code field of the cache line selected for access, the syndrome generator generating an error syndrome that indicates a detected error in the data; an error corrector, coupled to the syndrome generator, the error corrector examining the cache-state field for the cache line to determine when the cache line is in the clean state, the error corrector re-fetching the back-up copy of the cache line from the external memory to replace the data in the data field when the syndrome generator indicates the detected error for a cache line in the clean state; wherein the error corrector uses the error syndrome generated from the error code to locate and correct an error in the data field when the cache line is in the dirty state; wherein the error corrector corrects single-bit errors in the data field and signals an uncorrectable error for longer multi-bit errors in the data field, wherein single-bit errors in dirty cache lines are corrected while longer multi-bit errors are uncorrectable for dirty cache lines but corrected by re-fetching clean cache lines; wherein the error code for dirty cache lines is a code value in a first error code, the first error code comprising a first set of error encodings of the data field; wherein the error code for clean cache lines is a code value in a second error code, the second error code comprising a second set of error encodings of the data field, whereby clean and dirty cache lines use different error codes in different sets of error encodings of the data field and whereby clean cache lines with detected errors are re-fetched from the external memory, and dirty cache lines are error-corrected using the error code.