Patent ID: 6754775
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A method for facilitating flow control at a cache memory in order to support pipelined accesses to the cache memory, comprising:receiving an access to the cache memory; wherein the cache memory is set-associative; if the access generates a miss in the cache memory, identifying a set that the access is directed to, incrementing a number of outstanding misses that are currently in process for the set, and if the number of outstanding misses is greater than or equal to a threshold value, stalling generation of subsequent accesses to the cache memory until the number of outstanding misses for each set in the cache memory falls below the threshold value, wherein the threshold value is less than a number of entries in the cache memory associated with each set, thereby reserving one or more additional entries for each set to accommodate in-flight accesses that have been generated but not received at the cache memory.