Patent ID: 6069050
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method for manufacturing a low voltage coefficient capacitor comprising:providing a partially completed integrated circuit;depositing a first layer of polysilicon;forming a layer of tungsten silicide on said first layer of polysilicon;photolithographically etching said layer of tungsten silicide and said first layer of polysilicon to form first and second bottom electrodes;depositing a layer of a dielectric on said layer of tungsten silicide;photolithographically etching contact holes in the dielectric layer down to the level of the tungsten silicide;depositing a second layer of polysilicon on the dielectric layer, said polysilicon having semiconductive conductionphotolithographically etching said second layer of polysilicon to form first and second top electrodes that overlie the bottom electrodes, while leaving said contact holes clear;depositing a layer of a conductive material on the top electrodes and on the dielectric layer; andphotolithographically etching said layer of conductive material to form thin film wiring extending from the first bottom electrode, through the contact holes, to the second top electrode and from the second bottom electrode, through the contact holes, to the first top electrode.