Patent ID: 6025623
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A semiconductor device comprising:a plurality of active region groups regularly arranged on the surface of a semiconductor substrate;an element isolation region formed between said plurality of active region groups;a plurality of wiring groups arranged in parallel to one another on and intersecting said plurality of active region groups;a first insulating film formed to selectively cover said plurality of wiring groups; anda second insulating film formed to fill spaces between said plurality of wiring groups;wherein said plurality of active region groups are arranged and shifted from one another in the array direction of said plurality of wiring groups by a deviation amount of 1/n (n>1) of a distance between said plurality of active region groups in a direction in which said plurality of wiring groups extend, contact areas for each of said plurality of active region groups are each formed in an area extending in a projection form from each of said plurality of active region groups in a direction in which said plurality of wiring groups extend between adjacent wirings among said plurality of wiring groups, said second insulating film has openings on said contact areas and on areas of said plurality of active region groups between said plurality of wiring groups, contact electrode wiring layers are formed to fill the openings on said contact areas, and the length X of the area extending in the projection form in said contact area in the direction in which said plurality of wiring groups extend satisfies the relation of L.sub.1 <X<2L.sub.1 +L.sub.2 when the width of each of said element isolation regions in the direction in which said plurality of wiring groups extend is set to L.sub.1 and the width of one of said plurality of active regions in the above direction is set to L.sub.2.