Patent ID: 7135773
Filing Date: 2006-11-14
Classification: B82Y,H01L,Y10S

Abstract:
1. An integrated circuit chip, comprising: a plurality of active devices formed on a substrate; a plurality of electrical conductors in one or more conductive layers for providing electrical connections to said plurality of active devices, each said electrical conductor lying in a respective conductive layer of said one or more conductive layers and forming a respective portion of a respective electrical logic circuit path to one or more said plurality of active devices; and a plurality of electrically conductive vias, each via electrically connecting a respective first electrical conductor of said plurality of electrical conductors in a respective first conductive layer with at least one of the set consisting of: (a) a respective second electrical conductor of said plurality of electrical conductors in a respective second conductive layer, each said respective second conductive layer being separated from the respective first conductive layer by a dielectric layer, and (b) a respective active device of said plurality of active devices formed on said substrate, said plurality of active devices being separated from the respective first conductive layer by a dielectric layer, each said electrically conductive via forming a respective portion of a respective electrical logic circuit path to one more said plurality of active devices; wherein each said conductive via comprises a plurality of carbon nanotubes embedded in an electrically conductive metal, said plurality of carbon nanotubes being surrounded by and embedded in said electrically conductive metal throughout the length of the via.