Patent ID: 6098160
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes comprising, in combination:a data pointer register for storing a current address of an operand to be used in a simple indirect addressing mode;a processor architecture scheme which allows for encoding of multiple addressing modes, said processor architecture scheme comprising:a central processing unit (CPU);a memory coupled to said CPU for storing data; anddedicated virtual register address locations in said memory associated with said data pointer register wherein each of said dedicated virtual register address locations dictates and establishes a separate and different indirect addressing mode to be used with said data pointer register when accessed;an incrementer coupled to said data pointer register for incrementing said current address of an operand to be used in a simple indirect data addressing mode by a set number for generating an address of an operand to be used in an indirect addressing mode with auto preincrement;an adder coupled to said data pointer register for combining said current address of an operand to be used in a simple indirect data addressing mode with an offset number for generating an address of an operand to be used in an indirect addressing mode with offset, said adder being a simple serial adder with serial carry;an offset register coupled to said adder for storing and sending said offset number to said adder when signaled; anda multiplexer circuit coupled to an output of said data pointer register, to an output of said incrementer, and to an output of said adder for selecting a desired indirect addressing mode address.