Patent ID: 6011727
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A block write circuit in a memory device including at least one array of memory cells, each of the at least one array of memory cells including a plurality of memory cells arranged in rows and columns and a plurality of digit lines, each digit line coupled to a plurality of memory cells in an associated column, the block write circuit comprising:a plurality of input/output lines;a switch circuit coupled between the input/output lines and the digit lines, the switch circuit selectively coupling at least one digit line to each input/output line responsive to an address signal during a block write mode of operation;a plurality of driver circuits, each driver circuit including an input an output coupled to a respective input/output line, and developing a data signal on its output in response to a data signal applied on its input; anda multiplexer circuit having an input adapted to receive a data signal, and a plurality of outputs coupled to respective inputs of the driver circuits, the multiplexer circuit coupling its input to its outputs responsive to a control signal during the block write mode of operation.