Patent ID: 6469937
Filing Date: 2002-10-22
Classification: G11C

Abstract:
A current sense amplifier circuit connected to a data line to which a bit line of a memory cell array is connected through a selection transistor, comprising:an inversion amplifier for receiving a voltage at the data line; a first N type MOS transistor connected to the data line, and having a control node connected to the output of the inversion amplifier; a first P type MOS transistor having a source connected to a power supply voltage, and a gate and a drain which are connected to each other and to the first N type MOS transistor; a second P type MOS transistor having a source connected to the power supply voltage, and a gate connected to the gate of the first P type MOS transistor; a second N type MOS transistor having a source connected to a ground voltage, and a drain connected to a drain of the second P type MOS transistor; a third N type MOS transistor having a source connected to a ground voltage, and a gate and a drain which are connected to a gate of the second N type MOS transistor; a third P type MOS transistor having a source connected to the power supply voltage, and a drain connected to the drain of the third N type MOS transistor; a fourth N type MOS transistor having a source, a drain, and a gate, one of the source and the drain being connected to the drain of the second P type MOS transistor while the other is connected to the drain of the third P type MOS transistor, and the gate being connected to a first input terminal to which an equalization signal is applied; a fourth P type MOS transistor having a source, a drain, and a gate, one of the source and the drain being connected to the drain of the second P type MOS transistor while the other is connected to the drain of the third P type MOS transistor, and the gate being connected to a second input terminal to which an inverse signal of the equalization signal is applied; a comparator having a positive input terminal connected to the drain of the third P type MOS transistor, a negative input terminal connected to the drain of the second P type MOS transistor, and an output terminal being an output terminal of the circuit; and a reference current generator for applying a voltage to a gate of the third P type MOS transistor so that the amount of drain current of the third P type MOS transistor becomes equal to a predetermined amount of reference current; wherein a memory cell current, which flows through the data line, is detected by comparing the amount of reference current with the amount of current at the data line.