Patent ID: 6301159
Filing Date: 2001-10-09
Classification: G11C

Abstract:
A tracking circuit for performing an erase verify/erase operation so to prevent over-erasure in an array of Flash EEPROM memory cells, said tracking circuit comprising:binary counter means responsive to clock pulses corresponding to erase pulses for counting the number of erase pulses during a normal erase verify/erase operation;counter register means for storing 50%, 25%, and 12.5% of a diagonal erase pulse count corresponding to binary representations of the total number of said clock pulses obtained from said binary counter means during a diagonal erase verify operation;said counter resister means including a first counter register for storing said 50% of the diagonal erase pulse count, a second counter resister for storing said 25% of the diagonal erase pulse count, and a third counter register for storing said 12.5% of the diagonal erase pulse count;multiplexer circuit means responsive to said counter register means for selectively pre-loading said binary counter means with a binary representation corresponding to one of a number of target counts prior to the normal erase verify/erase operation; andcomparator means responsive to said binary counter means and said counter register means for comparing a pulse count of said clock pulses obtained from the normal erase verify/erase operation and said 50% of the diagonal pulse count from said counter register means and for generating a high logic signal when said pulse count equals said 50% of the diagonal pulse count so as to indicate that said corresponding one of the number of target counts has been reached.