Patent ID: 6334120
Filing Date: 2001-12-25
Classification: G06N

Abstract:
A semiconductor arithmetic circuit to specify the maximum voltage signal among a plurality of input signals comprising:a plurality of inverter circuits constructed using a neuron MOS transistor, said neuron MOS transistor having a semiconductor region of one conductivity type on a substrate, said region provided with source and drain regions of an opposite conductivity type, a floating gate electrode which is provided at a region separating said source and drain regions via an insulting film and which is in an electrically floating state, and a plurality of input gates capacitively coupled with said floating gate electrode via an insulating film;a first logical arithmetic circuit having input and output terminals;a second logical arithmetic circuit having input and output terminals for input and output signals respectively; anda third logical arithmetic circuit having input and output terminals for input and output signals respectively, the performance of said third logical arithmetic circuit being controlled by the output signal of said second logical arithmetic circuit; whereinsaid plurality of input signals are inputted to respective first input gate of said plurality of inverter circuits, output signals of said plurality of inverter circuits are inputted to said input terminals of said first and second logical arithmetic circuits, an output signal of said first arithmetic logical circuit is inputted into said input terminal of said third arithmetic logical circuit, and said output signal of said third arithmetic logical circuit is fed back to second input gates of said plurality of inverter circuits.