Patent ID: 6211693
Filing Date: 2001-04-03
Classification: G01R

Abstract:
A testable cascode output buffer circuit used with an external voltage greater than a maximum voltage stress level of a single transistor, said output buffer circuit comprising:a bias network connected between the external voltage and ground, said bias network producing a first bias voltage equal to the maximum voltage stress level and a second bias voltage equal to a difference between the external voltage and the maximum voltage stress level;a cascode configuration of active devices includinga first switching transistor having a source connected to the external voltage, a gate connected to a first input and a drain connected to a first intermediate node,a first cascode transistor having a source connected to the first intermediate node, a gate connected to said second bias voltage and a drain connected to an output node of said output buffer circuit,a second cascode transistor having a source connected to said output node, a gate connected to said first bias voltage and a drain connected to a second intermediate node, anda second switching transistor having a source connected to said second intermediate node, a gate connected to a second input and a drain connected to ground; anda test circuit indicating normal operation of said first and second cascode transistors by not conducting and indicating a short of either said first cascode transistor or said second cascode transistor by conducting, said test circuit includinga first biasing transistor having a source connected to the external voltage, a gate connected to said first bias voltage and a drain connected to a third intermediate node,a first test transistor having a source connected to said third intermediate node, a gate connected to said first intermediate node and a drain connected to a fourth intermediate node,a second test transistor having a source connected to said third intermediate node, a gate connected to said second intermediate node and a drain connected to said fourth intermediate node, anda second biasing transistor having a source connected to said fourth intermediate node, a gate connected to said second bias voltage and a drain connected to ground.