Patent ID: 6651199
Filing Date: 2003-11-18
Classification: G01R

Abstract:
A trigger circuit for generating an instruction signal utilized by a control state machine in an In-System Programmable (ISP) memory device, the ISP memory device including a JTAG circuit having a standard TAP controller for generating a RUN-TEST signal when the TAP controller is in a RUN-TEST/IDLE state, and an instruction register circuit for generating a first instruction signal, the trigger circuit comprising:a first logic circuit for generating a logic high output signal when both the RUN-TEST signal and the first instruction signal are in a first logic state; a delay circuit for receiving the RUN-TEST signal and for generating a logic high output signal a predetermined number of clock cycles after the RUN-TEST signal changes to the first logic state; an inverter connected to an output terminal of the delay circuit; and a second logic circuit having a first input terminal connected to an output terminal of the first logic circuit, a second input terminal connected to an output terminal of the inverter, and an output terminal connected to an input terminal of the control state machine, wherein the trigger circuit transmits a second instruction signal to the control state machine in response to the RUN-TEST signal and the first instruction signal being in the first logic state, wherein the second instruction signal is maintained in the first logic state for the predetermined number of clock cycles, thereby avoiding erroneous operation of the control state machine caused when the RUN-TEST signal and the first instruction signal remain in the first logic state for an extended period.