Patent ID: 7158428
Filing Date: 2007-01-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines extending in a row direction; a plurality of pairs of local bit lines extending in a column direction; a plurality of memory cells respectively arranged in row and column directions, the memory cells being connected to the word line on every row and connected to the pair of local bit lines on every column; a pair of global bit lines extending in the column direction and corresponding to the plurality of pairs of local bit lines; a plurality of precharge circuits each including an input terminal being connected to a control signal line and an output terminal being connected to the plurality of pairs of local bit lines, the precharge circuits being activated during a period when the control signal line is set to a first polarity; and a plurality of local write amplifier circuits each including a data input terminal being connected to the pair of global bit lines, a control input terminal being connected to the control signal line, and an output terminal being connected to the plurality of pairs of local bit lines, the local write amplifier circuits being activated during a period when the control signal line is set to a second polarity, wherein the pair of global bit lines comprises: a first pair of global bit lines and a second pair of global bit lines extending in the column direction and corresponding to the pair of local bit lines, wherein the plurality of local write amplifier circuits each including a data input terminal being connected to the first pair of global bit lines, a control input terminal being connected to the control signal line, and an output terminal being connected to the plurality of pairs of local bit lines, the local write amplifier circuits being activated during a period when the control signal line is set to a second polarity, and wherein the semiconductor memory device further comprises: a plurality of local read amplifier circuits each including an input terminal being connected to the plurality of pairs of local bit lines and an output terminal being connected to the second pair of global bit lines; a global write amplifier circuit including an input terminal being connected to a data input signal line and an output terminal being connected to the first pair of global bit lines; and a global read amplifier circuit including an input terminal being connected to the second pair of global bit lines and an output terminal being connected to a data output signal line.