Patent ID: 6643197
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A semiconductor memory device comprising:an ordinary memory cell array, arranged in an M-column-by-N-row structure, comprising M ordinary columns each of which has N ordinary memory cells, and each ordinary column respectively coupled to a corresponding data line of a data bus, wherein M and N are a first and a second positive integers greater than one; an ordinary decoder, connected to the ordinary memory cell array, and receiving a decode-inhibit signal and an address signal, for decoding the address signal to drive one of the ordinary memory cells when the decode-inhibit signal is de-asserted; a redundant memory cell array, arranged in a P-column-by-N-row structure, including P redundant columns each of which has N redundant memory cells, and the P redundant columns adapted to replace defective columns in the M ordinary columns, in which a defective column Xm-p, where 1&lE;m&lE;M and 1&lE;p&lE;P, represents an mth ordinary column identified as defective and replaced with a pth redundant column, and wherein P is a third positive integer greater than one; a redundant decoder, connected to the redundant memory cell array and the ordinary decoder, comprising P redundant decode circuits respectively receiving a column address of the address signal, in which a pth redundant decode circuit provides a pth redundant decode signal to the pth redundant column in the redundant memory cell array for driving the pth redundant column when the pth redundant decode circuit receives the column address indicative of the defective column Xm-p; a redundant switch circuit having P redundant output switches, in which a pth redundant output switch, responsive to the pth redundant decode signal and a pth select code, couples the pth redundant column to a mth data line of the data bus corresponding to the defective column Xm-p; and a pth output set circuit, incorporated in the pth redundant output switch, comprising: k fuses working in conjunction with a plurality of transistors, in which the k fuses are selectively cut to set k logic signal values and respective complements thereof; and M logic circuits, for decoding the k logic signal values and the complements thereof into the pth select code when the pth redundant decode signal is asserted, where kk.