Patent ID: 7308594
Filing Date: 2007-12-11
Classification: G06F,G11C

Abstract:
1. A synchronous data output circuit, comprising: an output driver having a data input terminal at which input data is applied, an output terminal at which output data is provided, and a clock terminal at which a clock signal is applied, the output driver operable to provide the input data as the output data in response to the clock signal; a synchronizing circuit having an input terminal at which an external clock signal is applied and having an output terminal at which an internal clock signal is provided, the synchronizing circuit generating the internal clock signal based on the external clock signal; and a plurality of delay circuits, each having an input coupled to the output terminal of the synchronizing circuit, and having an activation terminal to which a selection signal is applied and further having an output terminal coupled to the clock terminal of the output driver, each of the plurality of delay circuits having a respective time delay and operable to generate a respective delayed output clock signal having the respective time delay relative to the internal clock signal when activated by the selection signal, one of the plurality of delay circuits activated by the selection signal to provide the respective delayed output clock signal as the clock signal synchronizing output of data by the output driver, each of the plurality of delay circuits having a different time delay.