Patent ID: 6812757
Filing Date: 2004-11-02
Classification: H03D,H03F,H03L

Abstract:
An integrated circuit including a phase lock loop circuit to reduce a phase difference between first and second clock signals, the phase lock loop circuit comprising:a voltage-to-current circuit to influence a voltage on a capacitor, wherein the voltage-to-current circuit comprises: a first transconductance amplifier to source a first current when a positive voltage differential exists between the two voltage values; a second transconductance amplifier to sink a second current when a negative voltage differential exists between the two voltage values; and an output stage coupled between the first transconductance amplifier and the capacitor, and coupled between the second transconductance amplifier and the capacitor; a voltage controlled oscillator responsive to the voltage on the capacitor to produce the second clock signal; and a sampling circuit responsive to the first and second clock signals to generate two voltage values, a difference of the two voltage values being a function of the phase difference between the first and second clock signals, wherein the first transconductance amplifier comprises: a first input stage having n-channel transistors with gates to receive the two voltage values; and a first current mirror coupled to the n-channel transistors, such that the first current is substantially equal to a difference between a current in the first current mirror and a current in the first input stage.