Patent ID: 7339220
Filing Date: 2008-03-04
Classification: H01L

Abstract:
1. A memory device, comprising: an array of memory cells disposed in rows and columns, said memory cells including (i) array transistors having gates, storage node contacts, and bitline contacts where said gates have sidewall spacers, (ii) first conductive pads abutting said sidewall spacers and connecting said storage node contacts to storage capacitors, and (iii) second conductive pads abutting said sidewall spacers and connecting said bitline contacts to bitlines; and peripheral circuitry disposed adjacent said array, said peripheral circuitry including (i) n-channel transistors having gates, sources, and drains where said gates have sidewall spacers which have the same structure as said sidewall spacers of said array transistor gates, and (ii) p-channel transistors having gates, sources, and drains where said gates have sidewall spacers which have the same structure as said sidewall spacers of said array transistor gates; wherein said peripheral circuitry lacks conductive pads which have the same structure as either said first conductive pads or said second conductive pads and wherein each of the conductive pads in the interior of said array abut two of said sidewall spacers but each of the conductive pads at the boundary of said array abut only one of said sidewall spacers.