Patent ID: 7028213
Filing Date: 2006-04-11
Classification: G06F

Abstract:
1. A system comprising: a host/data controller; and a memory system comprising a plurality of memory cartridges operably coupled to the host/data controller, each memory cartridge comprising an operation indicator configured to indicate the operational status of the corresponding memory cartridge, wherein the operation indicator comprises a bit having a first state and a second state, the first state indicating that the memory cartridge is operational and the second state indicating that the memory cartridge is not operational, wherein the memory system is configured to operate in a redundant mode when each of the bits is in the first state, wherein at least one of the host/data controller and the plurality of memory cartridges comprise error detection components, and wherein the host/data controller is configured to generate a low priority interrupt signal in response to error detection by the error detection components if each of the operation bits is in the first state.