Patent ID: 8880845
Filing Date: 2014-11-04
Classification: G06F

Abstract:
1. A memory system comprising: a memory; and an input/output memory management unit (I/O MMU) connected to the memory, and configured to receive a virtual address from an image rotator and configured to translate the virtual address into a physical address in the memory, wherein the memory includes a page table for storing entries matching the virtual addresses, and the page table comprises a first table that includes entries indicated by a first page descriptor, and a second table that includes entries indicated by a second page descriptor, wherein the I/O MMU includes a first buffer configured to only store a first entry in the first table that corresponds to the virtual address and is indicated by the first page descriptor, and a second buffer configured to store a plurality of second entries in the second table that correspond to the sequential virtual addresses and are indicated by the second page descriptor, wherein for translation of the virtual address, the I/O MMU searches within the I/O MMU for an entry matching the virtual address, and if no entry matching the virtual address is found within the I/O MMU as a result of searching within the I/O MMU for the entries, the I/O MMU accesses the memory, searches the memory for entries matching the virtual address, and stores the entries matching the virtual address into the I/O MMU.