Patent ID: 7093214
Filing Date: 2006-08-15
Classification: G06F,H01L

Abstract:
1. A method of performing a SPICE calculation and device simulation for a partially depleted SOI MOSFET formed on an SOI substrate comprising: increasing an input signal cycle and one of an output load capacitance and an output load resistance by a ratio X, wherein the ratio X is a ratio of an increased value of one of the input signal cycle, the output load capacitance, and the output load resistance to an initial value of one of the input signal cycle, the output load capacitance, and the output load resistance; finding an initial value Y of a total body charge at which there is zero fluctuation in the total body charge after one input signal cycle; and extrapolating a value of Y for when X=1 by expressing Y as a function of X to find a steady state during circuit operation of a partially depleted SOI MOSFET.