Patent ID: 6329832
Filing Date: 2001-12-11
Classification: G01R,Y10T

Abstract:
A method for electrically testing a flip-chip semiconductor assembly, comprising: providing at least one integrated circuit (IC) die having bond pads on a surface thereof; providing a substrate having electrical pads for mounting said at least one IC die thereto; placing curable wet conductive epoxy dots on said electrical pads on said substrate;attaching said at least one IC die to said substrate with said bond pads of said at least one IC die in contact with said curable wet conductive epoxy dots on said electrical pads on said substrate to form said flip-chip semiconductor assembly;testing said flip-chip semiconductor assembly;if said flip-chip semiconductor assembly fails said testing, then reworking said flip-chip semiconductor assembly and retesting said flip-chip semiconductor assembly or scrapping said flip-chip semiconductor assembly if it has already been reworked a preset number of times;if said flip-chip semiconductor assembly passes said testing, then curing said curable wet conductive epoxy dots; andencapsulating said at least one IC die on said substrate.