Patent ID: 7488662
Filing Date: 2009-02-10
Classification: H01L

Abstract:
1. A method of forming a VPNP transistor comprised of SiGe, the VPNP transistor is comprised of a VPNP emitter, a VPNP base, a VPNP collector, the method comprising: providing substrate having a VPNP region and a NPN region; said substrate having a VPNP buried N region around said VPNP region and a NPN buried N region in said NPN region; forming a buried N well in said VPNP region extending into said VPNP buried N region; forming a buried P+ region adjacent to and above said buried N well region; forming an epi layer over the substrate and the buried N well and the VPNP buried N region; said epi layer has a n-doping; forming an isolation region in said substrate at least between the VPNP region and a NPN region; forming N wells in said epi layer and substrate; said N wells contact said buried N well; forming a P well region in said VPNP region, wherein said P well region contacting said buried P region, the P Well in the epi layer and in the substrate, the P well is adjacent to the N Well, and portions of the P well are under the isolation region; forming a VPNP, P-collector region in said epi layer over said VPNP buried P region in said VPNP region; forming a VPNP N-base region in said VPNP collector region in said epi layer; forming a VPNP emitter in the VPNP region; forming N+ S/D regions in said VPNP region adjacent said VPNP emitter; forming a VPNP P+ region in the P well region; and forming a VPNP P+ emitter region in the VPNP base.