Patent ID: 7070088
Filing Date: 2006-07-04
Classification: B23K,H01L,H05K

Abstract:
1. A method for the assembly of a semiconductor device having fatigue-resistant interconnection elements, comprising the steps of: providing a semiconductor chip having at least one solder bump comprising an alloy of about ten weight percent tin and about ninety weight percent lead; providing a solder paste comprising tin and silver, said solder paste having a reflow temperature of about 221° C., said bump alloy having a melting temperature higher than said paste reflow temperature; bringing said solder bump in contact with said solder paste and immersing said bump partially in said paste; supplying thermal energy to reflow said solder paste at about 235° C.; controlling the amount of energy and time after said melting of said solder paste so that the molten paste dissolves a pre-determined amount of said solder bump to form a tin/lead/silver ternary alloy of about eutectic composition without melting said solder bump; and removing said thermal energy to cool said ternary alloy fillet and said bump.