Patent ID: 6236585
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A content addressable memory match circuit for detecting a match between a supplied data, bit and a stored data bit comprising:a data latch storing said stored data bit therein having a first output terminal producing a true bit signal and a second output terminal producing an inverse bit signal;a match precharge node;a source of precharge voltage;a precharge device connected to said match precharge node and said source of said precharge voltage during a precharge time;a conditional discharge device connected to said data latch and said match precharge node and receiving a supplied data bit signal, said conditional discharge device conditionally discharging said match precharge node during an evaluate time dependent on whether said stored data bit in said data latch matches said supplied data bit signal, said conditional discharge device includinga first series connection of a first transistor and a second transistor having serially connected source-drain paths connected between said match precharge node and a source of a second voltage other than said precharge voltage, said first transistor having a gate connected to said first output terminal of said data latch thus receiving said true data signal and said second transistor having a gate receiving an inverse of said supplied data bit signal, anda second series connection of a third transistor and a fourth transistor having serially connected source-drain paths connected between said match precharge node and said source of said second voltage other than said precharge voltage, said third transistor having a gate connected to said second output terminal of said data latch thus receiving said inverse data signal and said fourth transistor having a gate receiving said supplied data bit signal,whereby said precharge node is not discharged if said stored data bit in said data latch matches said supplied data bit signal.