Patent ID: 7557373
Filing Date: 2009-07-07
Classification: H01L

Abstract:
1. A thin-film transistor substrate including pixel regions where gate electrode lines are arrayed on an insulating substrate sandwiching semiconductor layer patterns and gate insulators with the substrate, wherein shapes of the semiconductor layer patterns and the gate electrode lines are set so that a value of k′ obtained from the following equation in case of n=1 is 0.40 (mm where capacitors constructing a capacitor between each of the semiconductor layer patterns and the metal table, a capacitor between each of the semiconductor layer patterns and each of the gate electrode lines, and a capacitor between each of the gate electrode lines and the metal table are calculated approximately as parallel plate capacitors of overlap areas, respectively, whereby, a parallel plate capacitor made between each of the semiconductor layer patterns and a projected pattern of the semiconductor layer pattern to a surface of the metal table is represented by Ca′, a parallel plate capacitor made only by an overlap area between each of the semiconductor layer patterns and each of the gate electrode lines is represented by Cb′, and a capacitor between each of the gate electrode lines and the metal table, obtained by composition calculation using Ca′ and Cb′, is represented by Ce′, a length of each of the gate electrode lines is represented by L, and a substrate surface area that one of the gate electrode lines is in charge of per unit length is S.