Patent ID: 8745608
Filing Date: 2014-06-03
Classification: G06F

Abstract:
1. A scheduler of a reconfigurable array having a plurality of processing elements, the scheduler comprising: an analyzer configured to analyze a sequence of executing commands or dependency thereof based on a data flow graph of the commands which are to be executed in the reconfigurable array; a first processor configured to detect a recurrence node which comprises a register node in which an output of a previous iteration is used as an input of a next iteration due to characteristics of a loop operation, and map the detected recurrence node to a central register file of the reconfigurable array; a second processor configured to detect a producer node recording the output from the previous iteration in the recurrence node, from the data flow graph, and map the producer node to a first processing element connected to the central register file for transferring data between the plurality of processing elements; and a third processor configured to detect a predecessor node receiving the input of the recurrence node in the next iteration, from the data flow graph, and map the predecessor node to a second processing element connected to the first processing element.