Patent ID: 7659958
Filing Date: 2010-02-09
Classification: G02F,H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate wire on an insulating substrate, the gate wire comprising gate lines, and first and second gate electrodes connected to the gate lines and spaced apart from each other by a predetermined distance; forming a gate insulating layer; forming first and second semiconductor layers; forming a data wire, the data wire comprising first and second data lines intersecting the gate lines and spaced apart from each other by a predetermined distance, first and second source electrodes which are respective parts of the first and the second data lines, and first and second drain electrodes respectively facing the first and the second source electrodes, wherein the first data line and the second data line are electrically connected to each other; forming a passivation layer having first and second contact holes respectively exposing the first and the second drain electrodes; and forming pixel electrodes, each connected to the first and the second drain electrodes, wherein the data wire further comprises upper and lower connection parts respectively disposed above and below each of two adjacent pixel electrodes in a layout view, the upper and lower connection parts connecting the first data line and the second data line.