Patent ID: 7293212
Filing Date: 2007-11-06
Classification: G01R,G11C

Abstract:
1. Apparatus for processing data, said apparatus being operable in a either a self-test mode or an operational mode, said apparatus comprising: a plurality of functional units, at least one of said functional units being operable to perform data processing operations and at least a subset of said plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory; a memory self-test controller operable in said self-test mode to output self-test data for performing access operations to confirm correct operation of said functional unit memory; a configuration ring-bus arranged to provide in said operational mode, a ring path for communication of configuration instructions between a first ring sequence of said plurality of functional units; a debug ring-bus arranged to provide in said operational mode, a ring path for communication of debug data between a second ring sequence of said plurality of functional units; wherein said first ring sequence is identical to said second ring sequence and said data processing apparatus is operable in said self-test mode to couple said configuration ring-bus and said debug ring-bus to provide a combined data path for communication of self-test data between said plurality of functional units.