Patent ID: 9171594
Filing Date: 2015-10-27
Classification: G06F,G11C

Abstract:
1. A multiport memory comprising: an array of storage cells for storing data, each storage cell comprising storage circuitry and a plurality of access control devices for isolating said storage circuitry from or connecting said storage circuitry to a data line, said memory comprising a plurality of sets of access control lines and corresponding data lines, each set of access control lines controlling one of said plurality of access control devices for each of said storage cells, said data lines each being coupled to a column of said storage cells and said access control lines each being coupled to a row of said storage cells; a plurality of data access ports; access control circuitry configured to assign each data access port to one of said sets of access control lines and corresponding data lines; said access control circuitry comprising collision detection circuitry configured to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port; said access control circuitry being configured to respond to said detected collision to assign said set of access control lines and corresponding data lines currently assigned to said first data access port to said second data access port and following completion of said data access request received at said first data access port to subsequently assign said first data access port to said set of access control lines and corresponding data lines previously assigned to said second data access port.