Patent ID: 9105637
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. An anti-fuse structure comprising: a first interconnect level comprising a first electrode embedded in a first dielectric layer, a top surface of the first electrode is substantially flush with a top surface of the first dielectric layer; a second interconnect level comprising a via embedded in a second dielectric layer above the first dielectric layer; a third dielectric layer in direct contact with and separating the first dielectric layer and the second dielectric layer, an entire top surface of the first electrode is in direct physical contact with a bottom surface of the third dielectric layer; and an interface between the first dielectric layer and the third dielectric layer extending from the top surface of the first electrode to the via, the interface comprising a length less than a minimum width of the via, wherein a bottom surface of the via is in direct physical contact with the first dielectric layer.