Patent ID: 8072808
Filing Date: 2011-12-06
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including at least one memory cell; an address storage section containing address information; an address judging section for judging whether an input address matches the address information in the address storage section and outputting a result of the judgment; and a control section for controlling a condition for writing or erasing data to or from the memory cell, wherein: the control section changes the condition for writing data to a memory cell of which address matched the address information in accordance with the output results from the address judging section, and data is written into said memory cell of which address matched the address information, by using the changed condition, or the control section changes the condition for erasing data from a memory cell of which address matched the address information in accordance with the output results from the address judging section, and data is erased from said memory cell of which address matched the address information, by using the changed condition.