Patent ID: 6434057
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A memory device comprising:a memory-array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each of the memory cells being coupled to a corresponding word line and a corresponding bit line and being used for storing one bit of data binary; a sense amplifier electrically connected to the memory array for sensing and amplifying data signals outputted from each of the memory cells to generate an output signal at a data output port of the sense amplifier; an output buffer electrically connected to the data output port of the sense amplifier for amplifying the output signal from the data output port, the output buffer comprising: a detector having an output terminal, the detector electrically connected to the data output port for producing a control signal at the output terminal according to the output signal from the data output port; and an amplifier electrically connected to the data output port and to the output terminal of the detector for amplifying the output signal from the data output port, the amplifier comprising: an input port electrically connected to the data output port for accepting the output signal from the data output port; and a control terminal electrically connected to the output terminal of the detector for a accepting the control signal from the detector to control operations of the amplifier; wherein when the detector produces the control signal and transmits the control signal to the control terminal of the amplifier, the amplifier begins amplifying the output signal transmitted from the data output port of the sense amplifier to the input port of the amplifier.