Patent ID: 9018773
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A chip arrangement comprising: a first chip carrier comprising a first chip carrier top side and a first chip carrier bottom side; a second chip carrier comprising a second chip carrier top side and a second chip carrier bottom side; a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; an electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; and one or more first electrically conductive portions and one or more second electrically conductive portions formed over the electrically insulating material, wherein the one or more first electrically conductive portions are formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side.