Patent ID: 6567336
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A semiconductor device for use with a memory cell, the semiconductor device comprising:a memory cell select control signal line configured to control a selection of the memory cell; and a transfer gate control circuit configured to either cut off or make a connection to the memory cell select control signal line in accordance with a set of voltages of a plurality of interface signals, wherein the transfer gate control circuit comprises a first NAND gate inputting the plurality of interface signals, a second NAND gate inputting a signal connectable to said memory cell select control signal line, a third NAND gate inputting an output of the first NAND gate, a fourth NAND gate inputting an output of the second NAND gate and formulating a latch circuit with the third NAND gate, and a fifth NAND gate inputting the output of the first NAND gate and an output of the fourth NAND gate and generating a transfer control signal.