Patent ID: 6862716
Filing Date: 2005-03-01
Classification: G06F

Abstract:
1. A method for designing interconnects of an LSI, comprising the steps of: preparing a netlist including a plurality of nets each specifying connection between two of terminals of circuit elements; performing a simulation for estimating a positive-component average current and a negative-component average current of each of said terminals; defining a graph including therein a set of nodes and a set of branches each connecting two of said nodes, said set of nodes including at least some of said terminals and branch points of at least some of said branches; nominating two of said nodes connected by a target branch selected from said at least some of said branches as a positive node and a negative node by using a fixed rule, and separating said at least some of said terminals by said target branch into a positive-node terminal set and a negative-node terminal set corresponding to said positive node and said negative node; calculating a first sum of said negative-component average currents of said terminals belonging to said positive-node terminal set and a second sum of said positive-component average current of said terminals belonging to said negative-node terminal set, to select a lower value of said first sum and said second sum as a positive-component average current of said target branch; calculating a third sum of said positive-component average currents of said terminals belonging to said positive-node terminal set and a fourth sum of said negative-component average currents of said terminals belonging to said negative-node terminal set, to select a lower value of said third sum and said fourth sum as a negative-component average current of said target branch; and designing a size of an interconnect corresponding to said target branch based on said positive-component average current and said negative-component average current of said target branch.