Patent ID: 7023945
Filing Date: 2006-04-04
Classification: H03L

Abstract:
1. A method for jitter reduction in a Phase Locked Loop (PLL) comprising: determining a strength of a first charge pump adequate to generate an appropriate first control voltage correction to a Voltage Controlled Oscillator (VCO) of a PLL based on receiving a single up signal or a down signal within one cycle of a PLL input reference clock; and generating N number of the up signal or the down signal to a second charge pump 1/N the strength of the first charge pump, the N number of the up signal or the down signal occurring within one cycle of the PLL input reference clock, wherein N is greater than one, wherein the second charge pump generates N second control voltage corrections each being 1/N the amplitude of the first control voltage correction generated by the first charge pump thus reducing glitches on the second control voltage corrections and reducing jitter to the VCO.