Patent ID: 8578193
Filing Date: 2013-11-05
Classification: G06F

Abstract:
1. An apparatus for optimizing performance and power consumption of a multi-core processor, comprising: a main controller; a multi-core processor including a plurality of cores, said multi-core processor being coupled to a clock source configured to provide a reference input clock frequency to said plurality of cores in said multi-core processor, each of said cores of said plurality of cores having a specification core frequency preset for said multi-core processor, and each of said cores of said plurality of cores being connected to separate supply voltage sources, the separate supply voltage sources being connected, in parallel, to said main controller and a voltage level-translating communication transceiver to allow individual adjustment of the separate supply voltage sources, by said main controller, for each of said cores of said plurality of cores; said supply voltage sources, wherein said plurality of cores having a respective operational core frequency that is proportional to said supply voltage provided by said respective supply voltage source; at least one PLL (Phase Locked Loop) having one or more voltage-controlled oscillators (VCOs) and one or more dividers, said at least one PLL being coupled to said multi-core processor and being configured to dynamically adjust said reference input clock frequency provided to a respective core of said plurality of cores to ensure that a respective operational core frequency of said respective core is at least equal to said reference input clock frequency; and said main controller coupled to said plurality of cores, said main controller being configured to collect core performance data and core power consumption data measured for said plurality of cores, said main controller being configured to adjust either said supply voltage provided by said supply voltage source connected to said respective core or being configured to adjust said reference input clock frequency provided to said respective core, wherein adjustment of either said supply voltage provided or said respective input clock frequency provided to said respective core optimizes a respective core performance and a respective core power consumption by said respective core, and wherein said main controller dynamically adjusts said supply voltage provided by said supply voltage source to said plurality of cores in real-time mode.