Patent ID: 8890603
Filing Date: 2014-11-18
Classification: G05F,H03K

Abstract:
1. An output circuit comprising: a current source and a first metal oxide semiconductor (MOS) transistor coupled in series between a high-potential power supply terminal and an output terminal; a second MOS transistor including a drain coupled to a backgate of the first MOS transistor; and a third MOS transistor including a source coupled to a source of the second MOS transistor, wherein backgates of the second MOS transistor and the third MOS transistor are coupled to the source of the second MOS transistor, and the backgates of the second MOS transistor and the third MOS transistor are in a floating condition, the first MOS transistor is an N-channel laterally diffused metal oxide semiconductor (LDMOS) transistor, each of the second MOS transistor and the third MOS transistor is a P-channel LDMOS transistor, and a drain of the third MOS transistor, and gates of the second and third MOS transistors are coupled to a low-potential power supply terminal.