Patent ID: 7447109
Filing Date: 2008-11-04
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a cell array including a plurality of memory cells; a circuit for executing a read/write access pipeline; a circuit for exercising control in such a manner that a write request and a write address are accepted in a cycle in which a read-out data signal from the cell array corresponding to an earlier accepted read request is output from a data terminal, and write data corresponding to the write request is accepted from the data terminal after the read data is output from said data terminal; a circuit for exercising control in such a manner that a write data signal corresponding to the write request is accepted from a data terminal in a cycle that follows a cycle in which the write request and a write address are accepted; and a circuit for exercising control in such a manner that a read request and a read address are accepted in a cycle the same as that in which the write-data signal is input, and read-out data corresponding to the read request is output from the data terminal after the write data is input from said data terminal.