Patent ID: 6768688
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells; a plurality of word lines to which voltages are applied to select the plurality of memory cells; a decoder for selecting one of the plurality of word lines based on an address signal representing an address of one of the plurality of memory cells to be accessed; a control circuit for outputting an activated control signal and an deactivated control signal according to a transition of the address signal; and a booster that has a plurality of booster circuits including first booster circuit and second booster circuit, said first and second booster circuits being connected to the decoder, performing a charging operation and supplying boosted voltage to a selected word line, wherein said first and second booster circuits are configured to perform the charging operation when receiving the deactivated control signal from the control circuit, and supply the boosted voltage to the selected word line when receiving the activated control signal from the control circuit, and the control circuit is configured to output the activated control signal and the deactivated control signal to said first and second booster circuits so that one of said first and second booster circuits performs the charging operation, while the other supplies the boosted voltage to the selected word line.