Patent ID: 7181659
Filing Date: 2007-02-20
Classification: G11C

Abstract:
1. A memory built-in self test (MBIST) apparatus for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic, the MBIST apparatus including: a finite state machine including a command generator and logic for incrementing data and addresses under test; a command scheduler in communication with the finite state machine, the command scheduler including resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters; a test memory storing subtests of an MBIST test, each of the subtests providing a full pass through a configured address range and providing information including subtest type, subcommand complement, address mode, data mode, and done bit; and a subtest pointer in communication with the test memory and the finite state machine, wherein the finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.