Patent ID: 6966020
Filing Date: 2005-11-15
Classification: G01R

Abstract:
1. A method of identifying faulty programmable interconnect resources of a field programmable gate array during normal on-line operation comprising the steps of: configuring said field programmable gate array into an initial self-testing area and a working area, said working area maintaining normal operation of the field programmable gate array; testing at least two groups of wires under test located within said self-testing area for faults; identifying a faulty group of wires under test from said at least two groups of wires under test having a faulty programmable interconnect resource therein; minimizing a region of said faulty group of wires under test containing said faulty programmable interconnect resource; identifying a wire within said faulty group of wires under test containing said faulty programmable interconnect resource; replacing programmable interconnect resources within said wire and said region with fault-free programmable interconnect resources for further testing in order to identify a wire segment, a configuration interconnect point, and/or a combination thereof which includes said fault.