Patent ID: 7266020
Filing Date: 2007-09-04
Classification: G06F,G11C,H03K

Abstract:
1. A multiple context memory cell configuration, comprising: a first pass gate coupled to receive a first data bit and adapted to pass the first data bit in response to a first address signal; a second pass gate coupled to receive the first data bit from the first pass gate and adapted to pass the first data bit in response to a configuration enable signal; a first latch coupled to receive the first data bit from the second pass gate and adapted to store the first data bit; and a first multiplexer coupled to the first latch and adapted to provide the first data bit as a first output of the multiple context memory cell configuration in response to a first level of the first address signal and adapted to provide a second data bit as the first output of the multiple context memory cell configuration in response to a second level of the first address signal.