Patent ID: 6721215
Filing Date: 2004-04-13
Classification: G11C

Abstract:
An integrated dynamic memory, comprising:a memory cell array having memory cells, each of said memory cells assigned to one of a plurality of cell groups, said plurality of cell groups divided into: defect-free groups having exclusively defect-free memory cells; and defective groups having at least one defective memory cell; a memory configuration table connected to said memory cell array and adapted to contain a list identifying said defect-free groups; and an assignment unit connected to said memory configuration table, said assignment unit programmed to execute memory accesses only to said memory cells of said defect-free groups based upon said list in said memory configuration table; said memory cell array having word lines and bit lines; said memory cells disposed at respective crossover points of one of said word lines and one of said bit lines; each of said plurality of cell groups having exactly one word line.