Patent ID: 6136679
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A method of forming a gate electrode by using very thin lithographic layers in a micro-patterning process comprising the steps of:providing a semiconductor substrate having active and passive regions defined therein;forming a gate oxide layer over said substrate;forming a conducting layer over said gate oxide layer;covering said conducting layer with a planarization layer wherein said planarization layer planarizes the surface of said substrate and also serves as a first hard mask;forming a bottom anti-reflective coating (BARC) layer over the surface of said planarization layer wherein said BARC layer also serves as a second hard mask;forming a thin photoresist layer over said BARC layer;exposing said thin photoresist layer to actinic light where said BARC layer prevents reflection of said actinic light from its surface and developing and patterning said thin photoresist layer with a gate pattern for said gatephotoresist layer with a gate pattern for said gate electrode to form a photoresist mask for forming said gate in said conducting layer;etching said BARC layer using said photoresist mask to form said second hard mask having said gate pattern in said BARC layer;etching said planarization layer using said second hard mask to form said first hard mask having said gate pattern in said planarization layer while simultaneously removing said photoresist mask;etching said conducting layer using said first hard mask having said gate pattern in said planarization layer to form said gate electrode in said conducting layer while simultaneously removing said second hard mask in said BARC layer; andremoving said planarization layer to complete the forming of said gate electrode.