Patent ID: 6285624
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A memory access control system comprising:(a) a memory system controller;(b) a plurality of memory system address-control lines;(c) a plurality of binary memory system data lines;(d) a plurality of multilevel memory system data lines;(e) a plurality of first multilevel-to-binary data signal converters;(f) a plurality of memory devices, each having a plurality of memory device address-control lines, a plurality of binary memory device data lines, a plurality of binary memory cells, and a plurality of first binary-to-multilevel data signal converters;wherein the memory controller generates memory address-control signals on the memory system address-control lines;wherein memory address-control signals on the memory device address-control lines are derived, at least in part, from the memory system address-control lines.wherein memory data from memory cells are selected by the memory device address-control lines and placed on the binary memory device data lines;wherein said first binary-to-multilevel data signal converters transform data signals from the binary memory device data lines to the multilevel memory system data lines;wherein said first multilevel-to-binary data signal converters transform data signals from the multilevel memory system data lines to the binary memory system data lines.