Patent ID: 6367046
Filing Date: 2002-04-02
Classification: G06F,H03M

Abstract:
An improved multi-bit error correction system for correcting an n times m bit data word, said correction system comprising:first means for dividing said n times m bit data word into m modules, each module having n bits; second parity generation means for combining the ith bit of each module to form a set of parity bits; third syndrome generation means for generating a number of syndrome bits from said parity bits; fourth means responsive to said syndrome generation means for locating multiple errors in said bits in said data word in accordance with a Hamming error detecting and correcting code and providing an indication of said located errors; and fifth means, including m parallel one bit decoders, for correcting said multiple errors in said bits in said data word in accordance with said Hamming error detecting and correcting code to provide corrected data bits.