Patent ID: 6711229
Filing Date: 2004-03-23
Classification: H03L

Abstract:
A method of synchronizing a phase-locked loop composed of, at least, a phase frequency comparator to output an up-clock or a down-clock having a pulse width or a number of pulses corresponding to a difference in an oscillation frequency between a reference clock and a frequency-divided clock, a charge pump to cause a control current to flow in or out in accordance with said up-clock or said down-clock, a low pass filter to smooth said control current and to output it as a control voltage, a voltage controlled oscillator to oscillate an internal clock having an oscillation frequency corresponding to said control voltage in accordance with set modulation sensitivity and a frequency divider to divide a frequency of said internal clock in accordance with a set multiplying factor and to output it as said frequency-divided clock, said method of synchronizing a phase-locked loop comprising a step of changing a value of said control current in accordance with said set modulation sensitivity and with said set multiplying factor.