Patent ID: 6906354
Filing Date: 2005-06-14
Classification: G11C,H01L

Abstract:
1. An array of planar T-RAM cells comprising: a plurality of T-RAM cells, said plurality of T-RAM cells being arranged in an array and fabricated over a substrate, each of said plurality of T-RAM cells including a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate having a body of a majority portion of single crystalline material using an n+ layer below it as seed material by a epitaxial lateral overgrowth technique, said horizontally stacked pseudo-TFT transfer gate including a source/drain and body, said thyristor being buried underneath said horizontally stacked pseudo-TFT transfer gate, wherein said horizontally stacked pseudo-TFT transfer gate covers at least a portion of said thyristor, and further wherein the top surface of said horizontally stacked pseudo-TFT transfer gate forms a co-planar top surface of each said horizontally stacked pseudo-TFT transfer gate of each said T-RAM cell,