Patent ID: 6730860
Filing Date: 2004-05-04
Classification: H01L,H05K,Y02P,Y10T

Abstract:
An electronic assembly comprising:a substrate having a plurality of layers, at least one of which is a power plane; a plurality of power vias in the substrate, having respective lower ends connected to the power plane at respective spaced apart locations, and respective upper ends; a power solder bump on an upper surface of the substrate having a height, a width and a length, the length being a multiple of the width, the upper ends of the power solder vias being connected to the power solder bump at respective spaced apart locations along the length of the power solder bump, so that the power solder vias connect the power solder bump in parallel to the power plane; a plurality of ground vias in the substrate having respective lower ends connected to the ground plane at respective spaced apart locations, and respective upper ends: and a ground solder bump on the upper surface of the substrate having a height a width and a length the length being a multiple of the width the upper ends of the ground solder vias being connected to the ground solder bump at respective spaced apart locations along the length of the ground solder bump so that the ground solder vias connect the ground solder bump in parallel to the ground plane, wherein the power and ground solder bumps are located directly adjacent one another, their lengths extending substantially parallel to one another so as to have surfaces facing one another to form a capacitor.