Patent ID: 7904614
Filing Date: 2011-03-08
Classification: G06F

Abstract:
1. A direct memory access controller comprising: a first programmable register programmable by an external device to store an address location value at which data transfers for a data transaction are to begin; a second programmable register programmable by the external device to store a value used to end data transfers of a single data transaction; a third programmable register programmable by the external device to store a value used to define how many data transactions are executed in a single multiple, consecutive data transaction cycle; a first temporary register; a second temporary register; a third temporary register; transfer control circuitry automatically executing multiple, consecutive data transactions using the values in the first, second, and third temporary registers, where the values in the first, second, and third temporary registers are updated during the execution of the multiple, consecutive data transactions, and where the values in the first, second, and third programmable registers are static during the execution of the multiple, consecutive data transactions; reset circuitry to transfer the address location value from the first programmable register to the first temporary register upon completion of a multiple, consecutive data transaction cycle, to transfer the value used to end data transfers of the single data transaction from the second programmable register to the second temporary register upon completion of the multiple, consecutive data transaction cycle, and to transfer the value used to define how many data transactions are executed in the single multiple, consecutive data transaction cycle from the third programmable register to the third temporary register upon completion of the multiple, consecutive data transaction cycle; and where the transfer control circuitry and reset circuitry cooperate to automatically continue execution of further multiple, consecutive data transaction cycles until receipt of a control signal from a device exterior to the direct memory access controller, where execution of each further multiple consecutive data transaction cycle begins with the transferred values stored in the first, second, and third temporary registers.