Patent ID: 6351501
Filing Date: 2002-02-26
Classification: H03M,H04L

Abstract:
An encoder circuit for DC-balanced transmission of digital signals over a transmission line, comprising:a) a counter circuit receiving an input word and a running word disparity (RWD), said counter circuit computing a single-word disparity (SWD) for said input word, and comparing said SWD to said RWD and for providing a first control signal indicating whether or not a sum of said SWD and RWD has a magnitude less than a magnitude of said RWD; and b) an inverter circuit receiving said first control signal and said input word from said counter circuit, said inverter circuit providing an output word, said output word comprising one of (i) a bit-wise complement of said input word and another bit indicating that a bit-wise complement operation was performed on said input word, when said first control signal indicates that said sum of said SWED and RWD has a magnitude less than the magnitude of said RWD, and (ii) said input word and another bit indicating that said bit-wise complement operation was not performed on said input word.