Patent ID: 9087777
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method for forming a semiconductor package comprising: providing a package substrate having first and second major surfaces, wherein the package substrate comprises a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate, wherein providing the package substrate comprises wherein the via contact comprises a width defined by circumference of the via contact; and forming further interconnect level of the package substrate which comprises forming a plurality of conductive studs directly coupled to and contact the via contacts by patterning the second and third conductive layers of the same conductive carrier, wherein a width of the conductive stud which is defined by circumference of the conductive stud is smaller than the width of the via contacts and the conductive stud is formed and contained within and does not extend beyond the width of the via contact; providing a die having conductive contacts on its first or second surface, wherein the conductive contacts of the die are electrically coupled to the interconnect structures; and forming a cap over the package substrate to encapsulate the die.