Patent ID: 7344966
Filing Date: 2008-03-18
Classification: H01L

Abstract:
1. A manufacturing method, comprising: forming, on a semiconductor substrate, first dielectric portions having a first thickness, each first dielectric portion having an upper surface; forming, on portions of said semiconductor substrate not covered by said first dielectric portions, a first dielectric layer thinner than said first dielectric portions; forming a conductive layer on said first dielectric layer and said first dielectric portions; forming a second dielectric layer on said conductive layer; anisotropically etching said second dielectric layer without a photolithographic pattern, the anisotropically etching step forming first dielectric spacers on side portions of the conductive layer; etching said conductive layer while using the first dielectric spacers as a mask, the etching said conductive layer forming, from the conductive layer, a first gate electrode having a top and a lateral edge substantially aligned with a lateral edge of one of the first dielectric spacers; and defining, between said first gate electrode and said substrate, second dielectric portions in said first dielectric layer, said second dielectric portions being in contact with said first dielectric portions, wherein defining the second dielectric portions includes etching the first dielectric layer using the first dielectric spacers as a mask, the defining the second dielectric portions resulting in each of the second dielectric portions having a lateral edge substantially aligned with a corresponding lateral edge of the first dielectric spacers.