Patent ID: 6480028
Filing Date: 2002-11-12
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of super-regions disposed on the programmable logic device in a two-dimensional array of intersecting rows and columns of such super-regions, each of said super-regions including a plurality of regions of programmable logic and a region of memory, each of said programmable logic regions including a plurality of subregions of programmable logic, each of the subregions of programmable logic having a plurality of inputs and an output and being programmable to perform any of several logic functions on its inputs to produce its output, and said memory region also having a plurality of inputs and a plurality of outputs and being responsive to its inputs to produce its outputs based at least in part on its inputs and data stored in the memory region; and programmable interconnection circuitry for selectively connecting said outputs of the memory region and said outputs of the programmable logic regions to said inputs of the memory region and said inputs of the programmable logic regions; wherein, for each of the multiplicity of subpluralities of said subregions of programmable logic in each of said super-regions, said programmable interconnection circuitry comprises: a plurality of local feedback conductors associated with that subplurality, each of the local feedback conductors that is associated with that subplurality extending substantially continuously adjacent to all of the subregions of programmable logic in that subplurality.