Patent ID: 6598154
Filing Date: 2003-07-22
Classification: G06F

Abstract:
Apparatus for reducing branch penalty in a processor, comprising:a branch predecode module for determining whether a branch instruction is predicted taken, wherein the branch predecode module comprises a length decode module for decoding the length of the instruction; a branch opcode detect module for decoding whether the instruction is a branch; and a detect taken branch module for determining whether the particular branch is predicted taken; an align stage in data communication relation with the branch predecode module, and receiving information indicating whether the branch is predicted taken therefrom; wherein the detect taken branch module comprises: a multiplexor connected to receive information input from the align stage and from the length decode module, the multiplexor selecting the prediction byte of the prediction marker corresponding to the length of the instruction; and an AND logic module connected to receive the selected prediction marker byte from the multiplexor, and to receive information as to whether the instruction is a branch from the branch opcode detect module.