Patent ID: 8482990
Filing Date: 2013-07-09
Classification: G11C

Abstract:
1. A circuit comprising: a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate; a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate; a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate; a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate; a third NMOS transistor having a third NMOS drain, a third NMOS source, and a third NMOS gate; and a fourth NMOS transistor having a fourth NMOS drain, a fourth NMOS source, and a fourth NMOS gate, wherein