Patent ID: 7972950
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device having a dual gate, the method comprising: forming, sequentially, a gate insulation layer, a first capping layer, and a barrier layer each across first and the second regions on a substrate; removing the first capping layer and the barrier layer from the first region to expose the gate insulation layer in the first region; forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region; thermally processing the substrate while the barrier layer remains on the first capping layer in the second region and the second capping layer remains on the barrier layer in the second region and on the gate insulation layer in the first region, such that material of the second capping layer spreads into the gate insulation layer in the first region, and material of the first capping layer spreads into the gate insulation layer in the second region: removing the second capping layer and the barrier layer from the second region, after the thermal processing of the substrate has been carried out, such that the gate insulation layer is exposed in the first and second regions; forming a gate electrode layer on the exposed gate insulation layer; and etching the gate electrode layer and the gate insulation layer to form a first gate in the first region and a second gate in the second region, and wherein the barrier layer is formed of material that prevents material of the second capping layer from spreading into the gate insulation layer in the second region during the thermal processing.