Patent ID: 8365042
Filing Date: 2013-01-29
Classification: G06F,H03M,H04L

Abstract:
1. A memory controller integrated circuit, comprising: a bidirectional link interface operable to transmit write data to a memory device and to receive read data from the memory device; encoder logic operable to compute a memory-controller-version of error-detection information for each of the write data and the read data; and a unidirectional link interface operable to receive a memory-device-version of error-detection information from the memory device for each of the write data and the read data; wherein the memory controller integrated circuit is operable to perform asymmetric error detection by comparing each memory-controller-version of error-detection information with a corresponding memory-device-version of error-detection information received via the unidirectional link interface, and by indicating an error condition in the event of mismatch.