Patent ID: 7352607
Filing Date: 2008-04-01
Classification: B82Y,G11C,Y10S

Abstract:
1. A structure comprising: an insulating layer on a top surface of a substrate; an electrically conductive bitline formed in said insulating layer or on a top surface of said insulating layer, a top surface of said bitline parallel to said top surface of said substrate; a first electrically conductive wordline having a bottom surface, a top surface, a first sidewall and an opposite second sidewall; a second electrically conductive wordline having a bottom surface, a top surface, a first sidewall and an opposite second sidewall, said top and bottom surfaces of said first and second wordlines parallel to said top surface of said bitline, said first and second sidewalls about perpendicular to said top surface of said bitline said first and second wordlines spaced apart, said first sidewall of said first wordline facing said first sidewall of said second wordline, said second sidewall of said first wordline facing away from said second sidewall of said second wordline; a dielectric layer between said bottom surfaces of said first and second wordlines and said top surface of said bitline; a dielectric first spacer on said first sidewall of said first wordline and a dielectric second spacer on said first sidewall of said second wordline, said first and second spacers separated by a gap, said first spacer abutting said gap and intervening between said first sidewall of said first wordline and said gap, said second spacer abutting said gap and intervening between said first sidewall of said second wordline and said gap, said top surface of said bitline exposed between said first and second spacers; at least one electrically conductive nanotube having a first end and an opposite second end, said first end permanently attached to said top surface of said bitline, said at least one nanotube extending away from said top surface of bitline in said gap between said dielectric first and second spacers; a first dielectric cap having a bottom surface, a top surface and a third sidewall, said bottom surface of said first dielectric cap in direct physical contact and coextensive with said top surface of said first wordline; a second dielectric cap having a bottom surface, a top surface and a fourth sidewall, said bottom surface of said second dielectric cap in direct physical contact and coextensive with said top surface of said second wordline, said third and fourth sidewalls facing each other, said first spacer extending over and in direct physical contact with said third sidewall and said second spacer extending over and in direct physical contact with said fourth sidewall; an electrically conductive third spacer on said first spacer and an electrically conductive fourth spacer on said second spacer, said third and fourth spacers spaced apart, said third and fourth spacers facing each other, a bottom surface of said third spacer facing and overhanging said top surface of said bitline exposed between said first and second spacers, and a bottom surface of said fourth spacer facing and overhanging said top surface of said bitline exposed between said first and second spacers; when an upper portion of said at least one nanotube proximate to said second end of said at least one nanotube is in contact with said first spacer, said second end of said at least one nanotube is positioned under but not touching a bottom surface of third spacer; and when said upper portion of said at least one nanotube proximate to said second end of said at least one nanotube is in contact with said second spacer, said second end of said at least one nanotube is positioned under but not touching said bottom surface of fourth spacer.