Patent ID: 6093606
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of forming a vertical transistor FET memory device comprising:forming an array of FET cells with rows and columns, with said rows being orthogonally arranged with respect to said columns, with said cells in a single row having a common source region and with said cells in a column having separate source regions,forming a set of trenches each having trench sidewalls and a trench bottom in a semiconductor substrate,performing a source connection implant with an anisotropic vertical implant of a first type of dopant to form source connection regions in said substrate at the bottoms of said trenches,forming threshold implant regions within said trench sidewalls with an angular ion implant of an opposite type of dopant for channel regions of FET cells,performing an anisotropic vertical implant of a first type of dopant forming doped drain regions near the surface of said substrate and forming doped source regions in said substrate below the bottoms of said trenches and below said source connection regions, with oppositely doped channel regions therebetween,forming a tunnel oxide layer over said substrate including said trenches,forming a thin floating gate layer of doped polysilicon over said tunnel oxide layer to the top of said trenches and extending above said trenches,etching back said floating gate layer leaving upright floating gate strips of said floating gate layer along the sidewalls of said trenches with all of said floating gate layer removed from said tunnel oxide layer centrally of said bottoms of said trenches above said source regions,forming an interelectrode dielectric layer over said floating gate strips and over said tunnel oxide layer,forming a blanket thick control gate layer of doped polysilicon over said interelectrode dielectric layer, andpatterning said control gate layer.