Patent ID: 8470707
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps: providing said integrated circuit that is partially formed with adjacent transistor gates and source and drain extensions self aligned to said adjacent transistor gates; depositing an etch stop layer over said adjacent transistor gates and over said source and drain extensions; depositing sidewall spacer dielectric material over said adjacent transistor gates and said etch stop layer; etching said sidewall spacer dielectric material to form adjacent sidewall spacers with a gap between bottoms of said adjacent sidewall spacers that is less than about 30 nm; implanting source and drain dopants self aligned to said sidewall spacers; removing a first portion of said two adjacent sidewall spacers with an etch to form adjacent reduced sidewall spacers where said gap is increased to greater than about 30 nm; annealing said integrated circuit and driving said source and drain dopants laterally under an edge of said reduced adjacent sidewall spacers to form source and drain regions; forming a silicide on said source and drain regions; and subsequently depositing a stressor layer.