Patent ID: 8067821
Filing Date: 2011-11-29
Classification: H01L

Abstract:
1. A semiconductor package comprising: a generally planar die paddle defining multiple peripheral edge segments; a plurality of first leads segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle; a plurality of second leads which each include first and second downsets formed therein in spaced relation to each other, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle; a plurality of third leads, at least some of which include a downset formed therein, the third leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle; a semiconductor die attached to the die paddle and electrically connected to at least one of each of the first second and third leads; and a package body defining opposed, generally planar top and bottom surfaces and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die paddle and the first and second leads are exposed in and substantially flush with the bottom surface of the package body, and at least portions of the second and third leads are exposed in and substantially flush with the top surface of the package body.