Patent ID: 6650159
Filing Date: 2003-11-18
Classification: G01R,G06F,H03K,H03L

Abstract:
A circuit comprising:a first array of selectable linear resistive elements, each of the linear resistive elements in the first array to receive a first input signal, each of the linear resistive elements in the first array having an output coupled to a first output signal line; a variable bandwidth-compensating circuit coupled to the first output signal line to compensate the bandwidth of a first output signal on the first output signal line, the variable bandwidth-compensating circuit including a first number of selectably enableable, parallel-coupled capacitive elements; a second array of selectable linear resistive elements, each of the linear resistive elements in the second array to receive a second input signal, the second input signal being out of phase with the first input signal, each of the linear resistive elements in the second array having an output coupled to the first output signal line, the first output signal on the first output signal line being an interpolated output signal; and a phase detection circuit to receive the first output signal and a second output signal, the phase detection circuit to provide a select signal responsive to a phase difference between the first and second output signals, the select signal to determine a number of capacitive elements to be enabled in the variable bandwidth-compensating circuit.