Patent ID: 7382055
Filing Date: 2008-06-03
Classification: H01L

Abstract:
1. A layer in the back end of the line of a multi-layer integrated circuit comprising a set of dual-damascene interconnects and at least one resistor: a lower layer having at least one lower metal interconnect and a lower ILD top surface; a first ILD layer having a first ILD thickness and a first ILD top surface on said lower ILD top surface; a resistor formed on said first ILD top surface having a resistor thickness and a resistor top surface and comprising at least a resistive layer and an etch-resistant resistor top cap layer above said resistive layer; a second ILD layer having a second ILD thickness substantially equal to said resistor thickness and planarized to said resistor top surface; a third ILD layer formed on said second ILD layer; a set of dual-damascene interconnects for making contact to at least some of said lower metal interconnects and a set of resistive contact members for making contact with said resistor in said third ILD layer, said set of resistive contact members extending through said resistor cap layer, whereby the bottom of said resistive contact apertures makes direct contact with said resistive layer.