Patent ID: 6012833
Filing Date: 2000-01-11
Classification: G06F,H01L

Abstract:
A method of manufacturing an integration circuit device, comprising the steps of:generating logic library data with respect to a macro that includes a macro core having a predetermined function and boundary cells positioned near input and output terminals of the macro core, wherein an input terminal is connected to a plurality of first cells of the macro core, or the input or output terminals of the macro core are connected to a first cell of the macro core via a substantial delay line, said logic library data including delay characteristic data of the boundary cells given as attribute data to input and output terminals of the macro;designing a logic circuit having at least a plurality of second cells and said macro, said plurality of second cells being connected to the input and output terminals of the macro so as to be connected to the input and output terminals of the macro core through the boundary cells;calculating a delay time of the macro based on said delay characteristic data with respect to the designed logic circuit; andeffecting a logic simulation of the designed logic circuit based on the calculated delay time.