Patent ID: 6756833
Filing Date: 2004-06-29
Classification: H03H

Abstract:
A delay signal generation circuit comprising:a first delay circuit, having a plurality of delay elements connected in series, for delaying a reference signal input thereto and for outputting the delayed reference signal; a second delay circuit, having a plurality of delay elements connected in series, for delaying a signal input thereto and for outputting the delayed input signal; detection means for detecting, in response to the reference signal applied to said first delay circuit, a number of delay elements of said first delay circuit which are in a given state after a lapse of a predetermined time interval; a selection means for storing correspondency data between the number of delay elements of said first delay circuit which is detected by said detection means, and one delay element of said second delay circuit which is to be selected, and for selecting any delay element from among the plurality of delay elements of said second delay circuit based on the correspondency data; and setting-changing means for setting and changing the correspondency data stored in said selection means.