Patent ID: 6525974
Filing Date: 2003-02-25
Classification: G11C

Abstract:
An integrated memory, comprising:two normal read amplifiers; first switching elements having control inputs; normal bit lines combined into at least two individually addressable normal columns, at least one of said normal bit lines from each of said normal columns connected to one of said normal read amplifiers through a respective one of said first switching elements, said control inputs of all of said first switching elements of a respective one of said normal columns connected to one another in order to receive a common column selection signal; data lines for transferring data to and from outside the integrated memory, at least one of said data lines connected to one of said normal read amplifiers; two redundant read amplifiers; second switching elements having control inputs connected to one another in order to receive a common redundant column selection signal; and redundant bit lines combined into one individually addressable redundant column, at least one of said redundant bit lines connected to one of said redundant read amplifiers through a respective one of said second switching elements, said redundant read amplifiers and said redundant column provided for replacing said two normal read amplifiers and one of said normal columns, respectively, if defective.