Patent ID: 8614132
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A method comprising: providing a semiconductor substrate; forming a gate structure over the substrate; performing a first implantation process with a first dopant on the substrate, thereby forming a lightly doped source and drain (LDD) region in the substrate, the LDD region being interposed by the gate structure; performing a second implantation process with a second dopant on the substrate, the second dopant being opposite the first dopant, thereby forming a doped region in the substrate, the doped region being interposed by the gate structure and spaced a distance from the gate structure; and after performing the first and second implantation processes, forming source and drain features on each side of the gate structure, wherein forming source and drain features on each side of the gate structure includes performing a combination dry etching process and wet etching process to the semiconductor substrate to form recesses interposed by the gate stack.