Patent ID: 6434689
Filing Date: 2002-08-13
Classification: G06F

Abstract:
Apparatus comprising:a) a data processing unit including 1) a register file having registers, 2) a memory, 3) a first bus coupling said register file with said memory, 4) a plurality of execution units, 5) a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from said memory, a decode stage for decoding an operational code from said instruction, an execution stage for activating one of said execution units, and a write-back stage for writing back from said execution unit; b) a coprocessor; c) a coprocessor interface for coupling said coprocessor with said data processing unit; d) a second bus including read-lines coupling said register file with said plurality of execution units and said coprocessor; e) a third bus including write-lines couplings said register file with said plurality of execution units and said coprocessor, the second and third buses exchanging operands between said registers and said plurality of execution units and between said registers and said coprocessor; f) at least one control line from said coprocessor to said pipeline configuration for indicating that said coprocessor is busy; and g) a plurality of control lines from said decode stage in said data processing unit to said coprocessor to provide said operational code to said coprocessor, the plurality of control lines operated upon detection by the decode stage that the instruction is a coprocessor instruction; h) whereby said coprocessor uses said registers from said register file during execution of a coprocessor instruction.