Patent ID: 6097255
Filing Date: 2000-08-01
Classification: H03L

Abstract:
A phase-locked loop circuit for locking the phase of an input signal to the phase of an input reference signal, comprising:a phase comparator for comparing the phase of the input reference signal to the phase of the input signal wherein the input reference signal and the input signal are clocked by an independent pre-set clock signal, said phase comparator includingfirst detection means for detecting a rising portion of reference data from the input reference signal andsecond detection means for detecting a rising portion of input data from the input signal wherein each of said first and second detection means include a first logic circuit for storing and outputting said reference and input data, respectively, responsive to the inputting of the clock signal, a second logic circuit for storing and outputting output data of said first logic circuit responsive to the inputting of the clock signal, a third logic circuit for storing and outputting output data of said second logic circuit responsive to the inputting of the clock signal and a fourth logic circuit outputting a positive state output if the state of output data of the second logical circuit and the state of a complemented version of output data of said third logic circuit are both positive.