Patent ID: 6665360
Filing Date: 2003-12-16
Classification: H03L,H03M

Abstract:
An apparatus comprising:a first circuit configured to generate (i) one or more first control signals, (ii) one or more second control signals, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal; a first serialization element configured to generate one or more intermediate data signals operating at a second speed in response to (i) said one or more first control signals, (ii) said one or more first clock signals and (iii) said first data signal; and a second serialization element comprising a multiplexer configured to generate an output data signal operating at a third speed in response to (i) said one or more second control signals and (ii) said one or more intermediate data signals operating at a second speed.