Patent ID: 7872987
Filing Date: 2011-01-18
Classification: H04L

Abstract:
1. An apparatus that divides roles in generating test packets for high packet volume tests between a general purpose processor and a configurable logic device, including: a microprocessor with a first memory; a programmable logic device with a second memory, wherein the programmable logic device is coupled to the first memory by at least a local bus; a physical port coupled to the test packets being dispatched from the physical port; wherein the microprocessor comprises: wherein the programmable logic device comprises: circuitry that retrieves the list via at least the local bus into the second memory; circuitry that retrieves the test packet ingredients and the test packet recipes according to the list, via at least the local bus into the second memory; circuitry that generates test packets that combine the test packet ingredients according to the test packet recipes and customizes test packets with the modifier ingredient, and adding timestamps; and circuitry that dispatches the test packets via the physical port according to the timestamps.