Patent ID: 8000432
Filing Date: 2011-08-16
Classification: G11C

Abstract:
1. A shift register comprising: a plurality of first flip-flops, each having a first master latch and a first slave latch, each of which is composed of a transistor with a first transistor size; a plurality of second flip-flops, each having a second master latch and a second slave latch, each of which is composed of a transistor with a size smaller than the first transistor size; a first transmission path which includes a transistor with the first transistor size and through which a master clock to be supplied to the first master latches is transmitted and a second transmission path which includes a transistor with the first transistor size and through which a slave clock to be supplied to the first slave latches is transmitted, the first and second transmission paths being provided for the plurality of first flip-flops; a third transmission path which includes a transistor with the second transistor size and through which the master clock is transmitted and a fourth transmission path which includes a transistor with the second transistor size and through which the slave clock is transmitted, the third and fourth transmission paths being provided for the plurality of second flip-flops; and a transfer portion configured to transfer pieces of data held in the plurality of second flip-flops to the first slave latches of the plurality of first flip-flops.