Patent ID: 7904695
Filing Date: 2011-03-08
Classification: G06F,Y02D

Abstract:
1. A computer, comprising: a processor for executing a plurality of instructions from an instruction area; and a sequencer for providing a pulse to advance from a presently executed instruction to a next instruction of said plurality of instructions; wherein each of said plurality of instructions includes a bit for providing an input to the sequencer such that the sequencer is triggered into providing the pulse when the bit is set; said computer is one of an array of computers integrated on a single chip; when said bit for providing the input to the sequencer is not set then the sequencer is not triggered into providing the pulse; when said bit for providing the input to the sequencer is not set then a first communications status line is set between the computer and a second computer; the sequencer includes a ring oscillator having an odd number of inverting logic elements connected in a ring; the sequencer has a first input terminal operative to trigger the sequencer into providing the pulse responsive to the bit being set; and the sequencer has a second input terminal operative to trigger the sequencer into providing the pulse responsive to an acknowledgment signal indicating completion of a communication between the computer and a second computer on the chip.