Patent ID: 7721077
Filing Date: 2010-05-18
Classification: G06F

Abstract:
1. A processor comprising: a processing unit to retrieve a data unit of a first endian format; an endian conversion logic coupled to the processing unit to convert the data unit from the first endian format to a second endian format based on the status of a endian toggle register control bit; and an endian toggle register coupled to the endian conversion logic to store the data unit, wherein the endian conversion logic is to convert the second endian format of the data unit stored in the endian toggle register to the first endian format before storing the data unit in a first memory, wherein the endian conversion logic is to store the data unit of the second endian format in an endian toggle disabled register, wherein the second endian format of the data unit is preserved if the data unit is stored in the endian toggle disabled register, wherein the processing unit is to support an endian storage class, and wherein the processing unit causes endian conversion to be performed on a pre-specified variable of the endian storage class before storing the pre-specified variable in the endian toggle register.