Patent ID: 8898368
Filing Date: 2014-11-25
Classification: G06F,G11C

Abstract:
1. A memory module, comprising: a plurality of dynamic random access memory (DRAM) chips, each DRAM chip having one or more data input/output (D/Q) terminals, each of said D/Q terminals having an associated load such that said DRAM chips present a plurality of loads, each of said D/Q terminals conveying data; and data redriving/retiming circuits connected between a system memory bus and the D/Q terminals of the plurality of DRAM chips such that data is written from said system memory bus to said DRAM chips in parallel and is read from said DRAM chips and conveyed to said system memory bus in parallel via said data redriving/retiming circuits; wherein the data redriving/retiming circuits provide isolation between said system memory bus and the D/Q terminals of the DRAM chips, thereby isolating said system memory bus from said plurality of loads associated with said plurality of DRAM chips; and wherein the data redriving/retiming circuits comprise: