Patent ID: 6029244
Filing Date: 2000-02-22
Classification: G06F

Abstract:
An execution unit in a microprocessor for executing a first instruction, wherein an encoded representation of said first instruction includes an opcode field, a first operand field, and a second operand field, said execution unit comprising:a first input register coupled to receive a first operand specified by a value of said first operand field;a second input register coupled to receive a second operand specified by a value of said second operand field;a comparator unit coupled to receive said first operand from said first input register and said second operand from said second input register, and wherein said comparator unit is coupled to receive a decoded opcode value of said opcode field on a decoded opcode bus;a multiplexer coupled to receive a plurality of inputs including said first operand from said first input register, said second operand from said second input register, a first constant value, and a second constant value, and wherein said multiplexer is configured to select one of said plurality of inputs to be conveyed as a result of said first instruction in response to receiving one or more control signals from said comparator unit;and wherein said comparator unit is configured to generate said one or more control signals in response to receiving said decoded opcode value, and wherein, if said decoded opcode value indicates that said first instruction is one of a plurality of extreme value instructions, said one or more control signals are usable to select either said first operand or said second operand as said output value, and wherein, if said decoded opcode value indicates that said first instruction is one of a plurality of compare instructions, said one or more control signals are usable to select either said first constant value or said second constant value as said output value.