Patent ID: 8982641
Filing Date: 2015-03-17
Classification: G11C

Abstract:
1. A memory erasing method, configured for selectively erasing a plurality of cells of a row of a block of a bank, the memory erasing method comprising the steps of: setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of each cell in any unselected block in a selected bank to be floating; supplying a positive voltage to sources of all the cells in a selected bank and a shared P well and N well; and supplying a negative voltage to the gates of the cells which are selected to be erased and located at the row of the selected block wherein the method is implemented by a driving circuit, applicable to a NOR flash memory, the driving circuit comprising pairs of neighboring banks, wherein a main driving circuit is disposed in two neighboring blocks of a pair of banks, and a secondary driving circuit is disposed in two neighboring blocks of other pairs of banks, the secondary driving circuit comprising: an extension second local word line driver for receiving a plurality of global word line signals and reverse global word line signals thereof generated from the main driving circuit and generating a voltage to be supplied to a word line of the two blocks adjacent to the extension second local word line driver; and a second bit line driving circuit for driving a bit line of the two blocks adjacent to the extension second local word line driver.