Patent ID: 7948036
Filing Date: 2011-05-24
Classification: H01L

Abstract:
1. An ESD protection circuit configured to introduce a substrate-biased effect, formed on a P-type semiconductor substrate, for I/O pin protection against both positive and negative ESD stress conditions, comprising: a first P-type well formed on the P-type semiconductor substrate, not hard-wired to VSS but shorted to VSS through the P-type semiconductor substrate; a second P-type well formed on the P-type semiconductor substrate hard-wired to VSS; multi-finger nMOS transistors formed on the first P-type well comprising source regions, hard-wired to VSS, drain regions, hard-wired to an I/O pad, and gate regions, hard-wired to VSS; a N-type well ring formed on the P-type semiconductor substrate, hard-wired to the I/O pad, and disposed between the first P-type well and the second P-type well, wherein the first P-type well is isolated from the second P-type well; a pMOSFET formed on the P-type semiconductor substrate, comprising a source node, connected to the I/O pad, a drain node, connected to a P-type diffusion ring formed on the first P-type well, and a gate node, connected to VDD; wherein the P-type diffusion ring is formed on the first P-type well, hard-wired to a drain node of the pMOSFET, not hard-wired to VSS, but shorted to VSS through the P-type semiconductor substrate.