Patent ID: 6198686
Filing Date: 2001-03-06
Classification: G11C

Abstract:
A memory device including a word decoder, said word decoder comprising:a word decoding circuit having an output to provide a set signal in response to a predecoded row-address signal; anda latch circuit coupled between said output of said word decoding circuit and one of word lines in a memory cell array,wherein said latch circuit comprises:a PMOS transistor and an NMOS transistor connected in series between first and second power source potentials;a first MOS transistor connected in parallel to one of said PMOS transistor or said NMOS transistor; anda second MOS transistor connected in series to the other of said PMOS transistor or said NMOS transistor, said second MOS transistor being operated in such a way that the on/off states of said first and second MOS transistors are reverse to each other.