Patent ID: 6597621
Filing Date: 2003-07-22
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory blocks, arranged in alignment in a row direction, each including word lines arranged extending in said row direction; a plurality of internal data buses provided for each respective memory block and arranged in a column direction perpendicular to said row direction; sub access circuits, provided corresponding to the respective memory blocks, each activated individually for selecting a word line and for making a data access to a memory cell in a corresponding memory block; control circuitry, provided commonly to said plurality of memory blocks, for controlling an access to the memory blocks in accordance with a mode selection signal instructing an operation mode, said control circuitry controlling the access on a memory block basis, in which memory blocks are activated independently from each other for selecting a word line and data access is made to a selected memory block in a first mode instructed by said mode selection signal, and controlling the access to the memory blocks commonly to the memory blocks in a second mode instructed by said mode selection signal, in which a word line is selected in each memory block at a time and data access is made to the memory blocks commonly; a plurality of data nodes, arranged in a multi-bit width equal in width to each of the internal buses, coupled to a device outside of said semiconductor memory device; and a plurality of bus selection circuits provided corresponding to said plurality of internal data buses respectively, for changing a correspondence in connection between said plurality of data nodes and corresponding internal data buses according to said mode selection signal.