Patent ID: 8145862
Filing Date: 2012-03-27
Classification: G07B

Abstract:
1. An arrangement for data processing in a franking machine, comprising: a secure housing that protects against unauthorized penetration into an interior of said secure housing; a circuit board in said interior of said secure housing; a data processor in said interior of said secure housing; a security module inserted in said circuit board and connected to the data processor in said interior of said secure housing that implements security-relevant services associated with franking using security data; a first memory entirely in said interior of said secure housing contained in a semiconductor package permanently mounted on said circuit board in order to be in permanent communication with the data processor and said data processor being configured to store user data a first time in said first memory, said user data being predetermined by a user and being different from said security data; and a second memory contained in a semiconductor package, separate from the semiconductor package in which said first memory is contained, entirely in said interior of said secure housing, said semiconductor package containing that contains said second memory being only temporarily mounted on a circuit board in order to be only in temporary communication with the data processor, said data processor being configured to store said user data in the second memory a second time as backup data for the user data stored in said first memory, with said user data being stored simultaneously in said first and second memories, said semiconductor package containing second memory being installed in said interior of said secure housing so as to be readily removable intact, with said backup data stored therein, from said interior of said security housing, upon authorized access to said interior of said security housing; said first memory having a first identification ID said second memory having a second identification ID said security module having a third identification ID said first memory having a fourth identification ID said second memory having a fifth identification ID said data processor being configured to update data in said second memory by transferring data from said first memory into said second memory when ID