Patent ID: 6087869
Filing Date: 2000-07-11
Classification: H03L,H04L

Abstract:
A digital PLL circuit for recovering a clock signal from an analog baseband signal whose frequency band is limited due to removal of high-frequency components, having an A/D converter for sampling the baseband signal according to the recovered clock signal, a phase comparator for detecting a phase difference between the output of the A/D converter and the recovered clock signal, a loop filter for integrating the phase difference, and a voltage-controlled oscillator (VCO) for changing the oscillation frequency of itself in response to the output of the loop filter and providing the recovered clock signal, the phase comparator comprising:means for determining whether or not the baseband signal has crossed a transition level;means for determining whether or not a time difference between a sampling point and a transition-level crossing point of the baseband signal is equal to or smaller than a threshold; andmeans for providing the loop filter with a control value for a period of the recovered clock signal after a determination is made, the control value corresponding to the time difference if the determination is that the baseband signal has crossed the transition level and the time difference is equal to or smaller than the threshold, and the control value keeping the preceding value if the determination is that the baseband signal has not crossed the transition level or the time difference is larger than the threshold.