Patent ID: 6762622
Filing Date: 2004-07-13
Classification: H03K

Abstract:
An output buffer circuit for excessive voltage protection, comprisinga pull-up transistor having a drain connected to an external voltage source, a source connected to an I/O node and a gate connected to a data out through a voltage-boosting node; a boost transistor having a drain connected to said external voltage source, and a source connected to said voltage-boosting node; a boost-controlling circuit having an input connected to said I/O node and an output connected to a gate of said boost transistor, said input of said boost-controlling circuit sensing an excessive voltage at said I/O node and said output of said boost-controlling circuit sending a signal to turn on said boost transistor, a gate voltage of said pull-up transistor being sustained to a predetermined high level when said pull-up transistor is turned off, a voltage difference between said gate voltage and a source voltage of said pull-up transistor being reduced.