Patent ID: 6501701
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array having first and second ports; a first row of sense amplifiers, which is associated with the first port; a second row of sense amplifiers, which is associated with the second port; a selector for selecting either the first or second port, through which burst data should be transferred, responsive to a port selection signal, the selector coupling either the first or second row of sense amplifiers, which is associated with the selected one of the first and second ports, to a data input circuit or a data output circuit; and a refresh control circuit for providing a refresh command to the first and second rows of sense amplifiers, wherein if the selector has selected the first port, a refresh operation on the memory array is performed in response to the refresh command using the second row of sense amplifiers, and wherein if the selector has selected the second port, the refresh operation on the memory array is performed in response to the refresh-command using the first row of sense amplifiers.