Patent ID: 8237143
Filing Date: 2012-08-07
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array including a plurality of memory cells, a plurality of bit lines each commonly connecting one ends of plural memory cells arranged in a first direction of the cell array, and a plurality of word lines each commonly connecting the other ends of plural memory cells arranged in a second direction of the cell array; and a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays, wherein the read/write circuit comprises: a bit line select circuit disposed around at least one side of first and second boundaries that define a cell array layout region of the semiconductor substrate in the first direction, to which the respective bit lines are connected for selecting the bit lines; a sense amp array including a plurality of sense amps for sensing data of bit lines selected by the bit line select circuit and disposed between the bit line select circuit and a central portion of the cell layout region in the first direction; a word line select circuit disposed around one side of third and fourth boundaries that define the cell array layout region of the semiconductor substrate in the second direction, to which the respective word lines are connected for selecting the word lines; and a write circuit for generating write pulses supplied to selected memory cell and disposed around the other side of the third and the fourth boundaries of the cell array layout region of the semiconductor substrate.