Patent ID: 7020007
Filing Date: 2006-03-28
Classification: G11C

Abstract:
1. A non-volatile SRAM including a plurality of unit memory cells arranged in an array, wherein each of the plurality of unit memory cells comprises: an SRAM unit including first and second transistors which are cross-coupled, a data true node to which a control electrode of the first transistor and a drain electrode of the second transistor are connected, and a data complement node to which a control electrode of the second transistor and a drain electrode of the first transistor are connected; and a non-volatile circuit including first and second storage transistors connected to the data true node and the data complement node, respectively, the first and second storage transistors being switched in response to a change in state of power supplied to the SRAM unit, first and second data storage elements respectively connected to the first and second storage transistors to respectively store data from the data true node and the data complement node in response to interruption of the power supplied to the SRAM unit, and first and second data recall transistors respectively connected to the first and second data storage elements, the first and second data recall transistors being switched to respectively recall the data stored in the first and second data storage elements in response to supply of power to the SRAM unit, wherein a thickness of gate insulation films of the first and second recall transistors is thinner than a thickness of gate insulation films of the first and second storage transistors.