Patent ID: 8477534
Filing Date: 2013-07-02
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: first and second select gate transistors; memory cell units each including memory cells connected in series between the first and second select gate transistors; a source line connected to the first select gate transistors; bit lines connected to the second select gate transistors, respectively; a selected word line which is connected to a selected memory cell as a target of a verify read among the memory cells; a non-selected word line which is connected to a non-selected memory cell except the selected memory cell among the memory cells; sense amplifiers including a sense node connected to the bit lines, respectively; a control circuit; and a potential generating circuit; wherein the control circuit supplies a selected read potential to the selected word line, and a non-selected read potential larger than the selected read potential to the non-selected word line, after that the control circuit supplies a bit line voltage to the bit lines at a first time, the sense amplifiers detect the sense node at a second time and a third time while the bit line voltage to the bit lines is maintained by the control circuit, the control circuit maintains the bit line voltage to the bit lines when a voltage of the sense node is larger than a first voltage at the third time, and the control circuit decreases the bit line voltage to the bit lines when the voltage of the sense node is smaller than the first voltage at the third time.