Patent ID: 6438570
Filing Date: 2002-08-20
Classification: G06F,H03H

Abstract:
A bit-serial multiplier implemented on an FPGA, comprising:a function generator configured as a multiplicand memory and having address inputs and a data output; a function generator configured as a multiplier memory and having address inputs and a data output; one or more function generators configured as a product memory, the product memory having address and data inputs and a data output; a 2's complement 1Ã—1 bit multiplier implemented with at least two function generators and having inputs coupled to data outputs of the multiplicand and multiplier memories; a 1Ã—1 bit adder implemented with at least two function generators and having a first input coupled to the output of the bit-serial multiplier, a second input coupled to the data output of the product memory, and an output coupled to the data input of the product memory; and a control circuit arranged to address the multiplicand, multiplier, and product memories.