Patent ID: 6765833
Filing Date: 2004-07-20
Classification: G11C

Abstract:
An integrated circuit device, comprising:first and second complementary data line pairs disposed on a substrate and extending along a first direction, the first and second complementary data line pairs arranged such that first and second data lines of the first complementary data line pair have a first data line of the second complementary data line pair disposed therebetween; an equalization transistor comprising respective first and second source/drain regions in the substrate that are coupled to respective ones of the first and second data lines of the first complementary data line pair and an equalization transistor gate electrode disposed on the substrate between the first and second data lines of the first complementary data line pair; a first precharge transistor comprising the first source/drain region, a third source/drain region in the substrate displaced from the first source/drain region along the first direction, and a first precharge transistor gate electrode disposed on the substrate between the first and third source/drain regions; and a second precharge transistor comprising the second source/drain region, a fourth source/drain region in the substrate displaced from the second source/drain region along the first direction, and a second precharge transistor gate electrode disposed on the substrate between the second and fourth source/drain regions; and a precharge voltage bus conductor on the substrate and electrically coupled to the third and fourth source/drain regions.