Patent ID: 6028793
Filing Date: 2000-02-22
Classification: G11C

Abstract:
A driving circuit for a row decoding circuit in a monolithically integrated non-volatile memory cell matrix memory device, having an input terminal for connection to the row decoding circuit and an output terminal for coupling to a selected word line of said memory cell matrix, comprising:a first field-effect transistor with a first type of conductivity and having first and second terminals, a control terminal which is connected to a bias voltage generator, and a body terminal which is connected to the first terminal, the second terminal of said first transistor being connected to the input terminal of the driving circuit;second and third field-effect transistors whose conductivities are respectively the same as and the opposite to the conductivity of the first transistor, each having first and second terminals and a control terminal which is connected to the input terminal of the control circuit, the respective first terminals of the second and third transistors being connected respectively toe a first voltage reference and a second reference voltage and the respective second terminals of the second and third transistors being connected to each other, the second transistor having a body terminal connected to its own first terminal, wherein the first terminal of the first transistor is connected to a body bias line of the memory device.