Patent ID: 6248666
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A process of manufacturing a a field effect transistor having a double-recessed gate with a central recess (A.sub.6) at a relatively deep level and a peripheral recess (A.sub.5) at a relatively shallow level, and a gate electrode (G) deposited so as to cover the entire central recess and extend continuously over a portion of the peripheral recess, said process comprising, for realizing said field effect transistor, the following steps:a) forming a stack of layers comprising, on a substrate (1), an active layer (3) of semiconductor material and a first dielectric layer (D.sub.1),b) covering the first dielectric layer (D.sub.1) with a second dielectric layer (R) having different etching properties, forming an aperture (A.sub.0) in the second dielectric layer (R) having a first width, then forming a first opening (A.sub.1) in the first dielectric layer (D.sub.1) having a same first width, while enlarging said aperture (A.sub.0) in the second dielectric layer ( R) to form a second opening (A.sub.2) having a second width, and then etching a preliminary recess (A.sub.4) in the subjacent layer of semiconductor material delimited by said first opening (A.sub.1) having said first width,c) enlarging said first opening (A.sub.1) in the first dielectric layer (D.sub.1) to form a third opening (A.sub.3) having a third width larger than the second width of the second opening (A.sub.2) of the second dielectric layer (R), and then etching the semiconductor layer through said preliminary recess (A.sub.4) to form relatively deep central recess (A.sub.6) having substantially said first width while etching said relatively shallow peripheral recess (A.sub.5) having substantially said third width of said third opening (A.sub.3) of the first dielectric layer (D.sub.1),d) depositing a gate metal material (8) onto said relatively deep central recess (A.sub.6), said material (8) extending over said peripheral recess substantially according to said second width of said second opening (A.sub.2) of said second dielectric layer (R).