Patent ID: 6216259
Filing Date: 2001-04-10
Classification: G06F

Abstract:
A method for configuration of a programmable logic device that is coupled to a processor using a library that comprises logic core generators and one or more router core generators, each of the logic and router core generators including code that is executable and embodies design information, comprising the steps of:executing a program on the processor, the program including instructions that reference selected ones of the logic core generators for functions to be provided by the programmable logic device;generating by one or more of the logic core generators in response to the program, logic core definitions that define at least two logic cores;generating by the router generators in response to the program, at least one router core definition that defines a coupling of the logic cores in the programmable logic device;generating programming bits from the logic core definitions and router core definition in response to the program; andloading the programmable logic device with the programming bits in response to the program.