Patent ID: 9117909
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A non-planar transistor, comprising: a substrate having an active region and an isolation region, wherein the isolation region encompasses the active region; a plurality of shallow trenches disposed in the substrate in the active region, wherein a portion of the substrate between each two shallow trenches is defined as a protruding structure, and the protruding structure has an upper portion having a substantially vertical sidewall and a lower portion having a tilted sidewall; a deep trench disposed in the substrate in the isolation region, wherein the deep trench is deeper than the shallow trenches and has a shoulder portion; an insulation layer disposed in the shallow trenches and the deep trench, wherein an upper surface of the insulation layer in the shallow trenches is level with that in the deep trench; a portion of the protruding structure that protrudes over the insulation layer defined as a fin structure; a conductive layer disposed on the fin structure; and a gate dielectric layer disposed between the fin structure and the conductive layer.