Patent ID: 8773932
Filing Date: 2014-07-08
Classification: G11C

Abstract:
1. A built-in self-test (BIST) circuit for a memory controller, the memory controller comprising a core circuit and an I/O port, the core circuit outputting a reset signal, a serial output signal and a serial enable signal, the I/O port comprising an output driver, the BIST circuit comprising: a detecting unit, having a first input terminal for receiving the serial output signal, a second input terminal for receiving the serial enable signal, and an output terminal for generating a detection signal a flag unit, for receiving the detection signal to generate a flag signal; and a selecting unit, for receiving the serial output signal, the serial enable signal and the flag signal; wherein, when the reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to an input terminal and an enable terminal of the output driver, respectively; when the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship, and the selecting unit transmits the flag signal to the input terminal of the output driver.