Patent ID: 6754814
Filing Date: 2004-06-22
Classification: G06F

Abstract:
An instruction processing apparatus, comprising:a pipeline instruction execution unit fetching and executing an instruction from a cache memory; a pipeline instruction execution control unit independent of said pipeline instruction execution unit controlling the pipeline instruction execution unit by a microprogram read from a microprogram storage; a halt unit halting a request for reading a subsequent instructions, based on halt-data of the microprogram at the time of an instruction re-reading operation in said pipeline instruction execution unit, in which at the time a state of the instruction processing apparatus is changed in an execution of a sequence of an instruction, an instruction re-reading operation which reads another sequence of instruction is executed; and a control unit releasing the halting by said halt unit according to the release-data of the microprogram which controls the instruction re-reading operation while the pipeline instruction execution unit is executing.