Patent ID: 6194761
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A VDMOS transistor structure in an integrated circuit formed in a semiconductor layer of first conductivity type on a substrate of second conductivity type, comprising:a first region of first conductivity type extending into the semiconductor layer from a major surface thereof farther from the substrate;a second region of second conductivity type extending from the major surface into the semiconductor layer around the first region and laterally limiting the first region and being a region for junction-isolation of the first region;a third region of second conductivity type extending from the major surface into the first region and defining a body region of a VDMOS transistor;a fourth region of first conductivity type extending from the major surface into the third region and defining a source region of the VDMOS transistor, the fourth region also defining a first channel with edges of the third region;a first insulating layer extending over the major surface at least over the first channel;a first electrically conductive layer extending over the first insulating layer at least over the first channel, the first electrically conductive layer defining a gate electrode of the VDMOS transistor;a fifth region of first conductivity type having lower resistivity than the first region and extending from the major surface into the first region, the first region and the fifth region together defining a drain region of the VDMOS transistor;a first electrode in contact with the fifth region, and defining a drain terminal of the VDMOS transistor;a second electrode in contact with the first electrically conductive layer, and defining a gate terminal of the VDMOS transistor;a third electrode in contact with the third region and with the fourth region, and defining a source terminal of the VDMOS transistor;a fourth electrode connected to the second region, and defining a biasing terminal therefor;a sixth region of second conductivity type extending from the major surface into the first region, in contact with the second region, and delimiting a second channel with an edge of the third region;a second insulating layer extending at least over the second channel; anda second electrically conductive layer extending at least over the second channel and connected to the second electrode;the third region and the sixth region defining source and drain regions of a MOS transistor, respectively, and the second electrically conductive layer defining a gate electrode of the MOS transistor, the MOS transistor having a threshold voltage lower than a breakdown voltage between the source and gate of the VDMOS transistor so that the MOS transistor acts as a voltage limiter.