Patent ID: 6744099
Filing Date: 2004-06-01
Classification: H01L,Y10S

Abstract:
A MIS semiconductor device comprising:a gate dielectric formed on a semiconductor substrate of a first conduction type; a gate electrode provided on a top surface of said gate dielectric; a first side-wall spacer formed on a surface of said semiconductor substrate spread over an outer circumference of said gate electrode, being in contact with a side wall of said gate electrode; a first impurity area formed by introduction of first impurities having a conduction type opposite to said first conduction type into said semiconductor substrate with said gate electrode and said first side-wall spacer used as masks; a second side-wall spacer formed by placing on a side wall of said first side-wall spacer; and a second impurity area, which has an impurity concentration higher than an impurity concentration of said first impurity area and is formed by introduction of said first impurities into said semiconductor substrate with said gate electrode, said first side-wall spacer and said second side-wall spacer used as masks, wherein: said first side-wall spacer has a relative dielectric constant greater than that of said second side-wall spacer for a predetermined width; and one edge of said gate electrode overlaps on said first impurity area.