Patent ID: 6479338
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of manufacturing a CMOS device comprising the steps of:preparing a semiconductor substrate having a first conductivity type; forming a well region in the substrate, the well having a second conductivity type opposite to the first conductivity type; implanting first ions having the first conductivity type, simultaneously into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region; implanting second ions having the second conductivity type, simultaneously into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a second drain region having a second impurity density; thermally diffusing the respective ion implanted regions to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate; forming a third drain region in the first drain region so as to have the first conductivity type and a third impurity density higher than the first impurity density; and forming a fourth drain region in the second drain region so as to have the second conductivity type and a fourth impurity density higher than the second impurity density.