Patent ID: 7869492
Filing Date: 2011-01-11
Classification: H03L,H04L

Abstract:
1. A frequency-locking device in a universal serial bus device, comprising: a digitally-controlled oscillator for generating an output frequency signal; a packet analyzing unit using the output frequency signal to sample a universal serial bus signal and analyzes part of a token packet of the universal serial bus signal to generate a reference signal; a control unit generating a calibration signal for adjusting the frequency of the output frequency signal and judging whether the number of erroneous transmission times equals to a predetermined number according to the reference signal; the control unit enabling a control signal when the number of erroneous transmission times equals to the predetermined number, or disabling or prohibiting the control signal from outputting when the number of erroneous transmission times does not equal to the predetermined number; and a voltage adjusting unit applying a voltage level to a transmission line of the universal serial bus and adjusting the voltage level according to the state of the control signal.