Patent ID: 6604193
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A processor for executing an instruction with a register number specified by said instruction different from the number of a physical register to be actually used, said processor comprising:a register number translation unit for translating a register number specified by an instruction into the number of a physical register; and a register rename unit for temporarily replacing the number of a physical register with the number of a rename register, wherein, after said register number translation unit translates a register number specified by an instruction into the number of a physical register, said register rename unit temporarily replaces said number of said physical register with the number of a rename register, wherein said register number translation unit includes an instruction decoder for decoding an instruction to determine what is to be executed for said instruction prior to execution of said instruction, wherein said instruction decoder decodes a plurality of instructions in parallel, wherein said register number translation unit includes: a first register number translator for translating a register number specified by each of said instructions being decoded in parallel into the number of a physical register in accordance with register number translation prior to a change caused by a slide instruction for updating translation of a register number specified by an instruction into the number of a physical register in said register number translation unit on the assumption that said instructions being decoded in parallel do not include said slide instruction, and a second register number translator for translating a register number specified by each of said instructions being decoded in parallel into the number of a physical register in accordance with register number translation after a change caused by a slide instruction for updating translation of a register number specified by an instruction into the number of a physical register in said register number translation unit on the assumption that said instructions being decoded in parallel include said slide instruction, and wherein there is also provided a translation result switching unit which is used for switching a result of translation produced by said register number translation unit from a result produced by said first register number translator for instructions preceding a slide instruction in an original program instruction sequence to a result produced by said second register number translator for instructions succeeding said slide instruction in said original program instruction sequence when a result of decoding said instructions indicates that said slide instruction is included among said instructions.