Patent ID: 7930481
Filing Date: 2011-04-19
Classification: G06F

Abstract:
1. A method, comprising: a computer system receiving a plurality of write operations directed to a storage area network (SAN) via a system cache implemented in a memory of the computer system, wherein the write operations are issued by an application running on the computer system, wherein the computer system is coupled to the SAN via a network interface, and wherein the SAN comprises a plurality of persistent caches; the computer system causing the plurality of write operations to be sent from the system cache to the SAN; the computer system receiving information from the SAN that indicates amounts of available memory within at least first and second ones of the plurality of persistent caches, wherein the at least first and second persistent caches are in different physical devices; and in response to determining that the received information is indicative of a violation of a write caching policy, the computer system changing one or more latency parameters of the system cache to decrease a rate at which first and second sets of one or more write operations are provided from the computer system to the SAN, wherein the first set of write operations includes one or more target addresses corresponding to the first persistent cache, and wherein the second set of write operations includes one or more target addresses corresponding to the second persistent cache.