Patent ID: 8786048
Filing Date: 2014-07-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first interface circuit; a second interface circuit formed adjacent to said first interface circuit; and a substrate on which said first interface circuit and said second interface circuit are formed, wherein said first interface circuit comprises: a first signal pad; a first power supply line; a first ground line; a first inductor section whose one end is connected to said first signal pad; a first terminating resistor connected between the other end of said first inductor section and said first power supply line or said first ground line; a first ESD protection element connected to a first node in said first inductor section; and a second ESD protection element connected to a second node whose position is different from that of said first node in said first inductor section, wherein said second interface circuit comprises: a second signal pad; a second power supply line; a second ground line; a second inductor section whose one end is connected to said second signal pad; a second terminating resistor connected between the other end of said second inductor section and said second power supply line or said second ground line; a third ESD protection element connected to a third node in said second inductor section; and a fourth ESD protection element connected to a fourth node whose position is different from that of said third node in said second inductor section, wherein a first interconnection connecting said first ESD protection element to said first ground line, which connects said third ESD protection element to said second ground line, are shared by adjacent said third ESD protection element.