Patent ID: 7932965
Filing Date: 2011-04-26
Classification: H01L

Abstract:
1. A method for manufacturing a thin film transistor array panel comprising: forming a data line, a gate electrode, a source electrode and a drain electrode on a substrate; forming a passivation on the data line, the gate electrode, the source electrode and the drain electrode; forming a first conductive film on the passivation layer; removing a portion of the first conductive film and a portion of the passivation layer to expose a portion of the data line, a portion of the source electrode, a portion of the drain electrode, and a portion of the gate electrode; forming a second conductive film on the first conductive film, an exposed portion of the data line, an exposed portion of the source electrode, an exposed portion of the drain electrode, and an exposed portion of the gate electrode; and removing a portion of the second conductive film and a portion of the first conductive film to form a pixel electrode, a data line connector and a gate line.