Patent ID: 9159730
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming a device isolation layer pattern on a substrate to form an active region having an isolated shape, the active region including a first contact forming region at an upper portion of a center portion of the active region and second and third contact forming regions at upper portions of both edge portions of the active region; forming an insulating layer on the substrate; forming a first conductive layer on the insulating layer; forming a mask pattern having an isolated shape on the first conductive layer, the mask pattern defining portions of the second and third contact forming regions and a portion of the device isolation layer pattern adjacent to the second and third contact forming regions; etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form a structure including a first preliminary conductive pattern and an insulating layer pattern and having a pillar shape covering the second and third contact forming regions and to form an opening portion between the structures, such that the opening portion extends to continuously overlap a plurality of active regions; forming a second conductive layer on the first preliminary conductive layer pattern, the second conductive layer filling up an inner portion of the opening portion; and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.