Patent ID: 7217642
Filing Date: 2007-05-15
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a thin film transistor, the method comprising the steps of: depositing an amorphous silicon layer onto an insulating substrate; forming a semiconductor layer through crystallizing the amorphous silicon layer through a sequential lateral solidification process using a polysilicon formation mask where slit patterns for defining light transmission regions are arranged while being sequentially reduced or enlarged in width in a predetermined direction; forming a gate insulating layer on the substrate such that the gate insulating layer covers the semiconductor layer; forming a gate electrode on the gate insulating layer over the semiconductor layer; forming source and drain regions at the semiconductor layer through implanting impurities into the semiconductor layer; forming an inter-layered insulating layer such that the inter-layered insulating layer covers the gate electrode; etching the inter-layered insulating layer and the gate insulating layer to thereby form contact holes exposing the source and the drain regions; and forming source and drain electrodes such that the source and the drain electrodes are connected to the source and the drain regions through the contact holes.