Patent ID: 7342284
Filing Date: 2008-03-11
Classification: H01L

Abstract:
1. A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device, comprising: providing a semiconductor substrate having thereon an active area isolated by a shallow trench isolation (STI) region; forming a gate dielectric layer on the active area; forming a gate electrode on the gate dielectric layer, wherein the gate electrode has vertical sidewalls and a top surface; forming a liner on the vertical sidewalls of the gate electrode; forming a silicon nitride spacer on the liner; ion implanting the active area using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the active area; forming a silicide layer on the top surface of the gate electrode and on the source/drain region; performing an etching process to etch away a thickness of the STI region, thereby forming a step height h at interface between the active area and the STI region; removing the silicon nitride spacer; and forming a stressed cap layer that borders the liner, wherein the stressed cap layer has a specific stress status and extends to the STI region.