Patent ID: 9196355
Filing Date: 2015-11-24
Classification: G11C,H01L

Abstract:
1. A method comprising: forming a memory cell including a variable resistance memory layer disposed between electrode layers, wherein the electrode layers are carbon layers; forming a semiconductor-oxide-based, non-silicon selector switch in direct contact with the memory cell at a temperature of less than 150° C.; providing a sealing layer in contact with the memory cell and the semiconductor-oxide-based, non-silicon selector switch; providing a plurality of dielectric layers at least partially surrounding the memory cell, the semiconductor-oxide-based, non-silicon selector switch, and the at least one sealing layer, the plurality of dielectric layers in direct contact with at least the memory cell and the at least one sealing layer, wherein the sealing layer separates two adjacent dielectric layers of the plurality of dielectric layers; providing a first conductive plug on the at least one sealing layer, the first conductive plug configured to allow electrical access between the semiconductor-oxide-based, non-silicon selector switch and a word line; providing a first diffusion barrier layer at least partially surrounding the first conductive plug; providing a second conductive plug on the memory cell, the second conductive plug configured to allow electrical access between the memory cell and a bit line; and providing a second diffusion barrier layer at least partially surrounding the second conductive plug.