Patent ID: 8977790
Filing Date: 2015-03-10
Classification: G06F

Abstract:
1. An electronic system comprising: a processing element adapted to execute machine readable code that causes the processing element to perform a data transfer of an x-bit wide data value, wherein performing the data transfer includes providing a first read/write signal and a single processing element-provided address that corresponds to a y-bit wide data register of a peripheral module, and wherein y is less than x; a bus controller adapted to receive the read/write signal and the single processing element-provided address, and in response, to perform a series of multiple data transfers with the peripheral module, wherein performing the series includes providing a second read/write signal and a first peripheral address for a first data transfer of the series, and providing different peripheral addresses for each other data transfer of the series, and wherein the series includes x/y sequential data transfers; and the peripheral module configured to map the first peripheral address to the y-bit wide data register, and also to map the different peripheral addresses to the y-bit wide data register.