Patent ID: 7115974
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a substrate baying a surface; a gate dielectric formed on the surface of the substrate; a gate electrode Conned on the gate dielectric; a pair of spacers formed along opposite sidewalls of the gate electrode and the gate dielectric; source and drain regions formed on opposite sides of the gate electrode; a contact etch stop (CES) layer blanket formed on the source and drain regions and the spacers wherein the CES layer is formed of a material selected from the group consisting essentially of a silicon oxycarbide (SiCO) based material and a silicon carbonitride (SiCN) based material; an inter-level dielectric (ILD) formed on the CES layer; and a conductive plug formed in the inter-level dielectric.