Patent ID: 6735612
Filing Date: 2004-05-11
Classification: G06F

Abstract:
A two-stage carry skip adder, comprising:two N-bit inputs, said N-bit inputs divided, from a lower level, into a first group having three bits, a second group having two bits, a third group having two 2-bit sets, and a fourth and following groups, wherein an n-th group (n is an integer of 4 or more) has nâˆ’1 sets, and in said n-th group, a first and a second set has two bits each, and an m-th set (m is an integer of 3 or more) has m bits; N adders, each said adder connected to two input at the same bit positions of said two N-bit inputs, and having a sum output and a carry output; a line for directly transmitting a ripple carry from one of said N adders to a succeeding one of said N adders in said first and second groups and in each said set; a line for transmitting a carry from a set to a succeeding set in each said group of said third group and following groups; a line for transmitting a carry from a group to a succeeding group in each said group of said second group and following groups; and a circuit for correcting said sum output of said N adders by using a transmitted carry from a previous set, a transmitted carry from a previous group, and said sum output.