Patent ID: 6108722
Filing Date: 2000-08-22
Classification: G06F

Abstract:
An apparatus coupled to a central processor, a system memory, a system bus, and a local memory to perform a DMA transfer of a block of data having discontinuous memory addresses, the apparatus comprising:an address calculating circuit coupled to the system bus which receives information regarding a block of memory locations inside the system memory, wherein the block of memory locations includes a plurality of memory location rows having discontinuous memory addresses, a memory location row having a plurality of memory locations for storing data words;wherein the information regarding the block of memory locations comprises an address of a first memory location in a first row, a number of memory location rows, a number of data words per memory location row, and a number of memory locations to be skipped between rows; andwherein the address calculating circuit generates a plurality of transaction entries corresponding to the number of memory location rows each having a transaction type to be carried out, a starting memory address, and data word count of each transaction.