Patent ID: 8769356
Filing Date: 2014-07-01
Classification: G11C

Abstract:
1. A memory device, comprising: a memory cell array comprising a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells; a bad page map that stores bad page location information indicating whether each of the pages of the first memory block is good or bad; a first page control unit that generates a first access page address to block access to a fail page address of the first memory block; and a second page control unit that generates a second access page address to allow access to a pass page address of the second memory block, wherein the fail page address of the first memory block is replaced by the pass page address of the second memory block according to the bad page location information, and wherein the second page control unit comprises: a first storage unit that stores a memory access page address received from an external source; a second storage unit that stores the pass page address of the second memory block that replaces the fail page address of the first memory block; a selection control unit that stores a control signal for instructing the fail page address of the first memory block to be replaced by the pass page address of the second memory block; and a selection unit that selects the memory access page address stored in the first storage unit or the pass page address of the second memory block stored in the second storage unit and outputs a result of the selection as the second access page address.