Patent ID: 6670652
Filing Date: 2003-12-30
Classification: H01L

Abstract:
A monolithically integrated E/D mode (p-)HEMT comprising:a buffer layer formed on a semi-insulating substrate; a channel layer formed on said buffer layer; a spacer layer formed on said channel layer; a first barrier layer, a second barrier layer, and a third barrier layer sequentially formed on said spacer layer; an ohmic layer formed on said third barrier layer; a first exposed gate region formed by etching said ohmic layer such that said third barrier layer is exposed; a second exposed gate region formed by etching said ohmic layer and said third barrier layer such that said second barrier layer is exposed; and gate electrodes, respectively, formed on said first exposed region and said second exposed region, wherein said first barrier layer is made of an n-type impurity-doped In0.5Ga0.5P that is lattice-matched to GaAs.