Patent ID: 6927430
Filing Date: 2005-08-09
Classification: G11C,H01L

Abstract:
1. A memory structure comprising: a) a substrate; b) a plurality of doped lines overlying the substrate and isolated from each other by shallow trench isolation; c) a plurality of bit electrodes overlying the doped bit lines at an angle, whereby a cross-point is formed at each location where a bit electrode crosses a doped bit line; d) a plurality of diodes comprising the doped lines and a doped region of opposite polarity in contact with the doped lines, with each doped region located at a cross-point; e) a plurality of bottom electrodes overlying the plurality of diodes; f) a resistive memory active layer interposed between the plurality of bit electrodes and the plurality of bottom electrodes; g) a second resistive memory active layer overlying the plurality of bit electrodes; h) a plurality of stacked electrodes overlying the second resistive memory active layer; and i) a plurality of top electrodes overlying the stacked electrodes to form a cross-point array with the plurality of bit electrodes.