Patent ID: 9135977
Filing Date: 2015-09-15
Classification: G11C,H01L

Abstract:
1. A static random access memory (SRAM) cell comprising: an isolated p-well; a first word line; a first bit line for providing thereon a signal; a second bit line, the second bit line for providing thereon an inverse signal of the signal of the first bit line; a first NMOS transistor laterally formed within the isolated p-well and having a drain portion, a source portion, and a gate portion; a second NMOS transistor laterally formed within the isolated p-well and having a drain portion, a source portion, and a gate portion; a first PMOS transistor electrically connected to the first NMOS transistor to form a first inverter having a respective input and a respective output; a second PMOS transistor electrically connected to the second NMOS transistor to form a second inverter having a respective input and a respective output, the output of the second inverter electrically connected to the input of the first inverter and the output of the first inverter connected to the input of the second inverter; a first transfer NMOS transistor laterally formed within the isolated p-well and having a gate portion electrically connected to the first word line, and further connected to provide an electrical path between the first bit line and the output of the first inverter; a second transfer NMOS transistor laterally formed within the isolated p-well and having a gate portion electrically connected to the first word line, and further connected to provide an electrical path between the second bit line and the output of the second inverter; and a first diode having an anode and a cathode, the anode electrically connected to the first word-line and the cathode electrically connected to the isolated p-well of the first NMOS transistor and the isolated p-well of the second NMOS transistor, such that when the anode of the first diode is at a first potential applied to the word-line the first NMOS transistor and the second NMOS transistor have a first threshold value, and when the anode of the first diode is at a second potential applied to the word-line the first NMOS transistor and the second NMOS transistor to have a second threshold value, wherein the second threshold value is lower than the first threshold value.