Patent ID: 6285172
Filing Date: 2001-09-04
Classification: G06F,H03L

Abstract:
A digital phase-locked loop circuit, comprising:a phase detector, having a first input for receiving a system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other;a latch, for storing the state of the direction signal;an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal;a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input;a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal;a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; andclock distribution circuitry, for receiving the first delayed clock and for distributing one or more chip clocks based thereupon.