Patent ID: 8698280
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first MOS device formed on a surface of a P-type substrate provided as a base that has a characteristic that is similar to that of a depletion mode MOS device; a second MOS device formed on a surface of the P-type substrate that has a characteristic that is similar to that of a depletion mode MOS device; and a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region, wherein the third MOS device comprises a well layer and the channel stop region is formed below an STI region, the STI region has a top surface that is coplanar with the P-type substrate and the well layer extends into second and third well layers, wherein the entire channel stop region lies between the second MOS device and the third MOS device and below the STI region.