Patent ID: 9070740
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A memory unit comprising: a substrate having a surface; at least one charge storage element; at least one first recessed access element disposed in an active area of the substrate and extending from the surface into the substrate, wherein the first recessed access element is a recessed access transistor, the first recessed access element is electrically connected to the charge storage element and, the first recessed access element is for inducing in the substrate a first depletion region; and an isolation portion adjacent to the active area and extending from the surface into the substrate, wherein the isolation portion includes a trenched isolating barrier and a second recessed access element, wherein the second recessed access element is disposed in the trenched isolating barrier for inducing in the substrate a second depletion region, and the trenched isolating barrier provides electrical insulation between the second recessed access element and the charge storage unit.