Patent ID: 6292413
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A semiconductor memory device including a plurality of memory cells, a memory cell selection line provided in correspondence to each said memory cell, a spare memory cell for substituting for defective said memory cell among said plurality of memory cells and a spare memory cell selection line provided in correspondence to said spare memory cell with a specific address signal allocated to each said memory cell, said semiconductor memory device comprising:a main power supply line supplied with a power supply potential;first and second transistors, having first electrodes connected to said main power supply line respectively, responsively rendered conductive when said address signal is inputted;first and second sub power supply lines connected to second electrodes of said first and second transistors respectively;a decoder provided in correspondence to each said memory cell selection line and driven by said power supply potential supplied from said first sub power supply line for responsively setting corresponding said memory cell selection line at a selection potential and activating corresponding said memory cell when corresponding said address signal is inputted;a determination circuit storing said address signal allocated to said defective memory cell and responsively outputting a hit signal when said address signal is inputted;a redundancy decoder driven by said power supply potential supplied from said second sub power supply line for responsively setting said spare memory cell selection line at a selection potential and activating said spare memory cell when said determination circuit outputs said hit signal; anda data input/output circuit inputting/outputting data between said spare memory cell activated by said redundancy decoder and an external device when said determination circuit outputs said hit signal while inputting/outputting data between said memory cell activated by said decoder and said external device when said determination circuit outputs no said hit signal.