Patent ID: 6348883
Filing Date: 2002-02-19
Classification: G11B,H03M

Abstract:
A method of converting channel bits of 16 bits long modulated by an 8/16 modulation scheme to output bits, comprising the steps of:(a) dividing a symbol of 16 bits long appearing at an instant â€œtâ€  into a first consecutive bit stream and a second consecutive bit stream; (b) generating a NEXT flag bit from a pattern of 16 bits appearing at an instant â€œt+1â€ , which is delayed for a single symbol period from said instant â€œtâ€ ; (c) associating patterns of â€œmâ€  bits with a plurality of patterns represented by said first consecutive bit stream other than those patterns being unable to exist under a minimum run-length condition for converting said first consecutive bit stream to said â€œmâ€  bits, and associating patterns of â€œnâ€  bits with a plurality of patterns represented by said second consecutive bit stream other than those patterns being unable to exist under said minimum run-length condition for converting said second consecutive bit stream to said â€œnâ€  bits; and (d) combining said NEXT flag bit, said â€œmâ€  bits and said â€œnâ€  bits for generating said output bits.