Patent ID: 6618842
Filing Date: 2003-09-09
Classification: G06F,H05K,Y10T

Abstract:
A prototype development apparatus comprising:a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; said LB including a logic board clock connector site (LBCCS) coupled to a number of clock traces and adapted to receive a clock connector; a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs; and a clock mezzanine board (CMB) having a clock mezzanine board connector site (CMBCS) adapted to receive said clock connector and coupled to a number of mezzanine clock traces.