Patent ID: 6694504
Filing Date: 2004-02-17
Classification: B81B,B81C

Abstract:
A method of fabricating an electrostatic vertical and torsional actuator using the micro electro mechanical system fabrication technology, comprising the following steps:step (a) of depositing silicon etch mask 1 on a silicon wafer and patterning it by a first photolithography process, thereby determining all planar dimensions of the electrostatic vertical and torsional actuator from a same photomask; step (b) of depositing silicon etch mask 2 on to of the already patterned etch mask 1 of step (a), and patterning it by a second photolithography process, making upper comb electrodes of the electrostatic vertical and torsional actuator to be completely covered by the silicon etch mask 2, while parts of a silicon substrate is exposed; step (c) of performing a first silicon etching by an amount of t1, during which the silicon etch mask 2 and parts of the silicon etch mask 1 that are not covered with the silicon etch mask 2 are also simultaneously etched, such that the silicon etch mask 1 has different thicknesses between parts that are covered with the silicon etch mask 2 and parts that are not covered with the silicon etch mask 2; step (d) of removing the silicon etch mask 2; step (e) of determining a thickness of the upper electrode by performing a second silicon etching by an amount of t2 in a state where the silicon etch mask 2 has been removed at said step (d); step (f) of depositing a wall protection layer on vertical sidewalls of the structure which has been formed during said step (e); step (g) of determining a vertical gap between the substrate and a lower electrode by performing a third silicon etching by an amount of t3 after said step (f); step (h) of laterally underetching silicon parts that are not covered with the wall protection layer and that are exposed in said step (g), in a horizontal direction using aqueous alkaline etchant, such that the body of the structure formed in said previous steps and its various combs are released from the main silicon wafer substrate; step (i) of, to the structure formed through said step (h), etching the silicon etch mask 1 by an amount of the thickness of the silicon etch mask 1 at the thinner parts within the silicon etch mask 1, where the thickness difference of the silicon etch mask 1 is caused by the etching of the exposed part of the silicon etch mask 1 which are not covered with the silicon etch mask 2, at said step (c) and determining a vertical offset between the upper electrode and the lower electrode by performing a fourth silicon etching by an amount of t4; and step (j) of removing the wall protection layer, which has been formed at said step (f), and removing the silicon etch mask 1, which is formed during said step (a).