Patent ID: 7671457
Filing Date: 2010-03-02
Classification: H01L,H05K,Y10T

Abstract:
1. A semiconductor package, comprising: a semiconductor die; a substrate including a conductive circuit pattern for connecting electrical connections of the semiconductor die to a plurality of bottom-side terminals accessible from the bottom side of the substrate, wherein the semiconductor die is mounted on a top surface of the substrate; an encapsulation covering the semiconductor die and at least the top surface of the substrate; and a plurality of top-surface terminals disposed on a top surface of the encapsulation for mounting and electrically connecting to a second semiconductor package, and wherein the top-surface terminals are electrically connected to at least one of the conductive circuit pattern of the substrate, the electrical connections of the semiconductor die and the bottom-side terminals, wherein the top-surface terminals are provided by conductor-filled vias provided through the encapsulation and substrate and are accessible from the bottom side of the substrate, and wherein at least one of the bottom-side terminals is provided by a bottom side of one of the vias, whereby an electrical interface of the second semiconductor package is accessible from the bottom side of the semiconductor package.