Patent ID: 8716695
Filing Date: 2014-05-06
Classification: B82Y,H01L

Abstract:
1. A FET device, comprising: nanowires and pads formed in a SOI layer over a BOX layer, wherein the nanowires are connected to the pads in a ladder-like configuration, and wherein the nanowires are suspended over the BOX; and one or more gates surrounding portions of each of the nanowires, wherein the portions of the nanowires surrounded by the gates comprise channel regions of the device and portions of the nanowires extending out from the gates and the pads comprise source and drain regions of the device, wherein each of the nanowires has 1) at least one first region that is deformed such that a lattice constant in the at least one first region is less than a relaxed lattice constant of the nanowires and 2) at least one second region that is deformed such that a lattice constant in the at least one second region is greater than the relaxed lattice constant of the nanowires, and wherein the one or more gates surround the at least one second region of each of the nanowires.