Patent ID: 8624349
Filing Date: 2014-01-07
Classification: H01L

Abstract:
1. A process comprising: simultaneously forming an isolation trench and a handle wafer contact trench in a silicon-on-insulator semiconductor substrate, the substrate including a buried insulating layer and a handle wafer bonded to a bottom surface of the substrate, the isolation trench having a first width and the handle wafer contact trench having a second width, the second width being greater than the first width and the buried insulating layer defining a trench bottom of the handle wafer contact trench, the isolation trench extending through a silicon-on-insulator layer, the silicon-on-insulator layer disposed directly on a buried oxide layer; depositing an oxide insulating layer in the isolation trench and the handle wafer contact trench, the oxide insulating layer covering a sidewall of the handle wafer contact trench and the trench bottom of the handle wafer contact trench, the oxide insulating layer at least substantially filling the isolation trench; etching the oxide insulating layer covering the sidewall of the handle wafer contact trench such that the sidewall shape defines a tapered portion and an untapered portion and the trench bottom of the handle wafer contact trench so that the oxide insulating layer covering the trench bottom is at least partially removed, the tapered portion having a continuously curved profile, the handle wafer contact trench having the tapered portion and the untapered portion caused by the sidewall shape; etching the buried insulating layer so that a top surface of the portion of the handle wafer is at least partially exposed; at least partially filling the handle wafer contact trench with an electrically conductive material; and covering a top of the electrically conductive material with an insulating material, wherein simultaneously forming the isolation trench and the handle wafer contact trench causes formation of at least three active silicon regions, wherein a first active silicon region of the at least three active silicon regions comprises a first dopant type and a second active silicon region and a third silicon region of the at least three active silicon regions comprise a second dopant type, the first dopant type different from the second dopant type.