Patent ID: 7888677
Filing Date: 2011-02-15
Classification: G02F,H01L

Abstract:
1. A thin film transistor (TFT) array panel, comprising: a substrate; a gate wire formed on the substrate and including a gate line, a gate electrode and a gate pad; a gate insulating layer pattern formed on the gate wire; a semiconductor layer pattern formed on the gate insulating layer pattern; an ohmic contact layer pattern formed on the semiconductor layer pattern; a data wire formed on the ohmic contact layer pattern, including a data line, a source electrode, a drain electrode and a data pad, and having a planar shape substantially the same as that of the ohmic contact layer pattern due to simultaneous etching; a passivation layer pattern formed on the data wire, having contact holes exposing the gate pad, the data pad and the drain electrode, having a planar shape substantially the same as that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire; and a pixel electrode electrically connected to the exposed portion of the drain electrode, wherein a portion of the pixel electrode is in direct contact with an upper surface of the gate insulating layer pattern.