Patent ID: 6764906
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A process of fabricating a power MOSFET comprising:providing a substrate of a first conductivity type; providing an epitaxial layer of a second conductivity type opposite to said first conductivity type on the substrate; forming a trench in the epitaxial layer; implanting dopant of said first conductivity type through a bottom of the trench to form a drain-drift region beneath said trench and within said epitaxial layer, immediately following said implanting said drain-drift region extending from said trench to said substrate; forming an insulating layer along the bottom and a sidewall of the trench; introducing a conductive gate material into the trench; and introducing dopant of the first conductivity type into the epitaxial layer to form a source region, the drain-drift region and the source region being formed under conditions such that the source region and drain-drift region are separated by a channel region of the epitaxial layer adjacent the sidewall of the trench.