Patent ID: 6115280
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory cell array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns for storing data, said memory cells being divided into a plurality of blocks each including a plurality of columns;a plurality of output registers for retaining data read from said blocks of said memory cell array, each of said output registers including a plurality of output data retaining blocks corresponding to said blocks of said memory cell array, each of said output data retaining blocks retaining data read from the corresponding block of said memory cell array;output register selecting means for selecting one of said output registers;counter means for performing a count in synchronization with a clock signal externally supplied;a data output pin for outputting the read data to the outside; andoutput data transfer means for successively selecting, in accordance with the result of the counting by said counter means, said output data retaining blocks of the output register selected by said output register selecting means, said output data transfer means further transferring data from the successively selected output data retaining blocks to said data output pin, thereby outputting said data over a plurality of cycles of said clock signal.