Patent ID: 6444593
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A method for fabricating an integrated circuit, the integrated circuit including a first metal stack, a dielectric layer, and a second metal stack, the dielectric layer being between the first metal stack and the second metal stack, the method comprising:providing the first metal stack; providing the dielectric layer including at least one layer including SiOF; first depleting fluorine from a top surface of the dielectric layer with a first plasma; first passivating the top surface with a second plasma; selectively etching through the top surface to form a via in contact with the first metal stack; second depleting fluorine from the top surface of the dielectric layer and from a side surface of the via with the first plasma; second passivating the top surface and the side surface with the second plasma; providing a conformal layer of conductive material above the top surface and filling the via with the conductive material; removing the conformal layer from the top surface, thereby leaving the conductive material in the via; third depleting fluorine from the top surface of the dielectric layer with the first plasma; third passivating the top surface with the second plasma; and providing the second metal stack.