Patent ID: 8208578
Filing Date: 2012-06-26
Classification: H04L

Abstract:
1. A system for fractional pre-emphasis of multi-mode interconnect, the system comprising: an encoder for receiving a plurality of bits of binary data in parallel and encoding the plurality of bits of binary data into a plurality of scalar values, each scalar value representing a level for a multi-level analog signal to be output over a multi-mode interconnect system during a current period; a plurality of multi-level drivers, each for receiving a respective one of the plurality of scalar values generated by the encoder for the current period and for generating an analog signal output whose value corresponds to the respective scalar value received from the encoder; a latch for storing the plurality of scalar values generated by the encoder during a previous period; a comparator module for receiving from the encoder the plurality of scalar values generated by the encoder for the current period, for receiving from the latch the plurality of scalar values generated by the encoder during the previous period, and for each respective scalar value, generating a difference signal indicating the difference between the scalar value generated by the encoder for the current period and the scalar value generated by the encoder during the previous period; and a pre-emphasis module for providing fractional pre-emphasis to the analog signal outputs from the multi-level drivers, wherein the pre-emphasis for each respective analog signal output is based on the respective difference signal generated by the comparator module, and wherein the emphasis is provided to the analog signal outputs during a fraction of a period that is less than the whole period.