Patent ID: 8436669
Filing Date: 2013-05-07
Classification: H03K

Abstract:
1. A single-trigger low-energy flip-flop circuit, comprising: a trigger sub-circuit that includes a first clock-activated transistor and is configured to arm a trigger signal when an input signal to the single-trigger low-energy flip-flop circuit is at a different level than a level of an output signal generated by the single-trigger low-energy flip-flop circuit; and a latch sub-circuit that includes a second clock-activated transistor and is configured to change the level of the output signal when the trigger signal is armed and a clock signal transitions from a first level to a second level and maintain the level of the output signal when the trigger signal is unarmed, wherein the latch sub-circuit further comprises a third clock-activated transistor that is configured as a pull-up transistor and is enabled for every Nth clock cycle where N is greater than ten.