Patent ID: 6031842
Filing Date: 2000-02-29
Classification: H04L,H04Q

Abstract:
Apparatus for reducing a data path latency and an inter-frame delay of a time slicing shared memory switch, comprising:a plurality of memory write data buses for receiving a respective plurality of data frames;a plurality of memory write address busses for supplying addresses of memory partitions associated with said plurality of data frames;an address slice crosspoint for generating a time slice number identifying memory partitions identified by portions of said addresses supplied by said memory write address busses; anda data slice crosspoint for applying said data frames to respective memory partitions identified by a corresponding time slice number generated by said address slice crosspoint, wherein data frames are applied to said memory partitions in a time sliced manner, and wherein a time slice for each partition of a shared memory is staggered so that on any clock cycle, one memory partition is being accessed for writing at least one of said data frames and on a next clock cycle said one memory partition may be accessed for reading at least a portion of data frames from said shared memory.