Patent ID: 9146870
Filing Date: 2015-09-29
Classification: G06F,Y02D

Abstract:
1. A processing apparatus comprising: a plurality of processors for processing data; a hierarchical memory system comprising a plurality of data stores for storing said data, said hierarchical memory system comprising a memory accessible to all of said plurality of processors, and a plurality of caches corresponding to each of said plurality of processors, each of said caches being accessible to said corresponding processor and comprising a plurality of storage locations and a corresponding plurality of indicators, said memory having a lower hierarchy than said plurality of caches; cache coherency control circuitry for maintaining coherency of data stored in said hierarchical memory system; each of said plurality of processors being configured to respond to receipt of a predefined request to perform an operation on a data item, to determine if said cache corresponding to said processor receiving said request comprises a storage location allocated to said data item; and if not, said processing apparatus is configured to: said processor is configured in response to said predefined request to perform said operation on data within said storage location allocated to said data item.