Patent ID: 7058073
Filing Date: 2006-06-06
Classification: H04J,H04L

Abstract:
1. An arrangement in a communication system including a TDM bus, a number of transmitters and receivers connected to said bus, at least one synchronization master developing Frame Synchronization signals, a stable oscillator supplying a free-running data clock, and a timeslot counter in each transmitter/receiver, wherein a free running data clock frequency is selected to give a number of periods within a frame that is always at least one more than a number of timeslots required, the periods that exceed the number of timeslots required constituting a dummy period, wherein each timeslot counter is adapted to identify the dummy period by introducing a carry bit, which is set each time the timeslot counter exceeds the number of timeslots required; and the frame synchronization signals are synchronized to the free-running data clock, wherein a switch over to another synchronization master takes place during the dummy period if the active synchronization master fails.