Patent ID: 7168004
Filing Date: 2007-01-23
Classification: G01R

Abstract:
1. A technique for testability of a semiconductor integrated circuit, comprising: the first step of conducting a fault simulation for the semiconductor integrated circuit based on a set of predetermined test signals and corresponding test results, and discriminating a detectable fault and an undetectable fault from each other, the predetermined test signals being a set of output values from a plurality of registers at an input side of a test object in the semiconductor integrated circuit the second step of listing undetectable faults as undetected faults; the third step of determining test signals for detecting the undetected faults; the fourth step of determining test signals most likely to meet the test signals of the third step from among the set of predetermined test signals of the fault simulation of the first step; the fifth step of replacing registers at the input side associated with the undetected faults of the second step with scan registers and connecting the scan registers in a scan chain thereby to construct a modified circuit; and the sixth step of conducting the fault simulation or a test by switching to the test signals determined in the fourth step at the timing corresponding to the undetected faults while using the predetermined test signals in the first step for the modified circuit.