Patent ID: 7298658
Filing Date: 2007-11-20
Classification: G11C

Abstract:
1. A semiconductor memory device having a row redundancy unit and an I/O redundancy unit as two dimensional redundancy units for relieving defects of an embedded memory, said row redundancy unit including redundant memory cell groups that replace memory cell rows addressed by row addresses, and said I/O redundancy unit including redundant memory cell groups that replace memory cell groups provided for every input/output data, wherein said memory device comprises: a built-in self-test circuit that tests an embedded memory, a redundant element location operator that selects a redundant memory cell group from said row redundancy unit and said I/O redundancy unit based on a preset order and according to the order in which defects are detected by said self-test circuit, and a redundancy replacement unit that replaces defects in said embedded memory with said redundant memory cell group selected by said redundant element location operator.