Patent ID: 9157169
Filing Date: 2015-10-13
Classification: C30B,H01L

Abstract:
1. A method of fabricating a power field-effect transistor (power FET), comprising: providing a substrate; growing a III-nitride body comprising aluminum nitride (AlN) over a major surface of said substrate to a final thickness over a growth period of time, wherein growth temperature is started at a low growth temperature and varied in cycles thereafter over said growth period of time, each cycle including a period of high temperature growth at a high temperature and a period of low temperature growth at a low temperature; said high temperature and said low temperature converging during said growth period of time until said high temperature and said low temperature are substantially equal to a final growth temperature of said III-nitride body; said III-nitride body being a superlattice structure wherein a number of layers grown at said high temperature is equal to a number of layers grown at said low temperature; forming a buffer layer over said III-nitride body; forming an active layer on said buffer layer, said active layer providing an active region for said power FET; said buffer layer and said III-nitride body being provided to resist current flow outside said active layer.