Patent ID: 6512717
Filing Date: 2003-01-28
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a core area including a plurality of memory blocks; a data bus including a plurality of data bus lines such that each of said plurality of data bus lines corresponds to one of said plurality of memory blocks, each of said data bus lines carrying a data bit to be written into or read out from a memory cell included in a memory block that corresponds to said data bus line; a plurality of input/output terminals provided in number corresponding to said plurality of data bus lines forming said data bus; and a data path switch circuit provided between said data bus lines and said input/output terminals for providing interconnection paths of said data bits between said input/output terminals and said data bus lines, wherein said data path switch circuit switches a part of said interconnection paths in response to a block address signal selecting a memory block from said plurality of memory blocks, said data path switch circuit changing a switching operation thereof between an ordinary operational mode and test operational mode.