Patent ID: 8717073
Filing Date: 2014-05-06
Classification: G11C,H03B,H03L

Abstract:
1. A digital PLL circuit comprising: a time to digital converter for comparing a reference clock signal with an internal clock signal and outputting a first digital data based on obtained comparison results; a digital loop filter for receiving the first digital data and outputting second digital data; a digitally controlled oscillator, an oscillation frequency of which is controlled based on the second digital data; a data holder for holding the second digital data in a time series manner; and a data controller for controlling switching in order to selectively transmit either the second digital data held in the data holder in accordance with the time series or the second digital data from the digital loop filter to the digitally controlled oscillator wherein, when the data controller selects the second digital data held by the data holder in the time series manner for transmission to the digitally controlled oscillator, the data controller halts at least either the time to digital converter or the digital loop filter.