Patent ID: 6545898
Filing Date: 2003-04-08
Classification: G11C

Abstract:
In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of biasing a selected X-line at a first voltage and a group of at least one unselected Y-lines at a second voltage different than the first voltage during a write operating mode, said method comprising the steps of:providing a source of the first voltage external to the integrated circuit; coupling the selected X-line through at least one switch circuit to the external source of the first voltage; providing on the integrated circuit a voltage regulator circuit responsive to the first voltage for generating a second voltage whose magnitude is less than the first voltage; and coupling a group of at least one unselected Y-lines through at least one switch circuit to the second voltage.