Patent ID: 6635915
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A semiconductor device comprising:an SOI substrate including a first semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor region formed on the buried insulating film, the SOI substrate including a DRAM array region and a logic circuit region: a trench with a depth to reach the first semiconductor region, extending from a surface of the second semiconductor region of the DRAM array region in the SOI substrate and passing through the buried insulating film; a trench capacitor formed within the trench; a first transistor formed within the DRAM array region in the SOI substrate, the first transistor having source and drain regions one of which is connected to one of electrodes of the trench capacitor, and forming a DRAM memory cell together with the trench capacitor; a gap region formed between a sidewall portion of the trench and the buried insulating film, as a recess of a buried oxide film; and a conductive layer formed to fit in the gap region, electrically insulated from the electrode of the trench capacitor formed within the trench, and electrically connecting the first semiconductor region and the second semiconductor region of the DRAM array region in the SOI substrate.