Patent ID: 7659741
Filing Date: 2010-02-09
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a semiconductor substrate; B. functional circuits formed on the substrate; C. plural scan path circuits formed on the substrate, each of the scan path circuits having a serial input for loading test stimulus data, a serial output for unloading test response data, parallel outputs coupled to the functional circuits to apply the test stimulus data to the functional circuits, and parallel inputs receiving the test response data from the functional circuits; D. scan distributor circuitry having a serial data input and plural parallel outputs, the parallel outputs being connected to the serial inputs of the scan path circuits, the scan distributor circuitry loading test stimulus data to the serial inputs of the scan path circuits, the scan distributor circuitry being free of any internal feedback shift register circuits; E. scan collector circuitry having a serial data output and plural parallel inputs, each parallel input being connected to the serial output of one of the scan path circuits, the scan distributor circuitry receiving test response data from the serial outputs of the scan path circuits.