Patent ID: 7972914
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming a dummy gate extending on an active region of a semiconductor substrate; providing a shielding layer on the dummy gate and on the active region, and planarizing the shielding layer using the dummy gate as an end point of planarization; forming an opening that exposes a surface of the active region; performing local channel ion implantation via the opening to form a channel ion implantation layer beneath the surface of the active region exposed by the opening using the shielding layer as an ion implantation mask, the local channel ion implantation layer being formed in a lower portion of the active region; after forming the channel ion implantation layer, doping an impurity of a conductivity type opposite that of an impurity of the channel ion implantation layer into an upper portion of the active region to form a threshold voltage controlling ion implantation layer; etching the active region under the opening using the shielding layer as an etch mask to form a central trench that exposes the channel ion implantation layer, wherein a portion of the channel ion implantation layer and a portion of the threshold voltage controlling ion implantation layer are removed during the etching of the active region; recessing the shielding layer; depositing a gate oxide layer in the central trench; forming a gate electrode on the gate oxide layer; and forming a source region and a drain region in the active region at both sides of the gate electrode.