Patent ID: 9047427
Filing Date: 2015-06-02
Classification: G06F

Abstract:
1. A computer-implemented method implemented with a processor for verifying a design, comprising: using at least one computing system to perform a process, the process comprising: implementing an enhanced transaction level model that groups and abstracts activities of an electronic design into one or more transactions at a higher level of abstraction than an RTL level model; implementing the RTL level model of the electronic design at a lower level of abstraction; verifying a property in the electronic design at a first level of abstraction to determine whether the property functions for its intended purpose, wherein the first level of abstraction is selected to correspond to either the enhanced transaction level model or the RTL level model; and verifying the electronic design at a second level of abstraction after verifying the electronic design at the first level by using one or more model consistency rules to expand at least one data type and to promote determinism, without requiring re-verification of the property that was verified earlier at the first level of abstraction, wherein