Patent ID: 6215127
Filing Date: 2001-04-10
Classification: G03F,H01L

Abstract:
A method of qualifying an apparatus used in connection with fabrication of integrated circuits, the method comprising:mapping critical dimensions of a predetermined plurality of features comprising ring oscillators, turning forks, test transistors, and wafer electrical testing-purpose (WET) transistors at each of a plurality of selected exposure fields of a first production stage of a predetermined number of production stages of a wafer on which a plurality of integrated circuits are fabricated to create a first mapping;mapping the critical dimensions of the predetermined plurality of features at each of the plurality of selected exposure fields of at least a second production stage to create a second mapping;comparing the data collected at each of the first and second mappings; anddetermining, from the comparison, what changes are required in a set-up of a predetermined piece of apparatus which is used in at least one of the production stages, to bring at least one critical dimension of at least one of the predetermined features into agreement with at least one of a predetermined set of design critical dimensions.