Patent ID: 7859122
Filing Date: 2010-12-28
Classification: H01L

Abstract:
1. A structure, comprising: a first dielectric layer; an electrically conductive bond pad on the first dielectric layer; a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad, wherein the electrically conductive bond pad is sandwiched between the first and second dielectric layers, wherein the second dielectric layer comprises N separate final via openings such that a top surface of the electrically conductive bond pad is exposed to a surrounding ambient through each final via opening of the N separate final via openings, and wherein N is a positive integer greater than 1; an electrically conductive line buried in the first dielectric layer; a via buried in the first dielectric layer, wherein the electrically conductive bond pad is electrically connected to the via through the electrically conductive line; a plurality of interconnect layers such that the first dielectric layer is sandwiched between the plurality of interconnect layers and the electrically conductive bond pad; and an integrated circuit such that the plurality of interconnect layers are sandwiched between the integrated circuit and the first dielectric layer, wherein the electrically conductive line is electrically connected to the integrated circuit through the via and the plurality of interconnect layers.