Patent ID: 6404662
Filing Date: 2002-06-11
Classification: G11C,H01L

Abstract:
A method for manufacturing a high density stacked memory package for use in a high speed memory channel, the method comprising the steps of:providing first and second packaged integrated circuits encased in packages each having an upper surface, a lower surface and a four-sided perimeter wall from which emerge from opposite sides, electrical leads, an identified one of which leads emerges from a first side of the four-sided perimeter wall; and disposing the second packaged integrated circuit in relation to the first packaged integrated circuit to create a stacked package in which the identified lead of the first packaged integrated circuit is on the opposite side of the stacked package from the identified lead of the second packaged integrated circuit and the upper surface of the first packaged integrated circuit is closer to the upper surface of the second packaged integrated circuit than the lower surface of the second packaged integrated circuit.