Patent ID: 8524552
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. A method of manufacturing a normally-off power JFET, comprising the steps of: (a) providing a semiconductor wafer having, in a first main surface of a silicon-carbide-based semiconductor substrate having a first conductivity type, a first silicon-carbide-based semiconductor epitaxial layer having the same conductivity type as the first conductivity type and a concentration lower than that of the semiconductor substrate; (b) doping a surface of the first silicon-carbide-based semiconductor epitaxial layer corresponding to the first main surface of the semiconductor wafer with an impurity having second conductivity type by ion implantation to introduce, into the surface of the first epitaxial layer, a plurality of first gate impurity regions; (c) after the step (b), performing first activation annealing on the first main surface of the wafer; (d) after the step (c), forming, in the surface of the first epitaxial layer corresponding to the first main surface of the semiconductor wafer, a second silicon-carbide-based semiconductor epitaxial layer having the same conductivity type as the first conductivity type and a concentration lower than that of the semiconductor substrate; (e) doping a surface of the second silicon-carbide-based semiconductor epitaxial layer corresponding to the first main surface of the semiconductor wafer with an impurity having the same conductivity type as the second conductivity type by ion implantation to introduce, into the surface of the second epitaxial layer, a plurality of second gate impurity regions coupled to the individual first gate impurity regions to form gate impurity regions; and (f) after the step (e), performing second activation annealing on the first main surface of the wafer.