Patent ID: 9142566
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A semiconductor fabrication process comprising: providing a wafer comprising a first device area for forming one or more first voltage level transistors, a second device area for forming one or more second voltage level dual gate oxide transistors, and a third device area for forming one or more third voltage level transistors; forming a high voltage gate dielectric stack on the first and third device areas of the wafer and not on the second device area of the wafer; forming a dual gate oxide layer over the first, second, and third device areas of the wafer by depositing one or more oxide layers on the high voltage gate dielectric stack and on the exposed second device area of the wafer; removing the high voltage gate dielectric stack and dual gate oxide layer from the third device area of the wafer while leaving the dual gate oxide layer formed on the first and second device areas; forming a high-k gate dielectric stack over the first, second, and third device areas of the wafer to cover the dual gate oxide layer formed on the first and second device areas and the third device area of the wafer; and forming a plurality of patterned high-k metal gate electrodes on the high-k gate dielectric stack in each of the first, second, and third device areas; where the first voltage level is higher than the second voltage level which is higher than the third voltage level.