Patent ID: 9146811
Filing Date: 2015-09-29
Classification: G06F,G11C,H03M

Abstract:
1. An apparatus, comprising: a plurality of memories coupled to each other via a plurality of conductors; a logic die coupled to the plurality of memories and configured to read data from the plurality of memories, the logic die including an error checking system configured to generate an error checking code corresponding to data read from an address in a memory of the plurality of memories, the error checking system fluffier configured to indicate an error if a stored error checking code corresponding to the data read from the address does not match the generated error checking code; and a state machine configured to determine whether the error originated in the memory of the plurality of memories or in a conductor of the plurality of conductors, wherein the state machine, responsive to a determination that the error originated in a conductor of the plurality of conductors, is configured to determine whether a fault of the plurality of conductors is related to coupling addresses to the plurality of memories or related to coupling data to and from the plurality of memories.