Patent ID: 6343355
Filing Date: 2002-01-29
Classification: G11C

Abstract:
A sequence controller comprising:a first cycle counter for repeatedly counting a high speed clock at a basic period, the basic period consisting of a basic period processing section and a time division period processing section, and for generating a basic period pulse that has said basic period; a second cycle counter for repeatedly counting said basic period pulse at a time division period that is an integral multiple of said basic period; a memory for storing beforehand basic period processing information and time division period processing information which consists of a plurality of blocks; a decoder for decoding counts input from said first cycle counter and said second cycle counter and for generating predetermined timing signals; a first address counter for continuously generating, during the basic period processing section of said basic period, addresses for reading said basic period processing information out of said memory in accordance with said timing signals; and a second address counter for continuously generating, during the time division period processing section of said basic period, address for reading, one block at a time, said time division period processing information out of said memory in accordance with said timing signals.