Patent ID: 8854909
Filing Date: 2014-10-07
Classification: G11C

Abstract:
1. A method of testing a semiconductor memory device including an open bit line structure, the method comprising: providing a selected cell storing first data and a non-selected cell storing second data that has a logic state opposite to that of the first data, wherein the selected cell and the non-selected cell are coupled to a selected word line and disposed adjacent to each other; activating the selected word line to read out the data stored in the selected cell and the non-selected cell; and sensing and amplifying a voltage level loaded on a first bit line coupled to the selected cell to determine whether or not the selected cell is failed, wherein, when sensing and amplifying the voltage level loaded on the first bit line, a bit line precharge voltage corresponding to the first data stored in the selected cell is provided to a third bit line adjacent to a second bit line coupled to a sense amplifier that senses and amplifies the voltage level loaded on the first bit line, the second and third bit line being disposed in a second memory cell mat that is adjacent to a first memory cell mat where the selected cell is disposed.