Patent ID: 6775263
Filing Date: 2004-08-10
Classification: H04J,H04L

Abstract:
A frame synchronizing apparatus using a memory comprising:a 4-byte shift register for shifting input data to 4-byte data; a counter performing a counting in accordance with an input bit clock, byte clock, and reset signal; a memory controller for controlling a memory in accordance with first to third count signals output from said counter; a memory controlled by said memory controller so as to store three-sub frames; a demux for demultiplexing an output of said counter and an output of said memory; a buffer for storing three headers output from said demux; a pattern comparing unit for comparing a header value of said 4-byte shift register and a header value of said buffer, and allows an adder to add 1 if a value of 16-bits is F628 or a value of an upper 8-bits is E8; an adder for adding an output of said pattern comparing unit; and a state machine for receiving an added value from said adder and declaring synchronization if said added value is higher than a predetermined value.