Patent ID: 9105323
Filing Date: 2015-08-11
Classification: G06F,G11C,Y02D

Abstract:
1. A memory device, comprising: a stack of memory arrays; a logic controller on a die stacked with the stack of memory arrays; and an activity tracker located in the logic controller to monitor different levels of activity of at least one of a plurality of portions of the stack of memory arrays, wherein the logic controller is configured to adjust a power state of the at least one portion to correspond to the level of activity of the at least one portion, wherein a power state includes powering down only selected memory vault controllers and their associated memory vaults, wherein the portions include a plurality of vertical memory vaults, and wherein each vertical memory vault is associated with a respective vault controller located on the logic die, and each vault controller includes an activity tracker; a plurality of serialized communication link interfaces to couple the plurality of vertical memory vaults to a host processor; and a matrix switch enabling cross-connecting each of the plurality of serialized communication link interfaces to a selected vertical memory vault.