Patent ID: 8972700
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. A processor comprising: an instruction unit which provides instructions for execution by the processor; a decode unit which decodes instructions received from the instruction unit; a plurality of execution units; a plurality of queues, each coupled to receive instructions from the decode unit, wherein each instruction in a same queue of the plurality of queues is executed in order, and wherein each instruction in the same queue is executed by a corresponding execution unit of the plurality of execution units; and a first arbiter coupled to each of the plurality of queues and to a first execution unit of the plurality of execution units, wherein the first execution unit executes instructions of a first instruction type, wherein the first arbiter selects a next instruction of the first instruction type from a bottom entry of a first queue of the plurality of queues for execution by the first execution unit, and further wherein the decode unit, in response to receiving a complex instruction from the instruction unit, separates the complex instruction into a first micro-instruction and a second micro-instruction which together perform the complex instruction, wherein the first micro-instruction is saved to a first selected queue of the plurality of queues, the second micro-instruction is saved to a second selected queue of the plurality of queues, and the first selected queue is different from the second selected queue.