Patent ID: 6456111
Filing Date: 2002-09-24
Classification: H04L

Abstract:
A receiver circuit comprising:first and second input terminals for receiving a complementary potential signal having a fixed potential level and a floating level; first and second current sources each having first and second current terminals, said first current terminals of said first and second current sources being connected together; first and second switching transistors each connected between a corresponding one of said first and second input terminals and said second current terminal of a corresponding one of said first and second current sources; a current detection transistor connected between said first current terminals of said first and second current sources and a first power source line; a voltage control unit for applying a potential corresponding to a current detected by said current detection transistor to gates of said first and second switching transistors; and an RS latch circuit for receiving potentials of drains of said first and second switching transistors at a set input and a reset input, respectively, of said RS latch circuit.