Patent ID: 7468306
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit comprising a semiconductor device having a plurality of capacitors, comprising: (a) providing a semiconductor body having a plurality of contact pads arranged on a first surface of the semiconductor body; (b) forming pillars of a first sacrificial material at least on the contact pads vertically protruding from the surface; (c) depositing a first dielectric layer to cover at least the pillars; (d) depositing a first conductive layer, at least partially, filling an area between the pillars covered by the first dielectric layer; (e) depositing a non-conductive layer on a horizontal surface of the first conductive layer; (f) removing the pillars to provide trenches arranged in the first conductive layer having walls provided by the dielectric layer; (g) depositing a second conductive layer on the first dielectric layer at least in the trenches; (h) depositing a second dielectric layer such that at least the second conductive layer in trenches is covered by the second dielectric layer; (i) depositing a third conductive layer at least on the second dielectric layer; and (j) forming at least one conductive plug through at least the second dielectric layer vertically, thereby electrically connecting the first conductive layer and the third conductive layer.