Patent ID: 8722481
Filing Date: 2014-05-13
Classification: H01L,Y02P

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a gate layer stack of a semiconductor device above a first active region, a second active region and an isolation region that laterally separates said first and second active regions along a width direction, said gate layer stack comprising a high-k dielectric material; forming a first gate electrode structure and a second gate electrode structure from said gate layer stack, said first and second gate electrode structures being laterally aligned along said width direction and being separated above said isolation region by a lateral distance; forming a resist mask so as to selectively cover said second active region and said second gate electrode structure; and performing a resist etch process based on a predefined etch recipe so as to remove resist material at least at a foot of said resist mask to provide a reduced resist mask, at least one of said lateral distance and a lateral overlap of said resist mask being selected so as to avoid exposure of an end portion of said second gate electrode structure above said isolation region during said resist etch process.