Patent ID: 8017979
Filing Date: 2011-09-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a first semiconductor layer having the first semiconductor layer formed into a mesa shape above the substrate and having strain, and including source and drain regions of a first conductivity type located at a distance from each other in a direction heading from the first side face to the second side face, and a channel region of a second conductivity type different from the first conductivity type, the channel region being located between the source region and the drain region; a second semiconductor layer having the fifth side face and the first side face disposed in a first vertical plane, the seventh side face and the third side face disposed in a second vertical plane, and the eighth side face and the fourth side face disposed in a third vertical plane, the second semiconductor layer formed on the source region to contain impurities of the first conductivity type, the second semiconductor layer having a lattice constant that is ±10% or less of a lattice constant of the channel region of the first semiconductor layer; a third semiconductor layer having the tenth side face and the second side face disposed in a fourth vertical plane, the eleventh side face and the third side face disposed in the second vertical plane, and the twelfth side face and the fourth side face disposed in the third vertical plane, the third semiconductor layer formed on the drain region to contain impurities of the first conductivity type, the third semiconductor layer having a lattice constant that is ±10% or less of a lattice constant of the channel region of the first semiconductor layer; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film.