Patent ID: 9130548
Filing Date: 2015-09-08
Classification: H03K

Abstract:
1. A pulse stretching circuit, comprising: A pulse stretching circuit, comprising: a pulse delay circuit having a pulse delay circuit input for receiving an input pulse signal and a pulse delay circuit output for outputting a delay pulse signal; and a pulse adjustment circuit connected to the pulse delay circuit, the pulse adjustment circuit receiving the input pulse signal and the delay pulse signal and outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal, wherein the pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, and a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal, the input pulse signal having a first pulse width and the delay pulse signal having a second pulse width, the first and the second pulse width including a completely non-overlapping relationship with respect to each other, and wherein the pulse adjustment circuit includes: a latch circuit having a set input and a reset input, the set input receiving the input pulse signal and the reset input receiving the delay pulse signal, wherein the delay pulse signal is a delayed version of the input pulse signal, the latch circuit including a latch circuit output for generating a latch circuit output signal based on the received input pulse signal and the received reset input, and an OR circuit having a first, a second, and a third OR circuit input, the first OR circuit input connected directly to the input pulse signal, the second OR circuit input connected directly to the pulse delay circuit output, and the third OR circuit input connected directly to the latch circuit output, wherein the first and the second input of the OR circuit receive the input pulse signal and the delay pulse signal that is the delayed version of the input pulse signal.