Patent ID: 6150281
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method for fabricating contact holes in a semiconductor device, comprising the steps of:(a) providing a semiconductor substrate where first and second conductive regions are formed;(b) forming a lower interdielectric layer on the semiconductor substrate;(c) forming an etching barrier layer on the lower interdielectric layer;(d) forming a first hole and a second hole in the etching barrier layer, said first hole overlying the first conductive region, said second hole overlying the second conductive region;(e) etching the lower interdielectric layer, using the first hole as an etching mask, thereby forming a first contact hole exposing the first conductive region;(f) forming a conductive line overlying the etching barrier layer and filling the first contact hole;(g) forming an upper interdielectric layer on the conductive line;(h) forming a mask pattern on the upper interdielectric layer, said mask pattern defining a third contact hole overlying the second hole; and(i) etching the upper interdielectric layer, using the mask pattern as an etching mask, thereby forming the third contact hole, and etching the lower interdielectric layer, using the second hole as an etching mask, thereby forming a second contact hole exposing the second conductive region.