Patent ID: 8981568
Filing Date: 2015-03-17
Classification: B23K,H01L

Abstract:
1. A semiconductor package comprising: a substrate comprising a plurality of first pads on a first surface and a plurality of second pads on a second surface, each of the first pads electrically coupled to one or more of the second pads; at least one semiconductor device comprising a first surface located proximate the first surface of a substrate and a second surface with terminals oriented to face away from the first surface of the substrate; at least one simulated wirebond comprising at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first wirebond contact pads and second wirebond contact pads, and conductive traces electrically coupling the first and second wirebond contact pads, the conductive traces formed in the recesses comprise a generally rectangular cross-sectional shape, the first wirebond contact pads electrically coupled to the terminals on the semiconductor device and the second wirebond contact pads electrically coupled to the first pads on the first surface of the substrate so the simulated wirebond extends from the first surface of the substrate to the second surface of the semiconductor device; and overmolding material sealing the semiconductor device and the simulated wirebonds to the first surface of the substrate.