Patent ID: 7834469
Filing Date: 2010-11-16
Classification: H01L

Abstract:
1. A stacked type chip package structure, comprising: a lead frame, comprising a plurality of first leads and second leads insulated from one another, wherein the first leads have a first upper surface and the second leads have a second upper surface which is not co-planar with the first upper surface; a chip package, disposed on the first upper surface of the first leads, the chip package comprising: a second chip, stacked on the chip package and electrically connected to the second leads; and a second molding compound, disposed on the lead frame and filled among the first leads and the second leads to encapsulate the chip package and the second chip, wherein the second molding compound has a lower surface, and each of the first leads and the second leads includes an upper portion, the upper portion of each of the first leads attached to the lower surface of the second molding compound, the upper portion of each of the second leads encapsulated by the second molding compound, and a lower portion, protruding from the lower surface of the second molding compound.