Patent ID: 6862730
Filing Date: 2005-03-01
Classification: G06F

Abstract:
1. A code translation device that translates a source code into a target code, the device comprising: a memory; a source processor; a target processor; and a controller that: divides the source code into first source code blocks based on branches and loops in the source code, divides the first source code blocks into second source code blocks based on target register capability, wherein: a largest number of source registers required in each second source code block being less than or equal to a maximum number of target registers that correspond to the source registers, and converts each of the second source code blocks directly into a corresponding target code block; wherein the controller identifies source register types as data registers or address registers of the source processor and corresponding target registers of the target processor that correspond to each of the source register types, selects one or more identified source register types and one or more maximum numbers of corresponding target registers that correspond to the selected source register types, and generates a source register map having a number of storage locations based on a number of instruction cycles required to update a source register.