Patent ID: 6247162
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A method for generating layout data of external power wirings that supply a power supply voltage to a plurality of power supply terminals in each block provided in a semiconductor integrated circuit device, the method comprising the steps of:acquiring design information of the semiconductor integrated circuit device including external power wiring layout information, block layout information, and block current consumption values;calculating a current consumption ratio for each power supply terminal of each block using the block layout information;calculating the current consumption for each power supply terminal using the corresponding calculated current consumption ratio and the block current consumption value;generating an external power network of the external power wirings using the external power wiring layout information;analyzing the external power network to calculate voltage and current values for a plurality of parts of the external power wirings; andgenerating a structure of the external power wirings in accordance with the calculated voltage and current values.