Patent ID: 9083973
Filing Date: 2015-07-14
Classification: H04N

Abstract:
1. A coding and decoding apparatus comprising: one or more processors; and non-transitory storage coupled to the one or more processors, the non-transitory storage including coding instructions for performing a coding process for coding a picture signal for a first unit including one or more second units, and decoding instructions for performing a decoding process for decoding a coded picture signal for a third unit including one or more fourth units; wherein the one or more processors are configured to perform the coding process, the coding process including: wherein the one or more processors are further configured to perform the decoding process, the decoding process including: performing an arithmetic decoding process on the luminance CBF flag using the selected one of the third probability table and the fourth probability table; and wherein when the size of the second unit is a first size which is not identical to the size of the first unit, the selecting included in the coding process selects the second probability table, wherein when the size of the second unit is a second size which is not identical to the size of the first unit and not identical to the first size, the selecting included in the coding process selects the second probability table, wherein when the size of the fourth unit is a third size which is not identical to the size of the third unit, the selecting included in the decoding process selects the fourth probability table, and wherein when the size of the fourth unit is a fourth size which is not identical to the size of the third unit and not identical to the third size, the selecting included in the decoding process selects the fourth probability table.