Patent ID: 6686655
Filing Date: 2004-02-03
Classification: H01L,H05K,Y02P,Y10T

Abstract:
A package having a substrate having a plurality of circuits and a cage for enclosing a plurality of semiconductor devices for connecting said plurality of semiconductor devices to said plurality of circuits of said substrate comprising:a plurality of encapsulated semiconductor devices in a substantially vertical stack, each encapsulated semiconductor device having an upper surface, a lower surface, a first lateral edge located between said upper surface and said lower surface, a second lateral edge located between said upper surface and said lower surface, and a plurality of outer leads extending from said first lateral edge and said second lateral edge, adjacent encapsulated semiconductor devices of said plurality of encapsulated semiconductor devices having portions thereof attached to each other; a cage for partially enclosing and retaining said plurality of encapsulated semiconductor devices in said substantially vertical stack, said cage having a wall located adjacent said plurality of encapsulated semiconductor devices in said substantially vertical stack, said cage including: a flexible member generally perpendicular to said upper surface and said lower surface of said encapsulated semiconductor device of said stacked plurality of encapsulated semiconductor devices, said flexible member comprising a layer of material on an inner surface of a portion of said cage, a second flexible member overlying said layer of material attached thereto, and at least one node on an interior of said cage wall adjacent said plurality of encapsulated semiconductor devices retaining said plurality of encapsulated semiconductor devices in said substantially vertical stack in said cage, said at least one node comprising a removable polymeric adhesive attaching said plurality of encapsulated semiconductor devices in said substantially vertical stack to said cage; and a conductive bus line formed on said flexible member, said conductive bus line extending substantially perpendicular to said plurality of encapsulated semiconductor devices in said substantially vertical stack, contacting an equivalent outer lead of said plurality of outer leads of each encapsulated semiconductor device of said plurality of encapsulated semiconductor devices, and connecting to at least one circuit of said plurality of circuits of said substrate.