Patent ID: 6578097
Filing Date: 2003-06-10
Classification: G06F

Abstract:
An apparatus for transmitting registered data onto a PCI bus, comprising:a data buffer for storing a plurality of registered data and outputting a current data signal and a next data signal according to a current phase data pointer and a next phase data pointer, respectively; an address buffer for storing address signals and outputting current address signal according to a current phase address pointer; a first multiplexer coupled to said data buffer and said address buffer for selecting said current data signal or said current address signal according to an address phase Select signal; a logic gate for receiving an IRDY# signal and a TRDY# signal from said PCI Bus and outputting a data Transfer Select signal; a second multiplexer coupled to said data buffer and said first multiplexer for selecting the output of said first multiplexer or said next data signal according to said data Transfer Select signal; and, a flip-flop coupled to said second multiplexer for toggling the output signal of said second multiplexer to said PCI Bus according to a reference clock.