Patent ID: 6716732
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method of fabricating a contact pad of a semiconductor device, the method comprising:(a) forming a gate structure including a gate upper dielectric layer on a semiconductor substrate; (b) forming a stopping layer over the semiconductor substrate; (c) forming an interdielectric layer over the stopping layer; (d) planarizing the interdielectric layer to expose at least the gate upper dielectric layer using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer; (e) etching the interdielectric layer in a region in which a contact pad will be formed on the semiconductor substrate; (f) depositing a conductive material for the contact pad on the semiconductor substrate; and (g) planarizing using a material which exhibits a high-polishing selectivity of the gate upper dielectric layer with respect to the conductive material.