Patent ID: 6219812
Filing Date: 2001-04-17
Classification: G01R

Abstract:
An apparatus for adapting boundary-scan test circuitry to support multiple signal modes, comprising:a first logic circuit to translate driver control signals into boundary-scan signals, said driver control signals being adapted for Dinamyc Termination Logic with on-chip drivers operating as parallel terminators;a first boundary-scan register (BSR) coupled to said first logic circuit, to store boundary-scan signals;a second BSR coupled to said first logic circuit, to store said boundary-scan signals;a second logic circuit coupled to said first BSR and to said second BSR, to translate boundary-scan signals into driver control signals; anda third logic circuit having a driver, said third logic circuit coupled to said second logic circuit, said third logic circuit configured so that said driver provides, in response to driver control signals received from said second logic circuit, a function equivalent to a response of a boundary-scan driver to boundary-scan signals from first and second BSRs.