Patent ID: 8686501
Filing Date: 2014-04-01
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; an isolation region formed in said semiconductor substrate, the isolation region defining a first active region; a first well of a first conductivity type formed in said first active region; a first gate electrode formed above said first well, said first gate electrode including a first edge and a second edge which is located opposite to said first edge; a first drain region formed from a location outside said first edge of said first gate electrode to a location under said first gate electrode and between said first edge and said second edge as viewed in plan in said first well, said first drain region having a first impurity concentration of a second conductivity type opposite to said first conductivity type; a first channel region formed from a location outside said second edge of said first gate electrode to a location under said first gate electrode and between said first edge and said second edge as viewed in plan in said first well, forming an overlap region which overlaps a portion of said first drain region under said first gate electrode, said overlap region being located between said first edge and said second edge as viewed in plan in said first well, said first channel region having a second impurity concentration of said first conductivity type; a source region of said second conductivity type formed outside said second edge of said first gate electrode as viewed in plan in said first well; and a second drain region of said second conductivity type formed outside of said first edge of said first gate electrode and spaced apart from said first gate electrode as viewed in plan in said first well, said second drain region having a third impurity concentration higher than said first impurity concentration, wherein a part of said first channel region located between said second edge of said first gate electrode and said overlap region has a fourth effective impurity concentration of the first conductivity type higher than a fifth effective impurity concentration of said overlap region, and a sixth effective impurity concentration of the second conductivity type of an intermediate region between said first edge of said first gate electrode and said second drain region, in said first drain region, is higher than the fifth effective impurity concentration of said overlap region.