Patent ID: 6460112
Filing Date: 2002-10-01
Classification: G11C,H04L

Abstract:
A content addressable memory (CAM) array comprising:a first plurality of memory cells for storing first data; a first plurality of compare circuits for comparing the first data or masked data with search data to generate first comparison results; a plurality of data compare lines for carrying the search data; a second plurality of memory cells for storing mask data corresponding to the first data; a second plurality of compare circuits for comparing a longest mask data with the mask data to generate second comparison results; a plurality of mask compare lines for carrying the longest mask data for the second compare circuits; a plurality of first match lines coupled to the first compare circuits to receive the first comparison results; a plurality of masking circuits each coupled to a corresponding one of the first memory cells and the second memory cells to selectively provide the first data or the masked data to the first compare circuits in response to the mask data; a plurality of prefix signal lines; and a plurality of prefix logic circuits each having a first input coupled to one of the first match lines, a second input coupled to receive the mask data from one of the second memory cells, and an output coupled to one of the plurality of prefix signal lines.