Patent ID: 8817992
Filing Date: 2014-08-26
Classification: G10L

Abstract:
1. An apparatus comprising at least one processor and at least one memory including computer program code the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to: divide a first and a second signal into a plurality of time frames; determine a first time delay associated with a delay between a start of a time frame of the first signal and a start of a time frame of the second signal; determine a second time delay associated with a delay between an end of the time frame of the first signal and an end of the time frame of the second signal; select from the second signal at least one sample from a block of samples, wherein the block of samples is defined as starting at the start of the time frame of the second signal offset by the first time delay and finishing at the end of the time frame of the second signal offset by the second time delay; generate a third signal by stretching the selected at least one sample to equal the number of samples of the time frame of the first signal; and combine the first and third signal to generate a fourth signal.