Patent ID: 6490706
Filing Date: 2002-12-03
Classification: H03H

Abstract:
A method for making a filter circuit comprising at least one filter stage, the method comprising:a) providing the at least one filter stage with a gyrator core section having four inverters mutually connected in a loop configuration between a pair of input terminals and a pair of output terminals; b) providing at least one common mode feedback section, the at least one common mode feedback section being connected between at least one said pair of input terminals and said pair of output terminals and comprising two series connections respectively formed by an inverter and a short-sectioned inverter connected antiparallely between at least one of said input terminals and said output terminals, each of said inverters including at least one of a MOS, CMOS, and BiCMOS transistor, the at least one of a MOS, CMOS, and BiCMOS transistor having a gate, drain, source, and a channel region between said drain and source, and c) wherein the channel region dimensions of the transistors of at least one of the gyrator core section and the common mode feedback section are selected such that the following relationship is fulfilled: g*C&gE;gm*cm where: g=effective conductive loading of the gyrator core section terminals; C=effective capacitive loading of the gyrator core section terminals; gm=effective gyrating constant of the gyrator core section; and cm=effective transcapacitance of the gyrator core section.