Patent ID: 7979761
Filing Date: 2011-07-12
Classification: G11C

Abstract:
1. A memory test device to test an external memory, comprising: a universal register to conduct an operation by a predetermined universal command language; an extension register having a larger capacity than the universal register, to conduct an operation by a predetermined extension command language; and a controller to write a predetermined test pattern in the external memory using the extension command language, to read the test pattern written in the memory, to compare the written test pattern and the read test pattern, and to determine a presence of an error in the external memory according to the comparison using the universal command language, wherein the universal register has a predetermined capacity of N bytes, where N is an integer, wherein the controller compares the written test pattern and the read test pattern in an N-byte unit, and wherein the size of units used for reading and writing the test pattern is larger than the size of the N-byte unit.