Patent ID: 7649241
Filing Date: 2010-01-19
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, and an upper electrode formed on the dielectric layer, the capacitor being formed on a semiconductor substrate; a first insulating layer formed on the semiconductor substrate to cover the capacitor; a plurality of first contact plugs formed in a plurality of first via holes of the first insulating layer, each of the plurality of first contact plugs being electrically connected to either the bottom electrode or the upper electrode; a first metal wiring formed on the first insulating layer and connected to the bottom electrode through one of the first contact plugs; a second insulating layer formed on the first insulating layer; a second contact plug in the second insulating layer formed on the first insulating layer and connected to the upper electrode through another one of the first contact plugs; an anti-fuse formed on the second contact plug in a second via hole of the second insulating layer; a third contact plug filling the second via hole and formed within the anti-fuse, wherein the third contact plug does not directly contact the second insulating layer; and a second metal wiring formed on the second insulating layer and electrically connected to the third contact plug and the anti-fuse.