Patent ID: 7818526
Filing Date: 2010-10-19
Classification: G11C

Abstract:
1. A semiconductor memory device for measuring a data access time by controlling data output operation, comprising: a test mode signal generation unit for generating a test mode signal in order to measure the data access time during a test mode measuring the data access time; a pipe latch control unit for generating an input control signal in response to the test mode signal; a pipe latch unit for outputting data from memory cells according to a column address strobe (CAS) latency in synchronization with a clock signal at a normal mode which is a data access mode and passing the data without synchronization with the clock signal at the test mode in response to the input control signal; an output control unit for generating an output node control signal based on the test mode signal; and an output unit for outputting data received from the pipe latch unit in response to a transition of a delay locked loop (DLL) clock signal at the normal mode and passing data received from the pipe latch unit in response to a predetermined logic level of the DLL clock signal wherein the output unit is enabled in response to the output node control signal; wherein the output control unit includes a DLL clock signal generator for outputting the DLL clock during the normal mode and outputting the DLL clock signal that maintains a constant level without oscillating as time elapses during the entire test mode to the output unit in response to the test mode signal during the test mode, wherein the output unit outputs the data received from the pipe latch unit without being synchronized with DLL rising and falling clock signals during the test mode.