Patent ID: 6310384
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A semiconductor device including:a semiconductor substrate;a plurality of circuit regions formed on device formation regions in said semiconductor substrate;device isolation regions provided as grooves, each groove having a depth, extending inwardly from a main surface of said semiconductor substrate, greater than 6 nm and formed before thermal oxide film formation thereof as to isolate said plurality of circuit regions from one another on said semiconductor substrate, andmeans for preventing stress at portions of the main surface of the substrate located adjacent mask ends of a mask used to form the grooves from exceeding a dislocation occurrence limit stress value which is otherwise likely to occur, based on the depth of the grooves exceeding 6 nm, to cause dislocation at said portions of the main surface of the substrate, by setting a ratio of the width of a circuit region to a width of an adjacent device isolation region within a predetermined range.