Patent ID: 6806785
Filing Date: 2004-10-19
Classification: H01L,H03B

Abstract:
An oscillator circuit, comprising:a supply voltage source having a supply potential terminal and a reference-ground potential terminal; a carrier; a semiconductor chip having a front side and a rear side fixed to said carrier; an oscillator core integrated on said semiconductor chip, said oscillator core including a pair of first circuit nodes, a first capacitance, a first inductor connected to said first capacitance at a first one of said pair of first circuit nodes, a second capacitance, and a second inductor connected to said second capacitance at a second one of said pair of first circuit nodes; a de-attenuation amplifier integrated on said semiconductor chip, said de-attenuation amplifier coupled to said oscillator core and to said supply voltage source; a resonance transformation circuit for coupling said oscillator core and said de-attenuation amplifier; a pair of second circuit nodes; a third inductor connected to a first one of said pair of second circuit nodes; a fourth inductor connected to a second one of said pair of second circuit nodes; and a pair of contact points; said first inductor formed as a bonding wire having a first terminal connected to a first one of said pair of contact points and a second terminal connected to said carrier; said second inductor formed as a bonding wire having a first terminal connected to a second one of said pair of contact points and a second terminal connected to said carrier; said first one of said pair of contact points connected to said first one of said pair of first circuit nodes; said second one of said pair of contact points connected to said second one of said pair of first circuit nodes; said resonance transformation circuit including a first coupling capacitor connected to said first one of said pair of first circuit nodes and to said first one of said pair of second circuit nodes; said resonance transformation circuit including a second coupling capacitor connected to said second one of said pair of first circuit nodes and to said second one of said pair of second circuit nodes.