Patent ID: 7546563
Filing Date: 2009-06-09
Classification: G06F

Abstract:
1. A method comprising: accessing a circuit; generating one or more seeds from one or more binary decision diagrams (BDDs) for executing two or more instances of validation of the circuit, the one or more BDDs representing one or more state spaces of the circuit, each instance being executable to validate one or more portions of the circuit, each instance comprising one or more tasks, each task comprising a particular portion of the instance comprising it; distributing to each of two or more nodes one or more particular ones of the one or more seeds and one or more particular ones of the one or more instances, each node comprising one or more computer systems operable to perform one or more of the one or more tasks of the one or more particular instances distributed to the node; and using the one or more seeds, executing the two or more instances at the two or more nodes independent of and in parallel with each other, the execution of each of the two or more instances comprising executing satisfiability (SAT) based bounded model checking (BMC) starting from one of the one or more seeds.