Patent ID: 9047943
Filing Date: 2015-06-02
Classification: G11C,H01L

Abstract:
1. A non-volatile storage system, comprising: a memory array, the memory array includes a plurality of word lines and a plurality of bit lines, the memory array comprises a cross-point memory array including a plurality of rewriteable non-volatile memory cells, each memory cell of the plurality of rewriteable non-volatile memory cells includes a reversible resistance-switching element without an isolation element in series with the reversible resistance-switching element; and one or more managing circuits in communication with the memory array, the one or more managing circuits set the memory array into a standby mode prior to receiving a read command, the one or more managing circuits determine a selected bit line of the plurality of bit lines and a plurality of unselected bit lines of the plurality of bit lines based on the read command, the one or more managing circuits determine a selected word line of the plurality of word lines and a plurality of unselected word lines of the plurality of word lines based on the read command, the one or more managing circuits cause the plurality of unselected word lines to be set to an unselected voltage, the one or more managing circuits cause the plurality of unselected bit lines to be floated, the one or more managing circuits cause the selected bit line to be biased to the unselected voltage, the one or more managing circuits cause the selected word line to be biased to a read voltage greater than the unselected voltage, the one or more managing circuits determine a state of a memory cell connected to the selected word line and the selected bit line while the selected word line is biased to the read voltage and the plurality of unselected bit lines are floated.