Patent ID: 6396078
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having an insulating surface; a gate electrode formed on the insulating surface; a gate insulating film formed on the gate electrode; a semiconductor island formed on the gate insulating film, said semiconductor island comprising a source region, a drain region and a channel region; a first interlayer insulating film comprising silicon nitride and formed on and in direct contact with the semiconductor island; a second interlayer insulating film comprising silicon oxide and formed on the first interlayer insulating film, said second interlayer insulating film including: a first dielectric layer formed on the first interlayer insulating film, and a second dielectric layer formed on the first dielectric layer, wherein the second dielectric layer has a higher etching rate than the first dielectric layer; a contact hole in the first and second interlayer insulating films on one of the source and drain regions; and a lead formed through the first and second interlayer insulating films and connected to the one of the source and drain regions, wherein the contact hole has a tapered configuration, wherein a diameter of the contact hole increases from a lower portion thereof to an upper portion thereof, wherein each of the first and second dielectric layers is formed through plasma CVD, wherein the second dielectric layer is formed with a smaller radio frequency power than the first dielectric layer.