Patent ID: 6255155
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method for manufacturing a memory comprising:on a substrate having a selection transistor region and a cell transistor region defined thereon, forming stacked first and second selection gate lines on the selection transistor region;forming floating gates on the substrate on the cell transistor region;forming control gate lines over and extending between the floating gates formed on the substrate;forming impurity regions in the substrate adjacent the first selection gate line and the control gate line;forming a first planar protection film over the stacked first and second selection gate lines and the floating gates;forming first contact holes in the first planar protection film and the second selection gate line to expose a portion of the first selection gate line and a portion of an impurity region formed in the substrate;forming conductive plugs in the first contact holes;forming a metal contacts electrically connected to the conductive plugs;forming a second planar protection film over the first planar protection film and the metal contacts;forming second contact holes in the second planar protection film to expose portions of the respective metal contacts; andforming a metal line over the second planar protection film and in the second contact holes so as to electrically contact the exposed portions of the metal contacts.