Patent ID: 7073045
Filing Date: 2006-07-04
Classification: G06F

Abstract:
1. A memory interface circuit comprising: an address generating unit for outputting an internal address received from a central processor to an external memory as an access address when the internal address is a branch address, and for incrementing the branch address by one at every access cycle and outputting the incremented branch address as the access address until a next branch address is received, said access address being for prefetching instruction data stored in said external memory; a plurality of prefetch buffers each having a tag register for storing a branch address, and a data register for storing instruction data stored in an area of said external memory designated by the branch address stored in the tag register; a first address comparing unit for activating a tag hit signal when said internal address coincides with the branch address stored in the tag register; a data selecting unit for outputting, to said central processor, instruction data read from the data register corresponding to the tag register containing the hit branch address when said tag hit signal is activated, and outputting, to said central processor, instruction data corresponding to the branch address read from said external memory when said tag hit signal is inactivated; and a main control unit for controlling operation of said address generating unit, said first address comparing unit, and said data selecting unit during a normal operation period in which said central processor outputs internal addresses successively, and wherein each of said prefetch buffers is assigned to either a first prefetch buffer which is rewritable during said normal operation period or a second prefetch buffer to be disabled for rewrite during said normal operation period and containing in advance a specified branch address and instruction data stored in an area of said external memory designated by the specified branch address.