Patent ID: 8751733
Filing Date: 2014-06-10
Classification: G06F,G11C

Abstract:
1. An electronic system comprising: a processor coupled through a standard interface to a memory device comprising: a first array of memory cells each memory cell having a first density; a second array of memory cells each memory cell having a second density; and control circuitry, wherein the processor is configured, based on usage data of a logical address in the memory device, to instruct the control circuitry to store data associated with the logical address in one of the first array and second array of memory cells at least partially based on the usage and wherein the processor is further configured to instruct the control circuitry to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.