Patent ID: 7902020
Filing Date: 2011-03-08
Classification: H01L

Abstract:
1. An apparatus comprising: a first conductivity-type deep well formed in a substrate; a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed; a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers; a first gate pattern formed over a portion of the second conductivity-type well; a second gate pattern formed over one of the device isolation layers; a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern; a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern; and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from the second conductivity-type well.