Patent ID: 7713815
Filing Date: 2010-05-11
Classification: H01L

Abstract:
1. A method, comprising: forming a recess in a semiconductor layer; forming a first portion of an insulation layer on said semiconductor layer and on an exposed surface of said recess; forming a plurality of transistor elements in and on said semiconductor layer, said plurality of transistor elements defining an arithmetic unit, wherein said insulation layer formed on said semiconductor layer defines a gate dielectric layer for said plurality of transistor elements; forming a decoupling capacitor in said recess, wherein said first portion of said insulation layer formed on said exposed surface defines a dielectric layer of said decoupling capacitor; depositing a conductive material to fill said recess; planarizing a surface topography of said conductive material to form a conductive layer; patterning said conductive layer to define gate electrodes of said plurality of transistor elements and to define an electrode portion for an inner electrode of said decoupling capacitor in a common patterning process, wherein said electrode portion extends above a surface of the semiconductor layer; and connecting said decoupling capacitor to said arithmetic unit.