Patent ID: 9087877
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method for forming an integrated circuit, the method comprising: forming a low-k dielectric layer over a semiconductor substrate; etching the low-k dielectric layer to form an opening; forming a dielectric barrier layer covering at least sidewalls of the opening, wherein the dielectric barrier layer comprises α-Terpinene (ATRP); performing a treatment to the dielectric barrier layer, the treatment forming a treated dielectric barrier layer consisting essentially of dielectric material, wherein process gases used in the step of performing the treatment comprise a nitrogen-containing gas and SiH removing the bottom portion of the treated dielectric barrier layer, and wherein sidewall portions of the treated dielectric barrier layer are not removed; and after the step of removing the bottom portion of the treated dielectric barrier layer, filling the opening with a conductive material, wherein the conductive material contacts the dielectric material of the treated dielectric barrier layer along substantially the entire sidewall of the opening.