Patent ID: 6400932
Filing Date: 2002-06-04
Classification: H03H,H03L

Abstract:
A frequency tuning circuit which comprises:integrating means for receiving a current multiplied by an offset voltage of each of Gm cells, receiving a first reference voltage and a second reference voltage from an external, generating a current multiplied by a voltage difference of the first reference voltage and the second reference voltage, generating a signal discharging from the first reference voltage to a first predetermined value and a signal charging from the second reference voltage to a second predetermined value according to the generated current, and tuning the Gm cells according to a control signal inputted to a control terminal; offset sampling means for receiving the current multiplied by the offset voltages from the Gm cells of the integrating means, sampling the offset voltages of the Gm cells by providing a feedback path between output nodes and input nodes of the Gm cells and generating a current multiplied by the sampled offset voltage, and tuning the Gm cells according to the control signal inputted to the control terminal; comparative signal generating means for generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and generating a comparative signal to compare an actual intersection and a target intersection of these signals; and control means for generating a control signal to regulate Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting phase differences therebetween.