Patent ID: 6404239
Filing Date: 2002-06-11
Classification: H01L,H03K

Abstract:
A semiconductor integrated circuit comprising:a circuit block including a first MOS transistor of which source-drain path is coupled between a first node and a second node; and a control circuit coupled between said first node and a third node; and wherein in a case that a control signal is in a first mode, said control circuit allows a current flowing between said first node and said second node through said source-drain path of said first MOS transistor being an on state, wherein in a case that said control signal is in a second mode, said control circuit limits a leak current flowing between said first node and said second node through said source-drain path of said first MOS transistor being an off state, wherein said leak current flows through the source-drain path of said first MOS transistor, even if the voltage difference between a gate and a source of said first MOS transistor is 0 volts, wherein the state of said control signal is changed from said second mode to said first mode, after a voltage of said third node reaches a predetermined voltage level during a rise of power.