Patent ID: 6140826
Filing Date: 2000-10-31
Classification: G01R,H05K

Abstract:
A method of performing a failure analysis on an integrated circuit chip package comprising the steps of:providing an integrated circuit chip package having a plurality of pin leads extending therefrom, a top surface adjacent to bonding wires in the chip, and a bottom surface adjacent to an active device in the chip,providing a printed circuit board having a plurality of terminals on a top surface and a recess, said plurality of terminals having inner ends adapted for engaging said pin leads on said integrated circuit chip package, and outer ends terminating at an periphery of the board,positioning the integrated circuit chip package in the recess of the printed circuit board with the bottom surface of the package facing upward and connecting electrically the pin leads on the package to the inner ends of said terminals on the board,removing a layer off the bottom surface of said package while maintaining substantially the electrical connection between the pin leads on the package and the inner ends of the terminals on the board, andconnecting said outer ends of said plurality of terminals to external circuits for performing failure analysis.