Patent ID: 6124739
Filing Date: 2000-09-26
Classification: H03K

Abstract:
A monolithically integrated signal processing, circuit, comprising:a signal series branch connected between a signal input terminal and a signal output terminal;a reference potential terminal;a series capacitor inserted in serial manner in the signal series branch and having a parasitic capacitance acting like a capacitor that is connected between a first electrode of the series capacitor directed towards the signal input terminal and the reference potential terminal;a first parallel capacitor connected directly between the first electrode of the series capacitor and the reference potential terminal with the first parallel capacitor being constituted at least in part by the parasitic capacitance;wherein the first parallel capacitor is connected to the signal series branch at a circuit node;between the signal input terminal and the circuit node, there is connected a first controllable ON/OFF switch which in the conducting state connects the circuit node to the signal input terminal;between the circuit node and the reference potential terminal, there is connected a series connection comprising a second parallel capacitor and a second controllable ON/OFF switch, said second switch, when in the conducting state, connecting the second parallel capacitor in parallel to the first parallel capacitor;between the series capacitor and the signal output terminal, there is connected an offset-inflicted comparator by means of which an analog signal can be reshaped to a square wave signal in threshold-dependent manner and which comprises a comparator signal input connected to the series capacitor, a comparator reference voltage input connected to a second reference potential terminal for connection to a threshold-determining reference potential, and a comparator output directed towards the signal output terminal; andbetween the comparator signal input and the comparator output, there is connected a controllable third switch which in the conducting state connects the comparator signal input and the comparator output to each other wherein the series capacitor serves as an offset storage capacitor;during window periods lying between the occurrence of adjacent edges of the square wave signal, the first switch can be controlled to the non-conducting state and the second switch and the third switch can be controlled to the conducting state; andduring the remaining time, the first switch can be controlled to the conducting state and the second switch and the third switch can be controlled to the non-conducting state.