Patent ID: 6107154
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method for fabricating an embedded DRAM device, the method comprising the steps of:preparing a semiconductor substrate which is partitioned into a transfer field effect transistor (FET) area and a logic circuit area;forming a first FET in the transfer FET area, the first FET including one polysilicon gate and one pair of associated source/drain regions;forming a second FET in the logic circuit area, the second FET including one polysilicon gate and one pair of associated source/drain regions;forming sidewall spacers on the sidewalls of the polysilicon gates of the first and second FETs;performing a selective epitaxial growth process so as to form a plurality of amorphous silicon layers over the polysilicon gates and source/drain regions of the first and second FETs;forming a metal layer over the entire top surface of the wafer;performing an annealing process to allow the forming of a metal silicide layer from a reaction between the metal layer and each of the amorphous silicon layers, wherein the amorphous silicon layers are entirely used to form the metal silicide;removing unreacted portions of the metal layer;forming a dielectric layer over the entire top surface of the wafer; andforming a capacitive element over the dielectric layer, the capacitive element being electrically coupled to one of the source/drain regions of the first FET.