Patent ID: 8716115
Filing Date: 2014-05-06
Classification: B01J,C23C,H01L

Abstract:
1. A method for forming capacitor structures on a substrate in a combinatorial manner, comprising: depositing a bottom patterned electrode layer on the substrate by depositing a bottom conductive material through one or more apertures in a first shadow mask, the bottom patterned electrode layer comprising bottom electrodes; defining site isolated regions on the bottom patterned electrode layer; depositing a dielectric layer on each of the site isolated regions, wherein at least one property of the dielectric layer is varied in a combinatorial manner among the dielectric layers in each region; and depositing a top patterned electrode layer on the dielectric layer by depositing a top conductive material through apertures in a second shadow mask, the top patterned electrode layer comprising multiple top electrodes; wherein the multiple top electrodes and multiple bottom electrodes overlap to form multiple capacitor structures; wherein each of the multiple capacitor structures comprises an interstitial dielectric area; and wherein the interstitial dielectric areas of the multiple capacitor structures have different sizes.