Patent ID: 6344398
Filing Date: 2002-02-05
Classification: H01L

Abstract:
A method for forming different spacer for different transistor devices on a semiconductor substrate, said method comprising of:forming at least a first conductive gate, a second conductive gate and a third conductive gate on said substrate; forming a first oxide layer over said first conductive gate, said second conductive gate and said third conductive gate; performing a first etch operation to form an oxide spacer along each sidewall of said first conductive gate, said second conductive gate and said third conductive gate; a first mask over said first conductive gate, while exposing said second conductive gate and said third conductive gate; removing said oxide spacer along each sidewall of said second conductive gate and said third conductive gate; removing said first mask over said first conductive gate; forming a silicon nitride layer over said first conductive gate with said oxide spacer formed along each sidewall thereof, said second conductive gate and said third conductive gate, wherein the thickness of said silicon nitride layer is different from that of said first oxide layer; performing a second etch operation to form a spacer of silicon nitride along each sidewall of said second conductive gate and said third conductive gate; forming a second conformal oxide layer over said first conductive gate, said second conductive gate and said third conductive gate; forming a second mask over said second conformal oxide layer formed on said second conductive gate, while exposing said second conformal oxide layer over said first conductive gate and said third conductive gate; removing said second conformal oxide layer over said first conductive gate and said third conductive gate; removing said second mask over said second conformal oxide layer formed on said second conductive gate; and removing said spacer of silicon nitride formed along each sidewall of said third conductive gate.