Patent ID: 6438038
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A read circuit of a nonvolatile semiconductor memory comprising:at least one sense amplifier; and a read control signal generating circuit for supplying a first signal to said at least one sense amplifier, wherein said at least one sense amplifier includes: a first P-channel MOS transistor having a source electrically connected to a first power supply node; a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell, and having a gate applied with a second signal; a first inverter, said first inverter includinga second P-channel MOS transistor having a gate applied with said first signal, a source electrically connected to said first power supply node, and a drain connected to the gate of said first N-channel MOS transistor; and a second N-channel MOS transistor having a gate connected to a first connection node between said first N-channel MOS transistor and said memory cell, a source connected to a second power supply node, and a drain connected to the gate of said first N-channel MOS transistor; and a third N-channel MOS transistor having a gate connected to the gate of said first N-channel MOS transistor, a drain connected to said first power supply node through a switch transistor, and a source connected to said first connection node, and a bit line precharged in a read operation by supplying charges from said third N-channel MOS transistor to said first connection node.