Patent ID: 6110772
Filing Date: 2000-08-29
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device carrying a capacitor and a resistance element being integrated on a single circuit substrate, comprising steps of:forming a first insulating layer on either the substrate of the semiconductor device or a predetermined semiconductor layer;forming an a-Si layer on a surface of the first insulating layer;doping the a-Si layer with impurities;heating the a-Si layer doped with impurities to diffuse the impurities to thereby form a first lower electrode;forming a second insulating layer on the first lower electrode, having an opening where the first lower electrode is partially exposed;forming a SiN dielectric layer in the opening and on a predetermined resistance layer formation region; andforming an a-Si layer covering the opening and the resistance layer formation region on the surface of the SiN dielectric layer to therewith constitute a first upper electrode and a resistance layer, respectively.