Patent ID: 6476631
Filing Date: 2002-11-05
Classification: G01R

Abstract:
A method for testing a series of functional blocks within an integrated circuit, the method comprising the steps of:testing each of the functional blocks in the series to determine a minimum parameter value associated with each of the functional blocks, calculating a minimum parameter delta value for each of the functional blocks in the series, where the minimum parameter delta value is the minimum parameter value associated with a given one of the functional blocks subtracted from the minimum parameter value for a functional block immediately following the given one of the functional blocks in the series, testing each of the functional blocks in the series to determine a maximum parameter value associated with each of the functional blocks, calculating a maximum parameter delta value for each of the functional blocks in the series, where the maximum parameter delta value is the maximum parameter value associated with the given one of the functional blocks subtracted from the maximum parameter value for the functional block immediately following the given one of the functional blocks in the series, comparing the minimum parameter delta value to a minimum parameter delta value tolerance limit, comparing the maximum parameter delta value to a maximum parameter delta value tolerance limit, selectively binning the integrated circuit based at least in part on whether the minimum parameter delta value for any of the functional blocks violates the minimum parameter delta value tolerance limit, and selectively binning the integrated circuit based at least in part on whether the maximum parameter delta value for any of the functional blocks violates the maximum parameter delta value tolerance limit.