Patent ID: 7348625
Filing Date: 2008-03-25
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a substrate; a first conductive layer provided on a first region of the substrate, and being insulated from the first region of the substrate; a second conductive layer provided on a second region of the substrate, the first region being spaced from the second region, the second conductive layer being insulated from the second region of the substrate; and a dielectric layer provided on a third region of the substrate, the third region being between the first and second regions, the dielectric layer for charge storage comprising a plurality of dielectric materials including a first insulating layer, a second insulating layer, and a third insulating layer, the third insulating layer being surrounded by the first insulating layer and second insulating layer; and a third conductive layer provided on the insulating layer, wherein upon application of first, second, and third biases to the first, second, and third conductive layers, respectively, the insulating layer receives and retains the carriers, and wherein the first, second, and third conductive layers are respectively a first assist gate line, a second assist gate line, and a word line.