Patent ID: 8039327
Filing Date: 2011-10-18
Classification: H01L

Abstract:
1. A transistor forming method comprising: providing an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate, the island having a fin of semiconductor material and the fin having a top, opposing sidewalls, and opposing endwalls and a portion of the island extending from the fin to an edge of the island; forming a dielectric spacer around the fin and over the portion of the island between the fin and the edge of the island, over the opposing sidewalls, and over the opposing endwalls, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness; forming line openings through the spacer and exposing through the line openings some of the semiconductor material between the fin and the edge of the island and some of the semiconductor material of the opposing sidewalls of the fin; forming a gate line on and in contact with the semiconductor material exposed above the spacer and the semiconductor material exposed through the line openings, the gate line extending through the line openings, over the opposing sidewalls, and over the top of the fin; and in operational association with the gate line, forming source/drain regions in the fin.