Patent ID: 9083327
Filing Date: 2015-07-14
Classification: G11C,H01L,H03K

Abstract:
1. A semiconductor device comprising: an arithmetic portion including a first node and a second node; a third node; a fourth node; a first transistor including a channel in an oxide semiconductor layer; a second transistor including a channel in an oxide semiconductor layer; and a comparator comprising a third transistor including a channel in a silicon wafer or a silicon film, wherein one of a source and a drain of the first transistor is electrically connected to the first node, wherein the other of the source and the drain of the first transistor is electrically connected to the third node, wherein one of a source and a drain of the second transistor is electrically connected to the second node, wherein the other of the source and the drain of the second transistor is electrically connected to the fourth node, wherein a non-inverting input terminal of the comparator is electrically connected to the third node, wherein an inverting input terminal of the comparator is electrically connected to the fourth node, wherein an output terminal of the comparator is electrically connected to the arithmetic portion, wherein an insulating film is over the third transistor, and wherein the first transistor and the second transistor are over the insulating film.