Patent ID: 6028795
Filing Date: 2000-02-22
Classification: G06T,G11C

Abstract:
A one chip semiconductor integrated circuit device comprising:a memory unit including a plurality of semiconductor memory elements;first terminals which are supplied with first signals;a second terminal which is supplied with a second signal;a third terminal which is supplied with a third signal; anda control unit which is coupled to said memory unit, said first terminals, said second terminal, and said third terminal,wherein during a write mode designation operation before a data write operation, write mode designation signals being said first signals are supplied from said first terminals to said control unit in response to a first predetermined combination of levels of said second signal and said third signal, and thereafter during said data write operation, said write data provided from an external device is written by said control unit into said memory unit in response to a second predetermined combination of levels of said second signal and said third signal in accordance with address signals being said first signals supplied from said first terminals, andwherein during a bits setting mode designation operation before a bits setting operations bits setting mode designation signals being said first signals are supplied from said first terminals to said control unit in response to said first predetermined combination of levels of said second signal and said third signal, and thereafter during said bits setting operation, said control unit sets a plurality of bits of said plurality of semiconductor memory elements of said memory unit into a predetermined logic level in response to said second predetermined combination of levels of said second signal and said third signal in accordance with address signals being said first signals supplied from said first terminals, said predetermined logic level being data irrespective of data provided by said external device.