Patent ID: 7149116
Filing Date: 2006-12-12
Classification: G11C

Abstract:
1. A programming method of semiconductor memory having a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors serially connected along a column-direction and a select transistor configured to select the memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix, the peripheral circuit, the programming method comprising: latching first data configured to be written into memory cell transistors in the first cell columns; latching second data configured to be written into memory cell transistors in the second cell columns after the first data are written into the memory cell transistors in the first cell columns; comparing the first data with the second data so as to determine shift of threshold voltages of memory cell transistors in the first cell columns, which are estimated to be induced by electric charges written in the memory cell transistors of the second cell columns; writing electric charges into memory cell transistors in the first cell columns, which correspond to the determined shift of threshold voltages; and writing second data into memory cell transistors in the second cell columns after the first data are written into the memory cell transistors in the first cell columns.