Patent ID: 6212092
Filing Date: 2001-04-03
Classification: G11C

Abstract:
A semiconductor integrated circuit comprising:a memory cell;a sense amplifier for amplifying data read from and written to said memory cell;an input/output controlling circuit comprising at least one of either a read controlling circuit receiving said data amplified by said sense amplifier in a read operation or a write controlling circuit for outputting said data to said sense amplifier in a write operation;a switching circuit for carrying out on/off control of a transmission path of said data between said sense amplifier and said input/output controlling circuit;a reference timing signal generator for generating a reference timing signal used in said read operation and said write operation;a timing controlling circuit for receiving said reference timing signal and for generating at least one of either a read controlling signal or a write controlling signal for controlling said input/output controlling circuit; anda switch controlling circuit for receiving said reference timing signal and for generating a switch controlling signal for the on/off control of said switching circuit, whereinsaid timing controlling circuit comprises a delay element identical or equivalent to a delay element existing in said switch controlling circuit.