Patent ID: 6986084
Filing Date: 2006-01-10
Classification: G01R,G11C

Abstract:
1. A method of testing a computer memory device, the method comprising: outputting to a memory device a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal; outputting to the memory device a first bank address signal defining a first bank of locations, within the memory device, to be precharged; outputting to the memory device a second bank address signal defining a second bank of locations, within the memory device, to be latched; outputting to the memory device a row address signal and a column address signal, the row address signal and the column address signal defining a test location within the latched bank of locations; receiving data stored at the test location; and comparing the received data with test data in order to test the integrity of the memory device.