Patent ID: 7936187
Filing Date: 2011-05-03
Classification: G11C,H03K

Abstract:
1. A sample/hold feed switch for switchably connecting and isolating an input node for receiving an input signal to and from an output node connectable to a sampling capacitor for holding a sample of the input signal, comprising: a first PMOS signal branch and a second PMOS signal branch, each of said PMOS signal branches extending from the input node to the output node and each having a PMOS switch FET connected with corresponding PMOS dummy FET, each of said PMOS switch FETs and each of said PMOS dummy FETs having a respective gate and a respective body; a first NMOS signal branch and a second NMOS signal branch, each of said NMOS signal branches extending from the input node to the output node and each having an NMOS switch FET connected with a corresponding NMOS dummy FET, each of said NMOS switch FETs and each of said NMOS dummy FETs having a respective gate and a respective body; and a clock distribution circuit, configured to receive and distribute a clock signal (CLK) switching between a GND voltage and a V a FET bias sequence circuit configured to receive said CLK and said NCLK, and to receive a signal voltage on the input node and a held voltage on the output node and, synchronized with the CLK to bias the bodies of the PMOS switch FETs, the bodies of the NMOS switch FETs, the bodies of the PMOS dummy FETs and the bodies of the NMOS dummy FETs to different bias levels in different operation modes.