Patent ID: 6985401
Filing Date: 2006-01-10
Classification: G11C,H03L

Abstract:
1. A memory device comprising: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer, wherein the DLL comprises: a delay line for delaying a phase of the internal clock; a phase detector for comparing a phase of the internal clock with that of a feedback clock fed back through an internal circuit; a delay line controller for regulating a delay ratio to delay the internal clock in response to a phase detecting signal outputted from the phase detector; and a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.