Patent ID: 8042076
Filing Date: 2011-10-18
Classification: G06F,H01L

Abstract:
1. A method for modeling a circuit, comprising: receiving, at a computing machine, a netlist that defines a plurality of connections between a plurality of circuit elements, wherein the netlist is associated with one or more design rules; generating, by the computing machine, a circuit model based on the netlist, wherein the circuit model comprises a model of one or more of the circuit elements; determining, by the computing machine, a wire width associated with at least a selected connection based, at least in part, on the design rules associated with the netlist; determining, by the computing machine, a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness; routing, by the computing machine, the selected connection in the circuit model based on the wire width associated with the connection and the wire thickness associated with the connection; and storing, by the computing machine, the circuit model in an electronic storage media; wherein at least one of the circuit elements comprises a junction field effect transistor (JFET) logic device that includes a JFET operable to turn on when a voltage differential of 0.5 volts is applied across a gate terminal and a source terminal of the JFET.