Patent ID: 6181160
Filing Date: 2001-01-30
Classification: H03K

Abstract:
A circuit comprising:a first conductor segment;a second conductor segment; andprogrammable buffering circuitry configured to selectively interconnect the first and second conductor segments and, when the first and second conductor segments are interconnected, to amplify the signal on a programmably selectable one of the conductor segments and to apply the amplified signal to the other of the conductor segments, wherein the programmable buffering circuitry comprises:a buffering circuit having an input terminal, an output terminal, first and second inverting drivers connected in series with one another between the input terminal and the output terminal, and a level corrector circuit connected in parallel with one of the inverting drivers;first programmable logic connector circuitry configured to selectively connect the first conductor segment to the input terminal;second programmable logic connector circuitry configured to selectively connect the second conductor segment to the output terminal;third programmable logic connector circuitry configured to selectively connect the second conductor segment to the input terminal; andfourth programmable logic connector circuitry configured to selectively connect the first conductor segment to the output terminal, wherein at least one of the first and second programmable logic connector circuitries and at least one of the third and fourth programmable logic connector circuitries are additionally configured to selectively disconnect the first and second conductor segments.