Patent ID: 9117879
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first semiconductor chip comprising a first metallic structure, a first surface, a second surface opposite to the first surface, and a first insulating layer including at least two adjacent layers differing in etch rate to a predetermined etchant; a second semiconductor chip comprising a second metallic structure and bonded with the first semiconductor chip on the second surface; a first recessed portion extended from the first surface of the first semiconductor chip to the first metallic structure, wherein the first recessed portion includes a first sidewall and a bottom surface disposed on or within the first metallic structure; a second recessed portion extended from the first surface to the second metallic structure, wherein the second recessed portion includes a second sidewall and a bottom surface disposed on or within the second metallic structure; a dielectric layer disposed on the first sidewall of the first recessed portion and the second sidewall of the second recessed portion; and a conductive material disposed DIRECTLY on the first surface, the dielectric layer, a portion of the first metallic structure interfaced with the bottom surface of the first recessed portion and a portion of the second metallic structure interfaced with the bottom surface of the second recessed portion, the first metallic structure being electrically connected with the second metallic structure, wherein the first sidewall or the second sidewall includes a staggered portion covered by the dielectric layer.