Patent ID: 6040199
Filing Date: 2000-03-21
Classification: G01R,H01L

Abstract:
A semiconductor test structure for estimating defects at an isolation edge, comprising:a first insulation film provided on a main surface of a semiconductor substrate in which a plurality of semiconductor elements can be provided, said first insulation film having a width so as to isolate said plurality of semiconductor elements from one another;a second insulation film provided on said main surface, said second insulation film including a plurality of regions spaced from one another and being contiguous with said first insulation film, thinner than said first insulation film, and having an edge which comprises at least a part of the isolation edge;an electrode disposed in common on said plurality of regions of said second insulation film, said electrode extending onto portions of said first insulation film; andelectrical connecting means connected with the semiconductor substrate so as to permit a voltage to be applied between the semiconductor substrate and the electrode.