Patent ID: 6344401
Filing Date: 2002-02-05
Classification: H01L

Abstract:
A method of forming a stacked-die integrated circuit chip package on a wafer level, comprising:providing a first semiconductor wafer and a second semiconductor wafer, each of the wafers including a plurality of dice, the plurality of dice of the second wafer being of a smaller size than the plurality of dice of the first wafer, each of the plurality of dice of the first and second wafers having a plurality of bonding pads disposed on a first surface thereof, attaching a plurality of interconnects to the plurality of bonding pads of the first surface of the plurality of dice of the second wafer, dicing the second wafer into a plurality of individual dice, attaching the individual dice of the second wafer to the first wafer, wherein a back surface of an individual die is placed on and attached to the first surface of the first wafer, to form a plurality of package structures on the first wafer, connecting the plurality of bonding pads of the individual dice to the plurality of bonding pads of the plurality of dice of the first wafer, and dicing the first wafer into a plurality of individual stacked-die integrated circuit packages.