Patent ID: 8539410
Filing Date: 2013-09-17
Classification: G06F,G11C,H01L,H03L

Abstract:
1. A method comprising: preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip including a second main surface opposite to the first main surface, data electrodes of the first and second memory chips being electrically connected in common to each other and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip through the data electrode of the second memory chip; accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time; accessing the second memory chip so that a data signal is outputted from the second memory chip and appears on the side of the second main surface of the second memory chip in second access time; and setting output timing adjustment information into at least one of the first and second memory chips so that delay time responsive to the output timing adjustment information is included in at least one of the first access time and the second access time, wherein the data electrode of the second memory chip penetrates the second memory chip to include a first end portion on a side of the first main surface of the second memory chip and a second end portion on a side of the second main surface of the second memory chip, and the first memory chip is stacked over the second memory chip to connect the data electrode of the first memory chip to the first end portion of the data electrode of the second memory chip.