Patent ID: 8059547
Filing Date: 2011-11-15
Classification: G01R,H04L

Abstract:
1. A test apparatus that tests a device under test, comprising: an upper sequencer, on a transmission-side relative to the device under test, that sequentially designates packets transmitted to and from the device under test, by executing a test program for testing the device under test; a packet data sequence storing section, on a transmission-side relative to the device under test, that stores a data sequence included in each of a plurality of types of packets; a lower sequencer, on a transmission-side relative to the device under test, that reads, from the packet data sequence storing section, a data sequence of a packet designated by the upper sequencer and generates a test data sequence used for testing the device under test; a transmitting section that transmits the test data sequence generated by the transmission-side lower sequencer to the device under test; another upper sequencer, another packet data sequence storing section, and another lower sequencer on a reception-side relative to the device under test; and a receiving section that receives a data sequence of a packet from the device under test, wherein the reception-side lower sequencer notifies the transmission-side lower sequencer that a data sequence has been received that matches the test data sequence generated by the reception-side lower sequencer, and the transmission-side lower sequencer receives the notification from the reception-side lower sequencer and generates a test data sequence of a predesignated packet.