Patent ID: 7881116
Filing Date: 2011-02-01
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a plurality of bit lines and word lines arranged to intersect each other, said plurality of word lines being divided into a plurality of word line groups, said plurality of word line groups including said plurality of word lines; a memory cell array having a plurality of memory cell groups comprised of a plurality of electrically-programmable memory cells arranged in a region in which said bit lines and said word lines intersect; a trimming circuit which obtains a parameter of an initial program voltage for each of said plurality of word line groups; an initial Vpgm parameter register which receives said parameter of said initial program voltage for each of said plurality of word line groups from said trimming circuit and stores said parameter; and a control circuit which programs data to each of said plurality of memory cell groups based on said parameter of said initial program voltage for each of said plurality of word line groups stored in said initial Vpgm parameter register, said trimming circuit being arranged in a part of said control circuit.