Patent ID: 7655972
Filing Date: 2010-02-02
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a semiconductor substrate including source/drain extension regions, a channel region located between said source/drain extension regions and source/drain regions; a gate dielectric and a gate conductor located above the channel region and positioned on a surface of said semiconductor substrate, said gate dielectric and said gate conductor having vertical edges that are covered by an offset spacer; silicide source/drain contacts located directly on and above source/drain regions; and a metallic or intermetallic material portion that includes at least a first portion, a second portion, and a third portion that are contiguous to one another and have a same material composition, wherein said first portion laterally abuts a lower portion of said offset spacer and a surface of said source/drain extension regions, said second portion laterally abuts a sidewall of said silicide source/drain contacts, and said third portion vertically abuts a top surface of said silicide source/drain contacts, wherein said silicide source/drain contacts are spaced apart from said channel region by said metallic or intermetallic material portion, and wherein said metallic or intermetallic material portion does not cover the entirety of said offset spacer.