Patent ID: 9009398
Filing Date: 2015-04-14
Classification: G06F,G11C

Abstract:
1. A method of operating a three dimensional nonvolatile memory formed in two or more physical levels of memory cells disposed above a substrate, comprising: receiving a portion of data to be stored in the three dimensional nonvolatile memory; buffering the portion of data in on-chip data latches formed on the substrate; writing the portion of data from the on-chip data latches as Single Level Cell (SLC) data in a first block in the three dimensional nonvolatile memory while asserting a busy indicator throughout the writing; subsequently, writing the portion of data from the on-chip data latches as Multi Level Cell (MLC) data in a second block in the three dimensional nonvolatile memory; suspending the writing of the portion of data as MLC data in the second block; performing a post write read of a previously programmed MLC block during the suspending; subsequent to the suspending, resuming the writing of the portion of data as MLC data in the second block; in parallel with the resumed writing of the portion of data as MLC data in the second block, transferring post write read data from the previously programmed MLC block; maintaining the portion of data in the on-chip data latches throughout a time that extends from the writing of the portion of data as SLC data in the first block to the writing of the portion of data as MLC data in the second block; and subsequently erasing the first block only after a post write read confirms that the second block contains data that passes a predetermined standard.