Patent ID: 7747833
Filing Date: 2010-06-29
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a plurality of memory banks; a plurality of link controllers each link controller having at least one input for receiving control and data and having at least one output for outputting the data; for each memory bank, first switching logic for receiving the at least one output for each link controller, and for passing on the at least one output of only one of the link controllers to the memory bank; for each link controller, second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller; and switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.