Patent ID: 7606054
Filing Date: 2009-10-20
Classification: G11C

Abstract:
1. A data processing system comprising: a processor; and a cache memory configured to store data to be used at the processor and having a cache hit logic for determining whether data requested by the processor is stored in the cache memory, wherein the cache hit logic includes: a tag memory cell array having tag memory cells arranged in rows and columns to store tag addresses; a row decoder for selecting the rows; a column decoder for selecting the columns; a sense amplifier for sensing a tag address stored in a cell of the tag memory cell array selected by the row decoder and the column decoder in response to an activation of an enable signal; and a comparison circuit for comparing the sensed tag address with an input tag address when a time required for the sense amplifier to sense the tag address has passed after the enable signal is activated, to output a hit signal corresponding to the comparison result, wherein the comparison circuit activates an output enable signal when a time required for the sense amplifier to sense the tag address has passed after the enable signal is activated.