Patent ID: 7190724
Filing Date: 2007-03-13
Classification: H04N

Abstract:
1. A circuit, comprising: a video decoder integrated circuit chip, the video decoder integrated circuit chip including, circuitry for receiving a bit stream of data associated with a frame of video data, wherein the frame of video is divided into a first series of blocks, each block in the series is representative of a specific portion of the frame of video; circuitry for decoding the bit stream of data into a transform domain representation, wherein the transform domain representation comprises a second series of blocks, each block in the second series of blocks is a transform domain representation of each block in the first series, and consists of a first number elements each element of the second series of blocks storing a zero or non-zero transform coefficient; circuitry for arranging non-zero transform coefficients of the transform domain representation in a hybrid data structure comprising a third series of blocks and an overflow vector associated with the frame of video in a memory associated with the video decoder; wherein each block in the third series of blocks is: circuitry for decompressing the non-zero transform coefficients of the transform domain representation for display.