Patent ID: 7723774
Filing Date: 2010-05-25
Classification: G11C,H01L

Abstract:
1. A flash memory structure formed on a semiconductor substrate of a first conductivity type, the structure comprising: a non-diffused channel region within the semiconductor substrate through which electron flow may be induced by application of voltage to gate elements disposed above the channel region; a plurality of floating gates, spaced apart from one another, each insulated from the channel region; a plurality of T-shaped control gates, spaced apart from one another, each insulated from the channel region, each control gate being laterally adjacent a first floating gate in position across form the channel region, and being capacitively coupled to the first floating gate, wherein each control gate and the first floating gate to which the control gate is capacitively coupled form a subcell; and a plurality of assist gates, spaced apart from one another, each insulated from the channel region, each assist gate being between and insulated from a first subcell and a second subcell, wherein each assist gate being between a floating gate in the first subcell and a floating gate in the second subcell; wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath; and wherein operation of the second subcell as a programmed cell is enabled via electron flow induced in the first channel region, the second channel region, and the third channel region by voltages on the first floating gate associated with the first control gate, the assist gate, and the second control gate, respectively.