Patent ID: 9189403
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. A data processing system, comprising: an interconnect fabric; a system memory coupled to the interconnect fabric; and a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches; a cache array in the first lower level cache, wherein the cache array includes a congruence class including a plurality of cache lines; a cache directory in the first lower level cache, wherein the cache directory includes: wherein the first lower level cache sets the respective associated one of the plurality of confidence indicators to indicate a lateral castout (LCO) in response to the first processor core accessing the associated cache line while the associated cache line has a position in the chronological access order at least as recent as a predetermined position; wherein the first lower level cache, responsive to a data request, selects a victim cache line to be castout from among the plurality of cache lines in the congruence class of the first lower level cache and decides, based upon the confidence indicator associated with the victim cache line, between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory; wherein the first processing unit, responsive to the first lower level cache deciding to perform the LCO, issues a lateral castout (LCO) command on the interconnect fabric and removes the victim cache line from the first lower level cache; and wherein the second lower level cache, responsive to the LCO command, holds the victim cache line.