Patent ID: 6040243
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A method to prevent copper diffusion into dielectric layers in the fabrication of a damascene via in the manufacture of an integrated circuit device comprising:providing copper traces through an isolation layer overlying a semiconductor substrate;depositing a passivation layer overlying said copper traces and said isolation layer;depositing a dielectric layer overlying said passivation layer;depositing a cap layer overlying said dielectric layer;patterning said cap layer and said dielectric layer to form an opening for planned said damascene via and to expose the top surface of said passivation layer overlying said copper traces;depositing a barrier layer overlying said passivation layer and said dielectric layer;etching through said barrier layer to expose the top surfaces of said passivation layer and said cap layer wherein remaining said barrier layer isolates sidewalls of said opening; andetching through said passivation layer to the top surface of said copper traces to complete said damascene via in the manufacture of said integrated circuit device.