Patent ID: 6275838
Filing Date: 2001-08-14
Classification: G06F,G11C,H03K

Abstract:
An enhanced floating point unit that in a single functional unit supports floating point operations, integer operations, and graphics operations, comprising:a register file;a plurality of bypass multiplexers coupled to said register file;a first, second, and third result path coupled to said bypass multiplexers, wherein said first result path includes single cycle integer operations including integer addition and multiply operations and single cycle graphic shift operations including graphics addition operations, and wherein said second result path includes 2 cycle integer add and subtract operations, 2 cycle graphics add and subtract operations, shifts, and simple register moves, and wherein said third result path includes graphic summation operations;an enhanced aligner and an enhanced multiplier coupled to said bypass multiplexers, said enhanced aligner aligns input operands and further comprises shifting input operands according to a shift amount when operating on graphics or integer instructions, said enhanced multiplier multiplies input operands and further comprises accepting integer operands and passing through one of the input operands unaffected for operations that do not require multiplication;an enhanced adder that couples to said aligner and said multiplier, said enhanced adder adds input operands and further comprises performing integer addition and partitioned graphics addition;a normalizer/rounder unit that couples to said enhanced adder, said normalizer/rounder unit further comprises passing the output of said enhanced adder unaffected and also to sum multiple results from said enhanced adder; andwherein the single functional unit supports floating point operations, integer operations, and graphics operations.