Patent ID: 8623229
Filing Date: 2014-01-07
Classification: H01L

Abstract:
1. A method for processing a semiconductor workpiece, wherein the workpiece includes a first region with relatively tall or relatively-high aspect ratio features and a second region with relatively short or relatively-low aspect ratio features, the method comprising: providing a first photoresist layer over the semiconductor workpiece, wherein the first photoresist layer has a negative photoresist tone; patterning the first photoresist layer to cover a relatively tall or relatively-high aspect ratio feature while concurrently exposing a relatively short or relatively-low aspect ratio feature; wherein patterning the first photoresist layer comprises: providing a first photomask over the first photoresist layer, wherein the first photomask comprises: a first window region corresponding to the relatively tall or relatively high aspect ratio feature, and a first blocking region corresponding to the relatively short or relatively-low aspect ratio feature; providing a second photoresist layer over the patterned first photoresist layer, wherein the second photoresist layer has a positive photoresist tone; patterning the second photoresist layer to cover the relatively tall or relatively-high aspect ratio feature while concurrently exposing the relatively short or relatively-low aspect ratio feature previously exposed through the first photoresist layer; and while the patterned first and second photoresist layers are in place, performing an etch to remove the exposed relatively short or relatively-low aspect ratio feature.