Patent ID: 6140242
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method of forming an isolation trench in a semiconductor device comprising:forming a trench etch mask layer over a semiconductor substrate;patterning the trench etch mask layer and exposing the semiconductor substate where an isolation trench is to be formed;etching an exposed portion of the semiconductor substrate, thereby forming the isolation trench;forming a thin oxide layer in the isolation trench;filling up the isolation trench with an insulating layer;performing first annealing at a temperature below a first temperature so as to remove substrate defects caused during said etching of the semiconductor substrate and to densify the insulating layer;planarizing the insulating layer, andperforming second annealing at a temperature above the first temperature so as to remove substrate defects caused during said etching of the semiconductor and to densify said insulating layer.