Patent ID: 9048257
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A method of manufacturing a backplane for a flat panel display apparatus, the method comprising: forming a pixel electrode and a capacitor first electrode on a substrate through a first mask process; forming a first protection layer covering the pixel electrode and the capacitor first electrode, and forming a gate electrode of a TFT and a capacitor second electrode on the first protection layer through a second mask process; forming a first insulating layer covering the gate electrode and the capacitor second electrode, and forming a semiconductor layer that comprises a transparent conductive material on a position corresponding to the gate electrode through a third mask process; forming a second insulating layer covering the semiconductor layer, forming a contact hole that penetrates the second insulating layer and exposes a portion of the semiconductor layer, and forming a via hole that penetrates the first protection layer, the first insulating layer, and the second insulating layer and exposes a portion of the pixel electrode through a fourth mask process; forming source and drain electrodes covering the contact hole and the via hole through a fifth mask process; and forming a third insulating layer covering the source and drain electrodes, and forming an opening that exposes an upper surface of the pixel electrode in the third insulating layer through a sixth mask process.