Patent ID: 9030246
Filing Date: 2015-05-12
Classification: H03K

Abstract:
1. A semiconductor device comprising an input node that receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby; a detection unit that sets an enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period; and a signal transmission unit that includes P-channel MOS transistors and transmits a signal input to the input node according to control by the enable signal, wherein the signal transmission unit comprises: a first NAND circuit with one input coupled to the input node and the other input coupled to an output of the detection unit; and a second NAND circuit with one input coupled to an output of the first NAND circuit and the other input coupled to the output of the detection unit, and wherein the input signal is a first clock that is input from outside the semiconductor device and remains at a high level during standby, and wherein the detection unit comprises: a charging unit in which an amount of charge stored therein varies depending on a duty ratio of the first clock input to the input node; and an output unit that sets the level of the enable signal based on whether or not an amount of charge stored in the charging unit exceeds a predetermined threshold value.