Patent ID: 6405235
Filing Date: 2002-06-11
Classification: G06F,G09G

Abstract:
A system for use in performing data communication between devices via a bus, comprising:a data sending device which sends first data to the bus in one-to-one data communication; a first data receiving device which receives the first data from the data sending device via the bus; and at least one second data receiving device which receives the first data sent from the data sending device to the first data receiving device, simultaneously with the first receiving device; and, wherein the second data receiving device is configured to receive the first data sent from the data sending device to the first data receiving device via the bus and comprises simultaneous receiving means to an existing second data receiving device which does not have a function to receive the first data in original and, wherein the first data includes an address, the simultaneously receiving means receiving the first data sent from the data sending device to the first data receiving device by determining whether the address meets a predetermined condition, and wherein the first data includes the address and the second data, the simultaneously receiving means comprising: a bi-directional buffer which temporarily stores the second data from the bus; a latch which latches the address from the bus, and sends the address to the memory control circuit; a bus control circuit which determines whether the first data currently received from the bus is the address or the second data, and according to the determination, controls the latch and the bi-directional buffer; an address decoder which determines whether or not the address from the latch is an address for the second receiving data; an address register which stores addresses which define ranges of addresses for the first receiving device; a comparator which determines whether or not the address from the latch is in the range of addresses stored in the address register; and an OR circuit which inputs a signal from the address decoder and a signal from the comparator and according to the signals, controls output of an enable signal for enabling the memory control circuit to access to the second data temporarily stored in the buffer.