Patent ID: 7313645
Filing Date: 2007-12-25
Classification: G06F

Abstract:
1. A processor comprising: a plurality of memory banks in which first to third matrices are dispersedly arranged; a readout-address generation circuit supplying a first readout address for reading out a predetermined row in the first matrix from the plurality of memory banks and a second readout address for reading out a predetermined column in the second matrix from the plurality of memory banks on the basis of a readout-register designation and a readout-register scan direction of the first and the second matrices; a readout control circuit controlling arrangement of the predetermined row in the first matrix and the predetermined column in the second matrix, both of which are read out from the plurality of memory banks, in accordance with the first and the second readout addresses on the basis of the readout-register designation and a readout-register displacement of the first and the second matrices; a processing unit performing inner product processing for the predetermined row in the first matrix and predetermined column in the second matrix which are subjected to the arrangement controlled by the readout control circuit; a write-address generation circuit supplying a write address in the plurality of memory banks on the basis of a write-register designation and a write-register displacement of the third matrix; and a write control circuit writing the inner product processing's results output by said processing unit in an address corresponding to the third matrix in the plurality of memory banks on the basis of said write-register designation and the write-register displacement.