Patent ID: 7343535
Filing Date: 2008-03-11
Classification: G01R,G11C

Abstract:
1. An integrated circuit comprising: a plurality of serializer/deserializers (SERDESs); core processing logic integrated with each of said plurality of SERDESs and connected to each of said plurality of SERDESs to exchange signals therewith; and a plurality of functionally identical testers integrated with said plurality of SERDESs and said core processing logic, said testers being connected to individually test each of said plurality of SERDESs, each of said testers being enabled to detect performance characteristics of an individual one of said plurality of SERDESs independently of other said testers and concurrently with said plurality of SERDESs, wherein a bit error rate for each of said plurality of SERDESs is individually identified, and wherein said testers perform loop-back testing, static data testing and dynamic data testing; wherein each of said testers is connected to a common test bus that is integrated with said plurality of SERDESs and said testers, said common test bus being separate from a data bus, each of said testers having a unique address that enables independent accessibility of each of said testers via said test bus, said test bus being dedicated to providing signaling for said enablement to detect performance characteristics of said individual one of said plurality of SERDESs and further comprising a built in self-test (BIST) state machine integrated with said plurality of SERDESs and said testers, said BIST being connected to said test bus and being configured to sequence test operations by each of said testers.