Patent ID: 7037795
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. A semiconductor fabrication process, comprising: forming a transistor gate structure overlying a silicon-on-insulator (SOI) wafer, the SOI wafer including an active semiconductor top layer overlying a buried dielectric layer overlying a semiconductor substrate, the transistor gate structure including a gate electrode overlying a gate dielectric overlying a channel region comprised of a portion of the semiconductor top layer; forming source/drain trenches in the buried dielectric layer disposed on either side of the gate structure, wherein the source/drain trenches extend through the buried dielectric layer exposing portions of the underlying semiconductor substrate; and forming source/drain structures within the source/drain trenches by epitaxial growth using the exposed portions of the semiconductor substrate as a seed, wherein an upper surface of the source/drain structure coincides approximately with an upper surface of the channel region; where forming the source/drain structures includes forming a first portion of the source/drain structures as an oxygen-rich epitaxial film and forming a second portion of the source/drain structures as a substantially oxygen free epitaxial film.