Patent ID: 6518592
Filing Date: 2003-02-11
Classification: G01R,H01L

Abstract:
A characteristic evaluation pattern for evaluating MOSFET characteristics, the pattern comprising:a first transistor; a second transistor having a gate-contact length equal to that of said first transistor and a gate length different from that of said first transistor; a third transistor having a gate-contact length different from that of said first transistor and a gate length equal to that of said first transistor; a gate terminal, a source terminal, a drain terminal, and a back gate terminal electrically conducting to a gate electrode, source region, a drain region, and a back gate electrode of said first transistor respectively; a gate terminal, a source terminal, a drain terminal, and a back gate terminal electrically conducting to a gate electrode, a source region, a drain region, and a back gate electrode of said second transistor respectively; and a gate terminal, a source terminal, a drain terminal, and a back gate terminal electrically conducting to a gate electrode, a source region, a drain region, and a back gate electrode of said third transistor respectively.