Patent ID: 6710415
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A semiconductor integrated circuit comprising:a semiconductor substrate having a surface; a MOS transistor formed on the surface of the semiconductor substrate, the MOS transistor comprising a first conductivity type source and drain regions and a second conductivity type channel region between the source and the drain regions, the MOS transistor having a first breakdown voltage between the drain and the source regions; an anti-fuse device formed on the surface of the semiconductor substrate, the anti-fuse device comprising a pair of diffusion regions of the first conductivity type and a second region of the second conductivity type between the pair of diffusion regions, the anti-fuse device having a second breakdown voltage between the pair of diffusion regions lower than the first breakdown voltage; and a writing circuit integrated on the surface of the semiconductor substrate, the writing circuit supplying a writing voltage between the pair of diffusion regions of the anti-fuse device to make the anti-fuse device permanently conductive between the pair of diffusion regions.