Patent ID: 8669167
Filing Date: 2014-03-11
Classification: H01L

Abstract:
1. A method of fabricating a FIN field effect transistor (FET) device, comprising the steps of: providing a semiconductor-on-insulator (SOI) wafer comprising a SOI layer over a buried oxide (BOX); forming an oxide layer over the SOI layer; patterning a plurality of fins in the SOI layer and the oxide layer such that at least one first group of the fins which corresponds to at least one first FIN FET device has at least one first pitch, and at least one second group of the fins which corresponds to at least one second FIN FET device has at least one second pitch; forming an interfacial oxide on the fins; depositing a conformal gate dielectric layer over the interfacial oxide; depositing a conformal gate metal layer on the conformal gate dielectric layer; and depositing a conformal work function setting material layer on the conformal gate metal layer to form gate stacks over the fins, wherein the conformal work function setting material layer acts as a doping source to alter a work function of the gate stacks, and wherein an amount of the conformal gate metal layer and an amount of the conformal work function setting material layer deposited on the fins varies proportionally to a pitch of the fins since there are different size gaps to fill between the fins based on the pitch of the fins, and wherein variations in the amount of the conformal work function setting material layer deposited on the fins alters a threshold voltage of the FIN FET devices, and thus by patterning the fins so as to have the at least one first pitch and the at least one second pitch the amount of the conformal work function setting material layer is varied by having the different size gaps for the work function material to fill in as a function of the pitch of the fins so as to configure the at least one first FIN FET device to have a threshold voltage that is different from a threshold voltage of the at least one second FIN FET device.