Patent ID: 6738411
Filing Date: 2004-05-18
Classification: H04J

Abstract:
A plural code series generator comprisinga first shift register including a plurality of shift stages in which a first initial value is loaded and adapted to be subject to a shift operation in synchronism with a clock; a first code generating exclusive OR means for forming an exclusive OR of outputs from a predetermined first set of plural shift stages of the first shift register and for delivering it as a first code series and also feeding the first code series back, to the input of the first shift register; a second code generating exclusive OR means for forming an exclusive OR of outputs from a second set of shift stages for delivering it as a second code series which is delayed by a given number of chips with respect to the first code series, wherein the first and the second sets of shift stages include an equal number of shift stages and equal relative positions between the plural shift stages in each set, the plural shift stages in the second set in the first shift register have positions which are offset by one or more stages relative to the positions in the first set while maintaining the relative positions between the plural shift stages in the first set; a second shift register including a plurality of shift stages in which a second initial value which is distinct from the first initial value is loaded and adapted to be subject to a shift operation in synchronism with the clock; a third code generating exclusive OR means for forming an exclusive OR of outputs from a predetermined third set of plural shift stages in the second shift register, for delivering it as a third code series and for feeding the third code series back to the input of the second shift register; a fourth code generating exclusive OR means for forming an exclusive OR of outputs from a fourth set of plural shift stages in the second shift register which is distinct from the third set, and for delivering it as a fourth code series, the third set and the fourth set having an equal number of shift stages and having equal relative positions between the plural shift stages in each set, the fourth set of plural shift stages in the second shift register having positions which obtain when the positions of the third set are offset by a given number of stages in the same direction as the second set of shift stages; a first and a second output exclusive OR means for forming exclusive OR's between the first and the second code series and between the third and the fourth code series, respectively, and for delivering them as a first and a second spread code which are offset in phase by a given number of chips relative to each other; a third shift register including a plurality of shift stages in which a third initial value which is distinct from the second initial value is loaded and adapted to be subject to a shift operation in synchronism with the clock; a fifth code generating exclusive OR means for forming an exclusive OR of outputs from a predetermined fifth set of plural shift stages in the third shift register, for delivering it as a fifth code series and feeding the fifth code series back to the input of the third shift register; a third output exclusive OR means for forming an exclusive OR of one of the third and the fourth code series and the fifth code series and for delivering it as a third spread code which is orthogonal to the first and the second spread code; and clock means for feeding a clock which is used in performing the shift operation in the first, second and third shift registers.