Patent ID: 6960508
Filing Date: 2005-11-01
Classification: H01L

Abstract:
1. A method of manufacturing a MOS transistor, comprising: forming an isolating layer in a semiconductor substrate; forming first and second drain regions in the surface of the substrate on both sides of the isolating layer; etching the portions of the first and second drain regions and the substrate on both sides of the isolating layer to form a projection having the isolating layer in its middle; forming a spacer on the sidewalls of the substrate of the projection; forming a barrier layer on the surfaces of the first and second drain regions and of the substrate on both sides of the projection; selectively removing the spacer; forming first and second recesses by etching the substrate exposed by the barrier layer; removing the barrier layer; forming a gate insulating layer on the entire surface of the substrate; forming first and second source regions within the surface of the substrate on both sides of the projection; depositing a gate material layer on the gate insulating layer so as to fill the first and second recesses; and forming first and second gates on the gate insulating layer on both sides of the substrate of the projection by patterning the gate material layer.