Patent ID: 6150842
Filing Date: 2000-11-21
Classification: H01L,H03K

Abstract:
A field programmable gate array (FPGA) device comprising:(a) interconnect lines;(b) a plurality of configurable building elements (CBE's) each disposed adjacent to a respective subset of the interconnect lines, with each given CBE comprising:(b.1) configurable signal acquiring resources for selectively acquiring signals from a respective CBE-associated subset of adjacent ones of said interconnect lines, the signal acquiring resources supplying their respectively-acquired signals to the given CBE in a first mode; and(b.2) a configurable lookup table (LUT);(b.3) wherein at least two of said CBE's respectively have different CBE-associated subsets of adjacent interconnect lines from which the respective CBE's can selectively acquire signals in said first mode; and(c) combining means for selectively folding together the signal acquiring resources of a respective two or more CBE's in a second mode so as to provide at least one of said two or more CBE's with comparatively larger signal acquiring capabilities than such at least one CBE has in the first mode from its respective signal acquiring resources and its respective CBE-associated subset of adjacent interconnect lines.