Patent ID: 6714463
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A semiconductor memory device for inputting/outputting data in response to an external chip select signal and an address signal that are inputted through signal input terminals, the semiconductor memory device comprising:a memory cell array for storing data; a write/read circuit for writing/reading the data to/from the memory cell array; a first input circuit for transferring the address signal to the write/read circuit through the signal input terminal in response to a first control signal; and a control logic circuit for detecting whether the address signal inputted to the first input circuit transitions, and for generating a series of pulse signals so that the write/read circuit writes/reads a data signal, wherein the control logic circuit generates the series of pulse signals in response to the activation of an internal chip select signal from the first input circuit when the external chip select signal transitions from inactive to active, wherein the control logic circuit comprises: a second input circuit for receiving the external chip select signal and activating the first control signal and a second control signal when the external chip select signal is active; a detect circuit for detecting whether the address signal inputted to the first input circuit transitions while the second control signal is activated, and outputting an address transition detect signal; a pulse enable control circuit for activating a pulse enable signal in response to the address transition detect signal when the first control signal is active, and for activating the pulse enable signal when the first control signal transitions from an inactive state to an active state; and a pulse generation circuit for generating the series of the pulse signals in response to the pulse enable signal.