Patent ID: 6542395
Filing Date: 2003-04-01
Classification: H01L

Abstract:
An integrated DRAM memory module, comprising:a plurality of sense amplifiers each formed from a multiplicity of transistor structures arranged in rows and comprising amplification transistors for bit line signal amplification, said amplification transistors lying opposite one another in pairs, being structurally identical, and arranged uniformly spaced apart in the row; voltage equalization transistors for voltage equalization between sense amplifier drive signals disposed to interrupt a respective row formed with amplification transistors situated in a structurally identical transistor environment; said voltage equalization transistors having a structure in a region of proximity to respectively adjoining said amplification transistors identical to a structure of said adjoining said amplification transistors; and said voltage equalization transistors being spaced from said adjoining amplification transistors at a spacing distance equal a spacing distance between said amplification transistors of the row.