Patent ID: 7145376
Filing Date: 2006-12-05
Classification: H03K

Abstract:
1. A differential solid state delay line for reducing distortion in differential solid state delay lines in integrated circuits comprising: n number of differential delay cells, each cell of the n number of differential delay cells including a first input associated with a first output and a second input associated with a second output, at least one present of asymmetry and distortion regarding circuitry between the first input and the first output in comparison to circuitry between the second input and the second output, each cell of the n number of differential delay cells being connected for forming the differential solid state delay line and an even number of the n number of differential delay cells being cross-connected using a twisted line interconnect between differential delay cells having the first output of a preceding one cell of the n number of differential delay cells being connected to the second input of a succeeding one cell of the n number of differential delay cells and the second output of the preceding one cell of the n number of differential delay cells being connected to the first input of the succeeding one cell of the n number of differential delay cells for reducing distortion in circuitry between the first input and the first output in comparison to circuitry between the second input and the second output.