Patent ID: 8120945
Filing Date: 2012-02-21
Classification: G11C

Abstract:
1. A non-Flash re-writeable non-volatile memory device, comprising: at least one host device configured to perform data operations on non-Flash re-writeable non-volatile memory; a memory bus in electrical communication with the at least one host device; a plurality of re-writeable non-volatile two-terminal memory devices in electrical communication with the memory bus, each memory device including at least one preservation circuit in electrical communication with the at least one two-terminal cross-point array and operative to perform preservation operations on one or more of the plurality of two-terminal non-volatile memory elements and configured to, in response to a trigger signal, restore the resistance values to represent the data; and at least one trigger circuit electrically coupled with the at least one preservation circuit and configured to detect a triggering event and generate the trigger signal.