Patent ID: 7487474
Filing Date: 2009-02-03
Classification: G06F

Abstract:
1. A method of designing an integrated circuit to improve yield when manufacturing the integrated circuit, the method comprising: obtaining a design element from a set of design elements used in designing integrated circuits; creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is modified to create the variant design element; determining a yield to area ratio for the variant design element; if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, retaining the variant design element to be used in designing the integrated circuit, wherein the design element is a bit cell, the set of design elements is a set of bit cells, and the variant design element is a variant bit cell; and selecting a memory macro from a set of memory macros; and applying the variant bit cell to the selected memory macro.