Patent ID: 7843068
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A semiconductor chip comprising: a semiconductor substrate; an insulating film provided to cover a surface of the semiconductor substrate and having a first side and a second side, the second side being in contact with the surface of the semiconductor substrate, the insulating film having an opening portion formed therein; a through via provided in a through hole that passes through the semiconductor substrate, wherein the through via extends with the through hole through the semiconductor substrate and terminates at the second side of the insulating film that contacts the semiconductor substrate; a multi-layered wiring structure including: a second wiring pattern provided in the plurality of insulating layers for electrically connecting the through via and the external connection terminal, the second wiring pattern having an integrally formed via and wiring, the second wiring pattern via being formed in the opening portion of the insulating film, wherein the second wiring pattern provided on the insulating film is an electroplating film, wherein the through hole formed in the semiconductor substrate exposes a bottom face of the second wiring pattern via in the opening portion wherein a diameter of the second wiring pattern via is larger than a diameter of the through via, and wherein the first wiring pattern electrically connects a plurality of semiconductor elements formed in the semiconductor substrate to constitute a semiconductor circuit.