Patent ID: 6112282
Filing Date: 2000-08-29
Classification: G06F

Abstract:
An apparatus for executing an atomic instruction, comprising:a shared resource having a memory location for storing control data for the shared resource;a plurality of processors;a write-cache for writing data to said shared resource; andmeans for transferring a store instruction from a front end of one of said plurality of processors to said write-cache to cause said write-cache to obtain exclusive access to said memory location of said shared resource, for transmitting a first signal to the front end of the one processor indicating that the write-cache has obtained exclusive access to the memory location of the shared resource, for executing at least one next instruction, for transmitting a second signal to the write-cache indicating that execution of the at least one next instruction has been completed, and for storing control data from the write-cache to the memory location of the shared resource in response to the second signal transmitted to the write-cache, wherein the store instruction and the at least one next instruction are non-atomic instructions.