Patent ID: 6429702
Filing Date: 2002-08-06
Classification: H03F,H03K

Abstract:
An input class AB stage of a buffer for generating a current for a large capacitive load, comprising:level shifting circuitry that biases an applied differential input signal; a pair of cross-coupled driving transistors that each receive said biased applied differential input signal at a gate terminal; at least one amplifier having a first input connected to a gate source terminal of one of said driving transistors and a second input connected to said level shifting circuitry; and a pair of current source transistors that generate an output current for said load, wherein each of said current source transistors have a gate terminal connected to an output of said at least one amplifier and a drain terminal connected to said gate source terminal of one of said driving transistors, wherein said pair of driving transistors are cross-coupled through said at least one amplifier and said level shifting circuitry, wherein said driving transistors are prevented from entering a linear region for substantially all input voltages.