Patent ID: 6700147
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A semiconductor device comprising:a first insulating layer formed over a semiconductor substrate; active pattern formed over the first insulating lays; a second insulating layer for covering the conductive pattern; a first hole formed in the second insulating layer the conductive pattern; a lower electrode of a capacitor formed over the second insulating layer and having a contact area, a lower surface of which is connected electrically to the conductive pattern via the first hole; second insulating layer and having a contact area, a lower surface of which is connected electrically to the conductive pattern via the first hole; a dielectric layer of the capacitor formed on the lower electrode; an upper electrode of the capacitor formed on the dielectric layer in a region except the contact area; a third insulating layer formed over the upper electrode and the second insulating layer; a second hole formed in the third insulating layer and the second insulating layer over the conductive pattern at an interval from the first hole; and a lower electrode leading wiring formed over the third insulating layer to be connected electrically to the conductive pattern via the second hole.