Patent ID: 8775739
Filing Date: 2014-07-08
Classification: G06F

Abstract:
1. A memory system comprising: a memory chip including a nonvolatile memory cell array and first and second cache regions configured to temporarily hold data of a predetermined size read out from the memory cell array; a memory interface configured to manage a first address information history which is a physical address on the memory cell array in which the data held in the first cache region is stored and a second address information history which is a physical address on the memory cell array in which the data held in the second cache region is stored; a controller configured to issue a readout request including a readout address that specifies the physical address on the memory cell array to the memory interface; and a buffer memory configured to temporarily hold the data read out from the memory chip; wherein the controller issues a pre-fetch request including a pre-fetch address specifying the physical address on the memory cell array to the memory interface; and the memory interface transfers the data held in the first cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the first address information history, transfers the data held in the second cache region to the buffer memory without reading out the data corresponding to the readout address from the memory cell array if the readout address matches the second address information history, reads out the data corresponding to the readout address from the memory cell array and transfers the data to the buffer memory if the readout address does not match either one of the first or second address information histories, terminates a process of the pre-fetch request without reading out data corresponding to the pre-fetch address from the memory cell array if the pre-fetch address matches the first or second address information history, and pre-fetches the data corresponding to the pre-fetch address from the memory cell array to the first or second cache region if the pre-fetch address does not match either one of the first or second address information history.