Patent ID: 6516513
Filing Date: 2003-02-11
Classification: H01L,H05K,Y10T

Abstract:
A method of making an interposer that compensates for CTE mismatch between a chip and a chip carrier, said method comprising the steps of:forming a first layer of dielectric material having a first elastic modulus and a first CTE; forming a second layer of dielectric material with metallurgy thereon having a second elastic modulus lower than said flat elastic modulus of said first layer of dielectric material and having a higher composite CTE than said CTE of said first layer of dielectric material; forming a third layer of dielectric material with metallurgy thereon having a composite CTE between said first CTE of said first layer of dielectric material and said composite CTE of said second layer of dielectric material; positioning said third layer of dielectric material between said first and second layers of dielectric material to form a composite structure; and forming an array of conductive vias through said composite structure.