Patent ID: 7326621
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. A method of fabricating a recess channel array transistor, the method comprising: filling a trench formed in a silicon substrate with an isolation insulating layer, thereby defining an active region; forming a buffer insulating layer on the silicon substrate; forming a mask layer on the buffer insulating layer, the mask layer having a high etch selectivity with respect to the silicon substrate; selectively etching the mask layer and the buffer insulating layer, thereby forming a mask layer pattern and a buffer insulating layer pattern to expose a portion of the active region; etching the exposed portion of the silicon substrate in the active region, using the mask layer pattern and the buffer insulating layer pattern as a mask, to form a recess channel trench in the active region, the recess channel trench having a negative slope sidewall; removing the mask layer pattern; forming a gate insulating layer and a recess gate stack on the recess channel trench; and forming a source and a drain in the silicon substrate adjacent to sidewalls of the recess gate stack.