Patent ID: 8164693
Filing Date: 2012-04-24
Classification: G11C,H04N

Abstract:
1. An apparatus including a first group of line memories for a luminance signal, a second group of line memories for a first color signal, and a third group of line memories for a second color signal, the apparatus comprising: a plurality of RAM components each of which is defined by the number of bits in a bit width direction that is larger than in a width direction of one of the line memories, the number of bits in a word length direction of one of the RAM components is less than that in a row length of the one of the line memories, the RAM components being connected together in a cascade fashion from a first-stage to a last-stage of the RAM components, where the total number of bits in the word length direction of the RAM components is over the number of bits in the row length of the one of the line memories; a first group of input parts for the luminance signal provided for the first-stage RAM component, a first group of output parts provided for the last-stage RAM component for the luminance signal, the output parts of the first group being connected in the cascade fashion to the input parts of the first group except an external Y signal input part, in order to form the first group of line memories; a second group of input parts for the first color signal provided for the first-stage RAM component, a second group of output parts provided for the last-stage RAM component for the first color signal, the output parts of the second group being connected in the cascade fashion to the input parts of the second group except an external first color signal input part, in order to form the second group of line memories; a third group of input parts for the second color signal provided for the first-stage RAM component, a third group of output parts provided for the last-stage RAM component for the second color signal, the output parts of the third group being connected in the cascade fashion to the input parts of the third group except an external second color signal input part, in order to form the third group of line memories; and a controller configured to control a write address and a read address of the RAM components to drive the line memories.