Patent ID: 7779212
Filing Date: 2010-08-17
Classification: G06F

Abstract:
1. An electronic system comprising: a processor, which generates and sends one or more memory access requests; and multiple memory modules, operatively coupled together through a communications bus, which return data requested in the one or more memory access requests, wherein each of the multiple memory modules is a data source, and a memory module of the multiple memory modules determines that first source data and second source data are available, generates a header for at least one of the first source data and the second source data, allocates one or more first contiguous lanes within a first section of a data block to at least some of the first source data, wherein the data block comprises a set of multiple lanes, and each lane includes a set of configurable bits, allocates one or more second contiguous lanes within a second section of the data block to at least some of the second source data, wherein the second section begins at a next lane, which is contiguous and abutting with the first section, sends, over the communications bus and during a data block transmission period, the at least a portion of the first source data within the first section of the data block, and the at least a portion of the second source data within the second section of the data block, wherein the header is positioned between the at least some of the first source data and the at least some of the second source data; wherein a memory module comprises: