Patent ID: 7146391
Filing Date: 2006-12-05
Classification: G06F,H03M,H04L,H04M

Abstract:
1. A digital signal processor (DSP) including a number of single instruction multiple data (SIMD) path logic units, each logic unit including (i) a multiplier having two or more input ports, one of the input ports being configured to receive input symbol data, the multiplier being configured to produce a multiplier output, (ii) an adder configured to receive the output product and produce an adder output therefrom, and (iii) a scalar configured to scale, at least indirectly, the adder output, the DSP comprising: a constants generator coupled to another one of the number of multiplier input ports and being configured to produce a fixed format signal based upon the input symbol data, the multiplier output being representative of a product of the received input symbol data and the fixed format signal; wherein the adder is configured to (i) receive boundary constraints representative of a first component of predetermined symbol standards and (ii) compare the multiplier output with the boundary constraints, the adder output being representative of the comparison; and a quantizer configured to (i) receive the adder output and (ii) associate the received adder output with a second component of the predetermined symbol standard, the quantizer producing a quantized output.