Patent ID: 6180494
Filing Date: 2001-01-30
Classification: H01L,Y10S

Abstract:
A method of fabricating integrated circuitry comprising:forming a conductive line having opposing sidewalls over a semiconductor substrate;depositing an insulating layer over the substrate and the line;etching the insulating layer proximate the line along at least a portion of at least one sidewall of the line;after the etching, depositing an insulating spacer forming layer over the substrate and the line, and anisotropically etching it to form an insulating sidewall spacer along said portion of the at least one sidewall;forming field isolation material regions and active area regions on the semiconductor substrate before the depositing;etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration; andforming a local interconnect layer of material over the substrate which at least partially fills the trench and which electrically connects with one of the active area regions.