Patent ID: 7127550
Filing Date: 2006-10-24
Classification: G01R

Abstract:
1. A memory device for storing data, the memory device comprising: a plurality of modules, the plurality of modules each including a plurality of storage elements, wherein the plurality of storage elements are arranged to hold the data; a logic block, the logic block being arranged to enable a first subset of the plurality of modules to be accessed in parallel, the logic block further being arranged to enable the first subset of the plurality of modules to be accessed serially, wherein the first subset of the plurality of modules includes a first module and a second module, the first module including a first storage element, the second module including a second storage element, the first storage element and the second storage element being included in the plurality of storage elements; and a signal source, the signal source being arranged to provide a signal including the data to at least one of the first storage element and the second storage element, wherein when the logic block enables the first subset of the plurality of modules to be accessed in parallel, the signal source provides the signal to the first storage element and the second storage element substantially concurrently and the signal source is in communication with a testing device to receive the signal from the testing device, the testing device having one or more test heads and a computing device.