Patent ID: 6985014
Filing Date: 2006-01-10
Classification: H03K

Abstract:
1. A circuit comprising: a first stage including first and second active devices, each including three nodes, a junction formed of first nodes of the first and second devices forming a first circuit input port configured to receive an input signal, a junction formed of respective second and third nodes of the first and second devices forming a first stage output port configured to output a delayed signal; a second stage including (i) third, fourth, fifth, and sixth active devices, a junction formed of first nodes of the third and fourth active devices forming a first second stage input port, the first second stage input port being coupled to the first stage output port and (ii) an output port formed of a junction of a respective one of second and third nodes of the third and sixth active devices and the other of the second and third node of the fourth active device, the output port being configured to output an output drive signal; and a charge storing device configured to sense a rate of change of predetermined characteristics of the input signal, the charge storing device having a first end forming a second circuit input port and a second end coupled to a first node of the fifth and sixth devices, the other of the second and third node of the fifth device being coupled to an open node of the fourth device; wherein the second circuit input port is configured to receive the input signal; and wherein the first output drive signal is responsive to the delayed signal and the sensed rate of change.