Patent ID: 7394272
Filing Date: 2008-07-01
Classification: G01R,G11C

Abstract:
1. A built-in self test circuit of a chip on a SIP (system in package), the SIP further including a memory module coupled to the chip, the built-in self test circuit comprising: a test pattern generator, generating test pattern signals based on a mode signal and the type of the memory module, the mode signal at least indicating a test mode and a normal mode; a signal selector, selecting and processing normal mode memory signals from the memory module under the normal mode, selecting and processing the test pattern signals from the test pattern generator to the memory module under the test mode, in response to the mode signal; and a comparator, receiving the test pattern signals from the test pattern generator; wherein in case of the mode signal indicating a test mode, the memory signal selector processes the test pattern signals from the test pattern generator to the memory module and the comparator receives output signals from the memory module to determine the test result; the test result being used for checking which read/write operations and which storage cells of the memory module fail.