Patent ID: 6277682
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method for manufacturing a mixed voltage CMOS integrated circuit comprising the steps of:(a) forming a first gate oxide and a second gate oxide on the substrate;(b) forming a first gate on the first gate oxide and a second gate on the second gate oxide;(c) lightly implanting the substrate with dopants of a first conductivity type, wherein a first photoresist layer is patterned to mask the second gate, the source and drain regions associated with the second gate, and the regions associated with transistors having channels of a second conductivity type;(d) forming side wall dielectrics next to the first gate and next to the second gate;(e) heavily implanting the substrate at an acute angle with dopants of the first conductivity type, wherein a second photoresist layer is patterned to mask the regions associated with transistors having channels of the second conductivity type.