Patent ID: 7516434
Filing Date: 2009-04-07
Classification: G06F

Abstract:
1. A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and comprising code that, when executed, causes a computer to perform the following: (a) placing a plurality of circuit blocks based on a netlist; (b) estimating an interconnection length between two of said placed plurality of circuit blocks based on said netlist and positions of said placed plurality of circuit blocks; (c) judging whether or not said estimated interconnection length satisfies timing constraints for connections among said plurality of circuit blocks, based on relation data indicating relations among interconnection lengths and timings; and (d) outputting said judgment result, wherein: said step (a) includes a step (a1) determining a placement position of a first circuit block of said plurality of circuit blocks based on numbers of connected interconnections among said plurality of circuit blocks, said first circuit block is not placed yet, said step (b) includes a step (b1) estimating said interconnection length based on a first coordinate of a first terminal and a second coordinate of a second terminal, said first terminal represents terminals of said first circuit block, to be connected to a second circuit block, said second circuit block is one of said plurality of circuit blocks, has the connection relation to said first circuit block and is already placed, said second terminal represents terminals of said second circuit block, to be connected to said first circuit block, candidates of said first terminal are a first center point indicating a geometric center of said first circuit block, a first closest point indicating the closest point of said first circuit block to said second circuit block, and a first farthest point indicating the farthest point of said first circuit block to said second circuit block, candidates of said second terminal are a second center point indicating a geometric center of said second circuit block, a second closest point indicating the closest point of said second circuit block to said first circuit block, and a second farthest point indicating the farthest point of said second circuit block to said first circuit block, and said step (b1) includes a step (b11) selecting one of a first interconnection length, a second interconnection length and a third interconnection length as said interconnection length, wherein said first interconnection length is a length of an interconnection connecting said first center point and said second center point, said second interconnection length is a length of an interconnection connecting said first closest point and said second closest point, and said third interconnection length is a length of an interconnection connecting said first farthest point and said second farthest point.