Patent ID: 6378108
Filing Date: 2002-04-23
Classification: H04L

Abstract:
A register formed by a first cell and a plurality of other cells, the register having a test mode in which a scan input of each of the other cells is connected to a scan output of another of the other cells or the first cell so as to form a scan path, each of the other cells comprising:a scan input; a scan output; a flip-flop having an input and an output, the scan input being coupled to the input of the flip-flop and the output of the flip-flop being coupled to the scan output when the register is in a test mode; and an XOR gate, the output of the flip-flop being coupled to a first input of the XOR gate, and the scan input being coupled to a second input of the XOR gate, wherein an output of the XOR gate is coupled to the scan output when the register is not in the test mode, and the output of the XOR gate is uncoupled from the scan output when the register is in the test mode.