Patent ID: 8076216
Filing Date: 2011-12-13
Classification: G01R,H01L

Abstract:
1. A method, comprising: providing a wafer translator having an inquiry-side and a wafer-side; disposing the wafer translator on a vacuum chuck such that the inquiry-side is facing the vacuum chuck; disposing a layer of wafer bonding thermoset plastic on the wafer-side of the wafer translator; patterning the wafer bonding thermoset plastic such that a plurality of wafer-side contact structures are exposed; providing a wafer having a topside and a backside, with a plurality of integrated circuits formed thereon; aligning the topside of the wafer to the wafer-side of the wafer translator; bringing the wafer and wafer translator into contact, and applying heat and pressure to removably attach the wafer and wafer translator, thereby forming a wafer/wafer translator pair in the attached state; thinning the wafer from the wafer backside; performing wafer level testing subsequent to thinning the wafer and prior to dicing the wafer; dicing the wafer to form one or more individual integrated circuits; and removing one or more diced integrated circuits.