Patent ID: 7581070
Filing Date: 2009-08-25
Classification: G06F

Abstract:
1. A multi-chip package device, comprising: first and second memory chips configured to share addresses and control signals, wherein each of the first and second memory chips comprises: wherein the option voltages provided to the first and second memory chips have different voltage levels from each other; wherein the main memory of the first memory chip stores boot code that includes a program capable of performing an operation in conformity with a certain priority processing command; wherein the buffer memory of the first memory chip includes boot memory for temporarily storing the boot code, the boot memory being specified in response to the boot code address; wherein the main memory of the second memory chip does not store any boot code; wherein the buffer memory of the second memory chip does not include any boot memory; and wherein the one-way transition of the buffer access signal of the first memory chip is a transition to an activation level, and the one-way transition of the buffer access signal of the second memory chip is a transition to an inactivation level.