Patent ID: 8098739
Filing Date: 2012-01-17
Classification: H03M,H04N

Abstract:
1. A decoding circuit decoding a data stream subjected to variable length coding, comprising: a dividing circuit dividing data of a predetermined number of bits in the data stream into a plurality of pieces of data from higher-order bits; a plurality of first step comparison circuits receiving the respective divided pieces of data supplied by said dividing circuit and outputting values corresponding to the respective divided pieces of data by referring to a table; a second step comparison circuit outputting decoded data and a number of bits in the data stream corresponding to the decoded data by referring to a variable length coding table based on a table address resulted from the output of the plurality of first step comparison circuits; and a shift circuit shifting the data stream to be divided by said dividing circuit according to the number of bits obtained by the second step comparison circuit, wherein the second step comparison circuit outputs the decoded data, wherein, when the dividing circuit divides data of the predetermined number of bits in the data stream into a plurality of pieces of data, each piece of data includes a plurality of bits, wherein each one of the plurality of bits in the data stream is assigned to a corresponding piece of the plurality of pieces, and wherein each bit in the data stream is assigned to only the one corresponding piece of the plurality of pieces.