Patent ID: 6347387
Filing Date: 2002-02-12
Classification: G06F

Abstract:
A test device for testing inter-device FPGA links among a plurality of FPGAs, said test device comprising:a control circuit for generating an input pattern signal, said control circuit comprising; a counter for generating a count signal; a pattern generator coupled to receive said count signal and generate a different data pattern responsive to each of a plurality of different count signals; and a comparator coupled to receive said output pattern signal from said output terminal of said shift register and for comparing said input pattern signal and said output pattern signal; a descrambler connected to said comparator, said descrambler capable of descrambling said output pattern signal to generate a value corresponding to a count signal and wherein said comparator compares said count signal from said counter to said value generated by said descrambler a shift register coupled to receive said input pattern signal from said control circuit, said shift register having an output for outputting an output pattern signal, said shift register configured from elements of said plurality of FPGAs, and said shift register forming a shift block through said inter-device FPGA links.