Patent ID: 8624880
Filing Date: 2014-01-07
Classification: G09G

Abstract:
1. A light emitting apparatus comprising: a first scan line; a second scan line; a first feed line; a second feed line; a third feed line; a fourth feed line; a data line; a first driving transistor having a first end electrically connected to the first feed line, a second end, and a first gate; a first light emitting device having a first end electrically connected to the second end of the first driving transistor, and a second end connected to the second feed line; a first capacitance device having a first end electrically connected to the first gate of the first driving transistor, and a second end electrically connected to a first source of the first driving transistor; a first selection transistor having a first end electrically connected to the first gate of the first driving transistor, a second end electrically connected to the data line, and a second gate electrically connected to the first scan line; a first reset transistor having a first end electrically connected a first node between the first gate of the first driving and the first end of the first selection transistor, and a second end electrically connected to the third feed line; a second driving transistor having a first end electrically connected to the third feed line, a second end, and a third gate; a second light emitting device having a first end electrically connected to the second end of the second driving transistor, and a second end connected to the second feed line; a second capacitance device having a first end electrically connected to the third gate of the second driving transistor, and a second end electrically connected to a second source of the second driving transistor; a second selection transistor having a first end electrically connected to the third gate of the second driving transistor, a second end electrically connected to the data line, and a fourth gate electrically connected to the second scan line; a second reset transistor having a first end electrically connected to a second node between the third gate of the second driving transistor and the first end of the second selection transistor, and a second end electrically connected to the fourth feed line; and a driving circuit; wherein