Patent ID: 7183828
Filing Date: 2007-02-27
Classification: G01R

Abstract:
1. A shift clock generator for generating a shift clock having a phase which is different from that of a reference clock by a predetermined value, comprising: a clock generating section for generating said shift clock; an insertion pulse generating section for generating insertion pulses to be inserted into said shift clock based on said phase difference preset value; a pulse inserting section for inserting said insertion pulses into said shift clock generated by said clock generating section; and a period control section for controlling periods of said shift clock generated by said clock generating section based on a difference between a sum of time during which said reference clock presents a predetermined logical value within a predetermined time and a sum of time during which said shift clock presents a predetermined logical value within said predetermined time; wherein said insertion pulse generating section comprises: a compensation memory for storing compensation data for calculating a number of insertion pulses to be inserted into said shift clock with respect to said phase difference preset value; a number-of-pulses calculating section for integrating said compensation data stored in an address range of said compensation memory to calculate number-of-insertion pulses data based on said phase difference preset value; and a pulse generating section for generating said insertion pulses based on said number-of-insertion pulses data.