Patent ID: 7064021
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT), the method comprising the steps of: providing a substrate comprising an N type LTPS TFT region and a P type LTPS TFT region; sequentially forming a patterned undoped polysilicon layer, a dielectric layer, a conductive layer, and a first patterned photo resist layer, the first patterned photo resist layer comprising two first gaps; performing an isotropic etching process to remove parts of the conductive layer via the two first gaps to form two second gaps, and to form a gate of an N type LTPS TFT; implanting N type dopants into the patterned undoped polysilicon layer of the N type LTPS TFT region to form a source and a drain of the N type LTPS TFT; removing the first patterned photo resist layer; implanting N type dopants into the patterned undoped polysilicon layer of the N type LTPS TFT region to form two lightly doped drains (LDD) of the N type LTPS TFT; forming a gate of a P type LTPS TFT in the P type LTPS TFT region; and forming a source and a drain of the P type LTPS TFT in the P type LTPS TFT region.