Patent ID: 6468864
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method of fabricating a silicon nitride read only memory (NROM), comprising:providing a substrate forming a trapping layer on the substrate, wherein the trapping layer is formed of an oxide layer, a nitride layer on the oxide layer and a dielectric layer on the nitride layer; forming a patterned photoresist layer on the substrate, wherein the substrate region at a lower portion of the trapping layer masked by the photoresist is defined as a channel, and a substrate region at the lower portion of the trapping layer not covered by the photoresist is defined as a source/drain region; performing a pocket ion implantation step while using the photoresist layer as a mask and implanting a first dopant into the source/drain region of the substrate; removing a part of the trapping layer while using the first dopant as a mask to pattern the trapping layer; performing a source/drain ion implantation step while using the photoresist layer as a mask and implanting a second dopant into the source/drain region of the substrate; removing the photoresist layer, and performing a thermal process using the trapping layer as a mask, wherein a surface of the substrate of the source/drain region forms a buried source/drain oxide layer while the second dopant in the buried source/drain oxide layer simultaneously forms a buried source/drain as a result of thermal diffusion, and the first dopant at an edge of the channel region located at a periphery of the source/drain source forms a pocket doped region; and forming a conductive gate on the substrate.