Patent ID: 6385078
Filing Date: 2002-05-07
Classification: G11C,H01L

Abstract:
A method for controlling a read/write operation of a ferroelectric random access memory (FRAM) device including an array consisted of a plurality of memory cells, arranged in rows and columns, each having a ferroelectric capacitor and an access transistor, the method comprising the steps of:enabling a chip enable flag signal when a chip enable signal is enabled; enabling a row address latch circuit to latch row address signals in response to the chip enable signal; generating a pulse signal in response to at least one transition of the row address signals latched in the row address latch circuit; delaying the pulse signal for a predetermined time; detecting whether or not the chip enable signal is disabled during the predetermined delay time of the pulse signal; and preventing a row decoder circuit from enabling when the chip enable signal is disabled during the delay time of the pulse signal.