Patent ID: 6201487
Filing Date: 2001-03-13
Classification: H03M

Abstract:
An error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, comprising:a first storage device for temporarily storing the run representing the number of zeros (`0`s) in said compressed image data and an end-of-block (EOB) signal externally inputted;a selection signal generator for generating a first and a second selection signal in response to said EOB signal supplied from said first storage device;a first selection circuit for selectively transferring said run supplied by said first storage device or ground signal according to said first selection signal;a second selection circuit for selectively transferring said run supplied by said first storage device or ground signal according to said second selection signal;a reference value generator for generating a reference value based on the output signal of said first selection circuit according to an operation control signal externally inputted;accumulator for accumulating the output of said second selection circuit based on the feedback signal from a second storage device, said second storage device temporarily storing the output of said accumulator; andan error detector for detecting said errors based on said reference value and the output of said second storage device.