Patent ID: 7116137
Filing Date: 2006-10-03
Classification: G11C,H03K

Abstract:
1. A system for reducing power consumption in digital circuits using charge redistribution, comprising: a plurality of signal lines; an intermediate floating virtual source/sink, and a charge redistribution circuit connected to a source and a load portion of at least one of said signal lines that isolates the load portion of said line from its source by entering a high impedance state and that connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state, wherein the charge redistribution circuit comprises a transition detector connected to the source of one of the signal lines and having two outputs, a first of the outputs connected to an input of a tri-state driver circuit, a second of the outputs for simultaneously (i) enabling the tri-state driver circuit to enter the high impedance state and (ii) enabling a control switch to connect an output of the tri-state driver circuit to the floating virtual source/sink whenever a transition is detected on the signal line, the output of the tri-state driver circuit coupled to the load portion of the signal line, and wherein the transition detector comprises a delay circuit having its input connected to the source of the signal line and its output connected to the first output of the transition detector and to a first input of a 2-input exclusive-OR or exclusive-NOR gate while a second input of the gate is directly connected to the source of the signal line and its output is connected to the second output of the transition detector.