Patent ID: 7245152
Filing Date: 2007-07-17
Classification: H03K

Abstract:
1. A voltage-level shifter comprising: an input to receive an input voltage; a first pair of transistors coupled to the input, the first pair of transistors to receive the input voltage, invert the input voltage into a first signal, and output the first signal; a second pair of transistors coupled to the first pair of transistors, the second pair of transistors to receive the first signal, invert the first signal into a second signal, and output the second signal; a third pair of transistors coupled to the input, the third pair of transistors to receive the input voltage, invert the input voltage into a third signal, and output the third signal; a first transistor coupled to the second pair of transistors, wherein when asserted the first transistor is configured to pass the second signal to a third transistor, the second signal being an assert signal for asserting the third transistor; a second transistor coupled to the third pair of transistors, wherein when asserted the second transistor is configured to pass the third signal to a fourth transistor, the third signal being an assert signal for asserting the fourth transistor, wherein when asserted the third transistor is configured to pass a deassert signal for deasserting the fourth transistor, wherein when asserted the fourth transistor is configured to pass an output voltage to an output of the voltage level shifter, the output voltage having a higher voltage level relative to the input voltage, the output voltage further representing a deassert signal for deasserting the third transistor.