Patent ID: 6738953
Filing Date: 2004-05-18
Classification: G06F

Abstract:
A memory characterization method, comprising the steps:generating a plurality of tiles operable to model a memory instance, said plurality of tiles including at least one of a sub-plurality of row decoder tiles, a sub-plurality of input/output (I/O) block tiles, a sub-plurality of bitcell array tiles and at least one control block tile; providing input and output pins for each tile with respect to a plurality of global signals spanning said memory instance in at least one of a horizontal and a vertical direction; obtaining a parametric dataset for each of said plurality of tiles; and creating a hierarchically-stitched parametric netlist for said memory instance by coupling said parametric datasets using said input and output pins of said plurality of tiles with respect to said global signals, said hierarchically-stitched parametric netlist for simulating said memory instance.