Patent ID: 7797561
Filing Date: 2010-09-14
Classification: G06F,Y02D

Abstract:
1. An apparatus, comprising: a processing pipeline of an electronic chip have a sequence of functional blocks and a directional flow of data through the sequence of functional blocks, a plurality of said functional blocks in said processing pipeline including at least a first functional block and a second functional block, with the plurality of functional blocks having individual clock gates to independently adjust clock signals to each of said plurality of functional blocks; at least one clock control module configured to receive a clock-control signal and in response adjust the clock gating of each of said clock gates of said plural of functional blocks; and a status module configured to determine the status of data-flow through the processing pipeline and produce the clock-control signal based on the status of a data-flow to independently control the clock signal to each of the functional blocks based on the data-flow, wherein the second functional block is upstream from the first functional block, the status module is configured to send a clock-disabled indicator to the second functional block indicating when the clock signal to the first functional block has been disabled, the clock-disabled indicator is used to prevent the second functional block from sending a data to the first functional block when the clock signal to the first functional block is disabled, wherein the status module is configured to determine the status of the data-flow based on an activity-level of an interface circuit disposed between the first functional block and the second functional block, the interface circuit being configured to transport data between the first functional block and the second functional block.