Patent ID: 8432216
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. A data-path cell produced on a semiconductor-on-insulator (SeOI) substrate comprising a thin layer of semiconductor material separated from a bulk substrate by an insulating layer, the cell comprising an array of field-effect transistors (FETs), each transistor comprising: within the thin layer of semiconductor material of the SeOI substrate, a source region, a drain region and a channel region interposed between the source and drain regions, and a front control gate above the channel region; and one or more back control gates formed within the bulk substrate of the SeOI substrate beneath the channel region of one or more FETs, with each back control gate associated with a particular transistor being configured and positioned so that the performance characteristics of that transistor varies in dependence on a bias applied to the back control gate, wherein the size and configuration of the FETs and the size and configuration of the back control gates are selected so that the data path cell is specifically adapted for use in the environment of a particular integrated circuit.