Patent ID: 7425476
Filing Date: 2008-09-16
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line including a gate electrode; forming a gate insulating layer on the gate line; forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe; forming a data line including a source electrode and a drain electrode on the ohmic contacts; depositing a passivation layer on the data line and the drain electrode; and forming a pixel electrode connected to the drain electrode, wherein forming the data line, the drain electrode, the ohmic contacts, and the semiconductor stripe comprises: depositing an intrinsic silicon layer, an extrinsic silicon layer, and a conductor layer on the gate insulating layer; forming a photoresist including a second portion corresponding to a channel area between the source electrode and the drain electrode, and a first portion corresponding to a wire area on the data line and the drain electrode, wherein the first portion is thicker than the second portion; etching the conductor layer corresponding to a remaining area except for the wire area and the channel area using the photoresist as an etch mask; removing the second portion of the photoresist to expose the conductor layer on the channel area; etching the intrinsic silicon layer and the extrinsic silicon layer on the remaining area and a portion of the conductor layer corresponding to the channel area in the same etching step; etching the rest of the conductor layer and the extrinsic silicon layer on the channel area after the etching of the portion of the conductor layer; and removing the first portion of the photoresist.