Patent ID: 9209271
Filing Date: 2015-12-08
Classification: B82Y,H01L

Abstract:
1. A method for fabricating a vertical III-V nanowire field-effect transistor, the method comprising: depositing a first layer of doped III-V semiconductor material on a substrate of III-V semiconductor material; depositing a layer of undoped III-V semiconductor material on top of said first layer of doped III-V semiconductor material; depositing a second layer of doped III-V semiconductor material on top of said layer of undoped III-V semiconductor material; growing a first dielectric layer on top of said second layer of doped III-V semiconductor material; depositing self-assembled monolayers of nanospheres on said first dielectric layer; and forming nanopillars using said nanospheres as a mask and said first dielectric layer as a hard mask to etch said second layer of doped III-V semiconductor material and said layer of undoped III-V semiconductor material using nanosphere lithography.