Patent ID: 7586850
Filing Date: 2009-09-08
Classification: H04L

Abstract:
1. A method for reducing head of line blocking in a first multi-port frame-based buffered storage switch having transmit buffers and receive buffers associated with each port when a high speed destination device attached to a first destination port and a low speed destination device attached to a second destination port both need to receive data from a high speed source device communicatively coupled to one or more source ports, the method comprising: maintaining a table of recent accesses at said ports; receiving a request to transfer data at the one or more source ports; determining a speed of a presumed destination device by reference to said table; if the presumed destination device is a low speed destination device, transferring data to the receive buffers of a source port only after determining that the data can be subsequently transferred to the transmit buffers of the second destination port attached to the low speed destination device without impediment; and if the presumed destination device is a high speed destination device, transferring data to the receive buffers of a source port only as long as the receive buffers have space to store the data.