Patent ID: 8370691
Filing Date: 2013-02-05
Classification: G01R,G06F,G11C,H03K

Abstract:
1. A programmable logic device (PLD) comprising: configuration memory including a configuration memory cell adapted to function as random access memory (RAM), the configuration memory cell having a first port for writing configuration data to the cell and a second port for writing RAM data to the cell; soft error detection (SED) logic adapted to check for an error in data stored by the configuration memory including the configuration memory cell by calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory; and a fuse configurable in a first logic state to enable RAM data from the configuration memory cell to be read through the first port for calculating the present data value of the configuration memory and configurable in a second logic state to prevent RAM data from being read from the configuration memory cell.