Patent ID: 9042492
Filing Date: 2015-05-26
Classification: H04L

Abstract:
1. An apparatus, comprising: a demodulator to process a continuous-time signal to generate a plurality of encoded bits, the plurality of encoded bits are generated from a plurality of symbols, the plurality of symbols having n bits per symbol; an inner decoder to process a first subset of bits within the plurality of encoded bits to correct selected ones of the first subset of bits to form a corrected first subset of bits and to generate partially corrected data from the plurality of encoded bits based on the corrected first subset of bits, wherein the first subset of bits correspond to a plurality of least significant bits of the n bits per symbol; an outer decoder to process the partially corrected data, to correct selected ones of a second subset of the plurality of encoded bits to form a corrected second subset of bits; and a bit combiner to generate data estimates by combining the corrected first subset of bits and the corrected second subset of bits.