Patent ID: 6025739
Filing Date: 2000-02-15
Classification: H03K

Abstract:
A circuit for providing a logic function while reducing a pass-through current flowing between a first voltage terminal and a second voltage terminal during transitions of at least one input signal, the input signal transitioning between at least two states, said circuit comprising:(a) a first transistor having a source coupled to the first voltage terminal, the first transistor having a drain and a gate receiving the input signal;(b) a second transistor having a source coupled to the drain of said first transistor, the second transistor having a drain and a gate;(c) a third transistor having a source, a drain coupled to the drain of said second transistor, and a gate, the drains of said second and third transistors being coupled to produce an output signal providing the logic function;(d) a fourth transistor having a drain coupled to the source of said third transistor, the fourth transistor having a source coupled to the second voltage terminal and a gate receiving the input signal; and(e) means for sampling the output signal at the drains of said second and third transistors and providing the output signal to the gates of said second and third transistors, said second and third transistors being responsive to said sampling means to enter an off-state during transitions of the input signal,wherein said second and third transistors interrupt the current flowing between the first voltage terminal and the second voltage terminal by entering the off-state during transitions of the input signal, thereby reducing the pass-through current.