Patent ID: 7099135
Filing Date: 2006-08-29
Classification: H02H

Abstract:
1. An inrush current limiter circuit, comprising: a first transistor operating in response to a control signal and having a first source coupled to an input node to receive a supply voltage and a drain coupled to an output node of the inrush current limiter circuit wherein the output node is configured to be plugged to a power supply that concurrently is supplying the supply voltage, the drain coupled for routing a load current of the supply voltage to the output node as a protection signal, the first transistor also having a gate coupled to receive the control signal; and a second transistor operating in response to the control signal and having a second source scaled to the first source and coupled to the input node for routing a portion of the load current to the output node as a sense current, the second transistor having a gate that is common with the gate of the first transistor; and a detection circuit configured to receive the sense current and responsively form the control signal to operably limit a maximum value of current flow through the first transistor wherein the maximum value is greater than zero.