Patent ID: 8201012
Filing Date: 2012-06-12
Classification: G06F,H02M,H03K,H04R

Abstract:
1. A frequency jittering device, comprising: a Variable State Machine for generating a variable logic number; a Time delay generator for generating a delay signal; a Digital Control Pulse Density Generator for generating a PWM control signal according to the variable logic number and the delay signal; a PWM Control Current Source for generating an output signal according to the PWM control signal; and a Current Control Oscillator for generating a clock signal with variable frequency according to the output signal; wherein the clock signal is fed back to the Variable State Machine to update the variable logic number, and a jittering clock signal modified in each clock cycle is produced; wherein the Digital Control Pulse Density Generator comprises: wherein the PWM control signal is realized by inserting the delay signal into the ring oscillator and receiving the variable logic number from the decoder.