Patent ID: 6141714
Filing Date: 2000-10-31
Classification: G06F

Abstract:
An apparatus for processing system bus operations to avoid deadlock conditions, the apparatus comprising:a plurality of processors each for executing instructions;memory for storing data;a system bus for transferring the stored data to the processors for execution, and for communicating operations to each of the processors;a first cache for a first one of the processors for processing snooped operations, the first cache including:first means for ensuring, by monitoring said system bus for retry signals, that each snooped operation is accepted by each one of the processors via their at least one cache before each snooped operation is processed; anda second cache for a second one of the processors for processing snooped operations, the second cache including:second means for ensuring, by monitoring said system bus for retry signals, that each snooped operation is accepted by each one of the processors via their at least one cache before each snooped operation is processed.