Patent ID: 7772057
Filing Date: 2010-08-10
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit with gate self-protection, said integrated circuit comprising a MOS device and a bipolar device region, said method comprising the steps of depositing a dielectric layer over a semiconductor layer in which electrically active and electrically inactive regions are formed; depositing a gate conductor layer over said dielectric layer; defining a base region of said bipolar device region and a selected region of said MOS device, wherein in said selected region of said MOS device said dielectric layer overlies an electrically active region of said semiconductor layer; removing said gate conductor layer in said base region of said bipolar device region and in said selected region of said MOS device; removing said dielectric layer in said base region of said bipolar device region and in said selected region of said MOS device; depositing a base layer on said gate conductor layer and on said semiconductor layer in said selected region of said MOS device and in said base region of said bipolar device region.