Patent ID: 6111785
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device having a main storage circuit in which memory cells comprised of floating-gate field-effect transistors capable of executing electrical writing and erasing are arranged in a matrix form, a redundancy storage circuit in which memory cells comprised of floating-gate field-effect transistors capable of executing electrical writing and erasing are arranged in a matrix form and a redundancy function which takes effect, when a defective column line, a defective row line or a defective memory cell exists in the main storage circuit, to replace the defective component with a normal column line, a normal row line or a normal memory cell in the redundancy storage circuit, the device comprising:a defective address storage circuit which is constructed of memory cells comprised of floating-gate field-effect transistors capable of executing electrical writing and erasing and in which address data of the defective column line, defective row line or defective memory cell is written; anda latch circuit which once latches the inputted address data when the address data is written into the defective address storage circuit and latches the address data that is being written in the defective address storage circuit when a power voltage rises.