Patent ID: 7863131
Filing Date: 2011-01-04
Classification: G11C,H01L

Abstract:
1. A semiconductor manufacturing method for a memory cell array of a semiconductor device, comprising: depositing a first conductive film over a semiconductor substrate and forming a first gate electrode and an auxiliary pattern electrically isolated from the first gate electrode; forming a first insulator film over the first gate electrode, the auxiliary pattern, and the semiconductor substrate; depositing a second conductive film over the first insulator film and, by etching back the second conductive film, respectively forming a side wall electrode along the first gate electrode interposing the first insulator film between the side wall electrode and the first gate electrode, and forming an extended electrode on a circumference of the auxiliary pattern as said extended electrode merges with side wall electrode; exposing the upper surface of the auxiliary pattern and the first gate electrode by stripping away the first insulator film formed over the first gate electrode and the auxiliary pattern; siliciding the upper surface of the first gate electrode, and the surface of the side wall electrode; forming a second insulator film over the auxiliary pattern and the extended electrode; forming at least one or more contact holes on the second insulator film and, exposing the extended electrode at the forming of one of the contact holes; and forming contacts in the contact holes.