Patent ID: 8189358
Filing Date: 2012-05-29
Classification: G11C,H01L

Abstract:
1. A semiconductor device having a static memory cell array, the static memory cell array comprising: first and second static memory cells, first, second, third and fourth word lines, and first and second pairs of bit lines, wherein each of the first and second static memory cells includes a latch circuit having a first inverter and a second inverter, a first access transistor and a second access transistor coupled to the first latch circuit, and a third access transistor and a fourth access transistor coupled to the second latch circuit, wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor, wherein the first word line is electrically coupled to the first and third access transistors of the first static memory cell, the second word line is electrically coupled to the second and fourth access transistors of the first static memory cell, the third word line is electrically coupled to the second and fourth access transistors of the second static memory cell, and the fourth word line is electrically coupled to the first and third access transistors of the second static memory cell, wherein one of the first pair of bit lines is electrically coupled to the first access transistor of each of the first and second static memory cells, the other of the first pair of bit lines is electrically coupled to the third access transistor of each of the first and second static memory cells, and one of the second pair of bit lines is electrically coupled to the second access transistor of each of the first and second static memory cells, and the other of the second pair of bit lines is electrically coupled to the fourth access transistor of each of the first and second static memory cells, wherein the first and third access transistors and the first driver transistor of each of the first and second static memory cells are disposed in a first well of a first conductive type, wherein the first and the second load transistors of the first and second static memory cells are disposed in a second well of a second conductive type, wherein the second and fourth access transistors and the second driver transistor of each of the first and second static memory cells are disposed in a third well of the first conductive type, wherein the first, second and third wells are arranged in a first direction in a row, wherein the first and second static memory cells are arranged mirror-symmetrically with respect to each other about a line extending between said first and second static memory cells, wherein the first static memory cell is arranged between the first word line and the second word line, wherein the second static memory cell is arranged between the third word line and the fourth word line, wherein the second word line and the third word line are arranged adjacently, and wherein a first distance between the first word line and the second word line is longer than a second distance between the second word line and third word line.