Patent ID: 8050075
Filing Date: 2011-11-01
Classification: G11C

Abstract:
1. A memory comprising: first and second memory blocks including memory cells arranged in matrix, the first block including bit lines aligned parallel to each other between boundaries of the first block, the boundaries of the first block being parallel with the bit lanes of the first block, the second block including bit lines aligned parallel to each other between boundaries of the second block, the boundaries of the second block being parallel with the bit lines of the second block; word lines intersecting with the bit lines in the first and second blocks, respectively; and conductive lines provided so as to extend parallel to the word lines, the memory cells being arranged on intersectional positions between the conductive lines and bit lines in the first and second blocks, each memory cell comprising a diode having an anode connected to a corresponding bit line and a cathode connected to a corresponding conductive line, wherein a bit line in the first block and a bit line in the second block are simultaneously selected, and the selected bit line in the first block is one close to one of the boundaries of the first block and the selected bit line in the second block is one distant from the boundaries of the second block, and vice versa.