Patent ID: 6913967
Filing Date: 2005-07-05
Classification: H01L

Abstract:
1. A method for fabricating a ferroelectric memory device, comprising the steps of: forming a storage node contact making a contact to a semiconductor substrate by passing through the first inter-layer insulating layer formed on the semiconductor substrate; forming a stack pattern of a barrier layer connected to the storage node contact and a lower electrode; forming a space between the lower electrode and the first inter-layer insulating layer by removing selectively lateral sides of the barrier layer; forming simultaneously a glue layer encompassing the lateral sides of the lower electrode as filling the space; forming a second inter-layer insulating layer exposing a surface of the lower electrode as laterally encompassing the glue layer; forming a ferroelectric layer on the second inter-layer insulating layer including the lower electrode; and forming an upper electrode on the ferroelectric layer.