Patent ID: 8294270
Filing Date: 2012-10-23
Classification: H01L,Y10T

Abstract:
1. An integrated circuit including a first layer having metal or metal alloy at a surface thereof, a second layer adjacent to said surface having a metal or metal alloy via therein, an interlayer connection between metal or metal alloy of said first layer and said metal or metal alloy via, said interlayer connection comprising a diffusion barrier and a stable alloy region having a concentration of alloying material which is continuously graded from a diffusion reaction front at a surface of one of said first layer and said second layer and graded mechanical characteristics, said stable alloy region containing a predetermined quantity of alloying material which is restricted to a region of one of said metal or metal alloy of said first layer and said metal or metal alloy via by said barrier layer and by said quantity of alloying material being fully reacted with said metal or metal alloy of said first layer or said second layer.