Patent ID: 7768754
Filing Date: 2010-08-03
Classification: H01C,H01L,H05K,Y10T

Abstract:
1. A device comprising: a ceramic substrate having a top surface and a bottom surface, the ceramic substrate providing electrostatic discharge (ESD) protection of a semiconductor device mounted over the top surface, a first metal layer overlying a portion of the first surface of the first layer; a second metal layer in contact with the first layer between the first layer and the second layer; a first electrode area electrically coupled to the first metal layer to which a first electrode of the semiconductor device is electrically connected when mounted over the first surface; a second electrode area electrically coupled to the second metal layer to which a second electrode of the semiconductor device is electrically connected when mounted over the first surface, whereby the first metal layer, the first layer, and the second metal layer form a low resistance path between the first electrode area and the second electrode area when a voltage between the first electrode area and the second electrode area exceeds a threshold.