Patent ID: 7629643
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor fin comprising a semiconductor fin material; at least one multi-gate pull down (PD) device connected directly to the semiconductor fin; a first associated n-type dopant concentration tip region, which formed in the semiconductor fin material, is directly connected to the PD device; and at least one multi-gate pass gate (PG) device connected directly to the semiconductor fin; a second associated n-type dopant concentration tip region, which formed in the semiconductor fin material, is directly connected to the PG device; wherein a second dopant concentration of the second n-type dopant concentration tip region is lower than a first dopant concentration of the first n-type dopant concentration tip region; and wherein the first and second associated n-type dopant concentration tip regions are doped a same dopant; wherein the semiconductor fin and each of the PD and PG devices are part of a static random access memory (SRAM) cell having a β ratio that is about equal to one, the β ratio being defined as: in which Z