Patent ID: 7304353
Filing Date: 2007-12-04
Classification: H01L

Abstract:
1. A CMOS device manufactured by the process comprising: defining at least one standard voltage threshold first type region in a substrate; defining at least one standard voltage threshold second type region in said substrate; defining at least one low voltage threshold first type region in said substrate; defining at least one low voltage threshold second type region in said substrate; forming a first type well in said substrate at each location defining said standard voltage threshold second type region; forming a first type well in said substrate at each location defining said low voltage threshold second type region; forming a second type well in said substrate at each location defining said standard voltage threshold first type region; forming a second type well in said substrate at each location defining said low voltage threshold first type region; doping said substrate with a first voltage threshold implant such that each standard voltage threshold second type region, each low voltage threshold first type region, and each low voltage threshold second type region is exposed to said first voltage threshold implant; doping said substrate with a second voltage threshold implant such that each standard voltage threshold first type region, each low voltage threshold first type region, and each low voltage threshold second type region is exposed to said second voltage threshold implant; forming a polysilicon gate over each of said first and second type wells; doping said polysilicon gates over each of said first type wells with a first gate conductor dopant; and doping said polysilicon gates over each of said second type wells with a second gate conductor dopant.