Patent ID: 7768037
Filing Date: 2010-08-03
Classification: G11C,H01L

Abstract:
1. In an integrated circuit chip including a plurality of metal layers and first and second supply potentials, a programmable memory cell for storing a value, the memory cell comprising: a plurality of first metal interconnect structures that traverse the plurality of metal layers using a first plurality of vias; a plurality of second metal interconnect structure that traverse the plurality of metal layers using a second plurality of vias and coupled to the first metal interconnect structures to form a plurality of programmable cycles, wherein each half cycle is programmable at least once; and an output coupled to one of the first and second supply potentials by at least one of said first and second metal interconnect structures; wherein at least one cycle is laid out to form a spiral-shaped structure that traverses the plurality of metal layers from a bottom metal layer to a top metal layer and back to the bottom metal layer, and wherein the first and second supply potentials comprise two buses located in a central region of the spiral-shaped structure and are accessible at each of the metal layers.