Patent ID: 9147608
Filing Date: 2015-09-29
Classification: H01L,Y10S

Abstract:
1. A method for integrated circuit fabrication, comprising: forming a plurality of mask lines in a first region of an integrated circuit structure, wherein the mask lines form loops, each loop having looped ends at ends of the loop; depositing a selectively definable material over the integrated circuit structure; patterning the selectively definable material to expose portions of the mask lines between the loop ends, while covering a width of the mask lines at the loop ends, and while defining a plurality of features in a second region of the integrated circuit structure, wherein the patterned selectively definable material and the exposed portions of the mask lines form a mask; and transferring a pattern defined by the mask to underlying material, wherein a minimum width of the features in the second region is greater than a minimum width of the mask lines.