Patent ID: 7906383
Filing Date: 2011-03-15
Classification: H01L

Abstract:
1. A method, comprising: forming a first stress-inducing layer above a first transistor and a second transistor formed above a substrate, said first stress-inducing layer generating a first type of stress; reducing a magnitude of said first type of stress of said first stress-inducing layer above said second transistor; depositing a buffer layer above said first stress-inducing layer and said first and second transistors; after reducing the magnitude of said first type of stress of said first stress-inducing layer, forming a second stress-inducing layer above said buffer layer while maintaining said buffer layer covering said first and second transistors, said second stress-inducing layer generating a second type of stress differing from said first type of stress, wherein said buffer layer has a thickness that is less than a thickness of said first stress-inducing layer and wherein said buffer layer is configured to reduce a surface topography above said first and second transistors; and forming an interlayer dielectric material above said first and second transistors, wherein said first stress-inducing layer, said buffer layer, and said second stress-inducing layer remain above at least said second transistor after forming said interlayer dielectric material.