Patent ID: 6826083
Filing Date: 2004-11-30
Classification: G11C

Abstract:
An NROM device comprising:a memory array, formed by a plurality of memory cells organized in rows and columns and provided with first conductive regions formed in a semiconductor body and connected to first bitlines, second conductive regions formed in said semiconductor body and connected to second bitlines, charge storage regions of insulating material, formed on top of said semiconductor body, and gate regions arranged on top of said charge storage regions and connected to respective wordlines; and a programming circuit for a selected cell connected to a selected one of the wordlines, the programming circuit having a plurality of drivers, including a first driver and second drivers, said first driver supplying a first voltage of a first value with respect to said semiconductor body to the selected one of said wordlines, and said second drivers configured to supply a second voltage having a non-zero second value, lower than said first value, to a plurality of said wordlines, excluding said selected wordline, each of said plurality of drivers having a signal input receiving a control signal, an output connected to a respective one of the wordlines, a first supply input connected to a first supply line, set at said first voltage, and a second supply input connected to a controllable biasing circuit.