Patent ID: 6904481
Filing Date: 2005-06-07
Classification: G06F

Abstract:
1. A method of handling bus operations in a computer system having a processor for forming a plurality of bus operation information structures, a plurality of memory spaces for containing the bus operation information structures and a sequencer for processing the bus operation information structures to perform the bus operations, comprising the steps of: sequentially forming each bus operation information structure by the processor in the memory spaces, said each bus operation information structure including both a command and data, said each bus operation information structure including an owner field indicating whether the processor or the sequencer has control over said each bus operation information structure; upon forming each bus operation information structure, setting control over the bus operation information structure to the sequencer by setting a corresponding owner field of the bus operation information structure; determining whether the sequencer has control over a first one of the bus operation information structures based on an owner field of the first one of the bus operation information structure; upon determining that the sequencer has control over the first bus operation information structure, processing the first bus operation information structure by the sequencer; determining whether the sequencer has control over a second one of the bus operation information structures based on an owner field of the second one of the bus operation information structure; and upon determining that the sequencer has control over the second bus operation information structure, processing the second bus operation information structure by the sequencer, wherein the computer system includes a central processing unit (CPU) and a bus adapter, the bus adapter including the processor, the sequencer and the memory spaces, the CPU being communicatively coupled to the bus adapter.