Patent ID: 6177959
Filing Date: 2001-01-23
Classification: G09G,H03L,H04N

Abstract:
A clock generation circuit for generating a clock signal synchronized with an edge of a time reference signal, said clock generation circuit comprising:a first oscillator for generating an internal reference signal;a phase detector coupled to said first oscillator, said phase detector generating an error voltage proportionate to the difference in phases of said internal reference signal and a divider output signal;a voltage controlled oscillator coupled to said phase detector, said voltage controlled oscillator generating an internal clock signal having a frequency substantially equal to the frequency of said clock signal, wherein the frequency of said internal clock signal is a low multiple of the frequency of said internal reference clock signal, and wherein the frequency of said internal clock signal is changed according to said error voltage;a divider coupled to said voltage controlled oscillator and said phase detector, said divider generating said divider output signal, wherein said divider output signal is generated by dividing the frequency of said internal clock signal by said low multiple;a resettable oscillator driven by said error voltage for generating an SCLK signal, said resettable oscillator having a restart input, wherein said SCLK signal is not generated when said restart input is asserted;a restart generation circuit for asserting said restart input a short duration prior to the expected arrival of said edge of said time reference signal, said restart generation circuit deasserting said restart input on the arrival of said edge of said time reference signal, whereby said SCLK signal is synchronized with said edge of said time reference signal;a stop circuit for generating a stop signal a few cycles after said edge of said time reference signal is received;an AND gate for receiving said SCLK signal and said stop signal, said AND gate providing said SCLK signal as said clock signal when said stop signal is not generated.