Patent ID: 7421525
Filing Date: 2008-09-02
Classification: G06F

Abstract:
1. A system comprising: a host; and a plurality of memory modules coupled serially in a chain to said host via a plurality of memory links, wherein each of said plurality of memory links includes an uplink for conveying transactions toward said host and a downlink separate from the uplink for conveying transactions originating at said host to a next memory module in said chain, and wherein each of said plurality of memory modules includes a memory control hub coupled to control access to a plurality of memory chips mounted thereon and coupled to said host via both said uplink and said downlink, wherein said uplink and said downlink are each a separate uni-directional link including a plurality of signals configured to convey transactions using packets that include control and configuration packets and memory access packets, wherein at least a portion of the packets include control, address and data information, and wherein said control, address and data information share the same wires of a given one of the separate uni-directional links, and wherein the plurality of signals of said downlink further include a busy signal indicating to each memory control hub a number of local transactions being injected by said memory control hub and by memory control hubs of each of said plurality of memory modules coupled between said host and said memory control hub, the memory control hub injecting packets into said uplink in response to said busy signal, and wherein said plurality of memory modules includes at least a first memory module and a last memory module, and wherein the plurality of memory modules are serially connected in the chain such that the first memory module is connected to said host via a first memory link of the plurality of memory links and the last memory module is a last memory module in the chain and all of the plurality of memory modules are connected to two of the plurality of memory links except that the last memory module is only connected to one of the plurality of memory links, and wherein the memory control hub of the last memory module discards any packet which is received and does not include an address within a range of addresses assigned to the last memory module.