Patent ID: 6143606
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A method for manufacturing a split-gate flash memory cell comprising:providing a semiconductor substrate having at least one multi-layer gate structure formed thereon, wherein the multi-layer gate structure includes a first conductive layer, a dielectric layer, a second conductive layer and a silicon nitride layer;forming a first spacer around the sides of the multi-layer gate structure;forming a polysilicon layer over the multi-layer gate structure and above the semiconductor substrate;forming a second spacer around the sides of the polysilicon layer;using the second spacer as a mask, performing a first ion implantation implanting ions into the semiconductor substrate to form a drain region;removing the second spacer to expose the polysilicon layer;forming a mask over the polysilicon layer, and then performing a second ion implantation implanting ions into the semiconductor substrate to form a source region; andforming a third conductive layer over the semiconductor substrate and the multi-layer gate structure.