Patent ID: 8767472
Filing Date: 2014-07-01
Classification: G11C

Abstract:
1. An apparatus comprising: a first memory cell; a second memory cell located on a first side of the first memory cell; a third memory cell located on a second side the first memory cell; a fourth memory cell located on the first side of the first memory cell; a fifth memory cells located on the second side the first memory cell; and a module configured to apply, during a memory operation, a first voltage to a gate of the first memory cell, a second voltage to a gate of the second memory cell and a gate of the third memory cell, and a third voltage to a gate of the fourth memory cell and a gate of the fifth memory cell, wherein the first, second, and third voltages have different values, wherein the fourth memory cell is immediately adjacent the first memory cell, and a value of the third voltage is greater than a value of the second voltage.