Patent ID: 6038271
Filing Date: 2000-03-14
Classification: H04B

Abstract:
A correlator comprising:a data bus for receiving blocks of n bit parallel in phase (I) and n bit parallel quadrature (Q) signal data and n bit parallel I and Q reference data from respective I and Q signal channels and I and Q reference channels, said data bus having n parallel paths extending therefrom;a circuit positioned along each n parallel path extending from said data bus for receiving the n bit parallel I and Q signal data and n bit parallel I and Q reference data and correlating the respective I and Q reference data with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path and producing an I component signal output and Q component signal output along each of the individual n parallel paths;an output bus for receiving I and Q component signal outputs from the n parallel paths one at a time at one bit input time periods such that there is one correlation product output for every I and Q pair of input bits; anda cascade adder circuit comprising at least one adder connected to the output bus and receiving the I and Q component signal outputs from the output bus and delayed I and Q component signal outputs from another correlator, wherein said cascade adder circuit sums the I and Q component signal outputs with the delayed I and Q component signal outputs from another correlator to allow correlator expansion.