Patent ID: 7510914
Filing Date: 2009-03-31
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a first insulation interlayer on a semiconductor substrate; forming a first etch stop layer on the first insulation interlayer; successively stacking a barrier layer, a metal layer and a capping layer on the first etch stop layer; forming a second etch stop layer on the capping layer to reduce the metal layer from being exposed during an etching process; patterning the stacked layers to form a metal wiring on the first etch stop layer and a plurality of fuses on the first etch stop layer; forming a second insulation interlayer on the metal wiring, the plurality of fuses and the first etch stop layer; and etching the second insulation interlayer to form an opening exposing a fuse box region.