Patent ID: 7554876
Filing Date: 2009-06-30
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a first word line driver unit for including N unit driving circuits for driving N word lines of a first cell block, the N unit driving circuits being divided into M group driving circuits; a second word line driver unit for including N unit driving circuits for driving N word lines of a second cell block, the N unit driving circuits being divided into M group driving circuits; a common address latch unit for latching a first address for selecting one of the M group driving circuits included in the first or second word line driver units, respectively, and outputting the latched first address to the first or second word line driver unit; a first address latch unit for latching a second address for selecting a unit driving circuit of the selected group driving circuit in the first word line driver unit, and outputting the latched second address to the first word line driver unit; and a second address latch unit for latching the second address for selecting a unit driving circuit of the selected group driving circuit in the second word line driver unit, and outputting the latched second address to the second word line driver unit.