Patent ID: 6531363
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of said silicon substrate by a thermal oxidation, forming a resist mask covering a region in which said silicon oxide film is required, ion-implanting a P-type impurity using said resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of said N-well and said P-well, so as to form a P-type buried impurity layer, thereafter removing said silicon oxide film not covered with said resist mask by an etching, then removing said resist mask, and conducting a thermal oxidation on the whole surface of said silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with said resist mask, and a relatively thin gate oxide film is formed on a region which was not covered with said resist mask, and thereafter, forming a gate electrode and a source/drain diffused layer in a required well.