Patent ID: 7669194
Filing Date: 2010-02-23
Classification: G06F

Abstract:
1. A method in a data processing system for minimizing effective memory latency, the method comprising: analyzing a portion of code that contains one or more loops, to form a loop table; identifying at least one candidate loop within the one or more loops of the loop table for prefetch efficiency optimization; inserting prefetch control instructions and directives to optimize the at least one candidate loop, wherein the prefetch control instructions and directives are inserted at selected locations in an instruction stream, in advance of data use, according to a stream type, and wherein a stream is a sequence of addresses which depend upon an induction variable of the at least one candidate loop; determining whether pipelining is available; responsive to a determination that pipelining is not available, adjusting prefetch addresses in the prefetch control instructions forward to fetch cache lines in advance of data use; gathering memory references of the at least one candidate loop; and performing at least one of data dependency analysis and reuse analysis on the at least one candidate loop to identify unique streams within the at least one candidate loop.