Patent ID: 7426667
Filing Date: 2008-09-16
Classification: G01R,G06F

Abstract:
1. A method of generating a power-on-reset clock signal immediately after power up comprising: coupling a power-on-reset output from a power-on-reset circuit to an input of an oscillator circuit to produce a first clock signal and to a reset input of a latch; coupling a reset input of a memory test device to said output of said power-on-reset circuit, wherein said data input of said memory test device is coupled to a VDD power line; coupling a row-control signal line and a column-control signal line of said memory test device to an output of said oscillator circuit; coupling an output of said oscillator circuit to a first frequency divider; coupling an output of said first frequency divider to an input of a second frequency divider; coupling an output of said second frequency divider to an Nth frequency divider, wherein said first clock signal reaches a desired frequency for clearing and programming operations; coupling to the output of said oscillator circuit to a first input of a two-input combinational circuit; coupling an output of said Nth frequency divider to a second input of a two-input combinatorial circuit through said latch, wherein an output of said two-input combinatorial circuit generates a second clock signal through a clock signal output line.