Patent ID: 6690631
Filing Date: 2004-02-10
Classification: G06F,G11B,H03L

Abstract:
A clock generation circuit (30) comprising:a programmable frequency divider (46) having a single clock input (45) for receiving an input clock signal (CLin), said programmable frequency divider (46) for generating an intermediate clock signal (CLa) from the input clock signal (CLin), a first logical unit (47) having a first input for receiving the the input clock signal (CLin) and a second input for receiving the intermediate clock signal (CLa), the first logical unit (47) for combining the input clock signal (CLin) and the intermediate clock signal (CLa) into a combined clock signal, a clocked bi-stable unit (48) having a clock input directly coupled to an output of the first logical unit (47) for receiving the combined clock signal, the clocked bi-stable unit (48) further having a data input directly connected to an output (49c) of a second logical unit (49) and a data output directly connected to an input (49b) of said second logical unit, said second logical unit (49) having a selection input connected directly to an output of a synchronization module (51) for receiving a synchronization signal (SorR), said synchronization module (51) having an input (71a) for receiving said input clock signal (CLin), the synchronization signal controlling selection between a feedback mode and a reset mode, in which during the feedback mode the second logical unit (49) logically couples the data input of said clocked bi-stable unit (48) inversely to the data output, and in which during the reset mode the second logical unit (49) provides a reset value to the data input, and an output (50) coupled to the data output for providing an output clock signal (Clout2).