Patent ID: 7956686
Filing Date: 2011-06-07
Classification: H03F

Abstract:
1. A differential amplifier circuit, comprising: a first input stage including a transistor pair of a first conductivity type, said transistor pair receiving differential input signals; a first output stage connected to said first input stage; a second input stage including a transistor pair of a second conductivity type different from said first conductivity type, said transistor pair receiving said differential input signals; a second output stage connected to said second input stage; and an output terminal, wherein said second output stage is structured with a circuit topology symmetric to a circuit topology of said first output stage such that transistors of said first conductivity type in said first output stage are replaced with transistors of said second conductivity type in said second output stage, transistors of said second conductivity type in said first output stage are replaced with transistors of said first conductivity type in said second output stage, ground terminals in said first output stage are replaced with power supply terminals in said second output stage, and power supply terminals in said first output stage are replaced with ground terminals in said second output stage, outputs of said first and second output stages are commonly connected to said output terminal, said first input stage includes first and second NMOS transistors having commonly connected sources, said second input stage includes first and second PMOS transistors having commonly connected sources, one of said differential input signals is fed to the gates of said first NMOS transistor and said first PMOS transistor, the other of said differential input signals is fed to the gates of said second NMOS transistor and said second PMOS transistor, said first output stage includes: said third and fourth NMOS transistors have sources connected to ground and commonly-connected gates, said fifth NMOS transistor has a source connected to the drain of said third NMOS transistor and a drain connected to the gates of said third and fourth NMOS transistors and to a first node, said sixth NMOS transistor has a source connected to the drain of said fourth NMOS transistor and a drain connected to a second node, a first bias voltage is fed to the gates of said fifth and sixth NMOS transistors, said third PMOS transistor has a drain connected to said first node, and a source connected to the drain of said first NMOS transistor, said fourth PMOS transistor has a drain connected to said second node, and a source connected to the drain of said second NMOS transistor, a second bias voltage is fed to the gates of said third and fourth PMOS transistors, said fifth PMOS transistor has a drain connected to the source of said third PMOS transistor, and a source connected to a power supply terminal, said sixth PMOS transistor has a drain connected to the source of said fourth PMOS transistor, and a source connected to a power supply terminal, a third bias voltage is fed to the gates of said fifth and sixth PMOS transistors, said second output stage includes: said seventh and eighth PMOS transistors have sources connected to power supply terminals and commonly-connected gates, said ninth PMOS transistor has a source connected to the drain of said seventh NMOS transistor and a drain connected to the gates of said seventh and eighth PMOS transistors and to a third node, said tenth PMOS transistor has a source connected to the drain of said eighth PMOS transistor and a drain connected to a fourth node, said second bias voltage is fed to the gates of said ninth and tenth PMOS transistors, said seventh NMOS transistor has a drain connected to said third node, and a source connected to the drain of said first PMOS transistor, said eighth NMOS transistor has a drain connected to said fourth node, and a source connected to the drain of said second PMOS transistor, said first bias voltage is fed to the gates of said seventh and eighth NMOS transistors, said ninth NMOS transistor has a drain connected to the source of said seventh NMOS transistor, and a source connected to ground, said tenth NMOS transistor has a drain connected to the source of said eighth NMOS transistor, and a source connected to ground, a fourth bias voltage is fed to the gates of said ninth and tenth NMOS transistors, and said output terminal is connected to said second node of said first output stage and said fourth node of said second output stage.