Patent ID: 6934832
Filing Date: 2005-08-23
Classification: G06F

Abstract:
1. The computer, comprising: a multi-stage execution pipeline; an instruction decoder designed: the pipeline being designed to recognize an exception occurring in an instruction after an earlier side-effect of the instruction has been architecturally committed and before a later side of the instruction is architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler; and pipeline resumption circuitry effective after completion of the software exception handler to resume execution of the excepted program based on the information in the processor registers; the processor registers of the computer being designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory.