Patent ID: 7742598
Filing Date: 2010-06-22
Classification: H04L

Abstract:
1. A parallel processing shrinking key generator, comprising: a selection linear feedback shift register (LFSR) coupled to receive a clock signal for shifting a selection bit according to the clock signal; a source LFSR coupled to receive the clock signal for shifting a source bit according to the clock signal; a selection logic circuit coupled to outputs of the selection LFSR and the source LFSR for selecting, according to the selection bit outputted from the selection LFSR, one of (a) the source bit outputted from the source LFSR and (b) a predetermined input bit; an index counter coupled to receive the clock signal and to the output of the selection LFSR for assigning an index indicating where output bits of the selection logic circuit are to be stored to an output amount register at a next clocking of said clock signal; and the output amount register coupled to receive the clock signal and to the output of the selection logic circuit for shifting an output bit of the selection logic circuit according to the index; wherein the selection logic circuit consists of multiplexers; wherein the selection logic circuit includes four identical pushing logics and six identical through logics when each of the selection LFSR and the source LFSR is a 16 bit LFSR; wherein the selection logic circuit further comprises wherein the selection LFSR outputs N bits from s[0], s[1], . . . to s[N−1], where N is great than 1; the source LFSR outputs N bits from a[0], a[1], . . . to a[N−1] which correspond to s[0], s[1], . . . to s[N−1], respectively; and for each bit among s[0], s[1], . . . to s[N−1] which is 1, the selection logic circuit outputs the corresponding bit among a[0], a[1], . . . to a[N−1].