Patent ID: 7761671
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. A data displacement bypass system, comprising: a CPU (Central Processing Unit), for outputting a plurality of address characters, an OE (Output Enable) signal and a CS (Chip Select) signal and receiving a plurality of data characters, wherein the binary value of said CS signal from said CPU is one of a first high voltage and a first low voltage; a first memory, for receiving said plurality of data characters, said OE signal and said CS signal and outputting said plurality of data characters according to said plurality of data characters, said OE signal and said CS signal, wherein the binary value of every data character from said first memory is one of a second high voltage and a second low voltage; a plurality of address lines, wherein said plurality of address characters are transmitted via said plurality of address lines; an OE line, wherein said OE signal is transmitted via said OE line, and said plurality of data characters are outputted according to said OE signal; a CS line, wherein said CS signal is transmitted via said CS line, and said plurality of data characters from said first memory are outputted according to said CS signal; a plurality of data lines, wherein said plurality of data characters are transmitted via said plurality of data lines; and a data displacement unit, for receiving said plurality of address characters and said OE signal and outputting said CS signal and said plurality of data characters according to said plurality of address characters and said OE signal, wherein said data displacement unit comprises a signal amplifier electrically coupled with said plurality of data lines or said CS line, wherein the binary value of said CS signal outputted from said data displacement unit by said signal amplifier is one of a third high voltage and a third low voltage, wherein the binary value of every data character outputted from said data displacement unit by said signal amplifier is one of a fourth high voltage and a fourth low voltage, wherein the voltage of said CS line is equal to or bigger than said first voltage when said signal amplifier is electrically coupled with said CS line, and said CS signal from data displacement unit is outputted as said third high voltage by said signal amplifier, the voltage of said plurality of data lines is equal to or smaller than said first low voltage when said signal amplifier is electrically coupled with said plurality of data lines, and said plurality of data characters from data displacement unit are outputted as said fourth low voltage by said signal amplifier, or the voltage of said plurality of data lines is equal to or bigger than said first high voltage when said signal amplifier is electrically coupled with said plurality of data lines, and said plurality of data characters from data displacement unit are outputted as said fourth high voltage by said signal amplifier.