Patent ID: 6493264
Filing Date: 2002-12-10
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory including at least two cells each comprising:a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed on the semiconductor substrate with the intervention of a second insulating film at a predetermined distance laterally spaced from the floating gate; a control gate formed at least partially over at least a portion of the floating gate with the intervention of a third insulating film, the control gate also being provided at least partially over at least a portion of the split gate with no part of the control gate being located directly between the floating gate split gate; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in the channel direction, wherein the floating gate and the split gate of one cell are alternately arranged with the floating gate and the split gate of another adjacent cell along the channel direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another adjacent cell, so that the floating gate and the slit gate of the one cell are adjacent one another and the floating gate of the one cell is also adjacent to the split gate of the another adjacent cell.