Patent ID: 7969214
Filing Date: 2011-06-28
Classification: H03L

Abstract:
1. A delay locked loop (DLL) circuit, comprising: a phase detection unit configured to compare a phase of a reference clock signal with a phase of a feedback clock signal so as to generate a phase detection signal; an update control apparatus configured to generate a valid interval signal and generate an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal; and a shift register configured to update a delay value supplied to a delay line according to the update control signal when the valid interval signal is enabled, wherein the update control apparatus is configured to determine a logical value of the phase detection signal every cycle of the reference clock signal and enable the valid interval signal when one of the number of first logical values and the number of second logical values exceeds the other by a predetermined number so as to output the phase detection signal as the update control signal.