Patent ID: 6614699
Filing Date: 2003-09-02
Classification: G11C

Abstract:
A booster circuit comprising:a plurality of booster units which include a first-stage booster unit having an input terminal applied with one of a power supply potential and ground potential and whose output terminals are respectively connected to the input terminals of next stage booster units; and an output circuit section controlled by an output potential of a final stage booster unit of said booster units, for transferring an output potential of one of said booster units which lies in a stage preceding the final-stage booster unit, each of said booster units including first and second clock input terminals to which first and second clock signals of different phases are input and a reset signal input terminal to which a reset signal is input, transferring charges from the input terminal to the output terminal in response to the first and second clock signals and turning ON resetting transistors in response to the reset signal after termination of the charge transfer to reset gate nodes of transistors in which charges remain; wherein a potential of the reset signal for turning ON the resetting transistors is created based on one of positive and negative boosted potentials output from said output circuit section.