Patent ID: 6646928
Filing Date: 2003-11-11
Classification: G06F,G11C

Abstract:
A packet-based integrated circuit device comprising:at least one dynamic random access memory bank having associated row and column decoders for specifying memory locations in said at least one dynamic random access memory bank in response to externally supplied row and column addresses; at least one sense amplifier circuit coupled to said column decoder for reading data from said at least one dynamic random access memory bank; a non-gated row register coupled to said at least one sense amplifier circuit for retaining at least a portion of said data read out from said at least one dynamic random access memory bank; a multiplexer circuit coupling said row register to an external data bus for supplying said at least a portion of said read out data thereon; and a demultiplexer circuit coupling said external data bus to said at least one sense amplifier circuit for supplying data applied to said external data bus to said at least one dynamic random access memory bank.