Patent ID: 6141163
Filing Date: 2000-10-31
Classification: G11B,H03L

Abstract:
A phase-locked loop circuit comprising:a phase comparator for receiving reproduction data and a reproduction clock and comparing a phase of the reproduction data with a phase of the reproduction clock to output a phase comparison result as a first voltage signal;a first charge pump for receiving the first voltage signal output from said phase comparator and converting the first voltage signal into a first current signal to output the first current signal;a frequency comparator for receiving a reference clock and the reproduction clock and comparing a frequency of the reference clock with a frequency of the reproduction clock to output a frequency difference;a frequency difference comparator for comparing the frequency difference output from said frequency comparator with a predetermined value, and outputting a second voltage signal which has a first value when the frequency difference is larger than the predetermined value, and a second value when the frequency difference is not more than the predetermined value;a second charge pump for receiving the second voltage signal output from said frequency difference comparator, and converting the second voltage signal into a second current signal to output the second current signal;an adder for receiving the first current signal output from said first charge pump and the second current signal output from said second charge pump, and adding the first current signal and the second current signal to output a third current signal;a loop filter for receiving the third current signal output from said adder to output a low-frequency voltage signal; anda voltage-controlled oscillator for receiving the low-frequency voltage signal output from said loop filter to output the reproduction clock having a frequency corresponding to the low-frequency voltage signal.