Patent ID: 6166772
Filing Date: 2000-12-26
Classification: G09G,H04N

Abstract:
A computer system having a processor, a video signal processing device coupled to the processor, and a video display device coupled to the video signal processing device, the video signal processing device coupled to receive at least two sequences of interlaced video fields each containing a set of data representing a plurality of scan lines, the video signal processing device for generating a second sequence of video frames and for providing the second sequence to the video display device, the video signal processing device comprising:a first buffer and a next buffer, the first buffer coupled to receive data from a video frame input source when the first buffer does not contain valid data and from the next buffer when an output frame is provided by video display device, the next buffer coupled to receive data from a video frame input source when the first buffer contains data;a compensator, coupled to receive data from the first buffer, the compensator being configured to compensate the data in the first buffer and further being coupled to provide a compensated field;a graphics deinterlacer, coupled to receive the compensated field from the compensator and further coupled to receive data from the next buffer, the graphics deinterlacer being configured to deinterlace the data from the next buffer with the compensated field and to merge the data from the next buffer and the compensated field into a video frame of the second sequence; anda graphics output coupled to receive the video frame of the second sequence from the deinterlacer and further coupled to provide the video frame of the second sequence to the video display device.