Patent ID: 6661102
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A reduced shear stress packaged semiconductor chip, comprising:a semiconductor chip package base having a die attachment area; a die having at least one side and at least one edge, said die comprising a semiconductor material selected from a group consisting essentially of silicon (Si), germanium (Ge), and gallium arsenide (GaAs), and each said at least one side having a thickness and a width; and a controlled amount of die attach material disposed between said die and said semiconductor chip package base; at least one portion of said die attach material forming at least one meniscus on said at least one side of said die, said at least one meniscus forming at least one die attach fillet upon curing of said die attach material, said at least one die attach fillet having at least one controlled height, said at least one controlled height comprising a range of greater than approximately 33% to approximately 75% of said at least one die side thickness along an approximately central 50% of said die width at a location of at least 25% inboard from each said at least one edge of any given at least one die side, and said die having reduced shear stress.