Patent ID: 9136214
Filing Date: 2015-09-15
Classification: C23C,H01L,H05K,Y10T

Abstract:
1. A method for manufacturing a multilayer wiring board comprising a silicon core substrate and two or more wiring layers provided through an electrical insulating layer on the silicon core substrate, said method comprising the steps of: subjecting a silicon core material for the silicon core substrate to dry etching utilizing plasma from one side of the silicon core material to form pores having an opening diameter in the range of 10 to 100 μm to a predetermined depth; polishing the other side of the silicon core material to expose the pores and thus to form throughholes; forming an insulation layer and an electroconductive material diffusion barrier layer at least on the inner wall surface of the throughholes so that the electronconductive material diffusion barrier layer is covered with the insulation layer; filling an electroconductive material into the throughholes to bring the silicon core substrate to such a state that the front side and back side of the silicon core substrate have been electrically conducted to each other; and forming vias on the silicon core substrate so as to be connected to the electronconductive material filled into the throughholes and, at the same time, forming a first wiring layer through an electrical insulating layer, wherein the step of forming the insulation layer and the electroconductive material diffusion barrier layer, after the formation of the insulation layer and the electroconductive material diffusion barrier layer on the surface of the silicon core material including the inner wall surface of the throughholes so that the electroconductive material diffusion barrier layer is covered with the insulation layer, an electroconductive base layer is formed on at least a part of the insulation layer located on the inner wall surface of the throughholes, and, in the step of filling the electroconductive material into the throughholes, a desired resist film is formed on the silicon core material excluding the inside of the throughholes followed by electroplating to fill the electroconductive material into the throughholes.