Patent ID: 6369423
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A semiconductor device with a thin gate stack including a plurality of insulating layers and a contact hole formed through the gate stack, comprising:a substrate; a gate oxide film formed selectively on the substrate; a gate electrode formed on the gate oxide film; a gate cap layer formed as an etching stopper on the gate electrode, and not extending over sidewalls of the gate electrode, the gate cap layer including a plurality of insulating layers; a protection insulating film formed on the gate cap layer and the sidewalls of the gate electrode; and a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode, the diffusion layer being located at a bottom of the contact hole wherein an etching rate of one of the insulating layers in the gate cap layer is lower than an etching rate of the protection insulating film.