Patent ID: 9189302
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. A processor comprising: at least one processor core; hardware-specific monitor logic to monitor hardware-specific events; a software-accessible register that is to have a plurality of bits, the software-accessible register accessible to software, wherein each of the plurality of bits is to correspond at a given time to a different software event, wherein a first bit in the software-accessible register is to store an indication of an occurrence of a corresponding software event in the software and is to be written by the software when the corresponding software event has occurred in the software to indicate that the corresponding software event has occurred, and wherein a second bit in the software-accessible register is to store an indication of an occurrence of a corresponding combination of events including a corresponding software event in the software and a corresponding hardware-specific event to be monitored by the hardware-specific monitor logic; and an event counter including hardware, the event counter coupled with the software-accessible register and with the hardware-specific monitor logic, the event counter to count events associated with the second bit, wherein the event counter is to one of: (1) start to count after the second bit is set, and stop counting after the second bit is cleared; and (2) count a number of times the second bit is one of set to 1 and cleared to 0.