Patent ID: 6040995
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A method for operating a memory cell arrangement, comprising the steps of:using MOS transistors each having a dielectric triple layer with a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer as gate dielectric, as memory cells, the first silicon oxide layer and the second silicon oxide layer being respectively at least 3 nm thick;applying, for writing a first logical value into one of the memory cells, a first charge amount onto the gate dielectric by Fowler-Nordheim tunneling, said first charge amount being stored in the gate dielectric thereby effecting a first cutoff voltage value of the MOS transistor;applying for writing a second logical value into one of the memory cells, a second charge amount onto the gate dielectric by Fowler-Nordheim tunneling, said second charge amount being stored in the gate dielectric thereby effecting a second cutoff voltage value of the MOS transistor;applying, for readout of digital information from one of the memory cells, a read voltage to the gate electrode of the memory cell, said read voltage lying between the first cutoff voltage value and the second cutoff voltage value, the read voltage being evaluated as to whether a current flows through the MOS transistor or not.