Patent ID: 7019570
Filing Date: 2006-03-28
Classification: H03L

Abstract:
1. A phase-locked loop circuit having an input terminal for receiving a reference signal and an output terminal for outputting an output signal locked to said reference signal, and comprising: a compensation component comprising an oscillator for producing said output signal; a high-gain coarse feedback path feeding said compensation component, said high-gain coarse feedback path accepting as inputs a reference frequency of said reference signal and an output frequency of said output signal, and causing said compensation component to drive said output frequency to within a predetermined variance from said reference frequency, wherein said coarse feedback path comprises: a frequency detector having inputs connected to said input terminal and said output terminal, said frequency detector producing a coarse-adjust signal based on a difference between said output frequency and said reference frequency, and a high-gain signal modifier downstream of said frequency detector, said high-gain signal modifier having a first gain; and a low-gain fine feedback path feeding said compensation component, said low-gain fine feedback path accepting as inputs said reference frequency and said output frequency, and causing said compensation component to drive said output to a phase-frequency lock with said reference frequency after said coarse feedback path has caused said compensation component to drive said output frequency to within said predetermined variance from said reference frequency, wherein said fine feedback path comprises: a phase-frequency detector having inputs connected to said input terminal and said output terminal, said phase-frequency detector producing a fine-adjust signal based on said difference between said output frequency and said reference frequency, and a low-gain signal modifier downstream of said phase-frequency detector, said low-gain signal modifier having a second gain that is less than said first gain.