Patent ID: 6690206
Filing Date: 2004-02-10
Classification: H01L,H03K

Abstract:
A semiconductor integrated circuit device, having at least one selector, the selector in the integrated circuit comprising:first and second PMOS transistors; first and second NMOS transistors; first to fourth input terminals; and a first node; wherein a source-drain path of the first PMOS transistor is connected between the first input terminal and the first node; a source-drain path of the first NMOS transistor is connected between the first input terminal and the first node; a source-drain path of the second PMOS transistor is connected between the second input terminal and the first node; a source-drain path of the second NMOS transistor is connected between the second input terminal and the first node; a control electrode of the first PMOS transistor is controlled by a first signal applied to the third input terminal; a control electrode of the second NMOS transistor is controlled by the first signal applied to the third input terminal; a control electrode of the second PMOS transistor is controlled by a second signal applied to the fourth input terminal; a control electrode of the first NMOS transistor is controlled by the second signal applied to the fourth input terminal; the first signal and the second signal are complementary signals; a first electrode of the first PMOS transistor and a first electrode of the second PMOS transistor are arranged to share impurity regions so that they are connected to each other; and a first electrode of the first NMOS transistor and a first electrode of the second NMOS transistor are arranged to share impurity regions so that they are connected to each other; wherein common portions of a second electrode of the first PMOS transistor and the first electrodes of the first and second NMOS transistors are arranged in line in a direction intersecting a direction in which a power supply line extends; and common portions of a second electrode of the second NMOS transistor and the first electrodes of the first and second PMOS transistors are arranged in line in a direction intersecting a direction in which the power supply line extends.