Patent ID: 6518125
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method for forming a gate of a flash memory, the method comprising:providing a semiconductor substrate; forming a tunnel oxide layer on said semiconductor substrate; forming a first polysilicon layer on said tunnel oxide layer; forming a source/drain region in said semiconductor substrate; forming a first dielectric layer on said source/drain region; forming plurality photoresist layers on said first dielectric layer and said first polysilicon layer; etching first dielectric layer by said plurality photoresist layers as etched masks to form a contoured surface on said first dielectric layer; removing said plurality photoresist layers; and conforming a second polysilicon layer along said first dielectric layer and said first polysilicon layer, so as to form said gate of said flash memory, wherein said first polysilicon layer and said second polysilicon layer are electrically connected.