Patent ID: 8681166
Filing Date: 2014-03-25
Classification: G06F,G06T

Abstract:
1. A method, comprising: determining a buffer sequence associated with a signal flow for an electronic circuit, wherein the signal flow includes a plurality of algorithm elements interconnected with connections and processed according to a connection sequence, and wherein the buffer sequence indicates an order of using a plurality of on-chip memory buffers to process the plurality of algorithm elements according to the connection sequence; identifying an algorithm element from the plurality of algorithm element that uses an off-chip memory and one of the on-chip memory buffers; generating a first dummy algorithm element by a first Direct Memory Access (DMA) request and a second dummy algorithm element by a second DMA request, wherein the first dummy algorithm element is different from the second dummy algorithm element, wherein each dummy algorithm element includes functions for writing to and reading from memory buffers; and modifying the buffer sequence such that the first dummy algorithm element writes to the on-chip memory buffer from the off-chip memory before the algorithm element is processed, and the second dummy algorithm element writes to the off-chip memory from the on-chip memory buffer after the algorithm element is processed.