Patent ID: 7983072
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A semiconductor device, comprising: a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transfer transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to a well region of the first transfer transistor and a well region of the second transfer transistor, the voltage being one of more than a GND voltage and less than a GND voltage wherein the voltage supplying circuit is configured to supply a voltage which is less than a GND voltage to the well region of the first transfer transistor and the well region of the second transfer transistor when data is started to be written to the SRAM cell.