Patent ID: 6825082
Filing Date: 2004-11-30
Classification: H01L

Abstract:
A method of forming a ferroelectric memory device, comprising:forming a transistor on a semiconductor substrate, the transistor comprising a source region, a drain region, and a gate electrode; forming a first interlayer insulating layer over the transistor and the substrate; forming first contact holes in the first interlayer insulating layer to expose the source and drain regions; forming a conductive layer on the first interlayer insulating layer and within the first contact holes; patterning the conductive layer to form a buried contact structure and a bit line, wherein the buried contact structure is electrically connected to the source or drain region through one of the first contact holes, and wherein the bit line is electrically connected to the other source or drain region through one of the first contact holes; forming a blocking layer on the buried contact structure, the bit line, and the first interlayer insulating layer to prevent oxygen diffusion; forming a second interlayer insulating layer on the blocking layer; form a second contact hole extending through the second interlayer insulating layer and the blocking layer to expose a top surface of the buried contact structure; and forming a ferroelectric capacitor on the second interlayer insulating layer, wherein the ferroelectric capacitor is electrically connected to the buried contact structure through the second contact hole.