Patent ID: 7373216
Filing Date: 2008-05-13
Classification: G05B,Y02P

Abstract:
1. A method of verifying a Site-Dependent (S-D) wafer comprising: receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing subsystems, wherein the one or more S-D processing elements are coupled to one or more S-D transfer subsystems, each wafer having wafer data associated therewith, wherein the wafer data includes historical and/or real-time data; creating a first set of unverified S-D wafers by performing a first S-D creation procedure using the one or more S-D processing elements, wherein one or more unverified evaluation features are created at a first number of evaluation sites on each of the unverified S-D wafers; establishing S-D wafer state data for each unverified S-D wafer, wherein the S-D wafer state data comprises a number of required creation sites and a number of required evaluation sites for each unverified S-D wafer; establishing a first set of evaluation wafers comprising a first number of the unverified S-D wafers, the first set of evaluation wafers being evaluated using a first S-D evaluation procedure; establishing first operational states for a plurality of S-D evaluation elements in one or more subsystems coupled to the one or more S-D transfer subsystems; determining a first number of available evaluation elements using the first operational states for one or more of the S-D evaluation elements; establishing a first S-D transfer sequence using the wafer data, the S-D wafer state data, the first number of S-D evaluation wafers, or the first number of available evaluation elements, or any combination thereof; transferring the first set of S-D evaluation wafers to the first number of available evaluation elements in one or more evaluation subsystems using the first S-D transfer sequence when the number of S-D evaluation wafers is less than or equal to the first number of available evaluation elements, and applying a first corrective action when the number of S-D evaluation wafers is greater than the first number of available evaluation elements.