Patent ID: 6145087
Filing Date: 2000-11-07
Classification: G01R

Abstract:
A semiconductor integrated device comprising:an internal oscillation circuit that generates an internal clock through oscillation;a selector that selects either a test clock provided from the outside or said internal clock based upon a select signal;a core logic unit that takes in input data input through an input terminal in synchronization with said test clock or said internal clock provided by said selector, performs processing on said input data and outputs output data resulting from said processing to an output terminal;an input data register connected between said input terminal and said core logic unit, that stores therein test data provided via said input terminal as said input data in synchronization with said test clock output by said selector during a first period elapsing after a test mode is set; andan output data register connected between said core logic unit and said output terminal, that stores therein said output data output by said core logic unit in synchronization with said internal clock output by said selector during a second period following said first period and provides said output data which have been stored to said output terminal in synchronization with said test clock output by said selector during a third period starting after said second period is completed.