Patent ID: 7979682
Filing Date: 2011-07-12
Classification: G06F

Abstract:
1. A computer implemented method in a data processing system to prevent livelock, the computer implemented method comprising: determining, by a processor, whether a prediction mechanism override bit for overriding a prediction mechanism is set in an instruction; responsive to the prediction mechanism override bit being set in the instruction, overriding the prediction mechanism so that the prediction mechanism does not predict a column address in a data cache memory for a datum to be accessed for the instruction; executing, by the processor, the instruction using a correct column address that is appended to the instruction to access the datum in the data cache memory, wherein the correct column address and the prediction mechanism override bit are appended to the instruction in response to determining that an outcome of an event was mispredicted using a predicted column address during a previous execution of the instruction; and rejecting, by the processor, the instruction by sending the instruction with an appended correct column address and an appended prediction mechanism override bit back to an instruction decode and dispatch unit for re-execution at a later time in response to determining that the outcome of the event was mispredicted using the predicted column address.