Patent ID: 6175146
Filing Date: 2001-01-16
Classification: H01L,Y10S

Abstract:
Memory integrated circuitry comprising:a memory array area and a peripheral circuitry area operably associated with one another, the memory array area comprising a buried contact interconnecting plug formed through an insulating dielectric layer, the plug comprising an inner conductive polysilicon material portion disposed over a conductive substrate node location, the inner conductive polysilicon portion being in conductive electrical connection with the conductive substrate node location, and a silicide material portion formed atop the inner conductive portion; andthe peripheral circuitry area comprising a peripheral line extension electrically interconnecting substrate active area with a conductive peripheral line, the peripheral line extension being at least in part formed from the polysilicon material and the silicide material of the buried contact interconnecting plug, the peripheral line extension being longer than it is wide.