Patent ID: 8347150
Filing Date: 2013-01-01
Classification: G11C

Abstract:
1. A data processing system having a semiconductor memory with a memory matrix which is addressed by an addressing circuit which comprises addressing lines, wherein the memory comprises additional bit lines for recovering the address/subaddress, and the data processing system comprises a device for recognizing and/or correcting addressing errors with means for comparing a read-back address/subaddress and an applied address/subaddress, wherein the data processing system comprises a microprocessor, memory access means, address read-back means and comparison means which the microprocessor can use to read back and check the actual memory access address from the semiconductor memory, wherein the semiconductor memory has an addressing circuit having at least one feedback path for checking the addressing circuit, wherein the feedback path is routed from the microprocessor via a first bus to a bus matrix, a second bus to a peripheral bridge, via a peripheral bus to a memory controller and via address echo lines to the semiconductor memory, which is provided in addition to a first path routed via a third bus between the bus matrix and the memory controller, wherein the actually accessed address is returned to the memory controller by way of the address echo lines, and wherein the address echo lines extend an interface which is present between the memory controller and the memory.