Patent ID: 8228733
Filing Date: 2012-07-24
Classification: G11C,H01L

Abstract:
1. A three-dimensionally stacked nonvolatile semiconductor memory comprising: a memory cell array provided in a semiconductor substrate; conductive layers stacked above the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another; a bit line which is disposed above the conductive layers in such a manner as to be insulated from the conductive layers; a semiconductor column which extends through the conductive layers and which has an upper end connected to the bit line and a lower end connected to the semiconductor substrate; word lines for which the conductive layers except for the uppermost and lowermost conductive layers are used; memory cells provided at intersections of word lines and the semiconductor column, respectively; a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the word lines; and a potential control circuit which controls the potentials supplied to the word lines and which reads the information retained in the register circuit in accordance with a position of a word line in a direction perpendicular to the surface of the semiconductor substrate and which supplies a potential suitable for the word line corresponding to an input address signal.