Patent ID: 6826652
Filing Date: 2004-11-30
Classification: G06F

Abstract:
A processing device comprising:a processing core having circuitry for generating addresses to access a main memory; an n-way cache comprising: n data memories each having a plurality of entries for storing information from said main memory; one or more tag memories for storing address information identifying a main memory address associated with each of said entries in a corresponding data memory; one or more tag registers for storing address information defining a contiguous block of main memory addresses, each tag register associated with a corresponding data memory; and control circuitry for defining a cache association between each data memory and either a tag memory or a tag register and selectively accessing each data memories in response to an address from said processing core based on said cache association and wherein said control circuitry can define an association between m tag memories and m data memories to form an m-way set associative cache and n-m caches for storing information mapped to respective blocks of main memory addresses.