Patent ID: 6671219
Filing Date: 2003-12-30
Classification: G06F,G11C

Abstract:
A storage device that comprises a memory cell array comprising a plurality of memory cells; word lines used to select memory cells from said plurality of memory cells in response to an address signal; and bit lines used to read information stored in the selected memory cells, wherein said storage device is connected to an address bus and a data bus, and wherein a bit array of data stored in the memory array is different from a bit array in the data bus;wherein information pieces transmitted via adjacent bit signal lines on the data bus are stored in the memory cells a predetermined number of bits apart; and wherein, when a basic read unit is n bits, information pieces, whose logical bit positions are 0*8+k, 1*8+k, 2*8+k, 3*8+k, . . . , m*8+k (where k and m are natural numbers, 0&lE;k&lE;7 and 0&lE;m&lE;n/8âˆ’1), are stored in the memory cells close to one another in the memory cell array.