Patent ID: 6567322
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of normal banks formed by dividing a memory cell array into a plurality of sections; a first redundant cell array provided as one spare bank so as to be substituted for a defect memory cell of the memory cell array; a plurality of second redundant cell arrays provided to correspond to the plurality of normal banks; normal decoders provided to correspond to the normal banks and arranged to select the row and column of the memory cell array in accordance with an input address; a first spare decoder for selectively operating the first redundant cell array; a plurality of second spare decoders for selectively and correspondingly operating the plurality of second redundant cell arrays; a first substitution-control signal line for supplying a first substitution-control signal for controlling the operation of the first spare decoder; a second substitution-control signal line for supplying a second substitution-control signal for controlling the operation of the plurality of second spare decoders; a plurality of first memory circuits in which information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell arrays corresponds to each of the plurality of first memory circuits are previously stored to selectively output the first substitution-control signal or the second substitution-control signal in accordance with a detection result of the correspondence between the stored address of the defect memory cell and the input address and information of the correspondence with the first redundant cell array or the second redundant cell arrays; and a control circuit for controlling the normal decoder to be deactivated when either of the first substitution-control signal line or the second substitution-control signal line is in an active state.