Patent ID: 8994431
Filing Date: 2015-03-31
Classification: H03K

Abstract:
1. A flip-flop circuit, comprising: an input stage circuit, arranged for receiving a first signal from a first node, and selectively outputting a second signal corresponding to the first signal at a second node according to at least one control signal; a middle stage circuit, coupled to the input stage circuit, arranged for receiving the second signal, and selectively outputting a third signal corresponding to the second signal at a third node according to the at least one control signal; an output stage circuit, coupled to the middle stage circuit, arranged for receiving the third signal to output an output signal; and a set/reset circuit, coupled to the second node and the third node, arranged for receiving a set signal and a reset signal, and selectively determining a voltage level of the third signal at the third node; wherein the flip-flop circuit selectively operates in a first mode or a second mode according to the at least one control signal, when the flip-flop circuit operates in the first mode, the input stage circuit disconnects the first node from the second node, and the set/reset circuit determines the voltage level of the third signal according to the set signal and the reset signal; when the flip-flop circuit operates in the second mode , the set/reset circuit is disabled, and the input stage circuit generates the second signal according to the first signal, and the middle stage circuit generates the third signal according to the second signal; and the input stage circuit comprises: the flip-flop circuit further comprises: a control circuit, arranged for receiving a start signal and a clock signal, and accordingly generating the at least one control signal, wherein the start signal is used to indicate whether the flip-flop circuit currently operates in the first mode or the second mode.