Patent ID: 6810508
Filing Date: 2004-10-26
Classification: G06F

Abstract:
A computer system for constructing HDL test benches based upon HDL descriptions of electrical circuits, comprising:means for generating and modifying said HDL descriptions; a computer including a monitor and memory storage means, said memory storage means containing instructions for displaying, on said monitor, a spreadsheet comprised of timing waveforms superimposed on an array of cells containing time-varying signal data patterns, wherein said waveforms and said data patterns correspond to said HDL descriptions and are simultaneously displayed on said monitor; means for modifying said waveforms and said signal data patterns; means for automatically translating said waveforms into a complete HDL test bench file, said test bench file being fully compatible with industry-standard HDL simulators; and wherein said spreadsheet comprises rows and columns, said rows representing signal names and said columns representing cell values of said time varying signal data patterns.