Patent ID: 7651942
Filing Date: 2010-01-26
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a wafer that includes a conductive region covered by a cap layer; depositing a dielectric layer over the conductive region, said dielectric layer extending from said cap layer at a lower surface to an upper surface and comprising the same material therethrough; etching a recess in the dielectric layer extending from said upper surface to said cap layer, the recess overlying the conductive region; depositing a sacrificial liner conformally over the dielectric layer subsequent to etching said recess, the conformal sacrificial liner being formed on the cap layer at the bottom of the recess and also formed on and extending from said upper surface to said lower surface along the sidewall of the recess, the sacrificial liner also being formed over said upper surface of the dielectric layer said liner having a constant thickness of between about 3 nm and 10 nm and being formed of a material removable by an aqueous wash that will not damage the conductive region; depositing an organic material over said sacrificial liner, said organic material filling said recess having said conformed sacrificial liner and forming a layer of said organic material over said sacrificial liner covering the upper surface of the said dielectric layer; planarizing said organic material, such that an organic planarization layer of said organic material remains over said sacrificial liner covering the upper surface of the dielectric layer including said recess; forming a trench structure within said organic planarization layer and transferring said trench structure from said planarization layer to said dielectric layer; and forming a dual damascene structure within the dielectric layer, the dual damascene structure including the recess, and the trench structure transferred from said organic planarization layer, wherein forming the dual damascene structure further comprises removing a portion of the planarization layer in said recess and a portion of the cap layer with a dry etch to expose the conductive region and depositing chemically altered portions of said planarized layers as residue onto said sacrificial liner on one of said sidewalls of the recess and said upper surface of the dielectric layer, the residue having a different chemical composition than said planarized layers, and then removing the sacrificial liner and any remaining chemically altered portions of said planarization layer that have been deposited as a residue onto said sacrificial liner on said sidewalls of the recess and said upper surface with said aqueous wash that will not damage said conductive region.