Patent ID: 7561475
Filing Date: 2009-07-14
Classification: G11C

Abstract:
1. An apparatus for controlling a flash memory device, the apparatus comprising: a signal generator for generating a clock signal for an operation; a first buffer disposed along a first clock signal path and electrically connected between the signal generator and the flash memory device, wherein the first buffer receives the clock signal and outputs a clock enable signal along the first clock signal path to a first terminal of the flash memory device based on the clock signal; a latch circuit; a second buffer disposed along a data path and electrically connected between a second terminal of the flash memory device and a data input of the latch circuit, wherein the second buffer receives data along the data path from the flash memory device in synchronization with the clock enable signal; a third buffer disposed along a second clock signal path and electrically connected at an input end to an output of the first buffer and the first terminal of the flash memory device and at an output end to a latching input of the latch circuit, wherein the third buffer receives the clock enable signal from the first buffer and outputs a latch signal along the second clock signal path to the latching input of the latch circuit based on the output of the first buffer, and wherein the latch circuit latches an output of the second buffer in synchronization with the latch signal output from the third buffer.