Patent ID: 8923058
Filing Date: 2014-12-30
Classification: G11C

Abstract:
1. A memory device comprising a plurality of cell strings, wherein the plurality of cell strings are configured to share a bit line and word lines, wherein at least one of the cell strings comprises a plurality of memory cells connected in series to each other and a string selection device configured to control connections between the memory cells and the bit line, and wherein the string selection device comprises: wherein at least one of the first and second string selection elements comprises a plurality of switching elements connected in series to each other, wherein the memory cells comprise a data storing layer provided between the word lines and a semiconductor layer, and wherein the plurality of switching elements respectively comprise gate electrodes, respectively on the semiconductor layer and gate insulating layers, respectively, between the gate electrodes and the semiconductor layer, and at least one of data storing layer and the gate insulating, layer comprises a tunnel insulating layer, a charge storing layer, and a blocking insulation layer sequentially stacked on the semiconductor layer.