Patent ID: 9141829
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. A processor comprising: an execution unit configured to output a first virtual address; a mode register configured to indicate whether the processor is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited; and a memory access control unit configured to output a first physical address corresponding to the first virtual address by referring to either a first translation look aside buffer for the first mode or a second translation look aside buffer for the second mode in accordance with a value of the mode register, wherein, by executing a first instruction code stored in the secure address space in the first mode, a second instruction code is checked in the first mode before the second instruction code is executed in the second mode, and wherein, in the second mode, the memory access control unit prohibits an access to a physical address within the secure address space in accordance with the second translation look aside buffer.