Patent ID: 6297665
Filing Date: 2001-10-02
Classification: G11C,H03K

Abstract:
A configurable logic block (CLB) comprising:a plurality of function generators, each having a read address port and a write address port and an output data terminal;a first set of multiplexers (F5.sub.0, F5.sub.1, FX.sub.0) configured to route data values from the output data terminals of a first set of the function generators (F.sub.0, G.sub.0, F.sub.1, G.sub.1);a second set of multiplexers (F5.sub.2, F5.sub.3, FX.sub.2) configured to route data values from the output data terminals of a second set of the function generators (F.sub.2, G.sub.2, F.sub.3, G.sub.3); anda first set of dedicated address lines (AA[4:1]) coupled to the read and write address ports of a third set of the function generators and to the write address ports of a fourth set of the function generators, wherein the third set of function generators is a subset of the first set of function generators, and the fourth set of function generators is a subset of the second set of function generators.