Patent ID: 7430695
Filing Date: 2008-09-30
Classification: G01R,G11C

Abstract:
1. A register file, comprising: a memory array where a predetermined number of first storage devices, each first storage device including a data input terminal, a data output terminal, a shift input terminal and a shift output terminal arranged on an address basis to constitute a plurality of registers, wherein a scan connection configuration circuit where second storage devices each second storage device comprising a shift input terminal and a shift output terminal, as many as the first storage devices are arranged in a register in the memory array following a last register in the memory array, wherein a file writing unit for designating an arbitrary address of the memory array and writing data in a register corresponding to the arbitrary address; a file reading unit for designating an arbitrary address of the memory array and reading data from a register corresponding to the arbitrary address; a scan control circuit where a first shift clock is input in an order starting from the last register in the scan connection configuration circuit and the memory array to the head register, wherein, until all the data held in the memory array when scan started, is output from the shift register output terminal,