Patent ID: 6151694
Filing Date: 2000-11-21
Classification: G01R

Abstract:
A method of evaluating fault coverage of a test pattern, comprising the steps of:preparing a fault list in which faults are assumed by sampling in a logic circuit constituting all or a part of a first circuit;using the fault list as a fault list used for the logic circuit included in a second circuit including the logic circuit;performing fault simulation for the first circuit by inputting a predetermined test pattern into the first circuit;preparing a first fault information list by adding to the fault list information on detection of the assumed faults, which is obtained by the fault simulation for the first circuit;performing fault simulation for the second circuit by inputting the predetermined test pattern which is modified to be applicable to the logic circuit included in the second circuit;preparing a second fault information list by adding to the fault list information on detection of the assumed faults which is obtained by the fault simulation for the second circuit; andcomparing the first and second fault information lists.