Patent ID: 7330392
Filing Date: 2008-02-12
Classification: G09G,G11C,H01L

Abstract:
1. A dual port semiconductor memory device comprising: a memory cell array including a plurality of memory cells, each cell including: a plurality of wordlines and a plurality of scan address lines; a plurality of pairs of bitlines, comprised of bitlines and complementary bitlines, and a plurality of scan data-out lines; a read/write row decoder unit to select one from among the plurality of wordlines; a scan row decoder unit to select one from among the plurality of scan address lines; a column decoder unit to select one from among the plurality of pairs of bitlines; a scan latch circuit unit to latch data output to the plurality of scan data-out lines and to thus generate scan output signals; a precharge circuit unit to precharge the plurality of pairs of bitlines; a predischarge circuit unit to predischarge the plurality of scan data-out lines; a data input/output gate unit to input and output data to the plurality of pairs of bitlines; a sense amplifier unit to amplify a voltage difference between each of the plurality of bitlines; and a data input/output circuit unit to generate output data using data output from the sense amplifier unit and to output data to the data input/output gate unit.