Patent ID: 6504769
Filing Date: 2003-01-07
Classification: G11C,H01L

Abstract:
A semiconductor memory device having a plurality of cell blocks, comprising:a fuse box group, coupled to the cell blocks, for generating a repair signal in response to a row address signal, the fuse box group including upper fuse box pairs and lower fuse box pairs; a repair signal summation means for generating a repair summation signal for controlling a repair operation in response to the repair signal, wherein the repair signal summation means includes: a plurality of first NAND gates for NANDing outputs of the upper fuse box pairs to provide a first repair summation signal; a plurality of second,NAND gates for NANDing outputs of the lower fuse box pairs to provide a second repair summation signal; a first NOR gate for NORing outputs of the first NAND gates; a second NOR gate for NORing outputs of the second NAND gates; a third NAND gate for NANDing an output of the first NOR gate and an output of the second NOR gate; a first buffer unit for buffering an output of the first NOR gate to generate a lower spare row enable signal; a second buffer unit for buffering an output of the second NOR gate to generate an upper spare row enable signal; and an inverter for inverting an output of the third NAND gate to generate a normal row enable signal; a block selection signal generation means for generating a block selection signal for selecting a cell block to be repaired in response to the first and second repair summation signals and a block selection address signal; and a repair row decoding means for driving a redundant word line in response to the repair signal and a block selection signal.