Patent ID: 6167418
Filing Date: 2000-12-26
Classification: G06F

Abstract:
A byte-switching arithmetic unit comprising at least three stages, each of which has a plurality of two-input selectors operable in a predetermined minimum bit width unit, said byte-switching arithmetic unit having two inputs of a predetermined input bit width,wherein a first stage has a first number of first stage two-input selectors where said first number corresponds to a quotient of a division to said predetermined input bit width of the two inputs by said predetermined minimum bit width unit,wherein a second stage has a second number of second stage two-input selectors where said second number corresponds to a half of said first number so that said second stage two-input selectors receive a half of outputs from said first stage two-input selectors, andwherein a third stage has a third number of third stage two-input selectors where said third number also corresponds to said half of said first number so that said third stage two-input selectors receive both a half of outputs from said second stage two-input selectors and a half of outputs from a remaining half group of said first stage two-input selectors.