Patent ID: 7216219
Filing Date: 2007-05-08
Classification: G06F

Abstract:
1. A method for avoiding write-after-read (WAR) hazards while speculatively executing instructions on a processor, comprising: issuing instructions for execution in program order during a normal execution mode; upon encountering an unresolved data dependency during execution of an instruction, generating a checkpoint, deferring the instruction and executing subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, wherein other non-deferred instructions are executed in program order; wherein deferring the instruction involves storing the instruction along with any resolved source operands for the instruction into a deferred buffer; and if an unresolved data dependency is resolved during the execute-ahead mode, executing deferred instructions in a deferred mode, wherein deferred instructions that are able to be executed are executed in program order, and wherein other deferred instructions that still cannot be executed because of unresolved data dependencies are deferred again; wherein executing a deferred instruction involves using resolved source operands from the deferred buffer, if such resolved source operands were previously stored along with the instruction in the deferred buffer, whereby instructions following the deferred instruction that overwrite the resolved source operands cannot create a WAR hazard.