Patent ID: 6249526
Filing Date: 2001-06-19
Classification: H04J,H04L,H04N,H04Q

Abstract:
A time division multiple access (TDMA) slot allocation unit in a system having a host processor, comprising:a slot counter to provide an address representative of a time slot;a slot descriptor table including a first port and a second port, said slot descriptor table to contain one or more slot descriptors each of which describes an action that may be performed within said time slot, said slot descriptor table to receive said address on an address bus of said first port and to provide said slot descriptor corresponding to said address on a data bus of said first port;a device to receive messages for processing, said device to forward messages to the host processor, and to access the slot descriptor table via the second port for reading and/or writing slot descriptors responsive to receiving a time-critical message; anda slot descriptor decoder coupled to the data bus of the first port of the slot descriptor table, said slot descriptor decoder to decode said slot descriptor and to provide one or more signals.