Patent ID: 8981472
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate including a first well of a first conductivity type and a second well of a second conductivity type opposite to said first conductivity type; a channel region formed in said second well and having said second conductivity type, said channel region having a first end and a second end, said second end coinciding with an end surface of said second well facing said first well; a source extension region having said first conductivity type formed in said second well adjacent to said first end of said channel region; a buried insulation film region formed in said first well with a separation from said second well with a bottom edge located at a depth of 400 nm, shallower than a bottom edge of said first well; an offset region formed in said semiconductor substrate between said second well and said buried insulation film region; a drain extension region having said first conductivity type and formed in said first well at a side opposite to said offset region with regard to said buried insulation film; and a gate structure formed above said channel region, said offset region and said buried insulation film region, said gate structure comprising: a gate insulation film formed above said channel region, said offset region and said buried insulation film region; and a gate electrode on said gate insulation film, there being formed a region containing an impurity element of said first conductivity type at least in a part of said offset region along a surface of said semiconductor substrate with a concentration higher than in said first well, wherein said region is formed such that said concentration of said impurity element of said first conductivity type does not exceed a concentration level of about 2.5×10