Patent ID: 9093297
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate comprising first, second, and third active regions defined by a device isolation layer pattern, each of the first, second, and third active regions comprising an isolated shape in a first direction comprising a longitudinal direction, the first and third active regions being arranged in parallel in the first direction, and the first and second active regions being spaced apart and immediately adjacent each other in the first direction; first and second trenches in the substrate; a first buried gate structure in the first trench in the first active region; a second buried gate structure in the second trench between upper sidewalls of the first and second active regions, respectively, the second buried gate structure comprising a line shape extending in a second direction and a second width that is wider in the first direction than a first width of the device isolation layer pattern between the first and second active regions; and first and second impurity regions at surface portions of the substrate in the first active region at opposing sides of the first buried gate structure.