Patent ID: 6407460
Filing Date: 2002-06-18
Classification: H01L,H05K

Abstract:
A multilayer circuit board comprising:a base board, having a mounting surface for mounting thereon at least one of a semiconductor chip or an electronic element, having lattice-arranged connection terminals; connection terminal pads arranged on the mounting surface to form a plane lattice corresponding to the lattice arrangement of the connection terminals and having lattice sites each occupied by one of the connection terminal pads; lead wiring lines disposed on the mounting surface and having one end connected to the connection terminal pads and the other end extending outward from the plane lattice, wherein said plane lattice has a peripheral zone including periodic vacant lattice areas formed by vacant lattice sites occupied by no connection terminal pads; and wherein the vacant lattice areas have an open outer side and a closed inner side defined by the connection terminal pads in a number of r defined by: â€ƒr=b(d+s)/(w+s); d>s and d>w; where b is a number of vacant lattice sites occupied by no connection terminal pads on the open outer side, d is a diameter of the pads, w is a width of the lead wiring lines and s is a distance between neighboring pads and is also a distance between neighboring lead wiring lines, said r connection terminal pads each having a lead wiring line having one end connected thereto and the other end extending outward from the plane lattice.