Patent ID: 6177320
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for forming a self aligned contact in a semiconductor device having a semiconductor substrate, a device isolation layer formed on said semiconductor substrate to define active and inactive regions, and a transistor formed on said active and inactive regions, said transistor comprising a gate electrode, a gate mask thereon, and a sidewall gate spacer, said method comprising:forming an etch stopping layer over said semiconductor substrate and said transistor;forming an interlayer dielectric layer over said etch stopping layer, said interlayer dielectric layer having a planar top surface;forming a mask pattern over said interlayer dielectric layer, said mask pattern having a T-shaped opening exposing said active region and a portion of said inactive region;sequentially etching said interlayer dielectric layer and etch stopping layer using said mask pattern, thereby forming a self aligned contact opening exposing a top surface of said semiconductor substrate;removing said mask pattern;forming a conductive layer in said self aligned contact opening and over said interlayer dielectric layer; andplanarizing said conductive layer and interlayer dielectric layer to reveal a top surface of said gate mask, thereby forming at least two contact pads.