Patent ID: 6469935
Filing Date: 2002-10-22
Classification: G11C,H01L

Abstract:
A nonvolatile memory array, comprising:a plurality of memory cells two dimensionally disposed in a first direction and in a second direction, a plurality of first connection regions, a plurality of second connection regions, a plurality of conductive bit lines extending in said first direction, a plurality of conductive word lines extending in said second direction, a plurality of conductive control lines extending in said second direction, each of said plurality of first connection regions connecting together in said second direction a first cluster of cells where said first cluster further comprises a first cell and a second cell that are adjacent in said first direction with a third cell and a fourth cell that are adjacent in said second direction to said first and second cells, each of said plurality of second connection regions connecting together in said second direction a second cluster of cells where said second cluster further comprises a cell of said first cluster of cells, a fifth cell adjacent in said first direction to said cell of said first cluster of cells, and a sixth cell and a seventh cell that are adjacent in said second direction to said cell of said first cluster of cells and said fifth cell, a first portion of said plurality of bit lines connecting together said plurality of first connection regions in said first direction, a second portion of said plurality of bit lines connecting together said plurality of second connection regions in said first direction.