Patent ID: 6914453
Filing Date: 2005-07-05
Classification: H03K

Abstract:
1. A method for implementing a logic circuit with integrated logic and latch design, the method comprising the steps of: providing a clock input to the logic circuit; providing one or more static signal inputs to the logic circuit; generating one or more dynamic signal inputs by dynamically gating the one or more static signal inputs with the clock signal, wherein the step of generating is at least partially performed by a first AND logic circuit within the logic circuit that is at least configured to receive the clock signal and a static signal input; applying the one or more dynamic signal inputs to the logic circuit; generating one or more dynamic signal outputs of the logic circuit; precharging the one or more dynamic signal outputs based on the clock signal; evaluating the one or more dynamic signal outputs when the one or more dynamic signal outputs are not being precharged; holding the one or more dynamic signal outputs when the one or more dynamic signal outputs are neither being precharged nor being evaluated; and converting the one or more dynamic signal outputs into one or more static signal outputs.