Patent ID: 6043107
Filing Date: 2000-03-28
Classification: G11C

Abstract:
A method for producing an integrated circuit assembly comprising:fabricating a memory array on a substrate of a memory chip having a minor axis and a major axis with the memory array extending parallel to the major axis of the memory chip;disposing a plurality of address chip bond pads in a chip bond pad region between first and second sides of the memory chip with the plurality of address chip bond pads arranged in a first row of chip bond pads extending along the major axis of the memory chip;disposing a plurality of data chip bond pads in the chip bond pad region with the plurality of data chip bond pads arranged in a second row of chip bond pads extending parallel to the first row of chip bond pads;providing an elongated package having a major axis and a minor axis, a first plurality of address pins and a first plurality of data pins with the pluralities of pins extending parallel to the major axis of the package;mounting the memory chip in the elongated package with the major axis of the memory chip oriented along the minor axis of the package;connecting the plurality of address chip bond pads to the plurality of address pins; andconnecting the plurality of data chip bond pads to the plurality of data pins.