Patent ID: 8874993
Filing Date: 2014-10-28
Classification: G06F,G11C

Abstract:
1. A non-volatile solid state memory device comprising: a memory unit having (i) stored data which is readable using a read operation; and (ii) an error-correcting code for correcting a potential error in said data; a controller with a logic for programming said memory unit according to a monitored occurrence of said error during said read operation, by monitoring end of life blocks stored in the memory unit; a first counter coupled to the controller and associated with a first block in the memory unit, the first counter being configured to count the accumulated number of errors since a second counter was last incremented, wherein the first counter is reset at the being nine of each of a plurality of write-erase cycles of the memory unit; and the second counter coupled to the first counter and configured to count the number of times a threshold is exceeded within the write-erase cycles by counting the number of times the first counter exceeds the threshold, wherein a predetermined count by the second counter indicates that an end of life of the first block has been reached.