Patent ID: 8728945
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps: forming a photoresist pattern over an underlying layer with a minimum size space or hole, wherein said underlying layer comprises gate material which has been previously etched in a gate length reduction etch to form transistor gates, such that gate tips of two of said transistor gates are connected after said gate length reduction etch is completed, and wherein said photoresist pattern exposes a hole over remaining gate material between said two transistor gates; depositing a thin film onto said photoresist pattern using an atomic layer deposition (ALD) process; etching said thin film to form sidewalls on said photoresist pattern completely around a perimeter of said minimum size space or hole; and etching said underlying layer while said photoresist pattern is in place, forming a sublithographic space, so that said step of etching said underlying layer separates said two transistor gates.