Patent ID: 7915157
Filing Date: 2011-03-29
Classification: H01L,Y10T

Abstract:
1. A method for fabricating a chip, comprising: providing a wafer comprising a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a conductive pad over said silicon substrate, a passivation layer over said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a contact point of said conductive pad, and said contact point is at a bottom of said first opening, and a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said contact point, wherein said first polymer layer has a thickness between 1 and 100 micrometers; and forming a metallization structure over said wafer, on a top surface of said first polymer layer and on said contact point, wherein said metallization structure is connected to said contact point through said second opening, wherein said forming said metallization structure comprises forming a metal layer on said top surface of said first polymer layer, on a sidewall of said second opening and on said contact point, followed by forming a photoresist layer on said metal layer, wherein a third opening in said photoresist layer exposes a region of said metal layer, followed by electroplating a third copper layer on said region, followed by removing said photoresist layer, followed by removing said metal layer not under said third copper layer.