Patent ID: 6166409
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A memory cell formed in a semiconductor material of a first conductivity type, the cell comprising:a channel region defined in the semiconductor material, the channel region having a first side, an opposing second side, and a third side;a source region formed in the semiconductor material, the source region contacting the first side of the channel region, and being doped to have a second conductivity type;a drain region formed in the semiconductor material, the drain region contacting the second side of the channel region, and being doped to have the second conductivity type;a first dielectric region formed on the semiconductor material, the first dielectric region contacting the third side of the channel region;a first vertical area enhancing structure formed over the first dielectric region, the first vertical area enhancing structure being totally electrically isolated;a layer of dielectric material formed on the semiconductor material over the channel region;a floating gate formed over the first vertical area enhancing structure and the layer of dielectric material;an intergate dielectric formed on the floating gate; anda control gate formed on the intergate dielectric over the first vertical area enhancing structure.