Patent ID: 6134064
Filing Date: 2000-10-17
Classification: G11B,H03L

Abstract:
A playback clock extracting apparatus, comprising:a quantization means for quantizing, at a sampling clock rate twice a recording rate, a signal played back from a recording medium so as to output sample data;a digital equalizer for digitally equalizing the sample data so as to alternately output segments of playback data and PLL data at an interval of the sampling clock rate;a ternary decision means for making a ternary decision as to whether each segment of playback data is positive, zero or negative;an arithmetic means for calculating a sampling phase error in said quantization means by multiplying the ternary decision by a difference between two successive segments of PLL data, one segment of PLL data being outputted immediately prior to the segment of playback data having the ternary decision made thereon by said ternary decision means and the other segment of PLL data being outputted immediately subsequent to the segment of playback data having the ternary decision made thereon by said ternary decision means;a sampling clock generating means for controlling a phase and oscillation frequency on the basis of the sampling phase error outputted by said arithmetic means so as to generate the sampling clock rate; anda playback clock generating means for dividing a frequency of the sampling clock rate by two so as to generate a playback clock rate for detecting the playback data.