Patent ID: 8569845
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. A microelectronic device, comprising: a gate structure overlying a semiconductor substrate and for selectively operating a strained p-channel in the semiconductor substrate; and source and drain regions, each comprising: a clamping layer surrounding at least a portion of the gate structure and over the second doped region; an L-shaped dielectric liner having a first portion physically contacting a sidewall of a gate electrode of the gate structure and a second portion extending over the second doped region, wherein the sidewall of the gate electrode extends along an axis that is substantially perpendicular the top surface of the semiconductor substrate; and a relatively thin spacer extending over the first doped region and having a first side abutting the first portion of the liner and a second side abutting the second portion of the liner, wherein a length of the second portion of the liner is greater than a width of the second side of the spacer such that the second portion of the liner extends further over the second doped region than does the second side of the spacer, wherein the clamping layer extends further over the second doped region away from the gate structure than does the second portion of the liner.