Patent ID: 6215346
Filing Date: 2001-04-10
Classification: G09G,H03K

Abstract:
A clock pulse generator comprising a clock input and N stages, when N is greater than three, each ith one of the stages comprising a pass gate arranged to be controlled by a control signal from the (i-1)th stage for passing a clock pulse from the clock input to an output of the pass gate and a control signal generating circuit responsive to the output of the pass gate for supplying a control signal to the (i+1)th stage, the control signal generating circuit being arranged to be inhibited form supplying further control signals in response to a control signals from the (i+2)th stage, where 1<1<(N-1),wherein the controls signal generating circuit of each ith stage comprises first and second metal-oxide-silicon field effect transistors of opposite conductivity types connected in series between first and second power supply inputs, the gate of the first transistor being connected to the output of the pass gate and the gate of the second transistor being connected to the control signal generating circuit of the (i+2)th stage.