Patent ID: 6921697
Filing Date: 2005-07-26
Classification: H01L

Abstract:
1. A method of fabricating an MIS device, comprising: providing a semiconductor substrate; forming a trench in said substrate, said trench including a sidewall and a bottom; depositing a thick insulative layer on said sidewall and said bottom, wherein said thick insulative layer is not formed by thermally oxidizing said semiconductor substrate in said trench; depositing a mask layer in said trench; etching a first portion of said mask layer to expose a first portion of said thick insulative layer on said sidewall, while leaving a second portion of said mask layer at said bottom of said trench; etching said first portion of said thick insulative layer to form an exposed portion of said sidewall, while leaving a second portion of said thick insulative layer at said bottom of said trench; etching said second portion of said mask layer to expose said second portion of said thick insulative layer at said bottom of said trench; forming a first thin insulative layer on said exposed portion of said sidewall; and forming a gate above said portion of said thick insulative layer and adjacent said first thin insulative layer in said trench.