Patent ID: 6550022
Filing Date: 2003-04-15
Classification: G01R,G06F

Abstract:
A data processing system, comprising:one or more processors; a memory coupled to said one or more processors; a collection of interconnected modules coupled to said one or more processors, said collection including at least first and second modules, wherein said first module, responsive to detection of a condition, transmits a halt signal to all modules in said collection and transmits said halt signal, via said second module, to said one or more processors; wherein said second module stores an indication of a module from which said halt signal was received; wherein said one or more processors, responsive to said halt signal, query said second module and each successive module in a path coupling said first and second modules until said first module is identified as a source of said halt signal; and wherein said one or more processors stores system status information regarding said collection within said memory.