Patent ID: 7816199
Filing Date: 2010-10-19
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, comprising: providing a semiconductor substrate comprising a first doped gate electrode and a second doped gate electrode, the first doped gate electrode comprising a first doped radon separated from a first gate insulation layer by a first depletion layer and the second doped gate electrode comprising a second doped region separated from a second gate insulation layer by a second depletion layer; forming a mask over said substrate, said mask covering said first doped gate electrode; performing an ion implantation process to introduce ions of a non-doping element into said second doped gate electrode, the non-doping element reducing dopant diffusion in said second doped gate electrode, and said mask being adapted to absorb ions impinging on said first doped gate electrode; and performing an annealing process after said ion implantation process, wherein dopant diffusion in said second doped gate electrode is reduced relative to dopant diffusion in said first doped gate electrode by the presence of the non-doping element in said second doped gate electrode so that a first thickness of the first depletion layer is less than a second thickness of the second depletion layer following the annealing process.