Patent ID: 6340841
Filing Date: 2002-01-22
Classification: H01L,H05K

Abstract:
A package for semiconductor devices, comprising:a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a throughhole penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns has a pad for electrical connection to a semiconductor chip, wherein the pad is electrically connected, through the front side laminate of upper wiring patterns alone, to the throughhole of the core board; a back side laminate of insulating layers on the back side base wiring pattern; and an external connection wiring pattern including external connection terminals on the outermost one of the insulating layers of the back side laminate, wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers and the back side laminate of insulating layers includes no intermediate wiring patterns, except for ground or power planes, intervening between the insulating layers.