Patent ID: 9151712
Filing Date: 2015-10-06
Classification: G01N,G03F

Abstract:
1. A computer-implemented method, comprising: analyzing a computer-readable design file using a computer, wherein the design file defines a pattern to be formed on a substrate, the pattern including circuit features that correspond to operational device features in an integrated circuit, to select a circuit feature in the pattern as a metrology target for performing a metrology that requires a dedicated metrology target for performing the metrology, wherein the selected circuit feature is not a dedicated metrology target; and performing the metrology on the substrate with a computer-controlled metrology tool using a printed feature on the substrate that corresponds to the selected circuit feature as the metrology target, wherein the circuit feature is selected by performing a search of the design file for one or more circuit feature candidates from said circuit features that meet one or more pre-determined geometric and/or spatial criteria before the metrology tool performs the metrology, wherein the one or more circuit feature candidates are characterized by a pitch that is too small to be resolved by the metrology tool to ensure that only a specific diffraction order of light scattered from the printed feature is collected by the metrology tool during said performing the metrology.