Patent ID: 6406958
Filing Date: 2002-06-18
Classification: H01L,Y10S

Abstract:
A method of manufacturing a nonvolatile semiconductor memory device, comprising:depositing on a semiconductor surface at least three layers including a gate insulation film, a first silicon layer and a first insulation film; patterning said three layers into stripe columnwise lines; forming an element isolating region of a groove structured on the semiconductor surface, wherein an edge of said element isolating region extends along an edge of said first insulation film; removing said first insulation film and depositing a second silicon layer; patterning said second silicon layer into stripe columnwise lines each having a width greater than that of said first silicon layer, and covering said first silicon layer; depositing at least two layers including a second insulation layer and a third silicon layer; and patterning said first silicon layer, said second silicon layer and said third silicon layer into rowwise lines which extend substantially orthogonally to said columnwise lines.