Patent ID: 6093631
Filing Date: 2000-07-25
Classification: H01L,Y10S

Abstract:
A method for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer comprising the steps of:dividing each chip on the wafer into a plurality of regions;determining the metal density for each region of each chip based on the circuit pattern for that region;adding a dummy circuit pattern to each region on each chip to provide at least a minimum metal density in each region or setting a maximum and/or minimum noted density for each region;forming both the desired circuit pattern and any dummy circuit pattern as openings in a dielectric layer on each chip;coating the patterned dielectric layer with a layer of metal which metal fills the openings forming the desired circuit pattern and any dummy circuit pattern and covers the surface of the wafer including the circuit patterns; andpolishing the metal coated wafer until no metal remains outside the desired and any dummy circuit patterns.