Patent ID: 7456100
Filing Date: 2008-11-25
Classification: H01L,Y10T

Abstract:
1. A method for fabricating an integrated circuit chip, comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure and exposes said first contact point, and a second opening in said passivation layer is over a second contact point of said first metallization structure and exposes said second contact point, wherein said first and second contact points are separated from each other by an insulating material, and wherein said first opening has a transverse dimension between 0.5 and 3 micrometers, and wherein said passivation layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers; and forming a second metallization structure in said first and second openings, over said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said forming said second metallization structure comprises forming electroplated copper in said first and second openings, over said passivation layer and over said first and second contact points.