Patent ID: 6407642
Filing Date: 2002-06-18
Classification: H03D,H03L

Abstract:
A frequency detector comprising:a three-state phase detector including first and second input terminals and first and second output terminals, wherein to detect a phase difference between first and second input clock signals presented to the first and second input terminals, respectively, the phase detector outputs first and second phase difference pulse signals through the first and second output terminals, respectively, by alternating among three states in such a manner that: if an effective edge of the first input clock signal is presented to the phase detector in a neutral state, then the phase detector is set to change into a first phase detection state, if an effective edge of the second input clock signal is presented to the phase detector in the neutral state, then the phase detector is set to change into a second phase detection state and if effective edges of the first and second input clock signals are presented to the phase detector in this order or vice versa, then a reset signal is generated and the phase detector is reset and set back to the neutral state responsive to the reset signal; a first latch, which latches the signal, output through the first output terminal, responsive to an effective edge of the first input clock signal, and which is reset responsive to the reset signal, the first latch outputting a first frequency difference pulse signal if two edges of the first input clock signal have been presented to the phase detector consecutively with no effective edges of the second input clock signal presented between the two edges; a second latch, which latches the signal, output through the second output terminal, responsive to an effective edge of the second input clock signal, and which is reset responsive to the reset signal, the second latch outputting a second frequency difference pulse signal if two edges of the second input clock signal have been presented to the phase detector consecutively with no effective edges of the first input clock signal presented between the two edges; and circuit means for making pulse widths of the first and second frequency difference pulse signals constant and then outputting the first and second frequency difference pulse signals with the constant widths.