Patent ID: 6069832
Filing Date: 2000-05-30
Classification: G11C

Abstract:
A method of powering up a complementary metal-oxide semiconductor (CMOS) memory integrated circuit comprising the steps of:providing a supply voltage to the CMOS integrated circuit;dividing the CMOS memory integrated circuit into n memory array portions including a first memory array portion and a second memory portion, each memory array portion having memory cell capacitors organized in rows and columns for storing data;generating a first powerup control signal;coupling the supply voltage to the first memory array portion based on the first powerup control signal being active;charging the memory cell capacitors of the first memory array portion to a cell plate voltage based on the first powerup control signal being active;generating a second powerup control signal, which is active a selected time delay after the first powerup control signal is active;coupling the supply voltage to the second memory array portion based on the second powerup control signal being active; andcharging the memory cell capacitors of the second memory array portion to the cell plate voltage based on the second powerup control signal being active.