Patent ID: 8012874
Filing Date: 2011-09-06
Classification: H01L,H05K,Y02P

Abstract:
1. A method of manufacturing, comprising: forming a mask on a semiconductor chip substrate having a first pair of conductor pads and a second pair of conductor pads, the mask having a first plurality of openings exposing selected portions of one of the first pair of conductor pads and a second plurality of openings exposing selected portions of the other of the first pair of conductor pads, each of the first plurality of openings and the second plurality of openings having a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate, wherein the footprint provides the capability to couple different sized capacitors to the semiconductor chip substrate; and placing conductor material in the first plurality of openings and the second plurality of openings to establish plural capacitor pads.