Patent ID: 6117759
Filing Date: 2000-09-12
Classification: H01L,H05K

Abstract:
A method of packaging an integrated circuit, the method comprising the steps of:providing a non-semiconductor substrate having a top side and a bottom side and having a first plurality of metallized pads on the top side and a second plurality of pads arranged in a first pattern on the bottom side;providing a semiconductor device with a first interconnect structure attached thereto;placing the first interconnect structure with the semiconductor device attached thereto in aligned contact with the first plurality of metallized pads;providing a boat for holding solder balls arranged in the first pattern;placing solder balls in the boat;aligning the solder balls with and contacting the solder balls to the second plurality of pads; andcontemporaneously reflowing the first interconnect structure and the solder balls such that the semiconductor device and the solder balls are connected to the first and second plurality of metallized pads of the substrate.