Patent ID: 7239254
Filing Date: 2007-07-03
Classification: H03K,H03M

Abstract:
1. An integrated circuit comprising: a first digital circuit to source digital data at a first clock frequency; a second digital circuit to receive the digital data at the first clock frequency; and a plurality of signal conductors coupling the first digital circuit and the second digital circuit; wherein the first digital circuit includes output circuitry to drive a different subset of the digital data on each of the plurality of signal conductors at a frequency less than the first clock frequency, and wherein the second digital circuit includes input circuitry to multiplex the plurality of signal conductors back to a single conductor at the first clock frequency, and wherein the first and second digital circuits are spaced far enough apart on the integrated circuit such that a propagation delay on any of the plurality of signal conductors is greater than one clock period at the first clock frequency.