Patent ID: 7879706
Filing Date: 2011-02-01
Classification: H01L

Abstract:
1. A manufacturing method of a memory, the method comprising: orderly forming a first dielectric material layer, a first storage material layer, a first blocking material layer, and a first gate material layer; orderly removing part of the first gate material layer, part of the first blocking material layer, part of the first storage material layer and part of the first dielectric material layer to form a second gate material layer, a second blocking material layer, a second storage material layer and a second dielectric material layer; forming a source and a drain between the second dielectric material layer; forming a third isolation material layer on the source and the drain; removing part of the second gate material layer, part of the second blocking material layer, part of the second storage material layer and part of the second dielectric material layer to respectively form a first tunneling dielectric layer, a second tunneling dielectric layer, a first charge storage layer, a second charge storage layer, a first blocking layer, a second blocking layer, a first gate and a second gate in an opening, wherein the first tunneling dielectric layer, the first charge storage layer, the first blocking layer and the first gate have opposite lateral surfaces substantially being coplanar, and the second tunneling dielectric layer, the second charge storage layer, the second blocking layer and the second gate have opposite lateral surfaces substantially being coplanar; forming a first isolation wall, a second isolation wall and an isolation bottom layer in the opening, the first tunneling dielectric layer, the first charge storage layer, the first blocking layer and the first gate formed between the first isolation wall and the source, the second tunneling dielectric layer, the second charge storage layer, the second blocking layer and the second gate formed between the second isolation wall and the drain, the isolation bottom layer positioned between the first isolation wall and the second isolation wall; forming a conductive layer among the isolation bottom layer, the first isolation wall and the second isolation wall; removing part of the third isolation material layer to form a fourth isolation material layer and exposing the surfaces of the first gate, the first isolation wall, the conductive layer, the second isolation wall and the second gate; and forming a word line to cover the surfaces of the fourth isolation material layer, the first gate, the first isolation wall, the conductive layer, the second isolation wall and the second gate, the word line electrically connected to the first gate, the conductive layer and the second gate.