Patent ID: 8301870
Filing Date: 2012-10-30
Classification: G06F

Abstract:
1. An apparatus, comprising: an out-of-order processor executing at least two threads of instructions that communicate and synchronize with each other as two concurrent co-routine threads, wherein said two concurrent co-routine threads result because a synchronization of said at least two threads is achieved by monitoring addresses of instructions in at least one of said at least two threads without modifying, changing, or altering the threads, said monitoring of addresses being controlled by an occurrence of an instruction in an execution of a first thread that is monitoring a second thread, wherein two of said at least two threads comprise: wherein said out-of-order processor comprises an instruction decoder having a meta-program control unit (MPCU) that generates a meta-program instruction tag for each meta-program instruction to be processed, said meta-program instruction tag comprising a plurality of portions, wherein: said out-of-order processor further comprising: