Patent ID: 6410387
Filing Date: 2002-06-25
Classification: H01L,Y10S

Abstract:
A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than said low operating voltage of the logic circuitry, the process comprising:on first portions of a semiconductor substrate, forming a first gate oxide layer with a first thickness for first transistors operating at said high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer with a second thickness for memory cells of the memory device; on said first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; in said first portions of the semiconductor substrate, forming source and drain regions for the first transistors; after forming source and drain regions in the first portion, forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer with a third thickness for second transistors operating at said low operating voltage; on the dielectric layer and on said third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in said second portions of the semiconductor substrate, forming source and drain regions for the memory cells; and in said third portions of the semiconductor substrate, forming source and drain regions for the second transistors.