Patent ID: 7543216
Filing Date: 2009-06-02
Classification: G01R,G06F

Abstract:
1. An apparatus for detecting errors in data stored in SRAM in a field programmable integrated circuit, said apparatus comprising: a configuration SRAM configured to receive and store device configuration data from an external source in response to address signals generated by row and column counters and configured to cycle data out in response to address signals from the row and column counters; a user-assignable SRAM configured to receive data from a serial data stream from an external source in response to address signals generated by row and column counters and configured to cycle data out in response to address signals from said row and column counters; a CRC check circuit configured to selectively receive data cycled out of the configuration SRAM and the user-assignable SRAM and to generate an error signal when an error is detected; and an I/O pin on the integrated circuit coupled to the CRC check circuit to received the error signal.