Patent ID: 7826280
Filing Date: 2010-11-02
Classification: G11C

Abstract:
1. An integrated circuit comprising: at least one memory cell; a read circuit configured to read the memory cell, wherein the read circuit comprises an output holding circuit configured to hold a memory cell content signal read from the memory cell; an enable circuit configured to provide the memory cell content signal at an output of the read circuit only when the memory cell fulfills a predefined criterion, wherein the enable circuit further comprises an output holding circuit clock signal generator circuit configured to provide an output holding circuit clock signal; a valid bit memory cell storing information as to whether the memory cell is a valid bit memory cell; a valid bit memory cell sense amplifier circuit; wherein an input of the valid bit memory cell sense amplifier circuit is coupled with the valid bit memory cell to receive a valid bit memory cell content signal; wherein an enable input of the valid bit memory cell sense amplifier circuit is configured to receive a valid bit memory cell sense amplifier circuit enable signal; wherein an output of the valid bit memory cell sense amplifier circuit is coupled with the enable input of a memory cell sense amplifier circuit of the read circuit.