Patent ID: 7626878
Filing Date: 2009-12-01
Classification: G11C

Abstract:
1. A two-port static random access memory (SRAM) circuit, comprising: control logic configured to receive a reference clock signal and to transmit a read address, a write address and a read-write select signal; a shared address decoder configured to receive the read address, the write address and the read-write select signal from the control logic and to assert a word line signal; a single-port memory array configured to receive the asserted word line signal from the shared address decoder; and a read/write input/output unit configured to read data from and write data to the single-port memory array and including an active bit line charge keeper configured to increase a second differential voltage between the first bit line and the second bit line to achieve a differential state change and reduce a first differential voltage developed on a first bit line and a second bit line during a read cycle by activating a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the positive supply voltage and the second transistor is coupled between the second bit line and the positive supply voltage with a gate of the first transistor coupled to a gate of the second transistor to restore the first bit line and the second bit line between read and write cycles.