Patent ID: 6445018
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A semiconductor device comprising:a lower-layer signal line provided in a lower layer below one of a main power-supply line and a main ground line via an insulating layer; and an upper-layer signal line provided in an upper layer above said one of the main power-supply line and the main ground line via an insulating layer, wherein: the main power-supply line and the main ground line are wider than the upper-layer signal line; other lines formed in the upper layer for adjusting the wiring capacity between lines, said other lines functioning as master slice signal lines used for changing a mask pattern of the semiconductor device; a window formed in said one of the main power-supply line and the main ground line; the lower-layer signal line and the upper-layer signal line being electrically connected in a space inside the window, without contacting said one of the main power-supply line and the main ground line.