Patent ID: 6052316
Filing Date: 2000-04-18
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a first plurality of power supply terminals supplied with a power supply potential corresponding to the level of outputted data;a plurality of power supply lines, equal in number to that of said first plurality of power supply terminals, supplied with said power supply potential from said first plurality of power supply terminals respectively;a second plurality of data output terminals for outputting data; anda plurality of data output buffers, equal in number to that of said second plurality of power supply terminals, provided in corresponding to said second plurality of data output terminals respectively for receiving data from an internal circuit and driving the potentials of corresponding said second plurality of output terminals,each said data output buffer including:a third plurality of switching circuits connected between corresponding said data output terminal and any of said plurality of power supply lines respectively, anda control circuit for bringing said third plurality of switching circuits into conducting stages in response to said data from said internal circuit.