Patent ID: 8143075
Filing Date: 2012-03-27
Classification: B82Y,G03F,H01J,H01L

Abstract:
1. A semiconductor device manufacture method comprising steps of: (a) forming a semiconductor device structure in a chip and alignment marks, respectively in a semiconductor wafer, each of the alignment marks being constituted of a step or steps formed in the semiconductor wafer; (b) forming a workpiece layer above said semiconductor wafer covering the alignment marks; (c-1) forming a mask pattern over the workpiece layer; (c-2) etching the workpiece layer using the mask pattern as a mask, and exposing said alignment marks; (d) coating an electron beam resist film on said workpiece layer and on the exposed alignment marks; (e) scanning said steps of said exposed alignment marks with an electron beam to obtain plural position information of said alignment marks, said position information being represented in numerical values, and obtaining numerical differences between pairs among said plural position information of the alignment marks; (f) removing abnormal values of position information in accordance with the numerical differences between said pairs among said plural position information of the alignment marks, while retaining normal values of position information; and (g) performing an electron beam exposure in accordance with said retained normal values of said plural position information of said alignment marks.