Patent ID: 7492202
Filing Date: 2009-02-17
Classification: H03K

Abstract:
1. A flip-flop circuit comprising: an input terminal to which an input signal is input, a master latch portion for holding a signal input from the input terminal immediately before a timing signal changes from a first state to a second state, while the timing signal is in the second state; a slave latch portion for holding a signal input from the master latch portion immediately before the timing signal changes from the second state to the first state, while the timing signal is in the first state; an output terminal from which one of a signal according to a signal held in the master latch portion and a signal according to a signal held in the slave latch portion is output; and a selecting portion for selecting a signal according to a signal held in the master latch portion when the timing signal is in the second state, selecting a signal according to a signal held in the slave latch portion when the timing signal is in the first state, and causing the selected signal to be output from the output terminal, wherein an input capacitance at the input terminal and a driving capability at the output terminal when the timing signal is in the first state are equal to those when the timing signal is in the second state, and wherein the selecting portion includes: a first tri-state element for outputting a signal according to a signal held in the master latch portion when the timing signal is in the second state and setting an output thereof in a high-impedance state when the timing signal is in the first state; and a second tri-state element for outputting a signal according to a signal held in the slave latch portion when the timing signal is in the first state and setting an output thereof in a high-impedance state when the timing signal is in the second state, wherein the outputs of the first and second tri-state elements are connected to the output terminal, and a driving capability of the first tri-state element when the timing signal is in the second state is equal to that of the second tri-state element when the timing signal is in the first state.