Patent ID: 6274901
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a semiconductor substrate of a first conductivity type;a stacked gate portion formed by stacking a tunnel insulating film, a floating gate, a capacitive insulating film and a control gate in this order over the semiconductor substrate;source/drain regions of a second conductivity type, which are formed in an active region under the surface of the semiconductor substrate so as to sandwich the stacked gate portion therebetween; anda diffusion layer of the first conductivity type surrounding the bottom of the drain region of the second conductivity type,wherein the drain region at least includes a first diffusion layer containing a first impurity of the second conductivity type, and a second diffusion layer containing a second impurity of the second conductivity type, the second diffusion layer being adjacent to the first diffusion layer and overlapping with an entire edge region of the stacked sate portion in a gate width direction in the active region,and wherein the diffusion layer of the first conductivity type surrounds the bottoms of the first and second diffusion layers.