Patent ID: 6191445
Filing Date: 2001-02-20
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a substrate;a plurality of memory transistors formed in the vicinity of the surface of the substrate in a matrix form, each transistor including a semiconductor channel forming region formed in the vicinity of the surface of the substrate, a source region formed in the vicinity of the surface of the substrate and in contact with that channel forming region, a drain region in contact with the channel forming region at a distance from the source region, a gate insulating film containing a tunnel insulating film formed in the channel forming region, a conductive gate electrode formed on the gate insulating film, and a charge storing means formed inside the gate insulating film; anda non-selected column biasing means for supplying a non-selected bias voltage having a voltage value between a source voltage when reading a data from the selected memory transistor and a voltage supplied to the gate of the selected memory transistor when reading, to the sources and/or drains of the non-selected column memory transistors arranged in columns not containing the selected memory transistor for reading the data therefrom.