Patent ID: 6069834
Filing Date: 2000-05-30
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit device, comprising:a plurality of first modules, a second and a third module;each of said first modules including:a memory array having a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells arranged at the points of intersection thereof;a sense amplifier connected between bit lines of each of said plurality of bit line pairs for amplifying a signal of that bit line pair;a word driver for selectively driving said plurality of word lines;a data input/output line pair connected through a column switch to each of plural bit line pairs in each of a plurality of sets into which said plurality of bit line pairs are divided;a global bit line pair connected to said data input/output line pair, said global bit line pair extending on said memory array in the same direction as said bit line pairs; anda column decoder for outputting a column selection signal which opens and closes said column switch to select one of plural bit line pairs in each of said plurality of sets so that the selected bit line pair is connected to said global bit line pair,wherein said second module includes an amplifier for amplifying a signal from the memory cell through said global bit line pair and a writing circuit for writing data into the memory cell through said global bit line pair,said third module includes a circuit for generating voltages used in said first modules and said second module, andsaid plurality of said first modules are arranged adjacent each other, and said plurality of said first modules are connected to each other by said global bit line pairs.