Patent ID: 6873040
Filing Date: 2005-03-29
Classification: H01L

Abstract:
1. A packaged integrated circuit (IC) device comprising: a first package part having a top surface and a bottom surface, said top and bottom surfaces having pads for I/O terminals, said first part having connector lines between terminals on said top surface and terminals on said bottom surface; a cavity in said first package part; a chip mounted in said cavity, said chip having an active surface including an IC and contact pads; a second package part having a top surface and a bottom surface, said bottom surface having a first plurality of I/O terminals aligned with said chip contact pads, and a second plurality of I/O terminals aligned with said top surface I/O terminals of said first package part; said second package part further having connector lines between said first and second plurality of terminals; said connector lines including a signal layer, a power layer, and a ground layer, spaced by insulation of a thickness between 10 and 50 μm, and formed into lines having a width less than three times said insulator thickness; and interconnection elements between said chip contact pads and said first plurality of terminals of said second package part, and between said second plurality of terminals of said second package part and said top surface terminals of said first package part.