Patent ID: 6141272
Filing Date: 2000-10-31
Classification: G11C

Abstract:
A dynamic random access memory having a normal mode of operation and a test mode of operation, comprising:an array of individually addressable memory cells, each cell comprising a storage capacitor and an access transistor responsive to assertion of a row line signal applied to a gate thereof to selectively couple said capacitor to a digit line during a write access cycle;control and decoder circuitry having address inputs and control signal inputs, said control and decoder circuitry being responsive to application of timed sequences of address signals and control signals to said address inputs and control signal inputs to selectively assert row line signals applied to the gates of memory cell access transistors in said array;a programmable delay circuit coupled to said control and decoder circuitry and responsive to a first combination of control signals to assert a row line disable signal after a predetermined delay interval;wherein in said normal mode of operation said control and decoder circuitry is responsive to a second combination of said control signals to assert a row line signal and to a subsequent third combination of control signals to deassert said row line signal;and wherein in said test mode of operation said control and decoder circuitry is responsive to said second combination of said control signals to assert a row line signal and responsive to assertion of said row line disable signal to deassert said row line signal.