Patent ID: 6034384
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A semiconductor memory device fabricated on a semiconductor substrate, comprising:a plurality of memory cell arrays arranged in a first direction, and forming at least one pair of first memory cell arrays,one of the memory cell arrays of said at least one pair including a plurality of first memory cell sub-arrays each having first memory cells arranged in a first pattern in said first direction and a plurality of first peripheral circuits each electrically connectable to said first memory cells of the associated first memory cell sub-array and arranged in a second pattern, andthe other of said memory cell arrays of said at least one pair including a plurality of second memory cell sub-arrays each having second memory cells arranged in said first pattern in said first direction and a plurality of second peripheral circuits each electrically connectable to said second memory cells of the associated second memory cell sub-array and arranged in a third pattern symmetrical with said second pattern with respect to a second direction perpendicular to said first direction; andthird peripheral circuits electrically connectable to said memory cell arrays of said at least one pair, and located between said one of said memory cell arrays and said other of said memory cell arrays.