Patent ID: 9047077
Filing Date: 2015-06-02
Classification: G06F

Abstract:
1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions in an instruction set that includes a plurality of vector instructions that operate on data in a plurality of vector registers; and an optimizing compiler residing in the memory and executed by the at least one processor, the optimizing compiler including a vectorization mechanism that analyzes a portion of the computer program, generates from a first set of instructions in the computer program that does not include any of the plurality of vector instructions a second set of instructions that includes at least one of the plurality of vector instructions, determines when a second cost of processing the second set of instructions is less than a first cost of processing the first set of instructions, and when the second cost is less than the first cost, determining when the second set of instructions is likely to cause a processor running the computer program to stall when executing the second set of instructions by determining a ratio of vector instructions in the second set of instructions to total instructions in the second set of instructions, and when the second set of instructions is not likely to cause the processor running the computer program to stall when executing the second set of instructions, the vectorization mechanism substitutes the second set of instructions for the first set of instructions in the computer program, and when the second cost is not less than the first cost or when the second set of instructions is likely to cause the processor running the computer program to stall when executing the second set of instructions, the vectorization mechanism does not substitute the second set of instructions for the first set of instructions in the computer program.