Patent ID: 9024384
Filing Date: 2015-05-05
Classification: H01L

Abstract:
1. A method of forming an integrated circuit (IC) including at least one PMOS transistor, comprising: performing p-type lightly doped drain (PLDD) implantation to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on said semiconductor surface, wherein said PLDD implantation comprises co-implanting indium, carbon and a halogen, in addition to a boron comprising specie implant; performing source and drain implantation to establish source/drain regions, wherein said source/drain regions are distanced from said gate structure further than said source/drain extension regions, and source/drain annealing after said performing source and drain implantation, wherein said at least one PMOS transistor includes at least one core PMOS transistor and at least one non-core PMOS transistor, wherein said gate dielectric for said core PMOS transistor is at least 2 Å of equivalent oxide thickness (EOT) thinner as compared to said gate dielectric of said non-core PMOS transistor, and wherein during said PLDD implantation said indium, said halogen and said carbon are implanted into said source/drain extension regions for said core PMOS transistor and at least one of said indium, said halogen and said carbon are not implanted into said source/drain extension regions of said non-core PMOS transistor.