Patent ID: 6537923
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A process for forming an integrated circuit structure on a semiconductor substrate and characterized by reduced horizontal capacitance between closely spaced apart metal lines which comprises:a) forming, on an oxide layer of an integrated circuit structure on a semiconductor substrate, closely spaced apart metal lines with silicon nitride caps thereon; b) depositing low k silicon oxide dielectric material between said closely spaced apart metal lines and over said silicon nitride caps on said metal lines; c) forming a second layer of silicon nitride over said low k silicon oxide dielectric material; d) then planarizing said low k silicon oxide dielectric material down to the level of a top surface of said silicon nitride caps; and e) depositing a layer of standard k silicon oxide over said planarized low k silicon oxide dielectric and said silicon nitride caps.