Patent ID: 8095736
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. A method for managing a cache memory space having an associativity level associated therewith, said cache memory space being employed by a number of processor cores, said method comprising: determining a number n of partitions necessary in said cache memory space based on said number of processor cores, wherein each of said partitions: determining a number of cache pages in each of said n partitions and a number of cache sets to be used in each of said n partitions based on said number of cache pages and said associativity level, wherein each of said cache pages is assigned a cache page index; numbering each of said cache sets of each of said n partitions based on its associated partition number p and cache page index; and partitioning said cache memory space into said n partitions using said determined number of cache sets of each of said n partitions and said numbering of said cache sets.