Patent ID: 8806131
Filing Date: 2014-08-12
Classification: G06F,Y02D

Abstract:
1. A memory system comprising: a memory vault; a memory vault controller configured to communicate with the memory vault; a communication link interface configured to communicatively couple the memory vault controller at least one of an originating device or a destination device; a switch configured to connect the communication link interface to the memory vault controller; a packet decoder coupled to the switch to receive an outbound packet sent from the originating device across an outbound of the communication link interface, to extract at least one of an outbound memory command, an outbound memory address, or an outbound memory data field from the outbound packet, and to present a set of select signals to the switch; and a packet encoder coupled to the switch to receive at least one of an inbound memory command, an inbound memory address, or inbound memory data from the memory vault controller, and to encode the inbound memory address or the inbound memory data into an inbound packet for transmission across an inbound of the communication link interface to the destination device, wherein the communication link interface includes: