Patent ID: 7709301
Filing Date: 2010-05-04
Classification: G06F,H01L

Abstract:
1. A method of standard cell design of an integrated circuit comprising a substrate having a semiconducting surface, a plurality of standard cells arranged in a plurality of rows comprising at least a first row and a second row immediately above said first row, said first row comprising at least a first of said standard cells, said first standard cell comprising a first decap filler cell comprising at least a first MOS transistors having a gate electrode on a thick gate dielectric on said surface connected as a decoupling capacitor, said second row comprising at least a second of said standard cells, said second standard cell comprising a second decap filler cell comprising at least a second MOS transistors having a gate electrode on said thick gate dielectric on said surface connected as a decoupling capacitor, comprising: placing a plurality of circuit elements including said plurality of standard cells comprising a plurality of standard cell gates in a circuit layout for said integrated circuit and placing a plurality of decap filler cells including said first and second decap filler dells in at least some locations in said integrated circuit unused by said standard cell gates using design rules including a first minimum spacing between thick gate dielectric mask regions for adjacent cells; expanding at least one dimension of said thick gate dielectric mask for said plurality of decap filler cells to cause a violation of said first minimum spacing between said first and second decap filler cells, and placing a gap fill portion to add a thick gate dielectric mask portion across a border between said first and second decap filler cells to remove said violation.