Patent ID: 6574651
Filing Date: 2003-06-03
Classification: G06F

Abstract:
In a processing core having a register file and an arithmetic unit, the arithmetic unit comprising:a first set of input data lines effective for receiving the contents of a first register selected from the register file; a second set of input data lines effective for receiving the contents of a second register selected from the register file; a first multiplexer having mux input lines and mux output lines, the mux inputs in data communication with the first and second sets of input data lines, the mux inputs being grouped as subsets of mux input lines, the mux outputs being grouped as subsets of mux output lines; a plurality of multiplication circuits, each having inputs in data communication with one of the subsets of mux output lines, the multiplication circuits each having an intermediate output; a first adder circuit having inputs in data communication with the intermediate outputs and having an output, the first adder effective for outputting a product term corresponding to each of the intermediate outputs; a second adder circuit having inputs in data communication with the intermediate values and having an output, the second adder effective for outputting a single product term from the intermediate values; and a second multiplexer having inputs in data communication with the outputs of the first adder and the output of the second adder and having an output, whereby either the outputs of the first adder or the output of the second adder are produced at the output of the second multiplexer.