Patent ID: 8625781
Filing Date: 2014-01-07
Classification: H04L

Abstract:
1. Encryption processor comprising an S-box unit, a byte permutation unit, a MixColumns unit and a key expansion unit, wherein the byte permutation unit comprises: a data input terminal for receiving input data; two or more row processors, each row processor having an input coupled to the input terminal and an output; a clock gating circuit for generating for each of the two or more row processors a gated clock signal: wherein the byte permutation unit comprises four row processors, and the clock gating circuit is arranged for generating for each of the four row processors a different gated clock signal; wherein the byte permutation unit comprises four output terminals and each output of the four row processors being coupled to a corresponding output terminal; and wherein an output of the S-box unit is coupled to the input terminal of the byte permutation unit, and the four output terminals of the byte permutation unit are coupled to four input terminals of the MixColumns unit, wherein the MixColumns unit comprises: a rotator unit having four input terminals coupled to the four input terminals of the MixColumns unit and four output terminals, wherein the rotator unit is arranged to receive four bytes at the input terminal at a first frequency, to perform a cyclic shift on the four bytes at a second frequency to supply sequentially four groups of four intermediate bytes to four output terminals of the rotator unit, wherein the second frequency is four times the first frequency, and a mixing unit having four input terminals coupled to the four output terminals of the rotator unit and an output terminal, wherein the mixing unit is arranged to combine the data at the four input terminals (c wherein · is a multiplication in GF(2