Patent ID: 6713816
Filing Date: 2004-03-30
Classification: H01L

Abstract:
An ESD protection device for an integrated circuit which is integrated in a semiconductor substrate of said integrated circuit, comprising:a heavily doped p-region provided with a first connection electrode; a heavily doped n-region provided with a second connection electrode; a lightly doped p-region bordering on said heavily doped p-region; a lightly doped n-region bordering on said heavily doped n-region and said lightly doped p-region and having a first portion and a second portion; and a heavily doped n-layer; wherein said heavily doped n-region, said first portion of said lightly doped n-region and said lightly doped p-region form a lateral sequence of differently doped semiconductor regions adjacent a surface of said substrate; wherein said lightly doped p-region, said second portion of said lightly doped n-region and said heavily doped n-layer form a vertical sequence of differently doped semiconductor regions; wherein a lateral distance which exists between said lightly doped p-region and said heavily doped n-region and which is determined by said first portion of said lightly doped n-region is adjusted to be less than a distance which exists between said lightly doped p-region and said heavily doped n-layer and which is determined by said second portion of said lightly doped n-region such that a lateral breakthrough occurs between said lightly doped p-region and said heavily doped n-region before a vertical breakthrough occurs between said lightly doped p-region and said heavily doped n-layer, as a blocking voltage applied to said first and second connection electrodes increases; wherein said lightly doped p-region is implemented as a p-well around said heavily doped p-region; wherein said p-well is surrounded by said lightly doped n-region; and wherein said lightly doped n-region is surrounded by a buried heavily doped n-layer.