Patent ID: 6787411
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory device, comprising a memory array region constituted of a plurality of memory cells arranged in a matrix on a main surface of a semiconductor substrate,wherein each of said plurality of memory cells comprises: a reading MIS transistor having a source region and a drain region formed on the main surface of said semiconductor substrate, a channel forming region formed on the main surface of said semiconductor substrate positioned between said source region and said drain region, and a first gate electrode formed above the main surface of said semiconductor substrate, over said channel forming region, via a first gate insulating film; and a writing MIS transistor which is electrically connected to the first gate electrode of said reading MIS transistor, said writing MIS transistor having a source region, a channel forming region, and a drain region, which are formed to be a layered structure extending in a vertical direction to the main surface of said semiconductor substrate, and a second gate electrode formed on a sidewall of said layered structure via a second gate insulating film, the method of manufacturing the semiconductor memory device comprising the steps of: (a) locating a channel forming region of each row between a pair of rows adjacent to each other in said memory array region of the main surface of said semiconductor substrate, and forming a plurality of element isolation regions so as to define the source region and the drain region of said reading MIS transistor; (b) forming said first gate electrode of said reading MIS transistor and said layered structure such that said first gate electrode and said layered structure are arranged in said matrix, at positions corresponding to each row and each column and extending in the column direction intermittently, the first gate electrode being formed on said channel forming region of each row via the first gate insulating film such that both end portions thereof in the column direction terminate on said element isolation region, and the layered structure comprising a lower semiconductor layer constituting the source region of said writing MIS transistor deposited on the upper surface of said first gate electrode, an intermediate semiconductor layer constituting the channel forming region thereof, and an upper semiconductor layer constituting the drain region thereof; (c) introducing impurities into said semiconductor substrate using said layered structure and said element isolation region as a mask, thus forming the source region and the drain region of said reading MIS transistor; (d) forming a first interlayer insulating film on said semiconductor substrate so as to fill a gap between said plurality of layered structures arranged in said matrix; (e) forming a first conductive layer so as to be electrically connected to an upper surface of said plurality of layered structures exposed from said first interlayer insulating film and so as to cover said upper surface of said first interlayer insulating film; (f) performing etching of said first conductive layer, thus forming a first bit line, which extends in the row direction across the upper surface of a plurality of said layered structures positioned in each row and which is electrically connected to each of said upper semiconductor layers of said plurality of layered structures; (g) performing etching of said plurality of layered structures positioned below said first bit line such that the width of each layered structure corresponds to that of said first bit line and until the etching reaches said first gate electrode of said reading MIS transistor, thus exposing sidewalls of each of said plurality of layered structures; (h) forming a second gate insulating film on said sidewall of said plurality of layered structures exposed in said step (g), thus forming a second conductive layer so as to cover said sidewall portion and the upper portion of said first bit line; and (i) performing etching of said second conductive layer, thus forming a second gate electrode, of said writing MIS transistor, which extends in the column direction across the upper portion of said plurality of layered structures positioned in each column, and which covers each of said sidewall portions of said plurality of layered structures.