Patent ID: 7119594
Filing Date: 2006-10-10
Classification: H03K,H03L

Abstract:
1. A duty cycle correction circuit of a delay locked loop, comprising: a differential amplifier having first and second input terminals and first and second differential output terminals, and adapted to receive differential reference clock signals input via the first and second input terminals, to amplify the differential reference clock signals, and to output the amplified differential reference clock signals via the first and second differential output terminals, the differential amplifier including a switching device connected between the first and second differential output terminals, the switching device having a control terminal adapted to receive an equalization control signal and in response thereto to equalize voltages on the first and second differential output terminals; a first transmission circuit connected between the first differential output terminal of the differential amplifier and a first node, and adapted to transmit to the first node a first one of the amplified differential reference clock signals appearing at the first differential output terminal of the differential amplifier; a second transmission circuit connected between the second differential output terminal of the differential amplifier and a second node, and adapted to transmit to the second node a second one of the amplified differential reference clock signals appearing at the second differential output terminal of the differential amplifier; a first storage unit connected between the first node and a ground voltage, and adapted to store a signal of the first node; a second storage unit connected between the second node and the ground voltage and adapted to store a signal of the second node; and a switching circuit connected between the first node and a first output terminal of the duty cycle correction circuit, and connected between the second node and a second output terminal of the duty cycle correction circuit, the switching circuit having a control terminal adapted to receive a switching control signal to selectively provide the signals of the first and second nodes to the first and second output terminals of the duty cycle correction circuit.