Patent ID: 7531439
Filing Date: 2009-05-12
Classification: H01L

Abstract:
1. A method for forming an integrated semiconductor circuit arrangement, comprising: providing a semiconductor material region with a first semiconductor circuit region and with a second semiconductor circuit region, which are formed in the semiconductor material region and are covered with an intermediate oxide layer, contact structures or cutouts being formed in the intermediate oxide layer, which contact structures or cutouts reach as far as first contact locations of the first semiconductor circuit region and as far as second contact locations of the second semiconductor circuit region; forming a first metallization layer of a first metal material in such a way that at least the contact structures or cutouts are filled, the first contact locations of the first semiconductor circuit region are connected to the first metallization layer with first contacts, the second contact locations of the second semiconductor circuit region are connected to the first metallization layer with second contacts and metallization regions for wiring interconnects are formed in the region of and above the first semiconductor circuit region; forming a protective material region with or from one or more electrically conductive materials in such a way that the previously obtained structure, the first metallization layer and the first contacts are covered or embedded; forming and patterning a second metallization layer of a second metal material in such a way that the previously obtained structure and the first metallization layer in the region of and above the second semiconductor circuit region and the second contacts thereof are covered or embedded with the second metallization layer with the protective material region in between in such a way that the second contacts of the second semiconductor circuit region are covered and thereby reinforced; and that the previously obtained structure and the first metallization layer in the region of and above the first semiconductor circuit region and the first contacts with the protective material region uppermost remain free or are removed of the second metallization layer; the patterning of the second metallization layer being effected without a patterning of the protective material region; during the patterning of the second metallization layer, the protective material region is used for protecting the underlying structure, for protecting the first metallization layer and for protecting the first and second contacts thereof; after the patterning of the second metallization layer, patterning the first metallization layer of the first metal material and the protective material region in the region of and above the first semiconductor circuit region in such a way that, in the region of and above the first semiconductor circuit region, at least contact structures or cutouts are filled, first contact locations of the first semiconductor circuit region are connected to the first metallization layer with the first contacts and wiring interconnects are formed in the region of and above the first semiconductor circuit region; forming a planarization layer of the protective material region in such a way that a surface topography of a structure previously obtained after the patterning of the first and second metallization layers is planarized by filling depressions or cutouts and the integrated semiconductor circuit arrangement is planarized after forming the protective material region.