Patent ID: 7096406
Filing Date: 2006-08-22
Classification: G06F,G11C

Abstract:
1. A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2 n , where n is an integer greater than or equal to 2) cell memory via a data bus the width of which is a plurality of bits, and the memory controller comprising: first through Mth FCC circuits, into which first through Mth (where M is greater than or equal to n) data bus groups of a first data bus connected to said host are input in parallel respectively, and which, for first through Mth data groups being input via the first through Mth data bus groups respectively, generate first through Mth error correction codes for correcting a single-bit defect, a page of data being comprised of the first through Mth data groups; a data output unit, which outputs the first through Mth data groups to a second data bus connected to data input/output terminals of said N-level cell memory such that n data bits associated with a single N-level cell are separated into the first through Mth data groups, without overlap, such that each of the first through Mth data groups include no more than a single one of the n data bits, wherein said data output unit further outputs to said second data bus the respective error correction codes generated by the ECC circuits.