Patent ID: 6240044
Filing Date: 2001-05-29
Classification: G11C

Abstract:
An address sequencer receiving a clock signal and generating a plurality of even address signals and a plurality of odd address signals, the address sequencer comprising:a plurality of even address signal generators, each even address signal generator receiving the clock signal and generating one of the plurality of even address signals;a plurality of odd address signal generators, each odd address signal generator receiving the clock signal and generating one of the plurality of odd address signals;a plurality of even toggle logic cells generating one of a plurality of even toggle signals and one of a plurality of even toggle address signals, each even toggle logic cell is associated with and provides its said toggle address signal to one of the plurality of even address signal generators and receives one of the plurality of even address signals from the associated one of the plurality of even address signal generators; anda plurality of odd toggle logic cells generating one of a plurality of odd toggle signals and one of a plurality of odd toggle address signals, each odd toggle logic cell is associated with and provides its said toggle address signal to one of the plurality of odd address signal generators and receives one of the plurality of odd address signals from the associated one of the plurality of odd address signal generatorswherein each said toggle logic cell includes either a NAND or NOR sate for generating the corresponding toggle logic signal, and an output of said gate in each said toggle logic cell is connected to an input of said gate in another said toggle logic cell.