Patent ID: 7230460
Filing Date: 2007-06-12
Classification: H03L,H04L

Abstract:
1. An integrated circuit comprising: an input circuit configured to receive a channel signal from a source, provide impedance matching and amplify the channel signal; a clock generator configured to generate a plurality of clock signals with a substantially identical frequency and a phase shift in reference to an initial clock signal, wherein the initial clock signal is provided in accordance with a frequency in the channel signal; an oversampling circuit configured to sample the channel signal in response to the plurality of clock signals; a phase detection unit configured to receive sampled signals from the oversampling circuit and generate a first adjustment signal and a second adjustment signal according to a predetermined mapping relationship; and a phase alignment circuit configured to adjust the phases of the plurality of the clock signals in response to the first adjustment signal and the second adjustment signal, wherein the phase alignment circuit comprises a delay locked loop configured (i) to receive the plurality of clock signals from the clock generator, (ii) to adjust the phases of the plurality of clock signals in response to an offset signal and (iii) to present the phase adjusted plurality of clock signals to the oversampling circuit, wherein the offset signal is generated in response to the first adjustment signal and the second adjustment signal.