Patent ID: 7783861
Filing Date: 2010-08-24
Classification: G06F,G06T

Abstract:
1. A processor array system comprising a processor element (referred to below as PE) block array including at least three PE blocks, each of the PE blocks including a plurality (M items) of PEs that perform SIMD operations, wherein the M items of PEs that make up at least one PE block are connectable to the M items of PEs that make up at least one other PE block different from the one PE block via a first transfer buffer of the at least one PE block, through M number of first signal lines, each of the first signal lines having predetermined bits, M being the same as the number of the PEs included in the PE block, and the M items of PEs that make up the one PE block are connectable to the M items of PEs that make up at least one yet another PE block different from the one PE block and the other PE block via a second transfer buffer of the at least one PE block, through M number of second signal lines, each of the second lines having predetermined bits; and one of the M PEs included in the one PE block comprises a selector circuit that selects, based on control signals derived from a direction register and a mask register that are provided to the selector circuit, wherein signals output at least one of the other M−1 PEs of the at least one PE block are provided to the selector circuit of the at least one PE block, together with the first signal lines and the second signal lines respectively output from the first and second transfer buffers, wherein the selector circuit comprises: