Patent ID: 7126400
Filing Date: 2006-10-24
Classification: H03K,H03L

Abstract:
1. A delay adjustment circuit, comprising: a delay circuit to which an input signal is input, the delay circuit including a plurality of delay units and outputting a delay signal of the input signal; a comparison circuit which stores, to a comparison result register, comparison result data of a pulse width time of a pulse of a test input signal which is the input signal in a test mode and M-th to N-th (M and N are integers provided that N>M) delay times of M-th to N-th delay signals, the test input signal being input to the delay circuit and the M-th to N-th delay signals being respectively output from M-th to N-th taps among a plurality of taps provided between the delay units of the delay circuit; an adjustment circuit which adjusts delay time of the delay signal of the input signal in the delay circuit, wherein the adjustment circuit includes a second select circuit for typical value setting to which I-th to J-th (I and J are integers provided that J>I) delay signals are input and which selects and outputs one of the I-th to J-th delay signals, the I-th to J-th delay signals being respectively output from I-th to J-th taps among the plurality of taps of the delay circuit, and wherein the output from the second select circuit is input to a (J+1)th delay unit among the plurality of the delay units, a (J+1)th tap among the plurality of taps of the delay circuit being provided to an output of the (J+1)th delay unit.