Patent ID: 6859852
Filing Date: 2005-02-22
Classification: G06F

Abstract:
1. A data transfer system comprising: a plurality of first bus devices, at least one first bus device being a first bus data supplying device capable of supplying data, at least one first bus device being a first bus data receiving device capable of receiving data and at least one first bus device being a first bus master device capable of requesting and controlling data transfer and at least one first bus devices and capable of transferring data from a first bus data supplying device to a first bus data receiving device under control of a first bus master device; a first data bus connected to each of said plurality of first bus devices and capable of transferring data from a first bus data supplying device to a first bus data receiving device under control of a first bus master device; a plurality of second bus devices, at least one second bus device being a second bus data supplying device capable of supplying data, at least one second bus device being a second bus data receiving device capable of receiving data, a plurality of second bus devices each being a second bus master device capable of requesting and controlling data transfer, a predetermined one of said plurality of second bus devices being a dominant second bus master device responsive to real time events asynchronous to operation of said central processing unit; a second data bus connected to each of said plurality of second bus devices and capable of transferring data from a second bus data supplying device to a second bus data receiving device under control of a second bus master device; a bus bridge connected to said first data bus and said second data bus, said bus bridge capable of supplying data to said first bus, receiving data from said first bus, supplying data to said second bus, receiving data from said second bus, not capable of controlling data transfer on said first bus and capable of controlling data transfer on said second bus; and a second bus arbiter connected to each of said at least one second bus master device, said second bus and said bus bridge, said second bus arbiter granting control of data transfer on said second bus to one and only one of the set of devices including each second bus master and said bus bridge, said second bus arbiter granting control of data transfer to said dominant second bus master immediately upon request and interrupting any data transfer controlled by another second bus master.