Patent ID: 6385092
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A nonvolatile memory device comprising:a memory array; and a controller, wherein said memory array comprises a plurality of data latches, a plurality of nonvolatile memory cells, a plurality of word lines and a plurality of data lines, wherein each of the data latches is connected to a corresponding one of the data lines, wherein each of said memory cells is connected to a corresponding one of the word lines and a corresponding one of the data lines and is capable of storing data as a threshold voltage within one of a plurality of threshold voltage distributions, wherein said controller is capable of receiving a command information, an address information and a first data, and controls of a data erasing operation, a data writing operation, a data rewriting operation or a data reading operation according to said command information to said memory array, and wherein said controller controls steps in a data rewriting operation as follows: (1) selecting one word line corresponding to said address information, (2) reading data from said memory cells connected to said selected word line to said data latches, (3) storing said first data to ones of said data latches according to said address information, (4) erasing data in said memory cells connected to said selected word line, and (5) writing data in said data latches to said memory cells connected to said selected word line.