Patent ID: 6757788
Filing Date: 2004-06-29
Classification: G06F

Abstract:
A cache coherence control system for caches which store, in the unit of a predetermined block, data of a shared memory accessed by a CPU or an I/O device provided at each of a plurality of nodes interconnected by a mutual interconnection network, wherein:in the cache coherence control system, each node has an access right memory for registering an access right entry representative of that the node has an access right to an extended block corresponding to a plurality of blocks of the shared memory; when the CPU or I/O device issues a shared memory access with cache coherence control to perform cache coherence control for caches of other nodes, an access right status of the extended block including a target block for the shared memory access is determined, and the determined access right status of the extended block is stored in the access right memory of the node; if the CPU or I/O device issues the shared memory access with cache coherence control and the node including the CPU or I/O device has an access right to the extended block including the target block for the shared memory access, then the target block of the shared memory is accessed without cache coherence control at other nodes; and if the node does not have the access right to the extended block, the cache coherence control at other nodes is performed, and when necessary, the target block of the shared memory is accessed.