Patent ID: 6984534
Filing Date: 2006-01-10
Classification: G11C

Abstract:
1. A method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, comprising: providing a wafer with at least one scribe and at least one memory area; forming a plurality of memory cells in the memory area and at least one test device in the scribe line simultaneously, wherein the memory area has bit line contacts and active areas, the test device including: detecting a first resistance by the first terminal of the bit line and one of the two plugs; detecting a second resistance by the second terminal of the bit line and the other of the two plugs; determining whether the alignment of the bit line and the bar-type active area of the test device is normal according to the first resistance and the second resistance; and determining whether the alignment of the bit line contacts and the active areas in the memory areas is normal according to whether the alignment of the bit line contact and bar-type active area of the test device.