Patent ID: 6646947
Filing Date: 2003-11-11
Classification: G06F

Abstract:
A data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command and data transfer start addresses and a data transfer completion address of the first and second memory arrays, the device comprising:a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer start addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section; and a first comparison target address switch section for performing a switching operation from a memory address targeted for comparison with the data transfer completion address to a memory address corresponding to either the first or second memory arrays so as to detect the completion of the data transfer based on the input control command, wherein the mutual data transfer between the first and second memory arrays is performed based on sequentially-incremented address values of the first and second memory address storage sections.