Patent ID: 7719100
Filing Date: 2010-05-18
Classification: H01L

Abstract:
1. A semiconductor module comprising: a substrate having a main surface on which a wiring pattern including a first conductive film and a second conductive film is formed, a semiconductor element electrically connected with said first conductive film and mounted on the main surface of said substrate, and a lead electrically connecting said second conductive film and said semiconductor element, wherein said lead is disposed so that its main surface faces the main surface of said substrate, wherein the main surface of said lead includes a first region which faces a main surface of said semiconductor element in its opposite side with the main surface of said substrate and a second region facing said second conductive film, wherein an electrode soldered to said first region of said main surface of said lead is formed in said main surface of said semiconductor element, wherein said first region of said main surface of said lead extends in a first direction from one of ends thereof near said second region to another of ends thereof far from said second region, wherein the first width of at least a part of said first region of said main surface of said lead along the second direction transverse to said first direction is greater than or equal to the second width of said electrode soldered to said first region along said second direction, wherein said electrode formed in said main surface of said semiconductor element comprises a plurality of conductive layers juxtaposed in said second direction from one to another of both ends of said main surface facing each other in said second direction, and wherein said second width of said electrode is defined as the distance between a side of a first conductive layer positioned on said one end of the main surface of said semiconductor element and a side of a second conductive layer positioned on said another end of the main surface of said semiconductor element, when one of said plurality of conductive layers being nearest to said one end of said main surface of said semiconductor element is taken as the first conductive layer, while the other one of a plurality of conductive layers being nearest to said other end of said main surface of said semiconductor element is taken as the second conductive layer.