Patent ID: 7148544
Filing Date: 2006-12-12
Classification: H01L

Abstract:
1. A semiconductor-on-insulator construction, comprising: a substrate; an insulator layer over the substrate; a crystalline layer comprising silicon and germanium over the insulator layer; a transistor device supported by the crystalline layer, the transistor device comprising a gate and an active region proximate the gate; the active region including a channel region and a pair of source/drain regions; at least a portion of the active region being within the crystalline layer; an entirety of the active region within the crystalline layer being within a single crystal of the crystalline layer; a resistor in electrical connection with one of the source/drain regions; the resistor comprising p-doped semiconductive material; wherein the p-doped semiconductive material of the resistor comprises at least two stacked layers of p-doped semiconductive material; and wherein at least one of the stacked layers consists of a p-type doped mixture of Si and Ge.