Patent ID: 7425755
Filing Date: 2008-09-16
Classification: H01L,H05K

Abstract:
1. A semiconductor package, comprising: a semiconductor chip having an active area and a plurality of bonding pads in the active area; a plurality of leads disposed in the periphery of the semiconductor chip, which each lead has a first portion, a second portion and opposing upper and lower surfaces, wherein the second portion of the lead curves upwards upwards and the upper surfaces of the second portions of the leads face the semiconductor chip; a die pad seperated from and coplanar with the first portions of the leads to carry the semiconductor chip; a plurality of protrusions disposed on the lower surfaces of the second portions of the leads; a plurality of bonding wires having seperate one ends connecting to the bonding pads of the semiconductor chip and the seperate other ends physically connecting to the first portions of the leads; and a package body enclosing the semiconductor chip, substantially overall surfaces of the protrusions and the leads, wherein the leads are substantially embedded in the package body with the lower surfaces of the leads exposed outside of the package body.