Patent ID: 7414429
Filing Date: 2008-08-19
Classification: H03K

Abstract:
1. A programmable logic device comprising: logic array circuitry; high-speed serial interface circuitry along a first side of the logic array circuitry; and peripheral IO circuitry along at least one of three remaining sides of the logic array circuitry, wherein the high-speed serial interface circuitry comprises at least one group of plural channels of high-speed transceiver circuitry, each of the channels providing an interface between a high-speed serial data signal external to the device and a plurality of parallel data signals in the logic array circuitry, wherein the logic array circuitry comprises a plurality of rows of blocks of programmable logic, each of the rows also including a plurality of interconnection conductors that can be used for making connections between the blocks in that row, and wherein each of the channels interfaces with the interconnection conductors conveying the parallel data signals in a respective at least one of the rows.