Patent ID: 6429693
Filing Date: 2002-08-06
Classification: H03L

Abstract:
A digital fractional phase detector comprising:a time-to-digital converter (TDC) having a plurality of delay elements associated with a first input and a plurality of latch/register elements associated wit both a second input and a plurality of outputs, wherein the fist input is configured to receive a first clock signal, and further wherein the second input is configured to receive a reference clock signal such that the plurality of latch/register elements store a snapshot of a delayed replica vector of first clock signal data in response to significant edge transitions associated with the reference clock signal; and a digital edge detector having a plurality of inputs in communication with the plurality of outputs, and fixer having first and second outputs, wherein the edge detector is responsive to the delayed replica vector of first clock data such that the fist output generates a TDC rse-time signal associated with timing of a positive transition of the first clock signal and further wherein the edge detector is responsive to the stream of first clock state data such that the second output generates a TDC fall-dine signal associated with timing of a negative transition of the fist clock signal.