Patent ID: 6249469
Filing Date: 2001-06-19
Classification: G11C

Abstract:
A sense amplifier arrangement for an integrated circuit memory comprising:a plurality of sense amplifiers, each containing a respective latch circuit having internal nodes to which corresponding bit lines are coupled, each said latch circuit including a pair of P channel transistors and a pair of N channel transistors, wherein said plurality of sense amplifiers corresponds to a plurality of bit line pairs within the memory;a plurality of first and second local sense amplifier drive transistors coupled so that each said sense amplifier latch circuit is connected to respective first and second local sense amplifier drive transistors, wherein each said first local sense amplifier drive transistor is coupled to the source-drain path of the P channel transistors of the corresponding sense amplifier latch circuit, and wherein each said second local sense amplifier drive transistor is coupled to the source-drain paths of the N channel transistors of the corresponding sense amplifier latch circuit;each of said local sense amplifier drive transistors being coupled to provide selectively a respective voltage signal to the corresponding pair of transistors within said corresponding latch circuit;wherein a first plurality of said first local sense amplifier drive transistors is responsively coupled to a first control signal line for the P channel transistors, and a second plurality of said second local sense amplifier drive transistors is coupled to a second control signal line for the N channel transistors;a plurality of column read amplifiers corresponding to said plurality of sense amplifiers; anda plurality of data read lines;each said column read amplifier being responsively coupled to at least one of said internal nodes of the latch circuit of the corresponding sense amplifier, each said column read amplifier being coupled to at least one said data read line.