Patent ID: 7350169
Filing Date: 2008-03-25
Classification: G06F

Abstract:
1. A method for performing verification of an electronic design, said method comprising: receiving a design, wherein said design includes a first target set and a first register set comprising one or more registers; forming a structural product extraction from one or more targets from said first target set; first recursing said structural product extraction for one or more next-state functions of a subset of said one or more registers; second recursing a sum-of-products form from said structural product extraction for one or more next-state functions of a subset of said one or more registers; decomposing a product-of-sums form of a result of said second recursing to generate a decomposition of said product-of-sums form; synthesizing said decomposition of said product-of-sums form into a second target set; choosing a subset of said second target set to recursively decompose; in response to said subset of said second target set being nonempty, recursively decomposing said first target set; and in response to said second target set being empty, applying verification to said second target set.