Patent ID: 8772830
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A semiconductor wafer comprising: an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is epitaxially crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is epitaxially crystal-grown on the buffer layer, wherein the functional layer is an element formation layer that is a group 3-5 compound layer or a group 2-6 compound layer that lattice matches or pseudo-lattice matches with Ge, and the element formation layer has an arithmetic mean roughness value of no greater than 0.02 μm.