Patent ID: 7733987
Filing Date: 2010-06-08
Classification: H03L

Abstract:
1. A clock signal reproduction device, comprising: an output clock oscillating section which generates an output clock signal and shifts a phase of the output clock signal in a direction indicated by an output clock control signal supplied thereto; an internal clock oscillating section which generates an internal clock signal; a first data temporal lead/lag detecting section which acquires a data signal and the output clock signal, detects a time lag or a time lead of a phase of the data signal with respect to the output clock signal, and generates a first temporal lead/lag detection signal representing a result of detection; an output clock control section which acquires the first temporal lead/lag detection signal, measures a cumulated amount of the time lead or the time lag based on the first temporal lead/lag detection signal, and when the cumulated amount reaches a first predetermined value, generates the output clock control signal, which instructs that the phase of the output clock signal should be shifted in a direction to cancel occurrence of the time lag or the time lead which has reached the cumulated amount, supplies the generated output clock control signal to said output clock oscillating section, and newly starts measuring; an inter-clock phase difference detecting section which acquires the output clock signal and the internal clock signal, detects a phase difference between the output clock signal and the internal clock signal, and generates an inter-clock phase difference signal representing the detected phase difference, wherein said output clock control section further acquires the inter-clock phase difference signal, and stops generating the output clock control signal while an amount of the phase difference represented by the inter-clock phase difference signal is being a predetermined amount, and wherein said internal clock oscillating section comprises a section which shifts a phase of the internal clock signal in a direction indicated by an internal clock control signal supplied to said section; a second data temporal lead/lag detecting section which acquires the data signal and the internal clock signal, detects a time lag or a time lead of the phase of the data signal with respect to the internal clock signal, and generates a second temporal lead/lag detection signal representing a result of detection; and an internal clock control section which acquires the second temporal lead/lag detection signal, measures a cumulated amount of the time lag or the time lead based on the second temporal lead/lag detection signal, and when the cumulated amount reaches a second predetermined value larger than the first predetermined value, generates the internal clock control signal, which instructs that the phase of the internal clock signal should be shifted in a direction to cancel occurrence of the time lag or the time lead which has reached the cumulated amount, supplies the generated internal clock control signal to said internal clock oscillating section, and newly starts measuring.