Patent ID: 7785951
Filing Date: 2010-08-31
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, comprising: forming first, second and third gate electrodes on a semiconductor substrate; forming a first stress film that covers the first gate electrode and at least a first portion of the third gate electrode, said first stress film having a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode; forming an etch stop film that conforms to the first stress film and contacts a portion of the first stress film extending opposite a sidewall of the third gate electrode; and forming a second stress film that covers the second gate electrode and at least a second portion of the third gate electrode, said second stress film having a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode and having an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.