Patent ID: 6794237
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A method of fabricating a heterojunction bipolar transistor in a single-crystal silicon layer overlying an insulator layer, comprising the steps of:doping at least a portion of the silicon layer to form a collector region; forming an insulator layer over the silicon layer; etching an emitter opening through a portion of the insulator layer; then forming a first polysilicon layer over the insulator layer, the first polysilicon layer extending over the edge of the etched insulator layer into the emitter opening to contact the silicon layer, and extending over the insulator layer and an underlying portion of the collector region; anisotropically etching the first polysilicon layer to define a base electrode having a base link filament adjacent the edge of the etched insulator layer, the base link filament contacting the silicon layer; forming an insulator filament adjacent to the base link filament and contacting the silicon layer; etching through the silicon layer to the insulating layer, using the insulator filament as a mask to define an edge of the silicon layer; implanting heterojunction species into the edge of the silicon layer to form a heterojunction base region; forming an intrinsic emitter region at the implanted edge of the silicon layer and adjacent to the heterojunction base region; forming an emitter plug adjacent to the intrinsic emitter region; and forming a collector plug adjacent to the collector region.