Patent ID: 7864581
Filing Date: 2011-01-04
Classification: G11C

Abstract:
1. A method for recovery of a NAND flash memory device, the NAND flash memory device including a semiconductor substrate; a plurality of cell blocks, each of the cell blocks having a plurality of cell strings formed on the semiconductor substrate, each of the cell strings comprising a plurality of cells coupled in series; a drain select transistor formed between a cell string and a bit line of each of the plurality of the cell blocks; and a source select transistor formed between a cell string and a source region; the method comprising: erasing the NAND flash memory device; applying a first predetermined bias to each bit line of the plurality of cell blocks after erasing the NAND flash memory device, wherein the first predetermined bias is higher than 0V; applying a second predetermined bias to a drain select line of the drain select transistor of a selected cell block after erasing the NAND flash memory device, wherein the second predetermined bias is higher than 0V; applying a third predetermined bias to a source select line of the source select transistor of the selected cell block after erasing the NAND flash memory device, wherein the third predetermined bias is higher than 0V; applying a zero voltage to the source region after erasing the NAND flash memory device; and applying a fourth predetermined bias to cell gates of the selected cell block after erasing the NAND flash memory device, wherein the fourth predetermined bias is controlled according to a variation in a target threshold voltage of the selected of cell block, wherein the first predetermined bias, the second predetermined bias, the third predetermined bias, the zero voltage applied to the source region, and the fourth predetermined bias are applied so as to share a common time period of application.