Patent ID: 7746770
Filing Date: 2010-06-29
Classification: H04J,H04L

Abstract:
1. A method of controlling a jitter buffer using a FIFO, a packet deletion circuit, a packet addition circuit, and a jitter buffer control circuit, comprising the steps of: setting a packet delete area, a packet add area, and a clock control area inside the FIFO; controlling a stored packet quantity of the FIFO to delete a specified packet from an input side of the FIFO when the stored packet quantity exceeds a lower limit of the packet delete area, and to delete the packets when the stored packet quantity exceeds an upper limit of the packet delete area; controlling the stored packet quantity of the FIFO to add a specified packet when the stored packet quantity falls below an upper limit of the packet add area, and to add the packets when the stored packet quantity falls below a lower limit of the packet add area; raising a clock frequency when the stored packet quantity of the FIFO reaches an upper limit of the clock control area; lowering the clock frequency when the stored packet quantity of the FIFO reaches a lower limit of the clock control area; and setting the clock control area between the packet add area and the packet delete area.