Patent ID: 7723807
Filing Date: 2010-05-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: at least two adjacent memory cell blocks, each of said memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series; a plurality of cell gates for selecting said plurality of memory cells within said two adjacent memory cell blocks, each of said plurality of cell gates being formed with roughly U shaped open loops, each of said loops being connected to a corresponding cell of said memory cells in a corresponding memory cell unit of said plurality of memory cell units within one of said two adjacent memory cell blocks and being connected to a corresponding memory cell of said memory cells in a corresponding memory cell unit of said plurality of memory cell units within the other memory cell block of said two adjacent memory cell blocks; and a plurality of pairs of first and second selection gates for selecting said memory cell block, said plurality of cell gates being located between one pair of said first and second selection gates within a corresponding block of said memory cell block.