Patent ID: 7245025
Filing Date: 2007-07-17
Classification: H01L

Abstract:
1. A structure, comprising: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene or dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of said last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in physical and electrical contact with a top surface of said last damascene or dual-damascene wire, said last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of said last interlevel dielectric level; and an aluminum pad having a bottom surface, a top surface and sidewalls connecting said top and bottom surfaces, said bottom surface of said aluminum pad in physical and electrical contact with said capping layer, said top surface of said aluminum pad coplanar with a top surface of said dielectric passivation layer, said dielectric passivation layer in direct contact with said sidewalls of said aluminum pad.