Patent ID: 6097633
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A read circuit for non-volatile memories, comprising:an array section, with a corresponding bitline, and a reference section, with a corresponding reference bitline;a differential amplifier for comparing voltage signals obtained by current/voltage conversion of a respective current signal of an array cell and of a reference current signal;a cascode transistor for each one of said array and reference sections, each driven by a logic gate;a charge transistor for said bitline and a charge transistor for said reference bitline;column decoding transistors for said array section and for said reference section; andan additional transistor which is connected between said logic gate of the array section and a node for acquiring said array voltage signal sent to said differential amplifier for comparison with the reference voltage converted current signal, said additional transistor increasing the speed of the process for reading said bitline when said bitline is not charged.