Patent ID: 7231506
Filing Date: 2007-06-12
Classification: G06F

Abstract:
1. A microprocessor adopting a VLIW method in which a plurality of instructions contained in a single VLIW instruction are executed in parallel, comprising: a translation lookaside buffer having a plurality of entries in which address translation information is registered, the address translation information being obtained by translating a virtual address into a physical address, said translation lookaside buffer adopts a 2-way set associative method; a control circuit controlling said translation lookaside buffer; and a detection circuit detecting occurrence of continuous entry substitution requests under a single VLIW instruction, said control circuit chooses as a subject of entry substitution an entry that has been previously referred to, irrespective of states of the priority bits, when said detection circuit detects the occurrence of continuous entry substitution requests under a single VLIW instruction, wherein: each of the entries has a priority bit that is set when the registered address translation information is needed to be resident in the entries; and at the time an entry substitution request occurs while priority bits of all of the entries are in a set state, said control circuit chooses as a subject of entry substitution an entry that has been least recently referred to, irrespective of states of the priority bits, the entry substitution being for substituting the registered address information in the entries and at the time the entry substitution request occurs while a priority bit in at least one of the entries is in a reset state, said control circuit chooses as a subject of entry substitution an entry that has been least recently referred to from the at least one of the entries.