Patent ID: 8482992
Filing Date: 2013-07-09
Classification: G11C

Abstract:
1. A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM), the method comprising steps of: providing an external clock signal to a phase detector of the DLL; comparing the external clock signal with a feedback clock signal by using the phase detector, wherein the feedback clock signal is received from an output buffer of the DLL; generating a first control signal according to a result of the comparison of the external clock signal and the feedback clock signal; adjusting a delay of a delay line circuit of the DLL based on the first control signal, wherein the delay line circuit is coupled between the phase detector and the output buffer to receive and delay the external clock signal; and detecting variations of the first control signal to determine a length of an enable period of an enable signal, wherein the delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode.