Patent ID: 7269239
Filing Date: 2007-09-11
Classification: G06F

Abstract:
1. A two-wire communication protocol between a controller device and a controlled device, both devices being coupled by a clock line and a data line, said controller device sending control signals comprising N bits, N being greater than or equal to two, to the controlled device via the data line, wherein the bits of said control signals are latched onto the controlled device on consecutive edges of a clock signal sent by the controller device to the controlled device on the clock line, wherein after at least one of the N-1 first bits of a control signal has been latched onto the controlled device, the data line is temporarily set by the controller device in high impedance state during which a first acknowledgement data bit, which acknowledges whether the execution of an instruction corresponding to an anticipated control signal is possible or not, is generated by the controlled device, wherein the number N of bits of a control signal is greater than or equal to 2, which allows four control signals, said acknowledgement data bit being generated after the first bit of a control signal has been latched, and wherein said controlled device is an electronic device with a digitally adjustable quantity which comprises a counter storing a value of the digitally adjustable quantity, and wherein said four control signals include at least an increment signal and a decrement signal of said value.