Patent ID: 8117474
Filing Date: 2012-02-14
Classification: G06F,Y02D

Abstract:
1. A clock control device, comprising: an address information detecting section for detecting access to a main storage device from a central processing unit and detecting address information indicating an accessing address in the main storage device; a cache miss detecting section for detecting the occurrence of a cache miss in a cache device arranged between the central processing unit and the main storage device; a cache data detecting section for detecting the storage of data in the cache device; a stall notifying section for notifying the start and end of a memory stall indicating access to the main storage device based on the address information detected by the address information detecting section, a detection result in the cache miss detecting section and a detection result in the cache data detecting section; an instruction detecting section for detecting whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction; a clock switch judging section for receiving the notification of the start and end of the memory stall from the stall notifying section, determining whether or not a memory stall is occurring and judging whether to switch a clock signal to be supplied to the central processing unit to a low clock signal or to stop the clock signal based on a detection result of the instruction detecting section if it is determined that the memory stall is occurring; and a clock switching section for switching the clock signal based on judgment by the clock switch judging section.