Patent ID: 6277677
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:sequentially forming a gate oxide layer, a gate and a mask insulation layer on a semiconductor substrate;sequentially forming first and second insulation layers on a resulting structure after forming said mask insulation layer;forming a first spacer on a side wall of said gate and said mask insulation layer having said first insulation layer by etching said second insulation layer;etching said first insulation layer so that an undercut is formed and said substrate of both sides of said first spacer and surface of said mask insulation layer are exposed, whereby a second spacer is formed on side wall of said gate and mask insulation layer;forming an epitaxial silicon layer on said exposed substrate; andforming elevated source and drain regions in said substrate by implanting an impurity ion through said epitaxial silicon layer and by performing an annealing process,wherein the source and drain regions are formed such that they are separated from the gate by the first and second spacers.