Patent ID: 7834672
Filing Date: 2010-11-16
Classification: H03L

Abstract:
1. A circuit operative to control current flow at an output node, comprising: a first path configured to supply current to the output node, the first path comprising: a first switch responsive to a first control signal; a first current source coupled to the first switch at a first node and responsive to a second control signal; and a second switch coupled between the first node and the output node, wherein a timing of the first control signal and the second control signal are related so as to define a first operating interval in which the first switch conducts a current corresponding to the first current source and a second operating interval in which the first switch conducts a current absent the current corresponding to the first current source; a second path configured to receive current from the output node, the second path comprising: a third switch responsive to a third control signal; a second current source coupled to the third switch at a second node and responsive to a fourth control signal; and a fourth switch coupled between the second node and the output node, wherein a timing of the third control signal and the fourth control signal are related so as to define a third operating interval in which the third switch conducts a current corresponding to the second current source and a fourth operating interval in which the third switch conducts a current absent the current corresponding to the second current source; a first delay line configured to receive a first input signal and to produce the second control signal by delaying the first input signal for a first predetermined time, wherein a duration of the first operating interval is less than the first predetermined time.