Patent ID: 6694410
Filing Date: 2004-02-17
Classification: G06F

Abstract:
Apparatus for managing transactions between a plurality of memory access devices and a shared memory having an input queue, comprising:an address and data controller coupled to the memory access devices and the shared memory, the address and data controller coupling transaction request control signals and data from the memory access devices to the shared memory; and an identification memory coupled to the memory access devices, the shared memory and the address and data controller, the identification memory storing an identifier for each memory access device in the order in which transaction requests from the memory access devices are transmitted to the shared memory; upon completion of a transaction request, the shared memory providing transaction completion information to the address and data controller and the identification memory; the identification memory providing, in the order in which they were stored, one of the stored identifiers to the address and data controller each time that the identification memory receives transaction completion information from the shared memory; and the address and data controller providing the transaction completion information received from the shared memory to the memory device associated with the identifier provided by the identification memory.