Patent ID: 7515480
Filing Date: 2009-04-07
Classification: G11C

Abstract:
1. A writing method of a nonvolatile semiconductor memory device, which comprises a memory cell array including nonvolatile semiconductor memory cells arranged in a matrix in a row and column directions having a memory function unit capable of accumulating an electric charge and a MOSFET structure capable of controlling a memory cell current flowing through between a drain and a source depending on sizes of the electric charges accumulated in the memory function unit and a memory cell array configuration in which each drain of the memory cells arranged on the same column is connected to a common first bit line made of a metal wire via a second bit line having a higher resistance than that of the metal wire and a bit line contact to connect the first bit line to the second bit line electrically, and the shortest distance from each drain of the memory cells to the bit line contact varies in accordance with a location of the memory cell in the column direction, the writing method including a writing operation which is carried out sequentially from the memory cell arranged at the nearest position to the bit line contact, in the case of continuously carrying out the writing operation to control the accumulated electric charge amount of the memory function unit so that the memory cell current is made small for all or some of the memory cells on the same column arranged between the two adjacent bit line contacts in the column direction.