Patent ID: 6087879
Filing Date: 2000-07-11
Classification: H03K

Abstract:
A semiconductor integrated circuit device comprising:an input buffer having a latch circuit that receives an input signal inputted in synchronization with a clock signal and provided with high and low levels, wherein the voltage difference between the high and low levels has a first amplitude smaller than the difference between a first and a second supply voltage of the semiconductor integrated circuit device and wherein the latch circuit holds a signal corresponding to the received input signal as a latched signal with second high and low levels wherein the voltage difference between the second high and low levels has a second amplitude smaller than the difference between the first and second supply voltage, wherein said input buffer includes:differential MOSFETs of a first conductivity type for receiving said input signal and a reference voltage;a first switch MOSFET of the first conductivity type which is provided between said first supply voltage and a common source of said differential MOSFETs and which is turned on when the clock signal entered in synchronization with said input signal is at a first level;load elements provided between the respective drains of said differential MOSFET and said second supply voltage;the latch circuit including latch-type MOSFETs of the first conductivity type with gates and drains thereof interconnected in a cross-coupled manner, the drains of the latch-type MOSFETs being connected to the drains of said differential MOSFETs, respectively;a second switch MOSFET of the first conductivity type which is provided between said first supply voltage and sources of said latch-type MOSFETs, respectively, and which is turned on when said clock signal is at a second level; andan amplifying circuit which amplifies the latched signal with the second high and low levels to form an internal signal having a signal amplitude corresponding to said first supply voltage and said second supply voltage.