Patent ID: 7323741
Filing Date: 2008-01-29
Classification: G11C,H01L

Abstract:
1. A semiconductor nonvolatile memory device comprising: a first, second and fourth electrode mutually wired in parallel in a first direction formed on a semiconductor surface via an insulating film; a fifth electrode for controlling the voltage potential on the semiconductor surface between the first electrode and the second electrode, as well as between the second electrode and the fourth electrode, and the fifth electrode being wired in the second direction substantially perpendicular to the first direction; a first charge holding region for holding an electrical charge enclosed by the insulation film on the periphery between the first electrode and the second electrode; and a second charge holding region for holding an electrical charge enclosed by the insulation film on the periphery between the second electrode and the fourth electrode, wherein, in a write operation, the first electrode is supplied with a voltage potential A so as to form a first inversion layer in a vicinity of the semiconductor surface and the first inversion layer is supplied with a voltage potential B lower than the voltage potential A, wherein, in the write operation, the fourth electrode is supplied with a voltage potential C so as to form a second inversion layer in a state with a voltage potential D which is lower than the voltage potential C and higher than the voltage potential B due to coupling between the fourth electrode and the semiconductor surface in a floating state in the vicinity of the fourth electrode, wherein, in the write operation, the second electrode is supplied with a voltage potential E lower than the voltage potential A, wherein, in the write operation, the fifth electrode is supplied with a voltage potential F higher than voltage potential C, and wherein, in the write operation, the second charge holding region is injected with hot electrons generated at a semiconductor surface between the second and fourth electrodes due to discharge of electrons accumulated on the second inversion layer to the first inversion layer through a semiconductor surface under the second charge holding region, the second electrode, and the first charge holding region.