Patent ID: 6516439
Filing Date: 2003-02-04
Classification: H03M

Abstract:
An error control circuit including:a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes and to be interleaved in accordance with a predetermined interleave order; a first cyclic code checking circuit for receiving an output of said deinterleaver and conducting a cyclic code check on said data of the predetermined number of bits by a check system corresponding to a coding system of said cyclic code; and a second cyclic code checking circuit for receiving an output of said deinterleaver and conducting a cyclic code check on said data of the predetermined number of bits by a check system corresponding to the coding system of said cyclic code simultaneously with the cyclic code check by said first cyclic code checking circuit in substantially the same time while canceling an interleave effect by said deinterleaver.