Patent ID: 6596588
Filing Date: 2003-07-22
Classification: H01L

Abstract:
A method of fabricating a flash memory cell to that utilizes point discharge to reduce the an operation voltage of erasing, the method comprising:providing a semiconductor substrate; performing an etching process to remove portions of the semiconductor substrate to form at least one V-shape structure in the semiconductor substrate; performing a first ion implantation process to form a first doping region around the V-shape structure; forming a first dielectric layer on the surfaces of the semiconductor substrate and the first doping region; forming a floating gate on the first dielectric layer over the first doping region; forming a second dielectric layer on the floating gate; forming a controlling gate on the second dielectric layer, a side of the controlling gate being positioned on the semiconductor substrate adjacent to the floating gate; and performing a second ion implantation process ustilizing the controlling gate as a mask to form at least one a second doping region in the semiconductor substrate.