Patent ID: 7443031
Filing Date: 2008-10-28
Classification: H01L

Abstract:
1. A wiring structure of a semiconductor device comprising: a wiring layer having an upper surface and a lower surface; an upper plug formed in a first insulating layer above the upper surface of the wiring layer; a lower plug formed in a second insulating layer below the lower surface of the wiring layer and opposite to the upper plug with the wiring layer interposed; and at least one cap layer interposed between the wiring layer and any one of the upper plug and the lower plug and positioned below any one of a plane defined by a substantial portion of the upper surface and a plane defined by a substantial portion of the lower surface, respectively, wherein sizes of grains in a first region of the wiring layer between the upper plug and the lower plug are substantially equal to sizes of grains in a second region laterally adjacent to the first region between the first insulating layer and the second insulating layer.