Patent ID: 8716787
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A fabrication method of a power semiconductor device, comprising the steps of: providing a base; forming a plurality of gate structures; forming a pattern layer on the base by using a body mask, the pattern layer having at least a first open and at least a second open for forming at least a body region and at least a heavily doped termination structure in the base respectively, and an open width of the first open being wider than that of the second open; forming a shielding structure on the base, which fills the second open and covers a portion of a bottom of the first open adjacent to a sidewall thereof; forming a plurality of source doped regions by using an implantation mask composed of the pattern layer and the shielding structure; forming an interlayer dielectric layer on the base; forming a plurality of source contact windows penetrating the interlayer dielectric layer to expose the source doped regions; and forming a metal pattern layer on the interlayer dielectric layer to connect the source doped regions.