Patent ID: 6165860
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of, in sequence:(a) partially forming a first conductivity type buried layer in a semiconductor substrate and also forming a first conductivity type epitaxial layer on said buried layer;(b) forming a collector region in said epitaxial layer by selectively introducing first conductivity type impurities into said epitaxial layer so that said collector region reaches said buried layer;(c) forming an insulating film on said epitaxial layer;(d) forming a second conductivity type impurities doped polysilicon film on said insulating film;(e) patterning said polysilicon film to form a base electrode;(f) forming an interlayer insulating film over said base electrode and said insulating film;(g) patterning both said interlayer insulating film and said base electrode to form a base opening at a region at which a base region is to be formed and a collector opening above said collector region;(h) side-etching portions of said insulating film located below said base electrode to form undercut hollow portions in said insulating film;(i) filling said undercut hollow portions with polysilicon;(j) forming a base region in said epitaxial layer by introducing second conductivity type impurities into said epitaxial layer through said base opening;(k) forming insulating sidewalls on inner walls of said base and collector openings;(l) forming a second conductivity type impurities doped polysilicon film over a resultant; and(m) patterning said second conductivity type impurities doped polysilicon film to form both an emitter electrode and said collector electrode.