Patent ID: 8446016
Filing Date: 2013-05-21
Classification: H01L

Abstract:
1. A chip stack package comprising a plurality of chips that are stacked, and further comprising: a first chip of the plurality of chips, the first chip having an upper surface and a lower surface; a first through via electrode formed through at least a first portion of the first chip, at least a portion of the first through via electrode being exposed to the outside of the first chip at at least one surface of the first chip; and a second through via electrode formed through at least the first portion of the first chip, at least a portion of the second through via electrode being exposed to the outside of the first chip at at least one surface of the first chip, wherein at the first portion of the first chip, the first through via electrode is formed of a first material and the second through via electrode is formed of a second material different from the first material and does not include the first material.