Patent ID: 6768678
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A memory cell circuit comprising:a first memory cell for storing a non-volatile first data to generate a first current according to the first data when the memory cell circuit is in a read mode; a second memory cell for storing a non-volatile second data to receive a second current according to the second data when the memory cell circuit is in the read mode; a biasing circuit electrically connected to the first and the second memory cell for receiving the first current from the first memory cell and transmitting the second current to the second memory cell when the memory cell circuit is in the read mode; and an amplifying circuit electrically connected to a loading node of the biasing circuit for sensing a loading voltage when charging or discharging the loading node using a difference of the first and the second currents, and transmitting and amplifying the loading voltage to generate an output signal corresponding to the first data.