Patent ID: 6320807
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A random access memory device, comprising:a memory array having a plurality of columns, each column including a plurality of memory cells and a first bitline;a precharge line to connect the first bitline of each column to a voltage source to precharge at least a portion of the memory cells in the column before a read operation;at least one pass device connected to the first bitline of each column, the pass device dividing the memory cells into a first section on one side of the pass device and a second section on an opposite side of the pass device; andcontrol logic to open the pass device during the read operation if a memory cell in the first section is accessed so that memory cells in the first section are discharged and memory cells in the second section are not discharged during the read operation, and to close the pass device during the read operation if a memory cell in the second section is accessed so that memory cells in both the first and second sections are discharged during the read operation.