Patent ID: 8132169
Filing Date: 2012-03-06
Classification: G06F

Abstract:
1. A computer implemented method comprising: compiling a source code program into a logical program partition that includes a plurality of binary representations that are each executable code, wherein one or more of the plurality of binary representations are compiled to execute on one or more general purpose processors utilizing a first instruction set architecture (ISA) and wherein one or more of the plurality of binary representations are compiled to execute on one or more types of application specific processors that utilize one or more second ISAs; including one or more sets of acceptable performance threshold data corresponding to one or more of the binary representations in the logical program partition; packaging the logical program partition and an execution monitor into a logical program package; initiating execution of the logical program package on one of the general purpose processors, the initiating including: determining, by the execution monitor, that the performance of the first binary representation has fallen below the acceptable performance threshold data corresponding to the first binary representation; in response to the determination, selecting a second binary representation from the plurality of binary representations that has been compiled to execute on one of the application specific processors; and executing the second binary representation on one of the application specific processors.