Patent ID: 6803281
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a gate lead-out region and a MISFET-forming region, comprising the steps of:forming a trench in said MISFET-forming region of a major surface of a semiconductor substrate; forming a gate insulating film of a MISFET in said trench; forming a conductive film over an entire area of said major surface of said substrate such that said trench is filled by said conductive film through said gate insulating film and such that said conductive film is formed over a gate lead-out region of said major surface of said substrate; and selectively etching said conductive film to form a gate electrode in said trench and to form a gate lead-out electrode over said gate lead-out region such that said gate lead-out electrode is integrally formed with said gate electrode, wherein the top surface of said gate electrode is lower than the top surface of said semiconductor substrate in said gate lead-out region.