Patent ID: 6986131
Filing Date: 2006-01-10
Classification: G06F

Abstract:
1. A computer-implemented method of efficient code generation for modulo scheduled uncounted loops, the method comprising: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; using the given stage predicate to conditionally enable or disable the execution of an instruction during a prologue excecution and an epilogue execution; executing a first compare instruction inside an uncounted loop to determine if a new iteration of the uncounted loop is to be prevented; if a new iteration of the uncounted loop is to be prevented, then setting a static predicate to a value one, wherein the static predicate is in a kernel which is a code corresponding a steady state portion of a record of execution and wherein the static predicate guards a second compare instruction; and when the static predicate is set to the value one, executing the second compare instruction to terminate any subsequent iteration of the uncounted loop.