Patent ID: 9053789
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A resistive switching memory device, comprising: a) a plurality of resistive memory cells, wherein each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage, and to be erased to a high resistance state by application of a second voltage; b) a detector configured to detect when at least one of the plurality of resistive switching memory cells is to be rendered inoperable; c) a program controller configured to render the at least one resistive switching memory cell inoperable by application of a third voltage during a program operation, wherein the third voltage is greater in absolute value than the first voltage, and wherein the at least one resistive switching memory cell rendered inoperable remains in the low resistance state after subsequent erase operations; and d) an erase controller configured to render the at least one resistive switching memory cell inoperable by application of a fourth voltage during an erase operation, wherein the fourth voltage is greater in absolute value than the second voltage, and wherein the at least one resistive switching memory cell rendered inoperable remains in the high resistance state after subsequent program operations.