Patent ID: 9075110
Filing Date: 2015-07-07
Classification: G01R

Abstract:
1. A fault detection system configured to detect a fault in a logic circuit based on a plurality of output logic values output from the logic circuit after a test input pattern is input, wherein the plurality of output logic values are input to the logic circuit as an updated test input pattern, the fault detection system comprising: a first acquisition unit configured to acquire a part of or otherwise all of the plurality of output logic values; a comparison unit configured to compare an output logic value acquired by the first acquisition unit with an output logic value expected when no fault is present in the logic circuit or otherwise an output logic value expected when a fault is present in the logic circuit; and a fault judgment unit configured to judge whether or not there is a specific fault in the logic circuit, based on a comparison result obtained by the comparison unit, wherein the plurality of output logic values are held by a holding unit comprising a plurality of individual holding units each configured to hold a single logic value, and wherein the first acquisition unit is configured to acquire a part of or otherwise all of the plurality of output logic values held by the holding unit, and wherein a part of or otherwise all of the output logic values respectively held by the plurality of individual holding units are acquired directly such that each output logic value is acquired from the corresponding individual holding unit without passing through the other individual holding units, the fault detection system further comprising a second acquisition unit configured to acquire a part of or otherwise all of the plurality of output logic values respectively held by the plurality of individual holding units via a different individual holding unit, wherein the comparison unit is configured to compare the output logic value acquired by the second acquisition unit with an output logic value expected when no fault is present in the logic circuit or otherwise an output logic value expected when a specific fault is present in the logic circuit, and wherein a number of times the first acquisition unit acquires the output logic value is greater than a number of times the second acquisition unit acquires the output logic value.