Patent ID: 7701461
Filing Date: 2010-04-20
Classification: G06F,G06T

Abstract:
1. A method of coordinating between graphics hardware and a processor to control the flow and processing of graphics data, comprising: writing first frame graphics commands and second frame graphics commands into a FIFO buffer; writing a break point specifying a variable location where the first frame graphics commands end within the FIFO buffer and said second frame graphics commands begin; reading said first frame graphics commands from the FIFO buffer in sequence and processing said first frame graphics commands to render first frame graphics into an embedded frame buffer memory; suspending reading of graphics commands from the FIFO buffer and generating a processor interrupt upon encountering the break point location; after suspending, copying the rendered first frames graphics out of the embedded frame buffer; and then resuming reading of second frame graphics commands from the FIFO buffer to render second frame graphics into said embedded frame buffer memory.