Patent ID: 8704561
Filing Date: 2014-04-22
Classification: H03L

Abstract:
1. A delay locked loop comprising: a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal; and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal, wherein the delay adjusting unit includes: a replica delay unit configured to delay the first clock signal regardless of the delay control signal; a second variable delay line configured to output the second clock signal by delaying an output of the replica delay unit in response to the delay control signal, wherein the replica delay unit provides the output thereof without receiving an input through the second variable delay line; and a delay control unit configured to generate the delay control signal in response to the first clock signal and the second clock signal.