Patent ID: 8868396
Filing Date: 2014-10-21
Classification: G06F

Abstract:
1. A method of verifying and debugging a module of a circuit design, the module including two or more sub-modules, the method comprising: inputting test vectors for the module; simulating on a programmed processor, the module of the circuit design on different simulation models including at least a first simulation model, a second simulation model and a third simulation model of the module, the simulating using the test vectors for input to the module and the module being simulated separately from other modules of the circuit design; wherein the first simulation model is an RTL simulation model, the second simulation model is a post-synthesis simulation model, and the third simulation model is a hardware-in-the-loop simulation model; comparing output from the simulation of the module using the first simulation model, output from the simulation of the module using the second simulation model and output from the simulation of the module using the third simulation model; and in response to a discrepancy between outputs from simulation of the second and third simulation models and no discrepancy between outputs from simulation of the first and second simulation models, storing data indicative of an error in the module and, for each sub-module of the two or more sub-modules contained within the module, using the sub-module as the module repeating the inputting test vectors for the module, simulating the module using only the second and third simulation models, comparing output from simulating only the second and third simulation models, and storing data indicative of results of the comparing.