Patent ID: 7391776
Filing Date: 2008-06-24
Classification: H04L

Abstract:
1. A processor comprising: a first multi-threaded processor engine configured for connection to a serial link; a second multi-threaded processor engine, coupled to the first multi-threaded processor engine by an interface, to process data received by the first multi-threaded processor over the serial link and to provide the processed data to the first multi-threaded processor engine for transmission over the serial link, the second multi-threaded processor engine being capable of operating at a faster rate than the first multi-threaded processor engine; and one or more communication data structures usable by the first and second multi-threaded processor engines to control interaction therebetween, wherein at least one of the one or more communication data structures is usable by the first and second multi-threaded processor engines to control the rate at which the processed data is provided to the first multi-threaded processor engine by the second multi-threaded engine, the at least one or more communication data structures includes a shared memory comprising memory locations corresponding to each of the channels that handles cell data, each memory location storing a count value indicating the number of cells transmitted by the first multi-threaded processor engine for the channel to which such memory location corresponds, the second multi-threaded processor engine being operable to poll the memory locations, wherein the second multi-threaded processor engine, after polling one of the memory locations of a selected one of the channels, is operable to compare the count value with another count value indicative of a number of cells scheduled for transmission, maintained by the second multi-threaded processor engine, to determine a number of cells in flight.