Patent ID: 8975913
Filing Date: 2015-03-10
Classification: G01R,H03K

Abstract:
1. A circuit structure for suppressing single event transients (SETs) or glitches in digital electronic circuits, comprising: a first input which receives an output of a digital electronic circuit; a second input which receives a redundant or duplicated output of the digital electronic circuit; two sub-circuits that each receive the first and second inputs and each have one output; wherein the output of one of the sub-circuits is insensitive to a change in the value of one of the inputs when the inputs are in a first logic state, and wherein the output of the other of the sub-circuits is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state; a two-input multiplexer which receives the outputs of the two sub-circuits as the multiplexer's inputs and selects one of the multiplexer's inputs as its output; wherein the selected multiplexer input is determined by the logic value of the output of the multiplexer and the two sub-circuits are arranged so that the output of the sub-circuit which is insensitive to a change in the value of one of the inputs is selected whenever the output of the multiplexer changes; so that the output of the multiplexer is always insensitive to an SET or glitch in the digital electronic circuit that may result in a temporary change in the logic value of either the first input or the second input; the output of the multiplexer being provided as a final output of the digital electronic circuit in which SETs and glitches have been suppressed.