Patent ID: 6775177
Filing Date: 2004-08-10
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines arranged along the row direction; a plurality of bit line pairs arranged along the column direction; and a decoder for selecting a word line and a bit line pair corresponding to an address signal specifying each of said plurality of memory cells among said plurality of word lines and said plurality of bit line pairs, respectively; wherein in a twin cell mode in which a twin cell mode signal is active, memory data corresponding to 1 bit of memory information represented as binary information is stored by using two memory cells, in a single cell mode in which said twin cell mode signal is inactive, said memory data corresponding to 1 bit of memory information is stored by using one memory cell, in said twin cell mode, said decoder selects the word line and the bit line pair for activating said two memory cells, and said two memory cells store said memory data and an inverted data of said memory data, respectively, said decoder generates an internal row address signal for selecting said word line corresponding to said address signal, and when said twin cell mode signal is activated, simultaneously selects a first word line corresponding to a prescribed bit of said internal row address signal which is at a first logic level, and a second word line corresponding to said prescribed bit which is at a second logic level, said prescribed bit is the least significant bit of said internal row address signal; and said decoder allocates the most significant bit of said address signal which is used in said single cell mode and is not used in said twin cell mode to the least significant bit of said internal row address signal, and allocates the least significant bit of said address signal to the most significant bit of said internal row address signal.