Patent ID: 7242740
Filing Date: 2007-07-10
Classification: H03L,H04J

Abstract:
1. A clock generation system for providing clock synchronization in a switching system wherein several cards are connected to a common backplane data bus, comprising: a primary master clock including a first digital phase locked loop with a loop filter for generating first clock signals from a reference source; a secondary master clock including a second digital phase locked loop with a loop filter for generating second clock signals; and said secondary master clock being operable in either a first mode wherein said secondary master clock is locked to said first clock signals or a second mode wherein said secondary master clock is locked to an alternative reference source; and wherein said loop filter in said secondary master clock is configured to be in a high bandwith mode when said secondary master clock is operating in said first mode and said loop filter in said secondary master clock is configured to be in a low bandwidth mode when said secondary master clock is operating in said second mode; whereby when operating in said first mode said secondary master clock tracks jitter in the clock signals generated by said primary master clock and when operating in said second mode said secondary master clock attenuates jitter from said alternative reference source.