Patent ID: 9165787
Filing Date: 2015-10-20
Classification: G11C,H01L

Abstract:
1. An electronic device comprising a semiconductor memory unit which includes: a substrate; a first interlayer insulating layer formed over the substrate; first and second contact plugs passing through the first interlayer insulating layer and located over the substrate, the first and second contact plugs alternately arranged to have a regular intervals from each other; a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug; a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer, the variable resistance element, the first contact plug and the second contact plug; a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element; a fourth contact plug passing through the second interlayer insulating layer so as to be electrically connected to the second contact plug; and conductive lines coupled to the third contact plug and the fourth contact plug, respectively.