Patent ID: 7085174
Filing Date: 2006-08-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of data write lines provided corresponding to the rows or columns of said plurality of memory cells; a plurality of current drivers receiving a voltage of a first power supply potential and a voltage of a second power supply potential lower than said first power supply potential, each connected to one end of the corresponding data write line; and a common line receiving a voltage of a third power supply potential lower than said first power supply potential and higher than said second power supply potential, and connected to the other end of each of said plurality of data write lines; wherein each of said plurality of current drivers includes a first transistor causing a current for data writing to flow through said corresponding data write line in a direction from the current driver to said common line, based on potential difference between said first power supply potential and said third power supply potential applied to said common line, when a write data is of a first logic level, and a second transistor causing said current for data writing to flow through said corresponding data write line in a direction from said common line to the current driver, based on potential difference between said third power supply potential applied to said common line and said second power supply potential, when said write data is of a second logic level complementary to said first logic level.