Patent ID: 7982499
Filing Date: 2011-07-19
Classification: G01R

Abstract:
1. A device comprising: a first transistor having a first gate, a first terminal coupled to a node, and a second terminal coupled to a pin; a second transistor having a second gate, a third terminal coupled to the node, a fourth terminal coupled to a ground pin, the first and second gates being coupled to each other at a same transistor gate node, wherein the first and second transistors are coupled in series between the pin and the ground pin; and a logic circuit including a first input to receive a first signal, a second input to receive a second signal, and an output directly coupled to the transistor gate node to provide an output signal having signal levels corresponding to signal levels of the first signal when the second signal has a first signal level indicating a normal operating mode of the device, such that in the normal operating mode the output signal has a logic zero level when the first signal has a logic zero signal and the output signal has a logic one level when the first signal has a logic one level, and the output to provide the output signal having a signal level that turns off the first transistor during an electrostatic discharge (ESD) test in a standby mode of the device, wherein the second signal has a second signal level indicating the standby mode is to perform the ESD test to the device.