Patent ID: 9047429
Filing Date: 2015-06-02
Classification: G06F,H03K

Abstract:
1. An apparatus for increasing fault tolerance of an FPGA circuit, comprising: a computer configured for designing an FPGA circuit; and programming executable on said computer for: describing a logic circuit for implementation on the FPGA circuit and routing of circuits through a synthesis process which arrives at a physical design; performing a circuit analysis on said logic circuit; performing in-place iterations of reconfiguring, don't care X filling, and/or inversion of look-up table (LUT) bits toward increasing overall reliability of said logic circuit; and updating said FPGA circuit in response to said in-place iterations; wherein said in-place iterations are performed after placement and routing to preserve physical design while optimizing the logic circuit to mask faults originating upstream; and wherein said programming executable on said computer is configured to perform said in-place iterations by performing single event upset (SEU) fault analysis to obtain weight values for routing configuration memory (CRAM) bits, followed by performing in-place logic inversion which inverts functions of driving logic in response to reassigning look-up table (LUT) polarities, followed by adjusting all of the truth tables of its fanout LUTs and driven LUTs to preserve functionality, whereby total weight of configuration memory (CRAM) bits on routing multiplexers is minimized.