Patent ID: 6345334
Filing Date: 2002-02-05
Classification: G06F,G11C

Abstract:
A semiconductor memory device for arranging a sequence of digital data that is to be transmitted as a unit during one of a read and write operation, the device comprising:a memory cell array; a write-data latch circuit receiving in serial form a sequence of data and providing in parallel form plural unit data each comprising plural bytes, the sequence of data being synchronized with an external clock signal; an address decoder decoding least significant bits of an address of an initial one of the sequence of data; a clock counter counting clock cycles of the external clock signal; a data sequence switching circuit connected to said write-data latch circuit, said address decoder, and said clock counter, said data sequence switching circuit logically combining a count from said clock counter and the least significant bits of the address for storing the initial one of the sequence of data in said memory cell and arranging the sequence of data based on the logical combination; and a read-data latch circuit connected to said data sequence switching circuit for converting data in parallel form from said data sequence switching circuit to data in serial form for output from the device.