Patent ID: 7582511
Filing Date: 2009-09-01
Classification: H01L

Abstract:
1. An integrated wafer packaging method, comprising: forming an interfacing layer on a surface, comprising a shallow connecting pad, of a wafer; forming a photo resist layer comprising at least an opening in a proximate area of a corresponding area of the shallow connecting pad, wherein the opening defines a shape and a size of at least a passive component; forming at least a passive component on the at least an opening and then removing the photo resist layer; forming a masking layer on another surface of the wafer, wherein the masking layer comprising at least an opening in the proximate area of the corresponding location of an internal connecting pad; coating an electricity isolating material on the surface of the wafer and covering at least a passive component to form a combining layer; combining a passivation layer with the combining layer; etching the another surface of the wafer to remove an unmasked portion of the wafer to form at least a wafer opening connected to at least an internal connecting pad; removing the masking layer; forming an isolation layer on the another surface of the wafer; and forming a connecting wire layout over the isolation layer.