Patent ID: 6219299
Filing Date: 2001-04-17
Classification: G11C

Abstract:
An address decoder for a memory device, comprising:a number of address lines;a number of output lines;wherein the address lines, and the output lines form an array;a number logic cells that are disposed at the intersections of output lines and address lines; anda number of non volatile memory cells are disposed at the intersections of the address lines and at least one output line, the number of non volatile memory cells including:a source region in a horizontal substrate;a drain region in the horizontal substrate;a channel region separating the source and the drain regions;a first vertical gate located above a portion of the channel region and separated from the channel region by a first thickness insulator material; anda second vertical gate located above another portion of the channel region and separated therefrom by a second thickness insulator material, wherein the second vertical gate opposes the first vertical gate, and wherein the second vertical gate is separated from the first vertical gate by an intergate dielectric.