Patent ID: 6370053
Filing Date: 2002-04-09
Classification: G11C,H05K

Abstract:
A memory address driver circuit, comprising:a first memory module slot having a plurality of address pins, wherein the first memory module slot can accommodate a first memory module; a second memory module slot having a plurality of address pins, wherein the second memory module slot can accommodate a second memory module; and a control chipset coupled to the first memory module slot and the second memory module slot for controlling the access of data in any first memory module plugged into the first memory module slot and any second memory module plugged into the second memory module slot, wherein the control chipset includes a first memory control circuit and a second memory control circuit, the first memory control circuit and the second memory control circuit each has an independent group of address pins, the address pins of the first memory control circuit and the address pins of the first memory module slot are connected together, and the address pins of the second memory control circuit and the address pins of the second memory module slot are connected together, wherein when the first memory module is plugged into the first memory module slot, the first memory control circuit uses a first memory command timing to access the data in the first memory module, and when the second memory module is plugged into the second memory module slot, the second memory control circuit uses a second memory command timing to access data in the second memory module.