Patent ID: 7433909
Filing Date: 2008-10-07
Classification: G06F

Abstract:
1. A reconfigurable arithmetic node (RAN) in an adaptive computing system configurable to execute any one of a plurality of target algorithms, wherein the target algorithms include an Asymmetric FIR filter, a Symmetric FIR Filter, a Complex Multiply FIR Filter, a Sum-of-absolute-differences, a Bi-linear interpolation, a Bi-quad IIR filter, a Radix-2 Fast Fourier Transform/Inverse Fast Fourier Transform, a Radix -2 Discrete Cosine Transform/Inverse Discrete Cosign Transform, a Golay Correlator, and a Local Oscillator/Mixer, the RAN comprising an execution unit having: a program control unit (PCU) for controlling task set-up and tear down in the RAN for execution of the one target algorithm; an algorithm control unit (ACU) for controlling a data path unit and generating a control sequence associated with the one target algorithm of the plurality of algorithms and an address generator unit to selected and enable execution of the one target algorithm; and a finite state machine for receiving control signals to execute one of the target algorithms and for selecting between the PCU and the ACU to execute the one target algorithm.