Patent ID: 6320438
Filing Date: 2001-11-20
Classification: H03K

Abstract:
A duty-cycle-correcting clock driver comprising:clock input for receiving an input clock with an input duty cycle that varies from a target duty cycle;a modulator, receiving the input clock and generating an intermediate clock, for adjusting rise and fall delays of the intermediate clock in response to a control signal to adjust the input duty cycle;a driver, receiving the intermediate clock, for generating a final clock, the final clock being corrected to the target duty cycle by the modulator;a feedback loop for generating the control signal to the modulator, receiving the final clock, the feedback loop including:an error amplifier for amplifying a difference between a first input and a reference voltage applied to a second input to generate an amp output;a detector filter having a series resistor between the final clock and the first input of the error amplifier, the detector filter also having an input capacitor attached to the first input; andan output capacitor, coupled to the amp output, for filtering the amp output to generate the control signal to the modulator,wherein the modulator comprises:a source-limiting p-channel transistor having a gate coupled to the control signal and a source connected to a power supply, for limiting charging current in response to the control signal;a switching p-channel transistor, coupled to receive charging current from the source-limiting p-channel transistor, having a gate coupled to the input clock and a drain driving the intermediate clock;a source-limiting n-channel transistor having a gate coupled to the control signal and a source connected to a ground supply, for limiting discharging current in response to the control signal;a switching n-channel transistor, coupled to sink discharging current to the source-limiting n-channel transistor, having a gate coupled to the input clock and a drain driving the intermediate clock,whereby the feedback loop includes the series resistor and senses the final clock to generate the control signal for the modulator.