Patent ID: 6735189
Filing Date: 2004-05-11
Classification: H04B,H04W

Abstract:
A combiner (CMB) for combining digital data samples from a predetermined number n of inputs (&phgr;1, . . . ,&phgr;n) onto a predetermined number m of outputs (sc-1, sc-2, . . . sc-m), said digital data samples having a predetermined bit width (in_bit) and arriving parallely at said combiner as data sets respectively consisting of one data sample from each input at a predetermined common data rate CLK (CLK, t0, t1, . . . ,tkâˆ’1, tk), comprisinga) a plurality of k subprocessing units SU1, SU2, . . . ,SUiâˆ’1, SUi, . . . ,SUk which respectively include: a1) an input register (R21, R22, R2k) for downsampling and storing arriving data sets at a clock rate of CLK/k; and a2) a multiplex/add means (M1k; ADDk, R3k, SUMk, R4k; F1k) for receiving said data sets stored in said input register and for outputting at said clock rate of CLK/k, for each of said m outputs, an added data sample respectively formed by an addition of predetermined ones of said stored data samples; and b) a selector (M3) for cyclically selecting at the common data rate CLK from said multiplex/add means of said subprocessing units a respective output data set consisting of said m added data samples; and c) wherein the sampling phase of the input register of subprocessing unit SUi is delayed by 1/CLK with respect to the sampling phase of the input register of the subprocessing unit SUiâˆ’1, where i=2,3, . . . ,k.