Patent ID: 7441211
Filing Date: 2008-10-21
Classification: G06F,H01L

Abstract:
1. A gate-length biasing method for modifying a nominal cell of an integrated digital circuit, the nominal cell containing one or more transistors, the method comprising the steps of: (a) selecting a trial set of one or more transistors in the nominal cell, each selected transistor having a nominal gate-length; (b) determining trial small bias lengths for the selected trial set of transistors, the trial small bias lengths all less than a predefined fraction of the nominal gate-length; (c) adjusting the gate-lengths of the selected trial set of transistors by the small bias lengths to create a trial biased cell; (d) comparing the trial biased cell to a current best biased cell with respect to a predefined goal including a tradeoff between reducing a leakage power for the biased cell and reducing an impact on timing delays for the digital circuit; and (e) updating the current best biased cell based on the comparison.