Patent ID: 7154293
Filing Date: 2006-12-26
Classification: H03K,H04L

Abstract:
1. A high-speed transmitter circuit comprising: an input separator circuit for inputting a signal for a single-wire circuit and separating the signal into two signals; a two-wire transmitter circuit including at least one pair of logic gates in which a P-channel CMOS transistor and an N-channel CMOS transistor whose size is different from that of the P-channel CMOS transistor are complementarily connected, outputting a first signal speeded up a rising transition time thereof from one of the logic gates and outputting a second signal speeded up a falling transition time thereof from the other of the logic gates; and an output converter circuit receiving in parallel the first signal and the second signal outputted from the two-wire transmitter circuit and converting the signals into a signal for the single-wire circuit, the output converter circuit picking up an edge of the rising output signal with speeded-up rising transition time at the first logic gate and an edge of the falling output signal with speeded up falling transition time at the second logic gate, respectively and converting them into a signal for the single-wire circuit, the output converter circuit comprising: