Patent ID: 9147664
Filing Date: 2015-09-29
Classification: H01L,H05K

Abstract:
1. A semiconductor package, comprising: a substrate; a first pad formed on the substrate; a second pad formed on the substrate; a first conductive element formed on the substrate; a surface mount device mounted on the first pad and the second pad; a first bonding wire electrically connecting a first bonding area of the first conductive element and a second bonding area of the first pad; a second conductive element formed on the substrate, and formed between the first pad and the first conductive element; a solder resistance layer, covering a portion of the first bonding area and a portion of the second bonding area; a molding compound layer encapsulating the substrate, the first pad, the second pad, the first conductive element, the second conductive element, the bonding wire and the surface mount device.