Patent ID: 6723583
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:(a) providing a substrate having a main surface, a rear surface opposed to the main surface, wirings formed on the main surface, and a plurality of semiconductor device forming areas arranged on each of the main and rear surfaces thereof; (b) providing a plurality of semiconductor chips each having a main surface, a rear surface opposed to the main surface, and electrodes formed on the main surface; (c) mounting the plurality of semiconductor chips on the plurality of semiconductor device forming areas on the main surface of the substrate, respectively; (d) after the step (c), electrically connecting electrodes of the plurality of semiconductor chips with the wirings of the substrate by wires; (e) providing a mold having an upper mold half, a lower mold half and a cavity formed in the upper mold half; (f) after the step (d), setting the substrate with the plurality of semiconductor chips mounted thereon into a mold so that the rear surface of the substrate faces the lower mold half and so that the plurality of semiconductor chips are received into the cavity; (g) after step (f), sealing the plurality of semiconductor chips with resin in block to form a seal member by injecting the resin into the cavity while allowing the rear surface of the substrate to be vacuum-chucked to the lower mold half of the mold; and (h) cutting the substrate and the seal member into individual semiconductor devices, wherein the substrate has dummy conductor patterns, and wherein the plurality of semiconductor chips are arranged so as to overlap the dummy conductor patterns in plan view.