Patent ID: 7024448
Filing Date: 2006-04-04
Classification: G06G

Abstract:
1. A multiplier comprising: a first current output circuit that has an input portion, which has one signal of a first differential signal applied to it, and a current output portion which outputs a first current corresponding to said one signal; a second current output circuit that has an input portion, which has another signal of said first differential signal applied on it, and a current output portion which outputs a second current corresponding to said another signal; a first transistor pair that has a first transistor and a second transistor, to which a second differential signal is applied, and feeds said first current; a second transistor pair that has a third transistor and a fourth transistor, to which said second differential signal is applied, and feeds said second current; a first resistor for feeding current to said second transistor and third transistor, and a second resistor for feeding current to said first transistor and fourth transistor; a differential signal output from the connecting node between said first resistor and said second and third transistor and the connecting node between said second resistor and said first transistor and fourth transistor.