Patent ID: 6229346
Filing Date: 2001-05-08
Classification: H03K

Abstract:
A comparator circuit comprising:a differential input stage comprising transistors;a second differential stage connected to said differential input stage and having a differential output;an output stage connected to the differential output of said second differential stage for transforming a differential output signal therefrom into a single ended output signal having a logic level;a common mode measuring stage comprisinga pair of current generators,a differential pair of input transistors and a differential pair of complementary transistors biased by said pair of current generators, anda current mirror summing differential output currents of said differential pair of input transistors and said differential pair; anda switching stage comprising a differential pair of transistors respectively controlled by the differential output of said second differential stage, the differential pair of transistors each comprising a common source coupled to the output of said common mode measuring stage and respective drains coupled to differential output nodes of said differential input stage;the transistors of said differential input stage and said common mode measuring stage operating under the same bias conditions.