Patent ID: 6368923
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A method of fabricating a dual metal gate, comprising:forming a cell region and a peripheral region in a provided substrate, wherein a first dummy gate electrode and a second dummy gate electrode are formed on the substrate, respectively, in the cell region and in the peripheral region, and source/drains are formed in the substrate below the sidewalls of the first dummy gate electrode and the second dummy gate electrode; forming a patterned first dielectric layer above the substrate, which layer exposes surfaces of the first dummy gate electrode and the second dummy gate electrode; removing the first dummy gate electrode and the second dummy gate electrode to expose the substrate; forming an oxide layer on the exposed substrate in the peripheral region; performing a remote plasma nitridation step to nitridate the surface of the oxide layer into a material layer in the peripheral region and to nitridate the exposed surface of the substrate in the cell region; forming a conformal second dielectric layer above the substrate; forming a conducting layer on the second dielectric layer, wherein the conducting layer fills up trenches that are formed by removing the first dummy gate electrode and the second dummy gate electrode; and removing a part of the second dielectric layer and a part of the conducting layer until the surface of the first dielectric layer is exposed.