Patent ID: 8107300
Filing Date: 2012-01-31
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a P type non-volatile memory cell formed in an N type well, said P type non-volatile memory cell including a source, a drain, a charge accumulation layer and a control gate; a sub-bit line physically directly connected to said drain of said P type non-volatile memory cell; an N type selection transistor including a source, a drain and a control gate, said drain of said N type selection transistor being physically directly connected to said sub-bit line; a well bias circuit to bias said N type well with a first voltage so that said sub-bit line is floated and boosted to a program inhibit voltage by a capacitive coupling between said N type well and said drain of said P type non-volatile memory cell; and wherein, said P type non-volatile memory cell is programmed by applying a word line voltage to said control gate of said P type non-volatile memory cell and by applying a programming voltage to said source of said N type selection transistor, so that said sub-bit line is discharged to said programming voltage by said N type selection transistor.