Patent ID: 8976590
Filing Date: 2015-03-10
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells, wherein each memory cell of the plurality of memory cells has a drain connected to a bit line, a gate connected to a word line, and a source connected to a source line, such that the memory cells of the plurality of memory cells connected in common to the bit line are connected in parallel between the bit line and the source line; a first block which includes a plurality of first bit lines to each of which M number of memory cells (M is an integer of two or greater) among the memory cells are connected; a second block which includes a plurality of second bit lines to each of which N number of memory cells (N is an integer of two or greater satisfying M>N) among the memory cells are connected; a write circuit which selects P number of memory cells (P is an integer of two or greater) among the memory cells and performs writing at once in writing of the first block and selects Q number of memory cells (Q is an integer of two or greater satisfying P>Q) among the memory cells and performs writing at once in writing of the second block; and a source line control circuit which supplies a first voltage to the source line of the first block in writing of the first block and supplies a second voltage different from the first voltage to the source line of the second block in writing of the second block.