Patent ID: 9142284
Filing Date: 2015-09-22
Classification: G11C

Abstract:
1. A memory, comprising: first memory cells, each of the first memory cells comprising first and second pass gates including NMOS transistors; second memory cells, each of the second memory cells comprising first and second pass gates including PMOS transistors, wherein the first memory cells are pre-charged by one polarity of a voltage supply, and wherein the second memory cells are pre-charged by an opposite polarity of the voltage supply, first wordline segments, each of the first wordline segments including a plurality of the first memory cells; and second wordline segments, each of the second wordline segments including a plurality of the second memory cells, wherein individual ones of the first wordline segments are arranged between individual ones of the second wordline segments such that the individual ones of the first wordline segments alternate with the individual ones of the second wordline segments in a row of the memory.