Patent ID: 8153483
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having a vertical transistor, the method comprising: forming a first conductivity type first ion implantation layer, a second conductivity type second ion implantation layer, a first conductivity type third ion implantation layer and a first conductivity type fourth ion implantation layer in a silicon substrate such that the ion implantation layers are sequentially positioned from a surface toward the inside of the silicon substrate; etching the first through fourth ion implantation layers to form stack patterns including buried type bit lines, each of which comprises the first conductivity type fourth ion implantation layer extending in one direction; forming a first insulation layer on the silicon substrate to fill spaces between the stack patterns; etching the first conductivity type first ion implantation layer, the second conductivity type second ion implantation layer and a partial thickness of the first conductivity type third ion implantation layer of each stack pattern to form a drain region, a channel region and a source region which are vertically stacked; forming gates on both side walls of the drain region, the channel region and the source region, wherein the drain region, the channel region and the source region are vertically stacked; and forming a second insulation layer on the silicon substrate which is formed with the gates, to expose the source region.