Patent ID: 6653692
Filing Date: 2003-11-25
Classification: G11C,H01L

Abstract:
A double access path mask ROM array structure, comprising a plurality of pairs of banks, wherein said each pair of banks comprises:a plurality of n+-buried regions formed on a substrate to function as part of a first access path and part of a second access path; a plurality of contact holes, wherein two of said contact holes construct a conductive path to the ground and two of said contact holes construct a conductive path to an external sense amplifier; a plurality of block select transistors; a plurality of select cell transistors; a plurality of conductive bit lines, connecting the sources of said different block select transistors to said respective contact holes; a plurality of word lines; a cell array composed of said plurality of word lines to store data; and a first metal line and a second metal line forming part of a double access path; wherein, the plurality of select cell transistors is placed between the plurality of block select transistors and the cell array, the cell array being arranged into two rows.