Patent ID: 6723587
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method of fabricating an ultra small-sized SOI MOSFET comprising:preparing a SOI substrate on which a monocrystalline silicon layer is formed; forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate; forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer; forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening; forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment; forming a gate dielectric layer in the opening on the channel region; forming a gate electrode on the gate dielectric layer to fit in the opening; forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed; forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer; and forming metal interconnections to bury the contact holes.