Patent ID: 6622235
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A scheduler comprising:an instruction buffer configured to store a load memory operation; an address buffer comprising a plurality of entries, wherein a first entry of the plurality of entries is assigned to the load memory operation, and wherein the address buffer is coupled to receive a first address accessed by the load memory operation during execution of the load memory operation, wherein the address buffer is configured to store the first address in the first entry responsive to receiving the first address; circuitry coupled to receive a second address and configured to compare at least a portion of the second address to a corresponding portion of the first address in the first entry, and wherein the circuitry is configured to output a first signal indicative of whether or not a match is detected between the portions; and a control circuit coupled to the instruction buffer and configured to retain the load memory operation in the instruction buffer responsive to issue of the load memory operation for execution, and wherein the control circuit is coupled to receive the first signal and is configured to cause a reissue of the load memory operation if the first signal indicates that the match is detected.