Patent ID: 8026919
Filing Date: 2011-09-27
Classification: G09G,H04N

Abstract:
1. A graphics processor operative to supply a buffer switching signal for timing of switching between a plurality of frame buffers, each of which is adapted to hold a frame of rendering data, to a display controller which switchably selects one of the frame buffers according to a sequence, and supplies the rendering data read by scanning the selected frame buffer to a display, wherein the graphics processor determines whether a vertical synchronization frequency which the graphics processor assumes when generating the rendering data frame by frame matches an actual vertical synchronization frequency of the display, and when the frequencies do not match, generates the buffer switching signal at the assumed vertical synchronization frequency, and when the frequencies match, generates the buffer switching signal at the actual vertical synchronization frequency of the display, and wherein the selected frame buffer from which the rendering data is to be read is switched to another frame buffer when the buffer switching signal is received such that the display switches the buffers at the assumed vertical synchronization frequency and a time point of the buffer switch is determined independently from a time of occurrence of a vertical synchronization of the display when the frequencies do not match.