Patent ID: 6714451
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of word lines arranged in rows; a plurality of bit lines arranged in columns; a plurality of nonvolatile memory cells arranged in the rows and the columns; a plurality of latch circuits arranged to be electrically connected to said plurality of bit lines, and latching a plurality of data inputted externally; and a bit line select circuit supplying a predetermined potential to said plurality of bit lines, respectively, and maintaining potentials on said plurality of bit lines supplied with the predetermined potential, wherein a plurality of nonvolatile memory cells arranged in each of said rows are connected in series, and gates thereof are connected to the word line arranged in the row, and said plurality of bit lines are connected with the plurality of nonvolatile memory cells arranged in two columns neighboring to each other, respectively.