Patent ID: 8166239
Filing Date: 2012-04-24
Classification: G06F

Abstract:
1. A method for operating a TLB (translation lookaside buffer) for virtual addresses of a computer system, wherein the TLB entries are stored in a RAM (random access memory) of said TLB, and wherein a valid entry in said RAM is associated to an entry in a CAM (content-addressable memory) of said TLB, and wherein an entry in said CAM comprises attribute data for an associated virtual address, the attribute data comprising a task ID of a processor task of said computer system for which the entry was formed, said method comprising: a) when adding an entry for a virtual address to said TLB, testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; whereas if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and b) when performing a TLB lookup operation: applying the task ID of the attribute data to the CAM to select the entry in the CAM and read the validity flag and the tag data from the entry in said CAM, absent applying the virtual address to the CAM to select the entry and to read the validity flag and the tag data, which entry in the CAM is associated to the entry in said RAM for said virtual address, and separately addressing the RAM, in parallel to the applying the task ID of the attribute data to the CAM, by applying at least a portion of the virtual address to the RAM to select the entry in the RAM and read the an absolute address, a task ID, and the tag data from the entry in said RAM for said virtual address, thereby reading in parallel the tag data from the entry in the CAM and the task ID and tag data from the entry in the RAM for comparison of the tag data from the entry in the CAM with the tag data from the entry in the RAM, and for comparison of the task ID applied to the CAM to select the entry in the CAM with the task ID stored in the entry in RAM, and generating a TLB hit only if (i) the tag data read from said CAM is valid and matches the tag data read from said RAM, and (ii) the task ID applied to the CAM to select the entry in the CAM matches the task ID stored in the entry in RAM.