Patent ID: 8731006
Filing Date: 2014-05-20
Classification: H04J,H04L

Abstract:
1. A signal multiplexing circuit for receiving data signals of first and second channels which are RZ (Return to Zero) signals, and for generating a multiplexed signal obtained by time-division multiplexing the data signals of the first and second channels at a repetition period T of the first and second channels, comprising: defining T a first pulse generating circuit converting the data signal of the first channel to a signal which has a period of m as the pulse width of the “Hi” level and a period of T a second pulse generating circuit converting the data signal of the second channel to a signal which has a period of n as the pulse width of the “Hi” level and a period of T a time-division multiplexing circuit time-division multiplexing and outputting the data signals of the first and second channels as a multiplexed signal having “Hi” level period m, “Lo” level period T the minimum value of the “Hi” level period n and the “Lo” level periods (T