Patent ID: 7518169
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. An MOS transistor having a source region, a drain region and a channel region formed in a semiconductor layer of an SOI substrate having a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, wherein one of the drain or source region is electrically connected to a backside contact formed on the side of the semiconductor substrate facing away from the isolation layer through a via running through the semiconductor substrate, wherein the via has an opening filled with a conductive material running from the one of the drain or source region at least through the isolation layer, and wherein a portion of the via extending through the semiconductor substrate has a greater conductivity than surrounding portions of the semiconductor substrate, wherein the portion of the via extending through the semiconductor substrate comprises a continuation of the opening filled with a conductive material so that the opening runs to the side of the semiconductor substrate facing away from the isolation layer, and so that a continuous path of the conductive material extends through the via from said side of the semiconductor substrate to a side of the semiconductor layer facing away from the isolation layer, the conductive material comprising metal and the semiconductor substrate having a doping concentration lying between 1×10 12 and 1×10 16 cm −3 .