Patent ID: 7863948
Filing Date: 2011-01-04
Classification: H03B,H03K

Abstract:
1. A clock frequency dividing circuit comprising: a first frequency dividing circuit having a first mixer multiplying a first external clock and a first internal feedback signal, a first adding circuit adding an output of the first mixer and a first external input signal, and a first phase circuit phase-shifting an output of the first adding circuit to output a first output signal and the first internal feedback signal; a second frequency dividing circuit having a second mixer multiplying a second external clock and a second internal feedback signal, a second adding circuit adding an output of the second mixer and a second external input signal, and a second phase circuit phase-shifting an output of the second adding circuit to output a second output signal and the second internal feedback signal; a first coupling circuit receiving the first output signal of the first frequency dividing circuit to output the second external input signal; and a second coupling circuit receiving the second output signal of the second frequency dividing circuit to output the first external input signal, wherein the first coupling circuit includes a first transconductance amplifier, and the second coupling circuit includes a second transconductance amplifier.