Patent ID: 6448510
Filing Date: 2002-09-10
Classification: C25D,H01L,H05K,Y10S,Y10T

Abstract:
A substrate for use in electronic packaging, the substrate consisting of a discrete, non-layered, solid body having a pair of generally parallel major surfaces and having one or more electrically insulated original valve metal vias substantially perpendicularly disposed to said major surfaces and at least partially surrounded by porous valve metal oxide based material, each via having exposed end surfaces substantially co-directional with said major surfaces, the substrate being formed only from a non-layered original valve metal solid blank having major surfaces with a distance therebetween equal to a distance between the substrate's major surfaces, by a single process of porous anodization of said blank with the blank's major surfaces being masked, at least one of the blank's major surfaces being masked selectively, for converting portions of said blank that were non-masked at least at one of the blank's major surfaces into porous valve metal oxide and thereby retaining portions of said blank that were masked at both of the blank's major surfaces as said one or more electrically insulated original valve metal vias.