Patent ID: 7660178
Filing Date: 2010-02-09
Classification: G06F

Abstract:
1. A FIFO memory having an available capacity of no more than N words deep by M bits wide, comprising: a write port for receiving data to store in the FIFO memory, a read port for providing the data stored in the FIFO memory, X memories to store the data, where each of the X memories has a size of N/X by M, and control logic for receiving the data from the write port, writing the data into at least one of the X memories in a serial write manner, reading the data from at least one of the X memories in a serial read manner, and providing the data to the read port, the control logic also for disabling power to selected ones of the X memories when they are not being written to or read from, where the FIFO memory is configured to both read and write the data at a given time to a given one of the X memories.