Patent ID: 9059829
Filing Date: 2015-06-16
Classification: H04L

Abstract:
1. A receiver receiving a sequence of symbols converted from given g bits (where g is an integer greater than zero), wherein the sequence of symbols is generated in such a manner that, after the given bits are encoded, the encoded bits are reordered by interleaving, thus generating information bits, every L bits of which are reduced to m bits (where m and L are integers greater than zero which satisfy m<L), and one symbol is assigned to the m bits, the receiver comprising: a symbol demapper outputting one bit of first extrinsic information by using one received symbol and (m−1) bits of a priori information; a check node decoder outputting one bit of second extrinsic information by using m bits of the first extrinsic information output by the symbol demapper with respect to each of m bits corresponding to the one received symbol and (L−1) bits of a priori information; a deinterleaver deinterleaving a plurality of bits of second extrinsic information corresponding to the sequence of symbols in a manner inverse to the interleaving; a variable node decoder outputting one bit of third extrinsic information by using a plurality of bits of second extrinsic information output from the deinterleaver as a priori information; an interleaver interleaving third extrinsic information output from the variable node decoder in a manner inverse to the deinterleaving; and a resequencer disposed in at least one stage preceding or following the interleaver and the deinterleaver, wherein the check node decoder outputs m bits of fourth extrinsic information by using L bits of the third extrinsic information output from the interleaver as a priori information, wherein the fourth extrinsic information is used as a priori information by the symbol demapper, wherein a plurality of modules of the deinterleaver and the interleaver are provided for parallel processing of each of interleaving and deinterleaving, wherein the resequencer, if disposed in the preceding stage, rearranges a sequence of bits of the second extrinsic information to be input to the deinterleaver and rearranges a sequence of bits of the third extrinsic information output from the interleaver, and wherein the resequencer, if disposed in the following stage, rearranges a sequence of bits of the second extrinsic information output from the deinterleaver and rearranges a sequence of bits of the third extrinsic information to be input to the interleaver.