Patent ID: 7373564
Filing Date: 2008-05-13
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a plurality of external data terminals inputting and outputting data; a plurality of regular cell arrays having regular memory cells where data, which are input to and output from the external data terminals, are read and written and where said data is written to one of said regular cell arrays during a normal operation mode; a plurality of external parity data terminals inputting and outputting test parity data during a test mode; a parity cell array having parity memory cells in which parity data of data written into the regular cell arrays during a normal operation mode are read and written, and the test parity data are thus read and written during the test mode, where allocations of addresses differ in said normal operation mode and in said test mode; a normal write data selection circuit outputting the data received through the external data terminals to any one of the regular cell arrays selected according to an address, in the normal operation mode; a normal read data selection circuit outputting to the external data terminals the data read from any one of the regular cell arrays, which is selected according to the address in the normal operation mode; a test write control circuit writing a test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which the test parity data are written, the test write control circuit operating in the test mode, and said test data are written in the regular memory cells in each said regular cell arrays; and a test read control circuit reading the test data from the regular memory cell at the location corresponding to the location of the parity memory cell from which the test parity data are read, the test read control circuit operating in the test mode, and said test data are read from the regular memory cells in each said regular cell arrays.