Patent ID: 6870252
Filing Date: 2005-03-22
Classification: H01L

Abstract:
1. A semiconductor package comprising: a substrate; a plurality of I/O cells; a silicon chip mounted on the substrate, wherein the silicon chip is electrically coupled to the plurality of I/O cells, wherein the I/O cells receive power separately from core power received by the silicon chip; a first horizontal conductor and a second horizontal conductor within the substrate; a first plurality of vertical conductors, wherein the silicon chip is coupled to the first horizontal conductor by the first plurality of vertical conductors, and wherein the silicon chip receives core power through the first plurality of vertical conductors; a second plurality of vertical conductors, wherein the silicon chip is coupled to the second horizontal conductor by the second plurality of vertical conductors; a third plurality of vertical conductors coupled to provide an electrical connection between the first horizontal conductor and a first plurality of terminals; and a fourth plurality of vertical conductors coupled to provide an electrical connection between the second horizontal conductor and a second plurality of terminals.