Patent ID: 6456113
Filing Date: 2002-09-24
Classification: H03K

Abstract:
A scan flip-flop circuit comprising:a selector circuit having a first input terminal for being supplied with a logic signal for a normal mode of operation and a second input terminal for being supplied with a logic signal for a scan test, for outputting the logic signal for the normal mode of operation in the normal mode of operation and outputting the logic signal for the scan test in the scan test; a master latch circuit for latching and outputting a signal outputted from said selector circuit; and a slave latch circuit having first and second output terminals for latching and outputting a signal outputted from said master latch circuit, for latching the signal outputted from said master latch circuit and outputting the latched signal from said first output terminal, and fixing an output signal outputted from second output terminal to a power supply potential in the normal mode of operation, and latching the signal outputted from said master latch circuit and outputting the latched signal from said first and second output terminals in the scan test.