Patent ID: 6442679
Filing Date: 2002-08-27
Classification: G06F

Abstract:
Guard prediction apparatus for predicting an outcome of a predicated instruction for a microprocessor, the predicated instruction specifying a guard condition and an operation to be performed when the guard condition has a value of true, the guard prediction apparatus comprising:a) an initial prediction circuit that generates an initial prediction of the value of the guard condition; b) a cache of previous predictions of values of guard conditions; c) availability logic coupled to the cache to generate a select signal to indicate whether the cache includes a previous prediction indicative of the value of the guard condition; d) a selection circuit for selecting as a final prediction of the value of the guard condition one of the previous prediction and the initial prediction in response to the select signal; and e) a circuit that enables execution of the operation when the final prediction has the value of true and disables execution of the operation when the final prediction has a value of false.