Patent ID: 6423608
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A method of manufacturing a capacitor in a semiconductor integrated circuit, comprising:providing a semiconductor substrate having an interlayer insulating layer disposed thereon; sequentially forming an upper etching stopper layer and a lower sacrificial insulting layer on the interlayer insulating layer on the semiconductor substrate; sequentially patterning the lower sacrificial insulating layer and the upper etching stopper layer to form a storage electrode hole and to expose a predetermined portion of the interlayer insulating layer; forming an outer cylindrical storage electrode in the storage electrode hole, a conductive liner surrounded by the outer cylindrical storage electrode, and an inner storage electrode surrounded by the conductive liner; and selectively etching the conductive liner to expose an inner sidewall of the outer cylindrical storage electrode and an outer sidewall of the inner storage electrode.