Patent ID: 7203116
Filing Date: 2007-04-10
Classification: G11C

Abstract:
1. A semiconductor device, comprising: a first semiconductor memory device formed on a first semiconductor chip; a second semiconductor memory device formed on a second semiconductor chip and different from the first semiconductor chip, including: word lines, bit lines, storage circuits coupled to the word lines and the bit lines so that one storage circuit is coupled to one word line and one bit line, wherein the storage circuits store data therein and each storage circuit is configured to require a refresh operation to hold the data stored therein; a row address decoder configured to receive row address signals and to select one of the word lines in accordance with the row address signals; a row address transition detector configured to receive the row address signals to detect a transition of the row address signals; a column address decoder configured to receive column address signals and to select one of the bit lines in accordance with the column address signals; a column address transition detector configured to receive the column address signals to detect a transition of the column address signals; and a timer configured to signal the refresh operation to the storage circuits in accordance with data holding capability of the storage circuits, wherein the column address transition detector signals a page mode operation which selects bit lines continuously to the column address decoder when the row address signals are constant and the column address signals are changed, and the refresh operation is executed autonomously before or after a memory operation which is a reading operation for outputting the data from the storage circuits or a writing operation for inputting the data to the storage circuits each of which is different from the refresh operation.