Patent ID: 6504854
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A method of carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed, the method comprising the steps of:receiving, from a device associated with the clock domain of the second data bus, a sample signal associated with the second clock speed; and dynamically adjusting the speed of operation of a state machine of a peripheral controller in response to the sample signal by gating a clock at the first clock speed which clocks the state machine of the peripheral controller with the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur at the second clock speed.