Patent ID: 8930787
Filing Date: 2015-01-06
Classification: H03M

Abstract:
1. A decoder in a device receiving data having an error correction code, the decoder comprising: a memory storing program code having a plurality of instructions including control signals for decoding an error correction code; an address generator coupled to the memory, the address generator updating an address coupled to the memory for generating an instruction of the plurality of instructions; a first data processing circuit coupled to receive the instruction from the memory and further coupled to receive first syndrome data, wherein the first data processing circuit generates first error locator polynomials; and a second data processing circuit coupled to the memory, the second data processing circuit coupled to receive the instruction and further coupled to receive second syndrome data, wherein the second data processing circuit generates second error locator polynomials; wherein the memory is shared with the first data processing circuit and the second data processing circuit, and a control signal of the instruction is provided to the first data processing circuit and the second data processing circuit in response to the address generator updating the address coupled to the memory for generating the instruction.