Patent ID: 7538002
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A semiconductor fabrication process, comprising: forming first and second isolation structures laterally positioned on either side of a transistor region of a semiconductor layer; forming a gate structure overlying a portion of the transistor region, wherein the gate structure includes an electrically conductive gate electrode overlying a gate dielectric layer overlying the semiconductor layer, and further wherein sidewalls of the gate electrode define boundaries of a channel region underlying the gate structure and source/drain regions on either side of the channel region extending between the channel region and the first and second isolation structures; removing portions of the semiconductor layer in the source/drain regions to form source/drain recesses; removing upper portions of the first and second isolation structures to form first and second recessed isolation structures, wherein a lower surface of the source/drain recesses and an upper surface of the first and second recessed isolation structures are vertically displaced below an upper surface of the semiconductor substrate by a first displacement and a second displacement respectively, wherein the first displacement is greater than the second displacement; and filling the source/drain recesses with a source/drain stressor.