Patent ID: 8169071
Filing Date: 2012-05-01
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a substrate; a first recessed conductive layer that is embedded in the substrate and recessed into a first surface of the substrate; a first raised conductive layer disposed above the first surface of the substrate such that a first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer; a second recessed conductive layer embedded in the substrate and recessed into a second surface of the substrate, the second surface of the substrate opposite the first surface of the substrate; a second raised conductive layer disposed beneath the second surface of the substrate such that a second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer; and an interconnect structure disposed on the first recessed conductive layer, the first raised conductive layer, the second recessed conductive layer, and the second raised conductive layer.