Patent ID: 8940593
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A method of forming a transistor comprising: Forming a channel layer including GaN; forming a barrier layer, the barrier layer including AlGaN; forming a lower transition layer touching the barrier layer forming a layer of Si an upper transition layer touching the Si forming a layer of SiO forming a metal gate the metal gate having a bottom surface that touches the top surface of the region of SiO forming a spaced-apart metal source region and metal drain region that touch the barrier layer, wherein the barrier layer including AlGaN is below a threshold of thickness such that when substantially zero volts are applied to the metal gate region, and the metal gate region and the metal drain region are differently biased, substantially no electrons comprise a two-dimensional electron gas region between the barrier layer including AlGaN and the channel layer including GaN; and when a voltage that exceeds a threshold voltage of the enhancement-mode transistor is applied to the metal gate region, and the metal source region and the metal gate region are differently biased, electrons accumulate in the two-dimensional electron gas region between the barrier layer including AlGaN and the channel layer including GaN, and the electrons flow from the metal source region to the metal drain region.