Patent ID: 7095657
Filing Date: 2006-08-22
Classification: G11C

Abstract:
1. A nonvolatile memory comprising: a nonvolatile memory array including a plurality of memory banks, each of which has a plurality of nonvolatile memory cells; a plurality of buffer memories, each of which has a plurality of SRAM memory cells and corresponds to one of the memory banks; and a control circuit, wherein each of the plurality of SRAM memory cells is used for storing data to store to the corresponding memory bank, wherein the control circuit is capable of controlling a program operation in response to a program command accompanied with address information and program data, and wherein in the program operation, the control circuit selects one of the memory banks and one of the buffer memories corresponding to the address information, stores the program data to the selected buffer memory, and then stores the program data stored in the selected buffer memory to one of the nonvolatile memory cells in the selected memory bank.