Patent ID: 7755406
Filing Date: 2010-07-13
Classification: H03K,H03L

Abstract:
1. A duty cycle correction circuit with wide-frequency working range, the duty cycle correction circuit receiving a reference clock signal from a clock generator and correcting duty cycle of the received reference clock signal for outputting an output clock signal, the duty cycle correction circuit comprising: a modulation circuit, comprising: a delay circuit coupled to one output end of the modulation device for delaying the output clock signal by a predetermined period and accordingly outputting a first corrected clock signal and a second corrected clock signal; wherein the first corrected clock signal and the second corrected clock signal are inverted to each other; and a Phase Lock Loop (PLL) circuit, coupled to the delay circuit, for estimating high-level status and low-level status of the first corrected clock signal and the second corrected clock signal and accordingly generating the reference voltage.