Patent ID: 6496504
Filing Date: 2002-12-17
Classification: H04L,H04Q

Abstract:
An apparatus in a digital network computer-based system, comprising:a source terminal, having, a source processor, a source memory accessible to the source processor, said source memory configured to hold a source terminal program that when executed by the source processor forms a setup message having a bandwidth coordination message contained therein, said source memory being configured to hold in said bandwidth coordination message, a bandwidth allocation indicator, an address of a destination terminal to which said source terminal will send a data message via a subchannel, and a subchannel data rate for said subchannel; a source terminal interface configured to be coupled to a digital network switch, said digital network switch having a bandwidth coordination mechanism that dynamically subdivides a capacity of a communication channel into multiple subchannels based on said bandwidth coordination message, said multiple subchannels including the subchannel that will be used for transmitting the data message, wherein said bandwidth coordination message informs the digital network switch of the subchannel data rate so that the digital network switch establishes the subchannel.