Patent ID: 9201651
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A data processing apparatus, comprising: a first set of integer registers; a second set of floating point registers; and processing circuitry responsive to data processing instructions and configured to execute integer data processing operations using the first set of integer registers and floating point data processing operations using the second set of integer registers; wherein: said processing circuitry is responsive to an interrupt request to perform one of an integer state preservation function in which at least a subset of said integer registers are copied to a stack memory without copying said floating point registers to the stack memory, and a floating point state preservation function in which at least a subset of both said integer registers and said floating point registers are copied to said stack memory, said one of said integer state preservation function and said floating point state preservation function being selected by said processing circuitry in dependence on state information, said state information comprises first state information indicative of whether a current data processing context being executed by said processing circuitry when the interrupt request is received is a floating point data processing context which includes one or more floating point data processing operations or an integer data processing context which does not include any floating point data processing operations; said first state information is set in response to a data processing instruction which causes the processing circuitry to execute floating point data processing operations; said processing circuitry is responsive to said interrupt request to perform said integer state preservation function if said first state information indicates that the current data processing context is an integer data processing context, and to perform, if said first state information indicates that the current data processing context is a floating point data processing context, a first part of said floating point state preservation function in which the subset of integer registers are copied to the stack memory and a second part of said floating point state preservation function including allocating space on the stack memory for the subset of floating point registers without copying the subset of floating point registers to the stack memory; and said processing circuitry is configured to perform a third part of said floating point state preservation function in which the subset of floating point registers are copied to the allocated portion of the stack memory, responsive to a determination that a data processing instruction is to be executed following the allocation of space on the stack memory, which causes the processing circuitry to execute floating point data processing operations.