Patent ID: 7375430
Filing Date: 2008-05-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a first surface; two first gate electrodes formed along a first direction on the first surface; source/drain areas formed in the first surface and sandwiching a channel region under each of the first gate electrodes; a first interlayer insulating layer filling a region between the first gate electrodes and having a top lower in level than a top of each of the first gate electrodes; a second interlayer insulating layer formed above the first gate electrodes and the first interlayer insulating layer; two interconnect layers formed in the second interlayer insulating layer along a direction which intersects the first direction and being electrically insulated from each other, a region between the interconnect layers being filled with the second interlayer insulating layer; and a contact plug formed in the first interlayer insulating layer and the second interlayer insulating layer and being in contact with one of the interconnect layers and one of the source/drain areas.