Patent ID: 9130150
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate; gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround outer sidewalls and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer; a source region formed in the active region connected to the semiconductor substrate; and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures, wherein the gate insulating layer is formed along on the upper surface and the outer sidewalls of the active region, and a bottom of a space between adjacent active regions; the liner conductive layer is formed on the gate insulating layer along over the upper surface and the outer sidewalls of the active region, and the bottom of the space between adjacent active regions: and the gate conductive layer is formed on the liner conductive layer so as to fill the space between adjacent active regions.