Patent ID: 6063711
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A method of forming a dual damascene structure utilizing a highly selective etching stop layer comprising the steps of:providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon;forming a first intermetal dielectric (IMD) layer over said substrate;forming a high-selectivity etch-stop layer over said first IMD layer, wherein said forming said high-selectivity etch-stop layer is accomplished by reacting SiH.sub.4 with N.sub.2 O and NH.sub.3 at a temperature between about 300 to 40.degree. C. through chemical vapor deposition (CVD) to form oxynitride having a thickness between about 500 to 1,500 .ANG.;forming a second IMD layer over said etch-stop layer;forming a first photoresist layer over said second IMD layer and patterning said photoresist layer with a mask comprising a line trench pattern;etching through said line trench pattern in said first photoresist layer until said etch-stop layer is reached to form said line trench pattern into said second IMD layer;removing said first photoresist layer;forming a second photoresist layer over said second IMD layer including said line trench in said second IMD layer;patterning said second photoresist layer with a mask comprising a via hole pattern;etching through said via hole pattern in said second photoresist layer into said etch-stop layer, thus forming a via hole opening in said etch-stop layer, wherein said etching is accomplished with a recipe comprising gases CF.sub.4 with a flow rate between about 80 to 90 sccm, CHF.sub.3 between about 10 to 20 sccm, and Ar between about 180 to 200 sccm;etching further through said via hole opening in said etch-stop layer to form said via hole pattern into said first IMD layer;removing said second photoresist layer;depositing metal in said line trench and said via hole composite structure; andremoving said metal from the surface of said substrate for subsequent process steps to complete the fabrication of a semiconductor substrate.