Patent ID: 6403404
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method of selectively forming a silicide layer on a logic region of a semiconductor substrate which has an integration of a memory cell region and said logic region, said method comprising the steps of:forming an insulation film over said memory cell region and said logic region; entirely applying a resist film over said insulation film; selectively removing said resist film over at least a predetermined part of said logic region by use of a lithography process, whereby said insulation film is shown over said logic region; selectively etching said insulation film over said logic region by use of said resist film, whereby at least a silicon region is shown over said logic region; removing said resist film; entirely depositing a refractory metal layer on said insulation film over said memory cell region and also on said silicon region over said logic region; carrying out a heat treatment to cause a silicidation reaction to form at least a silicide layer on said silicon region over said logic region; and removing an unreacted refractory metal layer from said silicon oxide film.