Patent ID: 7193913
Filing Date: 2007-03-20
Classification: G11C

Abstract:
1. A sense amplifier circuit for a semiconductor memory device, the sense amplifier circuit comprising: a local I/O line pair comprising a local I/O line and an inverted local I/O line; a global I/O line pair comprising a global I/O line and an inverted global I/O line; a write amplification unit amplifying data output from the a global I/O line pair in response to a first control signal and transferring the data to the local I/O line pair; and a read amplification unit amplifying data output from the local I/O line pair in response to a second control signal and transferring the data to the global I/O line pair; wherein the read amplification unit comprises: a first transistor having a first terminal connected to ground, a second terminal, and a gate receiving the second control signal; a second transistor having a gate connected to the local I/O line and a first terminal connected to the second terminal of the first transistor, and a second terminal; a third transistor having a gate connected to the inverted local I/O line, a first terminal connected to the second terminal of the first transistor, and a second terminal; a fourth transistor having a gate receiving the second control signal, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the inverted global I/O line; and a fifth transistor having a gate receiving the second control signal, a first terminal connected the second terminal of the third transistor, and a second terminal connected to the global I/O line.