Patent ID: 6344395
Filing Date: 2002-02-05
Classification: H01L

Abstract:
A method for fabricating a nonvolatile memory on a semiconductor substrate, comprising the steps of:forming a plurality of trench isolation regions in the semiconductor substrate, said isolation regions being separated from each other by an active region, wherein some of the active regions are located in a cell region of the semiconductor substrate, and the other of the active regions are located in a periphery region of the semiconductor substrate; firstly implanting ions of a first conductivity type and ions of a second conductivity type into the active regions of the substrate, so that a first ion region of the first conductivity type and a first ion region of the second conductivity type are sequentially and respectively formed, wherein said firstly implanting step is performed by using a first photoresist layer and a second photoresist layer as masks; secondly implanting ions of the first conductivity type and ions of the second conductivity type into the active regions of the substrate, so that a second ion region of the first conductivity type and a second ion region of the second conductivity type are sequentially and respectively formed, wherein said secondly implanting step is performed by using a third photoresist layer and a fourth photoresist layer as masks,; growing a first oxide layer on said semiconductor substrate; removing said first oxide layer; growing a second oxide layer on said semiconductor substrate; growing a third oxide layer on said second oxide layer; blanket and conformably forming a first conductive layer on the third oxide layer; forming a sixth photoresist on first conductive layer to define an opening in the first conductive layer, wherein said opening is located between the periphery region and the cell region; etching the first conductive layer until the trench isolation region being exposed, so that opening is formed and the sixth photoresist is used as an etching mask; removing the sixth photoresist; sequentially forming a dielectric layer over the first conductive layer and the opening; forming a seventh photoresist over the dielectric layer located on the cell region to expose the periphery region; etching the dielectric layer located on the periphery region until the surface of the trench isolations located under the opening being exposed, wherein the seventh photoresist being used as an etching mask for leaving portions of the dielectric layer located on the periphery region; forming a second conductive layer on the first conductive layer located on the periphery region and on the third oxide layer located on the cell region; forming a eighth photoresist on the active region of the second conductive layer, wherein the active regions being on the first ion region of the first conductivity type and the first ion region of the second conductivity type; and etching a portion of the second conductive layer, a portion of the first conductive layer, a portion of the third oxide layer and a portion of the second oxide layer until the surface of trench isolation being exposed, so that capacitor columns being formed, some of the capacitor columns including the second conductive layer, the first conductive layer and the third oxide layer located on the periphery region, some of the capacitor columns including the second conductive layer, the first conductive layer, the third oxide layer and the second oxide layer on the periphery region, and the other of the capacitor columns including the second conductive layer, the dielectric layer, the first conductive layer and the third oxide layer on the cell region.