Patent ID: 6162698
Filing Date: 2000-12-19
Classification: C23C,H01L

Abstract:
A method of manufacturing a capacitor in a semiconductor device comprising:providing a lower substrate on which an insulation layer is formed;forming a contact hole for a wire on a selected portion of said insulation layer;forming a wiring plug by depositing a polysilicon layer within said contact hole;forming a diffusion prevention layer, which is composed of Ti/TiN layers, on an exposed portion of said wiring plug and said insulation layer;forming a lower electrode, which is composed of a Pt layer, on said diffusion prevention layer;forming a ferroelectric PZT layer on said Pt layer;after forming said ferroelectric PZT layer, transforming a fine structure of said ferroelectric PZT layer into a domain structure and structure having a grain boundary of orientation polarization in a vertical direction of said lower substrate by maintaining said ferroelectric PZT layer for a few minutes under a RF plasma generated by supply of a DC bias voltage and, after maintaining said ferroelectric PZT layer under said RF plasma, performing a cooling process;forming a silicon oxidation layer over a resulting structure;selectively etching said silicon oxidation layer to expose said ferroelectric PZT layer by means of a photo mask and dry etching method; andforming an upper electrode over an exposed portion of an entire structure.