Patent ID: 6195629
Filing Date: 2001-02-27
Classification: G06F

Abstract:
A method for selectively disabling an output of an instrumentation entity during simulation of a digital circuit design, wherein said instrumentation entity includes an output signal to indicate an occurrence of an event during simulation of said digital circuit design said method comprising the steps of:describing a design entity utilizing a hardware description language, said design entity instantiated in at least one instance within said simulation model of said digital circuit design;associating said instrumentation entity with said design entity utilizing a non-conventional comment, such that said instrumentation entity is automatically instantiated in at least one instance corresponding to said at least one instance of said design entity within said simulation model without said instrumentation entity becoming incorporated into said digital circuit design;associating said output signal with a unique output storage element; andproviding a disable mechanism uniquely associated with said output signal, such that said output signal may be selectively masked by disabling said storage element during simulation testing of said digital circuit design.