Patent ID: 7692314
Filing Date: 2010-04-06
Classification: H01L

Abstract:
1. A wafer level chip scale package, comprising: an integrated circuit (IC) chip, the IC chip including a plurality of chip pads and a passivation layer exposing the chip pads on a top surface thereof; a first dielectric layer disposed on the passivation layer, the first dielectric layer defining a plurality of first openings such that the chip pads are exposed; ball pad sections having conductive patterns protruding from the first dielectric layer and exposing a portion of the first dielectric layer; trace layer patterns disposed on the first dielectric layer so as to connect the conductive patterns of the ball pad sections with the chip pads; a second dielectric layer formed on the trace layer patterns and the first dielectric layer, the second dielectric layer defining a plurality of second openings such that the ball pad sections are exposed; and conductive balls disposed on the ball pad sections and electrically connected with the conductive patterns of the ball pad sections.