Patent ID: 6219686
Filing Date: 2001-04-17
Classification: G06F,G11C,H03K

Abstract:
An apparatus that processes two N-NARY 1 of N input signals to produce an N-NARY 1 of N signal result and an N-NARY 1 of N signal HPG indicator, comprising:a 1-of-P first addend input configured to receive the first addend wherein said 1 of P first addend input comprises a 1 of N signal where N is greater than 2;a 1-of-Q second addend input configured to receive the second addend wherein said 1 of Q second addend input comprises a 1 of N signal where N is greater than 2;a 1-of-R Add/Sub input configured to receive a 1-of-R operation selector wherein said 1 of R Add/Sub input comprises a 1 of M signal;a sum/HPG circuit that is configured to perform an arithmetic operation on the addends, based on the value of said operation selector, to produce the result;said sum/HPG circuit is further configured to perform carry propagate logic to produce the HPG indicator; andsaid sum/HPG circuit is coupled to said first addend input, said second addend input, and said Add/Sub input, said sum/HPG circuit is further coupled to a 1-of-S result output that is configured to deliver the result wherein said 1 of S result output comprises a 1 of N signal where N is greater than 2, and said sum/HPG circuit is further coupled to a 1-of-T HPG output that is configured to deliver the HPG indicator wherein said 1 of T HPG output comprises a 1 of N signal where N is greater than 2.