Patent ID: 6829752
Filing Date: 2004-12-07
Classification: G06F

Abstract:
A system for analyzing a monolithic integrated circuit, comprising:a logic circuit simulator configured to obtain a cell duty of a primitive cell configuring a logic circuit by performing a logic simulation of the logic circuit based on a netlist of the logic circuit and input vectors for the logic circuit; an analog circuit simulator configured to obtain a transistor duty of a transistor configuring the primitive cell by performing an analog simulation of the primitive cell based on a netlist in the analog circuit of the primitive cell and input vectors for the primitive cell; and a synthesis module configured to obtain a synthesized duty of the transistor of the logic circuit by performing a synthesis of the cell and transistor, wherein the cell duty corresponds to a percentage of a period that an input signal is applied to said cell during a designated unit cycle and defined as a probability that an input status will change and the transistor duty corresponds to a percentage of time said transistor is at a certain specified bias status during said unit cycle.