Patent ID: 6664118
Filing Date: 2003-12-16
Classification: H01L

Abstract:
An operation method of a ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit,the first memory unit comprising; (A-1) a first bit line, (B-1) first transistor or transistors for selection in the number of N wherein N&gE;1, (C-1) first sub-memory unit or units in the number of N, each first sub-memory unit comprising first memory cells in the number of M wherein M&gE;2, and (D-1) plate lines in the number of M, each of the plate lines being common to the first memory cell or cells constituting the first sub-memory unit or units in the number of N, and the second memory unit comprising; (A-2) a second bit line, (B-2) second transistor or transistors for selection in the number of N, (C-2) second sub-memory unit or units in the number of N, each second sub-memory unit comprising second memory cells in the number of M, and (D-2) the plate lines in the number of M, each of the plate lines being common to the second memory cell or cells constituting the second sub-memory unit or units in the number of N, the plate lines constituting the second memory unit being common to the plate lines constituting the first memory unit, in which each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, in the first memory unit, the first electrodes of the first memory cells constituting the n-th-place first sub-memory unit are in common in the n-th-place first sub-memory unit wherein n=1, 2 . . . N; the common first electrode in the n-th-place first sub-memory unit is connected to the first bit line through the n-th-place first transistor for selection; and the second electrode of the m-th-place first memory cell is connected to the common m-th-place plate line wherein m=1, 2 . . . M, and in the second memory unit, the first electrodes of the second memory cells constituting the n-th-place second sub-memory unit are common in the n-th-place second sub-memory unit; the common first electrode in the n-th-place second sub-memory unit is connected to the second bit line through the n-th-place second transistor for selection; and the second electrode of the m-th-place second memory cell is connected to the common m-th-place plate line, said method comprising performing reading out data stored in the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line and re-writing data into the first memory cell of the first sub-memory unit and the second memory cell of the second sub-memory unit which memory cells share the plate line by performing potential rising and potential falling once each.