Patent ID: 8458439
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A processor having an associated memory hierarchy including multiple levels of cache memory, said processor comprising: an instruction sequencing unit that sequences processing of compiled program code by the processor, wherein the compiled program code includes executable instructions, an operand data structure describing a plurality of sequentially processed computation blocks, and block computation commands invoking processing of the computation blocks, wherein the instruction sequencing unit asserts an initiation signal in response to detecting a block computation command in the compiled program code; at least one execution unit that, responsive to receipt of executable instructions of the complied program code from the instruction sequencing unit, executes the executable instructions; data storage that buffers the operand data structure, wherein the operand data structure includes a plurality of entries corresponding to operands of computation blocks to be performed by the processor, wherein a first entry among the plurality of entries specifies a first caching policy for a first operand and a second entry among the plurality of entries specifies a different second caching policy for a second operand, wherein the first caching policy identifies a first level among the multiple levels of cache memory to hold the first operand and the second caching policy identifies a second level among the multiple levels of cache memory to hold the second operand; and a computation engine that, responsive to assertion of the initiation signal, computes operands of one of the computation blocks and stores the computed operands in the memory hierarchy in accordance with the cache policies indicated within the operand data structure.