Patent ID: 6253359
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A method of fabricating an integrated circuit which contains a first plurality of signal lines in close proximity, such that capacitive coupling among the signal lines is operable to affect a delay time of a signal on a victim signal line of the first plurality of signal lines, the method comprising the steps of;creating a trial layout for the plurality of signal lines;assigning a coupling capacitance parameter to the victim signal line representative of a coupling capacitance between the victim signal line and an aggressor signal line from the first plurality of signal lines;compensating for a variation in delay time of the signal on the victim signal line due to simultaneous switching of a signal on the aggressor signal line by modifying the coupling capacitance parameter;simulating the operation of the trial layout using the modified coupling capacitance parameter to determine a total propagation delay time for the signal on the victim signal line;modifying the trial layout if the total propagation delay time for the signal on the victim signal line is not an allowable propagation delay time value; andfabricating the integrated circuit according to the modified trial layout.