Patent ID: 7200708
Filing Date: 2007-04-03
Classification: G11C

Abstract:
1. An apparatus, comprising: a memory device including a block of memory operable to store data, said memory device being adapted to at least partially erase said block of memory in a first erase cycle and in a second erase cycle subsequent to the first erase cycle, said memory device stores a first voltage increment threshold count and a second voltage increment threshold count associated with said block of memory, said memory device being further adapted to count a total number of erase pulses applied to said block of memory, said memory device being further adapted to apply an erase pulse to said block of memory during the first and the second erase cycles having an erase pulse voltage level based at least in part on the total number of erase pulses applied to said block of memory, the first voltage increment threshold count, and a second voltage increment threshold count.