Patent ID: 7999299
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of unit cells formed in a cell array region, the plurality of unit cells each comprising: a first peripheral circuit capacitor formed in a peripheral circuit region spaced apart from the cell array region, wherein the first peripheral circuit capacitor comprises a plurality of first capacitors connected to each other in parallel and formed at substantially the same level as the cell capacitor of the cell array region, each of the first capacitors including an upper electrode including a top surface and a lower electrode including a bottom surface, wherein the top surface of the cell capacitor is formed at substantially the same level as the top surfaces of the upper electrodes, and the bottom surface of the cell capacitor is formed at substantially the same level as the bottom surfaces of each of the lower electrodes; a first node of the first peripheral circuit capacitor electrically connected to at least a first portion of the lower electrodes of the first capacitors in the peripheral circuit region to connect the first portion of the first capacitors in parallel; and a second node of the first peripheral circuit capacitor electrically connected to at least a second portion of the upper electrodes of the first capacitors in the peripheral circuit region to connect the second portion of the first capacitors in parallel, wherein the first node of the first peripheral circuit capacitor comprises a first conductive layer that is formed in the peripheral circuit region at substantially the same level as the bit line of the cell array region.