Patent ID: 6420228
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method for the production of a DRAM cell configuration, which comprises:producing memory cells each having a read-out transistor and a storage capacitor with a storage node; producing bit and word lines; forming the read-out transistor as a vertical MOS transistor integrated in a substrate of semiconductor material; providing the MOS transistor with two first source/drain regions each belonging to a further, adjacent vertical MOS transistor, disposed separately one after the other along the bit line and adjoining the bit line, two second source/drain regions each connected to the storage node; producing two channel regions; producing a gate oxide adjoined by the two channel regions; producing a gate electrode between the two channel regions; adjoining exactly two opposite sides of the gate electrode with the gate oxide; electrically connecting the gate electrodes of adjacent MOS transistors along the word line; and placing the gate electrode and the storage node one under the other.