Patent ID: 8225075
Filing Date: 2012-07-17
Classification: G06F

Abstract:
1. A processor for shuffling data comprising: a decoder to decode a shuffle instruction; a register file including an integer register and a floating point register; a register renaming logic to rename the registers in the register file for the decoded instruction, the register file comprising a first 64-bit source register to store a first operand that comprises four data elements, a second 64-bit register to store a second source operand comprising a set of four 2-bit selection fields and a set of source select fields to indicate from the first source register of a plurality of source data registers a data element is to be provided, and a 64-bit destination register; a queue to store the register renamed instruction; a scheduler to schedule execution of operations of the register renamed instruction based on the readiness of the dependent operands in the source registers; an execution unit operative to receive from the register file the first operand and the set of selection fields, wherein each of said selection fields is associated with a data element location in the destination operand, and each of said selection fields being a position selection filed operative to select one of said data elements from the first operand to be copied to the destination operand; said execution unit is also operative to: copy data from a data element of the first operand based on an order designated by said individual 2-bit selection field to said associated destination data element position.