Patent ID: 8245065
Filing Date: 2012-08-14
Classification: G06F

Abstract:
1. A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive signals from and send signals to said instruction scheduling unit; and a state machine located within said execution unit, said method comprising the steps of: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, subsequent to obtaining the number of instructions per cycle, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; and power gating the microprocessor to gate off power to idle macros with a signal from said state machine when said instructions are independent of each other without incurring significant loss of performance until an instruction queue in the instruction scheduling unit is filled with instruction data.