Patent ID: 6493401
Filing Date: 2002-12-10
Classification: B60R,H04L

Abstract:
A receiving circuit for a digital data transfer system with differential data transfer via a bus having a first line and a second line, a first bit value of the transferred data having associated therewith a high potential on the first line and a low potential on the second line, and a second bit value of the transferred data having associated therewith a low potential on the first line and a high potential on the second line, the receiving circuit comprising:a first signal input connected to the first line, a second signal input connected to the second line, and a signal output; a first comparator circuit assembly for differential evaluation of first and second pulse signals received via the first and second lines, respectively, with the second pulse signal having an offset voltage superimposed thereon prior to said differential evaluation; the first comparator circuit assembly superimposing on the second pulse signal both a positive offset voltage and a negative offset voltage and having two comparator outputs, a first one of these comparator outputs delivering a first logic potential value when the first pulse signal exceeds a higher, first threshold value corresponding to the potential value of the second pulse signal increased by the positive offset voltage, and otherwise delivers a second logic potential value, and a second one of the comparator outputs delivering the first logic potential value when the first pulse signal exceeds a lower, second threshold value corresponding to the potential value of the second pulse signal reduced by the negative offset voltage, and otherwise delivers the second logic potential value; and a bistable multivibrator circuit connected between the outputs of the first comparator circuit assembly and the signal output, the bistable multivibrator circuit being switchable to a setting state by a change of the first or second comparator output to the first logic potential value, and to a resetting state by a change of the first or second comparator output to the second logic potential value.