Patent ID: 6657451
Filing Date: 2003-12-02
Classification: G01R

Abstract:
A method for entering an electronic test pattern into an integrated circuit, comprising the steps of:presenting a test forcing pattern on a subset of the circuit's external pins for driving the circuit to a test mode, said subset being arranged for also communicating non-test-related patterns with the circuit's functional interior, presenting the electronic test pattern to the circuit and executing the test proper, said method being characterized by the following steps: presenting said test forcing pattern on a single one circuit pin which is a member of said subset in the form of an aggregate of a clocking sequence and a transition signalling data sequence as data to an in-circuit storage element; clocking said storage element by a delayed version of said test forcing pattern; sequentially storing successive data parts of said pattern in said storage element under successive control of clock parts of said pattern as delayed; matching a predetermined string of said data parts as stored versus a standard pattern, and Upon finding a match driving said circuit to a test condition for therein executing a test procedure.