Patent ID: 8816273
Filing Date: 2014-08-26
Classification: G04F,H01J

Abstract:
1. A time-to-digital converter, comprising: an event frame latches and logic module having a plurality of memory cells; an analog front-end module connected to the event frame module; and a bin increment generator module connected to the event frame latches and logic module, wherein the bin increment generator module is configured to issue a sequence of bin increments to the event frame latches and logic module and wherein a successive bin increment follows a predecessor bin increment by a time interval, wherein the analog front-end module is configured to issue an event start indication to the event frame latches and logic module, wherein the analog front-end module is configured to issue at least one event stop indication to the event frame latches and logic module, wherein the event frame latches and logic module is configured to update at least one memory cell when the bin increment generator module issues a bin increment, and wherein the memory cell update comprises a first bit-type following the issue of the start event indication, and wherein the memory cell update comprises a second bit-type following the issue of the stop event indication.