Patent ID: 7287148
Filing Date: 2007-10-23
Classification: G06F,Y02D

Abstract:
1. An integrated circuit comprising: a reduced instruction set computer (RISC) controller to execute RISC instructions; one or more digital signal processing (DSP) units to execute DSP instructions; and a unified pipeline controller coupled to the RISC controller and the one or more DSP units, the unified pipeline controller to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified pipeline controller comprising a first portion of stages and a second portion of stages, the first portion providing a first depth for decoding and initiating the RISC instructions when the DSP instructions are inactive, and the first portion and the second portion together providing a second depth for decoding and initiating the DSP instructions when the RISC instructions are inactive.