Patent ID: 6236278
Filing Date: 2001-05-22
Classification: H03L,Y10S

Abstract:
An apparatus including a dual mode control circuit for a phase lock loop (PLL), comprising:a reference signal frequency divider circuit configured to couple to a PLL and receive at least one reference divider control signal and in accordance therewith receive and frequency divide an input reference signal having an input reference signal frequency and in accordance therewith provide one or more divided reference signals having one or more divided reference signal frequencies and phases;a feedback signal frequency divider circuit configured to couple to said PLL and receive at least one feedback divider control signal and in accordance therewith receive and frequency divide a PLL feedback signal having a PLL feedback signal frequency and in accordance therewith provide one or more divided feedback signals having one or more divided feedback signal frequencies and phases; anda control circuit, coupled to said reference and feedback signal frequency divider circuits, configured to couple to said PLL, receive a PLL lock signal from said PLL and receive and process one of said one or more divided feedback signals and in accordance therewith provide said at least one reference divider control signal and said at least one feedback divider control signal;wherein said control circuit, in accordance with said PLL lock signal, and said reference and feedback signal frequency divider circuits, in accordance with said at least one reference divider control signal and said at least one feedback divider control signal, transition between first and second circuit operation modes whensaid PLL lock signal indicates that said PLL has transitioned between unlocked and phase locked states of operation, andsaid processing of said one of said one or more divided feedback signals indicates that a phase difference between said one of said one or more divided feedback signal phases and a desired signal phase transitions between outside and inside of a predetermined phase difference range.