Patent ID: 7761828
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. A computer-based method of simulating an integrated circuit design in a testbench, the method comprising: read in netlist and timing data for the design; flatten the design, thereby obtaining a flattened design; store a data structure in a computer readable medium, the data structure comprising a plurality of cells, one cell per circuit element of the flattened design, each cell of the plurality of cells comprising timing and connectivity information for the circuit element associated with said each cell, said each cell further comprising an input periphery (N identify, from the information in the data structure, one or more primary inputs of the circuit design, each primary input of the one or more primary inputs having direct interaction with the testbench; forward trace from said each primary input until an edge triggered flip-flop (ETFF) is encountered; for said each primary input, turn on the N for said each primary input, add the ETFF encountered in the step of forward tracing from said each primary input to a first linked list of ETFFs to be placed in a single subset; select N′, N′ being greater than or equal to N; create a master list S of all ETFFs in the data structure, the master list S comprising a first group of ETFFs of the circuit design and a second group of ETFFs of the circuit design, the first group of ETFFs comprising all ETFFs having N divide the master list into (n−1) primary subsets {S( for each ETFF in each primary subset of the (n−1) subsets, first backtrace from an input of said each ETFF in said each primary subset stopping when another ETFF is encountered, wherein N for said each primary subset, create a master association set S* by merging all the association sets; create a master testbench association set T* by merging all the testbench subsets; turn on the N for said each primary subset, for each completion set, create a corresponding netlist module, thereby obtaining a plurality of netlist modules; implement clock (CLK) inputs to the plurality of netlist modules; load each netlist module of the plurality of netlist module onto a different computer of a plurality of networked computers, each networked computer of the plurality of networked computers configured to have access to a different memory and a different circuit simulator; simulate said each netlist module on the computer associated with said each netlist module; merge results of the step of simulating, thereby obtaining merged simulation results; and provide user access to the merged simulation results.