Patent ID: 6638849
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A process for forming semiconductor devices containing a metal interconnect and a low-K (low dielectric constant) dielectric layer on a wafer, said low-K dielectric layer having a dielectric constant lower than that of SiO2, and said process comprising the steps of:(a) forming a silica glass layer on a wafer surface; (b) photolithographically patterning said silica glass layer according to a pattern intended for a metal interconnect; (c) conformably depositing a spacer dielectric layer on said silica glass layer; (d) anisotropically etching said spacer dielectric layer to form a sidewall spacer on the sidewall of the silica glass layer; (e) depositing a low-K dielectric material on said wafer to form a low-K dielectric layer, covering said silica glass layer and said sidewall spacer, followed by planarizing said low-dielectric layer by chemical-mechanical polishing (CMP); (f) photolithographically removing said silica glass layer to form a trench in said low-K dielectric layer; (g) depositing a conductive metal layer to fill said trench; and (h) planarizing said conductive metal layer.