Patent ID: 6801080
Filing Date: 2004-10-05
Classification: H03K

Abstract:
A differential input buffer comprising:a true differential input and a complement differential input; a clamp circuit that receives the true differential input and the complement differential input and outputs a true clamped differential input and a complement clamped differential input, wherein the clamp circuit outputs a lower limit voltage as the true clamped differential input when the true differential input is below a minimum input voltage, wherein the clamp circuit outputs the lower limit voltage as the complement clamped differential input when the complement differential input is below the minimum input voltage; and a differential stage, receiving the true and complement clamped differential inputs from the clamp circuit, and outputting a true and a complement differential output, wherein the differential stage comprises: a first tail current sink; a first differential transistor having a gate that receives the true clamped differential input and a source connected to the first tail current sink; a first middle transistor having a gate that receives a middle voltage between voltages of the true clamped differential input and the complement clamped differential input, and a source connected to the first tail current sink; a second tail current sink; a second differential transistor having a gate that receives the complement clamped differential input and a source connected to the second tail current sink; a second middle transistor having a gate that receives the middle voltage and a source connected to the second tail current sink; and a middle current source for generating a current that branches to the first and second middle transistors, whereby the true and complement differential inputs are clamped to the lower limit voltage before being applied to the differential stage.