Patent ID: 6944062
Filing Date: 2005-09-13
Classification: G11C,H01L

Abstract:
1. A transistor comprising: a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other; a first insulation layer formed on a top of said projection; a pair of counter-conductivity type source/drain regions formed on a surface of said semiconductor substrate at opposite sides of said projection; second insulation layers each covering one of the pair of side walls of said projection and one of said pair of source/drain regions; a pair of floating gates respectively formed on the pair of side walls of said projection and facing said pair of side walls and said pair of source/drain regions via respective second insulation layers; third insulation layers each being formed on one of said pair of floating gates; and a control gate facing said pair of floating gates via said third insulation layers and facing the top of said projection via said first insulation layer; wherein said second insulation layers and said third insulation layers each are configured to have a larger capacitance than said first insulation layer, and a delete voltage for deleting charges stored in said floating gates is applied between said control gate and said source/drain regions to thereby cause a delete current to flow toward said control gate or said source/drain regions, the charges stored being deleted.