Patent ID: 6876319
Filing Date: 2005-04-05
Classification: H03C,H03D,H03H

Abstract:
1. An integrated demodulator and decimator circuit for processing digital samples of a received signal having a predetermined intermediate frequency (IF) and sampled at a sample rate based on a clock having a frequency that is four times the IF, said integrated demodulator and decimator circuit comprising: a digital sign inverter that sign inverts selected digital samples according to a predetermined phase-shift pattern and that outputs demodulated digital samples at said sample rate; and a decimator, comprising a symmetric half-band FIR filter with a plurality of taps including alternate zero and non-zero taps and a center tap, wherein said demodulated digital samples are sequentially shifted through said plurality of taps at said sample rate, and wherein said decimator outputs complex digital values at half said sample rate including real output values based on demodulated digital samples shifted into alternate taps and corresponding imaginary output values based on demodulated digital samples shifted into said center tap.