Patent ID: 6114717
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A solid-state imaging device comprising:photoelectric converter elements arranged in a matrix array;vertical charge-transfer sections arranged along respective columns of said matrix array;a horizontal charge-transfer section disposed at output-side ends of said vertical charge-transfer sections;an output section disposed at an output-side end of said horizontal charge-transfer section;said photoelectric converter elements converting incident light to electric signal charges;said vertical charge-transfer sections transferring said signal charges to said horizontal charge-transfer section according to a first driving signal;said horizontal charge-transfer section transferring said signal charges to said output section according to a second driving signal, generating an output electric signal;said vertical charge-transfer sections including a first plurality of buried channel regions extending along said respective vertical charge-transfer sections and a first plurality of gate electrodes arranged along said respective vertical charge-transfer sections over said first plurality of buried channel regions, said first buried channel regions extending from corresponding ends of said first plurality of gate electrodes;said horizontal charge-transfer section including a second buried channel region extending along said horizontal charge-transfer section and a second plurality of gate electrodes arranged along said horizontal charge-transfer section over said second buried channel region;said second buried channel region having a same conductivity type as that of said first plurality of buried channel regions and a different doping concentration from that of said first plurality of buried channel regions; andsaid first plurality of buried channel regions being connected to said second buried channel region via a single interface between each of said first plurality of buried channel regions and a corresponding one of said second buried channel region, said single interface being aligned with one of said corresponding ends of said first plurality of gate electrodes.