Patent ID: 8238177
Filing Date: 2012-08-07
Classification: G11C

Abstract:
1. An integrated circuit comprising: a plurality of memory cells; a plurality of fuses; a redundant memory having a function of repairing a defective cell included in the plurality of memory cells by placing a corresponding fuse among the plurality of fuses into a first state; a fuse data conversion circuit that generates first information of a first defective cell based on position information of the fuse placed into the first state, the fuse corresponding to the first defective cell having been repaired; a repair data generation circuit that generates, upon detection of a second defective cell as a result of a test for the plurality of memory cells, repair information for repairing the second defective cell according to the first information of the first defective cell and second information of the second defective cell detected; and a fuse state change circuit that places a predetermined fuse among the plurality of fuses into the first state according to the repair information generated by the repair data generation circuit.