Patent ID: 7225288
Filing Date: 2007-05-29
Classification: G06F

Abstract:
1. A USB (Universal Serial Bus) host controller comprising: an enhanced host controller adapted to control a USB high-speed data traffic; at least one companion host controller adapted to control a USB full-speed and/or low-speed data traffic; and a USB transceiver macrocell connected to said enhanced host controller to handle the data transfer to and from a USB device; wherein the enhanced host controller comprises a register file, the register file including first registers adapted to store data with respect to host controller capabilities and operational modes and second registers adapted to store data with respect to at least one of said full-speed and/or low-speed test functions, wherein at least one of said second registers is a control register storing data indicating one of said full-speed and/or low-speed test functions, wherein said control register is adapted to store a flag indicating whether said one of said full-speed and/or low-speed test functions is currently being performed; wherein said enhanced host controller comprises a test circuit for controlling said USB transceiver macrocell to perform full-speed and/or low-speed test functions; wherein said USB transceiver macrocell is configured to handle an NRZI (Non Return to Zero Invert) data transfer of K and J states, and said full-speed and/or low-speed test functions comprise a test function forcing said USB transceiver macrocell to repetitively transmit a full-speed or low-speed test pattern until an exit action is taken; and wherein said full-speed or low-speed test pattern is a concatenation of four KJ state pairs, two single-ended-zero signals, and two J states.