Patent ID: 6197642
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method for manufacturing a gate terminal, comprising the steps of:providing a substrate having an isolation structure thereon;forming a silicon nitride layer on the substrate, at least covering the isolation structure;forming an oxide layer over the silicon nitride layer;patterning the oxide layer and the silicon nitride layer to form an opening exposing a portion of the substrate, wherein the opening serves a gate region;forming a gate oxide layer over the exposed substrate in the gate region;forming a crystalline silicon layer having a thickness of 200 Angstroms to 300 Angstroms in the gate region over the sidewalls of the oxide layer and over the exposed gate oxide layer, by using a lower pressure vapor deposition method;forming a metallic layer inside the gate region, the crystalline silicon layer being worn away during the metal deposition;removing the oxide layer to expose the silicon nitride layer by using the silicon nitride layer as a stop layer;removing the silicon nitride layer;forming lightly doped source/drain regions in the substrate on each side of the metallic layer via ion implantation;forming spacers on two sidewalls of the metallic layer; andforming heavily doped source/drain region in the substrate on the sides of the spacers via ion implantation.