Patent ID: 7194601
Filing Date: 2007-03-20
Classification: G06F

Abstract:
1. A processor comprising: fetch logic for fetching an encoded instruction; first decoder logic capable of decoding a plurality of encoded instructions of a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic; second decoder logic capable of decoding a plurality of encoded instructions of a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic, wherein instructions of the first instruction set are of a different length than instructions of the second instruction set; decoder control logic configured to selectively control active operation of the first decoder logic and the second decoder logic, such that when the first decoder logic is decoding an instruction then the second decoder logic is operated in a lower-power, inactive mode, and when the second decoder logic is decoding an instruction then the first decoder logic is operated in a lower-power, inactive mode; and logic for directing an instruction from the fetch logic to either the input of the first decoder or the input of the second decoder, based upon whether the instruction is an instruction of the first instruction set or an instruction of the second instruction set.