Patent ID: 6548851
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A semiconductor memory device having a memory cell array area and a peripheral circuit area, comprising:a first resistor device formed in the peripheral circuit area when a landing pad is formed to contact an impurity diffusion region of an access transistor in the memory cell array area; a first interlevel insulation layer formed on the overall surface of the semiconductor substrate having the first resistor device formed thereon; a bit line formed in the memory cell array region on the first interlevel insulation layer; a second interlevel insulation layer formed on the overall surface of the semiconductor substrate having the bit line formed thereon; a lower electrode formed in the memory cell array area in contact with the landing pad; and a second resistor device formed on a part of the second interlevel insulation layer in the peripheral circuit area when a capacitor upper electrode is formed in the memory cell array area.