Patent ID: 8878203
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A switching circuit, comprising: a semiconductor substrate having an active area; a gate insulation layer disposed on the active area; a gate electrode layer disposed on the gate insulation layer; first and second transistors each having a different gate formed in the gate electrode layer, a different drain region formed in the semiconductor substrate, and a shared source region formed in the semiconductor substrate; a plurality of intermediate wiring layers stacked above the gate electrode layer; a first via wiring layer making electrical connections between regions in the semiconductor substrate and a first wiring layer that is the intermediate wiring layer closest to the semiconductor substrate; a plurality of intermediate vias each disposed between the intermediate wiring layers to form electrical connections between the intermediate wiring layers; a plurality of source wires arrayed in a first direction and extending in a second direction that is substantially orthogonal to the first direction, and electrically connected to the shared source region of the first and second transistors; a plurality of drain wires arrayed in the first direction and extending in the second direction, and electrically connected to the drain regions of the first and second transistors, wherein the first wiring layer is directly underneath the drain wires with no intermediate wiring layers interposed between the first wiring layer and the drain wires and the first wiring layer is directly underneath the source wires with no intermediate wiring layers interposed between the first wiring layer and the source wires.