Patent ID: 6314443
Filing Date: 2001-11-06
Classification: G06F

Abstract:
Data processing apparatus comprising:(i) an instruction decoder responsive to data processing instruction words to generate processing control signals; and(ii) processing logic controlled by said processing control signals to perform data processing operations upon data operand words; wherein(iii) said instruction decoder is responsive to a first instruction word to generate control signals to control said processing logic to perform a data processing operation upon a first N-bit data operand word P and a second N-bit data operand word Q to generate a result N-bit data word R as given by:R=Sat(Fun(P)+Q),whereSat (X) is a function returning a saturated value of X; andFun (X) is a function operative for at least those values of X that may be generated by an N/2-bit by N/2-bit signed multiplication to return a value obtained by shifting X by a shift amount to generate a shifted word and saturating said shifted word.