Patent ID: 8441380
Filing Date: 2013-05-14
Classification: H03M

Abstract:
1. An apparatus comprising: a sample-and-hold (S/H) circuit that is configured to generate a sample voltage from an input signal, wherein the S/H circuit is controlled by a sample clock signal; a digital-to-analog converter (DAC) that is coupled to an output terminal of the S/H circuit so as to apply at least one of a plurality of applied currents to the output terminal of the S/H circuit; a comparator that is coupled to the output terminal and that receives a reference voltage; a counter that is configured to determine the length of a first interval over which a first voltage on an output terminal of the S/H circuit changes from the sample voltage to the reference voltage using a first applied current of the plurality of applied currents from the DAC; and a controller that is coupled to the comparator, the DAC, the counter, and the S/H circuit, wherein the controller provides the sample clock signal to the S/H circuit, and wherein the controller provides a clock signal to the counter, and wherein the controller is configured to adjust the DAC to provide a second applied current after the first voltage on the output terminal of the S/H circuit reaches the reference voltage, and wherein the counter, during a sample period of the sample clock associated with the sample voltage, is configured to determine the length of a second interval over which a second voltage on the output terminal of the S/H circuit changes from the sample voltage to the reference voltage using the second applied current of the plurality of applied currents from the DAC.