Patent ID: 6150679
Filing Date: 2000-11-21
Classification: G06T,G09G

Abstract:
a first-in-first-out (FIFO) memory device comprising:a first memory element, the first memory element receiving a first set of entries from an input port of the FIFO memory device and storing each of the entries of the first set in a storage location in the first memory element addressed by a write pointer device;a second memory element, the second memory element receiving a second set of entries from the input port of the FIFO memory device and storing each of the entries of the second set in a storage location in the second memory element addressed by the write pointer device;a first read pointer device, the first read pointer device determining first read pointer addresses in the first memory element, the first read pointer addresses being used to address storage locations in the first memory element for reading entries of the first set of entries out of storage locations in the first memory element, the entries read out of the first memory element being output from the FIFO memory device via a first output port of the FIFO memory device; anda second read pointer device, the second read pointer device determining whether any of the entries of the second set are tagged entries, the second read pointer device calculating second read pointer addresses based on any tagged entries in the second set, the second read pointer device using the second read pointer addresses for reading the tagged entries of the second set out of their respective storage locations in the second memory element, the tagged entries read out of the second memory element being output from the FIFO memory device via a second output port of the FIFO memory device.