Patent ID: 7304348
Filing Date: 2007-12-04
Classification: H01L

Abstract:
1. An LDMOS transistor comprising a source region ( 3 ), a drain region ( 5 ), a control gate ( 9 ) and a drift zone ( 20 ) extending between the drain region ( 5 ) and the control gate ( 9 ), wherein formed in the drift zone ( 20 ) is a first LDD region ( 22 ) of the same conductivity type as that of the drain region ( 5 ), characterised in that a cover layer ( 24 ) is provided over the first LDD region ( 22 ) and that the cover layer ( 24 ) is of the conductivity type opposite to the conductivity type of the first LDD region ( 22 ), and in that a second LDD region ( 26 ) more highly doped in relation to the first LDD region ( 24 ) is disposed at the gate end of the first LDD region ( 22 ), and compensates at least partially the doping of the cover layer ( 24 ).