Patent ID: 7765512
Filing Date: 2010-07-27
Classification: G06F

Abstract:
1. A system for implementing circuits in programmable logic of an integrated circuit device, comprising: a processor that accesses an address space with read and write transactions issued on an interface bus; a configuration port of the programmable logic coupled to an array of programmable logic and interconnect resources of the programmable logic, wherein the programmable logic and interconnect resources are configurable via the configuration port; a relocatable circuit implemented in a selected one of a plurality of regions within the array by configuring the programmable logic and interconnect resources in the selected region with configuration data via the configuration port; and an interface circuit coupled between the interface bus and the relocatable circuit, wherein the interface circuit translates the transactions accessing a portion of the address space assigned to the relocatable circuit into a fixed address space of the relocatable circuit, and the configuration data for implementing the relocatable circuit is independent of the portion of the address space assigned to the relocatable circuit.