Patent ID: 6711055
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device, comprising:a plurality of banks including respective memory cell arrays independent of each other; a password storage area that is associated with one of the banks; a bank decoder which generates a bank selection signal by decoding a bank address; a first bank selection circuit which outputs a write instruction or a read instruction to said one of the banks; a plurality of second bank selection circuits which outputs a write instruction or a read instruction to the respective banks except for said one of the banks; and a command-decode-&-bank-control circuit which controls the first and second bank selection circuits such that receipt of a first command causes one of the first and second bank selection circuits selected by the bank selection signal to output a write instruction or a read instruction, and such that receipt of a second command causes the first bank selection circuit to output a write instruction independently of the bank selection signal, and causes one of the second bank selection circuits selected by the bank selection signal to output a read instruction.