Patent ID: 7640281
Filing Date: 2009-12-29
Classification: H03M

Abstract:
1. A method using a signal processing circuit to reduce delay in signal processing of a predictive digital control system, for use in a real time control system, said method comprising: modulating a signal output from a digital controller to create a staircase approximation of a digital first order hold (DFOH) by combining digital up sampling with linear staircase data insertion and a zero order hold to create a first order hold mechanism; outputting the modulated signal to a digital-to-analog converter (DAC); filtering a signal output from the DAC utilizing a reconstruction filter to attenuate noise in the signal output from the DAC; wherein the modulating the signal output from the digital controller comprises reducing the size of the plurality of steps included in the staircase approximation, and increasing a fundamental frequency of the signal output from the digital controller, to reduce delay through the reconstruction filter while filtering digital noise from the signal; and wherein the reducing the size of the plurality of steps and increasing the fundamental frequency includes modulating the signal in accordance with at least one of the formulas: where n=an integer≧0, N=an up-sampling ratio, j=an integer≧0<N, T=a base sample period, r=the input signal, and m=partial rate first order hold constant.