Patent ID: 8847812
Filing Date: 2014-09-30
Classification: G04F,H03K,H03M

Abstract:
1. A time-to-digital conversion stage, comprising: a time-to-digital conversion circuit configured to output a digital signal having an n-bit width, which represents an integer value ranging from −(2 a time difference amplifier circuit configured to receive the first and the second signals, to amplify the phase difference between the first and the second signals received 2 a delay adjustment circuit configured to receive the two resultant signals output from the time difference amplifier circuit, to add a phase difference dependent on the digital signal to the two resultant signals received, and to output another two resultant signals; an output detection circuit configured to detect that the delay adjustment circuit has output the another two resultant signals, and to output a detection signal; and a storage circuit configured to latch the digital signal in synchronism with the detection signal.