Patent ID: 7176082
Filing Date: 2007-02-13
Classification: H01L

Abstract:
1. An integrated circuit including a capacitive structure that includes an upper layer wholly disposed on a first plane having a first capacitor electrode section therein, formed according to the process of: (a) forming a capacitor dielectric layer adjacent the upper layer, the capacitor dielectric layer wholly disposed on a second plane and completely covering the first capacitor electrode section, (b) forming a second capacitor electrode layer including a second capacitor electrode section adjacent the capacitor dielectric layer, the second capacitor electrode section wholly disposed on a third plane and at least partially covering the first capacitor electrode section and having an edge portion extending beyond the underlying first capacitor electrode section, the capacitor dielectric layer disposed between the first capacitor electrode section and the second capacitor electrode section and completely underlying the second capacitor electrode section, where the first plane, the second plane, and the third plane are not coplanar, (c) forming an upper dielectric layer adjacent the second capacitor electrode section, (d) selectively removing portions of the upper dielectric layer to form a first via cavity extending through the upper dielectric layer and at least to the edge portion of the second capacitor electrode section, thereby exposing the edge portion of the second capacitor electrode section within the first via cavity, where the via cavity does not overlie any portion of the first capacitor electrode section, and no via cavities to the second capacitor electrode section overlie the first capacitor electrode section at a point where the via cavities intersect the second capacitor electrode section, and (e) filling the first via cavity with a via metal, the via metal making electrical connection with the edge portion of the second capacitor electrode section exposed within the first via cavity.