Patent ID: 6066997
Filing Date: 2000-05-23
Classification: H03B,H03C

Abstract:
A frequency multiplier for inputting an input signal to a transistor through an input matching circuit and outputting a multiplied output signal from said transistor through a reflecting type fundamental wave signal band suppressing circuit and an output matching circuit, said frequency multiplier comprising:a transmission line disposed between an output terminal of said transistor and an input terminal of said reflecting type fundamental wave signal band suppressing circuit, for producing a standing wave therebetween, wherein:a length of said transmission line is set so that a fundamental wave signal output from said transistor and a reflection signal are in a phase relationship such that said fundamental wave signal and said reflection signal superimpose each other and are strengthened, the reflection signal resulting from said fundamental wave signal being reflected by said reflecting type fundamental wave signal band suppressing circuit and reflected again at said output terminal of said transistor, andsaid length of said transmission line is set so that a phase difference .phi.d between said fundamental wave signal and said reflection signal lies within a range defined byn.times.360-120.ltoreq..phi.d.ltoreq.n.times.360+120wherein n (n.gtoreq.0) is an integer.