Patent ID: 6836425
Filing Date: 2004-12-28
Classification: G11C

Abstract:
A coding cell of a nonvolatile ferroelectric memory device, comprising:a first latch having one node connected with a first node and the other node connected with second and third nodes; a first transistor having a gate terminal to which a gate control signal is input, a source terminal to which a signal of the second node is transferred, and a drain terminal to which a first data signal is input; a second transistor having a gate terminal to which the gate control signal is input, a source terminal to which a signal of the third node is transferred, and a drain terminal to which a second data signal is input; a second latch having one node connected with a fourth node and the other node connected with the second and third nodes; a first ferroelectric capacitor arranged between an input terminal of a control signal and the second node; a second ferroelectric capacitor arranged between the input terminal of the control signal and the third node; a third ferroelectric capacitor arranged between the second node and a voltage terminal; and a fourth ferroelectric capacitor arranged between the third node and the voltage terminal.