Patent ID: 8578103
Filing Date: 2013-11-05
Classification: G06F

Abstract:
1. A coherency control system, comprising: a logical-physical address translation unit which translates a logical address including a first tag, an index address and an offset address of a first storage unit of a set associative system into a physical address of a second storage unit, the physical address including a second tag, the index address and the offset address; a request output unit which transmits a load request including at least the physical address and a way number of a way to which an area of the first storage unit designated by the logical address corresponding to said physical address belongs; a corresponding state storage unit which stores a relation state between an area of the second storage unit and an area of the first storage unit, when receiving the load request, by storing the second tag in the physical address included in the load request received, in the area designated based on the way number included in the load request and the index address of the physical address also included in the load request; and an invalidation instructing unit which includes a command register which holds information indicating the load request or information indicating a store request, an address register which holds the physical address included in the load request or the store request, a way number register which holds the way number included in the load request, a decoder which outputs a load request signal or a store request signal and a determination circuit which performs comparative determination of the second tag of the physical address included in the store request and the second tag stored in the corresponding state storage unit, receives the store request including the physical address, and outputs, when detecting the second tag of the physical address included in said store request received and any of the second tags stored in the area corresponding to the index address of the physical address included in said store request among the second tags stored in the corresponding state storage unit are identical, the index address and an invalidation signal corresponding to the way number of the area, where the second tag detected as identical is stored, as an invalidation instruction.