Patent ID: 6670825
Filing Date: 2003-12-30
Classification: H03K

Abstract:
A logic device having a two-dimensional array of intersecting rows and columns of logic super-regions, each of the super-regions including a plurality of logic regions, the logic device comprising:a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows that convey signals between the logic super-regions; said horizontal inter-super-region interconnection conductors being distributed in groups throughout the logic regions; a plurality of horizontal inter-region interconnection conductors that are associated with each of the logic regions for conveying signals between the logic regions; said horizontal inter-region interconnection conductors being distributed in subsets throughout the logic regions; and a plurality of different adjacent interconnection blocks that are associated with each of the logic regions, each of said adjacent interconnection blocks including substantially different interconnection resources that route signals between the logic regions.