Patent ID: 6319800
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method of fabricating an integrated circuit memory cell comprising first and second access transistors and first and second pull-down transistor, the method comprises:forming a single uninterrupted active area, the single active area defining first and second active area strips, the first and second active area strips are formed essentially parallel to each other;doping first and second separated regions of the first active area strip to define source and drain regions of the first access transistor;forming a wordline perpendicular to the first and second active area strips, the wordline forming a gate of the first access transistor;doping a third region of the first active area strip to define a source region of the first pull down transistor, the second region defining a drain of the first pull down transistor;fabricating a gate of the first pulldown transistor, the gate of the first pulldown transistor is essentially parallel to the wordline;doping fourth and fifth separated regions of the second active area strip to define source and drain regions of the second access transistor, the wordline forming a gate of the second access transistor;doping a sixth region of the second active area strip to define a source region of the second pull down transistor, the fifth region defining a drain of the first pull down transistor;fabricating a gate of the second pulldown transistor, the gate of the second pulldown transistor is essentially parallel to the wordline; andwherein the first and second pulldown transistors are located on a same side of the wordline in a plan view.