Patent ID: 8850280
Filing Date: 2014-09-30
Classification: G01R

Abstract:
1. An integrated circuit comprising: scan test circuitry; and additional circuitry subject to testing utilizing the scan test circuitry; the scan test circuitry comprising at least one scan chain having a plurality of scan cells; the scan test circuitry further comprising scan enable timing control circuitry coupled between a scan enable input of the scan test circuitry and scan enable inputs of respective ones of the scan cells; wherein the scan enable timing control circuitry is operative to control timing of a transition between a scan shift configuration of the scan cells and a functional data capture configuration of the scan cells by generating a delayed version of a scan enable signal applied to the scan enable input of the scan test circuitry to delay a change in a logic level of the scan enable signal from a first logic level associated with the scan shift configuration to a second logic level associated with the functional data capture configuration until after both a first clock pulse and a rising edge of a second clock pulse ordinarily used for functional data capture in the functional data capture configuration are applied to the scan cells in the scan shift configuration so as to permit the first and second clock pulses to capture values at respective scan inputs of the scan cells during testing of the scan cells in the scan shift configuration.