Patent ID: 7375565
Filing Date: 2008-05-20
Classification: G06F,G11C,H03L

Abstract:
1. A delayed lock loop for preventing a stuck fail in a dead-zone, comprising: a clock buffering block for receiving an external clock signal and a reverse external clock signal and generating a first and a second internal clock signals; a phase comparison block including a first phase comparator and a feedback delay block coupled to a second phase comparator, the first phase comparator and the second phase comparator concurrently comparing a phase of a delayed feedback signal with a phase of the external clock signal and a phase of a feedback signal with a phase of the external clock signal, respectively, the feedback delay block delaying the feedback signal by a first predetermined value to produce the delayed feedback signal; a clock selecting block for selecting one of the first and second internal clock signals based on a first comparison result of the delayed feedback signal and the external clock signal to thereby generate a selected internal clock signal; a stuck checking block for determining a delay value based on a second comparison result of the feedback signal and the external clock signal and the first comparison result of the delayed feedback signal and the external clock signal; a delay line block for delaying the selected internal clock signal by the delay value; and an output buffer for buffering an outputted signal from the delay line block to thereby generating a DLL clock signal.