Patent ID: 6576147
Filing Date: 2003-06-10
Classification: G03F

Abstract:
A method of layout compaction, comprising:a layout compaction step for compacting an input layout pattern based on a compaction condition and generating a compacted layout pattern; a first verification step for receiving the input layout pattern and the compacted layout pattern as data, verifying that the compacted layout pattern performs a proper circuit operation by comparing the input layout pattern and the compacted layout pattern, in case where any problem is detected, a first error data is outputted; an optical proximity correction step for carrying out an optical proximity correction based on an optical proximity correction condition on the compacted layout pattern and generating an optical proximity corrected layout pattern; and a second verification step for receiving the compacted layout pattern and the optical proximity corrected layout pattern as data, obtaining a finish pattern to be formed on a wafer by the optical proximity corrected layout pattern, and verifying that the optical proximity corrected layout pattern is properly formed by comparing the compacted layout pattern and the finish pattern, and in case where any problem is detected, outputting a second error data, wherein the generation of the compaction condition is controlled based on the first error data and the second error data.