Patent ID: 6339817
Filing Date: 2002-01-15
Classification: G11C

Abstract:
A semiconductor memory device comprising, on a single semiconductor chip:a set of input/output pins; a main memory portion including a plurality of first memory cells arranged in rows and columns; a plurality of first data transfer bus lines each coupled in common to the first memory cells arranged in an associated column; a sub memory portion including a plurality of second memory cells arranged in rows and columns, each of said second memory cells having first and second ports; a plurality of second data transfer bus lines each coupled in common to the first ports of the second memory cells arranged in an associated column; a plurality of bit lines each coupled in common to the second ports of the second memory cells arranged in an associated column; a selection circuit coupling, when activated, selected ones of said plurality of bit lines to said input/output pins to perform a first data transfer therebetween; a transfer circuit coupling, when activated, said first and second data transfer bus lines to each other to perform a second data transfer therebetween; and a control circuit activating said selection circuit during said transfer circuit being activated to allow said first data transfer to be performed during said second data transfer being performed.