Patent ID: 9024668
Filing Date: 2015-05-05
Classification: G05F,G11C,H03K,H03L

Abstract:
1. A clock generation circuit of a semiconductor apparatus, comprising: a first delay line configured to delay a first clock and generate a first delayed clock which swings between a level of a power supply voltage and a level of a set voltage; a second delay line configured to delay a second clock and generate a second delayed clock which swings between the level of the set voltage and a level of a ground voltage; a regulator configured to supply the set voltage to the first delay line and the second delay line; a delay modeling unit configured to delay the first delayed clock by a model delay amount and output a delay modeling clock; a phase comparison unit configured to compare phases of the first clock and the delay modeling clock and output a comparison signal; and a control unit configured to output a control signal in response to the comparison signal, such that the same delay amount is set for the first delay line and the second delay line.