Patent ID: 6238981
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A process for forming an MOS-gated device having self-aligned trenches, said process comprising:(a) forming a screen oxide layer on an upper layer of a semiconductor substrate;(b) forming a nitride layer on said screen layer;(c) using a well mask, patterning and etching said nitride layer, thereby defining a well region in the masked upper layer of the substrate;(d) implanting and diffusing ions of a first conductivity type into the masked upper layer, thereby forming a well region in said upper layer;(e) implanting and diffusing ions of a second, opposite conductivity type into the well region of the masked upper layer under conditions effective to form a source region extending to a selected depth in said upper layer, said selected depth defining a source-well junction;(f) removing the well mask, thereby exposing the portion of the nitride layer previously underlying said mask;(g) forming an oxide insulating layer substantially overlying said well and source regions, said insulating layer forming a hard mask over a portion of the upper layer;(h) etching said portion of the nitride layer and screen oxide layer underlying said nitride layer portion, thereby exposing the portion of the upper layer not masked by the oxide insulating layer,(i) etching said portion of the upper layer not masked by the oxide insulating layer, thereby forming a gate trench extending into the upper layer to a selected depth below the well region;(j) forming sidewalls and a floor comprising an insulator in said trench;(k) filling the gate trench with a semiconductor material, and planarizing the semiconductor material in said trench to a surface substantially coplanar with an upper surface of the oxide insulating layer;(l) forming an interlevel dielectric layer on the planarized semiconductor material in said trench and the upper surface of the oxide insulating layer;(m) forming a contact window mask on the interlevel dielectric layer and etching said interlevel dielectric layer and said oxide insulating layer, thereby forming contact openings to the gate trench semiconductor material and the source region;(n) through said contact openings, simultaneously etching the gate trench semiconductor material and the source region, said source region being etched to a depth substantially corresponding to the depth of said source-well junction;(o) implanting ions of said first conductivity type through said contact openings into the gate trench semiconductor material and the source region;(p) removing said contact window mask and depositing metal on said interlevel dielectric layer and in said contact openings; and(q) patterning said metal to form discrete source and gate connectors.