Patent ID: 7232729
Filing Date: 2007-06-19
Classification: H01L

Abstract:
1. A method of fabricating a doped semiconductor region comprising: selectively implanting a first impurity of a first conductivity type to form a first heavily doped region; selectively implanting said first impurity to form a second heavily doped region, wherein said second region is disposed laterally within said first region and vertically within and below said first region, and wherein said second region is more heavily doped than said first region; selectively implanting a second impurity of a second conductivity type to form a third doped region, wherein said second impurity has a higher diffusivity than said first impurity, and wherein said second conductivity type is not the same as said first conductivity type, wherein said third region is disposed within said second heavily doped region and within and vertically below said first region, wherein said first, second and third doped regions form a compound doped region; and annealing, wherein a doping profile of said second heavily doped region is graded along a junction region, wherein said graded doping profile results in decreased junction capacitance.