Patent ID: 6990028
Filing Date: 2006-01-24
Classification: G11C,H01L

Abstract:
1. A semiconductor memory comprising: a memory cell array having a memory cell; a sense amplifier to read/write data from/in the memory cell array; a pair of bit lines to connect the memory cell to the sense amplifier; a bit line equalizer to equalize potentials of the pair of bit lines; and a sense amplifier equalizer to equalize potentials of two power supply nodes of the sense amplifier, wherein the sense amplifier equalizer comprises MOS transistors whose gate oxide films have different thicknesses; and wherein the MOS transistors comprises, a thin film type transistor which short-circuits the two power supply nodes, and a thick film type transistor which has a gate oxide film thicker than that of the thin film type transistor and applies a precharge potential to the two power supply nodes.