Patent ID: 6528366
Filing Date: 2003-03-04
Classification: H01L

Abstract:
A method for fabricating a capacitor comprising:providing a plurality of contact plugs through an insulating layer to semiconductor device structures in a substrate wherein said contact plugs are formed in a logic area of said substrate and in a memory area of said substrate; forming a plurality of metal lines and via plugs through a plurality of insulating layers vertically contacting one another and contacting said contact plugs in said logic area wherein said insulating layers are also deposited vertically in said memory area; depositing an oxide layer overlying topmost of said metal lines and via plugs in said logic area and topmost of said insulating layers in both said logic area and said memory area; patterning openings through said oxide layer and said plurality of insulating layers in said memory area whereby a top portion of said contact plugs in said memory area is exposed; depositing a first conducting layer conformally within said openings and contacting said exposed top portion of said contact plugs wherein said first conducting layer and said exposed said contact plugs in said memory area together form a capacitor bottom plate electrode; thereafter partially filling said openings with a protective layer and etching back a top portion of said first conducting layer on upper sidewalls of said openings 2000 to 3000 Angstroms; removing said protective layer; thereafter depositing a capacitor dielectric layer overlying said first conducting layer; depositing a second conducting layer overlying said capacitor dielectric layer; and removing said second conducting layer and said capacitor dielectric layer except within said openings to complete formation of said capacitor in the fabrication of said integrated circuit device.