Patent ID: 6800893
Filing Date: 2004-10-05
Classification: H01L

Abstract:
A semiconductor circuit configuration, comprising:having a matrix of a plurality of switching elements; a plurality of essentially straight word lines for row by row driving said plurality of switching elements; a plurality of essentially straight bit lines for column by column driving said plurality of switching elements; and a plurality of electrically conductive connection elements located between said plurality of word lines; said plurality of switching elements having control layers essentially forming said plurality of word lines; said semiconductor substrate including a plurality of essentially straight active regions; each one of said plurality of switching elements including a source region and a drain region spaced apart from said source region; said plurality of said active regions having said source region and said drain region of each one of said plurality of switching elements formed therein; each one of said plurality of bit lines having a source line for selectively driving said source region of a respective one of said plurality of switching elements; each one of said plurality of bit lines having a drain line for selectively driving said drain region of a respective one of said plurality of switching elements; said plurality of electrically conductive connection elements for connecting said source region of each one of said plurality of switching elements to said source line of a respective one of said plurality of bit lines; said plurality of electrically conductive connection elements for connecting said drain region of each one of said plurality of switching elements to said drain line of a respective one of said plurality of bit lines; said plurality of electrically conductive connection elements formed by a plurality of connection strips; said semiconductor substrate having a surface and a plurality of trench isolations; each one of said plurality of connection strips including a portion directly making contact with said source region of a respective one of said plurality of switching elements at said surface of said semiconductor substrate or with said drain region of a respective one of said plurality of switching elements at said surface of said semiconductor substrate; and each one of said plurality of connection strips including a remaining portion lying above one of said plurality of trench isolations.