Patent ID: 6566930
Filing Date: 2003-05-20
Classification: H03K

Abstract:
A level shift circuit comprising:an inverter circuit having a first first-conductivity-type MOS transistor and a first second-conductivity-type MOS transistor connected in series to each other between a first power supply and a ground, the inverter circuit providing an inverted signal of an input signal; a second first-conductivity-type MOS transistor to a gate of which the input signal is connected and a source of which is connected to the ground; a third first-conductivity-type MOS transistor to a gate of which an output of the inverter circuit is connected, and a source of which is connected to the ground; a second second-conductivity-type MOS transistor whose gate is connected to a drain of the third first-conductivity-type MOS transistor, and whose source is connected to a second power supply, and whose drain is connected to a drain of the second first-conductivity-type MOS transistor; and a third second-conductivity-type MOS transistor whose gate is connected to the drain of the second first-conductivity-type MOS transistor, and whose source is connected to the second power supply, and whose drain is connected to the drain of the third first-conductivity-type MOS transistor, wherein the first first-conductivity-type MOS transistor and the first second-conductivity-type MOS transistor of the inverter circuit, and the second and third first-conductivity-type MOS transistors are each a MOS transistor whose channel forming semiconductor region is electrically connected to its gate, wherein the second and third first-conductivity-type MOS transistors and the second and third second-conductivity-type MOS transistors each have a gate oxide larger in film thickness than gate oxides of the first first-conductivity-type MOS transistor and the first second-conductivity-type MOS transistor of the inverter circuit.