Patent ID: 6169448
Filing Date: 2001-01-02
Classification: H04L

Abstract:
A digital demodulator comprising: phase difference data output means for comparing a phase-modulated input signal with a clock signal which is not in synchronization with the carrier wave component of the input signal, and outputting phase difference data which corresponds to the phase difference between the input signal and the clock signal; delaying means for delaying the phase difference data outputted from said phase difference data output means by a predetermined period of time; compensation value hold means for holding as a compensation value a fixed value which corresponds to a phase shift caused by the frequency difference between the carrier wave component and the clock signal; differential detection means for performing a differential detection using the phase difference data outputted from said phase difference data output means, the compensation value held by said compensation value hold means, and the phase difference data delayed by said delaying means by the predetermined period of time; and demodulation means for demodulating the input signal based on the result of the differential detection, wherein said differential detection means includes: addition means for adding the phase difference data outputted from said phase difference data output means and the compensation value held by said compensation value hold means; and subtraction means for subtracting the phase difference data delayed by said delaying means by the predetermined period of time from the result of the addition by said addition means.