Patent ID: 8389359
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A method for making metal gate stacks of a semiconductor device comprising: forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and the polysilicon layer to form a first dummy gate in a first field effect transistor (FET) region and a second dummy gate in a second FET region; after patterning the high k dielectric layer and the polysilicon layer, forming an inter-level dielectric (ILD) layer on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate, such that a portion of the ILD layer is removed thereby exposing the first and the second dummy gates; after applying the first CMP process, removing the polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal gate electrode over the high k dielectric layer in the first gate trench; after forming the first metal gate electrode, applying a second CMP process to the semiconductor substrate; after applying the second CMP process, forming a mask covering the first metal gate electrode and exposing the second dummy gate; after forming the mask, removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; forming a second metal gate electrode over the high k dielectric layer in the second gate trench; and after forming the second metal gate electrode, applying a third CMP process to the semiconductor substrate; wherein the step of forming a mask includes forming a titanium nitride (TiN) layer.