Patent ID: 8756550
Filing Date: 2014-06-17
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps: forming a first metal-1 pattern of a metal-1 interconnect layer of a double pattern technology (DPT) process over said integrated circuit, said first metal-1 pattern including first geometries of a first standard cell and first geometries of a second standard cell laterally adjacent to said first standard cell; forming a second metal-1 pattern of said metal-1 interconnect layer of said DPT process over said integrated circuit, said second metal-1 pattern including second geometries of said first standard cell and second geometries of said second standard cell; forming a first metal-2 pattern of a metal-2 interconnect layer over said metal-1 interconnect layer of said DPT process over said integrated circuit, said first metal-2 pattern including first geometries of said first standard cell and first geometries of said second standard cell abutting said first standard cell; and forming a second metal-2 pattern of said metal-2 interconnect layer of said DPT process over said integrated circuit, said second metal-2 pattern including second geometries of said first standard cell and second geometries of said second standard cell; wherein each of said first standard cell and said second standard cell; have cell side boundaries which lie outside an outermost vertical dummy poly lead; have a first metal-1 power rail across a top of said standard cells where said first metal-1 power rail traverses a width of each of said standard cells and touches a top boundary and said cell side boundaries; have a second metal-1 power rail across a bottom of said standard cells where said second metal-1 power rail traverses said width of each of said standard cells and touches a bottom boundary and said cell side boundaries; have DPT compatible metal-1 geometries in an interior of said standard cells where said metal-1 geometries terminate a design rule distance from said outermost vertical dummy poly lead or terminate a design rule distance from said cell side boundary; have a first metal-2 power rail across said top of said standard cells where said first metal-2 power rail traverses said width of each of said standard cells and touches said top boundary and said cell side boundaries; have a second metal-2 power rail across said bottom of said standard cells where said second metal-2 power rail traverses said width of each of said standard cells and touches a bottom boundary and said cell side boundaries; and have DPT compatible metal-2 geometries in said interior of said standard cells where said metal-2 geometries terminate a design rule distance from said outermost vertical dummy poly lead or terminate a design rule distance from said cell side boundaries; and where said cell side boundary of said first standard cell lies between a first outermost vertical dummy poly lead of said first standard cell and a second outermost vertical dummy poly lead of said second standard cell; where said first metal-1 power rail across said top of said first standard cell is continuous with said first metal-1 power rail across said top of said second standard cell; where said first metal-1 power rail across said bottom of said first standard cell is continuous with said first metal-1 power rail across said bottom of said second standard cell; where said first metal-2 power rail across said top of said first standard cell is continuous with said first metal-2 power rail across said top of said second standard cell; and where said first metal-2 power rail across said bottom of said first standard cell is continuous with said first metal-2 power rail across said bottom of said second standard cell.