Patent ID: 6168992
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method for fabricating a DRAM cell capacitor comprising the steps of: forming a gate electrode on a semiconductor substrate; forming a first insulating layer on the semiconductor substrate and on the gate electrode; forming a bit line on the first insulating layer; forming a second insulating layer on the first insulating layer and on the bit line; forming an etch stop layer on the second insulating layer opposite the substrate; forming a sacrificial layer on the etch stop layer opposite the substrate wherein the sacrificial layer can be etched selectively with respect to the etch stop layer; forming a barrier layer on the sacrificial layer opposite the substrate; forming a mask pattern on the barrier layer to define a storage electrode contact hole; sequentially etching the barrier layer, the sacrificial layer, the etch stop layer, the second insulating layer, and the first insulating layer using the mask pattern as a contact hole forming mask to form a contact hole for a storage electrode; removing the mask pattern; forming a conductive layer in the contact hole and on the barrier layer; planarization-etching the barrier layer and the conductive layer to expose a surface portion of the sacrificial layer; and removing the sacrificial layer using the etch stop layer to stop the etch thereby forming a storage electrode electrically coupled with the semiconductor substrate.