Patent ID: 6925634
Filing Date: 2005-08-02
Classification: G06F

Abstract:
1. A method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory the method comprising the steps of: creating a software memory map of the memory usage of a plurality of processors in the system to be debugged denoting in the software memory map whether or not each processor of the plurality of processors has a cache; activating a first debug session associated with a first processor of the plurality of processors and at least a second debug session associated with a second processor of the plurality of processors; detecting a write request to a shared memory location by the first debug session; passing the write request initiated by the first debug session to the first processor for execution; searching the software memory map for a first plurality of processors that have read access to the shared memory location; broadcasting the write request to the first plurality of processors; and performing cache coherency updates in response to the write request in each of the first plurality of processors.