Patent ID: 6064225
Filing Date: 2000-05-16
Classification: H03K

Abstract:
An integrated circuit having a field programmable gate array (FPGA) comprising:(a) an array of programmable logic cells (PLCs), each of which comprises a programmable function unit (PFU);(b) a ring of programmable input/output cells (PICs) surrounding the array of PLCs;(c) one or more wires used as spines running in a first direction on the FPGA; and(d) two or more wires used as branches running in a second direction, orthogonal to the first direction, on the FPGA, wherein:each spine runs across all PLCs in its row/column;each branch runs across all PLCs in its row/column;each spine is configured to programmably directly drive two or more branches, wherein no two branches that are directly driven by any one spine are in adjacent rows/columns; andeach branch is configured to programmably directly drive two or more PFUs in at least two rows/columns parallel to the branches.