Patent ID: 7747904
Filing Date: 2010-06-29
Classification: H04L

Abstract:
1. A packet switch integrated circuit, comprising: an error management module; and at least one component configured to facilitate routing of data packets through the packet switch and to generate a first plurality of error codes, each error code of the plurality of error codes identifying an error occurring in the packet switch, the at least one component further configured to provide the first plurality of error codes to the error management module, the error management module configured to select at least one error code in the first plurality of error codes and to generate an error log in the packet switch comprising the at least one selected error code, wherein a first component of the at least one component is configured to generate a first error code of the at least one selected error code, the error management module is further configured to generate an acknowledgment based on the first error code, the first component is further configured to receive the acknowledgement, and the first component is inhibited from providing the first error code to the error management module more than once before the first component receives the acknowledgement.