Patent ID: 7334172
Filing Date: 2008-02-19
Classification: G01R

Abstract:
1. An apparatus comprising: a register for an integrated circuit for shifting a scan test pattern in response to a scan enable signal, the register comprising: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving clock pulses; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to a clock pulse; and a scan enable gating circuit coupled to the scan enable input comprising first means for gating the scan enable signal to the scan enable input immediately following a transition of the scan enable signal from the normal mode to the shift mode and second means for gating the scan enable signal to the scan enable input immediately following a second one of the clock pulses immediately following a transition of the scan enable signal from the shift mode to the normal mode.