Patent ID: 6246621
Filing Date: 2001-06-12
Classification: G11C

Abstract:
A semiconductor memory device having transistors with respective control terminals, the transistors being of a first type and a second type, each transistor of the first type being switched on when its control terminal is at a first potential and off when its control terminal is at a second potential, each transistor of the second type being switched on when its control terminal is at the first potential and also when its control terminal is at the second potential, the transistors of the first type having a higher on-resistance than the transistors of the second type, comprising:a plurality of word lines drivable to said first potential and said second potential;at least one column of memory cells, each memory cell among said memory cells having a transistor of a type selected from among said first type and said second type, the control terminal of the transistor in the memory cell being coupled to one of said word lines, the transistors in said column of memory cells being mutually coupled in series and conducting a cell current when all switched on;a reference amplifier receiving a reference current and converting the reference current to a reference voltage;a data sensing amplifier coupled to said column of memory cells and said reference amplifier, using said reference voltage to convert said cell current to a data voltage signal; anda reference column having two parallel current paths joining at a common node from which said reference current is supplied to said reference amplifier, each of said two parallel current paths having a number of transistors of said first type coupled in series with a substantially equal number of transistors of said second type, each word line among said word lines being coupled to the control terminals of one transistor of said first type on one of said two parallel current paths and one transistor of the second type on another one of said two parallel current paths.