Patent ID: 9183143
Filing Date: 2015-11-10
Classification: G06F,H01L

Abstract:
1. A memory device comprising: a memory to which data is written using memory cells as a write unit; and a controller which, in response to a request to write data with a logical address to the memory from a host device, requests the host device to transmit a segment of the write data with a size of the segment of the write data specified by the controller, wherein when the controller receives the segment of the write data, the controller each of the sections of the segment of the write data has a same fixed size, each of the additional data pieces has a same fixed size, and the segment of the write data has a first size determined to allow a combined size of the segment of the write data and the additional data pieces for the sections of the segment of the write data to be largest among sizes that are smaller than the size of the write unit or the segment of the write data has a size of a multiple integral of the first size.