Patent ID: 6477107
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A semiconductor memory device operating in synchronicity with an external system clock, comprising:a first memory array for storing a plurality of data and outputting data addressed by a row address and a first column address to a first data line; a second memory array for storing a plurality of data and outputting data addressed by the row address and a second column address to a second data line; an internal clock generator for generating a first clock having a period which is an integer multiple of the period of the external system clock and a second clock having a longer period than the first clock, and for outputting either the first or the second clock as an internal clock in response to a control signal; and an amplifying and multiplexing circuit, operating in synchronicity with the internal clock, for receiving data output by the first and second memory arrays and amplifying and multiplexing the received data to output the multiplexed data.