Patent ID: 7582925
Filing Date: 2009-09-01
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a substrate; a plurality of storage electrode landing pads on the substrate, wherein each of the plurality of storage electrode landing pads have major axis and minor axis; a plurality of storage electrodes with each of the plurality of storage electrodes being on a respective first portion of a respective one of the plurality of storage electrode landing pads wherein second portions of the storage electrode landing pads are free of the storage electrodes; an insulating support layer on the substrate, on the second portions of the storage electrode landing pads that are free of the storage electrodes, and on first portions of sidewalls of the storage electrodes, wherein second portions of the sidewalls of the storage electrodes are free of the insulating support layer, wherein the first portions of the sidewalls of the storage electrodes are free of the storage electrode landing pads; and first and second adjacent bit lines on the substrate wherein the first and second adjacent bit lines are parallel; wherein the plurality of storage electrode landing pads include first and second adjacent storage electrode landing pads between the first and second adjacent bit lines, wherein a first one of the plurality of storage electrodes is on an end of the first storage electrode landing pad adjacent the first bit line, and wherein a second one of the plurality of storage electrodes is on an end of the second storage electrode landing pad adjacent the second bit line, wherein the first and second bit lines extend in a direction of the minor axis of the storage electrode landing pads.