Patent ID: 7273796
Filing Date: 2007-09-25
Classification: H01L

Abstract:
1. A method of forming trench isolation in the fabrication of integrated circuitry, comprising: forming first and second isolation trenches into semiconductive material of a semiconductor substrate, the first isolation trench having a narrowest outermost cross sectional dimension which is less than that of the second isolation trench; depositing a spin-on-dielectric to within the first and second isolation trenches, the spin-on-dielectric comprising a polysilazane; etching the polysilazane effective to recess the spin-on-dielectric in the first and second isolation trenches relative to an outermost surface of the semiconductive material adjacent the first and second isolation trenches, the polysilazane not being polished prior to said etching and the polysilazane being entirely outwardly exposed within the first and second trenches during at least some of said etching; and after the etching, annealing remaining spin-on-dielectric comprising polysilazane within the first and second isolation trenches effective to form a trench isolation dielectric within the first and second isolation trenches which is different in composition from the spin-on-dielectric.