Patent ID: 8624297
Filing Date: 2014-01-07
Classification: H01L,H05K

Abstract:
1. A computer-performed method of designing layers of a substrate for mounting and interconnecting a semiconductor die, the method comprising: within a computer executing a program modeling a design of the substrate stored in a memory of the computer, identifying locations of signal bearing vias from among a pattern of large-diameter conductive vias extending from a top side to a bottom side of a core comprising a dielectric layer; and within the computer executing the program modeling the design of the substrate, generating a first mask design for a transmission line reference plane metal layer including regions substantially devoid of metal around the profile of the signal-bearing vias so that capacitive coupling between the ends of the signal-bearing vias and the transmission line reference plane metal layer is substantially reduced, whereby the design of the substrate stored in the memory is modified, and wherein the transmission line reference plane metal layer does not provide power distribution within the substrate.