Patent ID: 6740923
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A capacitor structure comprising:two gate stacks situated upon a semiconductor substrate; a dielectric material upon the semiconductor substrate, the dielectric layer having a concave recess formed therein defined by an interior surface; a storage node layer; a cell dielectric layer situated on the storage node layer; a cell plate layer situated on the cell dielectric layer, wherein each of the storage node layer, cell dielectric layer, and cell plate layer are situated above the two gate stacks, and the storage node layer has portions thereof that contact the two gate stacks; and a concave shaped storage container cell region having an opening thereto and being defined by the storage node layer, the storage node layer being in contact with the interior surface of the concave recess, wherein: the opening to the storage container cell region has a width; and the storage container cell region has a maximum width that is greater than the width of the opening to the storage container cell region; and a contact plug situated between and in contact with the two gate stacks and extending at least partially above both the gate stacks and the semiconductor substrate, wherein the contact plug has a top surface in contact with the storage node layer and a top surface of the contact plug has a recessed area that contacts a conformal portion of the storage node layer such that the storage layer and the cell plate layer each obtain a greater surface area; wherein the cell dielectric layer makes a conforming contact with the storage node layer, and the cell plate layer makes a conforming contact with the cell dielectric layer.