Patent ID: 6075748
Filing Date: 2000-06-13
Classification: G11C

Abstract:
A latch comprising:(a) a pair of PMOS FETs having their source-drain circuits connected in series between a voltage source VDD and serially connected source-drain circuits of a pair of NMOS FETs which are connected between the PMOS FETs and ground,(b) a gate of a first of the PMOS FETs, which is connected to the voltage source VDD, being coupled to ground,(c) a gate of a first of the NMOS FETs, which is connected to ground, being coupled to the voltage source VDD,(d) an input to the latch being coupled to a junction of the other PMOS FET and the other NMOS FET, and to an input of an inverter,(e) an output of the inverter being coupled to gates of said other PMOS FET and of said other NMOS FET, the output of the inverter providing an output to the latch, and(f) gate lengths of the first PMOS FET and the first NMOS FET being substantially larger than gate lengths of said other PMOS and NMOS FETS.