Patent ID: 7702888
Filing Date: 2010-04-20
Classification: G06F

Abstract:
1. An apparatus, comprising: an instruction cache; a fetch unit coupled to the instruction cache and configured to perform fetch operations; a branch prediction unit coupled to the fetch unit and configured to provide, to the fetch unit, an address of a predicted first instruction, an address of a predicted next instruction, and way prediction information for the predicted next instruction, wherein the way prediction information includes a prediction of a particular way within the instruction cache that stores the predicted next instruction; wherein the fetch unit is configured to send a fetch request for the predicted first instruction to the instruction cache to perform a fetch operation; wherein, in response to detecting a cache miss corresponding to the predicted first instruction, the fetch unit is configured to perform one or more prefetch operations while the cache miss corresponding to the predicted first instruction is being serviced; wherein to perform the one or more prefetch operations, the fetch unit is configured to send a prefetch request for the predicted next instruction to the instruction cache, wherein the prefetch request includes the way prediction information; and wherein, during subsequent fetch operations, the fetch unit is configured to use way misprediction information resulting from a miss in the instruction cache corresponding to the prefetch request.