Patent ID: 9147764
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a MOS transistor with a first polysilicon gate formed in a substrate of said integrated circuit; an extended drain diffusion formed in said substrate; an LDMOS transistor having a same polarity as said MOS transistor with a second polysilicon gate formed in said substrate where said extended drain diffusion is a drain of said LDMOS and where a portion of said second polysilicon gate overlying a channel and adjacent to a source of said LDMOS transistor is doped with at least one dopant selected from the group indium, carbon, nitrogen, and halogen that raises a threshold voltage of said LDMOS transistor; and wherein said first polysilicon qate is also doped with said at least one dopant and where said at least one dopant raises a threshold voltage of said MOS transistor.