Patent ID: 6344996
Filing Date: 2002-02-05
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell unit having a plurality of memory cells connected in series; a first select transistor connected to said memory unit at a first end; a second select transistor connected to said memory unit at a second end; and a programming circuit for programming into a selected memory cell among said plurality of memory cells, wherein said programming circuit applies, at a time of programming, a first voltage to a gate electrode of said selected memory cell, applies a second voltage to a gate electrode of a second memory cell positioned between the selected memory cell and the second end and adjacent to said selected memory cell, the second voltage being lower than the first voltage, and applies a third voltage to a gate electrode of at least a third memory cell positioned between the memory cell, to which the second voltage is applied, and the second end, the third voltage being lower than the first voltage but higher than said second voltage.