Patent ID: 8779546
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A method of manufacture of a semiconductor memory system comprising: forming isolation regions having contact holes on a base wafer including forming an ion implanted region in the contact holes; depositing a bit line contact plug in one of the contact holes; removing a portion of the isolation regions from between the bit line contact plug and another of the bit line contact plug including forming isolation sidewalls of the isolation regions in direct contact with sides of the bit line contact plug; forming a resistor or capacitor on the isolation sidewalls opposite to the bit line contact plug between the bit line contact plug and another of the bit line contact plug; and forming a bit line on the bit line contact plug and the another of the bit line contact plug and over the resistor or capacitor; wherein forming the resistor or capacitor includes: depositing a resistive or capacitive film on the isolation sidewalls between the bit line contact plug and the another of the bit line contact plug; depositing a metal film on the resistive or capacitive film; and planarizing a top surface of the isolation region, the bit line contact plug, the resistive or capacitive film, and the metal film.