Patent ID: 6236595
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A method of operating a memory including first and second groups of memory cells, cells of the first group formed in a first semiconductor region and operatively coupled to a word line and respective bit lines, cells of the second group formed in a second semiconductor region and are operatively coupled to the word line and respective bit lines, the method comprising:applying a first voltage to the word line;applying a second voltage to the first semiconductor region;applying selected voltages to the bit lines of the first group of cells;applying a fourth voltage to the second semiconductor region;applying a fifth voltage to the bit lines of the second group of cells;wherein during a first time the first and fourth voltages are substantially the same, and the second and the selected voltages are substantially the same, and the fifth voltage is selected from the range of the first voltage to the second voltage, andwherein during a second time the second and fourth voltages are substantially the same and different from the first voltage, the fifth voltage is selected from the range of the first voltage to the second voltage, and the selected voltages being selected from the fifth and second voltages.