Patent ID: 9223711
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A processor storing instructions for executing a process, the instructions comprising: managing a cache coherency maintenance data structure based on a hash table comprising a plurality of cuckoo ways; wherein each of the plurality of cuckoo ways is associated with at least one multi-set associative table; wherein each of the plurality of cuckoo ways is associated with a hash function, and wherein the managing the cache coherency maintenance data structure further comprises processing an address with the hash function of each of the plurality of cuckoo ways to generate an index for each of the plurality of cuckoo ways, the index for each of the plurality of cuckoo ways being indicative of a value corresponding to the address and the set for the address in the associated at least one multi-way set associative table of each of the plurality of cuckoo ways.