Patent ID: 6144979
Filing Date: 2000-11-07
Classification: G06F

Abstract:
A method for multiplying floating point data in two pipelincd cycles, comprising the steps of:(a) receiving multiplier data and multiplicand data from pipelined inputs in a first cycle of multiply operation;(b) generating a partial product by means of said multiplier data and multiplicand data, and generating a first sum and a first carry by adding said partial product through adding tree means; and(c) generating an output of said multiply operation by adding a second sum and a second carry to said first sum and said first carry, wherein said second sum and said second carry are generated by feedbacking said first sum and the first carry in a second cycle of said multiply operation which succeeds said first cycle;wherein said step (c) comprises the step of:in said first cycle, generating a carry needed in said second cycle by adding a lower bits portion of said first sum and a lower bits portion of said first carry, wherein the number of bits of said lower bits portion of said first sum is equal to the number of bits of said first sum minus the number of bits of said multiplicand data, and the number of bits of said lower bits portion of said first carry is equal to the number of bits of said first carry minus the number of bits of said multiplicand data.