Patent ID: 6933558
Filing Date: 2005-08-23
Classification: H01L

Abstract:
1. A memory device, comprising: a first conductive layer, wherein a portion of the first conductive layer acts as a source region for the memory device; a conductive structure having a cylindrical shape formed on the first conductive layer, the conductive structure having a first end and a second end opposite the first end, wherein the first end is disposed adjacent the portion of the first conductive layer that acts as the source region for the memory device and wherein the second end acts as a drain region for the memory device; a plurality of dielectric layers formed around at least a portion of the conductive structure, wherein at least one of the dielectric layers acts as a floating gate electrode for the memory device; and a control gate formed over the plurality of dielectric layers, and wherein a top portion of the second end of the conductive structure does not contact any of the plurality of dielectric layers.