Patent ID: 7148135
Filing Date: 2006-12-12
Classification: G06F

Abstract:
1. A design method for changing layout results of a semiconductor integrated circuit, the method comprising the steps of: detecting a branching point of a wire in the layout results including information regarding types of cells, information regarding arrangement of the cells, and information regarding wiring among the cells; virtually inserting a load having a predetermined amount at a predetermined point on one of wires subsequent to the detected branching point; calculating a delay amount of each route connecting cells via the branching point with the load being inserted and a delay amount thereof without the load being inserted; determining, based on the delay amounts of each route, an insertion point at which a load-dividing buffer is to be inserted; calculating a drive capability of a driving cell preceding the insertion point, on condition that the load-dividing buffer is to be inserted at the determined insertion point and based on timing-constraints of each route; deciding, based on the layout results, whether the load-dividing buffer is insertable at the insertion point; and performing a process of changing the layout results based on the decision results, the process including a process of placing the load-dividing buffer at the insertion point, a process of changing the driving cell to a cell having the calculated drive capability, and a process of changing wiring information in accordance with circuit changes.