Patent ID: 6747910
Filing Date: 2004-06-08
Classification: G11C

Abstract:
A thin film magnetic memory device, comprising:a plurality of magnetic memory cells arranged in a matrix, wherein said plurality of magnetic memory cells being divided into N memory blocks of first to Nth stages along a row direction so that said N memory blocks share memory cell rows (where N is a natural number), said thin film magnetic memory device further comprising in each of said memory blocks: a plurality of digit lines provided corresponding to the memory cell rows, respectively, for selectively supplying a data write current for generating a data write magnetic field to the magnetic memory cell selected for data write operation; a plurality of first driver units provided corresponding to said plurality of digit lines, respectively, and each controlling connection between one end of the corresponding digit line and a first voltage; and a plurality of second driver units provided corresponding to said plurality of digit lines, respectively, and each controlling connection between another end of said corresponding digit line and a second voltage, wherein in said data write operation, each of said first driver units corresponding to the memory block of the first stage connects said one end of the corresponding digit line to said first voltage according to a row selection result, in said data write operation, each of said second driver units corresponding to the memory block of the Ith stage including the selected magnetic memory cell (where I is a natural number satisfying I&lE;N) connects said another end of the corresponding digit line to said second voltage according to a selection result of said N memory blocks, when I&gE;2 in said data write operation, each of said first driver units corresponding to each of the memory blocks of the second to Ith stages connects said one end of the corresponding digit line to said first voltage according to a voltage level on the digit line of the same memory cell row in the memory block of a previous stage, and when I&gE;2 in said data write operation, each of said second driver units corresponding to each of the memory blocks of the first to (Iâˆ’1)th stages disconnects said another end of the corresponding digit line from said second voltage according to said selection result of said N memory blocks.