Patent ID: 6124187
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A method of fabricating a semiconductor device having an N.sup.+ -type source/drain layer or P.sup.+ -type source/drain layer containing an impurity in a concentration of 1.times.10.sup.19 /cm.sup.3 or more, comprising the steps of:forming an N.sup.+ -type source/drain layer or P.sup.+ -type source/drain layer containing an impurity in a concentration of 1.times.10.sup.19 /cm.sup.3 or more; andsubjecting said N.sup.+ -type source/drain layer or P.sup.+ -type source/drain layer to heat treatments, each of said heat treatments exerting an effect to an active state of said impurity;wherein said heat treatments each exerting an effect on the active state of said impurity, include a first rapid thermal anneal performed after formation of said N.sup.+ -type layer or P.sup.+ -type layer, a high temperature/long-time anneal performed at a temperature of from 600 to 950.degree. C. for a time of at least 10 minutes after said first rapid thermal anneal, and a final rapid thermal anneal.