Patent ID: 6133628
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate;a first dielectric layer formed on the substrate;a first patterned metal layer on the first dielectric layer;a second dielectric layer on the first patterned metal layer;a second patterned metal layer on the second dielectric layer;a third dielectric layer on the second patterned metal layer;a third patterned metal layer on the third dielectric layer; anda conductive via providing a direct electrical connection between the first and third patterned metal layers without a landing pad on the second patterned metal layer, wherein the conductive via comprises:a through-hole formed in both the second and third dielectric layers exposing the first patterned metal layer without exposing any metal of the second patterned metal layer; anda conductive plug filling the through-hole and forming a direct electrical connection between the first and third patterned metal layers; andthe combined thickness of the second and third dielectric layers at the through-hole is from about 2.8 to about 3.5 microns.