Patent ID: 6282117
Filing Date: 2001-08-28
Classification: G11C

Abstract:
A multi-level flash memory device comprising:a plurality of flash memory cells each being able to store four level data of ""0"", ""1"", ""2"" and ""3"";a plurality of data storage circuits, each being associated to corresponding one of said memory cells, for storing write data of ""0"", ""1"", ""2"" and ""3"" to be written into said memory cells; anda write controller for carrying out first write sequence in which ""1""-data are simultaneously written into the memory cells corresponding to the data storage circuits storing ""1""-write data, for carrying out second write sequence in which ""2""-data and ""3""-data are simultaneously written into the memory cells corresponding to the data storage circuits storing ""2""-write data or ""3""-write data, respectively;wherein, in said first write sequence, first write voltage promoting ""1""-write is applied to the memory cells to be written, and it is determined that ""1""-data has been written successfully,wherein, in said second write sequence, second write voltage promoting ""2""-write or ""3""-write is applied to the memory cells to be written, and it is determined that ""2""-data has been written successfully in the memory cells corresponding to the data storage circuits storing ""2""-write data and that ""3""-data has been written successfully in the memory cells corresponding to the data storage circuits storing ""3""-write data.