Patent ID: 6496878
Filing Date: 2002-12-17
Classification: G06F

Abstract:
A data communication system for fast processing of a data transfer load, divided individual data blocks, said processing optimizing the overlap of pipelined operations including data transfers and post-processing performed on individual data blocks, said system comprising:at least one peripheral interface adapter having: an internal bus connected to a peripheral interface, a DMA channel connected to the internal bus assisting in the DMA transfer of individual data blocks, and a Transfer Progress Alert (TPA) module connected to the internal bus; and a bridge placed between the internal bus and at least one external bus, each said external bus connected to a data storage device, a main memory, and a main processor, wherein said bridge connecting a processor, a post-processing module and a memory; said internal bus transferring individual data blocks between the peripheral interface and the memory; said TPA module determining when each said transferred individual data block being transferred on the internal bus and ready for a post-processing operation in the post-processing module; and the pipelined operations occurring on different individual data blocks simultaneously, and including transferring incoming individual data blocks, at least one post-processing operation, and transferring the processed data, until all individual data blocks from the data transfer load are processed.