Patent ID: 7372083
Filing Date: 2008-05-13
Classification: H01L

Abstract:
1. A device comprising: a substrate doped with a first conductivity type impurity; a buried layer, doped with an impurity of a second conductivity type opposite the first conductivity type, in the substrate; a first high-voltage well region, doped with an impurity of the first conductivity type, overlying the buried layer; a second high-voltage well region, doped with an impurity of the second conductivity type, overlying the buried layer and in contact with the first high-voltage well region; a field region substantially in the first high-voltage well region and substantially close to an interface between the first high-voltage well region and the second high-voltage well region; a first and a second doped region doped with an impurity of the first conductivity type, wherein the first doped region is in the first high-voltage well region and physically in contact with the field region, and the second doped region is in the second high-voltage well region; a third doped region of the second conductivity type in the first high-voltage well region and in contact with the first doped region; a fourth doped region of the second conductivity type in the second high-voltage well region and in contact with the second doped region; a gate dielectric on the field region and the first and second high-voltage well regions, the gate dielectric having a first side edge substantially aligned with an edge of the second doped region, and a second side edge over the field region; and a gate electrode on the gate dielectric.