Patent ID: 9007248
Filing Date: 2015-04-14
Classification: H03M

Abstract:
1. A MASH sigma-delta modulator comprising: an integration part having parallel integration units in M (M; an integer not less than 1) stages configured to receive N (N; an integer not less than 2) pieces of data from a previous stage, to perform integral calculation in parallel, and to output a result to a subsequent stage; a differentiation part having parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part and also to receive the difference, to perform differential calculation in parallel, and to output a result to a subsequent stage; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units in the initial stage of the integration part receive pieces of input data in parallel, the parallel integration unit in each stage of the integration part and the parallel differentiation unit in each stage of the differentiation part perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.