Patent ID: 9047426
Filing Date: 2015-06-02
Classification: G06F

Abstract:
1. A method for optimizing a circuit design over a set of scenarios, the method comprising: determining a first subset of scenarios such that, if the circuit design meets a first set of design constraints in each scenario in the first subset of scenarios, the circuit design is expected to meet the first set of design constraints in each scenario in the set of scenarios, wherein the first set of design constraints does not include minimum-delay timing-constraints; determining a second subset of scenarios such that if the circuit design meets a second set of design constraints in each scenario in the second subset of scenarios, the circuit design is expected to meet the second set of design constraints in each scenario in the set of scenarios, wherein the second set of design constraints includes minimum-delay timing-constraints; optimizing the circuit design using the first set of design constraints over the first subset of scenarios to obtain a first optimized circuit design; and optimizing, by computer, the first optimized circuit design using the first set of design constraints and the second set of design constraints, wherein said optimizing the first optimized circuit design is performed over at least the second subset of scenarios to obtain a second optimized circuit design.