Patent ID: 7009300
Filing Date: 2006-03-07
Classification: H01L

Abstract:
1. An integrated circuit package, comprising: a first chip having a first side and a second side, the first and second sides having a first plurality of conductive pads formed thereon, at least one conductive pad on the first side being electrically connected to a conductive pad on the second side, the first side containing active circuitry of the first chip; a first layer formed directly on the second side and having a first cutout, wherein the first layer comprises a polymer material; a second chip disposed in the first cutout; a dielectric second layer formed directly on the first layer and the second chip and having a second cutout; a third chip disposed in the second cutout; a third dielectric layer formed directly on the second layer and the third chip; and an interconnect formed in the one or more of the first, second or third layers to electrically connect at least one conductive pad of the first plurality of conductive pads to one or more of the second and third chips.