Patent ID: 6452235
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A floating body ESD protection circuit, coupled between an I/O pad and an internal circuit, comprising:a p-type depletion mode transistor, having a gate coupled to the I/O pad, a source coupled to a grounded voltage, and a drain; an n-type depletion mode transistor, having a gate coupled to the I/O pad, a source coupled to a high voltage, and a drain; a p-type enhancement mode transistor, having a source and a gate both coupled to the high voltage, a drain coupled to the I/O pad and a substrate coupled to the drain of the n-type depletion mode transistor; and an n-type enhancement mode transistor, having a source and a gate both coupled to the grounded voltage, a drain coupled to the I/O pad, and a substrate coupled to the drain of the p-type depletion mode transistor.