Patent ID: 6781365
Filing Date: 2004-08-24
Classification: G01R,H01L

Abstract:
A test pad fabricated in a semiconductor memory, the test pad comprising:a substrate; a metal layer; a first dielectric layer above the metal layer; a plug in the first dielectric layer, the plug in communication with the metal layer; an aluminum layer in communication with the plug wherein the aluminum layer is above the plug; a TiBxNy layer in communication with the aluminum layer wherein the TiBxNy layer is above the aluminum layer, the TiBxNy having the x-factor between about 0.5 and 2 and the y-factor between about 0.2 and 2; and a second dielectric layer above the TiBxNy layer wherein the second dielectric layer is etched to expose the TiBxNy layer, wherein the exposed TiBxNy layer forms the surface of a test pad associated with a semiconductor memory.