Patent ID: 6448125
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A process for the manufacturing of an electronic power device integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer has grown, of the first conductivity type, said power device including a power stage PT and a control stage CT, the latter enclosed in an isolation region having a second conductivity type, said portion of power PT including a first buried area, having the second conductivity type, and a second buried area, partially overlapping the first buried area and having the first conductivity type, said isolation region and said control stage CT comprising respectively a third buried area, having the second conductivity type, and a fourth buried area, partially overlapping the third buried area and having the first conductivity type, the method comprising:depositing a first thick photoresist film on a portion the epitaxial layer and leaving portions of the epitaxial layer unprotected by the first thick photoresist film; implanting at high energy first dopant ions having the second conductivity type in the portions of epitaxial layer not protected by the first thick photoresist film, for forming the first and third buried areas; removing the first thick photoresist film and depositing on a portion of the epitaxial layer a second thick photoresist film and leaving portions of the epitaxial layer unprotected by the second thick photoresist film; implanting at high energy second dopant ions having the first conductivity type in the portions of epitaxial layer not protected by the second thick photoresist film, for forming the second and fourth buried areas, wherein each of the buried areas is buried within the epitaxial layer such that each buried layer is completely covered by the epitaxial layer; removing the second thick photoresist film; and totally forming the power stage PT and the control stage CT in the epitaxial layer.