Patent ID: 6341081
Filing Date: 2002-01-22
Classification: G11C

Abstract:
A nonvolatile ferroelectric memory comprising: p1 a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at a corresponding crossing point of the bitlines with the wordlines and the platelines;a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on a corresponding crossing point of the first and second reference bitlines with the wordlines and the platelines; a first lower sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; a first upper sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline; a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first lower sense amplifier block; a second switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first lower sense amplifier block; a third switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first upper sense amplifier block; a fourth switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first upper sense amplifier block; and first and second pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.