Patent ID: 7626235
Filing Date: 2009-12-01
Classification: H01L

Abstract:
1. A NAND nonvolatile semiconductor memory device that has a memory cell array region and a selection gate region, comprising: a semiconductor layer; a gate insulating film disposed on said semiconductor layer; a plurality of first electrode layers selectively disposed on said gate insulating film; a first device isolation insulating film formed in said memory cell array region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; a second device isolation insulating film formed in said selection gate region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; an interpoly insulating film formed at least on the top of said first electrode layers and said first device isolation insulating film in said memory cell array region; a second electrode layer disposed on said interpoly insulating film; and a third electrode layer disposed on said second electrode layer, said second device isolation insulating film and the first electrode layers in said selection gate region, wherein the height of the top surface of said second device isolation insulating film is greater than the height of the top surface of said first device isolation insulating film.