Patent ID: 8343836
Filing Date: 2013-01-01
Classification: H01L

Abstract:
1. A method of forming a recessed gate FET comprising the steps of: providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface; forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate; lining sidewalls and bottom portions of said trench with dielectric material layer; filling said trench with a material to form a gate conductor; recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench; optionally forming doped pocket regions at either side of and abutting said gate electrode, each doped pocket region extending into said channel region; providing a dielectric cap in said formed opening; and forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective formed doped pocket regions, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects.