Patent ID: 9020024
Filing Date: 2015-04-28
Classification: H04L

Abstract:
1. A rate-adaptive equalizer comprising: equalizer circuitry having a plurality of clocked delay elements, the clocked delay elements having tap coefficients that can be varied to vary a delay provided by the clocked delay elements, the tap coefficients being applied to taps of the clocked delay elements, the equalizer circuitry receiving an input signal and outputting at least a first equalizer output signal; clock-and-data recovery (CDR) circuitry, the CDR circuitry electrically coupled to the equalizer circuitry, the CDR circuitry receiving the equalizer output signal and recovering a clock signal from the received equalizer output signal, the CDR circuitry outputting the clock signal and a frequency lock signal, F_LOCK, the clock signal being delivered to the clocked delay elements; and adaptive control logic configured to provide at least one control signal to the equalizer circuitry to select values of the tap coefficients being applied to the taps of the equalizer circuitry, wherein the adaptive control logic is configured to perform an initialization algorithm that generates different combinations of tap coefficients and causes the combinations of tap coefficients to be applied to the clocked delay elements while evaluating information relating to an eye associated with the input signal to determine which combination of tap coefficients results in a highest quality eye, and wherein the adaptive control logic designates the combination of tap coefficients resulting in the highest quality eye as initial coefficients to be applied to the taps of the equalizer circuitry.