Patent ID: 6226322
Filing Date: 2001-05-01
Classification: H04B,H04L

Abstract:
A receive equalizer circuit, comprising:a first stage, comprising:a first operational amplifier, having an input and an output;a first input impedance network, coupled between an input of the receive equalizer circuit and the input of the first operational amplifier, having an impedance selected from one of a first plurality of input impedance values to define a first dominant zero in a frequency characteristic of the receive equalizer circuit, and comprised of a capacitor and a variable resistance connected in parallel with the capacitor; anda first feedback impedance network, coupled between the output and the input of the first operational amplifier, and having an impedance selected from one of a first plurality of feedback impedance values and that is comprised of a capacitor and a variable resistance connected in parallel with the capacitor; anda second stage, comprising:a second operational amplifier, having an input, and an output;a second input impedance network, coupled between the output of the first operational amplifier and the input of the second operational amplifier, to define a second dominant zero in the frequency characteristic of the receive equalizer circuit; anda second feedback impedance network, coupled between the output and the input of the second operational amplifier;wherein each of the variable resistances comprise a plurality of resistors connected in parallel with one another, each of the plurality of resistors capable of being selectably enabled and disabled.