Patent ID: 8959467
Filing Date: 2015-02-17
Classification: G06F

Abstract:
1. A structural analysis tool for analyzing a structural framework of a circuit design during a design process implemented as a series of operating instructions stored on a non-transitory computer readable medium that direct the operation of a processor when initiated, said tool comprising: a structural analyzer configured to apply at least two structural rules to said circuit design in a synthesis or a pre-layout static timing analysis environment of said design process having valid timing data, wherein non-timing critical logic automatically receive lower priority, said structural rules including at least two of registered input/output analysis, fanin and fanout logic cone analysis, Vt (threshold voltage) spread analysis, and logic level depth analysis; and a structural assessor configured to generate structural data of said circuit design based on application of said structural rule by said structural analyzer; wherein said structural analysis tool is implemented as a set of tool command language (TCL) scripts of a synthesis or static timing analysis EDA (electronic design automation) tool; and wherein and said structural data identifies at least one of a percentage of standard Vt cells, a percentage of low Vt cells, a percentage of high Vt cells, a percentage of performance library cells, and a percentage of density library cells in said circuit design.