Patent ID: 7459366
Filing Date: 2008-12-02
Classification: H01L,Y10S

Abstract:
1. A method of fabricating high-voltage transistor comprising: forming an epitaxial layer on a semiconductor substrate, the epitaxial layer and the semiconductor substrate being of a first conductivity type, the epitaxial layer being formed with first and second sections having respective first and second doping concentration gradients that differ by at least 10%, the first and second sections being formed below an upper surface of the epitaxial layer, the first section being formed above the second section, doping concentration in each of the first and second sections increasing with distance from the upper surface; forming first and second trenches in the epitaxial layer that extend vertically from the upper surface to define a mesa, the first and second sections comprising a drift region of the mesa; forming first and second field plate members in the first and second trenches, respectively, the first and second field plate members being formed of a conductive material fully insulated from the mesa by a dielectric material; forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from the first section of the drift region; forming a gate embedded within the dielectric material adjacent the body region.