Patent ID: 6282456
Filing Date: 2001-08-28
Classification: H03K

Abstract:
A digital audio processor comprising:a first logic unit reversing an enable signal;a second logic unit reversing a data signal;a third logic unit receiving output signals from the first logic unit and second logic unit and outputting a logical NOR result;a fourth logic unit receiving an output signal from the second logic unit and the enable signal, and outputting a logical NAND result;a 5V tolerant circuit receiving an output signal from the third logic unit and outputting signals depending upon an input voltage of a pad, the 5V tolerant circuit consisting of three PMOS transistors and two NMOS transistors, wherein a PMOS transistor, which has a gate that receives the logical NOR result from the third logic unit, has a drain which is directly connected to a source of a PMOS transistor, which has a gate that receives a supply voltage;a fifth logic unit reversing an output from the fourth logic unit;a first PMOS transistor coupled to the supply voltage and receiving an output signal from the 5V tolerant circuit, wherein the first PMOS transistor having a gate receiving the signals from the 5V tolerant circuit and a substrate connected to a bulk, so that when the first PMOS transistor is turned off, there is no current between the substrate and the pad; anda first NMOS transistor connected serially to the first PMOS transistor and a ground voltage.