Patent ID: 6379978
Filing Date: 2002-04-30
Classification: B82Y,G11C,H01L

Abstract:
A method for fabricating a memory cell configuration, which comprises the steps of:producing trenches running essentially parallel to one another in a substrate and as a result of which strip-type semiconductor structures are produced; producing first source/drain regions of vertical transistors in the strip-type semiconductor structures; producing channel regions of the vertical transistors under the first source/drain regions in the strip-type semiconductor structures; producing channel stop regions at least on parts of side walls of the strip-type semiconductor structures by inclined implantation; producing gate lines for driving the transistors in the trenches; forming memory elements each connected to one of the transistors and together defining memory cells, each of the memory elements having an electrical resistance representing an information item which can be influenced by a magnetic field; producing bit lines disposed transversely with respect to the gate lines and connected to the memory cells; and producing write lines disposed transversely with respect to the bit lines, the write lines cross the bit lines in regions of the memory elements.