Patent ID: 6373113
Filing Date: 2002-04-16
Classification: H01L

Abstract:
An integrated circuit comprising:a semiconductor substrate comprising an n-well and a p-well, wherein said n-well is laterally displaced from said p-well; a dielectric layer formed on an upper surface of said semiconductor substrate, wherein said dielectric layer comprises a distribution of a nitrogen bearing molecule; a first and a second gate structure formed on said dielectric layer over a first and a second channel region of said p-well and said n-well respectively, wherein said first and second gate'structures include a nitrogen bearing impurity distribution, and wherein said dielectric layer extends beyond the lateral boundaries of the first and second gate structures and wherein said dielectric layer is continuously arranged to form the gate dielectrics of the first and second gate structures; a first source/drain impurity distribution substantially contained within a first pair of source/drain regions laterally displaced on either side of said first channel region, wherein said first source/drain impurity distribution comprises ions selected from the group consisting of phosphorous and arsenic, and further wherein a peak impurity concentration of said first source/drain impurity distribution is greater than approximately 1Ã—1019 atoms/cm3; and a second source/drain impurity distribution substantially contained within a second pair of source/drain regions laterally displaced on either side of said second channel region, wherein said second source/drain impurity distribution comprises boron ions, and further wherein a peak impurity concentration of said second source/drain impurity distribution is greater than approximately 1Ã—1019 atoms/cm3.