Patent ID: 6933775
Filing Date: 2005-08-23
Classification: H03J

Abstract:
1. A circuit for detecting and correcting a center level of an FSK demodulation signal, comprising: first, second, third and fourth samplers; first and second holders, first and second subtractors, an ADA converter, an adder, a mean value calculation unit, a comparator and a bit detection unit; the third sampler and the first holder for sampling and holding a positive peak value of a baseband signal obtained from said FSK demodulation signal, the fourth sampler and the second holder for sampling and holding a negative peak value of said baseband signal, the second subtractor for determining a difference in output between said first and second holders and producing a voltage (e the ADA converter for subjecting said voltage (e the adder for adding an analog voltage, which has been output from said ADA converter, to said baseband signal such that an output from said adder is sampled by said first sampler and an output from said first sampler is held in said first holder, the first subtractor for subtracting said analog voltage from said baseband signal such that an output from said first subtractor is sampled by said second sampler and an output from said second sampler is held in said second holder, the mean value calculation unit for calculating a mean value of outputs from said first and second holders and setting said mean value as a center level for said FSK demodulation signal, the comparator for comparing said center level, which has been set by said mean value calculation unit, with binary format data of said FSK demodulation signal and outputting bit “1” or bit “0” of said binary format data on a basis of results of said comparison, the bit detection unit for feeding a detection output to said ADA converter when there are successive bits of the same polarity in binary format data output from said comparator, and the controller for controlling said first to fourth samplers, said first and second holders, said first and second subtractors, said ADA converter, said adder, said mean value calculation unit, said comparator and said bit detection unit, wherein said ADA converter retains said digital signal holding function while detection outputs are being fed from said bit detection unit.