Patent ID: 6891752
Filing Date: 2005-05-10
Classification: G11C

Abstract:
1. A method for controlling gate voltage during an erase of a flash memory device comprising a plurality of memory sectors, the method comprising: a) selecting a portion of said plurality of memory sectors ( b) selecting an unerased subset of said portion of said plurality of memory sectors ( c) applying an erase pulse having a gate erase voltage to the subset of memory sectors ( d) selecting a memory sector from the subset and erase verifying the selected sector ( e) if the selected sector is not erased, applying a monotonically increasing function to said gate erase voltage ( f) repeating c) through e) until said subset of memory sectors is erased; g) repeating steps b) through f) until said portion of said plurality of memory sectors is erased; h) resetting said gate erase voltage ( i) repeating steps a) through h) until said plurality of memory sectors is erased (