Patent ID: 7376026
Filing Date: 2008-05-20
Classification: G11C

Abstract:
1. An integrated semiconductor memory, comprising: a memory cell array comprising a plurality of memory cells, including first and second memory cells; a common word line coupled to the first and second memory cells; a first activatable sense amplifier and a second activatable sense amplifier arranged on different sides of the memory cell array, the first memory cell being coupled to the first sense amplifier via a first bit line and the second memory cell being coupled to the second sense amplifier via a second bit line; wherein a timing of activation of the first sense amplifier for a read access of the first memory cell is separately controllable from a timing of activation of the second sense amplifier for a read access of the second memory cell by respective first and second activation signals, such that the first and second sense amplifiers are activatable temporally successively for respective read accesses of the first and second memory cells; a first delay device configured to receive the first activation signal, the first delay device generating a delayed first activation signal by delaying transmission of the first activation signal to the first sense amplifier; a second delay device configured to receive the second activation signal, the second delay device generating a delayed second activation signal by delaying transmission of the second activation signal to the second sense amplifier; the first delay device including at least first and second delay elements, the first delay element of the first delay device generating the delayed first activation signal by delaying the first activation signal by a first time duration, and the second delay element of the first delay device generating the delayed first activation signal by delaying the first activation signal by a second time duration, the second time duration being different from the first time duration; and the second delay device including at least first and second delay elements, the first delay element of the second delay device generating the delayed second activation signal by delaying the second activation signal by a first time duration, and the second delay element of the second delay device generating the delayed second activation signal by delaying the second activation signal by a second time duration, the second time duration being different from the first time duration.