Patent ID: 8114723
Filing Date: 2012-02-14
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of fabricating a structure, comprising: simultaneously forming first sets of parallel two or more nano-fins and second sets of parallel two or more nano-fins on a dielectric layer, each nano-fin of each of said first and second sets of two or more nano-fins comprising an elongated block of semiconductor material extending axially along a first direction, said second sets of two or more nano-fins interdigitated with said first sets of two or more nano-fins, first ends of nano-fins of said first sets of two or more nano-fins extending past first ends of nano-fins of said second sets of two or more nano-fins in said first direction and second ends of nano-fins of said second sets of two or more nano-fins extending past second ends of nano-fins of said first sets of two or more nano-fins in said first direction; forming a gate dielectric on all exposed surface of said nano-fins of said first and second sets of nano-fins; and forming a first electrically conductive gate over only said first set of nano-fins and on said gate dielectric in spaces between said nano-fins proximate to said first ends of said first sets of two or more nano-fins; and forming a second electrically conductive gate over only said second set of nano-fins and on said gate dielectric in spaces between said nano-fins proximate to said second ends of said second sets of nano-fins.