Patent ID: 6833301
Filing Date: 2004-12-21
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device comprising:forming a gate electrode on a semiconductor substrate by performing a lithography process using a reticle, the reticle having a substantially linear gate electrode pattern having paired first and second long sides and a pair of short sides and being set on two transistor regions and sandwiched region between the two transistor regions of the semiconductor substrate, a convex portion in which at least a part of the sandwiched region is arranged being included in the first long side, a concave portion facing at least the entire length of the convex portion being included in the second long side and being substantially in the sandwiched region, a length of the concave portion parallel to the second long side being longer than a length of the convex portion parallel to the first long side, a width of the concave portion parallel to the short side being smaller than a diameter of a contact portion formed in the sandwiched region and on the gate electrode pattern.