Patent ID: 8516316
Filing Date: 2013-08-20
Classification: G01R

Abstract:
1. An apparatus for diagnosing an integrated circuit comprising: a plurality of flip-flops arranged to perform scan chain design for test procedures; a buffer chain having a plurality of buffers separate from the plurality of flip-flops, the buffer chain communicatively coupled to an output of a first flip-flop of the plurality of flip flops; a first diagnosis cell, communicatively coupled in series with the buffer chain, configured to receive a buffer chain output signal from a first intermediate buffer in the buffer chain, a first input signal, and a second input signal, and produce a diagnostic signal indicating the operational status of the integrated circuit based on at least the buffer chain output signal and the first input signal; and a second intermediate buffer configured to receive the diagnostic signal and transmit the diagnostic signal to an input of a second flip-flop of the plurality of flip-flops.