Patent ID: 6477671
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A nonvolatile memory device comprising:a plurality of nonvolatile memory cells; a chip-selecting signal terminal; and a plurality of address terminals, wherein said nonvolatile memory device is arranged to operate in a plurality of operation modes including a first operation mode and a second operation mode, wherein, if said chip-selecting signal terminal receives a first status signal, said nonvolatile memory device is capable of accessing said nonvolatile memory cells, when said nonvolatile memory device is in said first operation mode, and wherein, if said chip-selecting signal terminal receives a first status signal and a part of said address terminals receives a second status signal, said nonvolatile memory device is capable of accessing said nonvolatile memory cells, and, if said chip-selecting signal terminal receives said first status signal and said part of said address terminals receives a third status signal, said nonvolatile memory device is not capable of accessing said nonvolatile memory cells, when said nonvolatile memory device is in said second operation mode.