Patent ID: 9219125
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a field-effect transistor core region of a first-type of conductivity having a first gate stack on the substrate, the first gate stack including an interfacial layer, a capping layer of a first material over the interfacial layer, a high k (HK) dielectric layer over the capping layer of the first material such that the HK dielectric of the first gate stack is separated from the interfacial layer of the first gate stack by the capping layer of the first gate stack, wherein the HK dielectric layer of the first gate stack has a first thickness; an input/output region of the first-type of conductivity having a second gate stack on the substrate, the second gate stack including an interfacial layer, a capping layer of the first material on the interfacial layer, a HK dielectric layer on the capping layer of the first material, wherein the HK dielectric layer of the second gate stack has a second thickness; a field-effect transistor core region of a second-type of conductivity having a third gate stack on the substrate, the third gate stack including an interfacial layer, a HK dielectric layer on the interfacial layer, and a capping layer of a second material on the HK dielectric layer, wherein the HK dielectric layer of the third gate stack has a third thickness; an input/output region of the second-type of conductivity having a fourth gate stack formed on the substrate, the fourth gate stack having an interfacial layer, a HK dielectric layer on the interfacial layer, and a capping layer of the second material on the HK dielectric layer, wherein the HK dielectric layer of the fourth gate stack has a fourth thickness, and wherein the first thickness, second thickness, third thickness, and fourth thickness are all different from each other.