Patent ID: 9093517
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A radiation-hardened transistor, comprising: a p-type body well disposed in triple-well structure including a p-type substrate, a deep n-type well disposed in the p-type substrate, the p-type body well disposed in the deep n-well; an active region within the p-type body well having a perimeter defined by a shallow trench isolation region filled with a dielectric material; spaced-apart n-type source and drain regions disposed in the active region, forming a channel therebetween; a polysilicon gate disposed above, aligned with, and insulated from the channel region; and a p-type isolation region in the p-type body well formed on an inner sidewall of the shallow trench isolation region, the p-type isolation region spaced apart from the drain region separating outer edges of at least the drain region from the perimeter of the active region.