Patent ID: 7179681
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. A method of fabricating a stacked package comprising: fabricating an interposer, the interposer having conductive vias therethrough and comprising a trace layer; attaching the first side of the first plurality of integrated circuit dice to a first side of the interposer; coupling a plurality of bond wires from the second side of the first plurality of integrated circuit dice to the trace layer to electrically couple the first plurality of integrated circuit dice to the interposer; disposing a first plurality of conductive elements on the second side of the first plurality of integrated circuit dice; encapsulating the first plurality of integrated circuit dice with a first encapsulant such that the first plurality of conductive elements are exposed through openings in the first encapsulant; fabricating a multi-chip package comprising a second plurality of dice, wherein each of the second plurality of dice is coupled to a carrier and wherein a second encapsulant is disposed about the second plurality of dice, wherein the second plurality of dice comprises a second plurality of conductive elements electrically coupled to the respective second plurality of dice and wherein the second plurality of conductive elements are exposed through openings in the second encapsulant; and coupling the second plurality of conductive elements of the multi-chip package to the conductive vias of the interposer.