Patent ID: 8995748
Filing Date: 2015-03-31
Classification: G01N,G06T,H01L

Abstract:
1. A defect image processing apparatus, comprising: a matching processing unit that executes an image matching between a defect image, which is acquired by a defect inspection device or a defect review device of a semiconductor device, of a portion containing a defect of the semiconductor device and a layout image, which is generated from a layout data of the semiconductor device, of an area corresponding to an area of the defect image in a layer identical to a layer containing the defect; and an output processing unit that displays a superimposed image which is formed by superimposing the defect image on the layout image, on a display unit, the defect image being matched with the layout image by the matching processing unit, wherein when the image matching between the defect image and the layout image is executed, the matching processing unit removes or masks an image of an area of a defect portion from the defect image and executes the image matching between the layout image and a remaining image that is formed by removing or masking the image of the area of the defect portion from the defect image.