Patent ID: 6127696
Filing Date: 2000-10-03
Classification: H01L,Y10S

Abstract:
A memory circuit comprising:a) a high voltage transistor, said high voltage transistor comprising:a first set of first and second spaced-apart regions formed in a silicon substrate, said first set of first and second spaced-apart regions substantially forming a first channel in said substrate therebetween;a first gate insulator comprising a first oxide layer, said first gate insulator disposed on said first channel;a high voltage transistor control gate disposed on said first gate insulator;b) a peripheral transistor comprising:a second set of first and second spaced-apart regions formed in said silicon substrate, said second set of first and second spaced-apart regions substantially forming a second channel therebetween;a second gate insulator comprising a second oxide layer, said second oxide layer being a different layer from said first oxide layer and having a different thickness than said first oxide layer, said second gate insulator disposed on said second channel;a peripheral transistor control gate disposed on said second gate insulator; and,c) a floating gate memory device comprising:a third set of first and second spaced apart regions formed in said silicon substrate, said third set of first and second spaced apart regions substantially forming a third channel therebetween;a third gate insulator disposed on said third channel;a floating gate;an intergate insulator disposed on said floating gate; and,a memory device control gate disposed on said intergate insulator.