Patent ID: 6950921
Filing Date: 2005-09-27
Classification: G06F

Abstract:
1. A method for operating an integrated memory with a reduced number of external terminal pins including a counter for internally generating addresses and a memory cell field being able to be divided into a number of memory areas of uniform size, which comprises: receiving a control signal from outside the integrated memory unit with the external terminal pins; before a memory access, partitioning the memory cell field into a plurality of memory areas, the uniform size of the memory areas or the number of the memory areas being dependent on the control signal; for the memory access, selecting one of the memory areas by applying a memory area address to the external terminal pins; for the memory access, selecting one of the memory cells inside the selected one of the memory areas by applying a memory cell address to the external terminal pins; activating the selected one of the memory cells inside the selected one of the memory areas for a write/read access; writing/reading data in/out of the selected one of the memory cells; generating a further memory cell address, subsequent to the memory cell address of the memory cell on which the last write/read access was carried out, by the counter of the integrated memory for selecting a further memory cell in the selected one of the memory areas; performing a further write/read access in the selected one of the memory areas until the further write/read access is interrupted by an interrupt command or the further memory cell address is the last memory cell address inside the selected one of the memory areas, by repeating the following steps: