Patent ID: 6013558
Filing Date: 2000-01-11
Classification: H01L

Abstract:
A method of isolating a semiconductor device by shallow trench isolation, the method comprising:(a) etching a trench into the surface of an integrated circuit;(b) depositing an oxide in said trench, wherein at least the upper portion of said oxide is silicon-rich;(c) providing a gate electrode on the surface of the integrated circuit, wherein said gate electrode is provided substantially adjacent to said trench, with a space between the trench and the gate electrode;(d) providing a spacer oxide to cover said trench oxide, said gate electrode, and said space between said trench and said gate electrode, wherein said spacer oxide has near-stoichiometric levels of silicon;(e) etching the spacer oxide from the surface of the integrated circuit under conditions effective to selectively etch the spacer oxide from the upper surface of the integrated circuit and from the upper surface of the gate electrode without etching the trench oxide from the upper portion of the trench.