Patent ID: 8166316
Filing Date: 2012-04-24
Classification: G06F,Y02D

Abstract:
1. A system comprising: a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules; a second MMIU configured to couple to a second one or more memory modules; and a memory controller, wherein the memory controller and the first MMIU are coupled by a first link and the first MMIU and the second MMIU are coupled by a second link, and wherein the first link and the second link are part of a same interface and are operated at a same frequency, wherein the memory controller is configured to issue a memory access having an address mapped to either of the first one or more memory modules or the second one or more memory modules on the first link, wherein the first MMIU is configured to accept the memory access in response to the address being mapped to the first one or more memory modules, and wherein the first MMIU is configured to forward the memory access on the second link in response to the address not being mapped to the first one or more memory modules; wherein the first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency.