Patent ID: 7869245
Filing Date: 2011-01-11
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device having: a memory array section which is arranged on a substantially square substrate and constituted of a plurality of memory cells which store data; a plurality of first pads arranged near one side of an outer periphery of the substrate in parallel with the one side; a plurality of second pads which are arranged on an inner side of the plurality of first pads in parallel with the plurality of first pads; a plurality of first output transistors which are respectively arranged near the plurality of first pads and respectively output data read from the memory array section to the plurality of first pads; and a plurality of second output transistors which are respectively arranged near the plurality of second pads and respectively output the data read from the memory array section to the plurality of second pads, wherein each one of said plurality of first output transistors is constituted of a first complementary transistor formed of a first MOS transistor which is of a first electroconductive type and a second MOS transistor which is of a second electroconductive type, and each one of said plurality of second output transistors is constituted of a second complementary transistor formed of a third MOS transistor which is of the first electroconductive type and a fourth MOS transistor which is of the second electroconductive type, the second electroconductive type is opposite to the first electroconductive type.