Patent ID: 6226710
Filing Date: 2001-05-01
Classification: G06F,G11C,Y10S

Abstract:
A memory controller adapted to interface with a plurality of normally location-addressed randomly-accessible memory cells, the memory controller comprising:receiving means for receiving a plurality of command signals indicative of data storage and retrieval operations of the memory controller; andsignal processing means responsive to the command signal:for partitioning the plurality of memory cells into at least two tables;for storing data in certain ones of the plurality of memory cells of the tables, the data stored including a plurality of keys and a plurality of associations, wherein each key has a width and is related to one of the plurality of associations;for arranging at least two of the plurality of tables into a hierarchical relationship comprising a parent table and a child table; andfor retrieving data by searching the parent table for the desired key and if that key is not found in the parent table then searching the child table for the desired key, wherein if the width of the key searched for in the parent table is less than the width of the key searched for in the child table then the key searched for in the child table is masked to the number of data bits comprising the key stored in the child table.