Patent ID: 8832418
Filing Date: 2014-09-09
Classification: G06F

Abstract:
1. A microprocessor, comprising: a branch target address cache (BTAC), wherein each entry of the BTAC is configured to store branch prediction information and the BTAC is organized into multiple groups of N entries so that each group provides N entries for storing branch prediction information for N branch instructions per fetch quantum, wherein N is a constant integer value, N is at least two, and branch instructions are classified with replacement priorities that are based on branch instruction type; and an execution unit, configured to execute a new branch instruction previously fetched from an instruction cache in a fetch quantum; an override indicator that regularly, approximately X of every Y clock cycles, provides an indication to force an update of the BTAC with branch information for a branch instruction, wherein Y is greater than X; and update logic, coupled to the BTAC and execution unit, configured to: