Patent ID: 7103855
Filing Date: 2006-09-05
Classification: G06F,H03L

Abstract:
1. A clock control circuit comprising: an input buffer for receiving a clock input thereto; a phase-difference generating circuit, receiving an output signal of said input buffer from one input terminal and one output clock from another input terminal, for producing two output signals, having a phase difference decided by phase decision information input thereto as a control signal, between the output signal of said input buffer and the output clock; a phase comparator circuit for detecting and outputting a phase difference between the two output signals of said phase-difference generating circuit; a filter for smoothing a phase-difference detection signal output from said phase comparator circuit; a first variable delay circuit for delaying the output signal of said input buffer; and a first clock buffer, receiving an output signal of said first variable delay circuit an input, for producing an output clock; wherein the output clock of said first clock buffer is supplied as said output clock applied to said another input terminal of said phase-difference generating circuit; and wherein a delay time of said first variable delay circuit is varied by the output signal of said filter.