Patent ID: 7109751
Filing Date: 2006-09-19
Classification: G03F,G06F,G11C

Abstract:
1. A method of implementing a configuration memory cell for a programmable logic device (PLD) comprising programmable logic elements, the method comprising: implementing a bit line; implementing first and second word lines; implementing first and second cross-coupled logic gates having output terminals coupled to first and second storage nodes, respectively, each of the first and second logic gates comprising a plurality of transistors, each transistor comprising a fabrication layer implementing a gate node of the transistor, the gate node extending substantially in a first direction; implementing a first pass gate coupled between the first storage node and the bit line and having a gate terminal coupled to the first word line, the first pass gate utilizing the fabrication layer to implement a gate node thereof extending substantially in the first direction; implementing a second pass gate coupled between the second storage node and the bit line and having a gate terminal coupled to the second word line, the second pass gate utilizing the fabrication layer to implement a gate node thereof extending substantially in the first direction; and implementing an interconnection between at least one of the first and second storage nodes and at least one of the programmable logic elements, wherein throughout the configuration memory cell the fabrication layer is implemented without T-shaped polygons in compliance with the requirements for a phase shift mask.