Patent ID: 6571267
Filing Date: 2003-05-27
Classification: G06F

Abstract:
A floating point execution unit in which a subtraction circuit executes a subtraction operation only when a difference of exponent parts in two operands as floating point numbers is 1, 0, and âˆ’1, the floating point execution unit comprising:a first selection circuit for an alignment of said mantissa parts in said two operands by selecting one of cases where one of said mantissa parts in said two operands is shifted by one bit and no mantissa parts are shifted, by comparing exponent parts in said two operands; a subtraction circuit for executing a subtraction of said mantissa parts in said two operands after said alignment; a second selection circuit for selecting one of said subtraction result and an inverted value that is obtained by inverting said subtraction result; a left shifter circuit for executing normalization operation for said selected one output from said second selection circuit; an error compensation circuit for compensating a canceling prediction error in said subtraction result after said normalization operation; a canceling prediction circuit for generating a canceling bit prediction signal of said subtraction result based on said mantissa parts of said two operands before said alignment executed by said first selection circuit, and then for determining a position of said canceling bit; and a prediction error detection circuit for generating a compensation signal to compensate a prediction error indicated by said canceling bit prediction signal from said canceling prediction circuit, wherein said left shifter circuit executes said normalization operation for said subtraction result by shifting it leftward from said position of said canceling bit generated by said canceling prediction circuit, and said error compensation circuit compensates said canceling prediction error for said subtraction result that has been normalized based on said compensation signal output from said prediction error detection circuit, and wherein said canceling prediction circuit comprises: a first canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 1; a second canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is âˆ’1; a third canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 0 and said difference of said mantissa parts in said two operands is assumed as positive; a fourth canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 0 and said difference of said mantissa parts in said two operands is assumed as negative; a first selection circuit for selecting one of said canceling bit prediction signals generated by said first canceling bit prediction signal generation circuit and said third canceling bit prediction signal generation circuit when said difference of said exponent parts in said two operands is 1 or 0, a second selection circuit for selecting one of said canceling bit prediction signals generated by said second canceling bit prediction signal generation circuit and said fourth canceling bit prediction signal generation circuit when said difference of said exponent parts in said two operands is âˆ’1 or 0, a first canceling bit position determination circuit for determining a position of said canceling bit based on said canceling bit prediction signal selected by said first selection circuit; a second canceling bit position determination circuit for determining a position of said canceling bit based on said canceling bit prediction signal selected by said second selection circuit; and a third selection circuit for selecting one of said positions of said canceling bits determined by said first canceling bit position determination circuit and said second canceling bit position determination circuit based on a sign of said difference of said mantissa parts in said two operands.