Patent ID: 6445069
Filing Date: 2002-09-03
Classification: H01L

Abstract:
An integrated circuit structure comprising in combination:a. a semiconductor wafer having an upper surface, the semiconductor wafer having a plurality of identical die formed therein, each of the identical die having a plurality of semiconductor devices formed therein upon the surface of the semiconductor wafer; b. a patterned layer of interconnect metal formed upon the upper surface of the semiconductor wafer for electrically interconnecting the plurality of semiconductor devices formed within each such die, said patterned layer of interconnect metal including connection pads for making electrical connection to circuitry external to the semiconductor wafer; c. a patterned layer of nickel plated over each connection pad for mechanically and electrically bonding to the interconnect metal forming such connection pad, the patterned layer of nickel being in direct contact with the underlying connection pads; d. a patterned layer of palladium plated over the patterned layer of nickel above each connection pad for preventing the nickel from diffusing outwardly through the palladium during subsequent heating cycles; and e. a patterned layer of gold plated over the patterned layer of palladium above each connection pad to facilitate the joinder of such connection pad with a connection element.