Patent ID: 7977730
Filing Date: 2011-07-12
Classification: H01L,Y10S

Abstract:
1. A memory device, comprising: a semiconductor substrate comprising a cell array area and a peripheral circuit area; a plurality of word lines on the semiconductor substrate of the cell array area; a peripheral transistor in the peripheral circuit area; a string selection line and a ground selection line parallel to each other, the word lines being between the string selection line and the ground selection line; a cell gate insulating layer between the semiconductor substrate and the word lines, the cell gate insulating layer comprising a first insulating layer, a charge trapping layer and a blocking insulating layer, a string selection gate insulating layer between the semiconductor substrate and the string selection line, the string selection gate insulating layer thinner than the cell gate insulating layer; and a ground selection gate insulating layer between the semiconductor substrate and the ground selection line, the ground selection gate insulating layer thinner than the cell gate insulating layer, wherein the peripheral transistor comprises a peripheral gate insulating layer, the peripheral gate insulating layer including a second insulating layer and the blocking insulating layer.