Patent ID: 6211007
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A process for making a semiconductor memory cell, comprising:providing a silicon structure having a first conductivity type;forming a gate electrode over the silicon structure;defining a capacitor contact region in the silicon structure adjacent to one side of the gate electrode and a bit line contact region in the silicon structure adjacent to the other side of the gate electrode;performing a first doping operation wherein a second conductivity type dopant opposite the first conductivity type is implanted into the capacitor and bit line contact regions;forming an insulating layer over the silicon structure including the capacitor and bit line contact regions;selectively removing the insulating layer to expose the capacitor contact region without exposing the bit line contact region and to form a spacer along the sidewall of the gate electrode adjacent to the capacitor contact region; andperforming a second doping operation wherein a further dosage of a second conductivity type dopant is implanted into the exposed capacitor contact region.