Patent ID: 7404066
Filing Date: 2008-07-22
Classification: G06F

Abstract:
1. A memory control system comprising: a buffer circuit configured to receive command signals corresponding to respective memory operations, the buffer circuit operable to provide the received command signals in the order they are received; a first control circuit coupled to receive the command signals from the buffer circuit, the first control circuit operable to generate either a first group of sub-command signals or a second group of sub-command signals responsive to each respective command signal; a second control circuit coupled to receive the first group of sub-command signals from the first control circuit, the second control circuit operable to generate a respective group of processing instructions responsive to the first group of sub-command signals; a first multiplexer coupling the second control circuit to the first control circuit and to the buffer circuit, the first multiplexer operable to transfer either the first group of sub-command signals from the first control circuit or the command signals directly from the buffer circuit to the second control circuit; a third control circuit coupled to receive the second group of sub-command signals from the first control circuit, the third control circuit operable to generate a respective group of memory instructions responsive to the second group of sub-command signals; and a second multiplexer coupling the third control circuit to the first control circuit and to the buffer circuit, the second multiplexer operable to transfer either the second group of sub-command signals from the first control circuit or the command signals directly from the buffer circuit to the third control circuit.