Patent ID: 9159259
Filing Date: 2015-10-13
Classification: G09G

Abstract:
1. A testing circuit of a display panel, the display panel comprises a plurality of pixels arranged in a matrix comprising sub-pixel rows and sub-pixel columns, each of the pixels is controlled by a charging gate line and a sharing gate line, comprising: a first data testing pad electrically coupling a plurality of red sub-pixels; a second data testing pad electrically coupling a plurality of green sub-pixels; a third data testing pad electrically coupling a plurality of black sub-pixels; the sharing gate line of m-th sub-pixel row electrically connects to the charging gate line of (m+2n)-th sub-pixel row, and wherein m is a positive integer, and n is the positive integer not less than 2; k gate testing pads, wherein a row number of the sub-pixel row is divided by k to obtain a remainder q, the q-th gate testing pad electrically connects to the charging gate lines coupled with the sub-pixel row, and k and q are positive integers; and wherein 2n is not divisible by k.