Patent ID: 6288939
Filing Date: 2001-09-11
Classification: G11C

Abstract:
A circuit configuration, comprising:a plurality of memory devices each including:a programmable element having a first output and a second output;a volatile memory element having an input and an output; a switching device connecting said first output of said programmable element to said input of said volatile memory element; andtwo output terminals including a first output terminal connected to said programmable element for outputting a state of said programmable element and a second output terminal connected to said volatile memory element for outputting a state of said volatile memory element;a selection circuit connected to said memory devices, said memory devices being individually addressed via said selection circuit to output states of said programmable element and of said volatile memory element;a further volatile memory element having an output and an input connected to said first output terminal for storing the state of said programmable element in said further volatile memory element; anda comparison device connected to said output of said further volatile memory element and to said second output terminal, said comparison device comparing signals present at said output of said further volatile memory element and said second output terminal.