Patent ID: 8908434
Filing Date: 2014-12-09
Classification: G11C,H01L

Abstract:
1. A method of operating a FLASH memory cell, the FLASH memory cell comprising a floating gate being disposed over a substrate, a control gate being disposed over the floating gate, a wall line being disposed adjacent to a first sidewall of the control gate, an erase gate being disposed adjacent to a second sidewall of the control gate, a first source/drain (S/D) region being disposed in the substrate and adjacent to a sidewall of the wall line, and a second S/D region being disposed in the substrate and adjacent to a sidewall of the floating gate, the method comprising: applying a first voltage level to the control gate; applying a second voltage level to the wall line, wherein the second voltage level is lower than the first voltage level; applying a third voltage level to the first S/D region, wherein the third voltage is greater than a ground voltage; applying a fourth voltage level to the second S/D region, wherein the fourth voltage level is higher than the third voltage level; and electrically floating the erase gate using an erase gate decoding circuit, the erase gate decoding circuit comprising: a switch electrically coupled between the erase gate and a latch.