Patent ID: 6472286
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A Method for forming an integrated multiple transistor ESD protection device on a semiconductor substrate, functionally connected to an integrated circuit input or output pin which will prevent electrostatic discharge damage to said integrated circuit comprising;forming a first semiconductor layer having a first conductivity dopant type; forming a second semiconductor layer overlying said first semiconductor layer, having a similar conductivity type as said first layer, but a different dopant concentration; depositing a third semiconductor layer having a second conductivity dopant type opposite that of said first semiconductor layer, disposed in overlying relation to said second semiconductor layer; forming a plurality of first regions of said first conductivity type electrically connecting with said first semiconductor layer, having a top element making electrical contact to said first regions and said first semiconductor layer; forming a plurality of second regions of said second conductivity dopant type laterally spaced from said first regions, being electrically connected to said third semiconductor layer having a top element making electrical contact to said second regions and said second semiconductor layer; Connecting said plurality of said first regions by either polysilicon or aluminum conductor elements to said integrated circuits input or output pins, and connecting said plurality of second regions and said third regions together by either polysilicon or aluminum conductor elements and to a second voltage source, typically ground.