Patent ID: 6097307
Filing Date: 2000-08-01
Classification: G07C,G08C

Abstract:
A method, comprising the steps of:(a) powering up an integrated circuit;(b) causing said integrated circuit to transition through a first number of states to generate a first binary number;(c) using said first binary number to generate a first synchronization code and to output said first synchronization code onto an output terminal of said integrated circuit;(d) after step (c), generating a second binary number by causing said integrated circuit to transition a predetermined number of times;(e) using said second binary number to generate a verification code and to output said verification code onto said output terminal of said integrated circuit;(f) after steps (a) through (e), powering down said integrated circuit;(g) after step (f), powering up said integrated circuit;(h) after step (g), causing said integrated circuit to transition through a second number of states to generate a third binary number; and(i) using said third binary number to generate a second synchronization code and to output said second synchronization code onto said output terminal of said integrated circuit, wherein said integrated circuit comprises a first pseudo-random number generator and a second pseudo-random number generator, said method further comprising the steps of:(b1) after step (a) and before said first synchronization code is generated, loading said first pseudo-random number generator with a predetermined value; and(h1) after step (g) and before said second synchronization code is generated, loading said first pseudo-random number generator with said predetermined value; andwherein step (d) of generating a second binary number further comprises the steps of:causing said first pseudo-random number generator to transition to a new state; andcausing said second pseudo-random number generator to transition to a new state.