Patent ID: 8969165
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A method for forming a semiconductor device, comprising: providing a substrate having a transistor that includes a sacrificial gate electrode; forming a first interlayer dielectric (ILD) over the substrate and the sacrificial gate electrode; planarizing the first ILD, such that a top surface of the first ILD is substantially coplanar with an exposed top surface of the sacrificial gate electrode; removing the sacrificial gate electrode to form a first via; disposing a metal gate electrode into the first via, wherein a top surface of the metal gate electrode is substantially coplanar with the top surface of the first ILD; exposing the top surfaces of the first ILD and the metal gate electrode to a silane that selectively functionalizes the top surface of the first ILD and not the top surface of the metal gate electrode, wherein the functionalized top surface of the first ILD inhibits growth of a non-conductive metal oxide layer; and growing a non-conductive metal oxide layer on the metal gate electrode.