Patent ID: 6639838
Filing Date: 2003-10-28
Classification: G11C

Abstract:
A non-volatile memory comprising:an array of memory cells arranged in rows and columns, and organized in words, each word being defined by a plurality of memory cells in a same row, and each memory cell comprising a memory effect transistor including a control terminal, a first conducting terminal, and a second conducting terminal; bit lines connected to the first conducting terminals of said memory effect transistors; an address decoder for providing a row-selection signal and a column-selection signal for selecting a word; a plurality of control terminal lines connected to the control terminals of said memory effect transistors, each respective control terminal line being connected in common to the control terminals of said memory effect transistors of a same row; and a plurality of selection transistors connected to the second conducting terminals of said memory effect transistors, each selection transistor for selecting a respective word, and being controlled by the row-selection signal and the column-selection signal for selecting the respective word.