Patent ID: 7195969
Filing Date: 2007-03-27
Classification: H01L,Y10S

Abstract:
1. A method for forming a NMOS and PMOS device pair including fully silicided gate electrodes comprising the steps of: providing a semiconductor substrate comprising NMOS and PMOS device regions comprising respective gate structures comprising polysilicon gate electrodes; forming recessed regions on either side of a channel region comprising at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.