Patent ID: 7619916
Filing Date: 2009-11-17
Classification: G11C

Abstract:
1. An SRAM cell for providing low leakage current comprising: a first PMOS transistor having a source connected to a power supply voltage node, a gate connected to a first control signal node, and a drain connected to a first virtual power supply voltage node; a second PMOS transistor having a source connected to the power supply voltage node, a gate connected to the first virtual power supply voltage node and a drain connected to the first control signal node; a first inserted NMOS transistor having a source connected to the first control signal node, a gate connected to a second control signal node, and a drain connected to a second virtual power supply voltage node; a third NMOS transistor having a source, and a gate connected to a word line, and a drain connected to a third virtual power supply voltage node; a first NMOS transistor having a source connected to the third virtual power supply voltage node, a gate connected to the second virtual power supply voltage node, and a drain connected to a ground voltage node; a second NMOS transistor having a source connected to the second virtual power supply voltage node, and a gate connected to the third virtual power supply voltage node, and a drain connected to the ground voltage node; and a fourth NMOS transistor having a source connected to the second virtual power supply voltage node, a drain, and a gate connected to the word line, wherein a second inserted NMOS transistor having a source connected to the first virtual power supply voltage node, and a drain connected to the third virtual power supply voltage node, and a gate connected to the second control signal node such that, when the SRAM cell stores bit ‘