Patent ID: 8835256
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method for fabricating a memory array device comprising: forming a plurality of field effect transistor (FET) layers over a substrate; forming a plurality of memory element layers over the plurality of FET layers, wherein each of the memory element layers is epitaxially grown; forming a plurality of memory cell pillars by etching through portions of the plurality of memory element layers and portions of the plurality of FET layers, such that each memory cell pillar includes a FET and a memory element; forming a plurality of gate conductors configured along a first axis in parallel, wherein each gate conductor laterally surrounds a plurality of FETs along the first axis; and forming a plurality of bit lines configured along a second axis in parallel, wherein each bit line is electrically coupled to a plurality of memory elements along the second axis, the second axis being perpendicular to the first axis.