Patent ID: 6216246
Filing Date: 2001-04-10
Classification: G06F,G11C,H01L

Abstract:
An error correction code (ECC) logic circuit for receiving N sets of input data bits D(i, j) and error correction bit C(i), for generating a set of correction bits F(i), where i=1, 2, 3, . . . , N, and j=1, 2, 3, . . . , M, and N and M are positive integers, the error correction code (ECC) logic circuit comprising:a set of identical parity check blocks (P(i), i=1, 2, 3, . . . , N) wherein each of said parity check blocks P(i) includes an external input means for receiving said input data bits D(i, j) and said error correction bit C(i);every one of said parity check blocks P(i) further includes a plurality of inter-block bit input lines for directly receiving inter-block input bits from two direct bit-line interconnected parity check blocks P(i-1) and P(i+1) and each of said parity check blocks P(i) further includes a plurality of inter-block bit output lines for directly transmitting inter-block output bits to said two direct bit-line interconnected parity check blocks P(i-1) and P(i+1) wherein a parity check block P(N) having two direct bit-line interconnected parity check blocks of P(N-1) and P(1) for constituting a circular configuration; andevery one of said parity check blocks P(i) further includes an external output means for outputting said parity correction bit F(i) wherein a combination of said parity correction bits {F(i), i=1, 2, 3, . . . , N} being provided as a N-bit error decoding input to a set of identical error decoding circuits {DC(i) i=1, 2, 3, . . . , N}, defined by a combination of said parity correction bits (F(i), i=1, 2, 3, . . . N} wherein said combination constituting a single-bit circular shifting relationship, and said error decoding circuits DC(i) generating an unique bit pattern for an error occurring to each of said data bits D(i, j).