Patent ID: 6853578
Filing Date: 2005-02-08
Classification: G11C

Abstract:
1. A memory cell comprising: a first inverter for generating, at an output of the first inverter, a logical inversion of a signal at an input of the first inverter; a second inverter for generating, at an output of the second inverter, a logical inversion of a signal at an input of the second inverter, the input of the second inverter being connected to the output of the first inverter; wherein the first and second inverters are configured to operate from a voltage applied between a supply line and a return line; a feedback-control transistor having a gate and a channel between a source region and a drain region of the transistor, the channel of the feedback-control transistor being connected between the output of the second inverter and the input of the first inverter; a write-access transistor being opposite in type to the feedback-control transistor, and having a gate and a channel between a source region and a drain region of the transistor, the channel of the write-access transistor being connected between the input of the first inverter and the bit line, and the gate of the write access transistor being connected to the gate of the feedback-control transistor; a read buffer transistor having a gate and a channel between a source region and a drain region of the transistor, the gate of the read buffer transistor being connected to the output of the first inverter; and a read access transistor having a gate and a channel between a source region and a drain region of the transistor, the channel of the read buffer transistor and the read access transistor being connected in series, the series-connected channels being connected between the return line of the first inverter and the read data output line, the gate of the read access transistor being connected to a read enable line.