Patent ID: 6043694
Filing Date: 2000-03-28
Classification: G11C,H03L

Abstract:
A calibrated Delay Locked Loop (DLL) comprising:a DLL locking arrangement comprising a selectively adjustable delay line which is responsive to a received clock input signal for generating an output clock signal that is in phase with the clock input signal, and a driver for providing an output data signal from the calibrated Delay Locked Loop; anda gating circuit coupled between the selectively adjustable delay line and the driver and being responsive to the output clock signal from the selectively adjustable delay line for separately (a) generating an imitation data signal which is in phase with said output clock signal from the selectively adjustable delay line, and (b) latching a received input data signal to generate a data output signal that is in phase with said output clock signal from the selectively adjustable delay line, the gating circuit being further responsive to a switching control signal having a first logical value for coupling only the data output signal generated within the gating circuit to an input of the driver, and to the switching control signal having a second logical value for only coupling the imitation data signal generated within the gating circuit to the input of the driver; andwherein the DLL locking arrangement is responsive to the switching control signal having the second logical value for synchronizing the imitation data signal appearing at the driver output to the clock input signal received by the DLL locking arrangement to generate the output clock signal from the adjustable delay line, and is responsive to the switching control signal having the first logical value to disable any synchronization of the output data signal at the driver output to the clock input signal and to maintain a latest output clock signal produced by the adjustable delay line during the period when the switching control signal having the second logical value was applied.