Patent ID: 6391736
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for fabricating a capacitor of a semiconductor device comprising:providing a semiconductor substrate having a cell array region and a core/peripheral region; forming at least one first gate line on the cell region of the semiconductor substrate; forming a second gate line on the core/peripheral region of the semiconductor substrate; forming over the first and second gate lines a first interlayer insulating layer thereby protecting the first and second gate lines from one another; patterning the first interlayer insulating layer in the cell region to expose the semiconductor substrate between the gate lines; forming a storage node contact pad and a bit line contact pad by filling the exposed area with a first conductive material; sequentially forming a second interlayer insulating layer, a second conductive material layer, and an oxide layer on the resulting structure having the storage node and bit line contact pads; patterning the oxide layer and the second conductive material layer to expose the second interlayer insulating layer over the storage node contact pad thereby forming an opening having sidewalls and a bottom; sequentially forming a dielectric layer and a third conductive layer on the bottom and sidewalls of the opening; etching the third conductive layer until the dielectric layer on the bottom of the opening is exposed, thereby forming a conductive spacer on the dielectric layer on the sidewalls of the opening; etching the dielectric layer and the second interlayer insulating layer using the conductive spacer as a mask to expose the storage node contact pad; forming a fourth conductive layer to electrically connect the conductive spacer and the storage node contact pad; forming a third interlayer insulating layer on the resulting structure having the fourth conductive layer and the oxide layer; patterning the third interlayer insulating layer, oxide layer, second conductive layer, second interlayer insulating layer, and first interlayer insulating layer to form a contact hole to the bit line contact pad in the cell array region, and to form a contact hole to the semiconductor substrate outside of the second gate line of the core/peripheral region; forming an insulating spacer in the contact hole; forming a fifth conductive layer in the contact hole to form a contact plug; and forming a bit line on the third interlayer insulating layer thereby electrically connecting the bit line to the contact plug.