Patent ID: 6552953
Filing Date: 2003-04-22
Classification: G11C

Abstract:
A high speed signal path, comprising:a first set of inverters, each of the inverters in the first set being skewed toward a first polarity of signal transition so that each of the inverters in the first set accelerates a transition from a first logic level to a second logic level; a second set of inverters, each of the inverters in the second set being skewed toward a second polarity of signal transition, the second polarity being different from the first polarity so that each of the inverters in the second set accelerates a transition from the second logic level to the first logic level, the inverters in the first and second set being coupled in series with each other between an input node and an output node with the inverters in the first set alternating with the inverters in the second set; and a logic circuit coupling an input terminal to the input node, the logic circuit being operative to couple the input terminal to the input node responsive to a control signal having a first value, and being operable to couple an input of one of the inverters to a reference voltage responsive to the control signal having a second value that is different from the first value, the reference voltage being a voltage corresponding the logic level from which the inverter accelerates a transition.