Patent ID: 8987101
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A method of forming strained source and drain regions in a P-type FinFET structure comprising the following steps: Step S01, depositing an isolation layer on the P-type FinFET structure, the P-type FinFET structure comprises a gate and a fin having a channel region and source and drain regions extending from the channel region, wherein the source and drain regions are filled with a first semi-conductive material; Step S02, applying a lithography and etching process to expose the isolation layer in two areas on opposite sides of the gate over the source and drain regions, and then etching through the exposed isolation layer to expose the first semi-conductive material in the two areas; Step S03, forming a recess in each of the source and drain regions by etching from the exposed first semiconductor material, wherein the maximum width of the recess is smaller than that of the fin, and the sidewall surface of the recess is wrapped around by the first semi-conductive material; Step S04, selectively epitaxial growing a second semi-conductive material in the recesses, wherein the second semi-conductive material has a larger lattice constant than the first semi-conductive material; Step S05, removing the rest of the isolation layer.