Patent ID: 8674975
Filing Date: 2014-03-18
Classification: G09G

Abstract:
1. A liquid crystal display comprising: a first gate line for transmitting a first gate signal; a second gate line for transmitting a second gate signal; a first data line for transmitting a first data signal; a second data line for transmitting a second data signal; a first data switch having a first end electrically connected to the first data line for receiving the first data signal, agate end electrically connected to the first gate line for receiving the first gate signal, and a second end for outputting a first electrode voltage; a second data switch having a first end electrically connected to the second data line for receiving the second data signal, a gate end electrically connected to the first gate line for receiving the first gate signal, and a second end for outputting a second electrode voltage; a liquid crystal capacitor, electrically connected between the second end of the first data switch and the second end of the second data switch, for controlling liquid-crystal transmittance according to a difference between the first electrode voltage and the second electrode voltage; a first storage capacitor having a first end electrically connected to the second end of the first data switch and a second end; a first auxiliary switch having a first end for receiving a first common voltage, agate end electrically connected to the second gate line for receiving the second gate signal, and a second end electrically connected to the second end of the first storage capacitor, wherein the first auxiliary switch is employed to provide a control of furnishing the first common voltage to the second end of the first storage capacitor according to the second gate signal; a second storage capacitor having a first end electrically connected to the second end of the second data switch and a second end; and a second auxiliary switch having a first end for receiving a second common voltage, agate end electrically connected to the second gate line for receiving the second gate signal, and a second end electrically connected to the second end of the second storage capacitor, wherein the second auxiliary switch is employed to provide a control of furnishing the second common voltage to the second end of the second storage capacitor according to the second gate signal; providing the second gate pulse partly overlapped with the first gate pulse to the second gate line during a second interval partly overlapped with the first interval; the first auxiliary switch furnishing the first common voltage to the first storage capacitor according to the second gate pulse, and the second auxiliary switch furnishing the second common voltage to the second storage capacitor according to the second gate pulse during the second interval; providing the first gate signal having low-level voltage for turning off the first and second data switches during a third interval within the second interval and not overlapped with the first interval; and providing the second gate signal having low-level voltage for turning off the first and second auxiliary switches after the third interval.