Patent ID: 8601219
Filing Date: 2013-12-03
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a random access memory capable of storing a plurality of data supplied from a host apparatus; a nonvolatile memory including a plurality of blocks, each one of the plurality of blocks being a data erasing unit and including a plurality of pages, each one of the plurality of pages being a data programming unit and includes a plurality of memory cells, each one of the plurality of memory cells being capable of storing multiple bits; and a controller configured to flush the plurality of data stored in the random access memory to the nonvolatile memory such that a total amount of the plurality of data programmed in the nonvolatile memory is an integer times as large as a data amount storable in one block, wherein when a data amount decided to be flushed is less than one block, the controller adds data until the data amount decided to be flushed reaches an integer times as large as the data amount storable in one block.