Patent ID: 7076638
Filing Date: 2006-07-11
Classification: G06F

Abstract:
1. A processor comprising: a plurality of registers each for storing a flag designating true or false; an instruction fetching unit for fetching a plurality of instructions in parallel, each of the plurality of instructions fetched in the instruction fetching unit having an operation code field designating an operation to be executed and an execution condition field designating a register of the plurality of registers to be accessed by the operation, wherein an operation designated by an operation code field of a specific instruction fetched in the instruction fetching unit is executed only when a value determined in response to a flag stored in a specific register of the plurality of registers, the specific register designated by an execution condition field of the specific instruction, designates true; a plurality of decoders each for decoding an instruction of the plurality of instructions fetched in the instruction fetching unit; a first executing unit for executing an operation designated by an operation code field of an instruction of the plurality of instructions fetched in the instruction fetching unit in response to a decoded result in a decoder of the plurality of decoders; and an instruction issue controller for referencing a flag stored in a first register of the plurality of registers, the first register designated by an execution condition field of a first instruction of the plurality of instructions fetched in the instruction fetching unit, and for controlling the first executing unit to execute an operation designated by an operation code field of a second instruction of the plurality of instructions fetched in the instruction fetching unit instead of an operation designated by an operation code field of the first instruction in response to a decoded result of the second instruction when a value determined in response to the flag stored in the first register designates false before a decoded result of the first instruction is issued to the first executing unit by the instruction issue controller.