Patent ID: 6298106
Filing Date: 2001-10-02
Classification: H03L

Abstract:
A synthesizer that generates a digital output signal the frequency of which has a fractional relationship of value Nn/Nd, where Nn and Nd are integers, with respect to the frequency of a digital input signal, characterized in that said synthesizer comprises a frequency multiplier to multiply by a modulus M, where M is an integer number, the frequency of said input signal in order to produce a high frequency intermediate signal, and a divider that divides by (M.times.Nd)/Nn, the frequency of said intermediate signal, in order to produce said output signal, and further characterized in that (M.times.Nd)/Nn is not an integer number and in that the divider comprises a first counter that generates a clock cycle every P pulses of the intermediate signal, P being the integer part of the division of M.times.Nd by Nn, and a second counter that counts the number of clock cycles generated by the first counter and forces the generation of Q clock cycles for every Nn clock cycles generated by said first counter, where Q is the remainder of the division of M.times.Nd by Nn.