Patent ID: 6664827
Filing Date: 2003-12-16
Classification: H03L,H04J

Abstract:
A phase locked loop, comprising:a digital phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal; a digital loop filter having an input for receiving the error signal and an output for providing a control signal; a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal; a processor coupled to the digital phase comparator; and a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon that cause the processor to monitor the digital phase comparator, to detect a step change in a phase relationship between the reference clock signal and the feedback signal, and to recenter the digital phase comparator if a step change is detected.