Patent ID: 7020021
Filing Date: 2006-03-28
Classification: G11C

Abstract:
1. A method for performing over-erase correction after erase in a flash Electrically-Erasable Programmable Read Only Memory (EEPROM) that includes a plurality of field-effect transistor memory cells each having a source, a drain, a bitline connected to said drain, a floating gate, a well and a control gate, the method comprising: (a) applying an overerase verify pulse after each erase pulse in the erase process to determine if one of the flash memory cells is overerased; (b) applying an overerase correction pulse after each determining step indicates an overerased cell exists; (c) applying an overerase verify pulse after each overerase correction pulse, and if one of the flash memory cells is overerased, applying an incremented overerase correction pulse; (d) incrementing the voltage of each successive overerase correction pulse by ΔV; and (e) repeating (a)–(d) until none of said plurality of cells verifies as over-erased.