Patent ID: 6503796
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A process for fabricating an array of memory cells on a dynamic random access memory (DRAM) device comprising the steps of:providing a substrate having partially completed DRAM devices consisting of an array of device areas surrounded and electrically isolated by field oxide regions, each of said device areas having field effect transistors with gate electrodes and first and second source/drain areas; depositing a first insulating layer on said substrate; forming conducting first plug contacts in said first insulating layer to said first source/drain areas for capacitors, and forming conducting second plug contacts to said second source/drain areas for bit-line contacts; depositing a second insulating layer and forming first openings aligned over and to said first plug contacts; depositing a conformal first conducting layer over said second insulating layer and in said first openings for capacitor bottom electrodes; depositing an organic layer to fill said first openings and having an essentially planar top surface; forming second openings in said organic layer over portions of said second insulating layer between adjacent said first openings, and further, said second openings extending partially over said first openings and exposing said first conducting layer on said second insulating layer, and leaving portions of said organic layer aligned over said second plug contacts; removing exposed portions of said first conducting layer in said second openings to expose portions of said second insulating layer; removing completely remaining portions of said organic layer; partially etching back and recessing said exposed portions of said second insulating layer in said second openings; forming an interelectrode dielectric layer on said first conducting layer; depositing a second conducting layer sufficient to fill said first openings; polishing back said second and said first conducting layers to said second insulating layer over said second plug contacts to form capacitors having top plates auto-self-aligned to said second insulating layer over said second plug contacts; depositing a third insulating layer; etching third openings in said third insulating layer and said second insulating layer, said third openings aligned over and etched to said second plug contacts; forming a third conducting layer in said third openings for bit-line contacts; depositing and patterning a fourth conducting layer to form bit lines and completing said array of memory cells.