Patent ID: 7287235
Filing Date: 2007-10-23
Classification: G06F

Abstract:
1. A method of simplifying a logic circuit, the simplification being performed for achieving cycle-by-cycle equivalence checking between the logic circuit and a second logic circuit, the logic circuit being a sequential logic circuit or a combinational logic circuit, the method comprising the steps of: a. identifying whether the logic circuit is a variable delay circuit; b. if the logic circuit is a variable delay circuit, then converting the variable delay behavior to fixed delay behavior by adding an extra circuitry in the logic circuit; c. accelerating the logic circuit to produce an accelerated circuit for each output of the logic circuit, the acceleration being a circuit transform achieved by mapping the multi-cycle behavior of the logic circuit to one cycle behavior; d. combining all the accelerated circuits to get a combined accelerated circuit; e. identifying constant valued flip-flops in the combined accelerated circuit, the constant valued flip-flops being those flip-flops that do not change their values in any state of the combined accelerated circuit; and f. removing constant valued flip-flops from the combined accelerated circuit, the remaining circuit being termed as a simplified accelerated circuit.