Patent ID: 6226736
Filing Date: 2001-05-01
Classification: G06F

Abstract:
A microprocessor circuit arrangement, the circuit arrangement including a microprocessor having address signals generated to retrieve instructions and capable of executing a set of instructions in a start-up mode, and a memory arrangement that is responsive to the microprocessor and configured to generate the address signals, to retrieve the set of instructions and to provide the instructions to the microprocessor, the circuit arrangement comprising:a program memory that stores the set of instructions in noncontiguously-addressed memory locations using a plurality of possible bit-widths, wherein the memory arrangement is coupled to the program memory and responds to a chip selection signal by enabling the program memory and responds to a data word width selection signal and a least significant bit address signal by selectively retrieving multiple bit data words from the program memory; anda byte interleaver circuit configured to respond to a microprocessor-reset signal by mapping the address signals for retrieving the set of instructions, the byte interleaver circuit returning to the microprocessor a set of instructions in a first bit-width from where the instructions were stored, the byte interleaver circuit returning a set of instructions in a second bit-width from where the instructions were stored, the first and second bit-widths being different, the set of instructions causing the microprocessor to select a memory configuration as a function of the bit-width and to reconfigure the byte interleaver circuit for retrieving additional instructions rather than the set of instructions.