Patent ID: 6208561
Filing Date: 2001-03-27
Classification: G11C

Abstract:
In a semiconductor memory device including an array of Flash EEPROM memory cells, the improvement comprising in combination a decoding structure for reducing capacitive loading so as to accurately control the voltages at selected wordlines and block select lines:a memory array having a plurality of memory core cells divided into a plurality of sectors, each sector having the memory core cells therein arranged in rows of wordlines and columns of bit lines intersecting the rows of wordlines;first booster circuit means for generating a first boosted voltage to be higher than a power supply potential for driving a wordline N-well region and a second boosted voltage to be higher than the power supply potential for driving a selected wordline during a Read mode of operation;second booster circuit means for generating a third boosted voltage to be higher than the power supply potential for driving a select gate N-well region and a fourth boosted voltage to be higher than the power supply potential for driving a block select line;decoding structure including wordline decoding means responsive to said first and second boosted voltages for separately applying said first boosted voltage to the wordline N-well region and said second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region; andsaid decoding structure further including select gate decoding means responsive to said third and fourth boosted voltage for separately applying said third boosted voltage to the select gate N-well region and said fourth boosted voltage to the select block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region.