Patent ID: 6198354
Filing Date: 2001-03-06
Classification: H03L

Abstract:
An apparatus for limiting intermediate frequency variation in a multiple conversion phase locked loop, comprising:a reference oscillator generating a first reference signal, said first reference signal having a first reference frequency;a voltage controlled oscillator (VCO) generating an output signal, said output signal having an output frequency controlled by a VCO input;a first VCO divider coupled to said VCO and receiving said output signal, said first VCO divider dividing said output frequency by a first VCO divider value to generate a first VCO signal having a first VCO frequency, said first VCO signal coupled to said first reference signal to generate a first intermediate signal having a first intermediate frequency;a second VCO divider coupled to said VCO and receiving said output signal, said second VCO divider dividing said output frequency by a second VCO divider value to generate a second VCO signal having a second VCO frequency, said second VCO signal coupled to said first intermediate signal to generate a second intermediate signal having a second intermediate frequency;a loop filter coupled to said second VCO divider and receiving said second intermediate signal, said loop filter filtering said second intermediate signal to generate a VCO control signal, said VCO control signal coupled to said VCO input; andan algorithm processor coupled to said reference oscillator, said first VCO divider, said second VCO divider, and said VCO, said algorithm processor generating said first VCO divider value, and said second VCO divider value.