Patent ID: 8487316
Filing Date: 2013-07-16
Classification: H01L

Abstract:
1. An integrated semiconductor substrate structure comprising: a substrate; a GaN-heterostructure being present in a first device area for definition of GaN-based devices, the GaN-heterostructure being covered at least partially with a protection layer; and a semiconductor layer being present in a second device area for definition of CMOS devices, wherein at least one of the GaN heterostructure and the semiconductor layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor layer are laterally juxtaposed, wherein the substrate is a silicon-on-insulator (SOI) substrate comprising a handling layer, a buried insulating layer and a device layer, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the silicon-on-insulator (SOI) substrate, the buried dielectric layer and the device layer having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the silicon-on-insulator (SOI) substrate.