Patent ID: 7180786
Filing Date: 2007-02-20
Classification: G11C

Abstract:
1. A row decoder for an electrically programmable NAND memory including an array of a plurality of memory cells arranged in a plurality of rows, said memory cells being grouped into a plurality of memory blocks each one including a plurality of strings of memory cells, and each string including at least one access element for coupling the string to a respective bit line, the access elements of the strings of a respective memory block being controlled by a respective select line, the row decoder including: a global select line selectively couplable to the select line corresponding to an addressed memory block; switching means for each memory block for selectively coupling the global select line to the select line, the switching means having a respective control node; and precharging means for precharging to a select voltage the control nodes, the precharging means being activatable in a testing operation for precharging all the control nodes to the select voltage adapted to cause the coupling of the global select line to the select lines, wherein the row decoder further includes: first means for keeping at least the control node of the addressed memory block charged at said select voltage; second means for decoupling all the select lines from the global select line; and third means for providing an access voltage to the select line corresponding to the addressed memory block for enabling the respective access elements and for providing an access inhibition voltage to the select lines corresponding to the non-addressed memory block, the first, second and third means being activatable in the testing operation.