Patent ID: 6387743
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A semiconductor device manufacturing method, comprising the steps of:(a) forming first and second main source/drain regions of a first conductivity type in a surface of a semiconductor substrate and a temporary gate electrode portion on said semiconductor substrate between said first and second main source/drain regions: (b) forming first and second auxiliary side walls on sides of said temporary gate electrode portion; (c) removing said temporary gate electrode portion to obtain an opening whose sides are defined by said first and second auxiliary side walls; (d) forming first and second extension-forming side walls adjacent respectively to said first and second auxiliary side walls in said opening, said first and second extension-forming side walls containing a first extension-forming impurity of the first conductivity type; (e) after said step (d), sequentially forming a first real gate insulating film and a first real gate electrode in said opening to obtain a first real gate electrode portion; and (f) forming first and second extension regions of the first conductivity type adjacent respectively to said first and second main source/drain regions through a first diffusion process where said first extension-forming impurity in said first and second extension-forming side walls serves as a diffusion source, wherein said first real gate insulating film, said first real gate electrode, said first and second main source/drain regions and said first and second extension regions define an insulated-gate, first transistor of the first conductivity type.