Patent ID: 8411503
Filing Date: 2013-04-02
Classification: G11C

Abstract:
1. A method of operating a semiconductor memory device, comprising: coupling cell strings, comprising memory cells having gates coupled to respective word lines, to respective bit lines; discharging channel regions of third cell strings including third memory cells and precharging channel regions of remaining cell strings; applying a program pass voltage to unselected word lines; applying a program voltage of a third level to a selected word line in order to raise threshold voltages of the third memory cells; decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of the second memory cells; and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of the first memory cells, wherein the cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage.