Patent ID: 6329271
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method for forming field effect transistors in a semiconductor body of one conductivity type which has a surface layer comprising the steps of:forming over the surface layer of the semiconductor body a dual layer including an underlying thin silicon oxide layer and an overlying thick silicon nitride layer;patterning the dual layer to leave an intermediate region of the dual layer in place between two regions where it has been removed;forming an isolation trench surrounding each of said regions where the dual layer has been removed;filling said trenches with a dielectric material to the same height above the surface of the semiconductor body as that of the dual layer in said intermediate regions;forming a recess in the region of the dual layer essentially of a length to match the length of the channel desired for the field effect transistor;irradiating the semiconductor body with dopant ions characteristic of the one conductivity type to form, aligned with said last-mentioned recesses in the dual layer, an implanted buried region of the one conductivity type with an impurity concentration greater than that of the semiconductor body;forming over said recess a layer suitable for use as the gate dielectric;filling in the recess over the gate dielectric layer with conductive polysilicon to the level of the isolation trenches and the dual layer;removing at least most of the dual layer remaining in the regions between the conductive polysilicon and the isolation trench for effectively exposing the surface layer of the semiconductor body; anddoping the regions of the exposed surface layer of the semiconductor body with dopants characteristic of the conductivity type opposite said one conductivity type for forming source and drain regions of the transistors, said source and drain regions being on opposite sides of the implanted buried regions.