Patent ID: 6259278
Filing Date: 2001-07-10
Classification: G01R,H03L

Abstract:
A phase detector, comprising N phase detection units: U.sub.0, U.sub.1, . . . , U.sub.N-1, wherein N is even and N.gtoreq.4, said N phase detection units being connected in cascade configuration, each phase detection unit U.sub.j (0.ltoreq.j.ltoreq.N-1) comprising:an inverter arranged to receive a clock signal CK.sub.j ;a first D flip-flop arranged to receive a common data signal data at its data input terminal and the output signal of said inverter at its inverting clock input terminal;an exclusive OR gate arranged to receive the output signal of said first D flip-flop and another input signal; anda second D flip-flop arranged to receive the output signal of said exclusive OR gate at its data input terminal and the clock signal CK.sub.j at its inverting clock input terminal, and to output a charge/discharge signal,wherein said another input signal of said exclusive OR gate in the phase detection unit U.sub.j (0.ltoreq.j.ltoreq.N-1) is the output signal of the first D flip-flop in the phase detection unit U.sub.j+1(mod N), andwherein a phase difference between the clock signals CK.sub.j (0.ltoreq.j<N-1) and CK.sub.j+1 is 2.pi./N.