Patent ID: 7549024
Filing Date: 2009-06-16
Classification: G06F

Abstract:
1. An integrated circuit comprising: a plurality of processor cores operable to perform respective data processing operations, at least one of said processor cores for operating in both of (a) a coherent multi-processing mode having access to a coherent region within a memory shared with at least one other processor core and (b) a non-coherent mode in which coherency managing operations are never required to be performed in response to any memory access request that said at least one of said processor cores makes; at least one write enabled control parameter storage element operable to store at least one mode control parameter related to said at least one configurable processor core, said mode control parameter controlling whether said at least one configurable processor core is currently operable in a coherent multi-processing mode or in a non-coherent processing mode; a memory access control unit operable to control access to said memory by said plurality of processor cores, wherein said memory access control unit is operable to perform coherency management operations on at least some memory access requests received from said processor cores operating in a coherent multi-processing mode and to direct memory access requests received from said processor cores operating in a non-coherent processing mode to said memory without performing coherency management operations; and at least one data bus for passing said memory access requests from said at least one configurable processor core to said memory control unit, said at least one data bus comprising a main portion and a multi-processing portion, said at least one configurable processor core being operable to transmit said memory access requests via said main portion of said bus and said additional information via said multi-processing portion, said at least one configurable processor core being operable to de-activate said multi-processing portion of said bus in response to said mode control parameter indicating said at least one configurable processor core to be currently operable in said non-coherent processing mode.