Patent ID: 7408811
Filing Date: 2008-08-05
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device performs such a carrier discharging operation as to set a state that the entire memory cells in the NAND cell unit are turned on; and then sequentially turn off the memory cells in the NAND cell unit from one disposed near one of a bit line contact and a source line contact and discharge the channel carriers to another one of the bit line and the source line.