Patent ID: 7301206
Filing Date: 2007-11-27
Classification: H01L

Abstract:
1. A static memory element comprising: a first inverter having an input coupled to a left bit node and an output coupled to a right bit node, wherein the first inverter comprises a first pull-down transistor coupled in series with a first pull-up transistor; a second inverter having an input coupled to the right bit node and an output coupled to the left bit node, wherein the second inverter comprises a second pull-down transistor coupled in series with a second pull-up transistor; a first fully depleted semiconductor-on-insulator transistor having a drain coupled to the left bit node, wherein the first fully depleted semiconductor-on-transistor insulator has a first conductance that is smaller than a conductance of the second pull-down transistor; and a second fully depleted semiconductor-on-insulator transistor having a drain coupled to the right bit node.