Patent ID: 6744675
Filing Date: 2004-06-01
Classification: G11C

Abstract:
A method of programming a memory device having a charge storing layer with a first charge storing cell and a second charge storing cell, the charge storing layer being disposed between a top dielectric layer and a bottom dielectric layer, said charge storing layer having an upper portion disposed adjacent the top dielectric layer and a lower portion disposed adjacent the bottom dielectric layer, and a gate electrode disposed over the top dielectric layer, the bottom dielectric layer disposed over a substrate having a first conductive region adjacent the first charge storing cell and a second conductive region adjacent the second charge storing cell, said method comprising:programming the first charge storing cell by: selectively storing charge in the upper portion of the first charge storing cell such that substantially all of the charge stored within the first charge storing cell resides within the upper portion and substantially no charge resides within the lower portion of the first charge storing cell.