Patent ID: 7526609
Filing Date: 2009-04-28
Classification: G06F

Abstract:
1. An apparatus for accessing a storage structure, implemented in hardware said apparatus comprising: an arrangement for providing a storage access instruction; an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction; an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, wherein information contained in the predicted register number field comprises: an associative set number; a way number within set; and an offset within line; an arrangement for speculatively accessing a storage structure with a storage access instruction extended by said extending arrangement; and an arrangement for reverting to said arrangement for inputting an address if the load/store operand is not in the speculative location; wherein the storage structure is a data cache, the speculative location is a speculative cache array location, and the predicted register number field contains information to start the speculative access as soon as the instruction is available, thereby precluding a need to compute and translate a load/store address.