Patent ID: 7345359
Filing Date: 2008-03-18
Classification: H01L,H05K

Abstract:
1. An apparatus comprising a processing node; a package structure, having a first portion of a first surface coupled to the processing node, and a first layer to route input signals to the processing node at the first portion from a second portion of the surface of the package structure and to route output signals from the processing node at the first portion to the second portion of the first surface, and a second layer to route power to the processing node from a second suface of the package structure; a chip-side connector having a cavity and coupled to the second portion of the first surface such that the processing node is disposed within the cavity, the chip-side connector to provide the input signals to the first surface and receive the output signals from the first surface; and a flex circuit, including a flex cable, coupled to the chip-side connector, to communicate signals with the processing node.