Patent ID: 6199092
Filing Date: 2001-03-06
Classification: G06G

Abstract:
A semiconductor arithmetic circuit, comprising:a signal line providing a predetermined potential;a first MOS transistor and a second MOS transistor each having a gate electrode selectively switchable between a predetermined potential and an electrically floating state, a drain electrode connectable with said signal line, and a source electrode connectable with a ground potential and defining a circuit output;a first electrode assembly having a plurality of input electrodes each capacitively coupled to the gate electrode of said first MOS transistor;a second electrode assembly having a plurality of input electrodes each capacitively coupled to the gate electrode of said second MOS transistor;an input circuit for operatively applying a respective selectable set of voltages to the input electrodes of each respective one of said first electrode assembly and said second electrode assembly to thereby define a respective voltage state thereof which produces an effective capacitively coupled transistor input voltage for the gate electrode of the respective MOS transistor associated therewith, each effective capacitively coupled transistor input voltage being defined at least in part as a function of the selected set of applied voltages associated therewith and the respective coupling capacitance values of the input electrodes associated therewith;said arithmetic circuit having an operation comprising:(i) operating said input circuit to place said first electrode assembly in a first voltage state producing a first effective capacitively coupled transistor input voltage and to place said second electrode assembly in a second voltage state producing a second effective capacitively coupled transistor input voltage,(ii) setting the respective gate electrode of each one of said first MOS transistor and said second MOS transistor to the predetermined potential associated therewith,(iii) placing the respective gate electrode of each one of said first MOS transistor and said second MOS transistor in the electrically floating state associated therewith, and(iv) operating said input circuit to place said first electrode assembly in said second voltage state and to place said second electrode assembly in said first voltage state,such that an output signal provided at said circuit output being representative of a difference between said first effective capacitively coupled transistor input voltage and said second effective capacitively coupled transistor input voltage.