Patent ID: 9190127
Filing Date: 2015-11-17
Classification: G11C

Abstract:
1. A burst length control circuit comprising: a burst length input circuit configured to output a mode register burst length signal including burst length information, an on-the-fly signal, and a burst length on-the-fly signal including on-the-fly information, in correspondence to command addresses and an internal command address; a burst length generator circuit configured to output a burst length signal according to the mode register burst length signal and the burst length on-the-fly signal; a burst length adjuster configured to produce a write burst length control signal by delaying the burst length signal by a write latency time; a selection circuit configured to produce a burst length control signal by selecting, according to a write read command signal and the on-the-fly signal, any one of the burst length signal and the write burst length control signal; and a burst stop counter configured to produce a burst stop signal by counting the burst length control signal according to an internal write command signal and an internal read command signal.