Patent ID: 8618841
Filing Date: 2013-12-31
Classification: G06F,H03B,H03L

Abstract:
1. A method for reducing spurious for a clock distribution system, the method comprising: a) providing a system controller; b) providing a clock distribution system including: one or more fractional synthesizers each responsive to one of the one or more intermediate clock signals and each configured to generate an output signal at a desired frequency from a wide range of possible output frequencies based on a command from the system controller; c) inputting characteristics of the clock distribution system in advance of operation thereof; d) calculating an expected level of the integer boundary spurious as a function of fractional offset value to select a preferred region of operation; e) providing a desired frequency of the output signal of operation; f) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region; and g) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution; and h) repeating steps e) through g) as needed.