Patent ID: 8877629
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A semiconductor manufacturing process at least includes: providing a silicon substrate having a surface, at least one connection pad formed on the surface and a protection layer formed on the surface, the protection layer covers the connection pad and comprises at least one first opening revealing the connection pad; forming a first seed layer on the protection layer and the connection pad, the first seed layer comprises at least one first section and at least one second section located outside the first section; forming a first photoresist layer on the first seed layer, wherein the first photoresist layer comprises at least one first opening slot to reveal the first section; forming a first buffer layer at the first opening slot, the first buffer layer covers the first section of the first seed layer and comprises a coupling portion and a cladding portion; removing the first photoresist layer to reveal the second section of the first seed layer; removing the second section of the first seed layer to make the first section formed as a first under bump metallurgy layer; forming a support layer on the protection layer and the first buffer layer, the support layer comprises at least one second opening revealing the coupling portion of the first buffer layer, the first under bump metallurgy layer comprises a first ring wall, the first buffer layer comprises a second ring wall, wherein the first ring wall of the first under bump metallurgy layer, the second ring wall and the cladding portion of the first buffer layer are cladded by the support layer; and forming a connection portion at the second opening and covering the coupling portion of the first buffer layer with the connection portion.