Patent ID: 6507075
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A MOS transistor comprising:a semiconductor substrate of a first conductivity type; a second conductivity type well formed at a predetermined region of the semiconductor substrate of a first conductivity type; a first insulated gate pattern having sidewalls and a second insulated gate pattern having sidewalls formed on a predetermined region of the semiconductor substrate of a first conductivity type, and on a predetermined region of the well, respectively so that portions of the semiconductor substrate of a first conductivity type on both sides of the first insulated gate pattern remain exposed, and portions of the well on both sides of the second insulated gate pattern remain exposed; second conductivity type impurity regions formed in portions of a surface of the semiconductor substrate of a first conductivity type at both sides of the first insulated gate pattern that remain exposed; first conductivity type impurity regions formed in portions of a surface of the well at both sides of the second insulated gate pattern that remain exposed; a first interlayer insulating layer formed on the entire surface of the resultant structure having the first and second conductivity type impurity regions and the first and second insulated gate patterns, wherein the first interlayer insulating layer is patterned to form pad contact holes such that the first and second conductivity type impurity regions are exposed, and portions of the first interlayer insulating layer remain disposed on the first and second insulated gate patterns; a conformal undoped buffer layer formed on the entire surface of the resultant structure having the pad contact holes and the portions of the first interlayer insulating layer; a second conductivity type buffer layer formed by ion-implanting second conductivity type impurities in the conformal undoped buffer layer that is disposed on the second conductivity type impurity regions; a first conductivity type buffer layer formed by ion-implanting first conductivity type impurities in the conformal undoped buffer layer that is disposed on the first conductivity type impurity regions; sacrificial insulating layer residues covering the first and second conductivity type buffer layers formed on bottoms of the pad contact holes; and a first conductivity type pad and a second conductivity type pad formed on the first conductivity type impurity region and on the second conductivity type impurity region, respectively, formed by etching the first and second conductivity type buffer layers using the sacrificial insulating layer residues as etching masks.