Patent ID: 9082502
Filing Date: 2015-07-14
Classification: G11C

Abstract:
1. A method for operating non-volatile storage, comprising: applying a first set of one or more bit line voltages to a plurality of bit lines; verifying programming for non-volatile storage elements connected to a first set of word lines and the plurality of bit lines in response to the first set of one or more bit line voltages; applying a second set of one or more bit line voltages to the plurality of bit lines, the first set of one or more bit line voltages are lower than the second set of one or more bit line voltages; verifying programming for non-volatile storage elements connected to a second set of word lines and the plurality of bit lines in response to the second set of one or more bit line voltages, the non-volatile storage elements connected to the first set of word lines are programmed prior to programming of the non-volatile storage elements connected to the second set of word lines after a common erasing, the non-volatile storage elements connected to the first set of word lines and the non-volatile storage elements connected to the second set of word lines are in a common block; applying one or more read bit line voltages to the plurality of bit lines; and reading the non-volatile storage elements connected to the first set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, either the verifying programming for non-volatile storage elements connected to the first set of word lines or the reading the non-volatile storage elements connected to the first set of word lines includes applying a compare voltage to a selected word line for a data state on the first set of word lines that is different than another compare voltage for the data state used for non-volatile storage elements connected to the second set of word lines.