Patent ID: 6587533
Filing Date: 2003-07-01
Classification: H03L,H04J

Abstract:
A method to attenuate transients caused in a desynchroniser by stuffing events in a digital transmission system comprising a data buffer (1), a write address counter (2) controlled by a write clock (CLK1), a read counter (3) controlled by a read clock (CLK2), and a phase locked loop (PLLa; PLLd), which contains a phase discriminator (4, PD), a loop filter (AMP, AMP1; LOOP FILTER) and a controlled oscillator (5, VCO; DCO) for controlling the read and write clocks on the basis of a phase difference, said method comprising the steps of:forming a pulse signal (BPin) representing justification events upwards and/or downwards caused by phase changes in a tributary unit signal; directing the pulse signal (BPin) through second filtering means (R8 and C8; LPF); and adding the filtered pulse signal (AMP2; SUM) to the output signal of the loop filter (AMP1; LOOP FILTER), whereby the summed output signal controls the loop oscillator (VCO; DCO).