Patent ID: 7053696
Filing Date: 2006-05-30
Classification: G05F,H01L

Abstract:
1. A semiconductor device comprising: an output adjusting circuit which includes a first input terminal supplied with a fixed potential, a second input terminal supplied with a reference potential from a reference node, and an output terminal, and is operable in a standby mode and in an active mode; and an output setting unit including a first output setting circuit connected between the reference node and a reference potential terminal, and a second output setting circuit connected between the output terminal and the reference node, wherein the first output setting circuit includes at least first and second resistor elements connected in series via a first voltage-division node between the reference node and the reference potential terminal in the standby mode, and at least third and fourth resistor elements connected in series via a second voltage-division node connected to the first voltage-division node between the reference node and the reference potential terminal in the active mode, and a ratio in resistance value between the first resistor element and the second resistor element is substantially equal to a ratio in resistance value between the third resistor element and the fourth resistor element, and the second output setting circuit includes at least fifth and sixth resistor elements connected in series via a third voltage-division node between the output terminal and the reference node in the standby mode, and at least seventh and eighth resistor elements connected in series via a fourth voltage-division node connected to the third voltage-division node between the output terminal and the reference node in the active mode, and a ratio in resistance value between the fifth resistor element and the sixth resistor element is substantially equal to a ratio in resistance value between the seventh resistor element and the eighth resistor element.