Patent ID: 7256096
Filing Date: 2007-08-14
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device having a dual-damascene gate, comprising steps of: forming lightly doped drain (LDD) regions by forming a gate oxide film on a semiconductor substrate and implanting low-concentration impurities in the semiconductor substrate in accordance with a predetermined LDD pattern; forming a nitride film on the gate oxide film and forming a wide nitride film in accordance with a wide nitride pattern; forming a narrow nitride film by a narrow etching process on the wide nitride film in accordance with a predetermined narrow nitride film pattern; forming a dual-damascene gate by depositing a polysilicon layer on an exposed entire surface and smoothing the deposited polysilicon layer until a top surface of the nitride film is exposed; forming a gate electrode by removing a predetermined portion of the polysilicon layer; forming a sidewall nitride film on the gate electrode by etching the exposed nitride film in accordance with a nitride film pattern; and forming source/drain regions by performing an ion implantation process on source/drain active regions.