Patent ID: 6101598
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A method of debugging a multiple processor device fabricated on a single-chip using an external debugger comprising the steps of:receiving a first word of a sequence of words transmitted in serial from the external debugger and forming a message in a register;determining a target processor from the first word;interrupting the target processor;the target processor setting an input ready bit in a status register;reading the first word from the register by the target processor;determining a number of words of the sequence to follow the first word from the first word, the sequence of words forming a debugging message;setting a word counter to a value indicating the number of words of the sequence to follow the first word; decrementing the word counter value;clearing the input ready bit using the target processor when the value in the word counter is a predetermined value; andreturning target processor to main code execution.