Patent ID: 6157201
Filing Date: 2000-12-05
Classification: G01R,G06F

Abstract:
A method of manufacturing a batch of integrated circuits (ICs), comprising:(a) fabricating a batch of ICs;(b) testing said batch and discarding therefrom any non-functional ICs;(c) selecting a predetermined number of ICs from said batch;(d) exercising said selected ICs in a burn-in chamber, said burn-in chamber operable to subject said selected ICs to environmental stress, and said burn-in chamber having within it an input-stimuli generator to generate a programmable input-stimuli sequence, said input-stimuli sequence being coupled to input pins of each of said selected ICs; and(e) testing said selected ICs to determine a failure rate, whereby said failure rate is indicative of the longevity of the ICs in said batch.