Patent ID: 6836010
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate including a first surface and a second surface; first bonding pads disposed spaced from the substrate near a periphery of the substrate; a semiconductor chip including an upper surface disposed with second bonding pads and an undersurface mounted on the substrate first surface; at least one relay chip including (1) an upper surface disposed with third bond pads, (2) a first wiring pattern formed of wiring for connecting corresponding pad pairs of the third bonding pads, and (3) an undersurface mounted on the upper surface of the semiconductor chip; and lead wires for electrically connecting the first bonding pads and the second bonding pads via the first wiring pattern and the third bonding pads of the at least one relay chip, wherein one first bonding pad and one of a pad pair of third bonding pads corresponding to the one first bonding pad are electrically connected via one lead wire, and another of the pad pair of third bonding pads and a second bonding pad corresponding to the other of the pad pair of third bonding pads are electrically connected via another lead wire.