Patent ID: 6140990
Filing Date: 2000-10-31
Classification: G09G

Abstract:
A display comprising:a plurality of pixel assemblies arranged in a matrix of rows and columns, each of said pixel assemblies including a display element having a display electrode, and a semiconductor device having a control port, an input port and an output port, each of said output ports being connected to a corresponding display electrode;a plurality of bootstrap lines, each bootstrap line connected to said display electrodes of at least one row of said pixel assemblies;a plurality of data lines each connected to said input ports arranged in one of said column;a plurality of gate lines with each gate line associated with a row of pixels in said matrix and connected to control ports of pixel assemblies in said row for receiving gate line pulses, said control ports of semiconductor devices associated with pixels located on two adjacent rows being alternately connected to either one of two associated gate lines in an interleaved fashion; anda bootstrap pulse timing and generating circuit connected to each bootstrap line to provide a bootstrap pulse in timed relation with gate line pulses applied to each of two gate lines associated with said pixels of two adjacent rows, wherein said timing relationship causes display electrodes of alternately connected interleaved pixels of said two adjacent rows to shift in voltage in a first time frame and successive time frames, and enabling display electrodes of remaining alternately connected interleaved pixels of said two adjacent rows of pixels to shift in voltage in a second time frame and successive second time frames.