Patent ID: 8497834
Filing Date: 2013-07-30
Classification: G09G,G11C

Abstract:
1. A signal output circuit that is provided in a unit stage of a shift register, comprising: a set-reset flip-flop including a reset input terminal and a set input terminal; a logic circuit; and an analog switch, the analog switch including an input terminal connected to a line via which a clock signal is supplied, the logic circuit including a first input terminal connected to an output terminal of the flip-flop and a second input terminal connected to an output terminal of the signal output circuit, the logic circuit including an output terminal connected to a control terminal of the analog switch, and the reset input terminal being connected to the output terminal of the signal output circuit, wherein: an output of the flip-flop is (A) active when an input to the set input terminal is active, and (B) inactive when an input to the reset input terminal is active; an output of the logic circuit is (a) inactive when the output of the flip-flop and an output of the signal output circuit are inactive, and (b) active when at least one of the output of the flip-flop and the output of the signal output circuit is active; and the analog switch (i) brings in the clock signal from its input terminal when the output of the logic circuit is active, and (ii) blocks off the clock signal when the output of the logic circuit is inactive.