Patent ID: 7885806
Filing Date: 2011-02-08
Classification: G06F

Abstract:
1. A simulation method for simulating an operation of a processor (CPU) using a cycle accurate (CA) simulator comprising an instruction emulator for fetching and executing target instructions of a program sequence, an execution log recorder that records results of the executed target instructions, an instruction scheduler for scheduling the executed instructions, and a calculation re-use engine to obtain performance evaluation and operation inspection of the processor, the method comprising: fetching a sequence of target instructions including a loop; emulating the execution of the target instructions for obtaining an actual execution result of the target instructions; recording the actual execution results of the executed target instructions in the execution log recorder; scheduling the target instructions based on the recorded actual execution results; detecting the loop in the target instructions based on the execution results recorded in the execution log recorder; registering the instructions of the loop and their scheduling with the calculation re-use engine if the instructions are not already registered; and determining if a sequence of instructions in the instruction scheduler is registered with the re-use engine and if so, re-using the registered scheduling for the sequence of instructions of the loop for a subsequent cycle of the loop.