Patent ID: 7977181
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first region and a second region; forming a first gate structure in the first region and a second gate structure in the second region, the first gate structure including a first hard mask layer that has a first thickness and the second gate structure including a second hard mask layer that has a second thickness less than the first thickness; removing the first and second hard mask layer from the first and second gate structure, respectively, wherein a portion of the first hard mask layer remains in the first gate structure and all of the second hard mask layer is removed from the second gate structure; forming an inter-layer dielectric (ILD); performing a first chemical mechanical polishing (CMP) to expose a silicon layer in the second gate structure; removing the silicon layer from the second gate structure thereby forming a first trench, wherein the remaining portion of the first hard mask layer protects a silicon layer in the first gate structure from being removed; forming a first metal layer to fill the first trench; performing a second CMP to expose the remaining portion of the first hard mask layer in the first gate structure; removing the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench; forming a second metal layer to fill the second trench; and performing a third CMP to planarize the semiconductor device.