Patent ID: 7197678
Filing Date: 2007-03-27
Classification: G11C

Abstract:
1. A test circuit for testing a memory circuit, the test circuit comprising: a data input line for providing test data to be written to the memory circuit; a comparator unit connected to said data input line and to the memory circuit, said comparator unit comparing expected values received over said data input line with the test data read from the memory circuit, the test data previously having been written to the memory circuit over said data input line; and a data change circuit connected between said data input line and the memory circuit, said data change circuit being controllable depending on a result of a comparison performed in said comparator unit such that when an error occurs, further test data can be written to the memory circuit in a manner altered by said data change circuit; said data change circuit passing the test data in an unaltered form to said memory circuit if no error occurs and passing the test data in an inverted form to said memory circuit if an error occurs.