Patent ID: 8450617
Filing Date: 2013-05-28
Classification: H01L,H05K

Abstract:
1. A multilayer wiring substrate including a main face and a back face, a laminate structure in which a plurality of resin insulation layers and a plurality of conductor layers are laminated, and a plurality of main-face-side connection terminals provided on the main face for surface connection of terminals of a chip component, the multilayer wiring substrate comprising: a resin insulation layer defining a center layer located at a center in consideration of a number of the plurality of resin insulation layers; of the plurality of conductor layers, back-face-side conductor layers provided on a side toward the back face in relation to the center layer formed such that an average of area ratios of the back-face-side conductor layers becomes greater than an average of area ratios of front-face-side conductor layers provided on a side toward the main face in relation to the center layer; a conductor layer defining a center conductor located at the center in consideration of the number of the plurality of resin insulation layers; and of the plurality of resin insulation layers, back-face-side resin insulation layers provided on the side toward the back face in relation to the center conductor formed such that an average of thicknesses of the back-face-side resin insulation layers becomes greater than an average of thicknesses of front-face-side resin insulation layers provided on the side toward the main face in relation to the center conductor; wherein the plurality of resin insulation layers are made of the same material.