Patent ID: 6277717
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A fabrication method for a memory device comprising a buried bit line, the method comprising:providing a substrate comprising device isolation structures;forming a plurality of word lines on the substrate;forming a plurality of source/drains regions on sides of the word lines in the substrate;forming a first insulation layer on the substrate to cover the word lines and to fill the space between the word lines;forming a plurality of first openings in the first insulation layer to expose some of the source/drain regions, wherein the first openings serve as node contact openings;forming a liner layer along sidewalls of the node contact openings;partially filling the node contact openings with a first conductive material, wherein the first conductive material serves as node landing pads;filling a remaining space of the node contact openings with a second insulation layer, wherein the second insulation layer has a first thickness;forming a plurality of second openings in the substrate, wherein the second openings serve as bit line contact openings;partially filling the bit line contact openings with a second conductive material, wherein the second conductive material serves as bit line contacts;filling a remaining space of the bit line contact openings with a third insulation layer, wherein the third insulation layer has a second thickness, and the second thickness is greater than the first thickness of the second insulation layer;forming a plurality of trenches in the first insulation layer, wherein the trenches extend along the sides of the bit line contact openings and traverse across the first insulation layer;partially filling the trenches with a third conductive material, wherein the third conductive material serves as buried bit lines;filling a remaining space of the trenches with a fourth insulation layer, wherein the fourth insulation material has a third thickness and the third thickness is greater than the first thickness;planarizing a surface of the first insulation layer until the second insulation material is removed to expose the landing pad; andforming a bottom electrode on the exposed surface of the node landing pad.