Patent ID: 6525398
Filing Date: 2003-02-25
Classification: H01L,Y10S

Abstract:
A semiconductor device having multi-level interconnect wiring including a lowermost wiring and an uppermost wiring, and a fuse opening portion for cutting a fuse line, the semiconductor device comprising:an insulating layer formed over the fuse line; first and second etching stop layer patterns formed on the insulating layer; a multi-layer interlayer insulating structure formed overlying the first and second etching stop layer pattern; a guard ring formed in the multi-layer insulating layer structure; and a passivation layer formed over the multi-layer insulating layer structure, wherein the fuse opening portion is formed in the passivation layer and the multi-layer insulating layer structure inside the guard ring, the first etching stop layer pattern is formed under the guard ring and the second etching stop layer pattern is formed along the sidewall of the fuse opening portion inside the first etching stop layer pattern.