Patent ID: 6029006
Filing Date: 2000-02-22
Classification: G06F

Abstract:
A method of operating a data processor comprising the steps of:generating a first fetch address, the first fetch address indexing a first instruction;fetching the first instructiongenerating a second fetch address, the second fetch address indexing a second instruction;during a first time interval, executing the first instruction; and executing a loop comprising the steps of;comparing a first value to a predetermined number wherein the first value is user programmable;de-asserting an enable address signal responsive to being in a first power mode and to the first value not equaling the predetermined value, the data processor not fetching the second instruction while de-asserting the enable address signal;asserting the enable address signal responsive to being in a first power mode and to the first value equaling the predetermined value, the data processor fetching the second instruction while asserting the enable address signal;decrementing the first value during a second time interval,asserting the enable address signal responsive to being in a second power mode; andaccessing a memory system responsive to the fetch address and enable address signal.