Patent ID: 6351393
Filing Date: 2002-02-26
Classification: H01L,H05K,Y10T

Abstract:
A multi-layered interconnect structure adapted for electrically interconnecting a semiconductor chip and a circuitized substrate using solder connections, said interconnect structure comprising:a thermally conductive layer including first and second opposing surfaces; first and second dielectric layers positioned on said first and second opposing surfaces, respectively; a first electrically conductive layer within said first dielectric layer; a second electrically conductive layer within said first dielectric layer positioned between said first electrically conductive layer and said thermally conductive layer wherein said second electrically conductive layer comprises a first plurality of shielded signal conductors; and first and second pluralities of electrically conductive members positioned on said first and second dielectric layers, respectively, each of said first and second pluralities of said electrically conductive members adapted for having solder connections thereon, for being electrically connected to a semiconductor chip and a circuitized substrate, respectively, said thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of said solder connections between said first plurality of electrically conductive members and said semiconductor chip and between said second plurality of electrically conductive members and said circuitized substrate.