Patent ID: 6255169
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A process of fabricating a non-volatile memory device having reduced stress-induced-leakage-current comprising the steps of:providing a semiconductor substrate having a tunnel oxide region and a sense transistor region;forming a sacrificial oxide layer to overlie the tunnel oxide region and the sense transistor region;forming a masking pattern overlying the sacrificial oxide layer, wherein the masking pattern exposes a portion of the sacrificial oxide layer overlying the tunnel oxide region and a portion of the sacrificial oxide layer overlying the sense transistor region;introducing nitrogen atoms into the tunnel oxide region and the sense transistor region of the substrate;removing the masking pattern and the sacrificial oxide layer;forming a tunnel oxide layer overlying the tunnel oxide region and a gate oxide layer overlying the sense transistor region,wherein the tunnel oxide layer has a first thickness and the gate oxide has a second thickness, andwherein the first thickness is no greater than the second thickness; andforming a first portion of a floating-gate electrode on the tunnel oxide layer and a second portion of the floating-gate electrode on the gate oxide layer.