Patent ID: 8230173
Filing Date: 2012-07-24
Classification: G06F,Y02D

Abstract:
1. A cache memory system comprising: a plurality of first storage hierarchical units provided individually to a plurality of processors; a second storage hierarchical unit provided commonly to the plurality of processors; and a control unit controlling data transfer between the plurality of first storage hierarchical units and the second storage hierarchical unit, wherein each of the plurality of processors is capable of executing a no-data transfer store command as a store command that does not require data transfer from the second storage hierarchical unit to a corresponding first storage hierarchical unit, each of the plurality of first storage hierarchical units outputs a transfer-control signal when executing the no-data transfer store command output by a corresponding processor of a first storage hierarchical unit and a cache miss hit occurs indicating that the first storage hierarchical unit of the corresponding processor does not have data designated by the no-data transfer store command, and the control unit updates state information of a first storage hierarchical unit corresponding to a first processor from among the plurality of processors without performing data transfer at least from the second storage hierarchical unit to the first storage hierarchical unit corresponding to the first processor with respect to a storage area designated by the first storage hierarchical unit corresponding to the first processor, in case where the transfer-control signal is output by the first storage hierarchical unit corresponding to the first processor.