Patent ID: 9048855
Filing Date: 2015-06-02
Classification: H03K,H03M,H04L

Abstract:
1. A semiconductor device, comprising: a scrambling code generator configured to generate a scrambling code using a seed; a scrambler configured to scramble a first parallel data group, which includes at least two sets of N-bit parallel data, using the scrambling code and generate a second parallel data group, which includes at least two sets of N-bit scrambled parallel data, where N is 2 or an integer greater than 2; a balance encoding block configured to receive the second parallel data group, perform direct current (DC) balance encoding of the N-bit scrambled parallel data sets in the second parallel data group, and generate M-bit balance codes, where M is an integer greater than N; and an output driver configured to sequentially output the balance codes and the seed through a plurality of data lines.