Patent ID: 6185141
Filing Date: 2001-02-06
Classification: G11C

Abstract:
A semiconductor device for operating in response to a plurality of control signals, comprising:a plurality of pads for receiving a plurality of control signals;a precharge control pad for receiving a test precharge signal for designating precharge timing in a test mode;a memory cell array including a plurality of memory cells arranged in rows and columns,said memory cell array including a plurality of bit line pairs arranged corresponding to the respective columns of said memory cells; anda control circuit for controlling operations of said semiconductor device in response to said plurality of control signals,said control circuit including a precharge control circuit for instructing a precharge operation for said plurality of bit line pairs, andsaid precharge control circuit instructing execution of said precharge operation in accordance with a combination of the signal levels of said plurality of control signals in a normal operation, and instructing execution of said precharge operation in accordance with the signal levels of said test precharge signal in the test mode.