Patent ID: 6404359
Filing Date: 2002-06-11
Classification: H03M

Abstract:
A variable length code decoding system having a cache memory and so configured to execute a decoding by accessing said cache memory by using a variable length code as an address, the system comprising a hit/mishit discriminating means for discriminating whether or not said cache is hit, by comparing said address with a tag read out from said cache memory in only a limited range corresponding to an effective code length of the variable length code,Said hit/mishit discriminating means includes a mask circuit and a comparing circuit, said mask circuit receiving code bits of 7 bits succeeding to a firstly appeared â€œ1â€  in a modified Huffman code sequence, a tag value of 7 bits outputted from said cache memory, and a number of remaining bits in an actual code, succeeding to said firstly appeared â€œ1â€ , which is a portion of data outputted from said cache memory, said mask circuit outputting said code bits of 7 bits succeeding to said firstly appeared â€œ1â€  and having bits which are other than said remaining bits in the actual code and which are masked by said mask circuit, and said tag value of said 7 bits outputted from said cache memory and having bits which are other than said remaining bits in the actual code and which are masked by said mask circuit, said comparing circuit receiving and comparing said code bits of 7 bits having the bits masked by said mask circuit and said tag value of said 7 bits having the bits masked by said mask circuit, said comparing circuit outputting a control signal indicative of a cache hit only when coincidence is obtained in the comparison and a valid bit outputted from said cache memory is indicative of valid, said comparing circuit otherwise outputting a control signal indicative of a mishit.