Patent ID: 7707019
Filing Date: 2010-04-27
Classification: G06F

Abstract:
1. A method of hardware co-simulation implemented within a computer involving a high level modeling system and an integrated circuit (IC) coupled to the computer, said method comprising: simulating a design under test within the computer, wherein at least a portion of the design under test is implemented in hardware within the IC; storing a first hardware co-simulation command within a command buffer within a physical memory of the computer, the first hardware co-simulation command controlling operation of the portion of the design under test implemented within the IC; returning from a function call that initiated the first hardware co-simulation command without causing the first hardware co-simulation command to be sent from the computer to the IC when no send condition is detected; storing at least a second hardware co-simulation command within the command buffer within the physical memory of the computer, the second hardware co-simulation command controlling operation of the portion of the design under test implemented within the IC; determining a type of the second hardware co-simulation command; and responsive to detecting a send condition during hardware co-simulation comprising identifying the second hardware co-simulation command as a selected type of command, within the computer, packaging the first and at least the second hardware co-simulation commands together and sending the first and at least the second hardware co-simulation commands from the command buffer of the computer to the IC as a single transaction.