Patent ID: 6114768
Filing Date: 2000-09-05
Classification: H01L,Y10S

Abstract:
An integrated circuit comprising:a device layer having first and second surfaces, one or more devices formed in the first surface of the device layer, each device having one or more internal device contacts on the first surface of the device layer for connecting one internal device contact to other internal device contact;one or more vias in the device layer, each via filled with conductive material, said vias extending from the first surface of the device layer to the second surface of the device layer and terminating in an external circuit contact for connecting the integrated circuit to other, external circuits;a handle wafer;an interconnect layer disposed between the first surface of the device layer and the handle wafer for interconnecting one or more devices in the device layer to one or more other devices in the device layer, said interconnect layer comprising a dielectric material for insulating a plurality of elongated conductors from each other, each of said elongated conductors having one end connected to one or more internal device contacts and the other end connected to one of the conductive vias.