Patent ID: 6806530
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A memory device, comprising:a memory transistor comprising a tunnel insulating layer, first conductive layer patterns, and second conductive layer patterns stacked on a first portion of a semiconductor substrate, and a common source region and a floating junction region arranged at opposite sides of the second conductive layer patterns; and a selection transistor, which is connected to the floating junction region, the selection transistor comprising a gate insulating layer, the first conductive layer patterns, and the second conductive layer patterns stacked on a second portion of the semiconductor substrate, and a drain region arranged at one side of the second conductive layer patterns opposite the floating junction region, wherein the first conductive layer patterns in the memory transistor are separated by cell unit and floated, wherein the insulating layer and the second conductive layer patterns stacked on the first conductive layer patterns are connected to a cell and an adjacent cell, and wherein the first conductive layer patterns and the second conductive layer patterns of the selection transistor are etched and connected by metal plugs.