Patent ID: 6143613
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A process for manufacturing an integrated circuit, comprising the steps of:(a) defining a region of a silicon substrate for formation of a polysilicon resistor adjacent a field effect transistor, the region including a first structure extending from the substrate spaced apart from a second structure extending from the substrate, the first and second structure each including a polysilicon strip on an oxide pad, the oxide pad being positioned between the polysilicon strip and the substrate, The first structure being bounded by a first spacer wall and the second structure being bounded by a second spacer wall separated from the first spacer wall along the substrate to define a gap therebetween;(b) depositing a silicon dioxide layer on the region, the silicon dioxide layer covering the first and second structures and filling the gap;(c) removing a portion of the silicon dioxide layer by chemical mechanical polishing to expose the polysilicon strip of each the first and second structures, the silicon dioxide layer remaining in the gap after said removing and the polysilicon strip of each of the first and second structures defining a generally planar surface;(d) providing a metallic layer covering the generally planar surface;(e) establishing a photoresist pattern on the metallic layer, the photoresist pattern defining an opening over the first structure and covering the second structure;(f) etching the metallic layer to remove a portion of the metallic layer corresponding to the opening over the first structure to reexpose the polysilicon strip of the first structure;(g) stripping the photoresist pattern;(h) performing a self-aligned silicidation process to define a silicide layer from a portion of the polysilicon strip of the second structure; and(i) completing formation of the polysilicon resistor from the first structure and the field effect transistor from the second structure.