Patent ID: 6465334
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A method of forming a semiconductor device comprising at least one MOS transistor, comprising the sequential steps of:(a) providing a semiconductor substrate including at least a region of a first conductivity type and having a surface; (b) forming in said region of first conductivity type a pair of spaced-apart source and drain regions of a second, opposite conductivity type, said pair of spaced-apart source and drain regions extending to said substrate surface and including a pair of opposed, facing edges with a space therebetween; (c) forming a layer of an insulative material extending over said substrate surface; (d) exposing a portion of said substrate surface including said pair of facing edges of said pair of spaced-apart source and drain regions and said space therebetween; (e) forming an ultra-thin catalytic layer comprising at least one metal on said exposed portion of said substrate surface; (f) forming a layer of a gate insulator precursor material on said catalytic layer by electroless plating; (g) converting said layer of electrolessly-plated gate insulator precursor material into a layer of a gate insulator material; and (h) forming an electrically conductive gate electrode material in contact with said layer of gate insulator material.