Patent ID: 6963560
Filing Date: 2005-11-08
Classification: H04J

Abstract:
1. A system for processing digital signals, comprising: a pointer follower to receive a first digital signal having a first signal frame, first embedded payload and a pointer follower (“PF”) pointer, extract said first embedded payload from said first digital signal and forward said first embedded payload; an elastic buffer in electrical connection with said pointer follower operable to receive, delay and forward said first embedded payload; a pointer generator to receive said first embedded payload and a synchronization pulse and construct a new digital signal comprising said first embedded payload, a new signal frame, and a pointer generator (“PG”) pointer, wherein the location of said new signal frame within said new digital signal is determined according to said synchronization pulse; and a synchronization module to generate said synchronization pulse according to a predetermined schedule and communicate said synchronization pulse to said pointer generator; a first comparator operable to compare the value of said PF pointer and the value of said PG pointer and generate a pointer offset signal; and a second comparator operable compare said pointer offset signal a target offset signal, generate an increment/decrement request signal based on the comparison, and communicate the increment/decrement request signal to said elastic buffer; and wherein said elastic buffer delays said embedded payload according to said increment/decrement signal; a PG counter synchronized according to said synchronization pulse; a PF counter to track the location of said signal frame of said first digital signal; and a third comparator to measure the offset between said PG counter and said PF counter.