Patent ID: 6682993
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A method of forming a protection circuit for protecting integrated semiconductor active devices from damage due to ESD voltages appearing on the circuit power bus lines said method comprising:connecting source region of a used PMOS device and the source and gate of an unused PMOS device to a first voltage source; connecting the drains of said used and unused PMOS devices to the active devices input/output pad; connecting the drain of said used PMOS device to a drain of a first used NMOS device, and the drain of said unused PMOS device to a drain of a first unused NMOS device; connecting the gate of said used PMOS device and the gate of a second used NMOS device to separate logic signal lines; connecting the gates of said first used and said first unused NMOS devices to said first voltage source; connecting the source of said first used NMOS device to the drain of said second used NMOS device and connecting the source of said first unused NMOS device to the drain of a second unused NMOS device; connecting the source of said second used NMOS device and the source and gate of said second unused NMOS device to a second voltage source; and connecting an ESD discharging means for discharging ESD energy appearing between said first and second voltage source, wherein said ESD protection discharging means comprises a discharging NMOS device with a special dopant region under and around said device normal drain region of opposite dopant than the normal drain region, and a resistor with a value between 1,000 and 100,000 ohms.