Patent ID: 7944726
Filing Date: 2011-05-17
Classification: G11C,H03K

Abstract:
1. An apparatus comprising: a memory controller having first circuitry to access a first memory and a second memory of a first memory module coupled to a memory channel, and the memory controller having second circuitry to access a third memory of a second memory module coupled to the memory channel, the first memory having a first on-die termination (ODT) circuit, the second memory having a second ODT circuit, the third memory having a third ODT circuit, and the memory controller having third circuitry to provide a first ODT signal to disable the first ODT circuit of the first memory when the first memory is to be active, the third circuitry to provide a second ODT signal to enable the second ODT circuit of the second memory of the first memory module when the first memory is to be active and the third circuitry to provide a third ODT signal to enable the third ODT circuit of the third memory when the first memory is to be active and the second memory module is to be non-active.