Patent ID: 8068559
Filing Date: 2011-11-29
Classification: H03K,H04J,H04L

Abstract:
1. A pulse width modulation (PWM) clock and data receiver, comprising: a first digital-to-analog (D/A) converter; a second D/A converter; a third D/A converter coupled to a transformer; a first comparator having a first input port, a second input port, and a first output port, the first input port coupled to the transformer and the second input port coupled to the first D/A converter; a second comparator having a third input port, a fourth input port, and a second output port, the third input port coupled to the transformer and the fourth input port coupled to the second D/A converter; a clock and data recovery (CDR) element coupled to the first and second output ports, the CDR element configured to recover, based on the first and second comparators, digital data and a clock signal from a data signal received via the transformer; and a PWM control element configured to transmit a first PWM control signal to the first D/A converter, a second PWM control signal to the second D/A converter, and a third PWM control signal to the third D/A converter, wherein the first D/A converter is configured to convert the first PWM control signal into a first direct current (DC) voltage for biasing the first comparator, wherein the second D/A converter is configured to convert the second PWM control signal into a second DC voltage for biasing the second comparator, and wherein the third D/A converter is configured to convert the third PWM control signal into a third DC voltage for biasing of the first and second comparators.