Patent ID: 6298432
Filing Date: 2001-10-02
Classification: G06F

Abstract:
A one-chip microcomputer, comprising:a Reduced Instruction Set Computer (RISC) type processor, said RISC type processor being a pipeline processor and including a bypass circuit for generating a flag corresponding to a result of a comparison instruction so that the result of the comparison instruction is available for use in the same pipeline cycle in which the comparison instruction was executed; andone or more coprocessors, said coprocessors having one or more registers and being coupled to said RISC type processor via a coprocessor bus, at least one of said coprocessors having a plurality of general purpose registers and a plurality of control registers, wherein one or more of said control registers are mapped as internal registers for said RISC type processor;wherein said RISC type processor employs multiple purpose instructions formed by adding a plurality of bits to respective fixed-length instructions.