Patent ID: 6541827
Filing Date: 2003-04-01
Classification: H01L

Abstract:
An insulated gate type semiconductor device comprising:a plurality of transistor cells, each of which comprising; a first conductivity type semiconductor layer, a body region comprising a second conductivity type diffusion region provided on a surface of said semiconductor layer, said body region being formed in a quadrilateral form, a first conductivity type diffusion region formed on the surface of said body region, a channel region formed on the surface of said body region between said first conductivity type diffusion region and said first conductivity type semiconductor layer, said plurality of transistor cells being arranged in a matrix to adjoin one corner of four of said plurality of transistor cells, and a gate electrode provided on the surface of said semiconductor layer via an insulator film so as to cover at least the surface of said channel regions, said gate electrode being patterned with removed portions to have a certain shape, the removed portions being formed above where adjoining four transistor cells are bordering on each other, without including any part of said channel regions.