Patent ID: 6492238
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a complementary metal-oxide-semiconductor (CMOS) circuit, the process comprising the steps of:(a) providing an intermediate semiconductor structure having a bipolar area and a CMOS area with a gate conductor; (b) providing an intrinsic base layer, having a thickness, in the bipolar area; (c) forming a base oxide across both the CMOS and bipolar areas; (d) depositing on both the CMOS and bipolar areas an emitter stack silicon layer having a thickness; (e) applying a photoresist to protect the bipolar area; (f) etching to remove the emitter stack silicon layer from the CMOS area only such that the top surface of the emitter stack silicon layer on the bipolar area is substantially flush with the top surface of the CMOS area; and (g) depositing a polish stop layer having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP).