Patent ID: 8285970
Filing Date: 2012-10-09
Classification: G06F

Abstract:
1. A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks, and a processing unit, the method being performed by the processing unit and comprising: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the at least one local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the at least one local page address linking table; wherein the step of providing the block of the memory apparatus with the local page address linking table within the memory apparatus further comprises: building a temporary local page address linking table for the local page address linking table during programming/writing operations of the memory apparatus; wherein the step of providing the block of the memory apparatus with the local page address linking table within the memory apparatus further comprises: temporarily storing the temporary local page address linking table in a volatile memory of the memory apparatus, and further updating the temporary local page address linking table when any linking relationship between a physical page address and a logical page address of a page in the block is changed.