Patent ID: 6100150
Filing Date: 2000-08-08
Classification: H01L,Y10S

Abstract:
A method of providing a more uniform temperature for a semiconductor wafer during processing, comprising the steps of:providing said semiconductor wafer, having a top surface, a bottom surface, said semiconductor wafer patterned with gate electrode structures on said top surface;depositing a first silicon nitride layer on said top surface and said gate electrode structures;depositing a first in situ polysilicon layer on top of said silicon nitride layer;depositing a second in situ polysilicon layer on said bottom surface;etching back said first in situ polysilicon layer;etching back said first silicon nitride layer, creating spacers bordering both sides of each of said gate electrode structures;implanting source and drain regions adjacent to each side of said gate electrode structure;subjecting said semiconductor wafer to rapid temperature annealing (RTA); anddepositing a metal layer on top of said top surface and said gate electrode structures.