Patent ID: 6778627
Filing Date: 2004-08-17
Classification: G11C

Abstract:
A shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, a first voltage and a second voltage, comprising:a first transistor having a first gate coupled to an output of a previous-stage shift-register unit, a first drain coupled to the first voltage and a first source; a second transistor having a second gate coupled to an output of a next-stage shift-register unit, a second drain coupled to the first source and a second source coupled to the second voltage; a third transistor having a third gate coupled to the second gate, a third drain coupled to the first voltage and a third source; a fourth transistor having a fourth gate coupled to the first gate, a fourth drain coupled to the third source and a fourth source coupled to the second voltage; a fifth transistor having a fifth gate coupled to the third source, a fifth drain coupled to a connection point of the first source and the second drain and a fifth source coupled to the second voltage; a sixth transistor having a sixth gate coupled to the fifth drain, a sixth drain coupled to the clock signal and a sixth source coupled to an output terminal; and a seventh transistor having a seventh gate coupled to the fifth gate, a seventh drain coupled to the output terminal and a seventh source coupled to the second voltage.