Patent ID: 7519750
Filing Date: 2009-04-14
Classification: H03L,H04L

Abstract:
1. A burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system, for recovering a clock signal from a subscriber data burst having a non-data preamble of less than 250 ns, the circuit having an adjustable bandwidth and comprising: (a) an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; (b) a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input corresponding to a difference between the frequency and phase of the output clock signal and that of the data burst until the output clock signal is substantially locked in frequency and phase to the reference signal; (c) a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input corresponding to a difference between the frequency and phase of the output clock signal and that of the data burst until the output clock signal is substantially locked in frequency and phase to the data burst; (d) a system controller constructed and arranged to selectively widen and narrow the bandwidth of the circuit and to generate a selector signal; and (e) a selector constructed and arranged to switch the signal provided to the oscillator input between the first and second feedback signals in response to the selector signal data signal; wherein the system controller widens the bandwidth of the circuit in response to a data detected signal and generates the selector signal in response to the data detected signal; the adjustable oscillator generates the output clock signal that is substantially locked in the frequency and phase to that of the data signal; and the system controller narrows the bandwidth of circuit before receipt of a last bit of the preamble.