Patent ID: 6831870
Filing Date: 2004-12-14
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising:a plurality of sub memory units each having a plurality of bit lines connected to memory cells, said bit lines corresponding to different data terminals with numbers, said sub memory units being arranged in a direction orthogonal to a wiring direction of said bit lines, a plurality of sense amplifiers connected to said bit lines, and a plurality of column switch circuits connecting said bit lines to data bus lines, respectively; a plurality of main memory units each comprising an even number of said sub memory units having different addresses from each other and comprising a defective sub memory unit; a redundancy memory unit having at least one of said sub memory units, and being enabled when said defective sub memory unit is disabled; and column switch areas formed in said main memory units, and having said column switch circuits arranged therein, wherein every two of said column switch areas are formed in mirror symmetry in the wiring direction of said bit lines, and for each of said data terminals, the data bus lines having a same logic are wired in said main memory units and said redundancy memory unit.