Patent ID: 7480495
Filing Date: 2009-01-20
Classification: H04N,H05K

Abstract:
1. A cable television tuner comprising an up/down tuner, said up/down tuner comprising: a data circuit for transmitting and receiving a signal to and from a cable television station; an input filter circuit for filtering the signal received by said data circuit; a first mixer circuit for mixing the signal passing through said input filter circuit with a first local oscillation signal to generate a first intermediate frequency signal; a first local oscillation circuit including a first phase-locked loop circuit and a first voltage-controlled oscillator for supplying the first local oscillation signal to said first mixer circuit; a first intermediate frequency circuit for filtering and amplifying the first intermediate frequency signal; a second mixer circuit for mixing a signal output from said first intermediate frequency circuit with a second local oscillation signal to generate a second intermediate frequency signal; a second local oscillation circuit including a second phase-locked loop circuit and a second voltage-controlled oscillator for supplying the second local oscillation signal to said second mixer circuit; a second intermediate frequency circuit for filtering and amplifying the second intermediate frequency signal; and a housing including a plurality of partitioned chambers for housing therein said data circuit, said input filter circuit, said first mixer circuit, said first local oscillation circuit, said first intermediate frequency circuit, said second mixer circuit, said second local oscillation circuit, and said second intermediate frequency circuit; wherein said second mixer circuit, said second phase-locked loop circuit, and said second voltage-controlled oscillator are integrated into a single-chip integrated circuit; said first local oscillation circuit and said second local oscillation circuit are housed in respective ones of the plurality of partitioned chambers that are adjacent to each other; and each of said first phase-locked loop circuit and said second phase-locked loop circuit includes a common clock terminal, and each of said first phase-locked loop circuit and said second phase-locked loop circuit includes a common data terminal.