Patent ID: 6297108
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A method of forming a high voltage metal-oxide semiconductor (HVMOS) transistor on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, a silicon oxide layer positioned on the silicon substrate, and a silicon nitride layer positioned on a predetermined area of the silicon oxide layer, the method comprising:performing a lithographic process to form a photoresist layer on the semiconductor wafer, the photoresist layer being used as a mask and comprising at least an opening through to the surface of the silicon nitride layer;performing a first ion implantation process to implant a first specific dosage of dopants into the silicon substrate under the opening;removing the photoresist layer on the semiconductor wafer;performing a thermal oxidation process to form a field oxide layer in the region not covered by the silicon nitride layer, and to simultaneously drive the dopants into the silicon substrate so as to form doped regions that are used as a source and a drain of the high voltage metal-oxide semiconductor (HVMOS) transistor;removing the silicon nitride layer on the semiconductor wafer;forming a gate on the silicon substrate between the two doped regions;forming a spacer around the walls of the gate; andperforming a second ion implantation process to implant a second specific dosage of dopants into the two doped regions so as to cause the two doped regions to each have a double diffuse drain (DDD).