Patent ID: 8201123
Filing Date: 2012-06-12
Classification: G06F

Abstract:
1. A method of tuning an input/output (I/O) interface of a circuit design for a selected programmable integrated circuit, the method comprising: determining that the I/O interface does not meet a timing requirement and an amount of adjustment required to meet the timing requirement; determining a granularity of adjustment for a first timing adjustment technique corresponding to clock phase delay and a granularity of adjustment for a second timing adjustment technique corresponding to delay of an I/O data signal available from the selected programmable integrated circuit; comparing the amount of adjustment required by the I/O interface with the granularity of adjustment for the first timing adjustment technique and the granularity of adjustment for the second timing adjustment technique; automatically selecting a timing adjustment technique according to the comparing; and adjusting, using a processor, a timing setting using the selected timing adjustment technique.