Patent ID: 6333666
Filing Date: 2001-12-25
Classification: G11C

Abstract:
An antifuse circuit for use in a chip, comprising:a power-up detecting means for generating a power stabilization signal by detecting a supply voltage;a power-up pulse means for generating a first and a second control signal in response to the power stabilization signal;an antifuse programming means for, under the control of the first and the second control signals, detecting whether an antifuse element is programmed or not, latching the result of the detection and programming the antifuse element in response to an external high voltage and a precharge signal;a pin for receiving the external high voltage so as to program the antifuse element;a pad for providing the external high voltage to the inside of the chip; anda diode for supplying the external high voltage to the antifuse programming means and preventing a voltage of the antifuse programming means from being provided to the pin.