Patent ID: 6525595
Filing Date: 2003-02-25
Classification: G06K,H02M

Abstract:
A booster, comprising:first to k-th (k is an even number) transistors connected to one another in series; first to k-th capacitors each having a terminal connected to a gate and a source of each of said first to k-th transistors; and a clock driver which supplies clock signals out of phase with one another to the other terminals of said first to k-th capacitors, said clock driver simultaneously supplies clock signals to said first to k-th capacitors, wherein the clock signals at two or more adjacent capacitors of said first to k-th capacitors are at a low level simultaneously; wherein said clock driver comprises: a frequency demultiplier which divides a reference clock signal into divided signals and inverted divided signals, which are inverted signals of said divided signals; and a circuit which receives said divided signals and said inverted divided signals, and outputs said clock signals with k number of phases.