Patent ID: 7061109
Filing Date: 2006-06-13
Classification: G01R,H01L,H05K

Abstract:
1. A substrate for testing at least one semiconductor device having at least one substantially spherical interconnection element protruding from a surface thereof, consisting essentially of: a semiconductor substrate having a dielectric layer on an exposed surface thereof; at least one conductive trace over the dielectric layer; a passivation layer over the at least one conductive trace and the dielectric layer; and a metal-lined via extending through the passivation layer to a portion of the at least one conductive trace, wherein the metal of the metal-lined via is in electrical communication with the at least one conductive trace, wherein the metal-lined via is sized and configured to receive, without deformation, the at least one substantially spherical interconnection element protruding from the at least one semiconductor device to a depth corresponding to approximately 10% to 50% of an overall height of the substantially spherical interconnection element and establish an electrical connection therewith at the depth by way of biased contact of only a portion of an interior surface of the metal-lined via with only a portion of an exterior surface of the substantially spherical interconnection element received therewithin.