Patent ID: 6738306
Filing Date: 2004-05-18
Classification: G11C

Abstract:
A multiport SRAM (static random access memory) cell comprising:a bistable loop of a first inverter and a second inverter, wherein an input terminal of the first inverter is coupled to an output terminal of the second inverter at a first bistable node, and wherein an input terminal of the second inverter is coupled to an output terminal of the first inverter at a second bistable node; a single-ended port coupled to one of the first bistable node or the second bistable node; wherein the single-ended port is operable to both read data from and write data to the bistable node through a same single transistor; and a differential port coupled to both of the first and second bistable nodes, wherein the differential port is operable to both read data from and write data to the bistable nodes through a same pair of transistors.