Patent ID: 8471618
Filing Date: 2013-06-25
Classification: H03K

Abstract:
1. A flip-flop, powered by a first voltage source and receiving a low swing clock signal, wherein the low swing clock signal is inverted according to a second voltage source lower than the first voltage source to obtain an inverted low swing clock signal, comprising: a first NMOS transistor, coupled between a receiving node and a first node and having a gate coupled to the inverted low swing clock signal, the first NMOS transistor passing a data signal from the receiving node to the first node when the inverted low swing clock signal is at a logic high level; a first latch circuit, coupled between the first node and a second node, capable of inverting the data signal to generate an inverted data signal on the second node; a second NMOS transistor, coupled between the second node and a third node and having a gate coupled to the low swing clock signal, the second NMOS transistor passing the inverted data signal from the second node to the third node when the low swing clock signal is at the logic high level; and a second latch circuit, coupled between the third node and a fourth node, capable of inverting the inverted data signal to generate an output signal on the fourth node.