Patent ID: 6492205
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method of fabrication of buffer cells in power line areas between macro cells in a semiconductor device; comprising the steps of:a) providing a substrate with a macro block area and a standard cell area; providing macro cells in said macro block area; said macro cells separated by power line areas; providing a driver located in said standard cell area; b) forming at least a buffer cell in said power lines areas; c) forming a plurality of interconnect layers over said substrate; said interconnect layers interconnecting devices within said macro cells and said standard cells and providing sublevel power lines; d) forming a power level layer over said plurality of interconnect layers; said power level layer comprised of VDD and VSS lines running in parallel over said power line area between said macro cells; said power level layer comprised of a pin to connect to said buffer cell; said pin located over said power line area; e) forming a signal line over said power level layer over said macro block area; said signal line having contacts to said pin and are connected to said buffer cell; said signal line connected to said driver located in said standard cell area.