Patent ID: 6738889
Filing Date: 2004-05-18
Classification: G06F

Abstract:
An apparatus comprising:(1) at least one processor; (2) a memory coupled to the at least one processor; (3) a first process residing in the memory and executed by the at least one processor; (4) a virtual address space that is addressable by at least one instruction executed by the at least one processor, the virtual address space comprising: (4a) a global address space partition that may be accessed by any process executed by the at least one processor, including the first process; and (4b) a local address space partition that may be accessed only by the first process; an (5) a hardware address translation mechanism coupled to the at least one processor that: (5a) detects whether a virtual address referenced by the at least one instruction accesses the global address space, and if so, maps the virtual address to an internal address sing at least one global address translation criterion, and that maps the internal a dress to a corresponding physical address; and (5b) detects whether a virtual address referenced by the at least one processor accesses the local address space, and if so, maps the virtual address to an internal address sing at least one local address translation criterion, and that maps the internal a dress to a corresponding physical address.