Patent ID: 8407638
Filing Date: 2013-03-26
Classification: G01R,G06F

Abstract:
1. A method of designing a circuit, comprising: providing a computer model of an original circuit design including a latch; providing a computer model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of N latches associated with the latch of the original circuit design, wherein N is an odd number, and voting logic having inputs coupled to respective outputs of latches in the latch set; during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function; determining subsets of the set of latches, wherein each subset is a unique group of M latches, where M is the integer value of N/2 and injecting an error includes injecting an error on each latch in the subset for each of the subsets; and for each of the subsets, after injecting an error, testing the voting logic by determining a logical function at a point of the modified version of the original circuit that is downstream from the voting logic and based on the output of the voting logic.