Patent ID: 6400219
Filing Date: 2002-06-04
Classification: H03F

Abstract:
A high-speed differential offset comparator circuit, providing a comparator function at a predetermined offset voltage, comprising:a substantially zero offset comparator circuit having a first and a second differential input; and a first pre-amplifier circuit and a second pre-amplifier circuit having an output coupled to said first and said second differential input, respectively, of said substantially zero offset comparator circuit, capable of providing a controllable offset to said circuit, wherein said first and second pre-amplifier circuits each comprise a first MOS transistor and a second MOS transistor connected in series to form a first composite transistor having an effective source, gate and drain, said first MOS transistor receiving an input of said differential offset comparator circuit at a gate thereof and said second MOS transistor receiving a control voltage corresponding to an offset control voltage at a gate thereof, said offset control voltage controlling the value of said predetermined offset voltage, wherein said first and second pre-amplifier circuits each further comprise a diode connected MOS transistor connected to the effective drain of said first composite transistor and in series therewith between the terminals of a voltage source, wherein the output of said pre-amplifier circuit comprises the common connection node of said diode connected MOS transistor and said first composite transistor, wherein said first and second pre-amplifier circuits each further comprise compensation circuitry functioning to cancel dependency of current through said first composite transistor on temperature and process variations, and wherein said compensation circuitry comprises a third MOS transistor and a fourth MOS transistor connected in series to form a second composite transistor, said third MOS transistor receiving said offset control voltage at a gate thereof and said fourth MOS transistor providing at a gate thereof said control voltage to said gate of said second MOS transistor.