Patent ID: 8809932
Filing Date: 2014-08-19
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor substrate having projecting portions; a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions; a floating gate structure disposed over the tunnel insulation layer, an upper portion of the floating gate structure being wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure having a width less than a width of the tunnel insulating layer; first insulation layer portions formed in the semiconductor substrate and projecting from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions; a dielectric layer formed over the first insulation layer portions and the floating gate structure; and a control gate formed over the dielectric layer, wherein the upper portion of the floating gate structure is formed of a different material than the lower portion of the floating gate structure.