Patent ID: 7710808
Filing Date: 2010-05-04
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first block and a second block adjacent to each other in a column direction, each block including a first memory cell array and a second memory cell array adjacent to each other in the column direction, and each including a plurality of memory cells arranged in a matrix, a plurality of local bit lines provided in each memory cell array, and configured to select a column of the memory cell array, and a local sense amplifier shared by the first memory cell array and the second memory cell array, and configured to sense data transferred from a memory cell to a local bit line; a plurality of global bit lines shared by the first block and the second block, and configured to receive data transferred from the local sense amplifier; a global sense amplifier adjacent to the second block in the column direction, and configured to sense data transferred to the global bit lines; a first replica cell group and a second replica cell group respectively provided in the first block and the second block, and each including a plurality of replica cells; a first replica bit line and a second replica bit line respectively connected to the first replica cell group and the second replica cell group; an activation circuit connected to each replica bit line, and configured to activate the local sense amplifier on the basis of a potential of the replica bit line; an edge cell group surrounding the first block and the second block, and configured to store no data; and a contact region surrounding the edge cell group, and having contacts which supply power to a well region of transistors forming the memory cells.