Patent ID: 8745111
Filing Date: 2014-06-03
Classification: G06F,H03M

Abstract:
1. A logic for converting floating point formats having different precisions, the logic comprising: an addend generator logic to generate an addend in a first floating point format from a first number of the first floating point format, the first floating point format having a first precision, wherein the first number is represented via a plurality of bits, wherein the bits represent the first number based on the first floating point format, wherein the bits represent a first integer based on an unsigned integer format, the bits include a signed portion, an exponent portion and a mantissa portion for the first floating point format, the signed portion of the bits representing a second integer based on the unsigned integer format, the exponent portion of the bits representing a third integer based on the unsigned integer format, the mantissa portion of the bits representing a fourth integer based on the unsigned integer format, the first integer being equal to an arithmetic sum of the second integer, the third integer and the fourth integer, wherein the addend corresponds to a fifth integer based on the unsigned integer format, and wherein the fifth integer corresponds to a result of arithmetic operations on a representation of the third integer based on the unsigned format, the result being independent of the fourth integer; and an adder logic to perform a floating point add operation on the first number and the addend, the floating add operation to provide a sum in the first floating point format, the adder logic including a rounding scheme of the first precision, wherein the sum includes a second number of a second floating point format having a second precision, the second number representing a conversion of the first number from the first floating point format to the second floating point format.