Patent ID: 7802023
Filing Date: 2010-09-21
Classification: G06F

Abstract:
1. A multiprocessor, comprising: a plurality of processors operatively coupled to one another over one or more communication busses; and a configurable interface circuit operating in a first mode and a second mode in response to one or more control signals, where: (i) the first mode provides a coherent symmetric interface interconnecting the multiprocessor and one or more external devices, and maintains cache coherency between one or more memories of the multiprocessor and one or more memories of the one or more external devices; and (ii) the second mode provides a non-coherent interface interconnecting the multiprocessor and one or more external devices, and provides at least some memory protection of the one or more memories of the multiprocessor, wherein the configurable interface circuit includes a logical layer, a transport layer, and a physical layer, the logical layer defines coherency rules for operating in the first mode, and ordering rules for operating in the second mode, the transport layer defines command and data packet configurations for transmission between the multiprocessor and the one or more external devices, and the physical layer defines electrical characteristics and timing of memory access commands, memory snoop requests, and data transfers between the multiprocessor and the one or more external devices.