Patent ID: 7541276
Filing Date: 2009-06-02
Classification: H01L

Abstract:
1. A method for forming an interconnection structure, comprising: forming an etch stop layer on a semiconductor substrate that has a lower conductive layer formed thereon; forming an ILD (interlayer dielectric) layer on the etch stop layer; forming a capping layer on the ILD layer; forming a via hole through the capping layer and the ILD layer to expose a portion of the etch stop layer, the via hole being aligned with a portion of the lower conductive layer; removing the exposed portion of the etch stop layer to expose a portion of the lower conductive layer; forming a via capping layer on the exposed portion of the lower conductive layer; depositing a sacrificial material layer to fill the via hole with sacrificial material; forming a trench aligned with the via hole by etching the sacrificial material layer, the capping layer and ILD layer; removing sacrificial material remaining in the via hole to expose the via capping layer; forming an interconnection by filling the trench and via hole with a conductive material, wherein forming the interconnection comprises: planarizing the conductive material down to the surface of the capping layer.