Patent ID: 6255022
Filing Date: 2001-07-03
Classification: G03F

Abstract:
A method of fabricating a bi-layer photoresist mask having uniform critical dimension in the fabrication of an integrated circuit comprising:providing a layer to be etched on a semiconductor substrate wherein the surface of said layer has an uneven topography;coating said layer to be etched with a first photoresist layer wherein said first photoresist layer is planarized;baking said first photoresist layer;coating said first photoresist layer with a second silicon-containing photoresist layer;baking said second silicon-containing photoresist layer;exposing portions of said second silicon-containing photoresist layer not covered by a mask to actinic light;first developing away said exposed portions of said second silicon-containing photoresist layer;second developing away portions of said first photoresist layer not covered by said second silicon-containing photoresist layer remaining wherein sufficient SO.sub.2 gas is included in said second developing to reduce microloading to form said bi-layer photoresist mask comprising said first photoresist layer and said second silicon-containing photoresist layer remaining; andthereafter ashing said bi-layer photoresist mask to smooth sidewall edges of said bi-layer photoresist mask to complete fabrication of said bi-layer photoresist mask.