Patent ID: 7124383
Filing Date: 2006-10-17
Classification: G06F

Abstract:
1. A method of checking a circuit design including a plurality of flip flops adapted to hold a plurality of values and a plurality of combinational elements, comprising: accessing a plurality of one or more properties of the circuit design, wherein each property of the plurality of one or more properties describes behavior of one or more signals in at least part of the circuit design; and modifying at least a first coverage metric of at least one property of the plurality of one or more properties of the circuit design, based on at least: initially attempting formal verification and then attempting nonformal verification; wherein formal verification at least checks behavior defined in the at least one property over all states possible during operation of the circuit design, the operation starting from one or more initial states of the circuit design, and each state of the all states is characterized by the plurality of values held in the plurality of flip-flops of the circuit design; and wherein nonformal verification checks at least the behavior defined in the at least one property over a subset of the all states possible during operation of the circuit design.