Patent ID: 8563390
Filing Date: 2013-10-22
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a well region, doped with a first-type dopant, in a semiconductor substrate; defining a discharge active portion and a plurality of electrode active portions by forming a device isolation pattern in the well region; forming a capacitor-dielectric layer on each of the electrode active portions; covering the electrode active portions with a plurality of capping electrodes on the capacitor-dielectric layer; forming a counter doped region, doped with a second-type dopant, in the discharge active portion; covering a surface of the semiconductor substrate with a lower interlayer dielectric; forming an electrode contact plug contacting each of the capping electrodes; forming a discharge contact plug contacting the counter doped region; and forming a lower interconnection on the lower interlayer dielectric contacting the electrode contact plug and the discharge contact plug.