Patent ID: 8711889
Filing Date: 2014-04-29
Classification: H04J,H04L

Abstract:
1. A method for adapting the rates of a plurality of asynchronous High Speed Data Link Control (HDLC) channels to a single clock domain for time-division multiplex (TDM) interfacing with an HDLC processor, the method comprising: writing each asynchronous HDLC channel into a corresponding buffer according to an asynchronous clock associated with the asynchronous HDLC channel; and reading the buffers according to a common synchronous clock having a clock rate just above an expected maximum HDLC rate while inserting neutral information as needed to avoid an under-run condition, wherein reading the buffers forms a TDM channel of the plurality of asynchronous HDLC channels for TDM interfacing with the HDLC processor, and wherein inserting the neutral information comprises inserting the neutral information into the TDM channel.