Patent ID: 6218265
Filing Date: 2001-04-17
Classification: H01L

Abstract:
Process for fabricating a semiconductor non-volatile memory device arranged in rows and columns in a matrix structure, comprising a first step of forming active area's parallel lines delimited by field oxide lines by means of a Shallow Trench Isolation process, a second step of forming matrix rows which extend transversally to said active area lines, a third step of forming common source lines alternated between pairs of said matrix rows, said second step comprising a first sub-step of forming first lines in a first polysilicon layer, along said active area lines, a second sub-step of forming an intermediate dielectric layer, a third sub-step of forming second lines in a second polysilicon layer for defining said matrix rows, a fourth sub-step of defining said intermediate dielectric layer, a fifth sub-step of etching said first polysilicon lines, characterized in that said first polysilicon lines have interruptions in regions of said active area lines corresponding to the future common source lines of the matrix, so that, during said fifth etching sub-step, simultaneously with said first polysilicon lines etching, the regions of said active area lines not covered with said first polysilicon lines are etched in order to reduce the difference of level along the common source lines between the regions of said active area lines and the regions of said field oxide lines and consequently to guarantee the electrical continuity of the common source regions of the memory device.