Patent ID: 7593257
Filing Date: 2009-09-22
Classification: G11C

Abstract:
1. A memory, comprising: a memory cell, connected to a bit line and configured to hold data; a bipolar transistor having a base connected to the bit line, wherein the bipolar transistor is configured to read the data by amplifying a current corresponding to the data that appears on the bit line if the data is read; and a resistor having a resistance larger than an interconnection resistance and having a first end connected to a collector of the bipolar transistor, wherein a second end of the resistor is configured to receive a positive potential while a negative potential is applied to an emitter of the bipolar transistor, wherein the collector of the bipolar transistor is further connected to a first end of a first field-effect transistor and wherein a second end of the first field-effect transistor is connected to a sense amplifier.