Patent ID: 6166403
Filing Date: 2000-12-26
Classification: H01L

Abstract:
An integrated circuit comprising:a substrate having a memory area and a non-memory area;a voltage supply conductor;an embedded memory fabricated on the substrate within the memory area;at least one memory routing layer, which includes a highest memory routing layer relative to the substrate, fabricated within the memory area and electrically coupled to the embedded memory;first and second semiconductor cells fabricated on the substrate within the non-memory area;an electromagnetic shield fabricated as an additional, non-routing layer on the integrated circuit over the highest memory routing layer and covering substantially the entire memory area, wherein the electromagnetic shield is electrically coupled to the voltage supply conductor;a logic routing layer, which is the next-higher routing layer on the integrated circuit above the highest memory routing layer and is fabricated over the memory and non-memory areas and over the electromagnetic shield; anda signal wire electrically coupled between the first and second semiconductor cells and having a first conductive segment routed within the logic routing layer and extending over the memory area.