Patent ID: 7724590
Filing Date: 2010-05-25
Classification: G06F,G11C

Abstract:
1. A memory controller including: a first output driver circuit to provide control information to a first signal path; a second output driver circuit to provide, to a second signal path, write data associated with the control information; and a third output driver circuit to provide timing information to a third signal path, wherein a rising edge transition of the timing information indicates that a first symbol of the write data is valid on the second signal path, and a falling edge transition of the timing information indicates that a second symbol of the write data is valid on the second signal path, wherein the timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach a destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path.