Patent ID: 9001090
Filing Date: 2015-04-07
Classification: G02F,G09G

Abstract:
1. A display device, comprising: a data signal line; a plurality of pixel circuits, which are connected to the data signal line and arranged in order; a plurality of gate signal lines arranged in the arrangement order, each of which extends between adjacent ones of the plurality of pixel circuits and is connected to pixel circuits disposed on one side; a gate signal line driving circuit for selecting any one of a forward scanning driving with a forward direction and a backward scanning driving with a reverse direction to the arrangement order as time passes, and outputting a plurality of gate signals that are controlled to an ON voltage sequentially in the selected scanning driving, to the plurality of gate signal lines arranged in the arrangement order; a data signal line driving circuit for selecting one of the plurality of pixel circuits and supplying a display control voltage corresponding to display data of the selected pixel circuit to the data signal line; and a reference voltage line driving circuit for supplying a reference voltage corresponding to each of the plurality of pixel circuits to the each of the plurality of pixel circuits, wherein: the plurality of pixel circuits include a first pixel circuit and a second pixel circuit being disposed adjacent to the first pixel circuit in the arrangement order; the plurality of gate signal lines include a first gate signal line being disposed between the first pixel circuit and the second pixel circuit and being connected to the first pixel circuit, and a second gate signal line being disposed adjacent to the first gate signal line in the arrangement order and being connected to the second pixel circuit; the plurality of gate signals include a first gate signal output to the first gate signal line and a second gate signal output to the second gate signal line; the gate signal output to each of the plurality of gate signal lines is controlled to the ON voltage in a period in which the data signal line driving circuit supplies, to the data signal line, a display control voltage corresponding to display data of a pixel circuit connected to the each of the plurality of gate signal lines, and in a predetermined period prior to the period; each of the plurality of pixel circuits comprises a pixel electrode, a reference electrode to which the reference voltage corresponding to each of the plurality of pixel circuits is supplied, and a switching element which is provided between the data signal line and the pixel electrode and is controlled by the gate signal, wherein the pixel electrode and the reference electrode form a pixel capacitance; the data signal line driving circuit is configured so that, in the forward scanning driving, the display control voltage in the pixel electrode of the second pixel circuit supplied from the data signal line is lowered by a first drop-off voltage due to a change of the second gate signal from the ON voltage to an OFF voltage in accordance with the first gate signal being at the OFF voltage; the data signal line driving circuit is configured so that, in the backward scanning driving, the display control voltage in the pixel electrode of the second pixel circuit supplied from the data signal line is lowered by the first drop-off voltage due to a change of the second gate signal from the ON voltage to the OFF voltage under the first gate signal being at the ON voltage, and is further lowered by a second drop-off voltage due to change of the first gate signal from the ON voltage to the OFF voltage in accordance with the second gate signal being at the OFF voltage; the reference voltage line driving circuit is configured to generate a reference voltage for forward direction to compensate a drop of the first drop-off voltage, to generate a reference voltage for reverse direction to compensate drops of both the first drop-off voltage and the second drop-off voltage, and to select and supply one of the reference voltage for forward direction and the reference voltage for reverse direction to the reference electrode of the each of the plurality of pixel circuits in accordance with whether the gate signal line driving circuit outputs the plurality of gate signals in the one of the forward direction and the reverse direction to the arrangement order.