Patent ID: 6904113
Filing Date: 2005-06-07
Classification: H03L,H04J

Abstract:
1. A method for controlling a phase locked loop during change of synchronisation source, wherein a fixed setting value of the phase difference is originally set for the phase locked loop, the method comprising: changing a synchronisation signal from a first synchronisation to a second synchronisation signal; measuring a phase difference between said second synchronisation signal and a signal formed in a phase lock's oscillator; comparing the measured phase difference to a predetermined limit value; when the comparing step shows that the measured phase difference is greater than the predetermined limit value, changing the phase difference between the second synchronisation signal and the signal formed from the phase lock's oscillator repeating the measuring and comparing steps until the measured phase difference is less than or equal to a said predetermined limit value; and when the comparing step shows that the measured phase difference is less than or equal to said predetermined limit value, setting the measured phase difference as a new setting value for the phase difference for use in the normal adjustment function of the phase locked loop instead of the fixed setting value.