Patent ID: 6972234
Filing Date: 2005-12-06
Classification: H01L

Abstract:
1. A method of fabricating a transistor in an integrated circuit device comprising: providing a semiconductor substrate; implanting a field implant; implanting a well implant; implanting an enhancement implant; forming a gate oxide on the semiconductor substrate; forming a gate on the gate oxide; implanting a first pocket implant into the semiconductor substrate from a first side of the gate; and implanting a second pocket implant into the semiconductor substrate from a second side of the gate; and diffusing the first pocket implant and the second pocket implant laterally in the semiconductor substrate to form a non-uniform dopant concentration throughout a channel region, the non-uniform dopant concentration is configured to increase a punch-through voltage immunity threshold, and wherein the first pocket implant and the second pocket implant are in contact at about the center of the channel region.