Patent ID: 7253754
Filing Date: 2007-08-07
Classification: H03M

Abstract:
1. A serial-to-parallel converter for converting serial input data to parallel output data, wherein the serial input data is synchronized with an input clock, comprising: a frequency divider for dividing the input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock; a serial-to-parallel conversion section for converting the serial input data to n-bit parallel data, where n is an integer greater than 1, which is determined depending on the variable frequency division ratio; a synchronizing section for synchronizing the n-bit parallel data with the single frequency-divided clock to output the parallel output data; and a pattern detector for detecting a predetermined pattern of bits from the n-bit serial input data stored in the data shift circuit, wherein the predetermined pattern detector generates a reset signal when the predetermined pattern of bits has been found, wherein the frequency divider is reset to start its frequency dividing operation when the reset signal is generated, causing the synchronizing section to output the parallel output data including the predetermined pattern of bits.