Patent ID: 6743675
Filing Date: 2004-06-01
Classification: H01L

Abstract:
A manufacturing method comprising:forming at least one field dielectric region to insulate active areas of a semiconductor substrate from each other, wherein the top surface of the field dielectric region is above the top surface of the semiconductor substrate; subjecting the field dielectric region to an etch that includes a horizontal component, to recess at least a portion of at least one sidewall of the field dielectric region away from an active area adjacent to the sidewall; and forming a first conductive layer over the substrate, the first conductive layer having a sidewall adjoining the recessed portion of the sidewall of the field dielectric region, the first conductive layer providing at least a portion of a floating gate for one or more nonvolatile memory cells; wherein the first conductive layer is formed with its top surface being even with the top surface of the field dielectric region; and the method further comprises, after forming the first conductive layer, etching the field dielectric region to lower the top surface of the field dielectric region to a level below the top surface of the first conductive layer.