Patent ID: 6081874
Filing Date: 2000-06-27
Classification: G06F

Abstract:
A computer system, comprising:a node interconnect; andat least a first processing node and a second processing node that are each coupled to said node interconnect, said first and said second processing nodes each including a local interconnect, a processor coupled to said local interconnect, a system memory coupled to said local interconnect, and a node controller interposed between said local interconnect and said node interconnect, wherein the node controller of said first processing node, responsive to receipt of a request transaction on said local interconnect of said first processing node, said request transaction including an address, decodes said address to identify said second processing node as a target and then speculatively transmits said request transaction to said second processing node via said node interconnect prior to receipt of a local combined coherency response for said request transaction, such that communication latency is reduced.