Patent ID: 6351805
Filing Date: 2002-02-26
Classification: G06F

Abstract:
A computer system having memory and a processor, wherein the processor is capable of executing a plurality of instructions, including a first instruction, wherein the processor comprises:a plurality of instruction pipelines; a plurality of result pipelines; and a plurality of reorder buffers, wherein each reorder buffer receives instructions from one instruction pipeline and issues instructions to a second instruction pipeline, wherein each reorder buffer receives data from one result pipeline and issues data to a second result pipeline and wherein each reorder buffer includes: a register file having a plurality of registers, wherein each register includes a data entry and a tag field; and a register alias table having a plurality of register alias table entries, wherein each register alias table entry includes a pipeline field and a register field, wherein the pipeline field shows which instruction pipeline the first instruction was dispatched into and wherein the register field show the register into which the first instruction will write its result.