Patent ID: 9202056
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A processor comprising: an execution core to execute instructions; and first attestation hardware, wherein the first attestation hardware is unshared with the execution core, the first attestation hardware including a state machine to control the first attestation hardware to calculate a first measurement of a first security software module associated with the first processor, compare the first measurement to a second measurement to verify integrity of the first security software module, and send a first attestation message to second attestation hardware in another processor, wherein operation of the state machine, after being started, is independent from the processor's execution of instructions, and wherein the first attestation message is creatable only by the first attestation hardware; a private key configured to encrypt the first attestation message such that the first attestation message can be decrypted only by attestation hardware; and a storage location, writable only by the first attestation hardware, in which to store an indication that the first attestation hardware has received a second attestation message from the second attestation hardware, the second attestation message to indicate that the second attestation hardware has verified integrity of a second security software module associated with the second processor.