Patent ID: 7800158
Filing Date: 2010-09-21
Classification: H01L,Y10S

Abstract:
1. A semiconductor device comprising: a non-volatile memory device formed on a substrate, the non-volatile memory device comprising a stacked gate structure having a floating gate, a control gate, and an insulation layer formed between the floating gate and the control gate; a first selection device formed on the substrate at one side of the non-volatile memory device; a floating junction formed in the substrate between the non-volatile memory device and the first selection device; and a spacer formed on one sidewall of the stacked gate structure in the non-volatile memory device adjacent to a gate of the first selection device, the spacer completely covering the floating junction between the non-volatile memory device and the first selection device and extending toward a sidewall of the gate in the first selection device; wherein the gate of the first selection device is formed of a single-layered conductive layer.