Patent ID: 6482700
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method for fabricating a split gate field effect transistor comprising:providing a semiconductor substrate; forming upon the semiconductor substrate a gate dielectric layer; forming upon the gate dielectric layer a blanket floating gate electrode material layer; forming upon the blanket floating gate electrode material layer a patterned mask layer; etching, while employing the patterned mask layer as an etch mask layer, the blanket floating gate electrode material layer to form a floating gate electrode; etching laterally, at least partially, the patterned mask layer to fully expose an edge of the floating gate electrode; covering covering the floating gate electrode and the edge of the floating gate electrode with an inter-gate electrode dielectric layer; forming upon the inter-gate electrode dielectric layer a control gate electrode at least partially covering the floating gate electrode; and forming into the semiconductor substrate a pair of source/drain regions which define a floating gate electrode channel with respect to the floating gate electrode and an adjoining control gate electrode channel with respect to the control gate electrode.