Patent ID: 7847419
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A semiconductor package comprising: a semiconductor chip module having an upper surface and a lower surface opposing the upper surface, the semiconductor chip module being formed with a plurality of integrally formed semiconductor chips, each semiconductor chip having bonding pads in the upper surface of the semiconductor chip module; a re-distribution layer formed over the semiconductor chip module, the re-distribution layer having a plurality of pad parts and a plurality of connection parts electrically connecting each pad part to the respective bonding pad, wherein the connection parts electrically connect a first bonding pad arranged on a first semiconductor chip to a second bonding pad arranged on a second semiconductor chip such that the connection parts are disposed to extend from the first semiconductor chip to the second semiconductor chip wherein the re-distribution layer is formed over the lower surface of the semiconductor chip module; and a plurality of through electrodes, each through electrodes extending from the upper surface to the lower surface and penetrating the bonding pads, and each through electrode being electrically connected to the penetrated bonding pad.