Patent ID: 6462995
Filing Date: 2002-10-08
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a) a semiconductor substrate; b) a semiconductor memory region disposed in said semiconductor substrate and including: 1) a plurality of semiconductor memory elements; and 2) a redundant semiconductor memory element with which a defective memory element in the semiconductor memory elements is to be replaced; c) a fuse region containing a plurality of fuses configured to store redundancy information according to an address of the defective memory element into or from which data is unable to be written or read; d) a register circuit connected to said fuse region, said register circuit being configured to receive and hold said redundancy information stored in said fuse region based on whether or not a fuse provided in said fuse region is cut and to transmit said redundancy information; and e) a transfer circuit configured to transfer said redundancy information received from said register circuit to said semiconductor memory region serially so that the defective semiconductor memory element is replaced with the redundant semiconductor memory element; wherein each of said fuse region, said register circuit and said transfer circuit is disposed in an end portion or said semiconductor substrate.