Patent ID: 6012133
Filing Date: 2000-01-04
Classification: G06F,G11C

Abstract:
A match-line-to-word line transfer circuit for a translation lookaside buffer (TLB) comprising:a first match line carrying a logic level indicating a first miss or a first hit in the first match line;a second match line carrying a logic level indicating a second miss or a second hit in the second match line;a first word line;a second word line;a first control means for enabling activation of the second word line when the logic level on the first match line indicates the first miss;a second control means for enabling activation of the first word line when the logic level on the second match line indicates the second miss, wherein the first control means maintains the second word line in an inactive state when the logic level on the first match line indicates a hit, and wherein the second control means maintains the first word line in an inactive state when the logic level on the second match line indicates a hit.