Patent ID: 6611948
Filing Date: 2003-08-26
Classification: G06F

Abstract:
A method for modeling circuit environmental sensitivity for a minimal level sensitive timing abstraction model, comprising:extracting a plurality of parameters from a circuit that includes an input port and an output port; creating an echo-circuit that represents the plurality of parameters and models environmental sensitivity on a circuit block, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and is used in standard static timing analysis (STA) tools, wherein the echo-circuit includes a dummy latch node that is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port, and wherein the echo-circuit enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the output port; adding an input delay arc at the input port; adding an output delay arc at the output port; and applying a transparent delay arc to the echo-circuit, whereby the echo-circuit reflects environmental conditions on said circuit block.