Patent ID: 6677198
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A fabricating method of a low-voltage channel write/erase flash memory cell, comprising mainly the steps of:a. ion-implanting a deep P-well in an N-substrate; b. ion-implanting an N-well in said deep P-well; c. ion-implanting a shallow p-type region on the surface of said N-well; d. growing a tunnel oxide on said shallow p-type region and depositing a poly-Si layer; e. etching said tunnel oxide and said poly-Si layer; f. etching out an oxide-nitride-oxide (ONO) film on said etched tunnel oxide and said etched poly-Si layer; g. depositing a poly-Si layer on said oxide-nitride-oxide (ONO) film; h. etching all grown layers and deposited layers on said oxide to form a rectangular stacked layer with exposed regions of said tunnel oxide region at two sides thereof; i. performing oxidation to form a smiling effect oxide between said rectangular stacked layer and the surface of said N-well; j. ion-implanting a deep p-type region at one side of said rectangular stacked layer and in said N-well; and k. ion-implanting a plurality of n-type regions in said N-well and at two sides of said rectangular stacked layer.