Patent ID: 7105901
Filing Date: 2006-09-12
Classification: H01L

Abstract:
1. A semiconductor device comprising: an active area with at least one MOS transistor to be formed therein; an insulation film for defining said active area, said insulation film having a top surface; and a current/leakage prevention portion for preventing current leakage, said active area having a recess in plan configuration, said recess being defined by first, second and third edges, said first and second edges being parallel to each other, with said insulation film positioned therebetween, said third edge being connected to a first end of said first edge and first end of said second edge, said third edge extending in a direction perpendicular to a direction in which said first and second edges extend, said active area having a fourth edge connected to a second end opposite from said first end of said first edge, said fourth edge being parallel to said third edge, said fourth edge extending in a direction opposite from said second edge, and said active area having a fifth edge connected to a second end opposite from said first end of second edge, said fifth edge being parallel to said third edge and said fifth edge extending in a direction opposite from said first edge, said at least one MOS transistor including a first MOS transistor having a first gate electrode, and a second MOS transistor having a second gate electrode, said first gate electrode extending in a direction perpendicular to the direction in which said fourth edge extends, said second gate electrode extending in a direction perpendicular to the direction in which said third edge extends, and said first and second gate electrodes being parallel to one another and having a source/drain disposed therebetween, said current/leakage prevention portion including