Patent ID: 9076536
Filing Date: 2015-07-07
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a plurality of memory cells; a plurality of word lines electrically connected to the memory cells, the word lines including a first word line, a second word line, and a third word line; and a control circuit configured to perform a first operation, a second operation, a third operation, a fourth operation, and a fifth operation, when the nonvolatile semiconductor memory device receives an erase command and a first address and receives a first interruption command during the first operation or the second operation, the first address including a first page address, a second page address, and a third page address, the first page address corresponding to the first word line, the second page address corresponding to the second word line, the third page address corresponding to the third word line, the control circuit being configured to perform the first operation for memory cells electrically connected to at least one of the first word line, the second word line and the third word line, the first operation including an erase operation, the control circuit being configured to perform the second operation for a memory cell electrically connected to the first word line after the first operation, the second operation including a first write operation, the control circuit being configured to perform the third operation after the second operation, the control circuit being configured to perform the fourth operation for a memory cell electrically connected to the second word line after the third operation, the fourth operation including a second write operation, the control circuit being configured to perform the fifth operation for a memory cell electrically connected to the third word line after the fourth operation, the fifth operation including a third write operation.