Patent ID: 6310803
Filing Date: 2001-10-30
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of normal blocks including a plurality of normal memory cells;at least one spare block including a plurality of spare memory cells for replacing and repairing a defective normal memory cell in a corresponding normal block;a selecting circuit responsive to an external address signal for selecting the normal block and the at least one spare block;a spare determining circuit responsive to the external address signal for determining whether or not to carry out said replacing and repairing using the at least one spare block;a plurality of sense amplifier blocks, said plurality of sense amplifier blocks being arranged corresponding to said plurality of normal blocks and the at least one spare block and each operating to read/write data from/to a corresponding normal block or the at least one spare block;a plurality of selection gates, said plurality of selection gates being arranged corresponding to said plurality of normal blocks and the at least one spare block and each coupling a corresponding normal block or the at least one spare block to a corresponding sense amplifier block;a selection gate controlling circuit for controlling opening and closing of said plurality of selection gates to simultaneously couple the selected normal block to said corresponding sense amplifier block and the selected spare block to said corresponding sense amplifier block prior to the determination result of said spare determining circuit; anda controlling circuit for carrying out data reading/writing operations on said selected normal block or said selected spare block according to the determination result of said spare determining circuit.