Patent ID: 9082473
Filing Date: 2015-07-14
Classification: G11C

Abstract:
1. An integrated circuit FRAM (ferroelectric random access memory) system comprising: (a) a FRAM; (b) a digital circuit coupled to the FRAM for controlling read and write operations in the FRAM; (c) a first supply voltage conductor coupled to the digital circuit for applying a first supply voltage to the digital circuit and also coupled to a conductive pin that conducts a second supply voltage and is coupled to an external capacitor so that a DC value of the first supply voltage is substantially equal to a DC value of the second supply voltage; (d) a second supply voltage conductor coupled to the FRAM for applying a third supply voltage to the FRAM; (e) a switch circuit having a first terminal coupled by the second supply voltage conductor to an internal capacitor and a second terminal coupled to the conductive pin so that a DC value of the third supply voltage is substantially equal to the DC value of the second supply voltage when the switch circuit is closed; (f) a power interrupt detection circuit for detecting an interruption of the first supply voltage to produce an interruption signal and turning the switch circuit off and for causing the digital circuit to operate in response to the interruption signal to prevent initiating of new read and write operations and to allow completion of ongoing read and write operations in the FRAM in response to the detecting of the interruption, wherein the internal capacitor maintains the third supply voltage above a predetermined level during the completing of ongoing read and write operations; and (g) delay circuitry for producing a delayed signal for resetting the FRAM after the ongoing read and write operations have been completed.