Patent ID: 8059462
Filing Date: 2011-11-15
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a cell array including a memory string, said memory string including a plurality of memory cells connected in series; a bit line connected to said memory string; a first wire connected to a cell source of said plurality of memory cells; a second wire connected to a cell well line of a memory cell of said plurality of memory cells; a third wire which supplies a power supply voltage to a circuit arranged outside of a region of said cell array; a fourth wire formed in a first direction which is parallel to said bit line within said cell array region; a fifth wire formed in said first direction within said cell array region; and said first wire, said second wire and said third wire being formed in a layer above a layer in which said bit line within said cell array region is formed, said fourth wire and said fifth wire being formed in said layer in which said bit line within said cell array region is formed, and said first wire and said fourth wire being connected and said second wire and said fifth wire being connected.