Patent ID: 6664807
Filing Date: 2003-12-16
Classification: G11C,H03K

Abstract:
A configuration memory array for a programmable logic device comprising:an array of configuration memory cells arranged in a plurality of rows and columns, wherein the configuration memory cells store configuration data values used to configure the programmable logic device; a plurality of data lines, wherein each data line is coupled to a corresponding row of configuration memory cells; a plurality of data line drivers, wherein each data line driver is coupled to a corresponding data line, each data line driver being configured to drive a configuration data value onto the corresponding data line; and a plurality of repeater cells, wherein each repeater cell is located along a corresponding data line, and wherein each of the repeater cells comprises a logic circuit coupled to the corresponding data line, and coupled to receive a write enable signal, the logic circuit being configured to pull the corresponding data line to a first voltage having a first logic level when the write enable signal is asserted and the corresponding data line has a voltage representative of the first logic level.