Patent ID: 8502316
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a semiconductor substrate comprising an active region; a first shallow trench isolation (STI) region adjoining a first side of the active region; a gate electrode of an MOS device over the active region and the first STI region; a source/drain stressor region of the MOS device comprising a portion in the semiconductor substrate and having a vertical side substantially aligned with a vertical side of the gate electrode; a trench in the semiconductor substrate and adjoining a second side of the active region, wherein the trench has a bottom no lower than a bottom of the source/drain stressor region; and an inter-layer dielectric (ILD) extending from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region, wherein the second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.