Patent ID: 6010921
Filing Date: 2000-01-04
Classification: H01L

Abstract:
A method of fabricating a field-effect transistor, comprising:forming a LOCOS oxide restraining film on an SOI layer which is formed on a substrate of a wafer with interposition of a first insulating film between said substrate and said SOI layer;forming an opening in said restraining film in a region corresponding to a channel region;thermally oxidizing said SOI layer using said restraining film having the opening as a mask to form a LOCOS oxide film, and then removing said LOCOS oxide film to thereby provide the SOI layer with a recess defining the channel region;depositing a second insulating film on an entire surface of the wafer and then anisotropically etching said second insulating film to thereby form first side walls on side surfaces defining said opening of said restraining film;exposing a top surface of said SOI layer inside said opening to form a gate insulating film on that top surface, and then forming a polycrystalline silicon film serving as a gate electrode inside said opening, wherein a top surface of said polycrystalline silicon film is at a level not higher than that of a top surface of said restraining film; andremoving said restraining film and said first side walls, and then, implanting ions into said SOI layer using said gate electrode as a mask to thereby form a source region and a drain region.