Patent ID: 7558133
Filing Date: 2009-07-07
Classification: G11C

Abstract:
1. A memory system, comprising: a memory controller having a first group of terminals, a second group of terminals, and a data strobe terminal, the memory controller being operable to output memory command signals and address signals from the terminals in the first group, write data signals from the terminals in the second group, and a write data strobe from the data strobe terminal having transitions that are synchronized to the write data signals, the memory controller being operable to generate at least one transition of the write data strobe immediately prior to generating the transitions that are synchronized to the write data signals, the memory controller further being operable to receive and process read data signals received from the terminals in the second group in synchronism with transitions of a read data strobe received from the data strobe terminal; a memory device having a first group of terminals, a second group of terminals, and a data strobe terminal, the memory device being operable to process memory command signals and address signals received from the terminals in the first group, to store write data corresponding to write data signals received from the terminals in the second group, and to process a write data strobe received from the data strobe terminal, the memory device being operable to output the read data signals from the terminals in the second group in synchronism with the read data strobe received from the data strobe terminal, the memory device further comprising: