Patent ID: 6410859
Filing Date: 2002-06-25
Classification: H01L,H05K,Y10T

Abstract:
An electrical assembly comprising:a substrate comprising a surface and a plurality of electrical connection points on the surface; an interconnect comprising an edge, a second surface and a plurality of conductive traces comprising electrically insulated trenches in the second surface and the edge at least partially filled with a conductive material, the traces substantially co-planar with the second surface and including edge portions in the edge, the interconnect mounted on the edge to the substrate with the edge portions of the conductive traces in electrical communication with the connection points; a conductive material on the edge attaching the interconnect to the surface and electrically connecting the edge portions of the conductive traces to the connection points; a semiconductor die comprising a face and a plurality of contacts on the face, the die mounted face down on the second surface with the contacts bonded to the conductive traces; and a second interconnect and a second die attached to the substrate to form a stacked array in which the interconnect and the second interconnect are in physical contact with and separated by the second die.