Patent ID: 9129935
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A multi-chip package, comprising: at least one integrated circuit; an interposer structure, wherein the at least one integrated circuit is mounted on the interposer structure, and wherein the interposer structure includes a plurality of series-connected through-substrate vias arranged in a non-looping configuration and a shielding through-substrate via that is formed between a pair of adjacent through-substrate vias in the plurality of series-connected through-substrate vias and that reduces inductance of the plurality of series-connected through-substrate vias; a package substrate, wherein the interposer structure is mounted on the package substrate; and decoupling capacitor circuitry on the package substrate, wherein the decoupling capacitor circuitry is connected in series to the plurality of series-connected through-substrate vias.