Patent ID: 9141548
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. A network services processor comprising: a plurality of processors; a coherent shared memory including a cache and a memory, the coherent shared memory shared by the plurality of processors; a free pool allocator configured to maintain pools of pointers to free memory locations; an input/output bridge coupled to the plurality of processors and the cache, the input/output bridge intercepting memory free commands issued by one or more of the processors and destined for the free pool allocator, each memory free command requesting to free one or more portions in the memory, and based on intercepting a memory free command to request to free a selected memory portion, issuing a don't write back command to a cache controller, and forwarding the memory free command to the free pool allocator based on completion of the don't write back command; and the cache controller coupled to the plurality of processors, the cache and the input/output bridge, the cache controller configured to receive the don't write back command from the input/output bridge and to compare an address of the selected memory portion to addresses stored in the cache and, in an event the address of the selected memory portion is replicated in the cache, void a memory update to the selected memory portion by clearing a dirty bit associated with a corresponding modified cache block.