Patent ID: 7664936
Filing Date: 2010-02-16
Classification: G06F

Abstract:
1. An apparatus for scheduling dispatch of instructions among a plurality of threads of execution being concurrently executed in a multithreading processor, the apparatus comprising: an instruction decoder, configured to decode an instruction from each of the plurality of threads and to generate register usage information based thereon, said register usage information specifying source registers of said decoded instruction and specifying a stage of an execution pipeline in which said source registers are needed by said execution pipeline to execute said decoded instruction to avoid stalling; a priority generator, coupled to said instruction decoder, configured to generate a priority for each of said decoded instructions, based on said register usage information and based on state information, wherein said state information indicates a state of instructions currently executing in said execution pipeline, said state information specifying destination registers of said instructions currently executing in said execution pipeline and a number of pipeline stages between said decoded instruction and said instructions currently executing in said execution pipeline, wherein said priority indicates a likelihood said decoded instruction will execute in said execution pipeline without stalling; and selection logic, coupled to said priority generator, for dispatching at least one of said decoded instructions from at least one of the plurality of threads to said execution pipeline, based on a final thread priority of each of the plurality of threads, said final thread priority of each of the plurality of threads comprising said priority of said decoded instructions and a component thread priority of the thread.