Patent ID: 7643367
Filing Date: 2010-01-05
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory banks including a plurality of memory cell transistors respectively, each of the memory cell transistors having a first main electrode, a second main electrode and a control electrode, each of the memory cell transistors being written with a stored value depending on whether a connection is made between the first main electrode thereof and a first voltage line; a plurality of word lines connected to the control electrodes of the memory cell transistors respectively; a plurality of bit lines connected to the second main electrodes of the memory cell transistors in the memory bank respectively; a plurality of global bit lines connected to the bit lines in the memory banks; a plurality of bank selector circuits, each of the bank selector circuits being provided for the memory banks respectively, each of the bank selector circuits being adapted to receive a bank selector signal having any one of a select level and a non-select level, and each of the bank selector circuits electrically connecting the bit lines in the corresponding memory bank with the global bit lines when the bank selector signal assumes the select level, at least one pull-down circuit connected to the global bit lines, the pull-down circuit pulling the global bit lines down to the voltage level of the first voltage line when a first input signal, having any one of a first active level and a first inactive level, inputted thereto assumes the first active level; a data line for selectively outputting voltages of the global bit lines; a plurality of selector circuits connected between the global bit lines and the data lines, each of the selector circuits electrically connecting the corresponding global bit line with the data line according to a select signal inputted thereto; and a least one precharge circuit connected to the data line, the precharge circuit precharging the global bit lines to a predetermined voltage level when a second input signal having any one of a second active level and a second inactive level, inputted thereto assumes the second active level, the predetermined voltage level being different from a voltage level of the first voltage line, wherein the selector circuits comprise a plurality of first selector circuits, a plurality of second selector circuits, and a plurality of third selector circuits; the first selector circuits being connected between the global bit lines and the third selector circuits, each of the first selector circuits electrically connecting the global bit line with the third selector circuit when a first select signal inputted thereto assumes the select level, and electrically isolating the global bit line from the third selector circuit when the first select signal assumes the non-select level; the second selector circuits being connected between the global bit lines which is adjacent to the global bit lines connected with the first selector circuits and the third selector circuits, each of the second selector circuits electrically connecting the global bit line with the third selector circuit when a second select signal inputted thereto assumes the selected level, and electrically isolating the global bit line from the third selector circuit when the second select signal assumes the non-select level; and the third selector circuits being connected between both of the first selector circuit and the second selector circuit and the data line, each of the third selector circuits electrically connecting both of the first selector circuit and the second selector circuit with the data line when a third select signal inputted thereto assumes the select level, and electrically isolating both of the first selector circuit and the second selector circuit from the data line when the third select signal assumes the non-select level.