Patent ID: 6046604
Filing Date: 2000-04-04
Classification: G06F,G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit device, comprising:a first logic gate having a first MOSFET whose source/drain path is between a first node and a first output node;a second logic gate having a second MOSFET whose source/drain path is between a second node and a second output node;a first control circuit connected to receive a control signal, said first control circuit being provided between said first node and a first potential point, whereinsaid first control circuit permits a first current to flow between said first node and a third node in response to said control signal being in a first state,said first control circuit limits the current flowing between said first node and said third node to a current smaller than said first current in response to said control signal being set to a second state different from said first state, anda second control circuit provided between said second node and a second potential point, whereinsaid second control circuit permits a second current to flow between said second node and a fourth node in response to said control signal being in said first state,said second control circuit limits the current flowing in said second logic gate to a current smaller than said second current in response to said control signal being in said second state,a third logic gate having a fifth MOSFET whose source/drain path is between a fifth node and a third output node and a sixth MOSFET whose source/drain path is between a sixth node and said third output node,and a fourth logic gate having a seventh MOSFET whose source/drain path is between a seventh node and a fourth output node and an eighth MOSFET whose source/drain path is between an eighth node and said fourth output node;wherein said first logic gate has a third MOSFET whose source/drain path is between said third node and said first output node;wherein said second logic gate has a fourth MOSFET whose source/drain path is between said fourth node and said second output node;wherein said third node is directly coupled to said second potential point;wherein said fourth node is directly coupled to said first potential point;wherein said fifth node is connected to said first control circuit;wherein said seventh node is connected to said second control circuit;wherein said sixth node is directly coupled to said second potential point;and wherein said eighth node is directly coupled to said first potential point.