Patent ID: 7139788
Filing Date: 2006-11-21
Classification: G06F

Abstract:
1. A multiplication logic circuit for multiplying two n bit binary numbers, the circuit comprising: array generation logic for performing the logical AND operation between each bit in one binary number and each bit in the other binary number to generate an array of logical AND combinations comprising an array of binary values; array reduction logic for reducing the depth of the array to two binary numbers; and addition logic for adding the binary values of the binary numbers; wherein the array reduction logic comprises: first array reduction logic comprising a plurality of binary counters, each for receiving the binary values of all binary numbers in a respective column of the array, and for outputting binary numbers; and second array reduction logic having logic imposing asymmetric delays on inputs to the logic and for receiving the binary numbers output from the parallel counters at the inputs and for outputting said binary numbers to said addition logic.