Patent ID: 7436007
Filing Date: 2008-10-14
Classification: H01L

Abstract:
1. A master slice type semiconductor integrated circuit device comprising: a basic cell formed on a semiconductor substrate, a plurality of grid lines including first to fourth grid lines which extend in a same direction being imagined on the semiconductor substrate, the basic cell having a plurality of terminals arranged along said plurality of grid lines and respectively composed of a metal layer, wherein at least one terminal of said plurality of terminals includes: first and second patterns which are arranged on the semiconductor substrate, the first and second patterns being spaced from each other along the first grid line; third and fourth patterns which are arranged on the semiconductor substrate, the third and fourth patterns being spaced from each other along the second grid line adjacent to the first grid line, and the third and fourth patterns being adjacent to the first and second patterns; and a fifth pattern which is arranged between the first and second grid lines, and is arranged on the semiconductor substrate interconnecting the first, second, third and fourth patterns, a dimension of the fifth pattern in a direction of extension of said plurality of grid lines being set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of said plurality of grid lines to an interval between the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns in the direction of extension of said plurality of grid lines to an interval between the both patterns.