Patent ID: 6552578
Filing Date: 2003-04-22
Classification: G06F,H03K,Y02D

Abstract:
A duty-cycle detector comprising:a clock input; a filter for averaging the clock input over at least one clock period to produce average clock voltage; a first comparator, receiving the average clock voltage from the filter and receiving a first reference voltage, and generating an upper-limit signal when the average clock voltage exceeds the first reference voltage; a second comparator, receiving the average clock voltage from the filter and receiving a second reference voltage, and generating a lower-limit signal when the average clock voltage is below the second reference voltage; and logic that receives the upper-limit signal from the first comparator and the lower-limit signal from the second comparator, that generates a power-down signal when the lower-limit signal or the upper-limit signal is asserted, whereby the power-down signal is generated when the average clock voltage is above an upper limit or below a lower limit.