Patent ID: 8051116
Filing Date: 2011-11-01
Classification: G06F

Abstract:
1. A method for executing an MMX PSADBW instruction by a microprocessor, comprising: generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed differences, determining whether the borrow bit indicates the packed difference is positive or negative; for each of the packed differences, selecting a value in response to said determining, said value comprising the packed difference if the associated borrow bit is positive and a complement of the packed difference if the associated borrow bit is negative; adding said selected values to generate a first sum and a first carry; adding said borrow bits to generate a second sum and a second carry in parallel with said adding said selected values to generate a first sum and a first carry; adding said first and second sums and said first and second carries to generate a result of the instruction; and storing said result in a register of the microprocessor.