Patent ID: 6992922
Filing Date: 2006-01-31
Classification: G11C

Abstract:
1. A cross point memory array comprising: a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other, each conductive array line beign in electrical contact commmunication with a row of bottom memory element electrodes; a second layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer, each conductive array line being in electrical communication with a column of top memory element electrodes; and a plurality of non-ohmlc devices in electrical communication with the memory element electrodes and exhibiting a very high resistance regime for a certain range of voltages and a very low resistance regime for voltages above and below that range, wherein non-destructive voltages across a top memory element electrode and a bottom memory element electrode substantially follow a hysteresis curve that is characterized by a first write threshold voltage that is associated with a first state of conductance and a second write threshold voltage that is associated with a second state of conductance, such that