Patent ID: 6096596
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A method of fabricating a vertically integrated semiconductor structure having an access transistor, comprising the steps of:(a) providing a substrate having an array area doped with an N+ dopant and an area surrounding the array area that is doped with a P- dopant;(b) forming an intermediate oxide layer on the substrate;(c) etching a plurality of trenched areas into the substrate, an area between two adjacent said trenched areas comprising a digit line;(d) depositing an epitaxial layer doped with a P- dopant on the substrate;(e) patterning said epitaxial layer with a photoresist;(f) anisotropically dry-etching said photoresist to leave a plurality of pillar-like word lines;(g) thermally growing a first portion of an insulator oxide on said word lines;(h) depositing on said substrate a polysilicon layer doped in situ with an N- dopant;(i) depositing a second portion of said insulator oxide on said substrate;(j) etching an opening through said first portion and said second portion of the insulator oxide extending to each word line;(k) implanting an N- dopant material through said openings onto the word lines;(l) depositing a third portion of said insulator oxide on said substrate;(m) etching an opening through said third portion of the insulator oxide above each word line;(n) depositing a polysilicon layer on the substrate with in-situ doping of an N+ material;(o) anistropically etching said N+ doped polysilicon layer to form a structure having vertical sidewalls above each said word line, said structure being referred to as a storage node; and(p) forming a capacitor above said storage node.