Patent ID: 8850123
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. An apparatus comprising: a processor configured to generate (i) a plurality of access addresses and (ii) a plurality of program counter values corresponding to said access addresses, wherein said processor is implemented with hardware; a cache configured to present in response to said access addresses (i) a plurality of data words, (ii) a plurality of address information corresponding to said data words and (iii) a hit/miss signal; and a circuit configured to (a) record a plurality of events in a file in response to a plurality of cache misses while in a first mode and (b) initiate a prefetch of a first of said data words in response to reaching a particular one of said program counter values while in a second mode, wherein (A) a first of said events in said file due to a first of said cache misses comprises (i) a first of said program counter values, (ii) a first of said address information and (iii) a first time to transfer said first data word from a memory to said cache, (B) one of said cache or said circuit measures said first time to transfer said first data word from said memory to said cache, (C) said address information identifies where said data words missed in said cache are located in said memory, and (D) said particular program counter value is reached at least said first time before said first program counter value such that said prefetch of said first data word is complete before said first program counter value is reached.