Patent ID: 6098139
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A circuit for enabling writing data units to and reading data units from a FIFO at disparate clock frequencies, comprising:a data unit memory having an input port and an output port;a write control circuit operating at a first clock frequency; anda read control circuit operating at a second clock frequency,wherein said write control circuit comprisesa write count register for maintaining a number of data units written to said memory and not identified as having been read therefrom,a write count to be acknowledged register, in communication with said write count register, for maintaining a number of data units written to said memory but not made available for reading therefrom,a write count ready circuit, in communication with said write count to be acknowledged register and said read control circuit, for issuing an indication to said read control circuit that at least one data unit has been written to said memory and is ready to be read therefrom, anda write count latch register, in communication with said write count to be acknowledged register, said write count ready circuit, and said read control circuit, for maintaining a number of data units written to said memory but not made available for reading therefrom as of issuance of said indication to said read control circuit, andwherein said read control circuit comprisesa read count register, in communication with said write control circuit, for maintaining a number of data units written to said memory and ready to be read therefrom,a read count to be acknowledged register for maintaining a number of data units read from said memory but not made available to said write count register for accounting therein,a read count ready circuit, in communication with said read count to be acknowledged register and said write control circuit, for issuing an indication to said write control circuit that at least one data unit has been read from said memory and can be reflected in said write count register, anda read count latch register, in communication with said read count to be acknowledged register, said read count ready circuit, and said write count circuit, for maintaining a number of data units read from said memory but not reflected in said write count register as of issuance of said indication to said write control circuit.