Patent ID: 8575702
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an active region configured in or over a substrate to include a first conductive-type first deep well and a second conductive-type second deep well that form a junction therebetween; a gate electrode extending over the junction and over a portion of the first conductive-type first deep well and a portion of the second conductive-type second deep well; a gate insulation layer interposed between the gate electrode and the substrate; a second conductive-type source region configured in the first conductive-type first deep well on one side of the gate electrode; a second conductive-type drain region configured in the second conductive-type second deep well on another side of the gate electrode; a first conductive-type first impurity region configured in the first conductive-type first deep well, the first conductive-type first deep well having a greater depth than the first conductive-type first impurity region; a device isolation layer configured over the substrate to define boundaries of the active region; and a first conductive-type pickup region configured in the first conductive-type first impurity region, at least a portion of the device isolation layer disposed between the second conductive-type source region and the first conductive-type pickup region, wherein the first conductive-type first impurity region has a greater depth than the portion of the device isolation layer disposed between the second conductive-type source region and the first conductive-type pick-up region and encompasses the first conductive-type pick-up region, the second conductive-type source region, and the portion of the device isolation layer disposed therebetween in a cross-sectional view, and surrounds both the first conductive-type pick-up region and the second conductive-type source region in a plan view, the first conductive-type first impurity region extending toward the junction in such a manner as to form a first overlap region in which the first conductive-type first impurity region overlaps with a portion of the gate electrode and/or a portion of the second conductive-type source region.