Patent ID: 8304871
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A packaged semiconductor device, comprising: a semiconductor die comprising a substrate having a topside including active circuitry and a bottomside, and at least one backside metal layer on said bottomside of said substrate, wherein said backside metal layer is directly attached to said bottomside of said semiconductor die and an area of said backside metal layer matches an area of said bottomside of said semiconductor die; a package including a molding material having a die pad and a plurality of leads encapsulated within said molding material, wherein said plurality of leads include an exposed portion that includes a bonding portion; wherein said topside of said semiconductor die is attached to said die pad, and wherein said package includes a gap that exposes said backside metal layer along a bottom surface of said package, and bond wires coupling pads on said topside of said semiconductor die to said plurality of leads, wherein said bonding portions, said molding material along said bottom surface of said package, and said backside metal layer are all substantially planar to one another.