Patent ID: 9001479
Filing Date: 2015-04-07
Classification: H01L,H03K

Abstract:
1. An electrostatic discharge (ESD) protection circuit, comprising: a first NMOS transistor coupled to a power line; a second NMOS transistor coupled between the first transistor and a ground; a detection unit, providing a detection signal when an ESD event occurs at the power line; and a trigger unit, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors, wherein the detection unit comprises: a first resistor coupled between the power line and a gate of the first NMOS transistor; a second resistor coupled between the gate of the first NMOS transistor and the ground; a third resistor coupled to the power line; and a diode, having an anode coupled to the ground and a cathode coupled to the third resistor.