Patent ID: 6096632
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A fabrication method of a semiconductor device, comprising the steps of:(a) preparing a first layer having a hole;(b) forming a second layer to cover side walls and a bottom of said hole;said hole being not filled with said second layer to thereby form a gap on said second layer, said gap being located in a central portion of said hole;(c) forming a protection layer on said second layer so that said gap is filled with said protection layer;(d) removing said protection layer and said second layer by a CMP process until said first layer is exposed, thereby selectively leaving said protection layer and said second layer in said hole;said second layer left in said hole serving as a plug;(e) forming a third layer on said second layer to cover said plug; and(f) selectively removing said protection layer left in said gap between said steps (d) and (e).