Patent ID: 8637376
Filing Date: 2014-01-28
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising a capacitor region on which at least a capacitor is formed and a non-capacitor region on which no capacitor is formed, wherein the method comprises: prescribing the capacitor region and the non-capacitor region by forming a capacitor at a first height on a semiconductor substrate of which the surface is substantially flat; covering the non-capacitor region and the capacitor with an interlayer insulating film with a thickness that is greater than the height of the capacitor, the interlayer insulating film comprising first, second and third portions, the first portion being over the non-capacitor region and including a substantially even surface at a second height greater than the first height, a second portion being over the capacitor and including a substantially even surface at a third height greater than the second height, and the third portion intervening between the first and second portions and including a slant surface to interface the substantially even surface of the first portion with the substantially even surface of the second portion; performing a selective etching on the second portion of the interlayer insulating film to leave first and second parts thereof, the first part being over a major part of the capacitor and including a substantially even surface at a fourth height greater than the first height and less than the third height, and the second part being over a remaining part of the capacitor to intervene between the first part and the third portion of the interlayer insulating film and including a substantially even surface at the third height and a side surface interfacing the substantially even surfaces of the first and second parts with each other; and performing a chemical mechanical polishing to remove the third portion and the second part of the interlayer insulating film so that the interlayer insulating film is flattened to provide an insulating layer covering both the non-capacitor region and the capacitor in a substantially even height greater than the first height, wherein the selective etching on the second portion of the interlayer insulating film is performed to make a difference H