Patent ID: 6521981
Filing Date: 2003-02-18
Classification: H01L,Y10T

Abstract:
A semiconductor device comprising:a semiconductor chip having a main surface, and a plurality of external terminals formed on the main surface; an elastic layer provided over the main surface of the semiconductor chip; a wiring substrate provided over the elastic layer and comprising an insulating substrate, a plurality of wirings and a plurality of bump lands; and a plurality of bump electrodes formed on the plurality of bump lands, wherein each of the elastic layer and the insulating substrate has a central portion and a peripheral protrusion, the central portion corresponds to the part thereof overlying the main surface of the semiconductor chip, and the peripheral protrusion corresponds to the peripheral part thereof extended outwardly from the peripheral circumference of the main surface of the semiconductor chip, wherein all of the bump electrodes, electrically connected with the external terminals through the bump lands, are arranged on the central portion of the insulating substrate through the elastic layer, and wherein the plurality of bump lands are electrically connected with the plurality of external terminals through the plurality of wirings.