Patent ID: 7676919
Filing Date: 2010-03-16
Classification: H05K,Y10T

Abstract:
1. A method for forming a via, comprising: forming a first conductive layer on a first side of a circuit board, and forming a second conductive layer on a second side of the circuit board; forming a first hole in the first side of the circuit board, wherein the first hole does not proceed through the entirety of the circuit board; forming a first cylinder on vertical edges of the first hole and in contact with the first conductive layer; forming a second hole in the second side of the circuit board, wherein the second hole does not proceed through the entirety of the circuit board; forming a second cylinder on vertical edges of the first hole, wherein the second cylinder is surrounded by first cylinder and in contact with the second conductive layer; and forming a via in the circuit board, wherein the via is surrounded by the second cylinder.