Patent ID: 6815298
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising the steps of:forming a gate insulating film on a single crystal silicon layer; forming a gate electrode on said gate insulating film; forming a source region and a drain region in said single crystal silicon layer, said source region and said drain region being separated from each other by at least a width of said gate insulating film; forming extension layers of said source region and said drain region, said extension layers extending under said gate insulating film, being shallower than said source region and said drain region, and being of the same conductivity type as said source region and said drain region; forming a cobalt silicide layer having a first compound phase on said source region, said drain region, and said gate electrode; forming an amorphous silicon layer on said first cobalt silicide layers, said amorphous silicon layer being adapted to react with said first cobalt silicide layer; and forming a second cobalt silicide layer having a second compound phase by reacting said amorphous silicon layer and said first cobalt silicide layer at a temperature above which a phase transition reaction occurs between said first cobalt silicide layer and said amorphous silicon layer and below which a phase transition occurs between said first cobalt silicide layer and said single crystal silicon layer, wherein concentrations of cobalt atoms in said source region and said drain region are not higher than 1Ã—1019 cmâˆ’3 after formation of the second cobalt silicide layer.