Patent ID: 9165891
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. An electrostatic discharge protection circuit, comprising: a p-type field effect transistor, having a source coupled to an input/output terminal, a gate coupled to a first node and a drain coupled to a second node; a capacitance device, having a first terminal coupled to a first rail and a second terminal coupled to the first node; an n-type field effect transistor, having a source coupled to the first rail, a gate coupled to the second node and a drain coupled to the first node, wherein the p-type field effect transistor is formed on a first N-well, and the first N-well and the n-type field effect transistor are formed on a substrate; a parasitic silicon controlled rectifier, wherein the parasitic silicon controlled rectifier is constructed by the source of the p-type field effect transistor, the first N-well, the substrate and the source of the n-type field effect transistor, and the parasitic silicon controlled rectifier further comprises a first control terminal coupled to the second node and/or a second control terminal coupled to the first node, wherein the parasitic silicon controlled rectifier is triggered by injecting current into the first control terminal and/or drawing current from the second control terminal.