Patent ID: 6737903
Filing Date: 2004-05-18
Classification: G06F,H01L

Abstract:
A semiconductor integrated circuit device comprising:a group of clock buses of a hierarchical tree structure provided for transmitting a clock signal; a plurality of internal circuits divided into a plurality of blocks, said internal circuits each receiving said clock signal to operate when activated, activation of each of said internal circuits being controlled block by block of said blocks; a plurality of clock distribution networks provided correspondingly to said plurality of blocks respectively, each for transmitting said clock signal to said internal circuits of a corresponding one of said blocks; and a plurality of clock drive control units provided correspondingly to said plurality of blocks respectively, each for supplying said clock signal from said group of clock buses to a corresponding one of said clock distribution networks, each of said plurality of clock drive control units stopping supply of said clock signal when internal circuits of the corresponding block are inactivated; wherein one of said plurality of clock drive control units stops supply of said clock signal to the corresponding clock distribution network irrespective of the activation and inactivation of the internal circuits of the corresponding block, said semiconductor integrated circuit device further comprises a connection switch provided between said corresponding clock distribution network corresponding to said one of said clock drive control units and another clock distribution network, and said connection switch connects said corresponding clock distribution network and said another clock distribution network at least when internal circuits corresponding to said one of said clock drive control units and internal circuits corresponding to said another clock distribution network are all activated.