Patent ID: 6507103
Filing Date: 2003-01-14
Classification: B81B,B81C,G01P,H01L

Abstract:
A semiconductor device comprising;a semiconductor substrate having an upper surface and lower surface, an element formed on said upper surface and a cap for sealing said element so as to form a space over said element, wherein said element is sealed by bonding a laminated rig bonding layer formed around said element provided on said upper surface and an Ni layer formed on said cap, wherein said laminated bonding layer is constituted from a first polysilicon layer doped with an impurity on said upper surface, an insulation layer on said first polysilicon layer and a second polysilicon layer which is not doped with an impurity on said insulation layer, said first polysilicon layer and said second polysilicon layer being contact with each other in a part thereof so that the impurity diffuses through the contact area from the first polysilicon layer into the second polysilicon layer.