Patent ID: 6445048
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A semiconductor configuration, comprising:a substrate having a first conduction type, an edge, and a surface; a transistor configuration disposed at said substrate, said transistor configuration formed from at least one field-effect transistor having at least two doped regions embedded in said substrate and at least one gate electrode; at least two regions having a second conduction type and disposed between said transistor configuration and said substrate edge, said at least two regions extending from said surface of said substrate into said substrate and surrounding said transistor configuration; and at least two insulating trench regions each disposed adjacent one of said at least two regions and between said at least two regions and extending from said surface of said substrate into said substrate, said at least two regions isolated from one another by said at least two insulating trench regions, said at least two trench regions having a depth smaller than said at least two regions.