Patent ID: 7253521
Filing Date: 2007-08-07
Classification: H01L

Abstract:
1. An integrated-memory-circuit assembly comprising: a surface having one or more transistor regions; a first copper-, silver-, or gold-based wiring level having one or more first portions coupled to one or more of the transistor regions, the one or more first portions having a first diffusion-barrier lining and defining a substantially horizontal first plane, with the first plane and the surface bounding at least a portion of a first insulative region; and at least a second copper-, silver-, or gold-based wiring level having one or more second portions electrically coupled and attached to the first wiring level, the one or more second portions having a second diffusion-barrier lining and defining a substantially horizontal second plane which is substantially parallel to the first plane, with the first and second planes bounding at least a portion of a second insulative region that is continuous with the first insulative region, wherein the first and second insulative regions are the same insulative layer, and the first and second diffusion-barrier linings are the same diffusion-barrier lining.