Patent ID: 7680231
Filing Date: 2010-03-16
Classification: H04L

Abstract:
1. An adaptive variable length pulse synchronizer which detects an asynchronous pulse in response to a request signal and which captures corresponding asynchronous data, said adaptive variable length pulse synchronizer comprising: a state keeper circuit which transitions a first signal to a first logic state upon detection of a leading edge of the asynchronous pulse when the request signal is provided and which keeps said first signal in said first logic state while the request signal is provided; an asynchronous pulse edge detection circuit which transitions a second signal to a second logic state in response to a trailing edge of the asynchronous pulse if said first signal is in said first logic state, and which provides a synchronous pulse synchronized with a clock signal when said second signal is in said second logic state; a data synchronization circuit which latches the asynchronous data and provides said synchronous data in response to a leading edge of said synchronous pulse; and a pulse edge synchronization circuit which provides a synchronous ready signal after a leading edge of said synchronous pulse and before a trailing edge of said synchronous pulse.