Patent ID: 6410963
Filing Date: 2002-06-25
Classification: H01L

Abstract:
An electrostatic discharge protection circuit with latch-up prevention function, said protection circuit is electrically coupled with an interface terminal and a devices area, comprising:a well, said well having a first conductivity and being located in a substrate which has a second conductivity; a first doped region, said first doped region being located in said well and electrically coupled with said interface terminal, and said first doped region having said second conductivity and having a dosage which is larger than the dosage of said well; a second doped region, part of said second doped region being located in said well and part of said second doped region being directly located in said substrate, said second doped region being not contacted with said first doped region, and said second doped region having said second conductivity and having a dosage which is larger than the dosage of said well; a gate, said gate being located over said well and between said first doped region and said second doped region; a third doped region, said third doped region being located in said well and electrically coupled with said interface terminal, said third doped region being not contacted with said first doped region, said third doped region and said second doped region being located on opposite sides of said first doped region, and said third doped region having said first conductivity and having a dosage which is larger than the dosage of said well; a fourth doped region, said fourth doped region being directly located in said substrate and being not contacted with said second doped region, said fourth doped region and said first doped region being located on opposite sides of said second doped region, said fourth doped region being electrically coupled with a first ground point, and said fourth doped region having said first conductivity and having a dosage which is larger than the dosage of said substrate; a fifth doped region, said fifth doped region being directly located in said substrate and being not contacted with said fourth doped region, said fifth doped region and said second doped region being located on opposite sides of said fourth doped region, said fifth doped region being electrically coupled with said first ground point, and said fifth doped region having said second conductivity and having a dosage which is larger than the dosage of said substrate; a voltage base point, voltage of said voltage base point being equal to the work voltage of said devices area; and a MOS transistor, drain of said MOS transistor being electrically coupled with said second doped region, source of said MOS transistor being electrically coupled with a second ground point, gate of said MOS transistor being electrically coupled with said voltage base point, and both source and drain of said MOS transistor having said first conductivity.