Patent ID: 7243276
Filing Date: 2007-07-10
Classification: G11C

Abstract:
1. A method, comprising in the order recited: (a) placing a DDR DRAM having a test mode and an operational mode in test mode, said DDR RAM comprising an array of storage cells arranged in rows and columns, storage cells each row addressable by a respective wordline of a set of wordlines and each storage cells in each column addressable by a respective bitline of a set of bitlines; (b) issuing a bank activate command on an occurrence of a rising edge of a first clock signal of a pair of adjacent clock signals of a test clock to select and bring up a wordline selected from said set of wordlines for write of said wordline selected for write; (c) issuing a write with auto-precharge command on an occurrence of a rising edge of a second clock signal of said pair of adjacent clock signals to write a test pattern to storage cells corresponding to said wordline selected for write; (d) repeating steps (b) and (c) until all wordlines of said set of wordlines have been selected and written; (e) issuing a bank activate command on an occurrence of a rising edge of a first clock signal of a subsequent pair of adjacent clock signals to select and bring up a wordline selected from said set of wordlines for read of said wordline selected for read; (f) issuing a read with auto-precharge command on an occurrence of a rising edge of a second clock signal of said subsequent pair of adjacent clock signals to read the stored test pattern from storage cells corresponding to said wordline selected for read; and (g) repeating steps (e) and (f) until all wordlines of said set of wordlines have been selected and read.