Patent ID: 6452830
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A memory configuration, comprising:a plurality of resistive ferroelectric memory cells, each of said resistive ferroelectric memory cells including a selection transistor and a storage capacitor; said selection transistor having a given zone of a first conductivity type; said storage capacitor having a first electrode and a second electrode, said first electrode being supplied with a fixed cell plate voltage, said second electrode being connected to said given zone of said first conductivity type; a semiconductor substrate of a second conductivity type opposite said first conductivity type; said selection transistor being provided in said semiconductor substrate, said storage capacitor being provided on said semiconductor substrate; a MOS transistor having a source, a drain, and a channel, said source and said drain being supplied with the fixed cell plate voltage, said channel having a channel length extending over at least two of said resistive ferroelectric memory cells; a resistor; and said given zone of said first conductivity type being connected, via said resistor, to said channel of said MOS transistor such that said given zone is electrically connected to said first electrode of said storage capacitor via said resistor and said MOS transistor.