Patent ID: 7099222
Filing Date: 2006-08-29
Classification: G11C

Abstract:
1. A semiconductor memory device incorporating a memory core circuit requiring a refresh operation, comprising: a clock signal modifying circuit adapted to receive an external clock signal to generate a modified clock signal which is ineffective from a timing when the control is switched from an active mode to a special mode to a timing when at least one clock pulse time period of said external clock signal has passed after the control is switched from said special mode to an active mode; a forced refresh request signal generating circuit adapted to generate a forced refresh request signal at predetermined time periods and an internal clock signal having the same period as said forced refresh request signal; an all-time refresh request signal generating circuit connected to said clock modifying circuit and adapted to generate an all-time refresh request signal in synchronization with said modified clock signal and said internal clock signal; a multiplexer connected to said forced refresh request signal generating circuit and said all-time refresh request signal generating circuit and adapted to select said forced refresh request signal in said special mode and select said all-time refresh request signal in said actual mode; a refresh pulse generating circuit connected to said multiplexer and adapted to generate a refresh pulse signal in accordance with one of said forced refresh request signal and said all-time refresh request signal selected by said multiplexer and transmit said refresh pulse signal to said memory core circuit; and a read/write pulse generating circuit connected to said modified clock signal generating circuit and adapted to generate a read/write pulse signal in synchronization with said modified clock signal and transmit said read/write pulse signal to said memory core circuit.