Patent ID: 8921909
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A DRAM array, comprising: a plurality of transistors supported by a base; each transistor comprising a gate; a channel proximate the gate; and a pair of source/drain regions on opposing sides of the channel; each transistor comprising a dielectric material between the gate and the channel; capacitors electrically coupled with source/drain regions of the transistors; wherein each channel has a longitudinal axis from one of the source/drain regions to the other, and has a lateral periphery along a cross-section substantially orthogonal to the longitudinal axis; wherein the lateral periphery is a shape having a bottom surface, a top surface, and a pair of side surfaces extending from the bottom surface to the top surface; wherein the dielectric material of each transistor is along and directly against entireties of the top and side surfaces of the shape of the lateral periphery of the channel, and extends under an entirety of the bottom surface but is only directly against a portion of the bottom surface; the dielectric material from one side of the shape contacting the dielectric material from the other side of the shape under the bottom surface; and wherein the gate of each transistor extends conformally along the dielectric material along the top and side surfaces of the shape of the lateral periphery of the channel, and extends under the channel.