Patent ID: 6185133
Filing Date: 2001-02-06
Classification: G11C

Abstract:
A method of erasing a memory cell in a flash memory cell array, which cell includes a control gate, a floating gate, a source, a drain, a channel region between the source and drain, and a gate dielectric situated between the floating gate and the channel and an associated substrate, the method including the steps of:(a) applying a positive erase voltage to either the source or drain of such cell, said erase voltage being generated from a constant current applied to said source or drain so that a voltage is automatically adjusted in a junction of said cell to a value suitable for causing breakdown in such junction; and(b) floating the source or drain of such cell which is not already biased with said positive erase voltage;(c) grounding the substrate;(d) wherein said positive voltage is selected to be sufficient to cause positive charge carriers in the form of hot holes to move into the floating gate to erase the cell.