Patent ID: 6819596
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array in which nonvolatile memory cells are arranged in column and row directions of a matrix, the memory cells being programmable in a write operation and erasable in an erase operation; an address register that stores an address of each of units of the memory cells of the memory cell array, the memory cells or each unit being programmed simultaneously and erased simultaneously; and a control circuit that carries out an erase verify operation to output a â€œpassâ€  or â€œfairâ€  signal according to whether or not all of the memory cells, which are targeted for erase are erased, a write verify operation to output the â€œpassâ€  or â€œfail â€  signal according to whether or not all of the memory cells, which are targeted for write are written, and a data change/non-change operation activated by an input of a first command, for changing data of the address register when either of results of the erase verify and write verify operations is â€œfailâ€ , and for not changing data of the address register when the results are â€œpassâ€ .