Patent ID: 9111060
Filing Date: 2015-08-18
Classification: G06F

Abstract:
1. A method comprising: generating, by one or more computer systems, a hardware description language (HDL) implementation of a circuit design to be implemented on a programmable logic device (PLD); partitioning, by the one or more computer systems, the circuit design into a first portion and a second portion, the first portion including an interface for coupling the first portion and the second portion; generating, by the one or more computer systems, a netlist representation of the second portion; generating, by the one or more computer systems, programming bits for the second portion based on the netlist representation of the second portion; verifying by the one or more computer systems, or providing to a third-party certification body for verification, the programming bits for the second portion; revising, by the one or more computer systems, the first portion after generating the netlist representation of the second portion; generating, by the one or more computer systems, a netlist representation of the revised first portion; and merging, by the one or more computer systems, the netlist representation corresponding to the previously-verified second portion with the netlist representation of the revised first portion.