Patent ID: 7223673
Filing Date: 2007-05-29
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of integrated circuits over a workpiece, each integrated circuit comprising a scribe line at exterior edges thereof and including a plurality of metallization layers formed over and being electrically coupled to the integrated circuit, the plurality of metallization layers comprising a first metallization layer extending a first depth from a top surface of the integrated circuit, and at least one second metallization layer disposed over the first metallization layer and extending a second depth from the top surface of the integrated circuit, wherein each metallization layer is formed in an insulating layer; forming a seal ring around at least one of the integrated circuits; forming a trench around and outside of the at least one of the integrated circuits, wherein the trench is located between the seal ring and the scribe line, and wherein the trench extends at least to the second depth of the at least one second metallization layer; forming a conductive material over at least the trench around the at least one integrated circuit, wherein the conductive material within the trench forms a crack prevention ring; and separating the plurality of integrated circuits at the scribe lines, wherein the crack prevention ring prevents cracking of the insulating layers while separating the plurality of integrated circuits.