Patent ID: 7430144
Filing Date: 2008-09-30
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: one or more memory planes in which a plurality of memory cells are arranged in a row direction and column direction in the form of an array and the memory cells in the same column are connected to a common bit line to form a memory block, and a plurality of the memory blocks are arranged in the column direction; at least two global bit lines extending across the memory planes in the column direction each of which can be connected to one or more of the bit lines of each of the memory blocks through each bit line selection element; and a block selection circuit, at the time of a reading operation, for selecting a selected memory block containing a selected memory cell to be read out by putting one of the bit line selection elements into a conduction state so that the bit line connected to the selected memory cell is connected to the one global bit line and for selecting a memory block other than the selected memory block as a dummy block by putting another one of the bit line selection elements into a conduction state so that one of the bit lines in the other memory block is connected to the other global bit line, wherein when a defective block is contained in one or more of the memory planes, the block selection circuit generates a dummy block address for selecting the dummy block that is different from both of a selected block address of the selected memory block and a defective block address of the defective block by a predetermined logical operation targeted for a specific partial bit of each address bit of the selected block address.