Patent ID: 6717887
Filing Date: 2004-04-06
Classification: G11C,H03L

Abstract:
A semiconductor memory device inputting/outputting data in synchronization with a rise and a fall of an external clock, comprising:a first internal clock generation circuit generating a first internal clock having a constant delay amount with respect to the external clock having a cycle T; a second internal clock generation circuit generating a second internal clock having a constant backward amount with respect to said external clock, in order to synchronize an output timing of the data to outside with said external clock; a frequency divider dividing a frequency of said second internal clock into N (&gE;2) to output cyclically sequenced N frequency division clocks; a first circuit specifying a frequency division clock including a second internal clock pulse having a constant phase difference from a first internal clock pulse corresponding to an external clock pulse indicating a timing of input of a read command, among said N frequency division clocks; and a second circuit selecting the second internal clock pulse corresponding to each external clock pulse after the input of the read command, when said specified frequency division clock is regarded as a starting point.