Patent ID: 6570874
Filing Date: 2003-05-27
Classification: H04B,H04L,H04Q

Abstract:
An ATM switch including S stages (S is an integer and 2<=S), wherein said each stage includes a plurality of basic switches, said ATM switch comprising:MÃ—N (each of M and N is an integer) basic switches per said each stage; and interconnecting means for interconnecting between said stages, wherein said MÃ—N basic switches have N groups, and said interconnecting means connects a jth (j is an integer and 1<=j<=N) output port of said each basic switch belonging to an ith (i is an integer and 1<=i<=N) group at an (sâˆ’1)th (s is an integer and 2<=s<=S) stage to at least one ith input port of said basic switches belonging to a jth group at an sth stage.