Patent ID: 7424019
Filing Date: 2008-09-09
Classification: H04L

Abstract:
1. A packet processor for a network device that alters headers of packets, comprising: an incoming port; a first outgoing port; a control data processor of the packet processor that receives a first control portion of a first packet from said incoming port and that transmits said first control portion to said first outgoing port, wherein said control data processor receives said first control portion independent from a first portion of said first packet; a header altering device that strips, modifies and encapsulates said first portion of said first packet on egress based upon first protocol layering requirements of said first outgoing port, wherein said header altering device includes: a tunnel sync stage that communicates with said stripping stage and that synchronizes tunnel data returned from said first table with said stripped first portion, wherein said header manipulator stage communicates with a second table that stores address resolution protocol (ARP) data.