Patent ID: 7065601
Filing Date: 2006-06-20
Classification: G06F

Abstract:
1. An interface for carrying packets each comprising a plurality of fields between an on-chip communication path connected to at least one on-chip module and off-chip circuitry, said interface comprising; at least one chip-side port comprising a plurality of pins for conveying the fields of the packet in parallel; first and second circuit-side ports, each circuit-side port comprising a set of pins having a lower number than pins of said at least one chip-side port, each of said first and second circuit-side ports providing a unidirectional pathway between said interface and said off-chip circuitry; means for transmitting interrupt signals from said off-chip circuit to said on-chip communication path in a manner such that said interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to said on-chip communication path; and means for conveying power down signals between said off-chip circuit and said on-chip communication path in a manner indistinguishable from power down signals provided between on-chip modules connected to said on-chip communication path.