Patent ID: 6713336
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of fabricating a flash memory device comprising the steps of:forming a first trench having a width including an active region and an isolation region at each side thereof on a predetermined position of a semiconductor substrate; filling up a sacrificial layer in the first trench; patterning the sacrificial layer to expose the isolation regions of the first trench; forming a source region and a drain region by implanting a predetermined conductive type impurity ions into the exposed first trench regions; forming an isolation layer by filling up an insulating layer in the exposed first trench regions; removing the patterned sacrificial layer to form a second trench exposing the active region; forming a tunnel oxide layer and a floating gate sequentially on a surface of the second trench; forming a control gate with a gate insulating layer interposed on the floating gate and the substrate; and forming metal wirings to be in contact with the source and the drain regions, respectively, through the isolation layer on the substrate.