Patent ID: 8423343
Filing Date: 2013-04-16
Classification: G06F

Abstract:
1. A parallelism synchronization method for multi-core instruction-set simulation, comprising: performing a best-case prediction of future sync points for each ISS of multi-core instruction-set simulation by analyzing control flow graphs of a simulated program by a static module; checking whether a next sync point for said each ISS belongs to the same block; if it does, a relative execution time to said next sync point can be calculated; otherwise, traverse its succeeding blocks to make said best-case prediction of said next sync point based-on the shortest path; wherein said best-case prediction of said next sync point for said each ISS is performed by recursively checking said succeeding blocks until reaching a sync point, and comprises a step of pre-calculating best-case delay to said next sync point of said each ISS; estimating best-case execution time of each basic block and/or path for said each ISS of said multi-core instruction-set simulation in said control flow graphs by said static module; and utilizing distributed scheduling said each ISS of said multi-core instruction-set simulation based-on said best-case prediction of said future sync points and said best-case execution time by a dynamic module for shortening the waiting time of said each ISS spent on synchronization.