Patent ID: 7361598
Filing Date: 2008-04-22
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a semiconductor device, comprising the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which particles with a pointed shape are generated is formed; forming an inter-layer insulation layer with a poor step coverage on the metal plate electrode, the particles with the pointed shape in the cell region and a surface of the substrate in the peripheral region wherein the shape of the inter-layer insulation layer is dependent upon the shape of the particles with the pointed shape; etching a portion of the inter-layer insulation layer to expose lateral sides of the particles with the pointed shape; selectively removing the exposed portions of the particles with the pointed shape to separate top portions of the particles with the pointed shape from the inter-layer insulation layer; and planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process for reducing a height difference between the cell region and the peripheral region.