Patent ID: 7018788
Filing Date: 2006-03-28
Classification: G03F

Abstract:
1. A phase shifting lithographic process capable of creating a shrunk fine line pattern on a photoresist layer coated on a semiconductor wafer, the shrunk fine line pattern comprising a first fine line image and a second fine line image connected to the first fine line image, the phase shifting lithographic process comprising: providing a first phase shift mask comprising thereon a first phase shift clear area, a second phase shift clear area situated adjacent to the first phase shift clear area, a first control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, and a first opaque area connected to the first control chrome line section; implementing a first exposure process to expose the photoresist layer to light transmitted from clear areas of the first phase shift mask so as to form the first fine line image corresponding to the first control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, a first unexposed area connected to the first fine line image, and a peripheral unexposed line pattern; providing a second phase shift mask comprising thereon a third phase shift clear area, a fourth phase shift clear area situated adjacent to the third phase shift clear area, a second control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area, and a second opaque area connected to the second control chrome line section for shielding the first fine line image on the photoresist layer; and implementing a second exposure process to expose the photoresist layer to light transmitted from clear areas of the second phase shift mask so as to form the second fine line image corresponding to the second control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area.