Patent ID: 8134238
Filing Date: 2012-03-13
Classification: H01L

Abstract:
1. A semiconductor device having a wafer level chip size package (WL-CSP) structure, comprising: a semiconductor substrate having an integrated circuit formed thereon; a plurality of electrode pads formed on the semiconductor substrate, being intended for input and output of signals between the integrated circuit and an external circuit; at least one rewiring layer which includes rewiring formed adjacent to the plurality of electrode pads so as to be integral with the semiconductor substrate; and a plurality of external electrodes which is formed on the rewiring layer so as to be integral with the semiconductor substrate, the plurality of external electrodes being connected to the plurality of electrode pads via the rewiring, the external electrodes making connection terminals for the external circuit, wherein the plurality of external electrodes are arranged along an edge of the semiconductor substrate, and wherein the plurality of electrode pads are arranged inside the external electrodes, and are each connected to the external electrodes via the rewiring, wherein the integrated circuit includes input/output circuits to be connected to the plurality of electrode pads, the input/output circuits being arranged along the edge along which the external electrodes are arranged such that at least a part of the circuits overlaps an area where the external electrodes are arranged; and a functional circuit arranged near the center of the semiconductor substrate; and the plurality of electrode pads are arranged between the input/output circuits and the functional circuit, wherein the input/output circuits and the external electrodes are isolated from each other by an insulating layer.