Patent ID: 6815737
Filing Date: 2004-11-09
Classification: H01L

Abstract:
An electrical structure, comprising:a semiconductor substrate having an electrically insulative isolation structure therein, wherein a top surface of the substrate and a top surface of the isolation structure are coplanar; a first gate oxide layer on the substrate and in direct mechanical contact with the top surface of the substrate; a first polysilicon layer on the first gate oxide layer and in direct mechanical contact with the first gate oxide layer; a second gate oxide layer on the isolation structure and in direct mechanical contact with the top surface or the isolation structure, wherein the first and second gate oxide layers have a same thickness in a first direction perpendicular to the top surface of the substrate, and wherein the first gate oxide layer has a smaller width than the second gate oxide layer in a second direction parallel to the top surface of the substrate; and a second polysilicon layer on the second gate oxide layer and in direct mechanical contact with the second gate oxide layer, wherein the first polysilicon layer has a smaller thickness than the second polysilicon layer in the first direction, and wherein the first polysilicon layer has a smaller width than the second polysilicon layer in the second direction.