Patent ID: 7218083
Filing Date: 2007-05-15
Classification: G05F

Abstract:
1. A low drop-out (LDO) voltage regulator circuit with enhanced frequency compensation, comprising: an error amplifier for generating an amplified error voltage having a first input terminal for receiving a reference voltage, a second input terminal for receiving a feedback voltage, a third input terminal, and an output terminal; a dynamic bias circuit having an input terminal and an output terminal, the input terminal of the dynamic bias circuit being connected to the output terminal of the error amplifier; an enhanced frequency compensation unit for generating a zero reference value, the enhanced frequency compensation unit being connected between the output terminal of the error amplifier and the ground; a pass device having an input terminal and an output terminal for providing an output voltage to drive a plurality of external components, the input terminal of the pass device being connected to the output terminal of the dynamic bias circuit; and a feedback circuit for scaling down the output voltage, the feedback circuit having a first terminal and a second terminal, the first terminal of the feedback circuit being connected to the output terminal of the pass device, the second terminal of the feedback circuit being connected to the second input terminal of the error amplifier.