Patent ID: 6289488
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the step of parsing one or more task graphs, one or more architectural hints, one or more system/task constraints, and a resource library for the embedded system; and(b) a constructive co-synthesis phase, following the pre-processing phase, comprising the step of allocating one or more groups of one or more tasks in the task graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the task graphs to one or more communication links in the resource library, based on one or more of the architecture hints and performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, wherein an architectural hint provides a priori information that directs allocation of (1) a group of one or more tasks in a task graph towards a particular PE or (2) an edge in a task graph towards a particular communication link.