Patent ID: 6350696
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A method of forming spacers on a semiconductor device, comprising:providing a semiconductor substrate; forming a plurality of gate electrodes on the semiconductor substrate using polysilicon; forming an insulating layer between each of the gate electrodes and the semiconductor substrate, each of the insulating layers comprising an oxide-nitride-oxide material to insulate the gate electrode from the semiconductor substrate; depositing a spacer layer, comprised of oxide or nitride insulating material, over the gate electrodes and the semiconductor substrate to a thickness of approximately 500 Ã¥; anisotropically etching, using a plasma reactive-ion etching process, the spacer layer to leave approximately 400 Ã¥ of the spacer layer covering the semiconductor device; and isotropically etching, using a dilute hydrofluoric or buffered oxide etching process, the portion of the spacer layer to form the spacers on the semiconductor device, the isotropic etching stopping at the nitride material of the insulating layer.