Patent ID: 6815806
Filing Date: 2004-11-09
Classification: H01L,Y10T

Abstract:
A lead frame for use in a chip package, comprising:a. a central region having a first plurality of sides; b. a peripheral edge region having a second plurality of sides positioned in spaced relation around said central region; c. a first set of leads extending from each of said second plurality of sides, each of said first set of leads being partially defined by a first terminal end, first opposing side surfaces each of which extends along a respective first longitudinal axis, and a lower surface that extends in a first plane; d. a second set of leads extending from said second plurality of sides, each of said second set of leads being partially defined by a second terminal end, second opposing side surfaces each of which extends along a respective second longitudinal axis, and an upper surface that extends in a second plane; and e. wherein each of said first set of leads are positioned in staggered non-overlapping relation to corresponding ones of said second set of leads such that said first terminal ends are spaced from said second terminal ends by a first predetermined distance, each of said first longitudinal axes are substantially parallel to and spaced from the adjacent ones of said second longitudinal axes by a second predetermined distance, and said first plane is spaced from said second plane by a third predetermined distance.