Patent ID: 7202516
Filing Date: 2007-04-10
Classification: H01L

Abstract:
1. An integrated circuit including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said NFET and said PFET each having a Channel region, a source region and a drain region, comprising: a PFET gate stack and an NFET gate stack overtying a substrate including a single-crystal semiconductor region, said PFET gate stack and said NFET gate stack each having a gate conductor overlying a gate dielectric formed on a main surface of said single-crystal region; a continuous first film including a first material overlying said source and drain regions of said NFET and said PFET, said first film having a first magnitude stress in a first region where said first film overlies said source and drain regions of one of said NFET or said PFET and said first film having a second magnitude stress lower than said first magnitude stress in a second region where said first film overlies said source and drain regions of the other of said NFET or said PFET, both of said first and second magnitude stresses being non-zero; and a layer including an oxide of said first material contacting said first film in said second region, said layer not contacting said first film in said second region, wherein a portion of said first material of said first film in said second region is consumed in said layer including said oxide.