Patent ID: 9025377
Filing Date: 2015-05-05
Classification: G11C,H01L

Abstract:
1. A method of operating a semiconductor memory device, comprising: storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body, the channel body extending upward from a substrate to intersect a plurality of electrode layers stacked on the substrate; and prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell, wherein: a data erase operation of a normal memory cell other than the read-only memory cell is collectively performed for a block unit multiply including a string including a first selection transistor, a second selection transistor, and the plurality of memory cells connected in series, the first selection transistor being provided in one end portion of the channel body, the second selection transistor being provided in one other end portion of the channel body; and a potential difference between the channel body and an electrode layer of the read-only memory cell is less than a potential difference between the channel body and an electrode layer of the normal memory cell in an erasing operation of a block selected to be erased.