Patent ID: 7492203
Filing Date: 2009-02-17
Classification: H03K

Abstract:
1. A flip-flop comprising: a first PMOS transistor having a source to which a power supply voltage is connected and a gate to which a second clock signal is applied; a second NMOS transistor having a drain to which a drain of the first PMOS transistor is connected and a gate to which a clock pulse signal is applied; a third NMOS transistor having a drain to which a source of the second NMOS transistor is directly connected, a gate to which input data is applied, and a source to which a ground voltage is directly connected; a first latch latching a logic level of a first node between the first PMOS transistor and the second NMOS transistor; a fourth PMOS transistor having a source to which the power supply voltage is connected and a gate to which the first node is connected; a fifth NMOS transistor having a drain to which a drain of the fourth PMOS transistor is connected and a gate to which the second clock signal is connected; a sixth NMOS transistor having a drain to which a source of the fifth NMOS transistor is connected, a gate to which the first node is connected, and a source to which the ground voltage is connected; and a second latch latching a logic level of a second node between the fourth PMOS transistor and the fifth NMOS transistor.