Patent ID: 6971039
Filing Date: 2005-11-29
Classification: G11C

Abstract:
1. A memory configuration, comprising: at least two semiconductor memory modules, including a first semiconductor memory module and a second semiconductor memory module, controlled by internal clock signals, said two semiconductor memory modules output or receive data only on one of a rising edge and a falling edge; an interface device for receiving an external clock signal and the data on a rising edge and a directly succeeding falling edge of the external clock signal or outputying the data between the rising edge and the directly succeeding falling edge of the external clock signal; and a conversion device connected between said interface device and said two semiconductor memory modules to route the data for outputting or reception; the external clock signal being fed to said interface device, and said conversion device generating complementary clock signals, of which one of the complementary clock signals being fed to said first semiconductor memory module and another of the complementary clock signals being fed to said second semiconductor memory module; said conversion device having a command decoder for detecting a command for receiving data, the command for receiving data containing at least two signal pulses present on the rising edge of the external clock signal, and the command for receiving data being forwarded to said first semiconductor memory module in a manner delayed by 3½ clock periods of the external clock signal and being forwarded to said second semiconductor memory module in a manner delayed by three clock periods of the external clock signal; said command decoder detecting a command for outputting data, the command for outputting data containing two signal pulses present on the rising edge of the external clock signal, and the command for outputting data being forwarded to said first semiconductor memory module in a manner delayed at most by one clock cycle of the external clock signal and being forwarded to said second semiconductor memory module in a manner delayed at most by 1½ clock periods of the external clock signal.