Patent ID: 6043684
Filing Date: 2000-03-28
Classification: G11C,H03K

Abstract:
An integrated circuit, comprising:an input buffer configured to receive a first input signal and to produce an output signal in response thereto comprising a first stage having (i) a first NMOS device connected in series with a first PMOS device between a power supply and ground, (ii) a first input line coupled to a gate of said first PMOS device and to a gate of said first NMOS device, and (iii) a first output line coupled to a second stage, said second stage having a first inverter and a second PMOS device coupled between said power supply and said first output line, said second PMOS device gated by an output of said first inverter;a decoder coupled to receive said output signal and configured to produce a first decoded signal in response thereto, said decoder comprising a first pair of PMOS devices coupled in parallel to said power supply and a first pair of NMOS devices coupled in series between said first pair of PMOS devices and ground and having two inputs, each coupled to a gate of a respective one of said first pair of PMOS devices and further having an output coupled between said first pair of PMOS devices and said first pair of NMOS devices;a register coupled to receive a first signal provided by said decoder; anda clock signal path configured to receive a second input signal and to produce a clock signal at said register at a predetermined time with respect to said first signal.