Patent ID: 6473873
Filing Date: 2002-10-29
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory block including a plurality of cells; a test pattern generation circuit for generating at least one test pattern for use in testing the memory block; a first bus line coupled to the memory block and a second bus line for coupling the memory block to the exterior of the semiconductor memory device, the first bus line having a large width than that of the second bus line; a comparison circuit for comparing a test pattern which is read from the memory block against a test pattern which is generated by the test pattern generation circuit; a switching circuit for selectively outputting the test pattern which is generated by the test pattern generation circuit to the memory block via the first bus line in order to be stored in the memory block, and for selectively outputting the test pattern which is generated by the test pattern generation circuit to the comparison circuit via a third bus line in order that the comparison circuit may compare the test pattern stored in the memory block with the test pattern selectively output to the comparison circuit from the test pattern generation circuit.