Patent ID: 8745454
Filing Date: 2014-06-03
Classification: G11C

Abstract:
1. A device comprising: a latch control circuit including first, second and third input nodes, the first and second input nodes receiving first and second commands, respectively, the latch control circuit being configured to produce a latch signal in response to each of the first and second commands when the third input node is at a first logic level, the latch control circuit being configured to produce the latch signal in response to the first command when the third input node is at a second logic level and not to produce the latch signal in response to the second command when the third input node is at the second logic level; a latch circuit configured to capture address information in response to the latch signal; a first circuit unit including a plurality of fourth input nodes receiving the address information from the latch circuit and first and second output nodes, the first output node being coupled to the third input node of the latch control circuit, the first circuit unit being configured to respond the address information to produce an update disable signal, that changes between the first and second logic levels, at the first output node thereof so as to drive the third input node of the latch control circuit, and produce an operation signal at the second output node thereof; and an internal circuit configured to operate in response to the operation signal.