Patent ID: 6522597
Filing Date: 2003-02-18
Classification: G11C

Abstract:
An integrated semiconductor memory device comprising:a plurality of memory cell array blocks, each memory cell array block having an input port and an output port and further comprising; a plurality of memory cells; an input amplifying means for amplifying a received data signal; an output amplifying means for amplifying a stored data signal; a first precharging means which is electrically associated with the input port; and a second precharging means which is electrically associated with the output port; a first plurality of differential conductor pairs, each pair of conductor pairs being associated with a single data bit and being electrically associated with an input port of one of the plurality of memory cell array blocks; a second plurality of differential conductor pairs, each pair being associated with a single data bit and each pair being electrically associated with an output port of one of the plurality of memory cell array blocks; a plurality of isolation components, each one switchably isolating an input port of a first memory cell array block from an output port of a second memory cell array block when the two memory cell array blocks are electrically coupled; and characterized in that the two ports are further isolated from an associated differential conductor pair; and an address decoding means for selectively enabling a memory cell array block in the plurality of memory cell array blocks in response to a unique address signal; wherein at least two of the plurality of memory cell array blocks, which are not connectively coupled to an adjacent memory cell array block, have a port that is directly connected to an input/output conductor.