Patent ID: 9196620
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an insulating interlayer over a substrate in a cell region, the insulating interlayer including contact holes exposing a portion of a surface of the substrate; contact plugs in the contact holes, the contact plugs including a stacked structure of a first barrier metal layer pattern and a first metal layer pattern; second metal layer patterns directly contacting the contact plugs and an upper surface of the insulating interlayer, the second metal layer pattern being a metal material layer, without a barrier metal material, and an area of a bottom region of each of the second metal layer patterns contacting a respective one of the contact plugs is about 30% to about 70% of a total area of the bottom portion of each of the second metal layer patterns, a gate insulating layer on the substrate in a core/peripheral region; and gate electrode structures each including a stacked structure of a lower gate pattern, a second barrier metal layer pattern, a third metal layer pattern, and a fourth metal layer pattern on the gate insulating layer, the first and second barrier metal layer patterns including the same materials.