Patent ID: 8416900
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A method, comprising: providing a coincident edge detector circuit adapted to detect coincident edges of a first clock signal and a first set of derived clock signals, a second clock signal and a second set of derived clock signals and to generate a first coincident edge detected signal and a second coincident edge detected signal when said first clock signal, said second clock signal, all clock signals of said first set of derived clock signals and all clock signals of said second set of derived clock signals have coincident edges; coupling a first clock divider network to said coincident edge detector circuit, said first clock divider network adapted to enable a change of frequency of a clock signal of said first set of derived clock signals in response to said first coincident clock edges detected signal; and coupling a second clock divider network to said coincident edge detector circuit, said second clock divider network adapted to enable a change of frequency of a clock signal of said second set of derived clock signals in response to said second coincident clock edges detected signal.