Patent ID: 6344099
Filing Date: 2002-02-05
Classification: B32B,G02F,Y10S,Y10T

Abstract:
A method of aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display, the method comprising the steps of:placing a coverplate that the tiles are to be attached to on a coverplate support at a coverplate loading station; applying a bonding material for bonding the tiles to the coverplate onto the coverplate at a coverplate bonding material dispensing station, wherein said bonding material is optically clear and wherein said applying is performed such that the entire mating area of said tile and said coverplate is covered with said bonding material arranging a plurality of tiles on a tile support at a tile loading station; connecting the tiles to a tile aligner; arranging the tiles on the coverplate at a tile placement station; aligning the tiles relative to each other and the coverplate by the tile aligner and at least partially onding the tiles to the coverplate at a tile aligning and securing station; applying a bonding material to a surface of the tiles opposite the side that the coverplate is bonded to a tile assembly bonding material dispensing station, wherein said bonding material is optically clear and wherein said applying is performed such that the entire mating area of said tile and said backplate is covered with said bonding material; arranging a backplate on the tiles at a backplate placement station; at least partially bonding the backplate to the tiles at a backplate aligning and securing station; and fully bonding the coverplate and the backplate to the tiles at a full bonding station.