Patent ID: 8779420
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate electrode layer; a gate insulating layer over the gate electrode layer; a first oxide semiconductor layer over the gate electrode layer with the gate insulating layer interposed therebetween; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer over and electrically connected to the second oxide semiconductor layer, wherein the first oxide semiconductor layer comprises indium and zinc, wherein the second oxide semiconductor layer comprises indium and zinc, wherein the second oxide semiconductor layer comprises a first crystalline region, wherein the first crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor layer, wherein the first oxide semiconductor layer comprises a second crystalline region, and wherein the second crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the first oxide semiconductor layer.