Patent ID: 7898515
Filing Date: 2011-03-01
Classification: G09G

Abstract:
1. A liquid crystal display device having a thin film transistor substrate, comprising: a plurality of pixel electrodes to which a data voltage is supplied; a plurality of common electrodes arranged to form horizontal electric fields with the pixel electrodes; a plurality of common wire lines commonly connected to the common electrodes in each horizontal line; a plurality of common voltage drive circuits to supply a first and second common voltage to each of the corresponding common wire lines in response to the clock signals for each frame period; and a controller to generate clock signals which control the common voltage drive circuits that invert an electric potential of the common voltage to be output from each of the common voltage drive circuits for each frame period, wherein the pixel electrodes, the common electrodes, the common wire lines, and the common voltage drive circuits are formed on the thin film transistor substrate, wherein each of the common voltage drive circuits includes a first transistor and a second transistor commonly connected to the common wire line, wherein a gate electrode of the first transistor is connected to a first clock signal line, a drain electrode of the first transistor is connected to a first common voltage line, and a source electrode of the first transistor is connected to the common wire line, and a gate electrode of the second transistor is connected to a second clock signal line, a source electrode of the second transistor is connected to a second common voltage line, and a drain electrode of the second transistor is connected to the common wire line, wherein the plurality of common voltage drive circuits to supply a first and second common voltage to each of the corresponding common wire lines in response to the clock signals for each frame period comprising a first common drive circuit of the plurality of common voltage drive circuits is connected to a first common wire line of the plurality of common wire lines supplies the first common voltage of high potential to the first common wire line of the first horizontal line during an odd-numbered frame period and a negative analog data voltage is supplied by the data drive circuit to the pixel electrodes of a liquid crystal cells included in the first horizontal line and, subsequently the first common drive circuit is supplied the second common voltage of low potential to the first common wire line during an even-numbered frame period and a positive analog data voltage is supplied to the pixel electrodes of the liquid crystal cells included in the first horizontal line, a second common drive circuit of the plurality of common voltage drive circuits is connected to a second common wire line of the plurality of common wire lines supplies the second common voltage of low potential to the second common wire line of the second horizontal line during the odd-numbered frame period and the positive analog data voltage is supplied by the data drive circuit to the pixel electrodes of the liquid crystal cells included in the second horizontal line and, subsequently the second common drive circuit is supplies the second common voltage of high potential to the second common wire line during the even-numbered frame period and the negative analog data voltage is supplied to the pixel electrodes of the liquid crystal cells included in the second horizontal line.