Patent ID: 8949579
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. A method of determining the ineffectiveness of prefetches in a processor, the method comprising: prefetching, by the processor, a plurality of instructions from an instruction source; storing, by the processor, the plurality of instructions in a prefetch cache; selecting, by the processor, a particular instruction of the plurality of instructions for ineffectiveness tracking to categorize the particular instruction into one of a plurality of prefetch effectiveness categories, wherein the selecting includes tagging the particular instruction as a target instruction; initiating, by a processor performance monitoring unit (PMU) in the processor, a timer to measure the time that the particular instruction ages in the prefetch cache before the particular instruction times out in the prefetch cache; testing, by the processor PMU, for ineffectiveness of the prefetch of the particular instruction by accessing the timer to determine if timeout is reached for the particular instruction, thus designating an ineffective prefetched instruction; storing in a database, by the processor, prefetch information that includes a prefetch source address associated with the particular instruction, a prefetch age of the particular instruction and a category of prefetch effectiveness for the particular instruction; and prohibiting, by the processor PMU, the processor from prefetching instructions from the instruction source in an address range associated with ineffective prefetched instructions.