Patent ID: 7622959
Filing Date: 2009-11-24
Classification: H03D

Abstract:
1. A phase comparator, comprising: a first edge detection circuit for detecting a first comparison target signal; a second edge detection circuit for detecting a second comparison target signal; a phase difference signal generation circuit for outputting a signal corresponding to a phase difference between the first and second comparison target signals to a control terminal of a tri-state circuit, based on a detection signal of the first and second detection circuits; and a status management circuit for outputting a signal corresponding to a phase advance or delay of the first and second comparison target signals to an input terminal of the tri-state circuit, wherein the status management circuit outputs a first-state signal either at a high level or at a low level to an input terminal of a tri-state buffer in timing synchronous with the start-up of the first comparison target signal when the phase of the first comparison target signal is ahead of the phase of the second comparison target signal, and when the second comparison target signal changes, the status management circuit continues to output the first-state signal whose state is the same as before the second comparison target signal changes.