Patent ID: 8866309
Filing Date: 2014-10-21
Classification: H01L

Abstract:
1. A chip package structure, comprising: a carrier having a first surface and a second surface opposite to each other; a first chip disposed on the carrier, the first chip having a first active surface and a first back surface, the first back surface facing toward the first surface, and the first active surface having a plurality of first pads and a first insulting layer thereon; a second chip disposed on the first chip and electrically connected to the carrier, the second chip having a second active surface and a second back surface, the second active surface facing toward the first active surface, and the second active surface having a plurality of second pads and a second insulting layer thereon; a plurality of bumps connecting the first pads and the second pads as an electrical conduction of the first chip and the second chip; a first daisy chain circuit disposed on the first insulting layer of the first active surface; a second daisy chain circuit disposed on the second insulting layer of the second active surface; a plurality of hetero thermoelectric device pairs disposed between the first chip and the second chip, and connected in series by the first daisy chain circuit and the second daisy chain circuit, and the hetero thermoelectric device pairs constituted a circuit with an external device; a first heat sink disposed on the second surface of the carrier; a second heat sink disposed on the second back surface of the second chip, wherein the first heat sink and the second heat sink have different heat dissipation efficiencies; and an encapsulant covering the carrier, the first chip and the second chip.