Patent ID: 7106121
Filing Date: 2006-09-12
Classification: H03J,H03K

Abstract:
1. A high frequency switch circuit, comprising: a first FET, a second FET, a third FET, a fourth FET, a first high frequency signal input and output terminal, a second high frequency signal input and output terminal, first through ninth resistors, a first control terminal, and a second control terminal, wherein said first FET has a drain terminal connected to a source terminal of the second FET, a drain terminal of said second FET is connected to a source terminal of said third FET, a drain terminal of said third FET is connected to a source terminal of said fourth FET, a source terminal of said first FET is connected to said first high frequency signal input and output terminal, a drain terminal of said fourth FET is connected to said second high frequency signal input and output terminal, one end of said first resistor is connected to a gate terminal of said first FET, one end of said second resistor is connected to a gate terminal of said second FET, one end of said third resistor is connected to a gate terminal of said third FET, one end of said fourth resistor is connected to a gate terminal of said fourth FET, the other ends of said first through fourth resistors are connected in common to said first control terminal, one end of said fifth resistor is connected to said first high frequency signal input and output terminal, one end of said sixth resistor is connected to a connection point between said first FET and said second FET, one end of said seventh resistor is connected to a connection point between said second FET and said third FET, one end of said eighth resistor is connected to a connection point between said third FET and said fourth FET, one end of said ninth resistor is connected to said second high frequency signal input and output terminal, the other ends of said fifth through ninth resistors are connected in common to said second control terminal, a high level voltage or a low level voltage is selectively applied to said first control terminal, and a predetermined voltage is applied to said second control terminal, and wherein a third control terminal is connected to a voltage input terminal of a step-up circuit; a voltage output terminal of said stepup circuit is connected to said second control terminal; a voltage output terminal of said step-up circuit is connected to a supply voltage terminal of a logic circuit; a fourth control terminal is connected to a signal input terminal of said logic circuit; and a signal output terminal of said logic circuit is connected to said first control terminal.