Patent ID: 8266367
Filing Date: 2012-09-11
Classification: G06F,G11C

Abstract:
1. A two-level flash device comprising: a smart storage switch which comprises: a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped; a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises: NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data.