Patent ID: 6385070
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A content addressable memory system comprising: an array comprising a plurality of cells, the cells organized into at least one rectangular array having rows each comprising a plurality of cells and columns each comprising a plurality of cells, where each column has a compare data line and a compare data complement line, where each row has a match line, and wherein each cell is associated with a row and a column of the array and comprises:at least one memory element for storing a data bit, and comparison circuitry capable of comparing the data bit with compare data, and for driving a signal onto the match line of the associated row when the data bit is not equal to the compare data, the comparison circuitry comprising: a mismatch node, a pre-discharge device coupled to the mismatch node, a rail, and having a gate coupled to a pre-discharge signal, a match line drive device coupled to the match line, a rail, and having a gate coupled to the mismatch node, a first comparison device coupled to an output of the memory element for storing a data bit, the mismatch node, and having a gate coupled to the compare data line of the associated column, and a second comparison device coupled to a second output of the memory element for storing a data bit, the mismatch node, and having a gate coupled to a compare data complement line of the associated column.