Patent ID: 6745373
Filing Date: 2004-06-01
Classification: G01R

Abstract:
A method of inserting a test point into a circuit design, comprising:selecting a test point to be inserted into said circuit design, said circuit design having signal propagation delay limits; determining a driver cell of the test point; selecting from a file, all potential replacement cells for said driver cell, said potential replacement cells having the same function of said driver cell and a test point function; determining a delay of said circuit design with each of said potential replacement cells; adding to an accept list those potential replacement cells where the delay of said circuit design with said potential replacement cell is within said signal propagation delay limits; selecting a replacement cell from said accept list; replacing said driver cell with said replacement cell; and wherein the step of selecting a replacement cell from said accept list comprises selecting the potential replacement cell having a smallest power requirement of all potential replacement cells in said accept list.