Patent ID: 6219797
Filing Date: 2001-04-17
Classification: G06F,H03K

Abstract:
A microprocessor circuit comprising:a microprocessor core;a first oscillator circuit for outputting a first signal, said first oscillator circuit configurable in a powered-up state and a powered-down state;a second oscillator circuit for outputting a second signal;a switch connected to the first oscillator circuit and the second oscillator circuit, the switch for receiving the first signal and the second signal, and the switch further for outputting an operating clock signal to the microprocessor core, wherein the operating clock signal is generated responsive to one of the first signal and the second signal; andmeans for selectively powering-down said first oscillator circuit, thereby reducing power consumption by the first oscillator circuit and placing the first oscillator in the powered-down state;wherein said microprocessor core is configured to operate according to the operating clock signal generated responsive to the second signal when the first oscillator circuit is in the powered-down state.