Patent ID: 6530005
Filing Date: 2003-03-04
Classification: G06F

Abstract:
A circuit arrangement for replacement of executable program instructions and data, said circuit arrangement comprising:a data bus; an address bus; a memory device that is coupled to said address and data buses, and stores executable program instructions and data; a programmable patch-memory module coupled to said address and data buses, wherein said programmable patch-memory module includes a patch address register that stores and provides a patch address value indicative of an address within said memory device, wherein said patch address value is associated with an address within said memory device which is being updated; a comparator that is coupled to said address bus, and compares an address signal value on said address bus with said patch address value, and provides a comparator status signal indicative of whether or not there is a match; a patch data register, that stores a patch data value, and outputs said patch data value onto said data bus when said comparator status signal indicates a match; a central processing unit coupled to said address and data buses to execute said executable program instructions; and a sequence control unit that receives said comparator status signal, and in response to said comparator status signal indicating an address match said sequence control unit provides a wait state output signal, wherein said central processing unit receives said wait state output signal and delays execution of said executable program instructions for a period of time in response to said wait state output signal.