Patent ID: 7932550
Filing Date: 2011-04-26
Classification: H01L

Abstract:
1. An apparatus comprising: a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack disposed over a substrate; a first conductive material between the first and second gate stacks and contacting a first portion of the substrate, the first conductive material having an upper surface; a second conductive material between the second and third gate stacks and contacting a second portion of the substrate, the second conductive material having an upper surface, wherein the second material is coupled to a digit line; a third conductive material between the third and fourth gate stacks and contacting a third portion of the substrate, the third conductive material having an upper surface, wherein the upper surfaces of the first, second, and third conductive materials are at substantially a same horizontal level; and a conductive structure including: a second capacitor structure including: a first conductive segment contacting the third conductive material; a second conductive segment coupled to a first end of the first conductive segment and arranged vertically with respect to the first conductive segment; and a third conductive segment coupled to a second end of the first conductive segment and arranged vertically with respect to the first conductive segment, wherein the first, second, and third conductive materials include doped n-type polysilicon; and a first dielectric disposed over the first, second, and third segments of each of the first and second capacitor structures, the first dielectric contacting a portion of at least one of the first, second, and third conductive materials; an additional conductive material disposed over the first dielectric; and a second dielectric disposed over the additional conductive material.