Patent ID: 7590207
Filing Date: 2009-09-15
Classification: H03L,H04J,H04L

Abstract:
1. A high-speed serial interface for a programmable logic device, said high-speed serial interface comprising a plurality of clock-data recovery modules and at least one clock management unit including a loop circuit for frequency generation, each of said clock-data recovery modules comprising: a clock-data recovery loop; a frequency acquisition loop having a programmable selector for selecting, as an input to said frequency acquisition loop, one of (a) a first signal, and (b) an input of said clock-data recovery loop; and circuitry for programmably enabling and disabling said clock-data recovery loop by applying a control signal, said control signal also controlling said programmable selector to (i) select said first signal when enabling said clock-data recovery loop, and (ii) select said input of said clock-data recovery loop when disabling said clock-data recovery loop; whereby: any one or more of said clock-data recovery modules is programmably configurable as an additional frequency generation unit by applying said control signal to disable said clock-data recovery loop and to select said input of said clock-data recovery loop as an input to said frequency acquisition loop.