Patent ID: 7054206
Filing Date: 2006-05-30
Classification: G11C

Abstract:
1. An arrangement for repairing at least one faulty bit line of a memory, said memory having a plurality of columns, each column having k memory subcolumns, each memory subcolumn having n bit lines, the arrangement comprising: a) a first multiplexer stage, having k multiplexers, each multiplexer having a multiplexer output and n multiplexer inputs connected to n bitlines of a memory subcolumn, the multiplexers of the first multiplexer stage being switched in response to a first address decoding signal; b) a second multiplexer stage having k multiplexers, each multiplexer of the second multiplexer stage having a first multiplexer input connected to an multiplexer output of a multiplexer of the first multiplexer stage associated with a first memory subcolumn, a second multiplexer input connected to a multiplexer output of a multiplexer of the first multiplexer stage belonging associated with a second memory subcolumn, and a multiplexer output, the multiplexers of the second multiplexer stage being switched in response to a fuse data signal; c) a third multiplexer stage including at least one multiplexer having k multiplexer inputs connected to the multiplexer outputs of the multiplexers of the second multiplexer stage and one multiplexer output operably connected to a data bus of the memory, the multiplexer of the third multiplexer stage being switched in response to a second address decoding signal.