Patent ID: 6401148
Filing Date: 2002-06-04
Classification: G06F,G11C

Abstract:
A first in, first out (FIFO) memory system, comprising:a memory having a plurality of locations, each location being addressable during write operations by an associated binary write address received through a write address port, and each location being addressable during read operations by an associated read address received through a read address port; a write address counter having an output port coupled to the write address port of the memory, wherein the write address counter generates binary write addresses in synchronization with a write clock signal; a read address counter having an output port coupled to the read address port of the memory, wherein the read address counter generates binary read addresses in synchronization with a read clock signal; a write-synchronization circuit coupled to the read address counter, the write-synchronization circuit including a first plurality of registers having clock terminals connected to receive the read clock signal, and a second plurality of registers having clock terminals connected to receive the write clock signal; and a subtractor circuit coupled to output terminals of the second plurality of registers of the write-synchronization circuit, and to the output port of the write address counter, wherein the write-synchronization circuit comprises: a first binary-to-Gray-code converter including the first plurality of registers and a first plurality of logic gates having input terminals connected to the output port of the read address counter and output terminals connected to data input terminals of the first plurality of registers; and a second Gray-code-to-binary converter including the second plurality of registers and a second plurality of logic gates having output terminals connected to data input terminals of the second plurality of registers.