Patent ID: 8153490
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A fabrication method of a power semiconductor structure with reduced gate impedance comprising: a) forming a polysilicon gate in a substrate comprising the steps of: forming a gate trench in the substrate; forming a dielectric layer at least on an inner surface in the gate trench; and forming the polysilicon gate in the gate trench; b) implanting dopants into the substrate with the substrate being partially shielded by the polysilicon gate; c) forming an isolation layer covering the polysilicon gate; d) applying a thermal drive-in process to form at least a body surrounding the polysilicon gate, wherein the isolation layer deposited on the polysilicon gate substantially prevents the formation of silicon oxide on the polysilicon gate during the thermal drive-in step; e) removing the isolation layer to expose the polysilicon gate; f) depositing a metal layer on the dielectric layer and the polysilicon gate; and g) forming a self-aligned silicide layer on the polysilicon gate by using a thermal process.