Patent ID: 6636451
Filing Date: 2003-10-21
Classification: G05F

Abstract:
A semiconductor memory device having an internal voltage generator to generate an internal voltage from an external voltage, the internal voltage lower than the external voltage, the internal voltage generator comprising:a PMOS driving transistor having a source connected to the external voltage, a gate connected to a driving signal, and a drain that supplies the internal voltage; a pull-up device connected between the external voltage and the gate of the PMOS driving transistor; and a driving signal generator that generates the driving signal, the driving signal generator comprising a voltage divider to divide the internal voltage so as to generate a control voltage that is substantially uniform, and a pull-down device connected to the gate of the PMOS driving transistor, the pull-down device controlled by the control voltage, wherein the driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level during variations in the external voltage.