Patent ID: 7535898
Filing Date: 2009-05-19
Classification: H04L

Abstract:
1. A distributed memory switch system, comprising: a plurality of ports including a source port and a destination port; a memory pool; an interconnection stage to couple between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be sent from the source port to the destination port via the memory pool, the interconnection stage to split the packet received from the source port into multiple packet portions for storage in the memory pool, wherein the interconnection stage includes a switch stage to couple to the plurality of ports, and a memory switch to couple to the switch stage and to the memory pool; and a processor to couple to the interconnection stage, the processor to assign memory space from the memory pool to the ports, and wherein the processor assigns a larger amount of memory space from the memory pool to higher speed ports and a smaller amount of memory space from the memory pool to lower speed ports.