Patent ID: 7384566
Filing Date: 2008-06-10
Classification: H05K,Y10T

Abstract:
1. A fabrication method for printed circuit boards (PCBs), comprising: providing a substrate having a layout area and a periphery area around the layout area on a surface; forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of straight bridge lines providing electrical connection between the pads, a branch bridge line providing electrical connection between a node in one of the straight bridge lines and one of the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, wherein the bus line surrounds the layout area, each of the straight bridge line is disposed in the layout area and has two ends for being physically connected to the two adjacent pads; forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads; plating a metal layer respectively overlying the pads; forming a plurality of second openings in the solder mask, respectively exposing the straight bridge lines between the pads, the plating line between the bus line and pads, and the node; and removing the exposed straight bridge lines, plating line, and node.