Patent ID: 6028791
Filing Date: 2000-02-22
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell transistor;a bit line connected to one end of the memory cell transistor;a word line connected to a gate of the memory cell transistor;a reference cell transistor;a reference bit line connected to one end of the reference cell transistor;a reference word line connected to a gate of the reference cell transistor;a sense circuit for sensing data stored in the memory cell transistor, the sense circuit includinga first MIS transistor of a first conductivity type having a first terminal connected to a first sense output node, a second terminal electrically connected to a first potential, and a gate coupled to the one end of the memory cell transistor,a second MIS transistor of the first conductivity type having a first terminal connected to a second sense output node, a second terminal electrically connected to the first potential, and a gate coupled to the one end of the reference cell transistor,a third MIS transistor of a second conductivity type having a first terminal connected to the first sense output node, a second terminal electrically connected to a second potential, and a gate coupled to the first sense output node,a fourth MIS transistor of the second conductivity type having a first terminal connected to the second sense output node, a second terminal electrically connected to the second potential, and a gate connected to the first sense output node, anda fifth MIS transistor of the first conductivity type connected between the second sense output node and the gate of the second MIS transistor; anda data readout control circuit for controlling the fifth MIS transistor to conduct for a predetermined interval of time.