Patent ID: 6747857
Filing Date: 2004-06-08
Classification: H01L,H03K

Abstract:
A protection circuit for protecting integrated semiconductor active devices from damage due to ESD voltages applied to an input or output signal pad said circuit comprising:at least one switching circuit string composed of a first and second used NMOS device and a used PMOS device, wherein the gate of said first used NMOS device is connected to a first voltage source and the drain element of said first used NMOS device is connected to said input/output signal pad and to the drain element of said used PMOS device, and the source of said first used NMOS device is connected to the drain element of said second used NMOS device and the gates of said second used NMOS and said used PMOS are connected to an internal circuit and the source of said used second NMOS is connected to a second voltage source, and the source of said used PMOS is connected to said first voltage source; and a discharging means for discharging positive charges accumulated on said gate of said second used NMOS wherein said discharging means are connected to said internal circuit and said switching circuit string to prevent said second used NMOS from turning on from said ESD voltage.