Patent ID: 7319237
Filing Date: 2008-01-15
Classification: G02F,H01L

Abstract:
1. A thin film transistor array substrate comprising: a substrate; a plurality of scan lines disposed on the substrate; a plurality of data lines disposed on the substrate, wherein a plurality of pixel regions are defined on the substrate by the data lines and the scan lines; a plurality of thin film transistors disposed on the pixel regions respectively and driven by the scan lines and the data lines; a plurality of pixel electrodes disposed in the pixel regions respectively, wherein each of the pixel electrodes is electrically connected with the corresponding thin film transistor, a gate insulating layer disposed on the substrate and covering the scan lines and the gates of the thin film transistors; and a patterned leaning layer disposed on the gate insulating layer end correspondingly located under the data lines, wherein the patterned leaning layer comprises a plurality of non-continuous patterns disposed under each of the data lines and exposing portions of the gate insulating layer under the data lines, so as to make a part of each data line directly attach to the gate insulating layer underneath.