Patent ID: 9069042
Filing Date: 2015-06-30
Classification: G01R,G11C

Abstract:
1. A semiconductor device, comprising: a non-logic circuit block coupled to receive an n-bit input and to generate an m-bit output from the n-bit input after a first propagation delay; a shadow logic coupled to the non-logic circuit block for interfacing the non-logic circuit block with external circuitry by generating an n-bit input signal for selective connection to the n-bit input of the non-logic circuit block and by processing an m-bit output signal that may be selectively connected from the m-bit output of the non-logic circuit block to generate a shadow logic output; a test input control circuit for generating a multi-bit input test signal for the shadow logic with each bit of the multi-bit input test signal being independently controllable; a bypass circuit coupled to receive the n-bit input in a shadow logic test mode and to generate an m-bit test output from the n-bit input with each bit of the m-bit test output from the bypass circuit being independently controllable, where the bypass circuit comprises delay matching circuitry for matching the first propagation delay of the non-logic circuit block; and a signal selection circuit coupled to the non-logic circuit block, bypass circuit, and shadow logic for selectively passing the m-bit output to the shadow logic in a first mode and passing the m-bit test output to the shadow logic in the shadow logic test mode.