Patent ID: 6268279
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A manufacturing method of a semiconductor device, comprising:forming a first interlayer insulating film on a semiconductor substrate with a surface area on which a first wiring is formed;forming an etching stopper film made with a material different from a material of said first interlayer insulating film on said first interlayer insulating film;patterning said etching stopper film so as to remove a first portion corresponding to a via hole to be formed in said first interlayer insulating film and a second portion corresponding to an area extending outwardly from a periphery of an area where a second wiring is to be formed;forming a second interlayer insulating film on said etching stopper film;forming a wiring trench corresponding to said second wiring in said second interlayer insulating film by etching said second interlayer insulating film until said patterned etching stopper film is exposedforming said via hole in said first interlayer insulating film by etching said first interlayer insulating film by using said patterned etching stopper film as a mask;removing said etching stopper film; andforming said second wiring connected to said first wiring by laying a conductive material in said via hole and said wiring trench.