Patent ID: 9093421
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A method for implementing a field effect transistor said method comprising: utilizing a replacement metal gate process (RMGP) including a sacrificial gate formed in a central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers above the source and drain on opposite sides of the sacrificial gate; etching and removing the sacrificial gate inside the central metal gate region and exposing a pair of contact areas disposed on opposite sides of the central metal gate region; depositing a first gate metal layer on the dielectric layer; anisotropically etching said first gate metal layer and removing a bottom of said first gate metal layer together with an adjacent dielectric layer below the bottom of said first gate metal layer; depositing a second gate dielectric layer on said first gate metal layer and the substrate; depositing a second metal gate on said second gate dielectric layer filling a remaining area in the central metal gate region; and forming a respective electrical contact at said exposed pair of contact areas disposed on said opposite sides of the central metal gate region for respectively electrically connecting said first metal gate layer and said second metal gate to a respective voltage by depositing an electrical contact layer for electrically connecting said first metal gate layer with the depositing said first gate metal layer on the dielectric layer includes providing a blocking dielectric deposit before performing the anisotropically etching said first metal gate layer; and depositing another electrical contact layer for electrically connecting said second metal gate with the depositing said second metal gate on said second gate dielectric layer.