Patent ID: 7320022
Filing Date: 2008-01-15
Classification: G06F,H04L

Abstract:
1. An apparatus comprising: a cache to store a portion of a data packet in cache blocks; a memory controller to couple to a memory to store data packets in the memory; a register to store a value corresponding to N cache blocks; and a circuit coupled to an interface to receive the data packet from the interface, wherein the circuit generates a control signal, which when asserted, to select first N cache blocks of the received data packet to be cached in the cache with a cache miss, the first N cache blocks, determined by the value in the register, to include at least a portion of a header of the data packet, and the control signal to be deasserted after the first N cache blocks have been cached to inhibit caching of remaining portion of the data packet in the cache, in order to store the remaining portion of the data packet in the memory; the circuit to store all of the received data packet without caching when the control signal is not asserted with a cache miss; the cache to be updated with the data packet with a cache hit regardless of assertion or de-assertion of the control signal; and in which the circuit, the register, the memory controller, and the cache are integrated in a single integrated circuit chip.