Patent ID: 6329855
Filing Date: 2001-12-11
Classification: H03K,H03L

Abstract:
A frequency synthesizer comprising:a voltage controlled oscillator configured to generate an oscillation signal of a frequency corresponding to a control voltage;a divider configured to divide said oscillation signal and to generate a dividing signal;a reference signal oscillator configured to generate a reference signal;a phase comparator configured to obtain a phase error between the reference signal and the dividing signal; anda filter to smooth a comparison result of said phase comparator and generate the control voltage, whereinsaid divider comprises:a prescaler configured to divide a frequency of the oscillation signal by one of a plurality of selectable values based on a switching signal, generating a frequency divided oscillation signal, wherein the prescaler outputs a first prescaler output signal while dividing and outputs a second prescaler output signal when dividing is complete;a variable divider configured to receive and divide a frequency of the frequency divided oscillation signal from the prescaler by a value N, wherein the variable divider outputs a first variable divider output signal while dividing and outputs a second variable divider output signal when dividing is complete;an AND gate having as a first input the frequency divided oscillation signal from the prescaler;a swallow counter configured to receive and divide an output of the AND gate by a value A, wherein the swallow counter outputs a first swallow counter output signal while dividing and outputs a second swallow counter output signal when dividing is complete;an inverter configured to receive the output signal of the swallow counter, wherein the AND gate has as a second input and output of the inverter; anda selector configured to output the switching signal to the prescaler based on the output signal of the swallow counter and a control signal, wherein the selector operates as a buffer or an inverter based on the control signal.