Patent ID: 6715120
Filing Date: 2004-03-30
Classification: H03M

Abstract:
A turbo decoder system, comprising:a plurality M of turbo decoder modules, each for decoding a maximum code word size corresponding to N information bits according to a MAP decoding algorithm; interleave/de-interleave-and-convert-data (IDC) circuitry for receiving input data samples having an (MÂ·N)-bit block-length, the IDC circuitry segmenting the input data samples into M segments, the IDC having predetermined interleaver and de-interleaver definitions therein, each respective segment being provided to a respective turbo decoder module which provides as output a posteriori bit probabilities based on the respective segment of input data samples, the IDC circuitry re-ordering and modifying the input data samples based on the a posteriori bit probabilities, the IDC circuitry providing the re-ordered and modified data samples to the turbo decoder modules for a predetermined number of decoding iterations.