Patent ID: 6661092
Filing Date: 2003-12-09
Classification: G11C,H01L

Abstract:
A memory module comprising:a command/address register device for generating an internal signal according to an external command/address signal, said command/address register device having an output transistor; a plurality of memory devices divided into first and second groups; wiring interconnecting said command/address register device and said memory devices; and a substrate on which said command/address register device and said multiple memory devices are mounted; wherein said wiring includes: a first wiring section extending from said command/address register device to a first branch point; a second wiring section extending from the first branch point to a second branch point; a third wiring section extending from the first branch point to a third branch point; a fourth wiring section which branches out from the second branch point and extends up to the memory devices of said first group; and a fifth wiring section which branches out from the third branch point and extends up to the memory devices of said second group; and said command/address register device includes: an impedance adjuster for adjusting the output impedance of said command/address register device viewed from a junction point between said command/address register device and the first wiring section in such a manner that said output impedance becomes substantially constant within an operating voltage range of the internal signal; and a rise time/fall time adjuster for adjusting rise time and fall time of the internal signal to specific values.