Patent ID: 7482232
Filing Date: 2009-01-27
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of fabricating a nanotube field effect transistor, comprising: providing a back gate layer formed from Si or degenerately doped Si; forming a gate dielectric layer on said back gate layer, wherein said gate dielectric layer is formed from at least one of: SiO forming a local gate electrode and an insulating layer on said gate dielectric layer, wherein said forming said local gate electrode comprises: forming a nanotube on said insulating layer and the gate dielectric layer, where said nanotube has a central region disposed on the insulating layer above the local gate electrode and a first end and a second end disposed on the gate dielectric layer, wherein said nanotube is formed from at least one of: C, Si, GaAs, lnP, and lnGaAs; forming a source electrode on the first end of the nanotube, where the source electrode is spaced from the central region and from the local gate electrode by a first peripheral region of the nanotube; forming a drain electrode on the second end of the nanotube, where the drain electrode is spaced from the central region and from the local gate electrode by a second peripheral region of the nanotube; and selectively doping said nanotube in the first peripheral region and in the second peripheral region using a dopant, where the dopant is one of a group consisting of: Cl