Patent ID: 6768668
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A nonvolatile memory cell comprising:first and second access transistors, each with a gate and first and second terminals; first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to the first terminal of the second access transistor; first and second word lines, the first word line coupled to the gate of the first access transistor and the second word line coupled to the gate of the second access transistor and a first voltage source, the first voltage source having a voltage level lower than the threshold voltage of the second access transistor to ensure the second access transistor is permanently deactivated; a storage transistor having a gate and first and second terminals, the first and second access transistors and the storage transistor are coupled in series such that the first terminal of the storage transistor is coupled to the second terminal of the first access transistor, the gate of the storage transistor is coupled to a first node, and the second terminal of the storage transistor is coupled to the second terminal of the second access transistor to form a second node, wherein the first node is coupled to a second voltage source having a voltage level higher than the threshold voltage of the storage transistor to ensure the storage transistor is activated; and the second node is permanently coupled to either a first voltage level or a second voltage level representing a first or a second state, depending on the desired information to be stored in the memory cell.