Patent ID: 6262916
Filing Date: 2001-07-17
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array having a plurality of memory cells arranged in a form of rows and columns;spare cells each for replacing a defective one of the memory cells of the memory cell array;a sense amplifier for reading information stored in the memory cells of the memory cell array;an input/output buffer for controlling input/output of data;a data input section and a data writing circuit for controlling writing data;a counter circuit for generating signals for successive selection of addresses of the memory cells of the memory cell array at pre-program operation;an address buffer for successively selecting the memory cells in response to the signals generated by the counter circuit;a main decoder for decoding addresses outputted from the address buffer;a defective cell address storing circuit for storing addresses of the defective memory cells of the memory cell array, and for generating a coincidence signal when an address of one of the memory cells selected by the signals generated by the counter circuit is identical to one of the addresses stored in the defective cell address storing circuit;a spare decoder for selecting the spare cells which are to replace the defective cells of the memory cell array;a signal generating circuit for generating a control signal for allowing selection of the spare cells and prohibiting selection of the memory cell array, after the counter circuit generates a signal for selecting a last one of the memory cells of the memory cell array; anda control circuit for controlling the data input section and the data writing circuit in such a manner that programming of data is first performed on the memory cells of the memory cell array and programming of data is thereafter performed on the spare cells, in response to the signal generated by the counter circuit at the pre-program operation, the control signal outputted from the signal generating circuit, and the coincidence signal outputted from the defective cell address storing circuit.