Patent ID: 6756262
Filing Date: 2004-06-29
Classification: H01L

Abstract:
A method of producing a semiconductor integrated circuit device comprising the steps of:(a) forming bit lines and a first layer wring over a MISFET on a main plane of a semiconductor substrate through a first inter-layer insulating film, forming a second inter-layer insulating film and an electrode-forming insulating film, and etching holes in said electrode-forming insulating film; (b) forming a metal or a metal compound on an inside of said holes, and then forming cylindrical first electrodes by forming a metal film or a metal compound film covering the inner wall of said holes; (c) depositing a dielectric capacitance insulating film to cover said first electrodes, and depositing further a ruthenium film by a CVD method and a conductor layer by a sputtering method; (d) patterning said ruthenium film and conductor layers to form second electrodes; and (e) depositing a third inter-layer insulating film covering said second electrodes, and forming a first connection hole reaching said second electrode and a second connection hole reaching said first layer wiring, by etching, wherein said third inter-layer insulating film comprises a silicon oxide film, and wherein said conductor layer and said first layer wiring are comprised of a material having a lower etching rate than said ruthenium film under a condition where the silicon oxide film is etched.