Patent ID: 6778441
Filing Date: 2004-08-17
Classification: G11C,H01L

Abstract:
A DEAPROM memory array, comprising:a number of DEAPROM memory cells, wherein each DEAPROM memory cell includes: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region in the number of pillars and separated therefrom by a gate oxide. a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the DEAPROM memory array; a number of control gate lines coupled to the control gates along a second selected direction in the DEAPROM memory array; a number of bitlines coupled to the second source/drain regions along a third selected direction in the DEAPROM memory array; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.