Patent ID: 6307858
Filing Date: 2001-10-23
Classification: H04L,H04Q

Abstract:
An ATM (Asynchronous Transfer Mode) cell transmission system having an ATM layer device, a data path interface and a plurality of normal PHY (Physical) layer devices whereof each is connected to the ATM layer device by way of the data path interface and returns a HIGH level of a cell transmission allowance signal on condition said each can accept one more whole ATM cell when said each is polled by the ATM layer device through the data path interface; said ATM layer device comprising:a cell buffer for storing ATM cells to be transmitted through the normal PHY layer devices;FIFO memories each provided corresponding to each one of the normal PHY layer devices;an output controller for controlling the cell buffer to output an ATM cell to be transmitted through one of the normal PHY layer devices into one of the FIFO memories corresponding to said one of the normal PHY layer devices, on condition that the ATM cell is stored in the cell buffer and said one of the FIFO memories is not full;a transmission cell selector for selecting one of the FIFO memories as a next sender for transmitting cell data through the data path interface at a next cell transmission cycle following a current cell transmission cycle; anda cell transmission controller forperforming polling of the normal PHY layer devices,designating a selected PHY layer device among the normal PHY layer devices which have returned the HIGH level of the cell transmission allowance signal to the polling and whereof corresponding FIFO memories are not empty,controlling the transmission cell selector to select one of the FIFO memories corresponding to the selected PHY layer device as the next sender, anddesignating the selected PHY layer device at an end of the current transmission cycle as a next receiver of the cell data to be transmitted through the data path interface at the next cell transmission cycle.