Patent ID: 9105661
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a substrate including at least two isolation features; forming a fin extending above the substrate and between the at least two isolation features, wherein the fin has a top surface two opposing sidewalls, and a first width; depositing an amorphous silicon layer over the fin including on the top surface and the two opposing sidewalls; oxidizing the amorphous silicon layer to concurrently form a silicon oxide layer directly on the top surface and the sidewall surfaces of the fin, wherein the fin has the first width after the oxidizing the amorphous silicon layer; and forming a gate electrode on the concurrently formed silicon oxide layer that is disposed on the top and sidewall surfaces of the fin, wherein the fin having the first width forms a channel of the semiconductor device having a gate structure on the fin including the gate electrode and a gate dielectric layer of the formed silicon oxide layer.