Patent ID: 8710879
Filing Date: 2014-04-29
Classification: H03K,H03L

Abstract:
1. A method for multiplying frequency of a clock signal, comprising: providing an initial oscillator signal; via a control signal generation circuit, comparing the initial oscillator signal with a reference signal to generate a first control signal and output the first control signal to a threshold value generation circuit; via the threshold value generation circuit, selecting one of at least one lower threshold value and at least one upper threshold value according to at least the first control signal, and outputting the selected one of the at least one upper and lower threshold values to a digital and logical module; and via the digital and logical module, processing a comparison between the initial oscillator signal and the selected one of the at least one upper and lower threshold values and a comparison between the initial oscillator signal and a low level signal, so as to output an output clock signal, wherein the step of outputting the output clock signal comprises: generating a plurality of logic signals by a plurality of comparators comparing the initial oscillator signal with the selected one of the at least one upper and lower threshold values and comparing the initial oscillator signal with the low level signal; and processing the logic signals by the digital and logical module to output the output clock signal; wherein while one of the logic signals is updated by the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values, at least other one of the logic signals is updated by the comparison between the initial oscillator signal and the low level signal.