Patent ID: 8976572
Filing Date: 2015-03-10
Classification: G11C

Abstract:
1. A method of erasing data stored in a dynamic random access memory (DRAM) array, comprising: (a) setting a wordline of the DRAM array to an active state, thereby causing charge to flow between memory cells coupled to the wordline and respective bitlines according to the data stored in the memory cells, wherein signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines; and (b) while maintaining sense amplifiers connected to the respective bitlines in inactive states in which the sense amplifiers do not amplify the signals to storable signal levels, setting the wordline to an inactive state such that insufficient charge remains in the memory cells coupled to the wordline, thereby erasing the data stored in the memory cells coupled to the wordline, wherein the sense amplifiers are maintained in the inactive states by a control block operating in an erasing mode in a state that at least one predefined event is detected, and the sense amplifiers are operated normally for read, write and refresh operations by the control block operating in a normal mode in a state that none of the at least one predefined event is detected.