Patent ID: 6432816
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of forming a contact hole in a semiconductor device according to a self-aligned contact process comprising, in the following order, the steps of:forming an insulation film pattern on a semiconductor substrate that exposes a device isolation region of the semiconductor substrate; forming a trench by etching the device isolation region using the insulation film pattern as an etching mask; forming an insulation film over the resulting structure; performing a chemical mechanical polishing process to expose the insulation film pattern; etching the insulation layer using a wet etch process to form a device isolation film in the trench, the surface of the device isolation film being lower then that of the semiconductor substrate; forming a protective film over the resultant structure; removing the protective film and the insulation film pattern by a chemical mechanical polishing process using the protective film over the device isolation film as a process endpoint to form a protective film pattern on the surface of the device isolation film; removing the remaining portion of the insulation film pattern; forming a stacked structure comprising a gate insulation film, a gate electrode pattern, and a mask insulation film pattern in the active region of the semiconductor substrate, the stacked structure having an insulation film spacer at its sidewalls; forming a planarization film over the resulting structure; and etching the planarization film to expose the predetermined regions of the active region, thereby forming contact holes.