Patent ID: 6069495
Filing Date: 2000-05-30
Classification: H03K

Abstract:
A logic circuit comprising:a means for dynamically enabling and disabling said logic circuit, said dynamic enable/disable means coupled between a first working potential and a first node, and being responsive to a clock signal having a first and second phase such that in said first phase said logic circuit is enabled and in said second phase said logic circuit is disabled;a latching portion coupled between said first node and first and second differential output nodes;first and second circuit branches each coupled between said first and second differential output nodes, respectively, and a second working potential, said first branch having a first set of input switching devices for receiving a first combination of at least two differential signals, each differential signal including a non-inverted signal and a corresponding complement of said non-inverted signal and for driving said first differential output node with a first output signal having a first logic state which corresponds to the results of a first logical function of said at least two differential signals;said second branch having a second set of input switching devices for receiving a second combination of said at least two differential signals and for driving said second differential output mode with a second output signal having a second logic state which corresponds to the results of a second logical function of said at least two differential signals;wherein said first and said second logical functions are performed on said at least two differential signals and said first and said second output signals are latched to said first and second outputs in the same clock phase.