Patent ID: 7802166
Filing Date: 2010-09-21
Classification: G06F

Abstract:
1. A memory controller, comprising: a first data interface for at least sending data to a memory circuit; a masking circuit; a data providing circuit that is connected with the first data interface and the masking circuit; wherein the data providing circuit is configured to deliver same data to the first data interface and to the masking circuit; wherein the first data interface outputs the data received from the data providing circuit with a predetermined time position relative to a reference time; an error detection circuit connected with the masking circuit; wherein the masking circuit masks parts of the data and delivers at least a non masked part of the data to the error detection circuit; wherein the error detection circuit calculates a first error result using the received non masked data; an analyzing comparing circuit connected with the error detection circuit and configured to receive the first error result; wherein the analyzing circuit is configured to receive a second error result of the memory circuit; wherein the analyzing circuit analyzes the first and second error result to produce correlation information; and a controlling circuit configured to receive the correlation information; the controlling circuit being configured to control the time position of the output of the data by the first data interface relative to the reference time on the basis of the correlation information.