Patent ID: 6298320
Filing Date: 2001-10-02
Classification: G06F

Abstract:
A system for testing an embedded electronic systems having a target processor executing a target program and coupled to target hardware, the target hardware consisting of one of physical target hardware, simulated target hardware, and combinations thereof, the system comprising:a hardware simulator configured to simulate the simulated target hardware;a target monitor coupled to the target processor, the target monitor being operative to determine when the target processor is attempting to communicate with the simulated target hardware and to suspend execution of the target program in response thereto, the target monitor further being operative to convert output signals from the target processor that are directed to the simulated target hardware to corresponding output data and to convert input data from the hardware simulator to corresponding input signals that are applied to the target processor; anda communications interface coupling the target monitor to the hardware simulator, the communications interface being operative to transfer the output data from the target monitor to the hardware simulator and being operative to transfer the input data from the hardware simulator to the target monitor.