Patent ID: 7945805
Filing Date: 2011-05-17
Classification: G06F,Y02D

Abstract:
1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a central processor unit (CPU) with a CPU front side bus (FSB) connected to a channel; a graphics processor unit (GPU) with a GPU FSB connected to the channel; and wherein the CPU FSB comprises a physical layer that receives a parallel data input from a plurality of receiver cores connected to the channel, and wherein the receiver cores comprise: a clock slice block having an analog portion and a digital portion, wherein the analog portion includes a filter that generates an unrotated in-phase clock (I) and Quadrature clock (Q), a phase rotator for creating a rotated I and Q clocks that is controlled by jitter control logic, and a mux for selecting between the unrotated I and Q clocks and the rotated I and Q clocks to output unrotated or rotated I and Q clocks; a plurality of data slice blocks having an analog portion and a digital portion; and a clock distribution block that distributes the selected rotated or unrotated I and Q clocks from the output of the mux to each copy of the data slice blocks.