Patent ID: 6456526
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A nonvolatile memory device comprising:a control circuit; a plurality of memory cells; a plurality of latch circuits; and a plurality of input/output terminals; wherein said control circuit receives a plurality of operation commands from outside said nonvolatile memory device and controls operations according to each operation command, said operation commands comprising a first read command, a second read command and a first write command, wherein in an operation of said first read command, said nonvolatile memory device receives said first read command and a first address information, said control circuit controls reading out read data stored in memory cells corresponding to said address information and outputting said read data to outside via said plurality of input/output terminals, wherein in an operation of said first write command, said nonvolatile memory device receives said first write command, a first address information and write data, said control circuit controls setting said write data to said plurality of data latch circuits, storing said write data in said data latch circuits to memory cells corresponding to said first address information, and verifying whether said write data has been stored in said memory cells or not, and wherein in an operation of said second read command, said nonvolatile memory device receives said second read command, said control circuit controls reading out said write data stored in said plurality of data latch circuits and outputting said reading out data to outside via said plurality of input/output terminals.