Patent ID: 7225375
Filing Date: 2007-05-29
Classification: G01R,G11C

Abstract:
1. A method for detecting degradation in an integrated circuit comprising the steps of: providing a monitor built-in self-test (MBIST) engine; providing MBIST control circuitry and MBIST registers with said MBIST engine; providing at least one monitor element coupled to said MBIST engine; said at least one monitor element being defined by predefined circuit elements in the integrated circuit; providing latch circuitry coupled to said MBIST engine, said latch circuitry used to communicate monitor bits with said MBIST engine; utilizing said MBIST engine for controlling operation of said at least one monitor element, communicating monitor bits, and deterministically stressing predefined circuit element functions of said at least one monitor element; identifying degradation of each of array signal, array timing, and voltage margins utilizing said at least one monitor element; and using said at least one monitor element with said MBIST engine to identify a degraded situation for enabling appropriate preventative action.