Patent ID: 6343019
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A microelectronics package, comprising:a substrate having a first surface, a second surface opposed to the first surface, the first surface having a recess disposed therein, the substrate further having an aperture disposed therethrough and extending from the second surface to a bottom surface of the recess; an inner die having an inner surface, an outer surface opposed to the inner surface, and a set of bonding pads on the inner surface, the inner surface of the inner die being mounted to the bottom surface of the recess, the bonding pads on the inner surface of the inner die being coupled by a plurality of first electrical conductors with a first set of terminals located on the second surface of the substrate, the first electrical conductors passing through the aperture; and an outer die having a first surface coupled directly to the outer surface of the inner die, a second surface substantially opposite from the first surface, and a set of second bonding pads disposed on the second surface, the outer die being stacked on the inner die to form a stack on a same side of the substrate, the plurality of second bonding pads on the second surface of the second die being coupled through a plurality of second electrical conductors with a second set of terminals located on the substrate.