Patent ID: 7009236
Filing Date: 2006-03-07
Classification: H01L

Abstract:
1. A memory device with vertical transistors and trench capacitors, comprising: a substrate, having at least one deep trench therein; a trench capacitor, deposited in a lower position of the deep trench; a conducting structure, deposited on the trench capacitor, comprising a first conductive layer and a second conductive layer; a ring shaped insulator, deposited on parts of the sidewall of the deep trench and between the substrate of the deep trench and the first conductive layer, such that the first conductive is surrounded by the ring shaped insulator, wherein the second conductive layer is deposited on the first conductive and the ring shaped insulator; a diffusion barrier, deposited on one side of the sidewall of the deep trench and between the second conductive layer and the substrate of the deep trench, comprising a thermal oxide; a trench top isolation, deposited on the conducting structure; and a control gate, deposited on the trench top isolation.