Patent ID: 6697921
Filing Date: 2004-02-24
Classification: G06F

Abstract:
A signal processor for performing an access from plural blocks toward a buffer memory connected to a memory data bus having a first bus width through a memory control block, said signal processor comprising:a memory control block for performing a writing of data into the buffer memory and a reading of data stored in the buffer memory through the memory data bus; and a data bus provided among the blocks which has a second bus width which is narrower than the first bus width, and provided for transferring the data among the plural blocks and said memory control block; wherein said memory control block is operable to relocate data on the memory data bus to said data bus provided among the blocks when performing reading of data from the buffer memory, and operable to relocate data on said data bus provided among the blocks to the memory data bus when performing writing of data into the buffer memory; and wherein said memory control block, when storing data of successive N frames comprising a prescribed word number into the buffer memory from a recording medium, is operable to store first frame data into the buffer memory at intervals of Nâˆ’1 word, store second frame data at intervals of Nâˆ’1 word so as to adjoin the first frame data, and store the rest of Nth frame data subsequently at intervals of Nâˆ’1 word so as to adjoin Nâˆ’1th frame data, and N pieces of word data of different frames are stored successively in the buffer memory.