Patent ID: 6159823
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A trench isolation method, comprising:forming a mask pattern over a semiconductor substrate to define a trench isolation region in the semiconductor substrate, the mask pattern including a stress-relief pad pattern and a hard mask pattern stacked in sequence, the stress-relief pad layer acting to relieve the transfer of stress between the hard mask pattern and the semiconductor substrate;etching the semiconductor substrate to a predetermined depth to form a trench, using the mask pattern as an etching mask;undercutting the stress-relief pad pattern from the hard mask pattern;forming a material layer on the sidewalls of the trench to allow the trench to recover from damage occurring during the etching of the semiconductor substrate;forming a conformal stress-buffer layer over the mask pattern and the material layer, and around the undercut such that it conforms to the shape of the undercut, the conformal stress-buffer layer acting to buffer stress applied to the substrate;filling the trench with an insulation material;removing the hard mask pattern; andremoving the stress-relief pad pattern to complete a trench isolation region.