Patent ID: 7884426
Filing Date: 2011-02-08
Classification: G06F,H01L

Abstract:
1. A method of placing a cell of a semiconductor integrated circuit comprising: placing a first cell pattern, which has both first n-type and p-type transistors, on a semiconductor substrate; placing a second cell pattern, which has both second n-type and p-type transistors and a deep well below the second n-type and p-type transistors, on the semiconductor substrate; placing the first cell pattern in a substrate potential region of the semiconductor substrate; placing the second cell pattern in a plurality of separating well regions of the semiconductor substrate; placing a third cell pattern, having a cell layout including a well wall that reaches the deep well from a surface of the semiconductor substrate, around the plurality of separating well regions of the semiconductor substrate; and providing a space between at least one of the plurality of separating well regions and the substrate potential region or at least one of the plurality of separating well regions and another of the plurality of separating well regions based on the cell layout of the third cell pattern.