Patent ID: 6370640
Filing Date: 2002-04-09
Classification: G06F

Abstract:
In an instruction set processor coupled to an internal or external memory, wherein said processor comprises one or more functional units and first and second register sets, said first register set operating in an active state responsive to processor instructions involving register operands, and said second register set operating in a shadow state not responsive to processor instructions involving register operands, said processor being adapted to switch said first register set to said shadow state and said second register set to said active state using at least one instruction, and a DMA/DRA controller capable of controlling sequences of data transfers between said first or second register set operating in said shadow state and memory, a method of register set storing and loading comprising:configuring said DMA/DRA controller to transfer data between said register set operating in the shadow state and a buffer area in said memory; and transferring data, under the control of said DMA/DRA controller, between said register set operating in the shadow state and said memory buffer area.