Patent ID: 7271100
Filing Date: 2007-09-18
Classification: C09G,C09K,H01L

Abstract:
1. A method for forming a gate pattern comprising: forming a silicon nitride layer pattern on a tunnel oxide layer formed on a substrate; forming a tunnel oxide layer pattern and a trench by partially etching the tunnel oxide layer and the substrate using the silicon nitride layer pattern as an etching mask; forming an oxide layer on the tunnel oxide layer pattern and filling the trench with the oxide layer; polishing the oxide layer until the silicon nitride layer pattern is exposed to form an isolation pattern in the trench; removing the silicon nitride layer pattern; forming a polysilicon layer on the isolation pattern and the tunnel oxide layer pattern; providing a first slurry composition, the first slurry composition comprising about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive; polishing the polysilicon layer using the first slurry composition, without exposing the isolation pattern and without exposing the tunnel oxide layer pattern; providing a second slurry composition, the second slurry composition comprising about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, about 0.01 to about 1.0 weight percent of an additive, and about 0.74 to about 2.0 weight percent of a surfactant; and polishing the polysilicon layer using the second slurry composition until the silicon oxide layer pattern is exposed.