Patent ID: 7465616
Filing Date: 2008-12-16
Classification: G06K,H01L

Abstract:
1. A method of forming a field effect transistor having elevated source/drains on a substrate constituting part of a final circuit construction, the field effect transistor comprising channel area and source/drain areas which are received within active area of the substrate that is laterally separate from an isolation trench area of the substrate, the field effect transistor comprising a channel area formed within semiconductive material of the substrate, the method comprising: etching into the semiconductive material of the substrate in the laterally separate trench isolation area while masking the channel area within the active area; and after the etching, forming elevated source/drain material of the transistor within the source/drain areas of the active area and subsequently depositing an outermost portion of trench isolation material into the laterally separate isolation trench area and constituting a portion of the final circuit construction.