Patent ID: 6229333
Filing Date: 2001-05-08
Classification: H03K

Abstract:
A dynamic random access memory having an address bus and at least one data bit line, comprising:an array of memory cells having a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digitline for each column of memory cells;an addressing circuit coupled to the address bus, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array;an output data buffer circuit coupled between the array and the data bit line, the output data buffer circuit adapted to receive a data bit and to transmit the data bit to the data bit line; anda smoothing circuit having a load circuit, the smoothing circuit having current draw characteristics that are complementary to a memory circuit in the dynamic random access memory, the memory circuit being coupled to a first voltage source through a first conductor having an inductance, the smoothing circuit being coupled to the first voltage source through the first conductor.