Patent ID: 6635539
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method for fabricating a MOS transistor comprising:forming a gate pattern including a gate electrode and a silicidation resistant layer sequentially stacked on a semiconductor substrate; conformally forming a screen oxide layer over the semiconductor substrate including the gate pattern; implanting impurities into the semiconductor substrate using the gate pattern as an ion-implantation mask to form a low concentration source/drain region; forming an insulation spacer on a sidewall of the gate pattern; implanting impurities into the semiconductor substrate using the gate pattern and the insulation spacer as ion-implantation masks to form a high concentration source/drain region having an impurity concentration that is higher than that of the low concentration source/drain region; selectively forming a first metal silicide layer on a surface of the high concentration source/drain region; removing the silicidation resistant layer pattern to expose the gate electrode; and selectively forming a second metal silicide layer on a surface of the exposed gate electrode.