Patent ID: 7375553
Filing Date: 2008-05-20
Classification: G06F,H03K

Abstract:
1. A method for providing a clock tree distribution network for a field programmable gate array (FPGA), said method comprising: providing an interface having a root signal selected from at least one of an external clock signal, an internal clock signal and a plurality of phase lock loop cell output signals, said interface having programmable elements; coupling a logic array to said interface, said logic array having a plurality of local signals and programmable elements; coupling a programmable routing architecture to said programmable elements of said interface and said logic array; providing a routed clock network that selects a signal from at least one of said root signal, a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to at least one of a plurality of logic modules and a plurality of flip-flops in said logic array; and providing a hardwired clock network configured to select a signal from at least one of said root signal and a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to said plurality of flip-flops in said logic array.