Patent ID: 6310361
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A semiconductor test structure for in situ determination of an etching attack on polysilicon, comprising:a semiconductor substrate;a plurality of MOS transistors formed in said semiconductor substrate;each of said transistors having a gate with a doped polysilicon layer for evaluating said etching attack and a conductive layer disposed above said polysilicon layer, a first S/D region and a second S/D region, said gate having a covering insulation layer and insulating sidewall spacers;said gates of said transistors being electrically connected to one another and having a terminal;said second S/D region of a first one of said transistors being electrically connected to said first S/D region of a second one of said transistors; andsaid first S/D region of said first transistor being connected to a first terminal and said second S/D region of the second transistor is connected to a second terminal.