Patent ID: 6681346
Filing Date: 2004-01-20
Classification: G06F

Abstract:
A digital processing system comprising:a central processing unit (CPU) operating in a virtual address domain for executing both operating system software and user software to perform various processing tasks; a direct memory access (DMA) controller; a memory management unit (MMU) programmed to translate virtual memory addresses to physical memory addresses; a plurality of memory blocks for storing digital words in registers having physical addresses; said DMA controller governed by said CPU and operable in the virtual address domain for controlling a transfer of digital words from a source block of memory to a destination block of memory through the MMU which translates the virtual source and destination memory addresses received from said DMA controller to corresponding source and destination physical addresses of said memory; wherein the MMU includes means for detecting an improper access task from the DMA controller; and wherein the DMA controller includes means responsive to said detected improper access ask by the MMU for suspending said task.