Patent ID: 8645879
Filing Date: 2014-02-04
Classification: G06F,Y02P

Abstract:
1. A method for layout of Cu interconnect dummy inserting, on a semiconductor chip, comprising semiconductor chip on a substrate, said semiconductor chip including signal trace, said signal trace is mainly formed by patterning metal layer, wherein, including the following steps: Step 1, divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlapping, each window is indicated by A Step 2, each said window is divided into two areas: a to-be-inserted area which need dummy pattern filling and it is indicated by D wherein determine the metal density of said dummy pattern comprises the following steps: calculate the average metal density of the non-inserting area, said average metal density is indicated by ρ among them: ρ adjust said metal density of each window, so that the density gradient of adjacent window will be in an preset allowed density fluctuation range; ultimately, confirm the metal density of each window, said metal density is indicated by ρ calculate said metal density of dummy pattern that needs to-be-inserted in each window, said metal density is indicated by ρ among them: ρ ρ wherein conforming the line width of dummy pattern inserted comprises the following steps: calculate the area-weighted average value, the average value is called effective line width which is indicated by W adjust the effective line width of each window, so that the effective line width of each adjacent window will be in an preset allowed line width fluctuation range; define the effective line width described in said step b as the line width of dummy pattern that needs to-be-inserted in each said window, the line width is indicated by W Step 3, determine a metal density of the dummy pattern inserted in each square window, said metal density is indicated by ρ Step 4, determine the dummy pattern inserted to each said window according to the metal density and line width, as well as pre-set dummy pattern and layouting rules.