Patent ID: 7349339
Filing Date: 2008-03-25
Classification: H04L,H04W

Abstract:
1. A method for the operation of an ad hoc network for wireless transmission of synchronous and asynchronous messages, where the network is composed of network nodes that are distributed in any desired manner, each of which has a receiving device having an input controller, a switching station, and a transmitting device having an output controller, where transmission paths for logical connections to be transmitted from a starting node to a target node are established by way of intermediate nodes, according to a routing method, and where the nodes administer local address and control data (LCI) that are assigned to the logical connections and are reported to a preceding node of the transmission path, wherein the messages are transmitted according to a frequency multiplex method, in the form of symbol vectors, which comprise a fixed, predetermined number of symbols transmitted in parallel, the transmitting and receiving devices of adjacent nodes of a transmission path are synchronized, using cyclically transmitted identifiers whose periodicities define a time frame, the nodes of the transmission path reserve time slots within the time frame, for transmitting symbol vectors of a logical connection to be transmitted synchronously, where a start signal is sent a synchronous transmission of the logical connection begins, subsequently data packets are transmitted in the reserved time slots, and the synchronous transmission is terminated by a stop signal, after determination of a transmission path for a logical connection to be transmitted synchronously, a check is made as to whether the time slots required for the synchronous transmission are available on radio channels, whether all the nodes of the transmission path reserve the time slots, and whether a preceding node reports the local address data and the reserved time slot, in the determination of the transmission path and the time slots for a connection to be transmitted synchronously, a time delay is proposed at a node whenever two independent logical connections between two nodes claim the same time slot, where all time delays of the transmission path, from the starting node to the target node, are added to obtain a total time delay, the total time delay for the synchronous transmission not being allowed to exceed a predetermined value, if the total time delay is less than or equal to the predetermined value, synchronous transmission is permitted for the connection and if the total time delay exceeds the predetermined value, synchronous transmission is not established for the connection, and any free time slots in the nodes are filled up with messages transmitted asynchronously, in a form of symbol vectors, each symbol vector having a respective header for identifying the symbol vector and being read out from an output buffer of the node.