Patent ID: 7498835
Filing Date: 2009-03-03
Classification: G06F,G11C,H03K,Y02D

Abstract:
1. An integrated circuit, comprising: a first voltage supply circuit to provide a first operating voltage on a first power rail; a plurality of logic blocks each having a power terminal coupled to the first power rail; a second voltage supply circuit, separate from the first voltage supply circuit, to provide a second operating voltage on a second power rail; a plurality of configuration memory cells each having a power terminal coupled to the second power rail; a power configuration memory for storing one or more power configuration signals; and a power management unit having an input to receive a standby signal, a control terminal to receive the one or more power configuration signals, a first output to provide a first enable signal that selectively enables the first voltage supply circuit, and a second output to provide a second enable signal that selectively enables the second voltage supply circuit, wherein the power management unit comprises a state machine to selectively implement one or more power reduction techniques in response to the power configuration signals when the standby signal is asserted.