Patent ID: 7840830
Filing Date: 2010-11-23
Classification: G06F

Abstract:
1. A semiconductor integrated circuit having a data input apparatus, comprising: a phase detector configured to compare a phase of a data strobe signal with a phase of a clock signal to output a first phase comparison signal and a second phase comparison signal having an opposite phase of the first comparison signal; a first delay controller configured to determine whether a first data input strobe signal will be delayed or not, to output a determined signal as a second data input strobe signal in response to the first phase comparison signal; an internal clock synchronizer configured to synchronize a first aligned data and a second aligned data with the clock signal in response to the second data input strobe signal, to output the synchronized first and second data as a first internal output data and a second internal output data, respectively; and a second delay controller configured to receive the first internal output data and the second internal output data, determine whether the first internal output data and the second internal output data will be delayed or not, in response to the second phase comparison signal, and output the first internal output data and the second internal output data as a first output data and a second output data, respectively.