Patent ID: 6344409
Filing Date: 2002-02-05
Classification: H01L,Y10S

Abstract:
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer, said method comprising:dividing each chip on the wafer into a plurality of regions; determining the metal density for each region of each chip based on the circuit pattern for that region; adding a dummy circuit pattern to each region on each chip to provide at least a minimum metal density in each region or setting a maximum and/or minimum noted density for each region; forming both the desired circuit pattern and any dummy circuit pattern as openings in adielectric layer on each chip; coating the patterned dielectric layer with a layer of metal which metal fills the openings forming the desired circuit pattern and any dummy circuit pattern and covers the surface of the wafer including the circuit patterns; and polishing the metal coated wafer until no metal remains outside the desired and any dummy circuit patterns.