Patent ID: 6333655
Filing Date: 2001-12-25
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a reference driving circuit;a first circuit driven by a said reference driving circuit;an inversion reference driving circuit inputting an output of said first circuit; anda second circuit driven by said inversion reference driving circuit, said first circuit and said second circuit having a substantially equal circuit arrangement and having the same combination of driving capability and driving capacity, and a difference between a rising time and a falling time of a signal generated in each circuit block of said first circuit being canceled by a difference between a rising time and falling time of a signal generated in a corresponding circuit block of said second circuit,wherein when said first circuit and said second circuit differ in circuit blocks and the number of different circuit blocks is odd, one circuit block is used as a dummy element; and when the number of the different circuit blocks is even, no circuit block is used as a dummy element.