Patent ID: 8536693
Filing Date: 2013-09-17
Classification: G02B,H01L,H05K,Y10T

Abstract:
1. A tiered assembly of integrated circuits (ICs), comprising: a base tier including a first set of ICs and a data bridge, the ICs each having a respective array of through silicon vias (TSVs), the data bridge having submicron metal interconnects arranged in a plane that is substantially orthogonal to a longitudinal axis of the TSVs; and a second tier adjacent to the base tier, the second tier including a second set of ICs, different from the first set of ICs, at least two members of the second set of ICs coupled to each other by the data bridge, the submicron metal interconnects of the data bridge providing an interconnect density and signal integrity between the second set of ICs coupled by the data bridge that is substantially similar to that provided by internal connections in the second set of ICs, wherein the second set of ICs generate thermal energy at a rate that requires an external thermal transfer element to maintain thermal equilibrium within the respective members of the second set of ICs.