Patent ID: 8906794
Filing Date: 2014-12-09
Classification: H01L

Abstract:
1. A method of performing silicidation of gate electrodes, comprising: (a) providing a semiconductor device comprising a semiconductor substrate with a defined active device area, a logic or SRAM area and a passive device area, wherein said active device area comprises two transistors, each comprising a gate electrode; (b) forming an oxide layer above said active device area, said logic or SRAM area and said passive device area, wherein said oxide layer covers said gate electrodes and said semiconductor substrate in said logic or SRAM area; (c) forming a mask layer above said oxide layer; (d) patterning said mask layer to define a patterned mask layer that covers said active device area and said passive device area and exposes portions of said oxide layer above said transistors and above said semiconductor substrate in said logic or SRAM area; (e) with said patterned mask layer in position, forming a cover layer above the exposed portions of said oxide layer above said transistors and above said semiconductor substrate in said logic or SRAM area; (f) etching said cover layer to expose portions of said oxide layer above said gate electrodes while maintaining a portion of said cover layer between said gate electrodes; (g) removing the exposed portions of said oxide layer from above said gate electrodes to expose upper portions of said gate electrodes while maintaining a portion of said oxide layer between said gate electrodes; and (h) performing silicidation of the exposed upper portions of said gate electrodes.