Patent ID: 6287894
Filing Date: 2001-09-11
Classification: H01L,H03H

Abstract:
Process of manufacturing packaged electronic devices that are packaged at the wafer level before singulation, comprising:patterning a first wafer with a plurality of active electronic devices forming dies at spaced locations on an upper surface of said first wafer;passivating said active devices by coating portions of said dies but leaving electrode portions thereof exposed;preparing a second wafer of a dielectric material with conductive vias at locations corresponding to the locations of the electrode portions on said first wafer;applying onto an upper surface of said second wafer a grid of an anisotropic conductive thermoplastic material with lines that cross said vias;placing the first and second wafers with their upper surfaces against each other and with the vias in registry with said electrode portions, and with said anisotropic conductive thermoplastic material therebetween;applying heat and pressure to said wafers to set said anisotropic conductive thermoplastic material; andsingulating said devices as packaged devices.