Patent ID: 6903408
Filing Date: 2005-06-07
Classification: H01L

Abstract:
1. A flash memory device comprising: a substrate; a stacked gate comprising a floating gate and a control gate wherein said floating gate comprises a first oxide layer overlying said substrate and a floating gate layer overlying said first oxide layer and wherein said control gate comprises a second oxide layer overlying said floating gate layer and a control gate layer overlying said second oxide layer; source and drain regions in said substrate adjacent to said stacked gate; a third oxide layer on the sidewalls of said stacked gate; and a conductive plugs contacting said source and drain regions wherein said conductive plugs extend parallel to said stacked gate and wherein said conductive plug layer provides coupling of between said drain and source and said floating gate, wherein the surface area between the conductive plug and the floating gate is larger than the overlap surface between the floating gate and said source and drain regions.