Patent ID: 6677206
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A process for making a non-volatile memory device consisting of memory cells in the ON state and memory cells in the OFF state formed as a MOS transistor, the process comprising the steps of:forming on a substrate a first type of conductivity on a source region and on a drain region; forming on the substrate a second type of conductivity on the source region, wherein the source region comprise high dopant zones; forming a gate with side walls on the substrate; and disposing dielectric spacers on the side walls of the gate comprising the sub-steps of: forming low dopant zones underneath the dielectric spacers in the source regions and in the drain regions; and forming layers of silicide on top of one or more active regions selected from the group of active regions consisting of the source region, the drain region, and the gate; wherein the sub-step of forming low dopant zones underneath the dielectric spacers includes forming low dopant zones underneath the dielectric spacers in the source regions and in the drain regions for one or more memory cells in an ON state and forming low dopant zones underneath the dielectric spacers in the drain regions of one or more memory cells in an OFF state, using a mask which covers areas of the source region of the one or more memory cells in the OFF state which are formed by a successive dopant implant of a second type of conductivity on the substrate.