Patent ID: 7389403
Filing Date: 2008-06-17
Classification: G06F,Y02D

Abstract:
1. A microprocessor comprising: one or more front-end circuits and one or more execution circuits, at least one of the execution circuits being operable in at least a single-thread mode and a multiple-thread mode and capable of simultaneously retaining architectural state of at least two threads of a plurality of threads; an interconnection circuit enabled to provide selective communication between each of the front-end circuits and each of the execution circuits; a memory circuit enabled to provide access to external memory by each of the front-end circuits and one or more of the execution circuits; a master control circuit; wherein with respect to the interconnection circuit, the front-end circuits, and the execution circuits, the master control circuit is enabled during microprocessor initialization to establish selected unestablished characteristics of a first set of microarchitecture characteristics and further enabled to subsequently alter selected characteristics of a second set of microarchitecture characteristics based at least in part on a plurality of samples over time of at least one type of behavior measurement; wherein for each of a plurality of active threads to be processed of the plurality of threads, the master control circuit is enabled to establish a respective transient circuit collection allocated from unallocated portions of the circuits; wherein each of the transient circuit collections is collectively enabled to fetch, decode, and execute its respective active thread; and wherein at least one of the front-end circuits is operable to translate variable-length macro instructions to a plurality of operations, wherein at least some of the operations refer to at least some of the architectural state, the selective communication comprises parallel communication of at least a portion of the operations from the at least one front-end circuit simultaneously to a plurality of the execution circuits, and the plurality of execution units are operable to perform the portion of the operations at least in part in response to the communication thereof.