Patent ID: 6737316
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A method of forming a deep trench DRAM cell on a semiconductor substrate of a first conductive type, comprising the steps of:forming a deep trench capacitor in the semiconductor substrate; providing a silicon wafer; using an oxygen treatment to form a silicon oxide layer on the silicon wafer; using hydrogen ion implantation to form a predetermined cutting line between an ion-implanted region and a non-implanted region in the silicon wafer; using wafer-bonding technology to reverse and bond the silicon wafer to the silicon substrate; cleaving off the non-implanted region on the backside of the silicon wafer; using CMP to planarize the ion-implanted region, whereby the remaining part of the ion-implanted region formed on the semiconductor substrate serves as a silicon layer on the deep trench capacitor; and forming a vertical transistor in the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.