Patent ID: 7886112
Filing Date: 2011-02-08
Classification: G06F

Abstract:
1. A method, comprising: providing a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; providing a software implemented cache refill function operable to pre-load the at least one address translation table cache prior to a cache miss; permitting application software, running on the processing system, to call operating system software of the processing system to: (i) control the hardware implemented cache refill circuit and the software implemented cache refill function to operate simultaneously in managing the at least one address translation table cache; and (ii) determine which of the hardware implemented cache refill circuit or the software implemented cache refill function is to operate, and which is not to operate, in managing the at least one address translation table cache.