Patent ID: 6562714
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A method of forming contacts in the fabrication of an integrated circuit comprising:providing semiconductor device structures in and on a substrate wherein said substrate is divided into an array area and a periphery area; covering said semiconductor device structures with an etch stop layer; depositing a dielectric layer overlying said etch stop layer; concurrently first etching through said dielectric layer in said array area to form bit line contact openings and etching through said dielectric layer in said periphery area to form substrate contact openings and through said dielectric layer to form gate contact openings wherein said etching stops at said etch stop layer; second etching through said etch stop layer using a directional etch selective to said substrate wherein said second etching etches nitride transversely at least three times faster than laterally; and filling said bit line contact openings, said substrate contact openings, and said gate contact openings with a conducting layer to complete said forming contacts in the fabrication of said integrated circuit device.