Patent ID: 7375708
Filing Date: 2008-05-20
Classification: G09G

Abstract:
1. An image display panel, which includes on a substrate (a) a pixel array having a plurality of pixels for displaying an image, and (b) a data signal line drive circuit for supplying video signals to the pixel array, wherein: the data signal line drive circuit drives an n number of data signal lines for sending the video signals to the pixels on the pixel array and includes m stages of pseudo tone gradation processing means, for carrying out pseudo tone gradation processing to reduce the bit count of the video signals that are to be sent respectively to the data signal lines, where m<n; each of the pseudo tone gradation processing means sends to the data signal lines the video signals subjected to the pseudo tone gradation processing every m lines, wherein said data signal line drive circuit includes m stages of first latch means, a first shift register, n stages of second latch means and a second shift register, and wherein the video signals subjected to the pseudo tone gradation processing by each of the pseudo tone gradation processing means are latched collectively as to m lines of the video signals into said second latch means synchronously to the output of said second shift register having a lower working frequency than said first shift register, and are then sent respectively to the data signal lines.