Patent ID: 7517764
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method, comprising: (a) forming a first dielectric pad layer on a top surface of a substrate; after (a), (b) forming an opening in said pad layer, etching a trench in said substrate through said opening in said pad layer, filling said trench with a dielectric material to form trench isolation in said substrate; after (b), (c) removing any remaining pad layer; after (c), (d) forming an etch stop layer on said top surface of said substrate and said trench isolation and a dielectric mandrel layer on a top surface of said etch stop layer; after (d), (e) forming an opening in said etch stop layer and said mandrel layer, a region of said top surface of said substrate exposed in said opening; after (e), (f) forming a single-crystal silicon fin on said top surface of said substrate by epitaxial deposition of silicon in said opening, said silicon deposition filling said opening, a top surface of said fin coplanar with a top surface of said mandrel layer and said etch stop layer; after (f), (g) removing an upper layer of said fin and forming a dielectric first cap on a top surface of said fin, a top surface of said first cap coplanar with said top surface of said mandrel; after (g), (h) removing said mandrel layer and said etch stop layer; after (h), (i) forming a gate dielectric on opposite sidewalls of said fin and exposed surfaces of said substrate by thermal oxidation of surface regions of fin not protected by said first cap and exposed top surface regions of said substrate; after (i), (j) forming a gate electrode over a channel region of said fin, said gate electrode in direct physical contact with said gate dielectric layer on said opposite sidewalls of said fin and in direct physical contact with said cap on said top surface of said fin and forming a dielectric second cap on a top surface of said gate electrode; after (j), (k) forming a first source/drain in said fin on a first side of said channel region and forming a second source/drain in said fin on a second side of said channel region by ion implantation after (k), (l), forming a dielectric first protective coating on exposed surfaces of said gate dielectric layer on said fins, said first cap, said gate electrode and said second cap; after (l), (m) forming a dielectric second protective coating on said first protective coating; after (m), (n) removing said first and second protective layers from said top surface and regions sidewalls of said second cap; after (n), (o) forming a dielectric spacer on said regions of said sidewalls of said second cap and removing said gate dielectric from said top surface regions of said substrate; after (o), (p) removing a layer of said substrate from under said fin to create a void by: (1) performing a first etch to form a trench into said substrate on opposite sides of said fin but not under said gate electrode; after (1), (2) performing an isotropic second etch to undercut said fin by laterally etching sidewalls of said trench, said second etch removing a layer from a bottom surface of said fin in a region of said fin exposed to said second etch; and after (2), (3) after said second etch, said void extending under a portion of said channel region, said substrate contacting said fin only under said channel region of said fin; and after (p), (q) filling said void with a dielectric material.