Patent ID: 7725690
Filing Date: 2010-05-25
Classification: G06F

Abstract:
1. A processor comprising: an instruction buffer coupled to receive instructions fetched from an instruction cache; and a pick unit coupled to the instruction buffer and configured to select up to N instructions from the instruction buffer for concurrent transmission to respective slots of a plurality of symmetrical slots, each of the plurality of symmetrical slots having a same set of hardware resources as each other one of the plurality of symmetrical slots, wherein N is an integer greater than one, and wherein the pick unit is configured to transmit an oldest instruction of the selected instructions to any of the plurality of slots even if a number of the selected instructions is greater than one, and wherein the pick unit is configured to transmit the oldest instruction of the selected instructions to a selected slot of the plurality of slots in a first clock cycle even if the number of the selected instructions is greater than one in the first clock cycle, and wherein the pick unit is configured to concurrently transmit other ones of the selected instructions to other slots of the plurality of slots based on the selected slot to which the oldest instruction is transmitted, wherein the selected slot in the first clock cycle is a next consecutive slot to a second slot to which a youngest instruction from a preceding set of up to N instructions from the instruction buffer was transmitted during a preceding clock cycle, and wherein the pick unit is configured to select the selected slot as the next consecutive slot responsive to the youngest instruction having been transmitted to the second slot in the preceding clock cycle.