Patent ID: 8667365
Filing Date: 2014-03-04
Classification: G06F,G11C

Abstract:
1. A memory system, comprising: a plurality of memory devices; a controller configured to control the plurality of memory devices, wherein the controller sends a read command and a program command to one of the plurality of memory devices at different times, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices; and at least one channel connected between the plurality of memory devices and the controller, the at least one channel comprising input/output data lines and control signal lines, which are connected with the plurality of memory devices and provide the read and program commands and read and program addresses to the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein chip enable signals are provided via the chip enable signal lines to the plurality of memory devices to enable the plurality of memory devices independently, wherein the one memory device performs the internal read operation when its respective chip enable signal is disabled and the another memory device has its data read when its respective chip enable signal is enabled.