Patent ID: 7139289
Filing Date: 2006-11-21
Classification: H04N

Abstract:
1. An error and sync detection device, comprising: a data rearrangement block for receiving 7-bit byte data and converting the 7-bit byte data to 8-bit byte data; a parity check block for receiving the 8-bit byte data, which has been converted by the data rearrangement block, and performing an MPEG sync byte detection operation and a parity-check-based error detection operation using the received byte data; and a data storage block, capable of receiving/outputting 8-bit byte data, for receiving and storing the 8-bit byte data, which has been converted by the data rearrangement block, and 8-bit intermediate byte data produced during a calculation process for the MPEG sync byte detection operation and the parity-check-based error detection operation performed by the parity check block, wherein the parity check block includes a first calculation block and a second calculation block for performing a predetermined syndrome computation including an operation of delaying data by a predetermined number of clocks; the first calculation block receives the 8-bit byte data that is output from the data rearrangement block, and performs a calculation therewith before the operation of delaying the data by a predetermined number of clocks, so as to output intermediate byte data to the data storage block, the intermediate byte data representing a result of the calculation; and the second calculation block receives the intermediate byte data from the data storage block, and performs the calculation therewith before the operation of delaying the data by a predetermined number of clocks, so as to output 8-bit byte data that has undergone the MPEG sync byte detection operation and the parity-check-based error detection operation.