Patent ID: 6799263
Filing Date: 2004-09-28
Classification: G06F

Abstract:
A computer readable medium containing executable instructions which, when executed in a processing system, causes the system to prefetch instructions into a cache memory, comprising:a branch predict instruction for predicting a branch and prefetching an instruction of a predicted path from said branch; a prefetch instruction for prefetching an instruction of an unpredicted path from said branch, said prefetch instruction does not include a branch instruction address and branch prediction information, said prefetch instruction comprising: a target field for specifying an address at which prefetching begins; a count field for specifying a number of instructions to prefetch; a cache level field for specifying a level of cache into which the instructions are to be stored; a trace field for, establishing a trace vector; and a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted; wherein said branch predict instruction and said prefetch instruction are separately emitted by a compiler, said branch predict instruction and said prefetch instruction are inserted into a programmed sequence of instructions, said branch predict instruction and said prefetch instruction do not change an architectural state of a processor, said branch predict instruction and said prefetch instruction pass static information from said compiler to said processor.