Patent ID: 7999574
Filing Date: 2011-08-16
Classification: H03K

Abstract:
1. A level conversion circuit, comprising: an intermediate voltage generating portion to generate an intermediate voltage between a first voltage supplied from a first power supply source and a second voltage supplied from a second power supply source upon receiving the first voltage and the second voltage higher than the first voltage; a first buffer portion operated by the intermediate voltage to receive a first signal and an inverted first signal of a first amplitude corresponding to the first voltage, the first buffer portion outputting a second signal and an inverted second signal having a second amplitude corresponding to the intermediate voltage; and a level shift portion operated by the second voltage to receive the second signal and the inverted second signal, and to output a third signal and an inverted third signal having a third amplitude corresponding to the second voltage, wherein the intermediate voltage generating portion includes, a P channel MOS transistor operated by the second voltage having a source, a gate connected to the first power supply source and a drain connected to a constant current source, and an inverting amplifier having an input terminal connected to a connection node of the drain of the P channel MOS transistor and the constant current source, and an output terminal connected to the source of the P channel MOS transistor, and wherein the intermediate voltage is outputted from a connection node between the source of the P channel MOS transistor and the output terminal of the inverting amplifier, the intermediate voltage being equal to a sum of the first voltage and a voltage between the gate-source of the P channel MOS transistor.