Patent ID: 9152326
Filing Date: 2015-10-06
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: a first sub memory block and a second sub memory block; a first redundancy memory block and a second redundancy memory block; a first data line group and a second data line group coupled to the first sub memory block and the second sub memory block, respectively; a first redundancy data line group and a second redundancy data line group coupled to the first redundancy memory block and the second redundancy memory block, respectively; a first switching circuit coupled between the first data line group and the first redundancy data line group; a second switching circuit coupled between the first redundancy data line group and the second redundancy data line group; a third switching circuit coupled between the second redundancy data line group and the second data line group; a first page buffer coupling the first sub memory block to the first data line group; a second page buffer coupling the second sub memory block to the second data line group; a first redundancy page buffer coupling the first redundancy memory block to the first redundancy data line group; and a second redundancy page buffer coupling the second redundancy memory block to the second redundancy data line group, wherein data to be programmed into the first redundancy memory block is transmitted to the first redundancy page buffer through the second data line group, when the second switch circuit and the third switching circuit are turned on.