Patent ID: 6567317
Filing Date: 2003-05-20
Classification: G11C

Abstract:
In a Rambus DRAM having two data ports DQA and DQB, a circuit for controlling output currents of the data ports, comprising:first and second current evaluation means for outputting first and second control signals respectively by evaluating currents of the data ports DQA and DQB; a current control value producing means for producing a next current control value for the data port DQA by receiving the first control signal and a present current control value of the data port DQA and producing a next current control value for the data port DQB by receiving the second control signal and a present current control value of the data port DQB, the current control value producing means operating repetitively to produce the next current control values alternately; and first and second control value latch means for latching the respective current control values of the data ports DQA and DQB produced by the current control value producing means.