Patent ID: 7210020
Filing Date: 2007-04-24
Classification: G06F

Abstract:
1. A method, comprising: forming a synchronous memory device having addressable memory cells adapted to access a sequence of memory cells in response to an externally provided start address; forming a microprocessor coupled to the synchronous memory device and adapted to initiate a first data read operation at a first memory cell address; and forming a memory controller in the synchronous memory device adapted to produce a second start address in response to the externally provided start address and initiate a read operation in anticipation of a second data read operation at a new memory cell start address provided from the microprocessor, such that data stored at the second start address is output on an external data communication connection of the synchronous memory device following data output by the first data read operation to maintain an active data output stream between the first data read operation and a second data read operation requested by the microprocessor at the new memory cell start address for each first data read operation.