Patent ID: 6137719
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array having a plurality of memory cells, arranged in rows and columns, each storing data of n bits, where n is integer of at least two;a plurality of word lines arranged in the rows, each connected with a control gate of a memory cell arranged on a corresponding row;a plurality of pairs of bit lines, arranged in the columns, each connected with a drain of a memory cell arranged on a corresponding column;a word line driver selectively supplying (2.sup.n -1) types of read voltages to said word lines in reading;a sense latch circuit group latching data of said plurality of pairs of bit lines;(2.sup.n -1) data latch circuit groups each latching said data latched by said sense latch circuit group when said word line driver supplies corresponding one of said (2.sup.n -1) types of read voltages to said word lines; anda read data conversion circuit converting said data latched by said data latch circuit groups to said data of n bits and reading said data of n bits.