Patent ID: 6266803
Filing Date: 2001-07-24
Classification: G06F

Abstract:
A method for achieving minimal clock skew in an integrated circuit, the integrated circuit including a circuit placement area in which are placed a plurality of building blocks arranged in a plurality of rows, one or more of said rows being designated for placement of clock buffers that generate a clock signal, the steps including:for each row of said plurality of building blocks:(a) identifying terminals of said building blocks designated for receiving said clock signal; and(b) determining a capacitance associated with electrically coupling the clock signal from clock buffers in an assigned buffer area to the identified terminals of said building blocks in said row;summing said capacitance in each row, over all rows in said circuit placement area, to determine a total capacitance for said circuit placement area; andfor each row designated for placement of clock buffers, assigning a number of clock buffers to be placed in said designated row based on said total capacitance, after deducting from said total capacitance an amount of capacitance equal to loads driven by clock buffers assigned in previous designated rows, and the number of said designated rows yet to have clock buffers assigned.