Patent ID: 8885759
Filing Date: 2014-11-11
Classification: H04B

Abstract:
1. A method for bit communication between two nodes through two independent channels, said method comprising: establishing two independent bidirectional paths as two independent channels between the two nodes; dedicating one channel of the two independent channels for carrying a non-modulated pulse representing only logic “1”, wherein dedicating the second channel for carrying a non-modulated pulse representing only logic “0”; sending a non-modulated pulse representing only logic “1” from the one node point to the second node point through one channel and sending a non-modulated pulse representing only logic “0” through the other channel; performing bit transmission mechanism for logic “0”, wherein at any clock cycle relative to the transmitting node, transmitting a bit representing logic “0” by generating a pulse of a finite duration through the dedicated independent channel for carrying pulses representing only logic “0”, while, during the same clock cycle at the same transmitting node, nothing transmitted through the dedicated channel for carrying pulses representing logic “1”; performing bit transmission mechanism for logic “1”, wherein at any clock cycle relative to the transmitting node, transmitting a bit representing logic “1” by generating a pulse of a finite duration through the dedicated independent channel for carrying pulses representing only logic “1”, while, during the same clock cycle at the same transmitting node, nothing transmitted through the dedicated channel for carrying pulses representing logic “0”; performing bit reception mechanism, wherein during any clock cycle with respect to the receiving node, the power on each of the two independent channels is sensed, a positive value higher than zero or higher than or equal to any predefined positive threshold results from any noise and interference generated power magnitude sensed at the channel representing logic “0” subtracted from the power magnitude sensed at the channel representing logic “1”, means logic “1” is received; wherein a negative value lower than zero or lower than or equal to any predefined negative threshold results from power magnitude sensed at the channel representing logic “0” subtracted from any noise and interference power magnitude sensed at the channel representing logic “1”, means logic “0” is received, wherein other values with respect to the said subtraction logic represent no confirmation of a logic being received; performing two channels balancing mechanism, wherein at a specific recurrent event with specific duration relative to transmitting and receiving nodes, a parallel-executed instruction transmitting two pulses of a common identical finite duration, simultaneously through the dedicated channel for logic “0” and the dedicated channel for logic “1” at the same clock cycle, from one specific node towards the other node, wherein during the same specific recurrent event, at the other node during any clock cycle of a specific number of predefined clock cycles with respect to receiving node, the power amount at each of the channels is sensed and labeled with a time tag; wherein a positive value higher than zero or higher than or equal to any predefined positive threshold results from the power amount sensed at the channel representing logic “0” subtracted from the power amount sensed at the channel representing logic “1”, renders logic “1” dedicated channel having an added attenuation factor relative to the value of the subtraction process; wherein a negative value lower than zero or lower than or equal to any predefined negative threshold results from the power amount sensed at the channel representing logic “0” subtracted from the power amount sensed at the channel representing logic “1”, renders logic “0” dedicated channel having an added attenuation factor relative to the value of the subtraction process; wherein a positive value higher than zero or higher than or equal to any predefined positive threshold results from time tag value of the power amount sensed at logic “0” dedicated channel subtracted from the time tag value of the power amount sensed at logic “1” dedicated channel, renders logic “0” dedicated channel having an added delay factor relative to the value of the subtraction process; wherein a negative value lower than zero or lower than or equal to any predefined negative threshold results from time tag value of the power amount sensed at logic “0” dedicated channel subtracted from the time tag value of the power amount sensed at logic “1” dedicated channel, renders logic “1” dedicated channel having an added delay factor relative to the value of the subtraction process.