Patent ID: 6888202
Filing Date: 2005-05-03
Classification: G11C,H03K

Abstract:
1. An integrated circuit comprising: a latch circuit including, a first inverter including a first PMOS transistor and a first NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second PMOS transistor and a second NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; an input switch including, an access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate coupled to a first access control node; and a first output switch, which includes a first discharge path coupled separate from the latch circuit to selectably discharge a precharge voltage in response to a stored data value of the first data node or the second data node.