Patent ID: 9025394
Filing Date: 2015-05-05
Classification: G11C

Abstract:
1. A memory device comprising: a first signal line; a memory cell array divided into a first area and a second area and comprising a plurality of first memory cells in the first area and a plurality of second memory cells in the second area, wherein the plurality of first and second memory cells are coupled the first signal line, and each of the plurality of first and second memory cells has a reference node; a first voltage adjustment circuit for adjusting voltages at the reference nodes of the plurality of first memory cells; and a second voltage adjustment circuit for adjusting voltages at the reference nodes of the plurality of second memory cells; wherein, the reference nodes of the plurality of first memory cells are coupled to a ground through the first voltage adjustment circuit, and the reference nodes of the plurality of second memory cells are coupled to the ground through the second voltage adjustment circuit, and wherein when the memory device is performing an access operation to the first area, the second voltage adjustment circuit adjusts the voltages at the reference nodes of the plurality of second memory cells of the second area to be at a reference voltage level which is higher than a voltage level of the ground.