Patent ID: 8923468
Filing Date: 2014-12-30
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit, comprising: a serial data input terminal, arranged for receiving a serial data; a reference clock input terminal, arranged for receiving a reference clock; a control circuit, arranged for generating a control signal to selectively configure the clock and data recovery circuit to operate in one of a plurality of stages; a detecting circuit, arranged for generating a first adjusting signal according to at least the reference clock when the clock and data recovery circuit operates in a frequency locking stage, and generating a second adjusting signal according to at least the serial data when the clock and data recovery circuit operates in a clock and data recovery stage; and a controllable oscillator, arranged for generating a recovered clock according to the first adjusting signal when the clock and data recovery circuit operates in the frequency locking stage, and generating the recovered clock according to the second adjusting signal when the clock and data recovery circuit operates in the clock and data recovery stage; wherein the control circuit comprises: