Patent ID: 6629187
Filing Date: 2003-09-30
Classification: G06F,Y02D

Abstract:
A digital system having a microprocessor, the microprocessor comprising:a central processing unit (CPU) connected to an address generation unit; a cache connected to the address generation unit via a first address bus, the cache having a plurality of operating modes; memory circuitry connected to the cache via a data bus, wherein the memory circuitry is connected to receive an address from the address generation unit via a second address bus; at least a first memory mapped device connected to the second address bus, wherein the first memory mapped device is mapped at a first address; and a physical address attribute memory (PAAM) connected to the second address bus, the PAAM being connected to the cache via at least a first attribute control signal, wherein the PAAM is operable to assert the first attribute control signal in response to the first address being on the second address bus, such that the cache operates in a first one of the plurality of operating modes when the first memory mapped device is addressed and in a different one of the plurality of operating modes when the memory circuitry is addressed.