Patent ID: 6734085
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method of using anti-code dosage as LDD implant to turn off a MOS transistor comprising the steps of:providing a substrate having an NMOS region and a PMOS region; forming a dielectric layer over said substrate, including over said NMOS and PMOS regions; forming an NMOS gate electrode over said NMOS region and a PMOS gate electrode over said PMOS region over said dielectric layer formed over said NMOS and PMOS regions; forming a first cover layer over said PMOS region including over said PMOS gate electrode; performing an N-type lightly doped drain (NLDD) implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask; removing said first cover layer from over said PMOS region; forming a second cover layer over said NMOS region including over said NMOS gate electrode; performing P-type lightly doped drain (PLDD) implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask; removing said second cover layer from over said NMOS region; forming a third cover layer over said PMOS region including over said PMOS gate electrode; performing a code implant over uncovered said NMOS region using said NMOS gate electrode as a self-aligned mask; removing said third cover layer from over said PMOS region; forming a fourth cover layer over said NMOS region including over said NMOS gate electrode; performing a code implant over uncovered said PMOS region using said PMOS gate electrode as a self-aligned mask; removing said fourth cover layer from over said NMOS region; and performing a vertical anti-code LDD implant to turn off said MOS transistor.