Patent ID: 9196362
Filing Date: 2015-11-24
Classification: G11C

Abstract:
1. A non-volatile storage system, comprising: a memory array, the memory array includes a first group of vertical bit lines connected to a plurality of word line combs, the first group of vertical bit lines includes a first bit line, each word line comb of the plurality of word line combs is connected to the first bit line, the memory array includes a second group of vertical bit lines connected to the plurality of word line combs, the second group of vertical bit lines includes a second bit line, each word line comb of the plurality of word line combs is connected to the second bit line; and one or more managing circuits in communication with the memory array, the one or more managing circuits cause a first forming operation to be performed to a first set of non-volatile storage elements connected to the first group of vertical bit lines and the plurality of word line combs, the one or more managing circuits cause a second forming operation to be performed to a second set of non-volatile storage elements connected to the second group of vertical bit lines and the plurality of word line combs, the second forming operation is performed subsequent to the first forming operation, the number of vertical bit lines in the second group of vertical bit lines is greater than the number of vertical bit lines in the first group of vertical bit lines.