Patent ID: 7444458
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. A method of controlling the operation of a memory system that includes a plurality of memory devices connected to a bus, with each of the memory devices including an array of memory cells and addressing circuitry which is used to uniquely address the addressing circuitry's single associated memory device, the method comprising: selecting a first one of the memory devices; transferring a first local address from a memory controller to the first memory device, with the first local address comprising at least three bits of address that are transferred to the first memory device over the bus in parallel, wherein the first local address uniquely identifies the first memory device; selecting a second one of the memory devices; transferring a second local address from the memory controller to the second memory device, with the second local address comprising at least three bits of address that are transferred to the second memory device over the bus in parallel, wherein the second local address uniquely identifies the second memory device; selecting a third one of the memory devices; transferring a third local address from the memory controller to the third memory device, with the third local address comprising at least three bits of address that are transferred to the third memory device over the bus in parallel, wherein the third local address uniquely identifies the third memory device; and wherein the first memory device is used as a boot memory carry out address assignment to other memory devices.