Patent ID: 6506639
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having low resistance reduced channel length transistors, the method comprising:(a) forming n-well regions and p-well regions in a semiconductor substrate; (b) forming isolation structures separating the n-well regions from the p-well regions forming exposed portions of the semiconductor substrate over the n-well regions and over the p-well regions; (c) forming a layer of dielectric on the exposed portions of the semiconductor substrate forming a surface of dielectric including the portions of dielectric and top surfaces of the isolation structures; (d) forming a layer of a high K dielectric material on the surface of the layer of dielectric, wherein the layer of high K dielectric material is selected from the group including barium strontium titanate (BST), strontium bismuth tantalate (SBT), tantalum oxide (Ta2O5), and lead zirconate titanate (PZT); (e) forming a layer of a material on the layer of the high K dielectric, wherein the layer of material is selected from the group including a nitride of titanium and a nitride of tantalum; (f) forming trenches having a width X1 in the layer of material and the layer of high K dielectric material over selected n-well regions and selected p-well regions; (g) forming PLDD regions in the n-well regions; (h) forming NLDD in the p-well regions; and (i) forming spacers on sidewalls of the trenches and on portions of the layer of dielectric, wherein the spacers are formed on the portions of the sidewalls made up of the layer of high K dielectric material and the layer of material formed on the layer of high K dielectric material, and wherein the spacers the spacers are separated by a distance X2, wherein X2 is less than X1 and the distance X2 determines the length of a gate channel.