Patent ID: 7342416
Filing Date: 2008-03-11
Classification: H03K

Abstract:
1. A system on a chip comprising: a microprocessor; a read-only-memory block; a random-access memory block; an FPGA section including at least one FPGA tile comprising: a plurality of functional groups (FGs) arranged in rows and columns, each configurable to perform Boolean functions, each (FG) having a first, second and third set of input ports and a first and second set of output ports; a first set of routing conductors disposed within said at least one FPGA tile programmmably coupled to said first set of output ports of said logic components and configured to receive signals, route signals within said at least one FPGA tile, and provide said signals to said first set of input ports of said logic components; a second set of routing conductors disposed across said at least one FPGA tile and at least one other FPGA tile, independent of said first set of routing conductors coupled to said second set of output ports and that is configured to receive, select and route signals around said at least one FPGA tile and within said at least one FPGA tile, and provide said signals to said second set of input ports of said logic components: and a third set of routing conductors disposed across said at least one FPGA tile, independent of said first and second set of routing conductors coupled to at least one of said first output ports of said logic components, and employing a plurality of tracks and a plurality of switches to receive signals, route signals around said at least one FPGA tile and within said at least one FPGA tile, and provide said signals to said third set of input ports of said logic components when said first set of routing conductors cannot be used.