Patent ID: 7750464
Filing Date: 2010-07-06
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising, over its module board: a plurality of memory chips in a stacked state; and a data processor chip capable of simultaneously accessing said memory chips, wherein a plurality of address system bonding pads related to an address and a command for said data processor chip to access said memory chips are coupled, through a common address system wiring among said plurality of memory chips, to address system bonding pads to which the memory chips correspond, wherein a plurality of data system bonding pads related to data and a data strobe signal for said data processor chip to access said memory chips are coupled, through individual data system wirings among said plurality of memory chips, to data system bonding pads to which the memory chips correspond, and wherein, with respect to an arrangement of a plurality of data system bonding pads of said data processor chip, an arrangement of the data system bonding pads to which the memory chips coupled by said data system wiring correspond is made such that the memory chips are disposed in an alternating sequence.