Patent ID: 8563962
Filing Date: 2013-10-22
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a plurality of memory cells; and a lead-out line provided in common to said plurality of memory cells, wherein each of said memory cells includes: a transistor formed above a substrate; and a variable resistance element which includes a lower electrode, an upper electrode comprising a noble metal, and a variable resistance layer disposed between said lower electrode and said upper electrode, said variable resistance layer has a resistance value that changes reversibly in response to an electric pulse that goes through said transistor and is applied between said lower electrode and said upper electrode, said lead-out line is in direct contact with said upper electrode included in each of said memory cells, and the bottommost surface of the bottom surface of said lead-out line is formed to be lower than the top surface of said upper electrode and higher than the top surface of said lower electrode, and said upper electrode is completely covered by said lead-out line.