Patent ID: 6166581
Filing Date: 2000-12-26
Classification: G06G,H03H

Abstract:
A differential integrator circuit, comprising:an input section having a first and a second input and a first and second output, said input section accepting a fully differential input signal through first and second switching means during a first period of time, said first and said second output providing a first and a second output signal, said input section further comprising:a first capacitive means connected serially between said first switching means and said first output;a second capacitive means connected serially between said second switching means and said second output;a third switching means of said first period of time connected between said first and said second output of said input section, said third switching means thereby connecting serially said first and said second capacitive means to form a voltage divider when said third switching means is closed;an offset and low noise storage section having a first and a second input, and a first and a second output, said first and said second input of said offset and low frequency noise section connected, through a third and a fourth switching means during a second period of time, to said first and said second output of said input section, respectively, said offset and low frequency noise section used to store an offset and a low frequency noise signal of an amplifying means, said offset and low noise storage section further comprising:a third capacitive means connected serially between said third switching means and said first output of said offset and low noise storage section, said third capacitive means storing said offset and low frequency noise signal;a fourth capacitive means connected serially between said fourth switching means and said second output of said offset and low noise storage section, said fourth capacitive means storing said offset and low frequency noise signal;said amplifying means with a first and a second input and a first and a second output, said first and said second input of said amplifying means connected to said first and said second output of said offset and low frequency noise section, respectively, said outputs of said amplifying means connected, through switching means during a first period of time, to an output VOUT+ and an output VOUT-, respectively;an upper integrator section connected between said first input and said first output of said amplifying means through switching means during a first period of time, and connected to said first input of said offset and low noise storage section through switching means during a second period of time; anda lower integrator section connected between said second input and said second output of said amplifying means through switching means during a first period of time, and connected to said second input of said offset and low noise storage section through switching means during a second period of time.