Patent ID: 6842374
Filing Date: 2005-01-11
Classification: G11C,H01L

Abstract:
1. An operating method for an N-channel electrically erasable programmable logic device, the electrically erasable programmable logic device comprising: a P substrate; a first N-type doped region disposed in the P substrate; a first gate on the P substrate and adjacent to the first N-type doped region, the first gate being in a floating state and used for storing data of the electrically erasable programmable logic device; a second N-type doped region laterally disposed in the P substrate and adjacent to the first gate, wherein the first N-type doped region and the second N-type doped region define a first channel; a second gate as a select gate of the electrically erasable programmable logic device, the second gate being on the P substrate and adjacent to the second N-type doped region; and a third N-type doped region in the P substrate, wherein the second N-type doped region and the third N-type doped region define a second channel; the operating method comprising: performing a program mode, wherein the first N-type doped region is coupled to a bit line voltage V by changing the bit line voltage V