Patent ID: 8999795
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A method for fabricating an asymmetrical field effect transistor (FET) device, the method comprising: forming a semiconductor structure having a substrate layer, a buried oxide (BOX) layer, a semiconductor-on-insulator (SOI) layer having a source and a drain region, a dummy gate on the SOI layer, and an offset spacer disposed around the dummy gate; removing at least a portion of the offset spacer and the dummy gate to expose a portion of the SOI layer; depositing a liner layer over the portion of the SOI layer and the offset spacer; implanting ions into a first portion of the liner layer; depositing an oxide film on a second portion of the liner layer; removing the first portion of the liner layer to form a trench between the oxide film and the offset spacer; forming an extended source region by implanting dopants in a portion of the SOI layer disposed beneath the trench; removing the oxide film and the second portion of the liner layer; depositing a high-k layer on exposed portions of the extended source region and the offset spacer; depositing a metal gate layer over the high-k layer; and forming a contact metal layer over the metal gate layer.