Patent ID: 7983102
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A data detecting apparatus that operates according to a first synchronization signal, the data detecting apparatus comprising: a plurality of memory cells; a plurality of data lines coupling to the plurality of memory cells separately for controlling reading or writing the plurality of memory cells; a plurality of bit lines coupling to the plurality of memory cells separately for outputting a datum stored in the plurality of memory cells; a plurality of sense amplifiers, coupling to the plurality of bit lines separately, for amplifying the data outputted from the plurality of memory cells; and at least one pre-charging circuit for setting a pre-determined period according to the first synchronization signal and generating a pre-charging signal within the pre-determined period, and for charging the memory cells and the sense amplifiers via the data lines, wherein the pre-charging circuit charges the memory cells and the sense amplifiers for a pre-determined width of time via the data lines during every half of the period of the first synchronization signal.