Patent ID: 8340239
Filing Date: 2012-12-25
Classification: H04N

Abstract:
1. A decoder capable of adaptively generating a clock window, comprising: a frame code searching unit configured to search for a match between a predefined frame code and received data bits, and to generate a frame code control signal when the predefined frame code is matched with the received data bits; a clock window generator adapted to determine a beginning and an end of the clock window based on a falling edge of a horizontal synchronization signal and the frame code control signal, and to determine a time difference between an actual frame code and the predefined frame code; and a symbol timing recovery unit is arranged to perform symbol timing recovery through received clock run-in signals within the clock window, wherein the clock window is bounded between the beginning and the end determined by the clock window generator; wherein the time difference is determined by using a first variable that represents a lead time of an actual leading frame code ahead of the predefined frame code and a second variable that represents a lag time of an actual lagging frame code behind the predefined frame code; wherein the time difference is determined at a time when the frame code control signal is asserted; wherein the beginning of the clock window (CLK_Win_Bgn) and the end of the clock window (CLK_Win_End) are determined as follows:  with T wherein at least one of the first variable and the second variable is updated by the clock window generator using expressions as follows whenever the frame code control signal becomes asserted:  with Alpha being a constant, TMR