Patent ID: 6184476
Filing Date: 2001-02-06
Classification: H05K,Y10T

Abstract:
A thin multi-layer circuit board which is obtained by alternately stacking wiring pattern layers, including a top wiring pattern layer and insulating layers on an insulating plate-like substrate;wherein said wiring pattern layers are electrically connected through vias in said insulating layers in order to constitute a predetermined circuit pattern by said wiring pattern layers;wherein a metallic barrier layer is formed on an exposed portion of said top wiring pattern layer so as to partially cover said top wiring pattern layer in an electronic part-mounting region, a barrier metal exclusion zone is included in said metallic barrier layer, said barrier metal exclusion zone being a part of said metallic barrier layer which does not cover said exposed portion of said top wiring pattern layer and a remodeling pad layer,an electronic part-mounting pad layer formed on said metallic barrier layer, said remodeling pad layer being arranged neighboring said barrier metal exclusion zone and said electronic part-mounting pad layer being arranged neighboring said remodeling pad layer, andwherein said metallic barrier layer is formed such that a barrier metal exclusion zone is at a first location, between the aligned vias in said insulating layers and a second location of the remodeling pad layer, wherein said barrier metal exclusion zone is a part of said metallic barrier layer which does not cover said exposed portion of said wiring pattern layer.