Patent ID: 6055197
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array having a plurality of memory cells arranged in the form of an array, and a plurality of elements, each of which selects a predetermined number of memory cells from said plurality of memory cells, x elements (x is an integer of 2 or more) of said plurality of elements being simultaneously activated, and said memory array being divided into a plurality of repair regions, each of which has at least two of said elements;a plurality of spare element groups, each of which is provided so as to correspond to a corresponding one of said repair regions, each of said spare element groups having a plurality of spare memory cells and a predetermined number of spare elements, each of said spare elements selecting a predetermined number of spare memory cells from said spare memory cells to replace a defective element in a corresponding one of said repair regions;a plurality of redundant control circuits, each of which is coupled to a corresponding one of said spare elements in a corresponding one of said spare element groups; anda plurality of control parts, each of which is coupled to a corresponding one of said spare element groups, each of said control parts controlling the replacement of one of said spare elements m said corresponding one of said spare element groups for a defective element on the basis of at least an output of said redundant control circuits corresponding to said one of said spare elements in said corresponding one of said spare element groups,wherein the number of said repair regions is x.multidot.y assuming that a ratio of a memory capacity of a region of said memory array per one of elements simultaneously activated in said memory array to a memory capacity of one of said repair regions corresponding to one of said spare element groups is y (y is an integer of 1 or more),each of said repair regions being designed so that a plurality of said elements are simultaneously activated therein, andeach of said spare element groups being designed so that the number of said spare elements simultaneously activated therein is one.