Patent ID: 9171626
Filing Date: 2015-10-27
Classification: G11C,H01L

Abstract:
1. A method of programming a memory array, comprising: decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source coupled to the first select gate while the first select gate is off; decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line coupled to the second select gate while the second select gate is off; and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell, not targeted for programming, in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and after or substantially concurrently with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.