Patent ID: 6107108
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of forming a test chip for measuring the concentration uniformity of an ion implanted dopant impurity in a semiconductor wafer comprising:(a) providing a semiconductor wafer;(b) implanting a dopant impurity of a first type into the surface of said semiconductor wafer by scanning an ion implantation beam containing said dopant impurity over the surface of said semiconductor wafer along a path;(c) forming a field isolation on said semiconductor wafer thereby forming islands of semiconductor active area;(d) forming a gate oxide on said islands of semiconductor active area;(e) depositing and patterning a polysilicon layer to form polysilicon gate electrodes over said gate oxide whereby a plurality of parallel gate electrodes extend over each of said islands in a direction parallel to said path of said ion implantation beam and whereby said plurality of parallel gate electrodes are interconnected in a comb-like fashion and terminated to a gate contact pad by a polysilicon stripe;(f) implanting dose of a dopant impurity of a second type into said semiconductor wafer thereby forming source/drain elements;(g) depositing an insulative layer over said semiconductor wafer;(h) patterning and etching contact openings to said source/drain elements and said gate contact pads in said insulative layer(i) forming conductive contacts in said contact openings;(j) depositing a metal layer over said semiconductor wafer; and(k) patterning and etching said metal layer thereby forming metal stripes connecting said source/drain elements and said gate contact pads to probe contact pads.