Patent ID: 7852867
Filing Date: 2010-12-14
Classification: H04L

Abstract:
1. An integrated egress/replay memory structure disposed within a device having one or more egress pipes with respective reconfigurable egress data bandwidths, said integrated egress/replay memory structure comprising: (a) a first packet data storage area for storing first-time playout payload data (PdUx) of a first packet that is subject to being played out for a first time from the memory structure through a corresponding first egress pipe, the first egress pipe having a configurably defined first egress data bandwidth, at an average first rate corresponding to the configurably defined first egress data bandwidth; (b) a second packet data storage area for storing second packet payload data (PdAx) that has been at least once transmitted via the first egress pipe as said first-time playout payload data (PdUx) but is subject to possibly being replayed through the first egress pipe at least one more time and at said average first rate corresponding to said predefined first egress data bandwidth; and (c) a third packet data storage area for storing third payload data (PdBx) of one or more packets that have not yet been transmitted wholly as said first-time playout payload data (PdUx), where the third payload data (PdBx) can be written to the third storage area at an average second rate corresponding to a raceway bandwidth that is no less than said first egress data bandwidth.