Patent ID: 8822278
Filing Date: 2014-09-02
Classification: H01L

Abstract:
1. A method for fabricating a field-effect transistor (FET) device, the method comprising the steps of: providing a wafer; forming active areas in the wafer using shallow trench isolation; forming gate stacks on the wafer present over one or more of the active areas, wherein a select two or more of the gate stacks have an irregular gate-to-gate spacing in that the gate-to-gate spacing between a given two of the gate stacks next to one another on the wafer is selectively configured to be greater than the gate-to-gate spacing of the gate stacks on the wafer to either side of the given two gate stacks, wherein by way of the irregular gate-to-gate spacing: i) for at least a given one of the active areas in which an asymmetrical transistor is formed a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area, and ii) for at least another given one of the active areas in which a symmetrical transistor is formed a gate-to-gate spacing on a source side of the other given active area is equal to a gate-to-gate spacing on a drain side of the other given active area, such that the gate stacks formed on the wafer all have a regular gate-to-gate spacing except for those of the gate stacks adjacent to the source side of the given active area in which the asymmetrical transistor is formed that have the irregular gate-to-gate spacing, which is achieved by first forming the gate stacks having the gate-to-gate spacing on the source side of the given active area which is greater than the gate-to-gate spacing on the drain side of the given active area, and then further increasing the gate-to-gate spacing on the source side of the given active area; forming spacers on opposite sides of the gate stacks; and performing an angled implant into the source side of the given active area.