Patent ID: 6614674
Filing Date: 2003-09-02
Classification: G11C,H02M

Abstract:
A memory circuit comprising:a memory array; a voltage pump supplying voltage to said memory array; and a regulator circuit connected to said voltage pump, said regulator circuit comprising: voltage divider means connected between a first and second voltage, said voltage divider means generating a reference voltage, first adjustment means for adjusting a resistance of said voltage divider means to modify a voltage level of the reference voltage, second adjustment means for adjusting the resistance of said voltage divider means to modify the voltage level of the reference voltage, first connection means for connecting said first adjustment means to said voltage divider means in response to a first control signal, said first connection means disconnecting said first adjustment means from said voltage divider means when the first control signal is not received, and second connection means for connecting said second adjustment means to said voltage divider means in response to a second control signal, said second connection means disconnecting said second adjustment means from said voltage divider means when the second control signal is not received, wherein said first and second control signals independently control said first and second connection means.