Patent ID: 7354837
Filing Date: 2008-04-08
Classification: H01L

Abstract:
1. A fabrication method for a semiconductor device, comprising: providing a substrate with an array area and a peripheral area, the array area comprising a first gate and the peripheral area comprising a second gate; forming a first isolation layer to cover the first gate, the second gate and the substrate; forming a second isolation layer to cover the first isolation layer, wherein the second isolation layer is made of a material different from the first isolation layer; removing a portion of the second isolation layer to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate; forming a photoresist layer to cover the peripheral area; removing the spacers in the array area while protecting the spacers in the peripheral area; removing the photoresist layer; and removing the first isolation layer on the top of the first gate and the surface of the substrate, thereby leaving a portion of the first isolation layer covering the sidewalls of the first gate as single-layer spacers in the array area, and removing a portion of both the spacers and the first isolation layer on the sidewalls of the second gate to form dual-layer spacers in the peripheral area.