Patent ID: 6459556
Filing Date: 2002-10-01
Classification: H03K

Abstract:
An input buffer comprising:an input terminal; a differential amplifier including a plurality of MOS transistors, said differential amplifier comprising a current mirror circuit, in that a reference voltage is applied to one side of the current mirror circuit; a protection circuit located between said input terminal and the other side of the differential amplifier, said protection circuit serving to protect a MOS transistor constituting the differential amplifier when a high voltage is applied to the input terminal; and a control transistor connected between said differential amplifier and a ground, a control signal is supplied to a gate thereof, wherein said protection circuit is an N-channel type MOS transistor of which a drain electrode is connected to said input terminal, a source electrode is connected to a gate terminal of an N-channel type MOS transistor constituting said differential amplifier, and a gate terminal is applied with a power source voltage.