Patent ID: 6532510
Filing Date: 2003-03-11
Classification: G06F

Abstract:
A computer system for processing system management interrupt (SMI) requests, comprising:a plurality of system management (SM) requesters adapted to assert SMI requestes; a processor coupled to the plurality of SM requesters, the processor being adapted to activate a system management mode in response to receiving an SMI request from at least one of the SM requesters; a system memory; and a memory controller coupled to the processor and the system memory, the memory controller including a selector component adapted to receive a mode indicator signal from the processor, the memory controller being adapted to access a first one of a plurality of SMI handler routines in the system memory in response to a first value of the mode indicator signal, the memory controller including a plurality of base address registers, each base address register storing an SMI base address corresponding to a respective one of the SMI handler routines; a memory address register block that stores an address of information that is accessed from the system memory; first and second multiplexers, the first multiplexer having a first input coupled to one of the plurality of SMI base address registers, a second input coupled to another of the SMI base address registers, and an output coupled to a first input of the second multiplexer, the second multiplexer having a second input coupled to the processor, and an output coupled to the memory address register block; and an SMI state machine coupled to the processor, the first multiplexer, and the plurality of SMI base address registers, the SMI state machine causing the first multiplexer to transmit at least one of the SMI base addresses to the second multiplexer in response to receiving from the processor the mode indicator signal having the first value, the SMI state machine further causing the second multiplexer to load into the memory address register block whichever SMI base address is output by the first multiplexer when the mode indicator signal has the first value and allowing the second multiplexer to load into the memory address register block an address from the processor when the mode indicator signal does not have the first value.