Patent ID: 7106618
Filing Date: 2006-09-12
Classification: G11C,H01L

Abstract:
1. A method of driving a non-volatile memory which comprises; a plurality of memory cells arranged in a two dimensional array, each of the memory cells having an n-channel field-effect transistor whose gate and substrate are connected electrically, and a variable resistor element comprising a phase change material and having a first terminal and a second terminal, the first terminal being connected to a source of the field-effect transistor, a word line connected to the gates of the memory cells of each line, a bit line connected to the second terminals of the memory cells of each row, and a common voltage supply section connected to drains of all the field effect transistors; the method carrying out, when a variable resistor element in a first memory cell is changed into a high resistance state, a first reset step in which an initial voltage is applied to all the word lines and a bit line connected to the first memory cell, and a first voltage which is higher than the initial voltage is applied to the voltage supply section and bit lines other than the bit line connected to the first memory cell, a second reset step in which a second voltage is applied to a word line connected to the first memory cell, the second voltage being, on the basis of the initial voltage, higher than a forward rise voltage of a pn junction of the field-effect transistor, higher than or equal to the first voltage and lower than the sum of the first voltage and the forward rise voltage, whereby a reset current is applied through a variable resistor element of the first memory cell, and a third reset step in which the initial voltage is applied to the word line connected to the first memory cell, the first to third reset steps being carried out in the order stated; the method carrying out, when a variable resistor element of a second memory cell is changed into a low resistance state, a first set step in which the initial voltage is applied to all the word lines and a bit line connected to the second memory cell, and a third voltage which is higher than the initial voltage is applied to the voltage supply section and bit lines other than the bit line connected to the second memory cell, a second set step in which a fourth voltage is applied to a word line connected to the second memory cell, the fourth voltage being, on the basis of the initial voltage, higher than a forward rise voltage of a pn junction of the field-effect transistor, higher than or equal to the third voltage and lower than the sum of the third voltage and the forward rise voltage, whereby a set current is applied through the variable resistor element of the second memory cell, and a third set step in which the initial voltage is applied to the word line connected to the second memory cell, the first to third set steps being carried out in the order stated; the method carrying out, when the state of a variable resistor element of a third memory cell is read, a first read step in which a fifth voltage is applied to a word line connected to the third memory cell to turn on a field-effect transistor of the third memory cell, and a current is applied by creating a potential difference between a bit line connected to the third memory cell and the voltage supply section, whereby a value of a current flowing through the variable resistor element of the third memory cell is detected as an amount of a current flowing through the bit line.