Patent ID: 8323989
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A method, comprising: forming a conductive layer on inner surface areas of a plurality of openings formed in a dielectric layer above a first substrate of a semiconductor device, said plurality of openings formed in a specified test area of said first substrate; forming said conductive layer on inner surface areas of a plurality of openings formed in a dielectric layer above a second substrate of a semiconductor device, said plurality of openings of said second substrate formed in a specified test area of said second substrate; exposing said first substrate comprising said conductive layer to a manufacturing environment that is established on the basis of a specific parameter setting; forming a metal region in each of said plurality of openings of said first substrate; forming a metal region in each of said plurality of openings of said second substrate substantially without exposing said second substrate to said manufacturing environment; determining a defect rate of said specified test area of said first substrate; and adjusting at least one parameter value of said specific parameter setting of said manufacturing environment on the basis of said defect rate obtained from said first substrate.