Patent ID: 6687796
Filing Date: 2004-02-03
Classification: G06F,Y02D

Abstract:
A digital system, comprising:a plurality of requestor circuits each having at least one request address output node for providing a request address and at least one request output, at least one of the plurality of requestor circuits comprises address generation circuitry for forming a sequence of request addresses as part of a single request; a port circuit with a plurality of request address input nodes connected respectively to the request address output nodes of the plurality of requester circuits, a memory address output node for providing a memory address selected from the plurality of request address output nodes, and a scheduler circuit with a plurality of request input nodes connected respectively to the request output of the plurality of requestor circuits operable to select a next request that will be served by the port, wherein after one of the sequence of request addresses from said at least one of the plurality of requestor circuits is selected the port circuitry a next sequential request address is provided to the port circuitry by the at least one requestor and wherein the port circuit is operable to select one of the plurality of request address input nodes for receiving a request address in response to the next request selected by the scheduler circuit; and a memory resource circuit coupled to receive the selected request address from memory address output node of the port circuit.