Patent ID: 6973529
Filing Date: 2005-12-06
Classification: G06F

Abstract:
1. An apparatus comprising: a main memory for storing data; one or more I/O devices for receiving data from or sending data to said main memory; a control unit for controlling said I/O devices; at least one I/O processor (IOP) for controlling I/O operations for sending data between said main memory and said I/O devices; a plurality of channels between said IOP and said control unit, said channels including multiple channel paths for carrying data between said main memory and said I/O devices during said I/O operations, said channels including at least one enterprise system connection (ESCON) channel, at least one Ficon Bridge (FCV) channel, and at least one Ficon Native channel (FC), each channel keeping a copy of channel busy data (CBD), said IOP keeping a copy of the CBD for each channel, said ESCON channel keeping a busy vector and a one deep queue full vector, said FC channel keeping DMA thresholds, number of exchanges, and queue totals; and a computer program executed by said IOP for selecting one of said channel paths as the next channel path to carry data between said main memory and said I/O devices, said computer program determining a path weight, said path weight being assigned to a path by building a path weight table, said path weight being adjusted to enable comparison between different types of channels, said path weight being based on said busy vector and said one deep queue full vector for said ESCON channel, said path weight being based on said DMA thresholds, said number of exchanges, and said queue totals for said FC channel; wherein each said channel has an affinity to one of said IOP.