Patent ID: 6937064
Filing Date: 2005-08-30
Classification: H03K

Abstract:
1. In an integrated circuit, a logic element comprising: a logic function block comprising a plurality of input terminals and an output terminal, wherein an output signal of the logic function block is output on the output terminal of the logic function block; a storage unit comprising an input terminal and an output terminal, the input terminal of the storage unit coupled to a particular one of a plurality of logic element input terminals and the output terminal of the logic function block, wherein a particular one of a plurality of logic element input signals is received on the particular one of the plurality of logic element input terminals, wherein the storage unit stores the particular one of the plurality of logic element input signals or the output signal of the logic function block; a first selection unit comprising a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to the output terminal of the storage unit, the second input terminal coupled to the particular one of the plurality of logic element input terminals, wherein the second input terminal receives the particular one of the plurality of logic element input signals, and the output terminal of the first selection unit coupled to a particular one of the plurality of input terminals of the logic function block to which the particular one of the plurality of logic element input signals is destined, wherein the first selection unit sends to the logic function block the particular one of the plurality of logic element input signals or an output signal of the storage unit; and a logic gate comprising an input terminal, and an output terminal, the input terminal of the logic gate receives a synchronous clear signal that indicates whether the storage unit is to be synchronously cleared, and the output terminal of the logic gate is selectively coupled to the storage unit.