Patent ID: 7671647
Filing Date: 2010-03-02
Classification: G11C,H03L

Abstract:
1. A clock signal generator circuit, comprising: a delay-locked loop (DLL) having a delay line providing an adjustable delay and a phase detector, the delay line operable to provide a delayed clock signal in response to an input clock signal and the phase detector operable to compare first and second signals and further operable to adjust the delay of the delay line based on the phase of the first and second signals, the delayed clock signal having a phase relative to the phase of the input clock signal that is determined by the delay line, the delayed clock signal being used to provide a feedback clock signal; a first adjustable trimming circuit having first and second adjustable delay circuits and operable to delay the input clock signal and the feedback clock signal, respectively, by respective first and second adjustable delays to provide the first and second signals to the phase detector, each of the first and second adjustable delays being set responsive to respective first and second trim control signals to provide respective delays within a range extending from a respective intrinsic delay to a respective maximum delay; and a trim decoder coupled to the first adjustable trimming circuit and being configured to be programmed to provide the first and second trim control signals to the first and second adjustable delay circuits, respectively, the trim decoder being programmed so that one of the first and second trim control signals sets its respective adjustable delay at substantially the intrinsic delay of the respective delay circuit while the other of the first and second trim control signals sets its respective adjustable delay to a delay that is less than the maximum delay of the respective delay circuit.