Patent ID: 6307403
Filing Date: 2001-10-23
Classification: H03K

Abstract:
A delay time control circuit comprising:a delay circuit composed of 2.sup.n series-connected unit delay circuits each including a pair of series-connected, first and second inverters, where n is an integer equal to or more than 2;a plurality of three-state buffer circuits each connected to a respective output of said second inverter of said unit delay circuit;connection lines for tournament-connecting said three-state buffer circuits of said unit delay circuits with using adjacent ones of said unit delay circuits as a unit and connecting an output of one of said three-state buffer circuits to an output terminal of said delay time control circuit; anda plurality of buffer circuits each connected to a respective output of said first inverter of said unit delay circuit, said buffer circuit being equivalent to said three-state buffer circuit,wherein, in response to an input signal input to said first inverter of first one of said unit delay circuits, an output signal delayed with respect to said input signal is obtained through one of said tournament connection lines.