Patent ID: 6919247
Filing Date: 2005-07-19
Classification: H01L

Abstract:
1. A method of fabricating a floating gate for a semiconductor device, said method comprising: depositing an undoped polycrystalline silicon layer on a tunnel oxide layer, wherein said undoped polycrystalline silicon layer has a first thickness; depositing a doped polycrystalline silicon layer on said undoped polycrystalline silicon layer, wherein said doped polycrystalline silicon layer has a second thickness, and wherein said undoped polycrystalline silicon layer and said doped polycrystalline silicon layer form said floating gate having a third thickness, wherein said doped polycrystalline silicon layer includes dopant material throughout said second thickness; and performing a plurality of thermal processes such that said floating gate comprises a plurality of grains, each grain being smaller than the grains of a floating gate formed using only doped polycrystalline silicon.