Patent ID: 8018783
Filing Date: 2011-09-13
Classification: H03K

Abstract:
1. A storage circuit comprising: a first switching unit that receives data and is controlled to switch between an electrically connecting state and an electrically disconnecting state according to a clock signal input to a gate terminal of the first switching unit; an inverting unit that inverts the data and outputs the inverted data; a second switching unit that receives the inverted data and is controlled simultaneously with the first switching unit to switch between the electrically connecting state and the electrically disconnecting state according to the clock signal input to a gate terminal of the second switching unit; and a latching unit that is connected to an output terminal of the first switching unit and an output terminal of the second switching unit, latches the data and the inverted data, and outputs the data and the inverted data simultaneously, wherein the latching unit includes two inverters that receive the data and the inverted data and are connected to each other to form a loop such that an input terminal of one of the inverters is connected to an output terminal of other one of the inverters and an output terminal of the one of the inverters is connected to an input terminal of the other one of the inverters, and a third switching unit that is commonly connected to ground terminals of the inverters, and grounds the ground terminals based on an inverted clock signal that is obtained by inverting the clock signal and that is input to a gate terminal of the third switching unit.