Patent ID: 6711642
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A method of system management mode interrupt for a multi-processor supporting system, wherein the multi-processor supporting system comprises a plurality of central processing units, a peripheral component interface bus, and a chipset, wherein the central processing units further comprise a first central processing unit and a second central processing unit, the method comprising:when any of the central processing units is executing a software program to access a specified IO port defined by the chipset, detecting the specified IO port and extracting a trap data to store in the chipset; enabling a system management interrupt signal by the chipset; the first and second central processing units entering a system management mode according to the system management interrupt signal; executing an operation according to the trap data of the chipset by the first central processing unit; and the first central processing unit returning to a previous state and executing a previous next command.