Patent ID: 6348375
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A method of fabricating a bit line structure for semiconductor devices, comprising:forming a first dielectric layer on a semiconductor substrate; forming a lower ARC layer on the first dielectric layer to prevent diffused reflection on a surface of the first dielectric layer; forming a first dielectric layer pattern having a first contact hole exposing the semiconductor substrate by patterning the lower ARC layer and the first dielectric layer; forming a first conductive layer for filling the first contact hole, on the lower ARC layer; forming an upper ARC layer for preventing diffused reflection on a surface of the first conductive layer, on the first conductive layer; forming a first conductive layer pattern used as a bit line by sequentially patterning the upper ARC layer, the first conductive layer, and the lower ARC layer, and upper and lower protecting film patterns which respectively comprise the upper and lower ARC layers and protect the first conductive layer pattern; forming a spacer on a sidewall of the first conductive layer pattern; and forming a second dielectric layer pattern which covers the first conductive layer pattern, is isolated from the first conductive layer pattern, and has a second contact hole for exposing the semiconductor substrate.