Patent ID: 7310399
Filing Date: 2007-12-18
Classification: G06F

Abstract:
1. High-speed serial interface receiver circuitry comprising: clock data recovery circuitry for recovering data information and clock information from a serial input data signal; deserializer circuitry for converting the recovered data information from serial to parallel form data information; byte alignment circuitry for reconstructing bytes of information in the parallel form data information; and first selection circuitry able to select a clock signal for use by the byte alignment circuitry from a plurality of clock signal sources including (1) the clock information recovered by the clock data recovery circuitry, which clock information can have any one of several different phases relative to a first reference clock signal, said one of said phases being selected by the clock data recovery circuitry based on a phase characteristic of the serial input data signal, and (2) a second reference clock signal having phase that is not determined by the clock data recovery circuitry.