Patent ID: 9059686
Filing Date: 2015-06-16
Classification: H01L,H03K

Abstract:
1. A circuit comprising: a first N-channel transistor having a source, a drain, and a gate; a second N-channel transistor having a source coupled to the source of the first N-channel transistor, a drain coupled to the gate of the first N-channel transistor, and a gate coupled to the drain of the first N-channel transistor; a third N-channel transistor having a source, a gate, and a drain coupled to the drain of the first N-channel transistor; a fourth N-channel transistor having a source coupled to the source of the first N-channel transistor, a gate, and a drain coupled to the source of the third N-channel transistor; a fifth N-channel transistor having a source, a gate, and a drain coupled to the drain of the second N-channel transistor; a sixth N-channel transistor having a source coupled to the source of the second N-channel transistor, a gate, and a drain coupled to the source of the fifth N-channel transistor; a first P-channel transistor having a source, a gate, and a drain coupled to the drain of the first N-channel transistor; a second P-channel transistor having a source coupled to the source of the first P-channel transistor, a gate coupled to the gate of the first P-channel transistor, and a drain coupled to the drain of the second N-channel transistor; a clock signal input conductor, wherein the gates of the third and fifth N-channel transistors are coupled to the clock signal input conductor; and an inverted clock signal input conductor, wherein the gates of the first and second P-channel transistors are coupled to the inverted clock signal input conductor.