Patent ID: 6482659
Filing Date: 2002-11-19
Classification: H01L,Y10S

Abstract:
A method for reducing the size of microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate, the method comprising:providing a semiconductor wafer; depositing an epitaxial layer on a surface of said semiconductor wafer, wherein during the deposition of the epitaxial layer, microsteps are formed on an exposed surface of said epitaxial layer; forming a boundary interface within said deposited epitaxial layer by thermal oxidizing at least a portion of the epitaxial layer of said semiconductor wafer including at least a portion of said exposed surface defining said microsteps, wherein said boundary interface being defined as an interface between said oxidized portion of said epitaxial layer and a portion of said epitaxial layer not oxidized, said boundary interface being relatively smoother than said exposed surface of said deposited epitaxial layer; and removing said microsteps by substantially removing the oxidized top portion of said epitaxial layer, wherein said relatively smoother boundary interface is exposed as a surface of said epitaxial layer.