Patent ID: 9015558
Filing Date: 2015-04-21
Classification: G06F,G11C,H03M

Abstract:
1. A memory system, comprising: a plurality of RAM chips; a memory buffer arranged to buffer n-bit data and/or command words being written to or read from said plurality of RAM chips by a host controller; an address match table which stores the addresses of faulty storage cells within said RAM chips; memory storage devices embedded within said memory buffer and distinct from said RAM chips; a plurality of bi-directional multiplexers which convey data words from said host controller to said embedded memory storage devices or said RAM chips when a write operation is performed, and from said embedded memory storage devices or said RAM chips to said host controller when a read operation is performed, each of said embedded memory storage devices connected to a respective one of said bi-directional multiplexers; said address match table arranged to: