Patent ID: 6242340
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A method of forming an interconnection in a semiconductor device, comprising:forming a first insulation layer on a semiconductor substrate;forming a first trench in the first insulation layer;forming a first interconnection layer in the first trench;forming a second insulation layer on the first insulation layer and the first interconnection layer;forming a third insulation layer on the second insulation layer;forming a fourth insulation layer on the third insulation layer;forming a second trench in the third and fourth insulation layers;forming a sidewall spacer on sidewalls of the second trench;removing a portion of the second insulation layer exposed by the second trench; andforming a second interconnection layer in the second trench by:forming a second metal layer comprising copper on an upper portion of the fourth insulation layer and in the second trench so that the second trench is filled with the second metal layer; andremoving portions of the second metal layer so that the upper portion of the fourth insulation layer is exposed, wherein the step of forming the sidewall spacer comprises:forming a second barrier metal layer on an upper portion of the fourth insulation layer and in the second trench; andremoving the second barrier metal layer by anisotropic etching so that the upper portion of the fourth insulation layer is exposed, the second barrier metal layer being selected from the group consisting TiN, Ta, TaN and WNx.