Patent ID: 8293644
Filing Date: 2012-10-23
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, the method comprising: forming a first insulation layer over a semiconductor substrate in which a first region and a second region are defined; forming a bit line contact over the second region through the first insulation layer; forming a second insulation layer over the first insulation layer and the bit line contact; patterning the second insulation layer and the first insulation layer such that the first region is exposed; depositing a first conductive layer on the exposed first region and the second insulation layer; forming a storage node contact (SNC) electrically connected to the first region by removing an upper portion of the first conductive layer such that the second insulation layer is exposed; patterning the second insulation layer such that the bit line contact is exposed; depositing a second conductive layer over the exposed bit line contact, the SNC and the second insulation layer; and forming a bit line, electrically connected to the second region through the bit line contact, by removing an upper portion of the second conductive layer such that the SNC and the second insulation layer are exposed; wherein the upper portion of the second conductive layer is removed using a chemical mechanical polishing (CMP) process; and wherein an upper portion of the SNC and an upper portion of the second insulation layer are removed by using the CMP process such that remaining parts of the SNC and the second conductive layer are electrically separated from each other.