Patent ID: 8627140
Filing Date: 2014-01-07
Classification: G06F

Abstract:
1. A failure management method for a computer including a processor, and a memory connected to the processor, the processor having a memory protection function to prohibit access to a specified address in the memory, and operating a first software program stored in the memory and a second software program stored in the memory to monitor operation of the first software program, and the second software program retaining error information including address information on the memory address where the error occurred, and access-related information on the access state of the address, the method comprising the steps of: (1) detecting, by the second software program, an error occurring in the memory; (2) adding, by the second software program, the memory address where the error occurred to the error information; (3) prohibiting, by the second software program, access to the memory where the error occurred by changing the settings on the memory protection function, and monitoring the access state to the memory address where the error occurred; (4) executing, by the second software program, failure processing when access is detected by the first software program to the memory address where the error occurred, wherein the step (4) further includes the steps of: (5) deciding whether or not the access to the memory address where the error occurred by the first software program is reading out the memory address where the error occurred, or is writing in the memory address where the error occurred; and (6) deciding the access state of the address detected in the reading out by the first software program based on the error information when the access by the first software program is reading out the memory address where the error occurred; and (7) executing the failure processing based on the decision results.