Patent ID: 8086990
Filing Date: 2011-12-27
Classification: G06F

Abstract:
1. A method for implementing a circuit, comprising steps of: determining a relationship between values for a first performance measure as generated by a first, stress-sensitive, transistor model, and values for a set of transistor instance parameters applicable to a second, stress-insensitive, transistor model, such that for layout characteristics of at least a subset of transistors, application of the transistor instance parameter values to the second, stress-insensitive, transistor model yields substantially the same value for a second performance measure as does the first, stress-sensitive, transistor model; for each particular transistor in a plurality of transistors in a layout of a circuit design, using a substitute stress analyzer on a computer to determine a value for the first performance measure in dependence upon the layout characteristics of the particular transistor; in dependence upon the relationship, using a computer to convert the first performance measure values determined for each transistor in the plurality of transistors to a corresponding set of transistor instance parameter values; using a computer, simulating an aspect of the circuit design using the second, stress-insensitive, transistor model for each given transistor in the plurality of transistors, in dependence upon the set of transistor instance parameter values obtained for the given transistor; and revising the layout in dependence upon a simulation performed in the step of simulating.