Patent ID: 6822919
Filing Date: 2004-11-23
Classification: G11C

Abstract:
A sense amplifier circuit for a memory cell comprising:a sense amplifier operable to be coupled to a memory cell via data lines and operable to amplify data, and further comprising read bus complement and read bus true lines and a data-line drive having a global data-bus line (GDB) and data output and coupled to the sense amplifier and operable to couple amplified data as a data output signal on the global data-bus line during a read cycle, and operatively connected to at least one of said read bus complement and read bus true lines through which a data output signal is output; an equalization circuit coupled to the sense amplifier and operable to receive an equalization signal to equalize the sense amplifier; an enable circuit coupled to the sense amplifier and operable to receive an enable signal to enable the sense amplifier to amplify data; and a control circuit operable for disconnecting the output from one of the read bus complement and read bus true lines when the sense amplifier is equalized to minimize unwanted transitions of the data output signal, said control circuit including a latch circuit that stores data when the enable signal is LOW and ensures that data is always drive onto the global data-bus line and data output, wherein during equalization or WRITE phase when the enable signal becomes LOW, the latch circuit is disconnected and prevents passage of unwanted transition of the latch circuit onto the data output of the global data-bus line.