Patent ID: 8954711
Filing Date: 2015-02-10
Classification: G06F

Abstract:
1. A data processing apparatus comprising: processing circuitry for processing data; an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said data processing; wherein said program instructions comprise an address calculating instruction having an instruction size, said processing circuitry being responsive to said address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value, wherein said processing circuitry is configured to calculate a full address specifying a memory location of an information entity from said partial address result using at least one supplementary program instruction and wherein said partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction, wherein said program instructions comprise said at least one supplementary program instruction such that said full address is obtained by execution of a set comprising at least two program instructions comprising said address calculating instruction and said at least one supplementary program instruction, wherein said full address is specified by a full offset value and said non-fixed reference address and wherein said at least one supplementary instruction provides a supplementary offset value such that said partial offset value and said supplementary offset value together specify said full offset value.