Patent ID: 6141277
Filing Date: 2000-10-31
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory cores each having at least one memory cell array composed of a plurality of memory cells, a plurality of word lines connected to the memory cells, a plurality of bit lines connected to the memory cells, a data line, and a column gate circuit for selectively connecting the bit lines to the data line, the memory cores being selected one at a time to read data from a selected memory cell;a sense amplifier having first and second input nodes for amplifying a potential difference between the first and second input nodes to sense data; anda data line switch circuit for connecting the data line associated with a selected one of the memory cores to the first input node of the sense amplifier and connecting the data line associated with a non-selected one of the memory cores to the second input node of the sense amplifier, wherein the load capacitances on the first input node and the second input node are substantially equal to each other during a read operation.