Patent ID: 7734000
Filing Date: 2010-06-08
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit receiving an input signal and outputting an output signal in phase with the input signal, comprising: a phase detection circuit estimating a significant transition of the input signal and outputting a first detection signal; a first oscillator receiving the first detection signal and outputting a first clock, wherein the first oscillator operates in a first mode during a first period and sequentially in second and synchronization modes during a second period; a second oscillator receiving the first detection signal and outputting a second clock, wherein the second oscillator operates sequentially in the second and synchronization modes during the first period and operates in the first mode during the second period; and a flip-flop receiving the input signal and outputting the output signal according to the first and second clocks respectively during the first and second periods, wherein the first oscillator comprises: a first multiplexer receiving the first clock and the first detection signal and controlled by a first select signal; a first delay unit coupled to an output terminal of the first multiplexer; a second multiplexer receiving the second clock and a signal output from the first delay unit and controlled by a second select signal; and a second delay unit coupled to an output terminal of the second multiplexer and outputting the first clock, wherein when the first oscillator operates in the first mode, the first multiplexer transmits the first clock to the first delay unit according to the first select signal at a first level or transmits the first detection signal to the first delay unit according to the first select signal at a second level; and wherein when the first oscillator operates in the first mode, the second multiplexer transmits the signal output from the first delay unit to the second delay according to the second select signal.