Patent ID: 8908447
Filing Date: 2014-12-09
Classification: G11C

Abstract:
1. A semiconductor device, comprising: a memory cell array configured to comprise a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines; a bit line sense amplifier (BLSA) connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment input/output (I/O) line; a control signal generator configured to output an I/O switch control signal in response to a pre-switching control signal and a level detection signal determined by a level of a power source voltage; and a local sense amplifier (LSA) connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line, wherein the pre-switching control signal is configured to have a predetermined level when a read operation is performed, and the control signal generator is configured to output the I/O switch control signal regardless of a level of the pre-switching control signal.