Patent ID: 6201277
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A programmable memory device having a memory array formed in a semiconductor body including a plurality of memory cells arranged into rows and columns comprising:a plurality of parallel and spaced apart slot trenches, said slot trenches formed in sequences between said columns, said slot trenches located at the crossings of diagonals with respect to said rows and columns, each of said slot trenches extending below said surface of said semiconductor body between said columns;a plurality of floating gates formed on a surface of said semiconductor body but separated from said surface of said semiconductor body by a gate dielectric, said floating gates positioned between said slot trenches;a plurality of control gates, each of said control gates extending over at least one of said floating gates and a portion of said slot trenches, said control gates running perpendicular to said slot trenches and parallel to each other, exactly two of said control gates running over each of said slot trenches away from the periphery of the array of said rows and columns of memory cells; anda plurality of source/drain regions formed in said semiconductor body between said control gates and between said slot trenches.