Patent ID: 6507936
Filing Date: 2003-01-14
Classification: G06F

Abstract:
A timing verifying method for verifying an operational timing of a semiconductor integrated circuit composed of a plurality of cells having logic functions, the plurality of cells being placed in the semiconductor integrated circuit and having respective terminals connected by wires, the method comprising:a variation delay time calculating step of calculating at least two variation delay times by performing at least twice each of a first sub-step of setting, for a process varying factor which is determined by a process for fabricating the semiconductor integrated circuit and which varies at least one of resistance of each of the wires and capacitance between each of the wires and the wire adjacent thereto, an amount of process variation which is an amount of variation caused in the process varying factor, a second sub-step of calculating the resistance of the wire and the capacitance between the wires based on the amount of process variation and on a layout configuration of the wires, and a third sub-step of calculating a first delay time in the wire and a second delay time in the driving cell of the plurality of cells which drives the wire by using the resistance of the wire and the capacitance between the wires that have been calculated, while varying the amount of process variation, each of the at least two variation delay times being composed of the first delay time and the second delay time; a delay data synthesizing step of generating a synthesized delay time which determines operation characteristics of the semiconductor integrated circuit based on the at least two variation delay times; and a logic simulation step of performing logic simulation of the semiconductor integrated circuit by using the synthesized delay time.