Patent ID: 8836408
Filing Date: 2014-09-16
Classification: H03K

Abstract:
1. A signal switching circuit comprising: a data link having a primary channel switchably connectable between at least two secondary channels; a FET-based switch including a FET transistor having gate, back-gate, source and drain terminals, the FET-based switch being configured and arranged to respond to control signals at the gate terminal to operate in a signal-passing mode in which an AC signal is passed between the source and drain terminals by coupling a first portion of a signal between the source and drain terminals and another portion of the AC signal is diverted due to AC-coupling across inherent capacitances associated with the FET-based switch, and to operate in another mode in which passage of the signal between the source and drain terminals is substantially blocked; and a biasing circuit configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal and therein offset loading caused by the inherent capacitances associated with the FET-based switch.