Patent ID: 8448107
Filing Date: 2013-05-21
Classification: G06F

Abstract:
1. A method for performing sequential logical formal verification of integrated circuit IC designs using a piecewise hierarchical approach, the method comprising: providing a reference IC design; providing a modified IC design that includes logic edits relative to said reference IC design; a computer performing sequential logical formal verification of logic between said reference IC design and said modified IC design with all of said logic edits disabled; creating groups of logic edits from said logic edits in said modified IC design; discovering dependencies between said logic edits in said modified IC design; ordering said groups of logic edits based upon said dependencies; checking that said ordering of said groups of logic edits obeys said dependencies between said one or more logic edits in said modified IC design; the computer performing sequential logical formal verification of logic independently on each of said groups of logic edits in accordance with said ordering; and tracking a validation status of said sequential logical formal verification of said logic edits.