Patent ID: 8487656
Filing Date: 2013-07-16
Classification: H03K

Abstract:
1. A dynamic logic circuit, comprising: an N channel transistor stack between a dynamic node and a first power supply terminal for receiving a plurality of logic signals; a P channel clock transistor coupled between a second power supply terminal and the dynamic node for receiving a clock signal; an N channel clock transistor in series with the N channel transistor stack and between the dynamic node and the first power supply terminal for receiving the clock signal; an inverter circuit having an input coupled to the dynamic node and an output; a keeper transistor having a control electrode coupled to the output of the inverter circuit, a first current electrode coupled to the dynamic node, and a second current electrode; and a plurality of P channel transistors in parallel coupled between the second current electrode of the keeper transistor and the second power supply terminal, wherein the plurality of P channel transistors are for receiving the plurality of logic signals.