Patent ID: 6625240
Filing Date: 2003-09-23
Classification: H04J

Abstract:
An alignment/frame synchronization apparatus comprising:frequency-dividing means for frequency-dividing a first clock to generate a second clock; data width extension means for extending eight input data into 16 output data E[1:16] in accordance with the first clock; byte alignment means for generating byte signals E[m:m+7] (m=integers of 1 to 8) from the output signals E[1:16] from said data width extension means, and byte-aligning the output signals E[1:16] from said data width extension means on the basis of a byte alignment control signal; control means for outputting byte alignment control signals to said byte alignment means in correspondence with the byte signals [m:m+7] in accordance with detection of A1A1 patterns and A2A2 patterns for the respective byte signals [m:m+7] from said byte alignment means, and outputting an A1/A2 consecutive pattern signal indicating that a predetermined number of A1 and A2 frame patterns are consecutively received; frame pulse generating means for generating a frame pulse signal in synchronism with the second clock when an A2 frame pattern is consecutively received following an A1 frame pattern on the basis of the A1/A2 consecutive pattern signal output from said control means; frame sync detection means for generating a frame sync signal in synchronism with the second clock when the frame pulse signal output from said frame pulse generating means is consecutively received a first predetermined number of times; frame sync loss detection means for outputting a frame sync loss signal when the frame sync signal output from said frame sync detection means is not consecutively received a second predetermined number of times; and frame sync error detection means for outputting a frame sync error signal in synchronism with the second clock when it is detected that the frame sync loss signal output from said frame sync loss detection means is maintained for a predetermined period of time.