Patent ID: 7482208
Filing Date: 2009-01-27
Classification: G02F,H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel comprising: forming a gate line including a gate electrode on an insulating substrate; forming a gate insulating layer coveting the gate line; forming a semiconductor on the gate insulating layer; forming a data line including a source electrode and intersecting the gate line and a drain electrode separated from and opposite to the source electrode with respect to the gate electrode; depositing a passivation layer; patterning the passivation layer along with the gate insulating layer to form contact holes exposing an expansions of the gate line and the data line and the drain electrode; depositing IZO layer and ITO layer in sequence; and photo-etching the IZO layer and ITO layer to form a pixel electrode and contact assistants respectively connected to the drain electrode and the expansions of the gate line and the data line, wherein the IZO layer and the ITO layer are etched by an IZO etchant containing HCl, CH