Patent ID: 7642856
Filing Date: 2010-01-05
Classification: H03F

Abstract:
1. An amplifier receiving a power supply voltage that is greater than all breakdown voltages of a process associated with transistors of the amplifier, the amplifier comprising: a plurality of transistor pairs, each transistor pair having an at-risk transistor and a corresponding compensation transistor, the plurality of transistor pairs having a cascoded configuration; a bias shunt for isolating a plurality of nodes of the amplifier from a low voltage source and a power supply voltage source during a power down mode; a charge circuit for charging the plurality of nodes to a predetermined voltage during the power down mode, thereby minimizing stress to the at-risk transistors during the power down mode; and a multi-flavor power down signal generator circuit for generating bias flavor power down signals, the bias flavor power down signals for driving various transistors of the amplifier during the power down mode.