Patent ID: 6523145
Filing Date: 2003-02-18
Classification: G11C

Abstract:
A method for testing a circuit comprising combinational logic and an array, wherein the array comprises a plurality of bit cells and a plurality of logic cells, wherein each logic cell is uniquely associated with a bit cell such that an output of a bit cell provides an input to a logic cell, wherein each set of logic cells for an address of the array provides an output data-vector from the array, wherein each cone of logic in the combinational logic receives an output data vector from an associated address in the array as an input data vector, and wherein each cone of logic in the combinational logic is independent from other cones of logic in the combinational logic, the method comprising the steps of:inputting a test vector at a write port of the array; inputting a set of logic cell input values into the array; and asserting simultaneously all write wordline signals of the array associated with the write port in order to write the test vector to all addresses of the array.