Patent ID: 8020142
Filing Date: 2011-09-13
Classification: G06F

Abstract:
1. A method comprising: adding, by an adder/subtractor, a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit; loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand; performing a single bit shift on the third operand by a shifter unit to produce a shifted operand wherein a mode of the shifter unit is set by control circuitry, the mode corresponding to one of a left shift and a right shift and a right shift corresponds to dividing the third operand by two; loading the shifted operand into the fourth register; loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand; generating a greatest common divisor (GCD) of the first and second operands using the fourth operand; and generating a public key, based on, at least in part, the GCD.