Patent ID: 6617882
Filing Date: 2003-09-09
Classification: H03K

Abstract:
A cascaded chain of clocked half-rail differential logic circuits, said chain comprising:a first clock d half-rail differential logic circuit, said first clocked half-rail differential logic circuit comprising: a first locked half-rail differential logic circuit clock input terminal; at least one first clocked half-rail differential logic circuit data input terminal; and at least one first clocked half-rail differential logic circuit data output terminal; a second clocked half-rail differential logic circuit, said second clocked half-rail differential logic circuit comprising: a second clocked half-rail differential logic circuit clock input terminal; at least one second clocked half-rail differential logic circuit data input terminal; and at least one second clocked half-rail differential logic circuit data output terminal; a third clock d half-rail differential logic circuit, said third clocked half-rail differential logic circuit comprising: a third clocked half-rail differential logic circuit lock input terminal; at east one third clocked half-rail differential logic circuit data input terminal; and at east one third clocked half-rail differential logic circuit data output terminal; a first clock signal coupled to said first clocked half-rail differential logic circuit clock input terminal; a second clock signal coupled to said second clocked half-rail differential logic circuit clock input terminal; a third clock signal coupled to said third clocked half-rail differential logic circuit clock input terminal, wherein; said at least one first clocked half-rail differential logic circuit data output terminal is coupled to said at least one second clocked half-rail differential logic circuit data input terminal, further wherein; said at least one second clocked half-rail differential logic circuit data output terminal is coupled to said at least one third clocked half-rail differential logic circuit data input terminal, further wherein; said second lock signal is delayed with respect to said first clock signal by a predetermined delay time, further wherein; â€ƒsaid third clock signal is delayed with respect to said second clock signal by a predetermined delay time; â€ƒa first delay circuit coupled between said first clocked half-rail differential logic circuit clock input terminal and said second clock d half-rail differential logic circuit clock input terminal for providing said predetermined delay time; and â€ƒa second delay circuit coupled between said second clocked half-rail differential logic circuit clock input terminal and said third clocked half-rail differential logic circuit clock input terminal for providing said predetermined delay time.