Patent ID: 8236679
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor memory device, comprising: forming a first gate electrode having a charge storage layer, a block layer, and a control gate electrode on a first region of a semiconductor substrate via a first gate insulating film; forming a second gate electrode on a second region of the semiconductor substrate via a second gate insulating film; forming a protective insulating film on side and upper surfaces of the first gate electrode, and on side and upper surfaces of the second gate electrode, by using a high temperature oxidation (HTO) method or an atomic layer deposition (ALD) method; forming a photoresist to cover the protective insulating film in the second region while exposing the protective insulating film in the first region; using the photoresist and the first gate electrode as masks to implant an impurity into the first region of the semiconductor substrate; removing the photoresist by wet etching which uses a mixed solution containing H after removing the photoresist, removing the protective insulating film on the upper surface of the first gate electrode and the upper surface of the second gate electrode, while the protective insulating film on the side surface of the first gate electrode and on the side surface of the second gate electrode remain; and after removing the photoresist, forming side walls on the side surface of the first gate electrode, and on the side surface of the second gate electrode via the protective insulating film, wherein the protective insulating film has an etching selective ratio of 1:100 or above with respect to the photoresist under wet etching conditions using the mixed solution, and the block layer is one of a high-dielectric-constant film having a higher dielectric constant than a silicon oxide film and a laminated film including the silicon oxide film and the high-dielectric-constant film.