Patent ID: 7741178
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A method of fabricating a vertical channel transistor in a semiconductor device, the method comprising: forming a plurality of pillars arranged in rows and columns respectively in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon; forming a bit line region in the substrate between the adjacent pillars; forming a first sidewall insulation layer over a first resulting structure including the pillars to cover tops and sidewalls of the pillars; filling an insulation layer in a space between the adjacent pillars; forming a mask pattern over a second resulting structure including the insulation layer; etching the insulation layer and the substrate using the mask pattern as an etch barrier to form a trench, between the adjacent rows of the pillars arranged in the first direction, for defining a bit line in the substrate; and forming a second sidewall insulation layer over a third resulting structure including the trench to cover (i) the first sidewall insulation layer on the tops of the pillars and (ii) sidewalls of the trench.