Patent ID: 6374337
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A nonvolatile memory control circuit for controlling reading and writing operations to and from a nonvolatile memory array, comprising:a set of page registers having at least a first page register and a second page register for buffering data that is to be written to or read from a nonvolatile memory array; said control circuit for receiving commands to operate said set of page registers for reading from and writing to said nonvolatile memory array; a set of address latches coupled to the nonvolatile memory array, said set of address latches having at least a first address latch for receiving data addresses for addressing the nonvolatile memory array; a state machine for operating said set of page registers and said address latches; an address decoder for receiving and decoding data addresses to the nonvolatile memory array; a state machine control logic for operating said machine in response to received commands; and wherein during a current write command, data corresponding to the current write command is stored in said second page register while data corresponding to a previous write command is stored in the nonvolatile memory array from the first page register thereby creating a pipe-lining affect so as to expedite the performance of write operations to the nonvolatile memory array.