Patent ID: 8958254
Filing Date: 2015-02-17
Classification: G11C

Abstract:
1. An 8T memory bit cell for connection to receive a clock signal and read and write address signals, comprising: a read word line; a write word line; a read address latch/clock circuit for receiving said clock signal and said read address signals to initiate a read operation during a first clock cycle state; a write address flip-flop/clock circuit for receiving said clock signal and said write address signals to initiate a write operation during a second clock cycle state; and an inverter for receiving and inverting said clock signal and for applying said inverted clock signal to said write address flip-flop/clock circuit; wherein said read address latch/clock circuit initiates a read word line precharge operation during said second clock cycle state and write address flip-flop/clock circuit initiates a write word line precharge operation during said first clock cycle state.