Patent ID: 6682982
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A method of forming a cell memory structure, comprising the steps of:providing a substrate having an isolation trench formed therein; forming an isolation structure within the isolation trench; forming a pad oxide layer over the substrate and the isolation structure; forming a first dielectric layer over the pad oxide layer; patterning the first dielectric layer, the pad oxide layer and the isolation structure to form at least: a) an initial node within the isolation trench; a portion of the initial node having an overlying patterned pad oxide layer portion and an overlying patterned first dielectric layer portion; and b) patterned first dielectric portions having underlying pad oxide layer portions over the substrate adjacent the isolation trench; forming a bottom plate electrode layer over the initial node, the substrate and the patterned first dielectric layer portions over the substrate; removing a portion of the bottom plate electrode layer, leaving a partially removed bottom plate electrode layer overlying at least the isolation trench, the initial node and any exposed substrate adjacent the isolation trench; forming a planarized second dielectric layer over the structure at least filling isolation trench and overlying the initial node and the patterned first dielectric layer portions over the substrate; removing a portion of the planarized second dielectric layer leaving only recessed portions of the second dielectric layer within isolation trench; removing: i) a portion of the bottom plate electrode layer overlying the initial node adjacent the patterned first dielectric layer portion, leaving a portion of the initial node exposed; and ii) the patterned first dielectric layer portion from the initial node; removing the second dielectric layer recessed portions, the patterned pad oxide layer portion overlying the initial node and the exposed portion of the initial node to leave a final node; forming a cap dielectric layer over the structure; forming a top plate dielectric layer over the cap dielectric layer and at least filling the isolation trench, overlying the final node and the patterned first dielectric layer portions over the substrate; planarizing the top plate dielectric layer, stopping on the patterned first dielectric layer portions over the substrate; forming an ARC layer over the planarized top plate dielectric layer; patterning: I) the ARC layer; and II) the patterned first dielectric layer portions over the substrate to expose side walls, stopping on the underlying pad oxide layer portions; forming sidewall spacers on the exposed side walls of the twice patterned first dielectric layer portions over the substrate, leaving peripheral portions of the underlying pad oxide layer exposed; and removing the peripheral exposed portions of the underlying pad oxide layer to leave remaining pad oxide layer portions and forming the cell memory structure.