Patent ID: 7346876
Filing Date: 2008-03-18
Classification: G09G,H04N

Abstract:
1. An integrated circuit, comprising: a substantially non-customizable hardware portion; a mask-programmable gate array portion; and interface circuitry capable of supplying, in a test mode, a first signal output from a source in the substantially non-customizable hardware portion to a first interface cell, the interface circuitry also being capable of supplying, in the test mode, a second signal received on a second interface cell to a destination in the substantially non-customizable hardware portion, the interface circuitry also being capable of supplying, in a normal operation mode, a third signal output from the source to the mask-programmable gate array portion, the interface circuitry also being capable of supplying, in the normal operation mode, a fourth signal output from the mask-programmable gate array portion to the destination, wherein the source outputs only a single signal at a time, and wherein the destination only receives a single signal at a time.