Patent ID: 6613624
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A method for fabricating an integrated semiconductor circuit, which comprises:depositing a first layer sequence onto a semiconductor substrate, the first layer sequence having a bottommost layer composed of an oxidizable material; patterning the first layer sequence by anisotropic etching in a first area region of the semiconductor substrate to form first gate structures having sidewalls and top sides, surfaces of the semiconductor substrate lying parallel to the top sides being defined between the gate structures, and removing the first layer sequence in a second area region of the semiconductor substrate; oxidizing the bottommost layer of the first layer sequence at the sidewalls of the first gate structures in the first area region; covering, in the first area region, at least the top sides of the first gate structures and the surfaces of the semiconductor substrate with an etch stop layer; covering the first gate structures of the first area region by depositing a second layer sequence onto the semiconductor substrate; patterning the second layer sequence by anisotropic etching of the second layer sequence to form second gate structures in the second area region and removing the second layer sequence from the first gate structures in the first area region, and stopping the removing of the second layer sequence in the first area region with the etch stop layer.