Patent ID: 7733159
Filing Date: 2010-06-08
Classification: H03K

Abstract:
1. An integrated circuit comprising: a pull-up MOS transistor having a source terminal coupled to a first supply voltage and a drain terminal coupled to an input/output pad; a pull-down MOS transistor having a drain terminal coupled to the input/output pad and a source terminal coupled to a second supply voltage that is lower than the first supply voltage; a first MOS transistor having a source terminal coupled to the first supply voltage and a bulk terminal coupled to the bulk terminal of the pull-up MOS transistor; an active diode having a first terminal coupled to the drain terminal of the first MOS transistor, and a second terminal coupled to the input/output pad; and a biasing circuit coupled between the input/out pad and the first supply voltage and adapted to apply to bulk terminals of the pull-up MOS transistor and the first MOS transistor the higher of a voltage applied to the input/output pad and the first supply voltage.