Patent ID: 6294806
Filing Date: 2001-09-25
Classification: H01L,Y10S

Abstract:
A SOI semiconductor device comprising:a semiconductor substrate having first and second surfaces opposing each other, the first surface having an active region and an inactive region, said active region including at least a pair of source/drain regions;a first gate electrode formed on the first surface of the substrate between the at least a pair of source/drain regions;a first insulating layer formed on the first gate electrode and the first surface of the substrate;a capacitor formed on the first insulating layer and being electrically connected to one of the at least a pair of source/drain regions;a second insulating layer formed on the capacitor and the first insulating layer;a third insulating layer formed on the second surface of the substrate;a body contact conductor line formed on and through the third insulating layer in alignment with the first gate electrode and being electrically connected to the active region of the substrate aligned with the first gate electrode between the at least a pair of source/drain regions;a fourth insulating layer formed on the body contact conductor line and the third insulating layer; anda bit line formed on the fourth insulating layer and being electrically connected to one of the at least a pair of source/drain regions of the substrate.