Patent ID: 6770492
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A manufacturing method of a semiconductor integrated circuit device having an MISFET formed on a main surface of a semiconductor substrate, and a capacitor electrically connected in series to said MISFET said method comprising the steps of:(a) forming the MISFET on the main surface of said semiconductor substrate; (b) forming a first insulating film on an upper portion of said MISFET; and (c) forming, on an upper portion of said first insulating film, the capacitor constituted a lower electrode, a capacitive insulating film, and an upper electrode; a first shielding film covering an upper side of said upper electrode: and a second shielding film covering a lower side of said lower electrode, wherein each of said first and second shielding films and the capacitive insulating film of said capacitor contains lead as a component, and wherein a lead composition ratio of each of said first and second shielding films is equal to or higher than that of said capacitive insulating film.