Patent ID: 6580176
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A multilayer wiring structure of a semiconductor device comprising:a substrate; two or more wiring layers formed on said substrate; an upper plug for electrically connecting a wiring formed at one of said wiring layers to the upper wiring layer; and a lower plug opposite to said upper plug with said wiring interposed, for electrically connecting said wiring to the lower wiring layer or to said substrate, and wherein a first cap metal layer is formed on the upper surface of said wiring and a second cap metal layer is formed on the lower surface of said wiring, wherein said upper plug is sunk into said wiring so that said first cap metal layer is not interposed between said upper plug and said wiring, wherein a third cap metal layer surrounds both the side and the bottom surfaces of said upper plug, wherein said wiring has a portion covered by said second cap metal layer and extending into said lower plug, wherein the sunk portion of said upper plug and the extending portion of said wiring have heights greater than zero and approximately &frac13; or less of the diameter of each of said upper and lower plugs, and wherein said wiring has no grain boundary in the region between said opposite upper and lower plugs.