Patent ID: 6703638
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A depletion/enhancement PHEMT device structure comprising:a semiconductor substrate; a buffer region comprising one or more semiconductor buffer layers over said substrate; a III-V semiconductor channel layer over said buffer region; an electron donor layer over said channel layer; a GaAs or AIGaAs first schottky layer over said electron donor layer; a first InGaP etch stop layer over said first schottky layer; a GaAs or AIGaAs second schottky layer over said first InGaP etch stop layer, said first InGaP etch stop layer acting as an etch stop for said second schottky layer; a second InGaP etch stop layer over said second schottky layer; a doped GaAs contact layer over said second InGaP etch stop layer, said second InGaP etch stop layer acting as an etch stop for said contact layer; an isolation structure extending from an upper surface of said contact layer at least to said buffer region, said isolation structure defining a first active region and a second active region; an enhancement ohmic source contact and an enhancement ohmic drain contact disposed on said doped GaAs contact layer within said first active region; an enhancement gate recess extending from an upper surface of said contact layer and through said first InGaP etch stop layer within said first active region; an enhancement gate contact disposed over said first schottky layer within said enhancement gate recess; a depletion ohmic source contact and a depletion ohmic drain contact disposed on said doped GaAs contact layer within said second active region; a depletion gate recess extending from an upper surface of said contact layer and through said second InGaP etch stop layer within said second active region; a depletion gate contact disposed over said second schottky layer within said depletion gate recess.