Patent ID: 6152612
Filing Date: 2000-11-28
Classification: G06F,Y10S

Abstract:
An application program interface for providing a C++ programming framework for simulating a circuit design within a computer system, said computer system having a processor coupled to a bus and a memory unit coupled to said bus, said interface realized as instructions stored in said memory unit and executed by said processor, said interface comprising:a) a C++ base class inherited by a plurality of C++ user processes that model the circuit behavior of said circuit design, wherein said C++ base class encapsulates data structures and methods but has no circuit behavior of its own and comprises:1) a scheduler for scheduling said plurality of C++ user processes for execution, said scheduler simulating concurrency of operation of circuits of said circuit design; and2) a reactivity model for allowing said plurality of C++ user processes to react to events represented as signals;b) a clock interface in C++ for defining clock objects upon which said plurality of C++ user processes are synchronized; andc) a multi-valued logic interface in C++ wherein signal values of: logical high (""1""); logical low (""0""); and high impedance; are represented by multi-value logic values, said multi-valued logic interface for AND, OR, XOR and NOT functions on multi-valued logic values.