Patent ID: 6559666
Filing Date: 2003-05-06
Classification: G01R,H01L,H05K

Abstract:
A method of testing a semiconductor chip using a separable connection, comprising the steps of:providing a semiconductor chip having contact pads located in an arrangement on a surface of the semiconductor chip; providing a test substrate having conductive test pads located on a surface of the test substrate in a mirror image pattern corresponding to the arrangement of the contact pads; placing an interposer between the semiconductor chip and the test substrate, the interposer having vias located through the interposer in a pattern corresponding to the arrangement of the contact pads and of the test pads with an electrically conductive adhesive material filling the vias; moving the semiconductor chip and the test substrate together, aligning the electrically conductive adhesive with the test pads and with the contact pads; testing the semiconductor chip; separating the semiconductor chip and the test substrate, and separating the electrically conductive adhesive material from the test pads and the contact pads.