Patent ID: 7987306
Filing Date: 2011-07-26
Classification: G06F,H04L

Abstract:
1. A method for addressing system latency within a network system, comprising: providing a network interface, the network interface including a plurality of direct memory access (DMA) channels, wherein each of the DMA channels is configured to transfer data between the network interface and a main system memory; and, moving data within each of the plurality of direct memory access channels independently and in parallel to and from the main system memory so that one or more of the plurality of direct memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests, wherein the data is moved within each of the plurality of DMA channels independent and parallel with respect to each of the other ones of the plurality of DMA channels; wherein the plurality of memory access channels include a plurality of receive memory access channels dedicated to moving data between the network interface and the memory system, wherein each of the plurality of receive memory access channels includes a receive descriptor ring.