Patent ID: 6441439
Filing Date: 2002-08-27
Classification: H01L

Abstract:
An electrostatic discharge (ESD) protection device to protect semiconductor devices against high-voltage transients due to electrostatic discharge, comprising:(a) an N-type well formed in a P-type substrate; (b) a plurality of first P+ regions formed in said P-type substrate; wherein each of said first P+ regions is connected to an input pad and all of said plurality of said first P+ regions are formed inside said N-type well; (c) a plurality of second P+ regions formed in said P-type substrate, wherein each of said second P+ regions is connected to said ground, at least one of said second P+ regions is outside said N-type well, and at least one of said second P+ regions is disposed either inside said N-type well or outside of but immediately adjacent to said N-type well; and (d) an N+ region formed outside of said N-type well, wherein said N+ region is not grounded; (e) whereby said plurality of first P+ regions, said plurality of second P+ regions, said N+ region, and said N-type well form a plurality of pnp devices to allow a transient voltage to be discharged from the input pad to ground.