Patent ID: 7411861
Filing Date: 2008-08-12
Classification: G09G

Abstract:
1. An integrated circuit device, comprising: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a data read control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block, wherein the data read control circuit reads data for pixels corresponding to data lines of each of the data line groups from the RAM block by N (N is an integer larger than one) times reading in one horizontal scan period, wherein the data line driver block includes first to N-th divided data line driver blocks, each of the first to N-th divided data line driver blocks driving a different data line group of the data line groups, and wherein each of the first to N-th divided data line driver blocks is aligned along a first direction in which the bitlines extend.