Patent ID: 7923302
Filing Date: 2011-04-12
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor package, the method comprising; (a) arranging a plurality of low thermal expansion material plates with clearances provided therebetween in a grid pattern in a plane; (b) providing resin layers in the clearances, thereby forming an integral underlying plate comprising a plurality of underlying plates, wherein each of the underlying plates comprises: a corresponding one of the low thermal expansion material plates; and the resin layer surrounding the corresponding one of the low thermal expansion material plates; (c) forming a build-up wiring layer comprising a plurality of metal wiring layers and a plurality of insulation resin layers, on the integral underlying plate, thereby obtaining a semiconductor package collective plate comprising a plurality of semiconductor packages, wherein each of the semiconductor package comprises: a corresponding one of the underlying plates; and a corresponding portion of build-up wiring layer formed on the corresponding one of the underlying plates; and (d) cutting portions of the semiconductor package collective plate where the resin layers are provided, thereby dividing the semiconductor package collective plate into the plurality of semiconductor packages.