Patent ID: 7738311
Filing Date: 2010-06-15
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory array comprising a plurality of memory banks, wherein each bank is divided into a plurality of sub-banks; a first set of data I/O lines extending in a first direction between sub-banks, wherein the first set of data I/O lines are formed in a first metallization level; a second set of data I/O lines extending in a second direction, perpendicular to the first direction, across one sub-bank, wherein the second set of data I/O lines are formed in a second metallization level and connected to the first set of data I/O lines; and a third set of data I/O lines extending in the first direction across the one sub-bank, wherein the third set of data I/O lines are formed in a third metallization level and connected to the second set of data I/O lines.