Patent ID: 6563735
Filing Date: 2003-05-13
Classification: G11C

Abstract:
A NOR-structured semiconductor memory device comprising:a semiconductor memory cell array having a plurality of semiconductor memory cells; a plurality of bit lines electrically connected to said semiconductor memory cell array and divided into at least four bit line groups; a plurality of bit line transistors divided into at least four bit line transistor groups in such a way that each group of said at least four bit line transistor groups corresponds to one of said at least four bit line groups; a plurality of main bit lines divided into at least four main bit line groups in such a way that each group of said at least four main bit line groups corresponds to one of said at least four bit line groups; wherein at least two bit lines of each bit line group of said at least four bit line groups are coupled to a main bit line of a corresponding main bit line group of said at least four main bit line groups through at least two bit line transistors of a corresponding bit line transistor group of said at least four bit line transistor groups, respectively; and at least four adjacent bit lines of the NOR-structured semiconductor memory device are selected from four different bit line groups and coupled to four different main bit lines, respectively.