Patent ID: 9177632
Filing Date: 2015-11-03
Classification: G06F,G11C

Abstract:
1. A controller integrated circuit (IC) device to control the operation of a dynamic random access memory (DRAM), the controller IC comprising: an interface to transmit a clock signal and a strobe signal to the DRAM, the strobe signal to convey phase information to the DRAM for sampling data associated with the strobe signal; and calibration logic to establish a receiver phase offset for receiving read data and to align at the DRAM, arrival of the strobe signal with arrival of the clock signal at an edge transition of the clock signal by using a delayed strobe, the calibration logic to calibrate a clock cycle delay between commands received at the DRAM and data corresponding to the commands, the calibration logic to set the clock cycle delay for the strobe signal by iteratively writing first data, using the delayed strobe, to a specific location in the DRAM, read back second data, using the receiver phase offset, from the specific location, and selectively adjust the clock cycle delay by an integer number of cycles based on whether the second data matches the first data.