Patent ID: 6934923
Filing Date: 2005-08-23
Classification: G06F,H01L

Abstract:
1. A method for designing a semiconductor integrated circuit, comprising the steps of: providing a cell library that includes gate cell information enabled to execute basic logical functions; generating a net list by allocating a gate cell stored in said cell library in a logical description described with a register transfer level description; and verifying whether or not characteristics of said generated net list satisfy a required specification, wherein said cell library includes information about a plurality of gate cells that execute the same basic logical function but which are characterized by different threshold voltages, and further wherein each gate cell is allocated in said generating step on a cell allocation condition such that a gate cell with a high threshold voltage of a first insulated gate field effect transistor is selected as a logic gate in which a first insulated gate field effect transistor with a first conductivity is included among a plurality of insulated gate field effect transistors connected serially between operating potential points, while no other insulated gate field effect transistor of the first conductivity type is included along said plurality of insulated gate field effect transistors connected serially between said operating potential points, and further wherein a gate cell with a low threshold voltage of a second insulated gate field effect transistor is selected as a logic gate in which at least three second insulated gate field effect transistors of the first conductivity type are included among a plurality of said insulated gate field effect transistors connected serially between said operating potential points.