Patent ID: 6794897
Filing Date: 2004-09-21
Classification: H03K

Abstract:
A partitioned field programmable array architecture comprising:a plurality of block regions; a plurality of bidirectional buffer banks, each of said plurality of bidirectional buffer banks coupled on a first side by buffer channels to one of said plurality of block regions, said plurality of bidirectional buffer banks configured to be connected on a second side by block interconnect channels to a second side of another of said plurality of bidirectional buffer banks; a plurality of routing channels intersecting said block interconnect channels to form a plurality of intersections; a plurality of user-programmable elements disposed at some of said plurality of intersections, said user-programmable elements configured to provide user-programmable connections between said block interconnect conductors and said routing conductors; and a plurality of repeater buffers disposed serially in said plurality of routing channels.