Patent ID: 7697655
Filing Date: 2010-04-13
Classification: G09G,G11C

Abstract:
1. A shift register, comprising a plurality of stages of shift register units, each stage of shift register unit generating a scan signal and comprising: a first level lifting unit, for controlling the scan signal to be equal to a first timing signal in response to a high level of a first control signal; a first level lowering unit, for controlling the scan signal to be equal to a first voltage in response to a high level of a second control signal; a first driving unit, for providing the first control signal to turn on the first level lifting unit in response to a rising edge of an input signal; and a level controller, for receiving the first control signal and accordingly outputting the second control signal at an output terminal, the level controller comprising: wherein the input signal inputted to the first driving unit of the corresponding stage of shift register unit is a scan signal outputted by a previous stage of shift register unit; wherein the first level lowering unit of n-th stage of shift register unit further comprises a transistor, having a gate for receiving the first control signal of the (n+1)-th stage of shift register unit, a drain coupled to the output terminal of the n-th stage of shift register unit and, a source for receiving the first timing signal, wherein n is a natural number.