Patent ID: 6787840
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A flash memory chip, comprising:a semiconductor substrate having a core region and a periphery region; at least one shallow trench isolation (STI) formed in the periphery region only of said substrate; at least one local oxidation of silicon (LOCOS) isolation formed in the core region only of said substrate; a plurality of core memory devices formed on said core region only of the semiconductor substrate, each core memory device of the plurality of core memory devices comprising: a nitridated tunnel oxide barrier layer formed on the surface of the substrate; a first polysilicon layer formed on the nitridated tunnel oxide barrier layer; an interpoly dielectric layer formed on the first polysilicon layer; and a second polysilicon layer formed on the interpoly dielectric layer; and a plurality of periphery memory devices formed on a periphery region only of the semiconductor substrate, each periphery memory device of the plurality of periphery memory devices comprising: a gate oxide layer formed on the surface of the substrate, the gate oxide layer being un-nitridated, and part of the substrate surface under the gate oxide layer being un-nitridated; and a first polysilicon layer formed over the gate oxide layer.