Patent ID: 6476644
Filing Date: 2002-11-05
Classification: H03K

Abstract:
A semiconductor integrated circuit, comprising:a buffer circuit for outputting true and complementary signals, in response to an input signal; and a decoder circuit for decoding based upon an output of said buffer circuit; wherein said buffer circuit or both of said buffer circuit and said decoder circuit, respectively, comprise: a first load provided between one electric potential and a first node, wherein said first load charges said first node in response to a control signal; a second load provided between said one electric potential and a second node, wherein said second load charges said second node in response to said control signal; a first logic circuit provided between said first node and a third node, wherein said first logic circuit electrically connects said first node and the third node in response to either single or plural input signals; a reference field effect transistor including a source-drain path formed between said second node and said third node, and a gate which is connected to said first node; and a drive circuit provided between said third node and another electric potential, wherein said drive circuit drives said first logic circuit and said reference field effect transistor in response to said control signal; and further comprising: at least either one or both of: a second logic circuit which receives true and complementary signals from said buffer circuit and outputs either of said true or complementary signals to said decoder circuit, in response to a selection signal; and a dummy circuit for said second logic circuit which outputs a signal for activating said decoder circuit.