Patent ID: 6954819
Filing Date: 2005-10-11
Classification: G06F

Abstract:
1. A peripheral bus interconnect system, comprising: first and second peripheral bus lines that are electrically independent from one another; first and second arrays of peripheral devices respectively connected to said first and second peripheral bus lines; first and second controllers respectively connected to said first and second peripheral bus lines to drive said first and second bus lines in order to access and control the first and second arrays of peripheral devices connected thereto, said first and second controllers including control circuitry to send health status signals to each other to indicate the normal operation of said first and second controllers, said control circuitry being responsive to the absence of said health signals to indicate a malfunction of one of said first or second controllers; and a normally open switch located between said first and second peripheral bus lines and adapted to be closed to connect said first and second bus lines together in response to the absence of a health status signal from a malfunctioning of one of said first and second controllers, whereby the first and second arrays of peripheral devices are accessed and controlled by the normally functioning other one of said first and second controllers by way of said switch, malfunctioning of one of said first and second controllers, whereby the first and second arrays of peripheral devices are accessed and controlled by the normally functioning other one of said first and second controllers by way of said switch.