Patent ID: 7206233
Filing Date: 2007-04-17
Classification: G06F,G11C

Abstract:
1. A nonvolatile memory system comprising: a controller; a buffer memory having a clock terminal, an address strobe terminal, an enable terminal, an address terminal, and a data input/output terminal; a nonvolatile memory; an input-output terminal; a first signal line coupled between said input/output terminal and said controller; second signal lines coupled between said controller and said buffer memory; and a third signal line coupled between said controller and said nonvolatile memory, wherein said second signal lines include a clock signal line for supplying a clock signal to said clock terminal of said buffer memory and a data line for data transfer between said controller and said data input/output terminal of said buffer memory, wherein said controller controls to carry out a data transfer between said buffer memory and said controller itself via said data line in response to said clock signal when an enable signal is supplied to said enable terminal of said buffer memory, after a first address is supplied to said address terminal of said buffer memory accompanied with an enable signal to said address strobe terminal of said buffer memory, wherein said controller controls to carry out a first data transfer between said input/output terminal and said buffer memory via both of said first signal line and said data line, and to carry out a second data transfer between said buffer memory and said nonvolatile memory via both of said data line and said third signal line, and wherein said controller is adapted to carry out said first data transfer and said second data transfer at least partially concurrently.