Patent ID: 7211495
Filing Date: 2007-05-01
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: sequentially forming first, second, and third insulating layers on a semiconductor substrate having a lower interconnection line thereon; etching the third insulating layer to form an insulating layer pattern having (i) a first space exposing a first portion of the second insulating layer over a first portion of the lower interconnection line and (ii) a second space exposing a second portion of the second insulating layer over a second portion of the lower interconnection line; forming a fourth insulating layer on the insulating layer pattern including in the first and second spaces; etching the fourth insulating layer using the insulating layer pattern as an etch barrier to form a first trench and a second trench; etching the first and second insulating layers to form a first via hole exposing the first portion of the lower interconnection line and a second via hole exposing the second portion of the lower interconnection line; forming a first metal layer on an entire surface of the device; forming a capacitor insulating layer on the first metal layer in the second via hole and the second trench; forming a second metal layer on an entire surface of the device including in the first and second via holes and first and second trenches; and planarizing the second metal layer to expose the fourth insulating layer and form an upper interconnection line on the first portion of the lower interconnection line and a capacitor on the second portion of the lower interconnection line.