Patent ID: 6955932
Filing Date: 2005-10-18
Classification: G01R,H01L

Abstract:
1. A method for fabricating double gate FET test structures for electrical evaluation of a semiconductor layer on a buried oxide on a Si substrate comprising: a) providing a gate insulator on a surface of the semiconductor layer; b) depositing source and drain metal electrodes on the gate insulator in a geometric pattern, including depositing a first metal electrode layer from the group consisting of Al, Er, Gd, Nd, Ti, and Y, followed by depositing a second metal layer from the group consisting of Ag, Al, Au, Cr, Cu, Mg, Ni, and Pt, to form an electrode structure for said source and drain metal electrodes; c) annealing the electrode structure at an elevated temperature in an inert atmosphere; d) depositing a gate electrode between the source and drain metal electrodes without contacting the source and drain metal electrodes; e) depositing a protective layer over an entire Si surface of said Si substrate over which said buried oxide, said semiconductor layer, said gate insulator, said source and drain metal electrodes, and said gate electrode are located; f) creating individual isolated mesas of the protective layer to form a protective mask layer on the Si surface with the source, drain, and gate electrodes residing within the boundaries of the mesas; g) removing the gate insulator and the semiconductor layer in regions between the mesas; h) removing the protective mask layer.