Patent ID: 7009456
Filing Date: 2006-03-07
Classification: H03L,H04L

Abstract:
1. A phase-locked loop (PLL) comprising: a phase detector (PD) adapted to generate an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal; a proportional charge pump adapted to generate a first voltage for a first time period based on the up/down signal; an integral charge pump adapted to generate a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period; and a voltage-controlled oscillator (VCO) adapted to generate the clock signal based upon a combination of the first and second voltages; wherein the phase detector is a bang-bang phase detector.