Patent ID: 6140836
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A self-timed pipelined datapath system comprising:a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data, and a register connected to the input side of said combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in said pipelined datapath circuit in response to a request signal;wherein said combinational circuit in each of said plurality of data processing stages is composed of a multi-threshold CMOS circuit, with said multi-threshold CMOS circuit further comprisinga logic circuit portion configured by a plurality of low-threshold CMOS circuits, anda power control circuit portion, which is configured by a plurality of high-threshold MOS transistors and controls power feeding with respect to said logic circuit portion; and wherein said asynchronous signal control circuit comprises:a signal generating means for controlling active and inactive states of each of said combinational circuits in response to a request signal,and a plurality of monitoring circuits, each of which delays a write enable signal generated, in response to a request signal, to be applied to the register preceding the current combinational circuit, and issues another request signal with respect to the register succeeding the current combinational circuit.