Patent ID: 6449728
Filing Date: 2002-09-10
Classification: G06F,H03L

Abstract:
A synchronous quad clock domain system comprising:an external primary clock controlling an external primary clock domain with an external primary clock signal; an external secondary clock controlling an external secondary clock domain with an external secondary clock signal synchronized with the external primary clock signal with a synchronous multiple ratio; an internal primary clock controlling an internal primary clock domain with an internal primary clock signal; an internal secondary clock controlling an internal secondary clock domain with an internal secondary clock signal; a phase lock loop circuit synchronizing the internal primary clock signal with the external primary clock signal; a clock divider applying the synchronous multiple ratio to the internal primary clock signal to produce the internal secondary clock signal; a phase adjustment circuit matching a phase of the internal secondary clock signal with a phase of the external secondary clock signal; a phase delay circuit matching a rising edge of the internal secondary clock signal with a rising edge of the internal primary clock signal; an external sample logic unit sampling the external secondary clock signal to produce an external sample signature and matching the external sample signature to a pattern corresponding to the synchronous multiple ratio to produce an external clock cycle signal representing a start of a clock cycle of the external secondary clock signal; an internal sample logic unit sampling the internal secondary clock signal to produce an internal sample signature and matching the internal sample signature to a pattern corresponding to the synchronous multiple ratio to produce an internal clock cycle signal representing a start of a clock cycle of the internal secondary clock signal; and a phase adjust logic unit comparing the internal clock cycle signal to the external clock cycle signal and providing a phase adjust signal to the clock divider to match a phase of the internal secondary clock signal with a phase of the external secondary clock signal.