Patent ID: 6938141
Filing Date: 2005-08-30
Classification: G06F

Abstract:
1. An operation method of a control chip for accelerating a memory access operation, wherein the control chip is coupled to a Central Processing Unit (CPU), the operation method comprising: receiving from the CPU a first address strobe signal, a request signal, and an address bus signal that refer to a first clock, wherein the request signal comprises a selection phase and a length phase, and the address bus signal comprises an address phase and a byte enable phase; issuing a second address strobe signal that refers to the first clock when the selection phase indicates either a memory read request signal or a memory write request signal and the address phase indicates an effective memory address; converting the second address strobe signal that refers to the first clock to a third address strobe signal that refers to a second clock; issuing an enable signal that refers to the first clock when a specific condition indicative of an invalidate memory cycle is not suggested; and issuing a memory control signal that refers to the second clock when both the third address strobe signal and the enable signal are enabled.