Patent ID: 6583659
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A parallel clock driver comprising:a reference clock; a plurality of pre-driver circuits, responsive to the reference clock, each pre-driver circuit outputting a pull-up pre-driver line and a pull-down pre-driver line and receiving an enable signal having an enabling state that enables the pre-driver circuit to drive high and low the pull-up and pull-down pre-driver lines in response to the reference clock; a plurality of output buffers, each having a pull-up transistor with a gate driven by the corresponding pull-up pre-driver line, and a pull-down transistor with a gate driven by the corresponding pull-down pre-driver line, each driving a clock output with the pull-up transistor and the pull-down transistor; and a plurality of shorting switches, each shorting switch receiving a pair of the enable signals for a pair of the pre-driver circuits, the shorting switch connecting together the pull-up pre-driver lines generated by the pair of pre-driver circuits when the pair of enable signals are both in the enabling state, whereby the pull-up pre-driver lines are connected together by the shorting switch when the pair of the pre-driver circuits are both enabled.