Patent ID: 6377502
Filing Date: 2002-04-23
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase, each of said memory cells being an electrically rewritable nonvolatile memory cell; core selecting portion configured to select an optional number of cores from said plurality of cores for writing or erasing data; data writing portion configured to write data in a selected memory cell in a core selected by said core selecting portion; data erasing portion configured to erase data from a selected block in a core selected by said core selecting portion; data reading portion configured to read data out from a memory cell in a core which is not selected by said core selecting portion; a first address bus line which is provided commonly for said plurality of cores and which is used during a data read operation; a second address bus line which is provided commonly for said plurality of cores and which is used during a data write or erase operation; a first data bus line which is provided commonly for said plurality of cores and which is used during the data read operation; a first sense amplifier circuit which is connected to said first data bus line and which is used during the data read operation; a second data bus line which is provided commonly for said plurality of cores and which is used during the data write or erase operation; and a second sense amplifier circuit which is connected to said second data bus line and which is used for carrying out a verify read operation during the data write or erase operation.