Patent ID: 6424179
Filing Date: 2002-07-23
Classification: G06F

Abstract:
A logic unit for coupling to a bus operating in a first clock domain, and for interfacing between the bus and a device operating in a second clock domain, the frequency of the second clock domain being less than the frequency of the first clock domain, the logic unit comprising:an interrupt source, responsive to a signal issued by the device, for asserting a first interrupt signal in the second clock domain; output logic, responsive to the first interrupt signal, to output a second interrupt signal via the bus to a processor operating in the first clock domain, the processor being arranged to process the interrupt indicated by the second interrupt signal, and to issue a clear request signal at a predetermined point during processing of the interrupt; clear generation logic arranged, whilst the first interrupt signal is asserted, to be responsive to receipt of the clear request signal to assert a clear signal to the interrupt source and to assert a control signal to the output logic; the output logic being responsive to receipt of the control signal to stop outputting the second interrupt signal; the interrupt source being responsive to the clear signal to de-assert the first interrupt signal, the de-assertion of the first interrupt signal causing a clear acknowledge signal to be generated; the clear generation logic being responsive to the clear acknowledge signal to de-assert the clear signal.