Patent ID: 8367502
Filing Date: 2013-02-05
Classification: H01L

Abstract:
1. A method of manufacturing a dual gate semiconductor device, the method comprising: providing a semiconductor substrate having first and second regions in which different conductive MOS (metal-oxide semiconductor) transistors are to be formed; forming a gate dielectric layer over the semiconductor substrate; sequentially forming a first metallic conductive layer and a second metallic conductive layer over the gate dielectric layer; covering the second region with a mask; performing ion plantation of a first material into the first metallic conductive layer over the first region; removing the second metallic conductive layer over the first region; and forming a first gate electrode over the first region and a second gate electrode over the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region.