Patent ID: 9029222
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A method for forming a transistor comprising: providing a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a fin part by etching the buffer layer, wherein the fin part is formed of an insulating material; forming an insulating layer on the semiconductor substrate, the insulating layer having a top surface lower than a top surface of the fin part; forming a quantum well (QW) layer on surface of the fin part; forming a barrier layer on surface of the QW layer; forming a gate structure on the barrier layer across the fin part and on the insulating layer, the gate structure including a gate dielectric layer on each of the insulating layer and the barrier layer, and a gate electrode on the gate dielectric layer; forming a sidewall spacer on both sidewalls of the gate structure; forming a recess in the fin part on both sides of the gate structure to suspend the sidewall spacer; and forming a source and a drain by growing an epitaxial material in the recess, each of the source and the drain including a side edge aligned with a sidewall edge of the gate structure such that a channel region in the QW layer under the gate structure having a same width with the gate structure and the channel region does not extend to under the sidewall spacer.