Patent ID: 8839171
Filing Date: 2014-09-16
Classification: G06F

Abstract:
1. An electronic circuit design automation method implemented in a computing system for providing global design closure at a high level of abstraction with direction for downstream floor planning and routing, the method comprising: receiving by the computing system a description of at least a portion of a synthesized logic design; performing a functional analysis by the computing system of a logic hierarchy of the received design to produce a corresponding physical hierarchy with clusters of locally-connected logic; iteratively checking by the computing system intra-cluster routing congestion and timing to redefine clusters and mapping data flow to define placement of clusters and inter-cluster interconnectivity; placing by the computing system any hard macros of the received design based on connectivity timing and power constraints; generating by the computing system a top-level global floorplan topology based on the placement of clusters and received physical constraints; analyzing by the computing system timing delay in inter-cluster global data paths and refining the floorplan topology to reduce delay; and generating by the computing system and storing in a memory a set of library and constraint files for the refined floorplan topology for the synthesized logic design.