Patent ID: 6239460
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having a major surface;an interlayer insulating film formed on said major surface of said substrate and having openings therein which reach said major surface;connection members disposed within said openings;a capacitor including lower capacitor electrodes, a dielectric film made of a high dielectric material and formed by a Chemical Vapor Deposition (CVD) method on said lower capacitor electrodes, and an upper capacitor electrode deposited on said dielectric film;each of said lower capacitor electrodes being separated from each other and being electrically connected with said major surface through said connection members;each of said lower capacitor electrodes being in the form of a metal electrode made mainly from ruthenium, said lower capacitor electrodes connecting directly to said dielectric film without a layer of oxide formed on a surface of said lower capacitor electrodes during formation of said dielectric film being in contact with said interlayer insulating film between said lower capacitor electrodes;a top surface of each of said connection members being formed at a certain level equal to or lower than the upper surface of said interlayer insulating film; andsaid lower capacitor electrodes being in direct contact with said connection members, such that no diffusion barrier is provided between said metal electrodes made mainly from ruthenium and said connection members.