Patent ID: 8513938
Filing Date: 2013-08-20
Classification: G05F

Abstract:
1. A reference voltage circuit comprising: a first amplifier including first and second input terminals, coupled to a first power source line and a second power source line, configured to output a reference voltage; a first load device and a first PN junction device coupled in series between a reference voltage line to which the reference voltage is applied and the second power source line; second and third load devices and a second PN junction device coupled in series between the reference voltage line and the second power source line, the first input terminal being coupled to a first coupling node which connects the first load device and the first PN junction device, the second input terminal being coupled to a second coupling node which connects the second load device and the third load device; an offset voltage reduction circuit configured to reduce an offset voltage between the first and second input terminals at the first amplifier; a coupling node potential takeout circuit configured to take out potentials of the first and second coupling nodes; and an area adjustment circuit configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.