Patent ID: 8209651
Filing Date: 2012-06-26
Classification: G06F

Abstract:
1. A wiring layout method comprising: performing a layout of a power wiring for an integrated circuit; performing a layout of a plurality of signal wirings for the integrated circuit; comparing a signal frequency of each of the signal wirings with a predetermined reference frequency; classifying the signal wirings into a first group and a second group, the first group consisting of the signal wirings having signal frequencies equal to or over the reference frequency and the second group consisting of the signal wirings having signal frequencies under the reference frequency; calculating, by a processor, an evaluation value of a temperature rise of the integrated circuit by excluding the temperature rise caused by a power consumption of the signal wirings of the first group; and modifying, by a processor, the layouts of a power wiring and the signal wirings of the integrated circuit when the evaluation value is over a predetermined allowable value.