Patent ID: 6713811
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A new split gate structure for improved programming efficiency comprising:a silicon region extending to the surface of a substrate, having parallel source/drain regions in said silicon region and electrical connecting regions disposed over said source/drain region; a multiplicity of structures situated between source drain regions, each composed of two tower structures and intervening oxide layers: a floating gate tower in which a first insulating layer separates a floating gate from said silicon region and a second insulating layer separates said floating gate from a top gate, with a third insulating layer disposed over the top gate; and a selected gate tower in which a silicon pedestal is in intimate electrical contact with said silicon region and said silicon pedestal is separated from a selected gate by an insulating layer, along the interfacing sidewalls the silicon pedestal is separated from the floating gate by a first intervening insulating layer and the selected gate is separated from the floating gate tower by a second intervening insulating layer.