Patent ID: 6621316
Filing Date: 2003-09-16
Classification: H03K,H03L

Abstract:
A synchronous mirror delay, comprising:a model delay line for receiving an input clock signal and operable to generate a model delayed clock signal in response to the input clock signal, the model delayed clock signal having a model delay relative to the input clock signal; a bi-directional delay line coupled to the model delay line and including a plurality of unit delays, the bi-directional delay line operable in a forward mode responsive to a mode control signal to propagate the model delayed clock signal through the unit delays in a forward direction, each unit delay delaying the model delayed clock signal by a corresponding delay, and operable in a backward mode responsive to the mode control signal to propagate the model delayed clock signal through the unit delays in a backward direction, each unit delay delaying the model delayed clock signal by the corresponding delay; and a control circuit coupled to the bi-directional delay line, the control circuit operable to alternately place the delay line in the forward and backward modes of operation to time a forward delay, and thereafter operable to alternately place the bi-directional delay line in the forward and backward modes to time a backward delay that is approximately equal to the forward delay, and the control circuit operable upon expiration of the backward delay to output the model delayed clock signal from a selected unit delay.