Patent ID: 6819579
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A ten-transistor (10-T) content addressable memory (CAM) cell comprising:a word line; a first pair of complementary bit lines comprising a first bit line; and a second bit line; a six-transistor (6-T) static random access memory (SRAM) cell coupled to the word line, the first bit line, and the second bit line for storing a digital data value; a match line for providing a match signal; a second pair of complementary bit lines comprising a third bit line and a fourth bit line; and a four-transistor (4-T) comparator module coupled to the match line, the third bit line, the fourth bit line, and the 6-T SRAM cell for comparing the digital data value stored in the 6-T SRAM cell with an input data value provided on the third bit line or the fourth bit line.