Patent ID: 8407715
Filing Date: 2013-03-26
Classification: G06F

Abstract:
1. A method of optimizing multi-set context switch for embedded processors, comprising the steps of: partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the plurality of registers; storing contents of first target registers according to live set information of a current task stored in a live-set-information register, wherein the first target registers are selected from the register sets; determining a next task by an operating system and updating the live set information stored in the live-set-information register according to the next task; and restoring contents of second target registers according to the updated live set information stored in the live-set-information register, wherein the second target registers are selected from the register sets, and wherein the live-range-sensitive context-switch procedure comprises the steps of: