Patent ID: 7227785
Filing Date: 2007-06-05
Classification: G01R,G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell being set to one of plural threshold voltage; a bit line connected to the memory cell; a first data storage circuit for storing data supplied from an exterior; a read circuit for reading data corresponding to the threshold voltage of the memory cell; a second data storage circuit for storing data read by the read circuit; a first switch circuit connected between the bit line and the first data storage circuit to connect the first data storage circuit to the bit line; a second switch circuit connected between the bit line and the second data storage circuit to connect the second data storage circuit to the bit line, and a transistor having a gate and a current path, the gate of the transistor being connected to receive data in the second data storage circuit, the current path arranged to transfer the data to the second data storage circuit without inverting the data.