Patent ID: 7952587
Filing Date: 2011-05-31
Classification: G03F,G06F,H03M,Y02D,Y02P

Abstract:
1. A processor comprising: a first data path having a first bit width; a second data path having a second bit width greater than the first bit width; a plurality of third data paths having a combined bit width less than the second bit width; a wide operand storage coupled to the first data path and to the second data path for storing a wide operand received over the first data path, the wide operand having a size with a number of bits greater than the first bit width; a register file including registers having the first bit width, the register file being connected to the third data paths, and including at least one wide operand register to specify an address and the size of the wide operand; a functional unit capable of performing operations in response to instructions, the functional unit coupled by the second data path to the wide operand storage, and coupled by the third data paths to the register file; and wherein the functional unit executes a single instruction containing instruction fields specifying (i) the wide operand register to cause retrieval of the wide operand for storage in the wide operand storage, (ii) an operand register in the register file, and (iii) a results register in the register file, the instruction causing the functional unit to perform a matrix multiply operation between matrix elements contained in the wide operand and a plurality of multiplier elements contained in the operand register in the register file, the matrix multiply operation producing a plurality of results elements for storage in the results register.