Patent ID: 6614696
Filing Date: 2003-09-02
Classification: G11C

Abstract:
A semiconductor device comprising:first and second wiring lines; a first memory block having a first switch, a plurality of first word lines, and a plurality of first memory cells; and a second memory block having a second switch, a plurality of second word lines, and a plurality of second memory cells; wherein each of said plurality of first memory cells has a first transistor, a second transistor, and a third transistor, gates of said first and second transistors are coupled to one of said plurality of first word lines, a gate of said third transistor is coupled to a drain/source path of said first transistor, and a drain of said third transistor is coupled to a drain/source path of said second transistor, wherein each of said plurality of second memory cells has a fourth transistor, a fifth transistor, and a sixth transistor, gates of said fourth and fifth transistors are coupled to one of said plurality of first word lines, a gate of said sixth transistor is coupled to a drain/source path of said fourth transistor, and a drain of said sixth transistor is coupled to a drain/source path of said fifth transistor, wherein said drain/source paths of said first transistors of said first memory cells are coupled to said first wiring line, wherein said drain/source paths of said fourth transistors of said second memory cells are coupled to said second wiring line, wherein said drain/source paths of said second transistors of said first memory cells are coupled to said second wiring line via said first switch, and wherein said drain/source paths of said fifth transistors of said second memory cells are coupled to said second wiring line via said second switch.