Patent ID: 6852595
Filing Date: 2005-02-08
Classification: H01L

Abstract:
1. A method of manufacturing a flash memory cell comprising: forming a tunnel oxide film and a first polysilicon layer with a given pattern; sequentially forming a dielectric film, a second polysilicon layer, a tungsten silicide layer and an anti-reflection film on the given pattern; forming a control gate consisting of the tungsten silicide layer and the second polysilicon layer by means of a patterning process; and forming a floating gate consisting of the first polysilicon layer by a self-aligned etching process, wherein, after the patterning process and before the self-aligned etching process, a cleaning process is carried out to remove oxide series particles but which leaves a polymer film at the side wall of the anti-reflection film, the tungsten silicide layer, the second polysilicon layer and the dielectric film, thereby protecting the side wall of the tungsten silicide layer from etching damage upon the self-aligned etching process.