Patent ID: 7969780
Filing Date: 2011-06-28
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a flip-flop having a first node (node T) and a second node (node B), the flip-flop having a first inverter to control the first node and a second inverter to control the second node, the first inverter and the second inverter being cross coupled, the first inverter including a first load transistor (MP a first bit line (BLT) and a second bit line (BLB); a voltage source line (SL) commonly and directly connected to a source of the first cell transistor and a source of the second cell transistor; a word line; a first gate transistor (MN a second gate transistor (MN a first precharge transistor (MP a second precharge transistor (MP wherein the voltage source line (SL) is configured so as to provide a positive voltage to the source of the first cell transistor (MCN