Patent ID: 7746137
Filing Date: 2010-06-29
Classification: G06F,H03K

Abstract:
1. A method comprising: receiving first data at a first transistor of a retention circuit from a first output of a first input element, wherein the first transistor selectively couples a second output of a second input element to a first supply terminal in response to the first data, wherein the first transistor selectively blocks a current path between the second output and the first supply terminal, and wherein the second input element is responsive to the first input element; and wherein a single clocked transistor is configured to provide a virtual voltage level to the first input element and to the second input element when a clock signal activates the single clocked transistor, wherein when the single clocked transistor is deactivated while the second data has a first logical value, the current path is held open by the first transistor responsive to the keeper transistor and by the second transistor responsive to the inverter.