Patent ID: 6378120
Filing Date: 2002-04-23
Classification: G06F,H01L

Abstract:
A method for generating power slits in a power bus located on a chip, comprising the steps of:(a) locating the data set representing the power bus in a mask layout database; (b) determining a width for the power bus; (c) determining a length for the power bus; (d) dividing said width of the power bus by a first width of the power slits plus a first spacing distance between a first number of power slits to be generated in a first direction of the power bus; (e) dividing said length of the power bus by a first length of the power slits plus a second spacing distance between the power slits to determine a second number of power slits to be generated in a second direction of the power bus; and (f) automatically adding a location of the power slits determined in said steps (d) and (e) to said data set representing the power bus on the mask layout database.