Patent ID: 8421793
Filing Date: 2013-04-16
Classification: G02F

Abstract:
1. A pixel array substrate, comprising: a substrate; a plurality of scan lines disposed on the substrate, wherein the scan lines are parallel with each other; a plurality of first patterned floating lines disposed on the substrate and located between the scan lines; an insulation layer disposed on the substrate and covering the scan lines and the first patterned floating lines; a plurality of data lines disposed on the insulation layer, wherein said data lines are parallel with each other, each of the data lines crosses the plurality of scan lines and is partially overlapped with at least one of the first patterned floating lines, and each of the data lines is isolated from the first patterned floating lines when the data line is not broken, whereas the data line is correspondingly connected to the first patterned floating line through a welding portion when the data line is broken, wherein a break of the data line occurs over the scan line; a plurality of active elements formed on the substrate, wherein each of the active elements is electrically connected to each corresponding scan line and each corresponding data line; a plurality of pixel electrodes formed on the substrate, wherein each of the pixel electrodes is electrically connected to each corresponding active element; and a plurality of first patterned connecting wires, wherein each of the first patterned connecting wires crosses one of the scan lines and is overlapped with the first patterned floating lines disposed on the two sides of the scan line.