Patent ID: 8463571
Filing Date: 2013-06-11
Classification: G06F

Abstract:
1. A computer-implemented method for performing reliability analysis of an integrated circuit design, said method comprising: simulating a periodic voltage waveform in a network model of said integrated circuit design, using a computerized device; determining resultant current values in each segment of nets of said integrated circuit design resulting from said periodic voltage waveform, using said computerized device; performing a Fourier transform of said periodic voltage waveform to generate a frequency domain representation of said periodic voltage waveform, using said computerized device, said frequency domain representation comprising multiple Fourier terms, each of said Fourier terms comprising a frequency that is a multiple of said periodic voltage waveform; performing an AC analysis of said integrated circuit at each frequency of said Fourier terms, using said computerized device, said AC analysis providing an electrical current value for each of said frequencies of said Fourier terms for each of said nets; computing a root mean square current through each said segment of said nets based on said AC analysis, using said computerized device; and determining whether said root mean square current for any said segment of said nets exceeds a current limit, using said computerized device; and reporting any said segment of said nets for which said root mean square current exceeds said current limit, using said computerized device.