Patent ID: 7808071
Filing Date: 2010-10-05
Classification: H01L

Abstract:
1. A semiconductor device, comprising: high voltage (HV) active regions located in a semiconductor substrate, wherein each of the HV active regions is located between isolation regions and has a corner adjacent the isolation regions and the isolation regions comprise a high density plasma oxide; a HV gate oxide layer located over the HV active regions having a thickness of greater than 5 nm and wherein a ratio of a thickness of the HV gate oxide layer over the corner to a thickness of the HV gate oxide layer over the active region ranges from about 0.6:1 to about 0.8:1; HV gates located over at least a portion of the HV gate oxide layer; low voltage (LV) active regions located in the semiconductor substrate; a LV gate oxide layer located over the LV active regions and having a thickness less than about 5 nm; and a LV gate located over at least a portion of the LV gate oxide layer.