Patent ID: 6505226
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A parallel adder, comprising:at least one pair of full adders, wherein each of the pair of full adders comprises: a logic combination unit for NORing and NANDing input signals to respectively generate a first control signal and a second control signal; a buffer comprising a plurality of transistors that buffers a carry input signal based on the first control signal and the second control signal; a carry output unit for generating a carry output signal based on the first control signal, the second control signal and the carry input signal; a sum output controller comprising a logic circuit for logically combining the first and second control signals to generate a third control signal; and a sum output unit that receives the third control signal and the carry input signal to generate a sum output signal, wherein the sum output unit comprises a transmission gate to output the sum output signal based on the third control signal and the carry input signal.