Patent ID: 8472272
Filing Date: 2013-06-25
Classification: G11C

Abstract:
1. A semiconductor device comprising a memory cell array configured with hierarchical local bit lines and global bit lines, the device comprising: first to fourth local bit lines respectively transmitting first to fourth signals corresponding to first to forth memory cells that are selected simultaneously; first to fourth global bit lines respectively corresponding to the first to fourth local bit lines; a first switch controlling a connection between one end of the first global bit line and one end of the second global bit line; a second switch controlling a connection between one end of the third global bit line and one end of the fourth global bit line; first and second sense amplifiers; a third switch selectively connecting one of the other ends of the first and third global bit lines to the first sense amplifier; a fourth switch selectively connecting one of the other ends of the second and fourth global bit lines to the second sense amplifier; fifth to eighth switches connecting between the first to fourth local bit lines and the first to fourth global bit lines respectively; and a control circuit controlling the first to eighth switches, wherein the first and third global bit lines are physically adjacent to each other and the second and fourth global bit lines are physically adjacent to each other, in a first period, the control circuit performs a first operation in which the first sense amplifier amplifies the first signal and a second operation in which the second sense amplifier amplifies the second signal, the first and second operations being performed in a state where the first and second global bit lines are electrically disconnected from each other by the first switch, the third and fourth global bit lines are electrically connected to each other via the second switch, the fifth and sixth switches become conductive, the seventh and eighth switches become non-conductive, the third and fourth global bit lines are set to a predetermined potential, the first global bit line is electrically connected to the first sense amplifier via the third switch, and the second global bit line is electrically connected to the second sense amplifier via the fourth switch, and in a second period different from the first period, the control circuit further performs a third operation in which the first sense amplifier amplifies the third signal and a fourth operation in which the second sense amplifier amplifies the fourth signal, the third and fourth operations being performed in a state where the first and second global bit lines are electrically connected to each other via the first switch, the third and fourth global bit lines are electrically disconnected from each other by the second switch, the seventh and eighth switches become conductive, the fifth and sixth switches become non-conductive, the first and second global bit lines are set to the predetermined potential, the third global bit line is electrically connected to the first sense amplifier via the third switch, and the fourth global bit line is electrically connected to the second sense amplifier via the fourth switch.