Patent ID: 6263399
Filing Date: 2001-07-17
Classification: G06F

Abstract:
A processor to NAND flash memory interface comprising:a processor also having a plurality of control lines, a plurality of address lines, and a plurality of data lines;a NAND flash memory unit also having a plurality of control lines and a plurality of I/O lines;a memory interface unit also having a first and second plurality of control lines, a plurality of address lines, a plurality of data lines, and a plurality of I/O lines where said plurality of processor control lines are operably coupled to said first plurality of control lines, said plurality of processor address lines are operably coupled to said plurality of address lines, said plurality of processor data lines are operably coupled to said plurality of data lines, said plurality of NAND flash memory control lines are operably coupled to said second plurality of control lines, said plurality of NAND flash memory I/O lines are operably coupled to said plurality of I/O lines;said memory interface configured to receive addresses from said processor in said processor's native address form, configure said processor's native address form to said NAND flash memory's native address form, send said NAND flash memory's native address form to said NAND flash memory, receive data from a location associated with said NAND flash memory's native form address from said NAND flash memory, extract at least one byte of data from said data received from said NAND flash memory where said at least one byte of data is associated with said processor's native address form, and send said extracted data to said processor in said processor's native data form; and,said memory interface further configured to be responsive to said processor before said processor is in operable communication with any component not addressable by said processor using said processor's native commands.