Patent ID: 6567880
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A computer system having a core logic chip set adapted for a plurality of accelerated graphics port (AGP) devices or one or more AGP devices and one or more peripheral component interconnect (PCI) devices, the AGP devices being compliant with Revision 2.0 of the AGP Specification (AGP 2.0 devices), the system comprising:a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chip set comprising: a first AGP 2.0 request queue; a first AGP 2.0 reply queue; a second AGP 2.0 request queue; a second AGP 2.0 reply queue; a first AGP 2.0 data and control logic; a second AGP 2.0 data and control logic; an AGP 2.0 and PCI arbiter; a PCI data and control logic; and a PCI to PCI bridge; the first and second AGP 2.0 request and reply queues connected to a memory interface and control logic, the memory and interface control logic connected to the random access memory bus; the first and second AGP 2.0 data and control logic connected to the memory and interface control logic; the PCI data and control logic connected to the memory and interface control logic; the first and second AGP 2.0 data and control logic and PCI data and control logic connected to a host bus interface, the host bus interface connected to the host bus; a host to primary PCI bus bridge connected to the host bus interface and connected to a primary PCI bus; the PCI to PCI bridge connected to the first and second AGP 2.0 data and control logic, and the PCI data and control logic, wherein the PCI to PCI bridge transfers PCI information transactions between the host to primary PCI bus bridge and the first and second AGP 2.0 data and control logic, and the PCI data and control logic; and the first and second AGP 2.0 data and control logic, the PCI data and control logic, and the AGP 2.0 and PCI arbiter connected to a first AGP 2.0 bus having two AGP 2.0 devices or one AGP 2.0 device and one PCI device.