Patent ID: 7733123
Filing Date: 2010-06-08
Classification: G06F,H03K

Abstract:
1. A circuit, comprising: a first logic circuit having a self-timed input and a self-timed output; a second logic circuit having a self-timed input and a self-timed output; an input circuit coupled to provide a self-timed input signal to the self-timed input of a selected one of the first or second logic circuits based on the value of a control signal, and further coupled to output a self-timed select signal; an output circuit coupled to receive the self-timed output from the first logic circuit and the self-timed output from the second logic circuit, and to output a selected one of the self-timed outputs based on a value of the self-timed select signal; and a pipelined routing path routing the self-timed select signal from the input circuit to the output circuit.