Patent ID: 6211012
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method of fabricating an ETOX flash memory adapted for a semiconductor substrate, the method comprising:providing the semiconductor substrate, the substrate comprising an active region isolated by an isolation structure therein;forming a stacked word line perpendicularly across the isolation structure on the substrate;forming a source region and a drain region in the active region isolated by the isolation structure on both sides of the stacked word line;forming spacers on sidewalls of the stacked word line;forming a first insulating layer over the substrate;removing parts of the first insulating layer to form a patterned trench exposing the source region and the drain region, while the isolation structure at the same side of the source region is exposed, and the isolation region at the same side of the drain region is covered by the first insulating layer;forming a first conductive material layer inside the trench to form a source line on the source region and the isolation structure at the same side of the source region and a landing pad on the drain region only;forming a second insulating layer over the substrate;removing parts of the second insulating layer to form a contact window that exposes the landing pad; andforming a contact plug in the contact window and a bit line on the second insulating layer, wherein the contact plug is electrically connected to the drain region and the bit line.