Patent ID: 8570100
Filing Date: 2013-10-29
Classification: H03H,H04B

Abstract:
1. A sampling circuit, comprising: a clock generating circuit that outputs four-phase control signals according with a period of a carrier frequency of an input signal; an IQ generating circuit that samples the input signal according to the four-phase control signals, and accumulates four kinds of sample values having different phases as electrical charge; and a group of discrete time circuits including a first to a fourth discrete time circuits that share electrical charge of the four kinds of sample values, respectively, wherein: each of the first to the fourth discrete time circuits includes: a charging switch; a rotate capacitor connected to the IQ generating circuit via the charging switch; a dump switch; and a buffer capacitor connected to the rotate capacitor via the dump switch; the charging switch is controlled on and off using any one of the four-phase control signals; the rotate capacitor shares electrical charge accumulated in the IQ generating circuit via the charging switch; the dump switch is controlled on and off using another one of the four-phase control signals having a different phase from the four-phase control signal used by the charging switch; and the buffer capacitor forms an output value by sharing electrical charge with the rotate capacitor via the dump switch.