Patent ID: 9135970
Filing Date: 2015-09-15
Classification: G06F,G11C

Abstract:
1. A device comprising: a plurality of detection memory cells, each detection memory cell of the plurality of detection memory cells configured to be pre-programmed to a respective initial predetermined state, the initial predetermined state of each of the plurality of detection memory cells configured to be unmodifiable by subsequent commands directed to the device; a plurality of reference bits, each reference bit of the plurality of reference bits corresponding to a respective one of the plurality of detection memory cells, wherein the initial predetermined state of each detection memory cell is represented by a corresponding reference bit of the plurality of reference bits; and comparator circuitry coupled to the plurality of detection memory cells and the plurality of reference bits, the comparator circuitry configured to compare a current state of each detection memory cell of the plurality of detection memory cells with a corresponding reference bit of the plurality of reference bits.