Patent ID: 8996960
Filing Date: 2015-03-31
Classification: G06F,H03M

Abstract:
1. A DIMM apparatus comprising: a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of data buffers, respectively, each of error correcting modules configured within each of the data buffers, each error correcting module being configured to correct a single or double bit error within each DRAM device, wherein the ECM is configured to associate error correcting check bits with a first number of bursts created from a data buffer to the DRAM device based upon a second number of bursts received from a memory controller device, the first number of bursts greater than the second number of bursts.