Patent ID: 6930946
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having dynamic memory cells; and a refresh controller that executes refresh operation for the memory cell array, wherein the refresh controller comprises: a refresh timing signal generator that periodically generates a refresh timing signal used to establish a timing of execution of the refresh operation; a refresh request signal generator that generates a refresh request signal indicating a request for the execution of the refresh operation in response to the refresh timing signal; and a refresh execution signal generator that generates a refresh execution signal indicating the execution of the refresh operation in response to the refresh request signal and another signal, wherein the refresh request signal generator comprises: a first counter that counts the number of times the refresh timing signal has been generated; and a second counter that counts the number of times the refresh execution signal has been generated, and wherein the refresh request signal generator generates the refresh request signal if a difference between the number of times the refresh timing signal has been generated and the number of times the refresh execution signal has been generated is one or more, and the refresh execution signal generator is capable of generating two or more of the refresh execution signals within one cycle of the refresh timing signal if the difference is two or more.