Patent ID: 7159199
Filing Date: 2007-01-02
Classification: G06F

Abstract:
1. A method of testing a circuit under design having a plurality of functional elements and having a plurality of clock environments, at least one signal passing from one clock environment to another clock environment in said circuit, said method comprising steps of: modelling at least one of the plurality of functional elements to have an unknown state as an output for a predetermined time after a timing event of a clock signal; simulating said circuit to identify one or more of said functional elements plurality of that is a source of propagation of said unknown state; and determining which of said plurality of functional elements is a synchronizer to thereby identify if there is a synchronization problem for said at least one signal passing from said one clock environment to said another clock environment so as to identify if a functional element which is a source of propagation of said unknown state is a hazard or a synchronizer.