Patent ID: 6504773
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A memory testing method wherein after data has been written in all of the memory cells in one block to be tested of a memory having its storage area divided into a plurality of blocks, an erase test has been carried out which comprises the steps of: erasing en bloc the storage data written in all of the memory cells in the block to be tested; and inspecting as to whether the storage data in each of the memory cells has been erased or not, said method comprising the steps of:in the first time erase test, sequentially reading out all of the memory cells in the block to be tested that have been erased en bloc, inspecting as to whether the storage data in each of the memory cells has been erased or not, and storing, when a failure memory cell the storage data of which has not been erased has been detected, the address of the failure memory cell; and in the second time and the succeeding erase tests in case a failure memory cell or cells have been detected, reading out only the failure memory cell or cells in the block to be tested, the address or addresses of the failure memory cell or cells having been stored, and inspecting as to whether the storage data in the failure memory cell or each of the failure memory cells has been erased or not.