Patent ID: 8841752
Filing Date: 2014-09-23
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a plurality of interposer dice on an un-singulated semiconductor wafer, wherein scribe lanes between neighboring pairs of the dice have widths of at least 5.0% of the width of each interposer die plus an amount that compensates for material that would be removed in singulating the wafer, and each interposer die including: for each interposer die of the plurality of interposer dice, one or more stiffening structures formed in and completely confined to one or more of the scribe lanes that circumscribe the interposer die, respectively, the one or more stiffening structures having a width of at least 2.5% of the width of each interposer die plus an amount that compensates for material that would be removed in singulating the wafer.