Patent ID: 6504772
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A method of testing a to-be-tested circuit comprising:an initial test condition testing step of performing a logical test of the to-be-tested circuit under a first test condition to obtain first fault information and judging, according to a first fault information, whether or not the repair of the faulty portion of the to-be-tested circuit by a redundancy circuit is possible; and a confirmation step including a first step of performing a logical test, which is the same as the logical test performed in the initial test condition testing step, for the to-be-tested circuit under a second test condition different from the first test condition to obtain second fault information, in a case where it is judged that the repair of the faulty portion of the to-be-tested circuit is possible, and a second step of comparing the first fault information with the second fault information to obtain a comparison result which indicates whether the to-be-tested circuit is correctly operable under each of the first test condition and the second test condition.