Patent ID: 7110228
Filing Date: 2006-09-19
Classification: H01L

Abstract:
1. An integrated circuit adapted to protect a first and a second internal circuits from electro-static discharge (ESD), the first internal circuit coupled between a first high power line and a first low power line, the second internal circuit coupled between a second high power line and a second low power line, the first and the second high power lines being separated from each other, the first and the second low power lines being separated from each other, the integrated circuit comprising: a first ESD protection circuit, coupled between the first high and the first low power lines; a second ESD protection circuit, coupled between the second high and the second low power lines; a third ESD protection circuit, coupled between the first high and the second high power lines, selectively grounding the first or the second high power lines while ESD occurring on the first or the second high power lines, wherein the third ESD protection circuit comprises a first diode string, a first metal-oxide-semiconductor (MOS) transistor and a second diode string, wherein the first diode string and the first MOS transistor are coupled in series; the second diode string are parallel and reverse to the first diode string and the first MOS transistor, and the first diode string and the first MOS transistor constitute a parasitic silicon-controlled rectifier (SCR) for providing a discharge route while triggered by ESD; and a fourth ESD protection circuit, coupled between the first low and the second low power lines, selectively grounding the first or the second low power lines while ESD occurring on the first or the second low power lines, wherein the fourth ESD protection circuit comprises third diode string, a second metal-oxide-semiconductor (MOS) transistor and fourth diode string, the third diode string and the second MOS transistor are coupled in series; the fourth diode string are parallel reverse to the third diode string and the second MOS transistor; and the third diode string and the second MOS transistor constitute a parasitic silicon-controlled rectifier (SCR) for providing a discharge route while triggered by ESD.