Patent ID: 6355980
Filing Date: 2002-03-12
Classification: H01L

Abstract:
An integrated-circuit chip having one or more pairs of reversible wire-bonding-pads to alternatively provide a standard pattern for the reversible wire-bonding-pads and a non-standard, reversed wire-bonding pattern for the reversible wire-bonding-pads, comprising:a first wire-bonding-pad; a second wire-bonding-pad; a first common signal line on said integrated-circuit chip; a second common signal line on said integrated-circuit chip; a first gate circuit having an input signal terminal connected to the first wire-bonding-pad, having an output signal terminal connected to the first common signal line, and having a control terminal which receives a standard wire-bonding configuration control signal which operates the first gate circuit to provide a standard pattern for the first wire-bonding-pad, which standard pattern connects the first wire-bonding-pad to the first common signal line to thereby provide the first input LOGIC signal to the first common signal line on said integrated-circuit chip; a second gate circuit having an input signal terminal also connected to the first wire-bonding-pad, having an output signal terminal connected to the second common signal line, and having a control terminal which receives a non-standard, reversed wire-bonding configuration control signal which operates the second gate circuit to alternatively provide a non-standard, reversed pattern for the first wire-bonding-pad, which non-standard, reversed pattern connects the first wire-bonding-pad to the second common signal line to thereby alternatively provide the first input LOGIC signal to the second common signal line on said integrated-circuit chip; a third gate circuit having an input signal terminal connected to the second wire-bonding-pad, having an output signal terminal connected to the second common signal line, and having a control terminal which receives the standard wire-bonding configuration control signal which operates the third gate circuit to provide a standard pattern for the second wire-bonding-pad, which standard pattern connects the second wire-bonding-pad to the second common signal line to thereby provide the second input LOGIC signal to the second common signal line on said integrated-circuit chip; a fourth gate circuit having an input signal terminal also connected to the second wire-bonding-pad, having an output signal terminal connected to the first common signal line, and having a control terminal which receives the non-standard, reversed wire-bonding configuration control signal which operates the fourth gate circuit to alternatively provide a non-standard, reversed pattern for the second wire-bonding-pad, which non-standard, reversed pattern connects the second wire-bonding-pad to the first common signal line to thereby alternatively provide the second input LOGIC signal to the first common signal line on said integrated-circuit chip; wherein the first gate circuit and the third gate circuit are controlled by the standard-bonding-pad control signal to provide a predetermined standard bonding-pad configuration for the integrated-circuit chip, which standard bonding-pad configuration connects the first wire-bonding input pad to the first common signal line on the integrated-circuit chip and which standard bonding-pad configuration also connects the second wire-bonding-pad to the second common signal line; and whereby the second gate circuit and the fourth gate circuit are controlled by the reverse-bonding-pad control signal to provide a predetermined alternative reversed bonding-pad configuration for the integrated-circuit chip, which alternative reversed bonding-pad configuration connects the first wire-bonding-pad to the second common signal line and which alternative reversed bonding-pad configuration also connects the second wire-bonding-pad to first common signal line.