Patent ID: 7586130
Filing Date: 2009-09-08
Classification: B82Y,H01L,Y10S

Abstract:
1. A vertical field effect transistor comprising: a bundle of multiple linear structures, which functions as a channel region where electric carriers are transported; a lower electrode, which is connected to the bottom of the bundle of multiple linear structures and which functions as one of source and drain regions; an upper electrode, which is connected to the top of the bundle of multiple linear structures and which functions as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of multiple linear structures; and a gate insulating film, which is arranged between the bundle of multiple linear structures and the gate electrode in order to electrically isolate the gate electrode from the bundle of multiple linear structures, wherein the transistor further includes a dielectric layer which supports the upper electrode, the dielectric layer having an outer peripheral side surface, wherein the upper electrode is located over the lower electrode with the dielectric layer interposed between the upper and lower electrodes, and includes an overhanging end portion that sticks out laterally from over the dielectric layer, wherein the bundle of multiple linear structures is located right under the overhanging end portion of the upper electrode and outside of the outer peripheral side surface of the dielectric layer, and wherein the bundle of multiple linear structures is in contact with the overhanging end portion of the upper electrode, and the dielectric layer is not in contact with the overhanging end portion of the upper electrode.