Patent ID: 6356495
Filing Date: 2002-03-12
Classification: G11C

Abstract:
A method of operating a dynamic random access memory including sense circuitry having first and second nodes, including a digit line and a plate line, including a first isolation transistor selectively coupling the digit line to the first node of the sense circuitry, including a second isolation transistor selectively coupling the plate line to the second node of the sense circuitry, including a first equilibration transistor selectively coupling the digit line to the plate line, including a second equilibration transistor selectively coupling the plate line to an equilibration voltage source which defines an equilibration voltage, and including a memory cell having a capacitor with a first plate coupled to the plate line and with a second plate and having an access transistor selectively coupling the second plate to the digit line, the method comprising:turning on the first and second equilibration transistors; turning off the first and second equilibration transistors; turning on the access transistor; reading the memory cell with the sense circuitry; and turning on the second equilibration transistor, while the first equilibration transistor is off.