Patent ID: 6373742
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A memory device comprising a memory array having circuit lines extending across said memory array; routing lines connected to said circuit lines extending from said memory array, wherein at least one of said routing lines extends from a first side of said memory array and at least one of said routing lines extends from a second side of said memory array; and decoding circuits connected to said routing lines; wherein said decoding circuits comprise a plurality of first decoding circuits, each of said plurality of first decoding circuits being individually connected to each of said routing lines, said decoding circuits also comprising second decoding circuits connected to said first decoding circuits, a plurality of said second decoding circuits being positioned on said first side of said memory array and being connected to said first decoding circuits positioned on said first side, a comparable plurality of said second decoding circuits being positioned on said second side of said memory array and being connected to said first decoding circuits positioned on said second side.