Patent ID: 6577545
Filing Date: 2003-06-10
Classification: G11C

Abstract:
An integrated circuit memory device, comprising:a normal memory cell block having a normal word line electrically coupled thereto; a spare memory cell block having a spare word line electrically coupled thereto; and a word line driver circuit comprising a normal word line driver electrically coupled to the normal word line and a spare word line driver electrically coupled to the spare word line, said spare word line driver comprising a programmable address decoder that generates a spare word line driver enable signal on an enable signal line and a spare word line driver enable signal precharger that is responsive to a multi-row address test signal and is electrically coupled to the enable signal line; wherein said spare word line driver further comprises a selector switch that is responsive to the spare word line driver enable signal and a driver that electrically coupled to the spare word line; wherein the selector switch comprises a MOS transistor having a drain electrically coupled to the driver and a gate electrically coupled to the enable signal line; and wherein said spare word line driver enable signal precharger comprises a pulse-generator that is responsive to the multi-row address test signal and at least one row address.