Patent ID: 6316825
Filing Date: 2001-11-13
Classification: H01L,Y10T

Abstract:
A chip stack package comprising:at least two semiconductor chips stacked up and down, which comprise a plurality of bonding pads arranged along a center of the respective semiconductor chips in one package;lead frames attached to bonding pad-disposed faces of the respective semiconductor chips, wherein the lead frames have inner leads electrically connected to each other, and one among the at least two semiconductor chips having an outer lead;a conductive adhesive coated at interface between outer ends of the lead frames having only the inner lead and the lead frames having both the inner and outer leads;a metal wire for electrically connecting the inner leads of the lead frames and the bonding pads;an epoxy compound for entirely molding a resultant structure so as to expose only the outer lead which is provided with the one lead frame; anda connecting hole formed at the outer ends of the inner leads of the lead frames not having the outer lead so as to increase contact area with the lead frame having the outer lead.