Patent ID: 6256254
Filing Date: 2001-07-03
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cell array blocks;an address transition detecting pulse generator to generate address transition detecting pulse signals by detecting the transition of a plurality of addresses;a global row decoder having a plurality of groups of pre-decoders and a main decoder to generate a plurality of global word line signals of a plurality of memory cell array blocks by decoding the plurality of addresses; anda plurality of block row decoders having a plurality of decoding cells to respectively respond to block controls signal to respectively select a plurality of memory cell array blocks and a plurality of pulse control signals combined with the address transition detecting pulse signals to output a plurality of global word line signals generated by the global row decoder as a plurality of local word line signals, wherein a plurality of the decoding cells of a plurality of the block row decoders comprises:switching means to switch the global word line signal into a local word line signal in response to the first state of the pulse control signals; andinactive means to put the local word line signal into its inactive state in response to the second state of the pulse control signals.