Patent ID: 6711064
Filing Date: 2004-03-23
Classification: G11C,H01L

Abstract:
A single-poly EEPROM, comprising:a first PMOS transistor serially connected to a second PMOS transistor, wherein the first and second PMOS transistors are both formed on an N-well of a P-type substrate, and wherein the first PMOS transistor includes a floating gate, a first P+ doped drain region, and a first P+ doped source region, the second PMOS transistor includes a gate and second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor; and an N-type doped region formed in the P-type substrate beneath the floating gate serving as an erase gate in the vicinity of the first PMOS transistor, wherein the floating gate of the first PMOS transistor overlaps with the N-well and the P-type substrate and extends to the erase gate.