Patent ID: 7123534
Filing Date: 2006-10-17
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of word lines; a plurality of bit lines arranged to intersect the word lines; a plurality of memory cells arranged at intersections between the word lines and the bit lines; and control means for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line, and for refreshing memory cells corresponding to the second word line by an end of the cycle, wherein each of the memory cells comprises: an amplifier section including two driver transistors of which gate electrodes and drain electrodes are respectively cross-coupled with each other; and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit lines, and either one of each of the driver transistors and each of the selector transistors is an n-channel transistor and the other one thereof is a p-type transistor.