Patent ID: 8344771
Filing Date: 2013-01-01
Classification: H03L

Abstract:
1. A delay locked loop (DLL) of a semiconductor integrated circuit, comprising: a first delay line configured to delay a source clock signal by a first delay time taken for a locking state and output a locked clock signal; a phase comparator configured to compare the phase of the source clock signal with the phase of a feedback clock signal; a second delay line configured to, before the locking state of the first delay line, delay the locked clock signal by a second delay time obtained by modeling a delay amount of an internal circuit and, after the locking state of the first delay line, delay the locked clock signal by a minimum delay time to maintain the locking state of the first delay line and further configured to provide the delayed signal as the feedback clock signal; a first delay controller configured to control the first delay time of the first delay line; a second delay controller configured to control the minimum delay time of the second delay line; and an operation mode controller configured to control the first and second delay controllers in response to an output signal of the phase comparator, and switch operation modes of the first and second delay controllers depending on the locking state of the first delay line, wherein the minimum delay time corresponds to a delay time obtained by subtracting the first delay time from a time corresponding to a period of the source clock signal.