Patent ID: 7091087
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A method for forming a floating gate memory array comprising: forming a gate dielectric layer on a substrate, wherein the substrate extends horizontally in perpendicular X and Y directions; forming a floating gate material layer on the gate dielectric layer; forming a disposable material layer on the floating gate material layer; etching column strips in the Y direction through the disposable material layer, floating gate material layer and the gate dielectric layer to form isolation trenches into the substrate which extend longitudinally in the Y direction; forming an insulator material to a vertical height above the disposable material layer; planarizing the insulator material to expose a top region of the disposable material layer; removing the disposable material layer to expose a top region of the floating gate material layer, wherein the top region of the floating gate material layer is recessed below a top surface of the planarized insulator material; forming layers of an intermediate dielectric, a conductive wordline, a tungsten silicide and an insulation cap; etching row strips in the X direction through the floating gate material layer to a depth of at least the gate dielectric layer to define transistor gates; performing a source implant to form rows of source regions in the substrate extending in the X direction in alternate ones of the row strips; performing a source/drain implant to simultaneously form drain regions unique to a respective transistor while increasing a doping of the rows of source regions; forming dielectric transistor gate spacers; forming a conformal etch stop barrier layer over the transistor gates, the gate spacers, the source regions and the drain regions; forming a planarized insulation material over the etch stop barrier layer; performing a via etch through the planarized insulation material to completely clear the planarized insulation material residing between the transistor gates, thus exposing the etch stop barrier layer and forming rows of source line vias running in the X direction and separate drain vias unique to each transistor running in the Y direction; clearing a horizontal component of the conformal etch stop barrier layer that covers the source regions and drain regions; and forming individual drain contacts to a respective transistor gate and rows of source contact interconnects, wherein the individual drain contacts and the rows of source contact interconnects substantially fill openings between the transistor gates and abut to a vertical component of the conformal etch stop barrier layer residing on the transistor gates.