Patent ID: 6515935
Filing Date: 2003-02-04
Classification: G11C

Abstract:
A circuit for reducing power in a plurality of memory arrays comprising:a set of diodes; a set of controlled voltage sources; a set of NFETs; wherein all sources of said set of NFETs and all cathodes of said set of diodes are electrically connected to GND; wherein a least one drain of a NFET from said set of NFETs and at least one anode of a diode from said set of diodes is connected to a negative electrical connection of a member of said plurality of memory arrays; wherein all members of said plurality of memory arrays are connected to at least one drain of a NFET from said set of NFETs and to at least one anode of a diode from said set of diodes; wherein at least one gate of a NFET from said set of NFETs is electrically connected to a member of said set of variable voltage sources.