Patent ID: 7930504
Filing Date: 2011-04-19
Classification: G06F

Abstract:
1. A data processing system comprising: a processor; a memory subsystem including a memory coupled to the processor and including a plurality of physical locations having real addresses for storing data; an asynchronous memory mover coupled to the processor and which, in response to receiving a set of parameters associated with a data move operation initiated by the processor utilizing a source effective address and a destination effective address, performs an asynchronous memory move (AMM) operation by which the actual data is moved from a first memory location having a source real address corresponding to the source effective address to a second memory location having a destination real address corresponding to the destination effective address; wherein the asynchronous memory mover further comprises a flag bit, which is set by the asynchronous memory mover logic when an AMM operation is ongoing at the memory; wherein the processor reads the flag bit before issuing a new memory access operation to determine possible address conflicts.