Patent ID: 6329242
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method for fabricating a semiconductor memory device including a substrate, a transfer transistor having source/drain regions formed on the substrate, and a charge storage capacitor that is electrically coupled to one of the source/drain regions, said method comprising:forming an insulating layer over the substrate, the insulating layer covering the transfer transistor;forming an insulating pillar over the insulating layer, the insulating pillar defining recess areas on either side thereof;sequentially forming a first conformal conductive layer, a first conformal dielectric layer, and a second conformal conductive layer over the insulating pillar and over the insulating layer in the recess areas;blanket depositing a second dielectric layer over the second conformal conductive layer;planarizing the top surfaces of the second dielectric layer, the second conformal conductive layer, the first conformal dielectric layer, and the first conformal conductive layer;forming a patterned photoresist mask layer over the planarized surface of the second dielectric layer;etching the second dielectric layer, the second conformal conductive layer, the first conformal dielectric layer, the first conformal conductive layer, and the insulating layer until one of the source/drain regions is exposed, forming a contact opening; andfilling the contact opening with a third conductive layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer in combination form a storage electrode of the charge storage capacitor.