Patent ID: 9081563
Filing Date: 2015-07-14
Classification: G06F

Abstract:
1. An apparatus comprising: a processor operable to execute a reordered sequence of instructions, wherein the reordered sequence of instructions includes a first instruction and a second instruction to be changed from being executable after the first instruction to being executable prior to the first instruction; a register operable to store, if the second instruction is executed, a first memory address range accessed by the second instruction, wherein the register is unusable by the reordered sequence of instructions, and wherein the first instruction includes information that indicates in a bitmask of the first instruction, which is affected by the reordering, to identify the register; and a comparator coupled to the register, wherein the comparator is operable to compare the first memory address range with a second memory address range accessed by the first instruction to determine an overlap responsive to an enable signal, wherein if the comparator determines the first memory address range overlaps the second memory address range, an exception is triggered.