Patent ID: 8735237
Filing Date: 2014-05-27
Classification: H01L

Abstract:
1. A method, comprising: forming a drain mask above a drain region of a transistor so as to substantially completely cover said drain region and expose a source region; performing a source implantation process to implant a dopant species into said source region of said transistor by using said drain mask and a gate electrode as an implantation mask, said source implantation process comprising at least one implantation step using a first tilt angle selected to enhance a penetration depth of the dopant species on the basis of a crystallographic orientation of the source region; forming a source mask above said source region to substantially completely cover said source region and expose said drain region; and performing a drain implantation process to implant said dopant species into said drain region by using said source mask and said gate electrode as an implantation mask, said drain implantation process comprising at least one implantation step using a second tilt angle of opposite sign to the first tilt angle, the second tilt angle being selected to enhance a penetration depth of the dopant species on the basis of a crystallographic orientation of the drain region.