Patent ID: 6507860
Filing Date: 2003-01-14
Classification: G06F

Abstract:
A method of designing a circuit for providing efficient simultaneous operation of a plurality of RADIX-2 elements to enable a Fast Fourier Transform (FFT) calculation, the circuit being implemented in a logic device including programmable resources for implementing the circuit, the method comprising the steps of:assigning a plurality of memory resources, each designated Rvw, to a plurality of RADIX-2 elements, each designated Xab; assigning a first multiplexing means to selectively forward data to at least one of said RADIX-2 elements from at least one of said plurality of memory resources; and assigning a second multiplexing means to selectively forward data from at least one of said RADIX-2 elements to at least one of said plurality of memory resources; whereby a RADIX-2 element Xab receives data from memory resources Rvw such that (vw=ab) or vw can be derived by changing either a or b from 0 to 1, and a memory resource Rvw receives data from a RADIX-2 element Xab whose ab is such that (ab=vw) or ab can be derived by changing either v or w from 1 to 0.