Patent ID: 7263539
Filing Date: 2007-08-28
Classification: G06F

Abstract:
1. A fixed point data generating circuit which receives a plurality of floating point data and converts said received plurality of floating point data into respective fixed point data, said fixed point data generating circuit comprising: a reference data determining unit for determining a reference floating point data from said received plurality of floating point data; an exponent part subtractor unit for obtaining the differences between the values of the exponent parts of the received floating point data which are not determined as said reference floating point data and a value of an exponent part of said reference floating point data; a shifting unit for shifting a mantissa part of each of said plurality of floating point data by the difference obtained for the corresponding floating point data; and a bit extracting unit for extracting a predetermined number of bits of each shifted mantissa part as fixed point data, a leading bit of said predetermined number of bits comprising a second bit from the most significant bit (MSB) of the shifted mantissa part except the sign bit, wherein when an overflow occurs in said extracted bits, said bit extracting unit outputs a predetermined maximum value of said fixed point data.