Patent ID: 7259599
Filing Date: 2007-08-21
Classification: H03K,H03L,H04N

Abstract:
1. A semiconductor device comprising: N stages of delay cells, each of the N delay cells delaying an input clock signal by 1/N clock period and outputting the respective delayed clock signal; a reference signal phase detection circuit for detecting a phase state of a present reference signal based on phase differences between the clocks outputted from the delay cells and the present reference signal, and detecting a phase state of a previous reference signal based on phase differences between the clocks outputted from the delay cells and the previous reference signal; a comparison circuit for comparing the phase state of the present reference signal and the phase state of the previous reference signal which are detected by the reference signal phase detection circuit; a phase control circuit for shifting the phase state of the present reference signal to make it coincide with the phase state of the previous reference signal, when the comparison circuit detects that the phase states of the present reference signal and the previous reference signal do not coincide with each other; a selector; and a selector control circuit for controlling the selector based on the output of the phase control circuit to select a clock which is most synchronized with the shifted phase state of the present reference signal from among clocks outputted from the respective delay cells, and to output the selected clock as a sync clock.