Patent ID: 6476641
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A low power consuming circuit comprising:a logic circuit containing, at least one inverter made up of a P-channel metal insulator semiconductor transistor and an N-channel metal insulator semiconductor transistor, both gates of which are connected to each other and both drains of which are connected to each other, and operating in an active mode and in a standby mode; and wherein a sub-threshold leakage current is reduced by boosting, in said standby mode, a threshold voltage in said P-channel and said N-channel metal insulator semiconductor transistors in said logic circuit by using a back gate bias effect induced by a source voltage control; and wherein a circuit to increase a source voltage used to boost said threshold voltage is made up of a source voltage control circuit having a complementary metal insulator semiconductor transistor and a source voltage bias transistor having a metal insulator semiconductor transistor whose gate is connected to a drain of said source voltage bias while in said standby mode.