Patent ID: 6591347
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A processor system comprising:a central processing unit; a graphics unit; a shared cache coupled to the central processing unit and the graphics unit; monitor circuitry to monitor hits or misses in the shared cache resulting from accesses by the graphics unit; cache replacement circuitry, responsive to the monitor circuitry detecting over-utilization of the shared cache by the graphics unit, to selectively limit eviction of cache segments within the shared cache for replacement with data requested by the graphics unit to selected regions of the shared cache; and an application program that reads a statistic counter to determine whether to program a programmable mode register to one of: (i) a mode limiting eviction of cache segments for replacement with data requested by the graphics unit to the selected regions and (ii) a mode in which eviction of cache segments for replacement with data requested by the graphics unit is not limited to the selected regions of the shared cache.