Patent ID: 7421568
Filing Date: 2008-09-02
Classification: G06F,Y02D

Abstract:
1. An apparatus for saving power in a processor environment which supports variable length instructions, the apparatus comprising: a predecoder for partially decoding instructions of a first length and a second length, the second length being longer than the first length, and generating predecode bits for instructions of both the first length and the second length; a processor operating mode state indicator, the processor operating mode state indicator indicating that the processor is operating in a mode that restricts instructions to instructions of the second length; an instruction cache having a plurality of cache lines, a cache line configured to store a plurality of instructions and to store predecode bits at a plurality of predetermined bit fields; and write control logic to selectively write predecode bits in a cache line dependent upon the processor operating mode state indicator whereby less than all the plurality of predetermined predecode bit fields for an instruction are written for an instruction of the second length.