Patent ID: 9058114
Filing Date: 2015-06-16
Classification: G06F

Abstract:
1. A solid-state storage device controller, configured to be coupled to a solid state memory, wherein the controller is configured to: determine average write throughput to the solid-state memory over a given period of time; determine a first amount of time that average write throughput is high, wherein determining the first amount of time that average write throughput is high comprises incrementing a time register for each period of time average write throughput to the solid-state storage device over the given period of time is greater than a high throughput threshold; determine a second amount of time that average write throughput is low, wherein determining the second amount of time that average write throughput is low comprises decrementing the time register for each period of time average write throughput to the solid-state storage device over the given period of time is less than a low throughput threshold; and throttle write throughput to the solid-state memory based on a comparison of the first amount of time and the second amount of time using the time register.