Patent ID: 6714441
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A latching circuit that senses and latches the magnetic states of a first bit line and a second bit line in a magnetoresistive random access memory (MRAM), the latching circuit comprising:a first output and a second output; a reset circuit having a first terminal, a second terminal, and a third terminal, the reset circuit responsive to a first state of an input signal applied to the first terminal to couple the second terminal to the third terminal, and responsive to a second state of the input signal applied to the first terminal to decouple the second terminal from the third terminal; a first n-type transistor having a source, a drain and a gate, the source of the first n-type transistor coupled to a first portion of the first bit line; a second n-type transistor having a source, a drain and a gate, the source of the second n-type transistor coupled to a first portion of the second bit line; a first p-type transistor having a source, a drain and a gate, the source of the first p-type transistor coupled to a second portion of the second bit line; a second p-type transistor having a source, a drain and a gate, wherein: the source of the second p-type transistor is coupled to a second portion of the first bit line; the drain of the second p-type transistor is coupled to the drain of the second n-type transistor, to the gate of the first n-type transistor, to the gate of the first p-type transistor, to the second terminal of the reset circuit, and to the second output; and the gate of the second p-type transistor is coupled to the gate of the second n-type transistor, to the third terminal of the reset circuit, to the drain of the first n-type transistor, to the drain of the first p-type transistor, and to the first output.