Patent ID: 8223558
Filing Date: 2012-07-17
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells being arranged in an array form; a plurality of word lines connected to the plurality of memory cells; a data-programming circuit for performing a program operation and a program verification operation, the program verification operation being performed to determine whether or not a first data has been programmed into selected memory cells, the selected memory cells being included in the plurality of memory cells; wherein the program operation and the program verification operation are repeated to program the first data into the selected memory cells; and wherein in the program operation, a first program pulse is applied to a selected word line connected to the selected memory cells, and then a second program pulse is applied to the selected word line, the program verification operation is not performed after the first program pulse and before the second program pulse, a first program voltage is applied to the selected word line in the first program pulse, and a second program voltage is applied to the selected word line in the second program pulse.