Patent ID: 6425071
Filing Date: 2002-07-23
Classification: G06F

Abstract:
An interface circuit comprising:a RISC processor bus; a RISC processor interface unit coupled to said RISC processor bus for generating memory access requests and for generating requests over a Peripheral Component Interconnect bus; a memory unit; a memory interface unit coupled to said memory unit and for responding to memory access requests to said memory unit; a Peripheral Component Interconnect interface unit coupled to said Peripheral Component Interconnect bus, said Peripheral Component Interconnect interface unit for communicating with a Peripheral Component Interconnect device; an internal bus coupled to said RISC processor interface unit, said memory interface unit and said Peripheral Component Interconnect interface unit; and a RISC processor coupled to said RISC processor bus, said RISC processor bus an Advanced Microcontroller Bus Architecture Advanced System Bus, said RISC processor for communicating with said memory unit and with said Peripheral Component Interconnect device, wherein said RISC processor interface unit operates at a first clock frequency and wherein said Peripheral Component Interconnect interface unit operates at a second clock frequency.