Patent ID: 8949540
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core having an associated first upper level cache and a first lower level cache, and wherein the second processing unit has a second processor core and an associated second upper level cache and second lower level cache, said method comprising: in response to a need to evict one of a plurality of cache lines in a congruence class of the first lower level cache: in response to determining to perform the LCO of the coherence state of the victim cache line, the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies an address of the victim cache line to be evacuated from the first lower level cache, indicates the first data-invalid coherence state, and indicates that a lower level cache is an intended destination of the coherence state of the victim cache line; and in response to a coherence response to the LCO command indicating success of the LCO command, evacuating the victim cache line from the first lower level cache and associating the address of the victim cache line with the first data-invalid coherence state in a directory of the second lower level cache, wherein the LCO command does not transfer data of the victim cache line from the first lower level cache to the second lower level cache.