Patent ID: 6292414
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A method for repairing defective memory cells connected to respective row lines and respective column lines in an integrated semiconductor memory, the method which comprises:providing at least two submethods for testing memory cells in an integrated semiconductor memory and repairing defective ones of the memory cells, each of the at least two submethods performing a successive testing of the memory cells and, after ascertaining a defect of a given one of the memory cells and prior to check a further one of the memory cells, replacing one of a row line and a column line connected to the given one of the memory cells by programming one of a plurality of redundant lines including redundant row lines and redundant column lines, the at least two submethods differing in terms of an order of checking the memory cells and in terms of selecting a given one of the plurality of redundant lines for the purpose of replacing one of the row line and the column line by programming the one of the plurality of redundant lines;calling one of the at least two submethods and terminating the one of the at least two submethods with a defect-signature, the defect-signature containing information about a number of checked memory cells and a number of one of programmed ones of the plurality of redundant lines and remaining ones of the plurality of redundant lines; andsubsequently, depending on the defect-signature, calling another one of the at least two submethods, the another one of the at least two submethods initially performing a step selected from the group consisting of entirely canceling, partially canceling, and not canceling the programming of at least one of the plurality of redundant lines.