Patent ID: 7385834
Filing Date: 2008-06-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n<m, and M=m+1; a first decoder region and a second decoder region respectively located on opposite sides of the data block; wherein a first data line group among the M data lines extend to the first decoder region from the data block, wherein a second data line group among the M data lines extend to the second decoder region from the data block, wherein the first data line group includes even numbered data lines among the data lines {0, 1, 2, . . . n}, and odd numbered data lines among the data lines {n+1, . . . m−1, m}, and wherein the second data line group includes odd numbered data lines among the data lines {0, 1, 2, . . . n}, and even numbered data lines among the data lines {n+1, . . . m−1, m}.