Patent ID: 8234537
Filing Date: 2012-07-31
Classification: H03M

Abstract:
1. A programmable decoder configurable to decode data encoded with multiple different LDPC codes, the decoder comprising: control circuitry programmed with a parity check matrix associated with one of the LDPC codes; a message memory to store layers of blocks of updated extrinsic reliabilities; a column-sum memory to store soft bits comprising column-sum data; a subtraction element to subtract a next layer of the updated extrinsic reliabilities from corresponding soft bits of the column-sum data; a layer processor to recalculate data stored in the message memory to update the extrinsic reliabilities of the next layer from a soft-bit output of the subtraction element; and a sum element to add the updated extrinsic reliabilities generated by the layer processor with a soft-bit output of a prior subiteration provided by the subtraction element to generate the column-sum data to be fed-back to update the column-sum memory for each iteration, wherein the control circuitry is to cause the message memory to exclude blocks of the updated extrinsic reliabilities from being provided to the subtraction element that correspond to null submatrices of the parity check matrix of the programmed LDPC code.