Patent ID: 6906362
Filing Date: 2005-06-14
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a die; an active area disposed on said die, said active area including source dopants and contacts, an active area metal layer overlying said active area; a sense area disposed on said die, a sense area metal layer overlying said sense area; a plurality of spaced-apart polysilicon gate stripes and body stripes disposed on said die, said plurality of polysilicon gate stripes and body stripes extending in a continuous and uninterrupted manner from said active area into said sense area; a first region surrounding a periphery of said sense area, said first region having excluded therefrom source dopants and contacts; an etched region disposed over said first region, said etched region separating and electrically isolating said sense area metal layer from said active area metal layer.