Patent ID: 6178116
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells arranged in a matrix form, each of the memory cells having a charge accumulation layer to store charges, an amount of the charges represents data stored, and each of the memory cells being subject to a data program, a data read and a data erasure;a plurality of word lines connected to the memory cells in the same rows for selecting the memory cells;a plurality of bit lines connected to the memory cells in the same columns;a voltage boosting circuit formed integrally in the semiconductor memory device for receiving a power supply voltage and for generating a high level voltage, the level of which is higher than the power supply voltage;a decoding circuit for receiving address signals and for generating a selection signal in response to the address signals;a plurality of transfer gates, each of the transfer gates being connected between an output of the decoding circuit an a corresponding one of the word lines, and each of the transfer gates having a gate electrode;wherein the gate electrode of the transfer gates is supplied with a first level voltage when at least one of the memory cells are subject to the data read, and is supplied with the high level voltage when at least one of the memory cells are subject to the data program, and wherein the level of the high level voltage is higher than the level of the first level voltage.