Patent ID: 6877119
Filing Date: 2005-04-05
Classification: G01R

Abstract:
1. A semiconductor integrated circuit having a test scan arrangement, comprising: a plurality of scan chains each having an input end and an output end and being arranged in pairs of a first scan chain and a second scan chain; a plurality of first terminals and second terminals; compression logic having a plurality of inputs and at least one output, the plurality of inputs being connected to the output ends of the plurality of scan chains, and the at least one output being connected to at least one compression logic output terminal of the semiconductor integrated circuit for external connection; the plurality of first terminals each being connected to the input end of the first scan chain of one pair of scan chains for external input connection; the plurality of second terminals each being selectively connected, in a first state, to the input end of the second scan chain of one of each pair of scan chains for external input connection or, in a second state, to the output end of the second scan chain for external output connection; the input end of the second scan chain of each pair being selectively connectable in the second state to the output end of the first scan chain of each pair.