Patent ID: 6536003
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A testable read-only memory for data memory redundant logic in a data memory, comprising:a plurality of sampling flip-flop; a plurality of read-only memory units for storing determined fault addresses of faulty data memory units, each of said plurality of read-only memory units connected to a corresponding one of said plurality of sampling flip-flops, an operability of each of said read-only memory units being checked by application of an input test data and by comparison of a read output test data with an expected nominal output test data, each of said read-only memory units having a latch circuit with a first data input, a second data input and a data output, each latch circuit including: a first feedback inverter having an input and an output and a second feedback inverter having an input and an output; and a multiplexer switched, in a normal mode, to said first data input connecting said input of said first inverter with said output of said second inverter and closing a feedback loop of said latch circuit, and said multiplexer switched, in a test mode, to said second data input connecting said input of said first inverter with an output of said corresponding sampling flip-flop for injection of a test data into the feedback loop of said latch circuit.