Patent ID: 7291907
Filing Date: 2007-11-06
Classification: H01L

Abstract:
1. A chip stack, comprising: a flex circuit comprising: a flex substrate; a plurality of conductive traces formed within the flex substrate; a first conductive pattern formed on a top surface of the flex substrate; a second conductive pattern formed on a bottom surface of the flex substrate, both the first and second conductive patterns being formed on opposite surfaces within a first portion of the flex substrate, and both conductive patterns being electrically coupled to the conductive traces formed within the flex substrate; and a third conductive pattern disposed on the top surface within a second portion of the flex substrate, the third conductive pattern being electrically coupled to the conductive traces; a first integrated circuit chip package comprising a first set of contacts, the first set of contacts being arranged to electrically couple to the first conductive pattern formed on the top surface of the flex substrate; at least one second integrated circuit chip package comprising a second set of contacts arranged to electrically couple to the second conductive pattern formed on the bottom surface of the flex substrate, wherein at least the second portion of the flex substrate is wrapped around a peripheral edge of the second integrated circuit chip package; and an adhesive layer provided on the top surface of the second integrated circuit chip package, wherein the second portion of the flex substrate is attached to the adhesive layer.