Patent ID: 7100134
Filing Date: 2006-08-29
Classification: G06F

Abstract:
1. A computer-implemented method of generating a layout for an integrated circuit, the computer-implemented method comprising: generating a layout based on a physical design of the integrated circuit; performing a first circuit performance analysis on the layout; incorporating manufacturing enhancements on the layout, the manufacturing enhancements including optical proximity correction; performing a second circuit performance analysis on the layout using the layout with the manufacturing enhancements incorporated therein to generate a taped-out layout of the integrated circuit; checking design-rules on the taped-out layout; modifying the taped-out layout by performing the manufacturing enhancements on the taped-out layout using at least in part results of the first circuit performance analysis; and performing a third circuit performance analysis on the modified taped-out layout with the manufacturing enhancements included therein to generate a final layout to be used in manufacturing of masks for fabrication of the integrated circuit.