Patent ID: 6222764
Filing Date: 2001-04-24
Classification: G11C

Abstract:
An electrically erasable memory device comprising:a substrate and a plurality of memory cells in said substrate, each memory cell comprisinga first region having a first conductivity type in said substrate,a first MOS transistor in said first region and comprising spaced apart source and drain regions defining a channel therebetween and a gate overlying said channel,a second region having a second conductivity type in said substrate laterally adjacent said first region,a capacitor comprising a first electrode overlying said second region and an insulating layer therebetween, and a third region having the first conductivity type in said second region defining a second electrode, andsaid gate of said first MOS transistor and said first electrode of said capacitor being connected together to define a floating gate, and said second region serving as a control gate; andan erasing circuit for selectively erasing at least one of said memory cells by supplying a first voltage reference of a first polarity to said spaced apart source and drain regions of said first MOS transistor, a second voltage reference of a second polarity to said first region, and a third voltage reference of the second polarity to said third region, so that a junction breakdown voltage of said first MOS transistor is not exceeded.