Patent ID: 8143126
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A method of forming a vertical MOS transistor using a semiconductor layer, comprising: etching an opening in the semiconductor layer; forming a gate dielectric in the opening that has a vertical portion that extends to a top surface of the semiconductor layer; forming a gate in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric; performing an implant to form a source region at the top surface of the semiconductor layer while the overhang portion is present; and forming a third insulating layer in the opening in the semiconductor layer having the first etch characteristic; and removing the third insulating layer using an etchant that laterally etches the first insulating layer to leave an undercut region between the first semiconductor layer and the second insulating layer prior to forming the gate dielectric.