Patent ID: 7609100
Filing Date: 2009-10-27
Classification: G01R

Abstract:
1. A sampling timing signal generator for generating an enable timing control signal based on a predetermined system clock signal and a predetermined master clock signal, said sampling timing signal generator comprising: a replica DLL (Delayed Locked Loop) circuit configured to generate a predetermined reference bias voltage in synchronization with the system clock signal based on the system clock signal, and to output the reference bias voltage; and a delay signal generator circuit configured to operate for integers n (where “n” is an integer equal to or larger than one) and to generate a current obtained by dividing a reference current corresponding to the reference bias voltage by “n”, to use the generated divided current for charging an output load capacitance whereby the time for charging the output load capacitance constitutes a desired time delay, the desired time delay being a multiplication product of the number n and an arbitrary delay time to delay the master clock signal by the desired delay time, and to generate a delayed signal as an enable timing control signal, wherein said replica DLL circuit is configured to generate the reference bias voltage so that the desired delay time is equal to a cycle of the system clock signal, whereby said delay signal generator circuit generates the enable timing control signal.