Patent ID: 8806245
Filing Date: 2014-08-12
Classification: G06F,Y02D

Abstract:
1. An integrated circuit comprising: a plurality of memory arrays; and a control unit coupled to the plurality of memory arrays, wherein the control unit includes a first table storing predefined delay values for a first one of the plurality of memory arrays, wherein each of the delay values is indicative of a delay time between the beginning of a read cycle and enabling of the first memory to provide valid data, wherein each delay value corresponds to a unique one of a plurality of predefined operating points; wherein responsive to an indication of a change of operation to a new operating point of the plurality of predefined operating points, the control unit is configured to access the first table to determine a first delay value based on a new value of the operating point and further configured to set the first delay value for the first memory array responsive to determining the first delay value; wherein the operating point includes a supply voltage used to power each of the plurality of memory arrays; and wherein the control unit further includes a second table storing delay values for each of the operating points for a second memory array, wherein responsive to an indication of a change of operation to a new value of the operating point, the control unit is configured to access the second table to determine a second delay value based on a new value of the operating point and further configured to set the second delay value for at least one of the second memory array responsive to determining the given delay value.