Patent ID: 6163863
Filing Date: 2000-12-19
Classification: G11C

Abstract:
A test circuit in a memory device, the memory device including first and second memory banks having a redundancy plane defined between the two banks, each bank including at least one array of memory cells and the memory device including at least one data terminal, the test circuit comprising:a test mode terminal adapted to receive a test mode signal;a test data write path coupled across the redundancy plane defined between the two memory banks to a plurality of memory cells in the first and second banks; anda test data write circuit coupled to the test mode and data terminals, and to the test data write path, the test data write circuit operable in a test write mode when the test mode signal is active to transfer test data placed on the data terminal across the redundancy plane through the test data write path, storing the test data in a plurality of memory cells in the first and second banks.