Patent ID: 8462908
Filing Date: 2013-06-11
Classification: H03L,H03M,H04L

Abstract:
1. Apparatus for converting parallel data to serial data comprising: first serializer circuitry operable to receive, at a first clock rate, the parallel data and operable to output, at a second clock rate larger than the first clock rate, each bit of the parallel data, one bit after another in succession; buffer circuitry operable to receive each bit, one bit after another, being output by the first serializer and, for each bit, the buffer circuitry is operable to output a number of instances of that bit in parallel on a number of corresponding parallel leads, wherein the number is based on a ratio of the first clock rate and the second clock rate; and second serializer circuitry operable to receive signals from the number of parallel leads in parallel, and wherein said second serializer circuitry is operable to output each of those signals, one signal after another, on a serial output lead.