Patent ID: 8631274
Filing Date: 2014-01-14
Classification: G06F,G11C

Abstract:
1. A FLASH memory based solid state storage system comprising: (a) a printed circuit board; (b) a plurality of FLASH memory chips mounted to the printed circuit board, each FLASH memory chip divided into planes, each plane divided into blocks, each block divided into pages, and each page including a plurality of FLASH memory cells arranged to store a page of digital data, each FLASH memory chip including a chip-level communications bus interface capable of receiving and sending digital data to be stored in, and retrieved from, FLASH memory cells within the FLASH memory chip; and (c) a system controller mounted to the printed circuit board, the system controller including a plurality of system communication bus interfaces, each system communication bus interface being coupled by a system communications bus to one or more chip-level communication bus interfaces such that the system controller can provide digital data to and retrieve digital data from memory cells within the one or more FLASH memory chips, the system controller further including an external communications bus interface capable of receiving digital data to be stored within the storage system; (d) wherein the system controller is configured to store data received over the external communications bus in the plurality of FLASH memory chips in the form of page stripes, each page stripe comprising a plurality of pages stored in the FLASH memory chips, each of the plurality of pages being stored in a FLASH memory chip that is different from, but in the same plane and block as, each of the FLASH memory chips in which the other pages within the page stripe are stored, the plurality of pages making up each page stripe including: (i) a plurality of data pages, and (ii) at least one data protection page containing data protection information that may be used to reconstruct data stored in a data page within the page stripe that becomes corrupted or unavailable, the data protection information for a given page stripe being obtained by performing a bitwise logical operation on the information within the data pages for the given page stripe; (e) the page stripes stored by the system controller including: (i) a first page stripe stored within the plurality of FLASH memory chips, the first page stripe having N data pages and one data protection page, where N is an integer greater than three; and (ii) a second page stripe stored within the plurality of FLASH memory chips, the second page stripe having M data pages and one data protection page, where M is an integer less than N, wherein each of the data pages within the second page stripe is stored within a FLASH memory chip and a plain that also store data from a data page within the first page stripe.