Patent ID: 8815741
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A method, comprising: providing a semiconductor structure comprising a substrate and a first transistor element and a second transistor element, said first transistor element comprising a first gate structure formed over said substrate, said second transistor element comprising a second gate structure formed over said substrate; depositing a layer of a spacer material over said substrate and said first and second gate structures, wherein the deposited layer of spacer material has an intrinsic stress; forming a masking layer above the layer of spacer material, the masking layer covering a portion of the deposited layer of spacer material positioned above the second transistor and exposing a portion of the deposited layer of spacer material positioned above the first transistor; with the masking layer in position, implanting ions into said exposed portion of the layer of spacer material positioned above the first transistor, wherein the ions are irradiated to said semiconductor structure, the implantation of ions into said exposed portion of said layer of spacer material relaxing the intrinsic stress of at least a part of said exposed portion of said layer of spacer material positioned above the first transistor; after the ion implantation, removing the masking layer; and forming a sidewall spacer at a sidewall of said first gate structure and a sidewall spacer at a sidewall of said second gate structure from said layer of spacer material.