Patent ID: 6529861
Filing Date: 2003-03-04
Classification: G06F

Abstract:
A method for reducing power consumption of a domino circuit comprising:generating an initial output phase assignment for outputs of the domino circuit; computing a first power consumption of the domino circuit using the initial output phase assignment output of the circuit; generating a plurality of additional output phase assignments; and for each one of the plurality of additional output phase assignments, performing the following: evaluating a power consumption of the domino circuit using each of the plurality additional output phase assignments; comparing the power consumption of the domino circuit using each of the plurality additional output phase assignments to the first power consumption; selecting either the initial output phase assignment or one of the plurality additional output phase assignments which results in a lowest power consumption by the domino circuit compared to the first power consumption; wherein evaluating the power consumption comprises: partitioning the domino circuit into combinational blocks; computing a signal probability at each node of the domino circuit; computing power at each of the nodes of the domino circuit, wherein the power at each of the nodes is equal to the signal probability times a load capacitance minus a penalty value; and summing the power at each of the nodes of the domino circuit.