Patent ID: 6665215
Filing Date: 2003-12-16
Classification: G11C

Abstract:
A memory cell reading device comprising:a differential amplifier having a first input connected to a memory cell to be read and a second input connected to a reference cell associated with the memory cell to be read; and a precharging circuit connected to an output of said differential amplifier for precharging the output to a predetermined voltage level during a reading phase of the memory cell, said precharging circuit comprising an upper arm comprising a PMOS transistor configured as a diode, and an activation PMOS transistor connected to said PMOS transistor and being controlled by a first precharging signal, and a lower arm connected to said upper arm and comprising an NMOS transistor configured as a diode, and an activation NMOS transistor connected to said NMOS transistor and being controlled by a second precharging signal.