Patent ID: 7660972
Filing Date: 2010-02-09
Classification: G06F

Abstract:
1. A method for processing data in a programmable processor, the method comprising: decoding and executing instructions that instruct a computer system to perform operations, at least some of the instructions including group floating-point instructions each operating on first and second registers partitioned into a plurality of floating point operands, the floating point operands having a defined precision and the defined precision being dynamically variable, having a defined result precision which is equal to the defined precision of the operands; at least one group floating-point instruction being a group floating-point multiply-and-add instruction, further operating on a third register partitioned into a plurality of floating-point operands, operable to multiply the plurality of floating-point operands in the first and second registers and add the plurality of floating-point operands in the third register, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for the plurality of floating point values.