Patent ID: 7788470
Filing Date: 2010-08-31
Classification: G06F

Abstract:
1. A method for supporting out of order execution of instructions, comprising: coupling a microprocessor to a coprocessor via a controller; receiving instructions by the microprocessor and the controller; generating by the microprocessor indices respectively associated with the instructions; the controller including a first queue and a second queue; first queuing the instructions and the indices in the first queue; the first queuing including steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices; popping the instructions from the first queue for execution by the coprocessor; and selectively popping off the instructions from the first queue out of order with respect to an order in which the instructions are received into the first queue, wherein the first queuing including steering the instructions and the indices associated therewith comprises: