Patent ID: 7617577
Filing Date: 2009-11-17
Classification: G11C,H01G,H01L,Y10T

Abstract:
1. A method of forming a digital variable capacitor, comprising: (a) disposing and patterning a relatively thin metal layer on a relatively thick wafer substrate to form a signal electrode and a ground plane region including a notched region; (b) disposing and patterning a sacrificial layer over portions of the signal electrode and the ground plane region; (c) etching a dimple in the sacrificial layer over and substantially aligned with the notched region defined on the ground plane region; (d) disposing a relatively thick metal layer over the signal electrode and the sacrificial layer; and (e) etching away the sacrificial layer including the dimple for forming at least one cantilever having a first end coupled to the signal electrode and a second end suspended over a predetermined portion of the ground plane and including a protrusion formed on a bottom surface of the second end having a position and dimension corresponding to a position and dimension of the dimple formed in the sacrificial layer and the protrusion being substantially aligned with the notched region defined on the ground plane so that the protrusion can be positioned into the notched region to contact the substrate for providing a positive downward stop for the second end of the cantilever, wherein the signal electrode is adapted to receive one or more control values operative to actuate the at least one cantilever to position the second end of the at least one cantilever in relative close proximity to the ground plane as defined by the protrusion being positioned into the notched region of the ground plane to contact the substrate for providing at least a first predetermined capacitance between the signal electrode and the ground plane.