Patent ID: 6635525
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method of making an integrated circuit having a device layer of semiconductor with a device layer thickness of less than 100 nm above an array insulating layer and containing an array of DRAM cells disposed in a first subset of DRAM cells and a second subset of DRAM cells, including a trench capacitor formed at an edge of said DRAM cells and connected by a buried strap to a horizontal pass transistor formed in said device layer and displaced laterally from said trench capacitor, comprising the steps of:forming said set of trench capacitors by etching trenches through said device layer and array insulating layer and depositing center electrodes insulated by a capacitor insulator; recessing said center electrodes below a bottom surface of said device layer; etching laterally into said array insulating layer outside said trenches, thereby exposing a contact area on said bottom surface of said device layer; depositing strap conductive material in said trenches to a level above said bottom surface of said device layer, whereby said strap conductive material makes electrical contact with said bottom surface to form said buried straps; depositing top insulating material having a top insulator thickness extending up to a surface of said device layer in said trenches above said strap conductive material, whereby said top insulator thickness is approximately equal to said device layer thickness; and forming a set of isolating trenches by removing said device layer and said array insulating layer outside said trenches and said cell pass transistors, to a depth of at least said bottom of said buried straps, whereby only that portion of said buried strap inside said trenches and underneath said transistors remains and said buried straps are isolated from corresponding buried straps in adjacent cells by said isolating trenches; forming a set of horizontal cell pass transistors in said device layer having cell electrodes, transistor gates disposed above said device layer and connected to a first subset of interconnect lines and internal electrodes in contact with said buried straps through said contact area and separated from an adjacent trench by said isolating trenches.