Patent ID: 6545931
Filing Date: 2003-04-08
Classification: G11C

Abstract:
A semiconductor memory device capable of operating in a normal mode for accessing data and in a refresh mode for holding data, comprising:a power source node for supplying a prescribed voltage; a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns and a repeating circuit group including a plurality of repeating circuits each having a common function for performing an operation related to a memory cell selection; a plurality of power source switch circuits provided corresponding to said plurality of memory blocks, each of the power source switch circuits for coupling said power source node and a repeating circuit group in a corresponding memory block, said plurality of power source switch circuits each causing a first current flow in a selected state and a second current flow smaller than said first current in a non-selected state; and control circuitry for selectively driving said plurality of power source switch circuits into a selected state according. to an address signal such that the number of selected power source switch circuits is different between said normal mode and said refresh mode.