Patent ID: 7299389
Filing Date: 2007-11-20
Classification: G01R

Abstract:
1. A test circuit for an integrated circuit comprising a plurality of macro blocks, the test circuit comprising: a first selector having a first input to which an output signal from a first macro block is input and a second input to which a test input signal for a second macro block is input; and a second selector having a first input to which an output signal from the first selector is input and a second input to which an output signal from the second macro block is input, wherein during a first test mode for testing the first macro block, the first selector outputs to the first input of the second selector the output signal that has been input from the first macro block to the first input of the first selector, and the second selector outputs to the first macro block the output signal that has been input from the first selector to the first input of the second selector, and wherein during a second test mode for testing the second macro block, the first selector outputs to the second macro block the test input signal for the second macro block that has been input to the second input of the first selector, and the second selector outputs the output signal from the second macro block that has been input to the second input of the second selector, as a test output signal for the second macro block.