Patent ID: 6701396
Filing Date: 2004-03-02
Classification: G06F

Abstract:
A data burst transfer circuit comprising:an oscillation circuit which outputs n (where n is an integer of 2 or above) timing signals of mutually different phases, said oscillation circuit having a self-oscillation circuit which self-oscillates at a specific frequency; a frequency divider which outputs the n timing signals based on an output signal of said self-oscillation circuit; and a control circuit which controls the operation of said self-oscillation circuit and said frequency divider based on a starting signal and a timing signal output from said frequency divider; one or a plurality of parallel-serial conversion circuits which convert n-bit parallel signals into serial signals based on the n timing signals; one or a plurality of serial-parallel conversion circuits which convert serial signals into n-bit parallel signals based on the n timing signals; a signal line which transmits serial signals from the parallel-serial conversion circuits to the serial-parallel conversion circuits; and a signal line which supplies the n timing signals from said oscillation circuit to said parallel-serial conversion circuits and said serial-parallel conversion circuits respectively.