Patent ID: 6900549
Filing Date: 2005-05-31
Classification: H01L,Y10T

Abstract:
1. A semiconductor assembly comprising: a first semiconductor die with a top and bottom surface; at least one second semiconductor die having a perimeter, including four sides, and a top and bottom surface, said bottom surface having a smaller area than said top surface of said first semiconductor die, said at least one second semiconductor die being secured at its bottom surface to said top surface of said first semiconductor die by a flowable adhesive material which does not extend past any one of the sides of said perimeter of said at least one second semiconductor die, said top surface of said first semiconductor die having at least one electrical contact area at a distance outside said perimeter of said at least one second semiconductor die, said at least one second semiconductor die being in electrical communication with said at least one electrical contact area; and an encapsulating material for encapsulating said at least one second semiconductor die, electrical communication, and at least a portion of said first semiconductor die, said encapsulating material filling a space between said bottom surface of said at least one second semiconductor die and said top surface of said first semiconductor die.