Patent ID: 9204533
Filing Date: 2015-12-01
Classification: H05K

Abstract:
1. An asymmetrical multilayer substrate comprising: a core layer in which a through-hole for passing through and connecting upper and lower portions thereof is formed; a first pattern layer formed on one of upper and lower portions of the core layer, and including a first signal line pattern connected with the through-hole; a second pattern layer formed on the other of the upper and lower portions of the core layer, and including a second metal plate providing a capacitance between itself and a pattern of an adjacent outer pattern layer and a second routing line pattern connected with the through-hole; a first insulating layer formed on the second pattern layer so as to have a thinner thickness than a thickness of the core layer, and including a first via connected with the second routing line pattern; and a third pattern layer formed on the first insulating layer, and including a third signal line pattern connected with the first via, wherein an impedance transformation circuit including an impedance load on a transmission line and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer, and the impedance load includes impedances of the through-hole, the second routing line pattern, and the first via which are forming the transmission line, and the parasitic capacitance load includes the capacitance provided by the second metal plate.