Patent ID: 7962819
Filing Date: 2011-06-14
Classification: G01R,G06F

Abstract:
1. A method for triggering a soft reset of a test mode being executed on an integrated circuit chip, comprising: coupling input-output pins of an integrated circuit chip to tester connections, the input-output pins including a scan-in pin and a scan clock pin; defining a test program for testing the integrated circuit chip in the test mode, the test program including program patterns consistent with the test mode that are defined to occur during a period of testing and a soft-reset pattern that is defined to occur after the period of testing; executing the test program; during execution of the test program, sampling a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin; and upon executing the soft-reset pattern of the test program, detecting a bit match from the sampled scan clock waveform, the bit match triggering the soft reset of the test mode being executed on the integrated circuit chip.