Patent ID: 6317362
Filing Date: 2001-11-13
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells formed on semiconductor substrate;a plurality of row lines and column lines for selecting a specific memory cell of said plurality of memory cells;first voltage applying means for passing a cell current through the specific memory cell selected by said plurality of row lines and column lines;a plurality of reference cells each having the same structure as that of each of the plurality of memory cells and formed on said semiconductor substrate;second voltage applying means for passing a reference current through each of said reference cells; andsense amplifier means for comparing the cell current and the reference current, whereinsaid plurality of memory cells include a plurality of memory cell groups arranged in plural different source/drain directions, and cell-layout is set so that the reference cells to each of the memory cell groups are arranged in the same direction as the memory cells in the corresponding memory cell group.