Patent ID: 7015723
Filing Date: 2006-03-21
Classification: H03K

Abstract:
1. A logical control element for providing a window signal active between assertion of a control signal and a time at which a logical combination of one or more other signals assumes a predetermined state, said logical control element comprising: a dynamic logic tree formed from one or more transistor ladders comprising transistors having series connected channels coupled between a summing node and a first power supply rail corresponding to a first logical state, and wherein gates of said transistors are connected to said one or more other signals; a precharge circuit connected to said summing node and a second power supply rail for setting said summing node to a precharge voltage level corresponding to a second logical state opposite from said first logical state, said precharge circuit having an input coupled to said control signal, whereby said summing node is held in said second logical state while said control signal is deasserted; an inverter having an input coupled to said summing node and an inverter output providing said window signal at an output of said logical control element; and a static override circuit having an input coupled to said control signal and an output connected to said inverter output for forcing said inverter output to a voltage level corresponding to said second logical state while said control signal is active, whereby said output of said control element is held in a first logical output state corresponding to an evaluated state of said control element until said control signal is asserted, and wherein said output of said control element is thereafter held in an opposite state by said inverter until said logical combination of said one or more other signals assumes said predetermined state.