Patent ID: 7234027
Filing Date: 2007-06-19
Classification: G06F

Abstract:
1. A method of maintaining a cache memory in a computer system having a first processor, a first memory, and at least a first cache between the first processor and the first memory, the method comprising: performing a first memory access to the first memory by the first processor; storing a first cache line from the first memory into the first cache; performing an instruction that enables a cache-invalidate function to be performed by the first processor upon execution of a resource-synchronization instruction; performing, within the first processor, a resource-synchronization instruction that operates on a first memory location in the first memory, wherein performing the resource synchronization instruction includes modifying the first memory location in the first memory and invalidating at least the first cache line in the first cache during execution of the resource synchronization instruction on the first memory location in the first memory; performing a second memory access to the first memory by the first processor; storing a second cache line from the first memory into the first cache; performing an instruction that disables the cache-invalidate function from being performed by the first processor upon execution of the resource-synchronization instruction; performing the resource-synchronization instruction on a second memory location in the first memory, wherein performing the resource synchronization instruction includes modifying the second memory location in the first memory without invalidating the second cache line in the first cache.