Patent ID: 9142680
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode, and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode is connected to the drain electrode through the contact hole, wherein the gate line comprises an electrode portion and a line portion, the electrode portion being the portion of the gate line overlapping with the channel portion and the line portion intersecting the data line, wherein the gate line extends in a lengthwise direction, wherein the channel portion of the semiconductor layer and the contact hole both overlap a centerline of the gate line in a plan view of the substrate, the centerline of the gate line extending in a direction the line portion of the gate line extends and crossing the line portion of the gate line, and wherein the drain electrode includes an opening disposed between two portions of the drain electrode and exposing a portion of the semiconductor layer.