Patent ID: 8163622
Filing Date: 2012-04-24
Classification: G11C,H01L

Abstract:
1. A method for creating NAND flash memory, comprising: creating stacked gate structures of a NAND string on a substrate, each stacked gate structure comprising a floating gate and a control gate positioned over the floating gate; performing source implantation at a first implantation angle to source/drain regions in the substrate between said stacked gate structures, at source sides of each of said stacked gate structures, said source implantation includes n-type and p-type materials implanted under different angles; and performing drain implantation at a second implantation angle to the source/drain regions in the substrate between said stacked gate structures of said NAND string, at drain sides of each of said stacked gate structures, said second implantation angle is different than said first implantation angle, and said drain implantation includes n-type and p-type materials implanted under different angles, the performing source implantation and the performing drain implantation create an asymmetric doping profile in each of the source/drain regions in the substrate, each source/drain region is between adjacent stacked gate structures in said NAND string.