Patent ID: 8222922
Filing Date: 2012-07-17
Classification: G11C,H03K

Abstract:
1. A logic device comprising: an array of read-only memory (ROM) cells comprising transistors, wherein each cell stores a value that is read from the cell to provide an output in response to an input pertaining to a logic design; a plurality of wordlines coupled to the array of ROM cells; the cells storing a value of ‘1’ are configured in parallel and coupled to a first column select transistor; the cells storing a value of ‘0’ are configured in parallel and coupled to a second column select transistor, wherein the output is the value of ‘1’ or ‘0’ based on a cell when a bitline is selected by the first column select transistor and the second column select transistor, wherein said first and second column transistors are pass transistors or transmission gates, and wherein said first column select transistor only passes through a value of ‘1’ and said second column select transistor only passes through a value of ‘0’.