Patent ID: 6489823
Filing Date: 2002-12-03
Classification: G11C,H03L

Abstract:
A semiconductor device comprising:an internal clock generation circuit generating an operating clock signal in response to an external clock signal, said internal clock generation circuit including a phase comparator comparing a phase of said external clock signal and that of said operating clock signal with each other, and a clock delay portion responsive to an output of said phase comparator for delaying a first internal clock signal to output said operating clock signal, said clock delay portion having a clock conversion portion generating from said first internal clock a second internal signal and a third internal signal complementary to said second internal signal, and a clock output portion responsive to the output of said phase comparator for changing by one stage a number of gate stages to be passed through, said clock output portion outputting said operating clock in response to said second internal clock signal when said number of gate stages is an odd number of stages, said clock output portion outputting said operating clock signal in response to said third internal clock signal when said number of gate stages is an even number of stages; and an internal circuit operating in response to said operating clock signal.