Patent ID: 8972636
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. A memory interface chip for connecting to a signal source and receiving a data signal, the memory interface chip corresponding to a first memory having a first memory structure or a second memory having a second memory structure, the memory interface chip comprising: a data output unit, only connected to one of the first memory and the second memory and correspondingly having only a data path, the data output unit including: a control module, connected to the data output unit, wherein the control module closes off the second output channel and the data path is between the first output channel and the first memory when the data output unit is connected to the first memory, and wherein the control module closes off the first output channel and the data path is between the second output channel and the second memory when the data output unit is connected to the second memory, wherein the data output unit further includes a post-driver connected to the first output channel, the second output channel, and the first/second memory, the post-driver receives the first output signal from the first output channel or the second output signal from the second output channel and then transmits the signal received to the memory connected to the data output unit, and the first output channel includes: the second output channel includes: wherein when the data output unit receives a first interface voltage corresponding to a first memory type from the memory connected to the data output unit, the control module identifies that the memory is the first memory type and forces the second pre-driver into a high output impedance state based on the first memory type; when the data output unit receives a second interface voltage corresponding to a second memory type from the memory connected to the data output unit, the control module identifies that the memory is the second memory type and forces the first pre-driver into the high output impedance state based on the second memory type, the control module disables the second pre-driver using thin-oxide layer transistors and the channel switch of the second output channel to prevent the second pre-driver and the channel switch of the second output channel from being damaged by an overstress produced by voltages higher than a core voltage of 1.2 volts to maintain a normal operation of the memory interface chip.