Patent ID: 6295241
Filing Date: 2001-09-25
Classification: G11C

Abstract:
A dynamic semiconductor memory comprising:parallel word lines provided on a substrate;parallel bit lines provided on the substrate to insulatively cross with said word lines, said bit lines including a bit-line pair having a first bit line and a second bit line;memory cells connected to crossing points of said word lines and said bit lines, said memory cells comprising voltage-controlled unipolar transistors and capacitors; andsense amplifier means connected to said bit-line pair, for sensing and amplifying a difference between potentials on said first and second bit lines when a memory cell connected to said bit-line pair is selected from among the memory cells in a data readout mode, said sense amplifier means comprising a BIMOS differential amplifier circuit having a voltage-controlled unipolar transistor and current-controlled bipolar transistors functioning as driver elements and each of which have a base electrode;said sense amplifier means further comprising a CMOS current mirror circuit connected to said first and second bit lines and said base electrodes of said current-controlled bipolar transistors.