Patent ID: 6736709
Filing Date: 2004-05-18
Classification: B24B,B24D

Abstract:
A polishing pad useful for planarizing a surface of a semiconductor wafer, the pad comprising:a polishing layer for planarizing the surface, wherein the polishing layer has the following: i. a thickness of about 250 to 5,100 micrometers; ii. a hardness of about 40-70 Shore D; iii. a tensile Modulus of about 160-2,000 MPa at 40Â° C.; iv. an Energy Loss Factor, KEL, of about 100-1,000 (1/Pa at 40Â° C.); and v. an Elastic Storage Modulus, Eâ€², ratio at 30Â° C. and 90Â° C. of about 1-5 the polishing layer having a macro-texture comprising a groove pattern having one or more grooves; the groove pattern having: i. a groove depth of about 75 to about 2,540 micrometers: ii. a groove width of about 125 to about 1,270 micrometers, and iii. a groove pitch of about 500 to 3,600 micrometers; the groove pattern being from the group consisting of random, concentric, spiral, cross-hatched, X-Y grid, hexagonal, triangular, fractal and combinations thereof.