Patent ID: 8202777
Filing Date: 2012-06-19
Classification: H01L

Abstract:
1. A method, comprising: forming a first plurality of recesses in a crystalline semiconductor region, said first plurality of recesses being offset from a gate electrode structure by a first sidewall spacer formed on sidewalls of said gate electrode structure, said first plurality of recesses extending to a first depth; forming a second plurality of recesses in said crystalline semiconductor region, said second plurality of recesses being offset from said gate electrode structure by a second sidewall spacer formed on said first sidewall spacer, said second plurality of recesses extending to a second depth that is greater than said first depth; forming a strain-inducing semiconductor alloy in said first and second recesses by performing a selective epitaxial growth process, wherein forming said first plurality of recesses comprises forming a first spacer layer above said gate electrode structure and a second gate electrode structure formed above a second crystalline semiconductor region, forming a first mask to cover said first spacer layer formed above said second gate electrode structure and said second semiconductor region, forming said first sidewall spacer from said first spacer layer and removing material from said crystalline semiconductor region in the presence of said first sidewall spacer and said first mask, wherein forming said second plurality of recesses comprises removing said first mask, depositing a second spacer layer and forming said second sidewall spacer from said second spacer layer; and forming a second mask above said second gate electrode structure and said second crystalline semiconductor region prior to forming said second sidewall spacer.