Patent ID: 8179346
Filing Date: 2012-05-15
Classification: G09G

Abstract:
1. A display panel driving circuit for driving a display panel, where the display panel has Y successive gate lines, M+1 successive data lines crossing the Y gate lines forming a plurality of crossing points of the Y gate lines and M+1 data lines, where M and Y are positive integers, and a plurality of display cells, wherein the plurality of display cells are positioned at corresponding crossing points of the Y gate lines and M+1 data lines thereby to form a matrix with a plurality of columns {i=1, 2, . . . , M+1}, wherein display cells within column i positioned at the crossing points of the i-th data line and the (2j+1)-th or (2j+2)-th gate line are connected to the i-th data line, where j=0, 2, 4, . . . , <[Y/2], and display cells within column i+1 positioned at the crossing points of the (i+1)-th data line and the (2j+1)-th or (2j+2)-th gate line are connected to the (i+1)-th data line, where j=1, 3, . . . , <[Y/2]+1, and wherein the i-th data line and the (i+1)-th data line have opposite data signal polarities, respectively, comprising: (i) a printed circuit board (“PCB”); (ii) an input interface adapted on the PCB to receive input video signal; (iii) a timing controller adapted on the PCB to control timing signal for the display panel; (iv) a plurality of first source drivers; and (v) at least one second source driver, wherein the plurality of first source drivers and the at least one second source driver are configured such that each of the plurality of first source drivers has N outputs to respectively drive N data lines, and the at least one second source driver had N+1 outputs to respectively drive N+1 data lines, where N is a positive integer no greater than M, wherein each of the M+1 data lines is driven by a respective, single source driver of the plurality of first source drivers and the at least one second source driver, and wherein the display cells within column i positioned at the crossing points of the i-th data line and the (2j+1)-th or (2j+2)-th gate line, where j=0, 2, 4, . . . , <[Y/2], and i=1, 2, . . . , M, receive data signals from corresponding data lines 1 through M, respectively, and the display cells within column (i+1) positioned at the crossing points of the (i+1)-th data line and the (2j+1)-th or (2j+2)-th gate line, where j=1, 3, . . . , <[Y/2]+1, and i=1, 2, . . . , M, receive shifted data signals from the data lines 2 through M+1, respectively.