Patent ID: 8471336
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device, comprising: a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET; a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of a MISFET provided with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode; and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer of the one of the plurality of ones of the MISFET through an isolation, respectively, wherein the MISFET comprises a drain diffusion layer, a source diffusion layer, a dummy gate electrode, and a dummy diffusion layer, and wherein the source diffusion layer, the dummy gate electrode, and the dummy diffusion layer are arranged in that order in at least one region.