Patent ID: 6219749
Filing Date: 2001-04-17
Classification: G11C

Abstract:
A system comprising:a common bus;a plurality of cascaded content addressable memory (CAM) arrays, each CAM array comprising encoding means and an array of core cells, of w words.times.b bits, associated with the encoding means, each CAM array being able to provide, through its respective encoding means, a hit signal and a match address signal resulting from a search operation in response to a clock signal; anda plurality of logic circuits, each logic circuit being associated with a respective CAM array to receive the hit signal and the match address signal provided therefrom, each logic circuit comprising:(i) timing signal generation means for generating a self-timed signal in response to the clock signal;(ii) hit propagation circuit for providing a propagation-out hit signal to a downstream logic circuit, by logically combining:a propagation-in hit signal provided from an upstream logic circuit;the hit signal provided from the respective CAM array; andthe self-timed signal provided from the timing signal generation means; and(iii) match address transfer circuit for transferring the match address signal provided from the respective CAM array to the common bus.