Patent ID: 7180785
Filing Date: 2007-02-20
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a plurality of sectors each including a memory cell array; a plurality of word line drivers provided in each one of the sectors to drive respective word lines; sector switches provided one for each sector, each sector switch being connected to the plural word line drivers in the corresponding sector, adapted to provide a negative voltage to be applied to the word lines to the plural word line drivers when the corresponding sector is selected for an erase operation, and only including transistors directly connected to an output signal line to provide the negative voltage to the plural word line drivers; and a decoding circuit shared by one or more sectors, adapted to control the sector switches to allow a sector switch in a selected sector to output the negative voltage and allow a sector switch in an unselected sector to output a voltage different from the negative voltage.