Patent ID: 8527974
Filing Date: 2013-09-03
Classification: G06F

Abstract:
1. A method, in a data processing system, for optimizing regular memory references in computer code, comprising: parsing the computer code to identify memory references in the computer code; classifying the memory references in the computer code as either regular memory references or irregular memory references, wherein accesses to a software cache by regular memory references are controlled by a high locality cache mechanism and accesses to a software cache by irregular memory references are controlled by a transaction cache mechanism; transforming the computer code, by a compiler, to generate transformed computer code in which regular memory references access a storage of the software cache of the data processing system through the high locality cache mechanism of the software cache; and mapping, by the compiler, regular memory references to the high locality cache mechanism by injecting explicit control code into the computer code to direct software cache access through the high locality cache mechanism, wherein regular memory references are memory references with high spatial locality and have a constant strided access pattern, and wherein irregular memory references are memory references that do not expose a high spatial locality or constant strided access pattern.