Patent ID: 6157541
Filing Date: 2000-12-05
Classification: H01L,H05K

Abstract:
A stack arrangement for first and second semiconductor memory chips, comprising:first and second semiconductor memory chips;a flexible carrier film made of an electrically insulating material;a first configuration of inner terminals onto which first contacts and second contacts of the first semiconductor memory chip are bonded;a second configuration of inner terminals onto which first contacts and second contacts of the second semiconductor memory chip are bonded;a first group of conductors on the carrier film which traverse a strip-shaped bonding region associated with the carrier film and which connect to the inner terminals connected to the first contacts of the first and second semiconductor memory chips which are jointly controllable;a second group of conductors on the carrier film which extend into the strip-shaped bonding region and which connect to the inner terminals connected to the second contacts of the first and second semiconductor memory chips which are selectively controllable; andthe flexible carrier film being folded about an elastic line which is situated in the strip-shaped bonding region such that the two semiconductor memory chips are arranged above one another in stacked fashion, and the individual first and second conductor groups in the folded bonding region form outer contacts which are situated in adjacent fashion in one row.