Patent ID: 9195540
Filing Date: 2015-11-24
Classification: G06F,G11C

Abstract:
1. A method for accessing a memory array comprising: grouping bits for error correction such that (i) bits obtained by accessing a multiple bit-per-cell memory element having at least two bits at a row address and a column address are divided across two groupings and (ii) fewer bits from the multiple bit-per-cell memory element are included in any grouping able to be corrected using an error-correcting algorithm; receiving a data-access request to access a first bit in the multiple bit-per-cell memory element, the first bit belonging to a first grouping; accessing all of the bits in the multiple bit-per-cell memory element, wherein a second bit in the multiple bit-per-cell memory element belongs to a second grouping different from the first grouping; and storing the first and second bits in at least one buffers, thereby avoiding having to re-access the row address and column address at a later point in time to access the second bits.