Patent ID: 6397310
Filing Date: 2002-05-28
Classification: G06F

Abstract:
Method for controlling write access to a memory of a digital data processing circuit, which circuit can be operated in an initialisation mode before operating in a normal processing mode, comprising the steps:combining a write enable signal, in particular by using an AND function, with an associated write allowance register output signal for providing a protected write enable signal for said memory; controlling writing of data into said memory in response to said protected write enable signal for avoiding storing into said memory invalid or unintended address values or pointers accidentally available on a common address bus, instead of storing into said memory from said common address bus valid or intended address values or pointers for controlling the operation of said digital data processing circuit during said normal processing mode; inverting said write allowance register output signal; and combining said write enable signal and the inverted write allowance register output signal, in particular by using a further AND function, to form a write attempt interrupt signal for controlling an address capturing register storing a current invalid or unintended address value or pointer from said common address bus.