Patent ID: 6136701
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A method for manufacturing a contact structure of a semiconductor device, comprising the steps of:sequentially forming a first oxide layer pattern and an isolation mask layer pattern on a semiconductor substrate;forming a trench in the semiconductor substrate, said trench having a vertical depth of 0.8-1.0 .mu.m in a first direction substantially perpendicular to a principle surface of said semiconductor substrate and having a horizontal width of 0.4 .mu.m in a second direction substantially parallel to said principle surface of said semiconductor substrate;filling said trench with an insulating layer;removing said first oxide layer pattern and said isolation mask layer pattern;forming a second oxide layer over the entire surface of said semiconductor substrate;etching a portion of said insulating layer and said second oxide layer, thereby forming a trench having a groove;forming a conductive layer pattern on said second oxide layer and said insulating layer and thus filling inside the groove; andforming an impurity-doped region connected to a side portion of said conductive layer pattern inside the groove through a side contact region formed on at least one side face of said impurity doped region.