Patent ID: 8647971
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit, the method comprising: forming a P-type anode region in a surface of an N-type layer; forming a first mask with an opening exposing an N-type Schottky region of the surface and an adjoining portion of the anode region; applying a first material and forming a first silicide layer of the first material on the exposed portions of the Schottky and anode regions; forming a second mask with an opening exposing a portion of the P-type anode region not having the first silicide layer; applying a second material different from the first material and forming a second silicide layer of the second material on the exposed portion of the P-type anode region not having the first silicode layer, the first and second silicide layers formed spaced entirely apart from each other, and forming an ohmic contact to the second silicide layer on the anode region and an ohmic contact to the N-type layer.