Patent ID: 6959428
Filing Date: 2005-10-25
Classification: G06F

Abstract:
1. A method to design an integrated circuit, comprising: (a) inputting an application set having a design database, the design database describing a transistor fabric, and/or at least one addressable hardmac register, and/or at least one addressable hardmac memory; (b) inputting a description of at least one addressable register and/or at least one addressable memory, implementable from the transistor fabric and/or from the addressable hardmacs register and/or from the addressable hardmac memory on the integrated circuit; (c) inputting a configuration of a bus to connect the at least one addressable register and/or the at least one addressable memory with each other and/or with at least one component that is implementable from the design database; (d) generating interconnect register transfer logic to connect the at least one addressable register and/or the at least one addressable memory with each other and/or with the at least one component on the bus; and (e) generating an address map of the at least one addressable register and/or the at least one addressable memory.