Patent ID: 8741718
Filing Date: 2014-06-03
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a gate-level layer on a semiconductor substrate, wherein a planar top surface of said gate-level layer extends over an entirety of said gate-level layer, and gate stacks of a gate dielectric and a gate electrode, gate spacers, and a planarized dielectric layer complimentarily fill portions of said gate-level layer that is within a distance from said planar top surface of said gate-level layer; forming a contact-level dielectric layer over said gate-level layer; forming a substrate contact via hole through a portion of said contact-level dielectric layer and a portion of said planarized dielectric layer to a semiconductor material portion located in or directly on said semiconductor substrate; forming a metal semiconductor alloy portion on said semiconductor material portion; forming a gate contact via hole through another portion of said contact-level dielectric layer overlying one of said gate electrodes; and forming a substrate contact structure directly on said metal semiconductor alloy portion and a gate contact structure directly on said one of said gate electrodes.