Patent ID: 7408824
Filing Date: 2008-08-05
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array which includes a plurality of blocks each having memory cells arranged in a matrix and which has a ferroelectric capacitor one electrode of which is connected to a plate line and a transistor whose drain terminal is connected to the other electrode of the ferroelectric capacitor, whose gate terminal is connected to a word line, and whose source terminal is connected to a bit line; a spare memory cell array which is for replacing a block including a defective bit in the memory cell array; a syndrome computing circuit which is supplied with redundancy information and is controlled and to which data read from the memory cell array, data read from the spare memory cell array, and parity bits read from the memory cell array are input and which is configured to calculate syndromes; a spare data replacing circuit which is configured to carry out the operation of replacing the data read from the memory cell array with the data read from the spare memory cell array in parallel with the syndrome calculation; and an error checking and correcting circuit to which the syndromes calculated at the syndrome computing circuit and the data replaced at the spare data replacing circuit are input and which is configured to correct the error if an error has occurred in a plurality of items of data read, wherein the syndrome computing circuit calculates the syndromes of the data read from the memory cell array, replaces the data read from the memory cell array with the data read from the spare memory cell in parallel with the syndrome calculation, and calculates the syndromes of the data read from the memory cell in the spare memory cell array, and when the syndromes of the data read from the memory cell array are calculated at the syndrome computing circuit, an input from the spare data replacing circuit to the error checking and correcting circuit is set to a level uninvolved in the output of the syndrome computing circuit.