Patent ID: 6833725
Filing Date: 2004-12-21
Classification: G01R,G11C

Abstract:
A semiconductor characteristic evaluation apparatus comprising:a plurality of measurement units arranged on a chip, on which a plurality of measured patterns of components configuring a semiconductor integrated circuit and varying in kind from component to component are mounted; a measurement bus group arranged above the plurality of measurement units and connected to the plurality of measured patterns to configure a measurement circuit system in accordance with measured items of the components; a plurality of measurement pads, on the chip, which are arranged in a region other than an arrangement region of the plurality of measurement units and to which a measuring device is connected; a plurality of selection switches which select, in accordance with the measured items of the components, a measurement bus group configuring the measurement circuit system in accordance with the measured items and which connect the group to the plurality of measurement pads; and a control circuit which electrically controls switching of the plurality of selection switches in accordance with the measured items of the components.