Patent ID: 6277695
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method of forming a vertical planar MOSFET comprising:providing a semiconductor body of a first conductivity type;forming a gate oxide layer on a surface of the semiconductor body;forming a conductive gate layer, the conductive gate layer being located at least partially on the gate oxide layer;removing a portion of the conductive gate layer to form a gate;implanting a first dopant of a second conductivity type into the semiconductor body to form a first PN junction between the body region and a portion of the semiconductor body doped to the first conductivity type, the first dopant not entering the semiconductor body beneath the gate such that the first PN junction is aligned with an edge of the gate;heating the semiconductor body to drive in the first dopant, thereby causing the first dopant to diffuse such that the first PN junction extends to a region beneath the gate;implanting a second dopant of the first conductivity type into the semiconductor body to form a source region, a second PN junction being formed between the source region and the body region, a region between the first and second PN junctions beneath the gate comprising a channel region;forming an oxide layer, the oxide layer overlying the gate and the source region;anisotropically etching the oxide layer so as expose a portion of the source region while leaving a spacer portion of the oxide layer on a sidewall of the gate, thereby forming a contact opening; andfilling the contact opening with a conductive material so as to form an electrical contact to the source region.