Patent ID: 6957373
Filing Date: 2005-10-18
Classification: G11C

Abstract:
1. An address generator for generating addresses for testing an addressable circuit, having: (a) at least one base address register for buffer-storing a base address, the base address register in each case being assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values; (b) a first multiplexer circuit, which, in a manner is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested, wherein the base address register is switched through by the first multiplexer circuit; (c) a second multiplexer circuit, which, in a manner is dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which, in a manner is dependent on an offset register selection control signal, through-connects an offset register of the through-connected offset register group to a second input of the addition circuit; and (d) the addition circuit adding the address present at the first input to the relative address value present at the second input to form an address which is buffer-stored in the base address register.