Patent ID: 6192482
Filing Date: 2001-02-20
Classification: G06F

Abstract:
A data processing system comprising in combination:a host processor;a peripheral controller;an input-output sub-element physically located remotely from said host processor;a self-timed interface link coupling host commands and data directly between said host processor to said input-output sub-element and said peripheral controller;said self-timed interface link including a transmitting node for transmitting a digital data and a clock signal and a receiving node for receiving said digital data and said clock signal, said transmitting node connected to said receiving node by a parallel data bus to individual lines of which respective bits of digital data streams are coupled in parallel by said clock signal at said transmitting node; andsaid bus including a separate line for transmitting said clock signal to said receiving node, and said receiving node including means to phase align said respective bits on each of said lines separately with respect to said clock signal transmitted to said receiving node.