Patent ID: 7754400
Filing Date: 2010-07-13
Classification: G03F

Abstract:
1. A method for determining an acceptable reticle tolerance for a reticle used to produce an integrated circuit layout, comprising: specifying a wafer target CD and wafer CD tolerance for the integrated circuit layout; providing a reticle target CD for the reticle producing the wafer target CD; selecting a critical reticle pattern pitch for the reticle target CD, wherein for said critical pattern pitch a relationship between wafer CD and illumination dose exposing the reticle for producing the wafer CD exhibits a maximum gradient; for the critical reticle pattern pitch, establishing a relationship between wafer CD and a deviation from the reticle target CD that arises from use of different illumination doses; from the relationship between wafer CD and the deviation from the reticle target CD, identifying a reticle target CD deviation interval that gives rise to the wafer CD tolerance that is provided; and selecting the reticle target CD deviation interval as the acceptable reticle tolerance.