Patent ID: 6043147
Filing Date: 2000-03-28
Classification: C23C,H01L

Abstract:
A method of manufacturing a multilevel semiconductor device, which method comprises:forming a first dielectric interlayer on a substrate;forming a first patterned metal layer on the first dielectric interlayer, said patterned metal layer having gaps therein and comprising a first metal feature;depositing a layer of low dielectric constant material directly on said first patterned metal layer and said first dielectric interlayer, thereby filling the gaps;treating the exposed upper surface of the layer of low dielectric constant material with a silane (SiH.sub.4)-containing plasma to passivate and stabilize said layer of low dielectric constant material, whereby the low dielectric constant is maintained substantially at its as-deposited value during subsequent device processing; anddepositing an oxide layer over the plasma treated upper surface of the layer of low dielectric constant material.