Patent ID: 6366507
Filing Date: 2002-04-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:memory cell arrays each having a plurality of memory cells arranged in matrix, a plurality of word lines having select terminals of said memory cells of the same row connected thereto in common and a memory array having a plurality of bit lines having data input/output terminals of said memory cells of the same column connected thereto in common; a sense amplification circuit which amplifies a potential of said bit lines forming a pair inside said memory array; a variable delay circuit capable of adjusting a switching timing from a select state to a non-select state of said word line; a delay quantity setting circuit which sets a delay quantity in said variable delay circuit; a third variable delay circuit capable of adjusting an activation timing of said sense amplification circuit; and second delay quantity setting-circuits which sets the delay quantity in said variable delay circuit.