Patent ID: 6028988
Filing Date: 2000-02-22
Classification: G06F

Abstract:
A logic synthesis-for-testability system comprising:a memory unit for memorizing an FSM (finite state machine) description as an objective circuit description which is logically synthesized, said FSM description having a plurality of states; anda testability improving unit connected to said memory unit for improving testability of said FSM description by reducing an average distance between all pairs of said plurality of states;said testability improving unit comprising:a center state selecting means connected to said memory unit for selecting a center state from candidate states of said plurality of states;transition providing means connected to said memory unit and said center state selecting means for providing, in order to reduce said average distance between all pairs of said plurality of states, said FSM description with new transitions, each of which is directed to said center state from each of said plurality of states other than said center state; andcandidate selecting means connected to said memory unit and said center state selecting means for selecting said candidate states among said plurality of states with an asynchronous reset state of said plurality of states excluded from said candidate states.