Patent ID: 8351891
Filing Date: 2013-01-08
Classification: H03D,H04B

Abstract:
1. A distributed complementary metal-oxide-semiconductor (CMOS) mixer, comprising: a plurality of CMOS mixer stages, each configured to mix a radio frequency (RF) signal with a local oscillator (LO) signal and output a mixed intermediate frequency (IF) signal, wherein each mixer stage is a single-balanced or double-balanced current commuting mixer, and wherein the mixed IF signal is generated by multiplying the RF signal by the LO signal; and a plurality of monolithic transmission lines configured to provide the RF and LO signals to each stage and output the mixed IF signal from each stage, wherein each of the plurality of monolithic transmission lines is of equal length and wherein each transmission line comprises a plurality of connection nodes at different locations, each connection node coupling the respective transmission line to a different mixer stage, and wherein each monolithic transmission line of the plurality of monolithic transmission lines provides wideband matching; wherein the mixer stages and monolithic transmission lines are integrated on a common semiconductor substrate, and wherein each monolithic transmission line of the plurality of monolithic transmission lines is one of a coplanar waveguide and a multistage ladder LC network; wherein the plurality of monolithic transmission lines includes: a first and a second monolithic transmission line coupled with a differential RF input to each stage at a first and a second connection node, respectively; a third and a fourth monolithic transmission line coupled with a differential LO input to each stage at a third and a fourth connection node, respectively; and a fifth and a sixth monolithic transmission line coupled with a differential IF output of each stage at a fifth and a sixth connection node, respectively, for outputting the mixed IF signal from each stage, the fifth and sixth monolithic transmission lines also coupled with a differential IF output terminal; wherein each mixer stage comprises: a first field-effect transistor having a first gate, a first drain and a first source, wherein the first gate is coupled with the fourth connection node; a second field-effect transistor having a second gate, a second drain and a second source, wherein the second gate is coupled with the first gate; a third field-effect transistor having a third gate, a third drain and a third source, wherein the third source is coupled with the first source and the sixth connection node; a fourth field-effect transistor having a fourth gate, a fourth drain and a fourth source, wherein the fourth gate is coupled with the third connection node and the third gate, and the fourth source is coupled with the second source and the fifth connection node; a fifth field-effect transistor having a fifth gate, a fifth drain and a fifth source, wherein the fifth gate is coupled with the second connection node, and the fifth source is coupled with the first drain and the fourth drain; and a sixth field-effect transistor having a sixth gate, a sixth drain and a sixth source, wherein the sixth gate is coupled with the first connection node, the sixth source is coupled with the second drain and the third drain, and the sixth drain is coupled with the fifth drain and a reference node.