Patent ID: 6458638
Filing Date: 2002-10-01
Classification: H01L,Y10S

Abstract:
A method for fabricating a SOI semiconductor device comprising:providing a semiconductor substrate having first and second surfaces opposing each other; forming a device isolation layer in and on the first surface of the semiconductor substrate to define an active region and an inactive region, wherein said active region includes at least a pair of source/drain regions; forming a first gate electrode on the first surface of the substrate between the at least a pair of source/drain regions; forming a first insulating layer on the first gate electrode and the first surface of the substrate; forming a capacitor on the first insulating layer to be electrically connected to one of the at least a pair of source/drain regions; forming a second insulating layer on the capacitor and the first insulating layer; forming a third insulating layer on the second surface of the substrate; forming a body contact conductor line on and through the third insulating layer in alignment with the first gate electrode to be electrically connected to the active region of substrate aligned with the first gate electrode between the at least a pair of source/drain regions; forming a fourth insulating layer on the body contact conductor line and the third insulating layer; and forming a bit line on the fourth insulating layer to be electrically connected to one of the at least a pair of source/drain regions of the substrate.