Patent ID: 7495968
Filing Date: 2009-02-24
Classification: G11C

Abstract:
1. A page buffer for a nonvolatile semiconductor memory device comprising a plurality of memory cells each storing data provided by a bit line, comprising: a main latch block comprising a main latch node adapted to store main latch data logically controlled in accordance with a response transmission node, and connected to the bit line, whereby the main latch data may be provided to the bit line; a cache latch block comprising a cache latch node adapted to store cache latch data logically controlled in accordance with input data, and connected to the response transmission node, whereby the cache latch data is provided to the response transmission node in response to a dumping control signal; and an output driver unidirectionally driving an internal output line in accordance with the main latch data, wherein the output driver comprises an output driving transistor driving the internal output line and gated by the main latch data, and wherein the internal output line is connected to an output switch and is electrically isolated from a transmission path associated with the input data, wherein the cache latch block is further adapted to load and store next input data to be programmed in one memory cell during a time period in which the main latch data is being programmed into the memory cell.