Patent ID: 6127848
Filing Date: 2000-10-03
Classification: H03K

Abstract:
A circuit for translating an input signal having a value switching between a reference voltage and a first power supply voltage into an output signal having a value switching between said reference voltage and a second power supply voltage, said second power supply voltage being larger than said first power supply voltage, while keeping all voltages across the gate oxides of the devices in said circuit less than a specified breakdown voltage, said circuit comprising:(i) a first power terminal for receiving said first power supply voltage;(ii) a second power terminal for receiving said second power supply voltage;(iii) a ground terminal for receiving said reference voltage;(iv) an input terminal for receiving said input signal;(v) an output stage for generating said output signal, said output stage including:(a) an upper driver transistor and a lower driver transistor connected in series as a complementary pair, said upper driver transistor being coupled to said second power terminal and said lower driver transistor being coupled to said ground terminal;(b) an output terminal connected between said upper driver transistor and said lower driver transistor to provide said output signal;(c) an upper buffer circuit to keep the voltage across the gate oxide of said upper driver transistor below said specified breakdown voltage; and(d) a lower buffer circuit to keep the voltage across the gate oxide of said lower driver transistor below said specified breakdown voltage;(vi) an upper signal inverter for converting said input signal into an upper driving signal switching between a first offset voltage and said second power supply voltage to turn on and turn off, respectively, said upper driver transistor, said first offset voltage being equal to the sum of said reference voltage and a first defined offset voltage, said upper signal inverter comprising:(a) an upper input inverter for inverting said input signal into a first intermediate signal, and creating a second intermediate signal by reducing the range of said first intermediate signal; and(b) an upper output inverter for converting said first intermediate signal and said second intermediate signal into said upper driving signal;(vii) a lower signal inverter for inverting said input signal into a lower driving signal to drive said lower driver transistor; and(viii) a gating circuit connected between said upper input inverter and said upper output inverter to prevent said upper driving signal from appearing at said upper input inverter.