Patent ID: 6243286
Filing Date: 2001-06-05
Classification: H01L,Y10S

Abstract:
A semiconductor memory device having at least one memory cell that includes first and second load transistors and first and second driver transistors, the semiconductor memory device comprising:a semiconductor substrate having a main surface;a first load transistor active region which is formed on the main surface as an active region for the first load transistor;a second load transistor active region which is formed on the main surface as an active region for the second load transistor;a first driver transistor active region which is formed on the main surface as an active region for the first driver transistor;a second driver transistor active region which is formed on the main surface as an active region for the second driver transistor;a first element isolation region which is formed on the main surface to isolate the first load transistor active region from the first driver transistor active region;a first conductive layer which extends from an area on the first load transistor active region to an area on the first driver transistor active region to be a gate electrode for the first load transistor and for the first driver transistor;a second conductive layer which branches from the first conductive layer on the first element isolation region and is electrically connected to the second driver transistor active region, wherein the width of part of the second conductive layer positioned on the first element isolation region is less than the width of the first conductive layer; anda third conductive layer which is electrically connected to the first load transistor active region, passes across the second load transistor active region, and extends to an area on the second driver transistor active region to be a gate electrode for the second load transistor and the second driver transistor.