Patent ID: 8856463
Filing Date: 2014-10-07
Classification: G06F

Abstract:
1. A system for implementing a data transaction between a transaction requesting component and a memory module, comprising: at least one FIFO buffer coupled to the transaction requesting component for receiving a transaction request, the transaction request including a header with a length indication specifying a predetermined amount of data for a data payload indicated by the transaction request; a memory controller coupled to the at least one FIFO buffer and the memory module and operable to receive the transaction request from the at least one FIFO buffer, and to access the memory module to execute the data transaction indicated in the transaction request, the transaction request being arranged as pipelined data, the memory controller being further operable to execute as pipelined data transfer in a plurality of stages for reading, at a respective stage of the pipelined data transfer, an amount of the data payload corresponding to the predetermined amount of data specified by the length indication from one of the at least one FIFO buffer and the memory module; and a counting device in the memory controller operable to receive the length indication as a count value, and to update the count value as the memory controller executes the data transaction such that the counting device can provide a transaction complete indication when the updated count value indicates that the memory controller has read, at the respective stage of the pipelined data transfer, the amount of the data payload corresponding to the predetermined amount of data specified by the length indication.