Patent ID: 7920429
Filing Date: 2011-04-05
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: an access control unit for outputting a control signal for a predetermined time period in response to an active signal: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time period of a transition period between a deactivation of a word line and an activation of the word line, and then outputting a high voltage greater than the power source voltage as the driving source signal in response to a driving signal activated in response to an address signal during the succeeding time period of the transition period; and a word line control unit for activating the word line at a voltage level of the driving source signal in response to the driving signal, wherein the voltage supplying unit outputs the power source voltage as a driving source signal when the control signal is activated, and outputs the high voltage as the driving source signal when the driving signal is activated and the control signal is deactivated, wherein the access control unit includes: a delay unit for delaying the active signal for a predetermined time to output a delayed active signal: a timing detection unit for outputting a beginning control signal and an end control signal, each control signal respectively activated during a beginning and an end of an activation period of the word line based on the active signal and the delayed active signal; and a logic combination unit for outputting the control signal by combining the beginning control signal and the end control signal, wherein the timing detection unit includes: a first inverter for inverting the active signal to output an inverted active signal; a first logic gate for performing a NAND operation on the inverted active signal and the delayed active signal to output the end control signal; a second inverter for inverting the delayed active signal to output an inverted delayed active signal; and a second logic gate for performing a NAND operation on the active signal and the inverted delayed active signal to output the beginning control signal.