Patent ID: 6597218
Filing Date: 2003-07-22
Classification: H03L,Y10S

Abstract:
An integrated circuit, comprising:a clock path for carrying a clock signal; a power supply path adapted to receive power from a power supply; a delay locked loop connected to the power supply path, comprising: a voltage-controlled delay line for generating a delayed clock signal dependent on an input thereto; a phase detector for detecting a phase difference between the clock signal and the delayed clock signal; and a bias-generator arranged to output a voltage to the input of the voltage-controlled delay line responsive to the phase detector; and an adjustment circuit operatively connected to the input of the voltage-controlled delay line, wherein the adjustment circuit modifies the voltage output by the bias-generator, wherein the adjustment circuit comprises a first p-channel transistor and a first n-channel transistor, and wherein the first p-channel transistor and the first n-channel transistor are connected in series.