Patent ID: 6639271
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A dual bit dielectric memory cell comprising:a) a substrate comprising a source region, a drain region, and a channel region positioned there between; b) a multilevel charge trapping dielectric positioned on the surface of the substrate; and c) a control gate positioned on the surface of the multilevel charge trapping dielectric and positioned over the channel region; d) wherein the multilevel charge trapping dielectric includes: i) a tunnel layer adjacent to the substrate of a first dielectric material; ii) a top dielectric layer adjacent to the control gate of a second dielectric material; and iii) a charge trapping layer positioned between the tunnel layer and the top dielectric layer, the charge trapping layer including a source charge trapping region towards one end of the charge trapping layer, a drain charge trapping region towards an opposite end of the charge trapping layer, and an isolation barrier interposed between the source charge trapping region and the drain charge trapping region, wherein the isolation barrier is substantially less conductive relative to the source charge trapping region and the drain charge trapping region, and functions to reduce charge spread through the charge trapping layer between the source charge trapping region and the drain charge trapping region.