Patent ID: 6560150
Filing Date: 2003-05-06
Classification: G11C

Abstract:
A method of operating a memory device, comprising:during a test mode: applying a first input signal to an input of a latch; latching the first input signal in the latch, thereby generating a first latch output signal from the first input signal; applying a control signal to the latch to introduce a test input signal into the latch, thereby generating a second latch output signal from the test input signal, wherein the second latch output signal is independent of a logic level of the first input signal; accessing a primary element when the second latch output signal has a first logic level; and suppressing access to the primary element when the second latch output signal has a second logic level; and during a normal operation: comparing an applied memory cell location address with a known defective address; generating a redundancy match signal indicative of whether the applied location address matches the known defective address; applying the redundancy match signal to the input of the latch; latching the redundancy match signal in the latch, thereby generating a third latch output signal, wherein the third latch output signal has either the first logic level or the second logic level, the first logic level being indicative of a match between the applied location address and the known defective address; accessing a primary element associated with the applied location address when the third latch output signal has the second logic level; and suppressing access to the primary element associated with the applied location address when the third latch output signal has the first logic level.