Patent ID: 8484501
Filing Date: 2013-07-09
Classification: G06F,G11C,Y02D

Abstract:
1. A computer system, comprising: a processor; an input device, operably connected to the processor, allowing data to be entered into the computer system; an output device, operably to the processor, allowing data to be output from the computer system; and a system memory operably connected to the processor through a system bus, the system memory comprising a plurality of DRAM devices having a plurality of rows of DRAM memory cells, the DRAM memory cells receiving, storing, and outputting data, at least one of the DRAM devices comprising: an input/output system operably connecting the plurality of DRAM devices the computer system; a refresh system for refreshing contents of the DRAM memory cells; control logic, the covered logic being operably interconnected with the input/output system and responsive to command from the external system; a delay locked loop subsystem synchronizing data communications between the input/output system and the computer system; and a delay locked loop control comprising: a device inactive circuit configured to selectively provide a device inactive signal; a delay lock coupled to the device inactive circuit, the device inactive circuit being configured to lock the delay interval of the delay locked loop on receiving the device inactive signal; and a stabilization circuit coupled to the delay lock, the stabilization circuit being configured to provide a stabilization signal to the delay lock when the delay locked loop is locked, and wherein the delay lock is further configured to suppress locking the delay interval until the stabilization signal has been received by the delay lock.