Patent ID: 6157576
Filing Date: 2000-12-05
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a voltage supply which supplies an erase voltage to a plurality of nonvolatile memory cells to erase data therein;a sense circuit which senses data of said plurality of nonvolatile memory cells;a controller which is coupled to said sense circuit and which includes an address generating circuit generating an address signal in an erase mode;an address decoder which decodes an address signal from said address generating circuit and which selects a plurality of nonvolatile memory cells so as to sense data of said plurality of nonvolatile memory cells supplied with said erase voltage; andan output circuit which outputs a condition of said plurality of nonvolatile memory cells in said erase mode,wherein said controller verifies in accordance with data sensed by said sense circuit whether or not data of said memory cells supplied with said erase voltage are erased.