Patent ID: 6995046
Filing Date: 2006-02-07
Classification: B82Y,G11C,H01L,Y10S

Abstract:
1. A method of making a device having nanotube memory elements, comprising: providing a structure having a plurality of transistors, each with a drain and a source with a defined channel region therebetween, each transistor further including a gate over said channel; for a predefined set of transistors, forming a corresponding trench between gates of adjacent transistors; for each trench, providing a defined pattern of nanotube fabric over at least a horizontal portion of the structure and extending into the trench; providing an electrode in each trench; suspending each defined pattern of nanotube fabric so that at least a portion is vertically suspended in spaced relation to the vertical walls of the trench and positioned so that the vertically suspended defined pattern of nanotube fabric is electromechanically deflectable into electrical communication with one of the drain and source of a transistor; providing an electrical communication path electrically connecting each electrode so that all electrodes may electro-statically attract a corresponding defined pattern of nanotube fabric away from a transistor and toward the electrode.