Patent ID: 6175943
Filing Date: 2001-01-16
Classification: G11B,H03M

Abstract:
An apparatus for controlling addresses for storing symbol data for error correction in a memory, wherein the symbol data is obtained by demodulating a bit stream read from a disk, comprising:a sync detecting portion for receiving the bit stream and detecting a frame sync and an identification (ID) sync included in the bit stream;a frame sync number generating portion for receiving and correcting a series of frame syncs detected by the sync detecting portion and generating information indicating the positions of the frame syncs;an ID error correcting portion for receiving the symbol data, correcting an error in an ID sync using ID parity data included in the symbol data, and outputting the ID sync in which the error is corrected;an ID sync number detecting portion for receiving the ID sync from the ID error correcting portion and the ID sync from the sync detecting portion, sequentially comparing the ID received sync with a sync frame structure, checking whether the received ID sync is corrected, and generating information indicating the position of the ID sync;an address generating portion for receiving the frame syncs and the information indicating the positions of the frame syncs from the frame sync number generating portion, and the ID sync and the information indicating the position of the ID from the ID sync number generating portion, generating addresses of symbol data corresponding to a predetermined position of an error correcting code (ECC) block, and outputting the addresses to the memory; anda controller for controlling the sync detecting portion, the frame sync number generating portion, the ID sync correcting portion, the ID sync number detecting portion, and the address generating portion.