Patent ID: 7697346
Filing Date: 2010-04-13
Classification: G11C

Abstract:
1. A data input/output circuit of a semiconductor memory apparatus, comprising: a first timing control unit configured to control an active timing of a first control signal to output a plurality of first driving control signals; a first data input/output unit configured to transmit write data from a data input/output buffer to a global input/output line, or transmit read data from the global input/output line to the data input/output buffer, in response to the first driving control signals; a second timing control unit configured to control an active timing of a second control signal to output a plurality of second driving control signals; and a second data input/output unit configured to transmit the write data from the global input/output line to a local input/output line, or transmit the read data from the local input/output line to the global input/output line, in response to the second driving control signals.