Patent ID: 7230815
Filing Date: 2007-06-12
Classification: H01G,H05K

Abstract:
1. A multilayered chip capacitor, comprising: a capacitor body, which is formed by stacking a plurality of dielectric layers and provides opposite first and second surfaces formed in a stacking direction of the plurality of dielectric layers as top and bottom surfaces; at least one pair of first and second internal electrodes which is formed on the plurality of dielectric layers to be spaced apart from the top and bottom surfaces of the capacitor body, and is alternately arranged on the plurality of dielectric layers so that one electrode of one pair of internal electrodes faces the other electrode of the one pair of internal electrodes with one of the plurality of dielectric layers interposed therebetween; a first external electrode and a second external electrode formed on the top and bottom surfaces, respectively, of the capacitor body; at least one of the first and second external electrodes formed over almost the entire area of the respective surface of the capacitor body such that a set back from an edge around the capacitor body is formed; a plurality of first leads protruding from the first internal electrodes so that the first internal electrodes are connected to the first external electrode; a plurality of second leads protruding from the second internal electrodes so that the second internal electrodes are connected to the second external electrode; the first and second leads formed in identical numbers; one first lead formed at each end of each first internal electrode; at least one first lead formed on each first internal electrode between the first leads formed at each end of each first internal electrode; one second lead formed at each end of each second internal electrode; and at least one second lead formed on each second internal electrode between the second leads formed at each end of each second internal electrode.