Patent ID: 8381083
Filing Date: 2013-02-19
Classification: G06F,H03M

Abstract:
1. Apparatus for decoding data comprising: receiving circuitry configured to receive a block of data formed of K M-bit words of payload data and P bits of received check data; check calculating circuitry configured to calculate P bits of calculated check data in dependence upon said K M-bit words of payload data; syndrome generating circuitry responsive to said received check data and said calculated check data to generated a syndrome value; and repair circuitry responsive to said syndrome value to detect a bit error in said K M-bit words of payload data and to repair said bit error in said K M-bit words of payload data; wherein said P bits of check data and said syndrome value have an address field of A bits, a bit error indicating field of E bits and an auxiliary field of (P−(A+E)) bits; said bit error indicating field indicates if said bit error is present and a position of said bit error within an M-bit word; said address field encodes a set of error addresses which has a cardinality of K providing a one-to-one mapping between values of said address field and a location of said M-bit word having said bit error within said K M-bit words of said payload data; said auxiliary field is a bit vector such that together with said address field and said bit error indicating field it provides a checksum for a systematic code with a minimum Hamming distance of T, where T is given by one of T=3 to provide single error correction capability and T=4 to provide single error correction and double error detection capability; said repair circuitry has error location determining circuitry responsive to said address field to identify an M-bit word containing a bit error within said payload data and responsive to said bit error indicating field to identify the location of said bit error within said M-bit word and bit repair circuitry responsive to said error location determining circuitry to repair said bit error at said location; said repair circuitry is responsive to said syndrome value to detect a bit error in said P bits of check data and to repair said bit error in said P bits of check data; and said repair circuitry responsive to said address field, said bit error indicating field and said auxiliary field to determine whether said address field and said bit error indicating field are valid.