Patent ID: 6519174
Filing Date: 2003-02-11
Classification: G11C

Abstract:
A memory cell system for a dynamic random access memory (DRAM) array, comprising:a plurality of data storage elements arranged in rows and columns; a plurality of wordlines, corresponding to said columns; a plurality of lower bitlines, corresponding to said rows, each of said plurality of lower bitlines further being associated with a plurality of upper, complementary bitlines thereto; said plurality of upper bitlines being vertically aligned with said plurality of lower bitlines, thereby defining a plurality of vertically folded bitline pairs; and a plurality of sense amplifiers, arranged in said rows, each of said plurality of sense amplifiers having one of said plurality of vertically folded bitline pairs as inputs thereto; wherein, when one of said plurality of wordlines is activated, a subset of said vertically folded bitline pairs is activated.