Patent ID: 6404264
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A fuse latch circuit comprising:a plurality of address lines; an input terminal for receiving a control signal from a fuse; a multiplexer for multiplexing the plurality of address lines in response to the control signal, wherein the multiplexer has transistors each being associated with each of the address lines, and all the transistors of the multiplexer are a single transistor type; an output terminal for providing a multiplexed signal from the multiplexer to a decoder; and a voltage supply unit for boosting the control signal, wherein the voltage supply unit is connected to the fuse through a means for precharging the input terminal, wherein the voltage supply unit provides a high voltage to boost the control signal provided to the multiplexer, wherein the nigh voltage is equal to or higher than a sum of a source voltage provided to the decoder and a threshold voltage of the transistors, wherein the transistors share a drain or a source region.