Patent ID: 6604065
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A software simulation method that models logic circuitry comprising:developing a gate syntax statement, said gate syntax statement describes a FAST14 logic circuit comprised of one or more 1-of-N input logic signals and one or more 1-of-N output logic signals; developing one or more input signal models for each of said 1-of-N input logic signals, each said input signal model further comprises one byte or less of information that identifies the following signal characteristics: signal is defined or undefined, signal's unique decimal signal value that further comprises one of N possible values where N is greater than 2, and signal's drive state that further comprises one of a plurality of possible drive states; developing one or more simulation environment files; and compiling said gate syntax statement and said simulation environment files to produce an executable software-implemented simulation model of said logic circuit, said executable software-implemented simulation model comprises a plurality of instructions that access said one or more input signal models and mathematically or logically manipulate the signal characteristics of said 1-of-N input logic signals to generate one or more output signal models that correspond to the signal characteristics of said one or more 1-of-N output signals.