Patent ID: 7406406
Filing Date: 2008-07-29
Classification: G06F

Abstract:
1. In a data processing system in which a structure and operation of a target system, which includes accumulator and supplementary accumulator registers, is emulated on a host system and in which a word length of the target system is shorter than, but more than half, a word length of the host system, a process for providing, during an emulation process, visibility in the emulated accumulator and supplementary accumulator registers of a target system word stored in the host system memory, the process comprising the steps of: A) in response to a first target system instruction to be executed during the emulation of a target system program by the host system, which first instruction includes an opcode specifying a first now functionality for reading entire content of an identified full word from the host system memory, and for providing the entire content of the identified full word to the target system program by: B) in response to a second target system instruction to be executed during the emulation of a target system program by the host system, which second instruction includes an opcode specifying a second new functionality provided to the target system program for writing into an identified full word of the host system memory by: