Patent ID: 7265589
Filing Date: 2007-09-04
Classification: H03K

Abstract:
1. A dynamic logic circuit having a clock input coupled to a clock signal, a plurality of logic inputs and a logic output comprising: a dynamic node pre-charged in response to a pre-charge phase of the clock signal; a logic tree for evaluating the dynamic node in response to a Boolean combination of the plurality of logic inputs and an evaluate phase of the clock signal; and a multi-gate FET device coupling an intermediate node of the logic tree to the dynamic node in response to a logic state on a first logic input of the plurality of logic inputs or during the pre-charge phase of the clock; wherein the multi-gate FET device is a dual gate NFET having a front gate terminal coupled to the first logic input of the plurality of logic inputs and a back gate terminal coupled to a logic complement of the clock signal, a drain terminal coupled to the dynamic node, and a source terminal coupled to the intermediate node of the logic tree; and wherein the dual gate NFET is an asymmetrical device and the back gate turns ON the dual gate NFET with a first conductivity, the front gate turns ON the dual gate NFET with a second conductivity and the second conductivity is greater than the first conductivity.