Patent ID: 7196560
Filing Date: 2007-03-27
Classification: H03K

Abstract:
1. A clock frequency multiplier, comprising: a tracking circuit, receiving a clearing signal and a reference clock signal, outputting a quotient of a number of cycles of the reference clock signal in a cycle of the clearing signal divided by a first predetermined value; a pulsing circuit, receiving the clearing signal and the reference clock signal, receiving one of the quotient and a compensated quotient derived from evening out intervals between consecutive pulses of a pulsing signal, and outputting the pulsing signal, wherein the frequency of the pulsing signal is the frequency of the clearing signal multiplied by the first predetermined value; and a shaping circuit, receiving the clearing signal, the reference clock signal and the pulsing signal, dividing the frequency of the pulsing signal by a second predetermined value and shaping the pulsing signal into a clock signal with a predetermined duty cycle, and outputting the divided and shaped pulsing signal as an output clock signal.