Patent ID: 9024657
Filing Date: 2015-05-05
Classification: G06F,H01L,H03K

Abstract:
1. A structured application specific integrated circuit (Structured ASIC), comprising: a core comprising memory cells and logic cells; a first IO routing fabric comprising a plurality of IO blocks along sides of the core, operatively connected to the core, the first IO fabric comprising a first routing fabric; a second IO routing fabric comprising a high-speed routing fabric operatively connected to the core; wherein, the second IO fabric is faster in data transfer than the first IO fabric, and the Structured ASIC is configured through via-configurable interconnections in the Structured ASIC, wherein the core is substantially rectilinear; the core logic cells comprise a module array having a plurality of logic cells arrayed in a repeating pattern; the first routing fabric is configurable through vias in the Structured ASIC, and connects the core to logical pin IO repeater areas; the module array further comprising a plurality of flip-flops, a clock macro, full adders and buffer cells operatively connected; and, the memory cells and logic cells of the core alternate and repeat in layout in columns along the vertical north-south direction to the core.