Patent ID: 6974978
Filing Date: 2005-12-13
Classification: H01L

Abstract:
1. An integrated circuit comprising: a plurality of arrangements of first size transistors adjacently disposed along a first stripe of substrate area, each arrangement of first size transistors having one or more pairs of a first size p-type transistor and a first size n-type transistor; first one or more interconnects interconnecting exclusively first size transistors of one or more adjacent ones of the plurality of arrangements of first size transistors to form a clock buffer of a logic component, consisting exclusively of first size transistors; a plurality of arrangements of second size transistors adjacently disposed along a second stripe of substrate area adjacently disposed parallel to the first stripe of substrate area, each arrangement of second size transistors having one or more pairs of a second size p-type transistor and a second size n-type transistors; and second one or more interconnects interconnecting exclusively second size transistors of one or more adjacent ones of the plurality of arrangements of second size transistors to form a logic element of the logic component, consisting exclusively of second size transistors.