Patent ID: 7573307
Filing Date: 2009-08-11
Classification: H03L

Abstract:
1. A method for reduced area delay signal timing, the method comprising: providing a delay lock loop circuit, wherein the delay lock loop circuit includes a plurality of selectable delay elements; operating the delay lock loop circuit in a first mode, wherein a program number is established in relation to a reference frequency, and wherein the program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency; multiplying the program number by a multiplicand; and operating the delay lock loop circuit in a second mode, wherein an input signal is applied to the delay lock loop circuit, wherein a derivative of the input signal is provided as an output that is delayed by a second delay time corresponding to the multiplied program number, and wherein the second delay time is approximately the first delay time multiplied by the multiplicand.