Patent ID: 6728808
Filing Date: 2004-04-27
Classification: G06F

Abstract:
A system which dynamically optimizes transaction retries issued by a peripheral component interconnect (PCI) bus master device to a target device coupled to a PCI bus, said system comprising:a first target device communicatively coupled to a PCI bus and able to issue a first retry signal over said PCI bus; a PCI bus master device communicatively coupled to said PCI bus and able to issue a first transaction and a second transaction over said PCI bus; a first latency determination circuit coupled to said PCI bus master device and determines a first delay value equivalent to how much time expires between said PCI bus master device receiving said first retry signal from said first target device and said first target device fulfilling said first transaction; and a first retry timer circuit coupled to receive said first delay value from said latency determination circuit, said first retry timer circuit able to respond when said PCI bus master device receives a second retry signal over said PCI bus corresponding to said second transaction, said first retry timer circuit causes said PCI bus master device to wait said first delay value before reissuing said second transaction over said PCI bus, said first delay value is regulated by said first retry timer circuit, provided said first retry timer circuit stores said first delay value longer than a predefined amount of time, said first latency determination circuit determines a second delay value, wherein said first latency determination circuit changes said first delay value stored within said first retry timer circuit in order to optimizes transaction retries issued by said PCI bus master device.