Patent ID: 8606990
Filing Date: 2013-12-10
Classification: G06F

Abstract:
1. An electronic apparatus comprising: a first data bus having a first bus width M1; a second data bus having a second bus width M2; a first memory; a second memory; a memory control circuit that controls the first memory and the second memory, the first memory being connected to the memory control circuit through the first data bus, the second memory being connected to the memory control circuit through the first data bus and the second data bus, a sum of the first bus width and the second bus width being larger than the first bus width by a times, wherein a=(M1+M2)/M1, and when the memory control circuit receives an access request for the second memory, the memory control circuit generates a command for accessing the second memory b times on the basis of an address of the access request point and accesses the second memory, and when the memory control circuit receives an access request for the first memory, the memory control circuit generates a command for accessing the first memory a×b times on the basis of an address of the access request point and accesses the first memory.