Patent ID: 8874996
Filing Date: 2014-10-28
Classification: G06F,G11C,H03M

Abstract:
1. A memory device, comprising: a normal storage area comprising first and second subsets configured to store first and second normal data, respectively; an error code storage area configured to store first and second error codes corresponding to the first and second normal data; an error detector configured to receive the first and second normal data and the first and second error codes, and further configured to detect the presence or absence of one or more errors in the first and second normal data or the first and second error codes; and a refresh controller configured to set respective refresh cycle times of the first and second subsets to different values according to the presence or absence of one or more errors in the first and second normal data or error codes; wherein where the first normal data or first error code contains at least one error and the second normal data and second error code do not include any errors, the refresh controller controls the refresh cycle time of the first subset to be smaller than the refresh cycle time of the second subset.