Patent ID: 9209806
Filing Date: 2015-12-08
Classification: H03K

Abstract:
1. A delay line for receiving and delaying an input signal comprising a plurality of inverters in series, each inverter comprising: a first PMOS transistor having a gate, a source connected to a voltage supply, and a drain; a second PMOS transistor having a gate which receives a first bias voltage, a source connected to the drain of the first PMOS transistor, and a drain; a first NMOS transistor having a gate which receives a second bias voltage, a drain connected to the drain of the first PMOS transistor, and a source; and a second NMOS transistor having a gate, a drain connected to the drain of the second PMOS transistor and the source of the first NMOS transistor, and a source connected to a ground; wherein the first PMOS and first NMOS transistors in the first inverter in the series receive the input signal, the drain of the first PMOS transistor in one inverter is connected to the gate of the PMOS transistor in the next inverter, and the source of the first NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the next inverter.