Patent ID: 8413106
Filing Date: 2013-04-02
Classification: G06F

Abstract:
1. A computer implemented method comprising: a) accessing a transaction level model description of an integrated circuit; re-writing the transaction level model description into a synthesizable subset of the transaction level model description including a communication portion comprising timing information and a behavioral portion wherein the communication portion and the behavior portion of the transaction level model description are separate so that the communication portion can be synthesized independently; b) automatically converting function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description; c) automatically generating interface logic in the synthesizable subset of the register transfer level description, said interface logic, comprising an interface between a bus interface and the signal accesses, wherein the interface logic includes combinational logic of a signal generator and butler registers, wherein the buffer registers are modeled as clock methods and the combination logic is modeled as a method sensitive to its inputs, and wherein buffer registers are inferred and one or more buffer registers store protocol content to implement a cross-reference to another transfer belonging to a same transaction; and d) storing the register transfer level description including said signal accesses and said interface logic between said bus interface and said signal accesses in a computer readable medium.