Patent ID: 6591354
Filing Date: 2003-07-08
Classification: G11C

Abstract:
A method for accessing a synchronous random access memory system, comprising:in a read operation, receiving a memory address in an nth clock cycle and outputting in an (n+1)th clock cycle data stored in the synchronous random access memory corresponding to the memory address received in the nth clock cycle, the data having at least two bytes each of which may be stored separately in the memory system; and in a write operation, receiving in a kth clock cycle a memory address to which data is to be written, the data having at least two bytes, receiving in a kth clock cycle at least two control signals which control individually whether each of the bytes of the data are to be written, and receiving in a (k+1)th clock cycle data to be stored in the synchronous random access memory at the memory address received in the kth clock cycle, wherein the nth clock cycle can be a clock cycle immediately following the kth clock cycle with no clock cycles intervening between the nth clock cycle and the kth clock cycle.