Patent ID: 6160420
Filing Date: 2000-12-12
Classification: G01R,H03K

Abstract:
A logic function circuit interconnect architecture for a user-programmable integrated circuit disposed on a substrate, said integrated circuit comprising:a plurality of logic function circuits placed in an array on said substrate;said array arranged as a plurality of rows and columns of said logic function circuits, each of said logic function circuits having a discernable height and width, and including at least one input and at least one output;said interconnect architecture including a plurality of sets of interconnect busses, each of said rows of said logic function circuits associated with at least one of said sets of interconnect busses and each of said columns of said logic function circuits associated with at least one other of said sets of interconnect busses;said sets of interconnect busses comprising wiring channels, at least one of said outputs of said logic function circuits being user-connectable through a single user-programmable element to at least one of said wiring channels of at least two of said sets of interconnect busses;said sets of interconnect busses associated with said columns of said logic function circuits cross said sets of interconnect busses associated with said rows of said logic function circuits at intersections;a plurality of said wire channels of said sets of interconnect busses associated with said columns of said logic function circuits are user-interconnectable at said intersections to a plurality of said wiring channels of said sets of said interconnect busses associated with said rows of said logic function circuits;said wiring channels comprise user-interconnectable segments of minimum fixed lengths spanning rows and columns of said logic function circuits of said array; andsaid wire segments of said interconnect busses are electrically user-interconnectable to an adjacent one of said wire segments in said same wiring channel and wherein said wire segments are offset.