Patent ID: 7517749
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method of forming an array of floating-gate memory cells, comprising: forming a first dielectric layer on a silicon substrate; forming a first polysilicon layer on the first dielectric layer; forming a second dielectric layer on the first polysilicon layer; forming a second polysilicon layer on the second dielectric layer; forming a third dielectric layer overlying the second polysilicon layer; patterning the first dielectric layer, the first polysilicon layer, the second dielectric layer, the second polysilicon layer, and the third dielectric layer to define word line gate stacks; forming source and drain regions between adjacent word line gate stacks; forming dielectric spacer layer over the word line gate stacks; patterning the dielectric spacer layer to define a portion of the dielectric spacer layer for removing the portion of the dielectric spacer layer; removing the portion of the dielectric spacer layer to define trenches exposing source regions, wherein each trench exposes a plurality of source regions; depositing a third polysilicon layer over the dielectric spacer layer, where the third polysilicon layer fills the trenches; patterning the third polysilicon layer to define one or more regions of the third polysilicon layer; selectively implanting ions in the one or more defined regions of the third polysilicon layer; and wet etching the third polysilicon layer to remove the non-implanted regions of the third polysilicon layer to form one or more polysilicon source local interconnect lines in the one or more trenches; wherein patterning the dielectric spacer layer and the third polysilicon layer comprises patterning the dielectric spacer layer and the third polysilicon layer with the same pattern.