Patent ID: 7966439
Filing Date: 2011-06-21
Classification: G06F

Abstract:
1. A method for using a system controller disposed in a single chip having a first clock domain and a second clock domain, the method comprising: receiving a read request in the first clock domain of a host interface of said system controller having a first clock rate; passing said read request into the second clock domain of a memory controller of said system controller associated with accessing a memory via a memory bus, said second clock domain having a second clock rate; in said second clock domain, said read request triggering said memory controller to assert a read command to said memory via said memory bus to fulfill said read request and the read request further triggering said memory controller to also send a delay-adjusted alarm message in said second clock domain to said host interface such that the delay-adjusted alarm message includes an indication of a time in the future when data to fulfill said read request will be returned from said memory to said first clock domain in response to the read command asserted on said memory bus and the indication is adjusted based on a time delay between said read request and said data becoming present and stable in said host interface, in said first clock domain, said host interface receiving said alarm message at a time before the data is ready for transfer, converting said alarm message in said second clock domain into an alarm message in said first clock domain, and dynamically monitoring attributes of said read request to generate a programmable offset to said alarm message in said first clock,