Patent ID: 6638817
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A fabrication method for a DRAM cell array, comprising:defining active regions and isolation regions in a rectangular strip shape at a predetermined distance from each other on a semiconductor substrate; forming a plurality of gate electrodes interleaved by a gate insulating film on the active regions; forming source and drain regions on the substrate at both sides of the gate electrodes in order to form a plurality of transistors; forming a plurality of lower electrodes connected to one of the source and drain regions of the transistors on the substrate on which the transistors are formed; forming upper electrodes interleaved by a capacitor insulating film on the lower electrodes to form a plurality of capacitors; forming a plurality of bit lines connected to one of the source and drain regions of the transistors on the substrate on which the capacitors are formed; and forming a plurality of word lines including first word lines and second word lines arranged in parallel with one another and in a direction perpendicular to a direction in which the bit lines are arranged, wherein the first word lines are connected to the gate electrodes of neighboring transistors and the second word lines are connected to insulating gate electrodes arranged on the substrate between neighboring transistors.