Patent ID: 7725685
Filing Date: 2010-05-25
Classification: G06F

Abstract:
1. An apparatus for detecting a hang condition in a multi-threading processor, the apparatus comprising: said processor executing threads on a plurality of execution units, the plurality of execution units shared among the threads, the plurality of execution units including a fixed-point unit, a floating point unit, and a load/store unit; the processor including instruction scheduling logic that schedules and dispatches instructions to the plurality of execution units; hang recovery logic coupled to the instruction scheduling logic to provide a hang recovery mechanism; including, in said hang recovery logic, a separate hang detect unit for each one of said threads, said hang recovery logic included for one of said threads detecting said hang condition when execution of an instruction for said one of said threads fails to complete; the instruction scheduling logic sending to the hang recovery logic a completion signal every time said instruction has completed; a failure of the instruction scheduling logic to send the completion signal indicating the hang condition in at least one of the processor, the fixed-point unit, the floating point unit, and the load/store unit; each hang detect unit including an OR gate, an incrementer, a multiplexer, a first AND gate, a second AND gate, a fault isolation register, and a comparator; the OR gate receiving the completion signal every time said instruction has completed; the OR gate capable of receiving a disable hang detect signal; the OR gate sending to the incrementer the completion signal unless the OR gate has received the disable hang detect signal; means for incrementing a count in the incrementer each time a timer pulse signal is applied to the incrementer; means for resetting the count in the incrementer each time the incrementer receives the completion signal from the OR gate; the multiplexer having a first input for receiving a first hang limit and a second input for receiving a second limit; the first hang limit and the second hang limit operating independently from each other; the first hang limit being shorter than the second hang limit, the second hang limit set to a timeout value of the maximum latency through the data processing system; the multiplexer receiving a memory request pending signal, the multiplexer outputting the first hang limit as a selected limit if the memory request pending signal is a logic zero, and outputting the second hang limit as the selected limit if the memory request pending signal is a logic one; means for using the first hang limit to detect a hang that is based on only instructions that stay internal to the plurality of execution units; the incrementer outputting the count to the comparator; the comparator comparing the selected limit to the count; the comparator generating an initial hang indication responsive to the selected limit equaling the count; said first AND gate and said second AND gate receiving the initial hang indication; said first AND gate generating a core hang detect indication; said second AND gate generating a memory hang detect indication; means for enabling and disabling the first and second AND gates using the memory request pending signal, wherein the first AND gate is enabled when the memory request pending signal is a logic zero and the second AND gate is enabled when the memory request pending signal is a logic one; the fault isolation register receiving the core hang detect indication when the memory request pending signal is a logic zero and the memory hang detect indication when the memory request is a logic one; in a first hang detect unit included in said hang recovery logic for a first thread: the memory request pending signal outputting a logic zero when the first thread does not have a pending transaction with the memory and the first thread is not in the blocked condition, wherein the first hang limit becomes the selected limit; responsive to an instruction pending in the processor for the first thread, means for starting a first count in the incrementer by applying the timer pulse to the incrementer; responsive to the first count reaching the selected limit before the instruction completes, means for identifying said hang condition in the processor; and responsive to identifying the hang condition, means for performing a recovery operation.