Patent ID: 6403996
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A semiconductor memory device including a cell array region and a peripheral region, comprising:a gate pattern formed on a semiconductor substrate in the peripheral region, the gate pattern including a gate electrode; a first insulating layer formed over the semiconductor substrate and the gate pattern in the peripheral region; a first conductive pattern formed over the first insulating layer in the cell array region, the first conductive pattern including a first conductive line and a first capping layer which are sequentially stacked, the first conductive line contacting the substrate through the first insulating layer; a second conductive pattern formed over the first insulating layer in the peripheral region, the second conductive pattern including a second conductive line, a first capping layer and a second capping layer which are sequentially stacked, the second conductive line contacting the gate electrode of the gate pattern through the first insulating layer; and a second insulating layer formed over the first insulating layer, and the first and second conductive patterns; the first and second capping layers having etch selectivity with respect to the second insulating layer.