Patent ID: 7418580
Filing Date: 2008-08-26
Classification: G06F

Abstract:
1. A computer processor comprising: a bus which transfers object-level instructions having a first format from a memory to an instruction cache in said processor for execution in multiple execution units; translation logic which generates translated instructions having a second format having multiple fields having contents that differ from those of said first format of said object-level instructions and replaces said object-level instructions with said translated instructions in accordance with positional information provided by a program counter; and a first execution unit of the multiple execution units which executes said instructions having the first format; a second execution unit of the multiple execution units that executes instruction having both the first format and the second format; and a dispatch unit coupled to the instruction cache that receives said object-level instructions having said first format from said bus; and said dispatch unit receives said object-level instructions having said second format to said execution unit, wherein said translation logic combines functions of two successive object-level instructions having said first format into a single translated instruction having said second format which is executed in the second execution unit and decreases the number of instructions to be executed and increases processing throughput, wherein said translation logic is coupled to said bus and to an instruction cache, and said translation logic receives said object-level instructions having said first format from said bus and transfers said translated instructions having said second format to said instruction cache.