Patent ID: 6157561
Filing Date: 2000-12-05
Classification: G11C,H01L

Abstract:
An integrated memory, comprising:a memory cell array having a first wiring plane, a second wiring plane, a third wiring plane, a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each one of said plurality of memory cells having a selection transistor with a control terminal, each one of said plurality of memory cells connected to a respective one of said plurality of bit lines through its selection transistor, each one of said plurality of memory cells connected to a respective one of said plurality of word lines through said control terminal of its selection transistor;a word line decoder having a plurality of outputs, each one of said plurality of outputs connected to a respective one of said plurality of word lines;a first supply line for supplying a first potential;a region configured in said third wiring plane;a plurality of parallel conductor tracks configured in said first wiring plane, said plurality of parallel conductor tracks including a plurality of conductortracks of a first type and at least one conductor track of a second type; anda plurality of segments configured in said second wiring plane and parallel to said plurality of parallel conductor tracks, each one of said plurality of segments connected to said control terminal of a respective one of said plurality of memory cells;each one of said plurality of word lines formed by one of said plurality of conductor tracks of the first type and by a group of said plurality of segments, said one of said plurality of conductor tracks of the first type connected to said group of said plurality of segments, each one of said plurality of conductor tracks of the first type connected to a respective one of said plurality of outputs of said decoder;said conductor track of the second type connected to said first supply line and to said region configured in said third wiring plane.