Patent ID: 8271827
Filing Date: 2012-09-18
Classification: G06F

Abstract:
1. A system comprising: a central processing unit; a first memory channel coupling the central processing unit to a first semiconductor memory unit, wherein the first memory channel is clocked with a first clock frequency; and a second memory channel coupling the central processing unit to a second semiconductor memory unit, wherein the second memory channel is clocked with a second clock frequency smaller than the first clock frequency, the second memory channel being separate from the first memory channel, wherein a databus width of the first memory channel is identical to a databus width of the second memory channel, and wherein the first and second memory units are configured to be capable of storing independent data, and wherein the first memory channel is directly coupled to a memory controller being integrated into the central processing unit and wherein the second memory channel is indirectly coupled to the memory controller via a buffer chip external to the central processing unit.