Patent ID: 7577891
Filing Date: 2009-08-18
Classification: H03M

Abstract:
1. A decoder architecture comprising: an input buffer configured to receive a plurality of codewords to be processed, wherein the input buffer is configured to receive each of the plurality of codewords at a pre-determined fixed rate; a decoder configured to receive a first codeword from the input buffer and process the first codeword, the decoder processing the first codeword only for an amount of time required for the first codeword to become substantially error free, wherein an average decoding speed of the decoder is set such that an average read speed of the decoder from the input buffer is faster than the pre-determined fixed rate of receiving the plurality of codewords in the input buffer; and logic in communication with each of the decoder and the input buffer, the logic configured to determine when the first codeword processed by the decoder becomes substantially error free, wherein the logic generates a signal for loading a second codeword from the input buffer into the decoder responsive to the logic determining that the first codeword has become substantially error free.