Patent ID: 6312984
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A semiconductor processing method of forming a conductive interconnect, comprising:providing a semiconductive substratewithin the substrate, providing a node location to which electrical connection is to be made;providing insulating dielectric material over the node location and substrate;etching an opening into the insulating dielectric material over the node location;forming a sidewall spacer within the opening, the sidewall spacer not extending downwardly to contact the substrate;filling the opening to the node location with a layer of electrically conductive material;rendering the sidewall spacer electrically conductive;the layer of electrically conductive material and sidewall spacer together defining a conductive interconnect to the node location; andafter filling the opening with the electrically conductive material, etching the electrically conductive material to form an upper surface of the conductive material which is substantially coplanar with a laterally adjacent upper surface of the dielectric material.