Patent ID: 7827020
Filing Date: 2010-11-02
Classification: G06F

Abstract:
1. A method of simulating a logic circuit, comprising: running an initial microcode load in a first configuration in a high level simulator that parallels a post-initial microcode load state in a post-initial microcode co-simulator environment, wherein the initial microcode load initializes a simulated logic circuit and loads firmware to support code execution using the simulated logic circuit; creating a snapshot of the post-initial microcode load state in the high level simulator of micro-architected facilities, a Hardware System Area (HSA), and associated data areas in memory in response to completing the initial microcode load; superimposing the post-initial microcode load state onto a post-initial microcode load co-simulation hardware model, and loading registers into the model to update the model state to run on a co-simulator; loading the HSA data into a memory section of the post-initial microcode load co-simulator model; inserting a new program status word (PSW) for a test case; retrieving the new PSW in response to applying a clock to the post-initial microcode load co-simulator model; and beginning post-initial microcode load co-simulator model execution on the co-simulator at an instruction address that points to the test case.