Patent ID: 6230254
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A superscalar microprocessor system capable of executing one or more instructions out of order with respect to an ordering defined by a program stream, the system comprising:an instruction window having two or more storage locations for storing instructions, the instruction window capable of transferring an instruction from one storage location to another storage location;an instruction fetcher that fetches a plurality of instructions in program order from an instruction store and stores the plurality of instructions in the instruction window; andan instruction execution unit having at least one functional unit and a register file comprising real registers and temporary registers, the instruction execution unit receiving instructions after the instructions pass through the instruction window, the instruction execution unit decoding and issuing instructions from the instruction window, the execution unit further including:a load store unit adapted to make load requests and store requests, the load store unit adapted to make at least one load request out of program order so that a load request can be made before a store request that precedes the load request in program order, the load store unit making store requests in program order responsive to a retire signal for a store instruction from the instruction execution unit,the load store unit including at least a first storage station and a second storage station,the load store unit including load dependency check circuitry coupled to the first storage station and the second storage station, the load store unit not making a particular load request when the load dependency check circuitry detects an address collision for that particular load request, andthe load store unit including a load aligner, the load aligner receiving unaligned data and aligning the data prior to routing out of the load store unit, anda data routing path including at least one bus coupling the load store unit to tie register file, wherein said data routing path is adapted to transfer data in response to load and store instructions.