Patent ID: 6809964
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A memory device comprising:a memory array comprising at least a first storage area and a second storage area, said first storage area including at least a first block and said second storage area including at least a second block, each of said first and second blocks including a plurality of sectors; a buffer; a control circuit coupled to the memory array and the buffer for accepting external commands and for reading, writing, and erasing portions of said memory array; said wherein said control circuit is responsive to a data transfer command, said data transfer command including a source address of a first sector in said first block, a destination address of a second sector in said second block, and a parameter specifying an amount of data, to copy the amount or data specified from sectors in said first block starting with said first sector and to sectors in said second block starting with said second sector, without transferring any content on an external bus.