Patent ID: 7436690
Filing Date: 2008-10-14
Classification: G11C,H01L

Abstract:
1. In a flat cell read only memory including a plurality of memory banks, each of the memory banks comprising: a memory array; a plurality of first bit lines each capable of being connected to the memory array through a first switch; a plurality of second bit lines each capable of being connected to the memory array through a second switch; a plurality of first contacts each for connecting one of the plurality of first bit lines and one of the plurality of second bit lines to a bit signal line; a plurality of virtual ground lines extending outside said memory array, the plurality of virtual ground lines being arranged in pairs of adjacent virtual ground lines, each virtual ground line of said pair of adjacent virtual ground lines being connected to the memory array through a third switch and a fourth switch, each switch being driven separately; a plurality of second contacts, each second contact connecting a respective one of said pairs of adjacent virtual ground lines to a virtual ground signal line; a first select line coupled to each of the first and third switches for controlling switching thereof; and a second select line coupled to each of the second and fourth switches for controlling switching thereof.