Patent ID: 6715104
Filing Date: 2004-03-30
Classification: G06F

Abstract:
A system for accessing a memory device comprising a plurality of memorization subsystems (100-1 to 100-n) for storing a plurality of data words, each data word being divided into â€˜pâ€™ unitary elements, said memory device being adapted to store each of the â€˜pâ€™ unitary elements into a different memorization subsystem of the plurality of memorization subsystems, said system comprising:an identifier for identifying at least one available memorization subsystem among a plurality of memorization subsystems, said available memorization subsystem being unused for storing any unitary elements of the plurality of data words, the identifier further comprising a detector for detecting a hardware failure in anyone of the plurality of memorization subsystems; an insulator coupled to the plurality of memorization subsystems for individually insulating anyone of the plurality of memorization subsystems, the insulator insolate a failed memorization subsystem, the insulator comprising an electrical insulator coupled to each of said plurality of memorization subsystems; a restorer for restoring the content of said insulated memorization subsystem into said available memorization subsystem; a display screen coupled to said insulator to forewarn a user which of the plurality of memorization subsystems is insulated; an access device coupled to the identifier and to the insulator for accessing the at least one available memorization subsystem in lieu of said insulated anyone of the plurality of memorization subsystems; an encoder to encode each of the plurality of data words into â€˜p=q+mâ€™ unitary elements, wherein â€˜mâ€™ is error correction unitary elements; and a decoder responsive to each of said â€˜q+mâ€™ unitary elements for producing an error free â€˜qâ€™ unitary elements data word.