Patent ID: 8222684
Filing Date: 2012-07-17
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a plurality of first gate patterns extending across a first region of a semiconductor substrate, first sidewalls of adjacent ones of the first gate patterns delimiting therebetween a first space having a first width and second sidewalls of adjacent ones of the first gate pattern delimiting therebetween a second space having a second width greater than the first width; a second gate pattern extending across a second region of a semiconductor substrate; a spacer layer pattern occupying the first space, wherein the spacer layer pattern is of insulating material; source/drain regions constituting an upper portion of the second region on both sides of the second gate pattern; a first impurity region at a surface of the substrate under the first space; a stress buffer layer covering the gate patterns, wherein the stress buffer layer has a first section disposed on the first impurity region as interposed between the first impurity region and the spacer layer pattern, a second section extending along the second sidewalls of the first gate patterns, and a third section covering top surfaces of the first gate patterns; a conformal etching stop layer overlying the spacer layer pattern and the stress buffer layer; and an interlayer insulating layer disposed on the etching stop layer, and wherein the conformal etching stop layer has a first section following alongside the entire second section of the stress buffer layer while in direct contact therewith, and a second section following over the entire third section of the stress buffer layer while in direct contact therewith.