Patent ID: 6214676
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A manufacturing method of an embedded memory logic device, comprising the steps of:forming first, second, and third gate electrodes over first, second, and third regions, respectively, of a semiconductor substrate;forming first, second, and third source/drain regions doped with a first impurity, in a semiconductor substrate, on both sides of the first, second, and third gate electrodes;forming an insulating layer on the entire surface of the resultant structure having the first, second, and third source/drain regions;forming a photoresist layer pattern exposing a region excluding the first region, on said insulating layer;anisotropically etching said insulating layer, to form spacers on the sidewalls of the gate electrodes formed in a region excluding said first region;doping the first and second gate electrodes, said first region, and said second source/drain region, with a second impurity;doping the third gate electrode and the third source/drain region with a third impurity; andforming silicide layers on the first, second, and third gate electrodes, on the second and third source/drain regions, and on the first region.