Patent ID: 8815670
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A FinFET structure, comprising: a substrate comprising a silicon-containing layer on an insulating layer; an array of fins formed to comprise the silicon-containing layer; a gate covering a portion but not all of a length of each fin in the array of fins, the portion covering each of the fins in the array, the gate defining source/drain regions on either side of the gate; a spacer on each side of the gate, wherein the spacer and the gate cover a multi-layer hardmask layer formed on the fins in the array, the hardmask layer being positioned under the gate, the hardmask layer comprising first, second and third layers on the silicon-containing layer, the first layer formed on the silicon-containing layer, the second layer formed on the first layer, and the third layer formed on the second layer; and merged fins in the source/drain regions, wherein at least the second and third layers of the hardmask layer do not cover portions of the fins in the source/drain regions.