Patent ID: 7525080
Filing Date: 2009-04-28
Classification: H03F,H04N

Abstract:
1. A readout circuit for a pixel array, comprising: a sample and hold circuit comprising: a first capacitor for storing a first signal from the pixel array, a first side of the first capacitor switchably coupled to a column line from the pixel array; a second capacitor for storing a second signal from the pixel array, a first side of the second capacitor switchably coupled to the same column line from the pixel array from which said first capacitor stores said first signal; a third capacitor for storing a third signal from the pixel array, a first side of the third capacitor switchably coupled to a column line from the pixel array; and a fourth capacitor for storing a fourth signal from the pixel array, a first side of the fourth capacitor switchably coupled to the same column line from the pixel array from which said third capacitor stores said third signal, where a second side of the first capacitor is coupled to a second side of the third capacitor, where a second side of the second capacitor is coupled to a second side of the fourth capacitor, wherein said first, second, third and fourth capacitors store signals from the same column line.