Patent ID: 8009461
Filing Date: 2011-08-30
Classification: G11C

Abstract:
1. A semiconductor device comprising an SRAM including a pair of MCSFETs connected as access transistors, each of the access transistors is electrically connected to a wordline control circuit including a single wordline conductor connected to a gate of each said MCSFET of said pair for controlling said MCSFET access transistor, said wordline control circuit including a switch device for driving a respective gate of each said MCSFET via said single wordline conductor at a voltage between a first threshold voltage Vt 1 and a second threshold voltage Vt 2 for a read operation of said SRAM, and, said switch device for driving a respective gate of each said MCSFET via said single wordline conductor at a voltage greater than Vt 2 for a write operation.