Patent ID: 7911243
Filing Date: 2011-03-22
Classification: G11B,H03K

Abstract:
1. A driver circuit comprising: an output transistor that is biased to provide an output signal in response to an input signal; and at least one programmable variable resistor configured to provide a bias magnitude of the output transistor that sets a power of the driver circuit to be commensurate with a data-rate of the input signal, wherein the driver circuit is a first driver stage and further comprising a second driver stage, the second driver stage comprising: an additional output transistor that is biased to provide a second stage output signal in response to the output signal from the first driver stage; and at least one additional programmable variable resistor configured to set a bias magnitude that is commensurate with a data rate of the output signal from the first driver stage, wherein the second driver stage further comprises a bias transistor configured as a level-shifting diode-connected transistor associated with the bias magnitude of the additional output transistor, the additional output transistor being biased by the output signal of the first driver stage such that the second stage output signal has a level-shifted magnitude.