Patent ID: 6272451
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A method for designing a field programmable system level integrated circuit (FPSLIC), comprising the steps of:simulating, pre-layout, the field programmable system level integrated circuit using co-verification software;generating, from an implementation of logic for the field programmable system level integrated circuit with instruction-set software, a simulation post layout model of the implementation for co-verification of the field programmable system level integrated circuit;simulating, with an instruction-set simulator, program code;outputting register contents from the instruction-set software, for the co-verification of the field programmable system level integrated circuit;creating a bit stream for a field programmable gate array (FPGA) device part of the field programmable system level integrated circuit;creating a program code for a micro-controller part of the field programmable system level integrated circuit; andcreating, from the bit stream and the program code, in a program file, a combined-bit stream that has data for both the FPGA device and instruction code for a RISC micro-controller.