Patent ID: 6192459
Filing Date: 2001-02-20
Classification: G06F

Abstract:
A memory system comprising:a tag ram comprising a memory controller and a tag ram lookup mechanism;a first connection coupled to a control bus through which data retrieval requests are sent;a data storage device comprising ways and sets;a set address bus coupled to the tag ram and the data storage device;way address links coupled to the tag ram and the data storage device;the tag ram to (i) receive a data retrieval request through the first connection in a first clock cycle, (ii) transmit a set address portion of the data retrieval request to the data storage device through the set address bus in a second clock cycle, (iii) look up way address information in the tag ram lookup mechanism in the second clock cycle based on the data retrieval request, (iv) transmitting the way address to the data storage device in a third clock cycle, and (v) retrieve data associated with the data retrieval request.