Patent ID: 8815736
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A method, comprising: forming a plurality of N-doped source/drain regions for NMOS transistors and a plurality of P-doped source/drain regions for PMOS transistors in a semiconducting substrate; performing a first heating process at a first temperature to initially form a first metal silicide region in each of said P-doped source/drain regions; performing a second heating process at a second temperature to initially form a second metal silicide region in each of said N-doped source/drain regions, wherein said second temperature is at least 30° C. less than said first temperature; and performing a third heating process at a third temperature on both the N-doped source/drain regions and the P-doped source/drain regions to complete the formation of said first and second metal silicide regions, said third temperature being greater than said first temperature.