Patent ID: 6421292
Filing Date: 2002-07-16
Classification: G11C

Abstract:
A semiconductor memory comprising:a parity generating unit which generates a first parity in accordance with a plurality of bits of write data; a memory cell array having a plurality of blocks which are simultaneously subjected to a data write or read operation, each block being provided with a plurality of sub-arrays storing the write data and one or more arrays storing the first parity, each of the plurality of sub-arrays being provided with a plurality of memory cells; a refresh unit which performs a refresh operation to each of the sub-arrays; and a parity-data comparing unit which compares the first party with a second parity generated by assuming that read data from at least one of the plurality of sub-arrays which cannot be accessed because at least one of the plurality of other blocks is activated by the refresh operation when the refresh operation and the data read operation are performed at the same time is 0 or 1, to determine the write data stored in the at least one of the plurality of sub-arrays.