Patent ID: 7056792
Filing Date: 2006-06-06
Classification: H01L

Abstract:
1. A method of fabricating stacked gate flash memory cells, comprising: providing a substrate; forming a plurality of parallel long trenches along a first direction in the substrate; forming a conductive layer and a pair of source regions on the bottom of each of the long trenches, wherein the source regions are respectively disposed in the substrate adjacent to two sidewalls of each of the long trenches and electrically connected by the conductive layer therein; forming a source isolation layer on the conductive layer; forming a tunnel oxide on two sidewalls of each of the long trenches; forming a U-shaped floating gate on the source isolation layer, contacting the tunnel oxide; forming a pair of control gate spacers respectively disposed on the vertical portion of the U-shaped floating gate, substantially having the same width as the vertical portion; forming a U-shaped inter-gate dielectric layer on the U-shaped floating gate and the control gate spacers; forming a control gate on the U-shaped inter-gate dielectric layer; forming a plurality of parallel shallow trench isolation (STI) regions along a second direction, thereby defining a plurality of cell trenches; and forming a drain region in the substrate adjacent to each of the cell trenches.