Patent ID: 7145545
Filing Date: 2006-12-05
Classification: G11C

Abstract:
1. A shift register comprising X stages having outputs, where X is an integer greater than three, and Y clock inputs, where Y is an integer greater than two, each xth one of said stages, for each x such that 1<x≦X, comprising a flip-flop and logic circuit arranged to receive a set enable signal from said output of an (x−1)th one of said stages, each (nY+y)th one of said stages being arranged to be set in response to one of a leading edge and a first level of a clock signal at a yth one of said clock inputs in a presence of said set enable signal and to be reset in response to one of a trailing edge and a second level of said clock signal at said yth clock input for each y such that O<y≦Y and where n is a non-negative integer.