Patent ID: 7449728
Filing Date: 2008-11-11
Classification: H01L

Abstract:
1. An integrated circuit comprising: a depletion mode (D-mode) field effect transistor (FET) and an enhancement mode (E-mode) FET in a multi-layer structure, wherein the multi-layer structure includes a semiconductor substrate overlaid with a plurality of epitaxial semiconductor layers common to the D-mode and E-mode FETs, including a channel layer overlaid by a single barrier layer overlaid by a single etch stop layer overlaid by a first layer, wherein the D-mode and E-mode FETs each include a source contact, a drain contact, and a gate contact, and wherein the respective source and drain contacts of the D-mode FET and E-mode FET are coupled to the first layer, and the respective gate contacts of the D-mode FET and E-mode FET are in contact with the single barrier layer, and wherein the gate contact of the E-mode FET forms a Schottky contact with the single barrier layer.