Patent ID: 7281231
Filing Date: 2007-10-09
Classification: H01L

Abstract:
1. An integrated circuit (IC) layout design method utilized for connection of elements in a standard cell, wherein said IC comprises a substrate, said substrate further including pluralities of circuit elements; and m metal layers disposed on said substrate, which are utilized as a connection layout for circuit elements, wherein each metal layer further including an isolation layer for electrical isolation among said metal layers; said IC layout design method comprising the following steps: arranging a pluralities of circuit passageways at one terminal of a circuit element, said pluralities of circuit passageways extending from said substrate through at least two of said metal layers; connecting pluralities of lines which are required to be electrically connected to said terminal, to said terminal by connecting said lines to said circuit passageways; forming an upper metal layer overlying the pluralities of circuit passageways and located adjacent to a top metal layer of the m metal layers, said upper metal layer being connected to a predetermined number of top metal layer circuit passageways, the predetermined number of top metal layer circuit passageways being less than all of a plurality of top metal layer circuit passageways of the pluralities of circuit passageways located through the top metal layer of the m metal layers; and modifying said circuit element by connecting said upper metal layer to a different set of the plurality of top metal layer circuit passageways located in the top metal layer of the m metal layers, the different set of top metal layer circuit passageways being less than all of the plurality of top metal layer circuit passageways of the pluralities of circuit passageways located through the top metal layer of the m metal layers.