Patent ID: 8432061
Filing Date: 2013-04-30
Classification: H03L,H04L

Abstract:
1. A digital frequency divider comprises: a phase toggling unit, coupled to receive a first in-phase clock, a reset signal and a fraction-enable signal, the phase toggling unit generates a phase toggling clock that is modified from the first in-phase clock under control of the fraction-enable signal; counter, coupled to receive the phase toggling clock, the reset signal and a first multiple-bit signal, the counter counts a number of clock cycles defined by the first multiple-bit signal and generates a second multiple-bit signal; a counter reset detection block, coupled to receive the second multiple-bit signal, the counter reset detection block generates a reset signal upon the second multiple-bit signal reaching a predefined number; a half period detection block, coupled to receive the first and the second multiple-bit signals, the half period detection block generates a half period signal identifying an approximate mid-point within the number of clock cycles defined by the first multiple-bit signal; and a duty cycle equalizer, coupled to receive the reset signal and the half period signal, the first in-phase clock and a first quadrature-phase clock, the duty cycle equalizer generates an intermediate clock having the 50% duty cycle at a second frequency.