Patent ID: 7385434
Filing Date: 2008-06-10
Classification: H02M

Abstract:
1. A circuit for preventing a latch-up phenomenon caused by a parasitic PNP bipolar junction transistor and a parasitic NPN bipolar junction transistor formed by a CMOS transistor arranged in a DC-DC converter system, the DC-DC converter system including a first DC-DC converters and a second DC-DC converter coupled with each other in one chip for receiving an input voltage for generating of a first voltage and generation of a second voltage, respectively, the circuit comprising: a first pathway to control current supplied to the first DC-DC converter during a voltage transition during the generation of a first voltage wherein the first pathway control the magnitude of the supplied current such that more than a predetermined current is not supplied into an emitter of the parasitic PNP bipolar junction transistor formed by the CMOS transistor; and a second pathway to conduct current after the first voltage and the second voltage have reached target voltages wherein the conducted current is supplied into the emitter of the parasitic PNP bipolar junction transistor formed by the CMOS transistor.