Patent ID: 9183336
Filing Date: 2015-11-10
Classification: G06F,H03K

Abstract:
1. An integrated circuit, said integrated circuit comprising: a plurality of destination storage elements; a source of an asynchronous signal, said asynchronous signal provided to said destination storage elements with a first interconnect; a distribution network providing the output from a distribution buffer to said destination storage elements with a second interconnect; a pipeline having a first storage element and a second storage element, the pipeline inserted between said distribution buffer and the source of said asynchronous signal, the first storage element coupled with the first interconnect for receiving the asynchronous signal from the source of the asynchronous signal and providing the asynchronous signal to the second storage element, the second storage element providing the asynchronous signal to the distribution buffer with the second interconnect; a first clock distribution network providing a clock signal from a first clock source to the first storage element and the plurality of destination storage elements with a third interconnect; a second clock distribution network providing the clock signal from the first clock source to the second storage element with a fourth interconnect, wherein a delay of the second clock distribution network providing the clock signal to the second storage element is less than a delay of the first clock distribution network providing the clock signal to the first storage element.