Patent ID: 6560136
Filing Date: 2003-05-06
Classification: G11C

Abstract:
A single-port memory cell arrangement(a) having a multiplicity of single-port memory cells, (a1) which each have a memory transistor and a selection transistor which are connected in series via their load paths and are arranged between a data line and a supply line, (a2) the control terminal of each selection transistor being connected to a respective word line, (a3) a supply potential being applied to the respective memory transistor at the control terminal, (b) having at least one controllable switch arranged between the supply line and the load path of the memory transistor, (b1) the load path of the respective memory transistor being arranged between the load paths of the controllable switch and the respective selection transistor, (c) having a single charging device assigned to the multiplicity of single-port memory cells, (c1) which charging device has a precharge circuit for providing a precharging potential and (c2) which charging device, via the supply line and the respective controllable switch, recharges the corresponding memory transistor of the assigned single-port memory cells from time to time with the charging potential, (d) the memory transistors can be charged, via the data line to a first potential for a digital â€œ1â€  and to a second potential for a digital â€œ0â€ , (d1) the first potential, the second potential and the supply potential being chosen in such a way that the source and drain terminals of the respective memory transistor have the same potential.