Patent ID: 6284603
Filing Date: 2001-09-04
Classification: H01L,Y10S

Abstract:
A method to form Flash EEPROM memory cells in the manufacture of an integrated circuit device comprising:providing a semiconductor substrate;forming a tunneling oxide layer overlying said semiconductor substrate;depositing a first conductive layer overlying said tunneling oxide layer;depositing an interpoly oxide layer is deposited overlying the first conductive layer;depositing a second conductive layer overlying said interpoly oxide layer;patterning said second conductive layer, said interpoly dielectric layer, said first conductive layer, and said tunneling oxide layer to form control gates and floating gates for planned Flash EEPROM memory cells;implanting ions into said semiconductor substrate to form drain junctions wherein a mask protects the planned source junctions from said implanting and wherein said drain junctions are of the opposite impurity type as the impurity type of said semiconductor substrate;implanting ions into said semiconductor substrate to form source junctions wherein a mask protects said drain junctions from said implanting and wherein said source junctions are of the opposite impurity type as the impurity type of said semiconductor substrate; andimplanting ions into said semiconductor substrate to form channel stop junctions to complete said Flash EEPROM memory cells in the manufacture of an integrated circuit device wherein said implanting is performed at an non-perpendicular angle with respect to said semiconductor substrate, wherein said channel stop junctions contain said source junctions, wherein said channel stop junctions are of the same impurity type as the impurity type of said semiconductor substrate, and wherein a mask protects said drain junctions from said implanting.