Patent ID: 7145802
Filing Date: 2006-12-05
Classification: G11C,H01L

Abstract:
1. A method for programming a split gate memory cell, comprising the steps of: providing a split gate memory cell formed on a semiconductor substrate of a first conductive type and having two bitlines of a second conductive type, a first select gate, a floating gate, a wordline and a dielectric layer between the floating gate and the semiconductor substrate, wherein the first select gate and floating gate are transversely disposed between the two bitlines, the wordline is above the first select gate and floating gate, the semiconductor substrate comprises a first well of the first conductive type and a second well of the second conductive type, the two bitlines are formed within the first well, and the first well is surrounded by the second well; applying a positive voltage to the wordline so as to turn on the floating gate; and applying a negative voltage to the bitline next to the floating gate; whereby a bias voltage across the dielectric layer is generated for programming.