Patent ID: 6067270
Filing Date: 2000-05-23
Classification: G11C

Abstract:
An integrated circuit memory device, comprising:first and second banks of memory;a first bit line sense amplifier electrically coupled to said first bank of memory by a first pair of differential bit lines;a second bit line sense amplifier electrically coupled to said second bank of memory by a second pair of differential bit lines;a first pair of differential input/output lines;a second pair of differential input/output lines that are electrically disconnected from said first pair of differential input/output lines;means, responsive to a first bank select signal and a first column select signal, for electrically connecting the first pair of differential bit lines to said first pair of differential input/output lines; andmeans, responsive to a second bank select signal and the first column select signal, for electrically connecting the second pair of differential bit lines to said second pair of differential input/output lines.