Patent ID: 7468545
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. A method of forming a circuit component, comprising: providing a wafer substrate, a MOS device on said wafer substrate, a contact pad over said wafer substrate, and a passivation layer over said wafer substrate, wherein a first opening in said passivation layer is over said contact pad, and said contact pad has a contact region at a bottom of said first opening; forming a first metal layer over said passivation layer and over said contact region; after said forming said first metal layer, forming a first photoresist layer on said first metal layer, wherein a second opening in said first photoresist layer is over said first metal layer; after said forming said first photoresist layer, forming a second metal layer over said first metal layer under said second opening; after said forming said second metal layer, removing said first photoresist layer; after said forming said second metal layer, forming a second photoresist layer on said second metal layer, wherein a third opening in said second photoresist layer is over said second metal layer; after said forming said second photoresist layer, forming a metal post over said second metal layer under said third opening; after said forming said metal post, removing said second photoresist layer; after said removing said first and second photoresist layers, removing said first metal layer not under said second metal layer; after said removing said first metal layer not under said second metal layer, forming a first polymer layer over said passivation layer, on said second metal layer and on said metal post; after said forming said first polymer layer, polishing said first polymer layer and uncovering an end of said metal post from said first polymer layer; and after said polishing said first polymer layer and said uncovering said end from said first polymer layer, forming a wirebonded wire bonded over said end.