Patent ID: 6490660
Filing Date: 2002-12-03
Classification: G06F

Abstract:
Cache coherency apparatus for a system including one or more processor nodes, a system bus interconnecting said processor nodes and other system devices, with all processor nodes operating without a second level cache installed, the cache coherency apparatus at said one processor node comprising:a second level cache controller including a first level cache snooping path; said second level cache controller including status generation logic for responding with a first status signal to a bus snoop request message on said system bus directed to said second level cache; means operable in the absence of said second level cache for reflecting said bus snoop request to said first level cache snooping path; a first level cache controller operable in the absence of a second level cache responsive to said reflected bus snoop request for generating and feeding to said status generation logic a second status signal consistent with timing required for support of a second level cache directory access; and said second level cache controller further being responsive to said second status signal for replacing said first status signal.