Patent ID: 6959398
Filing Date: 2005-10-25
Classification: G06F,Y10S

Abstract:
1. A computer system, comprising: a first logic circuit; a second logic circuit; and an interface coupling the first logic circuit to the second logic circuit, wherein the interface includes: an input logic block that receives an incoming data stream and a first clock from the first logic circuit, the input logic block provides an intermediate signal, wherein if the incoming data stream includes a first asserted signal, the intermediate signal inverts its logic state, wherein the input logic block includes; an output logic block coupled to the input logic block, the output logic block receives the intermediate signal and a second clock, wherein the output logic block provides to the second logic circuit an output signal, the output signal is a second asserted signal for one clock period of the second clock, when the output logic block detects a logic state change in the intermediate signal.