Patent ID: 8683134
Filing Date: 2014-03-25
Classification: G06F,Y02D

Abstract:
1. A prefetch control system in a shared memory multiprocessor system having a plurality of processors and a shared memory with a plurality of independently addressable memory banks comprising: a plurality of pending prefetch address registers, one pending prefetch address register for each processor of said multiprocessor system storing an address of a pending prefetch of a corresponding processor; a plurality of comparators, one comparator for each processor of said multiprocessor system connected to said pending prefetch address register of the corresponding processor and receiving a read request address of a read request by the corresponding processor, each of said comparators generating a match signal if said pending prefetch address and said read request address of the corresponding processor are identical; and a plurality of request managers, one request manager for each independently addressable memory bank within the shared memory connected to each comparator and submitting memory access requests directed to a corresponding independently addressable memory bank having a first priority for read requests and a second lower priority for prefetch requests, said request manager upgrading said pending prefetch request of the corresponding processor from said second priority to said first priority upon receipt of said match signal.