Patent ID: 6535412
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A semiconductor memory device capable of switching the number of terminals inputting/outputting data with a mode switching signal, comprising:a plurality of memory mats each having a rectangular shape, each said memory mat including a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines provided in correspondence to said columns of said plurality of memory cells, and a plurality of pairs of global I/O lines transmitting/receiving data to/from said plurality of pairs of bit lines; a plurality of data buses, provided in correspondence to each said memory mat, at least partially arranged in parallel with a shorter side of each said memory mat; and a plurality of input/output circuit zones each provided along said shorter side of each said memory mat for transferring data between said plurality of pairs of global I/O lines and said data buses, each said input/output circuit zone including a selection portion selecting a data line corresponding to said plurality of pairs of global I/O lines from a plurality of data lines included in said data buses in response to said mode switching signal.