Patent ID: 6490708
Filing Date: 2002-12-03
Classification: G06F

Abstract:
A method of integrated circuit design comprising the steps of:(a) providing a library of integrated circuit design element cells, said library comprising separate groups of functionally-equivalent cells, each of said cells in each of said groups having parameters P among which are featured parameter F and second parameter S, said cells being ordered from one extreme value to the other extreme value of said featured parameter F; (b) testing an integrated circuit to determine whether its performance with respect to said featured parameter F is within acceptable tolerances; (c) selecting from the appropriate one of said groups in said library, for each failing cell whose performance falls outside of acceptable tolerances for said featured parameter F, a particular library cell having a value of said featured parameter F that is one increment away from the value of said featured parameter F held by said failing cell and replacing said failing cell with said library cell; (d) repeating steps (b) and (c) until all cells belonging to said integrated circuit perform within acceptable tolerances for said featured parameter F.