Patent ID: 7381612
Filing Date: 2008-06-03
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having recess channels and asymmetrical junctions, the method comprising: (a) providing a semiconductor substrate comprising laterally located regions for storage node junctions, and a bit line junction, and channel regions disposed laterally between the storage node junctions and the bit line junction; (b) first implanting p-type ions into the region of the bit line junction and the channel regions to form an impurity region having a depth, and two side parts by using a mask film pattern having a width of one to three times of a feature size; (c) forming recess channel trenches in the substrate by etching the channel regions to a designated depth, the depth of the recess channel trenches being greater than the depth of the impurity region, so that the recess channel trenches cut out both side parts of the impurity region to confine a width of the impurity region to a reduced width region between the trenches; (d) forming gate stacks filling the recess channel trenches; and (e) second implanting n-type ions into the confined impurity region and the regions of the storage node junctions by using the gate stacks as an implanting mask, to form asymmetric junctions such that the bit line junction is formed as a more shallow junction than the storage node junctions due to the confined impurity region.