Patent ID: 6388913
Filing Date: 2002-05-14
Classification: G11C

Abstract:
A method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory, wherein the ferroelectric memory comprises a memory array and a plurality of sense linear capacitors disposed outside the memory array, which at least comprises a memory cell constituted of a transistor and a ferroelectric capacitor, and a first terminal of the ferroelectric capacitor and a gate terminal of the transistor are connected with a word line, and a second terminal of the ferroelectric capacitor is connected with a source terminal of the transistor, and a drain terminal of the transistor is connected with a bit line, the method comprising the steps of:providing a first voltage to the word line and a second voltage to the bit line for activating the transistor; detecting and obtaining an output voltage by utilizing a voltage division equation on a connection node, wherein the connection node is on the bit line and between the transistor and a first sense linear capacitor of the plurality of sense linear capacitors, wherein the first sense linear capacitor is connected with the drain terminal of the transistor in serial electrically via the bit line; if the output voltage is high level, a logic state of the memory cell is decided to a first logic state; and if the output voltage is low level, the logic state of the memory cell is decided to a second logic state.