Patent ID: 7042040
Filing Date: 2006-05-09
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a silicon substrate of a first conductivity type having a grid trench extending in two mutually orthogonal directions in an upper major surface of the silicon substrate, the trench having a trench width; a plurality of silicon columns formed on the major surface of the substrate and having a square upper surface defined by the trench, the square upper surface having a side length; a plurality of transistors each formed on a side surface of the respective silicon columns, each of the transistors comprising: wherein the connection line is insulatively buried in the trench so as to extend from the second impurity layer on the bottom of the trench to an upper side of the trench and be connected to the bit line, and wherein the plurality of silicon columns form an array of a matrix form and one pair of the silicon columns at both corners on a diagonal line of the matrix form are lacking.