Patent ID: 6537880
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A method of fabricating a flash memory device on a semiconductorsubstrate, comprising the steps of: forming shallow trench isolation (STI) regions in first portions of said semiconductor substrate; forming a first dielectric layer on a second portion of said semiconductor substrate, wherein said second portion is not occupied by said STI regions; depositing a first conductive layer; forming an insulator shape on said first conductive layer, in an area in which said first conductive layer overlays said first dielectric layer, wherein the thickness of said insulator shape is greater than the thickness of said first conductive layer; depositing a second conductive layer, in situ doped during deposition; applying a first anisotropic dry etching procedure to said second conductive layer to form conductive spacers on the sides of said insulator shape; performing a second anisotropic dry etch procedure to remove regions of said first conductive layer not covered by said insulator shape, or by said conductive spacers, and to thin said conductive spacers, forming a floating gate structure comprised of a floating gate base structure, formed from said first conductive layer, and comprised of thinned conductive spacers, located extending upwards from the periphery of said floating gate base structure; removing said insulator shape, via wet etch procedures; forming a second dielectric layer on said floating gate structure; and forming a control gate structure on said second dielectric layer, overlapping said floating gate structure.