Patent ID: 7916574
Filing Date: 2011-03-29
Classification: G06F,G11C,Y02D

Abstract:
1. A circuit configured to be mounted on a memory module having a physical memory domain with a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks by a first number of chip-select signals for receiving and transmitting data having a bit width of the rank, the first number of ranks comprising a first number of DDR memory devices, the memory module configured to be operationally coupled to a computer system, the circuit configurable to: receive a set of signals comprising bank address signals, row/column address signals, and a second number of chip-select signals, wherein the received set of signals are capable of controlling a memory module having a system memory domain with a second number of ranks of DDR memory devices that are configured to be activated concurrently with one another and separately from the DDR memory devices of the other ranks for receiving and transmitting data having a bit width of the rank, the second number of ranks comprising a second number of DDR memory devices, the second number of ranks smaller than the first number of ranks, the second number of chip-select signals smaller than the first number of chip-select signals, and the second number of DDR memory devices smaller than the first number of DDR memory devices; generate phase-locked clock signals in response to clock signals of the computer system, wherein the circuit is configurable to transmit the generated phase-locked clock signals to the first number of ranks; selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the received set of signals; and translate between the system memory domain and the physical memory domain, wherein the translating comprises generating the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals and the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.