Patent ID: 6177324
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for fabricating a low voltage electro-static discharge protective device, comprising the steps of:providing a semiconductor substrate;forming a Shallow Trench Isolation in the surface of said substrate having a depth of penetration into the surface of said semiconductor substrate;forming a pad oxide layer over the surface of said substrate thereby including said STI trench;forming a gate structure on the surface of said pad oxide layer said gate structure to align with said STI trench;performing a p-well implant into the surface of said substrate;performing an electro-static discharge implant into the surface of said substrate whereby said electro-static discharge is self-aligned with said gate structure and wherein said electro-static discharge implant forms regions of electro-static discharge impurity ions that are adjacent to said Shallow Trench Isolation trench and enter into the surface of said substrate to a depth that is larger than the depth of said Shallow Trench Isolation trench; andperforming a source and a drain implant into the surface of said substrate whereby said source and drain implants are self-aligned with said gate structure.