Patent ID: 8977921
Filing Date: 2015-03-10
Classification: G01R,G06F

Abstract:
1. A system for providing a test result from an integrated circuit to a status analyzer, the system comprising: a deserializer configured to deserialize, into data frames, messages received from the integrated circuit, wherein the messages include the test result and are received from the integrated circuit in a serial data format; a frame sync module configured to (i) synchronize the data frames, (ii) selectively output the synchronized data frames, and (iii) generate a clock signal; and a gateway module configured to (i) receive the synchronized data frames from the frame sync module in accordance with the clock signal, (ii) convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and (iii) provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.