Patent ID: 8732645
Filing Date: 2014-05-20
Classification: G06F

Abstract:
1. A method to place and route a circuit, the method comprising: grouping cells by paths to determine a first set of cells of a first path and a second set of cells of a second path; analyzing timing by comparing a first slack along the first path and a second slack along the second path to identify a critical timing path; placing the first set of cells; routing first nets of the first path before the second set of cells are placed; placing the second set of cells along the second path, wherein the second set of cells are placed along the second path after the first set of cells are placed along the first path if the first slack is lower than the second slack, wherein the first path is identified as the critical timing path; determining a third set of cells of a third path; and determining whether or not the second path is more critical in timing than the third path, wherein the second set of cells are placed before the third set of cells if the second path is more critical in timing than the third path, wherein the grouping, analyzing, and placing is performed using a processor.