Patent ID: 6489650
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure; in the first element active region, a first and a second conductive regions formed at a surface region of the semiconductor substrate; a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a first insulating film, forming a floating gate for a transistor with said first and second conductive regions; and in the second element active region, a third conductive region formed at the surface region of the semiconductor substrate forming a control gate of a non-volatile memory; and a second electrode formed on the third conductive region via a dielectric film forming a second floating gate, wherein said first electrode and the second electrode are electrically connected and a third electrode is connected to the semiconductor substrate to apply a predetermined electric potential to the semiconductor substrate in said first element active region to control the threshold voltage of said transistor.