Patent ID: 6657459
Filing Date: 2003-12-02
Classification: H03K

Abstract:
A microprocessor, for use in an information processing system, being characterized such that communication between separate component units within said microprocessor comprises a link-up interface between a signal transmitting circuit contained in one of said component units and a signal receiving circuit contained in another of said component units of said microprocessor,wherein said signal transmitting circuit and said signal receiving circuit are driven by a same power source potential, wherein said signal transmitting circuit includes at least one field effect transistor having a gate, a source and a drain, said transmitting circuit generates an output signal at a source or drain of said field effect transistor in accordance with operation thereof, and said output signal has an amplitude range lower than said power source potential, and wherein said signal receiving circuit is driven by said power source potential indicative of voltage difference between a first power terminal, applied with a first potential, and a second power terminal, applied with a second, different potential, and comprises: (a) a first field effect transistor of a first conductivity type having a gate, a source and a drain, said gate thereof is coupled to receive said output signal of said transmitting circuit as an input signal to said receiving circuit, said drain thereof is connected to an output of said receiving circuit and said source thereof is applied with said second potential; (b) a second field effect transistor of a second conductivity type, opposite to said first conductivity type, having a gate, a source and a drain, said source thereof is applied with said first potential and said drain thereof is connected to said output of said receiving circuit; (c) a third field effect transistor of said second conductivity type having a gate, a source and a drain, said source thereof is applied with said first potential, said drain thereof is connected to said gate of said second field effect transistor and said gate thereof is controlled so that said second field effect transistor attains a non-conducting state when said first field effect transistor is switched to a conducting state; and (d) a fourth field effect transistor of said first conductivity type having a gate, a source and a drain, one of said source or said drain thereof is connected to said gate of said first field effect transistor, and the other of said source or said drain thereof is connected to said gate of said second field effect transistor.