Patent ID: 7799646
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device including one main field effect transistor (FET) and one or more sense FETs, comprising: a) forming a source and a gate of a main FET in a substrate; b) forming a source and a gate of one or more sense FETs in the substrate; c) forming an electrical isolation in the substrate between the main FET and the one or more sense FETs; and d) electrically connecting the gate terminals of the main FET and the one or more sense FETs, whereby the main FET, the one or more sense FETs and the electrical isolation are formed in a common substrate wherein a) through d) include i) forming a first polarity type epitaxial (Epi) layer on top of a heavily doped first polarity type substrate; ii) forming a trench mask on top of the Epi layer; iii) etching the epi layer through the trench mask to a predetermined depth to form one or more main FET gate trenches, one or more sense FET gate trenches and one or more isolation trenches, wherein the isolation trenches are located in between the main FET gate trenches and the sense FET gate trenches; iv) filing the trenches with a conductive material to form main FET gate and sense FET gates; v) implanting opposite polarity type dopants in the epi layer proximate the isolation trenches to form an isolation between the main FET and the one or more sense FETs; and vi) forming a conductive layer between the main FET gate and the sense FET gates.