Patent ID: 7982505
Filing Date: 2011-07-19
Classification: G11C,H03K

Abstract:
1. A logic circuit comprising: a first NAND gate that receives a first pulse signal and a first selection signal as inputs to output an inverted version of a logical product of the two input signals; a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal; a second NAND gate that receives a second pulse signal and the first selection signal as inputs to output an inverted version of a logical product of the two input signals; a second inverter gate that inverts an output signal of the second NAND gate to output a resulting signal; a first PMOS transistor that has a drain connected to an output of the first NAND gate, has a gate connected to an output of the second NAND gate and has a source connected to a power supply voltage; and a first NMOS transistor that has a drain connected to an output of the first inverter gate, has a gate connected to an output of the second inverter gate and has a source connected to a ground potential.