Patent ID: 6194265
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A method of fabricating a capacitor structure, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, comprised the steps of:providing an underlying transfer gate transistor, comprised of a gate structure, on a gate insulator layer, insulator spacers on the sides of said gate structure, and a source/drain region in an area of said semiconductor substrate, not covered by said gate structure;forming a storage node contact hole, in a first composite insulator layer, exposing the top surface of a source region;forming a doped polysilicon plug, in said storage node contact hole;depositing a second composite insulator layer, comprised of a thick overlying insulator layer, and of a thin underlying insulator layer;selectively forming a capacitor opening in said second composite insulator layer, exposing the top surface of said doped polysilicon plug, with the selective opening procedure used for said capacitor opening, terminating on, and exposing, a portion of the top surface of an overlying insulator layer component of said first composite insulator layer;depositing a silicon layer on the top surface of said second composite insulator layer, on the sides of said second composite insulator layer, exposed in said capacitor opening, and on the top surface of said doped polysilicon plug, exposed at the bottom of said capacitor opening;selectively removing said silicon layer from the top surface of said second composite insulator layer, via a selective chemical mechanical polishing procedure, resulting in a crown shaped structure, in said capacitor opening, comprised of vertical silicon features, on the sides of said capacitor opening, connected to a horizontal silicon feature, located at the bottom of said capacitor opening, with said horizontal silicon feature overlying, and contacting, said doped polysilicon plug;selectively removing said thick overlying insulator layer, exposing a top portion of said crown shaped structure, with a bottom portion of said crown shaped structure still surrounded by said thin underlying insulator layer;selectively depositinghemispherical grain, (HSG), silicon seeds, on the surface of said top portion of said crown shaped structure;performing an anneal cycle to selectively create an HSG silicon layer, on said top portion of said crown shaped structure, via consumption of said HSG silicon seeds, and via consumption of a portion of said crown shaped structure;selectively removing said thin, underlying insulator layer, from the top surface of said first composite insulator layer, exposing smooth surface of said bottom portion of said crown shaped structure, and the top surface of said first composite insulator layer, resulting in a crown shaped storage node structure, comprised of said top portion of said crown shaped structure, with an HSG silicon layer surface, and comprised of said bottom portion, of said crown shaped structure, comprised with a smooth surface;forming a capacitor dielectric layer on said crown shaped storage node structure; andforming an upper plate electrode, for said capacitor structure.