Patent ID: 7792154
Filing Date: 2010-09-07
Classification: G06F,H04J,H04L

Abstract:
1. An apparatus for performing a synchronous operation across a synchronous/asynchronous clock domain boundary, comprising: test hold generation logic unit; and a switching unit, coupled to the test hold generation logic, associated with one or more first devices in an asynchronous clock domain, wherein the test hold generation logic controls the switching unit to: switch the one or more first devices from an asynchronous clock mode of operation to a synchronous clock mode of operation, and return the one or more first devices to the asynchronous clock mode of operation, and wherein a synchronous operation is performed using one or more second devices in a synchronous clock domain and the one or more first devices in the asynchronous clock domain while the one or more first devices are in the synchronous clock mode of operation, wherein the test hold generation logic controls the switching unit to switch the one or more first devices in an asynchronous clock domain from an asynchronous clock mode of operation to a synchronous clock mode of operation by controlling a test mode input signal, a system clock enable signal, and an asynchronous clock hold signal so as to switch an input clock signal to the one or more first devices from a local asynchronous clock signal to a synchronous system clock signal by: