Patent ID: 7606094
Filing Date: 2009-10-20
Classification: G11C

Abstract:
1. A semiconductor memory device having a plurality of memory cells arranged at intersections of a plurality of bit lines and a plurality word lines, comprising: a sense amplifier for amplifying a minute potential difference appearing on a bit line pair corresponding to an accumulated charge in said memory cell; a power supply line pair including a first power supply line for supplying a first potential to said sense amplifier and a second power supply line for supplying a second potential to said sense amplifier; a pre-charge power supply line for supplying a predetermined pre-charge potential; a power supply line equalize circuit for setting said first potential and said second potential of said power supply line pair at the same potential based on said pre-charge potential; a current limit circuit inserted in series in a predetermined current path from said pre-charge power supply line to said power supply line pair; and switch means capable of switching whether or not current flowing from said pre-charge power supply line to said power supply line pair is limited by said current limit circuit, based on a control signal.