Patent ID: 6108805
Filing Date: 2000-08-22
Classification: G01R

Abstract:
A scan flip-flop including:a system clock input;a domino clock input;a flip-flop data input for receiving a flip-flop input data signal;a flip-flop data output for providing a flip-flop output data signal;a first test enable input for receiving a first test enable input signal, the first test enable signal being of a first polarity;a second test enable input for receiving a second test enable input signal, the second test enable signal being of a second polarity, opposite the first polarity;a test data input for receiving a test data input signal;a latch having a data input, a clock input coupled to the system clock input, and a data output coupled to the flip-flop data output; anda domino logic multiplexer having a domino clock input coupled to the domino clock input of the scan flip-flop, a data input coupled to the data input of the scan flip-flop for receiving an input data signal, a first test enable input coupled to the first test enable input of the scan flip-flop, a second test enable input coupled to the second test enable input of the scan flip-flop, a test data input coupled to the test data input of the domino scan flip-flop for receiving a test input data signal, and a data output coupled to the data input of the latch for providing the flip-flop input data signal to the latch if the first test enable signal is asserted and the test input data signal if the second test enable signal is asserted.