Patent ID: 6130136
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A method for fabricating a spacer in a transistor, comprising the steps of:forming a stepped feature at a semiconducting surface of a body, said stepped feature having a lateral face substantially parallel to said surface and an angled edge substantially perpendicular to said surface;forming a screen dielectric layer in a contact opening location of the surface, adjacent the angled edge of the stepped feature;forming an insulating layer over said lateral face and angled edge of said stepped feature, and over the screen dielectric layer in the contact opening location;forming a sacrificial layer over said insulating layer;removing the portion of said sacrificial layer over said lateral face to expose portions of said insulating layer and to leave a remaining portion of said sacrificial layer along said angled edge of said stepped feature;removing said exposed portions of said insulating layer; andsimultaneously etching the screen dielectric layer and remaining portion of said sacrificial layer;wherein the sacrificial layer is comprised of a material that etches, in the etching step, at a rate that is substantially higher than twice the rate at which the material of the screen dielectric layer etches in the etching step, so that the etching step removes both the screen dielectric layer from the contact opening location and also the remaining portions of the sacrificial layer from along said angled edge of said stepped feature.