Patent ID: 6697277
Filing Date: 2004-02-24
Classification: G11C

Abstract:
A match line circuit for use in a content addressable memory (CAM) device, comprising:a first pull-up device, said pull-up device having selectively adjustable values of pull-up impedances associated therewith; a first pull-down device; a match line coupled to said first pull-up device and said first pull-down device, said match line further coupled to a plurality of CAM cells, thereby defining a match node there at; a second pull-up device coupled to a second pull-down device, defining a float node there at; and enabling means for activating the match line circuit during a memory comparison operation; wherein said enabling means causes said match node to be precharged to a logic low voltage level and said float node to be precharged to a logic high level in between memory comparison operations.