Patent ID: 6100177
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising the steps of:forming a first level insulator film on a silicon substrate;forming a first level wiring conductor on said first level insulator;forming a second level insulator film to cover said first level wiring conductor and said first level insulator film;forming a through-hole type opening and first and second groove type openings in said second level insulator film;forming a metal layer to cover the whole surface of said second level insulator and to fill up said through-hole type opening and said first and second groove type openings; andpartially removing said metal layer until a surface of said second level insulator film and a surface of said metal layer become substantially the same surface,wherein said first groove type opening is formed in said second level insulator film by a first photolithography and etching process at first and second locations, the first location partially overlapping with a region of said first level wiring conductor and being different from the second location, and thereafter, said through-hole type opening and said second groove type opening, having a depth different from that of said first groove type opening, are formed in said second level insulator film by a second photolithography and etching process at third and fourth locations, respectively, the third location partially overlapping with said first location, and the fourth location being different from said first and second locations, so that said metal layer filled in said through-hole type opening is electrically connected with said first level wiring conductor, and said metal layer filled in said first groove type opening formed at said second location has a first thickness, and said metal layer filled in said second groove type opening formed at said fourth location has a second thickness different from said first thickness.