Patent ID: 6713826
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A semiconductor device comprising:a gate insulating film formed on a semiconductor substrate; a gate electrode, which is formed on the gate insulating film and includes lower and upper electrodes that are stacked in this order, the lower electrode being made of silicon, at least an uppermost part of the upper electrode being made of a material containing a metal; an insulator cap formed on the gate electrode, at least an uppermost part of the insulator cap being made of silicon nitride; a first nitride sidewall formed to cover at least respective side faces of the upper electrode of the gate electrode and the insulator cap; a pad oxide film formed on part of the side faces of the gate electrode and part of the upper surface of the semiconductor substrate, the part of the side faces of the gate electrode being not covered with the first nitride sidewall; a second nitride sidewall formed on the first nitride sidewall and the pad oxide film; doped regions, which are defined within the semiconductor substrate and located beside the gate electrode; an interlevel dielectric film formed on the semiconductor substrate; and a contact, which passes through the interlevel dielectric film to reach one of the doped regions and is self-aligned with the gate electrode.