Patent ID: 7502436
Filing Date: 2009-03-10
Classification: H03K

Abstract:
1. An apparatus for generating push-pull pulse width modulation (PWM) signals, comprising: a counter having a clock input, wherein the counter increments a count value for each clock pulse received at the clock input; a duty cycle register having a duty cycle value; a duty cycle comparator coupled to the duty cycle register and the counter, wherein the duty cycle comparator outputs a PWM signal according to a comparison between the count value and the duty cycle value; a period register having a period value; a period comparator coupled to the period register and the counter, wherein the period comparator compares the count value to the period value and when the count value is equal to the period value the period comparator causes the counter to reset the count value to zero; PWM signal steering logic comprising: a toggle flip-flop having a toggle input coupled to the period comparator, and first and second outputs, wherein the second output is the logical inverse of the first output and the first and second outputs reverse logic levels each time the count value is reset to zero, a first AND gate comprising a first input coupled to the PWM signal from the duty cycle comparator, a second input coupled to the first output of the toggle flip-flop, and an output comprising a high PWM signal; and a second AND gate comprising a first input coupled to the PWM signal from the duty cycle comparator, a second input coupled to the second output of the toggle flip-flop, and an output comprising a low PWM signal; wherein the high PWM signal and the low PWM signal comprise push-pull PWM signals.