Patent ID: 9225333
Filing Date: 2015-12-29
Classification: H03K

Abstract:
1. A logic level shift circuit with a single voltage supply rail for level shifting an input logic signal IN with logic — 0 and logic — 1 states (IN=0 and IN=1) to a corresponding level shifted output logic signal that is one of OUT or OUT_X (corresponding to an inverted OUT), comprising: an IN inverter circuit configured to receive IN at an IN Node, and provide OUT as an inverted IN at an OUT Node, the IN inverter coupled between an INT Node and a ground/reference; an INT_Node PFET transistor source coupled to the supply rail and drain coupled to the INT Node, and controlled by an OUT_X control signal corresponding to OUT_X to provide INT Node pull-up in response to an OUT_X=0 control signal; an OUT_X network configured to provide OUT_X as an inverted OUT at an OUT_X Node, including providing the OUT_X control signal to the INT_Node PFET, the OUT_X network including: