Patent ID: 7940243
Filing Date: 2011-05-10
Classification: G09G

Abstract:
1. An integrated circuit device, comprising: a first decoder that is configured to select a first gray scale input voltage responsive to at least one bit of a multi-bit data signal; a second decoder that is configured to select a second gray scale input voltage responsive to the at least one bit of the multi-bit data signal; and an amplifier circuit with a single pull-up transistor, a single pull-down transistor, a first sub amplifier, and a second sub amplifier, the first and second sub amplifiers being selectively operable responsive to at least one other bit of the multi-bit data signal; wherein the first sub amplifier has a first input terminal connected to the first gray scale input voltage, a second input terminal connected to a common node of the pull-up and pull-down transistors, and an output terminal directly connected to a gate of the pull-up transistor; the second sub amplifier has a first input terminal connected to the second gray scale input voltage, a second input terminal connected to the common node of the pull-up and pull-down transistors, and an output terminal directly connected to a gate of the pull-down transistor; and wherein the first and second decoders are not responsive to the at least one other bit of the multi-bit data signal.