Patent ID: 6706614
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method of fabricating a silicon-on-insulator (SOI) transistor, comprising the steps of:providing an active layer disposed on a buried oxide (BOX) layer, the BOX layer being disposed on a substrate, the active layer having an active region defined by isolation regions; forming a transistor in the active region, the transistor having a source and a drain having a body disposed therebetween, forming the transistor including: implanting each of the source and the drain to have an extension region and a deep doped region, the extension regions each having a junction depth and are disposed laterally inward towards the body with respect to the deep doped regions; and forming a gate disposed over the body, the gate including a gate electrode that defines a channel extending from the extension of the source to the extension of the drain; and implanting the source with germanium to form an area of silicon-germanium adjacent a source/body junction and extending from the source extension junction depth to the BOX layer, the area of silicon-germanium in the source forming a hetero junction along the junction of the deep doped region of the source and the body.