Patent ID: 7229856
Filing Date: 2007-06-12
Classification: H01L,Y10T

Abstract:
1. A method of manufacturing an electronic part packaging structure, comprising the steps of: mounting an electronic part, which has a connection terminal and a passivating film to cover the connection terminal, on a core substrate having a first wiring pattern to direct the connection terminal upward; forming an insulating layer to cover the electronic part and the core substate; forming a first via hole in a portion of the passivating film and the insulating layer on the connection terminal to expose the connection terminal such that a via hole is formed simultaneously in a portion of the insulating layer first on the wiring pattern on the core substrate; and forming a second wiring pattern, which is connected electrically to the connection terminal via the first via hole, on the insulating layer, wherein the second wiring pattern connected to the first wiring pattern on the core substrate via the second via hole are formed simultaneously.