Patent ID: 6260137
Filing Date: 2001-07-10
Classification: G06F,G06T

Abstract:
Data processing unit comprising:a register file with a plurality of word-wide registers, whereby a word having a predefined number of bits,a register load and store buffer connected to said register file,a memory,a bus having at least first and second word lines to form a double word wide bus coupling said register load and store buffer with said memory, whereby said register file has at least two sets of registers,coupling means, so that said first set of registers can be coupled with one of said word lines and said second set of registers can be coupled with the respective other word lines,a load and store control unit for transferring data from or to said memory, wherein said load and store control unit is configured to, in response to a single instruction for the data processing unit, load one word from said memory and to split it into two half-words which are stored in one half of a first register from said first set of registers and in a corresponding half of a second register from said second set of registers. respectively.