Patent ID: 7092294
Filing Date: 2006-08-15
Classification: G11C,H01L

Abstract:
1. A semiconductor memory comprising: a memory cell array having a plurality of memory cell transistor units, each of the units being configured from a plurality of memory cell transistors vertically connected in series, which have a first and a second control gate disposed on both sides of a floating gate, and which are horizontally arranged with a first end connected to a bit line via a first select gate transistor, and a second end connected to a source line via a second select gate transistor, wherein the first and the second control gates of the memory cell transistors arranged in the same row are connected in common to a first and a second control gate line, respectively; a boosting circuit configured to generate a write-in voltage, different multilevel intermediate voltages, and a bit line voltage from a power source; and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate lines and configured to select a first and a second select gate line connected to the respective gates of the first and the second select gate transistors; wherein, the row decoder applies a low level read-out voltage to first control gate lines adjacent to a read-out memory cell transistor.