Patent ID: 7434000
Filing Date: 2008-10-07
Classification: G06F

Abstract:
1. A processor comprising: a cache; a cache miss unit coupled to the cache, wherein the cache miss unit is configured to initiate a cache fill of a cache line for the cache responsive to a first cache miss in the cache, wherein the first cache miss corresponds to a first thread of a plurality of threads in execution by the processor, and wherein the cache miss unit is further configured to record an additional cache miss corresponding to a second thread of the plurality of threads, wherein the additional cache miss occurs in the cache prior to the cache fill completing for the cache line, and wherein the cache miss unit is configured to inhibit initiating an additional cache fill responsive to the additional cache miss; and a fetch unit coupled to the cache and the cache miss unit, wherein the fetch unit is configured to inhibit scheduling the first thread responsive to the first cache miss, and wherein the fetch unit, in response to a redirect of the first thread to a redirect address that is different from a fetch address that caused the first cache miss and further in response to the cache fill corresponding to the first cache miss having been initiated, is configured to re-enable scheduling of the first thread to fetch the redirect address from the cache, and wherein the fetch unit is configured to inhibit scheduling of the first thread responsive to a subsequent second cache miss for a fetch of the first thread and the second cache miss requires a second cache fill of a second cache line different from the cache line corresponding to the first cache miss, wherein the fetch unit is configured to inhibit scheduling the first thread responsive to the second cache miss until the cache fill corresponding to the first cache miss completes for the cache line, including writing the cache line to the cache, and wherein the fetch unit is configured to inhibit scheduling the first thread even though instructions from the cache line corresponding to the first cache miss are no longer needed by the first thread, and wherein the redirect occurs in response to the processor executing a previous instruction from the first thread and causes fetching to beginning at the redirect address instead of addresses generated by the fetch unit.