Patent ID: 6721914
Filing Date: 2004-04-13
Classification: G01R

Abstract:
A method for diagnosing defects in an integrated circuit comprising:providing a set of failing test patterns, each failing test pattern comprising a set of values, one or more of said values being incorrect compared to a corresponding value of a set values from a corresponding expected set of passing test patterns; for each failing test pattern in said set of test patterns determining if any single stuck-at fault could potentially cause at least one of said one or more incorrect values of said failing test pattern and for each failing test pattern determined to have potentially been caused by any single stuck-at fault, determining a set of nodes of a circuit generating said failing test patterns corresponding to said at least one of said one or more incorrect values, a node being a connection between two gates or two latches or a gate and a latch of a circuit generating said set of failing test patterns; selecting all failing test patterns for which said sets of nodes corresponding to said at least one of said one or more incorrect values were determined; and for those selected failing test patterns determining a first set of sets of nodes, such that all incorrect values of said selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from said first set of sets of nodes.