Patent ID: 8982615
Filing Date: 2015-03-17
Classification: G11C

Abstract:
1. A decoding system for a phase change non-volatile memory device that includes a memory array comprising a plurality of memory cells arranged in rows and columns, the decoding system comprising: a column decoder comprising a programming decoding circuit configured to select at least one of the columns during programming operations of corresponding ones of said plurality of memory cells and comprising a control and timing circuit operatively coupled to said programming biasing circuit and configured to define successive biasing steps, preliminary to the programming operations, and define the first conductive path, each of the successive biasing steps corresponding to a respective biasing condition of said plurality of selection switches by said programming biasing circuit, the successive biasing steps including at least a first step of boosting a voltage of at least one internal node of said programming selection circuit to a value greater than or equal to the upper threshold voltage level, said control and timing circuit being further configured to define the first step of boosting to include at least one of voltage boosting the at least one main column and of the well-biasing terminal to a first pre-charging voltage lower than the programming voltage value and define the successive biasing steps to further include at least one step of boosting a biasing voltage of a control terminal of said plurality of protection elements up to the first pre-charging voltage.