Patent ID: 6175930
Filing Date: 2001-01-16
Classification: G06F

Abstract:
A method of facilitating instruction synchronization in a multiprocessor system, comprising:within each storage device connected to a system bus, responsive to snooping an architected operation on the system bus which may affect data storage within the respective storage device, returning a response code indicating whether the operation is being posted within the respective storage device;setting a flag controlling presentation of synchronization instructions on the system bus in response to eitherreceiving a response code indicating that an architected operation was posted within a storage device connected to the system bus, orreceiving an instruction from a processor corresponding to an architected operation which may affect data storage within other storage devices connected to the system bus; andresponsive to receiving a synchronization instruction from the processor, checking a state of the flag to determine whether a corresponding synchronization operation should be presented on the system bus.