Patent ID: 8331774
Filing Date: 2012-12-11
Classification: H02P

Abstract:
1. A fan controlling circuit, for controlling a rotating speed of fans, comprising: an integral unit, for receiving a first pulse width modulation (PWM) signal and a second PWM signal, and outputting a first voltage corresponding to an operation frequency of the first PWM signal and a second voltage corresponding to an operation frequency of the second PWM signal, wherein the integral unit comprises a first integral circuit for receiving the first PWM signal and outputting the first voltage to the negative input terminal of the operational amplifier, the first integral circuit comprising: an NMOS transistor, wherein a drain of the NMOS transistor is coupled to a first resistor, a source of the NMOS transistor is coupled to a ground terminal, and a gate of the NMOS transistor is coupled to a second resistor, and another end of the second resistor is coupled to the first PWM signal; and a third resistor, serially connected to a capacitor, and another end of the third resistor coupled to a voltage source, wherein another end of the capacitor is coupled to the ground terminal, and another end of the first resistor is coupled to a common node of the third resistor and the capacitor, wherein the common node of the third resistor and the capacitor outputs the first voltage; an operational amplifier, wherein a negative input terminal of the operational amplifier is coupled to the first voltage, and a positive input terminal of the operational amplifier is coupled to the second voltage; a p-channel metal-oxide-semiconductor (PMOS) transistor, wherein a drain of the PMOS transistor is coupled to the first PWM signal, a source of the PMOS transistor is coupled to an output terminal, and a gate of the PMOS transistor is coupled to an output of the operational amplifier; and an n-channel metal-oxide-semiconductor (NMOS) transistor, wherein a drain of the NMOS transistor is coupled to the second PWM signal, a source of the NMOS transistor is coupled to the output terminal, and a gate of the NMOS transistor is coupled to the output of the operational amplifier.