Patent ID: 8898502
Filing Date: 2014-11-25
Classification: G06F,H04L

Abstract:
1. A clock domain crossing interface for transferring data from a source clock domain to a destination clock domain, comprising: at least one pulse sync circuit for receiving a write control signal synchronized to said source clock domain and in response outputting a busy signal to said source clock domain and outputting said write control signal synchronized to said destination clock domain; at least one input register for latching write data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said write data from being latched in the event said busy signal is active so as not to corrupt previously written latched data; and at least one output register for receiving said write control signal from said pulse sync circuit and in response latching said write data from said at least one input register on a transition of said destination clock.