Patent ID: 6038176
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A presettable semiconductor memory device, comprising:an array of memory cells, arranged in m rows and n columns, each of said n columns having a corresponding set of data lines;a row address decoder for outputting row select signals;a column address decoder connected to said array of memory cells and outputting column select signals that are used to control switching of said sets of data lines of said n columns of memory cells to a common set of bit lines;a number n of setting cell circuits, each of said setting cell circuits being connected to said data lines of a corresponding one of said n columns of memory cells, said setting cell circuits being capable of being enabled to output a preset logic state value to said data lines of said corresponding one of said n columns of memory cells;a number m of row controller circuits connected to said array of memory cells, said row address decoder and said column address decoder, said row controller circuits corresponding to said m rows of memory cells and being responsive to said row and column select signals to control access to said m corresponding rows of memory cells;each of said row controller circuits maintaining the corresponding one of said m rows of memory cells in an asserted state upon sensing a write operation for the corresponding one of said m rows of memory cells, and upon sensing a read operation for the corresponding one of said m rows of memory cells subsequent to the write operation;each of said row controller circuits forcing the corresponding one of said m rows of memory cells to a non-asserted state upon sensing a read operation for the corresponding one of said m rows of memory cells when no previous write operation has taken place for the corresponding one of said m rows of memory cells; andan enabling circuit connected to said setting cell circuits and said row controller circuits, said enabling circuit disabling said setting cell circuits so that data can be written into and read from said array of memory cells when any one of said m rows of memory cells is in the asserted state, said enabling circuit enabling said setting cell circuits so that the preset logic state value is output to said data lines of said n columns of memory cells when all of said m rows of memory cells are in the non-asserted state during a read cycle.