Patent ID: 6594194
Filing Date: 2003-07-15
Classification: G11C

Abstract:
A memory array, comprising:a common write word line shared by a first memory bank and a second memory bank; a first write buffer having a first input to receive a first control signal, a second input to receive a data signal, and two or more outputs for asserting an encoded output signal, the first write buffer encodes the data signal and drives a first bit line and a second bit line of the first memory bank with the encoded signal in response to the first control signal, the first write buffer driving each of the outputs when the first control signal is in a selected state so a selected cell of the first memory bank holding a data value maintains the data value when the first control signal is in the selected state; and a second write buffer having a first input to receive a second control signal, a second input to receive a data signal, and two or more outputs for asserting an encoded output signal, the second write buffer encodes the data signal and drives a first bit line and a second bit line of the second memory bank with the encoded signal in response to the second control signal, the second write buffer driving each of the outputs when the second control signal is in a selected state so a selected cell of the second memory bank holding a data value maintains the data value when the second control signal is in the selected state.