Patent ID: 6643215
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A synchronous memory device, comprising:a first clock generator circuit that receives a first clock signal and generates a second clock signal therefrom, the second clock signal lagging the first clock signal by a first predetermined time; a second clock generator circuit that receives the first clock signal and generates a third clock signal therefrom, the third clock signal leading the first clock signal by a second predetermined time; a synchronous read status signal generator circuit, coupled to the first clock generator circuit, that receives a read initiation signal indicative of initiation of a read operation and a read termination signal indicative of termination of the read operation, that produces a transition in a read status signal in response to assertion of either of the read initiation signal or the read termination signal, and that latches the read status signal responsive to the second clock signal to generate a synchronized read status signal; a latency signal generator circuit, coupled to the second clock generator circuit and to the synchronous read status signal generator circuit, that receives the synchronized read status signal and generates a latency control signal therefrom responsive to the third clock signal; a memory cell array; a data output buffer coupled to the memory cell array that receives data from the memory cell array and outputs the received data responsive to an output control signal; and an output control circuit that generates the output control signal responsive to the latency control signal.