Patent ID: 6836868
Filing Date: 2004-12-28
Classification: G01R,G06F

Abstract:
An apparatus for generating an output vector sequence, the apparatus comprising:a vector memory for storing a vector and an accompanying repeat number at each of a plurality of addressable storage locations and for reading out each vector and its accompanying repeat number when addressed by an address of a first address sequence; an address counter for producing and supplying said first address sequence to said vector memory; an instruction memory for storing and reading out an instruction sequence in response to a second address sequence supplied as input thereto; an instruction processor for responding to the instruction sequence by generating the second address sequence and by transmitting control signals to the address counter causing it to produce the first address sequence; and a repeat processor for generating the output vector sequence, wherein in response to each vector and its accompanying repeat number read out of the vector memory, the repeat processor appends N instances of the vector to the output vector sequence, where N is an integer value of its accompanying repeat number.