Patent ID: 7892966
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method of fabricating a unit wiring level in a semiconductor device, the method comprising: forming first and second wiring layers separated by a small space on a support layer, wherein a large space is defined to one side of the first wiring layer; filling the small and large spaces with portions of a thermally degradable material layer; forming a porous insulating layer on the thermally degradable material layer, such that all of the portions of the thermally degradable material are completely covered by corresponding portions of the porous insulating layer; heating portions of the thermally degradable material layer proximate the first and second wiring layers using heat energy generated by applying light radiation to the first and second wiring layers to cause thermal degradation of the portions of the thermally degradable material layer and out-gassing of a resulting gas through the porous insulating layer, such that a first air gap is formed in the large space and a second air gap is formed in the small space while the first air gap and second air gap remain completely covered by the corresponding portions of the porous insulating layer.