Patent ID: 7187685
Filing Date: 2007-03-06
Classification: H04L

Abstract:
1. A multi-module switching system comprising: at least two switching modules for receiving data packets from at least one input adapter and transmitting said data packets to at least one output adapter, each of said switching modules comprising a shared buffer for buffering a portion of a data packet received from said at least one input adapter and transmitting said portion of data packet to said at least one output adapter, one of said switching modules being a master module for receiving a portion of a data packet containing a packet header and sending control information contained therein serially to each other switching module as a slave module, each slave module comprising a delay computing structure for computing a first delay needed to transmit said control information from said master module to said slave module and a first storing structure for storing said portion of data packet transmitted from said at least one input adapter to said slave module during said first delay before transmitting said portion of data packet to said shared buffer such that said portion of data packet is not received by said shared buffer before said slave module has received said control information from said master module.