Patent ID: 7323388
Filing Date: 2008-01-29
Classification: H01L

Abstract:
1. A method for fabricating memory cells, the method comprising: etching a trench having a bottom and lateral walls at a top side of a silicon region; introducing dopant for forming source and drain regions into the top side of the silicon region, the source and drain regions being adjacent to a top side of the trench and at the bottom of the trench; covering the top side of the silicon region which adjoins the trench and the bottom of the trench with a resist mask; implanting nitrogen into the lateral walls of the trench; removing the resist mask; forming a metal silicide layer in those regions of a top side of the silicon region which adjoin the trench and at the bottom of the trench; simultaneously forming a gate dielectric at the lateral walls of the trench and an oxide layer at the top sides of said source and drain regions over the metal silicide layer; and forming a gate electrode in the trench, the gate dielectric arranged between the gate electrode and the lateral walls of the trench.