Patent ID: 6285611
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A memory device having a plurality of memory banks, comprising:a plurality of data lines, each data line being connected in a corresponding one of the plurality of memory banks; andan input/output (IO) sense amplifier shared by at least two memory banks, for selectively sense-amplifying data of the data line connected to one of the at least two memory banks;wherein the IO sense amplifier comprises:at least two current sense amplifiers, each current sense amplifier being connected to a corresponding one of the data lines connected in the at least two memory banks, wherein each current sense amplifier senses current flowing through the data line and outputs a voltage indicating a data value on the data line; anda latch sense amplifier shared by the at least two current sense amplifiers, for sensing the voltage output from one of the current sense amplifiers and amplifying the same to a level which is enough to be transferred to a peripheral circuit.