Patent ID: 8134374
Filing Date: 2012-03-13
Classification: G01R

Abstract:
1. A capacitance evaluation circuit, comprising: an integrator circuit having a first input terminal and a first output terminal, which has an integrated voltage, wherein the integrator circuit is for setting the integrated voltage to be an initial level in response to an enable level of a first control signal; a first control circuit comprising a second output terminal, a to-be-measured capacitor and a capacitance-adjustable circuit, wherein the second output terminal is electrically connected to the first input terminal, the capacitance-adjustable circuit determines an equivalent capacitance approaching a capacitance of the to-be-measured capacitor in response to a signal value of a setting signal, the first control circuit switches voltage levels of at least one end of the to-be-measured capacitor and at least one end of the capacitance-adjustable circuit in response to a first set of clock signals, and thus performs a first adjusting operation to adjust the integrated voltage to be a sum of a present level of the integrated voltage and a first difference voltage, and the first difference voltage is relevant to a difference between the capacitance of the to-be-measured capacitor and the equivalent capacitance; a second control circuit comprising a third output terminal and a known capacitor, wherein the third output terminal is electrically connected to the first input terminal, the second control circuit is for switching a voltage level of at least one end of the known capacitor in response to a second set of clock signals to perform a second adjusting operation to adjust the integrated voltage to be a sum of the present level of the integrated voltage and a second difference voltage; and a processor circuit for providing the first and second sets of clock signals to drive the first and second control circuits to perform the first and second adjusting operations, respectively, for calculating the number of operation times that the second control circuit performs the second adjusting operation in a first integrating period, and for obtaining the capacitance of the to-be-measured capacitor according to the number of operation times and a capacitance of the known capacitor.