Patent ID: 6600204
Filing Date: 2003-07-29
Classification: H01L,Y10S

Abstract:
A bi-directional transient voltage suppression device comprising:a lower semiconductor layer of p-type conductivity; an upper semiconductor layer of p-type conductivity; a middle semiconductor layer of n-type conductivity adjacent to and disposed between said lower and upper layers such that lower and upper p-n junctions are formed, wherein said upper and lower layers have higher peak net doping concentrations than said middle layer, and wherein an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown; a mesa trench extending through said upper layer, through said middle layer and through at least a portion of said lower layer, said mesa trench defining an active area for said device; and an oxide layer covering at least portions of the walls of said mesa trench that correspond to said upper and lower junctions, the distance between said upper and lower junctions being increased at said walls.