Patent ID: 6456519
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A ferroelectric memory device, comprising:a memory array of memory cells organized into rows and columns, including a plurality of word lines, plate lines and bit lines, each row of memory cells being coupled to a word line and a plate line and each column of memory cells being coupled to a bit line, each memory cell comprising at least one ferroelectric capacitor and at least one transistor connected thereto; an address input buffer and timing circuitry for receiving an address signal during a memory access operation, asserting an edge detect signal in response to at least one edge transition appearing on a bit of the address signal, and latching the address signal following the edge detect signal being asserted, the address input buffer and timing circuitry comprises edge detect circuitry for generating the edge detect signal, the edge detect circuitry being disabled from re-asserting the edge detect signal during the memory access operation; control circuitry for receiving the edge detect signal and equilibrating and precharging the column lines and driving the row lines to a low reference voltage level during at least a portion of the time when the edge detect signal is asserted; address decode circuitry for receiving the latched address signal and generating decoded output signals identifying a row of memory cells to connect to the column lines; and data control circuitry for coupling at least one selected column line to data input/output terminals of the ferroelectric memory device.