Patent ID: 7679403
Filing Date: 2010-03-16
Classification: G11C,H03K

Abstract:
1. A dual redundant logic circuit comprising: a precharge circuit that is hardened against single event upset, wherein the precharge circuit comprises four transistors, wherein a first transistor and a second transistor are connected in series to form a first transistor pair, wherein a third transistor and a fourth transistor are connected in series to form a second transistor pair, and wherein the first and second transistor pairs are used to precharge a first output and a second output; a first pull down network connected to the precharge circuit, wherein the first pull down network receives a first set of inputs and controls the first output of the dual redundant logic circuit; and a second pull down network connected to the precharge circuit, wherein the second pull down network receives a second set of inputs substantially the same as the first set of inputs and controls the second output of the dual redundant logic circuit.