Patent ID: 6646907
Filing Date: 2003-11-11
Classification: G11C,H01L

Abstract:
A semiconductor memory de ice comprising:memory cells formed on a main surface of a semiconductor substrate, and each having first and second transistors each having a gate electrode and impurity regions forming source/drain as well as one capacitor; and bit and word lines for controlling an operation of said memory cells, wherein one of said impurity regions forming source/drain of said first transistor is electrically connected with a first bit line and the other impurity region forming source/drain is electrically connected with one electrode of said capacitor, one of said impurity regions forming source/drain of s id second transistor is electrically connected with a second bit line and the other impurity region forming source/drain is electrically connected with the other electrode of said capacitor, and a cell plate of said capacitor is formed of the same lay as said gate electrode.