Patent ID: 7082610
Filing Date: 2006-07-25
Classification: G06F

Abstract:
1. A method for handling exceptions in a multi-processor system, the method comprising: receiving an exception within a processor which is one of a plurality of processors of the multi-processor system which is implemented within a control card of a network element for routine data in networks, wherein each of the plurality of processors in the multi-processor system shares a memory within the multi-processor system, wherein the memory includes a common interrupt handling vector address space shared by the plurality of the processors and a dedicated interrupt handling vector address space for each of the plurality of the processors, and executing one or more instructions at an address associated with a type of the received exception within the common interrupt handling vector address space of the memory, wherein the one or more instructions cause the processor to modify based on an identification of the processor an execution flow of the received exception to execute an interrupt handler located within a respective dedicated interrupt handling vector address spaces associated with the processor, wherein the plurality of processors includes a first processor and a second processor, the first processor executing a first operating system and the second processor executing a second operating system, the second operating system being different from the first operating systems and wherein the first processor along with the first operating system is configured to handle routine of data received within the network element and the second processor along with the second operating system is configured to handle provisioning and configuration of the network element; wherein the first operating system is a real-time operating system handling the routing of data within the network element and the second operating system is a non real-time operating system handling the provisioning and configuration of the network element.