Patent ID: 6140240
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method for removing microscratches in planiarized dielectric surfaces covering conductor layers in submicron integrated circuit structures, comprising the steps of:providing a semiconductor substrate including at least one dielectric layer formed and planarized thereover;providing a chemical vapor deposition apparatus for depositing a PE-CVD polymer layer to fill said microscratches on said planarized dielectric layer;wherein said depositing a PE-CVD Polymer layer has conditions: RF between about 300-800 Watts, Pressure between about 100-500 mTorr, Reactive Gases=C.sub.4 F.sub.8 /CHF.sub.3 /CO/Ar/N.sub.2 ; andetching back well below depth of said microscratches.