Patent ID: 6063660
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A fabricating method of a stacked-type capacitor, comprising the steps of:providing a semiconductor substrate, wherein the semiconductor substrate at least comprises a transistor composing a gate electrode and a source/drain region, a field oxide layer and a conducting structure on the field oxide layer;forming a first dielectric layer on the semiconductor substrate, wherein a via is formed in the first dielectric layer to expose the source/drain region;forming a first conductive layer on the first dielectric layer and into the via;forming a first insulating layer on the first dielectric layer;forming a second dielectric layer on the first insulating layer;forming a second insulating layer on the second dielectric layer;forming a third dielectric layer on the second insulating layer;partially removing the third dielectric layer, the second dielectric layer, the first insulating layer and the second insulating layer to form a channel to expose the first conductive layer and the first dielectric layer, wherein the channel is directly located on the source/drain region;partially removing the first insulating layer and the second insulating layer around the channel to invaginate the margins of the first insulating layer and the second insulating layer to form a dendriform channel;selectively forming a second conductive layer by using the first conductive layer as a nucleating seed to fill the dendriform channel to form a dendriform lower electrode;removing all the first insulating layer, the second insulating layer, the second dielectric layer and the third dielectric layer to expose the dendriform lower electrode;forming a dielectric film on the dendriform lower electrode; andforming a third conductive layer on the dielectric film.