Patent ID: 6140178
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method to form a capacitor on a memory device, comprising the steps of:a) providing a semiconductor substrate to form a transistor therein, when a capacitor is to be formed on said substrate to contact with one region of said transistor, a layer of the first dielectric is deposited on said region, and then planarizing the surface of said first dielectric;b) depositing a layer of the second dielectric on said first dielectric, and then planarizing the surface of said second dielectric;c) etching through said first dielectric and said second dielectric to form a node contact hole above said region;d) depositing a layer of the first polysilicon on said second dielectric to fill up said node contact hole, and then remove the remaining polysilicon on top of said second dielectric so as to form a polysilicon plug in said node contact hole;e) depositing a layer of the third dielectric on said second dielectric and said polysilicon plug;f) etching said third dielectric to form a dielectric mesa near said polysilicon plug;g) depositing a layer of the second polysilicon to cover said dielectric mesa;h) etching said layer of the second polysilicon so that only the peripheral of said mesa will be wrapped with said second polysilicon which forms a polysilicon spacer a one electrode of the capacitor, and wherein only an edge of said spacer is in contact with said polysilicon plug;i) etching away said mesa completely;j) depositing a layer of capacitor dielectric to cover said polysilicon spacer;k) depositing a layer of the third polysilicon to cover said capacitor dielectric;l) etching away unnecessary said third polysilicon and said capacitor dielectric to form a capacitor on said polysilicon plug.