Patent ID: 7860329
Filing Date: 2010-12-28
Classification: A61B,G06T,H04N

Abstract:
1. An edge enhancement processing unit, comprising: a determination block that determines whether a luminance of a surrounding pixel, which is located around a focused pixel, is greater than at zero level; and a signal processing block that performs an edge enhancement process for a pixel signal generated by the focused pixel when said determination block determines that said luminance of said surrounding pixel is greater than at zero level; said signal processing block comprising: an input terminal that receives a pixel signal generated by a pixel; first and second pixel delay circuits that are sequentially connected to said input terminal; first and second multiplier circuits that are connected to output terminals of said first and said second pixel delay circuits, respectively, and that multiply pixel signals, output from said first and said second pixel delay circuits, by first and second coefficients; a third multiplier circuit that is connected to said input terminal, and that multiplies said pixel signal, output from said input terminal, by a third coefficient; a first adder circuit that sums said pixel signals output from said first, said second, and said third multiplier circuits; a fourth multiplier circuit that multiplies said pixel signal output from said first adder circuit by zero when said determination block determines that said luminance of said surrounding pixel is at zero level, and multiplies said pixel signal output from said first adder circuit by a fourth coefficient when said determination block determines that said luminance of said surrounding pixel is greater than at zero level; and a second adder circuit that adds said pixel signal output from said fourth multiplier circuit to said pixel signal output from said first pixel delay circuit.