Patent ID: 6791555
Filing Date: 2004-09-14
Classification: G06F,G09G

Abstract:
A memory system for a graphics processing system receiving a direct memory access request on a memory request bus to access memory, the direct memory access request including a memory address corresponding to a location in memory to be accessed, the memory system comprising:a first addressable memory area defined by a first start address and a first size value to store graphics data; a first memory controller coupled to the first addressable memory area and having a start address register and a memory size register for storing, respectively, the first start address and the first size value, the first memory controller coupled to a first memory request bus to receive the direct memory access request and adapted to access the first addressable memory area in response to the memory address being located therein and to generate an indirect memory access request including the memory address of the direct memory access request otherwise; a memory controller bus coupled to the first memory controller structured to transmit the indirect memory access request and to transmit graphics data; a second addressable memory area defined by a second start address and a second size value to store graphics data; and a second memory controller coupled to a second memory request bus and to the second addressable memory area, the second memory controller having a start address register and a memory size register for storing respectively, the second start address and the second size value, the second memory controller further coupled to the memory controller bus to receive the indirect memory access request from the first memory controller and adapted to access the second addressable memory area in response to the memory address of the indirect memory access request being located therein to service the direct memory access request received by the first memory controller.