Patent ID: 6498100
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A method of manufacturing semiconductor devices having a memory mat region, comprising the steps of:depositing a polishing stopper film on a semiconductor substrate; forming grooves in a field region by etching said polishing stopper film and said semiconductor substrate; depositing an insulating film so as to fill said grooves; partly etching said insulating film in such a manner that a corner and a plurality of pillars of said insulating film are left for said memory mat region; and chemically mechanically polishing said insulating film until said polishing stopper film is exposed; wherein said corner left by said step of partly etching said insulating film surrounds said memory mat region and extends within said memory mat region, and one of said pillars left by said step of partly etching said insulating film has a surface area in plan view that is larger than a surface area in plan view of an active region formed beneath said one of said pillars, and said one of said pillars is over a plurality of active regions formed for said memory mat region.