Patent ID: 6958961
Filing Date: 2005-10-25
Classification: G11B

Abstract:
1. A recording data processing circuit for processing received data sent at a slower data transmission speed than a data processing speed at which to write recording data onto a non-erasable, write-once disk, comprising: a buffer memory for temporarily storing the received data; a data processing circuit for preparing the recording data to record onto the disk, based on the received data read from the buffer memory; a system control circuit for controlling writing and reading of the received data with respect to the buffer memory, and operation of the data processing circuit, and a writing circuit for writing the recorded data supplied from the data processing circuit, onto the disk, wherein the system control circuit suspends operation of the data processing circuit until an amount of received data equivalent to a predetermined writing capacity has been stored in the buffer memory, and releases suspension of the operation of the data processing circuit when an amount of received data equivalent to the predetermined writing capacity has been stored in the buffer memory, said data processing circuit for recording data being placed in a suspended state by interrupting the power supply or by halting the supply of an operation clock, wherein the system control circuit stores an address successive to an address of received data last recorded onto the disk, as a recording start address on the disk, and controls the writing circuit so as to write the recording data supplied from the data processing circuit onto the disk at the recording start address, and wherein the system control circuit synchronizes the recording data to be newly recorded onto the disk, supplied from the data processing circuit to the writing circuit, with recording data recorded on the disk, said data processing circuit being operated in synchronism with a reproduction clock obtained by reproducing the data already recorded on the disk.