Patent ID: 7280620
Filing Date: 2007-10-09
Classification: G06F

Abstract:
1. An electronic device having a main processing unit and a plurality of sub-processing units, wherein each of the main processing unit and the plurality of sub-processing units includes a first bus-connecting unit for connecting a bus for data input, a second bus-connecting unit for connecting a bus for data output, and means for processing a process request packet directed to itself, and for bypassing a process request packet, directed to the other one and input from the first bus-connecting unit, to the second bus-connecting, and wherein the main processing unit further includes a signal terminal for sending test signals to each of the plurality of sub-processing units, the signal terminal being directly connected to each of the plurality of the sub-processing units, and wherein upon receiving the test signal, each of the plurality of sub-processing units outputs an interrupt packet via the second bus-connecting unit, and wherein a data bus in a loop is formed that connects the main processing unit and the sub-processing units, said electronic device comprising: determining means for outputting, to the second bus-connecting unit in the main processing unit, a command packet bypassed by all of the plurality of sub-processing units, and returned to the first bus-connecting unit of the main processing unit, to determine whether an error exists on the data bus in the loop, and identifying means for, in a case where an error exists, sending the test signal to each of the sub-processing units via the signal terminal of the main processing unit, wherein the identifying means determines whether the interrupt packet for the test signal has been received in order to identify a location of said error.