Patent ID: 9105509
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A computerized method of simultaneously comparing timing of conductive signal paths in a substrate and a printed circuit board to achieve a predetermined signal timing goal, said method comprising: identifying a conductor group within an integrated circuit design using a computing device, said conductor group comprising a plurality of substrate conductors within said substrate and a plurality of board conductors within said printed circuit board, each combination of substrate conductor and board conductor comprising one of a plurality of combined substrate-board conductors; automatically calculating a substrate-based length of time it will take a signal to pass within each of said substrate conductors within said conductor group based on a length of each of said substrate conductors and based on a speed with which signals pass within said substrate, using said computing device; automatically calculating a board-based length of time it will take a signal to pass within each of said board conductors within said conductor group based on a length of each of said board conductors and based on a speed with which signals pass within said printed circuit board, using said computing device; automatically adding said substrate-based length of time and said board-based length of time for each of said combined substrate-board conductors to produce a combined timing for each of said combined substrate-board conductors, using said computing device; automatically comparing said combined timing of each said combined substrate-board conductors to determine whether said combined substrate-board conductors pass signals within a predetermined timing variance limit, using said computing device; automatically reporting results of said comparing of said combined timing of each of said combined substrate-board conductors, using said computing device; and automatically providing user options to alter lengths of ones of said substrate-board conductors that do not comply with said predetermined timing variance limit, using said computing device.