Patent ID: 6512273
Filing Date: 2003-01-28
Classification: H01L

Abstract:
In an integrated circuit CMOS structure on a silicon wafer substrate including a p-channel device in an n-type region of said substrate with a gate separated from said substrate by a gate dielectric, said gate having edge surfaces and a top surface, and further including an n-channel device in a p-type region of said substrate with a gate separated from said substrate by a gate dielectric, said gate having edge surfaces and a top surface, said n-channel device being separated from said p-channel device by an insulating region, the improvement comprising:said edge surfaces of said gate of said p-channel device having p-channel device sidewall spacers thereon, said p-channel device sidewall spacers being comprised of a first spacer material; said edge surfaces of said gate of said n-channel device having n-channel device sidewall spacers thereon, wherein said n-channel device sidewall spacers are comprised of a second spacer material and wherein said n-channel device sidewall spacers do not include said first spacer material; wherein said first spacer material comprises silicon nitride, and said second spacer material comprises polysilicon.