Patent ID: 6893912
Filing Date: 2005-05-17
Classification: H01L

Abstract:
1. A method for fabricating a ferroelectric capacitor memory device comprising: forming a substrate comprising integrated circuitry including an interconnect layer and pass transistors; simultaneously forming first capacitor electrodes, contacts and pads on said substrate, said first capacitor electrodes being connected to associated pass transistors through said interconnect layer; forming a ferroelectric dielectric layer upon said first capacitor electrodes, contacts and pads; patterning said ferroelectric dielectric layer to (a) expose a portion of a chosen one of said contacts to form a contact opening, and (b) expose a portion of a chosen one of said pads to form a pad region; forming a second capacitor electrode over said patterned ferroelectric dielectric layer to create a via within said contact opening, said via extending to said chosen one of said contacts; forming a conductive layer upon said second capacitor electrode; and patterning said conductive layer, to form a plate line, said via connecting said chosen one of said contacts to said plate line.