Patent ID: 8994096
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. Multi-transistor memory cell arranged on a semiconductor substrate comprising: an access transistor and a memory transistor, the access transistor comprising an enhancement junction field effect transistor having an access channel region, a first implant and a second implant, a first diffusion implant and a second diffusion implant, and an access gate, wherein the access channel region is arranged intermediate the first implant and the second implant, the first implant and the second implant is arranged intermediate the first diffusion implant and the second diffusion implant, the access gate is arranged above the access channel region, the memory transistor comprises a memory channel region, a third implant and a fourth implant, a third diffusion implant and a fourth diffusion implant, a memory gate stack, and a memory gate, the memory channel region is arranged intermediate the third implant and the fourth implant, the third implant and the fourth implant is arranged intermediate the third diffusion implant and the fourth diffusion implant, the memory gate stack is arranged above the memory channel region, and the memory gate is arranged above the memory gate stack.