Patent ID: 6109201
Filing Date: 2000-08-29
Classification: G06F

Abstract:
A method of improving performance of an integrated circuit having critical paths of cells, each cell having one or more inputs, including a critical path input, and one or more outputs, including a critical path output, said method comprising the steps of:defining blocks, each defined block comprising one or more cells of the critical path and having a critical input and a critical output, wherein said step of defining blocks comprises the step of segmenting the critical path cells into groups of cells;transforming said defined blocks to decrease delay of the critical path;wherein said step of segmenting the critical path cells comprises the steps of:(1) determining a target delay, T.sub.trg ; and(2) determining a first segmentation value (S value) into which the critical path cells will be divided,wherein said first segmentation value, S.sub.trg1, isS.sub.trg1 =((mT.sub.trg /T.sub.c-path)-(m(m(T.sub.trg /T.sub.c-path).sup.2 -4)).sup.1/2)/2whereT.sub.trg is said target delay;T.sub.c-path is the delay of the critical path; andm is T.sub.c-path /T.sub.mux where T.sub.mux is the delay of a multiplexor used in said step of transforming each of said defined blocks.