Patent ID: 6504780
Filing Date: 2003-01-07
Classification: G06F,G11C

Abstract:
A memory system comprising:an array of memory cells, wherein each of the memory cells must be periodically refreshed to retain a data value; a terminal for receiving an external clock signal that periodically transitions between a first state and a second state; a terminal for receiving an external access signal that is activated to indicate a requested read or write access to the array; a refresh controller configured to periodically activate a refresh request signal; and a memory array sequencer coupled to receive the external clock signal, the external access signal, and the refresh request signal, the memory array sequencer being configured to implement a read or write access to the array when the external access signal is activated and the external clock signal transitions to the first state, the memory array sequencer further being configured to implement a refresh access to the array when the refresh request signal is activated and the external clock signal transitions to the second state.