Patent ID: 6480047
Filing Date: 2002-11-12
Classification: H03L,H04J,Y10S

Abstract:
A digital phase locked loop for generating a stable output clock signal from at least one reference frequency signal, comprising:a phase detector for detecting a phase difference between said reference frequency signal and said stable output clock signal and producing a phase error signal representative of the phase difference; a digital controlled oscillator for receiving said phase error signal and generating an output signal at a desired frequency and a control signal representing a time error in said output signal; a stable local oscillator for providing a clock signal to said digital controlled oscillator; a plurality of tapped delay lines for generating said stable output clock signal each of said tapped delay lines comprising a plurality of delay elements, the sum of the delay of each of said plurality of tapped delay lines being less than the period of said output signal of said digital controlled oscillator; each of said plurality of tapped delay lines including a coarse, tapped delay line for receiving the output signal of said digital controlled oscillator; and a fine, tapped delay line for receiving the output signal of said coarse tapped delay line, said fine tapped delay line having a plurality of delay elements having a delay time proportional to one of said coarse tapped delay line delay elements; and at least one ring oscillator comprising a plurality of said tapped delay elements for producing a clock output signal for controlling said coarse and fine tapped delay lines.