Patent ID: 7364948
Filing Date: 2008-04-29
Classification: H01L

Abstract:
1. A fabrication method of a semiconductor package, comprising the steps of: providing a substrate having an opening, a lead frame having a plurality of leads, and at least one chip having an active surface and a non-active surface, wherein the substrate further comprises an upper surface and a lower surface opposed to the upper surface, with at least one first circuit layer and at least one second circuit layer being respectively formed on the upper surface and the lower surface and being electrically connected to each other; mounting the lead frame on the substrate, and electrically connecting the plurality of leads to the first circuit layer on the upper surface of the substrate; mounting the active surface of the chip on the lead frame, and electrically connecting the active surface to the leads via a plurality of bonding wires formed in the opening; and forming an encapsulant on the substrate to fill the opening and encapsulate the chip, the lead frame and the upper surface of the substrate.