Patent ID: 6845438
Filing Date: 2005-01-18
Classification: G06F,G11C

Abstract:
1. A method for controlling a non-volatile semiconductor memory system, the method comprising: defining a plurality of physical blocks in a cell array of non-volatile semiconductor memory cells, each of the physical blocks including a plurality of non-volatile memory cells adapted for storing data; storing address mapping information between the physical blocks and corresponding logical blocks in the physical blocks; defining within the cell array at least first and second zones, each zone including at least one of the physical blocks; preparing, in response to a power supply being turned on, a prepared address translation table comprising address translation information between logical blocks and physical blocks within the memory array, the prepared address translation table including address translation information for logical block addresses within at least the first zone and not including address translation information for logical block addresses within at least the second zone; and determining that a requested logical block is not within the prepared address translation table and subsequently preparing a second address translation table comprising address translation information for logical block addresses within the second zone.