Patent ID: 8984319
Filing Date: 2015-03-17
Classification: G01R,G06F,H04L

Abstract:
1. A circuit device comprising: A. a test data in lead, a test data out lead, a test clock lead carrying test clock signals, and a test mode select lead; B. adapter circuitry that includes a first test access port controller coupled with the test clock lead and the test mode select lead, the firsts test access port controller having the states of Test Logic Reset, Run Test/Idle, Select-DR Scan, and Select-IR Scan; C. test logic circuitry that includes a second test access port controller coupled with the test clock lead and the test mode select lead, the second test access port controller having the states of Test Logic Reset, Run Test/Idle, Select-DR Scan, and Select-IR Scan; D. the adapter circuitry including power up circuitry that can: