Patent ID: 7075157
Filing Date: 2006-07-11
Classification: H01L,Y10S

Abstract:
1. A semiconductor device, comprising: a static memory cell including first and second driver MISFETs and first and second load MISFETs, and first and second transfer MISFETs; and a capacitor element including a first electrode, a dielectric layer, and a second electrode, wherein gates of said first driver MISFET and said first load MISFET are formed by a first gate layer, and wherein gates of said second driver MISFET and said second load MISFET are formed by a second gate layer; and first and second voltage lines, extending in a first direction crossing a second direction in which said first and second gate layers extend, wherein a third layer forming said first electrode electrically connects the drains of said first driver MISFET and said first load MISFET, wherein a fourth layer forming said second electrode electrically connects the drains of said second driver MISFET and said second load MISFET, wherein said third layer is formed between said first gate layer and said fourth layer, wherein a size of said fourth layer is larger than a size of said third layer, wherein said first and second voltage lines are metal layers, and wherein said fourth layer comprises a tungsten layer.