Patent ID: 7291927
Filing Date: 2007-11-06
Classification: H01L

Abstract:
1. A dual chips stacked packaging structure, comprising: a first chip, having an active surface and an opposing non-active surface, the active surface consisting of a central area and a peripheral area having a plurality of first bonding pads; a lead frame, comprising a plurality of leads and a chip paddle having a first adhering surface and a second adhering surface, the first adhering surface adhered to the active surface of the first chip in such a way as to avoid contact with the first bonding pads; a second chip, having an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, the active surface consisting of a central area and a peripheral area having a plurality of second bonding pads, wherein the central area of the active surface of the first chip directly adheres to the first adhering surface of the chip paddle while an opposing central area of the opposing non-active surface of the second chip adheres to the second adhering surface of the chip paddle, and wherein the opposing central area of the opposing non-active surface of the second chip is opposite to the central area of the active surface of the second chip; and a plurality of wires, wherein parts of the wires electrically connect with the first bonding pad and the leads, and parts of the wires electrically connect with the second bonding pad and the leads.