Patent ID: 6171973
Filing Date: 2001-01-09
Classification: G03F,H01L

Abstract:
Process for etching a gate material in the fabrication of MOS transistors, comprising:a) a thin and porous layer of a SiON-based alloy whose composition is Si.sub.x O.sub.y N.sub.z, in which x is between about 0.35 and 0.45 and z is between about 0.40 and 0.60, y differing from zero and making the total of x+y+z up to 1, is deposited on a semiconductor substrate already coated with a thermal oxide first layer and with a second layer comprising polycrystalline silicon;b) the said SiON-based layer is etched, using a resin mask produced on the SiON-based layer, in order to form a hard mask;c) after the masking resin has been removed, the region predefined by the hard mask in the layer based on polycrystalline silicon or on a silicon-germanium alloy is etched in order to form the future gate; andd) the SiON-based layer is removed.