Patent ID: 7091590
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A multiple stacked-chip packaging structure, including: a substrate; at least one lower layer chip located on and in contiguous contact with the substrate, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the lower layer chip and to the substrate; at least one carrier cap located on the lower layer chip and having an open cavity overlaying at least a portion of the plurality of bonding pads to provide an accommodating space to the bonding pads and the wires, the carrier cap having open sides in open communication with the accommodating space for passage of the wires therethrough; at least one upper layer chip located on an upper surface of the carrier cap, wherein a plurality of wires are respectively electrically connected to a plurality of bonding pads on the upper layer chip and to the substrate; and a molding compound to encapsulate the foregoing components.