Patent ID: 9087912
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method for wafer level packaging, comprising: providing a first wafer including a surface, wherein a dielectric layer and a first conducting pillar are disposed on the surface and the first conducting pillar is configured to penetrate through the dielectric layer; singulating the first wafer to form a first die; forming a through hole in an interposer, wherein the interposer includes a first surface and a second surface opposite to the first surface, and a thickness of the interposer is less than or equal to a length of the first conducting pillar; disposing the first wafer on the first surface of the interposer and disposing the first conducting pillar inside the through hole; covering an encapsulation layer on the first die and a portion of the interposer; coating a first electric insulation layer on the second surface of the interposer; forming a redistribution layer on the first electric insulation layer, wherein the redistribution layer is electrically coupled to the first conducting pillar; and disposing a solder ball on the redistribution layer.