Patent ID: 8963603
Filing Date: 2015-02-24
Classification: H03K

Abstract:
1. A clock generation device, comprising: a first delay unit for receiving an input clock and delaying the input clock by a first preset period to generate an input delay clock; a frequency divider for receiving the input delay clock and dividing a frequency of the input delay clock to generate a first frequency-divided clock and a second frequency-divided clock, wherein a frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock; an angle delay unit for delaying the first frequency-divided clock by a second preset period to generate a first delay clock at a first output terminal of the angle delay unit; and a first calculating unit for determining a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determining a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.