Patent ID: 6724668
Filing Date: 2004-04-20
Classification: G11C

Abstract:
A semiconductor device, comprising:a plurality of memory chips, each including a plurality of memory cells preassigned respectively with specific address signals, a spare memory cell for replacement of defective one of said plurality of memory cells, a holding circuit for holding the address signal of said defective memory cell, a memory cell select circuit receiving an address signal and selecting said spare memory cell for replacement of the memory cell corresponding to the received address signal when the received address signal matches the address signal held in said holding circuit, and selecting the memory cell corresponding to the received address signal when the received address signal differs from the address signal held in said holding circuit, and a write/read circuit performing writing/reading of a data signal to/from the memory cell selected by said memory cell select circuit; a tester circuit testing said plurality of memory chips in parallel, and obtaining the address signal of the defective one of said plurality of memory cells in each memory chip; a nonvolatile memory storing the address signal obtained by said tester circuit; and a transfer control circuit reading the address signal out of said nonvolatile memory for transfer to the holding circuit in the memory chip corresponding to the address signal.