Patent ID: 9122443
Filing Date: 2015-09-01
Classification: G06F,G09G

Abstract:
1. A vertical synchronization circuit for synchronizing multiple video streams using an input vertical sync signal, comprising: a digitally controlled circuit configured to generate a digital phase locked vertical sync value from the input vertical sync signal and an output vertical sync signal in a digital phase lock loop and to generate an intermediate horizontal sync signal at a frequency higher than the frequency of the input vertical sync signal based on the digital phase locked vertical sync value using a local oscillator clock signal having a higher frequency than the intermediate horizontal sync signal, the intermediate horizontal sync signal being locked to the input vertical sync signal, wherein the digital phase locked vertical sync value is a number representing the number of pulses of the local oscillator clock signal per the input vertical sync signal, and the digital phase vertical sync value is provided by an adder in the digital phase locked loop; an analog phase lock loop circuit configured to convert the intermediate horizontal sync signal into a pixel clock; and a circuit configured to generate the output vertical sync signal and an output horizontal sync signal based on the pixel clock, wherein the digitally controlled circuit comprises counters configured to generate the intermediate horizontal sync signal based on the digital phase locked vertical sync value and a programmable number of intermediate horizontal sync pulses of the intermediate horizontal sync signal per the input vertical sync signal.