Patent ID: 6307803
Filing Date: 2001-10-23
Classification: G11C

Abstract:
A dynamic random access memory structure suitable for use as a compatible transistor in a static random access memory, wherein the dynamic random access memory structure is operated under a normal operation mode and a low voltage operation mode, and uses a reference clock signal as an operation accordance, the dynamic random access memory comprising:a memory cell, to store a data;a sense amplifier, comprising sense unit, a first transistor and a second transistor, wherein the sense unit is connected to the first transistor, the second transistor, a bit line and a complementary bit line, the bit line and the complementary bit line are used to access and refresh the data stored in the memory cell, and a frequency for refreshing the data stored in the memory cell is according to the reference clock signal; anda switch, to receive a first voltage and a second voltage, and to select one of the first and the second voltages, wherein the first voltage has a voltage level higher than a voltage level of the second voltage; whereinwhen the dynamic random access memory structure is operated under the normal operation mode, the second voltage is an operation voltage to provide the operation of the dynamic random access memory structure to reduce power consumption; andwhen the dynamic random access memory structure is operated under the low voltage operation mode, the first voltage is the operation voltage to retain the data stored in the memory cell.