Patent ID: 8627253
Filing Date: 2014-01-07
Classification: G06F

Abstract:
1. A method for substrate noise analysis, the method comprising: using a first processor based system, creating a circuit schematic comprising a first circuit, an aggressor circuit, and a substrate network coupling the first circuit to the aggressor circuit, wherein the first circuit comprises a transistor, an intra-transistor component being within the transistor, and wherein the substrate network is based on physical features of an expected die size; using a second processor based system, simulating the circuit schematic thereby resulting in simulation results; determining when the simulation results are unacceptable; upon determining when the simulation results are unacceptable, modifying a representation of a physical feature of the intra-transistor component that is present in the circuit schematic during the simulating the circuit schematic, wherein the physical feature comprises at least one of: thereafter, creating a layout based on a plurality of properties represented in the circuit schematic.