Patent ID: 6194918
Filing Date: 2001-02-27
Classification: G01R

Abstract:
A frequency detector responsive to a predetermined number, K, of input signals, where K is a positive integer, said frequency detector comprising;a counter responsive to a clock signal for generating a counter signal which represents a running counter value in a counter sequence, wherein said counter makes a wrap at the end of said counter sequence and starts over again from the beginning of said counter sequence;K first registers, each one of said K first registers being responsive to said counter signal and a respective one of said K input signals for updating an individual first counter value by storing the current counter value of said counter signal generally in response to timing information carried by the respective input signal;K second registers, each one of said K second registers being connected to a respective one, referred to as its associated first register, of said K first registers and being responsive to the first counter value of its associated first register and to the same input signal as its associated first register for backing-up, prior to said updating, said first counter value as a back-up counter value, in response to said timing information carried by said input signal;subtractor means responsive to the counter values of each register pair that comprises an individual second register and its associated updated first register, for subtracting, for each register pair, the counter values of said register pair to generate a respective difference value representative of the frequency of the input signal that is associated with said register pair; andcorrection means for correcting for a difference value effecting wrap, by adding a positive/negative correction value to the difference value so as to generate a corrected difference value, or by adding said correction value to a counter value in a register pair, said corrected counter value being used in generating the difference value.