Patent ID: 6414530
Filing Date: 2002-07-02
Classification: G11C,H03K

Abstract:
A clock synchronous circuit comprising:a first delay circuit which receives therein a first clock signal delayed from a reference clock signal and propagates the first clock signal with a first time resolution; a first edge detector which compares an edge of a delay signal of each stage corresponding to the time resolution of said first delay circuit with a first clock edge of the reference clock signal to thereby detect time coincidence between both edges; a first multiplexer controlled by a signal detected by said first edge detector so as to output a delay signal which has a timing of a corresponding delay stage of said first delay circuit; a second delay circuit which receives therein a second clock signal obtained through said first multiplexer and propagates the second clock signal with a second time resolution higher in accuracy than the first time resolution; a second edge detector which compares an edge of a delay signal of each stage corresponding to the time resolution of said second delay circuit with a second clock edge of the reference clock signal to thereby detect time coincidence between both edges; and a second multiplexer controlled by a signal detected by said second edge detector so as to output a delay signal which has a timing of a corresponding delay stage of said second delay circuit; whereby an internal clock signal synchronized with the reference clock signal or a signal corresponding to the reference clock signal is formed based on a third clock signal obtained through said second multiplexer, said second delay circuit including, a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals, said each impedance element being provided between the first and second input terminals, and respectively form output signals according to the input signals supplied to the first and second terminals, said plurality of logic gate circuits being capable of being disposed in lattice form in a first signal transfer direction and a second signal transfer direction, and wherein the first input terminal of a logic gate circuit KL provided as a Kth other than the first as seen in the first signal transfer direction and disposed in an Lth stage as seen in the second signal transfer direction is supplied with a signal outputted from a logic gate circuit provided as the same Kth as seen in the first signal transfer direction and defined as an Lâˆ’1th stage as seen in the second signal transfer direction or an input clock signal in the case of the first-stage logic gate circuit, the second input terminal of the logic gate circuit KL is supplied with an input signal supplied to a first input terminal of a logic gate circuit provided as the immediately preceding Kâˆ’1th as seen in the first signal transfer direction and defined as the same Lth stage as seen in the second signal transfer direction; a second input terminal of a logic gate circuit provided as the first as seen in the first signal transfer direction and defined as an Lth as seen in the second signal transfer direction is supplied with an input signal supplied to a first input terminal of a logic gate circuit defined as the final stage as seen in the first signal transfer direction, said input signal being in phase with an input signal supplied to a first input terminal of a logic gate circuit at a stage preceding the final stage as seen in the second signal transfer direction; the first and second input terminals of the logic gate circuits defined as the first stage as seen in the second signal transfer direction and provided as the first as seen in the first signal transfer direction are respectively supplied with a clock signal corresponding to the second clock signal, and the input clock signals supplied to the first input terminals of the respective logic gate circuits extending from the second to the last as seen in the first signal transfer are delayed in order in the first signal transfer direction; and output signals are respectively obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.