Patent ID: 7583153
Filing Date: 2009-09-01
Classification: H03K

Abstract:
1. A multiphase synchronous clock multiplexer circuit, the circuit comprising: a first multiphase clock, wherein the first multiphase clock includes at least a first phase clock, a second phase clock, a third phase clock and a fourth phase clock; a second multiphase clock, wherein the second multiphase clock includes at least a fifth phase clock, a sixth phase clock, a seventh phase clock and an eighth phase clock; a select signal synchronizing circuit, wherein the select signal synchronizing circuit receives a select input and synchronizes the select input to either the fourth phase clock or the eighth phase clock to generate a first select output depending upon an assertion level of the first select output; wherein the select signal synchronizing circuit receives a second select output and synchronizes the second select output to the fifth phase clock to generate a fourth select output; and wherein the select signal synchronizing circuit receives a third select output and synchronizes the third select output to the first phase clock to generate a fifth select output; a first multiplexing block, wherein the first multiplexing block receives the first phase clock, the second phase clock, the fifth phase clock and the sixth phase clock; and wherein the first multiplexing block provides a first multiphase output including a combination of the first phase clock and the second phase clock or a combination of the fifth phase clock and the sixth phase clock depending upon a combination of the first select output, the fourth select output and the fifth select output; and a second multiplexing block, wherein the second multiplexing block receives the third phase clock, the fourth phase clock, the seventh phase clock and the eighth phase clock; wherein the second multiplexing block provides a second multiphase output including a combination of the third phase clock and the fourth phase clock or a combination of the seventh phase clock and the eighth phase clock depending upon a combination of the first select output, the fourth select output and the fifth select output; and wherein the second multiplexing block generates the second select output and the third select output based at least in part on the first select output.