Patent ID: 6255729
Filing Date: 2001-07-03
Classification: G01R,H01L

Abstract:
A multi chip package (MCP) comprising:(a) an MCP substrate;(b) a first semiconductor chip mounted on the MCP substrate having a control circuit configured to control signal transfer through the first semiconductor chip from an input of the first semiconductor chip to an output thereof;(c) MCP leads connected to a perimeter portion of the MCP substrate and configured to receive signals from external circuits;(d) MCP terminal wires disposed on the MCP substrate, said MCP terminal wires being configured to connect the MCP leads to the input of the first semiconductor chip so as to provide signals thereto;(e) a second semiconductor chip mounted on the MCP substrate having a second semiconductor chip input to receive signals applied thereto;(f) interface signal wires disposed on the MCP substrate and configured to connect the output from the first semiconductor chip to the input of the second semiconductor chip to provide for a normal mode transfer of signals between the first semiconductor chip and the second semiconductor chip;(g) at least one first extra bonding pad disposed on the MCP substrate said at least one first extra bonding pad being electrically connected to at least one of the interface signal wires and further being normally electrically isolated from other electrical connections during the normal mode transfer of signals between the first semiconductor chip and the second semiconductor chip; and(h) at least one second extra bonding pad disposed on the MCP substrate, said second extra bonding pad being electrically connected to at least one of the MCP leads and arranged near the at least one first extra bonding pad and further being normally electrically isolated from other electrical connections during the normal mode transfer of signals between the first semiconductor chip and the second semiconductor chip and being connected to the at least one first extra bonding pad during a ""failure analysis mode"" so that a signal can be provided to the second semiconductor chip during the ""failure analysis mode"",wherein the control circuit inhibits the transfer of signals between the first semiconductor chip and the second semiconductor chip during the ""failure analysis mode"".