Patent ID: 7028108
Filing Date: 2006-04-11
Classification: G06F

Abstract:
1. A system for controlling data transfer, comprising: a data bus which has an n-bit byte width and passes an input data; a data register which has a (2n−1)-bit byte lane and receives the input data, wherein the data register outputs the input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width when the input data lacks the set data width, in response to a first enable signal; a first selector which is located at an input side of the data resister and selects an n-bit byte lane from the (2n−1)-bit byte lane of the data register in response to a first select signal; a second selector which is located at an output side of the data resister and selects an n-bit byte lane out of a (2n−1)-bit byte lane and outputs a valid data in response to a second select signal; a data buffer which has an n-bit byte lane, wherein the data buffer receives and stores the valid data in response to a second enable signal; and a controller which generates the first and second select signals, and the first and second enable signals; wherein the controller generates the first select signal in accordance with a number of byte enable signals provided during a previous cycle.