Patent ID: 6504785
Filing Date: 2003-01-07
Classification: G06F

Abstract:
In a multiprocessor processing system, a memory system comprising:a controller for linking at least two processing units to a memory; and an integrated memory coupled to said controller, said integrated memory having a plurality of banks, each having a plurality of static random access cell arrays and a dynamic random access cell array coupled to said SRAM, and a data port for coupling said plurality of banks to said controller each of said banks further comprising: a plurality of sets of latches each for storing address bits associated with data stored in a corresponding one of said static random access cell arrays; and bit comparison circuitry for comparing an address bit received from said controller with an address bit stored in each of said plurality of sets of latches, and enabling access to a selected one of said static random access cell arrays corresponding to a said set of latches storing an address bit matching said received address bits.