Patent ID: 6785171
Filing Date: 2004-08-31
Classification: G11C

Abstract:
A semiconductor memory device comprising:a main wordline; a plurality of sub-wordlines corresponding to the main wordline; a plurality of main memory cells each being coupled to one of the sub-wordlines; a sub-wordline selector for activating at least one of the sub-wordlines based on a first external address; a main wordline selector for activating the main wordline based on a second external address; at least one redundancy main wordline; a plurality of redundancy sub-wordlines corresponding to the redundancy main wordline; a plurality of redundancy memory cells each being coupled to one of the redundancy sub-wordlines; and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline, wherein the number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline; and wherein the redundancy control circuit enables the main wordline and sub-wordline selectors when among the sub-wordlines, a sub-wordline to which a normal main memory cell is coupled is addressed.