Patent ID: 6822959
Filing Date: 2004-11-23
Classification: G06F

Abstract:
An integrated circuit for processing communication packets, said integrated circuit comprising:a core processor configured to execute software to process a series of communication packets, the processing of each packet being an event and having associated data and context information, said core processor having two sets of data registers, each set of data registers being capable of storing the context and data information required to process one packet, said core processor using said sets of registers alternatively; and a co-processor having a plurality of data buffers configured to store data and context information associated with a plurality of packets, data and context from one packet being transferred to one of said sets of data registers in said core processor while said core processor is utilizing data and context information stored in a different set of data registers in said core processor, whereby said core processor need not wait between packet processing in order to load data in said registers; and means for preventing the occurrence of two back to back events which use the same context data.