Patent ID: 8900949
Filing Date: 2014-12-02
Classification: H01L

Abstract:
1. A method of manufacturing a staggered column vertical superjunction semiconductor device comprising: a) applying a first mask to a surface of a first semiconductor layer of a first conductivity type, wherein the first mask is patterned with openings positioned at locations where first columns are to be located and no openings at locations where second columns are to be located, wherein the first and second columns alternate with each other in a row; b) implanting dopants having a second conductivity type into the first semiconductor layer through the openings of the first mask to form first implanted regions at the locations where the first columns are to be located without forming the first implanted regions at the locations where the second columns are to be located; c) growing a second semiconductor layer of the first conductivity type on top of the first semiconductor layer; d) applying a second mask on a surface of the second semiconductor layer, wherein the second mask is patterned with openings positioned at both the locations where the first columns are to be located and the locations where the second columns are to be located; e) implanting dopants having the second conductivity type into the second semiconductor layer through the openings of the second mask to form second implanted regions at both the locations where the first columns are to be located and the locations where the second columns are to be located; and f) repeating steps c) through e) one or more times to form the first and second columns of the second conductivity type in a cumulative semiconductor layer of the first conductivity type, whereby the cumulative semiconductor layer comprises the first semiconductor layer and a plurality of subsequent second semiconductor layers grown on top of it, and wherein at least some of the first columns are located in an active cell region.