Patent ID: 6768156
Filing Date: 2004-07-27
Classification: G11C,H01L

Abstract:
A memory device comprising:a crystalline layer separated from a substrate by an insulative material; the crystalline layer being less than or equal to about 2000 Ã¥ thick and comprising a material which includes silicon and germanium; a gate proximate the crystalline layer; a pair of source/drain regions proximate the gate and extending into the crystalline layer; accordingly, at least a portion of the source/drain regions being within the crystalline layer; the portion of the source/drain regions within the crystalline layer being contained within a single crystal of the material which includes silicon and germanium; a channel region extending between the source/drain regions, the channel region being part of a portion of the memory device that is oppositely doped relative to the source/drain regions; a gate insulator stack between the channel region and the gate, the gate insulator stack including a floating plate which is electrically connected to one of the source/drain regions; and a diode electrically connecting said one of the source/drain regions to the portion of the memory device that is oppositely doped relative to the source/drain regions.