Patent ID: 7277134
Filing Date: 2007-10-02
Classification: H04N

Abstract:
1. A chrominance signal demodulation apparatus comprising: a loop filter including a clock timing change unit which selectively outputs a clock signal synchronized with a burst signal, and a clock signal that is delayed by 90 degrees with respect to the phase of the clock signal synchronized with the burst signal, from a chrominance component signal that is a quantized signal, on the basis of the polarity of an R-Y component signal of a PAL system signal, said loop filter generating a clock signal that is synchronized with the burst signal and has a frequency N times (N: integer not less than 2) as high as that of the burst signal; a chrominance signal multiplexing unit for separating the chrominance component signal into an R-Y component signal and a B-Y component signal on the basis of the clock signal outputted from the loop filter, and outputting a signal that is obtained by alternately multiplexing the R-Y component signal and the B-Y component signal; an arithmetic unit for rotating, by 45 degrees, the phase axis of the multiplexed signal outputted from the chrominance signal multiplexing unit, and calculating correlation between the multiplexed signal and a 1H delay signal that is obtained by delaying the multiplexed signal by one cycle of a horizontal sync signal; an R-Y inversion unit for selectively changing the polarity of the R-Y component signal of the signal outputted from the arithmetic unit, on the basis of the polarity of the R-Y component signal of the PAL system signal; an R-Y output unit for outputting the R-Y component signal outputted from the R-Y inversion unit; and a B-Y output unit for outputting the B-Y component signal of the signal outputted from the arithmetic unit.