Patent ID: 6642101
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method for producing a semiconductor memory device comprising a plurality of memory cells each having a memory capacitor having a storage node electrode and a transistor, including:a step of forming said transistor on a substrate, a step of forming a first insulating film covering said transistor, a step of opening a storage node contact hole reaching a source and drain region of said transistor in said first insulating film, a step of forming a storage node contact plug by filling said storage node contact hole by a conductor, a step of forming a second insulating film having a different etching selectivity from that of said first insulating film above said first insulating film, a step of forming a third insulating film having a different etching selectivity from that of said second insulating film above said second insulating film, a step of opening a portion acting as a mold for forming the storage node electrode and exposing at least the top surface of said storage node contact plug in said second insulating film and said third insulating film, a step of etching to selectively remove said first insulating film and said third insulating film with respect to said second insulating film to cause a bottom surface and a side wall surface of said opening portion to retract, a step of forming the storage node electrode connected to said storage node contact plug while bringing it in contact with said second insulating film by using said opening portion as a mold, a step of removing said third insulating film by using said second insulating film as an etching stopper, a step of forming a capacitor insulating film above said storage node electrode, and a step of forming a plate electrode above said capacitor insulating film.