Patent ID: 6459730
Filing Date: 2002-10-01
Classification: H04L

Abstract:
In combination for operating upon digital signals provided at a particular frequency, which digital signals have been scrambled and encoded and then converted to analog signals, to recover the information represented by such digital signals,first means for providing clock signals at the particular frequency, second means for converting the analog signals to digital signals at the particular frequency, the digital signals having a pre-cursor response and a post-cursor response, a feed forward equalizer for producing signals inhibiting the pre-cursor response, a decision feedback equalizer for producing signals inhibiting the post-cursor response, an adder for combining the signals from the feed forward equalizer and the decision feedback equalizer to provide resultant signals, a high pass filter for producing signals limiting the time duration or tail of the post-cursor response before the introduction of the digital signals to the feed forward equalizer whereby the high pass filter reduces the length of the tail and accordingly the number of taps associated with the feed forward equalizer, and a tail canceller responding to the digital signal from the feed forward equalizer for producing signals further limiting the time duration of the post-cursor response in the digital signals, whereby the tail canceller reduces the number of taps required in the decision feedback equalizer.