Patent ID: 9118308
Filing Date: 2015-08-25
Classification: H03K

Abstract:
1. A duty cycle corrector, comprising: a VCD (Voltage-Controlled Delay) circuit, receiving an input clock signal, and delaying the input clock signal for a delay period so as to generate a delay clock signal, wherein the delay period is adjusted according to a CP (Charge Pump) control voltage; an edge detector, detecting clock edges of the input clock signal and the delay clock signal so as to correspondingly generate a first clock edge signal and a second clock edge signal; an SR latch, generating a toggling signal according to the first clock edge signal and the second clock edge signal; a mode controller, generating a mode control voltage; and a CP (Charge Pump) circuit, operating in either a first mode or a second mode according to the mode control voltage, and generating the CP control voltage according to the toggling signal and the mode control voltage; wherein the toggling signal is generated as an output signal of the duty cycle corrector.