Patent ID: 6496922
Filing Date: 2002-12-17
Classification: G06F

Abstract:
A system for executing first instructions and second instructions in a computer system including a processor, a memory coupled to said processor and storing a plurality of control modules comprising program instructions for manipulating said first and second instructions, the first and second instructions being configured according to first and second predetermined instruction set architectures (ISA's), respectively, where the first ISA is a native ISA for said processor and the second ISA is a non-native ISA for the processor, the system including:an instruction router coupled to the processor for receiving said first and second instructions; an instruction dispatch unit coupled to said instruction router for receiving said first instructions and said second instructions; at least one dynamic decode unit coupled to said instruction router and to said instruction dispatch unit for receiving said second instructions, configured to translate said second instructions into native instructions before said second instructions are processed by said instruction dispatch unit; an ISA tag coupled to each instruction in said first and second instructions, identifying the corresponding ISA for that instruction; a tag reading control module for reading each said ISA tag of said first and second sets of instructions; a tag identification control module for determining the ISA corresponding to each said ISA tag: a first routing control module for routing at least some said instructions having; an ISA tag corresponding to the processor's native ISA to said instruction dispatch unit; a second routing control module for routing at least some said instructions having an ISA tag corresponding to said predetermined non-native ISA to said dynamic decode unit; a translation control module for translating instructions received at said dynamic decode unit into modified instructions corresponding to said native ISA for said processor; an instruction emulation control module for emulating a second predetermined ISA that is non-native to said processor and for which a corresponding dynamic decode unit is not present in said system; and wherein each dynamic decode unit is configured to execute, as appropriate, the function of converting a complex non-native instruction into a plurality of native ISA instructions.