Patent ID: 9006827
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A method comprising: forming one or more first gate stacks and second gate stacks on a substrate; providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions; and providing a deep implant process for the one or more second gate stacks such that diffusions regions of the one or more second gate stacks are butted junction regions, wherein: the butted junction regions are source/drain (S/D) junctions; the butted junction regions are formed in a well; the non-butted junction regions are source/drain (S/D) junctions which extend partially through an SOI surface layer; and the butted junction regions extend completely through the SOI surface layer, making contact with an underlying oxide layer.