Patent ID: 9059241
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method for packaging a semiconductor device comprising: attaching a first array of solder material to a first surface of an interposer; bringing the first array of solder material into physical contact with a laminate; initially bonding the interposer to the laminate by applying a first temperature and pressure gradient to the first array of solder material by a thermal compression head such that a melting temperature of the first array of solder material is not exceeded; attaching a second array of solder material to a processor chip; bringing the second array of solder material into physical contact with a second surface of said interposer, wherein said second surface has a plurality of interconnect pads; and initially bonding the interposer to the processor chip by applying the first temperature and pressure gradient to the second array of solder material by the thermal compression head such that a melting temperature of the second array of solder material is not exceeded, wherein during said initial bonding steps, temperature of the thermal compression head includes a ramp up rate of greater than 10° C./s after making contact with materials to be bonded and the pressure is ramped down to a critical steady state pressure.