Patent ID: 6275547
Filing Date: 2001-08-14
Classification: H03L,H04L

Abstract:
A clock recovery circuit comprising:(a) a first synchronous delay circuit, to which a reference clock and data are input, for outputting a first clock;(b) an inverter for inverting the data and outputting inverted data;(c) a second synchronous delay circuit, to which the reference clock and inverted data are input, for outputting a second clock;(d) a delay circuit, to which data is input, for outputting delayed data;(e) a pulse combining circuit, to which the first clock and the second clock are input, for combining the first and second clocks and outputting the result as an extracted clock; and(f) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data and outputting the latched data as reproduced data;(g) wherein said first synchronous delay circuit comprises:(g1) a first delay line, to which the reference clock is input, comprising at least one first individual delay circuit;(g2) a first selection circuit array comprising at least one first individual selection circuit, to which the reference clock output by a respective one of the first individual delay circuits is input and which is rendered conductive based upon the data, for generating a first generated reference clock; and(g3) a first NAND gate, to which the data and the first generated reference clock are input, for outputting the first clock; and(h) wherein said second synchronous delay circuit comprises:(h1) a second delay line, to which the reference clock is input, comprising at least one second individual delay circuit;(h2) a second selection circuit array comprising at least one second individual selection circuit, to which the reference clock output by a respective one of the second individual delay circuits is input and which is rendered conductive based upon the inverted data, for generating a second generated reference clock; and(h3) a second NAND gate, to which the inverted data and the second generated reference clock are input, for outputting the second clock.