Patent ID: 7560808
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a plurality of macro-cell devices, each of the macro-cell devices comprising a plurality of LDMOS devices formed over a semiconductor substrate and coupled together to form the macro-cell device, wherein current flows across the macro-cell device through the substrate to a common vertical contact; a first conductive layer formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell devices, one of the source and drain contacts electrically coupled to the common vertical contacts; a first isolation layer formed over the first conductive layer; a second conductive layer formed over the first isolation layer, the second conductive layer forming a plurality of spaced source and drain busses arranged as a plurality of adjacent source and drain bus pairs, each bus pair being electrically coupled to a respective macro-cell device, wherein the drain buses are electrically coupled to the drain contacts through the first isolation layer and the source buses are electrically coupled to the source contacts through the first isolation layer; a second isolation layer formed over the second conductive layer and insulating the source buses from the drain buses; and a plurality of conductive solder bumps formed over the second isolation layer, wherein each pair of busses has a plurality of conductive solder bumps formed thereover with each conductive solder bump overlapping both the source and drain busses of a respective pair of busses so as to allow connection by an individual conductive solder bump to either a source bus or a drain bus of the respective pair of busses through the second isolation layer, wherein the conductive solder bumps formed over the respective pair of busses are alternatingly contacted to the source and drain buses.