Patent ID: 8358539
Filing Date: 2013-01-22
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device comprising: a memory cell array having a plurality of memory strings arranged therein, each of the memory strings including a plurality of electrically rewritable memory transistors, selection transistors operative to select a memory transistor, and a back-gate transistor, each of the plurality of memory strings comprising: wherein the memory transistors included in a first memory string as one of the memory strings connected to a pair of the third conductive layer and the fourth conductive layer are commonly connected to the first conductive layers connected to the memory transistors included in a second memory string as one of the memory strings, the second memory string being connected to the same pair of the third conductive layer and the fourth conductive layer as that of the first memory string, and adjacent to the first memory string, and the back-gate transistor in the first memory string and the back-gate transistor in the second memory string are each connected to independent of the fifth conductive layers.