Patent ID: 6750725
Filing Date: 2004-06-15
Classification: H03D,H03L

Abstract:
A phase locked loop circuit, comprising:an A/D converter for converting signals that are consecutively input into digital signals; a phase error detect unit for detecting a zero crossing of the digital signals and for detecting a timing error from the digital signal corresponding to the zero crossing; and an error correction unit for correcting a sampling timing of the A/D converter corresponding to the timing error, the phase error detecting unit comprising: a zero crossing detect unit for detecting the zero crossing of the digital signals consecutively input from the A/D converter; a switching unit for transmitting the digital signals input from the A/D converter when a zero crossing detect signal is input from the zero crossing detect unit; and an error calculate unit for obtaining and outputting the timing error between an input timing of a present digital signal input from the switching unit and an input timing of a previous digital -signal for the present digital signal.