Patent ID: 8379784
Filing Date: 2013-02-19
Classification: G11C,H03K,H03M

Abstract:
1. A semiconductor memory device, comprising: an output unit for outputting data in synchronization with clock signals; and a data eye control unit for detecting phases of an internal clock and pulse signals corresponding to delay locked clocks as the clock signals, and controlling pulse widths of the clock signals based on the detection result so as to control a data eye of the data output by the output unit, wherein the data eye control unit includes: a delay tuning unit for synchronizing the internal clock with the pulse signals and outputting the synchronized internal clock and the synchronized pulse signals; and a phase detector for detecting phases of the synchronized internal clock and the synchronized pulse signals which are outputted from the delay tuning unit, and outputting a phase detection result to the output unit so as to adjust pulse widths of the pulse signals.