Patent ID: 6717204
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A semiconductor device comprising:a memory region including a split-gate non-volatile memory transistor; a first transistor region including a first voltage-type transistor that operates at a first voltage level; a second transistor region including a second voltage-type transistor that operates at a second voltage level that is different than the first voltage level; and a third transistor region including a third voltage-type transistor that operates at a third voltage level that is different than the second voltage level; wherein the second voltage-type transistor includes a gate insulation layer formed from at least two insulation layers; wherein the non-volatile memory transistor comprises a source, a drain, a gate insulation layer a floating gate, an intermediate insulation layer adapted to function as a tunnel insulation layer, and a control gate, wherein the intermediate insulation layer is formed from at least three insulation layers, wherein a first insulation layer contacts the floating gate and a third insulation layer contacts the control gate; and wherein the third voltage-type transistor has a gate insulation layer formed from at least three insulation layers, wherein the at least three insulation layers of the third voltage-type transistor are identical in composition to the at least three insulation layers of tit intermediate insulation layer of the non-volatile memory transistor.