Patent ID: 9166600
Filing Date: 2015-10-20
Classification: G06F,H01L,H03K

Abstract:
1. A semiconductor device comprising: a pixel comprising an n-channel transistor; and a NOR cell operatively connected to the pixel, the NOR cell comprising: a first input side NOT gate including a first n-channel transistor and a first p-channel transistor; a second input side NOT gate including a second n-channel transistor and a second p-channel transistor; and a NAND gate having a first input terminal electrically connected to the first input side NOT gate and a second input terminal connected to the second input side NOT gate; and an output side NOT gate having an input terminal electrically connected to an output terminal of the NAND gate, the output side NOT gate including a third n-channel transistor and a third p-channel transistor, wherein each of the first p-channel transistor, the second p-channel transistor and the third p-channel transistor comprises a semiconductor layer on an insulating layer, the semiconductor layer comprising a channel region that comprises silicon, and wherein the NOR cell is included in a memory.