Patent ID: 6413808
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A semiconductor device, comprising:a CMOS internal circuit including a first well region and a second well region of different conduction types, the first well region and the second well region being formed on a semiconductor substrate, and a transistor being formed on each of the first well region and the second well region, and a CMOS I/O protective circuit including a third well region and a fourth well region of different conduction types, the third well region and the fourth well region being formed on the semiconductor substrate, and a transistor being formed on each of the third well region and the fourth well region, wherein each of the first well region and the second well region further comprises two regions including a low-impurity-concentration region and a high-impurity-concentration region, the high-impurity-concentration region being formed beneath the low-impurity-concentration region and having the same conduction type as the low-impurity-concentration region, and each of the third well region and the fourth well region comprises a single low-impurity-concentration region having an impurity concentration that is lower than each of the high-impurity concentration regions of the first well region and the second well region.