Patent ID: 6181591
Filing Date: 2001-01-30
Classification: G11C

Abstract:
An associative memory (CAM) cell comprising:a pair of CMOS inverters, an output of one inverter being connected to an input of the other inverter;a pair of first and second NMOS switches, said first switch being situated between the output of one inverter of said pair of CMOS inverters and one bit line of a pair of bit lines, said second switch being situated between the output of the other inverter of said pair of inverters and the other bit line of said pair of bit lines, said first and second switches being turned on or off in response to a signal on a word line connected to each of said first and second switches;a pair of third and fourth NMOS switches, said third switch being situated between one bit line of said pair of bit lines and a bit match node, said fourth switch being situated between the other bit line of said pair of bit lines and said bit match node, said third and fourth switches being turned on or off in response to the signal output from each inverter of said pair of inverters; anda fifth P-type MOS switch connected to a word match line and said bit match node, said fifth switch being turned on or off in accordance with a potential of said bit match node, for discharging said word match line,wherein said fifth PMOS switch is turned on when the potential of said bit match node is low, and said fifth switch is turned off when the potential of said bit match node is high.