Patent ID: 6098165
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A processor that executes instructions comprising complex and non-complex instructions, the processor comprising:an instruction cache for holding a plurality of instructions for processing;a fetch unit for fetching one or more instructions from said instruction cache;an execution unit for executing said instructions;by-passable helper logic for expanding a complex instruction into two or more microinstructions, said helper logic receiving said complex instruction from the fetch unit and passing said two or more microinstructions to the execution unit;control logic for detecting a non-complex instruction and directing said non-complex instruction to said execution unit along a path bypassing said helper logic;said fetch unit fetching instructions in an ordered instruction bundle; andsaid control logic parsing said instruction bundle into one or more sub-bundles comprising a non-complex sub-bundle having only non-complex instructions and a complex sub-bundle having the two or more microinstructions corresponding to a single complex instruction.