Patent ID: 7064043
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method of forming a MOS decoupling capacitor, comprising: patterning a layer of capacitor top electrode material formed over a layer of capacitor dielectric material; patterning the layer of capacitor dielectric material that is formed over a semiconductor substrate; forming a layer of dielectric material over the substrate and patterned layers of capacitor top electrode and dielectric materials; forming vias within the layer of dielectric material down to the patterned layer of capacitor top electrode material and down to the substrate, including forming at least one deep contact via that penetrates into the substrate; filling the vias with a conductive material; forming a first metallization layer over the layer of dielectric material and filled vias; patterning the first metallization layer to form conductive contact pads over the filled vias; aligning the capacitor with an integrated circuit device such that the contact pads of the capacitor are aligned with contact pads of the integrated circuit device; performing an anneal to fuse the contact pads of the capacitor and the contact pads of the integrated circuit device; removing some of the substrate to expose the at least one deep contact via; forming a second metallization layer over the substrate and the at least one deep contact via; and patterning the second metallization layer to form respective bond pads over the at least one deep contact via.