Patent ID: 6555482
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A method for fabricating a MOS transistor comprising:forming a first gate in a surface of a silicon-on-insulator (SOI) substrate by forming isolating regions in the SOI substrate defining an active zone and doping the active zone; epitaxially forming a semiconductor channel region on the surface of the SOI substrate transversely surmounting the first gate; isolating the semiconductor channel region from the first gate by forming a tunnel under the semiconductor channel region and at least partially filling the tunnel with a first dielectric; forming a second dielectric on an upper surface of the semiconductor channel region; forming a second gate on the second dielectric and transverse to the semiconductor channel region so that the second dielectric separates the semiconductor channel region from the second gate; and epitaxially forming a semiconductor drain region and a semiconductor source region on opposing sides of the semiconductor channel region so that the first gate is between the semiconductor drain and source regions.