Patent ID: 6025270
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method of fabrication of a planarized integrated circuit structure having planarized oxide layer portions which comprises:providing said oxide layer on the surface of an integrated circuit structure;applying a patterned mask layer over said oxide layer with mask regions in registry with depressed portions of said oxide layer and with a periodic array of masked and unmasked regions over the raised portions of said oxide layer, with the size and periodicity of said periodic array of masked and unmasked regions being chosen to enhance subsequent chemical/mechanical polish (CMP) removal uniformity;etching exposed portions of said oxide layer through unmasked regions of said patterned mask layer to approximately the same height as the height of said depressed portions of said oxide layer;removing said patterned mask layer; andchemical/mechanical polishing (CMP) the remaining portions of said oxide layer to obtain a planarized oxide layer having uniform thickness and a smooth surface.