Patent ID: 6459113
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, said field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to said active area and a cell plate electrode formed so as to cover part of said active area with a predetermined cell plate pattern through a capacitor dielectric, said cell plate pattern extending in said transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of said active area in which said cell plate electrode is not formed and serves as a gate electrode of said field effect transistor on said active area, said word line pattern being formed through a gate oxide at a predetermined interval, wherein the layout of a cell array of said memory cells is provided by a closest packing cell configuration.