Patent ID: 6882171
Filing Date: 2005-04-19
Classification: G01R,H01L

Abstract:
1. A system for testing a first integrated circuit chip to be packaged along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, wherein the first integrated circuit chip is designed for normal operation and a test mode, the system comprising on the first integrated circuit chip: a first bonding pad for a SET signal; a second bonding pad for a LOAD signal; a third bonding pad for a TEST signal; and a plurality of bonding pads for TDQ signals; wherein the SET, LOAD, and TEST signals are used to transition the first integrated circuit chip from normal operation into the test mode and to enable test codes to be loaded into the first integrated circuit during a programming phase of the test mode; wherein the TDQ signals are used to load test codes into the first integrated circuit during the programming phase and to read/write data to and from the first integrated circuit during an access phase of the test mode.