Patent ID: 8872543
Filing Date: 2014-10-28
Classification: H03K

Abstract:
1. A configurable logic block, comprising: a plurality of memory units, wherein one of the memory units comprises a first bias terminal, a second bias terminal, an output terminal, a first resistive non-volatile memory (RNVM) element and a second RNVM element, wherein a bottom electrode of the first RNVM element and a bottom electrode of the second RNVM element are respectively coupled to the first bias terminal and the second bias terminal of the one of the memory units when a top electrode of the first RNVM element and a top electrode of the second RNVM element are coupled to the output terminal of the one of the memory units; and the top electrode of the first RNVM element and the top electrode of the second RNVM element are respectively coupled to the first bias terminal and the second bias terminal of the one of the memory units when the bottom electrode of the first RNVM element and the bottom electrode of the second RNVM element are coupled to the output terminal of the one of the memory units; and a selecting circuit selecting one of the memory units according to an input logic value of the configurable logic block, and determining an output logic value of the configurable logic block according to a logic value of the output terminal of the selected one of the memory units.