Patent ID: 6466509
Filing Date: 2002-10-15
Classification: G11C

Abstract:
A semiconductor memory device comprising:first and second memory banks each including M memory blocks each divided into first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands each inputting and outputting data to and from one of said first and second memory regions in at least one, adjacent memory block of said M memory blocks, said M memory blocks being each arranged between adjacent two of said (M+1) sense amplifier bands; a first select line activated when said first memory region is selected; and a second select line activated when said second memory region is selected, said first memory bank having odd-numbered ones of said (M+1) sense amplifier bands each coupled with said first select line to input and output said data to and from said first memory region, and even-numbered ones of said (M+1) sense amplifier bands each coupled with said second select line to input and output said data to and from said second memory region, said second memory bank having odd-numbered ones of said (M+1) sense amplifier bands each coupled with said second select line to input and output said data to and from said second memory region, and even-numbered ones of said (M+1) sense amplifier bands each coupled with said first select line to input and output said data to and from said first memory region.