Patent ID: 7643364
Filing Date: 2010-01-05
Classification: G11C

Abstract:
1. A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage at an output and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level, comprising: a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.