Patent ID: 7716608
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. A method for designing a synchronous digital system comprising: using a computer to form a data representation of a synchronous digital system configured to schedule state transition rules for application, if enabled, in a single clocked cycle of the synchronous digital system to achieve a result equivalent to application of the rules in a predetermined order; specifying modules with multiple successive interfaces such that within the single clocked cycle, each module is specified to perform a function equivalent to completing interactions through one of its interfaces before performing interactions through a succeeding one of its interfaces; and wherein using the computer to form the data representation further includes associating the scheduled state transition rules with corresponding interfaces of the modules; and wherein each of the multiple successive interfaces is associated with a corresponding different phase of an ordered set of processing phases of the single clocked cycle, and at least some input to an interface associated with one of the processing phases depends at least in part on an output of an interface associated with a previous processing phase.