Patent ID: 6741519
Filing Date: 2004-05-25
Classification: G11C,H01L,H03K

Abstract:
An electronic system, comprising:a memory; and a processor coupled to the memory and formed on a die common with the memory; and wherein the processor includes at least one programmable logic array including: a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and wherein the non-volatile memory cells each include: a metal oxide semiconductor field effect transistor (MOSFET); a stacked capacitor formed according to a dynamic random access memory (DRAM) process, wherein the stacked capacitor has a coupling ratio greater than 1.0.; and an electrical contact that couples the stacked capacitor to a gate of the MOSFET.