Patent ID: 7515469
Filing Date: 2009-04-07
Classification: G11C

Abstract:
1. A column redundancy system for a non-volatile memory, the system comprising: a separate companion controller chip for controlling operational modes of the non-volatile memory chip, the separate companion controller chip including a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells; column redundancy match logic configured to compare user input addresses for the non-volatile memory to addresses of defective non-volatile memory cells stored in a column redundancy RAM memory array and configured to provide a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell stored in the column redundancy RAM memory array; and column redundancy replacement logic, in response to a match output signal from the column redundancy match logic, configured to dynamically substitute correct data associated with a defective non-volatile memory cell into an I/O data bit stream of a non-volatile memory chip.