Patent ID: 6417556
Filing Date: 2002-07-09
Classification: H01L

Abstract:
An integrated circuit comprising a substrate, a dielectric layer disposed over the substrate, and a conductive layer disposed over the dielectric layer, wherein the conductive layer includes:a first line disposed adjacent to a second line, the first line being separated from the second line by a first spacing; a high k dielectric material disposed in the first spacing between the first line and the second line; a third line separated from the first line by a second spacing, the second spacing being larger than the first spacing; and a first dielectric material disposed in the second spacing, the first dielectric material having a lower dielectric constant than the high k dielectric material, wherein the first line is coupled to receive a first signal and the second line being coupled to receive a capacitor signal, whereby a capacitor is formed between the first line and the second line separated by the high k dielectric material.