Patent ID: 6268250
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method for forming an integrated circuit with at least two types of wells, the method comprising the steps of:providing a first mask with a first opening over a substrate;forming a first well of a first well type in the substrate through the first opening;forming a first oxide layer over the substrate;providing a second mask with a second opening over the substrate;forming a second well of a second well type in the substrate through the second opening;doping the second well through the second opening to adjust a voltage threshold of a device to be formed in the second well to a first value;providing a third mask with third and fourth openings;modifying the thickness of the first oxide layer in areas corresponding to the third and fourth openings;doping areas corresponding to the third and fourth openings to adjust voltage thresholds of devices to be formed in areas corresponding to the third and fourth openings; andforming a first device in the first well, a second device in the second well, and a third device in an area of the substrate corresponding to the fourth opening.