Patent ID: 8158890
Filing Date: 2012-04-17
Classification: H01L,H05K

Abstract:
1. A packaging substrate, comprising: a plurality of layers, wherein layers of said plurality of layers are disposed over each other on opposing sides of a core; a decoupling capacitor disposed on a top surface of a top layer of the packaging substrate; and a first pair of vias and a second pair of vias, each of the first and second pairs including a first via type and a second via type traversing the plurality of layers from the top layer to a power supply plane affixed to the core, wherein the first via type of the first pair is disposed between the second via type of the first pair and the second via type of the second pair, and wherein each via type of the first and second pairs traversing the plurality of layers transition from a first axis of a top portion of the plurality layers to a second axis of a bottom portion of the plurality layers.