Patent ID: 7706191
Filing Date: 2010-04-27
Classification: G11C

Abstract:
1. A method comprising: applying one or more first voltage pulses to one or more first memory cells having a lower page and an upper page, the one or more first voltage pulses inducing a first threshold voltage on the lower page of each of the first memory cells within a first voltage range; applying one or more second voltage pulses to one or more second memory cells having a lower page and an upper page, the one or more second voltage pulses inducing a second threshold voltage on the lower page of each of the second memory cell within a second voltage range; shifting the first and second threshold voltages on the lower page of each memory cell to the upper page of each memory cell, and adjusting the magnitude to within a final range selected from a plurality of upper page voltage ranges; storing for each memory cell a final voltage within a final range representing a binary value; and performing an erase operation on the plurality of memory cells to set the voltages on the memory cells within an erased range on an erased page of the memory cells, wherein the first range is smaller than the erased range.