Patent ID: 7199426
Filing Date: 2007-04-03
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a channel region formed in a semiconductor substrate; a gate electrode formed over the channel region with a charge retaining insulating film formed therebetween; a first pair of source/drain regions formed in the semiconductor substrate and arranged in a first direction with the channel region formed therebetween; a second pair of source/drain regions formed in the semiconductor substrate and arranged in a second direction intersecting the first direction with the channel region formed therebetween, the second pair of source/drain regions having the same conductivity type as the first pair of source/drain regions; and device isolation regions formed of an insulating material and defining a region for the channel region, the first pair of source/drain regions and the second pair of source/drain regions, the channel region and the gate electrode being common between a first memory cell transistor including the first pair of source/drain regions and a second memory cell transistor including the second pair of source/drain regions.