Patent ID: 7514773
Filing Date: 2009-04-07
Classification: H01L

Abstract:
1. A die set interconnection system comprising: a first integrated circuit die to perform as a base memory controller, the first integrated circuit die having a first electrode configuration including a primary input bus connection, a secondary input bus connection, a primary output bus connection and a secondary output bus connection to interconnect with a primary and secondary input bus and a primary and secondary output bus; a second integrated circuit die having the first electrode configuration, including a primary input bus connection, a secondary input bus connection, a primary output bus connection and a secondary output bus connection to interconnect with the primary and secondary input bus and the primary and secondary output bus; and a multilayer flexible cable having a first surface and a second surface and pads on the first surface and the second surface to interconnect the secondary output bus of the first integrated circuit die to the secondary input bus of the second integrated circuit die and to connect the primary output bus of the second integrated circuit die to the primary input bus on the first integrated circuit die.