Patent ID: 7585723
Filing Date: 2009-09-08
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming an insulation structure over a substrate structure including contact plugs; etching the insulation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion; and forming a conductive layer contacting the contact plugs inside the opening regions, wherein etching the bottom electrode isolation structure to form the opening regions comprises: forming an etch barrier layer over the substrate structure; forming the insulation structure including first to third insulation layers over the etch barrier layer, wherein the second insulation layer is interposed between the first insulation layer and the third insulation layer and has an etch selectivity ratio different from those of the first and third insulation layers; etching the third insulation layer to form the upper opening portions each having a widened bottom critical dimension; etching the second insulation layer and the first insulation layer in a self-aligned manner using a patterned third insulation layer as an etch barrier, the patterned third insulation layer including the upper opening portions with the widened bottom critical dimension; and etching the etch barrier layer.