Patent ID: 9170300
Filing Date: 2015-10-27
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising: A. an integrated circuit test data in and test data out lead; B. an integrated circuit test clock lead; C. a first set of domain leads that include a first test data out lead, a first test data in lead, a first test clock lead, and a first test mode select lead; D. a second set of domain leads that include a second test data out lead, a second test data in lead, a second test clock lead, and a second test mode select lead; E. I/O circuitry including: F. instruction circuitry having a data input connected to the data in output of the input buffer and having control outputs; and G. linking circuitry having a linking data input connected to the data in output of the input buffer, a linking data output connected to the data out input of the output buffer, and inputs connected to the control outputs of the instruction circuitry, the linking circuitry including multiplexer circuitry selectively coupling the linking data input with the first test data out lead or the second test data out lead, and selectively coupling the linking data output with the first test data in lead or the second test data in lead.