Patent ID: 7362638
Filing Date: 2008-04-22
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying means coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying means in response to a control signal, wherein each of the first bit line pair and the second bit line pair makes an individual connection with the bit line sense amplifier means through a first interconnection line disposed in an identical layer, and each of the third bit line pair and the fourth bit line pair makes an individual connection with the bit line sense amplifier means through a second interconnection line disposed in a different layer from the first interconnection line.