Patent ID: 6414868
Filing Date: 2002-07-02
Classification: G11C

Abstract:
A memory module comprising:a printed circuit board including a connector edge adapted for insertion in a computer system; a lower bank of memory chips mounted upon said printed circuit board; an upper bank of memory chips mounted upon said printed circuit board; a bank control circuit coupled to said upper and lower banks of memory chips, wherein said bank control circuit is configured to receive a row address strobe (RAS) signal and a column address strobe signal, and at least one address signal, wherein said bank control circuit is configured to selectively provide at least one corresponding RAS output signal to either said upper bank of memory chips or said lower bank of memory chips depending upon said address signal to thereby allow either said lower bank of memory chips or said upper bank of memory chips to be selectively accessed during a given memory operation; wherein said bank control circuit includes a latch having a latch set input, wherein said bank control circuit further includes logic configured to assert a latch set signal that is provided to said latch set input in response to said CAS signal being asserted before said RAS signal, wherein assertion of the latch set signal causes an output of said latch to be set; wherein said bank control circuit is configured to assert said corresponding RAS output signals concurrently to both said upper bank and said lower bank in response to an assertion of said RAS signal while said output of said latch is set; and a line driver chip, wherein said line driver chip is configured to drive electrical signals, and wherein said line driver chip is further configured to duplicate said electrical signals for driving to said upper bank of memory chips and said lower bank of memory chips.