Patent ID: 7642823
Filing Date: 2010-01-05
Classification: G11C,H03L

Abstract:
1. A semiconductor memory device, comprising: a delay-locked-loop updated by a delay-locked-loop update signal; and a delay-locked-loop controller generating the delay-locked-loop update signal having a predetermined period when the delay-locked-loop is in an OFF state responding to any one of a power-down mode, a self-refresh emulation mode, and a self-refresh mode and providing the delay-locked-loop update signal to the delay-locked-loop, wherein the delay-locked-loop controller comprises: an oscillating portion generating an oscillation signal having a predetermined period when the delay-locked-loop is in the OFF state; a pulse generating portion generating a pulse signal having a predetermined period using the oscillation signal; and a dividing portion dividing the pulse signal to generate the delay-locked-loop update signal.