Patent ID: 6570793
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A redundancy circuit for a semiconductor memory having a memory cell matrix with memory cells, word lines and bit lines for selecting the memory cells, the word lines include redundant word lines activated when one of the word lines is defective, the redundancy circuit comprising:an address decoding device for decoding an applied address for a word line and activating the word line associated with the applied address; and a redundancy comparator device for testing the applied address for the word line to determine whether the word line has an address of a defective word line, and, after the applied address has been determined as being the address of the defective word line, said redundancy comparator device activates a respective redundant word line, said redundancy comparator device having an output device connected to said address decoding device and said output device outputting a deactivation signal after the applied address for the word line has been determined as being the address of the defective word line; said address decoding device and said redundancy comparator device are configured such that said address decoding device decodes the applied address for the word line in a chronologically parallel fashion and activates the word line associated with the applied address, and said redundancy comparator device tests the applied address for the word line to determine whether the word line is the defective word line, said address decoding device having a deactivation device for deactivating the word line being an activated defective word line after a reception of the deactivation signal from said redundancy comparator device.