Patent ID: 6781894
Filing Date: 2004-08-24
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged correspondingly to respective rows of said plurality of memory cells and a plurality of pairs of bit lines arranged correspondingly to respective columns of said plurality of memory cells; a sense amplifier provided correspondingly to each of said plurality of pairs of bit lines; and a read gate circuit provide correspondingly to each of said plurality of pairs of bit lines and connected to a pair of read data lines for reading data, said read gate circuit including a first transistor having its gate connected to one bit line of the corresponding pair of bit lines and its source arranged to dynamically change according to activation/inactivation of said sense amplifier and a second transistor having its gate connected to other bit line of said corresponding pair of bit lines and its source arranged to dynamically change according to activation/inactivation of said sense amplifier.