Patent ID: 6385100
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of bit lines; a plurality of word lines; a plurality of memory cells disposed to correspond to said plurality of bit lines and said plurality of word lines; a row address select circuit for designating a predetermined one from said plurality of word lines; a column address decoder for decoding a column address signal, as received for designating a predetermined bit line from said plurality of word lines, to form a select signal of said bit lines; and a column select circuit for selecting a predetermined one from said plurality of bit lines in response to the select signal formed by said column address decoder, wherein said column address decoder includes: a first pre-decoder corresponding to a high-order address; a second pre-decoder corresponding to a low-order address; a shift register for using the output signal of said second pre-decoder as an initial value; and an output circuit for selecting either the output signal of said second pre-decoder or the output signal of said shift register in accordance with an action mode, whereby said select signal is formed by the output signal of said first pre-decoder and the output signal through said output circuit, and wherein said shift register forms a plurality of continuous select signals of said bit lines by its shifting action.