Patent ID: 6078199
Filing Date: 2000-06-20
Classification: H03K

Abstract:
A negatively delayed signal generating circuit for compensating a duty rate of an input signal, comprising:a buffer for delaying an input signal and outputting a delayed input signal;a first delay unit for receiving the delayed input signal and outputting a plurality of first signals;a latch unit for receiving the delayed input signal and the plurality of first signals and outputting a plurality of second signals, wherein each of the second signals is a pair of negative and positive signals;a first logic unit for processing a subset of the second signals, and outputting a plurality of third signals;a second logic unit for logically processing a first subset of the first signals and the third signals, and outputting a plurality of fourth signals;a third logic unit for logically processing a second subset of the first signals and the third signals, and outputting a plurality of fifth signals;a second delay unit for delaying the fourth signals and outputting a plurality of sixth signals;a third delay unit for delaying the fifth signals and outputting a plurality of seventh signals; anda fourth logic unit for logically processing one of the sixth signals and one of the seventh signals, and outputting a negatively delayed signal.