Patent ID: 6211569
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A structure of metal interconnection lines in integrated circuits for improving thermal conductivity of said metal interconnection lines, comprising:a substrate, wherein said integrated circuits formed on said substrate;an interlayer dielectric layer formed on said substrate;a silicon nitride layer formed on said interlayer dielectric layer;at least one first metal plug formed in said interlayer dielectric layer and said silicon nitride layer;a first metal pattern formed on said silicon nitride layer and communicated with said integrated circuits by said at least one first metal plug;a liner oxide layer formed on said first metal pattern and on said silicon nitride layer;an intermetal dielectric layer formed on said liner oxide layer;at least one second metal plug formed in said intermetal dielectric layer and said liner oxide layer;at least one silicon nitride plug formed in said intermetal dielectric layer and said liner oxide layer; anda second metal pattern formed on said intermetal dielectric layer, said at least one silicon nitride plug and said at least one second metal plug, said second metal pattern communicated with said first metal pattern by said at least one second metal plug, wherein said at least one silicon nitride plug being adapted for improving thermal conductivity.