Patent ID: 6579756
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A DRAM processing method comprising:forming DRAM circuitry comprising DRAM array capacitors having a common cell electrode, respective storage node electrodes, and a high k capacitor dielectric region therebetween, at least one of the common cell electrode and the respective storage node electrodes comprising one or more metal oxides; and applying a first voltage to the cell electrode and a different second voltage to the storage node electrodes under conditions effective to cause oxygen vacancies in the capacitor dielectric region to migrate toward one of the cell electrode or the respective storage node electrodes and react with oxygen from the oxide of the one electrode to fill at least a portion of the oxygen vacancies in the high k capacitor dielectric region, one of the first and second voltages being positive relative to ground voltage, the other of the first and second voltages being negative relative to ground voltage.