Patent ID: 6294944
Filing Date: 2001-09-25
Classification: G06F,H03K,H03L

Abstract:
An interface system comprising:a receiving circuit receiving a clock signal and a data signal; anda transmitting circuit providing the clock signal and the data signal, the transmitting circuit including an interface circuit, the interface circuit comprising:a flip-flop provided on an output end of a data line of said transmitting circuit, said flip flop latching data, to be output from the transmitting circuit, on the data line;a phase difference compensation circuit provided directly on an output end of a clock line of said transmitting circuit, for delaying a clock signal being input according to a control signal being input, the delayed clock signal being output from said transmitting circuit; anda phase difference detection circuit for receiving an output signal of said flip-flop and the delayed clock signal of said phase difference compensation circuit, detecting phase difference between the output signal and the delayed clock signal, and outputting said control signal in response to said phase difference.