Patent ID: 7411808
Filing Date: 2008-08-12
Classification: G11C

Abstract:
1. A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, the array of switches consisting of switches that each have a control node and first and second switched nodes between which the flow of current is dependent on the voltage applied to the control node, wherein each row has a word line connected to the control nodes of the switches of that row, each column comprises only one switch from each row, and each column has first, second and third bit lines connectable to one of the switched nodes of each switch of that column to define the stored data, the other of the switched nodes of each switch being connected to a reference voltage, the method comprising: fixing the voltage of the second bit line of the switch while simultaneously reading data from the first and third bit lines, and subsequently: fixing the voltage of the first bit line of the switch while simultaneously reading data from the second and third bit lines.