Patent ID: 8652907
Filing Date: 2014-02-18
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit, the method comprising: depositing a first poly-silicon layer over a first region and a second region, wherein the first region and the second region each have different poly silicon gate structures; depositing, within the second region, an oxide layer over the first poly-silicon layer; depositing a second poly-silicon layer over the first poly-silicon layer and the oxide layer; stripping away a portion of the second poly-silicon layer that lies over the oxide layer such that another portion of the second poly-silicon layer remains after the portion is stripped away; after the stripping, etching the first and the second poly-silicon layer within the first region to provide at least one first poly-silicon gate region; after the stripping, etching the first poly-silicon layer within the second region to provide at least one second poly-silicon gate region; fabricating at least one first poly-silicon figer from the first poly-silicon layer; and fabricating at least one second poly-silicon finger from the second poly-silicon layer, wherein the at least one first and the at least one second poly-silicon fingers are oriented in a substantially orthogonal manner.