Patent ID: 7710804
Filing Date: 2010-05-04
Classification: G11C

Abstract:
1. An auto precharge circuit of a semiconductor memory device, comprising: a plurality of read auto precharge signal generating units, each of which logically combines an internal column access strobe (CAS) command signal, an internal address signal, and a pre auto precharge signal to generate an auto precharge detect signal and a read auto precharge signal; a write auto precharge signal generating unit which delays any one of the read auto precharge signals by a predetermined time to generate a write auto precharge signal; and a plurality of auto precharge signal output units each of which logically combines the respective one of the internal CAS command signal, the internal address signal, the read auto precharge signal, and the write auto precharge signal to output an auto precharge signal, wherein the plurality of read auto precharge signal generating units and auto precharge signal output units share the write auto precharge signal generating unit.