Patent ID: 6493048
Filing Date: 2002-12-10
Classification: G02F,H01L

Abstract:
A thin film transistor array panel for a liquid crystal display, comprising:a gate wire formed on an insulating substrate and including a gate line and a gate electrode connected to the gate line; a gate insulating layer covering the gate wire; a semiconductor layer formed on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer; a data wire including a data line intersecting the gate line, a source electrode connected to the data line and extending to the gate electrode, and a drain electrode located opposite to the source electrode with respect to the gate electrode, the data wire being formed on the ohmic contact layer and having the same layout as the ohmic contact layer; a protection layer formed on the data wire and the semiconductor layer, and having a first contact hole exposing the drain electrode; and a pixel electrode connected to the drain electrode through the first contact hole, wherein a portion of the semiconductor layer on the gate line between adjacent data lines is divided, and wherein peripheries of the gate insulating layer, the semiconductor layer, and the protection layer are substantially in an identical shape.