Patent ID: 6650334
Filing Date: 2003-11-18
Classification: G06T

Abstract:
A circuit for tag checking comprising:a first comparison gate operable to compare only a v field of a tag with a v-odd dimension element for a group of texels associated with a sample point, the first comparison gate operable to output a first match signal if the v field matches the v-odd dimension element; a second comparison gate operable to compare only the v field of the tag with a v-even dimension element for the group of texels associated with the sample point, the second comparison gate operable to output a second match signal if the v field matches the v-even dimension element; a third comparison gate operable to compare only a u field of the tag with a u-odd dimension element for the group of texels associated with the sample point, the third comparison gate operable to output a third match signal if the u field matches the u-odd dimension element; and a fourth comparison gate operable to compare only the u field of the tag with a u-even dimension element for the group of texels associated with the sample point, the fourth comparison gate operable to output a fourth match signal if the u field matches the u-even dimension element.