Patent ID: 8084869
Filing Date: 2011-12-27
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a wiring substrate having a first main surface, a plurality of first terminals formed in a chip mounting area over the first main surface, a first back surface positioned on the side opposite to the first main surface, and a plurality of lands formed over the first back surface; and a semiconductor chip having a second main surface, a plurality of first electrodes formed over the second main surface, and a plurality of salient electrodes formed over the first electrodes, the semiconductor chip being mounted over the first main surface of the wiring substrate through the salient electrodes such that the second main surface confronts the first main surface of the wiring substrate, wherein the first terminals have a first terminal group comprising the first terminals arrayed in a row, a second terminal group comprising the first terminals arrayed in a row, the second terminal group being disposed at a more inside position of the chip mounting area than the first terminal group, and a third terminal group comprising the first terminals and disposed at a more inside position of the chip mounting area than the second terminal group, wherein the first terminals of the first terminal group correspond to first-row terminals, the first terminals of the second terminal group correspond to second-row terminals, and the first terminals of the third terminal group correspond to third-row terminals, wherein the second-row terminals in the second terminal group are each positioned between the first-row terminals adjacent each other in the first terminal group, wherein the third-row terminals in the third terminal group are each positioned between the second-row terminals adjacent each other in the second terminal group, and wherein the distance between the first terminal group and the second terminal group is larger than the distance between the second terminal group and the third terminal group.