Patent ID: 6218879
Filing Date: 2001-04-17
Classification: H03K

Abstract:
An S-R flip-flop circuit comprising:(i) a first signal input for receiving a first input signal having a signal value of either A or B;(ii) a second signal input for receiving a second input signal having a signal value of either C or D;(iii) an output signal node bearing an output signal having a signal value of either E or F;(iv) an internal node bearing an internal signal having a signal value of either G or H;(v) a first stack of gates responsive to said output signal and said first input signal; and(vi) a second stack of gates responsive to said internal signal, said first input signal and said second input signal, said internal node being between said first stack of gates and said second stack of gates; wherein(vii) said first stack of gates forces said internal signal to G when said first input signal is A and said output signal is E and said first stack of gates forces said internal signal to H when said first input signal is B and said output signal is F;(viii) said second stack of gates forces said output signal to F when said internal signal is G and said first input signal is B, whereby(ix) when said output signal is E and said first input signal is A, said internal signal will be G and a transition in said first signal from A to B will force said output signal to transition from E to F followed by said internal signal being forced to transition from G to H, thereby effecting an edge-triggered change in said output signal from E to F in response to said first input signal changing from A to B.