Patent ID: 6643170
Filing Date: 2003-11-04
Classification: G11C,H01L

Abstract:
A memory cell of a multi-level nitride read-only memory (NROM), wherein a nitride layer is formed and the nitride layer traps a plurality of electrical charges locally to form a plurality of charge-trapping regions, wherein the charge-trapping regions store electrical charges as bits of memory, the memory cell of the multi-level NROM comprises:a first bit, wherein the first bit requires a threshold electrical current for reading the first bit; and a second bit, wherein the charges stored for the second bit form an electrical barrier, and the threshold electrical current for reading the first bit is affected by the electrical barrier, wherein a various size of the electrical barrier determines a various levels of the threshold electrical current, and each level of the threshold electrical current defines a different memory state of the memory cell of the multi-level NROM.