Patent ID: 8982646
Filing Date: 2015-03-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array; a data bus which is divided into a plurality of stages; a transfer controller which serially transfers data such that the data are respectively allocated to the plurality of stages; a plurality of column blocks which temporarily stores the data; and a column selector which selects a column block for each of the plurality of stages from the plurality of column blocks, and transfers the data parallel between the plurality of stages and the column blocks selected for the plurality of stages, wherein the data bus extends from one end to the other in a direction in which the plurality of column blocks are arranged, and returns from the other end to the one end, in a write operation, a plurality of write data are serially transferred by the data bus, and transmitted parallel from the plurality of stages to the plurality of selected column blocks, and in a read operation, a plurality of readout data are transferred parallel from the plurality of selected column blocks to the plurality of stages, and serially transferred by the data bus.