Patent ID: 6486033
Filing Date: 2002-11-26
Classification: H01L

Abstract:
A method for fabricating an integrated circuit device having logic and memory cells on a single semiconductor substrate comprising:forming isolation regions in and on said semiconductor substrate separating active areas wherein said active areas comprise at least one logic area and at least one memory area; forming gate electrode stacks in said active areas wherein said gate electrode stacks comprise a polysilicon layer, a silicide layer, a first oxide layer, and a first nitride layer; covering said semiconductor substrate and said gate electrode stacks with a first mask layer; exposing said first mask in said logic areas to a low energy exposure wherein said first mask layer is partially removed in said logic areas to expose said first nitride layer; removing said exposed first nitride layer to expose said first oxide layer in said logic areas; removing said first mask layer in both said logic areas and said memory areas; forming lightly doped regions; forming nitride spacers on said gate electrode stacks in said logic areas; forming source/drain regions in said logic areas; depositing a second nitride layer overlying said logic areas and said memory areas; forming a second oxide layer overlying said second nitride layer; forming memory devices in said memory areas; simultaneously etching contact openings through said second oxide layer in both said logic areas and said memory areas; and filling said contact openings with a metal layer to complete fabrication of said integrated circuit device having logic and memory cells on a single semiconductor substrate.