Patent ID: 6788484
Filing Date: 2004-09-07
Classification: G11B,H03L

Abstract:
A PLL circuit for generating a clock signal from an input analog signal, comprising:an A/D converter for sampling the input analog signal to produce a digital signal; a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive sample values successively outputted from said A/D converter and outputting pattern string identification information which indicates an identification result; a phase difference generator for outputting phase difference information which indicates a phase error of the output of said A/D converter based on the pattern string identification information and the output of said A/D converter; and a clock signal generator for generating a clock signal from the phase difference information to control the sampling timing of said A/D converter, wherein said A/D converter, said pattern string detector, said phase difference generator, and said clock signal generator are connected in a loop.