Patent ID: 6405273
Filing Date: 2002-06-11
Classification: G06F

Abstract:
Data processing unit comprising a first and a second register file having a plurality of registers, a first and second memory each having a plurality of n-bit input/output ports, a first bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each port of said first memory selectively with one of said sub-busses, second couplers for coupling said first register file with said first bus, a second bus having a bus width of at least 2n-bits forming at least a third and fourth sub-bus, third couplers for coupling each port of said second memory selectively with one of said sub-busses, fourth couplers for coupling said second register file with said second bus, and a bus-coupler for coupling said first and second bus.