Patent ID: 8254453
Filing Date: 2012-08-28
Classification: H04N

Abstract:
1. A multi-format video decoder, comprising: a bitstream buffer, for providing a video bitstream; a system controller, coupled to the bitstream buffer, for selectively generating a first control signal or a second control signal according to an information of the video bitstream; a bitstream decoding unit, coupled to the system controller and the bitstream buffer, for generating a decoding information signal according to the information of the video bitstream when receiving the first control signal; an intra mode decoding unit, coupled to the system controller, for generating an intra mode signal when receiving the second control signal; and a shared prediction module, coupled to the bitstream decoding unit and the intra mode decoding unit, for performing an AC/DC prediction operation upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal, and for performing an intra prediction operation upon the current block to generate a current second prediction result according to the intra mode signal, wherein the shared prediction module includes at least one shared component which is utilized in each of the AC/DC prediction operation and the intra prediction operation; wherein the shared prediction module comprises a prediction unit, and the prediction unit comprises: a first multiplexer, arranged for selectively outputting at least one of a horizontal data, a vertical data, and a diagonal data, and accordingly generating a first multiplexer output; a first operating unit, coupled to the first multiplexer, for generating a first operating result according to the first multiplexer output; a second operating unit, coupled to the first multiplexer, for generating a second operating result according to the first multiplexer output; an adder unit, coupled to the first operating unit and the second operating unit, for summing up the first operating result and the second operating result to generate a summing result; a shifter, coupled to the adder unit, for shifting the summing result to generate a first shifted result and a second shifted result; a second multiplexer, coupled to the first multiplexer, the first operating unit, and the shifter, for selectively outputting the first multiplexer output, the first operating result, or the first shifted result; and a third multiplexer, coupled to the first multiplexer, the second operating unit, and the shifter, for selectively outputting the first multiplexer output, the second operating result, or the second shifted result.