Patent ID: 6043668
Filing Date: 2000-03-28
Classification: G01R

Abstract:
A planarity verification system for proper positioning of testing probes used to analyze integrated circuits on a wafer, the system comprising:a plurality of electrical leads, each lead configured for connection to a testing probe;a light device electrically coupled to each of said leads and operable for being illuminated and providing an indication when an electric current flows therethrough;a power source for providing electric current between opposing terminals thereof, one of said terminals being electrically coupled to said leads through the indicators and the other of said terminals being electrically coupleable to a wafer to be analyzed for biasing the wafer;each electrical lead forming part of a completed current path between said power source terminals when a testing probe connected to said lead contacts a biased wafer being analyzed, the lead directing current along said current path and through an associated indicator to provide an indication;whereby the contact of a testing probe with a wafer is indicated for determining the position of the probes with respect to the wafer.