Patent ID: 9104556
Filing Date: 2015-08-11
Classification: G06F,G11C

Abstract:
1. A method of operating a three-dimensional block-erasable nonvolatile memory formed in a plurality of physical levels of memory cells disposed above a substrate comprising: maintaining a plurality of Single Level Cell (SLC) erase blocks to receive nonsequential data updates of host data; maintaining a plurality of Multi Level Cell (MLC) erase blocks as update blocks that are available to store newly-received sequential data updates of host data for particular host logical address ranges; programming newly-received sequential host data to word lines of an individual update block in a first order in which lower page programming of all of the word lines of the individual update block precedes upper page programming of any of the word lines of the individual update block; writing first sequential data entirely in lower pages of a first update block when the first sequential data is received for a first host logical address range associated with the first update block; subsequently, closing the first update block to newly-received host data and opening a second update block when second sequential data is received for a second host logical address range that overlaps the first host logical address range; writing the second sequential data to the second update block; subsequently copying additional data from elsewhere in the memory array to the closed first update block; and wherein the additional data from elsewhere in the memory array is written to previously unwritten word lines of the closed first update block in a second order in which lower page programming and upper page programming are performed together for a given word line.