Patent ID: 9097953
Filing Date: 2015-08-04
Classification: G02F,H01L

Abstract:
1. A semiconductor device comprising: a source line over a substrate; a gate line over the substrate extending across the source line; and first and second transistors, wherein a source or drain of the first transistor is electrically connected to the source line, wherein the gate line overlaps with a channel region of the first transistor and a channel region of the second transistor, wherein the first and second transistors are electrically connected in series, wherein a portion of the source line overlaps with at least the channel region of the first transistor, wherein a width of a first portion of the gate line is larger than a width of a second portion of the gate line, wherein the first portion of the gate line and the second portion of the gate line are aligned in a first line, wherein the channel region of the first transistor and the channel region of the second transistor are aligned in a second line, and wherein the first line and the second line are parallel and overlap each other.