Patent ID: 8218776
Filing Date: 2012-07-10
Classification: H04R

Abstract:
1. A surge protection circuit, comprising: a signal acquiring circuit to acquire and amplify signals of a left channel (LC) signal line and a right channel (RC) signal line; an electric charge accumulation circuit comprising a first capacitor configured to accumulate electric charge of the amplified signals; a time delay circuit comprising a second capacitor structured and arranged such that, the time delay circuit is triggered by the electric charge of the first capacitor and the second capacitor is charged by a positive voltage; a Schmitt trigger circuit to output a negative voltage or a positive voltage according to the electric charge of the second capacitor; a negation circuit to reverse the negative voltage and the positive voltage output from the Schmitt trigger circuit; and a mute circuit comprising a first input terminal coupled to the Schmitt trigger circuit, a second input terminal coupled to the negation circuit, a first output terminal coupled to the LC signal line, and a second output terminal coupled to the RC signal line; wherein, when the Schmitt trigger circuit outputs a negative voltage and the negation circuit outputs a positive voltage, the LC signal line and RC signal line are in a non-conducting state; when the Schmitt trigger circuit outputs a positive voltage and the negation circuit outputs a negative voltage, the LC signal line and RC signal line are in a conducting state; wherein the signal acquiring circuit comprises: a first amplifier comprising a positive input terminal coupled to the LC signal line, a negative input terminal, and an output terminal coupled to the negative input terminal; a second amplifier comprising a positive input terminal that is grounded, a negative input terminal coupled to the LC signal line via a first resistor, and an output terminal coupled to the negative input terminal via a second resistor; a third amplifier comprising a positive input terminal coupled to the RC signal line, a negative input terminal, and an output terminal coupled to the negative input terminal; and a fourth amplifier comprising a positive input terminal that is grounded, a negative input terminal coupled to the RC signal line via a third resistor, and an output terminal coupled to the negative input terminal via a fourth resistor; wherein the electric charge accumulation circuit further comprises: a first diode comprising an anode coupled to the output of the first amplifier and a cathode; a second diode comprising an anode coupled to the output of the second amplifier and a cathode coupled to the cathode of the first diode; a third diode comprising an anode coupled to the output terminal of the third amplifier and a cathode; a fourth diode comprising an anode coupled to the output terminal of the fourth amplifier and a cathode coupled to the cathode of the third diode; a fifth resistor comprising a first terminal coupled to the cathodes of the first, second, third, and fourth diodes and a second terminal; the first capacitor comprising a first terminal coupled to the second terminal of the fifth resistor and a second terminal that is grounded; wherein the time delay circuit further comprises: a first MOSFET being an n-channel metal oxide semiconductor (NMOS) transistor that comprises a drain connected to a positive voltage, a source, and a gate coupled to the second terminal of the fifth resistor; a second capacitor comprising a first terminal coupled to the source via a sixth resistor and a second terminal that is grounded; wherein the Schmitt trigger circuit comprises: a fifth amplifier comprising a positive input terminal coupled to the first terminal of the second capacitor, a negative input terminal, and an output terminal coupled to the positive input terminal via a ninth resistor; a seventh resistor comprising a first terminal coupled to the negative input terminal of the fifth amplifier and a second terminal connected to a positive voltage; a eighth resistor comprising a first terminal coupled to the negative input terminal of the fifth amplifier and a second terminal that is grounded; a tenth resistor comprising a first terminal coupled to the output terminal of the fifth amplifier and a second terminal connected to a positive voltage.