Patent ID: 7018873
Filing Date: 2006-03-28
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising the steps of: providing a structure comprising a carrier wafer, an oxide layer positioned on the carrier wafer, a polySi back-gate located on the oxide layer, a back-gate dielectric located on said polySi back-gate, and a Si-containing layer located on said back-gate dielectric; forming a channel region into a portion of said Si-containing layer; forming a front gate region comprising a front-gate dielectric, a front polySi gate and sacrificial spacers atop said channel region; forming undercutting shallow trench isolation regions in said structure, wherein during said forming of said undercutting shallow trench isolation regions the back-gate is etched to a length which is less than a length of the overlying Si-containing layer, yet aligned to a lateral edge of said front polySi gate; removing the sacrificial spacers and forming source/drain extensions into the channel region; and forming gate spacers atop the top of the channel region and source/drain regions in said channel region, wherein said polySi back-gate is self-aligned with the front polySi gate and the source/drain extensions.