Patent ID: 6580130
Filing Date: 2003-06-17
Classification: H01L

Abstract:
An integrated static random access memory device comprising:a semiconductor substrate; at least one memory cell comprising four transistors in said semiconductor substrate; a local interconnect layer providing connections for said at least one memory cell, said local interconnect layer forming a base metal layer above said semiconductor substrate; a first metal layer above said local interconnect layer; and said at least one memory cell further comprising two resistors extending in contact with respective first and second portions of said local interconnect layer between the base metal layer and said first metal layer, each resistor comprising an electrically conductive layer having first and second ends resting on the respective first and second portions of said local interconnect layer, a first dielectric layer between the first end of said electrically conductive layer and the first portion of said local interconnect layer, and a second dielectric layer between the second end of said electrically conductive layer and the second portion of said local interconnect layer.