Patent ID: 6359825
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A dynamic memory having a memory array that includes a plurality of memory blocks that have a plurality of memory cells, each one of the plurality of memory blocks including a plurality of first sense amplifier circuits directly connected to bit lines, and a second sense amplifier directly connected to a data input/output circuit shared by the first sense amplifiers of each of the memory blocks, at least a switching circuit connected between the first sense amplifier circuits and the second sense amplifier circuit, and a control means for controlling the switching circuit to separate the first sense amplifier circuits and the second sense amplifier circuit from each other after data is read out from a selected individual one memory cell of the plurality of memory cells, so that the read-out data is amplified by tho second sense amplifier circuit and outputted from the second sense amplifier circuit to a common external connection or the dynamic memory.