Patent ID: 9015023
Filing Date: 2015-04-21
Classification: G06F

Abstract:
1. A method for processing a circuit design, comprising: inputting delay-voltage data that describes a plurality of delay values, the delay values corresponding to operating voltage values of a target device; determining a delay scaling factor corresponding to a default gate-level delay of a target device and a maximum gate level delay at which the circuit design operates correctly; determining a voltage scaling factor corresponding to the delay scaling factor; synthesizing the circuit design, wherein the synthesized circuit design includes the voltage scaling factor, and the synthesized circuit design when implemented on the target device is configured and arranged to set an operating voltage to a value equal to a startup voltage value multiplied by the voltage scaling factor and cause the target device to exhibit the maximum gate-level delay for the circuit design, wherein the startup voltage value is stored in the target device; configuring a first target device and a second target device to implement the synthesized circuit design; and wherein: when configured to implement the synthesized design, the first and second target devices each operate at respective voltages equal to the respective first and second startup voltage values multiplied by the voltage scaling factor, causing the first and second target devices to each exhibit the maximum gate-level delay for the circuit design.