Patent ID: 8797785
Filing Date: 2014-08-05
Classification: G11C

Abstract:
1. A semiconductor device comprising: a first memory cell comprising a first switching element and a first capacitor; a second memory cell comprising a second switching element and a second capacitor; a first word line; a second word line; a first bit line; and a second bit line, wherein the first switching element is configured to control an electrical connection between the first bit line and a first electrode of the first capacitor in accordance with a potential applied to the first word line, wherein the second switching element is configured to control an electrical connection between the second bit line and a first electrode of the second capacitor in accordance with a potential applied to the second word line, wherein a second electrode of the second capacitor is electrically connected to the first word line, wherein the first memory cell and the second memory cell are stacked, and wherein the second memory cell is over the first memory cell.