Patent ID: 7180154
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. An integrated circuit device comprising: an integrated circuit substrate; first through fourth spaced apart lower interconnects on the integrated circuit substrate, the third and fourth spaced apart lower interconnects being parallel to the first and second lower interconnects; a first fuse on the first and second lower interconnects, the first fuse being between the first and second lower interconnects and electrically coupled to the first and second lower interconnects; a second fuse, spaced apart from the first fuse, on the third and fourth lower interconnects, the second fuse being between the third and fourth lower interconnects and electrically coupled to the third and fourth lower interconnects; and first, second and third intermediate interconnects on the integrated circuit substrate having surfaces that are substantially planar with surfaces of the first and second fuses, wherein the first intermediate interconnect is on the first lower interconnect and electrically coupled to the first lower interconnect, wherein the second intermediate interconnect is on the second and fourth lower interconnects and is electrically coupled to the second and fourth lower interconnects and wherein the third intermediate interconnect is on the third lower interconnect and is electrically coupled to the third lower interconnect.