Patent ID: 8101998
Filing Date: 2012-01-24
Classification: H01L

Abstract:
1. A MOSFET comprising: a semiconductor layer; a gate electrode formed over the semiconductor layer; a gate oxide film interposed between the semiconductor layer and the gate electrode; source and drain regions located in the semiconductor layer and spaced apart to define a channel region therebetween in the semiconductor layer below the gate oxide film, the source and drain regions each having a conductivity type which is different from a conductivity type of the channel region in the semiconductor layer; a first extension region which extends at an upper surface region of the semiconductor layer into the channel region from the source region, the first extension region having a same conductivity type and a lower impurity concentration than the source region; a second extension region which extends at an upper surface region of the semiconductor layer into the channel region from the drain region, the second extension region having a same conductivity type and a lower impurity concentration than the drain region; and an interposition layer interposed between the channel region and the source and first extension regions, and extending from an upper surface to a lower surface of the semiconductor layer, the interposition layer having a conductivity type which is different from the conductivity type of the source region, wherein the MOSFET is devoid of another interposition layer between the channel region and the drain and second extension regions.