Patent ID: 7281121
Filing Date: 2007-10-09
Classification: G06F

Abstract:
1. A pipeline processing device that sequentially executes, per set processing timing, plural stages including at least instruction decode, execution and memory access to thereby process in parallel plural instruction processing cycles that respectively process one instruction, so that mutually different stages are concurrently executed, the pipeline processing device comprising: a first multiplexer that selectively supplies one of output from a computing unit or data loaded from an external memory via a data bus to a buffer and a second multiplexer, wherein at the memory access stage executed after reception of an interrupt request, the first multiplexer replaces output data of an execution stage that is simultaneously executed in parallel at a timing of the memory access stage with a header address of an interrupt processing routine to be executed in response to the interrupt request, the header address being loaded from a memory for use as an input data for the memory access stage executed in a next processing timing.