Patent ID: 6380043
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method for fabricating a field effect transistor within an active device area of a semiconductor substrate, the method including the steps of:A. forming a gate structure on a gate dielectric on said active device area of said semiconductor substrate, wherein said gate dielectric has a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2); B. implanting an amorphization dopant and an extension dopant into exposed regions of said active device area of said semiconductor substrate; C. forming a first spacer at a first sidewall of said gate structure and said gate dielectric, and forming a second spacer at a second sidewall of said gate structure and said gate dielectric; wherein said first spacer is disposed over a drain extension junction extending down to an extension depth within said active device area of said semiconductor substrate and having said amorphization dopant and said extension dopant implanted therein; and wherein said second spacer is disposed over a source extension junction extending down to said extension depth within said active device area of said semiconductor substrate and having said amorphization dopant and said extension dopant implanted therein; D. etching down any exposed regions of said active device area of said semiconductor substrate beyond said extension depth; wherein said drain extension junction remains disposed under said first spacer; and wherein said source extension junction remains disposed under said second spacer; E. depositing a layer of amorphous semiconductor material to cover said first and second spacers and said gate structure and on any exposed regions of said semiconductor substrate; wherein said layer of amorphous semiconductor material is formed to be doped with a contact dopant in an in-situ deposition process using a temperature of less than about 500Â° Celsius; F. polishing down said amorphous semiconductor material until top surfaces of said gate structure and said first and second spacers are exposed such that said top surfaces of said gate structure and said first and second spacers are level with a top surface of said amorphous semiconductor material; wherein said amorphous semiconductor material remaining to said first sidewall of said gate structure forms an elevated drain contact structure; and wherein said amorphous semiconductor material remaining to said second sidewall of said gate structure forms an elevated source contact structure; and G. performing a thermal anneal using a temperature less than about 600Â° Celsius to activate said extension dopant within said drain and source extension junctions and to activate said contact dopant within said drain and source contact structures.