Patent ID: 6458708
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method for forming metal wiring in a semiconductor device, comprising:forming a first insulating structure comprising plural layers on a semiconductor substrate; etching the first insulating film to form a first contact hole; forming a first plug in the first contact hole, and removing at least a portion of one of the plural layers of the first insulating structure for planarizing the surface of the first plug and a remaining portion of the first insulating structure; forming a first wiring layer on at least a portion of the remaining portion of the first insulating structure on and around the first plug; forming a second insulating structure comprising plural layers on the first wiring layer and the first insulating structure; etching the second insulating structure for forming a second contact hole which exposes the first wiring layer; forming a second plug in the second contact hole and removing a portion of the second insulating structure, for planarizing the second plug and a remaining portion of the second insulating structure; and, forming a second wiring layer on the second plug.