Patent ID: 8153477
Filing Date: 2012-04-10
Classification: H01L,H05K

Abstract:
1. A method of making a semiconductor chip assembly, comprising: providing a first post, a second post, a first adhesive, a second adhesive, a first conductive layer, a second conductive layer and a dielectric base, wherein flowing the first adhesive in the first vertical direction into a first gap located in the first aperture between the first post and the first conductive layer; flowing the second adhesive in the second vertical direction into a second gap located in the second aperture between the second post and the second conductive layer; solidifying the adhesives, thereby mechanically attaching the first conductive layer to the first post and the dielectric base using the first adhesive and mechanically attaching the second conductive layer to the second post and the dielectric base using the second adhesive; then providing a conductive trace that includes a pad, a terminal and an electrical interconnect, wherein the pad extends vertically beyond the dielectric base in the first vertical direction and includes a selected portion of the first conductive layer, the terminal extends vertically beyond the dielectric base in the second vertical direction and includes a selected portion of the second conductive layer and the electrical interconnect extends through the dielectric base and the adhesives in an electrically conductive path between the pad and the terminal; providing a heat spreader that includes the posts and the dielectric base; then mounting a semiconductor device on the first post, wherein the semiconductor device extends vertically beyond the first post in the first vertical direction and extends laterally within peripheries of the posts and the posts are electrically isolated from one another; electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and thermally connecting the semiconductor device to the first post, thereby thermally connecting the semiconductor device to the second post.