Patent ID: 8975760
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a wiring substrate having a main surface, the wiring substrate including a plurality of first connection pads and a plurality of second connection pads which are formed on the main surface; a first semiconductor chip mounted over the main surface of the wiring substrate, the first semiconductor chip including a plurality of first electrode pads; a second semiconductor chip mounted over the main surface of the wiring substrate, the second semiconductor chip including a plurality of second electrode pads each of which has a size smaller than that of each of the plurality of first electrode pads; a plurality of first wires connecting the plurality of first electrode pads with the plurality of first connection pads, respectively, each of the plurality of first connection pads being connected to only one of the plurality of first wires; and a plurality of second wires connecting the plurality of second electrode pads with the plurality of second connection pads, respectively, the plurality of second wires having wide width parts at first ends thereof, each of the plurality of second connection pads being connected to only one of the plurality of second wires, wherein each of the plurality of first electrode pads is larger than each of the wide width parts of the plurality of second wires and each of the plurality of second electrode pads is smaller than each of the wide width part of the plurality of second wires, wherein the wide width parts of the plurality of second wires are connected to the plurality of second connection pads, respectively, and the plurality of second wires have second ends connected to the plurality of second electrode pads, respectively, via a plurality of bump electrodes which are smaller than the plurality of second electrode pads.