Patent ID: 6432827
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method to improve the planarization of an inter layer dielectric (ILD), the method comprising:providing a semiconductor wafer having both a memory array area and a periphery circuit region defined on the surface of the semiconductor wafer, a plurality of metal oxide semiconductor (MOS) transistors being installed in the periphery circuit region, and a plurality of metal oxide semiconductor (MOS) transistors and capacitors being installed in the memory array area; forming a dielectric layer on the surface of the semiconductor wafer that covers the metal oxide semiconductor (MOS) transistors and capacitors: forming a photoresist layer on the surface of the dielectric layer; performing a photolithographic process that uses the layout patterns of each of the capacitors as a reverse mask so as to remove the portions of the photoresist layer that are in the memory array area; using the residual photoresist layer as a hard mask to etch a portion of the dielectric layer in the memory array area; and performing a planarization process on the dielectric layer.