Patent ID: 6473529
Filing Date: 2002-10-29
Classification: G06F

Abstract:
A Sum-of-Absolute-Difference (SAD) calculator comprising:a plurality of k pixel-pair inputs, each pixel-pair input including a first pixel input receiving a first pixel from a first macroblock and a second pixel input receiving a second pixel from a second macroblock; a plurality of k subtractors, each subtractor generating a difference by subtracting a numeric value of the second pixel from a numeric value of the first pixel; a plurality of k inverter banks, each inverter bank coupled to the difference from one of the k subtractors, for generating bit-inverted differences; a plurality of k muxes, each mux receiving a difference from one of the k subtractors and receiving a bit-inverted difference from an inverter bank that receives the difference; a sign bit for each difference generated by each subtractor, the sign bit indicating when a difference represents positive or a negative value; each mux in the plurality of muxes being controlled by a sign bit for the difference input to the mux, each mux outputting the difference when the sign bit indicates that the difference represents a positive value, but each mux outputting the bit-inverted difference when the sign bit indicates that the difference represents a negative value; a plurality of kâˆ’2 summing adders, each summing adder having 2 multi-bit inputs and a single-bit carry input; wherein a first level of the summing adders receive outputs from the plurality of muxes, the plurality of summing adders outputting a first partial sum and a second partial sum; wherein each of the kâˆ’2 summing adders receives as the single-bit carry input a sign bit for a different one of the differences, wherein the kâˆ’2 summing adders compensate for bit-wise inversion rather than 2's complementing of all but 2 of the differences; a half-adder array, receiving the first and second partial sums from the plurality kâˆ’2 summing adders, for generating a sum and a carry bit for each bit position by adding each bit position of the first partial sum to a same bit position of the second partial sum, the half-adder array outputting all sum bits as a sums output and all carry bits as a carries output; and a final adder, having 2 multi-bit inputs and a single-bit carry input, receiving the sums output and the carries output from the half-adder array, the final adder receiving at the single-bit carry input the sign bit for a difference generated by one of the k subtractors, the final adder for summing the sum and carry bits output by the half-adder array with the sign bit and for propagating carries to generate a SAD value, the SAD value being a sum of absolute-values of the differences generated by the k subtractors, whereby the kâˆ’2 summing adders compensate for bit-wise inversion rather than 2's complementing of all but 2 of the differences, while the final adder and the half-adder array compensate for a remaining 2 of the differences.