Patent ID: 6674133
Filing Date: 2004-01-06
Classification: G11C,H01L

Abstract:
A twin bit cell flash memory device, the device comprising:a semiconductor substrate; a source and a drain positioned in a predetermined area of the semiconductor substrate, and the drain and the source separated by a predetermined distance; a channel positioned on the surface of the semiconductor substrate between the source and the drain; a first dielectric layer covering the surface of the channel; a polysilicon germanium layer covering the surface of the first dielectric layer, the polysilicon germanium layer having an insulating region for separating the polysilicon germanium layer and forming two isolated conductive regions so as to form a twin bit cell structure; a second dielectric layer covering the surface of the polysilicon germanium layer; and a gate covering the surface of the second dielectric layer; wherein each conductive region serves as a charge trapping layer so as to receive and store electrons injected into the conductive region to generate a respective bit.