Patent ID: 9123575
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of first level contacts arranged in an array with every third row vacant along a first direction, thereby forming multiple contact regions separated by multiple vacant regions along said first direction with each of said multiple contact regions comprising a first row and a second row of said first level contacts extending along a second direction substantially perpendicular to said first direction; a first and second plurality of second level contacts formed on top of said first level contacts and coupled thereto, said second plurality of second level contacts having elongated shape extending into said vacant regions adjacent thereto along said first direction; and a first and second plurality of memory elements formed on top of said first and second plurality of second level contacts, respectively, wherein said first and second plurality of memory elements are arranged to have greater center-to-center spacing between two closest neighbors than said first level contacts.