Patent ID: 6288584
Filing Date: 2001-09-11
Classification: H03K

Abstract:
A power-on-reset circuit comprising:a capacitive-pullup divider, outputting a sensing voltage on a sensing node, the capacitive-pullup divider having a pullup capacitor between the sensing node and a power supply, and a transistor pulldown from the sensing node to a ground;a charging transistor, having a gate controlled by the sensing node, for driving a threshold node high when the sensing voltage drops;a charging capacitor coupled between the threshold node and the ground;a discharge transistor, coupled between the threshold node and the ground, for discharging the charging capacitor before the charging transistor turns on;a threshold stage, receiving the threshold node as an input, for inverting the threshold node to drive a trigger input; anda series of inverters, receiving the trigger input, for generating a reset signal;wherein a reset pulse is generated on the reset signal, the reset pulse ending in response to the sensing voltage falling when the transistor pulldown turns on when the sensing voltage reaches a predetermined voltage,whereby the reset pulse is generated by the capacitive-pullup divider.