Patent ID: 6182206
Filing Date: 2001-01-30
Classification: G06F

Abstract:
A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first instruction set architecture (ISA) that executes instructions from a first instruction set and a second instruction set architecture (ISA) that executes instructions of a second instruction set, the dynamically reconfigurable processing unit when configured as the first ISA being responsive to a reconfigure directive to change the internal hardware organization of the dynamically reconfigurable processing unit to be configured as the second ISA, wherein each ISA for the changeable internal hardware organization is capable of being represented as binary data in a memory device, and wherein the reconfigure directive is one of the instructions in the first instruction set.