Patent ID: 9000804
Filing Date: 2015-04-07
Classification: G06F,H03K,Y02D

Abstract:
1. An integrated circuit comprising clock gating circuitry, wherein the clock gating circuitry comprises: a first clock gating component located within a clock distribution network and arranged to enable a first part of the clock distribution network to be gated; gating control circuitry arranged to cause the first clock gating component to disable the first part of the clock distribution network upon certain conditions being fulfilled; a first clock gating disabling element configurable to enable the first clock gating component to enable the gating of the first part of the clock distribution network, and to receive as inputs a first clock gating control signal and a first clock gating enable signal; a second clock gating component arranged to enable a second part of the clock distribution network to be gated; and a second clock gating disabling element arranged to enable the second clock gating component to enable the gating of the second part of the clock distribution network, and to receive as inputs a second clock gating control signal and a second clock gating enable signal.