Patent ID: 7863668
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a memory cell region provided on the semiconductor substrate and including a memory cell array region and a dummy cell region; a word line provided on the memory cell region, extending contiguously on the dummy cell region and on the memory cell array region; a first gate insulating film provided on the semiconductor substrate in the memory cell array region beneath the word line; a first floating gate electrode provided on the first gate insulating film; a plurality of second gate insulating films provided on the semiconductor substrate in the dummy cell region beneath the same word line as the first gate insulating film along the direction of the word line, the second gate insulating films being different from the first gate insulating film in thickness; a plurality of second floating gate electrodes provided on the second gate insulating films along the direction of the word line; a control gate electrode provided above the first and second floating gate electrodes and connected to the word line; and a gate interelectrode insulating film provided between the first and second floating gate electrodes and the control gate electrode, wherein: