Patent ID: 8310432
Filing Date: 2012-11-13
Classification: G02F,G09G,G11C

Abstract:
1. A gate driving circuit comprising a shift register having a plurality of stages cascaded to one another, each of the plurality of stages including a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node to which a first input signal is applied; a pull-down unit discharging the gate signal to a level of a gate-off voltage if a second input signal is inputted; a discharging unit discharging a signal of the first node in response to the second input signal to the level of gate-off voltage; and a holding unit holding the signal of the first node in response to the first clock signal at a level of the gate signal discharged to the level of the gate-off voltage, wherein at least one of the discharging unit and the holding unit includes an amorphous silicon thin film transistor and a polysilicon thin film transistor connected in parallel to each other, and wherein the amorphous silicon thin film transistor and the polysilicon thin film transistor are configured to operate simultaneously.