Patent ID: 6094532
Filing Date: 2000-07-25
Classification: G06F,H04L

Abstract:
A data processing system comprising:(A) a Plurality of nodes,(B) a serial data bus interconnecting the nodes in series in a closed loop for sassing address and data information, and(C) at least one processing node including:(a) a processor,(b) a printed circuit board,(c) a memory partitioned into a plurality of sections, a first section for directly sharable memory located on the printed circuit card, and a second section for block sharable memory,(d) a local bus connecting said processor, said block sharable memory, and said printed circuit board for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board, and(e) the printed circuit board having:(i) a sensor for sensing when data is transferred into the said directly sharable memory,(ii) a queuing device for queuing said sensed data,(iii) a serializer for serializing said queued data,(iv) a transmitter for transmitting said serialized data onto said serial bus to next successive processing node,(v) a receiver for receiving serialized data from next preceding processing node, and(vi) a deserialize for deserializing said received serialized data into parallel; wherein(A) the serial data bus is an electrical based bus,(B) the transmitter is comprised of a driver for driving data from said serializer onto said electrical based bus, and(C) the receiver is comprised of an electrical receiver for receiving said received serialized data from said electrical based bus and presenting it to said deserialization;and further comprising(A) a clock recovery circuit for separation of the clock and data of said received serialized data,(B) a multiplexer selecting a serial bit stream from one of the clock recovery circuit and said serializer,(C) an error detector for detection of the dysfunction of the printed circuit board, and(D) a control circuit for switching of said multiplexer in response to detection of the dysfunction of the printed circuit board.