Patent ID: 7685364
Filing Date: 2010-03-23
Classification: G06F,G11C,H01L

Abstract:
1. A system comprising: an integrated circuit buffer device including: a first integrated circuit memory device to output a first portion of the data; a first signal path coupled to the integrated circuit buffer device and the first integrated circuit memory device, the first signal path to convey the first portion of the data from the first integrated circuit memory device to the integrated circuit buffer device; a second integrated circuit memory device to output a second portion of the data; a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey the second portion of data from the second integrated circuit memory device to the integrated circuit buffer device; and a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.