Patent ID: 8978000
Filing Date: 2015-03-10
Classification: G03F,G06F,H01L,Y02P

Abstract:
1. A method of assembling a layout comprising: measuring a first density of gate features or source/drain diffusion features within an array of unit cells with a layout tool comprising hardware; measuring a background density of gate features or source/drain diffusion features within background circuitry, which is arranged outside the array with the layout tool; determining a maximum variation for a parameter of a unit cell of the array as a function of a density gradient between the first density and the background density; consulting a look-up table to predict a buffer zone width that achieves a variation of the parameter that is less than the maximum variation; and forming a buffer zone, comprising a width that is less than or equal to the buffer zone width, between the array and the background circuitry, wherein the buffer zone further comprises a second density, which is less than the first density, and which is greater than the background density.