Patent ID: 7551472
Filing Date: 2009-06-23
Classification: G11C

Abstract:
1. A ferroelectric semiconductor memory device comprising: a memory cell block including a plurality of ferroelectric memory cells connected in series, each memory cell including a ferroelectric capacitor for holding a charge and a transistor connected in parallel with the ferroelectric capacitor; word lines connected to the respective transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; a plate line connected to another end of the block; and a control circuit for changing potentials of the word line and the bit line, with the potential of the plate line being held constant, the potential of the word line being changed, thereby erasing information or writing information to the ferroelectric memory cells, the information of the memory cells included in the block being erased by sequentially executing steps comprising: the potential of the bit line and the potential of the plate line being held constant during the first step to the third step.