Patent ID: 7586332
Filing Date: 2009-09-08
Classification: H03K

Abstract:
1. A driver, comprising: a plurality of first PMOS transistors, comprising a first source/drain terminal, a second source/drain terminal and a gate terminal for each of the first PMOS transistors, wherein all the first source/drain terminals are together coupled to a first operation voltage, all the second source/drain terminals are coupled to each other and all the gate terminals are coupled to each other; a first resistor, comprising an end coupled to the second source/drain terminals of all the first PMOS transistors and another end served as the output terminal of the driver; a first amplifier, comprising a first input terminal coupled to a first reference voltage, a second input terminal, and an output terminal coupled to the gate terminals of all the first PMOS transistors and outputs a first regulating voltage; a second PMOS transistor, comprising a first source/drain terminal coupled to the first operation voltage, a second source/drain terminal coupled to the second input terminal of the first amplifier, and a gate terminal coupled to the first regulating voltage; a second resistor, comprising an end coupled to the second input terminal of the first amplifier and another end coupled to a second operation voltage, wherein the first regulating voltage is for regulating the drain currents of the first PMOS transistors and the second PMOS transistor; a plurality of first NMOS transistors, comprising a first source/drain terminal, a second source/drain terminal and a gate terminal for each of the first NMOS transistors, wherein all the first source/drain terminals are together coupled to the first resistor, all the second source/drain terminals are coupled to the second operation voltage and all the gate terminals are coupled to each other; a second amplifier, comprising a first input terminal coupled to a second reference voltage, a second input terminal, and an output terminal coupled to the gate terminals of all the first NMOS transistors and outputs a second regulating voltage; a second NMOS transistor, comprising a first source/drain terminal coupled to the second input terminal of the second amplifier, a second source/drain terminal coupled to the second operation voltage, and a gate terminal coupled to the output terminal of the second amplifier; and a third resistor, comprising an end coupled to the second input terminal of the second amplifier and another end coupled to the first operation voltage, wherein the second regulating voltage is for regulating the drain currents of the first NMOS transistors and the second NMOS transistor; a third PMOS transistor, comprising a first source/drain terminal coupled to the first operation voltage, a second source/drain terminal coupled to the gate terminals of all the first PMOS transistors, and a gate terminal receiving a data signal; and a third NMOS transistor, comprising a first source/drain terminal coupled to the gate terminals of all the first NMOS transistors, a second source/drain terminal coupled to the second operation voltage, and a gate terminal receiving the data signal.