Patent ID: 6701461
Filing Date: 2004-03-02
Classification: G01R,G06F,G11C

Abstract:
A testing apparatus for testing a cache, which apparatus uses a test command row composed of memory access commands that utilize said cache to test said cache, said testing apparatus comprising:a cache registration table composed of a plurality of blocks corresponding to each one of a plurality of cache entries, with each block assigned with an address registration region for storing an access address of data stored in a corresponding entry, and a flag region for storing information showing validity of test command corresponding to the entry; a command creating unit which creates the memory access commands including information of cache entry; a first registering unit which registers the access address of the memory access command in the address registration region when the information in the flag region of the block corresponding to the entry indicated by the memory access command created by said command creating unit shows an invalid state, and changing the information in the flag region to the information showing validity; and a second registering unit which selects a block having a flag region showing an invalid state when the information in the flag region of the block corresponding to the entry indicated by the memory access command shows a valid state, changing the cache entry included in this address to a cache entry corresponding to the selected block, registering the access address information of the memory access command in the address registration region of the selected block, and changing the information in the flag region of the selected block to information showing validity.