Patent ID: 8188902
Filing Date: 2012-05-29
Classification: H03M

Abstract:
1. An apparatus comprising: a capacitive digital-to-analog converter (CDAC) having a resolution of N-bits that receives an analog input signal and a reference voltage; a first comparator stage having: a plurality of second comparator stages coupled in series with one another in a sequence, wherein each second comparator stage has: successive approximation register (SAR) logic that is coupled to the output terminals of the first and second comparator from the first comparator stage, the output terminals of the third and fourth comparators from each of the second comparator stages, and the CDAC, wherein the SAR logic controls the CDAC, and wherein the SAR logic performs a successive approximation ternary search using the output values from the first comparator, the second comparator, each third comparator, and each fourth comparator.