Patent ID: 6271133
Filing Date: 2001-08-07
Classification: H01L,Y10S

Abstract:
A method of fabricating Field Effect Transistor (FET's) having low sheet resistance gate electrodes comprising the steps of:providing a semiconductor substrate;forming FET devices in and on said substrate, each FET device having a polysilicon gate with spacers on the gate sidewalls and adjacent source/drain regions in said substrate, each FET device further having a cap layer on top of said poly gate, said cap layer being formed by depositing a layer of titanium nitride over a layer of polysilicon of said polysilicon gate after which said layer of titanium nitride and said layer of polysilicon are etched, thereby forming said polysilicon gate over which said cap of titanium nitride remains in place;depositing a blanket layer of titanium (Ti) over said gate electrode and its adjacent areas;annealing said titanium to form titanium silicide (TiSi.sub.2) over said source/drain contact areas;removing unreacted Ti from above said gate electrode and its adjacent areas;removing said cap layer from above said gate electrode;depositing a layer of cobalt over said gate and its adjacent areas;annealing said cobalt to form CoSi.sub.2 over said gate; and removing unreacted cobalt from above said gate electrode and its adjacent areas.