Patent ID: 7829926
Filing Date: 2010-11-09
Classification: G11C,H01L

Abstract:
1. A semiconductor structure, comprising: (a) a substrate; (b) 2 wherein N is a positive integer, and wherein the 2 (c) first N gate electrode lines on the 2 wherein the first N gate electrode lines run in a second direction which is perpendicular to the first direction, and wherein the first N gate electrode lines are electrically insulated from the 2 (d) a contact region electrically coupled to the 2 (e) a first plurality of memory cells on the 2 wherein the first N gate electrode lines are disposed between the first plurality of memory cells and the contact region, wherein in response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells on only one of the 2 wherein intersection transistors on each semiconductor region of the 2