Patent ID: 9197398
Filing Date: 2015-11-24
Classification: H03K,H03L,H04L

Abstract:
1. A distributed phase-correction circuit, comprising: an input node configured to receive an input signal having a period; a first delay line, coupled to the input node and a second delay line, configured to provide an output signal, wherein the first delay line includes: the second delay line, coupled to the first delay line, configured to receive the output signal, to control phases of the phase-alignment elements for the first delay line and to provide a second output signal, wherein the second delay line includes: wherein a first of the phase-alignment elements in the second delay line receives an output of a last of the phase-alignment elements in the first delay line, wherein the output of the last of the phase-alignment elements in the first delay line controls a phase of a first of the phase-alignment elements in the first delay line, and wherein the first of the phase-alignment elements in the first delay line receives the input signal.