Patent ID: 8080842
Filing Date: 2011-12-20
Classification: H01L

Abstract:
1. A nonvolatile memory device comprising: a substrate having cell and peripheral circuit regions; a multi-layer charge-storage insulation layer physically formed on the substrate in the cell region; a cell gate electrode having a lower cell conductive layer and at least one upper cell conductive layer stacked on the multi-layer charge-storage insulation layer; a gate insulation layer formed on the substrate in the peripheral circuit region; and a peripheral-circuit gate electrode having peripheral conductive layers stacked on the gate insulation layer, wherein the lower cell conductive layer is different from the lowest one of the peripheral conductive layers of the peripheral-circuit gate electrode, and wherein the lower cell conductive layer is a single layer or a multiple layer of a metal having a work function larger than about 4 eV and physically contacts the multi-layer charge-storage insulation layer.