Patent ID: 8330231
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A transistor comprising: a semiconductor substrate; a gate stack overlying the semiconductor substrate and comprising a gate dielectric and an overlying gate electrode; a relatively thin sidewall spacer dielectric along sidewalls of the gate dielectric and the gate electrode, wherein a barrier layer adjacent each of an outer edge of the opposing vertical sides of a channel, the barrier layer comprising a dopant blocking species to impede migration of a dopant species, wherein the channel underlying the gate electrode and the gate dielectric, wherein the channel comprises opposing vertical sides adjacent the barrier layer; a source and a drain adjacent the opposing vertical sides of the channel and separated from the channel by the barrier layer, each of the source and the drain comprising the dopant species; a second sidewall spacer adjacent to the relatively thin sidewall spacer dielectric and overlying a portion of the source and drain, wherein the second sidewall spacer is relatively thick compared to the relatively thin sidewall spacer; and a deep source region and a deep drain region underlying a portion of the source and drain respectively, wherein