Patent ID: 6118334
Filing Date: 2000-09-12
Classification: G06F

Abstract:
A method of designing power supply wiring on a semiconductor integrated circuit formed within a semiconductor chip, comprising:a grid state power supply wiring layout determination step for determining the line width and the intervals of a grid state power supply wiring for supplying electric power to integrated circuits in accordance with an internal circuit placement of said integrated circuits;an electric current consumption calculation step for calculating power consumption within each region of said integrated circuit as defined by said grid state power supply wiring;an electric voltage/current calculation step for calculating an average voltage and an electric current of each side of a square formed by said grid state first power supply wiring in accordance with the calculation results of said electric current consumption calculation step; anda power supply auxiliary wiring layout determination step for obtaining restriction conditions of allowable minimum currents and allowable voltage drops applicable respectively to said sides and designing a power supply auxiliary wiring in the form of a binary tree which satisfies said restriction conditions in accordance with the calculation results of said electric voltage/current calculation step and connected to a power supply pad, to which said power supply wiring is not connected.