Patent ID: 6052011
Filing Date: 2000-04-18
Classification: H03H,H03L

Abstract:
A fractional period delay circuit to provide a plurality of delayed timing signals, wherein each delayed timing signal is delayed from a first timing signal by any predetermined fraction of a period of said first timing signal, comprising:a) a first delay line having an input connected to a master timing signal, a delay circuit connected to the input to delay the master timing signal to form the first timing signal, and an output connected to the delay circuit to transfer said first timing signal to subsequent circuitry:b) a plurality of adjustable delay lines, wherein each adjustable delay line has an input connected to said master timing signal, an adjustable delay circuit to delay the master timing signal, a delay adjustment input connected to the adjustable delay circuit to modify a delay parameter of said adjustable delay circuit, and an output connected to the adjustable delay circuit to transfer said one delayed timing signal to subsequent circuitry;c) a plurality of phase difference detectors, wherein each phase difference detector has a first input connected to the output of the first delay line, a second input connected to the output of one of the plurality of adjustable delay lines, a difference circuit to create a difference signal indicating a difference in phase between the first timing signal and a delayed timing signal, and an output to transfer the difference signal;d) a timing sequence generator connected to the output of the first delay line to create a plurality of sequence timing signals;e) a plurality of phase correction calculators, wherein each phase correction calculator is connected to one of the plurality of phase difference detectors and the timing sequence generators to calculate a delay adjustment signal that will maintain a correct delay signal indicating an error between the one delay timing signal and the first timing signal; andf) a plurality of delay line adjustment circuits, wherein each delay line adjustment circuit is connected to one of the plurality of phase correction calculators and to the delay adjustment input of one of the adjustable delay lines to adjust the delay of said adjustable delay line such that the one delay timing signal is correctly delayed with respect to said first timing signal.