Patent ID: 8872287
Filing Date: 2014-10-28
Classification: B81C,H01L

Abstract:
1. An integrated structure for a MEMS device and a semiconductor device, comprising: a substrate; a dielectric layer formed on the substrate; a MEMS device formed in the substrate or in or partially in the dielectric layer and exposed to the environment; a semiconductor device formed in or partially in the substrate or in or partially in the dielectric layer; an etch stopping element formed on the substrate and in or partially in the dielectric layer between the MEMS device and the semiconductor device, surrounding the MEMS device on all sides of the MEMS device in a plane parallel to the substrate, and not covering the MEMS device, and further comprising an etch-resistant material layer stacked with etch-resistant material plugs, thereby to protect the semiconductor device from being etched during a release process for making the MEMS device; an interconnect having a plurality of layers disposed within the dielectric layer and contacting the semiconductor device, wherein a top layer of the interconnect is on the dielectric layer; and a passivation layer covering the top layer of the interconnect and not covering the MEMS device.