Patent ID: 6169329
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A semiconductor device, comprising: a carrier substrate including a plurality of conductors on a surface thereof, the conductors of the plurality being arranged to mate with an array of external connections of a pitch and pattern and located over and projecting from an active surface of a first die; a second die having an active surface with a plurality of bond pads arranged thereover in an arrangement at least partially different from the arrangement of the plurality of conductors on the surface of the carrier substrate; a plurality of external connections on the second die located over and projecting from an active surface thereof, at least some of the plurality of external connections on the secind die being offset from at least some of the plurality of bond pads thereof, said plurality of external connections arranged in an array over the active surface of the second die, the array of external connections of the second die being arranged to substantially correspond in pitch and pattern to the pitch and pattern of the external connections of the array located over the active surface of the first die, the plurality of external connections of the second die being in mating contact with the conductors of the plurality on the surface of the carrier substrate; and a plurality of circuit traces extending over the active surface of the second die and connecting at least some of the plurality of external connections on the second die to at least some of the plurality of bond pads on the second die; wherein the second die differs from the first die in at least one of the following respects: size, shape, bond pad arrangement and circuitry.