Patent ID: 6191027
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:a) providing a substrate having an insulating layer thereon;b) forming a connection hole including a first sub-hole and a second sub-hole mutually aligned and connected in the insulating layer, wherein the first sub-hole has a first diameter and the second sub-hole has a second diameter larger than the first diameter;c) forming a first conductive layer over the substrate;d) removing the first conductive layer to a thickness so as to form a side wall spacer film on a side wall of the second sub-hole and a plug film in the first sub-hole;e) forming a barrier metal layer over the substrate to cover the side wall spacer and the plug film;f) forming a second conductive layer over the substrate to fill space in the connection hole; andg) chemical mechanical polishing the second conductive layer.