Patent ID: 6088235
Filing Date: 2000-07-11
Classification: G11B,H05K

Abstract:
A circuit assembly for a mass storage device comprising:an insulative substrate carrying a patterned array of conductive traces,an integrated circuit mounting region defined by the substrate as a pattern of connection pads aligned to be connected to pins of an integrated circuit, the pins including a single-ended preamplifier signal input pin and at least two ground pins,the patterned array of conductive traces including:a signal path extending from a trace pad aligned with the preamplifier signal input pin to a distal signal input connection pad, anda plurality of loops, the loops including corresponding ground return paths and the signal path, each of the corresponding ground return paths leading from a vicinity of the distal signal input connection pad to the at least two ground pins, the ground return paths including:a first ground return path combined with the signal path to form a first loop having a first position relative to a single-ended preamplifier, anda second ground return path combined with the signal path to form a second loop having a second position relative to the single-ended preamplifier approximately opposite the first position, andwherein the first loop and the second loop are arranged so that a common mode interference induces noise currents in approximately opposite directions in the first loop and the second loop, the noise currents becoming approximately canceled at the single-ended preamplifier signal input pin.