Patent ID: 7590827
Filing Date: 2009-09-15
Classification: G06F

Abstract:
1. A processor comprising: a buffer which is allocated a respective storage location for all general registers storing source data and stores latest register update data; a buffer control unit which stores the latest register update data into said buffer in accordance with success or failure of speculative execution of a register update instruction; and a storage control unit which reads out the latest register update data from said buffer and stores the latest register update data into a data area in a reservation station upon decoding the register update instruction, without determining whether the latest register update data is update-pending, wherein the buffer control unit stores the latest register update data obtained from the speculative execution into said buffer upon success in the speculative execution of the register update instruction, and stores data in a general register into the buffer as the speculative execution of the register update instruction is cancelled upon completion of a branch prediction of a branch instruction associated with the speculative execution of the register update instruction and failure of the branch instruction is predicted by the branch prediction.