Patent ID: 6885072
Filing Date: 2005-04-26
Classification: H01L

Abstract:
1. A nonvolatile memory with undercut trapping structure, said nonvolatile memory comprising: a semiconductor substrate; a gate oxide formed on said semiconductor substrate; a gate structure formed on said gate oxide, wherein said gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into said gate structure; an isolation layer formed over the sidewall of said gate structure; first spacers formed on the sidewall of said isolation layer and filled into said undercut structure for storing carriers; source and drain regions formed adjacent to said gate structure and under said undercut structure; and double doped drain region adjacent to said source and drain regions and under said undercut structure, wherein the junction of said double doped drain region is deeper than the one of said source and drain regions and said double doped drain region is closer to the channel under said gate structure than said source and drain regions; and pocket ion implantation region located adjacent to said source and drain regions and under said undercut structure, wherein the conductive type of the pocket ion implantation region is opposite to the one of the source and drain regions.