Patent ID: 6787855
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A semiconductor device comprising:an SOI substrate having respectively a semiconductor substrate, a dielectric layer, and a semiconductor layer; a transistor having a drain region and a source region respectively formed in said semiconductor layer; a gate electrode formed via a gate dielectric film on a channel region sandwiched between said drain region and said source region; an interlayer dielectric film formed on said transistor; a drain wiring and a source wiring formed on said interlayer dielectric film; a first conductor formed in said interlayer dielectric film and connecting said drain wiring to said drain region; a second conductor formed in said interlayer dielectic film and connecting said source wiring to said source region; said drain region including, a first part adjacent to said channel region, and a second part formed to protrude from said first part of the drain region so that a part of outer peripheries of said second part of said drain region extends away from said gate electrode in a plan view; and said first conductor is connected to said second part of said drain region.