Patent ID: 6678198
Filing Date: 2004-01-13
Classification: G11C

Abstract:
A DRAM with differential sensing means comprising:a top block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective top bit line; a bottom block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective bottom bit line; a plurality of sense amplifiers positioned between the top block of data cells and the bottom block of data cells, each sense amplifier of the plurality of sense amplifiers is shared by a respective top bit line and a respective bottom bit line; a first replica memory cell with a maximum driving strength of a portion of driving strength of each of the data cells in the top block and the bottom block of data cells, wherein when a first data cell in the top block is accessed, the first replica memory cell turns on to discharge a first respective bottom bit line at a portion of a discharge rate of a first respective top bit line driven by the accessed first data cell, and a first respective sense amplifier compares the charge on the first respective top bit line driven by the accessed first data cell and the charge on the first respective bottom bit line driven by the first replica memory cell to determine the state of the accessed data cell in the top block in response to portioned discharge rate of the first respective bottom bit line; a second replica memory cell with a maximum driving strength of a portion of driving strength of each of the data cells in the top block and the bottom block of data cells, wherein when a second data cell in the bottom block is accessed, the second replica memory cell turns on to discharge a second respective top bit line at a portion of a discharge rate of a second respective bottom bit line driven by the accessed second data cell, and a second respective sense amplifier compares the charge on the second respective bottom bit line driven by the accessed second data cell and the charge on the second respective top bit line driven by the second replica memory cell to determine the state of the accessed data cell in the bottom block in response to portioned discharge rate of the second respective top bit line; and a write equalization switch for equalizing a write bit line in the top block of data cells with a respective write bit line in the bottom block of data cells during a read cycle.