Patent ID: 7230459
Filing Date: 2007-06-12
Classification: H03K

Abstract:
1. A static frequency divider circuit, comprising: a first latch having a first input and first output; a second latch having a second input and second output; a first push-pull circuit interconnecting the first output of the first latch to the second input of the second latch with one of a negative/positive series path; and a second push-pull circuit interconnecting the second output of the second latch to the first input of the first latch with the other of the negative/positive series path, wherein each of the first and second latches include a clock input, the clock input of the first latch receiving a clock signal and the clock input of the second latch receiving the clock signal out of phase by 180 degrees, and wherein each of the first and second push-pull circuits include a clock input, the clock input of the first push-pull circuit receiving the clock signal and the clock input of the second push-pull circuit receiving the clock signal out of phase by 180 degrees.