Patent ID: 9111788
Filing Date: 2015-08-18
Classification: G11C,H01L

Abstract:
1. A memory device construction comprising: a first column line extending parallel to a second horizontal column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states, the memory material being above the second column line and below the row line, the row line and the memory material being comprised by a stack of materials having a pair of opposing sidewalls; a pair of insulative spacers along the opposing sidewalls of the stack, the insulative spacers being in direct contact with the row line and the memory material; a pair of conductive spacers along the insulative spacers, the conductive spacers comprising a material selected from a metal material and doped semiconductive material, a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material.