Patent ID: 6215339
Filing Date: 2001-04-10
Classification: H03K,H04L

Abstract:
An input buffer circuit for receiving digital data signals from a transmission line, comprisingan amplifier section (2) having a non-inverting input (INP) and an inverting input (INN) connected for receiving data signals transmitted over said transmission line, and an output (OUT) for outputting digital data corresponding to the received digital data signals;a monitor section (1) having a first input connected to the non-inverting input (INP) of said amplifier section, a second input connected to said inverting input (INN) of said amplifier section (2), and a monitor output (MOUT); anda power control section (3) connected to receive a control signal from said monitor output (MOUT) of said monitor section (1);said monitor section being adapted to output said control signal (MOUT) depending on whether a data signal transmitted via said transmission line is available at the inputs (INP, INN) of said monitor section (1);said power control section (3) being adapted to switch said amplifier section (2) into a low power stand-by state if no data are detected by said monitor section, and to switch said amplifier section into an operating state if data are detected by said monitor section (1);whereinsaid monitor section (1) is adapted to output said control signal (MOUT) indicating that data are present if an absolute difference between signals present at said first and second monitor section inputs is larger than a predetermined threshold, and to output said control signal (MOUT) indicating that no data are present, if said difference is smaller than said predetermined threshold;characterized in thatsaid monitor section (1) comprises an analogue multiplier circuit (T1 to T6) having a first differential input (112, 122), a second differential input (111,121) and an output (QA, QB);a first terminal (122) of said first differential input being connected with a first terminal (121) of said second differential input, and a second terminal (112) of said first differential input being connected with a second terminal (111) of said second differential input;said first terminals (121, 122) of said first and second differential input constituting said first input (12) of said monitor section (1), and said second terminals (111, 112) of said first and second differential input (11) constituting said second input of said monitor section (1).