Patent ID: 8127116
Filing Date: 2012-02-28
Classification: G06F

Abstract:
1. A processor embodied at least in part in hardware, the processor having a dependency matrix, the dependency matrix comprising: a first array comprising a plurality of first cells; a second array coupled to the first array and comprising a plurality of second cells; a first write port coupled to the first array and the second array and configured to write to the first array and the second array; a first read port coupled to the first array and the second array and configured to read from the first array and the second array; a second read port coupled to the first array and configured to read from the first array; a second write port coupled to the second read port and configured to read from the second read port and to write to the second array; and select logic coupled to the first array and the second array and configured to select between a read output of the first array and a read output of the second array.