Patent ID: 6748521
Filing Date: 2004-06-08
Classification: G06F

Abstract:
A digital system comprising a microprocessor having an instruction execution pipeline with a plurality of pipeline phases, wherein the microprocessor comprises:program fetch circuitry operable to perform a first portion of the plurality of pipeline phases; instruction decode circuitry connected to receive fetched instructions from the program fetch circuitry, the instruction decode circuitry operable to perform a second portion of the plurality of pipeline phases; and at least a first functional unit connected to receive control signals from the instruction decode circuitry, the functional unit operable to perform a third portion of the plurality of pipeline phases, the third portion being execution phases, wherein the first functional unit comprises: partitionable multi-field packing circuitry connected to receive a plurality of source operands and having outputs connected to provide a multi-field saturated result as a destination operand in response to control signals from the instruction decode circuitry, wherein the multi-field packing circuitry is operable to treat the plurality of source operands as a set of N1 fields, such that the multi-field saturated result includes N1 saturated results corresponding to the set of N1 fields; and wherein the first functional unit is operable to provide the multi-field saturated result in response to a single instruction of a first type, wherein N1 is two in response to a first instruction of the first the and wherein N1 is four in response to a second instruction of the first type.