Patent ID: 8486789
Filing Date: 2013-07-16
Classification: H01L

Abstract:
1. A method for manufacturing an insulated gate field effect transistor, the method comprising the steps of: (a) preparing a base that includes source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) forming a gate electrode by burying (i) a work function control layer and (ii) a conductive material layer in the gate electrode formation opening; (c) removing the insulating layer to expose the source/drain regions; and (d) depositing a first interlayer insulating layer and a second interlayer insulating layer sequentially across an entire surface of the exposed source/drain regions by vapor deposition; (e) forming sidewalls that define the gate electrode formation opening; and (f) removing an insulating film abutting at least one of the sidewalls so that the sidewalls remain intact, wherein,