Patent ID: 6560240
Filing Date: 2003-05-06
Classification: G06F,Y02D

Abstract:
An integrated circuit, the integrated circuit comprising:a bus; a clock coupled to the bus which provides a clock signal to the bus, wherein the clock signal has a clock rate, wherein the bus operates according to the clock rate; a plurality of modules, wherein each of the plurality of modules is coupled to said bus, wherein said each of the plurality of modules is operable to transfer data on the bus and to receive data on the bus; and a bus controller coupled to the bus which controls data transfers on the bus; wherein one or more of the plurality of modules is operable to generate requests to the bus controller to perform transfers on the bus, wherein each of said requests to perform data transfers comprises: an identifier which identifies one or more receiving modules; a transfer size value which specifies the amount of data to be transferred; and a timing value providing a time frame within which the requested data transfer should occur; wherein the bus controller receives said requests from one or more of the plurality of modules for data transfers among the plurality of modules, wherein, for each said request, the bus controller analyzes the timing value provided with said request and selectively adjusts the clock rate of the bus based on said timing value.