Patent ID: 6049493
Filing Date: 2000-04-11
Classification: G11C

Abstract:
A semiconductor memory device, which has a plurality of bit lines, a plurality of word lines and a plurality of memory cells provided at intersections of said bit lines and word lines, comprising:a sense amplifier for detecting a potential generated at said bit lines;a bit line precharge circuit for precharging said bit lines to a first potential during a precharging period;a sense amplifier precharge circuit for, during said precharging period, precharging said sense amplifier to a second potential differing from said first potential; anda bit line transfer gate circuit for separating said bit lines and said sense amplifier when said bit lines and said sense amplifier are precharged, and for coupling said bit lines and said sense amplifier when the precharge are completed and said bit lines and said sense amplifier are released from said first and said second potentials,wherein said word lines are driven after said bit line transfer gate circuit has connected said bit lines and said sense amplifier and said bit lines are set to a third potential between said first and said second potentials.