Patent ID: 6021481
Filing Date: 2000-02-01
Classification: G06F

Abstract:
An address translation cache management apparatus, comprising:an address translation cache storing recent effective-to-real address translations;a latch having at least one bit for each one of a plurality of segment registers;an invalidate pending latch;loading means for loading said address translation cache with an effective-to-real address translation upon an address translation cache miss with an address generated by one of the segment registers and a translation lookaside buffer;means for setting a bit of said latch corresponding to the segment register utilized by said loading means;means for setting said invalidate pending latch when a value stored by one of the segment registers is altered and when a corresponding bit in said latch has already been set for the segment register whose contents have been altered; andinvalidating means for invalidating said address translation cache when a context-synchronizing event occurs and said invalidate pending latch is set.