Patent ID: 7146468
Filing Date: 2006-12-05
Classification: G06F

Abstract:
1. A pipelined multi-pass cache memory in a microprocessor, which internally handles an in-flight transfer of a cache line between itself and a second cache that address-collides with a snoop operation, rather than canceling the in-flight operation, the cache memory comprising: a single-ported memory array, for storing cache coherency status for a plurality of cache lines; an arbiter, coupled to said single-ported memory array, configured to arbitrate among requests to pass through the cache memory pipeline to access said single-ported memory array to query or update said cache coherency status, and configured to grant access to a snoop query request temporally between granting access to a query request of an operation and granting access to a finish request of said operation, said operation for transferring a cache line between the cache memory and another cache memory in the microprocessor, said query request and said finish request comprising an address of said cache line, said snoop query comprising a snoop address; and control logic, coupled to said memory array, configured to generate said finish request in response to said query request of said operation, and configured to detect a collision between said snoop address and said address of said cache line of said finish request, and configured to generate a snoop action request to said arbiter, wherein said finish request comprises an update status for updating said cache coherency status in said single-ported memory array at said address of said cache line; wherein said snoop action request comprises a snoop update status generated by said control logic based on said update status of said finish request, based on a type of said finish request, and based on detection of said collision; wherein said arbiter is configured to grant access to said snoop action request to update said cache coherency status with said snoop update status, after granting access to said finish request to update said cache coherency status, whereby the cache memory internally handles said collision to eliminate the need to retry said operation for transferring a cache line between the cache memory and said another cache memory of the microprocessor.