Patent ID: 6429901
Filing Date: 2002-08-06
Classification: H03L,H04N

Abstract:
A phase locked loop (PLL) circuit for generating an oscillation clock which maintains a substantially constant phase difference with respect to a phase of a reference clock, comprising:a voltage controlled oscillator receiving a control voltage and producing an oscillation clock having a frequency corresponding to the control voltage; a comparison circuit receiving the reference clock and the oscillation clock and comparing phases of the reference clock and the oscillation clock with each other to produce a comparison signal indicative of a comparison result; a charge pump circuit, connected to said comparison circuit, a ground potential and a power supply potential, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the charge pump pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential; and a low-pass filter, connected between said charge pump circuit and said voltage controlled oscillator, for smoothing the output of the charge pump circuit to produce the control voltage, wherein said charge pump circuit includes: first and second transistors each having a source, a drain and a gate, wherein the first and second transistors are alternately turned on and off in response to the comparison signal applied to their gates; a constant current source for supplying a constant current; a first current mirror circuit, connected between the drain of said first transistor and the output terminal of the charge pump circuit, for allowing flow of a constant drive current according to the constant current of said constant current source when said first transistor is turned on; and a second current mirror circuit, connected between the drain of said second transistor and the output terminal of the charge pump circuit, for allowing flow of a constant drive current according to the constant current of the constant current source when the second transistor is turned on.