Patent ID: 9189050
Filing Date: 2015-11-17
Classification: G06F,Y02D

Abstract:
1. A method for reducing power usage of a memory, the method comprising: receiving a plurality of low-priority commands associated with the memory during low-power mode; grouping the plurality of low-priority commands into a batch; and delaying execution of the batch until a predetermined event associated with the memory occurs, wherein the memory remains in the low-power mode until the predetermined event associated with the memory occurs, wherein the predetermined event occurs when a command storage of an arbitration unit is full, when a maximum latency time for the at least one low priority command is reached, the low-power mode is changed to a high-power mode by a high-level power control, a watch dog time is expired, and at least one low-priority command of the plurality of low-priority commands is addressed to an open memory page.