Patent ID: 8238137
Filing Date: 2012-08-07
Classification: G11C

Abstract:
1. A ferroelectric random access memory device, comprising: a first bit line; a second bit line; a first ferroelectric memory cell connected between the first bit line and a first plate line; a second ferroelectric memory cell connected between the second bit line and a second plate line; a sense amplifier connected between the first bit line and the second bit line, and configured to amplify a potential difference between the first bit line and the second bit line; a first output terminal; a second output terminal; a first output line comprising a first end connected to a power supply and a second end connected to the first output terminal; a second output line comprising a first end connected to the power supply and a second end connected to the second output terminal; a first Metal Oxide Semiconductor (MOS) transistor connected between the first output line and ground, and comprising a gate connected to the first bit line; a second MOS transistor connected in series with the first MOS transistor between the first output line and the ground; a third MOS transistor connected between the second output line and the ground, and comprising a gate connected to the second bit line; and a fourth MOS transistor connected in series with the third MOS transistor between the second output line and the ground, wherein the first bit line is set to a first data potential according to first data stored in the first ferroelectric memory cell, the second bit line is set to a second data potential according to second data which are logical inversion of the first data, and the second MOS transistor and the fourth MOS transistor are turned on.