Patent ID: 6511878
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A manufacturing method for a semiconductor device having a memory cell region and a peripheral region, wherein said memory cell region includes a lower electrode electrically connected to a predetermined first connection region and an upper electrode provided to said lower electrode with a dielectric film interposed, comprising the steps of:forming a first interlayer insulating film on said first connection region; forming a second interlayer insulating film, of which a wet etching ratio with respect to a predetermined wet etchant is greater than that of said first interlayer insulating film, on said first interlayer insulating film; forming a first contact hole which penetrates said first interlayer insulating film and said second interlayer insulating film to reach up to said first connection region in said memory cell region, and which is provided in a connection region between said first interlayer insulating film and said second interlayer insulating film such that an inner diameter of said first interlayer insulating film becomes greater than that of said second interlayer insulating film; forming the lower electrode in a cylindrical form along an inner surface of said first contact hole; removing only said second interlayer insulating film in said memory cell region; and interposing the dielectric film with respect to said lower electrode to embed the dielectric film into an inner peripheral surface of said lower electrode, and forming the upper electrode so as to surround an outer peripheral surface of said lower electrode.