Patent ID: 9222968
Filing Date: 2015-12-29
Classification: G01R

Abstract:
1. A system for detecting stress degradation of a semiconductor circuit, the system comprising: a primary semiconductor circuit that has a plurality of monitor nodes; an amplifier circuit with at least one amplifier output terminal; at least one degradation test transistor; and a plurality of multiplexers each having an output coupled to a respective electrode of the degradation test transistor, and each of the multiplexers having an input coupled to one of the monitor nodes and a respective node of the amplifier circuit, wherein in operation the multiplexers selectively insert the degradation test transistor into either the primary semiconductor circuit or the amplifier circuit so that when inserted into the primary semiconductor circuit the degradation test transistor is subjected to stress degradation voltages in the primary semiconductor circuit and wherein when inserted into the amplifier circuit an output signal at the output terminal is indicative of stress degradation of the primary semiconductor circuit, wherein the amplifier circuit includes a differential amplifier and the degradation test transistor forms part of a first branch of the differential amplifier and part of a second branch of the differential amplifier is formed by a reference transistor.