Patent ID: 8055947
Filing Date: 2011-11-08
Classification: G01R

Abstract:
1. A process of operating an integrated circuit having a test mode select lead, the process comprising: A. receiving link identification data on the test mode select lead, the test mode select lead being coupled with a test mode select lead of each of plural target system adapters; B. for each target system adapter, supplying an isolation pattern of binary bits from the adapter to the test mode select lead through buffer circuitry; C. for each target system adapter, sampling the binary bits carried on the test mode select lead through buffer circuitry; D. for each target system adapter, comparing the supplied binary bits with the sampled binary bits; E. for a target system adapter in which the supplied binary bits do not match the sampled binary bits, stopping the supplying, sampling, and comparing; and F. continuing the supplying, sampling, and comparing in the remaining target system adapters.