Patent ID: 8946793
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit comprising the steps of: forming an interlayer dielectric (ILD) layer over a dummy gate stack, the dummy gate stack formed over a semiconductor substrate, the dummy gate stack comprising a dummy gate structure, a hardmask disposed over the dummy gate structure, and sidewall spacers disposed along sides of the dummy gate structure and the hardmask; removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer; forming a thin liner along the ILD layer within the first opening; extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, thereby exposing a portion of the semiconductor substrate; depositing at least one workfunction material layer within the first opening and within the first extended opening; removing portions of the at least one workfunction material within the first opening; and depositing a low-resistance material over a remaining portion of the at least one workfunction material, thereby forming a replacement metal gate structure comprising the remaining portion of the at least one workfunction material and the low-resistance material.