Patent ID: 6505276
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A processing-function-provided packet-type memory system comprising:a plurality of packet-type memory LSIs (Large Scale Integration circuits); a plurality of processing-function-provided packet-type memory LSIs; and a memory controller LSI; wherein the memory controller LSI, the packet-type memory LSIs, and the processing-function-provided packet-type memory LSIs are connected to one another by a bi-directional data bus and a bi-directional command bus and moreover, the packet-type memory controller LSIs and the processing-function-provided packet-type memory LSIs are connected to each other by a unidirectional ready signal line extending toward the memory controller LSI and a bus adjustment signal line serving as a bi-directional signal line, wherein whether the processing-function-provided packet-type memory LSI completes processing or the fact that the processing-function-provided packet-type memory LSI is ready to transfer an exclusive right is notified from the processing-function-provided packet-type memory LSI to the memory controller LSI through the ready signal line.