Patent ID: 7524733
Filing Date: 2009-04-28
Classification: H01L,Y10S

Abstract:
1. A method of fabricating an asymmetric source/drain transistor, comprising: defining an active region in a semiconductor substrate using an isolation layer; doping channel ions in the active region; planarizing a selective epitaxial growth (SEG) layer disposed in a predetermined region of the active region that contains the channel ions; sequentially depositing a gate insulating layer, a gate conductive layer, and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer; sequentially patterning the gate hard mask layer and the gate conductive layer to form a gate pattern crossing the active region, the planarized SEG layer located to one side of the gate pattern; and implanting impurity ions using the gate pattern as an ion implantation mask to form source/drain regions.