Patent ID: 6201732
Filing Date: 2001-03-13
Classification: G11C,H01L

Abstract:
A method for operating a memory array arranged in a plurality of N rows and a plurality of M columns, said memory array comprising:one or more source lines;one or more source select lines;a plurality of N control lines; anda plurality of N.times.M EEPROM cells, each uniquely associated with one of said rows and one of said columns, each of said EEPROM cells comprising:a memory transistor formed in a memory well, said memory transistor comprising a source, a drain, a channel, and a floating gate;a capacitor coupling between said control line and said floating gate of said memory transistor; anda source select transistor connected between said source of said memory transistor and its associated source line, and having a source select control gate connected to an associated one of said source select lines,said method comprising the steps of programming and erasing said EEPROM cells by tunneling of electrons between said floating gate and said channel, said tunneling being performed along substantially all of that portion of said channel which is located beneath said floating gate.