Patent ID: 9123422
Filing Date: 2015-09-01
Classification: G06F,G11C

Abstract:
1. A mixed-mode flash memory chip comprising: a flash memory having a plurality of blocks of flash memory cells that are Triple-Level-Cell (TLC) cells that are capable of storing three binary bits per physical flash memory cell, each flash memory cell having eight logic states determined by multiple voltage levels; wherein each block of the flash memory cells are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode and are capable of programming two binary bits per physical memory cell when operating in a Multi-Level-Cell (MLC) mode; a plurality of voltage references generated from a first reference voltage, the plurality of voltage references being in a sequence of differing values; a plurality of comparators that generate a plurality of compare results by comparing a bit line connected to a flash memory cell to the plurality of voltage references; two external mode pins for configuring the entire mixed-mode flash memory chip to function as TLC, MLC, or SLC; two internal mode registers for logically combining with the two external mode pins, the two internal mode registers being programmable by firmware to configure the whole chip to function as TLC, MLC, or SLC; two mode registers for each block of the flash memory cells, wherein the two mode registers are logically combined with the two external mode pins and the two internal mode registers when the block of the flash memory cells is being accessed, wherein the two mode registers for each block are programmable by firmware to configure the block of the flash memory cells to function as TLC, MLC, or SLC; a set of programmable level registers for each block of the flash memory cells, the set of programmable level registers only usable when the entire mixed-mode flash memory chip is configured to be either MLC or SLC; translation logic with truth table logic under control of the two external mode pins, the two internal mode registers, the set of programmable level registers, and the two mode registers for each block of the flash memory cells, the translation logic receiving the plurality of compare results as inputs; wherein in SLC mode, the translation logic generates one read data bit for a selected cell according to the truth table logic; wherein in MLC mode, the translation logic generates two read data bits for the selected cell according to the truth table logic; and wherein in TLC mode, the translation logic generates three read data bits for the selected cell according to the truth table logic.