Patent ID: 8448051
Filing Date: 2013-05-21
Classification: H03M

Abstract:
1. A memory system, comprising: a p-adic number converter unit operative to divide batch-processed binary data D into δ-digit (δ is an integer), h-bit (h is an integer) symbols and convert the symbols to a k-digit (k is an integer), p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from said data word p-adic converted at said p-adic number converter unit, a code C composed of a residual field Zp of the prime p, of n-digit (n=p−1) code words having numbers on digits each indicated by h bits; a memory unit operative to store the code C of Zp generated at said encoder unit as write data; an error correcting unit operative to generate, from read data Y read out from said memory unit, a syndrome S and apply an operation using said generated syndrome S for error correcting said read data Y to regenerate the code C of Zp; a decoder unit operative to reverse-convert the code C of Zp regenerated at said error correcting unit to regenerate the p-adic data word; and a binary converter unit operative to convert the data word regenerated at said decoder unit to a binary number to regenerate the binary data D.