Patent ID: 9087037
Filing Date: 2015-07-21
Classification: G06F

Abstract:
1. A method, comprising: testing Intellectual Property (IP) blocks in a system on a chip (SoC) by, for each of a plurality of IP blocks, receiving, at a test controller integrated on the SoC, tester input from a tester external to the SoC; generating, at the test controller and based on the tester input, a test package including test data and/or test commands for testing the IP block; transmitting, via an interconnect fabric integrated on the SoC, the test package from the test controller to a test wrapper integrated on the SoC and communicatively coupled to the IP block and the interconnect fabric, the test package being transmitted as one or more packets; and providing, via the test wrapper, test input data, control, and/or stimulus signals derived from the test package to the IP block to facilitate circuit-level testing of the IP block corresponding to the test data and/or test commands in the test package.