Patent ID: 6560568
Filing Date: 2003-05-06
Classification: G06F

Abstract:
A method for developing a statistical device model for a production process used to mass-produce chips each chip being formed in a substrate of a wafer and having an integrated circuit, each integrated circuit having a plurality of primitive device model types, the method comprising the steps of:(a) testing each wafer of a plurality during the production process to provide at least one set of e-test data for each said wafer, each wafer having at least one of said chips formed therein during the production process; and (b) deriving the statistical device model from the sets of e-test data, wherein each set of e-test data comprises a plurality of key electrical metrics for each of the plurality of primitive device model types, wherein each set of e-test data is made at a test site on a wafer, the test site comprising representative primitive device models for each of the plurality of primitive device model types, and wherein the plurality of primitive device model types comprises both nmos and pmos short-wide, long-wide, and long-narrow sized CMOS primitive device structures; and the key electrical metrics comprise a drain-source saturation region current metric, a threshold voltage metric, and a maximum gain metric for each of the primitive device types.