Patent ID: 8179178
Filing Date: 2012-05-15
Classification: H03K

Abstract:
1. A register circuit, comprising: a first level shift circuit which switches a first level shift node between a reference voltage level and an upper voltage level in response to a first clock node and a first input node; wherein said first clock node toggles between said reference voltage level and a lower voltage level, wherein said lower voltage level and said upper voltage level are both greater than said reference voltage level, and wherein said upper voltage level is greater than said lower voltage level; a first latch isolation circuit which isolates a first output node from said first input node when said first clock node is at said reference voltage level, and which asserts said first output node to one of said reference voltage level and said upper voltage level based on a state of said first input node when said first clock node is at said lower voltage level; and a first keeper circuit which maintains a state of said first output node when said first clock node is at said reference voltage level.