Patent ID: 7777823
Filing Date: 2010-08-17
Classification: G02F

Abstract:
1. A thin film transistor array panel comprising: a substrate; a first gate line disposed on the substrate; a second gate line disposed on the substrate and separated from the first gate line; a data line intersecting the first and second gate lines; a first thin film transistor connected to the first gate line and the data line; a second thin film transistor connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.