Patent ID: 6268257
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method, comprising:forming a gate insulation layer above a surface of a semiconducting substrate;forming a gate electrode above said gate insulation layer, said gate electrode having sidewalls;forming a cover layer above said gate electrode;forming a protective layer on said sidewalls of said gate electrode and said surface of said substrate;removing said cover layer;forming a first layer of refractory metal above said gate electrode and said protective layer;converting at least a portion of said first layer of refractory metal above said gate electrode to a first metal silicide region positioned above said gate electrode;removing said protective layer from above said surface of said substrate;forming a second layer of refractory metal above said first metal silicide region above said gate electrode and a source/drain region formed in said substrate; andconverting at least a portion of said second layer of refractory metal to a metal silicide region above said source/drain region.