Patent ID: 9048825
Filing Date: 2015-06-02
Classification: G11C,H03K

Abstract:
1. A semiconductor device comprising: a level shifter; a first buffer; and a second buffer, wherein the first buffer comprises a first transistor and a second transistor connected in series, wherein the second buffer comprises a third transistor and a fourth transistor connected in series, wherein the level shifter comprises a fifth transistor, a sixth transistor, and a seventh transistor connected in series and an eighth transistor, a ninth transistor, and a tenth transistor connected in series, wherein a gate of the second transistor, a gate of the third transistor, and a gate of the eighth transistor are electrically connected to each other, wherein a gate of the first transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected each other, wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a connection portion of one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, and wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to a connection portion of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, and wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the tenth transistor are n-channel transistors.