Patent ID: 6064364
Filing Date: 2000-05-16
Classification: G09G

Abstract:
A scanning circuit for use in an image display device comprising a decoder for outputting scanning pulses according to 2m pulse signals, each of the pulse signals being formed by m signals and m inverted signals which are the inverse of the m signals, said decoder including first to lth decoding sections for sequentially outputting the scanning pulses to l lines of output signal lines where l satisfies a condition of l.ltoreq.2.sup.m,wherein each of said decoding sections comprises a first transistor, and second to (m+1)th transistors having a channel including majority carriers of a type different from that of majority carriers of said first transistor,drains and sources of said first to (m+1)th transistors are connected in series,the scanning pulses are output from a junction between said first and second transistors,a reset signal is input to a gate of said first transistor, the reset signal switching on said first transistor when the pulse signal is switched from a high level to low level or from low level to high level, andthe pulse signals are input to gates of said second to (m+1)th transistors.