Patent ID: 6117692
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method of forming a silicon layer having hemispherical grains thereon on a microelectronic substrate in a reaction chamber including a heater and using a process reaction recipe, said method comprising the steps of:calibrating a heater temperature so that a process temperature is maintained when the microelectronic substrate is subsequently heated despite a number of processing runs previously performed, wherein said calibrating step comprises the steps of:loading a test substrate into the reaction chamber,subjecting the test substrate to the process reaction recipe wherein the test substrate is heated according to the process reaction recipe,measuring the temperature of the test substrate while heating the test substrate according to the process reaction recipe, wherein the temperature of the test substrate is measured while a source gas including silicon is injected in to the reaction chamber according to the process reaction recipe;removing the test substrate from the reaction chamber, andadjusting the heater temperature according to the measured temperature of the test substrate, wherein the heater temperature is adjusted by adjusting a current to the heater in response to a calibration value obtained by comparing the measured temperature of the test substrate with a calibration factor of the heater temperature;after calibrating the heater temperature, loading the microelectronic substrate into the reaction chamber;after loading the microelectronic substrate into the reaction chamber, forming a hemispherical grained silicon seed layer on the microelectronic substrate according to the process reaction recipe; andafter forming the hemispherical grained silicon seed layer on the microelectronic substrate, annealing the hemispherical grained silicon seed layer to form a hemispherical grained silicon layer according to the process reaction recipe.