Patent ID: 6768676
Filing Date: 2004-07-27
Classification: G11C

Abstract:
An electrically writable and erasable nonvolatile semiconductor memory device composed of one or more chips and having memory cells respectively constituted by a floating gate field effect transistor including a control gate, a drain, a source and a floating gate, wherein charged states corresponding to three or more values are generated in the floating gate, comprising:write means that, at the time of write operation for generating one of two or more charged states of the floating gate corresponding to two or more values, performs a first step of applying a write pulse being a positive write start voltage to the control gate, and thereafter repeatedly performs a second step of applying a write pulse to the control gate of the transistor of a memory cell which is not judged to be in a predetermined charged state, wherein the write pulse in the second step is repeatedly raised by a voltage increment until the transistor of the memory cell becomes the predetermined charged state, wherein a voltage increment setting means for setting the voltage increment in the second step for each chip.