Patent ID: 6309929
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method of fabricating trench MOS devices and termination structure simultaneously, said method comprising the steps of:providing a semiconductor substrate;forming a plurality of first trenches for forming said trench MOS devices in an active region of a semiconductor substrate, and a second trench for forming said termination structure from a boundary of said active region to a margin of said semiconductor substrate, said second trench and said first trench spaced by a mesa;performing a thermal oxidation process so as to form a gate oxide on all areas of said semiconductor substrate;refilling said plurality of first trenches and said second trench with a first conductive material;performing an etching back process using a surface of said semiconductor substrate of said mesa as a stopping layer, and forming a spacer on a sidewall of said second trench;removing said gate oxide layer using said surface of said semiconductor substrate of said mesa as a stopping layer;forming a termination structure oxide layer on all areas of said semiconductor substrate;forming a photoresist pattern on said termination structure oxide layer to define an insulating region and to expose a region from said active region to said spacer;etching away said exposed region using said photoresist pattern as a mask;stripping said photoresist pattern;removing backside unnecessary layers of said semiconductor substrate so as to expose said semiconductor substrate;forming a second conductive material on all areas of said semiconductor substrate;forming a photoresist pattern on said second conductive material so as to define an electrode; andetching away exposed portion of said second conductive material so that said electrode is formed.