Patent ID: 9177665
Filing Date: 2015-11-03
Classification: G11C

Abstract:
1. A write and read circuit for anti-fuse non-volatile memory used for treating a bit-writing operation and/or a bit-reading operation to a NOI (non-overlapped implementation) MOSFET device, wherein the NOI MOSFET device at least has a NOI gate side, a NOI drain side and a NOI source side, and the write and read circuit comprising: a bit-writing unit, being coupled to the NOI drain side for writing at least one memory bit into the NOI MOSFET device; a bit-reading unit, being coupled to the NOI drain side for reading the memory bit out from the NOI MOSFET device, so as to output a bit signal; a charging unit, being coupled to the NOI drain side, the bit-writing unit, the bit-reading unit, and a first bias voltage, wherein the charging unit couples the first bias voltage to the NOI drain side according to the control of a read/write command signal inputted by an external terminal; a discharge unit, being coupled to the NOI source side of the NOI MOSFET device; and a control unit, being coupled to the discharge unit and receiving the read/write command signal and the bit signal, so as to output a control signal to the discharge unit for making the NOI MOSFET device discharge via the discharge unit.