Patent ID: 8739100
Filing Date: 2014-05-27
Classification: G03F,G06F,H01L,H03B,H03K

Abstract:
1. A non transitory computer readable media for designing VLSI devices, comprising computer readable instructions to accomplish: (a) laying out a bounded skew routed clock tree distribution conductor pattern for incorporation on a semiconductor die; (b) applying a buffered clock root driver to a top level of said tree so as to enable a clock voltage swing from 0 to V (c) searching over a set of discrete resistances from said clock root driver by adding and sizing a level of LC tanks to said tree, wherein each LC tank is sized at its location so as to produce a predetermined resonant frequency using the distributed capacitances and conductor resistances at each location; and (d) simulating each LC tank using AC analysis to verify said predetermined resonant frequency and a predetermined clock voltage swing at each location.