Patent ID: 8176262
Filing Date: 2012-05-08
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a plurality of processing units, at least one of which is configured to be switchable between an active power state and a dormant power state; a memory shared between said plurality of processing units, each processing unit being configured to issue a memory access request when said processing unit requires access to a data item stored in said memory; at least one local storage unit, each local storage unit being associated with one of said plurality of processing units and being configured to store a local copy of a data item stored in said memory for access by its associated processing unit; and a snoop control unit configured to monitor memory access requests issued by said plurality of processing units and to store indications of local copies of data items stored in each local storage unit, wherein said snoop control unit is configured, on detection of a memory access request for a requested data item issued by a first processing unit of said plurality of processing units, to reference said indications and, when an indication of said requested data item corresponding to another processing unit of said plurality of processing units is found, said other processing unit is currently in said dormant power state and a cache coherency protocol requires that the local copy of said requested data item stored in the local storage unit associated with said other processing unit be invalidated, to store a marker indicating that the local copy of said requested data item stored in the local storage unit associated with said other processing unit should be later invalidated.