Patent ID: 6656786
Filing Date: 2003-12-02
Classification: H01L,Y10S

Abstract:
A method for manufacturing a capacitor for utilization with a logic-based DRAM device, said method comprising the steps of:providing a substrate; forming at least one transistor, an interlayer dielectric, at least one contact and at least one first metal layer on said substrate during a front end manufacturing operation of said capacitor on said substrate; thereafter depositing an inter-metal dielectric layer upon said substrate, followed thereafter by a chemical mechanical polishing operation; thereafter forming at least one dielectric deposition layer on said substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on said substrate; and thereafter forming at least one second metal layer on said substrate and associated layers thereof, thereby resulting in the formation of a capacitor fully compatible with logic-based devices and processes thereof, while alleviating process incompatibility.