Patent ID: 6266802
Filing Date: 2001-07-24
Classification: G06F

Abstract:
An apparatus for implementing a wiring layout, comprising:at least one processor having a memory;a logic model, stored in the memory of the processor, wherein the logic model comprises a grid model for each of a plurality of grid points that includes a cost model, the cost model comprising a plurality of programmable constraints associated with each grid point; anda routing tool, stored in the memory of the processor, for executing each grid model of the logic model in parallel to identify a plurality of non-overlapping interconnects from a starting grid point to a destination grid point, the routing tool determining for each grid point in the logic model where an input came from and where an output went to, disabling input lines to a grid point to preclude further input lines becoming associated with the grid point, selecting at least one interconnect according to the cost model and tracing back through the selected interconnect to record a path for the selected interconnect.