Patent ID: 7971161
Filing Date: 2011-06-28
Classification: G06F,Y02D

Abstract:
1. A method for implementing speculative clock gating of digital logic circuits included in a multiple stage pipeline design, the method comprising: generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage wherein the generating is performed using a computer system.