Patent ID: 8964450
Filing Date: 2015-02-24
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory circuit comprising a first transistor and a capacitor; a logic circuit comprising a second transistor, a third transistor, a fourth transistor, and a fifth transistor; and a control circuit comprising a sixth transistor and a seventh transistor, wherein a first terminal of the first transistor is electrically connected to one electrode of the capacitor, wherein a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor, a gate of the fourth transistor, a gate of the fifth transistor, and a gate of the sixth transistor, wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor, a first terminal of the sixth transistor, and a first terminal of the seventh transistor, wherein the first terminal of the sixth transistor is directly connected to the first terminal of the seventh transistor, wherein a second terminal of the sixth transistor is directly connected to a second terminal of the seventh transistor, wherein a second terminal of the third transistor is electrically connected to a first terminal of the fifth transistor, and wherein a gate of the second transistor and a gate of the third transistor are electrically connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor.