Patent ID: 8174050
Filing Date: 2012-05-08
Classification: H01L

Abstract:
1. A method for fabricating a transistor, comprising the steps of: (A) forming a high mobility layer, wherein said high mobility layer is configured to carry a two-dimensional electron gas; (B) forming a planar layer in contact with said high mobility layer, wherein said planar layer has a uniform composition; (C) forming a barrier layer in contact with said planar layer; (D) forming a doped layer in contact with said barrier layer, said doped layer (i) comprising a low bandgap III-V semiconductor and (ii) having a first surface that is doped; (E) forming a source and a drain in contact with said first surface of said doped layer; and (F) forming a gate in contact with said first surface of said doped layer, wherein (i) said gate is separated from both said source and said drain by corresponding ungated recess regions on said first surface of said doped layer and (ii) said high mobility layer, said planar layer, said barrier layer, said doped layer, said source, said gate and said drain are configured as a pseudomorphic high electron mobility transistor.