Patent ID: 7293185
Filing Date: 2007-11-06
Classification: G06F

Abstract:
1. A clock control circuit carrying out control of a clock signal supplied to a central processing unit, the clock control circuit comprising: a high-speed clock source whose oscillation operation is controlled by an operation control signal, and which generates a high-speed clock used in a usual operation mode; a low-speed clock source generating a low-speed clock whose frequency is lower than a frequency of the high-speed clock; a selector selecting one of the high-speed clock and the low-speed clock in accordance with a selection signal, and outputting the selected one of the high-speed clock and the low-speed clock to the central processing unit; a first control section that outputs the operation control signal for stopping the high-speed clock source responsive to a standby mode designated by a mode signal, that outputs the operation control signal for operating the high-speed clock source responsive to an interrupt signal, and that sets initial states of the central processing unit and causes the high-speed clock to be generated by the high-speed clock source a set time after a power source has been turned on, responsive to a reset signal; and a second control section which, when the standby mode is designated by the mode signal, outputs the selection signal for causing the low-speed clock to be selected, and which, when the interrupt signal is supplied, starts counting of the low-speed clock, and when a count value reaches a value set in a register, the second control section outputs the selection signal for causing the high-speed clock to be selected.