Patent ID: 6088701
Filing Date: 2000-07-11
Classification: G06F,G09G,Y10S

Abstract:
A computer based method for operation on a computer having a memory buffer, a graphics processor, and a processor capable of reordering write operations of data and for ensuring the graphics processor receives the data sequentially, comprising the steps of:(a) initializing a minimum address and a maximum address to an address larger than the address to be received by the write operation;(b) initializing a holes value to an initialization value;(c) receiving a signal representing a received address and received data, said received data to be written to the memory buffer at said received address;(d) setting said holes value equal to the holes value plus the received address minus said maximum address minus one if said address is greater than said maximum address;(e) setting said holes value equal to the holes value minus one if said address is greater than or equal to said minimum address;(f) transmitting a signal indicating that all data having an address that is less than the maximum address has been received if said holes value is equal to initialization value; and(g) repeating steps (c)-(f);wherein said holes value is dependent upon only the number of addresses between the minimum address and the maximum address that have not been received.