Patent ID: 8265070
Filing Date: 2012-09-11
Classification: H04L,H04Q

Abstract:
1. A system for implementing a multistage network, comprising: a first tile comprising a processor, a first top brick operatively connected to the processor, a first bottom brick, and a first intermediate brick; a second tile comprising a second intermediate brick and a second bottom brick; a first plurality of connections operatively connecting the first top brick with the second intermediate brick and the first intermediate brick with the second bottom brick using a passthrough on an intermediate tile between the first tile and the second tile, wherein the first tile, the intermediate tile, and the second tile are positioned in a row of a two-dimensional array; and a third tile comprising a cache operatively connected to a third bottom brick, wherein the second tile and the third tile are positioned in a column of the two-dimensional array, wherein the first bottom brick, the second bottom brick, and the third bottom brick are different bricks, and are associated with a bottom layer of the multistage network linking the processor and the cache, and wherein the first intermediate brick and the second intermediate brick are associated with an intermediate layer of the multistage network.