Patent ID: 6093590
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of fabricating a transistor, comprising:forming a first dielectric layer with a high dielectric constant on a substrate;forming an oxide layer on the first dielectric layer;forming a silicon nitride layer on the oxide layer;patterning the silicon nitride layer, the oxide layer, and the first dielectric layer to form a dummy gate structure;forming a spacer on a sidewall of the dummy gate structure, wherein the spacer and the dummy gate structure together form a dummy gate;performing an ion implantation step with the dummy gate serving as a mask and performing a thermal annealing step to form a source region and a drain region on opposite sides of the dummy gate in the substrate;forming a second dielectric layer next to the spacer, wherein a top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure;removing the silicon nitride layer of the dummy gate structure;performing a nitridation process to convert the oxide layer into a nitride layer;forming a metal barrier layer over the substrate to cover the second dielectric layer, the spacer, and the nitride layer;forming a metal layer on the metal barrier layer; andperforming a planarization process to remove a portion of the metal layer and the metal barrier layer to form a metal gate, wherein a top surface of the metal gate is level with a top surface of the second dielectric layer.