Patent ID: 7923309
Filing Date: 2011-04-12
Classification: G02F,H01L

Abstract:
1. A method for manufacturing a thin film transistor array substrate comprising: forming gate lines, gate electrodes and a gate pad pattern at an end of each gate line on a substrate with a first mask depositing a gate insulating layer, a semiconductor formation layer, and a data metal layer on a surface of the substrate including the gate lines and the gate electrodes; removing at least part of the data metal layer, the semiconductor formation layer, and the gate insulating layer to have same openings with a second mask, to form data lines extending substantially perpendicular to the gate lines and a data pad pattern at an end of each data line; depositing a transparent electrode layer over a surface of the substrate including the data lines; removing at least part of the transparent electrode layer, the data metal layer, and the semiconductor formation layer to a predetermined depth from regions corresponding to channels of the semiconductor layer formation region with a third mask; and patterning predetermined portions of pixel regions to form a semiconductor layer on the semiconductor formation layer, source and drain electrodes on the data metal layer, a pixel electrode coupled with the drain electrode on the transparent electrode, a gate pad terminal coupled with the gate pad pattern and a data pad terminal on the data pad pattern such that the gate pad terminal and the data pad terminal are disposed on the same layer as the pixel electrode.