Patent ID: 6362992
Filing Date: 2002-03-26
Classification: G11C

Abstract:
A content addressable memory (CAM), comprising:an input bus able to receive a data signal including a plurality of data bits; an array block having a plurality of CAM cells each including: a first storage location into which a content bit can be stored; a second storage location into which either a content bit or a mask bit can be stored; a comparator logic cell having inputs connected to each of said input bus, said first storage location, and said second storage location; said comparator logic cell being able to generate a bit signal based on comparison in two-bit binary manner of two said data bits and said content bits in each of said first storage location and said second storage location, when operation is desired in a binary mode; and said comparator logic cell further being able to generate said bit signal based on comparison in one-bit ternary manner of one said data bit with said content bit in said first storage location and said mask bit in said second storage location, when operation is desired in a ternary mode; a match detection block able to receive said bit signals from said array block and to generate there from a plurality of match signals; and a priority encoder block able to receive said plurality of match signals and to generate there from a result signal at a result output.