Patent ID: 6285625
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A semiconductor memory device, comprising:an array of memory cells including a plurality of memory cells disposed in rows and columns;a column select circuit coupled between the array of memory cells and a plurality of data input/outputs (I/Os), the column select circuit providing access to selected columns of the array of memory cells by way of the I/Os, the column select circuit being enabled in synchronism with a single internal control clock signal; anda clock circuit that receives a first differential system clock signal and a second differential system clock signal that is complementary to the first clock signal, and generates the single internal control clock signal, the single internal control clock signal having a first logic value when the first differential system clock signal is greater than the second differential system clock signal, and a second logic value when the first differential system clock signal is less than the second differential system clock signal, wherein the single internal control clock signal substantially compensates for any degradation in the first and second differential system clock signals.