Patent ID: 8867279
Filing Date: 2014-10-21
Classification: G11C

Abstract:
1. A flash memory apparatus, comprising: at least one flash memory array block, the flash memory array block comprises: N storage columns, each of the storage column comprises a plurality of memory cells coupled in serial, each of the memory cells coupled to a word line, a control line and a bit line, wherein N is a positive integer; N reference word-line cell units, each of the reference word-line cell units disposed in each of the storage columns and located in a central portion of the flash memory array block, and each of the reference word-line cell units coupled to the memory cells in the corresponding storage column, wherein, the reference word-line cell units further coupled to a reference word line, a reference control line and a dummy word line; and a reference storage column, the reference storage column is disposed neighbor to the storage columns, the reference storage column comprises a plurality of reference bit-line cells coupled in serial, the reference bit-line cells coupled to the word lines, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line, wherein when a control circuit is configured to control the flash memory apparatus to operate in a data read mode, a voltage level on the reference control line is a first voltage, and the first voltage is different from a second voltage on each control line of the N storage columns, wherein a current level on the reference bit line is between a logical “0” current level and a logical “1” current level; and a sense amplifying module, the sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.