Patent ID: 8441043
Filing Date: 2013-05-14
Classification: B82Y,H01L,Y10S

Abstract:
1. A device comprising: a first pad; a second pad; a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads; a gate surrounding the nanowires; a dielectric between the gate and the nanowires; and spacers adjacent to the gate, wherein the device comprises a field-effect transistor (FET) where portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.