Patent ID: 7687337
Filing Date: 2010-03-30
Classification: H01L

Abstract:
1. A method comprising: providing a semiconductor layer; forming a control electrode of a transistor overlying the semiconductor layer; removing a portion of the semiconductor layer lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode; forming a first stressor within the first recess, the first stressor having a first in-situ current electrode doping profile; forming a second stressor within the second recess, the second stressor having the first in-situ current electrode doping profile; forming a third stressor overlying the first stressor, the third stressor having a second in-situ current electrode doping profile that has a higher first conductivity type current electrode doping concentration than the first in-situ current electrode doping profile; and forming a fourth stressor overlying the second stressor, the fourth stressor having the second in-situ current electrode doping profile; wherein a first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively; forming a sidewall spacer adjacent the control electrode, wherein the sidewall spacer overlies a portion of the first stressor, a portion of the second stressor, a portion of the third stressor, and a portion of the fourth stressor; wherein the first current electrode includes an extension region; wherein the second current electrode includes an extension region; wherein the extension region of the first current electrode includes a portion of the third stressor; wherein the extension region of the second current electrode includes a portion of the fourth stressor.