Patent ID: 6424198
Filing Date: 2002-07-23
Classification: G06F,G11C

Abstract:
A memory clock generation logic circuit comprising:a configuration register configured for generating configuration register bits and driven by a memory controller internal clock signal; a first programmable delay configured for receiving a double-speed clock signal and generating from the double-speed clock signal a phase-delayed double-speed clock signal and connected to the configuration register for receiving a first part of the configuration register bits from the configuration register, the amount of the phase delay of the double-speed clock signal being determined by the first part of the configuration register bits received by the first programmable delay; a second programmable delay connected to a first flip-flop (FF) for receiving a phase synchronization load signal through the first FF and to the configuration register for receiving the first part of the configuration register bits from the configuration register, the second programmable delay outputting a phase-delayed phase synchronization load signal, the amount of the phase delay of the phase synchronization load signal being determined by the first part of the configuration register bits, the first FF being driven by the memory controller internal clock signal; and a state machine connected to the second programmable delay for receiving the phase-delayed phase synchronization load signal from the second programmable delay, and having its output connected to the input of a second FF, the state machine being driven by the phase-delayed double-speed clock signal, the second FF being driven by an XOR gate receiving the phase-delayed double-speed clock signal from the first programmable delay and a second part of the configuration register bits from the configuration register, the second FF being configured for outputting a generated memory clock signal.