Patent ID: 7342991
Filing Date: 2008-03-11
Classification: G11C

Abstract:
1. A shift register circuit having a cascade of shift registers, comprising: a first transistor having a gate, a first source/drain and a second source/drain, wherein the gate and the first source/drain of the first transistor are coupled to an output signal of a pre-stage shift register; a second transistor having a gate, a first source/drain and a second source/drain, wherein the gate of the second transistor is coupled to the first source/drain of the first transistor, and the second source/drain of the second transistor is coupled to a low voltage level; a third transistor having a gate, a first source/drain and a second source/drain, wherein the gate of the third transistor is coupled to the first source/drain of the second transistor, the first source/drain of the third transistor is coupled to the second source/drain of the first transistor, and the second source/drain of the third transistor is coupled to the low voltage level; a fourth transistor having a gate, a first source/drain and a second source/drain, wherein the gate of the fourth transistor is coupled to the second source/drain of the first transistor, the first source/drain of the fourth transistor is coupled to a first clock signal, and the second source/drain of the fourth transistor is coupled to a first output; a sixth transistor having a gate, a first source/drain and a second source/drain, wherein the gate and the first source/drain of the sixth transistor are coupled to a high voltage level; a seventh transistor having a gate, a first source/drain and a second source/drain, wherein the first source/drain of the seventh transistor is coupled to the second source/drain of the sixth transistor, and the second source/drain of the seventh transistor is coupled to the low voltage level; a eighth transistor having a gate, a first source/drain and a second source/drain, wherein the gate and the first source/drain of the eighth transistor is coupled to the high voltage level; and a ninth transistor having a gate, a first source/drain and a second source/drain, wherein the first source/drain of the ninth transistor is coupled to the second source/drain of the eighth transistor, the second source/drain of the ninth transistor is coupled to the low voltage level, and the gates of the seventh and ninth transistors are coupled to the first output.