Patent ID: 6750677
Filing Date: 2004-06-15
Classification: H03K

Abstract:
A semiconductor integrated circuit, comprising:a NOR dynamic circuit for receiving clock and a plurality of first data, holding a charge of a first output node in a case where during one of a period from rising to falling of the clock and a period from falling to rising of the clock, the first output node is charged, and during the other period, all the plurality of first data are matched with each other, and discharging the first output node in a case where at least one of the plurality of first data is not matched; a NAND dynamic circuit for receiving the clock and a signal from the first output node, holding a charge of a second output node in a case where during one of a period from rising to falling of the clock and a period from falling to rising of the clock, the first output node is discharged, and discharging the second output node in a case where the charge of the first output node is held; and a compensating circuit for compensating for a voltage drop of the first output node, which is caused by a coupling capacitance formed between the first output node and the second output node, which occurs when the second output node is discharged while the charge of the first output node is held, wherein the compensating circuit includes a feedback circuit for charging the first output node in a case where the second output node is discharged, and the compensating circuit comprises: an inverter in which an input terminal is connected to a second output node of the NAND dynamic circuit; and a MOS transistor in which a gate is connected to an output terminal of the inverter, and a source and a drain are connected in common to the first output node of the NOR dynamic circuit.