Patent ID: 6091651
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A semiconductor memory device formed on a main surface of a semiconductor substrate, comprising:a first memory cell for storing first data that takes one of first and second logical values;a word line for selecting said first memory cell;a first bit line pair for transmitting said first data to said first memory cell;a first bus line pair for transmitting said first data to said first bit line pair,said first bus line pair including:a first bus line to attain a first potential when said first data takes said first logical value, and a second potential lower than said first potential when said first data takes said second logical value, anda first complementary bus line to attain a potential complementary to said first bus line in response to said first data;a second memory cell selected in response to an activation of said word line for storing second data that takes one of said first and second logical values;a second bit line pair for transmitting said second data to said second memory cell;a second bus line pair for transmitting said second data to said second bit line pair,said second bus line pair including,a second bus line to attain said first potential when said second data takes said first logical value, and said second potential when said second data takes said second logical value, anda second complementary bus line to attain a potential complementary to said second bus line in response to said second data,at least a part of said second bus line intersecting said first and second bit line pairs lying between said first and second complementary bus lines on said semiconductor main surface;one data terminal; andtest control means for controlling a test operation to read/write data from/to said first memory cell and said second memory cell through said data terminal in response to an externally applied instruction,said test control means transmitting data externally applied to said data terminal to one of said first and second bus line pairs in a normal operation and to both said first and second bus line pairs in a test operation.