Patent ID: 7180130
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. A semiconductor device having a MISFETs forming region and a gate lead-out region on a main surface of a semiconductor substrate, comprising: a plurality of first trenches in said semiconductor substrate in said MISFETS forming region; a plurality of gate oxide films of said MISFETs formed in said plurality of first trenches; a plurality of gate electrodes of said MISFETs formed on said plurality of gate oxide films; a second trench formed in said gate lead-out region, said second trench being perpendicular to the first trenches; a gate lead-out electrode formed in said second trench and outside the second trench in said gate lead-out region, wherein said gate lead out region is located in a peripheral region of the main surface of said semiconductor substrate; said gate lead-out electrode and gate electrodes are comprised of a same material; said second trench is connected at an end portion of each of said first trenches; said first trenches are terminated by said second trench; and said plurality of gate electrodes are connected with said gate lead-out electrode.