Patent ID: 8977788
Filing Date: 2015-03-10
Classification: G06F

Abstract:
1. A System On Chip (SOC) device comprising: a first component coupled to a second component via an internal link, wherein the first and second components are to communicate via the internal link without use of any analog front ends; and logic to enable communication between the SOC device and an external link coupled to the SOC device, wherein the logic is to comprise a test controller to cause monitoring of operations of one or more components of the SOC device or cause monitoring of communications between the one or more components of the SOC device in response to a command, wherein the test controller is to cause selection of input signals of a first multiplexer and a second multiplexer, the first multiplexer having a first input coupled to a transmit portion of the internal link and a second input coupled to a receive portion of the internal link, the second multiplexer having a first input coupled to an output of the first multiplexer and a second input coupled to the external link.