Patent ID: 6051461
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A method for manufacturing a memory integrated circuit comprising the steps of:providing a semiconductor substrate of a first conductivity type;forming a field oxide film on portions of the semiconductor substrate, wherein other portions of the semiconductor substrate without field oxide formed thereon form a plurality of active regions, each having an H-shape;forming word lines passing through the active regions of the semiconductor substrate, selected word lines for connection to global word lines;forming sources and drains of a second conductivity type in active regions exposed between the word lines;forming a first insulating film on the semiconductor substrate on which transistors comprising the sources, the drains and the word lines are formed;removing the first insulating film so as to expose portions of word lines unconnected to global word lines, and the drains; andforming bit lines connected to the exposed drains, and strapping word lines connected to the word lines unconnected to the global word lines, simultaneously.