Patent ID: 6445618
Filing Date: 2002-09-03
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array divided into blocks, each of said blocks including memory cells, word lines and bit lines being connected to these memory cells, and a row decoder for selecting said word lines; a first decoder for supplying the voltage supplied to said word lines to said row decoder; a second decoder for supplying a substrate voltage to a substrate in which said memory cells are formed; a first switch circuit which is connected between a first node to which said substrate voltage is supplied and a second node to which the voltage on said word line is supplied, said first and second nodes being connected to each other via a parasitic capacitance; a second switch circuit which is connected between said second node and the output terminal of said first decoder; and a third switch circuit which is connected between said first node and the output terminal of said second decoder.