Patent ID: 6686282
Filing Date: 2004-02-03
Classification: H01L

Abstract:
A method of providing gates for transistors comprising:providing a gate dielectric layer overlying a substrate; providing a first seed layer overlying the gate dielectric layer; forming a first metal layer having a first work function over said first seed layer by using plating; removing a portion of the first metal layer and the first seed layer; forming a second seed layer overlying the gate dielectric layer; forming a second metal layer having a second work function different from the first work function and over at least a portion of said second seed layer by using plating; forming a conductive gate material overlying both the first metal layer and the second metal layer; and forming a first gate stack and a second gate stack by removing a portion of each of the conductive gate material, the first metal layer, the second metal layer, the first seed layer and the second seed layer, the first gate stack retaining a first portion of the first seed layer and the second seed layer while the second gate stack retains only a second portion of the first seed layer.