Patent ID: 6468858
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method of fabricating a metalâ€”insulatorâ€”metal (MIM), capacitor structure on a semiconductor substrate, comprising the steps of:providing a conductive plug structure, located in an opening in a first interlevel dielectric (ILD), layer, overlying and contacting a source/drain region of a transfer gate transistor; forming a composite landing pad structure on said first ILD layer, and on the top surface of said conductive plug structure, with said composite landing pad structure comprised with an overlying ruthenium layer; depositing a second ILD layer, and an overlying silicon nitride layer; forming a storage node contact hole in said silicon nitride layer, and in said second ILD layer, exposing a portion of the top surface of said ruthenium layer; forming a platinum plug structure in said storage node contact hole; forming a capacitor opening in a third ILD layer, exposing the top surface of said platinum plug structure, located at the bottom of said capacitor opening; forming silicon nitride spacers on the sides of said capacitor opening; forming a metal storage node structure on exposed surfaces of said capacitor opening, overlying and contacting the top surface of said platinum plug structure; forming a high dielectric constant (high k), layer on said metal storage structure; and forming a metal top plate structure on said high k layer, resulting in said MIM capacitor structure comprised of said metal top plate structure, said high k layer, and said metal storage node structure.