Patent ID: 7142183
Filing Date: 2006-11-28
Classification: G09G

Abstract:
1. A liquid crystal display comprising: a liquid crystal panel including a plurality of pixels at intersecting areas of a plurality of gate lines and a plurality of data lines; a gate driver for applying a signal to sequentially scan the gate lines of the liquid crystal panel; a source driver for selecting and outputting a gray voltage to be applied to each of the pixels based on image data; and a timing controller including a DCC processing unit for applying dynamic capacitance compensation (“DCC”) to a part of the pixels, a timing redistribution block for converting a format of the DCC-applied data to a predetermined format for the source driver, and a control signal generating block for generating a control signal for displaying an image, wherein the pixels are arranged in rows and columns at the intersecting areas of the gate lines and data lines, and wherein the DCC processing unit applies the DCC to odd data for odd pixels in odd rows of the rows and to even data for even pixels in even rows of the rows, and wherein the DCC processing unit comprises: a distributor for receiving the pixels of a current frame and outputting DCC-transforming pixel data of the pixels to a DCC block and DCC-untransforming pixel data of the pixels to a bypass block, based on row parity information of the pixels; the DCC block for comparing the gray value of the DCC-transforming pixel data of the pixels of the current frame with the gray value previous frame data to DCC-transform the DCC-transforming pixel data based on a difference between the gray values of the current frame data and the previous frame data; the bypass block for delaying the DCC-untransforming pixel data during the DCC transformation of the DCC-transforming pixel data in the DCC-block; a synthesizer for selecting one of outputs of the DCC block and the bypass block, based on the row parity information of the pixels and outputting the selected output as transformed data; a line counter for counting the rows of the pixels to provide the row parity information for the distributor and the synthesizer; first and second frame memories for storing the current frame data and the previous frame data, respectively; and a memory controller for receiving the DCC-transforming pixel data form the distributor and storing the pixel data in the first frame memory as the current flame data and for transmitting the previous frame data stored in the second frame memory to the DCC block.