Patent ID: 9071265
Filing Date: 2015-06-30
Classification: H03M

Abstract:
1. An analog-to-digital converter (ADC), comprising: a plurality of capacitors having first terminals for receiving an analog input signal during a sampling cycle of an analog-to-digital conversion cycle, and corresponding second terminals connected to a first node, wherein the plurality of capacitors comprise a first set of capacitors that generate a first set of voltage signals at the first node during a first set of comparison cycles of a plurality of comparison cycles of the analog-to-digital conversion cycle, an error-detection capacitor that generates an error-detection signal at the first node during an error-detection comparison cycle of the plurality of comparison cycles, and a second set of capacitors that generate a second set of voltage signals at the first node during a second set of comparison cycles of the plurality of comparison cycles; a comparator having a first input terminal connected to the first node for receiving the first set of voltage signals at the end of the first set of comparison cycles, the second set of voltage signals at the end of the second set of comparison cycles, and the error-detection voltage signal at the end of the error-detection comparison cycle, a second input terminal for receiving a common-mode voltage signal, and an output terminal for outputting a first set of control signals at the end of the first set of comparison cycles, an error-detection control signal at the end of the error-detection comparison cycle, and a second set of control signals at the end of the second set of comparison cycles; and a successive-approximation register (SAR) logic circuit, connected to the output terminal of the comparator, that generates a first set of bits corresponding to the first set of voltage signals by performing a first successive approximation using the first set of control signals, compensates for an error in the first set of bits based on the error-detection control signal, and generates a second set of bits corresponding to the second set of voltage signals by performing a second successive approximation using the second set of control signals, wherein the first and second sets of bits correspond to a binary representation of the analog input signal.