Patent ID: 7279929
Filing Date: 2007-10-09
Classification: H03K

Abstract:
1. An integrated circuit, comprising: a plurality of substantially similar programmable tiles, each tile comprising a logic block, segments of a plurality of interconnect lines interconnecting the programmable tiles one to another, and a plurality of programmable structures directly coupled to the segments of the interconnect lines, at least a subset of the programmable structures being further directly coupled to the logic block in each tile, the tiles being arranged in rows and columns, wherein: each of a first plurality of the interconnect lines is directly coupled to a first two of the programmable structures included in two tiles located in a first row; each of a second plurality of the interconnect lines is directly coupled to a second two of the programmable structures included in two tiles located in a first column; and each of a third plurality of the interconnect lines is directly coupled to a third two of the programmable structures included in two tiles located in different columns and in different rows, each of the third two of the programmable structures further being directly coupled to at least one other interconnect line, the at least one other interconnect line being selected from a group consisting of the first, second, and third pluralities of the interconnect lines.