Patent ID: 6125055
Filing Date: 2000-09-26
Classification: G11C

Abstract:
A simultaneous operation flash memory capable of write protecting predetermined sectors, comprising:a plurality of sectors divided into an upper bank and a sliding lower bank, wherein each said bank contains at least one sector;at least one upper address decoder circuit including a respective upper sector select line, wherein each said upper address decoder circuit generates a predetermined output signal on said upper sector select line when decoded;at least one lower address decoder circuit including a lower address sector select line, wherein each said upper address decoder circuit generates a predetermined output signal on said lower sector select line when decoded; andat least one write protect CAM electrically connected with a respective upper sector select line or a respective lower sector select line, wherein said write protect CAM generates a predetermined sector protect signal if said write protect CAM is selected by a signal from said respective upper sector select line or said respective lower sector select line.