Patent ID: 8972666
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. A computer system for mitigating conflicts for shared cache lines, the system comprising: an owning core that currently owns a cache line, a requestor core and a hardware-based reject threshold, the system configured to perform a method comprising: determining, by a processor, whether the owning core is operating in one of a transactional mode and a non-transactional mode; setting a hardware-based reject threshold at a first value when the owning core is determined to be operating in the transactional mode and a second value when the owning core is determined to be operating in the non-transactional mode; taking a first action to encourage sharing of the cache line between the owning core the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the first value when the owning core is determined to be operating in the transactional mode; and taking a second action, which is different from the first action, to encourage sharing of the cache line between the owning core and the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the second value when the owning core is determined to be operating in the non-transactional mode.