Patent ID: 6015984
Filing Date: 2000-01-18
Classification: H01L

Abstract:
A process for making embedded memory cells comprising the steps of:(a) forming a tunnel oxide layer on a substrate having a field oxide layer;(b) forming a first polysilicon (poly1) layer on said substrate covering said tunnel oxide layer;(c) forming a first poly1 photoresist on said poly1 layer, wherein said first poly1 photoresist is patterned to form a floating gate in a memory region of said poly1 layer and a bottom electrode in a capacitor region of said poly1 layer;(d) performing a first poly1 etch using said first poly1 photoresist so as to form said floating gate and said bottom electrode;(e) forming a second poly1 photoresist on said poly1 layer, wherein said second poly1 photoresist is patterned to reveal only said bottom electrode;(f) using said second poly1 photoresist to perform addition implantation in said bottom electrode;(g) forming an Oxide/Nitride/Oxide (ONO) layer on said substrate;(h) forming a second polysilicon (poly2) layer on said substrate covering said ONO layer;(i) forming a first poly2 photoresist on said poly2 layer, wherein said first poly2 photoresist is patterned to define a control gate in a memory region of said poly2 layer while covering at least said capacitor region of said poly2 layer;(j) using said first poly2 photoresist to perform a first poly2 etch to form said control gate, and removing said first poly2 photoresist;(k) forming a second poly2 photoresist on said poly2 layer, wherein said second poly1 photoresist is patterned to reveal only said top electrode;(l) using said second poly2 photoresist to perform a second poly2 etch and form said top electrode;(m) using said second poly2 photoresist to perform an ONO etch;(n) removing said poly2 photoresist and cleaning.