Patent ID: 9034744
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A method, comprising: forming first and second gate electrode structures of respective first and second transistors above respective first and second active regions of a semiconductor device, each of said first and second gate electrode structures comprising a placeholder material and a dielectric cap layer having a first thickness formed above said placeholder material; selectively reducing said thickness of said dielectric cap layer of said second gate electrode structure from said first thickness to a second thickness that is less than said first thickness; after selectively reducing said thickness of said dielectric cap layer of said second gate electrode structure, forming an etch stop layer above said first and second transistors; forming a sacrificial mask layer above said etch stop layer, wherein an upper surface of said sacrificial mask layer is at a height level relative to said first and second active regions that is above a height level of an upper surface of said dielectric cap layer of each of said first and second gate electrode structures; performing a material removal process to remove an upper thickness portion of said sacrificial mask layer from above said first and second transistors, wherein performing said material removing process comprises reducing said height level of said upper surface of said sacrificial mask layer to a height level that is below said upper surface of said dielectric cap layer of at least one of said first and second gate electrode structures so as to expose portions of said etch stop layer formed above said dielectric cap layer of each of said first and second gate electrode structures; exposing a surface of said placeholder material of each of said first and second gate electrode structures by performing a common etch process in the presence of a remaining lower thickness portion of said sacrificial mask layer to remove said exposed portions of said etch stop layer, and to remove said dielectric cap layer having said first thickness and said dielectric cap layer having said second thickness from said first and second gate electrode structures, respectively; removing an entirety of said remaining lower thickness portion of said sacrificial mask layer; after exposing said surface of said placeholder of each of said first and second transistors and removing said entirety of said remaining lower thickness portion of said sacrificial mask layer, forming a dielectric material layer above said semiconductor device, said dielectric material layer covering said first and second transistors; and removing a portion of said dielectric material layer from above said semiconductor device during a second common etch process, said second common etch process re-exposing said surface of said placeholder material of each of said first and second gate electrode structures.