Patent ID: 6033943
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A semiconductor process, comprising:providing a semiconductor wafer, wherein said semiconductor wafer includes a semiconductor substrate comprising a first region and a second region laterally displaced from said first region;forming a first dielectric layer on an upper surface of said semiconductor substrate, wherein said first dielectric layer has a first thickness;depositing a masking layer on said first dielectric layer;patterning said masking layer to expose said first dielectric layer above said second region of said semiconductor substrate;while retaining at least a portion of said first dielectric layer above the entirety of said second region, subjecting said semiconductor wafer to an oxygen bearing ambient at a temperature of approximately 700 to 1000.degree. C. such that a second dielectric layer is formed over said second region of said semiconductor substrate, wherein said second layer has a second thickness, and further wherein said second thickness is unequal to said first thickness;removing said masking layer from said upper surface of said first dielectric layer, subsequent to said subjecting;forming a first gate structure and a second gate structure on upper surfaces of said first dielectric layer and said second dielectric layer respectively; andintroducing impurities into a first and second pair of source/drain regions laterally displaced on either side of said first and second channel regions respectively whereby first and second transistors are formed, wherein said first dielectric layer serves as a gate dielectric for said first transistor and said second dielectric layer serves as a gate dielectric for said second transistor.