Patent ID: 6604176
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A memory system, comprising:a common memory region having a pair of control ports and a common DATA port; a switching network having a pair of information ports, for: coupling information having a control portion and a DATA portion between a first one of such pair of information ports and: a first one of pair of the control ports; and, the DATA port through a first switch section; and coupling information having a control portion and a DATA portion between a second one of said pair of information ports and: a second one of the pair of control ports; and, the DATA port though a second switch section; a pair of clocks, a first one of such clocks being fed to operate the first switch section in coupling the information through such first section and a second one of such clocks being fed to operate the second switch section in coupling the information through such first section.