Patent ID: 7765455
Filing Date: 2010-07-27
Classification: G06F,G11C,H03M

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells, and having a first area and a second area, the first area storing data, the second area storing a parity bit for error checking; a parity generation circuit which generates a parity bit with respect to first data including input data from an external source and a part of read data from the first area, each of the first data and the read data having a first number of data bits, the input data having a second number of data bits smaller than the first number of data bits; a syndrome generation circuit which generates a syndrome bit for correcting an error in the read data, based on the read data and the parity bit from the second area; a parity correction circuit which corrects the parity bit generated by the parity generation circuit, based upon the syndrome bit; and a data correction circuit which corrects the error included in the read data, based upon the syndrome bit, and forms corrected data, wherein a corrected parity bit and the corrected data are stored in the first area and the second area, respectively.