Patent ID: 6230238
Filing Date: 2001-05-08
Classification: G06F

Abstract:
An apparatus comprising:a processing unit;a first memory array coupled to the processing unit through a first bus interface unit;a second memory array coupled to the processing unit through a second bus interface unit;wherein the second bus interface unit contains logic that selectively accesses memory locations within the second memory array based upon: (1) a size of a data value being accessed; and (2) one or more low order bits of an address, so that aligned data values and mis-aligned data values stored within both the first and second memory arrays are accessed from the first and second memory arrays in substantially equal time intervals;wherein the first and second memory arrays can read and write in one of four modes, the four modes being: (1) a byte low mode wherein a byte of data is read exclusively from the first memory array; (2) a byte high mode wherein a byte of data is read exclusively from the second memory array; (3) an aligned multi-byte mode wherein a least significant byte is read from the first memory array and a more significant byte is read from the second memory array; and (4) an mis-aligned multi-byte mode wherein a more significant byte is read from the first memory array and a lesser significant byte is read from the second memory array;wherein the more significant byte and the lesser significant byte are swapped in position on a date bus that is used to read values from the first and second memory arrays.