Patent ID: 7589748
Filing Date: 2009-09-15
Classification: G06F,G06T,G09G,H01L,H04N

Abstract:
1. An image sensor, comprising: a timing controller for controlling an overall operation of the image sensor; a line memory for storing digital signals corresponding to a plurality of images in line unit; an image signal processor for processing the plurality of images by using the corresponding digital signal stored in the line memory so as to improve performance of the image sensor; and a scaler for generating a corresponding row/column address by calculating a scaling ratio according to a scaling factor of a desired image size from the timing controller, to scale the corresponding image, wherein the corresponding image of the desired size is outputted through a pre-scaler and a post-scaler coupled to each other in the image sensor and selectively executed according to the scaling ratio, wherein the scaler includes: wherein the post-scaler includes: a post-scaler address generator for receiving row/column addresses from the timing controller, pre-scaler row/column addresses, a pre-scaler valid signal, and a post-scaling ratio and generating post-scaler row/column addresses; first and second transmission gate for receiving the pre-scaler valid signal and inverted signal thereof through NMOS and PMOS gates and outputting pre-scaler image data and original image data, respectively; and a post-scaler data sampler for sampling the original image data or the pre-scaler image data through the post-scaler row/column addresses and outputting post-scaler image data.