Patent ID: 9075740
Filing Date: 2015-07-07
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a nonvolatile memory comprising a plurality of storage areas each including memory portions that each store one of a first data item and a second data item; a cache memory that temporarily stores data read from the nonvolatile memory; a control circuit that controls the nonvolatile memory and the cache memory, the control circuit comprising a counter that is configured to count the number of the first data items; and an interface circuit that communicates with a host, wherein the control circuit is configured to execute: a first determination in which it is determined whether data is written in each of the storage areas, counting a number of first data items stored in the memory portions in each of the storage areas; and a second determination in which the storage areas are sequentially read to determine a boundary between a first storage area in which data is written and a second storage area in which data is not written.