Patent ID: 7668983
Filing Date: 2010-02-23
Classification: G06F

Abstract:
1. A first-in-first-out (FIFO) data system, comprising: a FIFO memory that has a binary write pointer input, a binary read pointer input, a write data input, a write clock input, and a read data output, wherein the FIFO memory comprises a data structure of depth d from which data may be written into using the write data input and read out using the read data output, wherein d is not a value of 2 an output of a first set of flip flops coupled to an input of a first gray-to-binary converter, an input of a first gray-code generator, an input of a second set of flip flops, and an input of write clock logic that generates a first empty signal, a first full signal, and a first almost full signal; an output of the first gray-to-binary converter coupled to the binary write pointer input; an output of the first gray-code generator coupled to an input of the first set of flip flops; an output of the second set of flip flops coupled to an input of read clock logic that generates a second empty signal, a second full signal, and a second almost full signal; an output of a third set of flip flops coupled to an input of a second gray-to-binary converter, an input of a second gray-code generator, an input of a fourth set of flip flops, and the input of the read clock logic; an output of the second gray-code generator coupled to an input of the third set of flip flops; an output of the second gray-to-binary converter coupled to the binary read pointer input; and an output of the fourth set of flip flops coupled to the input of the write clock logic.