Patent ID: 8581410
Filing Date: 2013-11-12
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a wiring substrate including a plurality of build-up substrates stacked with one another, each of the plurality of build-up substrates having an insulating layer with through holes and conductive wirings, the wiring substrate having a first surface and a second surface opposite to each other; a semiconductor chip comprising a silicon substrate having a main surface and a rear surface opposite to each other, semiconductor elements on the main surface, insulating films over the semiconductor elements including a silicon oxide film and an interlayer dielectric film with a dielectric constant lower than that of the silicon oxide film, pad electrodes over the insulating films, and internal wiring layers electrically connecting to the semiconductor elements and the pad electrodes, the semiconductor chip being mounted on the wiring substrate via first bump electrodes such that the main surface of the silicon substrate faces the first surface of the wiring substrate, and such that the pad electrodes of the semiconductor chip are electrically connected to conductive wirings of a first one of the plurality of build-up substrates of the wiring substrate via the first bump electrodes, respectively; a resin layer between the semiconductor chip and the first one of build-up substrates and between the first bump electrodes; and second bump electrodes being on the second surface of the wiring substrate, and being electrically connected to conductive wirings of a second one of the plurality of build-up substrates of the wiring substrate, wherein each of the insulating layers of the plurality of build-up substrates contains glass cloths, respectively.