Patent ID: 9098259
Filing Date: 2015-08-04
Classification: G06F,Y02D

Abstract:
1. One or more non-transitory computer-readable storage media storing instructions that, when executed by a processor, cause the processor to perform acts comprising: while a secure digital input/output (SDIO) bus of an electronic device resides in a first mode, determining that an elapsed time since a last transfer of data over the SDIO bus of the electronic device coupled to a wireless network interface within the electronic device exceeds a time threshold; and causing the SDIO bus of the electronic device to enter a second mode at least partly in response to the determining the elapsed time since the last transfer of data over the SDIO bus exceeds the time threshold, wherein the wireless network interface within the electronic device is configured to maintain connectivity with an access point while the SDIO bus is in the second mode, the entering the second mode comprising: placing the SDIO bus into a one bit mode using a first line in the SDIO bus for data transfer; configuring a SDIO bus controller to receive an incoming interrupt from a peripheral device on a second, different line; and gating a SDIO clock configured to provide timing for data transfer along the SDIO bus and using an external clock to provide the timing for the data transfer along the SDIO bus, wherein the external clock maintains a lower rate for data transfer than the SDIO clock.