Patent ID: 6456137
Filing Date: 2002-09-24
Classification: H03H

Abstract:
A semiconductor circuit comprising:at least a first wire and a second wire disposed substantially parallel to each other without another wire in between the first and second wires; and an even number of buffer/inverter pairs, each pair comprising a buffer and an inverter, the buffer and the inverter in each of said pairs being disposed on said first or second wires, respectively, wherein the buffer and the inverter are aligned along an axis that is approximately perpendicular to the first and second wires, said first and second wires being respectively divided into even length wire sections by said buffers and inverters of each of said pairs and a device or terminal connected to an output side of said wires, said wire sections having length dimensions, wherein a length dimension of a wire section in the first wire is equal to a length dimension of an adjacent wire section in the second wire.