Patent ID: 7792230
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. A system for remotely synchronizing a majority voter circuit, the system comprising: a first processor for generating a data packet and a synchronization pulse wherein the synchronization pulse indicates a predetermined bit location in the data packet; a plurality of second processors communicatively coupled to the first processor wherein each of the plurality of second processors has a register, further wherein each of the plurality of second processors is configured for receiving the data packet and the synchronization pulse and storing the data packet and the synchronization pulse in its respective register; and a voting processor communicatively coupled to each of the plurality of second processors wherein the voting processor is configured for receiving at least a portion of the data packet from each of the plurality of second processors and utilizing the synchronization pulse to align each of the received portions of the data packets according to the synchronization pulse prior to voting.