Patent ID: 7078944
Filing Date: 2006-07-18
Classification: H03K

Abstract:
1. A power on reset circuit comprising: a resistor ladder providing a scaled version of a power supply voltage; a first MOS transistor configured to control generation of a power on reset signal, the first MOS transistor being coupled to a pull-up resistor; and a first process dependent element coupled to a node of the resistor ladder, the first process dependent element comprising a second MOS transistor, the first process dependent element and the first MOS transistor being formed in an integrated circuit using a same fabrication process, the first process dependent element being configured to adjust a first trip point of the power on reset circuit to compensate for a variation in a threshold voltage of the first MOS transistor due to a variation in the fabrication process, wherein a resistance of the first process dependent element tracks the variation in the threshold voltage of the first MOS transistor; wherein the first process dependent element has a first end directly connected to a gate of the first MOS transistor and a second end directly connected to a ground.