Patent ID: 7391416
Filing Date: 2008-06-24
Classification: G09G

Abstract:
1. A method comprising: (a) receiving digital synchronization signals of analog signals having digital information for digital display and detecting format based on said received digital synchronization signals; (b) setting an initial frequency value of a sampling clock of said analog signals by setting a phase locked loop division factor value equal to a digital horizontal synchronization signal cycle based on said detected format, and setting a phase value of the sampling clock at a phase locked loop mechanism; (c) fine tuning said initial frequency value of the sampling clock by fine tuning said phase locked loop division factor value, and fine tuning said phase value of the sampling clock, for synchronizing said phase locked loop mechanism with a sampling period; determining an error value of said phase locked loop division factor value, said error value being a difference between an actual said phase locked loop division factor value and a said phase locked loop division factor value matching said initial frequency value of the sampling clock to a frequency value of a transmitter timing clock; (d) sampling said received analog signals having digital information within said sampling period; and (e) receiving and displaying said digital image pixel information by a digital display device.