Patent ID: 8329566
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: a) providing a substrate; b) sequentially forming a source region, a drain region, a dummy gate structure, a gate dielectric layer on the substrate and sidewall spacers on sidewall surfaces of the dummy gate structure, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; then c) forming a stop layer covering the source region, the drain region, the dummy gate structure, the gate dielectric layer on the substrate and sidewall spacers; then d) forming a dielectric layer on the top of the stop layer; e) performing a chemical Mechanical Polishing (CMP) so as to stop on the stop layer; f) annealing the source region and the drain region; g) removing the dummy gate structure to form an opening; h) implanting dopants into the substrate from the opening to form a steep retrograded well; i) annealing to activate the dopants; and j) forming a metal gate on the gate dielectric layer by deposition; wherein step b) additionally comprises forming a work function metal gate layer prior to the formation of the dummy gate structure, such that the work function metal gate layer is between the gate dielectric layer and the dummy gate structure.