Patent ID: 6166410
Filing Date: 2000-12-26
Classification: G11C,H01L

Abstract:
A multi-level logic flash memory cell comprising:a) a substrate having a floating gate channel area, a MONOS channel area, and a source area adjacent the floating gate channel area and a drain area adjacent the MONOS channel area;b) a tunnel oxide layer over said floating gate channel area and said MONOS channel area of said substrate;c) a poly floating gate electrode over said floating gate channel area;d) an ONO layer over said poly floating gate electrode and said tunnel oxide layer over said MONOS channel area;e) a control gate electrode over said ONO layer over said poly floating gate electrode and said MONOS channel area;f) shallow trench isolation regions in portions of said source and drain area in said substrate;g) a source region in said source area in said substrate adjacent to said floating gate channel area and under a portion of said poly floating gate electrode;h) a drain region in said drain area in said substrate adjacent to said MONOS channel area and under a portion of said ONO layer; said source and drain regions orientated in a first direction;i) an insulating layer over said control gate electrode over said MONOS channel area;j) a word line over said control gate electrode and said insulating layer; said word line oriented in a second direction perpendicular to said source and drain regions;k) said control gate electrode and said poly floating gate electrode forming a floating gate transistor over said floating gate channel area; and said ONO layer and said control gate electrode over said MONOS channel area forming a MONOS transistor over said MONOS channel area; and said multi-level logic flash memory cell comprised of said MONOS transistor and said floating gate transistor.