Patent ID: 6292877
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A memory system comprising:a memory controller;a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;a first bidirectional data bus coupled to the memory controller, the memory controller communicating first data information to the bidirectional data bus for a write operation and receiving the first data information from the bidirectional data bus during a read operation;a second bidirectional data bus coupled to the memory controller, the memory controller communicating second data information to the second bidirectional data bus for a write operation and receiving the second data information from the second bidirectional data bus during a read operation;a first plurality N of pipelined memory subsystems, wherein each memory subsystem includes:a plurality of memory devices, wherein each memory device contains a data in and a data out buffer, a column decoder and a row decoder;a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices; anda data register connected between the plurality of memory devices and the first bidirectional data bus, the data register receiving and latching the first data information from the first bidirectional data bus and driving the first data information to the data in buffers of the plurality of memory devices for a write operation, the data register receiving and latching the first data information from the data out buffers of the plurality of memory devices and driving the first data information to the first bidirectional data bus for a read operation; anda second plurality P of pipelined memory subsystems, wherein each memory subsystem includes:a plurality of memory devices, wherein each memory device contains a data in and a data out buffer, a column decoder and a row decoder;a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices; anda data register connected between the plurality of memory devices and the second bidirectional data bus, the data register receiving and latching the second data information from the second bidirectional data bus and driving the second data information to the data in buffers of the plurality of memory devices for a write operation, the data register receiving and latching the second data information from the data out buffers of the plurality of memory devices and driving the second data information to the bidirectional data bus for a read operation.