Patent ID: 7502880
Filing Date: 2009-03-10
Classification: G06F,Y02D

Abstract:
1. A microprocessor, comprising: a system clock pin receiving a bus clock signal; a first plurality of address pins and a first plurality of request pins; a second plurality of address pins and a second plurality of request pins; and address bus configuration logic, comprising an enable input which receives an enable signal, for operating said first plurality of address pins and said first plurality of request pins to perform a first transaction when said enable signal is asserted, and for operating said first and second plurality of address pins and said first and second plurality of request pins to perform a second transaction when said enable signal is not asserted, wherein said address bus configuration logic asserts a plurality of request packets onto said first plurality of address pins for each of a plurality of phases of a cycle of said bus clock signal; wherein, when said enable signal is asserted, said address bus configuration logic multiplexes first and second address data and first and second request data onto said first plurality of address pins and said first plurality of request pins during a first phase of said cycle of said bus clock signal and multiplexes third and fourth address data and third and fourth request data onto said first plurality of address pins and said first plurality of request pins during a second phase of said cycle of said bus clock signal.