Patent ID: 6590816
Filing Date: 2003-07-08
Classification: G11C

Abstract:
An integrated memory, comprising:a plurality of memory cells arranged in a memory cell block having a plurality of column lines and a plurality of row lines; said plurality of row lines including regular row lines and redundant row lines; a self-test unit connected to said memory cell block, said self-test unit: upon a read access to a current row line, checking for a correctness of a memory cell content read in the read access and, upon detecting a defect, generating a defect signal for the current row line; for each regular row line, detecting defects thus ascertained and performing a comparison comparing the defects with an average defect for said regular row lines; and outputting a row repair signal for the current row line when a predetermined repair condition is met in the comparison; a self-repair unit connected to said self-test unit, said self-repair unit, in response to receiving the row repair signal, replacing the current row line by a redundant row line during an operation of the integrated memory.