Patent ID: 6483155
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A semiconductor device comprising:a silicon substrate having a principal surface; first and second active regions defined by an isolation region formed in a principal surface of said silicon substrate; a first n-channel MOS transistor comprising a first insulated gate with a gate insulating film formed on said first active region, first extension regions formed in said first active region on both sides of the first insulated gate, and first pocket regions formed in said first active region on both sides of the first insulated gate at a deeper position than the first extension regions, the first pocket regions being doped with indium at a first concentration; and a second n-channel MOS transistor comprising a second insulated gate with a gate insulating film formed on said second active region, second extension regions formed in said second active region on both sides of the second insulated gate, and second pocket regions formed in said second active region on both sides of the second insulated gate at a deeper position than the second extension regions, the second pocket regions being doped with indium at a second concentration lower than the first concentration.