Patent ID: 7376180
Filing Date: 2008-05-20
Classification: H04B,H04L

Abstract:
1. An adaptive equalizer structure comprising: an interface receiver port to provide connection of received Bit Rate Agile (BRA) and Modulation Demodulation (Modem) Format Selectable (MFS) modulated signal to a pre-demodulation adaptive equalizer; the pre-demodulation adaptive equalizer structure comprising BRA and MFS splitter, multiplier circuit and delay structure for delaying the modulated signal in one branch of the splifter and coupling the time delayed signal in one branch of the splifter and the said received modulated signal in the other branch of the splitter to a signal combiner; a BRA and MFS signal combiner structure for combining the delayed modulated signal and received modulated signal; a BRA and MFS demodulator structure for demodulating the combined delayed signal and received modulated signal; and a BRA and MFS control signal processor for generation of and connection of said control signal to the multiplier circuit.