Patent ID: 6090713
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a plurality of trenches formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises, sequentially:forming a pad oxide layer on a main surface of the substrate or epitaxial layer;forming a polish stop layer having an upper surface on the pad oxide layer;forming a large trench and a small trench, the large trench having a width at the main surface greater than a width at the main surface of the substrate of the small trench;depositing a first layer of an insulating material to fill the trenches and cover the polish stop layer, whereby the first insulating layer has a seam above the small trench;performing a first polish to substantially planarize a portion of the first layer of the insulating material above the small trench;depositing a second layer of the insulating material filling the seam;masking the large trench with a planarization mask having an opening above the small trench;etching to remove a portion of each of the first and second layers of the insulating material above the small trench;removing the planarization mask; andperforming a second polish to planarize such that the upper surface of the first layer of the insulating material in the large and small trenches is substantially flush with the upper surface of the polish stop layer.