Patent ID: 7516254
Filing Date: 2009-04-07
Classification: G06F

Abstract:
1. A memory control apparatus which performs data transfer between a master and an external memory, said apparatus comprising: a master interface operable to receive an access request from the master and issue the access request to the external memory; and an external memory interface operable to receive the access request from said master interface and access the external memory, wherein said master interface includes: a data buffer operable to store data transferred from said external memory interface when the access request is issued; an address buffer operable to store an address for which the access request has been issued; a first comparison unit operable to compare a new address for which the access request has newly been issued with the address stored in said address buffer, and output first comparison information indicating whether or not the new address matches the address stored in said address buffer which indicates an address range of data stored in said data buffer; a buffer control unit operable to issue an access request to said external memory interface, in the case where the first comparison information indicates a mismatch between the new address and the stored address, and operable to output data from said data buffer to the master without issuing an access request to said external memory interface, in the case where the first comparison information indicates a match between the new address and the stored address; and a specific access detection unit operable to detect a new access request made by the master to a specific address on the external memory and determine, irrespective of whether the first comparison information indicates the match or the mismatch, whether or not to issue an access request to said external memory interface so as to control said buffer control unit based on the determination.