Patent ID: 7391651
Filing Date: 2008-06-24
Classification: G11C

Abstract:
1. A method for programming a NAND flash memory device having zero memory cells, first memory cells, second memory cells and third memory cells, each memory cell being associated with a first register and a second register, the method comprising the steps of: (a) programming the zero, the first, second and the third memory cells to a zero state; (b) programming the first memory cells from the zero state to a first state by activating a first program signal, and programming the second memory cells from the zero state to a quasi-second state and the third memory cells from the zero state to a semi-third state by activating a second program signal; (c) programming the second memory cells from the quasi-second state to a second state and programming the third memory cells from the semi-third state to a quasi-third state by activating the second program signal; and (d) programming the third memory cells from the quasi-third state to a third state by activating the first program signal.