Patent ID: 7214609
Filing Date: 2007-05-08
Classification: H01L

Abstract:
1. A method of forming a dual damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer to provide electrical coupling to a conductive feature in the existing interconnect structure, the method comprising: forming an etch-stop layer directly on the existing interconnect structure; forming dielectric layer over the etch-stop layer; forming a resist pattern over the dielectric layer; forming a via cavity through a portion of the dielectric layer to expose a portion of the etch-stop layer; then, extending the via cavity through a portion of the etch-stop layer to expose the conductive feature in the existing interconnect structure with substantially no processing steps between forming and extending the via cavity; then, removing the resist pattern; then, etching the dielectric layer to form a trench cavity in the dielectric layer; and forming a conductive material in the trench and via cavities to provide electrical coupling to the conductive feature in the existing interconnect structure.