Patent ID: 6249902
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A method for determining placement of a circuit within a substrate area of an integrated circuit chip, wherein the circuit is defined as comprising a plurality of logic modules, each logic module including a plurality of cells, the circuit being further defined as comprising connections for carrying signals between said cells, the method comprising the steps of:a. generating a trial placement by initially assigning each cell of said circuit to a position within the substrate area in a manner that is biased towards clustering cells of the same logic module while satisfying other positioning criteria;b. identifying a plurality of module core areas within the substrate area, each module core area corresponding to a separate one of the logic modules and encompassing assigned positions of cells of the corresponding logic module;c. defining a plurality of rectangular guiding blocks, each guiding block corresponding to a separate one of the module core areas and being sized relative to its corresponding module core area;d. assigning each guiding block to a position within said substrate area; ande. generating a second placement by reassigning each cell of said circuit to a position within the substrate area in a manner that is biased towards positioning cells of each logic module in a vicinity of the guiding block corresponding to the logic module while satisfying said other positioning criteria.