Patent ID: 6469316
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A test circuit, comprising:a semiconductor substrate; a mask on the substrate having an opening with an edge, the opening to enable impurity doping of selected portions of the test circuit; a plurality of circuit devices on the substrate having respective active regions positioned at staggered known distances from the edge of the opening, each of the active regions having a second edge and a width measured from its second edge in a direction away from the first edge of the mask opening, the known distance between a given active region and the first edge of the mask opening differing from the staggered known distances between the other active regions and the first edge of mask opening by at least the width, each of the plurality of circuit devices having a predicted on-state output current, a first source/drain region and a second source/drain region of a fist conductivity type, and a gate electrode, the gate electrode extending to the opening and having a first impurity region of the first conductivity type and a second impurity region of a second and opposite conductivity type; and whereby the predicted on-state output current of given circuit device exceeding an actual output current of the given circuit device being indicative of an overlap between the second impurity region of the gate electrode and the active region of the given device.