Patent ID: 6713820
Filing Date: 2004-03-30
Classification: H01L,Y10S

Abstract:
A semiconductor device having a MOS transistor, the MOS transistor comprising: a plurality of gate electrodes; source and drain regions formed on opposite sides of the gate electrodes to define channel regions therebetween; a gate wiring pattern connected to the gate electrodes; a source wiring pattern connected to the source region; a drain wiring pattern connected to the drain region; one or more source contacts for connecting the source region to the source wiring pattern; one or more drain contacts for connecting the drain region to the drain wiring pattern; the one or more source contacts and the one or more drain contacts being longer in the channel width direction than in the channel length direction; and a well region and one or more well contacts connecting the well region to the source wiring pattern; the one or more source contacts and the one or more well contacts each comprising a batting contact having a diffusion region formed in the well region and a contact portion in contact with the diffusion region, one side of the diffusion region being shorter than an opposite side thereof.