Patent ID: 7535261
Filing Date: 2009-05-19
Classification: H03K

Abstract:
1. A logic circuit, comprising: a current signal generating circuit which generates a current signal changing between a first current and a second current smaller than said first current in accordance with alternate voltage level change of a control signal between a first voltage level and a second voltage level; a common constant current source generating a third current; a current mirror circuit which transfers the current generated in said current signal generating circuit to a transistor element which is connected between a voltage source node and a common node connected to said common constant current source; and a logic unit connected in parallel to said transistor element of the current mirror current, wherein the parallel connection of said logic unit and said transistor element of the current mirror circuit causes limitation on current supplied to said logic unit, wherein said logic unit is put into an active state by being supplied with a current corresponding to a residual obtained by subtracting said second current from said third current when said control signal is the first voltage level, and wherein said logic unit is put into an inactive state due to deprivation of the supplied current which is limited to a current corresponding to residual obtained by subtracting said first current from said third current when said control is a second voltage level; a logic output data is generated by processing a logic input data when said logic unit is in said active state.