Patent ID: 7382005
Filing Date: 2008-06-03
Classification: H01L

Abstract:
1. A chip comprising: a semiconductor substrate; a MOS device in or on said semiconductor substrate; a first metal pad over said semiconductor substrate; a passivation layer over said semiconductor substrate, wherein an opening in said passivation layer exposes said first metal pad; a second metal pad connected to said first metal pad through said opening in said passivation layer, wherein the position of said second metal pad from a top perspective view is different from that of said first metal pad, and wherein said second metal pad comprises a gold layer having a thickness greater than 1 micrometer; an adhesion/barrier layer directly on and in contact with said gold layer of said second metal pad; a copper layer over said adhesion/barrier layer; a nickel-containing layer over said copper layer; and a tin-containing bump over said nickel-containing layer.