Patent ID: 6597157
Filing Date: 2003-07-22
Classification: G05F,H02M

Abstract:
A controller for controlling high side and low side switches in a power converter that operates in a high frequency switching mode, the controller comprising:a plurality of phased clock units, each phased clock unit receiving a clock signal from a clock source and generating a phased clock signal; a plurality of ramp signal units, each ramp signal unit receiving a phased clock signal from the phased clock generation unit and generating a first ramp signal; a plurality of pulse width modulation units, each pulse width modulation unit receiving a first ramp signal from a ramp signal unit and generating a second ramp signal having a reduced amplitude; and a parallel gate drive unit, the parallel gate drive unit receiving second ramp signals and comparing the second ramp signals with an error signal, the parallel gate drive unit generating at least one parallel phased gate drive signal and at least one complimentary phased gate drive signal.