Patent ID: 7879658
Filing Date: 2011-02-01
Classification: H01L

Abstract:
1. A semiconductor device comprising: a silicon crystal layer formed on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane; a memory cell array portion formed on the silicon crystal layer, the memory cell array portion comprising a plurality of memory strings, each of the plurality of memory strings comprising a plurality of nonvolatile memory cell transistors connected in series in a first direction, the plurality of memory strings being arranged in a second direction orthogonal to the first direction; the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the plurality of nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the plurality of nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.