Patent ID: 9152594
Filing Date: 2015-10-06
Classification: G06F

Abstract:
1. A semiconductor memory device, comprising: a memory cell array section comprising a plurality of memory cell arrays; a peripheral circuit section; and an internal bus connecting the plurality of memory cell arrays and the peripheral circuit section; wherein the peripheral circuit section comprises a plurality of external input/output buffers, and a bus interface unit to execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers; wherein the plurality of external input/output buffers are arranged along a line; and wherein the bus interface unit is arranged between the plurality of external input/output buffers and the memory cell array section and is arranged in an area having a length, measured along the line, less than a distance between two ends of the plurality of external input/output buffers.