Patent ID: 7228485
Filing Date: 2007-06-05
Classification: H03M

Abstract:
1. An apparatus comprising: a detected sequence receive circuit to receive a detected sequence representing a signal on a channel, wherein the detected sequence comprises data bits and one or more error detection code bits; an error indications receive circuit to receive one or more error indications for the detected sequence, each of the one or more error indications identifying one or more of the data bits of the detected sequence that may have an erroneous value; an error correction circuit to generate a candidate sequence based on the detected sequence and the one or more error indications when an error signal is asserted for the detected sequence; an error detection decoder to detect one or more errors in the detected sequence using the one or more error detection code bits in the detected sequence; and an error signal circuit to assert the error signal for the detected sequence when the error detection decoder detects one or more errors in the detected sequence.