Patent ID: 8809929
Filing Date: 2014-08-19
Classification: H01L

Abstract:
1. A memory device comprising: a microelectronic substrate including a cell array region and a peripheral region adjacent the cell array region, the cell array region including therein an array of memory cells and the peripheral region including therein a plurality of peripheral circuits for the array of memory cells, the microelectronic substrate including a lower layer that extends across the cell array region and across the peripheral region and that includes a flat outer surface from the cell array region to the peripheral region; a signal transfer conductor layer that extends in the cell array region beneath the flat outer surface of the lower layer and that extends in the peripheral region above the flat outer surface of the lower layer; an insulating layer on the lower layer, the insulating layer extending across the cell array region and the peripheral region and also including a flat outer surface from the cell array region to the peripheral region; a flat stopper layer on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region; and an array of memory cell capacitor storage nodes in the cell array region that extend beyond the flat stopper layer and that penetrate through the flat stopper layer and the insulating layer.