Patent ID: 6084463
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A fuse circuit comprising:one or two or more first signal lines, provided in a semiconductor integrated circuit in which to form one or two or more internal circuits and a plurality of signal I/O circuits for inputting and outputting signals to be inputted and outputted to or from said internal circuits, and connected to said one or two more internal circuits, for transmitting the signals;one or two or more first pads so formed as to be connected to said one or two or more first signal lines;a plurality of fuses, provided corresponding respectively to said signal I/O circuits. one ends of which are each connected to said one or two or more first pads;a plurality of second signal lines, each correspondingly connected to the other end of said fuses and said signal I/O circuits for transmitting the signals; anda plurality of second pads each connected corresponding to said signal I/O circuits and connected to said first pads via said fuses,wherein each of said fuses is fused by selectively applying a voltage to said first pads and said second pads connected to said fuses, and any one of said signal I/O circuits selectively connected to any one of said internal circuits.