Patent ID: 6806751
Filing Date: 2004-10-19
Classification: H03L,Y10S

Abstract:
A phase-locked loop comprising:a selector receiving a first clock signal at a first input and a second clock signal at a second input and outputting an input clock signal at an output, wherein one of said first and second inputs is selectively coupled to said output; a phase detector receiving a feedback signal at a first input and said input clock signal at a second input and outputting a phase error signal indicative of a comparison between said input clock signal and said feedback signal; a loop filter receiving said phase error signal and outputting an error correction signal at an output, wherein said loop filter comprises: an amplifier having a first input, a second input, and an output, wherein said output of said amplifier is coupled to said output of said loop filter; a first resistor having a first lead, a second lead, and a first resistance value, wherein said first lead is coupled to a first input of said loop filter and said second lead is coupled to said first input of said amplifier; a second resistor having a first lead, a second lead, and a second resistance value, wherein said first lead is coupled to a second input of said loop filter and said second lead is coupled to said second input of said amplifier; a third resistor having a first lead, a second lead, and a third resistance value, wherein said first lead is coupled to said first input of said amplifier and said second lead is coupled to said output of said amplifier; a first capacitor having a first lead, a second lead, and a first capacitance value, wherein said first lead is coupled to said first input of said amplifier and said second lead is coupled to said output of said amplifier; a fourth resistor having a first lead, a second lead, and a fourth resistance value, wherein said first lead is coupled to said second input of said amplifier and said second lead is coupled to a reference potential; and a second capacitor having a first lead, a second lead, and a second capacitance value, wherein said first lead is coupled to said second input of said amplifier and said second lead is coupled to said reference potential; and a voltage controlled oscillator receiving said error correction signal at an input and generating an output clock signal of the phase-locked loop which is indicative of said feedback signal, wherein said first clock signal is produced by a first oscillator, said second clock signal is produced by a second oscillator, the nominal frequency of said first, second, and voltage controlled oscillators is substantially the same, and a frequency tolerance of said first and second oscillators is equal to or tighter than a frequency tolerance of said voltage controlled oscillator.