Patent ID: 8536681
Filing Date: 2013-09-17
Classification: H01L

Abstract:
1. A CMOS integrated circuit mixedly provided with a silicified transistor and a non-silicified transistor comprising: a semiconductor substrate; P wells and N wells on a surface layer region of the semiconductor substrate; STI isolation oxide films which are formed between the P wells and the N wells isolating the P wells and the N wells from each other; gate electrodes, each of the wells having a gate electrode disposed thereupon; P-type source and P-type drain regions on the N wells that are formed as a result of a PSD step; N-type source and N-type drain regions formed on the P wells by depositing an oxide film on the surface of the substrate, selectively covering the N wells with a first resist film, and implanting ions into a surface of the substrate through the deposited oxide film as a result of an NSD step; a silicide provided on the gate electrodes, the source and the drain regions of a first of the N wells and a first of the P wells from both of which the oxide film is removed by the steps of selectively removing the first resist film, thereafter selectively covering a second of the N wells and a second of the P wells to form a non-silicide transistor that is not subjected to silicide formation with a second resist film so as to not form silicide in the non-silicide transistor, and then removing the oxide film from the first N well and the first P well that both constitute a silicide transistor; and an interlayer oxide film directly deposited on the STI isolation oxide films, wherein the interlayer oxide film of the non-silicide transistor is disposed so as to not touch the silicide transistor.