Patent ID: 6788583
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A method of detecting a charge stored on a source charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells, the method comprising:grounding a first bit line that forms a source junction with a channel region of the first memory cell, the channel region being to the right of the first bit line; applying a high voltage to a gate of the first memory cell; applying a high voltage toga second bit line that forms a drain junction with the channel region, the second bit line positioned to the right of the first bit line and to the right of the channel region; isolating a third bit line such that its potential is effected only by its junctions with a second channel region and a third channel region; the third bit line being to the right of the second bit line and separated from the second bit line only by the second channel region that is positioned there between; the third channel region being positioned to the right of the third bit line; applying a high voltage to a pre-charge bit line, the pre-charge bit line being to the right of the third bit line; and detecting current flow at the second bit line.