Patent ID: 8095821
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. A method for error recovery for multiple errors in a microprocessor environment, wherein said microprocessor comprises a recovery unit, said method comprising: said recovery unit maintaining error information in a register; wherein said register comprises a counter; said counter tracking number of errors which occur after a first error; a forward progress event resetting said counter to zero; wherein said register comprises a first bit range and a second bit range; storing information about said first error in said first bit range; wherein said first bit range has a first predetermined limit; storing information about said errors which occur after a first error in said second bit range; wherein said second bit range has a second predetermined limit; wherein said second bit range comprises a last bit range; and in case said second bit range is full, said recovery unit overwriting information about the latest error in said last bit range, and said recovery unit raising said counter.