Patent ID: 8639943
Filing Date: 2014-01-28
Classification: G06F

Abstract:
1. A system comprising: a processor configured to run secure or non-secure instruction code; a memory configured to store a page table having execute permissions for memory pages from which instructions for the processor may be fetched and executed, wherein the execute permissions are settable between indicating allowing execution and indicating not allowing execution; a translation lookaside buffer configured to maintain, for each of a plurality of the memory pages, a valid entry corresponding to the memory page, the valid entry including the execute permissions for the memory page; a memory management unit configured to: set the execute permissions of entries in the translation lookaside buffer in accordance with the processor, wherein the memory management unit is configured to perform a lookup of the translation lookaside buffer, of a given address, to determine whether the translation lookaside buffer has, among said valid entries, a valid entry corresponding to the memory page, wherein the processor is configured to perform, in response to the translation lookaside buffer indicating having the valid entry corresponding to said memory page and that the execute permissions included in the valid entry are set as the execute permissions allowing execution, a fetch and execute of an instruction corresponding to the given address, else to perform an interrupt service routine comprising: and wherein the processor is configured to perform, in response to performing the interrupt service routine without invoking the error handling procedure, a fetch and execute of the instruction corresponding to the given address.