Patent ID: 6649933
Filing Date: 2003-11-18
Classification: G02F,H01L

Abstract:
A manufacturing method of a thin film transistor (TFT), comprising the steps of:providing a substrate; depositing a conductive layer above the substrate to form a gate electrode of the thin film transistor; forming an insulating layer above the conductive layer and the substrate; sequentially forming a semiconductor layer and a doped silicon layer on the insulating layer; depositing a sacrifice layer with an island shape above the doped silicon layer, and the sacrifice layer being positioned directly above the gate electrode; forming a metal layer covering the sacrifice layer and the doped silicon layer; patterning the metal layer to form a source electrode and a drain electrode, a channel being defined between the source electrode and the drain electrode, a non-TFT region being defined as a portion of the substrate not covered by the source electrode, the drain electrode, and the channel, and the island-shaped sacrifice layer being exposed in the channel and the doped silicon layer being exposed in the non-TFT region after the metal layer being patterned; using the source and the drain electrodes as a mask to perform the following etching processes at the same time during a predetermined period: (a) removing the island-shaped sacrifice layer and the doped silicon layer in the channel so that the semiconductor layer being exposed in the channel; and (b) removing the doped silicon layer and the semiconductor layer in the non-TFT region to expose the insulating layer; and forming a passivation layer to cover the source electrode, the drain electrode, the channel, and the substrate.