Patent ID: 6438670
Filing Date: 2002-08-20
Classification: G06F

Abstract:
A memory controller circuit arrangement for use with a plurality of types of memory storage devices having varying timing parameters related to a performance characteristic common to the plurality of types of memory storage devices, the circuit arrangement comprising:(a) a logic circuit configured to control data transfer with a memory storage device by performing first and second memory control operations, the memory storage device of the type having a predetermined timing parameter that defines a minimum delay between the first and second memory control operations; and (b) a tuning circuit coupled to the logic circuit and configured to control the delay between the first and second memory control operations to meet the predetermined timing parameter for the memory storage device, the tuning circuit including: (i) a configuration register configured to store a delay count representative of a number of clock cycles to delay performance of the second memory control operation; and (ii) a programmable delay counter configured to cycle the number of clock cycles represented by the delay count prior to performance of the second memory control operation by the logic circuit.