Patent ID: 6272058
Filing Date: 2001-08-07
Classification: G11C

Abstract:
A semiconductor memory device capable of reading/writing data in a unit of N bits (N is an integer at least 2), comprising:first to Nth memory arrays having a plurality of memory cells, respectively, each of the memory cells having a specific address signal assigned thereto;first to Nth read/write circuits provided corresponding to the first to Nth memory arrays, respectively, each selecting one of the plurality of memory cells included in corresponding said memory array according to an external address signal to perform reading/writing of data of the memory cell;first to Nth data input/output terminals coupled to said first to Nth read/write circuits, respectively, each performing output of read data and input of write data;a spare memory cell for replacement with a defective memory cell;an Nth plus one read/write circuit storing an address signal of the defective memory cell and performing reading/writing of data of said spare memory cell in response to matching of the external address signal and the stored address signal;a control circuit storing the address signal of the defective memory cell and a number i (i is an integer from 1 to N) of the memory array to which the memory cell belongs, and inactivating the ith read/write circuit in response to matching of the external address signal and the stored address signal; anda switching circuit coupling said Nth plus one read/write circuit with the ith data input/output terminal in response to the inactivation of said ith read/write circuit by said control circuit.