Patent ID: 6237074
Filing Date: 2001-05-22
Classification: G06F

Abstract:
Pipelined processor having consecutive pipeline cycles and including at least a prefetch stage, a decode stage, and an execute stage, said instructions comprising instruction segments and said segments comprising instruction portions, said processor further comprising;a line buffer in said prefetch stage for storing instruction portions retrieved from memory, said line buffer having a line width less than a maximum possible instruction width,retrieving said means for retrieving instruction portions from said line buffer into said decode stage including a plurality of shadow registers for storing an instruction portion retrieved from said line buffer,a decoder in said decode stage coupled to receive said instruction portions from said retrieving means, for decoding an instruction segment when said decoder has received a predetermined instruction segment from said retrieving means and for preventing decoding otherwise, andcontrol means for causing said shadow register to store an instruction portion until said retrieving means has retrieved all instruction portions comprising said predetermined instruction segment corresponding to said stored instruction portion and for causing said retrieving means to output said stored instruction portion along with any other retrieved instruction portion comprising said predetermined instruction segment when said retrieving means has retrieved all said instruction portions comprising said predetermined instruction portion,wherein said control means comprises a multiplexer for selectively coupling said instruction portions from said retrieving means to said decoder (1) directly from said line buffer or (2) from said shadow registers, andwherein said multiplexer complises a 2:1 multiplexer having a first input coupled to said shadow registers and a second input coupled directly to said line buffer and an output coupled to said decoder.