Patent ID: 6828686
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A chip size stack package comprising:upper and lower semiconductor chips having bond pads-forming surfaces which are opposed to each other; insulating layers applied to the bond pads-forming surfaces of the upper and lower semiconductor chips, each insulating layer being formed with via-holes for exposing bond pads, the insulating layers being bonded to the upper and lower semiconductor chips; metal traces deposited on the insulating layers and electrically connected to the bond pads through the via hole, each of the metal traces being exposed at sides of the insulating layers, the metal traces being bonded the upper and lower semiconductor chips; outside connection terminals each having one end connected to an exposed portion of the metal traces; and an encapsulate for molding each side of exposed portions of the upper and lower semiconductor chips which are stacked one upon the other, in a manner such that the other ends end of the outside connection terminal is exposed.