Patent ID: 6075721
Filing Date: 2000-06-13
Classification: G11C,H04L,H04Q

Abstract:
A random access memory circuit comprising:an array of memory cells arranged in a first number of columns having a second number of rows, each column of memory cells addressed by a corresponding set of bit lines and each row of cells addressed by a corresponding word line, each memory cell including a logic gate for generating a gating signal in response to a supplied write signal and a bit enable signal, the gating signal causing the corresponding memory cell to overwrite a stored data value with a supplied data value; andcontrol logic for supplying the bit enable signal to a selected group of said columns in response to a mask signal, whereinthe control logic comprises a plurality of decoders receiving a corresponding bit of the mask signal, each decoder outputting the bit enable signal to a corresponding group of the columns in response to the corresponding bit of the mask signal.