Patent ID: 6578062
Filing Date: 2003-06-10
Classification: G06F

Abstract:
A digital division circuit for calculating a quotient from a dividend and a divisor, wherein the divisor can be represented as (2N+2M) where N is greater than M, and wherein the dividend comprises a binary number having X bits indexed as bits 0-th through (Xâˆ’1)-th, the dividend being divisible by the divisor without a remainder, the digital division circuit comprising:(a) a first circuit for providing the M-th through the (Nâˆ’1)-th bits of the dividend as lower order bits of the quotient; (b) a second circuit for providing the (2Nâˆ’M)-th through the (Xâˆ’1)-th bits of the dividend as a first higher order bit segment for the quotient; (c) a detector for detecting the (Nâˆ’1)-th and the (2Nâˆ’Mâˆ’1)-th bits of the dividend and for generating a control signal if: (1) the (Nâˆ’1)-th bit of the dividend is â€œ1â€  and (2) the (2Nâˆ’Mâˆ’1)-th bit of the dividend is â€œ0â€ ; (d) a subtractor connected to the second circuit for subtracting the value â€œ1â€  from data including the (2Nâˆ’M)-th through the (Xâˆ’1)-th bits of the dividend and generating output bits as a second higher order bit segment for the quotient; and (e) a selector connected to the second circuit and to the subtractor, and responsive to the control signal from the detector for selecting between said first and second higher order bit segments as higher order bits of the quotient, wherein: (1) in the presence of the control signal the selector provides said second higher order bit segment as the higher order bits for the quotient, otherwise, (2) in the absence of the control signal the selector provides said first higher order bit segment as the higher order bits for the quotient; wherein the higher and lower order bits represent a value of the quotient.