Patent ID: 6287955
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A process for producing an integrated circuit structure which comprises(a) providing a substrate which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines;(b) depositing an organic dielectric layer on the substrate;(c) depositing an inorganic dielectric layer on the organic dielectric;(d) etching a pattern of vias through the inorganic dielectric layer;(e) etching a pattern of vias through the organic dielectric layer which correspond to the pattern of vias through the inorganic dielectric layer;(f) applying a photoresist to the top of the inorganic dielectric layer and filling the vias in the organic dielectric layer and the inorganic dielectric layer with photoresist;(g) imagewise removing a portion of the photoresist from the top of the inorganic dielectric layer; and removing a portion and leaving a portion of the photoresist through a thickness of the inorganic dielectric layer;(h) removing part of the inorganic dielectric layer underlying the portions of the photoresist removed from the top of the inorganic dielectric layer to form trenches in the inorganic dielectric layer;(i) removing the balance of the photoresist from the top of the inorganic dielectric layer and from the vias;(j) filling the vias in the organic dielectric and the trenches in the inorganic dielectric with a metal.