Patent ID: 7015086
Filing Date: 2006-03-21
Classification: H01L

Abstract:
1. A method of forming a smooth top surface topography for an isolation region in a semiconductor substrate, wherein said isolation region is comprised of a shallow trench-deep trench configuration, comprising the steps of: depositing a silicon nitride layer; forming a shallow trench shape in said silicon nitride layer and in a first portion of said semiconductor substrate; depositing a first silicon oxide layer completely filling said shallow trench shape; performing a first chemical mechanical polishing (CMP), procedure to remove a top portion of said first silicon oxide layer, forming an insulator filled shallow trench shape with a smooth top surface topography; forming a deep trench opening in said insulator filled shallow trench shape and in an underlying second portion of said semiconductor substrate; growing a silicon dioxide layer on surface of portions of said semiconductor substrate exposed in said second portion of said deep trench opening; performing an ion implantation procedure to form a channel stop region of the same dopant type as said semiconductor substrate, in a third portion of said semiconductor substrate, located underlying bottom of said deep trench opening, with the dopant concentration of said channel stop region greater than the dopant concentration of said semiconductor substrate; depositing a second silicon oxide layer, not filling said deep trench opening; depositing a polysilicon layer completely filling said deep trench opening; removing portions of said polysilicon layer and exposed portions of said second silicon oxide layer, resulting in a recessed polysilicon shape in a bottom portion of said deep trench opening; depositing a third silicon oxide layer completely filling a space in a top portion of said deep trench opening; performing a dry etch procedure using a photoresist shape as a mask, to remove portions of said third silicon oxide layer and bottom portions of said first silicon oxide layer, from the top surface of said silicon nitride layer, resulting in an insulator stack comprised of said third silicon oxide layer and of a bottom portion of first silicon oxide layer, with said insulator stack overlying insulator filled shallow trench shape, and overlying adjacent portions of said silicon nitride layer; performing a second CMP procedure to remove said insulator stack from the top surface of said adjacent silicon nitride layer resulting in a deep trench shape comprised of a third silicon oxide plug in a top portion of said deep trench opening, overlying said recessed polysilicon shape in turn located in said bottom portion of said deep trench opening, with top surface of said deep trench shape and said silicon nitride layer creating a smooth top surface topography; and removing said silicon nitride layer.