Patent ID: 6383877
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method of forming elevated salicide source/drain regions, comprising:(a) forming T-shaped isolation layers in a semiconductor substrate, the T-shaped isolation layers having narrow trench regions defined by a first width and a first depth in lower portions thereof and wide trench regions having a second width greater than the first width and a second depth less than the first depth in upper portions thereof; (b) forming a gate electrode pattern with a gate oxide layer, gate electrodes, and spacers on an active region of the semiconductor substrate defined by the T-shaped isolation layers; (c) growing a semiconductor material layer on the active regions exposed on both sides of the gate electrode pattern and on the gate electrodes; (d) forming elevated source/drain regions by implanting conductive impurities using the gate electrode pattern as an ion implantation mask, the impurities also being implanted in lower portions of the wide trench regions which are heads of the T-shaped isolation layers and which extend along both sides from the upper ends of the narrow trench regions; and (e) forming a silicide layer on the elevated source/drain regions.