Patent ID: 8015389
Filing Date: 2011-09-06
Classification: G09G,G11C

Abstract:
1. A semiconductor integrated circuit in which circuits are integrated on a single semiconductor substrate, the semiconductor integrated circuit comprising: a memory array in which memory cells connected to word lines and bit lines and storing data are arranged in the form of a matrix, and the memory array being sectioned into a plurality of bit groups, each of the plurality of bit groups having Nb number of memory cells, and each of the bit group storing Nb bits; a controller that selects a plurality of bit groups on the basis of an address signal including a row address signal and a column address signal, and further selects a bit group as a starting point among the selected plurality of bit groups, on the basis of a first combination information indicating a start position in the selected plurality of bit groups; and Nb×N number of output terminals, wherein the controller outputting, from the Nb×N number of output terminals in parallel, on the basis of a second combination information, data items that are stored in the memory cells contained in N number of bit groups including the bit group at the starting point.