Patent ID: 6333222
Filing Date: 2001-12-25
Classification: H01L

Abstract:
A semiconductor device comprising:a memory cell portion and a logic portion formed on a semiconductor substrate;a first MIS transistor formed in said memory cell portion;a second MIS transistor of a first conductivity type and a third MIS transistor of a second conductivity type formed in said logic portion;a gate electrode of said first MIS transistor having a first polycrystalline silicon film and a first silicide layer;a gate electrode of said second MIS transistor having a second polycrystalline silicon film of the first conductivity type and a second silicide layer of the first conductivity type; anda gate electrode of said third MIS transistor having a third polycrystalline silicon film of the second conductivity type and a second silicide layer of the second conductivity type; whereina gate insulation film of said first MIS transistor being thicker than a gate insulation film of said second MIS transistor and a gate insulation film of said third MIS transistor,source/drain active regions of said second MIS transistor and source/drain active regions of said third MIS transistor each having a third silicide layer, andsheet resistance of said second silicide layer and said third silicide layer being set lower than sheet resistance of said first silicide layer.