Patent ID: 6011742
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A semiconductor memory device coupled to first and second voltage supply terminals, comprising:a plurality of rows and columns of primary and redundant memory cells;a plurality of electronically programmable resistance circuits, each storing at least one bit of information of an address of one of the plurality of rows of primary memory cells, and at least one bit of information of an address of one of the plurality of columns of primary memory cells, each programmable resistance circuit comprising:first and second programmable resistance cells each coupled to the first voltage supply terminal;a single shared selection circuit coupled to both of the first and second programmable resistance cells and having an output terminal, the single shared selection circuit selectively providing first and second bits of information from the first and second programmable resistance cells to the output terminal upon receipt of first and second selection signals supplied thereto, respectively;a single output circuit coupled to the second voltage supply terminal and the output terminal of the single shared selection circuit and having a data output terminal, the output circuit providing the first and second bits of information for the first and second programmable resistance cells to the data output terminal, andwherein the first and second programmable resistance cells are antifuse cells, wherein the first and second voltage supply terminals provide ground and positive voltage, respectively, wherein the shared selection circuit includes first and second selection transistors, the first selection transistor being coupled between a second terminal of the first antifuse cell and the output terminal, and receiving the first selection signal at a control terminal, and the second selection transistor being coupled between a second terminal of the second antifuse cell and the output terminal, and receiving the second selection signal at a control terminal; andwherein the output circuit includes an inverter, a resistive element, and first and second latch transistors, the first and second latch transistors having first terminals coupled to receive the positive voltage, the resistive element being coupled between a second terminal of the first latch transistor and the output terminal of the shared selection circuit, the inverter being coupled between the output terminal and the data output terminal, a second terminal of the second latch transistor being coupled to the second terminal of the first latch transistor, a control terminal of the first latch transistor receiving an enabling signal, and a control terminal of the second latch transistor being coupled to the data output terminal.