Patent ID: 7838358
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device having at least a capacitor, a fuse and a MOS field effect transistor formed on one surface of a semiconductor substrate, the method comprising: a preparing step of preparing the semiconductor substrate having an element isolation insulating film and a gate insulating film for the MOS field effect transistor formed on the surface of the semiconductor substrate, the semiconductor substrate including a first conductive layer covering the element isolation insulating film and the gate insulating film, a dielectric layer and a second conductive layer made of a same material as a material of the first conductive layer, stacked in a recited order; a first patterning step of patterning the dielectric layer and the second conductive layer into a pattern by using one etching mask, wherein the dielectric layer in an area where the capacitor is to be formed, is left to be a capacitor insulating film of the capacitor, the second conductive layer on the capacitor insulating film is left without etching and the dielectric layer in an area where a first fuse is to be formed, is removed, wherein the first patterning step further leaves the dielectric layer in an area where a second fuse is to be formed, without etching, and leaves also the second conductive layer in the area where the second fuse is to be formed; a conductive layer forming step of forming a third conductive layer covering the first conductive layer, the dielectric layer and the second conductive layer, the third conductive layer being made of metal or metal silicide being different from a material of the first conductive layer; and a second patterning step of etching each layer over the element isolation insulating film into a second pattern by using a second etching mask and utilizing the dielectric layer and the element isolation insulating film as an etching stopper, wherein the second conductive layer on the capacitor insulating film is patterned to be a first upper electrode of the capacitor, the third conductive layer on the first upper electrode is patterned to be a second upper electrode of the capacitor, the first conductive layer under the capacitor insulating film is left to be a lower electrode of the capacitor, the first conductive layer in an area where the first fuse is to be formed, is left to be a first soluble layer of the first fuse, and the third conductive layer on the first soluble layer is left to be a second soluble layer of the first fuse, wherein the second patterning step further patterns the second conductive layer left in the area where the second fuse is to be formed, to be a first soluble layer of the second fuse, and patterns the third conductive layer on the first soluble layer to be a second soluble layer of the second fuse, using the dielectric layer as an etching stopper.