Patent ID: 8320204
Filing Date: 2012-11-27
Classification: G11C

Abstract:
1. A memory interface control circuit, comprising: an input/output circuit which transmits and receives a data strobe signal to and from a memory; a read control circuit which determines that the data strobe signal associated with a memory read, received from the input/output circuit has repeated a predetermined number of times of transitions based on information on the number of data reads, and then sets a mask signal to a mask state; and a write control circuit which controls a transmission timing of outputting the data strobe signal associated with a memory write from the input/output circuit, based on a temporal positional relationship between a data strobe output request signal associated with the memory write and the mask signal, wherein the write control circuit performs control so that when a first timing of transition of the data strobe output request signal from an active state to an inactive state is temporally before a second timing of transition of the mask signal from the mask state to a mask cancellation state, the data strobe signal associated with the memory write is delayed by a predetermined period of time; and when the first timing is temporally after the second timing, the write control circuit performs control so that the data strobe signal associated with the memory write is output without alteration, without being delayed.