Patent ID: 6436833
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of forming shallow trench isolation regions in the manufacture of an integrated circuit device comprising:depositing an etch stop layer on the surface of a semiconductor substrate; etching a plurality of isolation trenches through said etch stop layer into said semiconductor substrate to separate active areas of said semiconductor substrate; depositing an oxide layer over said etch stop layer and within said isolation trenches wherein said oxide layer fills said isolation trenches and overlies said etch stop layer on said active areas; depositing a polysilicon layer overlying said oxide layer within said isolation trenches and said oxide layer overlying said etch stop layer; polishing away said polysilicon layer until said oxide layer overlying said etch stop layer is exposed and said polysilicon layer remains only overlying said oxide layer in said isolation trenches; thereafter oxidizing said polysilicon layer whereby oxidized said polysilicon layer has a height close to the height of said oxide layer overlying said etch stop layer; and polishing down said oxidized polysilicon layer, said oxide layer overlying said etch stop layer, and said oxide layer in said isolation trenches until said etch stop layer is reached thereby planarizing said isolation trenches to complete planarized said shallow trench isolation regions in said manufacture of said integrated circuit device.