Patent ID: 9129060
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A processor comprising: a plurality of processing cores; a plurality of instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier; a store component storing a group execution matrix and a store execution matrix, the group execution matrix comprising a plurality of group execution masks, each group execution mask corresponding to a given group number and indicating which cores can process an instruction from the given group number; the store execution matrix comprising a plurality of store execution masks; a core selection unit configured to for each instruction within each instruction store: select a store execution mask from the store execution matrix using the unique identifier of a selected instruction store as an index, select at least one group execution mask from the group execution matrix using the group number of at least one selected instruction from the selected instruction store as an index, and for each selected group execution mask of the at least one group execution masks, perform logic operations on the selected group execution mask and the store execution mask to create a core request mask, the core request mask corresponding to the selected instruction store and indicating zero, one, or more candidate cores; and an arbitration unit configured to determine instruction priority among each instruction, each instruction store having at least one corresponding core request mask, accordingly assign an instruction for each available core, where the core request mask corresponding to the instruction store of the instruction indicates candidate cores that intersect with the available cores, and signal the instruction store corresponding to the assigned instruction to send the assigned instruction to the available core.