Patent ID: 9170814
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. A processor comprising: an universal serial bus (USB) interface; a synchronous dynamic random access memory (SDRAM) interface; an input/output (I/O) interface; a plurality of registers to store 128-bit operands; a decoder to decode a single instruction multiple data (SIMD) instruction, the SIMD instruction to indicate a first 128-bit operand having a first set of sixteen byte elements and a second 128-bit operand having a second set of sixteen byte elements, the SIMD instruction to have a 4-bit immediate to specify a number (n) of bytes; an execution unit coupled with the decoder and the plurality of registers, the execution unit in response to the SIMD instruction to store a 128-bit result in a destination indicated by the SIMD instruction, wherein the result is to include the number (n) least significant byte elements of the second operand in the number (n) most significant bytes of the result, concatenated with sixteen minus the number (n) most significant byte elements of the first operand in sixteen minus the number (n) least significant bytes of the result.