Patent ID: 6668365
Filing Date: 2003-12-23
Classification: G06F

Abstract:
A method for modifying an integrated circuit (IC) layout for an IC design describing the IC as being formed by cells interconnected by nets, wherein each cell is an integer number of cell units in area, and wherein the layout specifies a position for each cell within a semiconductor substrate upon which the IC is to be formed, the method comprising the steps of:a. organizing the layout into an array rows and columns of blocks, such that each block Bi,j residing at the intersection of an ith column and the jth row has at least one neighboring block, wherein each block Bi,j is sufficiently large in area to hold a plurality of cells; b. computing a separate overflow factor Fi,j corresponding to each block Bi,j; c. establishing a plurality of equations, wherein each block Bi,j corresponds to a separate one of the equations, wherein the equation corresponding to each block Bi,j relates a plurality of flow variables to the overflow factor Fi,j corresponding to that block Bi,j, wherein each flow variable of the equation corresponding to each block Bi,j corresponds to a separate one of that block's neighboring blocks and represents a direction and number of cell units that are to flow between the block and the corresponding neighboring block as layout is altered; and d. selecting a simultaneous solution to the plurality of equations that establishes values of their flow variables.