Patent ID: 6770551
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A method for manufacturing a semiconductor element including a first silicon region, a second silicon region, and a metal silicide layer having lower and upper sides, wherein said lower side of said metal silicide layer contacts with said first silicon region and said second silicon region separately, and said upper side of said metal silicide layer provides for a gate interconnect, said method comprising steps of:performing a first doping process to dope an N-type dopant into said first silicon region and to dope a silicon as a diffusion barrier impurity into a portion of said metal silicide layer at said lower side thereof contacting with said first silicon region; and performing a second doping process to dope a P-type dopant into said second silicon region and to dope a silicon as a diffusion barrier impurity into a portion of said metal silicide layer at said lower side contacting with said second silicon region.