Patent ID: 9135132
Filing Date: 2015-09-15
Classification: G01R,G06F

Abstract:
1. A method of testing a plurality of devices under test (DUTs), each DUT including a plurality of cores, the method comprising: providing a plurality of shift registers to test the plurality of cores; supplying a test input data, a test mode input signal, a test clock signal, and a test reset signal to the plurality of shift registers and the plurality of cores; receiving a master bit, a first control value, and a second control value which are generated by the plurality of shift registers based on the test input data and the test mode input signal, in response to the test clock signal and the test reset signal; selecting at least one core from among the plurality of cores and a test method, according to the first control value; selecting a target DUT that is to output test data output from among the plurality of DUTs, according to the master bit or the second control value; and simultaneously testing and debugging the selected at least one core according to the test method, and outputting the test data output of the target DUT to check a result of the testing when an output enable signal is received.