Patent ID: 8963228
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor structure, the method comprising: forming an SOI layer on a BOX layer, the BOX layer is on a substrate; forming an STI region extending vertically through the SOI layer, the BOX layer, and a portion of a substrate, the STI region defines boundaries of an SOI device region and a nonvolatile memory device region, a top surface of the STI region is coplanar with a top surface of the SOI layer; forming a gate dielectric layer on the SOI layer and the STI region; forming a gate conductor layer on the gate dielectric layer; forming a hard mask layer on the gate conductor layer; forming a FET hard mask and a NVRAM hard mask by patterning the hard mask layer, the FET hard mask is above the SOI device region and the NVRAM hard mask is above the nonvolatile memory device region; forming a first gate stack in the SOI device region and a second gate stack in the nonvolatile memory device region, the first and second gate stacks comprising a portion of the gate dielectric layer and a portion of the gate conductive layer, the first stack is masked by the FET hard mask and the second stack is masked by the NVRAM hard mask; selectively removing portions of the SOI layer in the nonvolatile semiconductor memory device region to form a floating gate layer of the second gate stack; and selectively removing portions of a BOX layer in the nonvolatile semiconductor memory device region to form a tunnel oxide layer of the second gate stack.