Patent ID: 8079012
Filing Date: 2011-12-13
Classification: G06F,H05K

Abstract:
1. A simultaneous switching noise estimating apparatus including a processor for estimating simultaneous switching noise based on simultaneous operations of input/output signals of a plurality of pins that can be set according to plural pieces of user setting information in a semiconductor device, comprising: a first unit which calculates simultaneous switching noise basic characteristic data indicating for each piece of user setting information a function relationship between a number of simultaneous switching signals as a number of simultaneously operating pins and an amount of simultaneous switching noise when the semiconductor device is loaded into a predetermined standard or evaluation printed circuit board; a second unit which calculates a number of simultaneous switching signals for each piece of user setting information about an area near each pin to be processed using each pin of the semiconductor device as a pin to be processed; a third unit which calculates an amount of simultaneous switching noise for each pin to be processed on the basis of the calculation result of the second unit and the simultaneous switching noise basic characteristic data calculated in the first unit; a fourth unit which calculates and corrects simultaneous switching noise basic characteristic data when a pin arrangement of a semiconductor device and a configuration of a printed circuit board into which the semiconductor device are provided are designed so that the amount of simultaneous switching noise for each pin to be processed calculated in the third unit can be within a predetermined allowable range; a fifth unit which calculates a number of simultaneous switching signals for each piece of user setting information on an area near each pin to be processed using each pin of the semiconductor device as a pin to be processed; a sixth unit which re-calculates an amount of simultaneous switching noise for each pin to be processed on a basis of a calculation result of the fifth unit and the simultaneous switching noise basic characteristic data corrected in the fourth unit; and a seventh unit which corrects design of the configuration of the printed circuit board for which the pin arrangement of the semiconductor device is performed and the semiconductor device is loaded so that the amount of simultaneous switching noise for each pin to be processed re-calculated in the sixth unit can be within a predetermined allowable range; wherein the first through seventh units are implemented by the processor.