Patent ID: 6704847
Filing Date: 2004-03-09
Classification: G06F

Abstract:
A digital system comprising:a memory subsystem; a multi-channel direct memory access (DMA) subsystem with a DMA port connected to the memory subsystem for accessing the memory subsystem, each channel having priority circuitry for holding a channel priority, the DMA subsystem being operable to sequentially schedule memory accesses to the memory circuit in accordance with channel priority; a host interface for connection to a host processor, the host interface coupled to the DMA subsystem for accessing the memory subsystem via the DMA port as a host channel, the host interface also coupled directly to the memory subsystem for accessing the memory subsystem directly; a priority register for holding a priority of the host; and control circuitry connected to receive the priority of the host and the priority of the DMA channels, the control circuit being operable to enable the host interface to directly access the memory subsystem when the host priority is higher than all of the DMA channel priorities, or to enable the host interface to access the memory subsystem via the DMA port when the host priority is the same as or less than the DMA channel priorities.