Patent ID: 7781281
Filing Date: 2010-08-24
Classification: H01L

Abstract:
1. A method of fabricating a SAC (self-aligned contact) pad, comprising: forming a layer for a gate line on a semiconductor substrate together with a gate dielectric layer; forming a capping layer on the layer for the gate line; etching the capping layer and the layer for the gate line to form stacks of the gate line and the capping layer; forming spacers to cover sidewalls of the stacks; forming an insulation layer filling gaps between the stacks; performing a chemical mechanical polishing (CMP) process on the insulation layer using the capping layer as a polishing end point; partially etching the exposed capping layer to form damascene grooves on the remaining capping layer; forming a layer for a plurality of first etching masks filling the damascene grooves, the layer formed of a material different from that of the capping layer; performing a CMP process on the layer for the first etching masks to expose the top of the insulation layer such that the first etching masks filling the damascene grooves are formed; forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks; etching the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes; removing the second etching mask; forming a conductive layer filling the opening holes to cover the remaining first etching masks; and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.