Patent ID: 8154088
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A method of processing a semiconductor topography, the method comprising: forming one or more gate structures with associated sidewall spacers upon a semiconductor layer; depositing a disposable spacer layer upon the one or more gate structures, the sidewall spacers and adjacent portions of the semiconductor layer; implanting a first set of dopants into the semiconductor layer to form a first set of source and drain regions, whose boundaries are laterally spaced from the sidewalls of a first one of the gate structures by a distance determined, at least in part, by a combined thickness of the disposable spacer layer and a sidewall spacer formed adjacent to the first one of the gate structures; altering a thickness of the disposable spacer layer; masking a portion of the semiconductor topography comprising the first one of the gate structures and the first set of source and drain regions; and implanting a second set of dopants into the semiconductor layer to form a second set of source and drain regions, whose boundaries are laterally spaced from the sidewalls of a second one of the gate structures by a distance determined, at least in part, by a combined thickness of the altered disposable spacer layer and a sidewall spacer formed adjacent to the second one of the gate structures.