Patent ID: 9081284
Filing Date: 2015-07-14
Classification: G03F,H01L

Abstract:
1. A method of manufacturing a semiconductor device including a layer having a first region and a second region contacting the first region at a boundary line between the first region and the second region, the layer within the first region including a plurality of first patterns and the layer within the second region including a plurality of second patterns, the method comprising: forming a pattern including an on-boundary-line line portion with a width defined by a first line which is arranged in the first region and is parallel to the boundary line, and a second line which is arranged in the second region and is parallel to the boundary line, wherein the first region includes a first area that is an entire area within an outer boundary of a region in which the plurality of first patterns and the first line are to be arranged, and the second region includes a second area that is an entire area within an outer boundary of a region in which the plurality of second patterns and the second line are to be arranged, and wherein the first area and the second area have no area shared by the first area and the second area, the forming the pattern including