Patent ID: 7517762
Filing Date: 2009-04-14
Classification: H01L,Y10S

Abstract:
1. A method for forming a fuse area of a semiconductor memory device having a fuse opening portion for cutting a fuse line, a capacitor including an upper electrode, and a guard ring surrounding the fuse opening portion, the method comprising: forming an etch stop layer over the fuse line and in a region, in which the guard ring is to be formed, concurrently with the upper electrode of the capacitor, the etch stop layer being formed of the same material as that of the upper electrode; forming a moisture barrier layer over the etch stop layer and at least in regions in which the guard ring and the fuse opening portion are formed; forming at least two levels of interlayer insulating films and at least two levels of interconnect wirings on the substrate including the etch stop layer, to form a multi-layer interlayer insulating layer structure in a fuse area and to form multi-level interconnect wirings, one of which is an uppermost interconnect wiring being formed in an area other than the fuse area, the interlayer insulating films alternating with the interconnect wirings; forming a guard ring opening portion having a ring shape surrounding the fuse opening portion by etching the multi-layer interlayer insulating layer structure until the etch stop layer is exposed; wherein said forming at least two levels of the interconnect wirings comprises depositing an uppermost wiring metal layer over the substrate including the guard ring opening portion to fill the guard ring opening portion with the uppermost wiring metal layer; patterning the uppermost wiring metal layer to complete the multi-level interconnect wirings and to form the guard ring; forming a passivation layer over the guard ring; and forming the fuse opening portion by etching the passivation layer and the multi-layer interlayer insulating layer structure.