Patent ID: 6131157
Filing Date: 2000-10-10
Classification: G06F

Abstract:
A superscalar processor that executes a group of instructions out of a program order, the superscalar processor comprising:a register renaming circuit that assigns tags to instructions;an index-addressable temporary buffer that stores results of executed instructions, wherein at least part of a tag assigned to an instruction indicates a location in said index-addressable temporary buffer where an execution result for the instruction is to be stored;a register array that stores results of instructions that are retirable;data dependency checking logic that determines whether an executed instruction is retirable, wherein an executed instruction is retirable if there are no unexecuted instructions appearing earlier in program order relative to said executed instruction; andan instruction retirement unit that retires approximately simultaneously a group of retirable instructions by transferring execution results of said group of retirable instructions from said index-addressable temporary buffer to said register array, wherein said execution results of said group of retirable instructions are retrieved from said index-addressable temporary buffer based on at least part of each tag assigned to an instruction in said group of retirable instructions.