Patent ID: 6455408
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A method for manufacturing semiconductor devices, said method comprising:providing a semiconductor wafer having a semiconductor substrate including a plurality of chip pads; applying a passivation layer on the semiconductor substrate, and providing openings in said passivation layer to expose said chip pads; forming a first polymer layer on the passivation layer; forming a first barrier metal layer on the chip pads and the first polymer layer; forming a plurality of redistribution patterns on the first barrier metal layer, each redistribution pattern having a portion connected to the chip pads and having an aperture formed through each redistribution pattern, the aperture formed within a bump pad area; forming a second barrier metal layer on the plurality of redistribution patterns, the second barrier metal layer being disposed within the aperture and contacting the first barrier metal layer; forming a third barrier metal layer on the second barrier metal layer, the third barrier metal layer comprising a concave pattern in said bump pad area, said concave pattern having sidewalls; forming a second polymer layer on the first polymer layer and the second barrier metal layer; forming a solder bump on said bump pad area such that said solder bump contacts said sidewalls of said concave pattern.