Patent ID: 8223044
Filing Date: 2012-07-17
Classification: H03M

Abstract:
1. A SAR ADC comprising: (a) a first CDAC receiving a first analog input signal and including a plurality of CDAC capacitors each having a first terminal coupled to a first conductor; (b) a first correction capacitor circuit including a correction capacitor having a first terminal coupled to the first conductor; (c) a comparator having a first input coupled to the first conductor; (d) SAR logic circuitry having an input coupled to an output of the comparator and also having a first output bus coupled to control a plurality of switches coupled to second terminals of the capacitors of the first CDAC, respectively, for selectively coupling the second terminals of the capacitors of the first CDAC to either a first reference voltage or a second reference voltage, the SAR logic circuitry producing a digital signal representative of the first analog input signal; and (e) decoder circuitry having a first output bus coupled to control a switch coupled to a second terminal of the correction capacitor to selectively couple the second terminal of the correction capacitor to either the first reference voltage or a third reference voltage in response to stored INL error information so as to correct INL errors in a transfer characteristic of the SAR ADC.