Patent ID: 6011411
Filing Date: 2000-01-04
Classification: H03K

Abstract:
A logic circuit for receiving a plurality of input signals each having a high or low level, wherein the circuit outputs a high or low output signal, the circuit comprising:a plurality of MOS transistors including a first MOS transistor and a second MOS transistor, each MOS transistor having one of a first conductivity and a second conductivity, said first MOS transistor being connected to one of the plurality of input signals, said second MOS transistor being connected to a power supply, said plurality of MOS transistors operating to produce the output signal in response to an another at least one input signal of the plurality of input signals, wherein the output signal has either substantially the same level as the one input signal or the level of the power supply; andan output signal stabilizing circuit, connected between a low-potential power supply and a high-potential power supply, for stabilizing the level of the output signal between the level of the high-potential power supply and the level of the low-potential power supply.