Patent ID: 6549989
Filing Date: 2003-04-15
Classification: G06F

Abstract:
A method, in a data processing system including a plurality of processors and a multiple-level memory hierarchy maintaining coherency using a coherency protocol, said method comprising:setting a reservation indicator associated with a particular processor which specifies a selected address for which the processor holds a reservation; thereafter, modifying contents of a memory unit corresponding to the selected address through the execution of first and second store-conditional instruction targeting the selected address; in response to execution of the first store-conditional instruction, setting a coherency state indicator associated with said selected address to a first modified state that indicates that particular processor has retained the reservation for the selected address; and in response to execution of the second store-conditional instruction, setting the coherency state indicator associated with the selected address to a second modified state that indicates that the particular processor has released the reservation for the selected address.