Patent ID: 8019944
Filing Date: 2011-09-13
Classification: G06F,Y02D

Abstract:
1. A circuit for tracking memory operations in an out-of-order and speculative processor, wherein the circuit is adapted for use with a trace unit and with an execution unit of the processor, where the trace unit sequences traces for execution thereby forming a trace sequence order, where each of the traces includes a sequence of operations that includes zero or more of the memory operations, where the execution unit executes the operations, and where the circuit comprises: a first memory configured to cache at least some of the data accessed by the memory operations, where the memory operations being executed form a set of active memory operations, a second memory configured to receive and hold a set of checkpoint entries, a first sub-circuit configured to hold a memory operation ordering entry corresponding to each one of the active memory operations, a second sub-circuit configured to receive the memory ordering violation signal and to determine whether a particular occurrence of the memory ordering violation signal was too late to prevent the updating and, if so, to overwrite in the first memory a set of the checkpoint locations based on a selected one of the particular traces,