Patent ID: 7500021
Filing Date: 2009-03-03
Classification: G06F

Abstract:
1. An operation mode control circuit in a microcomputer, resettable by a reset signal from the outside, for performing processes under the control of a control program, the operation mode control circuit comprising: a control signal generator for generating a first output signal, being output during a first subsequence for a reset of the microcomputer and for generating a second output signal for setting an operation mode of an input and output circuit; a write protection circuit for generating a buffer signal in response to a first signal of the first output signal; and a control circuit for latching the a second output signal from the control signal generator in response to the buffer signal from the write protection circuit, wherein the control circuit sets an operation mode of an input and output circuit, which receives a signal from and sends a signal to the outside, in accordance with the latched second output signal, wherein the write protection circuit comprises: buffer units for outputting a buffer signal that is a buffered version of a first signal of the first output signal and outputting a fixed logical value signal in response to the first output signal excluding the first signal of the first out put signal output from the control signal generator; and latch units for performing a latch process in response to the first output signal from the control signal generator and for outputting a status signal indicating a latch status thereof, wherein the buffer units has an input terminal for receiving the status signal from the latch units, and outputs the fixed logical value signal if the status signal indicates the latch status, or outputs the buffer signal if the status signal does not indicate the latch status.