Patent ID: 6400194
Filing Date: 2002-06-04
Classification: H03K,H04L

Abstract:
A synchronous feedback digital circuit, comprising:a data input for receiving an input data stream; a plurality of logic circuits connected to said data input; a plurality of clocked registers connected to said logic circuits; a clock generator for generating an operating clock signal at an operating clock period; a signal generating device connected to said clock generator and to said clocked registers for generating phase-shifted clock signals for said clocked registers, the phase-shifted clock signals having a phase shift &phgr;i for a specific said register &varphi;N-i-1=N-[i&it;â€ƒ&it;mod&it;â€ƒ&it;N]-1N&CenterDot;Twhere T is an operating clock period of the operating clock signal, N is a factor, i is a number of registers between said register clocked by the phase-shifted clock signal and said data input of the digital circuit.