Patent ID: 7714827
Filing Date: 2010-05-11
Classification: G09G

Abstract:
1. An integrated circuit for scan driving being used in sequentially selecting and driving scanning lines in a display, which has said plural scanning lines and plural signal lines arranged crossing each other in a matrix configuration, and which has a pixel arranged at each cross point; in this integrated circuit for scan driving, comprising: a chip, having plural output pads arranged as a column in a first direction, plural drive circuits for driving said scanning lines to the active state through said output pads, respectively, and plural selection circuits for individually selecting said driver circuits in a line-sequential scanning cycle in an order corresponding to the order of said scanning lines; the odd-numbered output pads, driver circuits and selection circuits corresponding to odd-numbered scanning lines are all arranged in a first region, the even-numbered output pads, driver circuits and selection circuits corresponding to the even-numbered scanning lines being all arranged in a second region adjacent to said first region in said first direction; said first region, in an order corresponding to the order of said odd-numbered scanning lines, said odd-numbered output pads, driver circuits and selection circuits being arranged as columns in said first direction, respectively, and, at the same time, said output pads, driver circuits and selection circuits corresponding to each of the scanning lines are arranged in the same row in the second direction nearly orthogonal to said first direction; in said second region, in an order corresponding to the order of said even-numbered scanning lines, said even-numbered output pads, driver circuits and selection circuits are arranged as columns in said first direction, and, at the same time, said output pads, driver circuits and selection circuits corresponding to each of the scanning lines being arranged in the same row in said second direction; said odd-numbered selection circuits are made of individual flip-flops that overall form the first shift register; the first shift data provided by the frame period is transferred sequentially to the latter-stage flip-flops in synchronization with the first transfer clock signal at a frequency half that of the line-sequential scanning cycle; by means of the output signals of the flip-flops with said first shift data latched in them, the corresponding driver circuits are selected; said even-numbered selection circuits are made of individual flip-flops that overall form the second shift register; the second shift data provided by frame period is transferred sequentially to the latter-stage flip-flops in synchronization with the second transfer clock signal at a frequency half that of the line-sequential scanning cycle and in a phase opposite to that of said first transfer clock signal; and, by means of the output signals of the flip-flops with said second shift data latched in them, the corresponding driver circuits are selected.