Patent ID: 6189052
Filing Date: 2001-02-13
Classification: G06F

Abstract:
An on-chip i/o-processor for controlling and communication with peripheral devices, characterized by an i/o-processor core (12), comprising at least one pin controller (29) for reading and setting physical i/o-pins (6), starting timers and generating interrupts for the i/o-processor core (12), at least one timer (26) for sampling i/o-pins (6), setting i/o-pins (6) and generating interrupts for the i/o-processor core (12) at well defined points of time, said i/o-processor core (12) providing instructions for controlling said at least one pin controller (29), said at least one timer (26) and i/o-pins (6), an on chip RAM (3) holding instructions for the i/o-processor core (12), at least one register (4) for exchanging information between the i/o-processor (2) and a connected CPU (1) on the same chip and inversely, configurable logic (5), connected between said core (12) and said i/o-pins (6), for synchronization of incoming and/or outgoing signals.