Patent ID: 9171595
Filing Date: 2015-10-27
Classification: G11C

Abstract:
1. A semiconductor device comprising: a first memory macro having memory cells arranged in a first number of rows; and a second memory macro having memory cells arranged in a second number of rows, said first negative bias reference voltage generation unit generates a first negative bias reference voltage based on a first resistance ratio between a first resistor and a second resistor, and outputs the first negative bias reference voltage to a first negative bias reference interconnection, said second negative bias reference voltage generation unit generates a second negative bias reference voltage based on a second resistance ratio between a third resistor and a fourth resistor, and outputs the second negative bias reference voltage to a second negative bias reference interconnection, said first negative bias voltage generation circuit generates said first negative bias voltage based on said first negative bias reference voltage, said second negative bias voltage generation circuit generates said second negative bias voltage based on said second negative bias reference voltage, and said first resistance ratio is different from said second resistance ratio.