Patent ID: 8724401
Filing Date: 2014-05-13
Classification: G06F,G11C

Abstract:
1. A flash memory device comprising: a plurality of programmable devices that are configured to simultaneously store data; a plurality of erasure blocks within each of the plurality of programmable devices, each of the plurality of erasure blocks having pages of transistors; and a plurality of stripes, each of the plurality of stripes having a width that includes more than one and less than all of the plurality of programmable devices within the flash memory device, wherein at least one of the plurality of stripes has a height of more than one page of transistors, and wherein each of the pages of transistors corresponds to a unique set of logical block addresses, and wherein a logical block addressing scheme utilized in the flash memory device employs logical block addresses, including the unique set of logical block addresses, that consecutively number the pages within the width and the height of each one of the plurality of stripes, and wherein different ones of the pages within at least one of the plurality of erasure blocks are non-consecutively numbered by the logical block addresses due to the different ones of the pages being distributed amongst different ones of the plurality of stripes.