Patent ID: 6797563
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A method for manufacturing a dynamic random access memory (DRAM) device, said method comprising the steps of:providing a substrate of semiconductor material having a main outer surface; said main outer surface of said substrate, each of said pillars having a pillar outer surface, said pillars being formed using a first mask, said pillars being electrically isolated from each other and including an active region of said semiconductor material; forming a plurality of substantially parallel bit lines located outwardly of said main outer surface of said substrate, each of said bit lines having a bit line width defined by first and second bit line edges and being separated from adjacent bit lines by a bit line separation distance, said bit lines being formed using a second mask; forming a plurality of pillars of semiconductor material extending outward from interconnecting said bit lines with said pillar outer surfaces via a plurality of bit line plugs so as to form, at intersections of said bit line plugs with said pillar outer surfaces, a plurality of bit line contacts and one of sources and drains of a plurality of MOS transistors; forming at least one hole region defined by a hole floor and at least one hole wall in each of said plurality of pillars, said hole floors being located outwardly of said main outer surface of said substrate; forming a plurality of substantially parallel word lines located outwardly of said main outer surface of said substrate, each of said word lines having a word line width defined by first and second word line edges and being separated from adjacent word lines by a word line separation distance, said word lines being substantially perpendicular to said bit lines, said word lines being formed using a third mask, a given one of said first and second word line edges of a given one of said word lines and a given one of said first and second bit line edges of a given one of said bit lines intersecting substantially outward of a center of a given one of said active regions; locating a word line plug in each of said hole regions, each of said word line plugs extending from a corresponding adjacent one of said word lines inwardly into said hole region and terminating outward of said hole floor, each of said word line plugs being electrically isolated from said semiconductor material of said pillar such that a portion of each of said word line plugs adjacent to and electrically isolated from said semiconductor material of said pillar forms a gate of said MOS transistor with a corresponding portion of said semiconductor material of said pillar forming a channel region of said MOS transistor; forming a plurality of storage nodes, one for each of said active regions, each of said storage nodes being offset from its corresponding one of said active regions in a direction away from said given one of said word lines and said given one of said bit lines which intersect substantially outwardly of said center of said given one of said active regions, said storage nodes being formed using a fourth mask; and interconnecting said storage nodes with said hole floors of said pillars via a plurality of storage node plugs so as to form, at intersections of said storage node plugs with said hole floors, a plurality of storage node contacts and another of sources and drains of said plurality of MOS transistors, said storage node plugs extending through said hole regions in said pillars and being electrically isolated from said hole walls and said word line plugs.