Patent ID: 7327176
Filing Date: 2008-02-05
Classification: H03K,H03L

Abstract:
1. A delay locked loop device for generating an internal clock signal synchronized with an input clock signal, said delay locked loop device comprising: a first phase detection circuit for comparing the rising phase of said input clock signal and the rising phase of said internal clock signal; a second phase detection circuit for comparing the falling phase of said input clock signal to the falling phase of said internal clock signal; first and second variable delay circuits having delays thereof varied by the results of phase comparison in said first and second phase detection circuits; the rising and fall of said internal clock signal, obtained on multiplexing outputs of said first and second variable delay circuits, being adjustable independently of each other; a mode decision circuit for determining the clock period and an initial delay value by comparison; a first selection circuit for selecting for control of which of said first and second variable delay circuits the results of phase comparison by said first and second phase detection circuits are to be used; and a second selection circuit for switching, in multiplexing signals output from said first and second variable delay circuits to generate said internal clock signal, between the use of the rise and the fall of signals output from said first and second variable delay circuits for the rising of said internal clock signal, and the use of the rise and the fall of signals output from said first and second variable delay circuits for the fall of said internal clock signal, based on the result of mode decision.