Patent ID: 7245160
Filing Date: 2007-07-17
Classification: G01R

Abstract:
1. A short pulse rejection circuit, comprising: a signal detected and converted circuit for receiving an input pulse signal and generating a detected pulse while said input pulse signal has a pulse edge raising or falling; a control signal generating circuit generating a first control signal and a second control signal while receiving said detected pulse, wherein said control signal generating circuit is composed of a first inverter, a second inverter, a third inverter, a first D flip-flop, and a second CMOS, and still said first inverter, second inverter, and third inverter are connected in series to a clock terminal of said first D flip-flop and said first D flip-flop is with a power source as an input signal and has an output terminal connecting to an input terminal of said second CMOS; a resetting and charging circuit including a pMOS and a nMOS and a capacitor, said nMOS and said capacitor in parallel connected and said pMOS cascode thereover, still said first control signal and said second control signal being connected, respectively, to input terminals of said pMOS and said nMOS to determine charging or discharging of said capacitor; a capacitor pulse detected and signal outputting circuit in series connected to said resetting and charging circuit to generate a desired output signal free from any short pulse while said capacitor is charged and with a terminal voltage of said capacitor over a predetermined voltage.