Patent ID: 8332619
Filing Date: 2012-12-11
Classification: G06F

Abstract:
1. An apparatus comprising: decode logic configured to decode a first instruction including a first prefix and a second instruction including a second prefix; execution logic coupled to the decode logic, the execution logic configured to speculatively execute a critical section demarcated by the first instruction and the second instruction in response to the decode logic decoding the first instruction including the first prefix and the second instruction including a second prefix; buffer logic coupled to the execution logic, the buffer logic configured to buffer memory updates from the critical section during the execution logic speculatively executing the critical section; monitor logic associated with the buffer logic, the monitor logic configured to track contention from other threads to memory locations accessed during the execution logic speculatively executing the critical section; and atomic commit logic coupled to the buffer logic and the monitor logic, the atomic logic configured to atomically commit the memory updates to memory in response to the decode logic decoding the second instruction and the monitor logic not tracking contention from other threads to memory locations accessed during the execution logic speculatively executing the critical section.