Patent ID: 7958429
Filing Date: 2011-06-07
Classification: H03M

Abstract:
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising: a plurality of registers and a plurality of multiplexers (MUXs) configured in a daisy chain, wherein the plurality of registers is operable to store both bit edge messages and check edge messages and the plurality of MUXs is interposed amongst the plurality of registers; and a check engine that is operable to employ a first bit edge message to update a first check edge message thereby generating a second check edge message; and a bit engine that is operable to: the soft information corresponding to the information bit encoded into the LDPC coded signal is used to make a best estimate of the information bit encoded into the LDPC coded signal; each register of the plurality of registers corresponds to a non-null location within a sub-matrix of a parity check matrix of an LDPC code by which the LDPC coded signal is generated; each register of the plurality of registers is operable to shift a check edge message or a bit edge message contained therein by one location; during bit node processing, a first select signal is provided to the plurality of MUXs that is interposed amongst the plurality of registers to ensure a check edge message is provided from at least one register of the plurality of registers to the bit engine; and during check node processing, a second select signal is provided to the plurality of MUXs that is interposed amongst the plurality of registers to ensure a bit edge message is provided from at least one register of the plurality of registers to the check engine.