Patent ID: 6560155
Filing Date: 2003-05-06
Classification: G11C

Abstract:
A DRAM memory, having circuitry to refresh its memory cells, and being responsive to external refresh commands and an external address signal, comprising:a DRAM array comprised of rows of DRAM memory cells that must be refreshed after an extended refresh interval; a row addressing system operably connected to the DRAM array, the row addressing system responsive to a row address signal by accessing a row in the DRAM array corresponding to the row address signal; a refresh controller generating a refresh signal; a refresh counter operably connected to the row addressing system, sequentially generating the row address signal of each row in the DRAM array in response to a delayed refresh signal; and a delay counter operably connected to the row addressing system, the refresh controller, and the refresh counter, the delay counter generating the delayed refresh signal causing the rows of DRAM memory cells comprising the DRAM array to be refreshed after the extended refresh interval has passed, the delay counter measuring the extended refresh interval by counting a number of the refresh signals received from the refresh controller.