Patent ID: 7161843
Filing Date: 2007-01-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising a memory array including a plurality of memory cells capable of storing data of at least 1 bit, the semiconductor memory device comprising: a data write control section for controlling a data write operation to the plurality of memory cells; an address signal generation section for generating an address signal which represents an address of a prescribed memory cell to which data is to be written, among the plurality of memory cells; a data read section for reading data from the prescribed memory cell; a buffer section for temporarily storing data to be written to the prescribed memory cell; a determination section for determining whether or not to write data to the prescribed memory cell and outputting a first write signal based on the determination result; a data register section for storing data represented by the first write signal and outputting a second write signal based on the stored data; and a data write section for writing data to the prescribed memory cell based on the second write signal, wherein the data register section stores the data represented by the first write signal based on a control signal which is output by the data write control section.