Patent ID: 6512282
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A semiconductor device comprising:a gate insulating film formed on a semiconductor substrate; a buried gate electrode formed on the gate insulating film; an upper insulating film formed on the buried gate electrode; a sidewall insulating film formed on side faces of the buried gate electrode and the upper insulating film; a trench isolation film self-aligned with the buried gate electrode, the upper surface of the isolation film being located at a level higher than the upper surface of the buried gate electrode, the lower surface of the isolation film being located at a level lower than the upper surface of the substrate at least on a cross section of the device taken in a gate length direction; source/drain diffused regions defined in respective regions of the substrate beside the buried gate electrode; and source/drain contacts formed between the sidewall insulating film and the isolation film and self-aligned with the buried gate electrode to make electrical contact with the source/drain diffused regions, wherein the size of the buried gate electrode as measured in the gate width direction is larger than that of the source/drain contacts, and the buried gate electrode protrudes laterally on both sides of the source/drain contacts in the gate width direction.