Patent ID: 8665624
Filing Date: 2014-03-04
Classification: G06F,G11C

Abstract:
1. A semiconductor system comprising: a host device including a CPU; and a semiconductor device; wherein the semiconductor device comprises: a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view; a connector to be connectable to the host device; a volatile semiconductor memory element provided on a front surface layer side of the substrate; a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; and a controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements, wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, and wherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element, wherein the CPU writes information on the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element through the connector.