Patent ID: 6430179
Filing Date: 2002-08-06
Classification: H04Q

Abstract:
A signal router having M input terminals and N output terminals and comprising:an input router stage having M inputs connected respectively to the M input terminals of the router and composed of M/m router modules each having m inputs, p outputs and a first switch means for selectively connecting any one of the m inputs to any one of the p outputs, and an intermediate router stage composed of p router modules each having M/m inputs and N/n outputs and a second switch means for selectively connecting any one of the M/m inputs to any one of the N/n outputs, an output router stage composed of N/n router modules each having p inputs and n outputs and a third switch means for selectively connecting any one of the p inputs to any one of the n outputs, p*(M/m) input stage clocked storage elements connected respectively between the outputs of the router modules of the input router stage and the inputs of the router modules of the intermediate router stage, the input stage clocked storage elements being responsive to a trigger event of a clock signal to capture a signal level present at the ith output of the jth router module of the input router stage (1<=i<=p; 1<=j<=M/m) and hold the signal level at the jth input of the pth router module of the intermediate router stage until a subsequent trigger event of the clock signal, p*N/n intermediate stage clocked storage elements connected respectively between the outputs of the router modules of the intermediate router stage and the inputs of the router modules of the output router stage, the intermediate stage clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the kth output of the lth router module of the second router stage (1<=k<=N/n; 1<=1<=p) and hold the signal level at the lth input of the kth router module of the output router stage until a subsequent trigger event of the clock signal, and N output stage clocked storage elements connected respectively between the outputs of the router modules of the third router stage and the output terminals of the router, the output stage clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the uth output of the vth router module of the third router stage (1<=u<=n; 1<=v<=N/n) and hold the signal level at the (n*v+u)th output terminal of the router until a subsequent trigger event of the clock signal.