Patent ID: 8599632
Filing Date: 2013-12-03
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a built-in self-test circuit configured to conduct a test on memory; and a memory block comprising a plurality of memories, the built-in self-test circuit comprising: an address generator configured to generate an address signal comprising an address of memory; a data generator configured to generate data to be written to memory and expected value data corresponding to the data to be written; a chip enable signal generator configured to generate a chip enable signal for controlling memory; and a control signal generator configured to generate a control signal for controlling a writing operation and a reading operation of memory, the memory block comprising: the plurality of memories; an address converter configured to generate, based on the address signal, an address input signal corresponding to an address of a memory to be tested of the plurality of memories, and configured to generate a memory selection signal for selecting the memory to be tested; and a memory output selector configured to select and output data from the memory to be tested based on the memory selection signal.