Patent ID: 6284604
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method for producing a field-effect-controllable, vertical semiconductor component, which comprises the following steps:depositing various epitaxial layers of an inner zone on a bulk region of a semiconductor body;epitaxially depositing drain and source zones on the inner zone;introducing contact regions and highly doped source regions by ion implantation;after introducing the contact regions and the highly doped source regions, anisotropically etching intercell zones;introducing channel zones by ion implantation using an etching mask;thermally applying a thin silicon dioxide layer as a gate oxide to trench walls of the intercell zones using the etching mask, filling the intercell zones with polysilicon as a gate material, etching excess polysilicon out of the intercell zones, and filling the intercell zones with silicon dioxide as a gate material;structuring the front wafer side once again, and anisotropically etching trenches down to a depth of the bulk zone in the region of the source zones;applying a thin oxide to walls of the trenches, and filling the trenches with conductive material;metallizing a source terminal over a large surface area on a rear wafer side;metallizing a drain terminal and a gate terminal on the front wafer side at corresponding contacts and insulating the drain and gate terminals from one another with an intermediate oxide; andconductively securing the source terminal to a cooling body with a solder.