Patent ID: 6812751
Filing Date: 2004-11-02
Classification: H03K

Abstract:
A power-on reset circuit comprising:an output stage circuit providing a power-on reset indication on an output line while a gate-to-source voltage of an output transistor of said output stage circuit is near a threshold voltage so as to turn said output transistor on with minimal current passing through said output stage circuit, wherein said output transistor is a first PMOS transistor having a gate, a source coupled to said power line, and a drain coupled to said output line and wherein said output stage circuit includes a first NMOS transistor having a gate, a drain coupled to said first PMOS transistor drain, and a source coupled to a ground line so as to pull a voltage on said output line down to ground to generate said power-on reset indication when turned on; and a charging circuit coupled to a power line and said output stage circuit so as to generate and hold said gate-to-source voltage of said output transistor when power to said power line is turned on or reset, said charging circuit including a first capacitor coupled between said first NMOS transistor gate and said ground line, and an input circuit generating and holding a first voltage provided to said first PMOS transistor gate so as to generate and hold said gate-to-source voltage of said first PMOS transistor, and charging up said first capacitor to a second voltage so as to turn said first NMOS transistor on when said power on said power line is turned on or reset wherein said input circuit includes a second PMOS transistor having a gate, a drain, and a source coupled to said power line, a second NMOS transistor having gate coupled to said gates of said first PMOS and said second PMOS transistors, a drain coupled to said second PMOS transistor drain and said gates of said second PMOS, said first PMOS, and said second NMOS transistors, and a source is coupled to said first NMOS transistor gate and said first capacitor, and a second capacitor coupled between said coupled gates of said second PMOS, said first PMOS, and said second NMOS transistors, and said ground line.