Patent ID: 8487372
Filing Date: 2013-07-16
Classification: H01L

Abstract:
1. A semiconductor power device layout consisted of dual trench MOSFETs wherein each of said dual trench MOSFETs comprising: multiple trenched floating gates formed in parallel in a termination area around outside of an active area, said multiple trenched floating gates having floating voltage and surrounded by body regions without having source regions, said multiple trenched floating gates having trench depth equal to or deeper than body junction of said body regions; at least one trenched channel stop gate formed in said termination area and around outside of said multiple trenched floating gates, each said trenched channel top gate being connected to at least one sawing trenched gate, each said sawing trenched gate being extended across over a space between said dual trench MOSFETs and connected with said trenched channel stop gate of said dual trench MOSFETs.