Patent ID: 6636455
Filing Date: 2003-10-21
Classification: G11C

Abstract:
A semiconductor memory device that takes in an external control signal, an external address signal, and an external data signal in synchronization with a clock signal, said semiconductor memory device comprising:a memory array having a plurality of memory cells arranged in plural rows and plural columns, a plurality of word lines respectively disposed in correspondence with said plural rows, and a plurality of bit line pairs respectively disposed in correspondence with said plural columns; a row selection circuit that takes in said external address signal as a row address signal in response to an active command being issued by said external control signal, selects one of said plurality of word lines in accordance with the row address signal, and activates each memory cell corresponding to the selected word line; a column selection circuit that takes in said external address signal as a column address signal in response to a writing command being issued by said external control signal, and selects one of said plurality of bit line pairs in accordance with the column address signal; and a writing circuit that, in a normal operation mode, takes in said external data signal when a predetermined first period of time passes after said writing command is issued following said active command and, in a testing mode, receives said external data signal without waiting for the elapse of said predetermined first period of time in response to said active command being issued, to write the external data signal into the memory cell activated by said row selection circuit via the bit line pair selected by said column selection circuit.