Patent ID: 8031542
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A read only memory, comprising: a word line; a read only memory array comprising a first transistor having a drain, a source, a gate and a bulk, the gate directly connected to the word line, wherein the drain, the source, the gate and the bulk are directly connected to a logic zero during an idle state for ensuring zero junction and sub-threshold leakage current; a first reference bit line directly connected to receive a clock signal and to provide a stop-read signal at the end of a read cycle; a second transistor directly coupled to the drain of the first transistor and a main bit line, the second transistor to pre-charge the main bit line during a read cycle; a second reference bit line directly connected to receive the clock signal and to provide a stop pre-charge signal to the second transistor; and a first sensing unit directly connected to the second reference bit line to generate the stop pre-charge signal when the second reference bit line pre-charges to a predetermined level.