Patent ID: 7587659
Filing Date: 2009-09-08
Classification: H03M

Abstract:
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising: a controller that provides a modulation/code signal indicating at least one of a respective code rate and a respective modulation corresponding to each respective symbol of the LDPC coded signal, each symbol of the LDPC signal having a respective in-phase (I) value, a respective quadrature (Q) value, and a respective signal to noise ratio; a metric generator circuitry that includes a symbol metric calculator circuitry and a bit metric calculator circuitry, wherein: a plurality of macro circuitries, coupled to the bit metric calculator circuitry, such that each of the plurality of macro circuitries includes: a hard limiter, coupled to the plurality of macro circuitries, that generates a hard decision corresponding to at least one bit encoded within the LDPC coded signal based on a most recently updated plurality of bit edge messages.