Patent ID: 6858903
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. An FET device comprising: a semiconductor substrate having a top surface; a gate dielectric layer formed on the top surface of the semiconductor substrate, a conductive gate electrode having a top, a base, and sidewalls, with the conductive gate electrode being formed over the gate dielectric layer with an interface therebetween, with the interface extending between the sidewalls and any layers formed thereover at the base of the conductive gate electrode; the gate dielectric layer having rounded surfaces at the base of the gate electrode extending outwardly from the sidewalls; a channel region formed in the semiconductor substrate below the gate electrode and the gate dielectric layer; and a silicon layer covering the device forming a raised doped source region and a raised doped drain region protruding above the top surface of the semiconductor substrate and beyond an exterior surface level of the gate dielectric layer.