Patent ID: 6818489
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising:forming an insulated gate pattern on a semiconductor substrate; forming low-concentration source/drain regions in the substrate adjacent the gate pattern; forming a first conformal etch stop layer on the substrate having the low-concentration source/drain regions; forming a spacer on the etch stop layer overlying sidewalls of the gate pattern; implanting impurity ions into the substrate having the low-concentration source/drain regions using the gate pattern and the spacer as implantation masks to form high-concentration source/drain regions; removing the spacer; and forming an interlayer insulating layer on the substrate where the spacer is removed, wherein forming the interlayer insulating layer is followed by sequentially patterning the interlayer insulating layer and the first etch stop layer to form a contact hole exposing an LDD-type source/drain region composed of the low-concentration source/drain region and the high-concentration source/drain region.