Patent ID: 8314423
Filing Date: 2012-11-20
Classification: H01L

Abstract:
1. A thin film transistor array substrate, comprising: a substrate; a first patterned conductive layer disposed on the substrate, the first patterned conductive layer comprising a plurality of scan lines and a plurality of gates connected with the scan lines; a patterned gate insulating layer disposed on the substrate to cover the first patterned conductive layer, the patterned gate insulating layer having a plurality of openings; a plurality of dielectric patterns located in the openings, a dielectric constant of the dielectric patterns being smaller than a dielectric constant of the patterned gate insulating layer; a plurality of semiconductor patterns disposed on the patterned gate insulating layer, the semiconductor patterns comprising a plurality of channel layers separated from one another; a second patterned conductive layer disposed on the semiconductor patterns, and the dielectric patterns, the second patterned conductive layer comprising a plurality of data lines, a plurality of sources connected with the data lines, and a plurality of drains; a passivation layer disposed on the semiconductor patterns, the patterned gate insulating layer, and the dielectric patterns to cover the second patterned conductive layer; and a plurality of pixel electrodes disposed on the passivation layer, each of the pixel electrodes being electrically connected with corresponding one of the drains, respectively.