Patent ID: 6061283
Filing Date: 2000-05-09
Classification: G01R

Abstract:
A semiconductor integrated circuit evaluation system, comprising:a test pattern file for storing a test pattern composed of an input pattern to be applied to a device for testing the device under test and an expected value pattern to compare with an output signal of the device under test responsive to the input pattern;a first memory for storing tester event information by receiving a predetermined amount of test pattern from the test pattern file;a first FIFO (first-in-first-out) for receiving a predetermined amount of the tester event information from the first memory and extracting the tester event information in the order of receiving the same;a second memory for storing device event information by receiving a predetermined amount of event information resulted from logic simulation of the device under test based on design data of the device produced through a computer aided design process;a second FIFO (first-in-first-out) for receiving a predetermined amount of the device event information from the second memory and extracting the device event information in the order of receiving the same;a comparator for comparing the event information from the first FIFO and the second FIFO; andmeans for generating a comparison result from the comparator.