Patent ID: 8181092
Filing Date: 2012-05-15
Classification: H04B,H04L

Abstract:
1. A system memory, comprising: a data link; a transmitter having one or more link control parameters coupled to the data link and operable to receive data and communicate the data through the data link; a receiver having one or more link control parameters coupled to the data link to receive data from the data link and operable to output the received data; a memory coupled to the receiver in the communications link, the memory operable during a synchronization mode to receive data from the receiver and compare the received data to expected values for the received data, the memory generating an error signal responsive to the comparison; and a memory controller coupled to the transmitter and receiver and coupled to the memory, the memory controller operable to apply control signals to adjust the values of the link control parameters of the transmitter and receiver and to apply a bit pattern to the transmitter at a plurality of potential values of the one or more associated link control parameters, and the memory controller adjusting the link control parameters to final values using the values of the generated error signals from the memory.