Patent ID: 6215704
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A semiconductor memory device for performing input/output of a data signal of M bit(s) (M: natural number) in response to an address signal of N bit(s) (N: natural number), comprising:a memory cell array having a plurality of memory cells arranged in rows and columns;an address decode circuit for selecting the memory cells of M in number from said plurality of memory cells in response to a combination of the respective bits of said address signal;a data I/O circuit for performing data input/output with respect to said selected M memory cells;a plurality of multi-function terminals commonly used by the input of said address signal and the input/output of said data signal;a first control terminal for receiving a first control signal/ADe for instructing input of said address signal to said plurality of multi-function terminals;a second control terminal/DQe for receiving of a second control signal for instructing input/output of said data signal to said plurality of multi-function terminals;a plurality of address register circuits provided between said plurality of multi-function terminals and said address decode circuit, respectively, and responding to activation of said first control signal by taking in the level of the signal supplied to said plurality of multi-function terminals, and transmitting said level to said address decode circuit; anda plurality of data register circuits provided between said plurality of multi-function terminals and said data I/O circuit, respectively, and responding to the activation of said second control signal by transmitting said data signal between said plurality of multi-function terminals and said data I/O circuit.