Patent ID: 7570511
Filing Date: 2009-08-04
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines, each of the memory cells including a variable resistance device in series with a diode; wherein the cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions; and wherein respective bit lines of each of the cell array layers are connected in common to respective column selector transistors or respective word lines of the cell array layers are connected in common to respective word line drivers; wherein bit lines other than a selected bit line are configured to be maintained at a floating state when a read voltage or a write voltage is applied to the selected bit line; and wherein bit lines in a cell array layer of the selected bit line are configured to be discharged to a ground voltage prior to a read operation.