Patent ID: 6624027
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A method of making an EEPROM structure with a tiny thin window using process equipment having a characteristic minimum feature dimension comprising:defining active regions of a substrate; forming a nitride mask with defined edges in a layer over a gate oxide layer deposited upon an active substrate region for the EEPROM structure; establishing buried implant regions in the active substrate region using defined edges of the nitride mask for source and drain self-alignment; etching down along an edge of the nitride mask and through the gate oxide layer to proximity with the substrate, thereby forming a spacer nest with a floor over one of the source and drain regions; forming a dummy nitride spacer on a side of the nitride mask in the spacer nest and resting on the floor of the nest, the nitride spacer adjacent to the nitride mask; simultaneously removing both the nitride mask and the dummy nitride spacer, thereby opening the spacer nest; depositing a layer of thin tunnel oxide across a portion of the substrate, including the floor of the spacer nest; and completing the EEPROM structure by depositing a poly one floating gate layer disposed over the gate oxide layer, the floating gate layer having a dip down region occupying the spacer nest above the thin tunnel oxide and by depositing a poly two control layer spaced from the poly one floating gate layer by an insulative layer, said one of the source and drain regions communicating electrical charge to the dip down region of the floating gate through the thin tunnel oxide.