Patent ID: 7603248
Filing Date: 2009-10-13
Classification: G01R

Abstract:
1. A testing circuit for a semiconductor device, comprising of: a pad formed in a cutting area of semiconductor wafer; a storage device which is formed in the cutting area of the semiconductor wafer and stores a test mode transition program, the test mode transition program including an instruction for changing a dividing frequency; and a control circuit that is formed in a chip area of the semiconductor wafer, decodes a Manchester coded signal input from the pad, and sets the test mode by the program stored in the storage device, wherein the control circuit comprises: a mode register in which the test mode is set; a test pad control circuit configured to decode the Manchester coded signal based on the program which is stored in the storage device and to generate a dividing frequency clock used when the Manchester coded signal is decoded by dividing a clock based on the instruction transmitted from the storage device; and an address and data selector configured to switch access to the storage device.