Patent ID: 6236623
Filing Date: 2001-05-22
Classification: G04R,H04J

Abstract:
A system for synchronizing clocks in a plurality of slave control device interconnected via a communication channel, said system comprising:a master control device comprising:master clock circuitry for maintaining an essentially fixed frequency output and a master time;a communication controller for periodically sending an interrogation signal to each of said slave control devices and receiving an acknowledgment signal from each of said slave control devices in response thereto, each said acknowledgment signal characterized by a time delay corresponding to each said slave control device; andan offset register for storing one or more time delay values corresponding to each said slave control device, said offset register storing said one or more time delay values between periodic interrogations of said slave control devices;at least one slave control device comprising:clock circuitry for maintaining a slave time;a communication controller for receiving said interrogation signal and sending said acknowledgment signal in response thereto; andan event controller for operating in association with said slave clock circuitry; anda communication channel for providing a bidirectional communication path between said master control device and each of said slave control devices for sending and receiving said interrogation and said acknowledgment signals wherein said slave communication controller is additionally responsive to a synchronization signal sent from said master control device across said communication channel, used in conjunction with an associated time delay value in said offset register, to cause said slave time to essentially synchronize with said master time.