Patent ID: 6111926
Filing Date: 2000-08-29
Classification: H03L,H04L

Abstract:
A bit synchronizing circuit comprising:an N-numbering counter which executes a counting operation in response to a clock having a clock speed N times higher than a bit rate of input data, N being an integer;an edge detector which detects an edge of a binary signal corresponding to the input data and which outputs an edge detection pulse responsive thereto;a reading device which reads a count value of said N-numbering counter every time said edge detector outputs one said edge detection pulse;a first counter which counts a total number of said edge detection pulses outputted from said edge detector within a first cycle defined between a first period when the count value of said N-numbering counter becomes a first predetermined value and when the count value of said N-numbering counter again becomes said first predetermined value;a judging circuit which judges a count value of said first counter every time the count value of said N-numbering counter becomes said first predetermined value, and which also judges a bit synchronization shift based on the count value of said N-numbering counter read by said reading device only when the count value of said first counter becomes a preselected value; andwherein said judging circuit outputs a correction signal used to correct the count value of said N-numbering counter based on a judgment result, and corrects the count value of said N-numbering counter in accordance with the correction signal.