Patent ID: 8816444
Filing Date: 2014-08-26
Classification: G03F,G06F,H01L

Abstract:
1. A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising: receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas and a plurality of planar contacts, each planar contact associated with a planar active area; defining, using a processor, a plurality of FinFET active areas corresponding to the planar active areas determining if at least one of each of the plurality of FinFET active areas is smaller than the corresponding planar active area; determining at least the at least one of the plurality of planar contacts does not sufficiently contact corresponding FinFET active areas; and creating a metal layer comprising metal lines to connect the at least the at least one of the plurality of planar contacts to portions of corresponding FinFET active areas.