Patent ID: 6046607
Filing Date: 2000-04-04
Classification: G06F,H03K

Abstract:
A semiconductor integrated circuit, which is disposed in a semiconductor chip, comprising:a clock signal delay device that is disposed within the semiconductor chip and generates a plurality of clock signals, each clock signal having a phase that is shifted by a small amount with respect to the other of the plurality of clock signals; anda plurality of circuit blocks collectively defining an integrated logic circuit,wherein each of the circuit blocks is capable of transferring and receiving data, is coupled to at least one neighboring circuit block, and is controlled by one of the plurality of clock signals,the amount of phase shift between any two of the plurality of clock signals that control a transferring circuit block and a corresponding receiving circuit block is small enough to cause the two clock signals to overlap, andthe phase shift of the clock signals is along a data transfer path defined by successive transferring and receiving circuit blocks.