Patent ID: 9129085
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A memory controller installed in an SIMD (Single Instruction Multiple Data) processor including N (N is an integer of 2 or more) number of processor elements having a capacity in S sized-units and a buffer to temporarily store data being transferred between an external memory and the applicable processor elements; the memory controller comprising: an address storage unit capable of setting N number of addresses Ai (i=1 through N) in the external memory; and a parameter storage unit capable of setting a first parameter OSV, a second parameter W, and a third parameter L; and a data transfer unit to transfer data between the buffers for the N number of processor elements and the external memory; wherein the data transfer unit repeatedly executes a first process a certain number of times matching the third parameter L stored in the parameter storage unit according to instructions of the data transfer, wherein the first process is a process that executes a fourth process along with a second process after repeatedly executing a third process along with a second process M times as shown in the formula (1); wherein the second process is a process that during the transfer of data from the external memory to buffers in the N number of processor elements, reads out data in S-sized unit portions from each address stored in the address storage unit and stores that data in the buffer of the corresponding processor element, so that one address corresponds to one processor element; wherein the second process is also a process that during transfer of data from buffers in the N number of processor elements to the external memory, reads out data stored in the buffers of each of the processor elements and writes that data into the corresponding address among N number of addresses stored in the address storage unit, so that one address corresponds to one processor element; wherein the third process is a process that increases each address Ai stored in the address storage unit according to the formula (2); and wherein the fourth process is a process that increases each address Ai stored in the address storage unit according to the formula (3); where W denotes the second parameter stored in the parameter storage unit, and S denotes the unit size where Ai denotes i-th address, and S denotes the unit size where Ai denotes i-th address, and OSV denotes the first parameter stored in the parameter storage unit, wherein in the control processor, the beginning address of N number of rectangular regions included within two-dimensional data, in the external memory storing a plurality of pieces of two-dimensional data arranged in S-sized units in two-dimensions, is set into the address storage unit as the N number of addresses Ai(i=1 through N), and the difference in addresses between the S-sized unit data at the beginning and end in the same row of the two-dimensional data, the size in the row direction of the rectangular region, and the number of rows of the rectangular region are set into the first parameter OSV, the second parameter W, and the third parameter L, respectively.