Patent ID: 7399700
Filing Date: 2008-07-15
Classification: H01L

Abstract:
1. A method of fabricating a dual damascene interconnection with a metal-insulator-metal capacitor, the method comprising: forming a via-level intermetal dielectric on a substrate where first and second lower metal interconnections are formed; forming a via hole for connecting a lower electrode of a metal-insulator-metal capacitor and the first lower metal interconnection by patterning the via-level intermetal dielectric; sequentially forming a metal layer for a capacitor lower electrode, a capacitor dielectric layer, and a metal layer for a capacitor upper electrode on the entire surface of the substrate; forming the metal-insulator-metal capacitor, which includes a lower electrode, a dielectric layer, and an upper electrode, by patterning the metal layer for the lower electrode, the capacitor dielectric layer, and the metal layer for the upper electrode, which are disposed over the via hole; forming a trench-level intermetal dielectric on the via-level intermetal dielectric including the metal-insulator-metal capacitor; simultaneously forming a groove including a via hole and a line trench for a dual damascene interconnection, exposing the second lower metal interconnection, and a second trench exposing the upper electrode by etching the via-level intermetal dielectric and the trench-level intermetal dielectric; and forming a dual damascene interconnection connected to the second lower metal interconnection and an upper metal interconnection connected to the upper electrode by filling the groove for the dual damascene interconnection and the trench with a metal.