Patent ID: 6822312
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A capacitor comprising:a first level of at least four electrically conductive parallel lines extending in a first direction and lying in a first plane, the first plane disposed above a substrate; at least a second level of at least four electrically conductive parallel lines extending in the first direction and lying in a second plane above the first plane, each of the second level lines being disposed over a respective one of the first level lines, such that the lines of the first and second levels are arranged in a series of at least four coplanar line pairs, each line pair comprising one of the first level lines and a respective one of the second level lines, the coplanar line pairs being substantially parallel to, and extending vertically upward from the substrate; a dielectric layer disposed between the first and second levels of conductive lines; a plurality of vias arranged in a plurality of groups, each group corresponding uniquely to one of the coplanar line pairs and each group including at least two vias connecting the first level line and the second level line of the corresponding line pair, thereby forming an array of at least four vertically oriented parallel capacitor plates, the vertically oriented parallel plates being spaced apart from each other, and only dielectric material being disposed between each of the vertically oriented parallel plates; and electrically opposing nodes forming the terminals of the capacitor, the array of vertically oriented parallel capacitor plates electrically connected to the opposing nodes in an alternating manner so that the vertically oriented parallel capacitor plates have alternating electrical polarities; wherein each vertically oriented parallel capacitor plate comprises a mesh structure.