Patent ID: 6834013
Filing Date: 2004-12-21
Classification: G11C

Abstract:
A method of erasing a non-volatile memory cell with a nitride tunneling layer, comprising:providing a non-volatile memory cell comprising a substrate, a nitride tunneling layer disposed on the substrate, a charge trapping layer having hot electrons and disposed on the nitride tunneling layer, a dielectric layer disposed on the charge-trapping layer, a gate conductive layer disposed on the dielectric layer, a source region and a drain region disposed in the substrate adjacent to the nitride tunneling layer; applying a first positive bias to the drain region; applying a second positive bias to the gate conductive layer; and grounding the source region and the substrate; wherein the first positive bias and the second positive bias are both sufficient to inject hot electron holes into the charge-trapping layer through the nitride tunneling layer to combine with hot electrons in the charge-trapping layer for erasing the non-volatile memory cell.