Patent ID: 8957882
Filing Date: 2015-02-17
Classification: G09G,G11C

Abstract:
1. A gate drive circuit comprising a shift register in which plural stages are cascade-connected to each other, an n-th stage (‘n’ is a natural number) comprising: an output node, connected through a first transistor of a pull-up part to a first clock signal, configured to output the n-th gate signal, wherein the control gate of the first transistor is connected to a first node; the pull-up part configured to pull up the output node to a high voltage of the fist clock signal as the high voltage of the n-th gate signal in response to a high voltage of the first node; a pull-down part configured to pull down the high voltage at the output node to a first low voltage level in response to an (n+1)th carry signal; a discharging part configured to discharge the first node down to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal or an (n+2)th carry signal; a carry part configured to output the high voltage in response to the high voltage at the first node while outputting the high voltage of the n-th gate signal; and a first holding part configured to holding the carry signal down to the second low voltage level while not outputting the high voltage of the n-th gate signal, wherein the discharging part comprises: a first discharging circuit configured to discharge the high voltage at the first node to the first low voltage or the second low voltage in response to the (n+1)th carry signal; and a second discharging circuit configured to discharge the high voltage at the first node to the second low voltage level in response to the (n+2)th carry signal.