Patent ID: 8519993
Filing Date: 2013-08-27
Classification: H02J

Abstract:
1. A dual voltage output circuit comprising: a first differential driving unit including a first input stage adapted for receiving a pair of first input voltages, and operable to generate first and second pairs of first intermediate voltages from the first input voltages, a first intermediate stage directly coupled to said first input stage for receiving the first and second pairs of first intermediate voltages therefrom, and operable to generate a pair of first control voltages from the first and second pairs of first intermediate voltages, said first intermediate stage having a first node to receive a first voltage level, and a second node to receive a second voltage level, and a first output stage directly coupled to said first intermediate stage for receiving the pair of first control voltages therefrom, and operable to generate a first output voltage from the pair of first control voltages, said first output stage being directly coupled to said first node of said first intermediate stage and having a first intermediate voltage node to receive a first intermediate voltage level that is between the first and second voltage levels; and a second differential driving unit including a second input stage adapted for receiving a pair of second input voltages, and operable to generate first and second pairs of second intermediate voltages from the second input voltages, a second intermediate stage directly coupled to said second input stage for receiving the first and second pairs of second intermediate voltages therefrom, and operable to generate a pair of second control voltages from the first and second pairs of second intermediate voltages, said second intermediate stage having a third node to receive the first voltage level, and a fourth node to receive the second voltage level, and a second output stage directly coupled to said second intermediate stage for receiving the pair of second control voltages therefrom, and operable to generate a second output voltage from the pair of second control voltages, said second output stage being directly coupled to said fourth node of said second intermediate stage and having a second intermediate voltage node to receive a second intermediate voltage level that is between the first and second voltage levels; wherein each of said first and second output stages includes a p-type transistor and an n-type transistor, each of which has a first terminal, a second terminal, and a control terminal, said control terminal of each of said p-type transistor and said n-type transistor of said first output stage is directly coupled to said first intermediate stage for receiving a respective one of the pair of first control voltages, said first terminals of said p-type transistor and said n-type transistor of said first output stage being directly coupled to each other, the first output voltage being outputted at said first terminals of said p-type transistor and said n-type transistor of said first output stage, said second terminal of one of said p-type transistor and said n-type transistor of said first output stage being directly coupled to said first node of said first intermediate stage, said second terminal of the other one of said p-type transistor and said n-type transistor of said first output stage being directly coupled to said first intermediate voltage node, and said control terminal of each of said p-type transistor and said n-type transistor of said second output stage is directly coupled to said second intermediate stage for receiving a respective one of the pair of second control voltages therefrom, said first terminals of said p-type transistor and said n-type transistor of said second output stage being directly coupled to each other, the second output voltage being outputted at said first terminals of said p-type transistor and said n-type transistor of said second output stage, said second terminal of one of said p-type transistor and said n-type transistor of said second output stage being directly coupled to said fourth node of said second intermediate stage, said second terminal of the other one of said p-type transistor and said n-type transistor of said second output stage being directly coupled to said second intermediate voltage node.