Patent ID: 6047373
Filing Date: 2000-04-04
Classification: G06F

Abstract:
An apparatus comprising:a configuration selector (CS) selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode;a programmable multiplexer, responsive to the CS, to assert a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the CS is configured to denote the configuration mode of operation;a storage medium, responsive to the CS, having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode, wherein the BIOS operates to facilitate user programming of a plurality of operating parameters for the apparatus;a processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio; anda bus, coupled to the programmable multiplexer, the processor and the storage medium, operates to provide instructions and data to the processor, including the BIOS, in a speed consistent with the asserted bus/core ratio.