Patent ID: 7421609
Filing Date: 2008-09-02
Classification: G06F,H03K

Abstract:
1. A circuit, comprising: a counter circuit operable to provide a counter signal corresponding to a set of timing intervals based upon an input clock signal having a first frequency, wherein the timing intervals occur at a second frequency which is a first ratio of the input clock signal and a duration of each of the timing intervals is a second ratio of the input clock signal; and a gating circuit coupled to the counter signal and operable to produce an output clock signal in a first mode of operation or a second mode of operation, wherein a third frequency of the output clock signal is substantially identical to the first frequency of the input clock signal in the first mode of operation and in the second mode of operation the gating circuit produces the output clock during each of the set of timing intervals, the output clock is held substantially constant between each of the timing intervals and the third frequency of the output clock is substantially identical to the first frequency of the input clock signal during each of the set of timing intervals.