Patent ID: 8656082
Filing Date: 2014-02-18
Classification: G06F

Abstract:
1. A memory system, comprising: a first group of serially-coupled memory cubes including a first portion of a plurality of memory devices, wherein each memory cube of the first group of serially-coupled memory cubes includes only one first memory device and only one first routing switch, and wherein each of the first portion of the memory devices is coupled to the first routing switch operably coupled to a source; a second group of serially-coupled memory cubes including a second portion of the plurality of memory devices, wherein each memory cube of the second group of serially-coupled memory cubes includes only one second memory device and only one second routing switch, and wherein each of the second portion of the memory devices is coupled to a second routing switch operably coupled to the source; and at least one bidirectional communications path that is configured to communicatively couple each of the first group and the second group to the source, wherein the first group and the second group are coupled in parallel to the source, in operation, wherein the first group and the second group are coupled in an intertwined manner to provide redundant communication paths, and wherein an output of each memory cube except for the last memory cube of the first group of serially-coupled memory cubes is directly coupled to an input of a memory cube of the second group of serially-coupled memory cubes.