Patent ID: 7532531
Filing Date: 2009-05-12
Classification: G11C

Abstract:
1. A method of performing a multi-block erase operation in a flash memory device, wherein the multi-block erase operation comprises first and second erase periods, the method comprising: in the first erase period, performing a first plurality of erase loops on a plurality of memory blocks, wherein performing an initial one of the first plurality of erase loops comprises applying respective bulk voltages to each of the plurality of memory blocks and detecting whether each of the plurality of memory blocks has been successfully erased, and wherein performing subsequent erase loops among the plurality of erase loops comprises applying respective stepped-up bulk voltages to each of the plurality of memory blocks that has not been detected to be successfully erased while interrupting the supply of bulk voltages to any of the plurality of memory blocks that has been detected to be successfully erased; and in the second erase period, performing a second plurality of erase loops on the plurality of memory blocks, wherein performing each of the second plurality of erase loops comprises applying a respective fixed-level bulk voltage to each one of the plurality of memory blocks, wherein each respective fixed-level bulk voltage is defined by a last stepped-up bulk voltage applied to the corresponding one of the plurality of memory blocks during the first erase period.