Patent ID: 9021502
Filing Date: 2015-04-28
Classification: G06F

Abstract:
1. A computer-implemented method, comprising: executing a thread on a given processor; reading, by the thread, a value from a shared memory location; subsequent to said reading, beginning execution of a sequence of program instructions by the thread, wherein the sequence of program instructions comprises: wherein termination of the execution of the sequence is dependent on receipt of an indication that a value has been written to the shared memory location by another thread and is not dependent on the value written to the shared memory location; during execution by the thread of the sequence of program instructions, writing, by a second thread executing on a second processor, a value in the shared memory location; subsequent to said writing, receiving, by the given processor, an indication from the second processor that a value has been written to the shared memory location; and in response to said receiving, terminating the execution of the sequence of instructions and performing a subsequent action dependent on the value of the shared memory location having changed.