Patent ID: 8952509
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A stacked multi-chip semiconductor device comprising: a lead frame unit having a die paddle, a first lead and a second lead, which are separated from each other, wherein the die paddle consists of a main paddle and a die pin located on two different height horizontal planes; a first chip flipped and attached on a top surface of the main paddle and a second chip attached on a bottom surface of the main paddle; a metal clip electrically connecting an electrode at the back of the first chip to the first lead positioned proximity to the main paddle and coplanar with the die pin of the die paddle; the second lead, positioned proximity to the main paddle, comprising a connecting part coplanar with the main paddle and electrically connecting to an electrode on the front of the first chip and a lead pin coplanar with the die pin of the die paddle; wherein a top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of the lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.