Patent ID: 6501400
Filing Date: 2002-12-31
Classification: H03M

Abstract:
An apparatus for compensating amplifier gain error in a pipelined analog to digital converter having a main pipeline including a plurality of analog to digital converter stages, each stage having a amplifier having a corresponding gain, the apparatus comprising:a plurality of error correcting stages including a predetermined number of adjacent analog to digital converter stages in the main pipeline, the plurality of error correcting stages providing a residue output signal; a shadow pipeline having at least one shadow stage, the shadow pipeline receiving a gain error signal from at least one of the plurality of error correcting stages, the shadow pipeline configured and arranged to provide a compensation signal; the compensation signal being equal to the gain error signal received from the at least one of the plurality of error correcting stages multiplied by a gain factor, wherein the gain factor is substantially equal to the product of the gains corresponding to each of the subsequent error correcting stages, multiplied by the sum of the gains of each gain corresponding to each of the stages in the plurality of error correcting stages; and a combination module configured and arranged to combine the compensation signal and the residue output signal to provide an error compensated signal.