Patent ID: 6486645
Filing Date: 2002-11-26
Classification: H02M

Abstract:
A voltage regulation circuit comprising:a feedback comparator having a feedback comparator first input terminal configured to receive a regulated output voltage, a feedback comparator second input terminal configured to receive a first reference voltage and a feedback comparator output terminal, said feedback comparator generating a comparison signal at said feedback comparator output terminal in response to said regulated output voltage; a latch module comprising a latch first input terminal in communication with said feedback comparator output terminal, a latch second input terminal configured to receive an off-time signal having a variable asserted duration, and a latch output terminal, said latch module generating a charge signal at said latch output terminal in response to said comparison signal and said off-time signal; a switch having a control terminal in communication with said latch output terminal, a first terminal configured to receive a current level signal, and a second terminal configured to receive a second reference voltage; a current limit module comprising a current limit first input terminal in communication with said latch output terminal, a current limit second input terminal configured to receive said current-level signal, a current limit third input terminal configured to receive said regulated output voltage, and a current limit output terminal, said current limit module generating a peak detect signal at said current limit output terminal in response to said charge signal, said regulated output voltage, and said current-level signal; and a pulse module comprising a pulse first input terminal in communication with said current limit output terminal, a pulse second input terminal configured to receive a supply voltage, a pulse third input terminal configured to receive said regulated output voltage, and a pulse output terminal in communication with said latch second input terminal, said pulse module generating said off-time signal at said pulse output terminal in response to said peak detect signal, said input voltage and said regulated output voltage.