Patent ID: 7279757
Filing Date: 2007-10-09
Classification: H01L

Abstract:
1. A method of using a double-sided extended drain field effect transistor that includes a substrate and a gate terminal overlying the substrate over a channel region in the substrate, wherein the substrate further comprises a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region of the first carrier type; and a source region of the first carrier type that is laterally separated from the channel region by a second RESURF region of the first carrier type, wherein the drain region, the source region, the first RESURF region and the second RESURF region are all disposed within a single well region of a second carrier type that is opposite the first carrier type, the well region being disposed within the substrate, the method comprising the following: an act of applying a first reverse bias to a first interface between the source region of the first carrier type and a body region of a second carrier type; and an act of applying a second reverse bias to a second interface between the drain region of the first carrier type and the body region of the second carrier type.