Patent ID: 7465977
Filing Date: 2008-12-16
Classification: B81C,H01L,Y10S

Abstract:
1. A method for producing a packaged integrated circuit, the method comprising: building an integrated circuit having at least one micro-structure suspended above a micro-cavity and having a heating element on said at least one micro-structure capable of heating itself and its immediate surroundings; depositing a layer of protective material on said micro-structure such that at least a top surface of said micro-structure and an opening of said micro-cavity is covered, wherein said protective material is in a solid state at room temperature and can protect said micro-structure during silicon wafer dicing procedures and subsequent packaging, and wherein said micro-structure, said micro-cavity, and said protective material provide an unobstructed volume above and below said micro-structure after said micro-structure is subjected to a heat source; packaging said integrated circuit; and passing an electric current through said heating element to generate said heat source to provide said unobstructed volume above and below said micro-structure.