Patent ID: 7886198
Filing Date: 2011-02-08
Classification: G06F

Abstract:
1. An integrated circuit comprising: a processing circuit that executes instructions; a first memory operatively coupled to the processing circuit, the memory having an overlay region where addresses of bytes in the overlay region are different than when the bytes are stored outside the first memory; a trace circuit operatively coupled to the processing circuit, the trace circuit gathers trace data comprising addresses of executed instructions, and wherein the trace circuit is configured to send the trace data to a debug-trace program; and a memory location operatively coupled to the trace circuit, wherein the trace circuit is configured to send a value in the memory location to the debug-trace program, while preempting capture of other data, only when the value is newly written; wherein each time the bytes are placed in the overlay region, the processing circuit writes an index value to the memory location, the index value indicative of an identity of the bytes in the overlay region.