Patent ID: 7564085
Filing Date: 2009-07-21
Classification: B82Y,G11C,H01L,Y10S

Abstract:
1. A memory device comprising: an insulating substrate; a source electrode formed on the insulating substrate; a drain electrode formed on the insulating substrate and spaced apart from the source electrode; a nanowire capacitor formed on the source electrode, the nanowire capacitor including a first nanowire grown vertically from the source electrode, a dielectric layer formed on the outer surface of the first nanowire, and a floating electrode formed on the outer surface of the dielectric layer; a second nanowire grown vertically from the drain electrode, the second nanowire bending towards the nanowire capacitor while a voltage is applied to the drain electrode; and a gate electrode formed on the insulating substrate and spaced apart from the drain electrode, the drain electrode being arranged between the source electrode and the gate electrode.