Patent ID: 9128701
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A microprocessor having an instruction set architecture that defines an instruction comprising an immediate field, wherein the immediate field has a first portion specifying a first value and a second portion specifying a second value, wherein the instruction instructs the microprocessor to perform an operation which uses a constant value as one of its source operands, wherein the constant value is the first value rotated/shifted by a number of bits based on the second value, the microprocessor comprising: an instruction translator, that translates the instruction into at least an immediate ALU microinstruction, wherein the immediate ALU microinstruction is encoded in a distinct manner from the manner in which instructions defined by the instruction set architecture are encoded; and an execution pipeline, that executes microinstructions generated by the instruction translator to generate a result defined by the instruction set architecture; wherein the instruction translator, rather than the execution pipeline, generates the constant value from the first and second values for provision to the execution pipeline as a source operand to the immediate ALU microinstruction for execution by the execution pipeline.