Patent ID: 7386823
Filing Date: 2008-06-10
Classification: G06F

Abstract:
1. A method for processing a description of a circuit provided by a user to produce a schematic diagram of the circuit, wherein the circuit comprises a plurality of electronic devices interconnected by conductors, wherein the schematic diagram comprises symbols representing the electronic devices and comprises representations of the conductors, and wherein in the schematic diagram resides in a plane having vertical and horizontal directions, the method comprising the steps of: a. establishing a set of rules, each rule corresponding to a separate characteristic pattern of interconnected devices, wherein each rule specifies at least one constraint on placement within the schematic diagram of a set of symbols representing any set of the devices interconnected to form the characteristic pattern corresponding to that rule, b. for each rule established at step a, processing the circuit description to identify each set of devices of the electronic circuit exhibiting the rule's corresponding characteristic pattern; c. for each set of devices identified at step b as exhibiting a characteristic pattern corresponding to any rule established at step a, identifying the set of devices as members of a soft group including only that set of devices and establishing at least one constraint on placement within the schematic diagram of symbols representing members of that soft group in accordance with the at least one constraint specified by the rule, wherein more than one soft group is identified, wherein more than one constraint is established, and wherein at least one device of the circuit is identified as being a member of more than one soft group; d. selecting positions and orientations within the schematic diagram for symbols representing the devices comprising the circuit in a manner consistent with at least one of the constraints established at step c; and e. generating the schematic diagram including symbols representing electronic devices residing at the positions established at step d and representations of the conductors interconnecting the electronic devices.