Patent ID: 8397096
Filing Date: 2013-03-12
Classification: H03K,H03L

Abstract:
1. Physical media attachment (“PMA”) circuitry on an integrated circuit comprising: a first plurality of transceiver channels (“low-speed channels”), each of which is adapted for transceiving a serial data signal having a first relatively low serial data bit rate; a second plurality of transceiver channels (“high-speed channels”), each of which is adapted for controllable selection between (1) transceiving a serial data signal that can have a serial data bit rate greater than the low-speed channels are adapted to transceive, and (2) performing a phase-locked loop (“PLL”) operation on a received reference clock signal to produce an output clock signal; PLL circuitry for producing a further output clock signal from a further received reference clock signal; circuitry for selectively applying the output clock signal produced by one the high-speed channels to another of the high-speed channels; and circuitry connected to at least a subset of the low-speed channels for selectively applying the further output clock signal to one channel of the subset of low-speed channels.