Patent ID: 8270478
Filing Date: 2012-09-18
Classification: G06F,H04N

Abstract:
1. A logic circuit for digitally processing images wherein the logic circuit is arranged to calculate a sum of absolute differences between a plurality of pixels and the same plurality of members respectively selected successively from all members of a sequence of pixels, the logic circuit comprising: a first subtractor comprising a first input configured to receive a first of the plurality of pixels, and a second input configured to receive a first member from the sequence of pixels, and configured to output a first difference between the first pixel and the first member; a second subtractor comprising a first input configured to receive a second pixel of the plurality of pixels, a second input configured to receive a second member of the sequence of pixels, and an output configured to output a second difference between the second pixel and the second member; a first adder/subtractor comprising a first input zeroed, a second input configured to receive the first difference, a control input configured to receive a top bit of the first difference, and an output configured to output a first absolute difference between the first pixel and first member; a second adder/subtractor comprising a first input configured to receive the first absolute difference, a second input configured to receive the second difference, a control input configured to receive a top bit of the second difference, and an output configured to output a sum of the first absolute difference and the absolute difference of the second pixel and second member; first and second intermediate registers, each comprising inputs electrically connected to the outputs of the first and second subtractors, respectively, and outputs electrically connected to second inputs of the first and second adder/subtractors, respectively; and wherein the logic circuit is configured such that once initial latency is passed, the logic circuit produces a result on every clock cycle.