Patent ID: 6519690
Filing Date: 2003-02-11
Classification: G06F

Abstract:
An address decoder mechanism for mapping addresses in a system providing a memory address space and an I/O address space and both memory and non-memory addressable resources having resource controllers each having a maximum addressable location, the mechanism comprising:a programmable address mapper for passing an address to one of the resource controllers; and a programmable address register coupled to the programmable address mapper for controlling the programmable address mapper, such that when the address is within a range specified by the programmable address register, the programmable address mapper passes the address to the resource controller specified by the programmable address register, wherein the programmable address register is selectively programmable to force the programmable address mapper to map to both memory and non-memory resource controllers, and wherein the range specified by the programmable address register is truncated at the maximum addressable location of the resource controller specified by the programmable address register.