Patent ID: 6275424
Filing Date: 2001-08-14
Classification: G11C,H01L

Abstract:
An apparatus for biasing a drain node of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory, said drain node being coupled to each respective control gate node of a plurality of core cells disposed within a well, the apparatus comprising:a voltage generator coupled to said well; anda microcontroller coupled to said voltage generator for controlling said voltage generator to ramp up a magnitude of a well voltage applied at said well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage;and wherein said microcontroller controls said voltage generator to couple said drain node of said high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after said start ramping time, said well voltage reaching an intermediate voltage at said predetermined time period after said start ramping time;and wherein said microcontroller controls said voltage generator to uncouple said drain node of said high voltage MOSFET from said ground node at said predetermined time period after said start ramping time;and wherein said drain node of said high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of said end voltage minus a magnitude of said intermediate voltage, at said end ramping time when said well voltage is at said end voltage.