Patent ID: 8218363
Filing Date: 2012-07-10
Classification: G11C

Abstract:
1. A multilevel flash memory device, comprising: a memory cell array comprising a plurality of multilevel (MLC) memory cells respectively connected between a plurality of words lines and a plurality of bits lines, wherein each MLC memory cell is capable of being programmed to an erase state or one of a plurality of standard program states; a status detector configured to detect whether or not a target memory cell is programmed to the erase state, and provide a detection result when the target memory cell is determined to be programmed to the erase state; and a control logic unit configured to receive the detection result and during a programming operation to control a program voltage applied to a neighboring memory cell adjacent to the target memory cell and to be programmed to one of a plurality of standard program states, such that the neighboring memory cell is programmed to a corresponding one of a plurality of correction program states different from the one of the plurality of standard program states.