Patent ID: 6815290
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of fabricating a stacked gate flash memory cell, comprising:providing a substrate; forming two parallel shallow trench isolation (STI) regions along a first direction in the substrate; forming a long trench in the substrate between the STI regions, wherein the long trench is parallel to the STI regions; forming a bottom insulating layer in the long trench; performing a threshold voltage (Vt) implant process on the sidewalls of the long trench; forming a tunnel oxide layer on each sidewall of the long trench; forming a floating gate on each sidewall of the long trench, covering the tunnel oxide layer thereon; forming a conformal inter-gate dielectric layer overlying the floating gates and the bottom insulating layer within the long trench; blanketly depositing a polysilicon layer covering the substrate and the inter-gate dielectric layer within the long trench; blanketly depositing a metal layer on the polysilicon layer; blanketly depositing a protecting layer on the metal layer; forming a plurality of parallel wordlines along a second direction, dividing the long trench into a plurality of first areas covered by the wordlines and a plurality of second areas not covered by the wordlines over the long trench; forming a plurality of source/drain regions in the sidewalls of the long trench oppositely adjacent to the second areas; and forming a second insulating layer within the second areas, wherein a plurality of cell trenches are formed under the first areas and a plurality of isolation trenches are formed under the second areas.