Patent ID: 6208179
Filing Date: 2001-03-27
Classification: H03K,H03L

Abstract:
A dividing circuit comprising a plurality (N) of transistor stages connected in a ring, each stage comprising:a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node;a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node,wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide a clock node for the stage,wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than a duty cycle of said clock signal;and further comprising a switching circuit that selectively connects one of at least two inputs to an output, wherein the output nodes of at least two alternate transistor stages of the dividing circuit are connected respectively to said at least two inputs, wherein one of said output nodes is selectively connected to the input node of a subsequent stage so that the integer N is programmable.