Patent ID: 9059272
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A transistor, comprising: a III-V substrate; a patterned gate stack disposed on the III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate comprising source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions; raised source/drain regions on the source/drain regions, the raised source/drain regions comprised of III-V semiconductor material; and metal contacts on the raised source/drain regions; wherein the raised source/drain regions on the source/drain regions comprise a first raised source/drain region comprising a first III-V material and a first dopant and a second raised source/drain region comprising a second III-V material and a second dopant, the second raised source/drain region being disposed on the first raised source drain region; wherein the metal contacts are selectively disposed on only upper surfaces of the first raised source/drain region having the first dopant and selectively disposed on only upper surfaces of the second raised source/drain region having the second dopant.