Patent ID: 7893440
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A thin film transistor (TFT) array arrangement, comprising: a substrate; an active layer of a TFT and a first electrode of a capacitor arranged on the substrate in a pattern, the active layer and the first electrode being comprised of a same material and being separated from each other by a distance, the active layer including a source region, a drain region and a channel region; a first insulation layer separately arranged on the active layer and on the first electrode; a gate electrode and a second electrode arranged on the first insulation layer, the gate electrode and the second electrode being arranged on a same layer and being comprised of a same material, the gate electrode being arranged to correspond to the channel region of the active layer and the second electrode being arranged to correspond to the first electrode; a second insulation layer arranged on the substrate, the first insulation layer, the gate electrode, and the second electrode, the second insulation layer being perforated by contact holes exposing the source region and the drain region of the active layer; a source electrode and a drain electrode arranged within the contact holes and providing electrical connection to the source region and the drain region respectively of the active layer; a pixel electrode arranged on the second insulation layer and being connected to one of the source electrode and the drain electrode; and a third electrode being arranged on the second insulation layer at a location that corresponds to the second electrode, the third electrode being comprised of same materials as that of the combination of the source electrode, the drain electrode and the pixel electrode.