Patent ID: 6424680
Filing Date: 2002-07-23
Classification: H03M,H04H,H04L

Abstract:
A method of interleaving a digital signal in which samples are delayed by an integral number times a unit delay, in accordance with a cyclically repeated delay pattern, comprising the following steps:cyclically activating parallel-arranged select lines of a memory at a cycle rate which is equal to the unit delay; writing to the memory, during one activation of a select line, a relevant bit of each sample to be delayed in an integral number of sample groups, a sample group being associated with one delay pattern cycle; and reading from the memory, during the one activation of the select line, a number of bits equal to the number of bits which is written, the bits being read in accordance with the delay pattern; and in which, data is both written to and read from the memory during consecutive select line activations of the cyclic activations of the select lines for each repeated delay pattern.