Patent ID: 8629025
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming, over a substrate, a stacked gate dielectric that comprises, from bottom to top, a first dielectric layer, a second dielectric layer and a third dielectric layer; forming a conductive layer on the stacked gate dielectric; patterning the conductive layer to form a gate conductor; removing an exposed portion of the third dielectric layer with the gate conductor as a mask; removing an exposed portion of the second dielectric layer; forming S/D extension regions in the substrate with the gate conductor as a mask; forming a first spacer on a sidewall of the gate conductor and removing a portion of the first dielectric layer exposed by the first spacer; forming S/D regions in the substrate at both sides of the first spacer; and forming a metal silicide layer at least on the S/D regions.