Patent ID: 7173610
Filing Date: 2007-02-06
Classification: G09G,G11C

Abstract:
1. A decoder system, comprising: an address input for receiving an address signal representing any of a plurality of address values (D); a plurality of intermediate nodes; a decoder responsive to the address signal and arranged to stimulate, for each address value, a respective combination of the intermediate nodes; and a plurality of outputs, each responsive to a respective group of the intermediate nodes such that the stimulation applied to that output is dependent upon the stimulation applied by the decoder to each of the intermediate nodes in the respective group; wherein the decoder is arranged to perform a plural-stage process in determining which of the intermediate nodes to stimulate in response to each address value, said plural-stage process comprising at least a first stage in which results are determined and a second stage for which the results of the first stage are provided as inputs, wherein the plural-stage process comprises the determination of a word of a predetermined constant weight code.