Patent ID: 8247286
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first isolation region and a second isolation region within a substrate to define an active region between the first and second isolation region; forming a gate insulating layer on the active region; forming a gate pattern on the gate insulating layer, the gate pattern overlapping the active region, wherein the gate pattern includes a length in a first direction and a width in a second direction perpendicular to the first direction, and wherein the gate pattern includes a first edge gate portion, a second edge gate portion opposite to the first edge gate portion in the first direction, a third edge gate portion, a fourth edge gate portion opposite to the third edge gate portion in the second direction, and a center gate portion being surrounded by the first through the fourth edge gate portions; and simultaneously forming a source region, a drain region, and a first impurity region, wherein all of the source region, the drain region, and the first impurity region are doped with impurities of a first conductivity type, wherein the source region and the drain region are formed in the active region, and wherein the first impurity region is formed selectively within the center gate portion of the gate pattern.