Patent ID: 7089402
Filing Date: 2006-08-08
Classification: G06F

Abstract:
1. A method for controlling an order of instructions executed by a computing architecture comprised of a plurality of computing functional units, for completing a plurality of jobs in a job queue, said method comprising: a selecting step of selecting at least one job from the job queue for each of the computing functional units, each job containing a plurality of sequential instructions; a first generating step of generating a first sequence of long instruction words based on the sequential instructions contained in the selected jobs, each long instruction word having a plurality of instruction fields, each instruction field corresponding to one of the computing functional units and containing a sequential instruction; a first execution step of sequentially executing the first sequence of long instruction words by the computing architecture, each computing functional unit executing the sequential instruction in the corresponding instruction field of each long instruction word; a detecting step of detecting when each of the computing functional units are in a free state, detecting when the first sequence of long instruction words is completed, or, in the case that the computing architecture includes a sub-processor, detecting when the first sequence of long instruction words is being executed; a halting step of halting, in the case that the computing architecture does not include a sub-processor, execution of the first sequence of long instruction words when at least one of the computing functional units is detected in a free state; a second generating step of generating, when at least one of the computing functional units is detected in a free state, a second sequence of long instruction words which includes instructions from a selected new job from the job queue for each computing functional unit detected to be in a free state; a copying step of copying the second sequence of long instruction words into the first sequence of long instruction words; and a resuming step of resuming, in the case that the computing architecture does not include a sub-processor, execution of the first sequence of long instruction words by the plurality of computing functional units.