Patent ID: 6279077
Filing Date: 2001-08-21
Classification: G06F

Abstract:
A microprocessor, comprising:data processing circuitry for executing instructions performed upon digital signals, and for communicating the results of such executing upon an internal bus synchronous with a internal clock; anda plurality of write buffers coupled to the internal bus, for communicating digital data corresponding to said results to a single external bus, said plurality of write buffers provided in a number and in respective sizes fixed upon manufacture, each of said write buffers comprising:a data portion for storing at least one digital data word received from the internal bus;a tag portion for storing a portion of a memory address associated with a digital data word stored in the data portion; anda control portion, coupled to the external bus and to the internal bus, for generating a status code corresponding to the capacity of the data portion that is available to receive digital data;wherein a first one of the plurality of write buffers has a first size; andwherein a second one of the plurality of write buffers has a second size different from the first size.