Patent ID: 6646490
Filing Date: 2003-11-11
Classification: H03K

Abstract:
A bipolar breakdown enhancement circuit for use with a tri-state output stage, comprising:a supply voltage, a ground terminal which is at a ground potential, an NPN emitter follower-connected bipolar output transistor, the collector-emitter circuit of said output transistor connected between said supply voltage and an output terminal, said transistor arranged to produce an output voltage at said output terminal which is referenced to said ground potential, a comparison circuit which produces an output equal to the lesser of said output voltage and said ground potential, wherein said comparison circuit comprises first and second FETs, said first FET connected between said ground terminal and a common node and arranged to conduct a first current to said common node in response to said output voltage and said second FET connected between said output terminal and said common node and arranged to conduct a second current to said common node in response to said ground potential, said common node being the output of said comparison circuit, and a switch arranged to connect the base of said output transistor to the output of said comparison circuit in response to a tri-state control signal which is asserted when said output transistor is to be placed in a high-impedance state.