Patent ID: 7653788
Filing Date: 2010-01-26
Classification: G06F,Y02D

Abstract:
1. A method of making cache memories of a plurality of processors coherent with a shared memory, comprising: determining at a first of the processors that an external memory operation is needed for data within a respective one of the cache memories to be maintained coherent with data within remaining ones of the cache memories and transmitting a cache coherency request to a traffic-monitoring device; transmitting memory operation information from the traffic monitoring device to the plurality of processors, the memory operation information comprising an address of the data to be maintained coherent; at each of the plurality of processors: determining whether the data to be maintained coherent is present in its cache memory; determining whether a memory operation is needed to make the data coherent; transmitting to the traffic-monitoring device a message indicating a state of the data in its cache memory and indicating the memory operation that the processor is going to perform; performing the memory operation indicated to the traffic-monitoring device; and ordering performance of two or more transmitted memory operations from two or more of the processors and relating to the data at the traffic monitoring device according to an order based on the indicated states of the data identified by the two or more processors to maintain coherency between the cache memories.