Patent ID: 6061281
Filing Date: 2000-05-09
Classification: G11C

Abstract:
A redundancy method comprising the steps of:sharing a redundancy switch between a plurality of redundancy memory objects having memory recovery lines;said redundancy switch divisionally and independently connecting to the memory recovery lines in the redundancy memory objects to replace defects generated in the redundancy memory objects with information of the memory recovery lines, and providing for replacement of a defect in each of the plurality of redundancy memory objects or replacement of a plurality of defects in one redundancy memory object,said redundancy switch comprising a plurality of redundancy connections, wherein each redundancy connection comprises a defective memory object selection which includes a least one AND gate providing for memory object selection, and a memory address selection which includes at least one AND gate providing for memory address selection; andreplacing defects generated in the redundancy memory objects with information of the recovery lines which are connected by the redundancy switch, thereby recovering the defects.