Patent ID: 8018254
Filing Date: 2011-09-13
Classification: H03H,H03K

Abstract:
1. A sampling circuit comprising: a memory element having an input terminal and an output terminal, a storage node configured to pass an input voltage to the input terminal for storage at the memory element, a first MOS transistor configured to provide a path from a first voltage to the storage node when the first MOS transistor is “ON,” a third MOS transistor configured to provide a path from a third voltage to a bulk of the first MOS transistor when the third MOS transistor is “ON” and to float the bulk of the first MOS transistor when the third MOS transistor is “OFF,” wherein an effective parasitic capacitance of the first MOS transistor is reduced when the third MOS transistor is “OFF,” a sixth MOS transistor coupled to the output terminal, and configured to provide a path from a sixth voltage to the output terminal when the sixth MOS transistor is “ON,” and a seventh MOS transistor configured to provide a path from a seventh voltage to a bulk of the sixth MOS transistor when the seventh MOS transistor is “ON,” and to float the bulk of the sixth MOS transistor when the seventh MOS transistor is “OFF,” wherein an effective parasitic capacitance of the sixth MOS transistor is reduced when the seventh MOS transistor is “OFF;” wherein: