Patent ID: 6525382
Filing Date: 2003-02-25
Classification: H01L,Y10S

Abstract:
A semiconductor memory device including in each cell two inverters in which input and output terminals are connected crossing over each other by first node wiring and second node wiring, each of the two inverters consisting of a first conductive drive transistor and a second conductive load transistor which are connected in series between a first power supply voltage line to supply a first power voltage and a second power supply voltage line to supply a second power supply voltage, where for each of the two inverters a gate line is connected to and serves as a gate electrode for the first conductive drive transistor and the second conductive load transistor, whereineach pattern of the first node wiring and second node wiring has the same shape in each cell and is disposed to have a different direction from each other between neighboring cells, with a space between the first node wiring and the second node wiring being smaller than a width of either node wiring, a first active region in which a channel of the drive transistor is formed and a second active region in which a channel of the load transistor is formed are disposed in each cell in such a manner that current directions of each channel of the drive transistor and the load transistor are parallel to each other in each cell, each drive transistor of the two inverters is arranged in series, word transistors are arranged so that word lines separately placed in each word transistor are orthogonal to the first active region at both ends of the cell, respectively.