Patent ID: 6430091
Filing Date: 2002-08-06
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in rows and columns for storing externally applied data; a voltage generating circuit for receiving and boosting an externally applied first power supply potential to generate a second power supply potential to be used for data transmission with respect to said memory cell array; a first internal node being activated by said second power supply potential; a first control circuit for issuing first and second control signals for driving said first internal node in accordance with an externally applied input signal, said first control circuit activating said first control signal for a predetermined time in accordance with change in said input signal, and activating said second control signal upon elapsing of said predetermined time after the change in said input signal; and a first drive circuit for receiving said first and second power supply potentials and driving the potential on said first internal node to said second power supply potential in accordance with said first and second control signals, wherein said first drive circuit includes: a first switch circuit to be turned on to couple said first power supply potential to said first internal node in accordance with said first control signal, and a second switch circuit to be turned on to couple said second power supply potential to said first internal node in accordance with said second control signal.