Patent ID: 7528025
Filing Date: 2009-05-05
Classification: H01L,Y10S

Abstract:
1. A method of forming a nonplanar device CMOS integrated circuit comprising: forming an n type and a p type semiconductor bodies, each semiconductor body comprising a top surface and sidewalls; forming a first sacrificial gate electrode over the top surface and sidewalls of the n type semiconductor body, wherein a portion of the n type semiconductor body area under the first sacrificial gate electrode defines an n type semiconductor channel region; forming a second sacrificial gate electrode over the top surface and sidewalls of the p type semiconductor body, wherein a portion of the p type semiconductor body area under the first sacrificial gate electrode defines a p type semiconductor channel region; forming a dielectric layer over said first and said second sacrificial gate electrodes; planarizing said dielectric layer; revealing the top surface of said first and second sacrificial gate electrodes; removing said first sacrificial gate electrode to form a first opening over said n type channel region and removing said second sacrificial gate electrode to form a second opening over said p type semiconductor channel region; forming a gate dielectric layer in said first opening on said n type semiconductor channel region and in said second opening on said p type semiconductor channel region; forming a metal gate electrode material onto said gate dielectric layer in said first opening and onto said gate dielectric layer in second opening and above said planarized dielectric layer; and polishing said gate electrode material from above said dielectric to form a first gate electrode over said gate dielectric layer in said opening and a second gate electrode on said gate dielectric layer in said second opening.