Patent ID: 6184081
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of fabricating a capacitor structure for a memory device, on a semiconductor substrate, comprising the steps of:providing insulator encapsulated gate structures, on a gate insulator layer, on said semiconductor substrate, with source/drain regions, in an area of said semiconductor substrate, not covered by said insulator encapsulated gate structures;forming self-aligned contact openings, in a first silicon oxide layer, exposing said source/drain regions, located between said silicon encapsulated gate structures;forming conductive plug structures, in said self-aligned contact openings;depositing a composite insulator layer, comprised an underlying first silicon nitride layer, and an overlying second silicon oxide layer;forming capacitor node openings in said composite insulator layer, with a first capacitor node opening, exposing the top surface of a first conductive plug structure, and with a second capacitor node opening exposing a portion of the top surface of said first silicon oxide layer;forming a first storage node structure, in said first capacitor node opening, overlying and contacting the top surface of said first conductive plug structure, and forming a second storage node structure, in said second capacitor node opening;forming a capacitor dielectric layer, on said first storage node structure, and on said second storage node structure;depositing a polysilicon layer, completely filling the space between said first storage node structure, and said second storage node structure;depositing a third silicon oxide layer;using a first opening, in a photoresist shape, as an etch mask, to create a first contact hole, in a region not covered by said storage node structures, with said first contact hole formed in said third silicon oxide layer, in said polysilicon layer, in said capacitor dielectric layer, and in said first silicon nitride layer, exposing the top of a second conductive plug structure, with said first contact hole featuring an undercut region, in said polysilicon layer;using a second opening, in said photoresist shape as an etch mask, to create a second contact hole, in the space between said first storage node structure, and said second storage node structure, with said second contact hole formed in said third silicon oxide layer, and in a top portion of said polysilicon layer, exposing the bottom portion of said polysilicon layer, and in said capacitor dielectric layer, exposing a portion of the top surface of said first storage node structure;using a third opening, in said photoresist shape, as an etch mask, to create a third contact hole, in a region not covered by said storage node structures, with said third contact hole formed in said third silicon oxide layer, in said polysilicon layer, in said capacitor dielectric layer, in said first silicon nitride layer, and in said first silicon oxide layer, exposing a portion of said semiconductor substrate, with said third contact hole featuring an undercut region, in said polysilicon layer;using a fourth opening, in said photoresist shape, to define a capacitor upper plate structure, with said capacitor upper plate structure formed in a region not covered by said storage node structures, and formed by the etching of: said third silicon oxide layer; said polysilicon layer; said capacitor dielectric layer; said first silicon nitride layer, and said first silicon oxide layer;forming silicon nitride spacers on the sides of said first contact hole, on the sides of said second contact hole, and on the sides of said third contact hole, with a thicker silicon nitride spacer formed in the undercut regions of said polysilicon layer, in said first contact hole, and in said third contact hole; andforming a bit line contact structure, in said first contact hole, forming a capacitor contact structure, in said second contact hole, and forming a substrate contact structure, in said third contact hole.