Patent ID: 8686778
Filing Date: 2014-04-01
Classification: G06F,H03K

Abstract:
1. A configurable clock circuit operable to receive a clock signal, comprising: a control and enable circuit having a clock input, a feedback input, and a control output, the clock input configured to receive the clock signal; and a clock distribution circuit coupled to the clock input configured to receive the clock signal and having an enable input and a clock output, the enable input coupled to the control output of the control and enable circuit; wherein when the feedback input is configured in a clock mode, the feedback input is coupled to VSS, and the control and enable circuit generates a control signal on the control output to enable the clock signal to propagate through the clock distribution circuit to the clock output, and wherein, when the feedback input is configured in the clock mode, enabling the clock signal to propagate through the clock distribution circuit to the clock output comprises using the feedback input to enable at least one full duty-cycle waveform for the clock input to propagate through the clock distribution circuit to the clock output; wherein when the feedback input is configured in a pulse mode, the feedback input is coupled to the clock output, and the control and enable circuit generates a control signal on the control output to control a length of a pulse responsive to the clock signal at the clock output of the clock distribution circuit; and wherein the feedback input is coupled to an input of an interruptible tri-state inverter and to a transistor, wherein the interruptible tri-state inverter has a second input coupled to an inverted version of the clock input, a third input coupled to a non-inverted version of the clock input, and an output coupled to the transistor.