Patent ID: 7973580
Filing Date: 2011-07-05
Classification: G06F,H02J,H02M,H03K,H03L

Abstract:
1. A semiconductor device comprising a digital PWM circuit outputting: a first pulse signal switching from a low level to a high level at a timing of being synchronized with a clock signal and switching from the high level to the low level at a timing set by a shorter time resolution than that of a period of the clock signal; and a second pulse signal switching from a low level to a high level at a timing set by a shorter time resolution than that of a period of the clock signal and switching from the high level to the low level at a timing set by a shorter time resolution than that of a period of the clock signal, the digital PWM circuit including: a delay circuit having a plurality of stages of delay elements connected serially; a first selection circuit selecting one from outputs of the respective delay elements and outputting a signal setting a falling timing of the first pulse signal; a first delay element delaying an output signal of the selection circuit and outputting a signal setting a rising timing of the second pulse signal; and a second delay element delaying an output signal synchronized with the clock signal and outputting a signal setting a falling timing of the second pulse signal.