Patent ID: 7208796
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A split gate flash memory, comprising: a substrate; at least one active layer disposed on the substrate and protruded from the surface of the substrate; a plurality of device isolation layers disposed on the sides of the active layer, wherein the surface of the device isolation layers is lower than the surface of the active layer; and at least one memory cell disposed on the substrate, the memory cell comprising: a stacked gate structure having at least a floating gate, wherein the floating gate is formed across the active layer; a select gate disposed on a top of the stacked gate structure and on a sidewall of the stacked gate structure in a extent direction of the active layer and across the active layer; a source region disposed in the active layer on a second side of the stacked gate structure and extended to an area underneath the floating gate, wherein the second side and the first side are disposed in reciprocal locations; and a drain region disposed in the active layer on one side of the select gate.