Patent ID: 6706575
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method for fabricating a non-volatile memory, comprising:providing a substrate having a strip stacked structure thereon, wherein the strip stacked structure comprises a gate conductive layer and a dielectric layer under the gate conductive layer; forming a buried drain line as a buried bit line in the substrate beside the strip stacked structure; forming an insulating layer on the buried drain line; forming sequentially a silicon layer and a cap layer over the substrate covering the strip stacked structure and the insulating layer; patterning the cap layer, the silicon layer, and the strip stacked structure in a direction perpendicular to the buried drain line to form a stacked gate structure, wherein the patterned silicon layer serves as a word line; forming a liner layer on exposed surfaces of the silicon layer, the gate structures and the substrate; removing the cap layer; and forming a metal salicide (self-aligned silicide) layer on the silicon layer.