Patent ID: 6166670
Filing Date: 2000-12-26
Classification: G05F,H03M

Abstract:
A self calibrating current mirror comprising:a current mirror input for receiving an input current;a current mirror output for providing an output current;a comparator having an input, an output and a switching threshold voltage, the comparator input being connected to said current mirror input;a first, second, third and fourth transfer gate each having a control input, an output and a switchable input which passes current to the output upon activation of the control input, the outputs of the first and second transfer gates being connected to the current mirror input, and the outputs of the third and fourth transfer gates being connected to the current mirror output;a first and second charge pump each having a first input for controlling the pump polarity which is connected to the comparator output, a second input for receiving a clock signal, and a pump output for producing incremental voltage steps responsive to the first and second input;a digital logic circuit to selectively operate the first and second charge pumps and the control inputs of the first, second, third and fourth transfer gates;a first current mirror MOS transistor having a drain, a gate and a source, the gate being connected to the pump output of said first charge pump and the drain being connected to the switchable inputs of the first and third transfer gates; anda second current mirror MOS transistor having a drain, a gate and a source, the gate being connected to the pump output of said second charge pump and the drain being connected to the switchable inputs of the second and fourth transfer gates.