Patent ID: 7776694
Filing Date: 2010-08-17
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device including vertical channel transistors, the method comprising: providing a substrate including a plurality of pillars each of which has a lower portion, wherein the lower portion corresponds to a channel region of a vertical channel transistor; forming a gate insulation layer over a surface of the substrate including the plurality of pillars, thereby forming a first resultant structure; forming a barrier metal layer over a portion of the gate insulation layer corresponding to the lower portion of each pillar; forming a metal gate electrode over the barrier metal layer to surround the lower portion of each pillar, thereby forming a second resultant structure; forming a first inter-layer insulation layer over the second resultant structure; forming a first trench exposing the substrate by selectively etching the first inter-layer insulation layer; forming a second inter-layer insulation layer to fill the first trench; and forming a word line coupled to the gate electrodes formed over the plurality of pillars.