Patent ID: 7551037
Filing Date: 2009-06-23
Classification: H03L

Abstract:
1. A PLL circuit, comprising: a voltage-controlled oscillator for altering an oscillation frequency according to an oscillation control voltage signal; a prescaler for dividing the oscillation frequency provided by the voltage-controlled oscillator to output a frequency-divided signal; a reference signal oscillator for producing an oscillating reference signal; a phase comparator for detecting a phase difference between the frequency-divided signal and the reference signal to output a phase difference signal based on the detection; a charge pump for outputting current in accordance with the phase difference signal from the phase comparator; a loop filter for smoothing the output current of the charge pump for output as the oscillation control voltage signal to the voltage-controlled oscillator, wherein the charge pump controls a voltage of the loop filter while the voltage-controlled oscillator is not oscillating; a voltage value memory circuit for recording a control voltage value of the loop filter; a comparator for comparing the control voltage value to an output voltage value from the loop filter while the voltage-controlled oscillator is not oscillating, to output a comparison signal, wherein the charge pump controls the voltage of the loop filter according to the comparison signal from the comparator while the voltage-controlled oscillator is not oscillating; and a multiplexer for selectively outputting, to the charge pump, either the comparison signal from the comparator or the phase difference signal from the phase comparator.