Patent ID: 6303461
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method for fabricating a shallow trench isolation (STI) structure on a semiconductor substrate, on which a pad oxide layer and a mask layer are sequentially formed, the method comprising:forming a material layer on the mask layer;patterning the material layer, the mask layer, and the pad oxide layer to form a trench in the semiconductor substrate, wherein an active region enclosed by the trench is also defined;forming an insulating layer over the substrate so that the trench is also filled;stripping the insulating layer at a portion above the active region, wherein the insulating layer leaves a smaller thickness on the material layer;performing a planarization process to strip a portion of the insulating layer and the material layer so as to expose the mask layer, in which a remaining portion of the insulating layer forms the STI structure to fill the trench, whereinthe material layer has a faster stripping rate than the stripping rate of the insulating layer.