Patent ID: 6854002
Filing Date: 2005-02-08
Classification: G11B

Abstract:
1. A circuit comprising: a plurality of n multipliers, each multiplier having a first input and a second input, n being an integer greater than one; a coefficient memory having at least n outputs, each output of the coefficient memory being coupled to a respective one of the multipliers at the first multiplier input; a select circuit comprising a plurality of n multiplexers and having at least n output nodes, each of the n output nodes being coupled to a respective one of the multipliers at the second multiplier input, wherein each multiplexer includes first and second inputs and wherein each of the multiplexers are labeled as a first multiplexer, a second multiplexer and so on to an nth multiplexer; and a plurality of input nodes coupled to the select circuit such that at a first time each of the input nodes is coupled to a respective one of the output nodes of the select circuit and such that at a second time at least some of the input nodes are coupled to a different one of the output nodes of the select circuit, wherein the input nodes are labeled as a first node, a second node and so on to an nth node, and wherein each input node is coupled to a corresponding first input of a respective one of the multiplexers such that the input nodes are coupled to the first input of the multiplexer in an forward order wherein the first input node is coupled to the first input of the first multiplexer, the second input node is coupled to the first input of the second multiplexer and the nth input node is coupled to the first input of the nth multiplexer and wherein each input node is also coupled to a corresponding second input of a respective one of the multiplexers such that the input modes are coupled to the second input of the multiplexers in a backward order wherein the first input node is coupled to the second input of the nth multiplexer, the second input node is coupled to the second input of the (n−1)th multiplexer and the nth input node is coupled to the second input of the first multiplexer.