Patent ID: 8918325
Filing Date: 2014-12-23
Classification: G10L,H04S

Abstract:
1. A signal processing device comprising: a prediction error calculating unit that receives a first signal and a second signal, and calculates an error signal between the first signal and a prediction signal of the first signal, which is predicted from the second signal; a first gain adjusting unit that controls a gain of the error signal; a first adder that adds the first signal and the second signal in phase, and outputs a result of said addition as a first addition signal; a second adder that adds the first signal and the second signal in opposite phase, and outputs a result of said addition as a second addition signal; a second gain adjusting unit that controls a gain of the second addition signal; a third adder that adds the error signal from the first gain adjusting unit and the second addition signal from the second gain adjusting unit in phase, and outputs a result of said addition as a third addition signal; a fourth adder that adds the first addition signal and the third addition signal in phase; and a fifth adder that adds the first addition signal and the third addition signal in opposite phase.