Patent ID: 7419879
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A method of fabricating a transistor comprising: forming a gate dielectric layer including a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion; forming a first gate overlapping the main portion of the gate dielectric layer; forming a second gate layer covering the sidewall portion of the gate dielectric layer exposed by the first gate, and covering the first gate; etching the second gate layer, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate; selectively etching an exposed sidewall portion of the gate dielectric layer using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates, wherein the pattern of the gate dielectric layer has a width between sidewalls of the pattern of the gate dielectric layer that is the same as that of a bottom surface of the second gates; and forming a source/drain in a first portion of the semiconductor substrate exposed by the second gates.