Patent ID: 7545697
Filing Date: 2009-06-09
Classification: G11C

Abstract:
1. A semiconductor storage device wherein an address signal for performing refresh while temporally splitting refresh becomes active N times, wherein N is an integer of at least 2, in a single refresh time period to thereby refresh a memory array successively, comprising: a DLL circuit that aligns phase of an internal clock signal with that of an external clock signal externally supplied; and a DLL control circuit that exercises control so as to halt operation of said DLL circuit in an interval in which the address signal becomes active one or more times and not more than N−1 times, said interval being included in an interval in which the address signal becomes active N times, wherein said DLL control circuit includes: a counter circuit that counts the address signal; and a decoder circuit that decodes the value of a count recorded by said counter circuit; said DLL control circuit halting operation of said DLL circuit while said decoder circuit is decoding a prescribed range of count values.