Patent ID: 9177631
Filing Date: 2015-11-03
Classification: G11C

Abstract:
1. A memory circuit comprising: at least one first memory cell of a first memory array for storing a first datum, the at least one first memory cell being coupled with a first word line and a first bit line, the first bit line having a first bit line portion and a second bit line portion; a first bit line bar disposed substantially parallel with the first bit line, the first bit line bar having a first bit line bar portion and a second bit line bar portion; a sense amplifier comprising a read/write circuit, the read/write circuit being configured to couple the second bit line portion to a global bit line; a first switch coupled between the first bit line bar portion and the second bit line bar portion, the first switch being configured to (1) electrically isolate the sense amplifier from the first bit line bar portion based on a first received signal during a period that the sense amplifier is operated to sense a first voltage difference between the second bit line portion and the second bit line bar portion, and to (2) electrically isolate the first bit line bar portion from the sense amplifier during a period that the read/write circuit is operated to couple the second bit line portion and the global bit line; and a second switch coupled between the first bit line portion and the second bit line portion, the second switch being configured to (1) electrically isolate the sense amplifier from the first bit line portion based on a second received signal during the period that the sense amplifier is operated to sense the first voltage difference between the second bit line portion and the second bit line bar portion, and to (2) electrically couple the first bit line portion and the sense amplifier during the period the read/write circuit is operated to couple the second bit line portion and the global bit line, wherein