Patent ID: 6418518
Filing Date: 2002-07-09
Classification: G06F

Abstract:
In a switch that provides for flow of packet data between input and output ports of the switch in a network environment, and wherein the switch includes a SDRAM that operate based upon a first clock signal, a buffer manager that manages the flow of packet data into the SDRAM, the buffer manager operating based upon a second clock signal that is asynchronous to the first clock signal, and a memory control unit that receives packet data and address information from the buffer manager and uses the address information to save the packet data into the SDRAM, the memory control unit comprising:a buffer manager interface that receives commands, address information and packet data from the buffer manager; an address translation circuit coupled with the buffer manager interface and that translates the address information into SDRAM address space, the address translation circuit operating based upon the second clock signal, the buffer manager interface synchronizing the address information between the first and second clock signals; a data synchronization circuit coupled to the buffer manager interface and that synchronizes the packet data to the second clock signal while the address translation circuit translates the address information into the SDRAM address space; and an SDRAM interface coupled with the address translation circuit and the data synchronization circuit and that writes the data to an SDRAM based upon the translated address information, the SDRAM interface operating based upon the second clock signal.