Patent ID: 8436482
Filing Date: 2013-05-07
Classification: H01L

Abstract:
1. A semiconductor device comprising: an insulating layer on a substrate and having a plurality of cavities; wiring lines on the insulating layer; a plurality of branched wiring lines that branch from the wiring lines so as to respectively overlap with the plurality of cavities; a conductive portion on the wiring lines; an external terminal on the conductive portion; and a sealing resin layer that seals the wiring lines and the conductive portion, wherein the wiring lines include a first wiring line portion that extends in a first direction, a second wiring line portion that extends from a first end of the first wiring line portion in a second direction orthogonal to the first direction, and a seat portion at a second end of the first wiring line portion, wherein the plurality of cavities are configured by first graduation portions arrayed at equal intervals in the first direction, and second graduation portions arrayed at equal intervals in the second direction, and wherein the first graduation portions and the second graduation portions are formed at the first wiring line portion and the second wiring line portion, respectively.