Patent ID: 6080674
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method for forming a plurality of self-aligned via holes applied to a semiconductor device comprising steps of:(a) providing a substrate forming thereon a conducting layer forming thereon a sacrificial layer;(b) partially removing said sacrificial layer and said conducting layer while retaining a plurality of sacrificial via pillars, wherein each of said sacrificial via pillars has a remaining conducting layer and a remaining sacrificial layer;(c) partially removing said remaining sacrificial layer on said plurality of sacrificial via pillars;(d) forming a first insulating layer between said plurality of said sacrificial via pillars, and then planarizing said first insulating layer to expose top surfaces of said plurality of sacrificial via pillars; and(e) removing said plurality of said sacrificial via pillars while retaining said first insulating layer to form said plurality of self-aligned via holes.