Patent ID: 7504297
Filing Date: 2009-03-17
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device comprising the steps of: (a) forming an isolation region over the main surface of a semiconductor substrate including silicon as a main component; (b) depositing a first conductive film including said silicon as a main component over said main surface of said semiconductor substrate and forming a gate electrode of a MISFET in a first region over said main surface of said semiconductor substrate by patterning said first conductive film; (c) forming a first semiconductor region in said semiconductor substrate at both sides of said gate electrode by selectively introducing a first impurity into said main surface of said semiconductor substrate, and forming a second semiconductor region in a second region of said semiconductor substrate; (d) forming a second insulation film over said semiconductor substrate and removing selectively said second insulation film over said gate electrode, said first semiconductor region, and said second semiconductor region; (e) depositing a first metallic film including a first metal as a main component over said semiconductor substrate in the presence of said second insulation film, forming a first metallic compound layer including said silicon and said first metal over said gate electrode, said first semiconductor region, and said second semiconductor region by applying a first heat treatment to said semiconductor substrate, and removing the remaining first metallic film; (f) after the step (e), forming a third insulation film having a selective etching rate different from said isolation region over said semiconductor substrate, and forming a first aperture reaching said semiconductor substrate by selectively removing said third insulation film at a different position from over said second semiconductor region in said second region over said main surface of said semiconductor substrate; (g) depositing a second metallic film including a second metal as a main component over said semiconductor substrate in the presence of said third insulation film, forming a second metallic compound layer including said silicon and second metal over said semiconductor substrate at the bottom part of said first aperture, and removing the remaining second metallic film; (h) after the step of (g), forming a first insulation film having a selective etching rate different from said third insulation film over said semiconductor substrate; (i) forming a second aperture reaching said first metallic compound layer over said first semiconductor region, a third aperture reaching said first metallic compound layer over said gate electrode, a fourth aperture reaching said first metallic compound layer over said second semiconductor region, and a fifth aperture reaching said second metallic compound layer, by selectively etching said first insulation film and said third insulation film; and (j) burying said second aperture, said third aperture, said fourth aperture, and said fifth aperture with a second conductive film to form a plug, wherein said first semiconductor region forms a source region and a drain region of said MISFET, and wherein said first metallic compound layer and said second metallic compound layer in said second region forms a first electrode and a second electrode of a Schottky-barrier diode, respectively.