Patent ID: 6310492
Filing Date: 2001-10-30
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising a P-channel field effect transistor (FET) which has a drain electrode, a source electrode, a gate electrode formed of a P-type semiconductor material, and a back gate electrode and which is configured such that in a normal operation mode (a) a certain voltage is supplied from a power supply to said source electrode and (b) another voltage representative of an input signal is supplied to said gate electrode,said semiconductor integrated circuit further comprising:control means, responsive to a control signal which is asserted when reducing power consumption in said semiconductor integrated circuit, for controlling at least one of the voltage of said gate electrode and the voltage of said back gate electrode so as to prevent said gate electrode voltage from exceeding said back gate electrode voltage, in order to protect said P-channel FET which is being in a state of not functioning as a transistor from degradation.