Patent ID: 7095478
Filing Date: 2006-08-22
Classification: G02F

Abstract:
1. An electric device comprising: a plurality of gate lines and a plurality of data lines arranged in a matrix form over a substrate; a plurality of thin film transistors over said substrate, each thin film transistor arranged at a pixel area surrounded by adjacent two of said gate lines and adjacent two of said data lines; an interlayer insulating film comprising silicon over said thin film transistors; a flattering film over said interlayer insulating film; a plurality of pixel electrodes over said flattering film, each connecting to a drain electrode of the corresponding thin film transistor; an opposed substrate comprising an opposed electrode on a surface thereof; and at least one spacer interposed between said substrate and said opposed substrate, wherein a pixel pitch of said pixel area is 40 μm or less, and wherein a thickness of said spacer in a direction vertical to said substrate and said opposed substrate is 4 μm or less.