Patent ID: 7043710
Filing Date: 2006-05-09
Classification: G06F

Abstract:
1. An early evaluation, self-timed phased logic gate, comprising: a block compute function; a master arrival detection function that is configured to output a feedback output; a trigger compute function; a trigger arrival detection function; a plurality of input conductors for conducting a plurarity of inputs; and at least one block output; wherein said block compute function is configured to update said at least one block output upon the arrival of only a subset of said plurality of inputs as indicated by said trigger detection function when said trigger compute function evaluates to true, and said block compute function is configured to update said at least one block output upon the arrival of all of said plurality of inputs as indicated by said master arrival detection function and said trigger arrival detection function, when said trigger compute function evaluates to false; and wherein said master arrival detection function is configured to update said feedback output upon the arrival of all of said plurality of input.