Patent ID: 7492655
Filing Date: 2009-02-17
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of data lines; and a plurality of sense amplifier circuits connected to the plurality of data lines, wherein each of the plurality of sense amplifier circuits is provided with a first MISFET pair of a first conductivity type in which a gate of one MISFET is directly connected to a drain of the other MISFET, a second MISFET pair of the first conductivity type in which a gate of one MISFET is directly connected to a drain of the other MISFET, and a third MISFET pair of a second conductivity type in which a gate of one MISFET is directly connected to a drain of the other MISFET, and wherein each of gate lengths of the first MISFET pair is longer than each of gate lengths of the second MISFET pair.