Patent ID: 7737985
Filing Date: 2010-06-15
Classification: G06F,G06T

Abstract:
1. Apparatus comprising: device memory and hardware entities connected to the device memory, at least some of the hardware entities to perform actions involving access to and use of the device memory, and the hardware entities including 3D graphics circuitry to process, for ready display, 3D images from primitive objects; a sub-image cell value cache separate from the device memory to hold data, including buffered sub-image cell values, the cache being connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory; and a cache write operator to write the buffered sub-image cell values to the device memory in accordance with a priority scheme, the priority scheme preserving in the cache border sub-image cell values bordering at least one primitive object.