Patent ID: 7380149
Filing Date: 2008-05-27
Classification: G06F,Y02D

Abstract:
1. An information processing device, comprising: a first area including a central processing unit and a peripheral circuit module; a second area having an information holding circuit for holding a value of a register contained in said peripheral circuit module; a first power switch that controls supply of a current to said first area and a second power switch that controls supply of a current to said second area; and a boot address register that holds an address in which an instruction to be executed by said central processing unit first is stored when the information processing device shifts from a second mode to a first mode, wherein when said information processing device operates in said first mode, said first and second power switches are controlled so that an operating current can be supplied to said first area and said second area; when said information processing device operates in said second mode, said first power switch is controlled so that the supply of the current to said first area can be shut off and the supply of the current to said second area is continued; the address output from said boot address register to the central processing unit when said information processing device shifts from said second mode to said first mode; a third area containing a standby control circuit, wherein when said information processing device operates in said first mode, said second power switch is controlled so that the current can be supplied to said second area; when said information processing device operates in a third mode, said first power switch is controlled so that the supply of the current to said first area can be shut off, said second power switch is controlled so that the supply of the current to said second area can be shut off, and the supply of the current to said third area is continued; the operation of said first power switch and second power switch is controlled through said standby control circuit; wherein said standby control circuit comprises a selector that selects an address output from said boot address register and an address in which an instruction to perform reset processing is stored; and said selector selects the address output from said boot address register when said information processing device shifts from said second mode to said first mode and the address in which the instruction to perform said reset processing is stored when said information processing device shifts from said third mode to said first mode.