Patent ID: 6785860
Filing Date: 2004-08-31
Classification: G06F

Abstract:
A memory comprising:a plurality of data storage words, each data storage word comprising a plurality of data storage cells, at least one of said data storage cells storing data specifying a data value having 3 or more states; a plurality of data lines, one such data line corresponding to each data storage cell, said corresponding data storage cell being connected to that data line, each data storage cell comprising a gate for connecting that storage cell to said corresponding data line, each data storage cell assuming one of said states in response to a signal on said corresponding data line and a write signal, said state being determined by said signal on said corresponding data line; a plurality of data writing circuits, one such data writing circuit corresponding to each data line and being connected to that data line, at least one of said data writing circuits comprising a circuit for receiving a digital value having a plurality of bits and for generating a data programming signal on said corresponding data line in response to said write signal; and an error encryption circuit for receiving a data word to be stored in said memory and generating therefrom an encrypted data storage word, dividing said encrypted data storage word into a plurality of sub-data storage words, at least one of said sub-data storage words having a plurality of bits; and coupling each sub-data storage word to a corresponding one of said data writing circuits in response to a write signal being received by said memory, wherein the least significant two bits of said sub-data storage words are encrypted via a first error-encryption algorithm and the most significant bits of said sub-data storage words are either not encrypted or encrypted via a second error encryption algorithm, said second error encryption algorithm having a Hamming Distance that is less than the Hamming Distance of said first error-encryption algorithm.