Patent ID: 6567335
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A memory system comprising:a system bus which includes a tag bus and a data bus; a memory controller operably coupled to the system bus, with said memory controller being configured to issue memory program instructions, with the memory program instructions comprising a memory program address, a memory program address command, memory program data and a memory program data command and with the memory controller being further configured to transfer the memory program address over the data bus together with the memory program address command over the tag bus and configured to transfer the memory program data over the data bus together with the memory program data command over the tag bus; a plurality of memory devices separate from one another and from the memory controller, with each of the memory devices comprising an array of memory cells; a memory operation manager operably coupled to the system bus and to the array of memory cells, said memory operation manager being configured to carry out memory program operations on the array, said memory operation manager including a command decoder configured to detect the memory program data command on the tag bus and to cause the memory program data on the data bus to be transferred to a data register block for subsequent programming of the array of memory cells and configured to detect the memory program address command on the tag bus and to cause the memory program address on the data bus to be transferred to an address register block for subsequent programming of the memory program data in the data register block at the memory program address in the address register block.