Patent ID: 8099561
Filing Date: 2012-01-17
Classification: G06F

Abstract:
1. An interconnection network for storing and retrieving information, comprising: a plurality of interconnected switches; at least one external memory port for connecting to at least one memory bank, said at least one memory bank providing a shared space of memory addresses; and a plurality of external processor ports for connecting to a plurality of processors, said processors being programmed to submit memory access initiatives through said external processor ports for accessing said shared space of memory addresses through said interconnection network, wherein said interconnection network is configured to operate in a time regime wherein time is divided into clock cycles, to receive, upon every clock cycle, a plurality of said memory access initiatives, and to provide, in response to said memory access initiatives, respective memory access paths through said switches for accessing said at least one external memory port, wherein an address included in a given memory access initiative defines a route, within said interconnection network, of the memory access path that is provided in response to the given memory access initiative, and wherein each of said switches is configured, upon encountering a conflict between memory access paths requested by ones of said processors, to allow providing at least one of the conflicting memory access paths, and to return reply signals toward at least one of said ones of said processors, thereby indicating to said at least one of said processors whether it needs to resubmit a rejected memory access initiative in a later clock cycle.