Patent ID: 7919990
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A semiconductor device comprising a CMOS inverter cascade circuit having a plurality of CMOS inverters cascade-connected in at least two stages, wherein the CMOS inverter cascade circuit includes a first CMOS inverter and a second CMOS inverter which are formed as a two-stage CMOS inverter made up of six MOS transistors arranged on a substrate in a two-row by three-column array, and wherein: each of two MOS transistors in a respective one of the 1st column and the 3rd column is a p-channel MOS transistor; and two MOS transistors in the 2nd column is an n-channel MOS transistor, each of the p-channel MOS transistors and the n-channel MOS transistors having a structure where a drain, a source and a gate thereof are arranged in a direction perpendicular to the substrate while allowing the gate to surround an island-shaped semiconductor layer, and wherein: the first inverter CMOS inverter includes the second CMOS inverter has and wherein: the first power supply line provided for the first CMOS inverter and the first power supply line provided for the second CMOS inverter are connected to each other on the source diffusion layers of the two n-channel MOS transistors in the 2nd column; and the first-CMOS-inverter output terminal is connected to the second-CMOS-inverter input terminal.