Patent ID: 6392641
Filing Date: 2002-05-21
Classification: G09G,H03L,H04N

Abstract:
A phase locked loop circuit for a digital display apparatus for outputting a clock signal whose frequency is a multiple of a frequency of a horizontal sync signal to be supplied by an integer number, and feeding back a comparison signal whose frequency is said clock signal frequency-divided by said integer number to thereby generate said clock signal phase-synchronous with said horizontal sync signal, said phase locked loop circuit comprising:a lock/unlock detection circuit for comparing phases of said horizontal sync signal and said comparison signal to detect a locked state and an unlocked state of said phase locked loop circuit; and an internal sync signal generation circuit for outputting said comparison signal inside as an internal sync signal when said locked state is detected by said lock/unlock detection circuit and outputting said horizontal sync signal as said internal sync signal when said unlocked state is detected.