Patent ID: 6191016
Filing Date: 2001-02-20
Classification: H01L,Y10S

Abstract:
A method of fabricating transistors, comprising:forming a gate oxide layer of less than 10 .ANG. on a semiconductor substrate;forming a first layer over the gate oxide layer;forming a second layer over the first layer,forming a third layer over the second layer, the third layer including nitrogen such that, when formed directly on the first layer causes stresses between the first layer and the third layer, but the second layer securing to relieve stresses between the first layer and the third layer, the second layer and the third layer forming a mask over the first layer, the mask being substantially free of carbon and comprising at least two masking portions with an opening between the masking portions;etching through the first layer in area between the masking portions, at least until the gate oxide layer is exposed without substantial breakthrough through the gate oxide layer, with the masking portions at least partially preventing etching of portions of the first layer below the masking portions; andforming electrical contacts on the substrate in an area where the first layer is etched through;etching the mask with an etchant that selectively removes materials of the masking portions including the nitrogen containing third layer, selectively over the first layer; andforming a silicide where the gate oxide layer is exposed.