Patent ID: 7536513
Filing Date: 2009-05-19
Classification: G06F

Abstract:
1. A method of data processing in a data processing system including a first processor core supported by a first cache hierarchy, a second processor core supported by a second cache hierarchy and an interconnect fabric, said method comprising: in response to a master in the first cache hierarchy receiving a memory access request indicating a target address, the master accessing a first cache directory of an upper level cache of the first cache hierarchy; in response to said target address being associated in said first cache directory with an entry having a valid address tag and a first invalid coherency state, said master issuing a request specifying said target address to the second cache hierarchy on the interconnect fabric without regard to a coherency state associated with said target address in a second cache directory of a lower level cache of said first cache hierarchy; and in response to said target address having a second invalid coherency state with respect to said first cache directory, said master issuing a request specifying said target address to the second cache hierarchy on said interconnect fabric after determining a coherency state associated with said target address in said second cache directory of said lower level cache of said first cache hierarchy.