Patent ID: 9112499
Filing Date: 2015-08-18
Classification: H03K

Abstract:
1. A field programmable gate array (FPGA) comprising: a first configurable logic block formed in a substrate; a first memory formed in at least one memory layer overlying the substrate and connected with the first configurable logic block, the first memory comprising non-volatile resistive memory elements, the first memory providing signals to drive the first configurable logic block; and an interface connected with the first memory and operative to provide write data to the first memory; a second configurable logic block formed in the substrate and a second memory formed in the at least one memory layer overlying the substrate, the second memory connected with the second configurable logic block, the second memory providing signals to drive the second configurable logic block, and wherein the interface further connects with the second memory and is operative to provide write data to the second memory; and a third memory formed overlying the substrate and comprising non-volatile resistive memory elements, the third memory providing data accessible to both the first and second configurable logic blocks.