Patent ID: 9208740
Filing Date: 2015-12-08
Classification: G09G

Abstract:
1. A gate driver; comprising: a logic circuit, for generating a plurality of buffer input signals and a modulation signal; a plurality of buffers, each receiving one of the plurality of buffer input signals and generating a gate driving signal according to the one of the plurality of buffer input signals, wherein the buffers are commonly coupled between a first voltage source node and a second voltage source; and a switch module, coupled to all of the buffers via the first voltage source node and coupled to a first voltage source, for determining whether the first voltage source is electrically connected to the first voltage source node according to the modulation signal; wherein during a modulation period, the modulation signal causes the switch module to be cut-off and causes the first voltage source node to be connected to only the plurality of buffers and the plurality of buffer input signals are configured to short all or some of a plurality of output terminals, so as to modulate at least one of the gate driving signals; wherein during the modulation period, the plurality of buffer input signals are at a first input level, and when each of the plurality of buffers receives the buffer input signal at the first input level, the output terminal of the buffer is connected to the first voltage source node and cut-off from the second voltage source.