Patent ID: 6133114
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method for fabricating a shallow trench isolation (STI) structure on a semiconductor substrate, having a pad oxide layer and a masking layer sequentially formed over the substrate, and having a trench formed in the substrate through the pad oxide layer and the masking layer, the method comprising:forming a first insulating layer over the substrate, in which a portion of the first insulating layer within the trench is lower than the masking layer;forming a second insulating layer over the substrate, in which the second insulating layer is at least about as hard as the masking layer or harder;performing a chemical mechanical polishing (CMP) process to polish the first insulating layer and the second insulating layer, using the masking layer as a polishing stop, so that the masking layer is exposed, wherein a portion of the second insulating layer remains in the trench; andremoving the masking layer and the pad oxide layer to form the STI structure on the substrate.