Patent ID: 7045892
Filing Date: 2006-05-16
Classification: H01L

Abstract:
1. A semiconductor package comprising: a first substrate having a first surface, a second surface, external connection terminals formed on the first surface, and a plurality of lands formed on the second surface; a first semiconductor chip mounted on the second surface of the first substrate; a second substrate attached by its first surface to the first semiconductor chip and including a plurality of outer lands in an outer perimeter of a second surface, a window penetrating between the first and the second surfaces, and inner lands around the window of the second surface; at least one second semiconductor chip mounted on the second surface of the second substrate; and at least one third substrate attached by its first surface to the second semiconductor chip and including a plurality of outer lands in the outer perimeter of a second surface, a window penetrating between the first and the second surfaces, and inner lands around the window of the second surface, wherein the outer lands of the second substrate and the third substrate are respectively connected to the outer lands of the first substrate by an electrical connection medium; wherein the inner lands of the second substrate are connected to pads of the first semiconductor chip via the window of the second substrate by the electrical connection medium; and wherein the inner lands of the third substrate are connected to pads of the second semiconductor chip via the window of the third substrate by the electrical connection medium.