Patent ID: 6356994
Filing Date: 2002-03-12
Classification: G06F

Abstract:
An apparatus including a plurality of addressing modes for providing indirect access to very long instruction words (VLIWs) allowing both sequential code and parallel operations in the form of VLIWs to be encoded efficiently, wherein the sequential code comprising a sequence of short instruction words (SIWs) including indirect VLIW SIWs is loaded as part of a single instruction stream, the apparatus comprising:a short instruction memory fetch logic for fetching a short instruction word from a short instruction memory (SIM); the short instruction memory storing the short instruction word, said short instruction word including a field defining an addressing mode associated with the short instruction word, wherein said addressing mode is one of the plurality of addressing modes for accessing the VLIW instruction; an instruction decoder for decoding the short instruction word; a VLIW instruction memory (VIM) for storing VLIW instructions; a VLIW memory address unit (VIM AGU) for determining the addressing mode associated with the short instruction word; VIM address registers; and a VIM address generation mechanism for selecting a VLIW in said VIM by generating a VIM address according to the address mode associated with said short instruction word; wherein said addressing mode associated with the short instruction word is one of said plurality of addressing modes: a direct VIM addressing mode, a base plus offset addressing mode, an indirect/indexed addressing mode, a circular indexed addressing mode, or a processing element (PE) relative addressing mode.