Patent ID: 8482326
Filing Date: 2013-07-09
Classification: H03L

Abstract:
1. A semiconductor device, comprising: an external terminal which receives an external clock; a first phase determination circuit configured to receive the external clock and an internal clock to generate a first determination signal based on a phase between a first edge of the external clock and a first edge of the internal clock, the first edge is one of a rising edge and a falling edge; a second phase determination circuit configured to receive the external clock and the internal clock to generate a second determination signal based on a phase between a second edge of the external clock and a second edge of the internal clock, the second edge is the other of the rising edge and the falling edge; a control circuit configured to receive the first and second determination signals and output a pitch enlargement signal based on the first and second determination signals; and a counter circuit configured to output a count value produced, by counting up or counting down based on the second determination signal, by a first pitch when the pitch enlargement signal indicates a first state, and by a second pitch larger than the first pitch when the pitch enlargement signal indicates a second state.