Patent ID: 6820192
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A central processing unit (CPU) for easily testing and debugging an application program, including a universal register file for temporarily storing data necessary for operation of data and address, a program counter storing addresses at which programs are stored, a special register file having a status register indicating a status of the CPU and a break register, an internal bus connecting the universal register file and the special register file, and a control unit connected to the internal bus, for outputting various control signals necessary for internal and external components of the CPU, the CPU comprising:a data communications unit for performing data communications with a host computer; a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state; a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program; a comparator for comparing a value stored in a break register with break data; a reset data storage unit storing reset data; and a reset data comparator for comparing the data input via the data communications unit with the reset data stored in the reset data storage unit, and instructing the control unit to initialize the CPU if the data input via the data communications is same as the reset data, wherein the CPU is converted into he debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.