Patent ID: 7360134
Filing Date: 2008-04-15
Classification: G01R,G11C

Abstract:
1. A method for using a built-in-self-test (BIST) engine to test multiple on-chip memory structures, comprising: running the BIST engine, which is located on-chip, during an initialization process for the chip; wherein running the BIST engine involves testing multiple on-chip memory structures which reside at different locations on the chip; wherein testing the multiple on-chip memory structures involves performing at-speed data-parallel testing operations on the multiple on-chip memory structures; and wherein testing the multiple on-chip memory structures involves communicating with the multiple on-chip memory structures through pre-existing data paths which are used for other purposes during normal operation of the chip, but which are used for communications between the BIST engine and the multiple on-chip memory structures during the testing process.