Patent ID: 8928180
Filing Date: 2015-01-06
Classification: G05F

Abstract:
1. A power supply circuit, comprising: a voltage output device, configured to generate an output voltage; a parasitic resistance, connected between an output end of the voltage output device and an external load, wherein two ends of the parasitic resistance generate a voltage drop; and a compensation circuit, connected to the output end of the voltage output device and configured to generate a compensation voltage, wherein the compensation voltage is loaded onto the voltage output device, so as to offset the voltage drop generated by the parasitic resistance, so that a voltage obtained at an input end of the load is roughly equal to the output voltage generated by the voltage output device; wherein the compensation circuit comprises a first resistance and a compensation current generation circuit, the first resistance is connected between the output end of the voltage output device and the compensation current generation circuit, and the compensation current generation circuit is configured to generate a compensation current having a first proportional relation with a current flowing through the parasitic resistance, the compensation current generates the compensation voltage after flowing through the first resistance, and according to a second proportional relation between resistance values of the parasitic resistance and the first resistance, the compensation voltage is substantially equal to the voltage drop generated at the two ends of the parasitic resistance; wherein the voltage output device comprises: a reference voltage providing device, an operational amplifier OP and a first Positive-channel Metal Oxide Semiconductor (PMOS) transistor, the operational amplifier OP comprises a positive input end, a negative input end and an output end, a source electrode of the first PMOS transistor is connected to a power supply voltage, a grid electrode of the first PMOS transistor is connected to the output end of the operational amplifier OP, and a drain electrode of the first PMOS transistor provides the output voltage of the voltage output device; and wherein the negative input end of the operational amplifier OP is connected to the reference voltage providing device so as to receive a reference voltage, the first resistance is connected in series between the positive input end of the operational amplifier OP and the drain electrode of the first PMOS transistor, the positive input end of the operational amplifier OP is further connected to a common ground end through a second resistance, and the output end of the operational amplifier OP is connected to the grid electrode of the first PMOS transistor, the source electrode of the first PMOS transistor receives an input power supply voltage, and the drain electrode of the first PMOS transistor is connected to the external load through the parasitic resistance, so as to provide an output current for the load.