Patent ID: 8201067
Filing Date: 2012-06-12
Classification: G06F

Abstract:
1. A method for processor error checking, the method comprising: receiving an instruction data, the instruction data including a decoded instruction; generating a pre-processing parity data based on the instruction data; maintaining the pre-processing parity data; processing the instruction data, the processing comprising passing the instruction data through a multi-stage instruction processing pipeline to produce processed instruction data; generating a post-processing parity data based on the processed instruction data; checking, by the computer, for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data; and transmitting an error signal that indicates that the error related to processing the instruction data occurred, the transmitting responsive to the post-processing parity data not matching the pre-processing parity data; wherein the checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.