Patent ID: 7089344
Filing Date: 2006-08-08
Classification: G06F,Y02D

Abstract:
1. A data transfer system comprising: a plurality of peripheral interfaces; a first memory; a programmable direct memory access module coupling the first memory to each of the plurality of peripheral interfaces, wherein the programmable direct memory access module configures selectively programmable direct memory access data channels between the first memory and, respectively, each one of the plurality of peripheral interfaces; a first processor coupled to the programmable direct memory access module and associated with the first memory through a first shared bus, which couples both the first processor and the first memory to the programmable direct memory access module; a second memory coupled to the programmable direct memory access module, wherein the programmable direct memory access module configures the selectively programmable direct memory access data channels between the second memory mid, respectively, each one of the plurality of peripheral interfaces; and a second processor coupled to the programmable direct memory access module and associated with the second memory through a second shared bus, independent of the first shared bus, which couples both the second processor and the second memory to the programmable memory access module.