Patent ID: 8383518
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. A method for forming contact holes, the contact holes applied in a transistor array substrate, the transistor array substrate comprising a substrate, a first metal pattern layer, a first insulation layer, a second metal pattern layer and a second insulation layer, wherein the first metal pattern layer is disposed on the substrate, the first metal pattern layer includes a plurality of first contact pads, the first insulation layer covers the substrate and the first metal pattern layer, the second metal pattern layer is disposed on the first insulation layer, the second metal pattern layer includes a plurality of second contact pads, and the second insulation layer covers the second metal pattern layer and the first insulation layer, the method for forming contact holes comprising the following steps: forming a photoresist pattern layer on the second insulation layer, wherein the photoresist pattern layer comprises a plurality of recesses and a plurality of first openings, the first openings expose the second insulation layer partially, and the second insulation layer is not exposed by the recesses, the first openings are located over the first contact pads respectively, and the recesses are located over the second contact pads respectively; using the photoresist pattern layer as a mask, and remove partially the second insulation layer and the first insulation layer inside the first openings, in order to expose the first contact pads; reducing the thickness of the photoresist pattern layer, so that the recesses form a plurality of second openings, wherein the second openings expose the second insulation layer partially; and using the photoresist pattern layer having a reduced thickness as a mask, and removing a part of the second insulation layer inside the second openings, so as to expose the second contact pads.