Patent ID: 6268642
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A wafer level package, comprising:a silicon chip having at least one integrated circuit device;an insulation layer covering the integrated circuit device;a plurality of bonding pads above the insulation layer and distributed along the edges of the silicon chip, wherein each bonding pad is electrically connected to a terminal of the integrated circuit device;a passivation layer covering the insulation layer and a portion of the bonding pad, wherein the passivation layer has a plurality of openings each exposing a portion of the bonding pad;a metallic layer covering the interior side walls of the opening, the exposed bonding pad and the passivation layer surrounding the opening, and a portion of the metallic layer even extends from the opening to the edge of the silicon chip;a packaging layer over the passivation layer outside the area with metallic layer; anda plurality of metallic bumps over the metallic layer above each opening wherein the metallic bumps are located next to the edge of the silicon chip so that both a top surface and an outer surface of the metallic bump can act as a contacting area for external connections.