Patent ID: 8604527
Filing Date: 2013-12-10
Classification: H01L

Abstract:
1. A die supporting a plurality of PMOS and NMOS field effect transistors (FETs) formed in a doped well in a bulk semiconductive substrate, the FETs respectively each having a source, a drain, and a gate stack having a gate length, comprising: a PMOS screening region extending under at least one PMOS FET formed above the doped well, the PMOS screening region being doped with n-type dopants to have a dopant concentration between 1×10 a NMOS screening region extending under at least one NMOS FET formed above the doped well, the NMOS screening region being doped with p-type dopants to have a dopant concentration between 1×10 a substantially undoped semiconductive layer formed to extend across at least one PMOS FET and NMOS FET, the substantially undoped semiconductive layer being disposed above the PMOS screening region and the NMOS screening region, the substantially undoped semiconductive layer abutting the PMOS screening region and the NMOS screening region; a PMOS threshold voltage setting region formed in the substantially undoped semiconductive layer, the PMOS threshold voltage setting region being doped with n-type dopants having a dopant concentration between 5×10 an NMOS threshold voltage setting region formed in the substantially undoped semiconductive layer, the NMOS threshold voltage setting region being doped with p-type dopants having a dopant concentration between 5×10 wherein the gate stack has a length Lg and is positioned above the doped well to control conduction between the drain and the source of the respective PMOS and NMOS FETs, and at least a portion of the undoped semiconductive layer is maintained as a substantially undoped channel region of the respective PMOS and NMOS FETs, and wherein the substantially undoped channel region is laterally positioned between the source and the drain and vertically positioned between the gate stack and the threshold voltage setting region of the respective PMOS and NMOS FETs, and the threshold voltage setting region is positioned between the substantially undoped channel region and the screening region of the respective PMOS and NMOS FETs.