Patent ID: 7836277
Filing Date: 2010-11-16
Classification: G06F

Abstract:
1. A processor configured to switch back and forth between two operational modes, the processor comprising: a processor core which is operated during a second operational mode and which sequentially performs a first set of instructions during the second operational mode; an instruction cache that generates a pseudo-program counter corresponding to the first set of instructions, pre-traces the first set of instructions based on the pseudo-program counter, and determines, during the first operational mode, whether the processor core will meet a cache miss with regard to the first set of instructions, wherein if it is determined that the processor core will meet a cache miss, the instruction cache receives the first set of instructions from a memory and stores the first set of instructions; a coarse-grained array which is operated during the first operational mode and which performs a second instruction during the first operational mode; and a configuration memory which stores configuration information that is used by the coarse-grained array to perform the second instruction, wherein, when the processor switches from the first operational mode to the second operational mode, if the instruction cache is not finished receiving the first set of instructions from the memory, the instruction cache continues to receive the remaining first set of instructions during the second operational mode and the processor core begins performing the first set of instructions by sequentially performing the first set of instructions that have been received.