Patent ID: 9015399
Filing Date: 2015-04-21
Classification: G06F,G11C

Abstract:
1. A memory module comprising: memory enabling simultaneous access to a plurality of sub cache blocks a for servicing a cache block access; multiple, independent data channels communicatively coupled to said memory, each data channel supporting a sub cache block access to a corresponding sub cache block, wherein an access bus of said memory module is partitioned into eight independent eight-byte sub-buses such that multiple ones of said multiple, independent data channels may be used for servicing said cache-block access; and a separate address/control channel dedicated for receiving only address and control information for memory operations for at least one of the pluralities of the sub cache blocks comprising the cache block access to be simultaneously serviced by the multiple, independent data channels, such that an address and a request type is independently supported for each of said eight-byte sub-buses individually.