Patent ID: 7319348
Filing Date: 2008-01-15
Classification: H03K

Abstract:
1. Circuitry for locally generating a ratio clock on a chip, comprising: circuitry for generating a global clock signal having a global clock cycle; a state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter; staging latches receiving the control signal and generating a clock high signal and a clock low signal, the clock high signal and clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and clock low signal having patterns that match the targeted divided clock frequency and duty cycle; a local pass gate receiving the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.