Patent ID: 6665228
Filing Date: 2003-12-16
Classification: G11C

Abstract:
An integrated memory, comprising:a row decoder; a column decoder for receiving a column address; word lines; bit lines; a memory cell array having memory cells connected to said word lines and to said bit lines, said memory cell array subdivided into a plurality of separate segments including a first segment and a second segment; said word lines each having local word lines including a first local word line disposed in said first segment and a second local word line disposed in said second segment, said first local word line and said second local word line together forming a common global word line decoded by said row decoder, and said first and second local word lines connected up to said column decoder such that said first and second local word lines being decoded individually and segment by segment in a manner dependent on the column address; a main word line running through said segments of said memory cell array, said main word line connected to and driving said local word lines in said segments; and a line for carrying a supply potential; each of said local word lines having a supply potential terminal coupled to said line for receiving the supply potential, said supply potential terminal coupled to said line in a decodable manner in dependence on said column decoder.