Patent ID: 6418078
Filing Date: 2002-07-09
Classification: G09G,G11C,H04B

Abstract:
A synchronous dynamic random access memory device comprising:A. a single chip integrated circuit; B. a dynamic random access memory array formed on the chip, the array including plural array data leads carrying parallel data signals to the array and parallel array address leads carrying parallel address signals to the array, one data signal representing one data bit and one address signal representing one address bit, the array being organized in plural addressable locations with each location containing one data word of plural data bits and each location being randomly addressable by the address signals for writing of one word of data bits from the array data leads to each addressed location; C. a clock signal terminal formed on the chip for receiving a clock signal formed of rising and falling edges regularly spaced in time, the clock signal being continuous during operation of the device; D. an address port formed on the chip; the address port including plural address terminals receiving parallel address signals from external the chip, the received address signals being received at the same time as the clock terminal receives the continuous clock signal, the received address signals indicating and address of a random location in the array; E. an address sequencer coupled between the address port and the array address leads and coupled to the clock signal terminal, the address sequencer receiving the address signals from the address port and providing address signals to the array address leads, the address sequencer sequencing through addresses starting from the address of the random location in the array received from the address port; F. a data port formed on the chip and connecting with the array data leads and the clock signal terminal, the data port including: i. plural data terminals for sending parallel data signals synchronous with the clock signal, each set of parallel data signals representing one data word; and ii. at least a read serial latch serially connected between the data terminals and the array data leads, the at least a read serial latch serially latching the data word signals received from the array data leads and carrying the received data signals to the data terminals synchronous with the clock signal for reading the data signals from the array at the random location indicated by the received address signals; and G. a control data buffer connected to the plural address terminals and connected to the address sequencer, the control data buffer receiving address control data signals from the address terminals for controlling the addresses produced from the address sequencer.