Patent ID: 6771728
Filing Date: 2004-08-03
Classification: H03L

Abstract:
A digital phase detector circuit comprising:a first latch having a first data input node configured to receive a digital input signal, said first latch being configured to generate a first digital output signal at a first data output node in response to said digital input signal and in response to a clock signal; a second latch having a second data input node configured to receive said first digital output signal, said second latch being configured to generate a second digital output signal at a second data output node in response to said first digital output signal and in response to an inverse clock signal; a third latch having a third data input node configured to receive said digital input signal, said third latch being configured to generate a third digital output signal at a third data output node in response to said digital input signal and in response to said inverse clock signal; a fourth latch having a fourth data input node configured to receive said third digital output signal, said fourth latch being configured to generate a fourth digital output signal at a fourth data output node in response to said third digital output signal and in response to said clock signal; a first exclusive OR (XOR) gate configured to receive said first digital output signal and said fourth digital output signal as inputs, said first XOR gate producing a first XOR output signal; and a second XOR gate configured to receive said second digital output signal and said third digital output signal as inputs, said second XOR gate producing a second XOR output signal.