Patent ID: 6258662
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method for making a stacked capacitor dynamic random access memory (DRAM) cell comprising the steps of:forming a first dielectric layer on a pre-processed wafer,forming contact windows to expose said wafer surface,depositing a first conductive layer and forming conductive plugs,depositing a second dielectric layer on top of said conductive plug,forming contact windows in said second dielectric layer exposing said conductive plugs,depositing a second conductive layer on said second dielectric layer and forming a lower electrode for said capacitor,depositing a third dielectric layer on top of said second conductive layer,planarizing said third dielectric layer and said second conductive layer by removing top portions of said layers,removing a remaining portion of said third dielectric layer,depositing a fourth dielectric layer of a thickness smaller than said third dielectric layer, on top of said second conductive layer after said second conductive layer being formed into a lower electrode, anddepositing a third conductive layer on top of said fourth dielectric layer forming upper electrodes for said cylindrical capacitors.