Patent ID: 7292061
Filing Date: 2007-11-06
Classification: H01L,H03K

Abstract:
1. A semiconductor integrated circuit (IC) operated with high and low power voltages, the semiconductor IC comprising a chain of a plurality of CMOS inverters that are coupled through intermediate nodes, the semiconductor IC responding to an input logic signal and providing an output logic signal, the chain of a plurality of CMOS inverters including at least first and second CMOS inverters, each of the first and second CMOS inverters having a first PMOS transistor and a first NMOS transistor that are series-coupled, a first intermediate input logic signal corresponding to the input logic signal being provided to the gates of the series-coupled first PMOS and NMOS transistors of the first CMOS inverter, the coupled node of which provides a first intermediate output logic signal that is a complementary version of the first intermediate input logic signal, a first feedback signal derived from the first intermediate output logic signal being provided to the first CMOS inverter to control the operation thereof, the first intermediate output logic signal being provided to the gates of the series-coupled first PMOS and NMOS transistors of the second CMOS inverter, the coupled node of which provides a second intermediate output logic signal that is a complementary version of the first intermediate output logic signal, a second feedback signal derived from the second intermediate output logic signal being provided to the second CMOS inverter to control the operation thereof, the second CMOS inverter having a second PMOS transistor, the drain of which is coupled to the source of the first PMOS transistor, the high power voltage being provided to the source of the second PMOS transistor, the gate of the second PMOS transistor responding to the second feedback signal.