Patent ID: 7846784
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line including a gate electrode on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line including a source electrode and a drain electrode on the ohmic contact layer; depositing a conductive film on the data line and the drain electrode; forming a first photoresist on the conductive film; etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode; depositing a passivation layer; and removing the first photoresist and a portion of the passivation layer thereon simultaneously to form a passivation member, wherein the gate insulating layer and the semiconductor layer are simultaneously etched, and wherein a boundary of a portion of the passivation layer disposed directly on a top surface of the drain electrode faces a boundary of the pixel electrode.