Patent ID: 7493461
Filing Date: 2009-02-17
Classification: G11C

Abstract:
1. In a memory controller, adapted to write data to an external memory device, and adapted to capture data read from the external memory device, a method of adapting a resynchronization of the captured data with a system clock, comprising: (a) writing a first data from the memory controller to the external memory device in a test pattern; (b) reading the first data in the test pattern from the external memory device into the memory controller and capturing the read data in the test pattern into a register block of the memory controller, wherein the read data is captured using a strobe signal received with the read data; (c) setting a trial value for a relative phase of the captured data and a resynchronization clock of the memory controller; (d) resynchronizing the captured data using the set trial value for the relative phase of the captured data and the resynchronization clock; (e) determining whether the resynchronized captured data meets a predetermined pass criterion; (f) repeating steps (b), (c), (d) and (e) until a plurality of relative phases of captured data and the resynchronization clock have been tested; and (g) selecting one of said relative phases of the captured data and the resynchronization clock for subsequent data reads.