Patent ID: 8525306
Filing Date: 2013-09-03
Classification: B29C,H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising the steps of: (a) providing a large-sized wiring board including an upper surface, a shape in plan view of which is comprised of a quadrangle, a lower surface on the opposite side of the upper surface, a quadrangular frame part, a plurality of device regions formed in an array inside the frame part, a plurality of bonding leads formed in the device regions, respectively, on the upper surface, and a plurality of lands formed in the device regions, respectively, on the lower surface; (b) providing a plurality of semiconductor chips each including a front surface, a shape in plan view of which is comprised of a quadrangle, a plurality of bonding pads formed on the front surface, and a rear surface on the opposite side of the front surface; (c) mounting the semiconductor chips in the device regions on the upper surface of the large-sized wiring board, respectively, by face-up mounting; (d) electrically coupling the bonding pads of the semiconductor chip mounted in the device regions, respectively, and the bonding leads formed in the device regions, respectively, with a plurality of wires; (e) after the step (d), electrically coupling a ball electrode constituting an external coupling terminal to each of the lands; (f) after the step (e), sealing the semiconductor chips and the wires all together with a resin sealing body by attaching the large-sized wiring board to a molding die and injecting a sealing resin into a cavity of the molding die; and (g) after the step (f), dividing the large-sized wiring board into pieces in units of the device regions, wherein the bonding leads formed in the device regions, respectively, have a plurality of first column bonding leads arranged along a first substrate side of the upper surface of the large-sized wiring board in the plan view and a plurality of second column bonding leads arranged along the first substrate side of the upper surface of the large-sized wiring board and arranged between the first column bonding leads and the first substrate side in the plan view, wherein the bonding pads formed on the semiconductor chips, respectively, have a plurality of first column bonding pads arranged along a first chip side of the front surface of the semiconductor chip in the plan view and a plurality of second column bonding pads arranged along the first chip side of the front surface of the semiconductor chip and arranged on the side closer to the central part of the front surface than the first column bonding pads in the plan view, wherein in the step (c), each of the semiconductor chips is mounted on the upper surface of the large-sized wiring board such that the first chip side aligns with the first substrate side of the large-sized wiring board, wherein the step (d) includes the steps of: electrically coupling the first column bonding pads and the first column bonding leads with a plurality of first wires, respectively; and electrically coupling the second column bonding pads and the second column bonding leads with a plurality of second wires, respectively; and wherein in the step (d), the second wires are bonded so as to have parts farther from the upper surface of the large-sized wiring board than the first wires and the diameter of the corner part wire of the second wires, which is coupled to the bonding pad arranged at the corner part on the front surface of the semiconductor chip, is larger than the diameter of each of the first wires and the second wires other than the corner part wire.