Patent ID: 8706795
Filing Date: 2014-04-22
Classification: G06F

Abstract:
1. A method, comprising: element-wise SIMD adding, by a SIMD integer adder, operated by a single-instruction multiple data (SIMD) computing device having SIMD registers, corresponding elements of a first SIMD-sized integer (A) and a second SIMD-sized integer (B) to generate a SIMD-sized integer result (R) and a carry bit, wherein A has an integer size (SizeA), and B has an integer size (SizeB); and in response to SizeA greater than SizeB, updating R and the carry bit, by the SIMD integer adder, in view of one or more elements of A that do not have corresponding element or elements of B; wherein element-wise SIMD adding includes performing one or more mathematical operations on first one or more masks, with the first one or more masks interpreted as integers, and interpreting one or more integer results of the one or more mathematical operations as second one or more masks; wherein performing one or more mathematical operations on first one or more masks comprises performing one or more mathematical operations on a carry mask and a saturation mask, wherein the carry mask indicates whether overflow occurred in each SIMD element during the element-wise SIMD adding, and wherein the saturation mask indicates which element or elements of R has all 1 bits; wherein performing one or more mathematical operations on a carry mask and a saturation mask comprises shifting left the carry mask by 1 bit to generate a first instance of a correction mask; performing a bitwise Boolean OR operation on the first instance of the correction mask with a carry in to generate a second instance of the correction mask; integer adding the saturation mask to the second instance of the correction mask to generate a third instance of the correction mask; and performing a bitwise Boolean XOR operation on the third instance of the correction mask with the saturation mask to generate a fourth instance of the correction mask.