Patent ID: 7851892
Filing Date: 2010-12-14
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a substrate having a semiconductor layer; an n-type semiconductor region formed beneath a main surface of the semiconductor layer; a plurality of cell gates being aligned at a space from each other and including a gate insulating film formed on the main surface of the semiconductor layer, a charge storage layer formed on the gate insulating film, a charge block layer formed on the charge storage layer and a control gate electrode formed on the charge block layer; an insulating film between cells formed on the main surface of the semiconductor layer between the cell gates next to each other, the insulating film between the cells insulating one cell gate from the other cell gate; and a carbon accumulation region formed in the insulating film between the cells and having a maximum concentration of a carbon element in a region within 2 nm from an interface between the semiconductor layer and the insulating film between the cells.