Patent ID: 9058135
Filing Date: 2015-06-16
Classification: G06F,G11C

Abstract:
1. A method of testing a digital system, comprising: calculating a first ratio of a first clock frequency for a first clock domain and a second clock frequency for a second clock domain different from the first clock domain using a processing device; calculating a first offset between a first timer in the first clock domain and a second timer in the second clock domain using the processing device; and using an expression dependent upon the first offset and the first ratio, converting event data from at least one of the first clock domain or the second clock domain to a common clock domain; wherein calculating the ratio comprises: responsive to receiving a first timer value from the first timer within the second clock domain, determining a first timer value from the second timer in the second clock domain: responsive to receiving a second timer value from the first timer within the second clock domain, determining a second timer value from the second timer in the second clock domain; and the second timer value from the first timer is sent responsive to a message sent from the second clock domain to the first clock domain responsive to the first timer value from the first timer.