Patent ID: 6442671
Filing Date: 2002-08-27
Classification: G06F

Abstract:
A system for transferring data between a digital signal processor (DSP) and a memory unit external to said DSP, said system comprising:a memory unit the memory unit external to said DSP; a plurality of buses coupled to said memory unit; the DSP coupled to said plurality of buses, said DSP for receiving data from said memory unit and for processing an application to generate therefrom data to be stored in said memory unit; and a data transfer element coupled between said memory unit and said DSP, wherein said data are transferred into said data transfer element during a first clock cycle and out of said data transfer element during a second clock cycle immediately following said first clock cycle, said data transfer element comprising: a first data bus coupled between said DSP and said memory unit, said first data bus for transferring a first set of data from said DSP to said memory unit; a first latch device coupled to said first data bus; a second data bus coupled between said DSP and said memory unit, said second data bus for transferring a second set of data from said memory unit to said DSP; and a second latch device coupled to said second data bus; said first latch device and said second latch device providing intermediate locations for storing said first and second sets of data between said DSP and said memory unit; an address bus coupled between said DSP and said memory unit; and an address mechanism coupled to said address bus, said address mechanism for mapping an address in said DSP to an address in said memory unit, wherein a specified offset value is added to said address in said DSP to generate said address in said memory unit.