Patent ID: 7675181
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A planar multi semiconductor chip package comprising: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate in an m×n matrix (where m and n are integers equal to or greater than 2), the memory devices comprising first memory devices and at least one second memory device and wherein the first memory devices substantially surround at least a portion of the second memory device; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the at least a portion of the second memory device; a plurality of through electrodes arranged on the second memory device and connecting the first and second semiconductor chips to the second circuit pattern of the substrate; and wherein the second memory device comprises a memory device including a defect.