Patent ID: 6642563
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A semiconductor memory including a ferroelectric gate capacitor structure, comprising:a semiconductor substrate; a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween; an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction; a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of said hole, said capacitor insulating film including a first recess at a position corresponding to said channel region; an upper electrode embedded in said first recess; and a conductive contact plug electrically connected to the upper electrode, said contact plug having a central portion disposed in contact with an upper surface of said upper electrode, and an extending portion extending beyond opposite ends of said upper electrode in said channel length direction, said extending portion being disposed in contact with an upper surface of said capacitor insulating film around said upper surface of said upper electrode.