Patent ID: 6656748
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A method of performing a post capacitor stack etch clean for a ferroelectric memory cell, comprising:forming a bottom electrode layer, a PZT ferroelectric layer, and a top electrode layer over a substrate; etching the top electrode layer, the PZT ferroelectric layer, and the bottom electrode layer to form a capacitor stack, wherein the PZT ferroelectric layer has damage associated therewith due to the etching of the PZT ferroelectric layer; annealing the etched capacitor stack in a chamber having a lead source and oxygen, wherein a vapor pressure of the lead source is greater than a vapor pressure of the etched PZT ferroelectric layer, thereby facilitating a vapor transport of lead from the lead source to the etched PZT ferroelectric layer for repair thereof.