Patent ID: 6327645
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A cache memory system for use with a main memory unit, comprising:a main memory controller having a memory address input and a memory data output, the main memory controller being adapted to be connected to the main memory unit and being adapted to retrieve memory data of the main memory unit corresponding to a requested memory address at the memory address input, and to provide the memory data retrieved thereby at the memory data output;a cache memory having a plurality of addressable storage locations, a write address port to receive a cache write address for addressing one of the storage locations, a write data port connected to the memory data output of the main memory controller so as to receive the memory data therefrom for storage in said one of the storage locations addressed by the cache write address, a read address port to receive a cache read address for addressing one of the storage locations, and a read data port to output the memory data stored in said one of the storage locations addressed by the cache read address;a tag memory module for storing a tag look-up table that includes a plurality of entries, each of the entries including a main memory address of a storage location of the main memory unit and a cache memory address of one of the storage locations of the cache memory,the tag memory module being adapted to receive an address signal, and determining presence of a cache hit condition, where the address signal corresponds to the main memory address of one of the entries of the tag look-up table, or a cache miss condition, where the address signal does not correspond to the main memory address of any one of the entries of the tag look-up table,the tag memory module having a missed address output, a cache write address output and a cache read address output,the tag memory module, upon determining the presence of the cache hit condition, which indicates presence of a valid data entry in the cache memory, outputting the cache memory address belonging to the entry of the tag look-up table that corresponds to the address signal at the cache read address output,the tag memory module, upon determining the presence of the cache miss condition, which indicates need for access to the main memory unit, generating the cache memory address of a selected one of the storage locations of the cache memory to correspond with the address signal, storing the main memory address and the cache memory address that correspond to the address signal as one of the entries of the tag look-up table, outputting the main memory address that corresponds to the address signal at the missed address output, and outputting the cache memory address that corresponds to the address signal at the cache write address output and the cache read address output;a read data controller connected to the cache read address output of the tag memory module and the read address port of the cache memory, the read data controller including a cache read address queue for receiving the cache memory address from the cache read address output, and for providing the cache memory address as the cache read address to the read address port in a first in, first out manner;a data request controller connected to the missed address output and the cache write address output of the tag memory module, and to the memory address input of the main memory controller, the data request controller including a memory request address queue for receiving the main memory address from the missed address output and the cache memory address from the cache write address output, and for providing the main memory address as the requested memory address to the memory address input in a first in, first out manner; anda write data controller connected to the data request controller and the write address port of the cache memory, the write data controller including a cache write address queue for receiving the cache memory address from the memory request address queue, and for providing the cache memory address as the cache write address to the write address port in a first in, first out manner.