Patent ID: 6026501
Filing Date: 2000-02-15
Classification: G06F

Abstract:
A data processor, comprising:a memory location in a memory circuit which is identified by an internal address;a debug module, the debug module processing an external request to access the memory location of the data processor, the debug module asserting a bus request signal to initiate an access operation of the memory location and executing the access operation of the memory location upon receipt of a bus grant signal;a central processing unit for controlling operation of the data processor, the central processing unit executing a plurality of data processing instructions using a pipeline method of operation wherein a first pipeline indicates a plurality of data processing instructions to be executed, the central processing unit selectively asserting a bus grant signal in response to the bus request signal when the plurality of data processing instructions have been executed;bus means for communicating information between each of the debug module, the central processing unit, and the memory, the bus means communicating a data value stored at the memory location to the debug module when the bus grant signal is asserted.