Patent ID: 6562656
Filing Date: 2003-05-13
Classification: H01L,H05K

Abstract:
A method of creating an interconnect substrate overlying a metal panel, said interconnect substrate having a first and a second surface, said interconnect substrate comprising a first and a second patterned layer of interconnect metal, whereby semiconductor devices and Ball Grid Array contact balls are attached to said first surface of said interconnect substrate, comprising the steps of:providing a metal panel said metal panel having a first surface and a second surface, said second surface of said interconnect substrate making contact with said first surface of said metal panel; providing at least one semiconductor device, said at least one semiconductor device being provided with metal bumps for semiconductor device interconnect; cleaning said first surface of said metal panel; creating a first patterned layer of interconnect metal comprising a first layer of interconnect lines and contact pads by depositing a first layer of dielectric over said first surface of said metal panel, then; creating a first via pattern in said first layer of dielectric, providing openings to said first surface of said metal panel, then; depositing a first layer of interconnect metal over said first layer of dielectric, contacting said first surface of said metal panel through the first via pattern in said first layer of dielectric, then; patterning said first layer of interconnect metal, completing said creation of a first layer of interconnect metal; creating a second patterned layer of interconnect metal comprising a second layer of interconnect lines and contact pads by depositing a second layer of dielectric over said first layer of dielectric, including said first patterned layer of interconnect metal, then; creating a second via pattern in said second layer of dielectric, providing openings to said first patterned layer of interconnect metal, then; depositing a second layer of interconnect metal over the surface of said second layer of dielectric, contacting said contact pads in said first layer of interconnect lines through the second via pattern in said second layer of dielectric, then; patterning said second layer of interconnect metal, completing said creation of a second patterned layer of interconnect metal; depositing a third layer of dielectric over the surface of said second layer of dielectric, including said second patterned layer of interconnect metal; creating a third via pattern in said third layer of dielectric, providing openings to said contact pads in said second patterned layer of interconnect metal, whereby said third layer of dielectric serves as a solder mask, providing points of electrical access to said second patterned layer of interconnect metal for semiconductor device bumps and for Ball Grid Array contact balls; subdividing said metal substrate into individual substrates; connecting at least one of said semiconductor devices to said points of electrical access to said second patterned layer of interconnect metal by means of metal bumps provided on said semiconductor devices by solder reflow or by other means of bumps to metal contact pad attachment; filling space between said at least one semiconductor device and said third layer of dielectric with dielectric material by an underfill step; providing Ball Grid Array contact balls; and attaching said Ball Grid Array contact balls to said first surface of said interconnect substrate by solder reflow or by other means of bumps to metal contact pad attachment.