Patent ID: 6518746
Filing Date: 2003-02-11
Classification: G01R

Abstract:
A test mode circuit of an integrated circuit device, comprising:a plurality of bipolar transistors, each having a collector connected to a first supply voltage, a base, and an emitter, with the emitter of a first bipolar transistor connected to the base of a second bipolar transistor and the base of the first bipolar transistor connected to the first supply voltage; a plurality of ETD transistors, each having a first source/drain, a second source/drain, and a gate, with the gate of each ETD transistor being controlled by a signal and with the first source/drain of a first ETD transistor connected to the emitter of the first bipolar transistor and the first source/drain of a second ETD transistor connected to the emitter of the second bipolar transistor, and with the second source/drain of each ETD transistor coupled to a second supply voltage via a first voltage control device controlled by a control signal; a first logic element having an input terminal and an output terminal, wherein a node coupled to the input terminal is defined by the electrical connection of the input terminal of the first logic element, a second voltage control device coupled to the first supply voltage and controlled by the control signal, the emitter of the second bipolar transistor, and the first source/drain of the second ETD transistor; wherein the first ETD transistor operates to ensure that the emitter of the first bipolar transistor is Vbe (base-to-emitter voltage) volts lower than the Vb (base voltage) of the first bipolar transistor and wherein the second ETD transistor operates to ensure that the emitter of the second bipolar transistor is Vbe (base-to-emitter voltage) volts lower than the Vb (base voltage) of the second bipolar transistor.