Patent ID: 6407464
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate; an active region formed by introducing an impurity onto a main surface of said semiconductor substrate; a gate interconnection deposited on the main surface of said semiconductor substrate with an insulating layer interposed; a gate interconnection coating formed of a nitride film enclosing and protecting said gate interconnection; a bit line formed above said gate interconnection crossing said gate interconnection when viewed two-dimensionally; an inter-layer oxide film covering the main surface of said semiconductor substrate and said gate interconnection coated by said gate interconnection coating; a memory cell having a first pad contact formed, penetrating through said oxide film, between said gate interconnection and said bit line, when viewed two-dimensionally and conducting said active region and an upper-layer conducting interconnection, and a second pad contact formed, penetrating through said oxide film, overlapped with said bit line when viewed two-dimensionally, between said gate interconnections, conducting said active region and said bit line via a bit line contact; a first dummy pad contact formed between said gate interconnections, using a self-alignment method, along with an end portion of said memory cell in a dotted line; and means for interrupting an electric conduction occurred between said first dummy pad contact and said bit line somewhere in a path leading from said first dummy pad contact through said active region, said second pad contact and said bit line contact to said bit line.