Patent ID: 7755104
Filing Date: 2010-07-13
Classification: H01L

Abstract:
1. A semiconductor device that has a pMOS double-gate structure, comprising: a substrate, the crystal orientation of the top surface of which is (100); a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at a sidewall of the semiconductor layer; a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of the first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of the first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the current flow direction; and a gate insulating film that is disposed between the semiconductor layer and the gate electrode, wherein a uniaxial tensile strain is applied to the semiconductor layer in the direction of the second <110> crystal orientation perpendicular to the current flow direction, and the gate electrode contains a shrinkable material and the shrinkability causes the uniaxial tensile strain applied to the side wall of the semiconductor layer in the direction of the second <110> crystal orientation perpendicular to the current flow direction, the gate electrode having conductivity.