Patent ID: 7408816
Filing Date: 2008-08-05
Classification: G11C

Abstract:
1. A memory voltage generating circuit, comprising: a core circuit outputting a voltage for a memory, the core circuit comprising: a regulation amplifier, a non-inverting input terminal of the regulation amplifier receiving a first standby voltage, an inverting input terminal of the regulation amplifier connected to an output terminal of the memory voltage generating circuit forming a negative-feedback loop, an output terminal of the regulation amplifier connected to the output terminal of the memory voltage generating circuit through a resistor; a first metal-oxide-semiconductor field-effect transistor (MOSFET), a gate of the first MOSFET connected to the output terminal of the regulation amplifier, a source of the first MOSFET connected to the inverting input terminal of the regulation amplifier, a drain of the first MOSFET receiving the first standby voltage via a switch; and a second MOSFET, a source of the second MOSFET receiving a first system voltage, a drain of the second MOSFET connected to the drain of the first MOSFET; a first control module connected to a gate of the second MOSFET for controlling working states of the second MOSFET, the first control module comprising a first transistor, an emitter of the first transistor receiving a first voltage control signal, a base of the first transistor being connected to the first standby voltage, a collector of the first transistor being connected to the gate of the second MOSFET and receiving a second system voltage as well; and a second control module connected to the non-inverting input terminal of the regulation amplifier for controlling working states of the regulation amplifier, the second control module comprising a second transistor and a third MOSFET, a base of the second transistor receiving a second standby voltage, a collector of the second transistor connected to the non-inverting input terminal of the regulation amplifier, a drain of the third MOSFET connected to the base of the second transistor, a gate of the third MOSFET receiving a second voltage control signal.