Patent ID: 6737885
Filing Date: 2004-05-18
Classification: G06F,H03K

Abstract:
A power detection circuit comprising:a first circuit coupled to a first plurality of power supplies, wherein an output of the first circuit is at a first logic level when at least one of the first plurality of power supplies is not at full rail level, and is tri-stated when each of the power supplies of the first plurality is at full rail level; a second circuit coupled to the first plurality of power supplies and the output of the first circuit, wherein an output of the second circuit is tri-stated when at least one of the first plurality of power supplies is not at full rail level, and is at a second logic level when each of the first plurality of power supplies is at full rail level; and a third circuit coupled to the output of the first circuit and the output of the second circuit, wherein the third circuit provides a power detection signal that is substantially related to the output of the first circuit when at least one of the first plurality of power supplies is not at full rail level, and is substantially related to the output of the second circuit when each of the first plurality of power supplies is at full rail level.