Patent ID: 6526430
Filing Date: 2003-02-25
Classification: G06F,H04N

Abstract:
An image processing peripherial comprising:a plurality of pairs of multiply accumulate circuits connected in parallel, each pair of multiply accumulate circuits comprising; first adder pairs, each one of each adder pair having first and second inputs receiving respective first and second inputs having a first predetermined number of bits and an output producing a sum or a difference of said inputs; first multiplier pairs, corresponding to said first adder pairs, each multiplier of each multiplier pair having a first input of said sum or difference of said first adders and a second input of a constant predetermined number and producing a product output; second adder pairs, corresponding to said first multiplier pairs, each one adder of said adder pair having first and second inputs receiving respective first multiplier outputs from one or the other of said multipliers of said corresponding multiplier pair as said first input and wherein said one of said pair of second adders receives an output from a first multiplexer, said first multiplexer having one input from a product of the other multiplier of said first multiplier pairs and a second input from an accumulated sum of said one adder of said second adder pairs as a second input of said one adder of said second adder pair and; wherein said other of said pair of second adders receives outputs from a second and a third multiplexer, said second multiplexer having one input from said other multiplier of said first multiplier pair and a second input from the sum of said one adder of said second adder pair, said third multiplexer having one input from the accumulated sum of said other adder of said second adder pair and a second input from the sum of a one adder of a second pair of second adder pairs, and; wherein each second adder of said second adder pairs produces a sum output according to selection made by said first, second and third multiplexers.