Patent ID: 7830693
Filing Date: 2010-11-09
Classification: G11C,H01L

Abstract:
1. An apparatus comprising a NAND block of non-volatile memory unit cells in a semiconductor memory array, each of the unit cells comprising a resistive sense element connected in parallel with a switching element, wherein the resistive sense elements are connected in series to form a first serial path and the switching elements are connected in series to form a second serial path parallel to the first serial path, and wherein each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically therebetween to provide operational isolation of said element, the resistive sense elements of the block each having a nominally common height at a selected elevation above a base substrate, and the portion of the tortuous path that extends substantially vertically between each adjacent pair of the resistive sense elements extending upwardly across said common height.