Patent ID: 6671841
Filing Date: 2003-12-30
Classification: G01R

Abstract:
A method for testing a processor having at least one functional unit using the JTAG standard, said method comprising:coupling a synchronizer to said processor, said synchronizer generating a signal â€œsync_ceâ€  at a synchronizer first output terminal and a signal â€œsync_seâ€  at a synchronizer second output terminal, said synchronizer having a synchronizer first input terminal, a synchronizer second input terminal; a synchronizer third input terminal and a synchronizer fourth input terminal; coupling a system clock to said processor, said system clock generating a signal â€œCLKâ€  with a first frequency at a system clock first output terminal, said system clock first output terminal being coupled to said synchronizer third input terminal; coupling a JTAG controller to said processor, said JTAG controller having a JTAG controller first signal â€œjt-shadow_ceâ€  at a JTAG controller first output terminal and a signal â€œjt_shadow_seâ€  at a JTAG controller second output terminal, said JTAG controller first output terminal being coupled to said synchronizer first input terminal and said JTAG controller second output terminal being coupled to said synchronizer second input terminal; coupling a JTAG clock to said processor, said JTAG clock generating a signal â€œTCKâ€  with a second frequency at a JTAG clock first output terminal, said JTAG clock first output terminal being coupled to said synchronizer fourth input terminal; coupling said synchronizer first output terminal to a functional unit first input terminal of a functional unit; coupling said synchronizer second output terminal to a functional unit second input terminal of said functional unit; said functional unit comprising: a primary scan path; and a shadow scan path; wherein in response to said signals sync_ce and sync_se from said synchronizer, said shadow scan path receives data contained in said primary scan path and scans said data out of said functional unit for testing the operation of said processor while said processor continues its normal operations.