Patent ID: 7057932
Filing Date: 2006-06-06
Classification: G11C,H01L

Abstract:
1. A flash memory, comprising: at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate; a memory control circuit for controlling operations on the at least one floating-gate memory cell; a wordline coupled to the control gate of the at least one memory cell; and a wordline drive transistor coupled to the wordline; wherein the memory control circuit is adapted to supply a positive voltage pulse to the source relative to a common voltage while supplying a negative voltage pulse to the control gate relative to the common voltage; wherein the memory control circuit is further adapted to discharge the positive voltage pulse while continuing to supply the negative voltage pulse; and wherein the memory control circuit is further adapted to discharge the negative voltage pulse before re-supplying a positive voltage pulse to the source relative to the common voltage.