Patent ID: 6084261
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A capacitor of a dynamic random access memory cell, said capacitor comprising:a semiconductor layer;a first dielectric layer formed over said semiconductor layer;a silicon oxide layer formed on said first dielectric layer;a first conductive region formed on a portion of said silicon oxide layer, said first conductive region communicating to said semiconductor layer via a hole in said first dielectric layer;at least two second conductive regions formed on said first conductive region, each of said at least two second conductive regions being spaced from each other;at least two third conductive regions formed on said silicon oxide layer, each of said at least two third conductive regions being spaced from each other, each of said at least two third conductive regions being spaced from each of said at least two second conductive regions, wherein a portion of each of said at least two third conductive regions abuts a sidewall of said first conductive region;a second dielectric film formed on surface of said first conductive region, said at least two second conductive regions, and said at least two third conductive regions; anda conductive layer formed on said second dielectric film.