Patent ID: 6662280
Filing Date: 2003-12-09
Classification: G06F

Abstract:
An apparatus comprising:a buffer including a plurality of entries, wherein each of said plurality of entries is configured to store: (i) at least an index portion of a store address of a store memory operation, (ii) a hit indication indicative of whether or not said store memory operation hits in a data cache, and (iii) store data corresponding to said store memory operation; and circuitry coupled to said buffer and coupled to receive: (i) said index portion of a load address of a load memory operation probing said data cache, and (ii) a load hit signal indicative of whether or not said load memory operation hits in said data cache, wherein said circuitry is configured to cause said store data to be forwarded from a first entry of said plurality of entries responsive to said index portion stored in said first entry matching said index portion of said load address and further responsive to said hit indication in said first entry indicating hit and said load hit signal indicating hit.