Patent ID: 7315918
Filing Date: 2008-01-01
Classification: G06F

Abstract:
1. A programmable logic device having an embedded processor, comprising: a data-side memory controller coupled to the embedded processor; an instruction-side memory controller coupled to the embedded processor; a data-side memory block coupled to the data-side memory controller, the data-side memory block including at least one data memory group; an instruction-side memory block coupled to the instruction-side memory controller, the instruction-side memory block including at least one instruction memory group; the programmable logic device having a columnar architecture, wherein the data-side memory block, the instruction-side memory block and the embedded processor all span one or more columns of the programmable logic device; the embedded processor being located between the data-side memory block and the instruction-side memory block; the instruction-side memory block and the data-side memory block being formed from a double-wide block random access memory column; the at least one data memory group composed of at least four block random access memories of the double-wide block random access memory column in a two-by-two array thereof; the at least one instruction memory group composed of at least two block random access memories of the double-wide block random access memory column in a one-by-two array thereof; a central point of the programmable logic device not being encompassed by a processor block in which the embedded processor, the data-side memory controller and the instruction-side memory controller are located; and wherein the at least one data memory group and the at least one instruction memory group are respectively located on opposing sides of the processor block.