Patent ID: 6090697
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method for fabricating an integrated circuit including a plurality of metal layers separated by dielectric layers, said method comprising the steps of:(a) forming a first conductive layer;(b) covering said first conductive layer with a conductive etchstop layer;(c) patterning and etching said etchstop layer in a desired pattern;(d) removing portions of said first metal layer not covered by said patterned etchstop layer;(e) depositing an interlevel dielectric layer on said etchstop layer plus first conductive layer;(f) etching a portion of said interlevel dielectric layer above said etchstop layer plus first conductive layer with an etchant that removes said interlevel dielectric layer at least thirty times faster than said etchstop layer to form a via through said interlevel dielectric layer having a bottom on said etchstop layer; and(g) filling said via with a second conductive layer.