Patent ID: 8578305
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a first instruction generated for forming gate structures for an NFET and a PFET on a wafer; a second instruction generated for forming sidewalls on the gate structures for the NFET and the PFET using a same deposition and etching process; and a third instruction generated for providing stress materials in source and drain regions of the NFET and the PFET, wherein said third instruction further comprises: forming, in a single masking process, recesses in source and drain regions of the NFET and the PFET in the wafer; filling the recesses with a single type of stress material; blocking one of the NFET and the PFET; etching out the single type of stress material in the source and drain regions of an unblocked one of the NFET and the PFET to reform recesses; and filling in the reformed recesses with a different type of stress material.