Patent ID: 8541877
Filing Date: 2013-09-24
Classification: H01L

Abstract:
1. An electronic device package, comprising: a carrier wafer; an electronic device chip disposed over the carrier wafer, wherein the electronic device chip has a plurality of conductive pads disposed thereon; an isolation combo layer comprising a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer, wherein the lower first isolation layer has a plurality of first openings to expose the plurality of conductive pads, and the upper second isolation layer conformably covers the lower first isolation layer and inner walls of the first openings, wherein the upper second isolation layer located in the first openings has a plurality of second openings respectively located in the first openings to expose the plurality of conductive pads; a plurality of redistribution patterns isolated from each other conformably formed on the isolation combo layer and in the first openings and the second openings, electrically connecting to the plurality of conductive pads, respectively; and a plurality of conductive bumps respectively formed on the plurality of redistribution patterns, electrically connecting to the plurality of conductive pads.