Patent ID: 6707866
Filing Date: 2004-03-16
Classification: H03K,H04L

Abstract:
A clock signal generating apparatus comprising:selection means for selecting one of two frequency-dividing number data items in accordance with selection data, one of data items representing at least one integral frequency-dividing number greater than a ratio (fa/fb) of a frequency (fa) of an input clock signal to a frequency (fb) of a target output clock signal, and an other of the data items representing at least one integral frequency-dividing number smaller than the ratio (fa/fb); frequency-dividing means for dividing a frequency of the input clock signal by the frequency-dividing number represented by the data item selected by the selection means, thereby generating an output clock signal; and selection data generating means for generating the selection data in accordance with frequency data representing a target frequency (fb), the selection data causing the selection means to select the frequency-dividing number data item repeatedly in response to clock pulses of the input clock signal, thereby dividing the frequency of the input clock signal and to make an average frequency of the clock signal output from the frequency-dividing means equal to the frequency (fb).