Patent ID: 6973405
Filing Date: 2005-12-06
Classification: G06F

Abstract:
1. An integrated circuit comprising: a processor; memory for storing code executable by the processor; a module under test that performs predetermined operations; an address bus; a programmable verification agent that interacts with the module under test, including sending at least one stimulus to the module under test and generating results based on such interaction, wherein the programmable verification agent comprises a plurality of testing modules formed in a programmable logic device and an address decoder for generating at least one control signal in response to an address in the address bus, the at least one control signal being connected to one of the testing modules, wherein at least one of the testing modules generates an output in response to receiving the at least one control signal, the output being used as the at least one stimulus; and wherein the code causes the processor to initiate the programmable verification agent, receive the results, and compare the results with expected values.