Patent ID: 6505277
Filing Date: 2003-01-07
Classification: G06F

Abstract:
In a multiprocessor data processing system with a first processor having a first cache and a second processor having a second cache and a cache operating protocol that supports intervention of data among caches, a method for ordering the time of execution of a load instruction to effectuate return of intervened data at a scheduled time, said method comprising the steps of:determining a value of a cycle of dependency (CoD) that is appended to a load instruction that was issued by said first processor to said first cache, said CoD value corresponding to a time on a synchronized timer (ST) of said data processing system at which said data is actually required by a process executing on said first processor, wherein said process executes a number of cycles following issuance of said load instruction from said first processor, said number of cycles being utilized within a calculation of said CoD value; responsive to a miss at said first cache, broadcasting said load instruction with said appended CoD to other memory components of said data processing system including intervening caches; and responsive to a hit at said second cache of said second processor, which supports intervention of data to said first cache, intervening data requested by said load instruction at a time associated with said CoD, wherein said data is returned to execution units of said first processor at the time that said data is actually required for utilization within the process executing on the first processor.