Patent ID: 6810042
Filing Date: 2004-10-26
Classification: H04L

Abstract:
An apparatus comprising:a processing module comprising one or more processors to process information into segmented information; a plurality of communication interface boards coupled to said processing module, said plurality of communication interface boards to transmit said segmented information, each communication interface board having a set individual transmission speed, wherein, a first communication interface board having a first set transmission speed amongst the transmission speeds offered by said plurality of communication interface boards does not have a buffer outside a physical layer interface that is incorporated onto said first communication board to queue that portion of said segmented information that is sent to said physical layer interface; a buffer that is incorporated onto a second communication interface board having a second set transmission speed amongst the transmission speeds offered by said plurality of communication interface boards, the buffer being sized to accommodate said second set individual transmission speed, said buffer to queue segmented information to be transmitted by said second communication interface board, said second set transmission speed higher than said first set transmission speed.