Patent ID: 6316319
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises sequentially:forming a dielectric layer on an upper surface of a semiconductor substrate;forming a silicon layer on the dielectric layer;patterning the silicon layer to form a gate electrode having an upper surface and side surfaces;ion implanting impurities, using the gate electrode as a mask, to form source/drain extension implants in the semiconductor substrate;depositing an insulating layer;etching the insulating layer to form sidewall species on the side surfaces of the gate electrode;depositing a metal on the semiconductor device;reacting the metal with silicon in the gate electrode and in the semiconductor substrate to form a metal-silicide layer on the gate electrode and on the semiconductor substrate, before activation annealing the source/drain extension implants; andion implanting impurities, using the gate electrode and sidewall spacers as a mask, to form moderately or heavily doped implants in the semiconductor substrate and to dope the gate electrode.