Patent ID: 6457168
Filing Date: 2002-09-24
Classification: G03F,H01L

Abstract:
A method for producing structures on a surface of a semiconductor wafer, which comprises:generating a primary layout of structures to be produced on a surface of a semiconductor wafer, in accordance with predetermined desired physical parameters of the structures; correcting the primary layout based on production- or technology-dictated deviations to be expected in a following structuring step; calculating parasitic fault parameters that would result from the semiconductor structures after a production thereof in accordance with the corrected primary layout; correcting the primary layout in accordance with a result obtained in the step of calculating the parasitic fault parameters; producing a mask based on the layout corrected in accordance with the parasitic fault parameters; and structuring the surface of the semiconductor wafer in an etching process subject to the production- or technology-dictated deviations from the shapes produced on the mask based on the primary layout.