Patent ID: 6348389
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A method for forming and etching a resist protect oxide layer, which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window, comprising the steps of:a. forming a shallow trench isolation on a semiconductor substrate; said semiconductor substrate having a first area and a second area; said first area being separated from said second area by said shallow trench isolation; b. forming a gate on said first area of said semiconductor substrate; said gate comprising source and drain regions; c. depositing a resist protect oxide layer over said semiconductor substrate, said gate and said shallow trench isolation; said resist protect oxide layer consisting of silicon oxynitride; d. forming a photoresist mask having an opening over said first area; e. etching said resist protect oxide layer using an end-point etch mode; thereby exposing said first area of said semiconductor substrate; f. removing said photoresist mask; and g. forming silicide regions over said source and drain regions.