Patent ID: 9082331
Filing Date: 2015-07-14
Classification: G09G,H04N

Abstract:
1. An array substrate for VA (vertical alignment) liquid crystal display panel, which comprises: at least a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines and a plurality of pixel units arranged in a matrix form; each of the plurality of pixel units further comprising: switch element and pixel electrode, and each of the plurality of pixel units corresponding to at least one of the plurality of first scan lines, one of the plurality of second scan lines and one of the plurality of data lines; the pixel electrode at least comprising a first sub electrode, a second sub electrode and a third sub electrode; number of the switch element of each of the plurality of pixel units being at least three, comprising a first switch element, a second switch element and a third switch element, respectively; output terminals of the first switch element, the second switch element and the third switch element being electrically connected to the first sub electrode, the second sub electrode and the third sub electrode, respectively; input terminals of the first switch element and the second switch element being electrically connected to the one of the plurality of data lines; control terminals of the first switch element and the second switch element being electrically connected to the one of the plurality of first scan lines individually, and control terminal of the third switch element being electrically connected to the one of the plurality of second scan lines; wherein under condition of input terminal of the third switch element being electrically connected to the one of the plurality of data lines, the one of the plurality of second scan lines inputting scan signal to control the third switch element to conduct when entering 3D display mode, the one of the plurality of data lines inputting a voltage signal corresponding to BM (black matrix) image through the third switch element to the third sub electrode, and then stopping inputting scan signal to the one of the plurality of second scan lines; after stopping inputting scan signal to the one of the plurality of second scan lines, the one of the plurality of first scan lines inputting scan signal to control the first switch element and the second switch element to conduct, the one of the plurality of data lines inputting voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode; when entering 2D display mode, the one of the plurality of first scan lines and the one of the plurality of second scan lines inputting scan signal respectively to control the first switch element, the second switch element and the third switch element to conduct, the one of the plurality of data lines inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element respectively to the first sub electrode, the second sub electrode and the third sub electrode, and controlling a default voltage difference existing between at least two sub electrodes of the first sub electrode, the second sub electrode and the third sub electrode.