Patent ID: 7443207
Filing Date: 2008-10-28
Classification: H03K

Abstract:
1. A differential output circuit, comprising: a bias circuit connected with a first voltage; an input circuit section comprising first and second MOS transistors of a first conductive type, wherein said first and second MOS transistors are connected with said first voltage through said bias circuit, and gates of said first and second MOS transistors receive a differential input signal; first and second resistance elements; and third and fourth MOS transistors of a second conductive type connected with said first and second MOS transistors through said first and second resistance elements, respectively, and connected with a second voltage, wherein a first connection node between said first MOS transistor and said first resistance element is connected with a gate of said fourth MOS transistor, wherein a second connection node between said second MOS transistor and said second resistance element is connected with a gate of said third MOS transistor, wherein a differential output signal is outputted from a first output node between said first resistance element and said third MOS transistor and a second output node between said second resistance element and said fourth MOS transistor in response to said differential input signal and wherein said bias circuit comprises: a third resistance element connected between said first MOS transistor and the first voltage; a fourth resistance element connected between said second MOS transistor and the first voltage; and a capacitance element connected between a first node between said first MOS transistor and said third resistance element and a second node between said second MOS transistor and said fourth resistance element.