Patent ID: 8898517
Filing Date: 2014-11-25
Classification: G06F

Abstract:
1. An apparatus for handling a failed processor of a multiprocessor information handling system, the multiprocessor information handling system comprising at least two processors interconnected by processor interconnects for facilitating transactions of the processors, the at least two processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor information handling system, the apparatus comprising: a baseboard management module for detecting and receiving health information of the at least two processors; a multiplexer coupled to the baseboard management controller and respectively to the at least two processors, wherein the multiplexer is operative to switch between the at least two processors; a first processor socket for accommodating the first processor and a second processor socket for accommodating the second processor; and a processor ID controller coupled to the baseboard management controller and respectively to the at least two processors, wherein the processor ID controller comprises a processor socket ID controller for setting either the first processor received in the first processor socket as the default boot processor or the second processor received in the second processor socket as the default boot processor; wherein, in response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management controller enables the multiplexer to switch to the second processor.