Patent ID: 6710371
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a pair of a first power wiring and a second power wiring, the pairs being arranged in one direction, wherein a first region between the first power wiring and the second power wiring; fundamental circuit units constituted by combining one or more PMOS transistors and one or more NMOS transistors, the fundamental circuit units being arranged along with the first power wiring and the second power wiring; logic circuit units constituted by a plurality of the fundamental circuit units; functional circuit units constituted by a plurality of the logic circuit units, the functional circuit units being connected each other; wherein at least one part of the PMOS transistors and that of the NMOS transistors are arranged below the first power wiring and the second power wiring; and unit connection wirings to connect between the fundamental circuit units or to connect between the logic circuit units, of which terminals terminate at the functional circuit units are arranged on second regions that are other than the first region, in case the unit connection wirings are constituted by a layer that is same as a wiring layer that constitutes the first power wiring and the second power wiring or by wiring layers that are under the wiring layer of the first and second power wirings.