Patent ID: 8954941
Filing Date: 2015-02-10
Classification: G06F

Abstract:
1. Method carried out by an apparatus of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising: a) receiving, in an instruction memory, at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions; b) initializing a set of removed instructions as empty; c) determining the most compact representation of the first set of instructions by applying a compression factor to obtain a size of a processor view of the first set of instructions, wherein the size of the view corresponds to a number of instruction bits; d) comparing the size of the view of said most compact representation with a goal size of a view, the goal size serving as a threshold value; e) carrying out operations e1 to e3 if the size is larger than said threshold value; e1) determining which instruction of the first set of instructions has a highest coding cost; e2) removing said instruction having the highest coding cost from the first set of instructions; and e3) adding said instruction to the set of removed instructions in a second instruction memory; and f) repeating operations b-f using a different compression factor, wherein the first set of instructions is formed by the set of removed instructions.