Patent ID: 6275086
Filing Date: 2001-08-14
Classification: G11C,H03K

Abstract:
A semiconductor integrated circuit comprising:a plurality of clock signal input circuits, including a first clock signal input circuit and a second clock signal input circuit, each receiving a respective one of a plurality of external clock signals and generating a respective one of a plurality of internal clock signals;an external control signal input circuit for receiving an external control signal and generating an internal control signal; andan output control circuit for receiving the internal control signal and controlling the output of the internal clock signals, wherein the output control circuit includes:a latch circuit connected to the external control signal input circuit and the first clock signal input circuit, where the latch circuit latches the internal control signal in response to a first internal clock signal generated by the first clock signal input circuit;a first enable signal generating circuit connected to the latch circuit and the first clock signal input circuit, wherein the first enable signal generating circuit holds the latched internal control signal in response to the first internal clock signal and generates a first enable signal;a gate circuit connected to the first enable signal generating circuit and the first clock signal input circuit, wherein the gate circuit controls the output of the first internal clock signal in accordance with the first enable signal; anda second enable signal generating circuit connected to the first enable signal generating circuit and the second clock signal input circuit, wherein the second enable signal generating circuit holds the first enable signal in response to the first internal clock signal and generates a second enable signal for selectively activating and deactivating the second clock signal input circuit.