Patent ID: 6737900
Filing Date: 2004-05-18
Classification: H03K

Abstract:
A d-type flip-flip (DFF) circuit, comprising:a) a first transistor stage, having a first P transistor, a first N transistor, a first signal input, a first clock input and a first signal output, wherein the first signal input is coupled to the first P transistor, and wherein the first clock input is coupled to the first N transistor, and wherein the first P transistor and the first N transistor are serially coupled, and wherein the first transistor stage has a first I/O speed; b) a second transistor stage, operatively coupled to the first transistor stage, having a second P transistor, a second N transistor, a second signal input, a second clock input and a second signal output, wherein the first signal output is coupled to the second signal input, and wherein the second signal input is coupled to the second P transistor, and wherein the second clock input is coupled to the second N transistor, and wherein the second P transistor and the second N transistor are serially coupled, and wherein the second transistor stage has a second I/O speed that is slower than the first I/O speed; and c) a third transistor stage, operatively coupled to the second transistor stage, having a third P transistor, a third N transistor, a third signal input, a third clock input and a third signal output, wherein the second signal output is coupled to the third signal input, and wherein the third signal input is coupled to the third N transistor, and wherein the third clock input is coupled to the third P transistor, and wherein the third P transistor and the third N transistor are serially coupled.