Patent ID: 6646509
Filing Date: 2003-11-11
Classification: H03F,H03G

Abstract:
A method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate, the electrical circuit including an electrical component having (i) input and output ports and (ii) a plurality of cascaded impedance devices configured for connection along a feedback path formed between the input and output ports, each impedance device having a predetermined impedance value, the method comprising:forming sets of parallel connected resistors, each set (i) corresponding to one of the impedance devices, (ii) including two or more parallel resistor paths, each resistor path including two or more cascaded resistors, and (iii) having a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device; and configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed thereon, the interdigital structure being formed when the parallel resistor paths split at one point on the substrate and recombine at another point.