Patent ID: 8335871
Filing Date: 2012-12-18
Classification: G06F

Abstract:
1. A memory system comprising: a first memory device connected to a system bus and comprising a first control sequencer that receives, stores and executes first microcode to control operation of the first memory device; a second memory device connected to the system bus and comprising a second control sequencer that receives, stores and executes second microcode to control operation of the second memory device; a host connected to the first and second memory devices via the system bus, the host comprising a top control sequencer that receives, stores and executes main microcode to control operation of the first and second control sequencers; and a system direct memory access (DMA) that transfers the first microcode to the first control sequencer, the second microcode to the second control sequencer, and the main microcode to the top control sequencer via the system bus.