Patent ID: 8571170
Filing Date: 2013-10-29
Classification: G09G,G11C

Abstract:
1. A shift register circuit comprising: first and second input terminals, first and second output terminals, and first and second clock terminals; first and second voltage signal terminals respectively supplied with first and second voltage signals that are complementary to each other; a first transistor that supplies said first output terminal with a first clock signal inputted to said first clock terminal; a second transistor that supplies said second output terminal with a second clock signal inputted to said second clock terminal; a third transistor that supplies said first voltage signal to a first node to which a control electrode of said first transistor connects or a second node to which a control electrode of said second transistor connects, in response to activation of a first input signal inputted to said first input terminal; a fourth transistor that supplies said second voltage signal to said first node or said second node in response to activation of a second input signal inputted to said second input terminal; and a fifth transistor connected between said first node and said second node, wherein said first clock signal and said second clock signal have a same phase, and a setting is possible such that only said second clock signal is activated and the first clock signal is kept at an inactive level in a particular period.