Patent ID: 6469947
Filing Date: 2002-10-22
Classification: G11C

Abstract:
A semiconductor memory device comprising:a block set having a plurality of cell array blocks which each is divided into a plurality of regions which employ wordlines independently from each other; row driving means to alternatively select the wordlines arranged each in the regions, the row driving means comprising a first buffer for generating compressed row address signals and NK refresh address signals in response to control signals and row address signals corresponding to two-grouped wordlines wherein N is an integer and K is the number of wordlines of a cell array, a block selection circuit for selecting an alternative one of the cell array blocks in response to a block selection address signal and the compressed row address signals, a second buffer for buffering and decoding wordline selection address signals, and a wordline selection circuit for activating an alternative one of the wordlines of the selected cell array block in response to the NK refresh address signals, the block selection address signal assigned to the selected cell array block, and the decoded wordline selection address signal; and column driving means to activate columns of the cell array blocks involved in the wordlines selected by the row driving means.