Patent ID: 7139905
Filing Date: 2006-11-21
Classification: G06F

Abstract:
1. An apparatus, comprising: a bi-endian processor having an endian select input, the processor configured to control a first signal; a circuit coupled to the bi-endian processor, the circuit configured to generate a second signal in response to the first signal, the endian select input of the processor being configured to receive the second signal; and a memory coupled to the processor, the memory storing a set of instructions, wherein the set of instructions are configured such that when the bi-endian processor interprets and executes the instructions in a first endian mode, the instructions cause the bi-endian processor to generate the first signal, and such that when the bi-endian processor interprets and executes the same set of instructions in a different second endian mode, the instructions do not cause the bi-endian processor to generate the first signal.