Patent ID: 6271084
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A method of fabricating a metal-insulator-metal (MIM), capacitor structure, on a semiconductor substrate, using a damascene process, comprising the steps of:providing a metal interconnect structure, embedded in an insulator layer, with said metal interconnect structure overlying and contacting a conductive region in said semiconductor substrate;forming a composite insulator layer, comprised of an underlying, first insulator stop layer, a low dielectric constant, (low k), insulator layer, and an overlying second insulator stop layer;anisotropically forming a first capacitor opening in said second insulator stop layer, and in said low k insulator layer;isotropically forming a lateral recess in said low k insulator layer;removing portion of said first insulator stop layer, exposed in said first capacitor opening, to form a final capacitor opening, exposing a portion of a top surface of said metal interconnect structure;forming a bottom electrode structure in said final capacitor opening, with said bottom electrode structure overlying and contacting said metal interconnect structure;depositing a high dielectric constant (high k), insulator layer;depositing a metal layer, completely filling said final capacitor opening; andremoving portions of said metal layer, and of said high k insulator layer from a top surface of said second insulator stop layer, resulting in a damascene type, capacitor structure, in said final capacitor opening, with said capacitor structure comprised of a top electrode structure, formed from said metal layer, a capacitor dielectric layer, formed from said high k insulator layer, and an underlying bottom electrode structure.