Patent ID: 9164534
Filing Date: 2015-10-20
Classification: G06F,H03K

Abstract:
1. A circuit for skew reduction, comprising: a plurality of first signal lines configured to transmit a plurality of first signals delayed by a plurality of first paths respectively; a plurality of second signal lines configured to transmit a plurality of second signals delayed by a plurality of second paths respectively; and a first swap circuit configured to swap and connect at least one of the plurality of first signal lines to at least one of the plurality of second signal lines in correspondence with a first control signal, wherein the first swap circuit is configured to swap and connect the at least one of the plurality of first signal lines to the at least one of the plurality of second signal lines, when a mutual delay time difference of the plurality of second signals in a state where the at least one of the plurality of first signal lines is swapped and connected to the at least one of the plurality of second signal lines is smaller than a mutual delay time difference of the plurality of second signals in a state where the plurality of first signal lines is connected to the plurality of second signal lines without being swapped.