Patent ID: 7853951
Filing Date: 2010-12-14
Classification: G06F

Abstract:
1. A processor, comprising: multiple programmable units integrated on a single die, each of the multiple programmable units to provide multiple program threads of execution; and circuitry integrated on the die, communicatively coupled to the multiple programmable units, the circuitry to reorder and grant lock requests received from the threads provided by the multiple programmable units based on an order in which the threads requested insertion into a sequence of lock grants, said circuitry configured to: (1) (a) receive a request for a sequence number for a specified lock from a one of the multiple programmable units, the request specifying the lock and one of multiple sequence domains; (2) (a) receive a lock request specifying a sequence number and a sequence number domain; (3) (a) receive a lock request not specifying a sequence number; (4) (a) receive an unlock request;