Patent ID: 6111795
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A memory device comprising:a buffer gate having an input to receive a row address;a row address register having a data input coupled to an output of said buffer gate, having a clock input;a complementary signal generation circuit having a data input coupled to a data output of said row address register;a predecoder having a data input coupled to a data output of said complementary signal generation circuit;a word decoder having a data input coupled to a data output of said predecoder;a control circuit for providing a control signal;a first timing generation circuit for delaying said control signal to generate a first strobe signal, said first strobe signal being provided to said clock input of said row address register; anda second timing generation circuit for delaying said first strobe signal to generate a second strobe signal,wherein a downstream side circuit which is downstream from said row address register has a strobing circuit, coupled in a data stream, for strobing its input data in response to said second strobe signal.