Patent ID: 9104829
Filing Date: 2015-08-11
Classification: G06F

Abstract:
1. A system for validating timing issues in a gate-level simulation of an integrated circuit design having a plurality of cells, the system comprising: a memory for storing the integrated circuit design and instructions; and a processor coupled to the memory, wherein the instructions are executed on the processor to run a simulation routine of a behavioral model of the integrated circuit design and obtain a first simulation result, and wherein the processor includes, if the first simulation result yields a possible timing violation at a cell corresponding to a forcing indeterminate value, means for forcing the simulated output of the cell to a first value, re-running the simulation routine, and obtaining a second simulation result; if the first simulation result does not yield a possible timing violation at the cell, means for generating a report indicating no apparent timing violation; if the second simulation result yields an apparent timing violation at the cell, means for generating a report of the apparent timing violation at the cell; if the second simulation result does not yield an apparent timing violation at the cell, means for generating a report of the first value and status of the simulated output of the cell, forcing the simulated output of the cell to a second value, re-running the simulation routine, and obtaining a third simulation result; if the third simulation result yields an apparent timing violation at the cell, means for generating a report of the apparent timing violation at the cell; and if the third simulation result does not yield an apparent timing violation at the cell, means for completing the simulation.