Patent ID: 9203606
Filing Date: 2015-12-01
Classification: G09G,H03L,H04L

Abstract:
1. A data receiving device comprising: a voltage control delay configured to delay a first or second master clock signal, and generate delayed clock signals which have time differences; a delay control circuit configured to feed back a part of the delayed clock signals, and control a delay time by which the first or second master clock signal is to be delayed in the voltage control delay, in correspondence to a phase difference of the fed-back delayed clock signals; and a clock generator configured to perform recovery of the first master clock signal by using a first clock-embedded data signal before a clock is locked and recovery of the second master clock signal by using a second clock-embedded data signal after the clock is locked, detect a clock edge of an embedded clock signal from the second clock-embedded data signal including the embedded clock signal in which the clock edge is scrambled, perform descramble of recovering the second master clock signal by sequentially performing pulldown and pullup after the detected clock edge, and control the detection of the clock edge, the pulldown and the pullup by using the delayed clock signals.