Patent ID: 6754110
Filing Date: 2004-06-22
Classification: G11C

Abstract:
A memory devices comprising:a memory cell; an evaluation circuit; a reference line connected to said evaluation circuit; a bit line defining a bit line direction; said memory cell being connected to said evaluation circuit via said bit line; said evaluation circuit being an amplifier selected from the group consisting of a measurement amplifier and a sense amplifier; said evaluation circuit containing two partial regions, whereas a first of said partial regions includes a first and a second n-channel MOS transistor and a second of said partial regions includes a first and a second p-channel MOS transistor; a first signal line, said bit line being connected, within said evaluation circuit, to said first signal line; a second signal line, said reference line being connected, within said evaluation circuit, to said second signal line; said first and second signal lines being formed within said evaluation circuit and interconnecting said first and second partial regions of said evaluation circuit; said bit line and said reference line having respective electrical potentials, said evaluation circuit amplifying a difference between the respective electrical potentials of said bit line and said reference line; and said first and second signal lines having a crossover region within said evaluation circuit, said crossover region forming sections along the bit line direction in said evaluation circuit, a first of said sections containing said first partial region and a second of said sections containing said second partial region of said evaluation circuit, and said sections along the bit line direction having mutually substantially compensating capacitances.