Patent ID: 6182254
Filing Date: 2001-01-30
Classification: G11C

Abstract:
A Rambus ASIC having a high speed testing function comprising:a Rambus ASIC chip constituting a master device, which includes an RAC having at least one I/O pin with a first data input/output speed based on an operating clock;a Rambus DRAM constituting a slave device;a test comparator that drives or compares data at a second speed, which is lower than the first data input/output speed through said at least one I/O pin in the RAC in the Rambus ASIC chip, for testing data input/output operations at the first data input/output speed;an operating clock supply part that supplies the operating clock to the RAC of the Rambus ASIC chip by varying the operating clock in data writing and reading under the control of the frequency of the test comparator; anda test logic part in the Rambus ASIC chip that outputs data judgement signals to the test comparator.