Patent ID: 8692310
Filing Date: 2014-04-08
Classification: H01L

Abstract:
1. A method for forming a NAND string of memory transistors, comprising: forming a plurality of charge trapping layers on a semiconductor substrate; and forming respective gate electrodes on the plurality of charge trapping layers, wherein the memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors, wherein the channel is formed using a gate fringing effect associated with each memory transistor of the adjacent pair of memory transistors, wherein a source select transistor and its neighboring memory transistor are formed close to each other such that a first channel is formed between the source select transistor and the neighboring memory transistor based on a gate fringing effect associated with the source select transistor and the neighboring memory transistor, wherein the first channel serves as source and drain regions, and wherein a width between the adjacent pair of memory transistors and a width between the neighboring memory transistor and the source select transistor are equal.