Patent ID: 7385424
Filing Date: 2008-06-10
Classification: G11C,H03K

Abstract:
1. A high-speed differential receiver used between a high voltage domain and a low voltage domain; said high-speed differential receiver comprising: a common mode differential amplifier receiving differential input signals and providing amplified differential output signals; a differential level shifter coupled to said common mode differential amplifier; said common mode differential amplifier and differential level shifter operating at the high voltage domain; said differential level shifter including a first pair of first P-channel field effect transistors (PFETs) connected to the high voltage domain supply; each said first PFET of said first pair of PFETs of said differential level shifter being connected to the common mode differential amplifier and respectively receiving a gate input of a respective one of said amplified differential output signals from the common mode differential amplifier, each said first PFET being series connected with a respective first N-channel field effect transistor (NFET) between the high voltage domain supply and ground, a gate of each said first NFET is cross connected to a common drain connection of the other series connected first PFET and first NFET, a pair of N-channel field effect transistors (NFETs) connected in parallel with each said first NFET, and a respective common drain connection of each said first PFET and said respective first NFET respectively providing a drain output of a respective voltage level shifted differential signals; a biased differential amplifier operating at the low voltage domain and coupled to said differential level shifter receiving said voltage level shifted differential signals and an enable signal for providing a biased output signal; said biased differential amplifier including a second pair of second P-channel field effect transistors (PFETs) connected to the low voltage domain supply; each said second PFET of said second pair of PFETs having a gate input enabled responsive to said enable signal and each said second PFET of said second pair of PFETs being series connected with a respective second N-channel field effect transistor (NFET) between the low voltage domain supply and a voltage bias node; said biased differential amplifier including a series-connected pair of third N-channel field effect transistors (NFETs) connected in series between said voltage bias node and ground; and a transistor stack including a series-connected third P-channel field effect transistor (PFET) and a fourth N-channel field effect transistors (NFET) and a parallel-connected pair of a fifth N-channel field effect transistor (NFET) and a sixth N-channel field effect transistor (NFET) connected in series between the low voltage domain supply and ground; said third P-channel field effect transistor (PFET) and said sixth N-channel field effect transistor (NFET) respectively receiving a gate input of an inverted enable siginal; and said third N-channel field effect transistors (NFETs) respectively receiving a gate input of a source and drain connection of the series-connected third P-channel field effect transistor (PFET) and fourth N-channel field effect transistors (NFET) and of a source and drain connection of the series-connected fourth N-channel field effect transistors (NFET) and said fifth N-channel field effect transistors (NFET); said respective second NFET having a gate connected to said respective common drain connection of each said first PFET and said respective first NFET of said differential level shifter; and a common drain connection of one of said second PFET and said respective second NFET of said biased differential amplifier providing the biased output signal responsive to said enable signal.