Patent ID: 8165255
Filing Date: 2012-04-24
Classification: H03H

Abstract:
1. A discrete time signal resampling circuit, comprising: a data sample processing module adapted to remove selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling, the selected samples being separated by a inter-removal sample count, the data sample processing module storing a filter length number of samples that is less than the inter-removal sample count; a coefficient generator, adapted to generate a sequential plurality of finite impulse response filter coefficient sets, each coefficient set being associated with a respective distinct portion of a plurality of discrete time signal samples consisting of the filter length number of samples, the sequential plurality of finite impulse response filter coefficient sets including at least a first group of coefficient sets that are associated with discrete time signal samples occurring between the selected samples, the first group of coefficient sets defining a sequence of low pass filters, each low pass filter having an increasing group delay relative to an immediately preceding low pass filter; a coefficient multiplier adapted to sequentially multiply each coefficient set by its associated respective distinct portion of the plurality of discrete time signal samples and to produce therefrom a product vector; and an adder adapted to produce a resampled output sample comprising a sum of elements of the product vector, wherein the data sample processing module operates at a first data clock rate corresponding to a sample rate of the discrete time signal samples, wherein the coefficient generator, the coefficient multiplier and the adder operate at a second data clock rate corresponding to a resampled output data clock rate that is fractionally related to the first data clock rate, and wherein a value of the increasing group delay is equal to a difference of the first data clock rate and the second data clock rate divided by the first data clock rate.