Patent ID: 9054207
Filing Date: 2015-06-09
Classification: G11C,H01L

Abstract:
1. A non-volatile storage transistor, comprising: a gate electrode formed above a semiconductor region and separated therefrom by a gate insulation layer; a source region formed in said semiconductor region and connecting to a channel region at a source side of said storage transistor; a drain region formed in said semiconductor region and connecting to said channel region at a drain side of said storage transistor; a floating sidewall spacer formed adjacent a sidewall of said gate electrode at least at said drain side of said storage transistor, said floating sidewall spacer being formed above a portion of said channel region and above a portion of said drain region; a first dielectric layer formed so as to separate said floating sidewall spacer from said gate electrode, wherein said first dielectric layer is comprised of a high-k dielectric material; and a second dielectric layer formed so as to separate said floating sidewall spacer from said channel region and said drain region.