Patent ID: 7203103
Filing Date: 2007-04-10
Classification: G11C

Abstract:
1. A ferroelectric memory device comprising: a voltage source for generating a predetermined voltage; a first bit line and a second bit line; a first ferroelectric capacitor having one end electrically connected to the first bit line; a first resistor having a first resistance value, provided between the first bit line and the voltage source; a first switch provided between the voltage source and the first bit line, for switching as to whether the predetermined voltage is to be supplied for a predetermined period to the first bit line through the first resistor; a second ferroelectric capacitor having one end electrically connected to the second bit line; a second resistor having a second resistance value different from the first resistance value, provided between the second bit line and the voltage source; a second switch provided between the voltage source and the second bit line, for switching as to whether the predetermined voltage is to be supplied for a predetermined period to the second bit line through the second resistor; and a sense amplifier that judges data written in the first ferroelectric capacitor by comparing a potential on the first bit line with a potential on the second bit line when the predetermined voltage is simultaneously supplied to both the first bit line and the second bit line.