Patent ID: 8072020
Filing Date: 2011-12-06
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a plurality of serially-connected memory cell transistors that have a storage section; a first select transistor connected to one end of said serially-connected memory cell transistors; a second select transistor connected to the other end of said serially-connected memory cell transistors; a first impurity diffusion region that is formed in a semiconductor substrate and is disposed on a side of the first select transistor opposite to a side of the serially-connected memory cell transistors; and a second impurity diffusion region that is formed in said semiconductor substrate and is disposed on a side of the second select transistor opposite to a side of the serially-connected memory cell transistors; a first contact formed on the first impurity diffusion region and extending in a perpendicular direction with respect to the semiconductor substrate; and a second contact formed on the second impurity diffusion region and extending in a perpendicular direction with respect to the semiconductor substrate, wherein a depth of said first impurity diffusion region from a surface of the semiconductor substrate is formed to be greater than a depth of said second impurity diffusion region from a surface of the semiconductor substrate, and a bottom surface of the first contact is positioned below a surface of the semiconductor substrate.