Patent ID: 6689665
Filing Date: 2004-02-10
Classification: H01L,Y10S

Abstract:
A method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners comprising the steps of:providing a shallow trench isolation (STI) feature included in a semiconductor process surface the STI feature comprising an etched trench formed into a semiconductor substrate extending through a thickness; said thickness comprising a thermally grown first silicon dioxide layer overlying the semiconductor substrate and a metal nitride hardmask layer overlying the first silicon dioxide layer; thermally growing a second silicon dioxide layer to line the etched trench to form a trench liner; filling said etched trench with a silicon dioxide filling material; removing excess silicon dioxide filling material overlying the hardmask layer according to a chemical mechanical polishing (CMP) process to stop on the hardmask layer; removing the hardmask layer according to a wet chemical etching process to leave a thickness portion of the first silicon dioxide layer; and, re-growing the first silicon dioxide layer to at least an originally formed first silicon dioxide layer thickness.