Patent ID: 6459592
Filing Date: 2002-10-01
Classification: H01L,H05K,Y02P

Abstract:
A VLSI package assembly, comprising:A PKG substrate carrying on one major surface thereof an IC chip, and having on another surface thereof a plurality of first connection pads arranged in a two-dimensional format; a motherboard having a plurality of second connection pads two-dimensionally arranged on one surface thereof confronting said other surface of the PKG structure, each of the first connection pads having a smaller exposed area for soldering than that of the second connection pads, the first pads treated with an electrolytic plating process and the second pads treated with a non-electrolytic plating process; and a plurality of solder bumps, the pluralities of first and second connection pads and the plurality of solder bumps together defining an electric path assembly including respective opposing ones of the pluralities of first and second connection pads and respective ones of the solder bumps electrically connecting between the opposing first and second connection pads, wherein said electric path assembly includes by itself an anti-stress structure with a high durability against stresses occurring therein.