Patent ID: 6833744
Filing Date: 2004-12-21
Classification: H03K,H03L

Abstract:
A circuit for correcting a duty factor of a clock signal, comprising:a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal; a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180Â° and 360Â° clock generating control signals; wherein the control signal generating part comprises a synchronized signal providing part for synchronizing a shifted clock generating reference signal to the input clock signal, a first delay loop for delaying the synchronized clock generating reference signal for a preset time period, to provide as a 180Â° clock generating phase signal, and a second delay loop for delaying the synchronized clock generating reference signal for a preset time period, to provide as a 360Â° clock generating phase signal; and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180Â° and 360Â° clock generating control signals; wherein the clock signal generating part comprises a correction delay for delaying the 360Â° clock generating control signal, a first pulse signal generator for generating a pulse signal in response to the 360Â° clock generating control signal delayed at the correction delay, and a second pulse signal generator for generating a pulse signal in response to the 180Â° clock generating control signal.