Patent ID: 7115935
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. An embedded DRAM and capacitor structure device comprising: trenched capacitors in two twisted trenches through an insulating layer in a memory area of an integrated circuit wherein said two twisted trenches are mirror images of each other and wherein each capacitor in a first of said two twisted trenches is horizontally aligned with a capacitor in a second of said two twisted trenches to form pairs of capacitors wherein said pairs of capacitors are separated from each other horizontally by a first or a second distance wherein said first distance is greater than said second distance; a bit line contact in said memory area through said insulating layer to a bit line wherein said bit line contact lies between said two twisted trenches and in a horizontal line with one capacitor pair wherein said one capacitor pair has said first separation distance and adjacent capacitor pairs have said second separation distance; and first line metal contacts in a logic area of said integrated circuit; wherein said bit line contact and said first line metal contacts are no higher vertically than said trenched capacitors.