Patent ID: 8151087
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. A cache memory including a first bank and a second bank, comprising: a first hash function module for converting a main memory address received from a central processing unit (CPU) into a first index value using a first hash function; a second hash function module for converting the main memory address into a second index value using a second hash function; a first comparator for comparing a tag value of a data block located at the first index value in the first bank with a tag value of the main memory address; and a second comparator for comparing a tag value of a data block located at the second index value in the second bank with the tag value of the main memory address, wherein each of the first and second hash functions is a 2m×m binary matrix, and m is an odd number equal to or more than 5, and wherein the first hash function is constructed by juxtaposing an m×m matrix A=(a