Patent ID: 7239575
Filing Date: 2007-07-03
Classification: G11C

Abstract:
1. A clock generator for generating an output clock signal synchronized with an input clock signal, comprising: a variable delay line having an input at which a buffered clock signal is applied, an output at which a delayed clock signal is provided, and a control node to which a first control signal is applied, the variable delay line configured to generate the delayed clock signal having a delay relative to the buffered clock signal controlled by the first control signal; a model delay line having an input coupled to the output of the variable delay line and further having an output at which a feedback clock signal is provided, the model delay configured to generated the feedback clock signal having a model delay relative to the delayed clock signal; a phase detector having an adjustable delay line having an input coupled to the output of the model delay line, an output at which a delayed feedback signal is provided, and a control node at which a second control signal is applied, the adjustable delay line configured to generate the delayed feedback signal having a delay relative to the feedback signal controlled by the second control signal, the phase detector further having a phase comparison circuit having a first input coupled to the output of the adjustable delay line, a second input at which the buffered clock signal is applied, and first and second output nodes, the phase comparison circuit configured to generate and provide at the first output node a phase signal indicative of the phase difference between the buffered clock signal and the delayed feedback signal, and further configured to generate and provide at the second output node an adjustable delay control signal coupled to the control node of the adjustable delay line; and a delay controller having an input coupled to the output of the phase detector and an output node coupled to the control node of the variable delay line, the delay controller configured to generate the control signal to control the delay of the variable delay line in accordance with the phase signal.