Patent ID: 6051457
Filing Date: 2000-04-18
Classification: H01L,Y10S

Abstract:
A method of fabricating an integrated circuit with an electrostatic discharge protection device comprising the steps of:patterning a first photoresist directly on a P substrate;implanting an N+ buried layer into the P substrate using the first patterned photoresist as an implant mask;patterning a second photoresist on the N+ buried layer;implanting a P+ buried layer in and on a top portion of the N+ buried layer using the second patterned photoresist as an implant mask;growing an N epitaxial layer over the P substrate, the N+ buried layer, and the P+ buried layer;etching the N epitaxial layer to define a first active area over the P+ buried layer and a second active area over the N+ buried layer, the first and second active areas separated by a gate oxide layer;implanting a P area over the P+ buried layer;implanting an N area over the N+ buried layer; anddepositing a cathode over the N area and an anode over the P area.