Patent ID: 6369629
Filing Date: 2002-04-09
Classification: H03K

Abstract:
A flip-flop circuit composed of a master latch and a slave latch and which operates on a data input signal and a clock input signal fed thereto,wherein the master latch comprises: a data input circuit which, when the clock input signal is at a first level, reads the data input signal; a first data holding circuit which, when the clock input signal is at a second level, holds the data read by the data input circuit; and a signal switching circuit which, when the clock input signal is at the first level, outputs a predetermined level and which, when the clock input signal is at the second level, outputs the data held by the first data holding circuit after inverting it, wherein the slave latch comprises: a data output circuit which, when the clock input signal is at the second level, reads an output of the signal switching circuit after inverting it; and a second data holding circuit which, when the clock input signal is at the first level, holds the data read by the data output circuit; wherein the flip-flop circuit uses the clock input signal without submitting it to any delay in the master latch, and wherein a transistor within said slave latch is directly coupled to another transistor within said master latch that is fed with said clock input signal at its gate and which is connected to a fixed voltage point at one of its electrodes other than said gate, wherein the data input circuit and the second data holding circuit share a single circuit including said another transistor.