Patent ID: 6578156
Filing Date: 2003-06-10
Classification: H03K

Abstract:
An output buffer circuit comprising:a signal output line; and a plurality of switching circuits connected to the signal output line at different locations thereof, wherein each of the plurality of switching circuits comprises: a first switching device connected between a power source line and the signal output line; a second switching device connected between the signal output line and a ground line; a first control signal line that turns the first switching device on and off; a second control signal line that turns the second switching device on and off, wherein the first switching device and the second switching device in one of the plurality of switching circuits have a minimum current drivability, and the first switching device and the second switching device in another of the plurality of switching circuits have a maximum current drivability; and a predriver circuit that supplies a control signal to the first control signal line and the second control signal line of each of the plurality of switching circuits based on an input signal and a clock signal, wherein, when the potential on the output signal line is turned to a high level, the predriver circuit turns on the first switching device in the switching circuit having the minimum current drivability, and then turns on the first switching device in the other switching circuits in the order from one having a lower current drivability, and wherein, when the potential on the output signal line is turned to a low level, the predriver circuit turns on the second switching device in the switching circuit having the minimum current drivability, and then turns on the second switching device in the other switching circuits in the order from one having a lower current drivability, wherein the plurality of switching devices are successively turned on at time intervals, wherein at least the last one of the time intervals is shorter than the first one of the time intervals.