Patent ID: 9064714
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a main surface; a first semiconductor layer of a first conductivity type formed to cover said main surface of said semiconductor substrate; a second semiconductor layer of a second conductivity type formed to reach a first depth from a surface of said first semiconductor layer; a first region disposed in said first semiconductor layer, a first circuit driven with a first voltage being formed in said first region; a second region disposed in said second semiconductor layer, a second circuit driven with a second voltage higher than said first voltage being formed in said second region; and an isolation region of the second conductivity type formed with a width in said second semiconductor layer along said second region to surround said second region, said isolation region electrically isolating said first region and said second region, said second region including a linear pattern and a corner pattern as a layout pattern, said isolation region including: a third semiconductor layer having a first impurity of the second conductivity type, said third semiconductor layer being located, with said width and a first thickness, along said linear pattern, and joins to said first semiconductor layer; and a fourth semiconductor layer having a second impurity of the second conductivity type, said fourth semiconductor layer being located, with said width and a second thickness, along said corner pattern, and joins to said first semiconductor layer, when an area of a junction surface where said fourth semiconductor layer and said first semiconductor layer join to each other is referred to as an area A, and a region having said width and said first thickness in said third semiconductor layer, in which an area of a junction surface where said third semiconductor layer and said first semiconductor layer join to each other corresponds to the same area as said area A, is referred to as a region A, a concentration of said first impurity and said first thickness of said third semiconductor layer, and a concentration of said second impurity and said second thickness of said fourth semiconductor layer are set in such a manner that the number of atoms of said second impurity in said fourth semiconductor layer, and the number of atoms of said first impurity in said region A of said third semiconductor layer become the same.