Patent ID: 7546410
Filing Date: 2009-06-09
Classification: G06F

Abstract:
1. A self timed memory chip having an apportionable data bus comprising: an array having an access timing; a self time unit configured to dynamically determine the access timing and to control a read access or a write access to the array according to the dynamic determination of the access timing, the self time unit further comprising: a shift register comprising a plurality of bits coupled to an output of the ring oscillator, and configured to shift responsive to the output of the ring oscillator; a decode coupled to one or more bits in the plurality of bits in the shift register, an output of the decode used to control the read access or the write access of the array; a data bus having “N bits”, the data bus consisting of: wherein a value of “M” is programmable; wherein a clock frequency of the data bus is independent of the access timing of the array; and wherein the self timed memory chip is a dynamic random access memory (DRAM) chip.