Patent ID: 6313018
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A process for fabricating a semiconductor structure having an interconnect, comprising the steps of:(a) providing a semiconductor substrate;(b) forming a semiconductor device having an interconnect area on a surface of the substrate;(c) forming an etch stop layer of a material selected from the group consisting of silicon nitride, silicon oxynitride and silicon oxime over the surface of the substrate and the device, the etch stop layer having a silicon content of approximately 40% to 50% by weight;(d) forming an insulator layer over the etch stop layer;(e) etching a first hole through the insulator layer to the etch stop layer in alignment with the interconnect area;(f) etching a second hole through the etch stop layer to the interconnect area; and(g) filling the first and second holes with an electrically conductive material which ohmically contacts the interconnect area to form the interconnect.