Patent ID: 9190265
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A method of forming a multi-level integrated circuit, comprising: forming circuit components onto a first substrate, the circuit components of the first substrate comprising a metal-containing conductive interconnect; forming an electrical insulator material over the circuit components of the first substrate; processing a second substrate to comprise first conductivity type semiconductor material having a dopant in only a portion thereof; activating the dopant to form a doped region that contains the activated dopant, the doped region exhibiting second conductivity type opposite the first conductivity type and forming a junction with a portion of the semiconductor material still exhibiting the first conductivity type; after activating the dopant, bonding the second substrate to the insulator material of the first substrate; removing at least some material of the second substrate where bonded to the insulator material to expose at least some of the underlying insulator material; and after the removing, forming a plurality of cross-point memory cells within the second substrate, the forming of the plurality of cross-point memory cells comprising patterning through the doped region of the second substrate to form a plurality of conductive lines of the cross-point memory cells, the plurality of conductive lines comprising the doped region exhibiting the second conductivity type.