Patent ID: 6130168
Filing Date: 2000-10-10
Classification: H01L,Y10S

Abstract:
The method of forming gate oxide layers having different thicknesses in the manufacture of an integrated circuit memory device comprising:providing a semiconductor substrate wherein active areas of said substrate are isolated from other active areas by shallow trench isolation regions and wherein there is at least one memory cell area, at least one low voltage area and at least one high voltage area;forming a tunneling oxide layer and a first polysilicon layer in said memory cell area;depositing an ONO layer overlying said first polysilicon layer and on the surface of said semiconductor substrate in said low voltage and said high voltage areas wherein said ONO layer comprises a top oxide layer, a middle nitride layer, and a bottom oxide layer;removing said ONO layer in said high voltage area;thereafter oxidizing said semiconductor substrate in said high voltage area to form a thick gate oxide layer wherein said ONO layer prevents oxidation in said low voltage area;thereafter removing said ONO layer in said low voltage area wherein said removing comprises:dry etching away said top oxide layer;thereafter dry etching away said middle nitride layer with an etch stop at said bottom oxide layer; andthereafter wet etching away said bottom oxide layer wherein said wet etching does not etch into said shallow trench isolation regions;thereafter oxidizing said semiconductor substrate in said low voltage area to form a thin gate oxide layer thinner than said thick gate oxide layer; andcompleting fabrication of said integrated circuit device having gate oxide layers having different thicknesses.