Patent ID: 8578199
Filing Date: 2013-11-05
Classification: G06F,H03K

Abstract:
1. A clock circuit, consisting of: an oscillating crystal circuit, providing an a reference clock; a buffer, coupled to the oscillating crystal circuit, delaying the reference clock; a timing circuit, coupled to the buffer, and converting the reference clock into time information; a bias unit; a clock detector, coupled to the bias unit and the buffer, configured to detect whether or not an interruption of the reference clock occurs, wherein when the interruption of the reference clock occurs, a clock interruption signal is issued as a reference whether or not to reset the timing circuit; and a storage device, coupled between the timing circuit and the clock detector, storing the clock interruption signal; wherein the clock detector is powered by the bias unit, and the clock detector consists of: a capacitor, coupled between the bias unit and a ground voltage, wherein a connection terminal of the capacitor and the bias unit outputs a detected voltage; a clock edge detector, detecting the reference clock and determining whether or not at a clock edge region; a switching device, coupled between the bias unit and the ground voltage and coupled with the capacitor in parallel, wherein the switching unit is conducted and the capacitor is discharged via the switching device when at the clock edge region of the reference clock, wherein the switching unit is open and the capacitor is charged due to the switching device when not at the clock edge region of the reference clock; and a first circuit, receiving the detected voltage, wherein the first circuit is a comparator or a trigger circuit, and when the detected voltage is greater than a reference voltage or a trigger voltage, the clock interruption signal is issued to serve as a reset signal of the timing circuit.