Patent ID: 6936929
Filing Date: 2005-08-30
Classification: H01L

Abstract:
1. A stacked, multi-chip package comprising: a substantially planar lead frame including a plurality of contacts; a mother die having a plurality of bond pads and a first plurality of I/O pads; a daughter die having a second plurality of I/O pads, the daughter die being flip chip mounted on the mother die such that the first plurality of I/O pads on the mother die are in electrical contact with the second plurality of I/O pads on the daughter die; a plurality of bonding wires that electrically connect at least some of the bond pads to corresponding contacts; and an encapsulant that covers at least portions of the bonding wires, the mother die, the daughter die and the contacts, wherein a bottom surface of the encapsulant is substantially coplanar with the bottom surfaces of the contacts and the package such that the contacts are exposed on a bottom surface of the package with encapsulant material between adjacent contacts; and wherein a back surface of at least one of the mother and daughter dice is exposed; and whereby a stacked, multi-chip quad flat pack, no leads package is formed.