Patent ID: 8679981
Filing Date: 2014-03-25
Classification: G03F,H01L

Abstract:
1. A method of semiconductor device fabrication for patterning a target layout of line features and large features comprising: depositing a first layer of a first material and patterning the first layer to form a first pattern on a substrate, wherein the first pattern comprises first array of line features; depositing a spacer material over the first pattern on the substrate; etching the spacer material such that spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the first pattern from the substrate; selectively removing the spacer material, such that the spacer material that remains forms a spacer material pattern comprising the line features of the target layout; and depositing a second layer of a second material over the spacer material pattern and patterning the second layer to form a second pattern, wherein the second pattern is different from the first pattern and comprises the larger features of the target layout.