Patent ID: 6359804
Filing Date: 2002-03-19
Classification: H01L,Y10S

Abstract:
A static semiconductor memory device, comprising:a pair of access transistors; a word line connected to a shared gate electrode of said pair of access transistors; a first transistor region provided with a pair of load transistors connected to said access transistors; a second transistor region provided with said pair of access transistors and a pair of driver transistors connected to said access transistors and said load transistors, said second transistor region arranged adjacent to said first transistor region and extending therefrom in a direction parallel to said word line; a bit line pair extending orthogonally to said word line, formed of an interconnection containing metal, and connected to said access transistors; a power supply line extending orthogonally to said word line, formed of an interconnection containing said metal, and connected to said load transistors.