Patent ID: 8190652
Filing Date: 2012-05-29
Classification: G06F

Abstract:
1. An apparatus comprising: a processor to execute code; a first search logic to search for a first entry for a first page containing a first code region in a first data structure to determine whether a first indicator in the first entry is set to a first value; an adder logic to add the first entry to the first data structure, in response to failing to find the first entry in the first data structure; and a second search logic to search for a second entry for the first code region in a second data structure, in response to determining that the first indicator is set to the first value, wherein the apparatus is configured to remove one or more dynamically optimized code regions corresponding to the first page from a code cache in response to determining that the first page has been modified, wherein the apparatus is configured to set the first indicator to a second value, and wherein the first value is to indicate whether code on a page is not coherent with one or more corresponding dynamically optimized code regions in the code cache.