Patent ID: 8324097
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming an isolation structure that touches a plurality of first metal structures and a plurality of second metal structures; wherein an adjacent pair of first metal structures are spaced apart by a first minimum distance, an adjacent pair of second metal structures are spaced apart by a second minimum distance, the second minimum distance being greater than the first minimum distance; simultaneously forming a plurality of first isolation openings and a plurality of second isolation openings in the isolation structure, the plurality of first isolation openings exposing the plurality of second isolation openings exposing the plurality of second metal structures; forming a seed layer that touches the isolation structure, the plurality of first metal structures, and the plurality of second metal structures; and forming a first plating mold that touches the seed layer, the first plating mold having a plurality of first mold openings that expose the seed layer that lies directly over the plurality of first metal structures, the first plating mold covering the seed layer that lies directly over the plurality of second metal structures; forming a plurality of first plated structures in the plurality of first mold openings in the first plating mold, wherein the plurality of first plated structures are substantially only copper; removing the first plating mold; and forming a second plating mold that touches the seed layer, the second plating mold having a plurality of second mold openings that expose the seed layer that lies directly over the plurality of second metal structures, the second plating mold covering the plurality of first plated structures.