Patent ID: 7338862
Filing Date: 2008-03-04
Classification: H01L

Abstract:
1. A method of fabricating a single transistor floating body dynamic random access memory (DRAM) cell, comprising: forming a barrier layer on a semiconductor substrate; forming a body layer on the barrier layer; forming an isolation layer defining a floating body region within the body layer, the isolation layer being in contact with the barrier layer and the floating body region and having a bottom surface positioned at a level relative to the semiconductor substrate no higher than a top surface of the barrier layer; forming a recess region in the floating body region; forming a gate electrode in the recess region; and implanting impurity ions of a first conductivity type into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.