Patent ID: 6699784
Filing Date: 2004-03-02
Classification: C23C,H01L

Abstract:
A method of forming an interconnect structure on a substrate surface, comprising:depositing a low k dielectric layer (k<3.5) comprising a polyimide, a polytetrafluoroethytene, a parylene, a polysilsesquioxane, a fluorinated poly(aryl ether), a fluorinated amorphous carbon, a silicon oxycarbide having a hardness of 1 giga Pascal or less, or a silicon carbide; depositing a low k silicon oxycarbide hard mask (k<3.5) having a hardness of greater than 1 giga Pascal over the low k dielectric layer; patterning the low k silicon oxycarbide hard mask with a horizontal interconnect pattern; and transferring the horizontal interconnect pattern into the low k dielectric layer to form cavities corresponding to the horizontal interconnect pattern.