Patent ID: 6480178
Filing Date: 2002-11-12
Classification: G09G,H03F

Abstract:
An amplifier circuit comprising:a plurality of amplification stages cascade-connected between a signal input terminal to which an input signal is supplied and a signal output terminal to which a capacitive load is connected and including at least an input amplification stage and an output amplification stage having an output terminal; and a resistor circuit including at least a resistor inserted between the output terminal of said output amplification stage and said signal output terminal, for introducing a zero into an open loop frequency characteristic to compensate a phase on said output amplification stage; wherein, said input amplification stage includes a positive-side amplifier circuit and a negative-side amplifier circuit to which a first and a second input signal changing to the positive side and negative side with respect to a specific common voltage are inputted, said positive-side amplifier circuit includes a first differential transistor pair to which said first input signal is inputted, a first current source configured to supply a tail current to the first differential transistor pair, a first current mirror circuit whose current input terminal and current output terminal are connected to the two output terminals of said first differential transistor pair, and a first switch provided between the two output terminals of said first differential transistor pair, said negative-side amplifier circuit includes a second differential transistor pair to which said second input signal is inputted, a second current source configured to supply a tail current to the second differential transistor pair, a second current mirror circuit whose current input terminal and current output terminal are connected to the two output terminals of said second differential transistor pair, and a second switch provided between the two output terminals of said second differential transistor pair, said first switch being brought into the off state and said second switch being brought into the on state when said first input signal is inputted to said positive-side amplifier circuit, and said first switch being brought into the on state and said second switch being brought into the off state when said second input signal is inputted to said negative-side amplifier circuit, and said output amplification stage includes a complementary transistor pair whose drains or collectors are connected to the output terminal of the output amplification stage, the gate or base of one of the complementary transistor pair being connected to one output terminal of said positive-side amplifier circuit and the gate or base of the other of the complementary transistor pair being connected to one output terminal of said negative-side amplifier circuit.