Patent ID: 7003064
Filing Date: 2006-02-21
Classification: G06F,H03L,H04L

Abstract:
1. A method for aligning clock signals, the method comprising the steps of: a) receiving first and second clock signals by respective first and second logic circuitry, wherein the first and second clock signals are substantially synchronized and operations of the first logic circuitry and second logic circuitry are clocked by the respective first and second clock signals; b) receiving, by the first logic circuitry, a third clock signal, wherein the third clock signal is derived from the second clock signal; c) repeatedly sampling the third clock signal with the first clock signal, using the first logic circuitry; d) detecting relative phase relations of the first and third clock signals repeatedly by the first logic circuitry; and e) altering the phase of the third clock signal responsive to an accumulation of the phase relation detecting.