Patent ID: 8725983
Filing Date: 2014-05-13
Classification: G06F,G11C

Abstract:
1. A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface configured to communicate with a memory controller, wherein at least one of the plurality of modules is a chunk buffer module comprising: a chunk buffering section including first type memory cells comprising a first portion of a total module address space of the chunk buffer module, the first type memory cells having a first type of memory interface and a first maximum access speed, second type memory cells comprising a second portion of the total module address space of the chunk buffer module, the second type memory cells having a second type of memory interface and a second maximum access speed slower than the first access speed, and a memory control section coupled to the module bus and configured to generate signals compatible with the second type of memory interface in response to memory access signals received at the channel interface from the memory controller, wherein the chunk buffering section is disposed between the channel interface and the memory control section and configured to generate signals compatible with the first type of memory interface in response to the memory access signals received at the channel interface from the memory controller.