Patent ID: 7403444
Filing Date: 2008-07-22
Classification: G11C

Abstract:
1. A memory circuit comprising: address decoder circuitry; and a plurality of row addresses latches coupled to receive respective address signals from the address decoder circuitry, wherein each row address latch is operable to: receive a deactivate-enable signal with a first logical value; receive a first pulse of an active signal; activate a word line of the memory circuit corresponding to the respective address signal in response to receiving the first pulse of the active signal when the deactivate-enable signal has the first logical value; receive the deactivate-enable signal with a second logical value; receive a second pulse of the active signal; and deactivate the word line of the memory circuit corresponding to the respective address signal in response to receiving the second pulse of the active signal when the deactivate-enable signal has the second logical value.