Patent ID: 6483145
Filing Date: 2002-11-19
Classification: H01L

Abstract:
An electrically erasable programmable read only memory (EEPROM) comprising:an integrated circuit substrate; a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer, on the integrated circuit substrate; a sense transistor gate on the tunnel insulating layer and on the gate insulating layer, the sense transistor gate comprising a floating gate on the tunnel insulating layer and on the gate insulating layer, a first interlevel insulating layer on the floating gate opposite the tunnel insulating layer and the gate insulating layer, and a sense gate on the first interlevel insulating layer opposite the floating gate; a select transistor gate on the gate insulating layer and spaced apart from the sense transistor gate, the select transistor gate comprising a first select gate on the gate insulating layer that is spaced apart from the sense transistor gate, a second interlevel insulating layer on the first select gate opposite the gate insulating layer, and a second select gate on the second interlevel insulating layer opposite the first select gate that is spaced apart from the sense gate; a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and extending in the integrated substrate to beneath the select transistor gate, the first doped region having: a first portion that extends from beneath the tunnel insulating layer to outside the sense transistor gate and extends to a first depth in the integrated circuit substrate; and a second portion that extends from the first portion to beneath the select transistor gate, extends to the first depth and is lightly doped relative to the first portion; a second doped region in the integrated circuit substrate beneath the sense transistor gate and spaced apart from the first doped region, the second doped region having: a third portion outside the sense transistor gate and extending to a second depth in the integrated circuit substrate; and a fourth portion extending from the third portion to beneath the sense transistor gate, extending to a third depth in the integrated circuit substrate, deeper than the second depth, and being lightly doped relative to the third portion; and a third doped region in the integrated circuit substrate beneath the select transistor gate and spaced apart from the first doped region, the third doped region having: a fifth portion outside the sense transistor gate and extending to a fourth depth in the integrated circuit substrate; and a sixth portion extending from the sixth portion to beneath the select transistor gate, extending to a fifth depth in the integrated circuit substrate, deeper than the fourth depth, and being lightly doped relative to the fifth portion.