Patent ID: 8874883
Filing Date: 2014-10-28
Classification: G06F

Abstract:
1. A data processing apparatus comprising: processing circuitry for processing data, said processing circuitry configured to operate at a plurality of privilege levels in one of a debug mode and a non-debug mode wherein at different privilege levels said processing circuitry imposes on program instructions different access permissions to at least one of a memory and a set of registers; instruction decoding circuitry, responsive to program instructions, configured to generate control signals for controlling said processing circuitry to perform said data processing; wherein said program instructions comprise a debug privilege-level switching instruction, said instruction decoding circuitry, responsive to said debug privilege-level switching instruction, configured: (i) if said processing circuitry is in said debug mode, to switch said processing circuitry from a current privilege level to a target privilege level while remaining in said debug mode; and (ii) if said processing circuitry is in said non-debug mode, to prevent execution of said debug privilege-level switching instruction regardless of said current privilege level.