Patent ID: 6507068
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A semiconductor device, comprising:a substrate; a gate electrode formed on said substrate; a first side wall insulation film formed on a first side wall of said gate electrode with a first thickness; a second side wall insulation film formed on a second side wall of said gate electrode with a second thickness substantially larger than said first thickness; a first diffusion region formed in said substrate adjacent to said first side wall of said gate electrode; a second diffusion region formed in said substrate adjacent to said s second side wall of said gate electrode; said first diffusion region having a first tip end, defining a boundary of said first diffusion region to said substrate, located under said gate electrode, when viewed perpendicularly to a principal surface of said substrate, with a first overlapping distance as measured from an outer surface of said first side wall insulation film, said second diffusion region having a second tip end, defining a boundary of said second diffusion region to said substrate, located inside said second side wall insulation film of said gate electrode with a second overlapping distance as measured from an outer surface of said second side wall, when viewed perpendicularly to said principal surface of said substrate, wherein said first overlapping distance has a magnitude larger than a magnitude of said second overlapping distance, said second tip end of said second diffusion region being located outside said second side wall of said gate electrode, said first diffusion region including therein a third diffusion region having an increased impurity concentration level over said first diffusion region, said third diffusion region including therein a fourth diffusion region having an increased impurity concentration level over said third diffusion region, said second diffusion region including therein no additional diffusion region.