Patent ID: 6442078
Filing Date: 2002-08-27
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction and a plurality of memory cells; an interface area for transmitting/receiving signals to/from an external device; a memory operation circuit arranged between said interface area and said memory cell array for writing data received from said interface area in said memory cell array and reading data from said memory cell array to output said data to said interface area; an internal data bus arranged in the row direction for transmitting write data output from said memory operation circuit in a write operation and transmitting read data read from said memory cell array to said memory operation circuit in a read operation; and a sense amplifier block including a plurality of sense amplifiers provided in correspondence to said plurality of bit lines respectively for amplifying the potentials of corresponding said bit lines and a plurality of input/output gates provided in correspondence to said plurality of bit lines respectively for electrically connecting/disconnecting corresponding said bit lines to/from said internal data bus, wherein said memory operation circuit includes: a selection circuit selecting a memory cell subjected to said write operation and said read operation on the basis of an address signal received from said interface area, and a data input/output circuit outputting said write data to said internal data bus on the basis of input data received from said interface area in said write operation and outputting output data to said interface area on the basis of said read data received from said internal data bus in said read operation.