Patent ID: 6326821
Filing Date: 2001-12-04
Classification: H03K

Abstract:
An integrated circuit output buffer, comprising:an output driver stage having at least one data input terminal for connection with at least one data terminal and having at least one control bit input terminal for connection with at least one control bit terminal, said output driver stage having at least one output terminal for connection with an output PAD, said output driver stage including a resistor arrangement having a plurality of coarse tuning branches coupled to said at least one data terminal,having a plurality of fine tuning branches coupled to said at least one data terminal, and having an enabled, fixed resistance branch coupled to a reference voltage to provide a fixed base-point resistance value;wherein each of said plurality of coarse tuning branches, each of said plurality of fine tuning branches, and said fixed resistance branch connected in parallel, comprisesat least one resistor, said at least one resistor of a fine tuning branch having a comparatively greater resistance than said at least one resistor of a coarse tuning branch, and said at least one resistor of said fixed resistance branch having a comparatively lesser resistance than said at least one resistor of a fine tuning branch and said at least one resistor of a coarse tuning branch, andat least one transistor operably connected in series to said at least one resistor, said at least one transistor having a gate operably connected to one of said at least one control bit input terminal or said data input terminal.