Patent ID: 6037266
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating a submicron polysilicon gate; comprising the steps of:forming sequentially a gate oxide layer, a polysilicon layer, a hard mask layer composed of silicon oxide, and a bottom anti-reflective coating (BARC) layer over a substrate;forming a resist layer over said bottom anti-reflective coating (BARC) layer; said resist layer defining said polysilicon gate;placing said substrate into a polysilicon high density plasma etcher and performing the following steps:a) in STEP 1, etching said bottom anti-reflective coating (BARC) layer by flowing bromine species gas and oxygen species gas, and applying a first TCP Power and a first Bias power;b) in STEP 2, etching said hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power;c) in STEP 3--stripping said bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power;d) in STEP 4--etching said polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.