Patent ID: 9069043
Filing Date: 2015-06-30
Classification: G01R,H03F,H03H,H03K,H04B,H04L

Abstract:
1. A termination circuit comprising: a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance, wherein a back gate of the pMOS transistor receives a voltage higher than a voltage obtained by subtracting a forward direction voltage to make a p-n junction of the pMOS transistor turn on, from a maximum voltage of the transmission signal.