Patent ID: 6603109
Filing Date: 2003-08-05
Classification: H04N

Abstract:
Circuit for reading charges comprising a capacitive means (C1, C2) with capacitance Ca to store charges and means of reading a voltage sampled at the terminals of the capacitive means, characterized in that the capacitive means is built up from a first capacitive means (C1) and a second capacitive means (C2) with a capacitance Cb less than Ca, comprising means (COMP) of comparing the voltage read at the terminals of the capacitive means with a threshold value (Vthreshold), means of controlling the transfer of charges stored in the first capacitive means (C1) to the second capacitive means (C2) with a capacitance Cb less than Ca when the voltage read at the terminals of the capacitive means exceeds the threshold value (Vthreshold) and means of reading a voltage sampled at the terminals of the second capacitive means.