Patent ID: 6822495
Filing Date: 2004-11-23
Classification: H03K

Abstract:
A flip-flop circuit for reducing the current spike, comprising:an input for receiving first data and second data, said first data being received and stored within said flip-flop circuit prior to said input receiving said second data, said first data being isolated from said second data, said input being controlled by a first clock signal; an output for transmitting said first data after said input receives said second data, said output being controlled by a second clock signal, said first and second clock signals having the same frequency and substantially the same phase, wherein the arrival time of first and second clock signals at said flip-flop are skewed; a first clock input comprising two p-type field effect transistors connected together, wherein the first clock input receives said first clock signal; a second clock input comprising two n-type field effect transistors connected together, wherein the second clock input receives said second clock signal, wherein the first one of said two p-type field effect transistors is connected in series with a first one of said two n-type field effect transistors; and an additional n-type field effect transistor connected in series with said first p-type field effect transistor and said n-type transistor, said additional n-type effect transistor being controlled by said first clock signal.