Patent ID: 7633505
Filing Date: 2009-12-15
Classification: G06T

Abstract:
1. A multi-chip graphics system having two graphics processors manufactured with a similar graphics pipeline architecture, comprising: a central processing unit; a first graphics processing unit (GPU) chip having a first set of graphics stages having a plurality of different types of stages including a first command module stage, a first version of a processing stage type having a first group of parallel processing units, a first memory interface, and a first GPU-to-GPU interlink interface; a second graphics processing unit (GPU) chip having a second set of graphics stages having a plurality of different types of stages including a second command module stage, a second version of a processing stage type having a second group of parallel processing units, a second memory interface, and a second GPU-to-GPU interlink interface; the system including a single frame buffer memory coupled to said first memory interface with said second memory interface being inoperative during a normal mode; the first GPU chip and the second GPU chip packaged with a high speed interlink between said first GPU-to-GPU interlink interface to said second GPU-to-GPU interlink interface to couple said first version of the processing stage type having a first group of parallel processing units to the second version of the processing stage type having a second group of parallel processing units; said GPU communicatively coupled to said first GPU chip with command strings generated by said GPU being received and processed by said first command module stage with said second command module stage being inoperative during the normal mode; said first GPU chip acting as a master to said second GPU chip with said system distributing a processing workload in parallel amongst a set of parallel processing units in both said first group of parallel processing units in said first GPU chip and the second group of parallel processing units in said second GPU chip; and the first GPU chip and the second GPU chip being perceived as a single entity by driver software executing on said GPU.