Patent ID: 7542341
Filing Date: 2009-06-02
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a first latch configured to store data; a nonvolatile memory cell coupled to the first latch and including two MIS transistors to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors selected in response to the data stored in the first latch; a second latch coupled to the nonvolatile memory cell and configured to store data obtained by sensing a difference in the transistor characteristics between the two MIS transistors of the nonvolatile memory cell; a logic circuit configured to produce a signal indicative of comparison between the data stored in the first latch and the data stored in the second latch; and a control circuit configured to repeat a store operation for storing data in the nonvolatile memory cell, a recall operation for storing data in the second latch, and a verify operation for producing the signal indicative of comparison until the signal indicates that the data stored in the first latch and the data stored in the second latch are the same.