Patent ID: 8723226
Filing Date: 2014-05-13
Classification: H01L

Abstract:
1. A transistor comprising: a substrate having a top surface; a layered structure having a top surface, and including a buffer layer that touches the top surface of the substrate, a channel layer that touches the buffer layer, and a barrier layer that touches the channel layer, the barrier layer including a first group III-N material; wherein the barrier layer that touches the channel layer forms a two-dimensional electron gas (2DEG) that lies at a top of the channel layer; a metal source that touches a first region of the barrier layer, the metal source being electrically connected to the channel layer; a metal drain that touches the a second region of the barrier layer, the metal drain being electrically connected to the channel layer, and horizontally spaced apart from the metal source; an undoped GaN spacer structure having a top surface, and touching the top surface of the layered structure, the spacer structure is in between and horizontally spaced apart from both the metal source and the metal drain, the undoped GaN is a second group III-N material that is different from the first group III-N material; a reverse polarized structure having a top surface, touching the top surface and is coextensive with the spacer structure, the reversed polarized structure including a third group III-N material that is different from the second group III-N material; a metal gate that touches the top surface and is coextensive with the reverse polarized structure; and a passivation layer that touches and lies over the barrier layer in the space between the spacer structure and the metal source and drain, the spacer structure, the reverse polarized structure, and the metal gate, the passivation layer having an opening that exposes a region of the metal gate, an opening that exposes the metal source, and an opening that exposes the metal drain.