Patent ID: 7276944
Filing Date: 2007-10-02
Classification: H03L

Abstract:
1. A clock generation circuit which receives a reference clock as an input and spreads a spectrum of an output clock according to a modulation signal, the clock generation circuit comprising: a divider circuit for receiving either the reference clock or the output clock as a first clock, dividing the first clock, and outputting the first clock, which has been divided, as a divided first clock; a first delay circuit for generating a plurality of delay divided first clocks having different phases, for the divided first clock; a selector circuit for selectively outputting, in response to the modulation signal, one of the plurality of delay divided first clocks according to timing of an edge of the first clock present during time other than a period which is from an edge of the divided first clock to an edge of the delay divided first clock of which delay time is maximum; and a phase comparator for making a comparison between a phase of the one of the reference clock and the output clock not received by the divider circuit as the first clock and a phase of the delay divided first clock selected by the selector circuit and outputting a signal according to a result of the comparison.