Patent ID: 6144586
Filing Date: 2000-11-07
Classification: G11C,H01L,Y10S

Abstract:
A method of erasing a nonvolatile memory cell in a chip, said cell comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, further referred to as the floating-gate channel, a control gate extending over another portion of the channel, further referred to as the control-gate channel, and a program gate capacitively coupled through a dielectric layer to said floating gate, said method comprising the steps of:applying a first negative voltage to said program gate;applying a third negative voltage to said control gate thereby establishing an electric field between said control gate and said substrate;said first and said third negative voltage coupling a second negative voltage to said floating gate;applying a fourth voltage equal or higher than the supply voltage of said chip to said drain region; andapplying a fifth negative voltage to the substrate, said negative voltage being large enough to reduce the electric field between the control gate and the substrate and to couple a sixth negative voltage to the floating gate.