Patent ID: 6795348
Filing Date: 2004-09-21
Classification: G11C,H01L

Abstract:
A method of erasing a non-volatile memory cell comprising a control gate, a floating gate, a source, a drain and a substrate, the method comprising:supplying a negative voltage pulse to the control gate relative to a common voltage for an erase period; supplying a positive voltage pulse to the source relative to the common voltage for a second period that is shorter in duration than the erase period; and discharging the positive voltage pulse at the end of the second period, wherein discharging the positive voltage pulse at the end of the second period effectively increases the magnitude of the negative voltage pulse; and wherein the method further comprises adjusting the length of time for the negative and positive voltage pulses to obtain a relative contribution of source erase and channel erase to achieve a desired balance between data retention and erase speed.