Patent ID: 6411135
Filing Date: 2002-06-25
Classification: G06F

Abstract:
A clock signal switching circuit receiving at least two clock signals having a phase difference between them, and an original signal for switching between the clock signals, and generating an output signal by selecting one of them, comprising:a detection circuit receiving the original signal, the detection circuit forming a detection signal when a transition between the first and the second logic level of the original signal is detected; a delay circuit receiving the original signal and the detection signal, the original signal passes through the delay circuit when the original signal maintains its logic level, and the delay circuit outputting and delaying a selection signal when the detection circuit receives the detection signal; a first selector receiving the clock signals, selecting one of the clock signals according to the logic level of the selection signal, and outputting a first selected signal; a second selector receiving a first control signal and a second control signal, selecting one of the control signals according to the logic level of the selection signal, and outputting a second selected signal, the logic level of the first control signal changing in response to one of the clock signals and the detection signal, and the logic level of the second control signal changing in response to the other clock signal and the detection signal; and a gate circuit receiving the first and second selected signals, generating the output signal; wherein the logic level of the selection signal is changed by the delay circuit after the logic level of both of the first and second control signals has changed.