Patent ID: 6154393
Filing Date: 2000-11-28
Classification: G11C

Abstract:
A semiconductor memory device comprising:memory cells for storing data;a first data storage circuit having a master latch circuit only;a second data storage circuit having a master latch circuit and a slave latch circuit, the second data storage circuit having a smaller current-drive power than the first data storage circuit;a data bus control circuit for selecting connection between the memory cells and the first data storage circuit and connection between the memory cells and the second data storage circuit, in accordance with prescribed rules, thereby to first output one of two data items read simultaneously from the memory cells to the first data storage circuit and to then output the other of the two data items to the second data storage circuit; anda multiplexer circuit for first outputting the data item stored in the first data storage circuit and then outputting the data item stored in the second data storage circuit.