Patent ID: 8219846
Filing Date: 2012-07-10
Classification: G09G,H03L

Abstract:
1. A circuit of an integrated circuit for receiving video data having a plurality of data streams of pixel data and a pixel clock, the circuit comprising: a plurality of data recovery circuits, each data recovery circuit coupled to receive a corresponding data stream of the plurality of data streams and having a phase shifter which shifts the phase of a bit rate sample clock signal with respect to the pixel clock by a fraction of the pixel clock, wherein the bit rate sample clock signal is used to receive the corresponding data stream; wherein each data recovery circuit comprises a word boundary detection circuit coupled to receive data of the corresponding data stream, the word boundary detection circuit enabling a selection of a phase of the bit rate sample clock signal used to receive the corresponding data stream to align to a bit of the corresponding data stream; and a channel deskew circuit coupled to receive an output of each data recovery circuit and the pixel clock.