Patent ID: 8532224
Filing Date: 2013-09-10
Classification: H03D,H04L

Abstract:
1. A signal processing circuit comprising: a frequency up-conversion circuit with an up-conversion input and an up-conversion output, for performing up-conversion with a first local oscillator frequency; a frequency down-conversion circuit with a down conversion input coupled to the up-conversion output and a down-conversion output, for performing down-conversion with a second local oscillator frequency; a digital signal processor, having a processor output, for controlling supply of first signals representing a first complex signal to the up-conversion input, and a processor input coupled to down-conversion output, for receiving second signals representing a second complex signal, the digital signal processor being configured to control a compensation of I/Q mismatch of results of up-conversion and/or down-conversion; the digital signal processor being configured to switch to a calibration mode for selecting a parameter of said compensation, and wherein, in said calibration mode, the digital signal processor is further operative to: