Patent ID: 6388932
Filing Date: 2002-05-14
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell matrix section comprising a plurality of memory cells arranged in a first matrix, wherein when one of said memory cells is selected based on an address signal, a read data signal corresponding to a storage data of said selected memory cell is outputted; a reference memory cell matrix section comprising a plurality of reference memory cells arranged in a second matrix having a structural aspect substantially identical to said memory cell matrix to ensure that a charging speed for said reference memory cell matrix is essentially identical to a corresponding charging speed for said memory cell matrix for each said address, and outputting a reference data signal for said read data signal outputted from said selected memory cell, said output reference data signal resulting from a selected one of said plurality of reference memory cells; and a sensing circuit sensing said storage data based on said read data signal from said memory cell matrix section and said reference data signal from said reference memory cell matrix section, wherein said reference memory cell matrix section makes said selection to correct a timing difference so as to output said reference data signal to said sensing circuit such that, for each said memory cell matrix address, said reference data signal appears substantially synchronous with said data read signal.