Patent ID: 6043696
Filing Date: 2000-03-28
Classification: H03K

Abstract:
A method of storing a logic level using a single clock signal, the method comprising:receiving a first signal and said clock signal;entering a first phase of a first clock cycle;providing a first node signal as a function of a logic level of said first signal;providing a first output signal of a predetermined logic level in response to entering said first phase and independently of said first node signal's logic level;transitioning to a second phase of the first clock cycle from said first phase;causing said first node signal to have a logic level as a function of said first signal's logic level during said transitioning to said second phase;causing said first output signal to have a first stored logic level throughout said second phase, said first stored logic level being a function of said first node signal's logic level during said transitioning to said second phase;receiving a second signal, wherein during said second phase said second signal is equivalent to a complement of said first signal;providing a second node signal as a function of a logic level of said second signal during said first phase;providing a second output signal having said predetermined logic level in response to entering said first phase and independently of said second node signal's logic level;causing said second node signal to have a logic level as a function of said second signal's logic level during said transitioning to said second phase; andcausing said second output signal to have a second stored logic level throughout said second phase, said second stored logic level being a function of said second node signal's logic level during said transitioning to said second phase.