Patent ID: 7187222
Filing Date: 2007-03-06
Classification: H03K

Abstract:
1. A master-slave latch comprising: a data output; a first data input; a second data input; a data select input for selecting one of said first and second data inputs and ignoring the other of said first and second data inputs; a clock input, wherein said master-slave latch is effective for tracking a signal at the selected one of said first and second data inputs when said clock input is at a first logic state, and for transferring to said data output the tracked result when the clock input transitions from said first logic state to a second logic state; wherein said master-slave latch is further effective for maintaining the transferred tracked result at said data output unchanged during a transition at said clock input from said second logic state to said first logic state; a logic block coupled to receive said first data input, second data input, and data select input, said logic block being effective for outputting a predetermined logic state when said first data input is at said predetermined logic state and said data select input selects said first data input or when said second data input is at said predetermined logic state and said data select input selects said second data input, and for outputting a logic complement of said predetermined logic state otherwise, wherein said logic block is enabled when said clock input is at said first logic state and is disabled when said clock input is at said second logic state; a first data latch couple to latch in the output from said logic block when enabled and for ignoring the output from said logic block when disabled, said first data latch being enabled when said clock input is at said second logic state and being disabled when said clock input is at said first logic state; a data transfer device for transferring onto an intermediary output the latched-in contents of said first data latch when said clock input is at said second logic state and for blocking said first data latch from said intermediary output in response to said clock input being at said first logic state; and a second data latch coupled to latch in and transfer to said a data output the data contents of said intermediary output when enabled, and effective for passing through without latching said intermediary output to said data output when disabled, said second latch being enabled when said clock input is at said first logic state and being disabled when said clock input is at said second logic state.