Patent ID: 7434030
Filing Date: 2008-10-07
Classification: G06F

Abstract:
1. A processor system comprising: a processor having an instruction decoder, a general register composed of a plurality of register areas, and at least one arithmetic and logic unit (ALU) and executing a native instruction sequence; and an accelerator for converting a bytecode sequence written in Java-type of programming language to the native instruction sequence for said processor and supplying the native instruction sequence to said instruction decoder, wherein said accelerator includes a bytecode translator for converting the bytecode sequence to the native instruction sequence for said processor and a register status control unit for mapping an operand stack related to the bytecode sequence to any of the register areas of said general register in accordance with the bytecode being converted in said bytecode translator, while a bytecode indicative of an instruction to load a variable on the operand stack is converted in said bytecode translator, the register status control unit judges whether or not the operand stack has been already mapped to one of the register areas, and when the register status control unit judges the operand stack has been already mapped to said one of the register areas the native instruction converted from the bytecode indicative of the instruction to load the variable on the operand stack is not supplied to the instruction decoder.