Patent ID: 7424697
Filing Date: 2008-09-09
Classification: G06F

Abstract:
1. A processor-implemented method for improving an implementation of a design in a programmable logic device (PLD), comprising: determining a topological level of the implementation of the design for each of a plurality of look-up tables (LUTs) of the PLD; determining a subset of the LUTs that are included on a plurality of critical timing paths of the implementation of the design for the PLD; for each topological level of the implementation of the design for the PLD, determining, for each LUT in the subset that is at the topological level, a set of combinations of assigning a plurality of signals for the LUT to a plurality of inputs of the LUT, the signals for the LUT coupled in the implementation of the design to the inputs of the LUT, wherein a current assignment for the LUT of the signals for the LUT to the inputs of the LUT is initialized in correspondence with the implementation of the design for the PLD; for each topological level of the implementation of the design for the PLD, determining, for each LUT in the subset that is at the topological level, whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the timing metric of the current assignment for the LUT, and updating the current assignment for the LUT with the respective assignment in response to improvement of the timing metric for the LUT, wherein an updated assignment results in a modified implementation of the design; and outputting the modified implementation of the design.