Patent ID: 6647541
Filing Date: 2003-11-11
Classification: G06F

Abstract:
A method for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information, comprising:receiving the circuit, the circuit being divided into a plurality of modules coupled together by a plurality of signal lines; defining a first set of timing constraints for the plurality of signal lines; compiling the circuit from a hardware description language specification into a first gate-level implementation using the first set of timing constraints; performing a timing analysis on the first gate-level implementation to determine a first set of slack values for the plurality of signal lines, wherein the first set of slack values specify amounts of extra propagation delay that are available on the plurality of signal lines; defining a second set of timing constraints by allocating the first set of slack values between the plurality of modules based upon wireload information, such that a given slack value associated with a given signal line is allocated between modules coupled to the given signal line in proportion to summed coefficients determined within each module for each gate type and propagation delay combination; wherein wireload information includes gate delays and drive strengths for gates coupled to the plurality of signal lines; and compiling the circuit from the hardware description language specification into a second gate-level implementation using the second set of timing constraints.