Patent ID: 7495965
Filing Date: 2009-02-24
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: first and second cell arrays having bit lines, word lines and electrically rewritable and non-volatile memory cells connected to the bit lines and word lines, main memory cells thereof being used as information cells for storing data while the others are used as reference cells; a sense amplifier disposed to be selectively coupled to a pair of bit lines selected from the first and second cell arrays, an information cell and a reference cell being coupled to the pair of bit lines, respectively; and a row decoder configured to selectively drive word lines in the first and second cell arrays with a voltage switching circuit for transferring a high voltage supplied to a first node to a second node in accordance with input address, wherein the voltage switching circuit comprises: a first E-type PMOS transistor disposed between the first and second nodes, the drain and gate of which are coupled to the second node and a third nodes, respectively; a first D-type NMOS transistor disposed between the first node and the source of the first E-type PMOS transistor, the gate of which is coupled to the second node, the first D-type NMOS transistor having a breakdown voltage higher than that of the first E-type PMOS transistor; a second E-type PMOS transistor disposed between the first and the third node, the drain and gate of which are coupled to the third node and the second node, respectively; a second D-type NMOS transistor disposed between the first node and the source of the second E-type PMOS transistor, the gate of which is coupled to the third node, the second D-type NMOS transistor having a breakdown voltage higher than that of the second E-type PMOS transistor; a first E-type NMOS transistor disposed between the second node and the ground potential node to be on-driven at a non-selected time and off-driven at a selected time; a third D-type NMOS transistor disposed between the second node and the drain of the first E-type NMOS transistor to be on/off-driven simultaneously with the first E-type NMOS transistor, the third D-type NMOS transistor having a breakdown voltage higher than that of the first E-type NMOS transistor; a second E-type NMOS transistor disposed between the third node and the ground potential node to be off-driven at the non-selected time and on-driven at the selected time; and a fourth D-type NMOS transistor disposed between the third node and the drain of the second E-type NMOS transistor to be on/off-driven simultaneously with the second E-type NMOS transistor, the fourth-D-type NMOS transistor having a breakdown voltage higher than that of the second E-type NMOS transistor.