Patent ID: 7564286
Filing Date: 2009-07-21
Classification: H03K,H04L

Abstract:
1. A clock regeneration circuit at which a multi-level input signal of a predetermined period, with at least two signal levels, is inputted and which outputs a clock signal synchronized with the predetermined period, the clock regeneration circuit comprising: a first delay device that delays the multi-level input signal by a duration shorter than a one-bit length of the multi-level input signal and outputs a first multi-level delayed signal; a second delay device that delays the multi-level input signal by a duration of the one-bit length of the multi-level input signal and outputs a second multi-level delayed signal; an adder that adds the second multi-level delayed signal with the multi-level input signal and outputs an added signal; an attenuator that attenuates the added signal and outputs a threshold signal; an exclusive or circuit, at which the multi-level input signal, the first multi-level delayed signal and the threshold signal are inputted, that calculates an exclusive or of and outputs a result of this calculation as an exclusive or signal; and a clock regeneration element that outputs the clock signal with a frequency corresponding to a bit rate of the exclusive or signal.