Patent ID: 8196023
Filing Date: 2012-06-05
Classification: G11B,H03M

Abstract:
1. An encoder which generates a block including a plurality of addresses, a plurality of flag bytes respectively corresponding to the plurality of addresses, and a plurality of sets of first parity symbols respectively corresponding to the plurality of addresses, where the plurality of addresses, the plurality of flag bytes, and the plurality of sets of first parity symbols are interleaved according to a predetermined rule, and which generates a plurality of sets of second parity symbols respectively corresponding to each column of data units included in the block, comprising: an information holding section configured to store the plurality of flag bytes and an initial address; a data generation section configured to generate the plurality of sets of first parity symbols from the initial address and from the plurality of flag bytes; and a parity generation section configured to generate and output the plurality of sets of second parity symbols, for each column of data units included in the block, from the columns of data units included in the block and from input user control data, wherein the data generation section generates the addresses and the sets of first parity symbols, required to generate the columns of data units included in the block, based on the initial address and the plurality of flag bytes, selects necessary portions from the plurality of flag bytes and the addresses and the sets of first parity symbols generated, and outputs the portions to the parity generation section, as the columns of data units included in the block.