Patent ID: 8351264
Filing Date: 2013-01-08
Classification: G11C,H03K

Abstract:
1. An integrated circuit, comprising: a substrate; a base layer formed on the substrate and including discrete devices configured to operate within a first voltage range; at least one cross-point memory array formed above the base layer and electrically coupled with the devices in the base layer, each cross-point memory array including an X-line decoder including a first subset of the discrete devices that operate in the first voltage range; and a Y-line decoder including a second subset of the discrete devices that operate in the first voltage range, wherein the X-line decoder and the Y-line decoder are configured to collectively generate a voltage in the second voltage range and to apply the voltage in the second voltage range across at least one of the plurality of the X-line conductive array lines and at least one of the plurality of the Y-line conductive array lines, whereby no single discrete device is subject to the second voltage range.