Patent ID: 9189282
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. A computing system, comprising: a multi-core processor comprising a plurality of processor cores on a chip; a performance counter circuit configured to collect data relating to execution characteristics of a particular thread to determine hardware capabilities of the processor cores, the performance counter circuit including a register built into the chip to store counts of hardware related activities of the processor cores; and a core controller configured to map the particular thread to the plurality of processor cores based in part on the determined hardware capabilities of the processor cores, wherein the processor cores are heterogeneous cores having differing processing capabilities, including at least one heterogeneous core having a streaming single instruction, multiple data (SIMD) extensions (SSE) accelerator that is different from an accelerator of another one of the heterogeneous cores, wherein when the particular thread includes an SSE demand, which is a larger SSE demand relative to other threads, the core controller is configured to map the particular thread to the at least one heterogeneous core having the SSE accelerator, wherein prior to a migration of the particular thread from a first core of the plurality of processor cores to a second core of the plurality of processor cores, the core controller is configured to pre-fetch cache data from a first cache associated with the first core of the plurality of processor cores, and the core controller is further configured to transfer the pre-fetched cache data to a second cache associated with the second core of the plurality of processor cores, wherein the pre-fetched cache data includes at least hits or evictions, associated with the particular thread; and wherein the core controller is further configured to determine that the particular thread is falling behind a target deadline, the determination that the particular thread is falling behind the target deadline is based on the data collected by the performance counter circuit, and the core controller is configured to map the particular thread to one of the processor cores based on the determination that the particular thread is falling behind the target deadline.