Patent ID: 6344997
Filing Date: 2002-02-05
Classification: G11C,H01L

Abstract:
A method of programming a flash memory cell constructed with buried bit lines used as sources and drains, comprising:a) applying a first positive voltage of high magnitude to a control gate overlaying a row of flash memory cells containing a first cell to be programmed, b) applying a second voltage of moderate magnitude to a first buried bit line laying beside and partially extending under a first floating gate of said first cell, c) applying zero volts to a second buried bit line laying beside and partially extending under a second floating gate of an adjacent second cell and separated from the first buried bit line by a channel length, d) floating all other bit lines overlaid by said control gate, e) connecting semiconductor substrate to zero volts, f) maintaining voltages and connections until a predetermined threshold voltage is reached on said cell being programmed.