Patent ID: 8252633
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A method for forming a semiconductor assembly, comprising: forming a first patterned polymer layer on a first surface of a first heat sink to define an exposed portion of the first surface, said exposed portion of the first surface extending radially inward along the first heat sink surface from the first patterned polymer layer; forming a second patterned polymer layer on a radially outer portion of the first patterned polymer layer, said first and second patterned polymer layers defining a cell for accommodating a power semiconductor die; applying a solder material onto the entire exposed portion of the first heat sink surface and in the cell; positioning a power semiconductor die within the cell on a radially inward portion of the first patterned polymer layer so that the die is thermally coupled to the first heat sink by the solder material; forming a packaging patterned polymer layer on top of a second surface of the first heat sink opposing the first surface and defining an interior surface portion of the first heat sink; and forming a semiconductor package in which the first heat sink, solder material and power semiconductor die are located such that the interior surface portion of the second surface of the first heat sink is not enclosed by the semiconductor package.