Patent ID: 7042768
Filing Date: 2006-05-09
Classification: G11C

Abstract:
1. A method of operating a semiconductor memory device having multi-bit non-volatile memory cells, comprising: activating a first burst read utilizing a first Row Address Strobe signal followed by a first Column Address Strobe signal, the first burst read mode addressing a first plurality of multi-bit non-volatile memory cells; sequentially outputting first multi-bit outputs for each of the first plurality of addressed multi-bit non-volatile cells; activating a second burst read utilizing a second Row Address Strobe signal followed by a second Column Address Strobe signal, the second burst read mode addressing a second plurality of multi-bit non-volatile memory cells; and sequentially outputting second multi-bit outputs for each of the second plurality of addressed multi-bit non-volatile cells, wherein the second mutli-bit outputs are output immediately after the first multi-bit outputs without latency.