Patent ID: 7103621
Filing Date: 2006-09-05
Classification: G06T

Abstract:
1. An apparatus for executing a programmable floating point to integer scaled (FTOIS) instruction, the apparatus comprising: a first input for receiving an FTOIS instruction, the FTOIS instruction including a target data type; a second input for receiving a floating point number, the floating point number including fraction bits and exponent bits; a floating point conversion module having a saturation and result formatting unit, the floating point conversion module calculating a fraction shift amount based on the exponent bits and shifting the fraction bits by the fraction shift amount plus an offset determined by the target data type, the floating point conversion module rounding the shifted fraction bits, the saturation and result formatting unit generating overflow and underflow results depending on the target data type and whether there is an overflow or underflow situation, the saturation and result formatting unit determining a scaled integer number by multiplexing the rounded bits with either overflow or underflow results, said scaled integer number comprising fewer bits than the input floating point number.