Patent ID: 8193625
Filing Date: 2012-06-05
Classification: H01L

Abstract:
1. A stacked-chip packaging structure, comprising: a plurality of chip sets stacked together, each of the chip sets comprising: a heat-dissipation structure comprising an interlayer portion, an extending portion extending from two ends of the interlayer portion, a chip recess formed between the interlayer portion and the extending portion, and a plurality of through holes arranged in the interlayer portion, wherein the through holes pass through the interlayer portion; a chip, disposed on the interlayer portion and disposed in the chip recess, wherein a plurality of bumps are disposed in the through holes of the heat-dissipation structure respectively, and a buffer material is filled in the through holes and filled between the interlayer portion and the bump; and wherein the extending portion of the heat-dissipation structure of each of the chip sets contacts the extending portion of the heat-dissipation structure of the neighboring chip set; a heat sink located at a top portion of the chip sets; a substrate located at a bottom portion of the chip sets; a circuit board located below the substrate; and a plurality of solder balls located between the circuit board and the substrate.