Patent ID: 7286440
Filing Date: 2007-10-23
Classification: G11C

Abstract:
1. A pseudo synchronous random access ram (SRAM) with common pad for address pin and data pin, the pseudo SRAM comprising: an address input unit for receiving an address through a pin and outputting the received address as an internal address; a transition detecting unit for detecting a transition of the internal address; a word line (WL) driving signal generating unit for generating a WL driving signal; and a control signal generating unit, in response to a pin select signal indicating whether a signal input through the pin is an address signal or a data signal, for generating a first control signal for controlling the address input unit to output only an valid address as the internal address, and a second control signal for controlling the WL driving signal generating unit, wherein the WL driving signal generating unit is configured for generating the WL driving signal in response to an output signal of the transition detecting unit and the second control signal.