Patent ID: 7266675
Filing Date: 2007-09-04
Classification: G06F

Abstract:
1. A processor comprising: one or more processing units including flushable queues, said processing units having flush mask inputs for receiving a flush mask directing flush of queue entries identified by said flush mask; and a flush mask register having a flush mask output coupled to said flush mask inputs of said processing units, said flush mask register comprising an array of bit stores populating a matrix of storage locations comprising rows for holding tags identifying said queue entries excepting absent bit stores in each row at a column position equal to a row number of each row, said flush mask register further comprising logic for performing a column reset simultaneously with a write of a first tag to a selected row of said flush mask register, whereby a selected column having a column index equal to said row index of said selected row is set to a value completely reset excepting a bit associated with a particular one of said absent bit stores that is within said selected row and said selected column.