Patent ID: 6766446
Filing Date: 2004-07-20
Classification: G06F

Abstract:
A signal processor to process digital signals in a loop, the signal processor comprising:program memory to store a plurality of digital signal processing instructions; and a core processor including: at least one signal processing unit to execute a digital signal processing instruction within a loop, and a pipe controller coupled to the program memory and the at least one signal processing unit, the pipe controller including a loop buffer to control the execution of digital signal processing instructions within a loop, the pipe controller to read a digital signal processing instruction from the program memory and to store the digital signal processing instruction within the loop buffer, the at least one signal processing unit to execute a digital signal processing instruction within the loop from the loop buffer without re-reading the digital signal processing instruction from the program memory during execution of the loop, wherein the loop buffer comprises a plurality of registers coupled in series to store digital signal processing instructions, the plurality of registers including a fist register and a last register, and wherein the number of digital signal processing instructions within the loop selects the last register in the series of registers having an output selectively coupled to an input of the first register.