Patent ID: 9159286
Filing Date: 2015-10-13
Classification: G09G

Abstract:
1. A display panel comprising: a plurality of gate bus lines; a plurality of source bus lines; first transistors each of which is provided in a vicinity of an intersection of a gate bus line with a source bus line and having a gate connected to the gate bus line; pixel electrodes each connected to a source bus line via a first transistor; first signal supplying means connected to respective first ends of the plurality of gate bus lines and supplying, to at least one of the plurality of gate bus lines, a first conduction signal for bringing the first transistors into conduction; second transistors provided for the plurality of respective gate bus lines and each having (i) a drain connected to a second end of a corresponding one of the plurality of gate bus lines and (ii) a gate connected to a common control line; a potential supply line connected in parallel and common to the respective second ends of the plurality of gate bus lines via the second transistors; potential supplying means for supplying to the potential supply line a potential for maintaining the first transistors in a non-conductive state; and second signal supplying means for, immediately after the first signal supplying means ends the supply of the first conduction signal, supplying to the control line a second conduction signal for bringing the second transistors into conduction, the first conduction signal being a pulse signal having (i) a high potential during a hi hg level period and (ii) a low potential du in a remaining period, the second conduction signal being a periodic pulse signal that (i) rises from a low level to a high level in synchronization with a timing of a fall of the first conduction signal and then (ii) falls after a high-level period has elapsed.