Patent ID: 6333889
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory blocks divided into first and second sub arrays along a column direction, each memory block including a plurality of memory cells arranged in rows and columns;a plurality of sense amplifier circuits provided corresponding to columns in said plurality of memory blocks for sensing and amplifying memory cell data of corresponding columns when activated;a plurality of internal data lines arranged extending along the column direction, each internal data line being provided corresponding to a predetermined number of sense amplifier circuits per one memory block, said plurality of internal data lines including a first group of the internal data lines provided for said first sub array and a second group of the internal data lines provided for said second sub array, the first group including a feed-through line arranged extending in the column direction over said second sub array and formed at an interconnection layer differing from an interconnection layer of the second group; anda plurality of column select circuits provided corresponding to the respective sense amplifier circuits and the respective internal data lines for coupling corresponding sense amplifier circuits to corresponding internal data lines according to a column select signal.