Patent ID: 6745216
Filing Date: 2004-06-01
Classification: G06F,G11C

Abstract:
A shift register comprising:a plurality of register units connected in series, wherein each of the register units comprises: an input selector for selecting one of first input data received from a previous stage and second input data received from a previous stage and second input data received from a data bus, depending on a selection signal; and a storage element for storing and outputting, the selected data to a next stage depending on a shift clock signal; and a controller controlling the selection signal and the shift clock signal to cause only a designated register unit to receive the second input data from the data bus and only downstream register units starting from the designated register unit to shift their data to respective ones of next stages, wherein the controller comprises: a shift position designator for supplying the selection signal to a designated one of the register units depending on the shift position designation data; and a shift clock generator for supplying the shift clock signal to each of the downstream units starting from the designated register unit.