Patent ID: 6159799
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:preparing a substrate having a high-voltage applied region, a peripheral region, a cell region with at least first and second portions, the high-voltage applied region having a well formed therein;simultaneously forming a plurality of spaced floating gates on the first and second portions of the cell region and a plurality of spaced first gates on the high-voltage applied region;implanting first impurity ions in the high-voltage applied region of the substrate using the spaced first gates as a mask to form a first impurity region, the spaced floating gates masking the cell region from the first impurity ions;simultaneously forming control gates each on respective ones of the spaced floating gates of the cell region and a plurality of spaced second gates on the peripheral region;selectively etching one of the control gates and one of the spaced floating gates to form a plurality of gate patterns in the first portion of the cell region; andimplanting second impurity ions in the substrate at sides of the gate patterns and at sides of the spaced first gates to simultaneously form second impurity regions at sides of the gate patterns and twice implanted first impurity regions at sides of the spaced first gates.