Patent ID: 6125470
Filing Date: 2000-09-26
Classification: H04L

Abstract:
An apparatus including a digital signal error detection circuit for identifying interruptions in respective occurrences of opposing signal states of an equalized digital data signal, comprising:an encoding circuit configured to receive and encode first and second data level signals and first and second prior data state signals and in accordance therewith provide first, second and third present data state signals, whereinsaid first data level signal identifies when a present level of an equalized digital data signal extends beyond a first reference prior level of said equalized digital data signal in a first direction beyond a baseline of said equalized digital data signal,said second data level signal identifies when said present level of said equalized digital data signal extends beyond a second reference prior level of said equalized digital data signal in a second direction, opposite said first direction, beyond said equalized digital data signal baseline,said first prior data state signal identifies when a prior equalized digital data signal level extended beyond only one of said first and second reference prior levels of said equalized digital data signal in one of said first and second directions, respectively, beyond said equalized digital data signal baseline,said second prior data state signal identifies which one of said first and second reference prior levels of said equalized digital data signal beyond which said prior equalized digital data signal level extended,said first present data state signal identifies when said present equalized digital data signal level extends beyond only one of said first and second reference prior levels of said equalized digital data signal in one of said first and second directions, respectively, beyond said equalized digital data signal baseline,said second present data state signal identifies which one of said first and second reference prior levels of said equalized digital data signal beyond which said present equalized digital data signal level extends, andsaid third present data state signal identifies when said present equalized digital data signal level has extended beyond only one of said first and second reference prior levels of said equalized digital data signal during a detection time period; anda delay circuit, coupled to said encoding circuit, configured to receive and delay said first and second present data state signals for a delay time period which is shorter than said detection time period and in accordance therewith provide said first and second prior data state signals, respectively.