Patent ID: 8492195
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A method for forming a memory device stack, comprising: providing a semiconductor substrate comprising a surface region; forming a first dielectric material overlying the surface region of the semiconductor substrate; forming a first plurality of memory cells overlying the first dielectric material, each of the first plurality of memory cells comprising at least a first top metal wiring structure spatially extending in a first direction, a first bottom metal wiring structure spatially extending in a second direction orthogonal to the first direction, and a first switching element sandwiched in an intersection region between the first top metal wiring structure and the first bottom metal wiring structure, the first plurality of memory cells forming a first crossbar array of memory cells; forming a second dielectric material overlying the first plurality of memory cells including the top metal wiring structures, the second dielectric material forming a thickness overlying the top metal wiring structures; and forming a second plurality of memory cells overlying the second dielectric material, each of the second plurality of memory cells comprising at least a second top metal wiring structure extending in a third direction, a second bottom metal wiring structure extending in a fourth direction orthogonal to the third direction, and a second switching element sandwiched in an intersection region of the second top metal wiring structure and the second bottom metal wiring structure, the second plurality of memory cells forming a second crossbar array of memory cells, the second plurality of memory cells being isolated from the first plurality of memory cells by the second dielectric material; wherein the first switching element and the second switching element each comprises an amorphous silicon material.