Patent ID: 6407607
Filing Date: 2002-06-18
Classification: H03H

Abstract:
A signal delay circuit, comprising:a first delay stage, a data input to said first stage connected to a first latch of said first stage, a first reference signal connected to input of a second latch of said first stage, a second reference signal connected to input of a third latch of said first stage, an enable signal connected to said first, second and third latch of said first stage, a first wire connected to an output of said first latch of said first stage, a second wire adjacent to said first wire connected to an output of said second latch of said first stage, a third wire adjacent to said first wire connected to an output of said third latch of said first stage, said second and third wire coupled by means of capacitance to said first wire and thereby delaying a first signal at an output end of said first wire by coupling a second signal from the second wire and a third signal from the third wire, a second delay stage configured in similar fashion to said first delay stage, said delayed signal in said first wire connected to an enable signal for said second stage, said data input connected to a first latch of said second stage, said first reference signal connected to input of a second latch of said second stage, and said second reference signal connected to input of a third latch of said second stage.