Patent ID: 7346867
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. A method for minimizing noise problems in a chip design, said chip design comprising one or more nets, each net comprising at least one driver gate driving the net, one or more sinks receiving signals from the net, and a plurality of resistance (R) and capacitance (C) elements representing electrical properties of the net, said resistance being converted to capacitance only, said conversion to capacitance only comprising the steps of: i) setting a load C equal to the total interconnect wire C; ii) modeling the driver gate by replacing the driver with a Thevenin model; iii) determining an amount of electric charge sent into the victim net by said Thevenin model; iv) determining an equivalent C that consumes the same amount of electric charge as the amount of electric charge that was computed in step (iii); and v) repeating steps ii) through iv) until convergence of the value of the equivalent C is achieved, said updated C being a final equivalent C at the output of said driver gate, the method comprising the steps of: a) identifying noise at inputs of the at least one driver gate and computing noise at an output thereof; b) propagating the computed noise at the output to all the sinks attached to said victim net; c) identifying nets coupled to said victim net and signal transitions on said coupled nets, and computing a coupled noise for all the sinks attached to said victim net; d) adding the computed propagation noise to the computed coupled noise; e) iteratively repeating steps a) through d) until a latch is reached; and f) determining if the noise at the latch input overlaps a signal clock, said overlap being indicative of a chip failure.