Patent ID: 8179715
Filing Date: 2012-05-15
Classification: G11C

Abstract:
1. An integrated circuit containing an array of SRAM cells arranged in rows and columns, each of said SRAM cells comprising: a bit-side driver transistor within said each of said SRAM cells of said integrated circuit, said bit-side driver transistor including a gate node, a source node and a drain node; a bit-side data node, wherein said bit-side data node is connected to said drain node of said bit-side driver transistor; a bit-side load transistor, said bit-side load transistor including a gate node, a source node and a drain node, wherein said drain node of said bit-side load transistor is connected to said bit-side data node; a bit-bar-side driver transistor, said bit-bar-side driver transistor including a gate node, a source node and a drain node, wherein said gate node of said bit-bar-side driver transistor is connected to said bit-side data node; a bit-bar-side data node, wherein said bit-bar-side data node is connected to said drain node of said bit-bar-side driver transistor, to said gate node of said bit-side driver transistor and to said gate node of said bit-side load transistor; a bit-bar-side load transistor, said bit-bar-side load transistor including a gate node, a source node and a drain node, wherein said drain node of said bit-bar-side load transistor is connected to said bit-bar-side data node, and said gate node of said bit-bar-side load transistor is connected to said bit-side data node; a bit-side auxiliary load transistor, said bit-side auxiliary load transistor including a gate node, a source node and a drain node, wherein said drain node of said bit-side auxiliary load transistor is connected to said bit-side data node, and said gate node of said bit-side auxiliary load transistor is connected to said bit-bar-side data node; and a bit-bar-side auxiliary load transistor, said bit-bar-side auxiliary load transistor including a gate node, a source node and a drain node, wherein said drain node of said bit-bar-side auxiliary load transistor is connected to said bit-bar-side data node, and said gate node of said bit-bar-side auxiliary load transistor is connected to said bit-side data node.