Patent ID: 8324960
Filing Date: 2012-12-04
Classification: H02M

Abstract:
1. An integrated circuit, comprising: a first PMOS transistor having a first gate oxide layer thickness, wherein a first drain of the first PMOS transistor is arranged to be coupled to a voltage output; a second PMOS transistor having a second gate oxide layer thickness, wherein a first source of the first PMOS transistor is coupled to a second drain of the second PMOS transistor and a second source of the second PMOS transistor is arranged to be coupled to a high power supply voltage; a first MOS capacitor having a third gate oxide layer thickness, wherein a third source of the first MOS capacitor and a third drain of the first MOS capacitor are coupled to the first source of the first PMOS transistor; a first NMOS transistor coupled between the voltage output and a low power supply voltage, the first NMOS transistor having a fourth gate oxide layer thickness, wherein a fourth drain of the first NMOS transistor is coupled to the first drain of the first PMOS transistor, wherein the integrated circuit is configured to receive a voltage input to generate the voltage output that has a broader voltage range with a higher maximum voltage than the voltage input, and the third gate oxide layer thickness of the first MOS capacitor is less than the first gate oxide layer thickness, and the third gate oxide layer thickness of the first MOS capacitor is less than the fourth gate oxide layer thickness of the first NMOS transistor.