Patent ID: 7245150
Filing Date: 2007-07-17
Classification: G01R,H03K

Abstract:
1. A combined multiplexor (mux)/storage circuit comprising: a latch element; a plurality of passgates connected to the latch element, wherein each of the plurality of passgates has an input coupled to receive a signal representing a respective one of a plurality of mux inputs and each of the plurality of passgates is configured to open and close responsive to respective pairs of control signals; and logic circuitry coupled to receive a clock signal, a delayed clock signal, and mux select control signals, wherein the logic circuitry is configured to generate pulses on the pair of control signals to control one of the plurality of passgates that has an input coupled to receive the signal representing a selected one of the plurality of mux inputs, wherein the selected one is indicated by the mux select control signals, and wherein a width of the pulses is dependent on the clock signal and the delayed clock signal; wherein the latch element is configured to latch the signal representing the selected one of the plurality of mux inputs in parallel with the selected one being driven as an output of the mux/storage circuit.