Patent ID: 7900117
Filing Date: 2011-03-01
Classification: G06F

Abstract:
1. A semiconductor memory device comprising: a temporary storage circuit configured to receive a plurality of data items and store the data items in rows and columns; a detecting code generator configured to generate a plurality of first detecting codes used to detect errors in the plurality of data items, respectively; a first correcting code generator configured to generate a plurality of first correcting codes used to correct errors in a plurality of first data blocks corresponding to the columns, respectively, each of the first data blocks containing a number of data items that are arranged in a corresponding one of the columns; a second correcting code generator configured to generate a plurality of second correcting codes used to correct errors in a plurality of second data blocks corresponding to the rows, respectively, each of the second data blocks containing a number of data items that are arranged in a corresponding one of the rows; a semiconductor memory configured to nonvolatilely store the data items, the first detecting codes, the first correcting codes and the second correcting codes; a first corrector configured to correct errors in the plurality of first data blocks using the plurality of first correcting codes, respectively; a detector configured to detect errors in the first data blocks corrected by the first corrector, using the plurality of first detecting codes; and a second corrector configured to correct errors in data items detected by the detector, using the plurality of second correcting codes, wherein the first and second correctors alternately repeat respective correction operations based upon an elapsed time of writing.