Patent ID: 6169439
Filing Date: 2001-01-02
Classification: H03K

Abstract:
A protection circuit for a power field effect transistor (FET), the power FET having a gate, source and drain electrodes, the protection circuit comprising: a drain-gate clamp circuit coupled to divert charge from the power FET drain electrode to the power FET sate electrode when a preselected drain-source voltage is present; a drain-source current limit circuit coupled to divert charge from the power FET gate electrode to the power FET source electrode when a preselected drain-source current occurs; a current limit inhibit circuit coupled between the current limit circuit and the power FET gate electrode, and having a control electrode coupled to the drain-gate clamp circuit, wherein the current limit inhibit circuit disables the current limit circuit when charge flows in the drain-gate clamp circuit; wherein the current limit inhibit circuit further comprises: a first switch having a control electrode coupled to the drain-gate clamp circuit, wherein the first switch is activated by charge from the drain-gate clamp; a second switch having a control electrode coupled to an output of the first switch, wherein the second switch is turned off when the first switch is activated; and a pull down device coupled between the control electrode of the second switch and the power FET source electrode, wherein the pull down device holds the second switch in a conductive state until the first switch is activated.