Patent ID: 6083765
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method for producing a semiconductor memory device, which comprises:placing a multiplicity of memory cells on a semiconductor substrate having a surface defining a plane extending substantially parallel to the surface;providing each of the memory cells with a selection transistor being disposed in the plane and having a gate terminal, a first electrode terminal and a second electrode terminal;providing each of the memory cells with a storage capacitor being associated with and triggerable by the selection transistor and having a ferroelectric dielectric, a first capacitor electrode and a second capacitor electrode;connecting the gate terminal of the selection transistor to a word line;connecting the first electrode terminal of the selection transistor to a bit line;connecting the first capacitor electrode of the storage capacitor to a common conductor layer of electrically conductive material;producing the storage capacitor after production of the selection transistor and metallizing layers associated with the selection transistor for connection of the word and bit lines, in a configuration projecting upward from the plane; andplacing the storage capacitor inside a trench extending as far as the second electrode terminal of the selection transistor.