Patent ID: 6279090
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A method of storing a packet of digital signals applied sequentially as a plurality of packet words to a packetized memory device during normal and synchronization modes of operation of the memory device, the method comprising:storing a plurality of packet words sequentially applied to the memory device responsive to an internal clock signal;storing a plurality of digital control signals sequentially applied coincident with each packet word in response to the internal clock signal by serially shifting the stored digital control signals through a plurality of storage locations, the applied digital control signal being shifted into a first storage location while shifting each previously stored digital control signal to the next higher storage location;detecting a first predetermined condition of the stored values of the digital control signal;placing the packetized memory device in the normal mode of operation upon detection of the first predetermined condition;shifting the stored packet words to a new storage location responsive to the values of the digital control signal stored in predetermined ones of the storage locations to thereby store a packet in the new storage location;detecting a second predetermined condition of the stored values of the digital control signal;placing the packetized memory device in a synchronization mode of operation upon detection of the second predetermined condition;generating a synchronization clocking signal in response to the internal clock signal during the synchronization mode of operation; andshifting the stored packet words to the new storage location responsive to the synchronization clocking signal to thereby store a packet in the new storage location during the synchronization mode of operation.