Patent ID: 7170781
Filing Date: 2007-01-30
Classification: B64C,G01N,G06F,G11C

Abstract:
1. A non-volatile semiconductor memory comprising: an array of memory cells; drivers and decoders coupled to apply voltages to the array, as required to write to any memory cell in the array and to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell; a reference generator that generates first reference signals and second reference signals, wherein the first reference signals indicate bounds of allowed ranges of threshold voltages corresponding to data values that can be stored in the memory cell, and the second reference signals indicate bounds of one or more forbidden ranges of threshold voltages corresponding to data errors, wherein the allowed ranges of threshold voltages are separated from each other by at least one forbidden range; and a control circuit coupled to control the drivers and decoders during a read process, the control circuit including logic that initiates a process to refresh a threshold voltage of a memory cell when a read process that detects that the threshold voltage of the memory cell is in a forbidden range.