Patent ID: 6654291
Filing Date: 2003-11-25
Classification: G11C

Abstract:
An electrically erasable programmable read-only memory comprising:a first memory cell having a first control gate and a first source; and a second memory cell having second control gate and a second source; wherein if the first and second control gates are configured to receive a control gate voltage, the first source is configured to receive a first source voltage, and the second source is configured to receive a second source voltage different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells, and wherein if the first and second sources are configured to receive a source voltage, the first control gate is configured to receive a first control gate voltage, and the second control gate is configured to receive a second control gate voltage different from the first control gate voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.