Patent ID: 6085277
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A system for handling I/O messages transmitted over an I/O bus, comprising:a processor complex connected to the I/O bus, said processor complex including a memory device having a message queue structure;an I/O adapter connected to the I/O bus, said I/O adapter includinga message processor to process messages, to generate messages, and to send messages to the message queue structure;a signalling timer timing an interval beginning with placing a message in the message queue structure; anddecision logic deciding when to signal an interrupt to said processor complex;said decision logic programs the signalling timer with a fast signal time value if the message has a relatively short latency period or with a slow signal time value if the message has a relatively long latency period, andthe decision logic starts the signalling timer when the message is enqueued, andsaid decision logic signalling an interrupt to said processor complex when the signalling timer has elapsed.