Patent ID: 6195783
Filing Date: 2001-02-27
Classification: H04H,H04L

Abstract:
A method for synchronizing a block counter in an RDS receiver, comprising the steps of:consecutively reading in bits from an output of an RDS receiver to a 26-bit shift register, the bits having a bit frequency and being read into the shift register at the bit frequency;cycling the bits in the shift register during a bit period for transfer into a syndrome detection circuit wherein in each bit period, the bits cycle a number of times at least equal to a number of total allowable offset words and bits are X-OR gated with bits of one of a plurality of offset words generated by an offset word generator, the bits being X-OR gated in a standard sequence controlled by an address counter prior to being transferred into the syndrome detection circuit; andtriggering a sync pulse via the syndrome detection circuit for predetermined cyclically used offset words, the sync pulse being generated when a zero syndrome is detected, the sync pulse setting a block counter to a status of the address counter and resetting a bit counter to zero when the one of the plurality of offset words is a predetermined offset word.