Patent ID: 8489789
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. An apparatus comprising: one or more hardware processors; a memory controller configured to couple to a memory; and a device interrupt manager implemented in hardware in an input/output memory management unit (IOMMU) separate from the hardware processors, wherein the device interrupt manager is coupled to the memory controller, and wherein the device interrupt manager is configured to receive an interrupt from a device that is assigned to a guest, wherein the device interrupt manager is configured to transmit a first write memory operation to the memory controller to record the interrupt in a memory location of the memory, wherein the memory location is associated with a virtual processor within the guest, wherein the virtual processor is targeted by the interrupt, and wherein the device interrupt manager is configured to record the interrupt in the memory location independent of whether or not the virtual processor is active on the hardware processor, and wherein the hardware processor is configured to detect the recordal responsive to the virtual processor being active on the hardware processor.