Patent ID: 6841874
Filing Date: 2005-01-11
Classification: H01L

Abstract:
1. A wafer-level chip-scale package comprising: a semiconductor die having top and bottom surfaces of an approximately planar shape and a plurality of metal pads formed at the top surface in an area array through a redistribution process; a first protective layer formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward; a second protective layer formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than the first apertures of the first protective layer so that regions of the metal pads and the first protective layer are opened to the outside; and a plurality of solder balls fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer.