Patent ID: 7863933
Filing Date: 2011-01-04
Classification: G06F

Abstract:
1. A tri-state I/O port comprising: a tri-state logical block having a data input terminal, an enable input terminal, and an output terminal wherein the data input terminal receives a data and the enable input terminal receives an enable signal and when the enable signal is enabled, the output terminal of the tri-state logical block is pulled high when the data is high while the output terminal of the tri-state logical block is pulled low when the data is low, wherein the tri-state logical block comprises a pull strong high block which is connected to the data input terminal, the enable input terminal, and the output terminal of the tri-state logical block; and a pull strong low block which is connected to the data input terminal, the enable input terminal, the output terminal of the delay block and the output terminal of the tri-state logical block; a weak buffer having an input terminal and an output terminal, wherein the input terminal and the output terminal of the weak buffer are directly connected to the output terminal of the tri-state logical block and the output terminal of the tri-state logical block is kept at a weak high level by the weak buffer when the output terminal of the tri-state logical block is from low to high while the output terminal of the tri-state logical block is kept at a weak low level by the weak buffer when the output terminal of the tri-state logical block is from high to low; and a delay block having an input terminal and an output terminal, wherein the input terminal of the delay block is connected to the output terminal of the tri-state logical block and the output terminal of the delay block is fed back to the tri-state logical block; wherein, the pull strong high block comprises a NAND component including an output terminal and a first input terminal connected to the data input terminal and a second input terminal connected to the enable input terminal, and a first transistor having a gate connected to the output terminal of the NAND component, a source connected to a power source, and a drain connected to the output terminal of the tri-state logical block; and the pull strong high block/pull strong low block is turned off when the output terminal of the tri-state logical block is kept at a weak high/low level by the weak buffer.