Patent ID: 8106699
Filing Date: 2012-01-31
Classification: H03K

Abstract:
1. A level shifter receiving an input signal and producing an output signal on an output path, the level shifter comprising: level detection circuitry coupled to the output path, the level detection circuitry operable to generate a mode selection signal in response to a signal level on the output path; mode control circuitry coupled to the level detection circuitry, the mode control circuitry operable to select a mode of operation in response to the mode selection signal; level shifting circuitry comprised of electronic components having signal level reliability limits less than a maximum signal level of the output; and a timing circuit coupled to said level shifting circuitry, said timing circuit operable to control a time of application of the input signal to said level shifting circuitry to prevent a signal level at one or more terminals of said electronic components from exceeding said signal level reliability limits wherein said level shifter operates to selectively shift a signal level of the input signal to a first signal level and a second signal level depending on said mode of operation, said second signal level being said maximum signal level of the output signal, and wherein said timing circuit. includes a mode selection input receiving the mode selection signal used to alter said time of application of said input signal in accordance with said mode of operation.