Patent ID: 6075729
Filing Date: 2000-06-13
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of word lines;a plurality of bit line pairs;a plurality of memory cells formed at points of intersection between said word lines and said bit line pairs;a word decoder for generating a word line select signal upon receipt of an address signal;a bit decoder for generating a bit line select signal upon receipt of said address signal;a bit line load circuit for receiving a signal current from an applicable one of the memory cells;a sense circuit for detecting an output signal from said bit line load circuit; anda bit line pull-down circuit and a bit line recovery circuit for driving the applicable bit lines at the time of writing data to a memory cell to be written;wherein said bit line load circuit and said bit line recovery circuit include pMOS transistors which have drains thereof connected to the bit lines and which have gates thereof fed with a control signal, and diodes which have anodes thereof connected to a first power supply and which have cathodes thereof connected to sources of said pMOS transistors, said pMOS transistors and said diodes being furnished to each of said bit line pairs; andwherein said PMOS transistors are inhibited from conducting while the bit lines are being driven Low by said bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a real cycle.