Patent ID: 6101595
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache configured to store a plurality of cache lines of instruction bytes and to provide a first group of instruction bytes upon receipt of a first index address and a first way address in a first clock cycle, to an instruction processing pipeline of said microprocessor;a branch prediction unit coupled to said instruction cache and coupled to receive said first index address and said first way address concurrent with said instruction cache, wherein said branch prediction unit is configured to provide a sequential way corresponding to said first group of instruction bytes in response to said first index address and said first way address, and wherein said sequential way is used as a subsequent way address by said instruction cache in response to a branch prediction algorithm predicting a sequential execution path; andwherein the instruction cache is configured to provide a second group of instruction bytes to the instruction processing pipeline of said microprocessor upon receipt of a second index and a second way in a second clock cycle succeeding said first clock cycle, wherein said second way is selected to be said sequential way.