Patent ID: 7496780
Filing Date: 2009-02-24
Classification: H04J,H04L

Abstract:
1. Signal processing circuitry comprising: (a) a plurality of parallel processing channels organized in one or more macrocells, each macrocell having one or more channels; and (b) clock-generation circuitry adapted to generate (i) one or more reference clock signals for driving the channels and (ii) one or more synchronization signals applied to the channels, wherein: each synchronization signal has a plurality of synchronization pulses; when a channel receives a synchronization pulse in a synchronization signal, the channel resets its operations to a specified state, thereby reducing data skew between the channels; each channel is adapted to function as a multiplexer; and each channel is adapted to implement a state machine used to control the multiplexing of input signals applied to the channel, wherein the state machine is reset to a specified state whenever a synchronization pulse is received by the channel.