Patent ID: 7702976
Filing Date: 2010-04-20
Classification: H03K

Abstract:
1. An integrated circuit structure comprising: a plurality of logic blocks, wherein at least one of said logic blocks comprises a redundant logic block; a logic built-in self test device (LBIST) operatively connected to said logic blocks that determines a logic block functionality of each of said logic blocks; an array of memory elements operatively connected to said logic blocks, wherein at least one of said memory elements comprises a redundant memory element; an array built-in self test device (ABIST) operatively connected to said array of memory elements that determines a memory element functionality of each of said memory elements; a first register operatively connected to said ABIST that stores said memory element functionality; a second register operatively connected to said ABIST that stores an identifier for failing memory elements; a first comparator operatively connected to said second register that enables said redundant memory element to operate in place of said failing memory elements; a third register operatively connected to said LBIST that stores said logic block functionality; a fourth register operatively connected to said LBIST that stores an identifier for failing logic blocks; a second comparator operatively connected to said fourth register that enables said redundant logic block to operate in place of said failing logic blocks; and a single controller operatively connected to said first register, said second register, said third register, said fourth register, said logic blocks, and said memory elements, that repairs said failing logic blocks using said redundant logic block, and that repairs said failing memory elements using said redundant memory element.