Patent ID: 6552936
Filing Date: 2003-04-22
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a memory cell array; a row decoder which selects a row of said memory cell array; a sense amplifier which senses a plurality of data corresponding to a plurality of addresses from said memory cell array; a column gate in which two or more stages are connected in series, and which selects a column of said memory cell array and electrically connects said selected column to said sense amplifier; a column gate driving circuit which selects and drives said column gate; a data latch which latches said plurality of data sensed by said sense amplifier; a multiplexer which sequentially selects said data corresponding to a predetermined address from said plurality of data latched by said data latch; and an address control circuit which reverses a driving signal to drive at least one stage of said column gate with said two or more stages connected in series and selects columns designated by a plurality of addresses selected next to said plurality of addresses, during sequential selection of said data corresponding to said predetermined address by said multiplexer.