Patent ID: 9116247
Filing Date: 2015-08-25
Classification: G01T

Abstract:
1. A neutron detector circuit for a neutron detector, comprising: a scintillator having a plurality of wavelength shifting optical fibers, wherein a first set of wavelength shifting optical fibers are connected with a first input of at least one photomultiplier tube (“PMT”) and a second set of wavelength shifting optical fibers are connected with a second input of said at least one PMT, wherein said at least one PMT includes a first PMT output and a second PMT output and is operable to generate a first PMT output pulse on said first PMT output in response to a first neutron event detected on said first input of said at least one PMT and a second PMT output pulse on said second PMT output in response to a second neutron event detected on said second input of said at least one PMT; a dual channel comparator circuit configured to receive said first PMT output pulse and said second PMT output pulse, wherein in response to said first PMT output pulse said dual channel comparator is configured to generate a first comparator output pulse and in response to said second PMT output pulse said dual channel comparator circuit is configured to generate a second comparator output pulse; a first logic algorithm circuit configured to receive said first comparator output pulse, wherein said first logic algorithm circuit is configured to generated a first logic algorithm circuit output pulse after a first predetermined number of first comparator output pulses are received by said first logic algorithm circuit and a second logic algorithm circuit output pulse after a second predetermined number of first comparator output pulses are received by said first logic algorithm circuit; a second logic algorithm circuit configured to receive said second comparator output pulse, wherein said second logic algorithm circuit is configured to generate a third logic algorithm circuit output pulse after a third predetermined number of second comparator output pulses are received by said second logic algorithm circuit and a fourth logic algorithm circuit output pulse after a fourth predetermined number of first comparator output pulses are received by said second logic algorithm circuit; and a coincidence detection circuit connected with said first and second logic algorithm circuits, wherein said coincidence detection circuit is configured to generate a neutron event output pulse if said coincidence detection circuit receives said first logic algorithm output pulse and said third logic algorithm output pulse or said second logic algorithm output pulse and said fourth logic algorithm output pulse.