Patent ID: 6292404
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A semiconductor memory, comprising:a memory cell array composed of plural memory cells of a predetermined number which are decoded in row and column directions,a data input memory means for temporarily storing a data to be written into said memory cell array, andan operation-control means which refers to another data read from a memory cell for write in said memory cell array and enable signals concerned with data-writing, and writes said data into said memory cell for write in accordance with a state of said enable signals whereinsaid operation-control means activates either OR operation enable (ORE) signal or AND operation enable (ANDE) signal and write enable (WE) signal in a write cycle,conducts OR or AND operation between said data to be written into said memory cell for write and said another data read from a memory cell for write in said memory cell array, andwrites said data for write supplied from said data input memory means into said memory cell for write in case that said OR or AND logic is met.