Patent ID: 6081904
Filing Date: 2000-06-27
Classification: G06F,H04L

Abstract:
A system for enabling chips having different clock frequencies to communicate, comprising:a computer system having an interconnected number of chips having at least two chips with different internal design clock frequencies, including slow chip and fast chips,a master clock source for at least those chips which have different internal design clock frequencies to provide a master clock reference signal which controls whether the chip internal clocks are on,each of said slow chips and said fast chips having said different internal design clock frequencies having chip intrepretation logic for intrepreting said reference signal as it pertains to the chip's internal clock frequency, a fast chip intrepretation logic intrepreting said reference signal such that a fast chip's internal clock always rises with a rising reference signal, and said slow chip intrepretation logic intrepreting said reference signal such that a slow chip's internal clock only rises periodically with said reference signal.