Patent ID: 7019568
Filing Date: 2006-03-28
Classification: H03K

Abstract:
1. A clock-independent power-on-reset circuit comprising: a first voltage divider connected to a supply voltage, wherein said first voltage divider is an NMOS voltage divider; a second voltage divider connected to said supply voltage; an amplifier coupled to said first and second voltage dividers, wherein an output of said first voltage divider is coupled to a non-inverting input of said amplifier, and wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to an even plurality of coupled asymmetrical inverters in addition to a coupled pair of asymmetrical inverters of said amplifier, wherein said high gain amplifier in open loop mode operates as a comparator; a feedback circuit for feeding back an output of the amplifier to said input of the amplifier, wherein said feedback circuit provides hysteresis to stabilize said high gain open loop mode amplifier; and an even plurality of coupled asymmetrical inverters in addition to the coupled pair of asymmetrical inverters of said amplifier.