Patent ID: 6348707
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A method of manufacturing a dynamic random access memory (DRAM) capacitor, comprising the steps of:providing a semiconductor substrate having a field effect transistor thereon, wherein the field effect transistor includes a source/drain region; forming an insulation layer over the semiconductor substrate; forming a contact opening in the insulation layer, wherein the contact opening exposes the source/drain region; forming a triblock copolymer layer over the semiconductor substrate and inside the contact opening; patterning the triblock copolymer layer; annealing the triblock copolymer layer at a low temperature; exposing the triblock copolymer layer to ultraviolet light in an atmosphere containing ozone so that the triblock copolymer transforms into a lower electrode layer having a bicontinuous interlaced three-dimensional nanoporous structure; forming a dielectric layer over the lower electrode layer; and forming an upper electrode layer over the dielectric layer.