Patent ID: 7978495
Filing Date: 2011-07-12
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array comprising two-terminal memory cells each comprising a variable resistance element having a resistance value reversibly changed by electric pulse application, the memory cells being arranged in a row direction and column direction such that one end of each memory cell in the same row is connected to a common word line and the other end of each memory cell in the same column is connected to a common bit line; a memory cell selecting circuit selecting the memory cell from the memory cell array by the row, column or memory cell; a voltage switch circuit applying a voltage required for each of a plurality of memory actions including a reading action, a programming action and an erasing action in the memory cell selected by the memory cell selecting circuit, to a selected word line and a selected bit line connected to a selected memory cell and to unselected word lines and unselected bit lines other than the above selected word line and selected bit line among word lines and bit lines, according to the memory actions; and a reading circuit reading information stored in the memory cell to be read in the selected memory cells by detecting the amount of a reading current flowing according to the resistance value of the variable resistance element in the memory cell to be read, wherein the voltage switch circuit applies a common unselect voltage to both the unselected word lines and the unselected bit lines during each of the reading, programming and erasing actions.