Patent ID: 7698357
Filing Date: 2010-04-13
Classification: G06F

Abstract:
1. A hardware device for calculating a multiplication of a multiplier and a multiplicand with regard to a modulus using an iteration method comprising several iteration steps, comprising a preceding iteration step, a current iteration step and an iteration step following the current iteration step, comprising: a hardware calculating unit; a first hardware register configured to store the modulus, the first hardware register being coupled to the hardware calculating unit; a second hardware register configured to store the multiplicand, the second hardware register being coupled to the hardware calculating unit; a third hardware register configured to store an intermediate result, the third hardware register being coupled to the hardware calculating unit; wherein the hardware calculating unit is configured to: wherein the multiplication of the multiplier and the multiplicand with regard to the modulus is calculated within a cryptographic calculation, and wherein the multiplier, the multiplicand and the modulus are parameters of the cryptographic calculation.