Patent ID: 6421291
Filing Date: 2002-07-16
Classification: G11C

Abstract:
A semiconductor memory device internally converting serial data supplied from and to any external unit into parallel data and executing reading and writing operations thereof, comprising:a memory cell array having a plurality of memory cells arranged in rows and columns; a data terminal for input and output of N data (N: natural number) transmitted in time series manner; and a data input/output circuit for reading and writing said N data from and into said memory cell array; said data input/output circuit including: N write data lines and N read data lines for transmitting said N data in parallel; a first data conversion circuit which converts N serial data supplied from said data terminal into N parallel data to transmit the parallel data to said N write data lines respectively; a second data conversion circuit which converts N parallel data transmitted by said N read data lines into N serial output data to be output from said data terminal; a read and write circuit for supplying and receiving said N data between said N write data lines and said memory cell array and between said N read data lines and said memory cell array; and an input/output test circuit which transfers data transmitted by said N write data lines respectively to said N read data lines in an input/output test operation.