Patent ID: 7599381
Filing Date: 2009-10-06
Classification: H04L

Abstract:
1. A method for scheduling using hardware control logic or one or more processor elements, the method comprising: (a) maintaining a plurality of schedule entries in one or more tangible computer-readable media, with each of the plurality of schedule entries respectively associated with a start time and a speed group of a plurality of speed groups, with each said speed group associated with a time value representing a single predetermined approximated finish delay for use in scheduling each scheduling entry associated with the corresponding said speed group, and with each of the plurality of speed groups representing a respective range of at least two different scheduling rates; (b) identifying an approximated earliest finishing entry of a subset of the plurality of schedule entries that are currently eligible, the approximated earliest finishing entry having an earliest approximated finish time of the subset of the plurality of schedule entries, each said approximated finish time determined based on an entry's respective said start time and said approximated finish delay of its associated said speed group; (c) initiating an action corresponding to the approximated earliest finishing entry in response to said identifying the approximated earliest finishing entry; and (d) updating said start time of the approximated earliest finishing entry based on an amount corresponding to the action.