Patent ID: 6785749
Filing Date: 2004-08-31
Classification: G06F,H03M

Abstract:
A processing system comprising:a central processing unit; a device peripheral bus; a plurality of peripheral modules coupled to the peripheral device bus, each peripheral module including a control register, each peripheral module generating selected status/event signals, the selected status event signals determined by control signals from the control register; an inter-module bus coupled to each of the modules; and an inter-module controller unit coupled to the peripheral modules, the inter-module control unit receiving at status/event signals from each module coupled thereto, the inter-module controller applying the selected status/event signals to the inter-module bus, the inter-module bus applying status/event signals from other modules to each module, each module entering preselected status/event signals therein, the preselected status/event signals determined by control signals from the control register.