Patent ID: 8525265
Filing Date: 2013-09-03
Classification: H01L,H02H

Abstract:
1. An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, the ESD protection circuit comprising: a P channel metal oxide semiconductor (PMOS) transistor having a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor; an impedance device, coupled between the gate of the PMOS transistor and a first power rail; a first ESD clamp circuit, coupled to a second power rail and the input pad; a second ESD clamp circuit, coupled to a second ground rail and the input pad; and a third ESD clamp circuit, coupled to a first ground rail and the second ground rail.