Patent ID: 9184290
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a sacrificial layer on a semiconductor substrate; forming a channel layer on the sacrificial layer; providing at least one gate structure on the channel layer, said at least one gate structure having a spacer located on each of vertical sidewalls of said at least one gate structure; recessing exposed portions of said channel layer and portions of said sacrificial layer and said semiconductor substrate located beneath said exposed portions of said channel layer utilizing said at least one gate structure and said spacer as an etch mask, wherein the recessing forms trenches in said semiconductor substrate; laterally recessing a remaining portion of said sacrificial layer selectively with respect to said channel layer and said semiconductor substrate by a lateral distance to provide a lateral recess in each side of said remaining portion of said sacrificial layer; depositing a doped semiconductor material in said trenches and said lateral recesses; and annealing the doped semiconductor material, wherein during the annealing dopants of the semiconductor material diffuse into portions of said semiconductor substrate adjacent said lateral recesses to form a first doped region and into portions of said channel layer over said lateral recesses to form a second doped region.