Patent ID: 8064249
Filing Date: 2011-11-22
Classification: B82Y,G11C,H01L,Y10S

Abstract:
1. A static random access memory (SRAM) device, the device comprising: first and second switching devices connected to bit lines; and third and fourth switching devices respectively connected to two load resistors, the third and fourth switching devices being connected in a latch structure, and each of the first, second, third, and fourth switching devices comprising: a source electrode and a drain electrode disposed on an insulating substrate and spaced apart from each other; a first nanowire vertically grown on the source electrode, and to which a V a second nanowire vertically grown on the drain electrode, and to which a V a gate electrode spaced apart from the second nanowire, partially surrounding the second nanowire and having an opening that faces the first nanowire to avoid disturbing a mutual switching operation of the first nanowire and the second nanowire, and to which a V