Patent ID: 6259389
Filing Date: 2001-07-10
Classification: G06F,H03M

Abstract:
A method of determining the non-linearity and non-ideality of an analog-to-digital device under test, the device under test having at least one integrator, a respective non-linear integrator model, and non-linearity parameters, said method comprising the following steps:generating a model data set from a plurality of simulations of the analog-to-digital device under test employing the respective non-linear integrator model wherein the respective non-linear integrator model comprises at least one polynomial equation;generating an n-dimensional prediction equation corresponding to said model data set;measuring the input response of each respective non-linear integrator to generate a respective input response test data set;generating a plurality of numerical values for the non-linearity coefficients in the non-linear integrator model from said respective test data set; anddetermining the acceptability of the analog-to-digital device under test by solving said prediction equation using said plurality of numerical values as input values.