Patent ID: 8751975
Filing Date: 2014-06-10
Classification: G06F

Abstract:
1. A method comprising: determining model parameters for forming an integrated circuit; and generating a techfile using the model parameters, wherein the generating the techfile is performed using a computer, and wherein the techfile comprises at least two of a C_worst table, a C_best table, and a C_nominal table, and wherein: converting the greatest capacitance and the smallest capacitance into an equivalent k_worst value and a k_best value, respectively, wherein the k_worst value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to increase to the greatest capacitance when the first lithography mask shift relative to the second lithography mask, and wherein the k_best value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to reduce to the smallest capacitance when the first lithography mask shift relative to the second lithography mask.