Patent ID: 6323118
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A method of forming a self-aligned, borderless contact utilizing a dual damascene process having two etch-stop layers comprising the steps of:providing a semiconductor substrate having a substructure further comprising a semiconductor device within said substrate and an interconnect metal line formed on said substrate;forming a first dielectric layer over said substrate;forming a first etch-stop layer over said first dielectric layer;forming a second dielectric layer over said first etch-stop layer;forming a second etch-stop layer over said second dielectric layer;forming a first photoresist layer over said second etch-stop layer;patterning said first photoresist layer with contact and via (contact/via) hole pattern;etching through said contact/via hole pattern in said first photoresist layer and forming contact/via hole opening in said second etch-stop layer wherein said contact hole pattern is disposed over said device in said substructure and said via hole pattern is disposed over said metal line in said substrate;removing said first photoresist layer from said substrate;forming a second photoresist layer over said substrate including said contact/via hole opening;patterning said second photoresist layer with a metal line trench pattern;etching through said line trench pattern in said second photoresist layer into underlying said substrate until etch-stop layers, including said first and second etch-stop layers, are reached;etching said line trench pattern into said first and second etch-stop layers forming said line trench opening into said first and second etch-stop layers;etching further said line trench pattern into underlying substrate including said first and second dielectric layers until reaching said substructure, thus completing the forming of said self-aligned borderless contact;removing said second photoresist layer;forming metal in said contact/via opening in said first and second dielectric layers; andremoving excess of said metal from the surface of said substrate in preparation for subsequent steps to complete the fabrication of a semiconductor substrate utilizing said dual damascene process.