Patent ID: 6204704
Filing Date: 2001-03-20
Classification: H03K

Abstract:
An integrated circuit comprising a DC sensing power-up reset (PUR) circuit, the PUR circuit comprising:(a) a first terminal for receiving a supply voltage and a second terminal for receiving a reference voltage corresponding to a low logic state;(b) a first transistor coupled between the first terminal and a first node, wherein the first transistor switches on when the supply voltage is rising and exceeds a rising trip point voltage and the first transistor has a gate terminal coupled to the second terminal;(c) a second transistor coupled between the first terminal and the first node, wherein the second transistor switches off when the supply voltage falls below a falling trip point voltage which is less than the rising trip point voltage;(d) a first inverter coupled at an input terminal to the first node and at an output terminal to a second node; and(e) a resistor coupled between the first node and the second terminal for pulling the first node down to the reference voltage while the first and second transistors are both off and for limiting current flowing through the first and second transistors while either or both of the first and second transistors is on.