Patent ID: 7941715
Filing Date: 2011-05-10
Classification: G01R,H03K

Abstract:
1. An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool and comprising: a first pair of logic gates, each logic gate having first and second inputs; a second pair of logic gates respectively coupled upstream from said first pair of logic gates, each logic gate of said second pair of logic gates having a first input configured to receive one of a pair of test command signals, a second input, and an output coupled to the respective first input of each logic gate of said first pair of logic gates; a plurality of feedback connections coupled between outputs of said first pair of logic gates and the respective second inputs of said second pair of logic gates; and a multiplexer coupled to the outputs of said first pair of logic gates and also coupled to at least one first input of said second pair of logic gates.