Patent ID: 6399426
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method for making an integrated circuit assembly comprising the steps of:(a) providing an integrated circuit chip having an active surface with a plurality of discrete solder bumps; (b) applying a hardened encapsulant over at least a portion of said active surface and the plurality of discrete solder bumps of the integrated circuit chip wherein said encapsulant after being cured has a coefficient of thermal expansion of about 30 ppm/Â° C. and an elastic modulus greater than about 2 GPa; (c) exposing the tips of one or more of said plurality of discrete solder bumps; (d) providing a printed circuit substrate having a substrate surface with a plurality of discrete metallized pads thereon at least one pad corresponding to an exposed solder bump on the encapsulated chip; (e) applying a polymer flux encapsulant over at least a portion of the interface between the printed circuit substrate and the encapsulated chip; (f) placing said encapsulated chip on said printed circuit substrate to form a combined unit whereby said solder bumps in said encapsulated chip are aligned with said corresponding pads on said printed circuit; (g) heating said combined unit to melt said solder bumps to electrically connect said solder bumps to said metallized pads of the printed circuit substrate; and (h) simultaneously curing said encapsulant.