Patent ID: 8873876
Filing Date: 2014-10-28
Classification: G06K,G06T,H04N

Abstract:
1. An image encoder configured to write coded image data in a memory, the encoder comprising: an encoding module configured to divide original image data comprising a plurality of pixels into a plurality of block lines, to divide each block line into a plurality of sub-block lines, to encode the original image data in each sub-block line, and to generate a plurality of coded sub-block lines; a write address determining module configured to determine a write address of the memory in each coded sub-block line based on a number of the sub-block lines, an original image data size of the original image data, and image coding rate; and a memory controller configured to write the coded sub-block line in the write address corresponding to the coded sub-block line, wherein: the coded sub-block line comprises a first coded sub-block line comprising a starting pixel of the block line and a second coded sub-block line subsequent to the first coded sub-block line, and the memory controller: