Patent ID: 6642781
Filing Date: 2003-11-04
Classification: H03H

Abstract:
In an integrated circuit (IC), a selectable input equalization system comprising:a first buffer having an input connected to a signal input of the IC, the first buffer having a control input and a signal output to selectably supply an equalized output in response to commands to the control input; a second buffer having an input connected to the signal output of the first buffer, the second buffer having a control input and a signal output to selectably supply an equalized output in response to commands to the control input; a third buffer having an input connected to the signal output of the second buffer, the third buffer having a control input and a signal output to selectably supply an equalized output in response to commands to the control input; at least a fourth buffer having an input connected to the signal output of the third buffer, the fourth buffer having a control input and a signal output to selectably supply an equalized output in response to commands to the control input; and a control unit having an input to accept equalization commands, a first output connected to the control input of the first buffer to supply selection commands, a second output connected to the control input of the second buffer to supply selection commands, a third output connected to the control input of the third buffer to supply selection commands and a fourth output connected to the control input of the fourth buffer to supply selection commands; wherein the signal input and signal output signals are differential signals; and wherein the control unit accepts digital logic equalization commands.