Patent ID: 6329287
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method for forming metal salicide regions and metal salicide exclusion regions during the manufacturing of an integrated circuit (IC), the method comprising the steps of:(a) providing an IC structure including a plurality of MOS transistor structures, the plurality of MOS transistor structures having exposed silicon surfaces;(b) depositing a metal layer on the IC structure;(c) forming a photoresist masking layer on those MOS transistor structures where metal salicide regions are to be formed;(d) removing the metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed;(e) after step (d), stripping the photoresist masking layer; and(f) after step (e), reacting metal in the metal layer with silicon in the exposed silicon surfaces to form metal salicide regions.