Patent ID: 6048740
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., comprising:preparing a silicon substrate for construction of a ferroelectric gate unit;implanting boron ions to form a p- well in the substrate;isolating plural device areas on the substrate;forming a ferroelectric (FE) gate stack surround structure for surrounding a ferroelectric (FE) gate stack which is formed in a subsequent step, the step of forming a FE gate stack surround structure including depositing a PSG layer by CVD at a temperature of between about 300.degree. C. and 500.degree. C. having a thickness of between about 100 nm to 300 nm over the device area; anddepositing an oxide layer over the PSG layer to a thickness of between about 20 nm to 50 nm;etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region;depositing, by CVD, oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate;forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.;depositing a first insulating layer over the structure;implanting arsenic ions to form a source region and a drain region; andannealing the structure, including forming a lightly doped source region and a lightly doped drain region in the silicon substrate below the PSG by heating the structure at a temperature of between 600.degree. C. to 1,000.degree. C. for between about 10 minutes and 60 minutes.