Patent ID: 6372586
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method for forming an LDMOS transistor, comprising the steps of:providing a plurality of striped diffusion regions of a first conductivity type defining source regions, the source regions being rectangular and being arranged in rows, the rows of source regions being further arranged in columns; providing a plurality of striped diffusion regions of a second conductivity type defining drain regions, the drain regions being rectangular and being arranged in rows disposed between said rows of source regions so that said rows of drain regions and rows of source regions alternate in said columns; providing a plurality of gate oxide regions being formed around said rows of said source regions so the gate oxide regions are disposed between said alternating rows of drain and source regions in said columns; providing a plurality of gate polysilicon regions partially overlying each one of said plurality of gate oxide regions; providing a plurality of first metal regions forming source busses, each running perpendicular to said rows of said alternating source and drain regions, each running parallel to said columns, each source bus partially overlying said rows of source and drain regions; providing a plurality of second metal regions forming drain busses, each running perpendicular to said rows of said alternating source and drain regions, each running parallel to said columns, each drain bus partially overlying said rows of source and drain regions and being spaced apart from said source busses and being disposed between them so that said source and drain busses alternate; and providing a plurality of copper third metal conductors overlying said second metal regions and electrically contacting said second metal regions to lower the resistance of said LDMOS transistor.