Patent ID: 6734748
Filing Date: 2004-05-11
Classification: H03L

Abstract:
A phase-locked loop frequency source comprising:an error detector, a loop filter receiving an output from said error detector, and a voltage controlled oscillator receiving an input from the loop filter and providing an output frequency; an oscillator; a first counter coupled to be clocked by said oscillator a second counter coupled to be clocked by said voltage controlled oscillator; said first and second digital counters providing outputs for comparison for said error detector; said error detector including a lock detect circuit providing a lock signal when the outputs of said digital counters are locked; a clock comparison circuit receiving inputs from said second counter and said oscillator, and when the outputs of said digital counters are locked, said input to the clock comparison circuit from said second counter occurring during a half cycle of said oscillator before said second counter reaches a total count; and a switching circuit responsive to the lock signal to couple the output of said first counter to said error detector when the lock signal does not indicate the outputs of said first and second counters are locked, and to couple an output of the clock comparison circuit to said error detector and to disable said first counter when the lock signal indicates the outputs of said first and second counters are locked.