Patent ID: 6078487
Filing Date: 2000-06-20
Classification: H01L,H03K

Abstract:
A protection circuit for protecting an integrated circuit (IC) device from damage due to electrostatic discharge (ESD) voltages applied to an input or output (I/O) signal pad of the IC, the protection circuit comprising:an ESD clamp device having a first terminal connected to the signal pad, a second terminal connected to a ground reference voltage, and a control terminal, the control terminal for selectively connecting the first and second terminals together; anda modulation circuit coupled to the ESD clamp, the modulation circuit disabling the ESD clamp during normal operation and thus disconnecting the signal pad from the ground reference voltage, but, when the voltage at the signal pad exceeds a predetermined control voltage indicating an ESD event, the modulation circuit enabling the ESD clamp and thus connecting the signal pad to the ground reference voltage said modulation circuit being an inverter that has a signal input terminal, a signal output terminal, and a supply voltage terminal, with the signal input terminal being connected to an operating supply voltage, the signal output terminal being connected to said control terminal, and the supply voltage terminal being connected to the signal pad.