Patent ID: 6795342
Filing Date: 2004-09-21
Classification: G11C

Abstract:
An array of dual bit dielectric memory cells, the array comprising:a first bit line of a first conductivity semiconductor forming a source region for each of a plurality of memory cells within a column of memory cells within the array; a second bit line of the first conductivity semiconductor forming a drain region for each of the plurality of memory cells within the column, the second bit line separated from the first bit line by a semiconductor of the opposite conductivity forming a channel region for each of the plurality of memory cells within the column; a selected word line positioned over the channel region of a selected one of the plurality of memory cells within the column and further forming a gate for each for a plurality of memory cells within a same row of the array as the selected memory cell; a plurality of non-selected word lines, each parallel to the selected word line and each forming a gate over one of the plurality of memory cells within the column other than the selected one of the plurality of memory cells; a word line control circuit for: applying a positive programming voltage to the selected word line; a bit line control circuit for applying, in conjunction with the word line control circuit applying the positive programming voltage to the selected word line: a positive drain voltage to the drain bit line; and a positive source voltage to the source bit line, the positive source voltage being less than the positive drain voltage.