Patent ID: 6201728
Filing Date: 2001-03-13
Classification: G11C,H01L

Abstract:
A dynamic random access memory (RAM), comprising:a dynamic memory cell including an address selection MOSFET including a gate, a source, and a drain, the gate being connected to a word line, one of the source and drain being connected to one of the complementary bit lines intersecting the word line, a remaining one of the source and drain being connected to an accumulation node of an information storage capacitor;a word line selector circuit which supplies to the word line a selection level corresponding to a power supply voltage and a non-selection level corresponding to a circuit ground potential;a sense amplifier which receives a potential difference between a signal voltage which is generated due to charge dispersion of a charge appearing on said one of the bit lines as a result of a precharge operation and storage charge of the dynamic memory cell which is supplied onto the remaining one of the bit lines through a read operation and a precharge voltage of the remaining one of the bit lines, amplifying the signal voltage, and generating a bit line voltage, the bit line voltage restoring the dynamic memory cell to the original state of storage charge;a first internal voltage decreasing circuit which forms a first internal voltage having a difference substantially equal to a threshold of the address selection MOSFET relative to the power supply voltage and supplying the first internal voltage as an operating voltage on the high-level side of the sense amplifier;a second internal voltage decreasing circuit which generates a second internal voltage having a predetermined difference relative to the circuit ground potential and supplying an operating voltage on the low-level side of the sense amplifier; anda write amplifier which transfers to the complementary bit lines a write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage.