Patent ID: 6988214
Filing Date: 2006-01-17
Classification: G06F,Y02D

Abstract:
1. A computing system comprising: a processor with various power state conditions, wherein the processor performs at a selectable operating mode; a north-bridge controller initiating a processor reset signal input; a south-bridge controller providing an interface for I/O devices to the processor; means for resetting the processor; a clock; a power supply; and a logic device interfaced to the processor, the north-bridge controller, the south-bridge controller, the clock, and the power supply, whereby the logic device asserts a transition to a different operating mode on the processor while the processor is in a deep sleep power state, and upon transition back to operating power state, the clock provides a frequency and the power supply provides a voltage matched to the different operating mode, and whereby the logic device provides control signals to the processor to cause the deep sleep immediately after reset.