Patent ID: 6064608
Filing Date: 2000-05-16
Classification: G11C

Abstract:
A semiconductor memory device comprising a plurality of bit lines and a plurality of word lines, wherein:said plurality of word lines include ordinary word lines and redundant word lines, said ordinary word lines being planned to be used ordinarily from the beginning, said redundant word lines being used if any ordinary word line is judged to have a fault;said semiconductor memory device further comprising:word line replacing means for activating a specific redundant word line to replace a specifically selected word line;bit line boosting means for forcibly setting all bit lines to a supply voltage; andfurther comprising a plurality of sense amplifiers;wherein said plurality of bit lines include a plurality of bit line pairs each connected to a common sense amplifier;wherein said semiconductor memory device also includes a plurality of equalizers each furnished to each of said bit line pairs for selectively bringing into either an equalized state or a nonequalized state, said equalized state being a state in which two bit lines constituting each bit line pair are equally supplied with a voltage of a main bit line voltage line, said nonequalized state being a state in which said two bit lines are left inactive; andwherein said bit line boosting means includes test state forming means for setting said main bit line voltage line to said supply voltage while bringing said equalizers into said equalized state.