Patent ID: 6983015
Filing Date: 2006-01-03
Classification: G11B,H04N

Abstract:
1. A signal processor for splicing a compressed bitstream B 0 to a compressed bitstream A 0 , the bitstreams A 0 and B 0 comprising bits representing one or more pictures the signal processor comprising: a decoder for decoding the bitstreams A a switch coupled to the decoder for producing a spliced bitstream S, comprising data from bitstream B an encoder for re-encoding the spliced bitstream S to form a re-encoded spliced bitstream C for supply to a downstream decoder having a downstream buffer an occupancy of such a downstream buffer being dependent upon the number of bits with which pictures of the spliced bitstream S are re-encoded by the encoder, wherein the encoder is controlled over a transitional region to allocate a number of bits with which to re-encode a picture of the spliced bitstream S in the transitional region in dependence upon a target downstream buffer occupancy for the bitstream B