Patent ID: 6794915
Filing Date: 2004-09-21
Classification: H03K

Abstract:
A tri-stable CMOS latch, having first and second inputs for receiving first and second input signals, respectively, where the first and second input signals have first and second signal levels, and with combinations or the signal levels of the first and second input signals defining first, second, and third ternary logic states, said tri-stable CMOS latch, comprising:a first series circuit coupling first and second supply voltage terminals, with the first series circuit including a first PMOS transistor, including source, drain, and gate terminals coupling the first supply voltage terminal to a first node, a first biasing element coupling the first node to a second node, and a first NMOS transistor, including source, drain, and gate terminals coupling the second node to the second supply voltage terminal; a second series circuit coupling the first and second supply voltage terminals, with the second series circuit including a second PMOS transistor, including source, drain, and gate terminals coupling the first supply voltage terminal to a third node, a second biasing element coupling the third node to a fourth node, and a second NMOS transistor, including source, drain, and gate terminals coupling the fourth node to the second supply voltage terminal; a feedback network coupling the first node to the gate terminal of the second NMOS transistor, the second node to the gate terminal of the second PMOS transistor, the third node to the gate terminal of the first NMOS transistor, and the fourth node to the gate terminal of the first PMOS transistor; with said first and second biasing elements, and said MOS transistors fabricated utilizing MOSFET technology, where said first and second biasing elements are diode-connected transistors, and with the first and second biasing elements creating unequal voltage drops to bias the PMOS and NMOS transistors in one of the first and second series circuits in a higher-current state and the PMOS and NMOS transistor of the other of the first and second series circuits in a lower-current state to achieve first and second stable operating points when the first and second input signals having signal levels defining a ternary signal in the first or second topiary logic states are received and creating substantially identical voltage drops to bias the PMOS and NMOS transistors in both the first and second series circuits in triode mode to achieve a third stable operating point, where the first and second PMOS and NMOS transistors conduct substantially the same current, when the first and second input signals having signal levels defining the third ternary logic state are received.