Patent ID: 8953354
Filing Date: 2015-02-10
Classification: G06F,G11C,Y02D

Abstract:
1. A semiconductor memory device comprising: a memory portion comprising i (i is a natural number) sets each comprising j (j is a natural number of 2 or larger) arrays each comprising k (k is a natural number of 2 or larger) lines each comprising a tag field and a data field; a comparison portion comprising i comparison circuits and a selection circuit to which the i comparison circuits and the i sets are connected; and a control circuit that is connected to the selection circuit and comprises an external input terminal through which an address and/or main data specified with the address are/is input and an external output terminal through which a cache miss signal or a cache hit signal and main data is/are output, wherein the i sets and the i comparison circuits are each connected to the control circuit, wherein each of the i sets is connected to a corresponding comparison circuit among the i comparison circuits, wherein a first bit column of the address is assigned to a corresponding line among the k lines, wherein a second bit column of the address is stored in the tag field of the corresponding line, wherein the main data specified with the address is stored in the data field of the corresponding line, wherein the comparison portion compares a second bit column of a tag field of each line selected by the control circuit with a second bit column of an address input from the control circuit, and outputs a cache miss signal to the control circuit when the second bit column of the tag field and the second bit column of the address input from the control circuit do not match each other or outputs a cache hit signal and main data stored in a data field of a line to the control circuit when the second bit column of the tag field and the second bit column of the address input from the control circuit match each other, wherein, in response to an address signal input through the external input terminal or the cache miss signal input from the comparison portion, the control circuit outputs, to the memory portion, a line selection signal for selecting the lines to each of which the first bit column of the input address is assigned and an array selection signal for selecting one of the j arrays in sequence, and outputs the second bit column of the input address to the comparison circuit, wherein the cache miss signal is output through the external output terminal in response to the cache miss signal input from the comparison portion after all of the j arrays are selected with the array selection signal, and wherein the cache hit signal and the main data are output through the external output terminal in response to the cache hit signal input from the comparison portion.