Patent ID: 9030397
Filing Date: 2015-05-12
Classification: G09G

Abstract:
1. A gate driver, comprising: input terminals for inputting a CPV signal, an OE signal and an STV signal, and output terminals for outputting a CKV signal and a CKVB signal, wherein a processing circuit is connected between the input terminals and the output terminals for processing the CPV signal, the OE signal, and the STV signal such that a preset time interval greater than zero is present between the fallings edge of the CKV signal and the rising edge of the CKVB signal during one period of the CKV signal, or a preset time interval greater than zero is psesent between the rising edge of the CKV signal and the falling edge of the CKVB signal during one period of the CKVB signal, wherein the processing circuit comprises a NOT gate L the input terminal of the NOT gate L the output terminal of the NOT gate L the triggering terminal CKV of the D flip-fop D the input terminal D of the D flip-flop D the inverse output terminal the output terminal Q of the D flip-flop D the reset terminal RST of the D flip-flop D the input terminals of the first logic combination circuit C the output terminals of the first logic combination circuit C the output terminal of the first logic selection circuit L the output terminal of the second logic selection circuit L the first logic selection circuit L