Patent ID: 6448839
Filing Date: 2002-09-10
Classification: H03F

Abstract:
A compensation circuit for compensating a difference between gate-source voltages of first and second MOS transistors of an integrated circuit, the first MOS transistor having a first type of conductivity and the second MOS transistor having a second type of conductivity, the compensation circuit comprising:third and fourth MOS transistors in the integrated circuit, said third MOS transistor having the first type of conductivity and said fourth MOS transistor having the second type of conductivity; a bias circuit connected to said third and fourth MOS transistors for biasing thereof; a measurement circuit for measuring a difference between gate-source voltages of said third and fourth transistors; a current compensation circuit connected to said measurement circuit for generating a compensation current based upon the measured difference between the gate-source voltages of said third and fourth transistors; and a bias compensation circuit connected to said measurement circuit for modifying biasing of the first and second MOS transistors using the generated compensation current.