Patent ID: 8959378
Filing Date: 2015-02-17
Classification: H03K

Abstract:
1. An output timing control circuit of a semiconductor apparatus, comprising: a delay amount counter block configured to count a delay amount of an output reset pulse signal based on an external clock signal and output a first counting code, wherein the delay amount counter block is configured to control the delay amount of the output reset pulse signal depending upon a frequency of the external clock signal; an operation block configured to subtract a code value of the first counting code from a code value of a data output delay code, and output a delay control code; and a phase control block configured to control a phase of a read command signal by the number of clocks of a DLL clock signal corresponding to a code value of the delay control code, and output an output enable flag signal, wherein the delay amount counter block comprises: wherein the counter unit starts counting in response to the output reset pulse signal and ends counting in response to the third delayed signal.