Patent ID: 7341905
Filing Date: 2008-03-11
Classification: H01L

Abstract:
1. A manufacturing process for making various high-voltage bipolar/CMOS/DMOS (BCD) integrated circuits of different type using a limited number of different mask steps, said process comprising: (a) predefining a set of mask steps, each mask step comprising performing an associated activity through a separate mask distinct from the respective masks associated with the other mask steps of said set of mask steps; (b) identifying a plurality of specific sequences of mask steps from said predefined set, each specific sequence being associated with the manufacture of one or more specific integrated circuits; (c) selecting a specific integrated circuit to manufacture; (d) selecting one of said specific sequences of mask steps from said predefined set of mask steps as a selected specific sequence to manufacture said specific integrated circuit; (e) providing a starting material selected from the group consisting of: a p-type bulk substrate, and a p-type epitaxial layer over a P+ bulk substrate; and (f) performing said selected sequence of mask steps on said starting material in numerical order to make said selected specific integrated circuit; and  said predefined set of mask steps consisting essentially of: (1) a first mask step wherein an n-type implant is performed in said p-type material to form an N-well with the aid of a mask identified as an N-well mask; (2) a second mask step wherein an active region is formed by etching through an oxidation layer with the aid of a mask identified as an active region mask; (3) a third mask step wherein a p-type field region is formed by performing a p-type implant with the aid of a mask identified as a P-field mask; (4) a fourth mask step wherein a gate oxide is etched with the aid of a mask identified as a gate oxide mask; (5) a fifth mask step wherein a p-type implantation is carried out with the aid of a mask identified as a thin gate oxide mask; (6) a sixth mask step wherein polysilicon gate regions are etched with the aid of a mask identified as a polysilicon gate patterning mask; (7) a seventh mask step wherein a p-base region is formed by p-type implantation with the aid of a mask identified as a p-base mask; (8) an eighth mask step wherein a N-extended region is formed by N-type implantation with the aid of a mask identified as an N-extended region mask; (9) a ninth mask step wherein a p-top region is formed by p-type implantation with the aid of a mask identified as a P-top mask; (10) a tenth mask step wherein an N+ implantation is carried out with the aid of a mask identified as an N+ implant mask; (11) an eleventh mask step wherein a P+ implantation is carried out with the aid of a mask identified as a P+ implant mask; (12) a twelfth mask step wherein contacts are etched with the aid of a mask identified as a contact mask; (13) a thirteenth mask step wherein a deposited first metal layer is etched with the aid of a mask identified as a first metal mask; (14) a fourteenth mask step wherein vias are etched in underlying material with the aid of a mask identified as a vias mask; (15) a fifteenth mask step wherein a deposited second metal layer is etched with the aid of a mask identified as a second metal mask; and (16) a sixteenth mask step wherein a passivation layer is etched with the aid of a mask identified as a passivation mask; and wherein said selected specific sequence consists of at least said mask steps 1 to 3, 5, 6, 9 and 10 to 16.