Patent ID: 6804759
Filing Date: 2004-10-12
Classification: G06F

Abstract:
A computer system, comprising:a memory addressable using real addresses, each said real address having M+L bits, including an M-bit high-order address portion and an L-bit low order address portion; address generation logic which generates virtual addresses for computer processing operations, each said virtual address having K+L bits, including a K-bit high-order address portion and an L-bit low-order address portion; an address translation mechanism which translates virtual addresses to real addresses, said address translation mechanism translating a source virtual address to a target real address by translating the K-bit high-order portion of said source virtual address to the M-bit high-order portion of said target real address and concatenating said M-bit high-order portion of said target real address with the L-bit low-order portion of said source virtual address, the L-bit low-order portion of said target real address being identical to the L-bit low order portion of said source virtual address; a pipeline mechanism; and a pipeline address conflict mechanism which detects an address conflict between a first operation in said pipeline mechanism and a second operation in said pipeline mechanism, said pine line address conflict mechanism comparing at least part of the L-bit low-order portion of a virtual address of said first operation in said pipeline mechanism with a corresponding part of the L-bit low-order portion of an address of a second operation in said pipeline mechanism, and taking an address conflict resolution action if the at least part of the L-bit low-order portion of a virtual address of said first operation in said pipeline mechanism is identical to the corresponding part of the L-bit low-order portion of the address of said second operation in said pipeline mechanism; wherein said address conflict resolution action comprises stalling a portion of the pipeline mechanism including said first operation for a pre-determined number of cycles.