Patent ID: 8410819
Filing Date: 2013-04-02
Classification: G01R,H03K

Abstract:
1. A pulse width discriminator circuit operable to sample an input signal and produce an output signal, the pulse width discriminator circuit comprising: a first multiplexer operable to receive an input signal and load a first value in a first memory when said input signal is a first logic state, and load a second value in said first memory when said input signal is a second logic state, wherein said loaded value is stored in said first memory responsive to a clock signal; a first comparator operable to compare said stored first memory value to said second value; a second memory operable to receive said stored first memory value and, responsive to said clock signal, store said stored first memory value when said stored first memory value is greater than said second value and said input signal is said second logic state; a second comparator operable to compare said stored second memory value to a first threshold value and output a second comparator signal having a third logic state or a fourth logic state; a third comparator operable to compare said stored second memory value to a second threshold value and output a third comparator signal having a fifth logic state and a sixth logic state; and logic circuitry operable to generate an output signal indicative of a relationship between said stored second memory value and at least one of said first and second threshold values.