Patent ID: 6734110
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method for forming a patterned microelectronics layer comprising:providing a substrate having at least one conductor stud within a contact region formed therein; forming on the at least one conductor stud a first lower sub-layer and a second upper sub-layer to provide a composite etch stop layer; forming over the composite etch stop layer an inter-level metal dielectric (IMD) layer; forming over the IMD layer a photoresist mask layer pattern of an interconnection line trench pattern centered over the contact layer and transferring the pattern by etching while employing a first etching method through the IMD layer and the second upper sub-layer of the composite etch stop layer to the first lower sub-layer of the composite etch stop layer; and etching while employing a second etch method the first lower sub-layer from the trench pattern for the interconnection lines.