Patent ID: 6010956
Filing Date: 2000-01-04
Classification: H05K,Y10S,Y10T

Abstract:
A process for producing a multilayer wiring board that has plurality of conductor patterns and an interlevel dielectric layer on at least one surface of a substrate, with via holes being provided at specified sites of said interlevel dielectric layer to establish an electrical interconnection between said conductor patterns, wherein prior to the provisions of said via holes, a coating having resistance to sandblasting is formed in a pattern over the interlevel dielectric layer and then sandblasting is performed to remove the interlevel dielectric layer in selected areas to form the via holes and, thereafter, the coating having resistance to sandblasting is removed, followed by the provision of a conductive layer, and wherein the interlevel dielectric layer is formed by slightly curing a heat or photocurable electrically insulating layer, removing the slightly cured insulating layer in selected areas by sandblasting, and heat curing the remaining insulating layer.