Patent ID: 7440345
Filing Date: 2008-10-21
Classification: G11C

Abstract:
1. A data output circuit of a semiconductor memory device, the data output circuit comprising: an I/O sense amplifier unit that selectively senses and amplifies a part or all of read data received from a memory bank through a Local Input and Output (LIO) lines and outputs amplified data to a part of all of Global I/O (GIO) lines, respectively, in response to a data width selection signal; a pipeline latch unit that latches the amplified data received through a part or all of the GIO lines and outputs latched data, in response to latch control signals; and an output driver circuit unit that outputs output data in response to the latched data, wherein the number of the output data is changed according to an output data width selected by the data width selection signal; wherein when the output data width is set to the H bits, the I/O sense amplifier unit selectively senses and amplifies first to H