Patent ID: 6014333
Filing Date: 2000-01-11
Classification: G11C

Abstract:
A semiconductive memory device comprising a plurality of memory cells and writing data in a specific one of said memory cells in accordance with a write-in address, comprising:control signal producing means for producing a plurality of control signals in accordance with a synchronous signal, said control signals having phases different from one another;column selection signal producing means that receives the control signals, the column selection signal producing means being responsive to said write-in address and said control signals for producing a plurality of column selection signals, the column selection signals being dependent on the control signals input to the column selection signal producing means;latch means for latching said data as latched data in synchronism with said control signals;write bus means for supplying said latched data to said memory cells; andwrite-in means for writing said latched data on said write bus means in said specific memory cell in accordance with said column selection signals.