Patent ID: 8249253
Filing Date: 2012-08-21
Classification: G06F,G06Q,G07F,H04L

Abstract:
1. A semiconductor integrated circuit comprising: a first circuit; a second circuit; a data BUS for transmitting a plurality of data bits between the first and second circuits, wherein the plurality of data bits are N-bit data, and N is an integer; a random number generator for generating a random number in response to a clock signal; and first and second encryption/decryption circuits for changing an array of the plurality of data bits based on the random number generated by the random number generator per every clock cycle, wherein the arrays that are changed are low order K-bit data, wherein K is an integer less than N, wherein the first encryption/decryption circuit encrypts data output from the first circuit based on the random number, outputs the encrypted data to the data BUS, decrypts an encrypted data received from the second encryption/decryption circuit based on the random number, and provides the decrypted data to the first circuit, and the second encryption/decryption circuit decrypts the encrypted data received from the first encryption/decryption circuit based on the random number, provides the decrypted data to the second circuit, encrypts data output from the second circuit based on the random number, and outputs the encrypted data to the data BUS, wherein each low order K-bit data is encrypted/decrypted in response to a respective portion of a selecting signal that is based upon the random number.