Patent ID: 7973555
Filing Date: 2011-07-05
Classification: H01L,H03K

Abstract:
1. A semiconductor device comprising: a first integrated circuit die having, programmable logic, a configuration frame address bus, and a configuration frame data bus; a second integrated circuit die attached to the first integrated circuit die; wherein the first integrated circuit die has first and second sides, and the second integrated circuit die has first and second sides; an inter-chip configuration frame address bus coupling at least low order configuration frame address bits of a configuration frame address of a configuration frame between the first integrated circuit die and the second integrated circuit die, the inter-chip configuration frame address bus including a first plurality of contacts formed between the first integrated circuit die and the second integrated circuit die; and an inter-chip configuration frame data bus coupling configuration frame data of the configuration frame between the first integrated circuit die and the second integrated circuit die, the inter-chip configuration frame data bus including a second plurality of contacts formed between the first integrated circuit die and the second integrated circuit die; wherein the second integrated circuit die has programmable logic, and the programmable logic of the first integrated circuit die and the programmable logic of the second integrated circuit die are configurable according to the configuration frame address and the configuration frame data; wherein the first side of the first integrated circuit die faces the second side of the second integrated circuit die, and the first plurality of contacts and the second plurality of contacts are formed between the first side of the first integrated circuit die and the second side of the second integrated circuit die.