Patent ID: 7148537
Filing Date: 2006-12-12
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film; control insulating films which are formed on both side faces in a gate length direction of the gate electrode, respectively; charge storage layers which are formed on both the side faces in the gate length direction of the gate electrode via the control insulating films, respectively; a tunnel insulating film which is formed between the charge storage layers and the semiconductor substrate; and source/drain regions between which the gate electrode and the charge storage layers are interposed in the gate length direction, and which are formed in a surface of the semiconductor substrate, wherein fixed information is stored depending on presence/absence of an impurity diffusion layer formed in a surface portion of the semiconductor substrate directly under the tunnel insulating film, semi-fixed information is stored depending on an amount of charges in the charge storage layers, and charges which are opposite in polarity to charges in the charge storage layers are induced in a surface portion of the semiconductor substrate directly under the tunnel insulating film.