Patent ID: 9093171
Filing Date: 2015-07-28
Classification: G11C

Abstract:
1. A method of operating a nonvolatile memory device having a memory cell array of nonvolatile memory cells configured to operate as multi-level memory cells (MLC) and arranged in a memory block including a plurality of pages respectively coupled to a plurality of word lines extending across the memory cell array, the method comprising: programming N-bit data to MLC of at least a first page among the plurality of pages using a N-bit mode, wherein “N” is a natural number greater than 1 and the plurality of pages includes an un-programmed page; checking whether a threshold voltage distribution shift exists for the un-programmed page; and upon determining that the threshold voltage distribution shift exits, programming M-bit data to the MLC of the un-programmed page using a M-bit mode, where “M” is a natural number less than N.