Patent ID: 7669155
Filing Date: 2010-02-23
Classification: G06F

Abstract:
1. A method comprising: selecting an instance of an IP core instantiated in an integrated circuit design, the instance of the IP core representing a block of logic instantiated as a single unit within the integrated circuit represented by the integrated circuit design; inputting a timing constraints template for the IP core which comprises a plurality of timing constraint statements for inputs and outputs of the IP core, wherein at least one of the statements comprises a configurable variable; substituting a value for the configurable variable to produce a configured timing constraints template for the instance of the IP core; generating a set of timing constraints for the instance of the IP core using the configured timing constraints template; repeating the steps of selecting, inputting, and substituting for each IP core instance in the integrated circuit design that has a timing constraint template having one or more constraint statements with one or more configurable variables; generating a set of chip-level timing constraints for the integrated circuit, which includes, for each IP core instance, the step of generating the set of timing constraints for the instance using the respective configured timing constraints template for each instance, the set of chip-level timing constraints representing at least one timing requirement of at least one input of the IP core instance; receiving the set of chip level timing constraints and the configured timing constraints template for each of the IP core instances; generating a set of golden timing constraints for each of the IP core instances using the respective configured timing constraints template for each instance; identifying timing constraints in the set of chip level timing constraints that are associated with at least one of the IP core instances; and, replacing the identified timing constraints with corresponding timing constraints from the sets of golden timing constraints by a computer processor.