Patent ID: 8779573
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a semiconductor chip including a front surface and a back surface opposite to the front surface; electrodes formed on the front surface of the semiconductor chip; bumps including side surfaces and being formed on the electrodes; a seal resin part covering the side surfaces of the bumps and including a top surface and a back surface; a rewiring pattern formed on the top surface of said seal resin part; a solder resist layer formed on said rewiring pattern and the top surface of said seal resin part except for portions where pads for external connection terminals are formed on said rewiring pattern; and a reinforcing member embedded in said seal resin part and including a bottom surface, an upper surface, an inner peripheral side surface, and an outer peripheral side surface, said reinforcing member having a frame shape from a plan view; wherein the frame shape surrounds an entire periphery of the semiconductor chip from the plan view; wherein said bottom surface of said reinforcing member is exposed on said back surface of said seal resin part; wherein said back surface of said semiconductor chip is flush with said bottom surface of said reinforcing member and said back surface of said seal resin part, wherein the back surface of the semiconductor chip is exposed, wherein the upper surface, the inner peripheral side surface, and the outer peripheral side surface of the reinforcing member are covered by the seal resin part.