Patent ID: 7871897
Filing Date: 2011-01-18
Classification: H01L

Abstract:
1. A method of forming a device isolation structure of a semiconductor device, the method comprising: forming a mask pattern on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined; forming respective trenches in the cell region, the PMOS region, and the NMOS region by etching the semiconductor substrate using the mask pattern as a mask; sequentially forming a sidewall oxide layer and a protection layer in the trenches; removing the protection layer in the PMOS region; forming a first device isolation insulating layer on the substrate, filling the trenches; removing portions of the first device isolation insulating layer to expose the mask pattern and the trenches of the cell region and the NMOS region and leave a portion of the first device isolation insulating layer in the trench in the PMOS region; forming a silicon nitride layer on the substrate to form an oxidation-resistant layer disposed on the first device isolation insulating layer and the mask pattern in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region; forming a second device isolation insulating layer on the substrate, filling the trenches in the cell region and the NMOS region; and removing portions of the second device isolation insulating layer to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.