Patent ID: 6349360
Filing Date: 2002-02-19
Classification: G06F

Abstract:
A data processing system comprising:a processor unit; a cache; means for coupling the processor to said cache, said means including an address bus; means for determining a desired preference of ordering a retrieval of load data from a cache line of said cache utilizing a hierarchical sequence of ordering preferences established for loading data, ranging from a most desired order to a least desired order, wherein said hierarchical sequence of ordering preferences is represented via preference order bits; means, responsive to said determining means, for encoding said preference order bits according to said hierarchical sequence with a value corresponding to said most desired order; and means for issuing from said processor to said address bus a load request along with said preference order bits, wherein said cache selects a most desired order that is available from among said hierarchal sequence of ordering preferences utilizing said value of said preference order bits, and said cache retrieves and returns said load data from said cache line according to said most desired order selected.