Patent ID: 8976587
Filing Date: 2015-03-10
Classification: G11C

Abstract:
1. A method of operating a data storage system comprising a controller including a buffer memory, and a non-volatile memory including a memory cell array divided into a first region and a second region, the method comprising: receiving first page data from the buffer memory and programming the first page data to first memory cells connected to a first word line in the first region using a buffer program operation and receiving second page data from the buffer memory and programming the second page data to second memory cells connected to a second word line different from the first word line in the first region using the buffer program operation and receiving third page data from the buffer memory and programming the third page data to third memory cells connected to a third word line different from the first and second word lines in the first region using the buffer program operation; programming first multi-level memory cells connected to a fourth word line in the second region with at least two of the first page data, the second page data and the third page data stored in the first region using a first sequence of a main program operation; then programming second multi-level memory cells connected to a fifth word line in the second region using the first sequence of the main program operation; and then, programming the first multi-level memory cells with the first page data, the second page data, and the third page data stored in the first region using a second sequence of the main program operation, wherein respective threshold voltage distributions for the first multi-bit memory cells are narrowed between the first and second sequences of the main programming operation of the first multi-level memory cells except for a threshold voltage distribution of an erase state; and then programming the first multi-level memory cells with the first page data, the second page data, and the third page data stored in the first region using a third sequence of the main program operation, wherein the respective threshold voltage distributions for the first multi-level memory cells are further narrowed between the second and third sequences of the main program operation of the first multi-level memory cells except for the threshold voltage distribution of the erase state.