Patent ID: 6304111
Filing Date: 2001-10-16
Classification: H03K

Abstract:
A CMOS switch circuit having concurrently switching complementary outputs, comprising:a first inverter having an input and output, said first inverter input coupled to an input signal;first PMOS and first NMOS transistors, said first PMOS transistor source coupled to said input signal, said first NMOS transistor source coupled to a low reference voltage, said first PMOS and said first NMOS transistor gates coupled to said first inverter output, and said first PMOS and said first NMOS transistor drains coupled together and providing a first output of a first pair of complementary outputs; andsecond NMOS and second PMOS transistors, said second NMOS transistor source coupled to said first inverter output, said second PMOS transistor source coupled to a high reference voltage, said second NMOS and said second PMOS transistor gates coupled to said input signal, and said second NMOS and said second PMOS transistor drains coupled together and providing a second output of said first pair of complementary outputs;wherein said first PMOS, said first NMOS, said second NMOS, and said second PMOS transistors are sized such that said first and said second outputs of said first pair of complementary outputs are substantially concurrently switching complementary outputs in response to said input signal.