Patent ID: 7933154
Filing Date: 2011-04-26
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a plurality of wordlines; a plurality of dummy-wordlines; a plurality of bitlines; a memory cell array including a plurality of memory cells having gates respectively connected to the plurality of wordlines and from which data is read via the plurality of bitlines; a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to three, to a corresponding wordline of the plurality of wordlines in a program mode; and a second type global wordline decoder configured to selectively apply up to (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder, wherein the n different voltages include a program voltage for programming a selected cell among the plurality of memory cells, a program inhibit voltage lower than the program voltage, and at least one bias voltage lower than the program inhibit voltage, and wherein the second type global wordline decoder includes an edge global wordline decoder configured to selectively apply up to (n−1) different voltages to a corresponding wordline among the plurality of wordlines in the program mode.