Patent ID: 6737354
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A method of CMOS source/drain extension processing comprising the steps of:providing a wafer including gates for NMOS devices and PMOS devices; forming a poly oxide layer over said wafer surface covering the top and sides of the gates; implanting HV NMOS device areas; dry etching the wafer in order to remove poly oxides from top of the gates and a base on either side of the gates but leaving the poly oxide on the sides of the gates, implanting NMOS and LV NMOS device areas on either side of the gates where said poly oxide has been removed on either side of the gates, covering the NMOS and PMOS device areas with a cap oxide including the top surface of the wafer, the top of the gates and the side walls of the gates; dry etching the PMOS device areas to remove all of the cap oxide but on the side walls of the gates; and implanting the PMOS device areas with the PMOS implant spaced by the poly oxide and the cap oxide from the gates.