Patent ID: 7199567
Filing Date: 2007-04-03
Classification: G05F

Abstract:
1. A circuit of an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels is comprising: a first low-voltage PMOS pass device having its source connected to VDD voltage and to its bulk, its gate is controlled by said LDO regulator, its drain is connected to a means of controllable resistance; and said means of controllable resistance, protecting actively the voltage level at the drain of said PMOS pass device, is implemented between the drain of said first PMOS pass device and an output port of the voltage regulator, wherein said resistance controlling means comprises a differential amplifier and a second PMOS device, wherein the inputs of said amplifier comprise a reference voltage and the voltage level of the drain of said PMOS pass device, the output of said amplifier is connected to the gate of said second PMOS device, the source of said second PMOS device is connected to its bulk and to the drain of said first PMOS pass device and its drain is connected to said output port.