Patent ID: 7428164
Filing Date: 2008-09-23
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a memory array including a plurality of SRAM cells; a first MOSFET; a plurality of second MOSFETs; a first line; and a second line; wherein the first line is connected to sources of driver MOSFETs in the plurality of SRAM cells; wherein a gate of the first MOSFET is connected to a drain of the first MOSFET; wherein the source-drain paths of the first and second MOSFETs are connected between the first and second lines; and wherein the second MOSFETs are turned ON or OFF by a control signal, and wherein a part of the plurality of second MOSFETs are arranged along one end of the memory array and the other part of the plurality of second MOSFETs are arranged along another end of the memory array, wherein the another end of the memory array is opposite to the one end of the memory array.