Patent ID: 7332428
Filing Date: 2008-02-19
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a workpiece that includes a conductive region; forming a dielectric layer over the conductive region; forming a dual damascene structure within the dielectric layer, the dual damascene structure including a trench that overlies a via hole, the via hole overlying the conductive region; forming a liner along sidewalls and a lower surface of the trench and along sidewalls of the via hole, the liner also being formed over an upper surface of the conductive region, the liner having a thickness on the lower surface of the trench; removing the liner from above the upper surface of the conductive region to expose the upper surface of the conductive region without substantially decreasing the thickness of the liner on the lower surface of the trench, wherein after the removing process at least a portion of the liner remains on the lower surface of the trench and along the sidewalls of the trench and the via hole; etching a recess in the upper surface of the conductive region, wherein the recess comprises a depth of between about 10% and about 30% of a thickness of the conductive region; and forming conductive material within the dual damascene structure.