Patent ID: 6832326
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A timer adjusting system for adjusting timers of a plurality of processors in a multi-processor system, each processor including a generating circuit generating a time synchronous signal for the multi-processor system, an output circuit outputting the time synchronous signal, and an input circuit inputting the time synchronous signal, said time adjusting system comprising:a distributing circuit propagating the time synchronous signal output from the output circuit of one of the processors to all of the processors in the multi-processor system and returning the time synchronous signal to the input circuit of the one of the processors after being propagated in the multi-processor system; a measuring circuit measuring a time from when the output circuit of the one of the processors outputs the time synchronous signal to when the input circuit of the one of the processors inputs the time synchronous signal; and a synchronization circuit correcting time information of one or more timers of the plurality of processors using the measured time as a time for distributing the time synchronous signal to the plurality of processors in the multi-processor system, and synchronizing the timers of the plurality of processors.