Patent ID: 6160590
Filing Date: 2000-12-12
Classification: H04N

Abstract:
A video signal processing circuit comprising:an input processor for reducing or enlarging an input video signal in accordance with image magnification data;a buffer memory for storing the reduced or enlarged video signal; anda write control unit for controlling writing to the buffer memory by generating a write control signal in accordance with the image magnification data, the write control unit including:a calculation circuit for calculating image size data after a change in the image magnification data, anda display control unit for writing the calculated image size data as a header together with the reduced or enlarged video signal in the buffer memory, the display control unit writing a flag bit indicating the change in the image magnification data in the header for a predetermined period after the change in the image magnification data, the display control unit controlling reading of video signals from the buffer memory in accordance with the image size data, and for muting a video output for a constant period of time after detecting the flag bit.