Patent ID: 8455942
Filing Date: 2013-06-04
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an active region including a surface region and a first recess, the active region extending along a first direction, wherein the first recess is formed below the surface region; a device isolation structure provided on an edge of the active region; a gate line traversing over the surface region of the active region along a second direction orthogonal to the first direction; a second recess formed in the device isolation structure to receive a given portion of the gate line into the second recess, wherein the second recess does not overlap with the first recess; a first junction region formed in the active region beneath the first recess and on a first side of the gate line; and a second junction region formed on a second side of the gate line and above the first junction region, wherein the first and second junction regions define a vertical-type channel that extends along lateral and vertical directions.