Patent ID: 8659120
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A semiconductor device substrate comprising: a multi-layer wiring layer; a first capacitor pad which is provided on any one of an uppermost layer and a lowermost layer of the multi-layer wiring layer, and which comprises a first power supply pad connected to a power supply layer of the multi-layer wiring layer through a first via and a first ground pad connected to a ground layer of the multi-layer wiring layer through a second via; and a second capacitor pad which is provided on any one of the uppermost layer and the lowermost layer of the multi-layer wiring layer, and which comprises a second power supply pad connected to the first power supply pad through a first wire and a second ground pad connected to the first ground pad through a second wire, wherein the first wire is formed above the same layer as the first power supply pad and the second power supply pad, and the second wire is formed above the same layer as the first ground pad and the second ground pad.