Patent ID: 7539067
Filing Date: 2009-05-26
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a bit line to which a memory cell is connected; a group of bit line application voltage terminals to which different voltages are applied; and a data circuit configured to hold program data to be programmed into the memory cell and change data to be held according to a verify result from the memory cell, the data circuit is further configured to select one of the bit line application voltage terminals based on the data held therein and apply a voltage to the selected bit line application voltage terminal to the bit line, wherein the data circuit includes a first data cache circuit configured to control and determine whether the memory cell is programmed, a second data cache circuit configured to control a strength of programming the memory cell, and a selection circuit configured to select the bit line application voltage terminal, and the selection circuit selects the bit line application voltage terminal based on the control operation by the first and second data cache circuits.