Patent ID: 8549521
Filing Date: 2013-10-01
Classification: G06F

Abstract:
1. A computer-implemented method for using a processor as a virtual device, said method comprising: loading data, by a first processor, to a first location in a common memory, wherein the common memory is shared by a plurality of heterogeneous processors in a computer system; writing an instruction block, by the first processor, to a second location in the common memory, the instruction block identifying the first location and a third location in the common memory, the third location corresponding to software code that is configured to process the data; writing, by the first processor, the second location to a mailbox corresponding to a second processor from the plurality of heterogeneous processors in the computer system; retrieving the instruction block, by the second processor, from the common memory in response to the first processor writing the second location to the mailbox; storing the data, by the second processor, in a local memory corresponding to the second processor in response to retrieving the instruction block; loading the software code, by the second processor, from the third location in the common memory to the second processor's local memory; and processing the data by the second processor using the software code loaded in the second processor's local memory.