Patent ID: 7464225
Filing Date: 2008-12-09
Classification: G11C,H01L

Abstract:
1. A memory module comprising: a connector interface; a first signal path coupled to the connector interface; a first integrated circuit memory die; a first integrated circuit buffer die coupled to the first signal path, the first integrated circuit buffer die to receive control information from the first signal path, wherein the control information specifies an access to the first integrated circuit memory die such that the first integrated circuit memory die provides first data to the first integrated circuit buffer die in response to the control information; a second integrated circuit memory die; and a second integrated circuit buffer die coupled to the first signal path, the second integrated circuit buffer die to receive the control information from the first signal path, wherein the control information specifies an access to the second integrated circuit memory die such that the second integrated circuit memory die provides second data to the second integrated circuit buffer die in response to the control information.