Patent ID: 6087718
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A stacked-type semiconductor chip package comprising:a first chip;a second chip;a plurality of leads positioned between the first and second chips and having first, second and third portions;a plurality of first media connecting the leads to an interface of the first chip;a plurality of second media connecting the third portions of the leads to an interface of the second chip; anda molding body encapsulating the first and second chips, the leads, and the first and second media,wherein the first portions are positioned closer to the interface of the first chip than the second portions, and the third portions are positioned closer to the interface of the second chip than the second portions,wherein the first, second and third portions of the leads extend along different planes, andwherein the first, second and third portions of the leads respectively extend along different but parallel planes.