Patent ID: 6025116
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A process for providing an interconnection pattern in an insulating layer that extends over a surface of a semiconductor body that includes circuit elements to be interconnected, the process comprising the steps of:forming a trench in the insulator layer that is to be filled with a conductor that is to provide conductive interconnection of circuit elements in the body;providing a layer of photoresist on the insulating layer that fills the trench and forms a substantially planar surface over the insulation layer;exposing the photoresist with light in a pattern designed for forming contact holes in the trench for providing vias through the insulating layer to circuit elements in the body;developing the pattern for baring the area of the desired contact holes;etching the contact holes in the trench; andfilling the trench and the vias in the insulating layer with a conductor for providing the interconnection pattern; and wherein a thickness of the photoresist is chosen such that the photoresist has low sensitivity to light outside the trench and the thickness corresponds to a thickness where there is a maximum in the dose-to-clear swing curve of the photoresist, and the trench depth is chosen such that the photoresist has high sensitivity to light inside the trench and the photoresist thickness in the trench corresponds to a thickness where there is a minimum in said swing curve and in which the photoresist overlies an opaque substrate that is reflective, characterized in that the trench is formed to a depth D given by [(2N+1).lambda.]/4n.sub.r, where N is an integer, .lambda. is the wavelength of the exposing light, and n.sub.r is th refractive index of the photoresist.