Patent ID: 7919830
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A semiconductor device comprising: a dielectric layer formed by a shallow trench isolation process; a bipolar transistor having collector, base and emitter regions, the collector region being in lateral contact with the dielectric layer; a contact bar formed by a contact plug process over the dielectric layer, the contact bar having a longitudinal dimension and a transverse dimension, a first end of the contact bar in a longitudinal direction being in electrical contact with the emitter region, the contact bar being isolated from the base region by a dielectric sidewall spacer; a metal pad disposed over and in contact with a second end of the contact bar in the longitudinal direction; and a layer of conductive material formed between the contact bar and the dielectric layer to increase a sheet resistance of the contact bar; whereby the resistance of a ballast resistor comprising the contact bar is substantially determined by the ratio of the longitudinal dimension to the transverse dimension and the sheet resistance of the contact bar.