Patent ID: 8796852
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A 3D integrated circuit structure comprising a first chip, wherein the first chip comprises: a first substrate; a first semiconductor device formed on the first substrate and a first dielectric layer formed on both the first substrate and the first semiconductor device; a through hole, a stress passage isolation layer and a stress releasing layer which penetrate both the first substrate and the first dielectric layer, wherein the stress passage isolation layer surrounds the outside of the through hole and the stress releasing layer surrounds the outside of the stress passage isolation layer; an insulating layer formed on inside walls of the stress passage isolation layer; a conductive material layer formed within free space of the through hole, wherein the conductive material layer comprises an internal conductive via and an external stop layer; and a first interconnecting structure connecting the conductive material layer with the first semiconductor device.