Patent ID: 6927104
Filing Date: 2005-08-09
Classification: H01L

Abstract:
1. A method of forming a double-gated transistor, comprising the steps of: a) providing a substrate having an SOI structure formed thereover; the SOI structure including a lower SOI oxide layer and an upper SOI silicon layer; b) forming a top oxide layer over the SOI structure; c) forming a first top dummy layer over the top oxide layer; d) patterning: e) forming a rounded oxide layer over the exposed side walls of the patterned upper SOI silicon layer; the formation of the rounded oxide layer also rounding the patterned upper SOI silicon layer; f) removing the patterned first top dummy layer exposing the patterned top oxide layer; g) forming a second patterned dummy layer over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer; the second patterned dummy layer having an opening that defines a gate area exposing: h) etching the exposed gate area portions of the upper surface of the lower SOI oxide layer into the lower SOI oxide layer to: i) forming a conformal oxide layer over: j) forming a gate within the second patterned dummy layer opening; the gate including an upper gate above the patterned upper SOI silicon layer within the gate area and a lower gate under the upper SOI silicon layer within the gate area; and k) removing the second patterned dummy layer to form the double-gated transistor.