Patent ID: 6078519
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A semiconductor device comprising:a bit line to which a plurality of electrically erasable and writable non-volatile memory cells are coupled;a sense latch circuit and a data latch circuit coupled to the bit line; andcontrol means for latching information read from said non-volatile memory cells through the sense latch circuit in the data latch circuit and for controlling a write operation on said non-volatile memory cells based the data latched in the data latch circuit, whereinsaid control means inputs additional write data to the data latch circuit, performs a logical synthesis process based on the additional write data and data read from the memory cells to obtain data for programming non-volatile memory cells in a write state into the same write state and for programming non-volatile memory cells in an erase state into a write state which is indicated by the additional write data, latches the data obtained by the logical synthesis process in said data latch circuit and performs writing in the non-volatile memory cells in accordance with the latched data.