Patent ID: 8873305
Filing Date: 2014-10-28
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal; and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal, wherein the data transmission unit is configured to transmit the first input data to the first and the second global line drivers when the test signal is asserted, and transmit the first input data only to the first global line driver when the test signal is deasserted, and the transmission element is configured to transmit the second input data to the second global line driver when the test signal is deasserted and not transmit the first input data to the second global line driver when the test signal is asserted.