Patent ID: 7515666
Filing Date: 2009-04-07
Classification: G06F

Abstract:
1. A method, comprising: providing a coincident edge detector circuit adapted to detect coincident edges of a first clock signal and a first set of derived clock signals, a second clock signal and a second set of derived clock signals and to generate a first coincident edge detected signal and a second coincident edge detected signal when said first clock signal, said second clock signal, all clock signals of said first set of derived clock signals and all clock signals of said second set of derived clock signals have coincident edges; coupling a first clock divider network to said coincident edge detector circuit, said first clock divider network adapted to enable a change of frequency of a clock signal of said first set of derived clock signals in response to said first coincident edge detected signal; coupling a second clock divider network to said coincident edge detector circuit, said second clock divider network adapted to enable a change of frequency of a clock signal of said second set of derived clock signals in response to said second coincident edge detected signal; wherein said first divider network includes a first finite state machine adapted to generate said first set of derived clock signals from said first clock signal; wherein said second divider network includes a second finite state machine adapted to generate said second set of derived clock signals from said signal clock signal; wherein said first finite state machine comprises a first set of state logic circuits coupled to a first a multi-bit register; wherein said second finite state machine comprises a second set of state logic circuits coupled to a second multi-bit register; wherein said first clock divider network includes a first clock tree coupled between said first clock signal and said first multi-bit register; and wherein said second clock divider network includes a second clock tree coupled between said second clock signal and said second multi-bit register; wherein said coincident edge detector comprises N clock domains, N first flip-flops, 2N−1 second flip-flops, 2N−1 third flip-flops, N AND gates, and a CE signal AND gate having N inputs, said N at least 2, and wherein for I=1, 2, . . . , N: said first flip-flop I has a first clock input coupled to a clock tree signal I and a data input is coupled to a signal P, said clock tree signal I being an output of a clock tree I whose input is a clock signal I; for J=1, 2, . . . , N subject to J not equal to I, said second flip-flop J has a data input coupled to an inverted and delayed clock signal J and a second clock input is coupled to said clock signal I, said third flip-flop J having a data input coupled to an un-inverted and un-delayed clock signal J and a third clock input coupled to a delayed clock signal I; each input of said AND gate I is coupled to an output of said first flip-flop I, to outputs of said second flip-flops J corresponding to said flip-flops I, and to outputs of said third flip flops J corresponding to said flip-flop I, an output of each AND gate I being a signal indicating all said N clock domains have coincident rising edges or indicating all said N clock domains have coincident falling edges; and each input of said CE signal AND gate is coupled to a different CE signal of N CE signals, said CE signal I indicating an edge of said clock tree signal I occurring in one cycle of said clock signal I.