Patent ID: 7461237
Filing Date: 2008-12-02
Classification: G06F

Abstract:
1. A method for improving performance in a processor which supports prefetching of cache lines, comprising: fetching a first cache line into in a fetch buffer; prefetching a second cache line, which immediately follows the first cache line, into the fetch buffer; scanning the first cache line to determine a location for a target instruction for a control transfer instruction in the first cache line and a position for a corresponding delay slot for the control transfer instruction; if the control transfer instruction in the first cache line has a target instruction which is located in the second cache line, determining if the control transfer instruction is located at the end of the first cache line so that the corresponding delay slot for the control transfer instruction is located at the beginning of the second cache line; if so, suppressing a subsequent prefetch for a target cache line containing the target instruction because the target instruction is located in the second cache line which has already been prefetched; and if the target instruction for the control transfer instruction is not located in the first cache line and is not located in the second cache line, determining if the control transfer instruction is located at the end of the first cache line;