Patent ID: 6269387
Filing Date: 2001-07-31
Classification: G06F

Abstract:
An apparatus that performs an arithmetic operation on two N-nary operands, comprising:a 1-of-P first input that receives the first operand;a 1-of-Q second input that receives the second operand;a sum/HPG logic, coupled to said first input and to said second input, that performs an arithmetic operation on one grouping of two or more bits of the first operand and on one grouping of two or more bits of the second operand, to produce an intermediate result and an HPG indicator;a block HPG logic, coupled to said sum/HPG logic, that receives said HPG indicator and produces a block HPG indicator; andan increment logic, coupled to said block HPG logic, that receives said intermediate result and said block HPG indicator and produces a 1-of-R final result and a 1-of-T carry indicator.