Patent ID: 8191057
Filing Date: 2012-05-29
Classification: G06F

Abstract:
1. A method for aggressive safe load speculation for a compiler in a computer system, the method consisting of: building a control flow graph; identifying both countable and non-countable loops; gathering a set of candidate loops for load speculation; for each candidate loop in the set of candidate loops gathered for load speculation performing: performing low-level instruction scheduling on the generated unrolled main loop, wherein a loop with an early exit is a candidate loop for load speculation and has stride-one accesses to memory, for a leading load with a data element size, that is aligned with its data alignment, that is bigger than the data element size, there are a number of subsequent data accesses equal to a quotient of the data alignment and the data element size, minus one, which are safe for load speculation; for a loop with early exit and with unit-stride accesses of a contiguous storage, performing: