Patent ID: 6346723
Filing Date: 2002-02-12
Classification: H01L

Abstract:
A semiconductor memory device having a memory cell area and a peripheral circuit area, comprising:a semiconductor substrate, said semiconductor substrate being divided into: a memory cell area provided with a plurality of memory cells; a peripheral circuit area provided with a plurality of circuits for controlling the operation of said memory cells, said peripheral circuit area being provided around said memory cell area; and a boundary area provided between said memory cell area and said peripheral circuit area; a first wiring layer disposed in said memory cell area on said semiconductor substrate; a first inter-layer insulating film disposed on said semiconductor substrate, for covering said first wiring layer; a second wiring layer formed in said memory cell area on said first inter-layer insulating film; a second inter-layer insulating film formed on said first inter-layer insulating film, for covering said second wiring layer; first a signal wiring disposed in said boundary area on said second inter-layer insulating film and connected to at least one of said circuits, said first signal layer running substantially in a first general direction; a second signal wiring disposed in said boundary area and connected to at least one of said circuits, said second signal layer running substantially in a second general direction; a first dummy wiring formed of the same layer as said first wiring layer, said first dummy wiring disposed below said first signal wiring and running substantially in the first general direction; and a second dummy wiring formed of the same layer as said second wiring layer, said second dummy wiring disposed below said second signal wiring and running substantially in the second general direction.