Patent ID: 8359438
Filing Date: 2013-01-22
Classification: G06F

Abstract:
1. A method for operating a memory system, the memory system comprising a plurality of memory banks of one or more single-port memory devices, a cache memory, and a tag memory, each memory bank having a plurality of storage locations for storing data and being accessible for no more than one memory access operation during a clock cycle, the cache memory having a plurality of storage locations corresponding to the storage locations in each of the plurality of memory banks, the method comprising: receiving a write request and a read request during each of a plurality of successive clock cycles, the write request including a write address and write data, the read request including a read address; during a clock cycle immediately preceding a memory access clock cycle, determining a write bank in response to the write address; during the clock cycle immediately preceding the memory access clock cycle, determining a read bank in response to the read address; during the clock cycle immediately preceding the memory access clock cycle, determining if a bank conflict exists, a bank conflict existing if the read bank and the write bank are the same as each other; during the clock cycle immediately preceding the memory access clock cycle, determining in response to the read address and the tag memory if data corresponding to the read address exists in the cache memory; during the clock cycle immediately preceding the memory access clock cycle, determining in response to the write address and the tag memory if data corresponding to the write address exists in the cache memory; performing a memory access operation comprising one of a write operation and a read operation upon a storage location corresponding to one of the write address and the read address, the memory access operation being performed upon a storage location in the cache memory if either a bank conflict exists or data corresponding to one of the read address and write address exists in the cache memory, wherein performing a memory access operation occurs during the memory access clock cycle; and updating the tag memory to indicate data exists in a storage location in the cache memory corresponding to the write address if a write operation is performed upon the storage location in the cache memory corresponding to the write address and if it is determined that data corresponding to the write address does not exist in the cache memory prior to the write operation; wherein a write operation is performed upon a storage location corresponding to the write address during the memory access clock cycle and a read operation is performed upon a storage location corresponding to the read address during the memory access clock cycle; and wherein if data corresponding to the read address exists in the cache memory and if data corresponding to the write address exists in the cache memory then the read operation is performed upon a storage location in the cache memory corresponding to the read address during the memory access clock cycle and the write operation is performed upon a storage location in the write bank corresponding to the write address during the memory access clock cycle.