Patent ID: 6411563
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a logic circuit for effecting an arithmetic operation on externally applied data and producing a control signal corresponding to one of a plurality of operation modes in accordance with externally applied instructions; a control circuit for receiving said control signal from said logic circuit, and producing one of memory control signal groups respectively corresponding to said plurality of operation modes, each of said memory control signal groups having a plurality of memory control signals; a memory circuit for transmitting storage data to and from said logic circuit, and storing said storage data, said memory circuit including: a memory cell array having a plurality of memory cells for storing said storage data, a plurality of control signal input node groups capable of receiving said memory control signal groups, respectively, and a plurality of decoder circuits, respectively provided for said plurality of control signal input node groups, each capable of decoding the memory control signal group applied to a corresponding one of said control signal input node groups and producing an internal control signal for said memory cell array; and a plurality of interconnections for transmitting said memory control signal group sent from said control circuit to one of said plurality of control signal input node groups.