Patent ID: 9201792
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A processor comprising: a requester to send a memory request, the memory request having a memory address of a memory that stores requested data; a record keeping structure to receive the memory request; circuitry to determine a local last accessor of the memory address having a copy of the requested data up to date with the memory, wherein the local last accessor is within a local domain that the requester belongs to; circuitry to send a cache probe to the local last accessor; and circuitry to retrieve a latest value of the requested data from the local last accessor to the requester, wherein the processor is a multi-core processor, and the requester is a core and the local last accessor is another core of the multi-core processor, wherein the record keeping structure is a tag directory belonging to a hierarchy of tag directories, the tag directory includes a tag entry associated with a cache line in the local last accessor storing the latest value of the requested data, the tag entry includes a domain state field that indicates whether the local domain has at least a copy of a particular cache line, and wherein the domain state field includes at least one of: