Patent ID: 7391087
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. A device comprising: a substrate having a first conductivity type region, wherein the substrate has inwardly concaved recesses having inflection points; a gate dielectric formed on the first conductivity region of the substrate between the recesses; a gate electrode formed on said gate dielectric, said gate electrode having a lower portion formed directly on said gate dielectric; a pair of sidewall spacers formed along laterally opposite sidewalls of said gate electrode; and a first silicon or silicon alloy layer in the inwardly concaved recesses that forms a pair of inwardly concaved source/drain regions of a second conductivity type having extensions at the inflection points on opposite sides of said gate electrode, wherein the pair of inwardly concaved source/drain regions have an abrupt junction between the first conductivity type region and the first silicon or silicon alloy layer filling the inwardly concaved recesses at the inflection points, wherein the pair of the inwardly concaved source/drain regions have extensions at the inflection points determined by the inwardly concaved recesses creating metallurgical inflection points directly beneath said lower portion of said gate electrode formed directly on said gate dielectric layer, and directly define a first channel region having a first metallurgical channel length directly beneath said lower portion of said gate electrode in said first conductivity type region, and a second channel region having a second metallurgical length between said metallurgical inflection points, wherein said first metallurgical channel length directly beneath said lower portion of said gate electrode is larger than said second metallurgical channel length between said metallurgical inflection points.