Patent ID: 6621536
Filing Date: 2003-09-16
Classification: G02F

Abstract:
A matrix wiring substrate comprising:a substrate having a principal surface; a plurality of first bus lines formed in a first wiring layer above the principal surface of said substrate and extending in a row direction of the principal surface; a first bundling line formed in the first wiring layer and extending in a column direction of the principal surface, said first bundling line being connected to one end portion of each of said first bus lines; a plurality of second bus lines formed in a second wiring layer different from the first wiring line above the principal surface of said substrate and extending in the column direction of the principal surface, each of said second bus lines crossing each of said first bus lines; a second bundling line formed in the second wiring layer and extending in the row direction of the principal surface, said second bundling line being connected to one end portion of each of said second bus lines; a first insulating film disposed between the first wiring layer and the second wiring layer to electrically insulate the first and second wiring layers; a first auxiliary line formed in the first wiring layer along said second bundling line; and an interlayer connection member for electrically connecting said first auxiliary line to said second bundling line or said second bus lines, wherein each of said first bus lines is cut at a point near a connection portion between each of said first bus lines and said first bundling line, and each of said second bus lines is cut at a point near a connection portion between each of said second bus lines and said second bundling line, wherein a portion of said first insulating film is disposed between said second bundling line and said first auxiliary line or between said second bus lines and said first auxiliary line, wherein said first auxiliary line overlaps said second bundling line, and wherein the interlayer connection member electrically connects said first auxiliary line and said second bundling line or said first auxiliary line and said second bus lines by penetrating said first insulating film.