Patent ID: 6011420
Filing Date: 2000-01-04
Classification: H01L

Abstract:
A structure for protecting input pads of a semiconductor device from electrostatic discharge (ESD), comprising:a substrate of a first conductivity type;a first ohmic contact of said first conductivity type formed in said substrate;a drain region of a second conductivity type opposite said first conductivity type formed in said substrate;a source region of said second conductivity type formed in said substrate, said source and drain regions being spaced apart to define a channel region therebetween;a well region of said second conductivity type formed in said substrate spaced from said source, channel, and drain regions, said well region including a second ohmic contact region of said second conductivity type formed in said well and a junction region of said first conductivity type formed in said well;a layer of dielectric material disposed over said substrate, said layer including a gate dielectric region overlying said channel region;a control gate formed over said layer of dielectric material, including a portion overlying said channel region;said first ohmic contact, said control gate, and said source region being connected to a negative power supply bus (V.sub.SS);an ESD bus isolated from a positive power supply bus (V.sub.DD) connected to said drain region, said junction region, and said second ohmic contact; and,a first diode having an anode coupled to one of the input pads and a cathode coupled to said ESD bus.