Patent ID: 6101516
Filing Date: 2000-08-08
Classification: G06F

Abstract:
An apparatus comprising:a combinatorial logic network operative on each bit position of fractional parts of first and second floating point operands, operand A and operand B, to determine trigger or borrow positions that qualify as a potential true normalization shift point for a mantissa portion of a calculated result of the two operands, the logic network including:a first detector to produce a first shift vector for an exponent difference corresponding to the exponent of the operand A being equal to the exponent of the operand B;a second detector to produce a second shift vector for an exponent difference corresponding to the exponent of the operand A being greater than the exponent of the operand B; anda third detector producing a third shift vector for an exponent difference corresponding to the exponent of the operand B being greater than the exponent of the operand A; anda multiplexor selecting one of the first, second and third shift vectors in accordance with an exponent difference between the operands.