Patent ID: 6645842
Filing Date: 2003-11-11
Classification: H01L

Abstract:
A method of arranging a buffer cell on a multi-layer wiring structured semiconductor circuit, comprising:forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; forming a wiring path in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at a first arbitrary point in the 45 degrees direction or the 135 degrees direction without going through the other layer; and inserting a buffer cell at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.