Patent ID: 6528734
Filing Date: 2003-03-04
Classification: H01L,H05K,Y10T

Abstract:
A packaged semiconductor device comprising a packaging substrate having a core substrate having core wiring layers formed on opposite surfaces thereof, respectively, and a plurality of core via holes in said core substrate for mutually electrically connecting said core wiring layers, and upper and lower buildup layers formed on an upper surface and a lower surface of said core substrate, respectively, and each having a wiring layer on a surface opposite to said core substrate, a semiconductor device chip mounted on mounting pads formed on said upper buildup layer, and externally connecting electrodes formed on said lower buildup layer, wherein the position of said core via holes in said core substrate is standardized, and said mounting pads formed on said upper buildup layer are located to coincide with a plurality of connection terminals of said semiconductor device chip.