Patent ID: 8452926
Filing Date: 2013-05-28
Classification: G06F

Abstract:
1. A digital system, comprising a memory interposer module configured to be coupled between a processor module and a memory module, wherein the processor module comprises a first and a second processor, the memory interposer module comprising: a memory controller configured to couple to the memory module; a first memory emulator configured to couple to the first processor, wherein: an arbiter coupled between the memory controller and the first memory emulator; and a second memory emulator couple to the second processor and connected to the arbiter, wherein wherein the memory interposer module is located on a ball grid array substrate, and wherein the second processor is further located on the ball grid array substrate, and wherein the first memory emulator is coupled to a connector comprising a plurality of balls in the ball grid array substrate, and wherein the memory interposer module is coupled via the ball grid array connector to the first processor, and is further situated between the first processor and the memory module in a same vertical stack.