Patent ID: 6516391
Filing Date: 2003-02-04
Classification: G06F

Abstract:
A processor system containing a memory for constituting a main memory, a plurality of processor nodes, and a network for mutually coupling said plurality of processor nodes to said memory, each of said plural processor nodes including at least one processor unit which contains a cache for temporarily storing a portion of a memory block of said main memory;wherein each of said processor nodes is comprised of: first means for specifying a memory containing an address to be accessed as a target node in response to such a fact that a main memory access request is produced in a processor unit contained in the own processor node, and for issuing a first sort of command to said target node; and second means for judging as to whether or not there is such a possibility that the memory block containing the address to be access is stored into a cache of another processor node in response to said main memory access request; for issuing a second sort of command to said target node when said judgment result is â€œno possibilityâ€ ; and for distributing said second sort of command to all of the processor nodes other than the own processor node so as to execute a cache united control when said judgment result is â€œpossibilityâ€ ; and wherein said memory is accessed when said first sort of command is received and thereafter said second sort of command is received.