Patent ID: 6141746
Filing Date: 2000-10-31
Classification: G06F

Abstract:
An information processor comprising:a plurality of executing units each operating according to each of a plurality of instructions including a source operand to execute the instructions simultaneously;a controller controlling an operation of each of said executing units according to each of said instructions; anda register file outputting register contents specified by said controller to said plurality of executing units,wherein said controller comprises:a decoder receiving an instruction directed to each of said executing units and decoding the instruction;a selector selecting an executing unit to which an instruction is to be dispatched from said plurality of executing units according to a result of the decoding by said decoder and outputting information related to the selected executing unit to said register file; anda dispatch inhibiting unit inhibiting dispatch of an instruction to any of said plurality of executing units according to the decoded instructions by said decoder and the selected executing unit by said selector,wherein said dispatch inhibiting unit does not inhibit, when a header first instruction of said plurality of instructions is using a particular source operand, and if a following second instruction is using said particular source operand identical to that for said first instruction or does not use any source operand, dispatch of said second instruction according, to a result of decoding by said decoder as well as to a result of selection by said selector, but inhibits the dispatch of said second instruction in a case other than the cases described above, and in addition, said dispatch inhibiting unit does not inhibit the dispatch of said second instruction regardless of whether said second uses any source operand or not said first instruction does not use said particular source operand.