Patent ID: 8995164
Filing Date: 2015-03-31
Classification: G11C,H01L

Abstract:
1. A read-only memory (ROM) in an integrated circuit, comprising: an array of memory cells arranged in rows and columns; a plurality of word lines, each associated with a row of memory cells in the array; and a plurality of bit lines, arranged in groups consisting of first, second, and third bit lines, each group associated with a column of memory cells in the array; a sense amplifier, associated with one or more columns of memory cells in the array; and a plurality of column select circuits, each associated with one of the columns, for coupling first and second pairs of the first, second and third bit lines associated with the column to the sense amplifier; wherein each of the memory cells comprises: a transistor having source and drain regions disposed on opposing sides of one of the word lines associated with the row of the memory cell; and at most one connection between the drain region of the transistor and the first, second, and third bit lines associated with the column of the memory cell.