Patent ID: 7895457
Filing Date: 2011-02-22
Classification: G06F,Y02D

Abstract:
1. A memory system comprising: power saving arbitrator responsive to an oscillator clock having a first clock rate, said power saving arbitrator includes, an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate; a host command counter responsive to the oscillator clock and the active enable signal and operative to generate an output reflective of the number of oscillator clock cycles during which a host command has not been detected; and a threshold comparator responsive to the counter output and further responsive to a threshold value and operative to compare the threshold value and the counter output to determine whether or not the predetermined period of time exceeds the threshold value and to generate a stand-by enable signal reflecting the same.