Patent ID: 9158330
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. An apparatus embedded in a processing system configured to compensate for data skew for multiple memory devices with each memory device including a plurality of data lines of varying lengths respectively coupled to the data lines of at least one other memory device, the apparatus comprising: delay circuitry that includes a plurality of delay devices each being individually adjustable to produce an individual delay for each data line with each data line including branches of different lengths leading to different memory devices; and memory control circuitry coupled to the delay circuitry and configured to determine, for each data line, an individual delay based on an optimized critical window, the optimized critical window being based on multiple chip select signals and further configured to adjust a delay of each individual data line based on the optimized critical window, wherein the optimized critical window is a smallest window of a plurality of possible windows based on the multiple chip select signals, the optimized critical window being increased in duration to a possible maximum at the expense of a duration of at least one other window for another chip select signal having a longer duration.