Patent ID: 7746142
Filing Date: 2010-06-29
Classification: G06F,H03K

Abstract:
1. A skew compensation circuit for minimizing clock skew between two power domains in a circuit, comprising: an input for receiving a clock signal; a first power domain clock circuit coupled to the input for outputting a first clock pulse, and having a first power supply voltage; a second power domain clock circuit coupled to the input for outputting a second clock pulse, and having a second power supply voltage lower than the first power supply voltage; a selectable delay circuit for providing one of a plurality of delays between the input and the first clock pulses, responsive to a control input; a skew comparator for determining the skew between the first clock pulse and the second clock pulse; a pulse delay circuit for outputting a plurality of delayed pulses from the first clock pulse; a skew sampling circuit for sampling the output of the skew comparator using the plurality of delayed pulses and for outputting a plurality of samples; and control logic for outputting the control input to the selectable delay circuit after determining from the samples a delay amount for the first clock pulse that will minimize the clock skew.