Patent ID: 8451026
Filing Date: 2013-05-28
Classification: G06F,H01L

Abstract:
1. A method of generating a layout of an integrated circuit, comprising the steps of: forming a plurality of rows within which to provide functional components of the integrated circuit, each row having a predetermined row height; providing a standard cell library, each standard cell within the standard cell library defining a corresponding functional component, each standard cell having an abutment area comprising a height dictated by the row height, and a width; populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row; for each row, providing a routing track running along that row; within each row, arranging for each standard cell in that row to have a voltage connection area that is aligned with said routing track, but with each standard cell in that row having said voltage connection area configured so as not to extend across the entire width of the standard cell; providing a plurality of voltage supplies; and within each row, for each standard cell in said row, connecting the voltage connection area of that standard cell to one of the plurality of voltage supplies having regard to a voltage requirement of the corresponding functional component defined by that standard cell, and independent of the voltage supply to which each adjacent standard cell in the row is connected.