Patent ID: 6961887
Filing Date: 2005-11-01
Classification: G01R

Abstract:
1. A method, comprising the steps of: completing a LASAR fault simulation on electronic circuitry resulting in output, including a fault dictionary and pattern files, being in a first computer language; converting the output into a second computer language, readable by an L200 electronic circuitry tester system, by: processing the output without the fault dictionary to generate files representing pin states for each pin of the electronic circuitry; generating a pin map of the electronic circuitry and appending any pin groups; running a program to generate new pattern files and a new pin map, from the pin map, pattern files, and files representing pin states, that are readable in the second computer language; processing the fault dictionary from the fault simulation to reside in a run-time test program directory; inputting a minimum scope level of analysis of the circuitry into the processed fault dictionary; generating a fault retriever file usable by the L200 electronic circuitry tester system; and transporting the processed fault dictionary, new pattern files, new pin maps, and fault retriever file to the L200 electronic circuitry tester system, accommodating run-time fault analysis.