Patent ID: 7280582
Filing Date: 2007-10-09
Classification: H04B

Abstract:
1. An apparatus for correlating a first sequence of data with a local code sequence, comprising: a first sub-chip delay circuit that receives the first sequence of data and outputs a second sequence of data that is a version of the first sequence delayed by a predetermined fraction of a chip; a second sub-chip delay circuit connected to receive the second sequence of data and output a third sequence of data that is a version of the second sequence delayed by a predetermined fraction of a chip; a first despreader circuit that receives the local code sequence and the first sequence of data and outputs a first despread data; a second despreader circuit that receives the local code sequence and the second sequence of data and outputs a second despread data; a third despreader circuit that receives the local code sequence and the third sequence of data and outputs a third despread data; a first summing circuit for receiving said first and said second despread data; and a second summing circuit for receiving the second and the third despread data.