Patent ID: 8910171
Filing Date: 2014-12-09
Classification: G06F,H04L

Abstract:
1. A network processor having a plurality of packet classification processors and at least one shared memory, wherein one of the plurality of the packet classification processors generates one or more tasks corresponding to each of a plurality of received packets to be distributed to others of the plurality of the packet classification processors, each of the packet classification processors comprising: a scheduler configured to generate one or more contexts corresponding to tasks received by the packet classification processor distributed by the one of the plurality of packet classification processors; a multi-thread instruction engine configured to process one or more threads of instructions, each thread of instructions corresponding to a context received from the scheduler; a function bus interface configured to transmit the contexts within the multi-thread instruction engine and the scheduler, queue the contexts so that newer context wait for oldest context to be executed, and determine if a function call of the context is a terminating function call that causes the packet classification processor to end context processing and generate an output task for subsequent processing in the network processor; and a thread status manager in communication with the scheduler configured to maintain: wherein the scheduler is further configured to schedule instructions for processing by the multi-thread instruction engine in an order in which the threads were started.