Patent ID: 6744428
Filing Date: 2004-06-01
Classification: G09G,H04N

Abstract:
An apparatus comprising:a first circuit configured to generate an address signal in response to (i) a first ramp signal, (ii) a second ramp signal, and (iii) a format signal, wherein said first circuit comprises an address arithmetic circuit configured to receive said first and second ramp signals and generate said address signal; and a second circuit configured to generate said first and second ramp signals in response to a one or more control signals; a first ramp generator configured to generate said first ramp signal; and a second ramp generator configured to generate said second ramp signal, wherein (i) said address signal supports a raster format when said format signal is in a first state and supports a macroblock format when said format signal is in a second state, (ii) said first ramp signal controls horizontal scanning and (iii) said second ramp signal controls vertical scanning.