Patent ID: 7346874
Filing Date: 2008-03-18
Classification: G06F,Y02P

Abstract:
1. A method for modeling effects of fabrication parameter variations in signal timing analysis of a resistance/capacitance circuit based on Elmore Delay based delay variance calculation in an electronic design automation tool for integrated circuit design, the method comprising: receiving resistance variation parameter values characteristic of variation in resistance values associated with the circuit due to a fabrication process, each resistance variation parameter value associated with at least one layer of the fabrication process; receiving capacitance variation parameter values characteristic of variation in capacitance values associated with the circuit due to the fabrication process, each capacitance variation parameter value associated with at least one layer of the fabrication process; composing a square matrix (T) of Elmore-Delay-based products of resistance multiplied by sums of downstream capacitances for each path associated with each resistor of the circuit, the matrix comprising a number of rows and columns corresponding to a number of layers associated with resistance and capacitance variations due to the fabrication process, wherein each column includes the Elmore-Delay-based products corresponding to resistors in one or more layers associated with a resistance variation parameter value and each row includes the sums of downstream capacitances associated with capacitors in one or more layers associated with a capacitance variation parameter value; and determining a delay variance based on the matrix T and the resistance and capacitance variation parameter values.