Patent ID: 6376352
Filing Date: 2002-04-23
Classification: G01R,H01L

Abstract:
A method of forming a membrane having compliant studs thereon for use in conjunction with a semiconductor carrier for electrically coupling die pads of a semiconductor device to said compliant studs, which comprises the steps of:(a) providing a semiconductor carrier and an electrically insulating substrate; (b) forming an interconnect pattern on said electrically insulating substrate; (c) forming at least one stud coupled to said interconnect pattern and over said substrate, each of said at least one stud being formed by the steps of: (i) forming at least one gold ball on said interconnect pattern; (ii) coating the portion of said at least one gold ball most remote from said interconnect pattern with an electrically conductive compliant material; and (d) placing said substrate with said interconnect pattern and at least one gold ball in said semiconductor carrier.