Patent ID: 7535741
Filing Date: 2009-05-19
Classification: G05F,H01L,H02M

Abstract:
1. A semiconductor device comprising: (a) a first chip mounting section having a first main surface and a second main surface disposed on the opposite side thereof; (b) a first external terminal which is disposed around the first chip mounting section and supplies a first power supply potential; (c) a second external terminal which is disposed around the first chip mounting section and supplies a second power supply potential lower than the first power supply potential; (d) output external terminals formed integrally with the first chip mounting section; (e) a first semiconductor chip mounted over a first main surface of the first chip mounting section and having a source-to-drain path connected in series between the first external terminal and the output external terminals; (f) a second semiconductor chip mounted over the first main surface of the first chip mounting section and having a source-to-drain path connected in series between the output external terminals and the second external terminal; (g) a first lead plate which electrically connects electrodes formed in a main surface of the first semiconductor chip and the first external terminal to each other; (h) a second lead plate which electrically connects electrodes formed in a main surface of the second semiconductor chip and the second external terminal to each other; (i) an encapsulator which seals the first semiconductor chip and the second semiconductor chip, and (j) a radiating fin attached to a part of each of the first and second lead plates through an insulative adhesive, wherein the part of each of the first and second lead plates is exposed from the encapsulator, wherein a p channel first field effect transistor is formed in the first semiconductor chip, wherein an n channel second field effect transistor is formed in the second semiconductor chip, wherein the first field effect transistor comprises: a semiconductor substrate having a first surface and a second surface; a trench formed from the first surface of the semiconductor substrate to the second surface thereof; a gate insulating film formed over an inner wall surface of the trench; a gate electrode formed over the gate insulating film; p type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode; and n type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions, wherein the second field effect transistor comprises: a semiconductor substrate having a first surface and a second surface; a trench formed from the first surface of the semiconductor substrate to the second surface thereof; a gate insulating film formed over an inner wall surface of the trench; a gate electrode formed over the gate insulating film; n type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode; p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and a drain semiconductor region formed in the second surface, and wherein the first semiconductor chip is disposed closer to the first external terminal than a center of the first chip mounting section.