Patent ID: 7872493
Filing Date: 2011-01-18
Classification: G11C,H03K

Abstract:
1. A device comprising: an output circuit; a replica circuit of the output circuit, which has an output node; a comparison circuit that compares an electric potential of the output node of the replica circuit with a predetermined potential to output a result of the comparison as a comparator signal; a counter circuit that updates a counter value thereof based on the comparator signal, outputs an impedance adjustment signal to adjust impedances of the output circuit and the replica circuit; wherein the counter circuit stops updating the counter value on a completion of a calibration operation; and a counter update clock gate circuit that supplies a counter update clock signal to the counter circuit and a determination circuit that determines the completion of the calibration operation and output a hit determination signal to the counter up date clock gate circuit, and wherein when the calibration operation is completed, the determination circuit activates the hit determination signal to inactivate the counter update clock signal and the counter circuit stops updating the counter value in response to an inactivation of the counter update clock signal.