Patent ID: 6614375
Filing Date: 2003-09-02
Classification: H03M

Abstract:
A low-noise, sigma-delta analog-to-digital converter having a differential reference voltage input, a first differential input, and a first and second clock signal input, comprising:a passive filter circuit having a first differential output, the passive filter circuit coupled to receive the differential reference voltage input; a differential multiplexer coupled to receive the first clock signal, the differential multiplexer having a second differential input and second and third differential output, the second differential input coupled to receive the first differential output of the passive filter circuit, each second differential output having an inherent parasitic capacitance, the differential multiplexer including a mode of operation whereby the parasitic capacitance of the second differential output discharges every clock cycle; a sigma-delta integrator coupled to receive the first differential input, the first and second clock signals, and the second differential output of the differential multiplexer; and a comparator coupled to the output of the sigma-delta integrator to provide a decision signal, the differential multiplexer coupled to receive the decision signal.