Patent ID: 6813188
Filing Date: 2004-11-02
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising: a memory cell including a pair of impurity regions formed spaced apart from each other on a main surface of a semiconductor substrate, a first insulating film formed on a region between said pair of impurity regions on said semiconductor substrate, a second insulating film formed on said first insulating film for storing charges as information, a third insulating film formed on said second insulating film, and an electrode portion formed on said third insulating film for controlling shift of charges relative to said second insulating film; anda voltage applying circuit supplying to said electrode portion a prescribed voltage, in an information write operation, for storing charges approximately at the center of said second insulating film in a direction of thickness; wherein said voltage applying circuit includes a voltage selecting circuit pre-selecting said prescribed voltage depending on the relationship between thickness of said first insulating film and thickness of said third insulating film.