Patent ID: 7078349
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A method of fabricating a self-aligned conductive region to active region structure comprising: providing a semiconductor region within a substrate extending to a surface, forming a gate insulator layer over said semiconductor region; forming, sequentially, a conductive layer, an insulator layer and a hard mask layer over said gate insulator layer, patterning said gate insulator layer, said conductive layer, said insulator layer and said hard mask layer to form a plurality of tiered parallel stripes; forming a spacer insulator layer over the sidewalls of said parallel stripes; forming trenches in said semiconductor region between said parallel stripes; growing an insulator liner layer over sides of said trenches and underlying said spacer insulator, and depositing an insulator filler layer so that said trenches and the space between said parallel stripes are filled with said insulator filler layer, planarizing so that said insulator filler layer above top of said insulator layer is removed and said hard mask is removed; etching said filler layer so that it just fills said trenches; removing said insulator layer and said insulator spacer layer; patterning said conductive layer to form separated conductive regions.