Patent ID: 7996658
Filing Date: 2011-08-09
Classification: G06F

Abstract:
1. A processor system comprising: a processor which executes a plurality of tasks by switching to one another; a first memory which stores a task ID identifying a task executed in the processor; a second memory which stores an evaluation ID identifying a task of a measurement target; a third memory which stores a mask value; a matching unit coupled to the first, second and third memories; and a counter which is coupled to the matching unit, and which counts in response to a signal output from the matching unit, wherein the task ID and the evaluation ID include a task group ID, an individual ID and a resource field, respectively, wherein the task group ID comprises an identifier indicating a collection of tasks, and specifies a task group to which the task corresponding to the task ID or the evaluation ID belongs, wherein the individual ID distinguishes each task in the task group corresponding to the task ID or the evaluation ID, wherein the resource field comprises an identifier indicating a particular hardware resource being used by the task corresponding to the task ID or the evaluation ID, and wherein the matching unit determines each evaluation range of the task ID and the evaluation ID based on the mask value, and compares a portion of the task ID corresponding to the determined evaluation range with a portion of the evaluation ID corresponding to the determined evaluation range to generate the signal.