Patent ID: 8156393
Filing Date: 2012-04-10
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a first memory in which data can be electrically written/erased; a nonvolatile second memory which is random access memory and counts the number of erase operations of the first memory and retains the number of erase operations and a maximum number of erase operations of the first memory; a controller which is connected to be given a self-diagnosis command from an outside through a connection interface, and which retrieves the number of erase operations and the maximum number of erase operations from the second memory based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the outside through the connection interface; and a time counter which measures a total time required for writing data in the first memory, wherein the nonvolatile second memory retains the number of erase operations, the maximum number of erase operations, and the time required for writing the data, the controller outputs the number of erase operations, the maximum number of erase operations, and the time required for writing the data based on the self-diagnosis command, and the time counter measures total time required for a store operation of the first memory and a verify operation for verifying whether data has been written, when the store operation and the verify operation are repeated.