Patent ID: 6720789
Filing Date: 2004-04-13
Classification: G01R

Abstract:
A test system for testing devices under test (DUTs) located on a product wafer, said test system comprising:a support plate having a surface with a simulated wafer being arranged thereon, said simulated wafer including a load plate and a plurality of load cells retained in a spaced array interposed between said load plate and said support plate surface; a wafer probe arrangement including a device interface board mounting a plurality of probes being arrayed in opposed relationship to said load cells facing towards said load plate; and movable structure for imparting movement to said support plate for biasing said simulated wafer into contact with said plurality of probes to determine an optimum overdrive for a specific product which results in optimized probe force, said movable structure implementing said optimum overdrive during testing of said DUTs on said product wafer, whereby said probe force for each said probe of the plurality of probes responsive to pressure exerted between said respective load cells and probes is indicative of the plurality of the wafer surface at the final overdrive position for said support plate.