Patent ID: 8031525
Filing Date: 2011-10-04
Classification: G11C

Abstract:
1. A flash memory device comprising: a voltage generator circuit configured to generate a program voltage, and a pass voltage; a plurality of planes configured to perform a program operation in response to the program voltage, and the pass voltage and to verify the program operation; and a control logic configured to control the plurality of planes in response to program operation verification results from the plurality of planes relating to program-passed planes and program-failed planes, wherein the control logic controls the plurality of planes to prevent the program and pass voltages from being applied to program passed planes without preventing the program and pass voltages from being applied to program-failed planes, and wherein each of the plurality of planes comprises: a memory cell array including a plurality of memory blocks each having memory cells arranged in rows and columns; a row selector circuit configured to select a memory block and a row of the selected memory block; and a pass/fail check circuit configured to check whether memory cells in the selected row are programmed normally and to provide a verification result to the control logic, wherein the row selector circuit is configured to prevent the program voltage and the pass voltage under control of the control logic.