Patent ID: 6445016
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A silicon-on-insulator (SOI) transistor formed from a wafer having a layer of silicon disposed on an insulating layer, the insulating layer disposed on a semiconductor substrate, comprising a source and a drain having a body disposed therebetween, the source, the drain and the body being formed from the layer of silicon and each of the source and the drain having an extension region and a deep doped region, the extension regions having a junction depth, a gate electrode is disposed over the body region and defines a channel extending from the extension of the source to the extension of the drain, the source being implanted with germanium to form an area of silicon-germanium adjacent a junction of the deep doped region of the source and the body and extending from the source extension junction depth to the insulating layer, the area of silicon-germanium in the source forming a hetero junction along the junction of the deep doped region of the source and the body.