Patent ID: 7414284
Filing Date: 2008-08-19
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device including a memory cell transistor and a select gate transistor, comprising: a silicon substrate; a gate insulator formed on the silicon substrate; a first gate electrode of the memory cell transistor, including a floating gate electrode having a first polysilicon layer formed on the gate insulator, an inter-gate insulator formed on the floating gate electrode, and a control gate electrode having a second polysilicon layer formed on the inter-gate insulator and a first metal layer formed on the second polysilicon layer; and a second gate electrode of the select gate transistor, located adjacent to the first gate electrode, including a third polysilicon layer formed on the gate insulator and a second metal layer formed on the third polysilicon layer, wherein a height of an upper surface of the first polysilicon layer is same as a height of an upper surface of the third polysilicon layer, and a height of an upper surface of the first metal layer is same as a height of an upper surface of the second metal layer, relative to an upper surface of the silicon substrate, a width of the second polysilicon layer is same as a width of the first metal layer, and a width of the third polysilicon layer is same as a width of the second metal layer.