Patent ID: 6452269
Filing Date: 2002-09-17
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit comprising:an internal circuit, including a memory cell array, supplied with a first power supply voltage; an input circuit capturing a signal for executing a write/read operation of said memory cell array; an output circuit outputting data read from said memory cell array; and a package, having 100 pins arranged on four side surfaces, enclosing said input circuit, said internal circuit and said output circuit, wherein a second power supply voltage is supplied to each of a fourth pin, an eleventh pin, a twentieth pin, a twenty-seventh pin, a fifty-fourth pin, a sixty-first pin, a seventieth pin and a seventy-seventh pin among said 100 pins, and said input circuit and said output circuit operate with supply of said second power supply voltage from different pins among said fourth pin, said eleventh pin, said twentieth pin, said twenty-seventh pin, said fifty-fourth pin, said sixty-first pin, said seventieth pin and said seventy-seventh pin.