Patent ID: 8487681
Filing Date: 2013-07-16
Classification: H03K

Abstract:
1. A dual-trigger low-energy flip-flop circuit, comprising: a trigger sub-circuit that includes only a single clock-activated transistor and is configured to arm either a first trigger signal or a second trigger signal when an input signal to the dual-trigger low-energy flip-flop circuit is at a different level than a level of an output signal generated by the dual-trigger low-energy flip-flop circuit; and a latch sub-circuit that includes a second clock-activated transistor and is configured to change the level of the output signal when either the first trigger signal or the second trigger signal is armed and a clock signal transitions from a first level to a second level and maintains the level of the output signal when neither the first trigger signal or the second trigger signal is armed, wherein the latch sub-circuit further comprises a third clock-activated transistor that is coupled to a first isolation transistor and a second isolation transistor.