Patent ID: 7941696
Filing Date: 2011-05-10
Classification: G06F

Abstract:
1. A FLASH memory based solid state storage system comprising: (a) a printed circuit board; (b) a plurality of FLASH memory chips mounted to the printed circuit board, each FLASH memory chip including a plurality of FLASH memory cells arranged to store a plurality of pages of digital data and a chip-level communications bus interface capable of receiving and sending digital data to be stored in, and retrieved from, FLASH memory cells within the FLASH memory chip; and (c) a system controller mounted to the printed circuit board, the system controller including a plurality of system communications bus interfaces, each system communications bus interface being coupled by a system communications bus to one or more chip-level communications bus interfaces such that the system controller can provide digital data to and retrieve digital data from FLASH memory cells within the one or more FLASH memory chips, the system controller further including an external communications bus interface capable of receiving digital data to be stored within the storage system; (d) wherein the system controller is configured to store data received over the external communications bus in the plurality of FLASH memory chips in the form of page stripes and auxiliary protection stripes, each page stripe comprising a plurality of pages of information stored in the FLASH memory chips, each page of information being stored in a FLASH memory chip that is different from each of the FLASH memory chips in which the other pages of information within the page stripe are stored, the plurality of pages making up each page stripe including: (i) a plurality of data pages, and (ii) at least one data protection page containing data protection information that may be used to reconstruct data stored in a data page within the page stripe that becomes corrupted or unavailable; (e) wherein the system controller is configured such that each auxiliary protection stripe includes: (i) a plurality of data pages, and (ii) at least one auxiliary protection page containing auxiliary data protection information that may be used to reconstruct data stored in a data page within the auxiliary protection stripe that becomes corrupted or unavailable; and (f) wherein each data page of a plurality of data pages is within both a page stripe and an auxiliary protection stripe; and (g) wherein the system controller is configured such that the number of data pages within each page stripe can vary, the system controller configured to: (i) maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that include memory locations previously used to store data in the page stripes, the page stripes each having a first number of pages, the memory locations being currently available for storage of data; and (ii) dynamically assemble the page stripes using the information contained in the one or more buffers, wherein the number of pages to be included in the page stripes is based on the information contained in the one or more buffers and the number of pages varies from the first number of pages to a second number of pages, where the first number is different from the second number, and where at least one dynamically assembled page stripe has the second number of pages and includes a storage location previously used to store data in a page stripe having the first number of pages.