Patent ID: 6381659
Filing Date: 2002-04-30
Classification: G06F

Abstract:
A first-in-first-out (FIFO) buffer control circuit to buffer data that is bi-directionally transferred between first and second asynchronous data handling systems, comprising:a FIFO buffer for buffering data between the first and second asynchronous systems; a read-pointer address register that stores a read-pointer address associated with a location in the FIFO buffer where data is read; a write-pointer address register that stores a write-pointer address associated with a location in the FIFO buffer where data is written; a bank of FIFO address registers including: (i) a first pair of FIFO buffer address registers coupled with the write-pointer address register for capturing and saving beginning and ending write-pointer addresses associated with a first data block written to the FIFO buffer, and (ii) a second pair of FIFO buffer address registers coupled with the write-pointer address register for capturing and storing beginning and ending write-pointer addresses associated with a second data block written to the FIFO buffer, wherein the bank of FIFO address registers captures and saves the beginning and ending write-pointer addresses held in the write pointer address register that are associated with segments of the first and second data blocks residing within the FIFO buffer register at the same instant in time; and control means for enabling the FIFO buffer register to accommodate said segments of said first and second data blocks without overlap.