Patent ID: 6107828
Filing Date: 2000-08-22
Classification: H03K

Abstract:
A programmable buffer circuit comprising:a first input terminal;a logical gate circuit having a second input terminal, a third input terminal and a first output terminal, said second input terminal being connected to said first input terminal;a selective signal generating circuit for supplying two kinds of selective signals in logical level to said third input terminal;a tri-state inverter circuit having a fourth input terminal and a second output terminal, said fourth input terminal being connected to said first output terminal;a tri-state buffer circuit having a fifth input terminal and a third output terminal, said fifth input terminal being connected to said first output terminal; anda fourth output terminal connected to said second output terminal and said third output terminal;wherein said tri-state buffer circuit further comprises:an inverter circuit having a fifth output terminal, an input terminal of said inverter circuit being said fifth input terminal;a first transistor;a first switch element;a second switch element;a second transistor; anda couple of power supply terminals,said first transistor, said first switch element, said second switch element and said second transistor respectively being connected in series between said couple of power supply terminals,a gate of said first transistor and a gate of said second transistor being connected to an output terminal of said inverter circuit, andsaid third output terminal being connected to a connection point between said first switch element and said second switch element.