Patent ID: 6128692
Filing Date: 2000-10-03
Classification: G11C,H03K

Abstract:
Electrical circuit apparatus comprising:a plurality of memory cells connectable in a substantially linear series through which data can be made to flow unidirectionally from each memory cell to a next successive memory cell in the series, wherein each memory cell has a storage capacity of one bit of binary data;first addressing circuitry configured to selectively address each of the memory cells to prevent data from flowing from an addressed memory cell to a next successive memory cell;an intermediate memory circuit connectable at an intermediate location in the series of memory cells, wherein the intermediate memory circuit comprises a plurality of memory subcircuits; andsecond addressing circuitry configured to selectively address each of the memory subcircuits to cause an addressed memory subcircuit to receive data that the intermediate memory circuit receives from a preceding memory cell in the series.