Patent ID: 7583544
Filing Date: 2009-09-01
Classification: G06F

Abstract:
1. A data reading circuit, comprising: a first register, for receiving a first data signal and for sampling the first data signal according to the first edges of a first predetermined signal to generate a second data signal; a second register, coupled to the first register, for sampling the second data signal according to the second edges of a second predetermined signal to generate a third data signal; a first selector, coupled to the second register, for selecting one of the second and third data signals as a fourth data signal according to the phases of the first and second predetermined signals; a second selector, coupled to the first selector, for selecting one of the fourth and a fifth data signals as a sixth data signal according to an enable signal; and a third register, coupled to the second selector, for sampling the sixth data signal according to the first edges of the second predetermined signal to generate the fifth data signal.