Patent ID: 8076956
Filing Date: 2011-12-13
Classification: H03K

Abstract:
1. A component of a wireless device, the component operable to be placed in (i) a normal operating state or (ii) a low power state, the component comprising: combinational logic configured to generate a value while the component operates in the normal operating state, wherein the combinational logic is powered up when the component is in the normal operating state and powered down when the component is in the low power state; a memory element configured to maintain the value generated by the combinational logic in response to the component being placed in the low power state and the combinational logic being powered down, wherein the memory element includes a first transistor stack, the first transistor stack including wherein, in response to a change in state of the value generated by the combinational logic, the third transistor and the fourth transistor respectively receiving the clock signal and the inverted version of the clock signal operate to prevent a direct electrical path between power and ground within the first transistor stack; an inverter coupled to the first transistor stack; and a second transistor stack coupled to the first transistor stack, wherein the inverter and the second transistor stack are configured to maintain the value generated by the combinational logic in response to the component being placed in the low power state.