Patent ID: 6253332
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A voltage lowering apparatus located on a removable circuit card, where said removable circuit card assembly also has a bus interface connector configured to operably and removably connect to a bus on a motherboard and where said motherboard provides a regular clock pulse available on said bus, comprising:a first resistor having a first input and a first output;a second resistor having a second input and a second output;a first transmission line having a first input and a first output, where said first input is operably connected to said bus interface connector and to said regular clock pulse and where said first output is operably connected to said first input of said first resistor and where said first output of said first resistor is operably connected to a junction point, and where said second input of said second resistor is operably connected to said junction point and said second output of said second resistor is operably connected to ground;a second transmission line having a second input and a second output where said second input of said second transmission line is operably connected to said junction point, and where said second output of said second transmission line is operably connected to devices on said removable circuit card.