Patent ID: 6326266
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A method for manufacturing a virtual ground EPROM memory device having a matrix of virtual ground floating gate EPROM memory cells, the EPROM memory device including selection transistors and addressing circuitry having P-channel and N-channel MOS transistors, said method comprising the steps of:forming a plurality of N-wells in at least a first portion of a substrate in order to accommodate the P-channel transistors;defining active areas for transistors by using a screening mask and growing an isolation layer through apertures in the screening mask;forming the virtual ground EPROM memory cell matrix in a second portion of the substrate; andforming a plurality of continuous bit lines that extend across the virtual ground EPROM memory cell matrix as discrete parallel continuous stripes,wherein the screening mask does not have apertures over the second portion of the substrate.