Patent ID: 8595658
Filing Date: 2013-11-26
Classification: G06F,H03K

Abstract:
1. Clock distribution circuitry for a structured application-specific integrated circuit (“structured ASIC”), the clock distribution circuitry comprising: a deterministic clock distribution portion; and configurable clock distribution portions, where each of the configurable clock distribution portions is associated with a predetermined location of a set of predetermined locations that are spaced from one another on the structured ASIC and is custom-configurable by a user to distribute a clock signal received from the deterministic clock distribution portion at the associated predetermined location to clock utilization circuitry within a predetermined area adjacent to the associated predetermined location, and where configurable logic elements (LEs) on the predetermined area of the structured ASIC are custom-configurable by the user to selectively: provide clock distribution buffer circuitry for routing the clock signal from the deterministic clock circuitry to the clock utilization circuitry within the predetermined area through a configurable clock distribution conductor, wherein the configurable clock distribution conductor is located within the predetermined area, or provide logic functions when not providing the clock distribution buffer circuitry.