Patent ID: 8575681
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a substrate having a major surface; a conductive layer provided on the major surface of the substrate; a stacked body including a plurality of insulating layers alternately stacked with a plurality of electrode layers on the conductive layer; a memory film including a charge storage film provided on a side wall of a hole made to pierce the stacked body; and a channel body including a pair of columnar portions and a linking portion, the pair of columnar portions being provided on an inner side of the memory film inside the hole, the linking portion being provided inside the conductive layer to link lower ends of the pair of columnar portions, the electrode layers being tilted with respect to the major surface of the substrate, the columnar portions of the channel body and the memory film being configured to pierce the tilted portion of the electrode layers.