Patent ID: 6635923
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A double-gated/double channel MOSFET structure comprising:a bottom Si-containing layer; an insulating region present on said bottom Si-containing layer; a top silicon layer having a vertical thickness on the order of about 80 nm or less present on a portion of said insulating region, wherein a portion of said top silicon layer functions as vertical channel regions and other portions of said top silicon layer abutting said vertical channel regions contain diffusion regions therein, said vertical channel regions are located on each side of said top silicon layer and said vertical channel regions have a length of less than about 0.05 &mgr;m; a hard mask formed on top of said top silicon layer containing said vertical channel regions; and a gate region surrounding said vertical channel regions, wherein said gate region includes at least a gate oxide located on each side of said top silicon layer.