Patent ID: 7952572
Filing Date: 2011-05-31
Classification: G09G

Abstract:
1. A source driver, comprising: a hold memory block storing digital image data; a first pre-decoding unit receiving lower bits of the digital image data from the memory block, wherein the first pre-decoding unit generates a plurality of first data codes from the lower bits and a plurality of first enable signals from the first data codes, and generates each first enable signal by performing a logical operation on each distinct pair of consecutive bits of the first data codes; a second pre-decoding unit receiving upper bits of the digital image data from the memory block, wherein the lower bits are distinct from the upper bits, wherein the second decoding unit generates a plurality of second data codes from the upper bits and a plurality of second enable signals from the second data codes, and generates each second enable signal by performing a logical operation on each distinct pair of consecutive bits of the second data codes; a plurality of first level shifters receiving the first data codes and the first enable signals, wherein each first level shifter receives a corresponding one of the distinct pairs of bits of the first data codes and the first enable signal derived from the corresponding pair and performs a level shifting on the received bits using the received first enable signal to generate a first level shifted data code; a plurality of second level shifters receiving the second data codes and the second enable signals, wherein each second level shifter receives a corresponding one of the distinct pairs of bits of the second data codes and the second enable signal derived from the corresponding pair and performs a level shifting on the received bits using the received second enable signal to generate a second level shifted data code; and a digital-to-analog converter (DAC) block receiving the first level shifted data codes, the second level shifted data codes and a plurality of grayscale voltages and outputting one of the grayscale voltages based on the first level shifted data codes and the second level shifted data codes.