Patent ID: 6214656
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:forming isolation areas on a semiconductor substrate surrounding and electrically isolating device areas;providing a gate oxide layer in said device areas;depositing a polysilicon layer overlying said gate oxide layer and said isolation areas;implanting ions into said polysilicon layer to define a surface channel dual gate wherein an NMOS channel area is formed in one of said device areas and wherein a PMOS channel area is formed in an adjoining one of said device areas and wherein the junction where said NMOS channel area meets said PMOS channel area forms a CMOS gate area;depositing a hard mask layer overlying said polysilicon layer;patterning said hard mask layer and said polysilicon layer to form an NMOS gate in a portion of said NMOS channel area, a PMOS gate in a portion of said PMOS channel area and a CMOS gate in said CMOS gate area wherein said CMOS gate comprises an NMOS gate adjacent to and adjoining a PMOS gate;forming spacers on the sidewalls of said gates;forming source and drain regions within said semiconductor substrate associated with said gates;thereafter removing said hard mask layer overlying said CMOS gate and overlying one of said NMOS or PMOS gates where a contact is to be made to said gate while leaving said hard mask layer over non-gate areas of said NMOS and PMOS channel areas;depositing a metal layer overlying said substrate and annealing said substrate wherein said metal layer is transformed into a metal silicide layer where it is not underlaid by said hard mask layer;removing said metal layer that is not transformed into said metal silicide layer leaving said metal silicide layer overlying said CMOS gate, overlying said gate to which a contact is to be made, and overlying said source and drain regions;depositing an insulating layer over the surface of said semiconductor substrate;forming a self-aligned contact opening through said insulating layer to one of said source and drain regions;forming a contact opening through said insulating layer to said metal silicide layer overlying said gate where said contact is to be made;depositing a conducting layer over said semiconductor substrate and within said self-aligned contact opening and within said contact opening and patterning said conducting layer to complete fabrication of said integrated circuit device.