Patent ID: 6222408
Filing Date: 2001-04-24
Classification: H03K

Abstract:
A synchronous delay circuit comprising:a clock driver;a synchronous delay circuit output;a first delay circuit array including a plurality of stages, an input at each of said stages, and an output at each of said stages, allowing a pulse or a pulse edge to progress during a constant time period;a second delay circuit array including a plurality of stages, an input at each of said stages, and an output at each of said stages, interconnected with said first delay circuit array, and allowing the pulse or the pulse edge to pass by a length in proportion to a length by which the pulse or the pulse edge has progressed in said first delay circuit array; anda circuit means interconnected with said first delay circuit array for storing and reproducing the period in which the clock pulse progresses in the clock driver; anda selector circuit interconnected with an input buffer, the clock driver, and an output of the second delay circuit.