Patent ID: 6265930
Filing Date: 2001-07-24
Classification: G06F,H03L,H04J,H04L

Abstract:
A clock selector circuit for selecting an output clock signal from a multiplicity of input clock signals, comprising:(i) means for asserting and deasserting a respective one of a multiplicity of hold signals in response to the assertion and deassertion respectively of a common hold signal and the assertion of a respective one of the input clock signals;(ii) means for selecting one of said input clock signals in response to the state of a selection signal;(iii) means for selecting one of said multiplicity of hold signals in response to the state of said selection signal; and(iv) gating means for asserting an output signal in response to the assertion of either or both of the selected hold signal and the selected input clock signal;wherein the assertion of the common hold signal precedes a change in state of the selection signal and endures at least until all the hold signals in said multiplicity of hold signals have been asserted and said change in state of the selection signal has occurred.