Patent ID: 6800890
Filing Date: 2004-10-05
Classification: G11C,H01L

Abstract:
An integrated circuit comprising:a plurality of memory calls coupled in series to form a series group, wherein a memory cell comprises a transistor having a gate and first and second diffusion regions, a capacitor coupled to the transistor in parallel, the capacitor includes first, second, and third electrodes separated by first and second capacitor dielectric layers to form first and second subcapacitors, the first subcapacitor being located below the second subcapacitor, wherein the second electrode is a common electrode of the first and second subcapacitors, and one of the first, second and third electrodes is coupled to the second diffusion region and the other two of the first, second, and third electrodes are coupled to the first diffusion region; a first encapsulation layer covering sidewalls of the first subcapacitor and a top surface of a first interlevel dielectric layer having a top planar surface located substantially in plane with a bottom surface of a bottom electrode of the first subcapacitor; and a second encapsulation layer covering sidewalls of the second subcapacitor and a top surface of a second interlevel dielectric layer having a top surface substantially in plane with a top surface of the common electrode of the first and second subcapacitors.