Patent ID: 7057431
Filing Date: 2006-06-06
Classification: H03K,H03L

Abstract:
1. A digital DLL apparatus for correcting a duty cycle, comprising: a buffer for receiving an external clock signal in order to output a first internal clock signal activated at an edge of the external clock signal; a delay line unit for receiving the first internal clock signal from the buffer, a first detection signal and a second detection signal to output a first delayed internal clock signal by delaying the first internal clock signal according to the first detection signal, and a second delayed internal clock signal by delaying the first internal clock signal according to the second detection signal; a duty error controller for receiving the first and a second delayed internal clock signals to output a first duty controlled clock signal and second duty controlled clock signal by shifting each edge of the first and second delayed internal clock signals in order to match; a first delay model unit for receiving the first duty controlled clock signal which travels to a data input/output pin to output a first compensated clock signal by compensating for a difference between the external clock signal and the first duty controlled clock signal; a first direct phase detector for receiving the external clock signal, generating the first detection signal by comparing the external clock signal and the first compensated clock signal and outputting the first detection signal to the delay line unit; a second delay model unit for receiving the second duty controlled clock signal which travels to a data input/output pin to output a second compensated clock signal by compensating for a difference between the external clock signal and the second duty controlled clock signal; and a second direct phase detector for generating the second detection signal by comparing the external clock signal and the second compensate clock signal to output the second detection signal to delay line unit.