Patent ID: 8921196
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A method of fabricating an array of vertical bipolar junction transistors, the method comprising: forming an array of base contact pillars and an array of emitter contact pillars with a lithographic technique having a minimum lithographical resolution F, the base contact pillars and the emitter contact pillars each having a width below the minimum lithographical resolution F, the forming of the array of base contact pillars and the array of the emitter contact pillars including forming a first set of shallow trench isolation regions extending at least to a first doped region and forming a second set of shallow trench isolation regions which do not extend to the first doped region, the first doped region being a common collector, the second set of shallow trench isolation regions being formed substantially perpendicular to the first set of shallow trench isolation regions; and forming a storage element above the array of base contact pillars and the array of emitter contact pillars.