Patent ID: 7426631
Filing Date: 2008-09-16
Classification: G06F

Abstract:
1. A data processor for processing instructions, the data processor comprising: a branch execution unit to predict directions of branch instructions; an instruction fetch unit connected to an instruction cache to fetch instructions for processing by a plurality of execution units; an address table containing addresses for every instruction of the data processor for storing addresses for use by both the instruction fetch unit and the branch execution unit, the address table being connected to both the instruction fetch unit and the branch execution unit, wherein the address table is adapted to store a plurality of entries each capable of storing multiple instructions, each entry of the address table being adapted to store a base address and a base instruction tag; wherein in response to a request to add an instruction to a current entry of the address table, the branch execution unit creates a new entry in the address table in the event a branch in the current entry is predicted to be taken and stores the instruction in the new entry; wherein the instruction fetch unit accesses the address table to determine an instruction address of an instruction having a first instruction tag based on a base address and base instruction tag of an entry of the address table associated with the first instruction tag; and wherein the branch execution unit accesses the address table to determine an address of a branch instruction having a second instruction tag based on a base address and base instruction tag of an entry of the address table associated with the second instruction tag.