Patent ID: 6589885
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A semiconductor device including a transistor and a memory capacitor connected to the transistor comprising:a semiconductor base having a principal surface; source and drain regions of the transistor formed in the principal surface of the semiconductor base; an insulating layer formed over the principal surface of the semiconductor base and having a contact hole aligned over either the source region or the drain region, a polycrystalline silicon layer formed over the insulating layer within the contact hole, wherein the polycrystalline silicon layer includes a lower polycrystalline silicon layer and an upper polycrystalline silicon layer, wherein the upper polycrystalline silicon layer is formed directly on the lower polycrystalline silicon layer, wherein a concentration of a conductive impurity in the upper polycrystalline silicon layer is higher than that in the lower polycrystalline silicon layer, wherein the lower polycrystalline silicon layer fills the contact hole and is located between the upper polycrystalline silicon layer and the insulating layer, and wherein edges of the lower polycrystalline silicon layer are substantially correspondent with edges of the upper polycrystalline silicon layer in a parallel direction with a channel between the source region and the drain region.