Patent ID: 8352531
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. A floating point processor, comprising: a normalizer result bus that contains an intermediate calculated result; and a rounder that has an increment data path and a non-increment data path, wherein the intermediate calculated result is provided to an input of each of the increment data path and the non-increment data path, wherein upon an occurrence of a corner case, the non-increment data path forces a fraction portion of the intermediate calculated result to all ones or all zeros and the increment data path does not force a fraction portion of the intermediate calculated result to all ones or all zeros; the non-increment data path comprises a leading zero correction multiplexer that selects between bits the increment data path comprises a fraction incrementer that adds 1 to a least significant bit position, the fraction incrementer outputting a second rounder input of a first set of bits