Patent ID: 6680659
Filing Date: 2004-01-20
Classification: H01L

Abstract:
A method of manufacturing an interconnect system for conveying signals between first and second nodes within an integrated circuit and an external node outside the integrated circuit, the first and second nodes each comprising capacitive impedance, the method comprising the steps of:a. providing a first conductive path comprising inductive impedance extending from the first node to the external node; b. providing a second conductive path comprising inductive impedance extending from the second node to the first node; c. selecting a characteristic of a frequency response of the interconnect system between the external node and one of the first and second nodes; d. evaluating a function of the impedances of the first and second conductive paths and the first and second nodes, to calculate a magnitude of a capacitance at the external node which will substantially optimize the frequency response characteristic selected at step c; and e. adjusting the capacitance at the external node to approximate the magnitude calculated at step d.