Patent ID: 8402449
Filing Date: 2013-03-19
Classification: G06F

Abstract:
1. A method for automatically assigning placement for one or more pipeline registers within hardware description language (HDL) code generated from a program specification such that the HDL code for the program specification executes over a plurality of pipeline stages, the method comprising: building at least one intermediate representation (IR) of the program specification, the at least one IR having a plurality of interconnected nodes that define a plurality of paths through the at least one IR, each node having an execution latency; storing the IR in a memory; scheduling an execution order of the nodes of the at least one IR, wherein one or more nodes of the at least one IR are scheduled to execute in a given pipeline stage, the scheduling including repeatedly applying a scheduling algorithm bounded by an input time threshold producing a final scheduled execution order of the nodes of the at least one IR; specifying one or more pipeline registers for insertion along one or more paths of the at least one IR between pipeline stages; providing the final scheduled execution order and the specification of pipeline register insertions; and generating the HDL code based on the final scheduled execution order and the specification of pipeline register insertions, the generated HDL code indicating the inserted pipeline registers.