Patent ID: 6851033
Filing Date: 2005-02-01
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a processor operable to execute instructions upon data items associated with a memory, said memory being arranged to store data delimited by address boundaries, said processor having a plurality of pipeline stages, including a memory access generation stage operable to generate from a memory instruction a memory access for a data item whose address is derived from one or more operands of said memory instruction, and in the event that said address indicates that said data item consists of data on both sides of one of said address boundaries, operable to generate at least two memory accesses to be output sequentially from said memory access generation stage to access said data item at addresses on both sides of said address boundary; prediction logic associated with said memory access generation stage and arranged to receive said one or more operands, to predict from said one or more operands whether said at least two memory accesses may be required to access said data item, and to generate a prediction signal indicative of said prediction; and control logic responsive to said prediction signal indicating that at least two memory accesses may be required to prevent at least said memory access generation stage of said processor from receiving signals from a preceding pipeline stage whilst said at least two memory accesses are being generated.