Patent ID: 6570781
Filing Date: 2003-05-27
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising:a plurality of bit line pairs, each bit line pair including a first bit line and a second bit line; a plurality of activatable word lines, at most one word line being activated at a time; a plurality of memory cells; and a plurality of multiplexers, the first bit line and the second bit line within each bit line pair being aligned with each other in an end-to-end arrangement; and the first bit lines being arranged substantially in parallel with each other and consecutively adjacent to one another; and the second bit lines being arranged substantially in parallel with each other and consecutively adjacent to one another; and each word line being associated with either all of the first bit lines or all of the second bit lines, such that a first array is formed by the first bit lines and their associated word lines and a second array is formed by the second bit lines and their associated word lines; and one of the plurality of memory cells being associated with every other bit line along each word line, such that for each word line, each bit line that is not associated with one of the plurality of memory cells acts as a shield between bit lines that are each associated with one of the plurality of memory cells; and each of the plurality of multiplexers being in communication with a voltage source input and with two adjacent bit lines within one of the two arrays; and wherein when a word line is activated, each of the plurality of multiplexers is configured to output a difference between signal levels of the two adjacent bit lines in communication with that multiplexer.