Patent ID: 8488384
Filing Date: 2013-07-16
Classification: G11C

Abstract:
1. An address decoder in a non-volatile memory device, comprising: a plurality of memory blocks including memory cells disposed corresponding to word lines and bit lines; a plurality of memory block selectors configured to select a memory block in the plurality of the memory blocks according to an address; an I/O circuit connected to the plurality of the memory blocks through the bit lines and configured to store data to be programmed in at least one memory cell, or to store data read from at least one memory cell; and a control logic configure to control the plurality of memory block selectors and the I/O circuit, wherein each of the memory block selectors comprises: a pull-up circuit configured to apply a high voltage to a block selection line in response to an enable signal for selecting a memory block; a pull-down circuit connected between a first terminal and a second terminal and configured to apply a well voltage of the second terminal to the block selection line in response to a complementary signal of the enable signal for unselecting a memory block; and a plurality of block selection transistors configured to electrically connect between selection lines and word lines of a memory block to be selected according to a voltage of the block selection line, wherein each of the block selection transistors includes a gate connected to the block selection line, and wherein when a negative voltage is applied to at least one of the word lines, the well voltage applied to a well of the address decoder is a negative well voltage applied to block selection lines of memory block selectors corresponding to unselected memory blocks, and the high voltage is applied to a block selection line corresponding to the selected memory block.