Patent ID: 6535451
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory array areas placed along a first direction; and a plurality of sense amplifier areas placed alternately to said plurality of memory array areas, wherein said plurality of memory array areas respectively have a plurality of bit lines provided along the first direction, a plurality of word lines provided along a second direction intersecting the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word lines intersect, wherein sense amplifiers, each of which receives a first signal from one of a pair of bit lines extending to one of the memory array areas on one side adjacent to the respective sense amplifier areas and receives a second signal from the other of the pair of bit lines extending to another of the memory array areas on an opposite side adjacent to the respective sense amplifier areas, are provided within said respective sense amplifier areas, and wherein respective word-line selecting timings with respect to two of the memory array areas, separated from each other with two or more different ones of the memory array areas interposed therebetween, are independently controlled.