Patent ID: 6157218
Filing Date: 2000-12-05
Classification: G01R,H03D

Abstract:
A phase-frequency detector with no dead zone which is used in a phase-locked loop comprising:(a) a first detecting means including a clock signal receiving terminal to receive reference clock signal input from the outside, a reset signal receiving terminal to receive reset signal which is capable of resetting the first detecting means, and an output terminal to output a control signal (up signal);(b) a second detecting means including a clock signal receiving terminal to receive the clock signal whose frequency within the interior of the phase-locked loop has been divided, a reset signal receiving terminal to receive reset terminal which is capable of resetting the second detecting means, and an output terminal to output a control signal (dn signal);(c) a first control logic circuit for receiving the control signal (up signal) output from the first detecting means, and the clock signal whose frequency within the interior of the phase-locked loop has been divided, and the control signal (dn signal) output from the second detecting means, and to produce a reset signal in accordance with the clock signal, to be input into the reset signal receiving terminal of the first detecting means; and(d) a second control logic circuit for receiving the control signal (up signal) output from the first detecting means, and the reference clock signal to produce a reset signal in accordance with the reference clock signal to be input into the reset signal receiving terminal of the second detecting means.