Patent ID: 6373913
Filing Date: 2002-04-16
Classification: H03K,H03L

Abstract:
An internal clock signal generator comprising:a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signal; and a delay locked loop (DLL) which receives the coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal; wherein the synchronized delay circuit comprises: a plurality of serially connected unit delays which provide a corresponding plurality of delayed clock signals; and a controller which selects one of the plurality of clock signals which is coarsely synchronized with the external clock signal and which generates a flag signal for enabling the DLL; wherein the DLL is enabled by the flag signal and generates the internal clock signal which corresponds to the external clock signal delayed by an integer multiple of the period of the external clock signal.