Patent ID: 7870453
Filing Date: 2011-01-11
Classification: G01R

Abstract:
1. An integrated circuit comprising: at least one application circuit to be tested; and at least one self-test circuit provided for testing the application circuit and generating at least one pseudo-random test sample, wherein the at least one pseudo-random test sample is converted into at least one test vector that is programmable and/or deterministic and is supplied to the at least one application circuit for testing purposes via at least one logic gate and through at least one signal that is applied to the at least one logic gate, and wherein an output signal arising in dependence on the at least one test vector is evaluated by the at least one application circuit using at least one signature register, wherein the at least one signal to be supplied to the at least one logic gate is made available by at least one bit flipping function (BFF) logic circuit, wherein the at least one BFF logic circuit comprises: at least one read-only memory (ROM) unit; at least one address counter unit whose output signal is applied to the at least one ROM unit; at least one counter unit, to which at least a first ROM output signal of the at least one ROM unit is applied, and which activates the at least one address counter unit with at least a first counter output signal; and at least a second logic gate, to which at least a second counter output signal of the at least one counter unit and at least a second ROM output signal of the at least one ROM unit is applied.