Patent ID: 8395932
Filing Date: 2013-03-12
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor device having a static memory cell array, the static memory cell array comprising: first and second static memory cells; and a word line, wherein each of the first and second static memory cells includes a latch circuit having a first inverter and a second inverter, and a first access transistor and a second access transistor connected to the latch circuit thereof, wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor, wherein the word line is electrically connected to gate electrode of the first and second access transistors of the first and second static memory cells, and the word line elongates along a first direction, wherein the first and second static memory cells are disposed adjacently along the first direction, wherein a gate electrode of each transistor of the first static memory cell and a gate electrode of each transistor of the second static memory cell are disposed as a mirror symmetry with respect to a line along a second direction perpendicular to the first direction, wherein a first gate wiring is integrated by the gate electrodes of the first driver transistor and the first load transistor of the first static memory cell, wherein a second gate wiring is integrated by the gate electrodes of the first driver transistor and the first load transistor of the second static memory cell, wherein a third gate wiring is integrated by the gate electrodes of the second driver transistor and the second load transistor of the first static memory cell, wherein a fourth gate wiring is integrated by the gate electrodes of the second driver transistor and the second load transistor of the second static memory cell, wherein a fifth gate wiring is integrated by the gate electrodes of the second access transistor of the first static memory cell and the second access transistor of the second static memory cell, wherein a sixth gate wiring includes the gate electrode of the first access transistor of the first static memory cell, wherein a seventh gate wiring includes the gate electrode of the first access transistor of the second static memory cell, wherein the first gate wiring, the second gate wiring, the third gate wiring, the fourth gate wiring, the fifth gate wiring, the sixth gate wiring, and the seventh gate wiring have a rectangular shape with a pair of longer sides along the first direction and a pair of shorter side along the second direction, respectively, wherein active regions of transistors of the first and second static memory cells have opposing first sides, and the first sides are disposed along the second direction, respectively, wherein the sixth gate wiring, the third gate wiring, the fourth gate wiring and the seventh gate wiring are disposed on a first straight line along the first direction in turn, wherein the first gate wiring, the fifth gate wiring and the second gate wiring are disposed on a second straight line along the first direction in turn, wherein a first distance between an edge of the first sides of the active region of each access transistor and an edge of the shorter side of the gate wiring of each access transistor is longer than a second distance between an edge of the sides of the active region of each driver transistor and an edge of the shorter side of the gate wiring of each driver transistor, wherein the first distance is a shortest distance along the first direction between the edge of the first side of the active region of each access transistor and the edge of the shorter side of the gate electrode of each access transistor, and the second distance is a shortest distance along the first direction between the edge of the first side of the active region of each driver transistor and the edge of the shorter side of the gate electrode of each driver transistor, wherein the sixth gate wiring, the third gate wiring, the fourth gate wiring and the seventh gate wiring are arranged to have a third distance between each adjacent gate wiring, and wherein the first gate wiring, the fifth gate wiring and the second gate wiring are arranged to have the third distance between each adjacent gate wiring.