Patent ID: 8035432
Filing Date: 2011-10-11
Classification: H03L

Abstract:
1. A DLL (delay locked loop) circuit having an input terminal and an output terminal, comprising: a first delay circuit that applies a first delay amount to an input signal having a predetermined frequency supplied to the input terminal to generate a delayed input signal as an output signal to the output terminal; a second delay circuit that further applies a second delay amount to the output signal to generates a first internal signal; a first comparing circuit that compares the input signal and the output signal to generate a first comparison result signal; a second comparing circuit that compares the input signal and the first internal signal to generate a second comparison result signal; and a control circuit that changes the first delay amount based on the first and second comparison result signals, wherein the control circuit changes the first delay amount of the first delay circuit by adding a first change amount to the first delay amount based on the first comparison result signal irrespective of the second comparison result signal when a lock determining signal indicating a state that a phase of the input signal and a phase of the output signal match is activated, and the control circuit changes the first delay amount of the first delay circuit by adding a second change amount larger in absolute value than the first change amount to the first delay amount based on the first and second comparison result signals, when the lock determining signal is not activated.