Patent ID: 6150278
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method of fabricating a node capacitor for a dynamic random access memory (DRAM) cell, on a semiconductor substrate, said node capacitor comprising:forming a first interpoly dielectric (IPD1) layer over said semiconductor substrate;forming a first photoresist layer on said first interpoly dielectric layer, said first photoresist layer defining a trench;removing a portion of said first interpoly dielectric layer using said first photoresist layer as a mask, thereby forming said trench in said first interpoly dielectric layer;removing said first photoresist layer;depositing a first polysilicon layer on said first interpoly dielectric layer, said first polysilicon layer filling said trench in said first interpoly dielectric layer;etching said first polysilicon layer to expose said first interpoly dielectric layer;forming a landing pad over said semiconductor substrate;depositing a polycide layer on said first interpoly layer and said landing pad;depositing a second interpoly dielectric (IPD2) layer on said polycide layer;forming a second photoresist layer on said second interpoly dielectric layer, said second photoresist layer defining a bit line structure;removing a portion of said second interpoly dielectric layer and a portion of said polycide layer using said second photoresist layer as a mask, thereby forming said bit line structure on said first interpoly dielectric layer;removing said second photoresist layer;forming a spacer on said bit line structure;depositing a second polysilicon layer on said first interpoly dielectric layer, said spacer, and said bit line structure;forming a third photoresist layer on said second polysilicon layer, said third photoresist layer defining a bottom electrode;removing a portion of said second polysilicon layer using said third photoresist layer as a mask, thereby forming said bottom electrode;removing said third photoresist layer;forming a thin dielectric layer on said bottom electrode; anddepositing a third polysilicon layer to form a top electrode, completely covering said thin dielectric layer.