Patent ID: 6300794
Filing Date: 2001-10-09
Classification: H03K

Abstract:
An integrated circuit comprising:a plurality of super-regions of programmable logic disposed on the integrated circuit in a two-dimensional array of rows and columns, each of the super-regions including:a plurality of regions of programmable logic, each of the regions including a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; anda plurality of local feedback interconnection conductors associated with each of said regions and configured to convey output signals of the subregions in the associated region so that said output signals on said local feedback interconnection conductors are available for programmable application to any of said subregions in the associated region as said input signals;a plurality of inter-region interconnection conductors configured to convey signals to the regions in the super-region so that said signals on said inter-region interconnection conductors are available for programmable application to any of said subregions in the super-region as said input signals;a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows and configured to convey signals to, from, and between super-regions in the associated row;a plurality of vertical inter-super-region interconnection conductors associated with each of said columns and configured to convey signals to, from, and between super-regions in the associated column;a first plurality of programmable logic connectors configured to selectively apply signals on the inter-region interconnection conductors associated with a super-region directly to each of said subregions in said super-region as said input signals without routing through any of said local feedback interconnection conductors;a second plurality of programmable logic connectors configured to selectively apply signals on the inter-super-region interconnection conductors associated with a super-region to each of said subregions in said super-region as said input signals without routing through any of said local feedback interconnection conductors; anda third plurality of programmable logic connectors configured to selectively interconnect said horizontal and vertical inter-super-region conductors.