Patent ID: 6480979
Filing Date: 2002-11-12
Classification: G01R,G11C

Abstract:
A method of testing a plurality of semiconductor integrated circuits having respective internal circuitry and respective selection circuits, the internal circuitry receiving control signals, performing functions that the semiconductor integrated circuits provide as a product, and generating response signals, the selection circuits receiving respective external selection signals having a first state and a second state, providing external output of the response signals when said respective external selection signals are in the first state, and blocking external output of the response signals when said respective external selection signals are in the second state, the method comprising the steps of:connecting all of the semiconductor integrated circuits in common to a single set of control signal output terminals of a tester, and to a single set of response signal input terminals of the tester; connecting each of the semiconductor integrated circuits to a separate selection signal output terminal of the tester, for sending said respective external selection signals to the selection circuits in the semiconductor integrated circuits; simultaneously sending said control signals from the tester to all of the semiconductor integrated circuits; selecting the semiconductor integrated circuits one by one, by placing their external selections signals in the first state; and making a pass/fail decision for each said semiconductor integrated circuit among said semiconductor integrated circuits by processing the response signals received from the semiconductor integrated circuit when the semiconductor integrated circuit is selected.