Patent ID: 6795346
Filing Date: 2004-09-21
Classification: G11C

Abstract:
A data processor, comprising:an electrically programmable non-volatile memory; and a CPU accessible to the non-volatile memory, wherein the non-volatile memory includes a plurality of non-volatile memory cells, word lines respectively connected to select terminals of the non-volatile memory cells, sub bit lines respectively connected to data terminals of the non-volatile memory cells, main bit lines, sub bit line selection switch elements which selectively connect the sub bit lines to the main bit lines, a sense amplifier connected to the main bit lines via column switch elements, voltage supply elements each of which supplies a predetermined clamp voltage to each main bit line, and discharge elements which discharge the sub bit lines, wherein each of the voltage supply elements supplies the clamp voltage to the corresponding main bit line before the start and end of a read operation effected on each non-volatile memory cell, and wherein the discharge elements discharge the sub bit lines after the completion of the read operation.