Patent ID: 8930873
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A method for reducing congestion using regional routing blockages in an integrated circuit (IC) design, the method comprising: detecting, at a set of layers in the IC design, a region of congestion, such that the region occupies the same area of each layer in the set of layers; defining, as a tuple, a routing blockage corresponding to the region, wherein the tuple comprises a set of coordinates to describe an area of the region, a first layer coordinate of a first layer in the set of layers, and a second layer coordinate in the set of layers; applying, using a processor and a memory, the routing blockage during an iteration of rough routing of the IC design; removing, before a detailed routing iteration of the IC design, the routing blockage; performing detailed routing using a g-cell in the region, wherein the detailed routing uses a routing capacity saved in the g-cell during the iteration of rough routing due to the routing blockage; and outputting a revised IC design, wherein in the revised design a revised congestion in an area corresponding to the region is less than a congestion in the region in the IC design.