Patent ID: 8633846
Filing Date: 2014-01-21
Classification: H03M

Abstract:
1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a comparator having a first input coupled to a first reference voltage; a multiplexor having an output coupled to a second input of the comparator, a first input coupled to an analog input of the SAR ADC, and a second input coupled to a second reference voltage; a digital-to-analog conversion (DAC) circuit having a first DAC sub-circuit, a second DAC sub-circuit, and a switch array coupling the first DAC sub-circuit to the second DAC sub-circuit, the DAC circuit being configured and arranged to output the second reference voltage to the second input of the multiplexor; and a control circuit coupled to the digital-to-analog circuit and configured and arranged to control the comparator, multiplexor, and DAC circuit to perform successive approximation on the analog input over a number of cycles by performing a first non-binary reference search using the first DAC sub-circuit and performing a second non-binary reference search using the second DAC sub-circuit.