Patent ID: 7761693
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a register data store configured to store data elements; an instruction decoder configured to decode an arithmetic returning high half instruction; and a data processor configured to perform data processing operations controlled by said instruction decoder, wherein: in response to said decoded arithmetic returning high half instruction, said data processor is configured to specify within said register data store, a size of one or more source registers to specifically store a plurality of source data elements of a first size, and a size of one or more corresponding destination registers to specifically store a corresponding plurality of resultant data elements of a second size, said second size being half the size of said first size, the one or more destination registers being half the size of the corresponding one or more source registers; and to perform each of the following operations on said plurality of source data elements in parallel to produce said corresponding plurality of resultant data elements; perform an arithmetic operation on said source registers specified by said instruction to produce a corresponding plurality of intermediate result data elements, wherein the arithmetic operation is an addition or a subtraction; form said resultant data elements from information derived from a high half of a corresponding one of said plurality of intermediate result data elements; and store said resultant data elements in said destination register.