Patent ID: 7716460
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. A method of forming an address to index lines in a branch history table (BHT) in a variable length instruction set processor to execute instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, wherein each instruction set execution mode has a different index address, comprising: identifying common line index address bits in an instruction address, the common line index address bits used by both the first and second instruction set execution modes in indexing the branch history table (BHT), wherein the common line index address bits occupy different positions in the instruction address used by the first and second instruction set execution modes; multiplexing between one or more most significant line index address bits exclusive to the first instruction set execution mode and one or more least significant line index address bits exclusive to the second instruction set execution mode, based on an instruction set execution mode indicator; concatenating the common line index address bits and the multiplexed line index address bits to form a concatenated address; and indexing lines in the BHT to retrieve counter values usable in both the first and second instruction set execution modes using the concatenated address.