Patent ID: 7002826
Filing Date: 2006-02-21
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a first word line selected by an address signal from a first port having a first input/output group; a second word line selected by an address signal from a second port having a second input/output group; and a memory cell array in which a plurality of memory cells are arranged in columns and rows, said memory cells each including a first region in which a first transistor of a first conductivity type connected to said first word line is formed, a second region arranged adjacent to said first region in a row direction toward which said first and second word lines extend, and in which a transistor of a second conductivity type is formed, and a third region arranged adjacent to said second region in said row direction and in which a second transistor of said first conductivity type connected to said second word line is formed; wherein between a first memory cell and a second memory cell adjacent to each other in a column direction of said memory cell array, a distance between said second word line connected to said first memory cell and said second word line connected to said second memory cell is longer than a distance between said second word line connected to said first memory cell and said first word line connected to said second memory cell.