Patent ID: 7215722
Filing Date: 2007-05-08
Classification: H04L

Abstract:
1. A baseband processor for processing an intermediate analogue signal received from a previous system, the baseband processor comprising: a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the intermediate analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal; an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into a digital signal and generating at an output the digital signal; a gain controller coupled to the output of the ADC for estimating a DC (Direct Current) offset of the digital signal and generating at a first output a gain control signal and at a second output a gain state signal, the gain control signal instructing the previous system to adjust a strength of the intermediate analogue signal; a DC estimator coupled to the output of the ADC for estimating the DC offset of the digital signal and generating at a first output a first DC offset signal and at a second output a second DC offset signal corresponding to the DC offset; a DAC (Digital-to-Analogue Converter) coupled to the first output of the DC estimator for receiving as an input the first DC offset signal and generating at an output a feedback signal corresponding to the first DC offset signal; an arithmetic module coupled to the output of the DAC and to the output of the programmable filter bank, the arithmetic module subtracting the feedback signal from the filtered signal for canceling DC offsets of the programmable filter bank and the ADC; and a DCF (DC-Filter) controller coupled to the second output of the DC estimator and to the second output of the gain controller for receiving the second DC offset signal to instruct the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system, wherein the DCF controller receives the gain state signal and generates the filter state signal at an output, to which the filter state input of the programmable filter bank is coupled.