Patent ID: 6807114
Filing Date: 2004-10-19
Classification: G11C

Abstract:
A system for selecting redundant sets of memory cells, comprisinga programmable circuit that is programmed to output an address corresponding to a defective set of memory cells; a defective memory cell decoder coupled to receive the address from the programmable circuit, the defective memory cell decoder outputting at least one shift control signal corresponding to the address from the programmable circuit, the at least one shift control signal indicating a shift direction for a select signal for the defective set corresponding to the address; and a select signal steering circuit coupled to receive the at least one shift control signal from the defective memory cell decoder, the select signal steering circuit being operable to shift in the direction indicated by the shift control signal the select signal for the defective set to an adjacent set of memory cells, to shift in the direction indicated by the at least one shift control signal the select signal for one of the sets to a redundant set of memory cells, and to shift in the direction indicated by the at least one shift control signal respective select signals for the sets intermediate the defective set and the one set to respective adjacent sets of memory cells.