Patent ID: 6400785
Filing Date: 2002-06-04
Classification: H04J,H04L,Y10S

Abstract:
A signal resynchronization apparatus which receives a data stream in synchronization with a first clock and outputs the data stream in synchronization with a second clock, the data stream containing a plurality of data words with an N-byte cyclic data structure, the apparatus comprising:input means for receiving the data stream from an external source; storage means, having a capacity of at least (MÃ—N) bytes (M=2, 3, 4, . . . ), for storing the data stream received by said input means; writing means, having a write address pointer, for sequentially writing each data word of the received data stream into said storage means in synchronization with the first clock; reading means, having a read address pointer, for sequentially reading out each data word from said storage means in synchronization with the second clock; output means for outputting to an external destination the data words read out by said reading means; detection means for detecting that the write and read address pointers have come within a predetermined threshold distance; and relocation means for moving the read address pointer by (PÃ—N) bytes (P=1, 2, 3, . . . ) to increase the distance between the read and write address pointers, when said detection means has detected that the write and read address pointers have come within the predetermined threshold distance.