Patent ID: 8008216
Filing Date: 2011-08-30
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit, comprising the steps of: providing a substrate; forming field oxide in said substrate; forming an n-well in said substrate; forming a p-well in said substrate; forming a gate dielectric layer on a top surface of said p-well; forming a sacrificial layer of material on a top surface of said gate dielectric layer; exposing said sacrificial layer to a nitridation source; removing said sacrificial layer; forming an n-channel MOS transistor in said p-well by a process comprising the steps of: forming a p-channel MOS transistor in said n-well by a process comprising the steps of: forming a pre-metal dielectric layer stack on said n-channel transistor and said p-channel transistor; forming contacts in said pre-metal dielectric layer stack on said n-type source and drain regions, said p-type source and drain regions, said first gate structure and said second gate structure; forming a first intra-level dielectric layer on said contact; and forming metal interconnect structures whereby the metal interconnect structures connect to and overlap said contacts.