Patent ID: 6406609
Filing Date: 2002-06-18
Classification: C25D,H01L

Abstract:
A method of fabricating an integrated circuit on a semiconductor wafer, comprising:forming transistors on a semiconductor wafer; forming a dielectric layer over the transistors; forming an opening dielectric layer; placing the semiconductor wafer into an aqueous electroplating solution, including: a copper salt; an acid having a dissociation constant of less than about 2.0; a hydrogenated halide; and a modulator comprising a weight by weight percent of the electroplating solution of about less than 1% and wherein said modulator includes a brightener that includes a derivative of 2,2â€²-thiobisalkyl acetoacetate having a general formula: (Xâ€”[CH2(CH2)2â€”Oâ€”C(O)CH2C(O)CH3]2), where X=S or N; electroplating copper in the opening; and interconnecting the transistors to form an operative integrated circuit.