Patent ID: 8421185
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A parasitic vertical PNP device in a BiCMOS process with shallow trench isolation (STI) on bulk silicon substrate comprises: a collector being formed by implanting p-type impurity in an active area; pseudo buried layers at the bottom of the STI at both sides of the active area by implanting heavy dose of the p-type impurity into the bulk silicon substrate, wherein the pseudo buried layers is directly connected with the bulk silicon substrate, and forms a PN junction; deep contacts wherein the deep contracts are through field oxide to connect to the pseudo buried layers and to pick up the collector; a base being formed by ion implanting a n-type impurity layer wherein the base sits on top of the collector; an emitter which is a single crystal p-type epitaxy layer wherein the emitter lies above the base and is connected directly by a metal contact; and a portion of the p-type epitaxy layer on top of the base is converted into n-type and serves as a connection path of the base.