Patent ID: 6282554
Filing Date: 2001-08-28
Classification: H03M

Abstract:
A floating point arithmetic apparatus for converting numbers between an integer format including a least significant bit position and a floating point format including an exponent portion and a fraction portion, wherein a conversion operation requires a greater data path width than a floating point arithmetic operation, said floating point arithmetic apparatus comprising:right shift circuitry to receive a number in the floating point format, wherein the right shift circuitry includes additional register positions to the right of the rightmost position required by a floating point arithmetic operation to accommodate a right shift beyond a data path width required by a floating point arithmetic operation; andright shift control circuitry to control the right shift circuitry to produce a number in the integer format with the least significant bit position having a first alignment, in response to the exponent portion of the number received in floating point format having a first magnitude, and to produce a number with the least significant bit position having a second alignment different from the first alignment in response to the exponent portion having a second magnitude different from the first magnitude.