Patent ID: 7552282
Filing Date: 2009-06-23
Classification: G06F

Abstract:
1. A computer-implemented method for caching data comprising: receiving data; determining whether to replicate the data in a cache in accordance with one or more designated types of data, said one or more designated types of data including data that is associated with a write operation, wherein the cache includes at least a first memory board and a second memory board different from said first memory board, wherein a logical address space is defined spanning a range of logical addresses from a first logical address to an ending logical address, said logical address space comprising mutually exclusive address range portions including a first logical address range portion and a second logical address range portion; if said determining determines that the data is to be replicated and the data is associated with a write operation, selecting a first cache location from a first set of cache locations on the first memory board associated with said first logical address range portion and selecting a second cache location from a second set of cache locations on the second memory board associated with said second logical address range portion in accordance with a mapping table indicating portions of the first and the second memory boards including the first and the second cache locations, and storing the data in the first cache location and the second cache location; and if said determining determines that the data is not to be replicated, selecting a single cache location from the first set of cache locations associated with said first logical address range portion or from the second set of cache locations associated with said second logical address range portion in accordance with the mapping table, and storing the data in the single cache location, wherein said single cache location is selected from a plurality of cache locations having a plurality of corresponding logical addresses comprising each logical address in said first logical address range portion and each logical address in said second logical address range portion, wherein said determining, said selecting the first cache location and selecting the second cache location are performed after the cache is initialized for selective data replication.