Patent ID: 6191627
Filing Date: 2001-02-20
Classification: H03L

Abstract:
An integrated circuit, comprising:a first delay unit having an adjustable delay time, an input for feeding in a first clock signal and an output;a second delay unit having an adjustable delay time, an input for feeding in a second clock signal and an output;a phase detector having a first input connected to said input of said first delay unit and a second input connected to said output of said first delay unit;a control unit controlling the delay time of said first delay unit for correcting a phase difference ascertained by said phase detector and setting the delay time of said second delay unit to substantially the same value as that of said first delay unit;a circuit unit having a first input connected to said output of said first delay unit and a second input connected to said output of the second delay unit; anda third delay unit having an adjustable delay time, said third delay unit connected between said output of said second delay unit and said second input of said circuit unit.