Patent ID: 7652346
Filing Date: 2010-01-26
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an active region formed on a semiconductor substrate; an element isolation region formed on the semiconductor substrate so as to surround the active region; and a gate electrode formed on the active region, wherein a first element isolation region that causes tensile stress so as to improve carrier mobility in the active region is provided in the element isolation region, the first element isolation region is formed in a trench arranged in the semiconductor substrate and has a first insulating film that causes the tensile stress and a void which is located so that the entire of the void is surrounded by the first insulating film, the active region is an N-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) region, the first element isolation region is provided in a portion of the element isolation region which is adjacent to the active region in a gate length direction, a second element isolation region is provided in a portion of the element isolation region which is adjacent to the active region in a gate width direction, and the second element isolation region has a second insulating film formed in a trench arranged in the semiconductor substrate but has no void.