Patent ID: 7863724
Filing Date: 2011-01-04
Classification: H01L,H05K,Y10T

Abstract:
1. A substrate for an integrated circuit package, comprising: a plurality of die interconnection lands disposed atop the substrate, wherein the interconnection lands include power supply lands and signal lands; a first power supply plane forming a top metal layer extending across the top surface of the substrate and forming a first set of the power supply lands, wherein the top metal layer is exclusive of a second set of the power supply lands and the signal lands; an insulating layer disposed below the first power supply plane; a second power supply plane disposed across substantially all of an inner metal layer of the substrate adjacent to and beneath the insulating layer, exclusive of second pass-through regions for vertical interconnects; a plurality of small-diameter power supply blind vias having first ends terminating on and electrically connected to the second set of power supply lands and second ends terminating on and electrically connected to the second power supply plane; large-diameter plated-through holes, disposed near edges of the substrate and extending from the top side of the substrate to the bottom side of the substrate, wherein a first plurality of the large-diameter plated-through holes are electrically connected to the first power supply plane and a second plurality of the large-diameter plated-through holes are electrically connected to the second power supply plane; and power supply terminals, electrically connected to bottom ends of the large-diameter plated-through holes for interconnecting the substrate to a power supply.