Patent ID: 6635544
Filing Date: 2003-10-21
Classification: H01L,Y10S

Abstract:
A method for fabricating a high-voltage transistor comprising:forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type and having a top surface; forming source and body regions in the epitaxial layer, the source region being of the first conductivity type and disposed at the top surface of the epitaxial layer, the body region being of a second conductivity type opposite to the first conductivity type; forming a pair of spaced-apart trenches in the epitaxial layer that define a mesa with first and second sidewall portions; forming a dielectric layer over each of the first and second sidewall portions; forming field plate members in the trenches, the field plate members comprising a conductive material that is insulated from the mesa; and forming an insulated gate member between each of the field plate members and the mesa, a channel being defined adjacent the insulated gate member in the mesa across the body region.