Patent ID: 6660599
Filing Date: 2003-12-09
Classification: H01L

Abstract:
An isolation method comprising the steps of:forming a polycrystalline silicon layer on a semiconductor substrate on which a pad oxide layer is formed; forming a trench in the semiconductor substrate by etching sequentially a part of the polycrystalline silicon layer, a part of the pad oxide layer, and a part of the semiconductor substrate; forming an oxide layer spacer on the walls of the trench and the side walls of the etched pad oxide layer and the etched polycrystalline silicon layer; forming a nitride liner on the oxide layer spacer; filling the trench with an insulating layer on the nitride liner; planarizing the insulating layer such that the polycrystalline silicon layer is exposed; and dry-etching the polycrystalline silicon layer, wherein the step of dry-etching comprises a first step of removing the polycrystalline silicon layer by etching back the polycrystalline silicon layer with an etchant having the first etching selectivity of the pad oxide layer with respect to the polycrystalline silicon layer, and a second step of etching back the polycrystalline silicon layer with an etchant having the higher second selectivity than the first selectivity of the pad oxide layer with respect to the polycrystalline silicon layer to remove the polycrystalline silicon layer remaining on the pad oxide layer, and a rounded bulge is formed on an upper portion of an isolation region above the substrate.