Patent ID: 8117512
Filing Date: 2012-02-14
Classification: A61B

Abstract:
1. A high integrity logic circuit comprising: a. a plurality of parallel cores, wherein said parallel cores are used to implement critical functions of said logic circuit, b. wherein said parallel cores are redundant or diverse, c. a redundancy checker, wherein said redundancy checker is used to: d. wherein said logic circuit is interfaced to a plurality of inputs and a plurality of outputs, e. wherein said logic circuit performs a mission related to said inputs and said outputs, wherein said mission is a safety critical function, f. wherein communication between said logic circuit and said inputs and said outputs is protected by at least one item selected from the group consisting of: g. a built in self test, wherein said built in self test is used to expose unannounced failures in any said parallel core, h. wherein said built in self test is performed periodically or continually while said logic circuit performs said mission, i. wherein said critical functions of said logic circuit are substantially implemented in at least one logic device, and j. wherein said at least one logic device is implemented free of the use of executable software.