Patent ID: 6981109
Filing Date: 2005-12-27
Classification: G06F

Abstract:
1. A digital signal processor comprising: a programmable memory having a plurality of blocks each of which is capable of having an instruction of a program written therein and read therefrom; a processor for sequentially executing instructions stored in the programmable memory; and an access controller for sequentially storing the instructions of the program in the blocks of the programmable memory responsive to addresses indicating a location of blocks where the instructions are to be stored, the access controller controlling an access of the processor to the blocks, wherein upon receiving a data signal describing a sequence of addresses of the blocks where the instructions are stored, the access controller compares the addresses of the sequence with addresses corresponding to the blocks to which the processor has made access at every access, and when it is determined that disagreement in value exists there between, the processor is made to transition to an access halt condition.