Patent ID: 6429487
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A semiconductor device comprising:an SOI substrate of multilayered structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; an isolation insulating film formed in said semiconductor layer in an isolation region of said SOI substrate; a body region selectively formed in said semiconductor layer in an element formation region of said SOI substrate defined by said isolation insulating film; a gate electrode formed on said body region with a gate insulating film interposed therebetween; an interlayer insulating film covering said isolation insulating film and said gate electrode; a contact hole so selectively formed in said interlayer insulating film as to expose part of said gate electrode and overlap in plane view part of said isolation insulating film; and a connection body including a conductor formed in said contact hole, for electrically connecting said gate electrode and said body region, wherein at least part of a bottom surface of said connection body is in contact with said isolation insulating film.