Patent ID: 6788143
Filing Date: 2004-09-07
Classification: H03F

Abstract:
An apparatus comprisinga first current source that is coupled to a first node; a second current source that is coupled to a second node; a first transistor that is coupled between a first power supply and a fifth node, wherein the first transistor is biased by a third node; a second transistor that is coupled between the first power supply and a sixth node, wherein the second transistor is biased by the third node; a third transistor that is coupled between the third node and the fifth node, wherein the third transistor is biased by a second power supply; a fourth transistor that is coupled between a fourth node and the sixth node, wherein the fourth transistor is biased by the second power supply; a fifth transistor that is coupled between the first node and the third node, wherein the fifth transistor is biased by a bias signal; a sixth transistor that is coupled between the second node and the fourth node, wherein the sixth transistor is biased by the bias signal such that the fourth node operates as a high impedance node that is responsive to current signal that are provided to the first and second nodes, respectively; and an output stage that is arranged to receive a high gain signal from the high impedance node such that the output stage provides an output signal in response to the high gain signal wherein the output stage comprises; a ninth transistor and a resistor, wherein the ninth transistor and the resistor are configured to operate as a gain stage that is responsive to the high gain signal.