Patent ID: 8094040
Filing Date: 2012-01-10
Classification: G08G

Abstract:
1. An apparatus for electronically detecting valid siren sound emitted from an emergency motor vehicle having a sounding siren, said siren being characterized as emitting loud, audible frequencies that cyclically vary with time between a high “B” frequency to a low “A” frequency for sounding a warning siren sound, said siren being characterized as being rich in harmonic overtones, comprising: means for receiving said siren sound frequencies and converting the received sounds to corresponding electrical signals, first operational amplifier circuit means coupled to said receiving means and amplifying the electrical signals coupled thereto and filtering out any high frequency signals, second operational amplifier circuit means having input and output terminals, circuit means coupled to the input terminals of said second amplifier circuit means for biasing said amplifier means in a near oscillatory mode at a pre-selected frequency above the frequency of the high frequency end or “B” frequency of the siren frequency range, feedback circuit means comprising a parallel circuit means network of a resistor and capacitor connected between the input and output terminals of second amplifying means, said feedback capacitor being selected and proportioned for stabilizing said second amplifier means for preventing said amplifier means from going into oscillation at said frequency above the siren frequency range and thereby causing said input circuit means for second amplifying means to function as a band pass filter that is frequency band limited to said siren sound frequencies applied to said second amplifying means, a frequency adjustable, phase lock detector circuit means arranged for detecting pre-selected frequencies including a pre-selected frequency range below said high “B” frequency and a frequency range above said low “A” frequency for locking said detector circuit means to said pre-selected frequency below said “B” frequency and providing an electrical output signal representative of said locked condition upon receipt of said signal below said high “B” frequency, said phase lock detector circuit means being coupled to a frequency setting network for setting said detector circuit means to said pre-selected high frequency, said frequency setting network comprising a combination of resistor and capacitor means for defining said pre-selected high frequency for said detector circuit means, said detector circuit means causing the lock up of said detector circuit means upon receipt of a signal having said pre-selected high frequency and causing the unlocking thereof upon the signal undergoing processing decreasing in frequency, resistor ladder network means including an individual resistor means continuously connected in combination with said frequency setting network for defining said pre-selected frequency for locking said phase lock detector, as the siren signals decrease from said pre-selected high “B” frequency to said pre-selected low “A” frequency, timing circuit means for timing a pre-selected time interval between the locking and unlocking periods of said phase lock detector circuit means and coupled to the output signal for said phase lock detector for initiating the timing period upon detection of a locking frequency, a binary coded decimal counter having input terminals and binary coded decimal output terminals, an input terminal for said counter being coupled to be responsive to said output signal for said phase lock detector upon receipt of a locking signal frequency for enabling said counter to count up, said output terminals for said counter providing binary coded decimal signals representative of the counters' count, said counter having a pre-selected total decimal count, multiplexing circuit means coupled to pre-selected output terminals of said counter and to said ladder network and providing an individual output count signal corresponding to the decimal count of said counter in response to the receipt of said inputted binary coded decimal signals, and effective to serially select and add a corresponding resistor or resistors from said ladder network for defining a lower high “B” frequency as the input signals coupled to said detector circuit means decrease in frequency, the “zero” output count of the counter causing a pre-selected resistor of said ladder network to be continuously connected in combination with the frequency setting network for determining the pre-selected high frequency below said “B” frequency lockout frequency of said phase lock detector circuit means, the decreasing frequencies of the input siren signals causing said phase lock detector circuit means therefrom upon the unlocking thereof that is coupled to said counter input terminal and causes said counter to count up one decimal count for each lock-unlock sequence that occurs during the pre-selected time interval of said timing circuit and thereby causing an additional resistor or resistors to be added to said pre-selected resistor of said ladder network to said frequency setting network for defining a lower frequency for said detector circuit means, upon said counter counting up to said pre-selected count, the counter directly provides an output signal representative of the complete tracking of the siren signal from said pre-selected high “B” siren frequency to the low “A” frequency incrementally in accordance with the total decimal count selected for said counter, and means coupled to said output signal representative of the complete tracking of the siren signal from said “B” frequency to said “A” frequency for signaling the detection of a valid siren sound signal.