Patent ID: 8922265
Filing Date: 2014-12-30
Classification: G11C,H03K

Abstract:
1. A noise current compensation circuit, comprising a first PMOS tube P 1 , a second PMOS tube P 2 , a third PMOS tube P 3 , a fourth PMOS tube P 4 , a fifth PMOS tube P 5 , a sixth PMOS tube P 6 , a seventh PMOS tube P 7 , a first NMOS tube N 1 , a second NMOS tube N 2 , a third NMOS tube N 3 , a fourth NMOS tube N 4 , a fifth NMOS tube N 5 , a sixth NMOS tube N 6 , a seventh NMOS tube N 7 , and an eighth NMOS tube N 8 , wherein, the source electrode of the first PMOS tube P In addition, the body terminals of the first PMOS tube P