Patent ID: 8242479
Filing Date: 2012-08-14
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory device comprising: a substrate; a plurality of first wires provided on the substrate so as to extend in parallel with each other in a first direction; an interlayer insulating layer provided over the substrate and the plurality of first wires; a plurality of via holes penetrating the interlayer insulating layer, each of said plurality of via holes exposing a respective one of said plurality of the first wires; a plurality of resistance variable layers, one of which is provided in each of said plurality of via holes, which are provided under upper openings of the via holes, respectively, each of said plurality of resistance variable layers being electrically connected to one of the plurality of first wires, respectively; a plurality of first electrode layers, each of which is electrically connected to one of the plurality of the resistance variable layers, respectively such that each of the plurality of first electrode layers covers an entire upper opening of associated one of the plurality of via holes and protrudes outwardly over an entire periphery of the upper opening; and a plurality of second wires provided so as to extend in parallel with each other in a second direction crossing the first direction when viewed from a thickness direction of the interlayer insulating layer such that each of the plurality of second wires covers an upper surface and side surfaces of associated one of the first electrode layers; wherein each of the second wires includes: a current control layer provided so as to cover an upper surface and side surfaces of the plurality of first electrode layers; and a second electrode layer provided so as to cover an upper surface of the current control layer and a portion of side surfaces of the current control layer, the said portion covering the side surfaces of the plurality of first electrode layers.