Patent ID: 6552708
Filing Date: 2003-04-22
Classification: G09G,H03F

Abstract:
A unit gain buffer for reducing the layout area of the data driver in TFT-LCD panel, comprising:an input transistor M1 connected to a constant current source I1 via the source pole of M1, the gate pole of M1 being the input Vin of the unit gain buffer; a high bias transistor consisted of transistors M2 and M3 in series connection, the gate pole of M3 connected to Vin, the source pole of M2 connected to the constant current source I1, further the gate pole of M2 connected to the drain pole of M3 and with a constant current source I2; an output transistor M4 connected to a constant current source I3 via the drain pole of M4, the drain pole of M4 being the output Vout of the unit gain buffer and connected to the gate pole of M4, the source pole of M4 connected to the connection point A between M2 and M3; wherein, the voltage of point A is almost the same as the input Vin, there is only difference Vgs of M3 between the point A and Vin, that is Vin=VAâˆ’DVgs3, by using the M4 to make the Vout=VA+Vgs4 and Vgs3 is same as Vgs4, then Vout is almost the same as Vin; and when the Vout and Vin are all in high level, then the Vin is changed into low level suddenly, the M1 is changed into linear region immediately and produces a large current, the large current flows into the drain pole of M4 via the N-well contact to output, that is the large current is from drain pole into body pole to form a current path, and this is the same as M2 to form a current path so the M2 and M4 produce a discharging current path.