Patent ID: 6974736
Filing Date: 2005-12-13
Classification: H01L

Abstract:
1. A method for fabricating a gate structure for a semiconductor device, the gate structure being formed on a substrate, the gate structure being adjacent to a dielectric material having a top surface, the method comprising the steps of: removing material in a gate region of the device to expose a portion of the substrate; forming a gate dielectric on the exposed portion of the substrate; forming an inner spacer layer overlying the gate dielectric and the dielectric material; forming a silicon layer overlying the inner spacer layer; removing a first portion of the silicon layer and a first portion of the inner spacer layer, so that the top surface of the dielectric material is exposed and a second portion of the silicon layer and a second portion of the inner spacer layer remain in the gate region and have surfaces coplanar with said top surface; and forming a silicide gate structure from the second portion of the silicon layer, the silicide gate structure being separated from the dielectric material by the second portion of the inner spacer layer.