Patent ID: 6526481
Filing Date: 2003-02-25
Classification: G06F

Abstract:
In a coherent shared-memory system that includes a plurality of caches and a shared memory coupled to each of the caches, wherein the shared memory includes a directory for associating each of a plurality of addresses in a shared address range with caches that each has a value associated with said address in a storage at that cache, a method comprising:at each of the plurality of caches, storing a value associated with a first address in the shared address range in the storage of said cache; while storing the values associated with the first address at each of the caches, associating in the directory the first address with some but not all of the caches which are storing said values; and while associating the first address with some but not all of the caches which are storing values associated with said first address, providing a coherent memory model for said first address to processors coupled to each of the plurality of caches.