Patent ID: 6222792
Filing Date: 2001-04-24
Classification: G11C

Abstract:
A semiconductor memory, comprising:a clock input circuit which receives an external clock signal therein to thereby generate an internal clock signal;an internal circuit which performs a memory operation in synchronism with the internal clock signal;an output circuit which outputs data obtained from each memory cell according to the memory operation of said internal circuit to the outside; anda clock reproducing circuit for matching the phase of an output operation of said output circuit with that of the external clock signal,said clock reproducing circuit including,first and second predetermined delay circuits which respectively add predetermined delay times to a reference clock signal synchronized with the internal clock signal and are connected to each other in series form;a forward delay circuit having unit delay circuits provided in series form in plural form, which successively propagate the output of said second predetermined delay circuit and selects the position of an output of said each unit delay circuit, which most approximates the state of the reference clock signal;a first backward delay circuit which has a plurality of unit delay circuits provided in series form in the reverse direction, each having a delay characteristic identical to or substantially identical to that of said forward delay circuit and which selects an input position of each of the unit delay circuits having, at a subsequent stage, the same number of stages as the number of stages of the unit delay circuits each corresponding to the output position selected by said forward delay circuit and adds the output of said first predetermined delay circuit to the selected input position;a plurality of fixed delay circuits which respectively receive a first clock signal outputted from said first backward delay circuit therein and add predetermined delay times different from one another to the input first clock signal;a detection circuit which receives clock signals outputted from said plurality of fixed delay circuits and the reference clock signal therein and generates detected signals represented in plural bits each corresponding to the difference in phase between the reference clock signal and the first clock signal;a second backward delay circuit which has a plurality of unit delay circuits provided in series form in the reverse direction, each having a delay characteristic identical to or substantially identical to that of said forward delay circuit and which selects an input position of each of the unit delay circuits having, at a subsequent stage, the same number of stages as the number of stages of the unit delay circuits each corresponding to the output position selected by said forward delay circuit and adds the reference clock signal to the selected input position;a variable delay circuit which receives said detected signals represented in a plurality of bits in parallel from said detection circuit and adds a delay of the phase difference corresponding to said each input detected signal to a clock signal outputted from said second backward delay circuit; andwherein said output circuit allows the phase of the output operation thereof to coincide with that of the external clock signal in synchronism with a clock signal outputted from said variable delay circuit.