Patent ID: 6298418
Filing Date: 2001-10-02
Classification: G06F

Abstract:
A cache coherency control method for a multiprocessor system including a plurality of processor modules sharing at least one memory module via a bus or a crossbar switch each processor module including a cache memory for temporarily storing data to be transferred to and from the at least one memory module, the cache coherency control method comprising the steps of:issuing an access request to updated data in said cache memory of one of the plurality of processor modules, from another processor module;selecting at least one of first, second, third, fourth, and fifth operations in response to the access request; andexecuting the selected one of said first to fifth operations, wherein:said first operation transfers updated data to the other processor module which issued the access request, if the updated data is latest updated data exclusively possessed by the one processor module and a memory write request for the updated data is not being executed;said second operation notifies, after the completion of the memory write request, the other processor module which issued the access request that the updated data in said cache memory is invalid, if the updated data is latest updated data exclusively possessed by the one processor module and the memory write request for the updated data is under execution;said third operation urges, after the completion of the memory write request, the other processor module which issued the access request to read the updated data from said memory module if the updated data is latest updated data exclusively possessed by the processor by the one processor module and the memory write request for the updated data is under execution;said fourth operation issues, after the completion of the memory write request, a read request for the updated data to said memory module as a proxy to the other processor module which issued the access request to transfer the updated data from said memory module to the access requested other processor module if the updated data is latest updated data exclusively possessed by the processor module and the memory write request for the updated data is under execution; andsaid fifth operation supplies the updated data in the processor module to the access requested other processor module and invalidates the updated data after a completion of the memory write request, if the updated data is latest updated data exclusively possessed by the one processor module and the memory write request for the updated data is under execution.