Patent ID: 6734477
Filing Date: 2004-05-11
Classification: H01L

Abstract:
An integrated circuit comprising:a transistor level comprising one or more semiconductor devices disposed over a substrate and an overlying transistor isolation structure having at least one contact via extending therethrough; a ferroelectric device level positioned over the transistor isolation layer, the ferroelectric device level completely encompassing at least one ferroelectric capacitor structure comprising a top electrode having an electrical contact area, a bottom electrode and ferroelectric dielectric material disposed between the top and bottom electrodes, the ferroelectric device level further including a ferroelectric isolation structure disposed over at least a portion of the top electrode of the at least one ferroelectric capacitor structure and electrically isolating non-electrical contact areas of the at least one ferroelectric capacitor structure from overlying and adjacent electrical structures, the ferroelectric isolation structure having at least one via extending therethrough and aligned with a corresponding contact via of the transistor isolation layer, the at least one via extending through the ferroelectric isolation structure being laterally sized larger than the corresponding contact via of the transistor isolation structure aligned therewith; a first wiring level disposed over the ferroelectric device level; an inter-level dielectric level disposed over the first wiring level; and a second wiring level disposed over the inter-level dielectric level.