Patent ID: 8481390
Filing Date: 2013-07-09
Classification: H01L

Abstract:
1. A method for forming an impurity region of a vertical transistor, comprising: preparing a semiconductor substrate having a first region where an active region is to be formed, and a second region where a trench is to be formed; forming an impurity ion junction region in the first region and the second region; and etching a portion of the semiconductor substrate including the second region to form a trench exposing a side of the first region and to form an active region which protrudes upwards having the first region at a lower portion of the active region, wherein the etching process is performed to remove the impurity ion junction region of the second region, so that the impurity ion junction region remaining in the first region serves as a buried bit line junction region exposed within the trench, wherein the forming of the impurity ion junction region comprises: wherein the forming of the trench comprises: wherein the second mask pattern covers a portion of the semiconductor substrate on the first region and exposes another portion of the semiconductor substrate on the second region; and wherein the second mask pattern is formed by an exposure process performed in such a state that a photomask used to form the first mask pattern is shifted in a horizontal direction.