Patent ID: 6947493
Filing Date: 2005-09-20
Classification: H03M

Abstract:
1. A dual phase pulse modulation (DPPM) decoder circuit, comprising: a DPPM signal input configured to receive a DPPM signal consisting of a series of alternately high and low signal pulses of specified widths corresponding to M-bit groups of data bits; where M is an integer greater than zero a signal inverter coupled to the DPPM signal input; high and low pulse width determining circuit blocks coupled to the DPPM signal input, the low pulse width determining circuit block coupled to the DPPM signal input via the signal inverter, each pulse width determining circuit block constructed to output M-bit data values corresponding to pulse widths of the respective high and low signal pulses; a parallel output register coupled to the high and low pulse width determining circuit blocks, the parallel output register configured to receive and interleave the M-bit data values and to output a data word corresponding to the DPPM signal.