Patent ID: 6200859
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method for fabricating a split-gate flash memory, comprising:forming a tunnelling oxide layer, a first conductive layer, and a hard mask layer on a substrate in sequence;defining the hard mask layer to form a drain opening and a floating gate opening on the hard mask layer and to expose the first conductive layer;forming a first polyoxide layer on the exposed first conductive layer of the drain opening and a second polyoxide layer on the exposed first conductive layer of the floating gate opening;removing the first polyoxide layer and the first conductive layer beneath the first polyoxide layer to expose the substrate;forming a drain in the exposed substrate;removing the hard mask layer;forming a floating gate by etching the first conductive layer while using the second polyoxide layer as a mask;forming a split-gate oxide layer on the substrate and the floating gate;forming a second conductive layer on the split-gate oxide layer;defining the second conductive layer to form a control gate; andforming a source in the substrate beside the floating gate.