Patent ID: 7679108
Filing Date: 2010-03-16
Classification: G11C,H01L

Abstract:
1. A semiconductor memory comprising: a plurality of active regions; a plurality of bit line contacts disposed on respective active regions; a plurality of first local lines formed in an island shape and in contact with upper surfaces of the plurality of bit line contacts; a plurality of first via contacts in contact with the upper surfaces of the plurality of first local lines respectively; a first bit line in contact with a second via contact which is one of the plurality of first via contacts and extending in a direction parallel to the active regions; a second bit line in contact with a third via contact which is one of the plurality of first via contacts and is not in contact with the second via contact, the second bit line is adjacent to the first bit line and extending in a direction parallel to the active regions; and a plurality of fourth via contacts arranged above fifth via contacts which are among the plurality of first via contacts and adjacent to the second via contact or the third via contact in a direction parallel to the active regions, and the fifth via contacts not being in contact with the first bit line and the second bit line through respective second local lines, wherein a space between the first bit line and the second bit line is wider than a space between the active regions.