Patent ID: 6538913
Filing Date: 2003-03-25
Classification: G11C

Abstract:
A method for operating a ferroelectric memory configuration in the VDD/2 mode, which comprises:providing a ferroelectric memory configuration having a plurality of memory cells which each have at least one selection transistor, one ferroelectric storage capacitor with an upper and a lower electrode, and one short-circuiting transistor having a source-drain junction connected in parallel with the storage capacitor; in a precharge phase, precharging bit lines; performing a procedure selected from the group consisting of a read procedure and a write procedure, in which at least some of the plurality of the memory cells are driven via respectively associated word lines and via respectively associated ones of the bit lines that have been precharged in the precharge phase; in a standby phase, driving the storage capacitor of at least one of the plurality of the memory cells to short-circuit the upper electrode and the lower electrode of the storage capacitor of the one of the plurality of the memory cells; performing the standby phase coincident in time with the precharge phase such that the bit line associated with the one of the plurality of the memory cells is at a different potential than that of the upper electrode and the lower electrode of the storage capacitor of the one of the plurality of the memory cells.