Patent ID: 7372906
Filing Date: 2008-05-13
Classification: H04N

Abstract:
1. A video compression circuit for generating an encoded bitstream from a plurality of video frames, the circuit comprising: a discrete cosine transform (DCT) circuit for accepting prediction error macroblocks and generating DCT transformed macroblocks; a first streaming data connection for streaming the DCT transformed macroblocks from the DCT transformation circuit to a processor, the processor being configured to run software for: a second streaming data connection for streaming the inverse quantized macroblocks from the processor to an inverse discrete cosine transform (IDCT) circuit, wherein the IDCT circuit transforms the inverse quantized macroblocks to generate reconstructed prediction error macroblocks; an addition circuit for adding a reconstructed prediction error macroblock and a corresponding predictor macroblock, thereby generating respective reconstructed macroblocks for use in the encoding of other macroblocks; and means for zig zag scanning, run level coding and variable length coding the quantized macroblocks to generate an encoded bitstream.