Patent ID: 7881029
Filing Date: 2011-02-01
Classification: H01Q,H03F

Abstract:
1. An electrostatic discharge (ESD) clamp circuit comprising: a first terminal; a second terminal having a first voltage with respect to a voltage at the first terminal, such that the first terminal and the second terminal are coupled between an ESD protected circuit and a direct current (DC) reference; a reverse protection circuit coupled between the first terminal and the second terminal; a first depletion-mode field effect transistor (FET) element formed using a compound semiconductor material and comprising: a source-coupled level shifting circuit coupled between the first source and the second terminal; a first resistive element coupled between the first gate and the second terminal, wherein when the first voltage exceeds a first threshold, the ESD clamp circuit is in a clamping state; a plurality of depletion-mode pseudomorphic high electron mobility transistor (pHEMT) elements: a plurality of resistive elements comprising the first resistive element, such that each of the plurality of resistive elements is coupled between a corresponding each of the plurality of gates and the second terminal.