Patent ID: 9122802
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A system on chip comprising: a plurality of masters comprising a first master and a second master; a plurality of slaves comprising a first slave and a second slave; and an interconnector through which the plurality of masters are connected to the plurality of slaves, the interconnector comprising: wherein a master address is transmitted to the bit selector from one of the plurality of masters, wherein address bit information corresponding to the master address is stored in the register, wherein the bit selector selects two or more bits among the master address based on the address bit information, outputs the selected two or more bits to the logic circuit, and outputs a slave address to the switching circuit, the slave address having at least a portion of the master address, wherein the logic circuit performs a logic operation with the selected two or more bits, and outputs a selection signal to the switching circuit, and wherein the switching circuit outputs the slave address to one of the plurality of slaves based on the selection signal.