Patent ID: 6716715
Filing Date: 2004-04-06
Classification: H01L,Y10S

Abstract:
A method for manufacturing a DRAM cell including two active word lines having a common drain/source region and having distinct source/drain regions contacting two memory points, comprising, after the forming of insulated conductive lines on a semiconductor substrate, the steps of:a) depositing a first insulating layer; b) depositing a second insulating layer, selectively etchable with respect to the first insulating layer; c) etching the second insulating layer to only maintain it above the insulated conductive lines, at least above an active region of the substrate; d) depositing and leveling a third thick insulating layer selectively etchable with respect to the second insulating layer; e) forming an opening in the first and third insulating layers to at least partially expose the common drain/source region and an insulating trench; f) depositing a conductive material to fill the previously-formed opening; g) performing a chem-mech polishing; and h) depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.