Patent ID: 6436765
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of fabricating a trenched flash memory cell, the method comprising:providing a silicon substrate, the silicon substrate having both a defined memory array area and a periphery circuits region; performing a shallow trench isolation (STI) process to form a plurality of shallow trench isolation structures in the silicon substrate, and at least a defined active area enclosed by the shallow trench isolation structures; performing a first ion implantation process on the silicon substrate in the memory array area so as to form a doped region; forming an isolation layer on the surface of the silicon substrate; performing a first photo and etching process (PEP) to remove a portion of both the isolation layer and the silicon substrate so as to form two trenches in the active area; forming a tunnel oxide layer and a floating gate, respectively, on the inner surface of each trench; forming a dielectric layer on the surface of the floating gates; forming a doped polysilicon layer on the silicon substrate to fill the trenches; performing a second photo and etching process to remove a portion of the doped polysilicon layer so as to simultaneously form two controlling gates in the active area and a plurality of gates in the periphery circuits region; performing a self-alignment source (SAS) etching process to etch the portion of the isolation layer between the two controlling gates down to the surface of the doped region so that the doped region positioned between the two controlling gates is used as a common source; forming a plurality of spacers on either side of each controlling gate; and performing a self-alignment silicide (salicide) process to form a silicide layer on the common source and each controlling gate; wherein the doped region, not occupied by the controlling gates and the common source, in the active area is defined as a drain of the trenched flash memory cell.