Patent ID: 6011743
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A charge pump circuit for memory device comprising:an elevated potential terminal connected to an output capacitor;a level monitor connected to said elevated potential terminal wherein a certain range of voltage is divided into a plurality of voltage level intervals, said level monitor generating a plurality of pumping enable signals corresponding to said plurality of voltage level intervals, said plurality of said pumping enable signals having different activated time with respect to one another,said level monitor activating respective pumping enable signals corresponding to said plurality of voltage level intervals to which an elevated potential belongs based on detection of the elevated potential;a pulse generator, coupled to said level monitor, for generating a pulse signal when at least one of said plurality of pumping enable signals is activated; anda plurality of charge pump modules, coupled to said pulse generator and enabled by said plurality of pumping enable signals, for supplying said output capacitor with electric charge via pumping operation based on said pulse signal.