Patent ID: 6624031
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A method for detecting semiconductor process stress-induced defects comprising:providing a polysilicon-bounded test diode 100, said polysilicon-bounded test diode comprising a diffused first region 110 formed in an upper portion of a second region 115 of a silicon substrate 105, said second region 115 of an opposite dopant type N from said diffused first region P, said diffused first region 110 surrounded by a peripheral dielectric isolation 120 and a peripheral polysilicon 125,170 gate comprising a polysilicon layer 125 over a dielectric layer 170, said polysilicon gate 125 overlapping a peripheral portion of said diffused first region 110; stressing said polysilicon-bounded test diode 100; and monitoring said stressed polysilicon-bounded test diode for spikes in gate current during said stress.