Patent ID: 8674342
Filing Date: 2014-03-18
Classification: B82Y,H01L,Y10S

Abstract:
1. A non-planar semiconductor device comprising: at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present within a portion of a bulk semiconductor substrate, wherein said semiconductor oxide layer has a topmost surface that is coplanar with a topmost surface of said bulk semiconductor substrate, and wherein no semiconductor pad region is present and connected to end segments of the at least one semiconductor nanowire; a gate surrounding a portion of said at least one suspended semiconductor nanowire; a source region located on a first side of the gate; and a drain region located on a second side of the gate which is opposite said first side of the gate, wherein the source region is in direct contact with an exposed end portion of the at least one suspended semiconductor nanowire, and the drain region is in direct contact with another exposed end portion of the at least one suspended semiconductor nanowire, and said source and drain regions have an epitaxial relationship with the exposed end portions of the suspended semiconductor nanowire.