Patent ID: 6421784
Filing Date: 2002-07-16
Classification: G06F,H03K,H03L

Abstract:
Circuitry for delaying a signal, comprising:a coarse delay element (CDE) coupled to a delay circuitry input node for receiving a delay circuitry input signal, and having an output node for outputting a CDE output signal, wherein the CDE receives at least one CDE control signal for selecting a CDE delay time, the CDE output signal being responsive to the delay circuitry input signal, and delayed with respect to the delay circuitry input signal according to the selected CDE delay time; a fine delay element (FDE) coupled to the delay circuitry input node for receiving the delay circuitry input signal, coupled to the CDE output node for receiving the CDE output signal, and having an output node for outputting an FDE output signal, wherein the FDE receives at least one FDE control signal for selecting i) an FDE delay time, and ii) an operative FDE input signal, from the delay circuitry input signal and the CDE output signal, the FDE output signal being responsive to the operative FDE input signal, and delayed with respect to the operative FDE input signal according to the selected FDE delay time.