Patent ID: 7619547
Filing Date: 2009-11-17
Classification: G09G,H03M

Abstract:
1. A serial-to-parallel converter circuit for converting serial data into parallel data to be output, comprising: an m-bit serial data holding unit configured to be input with serial data and a serial clock synchronized with the serial data, an input bit number of the serial data being set to be m bits or n bits smaller than the m bits within a transfer period from transfer start to transfer completion, and configured to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit configured to identify whether the input bit number is m bits or n bits, based on an count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit configured to output m-bit data held in the m-bit serial data holding unit as first parallel data when the input mode identifying unit identifies the input bit number to be m bits, and configured to output m-bit data obtained by adding predetermined (m−n)-bit data to n-bit data held in the m-bit serial data holding unit as second parallel data when the input mode identifying unit identifies the input bit number to be n bits.