Patent ID: 8716770
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A solid-state imaging apparatus comprising: a plurality of photoelectric conversion elements arranged in a semiconductor substrate to convert light into an electric charge, and which includes a first photoelectric conversion element and a second photoelectric element; a first semiconductor region, wherein electric charge is transferred from the first photoelectric conversion element to the first semiconductor region; a second semiconductor region, wherein electric charge is transferred from the second photoelectric conversion element to the second semiconductor region; an amplifying MOS transistor, wherein the amplifying MOS transistor has a common gate electrode electrically connected to the first and second semiconductor regions to amplify potentials of the first and second semiconductor regions wherein the amplifying MOS transistor is arranged between the first semiconductor region and the second semiconductor region, and wherein the first semiconductor region, the second semiconductor region, and the gate electrode of the amplifying MOS transistor are arranged in a straight line; a reset MOS transistor, wherein the reset MOS transistor has a third semiconductor region; a fourth semiconductor region, wherein the fourth semiconductor region is different from the first semiconductor region, the second semiconductor region, and the third semiconductor region; metal wiring layers arranged above the semiconductor substrate, and including a lowest metal wiring layer; interlayer insulating films arranged above the semiconductor substrate, and including a first interlayer insulating film, wherein the first interlayer film is arranged between the lowest metal wiring layer and the semiconductor substrate, and is arranged above the plurality of photoelectric conversion elements, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the amplifying MOS transistor; and a local interconnect of a first conductor electrically connecting the gate electrode of the amplifying MOS transistor and the first semiconductor region, wherein the local interconnect is within the first interlayer insulating film; wherein the local interconnect extends, along the straight line, from a position above the first semiconductor region to a position above the third semiconductor region across a position above the gate electrode of the amplifying MOS transistor and a position above the second semiconductor region, wherein the local interconnect forms a connection between the first semiconductor region, the gate electrode of the amplifying MOS transistor, the second semiconductor region and the third semiconductor region, and wherein a contact plug directly connecting the fourth semiconductor region, and connecting to at least a part of the lowest metal wiring layer, wherein the contact plug is within the first interlayer insulating film.