Patent ID: 6069081
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method of planarizing a dielectric coating applied over an underlying structure on an integrated circuit wafer, said underlying structure having elevated and recessed areas, the method comprising the steps of:applying a first polish stop on said elevated areas;depositing over said underlying structure a conformal layer of dielectric wherein said deposited conformal layer of dielectric has a thickness which is less than or equal to a step height of the underlying structure, said conformal layer of dielectric extending into said recessed areas and over said elevated areas of said underlying structure;depositing a second polish stop over the conformal layer of dielectric;polishing said second polish stop using a first slurry until said second polish stop is substantially removed over the elevated areas; andpolishing said dielectric using a second slurry which is different from said first slurry and which polishes said dielectric at a faster rate than either said second or first polish stop until said first polish stop is exposed, whereby said second polish stop protects said dielectric in said recessed areas.