Patent ID: 7464201
Filing Date: 2008-12-09
Classification: G06F

Abstract:
1. A process for a host a controller having at least one pointer pair, each said pointer pair having a head pointer and a tail pointer, said controller receiving packets from one or more sources and placing them in a memory having a plurality of memory slots, each memory slot including a descriptor status bit having the value FREE or USED, a descriptor memory, and a data segment memory, the process having: a first step of receiving said packets including a header and packet data; a second step of searching said memory slots for a current available slot having a said descriptor status bit with the value FREE; setting said descriptor status bit to the value USED; writing said packet header into said current available slot descriptor memory, writing said packet data into said current available slot data segment memory and for any remaining unwritten said packet data, finding a next available memory slot having said descriptor status bit set to FREE, changing said next available slot descriptor status bit to USED, and writing the location of said next available slot into said current available slot descriptor memory, setting associated said tail pointer to said next available slot; a third step of changing said second step next available slot to said current available slot and repeating said second step and said third step until no unwritten said packet data remains.