Patent ID: 7573109
Filing Date: 2009-08-11
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a resistance layer of a first conductivity type; a plurality of guard buried regions of a second conductivity type formed inside the resistance layer and concentrically disposed; a plurality of base diffusion regions of the second conductivity type disposed inside an innermost guard buried region and at least one of the plurality of base diffusion regions is positioned in the vicinity of an inner surface of the resistance layer; a source diffusion region of the first conductivity type formed in the vicinity of an inner surface of each of the base diffusion regions and the source diffusion region is positioned inside region of an edge of each of the base diffusion regions and has a depth shallower than each of the base diffusion regions; a channel region in the vicinity of the edge of each of the base diffusion regions and between the edge of each of the base diffusion regions and an edge of each of the source diffusion regions; a gate insulating film positioned at least on each of the channel regions; a gate electrode film positioned on the gate insulating film; and a plurality of base buried regions of the second conductivity type and a set of a plurality of the base buried regions is provided at the bottom of each of the base diffusion regions and connected to the respective base diffusion regions, wherein a distance Wm the bottom of each of the base buried regions and the bottom of each of the guard buried regions being positioned substantially in the same depth, the bottoms of the respective base diffusion regions being positioned substantially in the same depth, and an impurity quantity Q