Patent ID: 6771725
Filing Date: 2004-08-03
Classification: G01R,H04B,H04L

Abstract:
A method for generating a set of clock signals in a system, the set of clock signals comprising a set of sampling clock signals and a receive clock signal, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of the sampling clock signals, the digital sections operating in accordance with the receive clock signal, the method comprising the operations of:(a) generating a phase error for each of the sampling clock signals; (b) filtering each of the phase errors to produce filtered phase errors; (c) converting the filtered phase errors to analog filtered phase errors; (d) inputting each of the analog filtered phase errors to a corresponding oscillator; and (e) generating the sampling clock signals with the corresponding oscillators based on the analog filtered phase errors; wherein the receive clock signal is related to one of the sampling clock signals.