Patent ID: 7037803
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising the steps of: (a) forming a polishing stopper layer over a surface of a semiconductor substrate; (b) forming a trench in said semiconductor substrate by etching said stopper layer and said semiconductor substrate; (c) forming a first liner insulating layer of silicon oxide over a surface of said semiconductor substrate exposed in said trench; (d) forming a second liner insulating layer of silicon nitride in direct contact with said first liner insulating layer, said second liner insulating layer having a thickness of 20 nm or thicker; (e) depositing an isolation layer of silicon oxide by plasma CVD, said isolation layer burying a recess defined by said second liner insulating layer; (f) polishing and removing an unnecessary region of said isolation layer by using said stopper layer as a polishing stopper; (g) etching said stopper layer; and wherein said second liner insulating layer has a tensile stress of 1.2 GPa or larger.