Patent ID: 6030891
Filing Date: 2000-02-29
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device, which method comprises sequentially:forming a first dielectric layer on a substrate;forming a first patterned conductive layer, having gaps therein and comprising a first conductive feature, on the first dielectric layer;depositing a layer of hydrogen silsesquioxane (HSQ) filling the gaps;depositing a second dielectric layer on the first patterned conductive layer and on the HSQ gap fill layer;planarizing an upper surface of the second dielectric layer;forming a through-hole in the second dielectric layer exposing a portion of the upper surface and at least a portion of a side surface of the first conductive feature, and penetrating into and exposing a portion of the HSQ gap fill layer;vacuum baking; andfilling the through-hole with a conductive material to form a borderless via.