Patent ID: 6473700
Filing Date: 2002-10-29
Classification: G01R

Abstract:
Apparatus for rapidly producing a compressed display of data in a logic analyzer, comprising:a memory for storing logic state samples representing the behavior over time of one or more input signals; a starting memory address register for storing a starting memory address; an ending time stamp comparator for comparing a current time stamp with an ending time stamp to determine the last sample associated with a given pixel, said starting address and said ending timestamp defining a timeslice; hardware circuitry for compressing data descriptive of waveform activity during said timeslice by using said hardware circuitry to compare current sample data with reference data; and further comprising a display screen for displaying waveform data; and a controller for controlling said display screen; said controller loading said starting memory address into said starting memory address register; said controller loading said ending time stamp into said comparator; said hardware circuitry evaluating data read from said acquisition memory beginning at said starting address, incrementing said memory address and reading a current timestamp until said current timestamp value exceeds said ending timestamp value; said controller receiving only said compressed waveform data for display.