Patent ID: 7851235
Filing Date: 2010-12-14
Classification: H01L

Abstract:
1. A method comprising: forming device isolation layers over a first conductivity type semiconductor substrate; forming a second conductivity type well over the first conductivity type semiconductor substrate; forming first conductivity type impurity regions in first active areas of active areas defined by areas between the device isolation layers in the second conductivity type well; forming silicide layers over the first conductivity type impurity regions; forming monitoring contacts within the first active areas to monitor leakage current to detect misalignment of contacts and leakage current due to the misalignment; forming well pickup contacts within second active areas to surround the monitoring contacts, thereby absorbing leakage current flowing through the second conductivity type well; forming a first metal line to connect the monitoring contacts; and forming a second metal line to connect the well pickup contacts formed within the second active areas, wherein both the first metal line and the second metal line are serving as electrodes for leakage current measurement, wherein the device isolation layers, the second conductivity type well, the first conductivity type impurity regions, and the monitoring contacts as a test element group for monitoring leakage current in a semiconductor device, wherein the silicide layers are formed to reduce contact resistance between the monitoring contacts and the first conductivity type impurity regions.