Patent ID: 6466053
Filing Date: 2002-10-15
Classification: G11C,H01L,H03K

Abstract:
A memory circuit comprising:a logic circuit including an array of storage cells, an address decoder coupled to said array of storage cells, and a memory controller coupled to said array of storage cells; a first signal path having a first segment coupled to said logic circuit and a plurality of second segments, each of said plurality of second segments independent from one another; a routing matrix circuit in-line with said first signal path disposed between said first segment and said plurality of second segments, said routing matrix circuit programmable for each of said plurality of second segments between a first state wherein said first segment is coupled to a select one of said plurality of second segments, and a second state wherein said first segment is decoupled from said select one of said plurality of second segments; and, a programming circuit coupled to said routing matrix circuit, said programming circuit arranged to selectively program said routing matrix circuit between said first and second states for each of said plurality of second segments.