Patent ID: 7225284
Filing Date: 2007-05-29
Classification: G06F

Abstract:
1. A method of increasing the quantity of input/output (I/O) decode ranges in a chipset, comprising: generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap, the I/O address operably received at the chipset via a bus; automatically reprogramming a decode register in the chipset to include the I/O address such that the chipset forwards the information to a device on the bus; automatically entering a SMI handler based on the generation of the SMI; upon entry into the SMI handler, deactivating the SMI trap and resending information that accesses the I/O address to allow the information to be forwarded to the device on the bus; and following the resend, re-activating the SMI trap.