Patent ID: 6731567
Filing Date: 2004-05-04
Classification: G11C

Abstract:
A DDR memory having a plurality of memory cells which each have a prescribed word length, which comprises:(a) a first clock signal input for receiving a system clock signal; (b) a second clock signal input for receiving a data clock signal; (c) an instruction input for reading in and decoding a write instruction which is synchronized with the system clock signal; (d) a serial data input for reading in serial data on a rising edge and on a falling edge of the data clock signal; and (e) a serial-parallel converter for putting together a prescribed number of data items from the data read in to give a prescribed number of words from data words having a prescribed word length, wherein an interface memory which copies the at least one data word from the serial-parallel converter when it receives a copy signal which is synchronous with the data clock signal, and which outputs the at least one data word to a bus when it receives an output signal which is synchronous with the system clock signal.