Patent ID: 7446589
Filing Date: 2008-11-04
Classification: G06F,H03K

Abstract:
1. A pulse generation circuit comprising: a P-type MOS transistor having a gate electrode and a source electrode that is connected to a first power source line; a first N-type MOS transistor having a gate electrode and a drain electrode that is connected to a drain electrode of said P-type MOS transistor; a second N-type MOS transistor having a drain electrode that is connected to a source electrode of said first N-type MOS transistor, a gate electrode that is connected to only an input line to which an input pulse signal is inputted, and a source electrode that is connected to a second power source line; a delay circuit having an input terminal that is connected to the drain electrode of said P-type MOS transistor and to the drain electrode of said first N-type MOS transistor directly, and an output terminal that is connected to the gate electrode of said P-type MOS transistor and to the gate electrode of said first N-type MOS transistor, the delay circuit setting a delay-period arbitrarily; an inverter having an input terminal that is connected to the drain electrode of said P-type MOS transistor and to the drain electrode of said second N-type MOS transistor, and an output terminal that is connected to an output line to which a generated pulse is outputted; and a keeper keeping a voltage level of the line to which the input terminal of said inverter is connected, wherein when the input pulse signal is inputted to the input line, an output pulse having a pulse width corresponding to said delay period of said delay circuit is generated.