Patent ID: 6534365
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A method of fabricating a vertical TDMOS (Trench Double diffused MOS) power device, comprising the steps of:forming a first insulating film and a second insulating film over a n-type substrate, sequentially; forming a photo-resist (PR) film over the second insulating film; removing a predetermined portion of the second insulating film by etching the second insulating film using a first mask, and implanting p-type ions into an entire surface of a resultant structure; forming a channel layer beneath the first insulating film by heat treating after removing the PR film; forming a sidewall spacer on the side wall of the remaining second insulating film; forming a trench by etching the channel layer using both of the remaining second insulating film and the sidewall spacer as a mask to expose the substrate; implanting n-type ions into the entire surface of a resultant structure after removing the side wall spacer; forming a gate oxide film on the surface of the trench, and forming an n-type impurity region in the region of the channel layer adjacent to the trench and in a region of the substrate under the bottom of the trench by thermal treatment; forming a gate electrode within said trench by etch-back process using a second mask; forming an LTO film on the gate electrode and then removing all the remaining second insulating film; forming a body contact by implanting p-type ions into a region of the first insulating film using the LTO film as a mask and depositing a metal film on an entire surface; and forming a source electrode by etching the metal film using a third mask to expose a center region of the LTO film.