Patent ID: 8003454
Filing Date: 2011-08-23
Classification: H01L

Abstract:
1. A semiconductor fabrication process for forming a PMOS field effect transistor device, comprising: forming a first biaxial-tensile strained semiconductor layer; selectively relaxing a channel region portion of the first biaxial-tensile strained semiconductor layer where one or more PMOS transistor devices will be formed, thereby forming a PMOS active layer; epitaxially growing a second semiconductor layer on the PMOS active layer having a larger atom-to-atom spacing than the underlying PMOS active layer; and forming at least a PMOS gate structure overlying the second semiconductor layer to define a PMOS transistor channel region, the PMOS transistor channel region comprising at least a portion of the second semiconductor layer below the PMOS gate structure, the PMOS transistor channel region in the second semiconductor layer being subjected to biaxial compressive stress.