Patent ID: 7266747
Filing Date: 2007-09-04
Classification: G06F,H03M

Abstract:
1. A method of detecting and purging bit errors in a memory, comprising: a) executing a read operation for providing a data word to a local databus and for providing a corresponding row parity bit, from a memory block of the memory; b) comparing row parity of the data word on the local databus against the corresponding row parity bit and generating a row parity fail flag in response to row parity failure; c) iteratively multiplexing bits of the data word from the local databus onto a corresponding global dataline for comparing column parity of each bit of the data word against a corresponding bit of a column parity word stored in a parity block of the memory, in response to the row parity fail flag; and, d) inverting bits of the data word that fail column parity.