Patent ID: 6590244
Filing Date: 2003-07-08
Classification: B82Y,G11C,H01L

Abstract:
A semiconductor memory device comprising a memory cell section and a peripheral circuit section disposed at a periphery of the memory cell section, the memory cell section comprising:a first wiring which is extended in a first direction; a second wiring which is disposed above the first wiring and is extended in a second direction different from the first direction; a third wiring which is disposed between the first and second wirings; and a first magneto resistive effect element which is disposed at an intersection of the first and second wirings between the first and second wirings, and is connected to the second and third wirings, and the peripheral circuit section comprising: a fourth wiring; a fifth wiring which is disposed above the fourth wiring; and a second magneto resistive effect element which is disposed between the fourth and fifth wirings and is connected to the fourth and fifth wirings to be used as any of a resistive element, a fuse element, and a contact.