Patent ID: 6916738
Filing Date: 2005-07-12
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming a first insulating layer on a semiconductor having capacitor contact regions; forming bit lines on the first insulating layer between the capacitor contact regions, wherein each of the bit lines includes a first conductive pattern and a bit line mask pattern; forming a second insulating layer composed of an oxide based material on the bit lines and on the first insulating layer; forming contact patterns on the second insulating layer that open storage node contact hole regions, wherein each of the contact patterns comprises a material having an etching selectivity relative to the second insulating layer; partially etching predetermined portions of the second insulating layer using the contact patterns as a mask; forming first spacers on sidewalls of the etched portions of the second insulating layer, wherein each of the first spacers includes a material having an etching selectivity relative to the second insulating layer; simultaneously forming storage node contact holes exposing the capacitor contact regions and second spacers comprising portions of the second insulating layer on sidewalls of the bit lines beneath the first spacers by etching the second and first insulating layers using the first spacers as a mask; and forming storage node contact pads by filling the storage node contact holes with a second conductive layer.