Patent ID: 6211025
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method of fabricating a transistor on a substrate, comprising the steps of:forming a semiconductor layer on the substrate;forming an intermediary layer on the semiconductor layer and a top layer on the intermediary layer, the top layer being etch selective to the intermediary layer and the intermediary layer being etch selective to the semiconductor layer;forming a via in the intermediary layer, the top layer and the semiconductor layer extending to the substrate;forming an insulting layer in the via, the insulating layer having first and second sidewall spacers;forming a gate electrode on the insulating layer;removing the top and intermediary layers following the step forming the gate electrode layer; andforming first and second source/drain regions, wherein each of the first and second source/drain regions has a first portion positioned in the semiconductor layer and a second portion positioned in the substrate.