Patent ID: 6704914
Filing Date: 2004-03-09
Classification: G06F

Abstract:
A high level synthesis method for generating a logic circuit of a register transfer level from an operation description, the method comprising:a control data flowgraph generation stage of analyzing the operation description describing a processing operation and not including information regarding a hardware structure, and generating a control data flowgraph which represents a dependency relationship among calculations, input to and output from an external device, and a memory access execution order; a scheduling stage of scheduling each of a plurality of nodes of the control data flowgraph to a step corresponding to a state of a controller; an allocation stage of generating a calculator, a register, and input and output pins which are required to execute the scheduled control data flowgraph, and allocating a calculation of the control data flowgraph to the calculator, allocating a data dependency edge crossing a border between steps to the register, and allocating an external input, an external output and a memory access to the input and output pins; a data path generation stage of generating a data path corresponding to the data dependency edge of the control data flowgraph and generating a selector when necessary; and a control logic generation stage of generating a control logic for controlling the register and the selector generated in the allocation stage and the data path generation stage, wherein when generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of the control data flowgraph so as to perform scheduling, and a control logic is generated, which outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and which keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.