Patent ID: 8904256
Filing Date: 2014-12-02
Classification: G01R

Abstract:
1. A computer-implemented method of generating scan test circuitry for insertion into an integrated circuit design, comprising: receiving an integrated circuit design for storage in memory; instantiating in the integrated circuit design a deserializer, a decompressor, a plurality of cores comprising a plurality of scan chains comprising scan chain registers, and a controller, wherein the deserializer is configured to receive a serial input signal comprising a parallel output from an automatic test-pattern generator that has been compressed and manipulated into a serial bitstream, and wherein the deserializer is configured to output a parallel compressed signal, and wherein the decompressor is configured to receive the parallel compressed signal and outputs a plurality of test patterns; and configuring the controller so that it will transmit a plurality of scan clocks to the plurality of scan chains during scan testing to shift the plurality of scan chain registers, wherein each clock pulse of a first of the plurality of scan clocks are interleaved with each clock pulse of a second of the plurality of scan clocks to sequentially shift the plurality of scan chain registers of the plurality of cores.