Patent ID: 8673724
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a substrate which comprises a first region having a gate pattern and a second region having a first trench and a first insulating layer which fills the first trench; exposing a portion of a sidewall of the first trench by etching part of the first insulating layer; forming a second insulating layer on the substrate and forming a first spacer on a sidewall of the gate pattern and a second spacer on the exposed sidewall of the first trench by etching the second insulating layer, the first spacer and the second spacer being formed substantially simultaneously; forming a second trench by etching the first region on each of both sides of the gate pattern; forming a semiconductor pattern in the second trench; forming an interlayer insulating layer on the substrate; and forming an interlayer insulating pattern having an aperture on the semiconductor pattern by etching the interlayer insulating layer, wherein after forming the interlayer insulating pattern, the aperture includes a region that is formed to a depth that is lower than a boundary surface between the first insulating layer and the second spacer.