Patent ID: 6607950
Filing Date: 2003-08-19
Classification: H01L

Abstract:
A method of forming a MIS transistor comprising the steps offorming an active area region on a semiconductor substrate; forming a temporary gate stack within said active area region, the temporary gate stack comprising a top layer of a first material; forming spacers aligned with and adjacent to said temporary gate stack, said spacers comprising a second material, wherein said second material being selectively removable with respect to said first material; depositing a first dielectric layer on top of said semiconductor substrate; forming a Pre-Metal Dielectric (PMD) layer on top of said first dielectric layer; selectively removing said PMD layer at a removal rate that is higher than removal rate of said top layer, until said top layer of said temporary gate stack is exposed; removing said temporary gate stack thereby creating a cavity in said first dielectric layer, and forming at least in said cavity a stack of a high-k dielectric and a stack of at least one conductive layer.