Patent ID: 7739419
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A data transfer control device having a bus bridge function between a Parallel ATA and a Serial ATA, the data transfer control device comprising: a Parallel ATA interface that is connected to a Parallel ATA bus and interfaces between the data transfer control device and a host; a Serial ATA interface that is connected to a Serial ATA bus and interfaces between the data transfer control device and a Serial ATA device; and a sequence controller that controls a transfer sequence, the Parallel ATA interface including a task file register; and when the host has issued an ATA packet command, the sequence controller suspending transmission of a register FIS corresponding to the ATA packet command to the device, performing a dummy setting that causes the host to issue an ATAPI packet command corresponding to the ATA packet command using the task file register, and transmitting the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command, a command packet of the ATAPI packet command being set in a data register of the task file register.