Patent ID: 6768207
Filing Date: 2004-07-27
Classification: H01L

Abstract:
A multichip wafer-level package, comprising:a first chip having a semiconductor device, a first bonding ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit; a second chip having an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip; a bump ring disposed between the first bonding ring of the first chip and the second bonding ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity for accommodating the semiconductor device; and a plurality of bumps electrically connecting the internal bonding pads of the first chip to the bonding pads of the second chip.