Patent ID: 7994623
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first semiconductor integrated circuit including a first three-dimensional coupling circuit; a second semiconductor integrated circuit including a first feed-through electrode and a second three-dimensional coupling circuit for inductively coupling to the first three-dimensional coupling circuit; and a third semiconductor integrated circuit including a second feed-through electrode connected to the first feed-through electrode, and a third three-dimensional coupling circuit inductively coupling to the first three-dimensional coupling circuit, wherein the first, second, and third semiconductor integrated circuits are stacked, wherein the second semiconductor integrated circuit includes a first and a second three-dimensional receive circuit, and a first and a second three-dimensional transmit circuit, and is stacked between the first semiconductor integrated circuit and the third semiconductor integrated circuit, wherein data from the first semiconductor integrated circuit received by way of the first three-dimensional receive circuit is sent by way of the second three-dimensional transmit circuit to the third semiconductor integrated circuit, wherein data from the third semiconductor integrated circuit received by way of the second three-dimensional receive circuit is sent by way of the first three-dimensional transmit circuit to the first semiconductor integrated circuit, wherein the first and the second three-dimensional receive circuits, and the first and the second three-dimensional transmit circuits in the second semiconductor integrated circuit are positioned in the order of: the first three-dimensional transmit circuit, the first three-dimensional receive circuit, the second three-dimensional receive circuit, and the second three-dimensional transmit circuit, wherein the second semiconductor integrated circuit and the third semiconductor integrated circuit have an identical construction and functions, and wherein the third semiconductor integrated circuit is stacked on the second semiconductor integrated circuit with an offset such that the first three-dimensional transmit circuit of the third semiconductor integrated circuit is aligned with the second three-dimensional receive circuit of the second semiconductor integrated circuit.