Patent ID: 7665652
Filing Date: 2010-02-23
Classification: H01L,H05K

Abstract:
1. An electronic device comprising: a substrate including semiconductor portions thereof; first and second input/output pads on the substrate; and first and second metallurgy structures on the respective first and second input/output pads, the first and second metallurgy structures having a same structure adapted to receive solder and wire bonds wherein the first metallurgy structure comprises a first underbump metallurgy layer on the first input/output pad, a first barrier layer on the first underbump metallurgy layer, and a first passivation layer on the first barrier layer, and wherein the second metallurgy structure comprises a second underbump metallurgy layer on the second input/output pad, a second barrier layer on the second underbump metallurgy layer, and a second passivation layer on the second barrier layer; wherein the first metallurgy structure comprises a first underbump metallurgy layer on the first input/output pad, a first barrier layer on the first underbump metallurgy layer, and a first passivation layer on the first barrier layer, and wherein the second metallurgy structure comprises a second underbump metallurgy layer on the second input/output pad, a second barrier layer on the second underbump metallurgy layer, and a second passivation layer on the second barrier layer.