Patent ID: 7034868
Filing Date: 2006-04-25
Classification: H04N

Abstract:
1. An image processing circuit comprising: an image pickup sensor configured to be driven by an interlacing system of reading image signals from an odd field and an even field at temporally different timings, said odd field consisting of only odd lines of an image and said even field consisting of only even lines of said image; a buffer part configured to store pixel data of a first field, said first field being defined to be only one of said odd field or said even field; and an image processing part configured to read pixel data from said first field stored in said buffer part in synchronization with reading pixel data of a second field said second field being an even field if the first field is an odd field or an odd field if the first field is an even field and to simultaneously process said pixel data of both said first and second fields in real time, wherein said image processing part includes a pixel interpolation unit configured to sequentially interpolate pixel data, of a plurality of lines of said image during respective fractions of a same single reading cycle of a pixel transfer clock configured to drive said image pickup sensor.