Patent ID: 9133021
Filing Date: 2015-09-15
Classification: B81B,B81C,H01L

Abstract:
1. A wafer level package, comprising: a pressure sensor having a substrate and an intermetal dielectric layer formed on the substrate, a top cavity formed on a top surface of the intermetal dielectric layer, and a bottom opening penetrating the substrate and corresponding in position to the top cavity, wherein the intermetal dielectric layer is a circuit layer formed by a silicon material; a first seal ring formed on the pressure sensor that surrounds the top cavity, wherein the first seal ring is free from being integrated with the pressure sensor; a plurality of electrical connecting pads formed on a circumference of the top cavity; a sensor film installed between the top cavity and the bottom opening and connected to an inner rim of the top cavity; a lid bonded to the pressure sensor via a bottom surface of the lid, to thereby form a cavity chamber thereinbetween; a second seal ring formed on a bottom surface of the lid and correspondingly bonded to the first seal ring, wherein the second seal ring is free from being integrated with the lid and the first seal ring; a plurality of bonding wires each having one end in contact with a respective one of the electrical connecting pads, and electrically connecting the electrical connecting pads; an encapsulant formed on the pressure sensor and the lid for encapsulating the bonding wires, with another end of each of the bonding wires being exposed from a top surface of the encapsulant; and a redistribution layer formed on the top surface of the encapsulant and electrically connected to the another end of each of the bonding wires.