Patent ID: 7569881
Filing Date: 2009-08-04
Classification: G11C,H01L,H03K

Abstract:
1. A semiconductor integrated circuit device comprising: a plurality of static type memory cells each having a first P-channel transistor, a second P-channel transistor, a first N-channel transistor and a second N-channel transistor, a drain of the first P-channel transistor, a drain of the first N-channel transistor, a gate of the second P-channel transistor and a gate of the second N-channel transistor being connected to each other, and a drain of the second P-channel transistor, a drain of the second N-channel transistor, a gate of the first P-channel transistor and a gate of the first N-channel transistor being connected to each other; a word line connected to the plurality of static type memory cells; a power line connected to sources of the first and second P-channel transistors of the plurality of static type memory cells; and a source line connected to sources of the first and second N-channel transistor of the plurality of static type memory cells; wherein insulating layers used in gates of the first P-channel transistor, the second P-channel transistor, the first N-channel transistor and the second N-channel transistor have a thickness of 4 nm or less, wherein in a first state, a potential of the power line is a first potential and a potential of the source line is a second potential lower than the first potential, wherein in a second state, the potential of the power line is the first potential and the potential of the source line is a third potential between the first potential and the second potential, and wherein the plurality of static type memory cells connected to the word line are not selected to read out an information stored in the plurality of static type memory cells in a period in which the power line and the source line are in the second state.