Patent ID: 6366634
Filing Date: 2002-04-02
Classification: G11C

Abstract:
An address binary counter for an interleaved memory having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells, each bank of memory cells being organized into rows and columns and the interleaved memory operating in a burst access mode responsive to an enabling signal, the address binary counter comprising:a plurality of stages equal to a number of address bits for storing in memory cells of a row in one of the first and second banks of memory cells; and a carry calculation network comprising an ordered group of independent carry generators each having a predetermined number of stages, and each independent carry generator including an input for receiving an enabling bit and inputs for receiving a number of consecutive bits of a row in one of the first and second banks of memory cells, the enabling bit of a first carry generator of the ordered group of independent carry generators is the enabling signal, and the enabling bit of any other carry generator of the ordered group of independent carry generators is a logic AND of the enabling signal and of input bits of a preceding carry generator of the ordered group of independent carry generators, and an output for providing a carry bit.