Patent ID: 7627735
Filing Date: 2009-12-01
Classification: G06F,Y02D

Abstract:
1. A system comprising: an address generator to receive information corresponding to a vector memory instruction and to generate a plurality of addresses from the vector memory instruction, wherein the address generator is to permute the information into the plurality of addresses, wherein the plurality of addresses provide first conflict-free access to a plurality of partitions of a memory and second conflict-free access to a plurality of clusters of a register file, the address generator including a global unit coupled to a plurality of independent address generators, each associated with a different bank of the memory, wherein the global unit is to broadcast to the plurality of independent address generators a factorized stride based on stride information, a first factor, and a second factor that describes a distance between a pair of elements associated with a pair of addresses located in the same memory bank and consecutive line positions, and responsive to the broadcast, the plurality of independent address generators are to each output an address for the associated memory bank, a valid indicator, and an index to identify ordering of the elements in an output vector; and a dynamic random access memory (DRAM) coupled to the address generator.