Patent ID: 9094040
Filing Date: 2015-07-28
Classification: H03M

Abstract:
1. An analogue-to-digital converter, ADC, comprising: a first continuous-time, CT, delta-sigma, ΔΣ, modulator comprising a first analogue stage arranged to generate a first error signal dependent on an input signal, a first feedback signal and a second feedback signal, a first quantiser arranged to generate a first quantised signal by quantising the first error signal into at least three levels at a first sample rate, and a first digital-to-analogue converter, DAC, arranged to generate the first feedback signal from the first quantised signal; a second, first order CT ΔΣ modulator comprising a second analogue stage arranged to generate a second error signal dependent on the first error signal, the first feedback signal and the second feedback signal, a second quantiser arranged to generate a second quantised signal by quantising the second error signal into two levels at a second sample rate, and a second DAC arranged to generate the second feedback signal from the second quantised signal; and an output stage arranged to generate an output signal by summing the first quantised signal and the second quantised signal.