Patent ID: 7706202
Filing Date: 2010-04-27
Classification: G11C,H01L

Abstract:
1. A semiconductor device having a plurality of metal interconnection layers, and comprising: internal circuitry including a transistor element connected to interconnects in said plurality of metal interconnection layers; and at least one fuse program circuit including (i) a fuse element formed using an interconnect in a metal interconnection layer higher than a first metal interconnection layer at the lowest metal interconnection layer in said plurality of metal interconnection layers, and (ii) a fuse transistor element, connected in series to said fuse element, for selectively passing a current for blowing said fuse element, for storing fixedly information related to said internal circuitry according to a blown or non-blown state of said fuse element set according to fuse program information, wherein said fuse element includes copper material, said fuse transistor element is arranged below said fuse element, a source region of said fuse transistor element is arranged below a first metal interconnect formed in a second metal interconnection layer of said plurality of metal interconnection layers and said source region is connected to said first metal interconnect, a drain region of said fuse transistor element is arranged below a second metal interconnect formed in said second metal interconnection layer and said drain region is connected to said second metal interconnect, and after a reset operation is implemented to a drive circuit for driving a gate of said fuse transistor element, said first and second metal interconnects are kept at same potential as a potential at opposite ends of said fuse element in periods without a blowing operation of said fuse element and a cut determining operation of said fuse element.