Patent ID: 6117738
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method for fabricating a high-bias device, the method comprising:providing a P-type substrate;forming an oxide layer on the substrate;forming a first P well and a first N well in the substrate, wherein the first P well has greater dopant density than that of the substrate;forming a second P well in the first P well;forming a second N well separately in the first N well and in the second P well;removing the oxide layer;forming a gate oxide layer and a field oxide layer on the substrate, wherein the field oxide layer is on both the first N well and the second N well;forming a gate layer on a portion of the gate oxide layer and the field oxide layer, wherein the gate layer extends to the second N well;forming a source/drain region in the second N well, wherein the source/drain region is doped with an N-type dopant; andforming a P.sup.+ doped region abutting to the source/drain region in the second P well by implanting a P-type dopant.