Patent ID: 9165500
Filing Date: 2015-10-20
Classification: G09G

Abstract:
1. A pixel circuit having first and second power source voltages, the pixel circuit comprising: an organic light emitting diode, a cathode electrode of the organic light emitting diode being coupled to the second power source voltage; a first p-channel metal oxide semiconductor (PMOS) transistor having a first electrode, a second electrode coupled to an anode electrode of the organic light emitting diode, and a gate electrode coupled to a gate control-line; a second PMOS transistor having a first electrode and having a second electrode coupled to the first electrode of the first PMOS transistor; a third PMOS transistor having a first electrode coupled to the first power source voltage, a second electrode coupled to the first electrode of the second PMOS transistor, and a gate electrode coupled to the gate control-line; a fourth PMOS transistor having a first electrode coupled to the gate electrode of the second PMOS transistor, a second electrode coupled to the anode electrode of the organic light emitting diode, and a gate electrode coupled to a scan-line; and a storage capacitor having a first electrode coupled, in common, to the first electrode of the second PMOS transistor and a data-line, and a second electrode coupled to the gate electrode of the second PMOS transistor, wherein during an initialization period, the first power source voltage is set as a first voltage lower than the second power source voltage, the gate electrode of the first PMOS transistor and the gate electrode of the third PMOS transistor receive a gate control signal having a logic low level through the gate control-line, and the gate electrode of the fourth PMOS transistor receives a scan signal having a logic high level through the scan-line.