Patent ID: 6913990
Filing Date: 2005-07-05
Classification: H01L

Abstract:
1. A method of planarizing active layers of devices on a semiconductor structure comprising the steps of: providing a semiconductor structure, said semiconductor structure having a top layer of dielectric material and areas of metallization defined in the top surface of said top layer of dielectric material; depositing tunneling magneto-resistance “TMR” devices at selected locations over said areas of metallization, said TMR devices having a known height above said top surface of said top layer of dielectric material; depositing a first dielectric layer over said top surface of said top layer of dielectric material and over said TMR devices; forming a dummy layer of dielectric material over said first dielectric layer to a thickness equal to said known height of said TMR devices; forming a dummy structure pattern mask over said dummy layer of dielectric material; etching said dummy layer of dielectric material selective to said first dielectric layer so as to leave portions of said dummy layer as dummy structures on said top surface of said top layer of dielectric material, said dummy structures having a height equivalent to said known height; and depositing another layer of dielectric material over said TMR devices and said dummy structures, said another layer of dielectric material having a thickness at least greater than said known height of said TMR devices.