Patent ID: 7094679
Filing Date: 2006-08-22
Classification: H01L,Y10S

Abstract:
1. A method for fabricating an electrical interconnect, the method comprising: depositing a selected conductive substance of a first selected thickness on a substrate of selected material; depositing a selected catalyst substance in a selected pattern in a selected second thickness on the conductive substance; growing an array of one or more spaced apart multi-wall carbon nanotubes (“MWCNTs”) on the selected pattern to a selected MWCNT third thickness, using a plasma enhanced CVD process, so that each MWCNT is oriented at approximately a selected angle θ, relative to an exposed surface of the conductive substance at a first end of the at least one MWCNT; depositing a selected insulator material around at least one MWCNT so that the selected insulator encapsulates the at least one MWCNT; and performing chemical mechanical polishing of the selected insulator and of the MWCNT array to provide an approximately planar surface of the selected insulator in which a second end of each of the at least one MWCNT is exposed above an exposed surface of the insulator by a distance in a range of 1–50 nm.