Patent ID: 7432689
Filing Date: 2008-10-07
Classification: H02M

Abstract:
1. A switching voltage regulator that operates in buck and boost modes comprising: a dual ramp generator that generates a first ramp waveform and an identical second ramp waveform at a certain frequency, the first ramp waveform being 180 degrees out of phase with the second ramp waveform, the first ramp waveform and the second ramp waveform having a same voltage at a transition level; a clock generator for generating a clock signal and an inverted clock signal having a period equal to a period of the first ramp waveform; an error amplifier receiving a feedback voltage corresponding to an output of the regulator and receiving a reference voltage, an output of the error amplifier being an error signal corresponding to a duty cycle needed to switch at least one buck switching transistor in a power stage, for generating a regulated voltage lower than an input voltage, or switch at least one boost switching transistor in the power stage, for generating a regulated voltage higher than an input voltage, in order to maintain the feedback voltage substantially matching the reference voltage; and an arrangement of logic circuits receiving the first ramp waveform, the second ramp waveform, the clock signal, the inverted clock signal, and the error signal, the arrangement of logic circuits being configured to output either pulse width modulated (PWM) buck control pulses for controlling the at least one buck switching transistor or PWM boost control pulses for controlling the at least one boost switching transistor based on whether the error voltage crosses the first ramp waveform and the second ramp waveform above or below the transition level; wherein the logic circuits comprise a first comparator comparing the first ramp waveform to the error voltage to generate a first comparator signal, and a second comparator comparing the second ramp waveform to the error voltage to generate a second comparator signal; wherein the logic circuits further comprise a plurality of flip flops coupled to signals corresponding to the first comparator signal, the second comparator signal, the clock signal, and the inverted clock signal so as to either output PWM buck control pulses or PWM boost control pulses; wherein only one flip flop at a time outputs PWM buck control pulses or PWM boost control pulses; wherein a first flip flop receives the clock signal and a signal corresponding to the second comparator signal, a second flip flop receives the inverted clock signal and a signal corresponding to the first comparator signal, a third flip flop receives the inverted clock signal and a signal corresponding to the second comparator signal, and a fourth flip flop receives the clock signal and a signal corresponding to the first comparator signal; and wherein the first flip flop and the second flip flop generate PWM boost control pulses, and the third flip flop and the fourth flip flop generate PWM buck control pulses.