Patent ID: 6542399
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A memory, comprising:a first bit line; a first charge-storing element having a first plate and a second plate; a first access device having a first end, a second end and a control terminal, the first end coupled to the first bit line, the second end coupled to the first plate of the first charge-storing element and defining a node, and the control terminal coupled to a first word line; a second bit line; a second charge-storing element having a first plate and a second plate; a second access device having a first end, a second end and a control terminal, the first end coupled to the second bit line, the second end coupled to the first plate of the second charge-storing element and defining a node, and the control terminal coupled to a second word line; a voltage driver circuit having a first output terminal coupled to the second plates of the first and second charge-storing elements, and wherein the voltage driver circuit provides a high logic level voltage to the second plate of the first charge-storing element when a low logic level is present on a first bit line, a low logic level voltage to the second plate of the first charge-storing element when a high logic level voltage is present on a first bit line, and substantially the same voltage as an intermediate voltage to the second plate of the first charge-storing element when the intermediate voltage level is present on the first bit line.