Patent ID: 6321320
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A method of testing and monitoring arrays on an integrated circuit chip having a built-in-self-test (BIST) engine comprising one or more address generation blocks capable of being programmed with an address generation program, one or more data generation blocks capable of being programmed with a data generation program, and a main control block, said method comprising:a) dynamically programming the one or more address generation blocks of the built-in-self-test (BIST) engine with the address generation program to selectively provide address information to one or more on-chip memory arrays;b) dynamically programming the one or more data generation blocks of the BIST engine with the data generation program to selectively provide and receive data information to and from the one or more on-chip memory arrays; andc) dynamically programming the main control block of the BIST engine to coordinate when the one or more address generation blocks execute the address generation program and when the one or more data generation blocks execute the data generation program.