Patent ID: 8635685
Filing Date: 2014-01-21
Classification: G06F

Abstract:
1. A processing system comprising: A. interconnect leads; B. initiator circuits coupled to the interconnect leads; C. initiator firewall circuits coupled to the initiator circuits, there being one initiator firewall circuit for each initiator circuit; D. target circuits coupled to the interconnect leads; E. target firewall circuits coupled to the target circuits, there being one target firewall circuit for each target circuit; F. each of the firewall circuits including programmable qualifier data structure logic and a security violation output lead; G. control circuitry connected to the security violation output lead of the firewall circuits and having a control output; and H. value generator circuitry having an input connected to the control output of the control circuitry and having an output coupled to the programmable qualifier data structure logic of the firewall circuits.