Patent ID: 8145877
Filing Date: 2012-03-27
Classification: G06F,H03M

Abstract:
1. A method for address generation, comprising: obtaining a block size and a skip value; initializing at least one address, at least one increment value, and a step value; wherein the initializing of the at least one address follows from: Π(x)=(f where the increment value Π′(x) is a derivation of the address Π(x), and where n is the skip value and x is a first count index for incrementally counting from a first initial value to a first terminal value; setting, by a processor, a second count index for incrementally counting from a second initial value to a second terminal value, the second terminal value being bounded by the block size; for the second count index not in excess of the second terminal value, iteratively performing: the incrementing to output a sequence of addresses; and outputting the sequence of addresses responsive to iterative generation of the output address.