Patent ID: 7450047
Filing Date: 2008-11-11
Classification: H03M

Abstract:
1. An apparatus including a multiple order sigma-delta modulator, comprising: an input electrode to convey an analog input signal; one or more output electrodes to convey one or more digital output signals; a plurality of analog adder circuits including first and last analog adder circuits, wherein said first analog adder circuit is coupled to said input electrode to receive said analog input signal and a first one of a plurality of analog feedback signals and provide a first one of a plurality of analog added signals, and each remaining one of said plurality of analog adder circuits is to receive a respective upstream one of a plurality of analog integrated signals and a respective additional one of said plurality of analog feedback signals and provide a respective downstream one of said plurality of analog added signals; a plurality of analog integrator circuits including first and last analog integrator circuits, wherein said first analog integrator circuit is coupled to said first analog adder circuit to receive said first one of said plurality of analog added signals and provide a first one of said plurality of analog integrated signals, and each remaining one of said plurality of analog integrator circuits is coupled to a respective upstream one of said plurality of analog adder circuits to receive a respective upstream one of said plurality of analog added signals and provide a respective downstream one of said plurality of analog integrated signals; analog-to-digital converter (ADC) circuitry coupled to said last analog integrator circuit to receive a last one of said plurality of analog integrated signals and provide an N-bit digital signal; a digital adder circuit coupled to said ADC circuitry to receive said N-bit digital signal and a last one of a plurality of digital integrated signals and provide a digital added signal; an output truncation circuit coupled between said digital adder circuit and said one or more output electrodes to receive said digital added signal and provide said one or more digital output signals including an M-bit digital signal, wherein N>M; a plurality of feedback truncation and saturation protection circuits coupled to said one or more output electrodes to receive said M-bit digital signal and including first and last feedback truncation and saturation protection circuits to provide first and last ones of a plurality of truncated and saturation protected signals, to provide corresponding first and last ones of a plurality of truncation and saturation error feedback signals, and to provide corresponding first and last ones of a plurality of digital feedback signals, having M1 and M2 bits, respectively, wherein a plurality of digital integrator circuits including first and last digital integrator circuits, wherein said first digital integrator circuit is coupled to said first feedback truncation and saturation protection circuit to receive said first one of said plurality of truncation and saturation error feedback signals and provide a first one of said plurality of digital integrated signals, and each remaining one of said plurality of digital integrator circuits is coupled to a respective upstream one of said plurality of feedback truncation and saturation protection circuits to receive a respective upstream one of said plurality of truncation and saturation error feedback signals and provide a respective downstream one of said plurality of digital integrated signals; and a plurality of digital-to-analog converter (DAC) circuits including first and last DAC circuits to receive said plurality of digital feedback signals and provide said plurality of analog feedback signals.