Patent ID: 9130020
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a plurality of interconnects of an nth (n being a positive integer) layer extending in a first direction; a plurality of interconnects of a (n+1)th layer extending in a second direction crossing the first direction above the interconnects of the nth layer; a plurality of stacked films of the nth layer provided respectively at portions where the interconnects of the nth layer and the interconnects of the (n+1)th layer cross between the interconnects of the nth layer and the interconnects of the (n+1)th layer, each of the plurality of stacked films of the nth layer including a memory element; an inter-layer insulating film of the nth layer provided between the plurality of stacked films of the nth layer; a plurality of interconnects of a (n+2)th layer extending in the first direction above the interconnects of the (n+1)th layer; a plurality of stacked films of the (n+1)th layer provided respectively at portions where the interconnects of the (n+1)th layer and the interconnects of the (n+2)th layer cross between the interconnects of the (n+1)th layer and the interconnects of the (n+2)th layer, each of the plurality of stacked films of the (n+1)th layer including a memory element; and an inter-layer insulating film of the (n+1)th layer provided between the plurality of stacked films of the (n+1)th layer and between the plurality of interconnects of the (n+1)th layer, the inter-layer insulating film of the (n+1)th layer being provided also at a side surface of an end portion in the first direction of the interconnects of the nth layer, a lower surface of the inter-layer insulating film of the (n+1)th layer exists at a position lower than a lower surface of the interconnects of the nth layer.