Patent ID: 6268658
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a memory cell of stacked capacitor structure formed above a memory cell-selecting MISFET;a bit line formed of a W-TiN-Ti film formed above said memory cell;a first contact hole for connecting a first semiconductor region of said memory cell-selecting MISFET and said bit line;a polycrystalline silicon plug formed in said first contact hole and having a same conductivity type as said first semiconductor region;a wiring layer electrically connected to a second semiconductor region of a MISFET of a peripheral circuit of said memory cell, said wiring layer being formed of a W-TiN-Ti film in a same layer as said bit line, said second semiconductor region and said wiring layer being connected to each other by a second contact hole formed with said wiring layer therein;a first titanium silicide film having a thickness of 120 nm or less formed between said polycrystalline silicon plug and said bit line in said first contact hole; anda second titanium silicide film having a thickness of 10 nm or more formed between said second semiconductor region and said wiring layer in said second contact hole.