Patent ID: 8938034
Filing Date: 2015-01-20
Classification: G06F,H03M

Abstract:
1. A processor for processing digital data, comprising: at least one butterfly operator for the execution of a fast Fourier transform computation, the butterfly operator including a first stage of complex multiplication and a second stage of complex addition and subtraction that receives output data from the first stage, with each of the two stages containing a plurality of addition/subtraction hardware modules and data transmission links between the modules, wherein the first stage of complex multiplication contains a first level of real addition/subtraction of input data, a second level of real multiplications carried out using data from the first level, and a third level of real addition/subtraction carried out using data from the second level, with at least a part of the addition/subtraction modules of the first level of the first stage of complex multiplication and at least a part of the links going to or leaving from the modules is configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out both a computation of branch metrics values and of path metrics and survivors values of a Viterbi algorithm, such that the processor is capable of operating in both of the first configuration and the second configuration and the processor is configured to switch between operating in the first configuration and the second configuration based on a value assigned to the at least one programmable parameter.