Patent ID: 6608583
Filing Date: 2003-08-19
Classification: H03M,H04N

Abstract:
An analog signal input circuit comprising:a clamping circuit for clamping the amplitude of an input analog signal to a clamp voltage corresponding to a clamping voltage setting signal; a sample-hold circuit for amplifying an output signal issued from said clamping circuit at a sample amplification rate and sample-holding the amplified signal; and an analog/digital converter for generating a digital signal representing the amplitude of the output signal from said sample-hold circuit; wherein said sample-hold circuit includes a switched capacitor amplifier which is provided with a plurality of capacitors, connected with a switch group for which the opening and closing is controlled according to an amplification rate setting command, as input side capacitors or feedback side capacitors, and said sample amplification rate is established according to the capacitance ratio of said input side capacitors and said feedback side capacitors on the basis of said setting command; and wherein said clamping circuit adjusts said clamp voltage in accordance with said setting command so that the central value of the amplitude of the output signal from said sample-hold circuit becomes the central voltage in the conversion range of said analog/digital converter.