Patent ID: 9000491
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A device comprising: a semiconductor device region; a gate region coupled to an upper surface of said semiconductor device region and extending upwardly from the upper surface to define a plurality of gate sidewalls; a source region coupled to the upper surface of said semiconductor device region laterally adjacent said gate region, said source region having a proximal end adjacent said gate region and an enlarged height distal end; a drain region coupled to the upper surface of said semiconductor device region laterally adjacent said gate region, said drain region having a proximal end adjacent said gate region and an enlarged height distal end; a first insulating layer above the semiconductor device region and coupled to the sidewalls of said gate region and an upper surface of the proximal end of said source and drain regions; and a second insulating layer coupled to the distal end of said source and drain regions, an upper surface of said gate region, said first insulating layer, and a lower surface of said semiconductor device region; wherein a portion of the semiconductor device region under said first and second insulating layers is doped.