Patent ID: 7266671
Filing Date: 2007-09-04
Classification: G06F

Abstract:
1. A computer system comprising: a decode unit for decoding instructions supplied to said decode unit from a program memory, wherein at least one instruction has at least one bit sequence defining a register address; a register file having a plurality of registers each having the same predetermined bit capacity and addressable via a plurality of address ports each associated with an execution channel of the computer system; a first register address supply path for supplying said at least one bit sequence in a particular one of said at least one instruction to a first register address port; and one or more additional register address supply paths for supplying said at least one bit sequence in said particular instruction to a corresponding one of a plurality of additional register address ports via a unitary operator which selectively alters a logical value of at least one bit in the register address from said particular instruction dependent on the logical value of each of said at least one bit.