Patent ID: 6205517
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A main memory control apparatus for use in a computer system having main memory, a CPU incorporating a cache memory, and an access enable device capable of making direct memory access to said main memory, said main memory including a first address area allocated as an address area from which data is loaded into said cache memory in said CPU but inhibiting data access from said access enable device to said first address area, and a second address area allocated as an address area to which data is accessed from said access enable device but inhibiting data from being loaded into said cache memory in said CPU from said second address area, said main memory control apparatus controlling data access to said main memory, comprising:a read buffer memory storing data stored in said second address area and, in response to a data access request from said CPU or access enable device, transferring the stored data to the one of said CPU and access enable device issuing a read request;a write buffer memory storing data to be written into said main memory from said CPU or access enable device; anda control portion, when said CPU or access enable device issues a data read request, operating in such a manner that, said control portion retrieves said read buffer memory, if data to be read exists in said read buffer memory, said control portion transfers said data in said read buffer memory to said CPU or access enable device issuing the read request, and, if data to be read does not exist in said read buffer memory, said control portion retrieves said write buffer memory, and if data to be read exists in said write buffer memory, said control portion transfers said data in said write buffer memory to said CPU or access enable device issuing the read request, and if data to be read does not exist in said write buffer memory, said control portion reads from said second address area data at addresses different from the address under the read request from said CPU or access enable device only in lower bits of fixed length, and loads the read data into said read buffer memory while transferring the read data to said CPU or access enable device issuing the read request.