Patent ID: 6243307
Filing Date: 2001-06-05
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array in which a plurality of memory cells are arranged in a matrix for storing data, said memory cell array includinga normal memory cell array including a plurality of normal memory cells, anda spare memory cell array including a plurality of spare memory cells;a memory cell select circuit for selecting said memory cell according to an address signal;a data transmission circuit for transferring data with respect to the selected memory cell; anda test circuit detecting a defective memory cell in said normal memory cell array for determining which said spare memory cell is to be used for replacement, said test circuit includinga signal generation circuit generating said address signal to sequentially select said memory cells, and generating test data to be written into the selected memory cells in a test write operation, and providing expected value data to be read out from said memory cells in a test read out operation,a comparator circuit comparing stored data from said selected memory cell and said expected value data in said test read out operation,an address storage circuit for storing a defective address corresponding to a defective memory cell according to a comparison result of said comparator circuit, anda determination circuit determining which said spare memory cell is to be used for replacement according to said defective address stored in said address storage circuit,said address storage circuit selectively storing a defective address differing from a defective address already stored out of sequentially detected defective addresses.