Patent ID: 6587954
Filing Date: 2003-07-01
Classification: G06F

Abstract:
A clock selection device comprising:a first clock source selection logic adapted to select from a first plurality of input clock signals based on the value of a clock mode signal, producing an output clock line; a clock mode change tracking logic, the clock mode change tracking logic receiving a clock mode signal and a clock invalid signal and generating a clock mode change detect signal upon detection of a change in the clock mode signal, the clock mode change tracking logic deasserting the clock mode change detect signal upon an assertion of a synchronous clock invalid duration elapsed signal and asserting a synchronous clock invalid duration counter reset signal upon an assertion of the synchronous clock invalid duration elapsed signal; a clock mode change detect logic coupled to the clock mode change tracking logic, the clock mode change detect logic receiving the clock mode change detect signal, asserting a clock mode change signal upon detection of a change in the clock mode signal, and asserting a detect clock mode change complete signal upon a deassertion of the clock mode change detect signal; a clock invalid generation logic coupled to the clock mode change detect logic, the clock invalid generation logic receiving the clock mode change signal and the detect clock mode change complete signal, asserting a clock invalid signal to indicate the output clock line is unstable upon an assertion of the clock mode change signal, and deasserting the clock invalid signal to indicate the output clock line is stable upon an assertion of the clock mode change complete signal; and a synchronous clock invalid duration counter coupled to the first clock source selection logic, the synchronous clock invalid duration counter counting clock cycles on the internal clock line, and generating the synchronous clock invalid duration elapsed signal after counting a predetermined number of clock cycles on the output clock line, wherein the clock mode change detect signal enables the synchronous clock invalid duration counter, wherein the synchronous clock invalid duration counter is disabled and reset upon an assertion of the synchronous clock invalid duration counter reset signal, and wherein a synchronous reset signal synchronized with the output clock line resets the synchronous clock invalid duration counter.