Patent ID: 7484062
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A method in a superscalar processor for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction, the method comprising: determining a start of a semi-synchronous memory copy operation associated with a memory, wherein the semi-synchronous memory copy operation operates semi-synchronously with the superscalar processor to provide maximum processor utilization such that the superscalar processor is able to execute at least one additional instruction on the memory during the semi-synchronous memory copy operation, and wherein the semi-synchronous memory copy operation takes virtual addresses as arguments to provide non-pinning of virtual memory pages that tolerate page faults referenced by the virtual addresses; determining a range of addresses where the semi-synchronous memory copy operation is being performed, wherein determining the range of addresses includes analyzing a fourth register associated with the semi-synchronous memory copy operation; identifying a cache injection bit within the fourth register, wherein the cache injection bit is associated with a given value indicating a given number of lines of destination data corresponding to the number of byes in the third register that are two be transferred to a given number of cache levels; copying, based on the cache injection bit, a first predefined number of lines of destination data into a first level of cache memory, a second predefined number of lines of destination data that is subsequent and sequential to the first predefined number of lines of destination data to a second level of cache memory, and at least a third predefined number of lines of destination data that is subsequent and sequential to the second predefined number of lines of destination data to at least a third level of cache memory; copying a remainder of destination data that has not been transferred to a level of cache memory from the source memory location to the target memory location within the memory; moving at least one line of destination data from the at least third level of cache memory to the second level of cache memory and at least one line of destination data from the second level of cache memory to the first level of cache memory in response to a least one of the first predefined number of lines of destination data being accessed in the first level of cache memory, wherein the at least one line of destination data being moved from the third level of cache memory to the second level of cache memory and the at least one line of destination data being moved from the second level of cache memory to the first level of cache memory are moved in a sequential manner; executing at least one subsequent instruction on the memory during the copying of the predefined number of lines of destination data into the at least one level of cache memory and the copying of the remainder of destination data to the target location within the memory; preventing write operations by the superscalar processor to the source address range and the target address range where the semi-synchronous memory copy operation is being performed; allowing a read operation by the superscalar processor from the source address range where the semi-synchronous memory copy operation is being performed; and preventing a read operation by the superscalar processor from the target address range where the semi-synchronous memory copy operation is being performed.