Patent ID: 7500123
Filing Date: 2009-03-03
Classification: G06F,Y02D

Abstract:
1. An apparatus for reducing power consumption in a graphics processing device, the apparatus comprising: a memory module monitoring device operative to receive a memory module status signal from at least one of a plurality of memory modules, wherein the memory module monitoring device generates a clock control signal in response to the memory module status signal; a clock cycle reduction circuit operatively coupled to the memory module monitoring device and operative to receive the clock control signal such that the clock cycle reduction circuit generates a reduced clock cycle signal in response to the clock control signal such that the reduced clock cycle signal reduces power consumption in the graphics processing device; a phase locked loop operatively coupled to the clock cycle reduction circuit such that the phase locked loop generates an original clock signal and the clock cycle reduction circuit reduces clock cycles of the original clock signal to generate the reduced clock cycle signal; wherein the memory module monitoring device reads the memory module status signal for a first predetermined number of intervals prior to generating a clock control signal; and wherein the clock cycle reduction circuit generates the reduced clock cycle signal for a second predetermined number of clock cycles prior to reading a second clock control signal from the memory module monitoring device.