Patent ID: 6606736
Filing Date: 2003-08-12
Classification: G06F

Abstract:
A computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said method comprising:preparing a timing error information including the types of timing errors and timing error paths, a delay information relating to signal propagation delay, and a logic information including function and driving capability of each cell in said combinational circuits; when said timing error information in which sequential circuit is a set-up error path, then selecting a cell which is estimated with referring to said delay information to be the greatest cause for the set-up error arising; searching a cell whose function is the same as the selected cell and driving capability is larger than said selected cell; and replacing said selected cell with the searched cell.