Patent ID: 9223924
Filing Date: 2015-12-29
Classification: G03F,G06F,Y02P

Abstract:
1. A method for layout decomposition, comprising: providing a portion of a layout of a single layer of an integrated circuit to be multi-patterned, the portion of the layout having a plurality of patterns representing circuit elements; determining spacings between adjacent pairs of patterns within the plurality of patterns; generating a conflict graph representing the layout, the conflict graph having a plurality of sub-graphs, each respective sub-graph having a respective vertex corresponding to each respective sub-graph; dividing the patterns within each respective sub-graph into at least a first group and a second group, each of at least the first and second groups to be assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask; determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.