Patent ID: 6466898
Filing Date: 2002-10-15
Classification: G06F

Abstract:
A method of performing a multithreaded event-driven logic simulation of an integrated circuit design, coded in one or a plurality of Hardware Description Language (â€œHDLâ€ ) languages including VHDL, Verilog languages and a mixed thereof on a multiprocessor platform, comprising the steps of:(a) pre-examining each user-specified HDL source file and automatically invoking an appropriate HDL compiler to compile a design source file into a common design database; (b) resolving any conflict in the design source file due to use of the plurality of HDL languages to ensure correct modeling and simulation of the design source file; and (c) automatically detecting the number of microprocessors (CPUs) available on the multiprocessor platform to create a master thread and a plurality of slave threads for concurrent execution of the multithreaded event-driven simulation of the design to achieve linear to super-linear scalable performance speedup as according to the number of CPUs on the multiprocessor platform.