Patent ID: 7919997
Filing Date: 2011-04-05
Classification: H03K,H03L

Abstract:
1. A frequency multiplier circuit, comprising: a plurality of serially connected delay elements configured to generate a plurality of delay tap signals from an input signal; a phase detector configured to receive a first selected delay tap signal and the input signal, to detect a phase shift between the first selected delay tap signal and the input signal, and to generate a phase detection signal indicative of a value of the phase shift; a digital logic gate configured to receive the input signal, the input signal bypassing the plurality of delay elements, and to receive a second selected delay tap signal, the digital logic gate further configured to generate an output signal responsive to the second selected delay tap signal and the input signal; a controller coupled to the phase detector and an output gate, the controller configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value; and a counter configured to generate a first counter signal indicative of a first number of delay elements that produce the first selected delay tap signal and a second counter signal indicative of a second number of delay elements that produce the second selected delay tap signal; and wherein, when enabled, the output gate provides the output signal.