Patent ID: 6072351
Filing Date: 2000-06-06
Classification: H03K

Abstract:
An output buffer comprising:a first plurality of transistors having source to drain paths connected in series to couple V.sub.SS to an output node, each of the first plurality of transistors having a maximum tolerable drain to gate voltage and a maximum tolerable gate to source voltage, wherein the first plurality of transistors comprise:a first transistor (101) having a source to drain path coupled on a first end to V.sub.SS, and having a gate coupled to receive a buffer input signal Q; anda second transistor (102) having a source to drain path coupling a second end of the first transistor at a node n2 to the output node, and having a gate;a second plurality of transistors having source to drain paths connected in series to couple a first voltage potential to the output node, each of the first plurality of transistors having the maximum tolerable gate to source voltage which is less than the first voltage potential and the maximum tolerable drain to gate voltage which is less than the first voltage potential, wherein the second plurality of transistors comprise:a third transistor (103) having a source to drain path coupled on a first end to the output node, and having a gate; anda fourth transistor (104) having a source to drain path coupling a second end of the third transistor at a node n1 to the first voltage supply, and having a gate;a power supply (108) controlled to apply voltages to the gates of the first and second plurality of transistors to maintain a drain to gate voltage for each of the first and second plurality of transistors less than the maximum tolerable drain to gate voltage, and to maintain a gate to source voltage for each of the first and second plurality of transistors below the maximum tolerable gate to source voltage, the power supply receiving the buffer input signal Q and applying voltages to the gate of the third transistor (103) to turn the third transistor (103) on and off in correspondence with a state of the signal Q, the power supply (108) further:applying a second voltage potential to the gate of the fourth transistor (104) when the third transistor (103) is turned off so that the drain to gate voltage for the second plurality of transistors will be less than the maximum drain to gate voltage,applying a third voltage potential to the gate of the fourth transistor (104) when the third transistor (103) is turned on to enable the first voltage potential to be substantially provided to the output node, andapplying a voltage potential to the gate of the second transistor (102) to turn it on so that with a voltage on the output node greater than the maximum drain to gate voltage and the first transistor (101) turned off, a voltage from the drain to gate of the second transistor (102) will be less than the maximum gate to drain voltage; anda first voltage switch (110) coupling the power supply (108) to the gate of the second transistor (102), the first voltage switch (110) further having an input coupled to node n2, the first voltage switch (110) being controlled to apply a first voltage from the power supply (108) to the gate of the second transistor (102) when the first transistor (101) is turned off and the output node voltage pulls node n2 above a predetermined value, and the first voltage switch (110) further applying a second voltage (V.sub.CC) from the power supply (108) to the gate of the second transistor (102) to turn it on when node n2 is pulled below the predetermined level.