Patent ID: 6104212
Filing Date: 2000-08-15
Classification: H03K

Abstract:
A CMOS circuit comprising:a plurality of more than two domino gates, a common virtual ground node and characterized by a common evaluation NFET device, and further characterized in that each said domino gate of said plurality of more than two domino gates respectively comprises a PFET precharge device, and an NFET device tree, and an output inverter stage, and a dynamic node, and a plurality of input nodes, and a clock input node and an output node; and whereineach domino gate receives unique inputs and an output node of a first domino gate of one of said plurality of domino gates is coupled to an input node of a next respective domino gate of said plurality of more than two domino gates to establish a sequential domino gate connection among said plurality of more than two domino gates with a first dynamic node in the first domino gate of said one of said plurality of domino rates discharging before the discharge of the dynamic node of the next domino gate; andsaid PFET precharge device of each said domino gate is coupled to a high voltage supply rail, and to said clock input node and said dynamic node of each said domino gate;said NFET device tree of each said domino gate being coupled to said common virtual ground node for said plurality of domino gates, and to said plurality of inputs and to said dynamic node;said output inverter stage coupled to said high voltage supply rail, to said dynamic node, to a low voltage supply rail and to said output node;said common evaluation NFET device coupled to said clock input node, to said low voltage supply rail and to said common virtual ground node whereby said common evaluation NFET device for all of said plurality of more than two domino gates is shared by all domino gates within the circuit.