Patent ID: 6397239
Filing Date: 2002-05-28
Classification: G06F,H03M

Abstract:
A microprocessor, comprising:an execution unit coupled to receive a first set of input data values, a second set of input data values, and an instruction indication specifying an operation to be performed by said execution unit, wherein said execution unit includes: a first add/subtract pipeline coupled to receive a first set of operands and said instruction indication, wherein said first set of operands are selected from said first set of input data values and said second set of input data values, and wherein said first add/subtract pipeline is configured to generate a first result value from said first set of operands according to said instruction indication; a second add/subtract pipeline coupled to receive a second set of operands and said instruction indication, wherein said second set of operands are selected from said first set of input data values and said second set of input data values, and wherein said second add/subtract pipeline is configured to generate a second result value from said second set of operands according to said instruction indication; an output multiplexer unit coupled to receive said first result value, said second result value, said instruction indication, and one or more additional input values, wherein said output multiplexer unit is configured to select a first output value and a second output value from said first result value, said second result value, and said one or more additional input values according to said instruction indication; wherein said first result value and said second result value are generated concurrently.