Patent ID: 6209067
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A computer system, comprising:a processor bus;a processor coupled to said processor bus;a memory;a local bus;a bus mastering device coupled to said local bus;a controller coupled to said memory and between said local bus and said processor bus, said controller comprising:a processor interface operable to interface said processor to said memory and said local bus, said processor interface having a write posting queue for receiving write cycles from said processor as long as a posting disable request is not received, said write cycles being destined for said local bus;a local bus interface operable to interface said local bus to said memory and said processor, said local bus interface receiving memory access requests from said bus mastering device and providing access to said memory if said write posting queue is empty, said local bus interface providing a posting disable request to said processor interface when posting is not desired; anda memory interface operable to interface said memory to said processor and said local bus;wherein if a memory access request is received from said bus mastering device and said write posting queue is not empty, said posting disable request is provided to allow said write posting queue to empty, and wherein if a memory access request is received from said bus mastering device and said write posting queue is empty, said memory access request is completed.