Patent ID: 6598192
Filing Date: 2003-07-22
Classification: G01R

Abstract:
An integrated circuit having a test mode, comprising:a programmable clock generator having an input for receiving a test clock input generated external from the integrated circuit, a first output, and a second output; a core for performing data processing which has an input coupled to the first output of the integrated circuit and comprises a first plurality of registers that are usable as data processing registers and scan registers; a peripheral logic circuit having a second plurality of registers which are usable as logic registers and scan registers; and a test controller, coupled to the core and the peripheral logic circuit, having an input for receiving at least a control signal generated external to the integrated circuit, wherein during the test mode the programmable clock generator is further characterized as generating a base clock having a base period and a chopped clock at the fist output comprising a series of pulses of a firs t pulse width, wherein the first pulse width is less than or equal to approximately one half of the base period and wherein the pulses occur no more than once per base period; and wherein the programmable clock generator is further characterized as providing a pulse of the series of pulses selectable at any location within the base period, said location selected by a chop control signal provided external from the integrated circuit, wherein said provided pulse is provided before any other pulse that is within the base period is provided by the programmable clock generator.