Patent ID: 9069926
Filing Date: 2015-06-30
Classification: G06F

Abstract:
1. A standard cell library used to design a layout, wherein a processor is used to produce a biased layout from the layout for fabricating a semiconductor device on a wafer, the layout stored on a non-transitory computer readable storage, comprising: the layout includes cell layouts from the standard cell library, the cell layouts include a plurality of layers, wherein at least one transistor in at least one cell layout is identified by an annotation layer, and the annotation layer itself identifies gate-length biasing to be applied to the at least one transistor of the at least one cell layout when the processor produces the biased layout, using the annotation layer, after the layout has been designed, wherein the gate-length biasing defines an amount of change to a gate length that is not width-sizing of a gate width of the at least one transistor; wherein the amount of change is a positive or a negative amount of change for the gate length, and the amount of change is represented as nanometer values from about 1 nanometer to about 10 nanometers, the gate-length biasing identified by the annotation layer represents design-specific directives that require implementation, and wherein fabricating the semiconductor device includes making one or more masks from the biased layout, the fabricating resulting in at least one fabricated feature on the wafer.