Patent ID: 6157203
Filing Date: 2000-12-05
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:an input circuit which includes a first MOSFET of a first conductivity type having a gate to which a reception signal with a small amplitude with respect to a power supply voltage is supplied through an external terminal, a second MOSFET of the first conductivity type having a gate to which a reference voltage corresponding to a value which judges logic levels of said reception signal is applied, and third and fourth MOSFETs of a second conductivity type provided to drains of said first and said second MOSFETs, respectively, and formed into current mirror forms, to generate an output signal corresponding to a difference current between drain currents of said first and said second MOSFETs;an electrostatic protection circuit provided to the external terminal which receives said reception signal; anda first circuit provided to the gate of said second MOSFET, and adapted to transmit the same noise as a noise on a power supply transmitted to the gate of said first MOSFET through said electrostatic protection circuit, to the gate of said second MOSFET;wherein sources of said first and said second MOSFETs are connected in common so as to be in a differential form and said common source is provided with a fifth MOSFET of a first conductivity type for supplying an operating current; andwherein said electrostatic protection circuit includes a first diode provided between a power supply voltage terminal and said external terminal in a reversely biased state and a second diode provided between said external terminal and an earth potential of the semiconductor integrated circuit in a reversely biased state and said first circuit includes third and fourth diodes being of sizes smaller than sizes of said first and said second diodes.