Patent ID: 6815777
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A semiconductor device comprising:a first conduction type well region; a second conduction type well region; a first gate-gate electrode layer including a gate electrode of a first load transistor and a gate electrode of a first driver transistor; a second gate-gate electrode layer including a gate electrode of a second load transistor and a gate electrode of a second driver transistor; a first drain-drain wiring layer that forms a part of a connection layer that electrically connects a drain region of the first load transistor and a drain region of the first driver transistor; a second drain-drain wiring layer that forms a part of a connection layer that electrically connects a drain region of the second load transistor and a drain region of the second driver transistor; a first drain-gate wiring layer that forms a part of a connection layer that electrically connects the first gate-gate electrode layer and the second drain-drain wiring layer; and a second drain-gate wiring layer that forms a part of a connection layer that electrically connects the second gate-gate electrode layer and the first drain-drain wiring layer, wherein the first load transistor and the second load transistor are provided in the first conduction type well region, wherein the first driver transistor and the second driver transistor are provided in the second conduction type well region, wherein the second drain-gate wiring layer is located in a layer over the first drain-gate wiring layer, and has an upper layer of the second drain-gate wiring layer and a lower layer of the second drain-gate wiring layer, wherein the upper layer is located in a layer over the lower layer, and wherein the upper layer is provided above one of the first conduction type well region and the second conduction type well region.