Patent ID: 8090930
Filing Date: 2012-01-03
Classification: G06F

Abstract:
1. In a pipelined computer architecture, a method for detecting instruction queue status at a cycle K, instructions capable of being removed from the queue out of sequence, the method comprising: determining a number of invalid instructions in the queue during cycle K−2; determining a number of instructions issued from the queue during cycle K−1; determining a number of instructions enqueued in the queue during cycle K−1; and determining a value indicative of a number of free rows in the queue at cycle K as the sum of the number of invalid instructions and the number of issued instructions, less the number of enqueued instructions, wherein the number of invalid instructions, the number of issued instructions, and the number of enqueued instructions are each represented as a flat vector, and wherein adding comprises shifting in one direction, and subtracting comprises shifting in an opposite direction.