Patent ID: 7467251
Filing Date: 2008-12-16
Classification: G06F

Abstract:
1. A flash memory data storage apparatus that transceives data with an external system through a host bus group in parallel, comprising: a flash memory that transceives data through a flash bus group, a bus width (FW) of the flash bus group being greater than a bus width (HW) of the host bus group, where the bus width (FW) of the flash bus group and the bus width (HW) of the host bus group each represents a number of bus lines that transceive data in parallel in response to a same clock signal; and a flash interface that controls a data transmission operation between the flash bus group and the host bus group, wherein the flash interface includes first through n'th flash input buffers that transfer data to the flash memory in stages in response to first through n'th transfer control clock signals, where n≧2, wherein, in a stage of the stages, an i'th flash input buffer of the first through n'th flash input buffers, where 2≦i≦n, receives data from an (i−1)'th flash input buffer, and provides data through i'th input-buffer bus groups to the flash memory in number of at least Ni, wherein a bus width (IBWi) of each of the i'th input-buffer bus groups is wider than a bus width (IBWi−1) of each of (i−1)'th input-buffer bus groups, wherein the first through n'th transfer control clock signals comprise an (i−1)'th transfer control clock signal and an i'th transfer control clock signal that is the (i-l)'th transfer control clock signal having a lengthened period, wherein a period (Ti) of the i'th transfer control clock signal applied to the i'th flash input buffer is longer than a period (Ti−1) of the (i−1)'th transfer control clock signal applied to the (i−1)'th flash input buffer, and wherein the Ni is obtained by dividing the bus width (FW) of the flash bus group by the bus width (IBWi) of the each of the i'th input-buffer bus groups.