Patent ID: 8120939
Filing Date: 2012-02-21
Classification: G11C,H01L

Abstract:
1. A semiconductor memory cell array comprising: an elongated continuous active region; first and second pass transistors formed in the elongated continuous active region and being part of first and second memory cells, respectively, the memory cells being adjacent cells in a column of memory cells in the semiconductor memory cell array; an isolation transistor formed in the elongated continuous active region between the first and second pass transistors and biased in an off state; first and second word lines coupled to gates of the first and second pass transistors, respectively, for applying a reading voltage; and a differential bit line pair including first and second bit lines, a first logic value being encoded into the memory cells by connecting the pass transistors to the first bit line and a second logic value being encoded into the memory cells by connecting the pass transistors to the second bit line.