Patent ID: 6621745
Filing Date: 2003-09-16
Classification: G11C

Abstract:
In a memory array having a plurality of memory cells, each of said memory cells having a plurality of memory states and being programmed to one of said memory states by at least one program pulse being applied to a wordline that is electrically coupled to a gate of a selected memory cell, and the memory state of the memory cell being verified by at least one read/verify pulse being applied to the wordline, a row decoder circuit comprising:means for selecting the wordline that is electrically coupled to the selected memory cell; and a wordline driver circuit receiving a programming voltage from a first power supply line and a read/verify voltage from a second power supply line, said wordline driver circuit further including means for switching between the programming voltage and the read/verify voltage to supply the at least one program and the at least one read/verify pulse to the wordline, whereby the selected memory cell is programmed.