Patent ID: 7242608
Filing Date: 2007-07-10
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: an SOI substrate in which a silicon layer is formed on an insulating film formed on a silicon substrate; a plurality of transistors formed on the silicon layer and arranged in a matrix form, each of the transistors having a gate electrode and source/drain diffusion regions, the upper face and both side faces of the gate electrode being covered with a first protection film, and the electrodes in one direction constituting word lines; a first interlayer dielectric film which covers the plurality of transistors; source contact plugs embedded in source contact holes which are formed in the first interlayer dielectric film and on the source diffusion regions of the transistors; drain contact plugs embedded in drain contact holes which are formed in the first interlayer dielectric film and on the drain diffusion regions of the transistors; source wiring portions each of which commonly connects the source contact plugs in a direction of the word line and the upper face and both side faces of which are covered with a second protection film; a second interlayer dielectric film which covers the source wiring portions; and bit lines which are formed on the second interlayer dielectric film so as to cross the word lines and which are connected to the drain diffusion regions of the transistors via the drain contact plugs; wherein each of the transistors has a first data state having a first threshold voltage in which excessive majority carriers are held in the silicon layer and a second data state having a second threshold voltage in which the excessive majority carriers in the silicon layer are emitted.