Patent ID: 6381723
Filing Date: 2002-04-30
Classification: H03M,H04L

Abstract:
An error correction device which corrects an error in a symbol string supplied via a data transmission line, comprising:a first delay circuit delaying said supplied symbol string by a first time; an error correction circuit performing a predetermined arithmetic operation on said supplied symbol string to correct an error in an output symbol string of said first delay circuit based on result of the arithmetic operation; a determination circuit determining whether or not error correction performed by said error correction circuit is normal, outputting a first signal if the correction is normal and outputting a second signal if the correction is abnormal; a second delay circuit delaying the output symbol string of said first delay circuit directly by a second time; a third delay circuit delaying by a third time the symbol string output from said first delay circuit and subjected to error correction by said error correction circuit; and a switching circuit receiving output symbol strings of said second and third delay circuits, supplying the output symbol string of said third delay circuit to a circuit in a following stage in response to output of the first signal from said determination circuit, and supplying the output symbol string of said second delay circuit to the circuit in the following stage in response to output of the second signal from said determination circuit.