Patent ID: 6801256
Filing Date: 2004-10-05
Classification: H04N

Abstract:
A solid-state imaging device comprising:an imaging area including units cells arranged in a two-dimensional matrix on a semiconductor substrate and vertical signal lines each connected n common to the unit cells in the same column, said unit cells each comprising: a photoelectric conversion element configured to generate charges in proportion to incident light; a read circuit configured to read a voltage corresponding to said generated charges; an amplifier circuit configured to amplify said read-out voltage; a reset circuit configured to reset the generated charges; and a row select circuit configured to allow the output signal of said amplifier circuit to be output onto said vertical signal line; load transistors each being connected to corresponding one of said vertical signal lines at one end; a load transistor on/off control circuit configured to control said load transistors in a manner such that said load transistors are turned off when said row select circuit is in off state; and signal storage circuits each being connected to corresponding one of said vertical signal lines at the other end, configured to store a signal output onto said corresponding one of said vertical signal lines, wherein: a bias voltage is applied to said vertical signal lines after said load transistor on/off control circuit has turned off said load transistors.