Patent ID: 7923299
Filing Date: 2011-04-12
Classification: H01L,H05K

Abstract:
1. A manufacturing process for an embedded semiconductor device, comprising: providing a substrate having a base, a first metal layer, a second metal layer, and at least a first conductive structure passing through the base and electrically connected to the first metal layer and the second metal layer, the first metal layer being disposed on a first surface of the base, the second metal layer being disposed on a second surface of the base; patterning the first metal layer to form a first circuit layer having a plurality of first pads; performing a roughening process on the first circuit layer, the second metal layer and the first conductive structure to form a roughened layer; disposing a semiconductor device on the first circuit layer, the semiconductor device being electrically connected to the first pads; forming at least an insulation layer to cover the first surface of the base and laminating a third metal layer on the insulation layer, whereby embed the semiconductor device in the insulation layer; forming at least a second conductive structure passing through the insulation layer and the first circuit layer and electrically connected to the second metal layer and the third metal layer; patterning the second metal layer to form a second circuit layer having a plurality of second pads; and patterning the third metal layer to form a third circuit layer having a plurality of third pads.