Patent ID: 8816490
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. An integrated circuit die stack comprising: a first integrated circuit die mounted upon a substrate, the first die comprising pass-through vias (‘PTVs’), each PTV comprising a conductive pathway through the first die with no connection to any circuitry on the first die; a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die, each TSV on the second die comprising a conductive pathway through the second die that is also connected to electronic circuitry on the second die; a first substack mounted upon the substrate, the first substack comprising two or more identical dies, each of the dies in the first substack stacked upon one another without rotation with respect to one another; and a second substack comprising two or more dies identical to the dies in the first substack, each of the dies in the second substack stacked upon one another without rotation with respect to one another, the entire second substack rotated with respect to the first substack and mounted upon the first substack so that PTVs in the first substack connect the signal lines from the substrate through the first substack to TSVs in the second substack, the TSVs in the second substack driving active circuitry in the dies of the second substack; the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.