Patent ID: 6667508
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A structure of nonvolatile memory, comprising:a p type silicon substrate; a split gate comprising a tunneling dielectric layer, a floating gate, a dielectric layer and a control gate formed on the p type silicon substrate; a source region located at a first side of the split gate adjacent to the floating gate in the p type silicon substrate; a drain region located at a second side of the split gate in the p type silicon substrate; and a channel region located between the source region and the drain region; wherein: the floating gate is located at a first side under the control gate and isolated with the control gate via the dielectric layer, a second side of the control gate extending on the p type silicon substrate and isolated with the p type silicon substrate via the dielectric layer and the tunneling dielectric layer; the drain region is a highly n doped region and diffuses beneath the split gate; the source region comprises a surface metal portion and a highly n doped region, wherein the surface metal portion and the channel region forming a Schottky barrier, the highly n doped region locates under the surface metal portion, contacts with the p type silicon substrate and has an offset with the channel region.