Patent ID: 6047247
Filing Date: 2000-04-04
Classification: G06F

Abstract:
A hot-carrier-delay-degradation estimation method of estimating, in timing verification of an LSI designed on a cell level, deterioration in reliability of the LSI due to the influence of hot carriers, comprising the steps of:a delay calculation step of calculating, for cells forming an LSI serving as an object of timing verification, delays, signal slew at input terminals of said cells, and load capacitances connected to output terminals of said cells, the calculations being based on (i) circuit information comprising characteristic information of said cells, information of connection between said cells and cell-to-cell wirings, and characteristic information of said cell-to-cell wirings, and (ii) a delay library containing delay parameters to be used for calculating said delays; anda delay degradation library generation step of generating a delay degradation library by obtaining delay parameters of said cells at the time when said LSI has operated for a predetermined period of time, and then generating said delay degradation library containing said delay parameters thus obtained, said delay parameters being obtained (i) based on said delay library and on delay degradation parameters, in which changes in delay of each of said cells due to the influence of hot carriers are expressed in terms of changes in delay parameters accompanied by a number of operation times of each of said cells, and (ii) with the use of an estimated number of operation times of each of said cells at the time when said LSI has operated for said predetermined period of time, and of said input signal slew and output load capacitances of said cells calculated in said delay calculation step,said delay calculation step and said delay degradation library generation step being repeated a predetermined number of repetition times,wherein on and after the second repetition time, said delay calculation step and said delay degradation library generation step being executed using, instead of said delay library, the delay degradation library generated at the delay degradation library generation step which has been just previously executed prior to a current repetition time,whereby deterioration in reliability of said LSI due to the influence of hot carriers is estimated based on the delays of said cells calculated at the delay calculation step which has been lastly executed.