Patent ID: 8729547
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: an oxide semiconductor layer comprising indium, zinc, gallium and oxygen, the oxide semiconductor layer including a channel formation region; a gate electrode adjacent to the channel formation region with a gate insulating layer therebetween; a first n-type conductivity region comprising indium, zinc, gallium and oxygen; a second n-type conductivity region comprising indium, zinc, gallium and oxygen; a source electrode comprising a first metal layer over the first n-type conductivity region, wherein the source electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the first n-type conductivity region; a drain electrode comprising a second metal layer over the second n-type conductivity region, wherein the drain electrode is in electrical contact with the channel formation region of the oxide semiconductor layer through the second n-type conductivity region, wherein an inner side edge of the first metal layer is substantially aligned with an inner side edge of the first n-type conductivity region, wherein an inner side edge of the second metal layer is substantially aligned with an inner side edge of the second n-type conductivity region, and wherein the oxide semiconductor layer comprises excessive oxygen.