Patent ID: 6946392
Filing Date: 2005-09-20
Classification: H01L,H05K,Y10T

Abstract:
1. A method of forming interconnects in a semiconductor device by filling openings extending through a dielectric layer to an underlying conductive layer supported by a substrate, said method comprising the acts of: forming a first dielectric layer over a base layer of a semiconductor device; forming openings in said first dielectric layer so as to expose contact regions within said base layer; positioning a conductive material in said openings formed in said first dielectric layer such that said conductive material is in electrical contact with said exposed contact regions; forming a second dielectric layer over said first dielectric layer and said conductive material; forming openings extending through said second dielectric layer such that said openings extend from an upper surface of said dielectric layer to said underlying conductive material in said openings formed in said first dielectric layer; forming a malleable conductive layer over said upper surface of said dielectric layer and within said openings extending through said second dielectric layer, wherein a thickness of said malleable conductive layer is substantially less than a thickness of said dielectric layer such that said malleable conductive layer lines said opening and an uppermost surface of said malleable conductive layer defines an unfilled void extending upwardly from said uppermost surface of said malleable conductive layer within said opening; and moving a portion of said malleable conductive layer formed over said upper surface of said dielectric layer into said unfilled void by polishing said malleable conductive layer so as to plug said opening.