Patent ID: 6479327
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising the steps of:(a) providing a plurality of semiconductor chips each having a first surface and a second surface opposite to said first surface, a gate electrode and a source electrode formed on said first surface, respectively and a drain electrode formed on said second surface; (b) providing a lead frame having a plurality of units arranged in a line, each of said plurality of units having a gate lead, a source lead and a chip support substrate as a drain lead, each of said gate and source leads extending in a direction substantially perpendicular to a direction of said line and having an inner lead portion and an outer lead portion which is continuously formed with said inner lead portion, ends of said inner lead portions of said gate and source leads being spaced from said chip support substrate in said perpendicular direction, said gate and source leads of each of said plurality of units being coupled with one another by a tie bar portion of said lead frame, said tie bar portion extending in the direction of said line at a boundary of said inner and outer lead portions, each of said chip support substrates of said plurality of units being coupled with said tie bar portion by one of a plurality of support leads of said lead frame, each said support lead being disposed between adjacent ones of said plurality of units in the direction of said line; (c) mounting said plurality of semiconductor chips on said chip support substrates of said plurality of units respectively such that said second surface of said semiconductor chip is adhered to an upper surface of the corresponding chip support substrate; (d) electrically connecting said gate electrode with said inner lead portion of said gate lead by a first wire in each of said plurality of units; (e) electrically connecting said source electrode with said inner lead portion of said source lead by second wires in each of said plurality of units; (f) sealing said semiconductor chip, said inner lead portion and said first and second wires by a resin member in each of said plurality of units, said outer lead portion, said tie bar portion and each said support lead protruding outwardly from said resin member respectively, (g) after step (f), cutting each said support lead and said tie bar portion of said lead frame, thereby providing a plurality of semiconductor packages each having said semiconductor chip, said gate, source and drain leads, and said first and second wires.