Patent ID: 7538000
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A method of making double gate transistors on an integrated circuit having a plurality of circuit areas of predetermined gate dielectric effective thicknesses, comprising: providing a first wafer, said first wafer having a first side and a second side, said first wafer comprising a first semiconductor substrate structure at the first side; forming a first dielectric layer over first, second and third circuit areas on the first side; removing the first dielectric layer from the first circuit area; forming a second dielectric layer over the first, second and third circuit areas; removing the second dielectric layer from the first circuit area; forming a final dielectric layer of a substantially uniform thickness over the first and second circuit areas on the first side, thereby forming a plurality of bottom gate dielectric layers, comprising: forming a substantially planar layer of bottom gate conductor material on the first side; bonding the first side of the first wafer to a second wafer; forming a top gate layer over and insulated from the first semiconductor substrate structure; and forming a plurality of self-aligned top gate structures, channel regions, and bottom gate structures by using an active area mask to selectively etch the top gate layer to form the plurality of top gate structures which are used as a mask to selectively etch the first semiconductor substrate structure and the plurality of bottom gate dielectric layers and the layer of bottom gate conductor material; whereby each of the bottom gate dielectric layers has predetermined effective thicknesses.