Patent ID: 6345336
Filing Date: 2002-02-05
Classification: G06F,Y02D

Abstract:
An instruction cache memory comprising:data RAM including a plurality of cache lines for storing a plurality of words which have consecutive memory addresses to output read-out data in response to an access address inputted from a processor; tag RAM for storing data necessary for specifying said memory addresses of the words stored in said cache lines as tag addresses for each cache line of said data RAM, and outputting one of said tag addresses of corresponding one of said cache lines as a tag signal in response to said access address inputted from said processor; a hit/miss judging circuit for comparing said tag signal outputted from said tag RAM with said access address from said processor to judge whether a word having said memory address corresponding to said access address is stored in said data RAM or not and output a result of the judgement as a hit/miss judging signal; and a clock gate circuit for selectively supplying a clock signal to said tag RAM when the cache line for storing the word to be read out changes from one to another, or, a branch instruction is detected in said processor, and otherwise stop the supply of the clock signal to said tag RAM.