Patent ID: 6628161
Filing Date: 2003-09-30
Classification: G05F

Abstract:
A reference voltage circuit comprising:a depletion type first PMOS transistor and an enhancement type second PMOS transistor serially connected to each other; wherein a gate electrode of the first PMOS transistor is formed from polysilicon including a P-type impurity and connected to a source electrode thereof; a gate electrode of the second PMOS transistor is formed from polysilicon including an N-type impurity and connected to a drain electrode thereof; a first power supply line is connected to the gate electrode and a source electrode of the first PMOS transistor; a second power supply line is connected to the gate electrode and a drain electrode of the second PMOS transistor; and a voltage corresponding to a difference between a threshold voltage of the second PMOS transistor and a threshold voltage of the first PMOS transistor is generated at a common connection section of both PMOS transistors as a reference voltage.