Patent ID: 9031179
Filing Date: 2015-05-12
Classification: H04B,H04L

Abstract:
1. A system for determining a bit sequence from an input signal, the system comprising: a data slicing subsystem that operates to generate data sampler decisions by sampling the input signal according to a clocking signal with respect to a reference level; an error slicing subsystem that operates to generate error slicer samples by sampling the input signal according to the clocking signal with respect to an estimated signal value; and a calibration subsystem, in communication with the data slicing subsystem and the error slicing subsystem, that operates to: compare the data sampler decisions with the error slicer samples to determine an effective clock mismatch window between the data slicing subsystem and the error slicing subsystem by: apply a clocking offset to at least one of the data slicing subsystem or the error slicing subsystem as a function of the determined effective clock mismatch window.