Patent ID: 6717236
Filing Date: 2004-04-06
Classification: C25D,H01L

Abstract:
A method of fabricating a semiconductor device, having a reduced-oxygen copper-zinc (Cuâ€”Zn) alloy filled dual-inlaid interconnect structure formed on a copper (Cu) surface formed by electroplating the Cu surface in a chemical solution, comprising the steps of:providing a semiconductor substrate having a Cu surface formed in a via; providing a chemical solution; electroplating the Cu surface in the chemical solution thereby forming said a Cuâ€”Zn alloy fill in the via and on the Cu surface, wherein said electroplating comprises using an electroplating apparatus, wherein said electroplating apparatus comprises: (a) a cathode-wafer, (b) an anode, (c) electroplating vessel; and (d) a voltage source, and wherein the cathode-wafer comprises the Cu surface, rinsing the Cuâ€”Zn alloy fill in a solvent; drying the Cuâ€”Zn alloy fill under a gaseous flow; annoling the Cuâ€”Zn alloy fill formed in the via and directly deposited on the Cu surface, thereby forming a reduced-oxygen Cuâ€”Zn alloy fill having an alloy surface and an alloy thickness and having a uniform zinc distribution across said alloy surface and said alloy thickness; planarizing the reduced-oxygen Cuâ€”Zn alloy fill and the Cu surface, thereby completing formation of a reduced-oxygen Cuâ€”Zn alloy filled dual-inlaid interconnect structure; and completing formation of the semiconductor device.