Patent ID: 8054705
Filing Date: 2011-11-08
Classification: G06F,G11C

Abstract:
1. A semiconductor integrated circuit comprising: K number of memory cells coupled to a same word line; a plurality of sense amplifier circuits coupled to the memory cells, wherein the plurality of sense amplifier circuits are divided into N number of groups, K and N are natural numbers of 2 or more, among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation; an ECC circuit that inputs data read out from the N number of groups to carry out an ECC process; and a parity bit cell for the ECC process, the parity bit cell being connected to the word line, wherein if K/N<2 if 2 x is a positive integer.