Patent ID: 7518881
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A computer system including a mechanism for reducing voltage noise for a processor chip, comprising: one or more processors located on the processor chip; a memory that stores instructions and data for the one or more processors; an interposer sandwiched between the processor chip and a circuit board; wherein the interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the processor chip; and a plurality of bypass capacitors, each including a set of internal planes, integrated into the interposer and coupled between the power and ground connections for the processor chip, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the processor chip, wherein the internal planes of the bypass capacitors extend downward from the top surface of the interposer in a direction that is normal to the top surface of the interposer; wherein the plurality of bypass capacitors are electrically connected to power and ground conductors on the top surface of the interposer, so that step currents caused by the processor chip which is coupled to the top surface of the interposer enter and leave the plurality of bypass capacitors through the top surface of the interposer.