Patent ID: 7818502
Filing Date: 2010-10-19
Classification: G06F,Y02D

Abstract:
1. An arithmetic processing device comprising: a cache memory comprising at least one set including a data memory and a tag memory; a set control circuit; a counting circuit; and a register, wherein the counting circuit counts the number of accesses to the cache memory, the number of cache hits of the cache memory and the number of tag hits of the tag memory per set; wherein a cache hit rate is obtained by dividing the number of cache hits by the number of accesses in an arbitrary period; wherein a tag hit rate per set is obtained by dividing the number of tag hits per set by the number of accesses to the cache memory in the arbitrary period; and wherein a state of one of the data memory and the tag memory is transitioned to be at an operating state or a resting state by the set control circuit.