Patent ID: 8482052
Filing Date: 2013-07-09
Classification: G11C,H01L

Abstract:
1. An integrated circuit memory device, comprising: a semiconductor body on an insulating layer; a plurality of gates arranged in series on the semiconductor body, the plurality of gates including a first gate in the series and a last gate in the series, with insulating members isolating gates in the series from adjacent gates in the series; and a charge storage structure on the semiconductor body, the charge storage structure including dielectric charge trapping locations beneath more than one of the plurality of gates in the series, the charge storage structure including a tunnel dielectric structure disposed above the semiconductor body, a charge storage layer disposed above the tunnel dielectric structure, and an insulating layer disposed above the charge storage layer; wherein the tunnel dielectric structure consists of (a) a bottom dielectric layer having a thickness less than about 2 nm and having a hole tunneling barrier height, (b) a middle dielectric layer on the bottom dielectric layer, the middle dielectric layer having a hole tunneling barrier height less than that of the bottom dielectric layer, the middle dielectric layer having a thickness of less than 3 nm, and (c) a top dielectric layer having a hole tunneling barrier height greater than that of the middle dielectric layer, the top dielectric layer having a thickness of about 3.5 nm or less; and wherein the semiconductor body includes a continuous, multiple-gate channel region beneath the plurality of gates in the series.