Patent ID: 6823431
Filing Date: 2004-11-23
Classification: G06F

Abstract:
A multi-processor system, comprising:at least first and second processors; a system bus providing communication between said first and second processors; a bus arbiter generating system responses to commands on said system bus; and wherein said first processor includes at least a level one cache, a system bus controller controlling communication between said first processor and said system bus, and a transition cache controlling and tracking communication between each level of cache and said system bus controller; and said system bus controller checks a reservation of a first command, said first command being a system bus command for transferring data on said system bus which requires a reservation, generated by said level one cache prior to placing said first command on said system bus, and converts said first command into a second command, said second command being a system bus command for transferring data on said system bus which does not require a reservation, when said reservation for said first command has been lost; and said transition cache receives said first command from said level one cache and communicates said first command to said system bus controller, snoops said second command on said system bus, and converts said first command stored therein into said second command based on said snooping of said second command.