Patent ID: 6049866
Filing Date: 2000-04-11
Classification: G06F

Abstract:
In a computer system having a processor coupled to a bus, a memory coupled to said bus, said processor having an instruction cache and a data cache, a method of synchronizing said instruction cache and said data cache from a program running in a user mode, wherein the processor does not include hardware support for a user mode cache synchronization instruction, said method comprising the computer implemented steps of:a) detecting a simulated instruction in a user mode executed program, said instruction, when executed, causing an error exception within said computer system;b) responsive to said error exception, executing a trap handler program running in a kernel mode to perform the steps of:b1) identifying said simulated instruction as an instruction cache manipulation instruction, wherein said instruction cache manipulation instruction is a privileged kernel mode instruction;b2) accessing an address range associated with said instruction cache manipulation instruction by reading a first predefined register to obtain a start address of said address range and reading a second predefined register to obtain an end address of said address range, the values of said first predefined register and said second predefined register determined by said user mode executed program;b3) invalidating each entry of said instruction cache that includes an address within said address range;b4) writing back entries of said data cache to said memory; andc) returning control to said user mode executed program.