Patent ID: 6468838
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method for fabricating a metal oxide semiconductor (MOS) transistor of an embedded memory, the method comprising:providing a semiconductor wafer with both a memory array area and a periphery circuit region defined on the surface of a silicon substrate of the semiconductor wafer; forming a first dielectric layer, an undoped polysilicon layer, a silicide layer, a doped polysilicon layer, a protection layer and a first photoresist layer respectively on the surface of the semiconductor wafer; performing a first photolithographic process so as to define a plurality of gate patterns in the first photoresist layer above the memory array area; using the gate patterns in the first photoresist layer as a hard mask to etch the protection layer down to the surface of the doped polysilicon layer; removing the first photoresist layer; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second photolithographic process to define a plurality of gate patterns in the second photoresist layer above the periphery circuit region; using the gate patterns of the second photoresist layer and the remaining portions of the protection layer above the memory array area as a hard mask to etch the doped polysilicon layer, the silicide layer and the undoped polysilicon layer down to the surface of the dielectric layer so as to form the gates for each MOS transistor in the memory array area and in the periphery circuit region; removing the second photoresist layer; performing a first ion implantation process to form a lightly doped drain (LDD) for each MOS transistor; forming a silicon nitride layer and a second dielectric layer respectively on the surface of the semiconductor wafer; performing an etching process to remove the second dielectric layer above the periphery circuit region and etching portions of the silicon nitride layer to form a spacer adjacent to each gate in the periphery circuit region; and performing a second ion implantation process to form a source and a drain for each MOS transistor in the periphery circuit region.