Patent ID: 7406585
Filing Date: 2008-07-29
Classification: G06F

Abstract:
1. Apparatus for processing data, said apparatus comprising: (i) an execution core for executing internal instructions; (ii) a translation buffer for storing a plurality of internal instruction blocks of one or more internal instructions, said internal instruction blocks comprising a dynamic translation of respective external instruction blocks of one or more external instructions; (iii) a remapper, responsive to an execution request for an external instruction that is within one of said external instruction blocks, for identifying a corresponding internal instruction block stored within said translation buffer and for supplying one or more internal instructions from said corresponding internal instruction block to said execution core, said remapper for storing in a remapper memory mapping data identifying a mapping between an address of an external instruction block and an address of a corresponding internal instruction block within said translation buffer; and said remapper memory is divided into a plurality of remapper memory portions each memory portion associated with a respective translation buffer portion within said translation buffer and at least one of said remapper memory portions stores a plurality of mappings comprising at least one mapping for an external instruction block comprising a plurality of external instructions, only one of said remapper memory portions receives newly generated mapping data until said associated translation buffer portion no longer has free space to accept newly generated internal instruction blocks whereupon another of said remapper memory portions is selected and cleared and newly generated mapping data is stored therein with newly generated internal instruction blocks being stored in an associated translation buffer portion.