Patent ID: 7877529
Filing Date: 2011-01-25
Classification: G11B,H04J

Abstract:
1. A serial-to-parallel conversion apparatus, comprising: an input configured to receive first and second segments of bits in a continuous stream of serial data bits, the continuous stream divided into consecutive segments, each segment divided into groups of bits, each group of bits having an equal number of bits; a plurality of sync counters, each sync counter configured to store one bit group in the first segment of bits; a state machine configured to cause each sync counter to increment the bit group stored in that sync counter; a comparator configured to compare each incremented bit group of the first segment stored in the sync counters with a corresponding bit group in the second segment; a plurality of status flags, each status flag corresponding to one of the sync counters and configured to indicate whether a bit group in the corresponding sync counter is active; and a detector configured to detect a status of each of the status flags; wherein the detector is configured to send a counter offset signal to the state machine and the state machine is configured to move a boundary between segments when the detector detects that only one of the status flags is set to “active”.