Patent ID: 8232954
Filing Date: 2012-07-31
Classification: G11C

Abstract:
1. A shift register comprising a plurality of serially connected stages, wherein one of the stages is connected to an input line of a start pulse, the shift register being driven by first, second, and third clock signals, respectively input to first, second and third input lines, wherein each of the stages comprises: a first transistor coupled between a first power source and an output node, the first transistor having a gate electrode coupled to a first node; a second transistor coupled between the output node and the third input line, the second transistor having a gate electrode coupled to a second node; a third transistor coupled between the first power source and the first node, the third transistor having a gate electrode coupled to an input terminal to which the start pulse or an output signal of a previous stage is input; a fourth transistor coupled between the first node and a second power source, the fourth transistor having a gate electrode coupled to the first input line; a fifth transistor coupled between the second node and a third node, the fifth transistor having a gate electrode coupled to the second power source; a sixth transistor coupled between the third node and the second power source, the sixth transistor having a gate electrode coupled to the input terminal; and a voltage controller coupled between the first and second power sources, the voltage controller being further coupled to the input terminal, the first input line and the third node, wherein the voltage controller is configured to control the voltage at the third node in response to the start pulse or output signal of the previous stage and the first clock signal.