Patent ID: 9077350
Filing Date: 2015-07-07
Classification: G11C,H03L

Abstract:
1. A delay-locked loop circuit, comprising: at least one phase detector to receive a feedback clock and a first clock to generate first and second phase detecting signals, respectively; and a coarse-lock detector to generate a coarse-lock signal based on changes of phase of the first and second phase detecting signals, wherein the phase changes include a change from in-phase state to an out-of phase state, and wherein the at least one phase detector includes: a first phase detector to generate the first phase detecting signal according to a level of the first clock at a front end of the feedback clock; a first delay circuit to generate a first delayed feedback signal by delaying the feedback clock for a first delay time; and a second phase detector to generate the second phase detecting signal according to the level of the first clock at a front end of the first delayed feedback clock.