Patent ID: 6427225
Filing Date: 2002-07-30
Classification: G03F,G06F

Abstract:
A layout verifying method for converting a layout figure on a semiconductor integrated circuit into vector data by means of vectors corresponding to the sides of the layout figure and verifying whether or not the layout figure conforms to a design rule on the basis of said vector data, said method comprising:a reference vector selecting step for selecting a reference vector which serves as a verification reference by its direction among vectors corresponding to said sides; a verification object vector selecting step for executing search in a specified direction from said reference vector among said vectors corresponding to said sides and selecting an object vector to be verified; and a verifying step for verifying a distance between each reference vector and said object vector to be verified, wherein said verifying step includes making a new reference vector of an error vector outputted as an error and selecting a new object vector to be verified in correspondence with said new reference vector among said vectors corresponding to said sides and executing verification by a distance between said new reference vector and said new object vector to be verified corresponding to said new reference vector and a distance obtained through the above verification.