Patent ID: 8077535
Filing Date: 2011-12-13
Classification: G11C

Abstract:
1. A method, comprising: simulating at least one first DRAM memory circuit having a first memory capacity and a first row refresh cycle time (tRFC) using an interface circuit connected to a plurality of second DRAM memory circuits each having a second memory capacity that is smaller than the first memory capacity and a second tRFC that is less than the first tRFC; receiving, at the interface circuit, a refresh control signal from a memory controller; and in response to receiving the refresh control signal from the memory controller, sending from the interface circuit a first refresh control signal to a first subset of the second DRAM memory circuits and a second refresh control signal to a second subset of the second DRAM memory circuits, wherein the first and the second refresh control signals are sent at different times with the different times being selected so that refresh cycles of the second DRAM memory circuits initiated by the first and second refresh control signals complete within a time span specified by the first tRFC associated with the at least one first DRAM memory circuit.