Patent ID: 7024533
Filing Date: 2006-04-04
Classification: G06F

Abstract:
1. A memory controller, comprising: a plurality of multi-entry read buffers each coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command; a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded; a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers; and wherein during initialization all of said unload pointer logic circuits receive a read strobe signal that causes the unload pointer logic circuits to release their unload pointers to begin incrementing, and a clock signal to increment the unload pointers.