Patent ID: 7926011
Filing Date: 2011-04-12
Classification: G06F

Abstract:
1. A method of designing a circuit, the method comprising: receiving top chip level timing constraints for a top chip level circuit design; with a processor, partitioning the top chip level circuit design into at least a first lower-level circuit design and a second lower-level circuit design; with a processor, determining a logical timing constraint point for a port of the first lower-level circuit design in response to the top chip level timing constraints of the top chip level circuit design, wherein the logical timing constraint point includes with a processor, after determining the logical timing constraint point, optimizing the first lower-level circuit design to implement the first lower-level circuit design and performing a lower level timing analysis on the implementation of the first lower-level circuit design using the logical timing constraint point to determine if the implementation of the first lower-level circuit design meets the data propagation delay specified by the delay parameter of the logical timing constraint point.