Patent ID: 7661043
Filing Date: 2010-02-09
Classification: G01R,G11C

Abstract:
1. A test apparatus for testing a memory-under-test, comprising: an address control apparatus comprising: a pattern generating section for generating test patterns; a data selecting section for selecting either said test patterns generated by said pattern generating section or said data patterns outputted by said pattern memory to input to said memory-under-test; and a judging section for reading data written in each address of said memory-under-test to judge whether a block corresponding to the address is good or bad based on the read data, wherein said address generating section further generates random addresses of said pattern memory, said pointer section generates sequential addresses of said pattern memory, and said test apparatus further includes a pattern memory address selecting section for selecting either said random addresses generated by said address generating section or said sequential addresses generated by said pointer section to input to said pattern memory.