Patent ID: 8922023
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first metallization layer comprising a first dielectric material and a first metal region laterally embedded in said first dielectric material, said first metal region having a first lateral metal extension in a first lateral direction and a second lateral metal extension in a second lateral direction; a via receiving region comprising an etch stop material, said via receiving region being above said first metal region, said via receiving region having a first lateral via region extension and a second via region extension in said first and second lateral via region directions, respectively, at least one of said first and second lateral via region extensions being less than at least one of said first and second lateral metal extensions; and a second metallization layer formed above said first metallization layer, said second metallization layer comprising a second metal region and a via, said via extending through said via receiving region to conductively couple to said first metal region.