Patent ID: 6073228
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A circuit for generating an updated address pointer, comprising:an address pointer latch adapted to retain a current address pointer;an adder adapted to receive the current address pointer as a first input and a displacement as a second input, the adder adapted to add the inputs to provide an output;a comparator adapted to receive as a first input the current address pointer and as a second input an ending address of a circular buffer, the comparator adapted to compare the first and second inputs ignoring least significant bits thereof when the displacement is greater than one, the comparator adapted to provide an output that is a first state when the inputs are the same and an output that is a second state when the inputs are different; anda control circuit, the control circuit adapted to receive an indicator of a beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer the control circuit adapted to provide the beginning address to the address pointer latch as an updated address pointer when the comparator output is in the first state, the control circuit adapted to provide the output of the adder to the address pointer latch as an updated address pointer when the indicators take on predetermined values and the comparator output is in the second state.