Patent ID: 6995087
Filing Date: 2006-02-07
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit comprising: providing a base; forming a first conductor on the base; forming a first barrier layer over the first conductor; forming a first dielectric layer over the first barrier layer; forming a second barrier layer over the first dielectric layer; forming a masking layer over the first dielectric layer; forming a first via opening in the masking layer; forming a first trench opening in the masking layer and simultaneously forming a second via opening in the second barrier layer and a layer under the masking layer; forming a second trench opening through the masking layer and in the layer under the masking layer using the first trench opening and simultaneously forming a third via opening in another layer under the masking layer using the second via opening; removing the first barrier layer using the third via opening and the masking layer to form a trench and a via; and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.