Patent ID: 6638776
Filing Date: 2003-10-28
Classification: H01L,Y10S

Abstract:
A method of standardizing a fabrication process for an integrated circuit, where the fabrication process includes a preceding thermal energy sensitive process and at least one set of selectable succeeding thermal energy delivery processes, where each one of the set of selectable succeeding thermal energy delivery processes delivers different amounts of thermal energy to the integrated circuit, where one of the different amounts of thermal energy is a greatest amount of thermal energy as compared to the different amounts of thermal energy the method comprising the steps of:forming an integrated circuit structure using the preceding thermal energy sensitive process, where the preceding thermal energy sensitive process is characterized based upon the greatest amount of thermal energy delivered to the integrated circuit by one of the set of selectable succeeding thermal energy delivery processes, and in the case where one of the set of selectable succeeding thermal energy delivery processes is selected that delivers an actual amount of thermal energy to the integrated circuit that is less than the greatest amount of thermal energy, delivering an additional amount of thermal energy to the integrated circuit equal to a difference between the actual amount of thermal energy and the greatest amount of thermal energy.