Patent ID: 6259904
Filing Date: 2001-07-10
Classification: H03G

Abstract:
A squelch circuit, comprising:a bandpass amplifier coupled to a demodulated signal, that generates a noise signal from the demodulated signal;a resettable noise integrator coupled to the bandpass amplifier, wherein the resettable noise integrator has essentially no decay rate and generates an integrated noise signal from the noise signal when a release of a reset control is performed, and wherein the integrated noise signal increases starting when the reset control is released towards a squelch voltage at a rate determined by an amount of energy in the noise signal;a memory coupled to the resettable noise integrator, for pre-storing a digitized first squelch voltage and a digitized second squelch voltage;a noise level section coupled to the memory that,in response to a good signal squelch check request, releases the reset control and generates a result of a comparison of a digitized integrated noise signal to the digitized first squelch voltage at an expiration of a predetermined delay started at the release of the reset control; andin response to a poor signal squelch check request, releases the reset control and generates a result of a comparison of the digitized integrated noise signal to the digitized second squelch voltage at an expiration of a predetermined delay started at the release of the reset control; anda mute section coupled to the noise level section and the demodulated signal that generates the squelch check request and controls muting of a speaker in response to the result.