Patent ID: 8492289
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A method of forming a barrier layer for metal interconnects of an integrated circuit device, the method comprising: forming a conductive line in an insulating layer of the semiconductor device by forming a metal material over a seed layer that is an impurity alloy of the metal; forming a first cap layer over a top surface of the conductive line, wherein oxygen is a constituent element of the first cap layer; forming a second cap layer over the first cap layer, the second cap layer comprising an oxygen blocking cap layer; and following forming the second cap layer, forming subsequent device layers of the integrated circuit device using thermal processing so as to combine diffused impurity atoms of the seed layer with oxygen released by the first cap layer, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line, wherein the first cap layer provides a controllable oxygen source for combining with the impurity atoms.