Patent ID: 7151052
Filing Date: 2006-12-19
Classification: H01L

Abstract:
1. A process for forming a multi-level metal semiconductor device having a bonding structure to electrically couple the semiconductor device to another component, the process comprising: forming a first metal layer; forming a first insulating layer over the first metal layer; forming a first etch-stop layer between the first metal layer and first insulating layer, and having a substantially different strength of adhesion from both the first metal layer and the first insulating layer; forming a second metal layer over the first insulating layer; forming a second insulating layer over the second metal layer; forming a second etch-stop layer between the second metal layer and the second insulating layer, and having a substantially different strength of adhesion from both the second metal layer and the second insulating layer, wherein the difference in strength of adhesion of the second etch-stop layer from the second metal layer and second insulating layer differs from the difference in strength of adhesion of the first etch-stop layer from the first metal layer and first insulating layer such that a greater chemical bond exists between the one of the first or second etch-stop layers and its adjacent metal and insulating layers that will undergo more mechanical stress therebetween caused by a connection from the other component to the bonding structure than the other of the first or second etch-stop layer and its adjacent metal and insulating layers; and forming a third metal layer over the second insulating layer.