Patent ID: 7057435
Filing Date: 2006-06-06
Classification: H02M,H03K,H03L,H04L

Abstract:
1. A clock and data recovery system for aligning a local clock with a data stream, comprising: a first section configured to compare the phase of a data stream with the phase of a local clock and output a control voltage corresponding to the difference in phase between the data stream and clock, wherein the first section comprises a half-rate phase detector configured to compare the phase of the incoming data stream with a first and a second clock signal, the second clock signal being out of phase with the first clock signal, and a charge pump coupled with a the phase detector; and a variable delay line comprising a plurality of variable impedance LC subcircuits responsive to the control voltage, the variable delay line configured to delay the local clock by an amount corresponding to the control voltage, wherein the delayed local clock is fed back to the first section.