Patent ID: 8560927
Filing Date: 2013-10-15
Classification: G06F

Abstract:
1. An integrated circuit, comprising: a plurality of memory elements; error detection circuitry coupled to the plurality of memory elements, wherein the error detection circuitry is coupled to the memory elements using data bit lines that carry data bits and check bit lines that carry check bits, wherein the check bit lines are interspersed throughout the data bit lines, and wherein the error detection circuitry comprises encoder circuitry that receives the data bits at an input, that provides the data bits to the data bit lines, and that includes an encoder that generates the check bits for the check bit lines based on the received data bits; and a respective multiplexer having a first input that receives the check bits from the encoder circuitry, a second input that receives a respective one of the data bits, and an output that is coupled to a corresponding check bit line of the check bit lines.