Patent ID: 6426743
Filing Date: 2002-07-30
Classification: G09G,G11C

Abstract:
A shift register circuit comprising a plurality of cascaded stages connected to a start pulse input line and driving sequentially a plurality of row lines, each of the stages having an input terminal, an output terminal, a low level voltage line and being connected to first to third clock signal lines, the input terminal receiving an output signal of a previous stage, and the output terminal being connected to a row line, each one of the stages comprising:a pull-up transistor having a control electrode and a conduction path connected between the first clock signal line and the output terminal; a pull-down transistor having a control electrode and a conduction path connected between the low level voltage line and the output terminal; first and second transistors having conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each having a control electrode, connected commonly to the second clock signal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor and, each having a control electrode connected commonly to the third clock signal line, the third and fourth transistors allowing a voltage to be charged on the control electrode of the pull-down transistor.