Patent ID: 7243317
Filing Date: 2007-07-10
Classification: G06F

Abstract:
1. A smart parameter checking method for on-chip ESD protection circuit physical design layout verification, comprising: a) determining a first list of ESD devices, the first list including both parasitic ESD devices and all intentional ESD devices contained in the layout; b) determining a critical operating parameter of the listed intentional and parasitic ESD devices; c) comparing the critical operating parameter of the listed intentional and parasitic ESD devices and determining if the parasitic ESD devices will interfere with the operation of the intentional ESD devices to cause ESD protection malfunction; d) eliminating parasitic ESD devices which do not interfere with the operation of the intentional ESD devices from the first list and; e) providing a second list of ESD devices for verifying the validity of the ESD design layout, the second list including the intentional ESD devices and any parasitic ESD devices remaining after step (d).