Patent ID: 6246628
Filing Date: 2001-06-12
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array, having a plurality of segments, each segment having a plurality of bit lines and a local data bus selectively coupled to one of said bit lines;a data input/output buffer circuit connected to a global data bus;read/write amplifiers, disposed for respective segments, each read/write amplifier being between said local data bus of corresponding segment and said global data bus, each read/write amplifier having a read amplifier and a write amplifier; andsegment selection circuits, disposed adjacent respective read/write amplifiers, arranged in a row, each for activating corresponding read or write amplifier in response to signals on segment address lines, a read timing signal line and a write timing signal line,wherein said segment address lines, said read timing signal line and said write timing signal line are laid out along said row of said segment selection circuits.