Patent ID: 8823076
Filing Date: 2014-09-02
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a silicon substrate; a first vertical channel located over the silicon substrate; a second vertical channel located horizontally adjacent to the first vertical channel in a first row over the silicon substrate; a third vertical channel located horizontally adjacent to the first vertical channel in a second row different from the first row over the silicon substrate; contacts coupling to the first vertical channel; contacts coupling to the second vertical channel; contacts coupling to the third vertical channel; a first charge storage region located adjacent to a first portion of the first vertical channel; a first control gate located adjacent to the first charge storage region; a second charge storage region located adjacent to a second portion of the first vertical channel above the first portion of the first vertical channel; and a second control gate located adjacent to the second charge storage region; wherein the first charge storage region and the second charge storage region comprise a continuous charge storage dielectric film and a continuous tunneling dielectric located between the first vertical channel and both the first and the second control gates; and wherein the first control gate is shared between the first vertical channel, the second vertical channel and the third vertical channel; and driver circuitry associated with the operation of said memory device.