Patent ID: 6366223
Filing Date: 2002-04-02
Classification: H03M

Abstract:
A method for coding a line code used for a transmission, an interconnection and storing apparatus, comprising:a first step for adding a one redundancy bit with respect to a n-bit (n represents an odd number higher than 3) source data to generate a pre-code; a second step for setting the pre-code as a code word when a disparity of the pre-code generated in the first step is 0 and the source data is not an in-band signal (or special character); a third step for inverting a half block (nibble) including a redundancy bit among the bits (block) forming a pre-code when the disparity of the pre-code generated in the first step is 0 and the source data is a set in-band signal (or special character), setting the nibble-inverted pre-code as a code word and generating a complement code word which is a block-inverted code word version and a code word; a fourth step for nibble-inverting a pre-code when the disparity of the pre-code generated in the first step is not 0, setting a nibble-inverted pre-code as a code word when the disparity of the nibble-inverted pre-code is within a predefined value and generating a complement code word which is a block-inverted code word and a code word when the disparity of the set code word is not 0; a fifth step for nibble-inverting the pre-code when the disparity of the pre-code generated in the first step is not 0, manipulating the bits of the pre-code when the disparity of the nibble-inverted pre-code is not within a predefined value, manipulating the bits of the pre-code so that the disparity of the nibble-inverted pre-code is within a predefined value when the disparity of the manipulated pre-code is 0 and concurrently manipulated, setting the manipulated and nibble-inverted pre-code as a code word, and generating a complement code word which is a block-inverted code word version and a code word when the disparity of the set code word is not 0; a sixth step for selecting a code word in which the absolute value of the running digital sum (RDS) is decreased when the code with respect to the source data exists as two values of a complement code word and a code word; and a seventh step for combining the code words for a frame synchronization and generating a synchronization code word so that a pattern is formed from a serial bit stream when the code word is converted from a parallel form to a serial form.