Patent ID: 9053818
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A circuit comprising: a PMOS transistor having a PMOS drain, a PMOS source, and a PMOS gate; an NMOS transistor having an NMOS drain, an NMOS source, and an NMOS gate; and a logic level generation section comprising an input and a logic level output; wherein the PMOS gate is configured to receive an input voltage having a voltage level determined based on an operational voltage; the PMOS drain is coupled to the NMOS drain and the input of the logic level generation section; the PMOS source is coupled to the operational voltage; the NMOS gate is configured to receive a voltage that causes the NMOS transistor to have a first driving capability; and the first driving capability of the NMOS transistor is less than that of the PMOS transistor if the input voltage has a voltage level greater than a predetermined voltage level.