Patent ID: 7687856
Filing Date: 2010-03-30
Classification: H01L,H03F

Abstract:
1. A method for matching transistors in an integrated circuit, comprising: forming a plurality of transistors over a semiconductor body, the transistors each comprising matched configurations of a gate electrode; spacers disposed about lateral edges of the gate electrode; pocket implant regions formed in the body substantially under the spacers and having pocket potential barriers associated therewith; and a source and a drain formed in the body and disposed laterally from the pocket implant regions; and applying a body-source bias to forward bias a pn junction between the source and body of each transistor, which forward bias reduces a magnitude of at least one of the pocket potential barriers associated with the pocket implant regions relative to a bulk potential of that transistor; whereby differences in source-to-drain current flow between ones of the transistors will be less affected by variations in concentrations of dopant in the respective pocket implant regions.