Patent ID: 6251725
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method of fabricating a DRAM storage node on a semiconductor wafer, the semiconductor wafer comprising a substrate, a first conductive layer positioned in a predetermined area on the surface of the substrate, and a dielectric layer positioned on the surface of the substrate covering the first conductive layer, the method comprising:forming a thin-film layer over the dielectric layer, the thin-film layer comprising a hole that penetrates down to the surface of the dielectric layer, the hole located above the first conductive layer;forming a first barrier layer on the surface of the semiconductor wafer to cover the thin-film layer and the internal walls of the hole;forming a spacer on the internal walls of the hole;performing a first dry etching process using the thin-film layer and the spacer as hard masks to form a contact hole that penetrates the dielectric layer down to the surface of the first conductive layer;forming a second barrier layer on the internal walls of the contact hole, the second barrier layer connecting with the first barrier layer;forming a second conductive layer on the surface of the semiconductor wafer that fills the contact hole;forming a first photo resist layer on the second conductive layer;performing a first lithographic process to define a pattern and a location of the storage node in the first photo resist layer above the contact hole;performing a second dry etching process to etch the second conductive layer using the first photo resist layer as a mask so as to form the storage node; andremoving the first photo resist layer.