Patent ID: 8564049
Filing Date: 2013-10-22
Classification: H01L

Abstract:
1. A power device package comprising: a power transistor formed as an integrated circuit (IC) chip on a semiconductor die wherein the IC chip having a top flat-surface die electrode and at least a bottom flat-surface die electrode wherein the power device package further containing, protecting and providing electrical contacts for the IC chip; the power device package further comprising a top metal plate directly contacting substantially a majority area of the top flat-surface die electrode for directly soldering to said top flat-surface die electrode of the IC chip as a top metal-surface-soldered-to-metal-surface attachment without any intermediate bonding or attachment layer between the top metal plate and the top flat-surface die electrode; and the power device package further comprising a bottom metal plate directly contacting substantially a majority area of the bottom flat-surface die electrode for directly soldering to said bottom flat-surface die electrode of the IC chip as a bottom metal-surface-soldered-to-metal-surface attachment without any intermediate bonding or attachment layer between the bottom metal plate and the bottom flat-surface die electrode.