Patent ID: 6477631
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A method of activating a row or column in each of a plurality of memory arrays in a packetized memory system, comprising the steps of:latching a first command packet; capturing a first set of addresses from the latched first command packet; latching the captured first set of addresses in response to a first timing signal; activating a first row or column of a first one of the memory arrays in response to the latched captured first set of addresses and a second timing signal; latching a second command packet; capturing a second set of addresses from the latched second command packet, the capturing of the second set of addresses starting during a first time interval for which the first row or column in the first one of the memory arrays is activated; latching the captured second set of addresses in response to a third timing signal; and activating a first row or column in a second one of the memory arrays in response to the latched captured second set of addresses and a fourth timing signal.