Patent ID: 6670240
Filing Date: 2003-12-30
Classification: G11C,H01L

Abstract:
A method to produce a twin MONOS memory cell array, comprising:a) preparing a semiconductor substrate to form cells of a twin MONOS memory array b) forming mask elements on a surface of said semiconductor substrate; c) implanting a lightly doped region between said mask elements and within said lightly doped region implanting a heavily doped region; d) forming a first insulator between said mask elements over said lightly doped region; e) planarizing the surface of said substrate, and stopping when said mask elements are detected; f) removing said mask elements and forming a second insulator over the surface of said substrate; g) forming sidewall spacers on sidewalls of said second insulator between regions of said first insulator and removing exposed areas of said second insulator; h) removing said sidewall spacers and forming a third insulator over surface of said substrate; i) forming a conductive layer on said third insulator between said regions of the first insulator.