Patent ID: 7306962
Filing Date: 2007-12-11
Classification: C23C,C25D,H01L

Abstract:
1. A method for electroforming metal integrated circuit structures, the method comprising: forming an opening through a first interlevel insulator, exposing a substrate surface; forming a base layer overlying the first interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; electroforming a first metal structure overlying the strike layer surface; using the first metal structure as a mask, removing the base, strike, and top layers overlying the first interlevel insulator; conformally depositing a second interlevel insulator; forming an opening through the second interlevel insulator, exposing a first metal structure surface; forming a base layer overlying the second interlevel insulator and first metal structure surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the first metal structure surface, exposing a strike layer surface; and, electroforming a second metal structure overlying the strike layer surface.