Patent ID: 6320213
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate;a conductive plug formed over the substrate;a buffet layer formed on the plug;a first diffusion barrier layer covering the entire buffer layer;a first capacitor electrode laid over the first diffusion barrier layer, wherein the diffusion barrier layer isolates the electrode from underlying layers;a layer of high dielectric constant material laid over the first capacitor electrode;a second capacitor electrode laid over the high dielectric constant material;a second diffusion barrier layer laid over the second capacitor electrode; anda conductor connecting with the second diffusion barrier layer, wherein the first and second diffusion barrier layers are conductive and independently comprise materials selected from the group consisting of:(a) amorphous nitrides selected from the group consisting of: TiSiN, TaBN, IiBN, and TaSiN,(b) exotic conductive nitrides selected from the group consisting of: TiAlN, Hfn, YN, ScN, LaN, rare earth nitrides, N-deficient AlN, doped AlN, MgN, CaN, SrN, BaN, and alloys thereof with an alloying component selected from the group consisting of Ti, Ga, Ni, Co, Ta and W, and(c) noble-metal-insulator-alloys selected from the group consisting of PdSiN, PtSiN, PtSiO, PdSiO, PdBO, PdBN, PdAlO, PdAIN, RuSiO, RuSiN, IrSiO, IrSiN, ReSiO, ReSiN, RhAlO, AuSiN and AgSiN.