Patent ID: 8149620
Filing Date: 2012-04-03
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a cell array including a plurality of blocks each of which is formed of a plurality of strings, each string including a plurality of memory cells assigned by an external address and connected to corresponding word lines and at least one memory cell not assigned by the external address and connected to a dummy word line; a storage device configured to store position data that selects the at least one memory cell; a pre-decoder configured to translate the external address to an internal address in response to the position data; a decoder configured to supply word line voltages to the word lines in response to the internal address and a control signal; a control unit configured to generate the control signal in response to the position data, wherein the control unit controls a driver so that the at least one memory cell connected to the dummy word line is programmed to a predetermined state after an erase operation.