Patent ID: 8953784
Filing Date: 2015-02-10
Classification: H04L

Abstract:
1. A method executable on a processing device having a processor and a memory for generating a linear cryptographic keystream on the processing device, comprising: i) performing by the processor loading a secret key and an initial vector (IV) into a linear feedback shift register (LFSR); ii) performing by the processor running the LFSR for an initial clock cycle with a nonlinear feedback Welch-Gong n-bit (WG-n) transformation module as a filtering function, wherein a Welch-Gong (WG) transformation comprises a Welch-Gong (WG) permutation and trace function, and wherein n is equal to 2.sup.k, and wherein n and k are positive integers, such that a finite field (Galois-field) GF(2.sup.(2.sup.k)) can be decomposed into an equivalent tower field representation GF((((2.sup.2).sup.2) . . . ).sup.2); and iii) outputting a 1-bit keystream from the WG-n transformation module for each clock cycle after the initial clock cycle; thereby performing a memory-optimized implementation of a Welch-Gong (WG) transformation utilizing a stream cipher equivalent tower field representation.