Patent ID: 6330698
Filing Date: 2001-12-11
Classification: G01R

Abstract:
A method for modifying a representation of a digital circuit in order to allow a scan test, the digital circuit having one or more combinational subcircuits, having one or more memory elements, and having circuit structures with reconvergent signal paths including sequentially redundant structures, the method comprising:searching the digital circuit for each reconvergent structure that has at least two reconvergent paths with a mutual equal number of memory elements, the searching including the reconvergent structures that are sequentially redundant and not excluding at least one structure that is not sequentially redundant;for each reconvergent structure found in the digital circuit, subsequently selecting from the memory elements of said each reconvergent structure one of the memory elements to be made scannable;replacing the selected memory elements by respective scannable memory elements; andconnecting the scannable memory elements into one or more scan chains.