Patent ID: 6236224
Filing Date: 2001-05-22
Classification: G01R

Abstract:
A method of operating an integrated circuit, which comprises:providing a wafer with a plurality of integrated circuits and defined scribe lanes along which the wafer is to be severed for separating the integrated circuits, the integrated circuits having an internal signal line connected, via a switching element having a terminal, to an external signal line running in a scribe lane;prior to a separation of one of the integrated circuits from the wafer, energizing the switching element and transmitting signals between the internal signal line and the external signal line via the switching element;separating the integrated circuits and interrupting the connection between the switching element and the external signal line at an interface, the terminal connected to the interface;after the separation of at least one of the integrated circuits from the wafer:connecting the terminal of the switching element to a fixed potential after the separation of the integrated circuit; andpermanently disabling the switching element and thereby disconnecting the internal signal line from the interface; andproviding a separated one of the integrated circuits with an electrically conductive protective sleeve connected to the fixed potential.