Patent ID: 8922428
Filing Date: 2014-12-30
Classification: G01S

Abstract:
1. A system comprising: a first memory comprising a first plurality of columns and a first plurality of rows; a sampler configured to sample a first portion of a signal during a first plurality of periods to obtain first sets of samples, respectively, wherein the first sets of samples comprise (i) a first set having a first plurality of samples, and (ii) a second set having a second plurality of samples; a first controller configured to write each set in the first sets of samples in a respective one of the first plurality of columns, wherein the first controller is configured to a second controller configured to, subsequent to the first controller writing the first plurality of samples and the second plurality of samples in the first memory, read (i) a third plurality of samples stored in a first row of the first memory, and (ii) a fourth plurality of samples stored in a second row of the first memory.