Patent ID: 8502523
Filing Date: 2013-08-06
Classification: G01R

Abstract:
1. A test apparatus that tests a device under test including a plurality of clock domains, the test apparatus comprising: a period generator that generates a rate signal for determining a test period corresponding to an operation period of the device under test; a pattern generator that generates a test pattern; phase comparing sections that, for each clock domain, receive an operation clock signal of the clock domain acquired from a terminal of the device under test included in the clock domain, and detect a phase difference of the operation clock signal of the clock domain with respect to the rate signal; and a plurality of waveform shaping sections that are provided respectively to the clock domains, and that each shape a test signal based on the test pattern, according to the phase difference of the corresponding clock domain, to substantially synchronize the test signal with the operation clock signal of the corresponding clock domain.