Patent ID: 6953725
Filing Date: 2005-10-11
Classification: H01L

Abstract:
1. A fabrication method for a memory device that comprises a deep trench, the method comprising: providing a substrate; forming a plurality of deep trenches in the substrate, wherein the deep trenches are rectangular shape when viewing from a top, and each trench comprises a first short side and a second short side, and between the first short side and the second short side of any two corresponding deep trenches is a pre-defined region for an active region; forming a doped region in the substrate around a lower part and a bottom part of each deep trench; forming a conformal dielectric layer on a bottom part and a sidewall of the lower part of each deep trench; forming a first conductive layer in the bottom part and the lower part of the deep trench encompassed by the first dielectric layer; forming a collar oxide layer at a periphery of a middle pair of each deep trench; forming a second conductive layer in each deep trench, encompassed by the collar oxide layer; forming an undoped semiconductor layer in the upper part of each deep trench; implanting dopants into the undoped semiconductor layer, except at the periphery of the first short side and the second short side of each deep trench, to form a third conductive layer; removing a portion of the third conductive layer, a portion of the collar oxide layer and a portion of the substrate inside the deep trenches to form a plurality of shallow trenches in the substrate; and filling in an insulation layer in each of the shallow trenches to form a plurality of isolation structures and to define a plurality of active regions in the pre-defined region for the active region.