Patent ID: 9099991
Filing Date: 2015-08-04
Classification: H03K

Abstract:
1. A NAND gate, comprising: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate and a seventh thin film transistor outputting the first power voltage to the output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor transferring a ground voltage according to a first input signal applied to a gate and a tenth thin film transistor outputting the ground voltage transferred from the fifth thin film transistor to the output terminal according to a second input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the first input signal and applying the second power voltage or the ground voltage to the gate of the seventh thin film transistor according to the second input signal; wherein the pull-up driver includes: a first thin film transistor in which a gate is connected to a first node, a drain is connected to the second power voltage, and a source is connected to a second node; a third thin film transistor in which a gate is connected to a first input terminal, a drain is connected to the first node, and a source is connected to the ground voltage.