Patent ID: 7535060
Filing Date: 2009-05-19
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor structure having a first sidewall and a channel region, wherein a portion of said channel region is disposed along said first sidewall, and wherein the channel region is disposed between first and second current electrode regions; first and second charge storage structures disposed adjacent to the first sidewall and adjacent to the portion of the channel region disposed along the first sidewall, wherein the first and second charge storage structures are electrically isolated from each other and from the semiconductor structure; a first control electrode formed adjacent to the first sidewall; a first dielectric layer disposed between the control electrode and the first sidewall; a second dielectric layer disposed between the control electrode and the first dielectric layer; and a third dielectric layer disposed between the first dielectric layer and the second dielectric layer; wherein a portion of the third dielectric layer is laterally disposed between the first charge storage structure and the second charge storage structure; wherein the first dielectric layer has a first lateral length L