Patent ID: 6835586
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device including an n-channel TFT and a p-channel TFT comprising the steps of:forming a first wiring line on a substrate, forming a first insulating layer on the first wiring line, forming an active layer of the n-channel TFT and an active layer of the p-channel TFT on the first insulating layer, wherein the active layer of the n-channel TFT is located over the first wiring line with the first insulating film interposed therebetween and the active layer of the p-channel TFT does not overlap any portion of the first wiring line, forming a second insulating layer on the active layer of the n-channel TFT and the active layer of the p-channel TFT, forming a second wiring line on the second insulating layer, and forming a LDD region in the active layer of the n-channel TFT; wherein the LDD region is provided overlapping the first wiring line and not overlapping the second wiring line.