Patent ID: 7872721
Filing Date: 2011-01-18
Classification: G02F

Abstract:
1. A method of fabricating a horizontal electric field switching liquid crystal display device, comprising the steps of: forming a first conductive pattern group including a gate line, a gate electrode, a lower gate pad electrode, a common line, a common electrode, a lower common pad electrode and a plurality of pixel electrodes on a substrate using a first mask process; forming a gate insulating film for covering the first conductive pattern group; forming a semiconductor pattern on the gate insulating layer and a second conductive pattern group on the semiconductor pattern, the second conductive pattern group including a source electrode, a lower data pad electrode, a drain electrode and first and second storage electrodes extending from the drain electrode using a second mask process; forming a protective film on the gate insulating film and over the second conductive pattern group and the semiconductor pattern; forming first, second, third, fourth and fifth contact holes using a third mask process; forming a third conductive pattern group including an upper data pad electrode, an upper gate pad electrode, an upper common pad electrode, first and second contact electrodes using a fourth mask process, wherein the first, second and third contact holes are formed by passing through the protective film and the gate insulating film and the fourth and the fifth contact holes are formed by passing through the protective film, wherein the first contact hole exposes side surfaces of the first storage electrode and the pixel electrodes, wherein the second contact hole exposes side surfaces of the second storage electrode and the pixel electrodes, wherein the third contact hole exposes the lower gate pad electrode, wherein the fourth contact hole exposes the lower data pad electrode, wherein the fifth contact hole exposes the lower common pad electrode, wherein the first contact electrode contacts the first storage electrode and the pixel electrodes, wherein the second contact electrode contacts the second storage electrode and the pixel electrodes, wherein the upper data pad electrode contacts the lower data pad electrode, wherein the upper gate pad electrode contacts the lower gate pad electrode, wherein the upper common pad electrode contacts the lower common pad electrode, wherein the third conductive pattern group is formed by patterning a conductive layer by a photolithography process and an etching process using the fourth mask, and wherein a common pad includes the lower common pad electrode connected to the semiconductor pattern, and the upper common pad electrode connected to the lower common pad electrode through the fifth contact hole exposing the lower common pad electrode.