Patent ID: 8193624
Filing Date: 2012-06-05
Classification: H01L

Abstract:
1. A semiconductor package assembly comprising: a first semiconductor package; a plurality of first solder balls attached to a first surface of the first semiconductor package; a circuit board having a plurality of mounting pads that is electrically connected to the plurality of first solder balls; a plurality of vias formed through the circuit board; a first underfill disposed between gaps of each of the plurality of first solder balls creating a void between at least two adjacent first solder balls; a plurality of second solder balls attached to a second surface of the first semiconductor package; and a second underfill disposed between gaps of each of the plurality of second solder balls creating a void between at least two adjacent second solder balls; wherein the first semiconductor package comprises: a first substrate having a first surface and a second surface, wherein a plurality of first conductive patterns is formed on the first surface of the first substrate and a plurality of second conductive patterns is formed on the second surface of the first substrate; a first semiconductor die attached to the first surface of the substrate; at least one first electrically conductive wire connecting at least one first conductive pattern and the first semiconductor die; a first encapsulant surrounding a periphery of the first electrically conductive wire and the first semiconductor die; wherein the plurality of first solder balls is electrically connected to at least one second conductive pattern; at least one third conductive pattern being formed on a periphery of the first encapsulant on the first surface of the first substrate; a second semiconductor package electrically connected to the third conductive pattern, wherein the second semiconductor package comprises: a second substrate having a first surface and a second surface, wherein a plurality of fourth conductive patterns is formed on the first surface and a plurality of fifth conductive patterns is formed on the second surface of the second substrate; a second semiconductor die attached to the first surface of the second substrate; at least one second electrically conductive wire electrically connecting at least one fourth conductive pattern and the second semiconductor die; and a second encapsulant being surrounding a periphery of the second electrically conductive wire and the second semiconductor die; wherein the plurality of second solder balls is electrically connected to at least one third conductive pattern, and at least one fifth conductive pattern; wherein the first underfill has been removed above a first group of the plurality of vias.