Patent ID: 6801455
Filing Date: 2004-10-05
Classification: G11C

Abstract:
A voltage generation circuit applied for a non-volatile semiconductor memory device, which has a memory cell array comprising multiple non-volatile memory elements,the non-volatile semiconductor memory device having plural working modes, a program mode for writing into each of the multiple non-volatile memory elements, an erase mode for erasing from each of the multiple non-volatile memory elements, a verify mode for reading each of the multiple non-volatile memory elements to verify either of a status of the writing and a status of the erasing, and a read mode for reading from each of the multiple non-volatile memory elements, the voltage generation circuit comprising: a booster circuit having at least a first booster module that boosts a power supply voltage and outputs a first boosted voltage corresponding to either of the program mode and the erase mode, and a second booster module that boosts the power supply voltage and outputs a second boosted voltage, which is different from the first boosted voltage, corresponding to the verify mode; and a control voltage generation circuit that generates at least a voltage corresponding to the program mode, based on the first boosted voltage, in the program mode, a voltage corresponding to the erase mode, based on the first boosted voltage, in the erase mode, and a voltage corresponding to the verify mode, based on the second boosted voltage, in the verify mode, as control voltages to control operations of each of the multiple non-volatile memory elements.