Patent ID: 8418089
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A computer readable non-transitory medium storing a design aiding program causing a computer to execute: mapping, among a plurality of worst-case corner candidates, a first worst-case corner candidate and a second worst-case corner candidate, an angle made by a first line which connects a point corresponding to the first worst-case corner candidate with a predetermined point and a second line which connects a point corresponding to the second worst-case corner candidate with the predetermined point being within a predetermined allowable range, after calculating, for each one of a plurality of condition sets, worst-case corner candidates on an equal probability plane representing a chip yield rate calculated from a capacity and a wafer yield rate of a SRAM circuit or a predetermined chip yield rate within a space of performance indices plotted by parameters that are random variables of a model function for calculating a performance index of an simulation model based on the condition sets, simulation model information representing the simulation model, and the chip yield rate; and determining a worst-case corner candidate that minimizes number of worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners used in simulating an operation of the simulation model under the condition sets.