Patent ID: 6707706
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A semiconductor memory device comprising:a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate, said columnar portions being isolated by a plurality of trenches having first and second bottoms which are different in depth; a plurality of cell transistors including first diffusion layer regions formed in said first bottoms shallower than said second bottoms, second diffusion layer regions formed in surface portions of said columnar portions, and a plurality of gate electrodes which are adjacent to said first and second diffusion layer regions and extending along one side-surface portions of said columnar portions; a plurality of word lines connected to said gate electrodes, respectively; a plurality of bit lines extending in a direction intersecting with said word lines and connected to said first diffusion layer regions, respectively; and a plurality of cell capacitors connected to said second diffusion layer regions, respectively.