Patent ID: 7363566
Filing Date: 2008-04-22
Classification: G01R,G11C

Abstract:
1. A pattern generator that generates a test pattern for testing an electronic device using test data previously supplied, comprising: a cache memory comprised of: a main memory operable to store a plurality of test data blocks of which each block is the test data of the magnitude capable of being stored on said cache memory, wherein the test data block is comprised of pattern data blocks and sequence data blocks; an instruction memory operable to store instruction information showing sequence in which the plurality of test data blocks should be stored on said cache memory, wherein the pattern generator sequentially outputs the test data blocks stored on said cache memory as the test pattern; and a memory control unit operable to read the test data blocks to be secondly stored on the pattern cache memory from the main memory while the pattern generating unit is developing one test data block, and to sequentially store the test data blocks on the cache memory with respect to vacant areas in the cache memory.