Patent ID: 7543260
Filing Date: 2009-06-02
Classification: G06F

Abstract:
1. A design supporting system of a semiconductor integrated circuit, comprising: a unit that converts a defective circuit pattern into computer detectable information when a layout of chip of the semiconductor integrated circuit is determined, and corrects the defective circuit pattern of the layout of the chip based on the computer detectable information; a layout designing unit that decides the layout of the chip by defining a plurality of areas in the chip and automatically placing/routing wirings and vias; a data storing equipment that stores the computer detectable information of the defective circuit pattern; a manufacturability analyzing unit that reads the computer detectable information of the defective circuit pattern, verifies the computer detectable information of the defective circuit pattern and the layout of the chip decided by the layout designing unit, and analyzes a manufacturability of the layout of the chip, wherein the computer detectable information of the defective circuit pattern and the layout of the chip decided by the layout designing unit can be verified, and the manufacturability analyzing unit analyzes the manufacturability of the layout of the chip based on an occurring frequency of the defective circuit pattern which is calculated in each area of the plurality of areas in the chip.