Patent ID: 6488570
Filing Date: 2002-12-03
Classification: B24B,B24D,G11B,H01L

Abstract:
A method of polishing a semiconductor substrate, comprising:introducing a polishing fluid having 0-2 weight percent particulate matter into an interface between a polishing pad and the substrate; the polishing pad having a self-dressing polishing layer comprising a high modulus phase component and a low modulus phase component; the low modulus phase component having a critical surface tension greater than or equal to 34 milliNewtons per meter and a modulus less than about 10 Gpa, the high modulus phase component having a modulus greater than that of the low modulus phase component; and providing the polishing layer with at least one flow channel having a depth, whereby as the surface texture wears to one half the depth of a deepest said flow channel, the amount of surface area capable of contacting the substrate changes by less than 20%.