Patent ID: 6326292
Filing Date: 2001-12-04
Classification: H01L,Y10S

Abstract:
A method of achieving a low resistance connection to a buried conductive layer in or below a device layer forming part of a semiconductor component, said method comprising the following steps:etching at least one trench in the device layer, delimiting the area of an active component;applying a layer of a material in which a dopant diffuses faster than in the substance in which the buried conductive layer is located, on the walls of the trench;doping an area of said active component in direct contact with the layer on the walls of the trench, to form a contact; andannealing the component until the dopant has diffused through the layer applied to the walls of the trench to the buried conductive layer, such that at least one portion of said layer on the wall of said trench is doped, and at least one portion of said layer on the wall of said trench is substantially undoped.