Patent ID: 8228084
Filing Date: 2012-07-24
Classification: G01R,G11C

Abstract:
1. A method for testing an integrated circuit device including a system on a chip, wherein the system on a chip includes a plurality of generic purpose input/output pins, the method comprising: storing test code within the system on a chip, the test code being stored within the system on a chip during production of the integrated circuit device; and during a latter phase of production of the integrated circuit device, performing a self-test on the integrated circuit device, wherein performing the self-test on the integrated circuit device includes wherein performing the self-test on the integrated circuit device comprises providing three distinct voltage levels to the system on a chip, and wherein the three distinct voltage levels include (i) a minimum voltage, (ii) a nominal voltage, and (iii) a maximum voltage, wherein the nominal voltage is within plus or minus five percent of each of the minimum voltage and the maximum voltage.