Patent ID: 6438081
Filing Date: 2002-08-20
Classification: G11B,H03L,H04L

Abstract:
A storage media reading system comprising:a phase detector having first and second input terminals, a binary signal obtained from data recorded on a recording medium and carrying said data being supplied to said first terminal; a voltage controlled oscillator for generating (2m+1) multi-phase clock signals (m being a positive integer) which are changed in oscillation frequency according to an output of said phase detector and which are mutually shifted in phase by an integral multiple of 2&pgr;/(2m+1) and for extracting one of said multi-phase clock signals as a sync clock signal for data reproduction and for supplying part of the sync clock signal to the second input terminal of said phase detector; a variable delay circuit for delaying said binary signal by a controllable delay time to generate a binary delayed signal; and a delay control circuit including first circuits for determining a value of the binary delayed signal from said variable delay circuit in synchronism with said sync clock signal to generate a reproduced data signal and also including a second circuit for comparing a phase of the binary delayed signal from said variable delay circuit with phases of the multi-phase clock signals from said voltage controlled oscillator to generate a delay control signal to be supplied to said variable delay circuit for control of said delay time, said reproduced data signal and said sync clock signal being used to reproduce the data recorded on said recording medium.