Patent ID: 7566962
Filing Date: 2009-07-28
Classification: H01L

Abstract:
1. A semiconductor package structure, comprising: a substrate having a first surface, a second surface opposite to the first surface, and an opening penetrating through the first surface and the second surface, the first surface having a plurality of first electrical contacts and a plurality of second electrical contacts disposed thereon, wherein the second electrical contacts are father away from the opening than the first electrical contacts; an interposer having a third surface and a fourth surface opposite to the third surface, the third surface having a plurality of third electrical contacts and a plurality of fourth electrical contacts disposed thereon, wherein the interposer is stacked on the first surface of the substrate, and covers at least one portion of the opening and the third electrical contacts, thereby defining an accommodation space, and the third electrical contacts are electrically connected to the first electrical contacts; a metal layer formed on the fourth surface of the interposer, a first chip received in the accommodation space and electrically connected to the fourth electrical contacts; and a second chip disposed on the metal layer and electrically connected to the second electrical contacts of the substrate.