Patent ID: 6476429
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A semiconductor device comprising:a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, and disposed on the first semiconductor layer; a third semiconductor layer of a second conductivity type, formed in a surface of the second semiconductor layer on a side reverse to the first semiconductor layer; a fourth semiconductor layer of the first conductivity type formed in a surface of the third semiconductor layer; a gate electrode facing, through a gate insulating film, a surface of the third semiconductor layer between the second and fourth semiconductor layers; a first electrode electrically connected to the fourth semiconductor layer; a second electrode electrically connected to the first semiconductor layer, such that the second semiconductor layer is sandwiched between the first and second electrodes; and a plurality of hetero regions having a dielectric constant higher than that of the second semiconductor layer, and disposed in the second semiconductor layer at positions located between the second electrode and a pn junction between the second and third semiconductor layers, and out of contact with the pn junction.