Patent ID: 6812759
Filing Date: 2004-11-02
Classification: H03K,H03L

Abstract:
A DLL circuit comprising:an output dummy circuit having a prescribed propagation delay; a first delay element for delaying a reference clock in accordance with a control signal and supplying a delayed signal to said output dummy circuit; a phase determination circuit for comparing the phases of said reference clock and a feedback signal that is supplied as output from said output dummy circuit, and based on the result of this comparison, supplying said control signal for altering the delay amount of said first delay element; a second delay element for receiving, one of said reference clock and said feedback signal, as a first signal that serves as a trigger of a phase comparison operation, and for delaying this signal by a prescribed delay amount; and a latch circuit for latching the value of the other of said reference clock and feedback signal as a second signal that does not serve as a trigger of said phase comparison operation in synchronization with the rising edge of the output signal of said second delay element, and for supplying an enable signal for turning on or off the input of said first signal to said phase determination circuit.