Patent ID: 9183053
Filing Date: 2015-11-10
Classification: G06F

Abstract:
1. A method, comprising: creating, by a processing device, a page table (PT) hierarchy associated with a thread to be run on the processing device, wherein the PT hierarchy comprises: utilizing, by the processing device, the PT hierarchy associated with the thread to identify locations of memory pages to access during execution of the thread by the processing device; setting the respective access bits of the memory pages accessed by the thread while the thread is executing on the processing device; collecting access bit information from the PT hierarchy associated with the thread, wherein the access bit information comprises the set access bits in the PT hierarchy; determining, in view of the collected access bit information, memory access statistics for the thread; and utilizing, by the processing device during runtime of the thread, the memory access statistics for the thread in a determination of whether to migrate the thread to another processing device during the runtime of the thread.