Patent ID: 7432145
Filing Date: 2008-10-07
Classification: H01L

Abstract:
1. A method for manufacturing a power semiconductor device comprising forming a two-dimensional array of individual cells from a first surface of a semiconductor substrate, each individual cell having source regions within a single and substantially uniformly doped base region surrounding said source regions of the individual cells of said array, and forming a patterned insulated gate region at said first surface, wherein the source regions of the individual cells of the array comprise a plurality of source region branches each extending towards at least one source region branch of an adjacent cell, the source region branches of adjacent cells presenting juxtaposed ends, wherein forming said single and substantially uniformly doped base region comprises the steps of: using said patterned insulated gate region in forming a plurality of base region branches extending radially towards at least one base region branch of an adjacent cell to present juxtaposed base region ends, subsequently merging together the base region branches of adjacent cells adjacent and between said juxtaposed base region ends to form said single and substantially uniformly doped base region.