Patent ID: 9100034
Filing Date: 2015-08-04
Classification: H03M

Abstract:
1. A semiconductor integrated circuit device comprising: an A/D conversion unit; a digital correction unit operable to output an A/D conversion result by performing digital correcting to a digital output received from the A/D conversion unit; and a holding unit operable to hold a test signal to the A/D conversion unit, wherein the A/D conversion unit is of a charge sharing type and operable to perform successive approximation, wherein, at the time of a test, a test signal with the same analog value from the holding unit is inputted into the A/D conversion unit in a first period and a second period different from the first period, a first dither signal is inputted into the A/D conversion unit in the first period, and an A/D conversion correction coefficient is determined, on the basis of a first digital correction result in the digital correction unit to a first digital output from the A/D conversion unit in the first period and a second digital correction result in the digital correction unit to a second digital output from the A/D conversion unit in the second period, and wherein, at the time of a normal operation, the digital correcting is performed with the use of the A/D conversion correction coefficient determined at the time of the test.