Patent ID: 7312504
Filing Date: 2007-12-25
Classification: H01L

Abstract:
1. A transistor for a memory device comprising: an active region protruding upwardly from and between two horizontal surfaces of a predetermined region of a semiconductor substrate, that remain after the semiconductor substrate is etched to form the upwardly protruding active region, the two horizontal surfaces being formed by selectively etching away semiconductor substrate material on at least two opposing sides of the active region to form a single, upwardly protruding semiconductor material structure, which extends above and between said two horizontal surfaces of semiconductor material, the upwardly protruding active region having an upper surface; a field oxide layer formed on the two horizontal surfaces of semiconductor substrate, that remain after being etched away to define the active region in such a manner that the field oxide layers on each of the horizontal surfaces is not on the upper surface of the active region but have an upper surface lower than the upper surface of the active region; a gate insulation layer, formed over the upper surface of the upwardly protruding active layer and filling a groove having a depth and that is formed across the upper surface of the upwardly protruding active region's upper surface, the groove being formed after the step of etching the semiconductor substrate; and a pair of gates formed from material deposited over the field oxide layer on each side of the active region and over the gate insulation layer filling the groove, the pair of gates being spaced apart and separated from each other across the upper surface of the active region while overlapping the active region.