Patent ID: 8421204
Filing Date: 2013-04-16
Classification: H01L,H05K

Abstract:
1. A semiconductor die package comprising: a first module comprising a package with at least one semiconductor device, said module having a first major surface, a second major surface, a plurality of first interconnect lands disposed at its first major surface, a plurality of second interconnect lands disposed at its second major surface, a first semiconductor die disposed between the first and second major surfaces, a first layer of electrically insulating material disposed between the first and second major surfaces and around the first semiconductor die, a second layer of electrically insulating material disposed between the first layer and the first major surface and over the first semiconductor die, a plurality of first electrically-conductive vias disposed through the second layer of electrically insulating material and electrically coupled to a plurality of conductive regions of the first semiconductor die, and a plurality of second electrically-conductive vias disposed through the first and second layers of electrically insulating material and electrically coupled to at least some of the second interconnect lands, wherein at least one first electrically-conductive via is electrically and conductively coupled to at least one second electrically conductive via, and wherein at least one second electrically-conductive via is electrically and conductively coupled to at least one first interconnect land; and a second module comprising a package with at least one electrical component, said second module, having a first major surface, a second major surface, a first electrical component disposed between the first and second major surfaces of the second module, a third layer of electrically insulating material disposed between the first and second major surfaces of the second module and around the first electrical component, wherein the second module is disposed over the first module with its first major surface facing the first major surface of the first module, and wherein the first electrical component is electrically coupled to the first semiconductor die by way of at least one of the first interconnect lands of the first module.