Patent ID: 6102962
Filing Date: 2000-08-15
Classification: G01R,G06F

Abstract:
A method for estimating quiescent currents in an integrated circuit having a layout structure represented by a layout database, comprising the steps of:extracting polysilicon layer data representing a polysilicon area, from the layout database, for a selected transistor of the integrated circuit;extracting active region data representing an active region area, from the layout database, for the selected transistor of the integrated circuit;determining the approximate length of the extracted polysilicon layer data and/or determining if the extracted polysilicon layer data corresponds to a minimum length allowed by applicable design rules;determining if the polysilicon area overlaps the active region area, comprising an overlapping area and, if so;storing a width dimension or a close approximation thereof for the overlapping area; andmultiplying the stored width dimension by a predetermined value related to unit width to generate an estimated quiescent current value for the selected transistor.