Patent ID: 8119470
Filing Date: 2012-02-21
Classification: H01L,Y02P

Abstract:
1. A method of manufacturing an integrated circuit, comprising: forming a gate stack over a semiconductor substrate, the gate stack including a gate electrode formed over a gate dielectric; forming offset spacers on sidewalls of the gate stack; after forming the offset spacers, forming source/drain extension regions in a first implantation into portions of the substrate that are not covered by the gate stack or the offset spacers; forming a layer of oxide material over the top of the gate stack, over and in contact with the offset spacers over the sidewalls of the gate stack, and over the not covered portions of the substrate; after forming the layer of oxide material, conducting a first anneal to activate dopants that were implanted during the first implantation; forming a first layer of nitride material over the layer of oxide material including over the top of the gate stack, over the offset spacers, and over the not covered portions of the substrate; etching the first layer of nitride material in a first etch to remove the first layer of nitride material from over the top of the gate stack and anisotropically from over the not covered portions of the substrate, leaving portions of the first layer of nitride material remaining over the offset spacers; following the first etch, etching the layer of oxide material in a second etch to remove parts of the layer of oxide material from over the top of the gate stack and anisotropically from over the not covered portions of the substrate, leaving portions of the layer of oxide material remaining over the offset spacers, wherein the portions of the first layer of nitride material left remaining after the first etch protect the portions of the layer of oxide material over the offset spacers during the second etch; following the second etch, forming a second layer of nitride material over the gate stack, over the portions of the layer of oxide material left remaining over the offset spacers, and over the not covered portions of the substrate; forming a layer of dielectric material over the second layer of nitride material; and forming conductive contacts in contact abutment with the portions of the layer of oxide material left remaining over the offset spacers, through the layer of dielectric material and down to source/drain regions formed in the substrate; wherein forming the conductive contacts comprises forming via openings through the layer of dielectric material; wherein forming the via openings removes portions of the second layer of nitride material over the portions of the layer of oxide material left remaining over the offset spacers; and wherein the first etch uses a first etchant; wherein the layer of oxide material is formed to a first thickness; wherein the first layer of nitride material is formed to a second thickness; and wherein the second thickness is related to the first thickness and to a selectivity of the first etchant, so that the second etch concurrently etches away substantially all of the portions of the first layer of nitride material left remaining after the first etch.