Patent ID: 7777557
Filing Date: 2010-08-17
Classification: G11C,H02M

Abstract:
1. A booster circuit comprising: boosting cells each having a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element in either or both of the first well region and the second well region, wherein the at least one switching clement switches to transfer charges from a first terminal to a second terminal; a first boosting cell row including N stages (N≧1) of the boosting cells; a second boosting cell row including M stages (M≧1) of the boosting cells; and at least one analog comparison circuit for outputting a well bias potential generated by an output potential of the boosting cell on the i-th stage (1≦i≦N) of the first boosting cell row and an output potential of the boosting cell on the i-th stage (1≧i≧M) of the second boosting cell row, wherein the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element included in the at least one boosting cell of the first and second boosting cell rows.