Patent ID: 7265042
Filing Date: 2007-09-04
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming a plurality of gate structures over a semiconductor substrate; forming a first insulation layer over the gate structures and the substrate; forming a second insulation layer over the first insulation layer; forming a third insulation layer over the second insulation layer; etching a portion of the third insulation layer using a first etch process without exposing the second insulation layer provided below the third insulation layer, the first etch process using a first pressure level and a first gas flow amount; and etching the first, second, and third insulation layers using a second etch process until the semiconductor substrate is exposed and the first, second, third insulation layers define a plurality of gate spacers, the second etch process using a second pressure level and a second gas flow amount, wherein the second pressure level is no more than 100 mtorr to increase an etch selectivity of the first insulation layer with respect to the semiconductor substrate, so that the etching of the semiconductor substrate is minimized.