Patent ID: 7638880
Filing Date: 2009-12-29
Classification: H01L

Abstract:
1. A chip package, comprising: a carrier having an opening; a first chip disposed on the carrier, wherein the first chip has a first active surface and a first rear surface opposite to the first active surface; a plurality of bumps disposed between the carrier and the first active surface of the first chip, wherein the first chip is electrically connected with the carrier and through the bumps; a second chip disposed on the carrier, wherein the first chip and the second chip are located at two opposite side of the carrier; a plurality of bonding wires electrically connected with the carrier and the second chip, wherein each of the bonding wires passes through the opening of the carrier; and a first adhesive layer adhered between the first active surface of the first chip and the carrier, wherein the first adhesive layer comprises: a molding compound disposed on the carrier to cover the first chip, the second chip, the bumps, the first adhesive layer and the bonding wires; a second adhesive layer adhered between the second active surface of the second chip and the carrier, wherein the second adhesive layer comprises: