Patent ID: 7120155
Filing Date: 2006-10-10
Classification: H04J,H04L

Abstract:
1. A network of switches comprising: a first switch having a first memory interface and a first expansion port; a first memory coupled to the first switch with a first memory bus; an expansion bus having a first expansion bus interface and a second expansion bus interface, said first expansion bus interface connected to said first expansion port; a second switch having a second memory interface and a second expansion port, said second expansion port connected to said second expansion bus interface, thereby connecting said first switch to said second switch; and a second memory coupled to the second switch with a second memory bus, wherein said expansion bus allows said first switch to directly access said second memory interface through said second switch and said second switch to directly access said first memory interface through said first switch to increase a bandwidth of a read/write operation to the first memory and the second memory, wherein said first expansion port further comprises a first proxy component that when activated allows data packets to be directly read from said first memory and directly written to said first memory by said second switch through said expansion bus, and wherein said second expansion port further comprises a second proxy component that when activated allows data packets to be directly read from said second memory and directly written to said second memory by said first switch through said expansion bus.