Patent ID: 6825529
Filing Date: 2004-11-30
Classification: H01L

Abstract:
A spacer structure for devices formed in a substrate, the devices including devices of a first conductivity type and devices of a second conductivity type, the devices each having a channel for conducting charge in a longitudinal direction and each having a gate terminal adjacent the channel, the structure comprising:a first spacer structure for a first one of the devices of the first conductivity type, the first spacer structure comprising a first stress inducing material adjacent to both a sidewall of the first one of the device's gate terminal and its channel which applies a first type of mechanical stress on the first one of the devices at least in the longitudinal direction, the first type of mechanical stress being one of tensile stress and compressive stress; and a second spacer structure for a second one of the devices of the second conductivity type, the second spacer structure comprising a second stress inducing material adjacent to both a sidewall of the second one of the device's gate terminal and its channel which applies a second type of mechanical stress, different from the first type of mechanical stress, on the second one of the devices at least in the longitudinal direction, the second type of mechanical stress being the other of tensile stress and compressive stress, wherein the first one of the devices is an NFET and the second one of the devices is a PFET, and the first stress inducing material is a tensile deposited nitride and the second stress inducing material is a compressive deposited nitride.