Patent ID: 8069325
Filing Date: 2011-11-29
Classification: G06F

Abstract:
1. A memory region protection unit comprising: a first register for storing a memory region bound address; a second register for storing a memory region size; an arithmetic function block for executing an arithmetic function on a memory address provided to the region protection unit and the address value in the first register; a comparator for comparing the output of the arithmetic function block with the size value in the second register, the comparator being coupled to an output for signalling the validity of the provided memory address; and a controller being configured to: store the memory region bound address in the first register and the memory region size in the second register in response to one or more instructions issued to the region protection unit for associating the region protection unit with said region; and dissociate the region protection unit from said region in response to a further instruction issued to the region protection unit.