Patent ID: 8856370
Filing Date: 2014-10-07
Classification: H04L

Abstract:
1. A hierarchical network of processing its comprising: a plurality of sub-network comprising at least a first sub-network and a second sub-network, wherein each sub-network within the plurality of sub-networks comprises at least one processing unit and wherein each sub-network within the plurality of sub-networks is connected to the hierarchical network via a gateway controller; a data stream controller directly coupled to each sub-network within the plurality of sub-networks and adapted to transmit data directly to processing units and gateway controllers within the plurality of sub-networks; and a diagnostic port directly coupled to the data stream controller, wherein the data stream controller is adapted to perform a diagnostic operation on at least a first gateway controller and processing unit within a first sub-network within the plurality of sub-networks and at least a second gateway controller and processing unit within a second sub-network within the plurality of sub-networks; wherein the diagnostic operation is a firmware flashing operation and wherein the data stream controller is adapted to flash the first gateway controller and processing unit within the first sub-network during a first time interval and the second gateway controller and processing unit within the second sub-network during a second time interval such that the data stream controller flashes the first gateway controller and processing unit within the first sub-network and the second gateway controller and processing unit within the second sub-network simultaneously during a time period that the first time interval and the second time interval overlap.