Patent ID: 8483004
Filing Date: 2013-07-09
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a plurality of memory transistors each storing data by a change in a level of a threshold voltage; a P-type transistor provided corresponding to each of the memory transistors, and having a source receiving a first voltage and a drain coupled to a gate of the corresponding memory transistor; an N-type transistor provided corresponding to each of the memory transistors, and having a drain coupled to the gate of the corresponding memory transistor and a source receiving a second voltage, which is lower than the first voltage; and a voltage control circuit rewriting data of a selected memory transistor of the memory transistors by applying a third voltage, which is a voltage between the first voltage and the second voltage, to the gate of one of the P-type transistor and the N-type transistor corresponding to each of the memory transistors and further applying the first or second voltage to the gate of the other transistor, wherein: the voltage control circuit, in rewriting data of the selected memory transistor, applies the first voltage to the gate of the P-type transistor corresponding to the selected memory transistor to turn off this P-type transistor, and applies the third voltage to the gate of the N-type transistor corresponding to the selected memory transistor to turn on this N-type transistor; and applies the third voltage to the gate of the P-type transistor corresponding to a non-selected memory transistor other than the selected memory transistor to turn on this P-type transistor, and applies the second voltage to the gate of the N-type transistor corresponding to the non-selected memory transistor to turn off this N-type transistor.