Patent ID: 7510959
Filing Date: 2009-03-31
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device having a damascene structure with air gaps, comprising: depositing and patterning a disposable layer; depositing a first barrier layer on the patterned disposable layer; depositing a metal layer on the first barrier layer and between the patterned portions of the disposable layer; planarizing the metal layer; depositing a second barrier layer on the planarized metal layer and the patterned portions of the disposable layer; planarizing the second barrier layer until substantially no barrier layer is present on top of the patterned portions of the disposable layer; depositing a permeable dielectric layer on the planarized second barrier layer and the patterned portions of the disposable layer; and removing the patterned portions of the disposable layer through the permeable dielectric layer so as to form air gaps, wherein the removing comprises heating the disposable layer so that the patterned portions decompose and diffuse through the permeable dielectric layer, and wherein a single CVD reactor is used for depositing the permeable dielectric layer and for removing of the patterned portions of the disposable layer by heating in order to decompose the disposable layer.