Patent ID: 6411631
Filing Date: 2002-06-25
Classification: H04L,Y10S

Abstract:
A multiplex type signal transmission apparatus, comprising:a plurality of slow signal receiving/transmitting sections for receiving and transmitting a slow signal; a multiplex separation converting section; and a fast signal receiving/transmitting section at a receiving side for receiving and transmitting a fast signal, wherein each of said plurality of slow signal receiving/transmitting sections includes: a receiving processing section for receiving said slow signal from a transmission path, an internal SS bit setting unit selected from one of: a first internal SS bit with respect to each SS bit set A of a plurality of H1 bytes existing in a same frame of the received slow signal, for setting, in case that the SS bit B received at first time are value of A10â€³or A00â€³, the internal SS bits to said value, and otherwise the internal SS bits hold a previous state, a second internal SS bit setting unit, with respect to each SS bit set C having value of A10â€³or A00â€³among said SS bit set A, for comparing the number of M of the SS bits having value of A10â€³with the number L of the SS bits having value of A00â€³, and for setting, in case that said M is larger than said L, the internal SS bits to A10â€³, in case that said M is smaller than said L, the internal SS bits to A00â€³, and in case that M is equal to said L or there is no elements of the SS bits set C, the internal SS bits hold a previous state, and a third internal SS bit setting unit, with respect to each SS bit set D not included in concatenation indicator and having value of A10â€³or A00â€³among said SS bit set A, for comparing the number of N of the SS bits having value of A10â€³with the number K of the SS bits having value of A00â€³, and for setting, in case that said N is larger than said K, the internal SS bits to A10â€³, in case that said N is smaller than said K, the internal SS bits to A00â€³, and in case that said Ni is equal to said K or there is no elements of the SS bits set D, the internal SS bits hold a previous state, and a transmission processing unit on a transmitting side for transmitting the slow signal onto said transmission path as keeping the plurality of SS bits of the signal from said multiplex separation converting section identical with the internal SS bits set by said internal SS bits setting section, wherein said fast signal receiving/transmitting section includes: a receive processing section for receiving said fast signal from a transmission path, an internal SS bits setting unit selected from one of: a fourth internal SS bit set E of a plurality of H1 bytes existing in a same frame of the received fast signal, for setting in case that the SS bits set F received at first time are value of A10â€³or A00â€³, the internal SS bits to said value, and otherwise the internal SS bits hold a previous state, a fifth internal SS bits setting unit, with respect to each SS bit set G having value of A10â€³or A00â€³among said SS bit set E, for comparing the number of P of the SS bits having value of A10â€³with the number Q of the SS bits having value of A00â€³, and for setting, in case that said P is larger than said Q, the internal SS bits to A10â€³, in case that said P is smaller than said Q, the internal SS bits to A00â€³, and in case that said P is equal to said Q or there is no elements of the SS bits set G, the internal SS bits hold a previous state, and a sixth internal SS bits setting unit, with respect to each SS bits set H not included in concatenation indicator and having value of A10â€³or A00â€³among said SS bit set E, for comparing the number of R of the SS bits having value of A10â€³with the number S of the SS bits having value of A00â€³, and for setting, in case that said R is larger than said S, the internal SS bits to A10â€³, in case that said R is smaller than said S, the internal SS bits to A00â€³, and in case that said R is equal to said S or there is no elements of the SS bits set H, the internal SS bits hold a previous state, and a transmission processing unit on a transmitting side for transmitting the fast signal onto said transmission path as keeping the plurality of SS bits of the signal from said multiplex separation converting section identical with the internal SS bits set by said internal SS bits setting section.