Patent ID: 6687844
Filing Date: 2004-02-03
Classification: G06F

Abstract:
A method of correcting clock duty cycle skew, comprising:generating a clock signal having clock cycles; delaying the clock signal by a clock cycle to generate a delayed clock signal; measuring the time interval between a phase 1 clock cycle and a phase 2 clock cycle in the clock signal and storing it as a first time period; measuring the time interval between the phase 2 clock cycle and a second phase 1 clock cycle in the clock signal and storing it as a second time period; determining when a delayed phase 2 clock cycle of the delayed clock cycle is high; subtracting the first time interval from the second time interval to yield a third time interval; and adjusting the start of the delayed phase 2 clock cycle by half of the third time interval so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.