Patent ID: 6542103
Filing Date: 2003-04-01
Classification: G11B,H03M

Abstract:
An arrangement for generating an error signal representing the difference between an input signal voltage level at a sampling instant and an estimated value for the input signal voltage level, the arrangement comprising first and second transconductors, means for feeding the input signal to an input of the first transconductor, means for feeding the estimated value to an input of the second transconductor, a differencing circuit for forming the modulus of the difference between the outputs of the first and second transconductors, the output of the differencing circuit providing the error signal, and a current subtractor for forming a probability signal, the probability signal representing the probability that the input signal is a signal of the estimated value, a reference current source being coupled to a first input of the subtractor and the error signal being coupled to a second input of the subtractor, the output of the subtractor providing the probability signal.