Patent ID: 8250659
Filing Date: 2012-08-21
Classification: G06F,H03M

Abstract:
1. An apparatus for protecting the integrity of data, comprising: a redundancy generator configured to form a data bit vector from a plurality of data words of a data block, and to generate a control bit vector by multiplying the data bit vector by a binary generator matrix consisting of square, circulant sub-matrices; an encryptor/decryptor configured to encrypt each of the data words to obtain encrypted data words, and to encrypt the control bit vector to obtain an encrypted control bit vector, and to decrypt each of the encrypted data words to obtain decrypted data words, and to decrypt the encrypted control bit vector to obtain a decrypted control bit vector; and a controller configured to form an overall bit vector from the decrypted data words or from the decrypted data words and the decrypted control bit vector, and to create a syndrome bit vector by multiplying a binary control matrix consisting of square, circulant sub-matrices by the overall bit vector, so that the integrity of the overall bit vector is verifiable using the syndrome bit vector, which additionally comprises a syndrome bit vector monitor configured to count zeros of the syndrome bit vector to trigger an alarm action when a number of zeros is higher than a predetermined threshold, wherein at least one of the redundancy generator, the encryptor/decryptor and the controller comprises a hardware implementation.