Patent ID: 6252788
Filing Date: 2001-06-26
Classification: G11C

Abstract:
A method of controlling a semiconductor memory device coupled to a bus to which first and second memory masters are further coupled, said semiconductor memory device comprising, on a single semiconductor chip, a main memory unit and a sub memory unit, said sub memory unit having a plurality of memory portions, said method comprising:operating said main memory unit as a main memory for storing data;operating each of said memory portions as a cache memory unit such that each of said memory portions copies an associated part of said data;allocating at least one of said memory portions for said first memory master as a cache memory unit for said first memory master, and at least one of the remaining ones of said memory portions for said second memory master as a cache memory for said second memory master; andin response to a request, changing in at least one of location and number of the memory portion to be allocated for one of said first and second memory masters.