Patent ID: 8129774
Filing Date: 2012-03-06
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: memory cell units each including a plurality of memory cells connected in series, a first select transistor and a second select transistor, the plurality of memory cells connected in series being connected between the first select transistor and the second select transistor; a memory cell array including the memory cell units arranged to form an array; control gate lines each including control gates of memory cells connected continuously in a row direction of the memory cell array; a first select gate line including gates of the first select transistors connected continuously in the row direction of the memory cell array; and a second select gate line including gates of the second select transistors connected continuously in the row direction of the memory cell array; wherein a first voltage is supplied to a control gate of a selected memory cell included in a selected memory cell unit, a second voltage is supplied to a control gate of an unselected memory cell included in the selected memory cell unit, a third voltage is supplied to a gate of the first select transistor in the selected memory cell unit, a fourth voltage is supplied to a gate of the second select transistor in the selected memory cell unit, thereby a verify read operation is performed, the first voltage is lower than the second voltage, and the second voltage is higher than any of the third voltage and the fourth voltage.