Patent ID: 7088620
Filing Date: 2006-08-08
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are disposed in a form of a matrix and are divided into a plurality of sectors; a plurality of row decoder circuits, each of which is provided so as to correspond to each sector of the memory cell array for selecting a memory cell included in the corresponding sector based on an externally inputted address signal; a plurality of switches provided so as to correspond to the plurality of row decoder circuits, such that each switch is operable to separately select and output any of a plurality of types of voltages supplied thereto to the corresponding row decoder circuit; a voltage boost circuit for generating the plurality of types of voltages by boosting a power supply voltage; and a regulator circuit for stepping down at least one of the plurality of types of voltages generated by the voltage boost circuit to stabilize a voltage value, and outputting the resultant voltage to each switch, wherein the row decoder circuit selects the memory cell by using a voltage outputted from the corresponding switch.