Patent ID: 6544840
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A manufacturing method for a semiconductor memory device comprising:forming a diffusion layer and gate electrodes on the surface of a semiconductor substrate; forming an interlayer insulation film on the surface of the semiconductor substrate; simultaneously forming capacitive cell grooves and upper electrode contact grooves at the interlayer insulation film; forming electric conductive substances at the bottom surfaces and side surfaces of the capacitive cell grooves and the upper electrode contact grooves to form lower electrodes and a first electric conductive layer, respectively; forming capacitive insulating films at the inner side surfaces and bottom surfaces of the capacitive cell grooves and lower electrodes; forming electric conductive substances within the capacitive cell grooves and upper electrode contact grooves to form upper electrodes and a second electric conductive layer, respectively, and simultaneously forming upper electrode extending parts connecting the upper electrodes and the second electric conductive layer; embedding insulation substances into the upper electrode contact grooves; simultaneously forming upper electrode contact holes and lower electrode contact holes in the insulation substances in the upper electrode contact grooves and interlayer insulation film, respectively, wherein the upper electrode contact holes extend into the upper electrode contact grooves more than one half of the depth of the grooves; and embedding electric conductive substances into the upper electrode contact holes and lower electrode contact holes to form upper electrode contacts and lower electrode contacts.