Patent ID: 8093937
Filing Date: 2012-01-10
Classification: G11C,H03L

Abstract:
1. A method of producing a clock signal, comprising: generating a first plurality of first intermediate clocks and a second plurality of second intermediate clocks by applying a reference clock to a plurality of series coupled delay elements, a first set of the plurality of delay elements alternating with a second set of the plurality of delay elements, each of the delay elements in the first set generating a respective one of the first plurality of first intermediate clocks, and each of the delay elements in the second set generating a respective one of the second plurality of second intermediate clocks, the first and second intermediate clocks generated by adjacent ones of the delay elements having a fixed phase difference therebetween; inputting each of said first and second intermediate clocks to a first level of switches; using the first level of switches to select a third plurality of said first intermediate clocks and a fourth plurality of said second intermediate clocks, the number of first intermediate clocks in said third plurality being less than the number of first intermediate clocks in said first plurality, and the number of second intermediate clocks in said fourth plurality being less than the number of second intermediate clocks in said second plurality, inputting the third plurality of first intermediate clocks and the fourth plurality of second intermediate clocks from said first level of switches to a second level of switches, wherein said second level of switches has fewer switches than said first level of switch; using the second level of switches to select one of the first intermediate clocks in the third plurality and one of the second intermediate clocks in the fourth plurality; and inputting the selected first intermediate clock and the selected second intermediate clock from said second level of switches to a phase mixer, said phase mixer generating an output clock from said selected first and said second intermediate clocks, wherein said output clock has a phase between the phases of said selected first and said second intermediate clocks.