Patent ID: 9087614
Filing Date: 2015-07-21
Classification: G06F,G11C

Abstract:
1. A memory module, comprising: a plurality of memory devices; and a buffer chip configured to manage the plurality of memory devices, the buffer chip including a memory management unit having an error correction unit configured to perform an error correction operation on each of the plurality of memory devices, wherein each of the plurality of memory devices includes at least one spare column accessible by the memory management unit, the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit, and the memory management unit further includes a first fail address table configured to store fail address information corresponding to an address of at least one memory cell row of at least one of the plurality of memory devices, the at least one memory cell row including at least one defective cell.