Patent ID: 8989331
Filing Date: 2015-03-24
Classification: G06F,H04L

Abstract:
1. A method for transferring data from one clock domain within an advanced high performance bus synchronizer to another domain within the synchronizer while preserving burst operations, comprising: determining system clock parameters within the synchronizer; analyzing a first clock signal associated with a first clock domain based upon the system clock parameters; analyzing a second clock signal associated with a second clock domain based upon the first clock signal and the system clock parameters; switching an operational mode of the synchronizer based on a ratio of frequencies of the first and second clock signals, wherein the switching of the operational mode includes switching between a latency mode, a bandwidth mode, and a bypass mode, the bypass mode including bypassing a transfer of data between the first clock domain and the second clock domain and bypassing a transfer of data between the second clock domain and the first clock domain; and providing a second clock domain enable signal to enable a rising edge of the second clock signal to transfer data between the first clock domain and the second clock domain and a first clock domain enable signal to enable a rising edge of the first clock signal to transfer data between the second clock domain and the first clock domain.