Patent ID: 6400181
Filing Date: 2002-06-04
Classification: H03K

Abstract:
A circuit arrangement for transmitting signals from an output of a first circuit to an input of a second circuit, where the first circuit has a first operating voltage and a first ground potential applied thereto, and the second circuit has a second operating voltage and a second ground potential applied thereto, and where variable potential differences arise between the ground potentials, wherein the output of the first circuit is provided with a controllable current source (9, 13; 9â€², 13â€²) outputting a first controllable current which flows towards a circuit point having a further potential applied thereto, the arrangement including a further current source connected to the circuit point, the first controllable current controlling the further current source (12, 15; 12â€², 15â€²) and flowing toward the input of the second circuit, and wherein the further potential is selected for enabling operation of the first controllable current source and operation of the further current source, the further potential providing a first voltage between the output of the first circuit and the circuit point, and providing a second voltage between the circuit point and the input of the second circuit for the potential differences which arise,wherein said further potential (GND3) is lower than the first operating voltage by at least the sum of emitter/collector voltage of a first transistor (9) of the controllable current source and a base/emitter voltage of a second transistor (12) of the further current source, an emitter of the first transistor having the first operating voltage applied thereto, and wherein said further potential is lower than the second operating voltage by at least the sum of the collector/emitter voltage of the second transistor (12) and a base/emitter voltage of a third transistor (16) in the input of the second circuit, wherein a collector terminal of the first transistor is connected to a base terminal of the second transistor, and the collector terminal of the second transistor is connected to a base terminal of the third transistor.