Patent ID: 8130543
Filing Date: 2012-03-06
Classification: G11C

Abstract:
1. A memory apparatus, comprising: a memory array having rows and columns of cells; a data buffer adapted to receive a plurality of data values to be programmed into cells in a selected row of the array, wherein each of the plurality of data values corresponds to one of a plurality of programming levels; an address decoder connected to receive an address, which corresponds to the selected row and to a plurality of columns in the row and enables cells in the plurality of columns in the selected row for programming; a first plurality of sense amplifiers and corresponding drivers adapted to receive the plurality of data values from the data buffer and to program selected memory cells in the array according to the plurality of data values; and column control circuitry connected and configured to receive the plurality of data values from the data buffer and to select a second plurality of the first plurality of sense amplifiers and corresponding drivers according to data values corresponding to one of the plurality of programming levels, the second plurality comprising no more than a specified number of sense amplifiers and corresponding drivers, the column control circuitry further being configured to program memory cells in the selected row and plurality of columns using the second plurality of sense amplifiers and corresponding drivers according to the one of the plurality of programming levels.