Patent ID: 6963115
Filing Date: 2005-11-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first discontinuous active region in which only a gate of a pMISFET is placed; a first continuous active region in which gates of three or more respective pMISFETs are arranged; and a trench isolation surrounding the first discontinuous active region and the first continuous active region, wherein gates of pMISFETs of a first type are arranged in the first continuous active region, whereas a gate of a pMISFET of a second type, which needs higher current driving capability than the pMISFETs of the first type, is placed in the first discontinuous active region, and a stress applied from the trench isolation to a channel of the pMISFET of the second type is larger than a stress applied to a channel of the pMISFET of the first type.