Patent ID: 6658520
Filing Date: 2003-12-02
Classification: G06F

Abstract:
A method for keeping two independent busses coherent comprising:writing data from an Input/Output (I/O) controller to a memory, the I/O controller sending the data to the memory via a first bus connected to a first port of a memory controller and the I/O controller; sending a tag, from the I/O controller, after the data via the first bus through the first port, the tag being received by the memory controller; requesting completion status of the data write from the I/O controller by a processing unit, the request being sent to the I/O controller via a second bus connected to a second port of the memory controller and the I/O controller; waiting for a tag acknowledgment, by the I/O controller, from the memory controller before providing notification to the processing unit that the data write has completed; writing the data to the memory from one of at least one Direct Memory Access (DMA) controller at the I/O controller; sending the data from the one of at least one DMA controller to a second memory at the I/O controller and then the writing the data to memory; sending the data, by the I/O controller, from the second memory via the first bus to a third memory at the memory controller and then the writing the data to memory; and sending the tag acknowledge from the memory controller to the one of at least one DMA controller via the third memory, first bus, and second memory, wherein the first bus and the second bus are coherent.