Patent ID: 6175497
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A thermal vias-provided cavity-down IC package structure, used to package a chip, comprising:a substrate consisting essentially of multiple layers of printed circuit boards which have a cavity at the center thereof, a plurality of metal layers between neighboring printed circuit boards, a plurality of plated-through-holes for electrically interconnecting the metal layers, a plurality of thermal vias in addition to the plated-through-holes for electrically interconnecting the metal layers in the surrounding thereof, and a plurality of bonding pads on the edges thereof for electrically connecting the chip;a heat sink having a chip mount area and a thermal via joint area, wherein the chip mount area is used to carry a chip mount pad by which the chip is connected to the heat sink, and the thermal via joint area comprises a plurality of island-shaped protrusions attached to the thermal vias which penetrate through the substrate to form a short path for heat transfer, the chip mount area and the thermal via joint area including the island-shape protrusions, said island-shape protrusions are formed as a single body with said heat sink; anda prepreg for attaching the heat sink and the substrate to each other.