Patent ID: 6480940
Filing Date: 2002-11-12
Classification: G06F

Abstract:
A multiprocessor system comprising:a plurality of processors each including a cache memory and accessing stored data via said cache memory; a main memory shared among said plurality of processors; a module detecting device possessed by each of said processors for detecting execution of a software module for accessing a shared memory area on said main memory; and an access control device possessed by each of said processors for controlling memory access executed in response to an accessing software module identifier detected by said module detecting device in a cache control protocol in a store-through scheme which updates said main memory simultaneously with update of said cache memory or for controlling memory access in other than said detection case in a cache control protocol in a store-in scheme which does not update said main memory at update of said cache memory, wherein said module detecting device comprises a first virtual space number register and a first instruction segment number register in which virtual space number of software modules in all processes which can access said shared memory area on said main memory and numbers of instruction segments storing instruction codes for said software modules are preset respectively, a second virtual space number register and a second instruction segment number register for respectively holding a virtual space number and a number of an instruction segment storing an instruction code for a software module which attempts to access the stored data via said cache memory, first and second comparators for comparing the virtual space numbers and the numbers of instruction segments stored in said four respective registers, and a logical circuit for detecting whether a match is detected in both said first and second comparators.