Patent ID: 8981974
Filing Date: 2015-03-17
Classification: G04F,H03M

Abstract:
1. A time-to-digital converter comprising: a plurality of first delay elements connected in series; a plurality of second delay elements disposed respectively for the plurality of the first delay elements and connected in series; a plurality of flip-flops configured to store a value of an input signal to a first delay element at a front stage of the plurality of the first delay elements and values of output signals of the plurality of the first delay elements in synchronization with an input signal to a second delay element at the front stage of the plurality of the second delay elements and output signals of the plurality of the second delay elements, respectively; a first switching unit configured to switch a first state for inputting a first clock signal input from a first input terminal, and a second state for inputting an output signal of a second delay element at a last stage of the plurality of the second delay elements, to the first delay element at the front stage; a second switching unit configured to switch a first state for inputting a second clock signal input from a second input terminal, and a second state for inputting an output signal of a first delay element at the last stage of the plurality of the first delay elements, to the second delay element at the front stage; a control unit configured to put the first and second switching units into the second state after the first clock signal and the second clock signal are taken in the plurality of the first delay elements and the plurality of the second delay elements, respectively, by putting the first and second switching units into the first state; and an output unit configured to output information indicating a phase difference between the first clock signal and the second clock signal obtained by decoding values stored in the plurality of the flip-flops in the second state.