Patent ID: 6128669
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A computer system having automatic direct memory access, the computer system comprising:a host bus;a main memory coupled to said host bus for storing at least one pool of packets, each pool comprised of a linked list of packets, each packet having a header including a physical address field for containing a physical address of a next packet to form the linked list;a processor coupled to said host bus;a local bus;a mass storage subsystem coupled to said local bus;a host/local bus bridge coupled between said host bus and said local bus, the bus bridge including a distributed burst engine for communicating packets between said mass storage subsystem and said main memory, the distributed burst engine comprising:a request head register operable to hold the physical address of a next packet of the linked list;a free queue register operable to hold the physical address of the last packet of the linked list;a request queue for holding packets, said request queue operable to provide a fullness indication when a packet is therein;a request doorbell register operable to receive an indication from the processor that a next packet is available to process;a completion head register operable to hold the physical address of a completion list;a completion queue for holding packets;a completion doorbell register operable to receive an indication from the processor that said completion queue has been serviced and that the processor is ready to receive packets;a first front end controller coupled to the request queue and responsive to said request doorbell register, said first front end controller operable to read a packet from the main memory according to the physical address stored in the request head register when said request doorbell register is rung and store the packet in said request queue;a first back end controller coupled to the request queue and the completion queue and responsive to the request queue fullness indication, said first back end controller operable to read a packet from said request queue when said request queue is not empty and provide the packet to the mass storage subsystem, said first back end controller further operable to provide the packet to said completion queue when the mass storage subsystem has completed processing the packet; anda completion controller coupled to said completion queue and responsive to the completion doorbell register and the completion head register, said completion controller operable to complete a packet from the completion queue back to the memory.