Patent ID: 8154050
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: an element formation region formed in a major surface of a semiconductor substrate, the element formation region being surrounded by an element isolation region; a gate electrode formed on a gate insulating film on a part of the element formation region; semiconductor epitaxial layers formed in source/drain regions of the element formation region to sandwich a channel region below the gate electrode, each semiconductor epitaxial layer having a three-layered structure in which first semiconductor films different in material or composition from the semiconductor substrate sandwich a second semiconductor film having a silicidation reactivity higher than that of the first semiconductor films; a first silicide layer formed on the gate electrode and the semiconductor epitaxial layers, the first silicide layer on the semiconductor epitaxial layers extending to and contacting each of the first and second semiconductor films; and a second silicide layer formed to extend from the first silicide layer to the second semiconductor film along a direction of an interface between the semiconductor substrate and the semiconductor epitaxial layers, so as to apply a compression stress to the channel region below the gate electrode by expansion caused by silicidation of the second semiconductor film.