Patent ID: 6281891
Filing Date: 2001-08-28
Classification: G09G

Abstract:
A product comprising:a first substrate with a surface at which circuitry can be formed; andarray circuitry formed at the surface of the first substrate, the array circuitry comprising:a set of N data lines, where N is an integer greater than 32; each of the N data lines extending across the surface of the first substrate; each of the N data lines having a drive input lead in a multiplexer region of the surface of the first substrate; andfor each of the N data lines, M units of cell circuitry, each connected for receiving signals from the data line, where M is an integer greater than zero;multiplexer circuitry formed in the multiplexer region of the surface of the first substrate; the multiplexer circuitry being connected to the drive input lead of each of the N data lines; the multiplexer circuitry comprising:for each of the N data lines, a drive output lead connected for providing multiplexed signals to the data line's drive input lead;P analog input leads for receiving input analog drive signals, where P is an integer less than N but not less than 32; andQ multiplexer control leads for receiving multiplexer control signals, where Q is an integer not less than N/P and less than N;the multiplexer circuitry responding to the input analog drive signals and the multiplexer control signals by providing the multiplexed signals; andone or more integrated circuit structures attached to the first substrate; the integrated circuit structures together comprising:R single crystal substrates, where R is an integer greater than zero; each single crystal substrate having a surface at which circuitry can be formed; andat the surface of each of the R single crystal substrates, digital-to-analog circuitry; the digital-to-analog circuitry on each substrate's surface having digital input leads and at least S analog output leads, where S is an integer not less than 32; the digital-to-analog circuitry providing, on each analog output lead, an analog drive signal with an amplitude that varies with a value indicated by a digital drive signal received from the digital input leads; the R single crystal substrates together having T analog output leads, where T is an integer not less than P; each of the P analog input leads of the multiplexer circuitry being paired with and connected to one of the T analog output leads so that the R single crystal substrates together provide the input analog drive signals.