Patent ID: 6078978
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A high-speed bus interface circuit comprising:a data driver to transmit a data signal through a first transmission line of which one end is terminated;a reference voltage driver to transmit a reference voltage signal through a second transmission line of which one end is terminated; anda receiver to determine a logic state by comparing the data signal transmitted by the first transmission line with the reference voltage signal transmitted by the second transmission line,wherein the levels of the data signal and the reference voltage signal maintain a termination voltage level Vtt at a stand-by state,wherein the level of the reference voltage signal becomes Vtt-.DELTA.Vr when the reference voltage driver is driven,wherein when the data signal is logic 0 the data driver is turned off so that the level of the data signal becomes the termination voltage level Vtt and when the data signal is logic 1 the data driver is turned on so that the level of the data signal becomes Vtt-.DELTA.VD, andwherein .vertline..DELTA.VD.vertline.>.vertline..DELTA.Vr.vertline..