Patent ID: 7514737
Filing Date: 2009-04-07
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor memory device, comprising: a word line; a bit line extending in a direction orthogonal to an extending direction of said word line; and a memory cell longer in the extending direction of said word line than in an extending direction of said bit line; said memory cell including a first well region of a first conductivity type, a second well region of a second conductivity type and a third well region of the first conductivity type arranged side by side in the extending direction of said word line, a first driver MOS transistor and a first access MOS transistor formed on said first well region, first and second load MOS transistors formed on said second well region, a second driver MOS transistor and a second access MOS transistor formed on said third well region, a first local interconnection formed in an interlayer insulating film covering said first and second driver MOS transistors, said first and second access MOS transistors and said first and second load MOS transistors, and connecting active regions of said first driver MOS transistor, said first access MOS transistor and said first load MOS transistor with gate electrodes of said second driver MOS transistor and said second load MOS transistor, a second local interconnection formed in said interlayer insulating film, and connecting active regions of said second driver MOS transistor, said second access MOS transistor and said second load MOS transistor with gate electrodes of said first driver MOS transistor and said first load MOS transistor, a first lower plate formed in contact with said interlayer insulating film and connected to said first local interconnection, a second lower plate formed on said interlayer insulating film, spaced apart from said first lower plate, and connected to said second local interconnection, and an upper plate formed on said first and second lower plates with a dielectric film interposed therebetween, and forming first and second capacitors together with said first and second lower plates respectively.