Patent ID: 6563740
Filing Date: 2003-05-13
Classification: G11C

Abstract:
An electronic circuit for monitoring and refreshing non-volatile memory, comprising:a non-volatile memory in an integrated circuit including a first plurality of non-volatile memory cells each having a voltage state and a gate; a gate bias circuit located in the integrated circuit, coupled to the gates of the first plurality of non-volatile memory cells, including a read voltage and a first margin voltage; a monitor circuit located in the integrated circuit and coupled to the first plurality of non-volatile memory cells, including a comparison circuit adapted to determine whether the voltage state of at least one non-volatile memory cell of the first plurality of non-volatile memory cells transitions across a reference voltage between the application of the read voltage and the first margin voltage to the gate of that cell; and a programming circuit located in the integrated circuit, including a programming voltage selectively coupled to the first plurality of non-volatile memory cells, wherein the programming voltage is applied to the non-volatile memory cell of the first plurality of non-volatile memory cells in response to the output signal of the monitor circuit indicating that the voltage state of the non-volatile memory cell transitions across the reference voltage between the application of the read voltage and the first margin voltage to the gate of that cell.