Patent ID: 7983288
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A data transmission line of a semiconductor memory device, the data transmission line comprising: a first repeater receiving first and second data through a first data line and a second data line, respectively, and having first and second output lines; a second repeater receiving third and fourth data through a third data line and a fourth data line, respectively, and having third and fourth output lines; a first latch switch operated when a start address of a column address applied during a read operation is an even address; and a second latch switch operated when the start address of the column address applied during the read operation is an odd address, wherein the first repeater is configured to transfer the first data through selected one of the first and second output lines and the second data through non-selected one of the first and second output lines using a control signal determined according to the start address, and wherein the second repeater is configured to transfer the third data through selected one of the third and fourth output lines and the fourth data through non-selected one of the third and fourth output lines using the control signal determined according to the start address, wherein each of the first to fourth data lines is configured to include at least two portions which are positioned in different planes and the two portions are electrically connected.