Patent ID: 7739572
Filing Date: 2010-06-15
Classification: G11C

Abstract:
1. A tester for testing a device under test (DUT), the tester comprising: a pattern generator for generating a logical test pattern data for a test of the DUT based on a test pattern program; a data selector for converting the logical test pattern data transmitted from the pattern generator into a physical test pattern data and an expected data based on the logical test pattern data; a format controller for converting the physical test pattern data to a test waveform based on a time delay value set for the test; a driver for applying the test waveform to the DUT; an output comparator for receiving an output corresponding to the test waveform from the DUT to output a test output data; and a test comparator for comparing the test output data with the expected data to determine the DUT is a defective DUT; a multiplexer for multiplexing the test waveform to comply with an operating speed of the DUT; a de-multiplexer for de-multiplexing the test output data to comply with an operating speed of the comparison of the test output data with the expected data; a timing controller for carrying out an oversampling of the test waveform prior to applying the test waveform to the multiplexer; and a bit shifter for shifting the test waveform by a unit of a bit to be applied to the multiplexer after carrying out the oversampling.