Patent ID: 7016226
Filing Date: 2006-03-21
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array configured by arranging a plurality of memory cells in a matrix, each of, which is capable of having one of four threshold voltages and storing two bits of data; a plurality of bit lines, each of which is connected to said plurality of memory cells arranged in the column direction; a plurality of word lines, each of which is connected to said plurality of memory cells arranged in the row direction; a first flag cell and a second flag cell which are selected at the same time when the memory cells are selected by each of the word lines; and a control section which, when writing the data in a second page composed of the two bits into the memory cells selected by the word line, writes specific data into the first and second flag cells and which, when reading the data in a first page from the memory cells, determines from the data read from the first flag cell whether the second page has been written into the memory cells and which, when reading the data in the second page from the memory cells, determines from the data read from the second flag cell whether the second page has been written into the memory cells.