Patent ID: 6664150
Filing Date: 2003-12-16
Classification: H01L,Y10S

Abstract:
A non-self-aligned method of fabricating a semiconductor device on a silicon-on-insulator substrate, said method comprising the steps of:forming a silicon-on-insulator (SOI) substrate, said SOI substrate having a patterned top Si-containing layer present atop a buried oxide region which includes areas that are exposed; forming a mask over a portion of said patterned top Si-containing layer; forming regions of porous Si in portions of said patterned top Si-containing layer not protected by said mask; forming a buried interconnect plane in portions of said patterned top Si-containing layer that are located beneath said regions of porous Si; removing the mask and the regions of porous Si from said patterned top Si-containing layer to provide a cavity in said regions previously occupied by porous Si; forming an isolation region within said cavity; and forming a field effect transistor on a portion of said patterned top Si-containing layer, wherein said field effect transistor includes at least diffusion regions formed within said top Si-containing layer above said isolation oxide region, said diffusion regions being separated by a body region.