Patent ID: 7482904
Filing Date: 2009-01-27
Classification: H01F,H03H

Abstract:
1. An on-chip transformer balun comprising: a primary winding as an input terminal of the on-chip transformer balun; and a secondary winding as an output terminal of the on-chip transformer balun, wherein one of the primary winding and secondary winding is seperated into a plurality of metal layers in which a spiral trace portion excluding an underpass is disposed on mutually different layers to have an asymmetrical structure, wherein the plurality of metal layers comprises a first metal layer and a second metal layer; and when the secondary winding is formed of the plurality of metal layers, amplitude imbalance generated between two output terminals of the secondary winding in a high frequency band is improved by controlling parisitic capacitance coupling by using a difference between a physical distance between the primary winding and the first metal layer and a physical distance between the primary winding and the second metal layer.