Patent ID: 6218857
Filing Date: 2001-04-17
Classification: H03K

Abstract:
A field programmable gate array (FPGA) device, comprising:(a) an input/output block (IOB), including:a first sized line driving amplifier for generating a first signal at a first output, and,a second sized line driving amplifier for generating a second signal at a second output, wherein the first sized line driving amplifier has a different size than the second sized line driving amplifier; and(b) an inter-connect network for carrying a plurality of signals, wherein the inter-connect network includes:a first line, coupled to the first JOB output, having a first capacitance,a second line, coupled to the second JOB output, having a second capacitance, anda third sized line driving amplifier for generating a third signal at a third output coupled to a third line in the interconnect network.