Patent ID: 7952436
Filing Date: 2011-05-31
Classification: H03L

Abstract:
1. A phase lock loop (PLL) circuit, comprising: a voltage controlled oscillator (VCO), for generating an output clock signal based on a control voltage; a controller, for providing a first digital control word, a second digital control word and a loop factor; a frequency modifier, coupled to the output clock signal, controlled by the controller to divide the output clock signal by the loop factor to generate a feedback frequency; a phase detector, having a first input end for receiving a reference frequency, and a second end coupled to the feedback frequency, and comparing phases of the reference frequency and the feedback frequency to assert an up signal or a down signal; a charge pump, controlled by the up signal and down signal to generate a charge pump current, comprising: a first digital to analog converter (DAC), operative to generate a first current based on the first digital control word when the up signal is asserted; and a second DAC, operative to generate a second current based on a second digital control word when the down signal is asserted; wherein the first current and the second current are output as the charge pump current; a low pass filter (LPF), coupled to the charge pump current, performing a low pass filtering on the charge pump current to output the control voltage; wherein: the controller defines a first relationship between the first digital control word and the loop factor; and the controller defines a second relationship between the second digital control word and the loop factor, wherein the first relationship and the second relationship are linear non-decreasing functions.