Patent ID: 7602323
Filing Date: 2009-10-13
Classification: H03M

Abstract:
1. A method for estimating and correcting nonlinear error introduced by one or more residue amplifiers in a pipelined analog to digital converter integrated circuit, the method comprising steps of: in one or more stages of the amplifier, introducing pseudo random calibration sequences into the digital signal to be converted by a flash digital to analog converter in the one or more stages; sampling a digital residue signal of the output of the pipelined analog to digital converter prior to the one or more stages; from a sample of the digital residue signal, determining intermodulation products of the pseudo random calibration sequences that are present in the digital residue signal to estimate nonlinear error introduced by the residue amplifier in the one or more stages; and providing a digital correction signal to the output of the one or more stages to cancel estimated nonlinear error determined in said step of determining.