Patent ID: 6983402
Filing Date: 2006-01-03
Classification: G06F

Abstract:
1. A computer device comprising: a CPU for outputting an address signal and also outputting an access signal twice for the same address signal; a memory for storing a series of programs, the memory receiving the address signal and the access signal from the CPU and outputting a program located at an address corresponding to the address signal twice in response to the access signal; a latch circuit for latching the program output from the memory, according to the access signal; and a match detection circuit for comparing the two programs at the same address output from the memory, that is, a first-time program output from the latch circuit and a second-time program output from the memory, and detecting matching of the two programs, wherein the CPU receives a comparison result signal from the match detection circuit, and outputs the access signal for the same address again if the matching of the programs fails, so that the match detection circuit performs comparison of a third-time program output from the memory with the second-time program output from the latch circuit.