Patent ID: 7793034
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. A method of translating a physical memory address to a device address in a device address space, comprising the actions of: a. performing a fast address translate of the physical memory address, thereby generating a first translated address, the fast address translate being adapted to translate addresses in uniformly configured device address space; b. performing a full address translate of the physical memory address, thereby generating a second translated address, the full address translate being adapted to translate addresses in non-uniformly configured device address space; c. identifying boundaries of a uniform portion of the device address space; d. comparing the physical memory address to the boundaries of the uniform portion of the device address space to determine if the physical memory address is in the uniform portion of the device address space; e. selecting the first translated address as the device address when the physical memory address is in the uniform portion of the device address space and when at least one of the following conditions has been met: the first translated address was selected in an immediately preceding cycle or no new translation was commenced in the immediately preceding cycle; and f. selecting the second translated address as the device address when the first translated address is not selected.