Patent ID: 6894350
Filing Date: 2005-05-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; an LDMOS (lateral double-diffused metal oxide semiconductor) transistor formed in a first region of the substrate; a MOS (metal oxide semiconductor) transistor formed in a second region of the substrate; and a field oxide layer formed in a third region including at least a portion between the first region and the second region, and configured to electrically isolate the first region and the second region, wherein the LDMOS transistor comprises: a channel well region formed in the first region; a first source region formed in the channel well region; a first drain region formed in the first region, apart from the source region; a first gate electrode formed over the first region between the source region and the drain region, at a position substantially near the source region and spatially separated from the drain region; a first gate oxide layer formed on the first region, under a bottom surface of the first gate electrode; and a mitigation oxide layer formed independently from the field oxide layer, on the first region between the first source region and the first drain region, closely contacting a part of the bottom surface of the first gate electrode, and having a thickness larger than a thickness of the first gate oxide layer, and wherein the MOS transistor comprises: a second source region formed in the second region; a second drain region formed in the second region, apart from the source region; a second gate electrode formed on the second region, independently from the first gate electrode, between the second source region and the second drain region; and a second gate oxide layer formed on the second region, independently from the first gate oxide layer, under a bottom surface of the second gate electrode.