Patent ID: 6301629
Filing Date: 2001-10-09
Classification: G06F

Abstract:
A high speed/low speed data processing system comprising:a processing unit that includes a high speed interface;a memory controller that includes a plurality of high speed interfaces;a first high speed bus, having a first data bandwidth, connected between the high speed interface of the processing unit and a first of the high speed interfaces of the memory controller for transfer of information between the processing unit and the memory controller at an information transfer rate;a high speed subsystem that includes a high speed interface;a second high speed bus, having the first data bandwidth, connected between the high speed interface of the high speed subsystem and a second high speed interface of the memory controller for transfer of the information between the high speed subsystem and the memory controller at the information transfer rate;a high speed/low speed interface system that includes a high speed interface and a low speed interface;a third high speed bus, having the first data bandwidth, connected between the high speed interface system and a third high speed interface of the memory controller for transfer of information between the high speed/low speed interface system and the memory controller at the information transfer rate.a low speed subsystem that includes a low speed interface; anda low speed bus connected between the low speed interface of the low speed subsystem and the low speed interface of the high speed/low speed interface system for transfer of information between the low speed subsystem and the high speed/low speed interface system, the low speed bus having a second bandwidth that is greater than the first bandwidth such that information is transferred between the low speed subsystem and the high speed/low speed interface system at the information transfer rate.