Patent ID: 7018753
Filing Date: 2006-03-28
Classification: G03F

Abstract:
1. In a method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design, where each of the integrated circuits is formed with a plurality of layer patterns, where at least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design, the improvement comprising the steps of: imaging the at least one first layer pattern on the substrate using a first mask having a first number of first layer patterns according to the first integrated circuit design formed in a block thereon, with no other layer patterns formed on the first mask, where the first layer patterns are imaged on the substrate by exposing and repeating the block of first layer patterns across the substrate according to a first grid without overlapping the block of first layer patterns, and imaging the at least one second layer pattern on the substrate using a second mask having a second number of second layer patterns according to the first integrated circuit design formed in a block thereon, where the second number is less than the first number with at least one additional layer pattern formed on the second mask, where the second layer patterns are imaged on the substrate by exposing and repeating the block of second layer patterns across the substrate according to a second grid without overlapping the block of second layer patterns, where the first grid and the second grid are aligned such that each integrated circuit and test structures in scribe lines between the integrated circuits are properly formed on the substrate according to the first integrated circuit design.