Patent ID: 6418356
Filing Date: 2002-07-09
Classification: G06Q

Abstract:
A method of optimizing throughput and performance in a wafer processing system, wherein the wafer processing system includes a plurality of modules for processing individual wafers in a sequence wafers, and the wafer processing system includes a plurality of transportation resources for transporting a wafer unit from a first module in the plurality of modules to a subsequent module in the plurality of modules, the method comprising:fixing a constant sending period for sequentially dispatching wafers into the wafer processing system, the sending period remaining fixed throughout the sequence of wafers; expressing times for pickup of the wafer from an ith module, (&tgr;i), in units of the sending period; expressing a plurality of times (&tgr;i) allotted for a wafer transporter to arrive at a module from initiation of a current sending period for transportation of a wafer from a module i to a module i+1 as a portion of the sending period, and; selectively incrementing at least one in the plurality of times (&tgr;i) to arrive at a solution of times (&tgr;i) that remains fixed at constant values throughout the sequence of wafers, the solution of times (&tgr;i) assuring availability of the plurality of transportation resources.