Patent ID: 7577163
Filing Date: 2009-08-18
Classification: H04J,H04L

Abstract:
1. A system for receiving packets, comprising: an asynchronous data packet receiver; a time division multiplex packet receiver; a frame synchronization packet receiver; a fan out circuit operable to receive a bit stream of data, the fan out circuit operable to provide the bit stream of data to the asynchronous data packet receiver, the time division multiplex packet receiver, and the frame synchronization packet receiver; wherein the frame synchronization packet processor is operable to identify a frame code in the bit stream of data for a frame of data, the frame synchronization packet receiver operable to process frame synchronization packets of the frame in the bit stream of data in response to identification of the frame code, the frame synchronization packet receiver operable to transfer operational control to the time division multiplex packet receiver; wherein the time division multiplex packet receiver is operable to process time division multiplex packets of the frame upon receiving control from the frame synchronization packet receiver, the frame synchronization packet receiver operable to transfer operational control to the asynchronous data packet receiver upon receipt of all time division multiplex packets of the frame in the bit stream of data by the time division multiplex receiver; wherein the asynchronous data packet receiver is operable to process asynchronous data packets of the frame upon receiving control from the frame synchronization packet receiver, the frame synchronization packet receiver operable to receive operational control from the asynchronous data packet receiver upon receipt of all asynchronous data packets of the frame in the bit stream of data by the asynchronous data packet receiver.