Patent ID: 7989292
Filing Date: 2011-08-02
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a substrate; forming a plurality of pillar patterns on the substrate; forming an impurity region in the substrate between adjacent the pillar patterns; forming a gate electrode surrounding a portion of each the pillar pattern; forming a first capping layer over an entire surface of the resultant structure including the gate electrode; forming a separation layer by separating the impurity region so that the separation layer contacts a portion of the first capping layer between the gate electrodes of the adjacent pillar patterns; removing the first capping layer except for the portion of the first capping layer contacting the separation layer, to partially expose the gate electrode of each the pillar pattern; forming a sacrificial layer covering the exposed gate electrodes by the portion of the first capping layer; forming a second capping layer over the resultant structure including the sacrificial layer to cover sidewalls of the pillar pattern; removing the entire sacrificial layer after the second capping layer is formed; and forming a word line in the place where the sacrificial layer has been removed to connect the gate electrodes of the adjacent pillar patterns.