Patent ID: 6570420
Filing Date: 2003-05-27
Classification: H03L

Abstract:
An integrated circuit, comprising:a clock path arranged to carry a clock signal; a power supply path arranged to receive power from a power supply; a delay locked loop operatively connected to the power supply path and the clock path, comprising a capacitor, responsive to a phase difference between the clock signal and a delayed clock signal, for storing a voltage potential; a leakage current offset circuit operatively connected to the capacitor, wherein the leakage current offset circuit is arranged to adjust the voltage potential; a programmable current source connected to the leakage current offset circuit, wherein the programmable current source comprises a first current source and a first switch arranged to control the leakage current offset circuit; and a combinational logic circuit, operatively connected to the programmable current source, wherein the combinational logic circuit is arranged to selectively adjust the programmable current source.