Patent ID: 6477661
Filing Date: 2002-11-05
Classification: H03M

Abstract:
A method of operating a digital signal processor capable of performing a Viterbi algorithm comprising:calculating a sum of path metric PM1 of an old state 2N and branch metric BM1, where N=0, 1, . . . 2kâˆ’2âˆ’1, and K represents a constraining length; calculating a sum of path metric PM0 of an old state 2N+1 and branch metric BM0; calculating a sum of the path metric PM1 and the branch metric BM0; calculating a sum of the path metric PM0 and the branch metric BM1; and comparing the value of PM1+BM1 to the value of PM0+BM0 to form a path metric of a new state N, and comparing the value of PM1+BM0 to the value of PM0+BM1 to form a path metric of a new state N+2Kâˆ’2.