Patent ID: 7382653
Filing Date: 2008-06-03
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell group in which a plurality of memory cells each having a control gate and a floating gate are connected in series; a first selection gate transistor connected between one end of the memory cell group and a bit line; a second selection gate transistor which is connected between the other end of the memory cell group and a source line and has a gate length shorter than a gate length of the first selection gate transistor; a control gate drive circuit which drives the control gates of the memory cell group; a selection gate drive circuit which drives gates of the first and second selection gate transistors; a source line drive circuit which drives the source line; and a bit line control circuit which supplies a bit line potential which is used to select data to be written in the memory cells through the bit line, wherein, at the time of a write operation, the control gate drive circuit applies a write voltage to the control gate of the memory cell as a write target in the memory cell group, and applies an intermediate voltage lower than the write voltage to the control gates of the other memory cells, the selection gate drive circuit supplies a first voltage lower than the intermediate voltage to the gate of the first selection gate transistor, and supplies a second voltage lower than the first voltage to the gate of the second selection gate transistor, and the bit line control circuit supplies the first voltage to the bit line which is not selected for writing, and the source line drive circuit supplies the first voltage to the source line.