Patent ID: 6445326
Filing Date: 2002-09-03
Classification: H03M

Abstract:
An analog to digital converter comprising a PWM circuit responsive to an analog parameter of an analog signal, said PWM circuit generating a PWM pulse having a PWM duty cycle proportional to said analog parameter, a counter for generating a plurality of counter pulses during said PWM duty cycle, a subcycle pulse generator for generating a series of subcycle pulses during each of said counter pulses, a latch circuit for latching the state of the subcycle pulse generator at a predetermined time relative to the termination of said PWM pulse, and a logic circuit for counting the number of said counter pulses generated during said PWM pulse to determine an MSB number, and for counting the state of said subcycle pulses in the latch circuit to determine an LSB number, and an adder circuit for adding the MSB number and the LSB number to provide a digital number representative of said analog parameter.