Patent ID: 8314637
Filing Date: 2012-11-20
Classification: G11C,H01L,H03K

Abstract:
1. A non-volatile latch circuit comprising: a first transistor; a second transistor; a first element including a third transistor; and a second element, wherein an output of the first element is electrically connected to an input of the second element and an output of the second element is electrically connected to an input of the first element through the second transistor, wherein the input of the first element is electrically connected to a wiring to which an input signal is applied through the first transistor and the output of the first element is electrically connected to a wiring to which an output signal is applied, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate of the third transistor, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the wiring to which the input signal is applied, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the gate of the third transistor, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output of the second element, wherein an insulating layer is provided over the third transistor, wherein the first transistor and the second transistor are provided over the insulating layer, and wherein a channel formation region of each of the first transistor and the second transistor includes an oxide semiconductor layer.