Patent ID: 6388344
Filing Date: 2002-05-14
Classification: H01L,H02M

Abstract:
A power semiconductor array, comprising:terminals including a first intermediate circuit terminal to be connected to a positive potential, a second intermediate circuit terminal to be connected to a negative potential, at least one load terminal, and a ground terminal; at least two power switches, including a first power switch and a second power switch, connecting said at least one load terminal to said first and second intermediate circuit terminals in alternation; and a direct copper bonding substrate having said at least two power transistors disposed thereon, said direct copper bonding substrate including an insulation layer having a first insulation layer, a second insulation layer, and a conductive intermediate layer disposed between said first insulation layer and said second insulation layer, said conductive intermediate layer connected to one of said first and second intermediate circuit terminals to capacitively connect one of said first and second intermediate circuit terminals to said at least two power switches.