Patent ID: 6055272
Filing Date: 2000-04-25
Classification: H04N

Abstract:
A run length encoder for encoding DCT coefficients obtained in a DCT, a quantization, and scanning steps in block units to output an encoded (run, level) symbol, and outputting a predetermined (run, level) symbol if the obtained DCT coefficients in the block unit are all zero, the run length encoder comprising:a run length encoding core for receiving the DCT coefficients and outputting the encoded (run, level) symbol;a zero coefficient detecting means for detecting whether the DCT coefficients are `0` or not;a zero block detecting means for receiving an output from said zero coefficient detecting means to detect whether all of the DCT coefficients of each block are `0` or not; andan output selecting means for selectively outputting the encoded (run, level) symbol outputted from said run length encoding core and the predetermined (run, level) symbol according to the detected result of the zero block detecting means,wherein said zero block detecting means comprises:a first logical OR gate for performing a logical OR operation for the first and second detection signals;a second logical OR gate for performing a logical OR operation for an output signal from said first logical OR gate and a feedback signal;a first D-flip-flop, being reset by a BS signal, for latching an output signal from said second logical OR gate to be provided to said second logical OR gate as the feedback signal;an inverter for inverting the output signal from said second logical OR gate;a logical AND gate for performing a logical AND operation for an inverted signal from said inverter and the BS signal; anda second D-flip-flop for latching an output signal form said logical AND gate and outputting a selection signal to said output selecting means.