Patent ID: 6385108
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A random access memory circuit comprising:a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array, comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.