Patent ID: 8264900
Filing Date: 2012-09-11
Classification: G11C

Abstract:
1. A memory device, comprising: a memory array having a plurality of bit lines; a plurality of sense amplifiers, each sense amplifier in the plurality having a first input for receiving a cell signal from the memory array and a second input for receiving a reference signal; and switching arrangements by which bit lines of the plurality of bit lines are selectively coupled to the first and second inputs of respective ones of the sense amplifiers in the plurality of sense amplifiers, the switching arrangements including pairs of first and second data lines coupled to the first and second inputs of corresponding sense amplifiers, and switches by which the bit lines are selectively coupled to the pairs of first and second data lines; and further wherein the pairs of first and second data lines are disposed in capacitive coupling relationships with other pairs of first and second data lines, and have twisted layouts which tend to balance effects of the capacitive coupling on the first and second data lines in each pair.