Patent ID: 7321505
Filing Date: 2008-01-22
Classification: G11C

Abstract:
1. A memory circuit, comprising: a latch including MIS transistors, said latch having a first node and a second node configured to be bi-stable with a potential of the first node inverse to a potential of the second node; a plate line; a word selecting line; a first MIS transistor having one of source/drain nodes thereof coupled to the first node of said latch, another one of the source/drain nodes thereof coupled to said plate line, and a gate node thereof coupled to said word selecting line; a second MIS transistor having one of source/drain nodes thereof coupled to the second node of said latch, another one of the source/drain nodes thereof coupled to said plate line, and a gate node thereof coupled to said word selecting line; and a driver circuit configured to set said plate line to a first potential causing the first node to serve as a source node of said first MIS transistor in a first operation mode and to a second potential causing the first node to serve as a drain node of said first MIS transistor in a second operation mode, said first operation mode causing a lingering change in characteristics of said first MIS transistor.