Patent ID: 6591294
Filing Date: 2003-07-08
Classification: G06F,H04W,Y02D

Abstract:
A system corn rising a plurality of microprocessors,wherein each of said plurality of microprocessors include arithmetic operating units, wherein said plurality of microprocessors include at least first and second microprocessors, wherein said first microprocessor is capable of operating in a master mode or a slave mode, wherein said first microprocessor comprises a first terminal, a second terminal and a mode terminal, wherein said first microprocessor receives a bus release signal via said second terminal and outputs a bus grant signal via said first terminal when said first microprocessor receives a first signal via said mode terminal, wherein the first signal controls the first microprocessor to operate in said master mode, wherein said first microprocessor outputs a bus request signal via said first terminal and receives a bus acknowledge signal via said second terminal when said first microprocessor receives a second signal via said mode terminal, wherein the second signal controls the first microprocessor to operate in said slave mode, and wherein said first microprocessor operates in said slave mode and said second microprocessor controls bus arbitration between said first microprocessor and said second microprocessor.