Patent ID: 6567933
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A digital system comprising a processor, wherein the processor is operable to execute a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit, wherein the processor comprises:test port circuitry for receiving test commands from a remote test host; interrupt circuitry for receiving a plurality of interrupt signals, operable to interrupt execution of the sequence of instructions; emulation circuitry for debug events connected to the test port circuitry, operable to cause the processor to enter a debug suspend state in response to a debug event and to leave the debug suspend state to resume execution of the sequence of instruction in response to a command received by the test port circuitry, wherein execution of the sequence of instructions ceases while the processor is in the debug suspend state; and wherein the processor is operable leave the debug suspend state in response to a first interrupt received by the interrupt circuitry to execute a corresponding first interrupt service routine (ISR).