Patent ID: 8610238
Filing Date: 2013-12-17
Classification: H01L

Abstract:
1. A processed wafer comprising: cell regions comprising active circuitry, the cell regions separated by dicing channels; back end of line (BEOL) layers disposed over the cell regions and the dicing channels; and crack stop trenches disposed in a portion of the BEOL layers, the crack stop trenches disposed between the cell regions and the dicing channels, wherein the crack stop trenches are disposed in the BEOL layers, wherein a crack stop trench of the crack stop trenches encircles each cell region of the cell regions in a continuous structure, wherein the crack stop trench of the crack stop trenches comprises an inner continuous metallic wall on an edge of each cell region and an outer continuous metallic wall on an edge of the dicing channel, wherein the crack stop trench comprises an opening with an air gap separating the inner continuous metallic wall from the outer continuous metallic wall such that sidewalls of the crack stop trench expose a major surface of the inner continuous metallic wall and a major surface of the outer continuous metallic wall, and wherein the air gap is disposed between the major surface of the inner continuous metallic wall and the major surface of the outer continuous metallic wall.