Patent ID: 6597217
Filing Date: 2003-07-22
Classification: G05F,H03K,H03L

Abstract:
A circuit comprising:a first transistor, a second transistor, and a third transistor coupled in series, wherein: (a) the first transistor includes a first terminal, a second terminal, and a first gate terminal; (b) the second transistor includes a third terminal, a fourth terminal, and a second gate terminal; and (c) the third transistor includes a fifth terminal, a sixth terminal, and a third gate terminal; wherein the first terminal and the second terminal are shorted together and connected to the third terminal; wherein the fifth terminal and the sixth terminal are shorted together and connected to the fourth terminal; wherein the second gate terminal is coupled to receive a first signal; and wherein the first gate terminal and the third gate terminal are coupled to receive a complement of the first signal; wherein a parasitic capacitance between the first gate terminal and the second terminal is approximately Â½ of a parasitic capacitance between the second gate terminal and the third terminal; and a fourth transistor including a seventh terminal, an eighth terminal, and a fourth gate terminal, wherein the seventh terminal is coupled to the third terminal, the eighth terminal is coupled to a power supply, and the fourth gate terminal is coupled to receive the first signal.