Patent ID: 6436812
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:forming, in sequential order, a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate; partially etching, in sequential order, said anti-reflective layer, said hard mask layer, and said etch stop layer, to form a plurality of parallel etch stop layer patterns and concurrently form a hard mask layer pattern and an anti-reflective layer pattern which are sequentially stacked on each of said etch stop layer patterns; etching said anti-reflective layer pattern; etching said first conductive layer to form a gate electrode under said etch stop layer patterns, with openings separating adjacent gate electrodes; forming a conformal spacer insulating layer on the whole surface of said semiconductor substrate on which said gate electrodes are formed; forming an interlayer insulating layer on said spacer insulating layer so as to fill in the openings between said gate electrodes; and etching said interlayer insulating layer, said spacer insulating layer and said hard mask layer pattern using said etch stop layer patterns as a mask, thereby forming self-aligned contact holes exposing said semiconductor substrate between said gate electrodes, and forming spacers on side walls of said gate electrodes and said etch stop layer patterns.