Patent ID: 6570412
Filing Date: 2003-05-27
Classification: H03H,H03J,H03L

Abstract:
A semiconductor amplification circuit comprising:a pair of differential input terminals; a first MOS transistor having a gate thereof connected to a mutual conductance controlling terminal; a pair of second and third MOS transistors having the gates thereof connected to said differential input terminals and sources thereof connected to either one of the source and drain of said first MOS transistor; a pair of fourth and fifth MOS transistors having the gates thereof connected to a constant bias signal input terminal and the sources thereof connected to the drains of said second and third MOS transistors, respectively; first and second current sources connected to the source and drain of said first MOS transistor, respectively; third and fourth current sources connected to the drains of said fourth and fifth MOS transistors, respectively; a pair of differential output terminals disposed between the drains of said fourth and fifth MOS transistors and said third and fourth current sources; and first and second capacitances having one end thereof connected to the sources of said fourth and fifth MOS transistors, respectively, and one other end thereof connected to a fixed potential.