Patent ID: 8367500
Filing Date: 2013-02-05
Classification: H01L

Abstract:
1. A method for providing self aligned contacts in an integrated MOSFET arrangement having an active area and a gate bus area comprising: providing a semiconductor substrate having a first surface and forming a plurality of semiconductor devices that are accessible at said first surface of said semiconductor substrate; forming an oxide layer on said semiconductor substrate; forming a hard mask of silicon nitride on said oxide layer; etching trenches in said active area of said substrate through a plurality of openings in said hard mask of silicon nitride that is formed on said oxide layer and forming a gate oxide layer on sidewalls of said trenches, wherein said silicon nitride and said oxide layer are formed in said active area of said substrate; forming polysilicon plugs inside said trenches to fill said trenches and polysilicon on the surface of said hard mask of silicon nitride; removing said polysilicon from the surface of said hard mask of silicon nitride and recessing said polysilicon plugs to form recesses above said polysilicon plugs wherein said recesses extend below the top surface of said substrate; and forming polysilicon in a trench in said gate bus area to have wholly planar top surfaces that are coincident with the surface of said hard mask of silicon nitride.