Patent ID: 6100131
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method of fabricating a random access memory cell including the step of forming a raised shallow trench isolation; said step comprising:forming a trench capacitor beneath a major surface of a silicon substrate;forming an oxidation layer on the major surface of the silicon substrate, the oxidation layer being the gate oxide of the transistor;forming a first conductive layer over the oxidation layer, the first conductive layer forming a lower portion of a gate conductor of the transistor;forming a dielectric layer over the first conductive layer, the dielectric layer serving as a polish stop layer for subsequent polishing step;defining and etching a non-active region, the non-active region overlapping a portion of the trench;filling the non-active region with a dielectric material to form a shallow trench isolation region;polishing the dielectric material, wherein the dielectric layer serves as a polish stop, resulting in a planar surface between the dielectric layer and dielectric material; andremoving said dielectric layer, wherein the removing step also removes the dielectric material to result in substantially planar surface between the first conductive layer and the dielectric material.