Patent ID: 6320235
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A semiconductor transistor, comprising:a gate formed over a substrate;a first source/drain region in the substrate, wherein the first source/drain region is adjacent the gate;a second source/drain region in the substrate, wherein the second source/drain region is adjacent the gate, further wherein the second source/drain region is physically separated from the first source/drain region;a buried contact region in the substrate, wherein the buried contact region is physically separated from the first source/drain region; andan electrically-conductive substrate interconnect, wherein the electrically-conductive substrate interconnect comprises an implanted region in the substrate interposed between the buried contact region and the first source/drain region, further wherein the electrically-conductive substrate interconnect provides electrical communication between the buried contact region and the first source/drain region.