Patent ID: 9177981
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A solid-state imaging device comprising: a sensor element interconnect layer between a sensor element semiconductor substrate and a logic element interconnect layer, said logic element interconnect layer being between a logic element semiconductor substrate and said sensor element interconnect layer; semiconductor devices in said sensor element semiconductor substrate, a chip periphery trench encircling said semiconductor devices in a top view of the solid-state imaging device; a first metallic chip periphery guard ring in said chip periphery trench, said chip periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer; a second metallic chip periphery guard ring in said logic element interconnect layer, said chip periphery trench terminating at said second metallic chip periphery guard ring; a first metallic pad periphery guard ring in a pad periphery trench, said pad periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer; a second metallic pad periphery guard ring in said logic element interconnect layer, said pad periphery trench terminating at said second metallic pad periphery guard ring.