Patent ID: 7327007
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type provided on said semiconductor substrate; a first impurity region of said first conductivity type provided in said semiconductor layer, extending from an upper surface of said semiconductor layer to an interface with said semiconductor substrate, to define a predetermined region in said semiconductor layer; a semiconductor element provided in said semiconductor layer outside said predetermined region; and a MOS transistor provided in said semiconductor layer within said predetermined region, said MOS transistor including: a second impurity region of said second conductivity type provided in the upper surface of said semiconductor layer within said predetermined region and having a higher impurity concentration than said semiconductor layer; and a drain electrode electrically connected to said second impurity region, said semiconductor device further comprising: a first insulation film provided on said semiconductor layer between said first impurity region and said second impurity region; a plurality of first field plates spaced from one another on said first insulation film along a direction from said first impurity region to said second impurity region; a second insulation film provided on said first insulation film to cover said plurality of first field plates; a plurality of second field plates spaced from one another on said second insulation film along a direction from said first impurity region to said second impurity region; a third insulation film provided on said second insulation film to cover said plurality of second field plates; and an interconnect line provided on said third insulation film, passing over said plurality of first field plates and said plurality of second field plates, to provide electrical connection between said drain electrode and said semiconductor element, wherein one of said plurality of first field plates which is closest to said first impurity region is a gate electrode of said MOS transistor; said plurality of second field plates respectively are provided above spaces between said plurality of first field plates; one of said plurality of second field plates which is closest to said gate electrode has a cut portion under said interconnect line; and in one of the spaces between said plurality of first field plates which is located under said cut portion, an electrode is provided apart from said plurality of first field plates.