Patent ID: 7574641
Filing Date: 2009-08-11
Classification: G01R,G11C

Abstract:
1. An integrated circuit, comprising: A. functional input pads and functional output pads; B. core circuitry having functional inputs and functional outputs respectively coupled to the functional input pads and functional output pads; C. an output buffer having an input that is coupled to a functional output and an output that is connected to one of the functional output pads; D. first and second test leads selectively connected to the one functional output pad through first and second test switches, the first and second test switches each having a control input; E. a third test lead selectively connected to the input of the output buffer through a third test switch, the third test switch having a control input; F. test access port circuitry including a test data input lead, a test data output lead, a test clock lead, a test mode select lead, and controller circuitry connected to the test data input lead, the test data output lead, the test clock lead, and the test mode select lead; and G. boundary scan circuitry connected to the test access port circuitry, the boundary scan circuitry including: