Patent ID: 7694248
Filing Date: 2010-04-06
Classification: G01R

Abstract:
1. An apparatus for supporting verification, comprising: a detecting unit that detects description data of a false path from first setting data for a system mode operation of a target circuit to be verified; an analyzing unit that stimulates the description data of a false path in the system mode operation and a test mode operation of the target circuit, and that outputs, based on a result of a simulation, a first driving clock which supplies to a first register at a start point of the false path in the system mode operation, a second driving clock which supplies to a second register at an end point of the false path in the system mode operation, a third driving clock which supplies to the first register in the test mode operation and a fourth driving clock which supplies to the second register in the test mode operation; a determining unit that determines, based on the first driving clock, the second driving clock, the third driving clock and the fourth driving clock, whether the description data is usable to the test mode operation; and a generating unit that generates second setting data for the test mode operation based on a result of determination by the determining unit.