Patent ID: 6489253
Filing Date: 2002-12-03
Classification: C23C,H01L

Abstract:
A method of fabricating a 0.18-&mgr;m flash memory semiconductor device, having a virtually void-free interlayer dielectric, comprising the steps of:A. depositing a first boron-phosphorous-tetraethylorthosilicate (BPTEOS) layer on a silicon substrate, the first boron-phosphorous-tetraethyl-orthosilicate (BPTEOS) layer being formed from a group of reagents comprising a boron dopant, a phosphorous dopant, and tetraethyl orthosilicate (TEOS), and the depositing step (A) comprises a first boron dopant flow rate, a first phosphorous dopant flow rate, and a first TEOS flow rate, the depositing step (A) being performed at a low deposition rate of approximately 8Â±2 Ã¥/sec, thereby gap-filling, and thereby eliminating voids; B. depositing a second boron-phosphorous-tetraethyl orthosilicate (BPTEOS) layer on the first BPTEOS layer, the second boron-phosphorous-tetraethyl-orthosilicate (BPTEOS) layer being formed from a group of reagents comprising a boron dopant, a phosphorous dopant, and TEOS, and the depositing step (B) comprises a second boron dopant flow rate, a second phosphorous dopant flow rate, and a second TEOS flow rate, thereby forming the virtually void-free interlayer dielectric; and C. completing formation of the semiconductor device, thereby forming the 0.18-&mgr;m flash memory semiconductor device, having a virtually void-free interlayer dielectric.