Patent ID: 7360036
Filing Date: 2008-04-15
Classification: G11C

Abstract:
1. A data memory circuit, comprising: a plurality of addressable memory cells; a command-decoding device configured for decoding external commands received from a source external to the data memory circuit; a control device configured for controlling and initiating operations on the memory cells in response to the decoded external commands; and a command buffer device configured for buffer-storing an external command received in a critical operating state period during which execution of the external command is impermissible and for releasing the buffer-stored external command for execution after end of the critical operating state period, wherein the command buffer device receives from the control device a multi-bit status signal which indicates the critical operating state period and a critical operating state selected from one of a plurality of critical operating states, wherein the selected critical operating state is determined by activation of multiple bits of the multi-bit status signal.