Patent ID: 7188274
Filing Date: 2007-03-06
Classification: G11C

Abstract:
1. A circuit for use in repairing memory arrays having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, said circuit comprising: an analysis circuit for analyzing failures detected during testing of said memory array and for generating segment repair solutions for each segment; said analysis circuit having registers for storing addresses of selected failures for each segment repair solution, said registers including row address registers for storing row addresses and one column address register for storing a column address; said analysis circuit being operable to store row addresses and one column address in a unique order in segment repair solutions associated with the same segment; and a segment repair solution processing circuit for identifying a best segment repair solution combination, consisting of one segment repair solution from each segment, having a number of different defective row addresses which is less than or equal to said predetermined number of spare rows, said best segment repair solution combination identifying rows and columns to be replaced by said spare rows and said spare column in each segment.