Patent ID: 6097645
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A redundancy circuit for use in a semiconductor memory device, comprising:a decoder circuit having a plurality of compare devices coupled between a match node and a first common node, each compare device receiving a compare signal and providing a low impedance path between the match node and the first common node when its respective compare signal is active;a mimic circuit having at least one mimic device coupled between an active mode node and a second common node, including at least a first mimic device that provides a low impedance path between the active operation node and the second common node;a match indication circuit coupled to the match node, the match indication circuit providing a match indication signal and a no match indication signal according to the potential of the match node; andan interlock circuit for coupling the match indication and no match indication to a match output and no match output, respectively, according to the potential of the active operation mode.