Patent ID: 6272588
Filing Date: 2001-08-07
Classification: G11C

Abstract:
A method for verifying a data retention time in a dynamic random access memory (DRAM) using built-in test circuitry, comprising the steps of:providing a DRAM having a plurality of rows of memory cells, each row periodically requiring a refresh operation to retain valid data;providing refresh control circuitry coupled to the DRAM, the refresh control circuitry providing at least one signal to the DRAM which initiates the refresh operation of the DRAM, the DRAM requiring every row to periodically receive a refresh operation to satisfy a data retention time specification for the DRAM; andproviding built-in test circuitry coupled to the refresh control circuitry and the DRAM, the built-in test circuitry dynamically determines a limit for reliable data retention of the DRAM by testing the DRAM with application of variable refresh rates until at least a first failure of data retention is encountered and scaling a rate of memory refresh at which the DRAM is being refreshed, the scaling being between a normal rate at which the refresh control circuitry initiates a refresh operation and a rate equal to the product of:1/(1+N/M)*normal refresh rate,where N is less than M, and N and M are integers.