Patent ID: 7475193
Filing Date: 2009-01-06
Classification: G06F

Abstract:
1. A multiprocessor system comprising: a plurality of processors; a main memory; and at least one shared cache memory; said shared cache memory including shared control logic; a dual system directory structure having two system shared cache directories including a shared superset cache directory and a shared subset cache directory for performing the role of L bidirectional control and data busses interconnecting said processors with said shared cache memory; bidirectional control and data busses interconnecting said shared superset cache directory with said shared control logic and said shared data array; a unidirectional control bus connecting from said shared superset cache directory to said shared subset cache directory and no data bus connecting to said shared subset cache directory; a bidirectional control bus interconnecting said shared subset directory and said shared control logic; bidirectional control and data busses interconnecting said shared superset cache directory and said main memory; no data bus or control bus between said L in response to an entry being removed from said shared cache memory, said superset directory entry is not invalidated and is instead migrated into said shared subset cache directory.