Patent ID: 8835232
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, said method comprising: forming a disposable dielectric structure on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, wherein all physically exposed surfaces of said disposable dielectric structure are dielectric surfaces; forming a stack of a planar source region and a raised source region and a stack of a planar drain region and a raised drain region, wherein a first interface between said planar source region and said first raised semiconductor material portion and a second interface between said planar drain region and said second raised semiconductor material portion are within a first plane including an interface between said disposable dielectric structure and said SOI substrate, wherein said raised source region and said raised drain region are formed by selective deposition of a first semiconductor material on a semiconductor surface of said top semiconductor layer of said SOI substrate, wherein said deposited first semiconductor material is in direct contact with a sidewall of said disposable dielectric structure; forming, after formation of said raised source region and said raised drain region, at least one dielectric gate spacer around said disposable dielectric structure over, and directly on, top surfaces of said raised source region and said raised drain region, while physically exposing a surface portion of each of said raised source region and said raised drain region; forming, after formation of said at least one dielectric gate spacers, elevated semiconductor material portions on said top surfaces of said raised source region and said raised drain region by selective depositing a second semiconductor material, wherein interfaces between said elevated semiconductor material portions and said raised source region and said raised drain region are formed within a second plane that includes a bottom surface of said at least one dielectric gate spacer; forming metal semiconductor alloy portions by reacting a metal with said second semiconductor material and a portion of said first semiconductor material, wherein interfaces between said metal semiconductor alloy portions and remaining portions of said raised source region and said raised drain region are formed between said first plane and said second plane; forming a planarization dielectric layer over said dielectric gate spacer; physically exposing a top surface of said disposable dielectric structure by planarizing said planarization dielectric layer; and replacing materials of said disposable dielectric structure with a gate dielectric and a gate electrode.