Patent ID: 7188232
Filing Date: 2007-03-06
Classification: G06F

Abstract:
1. A load/store centric exception processing method in a microprocessor employed in executing a plurality of instructions as part of a computing system comprising the steps of: issuing the plurality of instructions at a first pipeline state, the plurality of instructions including a plurality of exception free instructions and a plurality of exception taking instructions; completing each of the plurality of instructions; committing speculatively each of the plurality of instructions at a second pipeline stage when any of a first plurality of conditions is true such that only the plurality of exception free instructions are committed speculatively: generating an actual commit (ComId) for each of the plurality of exception free instructions selected by the committing speculatively, each ComId including a commit speculation control signal (SpecComId) and one of the plurality of identification for one of the plurality of exception free instructions; retiring the plurality of exception free instructions at a third pipeline stage when any of a second plurality of conditions is true; taking the plurality of exception taking instructions at the third pipeline stage; and retiring the plurality of exception taking instructions at the third pipeline stage.