Patent ID: 8767813
Filing Date: 2014-07-01
Classification: H04L

Abstract:
1. A circuit, comprising: an analog to digital converter (ADC) configured to sample a received signal based on a sampling clock; an adaptive timing loop circuit configured to adjust a timing phase of the sampling clock of the ADC to remove first precursor intersymbol interference from the received signal; a mapping circuit configured to generate, using a gain coefficient associated with the adaptive timing loop circuit, a filter coefficient; and a feed forward filter having the filter coefficient that is generated using the gain coefficient, the feed forward filter configured to, subsequent to the first precursor intersymbol interference being removed from the received signal, use the filter coefficient, as adjusted using the gain coefficient, to remove remaining precursor intersymbol interference from the received signal, wherein the adaptive timing loop circuit is configured to adjust the timing phase based on at least one of an estimate signal and a loop gain control constant.