Patent ID: 6788112
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A sense amplifier for a memory device comprising:a first sensing stage comprising a first sending device and a second sensing device; a first sensing line and a second sense line directly connected to a gate of said first sensing device and a gate of said second sensing device, respectively, to reduce capacitive load on said first sense line and said second sense line; wherein a source terminal of said first sensing device and said second sensing device, respectively, is connected to a switchable current sink and a drain terminal of said first sensing device and said second sensing device, respectively, connected to an input of a second sensing stage; said second sensing stage comprising cross-coupled inverters responsive to said first sensing stage, said second sensing stage activated by a sense enable signal following a selected delay, wherein said first sensing stage is deactivated once said second sensing stage is activated; an output driver responsive to said second sensing stage; wherein said second sensing stage of said sensing stage of said sense amplifier, when activated, provides a feedback signal to deactivate said first sensing stage so that at any time only one of said first sensing stage and said second sensing state is active.