Patent ID: 7476976
Filing Date: 2009-01-13
Classification: H01L

Abstract:
1. A QFN integrated circuit package, comprising: a substrate having a metal line extending from a perimeter region of the substrate to an interior region of the substrate, wherein the metal line comprises one or more connection elements disposed in the perimeter region and a high current contact pad disposed in the interior region of the substrate; a semiconductor chip having an active surface, wherein the active surface comprises an active component disposed thereon, and wherein the active surface generally faces the interior region of the substrate; a patterned metal distribution layer formed over the active surface and electrically connected to the active component, wherein the patterned metal distribution layer is operable to dissipate heat associated with the active component; a solder connection disposed between the high current contact pad and the patterned metal distribution layer, wherein the solder connection provides a low thermal and electrical resistance path between the high current contact pad and the patterned metal distribution layer; and an electrically insulative mold compound generally encapsulating the semiconductor chip, wherein the one or more connection elements provide an external electrical connection to the active component of the semiconductor chip encapsulated within the mold compound.