Patent ID: 6020643
Filing Date: 2000-02-01
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate having a main surface;a first conducting layer formed above the main surface of the semiconductor substrate;a second conducting layer formed above the first conducting layer with a first insulating layer interposed therebetween and connected to the first conducting layer through a first via-conductor formed in a first contact hole formed in the first insulating layer; anda third conducting layer formed beneath the second conducting layer with the first insulating layer and a second insulating layer interposed therebetween and connected to the second conducting layer through a second via-conductor formed in a second contact hole formed in the first and second insulating layers;wherein the wall of the first contact hole has a substantially arcuate profile in an area other than an uppermost and a lowermost portion of the first contact hole in a cross section taken on a center line of a vertical direction of the first contact hole, and the wall of the second contact hole has a substantially straight wall profile in an area other than an uppermost and a lowermost portion of the second contact hole in a cross section taken on a center line of a vertical direction of the second contact hole.