Patent ID: 9219074
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A three-dimensional (3D) semiconductor device, comprising: a plurality of memory layers vertically stacked on a substrate and parallel to each other; a plurality of selection lines disposed on the memory layers and parallel to each other; a plurality of bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; a plurality of strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein the bit lines are parallel to a column direction while the selection lines are parallel to a row direction; wherein the adjacent cells in the same column are electrically connected to the different bit lines.