Patent ID: 6797629
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A method of manufacturing a nano transistor, comprising the steps of:performing a first impurity ion implantation process for given regions on a SOI substrate in which a silicon substrate, a buried oxide film and a silicon layer are stacked to form a first well at a given region on the silicon substrate; performing a second impurity ion implantation for other given regions on the SOI substrate to form a second well at other regions on the silicon substrate; removing the given regions of the silicon layer and then forming first and second gate electrodes in which a gate insulating film and a conductive layer are stacked at a given region on the remaining silicon layer; forming first and second source and drain at given regions on the remaining silicon layer; forming an insulating film on the entire structure and then etching a given region of the insulating film to form a first contact hole through which the first and second wells are exposed; etching a given region of the insulating film to form a second contact hole through which the first and second gate electrodes and the second source and drain are each exposed; and forming a metal layer so that the first and second contact holes are buried and then patterning the metal layer to form a metal wire.