Patent ID: 6750147
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A process for integration of a trench for capacitors and removal of black silicon, suitable for a semiconductor substrate having a memory cell region and an edge region, comprising the steps in sequence of:(a) forming an etching mask on the semiconductor substrate; (b) etching the semiconductor substrate to form a capacitor trench having a predetermined depth while the etching mask is used as the shield, and black silicon spikes being generated on the semiconductor substrate at the edge region; (c) conformally forming a thermal oxide film on the capacitor trench; (d) forming a sacrificial layer on an upper surface of the semiconductor substrate at the memory cell region, wherein the sacrificial layer is filled into the capacitor trench; (e) removing the black silicon spikes while the sacrificial layer is used as the shield; (f) removing a part of the sacrificial layer to expose the thermal oxide film formed in the top portion of the capacitor trench and leave a sacrificial structure at the bottom portion of the capacitor trench; (g) removing the exposed thermal oxide film; and (h) removing the residual sacrificial structure.