Patent ID: 6324684
Filing Date: 2001-11-27
Classification: G06F

Abstract:
A processor having real-time execution control for debug functions, comprising:processor circuitry operable to execute embedded code, the embedded code including background code and foreground code; anddebug circuitry interfacing with the processor circuitry and operable to communicate with a debug host;the debug circuitry operable to receive a debug halt command from the debut host; andafter receipt of the debug halt command, the processor circuitry operable to suspend execution of the embedded code to allow debug of the embedded code;the processor circuitry further operable, while execution of the embedded code is suspended, to respond to an enabled interrupt by executing foreground code associated with the enabled interrupt;wherein the debug circuitry has a run state machine, a current state of the run state machine based upon debug commands received from the debug host and indicating execution control directives by the debug host; andthe processor circuitry has an execution state machine, a current state of the execution state machine based upon the current state of the run state machine and indicating execution of instructions by the processor circuitry;wherein the execution state machine has four states: an execute state, a suspend state, a voluntary foreground code execution state, and an involuntary foreground code execution state;wherein the processor suspends execution of the embedded code when the current state of the execution state machine is the suspend state;wherein the processor circuitry is operable to respond to an enabled time critical interrupt that occurs while the execution state machine is in the suspend state by moving to the involuntary foreground code state and executing foreground code associated with the interrupt.