Patent ID: 8320770
Filing Date: 2012-11-27
Classification: H03L,H04L

Abstract:
1. A method comprising: receiving a first input data stream comprising first input data bits at an input frequency, the first input data bits in the first input data stream having been decoded from a symbol stream, each symbol in the symbol stream comprising at least a first symbol bit and a second symbol bit, each first input data bit comprising one of the first symbol bits; generating a first clock signal having a clock frequency and n clock phases; sampling the first input data stream at a rate of n samples per cycle of the first clock signal to generate a first sample stream, the first sample stream comprising one or more first samples for each first input data bit; detecting a first phase difference between the first sample stream and the first clock signal to generate one or more first clock-correction signals and a first select signal; receiving a second input data stream comprising second input data bits at the input frequency, the second input data bits in the second input data stream having been decoded from the symbol stream, each second input data bit comprising one of the second symbol bits; generating a second clock signal having the clock frequency and n clock phases; sampling the second input data stream at a rate of n samples per cycle of the second clock signal to generate a second sample stream, the second sample stream comprising one or more second samples for each second input data bit; detecting a second phase difference between the second sample stream and the second clock signal to generate one or more second clock-correction signals and a second select signal; adjusting the clock signals based at least in part on the first and second clock-correction signals; generating a first recovered data stream by: generating a second recovered data stream by: combining the first and second recovered data streams with each other to generate one or more output streams.