Patent ID: 6324615
Filing Date: 2001-11-27
Classification: G06F

Abstract:
A data processor for performing data exchange commonly among inner circuits and providing reduced wiring resistance and parasitic capacitance of a data path connecting the inner circuits, comprising:more than one bus selectors cascade-connected into a loop by way of bus lines, each of the bus selectors outputting bus data supplied from a preceding one of the bus selectors as bus data to be supplied toward a following one of the bus selectors when none of the inner circuits connected to said each of the bus selectors enables an output enable signal, wherein each of the bus selectors comprises:a pre-selector for selecting output data of one of the inner circuits connected to said each of the bus selectors when said one of the inner circuits enables the output enable signal; anda selector for outputting the bus data supplied from the preceding one of the bus selectors as the bus data to be supplied toward the following one of the bus selectors when none of the inner circuits connected to said each of the bus selectors enables the output enable signal, and outputting the output data selected by the pre-selector when one of the inner circuits connected to said each of the bus selectors enables the output enable signal; anda plurality of said inner circuits connected to said each of the bus selectors, each of the inner circuits enabling said bus selectors to output the output data of one of the inner circuits as bus data to be supplied toward the following one of the bus selectors when said one of the inner circuits enables the output enable signal.