Patent ID: 6356219
Filing Date: 2002-03-12
Classification: G01D,H03M

Abstract:
A device for receiving first and second analog signals consisting of two sinusoidal signals shifted in phase from an encoder and outputting digital pulses corresponding to the approximate number of equal steps the system of which the encoder is a part has advanced or retreated comprising:an analog-to-digital converter for digitizing the input signals; an arctangent lookup table for calculating a relative value count within one input signal period from the digitized input signals; a cycle detector for recognizing advance or retreat to an adjacent first or second signal period; an up/down counter for holding the total value counts accumulated since the system has moved from a datum position; flash memory storing a table relating total value counts to the precise value as previously determined by calibration; a digital processor having a defined interrupt interval, said digital processor programmed, in response to each new interrupt interval, to: i) digitize the first and second analog quadrature signals to produce first and second digitized signals, ii) input the first and second digitized signals and with reference to the arctangent table to calculate the value count, iii) subtract the current value count from the last value count within one signal period and storing in a difference register, and iv) with reference to the flash memory table add or subtract counts to or from the difference register so that the count in the difference register corresponds to the calibrated value moved by the system, a pulse generator for generating the number of pulses in the difference register within an interrupt interval; and means for conveying the calibrated value to an external device.