Patent ID: 6493774
Filing Date: 2002-12-10
Classification: G06F

Abstract:
The microcomputer, comprising:a central processing unit; direct memory access control unit having a plurality of data transfer channels, for performing data transfer control based on data transfer control information supplied from said central processing unit or outside of the microcomputer; and a bus state controller for arbitrating competition between bus right requests supplied from said central processing unit, said direct memory access control unit and outside of the microcomputer and controlling a bus cycle for the outside, wherein said direct memory access control unit includes a first operation for, when a data transfer request is given from outside of the microcomputer with a data transfer set command for controlling the operation of said direct memory access control unit in a state in which said bus state controller has released a bus right to the outside of the microcomputer, performing data transfer control in accordance with the data transfer control information set by the data transfer set command, and wherein said direct memory access control unit includes a second operation for detecting after said first operation that a data transfer set command supplied together with a data transfer request from outside of the microcomputer is placed in a specific first state, to thereby perform data transfer control according to the set data transfer control information, using the same data transfer channel as that for said first operation, and a third operation for receiving a data transfer request from outside of the microcomputer without the delivery of a data transfer set command after said first operation to thereby perform data transfer control according to the set data transfer control information, using the same data transfer channel as that for the immediately preceding data transfer operation.