Patent ID: 7585787
Filing Date: 2009-09-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, comprising: forming a preliminary tunnel oxide layer pattern, a preliminary charge trapping layer pattern and a silicon oxide layer pattern in a first area of a substrate; forming a preliminary gate oxide layer pattern and a preliminary polysilicon layer pattern in a second area of the substrate; forming an aluminum-containing metal compound layer on the silicon oxide layer pattern and the preliminary polysilicon layer pattern; forming an electrode layer on the aluminum-containing metal compound layer; forming an aluminum-containing tertiary metal oxide layer between the preliminary charge trapping layer pattern and the electrode layer by reacting a first portion of the aluminum-containing metal compound layer with the silicon oxide layer pattern; forming an aluminum-containing tertiary metal silicide layer between the preliminary polysilicon layer pattern and the electrode layer by reacting a second portion of the aluminum-containing metal compound layer with the preliminary polysilicon layer pattern; forming a charge trapping structure and a first electrode in the first area by patterning a first portion of the electrode layer, the aluminum-containing tertiary metal oxide layer, the preliminary charge trapping layer pattern and the preliminary tunnel oxide layer pattern, wherein the charge trapping structure includes a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern; and forming a gate structure and a lower electrode in the second area by patterning a second portion of the electrode layer, the aluminum-containing tertiary metal silicide layer, the preliminary polysilicon layer pattern and the preliminary gate oxide layer pattern, wherein the gate structure includes a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern.