Patent ID: 6643746
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A circuit for use in a Unified Memory Architecture system, the circuit comprising:a memory of the Unified Memory Architecture system; a plurality of requesting devices; a plurality of channel selectors capable of receiving a command from at least one of said plurality of requesting devices for the Unified Memory Architecture system; a first memory channel coupled to each of said channel selectors that can provide access to a first area of address space of the memory; and at least one additional memory channel coupled to each of said channel selectors, the or each additional memory channel being capable of providing access to a additional address space of said memory, each channel selector maintaining a channel identification tag that identifies the memory channel associated with the command; an arbiter capable of passing said command to a memory controller with a selector-tag for use when said command is a read request to identify the channel selector that routed the command to the memory channel; wherein said arbiter, memory controller and memory channel used to pass said command are responsible for and capable of transmitting data both to and from said memory; and wherein said arbiter is capable of using said selector tag when passing data obtained from said memory, and said channel selector is capable of using said channel identification tag to order data received from said memory.