Patent ID: 6092127
Filing Date: 2000-07-18
Classification: G06F

Abstract:
A system which performs chained direct memory access (DMA) operations, comprising:a working set of buffers available for receiving data from chained DMA operations;a first-in-first-out memory for storing addresses of buffers, from the working set of buffers, which are available for immediate allocation;a first DMA co-processor which performs a portion of the chained DMA operations;second DMA co-processor which performs a portion of the chained DMA operations; and,a controlling processor which sets up the chained DMA operations and adds addresses of free buffers to the first-in-first-out memory;wherein buffers required for chained DMA operations are allocated separately for each link and only when needed by each link so that:when performing a first chained DMA operation, the first DMA co-processor accesses the first-in-first-out memory to allocate for itself a first buffer from the queue of buffers when a first link in the first chained DMA operation requires a buffer, and when the first buffer is filled, the first DMA co-processor immediately notifies the controlling processor; and,when performing a second chained DMA operation, the second DMA co-processor accesses the first-in-first-out memory to allocate for itself a second buffer from the queue of buffers when a first link in the second chained DMA operation requires a buffer, and when the second buffer is filled, the second DMA co-processor immediately notifies the controlling processor.