Patent ID: 7615859
Filing Date: 2009-11-10
Classification: H01L,Y10T

Abstract:
1. A semiconductor package comprising: a lead frame, a semiconductor chip, bonding wires and an encapsulant wherein the lead frame includes a paddle region, a terminal region and an intermediate region connecting the paddle region and the terminal region; wherein the paddle region includes a surface arranged and configured for receiving and mounting an active surface of the semiconductor chip, the semiconductor chip being mounted in such a way that bond pads provided on the active surface are exposed; the bonding wires provide electrical connections between the bond pads and corresponding bonding areas on the paddle region; the terminal region having upper surfaces that define an upper plane and lower surfaces that define a lower plane, the paddle region, the semiconductor chip and the bonding wires being positioned between the upper plane and the lower plane; and the encapsulant surrounding the semiconductor chip, the paddle region and the bonding wires, the encapsulant having an upper surface that is substantially coplanar with the upper surfaces of the terminal region and a lower surface that is substantially coplanar with the lower surfaces of the terminal region, wherein the terminal region has a plain portion that defines a periphery of the lead frame and a protrusion portion that protrudes inwardly from the plain portion, and a lower surface of the protrusion portion and a lower surface of the plain portion define a first recess T wherein an upper surface of the paddle region and an upper surface of the terminal region define a second recess having a depth T wherein a central region of the paddle region defines an aperture formed therein.