Patent ID: 6569725
Filing Date: 2003-05-27
Classification: G02F,H01L

Abstract:
A method for fabricating a thin film transistor (TFT) array, said TFT array having: a substrate; a plurality of pixel electrodes formed on said substrate and disposed in a matrix having rows and columns; a plurality of TFTs for display each of which is connected to a respective one of said pixel electrodes; a plurality of gate wirings each of which is disposed along every row of said pixel electrodes and each of which is used for supplying a gate signal to said TFTs for display in a corresponding row; a plurality of signal lines each of which is disposed along every column of said pixel electrodes and each of which is used for supplying a data signal to said TFTs for display in a corresponding column; a common conductor line on the gate wiring side formed on said substrate and extending in a direction perpendicular to the direction of extension of said gate wirings; a common conductor line on the signal line side formed on said substrate and extending in a direction perpendicular to the direction of extension of said signal lines; nonlinear elements which are respectively disposed between ends of respective gate wirings and said common conductor line on the gate wiring side and between ends of respective signal lines and said common conductor line on the signal line side, and each of which comprises a plurality of TFTs; said method comprising:providing a substrate; forming a first conductor layer on said substrate and patterning said first conductor layer to form at least said plurality of gate wirings, said common conductor line on the signal line side, and each gate electrode of at least one TFT among said plurality of TFTs forming a respective one of said nonlinear elements disposed between ends of respective gate wirings and said common conductor line on the gate wiring side, wherein said each gate electrode is formed as an isolated conductor region; forming a second conductor layer on said substrate and patterning said second conductor layer to form at least said plurality of signal lines, said common conductor line on the gate wiring side, and each source/drain electrode of at least one TFT among said plurality of TFTs forming a respective one of said nonlinear elements disposed between ends of respective signal lines and said common conductor line on the signal line side, wherein said each source/drain electrode is formed as an isolated conductor region; forming an insulating layer on said substrate and forming contact holes in said insulating layer; and forming a third conductor layer on said substrate and patterning said third conductor layer to form conductor portions which electrically connect respective ones of said gate electrodes formed by said first conductor layer as an isolated conductor region and said common conductor line on the gate wiring side formed by said second conductor layer via said contact holes, and which also electrically connect respective ones of said source/drain electrodes formed by said second conductor layer as an isolated conductor region and said common conductor line on the signal line side formed by said first conductor layer via said contact holes.