Patent ID: 7739478
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A method of pre-fetching data into a cache memory, comprising: storing, in an address memory, a first cache-line address of each of a plurality of data requests from at least one processor; comparing, by control logic, a second cache-line address of a next data request from the at least one processor to the first cache-line addresses, wherein the control logic is connected behind the cache memory such that the control logic is able to detect the next data request if the next data request resulted in a cache miss at the cache memory, but the control logic is unable to detect the next data request if the next data request resulted in a cache hit at the cache memory; and if the second cache-line address of the next data request detected by the control logic is adjacent to one of the first cache-line addresses, the control logic pre-fetching into the cache memory data associated with a third cache-line address adjacent to the second cache-line address.