Patent ID: 6542953
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A method of configuring the communication of data in a computer system having a processor, a bus, and a plurality of interconnection devices for operably connecting memory, additional buses, peripherals, and other apparatuses to the computer system, the plurality of interconnection devices including a primary interconnection device and a plurality of secondary interconnection devices, the method comprising:connecting the primary interconnection device and the plurality of secondary interconnection devices to the bus in a peer arrangement without any interconnection devices hierarchically interconnected between the bus and the interconnection devices; transmitting one or more read configuration commands from the processor on the bus; responding to the configuration read requests from each of the interconnection devices by signaling that each of the plurality of secondary interconnection devices are interconnected to the bus through the primary interconnection device; transmitting one or more configuration write commands from the processor on the bus, the configuration write commands including configuration data representing a range of addresses assigned to the interconnection devices; storing in the primary interconnection device the configuration data for the plurality of secondary interconnection devices; transmitting from the processor on the bus a transaction request directed to an address within the range of addresses assigned to one of the plurality of secondary interconnection devices; and, based on the configuration data stored in the primary interconnection device, the primary interconnection device not responding to the transaction request.