Patent ID: 9087597
Filing Date: 2015-07-21
Classification: G11C

Abstract:
1. A semiconductor storage comprising: a plurality of memory cells formed above a semiconductor substrate; a plurality of bit lines electrically connected to the memory cells; a plurality of sense amplifiers electrically connected to the plurality of the bit lines, each of the sense amplifiers including a first transistor that controls precharging of the bit line, a second transistor that controls a charging of a first node, a third transistor that controls a connection of the bit line to the first node, a fourth transistor that controls a connection of the first node to a second node, a fifth transistor that controls a connection of the first node to a third node, and a sixth transistor that is controlled by a potential of the third node; and a controller configured to control the first through sixth transistors to perform a read operation based on the potential of the third node, wherein during the read operation: (1) the first through fourth transistors are turned on during a first time period, (2) the second transistor is turned off in a second time period after the first time period, (3) the second transistor is turned on and the fourth transistor is turned off in a third time period after the second time period, (4) the second transistor is turned off in a fourth time period after the third time period, (5) the third and fourth transistors are turned off and the fifth transistor is turned on in the fifth time period after the fourth time period, and (6) the fourth transistor is turned on in a sixth time period after the fifth time period, wherein a first voltage is kept during the read operation, the first voltage being applied to a gate of a selected memory cell.