Patent ID: 6011697
Filing Date: 2000-01-04
Classification: H01L,Y10S,Y10T

Abstract:
A chip package comprising:an interconnect substrate having a coefficient of thermal expansion (CTE), a modulus of elasticity, first and second opposite surfaces, peripheral edges, and a central chip mounting area on the first surface;an adhesive layer; anda substantially planar constraining ring having a CTE, a modulus of elasticity, first and second opposite surfaces, outer peripheral edges and a central opening, the substantially planar constraining ring being a laminate having at least one conductive layer and at least one dielectric layer, andwherein the first surface of the substantially planar constraining ring is bonded, by the adhesive layer, to the first surface of the interconnect substrate such that the central opening of the substantially planar constraining ring is positioned over said central chip mounting area of the first surface of the interconnect substrate, andwherein the CTE of the interconnect substrate is within +/-20% of the CTE of the substantially planar constraining ring and the modulus of elasticity of the interconnect substrate differs from the modulus of elasticity of the substantially planar constraining ring.