Patent ID: 6763421
Filing Date: 2004-07-13
Classification: G06F

Abstract:
A data cache subsystem for providing data corresponding to a first and a second addresses associated with first and second instructions in parallel, the data cache subsystem comprising:a data cache RAM including a plurality of data cache lines each having a plurality of data banks, wherein the data cache RAM is configured to output a data cache line selected by the first address; a bank selector circuit coupled to the data cache RAM to receive the data cache line selected by the first address, output a first data bank selected by the first address from the selected data cache line on a true port, and output a second data bank selected by the second address from the selected data cache line on a pseudo port; and an instruction pair testing circuit to generate a non-pair signal indicative of the validity of the second data bank for use with the second instruction based on the probability of the first and second addresses accessing a same data cache line.