Patent ID: 6751762
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A method of testing a memory in an integrated circuit (IC), the method comprising:providing an integrated circuit that includes a memory array, a self test circuit coupled to the memory array and a plurality of I/O pads coupled to the self test circuit; at the integrated circuit, receiving a test pattern from an external circuit through the I/O pads, the external circuit being external relative to the integrated circuit; writing the test pattern to a plurality of locations in the memory array in the integrated circuit; initializing a state in a latch within the self test circuit in the integrated circuit; subsequently, performing the following steps multiple times: changing a column address associated with a data line; reading from the data line; comparing a value read from the data line with a value based on the test pattern; and setting the state of the latch to a value depending upon the results of the comparing and the current value of the state; and after performing the steps multiple times, providing the contents of the latch from the integrated circuit to the external circuitry through the I/O pads.