Patent ID: 6195268
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A stack of IC chip-enclosing layers, comprising:a first layer having a dielectric body providing a cavity and having via conductors in its wall which electrically connect the top and bottom surfaces of the first layer;an IC chip inside the first layer cavity having I/O terminals thereon;an array of low-profile closely-spaced bumps formed on the bottom surface of the first layer adapted to be connected by soldering to external circuitry, each bump comprising a surface mount pad and solder material applied thereon;electrical connections between the chip terminals and the bumps on the bottom surface of the first layer;an array of low-profile closely-spaced bumps formed on the top surface of the first layer in the peripheral space outside the area of the cavity, each bump comprising a surface mount pad and solder material applied thereon;means for enclosing the first layer cavity to permit testing to establish known good quality of the layer prior to stacking, an upper surface of the first layer enclosing means being substantially flush with the top surface of the first layer and the array of low-profile closely-spaced bumps formed on the top surface of the first layer;a second layer supported on the top of the first layer and having a dielectric body providing a cavity and having via conductors in its wall which electrically connect the top and bottom surfaces of the second layer;an IC chip inside the second layer cavity having I/O terminals thereon;means for enclosing the second layer cavity to permit testing to establish known good quality of the second layer prior to stacking;an array of low-profile closely-spaced bumps formed on the bottom surface of the second layer, in the peripheral space outside the area of the cavity, each bump comprising a surface mount pad and solder material applied thereon;the bottom surface of the second layer located closely adjacent to the top surface of the first layer with the array of low-profile closely-spaced bumps formed on the bottom surface of the second layer being aligned with and contacting the array of low-profile closely-spaced bumps formed on the top surface of the first layer due to the upper surface of the first layer enclosing means being substantially flush with the top surface of the first layer;the low-profile closely-spaced bumps on the bottom surface of the second layer being reflow soldered to the low-profile closely-spaced bumps on the top surface of the first layer, adjacent to the upper surface of the first layer enclosing means that is substantially flush with the top surface of the first layer in such a way that the soldering process insures connection of the two sets of bumps regardless of any surface unevenness of the adjacent surfaces of the first and second layers.