Patent ID: 8664995
Filing Date: 2014-03-04
Classification: G06F,H03H,H03K

Abstract:
1. A delay cell for a complementary metal oxide semiconductor (CMOS) integrated circuit (IC), the delay cell comprising: a delay stage configured to generate a delayed output signal based on a provided input signal, the delayed output signal having a programmable delay through the delay cell, the delay cell having at least one of (i) a selectable delay value from a plurality of delay values and (ii) a selectable skew value of a rise time and fall time of an output signal of the delay cell, wherein the delay cell has a relatively uniform cell size and terminal layout over a range of the plurality of delay values and the range of skew values; wherein the at least one of the selectable delay value and the selectable skew value are selected by modifying a single layer of a layout of the IC, without modifying the cell size and terminal layout of the delay stage, thereby achieving a delay cell having a substantially uniform cell size and terminal layout over the range of the plurality of delay values and the range of skew values.