Patent ID: 6321329
Filing Date: 2001-11-20
Classification: G06F

Abstract:
Apparatus for processing data, said apparatus comprising:a main processor driven by a main processor clock signal at a main processor clock frequency, said main processor in a non-debug mode performs normal data processing operations;debug logic at least a portion of which is driven by a debug clock signal at a debug clock frequency, said debug clock frequency being different from said main processor clock frequency and said main processor clock signal being asynchronous with said debug clock signal; andan instruction transfer register into which a main processor compatible data processing instruction is transferred by said debug logic and from which said data processing instruction is read by said main processor; whereinwhen switched from a normal mode to a debug mode said main processor continues to be driven by said main processor clock signal executing no-operation instructions until a data processing instruction is present within said instruction transfer register and said debug logic triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal.