Patent ID: 8330532
Filing Date: 2012-12-11
Classification: G05F

Abstract:
1. A method for a power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks, comprising the following steps: (1) providing an integrated circuit comprising analog blocks generating one or more internal reference voltages, one or more internal supply voltages, and one or more biasing currents, a pulsed mode control logic block, and one or more external capacitors; (2) operating all analog blocks of the circuit in pulsed mode; (3) reducing the ON-time of the analog blocks by achieving quick recharge of internal nodes and the external capacitors by a top-up buffer; (4) minimizing the ON-time of the analog blocks by introducing dynamic control of commutating components ensuring least disturbances of the voltage potentials of the circuit; (5) bypassing low bandwidth blocks by fast bypass comparators; and (6) maintaining voltage levels in the circuit by charge holding capacitors during OFF periods of the pulsed mode.