Patent ID: 9025403
Filing Date: 2015-05-05
Classification: G11C

Abstract:
1. A dynamic logic driver circuit for generating a buffered global word-line output signal having a voltage swing substantially greater than a voltage swing of an input signal provided to the dynamic logic driver circuit, the dynamic logic driver circuit comprising: an input for receiving the input signal; an input logic stack comprising a first plurality of transistors having source and drain terminals connected in series between a power supply voltage and a power supply return voltage, wherein a connection between two of the first plurality of transistors is further connected to an evaluation node, wherein a first one of the first plurality of transistors has a gate coupled to a pre-charge signal and a source coupled to the evaluation node for pre-charging the evaluation node in response to the pre-charge signal, wherein a second one of the first plurality of transistors has a gate terminal connected to the input, wherein at least a third one of the first plurality of transistors is biased by at least one reference voltage, and wherein the reference voltage is between the power supply voltage and the power supply return voltage, so that the third transistor forms a cascode follower that prevents a leakage current within the input logic stack from causing a full difference between the power supply voltage and the power supply return voltage from being applied across a given one of the first transistor or the second transistor; and an output driver circuit for generating the buffered global word-line output signal from a state of the evaluation node.