Patent ID: 6075767
Filing Date: 2000-06-13
Classification: H04L,H04Q

Abstract:
An ATM handler accommodating redundant transmission paths comprising:switch means including a plurality of input ports and a plurality of output ports for distributing an input cell from each of the input ports to either one of the output ports determined according to header information of the input cell;at least one pair of line interface circuits connected to the redundant transmission paths;selector means connected between each of the line interface circuits and the input ports of the switch means;a controller for controlling an overall operation of the ATM handler;register means having a status value to be altered according to a system switchover order from the controller,wherein a switchover operation of the line interface circuit to be coupled with one of the input ports of the switch means by the selector means and a switchover operation of an operation to count cells in the line interface circuits are accomplished in response to a system switchover signal output from the register means;a first microprocessor including a communication interface connected to one of the line interface circuits;a second microprocessor including a communication interface connected to other one of the line interface circuits; anda third microprocessor including a communication interface connected the register means,wherein the controller communicates via a control line with each of the microprocessors according to a predetermined communication protocol;wherein the third microprocessor changes the status value of the register means in response to the system switchover order;a system switchover signal output from the register means is input via a wire independent of the control line to the selector means and the line interface circuits;wherein each of the line interface circuits including first cell processing means having a predetermined count function for input cells from the transmission path and second cell processing means having a predetermined count function for output cells to the transmission path;wherein the selector means selects one of two steams of input cells having passed each of the first cell processing means of the pair of line interface circuits according to the system switchover signal and supplies the selected stream of input cells to either one of the input ports;wherein the selector means supplies a stream of output cells from either one of the output ports of the switch means to each of the second cell processing means in a concurrent manner;wherein each of the first cell processing means includes a first count processing unit for achieving a predetermined header conversion for each input cell from the transmission path and a first header processing unit for conducting a predetermined header conversion for each input cell;wherein each of the second cell processing means includes a first header processing unit for achieving a predetermined header conversion for each output cell to the transmission path and a second count processing unit for conducting a predetermined counting operation for each output cell; andwherein the first and second microprocessors periodically collect count values of cells respectively from the first and second count processing units in the line interface circuits respectively corresponding thereto and transmit, in response to a request from the controller, results of the collection to the controller.