Patent ID: 7396710
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A semiconductor device manufacture method comprising the steps of: (a) patterning a semiconductor layer of an SOI substrate to form a fin-type semiconductor region on a support substrate having an insulating surface, said fin-type semiconductor region having a pair of side walls generally vertical to a surface of said support substrate and an upper surface coupling said side walls; (b) forming an insulated gate electrode structure traversing an intermediate portion of said fin-type semiconductor region and including a gate insulating film and a conductive gate electrode formed on said gate insulating film, said gate electrode having side walls in conformity with the side walls of said fin-type semiconductor region; (c) forming a side wall insulating film on the side walls of said fin-type semiconductor region and on side walls of said insulated gate electrode structure; (d) forming source/drain regions in said fin-type semiconductor region on both sides of said conductive gate electrode; (e) depositing an interlayer insulating film covering said side wall insulating films; (f) opening contact holes through said interlayer insulating film, said contact holes reaching said source/drain regions, and removing said side wall insulating films in said contact holes to expose said source/drain regions; and (g) forming a silicide layer on semiconductor surfaces in said contact holes.