Patent ID: 6400290
Filing Date: 2002-06-04
Classification: H03M

Abstract:
A programmable logic device comprising:a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions; wherein a plurality of regions in at least a subset of the plurality of regions of programmable logic comprises additional logic dedicated to the performance of a turbo decoder, the additional logic comprising a log maximum a posteriori decoder, the log maximum a posteriori decoder comprising: approximation circuitry for approximating the normalization of probability values in the log maximum a posteriori decoder that decodes signals encoded by a turbo encoder whose output is represented by a trellis diagram, the approximation circuitry comprising: a plurality of inputs, each of which provides a probability value having a corresponding sign bit and a plurality of magnitude bits; extraction circuitry that extracts the sign bit from each of the inputs and that provides a corresponding output signal that indicates whether at least one of the sign bits is positive; circuitry responsive to the output signal that provides an approximated probability value when at least one of the sign bits is positive; subtraction circuitry that receives each of the probability values from the inputs and that subtracts the approximated probability value from each of the probability values to produce corresponding normalized probability values; and a plurality of outputs on which the normalized probability values are provided.