Patent ID: 6411125
Filing Date: 2002-06-25
Classification: H03K

Abstract:
A CMOS bus driver circuit comprising an input stage of two complementary MOS transistors (P1,N1), as well as an output stage of two complementary MOS transistors(P2,N2) with an output 18, characterized in that the connection of the source-drain paths of said MOS transistors of said input stage a diode (D) is inserted so that the flow of a current in the direction of said MOS transistor (P1) connected to a supply voltage terminal (14) of said input stage is blocked, its cathode being connected to the gate of said one MOS transistor (P2) of said output stage, and that a blocking circuit component (N3, P5, X) is provided which sets said output stage (P2, N2) into a high impedance state when said driver circuit is not supplied with an enable input EN signal for bus driving.