Patent ID: 8390330
Filing Date: 2013-03-05
Classification: G06F

Abstract:
1. A circuit base cell for implementing an engineering change order (ECO) on a substrate of semiconductor material, the substrate having an N-well thereon, the circuit base cell comprising: a P-type metal-oxide-semiconductor (PMOS) transistor comprising a first diffusion layer, and a first active region in said first diffusion layer and being in the N-well on the substrate; and an N-type metal-oxide-semiconductor (NMOS) transistor comprising a second diffusion layer, and a second active region in said second diffusion layer and being on the substrate to be electrically insulated from said first diffusion layer; said first and second active regions and said first and second diffusion layers being aligned with respect to a reference axis and extending symmetrically in a direction orthogonal to the reference axis; said first and second active regions each having a first width, said first and second diffusion layers each having a second width, the first and second widths each being greater than a circuit base cell width, the circuit base cell width defining a pitch.