Patent ID: 6021467
Filing Date: 2000-02-01
Classification: G06F,Y02D

Abstract:
A central processing unit (CPU) for an information handling system, said CPU comprising:a level one cache for storing a first set of data for use by said CPU;a level two cache for storing a second set of data for use by said CPU wherein the level two cache includes a level two cache output for outputting cache lines of data;at least one data transfer unit operably associated with said level one cache for transferring data within said CPU, said data transfer unit including request means for requesting data to be transferred from said level one cache;miss queue means operably coupled to said data transfer unit and to said level two cache for storing every request for data from said request means in which the data was not located in said level one cache and for forwarding requests stored in said miss queue means to said level two cache;first output means operably associated with said transfer unit for outputting data to be transferred by said transfer unit from said level one cache when the data requested by said request means is located in said level one cache; andlevel two cache access bypass means for providing a single cache line of data from said level two cache output to said first output means in response to multiple requests stored in said miss queue, which have been grouped together into a single request by said level two cache access bypass means, such that multiple accesses of said level two cache for instances of data located in the same cache line are avoided.