Patent ID: 8305826
Filing Date: 2012-11-06
Classification: G11C

Abstract:
1. A method for programming an anti-fuse memory block of a power integrated circuit (IC) device, comprising: applying a first voltage to a pin of the power IC device, the pin being connected to a drain of a high-voltage output field-effect transistor (HVFET) and also to a first terminal of a tap transistor device, a tap voltage being provided at a second terminal of the tap transistor device when an external voltage applied to the pin exceeds a pinch-off voltage of the tap transistor device, the first voltage being less than the pinch-off voltage; turning on a trimming MOSFET associated with a selected anti-fuse of the anti-fuse memory block, the selected anti-fuse including first and second capacitive plates separated by a dielectric layer, the first capacitive plate being coupled to a common node of the anti-fuse memory block, the second capacitive plate being coupled to a drain of the trimming MOSFET; applying a write signal that causes a source of the trimming MOSFET to be shorted to ground through a low-impedance; coupling the second terminal of the tap transistor device to the common node; applying a second voltage that is higher than the first voltage to the pin such that a programming voltage is applied to the first capacitive plate of the selected anti-fuse, the programming voltage being high enough to cause a current to flow through the selected anti-fuse sufficient to destroy at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates.