Patent ID: 7291910
Filing Date: 2007-11-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor chip having a row of external terminals provided at a main surface thereof, the main surface having a first area at a first side of the row of external terminals and a second area at the opposing, second side of the row of external terminals of the semiconductor chip; a first row of bump electrodes positioned over the first area of main surface; a second row of bump electrodes positioned over the first area of main surface and further away from the row of external terminals than that of the first row of bump electrodes; a third row of bump electrodes positioned over the second area of main surface; a fourth row of bump electrodes positioned over the second area of main surface and further away from the row of external terminals than that of the third row of bump electrodes; and a plurality of wirings electrically connecting the bump electrodes and the external terminals, respectively.