Patent ID: 6369422
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A memory cell comprising:a field oxide having spaced apart, opposed barrier walls defining the width limits of the active area of said memory cell, said field oxide being on a substrate of first conductivity type; a source region diffused into said substrate and extending across the cell in the widthwise direction from one field oxide barrier wall to the opposed field oxide barrier wall; a drain region diffused into said substrate and spaced apart from said source region defining a channel region therebetween, said drain region having opposed ends in abutment with said opposed field oxide barrier walls, said source and drain regions being of second conductivity type opposite to said first conductivity type; a first gate oxide overlaying said channel region, an oxide window region extending from within said channel region to within a selected one of said field oxide barrier walls, said oxide window region not extending to the opposed field oxide barrier wall and not extending to said source and drain regions, said oxide window region characterized by a recessed opening in said first gate oxide defining a first zone over said channel region and a recessed opening in said selected field oxide barrier wall defining a second zone over said selected field oxide barrier wall; a conductive floating gate layer overlaying said first gate oxide including all of said first zone of said oxide window region.