Patent ID: 8158965
Filing Date: 2012-04-17
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a dielectric layer having a top surface; a via extending from the top surface of the dielectric layer and having a bottom portion and a top portion; a bottom electrode within the bottom portion of the via; a first phase change layer comprising a first phase change material within the top portion of the via and contacting the bottom electrode, the first phase change layer having a first contact area on a top surface having a first width; a resistive heater layer comprising a heater material having a bottom side in contact with the contact surface on the first phase change layer and having a second contact area on a top side, the second contact area having a second width greater than the first width, and wherein the resistive heater layer has a thickness less than or equal to 10 nm; a second phase change layer comprising a second phase change material, the second phase change layer having a bottom side in contact with the second contact area on the top side of the resistive heater layer; and a top electrode on the second phase change layer; wherein the heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials.