Patent ID: 6411151
Filing Date: 2002-06-25
Classification: G06F,H03K

Abstract:
A semiconductor die comprising:a data line to receive a data signal; a first clock signal line and a second clock signal line to receive a differential clock signal that is synchronized with the data signal; and a differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a single-ended output clock signal, the differential amplifier comprising: a first differential amplifier having a non-inverting input coupled to the first clock signal line and an inverting input coupled to the second clock signal line to amplify the differential clock signal into a single-ended clock signal; a second differential amplifier having an inverting input coupled to the first clock signal line and a non-inverting input coupled to the second clock signal line to amplify the differential clock signal into a single-ended clock signal; an inverter having an input coupled to one of the first differential amplifier or the second differential amplifier to receive one of the single-ended clock signals, and an output to generate an inverted single-ended clock signal; and a voltage follower having an input coupled to one of the first differential amplifier or the second differential amplifier to receive one of the single-ended clock signals that is not received by the inverter and to generate an intermediate single-ended clock signal, the voltage follower having an output connected to the output of the inverter to combine the inverted single-ended clock signal with the intermediate single-ended clock signal to generate the single-ended output clock signal.