Patent ID: 6462428
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A semiconductor device in which semiconductor elements are isolated by an isolation structure, comprising:an SOI substrate having a semiconductor substrate, a buried insulating film formed on said semiconductor substrate, and an SOI layer formed on said buried insulating film; an alignment mark area having a first trench provided in a surface of said SOI layer and an alignment insulating film provided in said first trench; an element forming area provided in the surface of said SOI layer and having at least one element isolated by an isolation insulating film, said at least one element having a control electrode for operation control; an interlayer insulation film covering surfaces of said alignment mark area and said element forming area; a first through hole penetrating said interlayer insulation film said first trench, and said buried insulating film to reach said semiconductor substrate; a first interconnection layer electrically connected through said first through hole to said semiconductor substrate; a second through hole penetrating said interlayer insulation film to reach said control electrode; and a second interconnection layer electrically connected through said second through hole to said control electrode.