Patent ID: 9030881
Filing Date: 2015-05-12
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: memory cells each of which stores data with two or more levels, each of the memory cells including a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer including a ferroelectric layer; and a control circuit which is configured to: apply a first pulse voltage having a first voltage value and a first pulse width to the control gate electrode in a write mode in which charges are stored in the charge storage layer, and apply a second pulse voltage to the control gate electrode in a read mode in which a charge amount in the charge storage layer is judged, wherein the second pulse voltage has a first period and a second period after the first period, wherein the second period has a read voltage value to judge the charge amount in the charge storage layer, and wherein the first period has a second voltage value larger than the read voltage value and a polarization arrangement pulse voltage having a second pulse width narrower than the first pulse width.