Patent ID: 7384838
Filing Date: 2008-06-10
Classification: H01L

Abstract:
1. A method for fabricating a FinFET structure, the method comprising: forming a fin body of semiconductor material having a central channel region and first and second end regions flanking the central channel region; forming a gate electrode having a plurality of sidewalls intersecting the central channel region of the fin body; forming a cap on the gate electrode; depositing a dielectric material that covers the fin body and the gate electrode; recessing the dielectric material to partially expose the cap on the gate electrode without exposing the sidewalls of the gate electrode; forming a plurality of cap spacers flanking the cap on the gate electrode to mask underlying portions of the dielectric material flanking the sidewalls of the gate electrode; anisotropically etching the dielectric material to encapsulate the gate electrode by defining a sidewall spacer on each of the sidewalls of the gate electrode from the portion of the dielectric material masked by a respective one of the cap spacers and to reveal the first and second end regions of the fin body; and after the dielectric material is anisotropically etched, introducing a dopant into the first and second end regions of the fin body to define source/drain regions.