Patent ID: 7002852
Filing Date: 2006-02-21
Classification: G11C

Abstract:
1. A data output circuit, comprising: a plurality of registers; a plurality of register output selection switches respectively connected to the plurality of registers via a plurality of first wires having first lengths, pairs of the plurality of register output selection switches being connected by respective common active regions; a first data group selection switch that is connected to the common active regions of a first subset of the plurality of register output selection switches via a plurality of second wires having second lengths that are shorter than the first lengths; a second data group selection switch that is connected to the common active regions of a second subset of the plurality of register output selection switches via a plurality of third wires having third lengths that are shorter than the first lengths, the first and second data group selection switches being disposed approximately a same distance from the first and second subsets of the plurality of register output selection switches, respectively; and an output driver that is connected to the first and second data group selection switches.