Patent ID: 6683486
Filing Date: 2004-01-27
Classification: H03K

Abstract:
A low voltage level shifter circuit having a latching function implemented on a signal line of an integrated circuit comprising:an input terminal for receiving an input signal having a first voltage range, the first voltage range being from a first low to a first high voltage level, the first high voltage level is less than a full internal device voltage (VCC); a level shifter stage, the level shifter stage being configured to receive the input signal and output a level shifter stage output signal, the level shifter output signal having a second voltage range, the second voltage range being from a second low to a second high voltage level, the second high voltage level is equal to out VCC; a latching circuit coupled to the level shifter stage, the latching circuit being configured to latch the input signal; and an output stage for receiving that level shifter stage output signal and generating an output signal at an output terminal, the output signal having the first voltage range.