Patent ID: 8884288
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A semiconductor structure with multi-layers for testing a Metal-Insulator-Metal capacitor, comprising: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween, and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer, and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate by an insulation layer lying therebetween, and connected with the second circuit area; wherein, the semiconductor structure is formed on a P-type substrate; the second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway which comprises the first electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.