Patent ID: 8642431
Filing Date: 2014-02-04
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a field effect transistor (FET), comprising: hosting a channel region of said FET in germanium (Ge); forming a source and a drain for said FET using selective epitaxy of SiGe, wherein the composition of said SiGe is so chosen to cause a tensile strain of desired extent for said channel region, wherein said SiGe has a SiGe atomic radius; during said forming, incorporating into said SiGe an n-type dopant species and a compensating species, wherein said n-type dopant species has a dopant atomic radius and said compensating species has a compensating atomic radius; selecting said n-type dopant species and said compensating species in such manner that the size of said SiGe atomic radius is inbetween said dopant atomic radius and said compensating atomic radius; and selecting said n-type dopant species to be phosphorous (P), and selecting said compensating species to be antimony (Sb), whereby said P generates n-type carriers, wherein said method further comprises selecting a dose for said P in such manner that a concentration of said n-type carriers in said SiGe is between about 25% and about 75% of the equilibrium solubility limit of P in Ge.