Patent ID: 7811869
Filing Date: 2010-10-12
Classification: G02F

Abstract:
1. A fabrication method of a multi-domain vertical alignment pixel structure, comprising: providing a substrate; forming a gate on the substrate; forming an insulating layer on the substrate to cover the gate; forming a channel layer and a semiconductor layer on the insulating layer, wherein the channel layer is located over the gate; forming a source and a drain and a capacitor-coupling electrode on the substrate, wherein the source and the drain are located on the channel layer and at both sides of the gate, respectively; forming a passivation layer to cover the source, the drain, a part of the channel layer and a part of the semiconductor layer; forming a via hole in the passivation layer to expose the drain, and forming a trench in the passivation layer and the insulating layer and forming a lateral etched groove located on the sidewall of the trench to expose the side edge of the semiconductor layer; forming a first pixel electrode and a second pixel electrode on the passivation layer at both sides of the trench, respectively, wherein the first pixel electrode is electrically connected to the drain through the via hole, while the second pixel electrode is electrically insulated from the first pixel electrode, and the capacitor-coupling electrode is located between the second pixel electrode and the substrate.