Patent ID: 7432750
Filing Date: 2008-10-07
Classification: H03K,H03L

Abstract:
1. A frequency synthesis circuit comprising: a phase locked loop circuit for receiving a reference clock and a feedback clock and for generating an output clock comprising a frequency based on said reference clock and said feedback clock; an interpolator control circuit for programming a frequency for said output clock by generating a control word during an increment interval, said interpolator control circuit for incrementing said control word by an increment size during said increment interval to generate a magnitude for the control word, the control word for providing a control value having said magnitude and a resolution, an interpolator circuit, coupled in a feedback path to said phase locked loop circuit, for receiving said control word from said interpolator control circuit and for receiving said output clock and for generating said feedback clock by introducing a time delay in said output clock based on said control word that varies each increment interval so as to change said frequency of said output clock.