Patent ID: 6150214
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method of fabricating an integrated memory circuit at a semiconducting surface of a body, the integrated memory circuit having both an array portion and a periphery portion, comprising:forming gate structures near doped regions of the surface in both of the array portion and the periphery portion;forming an interlevel dielectric layer over the gate structures and the doped regions;etching contact openings through the interlevel dielectric layer to expose selected locations of the doped regions in both of the array portion and the periphery portion;forming a layer of interconnect material over the interlevel dielectric and into the contact openings in both of the array portion and the periphery portion, so as to make electrical contact with the selected locations of the doped regions, the interconnect material having the properties of stability when subjected to temperatures above a first temperature, and being substantially a barrier to diffusion of dopant from the doped regions;etching the layer of interconnect material to provide interconnections in both of the array portion and the periphery portion; andthen forming capacitor structures overlying the layer of interconnect material in the array portion; wherein the interconnect material consists essentially of titanium nitride; and wherein the step of forming the layer of interconnect material also forms a silicide film between the layer of interconnect material and the selected locations of the doped regions.