Patent ID: 6330286
Filing Date: 2001-12-11
Classification: H04N

Abstract:
In a compressed domain digital communications system, a method for reducing a variable latency associated with a buffer and at least partially resulting from at least one splice between a FROM bitstream and a TO bitstream each including data corresponding to a plurality of frames, the method comprising:temporarily storing a portion of said TO bitstream data in a buffer;determining a value associated with said buffered data and being indicative of said variable latency;regulating a flow of data in the system to reduce the variable latency when the determined value corresponds to a number of frames greater than a given number of frames by selectively deleting a portion of said buffered data corresponding to a select at least one of the frames from the buffer; and,regulating a flow of data in the system to prevent an underflow condition in the system by effecting a repeat last frame command using said buffered data and prevent an overflow condition in the system by slowing a rate of transmission for at least a portion of the data associated with at least one of the frames in the TO bitstream while maintaining a substantially noninterrupted flow of data in said system.