Patent ID: 6130574
Filing Date: 2000-10-10
Classification: G11C,H02M

Abstract:
A circuit configuration for producing negative voltages, comprising;an input connection and an output connection;first and second clock signal connections;a first MOS transistor having a first connection connected to said input connection, a second connection connected to said output connection, and a gate connection;a first capacitor connected between said gate connection of said first transistor and said first clock signal connection;a second MOS transistor having a first connection connected to said gate connection of said first transistor, a second connection connected to said second connection of said first transistor, and a gate connection connected to said first connection of said first transistor;a second capacitor having a first connection connected to said second connection of said first transistor and a second connection connected to said second clock signal connection;a third transistor having a first connection connected to said second connection of said first transistor, a second connection connected to backgates of said first and second transistors, and a gate connection connected to said first connection of said first transistor;a third capacitor having a first connection connected to said first connection of said first transistor and a second connection connected to backgates of said first and second transistors; andsaid first, second and third MOS transistors produced in a triple well structure.