Patent ID: 6831310
Filing Date: 2004-12-14
Classification: B82Y,H01L

Abstract:
An integrated circuit having multiple memory types comprising:a first region having a plurality of transistors for implementing a non-volatile memory, the non-volatile memory comprising charge storing transistors, each of the charge storing transistors having three physically separate gate electrodes surrounding a channel and respective charge storage structures positioned around the channel and the three physically separate gate electrodes, a first gate electrode and a second gate electrode positioned adjacent opposite sidewalls of the channel and a third gate electrode overlying the channel, the third gate electrode receiving electrical bias to program and erase its respective underlying charge storage structure; and a second region having a plurality of transistors for implementing a volatile memory, the volatile memory comprising charge storing transistors, each of the charge storing transistors having three physically separate gate electrodes surrounding a channel and respective charge storage structures positioned around the channel and the three physically separate gate electrodes, a first gate electrode and a second gate electrode positioned adjacent opposite sidewalls of the channel and a third gate electrode overlying the channel, each of the first and second gate electrodes receiving electrical bias to program and erase a respective one of the underlying charge storage structures.