Patent ID: 6829189
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit connected to the cell bit line pair for pre-charging the cell bit line pair to a voltage lower than a first voltage in response to a cell bit line pre-charge control signal; a sense amplifier bit line pre-charge circuit connected to a sense amplifier bit line pair for pre-charging the sense amplifier bit line pair to the first voltage in response to a sense amplifier bit line pre-charge control signal; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair for transferring charges to the cell bit line pair and the sense amplifier bit line pair in response to a control signal; a first sense amplifier circuit connected between the sense amplifier bit line pair for amplifying a voltage of a first bit line of the sense amplifier bit line pair to the first voltage; and a second sense amplifier circuit connected between the sense amplifier bit line pair for amplifying a voltage of a second bit line or the sense amplifier bit line pair to a second voltage in response to a sense amplifier enable signal.