Patent ID: 6240152
Filing Date: 2001-05-29
Classification: G06F,H03L

Abstract:
A clock frequency mode switching system comprising:a first frequency shifter circuit having an input node and an output node;a phase-locked loop (PLL) circuit having a first input node, a second input node and an output node, the first input node coupled to the first frequency shifter output node;a second frequency shifter circuit having an input node and an output node, the second frequency shifter output node coupled to the PLL circuit second input node;a third frequency shifter circuit having an input node and an output node, the third frequency shifter input node coupled to the PLL circuit output node;a synchronizer circuit, coupled to the PLL circuit, the first frequency shifter, the second frequency shifter and the third frequency shifter, to align a frequency update signal with respect to a PLL circuit output signal and subsequently to utilize said frequency update signal to align a logic circuit clock signal with respect to a reference clock signal.