Patent ID: 8298876
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A method, comprising: forming first and second field effect transistors of an integrated circuit; forming a stress layer over said first and second field effect transistors, said stress layer having a first thickness, said stress layer inducing strain in channel regions of said first and second field effect transistors; and selectively thinning said stress layer over at least a portion of said second field effect transistor to a second thickness, a region of said stress layer having said first thickness remaining over at least a portion of said first transistor wherein before said selectively thinning said stress layer, a first difference between amounts of strain in channel regions of said first and second field effect transistors is greater than a second difference between amounts of strain in said channel regions of said first and second field effect transistors after said selectively thinning said stress layer.