Patent ID: 6492260
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method of forming damascene wiring in a semiconductor device, comprising:forming an insulative layer; patterning the insulative layer to form a damascene region in the insulative layer; forming a first conductive layer on the surface of the insulative layer, the conductive layer filling the damascene region; forming a dummy layer on a portion of the first conductive layer that is in the damascene region, wherein a top surface of the portion of the first conductive layer in the damascene region is lower than a top surface of the insulative layer; forming a second conductive layer on the first conductive layer and the dummy layer; and planarizing a resulting structure by removing portions of the dummy layer and the first and second conductive layers until the insulative layer is exposed, such that a portion of the dummy layer remains after the planarization of the resulting structure.