Patent ID: 6103602
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method for providing a memory cell on a semiconductor having a surface, the memory cell having a source, a drain, and a gate stack, the method comprising the sequential steps of:(a) providing a source implant of a first conductivity type in the semiconductor in a source side of the gate stack;(b) providing a pocket implant of a second conductivity type in the semiconductor in the source side of the gate stack and a drain side of the gate stack, the drain side of the gate stack being opposite to the source side of the gate stack, the pocket implant being in a direction substantially perpendicular to the surface of the semiconductor and within seven degrees of perpendicular to the surface of the semiconductor, the second conductivity type being opposite in charge polarity to the first conductivity type; and(c) providing a drain implant of the first conductivity type in the semiconductor in the drain side of the gate stack, wherein short channel effects are reduced.