Patent ID: 6635542
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method of forming an SOI integrated circuit comprising the steps of:preparing an SOI substrate having a silicon device layer above an underlying dielectric, including forming a set of isolation members that define a set of active areas in said device layer; forming a set of NFETs in said set of active areas, said set of NFETs having a set of NFET sources, a set of NFET gates and a set of NFET drains; forming a block mask that exposes said set of NFET sources of said set of NFETs while blocking said set of NFET drains; implanting a set of p-n source junctions at said set of NFET sources with a leakage implant to form body contacts from portions of said silicon device layer below said set of NFET gates through said p-n source junctions to said NFET sources; and completing said SOI integrated circuit.