Patent ID: 6085305
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A processor that executes coded instructions, the processor comprising:at least one execution unit generating speculative results and speculative condition codes affecting an architectural state of the processor;a results buffer having a number of slots, wherein each live instruction in the processor holds a slot in the results buffer;a condition code buffer having the same number of slots as the results buffer, each live instruction in the processor holds a slot in the condition code buffer such that each slot in the condition code buffer has a one-to-one correspondence with a slot in the results buffer;a plurality of speculative results produced by the execution units in response to a live instruction, wherein each speculative result is stored in a unique slot in the results buffer;a plurality of speculative condition codes produced by the execution units each stored a unique slot in the condition code buffer; anda retirement device determining which slots in the results buffer and condition code buffer are no longer dependent on an unresolved branch and transferring the results in the non-speculative slot to an architectural results register and transferring the condition code in the non-speculative slot to an architectural condition code register.