Patent ID: 6081853
Filing Date: 2000-06-27
Classification: G06F

Abstract:
A method for burst transferring of data in a processing system, the processing system having a data bus width of W bytes and a cache line length of L bytes, the cache line having L/W banks, where W and L are even numbers, the lowermost bank being in an odd position and the uppermost bank being in an even position, the method comprising:a) determining a particular bank within a particular cache line for storage of a particular data entity;b) generating an initial address, A.sub.0, for retrieving the particular data entity, wherein the initial address, A.sub.0, is the base address of the particular bank;c) issuing the initial address, A.sub.0, on an address bus to retrieve the particular data entity into the cache line;d) if the particular bank within the particular cache line is in an even position, but is not the uppermost bank, generating a sequence of remaining addresses, wherein each one of the remaining addresses is determined relative to the initial address according to the relationship: ##EQU10## wherein A.sub.i represents an i.sup.th address in the sequence of remaining addresses; ande) applying the remaining addresses on the address bus to retrieve remaining data entities into the cache line.