Patent ID: 6459645
Filing Date: 2002-10-01
Classification: G11C

Abstract:
A method, comprising:segmenting a memory array into a first bank and a second bank, said first bank comprising of a first set of memory cells and a first decoding logic, said second bank comprising of a second set of memory cells and a second decoding logic; coupling a global programming voltage to a first switch coupled to said first bank and to a second switch coupled to said second bank, wherein said first switch and said second switch are turned off and do not pass current; selecting said first bank for programming; enabling said first switch to pass said global programming voltage to said first bank and to said first decoding logic, said second switch to remain turned off, and said second bank and said second decoding logic not receiving said global programming voltage; charging up said first decoding logic for said first bank with said global programming voltage; decoding a memory location within said first bank for programming; and providing said global programming voltage to said memory location.