Patent ID: 8949703
Filing Date: 2015-02-03
Classification: H03M

Abstract:
1. An encoder module for parallel encoding L-digit portions of a K-digit message into an N-digit coded message with P parity digits, comprising: an input configured to receive the L-digit portions of the K-digit message; an output configured to output the N-digit coded message; an L-digit input shift register, wherein an input of the L-digit input shift register is coupled to the input of the encoder module, and an output of the L-digit input shift register is coupled to the output of the encoder module; P/L parity shift registers that are sequentially coupled, wherein an input of a last parity shift register of the P/L parity shift registers is coupled to the input of the encoder module, and an output of the last parity shift register is coupled to the output of the encoder module; and a feedback circuit comprising P/L parity generation modules, wherein each of the P/L parity generation modules is coupled to the output of the last parity shift register by a switch and also coupled to an input of a corresponding one of the P/L parity shift registers, wherein each of the P/L parity generation modules is configured to generate L parity digits to be stored in a corresponding one of the P/L parity shift registers when the switch is closed, wherein L, K, N, and P are positive integers, L is greater than 1, and P is a multiple of L.