Patent ID: 7977726
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A dynamic random access memory (DRAM) cell, comprising: a cell transistor located on a substrate, the cell transistor comprising a source, a drain and a gate structure; and a cell capacitor comprising: a first capacitor electrode located on the substrate and electrically connecting with the drain; a first dielectric layer located on the first capacitor electrode; a second capacitor electrode located on the first dielectric layer; a second dielectric layer located on the second capacitor electrode; a third capacitor electrode located on the second dielectric layer, electrically connecting with the drain and isolated by the second dielectric from the second capacitor electrode and the first dielectric layer, wherein the third capacitor electrode overlaps a portion of the gate structure; and a third dielectric layer located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.