Patent ID: 6147924
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A semiconductor memory device formed on a chip, comprising:a plurality of memory cell blocks arranged in rows and columns, wherein each memory cell block comprises a plurality of memory cells for storing data;a plurality of data input/output circuits divided into a first group and a second group, wherein the first group and the second group are associated with and disposed between a respective subset of the memory cell blocks, and the data input/output circuits have a plurality of data input/output pins; anda plurality of address signal circuits arranged between the first group and the second group, for receiving externally applied address signals, wherein the semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first and second groups are collectively arranged adjacent to each other.