Patent ID: 6989551
Filing Date: 2006-01-24
Classification: G11C,H01L

Abstract:
1. A test structure for testing the sufficiency of tunnel opening sizes in a non-volatile memory cell, comprising: multiple individually programmable write paths aligned substantially in parallel; multiple floating gates aligned substantially in parallel and aligned substantially perpendicularly to the multiple write paths, the floating gates overlapping the multiple write paths to form an array of intersecting areas; an array of tunnel openings formed in the intersecting areas and between the floating gates and write paths, with the tunnel openings formed over a same write path being of substantially a same size and with the tunnel openings farmed over different write paths being of different sizes; and a read path coupled to the floating gates and operable to detect a programmed write path if the tunnel openings formed over the programmed write path are of sufficient size to successfully couple the floating gates to the programmed write path.