Patent ID: 6121085
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method of fabricating a contact opening for a memory cell unit of a semiconductor dynamic random-access memory integrated circuit device, comprising:forming on a substrate, a cell unit transistor, a first oxide layer insulating the transistor, and a bit line, the bit line on the first oxide layer;forming a second oxide layer for insulating the bit line, the second oxide layer covering the first oxide layer, such that the first and second oxide layers are in direct contact with each other throughout a contact area above the source/drain region of the transistor;forming a shielding layer covering the second oxide layer;patterning the shielding layer to form an initial opening for defining the contact opening located substantially above the source/drain region of the transistor to be electrically connected, and revealing the surface of the second oxide layer in the region of the defined contact opening;forming a sidewall spacer covering the sidewall of the initial opening and in direct contact with the second oxide layer;after said forming a sidewall spacer, etching into the second oxide layer where the surface of the second oxide layer is revealed in the initial opening, and through the first oxide layer only in an area within and smaller than the contact area, so as to reveal the surface of the source/drain region, andforming a capacitor bottom plate that includes the shielding layer and the sidewall spacer.