Patent ID: 6594788
Filing Date: 2003-07-15
Classification: G11C

Abstract:
A method of analyzing a repair of failure cell in a memory comprising the steps of:testing a memory having a plurality of storage areas and a plurality of spare lines for relieving failures in said storage areas, and storing in a failure memory cell storage an indication of failure memory cells in the storage areas; counting for each of the storage areas a number of failure memory cells for each row address, a number of failure memory cells for each column address, and a total number of failure memory cells by accessing each memory cell of the failure memory cell storage once; storing the counted numbers as stored data; detecting whether or not the number of failure memory cells for a row or column address of each of the storage areas is greater than a number of spare lines available for relieving a failure; determining a set of failure memory cells to be must-repair when the number of failure memory cells is greater than the number of spare lines available for relieving the set of failure memory cells; updating the stored data and the number of spare lines available for relieving a failure to show said must-repair has been repaired; and resuming a search in said failure memory cell storage for a must-repair condition.