Patent ID: 6353340
Filing Date: 2002-03-05
Classification: H03K

Abstract:
A differential-signal input and output circuit comprising:two transistor groups each formed of two p-channel transistors and two n-channel transistors connected in series in this order from a power to the ground; a first input terminal connected to the gate of a first p-channel transistor of the two p-channel transistors constituting a first transistor group and to the gate of a first n-channel transistor of the two n-channel transistors constituting the first transistor group; a first output terminal connected to a first connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the first transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the first transistor group; a second input terminal connected to the gate of a second p-channel transistor of the two p-channel transistors constituting a second transistor group and to the gate of a second n-channel transistor of the two n-channel transistors constituting the second transistor group; a second output terminal connected to a connection point of a p-channel transistor closer to the ground of the two p-channel transistors constituting the second transistor group and an n-channel transistor closer to the power of the two n-channel transistors constituting the second transistor group; a first inverter whose input side is connected to the second input terminal and whose output side is connected to both of the gate of a third p-channel transistor of the two p-channel transistors constituting the first transistor group, other than the first p-channel transistor, and the gate of a third n-channel transistor of the two n-channel transistors constituting the first transistor group, other than the first n-channel transistor; and a second inverter whose input side is connected to the first input terminal and whose output side is connected to both of the gate of a fourth p-channel transistor of the two p-channel transistors constituting the second transistor group, other than the second p-channel transistor, and the gate of a fourth n-channel transistor of the two n-channel transistors constituting the second transistor group, other than the second n-channel transistor.