Patent ID: 9059395
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A resistive memory device, comprising: a gate stack including mold insulating layers and gates vertically stacked on a substrate; a channel penetrating the gate stack in a vertical direction and electrically connected to the substrate; a gate insulating layer provided between the channel and the gates; and a variable resistance layer on the channel, wherein the variable resistance layer comprises: a vertical layer extending on the channel in the vertical direction; and a protrusion extending toward a sidewall of the gate from the vertical layer in a horizontal direction, the sidewall of the gate facing the channel; wherein the gates in the gate stack define an alcove, the alcove being formed by recessing the gate in the horizontal direction; and wherein the protrusion of variable resistance layer extends towards the alcove in the horizontal direction and overlaps with at least one of the gates in the horizontal direction.