Patent ID: 6539530
Filing Date: 2003-03-25
Classification: G06F

Abstract:
A method for designing a semiconductor integrated circuit having a logic macro-cell, a circular power source wiring disposed around the logic macro-cell in a ring shape and a signal wiring that traverses the circular power source wiring and is led out from the logic macro-cell to an outside, wherein at least the circular power source wiring is formed from a plurality of wiring layers, and a priority wiring direction for each of the plurality of wiring layers are specified; the method comprising:inputting in a library definitions required for automatic placing and routing; inputting the library and a net list defining connections between the logic macro-cell and other logic macro-cells in an automatic placing and routing apparatus; ten determined a placement of the logic macro-cell; ten specifying the priority wiring direction for each of the plurality of wiring layers; then determining the circular power source wiring according to the priority wiring directions; and thereafter, determining the signal wiring according to the priority wiring directions, wherein inputting in a library definitions required for automatic placing and routing includes inputting definitions for positions of vias that mutually connect the plurality of wiring layers that form the circular power source wiring, and wherein determining a placement of the logic macro-cell includes designating an orientation of the logic macro-cell and then determining which one of the plurality of wiring layers forms the edges that compose the circular power source wiring according to the designated orientation and the priority wiring directions.