Patent ID: 6744283
Filing Date: 2004-06-01
Classification: H03K

Abstract:
A cascaded chain of synchronous clocked half-rail differential logic circuits comprising:a first synchronous clocked half-rail differential logic circuit, said first synchronous clocked half-rail differential logic circuit comprising: a first synchronous clocked half-rail differential logic circuit first clock input terminal; a first synchronous clocked half-rail differential logic circuit second clock input terminal; at least one first synchronous clocked half-rail differential logic circuit data input terminal; and at least one first synchronous clocked half-rail differential logic circuit data output terminal; a second synchronous clocked half-rail differential logic circuit, said second synchronous clocked half-rail differential logic circuit comprising: a second synchronous clocked half-rail differential logic circuit first clock input terminal; a second synchronous clocked half-rail differential logic circuit second clock input terminal; at least one second synchronous clocked half-rail differential logic circuit data input terminal; and at least one second synchronous clocked half-rail differential logic circuit data output terminal; a first clock signal coupled to said first synchronous clocked half-rail differential logic circuit first clock input terminal; a second clock signal coupled to said second synchronous clocked half-rail differential logic circuit first clock input terminal and said first synchronous clocked half-rail differential logic circuit second clock input terminal, wherein; said at least one first synchronous clocked half-rail differential logic circuit data output terminal is coupled to said at least one second synchronous clocked half-rail differential logic circuit data input terminal, further wherein; said second clock signal is said first clock signal delayed by a predetermined fixed delay time such that said second synchronous clocked half-rail differential logic circuit is switched only after it has received an input from said first second synchronous clocked half-rail differential logic circuit.