Patent ID: 6405297
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A serial access memory circuit comprising:a memory array for storing data; a serial access register having first and second portions each having addressable cells for storing data from the memory array, the first portion having a last cell with a last address, wherein the serial access memory circuit has a split read transfer (SRT) mode which transfers selected data from the memory array into the second portion of the serial access register while the memory circuit outputs data from first portion, the SRT mode initiated by a control signal; a SRT fault detector responsive to the memory circuit generating an incorrect internal address for the serial register address during the SRT mode to provide a detection signal; and an SRT fault corrector responsive to the detection signal to provide a signal that causes the memory circuit to restart internal address generation at a correct address; wherein the detection signal is based on an SRT signal, a serial-direction (SDIR) signal controlling direction of an I/O port associated with the serial access register, a signal representative of whether the memory circuit has generated an internal address beyond the last address, and a column-address-strobe (CAS) signal.