Patent ID: 6958507
Filing Date: 2005-10-25
Classification: G11C,H01L

Abstract:
1. A memory, comprising: a memory column including, a plurality of word line pairs, a pair of data lines, wherein the plurality of word line pairs intersects the pair of data lines at intersections, and memory cells, wherein each memory cell is coupled to one of the plurality of word line pairs and the pair of data lines, wherein each of the plurality of word line pairs include a read word line and a write word line, and the read word line and the write word line which are included in different word line pairs can both be active simultaneously, wherein the pair of data lines includes a read data line and a write data line, wherein the memory further comprises: a latch having a latch input and a latch output, wherein the latch input is connected to the read data line and to an input data line, wherein the latch is configured to hold data of the input data line or data of a connected memory cell, wherein the latch output is connected to the write data line, and wherein the memory column further comprises a sense amplifier configured to connect the read data line to the latch, wherein the read data line is connected to a sense amplifier input, wherein a sense amplifier output is connected to the latch input.