Patent ID: 6446158
Filing Date: 2002-09-03
Classification: G06F,G11C

Abstract:
A computer memory system having a data bus, with a signal on the data bus having a period p1, the system comprising(a) a first memory bank having data lines; (b) a second memory bank having data lines; (c) a first clock signal attached to the first memory bank, and a second clock signal attached to the second memory bank, each clock signal having a period p2, and wherein the second clock signal is delayed by a time &Dgr;T from the first clock signal; (d) a first FET switch connecting the data lines of the first memory bank with the data bus beginning at the start of each cycle of the first clock signal, and lasting for a time &Dgr;T1; and (e) a second FET switch connecting the data lines of the second memory bank with the data bus beginning at a time &Dgr;T2 after the start of each cycle of the second clock signal, and lasting for a time &Dgr;T3, wherein &Dgr;T, &Dgr;T1, &Dgr;T2, and &Dgr;T3 are chosen so that the data lines of the first FET switch and those of the second PET switch are never connected to the data bus concurrently.