Patent ID: 6708257
Filing Date: 2004-03-16
Classification: G06F

Abstract:
A computer system, comprising:a processor; a first buffer coupled to the processor by a first bus; a second buffer coupled to the first buffer by a second bus; a local memory coupled to the second bus;a first memory controller coupled to the processor by the second bus, further coupled to the second buffer, and further coupled to a memory interface; and a second memory controller coupled to the processor by the second bus, further coupled to the second buffer, and further coupled to the memory interface; wherein the second buffer for storing data-transfer requests, the second buffer is coupled to the memory interface, and the memory interface is adapted to transmit data to, and receive data from a third bus;a first memory and a second memory, each coupled to the third bus, wherein the first memory is connected to the first memory controller, and the second memory is connected to the second memory controller; and a read bypass path, the read bypass path connected to the memory interface, and adapted to transfer data from the memory interface to the second bus without having the data pass through the second buffer.