Patent ID: 6777990
Filing Date: 2004-08-17
Classification: H03L

Abstract:
A delay lock loop circuit receiving a reference clock signal, said delay lock loop (DLL) circuit for aligning in time an output clock signal thereof with an internal feedback clock signal, said DLL circuit comprising:a forward delay circuit receiving said reference clock signal, said forward delay circuit issuing a first delayed clock signal, said forward delay circuit adjustably shifting in time said first delayed clock signal relative to said reference clock signal; a fixed delay circuit receiving said first delayed clock signal, said fixed delay circuit issuing a second delayed clock signal, said second delayed clock signal being shifted in time relative to said first delayed clock signal; a selecting means selecting one of said first delayed and said second delayed clock signals to issue as said output clock signal; and a feedback delay circuit receiving said output clock signal and issuing said feedback clock signal, said feedback clock signal being shifted in time relative to said output clock signal.