Patent ID: 6011748
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A semiconductor device comprising:a memory (90) comprising a plurality of memory cells, each memory cell being selected by a unique combination of row and column addresses supplied to said memory, each memory cell receiving and storing data written thereto and then reading out the stored data when said memory cell is selected;means (80) for comparing data written into each memory cell to data read out of said memory cell when selected;a column address generator (40,49,70) for generating and supplying a column address sequence to said memory in response to successive pulses of an input column address clock signal (14);a row address generator (50,59,70) for generating and supplying a row address sequence to said memory in response to successive pulses of an input row address clock signal (13), such that the column and row address sequences select a sequence of said memory cells; andmeans (10) for selectively generating said column address clock signal and said row address clock signal one of at the same time and at differing times.