Patent ID: 8139004
Filing Date: 2012-03-20
Classification: G09G

Abstract:
1. A display device comprising: a pixel array section; and a drive section, wherein the pixel array section includes power lines, scanning lines arranged in rows, signal lines arranged in columns, and pixels that are arranged in a matrix and that are disposed at intersections of the scanning lines and the signal lines, wherein each of the pixels at least includes a sampling transistor, a drive transistor, a light-emitting element, and a storage capacitor, wherein the sampling transistor has a control end connected to a corresponding one of the scanning lines and a pair of current ends connected between a corresponding one of the signal lines and a control end of the drive transistor, wherein the drive transistor has a pair of current ends, one current end being connected to the light-emitting element and the other current end being connected to a corresponding one of the power lines, wherein the storage capacitor is connected between the control end of the drive transistor and the one current end of the drive transistor, wherein the drive section includes a write scanner configured to sequentially supply a control signal to one of the scanning lines at a time in each horizontal scanning period, and a signal selector configured to supply a drive signal to each of the signal lines, the drive signal being switched between a signal potential and a reference potential in each horizontal scanning period, wherein the sampling transistor applies the drive signal to the control end of the drive transistor in accordance with the control signal, wherein the drive transistor supplies a drive current to the light-emitting element in accordance with the drive signal, wherein the write scanner includes output buffers, each of the output buffers being configured to output a control signal to a corresponding one of the scanning lines, the control signal including a first pulse and a second pulse in each horizontal scanning period, and wherein each of the output buffers includes a first output section connected to a fixed power supply and a second output section connected to a pulse power supply, the first output section outputting the first pulse, and the second output section extracting a pulse supplied from the pulse power supply and outputting the extracted pulse as the second pulse.