Patent ID: 6287905
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, the method comprising:forming a device isolating insulating film for defining an active region on a semiconductor substrate;forming a gate insulating film at the upper portion of the resultant structure;forming a gate electrode overlapped with a mask insulating film pattern at the upper portion of the gate insulating film;forming insulating film spacers at the side walls of the gate electrode and the mask insulating film pattern;forming source/drain regions on the semiconductor substrate at both sides of the insulating film spacers;forming a device isolating insulating film protective film at the upper portion of the resultant structure;forming a sacrificed insulating film at the upper portion of the resultant structure;forming a photoresist film pattern for exposing the whole region in an I type, except the presumed portion of a bit line contact and a storage electrode contact at the upper portion of the sacrificed insulating film;forming a sacrificed insulating film pattern by etching the sacrificed insulating film by using the photoresist film pattern as an etching mask;removing the photoresist film pattern;forming an interlayer insulating film at the upper portion of the resultant structure;forming an interlayer insulating film pattern filled between the sacrificed insulating film patterns, by etching the interlayer insulating film;exposing the device isolating insulating film protective film, by removing the sacrificed insulating film pattern by using an etching selection ratio difference from the interlayer insulating film pattern;exposing a contact region of the semiconductor substrate, by removing the device isolating insulating film protective film by using the etching selection ratio difference from the interlayer insulating film pattern;forming a conductive layer at the upper portion of the resultant structure; andforming a contact plug by removing the conductive layer and the interlayer insulating film pattern according to a chemical mechanical polishing process employing the mask insulating film pattern as an etching barrier.