Patent ID: 6513138
Filing Date: 2003-01-28
Classification: G01R

Abstract:
A pattern generator for generating a test pattern to test a memory device, comprising:an address generator for generating an address signal with a test rate T to be supplied to a memory device under test: a data generator for generating write data to be stored in the memory device under test, said data generator comprising: a first data generator for generating even number write data; a second data generator for generating odd number write data; an address converter provided with said address signal from said address generator for generating an even number address incrementing by two at each test rate T and an odd number address incrementing by two at each test rate T; first means for inverting said even number data from said first data generator as a function of said even number address from said address converter; and second means for inverting said odd number data from said second data generator as a function of said odd number address from said address converter.