Patent ID: 7465626
Filing Date: 2008-12-16
Classification: C23C,H01L

Abstract:
1. A method for fabricating a dielectric stack in an integrated circuit, the method comprising the steps of: forming a high-k dielectric layer on a semiconductor substrate; exposing the high-k dielectric layer on the semiconductor substrate to a vapor phase reactant comprising nitrogen and a vapor phase reactant comprising silicon in a plasma-enhanced chemical vapor deposition process or a plasma-enhanced atomic layer chemical vapor deposition process at a temperature of from 300 degrees Celsius to 600 degrees Celsius so as to form a dielectric layer comprising silicon and nitrogen and essentially no high-k material and an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising The high-k material, silicon, and nitrogen, whereby a dielectric stack is fabricated, wherein a crystallization temperature of the dielectric stack is higher than a crystallization temperature of the high-k dielectric layer and higher than 600 degrees C., such that integrity degradation of the high-k dielectric due to crystallization is minimized; and depositing a polysilicon conducting layer atop the dielectric layer, wherein essentially no high-k material is in contact with the polysilicon conducting layer such that reaction between The high-k dielectric and the polysilicon is prevented, whereby thermal stability of the high-k dielectric against crystallization is increased.