Patent ID: 6181165
Filing Date: 2001-01-30
Classification: B24B,H03K

Abstract:
A buffer circuit comprising:a high power source at a high voltage level (V.sub.DD) coupled to the buffer circuit, wherein V.sub.DD is used to operate most of logic circuits of the buffer circuit;a low power source at a low voltage level (V.sub.SS) coupled to the buffer circuit;an input node for receiving an input signal;an enable node for receiving an enable signal;an output node;the buffer circuit, in response to an input signal having a reduced voltage range and an active enable signal, generates an output signal having the reduced voltage range, wherein the reduced voltage range comprises a logic 0 level of about V.sub.SS and a logic 1 level of about V.sub.RED, where V.sub.RED is less than V.sub.DD ; andthe buffer circuit, in response to an inactive enable signal, decouples the input node from the output node.