Patent ID: 6223254
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A microprocessor that processes microprocessor instructions, comprising:an instruction cache for storing at least one said microprocessor instruction;a decode pipeline for translating said microprocessor instruction into at least one corresponding decoded parcel; anda parcel cache for storing said corresponding decoded parcel when said microprocessor instruction is translated;wherein said decode pipeline is bypassed by providing said corresponding decoded parcel from said parcel cache to at least one execution unit when said microprocessor instruction is to be processed and said corresponding decoded parcel is present in said parcel cache, said microprocessor instruction translating into a plurality of interdependent decoded parcels which are iteratively executed by said at least one execution unit, wherein at least one of said interdependent decoded parcels includes a control transfer parcel that branches to said microprocessor instruction when a particular condition is met, said microprocessor instruction pointing to a target one of said interdependent decoded parcels, wherein said interdependent decoded parcels are provided to said at least one execution unit from said parcel cache without said microprocessor instruction being decoded for each iterative execution of said interdependent decoded parcels.