Patent ID: 6195733
Filing Date: 2001-02-27
Classification: G06F

Abstract:
A method to share memory in a single chip multiprocessor system, the method comprising:presenting a shared bus coupled to a microprocessor through a bus coupler;presenting a first digital signal processor coupled to a first array of random access memories over a first private program bus, wherein the first array of random access memories is coupled to the shared bus;presenting a second digital signal processor coupled to a second array of random access memories over a second private program bus, wherein the second array of random access memories is coupled to the shared bus,wherein each of the first digital signal processor and the second digital signal processor are adapted to process data in the second array of random access memories in accordance with program instructions stored in one of first array of random access memories;loading a predetermined page of program instructions into at least a first and second available memory of the first array of random access memories;coupling the first memory to one of the first private program bus and the second private program bus;executing the program instructions in one of the first digital signal processor and the second digital signal processor;releasing the first memory from one of the first private program bus and the second private program bus;coupling the second memory to one of the first private program bus and the second private program bus;executing the program instructions in one of the first digital signal processor and the second digital signal processor; andreleasing the second memory from one of the first private program bus and the second private program bus.