Patent ID: 6871246
Filing Date: 2005-03-22
Classification: G06F,Y02D

Abstract:
1. A data processing system, comprising: interconnect; a first interconnect master, coupled to the interconnect; a second interconnect master, coupled to the interconnect; shared storage, coupled to the interconnect, for use by the first interconnect master and the second interconnect master; a first control storage circuit which corresponds to the first interconnect master; a second control storage circuit which corresponds to the second interconnect master; and prefetch circuitry, coupled to the first control storage circuit and to the second control storage circuit, said prefetch circuitry selects one of the first and second control storage circuits based upon which one of the first and second interconnect masters is requesting an access to the shared storage, and said prefetch circuitry uses the selected control storage circuit to selectively restrict prefetches from the shared storage triggered by the access to the shared storage.