Patent ID: 8542030
Filing Date: 2013-09-24
Classification: G01R

Abstract:
1. A method of testing a three-dimensional (3D) integrated circuit, the method comprising: defining a first group of parts by at least one of a region and a layer on the 3D integrated circuit; applying a first intensity of stress test conditions to the first group of parts on the 3D integrated circuit; defining a second group of parts by at least one of a region and a layer on the 3D integrated circuit that is different from the region or layer of the first group of parts; applying a second intensity of stress test conditions to the second group of parts on the 3D integrated circuit, the second intensity of stress test conditions different from the first intensity of stress test conditions, the second intensity of stress test conditions determined by sensitivities identified for each of the first group of parts and the second group of parts; and determining whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.