Patent ID: 9030901
Filing Date: 2015-05-12
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first memory block group including memory blocks coupled to first sub bit lines; a second memory block group including memory blocks coupled to second sub bit lines; an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group; and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit, wherein the operation circuit controls the voltage levels of the main bit lines according to data in a program operation for storing the data in memory cells included in the selected memory block of the first memory block group.