Patent ID: 6543027
Filing Date: 2003-04-01
Classification: G11C

Abstract:
An application specific integrated circuit which includes:(a) a clock recovery circuit responsive to an input signal to recover therefrom a sequence of data values and a recovered clock; (b) a memory for receiving input data in addressable storage locations; (c) a first address generator for generating memory addresses in a cyclic sequence said first address generator having an input responsive to said recovered clock signal, whereby the addresses generated by the first address generator increment in response to a repetitive transition in said recovered clock signal; (d) a second address generator for generating memory addresses said second address generator having an input responsive to said recovered clock signal whereby the addresses generated by the second address generator increment in response to a repetitive transition in said recovered clock signal; (e) a multiplexer for selecting between addresses generated by said first address generator and addresses generated by said second address generator; and (f) means for reading data values from a set of locations corresponding to the addresses generated by the first address generator to determine whether any two consecutive locations contain the same data.