Patent ID: 6072749
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A memory device having a burst mode that performs write and read of multiple bits synchronous with a clock, comprising:a memory cell array including plural memory cells for storing data and plural bit lines connectable thereto;a sense amplifier that detects and amplifies the electric potential of said bit lines;a first column selection circuit that is driven according to said bit line electric potential, and that is opened or closed by a first column selection signal generated for each of said bit lines;a first data bus provided in common with said plural bit lines, and driven by said first column selection circuit;a read main amplifier connected to said first data bus;a second column selection circuit that is opened or closed by said first column selection signal;a second data bus provided in common with said plural bit lines via said second column selection circuit; anda write amplifier that, in synchronous with said clock, drives said second data bus according to the written data so as to perform a write operation to said memory cells; andwherein, in said burst write mode, said write amplifier is prohibited from driving said second data bus in response to a mask signal that requests prohibition of predetermined write operations.