Patent ID: 7777551
Filing Date: 2010-08-17
Classification: G06G

Abstract:
1. A multiplier circuit comprising: a voltage summation circuit that receive first and second input voltages and produces a differential sum voltage of the first and second input voltages; and a voltage subtraction circuit that receive the first and second input voltages and produces a differential subtraction voltage of the first and second input voltages; a first squaring circuit including: a diode-connected first MOS transistor; and a first differential MOS transistor pair that is connected in cascode to the diode-connected first MOS transistor and receives the differential sum voltage, an output of the first squaring circuit being a first terminal voltage of the diode-connected first MOS transistor; and a second squaring circuit including: a diode-connected second MOS transistor; and a second differential MOS transistor pair that is connected in cascode to the diode-connected second MOS transistor and receives the differential subtraction voltage, an output of the second squaring circuit being a second terminal voltage of the diode-connected second MOS transistor, a differential voltage between the first and second terminal voltages of the first and second squaring circuits corresponding to a product of the first and second input voltages.