Patent ID: 6025737
Filing Date: 2000-02-15
Classification: H03K

Abstract:
An integrated circuit comprising:an output driver coupled to a first voltage supply;a level shifter circuit coupled to a second voltage supply; anda voltage down converter circuit, coupled to the second voltage supply, to generate a third voltage supply having a voltage level below the second voltage supply, wherein circuitry in a core of the integrated circuit is coupled to the third voltage supply, wherein the voltage down converter comprises:a conversion transistor coupled between the second power supply and the third power supply; andan amplifier coupled to receive the third power supply and feedback a control signal to the conversion transistor, thereby regulating an output of the third power supply, wherein the conversion transistor is formed by a plurality of parallel transistors and the amplifier is formed by a plurality of smaller amplifiers, and each smaller amplifier is coupled to a group of the parallel transistors, thereby minimizing parasitic resistance and capacitance in the coupling of the amplifier to the conversion transistor.