Patent ID: 8723571
Filing Date: 2014-05-13
Classification: H03L

Abstract:
1. An integrated circuit comprising: a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input and configured to receive a digital control parameter; and a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator; wherein the integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage, and wherein the frequency of the clock signal varies both with the supply voltage and the digital control parameter such that the digital control parameter determines the way in which the frequency of the clock signal varies with the supply voltage, and wherein the digital control parameter is adjustable such that the frequency of the clock signal can be reduced whilst the supply voltage is maintained above an acceptable minimum voltage range so as to prevent a failure in the operation of the microprocessor.