Patent ID: 7522898
Filing Date: 2009-04-21
Classification: H03D,H03L

Abstract:
1. A frequency synthesizer comprising: a phase detector having a first input that receives a reference signal having a reference frequency and a second input that receives a feedback signal; a charge pump coupled to the phase detector; a filter coupled to the charge pump; a voltage controlled oscillator coupled to the filter; a first plurality of dividers coupled to an output of the voltage controlled oscillator that generate a first plurality of divided signals, wherein the first plurality of dividers are divide-by-two circuits coupled in series; a digital divider coupled between the first plurality of dividers and the second input of the phase detector; a first mixer having a first input coupled to an output of a first divider in the first plurality of dividers having a frequency of one-half a frequency of the voltage controlled oscillator, a second input coupled to an output of a second divider in the first plurality of dividers having a frequency of one-fourth the frequency of the voltage controlled oscillator, and an output for producing the sum of the first mixer input frequencies; a first divide-by-two circuit coupled to the output of the first mixer; a second divide-by-two circuit coupled to an output of the first divide-by-two circuit; a second mixer having a first input coupled to the output of the first mixer, a second input coupled to an output of the second divide-by-two circuit, and an output for producing the sum of the second mixer input frequencies; a third mixer having a first input coupled to a third divider in the first plurality of dividers having a frequency of one-eighth the frequency of the voltage controlled oscillator, a second input coupled to the output of the second mixer, a control terminal for configuring the third mixer to produce either the sum or difference of the input frequencies, and an output for producing the sum or difference of the third mixer input frequencies; a first intermediate multiplexer having a first input coupled to the output of the second mixer, a second input coupled to the output of the third mixer, and a first select line for selectively coupling the first or second inputs to a first intermediate multiplexer output; a fourth mixer having a first input coupled to the output of the first intermediate multiplexer, a second input coupled to the output of the first divide-by-two circuit, and an output for producing the sum of the forth mixer input frequencies; a second intermediate multiplexer having a first input coupled to the output of the first mixer, a second input coupled to the output of the first divide-by-two circuit, and a second select line for selectively coupling the first or second inputs to a second intermediate multiplexer output; a fifth mixer having a first input coupled to the output of the forth mixer, a second input coupled to the output of the second intermediate multiplexer, and an output for producing the sum of the fifth mixer input frequencies; and a third multiplexer having a first input coupled to the output of the first intermediate multiplexer, a second input coupled to the output of the forth mixer, a third input coupled to the output of the fifth mixer, and a select line for selectively coupling the first, second or third inputs to a third multiplexer output.