Patent ID: 7198979
Filing Date: 2007-04-03
Classification: H01L

Abstract:
1. A method of stacking semiconductor chips, the method comprising: providing first, second, third and fourth semiconductor chips, each semiconductor chip including a top surface having central wire bond pads formed in a central portion thereof, each of the wire bond pads being electrically coupled to second wire bond pads located in a peripheral portion of the top surface of the semiconductor chip through a conductive layer, each semiconductor chip further including an encapsulation material overlying the central portion, each semiconductor chip including a bottom surface, which is opposite the top surface; arranging the first and the second semiconductor chips alongside one another on a substrate that includes a plurality of wire bond landing pads on a top surface of the substrate, wherein the bottom surfaces of the semiconductor chips are placed on the top surface of the substrate; electrically connecting second wire bond pads from the first and second semiconductor chips to corresponding wire bond landing pads on the substrate; stacking the third semiconductor chip over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip; bonding the second wire bond pads of the third and fourth semiconductor chips to wire bond landing pads of the substrate; and cutting the substrate to separate a first stack that includes the first and third semiconductor chips from a second stack that includes the second and fourth semiconductor chips, wherein cutting the substrate includes severing the wire bonds between the second wire bond pads of the third and fourth semiconductor chips and the wire bond landing pads to create free ends of the wire bonds.