Patent ID: 8583845
Filing Date: 2013-11-12
Classification: G06F

Abstract:
1. A multi-processor system comprising: at least one main processor; a plurality of sub-processors; an execution control unit that issues a process command to each of the sub-processors based on a process sequence designated by the main processor, and acquires an execution result of processing executed by each of the sub-processors in accordance with the process command; and an arbiter unit that arbitrates transfer of the process command and the execution result between the execution control unit and each of the sub-processors, wherein the arbiter unit includes: a control bus control unit that controls a control bus for transferring the process command from the execution control unit to each of the sub-processors; and a status bus arbiter unit that arbitrates access to a status bus for transferring the execution result from each of the sub-processors to the execution control unit, wherein the execution control unit includes: a memory in which a command FIFO area storing a command from the main processor, a status FIFO area storing the execution result, and an interruption FIFO area storing content of an interruption notification to the main processor are formed on the same address space; and an address generation unit that generates an address on the memory for accessing desired data in each of the FIFO areas, based on a base address of each of the FIFO areas and the number of stages of data capable of being stored in each of the FIFO areas.