Patent ID: 6504788
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A semiconductor memory comprising:a first inverter having its input terminal connected to a first memory node that is connected to a first bit line when a first word line is active, and its output terminal connected to a second memory node that is connected to a second bit line when a second word line is active; a second inverter having its input terminal connected to the second memory node, and its output terminal connected to the first memory node; and a first read circuit having its input terminals connected to the first memory node and the second memory node, and its output terminal connected to a read bit line, wherein said first read circuit includes: a first MOS transistor having its gate connected to the first memory node; a second MOS transistor having its gate connected to the second memory node, and its drain connected to the drain of said first MOS transistor; and a third MOS transistor having its source and drain brought into conduction when a read control line connected to its gate is active, thereby connecting the read bit line to the drains of said first MOS transistor and said second MOS transistor.