Patent ID: 6260164
Filing Date: 2001-07-10
Classification: G11C

Abstract:
An SRAM comprising:a. a clock signal having two phases;b. a scan/hold/enable controller which generates a first selection signal;c. an ABIST controller which generates a second selection signal;d. a plurality of first multiplexers responsive to the first selection signal, wherein each of the first multiplexers selects as an output one of a scan data in signal, a hold signal, and a data capture feedback signal;e. a plurality of latches that can be clocked on either of the two phases of the clock signal and which receive as data the outputs of the first multiplexers; andf. a plurality of second multiplexers responsive to the second selection signal, wherein each of the second multiplexers selects either of a logic data-in signal or an output from the plurality of latches;wherein the first selection signal is latched by non-scan repower latches.