Patent ID: 7825777
Filing Date: 2010-11-02
Classification: G06F

Abstract:
1. An integrated circuit comparator, comprising: at least one n-bit comparator cell configured to determine a non-strict inequality between a first n-bit operand A[n−1, . . . , 0] and a second n-bit operand B[n−1, . . . , 0], according to the following expression and boolean equivalents of the following expression:  where n is a positive integer greater than one, C a first pair of MOS transistors electrically connected in parallel between first and second nodes and having gate terminals that receive operand bit A a second pair of MOS transistors electrically connected in parallel between the second node and a third node and having gate terminals that receive operand bit A a third pair of MOS transistors electrically connected in series between the second node and a fourth node and having gate terminals that receive the operand bit A a fourth pair of MOS transistors electrically connected in series between the third node and the fourth node and having gate terminals that receive the operand bit A a MOS input transistor having a first current carrying terminal electrically connected to the first node, a second current carrying terminal electrically connected to the fourth node and a gate terminal that receives the control input signal C