Patent ID: 6642612
Filing Date: 2003-11-04
Classification: H01L,H05K,Y10T

Abstract:
A lead-bond type chip package, comprising:a multilayer substrate having opposing upper and lower surfaces, the multilayer substrate having therein a slot, the multilayer substrate comprising an interlayer circuit board having opposing upper and lower surfaces, said interlayer circuit board having conductor circuits formed therein, dielectric layers on the upper and lower surfaces of the interlayer circuit board, a plurality of leads on the dielectric layer on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection disposed on the dielectric layer on the lower surface of the interlayer circuit board, wherein the solder pads are electrically connected to corresponding leads by a plurality of conductive traces and at least one through hole extending from the upper surface of the multilayer substrate to the lower surface of the multilayer substrate; a semiconductor chip disposed on the multilayer substrate, the semiconductor chip having a plurality of bonding pads electrically connected to corresponding leads of the multilayer substrate; and a package body formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate.