Patent ID: 7461238
Filing Date: 2008-12-02
Classification: G06F

Abstract:
1. A method of executing instructions in a processor, the method comprising: receiving a load instruction and a store instruction to be executed in the processor; determining if load-store conflict information encoded in both the load instruction and the store instruction indicates that the load instruction previously conflicted with the store instruction, wherein the load-store conflict information includes a conflict bit and history bits, and wherein detecting a conflict comprises: scheduling execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict only if the load-store conflict information is set for both the load instruction and the store instruction and the value stored in a plurality of history bits are above a threshold level; executing the load instruction and the store instruction; and changing the history bits, wherein the history bits are decremented if the load effective address does not match the store effective address and incremented if the load effective address and the store effective address match, wherein the history bits are indicative of a prediction level, wherein a higher value of the prediction level represents a greater chance of detecting a conflict between the load instruction and the store instruction during subsequent execution of the load instruction and the store instruction.