Patent ID: 7782688
Filing Date: 2010-08-24
Classification: G01R,G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a die in which a plurality of internal circuits are integrated; and a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits external to the semiconductor device, and wherein the semiconductor device is configured so that when a first wafer test is completed through one of the first channel pads and the second channel pads, a lateral movement corresponding to the pad pitch of the semiconductor device relative to the probe card enables a second wafer test to be performed through the other of the first channel pads and the second channel pads.