Patent ID: 8472251
Filing Date: 2013-06-25
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory cell formed on a substrate, the nonvolatile memory cell comprising: a first deep diffusion well of an impurity of a first conductivity type formed in a surface of the substrate; a first shallow diffusion well of an impurity of a second conductivity type formed within the first deep diffusion well; a second shallow diffusion well of the second conductivity type formed within the first deep diffusion well; a programming charge coupling metal oxide semiconductor (MOS) transistor connected as a capacitor wherein the programming charge coupling MOS transistor comprises: a storage MOS transistor comprising: wherein the physical size of the programming charge coupling MOS transistor is relatively large when compared to a physical size of the storage MOS transistor to establish a large coupling ratio between a bulk region, the source region, the drain region of the coupling MOS transistor and the floating gate node wherein the threshold voltage of the storage MOS transistor is set to an erased threshold voltage level to erase the nonvolatile memory cell and to a programmed threshold voltage level to program the nonvolatile memory cell.