Patent ID: 7550773
Filing Date: 2009-06-23
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a semiconductor fin located on a buried insulator layer of a semiconductor-on-insulator (SOI) substrate and having a width that is substantially the same throughout said semiconductor fin; source and drain regions disjoined from a top surface of said semiconductor fin; source and drain reach-through regions abutting said source and drain regions and said top surface of said semiconductor fin; a body separating said source and drain regions and abutting said top surface of said semiconductor fin; a body contact via abutting said body at said top surface of said semiconductor fin; source and drain contact vias abutting said source and drain reach-through regions; a gate dielectric located on two sidewalls of said body of said semiconductor fin; two disjoined portions of a gate conductor directly contacting said gate dielectric; two gate contact vias, each of which contacting one of said two disjoined portions of said gate conductor; dielectric spacers contacting said body, said source and drain reach-through regions, and said source and drain contact vias; two disjoined portions of a patterned gate cap abutting said body contact via and said two disjoined portions of said gate conductor; and a fin cap abutting said top surface of said semiconductor fin, said two disjoined portions of said patterned gate cap, said body contact via, and said source and drain contact vias and disjoined from said two disjoined portions of said gate conductor, wherein said body contact via is self aligned to an intersection of said semiconductor fin and said two disjoined portions of said gate conductor.