Patent ID: 6956435
Filing Date: 2005-10-18
Classification: H03F,H03G

Abstract:
1. A multiplication circuit comprising: first, second, third, fourth, fifth and sixth transistors each having a first terminal, a second terminal and a third terminal; and a variable impedance circuit, wherein said first terminal of said first transistor receives a first input signal, said second terminal of said first transistor is connected to a first potential through a first load and said third terminal of said first transistor is connected to said second terminal of said fifth transistor, said first terminal of said second transistor receives a second input signal, said second terminal of said second transistor is connected to said first potential through a second load and said third terminal of said second transistor is connected to said second terminal of said fifth transistor, said first terminal of said third transistor receives said second input signal, said second terminal of said third transistor is connected to said first potential through said first load and said third terminal of said third transistor is connected to said second terminal of said sixth transistor, said first terminal of said fourth transistor receives said first input signal, said second terminal of said fourth transistor is connected to said first potential through said second load and said third terminal of said fourth transistor is connected to said second terminal of said sixth transistor, said first terminal of said fifth transistor receives a third input signal and said third terminal of said fifth transistor is connected to a second potential through a third load, said first terminal of said sixth transistor receives a fourth input signal and said third terminal of said sixth transistor is connected to said second potential through a fourth load, and said variable impedance circuit includes: a plurality of first variable impedance devices serially connected between said third terminal of said fifth transistor and said third terminal of said sixth transistor, and at least one second variable impedance device that is connected between a node between said plurality of first variable impedance devices and said second potential and is turned on/off complementarily to said plurality of first variable impedance devices.