Patent ID: 6377093
Filing Date: 2002-04-23
Classification: G11C,H03L

Abstract:
An integrated circuit having a locking circuit for generating an internal clock signal in synchronization with an input reference clock signal, wherein the internal clock signal is a signal obtained when an initial internal clock signal at an output terminal of the locking circuit is delayed by a predetermined time for which the initial internal clock signal is transmitted from the output terminal to an input terminal of a circuit at a predetermined distance from the output terminal, the locking circuit comprising:an internal clock signal generator for (i) delaying the reference clock signal by a first delay time corresponding to the phase difference between the reference clock signal and a feedback signal that is controlled to have the same phase as that of the internal clock signal and (ii) generating the initial internal clock signal based on the delayed reference clock signal; a mirror delay circuit for (i) delaying the initial internal clock signal by a second delay time in response to a predetermined delay control signal group and (ii) generating the feedback signal; and a time-to-digital converter for generating the delay control signal group for controlling the mirror delay circuit to reduce the phase difference between the feedback signal and the internal clock signal.