Patent ID: 6178132
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A non-volatile memory device, comprising:an integrated circuit substrate;a first array of memory cells on the integrated circuit substrate;a first address decoder, coupled to the first array of memory cells, including circuits for selecting memory cells in the first array for access in response to addresses;a second array of memory cells on the integrated circuit substrate;a second address decoder, coupled to the second array of memory cells, including circuits for selecting memory cells in the second array for access in response to addresses;control logic and bias resources on the integrated circuit substrate, coupled to the first and second memory arrays, which execute a function to change data in one of the first and second arrays, and while executing said function, execute a read function for the other of the first and second array;a set of address inputs on the integrated circuit substrate;an address register. including an input and an output; andselector circuitry, including first circuits connected to the set of address inputs the input of the address register the first address decoder and the second address decoder and responsive to the control logic to connect the set of address inputs to a first selected target selected from targets including the input of the address register, the first address decoder and the second address decoder, and second circuits connected to the output of the address register, the first address decoder and the second address decoder and responsive to the control logic to connect the output of the address register to a second selected target selected from targets including the first address decoder and the second address decoder.