Patent ID: 6108266
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A memory, comprising:an address buffer having an input for receiving an address signal, a first output for providing a true address signal, a second output for providing complementary address signal, and a control input;a plurality of fuses for providing a delay program signal;a clock circuit having an input which receives an external clock and an output;a programmable pulse width circuit having a first input coupled to the output of the clock circuit, a second input for receiving the delay program signal, and an output coupled to the control input of the address buffer;word line drivers enabled in response to enable signals;sense amplifiers enabled in response to delayed enable signals; andprogrammable delay circuits which provide the delayed enable signals in response to the enable signals wherein the programmable delay circuits have a delay which is the same as a width of a pulse gene rated by the programmable pulse width circuit;wherein the address buffer causes both the true and complementary address signals to be at the same logic state in response to the control input being disabled.