Patent ID: 8477898
Filing Date: 2013-07-02
Classification: H03L

Abstract:
1. A phase-locked loop (PLL), comprising: a 1/N frequency divider, wherein N is an integer; a voltage-controlled oscillator (VCO) configured to receive a control voltage and generate an output clock signal of frequency f a programmable phase mixer coupled between an output of the VCO and an input of the 1/N frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f wherein the 1/N frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f a phase detector configured to receive a reference clock signal of frequency f a controller coupled to the programmable phase mixer, wherein the controller sends a control signal to the programmable phase mixer to control a phase offset produced by the programmable phase mixer; wherein the controller receives a control clock signal of frequency f