Patent ID: 7746116
Filing Date: 2010-06-29
Classification: H03K

Abstract:
1. A device comprising: a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element; and the CL element, wherein the output of the CL element is exclusively sensitized from at least one data input of the CL element by at least one control input of the CL element when each of the at least one control input of the CL element is in a first quiescence inducing condition with respect to the clock signal, wherein each of the at least one control input of the CL element does not change state between previous and current clock periods in the first quiescence inducing condition, wherein the first clock enable signal is generated, using the at least one data input of the CL element, the at least one control input of the CL element, and the clock signal, to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition, wherein each of the at least one data input of the CL element does not change state from the previous clock period to the current clock period in the second quiescence inducing condition.