Patent ID: 6157690
Filing Date: 2000-12-05
Classification: H03L,H04L

Abstract:
A digital phase locked loop (PLL) circuit comprising a phase comparator for comparing an internal clock signal against a reference clock signal to generate a phase lead/lag signal representing whether said internal clock signal leads or lags in phase with respect to said reference clock signal and a phase error signal representing a phase error between said internal clock signal and said reference clock signal, a delay controller for receiving said phase lead/lag signal to increment or decrement a delay control signal based on said phase lead/lag signal, a variable delay circuit for receiving said reference clock signal and said delay control signal to generate said internal clock signal having a phase delay based on said delay control signal with respect to said reference clock signal, and an enable signal generator for receiving said phase error signal to generate an enable signal for allowing or retarding said delay control signal based on said phase error to increment or decrement said delay control signal wherein said enable signal generator further receives said phase lead/lag signal, and said enable signal retards said delay control signal generator for a time length based on said phase error.