Patent ID: 6973558
Filing Date: 2005-12-06
Classification: G06F,H04L

Abstract:
1. An apparatus for buffering packet data in a micro-processor based packet data communications system, comprising: means for generating a byte-addressable netbuf having a list of logical memory addresses, each mapping a fixed-size physical memory location in a main memory device and in a secondary memory device, each fixed-size memory location having a physical memory address being mapped by two logical memory addresses; means for generating a set of pointers indicating the first logical memory address, the last logical memory address, and the logical memory address to be accessed of the byte-addressable netbuf; and means for managing the byte-addressable netbufs by modifying the set of pointers to process packet data in the fixed-size physical memory locations by indicating the logical memory addresses in the byte-addressable netbuf that map to the physical memory addresses of the fixed-size memory location.