Patent ID: 7468307
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor structure comprising: providing a semiconductor layer stack comprising a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor substrate and the buried layer, the monocrystalline semiconductor layer having an upper surface forming a surface of the semiconductor structure; forming a contact hole in the surface of the semiconductor structure so as to contact the buried layer, the contact hole having a first width and a first depth, the depth being measured from the surface of the semiconductor structure; forming an isolation trench in the surface of the semiconductor structure so as to laterally insulate different portions of the semiconductor structure, the isolation trench having a second width and a second depth, the depth being measured from the surface of the semiconductor structure; and selecting a ratio of the first to the second width in accordance to the desired ratio of the first to the second depth; wherein the isolation trench and the contact hole are formed simultaneously by one etching process.