Patent ID: 6388485
Filing Date: 2002-05-14
Classification: H03L

Abstract:
A delay-locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal, comprising:a phase comparator for comparing the phase of the external clock signal and the phase of a feedback signal and generating a detection signal corresponding to a phase difference between the external clock signal and the feedback signal, wherein the external clock signal is applied directly to the phase comparator; a delay controller for receiving the detection signal and generating a first delay control signal; a first digital delay part for delaying the external clock signal by a predetermined delay time in response to the first delay control signal and then generating the feedback signal, wherein the external clock signal is applied directly to the first digital delay part; a digital filter for removing a high frequency component from the first delay control signal and generating a second delay control signal; and a second digital delay part for delaying the external clock signal by the predetermined delay time in response to the second control signal and generating the internal clock signal.