Patent ID: 6301187
Filing Date: 2001-10-09
Classification: G11C

Abstract:
A synchronous semiconductor memory device receiving an address signal and a control signal, and exchanging storage data in synchronism with an externally applied clock signal, comprising:a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, said memory cell array being divided into a plurality of memory cell blocks;an internal synchronizing signal generation circuit for outputting an internal clock signal in synchronism with said externally applied clock signal;an address signal input circuit for externally receiving said address signal in synchronism with said internal clock signal;an address bus provided commonly to said plurality of memory cell blocks for transmitting said address signal from said address signal input circuit; anda plurality of selecting circuits provided corresponding to said memory cell blocks, each for selecting a memory cell row and a memory cell column in a corresponding memory cell block based on said address signal from said address bus,said selecting circuit being activated in response to a selection of the corresponding memory cell block based on said address signal.