Patent ID: 7324405
Filing Date: 2008-01-29
Classification: G11C,H03K,H03M

Abstract:
1. An integrated circuit comprising: a first flip-flop coupled to a pad to receive an input signal; a second flip-flop coupled to the pad to receive the input signal; a third flip-flop coupled to receive a control signal; and a combinatorial logic gate having a first input coupled to receive a clock signal and a second input coupled to an output of the third flip-flop, and further having an output coupled to a clock input of the first flip-flop, a clock input of the second flip-flop, and a clock input of the third flip-flop, wherein the first flip-flop is clocked by rising edges of a signal at the output of the combinatorial logic gate and the second flip-flop is clocked by falling edges of the signal at the output of the combinatorial logic gate.