Patent ID: 6081469
Filing Date: 2000-06-27
Classification: G11C,H01L

Abstract:
In combination with a semiconductor memory configuration having a memory cell array with bit lines, a combined precharging and homogenizing circuit for the semiconductor memory configuration, the combined precharging and homogenizing circuit comprising:a first field-effect precharging transistor having a gate, a source and a drain;a second field-effect precharging transistor having a gate, a source and a drain;a homogenizing transistor having a gate, a source and a drain, and connected in series between said first field-effect precharging transistor and said second field-effect precharging transistor;said gate of said first field-effect precharging transistor, said gate of said second field-effect precharging transistor and said gate of said homogenizing transistor connected together forming a common gate, said common gate angled and rotated through about 45.degree. in relation to a longitudinal direction of the bit lines;said source of said first field-effect precharging transistor and said source of said second field-effect precharging transistor connected together forming a common source;said drain of said first field-effect precharging transistor and said drain of said homogenizing transistor connected together forming a common drain;said source of said homogenizing transistor and said drain of said second field-effect precharging transistor connected together forming a common source/drain;said common drain and said common source/drain being drawn forward beyond said common gate defining protruding regions; andbit line contacts disposed in said protruding regions.