Patent ID: 8786349
Filing Date: 2014-07-22
Classification: H03K

Abstract:
1. A semiconductor device comprising: a first wiring; a first switch comprising a first terminal and a second terminal; the first terminal of the first switch being electrically connected to the first wiring; a second switch comprising a first terminal and a second terminal, the first terminal of the second switch being electrically connected to the second terminal of the first switch; a second wiring electrically connected to the second terminal of the second switch; a capacitor comprising a first electrode and a second electrode, the first electrode being electrically connected to the second terminal of the first switch; a third switch comprising a first terminal and a second terminal, the first terminal being electrically connected to the second electrode of the capacitor; a third wiring electrically connected to the second terminal of the third switch; a transistor comprising a gate, a first terminal, and a second terminal, the gate being electrically connected to the second electrode of the capacitor and to the first terminal of the third switch, and the first terminal being electrically connected to the third wiring; and a fourth wiring electrically connected to the second terminal of the transistor, wherein an input signal is input to the second terminal of the second switch, wherein the third wiring is configured to be set at a high power supply potential, wherein the fourth wiring is configured to be set at a low power supply potential, wherein the first wiring is configured to be set at a potential lower than the high power supply potential and higher than the low power supply potential, and wherein the second electrode of the capacitor, the first terminal of the third switch, and the gate of the transistor are directly connected to a same electrical node.