Patent ID: 8847407
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A structure of an output stage, comprising: a first electrode; a second electrode; a third electrode; a plurality of first auxiliary electrodes, disposed between the first electrode and the second electrode and connected to the first electrode, wherein a width of each of the first auxiliary electrodes is inversely proportional to a distance thereof from the first electrode; a plurality of second auxiliary electrodes, disposed between the first electrode and the second electrode and connected to the second electrode, wherein a width of each of the second auxiliary electrodes is inversely proportional to a distance thereof from the second electrode; a plurality of third auxiliary electrodes, disposed between the second electrode and the third electrode and connected to the second electrode, wherein a width of each of the third auxiliary electrodes is inversely proportional to a distance thereof from the second electrode; a plurality of fourth auxiliary electrodes, disposed between the second electrode and the third electrode and connected to the third electrode, wherein a width of each of the fourth auxiliary electrodes is inversely proportional to a distance thereof from the third electrode; a first switching unit, wherein the first auxiliary electrodes and the second auxiliary electrodes are electrically connected to each other respectively through the turned-on first switching unit; meanwhile, wherein a plurality of first currents flow through the turned-on first switching unit, and a first flowing direction of the first currents in the turned-on first switching unit is from the first electrode to the second electrode, wherein the first switching unit comprises at least a PMOS-type transistor, each of the PMOS-type transistors comprises a plurality of first source electrodes and a plurality of first drain electrodes, the first source electrodes and the first drain electrodes are extended beyond the corresponding first auxiliary electrode and the corresponding second auxiliary electrode from the first electrode to the second electrode, the first source electrodes are connected to the first electrode, the first drain electrodes are connected to the second electrode, each of first auxiliary electrode is connected to the corresponding first source electrodes, and each of second auxiliary electrode is connected to the corresponding first drain electrodes; and a second switching unit, wherein the third auxiliary electrodes and the fourth auxiliary electrodes are electrically connected to each other respectively through the turned-on second switching unit; meanwhile, wherein a plurality of second currents flow through the turned-on switching unit, and a second flowing direction of the second currents in the turned-on second switching unit is from the second electrode to the third electrode, wherein the second switching unit comprises at least a NMOS-type transistor, each of the NMOS-type transistors comprises a plurality of second source electrodes and a plurality of second drain electrodes, the second source electrodes and the second drain electrodes are extended beyond the corresponding third auxiliary electrode and the corresponding fourth auxiliary electrode from the second electrode to the third electrode, the second drain electrodes are connected to the second electrode, the second source electrodes are connected to the third electrode, each of third auxiliary electrode is connected to the corresponding second drain electrodes, and each of fourth auxiliary electrode is connected to the corresponding second source electrodes.