Patent ID: 8159057
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a wiring substrate having an upper surface on which a plurality of bonding leads are formed, and a lower surface on which a plurality of lands are formed, wherein the lower surface opposes to the upper surface; a semiconductor chip having a main surface on which a plurality of pads are formed, and mounted over the upper surface of the wiring substrate; a plurality of conductive members electrically coupling the pads of the semiconductor chip and the bonding leads of the wiring substrate; and a plurality of external terminals coupled to the lands of the wiring substrate, respectively, wherein the wiring substrate includes a core material having an upper surface positioned on the upper surface side of the wiring substrate and a lower surface positioned on the lower surface side of the wiring substrate, wherein the wiring substrate is a multilayer wiring substrate in which a plurality of wiring layers and a plurality of insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material, wherein the bonding leads are formed of part of the uppermost wiring layer of the wiring layers, wherein the lands are formed of part of the lowermost wiring layer of the wiring layers, wherein the core material is a first insulating layer containing fiber and resin, wherein the insulating layers include second insulating layers containing fiber and resin, and third insulating layers, wherein content of fiber in each of the third insulating layers is smaller than that of each of the first insulating layer and the second insulating layers, wherein the second insulating layers are formed on the upper surface side and on the lower surface side of the core material, wherein the third insulating layers are formed on the upper surface side and on the lower surface side of the core material via the second insulating layers, wherein the uppermost wiring layer and the lowermost wiring layer are formed over the third insulating layers, respectively, wherein three of the wiring layers are formed on the upper surface side and on the lower surface side of the core material, wherein the thickness of the first insulating layer is larger than the thickness of the second insulating layers, and wherein the thickness of the second insulating layers is larger than the thickness of the third insulating layers.