Patent ID: 9007861
Filing Date: 2015-04-14
Classification: G11C,H03L

Abstract:
1. A semiconductor device, comprising: a clock generating circuit that generates an internal clock signal based on an external clock signal, wherein the clock generating circuit includes: wherein the phase-controlling unit includes a frequency dividing circuit that divides the external clock signal to generate a divided clock signal, the phase control value being updated in response to the divided clock signal, wherein the phase-controlling unit has a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, wherein the mode switching unit is responsive to a trigger signal to cause the phase-controlling unit to transition from the second operation mode to the first operation mode, and the mode switching unit changes the phase-controlling unit from the first operation mode to the second operation mode in response to a state where the internal clock signal attains a predetermined phase, and wherein the trigger signal is generated in response to an output signal of a power detecting circuit of the semiconductor device.