Patent ID: 6311313
Filing Date: 2001-10-30
Classification: G06F

Abstract:
A clock distribution network, comprising:one or more primary inputs for accepting one or more primary clock signals;a tree coupled to the one or more primary inputs, the tree deriving separate clock signals from the one or more primary clock signals and including N levels of sub-trees where N is greater than 1, wherein the separate clock signals are produced at tree end points and wherein a number of said tree end points for level N is greater than the number of clock signals for level N-1;one or more repower drivers buffering the separate clock signals between any two levels of trees;an X-Y grid vertically and horizontally connecting all the tree end points; wherein no drivers are used at connection points of the tree end points to the X-Y grid; andlocal distribution wiring, coupled to the X-Y grid, distributing a clock signal on the X-Y grid to one or more clock pin locations.