Patent ID: 6462745
Filing Date: 2002-10-08
Classification: G06F,G09G

Abstract:
A computer system, said computer system comprising:a central processing unit connected to a host bus; a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of said plurality of bytes of storage has a unique address; a first memory controller connected to said host bus, said first memory controller connected to a first portion of said system memory; a second memory controller connected to said host bus, said second memory controller connected to a second portion of said system memory; a bus connecting a peripheral components interconnect (PCI) device to said first memory controller and to said host bus, said PCI device being controlled by a driver; and a memory bank allocation table, said memory bank allocation table capable of containing said unique addresses of said first portion of said system memory; wherein said driver references said memory bank allocation table in order to determine a range of said system memory connected to said first memory controller to permit said driver to allocate some of said first portion of said system memory.