Patent ID: 6764950
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of fabricating a semiconductor integrated circuit device comprising:(a) forming a first insulating film over a first major surface of a wafer; (b) forming a groove in the first insulating film and a hole connected to a bottom surface of the groove in the first insulating film; (c) forming a barrier metal film over inner surfaces of the groove and the hole, and over an upper surface of the first insulating film; (d) forming a copper seed layer over the barrier metal layer inside and outside the groove and the hole by copper sputtering with a copper target having a purity of 99.999% or more; (e) forming a copper film containing copper as its principal component on the copper seed layer inside and outside the groove and the hole by electroplating so as to fill the groove and the hole; (f) removing the barrier metal film, the copper seed layer, and the copper film formed on the copper seed layer outside the groove and the hole so as to leave a cooper interconnection in the groove and the hole, thereby exposing the first insulating film; (g) performing an ammonia plasma treatment to the exposed surface of the first insulating film and an upper surface of the copper interconnection; and (h) forming an insulating barrier film on the exposed surface of the first insulating film and the upper surface of the copper interconnection by plasma CVD, wherein the total concentration of components other than copper in the copper interconnection, when step (h) is completed, does not exceed 0.8 At %, and wherein the film thickness of the thinnest part of the barrier metal film in the groove and the hole is less than 10 nm.