Patent ID: 9124247
Filing Date: 2015-09-01
Classification: H03H,H03M

Abstract:
1. A semiconductor device comprising: a decimation filter that sequentially inputs a signal sampled at a predetermined sampling rate, performs predetermined filtering processing on an input signal, and converts a resulting signal to a signal based on a required sampling rate to output the resulting signal, wherein the decimation filter calculates, for the each input signal that is input within a predetermined period, a filter coefficient for performing predetermined filtering processing in response to a trigger signal continuously applied, sequentially multiplies the input signal by the calculated filter coefficient, and furthermore accumulates a multiplication value within the predetermined period and sequentially outputs the resulting value, wherein the predetermined period is made variable in accordance with a time interval at which the trigger signal is applied, wherein the decimation filter includes: wherein the coefficient calculation unit, in a first period after the trigger signal is applied, sequentially calculates the filter coefficient so that a value increases in accordance with a number of times when the input signal is input after the trigger signal is applied, while in a second period after the trigger signal is applied, the coefficient calculation unit sequentially calculates the filter coefficient so that the value decreases in accordance with a number of times when the input signal is input after the trigger signal is applied, wherein the arithmetic unit sequentially outputs a value obtained by accumulating the multiplication value from the time when the first period is started to the time when the second period ends, and wherein the coefficient calculation unit sets the first period and the second period that are each a period that is shorter than a cycle corresponding to the required sampling rate and is a predetermined period.