Patent ID: 6596549
Filing Date: 2003-07-22
Classification: G06F,H01L

Abstract:
An automatic wiring method for a semiconductor package by use of a CAD system, wherein bonding pads to b connected to semiconductor chips and vias round the bonding pads are disposed on a virtual plane, and a wiring pattern is formed by connecting the bonding pads to the vias, the method comprising:a provisional wiring step for sequentially specifying a first line of a terminal to an n-th line of the terminal, that is from the innermost periphery to the outermost periphery, of the bonding pads, connecting the bonding pads to predetermined vias present on the specified line of the terminal with line segments, and provisionally determining a wiring route for each line of the terminal such that the line segment asses through between the vias at equal intervals.