Patent ID: 6774690
Filing Date: 2004-08-10
Classification: G11C,H03L

Abstract:
A circuit comprising:a first delay line for applying a first delay to an input signal to produce a first delayed signal; a first phase detector connected to the first delay line for comparing the input signal and a feedback signal to produce first shifting signals; a first shift register connected to the first phase detector for adjusting the first delay based on the first shifting signals, the first shift register including a number of register cells, each connecting to multiple delay cells of the first delay line; a second delay line connected to the first delay line for applying a second delay to the first delayed signal to produce a second delayed signal; a second phase detector connected to the second delay line for comparing the input signal and the feedback signal to produce second shifting signals; and a second shift register connected to the second phase detector for adjusting the second delay based on the second shifting signals.