Patent ID: 6740924
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A semiconductor integrated circuit device, comprising:memory cells; a semiconductor substrate; and memory cell selecting MISFETs formed on a principal plane of the semiconductor substrate and provided with gate electrodes that are integrally formed with word lines extending in a first direction of the principal plane, wiring grooves formed in a first insulating film over the memory cell selecting MISFETs, the wiring grooves extending in a second direction intersecting the first direction and having a second insulating film formed on side walls thereof, bit lines formed inside the wiring grooves and electrically connected to one of sources and drains of the memory cell selecting MISFETs, and data storing capacitors formed over the bit lines and electrically connected to the other one of the sources and drains, wherein the bit lines are comprised of a first conductive film containing tungsten as a principal component, and an adhesive layer comprised of a second conductive film that has a higher adhesive strength to the second insulating film than the tungsten that is formed on a boundary face between the second insulating film inside the wiring grooves and the first conductive film, and wherein each of the wiring grooves extends in the second direction over the memory cells.