Patent ID: 9158726
Filing Date: 2015-10-13
Classification: G06F,Y02D

Abstract:
1. A method of operating a memory system, the method comprising: receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, the buffer device being coupled to a memory controller, the memory controller being coupled to a plurality of DIMM devices consisting of DIMM transferring an ODT (On Die Termination) signal from the CPU to a command port of the buffer device; and providing a termination array value and a timing information for a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface, while maintaining all of the DIMM devices in a termination state other than the DIMM device being read or write to prevent any other signal from traversing to the common data bus interface, wherein the providing is not based upon the ODT signal.