Patent ID: 8558317
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A semiconductor device serving as an inverter, comprising: a first island-shaped semiconductor layer; a second semiconductor layer; a gate electrode at least a part of which is between the first island-shaped semiconductor layer and the second semiconductor layer; a first gate insulating film at least a part of which is between the first island-shaped semiconductor layer and a first surface of the gate electrode and is in contact with at least a part of the periphery of the first island-shaped semiconductor layer and a surface of the gate electrode; a second gate insulating film between the second semiconductor layer and a second surface of the gate electrode opposite to the first surface and in contact with the second semiconductor layer and the second surface of the gate electrode, the second semiconductor layer contacting only a portion of the second gate insulating film opposite to the gate electrode, wherein the second semiconductor layer has an arc shape and less area than a side of the first island-shaped semiconductor layer in proximity to the first surface of the gate electrode via the first gate insulating film; a first first-conductive-type semiconductor layer on the top of the first island-shaped semiconductor layer; a second first-conductive-type semiconductor layer on the bottom of the first island-shaped semiconductor layer and having a polarity identical to that of the first first-conductive-type semiconductor layer; a first second-conductive-type semiconductor layer on the top of the second semiconductor layer and having a polarity opposite to that of the first first-conductive-type semiconductor layer; and a second second-conductive-type semiconductor layer on the bottom of the second semiconductor layer and having a polarity opposite to that of the first first-conductive-type-semiconductor layer, wherein the second first-conductive-type semiconductor layer contacts the second second-conductive-type semiconductor layer at an interface below the gate electrode.