Patent ID: 7263011
Filing Date: 2007-08-28
Classification: G11C

Abstract:
1. A memory circuit having a data input and a data out-put, comprising: a main memory block having a data input and a data output and comprising at least one complete memory array of memory cells being connected to wordlines and bitlines, with the memory cells being addressable via an address signal; a substitution memory block for the substitution of memory cells within the main memory block, having at least one data input and at least one data output and comprising a plurality of substitution memory cells; wherein the substitution memory block is external to the main memory block and arranged to substitute at least one bitline-related set of memory cells being connected to the same bitline in one memory array of the main memory block; and a redirection circuit for redirecting access to a memory cell of the at least one respective substituted bitline-related set of memory cells in the main memory block to the substitution memory block, wherein the redirection circuit comprises: