Patent ID: 6083829
Filing Date: 2000-07-04
Classification: C23C,H01L

Abstract:
A method for forming a metal interconnect structure, on a semiconductor substrate, comprising the steps of:providing a insulator layer, on said semiconductor substrate, with openings in said insulator layer, exposing underlying conductive elements;depositing a barrier layer;depositing a germanium layer;depositing a copper layer;annealing to form a Cu.sub.3 Ge, intermetallic layer, between a top portion of said copper layer, and said barrier layer, with the formation of said intermetallic layer consuming all of said germanium layer, and consuming a bottom portion of said copper layer; andpatterning of said top portion of said copper layer, of said Cu.sub.3 Ge intermetallic layer, and of said barrier layer, via dry etching procedures, or via a copper chemical mechanical polishing procedure, to form said metal interconnect structure.