Patent ID: 7781250
Filing Date: 2010-08-24
Classification: B81B,B81C,H01L

Abstract:
1. A method for fabricating a wafer level chip size package for MEMS devices comprising: providing a substrate wafer having formed thereon MEMS dies, with a plurality of compatible pads disposed at the periphery of each of said MEMS dies on the substrate wafer; providing a cap substrate, spin coating photo sensitive BCB on said cap substrate, then form a plurality of cavity walls by lithography, the position of each cavity wall is corresponding to that of the MEMS die; aligning and bonding the substrate wafer with the cap substrate; thinning the substrate wafer by backside grinding, notching to remove most of the substrate wafer material at scribe lines; plasma etching at the backside of the substrate wafer to remove the rest of the substrate wafer material and expose part of the compatible pads, trenches being formed; filling the trenches with insulating materials to cover the exposed compatible pads, spin coating this insulating material on the backside of the substrate wafer as a first insulating layer; notching again to expose flanks of the compatible pads; depositing a metal layer on the backside of the substrate wafer by sputtering, forming redistribution leads by lithography and plating; spin coating a photo sensitive second insulating layer to cover the redistribution leads, making openings by lithography for solder bump forming; forming solder bumps at the openings of the second insulating layer by screen printing, each solder bump corresponding to a compatible pad; and dicing the substrate wafer along the scribe lines to singulate the MEMS dies therefrom.