Patent ID: 7505296
Filing Date: 2009-03-17
Classification: G11C

Abstract:
1. A semiconductor device comprising an input/output circuit arranged to connect a first group of signal lines and a second group of signal lines, a first register, an encoder, an entry compressor and a memory array, wherein the input/output circuit outputs a first information or a second information to the second group of signal lines, the first register holds the first information, the encoder outputs a third information encoded based on the first and second information received through the second group of signal lines to a third group of signal lines, the entry compressor receives a plurality of the third information sequentially inputted through the third group of signal lines and performs logical operation to generate a fourth information and outputs the fourth information to a fourth group of signal lines, and the memory array stores the fourth information inputted through the fourth group of signal lines and compares the fourth information with the third information through the third group of signal lines.