Patent ID: 6487263
Filing Date: 2002-11-26
Classification: H04L

Abstract:
A digital circuit for generating a signal in phase synchronization with a biphase modulated digital input signal, the digital circuit comprising:a controlled frequency divider for outputting a phase synchronized signal based upon a master clock signal having a frequency higher than a maximum frequency of the biphase modulated digital input signal; a first detection circuit for generating a first control signal responsive to detection of a triplet sequence comprising 001 or 110 of sampled values of the biphase modulated digital input signal with the master clock signal; and a second detection circuit for generating a second control signal responsive to detection of a triplet sequence comprising 011 or 100 of the sampled values of the biphase modulated digital input signal with the master clock signal; the first and second control signals enabling or disabling switching of an output of said controlled frequency divider.