Patent ID: 7485510
Filing Date: 2009-02-03
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor structure comprising: forming within a semiconductor layer a V shaped notch, said forming comprises a crystallographically specific etchant; forming a first gate dielectric upon the V shaped notch and forming a first gate electrode upon the first gate dielectric; inverting the semiconductor layer to provide a first planar surface and a second interface opposite the first planar surface and including an inverted V shaped notch, said inverting including laminating a handling substrate over the interface including the V shaped notch; forming a second gate dielectric and a second gate electrode over the first planar surface and aligned with the inverted V shaped notch; forming a pair of source/drain regions within the semiconductor layer and separated by the inverted V shaped notch, wherein the pair of source/drain regions is raised with respect to the first gate electrode.