Patent ID: 8982605
Filing Date: 2015-03-17
Classification: G11C,H01L

Abstract:
1. A phase change memory device comprising: a semiconductor substrate having peripheral areas and a cell area therebetween; first and second word line select switches on an upper part of the semiconductor substrate in the peripheral areas; first word lines electrically connected to the first word line select switches, the first word lines on the upper part of the semiconductor substrate on which the first word line select switches are formed; first diodes on the upper parts of the first word lines; second word lines on the upper parts of the first diodes; second diodes on the upper parts of the second word lines correspondingly aligned over the first diodes; heating electrodes correspondingly coupled to upper parts of the second diodes; phase change patterns correspondingly coupled to upper parts of the heating electrodes; and bit lines correspondingly coupled to upper parts of the phase change patterns.