Patent ID: 6925133
Filing Date: 2005-08-02
Classification: H04B,H04L

Abstract:
1. A demodulator for demodulating a set of S possible orthogonal modulation codes received serially as binary data, wherein each of said orthogonal modulation codes comprises M binary bits representing an N-bit data symbol and wherein M=2 N , said demodulator comprising: a Logic 0 input detector capable of comparing each of said M binary bits of said serially received orthogonal modulation codes to a Logic 0 and outputting a +1 signal if a match occurs and outputting a −1 signal if a match does not occur; a summation circuit comprising S accumulators; a Logic 0 switch array comprising S switches, wherein a Kth one of said S switches in said Logic 0 switch array is capable of coupling an output of said Logic 0 input detector to a first input of a Kth one of said S accumulators; a storage array capable of storing said S orthogonal modulation codes; and control circuitry capable of synchronously applying the M bits in a Kth one of said S orthogonal modulation codes in said storage array as a switch control signal to said Kth switch in said Logic 0 switch array so that each Logic 0 binary data in said Kth orthogonal modulation code closes said Kth switch in said Logic 0 switch array, thereby connecting the output signal of said Logic 0 input detector to said first input of said Kth accumulator.