Patent ID: 6274421
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method of forming a MOS transistor on a substrate of single crystal silicon, comprising:forming a silicon device area in the substrate;implanting doping impurities of a first type in the silicon device area to form a conductive channel of a first type for use as a gate region;forming an insulation region boundary on each side of the device area;forming a layer of silicon oxide inside of the insulation region boundary on the substrate;depositing a layer of silicon nitride to a thickness of about 300 nm to 700 nm over the silicon oxide layer;etching the silicon nitride layer and the silicon oxide layer to form a stacked layer having sidewalls, said stacked layer including a silicon nitride plug and silicon oxide over the gate region;depositing a layer of silicon oxide over the substrate, insulation region boundary and the stacked layer to a thickness of between about 50 nm to 200 nm;etching the silicon oxide to form spacers about the sidewalls of the stacked layer;implanting ions of a second type in said substrate to form conductive layers of a second type for use as a source region and a drain region;depositing a layer of silicon oxide to a thickness of between about 1.5 to 2.0 times that of the stacked layer over the insulation region boundary, the conductive layers of the second type and the stacked layer;planarizing the structure to expose the upper surface of the silicon nitride plug;selectively etching the structure to remove the silicon nitride plug, thereby forming an electrode receiving structure for a gate electrode;depositing a layer of electrode metal to form a metal gate; andplanar etching the structure.