Patent ID: 6342816
Filing Date: 2002-01-29
Classification: H03F

Abstract:
A cascode circuit comprising:a first transistor having respective source, drain and gate terminal, said first transistor gate terminal coupled to an input signal referenced to a first power supply and said first transistor source terminal coupled to said first power supply; a second transistor having respective source, drain and gate terminal; said second transistor source terminal and said first transistor drain terminal coupled to form a first source-drain connection; a first cascode circuit output terminal coupled to a second power supply voltage; first circuit means for biasing said second transistor gate terminal with respect to said first power supply such that said first transistor operates in a saturation operating region; and a voltage limiting circuit interposed between said first output terminal and said second transistor drain adapted to limit a respective first drain-to-source voltage across said first transistor and a respective second drain-to-source voltage across said second transistor not to exceed a corresponding first maximum drain-to-source voltage limit and a corresponding second maximum drain-to-source voltage limit, the voltage limiting circuit comprising a third transistor having respective source, drain and gate terminals, said third transistor drain being coupled to said output terminal, said third transistor source being coupled to said second transistor drain and said third transistor gate being coupled to a selected, substantially fixed voltage.