Patent ID: 6307480
Filing Date: 2001-10-23
Classification: G06F,H03K

Abstract:
A reset circuit for use in an integrated circuit, the reset circuit comprising:an oscillator circuit having an oscillator disable input;a battery monitor arranged to detect that a charge level of the battery has fallen below a predetermined charge level and having an output for indicating a charge state of a battery;a watchdog timer having an output for indicating an operational state of software operating on the integrated circuit; andreset logic circuitry coupled to receive the battery monitor output and the watchdog timer output and having an oscillator disable output coupled to the oscillator disable input and a reset signal output, the reset logic circuitry being configured and arranged to generate an oscillator disable signal on the oscillator disable output to disable the oscillator when both the battery monitor output and the reset signal output are active, and the reset logic circuitry further configured and arranged to generate the reset signal output if the battery monitor output or the watchdog timer output is active.