Patent ID: 6642871
Filing Date: 2003-11-04
Classification: H03M

Abstract:
An analog/digital converter comprising an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit, wherein each of said stages includes:a sub-analog/digital converter for outputting a segment number corresponding to the level of a first analog signal; a sub-digital/analog converter for outputting a second analog signal corresponding to said segment number; and an amplifier circuit for adding said second analog signal to said first analog signal to produce a sum analog signal and amplifying said sum analog signal at a predetermined gain, and wherein said digital conversion unit includes: digital-value storage registers, which are each provided for one of said stages, each of said registers used for storing a digital value completing error correction for a segment and being adapted to output said digital value that corresponds to said segment number, an addition-processing unit for summing up said digital values output for all said stages from said specific digital-value storage registers to output digital-converted data; and an error-computation control unit for controlling said stages so that a specific one of said stages inputs an error computation analog, signal when said digital value stored in said digital-value storage registers corresponding to said specific stage is to be corrected, computing an error of said specific stage on the basis of said digital-converted data computed by said addition-processing unit which sums up said digital values on the basis of said error computation analog signal output by said digital-value storage registers, in accordance with said segment numbers received from all said stages following said specific stage and updating said digital values stored in said digital-value storage registers associated with all said stages following said specific stage in order to cancel said error of said specific stage.