Patent ID: 8723585
Filing Date: 2014-05-13
Classification: G09G,H03K

Abstract:
1. A level shift circuit, characterized in that, the level shift circuit comprising: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module; wherein, the first level shift module comprises: a first transistor having a gate connected to the first signal output terminal and a source connected to a low-voltage ground reference voltage source; a second transistor having a gate connected to its drain and a source connected to a high-voltage reference voltage source; a third transistor having a gate connected to the gate of the second transistor, a source connected to the high-voltage reference voltage source, and a drain connected to the drain of the first transistor and the first signal output terminal; a fourth transistor having a gate connected to a second complementary signal input terminal for inputting a second complementary signal and a drain connected to the drain of the second transistor, wherein the second complementary signal is complementary to the second input signal; a first clamping module having one end connected to the high-voltage reference voltage source and the other end connected to the drain of the first transistor; a first current limiting module having one end connected to the source of the fourth transistor and the other end connected to the low-voltage ground reference voltage source; the second level shift module comprises: a fifth transistor having a gate connected to the second signal output terminal and a source connected to a low-voltage reference voltage source; a sixth transistor having a gate connected to its drain and a source connected to a high-voltage ground reference voltage source; a seventh transistor having a gate connected to the gate of the sixth transistor, a source connected to the high-voltage ground reference voltage source, and a drain connected to the drain of the fifth transistor and the second signal output terminal; an eighth transistor having a gate connected to a first complementary signal input terminal for inputting a first complementary signal and a drain connected to the drain of the sixth transistor, wherein the first complementary signal is complementary to the first input signal; a second clamping module having one end connected to the high-voltage ground reference voltage source and the other end connected to the drain of the fifth transistor; a second current limiting module having one end connected to the source of the eighth transistor and the other end connected to the low-voltage reference voltage source.