Patent ID: 6101587
Filing Date: 2000-08-08
Classification: G06F

Abstract:
In a semiconductor memory device which includes a first decoder for decoding a row address signal and selecting a word line, a second decoder for decoding a column address signal and selecting a bit line, and a memory cell array for writing and reading data to and from memory cells therein in accordance with word line and bit line selection signals outputted respectively from the first decoder and the second decoder, a data protection circuit, comprising:an address conversion unit for executing a program in accordance with a user's program so as to output a stored data value, converting an externally applied address signal in accordance with the stored data value, and outputting the converted address signal, andan address selection unit for comparing the stored data value inputted from the address conversion unit with a user data value, and selectively outputting the converted address signal inputted from the address conversion unit or the externally applied address signal in accordance with the compared resultant value.