Patent ID: 6272659
Filing Date: 2001-08-07
Classification: H03M

Abstract:
An error correction code (ECC) processor for correcting errors in binary data of an ECC codeword, including a plurality of ECC redundancy symbols for correcting a maximum number of correctable errors in the ECC codeword, read from a disc storage medium, the ECC codeword comprising a first and a second set of intersecting ECC codewords of a multi-dimensional code wherein the error correction code processor processes the first and second sets of ECC codewords in iterative error correction passes, the ECC processor comprising:(a) a data buffer for storing the binary data read from the disc storage medium;(b) a syndrome generator for generating ECC syndromes in response to the ECC codeword, the ECC syndromes used to determine a number of detected errors in the ECC codeword;(c) an error limit controller for generating an enable signal if the number of detected errors in the ECC codeword is greater than zero and less than an adjustable limit value being less than the maximum number of correctable errors in the ECC codeword, the error limit controller increasing the adjustable limit value if a first predetermined criteria is satisfied after an error correction pass; and(d) an error corrector enabled by the enable signal for generating correction values in response to the ECC syndromes, the correction values for correcting the detected errors in the ECC codeword.