Patent ID: 8788792
Filing Date: 2014-07-22
Classification: G06F

Abstract:
1. A multi-instruction set architecture (ISA) computer system, comprising: a computer program including instructions of a first ISA, the first ISA having a first complexity; a first processor configured to execute instructions of the first ISA; a second processor configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity; wherein the ISA is indicated in the computer program by one bit in each page of instructions in the computer program; a profiler configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA; and a translator configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.