Patent ID: 9194915
Filing Date: 2015-11-24
Classification: G01R

Abstract:
1. A control test point (CTP) of an integrated circuit (IC) scan chain, the CTP comprising: a first integrated clock gate (ICG) of the IC scan chain CTP, the first ICG having a clock input, a gated clock output, a functional enable (FE) input, and a first scan enable (SE) input, the first ICG configured to operate, in response to an active state of the first SE input, in a serial scan mode that allows the gated clock output to change in response to data received by the first SE input during a serial scan operation, the first ICG further configured to operate in response to an inactive state of the first SE input, in a scan capture mode in which the gated clock output is, in response to the FE input being held at a low logic level, inhibited from changing during a scan capture operation; and a scan latch having a second clock input coupled to the gated clock output of the first ICG, the scan latch further having a data output, the scan latch configured to hold the data output at a fixed logic level in response to the gated clock output of the first ICG being inhibited from changing during the scan capture operation.