Patent ID: 6337254
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method, of fabricating a device isolation structure for a semiconductor device, comprising:forming plural dummy active regions adjacent to at least one active region of a semiconductor substrate of the semiconductor device; and filling trenches located between each dummy active region and between an outer dummy active region and the active region adjacent thereto with a filling layer; the method further comprising: sequentially forming a first insulation layer and a first conduction layer on the semiconductor substrate in which a field isolation region and an active region are defined, the field isolation region including a plurality of dummy active regions; etching and patterning the first insulation layer and the first conduction layer to form a mask and to expose an upper portion of the semiconductor substrate on which a plurality of trenches will be formed; forming the plurality of trenches by etching the exposed semiconductor substrate using the patterned first insulation layer and first conduction layer as a mask; forming a gate insulation layer on the semiconductor substrate and the filling layer located in the plurality of trenches; and forming a second conduction layer on the gate insulation layer, N-type impurity or P-type impurity being discriminately doped by ion implantation into the second conduction layer which corresponds to the active region, wherein the filling of trenches comprises: forming the filling layer on the first conduction layer and in the plurality of trenches; etching the filling layer until an upper portion of the first conduction layer is exposed; and removing the mask by removing the first insulation layer and the first conduction layer, leaving the filling layer in the trenches.