Patent ID: 7797574
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. A method for cryptographically protecting against possible fault injections during an execution of a calculation, the calculation comprising operations successively performed by a sequence of hardware cells of a same electronic element, the method comprising: starting a first execution of the calculation in a first hardware cell; prior to completing the first execution of the calculation, starting a second execution of the same calculation in the first hardware cell, the second execution started once the first execution has freed the first hardware cell and goes on in a second hardware cell; synchronizing the executions so that the second execution uses each intermediate hardware cell in the sequence only when the first execution has passed from said intermediate hardware cell to a next hardware cell in the sequence; and verifying, after the end of the first and second executions, the identity between a first result produced by the first execution and a second result produced by the second execution.