Patent ID: 8521968
Filing Date: 2013-08-27
Classification: G06F

Abstract:
1. A memory controller providing a plurality of write ports that allow shared access to at least one memory device, the memory controller comprising: a plurality of write ports, at least one of the write ports having a clock frequency and comprising: a data buffer having a plurality of storage locations, wherein said data buffer is configured to allow data of a first bit width to be written to at least a first number of its storage locations at a pre-determined time; an address buffer having a plurality of address locations, the address buffer being configured to allow addresses to be written to a first number of its address locations; and an address translator configured to translate an address associated with data written to a storage location in the data buffer from an address space of the write port to an address space of at least one memory device, such that an address contained in a given address location in the address buffer relates to a memory address of at least one memory device to which data held in a corresponding storage location of the data buffer of the write port is to be written,