Patent ID: 8441883
Filing Date: 2013-05-14
Classification: G06F,G11C

Abstract:
1. A memory arrangement having a plurality of memory elements, the elements being associated with a memory space which can be addressed in a row and column fashion during a write or a read access, the memory arrangement comprising a first macro bank comprising a first plurality of memory cells, the first plurality of memory cells comprising a first subset of the memory elements; a second macro bank comprising a second plurality of memory cells, the second plurality of memory cells comprising a second subset of the memory elements; an address resolution stage for addressing the memory cells in the respective macro banks, wherein the memory cells (p) are arranged so that the memory space is partitioned into a plurality of non-overlapping basic matrices; whereby each basic matrix is mapped to a given macro bank and wherein the memory cells (p) are arranged logically so that the memory space is partitioned into a plurality of non-overlapping logic matrices of a given size (S), each logic matrix being of a size equal or larger than a basic matrix; wherein the address resolution stage is adapted for transforming a logic address (R, C, r, c, d, S) as designating the location of the memory element in the logic matrix (r, c) and the location of the logic matrix in the memory space (R, C) and a direction (d) indicating either row or column access of the memory space and the size (S) of the logic matrix into a resolved address (A), the memory arrangement further comprising algorithm functions which transform the resolved address into a set of macro bank addresses (A