Patent ID: 6819600
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first and a second bit line in a first region and connected to a plurality of memory cells; an offset-compensated amplifier circuit structured to detect a voltage variation of the first bit line based on a reference voltage and to drive the second bit line according to a detection result; and a sense amplifier circuit in a second region and structured to sense and amplify a voltage difference between the first and second bit lines, wherein the offset-compensated amplifier circuit is structured to compensate an offset voltage with respect to the reference voltage in response to a first control signal before the voltage variation of the first bit line is detected; and wherein a part of the offset-compensated amplifier circuit is disposed at the first region and a remaining part of the offset-compensated amplifier circuit is disposed at a third region that is different from the first and second regions.