Patent ID: 7324388
Filing Date: 2008-01-29
Classification: G11C

Abstract:
1. A nonvolatile memory comprising: circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence; read/write circuits each used to form inversion layers in a direction intersecting said serial direction with turning on of the first and second control transistors and perform reading and writing of memory information from and to each memory transistor; and a selection circuit which selects a connection of the inversion layer placed under the first control transistor and the corresponding read/write circuit, wherein upon a read operation, the second control transistor and one of the right and left first control transistors are turned on to perform reading of one of the right and left memory transistors, and upon a write operation, the first control transistors on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other memory transistor via one of the right and left memory transistors, and wherein the selection circuit controls a connection of the read/write circuit and the inversion layer placed under the first control transistor in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.