Patent ID: 8860147
Filing Date: 2014-10-14
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising: forming first and second contact holes through a first dielectric layer respectively down to first and second terminals of a semiconductor device formed in a semiconductor body; forming a landing pad recess in the first dielectric layer near a top of the second contact hole; filling the first contact hole, second contact hole, and landing pad recess with a first fill material comprising tungsten, deposited using a chemical vapor deposition process; forming an interconnect line trench in the first dielectric layer near a top of the first contact hole; and filling the interconnect line trench with a second fill material different from the first fill material and comprising copper, using an electroplating process; whereby first and second contacts comprising tungsten are formed, with the first contact having an interconnect line comprising copper at a top thereof and the second contact having a landing pad comprising tungsten at a top thereof, wherein the landing pad recess has a length that is less than a minimum length of a copper interconnect line trench as a consequence of the chemical vapor deposition process.