Patent ID: 7491584
Filing Date: 2009-02-17
Classification: H01L

Abstract:
1. A method for manufacturing an ESD protection device, at least one PNP transistor and at least one diode are coupled between a ground and an input, the method comprising: providing a P-type semiconductor substrate; implanting P-type ions to the P-type semiconductor substrate, and diffusing to form a plurality of lightly doped P-type wells; implanting N-type ions to the P-type semiconductor substrate, and diffusing to form a plurality of lightly doped N-type wells adjacent to the lightly doped P-type well; in a first region of the P-type semiconductor substrate, doping heavily concentration P-type semiconductor material P+ into the lightly doped N-type well to form a first conducting terminal and the lightly doped P-type well to form a second conducting terminal, wherein the first conducting terminal couples with the input and the second conducting terminal couples with the ground; in a second region of the P-type semiconductor substrate, doping heavily concentration N-type semiconductor material N+ into the lightly doped N-type well to form a third conducting terminal coupled with the input; and in the second region of the P-type semiconductor substrate, doping heavily concentration P-type semiconductor material P+ into the lightly doped P-type well to form a forth conducting terminal coupled with the ground; wherein, in the first region, the PNP transistor is composed of the first conducting terminal, the lightly doped N-type well and the lightly doped P-type well, and the PNP transistor couples to the input through the first conducting terminal and couples to the ground through the second conducting terminal; and wherein, in the second region, the diode is composed of the lightly doped P-type well and the lightly doped N-type well, and the diode couples to the input through the third conducting terminal and couples to the ground through the fourth conducting terminal.