Patent ID: 6502226
Filing Date: 2002-12-31
Classification: G06F,H01L

Abstract:
A semiconductor device design method for forming a semiconductor device by combining and placing previously registered functional blocks, and determining a wiring pattern in accordance with given logical circuit specifications, said design method comprising:a registration step of previously registering a first functional block having a first conduction type diode comprising a first conduction type diffusion layer connected to an input pin of the functional block, and a second conduction type well connected to a second power supply or a second conduction type diode comprising a second conduction type diffusion layer connected to the input pin and a first conduction type well connected to a first power supply and a second functional block having the same logic as and the same drive capability as the first functional block but not containing the first or second conduction type diode; a determination step of determining whether or not a wiring conductor conducting to the input pin and a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in said semiconductor device when the antenna ratio is a ratio between an area of the wiring conductor conducting to the gate electrode and an area of the gate electrode; and a selection step of selectively using the first functional block, if said determination step determines that the input pin conducts to the gate electrode exceeding the antenna ratio.