Patent ID: 6674107
Filing Date: 2004-01-06
Classification: H02M

Abstract:
An N-channel normally off power junction field effect transistor (JFET) comprising:a heavily doped N+ substrate; an epitaxial N layer formed on the top of said N+ substrate; a drain; a source disposed at the bottom of said N+ substrate; a heavily implanted N+ region disposed on said epitaxial N layer to form an ohmic contact for said drain; and a plurality of P-type gate regions implanted into said epitaxial N layer, each gate region separated by a distance, W, wherein a gate having a gate junction is formed at the interface between each of said P-type gale regions and said epitaxial N layer, and wherein the gate junctions, when zero biased, create depletion regions that prevent current flow between said drain and said source and wherein further said gate junctions, when forward biased, reduce said depletion regions to provide a low resistance conduction channel between said drain and said source, said JFET having an on threshold voltage for the voltage between said gate and said source within the range of 0.2 volt and 0.3 volt.