Patent ID: 6100138
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method for fabricating capacitors in a DRAM cell, said method comprising the steps of:providing a semiconductor substrate, which is formed therein with isolation regions, source/drain regions, and word lines which are with first nitride spacers and first nitride capping layers formed atop said word lines;forming landing pads on said source/drain regions, said first spacers, said first capping layer of said word lines, each one of said landing pads being separated by an isolating layer, said isolating layer is on a portion of said first capping layers;forming a first dielectric layer on said landing pads and said isolating layers;forming a nitride barrier layer on said first dielectric layer;forming bit lines on said nitride barrier layer, each said bit line being formed of a conductive layer, and having a second nitride capping layer on said conductive layer and second nitride spacers on sidewalls of said bit line;forming a second dielectric layer on all areas of said semiconductor to fill the resulting topography;forming line photoresist masks on said second dielectric layer, said line photoresist masks being substantially perpendicular to said bit lines, and having line openings each being smaller than each said landing pad, so that said line opening each is above and within only one landing pad;forming recessed regions by anisotropic etching away unmasked portions of said second dielectric layer through said nitride barrier and said first dielectric layer to stop on said landing pads using said line photoresist masks as a mask, and said second nitride capping layer and said second nitride spacers as a hard mask so as to form recessing regions;performing a photoresist descum to shrink said line photoresist masks;anisotropic etching away unmask portions of said second dielectric layer so as to expand said recessed portions using line photoresist masks, said second nitride capping layer, said second nitride spacers as etching masks, and using said nitride barrier layer as an etching stopper;removing said line photoresist masks;conformal forming a polysilicon layer on all resulting surface of substrate;forming a photoresist layer on polysilicon layer to refill resulting topography; andperforming a planarization process using said second nitride capping layer as a stopping layer.