Patent ID: 7669163
Filing Date: 2010-02-23
Classification: H03K

Abstract:
1. A method for implementing designs on a programmable gate array, comprising: generating from first and second designs a first configuration data set that implements the first and second designs in first and second areas of the programmable gate array, respectively, wherein the first and second areas do not overlap, and each of the first and second designs includes a bus macro that defines a bus interface between the first and second designs, the bus interface including a set of signal lines coupled to the first and second designs and logic that controls input and output of signals over the signal lines; configuring the programmable gate array with the first configuration data set; generating from a third design a second configuration data set that implements the third design in the first area and that does not implement any version of the second design; wherein the third design is different from the first design and includes the bus macro for coupling the third design to the second design with the set of signal lines; and partially reconfiguring the programmable gate array with the second configuration data set in the first area, wherein in the partially reconfigured programmable gate array, the third design implemented with the second configuration data set in the first area is coupled to the set of signal lines.