Patent ID: 6014048
Filing Date: 2000-01-11
Classification: G06F,H03L

Abstract:
An integrated circuit device, comprisinga clock generator configured to receive an external clock and a feedback clock and to provide a clock signal, said clock generator configured to maintain approximate phase consistency between said external clock and said feedback clock;a clock distribution path configured to receive said clock signal and to distribute said clock signal to circuits included in the integrated circuit device as an internal clock;a matching path configured to receive said clock signal from said clock generator, to receive said internal clock from said clock distribution path, and to provide a matching clock, wherein said matching path comprises a delay locked loop circuit configured to approximate performance characteristics of said clock distribution path; anda feedback path configured to provide said feedback clock, wherein said feedback path is configured to select said feedback clock as said internal clock from said clock distribution path in a first mode and as said matching clock from said matching path in a second mode.