Patent ID: 7648875
Filing Date: 2010-01-19
Classification: H01L

Abstract:
1. A method for forming a DRAM device, comprising: forming a first interlayer dielectric on a semiconductor substrate; forming a contact pad to contact the semiconductor substrate through the first interlayer dielectric; forming a bitline on the first interlayer dielectric not to contact the contact pad; forming and planarizing a second interlayer dielectric to expose a top surface of the bitline; forming a protective layer above the bitline and the second interlayer dielectric layer; forming a sacrificial layer on the protective layer; patterning the sacrificial layer, the protective layer, and the second interlayer dielectric between adjacent two bitlines to form a bottom electrode contact hole exposing the contact pad; isotropically etching the second interlayer dielectric to increase width of the bottom electrode contact hole; conformally forming a spacer layer; anisotropically etching the spacer layer to expose the contact pad; and forming and planarizing a conductive layer to form a bottom electrode contact plug filling the bottom electrode contact hole, wherein the bitline includes a barrier pattern, a conductive interconnection, and a capping pattern which are stacked in the order named as well as spacers covering sidewalls of the barrier pattern, the conductive interconnection, and the capping pattern.