Patent ID: 8921182
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A method for fabricating a nonvolatile memory device, comprising: forming a stacked structure in which a plurality of interlayer dielectric layers and a plurality of sacrificial layers are alternately stacked over a substrate, wherein thicknesses of the sacrificial layers decrease from downward to upward; forming a first hole which exposes the substrate and has a diameter increasing from downward to upward by selectively etching the stacked structure; forming a first insulation layer in the first hole; forming a second hole which exposes the substrate and has a smaller sidewall slope than the first hole by selectively etching the first insulation layer; forming a channel layer in the second hole; forming a slit to expose the plurality of sacrificial layers in the stacked structure; removing the exposed sacrificial layers; forming grooves by etching the first insulation layer exposed by removing the sacrificial layers until a sidewall of the second hole is exposed, wherein parts of the interlayer dielectric layers exposed by removing the sacrificial layers are etched together with the first insulation layer, wherein an etching amount of the first insulation layer is substantially same as that of the parts of the interlayer dielectric layers, and wherein the etching amounts of the first insulation layer and the parts of the interlayer dielectric layers increase from downward to upward so that the grooves have substantially the same thickness; and forming gate electrode layers buried in the grooves and contacted with the channel layer with a memory layer interposed therebetween.