Patent ID: 6795352
Filing Date: 2004-09-21
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a first and second nonvolatile memory banks; a data-line for read and a data-line for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected to bit-lines of said first and second nonvolatile memory banks, said data-line for read and said data-line for program and verify being shared between said first and second nonvolatile memory banks; a reference current generator configured to generate a first voltage dependent upon a current flowing through a reference cell; first current converters to which the first voltage is input, each configured to generate a second voltage, second current converters to which the first voltage is input, each configured to generate a third voltage, sense amplifiers for read, first terminals respectively connected to a data-line for read, and second terminals respectively applied with the second voltage each generated by said first current converters, each configured to output data of a selection memory cell comparing a voltage of the data-line for read with the second voltage; sense amplifiers for program and verify, first terminals respectively connected to data-line for program and verify, and second terminals respectively being applied with the third voltage generated by said second current converters, each configured to output program and verify data of the selection memory cell, comparing a voltage of the data-line for program and verify with the third voltage; and a program circuit connected to said data-line for program and verify.