Patent ID: 6387747
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method for fabricating an RF inductor with minimum area and high Q comprising:providing a substrate; forming on said substrate a plurality of parallel, equidistant linear conducting segments using a first patterned photolithography mask; forming over said substrate and conducting segments a first layer of intermetal dielectric (IMD) material wherein said layer covers said conducting segments and conformally fills the spaces between them; planarizing said first IMD to expose said linear conducting segments; forming a second layer of IMD material over said planarized first layer of IMD material; patterning and etching said second layer of IMD material using a second patterned photolithography mask so as to form a plurality of parallel equidistant trenches extending vertically to the surface of said first IMD layer, said trenches also being parallel to and dimensionally equivalent to the linear conducting segments within the first IMD layer and wherein each trench is positioned between a pair of said conducting segments formed in said first IMD; forming a plurality of parallel conducting segments by depositing conducting material within said trenches formed in said second IMD layer; planarizing said second IMD layer now containing said deposited conducting material segments; forming on said planarized second IMD layer a third IMD layer; planarizing said third IMD layer; forming and patterning a third photolithography mask on said third IMD layer; etching said third IMD layer through said third photolithography mask so as to form two sets of cylindrical vias, wherein one said set is positioned over opposite ends of the conducting segments formed within the second IMD layer and extends completely through said third IMD layer and the second said set is positioned over opposite ends of the metal segments formed within the first IMD layer and extends completely through the third IMD layer and the second IMD layer; depositing conducting plugs within said vias so as to electrically contact said linear conducting segments formed within said first and second IMD layers; forming and patterning a fourth photolithography mask over said third IMD layer; depositing on said third IMD layer, through said patterned fourth photolithography mask, a plurality of parallel linear conducting material segments which are obliquely disposed relative to the conducting linear segments of the first and second IMD layers and wherein one end of each of said linear conducting material segments makes electrical contact with a conducting material filled via of one set of vias and the other end of said linear conducting material segment makes electrical contact with a conducting material filled via belonging to the other set of said vias in said third IMD and wherein said formation of linear conducting material segments thereby produces a continuous electrically conductive helical path.