Patent ID: 6274912
Filing Date: 2001-08-14
Classification: G11C,H01L

Abstract:
A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control,said semiconductor memory cell having;(1) a first semi-conductive region of the first conductivity type,(2) a second semi-conductive or conductive region formed in a surface region of the first region, said second region forming a rectifier junction together with the first region,(3) a third semi-conductive region of the second conductivity type formed in a surface region of the first region and spaced from the second region,(4) a fourth semi-conductive region of the first conductivity type formed in a surface region of the third region,(5) a fifth semi-conductive or conductive region formed in a surface region of the fourth region, said fifth region forming a rectifier junction together with the fourth region, and(6) a gate portion shared by the first transistor and the second transistor, and formed on a barrier layer so as to bridge the first region and the fourth region and so as to bridge the second region and the third region,wherein;(A-1) one source/drain region of the first transistor is constituted of the surface region of the fourth region,(A-2) the other source/drain region of the first transistor is constituted of the surface region of the first region sandwiched by the second region and the third region,(A-3) a channel forming region of the first transistor is constituted of the surface region of the third region sandwiched by the surface region of the first region and the surface region of the fourth region,(B-1) one source/drain region of the second transistor is constituted of the second region,(B-2) the other source/drain region of the second transistor is constituted of the surface region of the third region constituting the channel forming region of the first transistor,(B-3) a channel forming region of the second transistor is constituted of the surface region of the first region constituting the other source/drain region of the first transistor,(C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the third region facing the fifth region,(C-2) a channel region of the junction-field-effect transistor is constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region,(C-3) one source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from one end of the channel region of the junction-field-effect transistor and constituting one source/drain region of the first transistor,(C-4) the other source/drain region of the junction-field-effect transistor is constituted of a portion of the fourth region extending from the other end of the channel region of the junction-field-effect transistor,(D) the gate portion is connected to a first memory-cell-selecting line,(E) a diode is formed between the first region and the second region, and the first region is connected to a write-in information setting line through the diode,(F) the second region is connected to the write-in information setting line,(G) the portion of the fourth region constituting the other source/drain region of the junction-field-effect transistor is connected to a second memory-cell-selecting line, and(H) the fifth region is connected to a predetermined potential line.