Patent ID: 7965567
Filing Date: 2011-06-21
Classification: G06F,G11C,H01L,H04L

Abstract:
1. A memory controller comprising: a data interface to couple to an external memory device, the data interface to receive a first input data pattern from the external memory device; a first pattern register to store a first calibration data pattern; a second pattern register to store a second calibration data pattern; compare logic coupled to the data interface and to the pattern register circuitry, to perform a first comparison of the first input data pattern to the first calibration data pattern and to generate a first phase adjustment signal in response to the first comparison, and to perform a second comparison of a second input data pattern to the second calibration data pattern and to generate a second phase adjustment signal in response to the second comparison; delay register circuitry to store a first delay value that is determined in accordance with the first phase adjustment signal; and an input sampling circuit to sample, in accordance with the first delay value, data received from the external memory device.