Patent ID: 7539070
Filing Date: 2009-05-26
Classification: G11C

Abstract:
1. A semiconductor memory apparatus comprising: a plurality of unit cell blocks formed in row and column directions; at least a pair of first input and output lines formed at predetermined intervals in the row direction; at least a pair of second input and output lines that are formed at predetermined intervals in the column direction; I/O switches connected to a first node group and a second node group and control data input and output of the first input and output lines and the second input and output lines, the first node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the odd-numbered intervals of the intervals between columns of unit cell blocks, and the second node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the even-numbered intervals of the intervals between columns of unit cell blocks; and a reset selection unit that selectively outputs a reset signal to each line of the I/O switches.