Patent ID: 6090150
Filing Date: 2000-07-18
Classification: G06F

Abstract:
A clock wiring designing apparatus for designing clock wiring of an LSI, PWB or the like, said clock wiring designing apparatus comprising:delay analyzing means for evaluating delay time margins for a plurality of paths;means for detecting a worst case path having a worst delay time margin among the delay time margins;means for calculating a clock skew adjusting time by determining a difference between a delay time margin of a secondary worst case path and the worst delay time margin;additional delay time calculating means for determining an optimum delay time to be added to a clock net leading to a clock input terminal at a terminal side of the worst case path within a range of the clock skew adjusting time; andmeans for inserting a delay gate in said clock net so that the delay time determined by the additional delay time calculating means is added to the clock net as an additional clock skew, whereby a total time margin is used between said worst case path and said secondary worst case path.