Patent ID: 6832308
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A processor, comprising:a) an array to hold addresses of instructions waiting to be fetched; and, b) an array control circuit to control the order in which said addresses are sent from said array, said array control circuit comprising: a plurality of content addressable memory (CAM) cells, said plurality of CAM cells capable of holding a plurality of data structures from a pool of data structures, each data structure of said plurality of data structures pointing to a different location of said array that is holding an instruction address, said plurality of CAM cells comprising an input to receive an input vector that is capable of indicating which data structures of said plurality of data structures desire to issue from said plurality of CAM cells, said plurality of CAM cells further comprising an output to provide an output vector that indicates which of said plurality of CAM cells contain those of said one or more data structures that have issued from said plurality of CAM cells.