Patent ID: 9065235
Filing Date: 2015-06-23
Classification: H01L,H01S

Abstract:
1. A method of assembling VCSEL chips on a sub-mount comprising the following steps: forming p-type mesas by providing electrical p-contacts on top of the mesas, forming a n-type mesa by covering a mesa with an electrically isolating passivation layer overlapping at least over a p-n junction of the mesa, depositing a de-wetting layer on a connecting side of the VCSEL chips, depositing a further de-wetting layer on a connecting side of the sub-mount, said de-wetting layers being deposited with a patterned design or being patterned after deposition to define corresponding connecting areas on the sub-mount and the VCSEL chips which connecting areas provide a wetting surface for a solder, applying the solder to the connecting areas of at least one of the two connecting sides, placing the VCSEL chips on the sub-mount and soldering the VCSEL chips to the sub-mount without fixing the VCSEL chips relative to the sub-mount to allow a movement of the VCSEL chips on the sub-mount through surface tension forces of the melted solder, wherein the VCSEL chip comprises a bottom-emitter VCSEL array which is soldered with its mesa side to the sub-mount wherein prior to the deposition of the de-wetting layer on the connecting side of the VCSEL chips a first metal layer is deposited which is electrically connecting to the n-contacts of the VCSELs and overlapping the n-type mesa, said n-contacts forming a conducting network between p-type mesas of the VCSELs for electrically connecting the VCSELs and distributing the current equally over the p-type mesas, wherein a second metal layer is deposited at the same time as the first metal layer to overlap the p-type mesas and p-contacts, the first metal layer and the second metal layer mechanically stabilizing the VCSEL chips such that an electrical connection to the n-contact is at the same height as the p-contacts.