Patent ID: 7206857
Filing Date: 2007-04-17
Classification: G06F,H04L

Abstract:
1. An apparatus, comprising: an input RAM controller, an output RAM controller and an intermediate RAM controller, said input RAM controller to read a buffer's worth of information from an input RAM if a state of a first queue that is implemented with said input RAM has reached a threshold, said intermediate RAM controller to burst write said buffer's worth of information into an intermediate RAM in response to said reading of said buffer's worth of information from said input RAM, said buffer's worth of information stored within a second queue that is implemented with said intermediate RAM, said intermediate RAM controller to burst read said buffer's worth of information from said intermediate RAM in response to a third queue having room to receive said buffer's worth of information, said third queue implemented with an output RAM, said output RAM controller to write said buffer's worth of information into said third queue, said input RAM controller also to read an amount of information from said input queue if: a) said first queue has at least said amount of information; b) said second queue does not have information to store into said third queue; and, c) said third queue room has room to receive said amount of information, said output RAM controller to write said amount of information into said third queue.