Patent ID: 6366148
Filing Date: 2002-04-02
Classification: H03L

Abstract:
A delay locked loop circuit for receiving an input clock signal and generating an output clock signal, the output clock signal leading in phase the input clock signal by a predetermined time, the delay locked loop circuit comprising:a phase shifter for generating a first clock signal in phase with the input clock signal and a second clock signal having a 90Â° phase difference with respect to the first clock signal; a compensation delay unit for outputting a third clock signal which lags the input clock signal by the predetermined time; a component coefficient extractor for extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; a phase inverter for inverting the second component coefficient to produce an inverted second component coefficient; a first component signal generator for generating a first component signal by multiplying the first component coefficient by the first clock signal; a second component signal generator for generating a second component signal by multiplying the inverted second component coefficient by the second clock signal; and a phase mixer for mixing the first and second component signals to generate the output clock signal.