Patent ID: 7795085
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A method of fabricating an SRAM memory cell, comprising: providing a silicon substrate having a first pair of adjacent active regions of given n or p conductivity type well disposed between second and third pairs of adjacent active regions of opposite n or p conductivity type well, the active regions being isolated from one another by isolation regions formed in the substrate; forming common gates over at least the active regions of the first pair, and over ones of the active regions of the first pair and respective ones of the active regions of the second and third pairs; patterning a resist layer overlying the active regions of the first pair and over a portion of the isolation regions isolating at least one of each of the active regions of the second and third pairs, such that resist structures are formed on opposite sides of the at least one of each of the active regions of the second and third pairs to equally shadow laterally opposed first and second pocket implants made at same by oppositely directed angles, wherein the patterned resist structures overlying the isolation regions are about equally spaced away from and on opposite sides of the at least one of each of the active regions of the second and third pairs; implanting one or more dopant species of the opposite n or p conductivity type at an angle into the at least one of each of the active regions in a first pocket implant using the patterned resist layer including the resist structures as an implant mask; adjusting the rotational orientation between the substrate and the first pocket implant by about 180 degrees; and implanting the one or more dopant species at about the same but oppositely directed angle into the at least one of each of the active regions in a second pocket implant using the patterned resist layer including the resist structures as an implant mask.