Patent ID: 8110245
Filing Date: 2012-02-07
Classification: H01L,H05K

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a through hole in a substrate and an interconnect pattern on the substrate, a first portion of the interconnect pattern passing over the through hole; forming a first plating layer by covering a first surface of the first portion of the interconnect pattern with a first resist and by applying electroless plating to the interconnect pattern so that the first plating layer is formed on a second surface of the interconnect pattern, the first surface being on the side of the substrate, and the second surface being opposite to the first surface; forming a second plating layer by exposing the first surface of the first portion of the interconnect pattern, and by covering the second surface of the interconnect pattern with a second resist, and by applying electroless plating to the interconnect pattern so that the second plating layer is formed on the first surface of the first portion of the interconnect pattern; mounting a semiconductor chip on the substrate with a resin positioned between the semiconductor chip and the substrate, the resin'being positioned on the first plating layer; and providing a conductive material on the second plating layer, wherein the first plating layer is positioned between the interconnect pattern and the resin, and the second plating layer is thicker than the first plating layer.