Patent ID: 6320203
Filing Date: 2001-11-20
Classification: H01L,Y10S

Abstract:
A MOS structure, comprising:at least two first activated areas of a first conductivity type, adjacent activated areas of said first conductivity type being laterally spaced apart from one another to facilitate at least partial positioning of a transistor gate structure laterally therebetween;at least two second activated areas of a second conductivity type, said second conductivity type being opposite said first conductivity type;at least one isolation barrier comprising a dielectric material, said at least one isolation barrier located between at least one first activated area and at least one second activated area, said at least one isolation barrier having at most the same height as said at least one second activated area; andat least one conductive plug with a single downwardly extending member contacting a first activated area, a second activated area, and an isolation barrier located between said first and second activated areas.