Patent ID: 6577318
Filing Date: 2003-06-10
Classification: G09G,G11C

Abstract:
An integrated circuit device comprising:a first memory unit including data organized into rows which may be read in parallel; a conversion part which converts parallel data read from said first memory unit into serial data; and a second memory unit that can write and read control data indicating an order of reading the rows of said parallel data from said first memory unit, said control data including a plurality of entries, each of said plurality of entries corresponding to a row number of said first memory unit and including a first portion and a second portion of control data, said first portion specifying said row number of said first memory unit, said second portion specifying a serial conversion direction indicating a row direction in which data of said row number of said first memory unit is converted when converting said parallel data into said serial data and output as display data, said order of reading said rows specified by a position of each of said plurality of entries relative to said other entries.