Patent ID: 8962349
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method of manufacturing a magnetic tunnel junction (MTJ) memory element comprising the steps of: providing a substrate including a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; forming a first mask feature on top of said top electrode layer; etching said top electrode layer with said first mask feature thereon to form a top electrode; etching said MTJ layer stack with said top electrode thereon to form a patterned MTJ; encapsulating said patterned MTJ and said top electrode with a passivation layer; depositing a dielectric layer on top of said passivation layer; planarizing said dielectric layer without exposing said passivation layer therebeneath; forming a second mask feature on top of said dielectric layer, said second mask feature being aligned to said patterned MTJ and having a substantially larger lateral dimension than said patterned MTJ; and etching said bottom electrode layer, said etch stop layer, said passivation layer, and said dielectric layer with said second mask feature thereon to form a bottom electrode without exposing the patterned MTJ.