Patent ID: 9059010
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A device comprising: a wiring circuit board; and a plurality of semiconductor chips that are stacked with each other on the wiring circuit board, the plurality of semiconductor chips including an uppermost semiconductor chip and an other semiconductor chip over which the uppermost semiconductor chip is stacked, wherein the uppermost semiconductor chip includes a circuit layer in which a memory circuit is formed, and the other semiconductor chip includes a circuit layer in which an interface circuit is formed, wherein the circuit layer of the uppermost semiconductor chip is formed on a surface which faces down toward the other semiconductor chip and the wiring circuit board, wherein the circuit layer of the other semiconductor chip is formed on a surface which faces up toward the uppermost semiconductor chip, wherein the uppermost semiconductor chip and the other semiconductor chip each further includes four or more bonding pads, each of the four or more bonding pads of the uppermost semiconductor chip being vertically aligned with and electrically connected to an associated one of the four or more bonding pads of the other semiconductor chip, and wherein the uppermost semiconductor chip is greater in thickness than the other semiconductor chip.