Patent ID: 6167420
Filing Date: 2000-12-26
Classification: G06F

Abstract:
A multiplication method for carrying out a multiplication process by generating and adding subproducts, comprising:a rounding signal generation process for generating a rounding signal including a rounding value to be added to a low-order bit adjacent to the least significant bit in a given cut-out bit range of a multiplication result obtained by said multiplication process on the basis of a shift bit count signal corresponding to the difference between the least significant bit in said given cut-out bit range of said multiplication result obtained by said multiplication process and the least significant bit in a reference cut-out bit range;a subproduct generation process for generating subproducts of a multiplier and a multiplicand obtained by a multiplication instruction;an addition process for adding all of said subproducts generated by said subproduct generation process to said rounding signal in order to generate a multiplication result obtained after rounding; anda shift process for shifting said multiplication result obtained after rounding by a shift bit count indicated by said shift bit count signal in order to cut out said given cut-out bit range from said multiplication result obtained after rounding.