Patent ID: 7122472
Filing Date: 2006-10-17
Classification: H01L

Abstract:
1. A method of forming an integrated circuit on a semiconductor substrate, said method comprising: forming a first type semiconductor device having first source/drain silicide areas and a first type gate region isolated from said first source/drain silicide areas; forming a second type semiconductor device having second source/drain silicide areas and a second type gate region isolated from said second source/drain silicide areas; forming a dielectric layer over all of said first and second source/drain silicide areas; depositing a first metal layer over said second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only said second type gate region; depositing a second metal layer over both of the first and second type semiconductor devices; forming a cap layer over each of said first metal layer and said second metal layer; and performing a second FUSI gate formation on only said first type gate region.