Patent ID: 6687813
Filing Date: 2004-02-03
Classification: G06F

Abstract:
A data processing system having a pipelined architecture and having looping capability that allows a sequence of instruction execution sets to be repeated N times, the repetition involves a first delayed conditional jump operation to the first instruction execution set of the sequence of the instruction sets, the data processing system comprising:an internal memory module, for storing a plurality of instruction fetch sets; data arithmetic logic units, wherein the data arithmetic logic units have the ability to work in parallel; a program sequencer, coupled to the data arithmetic logic units and to the internal memory module, for fetching instruction fetch sets, for dispatching instructions out of an instruction execution set to the data arithmetic logic units, and for controlling the execution of nested loops; wherein the instruction execution set is a subset of the instruction fetch set; and wherein the first instruction execution set that initiated the first delayed conditional jump operation has a first prefix instruction, for initiating the first delayed conditional jump operation and a second instruction execution set of the sequence of instruction execution sets scheduled after the first instruction execution set and before the first delayed conditional jump operation comprises a second prefix instruction initiating a second delayed conditional jump operation performed only when the first conditional jump operation is not performed.