Patent ID: 6411127
Filing Date: 2002-06-25
Classification: H03K

Abstract:
A multi-level buffer, comprising:a first node for connection to a pad; a first current control circuit coupled between the first node and a first prescribed reference voltage, wherein a first current flows through the first current control circuit to the first node when a first control signal is not activated, and wherein a second current larger than the first current flows when the first control signal is activated; a resistor coupled between the first node and a second node; a second current control circuit coupled between the second node and a second prescribed reference voltage, wherein a third current substantially equal to the first current flows through the second current control circuit when the first control signal is not activated, and wherein a fourth current substantially equal to the second current flows when the first control signal is activated; and a logic signal generator that generates a first buffer output signal and a second buffer output signal, respectively, by transforming signals of the first and second nodes into logic signals of prescribed internal voltage levels.