Patent ID: 6289406
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A system for completing a present read transaction between an initiator device and a host memory device in a computer system, said system comprising:a bus;a bus bridge device, said bus bridge device comprising:a target device, said target device coupled to said initiator device via said bus; anda timer mechanism coupled to said target device; and said host memory device coupled to said bus bridge device;said initiator device adapted to assert an access to said target device, such that said present read transaction is initiated;said timer mechanism adapted to measure target latency for one or more read transactions contiguously preceding said present read transaction, said timer mechanism further adapted to use said target latency to determine a dynamic target latency period and to update said dynamic target latency period after each read transaction; andsaid bus bridge device adapted to maintain said access to said initiator device during said dynamic target latency period, thereby facilitating completion of said present read transaction.