Patent ID: 6711724
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A method of designing a semiconductor integrated circuit device comprising a pipeline including a plurality of flip-flop circuits each transferring a signal synchronously with a basic clock signal, comprising the steps of:designing said pipeline using the flip-flop circuits with a cycle period of a transfer clock signal being a sum of a cycle of said basic clock signal and a gain time obtained when a specific flip-flop circuit in said pipeline is replaced by a latch circuit; setting the cycle period of said transfer clock signal at the cycle period of said basic clock signal and detecting an error path in the designed pipeline; dividing a flip-flop circuit related to said error path into a plurality of latch circuits complementarily operating synchronously with said transfer clock signal; and dividing a logic circuit related to said error path by said plurality of latch circuits such that a predetermined conditional inequality for signal propagation delay is satisfied for logic circuit stages related to the respective latch circuits, thereby rearranging the logic circuit.