Patent ID: 6917552
Filing Date: 2005-07-12
Classification: G11C

Abstract:
1. A semiconductor device, comprising: a plurality of memory cells each disposed at one of a plurality of intersections between a plurality of word lines and a plurality of data lines; a plurality of first sense amplifiers each comprising a pair of MISFETs of a first conductivity type arranged to match each of said plurality of data lines; a plurality of second sense amplifiers each comprising a pair of MISFETs of a second conductivity type and arranged to match each of said plurality of data lines; a first power source supply line for supplying a first power source to said plurality of first sense amplifiers; a first common source line where source nodes of said plurality of first sense amplifiers are commonly connected; a second power source line for supplying a second power source to said plurality of second sense amplifiers; a second common source line where source nodes of said plurality of second sense amplifiers are commonly connected; a plurality of first switches provided between said first power source supply line and said first common source line; a plurality of second switches provided between said second power source supply line and said second common source line; a third power source supply line for supplying a third power source to said plurality of first sense amplifiers; a third switch provided between said third power source supply line and said first common source line; and a first output amplifier circuit connected with one of said data lines and having an input and an output separated from each other, whereby: said first power source voltage is higher than said third power source voltage; and said first output amplifier is activated earlier than said first and second sense amplifiers.