Patent ID: 6968492
Filing Date: 2005-11-22
Classification: H03M

Abstract:
1. An integrated circuit adapted to receive data bits of a packet via a N-bit bus and generate a cyclic redundancy check for the packet, the integrated circuit comprising: a first dividing logic comprising M dividers each adapted to receive and divide a different one of the N/M bits of the data by a first generator polynomial, wherein the divider receiving the first of the N/M bits of data supplies a first output signal; a second dividing logic adapted to receive the first output signal, said second dividing logic comprising P dividers each adapted to receive and divide a different one of the N/P bits of the data it receives by the first generator polynomial to generate a remainder, said second dividing logic further adapted to supply one of the N/P remainders as a second output signal; and a third dividing logic adapted to receive and divide the second output signal by a second generator polynomial.