Patent ID: 7393775
Filing Date: 2008-07-01
Classification: G06F,H01L

Abstract:
1. A wiring layout method for a semiconductor integrated circuit having a plurality of circuit elements and a plurality of wires connecting the circuit elements, comprising: generating data, in a first wiring layer, for orthogonal wires disposed on a standard grid, which has a pitch P and extends in a horizontal or vertical direction, at intervals of at least said pitch P; and generating data, in a second wiring layer, which differs from said first wiring layer, for diagonal wires inclined by 45° or 135° in relation to said orthogonal wires, said data for diagonal wires including data for a first diagonal wire formed on a grid point of said standard grid, and data for a second diagonal wire formed on a ½ grid point at which said standard grid intersects a ½ grid which is displaced from said standard grid by P/2, wherein said first and second diagonal wires are disposed at intervals of at least (1.5/√2)×P in relation to said pitch P.