Patent ID: 6384644
Filing Date: 2002-05-07
Classification: H03K

Abstract:
An output circuit receiving an external input signal and first to third control signals, comprising:an input circuit generating an internal input signal in response to the external signal; an output circuit including a first pair of transistors, said first pair of transistors including a first pMOS transistor coupled between a positive potential source and an output terminal and a first nMOS transistor coupled between a reference potential source and the output terminal, a gate of one of the first pair of transistors receiving the internal input signal; a first control circuit receiving the internal input signal and the first control signal, said first control circuit outputting a first internal signal, in response to the internal input signal and the first control signal, to a gate of the other one of the first pair of transistors, the first control circuit outputting the internal input signal as the first internal signal when the first control signal has a first level, and outputting a predetermined level signal as the first internal signal when the first control signal has a second level, so that the other one of the first pair of transistors has a predetermined state; a second pair of transistors including a second nMOS transistor coupled between the reference potential source and the output terminal, and a second pMOS transistor coupled between the positive potential source and the output terminal, said second pMOS transistor receiving and being controlled by the third control signal; and a second control circuit receiving the internal input signal and the second control signal, and outputting a second internal signal, in response to the internal input signal and the second control signal, to a gate of the second nMOS transistor, the second control circuit outputting the internal input signal as the second internal signal when the second control signal has the second level and outputting a low level signal as the second internal signal when the control second signal has the first level, so that the second nMOS transistor is in an OFF state.