Patent ID: 8937845
Filing Date: 2015-01-20
Classification: G11C

Abstract:
1. A system for managing redundancy in a memory device, wherein the memory device includes a first memory array and a first periphery logic circuit associated therewith, and at least one redundant memory array and a redundant periphery logic circuit associated therewith, wherein the first periphery logic circuit includes first and second logic circuits, and wherein the second logic circuit includes first and second sets of logic circuits, the system comprising: a memory input/output (I/O) switch, connected to a power supply, the first memory array, and the first periphery logic circuit, wherein the memory I/O switch is configured to be switched on during a memory built-in-self-test (BIST) operation for detecting at least one defect in the first memory array and switched off for disabling a supply of power to the first memory array, the first logic circuit, and the first set of logic circuits, based on the detection of the at least one defect; and a redundant I/O switch, connected to the power supply, the redundant memory array, and the redundant periphery logic circuit, wherein the redundant I/O switch is configured to be switched on when the redundant memory array and the redundant periphery logic circuit are substituted for the first memory array and the first periphery logic circuit, respectively, based on the detection of the at least one defect, and switched off when the redundant memory array and the redundant periphery logic circuit are not in use, wherein the second set of logic circuits is connected to the power supply to receive a continuous supply of power therefrom to enable shifting of data stored in the first memory array to the redundant memory array, based on the detection of the at least one defect, wherein the second logic circuit includes at least one of a read latch, an output driver, a write latch, and a redundancy decoder, and wherein the read latch includes: