Patent ID: 9135985
Filing Date: 2015-09-15
Classification: G11C

Abstract:
1. An SRAM cell array comprising a plurality of SRAM cells, wherein, said SRAM cell includes a core memory circuit and a write-related circuit, and further comprises: a first transistor; a second transistor; and a third transistor, wherein: the SRAM cell array further comprising: a fourth transistor, wherein one of the source and the drain of said first transistor is connected to said working level by said fourth transistor, wherein one of a source and a drain of said fourth transistor is connected to one of the source and the drain of said first transistor while the other one is connected to said working level, and wherein a gate of said fourth transistor is connected to a first read control signal, which enables said fourth transistor to be turned on during period of performing a read operation on said SRAM cell; the SRAM cell further comprising: a fifth transistor, wherein one of the source and the drain of said second transistor is connected to said reference level by said fifth transistor, wherein one of a source and a drain of said fifth transistor is connected to one of the source and the drain of said second transistor while the other one is connected to said reference level, wherein a gate of said fifth transistor is connected to a second read control signal, which enables said fifth transistor to be turned on during period of performing a read operation on said SRAM cell, and wherein the channel dimension of said fourth transistor and said fifth transistor is greater than two times the channel dimension of said first transistor and said second transistor.