Patent ID: 8130891
Filing Date: 2012-03-06
Classification: H03L,H04L

Abstract:
1. A circuit capable of tracking a data signal, comprising: a clock circuit to generate at least one clock signal; a sampler circuit to sample the data signal in response to the at least one clock signal to produce a series of data samples and a series of edge samples, the data signal having a variable data bit rate; a phase detector to generate a phase movement signal in each of a plurality of adjustment cycles based on M data samples and N edge samples, wherein M and N are positive integers each larger than one; and logic circuitry to determine a phase drift of the data signal with respect to the at least one clock signal based on a plurality of phase movement signals output by the phase detector over a period of time that includes multiple adjustment cycles; wherein the clock circuit is configured to adjust the at least one clock signal to track the data signal in response to a phase adjust signal derived from the phase movement signal and the phase drift, wherein the logic circuitry includes stall logic capable of stalling adjustment of the at least one clock signal during one or more current adjustment cycles in response to data phase information derived during one or more previous adjustment cycles.