Patent ID: 6128248
Filing Date: 2000-10-03
Classification: G11C,H03K,H04L

Abstract:
A semiconductor memory device comprising:a memory cell array;a read circuit which reads data from said memory cell array;an external terminal which receives an external clock signal;a first input circuit which receives the external clock signal therein and outputs a first internal clock signal delayed from the external clock signal;a second input circuit which receives the first internal clock signal therein and outputs a second internal clock signal delayed from the first internal clock signal;a circuit which counts a clock signal having a frequency higher than that of the external clock signal;a circuit which starts said counting in response to the second internal clock signal, reverses the direction of said counting in response to the first internal clock signal and detects when a count of said counting circuit again reaches the count at the start of said counting, thereby outputting a timing signal therefrom; anda clock output circuit which outputs a third internal clock signal for controlling the operation of said read circuit based on the timing signal.