Patent ID: 7419909
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A method of forming patterns in a semiconductor device, comprising: defining a lower layer that comprises a first region and a second region on a semiconductor substrate; forming first patterns with a first pitch that extend to the first and second regions; forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns; forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns; forming third patterns that correspond to the second patterns in the gap regions, respectively; etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns; and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.