Patent ID: 6172495
Filing Date: 2001-01-09
Classification: G05F

Abstract:
A circuit for mirroring currents in application specific integrated circuits, comprising:an array of two or more active devices;a group of three matched resistors corresponding to each active device within said array, said group of three matched resistors having a center resistor, a first side resistor and a second side resistor, said center resistor coupled to a source contact of a corresponding active device as a source degeneration resistor, said first side resistor coupled to a summing junction and said second side resistor coupled as part of a reference resistor;a current input coupled to said reference resistor;an error amplifier having a first input coupled to said reference resistor, a second input coupled to said summing junction, and an output coupled to the gate contact of each of said two or more active devices; anda single array output formed by coupling the drain contact from each of said two or more active devices.