Patent ID: 6255189
Filing Date: 2001-07-03
Classification: G03F,H01L

Abstract:
A method of manufacturing a semiconductor device, in particular an integrated circuit, in a silicon body, comprising providing an alignment grating at a surface for aligning the silicon body relative to masks which are used in a number of successive process steps to image patterns onto the surface of the silicon body; providing the alignment grating in the form of a strip pattern of adjacent elevations and valleys; and providing the surface with a mask of a material which protects the silicon body against oxidation; providing the mask with apertures at the location of the semiconductor device; then providing the silicon body with an oxide pattern by means of oxidation; recessing the pattern in the silicon body over at least a part of its thickness to define active regions in the silicon body; simultaneously providing the alignment grating and the partly recessed oxide pattern; providing the material which protects against oxidation at the location of the alignment grating to be produced so as to comprise first wide strips, where the surface remains entirely free of recessed oxide, which alternate with second wide strips; forming each of said second wide strips by a sub-pattern of relatively narrow strips of the material which protects against oxidation; separating said narrow strips from each other by relatively narrow apertures, which are smaller than the apertures at the location of the semiconductor device; then, during oxidation, providing each of the second wide strips with a segmented, also partly recessed, oxide pattern with a profiled surface; providing the relatively narrow apertures with a width such that the recessed oxide pattern in the alignment grating is thinner than the simultaneously formed recessed oxide pattern in the semiconductor device.