Patent ID: 6535456
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array having a plurality of memory cells arranged in rows and columns; a counting section, to which a clock signal is input, configured to count transitions of the clock signal and to determine first data of a plurality of data to be transferred sequentially; a control section configured to fetch information indicating a memory cell location in the memory cell array in response to a counting result of said counting section and to control consecutive input and output of a plurality of data stored in the memory cell array each cycle of the clock signal; a specification section configured to decode the information fetched by said control section and to designate a memory cell in the memory cell array; and a data input/output section configured to input data to the memory cell designated by said specification section and to output data from the memory cell designated by said specification section, wherein input and output of the data are time-shared.