Patent ID: 6642135
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising:providing a substrate including a first area, a second area and a global step difference between the first and the second areas, wherein the substrate comprises a fuse formed in the second area of the substrate; forming an interlayer insulating layer on the substrate; simultaneously removing a first portion of the interlayer insulating layer in the first area and a second portion of the interlayer insulating layer in the second area, thereby decreasing the global step difference and defining a first recess in the interlayer insulating layer in the second area, wherein the first recess is defined over the fuse; forming a passivation layer on the interlayer insulating layer; and forming a fuse opening on the fuse, wherein the fuse opening is formed through the passivation layer, the interlayer insulating layer and the first recess.