Patent ID: 9053797
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A method of inhibiting programming of a memory cell corresponding to a pillar of semiconductor material, comprising: increasing a voltage on the pillar corresponding to the memory cell to be inhibited from programming without increasing a voltage on a pillar corresponding to a memory cell to be enabled for programming; and after increasing the voltage on the pillar, boosting the voltage on the pillar corresponding to the memory cell to be inhibited from programming prior to applying a program pulse on a control gate coupled to the memory cell to be inhibited from programming and the memory cell to be enabled for programming; wherein increasing the voltage on the pillar comprises decreasing a voltage on a select device corresponding to the pillar corresponding to the memory cell to be inhibited from programming from a first voltage to a second voltage while a data line coupled to the select device is at an inhibit voltage.