Patent ID: 7659177
Filing Date: 2010-02-09
Classification: H01L

Abstract:
1. A manufacturing method of a high voltage semiconductor device, comprising: forming a semiconductor substrate, the substrate being defined by a key area for an alignment key, a low voltage area for a low voltage device, and a high voltage area for a high voltage device; forming an oxide film on the substrate; forming an insulating film on the oxide film; after removing the insulating film, forming a plurality of shallow trench isolations (STI's) in the key area, the low voltage area, and the high voltage area; forming a nitride layer on the substrate and on the plurality of STIs; sequentially forming a plurality of high voltage area wells and high voltage area drift areas by implanting an impurity ion into the high voltage area; and sequentially forming a plurality of low voltage area wells and low voltage area drift areas by implanting an impurity ion into the low voltage area after sequentially forming the plurality of high voltage area wells and high voltage area drift areas.