Patent ID: 6339350
Filing Date: 2002-01-15
Classification: H03D,H03L

Abstract:
A conversion circuit, comprising:a phase comparator for outputting first and second digital signals one of which has a first level and the other of which has a second level in a case where phases of two input signals do not coincide with each other, and for outputting the first and second digital signals both of which have the first level in a case where the phases of the two input signals coincide with each other; a charge pump circuit for outputting an outflow current when the first digital signal outputted from the phase comparator is in the first level, and for outputting an inflow current when the second digital signal outputted from the phase comparator is in the first level; and a delay circuit for causing the first and second digital signals outputted from the phase comparator to become the second level after a first delay time in a case where the phases of the two input signals coincide with each other. the charge pump circuit including a first transistor circuit for outputting one of the outflow current and the inflow current by a second delay time. the delay circuit includes a second transistor circuit for determining the first delay time, the second delay time being substantially equal to the first delay time, and the delay circuit including a third transistor , said third transistor having a gate connected to said gate of said second transistor, and a source/drain path connected to a source of said second transistor.