Patent ID: 6122216
Filing Date: 2000-09-19
Classification: G11C

Abstract:
A memory device, comprising:an integrated circuit package including a plurality of address, data, and control terminals;a first memory array encapsulated in said integrated circuit package, said first memory array connecting to said terminals via a first set of data, address and control signals;a second memory array encapsulated in said integrated circuit package, said second memory array connecting to said terminals via a second set of data, address and control signals, wherein the second set of address and data signals directly connect to the first set of address and data signals respectively within the integrated circuit package;wherein said first and second memory arrays comprise different types of memory technologies; anda select signal coupled to one of said control terminals that selects either said first memory array or said second memory array, wherein said memory device carries out memory operations using said second memory array if the select signal is asserted, and wherein said memory device carries out memory operations using said first memory array if the select signal is deasserted.