Patent ID: 7987347
Filing Date: 2011-07-26
Classification: G06F

Abstract:
1. A system implemented on an integrated circuit chip for processing a sequence of instructions, the system comprising: a program counter register configured to store an address for an instruction currently being processed; a loop counter register configured to store a number of times to process the sequence of instructions; a loop start register configured to store a reference to an address of a first instruction to execute within the sequence of instructions, wherein the reference to the address of the first instruction stored by the loop start register comprises an offset value that, when subtracted from the breakpoint address, results in the address of the first instruction of the sequence of instructions; an existing breakpoint-match hardware within a microprocessor comprising: a pipeline comprising a plurality of pipeline stages; and a branch-target cache configured to retrieve one or more subsequent instructions from a cache and to place the subsequent instructions in the pipeline in parallel with the instruction currently being processed, the one or more subsequent instructions being selected from a set of instructions beginning with the first instruction, if the address stored in the program counter register is not same as the address stored in the breakpoint register and a next value of the address stored in the program counter, corresponding to the program counter offset by an address, is same as the address stored in the breakpoint register, and the loop counter indicates that the sequence of instructions must be processed at least once more; wherein the breakpoint-match hardware is configured to break execution of the sequence of instructions at the breakpoint and to set the program counter register to the address specified by the loop start register when the comparator determines that the address stored in the breakpoint register matches the address stored in the program counter register and the loop counter register indicates that the sequence of instructions must be processed at least once more.