Patent ID: 6034898
Filing Date: 2000-03-07
Classification: G11C

Abstract:
A memory device which includes:first to 2N-th data bus sense amplifiers which sense and amplify data transmitted from data bus lines;first to 2N-th read data transmitters for receiving output signals of the first to 2N-th data bus sense amplifiers; andfirst to 2N-th data output drivers which are made of pull-up and pull-down transistors and receive output signals of the first to 2N-th read data transmitters, whereby output lines of the first to 2N-th data output drivers are connected to first to 2N-th data output pins,the memory device for increasing a data output driver current comprising:a) a plurality of first switching means which sequentially connect output lines of even data bus sense amplifiers among the first to 2N-th data bus sense amplifiers to input lines of even read data transmitters among the first to 2N-th read data transmitters;b) a plurality of second switching means which sequentially connect input lines of odd read data transmitters among the first to 2N-th read data transmitters to input lines of even read data transmitters among the first to 2N-th read data transmitters; andc) a plurality of third switching means which sequentially connect output lines of odd data output drivers among the first to 2N-th data output drivers to output lines of even data output drivers among the first to 2N-th data output drivers; wherein:the first to third switching means are controlled by a common control signal;when the common control signal is at a first logic state, the first switching means are turned on and the second to third switching means are turned off; andwhen the common control signal is at a second logic state, the first switching means are turned off and the second to third switching means are turned on.