Patent ID: 6505182
Filing Date: 2003-01-07
Classification: G06K,G06N

Abstract:
A TRNN algorithmic engine for neuron-like computing comprising:a source (1) of a weighting parameter W, a growth or decay parameter Q and an address parameter A; a source of signals (2); a coincidence detector (3) for generating at its output a high value when a signal from said source of signals (2) available at its first input and said parameter W available at its second input are approximately equal; a shared memory (4) containing a plurality of memory elements with address A, each memory element constituting a neuron capable of storing a multivalued quantity, said each memory element also capable of being written to or read from at the same time by a plurality of users by means of a plurality of data buses, each data bus being associated with its own address bus; a latch (5) for holding at its output a value previously supplied at its input and representing previous contents of one of said neurons; a multiplier (6) for generating at its output an arithmetic product of said parameter Q available at its first input and said output of latch (5) available at its second input; an adder (7) for generating at its output an arithmetic sum of said output of coincidence detector (3) available at its first input and said output of multiplier (6) available at its second input; a switch (17) for gating said output of adder (7) to one of said plurality of data buses (14) of said shared memory (4); means for connecting said source of signals (2) to said first input of said coincidence detector (3); means for connecting said parameter W to said second input of said coincidence detector (3); means for connecting said parameter Q to said first input of said multiplier (6); means for connecting said parameter A to one of said plurality of address busses of said shared memory (4) associated with said data bus (14) for selecting a said neuron; means for connecting said data bus (14) of said shared memory (4) to said input of latch (5); means for connecting said output of latch (5) to said second input of multiplier (6); means for connecting said output of coincidence detector (3) to said first input of adder (7); means for connecting said output of multiplier (6) to said second input of adder (7); means for connecting said output of adder (7) to said input of switch (17); means for connecting said output of switch (17) to said first of said plurality of data busses (14) of said shared memory (4); and control circuits (16) and means for connecting said control circuits (16) to said source (1) of parameters W, Q and A, said shared memory (4), said latch (5) and said switch (17) for causing a new value of said parameter W, a new value of said parameter Q and a new value of said parameter A to become available from said source (1), causing a value previously stored at said new address A in said shared memory (4) to be read out and causing it to be held in said latch (5), and causing said sum generated at said output of adder (7) to be connected by means of said switch (17) to said data bus (14) of said shared memory (4) and causing said sum to be stored as an updated value in said shared memory (4) at said new address A.