Patent ID: 6097229
Filing Date: 2000-08-01
Classification: H03K

Abstract:
A bus-hold circuit comprising:an inverter having an input and an output;a first transistor of a first conductivity type having a source-drain current path and a gate coupled to said output;a second transistor of a second conductivity type having a source-drain current path and a gate, the source-drain current paths of said first and second transistors being coupled in series between a power supply terminal and a reference terminal;a third transistor of said first conductivity type having a source-drain current path coupled between the gates of said first and second transistors and a gate coupled to said power supply terminal;a fourth transistor of said second conductivity type having a source-drain current path and a gate, the source-drain current path of said fourth transistor coupled between the gate of said second transistor and said input, the gate of said fourth transistor coupled to said power supply terminal; anda resistor having a first terminal coupled to the source-drain current paths of said first and second transistors and a second terminal coupled to said input.