Patent ID: 8754450
Filing Date: 2014-06-17
Classification: H01L

Abstract:
1. A manufacturing method of a silicon-germanium heterojunction bipolar transistor having low collector-base capacitance, which comprises: A) performing ion implantation to predetermined locations in a silicon substrate to form implantation regions; B) depositing a bottom oxide layer, a nitride film and a top oxide layer successively on the silicon substrate as hard mask; C) forming hard mask windows for trench isolation regions by etching the top oxide layer, the nitride film and the bottom oxide layer; D) depositing first oxide film and forming oxide spacers in the hard mask windows through an etch-back process; E) forming isolation trenches by dry etching the silicon substrate, each isolation trench being connected to a corresponding one of the implantation regions; F) forming lateral trenches by etching the implantation regions; G) removing the top oxide layer and the oxide spacers; H) forming pad oxide layers in the isolation trenches and the lateral trenches; I) filling second oxide film into the isolation trenches and then removing the nitride film and the bottom oxide layer on the surface of the silicon substrate; J) depositing a first dielectric film and forming a base window in the first dielectric film, and performing epitaxial deposition of a base SiGe film; K) depositing a second dielectric film and forming an emitter window in the second dielectric film; L) depositing an emitter polysilicon; M) forming a final silicon-germanium heterojunction bipolar transistor by etching the emitter polysilicon.