Patent ID: 6748505
Filing Date: 2004-06-08
Classification: G06F

Abstract:
A method of performing memory transactions in a processing system including a plurality of system sub-blocks, a memory controller, a main memory, and a system bus including a first set of signal lines for transmitting memory transaction request and grant signals, a second set of signal lines for transmitting memory transaction address signals, and a third set of signal lines for transmitting memory transaction data signals, said method comprising the steps of:1) a first sub-block transmitting a first memory transaction request signal on said first set of signal lines to said memory controller for performing a first memory transaction with said main memory; 2) said memory controller issuing a first grant signal on said first set of signal lines to said first sub-block in response to said first memory transaction request signal; 3) said first sub-block transmitting a first address corresponding to said first memory transaction; 4) said memory controller servicing said first memory transaction request upon receipt of said first address; wherein after said issuing of said first grant signal (step 2) and prior to completion of said servicing of said first memory transaction (step 4): a) said memory controller issuing a second grant signal, based upon an arbitration scheme in response to a second memory transaction request signal originating from one of said plurality of system sub-blocks; and b) said one system sub-block transmitting a second address corresponding to said second memory transaction to said memory controller; c) storing said second address in said memory controller; d) said memory controller accessing said second address on completion of said servicing of said first memory transaction request; and e) servicing said second memory transaction request.