Patent ID: 7852696
Filing Date: 2010-12-14
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a semiconductor layer; a source layer and a drain layer provided in the semiconductor layer; a body region provided on the semiconductor layer between the source layer and the drain layer, and accumulating electric charges or emitting the electric charges to store logic data; a first gate dielectric film provided on a first surface of the body region; a first gate electrode provide on the first surface of the body region via the first gate dielectric film; a second gate dielectric film provided on a second surface of the body region, the second surface different from the first surface; a second gate electrode provide on the second surface of the body region via the second gate dielectric film; a driver driving the first gate electrode or the second gate electrode; and a sense amplifier sensing the logic data from a memory cell including the source layer, the drain layer, and the body region, wherein when a refresh operation for returning deteriorated logic data of the memory cell to original logic data is periodically executed, a first current is carried from the drain layer or the source layer to the body region and a second current is carried from the body region to the second gate electrode by respectively applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other with respect to a potential of the source layer set as a reference potential, and a state of the memory cell is recovered to a stable stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation.