Patent ID: 6202143
Filing Date: 2001-03-13
Classification: G06F

Abstract:
A data processing system comprising:a first program memory that stores a plurality of unit instructions;a second program memory that stores a plurality of multi-instructions that consists of plural unit instruction;a first program bus, coupled to said first program memory, that transfers the unit instructions;a second program bus, coupled to said second program memory, that transfers the multi-instructions; anda processor core, coupled to said first and second program buses, that receives and executes the transferred unit instructions and the transferred multi-instructions,wherein said processor core including an instruction input interface circuit that adds one or more NOP (No-Operation) instructions to each of the transferred unit instructions to convert the transferred unit instructions into converted multi-instructions;wherein said first and second program memories have different bit-widths; andwherein the unit instruction contains an end bit indicative of whether the unit instruction is a final unit instruction in a multi-instruction.