Patent ID: 8687458
Filing Date: 2014-04-01
Classification: G11C

Abstract:
1. A semiconductor apparatus comprising: an odd data clock buffer group configured to buffer a phase of a multi-phase source clock signal, and output a first multi-phase clock signal; an even data clock buffer group configured to buffer the phase of the multi-phase source clock signal, and output a second multi-phase clock signal; an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal, and output the driven data to an odd data pad group; and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal, and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other, wherein each of the odd and even data clock buffer groups is configured to control an amount of a phase shift of the first and second multi-phase clock signal respectively, in response to a control signal, wherein each of the odd and even data clock buffer groups comprises: a first selection section configured to select one of the inputted multi-phase source clock signal in response to the control signal; a second selection section configured to select one of the inputted multi-phase source clock signal in response to the control signal; and an output section configured to mix an output signal of the first selection section and an output signal of the second selection section, and output the mixed signal.