Patent ID: 7102422
Filing Date: 2006-09-05
Classification: H02M

Abstract:
1. A semiconductor booster circuit, comprising: a plurality of stages each having a MOS transistor, a first capacitor and a second capacitor, said MOS transistor being formed in a well and having a drain, a source and a gate, said first capacitor having one terminal connected to the drain of said MOS transistor, and said second capacitor having one terminal connected to the gate of said MOS transistor; said plurality of stages being connected in series between an input terminal and an output terminal by connecting said MOS transistors of said plurality of stages in cascade; means for applying a power supply voltage to the drain of said MOS transistor in the stage closest to said input terminal so that said power supply voltage is boosted by said MOS transistor in each of said stages thereby generating a boosted voltage which is higher than said power supply voltage at the source of said MOS transistor in the stage closest to said output terminal; a first clock signal generating means for generating a first clock signal, and supplying said first clock signal to another terminal of said first capacitor in each stage; and a second clock signal generating means for generating a second clock signal which has a larger amplitude than said power supply voltage, and supplying said second clock signal to another terminal of said second capacitor in each of said plurality of stages; wherein