Patent ID: 7872923
Filing Date: 2011-01-18
Classification: G11C

Abstract:
1. A sense amplifier circuit in a memory device, comprising: a pair of sense amplifiers; a pair of sense amplifier control lines connected to said pair of sense amplifiers and configured to control activation and deactivation of said pair of sense amplifiers; a first switching device connected to one of said sense amplifier control lines to maintain a first voltage level on said sense amplifier control line; a voltage clamping device connected to said one of said sense amplifier control lines to change said first voltage level thereon to a second voltage level; and a control circuit connected to said first switching device and said voltage clamping device to control operations thereof, wherein said control circuit is configured to turn on said first switching device and turn off said voltage clamping device prior to a power down mode, and wherein said control circuit is further configured to turn off said first switching device and turn on said voltage clamping device during said power down mode.