Patent ID: 9019755
Filing Date: 2015-04-28
Classification: B65D,G11C

Abstract:
1. A memory unit comprising: a plurality of memory cells that each have a memory element in which a resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting the memory cell as a drive target; a plurality of word lines and a plurality of first and second bit lines, each connected to one of the plurality of memory cells; and a drive section that selects at least one of the plurality of memory cells as the drive target and selectively changes the resistance state of the memory element of the memory cell selected as the drive target between a low resistance state and a high resistance state by applying electric potentials to the word line and the first and the second bit lines connected to the memory cell selected as the drive target, wherein the drive section performs a setting operation to change the resistance state from the high resistance state to the low resistance state for a first memory element located on one word line and a resetting operation to change the resistance state from the low resistance state to the high resistance state for a second memory element located on the one word line by: wherein P where ΔV is a non-zero number.