Patent ID: 8019951
Filing Date: 2011-09-13
Classification: G06F

Abstract:
1. A memory controller which controls a memory configured to be shared by a plurality of buses, comprising a plurality of bus interface units, a memory controller core unit, an internal bus and a memory interface unit, wherein said plurality of bus interface units receive commands from said plurality of buses, and convert the commands into commands receivable by said memory controller core unit via said internal bus, wherein said memory controller core unit includes a command controller which issues a received command to said memory interface unit, wherein said memory interface unit converts the received command from said memory controller core unit into a command corresponding to the memory, and wherein said internal bus exchanges commands between each of the plurality of bus interface units and said command controller, and wherein the memory controller further comprises a direct read data bus which transfers readout data from said memory interface unit to said internal bus without transferring the readout data via said command controller.