Patent ID: 8127189
Filing Date: 2012-02-28
Classification: G01R,G06F,H03K

Abstract:
1. An integrated circuit comprising: A. a TDI lead, a TDO lead, a TMS lead, and a TCK lead; B. test access port circuitry having a TDI input connected to the TDI lead, a TDO output connected to the TDO lead, a TMS input coupled to the TMS lead, and a TCK input coupled to the TCK lead, the test access port circuitry providing an enable serial output lead, an enable serial input lead, an input/output sync lead, and a Run Test/Idle lead; C. first gate circuitry having an input connected to the enable serial output lead, another input connected to the Run Test/Idle output lead, and an output enable output lead; D. second gate circuitry having an input connected to the enable serial input lead, another input connected to the Run Test/Idle output lead, and an input enable output lead; E. sync circuitry having a first input coupled to the input enable output lead, a second input connected to the input/output sync lead, a sync clock input connected to the TMS lead, and an input enable output; and D. serial communication circuitry having an output enable input connected to the output enable output lead and an input enable input connected to the input enable output lead.