Patent ID: 6236601
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A semiconductor memory device in which a semiconductor memory having partially faulty memory cells each of which is defective in the function of storing data is used as a part of or all of a storage medium, the data being stored, when holding the data or reading out the data thus held in said semiconductor memory device, in data administrative units of a fixed amount of data which is continuously transferred, said semiconductor memory device comprising:a faulty location registering circuit to register faulty locations containing therein the defective memory cells, each of which is defective in the storage function, in either ascending or descending order depending on the magnitude of address values appended to the data administrative units;alternative storage regions as storage regions with which the faulty locations are replaced in units of the fixed amount of data which is continuously transferred;an alternative location registering circuit to register therein the replacement locations when replacing the faulty locations registered in said faulty location registering circuit with said alternative storage regions;a fault registration retrieving circuit to retrieve said faulty location registering circuit in order to judge whether or not the storage location where holding or reading of the data is carried out corresponds to the faulty location;an access control circuit to carry out the control so as, when the storage location where the holding or reading of the data is carried out is registered in said faulty location registering circuit, to access the alternative region therefor by referring to alternative location registering circuit; anda registering updating circuit to carry out, when a faulty newly occurs, the reloading in accordance with the rule of either the ascending order or descending order in said faulty location registering circuit, the decision of the alternative location therefor and the update of said alternative location registering circuit.