Patent ID: 8174913
Filing Date: 2012-05-08
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell region comprising a plurality of nonvolatile memory cells; a spare region comprising a spare block configured to store data instead of a remedy target block in the memory cell region and comprising a defective memory cell; a nonvolatile memory fuse region configured to store remedy information for an access to the spare block, the nonvolatile memory fuse region comprising non-defective memory cells other than the defective memory cell in the remedy target block, or comprising memory cells in a first block of the spare region; an initial reading fuse configured to store a block address for identifying the remedy target block or the first block allocated as the nonvolatile memory fuse region, and a selection address configured to select a region in the remedy target block or a region in the first block allocated as the nonvolatile memory fuse region; and a controller configured to receive the remedy information from the nonvolatile memory fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information.