Patent ID: 7432748
Filing Date: 2008-10-07
Classification: G06F,H03K

Abstract:
1. A power-on reset (“POR”) circuit for a multi-voltage circuit, said POR circuit comprising: a POR node for a POR output signal; a pull-up circuit comprising a pull-up output node coupled to said POR node, and having pull-up input nodes for receiving a plurality of supply voltage signals, wherein said pull-up circuit comprises a plurality of PMOS transistors, each having a drain coupled to said POR node, and each having a source coupled to one of said pull-up input nodes; and a pull-down circuit comprising a pull-down output node coupled to said POR node, and having pull-down input nodes for receiving said plurality of supply voltage signals, wherein said pull down circuit comprises a plurality of NMOS transistors coupled in series between said POR node and a low reference potential, each of said NMOS transistors having a gate coupled to one of said pull-down input nodes; wherein said pull-up circuit and said pull-down circuit generate a high POR output signal at said POR node in response to ramp-up of a first supply voltage signal, wherein ramp-up of said first supply voltage signal occurs first in time, and wherein said pull-up circuit and said pull-down circuit generate a low POR output signal at said POR node in response to ramp-up of a last supply voltage signal, wherein ramp-up of said last supply voltage signal occurs last in time.