Patent ID: 8543856
Filing Date: 2013-09-24
Classification: G06F

Abstract:
1. A semiconductor device having a plurality of I/O pads, wherein the semiconductor device is operable in a low power mode, the semiconductor device comprising: at least one interface pad; a buffer circuit connected to the interface pad, wherein the buffer circuit includes, a power management controller (PMC) coupled to said I/O pads and said interface pad for supplying power thereto, wherein power to said I/O pads and said interface pad is disabled during said low power mode by assertion of a power on reset signal of said PMC; a first level shifter, connected to the second terminal of the resistor of the buffer circuit, for receiving the wake-up signal and shifting a voltage level of the wake-up signal from a analog supply high operation voltage level to a core operation voltage level; and a wake-up unit connected to the first level shifter for receiving the level-shifted wake-up signal, wherein the wake-up unit wakes up at least a part of said semiconductor device from said low power mode.