Patent ID: 8652913
Filing Date: 2014-02-18
Classification: H01L

Abstract:
1. A method, comprising: forming a masking material above a gate electrode of a P-type transistor, wherein said masking material covers sidewall and upper surfaces of said gate electrode; forming a strained silicon/germanium material in a recess formed adjacent to said masked gate electrode of said P-type transistor; forming a protection layer above said P-type transistor while said masking material covers said sidewall and upper surfaces of said gate electrode, wherein at least a first portion of said protection layer completely covers said strained silicon/germanium material; and forming drain and source regions at least partially in said silicon/germanium material in the presence of said protection layer, wherein forming said drain and source regions comprises performing an implantation process to implant P-type dopants through said first portion of said protection layer.