Patent ID: 6121821
Filing Date: 2000-09-19
Classification: G11C

Abstract:
A booster circuit having a plurality of booster cells tandem-connected, each of the boosters having a transfer transistor and a capacitor, an input terminal, a drain, and a gate of the transfer transistor being connected, a source of the transfer transistor being an output terminal, a first terminal of the capacitor being connected to the source of the transfer transistor, a clock signal being supplied to a second terminal of the capacitor,wherein the transfer transistor is composed of a triple-well having a first well and a second well, the first well being formed on a semiconductor substrate, the second well being formed on the first well, andwherein the semiconductor substrate is connected to a reference voltage, a diffusion layer in the first well, a first diffusion layer in the second well, a second diffusion layer in the second well, the first terminal of the capacitor, and the gate of the transfer transistor being connected, the conduction type of the first well being the same as the conduction type of the diffusion layer in the first well, the conduction type of the second well being the same as the conduction type of the first diffusion layer in the second well, the conduction type of the second well being different from the conduction type of the second diffusion layer in the second well.