Patent ID: 9171606
Filing Date: 2015-10-27
Classification: G11C

Abstract:
1. A method for accessing a DRAM having first and second bit lines connected to a sense amplifier, the method comprising: inactivating an equalize transistor connected between the first bit line and the second bit line; inactivating a first dummy word line to disconnect a first dummy memory cell from the first bit line; activating a first word line to connect a first memory cell to the first bit line; activating the sense amplifier; inactivating the first word line to disconnect the first memory cell from the first bit line; activating the first dummy word line to connect the first dummy memory cell to the first bit line; inactivating the sense amplifier; and activating the equalize transistor, wherein a second dummy word line connected to a second dummy memory cell remains activated to connect the second dummy memory cell to the second bit line and a second word line connected to a second memory cell remains deactivated to disconnect the second memory cell from the second bit line throughout the accessing.