Patent ID: 6346828
Filing Date: 2002-02-12
Classification: G06F

Abstract:
A tri-state driver controller comprising:a first latch to receive a data input signal, the first latch clocked by a pulsed clock signal to generate a first latch output; a second latch to receive the first latch output, the second latch clocked by an inverted pulsed clock signal to generate a latched data output signal to couple into a data input of a tri-state buffer; a third latch to receive an enable input signal, the third latch clocked by the pulsed clock signal to generate a latched enable signal; and an enable pulse controller having an input coupled to the third latch output to receive the latched enable signal and another input to couple to a global clock signal, the enable pulse controller to gate the latched enable signal to generate a clocked tri-state enable signal to couple into an enable input of a tri-state buffer.