Patent ID: 7272739
Filing Date: 2007-09-18
Classification: H04J,H04Q

Abstract:
1. An apparatus for aligning data, comprising: a first buffer operable to receive a first data signal, a first write address signal, and a first clock signal, the first buffer operable to store a particular byte of the first data signal in a particular location of the first buffer in response to the first write address signal and the first clock signal, the first buffer operable to receive a recovered clock signal, the first buffer operable to transmit a stored first data signal in response to the recovered clock signal, the recovered clock signal operable to control a read address of the first buffer in transmitting the first data signal from the first buffer; an output timer operable to receive the recovered clock signal and a recovered reference signal, the output timer operable to control the read address of the first buffer to place the first data signal in alignment with a second data signal.