Patent ID: 6376878
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A MOS-gated semiconductor device comprising:a substrate of semiconductor material having top and bottom surfaces; a well region of a first conductivity and extending to the top surface; a pair of source regions of a second conductivity, disposed in the well region and extending to the top surface; a gate and channel region disposed between the source regions; a drain zone of a second conductivity disposed beneath the gate the well region; a drain contact region of a second conductivity, highly doped, and extending from the drain zone to the opposite surface of the substrate; a pair of extended well regions extending from distal ends of the well region in a direction through a substantial portion of the drain zone and in a direction toward the drain contact, said extended well regions proximate to but not contacting said drain contact region and having a first conductivity and generating opposing induced electrical fields at their respective junctions with the drain zone.