Patent ID: 7224294
Filing Date: 2007-05-29
Classification: G11B,H03M

Abstract:
1. A compressing device, comprising: delay circuits of four stages for sequentially delaying each sampling data inputted therein in sequence; a multiplying/adding circuit for performing weighted addition on data outputted from each of the delay circuits, the weighted addition being performed according to a value of a digital basic function, whereby thinned-out data is produced from the sequentially inputted sampling data; and a first multiplying/adding circuit for adding output data from the delay circuits of the second and third stages and then multiplying the added data by 9; a second multiplying/adding circuit for adding output data from the delay circuits of the first and fourth stages and then multiplying the added data by −1; and a third multiplying/adding circuit for adding output data from the first multiplying/adding circuit and output data from the second multiplying/adding circuit and then multiplying the added data by 1/16.