Patent ID: 8634268
Filing Date: 2014-01-21
Classification: G11C

Abstract:
1. A memory circuit comprising: a first memory bank controlled by a first plurality of cell selection signals; a first decoder coupled to the first memory bank and configured to receive a plurality of address control signals through a first plurality of address control signal lines and to generate the first plurality of cell selection signals responsive to the plurality of address control signals; a second memory bank controlled by a second plurality of cell selection signals; a second decoder coupled to the second memory bank and configured to receive a plurality of inverted address control signals through a second plurality of address control signal lines and to generate the second plurality of cell selection signals responsive to the plurality of inverted address control signals; and an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals from the first plurality of address control signal lines into the plurality of inverted address control signals on the second plurality of address control signal lines, wherein the first decoder and the second decoder are configured to have one of the following configurations: