Patent ID: 7390713
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. A method for forming trench memory cell structures each having a trench capacitor and a selection transistor for selectively addressing the trench capacitor, the method comprising: forming trench capacitors, each having a storage electrode formed as filling of a hole trench introduced into a semiconductor substrate from a substrate surface; depositing and patterning a gate conductor layer stack on a gate dielectric bearing on the semiconductor substrate to form gate stacks, wherein in the semiconductor substrate in each case a node section and a bit contact section of an active zone of the respective selection transistor is defined and wherein the bit contact section and the node section face each other at the respective gate stack; applying a conformal base layer of a first insulator layer to cover a relief formed by the gate stacks; forming by implantation doped reinforcement zones at least in the node sections of the semiconductor substrate; and then applying a conformal covering layer of the first insulator layer to cover the base layer.