Patent ID: 6570786
Filing Date: 2003-05-27
Classification: G11C,H01L

Abstract:
A NAND-type memory array, comprising:a P type substrate; a triple P well formed in said P type substrate; first through fourteenth N+ junctions formed in said triple P well; a P+ junction formed in said triple P well, wherein said first through eighth N+ junctions, said P+ junction, and said ninth through fourteenth N+ junctions are sequentially formed within said triple P well; first through sixth floating gates formed on said triple P well; a source node connected to said second N+ junction; first and second source select lines each formed at both sides of said second N+ junction; a bit line connected to said seventh and eleventh N+ junctions; a first drain select line formed at one side of said N+ junction; a second drain select line formed at one side of said eleventh N+ junction; a first pass gate formed between said second source select line and said first drain select line; a first cell gate formed between said second source select line and said first drain select line; a second pass gate formed between said second source select line and said first drain select line; a third pass gate formed on said triple P well on said second drain select line side; a second cell gate formed on said triple P well on said second drain select line side; a fourth pass gate formed on said triple P well on said second drain select line side; an interconnect line connecting said eighth N+ junction, said P+ junction and said ninth N+ junction; a program well select gate formed between said seventh N+ junction and said eighth N+ junction; a P well node connected to said tenth N+ junction between said ninth N+ junction and said eleventh N+ junction; and a triple P well select gate formed between said ninth N+ junction and said tenth N+ junction.