Patent ID: 6157588
Filing Date: 2000-12-05
Classification: G11C

Abstract:
A semiconductor memory device, comprising:first and second main blocks;a first global input/output line arranged to traverse said first and second main blocks; anda second global input/output line arranged adjacent to and in a complementary relation with said first global input/output line,each of said first and second main blocks includinga plurality of sub blocks,a plurality of main word lines arranged longitudinally across said plurality of sub blocks,a local input/output line pair, anda transfer gate connected between said local input/output line pair and said first and second global input/output lines,each of said plurality of sub blocks includinga plurality of memory cells arranged in rows and columns,a plurality of sub word lines arranged corresponding to said plurality of main word lines and in said rows,a plurality of sub word line drivers driving said plurality of sub word lines,a plurality of bit line pairs arranged in said columns, anda plurality of column selection gates arranged corresponding to said plurality of bit line pairs and each connected between said corresponding bit line pair and said local input/output line pair,said semiconductor memory device further comprisinga row decoder substantially simultaneously selecting one of said plurality of main word lines included in said first main block and one of said plurality of main word lines included in said second main block,at least one of said sub block included in said first main block further includinga first activation signal line arranged adjacent to said first global input/output line and transmitting a signal for activating said sub word line driver, andat least one of said sub blocks included in said second main block further including a second activation signal line arranged adjacent to said second global input/output line and transmitting a signal for activating said sub word line driver.