Patent ID: 7443218
Filing Date: 2008-10-28
Classification: H03K

Abstract:
1. A semiconductor integrated circuit device comprising: a pulse generator circuit to which an external clock signal is input, and which outputs a pulsed clock signal in synchronization with a transition of said external clock signal from a first level to a second level, a pulsed clock signal having a second level period shorter than that of said external clock signal; a data latch circuit to which an input data signal and an internal clock signal are input, and which incorporates a value of said input data signal during a period when the internal clock signal is at a fourth level, retains the incorporated value during a period when the internal clock signal is at a third level, and outputs the incorporated value as a retained data signal; and a data comparator circuit to which said pulsed clock signal, said input data signal of said data latch circuit, and said retained data signal are input, wherein said data comparator outputs the internal clock signal at the third level during a period when said pulsed clock signal is at the first level, wherein said data comparator compares said input data signal with said retained data signal during a period when said pulsed clock signal is at the second level, outputs said internal clock signal at the fourth level when the comparison result is inconsistent, and outputs said internal clock signal at the third level when the comparison result is consistent, and wherein, in said data comparator circuit, when the pulsed clock signal is at the first level, transistors to which said input data signal, said retained data signal, and inverted values of the input data signal and the retained data signal are respectively input is cut off from one of a power supply and ground by the pulsed clock signal.