Patent ID: 6229744
Filing Date: 2001-05-08
Classification: G11C

Abstract:
A semiconductor memory device with a function of equalizing voltages of a pair of datalines, comprising:a memory cell array;a bit line sense amplifier, connected to the memory cell array via a pair of bit lines;the pair of datalines, including a first dataline and a second dataline complementary to each other connected to the bit line sense amplifier;an equalization means, connected across the first and the second datalines;a dataline sense amplifier, connected across the pair of datalines to connect to the equalization means;an NMOS transistor, comprising a source region connected to ground, a gate to receive a first signal and a drain region coupled to the first dataline; anda PMOS transistor, comprising a source region connected to a supplied voltage, a gate to receive a second signal and a drain region coupled to the second dataline.