Patent ID: 6521990
Filing Date: 2003-02-18
Classification: H01L,H05K

Abstract:
A semiconductor package comprising:a semiconductor chip having a plurality of electrode pads on its active surface; a printed circuit board, said semiconductor chip mounted thereon, the printed circuit board comprising: a board body having an upper surface and an opposing lower surface; an upper wiring layer formed on the upper surface of the board body, the upper wiring layer including a chip-mounting portion for mounting the semiconductor chip, board pads formed around the chip-mounting portion and electrically connected to said semiconductor chip, and an upper heat dissipation layer around said chip-mounting portion; and a lower wiring layer including a lower heat dissipation layer formed on the lower surface of the board body; first heat-dissipating via holes formed through the board body between the chip-mounting portion and the lower heat dissipation layer, the first heat-dissipating via holes filled with a thermally conductive material for dissipating heat from the chip through the board body toward the lower wiring layer; second heat-dissipating via holes formed through the board body below said upper heat dissipation layer, the second heat-dissipating via holes filled with a thermally conductive material for dissipating heat generated from the chip through the board body toward the upper heat dissipation layer; and an electrically insulating encapsulant covering said semiconductor chip; and a heat sink thermally connected to the encapsulant, and wherein a lower surface of said heat sink is thermally connected to the upper heat dissipation layer.