Patent ID: 6195278
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A content addressable memory comprising:a memory cell having a true output and a complement output;true and complement bit lines;a first field effect transistor having a source/drain connected to the true output of the memory cell, a drain/source connected to the true bit line, and a gate;a second field effect transistor having a source/drain coupled to the complement output of the memory cell, a drain/source coupled to the complement bit line, and a gate;a word line connected to the gates of the first and second transistors;a third field effect transistor of a first channel type having a source/drain coupled to a first match line segment, a drain/source coupled to a second match line segment, and a gate;true and complement comparison bit lines;a fourth field effect transistor of a second different channel type having a source/drain coupled to the true comparison bit line, a drain/source coupled to the gate of the third transistor, and a gate coupled to the complement output of the memory cell; anda fifth field effect transistor of the second channel type having a source/drain coupled to the complement comparison bit line, a drain/source coupled to the gate of the third transistor, and a gate coupled to the true output of the memory cell.