Patent ID: 6125381
Filing Date: 2000-09-26
Classification: G06F,H03K

Abstract:
A recursively partitioned carry select adder, said carry select adder comprising means for computing an n bit sum and carry (s.sub.0, c.sub.0) of two n bit numbers (a,b) without carry in and another n bit sum and carry (s.sub.1, c.sub.1) of said two n bit numbers with carry in, wherein n is an integer greater than 1 and said means for computing comprisesan m bit wide recursively partitioned carry select adding device comprising means for computing an m bit sum and carry (S.sub.0h, C.sub.0h) of an m bit more significant part of said two n bit numbers (a,b) without carry in and another m bit sum and carry (S.sub.1h, c.sub.1h) of said m bit more significant part of said two n bit numbers with carry in, said m being less than n;an n-m bit wide recursively partitioned carry select adding device comprising means for computing an n-m bit sum and carry (s.sub.0l, c.sub.0l) of an n-m bit less significant part of said two n bit numbers (a,b) without carry in and another n-m bit sum and carry (s.sub.1l, c.sub.1l) of said n-m bit less significant part of said two n bit numbers with carry in;and two m+1 bit wide 2:1 multiplexers or one m+1 bit wide 2:2 multiplexer, wherein said 2:1 multiplexers or said 2:2 multiplexer comprise means for selecting between the sums (S.sub.0h, S.sub.1h) and the carries (c.sub.0h, C.sub.1h) of said m bit more significant part according to said carries (c.sub.0l, c.sub.1l) of said less significant part; anda plurality of XNOR gates and XOR gates for computing 1 bit sums of respective corresponding bits of said two n bit numbers (a,b) with and without carry in, and either a plurality of AND gates and OR gates for computing the carries with and without carry in or a plurality of NAND and NOR gates for computing inverted carries with and without carry in.