Patent ID: 6252277
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method for forming and embedded polysilicon gate MOSFET comprising:(a) providing a silicon wafer having an active region of a first conductivity type surrounded by a field isolation;(b) depositing a doped oxide layer on said silicon wafer;(c) forming an opening in said doped oxide layer, said opening bridging across said active region;(d) forming silicon nitride spacers along the periphery of said opening;(e) etching a trench in said opening;(f) depositing a silicon oxide layer over said silicon wafer;(g) planarizing said silicon oxide layer;(h) etching said silicon oxide layer with a calibrated wet etch to expose the surface of said silicon wafer and said spacers while leaving a pocket of said silicon oxide layer in said trench, the surface of said pocket extending above the base of said spacers by a distance;(i) selectively depositing an epitaxial silicon layer of a second conductivity type on said wafer, thereby forming source/drain regions;(j) further etching said pocket to expose silicon along the sidewalls of said trench and leaving a residual portion of said pocket over the base of said trench;(k) implanting ions of said second conductivity type into said sidewalls of said trench, thereby forming LDD regions;(l) removing said residual portion;(m) forming a gate oxide on the walls and base of said trench and a corresponding oxide layer on the surface of said source/drain regions;(n) depositing a polysilicon layer over said wafer;(o) planarizing said polysilicon layer;(p) etching back said polysilicon layer, stopping in said corresponding oxide layer and leaving the level of the surface of said polysilicon in said trench between about 1,000 and 2,000 Angstroms above the base of said spacers, thereby forming an embedded gate electrode;(q) removing said corresponding oxide layer, thereby exposing said source/drain regions; and(r) forming a metal silicide on said source/drain regions and said polysilicon layer.