Patent ID: 8188803
Filing Date: 2012-05-29
Classification: H03H,H04J,H04L

Abstract:
1. An apparatus for digital up converting in a mobile communication system, the apparatus comprising: a Selectable Input Logic (SIL) for receiving an input of a signal from a channel card, and for performing decimation at a decimation rate variable depending on a frequency bandwidth of the input signal; a Scalable Clock Distribution Logic (SCDL) for controlling a clock frequency depending on the frequency bandwidth of the input signal; a filter logic for receiving a clock from the SCDL, for performing channel filtering for the decimated signal according to standards regulated depending on the frequency bandwidth of the input signal, and for performing interpolation at an interpolation rate variable depending on the frequency bandwidth of the input signal; and a mixer logic for up-converting the signal provided from the filter logic.