Patent ID: 8345113
Filing Date: 2013-01-01
Classification: G06F,H04N

Abstract:
1. An image processing apparatus comprising: a data memory configured to store image data; a first register configured to hold a first two-dimensional address indicating a position of a read pointer in a frame of the image data; a control circuit configured to control the first two-dimensional address held by the first register on the basis of a width of the frame and a height of the frame; a load/store unit configured to read reading target pixel data from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the read pointer by a combination of two immediate values and write pixel data obtained by performing predetermined operation processing for the target pixel data which has been read, into a predetermined area of the data memory; and an address calculation unit configured to, when the load/store unit reads the reading target pixel data from the data memory, calculate an address at which the reading target pixel data is stored, on the basis of the first two-dimensional address, the combination of immediate values and the width of the frame.