Patent ID: 8154916
Filing Date: 2012-04-10
Classification: G11C

Abstract:
1. A nonvolatile memory circuit comprising: a first p-channel MOS transistor including a first source/drain electrode and a second source/drain electrode, the first source/drain electrode being connected to a first wiring line; a second p-channel MOS transistor including a third source/drain electrode and a fourth source/drain electrode, the third source/drain electrode being connected to the first wiring line, the fourth source/drain electrode being connected to a gate of the first p-channel MOS transistor, the second p-channel MOS transistor including a gate connected to the second source/drain electrode of the first p-channel MOS transistor; a first n-channel spin MOS transistor including a fifth source/drain electrode and a sixth source/drain electrode, the fifth source/drain electrode being connected to a second wiring line, the sixth source/drain electrode being connected to the second source/drain electrode of the first p-channel MOS transistor, the first n-channel spin MOS transistor including a gate connected to the fourth source/drain electrode of the second p-channel MOS transistor; a second n-channel spin MOS transistor including a seventh source/drain electrode and an eighth source/drain electrode, the seventh source/drain electrode being connected to the second wiring line, the eighth source/drain electrode being connected to the fourth source/drain electrode of the second p-channel MOS transistor, the second n-channel spin MOS transistor including a gate connected to the second source/drain electrode of the first p-channel MOS transistor; a first n-channel MOS transistor including a ninth source/drain electrode and a tenth source/drain electrode, the ninth source/drain electrode being connected to the second source/drain electrode of the first p-channel MOS transistor, the tenth source/drain electrode being connected to a third wiring line, the first n-channel MOS transistor including a gate connected to a fourth wiring line; and a second n-channel MOS transistor including an eleventh source/drain electrode and a twelfth source/drain electrode, the eleventh source/drain electrode being connected to the fourth source/drain electrode of the second p-channel MOS transistor, the twelfth source/drain electrode being connected to a fifth wiring line, the second n-channel MOS transistor including a gate connected to the fourth wiring line.