Patent ID: 6195297
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A semiconductor memory device comprising:first and second power supply terminals;a plurality of bit lines;a memory cell array including a plurality of read-only memory cells connected to said bit lines;a plurality of sense amplifiers connected to said first power supply terminal, each of said sense amplifiers including a first MOS transistor connected to one of said bit lines;a reference voltage generating circuit for generating a reference voltage and applying said reference voltage to a gate of said first MOS transistor;a bit line selection circuit, connected to said sense amplifiers, for generating a plurality of bit line selection signals for selecting said bit lines respectively;a plurality of second MOS transistors, each connected between one of said bit lines and said second power supply terminal;a plurality of inverters, each connected between said bit line selection circuit and one of said second MOS transistors, so that said second MOS transistors are controlled by inverted signals of said bit line selection signals;a data sense recognition signal generating circuit for generating a data sense recognition signal; anda plurality of NOR circuits each, having a first input connected to one of said inverters, a second input connected to said data sense recognition signal generating circuit, and an output connected to one of said second MOS transistors.