Patent ID: 6038185
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A serial memory device comprising:a memory array arranged in a plurality of rows, each row having a plurality of memory locations, each memory location having a plurality of data bits, the memory array having bit lines for outputting the data bits of every memory location of a selected row;a decoder circuit coupled to receive the bit lines from the memory array, the decoder circuit including data lines and gating circuitry which selectively couples the bit lines of every memory location of a selected row in one to one correspondence with the data lines, the decoder circuit further including address lines operatively coupled to the gating circuitry to couple selected ones of the bit lines to their corresponding data lines;a first plurality of N sense amplifiers having inputs in electrical communication with first data lines corresponding to every Nth memory location of a selected row; andat least one sense amplifier having an input in electrical communication with one of the data lines of every memory location in a selected row.