Patent ID: 6487707
Filing Date: 2002-11-26
Classification: G06F

Abstract:
A layout design system of semiconductor IC device, comprising:a first design section which decides a placement position of a clock buffer to be a basis of a clock signal in each of a plurality of blocks whose cell layout has been fixed, and also designs a first clock tree in each block based on the decided placement position of the clock buffer; a second design section, which designs a second clock tree between the blocks based on the placement position of the clock buffer in the blocks decided by said first design section and based on a delay value of the clock signal propagated in the first clock tree, and for adding an additional buffer; and an adjustment section which adjusts a placement position of the additional buffer so that the placement position of the additional buffer is in accordance with tee placement position of at least one of the cells of the corresponding block if there is the additional buffer added by said second design section.