Patent ID: 9195587
Filing Date: 2015-11-24
Classification: G06F,G11C

Abstract:
1. A method for operating a computer memory, comprising: determining a dynamic read case designation for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups, the dynamic read case designation for any given one of the multiple wordline regions specifying a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions, wherein determining the dynamic read case designation for a given wordline region includes determining a wordline read voltage that when applied to read memory cells of a sampling wordline of the given wordline region will yield a fail bit count less than a fail bit count limit, wherein the memory cells of the sampling wordline of the given wordline region are used to store normal operational data, and wherein the fail bit count is determined by putting data read from the memory cells of the sampling wordline through an error correction code checking process; and folding the number of single-level cell logic groups into a multi-level cell block, the folding including reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation as determined for the wordline region within which the read memory cells reside.