Patent ID: 7208837
Filing Date: 2007-04-24
Classification: H01L,Y10T

Abstract:
1. An integrated circuit comprising: a damascened intermediate metal layer fabricated in a first inter-metal dielectric (IMD) layer; a bondable metal pad defined on a stress-buffering dielectric layer having a thickness T that is deposited on said first IMD layer, and said bondable metal pad being disposed directly above and electrically connected to said damascened intermediate metal layer through a plurality of via plugs integrated with said bondable metal pad; a damascened metal frame fabricated in a second IMD layer under said first IMD layer, wherein said stress-buffering dielectric layer is structurally denser and less porous than any of said first IMD layer and second IMD layer, and wherein when the thickness T of said stress-buffering dielectric layer is greater than 2000 angstroms, said damascened metal frame is omitted; a portions of active circuit components of said integrated circuit disposed directly under said damascened metal frame; and a passivation layer comprising silicon oxide, silicon nitride and polyimide covering said stress-buffering dielectric layer and partially covering said bondable metal pad.