Patent ID: 6088744
Filing Date: 2000-07-11
Classification: G06F,H04L

Abstract:
A multi-port buffer providing multi-level caching, comprising:buffer management logic, comprised of:a plurality of data ports;a plurality of FIFO buffers, wherein there is at least one FIFO buffer each for each said data port of said multi-port buffer, and wherein said FIFO buffers may comprise any of input and output buffers; andsequencing logic therefor; anda random access memory (RAM) for caching data routed to and from said FIFO buffers via said ports; anda microprocessor for moving data into and out of said RAM from one of said ports;wherein said microprocessor moves data into said RAM from one of said ports by first instructing a control logic circuit to clear an input FIFO buffer associated with said port and disable associated sequencing logic,wherein said microprocessor then writes a FIFO start address to said FIFO buffer's address counter,wherein said microprocessor next enables said sequencing logic for said input FIFO buffer,wherein said sequencing logic attempts to keep said FIFO buffer empty by moving data to said RAM,wherein said sequencing logic detects that said FIFO buffer is not empty when data are written to said input FIFO buffer via said port by an associated external device,wherein a synchronous arbiter resolves simultaneous RAM accesses, andwherein said sequencing logic increments said FIFO buffer's RAM address counter after each RAM write.