Patent ID: 6954927
Filing Date: 2005-10-11
Classification: G06F

Abstract:
1. A method for optimizing a software pipelineable loop in a software code, wherein the loop comprises one or more pipelined stages and one or more loop operations, the method comprising: (a) evaluating an initiation interval time (IN) for a pipelined stage of the loop; (b) determining a loop operation time latency (Tld); (c) determining a number of loop operations (Np) from the pipelined stages to peel based on IN and Tld; (d) peeling Np copies of the loop operation, wherein the number of peeled loop operations equals (Tld+IN−1)/IN; (e) copying the peeled loop operations before the loop in the software code; (f) allocating a vector of registers; (g) assigning results of the peeled loop operations and a result of an original loop operation to the vector of registers; and (h) assigning memory addresses to the results of the peeled loop operations and original loop operation.