Patent ID: 6064613
Filing Date: 2000-05-16
Classification: G11C

Abstract:
A two stage memory sense amplifier where the second stage is an output buffer amplifier and where the first stage is a semiconductor memory pre-sense amplifier having a pair of differential inputs and a pair of complementary outputs and where the memory pre-sense amplifier consists of two sections, each section having a pair of differential input nodes and a pair of complementary output nodes which provide feedback between said sections so as to result in an output response with reduced delay comprising:a first and second memory data line connected respectively to a first and second input of a first pre-sense amplifier section;a first and second memory data line connected respectively to a second and first input of a second pre-sense amplifier section;a first output node and a complementary second output node on said first pre-sense amplifier section where said first output node is a first output of said memory pre-sense amplifier;a first output node and a complementary second output node on said second pre-sense amplifier section where said first output node is a second output of said memory pre-sense amplifier;a mechanism for feedback implementation on each of said pre-sense amplifier sections;wherein said mechanism for feedback implementation on said first pre-sense amplifier section is connected to said second output node of said second pre-sense amplifier section;wherein said mechanism for feedback implementation on said second pre-sense amplifier section is connected to said second output of said first pre-sense amplifier section; andwherein said pre-sense amplifier connections provide a feedback such as to limit the signal excursion on said first and second memory pre-sense amplifier outputs thereby reducing the delay of the output response of said memory pre-sense amplifier to an input signal on the differential inputs of said memory pre-sense amplifier.