Patent ID: 6449578
Filing Date: 2002-09-10
Classification: G06F

Abstract:
An apparatus for determining RC delays associated with one or more output nodes of a network and an input node of the network, the network being comprised in an integrated circuit, the apparatus comprising:logic configured to perform a rules checker algorithm, wherein when the rules checker algorithm is performed, the rules checker algorithm analyzes information relating to the network to determine an RC delay between each output node of the network and the input node of the network, and said logic receives information associated with a netlist from a static timing analyzer, the netlist comprising the information relating to the network, the information describing parasitic resistance and capacitance characteristics of the network, the rules checker algorithm utilizing information associated with the netlist to generate a Spice deck associated with the network, the Spice deck including control information which describes a manner in which the network is to be simulated, the rules checker algorithm calling a Spice simulation routine which utilizes the Spice deck to simulate the network, the Spice simulation routine generating a Spice results file which comprises voltage waveform information, the voltage waveform information describing voltage waveforms at each output node and at the input node, the rules checker algorithm comparing the waveform at one of the output nodes with the waveform at the input node to determine any RC delays between the output node and the input node.