Patent ID: 7705644
Filing Date: 2010-04-27
Classification: H03L

Abstract:
1. A delay locked loop (DLL) circuit comprising: a delay matrix formed of M delay chains including N delay cells connected in series; an interpolator connected to said delay matrix configured to receive a clock signal and to generate M output signals at equal interval phase differences corresponding to Td/M where Td is the delay time associated with said delay cells, said interpolator supplying said output signals to the delay matrix; a phase detector configured to receive an output signal from a first delay cell and a last delay cell of said N delay cells in a first delay chain among said M delay chains, said phase detector detecting a phase difference between said output signal from said first delay cell and said output signal from said second delay cell; an electric charge pump connected to said phase detector and configured to generate a control voltage in response to said output signals of said phase detector; and a bias control circuit disposed between said electric charge pump and said delay matrix, said bias control circuit receiving said control voltage and generating bias voltages to control the delay cells of said delay matrix.