Patent ID: 7570515
Filing Date: 2009-08-04
Classification: G11C

Abstract:
1. For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells having a non-volatile memory storage portion for determining an electrically alterable voltage threshold value, electrons being capable of being injected into the non-volatile memory storage portion, an apparatus for operating the electrically alterable non-volatile multi-level memory device, comprising: means for determining a status of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a plurality of states including at least a first level state of an erased state, a second level state, a third level state and a fourth level state of a plurality of programmed states, a level distance to the fourth level state from the first level state being larger than a level distance to the third level state from the first level state and a level distance to the third level state from the first level state being larger than a level distance to the second level state from the first level state, and means for controlling an electrically alterable voltage threshold value of the at least one non-volatile multi-level memory cell to a value which responds to a first bit received into a first buffer and a second bit received into a second buffer of digital data to be stored in the at least one non-volatile multi-level memory cell, wherein the first bit to be stored in the at least one non-volatile multi-level memory cell is digital data of one block data and the second bit to be stored in the least one non-volatile multi-level memory cell is digital data of another block data, and wherein said another block data is received from an exterior of the electrically alterable non-volatile multi-level memory device after said one block data is programmed.