Patent ID: 7629218
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A method of manufacturing a capacitor, comprising: forming a mold layer on an etch stop layer; partially etching the mold layer by a first etching process to form a first contact hole exposing the etch stop layer; partially etching the mold layer by a second etching process to form a second contact hole having a dimension substantially wider than that of the first contact hole; selectively etching the exposed etch stop layer by a third etching process to form a third contact hole exposing a pad in an insulation layer; removing a native oxide layer on the exposed pad by a fourth etching process to form a capacitor contact hole, wherein the fourth etching process is performed without expanding the third contact hole; forming a lower electrode in the capacitor contact hole; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.