Patent ID: 7000070
Filing Date: 2006-02-14
Classification: G06F

Abstract:
1. A disk array controller comprising a plurality of disk array control units, wherein each of said plurality of disk array control units includes: a channel interface unit having an interface with a host computer; a disk interface unit having an interface with a magnetic disk drive; and a cache memory unit for storing data read/to be written from/in said magnetic disk drive; and means for connecting both said channel interface unit and said disk interface unit to said cache memory unit; wherein said channel interface unit transfers data between an interface of said host computer and said cache memory unit in response to a data read/write request from said host computer while said disk interface unit transfers data between said magnetic disk drive and said cache memory unit, thereby allowing said disk array control unit to read/write data; wherein said connecting means used for the connection among said plurality of disk array control units is configured by a plurality of switches to be increased in a scalable manner and each of said plurality of switches has an output destination path table and a path selector used to form a logical mesh connection path to/from another switch and reform the path-topology of said logical mesh connection when a switch is added to said means for connecting; wherein each of said plurality of switches is provided with the minimum necessary number of ports by merging a plurality of paths corresponding to said plurality of switches and setting them in the same physical path so as to form a logical mesh connection path from each of said switches to other switches with a redundant path having a separated physical route; and wherein when four of said switches are to be connected to said means for connecting said plurality of disk array control units and disposed like a matrix, each of said four switches having five switch connection ports and being connected to its adjacent switches through two direct-connection physical ports to form a redundant path thereto while each of said switches is connected to its diagonal switches through a direct connection physical port respectively and through an adjacent switch by sharing one of said two direct-connection physical ports with said adjacent switch to form a redundant path.