Patent ID: 8171261
Filing Date: 2012-05-01
Classification: G06F

Abstract:
1. A method comprising: stalling dispatches of newer memory load instructions, which are newer in program order than a load fencing instruction, from a memory subsystem of a processor; allowing a newer memory store instruction, which is newer than the load fencing instruction in the program order, to retire; allowing older memory load instructions, which are older in the program order than the load fencing instruction, to be globally observed; and after allowing the newer memory store instruction to retire, dispatching the load fencing instruction when all of the older memory load instructions have been globally observed, wherein the load fencing instruction is dispatched before all of the older memory load instructions have completed, wherein the load fencing instruction is treated as a non-operation (NOP) after it is dispatched, and wherein the load fencing instruction does not have a data operand.