Patent ID: 7349281
Filing Date: 2008-03-25
Classification: G11C

Abstract:
1. An anti-fuse memory circuit comprising: first and second anti-fuse elements each having first and second ends, the first ends thereof being interconnected; a program voltage generating circuit which generates a programming voltage during a programming period to program the first and second anti-fuse elements, and applies the programming voltage to a common connection node of the first ends of the first and second anti-fuse elements; a read voltage generating circuit which generates a readout voltage during a readout period to read out data from the first and second anti-fuse elements, and applies the readout voltage to the common connection node of the first ends of the first and second anti-fuse elements; a first transistor being turned on by a first select signal during the programming period, a current path of the first transistor being connected to between the second end of the first anti-fuse element and a reference potential node; a second transistor having a current path thereof being connected to between the second end of the second anti-fuse element and the reference potential node, the second transistor being turned on by a second select signal during the programming period; a switch element which is connected to the first ends of the first and second transistors being interconnected, the switch element being put in an off state during the programming period and in an off state during the readout period; and a sense amplifier which is connected at an input terminal to the first end of the switch element, the sense amplifier being sensed data read out from the first and second anti-fuse elements.