Patent ID: 8683182
Filing Date: 2014-03-25
Classification: G06F

Abstract:
1. In a programmable processor having an instruction path, a data path, a register file having at least a source register and a result register coupled to the data path, and having an execution unit coupled to the instruction path and the data path operable to decode and execute group instructions received from the instruction path, a method comprising: decoding a single group floating-point instruction indicating (i) the source register, (ii) the result register, and (iii) a source precision and a result precision, the result precision being a factor of two different than the source precision; on an instruction-by-instruction basis, dynamically partitioning data from the source register into multiple source floating-point data elements each having the source precision; converting each of the multiple source floating-point data elements to the result precision, thereby forming multiple result floating-point data elements; and catenating the multiple result floating-point data elements in the result register.