Patent ID: 6218689
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method for providing a NAND-type flash memory device, comprising:(a) forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate;(b) forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line resistance problem and a charge gain/charge loss problem wherein the doped amorphous silicon layer has a dopant level between approximately 5.times.10.sup.18 and 8.times.10.sup.19 ions/cm.sup.3 of phosphorus, and wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square;(c) forming an insulating layer on the doped amorphous silicon layer;(d) forming a control gate layer on the insulating layer; and(e) etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure.