Patent ID: 6925022
Filing Date: 2005-08-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; an internal data bus; row select circuitry activated in response to an array activation instructing signal, for selecting a row in said memory cell array, said row select circuitry selecting a first row of said memory cell array according to a first address and selecting a second row of said memory cell array according to a second address; a rearrangement data bus provided separately from said internal data bus; column select circuitry activated when a data rearrangement write instructing signal is deactivated, for selecting a column of said memory cell array on which a memory cell on said first row is located according to a column address signal, to couple a selected column with said internal data bus; rearrangement column select circuitry activated when said data rearrangement write instructing signal is activated, for selecting a column of said memory cell array on which a memory cell on said second row is located according said column address signal, to couple a selected column with said rearrangement data bus; a preamplifier for amplifying and latching data on said internal data bus; and a data buffer activated when a data rearrangement operating mode instructing signal is activated, for transferring data outputted by said preamplifier onto said rearrangement data bus.