Patent ID: 8275598
Filing Date: 2012-09-25
Classification: G06F

Abstract:
1. A computer-implemented method of performing a software table walk during test verification in a computer simulation, the computer-implemented method comprising utilizing a specific hardware system that performs the steps of: loading a Translation Lookaside Buffer (TLB) interrupt handler into a test generator, wherein the test generator randomly generates instructions for a test program to be virtually executed within a computer simulation; populating the computer simulation with at least one Translation Lookaside Buffer (TLB), wherein the TLB contains a sub-set of entries from a page table, wherein entries from the page table map a virtual address to a real address in the computer simulation, and wherein the virtual address is for data used by an instruction from the test program; utilizing the test generator to generate the test program; stripping said at least one TLB from the computer simulation; executing a first instruction from the test program in the computer simulation; in response to the test program detecting a TLB miss of a needed virtual page that is required to execute the first instruction, utilizing the TLB interrupt handler to walk the page table until the needed virtual page is located; writing the needed virtual page to the TLB; and completing execution of the first instruction by using the needed virtual page from the TLB.