Patent ID: 7659171
Filing Date: 2010-02-09
Classification: H01L

Abstract:
1. A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising: forming a gate conductor stack on a substrate; forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume; depositing a liner layer on the substrate, the spacers, and the gate conductor stack; depositing a dielectric layer on the liner layer; etching to form a contact hole in the dielectric layer; etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed, and a portion of the liner layer above the gate conductor stack is removed; and depositing contact metal in the contact hole.