Patent ID: 8990513
Filing Date: 2015-03-24
Classification: G06F

Abstract:
1. A coherent attached processor proxy (CAPP), comprising: logic that participates in coherent communication of memory access requests within a primary coherent system on behalf of an external attached processor (AP) including a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system; a CAPP directory of the cache memory, wherein the CAPP directory includes a plurality of entries each holding information regarding a respective associated cache line of data from the primary coherent system that is held in the cache memory of the external attached processor, the information including an address tag; recovery circuitry, that responsive to initiation of recovery operations, performs coherence recovery operations by transmitting, for each of multiple entries in the CAPP directory, one of a corresponding plurality of memory access requests in the primary coherent system indicating an error for an address specified by the address tag of that entry, wherein the recovery circuitry transmits the plurality of memory access requests in a generally sequential order with respect to the CAPP directory, and wherein the recovery circuitry, responsive to a snooped memory access request that targets a particular address hitting in the CAPP directory during the coherence recovery operations, performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.