Patent ID: 6033922
Filing Date: 2000-03-07
Classification: B24B,H01L

Abstract:
A test wafer that is included with a lot of product wafers during thermal processing of the product wafers to determine a product wafer temperature achieved at the product wafers during the thermal processing of the product wafers, the test wafer comprising:a lightly doped silicon wafer having a bare sheet resistance of 10 .OMEGA./square to 40 .OMEGA./square; anda layer of titanium deposited on the lightly doped silicon wafer after the lightly doped silicon wafer is precleaned, the layer of titanium having a predetermined thickness such that an initial sheet resistance measured on top of the layer of titanium is 6.3.+-.0.2 .OMEGA./square, and wherein a measurement of the initial sheet resistance at a plurality of locations on the test wafer results in a standard deviation that is less than 1% of a mean of the measurement of the initial sheet resistance at the plurality of locations.