Patent ID: 6133116
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method of forming an integrated circuit device having a trench isolation region therein, comprising:forming a trench isolation region in a semiconductor substrate, the trench isolation region having an embedded-conductive shield therein and surrounding a predetermined portion of the semiconductor substrate which comprises an active region;forming a transistor on the active region;forming an interlayer insulating layer on the semiconductor substrate; andforming a power supply line that extends on the interlayer insulating layer and is electrically connected to the embedded-conductive shield within the trench isolation regionwherein the step of forming the trench isolation region comprises:etching the semiconductor substrate to form a trench therein having a bottom and sidewalls;growing a thermal oxide layer on the bottom and sidewalls of the trench:filling the trench with a conductive material;etching back the conductive material to define a recess therein;forming a protection layer comprising a material that has an etching selectivity relative to an insulator material, in the recess; thenfilling the recess in the conductive material with the insulator material to thereby define an embedded-conductive shield.