Patent ID: 6822285
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A multi-element floating gate for an EEPROM comprising:a main polysilicon body disposed over a semiconducting substrate and electrically insulated therefrom in a first active region; source and drain implants within the semiconducting substrate on opposed sides of the main polysilicon body, the drain implant having a size exceeding the source implant; a polysilicon spacer disposed over the semiconducting substrate and electrically insulated therefrom and spaced from the main polysilicon body by a layer of thin oxide, the thin oxide extending over the main polysilicon body, all in the first active region; a polysilicon cap disposed over the polysilicon spacer in electrical contact therewith and disposed over the thin oxide on the main polysilicon body, the polysilicon cap having a metal filled hole through the cap and through the main polysilicon body whereby metal in the hole electrically joins the main polysilicon body with the polysilicon spacer; a second active region having an implanted region, the second active region insulated from the first active region, said drain implant electrically extending to the implanted region in the second active region wherein a charge storage reservoir is provided for programming.