Patent ID: 6052768
Filing Date: 2000-04-18
Classification: G06F

Abstract:
A modulo address generator comprising:an adder configured to receive a current address value and an address increment value and add the address increment value to the current address value in order to generate an incremented address value;an adder/subtracter circuit configured to receive the incremented address value, a data region size value corresponding to a data region and a sign bit of the address increment value, wherein the adder/subtracter circuit is further configured to add the data region size value to the incremented address value responsive to negative value of the sign bit and subtract the data region size value from the incremented address value responsive to a positive value of the sign bit in order to generate a revised address value; andan output selection circuit configured to receive the incremented address value, the data region size value and the sign bit, wherein the output selection circuit is further configured to select the incremented address value for a next address value responsive to the positive value of the sign bit and the revised address value being less than a minimum address value of the data region, select the revised address value for the next address value responsive to the positive value of the sign bit and the revised address value being one of greater than or equal to the minimum address value of the data region, select the revised address value for the next address responsive to the negative value of the sign bit and the incremented address value being less than the minimum address value of the data region, and select the incremented address value for the next address responsive to the negative value of the sign bit and the incremented address value being one of greater than or equal to the minimum address value of the data region.