Patent ID: 7271438
Filing Date: 2007-09-18
Classification: H01L

Abstract:
1. A floating-gate memory cell, comprising: a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of the tunnel dielectric layer; a source region formed in a semiconductor substrate adjacent a second side of the tunnel dielectric layer; a floating-gate layer formed overlying the tunnel dielectric layer; a control-gate layer formed overlying the floating-gate layer; and an intergate dielectric layer formed interposed between the floating-gate layer and the control gate layer; wherein the control-gate layer comprises a silicide layer in contact with an underlying polysilicon layer; wherein there is no interposing dielectric layer between the control-gate layer and an overlying bulk insulator layer; and wherein a width of the silicide layer is substantially equal to a width of the polysilicon layer.