Patent ID: 6584530
Filing Date: 2003-06-24
Classification: G06F

Abstract:
An information processing system, comprising:a plurality of first modules and a second module each connected to a first bus; a third module connected to a second bus; a bus conversion device, connected to said first bus and said second bus, having a bus arbiter for arbitrating bus occupation of the modules and a data storage unit, wherein said bus arbiter includes a signal input means for receiving a first bus occupation right request signal issued by one of said first modules for accessing said third module, a second bus occupation right request signal issued by one of said first modules for accessing said third module, a third bus occupation right request signal issued by one of said first modules for accessing said second module, and access destination information indicating to which of the buses of a module access is to be conducted in correspondence with each of the bus occupation right request signals, and wherein when the bus occupation right request signals are received in an order of said first bus occupation right request signal, said second bus occupation right request signal, and said third bus occupation right request signal, and when a signal indicating that a storage area is full for storing access data where said second bus occupation right request signal has been received, said information processing system refers to said access destination information, changes the order of said second bus occupation right request signal and said third bus occupation right request signal, and gives a bus occupation right to a bus master which issued said third bus occupation right request signal.