Patent ID: 7074691
Filing Date: 2006-07-11
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming an element isolation trench in a first element isolation region and in a second element isolation region which is larger than said first element isolation region, of a semiconductor substrate; (b) filling said isolation trench up to a predetermined position in its depth direction with a first insulating film deposited by a coating method; (c) depositing a second insulating film on a main surface of said semiconductor substrate by a chemical vapor deposition method so as to fill a remaining depth portion of said isolation trench; and (d) polishing said second insulating film on the main surface of said semiconductor substrate by a chemical mechanical polishing method; wherein dummy patterns are provided in said second element isolation region before said first insulating film is deposited, and wherein an etching rate of said second insulating film is lower than that of said first insulating film.