Patent ID: 7435677
Filing Date: 2008-10-14
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a first inter-layer insulation layer over a substrate where a plurality of first contact holes are formed; forming a conductive layer over the first inter-layer insulation layer to fill the first contact holes; forming a conductive layer for a storage node contact plug such that a storage node contact hole, which is formed by etching a portion of a second inter-layer insulation layer formed over the first inter-layer insulation layer, is filled; planarizing the conductive layer for the storage node contact plug to have a surface thickness difference between the second inter-layer insulation layer and the storage node contact plug; and forming an etch stop layer more thickly over the surfaces of the storage node contact plug than the surface of the second inter-layer insulation layer.