Patent ID: 8232951
Filing Date: 2012-07-31
Classification: G09G

Abstract:
1. A dynamic image control device using coincident blank insertion signals, comprising: a sequence control unit, said sequence control unit controlling timing sequence data; a data access unit, said data access unit connecting to said sequence control unit, said data access unit accessing required data; a buffer unit, said buffer unit connecting to said data access unit, said buffer unit buffering said required data; a register, said register connecting to said sequence control unit, said register buffering said timing sequence data; a data output unit, said data output unit connecting to said sequence control unit and said data access unit, said data output unit outputting an reduce swing differential signal; and a driving signal unit, said driving signal unit connecting to said data sequence control unit and said register, said driving signal unit outputting a output signal, a transference control signal, a polarity control signal, a start pulse signal, a clock signal and a plurality of output control signals, wherein control waveform of each of said transference control signal, said polarity control signal, said start pulse signal, said clock signal and each of said output control signals is divided into a display section and a blank insertion section; wherein said clock signal in said display section comprises cyclic signals and each cyclic signal comprises sequential signals of a first clock pulse signal and a second clock pulse signal; wherein said start pulse signal in said display section is a high level signal at said second clock pulse signal; wherein said output control signal in said display section comprises cyclic signals and each cyclic signal comprises sequential signals of a first output control low potential signal, an output control high potential signal and a second output control low potential signal; wherein said start pulse signal in said blank insertion section is a high level signal during said second clock pulse signal of a cyclic signal of said clock signal and said first clock pulse signal of next cyclic signal of said clock signal; and wherein said output control signal in said blank insertion section comprises cyclic signals and each cyclic signal comprises sequential signals of a first output control high potential signal, an output control low potential signal and a second output control high potential signal sequentially.