Patent ID: 9111948
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A fabrication method of a semiconductor package structure, comprising: providing a carrier board having a first adhesive layer formed on a surface thereof, and, a plurality of semiconductor chips, each of which has an active surface and an opposite inactive surface, a plurality of electrode pads formed on the active surface, and a plurality of metal humps disposed on the electrode pads, respectively; adhering the semiconductor chips to the first adhesive layer through the active surfaces thereof; forming an encapsulant on the first adhesive layer to encapsulate the semiconductor chips; providing a metal foil having a plurality of metal posts disposed on a surface thereof, and attaching the metal foil to the encapsulant through the surface thereof such that the metal posts penetrate the encapsulant and extend to the inactive surfaces of the semiconductor chips; removing the carrier board and the first adhesive layer; forming a dielectric layer on the encapsulant and the semiconductor chips, wherein the dielectric layer has a plurality of patterned intaglios for exposing the metal bumps, respectively; forming a wiring layer in the patterned intaglios of the dielectric layer such that the wiring layer is electrically connected to the metal bumps; forming an insulating protective layer on the dielectric layer and the wiring layer, wherein the insulating protective layer has a plurality of openings for exposing portions of the wiring layer; removing portions of the metal foil to form dicing lines such that the metal foil is separated corresponding to the semiconductor chips; and cutting the encapsulant, the dielectric layer and the insulating protective layer along the dicing lines of the metal foil such that a plurality of semiconductor package structures are formed.