Patent ID: 6991960
Filing Date: 2006-01-31
Classification: H01L,H05K,Y02P,Y10S

Abstract:
1. A method for aligning a semiconductor device package with a carrier substrate for electrical interconnection therebetween, the method comprising: surface thereof to a second, opposing major surface thereof; providing a major surface of the carrier substrate with at least two alignment features including forming at least two holes in the carrier substrate, each of which are spaced and positioned in respective correspondence to one of the at least two channels; engaging the at least two channels formed in the semiconductor device package with at least two pins carried by a head of a pick and place device and grasping the semiconductor device package with the pick and place device; positioning the pick and place device and the semiconductor device package over the carrier substrate with the first major surface of the semiconductor device package facing the major surface of the carrier substrate; aligning the at least two pins with the at least two alignment features of the carrier substrate; placing the at least two pins through the at least two channels and into the at least two holes; and engaging a portion of a second, opposing surface of the carrier substrate with a mechanical self-locking mechanism carried by at least one of the at least two pins.