Patent ID: 7157773
Filing Date: 2007-01-02
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device including a memory cell, comprising: a semiconductor substrate; a semiconductor layer, located above said semiconductor substrate, including a source region, a channel region and a drain region of said memory cell; a lower insulator film located between said semiconductor substrate and said semiconductor layer, said lower insulator film includes a charge trap insulator film capable of trapping charges; an insulator film on said channel region, wherein said insulator film includes a multilayer structure of a first insulator film, a first charge trap insulator film capable of trapping charges and second insulator film, wherein said lower insulator film has a multilayer structure of a third insulator film, a second charge trap insulator film for trapping charges and a fourth insulator film, first charge trap regions trapping charges in a region including a portion corresponding to the boundary between said source region and said channel region and a region including a portion corresponding to the boundary between said drain region and said channel region in said first charge trap insulator film while having second charge trap regions trapping charges in a region including a portion corresponding to the boundary between said source region and said channel region and a region including a portion corresponding to the boundary between said drain region and said channel region in said second charge trap insulator film.