Patent ID: 9093909
Filing Date: 2015-07-28
Classification: H02M

Abstract:
1. A switching mode power supply, comprising: an input port configured to receive an input voltage; an output port configured to provide an output voltage to a load; an energy storage component and a power switches coupled between the input port and the output port; an error amplifier having a first input terminal configured to receive a feedback signal indicative of the output voltage, a second input terminal configured to receive a reference signal, and an output terminal configured to generate an amplified error signal based on the feedback signal and the reference signal; an error comparator having a first input terminal configured to receive the amplified error signal, a second input terminal configured to receive a first sawtooth signal, and an output terminal configured to generate a frequency control signal based on the amplified error signal and the first sawtooth signal; a peak current generator having an input terminal coupled to the output terminal of the error comparator to receive the frequency control signal, and an output terminal configured to generate a peak current signal based on the frequency control signal, wherein the value of the peak current signal is varying with a switching frequency of the switching mode power supply; a peak current comparator having a first input terminal coupled to the output terminal of the peak current generator to receive the peak current signal, a second input terminal configured to receive a current sense signal indicative of a current flowing through the energy storage component, and an output terminal configured to generate a current limit signal based on the peak current signal and the current sense signal; and a logic circuit having a first input terminal coupled to the output terminal of the error comparator to receive the frequency control signal, a second input terminal coupled to the output terminal of the peak current comparator to receive the current limit signal, an output terminal configured to generate a switching signal to control the power switches based on the frequency control signal and the current limit signal, and an oscillator configured to generate a clock signal with a fixed frequency; a selector having a first input terminal coupled to the output terminal of the error comparator to receive the frequency control signal, a second input terminal coupled to the oscillator to receive the clock signal, and an output terminal configured to select the lower frequency value of between the frequency control signal and the clock signal; a RS flip-flop having a set terminal coupled to the output terminal of the selector, a reset terminal coupled to the output terminal of the peak current comparator to receive the current limit signal, and an output terminal configured to generate the switching signal based on the output signal of the selector and the current limit signal.