Patent ID: 7239566
Filing Date: 2007-07-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a pair of first global input/output (I/O) lines connecting with a plurality of pairs of first local I/O lines; a pair of second global I/O lines connecting with a plurality of pairs of second local I/O lines; a first precharge circuit for precharging the pair of first global I/O lines in response to a first precharge enable signal; a second precharge circuit for precharging the pair of second global I/O lines in response to a second precharge enable signal; a switch for connecting the pair of first global I/O lines and the pair of second global I/O lines; a first precharge driver for enabling the first precharge enable signal when a first memory region is selected during a precharge operation; and a second precharge driver for enabling the second precharge enable signal when the first memory region is selected during a precharge operation or when a second memory region is selected during a precharge operation, wherein the first and second precharge drivers enable the first and second precharge enable signals based on at least one of a precharge control signal, a memory region selection signal, and enable information from a first or a second row decoder.