Patent ID: 6291894
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A processed semiconductor wafer, comprising:a semiconductor wafer having first and second integrated circuit devices formed on a first surface of the wafer;a first plurality of contact pads associated with the first integrated circuit device and a second plurality of contact pads associated with the second integrated circuit device;a plurality of wire leads coupled between the first and second pluralities of contact pads;a covering of encapsulating material substantially covering at least the first and second integrated circuit devices, covering the first and second pluralities of contact pads, and covering the wire leads coupled between the first and second integrated circuit devices; anda scribe line between the first plurality of contact pads and the second plurality of contact pads, the scribe line extending orthogonally to the wire leads and defining a boundary along which the first integrated circuit device and the second integrated circuit device are to be separated, whereby, upon separation of the first and second integrated circuit devices, each of the first and second integrated circuit devices includes a plurality of exposed ends of wire leads for electrical contact along only an edge surface, the exposed ends being substantially flush with the edge surface.