Patent ID: 6360310
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A data processing system, comprising:an instruction cache unit; and a processor coupled to the instruction cache unit, the processor including: a program counter, the program counter storing a current address field of an instruction field being accessed in the instruction cache unit during the current clock cycle; an incrementing unit for incrementing the current address field stored in the program counter during the current clock cycle, the incrementing unit providing a speculative instruction cache address, the speculative address field used to access the speculative instruction cache address during the next clock cycle; a decoder unit responsive to an instruction field accessed during a next previous clock cycle, the decoder unit assisting in providing a actual instruction cache address; and a comparison unit responsive the current program counter address and to the actual next program counter address; when the current program counter address is equal to the actual next program counter address, applying the speculative next program address to the program counter to determine an address for the next cycle; when the current program counter address not equal to the actual next program counter address, canceling the instruction cache access occurring during the present clock cycle and applying the actual next program counter address to the program counter to determine an address for the next cycle.