Patent ID: 8780642
Filing Date: 2014-07-15
Classification: G11C,H01L

Abstract:
1. A method of erasing a plurality of flash memory cells in a flash memory structure formed in a semiconductor substrate of a first conductivity type wherein said structure has a first region of a second conductivity type in said substrate; a second region of a second conductivity type in said substrate, spaced apart from said first region, thereby defining a continuous channel region therebetween; a plurality of floating gates, spaced apart from one another, each positioned over a separate portion of the channel region, wherein each floating gate defines a flash memory cell; a plurality of control gates, each associated with and adjacent to one of the floating gates, each control gate having two portions directly and electrically connected to one another: a first portion over a portion of the channel region and not over any of the floating gates, and a second portion over the floating gate associated therewith and capacitively coupled thereto; wherein said method comprising: applying a positive voltage to each of said control gates to provide capacitive coupling to the floating gates associated therewith; thereby causing tunneling of electrons from each floating gate to the control gate associated therewith.