Patent ID: 6363016
Filing Date: 2002-03-26
Classification: G11C

Abstract:
A non-volatile memory system comprising:an array of non-volatile memory cells fabricated in a substrate, the array being arranged in a plurality of rows and columns, each of the non-volatile memory cells having a source, a drain, a floating gate and a control gate; means for biasing the gate of each non-volatile memory transistor in a selected row of the array with a VCC supply voltage during a read operation; means for biasing the substrate with a control voltage less than 1.0 Volt and greater than 0 Volts during a read operation; means for biasing the source of each non-volatile memory transistor in a selected column of the array with a ground supply voltage during a read operation; means for biasing the drain of each non-volatile memory transistor in the selected column of the array with a read voltage between the VCC and ground supply voltages during a read operation; and means for biasing the sources and drains of the non-volatile memory transistors in non-selected columns of the array with the control voltage.