Patent ID: 6516437
Filing Date: 2003-02-04
Classification: H03M

Abstract:
A control for a turbo decoder for decoding turbo codes comprising two recursive systematic code words concatenated in parallel, each code word comprising systematic data and parity data, the turbo decoder comprising a MAP decoding algorithm, the turbo decoder comprising a gamma block for calculating unconditioned symbol transition probabilities, each unconditioned symbol transition probability representing a gamma value, the gamma block receiving as inputs channel transition probabilities and a priori bit probabilities, alpha and beta blocks for receiving the gamma values from the gamma block and for recursively calculating forward and backward state probabilities, respectively, the forward state probabilities representing alpha values and the backward state probabilities representing beta values, a sigma block for receiving the alpha and beta values, respectively, from the alpha and beta blocks, respectively, and for calculating a posteriori transition probabilities therefrom, the a posteriori transition probabilities representing sigma values, the sigma block performing a summation function of the sigma values to provide a posteriori probability estimates of the systematic symbols of the component code words as outputs of the turbo decoder, the turbo decoder control comprising:an address generator for addressing the systematic data, the parity data, and systematic likelihood ratios according to a pre-determined memory mapping such that the systematic data samples are accessed in the order required by the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time; a de-interleaver definition block for receiving the address from the address generator and providing a de-interleaver definition address; a multiplexer, which is controlled by a top/bottom code select block, for selecting the address from the address generator or the address from the de-interleaver definition block and for providing the selected address directly and through a delay to a systematic likelihood ratio circuit and directly to a systematic data block, the systematic likelihood ratio circuit providing the systematic likelihood ratios to a component decoder, the systematic data block providing systematic data to the component decoder in parallel with the systematic likelihood ratio circuit, the output of the component decoder comprising the a posteriori probability estimates which are fed back through the systematic likelihood ratio circuit; bottom and top code parity data blocks for receiving the address from the address generator and for providing the parity data via a multiplexer controlled by the top/bottom code select block to the component decoder.