Patent ID: 9041057
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A field effect transistor device comprising: a substrate; a silicon germanium (SiGe) layer disposed on the substrate; a gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer; a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity; ion doped regions disposed in an upper surface of the SiGe layer; a silicon layer disposed on the ion doped regions of the SiGe layer; spacers disposed on the ion doped regions of the SiGe layer, the spacers having an outside surface abutting the silicon layer, the spacers further defining the cavity, and the gate dielectric layer lining an entire inside surface of the spacers; a source region; and a drain region, wherein the source and drain regions comprise both the silicon layer and the ion doped regions such that a channel length, L, is defined by a distance L=(2*L