Patent ID: 8477885
Filing Date: 2013-07-02
Classification: H04B,H04L

Abstract:
1. A method of generating a recursive maximum likelihood (ML) frequency estimator in a digital integrated circuit comprising one or more memory devices and operatively connected to a network, comprising the steps of: determining, in a digital integrated circuit comprising one or more memory devices and operatively connected to a network, a frequency f of a digital signal at a time period N; forming, in the digital integrated circuit, an alternate quantity, {tilde over (Λ)}(f, N) computing, in the digital integrated circuit, the alternate quantity recursively by recursively determining an updated value Γ(f,N) at a predetermined update rate, and using the updated value to update {tilde over (Λ)}(f, N) estimating the maximum likelihood frequency as the value of f that produces the maximum value of {tilde over (Λ)}(f, N)