Patent ID: 6596624
Filing Date: 2003-07-22
Classification: H01L

Abstract:
A process for making a multilevel integrated circuit chip structure, comprising:a. depositing atop a semiconductor substrate a minimum total of between about 5 and about 11 layers, comprising support studs provided at preselected sites within the chip and through all levels in the chip periphery, and via levels alternating with copper wiring levels which are protected with an anticorrosion overcoat; b. providing a temporary dielectric material in more than two of the copper wiring levels, and providing a permanent solid dielectric material in any levels in which temporary dielectric material is not provided; c. dicing the resulting chip structure into individual chips and joining at least one diced chip to a chip carrier; d. after joining, selectively removing the temporary dielectric material by means selected to be nondestructive to the permanent solid dielectric material and to the structure as a whole; and e. replacing the temporary dielectric material with a permanent gas dielectric material selected from the group consisting of air, nitrogen, carbon dioxide, mixtures thereof and partial vacuum.