Patent ID: 8853764
Filing Date: 2014-10-07
Classification: H01L

Abstract:
1. A method comprising: forming first, second, and third shallow trench isolation (STI) regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with a second mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a third mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the third mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.