Patent ID: 7474123
Filing Date: 2009-01-06
Classification: H03K

Abstract:
1. A method for configuring power consumption of sequential logic, the method comprising: providing a sequential logic device including a first latch, a second latch, and first and second enable inputs, wherein the first enable input enables and disables the first latch and the second latch, and the second enable input enables and disables the second latch and does not affect the first latch, wherein the first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle; and providing circuit capability to configure the sequential logic device at operating time to operate in a lower frequency mode that consumes less power during a lower frequency of operation of the sequential logic device, and to operate in a higher frequency mode that consumes more power during a higher frequency of operation of the sequential logic device, wherein the circuit capability transmits a combined enable signal to the second enable input that completely describes the enabling conditions of the sequential logic device, the combined enable signal including a first enable signal ANDed with a second enable signal, the first enable signal having the required signal arrival time for the first enable input and the second enable signal not having the required signal arrival time for the first enable input.