Patent ID: 6279103
Filing Date: 2001-08-21
Classification: G06F

Abstract:
A single chip integrated circuit device comprising:an on-chip CPU comprising fetch circuitry and execution circuitry for fetching and executing instructions from a memory, and an instruction pointer register for holding sequentially instruction pointers comprising addresses in memory of instructions to be executed by the CPU, the execution circuitry of the CPU being operable to generate a control signal indicating a discontinuity in that one of said addresses is not the next sequential address in memory after the previous one of said addresses; andan instruction trace controller connected to said CPU by a bus, said instruction trace controller being operable to monitor said addresses of said instruction pointers which are received from said CPU on said bus, said instruction trace controller being connected to trace storage locations for causing selected ones of said addresses to be stored at said trace locations, wherein said instruction trace controller also receives said control signal which is sent with said instruction pointer from said CPU to said instruction trace controller on said bus and selected ones of said address are stored at said trace locations dependent on detection of said control signal wherein said control signal is generated by said execution circuitry to control when said fetch circuitry is to start fetching instructions from a new memory location.