Patent ID: 8460980
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A method, comprising: forming cavities in a crystalline semiconductor region laterally offset to a gate electrode structure of a transistor by performing a first etch process on the basis of a plasma ambient, said cavities having a lateral offset along a length direction with respect to an electrode material of said gate electrode structure; increasing said cavities along said length direction so as to extend below said electrode material by performing a second wet chemical etch process having a crystallographically anisotropic etch behavior to define an inclined surface in the cavity starting proximate an edge of said electrode structure and terminating at an apex disposed beneath said gate electrode structure, wherein prior to the forming and increasing of said cavities a mask is formed above said crystalline semiconductor material along only a portion of a width of one side of said gate electrode, and wherein a portion of the crystalline semiconductor material remains below the mask after the forming and increasing of said cavities to define a stiffening area in said crystalline semiconductor region extending outward from said gate electrode and perpendicularly from a width direction of said gate electrode and mechanically coupled to said gate electrode; forming a strain-inducing semiconductor alloy in said cavities; and forming drain and source regions in a portion of said strain-inducing semiconductor alloy.