Patent ID: 6356474
Filing Date: 2002-03-12
Classification: G11C

Abstract:
A memory array comprising:a plurality of sub-arrays, each sub array including a plurality of memory cells arranged in rows and columns; a digit line for each column of each sub-array; a plurality of sense amplifiers, the digit lines and sense amplifiers being arranged in an open-array architecture so that each of a first plurality of sense amplifiers is coupled to a digit line in each of two adjacent sub-arrays except for a first set of digit lines in at least one end sub-array; a second plurality of sense amplifiers each having first and second complimentary inputs, the digit lines in the first set being coupled to the first input of a respective sense amplifier in the second plurality of sense amplifiers; and a load circuit coupled to the second input of each sense amplifier in the second plurality, the load circuit having an adjustable impedance.