Patent ID: 8084350
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A method comprising: sequentially forming a first interlayer dielectric film, an etch stop film, a second interlayer dielectric film, and first and second hard mask layers over a lower metal wire; and then forming a second hard mask pattern by patterning the second hard mask layer exposing a portion of the first hard mask layer in a trench region; and then forming a first hard mask pattern by patterning the first hard mask layer exposing the second interlayer dielectric layer in a via hole regions; and then etching the second interlayer dielectric film and the etch stop film in the via hole regions using the first hard mask pattern as a mask thereby exposing the first interlayer dielectric film; and then forming a trench by etching the first hard mask pattern and the second interlayer dielectric film in the trench region using the second hard mask pattern as a mask thereby exposing the etch stop layer; and then forming via holes by etching the first interlayer dielectric film in the via hole regions using the etch stop layer as a mask thereby exposing the lower metal wire; and then forming an upper metal wire in the trench and the via holes, wherein forming the second interlayer dielectric film comprises: forming a first silicon-rich oxide (SRO) layer over the etch stop film; and then forming an interlayer dielectric layer having a low-k value over the first SRO layer; and then forming a second SRO layer over the interlayer dielectric layer.