Patent ID: 6256424
Filing Date: 2001-07-03
Classification: G06T,H04N

Abstract:
An image filter circuit for subjecting image signals to a dodging treatment, comprising:a filter for filtering and generating unsharp image signals, thereby subjecting inputted image signals to a dodging treatment which adjusts areas of exposure over an entire image;at least one memory for delaying input image signals which are not subjected to the dodging treatment at said filter for a time period corresponding to a delay time during which image signals are subjected to the dodging treatment at said filter; anda main controller for generating signals which control writing to and reading from said at least one memory to control the operation timing of said at least one memory in accordance with the delay time of said image signals at said filter, wherein said main controller includes:a first counter which counts a number of pixels in horizontal and vertical directions of a reproduced image;a first flip-flop which generates said signals controlling writing during a time period from when said first counter starts counting until the end of counting;a second counter which starts counting a number of horizontal and vertical delays of said image signals at said filter, beginning when said first counter starts counting;a third counter which starts counting the number of horizontal and vertical delays of said image signals at said filter, after said first counter has finished counting; anda second flip-flop which generates said signals controlling reading after said second counter has finished counting, and until a time period when said third counter finishes counting.