Patent ID: 6844247
Filing Date: 2005-01-18
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a first gate electrode structure having first stacked layers formed on a first insulating film deposited on a surface of said semiconductor substrate in a memory cell area where memory cells are formed; a second gate electrode structure having second stacked layers formed on a second insulating film deposited on a surface of said semiconductor substrate in a logic circuit area where logic circuits are formed; wherein a first lowermost layer in said first stacked layers and a second lowermost layer in said second stacked layers comprise different materials; wherein said first lowermost layer contacting with said first insulating layer is a polycrystalline silicon layer, and said second lowermost layer contacting with said second insulating layer is a first polycrystalline silicon germanium layer; wherein said first gate electrode structure comprises a second polycrystalline silicon germanium layer provided on said polycrystalline silicon layer through a third insulating layer that is electrically insulating.