Patent ID: 7078285
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A method of forming a CMOS device, comprising: forming at least one patterned gate region atop a first semiconductor layer that includes silicon; forming dielectric spacers about exposed portions of the patterned gate region; forming source-drain regions in the first semiconductor layer; forming recesses in the first semiconductor layer that extends under the dielectric spacers, said first semiconductor layer having exposed surfaces that in part define sidewalls of the recesses; forming a nickel barrier layer on each of said exposed surfaces of the first semiconductor layer; etching the nickel barrier layers so that the nickel barriers remain only on portions of said exposed surfaces located under the dielectric spacers and not on remaining portions of said exposed surface; forming a silicon-containing layer on each of said remaining exposed surfaces of the first semiconductor layer; and forming silicide layers on said silicon-containing layers, wherein said silicide layer includes nickel.