Patent ID: 6500739
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A method of forming an N channel, metal oxide semiconductor (NMOS), device, on a semiconductor substrate, comprising the steps of:providing a gate structure, overlying a gate insulator layer, on a semiconductor substrate comprised with a first conductivity type dopant; performing a first ion implantation procedure to form a pocket implant region, of a first conductivity type, in a region of said semiconductor substrate not covered by said gate structure; performing a second ion implantation procedure to place antimony ions in said pocket implant region; performing a third ion implantation procedure to form a lightly doped source/drain (LDD), region, of a second conductivity type, in an area of said semiconductor substrate not covered by said gate structure, with said LDD region located in a top portion of said pocket implant region; performing an anneal procedure to activate antimony ions in said pocket implant region, to activate ions used to form said pocket implant region, and to activate the ions in said LDD region; forming insulator spacers on sides of said gate structure; and performing a fourth ion implantation procedure to from a heavily doped source/drain region, of a second conductivity type, in a region of said semiconductor substrate not covered by said gate structure, and not covered by insulator spacers on sides of said gate structure.