Patent ID: 7262081
Filing Date: 2007-08-28
Classification: H01L

Abstract:
1. A process of fan out type wafer level package, comprising the steps of: adhering plurality of first dice to a base; forming a first material layer on said base to fill in a space among plurality of said first dice on said base; forming a second material layer on said first material layer and said plurality of first dice; etching a partial region of said second material layer on first pads of said plurality of first dice to form first openings; forming a first contact conductive layer on said first openings to electrically couple with said first pads, respectively; forming first conductive lines over said first contact conductive layer within said first opening and said second material layer; forming a first isolation layer on said first conductive lines and said second material layer; adhering plurality of second dice to said first isolation layer; forming a third material layer on said first isolation layer to fill in a space among plurality of said second dice on said first isolation layer; forming a fourth material layer on said third material layer and plurality of said second dice; etching a partial region of said fourth material layer on second pads of plurality of said second dice to form second openings; forming a second contact conductive layer on said second openings to electrically coupling with said second pads, respectively; removing a partial region of said fourth material layer, said third material layer, and said first isolation layer on said first conductive lines to forming third openings; filling up said third openings with conductive material; forming second conductive lines over said second contact conductive layer within said third opening and said fourth material layer, wherein said first die is coupled to said second die through said conductive material to communicate with each other; forming a second isolation layer on said second conductive lines and said fourth material layer; removing a partial region of said second isolation layer on said second conductive lines to forming fourth openings; and welding solder balls on said fourth openings.