Patent ID: 7627843
Filing Date: 2009-12-01
Classification: G01R,G06F

Abstract:
1. A method for functional verification of a design comprising the steps of: providing a processor and a memory accessible to the processor in which computer program instructions are stored, the instructions comprising distinct software modules including a test generator engine, the processor operative under control of the instructions for: defining respective first and second templates directed to first and second sets of functions of the design; operating the test generator engine to prepare first and second test cases from the first and second templates, respectively; using the first test case, operating an execution engine a first time to verify the first set of functions in the design; using the second test case, operating the execution engine a second time to verify the second set of functions in the design; after performing the steps of operating the execution engine a first time and a second time, interleaving instances of the first and second templates in a nonpredetermined order, using a template arbitrator; wherein said non-predetermined order a number of occurrences of the first templates between occurrences of the second templates does not exceed a predetermined value; processing the interleaved first and second templates in the test generator engine to prepare a combined test case, wherein invocations of the first set of functions are correspondingly interleaved with invocations of the second set of functions; and using the combined test case, operating the execution engine a third time to verify the first and second sets of functions in combination.