Patent ID: 6351790
Filing Date: 2002-02-26
Classification: G06F

Abstract:
A computer system comprising:a plurality of processors, each of the plurality of processors comprising an execution unit for executing a sequence of instructions, and at least one of the processors having associated therewith a cache memory having a plurality of cache locations for holding items for use by the at least one processor; storage circuitry having addressable storage locations in a memory address space of the at least one processor in which items are stored for use by the plurality of processors; a behaviour store for holding in association with an address of an item a cache behaviour that identifies cacheable behaviours of the item, wherein the cacheable behaviours include a software coherent behaviour wherein cache coherency is controlled by software and an automatically coherent behaviour wherein cache coherency is maintained by a hardware cache coherency unit, and wherein the instructions for execution by the execution unit include cache coherency instructions which each specify an operation to be executed on the contents of a specified cache location and a specified address in the storage circuitry; each processor being operable responsive to the cache coherency instructions to execute an operation on the contents of the specified cache location and to effect a cache coherency operation to render the contents of the specified cache location coherent with the storage circuitry in a manner dependent on the cacheable behaviour of the specified address and whether or not the processor executing the operation contains a hardware cache coherency unit for automatically implementing coherency.