Patent ID: 7507647
Filing Date: 2009-03-24
Classification: H01L

Abstract:
1. A method of manufacturing a high voltage semiconductor device, comprising: forming a buffer oxide layer on the silicon substrate; forming a first mask pattern to expose a first region of the buffer oxide layer; forming the P-type region in the silicon substrate by implanting P-type impurities using the first mask pattern as an ion implantation mask; removing the first mask pattern; forming a second mask pattern to expose a second region of the buffer oxide layer; and forming the N-type region in the silicon substrate by implanting N-type impurities using the second mask pattern as an ion implantation mask; forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate; forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask; forming a trench oxide layer pattern in the trench, comprising: forming a trench oxide layer so as to fill in the trench; performing chemical mechanical polishing to the trench oxide layer so as to expose a surface of the silicon nitride layer pattern; and removing the silicon nitride layer pattern and pad oxide layer pattern by etching them; and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, respectively, while forming a gate oxide layer on the silicon substrate including the trench oxide layer pattern.