Patent ID: 7467317
Filing Date: 2008-12-16
Classification: G06F,G11C

Abstract:
1. A memory system having a plurality of memory circuits and a control circuit for controlling said plurality of memory circuits according to main clocks, wherein said plurality of memory circuits and said control circuit are connected via first wiring for transmitting/receiving data signals, and second wiring having a length different from that of said first wiring, characterized in that said control circuit attains a clock signal obtained by n-dividing (n is a positive integer equal to or greater than 2) said main clocks in frequency, outputs a command/address signal to said plurality of memory circuits via said second wiring while matching said command/address signal with said n-divided clock signal, and outputs via said first wiring a data phase signal (DPS) having a predetermined frequency relationship with said n-divided clock signal and representing a phase of said data signal, and said plurality of memory circuits each absorb a timing skew caused by a difference in wiring length between said first and second wirings, using said data phase signal.