Patent ID: 6201758
Filing Date: 2001-03-13
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns;a cell select circuit to select said memory cell in response to an externally applied address signal;a plurality of read word lines provided corresponding respectively to said memory cell rows and selectively activated in a reading operation under the control of said cell select circuit;a plurality of write word lines provided corresponding respectively to said memory cell rows and selectively activated in a writing operation under the control of said cell select circuit;a plurality of read bit line pairs provided corresponding respectively to said memory cell columns to transmit storage data from a selected memory cell in said reading operation;a plurality of write bit line pairs provided corresponding respectively to said memory cell columns to transmit storage data to a selected memory cell in said writing operation; anda bit line pair potential control circuit capable of precharging each of said read bit line pairs and supplying a prescribed current to each of said read bit line pairs at least in said reading operation,each said memory cell including:a latch circuit having first and second input/output nodes and holding one of first and second potentials;first and second read access transistors provided between said first and second input/output nodes and one and the other read bit lines of a corresponding one of said read bit line pairs, respectively to attain a conductive state in response to an activation of a corresponding read word line of said read word lines;a first write access transistor and a first storage level driving transistor provided in series between said first input/output node and said first potential, anda second write access transistor and a second storage level driving transistor provided in series between said second input/output node and said first potential.