Patent ID: 8705271
Filing Date: 2014-04-22
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising nonvolatile memory cells arranged over a semiconductor substrate, wherein each of the nonvolatile memory cells comprises: a first semiconductor region of a first conductivity type formed in the semiconductor substrate and extending along a first direction in plan view; a first gate electrode of a selection transistor formed over the first semiconductor region; a floating gate electrode formed over the first semiconductor region; a third semiconductor region of a second conductivity type opposite to the first conductivity type formed in the first semiconductor region and arranged at one side of the first gate electrode; a fourth semiconductor region of the second conductivity type formed in the first semiconductor region and arranged between another side of the first gate electrode and one side of the floating gate electrode; and a fifth semiconductor region of the second conductivity type formed in the first semiconductor region and arranged at another side of the floating gate electrode, wherein a second semiconductor region of the first conductivity type is formed in the semiconductor substrate and electrically isolated from the first semiconductor region, wherein the floating gate extends along a second direction perpendicular to the first direction in plan view and is formed over the second semiconductor region so as to overlap at least a portion of the second semiconductor region in plan view, and wherein a STI structure, which includes an insulating film embedded in a groove formed in the semiconductor substrate, is arranged between the first and second semiconductor regions.