Patent ID: 7721174
Filing Date: 2010-05-18
Classification: G11C

Abstract:
1. A circuit including a memory, comprising: means for switching the circuit between a normal mode of operation wherein logic associated with the functionality of the circuit interacts with the memory and a test mode of operation wherein test logic interacts with the memory; means for providing, from the test logic, an expected value of data; means for reading, during a read cycle, an actual value of data stored in the memory; means for comparing the expected value of data to the actual value of data stored in the memory to provide a result of the comparison; and means for delaying the result of the comparison from being output from the means for comparing: the means for providing the expected value of data being coupled in parallel, with the means for delaying, to the means for comparing; the circuit allowing consecutive reads and compares of the memory on every clock cycle in order to test the memory.