Patent ID: 7268382
Filing Date: 2007-09-11
Classification: H01L,Y10S

Abstract:
1. A DRAM cell, comprising: a capacitor which includes a first capacitor electrode, a second capacitor electrode, and at least one dielectric material between the first and second capacitor electrodes; one of the first and second capacitor electrodes including a stack comprising at least three semiconductor layers, two of the three semiconductor layers being adjacent one another; a bottom of the stack being conductively-doped semiconductor material and a top of the stack comprising a rugged semiconductor-containing surface, there being an interface layer in the stack, the interface layer being between the adjacent semiconductor layers, wherein the conductively-doped semiconductor material of the bottom of the stack does not directly contact the rugged semiconductor-containing surface of the top of the stack; and a transistor having a source/drain region electrically coupled with one of the first and second capacitor electrodes.