Patent ID: 8791895
Filing Date: 2014-07-29
Classification: G02F,G09G

Abstract:
1. A memory liquid crystal display device that carries out a refresh operation in a period in which data is held after a data signal potential is written in, the device comprising: data signal lines; scanning signal lines; storage capacitor lines; data transfer lines; refresh lines; pixel electrodes; a counter electrode; first transistors, each of whose control terminal is connected to a respective one of the scanning signal lines; second transistors, each of whose control terminal is connected to a respective one of the data transfer lines; third transistors, each of whose control terminal is connected to a respective one of the pixel electrodes via a respective one of the second transistors; fourth transistors, each of whose control terminal is connected to a respective one of the refresh lines; first storage capacitors, each of which is connected to a respective one of the pixel electrodes; and second storage capacitors, each of which is connected to a respective one of the pixel electrodes via a respective one of the second transistors, each of the pixel electrodes being connected to a respective one of the data signal lines via a respective one of the first transistors and being connected to a respective one of the data transfer lines via a respective one of the third transistors and a respective one of the fourth transistors, and during the period in which the data is held, a storage capacitor line signal supplied to the storage capacitor lines once being decreased in potential while the scanning signal lines are simultaneously active, and having the potential of the storage capacitor line signal be back to its original potential during a period after the scanning signal lines are made simultaneously inactive but before the refresh lines are made active.