Patent ID: 6642104
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method of forming the floating gate of a flash memory unit, comprising the steps of:forming a tunnel oxide layer and a first floating gate layer over a substrate; patterning the first floating gate layer, the tunnel oxide layer and the substrate to form an opening; forming a first dielectric layer covering an interior surface of the opening and the first floating gate layer but without completely filling the opening; forming a second dielectric layer over the first floating gate layer and the first dielectric layer so that the opening is completely filled; planarizing the second dielectric layer to expose the first dielectric layer that was formed over the first floating gate layer; removing a portion of the first dielectric layer to expose the first floating gate layer and to make the second dielectric layer raise above a top surface of a remaining first dielectric layer; forming a second floating gate layer that covers the first dielectric layer, the second dielectric layer and the first floating gate layer; and planarizing the second floating gate layer to expose the second dielectric layer, so that a remaining second floating gate layer covers the first floating gate layer as well as extending over the remained first dielectric layer.