Patent ID: 7653780
Filing Date: 2010-01-26
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: a cell array including a plurality of dynamic memory cells; a cache memory; a read bus interconnecting said cell array and said cache memory to an output port, said read bus permitting data to be selectively provided to said output port from either of said cell array and said cache memory; a control circuit performing control so that, if at a time of a read operation, data to be read from said cell array is present in said cache memory, the data is read from said cache memory and refreshing of said cell array is performed; a plurality of subarrays each having a plurality of dynamic memory cells provided in a region of said cell array; at least one cache memory provided for said plurality of subarrays as said cache memory; and a circuit receiving a read request to a subarray for determining whether data to be read from the subarray is present in said cache memory or not, based on a read address, and performing control so that when the data to be read from the subarray is present in said cache memory, the reading of the data from said cache memory and refreshing of the subarray are performed concurrently, wherein at least one of said subarrays has two ports for a read system and a write system, wherein each of said dynamic memory cells composing said subarray comprises: wherein said subarray comprises: