Patent ID: 7576595
Filing Date: 2009-08-18
Classification: H03F

Abstract:
1. A buffer circuit comprising: a first transistor that regulates a current flowing from a first node to a second node in accordance with an output signal of an amplification circuit of a previous stage applied as an input signal to a control terminal of the first transistor; a second transistor that regulates a current flowing from the second node to a reference potential in accordance with a bias voltage applied to a control terminal of the second transistor; a current detection circuit which detects the current input to the first transistor via the first node, wherein the current detection circuit includes a first inductor inserted in a path used to input current to the first transistor via the first node; and a bias control circuit that regulates the bias voltage, responsive to the current detected by the current detection circuit such that the current of the second transistor is decreased in accordance with an increase in the current detected by the current detection circuit, and the current of the second transistor is increased in accordance with a decrease in the current detected by the current detection circuit, wherein the bias control circuit includes a second inductor joined magnetically with the first inductor so as to generate a voltage in accordance with the current flowing in the first inductor and so as to superimpose it on the bias voltage, and wherein an output signal corresponding to the input signal is output from the second node.