Patent ID: 7965836
Filing Date: 2011-06-21
Classification: H04L

Abstract:
1. A data cipher processor that uses a masking method in which original data and random data are processed according to a predetermined rule for encryption or decryption, the data cipher processor comprising: a 2-bit multiplication operation block, wherein, when the processor uses a masking method, the 2-bit multiplication operation block comprises: a first 2-bit multiplication operation block that multiplies two masked original data a′ and b′; a second 2-bit multiplication operation block that multiplies the masked original data a′ by random data s; a third 2-bit multiplication operation block that multiplies random data r by the masked original data b′; a fourth multiplication operation block that multiplies the random data r by the random data s; and wherein when the processor does not use the masking method, the 2-bit multiplication operation block comprises: a first AND gate that logically ANDs two original data a and c and outputs a result thereof as data; a second AND gate that logically ANDs two original data b and c and outputs a result thereof as data; a third AND gate that logically ANDs two original data a and d and outputs a result thereof as data; a fourth AND gate that logically ANDs two original data b and d and outputs a result thereof as data; a first XOR gate that XORs the data output from the first AND gate and the second AND gate and outputs the result thereof as data; a second XOR gate that XORs the data output from the first AND gate and the data output from the fourth AND gate and outputs a result (ac+bd) thereof as data; and a third XOR gate that XORs the data output from the first XOR gate and the data output from the third AND gate (