Patent ID: 9190404
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region; a shared contact plug electrically connected to the gate electrode and the impurity region; and an etch-stop layer between side surfaces of the gate electrode and the shared contact plug, wherein the shared contact plug comprises a first conductive pattern electrically connected to the impurity region and a second conductive pattern electrically connected to the gate electrode, and wherein a top surface of the first conductive pattern is higher than a top surface of the gate electrode, wherein the second conductive pattern is on a portion of a sidewall of the first conductive pattern and on the top surface of the first conductive pattern, wherein the top surface of the first conductive pattern is parallel to and remote from a surface of the substrate.