Patent ID: 7465973
Filing Date: 2008-12-16
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a plurality of repeatable circuit cells connectable to one or more conductors providing at least one of electrical connection to the circuit cells and electrical connection between one or more circuit elements in the cells, each of the circuit cells being configured having gates and active regions forming a grid, wherein, for a given active layer in the device, each active region is substantially linear relative to one another and substantially parallel to one another, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same; and a plurality of active layers, each of the active layers being stacked in a substantially vertical dimension relative to one another when viewed in cross-section, at least a first one of the plurality of circuit cells being formed in a first one of the active layers, and at least a second one of the plurality of circuit cells being formed in a second one of the active layers; and one or more active regions are broken up in at least one region so as to satisfy specified minimum design rule requirements associated with a fabrication process used to form the device.