Patent ID: 6127221
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A method of fabricating a capacitor structure, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, featuring a combination of process steps, such as a storage node shape, pre-clean procedure, deposition of hemispherical grain silicon, (HSG), seeds, annealing to convert said HSG silicon seeds to an HSG silicon layer, and deposition of a silicon nitride layer, all performed in situ, in a ultra high vacuum, (UHV), system, comprised the steps of:providing an underlying transfer gate transistor, comprised of a gate structure, on a gate insulator layer, insulator spacers on the sides of said gate structure, and a source/drain region in an area of said semiconductor substrate, not covered by said gate structure;forming a storage node contact hole, in a composite insulator layer, exposing the top surface of a source region;forming a doped polysilicon plug, in said storage node contact hole;forming said storage node shape, on the top surface of said composite insulator layer, and overlying, and contacting, the top surface of said doped polysilicon plug, with native oxide forming on exposed surfaces of said storage node shape;removing a portion of said native oxide from said exposed surfaces of said storage node shape;removing remaining portion of said native oxide from said exposed surfaces of said storage node shape, in said UHV system;selectively depositing said HSG silicon seeds, on said exposed surfaces of said storage node shape, in situ, in said UHV system;performing an anneal procedure, in situ, in said UHV system, to form a DRAM storage node electrode, comprised of said HSG silicon layer, on said storage node shape, with said HSG silicon layer formed via the reaction between said HSG silicon seeds and a top portion of said storage node shape;depositing a silicon nitride layer, in situ, in said UHV system;performing an oxidation procedure, creating a nitride--oxide, capacitor dielectric layer, comprised of a silicon oxide layer, on said silicon nitride layer, with said silicon oxide layer, formed via oxidation of a top portion of said silicon nitride layer; andforming an upper plate electrode, for said capacitor structure.