Patent ID: 8120102
Filing Date: 2012-02-21
Classification: H01L

Abstract:
1. A semiconductor device comprising: a MISFET disposed in a chip region of a semiconductor substrate and having a gate comprised of a first conductor, a source, and a drain; a gate electrode disposed over the gate and electrically coupled to the gate, the gate electrode being comprised of a second conductor having a resistivity lower than the first conductor, and the gate electrode having a gate finger portion; a source electrode disposed over the source and electrically coupled to the source, the source electrode being comprised of the second conductor, and the source electrode having a plurality of regions; a drain electrode disposed over the drain and electrically coupled to the drain of the MISFET; a gate bump electrode disposed over the gate electrode and electrically coupled to the gate of the MISFET; a plurality of source bump electrodes disposed over each of the respective plurality of regions of the source electrode; a gate lead disposed over the gate bump electrode and electrically coupled to the gate bump electrode; a source lead disposed over the source bump electrodes and electrically coupled to the plurality of source bump electrodes; a drain lead disposed over the drain electrode and electrically coupled to the drain electrode; and a resin body sealing the semiconductor substrate, wherein the gate electrode and the source electrode are formed in a same conductive layer, and wherein the gate finger portion of the gate electrode is located between two adjacent regions of the plurality of regions of the source electrode.