Patent ID: 8619480
Filing Date: 2013-12-31
Classification: G06F

Abstract:
1. A method for calibration of a memory controller, comprising: determining if an unused memory location exists in a memory; in response to a determination that the unused memory location exists, writing a first pattern to the unused memory location; in response to a determination that the unused memory location does not exist, determining if a second pattern exists in the memory; iteratively modifying a first delay of a first delay control module among a plurality of delay values, the first delay control module configured to delay a clock or data signal by the first delay; for each iteration of modification of the first delay, reading from a memory location including the first pattern or the second pattern; and based on the results of reading from the memory location, modifying one or more second delays, each second delay associated with one of one or more second delay control modules, the one or more second delay control modules each configured to delay the clock or data signal by the one or more second delays.