Patent ID: 7263600
Filing Date: 2007-08-28
Classification: G06F

Abstract:
1. A system comprising: a memory file including an entry configured to store a first addressing pattern and a first tag, wherein the memory file is configured to compare the first addressing pattern included in the entry to a second addressing pattern of a load operation, wherein each of the first and second addressing patterns specifies one or more address operands used to generate a respective data value address, and wherein if the second addressing pattern matches the first addressing pattern stored in the entry, the memory file is configured to link a data value identified by the first tag to a speculative result of the load operation; an execution core coupled to the memory file, wherein the execution core is configured to access the speculative result when executing a second operation that is dependent on the load operation; and a load store unit coupled to the memory file and configured to verify the link between the data value identified by the first tag and the speculative result of the load operation by performing a comparison between one or more addresses.