Patent ID: 7462916
Filing Date: 2008-12-09
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a trench isolation region having a plurality of inner edges defining a bounded area, said inner edges including a first edge and a second edge remote from and parallel to said first edge, and further including a third edge extending between said first and second edges and a fourth edge extending between said first and second edges, said fourth edge being remote from and parallel to said third edge; an active semiconductor region disposed within said bounded area, said active semiconductor region having a longitudinal direction in a direction extending between said first and second edges and a transverse direction in a direction between said third and fourth edges, a field effect transistor (“FET”) having a channel region, a first source-drain region and a second source-drain region disposed within said active semiconductor region, a length of said channel region being oriented in said longitudinal direction, and a width of said channel region being oriented in said transverse direction; a first triangle-shaped stressor element disposed within said bounded area having an edge extending from said first edge to said third edge of said trench isolation region, said first stressor element applying a first stress to said active semiconductor region in a first direction to apply a first torsional stress to said active semiconductor region; and a second triangle-shaped stressor element disposed within said bounded area having an edge extending from said second edge to said fourth edge of said trench isolation region, said second stressor element applying a second stress to said active semiconductor region in a second direction to apply a second torsional stress to said active semiconductor region.