Patent ID: 6537848
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A method of creating ultra-thin semiconductor packages, comprising the steps of:(a) providing a first substrate having a first and a second surface, said first substrate comprising: (i) a multiplicity of second substrates having a first and second surface; (ii) an interconnect substrate comprising copper traces for said second substrates, said interconnect substrate having a first and a second surface, said first surface of said interconnect substrate being in contact with said second surface of the first substrate; (iii) a solder mask having a first and a second surface for said second substrates; (iv) points of electrical contact in the first and the second surface of said first substrate for said second substrates; (v) points of electrical interconnect in the first surface of said interconnect substrate; (vi) said points of electrical interconnect provided in said first surface of said interconnect substrate being connected with said traces of the interconnect substrate; (vii) said points of electrical interconnect provided in the first surface of said interconnect substrate further being electrically connected with points of electrical interconnect provided in the second surface of said second substrates; (viii) said solder mask exposing points of electrical contact provided in the first surface of said first substrate for said second substrates; (ix) said second substrates provided in said first substrate further having been provided with a cut-out through said first substrate of a size allowing insertion of a semiconductor die therein, said insertion leaving a distance between sidewalls of said die and an internal perimeter of said cut-out through said first substrate; (b) optically inspecting said first substrate; (c) mounting and cutting said first substrate to a desired size; (d) pre-baking said first substrate; (e) attaching a copper foil to the second surface of said interconnect substrate; (f) inserting a semiconductor die in said cut-out provided in said first substrate for said second substrates, said semiconductor die having a first surface and a second surface, said first surface having been provided with points of electrical contact for said second substrates, said second surface of said semiconductor die being in contact with said first surface of said interconnect substrate; (g) curing said first substrate; (h) plasma cleaning exposed surfaces of said first substrate; (i) providing wire bond connections between points of electrical contact provided in said first surface of said semiconductor die and said points of electrical contact in said first surface of said first substrate; (j) optically inspecting said first substrate for defects; (k) plasma cleaning said first substrate; (l) providing a mold compound surrounding the semiconductor die and the bond wires for said second substrates, said mold compound molding partially overlapping the first surface of the solder mask; (m) providing a black ink topping on the second surface of said copper foil for said second substrates; (n) curing said black ink topping and said mold compound; (o) attaching solder balls to points of electrical contact provided in said first surface of said first substrate for said second substrates, using the solder mask as a guide in placing the solder balls with respect to the second substrates; (p) providing laser marking overlying the black ink topping for said second substrates; (q) dividing or singulating said first substrate into said second substrates, said second substrates comprising a semiconductor die; (r) optically inspecting the singulated second substrates; (s) electrically testing the second substrates; (t) packaging second substrates that pass the electrical testing; and (u) shipping the packaged second substrates.