Patent ID: 6970365
Filing Date: 2005-11-29
Classification: G05F,H02M,Y02B

Abstract:
1. A power factor correction circuit, comprising: a first latch having an output for initiating a coil current in response to a transition edge of a clock signal to generate a PFC signal, and an input for receiving a control signal; a current modulation circuit having a first input coupled for receiving the PFC signal to establish a charging time of the coil current, a second input coupled for sensing the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output for providing the control signal as a function of the charging time and the duty cycle; and a current sensor having an input coupled for sensing the coil current and an output for providing a sense signal, the current sensor including a first amplifier having a first input coupled to the input of the current sensor and a second input for establishing a threshold level of the coil current, and the current sensor also including a second latch having a first input coupled to the output of the first latch, a second input coupled to an output of the first amplifier and an output coupled to the second input of the current modulation circuit for generating the sense signal as a first logic state on the transition edge of the clock signal and as a second logic state when the coil current falls below the threshold level.