Patent ID: 6365455
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method of forming an electrically programmable read-only memory (EPROM) cell, said method comprising:providing a substrate having a dielectric layer thereon; forming a gate electrode having edges overlying said dielectric layer, said gate electrode having a nitride cap layer thereon; forming a first oxide layer overlying said nitride cap layer and edges of said gate electrode; forming an amorphous silicon layer overlying said oxide layer to a selected thickness; forming a second oxide layer overlying said amorphous silicon layer; forming sidewall spacers on said edges of said gate electrode from at least said thickness of amorphous silicon and a portion of said second oxide layer, wherein the second oxide layer acts as a width-limiting structure, said width-limiting structure determining at least one dimension of at least one of said sidewall spacers during the formation of the sidewall spacers; and after forming the sidewall spacers, converting said thickness of said amorphous silicon into a dielectric layer comprising silicon.