Patent ID: 9209116
Filing Date: 2015-12-08
Classification: H01L,H03F

Abstract:
1. A semiconductor device package, comprising: a solid metal base comprising a top surface; an electrically conductive chip mounting area on the top surface; a first pair of conductive leads attached to and insulated from the base, the first pair comprising first and second leads extending away from one another such that the first lead extends laterally beyond a first edge of the base and the second lead extends laterally beyond a second edge of the base opposite the first edge; a second pair of conductive leads attached to and insulated from the base, the second pair comprising third and fourth leads extending away from one another such that the third lead extends laterally beyond the first edge and the fourth lead extends laterally beyond the second edge; a first amplifier attached to the top surface and comprising a first terminal electrically connected to the first lead and a second terminal electrically connected to the second lead; and a second amplifier attached to the top surface and comprising a first terminal electrically connected to the third lead and a second terminal electrically connected to the fourth lead, wherein the first pair is separated from the second pair by a horizontal gap between inner edge sides of the first and third leads and between inner edge sides of the second and fourth leads, wherein a reference line in the horizontal gap that extends perpendicular to the first and second edges of the base divides the chip mounting area into first and second chip mounting sections, wherein an area of the first chip mounting section is smaller than an area of the second chip mounting section, and wherein the first and second leads have a smaller width than the third and fourth leads.