Patent ID: 6297992
Filing Date: 2001-10-02
Classification: G11C

Abstract:
An EPROM writing circuit comprising:a cell array consisting of an EPROM cell;a word line decoder and a bit line decoder for respectively decoding an address and a writing signal and enabling corresponding word lines and bit lines among a plurality of word lines and bit lines;a level sensing unit for sensing a level of a booster voltage and outputting a level sensing signal;a decoding unit for logically processing the level sensing and the writing signal and outputting a decoding signal;a first, a second and a third power switches enabled by the decoding signal, for switching the sensed booster voltage;a voltage distribution unit enabled by an output voltage of the power switches, for selectively stepping down the booster voltage to a different voltage level and outputting it; anda switching unit for outputting the stepped-down booster voltage to the cell array.