Patent ID: 6414621
Filing Date: 2002-07-02
Classification: H03M

Abstract:
An analog to digital converter (ADC) circuit, comprising:a clock control block for providing first and second internal clock signals; a parallel analog to digital converter for receiving and converting an analog signal into parallel digital data synchronously with the first internal clock signal; and a parallel to serial transform logic control block for transforming the parallel digital data into serial digital data synchronously with the second internal clock signal, wherein the clock control block adjusts a number of rising edges of the second internal clock signal in response to a number of bit control signals, the number of rising edges of the second internal clock signal being adjusted to be identical to a desired number of bits of serial digital data, the clock control block adjusting an output direction of the serial digital data from most significant to least significant bits or from least significant to most significant bits by providing a forwarding direction control signal to the parallel to serial transform logic control block.