Patent ID: 7660157
Filing Date: 2010-02-09
Classification: G11C

Abstract:
1. A NAND flash memory in which all bit lines are pre-charged and simultaneously read, comprising: a memory cell array including a plurality of blocks each of which includes a row decoder that is connected to word lines connected to gates of the memory cells, the drain-side select gate line and the source-side select gate line, makes a selection from the blocks by controlling the voltage applied to the drain-side select gate line and the source-side select gate line, and selects the memory cell for operation by controlling the voltage applied to the word line; and a sense amplifier that is connected to the bit lines of the memory cell array and detects data in the selected memory cell, wherein in a read operation, the p-type semiconductor substrate is set at a ground potential, the bit line is charged to a first voltage, the source line, the n-type well and the p-type well are charged to a second voltage, which lies between the ground potential and the first voltage, and in the block not selected by the row decoder, the drain-side select gate line and the source-side select gate line are charged to a third voltage, which is higher than the ground potential and is equal to or lower than the second voltage.