Patent ID: 6975135
Filing Date: 2005-12-13
Classification: H03K

Abstract:
1. An output buffer circuit, comprising: a first pull up transistor coupled to a first output terminal of the output buffer; a second transistor coupled between the first transistor and a first voltage source, an input of the second transistor being coupled to receive a first signal that controls a first voltage at the first output terminal; a third pull down transistor coupled to the first output terminal; a fourth transistor coupled between the third transistor and a second voltage source, an input of the fourth transistor being coupled to receive a second signal that controls a second voltage at the first output terminal; a fifth pull up transistor coupled between a second output terminal of the output buffer and the second transistor; a sixth pull down transistor coupled between the second output terminal and the fourth transistor, a seventh transistor coupled to the first transistor, an input of the seventh transistor being coupled to receive a third signal that controls the first voltage at the first output terminal; an eighth transistor coupled to the third transistor, an input of the eighth transistor being coupled to receive a fourth signal that controls the second voltage at the first output terminal; a ninth transistor coupled to the first transistor, an input of the ninth transistor being coupled to receive a fifth signal that controls the first voltage at the first output terminal; and a tenth transistor coupled to the third transistor, an input of the tenth transistor being coupled to receive a sixth signal that controls the second voltage at the first output terminal.