Patent ID: 7203779
Filing Date: 2007-04-10
Classification: G06F,Y02D

Abstract:
1. A bus arbitrator comprising: an input circuit receiving a first bus access request signal from a first bus device and a second bus access request signal from a second bus device, the input circuit outputting the second bus access request signal when the first bus access request signal is not enabled and blocking the second bus access request signal when the first bus access request signal is enabled, the input circuit associated with a first delay; a delay circuit generating a time-delayed first bus access request signal from the first bus access request signal and a time-delayed second bus access request signal from the second bus access request signal, the delay circuit associated with a second delay; and a comparator circuit generating a first line driver enable signal only if both the first bus access request signal and the time-delayed first bus access request signal are enabled and generating a second line driver enable signal only if both the second bus access request signal and the time-delayed second bus access request signal are enabled, wherein the second delay delays low-to-high transitions in the first and second line driver enable signals by no more than one-half of a clock cycle of a clock signal, and wherein the first delay delays high-to-low transitions in the second line driver enable signal by an amount less than the second delay but does not delay high-to-low transitions in the first line driver enable signal.