Patent ID: 7091092
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit device comprising: providing a semiconductor substrate; providing an active region on said semiconductor substrate contained by an isolation region; growing a mask oxide layer overlying said substrate and said isolation region; patterning said mask oxide layer forming an opening exposing said substrate within said active region; anisotropically etching a gate recess into said semiconductor substrate below said opening in said mask oxide layer, whereby said mask oxide layer is eroded away during said etching of said gate recess and a portion of said isolation region is removed; growing a pad oxide layer over said gate recess, said isolation region, and said semiconductor substrate; depositing a nitride layer overlying said pad oxide layer and filling said gate recess; planarizing said nitride layer to expose said pad oxide layer and top of said nitride layer filling said gate recess; growing a first overlap oxide layer on said pad oxide layer; partially etching away said nitride layer within said gate recess thereby exposing said pad oxide lining sidewalls of said gate recess; growing a second overlap oxide layer on said pad oxide layer and said first overlap oxide layer thereby thickening said pad oxide lining sidewalls of said gate recess; etching away said nitride layer remaining within said gate recess; implanting threshold adjusting ions through said pad oxide layer at bottom of said gate recess and into said substrate below said gate recess, whereby said pad oxide lining sidewalls and said first and second overlap oxide layers function as a mask for said threshold adjusting ions; isotropically etching away said pad oxide layer on said bottom of said gate recess exposing said substrate at said bottom of said gate recess; growing a gate dielectric layer overlying said substrate at said bottom of said gate recess and said second overlap oxide; depositing a polysilicon gate layer overlying said gate dielectric layer and filling said gate recess; planarizing said polysilicon gate layer to expose said top of said gate recess, said substrate and said isolation region thereby forming the gate structure comprised of said polysilicon gate layer, said gate dielectric layer, said pad oxide layer, said first overlap oxide layer and said second overlap oxide layer; depositing a screen oxide layer overlying said substrate, said isolation region and said gate structure; forming a double implanted drain (DID) structure by implanting a light dosage of ions forming lightly doped source and drain (S/D) regions of said DID structure and thereafter implanting a heavy dosage of ions forming heavily doped source and drain (S/D) regions of said DID structure; annealing said DID structure; depositing an inter-electrode dielectric layer overlying said substrate, said isolation region and said gate structure; etching contact holes in said inter-electrode dielectric layer to expose said polysilicon gate layer and said heavily doped S/D regions of said DID structure; depositing a metalization layer overlying said inter-electrode dielectric layer and filling said contact holes; patterning said metalization layer to form conductive lines; and depositing a passivation layer thereby completing fabrication of said integrated circuit device.