Patent ID: 7294563
Filing Date: 2007-11-13
Classification: H01J,H01L

Abstract:
1. A process for fabricating a vertical transistor on a semiconductor-on-insulator wafer consisting of an underlying substrate, an intermediate insulator layer and a top crystalline semiconductor active layer, said process comprising: sculpting from said active layer a 3-dimensional source-channel-drain structure having horizontal and vertical surfaces and comprising a channel with a source and drain at either end of the channel; forming a thin gate oxide layer over a section of the channel; forming a 3-dimensional gate structure over said thin gate oxide layer; while supporting the wafer in a plasma immersion ion implantation reactor chamber, introducing into the chamber a dopant-containing process gas and applying RF plasma source power into the chamber to generate from said process gas a plasma; and applying RF plasma bias power or voltage to the wafer to draw ions from the plasma toward the wafer across a plasma sheath at a sufficient energy to implant the ions in the source-drain-channel structure.