Patent ID: 8711634
Filing Date: 2014-04-29
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array having a NAND cell unit including a plurality of memory cells connected in series each having a control gate and a charge storage layer, one end of the NAND cell unit being connected to a bit line via a first selection gate transistor, the other end of the NAND cell unit being connected to a source line via a second selection gate transistor, control gates of the plurality of memory cells being respectively connected to word lines, gates of the first and second selection gate transistors being respectively connected to the first and second selection gate lines; and a control circuit, wherein during data read process, the control circuit gives a read voltage to a selected word line connected to a selected memory cell of the plurality of memory cells from which data is read, and gives read pass voltages for turning on the memory cells regardless of cell data to unselected word lines connected to unselected memory cells of the plurality of memory cells, the control circuit respectively giving a first read pass voltage, a second read pass voltage, and a third read pass voltage to a first unselected word line adjacent to the selected word line at a side of at least one of a bit line and a source line, a second unselected word line adjacent to the first unselected word line at a side opposite to the selected word line, and a third unselected word line adjacent to the second unselected word line at a side opposite to the selected word line, the second read pass voltage being higher than the third read pass voltage.