Patent ID: 6721378
Filing Date: 2004-04-13
Classification: H04L

Abstract:
A circuit for receiving data comprising:a first receiver having an input for receiving said data and an input for receiving a first clock signal, whereby said data is clocked into said first receiver by said first clock signal; a second receiver having an input for receiving said data and an input for receiving a second clock signal, said first and second clock signals having an identical clock frequency and being phase shifted with respect to one another, whereby said data is clocked into said second receiver by said second clock signal; determining circuitry for determining if at least one of said receivers has correctly received said data; and enabling circuitry for selectively enabling a first output of one of the receivers in accordance with the determination made by said determining circuitry, wherein said determining circuitry is arranged to detect an indication of the beginning of the data and to determine if the data received by at least one of said receivers includes a known pattern, and wherein said determining circuitry is arranged to determine if the data received by at least one receiver includes the known pattern only if the indication of the beginning of data has been detected.