Patent ID: 9032122
Filing Date: 2015-05-12
Classification: G06F

Abstract:
1. A system comprising: a main memory; a plurality of Peripheral Component Interconnect (PCI) adapter devices having virtual functions with direct memory access (DMA) capabilities to the main memory, wherein at least one of the plurality of Peripheral Component Interconnect (PCI) adapter devices has at least two of the virtual functions; a plurality of PCI Bridges that provide corresponding real PCI busses upon which the plurality of PCI adapter devices reside, the real PCI busses having real PCI bus numbers; a plurality of virtual machines each having one or more device drivers configured to manage access to the virtual functions using one or more hypervisors configured to translate the separate and different virtual PCI busses to the real PCI bus numbers; and a memory storing offset values relative to the common address range and a mapping of each virtual function to a distinct location in the main memory; and wherein the one or more hypervisors are configured to: notify at least one of the device drivers that one of the virtual function is in a hold state: modify, for the one virtual function, an offset value in the memory; and notify the at least one of the device drivers that the hold state has been lifted.