Patent ID: 6498089
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A semiconductor integrated circuit device, comprising:a semiconductor substrate having a circuit area defined in a central portion of said semiconductor substrate and a moisture-proof ring area surrounding the circuit area in a loop-shape; a plurality of semiconductor elements formed in the circuit area; a plurality of insulating layers formed on said semiconductor substrate; cavities for forming wiring layers of a multi-layer structure, said cavities being formed in each of said insulating layers in the circuit area, each of said cavities in each wiring layer of the multi-layer structure having a lower via hole and an upper wiring pattern trench; wiring layers of the multi-layer structure formed in said cavities including a lower via conductor filled in the via hole and an upper wiring pattern filled in the wiring pattern trench, the via conductor forming an electrical connection between the wiring patterns of different wiring layers or between the wiring pattern and the semiconductor element; moisture-proof ring trenches of a multi-layer structure corresponding to said cavities for forming the wiring layers of the multi-layer structure, said moisture-proof ring trenches surrounding the circuit area of said semiconductor substrate in a loop-shape and formed through said insulating layers in the moisture-proof ring area, a width of each of said moisture-proof ring trenches corresponding to a corresponding one or ones of said via holes being set smaller than a minimum diameter of said via holes; and a conductive moisture-proof ring filled in corresponding one of said moisture-proof ring trenches and made of a same layer as the via conductor and the wiring pattern.