Patent ID: 6947310
Filing Date: 2005-09-20
Classification: G11C

Abstract:
1. A memory device, comprising: an input circuit comprising: a first ferroelectric capacitor coupled between the first internal node and a plateline node; a second ferroelectric capacitor coupled between the second internal node and the plateline node; a control circuit coupled with the plateline node, the control circuit being operable to selectively provide a plateline signal to the plateline node to store the data state to the first and second ferroelectric capacitors according to the first and second voltages when the input circuit is in the first mode; a restore circuit coupled with the first and second internal nodes, the restore circuit being operable to restore the data state from the first and second ferroelectric capacitors to the first and second internal nodes when the input circuit is in the second mode; and an output circuit coupled with the first and second internal nodes, the output circuit being operable to provide a restored data state as an output according to the data state from the first and second ferroelectric capacitors when the input circuit is in the second mode.