Patent ID: 7208095
Filing Date: 2007-04-24
Classification: H01L,Y10S

Abstract:
1. A method for fabricating bottom electrodes of stacked capacitor memory cells, comprising: providing a semiconductor wafer having a substrate; forming a plurality of contact plugs on the surface of the substrate; depositing a sacrificial conductive layer on the surface of the substrate and the plurality of contact plugs; depositing a mask layer on the sacrificial conductive layer; etching a plurality of trenches into the mask layer, each of the trenches being located above the contact plugs and ranging from the surface of the mask layer to the contact plugs; removing the sacrificial conductive layer above the contact plugs; depositing a metal layer on the surface of the mask layer, the metal layer covering the side walls of the trench and the contact plugs; removing the mask layer by wet etching; providing a wafer dryer, the wafer dryer comprising a basin filled with a cleaning liquid for rinsing the wafer and a drying area above the surface of the cleaning liquid; providing a voltage source having a first terminal and a second terminal; providing a counter electrode, the counter electrode being electrically connected to the first terminal; electrically connecting the second terminal of the voltage source to the sacrificial conductive layer and metal layer; immersing the wafer and the counter electrode into the cleaning liquid of the basin; selecting an output voltage of the voltage source; gradually withdrawing the wafer from the basin into the drying area; and removing the sacrificial conductive layer by dry etching the sacrificial conductive layer selectively to the metal layer to form electrically isolated elements of the metal layer serving as bottom electrodes.