Patent ID: 7539851
Filing Date: 2009-05-26
Classification: G06F

Abstract:
1. A method for using register readiness to facilitate value prediction, comprising: loading a previously computed result for a function to a destination register for the function from a lookup table, wherein some or all of the lookup table is stored in an L1 cache, an L2 cache, and a memory that are separate from a register file where the destination register is located; waiting for a first predetermined delay and then using a Branch-Register- Not-Ready (BRNR) instruction to check the readiness of the destination register, wherein the first predetermined delay is proportional to a latency of a return of data from the L1 cache; and if the destination register is not ready, rechecking the destination register one or more times, wherein each recheck of the destination register involves waiting for a predetermined delay corresponding to each recheck and then checking the readiness of the destination register by using a BRNR instruction, wherein a predetermined delay for a first recheck is proportional to a latency of a return of data from the L2 cache and wherein a predetermined delay for a second recheck is proportional to a latency of a return of data from the memory; if the destination register remains not ready, using the function to calculate a result for the function; otherwise if any BRNR instruction indicates that the destination register is ready, using the previously computed result in the destination register as the result of the function.