Patent ID: 6167549
Filing Date: 2000-12-26
Classification: G06F

Abstract:
A memory access control device comprising:a data register connected with a first memory and a second memory for temporary storage of data from said first memory and said second memory;a data processor connected to said data register;a control logic circuit for controlling and driving said data processor to subdivide data in said data register into a plurality of data fields;an encoder controlled by said control logic circuit to add a respective error correcting code to every data field in said data register;at least one error correcting code recorder for temporary storage of the error correcting codes from said encoder;a decoder controlled by said control logic circuit to decode the added error correcting code at every data field in said data register, and to temporarily store the decoded error correcting codes in said at least one error correcting code recorder; andan error correcting logic circuit connected between said at least one error correcting code recorder and said data processor, and controlled by said control logic circuit to check the error correcting codes received from said data fields through said decoder, and to control said data processor in correcting an incorrect data field.