Patent ID: 7208335
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A method for fabricating a chip-scale package, comprising: positioning a sacrificial substrate adjacent to a back side of a device substrate with a plurality of conductive elements on an active surface of the sacrificial substrate being aligned along at least one street between adjacent semiconductor devices on an active surface of the device substrate; securing the active surface of the sacrificial substrate to the back side of the device substrate with a quantity of dielectric material electrically isolating each conductive element of the plurality of conductive elements from the back side of the device substrate; severing the device substrate to physically separate the adjacent semiconductor devices from one another and to form peripheral edges of each semiconductor device of the adjacent semiconductor devices, relative positions of the adjacent semiconductor devices being maintained by the sacrificial substrate; forming a dielectric coating on at least portions of at least some of the peripheral edges; exposing at least portions of at least some conductive elements of the plurality of conductive elements, each exposed conductive element comprising a lower section of a contact pad of the chip-scale package; and forming a peripheral section of the contact pad in communication with a corresponding lower section and on a peripheral edge of a semiconductor device.