Patent ID: 7433803
Filing Date: 2008-10-07
Classification: G06F

Abstract:
1. A performance monitor for monitoring performance on a processor, the performance monitor comprising: a control register, the control register configured to store a first instruction address, and wherein the control register is further configured to store a second instruction address; a comparator coupled to the control register, the comparator configured to receive an current instruction address, the comparator comparing the current instruction address to the first instruction address, and wherein the comparator is configured to compare the current instruction address to the second instruction address; a counter coupled to the comparator, the counter including an input to receive event indicators, the counter starting counting of the received event indicators when the current instruction address corresponds to the first instruction address, and wherein the counter stops counting of the received event indicators when the current instruction address corresponds to the second instruction address; and a clock cycle counter, the clock cycle counter including an input to receive clock cycles, the clock cycle counter starting counting of the received clock cycles when the current instruction address corresponds to the first instruction address, the clock cycle counter stopping counting of the received clock cycles when the current instruction address corresponds to the second instruction address.