Patent ID: 6215326
Filing Date: 2001-04-10
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of super-regions disposed on the programmable logic device in a two-dimensional array of intersecting rows and columns of such super-regions, each of said super-regions including a plurality of regions of programmable logic and a region of memory, each of said programmable logic regions having a plurality of inputs and a plurality of outputs and being programmable to perform any of several logic functions on its inputs to produce its outputs, and said memory region also having a plurality of inputs and a plurality of outputs and being responsive to its inputs to produce its outputs based at least in part on its inputs and data stored in the memory region; andprogrammable interconnection circuitry for selectively connecting said outputs of said programmable logic regions and said memory regions to said inputs of said programmable logic regions and said memory regions, wherein, for each of the super-regions, the programmable interconnection circuitry comprises:a plurality of first interconnection conductors uniquely associated with that super-region, each of the first interconnection conductors that is associated with a super-region extending substantially continuously adjacent to all of the logic and memory regions in that super-region and being connectable only to the logic and memory regions in that super-region.