Patent ID: 6745277
Filing Date: 2004-06-01
Classification: G06F

Abstract:
A method for interleaving packets in a memory having multiple memory banks, comprising:identifying output queues assigned to packets received over a network, the output queues associated with output ports used for outputting the packets back over the network and the packets for any of the output ports stored in any of multiple memory banks; identifying multiple reads and multiple writes for a same memory cycle, the memory cycle including multiple clock cycles for conducting the multiple reads and multiple writes; identifying multiple reads that need to be read from the same memory banks during the memory cycle; sequencing the clock cycles for the identified multiple reads as far apart as possible from each other during the memory cycle; identifying the output queues associated with the multiple writes for the memory cycle; selecting the memory banks for the multiple writes to be different than the memory banks previously used for storing received packets directed to the same output queues thereby causing back-to-back reads for the same output queues to be read from different memory banks; identifying any of the multiple writes and multiple reads for the memory cycle that need to access the same memory banks; sequencing clock cycles for the identified writes and reads as far apart as possible during the memory cycle; and accessing the memory banks during the memory cycle in sequence according to the clock cycle sequencing so that the memory banks can be precharged during the memory cycle while other memory banks are being accessed during the memory cycle.