Patent ID: 6232170
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A method of forming a merged logic DRAM device having a trench etched into a silicon-on-insulator (SOI) substrate without etching into a buried oxide (BOX) layer present in said SOI substrate, said method comprising the steps of:(a) providing an SOI substrate having a buried oxide layer formed therein, said SOI substrate further comprising selected array device areas and selected logic device areas;(b) forming an insulator layer on the surface of said SOI substrate;(c) forming a photoresist on said insulator layer over said selected logic device areas;(d) etching said insulator layer in said selected array device areas;(e) etching the SOI substrate through said BOX layer in said selected array device areas;(f) removing said photoresist located over said selected logic device areas;(g) forming an epitaxial silicon layer in the etched areas of said selected array device areas; and(h) forming a trench in said selected array device areas of said SOI substrate.