Patent ID: 6878599
Filing Date: 2005-04-12
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming an etching mask comprising a first insulating film having an opening portion including a gate forming portion and source/drain extension regions forming portions on a surface of a semiconductor substrate; forming a trench in the semiconductor substrate corresponding with the opening portion; forming a gate insulating film comprising a second insulating film on an inner surface of the trench; forming a gate material film to cover a surface of the semiconductor substrate; forming a third insulating film on the gate material film; etching-back upper surfaces of the third insulating film and the gate material film to form a gate forming etching mask comprising the third insulating film buried in the gate material film on a central portion between both sides of the opening portion on a source/drain side; and anisotropically etching the gate material film using the third insulating film buried in the gate material film as a mask to process the gate, thereby forming a MIS-type field effect transistor having a self-aligned gate formed on the central portion between both sides of the trench on the source/drain side, in which a position where an impurity concentration of highly-doped source/drain regions in the direction of depth is maximum substantially coincides with a position where an impurity concentration of the source/drain extension regions in the direction of depth is maximum.