Patent ID: 6772316
Filing Date: 2004-08-03
Classification: G06F

Abstract:
A method for updating and invalidating store data, comprising:writing a first data line in a cache, wherein the cache comprises: a data section a prevalidated cache tag section, and a first translation lookaside buffer (TLB); generating physical TLB hit vector corresponding to the first data line; storing the physical TLB hit vector in the prevalidated cache tag section; comparing a virtual TLB hit vector to a prevalidated cache tag, the prevalidated cache tag comprising TLB hit formation; if the virtual TLB hit vector and the prevalidated cache tag match, declaring a cache hit; if the virtual TLB hit vector and the prevalidated cache tag do not match, declaring a cache miss; restricting TLB operations of the first TLB to operations having a low latency requirement; providing a second TLB, larger than the first TLB, wherein the second TLB comprises entries for operations having a high latency; setting a store valid bit in a tag associated with the second TLB when the first data line is written in the cache; and clearing the store valid bit based on an invalidation operation, wherein an invalidation comprises one or more of a system bus request whereby an address compare shows a data line having a same physical address as the first data line, a cache flush operation, read-modify-write operations, and hardware failure recovery operations.