Patent ID: 8966488
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. A processor comprising: an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions; and a plurality of synchroniser modules comprising dedicated hardware logic for synchronising threads including respective synchronisation registers operable to store synchronisation information relating to the synchronisation of the threads; wherein the dedicated hardware logic of each of said synchroniser modules is operable, in response to execution by the execution unit of one or more synchroniser allocation instructions, to associate with a group of at least two threads by storing synchronisation information relating to that group in the synchronisation registers; and wherein the dedicated hardware logic of each of said synchroniser modules is operable, when thus associated, to synchronise the threads of said group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group, the synchronisation information relating to the associated group remaining stored, and the dedicated hardware logic thereby remaining thus associated, following said synchronisation point.