Patent ID: 6664585
Filing Date: 2003-12-16
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a semiconductor substrate, and a pad disposed on said semiconductor substrate; an interlayer dielectric layer disposed on said semiconductor substrate so as to insulate the pad; a bit line stack forming a series of bit lines disposed on the interlayer dielectric layer; a pair of bit line spacers extending, respectively, along side walls of each of the bit lines of the bit line stack; a storage node contact hole extending between the bit line spacers of an adjacent pair of the bit lines of said bit line stack and through the interlayer dielectric layer to the pad, wherein the storage node contact hole is self-aligned with the bit line spacers of said adjacent pair of the bit lines; and a multi-layered storage node contact plug occupying the entirety of said storage node contact hole, said multi-layered storage node contact plug including first storage node contact plug layer of titanium nitride conformal to the storage node contact hole and a second storage node contact plug of polysilicon disposed on the first storage node contact plug layer and filling the storage node contact hole within said first storage node contact plug layer.