Patent ID: 6211011
Filing Date: 2001-04-03
Classification: G11C,H01L

Abstract:
A method for manufacturing asymmetric memory cells in a nonvolatile memory cell array, the method comprising the steps of:forming a semiconductor substrate characterized by a first conductivity type;forming a dielectric covering the semiconductor substrate;forming a first and a second column of floating gate cores on the dielectric;implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first column and the second column, the first dopant characterized by a second conductivity type;ion implanting at an angle in a first orientation a second dopant in a second dopant strip, the second dopant strip aligned with the first dopant strip and extending below the second column, the second dopant characterized by being the first conductivity type, and having a higher concentration than said substrate;ion implanting at an angle in a second orientation a third dopant in a third dopant strip, the third dopant strip aligned with the first dopant strip and extending below the first column, the third dopant characterized by being the second conductivity type, and having a lower concentration than the first dopant strip; andcompleting formation of control gate dielectric and control gates.