Patent ID: 6651152
Filing Date: 2003-11-18
Classification: G06F

Abstract:
A microcomputer comprising:a plurality of memories; a bus interface circuit connected to said plurality of memories through a bus group; a central processing unit to be coupled to said memories via said bus interface circuit, and operating using said memories, said central processing unit being reset in response to a reset signal to stop its operation; a download circuit coupled to said memories via said bus interface circuit, and carrying out data input/output with respect to said memories; a first reset signal generation circuit generating and applying to said central processing unit a first reset signal to reset said central processing unit; a second reset signal generation circuit generating and applying to said plurality of memories and said bus interface circuit a second reset signal according to a mode set signal specifying input/output execution with one of said memories using said download circuit and said first reset signal; and a selector selectively coupling said central processing unit and said download circuit to said bus interface circuit in response to said mode set signal.