Patent ID: 7242627
Filing Date: 2007-07-10
Classification: G11C

Abstract:
1. A semiconductor device comprising: a bit line pair coupled to a plurality of memory cells; a pre-sense-amplifier coupled to the bit line pair; a local bit line pair coupled to the pre-sense amplifier; a sense amplifier between the local bit line pair and including PMOS transistors which are supplied with a first voltage and NMOS transistors which are connected a first control line which transfers a first control signal; a first pre-charge circuit which charges the bit line pair to a first pre-charge potential; a second pre-charge circuit which charges the local bit line pair to a second pre-charge potential larger than the first pre-charge potential; and a second control line which transfers a second control signal by which an operation state of the pre-sense amplifier is controlled, wherein the pre-sense amplifier starts an amplification operation and generates a difference of potential between the local bit line pair by discharging the local bit line pair according to a difference of potential between the bit line pair when the second control signal is activated, wherein the PMOS transistors of the sense amplifier start to amplify the difference of potential between the local bit line pair when the second control signal is activated, wherein the NMOS transistors of the sense amplifier start to amplify the difference of potential between the local bit line pair when the first control signal is activated, the first control signal being activated after the second control signal, wherein the sense amplifier amplifies one of the local bit lines to a first potential and the other of the local bit lines to a second potential according to the difference of the potential between the local bit line pair, and wherein the first pre-charge potential is between the first potential and the second potential.