Patent ID: 9093132
Filing Date: 2015-07-28
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: a first plane configured to perform a first operation directed to a first memory cell array in response to a first command received from a controller, wherein the first plane comprises: a second plane configured to perform a second operation directed to a second memory cell array physically separate from the first memory cell array in response to a second command received from the controller, wherein the second plane comprises: a data input/output (I/O) circuit that transfers read data to the controller via a common data bus obtained from at least one of the first memory cell array and the second memory cell array in response to a read command, that transfers program data received from the controller via the common data bus to at least one of the first memory cell array and the second memory cell array in response to a program command, and that provides a ready/busy signal indicating one of an idle state and a busy state, wherein the first command and second command are coincidently applied to the first control logic and second control logic by the data I/O circuit, the first address and second address are coincidently applied to the first address decoder and second address decoder by the data I/O circuit, and the state of the ready/busy signal determines whether the first command and the second command are executed.