Patent ID: 6841463
Filing Date: 2005-01-11
Classification: H01L

Abstract:
1. A method of forming an interlevel dielectric comprising the steps of: providing a first dielectric layer over a surface of a substrate situated on a semiconductor wafer; depositing a conductive layer on said first dielectric layer, the conductive layer having an upper surface and a lower surface; depositing an additional layer on said conductive layer; patterning said conductive layer and said additional layer by: depositing a layer of dielectric material having a dielectric constant of less than about 3.6 to fill said space, the layer of dielectric material extending above the upper surface of the adjacent lines of conductive material and below the lower surface of the adjacent lines of conductive material sufficient to reduce the fringe capacitance therebetween, but not extending directly over or under the upper and lower surfaces of the adjacent lines of conductive material; removing said layer of dielectric material from the top thereof downward to at least to the level of the top of said additional layer; and depositing a second dielectric layer over all layers on said surface of said substrate.