Patent ID: 6754865
Filing Date: 2004-06-22
Classification: G11C

Abstract:
An integrated circuit comprising;a semiconductor memory for receiving therein m-bit internal data (m is an integer of 2 or more) and outputting the data from an internal address; a logic circuit for receiving the m-bit internal data and outputting the data to the semiconductor memory while designating the internal address; an internal data bus connected between the semiconductor memory and the logic circuit, having m internal data lines, for transmitting the m-bit internal data between the semiconductor memory and the logic circuit; a data input/output terminal group for receiving n-bit external data (n is less than m and an integer of 1 or more) and outputting the data to the outside; an external data bus connected between the logic circuit and the data input/output terminal group, having n external data lines, for transmitting the n-bit external data between the logic circuit and the data input/output terminal group; and a data switching unit for connecting the external data line to a plurality of the internal data lines when a mode is switched from a normal mode to a test mode; wherein the data switching unit includes at least one simultaneous write circuit, each connected to a plurality of internal data lines and an external data line, for receiving from the external data lines bit data which is at least a part of n-bit data on the external data bus from the external data line, dividing the data into a plurality of bit data of a same value, and simultaneously outputting the divided data to the internal data lines; and at least one coincidence judgement circuit of the same number as that of the simultaneous write circuit(s), each connected to same internal data lines and external data line as the simultaneous write circuit, for effecting coincidence judgement of data out of the simultaneous write circuit on these internal data lines and outputting a coincidence judgement result to the external data line.