Patent ID: 6100195
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method of forming an interconnect line on a first dielectric layer on a semiconductor device comprising:said first dielectric layer having a top surface,forming an interconnect trench hole in said first dielectric layer, said interconnect trench hole having walls and a bottom in said first dielectric layer,forming a blanket diffusion barrier on said top surface, on said walls and said bottom of said interconnect trench hole,filling said interconnect trench hole lined with said diffusion barrier with a copper metal line and overgrowing said copper metal line above said interconnect trench hole above said top surface covered with said diffusion barrier,then polishing the surface of said device removing the overgrowth of said metal layer to planarize the surface of said device and said copper metal line to achieve coplanarity of metal deposit with the topography of said top surface of said first dielectric layer, anddepositing a passivating metal layer on the surface of said copper metal line encapsulating said copper metal line at the top of said interconnect trench hole.