Patent ID: 6912157
Filing Date: 2005-06-28
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix and which includes a plurality of blocks, each of said blocks having memory cells connected to one word line or a plurality of word lines; and a row decoder circuit configured to select a word line in said memory cell array, said row decoder circuit including: wherein only said first transistors of the first conductivity type apply voltages to said word lines, at least one of said second transistors is provided in a row decoder circuit corresponding to every block, and source or drain of said at least one second transistor is connected to a gate of said first transistor, and when at least one word line in a selected block is biased to a first voltage which is higher than a power supply voltage, said second transistor applies a second voltage to said gate of said first transistor, and said second voltage is higher than the power supply voltage.