Patent ID: 7466164
Filing Date: 2008-12-16
Classification: H03K

Abstract:
1. A multiplexer (MUX) circuit comprising: a logic gate; a plurality of pull-up transistors coupled in series between a reference voltage and an input of said logic gate; a plurality of current control elements with outputs coupled to said plurality of pull-up transistors and said input of said logic gate; a plurality of input signals coupled to respective inputs of said plurality of current control elements, wherein said plurality of input signals comprise a plurality of select signals and a plurality of corresponding data signals; wherein when a select signal exceeds a threshold value, deactivating a pull-up transistor and enabling a data signal that corresponds to said select signal to provide input to said logic gate; and wherein when said select signal does not exceed said threshold value, activating said pull-up transistor and preventing said data signal from providing input to said logic gate.