Patent ID: 6615380
Filing Date: 2003-09-02
Classification: G01R,G06F

Abstract:
In a computer implemented test synthesis system, a method of implementing design for test circuitry within an integrated circuit design, said method comprising the steps of:a) accessing a netlist description of an integrated circuit design, said netlist description comprising a plurality of memory cells; b) replacing said plurality of memory cells with a plurality of scan cells; c) interconnecting said plurality of scan cells with a plurality of nets to form a scan chain; d) selecting a partition point from one of said plurality of nets, wherein said partition point segments said scan chain into a first segment and a second segment; and e) inserting a reconfiguration circuitry at said partition point, wherein said reconfiguration circuitry enables selectively coupling a truncated test pattern to an applicable one of said first segment or said second segment during test application, and wherein said truncated test pattern includes specified one or more of a plurality of bits applicable to one of said first segment or said second segment and excludes unspecified one or more of said plurality of bits inapplicable to one of said first segment or said second segment.