Patent ID: 6202164
Filing Date: 2001-03-13
Classification: G06F,H04L

Abstract:
A computer system, comprising:a central processing unit (CPU);a data buffer operably coupled to said CPU, wherein said CPU is configured to read data from said data buffer at a first predetermined clock rate;a clock controller coupled to said data buffer and configured to monitor levels of data in said data buffer, and to provide a signal indicative of said levels of data;a video camera operably coupled to said data buffer and configured to generate said data and write said data to said data buffer at a second predetermined clock rate, wherein said video camera in coupled to a clock that includes: a data clock configured to provide a data clock signal; and a programmable clock divider coupled to said data clock;wherein said second predetermined clock rate is generated by programming a value into said programmable clock divider and dividing said data clock by said value; andwherein said value is programmed responsive to said clock controller determining that said levels of data in said data buffer cross a predetermined threshold, such that said second predetermined clock rate approximates said first predetermined clock rate.