Patent ID: 7715256
Filing Date: 2010-05-11
Classification: G11C

Abstract:
1. A memory device, comprising: a plurality of externally-accessible terminals; a command decoder configured to receive memory command signals through at least one of the externally accessible terminals, the command decoder configured to generate memory control signals responsive to predetermined combinations of the command signals; an address decoder configured to receive address signals through at least one of the externally accessible terminals, the address decoder configured to generate row and column addressing signals responsive to the address signals; at least one memory array, the at least one memory array configured to write data to and read data from locations corresponding the address signals responsive to the memory control signals; a data path extending between at least one of the plurality of externally accessible terminals and the memory array and configured to couple data signals to and from the memory array; and an active termination circuit configured to set the input impedance of a first plurality of the externally accessible terminals to a predetermined value, the active termination circuit comprising: