Patent ID: 8723570
Filing Date: 2014-05-13
Classification: H03L

Abstract:
1. A delay-locked loop, comprising: a first delay unit for receiving a clock, and generating a first delay clock according to a first delay time of the first delay unit and the clock; a second delay unit coupled to the first delay unit for receiving the first delay clock, and generating a second delay clock according to a second delay time of the second delay unit and the first delay clock; a third delay unit coupled to the second delay unit for receiving the second delay clock, and generating a third delay clock according to a third delay time of the third delay unit and the second delay clock, wherein the third delay time is equal to the second delay time, a sum of the first delay time and the second delay time is equal to a period of the clock; an internal delay unit of an application circuit coupled to the third delay unit for receiving the third delay clock, and generating an output data clock of the application circuit according to a fourth delay time and the third delay clock, wherein the first delay time is equal to the fourth delay time; a phase detector for generating a phase detection signal only according to the clock and the second delay clock; and a controller coupled to the phase detector for receiving the phase detection signal, and generating and outputting a phase control signal to the second delay unit and the third delay unit according to the phase detection signal, wherein the phase control signal is not transmitted to the first delay unit; wherein the second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal.