Patent ID: 8640070
Filing Date: 2014-01-28
Classification: G06F,H03K

Abstract:
1. An apparatus comprising: a plurality of target field programmable gate arrays interconnected in accordance with a connection topology and mapping portions of a target system; a control module coupled to said plurality of target field programmable gate arrays; a balanced clock distribution network configured to distribute a reference clock signal; a balanced reset distribution network coupled to said control module and configured to distribute a reset signal to said plurality of target field programmable gate arrays, said control module and said balanced reset distribution network being cooperatively configured to initiate and control a simulation of said target system with said plurality of target field programmable gate arrays; and a plurality of local clock control state machines residing in said target field programmable gate arrays, said local clock control state machines being coupled to said balanced clock distribution network and obtaining said reference clock signal therefrom, said plurality of local clock control state machines being configured to generate a set of stoppable clocks and a set of free-running clocks synchronized to the stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of said simulation of said target system.