Patent ID: 7349938
Filing Date: 2008-03-25
Classification: G06F

Abstract:
1. An adder circuit comprising: a plurality of adder stages interconnected in series, a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages; wherein carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least a given one of the adder stages are substantially balanced in terms of a number of gate delays experienced by said signals within said adder circuit in arriving at their respective inputs of the carry out computation element, and wherein the adder circuit processes data received via at least two inputs through the plurality of adder stages to produce an output signal output from an output of the final adder stage, such that the adder circuit exhibits minimized dynamic switching power and short circuit power in processing the data received via the at least two inputs.