Patent ID: 9000512
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A multi-layer wafer level assembly comprising: a first layer, the first layer including a temporary fabrication substrate; a second layer coupled to a facing of the first layer, the second layer including: a mass of conductive material, a circuit device, and insulation material; a thickness of the circuit device extending from a first surface region on the facing of the first layer to an exposed surface facing of the second layer, the exposed surface facing disposed on the second layer opposite a respective surface of the second layer coupled to the facing of the first layer; a thickness of the mass of conductive material extending from a second surface region on the facing of the first layer to the exposed surface facing of the second layer; the insulation material disposed in the second layer between the circuit device and the mass of conductive material; and wherein the exposed surface facing of the second layer is openly accessible to apply an electrically conductive link on the exposed surface facing between the circuit device and the conductive material.