Patent ID: 8455340
Filing Date: 2013-06-04
Classification: H01L

Abstract:
1. A method of fabricating a transistor having a source region, a drain region, and a gate region on a substrate, the method comprising: implanting, into a surface of the substrate, a n-doped n-well; forming a gate oxide between the source region and the drain region of the transistor; covering the gate oxide with a conductive material; implanting, into the source region of the transistor, a p-doped p-body; implanting, into the source region of the transistor, a first n-doped n+ region to overlap the p-body, implanting, only into the source region of the transistor, a source, heavily double-diffused (SHDD) region to overlap the p-body, the SHDD region being an n-doped region implanted to a depth about equal to that of the first n-doped n+ region, the SHDD region extending further laterally than the first n-doped n+ region beneath the gate oxide, a portion of the SHDD region overlapping a portion of the first n-doped n+ region, the first n-doped n+ region extending further laterally than the SHDD region toward the source region; implanting, into the source region of the transistor, a p-doped p+ region, the p-doped p+ region in proximity to the first n-doped n+ region; implanting, into the drain region of the transistor, a second n-doped n+ region; and implanting into the drain region an n-doped shallow drain, wherein the SHDD region is implanted using a dopant concentration greater than that used in the implant of the n-doped shallow drain but less than that used in the implant of the first n-doped n+ region.