Patent ID: 6326661
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A semiconductor device comprising a semiconductor body having a region of a first conductivity type adjoining a surface of the semiconductor body, which semiconductor body is provided at the surface with a non-volatile memory cell comprising a source and a drain of an opposite, second conductivity type provided in the semiconductor body, between which source and drain the surface of the semiconductor body is provided with a floating gate and a select gate, the floating gate and the select gate both having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and having side-wall portions extending substantially transversely to the surface of the semiconductor body, above which floating gate a control gate is situated, which control gate overlaps the select gate, characterized in that the control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the side-wall portions of the floating gate facing the source and the drain, and ends above the substantially flat surface portion of the select gate wherein the floating gate does not extend over the select gate.