Patent ID: 7378286
Filing Date: 2008-05-27
Classification: H01L

Abstract:
1. A method of fabricating a ferroelectric memory transistor comprising: preparing an isolation substrate; forming a semiconductive metal oxide channel layer on the isolation substrate; forming a replacement gate stack on the semiconductive metal oxide layer, the replacement gate stack comprising a sacrificial layer over the semiconductive metal oxide layer; forming drain and source regions on opposite sides of the replacement gate stack; filling the areas surrounding the replacement gate stack while exposing the top portion of the replacement gate stack; removing the sacrificial layer portion of the replacement gate stack; forming the remainder of the gate stack, the remainder of the gate stack comprising; a ferroelectric material layer over the semiconductive metal oxide layer; and a top electrode conductive layer over the ferroelectric material layer, and forming drain and source regions on opposite sides of the replacement gate stack before forming any of the other recited components of the gate stack.