Patent ID: 7881895
Filing Date: 2011-02-01
Classification: H03L,H04W,Y02D

Abstract:
1. A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods, the method comprising: generating incremented counter values at a counter responsive to edges of the second clock signal; for each of the plurality of calibration periods, storing in memory an initial incremented counter value from the counter at an initial edge of the first clock signal for the respective calibration period and storing in the memory a final incremented counter value from the counter at a final edge of the first clock signal for the respective calibration period wherein at least two of the plurality of calibration periods are overlapping with different initial and final edges of the first clock signal; for each of the plurality of calibration periods, determining a number of edges of the second clock signal occurring during the respective calibration period using the initial and final incremented counter values stored in the memory; and determining a relationship between the first and second clock signals using a sum of a number of edges of the second clock signal occurring during each of the plurality of calibration periods and using a sum of a number of first clock signal cycles occurring during each of the plurality of calibration periods.