Patent ID: 6643755
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A memory system, comprising:a memory, the memory logically partitioned into K two-dimensional partitions, each of the partitions having N columns, and S rows; a first set of K one-dimensional buffers, where each buffer has a width of N addressable locations, and each of the K one-dimensional buffers is associated for one or more memory transactions, with a unique one of the K two-dimensional partitions; K registers, each of the K registers uniquely associated with a unique one of the K two-dimensional partitions; and a memory controller coupled to the memory, coupled to the K registers, and further coupled to the K one dimensional buffers, the memory controller configured to direct memory transactions between each of the K partitions and each of the respectively associated K one-dimensional buffers, the memory controller further configured to record, into each of the K registers, a number indicative of the row of the partition with which a memory transaction has been performed; wherein K, N, and S are integer numbers.