Patent ID: 6556645
Filing Date: 2003-04-29
Classification: G11C

Abstract:
A multi-bit counter comprising a multiplicity of unit counters, each for receiving bit combinations of a unit external address signal, setting an external input by a count set signal and increasing bits by a count increase signal and a carry to output an internal address signal and a final state signal; and a plurality of logical combining means, each for combining the carry and the final state signal of each unit counter to apply the combined signal to the carry of a next unit counter, the unit counter including:a first NAND gate for NAND-operating the count increase signal and the carry to output an inverted increase control signal; a first inverter for inverting the output of the first NAND gate to output an increase control signal; a multiplicity of counting means, each receiving the bit combinations of the unit external address signal to output a number of state signals; a multiplicity of state means for presetting all possible bit combinations of the unit external address signal and selectively outputting bit combinations as a plurality of internal address signals in response to the state signals outputted from the multiplicity of counting means; and a second to a fifth inverter, an input of the second inverter coupled to an output of the third inverter and an input of the third inverter coupled to an output of the second inverter, an input of the fourth inverter coupled to an output of the fifth inverter and an input of the fifth inverter coupled to an output of the fourth inverter, for latching the plurality of the internal address signals selectively outputted by the multiplicity of the state means.