Patent ID: 6304944
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A processor comprising:a region register defining a physical address region and including an attributes field defining at least one memory attribute of the physical address region;a translation lookaside buffer (TLB) comprising a plurality of entries, each of the plurality of entries storing a linear address tag and a corresponding physical address defining a page of memory to which linear addresses matching the linear address tag translate, each of the plurality of entries also configured to store an indication of the at least one memory attribute from the region register if the physical address is within the physical address region; anda translation control unit coupled to the region register and the TLB, wherein the translation control unit is configured, in response to a miss in the TLB for a first linear address, to: (a) locate a translation corresponding to the first linear address within a plurality of page tables in a main memory, the translation defining a first physical address corresponding to the first linear address, (b) compare the first physical address with the physical address region defined by the region register, (c) store the first physical address in a first entry of the plurality of entries of the TLB, and (d) store the indication of the at least one memory attribute from the region register in the first entry if the first physical address is within the physical address region;wherein the at least one memory attribute is independent of the translation.