Patent ID: 6747984
Filing Date: 2004-06-08
Classification: H04L

Abstract:
An apparatus comprising:an interface configured for connection to a bus; a memory connected to the interface; a controller connected to the memory, wherein the controller has a plurality of modes of operation including: a first mode of operation in which the controller is idle and monitors for signals; a second mode of operation, responsive to detecting a request to transmit data signal in the first mode of operation, in which the controller allocates a first buffer space in the memory for a first data transfer, loads a first set of data into the first buffer space in the memory, and begins the data transfer; a third mode of operation, responsive to receiving a blocked indication, in which the controller halts the data transfer, determines if a second set of data is available for transfer; a fourth mode of operation, responsive to another set of data being present in the memory, in which the memory controller allocates a second buffer space for a second data transfer, loads the second set of data to the second buffer space, and begins the second data transfer.