Patent ID: 8117475
Filing Date: 2012-02-14
Classification: G06F,Y02D

Abstract:
1. A system comprising: a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode; a plurality of system components operable to operate in a sleep or low power mode and in an active mode; a direct memory access (DMA) controller operating independently from said CPU and operable to operate in a sleep or low power mode and in an active mode, wherein the DMA controller is further operable to transfer data from and to a memory or peripheral device, wherein when said system is in a sleep or low power mode, upon an event only said DMA controller and if necessary any system component which is necessary to perform a DMA transaction are switched into active mode while said CPU remains inactive, and wherein said DMA controller generates a signal after said DMA transaction has been partially completed which is used to de-activate said sleep mode of said CPU.