Patent ID: 8997099
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A processor, comprising: an instruction decode logic to decode instructions; and an execution unit to execute the instructions, wherein execution of at least one instruction is to cause an interrupt; a first logic to determine whether the interrupt is a top-down virtualization event or a bottom-up virtualization event; a second logic to determine whether to transfer control of the processor from a first child guest to an intervening virtual machine monitor hosting the first child guest in response to the recognized virtualization event, by checking, if the virtualization event is recognized as a top-down virtualization event, a control structure of the first child guest before checking a control structure of the intervening virtual machine monitor hosting the first child guest, and by checking, if the virtualization event is recognized as a bottom-up virtualization event, the control structure of the intervening virtual machine monitor hosting the first child guest before checking the control structure of the first child guest.