Patent ID: 6496131
Filing Date: 2002-12-17
Classification: H03M

Abstract:
A capacitor-array D/A converter which comprises:a thermometer decoder (103) for thermometer-decoding a decoder input signal having first through m-th input bits (D3 to D7) to produce an output signal (107) having first through n-th output bits (T1 to T31), where m is an integer not less than two and where n is equal to (2mâˆ’1); first through n-th switches (SU1 to SU31) corresponding to said first through said n-th output bits of said thermometer decoder; and a capacitor array (104) comprising first through n-th capacitors (8C1 through 8C31) corresponding to said first through said n-th switches; each of said first through said n-th switches being supplied with a corresponding bit of said first through said n-th output bits from said thermometer decoder, said corresponding bit corresponding to said each of the first through the n-th switches, each of the first through the n-th switches operating so that, when said corresponding bit has a logic â€œ1â€  level, a corresponding capacitor of said first through said n-th capacitors is applied with a predetermined voltage (VREF) not equal to zero and that, when said corresponding bit has a logic â€œ0â€  level, said corresponding capacitor is grounded (205), said corresponding capacitor corresponding to said each of the first through the n-th switches; said capacitor array having a main area; said first through said n-th capacitors being arranged in said main area and in a row direction of said capacitor array consecutively in the order of selection from the center outward, alternating to the left and the right, to be symmetrical.