Patent ID: 7774730
Filing Date: 2010-08-10
Classification: G06F

Abstract:
1. A method of designing a semiconductor integrated circuit, performed by a computer, comprising: reading, by using the computer, an RTL data indicating RTL description of said semiconductor integrated circuit; and providing, by using the computer, a gating cell for clock gating at least one target element of said semiconductor integrated circuit during logic synthesis of said RTL description, wherein said gating cell includes a latch circuit that latches an enable signal, which activates the at least one target element, in synchronization with a clock signal, wherein said gating cell is not provided in a timing exception path containing a design target circuit which needs not meet design timing constraints of the semiconductor design, wherein said providing a gating cell comprises: analyzing said RTL description to generate a logic circuit that is logically equivalent to said RTL description, wherein said logic circuit includes a flip-flop as said target element and a selector; reading a timing-exception specification data that specifies timing-exception; analyzing a select signal input to said selector and, if said select signal is independent of said timing-exception, identifying said selector as a target selector; and providing said gating cell such that said enable signal is generated from only said select signal input to said target selector.