Patent ID: 6403424
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method for forming a self-aligned mask read only memory by dual damascene trenches comprising the steps of:forming a gate oxide layer on a substrate and a defined first polysilicon layer; doping the substrate by using the first polysilicon layer as a mask so as to be formed with a buried bit line; depositing a first oxide layer and removing part of the first oxide layer until the first polysilicon layer is exposed; forming a patterned second polysilicon layer on the substrate to cover part of the first polysilicon layer and part of the first oxide layer; removing the first polysilicon layer and the first oxide layer by using the second polysilicon layer as a mask; depositing a second oxide layer on the substrate, and removing part of the second oxide layer until the second polysilicon layer is exposed; removing the second polysilicon layer and part of the first polysilicon layer so as to be formed with dual damascene trenches; forming a first patterned photo resistor on the substrate to cover part of the first polysilicon layer; using the first patterned photo resistor as a mask to perform ion implantation process so as to form a self-aligned first ion doping area below the exposed first polysilicon layer; removing the first patterned photo resistor; forming a second patterned photo resistor on the substrate to cover part of the first polysilicon layer; using the second patterned photo resistor as a mask to perform a second ion implantation so as to form a self-aligned second ion doping area on the substrate below the first polysilicon layer; removing the second patterned photo resistor; depositing a conductive layer to fully fill the dual damascene trenches on the substrate; and removing part of the metal layer until the second oxide layer is exposed.