Patent ID: 6694418
Filing Date: 2004-02-17
Classification: G06F

Abstract:
A cache defining arrangement comprising an arrangement having at least one of a memory hole modification scheme, and a mixed technique scheme where differing non-memory-hole portions of cacheable memory space is defined with at least two mutually different defining techniques, comprising the mixed technique scheme to use a bottom-up scheme to define a first non-memory-hole portion of cacheable memory space, and to use a top-down scheme to define a second non-memory-hole portion, wherein in the bottom-up scheme, mainly substantially additive blocks of cacheable memory space are defined so as to cumulatively define the first non-memory-hole portion, and wherein in the top-down scheme, an oversized block of cacheable memory space is defined, and then mainly substantially subtractive blocks of cacheable memory space are subtracted so as to subtractively define the second non-memory-hole portion.