Patent ID: 7749837
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A method for fabricating a memory cell in a memory array, the method comprising: forming a tunnel dielectric layer over a substrate; forming a plurality of isolation trenches in the tunnel dielectric layer and substrate, each isolation trench filled with an oxide dielectric having an upper portion that extends above the tunnel dielectric layer; forming a substantially concave shape on each side of the upper portion of each oxide dielectric using an isotropic strip process; forming a single layer floating gate over the tunnel dielectric layer and around the upper portions; etching the floating gate to form multi-level troughs in the floating gate substantially above each concave shape of each upper portion; forming an intergate dielectric layer over the floating gate that is composed of a nitride-oxide; and forming a control gate over the intergate dielectric layer wherein the control gate is composed of a polysilicon/silicide/metal structure.