Patent ID: 6597625
Filing Date: 2003-07-22
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory section that is composed of a plurality of memory banks, an address-input buffer section that generates and outputs an internal address signal corresponding to an external address signal, which is an address signal input from the outside, a first address-latch circuit section that latches data indicative of a desired memory bank contained in the internal address signal output from said address-input buffer section to output to each memory bank of said memory section, and a second address-latch circuit section that latches data indicative of a cell address contained in the internal address signal output from said address-input buffer section to output to each memory bank of said memory section, said second address-latch circuit being arranged at a neighborhood of said address-input buffer sections, wherein said first address-latch circuit section further latches data that is used for generating commands for performing the operation control of each memory bank of said memory section, and outputs the latched address data into each memory bank of said memory section, wherein said first address-latch circuit section is arranged at a central part of a memory chip of said semiconductor memory device.