Patent ID: 8107079
Filing Date: 2012-01-31
Classification: G03F

Abstract:
1. A method of determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level comprising: creating a first target pattern on a first lithographic field containing an integrated circuit pattern, the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center; creating a second target pattern on a second lithographic field that is different than the first lithographic field and containing an integrated circuit pattern, the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center, the second target pattern center intended to be at the same location as the first target pattern center, the second distance being the same or different than the first distance and the plurality of sub-patterns of the second target pattern being substantially non-overlapping with the plurality of sub-patterns of the first target pattern; and measuring positioning error between the first lithographic field and the second lithographic field using the first target pattern and the second target pattern, wherein the plurality of sub-patterns of the first target pattern and the second target pattern form cross shapes that are located at corners of a geometric shape.