Patent ID: 6165893
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method of forming insulating layers to reduce parasitic capacitance, comprising:forming an insulating interlayer on a semiconductor substrate;forming a first conductive layer and a first high thermal conductivity, high dielectric constant insulating layer on the insulating interlayer successively;forming a first wire by removing portions of the first high thermal conductivity, high dielectric constant insulating layer and the first conductive layer wherein the first high thermal conductivity, high dielectric constant insulating layer remains only on the first wire;filling spaces where the first high thermal conductivity, high dielectric constant insulating layer and conductive layer have been removed with a second low dielectric constant insulating layer such that the second low dielectric constant insulating layer extends between and contacts adjacent wire portions to reduce parasitic capacitance between wire portions;forming a third high thermal conductivity, high dielectric constant insulating layer on the second low dielectric constant insulating layer and the remaining first high thermal conductivity, high dielectric constant insulating layer;forming a via hole exposing a portion of the first wire by removing portions of the first high thermal conductivity, high dielectric constant and third high thermal conductivity, high dielectric constant insulating layers which overlap each other;forming a conductive plug filling the via hole; andforming a second wire on the third high thermal conductivity, high dielectric constant insulating layer wherein the second wire is connected to the plug electrically.