Patent ID: 7061412
Filing Date: 2006-06-13
Classification: H03M

Abstract:
1. An apparatus for reducing harmonic error power, in a current-mode self-calibration digital-to-analog converter (DAC), comprising: a shift register, outputting a shift timing signal; a coarse decoder, receiving and decoding a digital signal to output a compensation decoding signal; a shift, coupled to the shift register and the coarse decoder, shifting the compensation decoding signal based on the shift timing signal and outputting a shifted compensation decoding signal; a unit current array, comprising a plurality of unit current sources for outputting unit currents; a calibration switch network, coupled to the shift register and the unit current array, calibrating the unit currents from the plurality of unit current sources based on the shift timing signal and a reference current and outputting calibrated unit currents; and a current switch, coupled to the shift and the calibration switch network, comprising a plurality of switches for receiving the calibrated unit currents and conducting or blocking the calibrated unit currents based on the shifted compensation signal, outputting the conducted calibrated unit currents as an analog current signal.