Patent ID: 6058495
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A method for testing a plurality of memory cells simultaneously to generate fail bit information, in a semiconductor memory device including a memory cell array divided into a plurality of sub-arrays each being divided again into a plurality of blocks by a word line, said each block including a plurality of the memory cells connected respectively at intersections of a plurality of bit lines and one word line, the method comprising the steps of:simultaneously storing test data bits received from a plurality of multibit input/output pins into the memory cells, a test data bit of the same logic state received from one of the multibit input/output pins being stored into selected ones of the memory cells in each block simultaneously;comparing the data bits stored into a same block with one another, to generate a comparison data bit; andtransferring said comparison data bit to said multibit input/output pins.