Patent ID: 6629234
Filing Date: 2003-09-30
Classification: G06F

Abstract:
An apparatus in a pipeline microprocessor for providing a speculative address operand associated with a result of an arithmetic operation, the arithmetic operation being prescribed by a preceding micro instruction, the apparatus comprising:speculative operand calculation logic, within an address stage of the pipeline microprocessor, configured to perform the arithmetic operation to generate the speculative address operand prior to when execute logic executes the preceding micro instruction to generate the result, wherein the speculative address operand is obtained from the result that is to be generated when said execute logic executes the preceding micro instruction, and wherein the result has not yet been generated by said execute logic and written to a register file for access by following micro instructions, and wherein the result is required by an address-dependent micro instruction within said address stage for computation of a memory address, wherein said speculative operand calculation logic comprises: addition logic, configured sum a first source operand with a second source operand, said source operands being prescribed by the preceding micro instruction; an arithmetic opcode decoder, configured to direct said addition logic to sum said source operands if the arithmetic operation prescribed by the preceding micro instruction is an addition operation; and subtraction logic, coupled to said arithmetic opcode decoder, configured to subtract said second source operand from said first source operand; wherein, if the arithmetic operation is a subtraction operation, said arithmetic opcode decoder directs said subtraction logic to subtract said second source operand from said first source operand; and an update Forwarding cache, coupled to said speculative operand calculation logic, configured to tenporarily store the speculative address operand, wherein said address-dependent micro instruction can retrieve the speculative address operand, thereby permitting said address-dependent micro instruction to proceed without incurring delay, and wherein the speculative address operand is provided by said update forwarding cache to said address-dependent micro instruction prior to when said address-dependent micro instruction enters said address stage, thereby allowing said address-dependent micro instruction to generate said memory address without incurring said delay, and wherein said update forwarding cache comprises a plurality of cache buffers, each of said plurality of cache buffers corresponding to each of a plurality of speculative operands.