Patent ID: 6892279
Filing Date: 2005-05-10
Classification: G06F

Abstract:
1. A memory system comprising: (a) at least one bank of memory having a plurality of memory locations for storing data; (b) a memory controller operatively coupled to said at least one bank of memory for controlling said bank of memory; (c) a buffer operatively coupled to said at least one bank of memory said buffer comprising a plurality of buffer entries, each buffer entry including an address portion and a data portion, said address portion addressing at least one of the plurality of memory locations in said bank of memory, said data portion being row head data and including a first portion of the data stored in said at least one of the plurality of memory locations; (d) a buffer controller operatively coupled to said buffer for issuing instructions to said buffer; and (e) a second portion of the data associated with an address stored in said address portion of said buffer, said second portion being not included in said data portion of said buffer.