Patent ID: 6658554
Filing Date: 2003-12-02
Classification: G06F

Abstract:
In an electronic processor executing data-producing instructions, producing data to be loaded into a memory, and data-consuming instructions, reading data from the memory, a memory bypass circuit comprising:a) a dependency table linking in read-read dependencies first data-consuming instructions to second data-consuming instruction according to a probability that both data consuming instructions read data produced by a same data-producing instruction; b) a storage register storing the data received by a first data consuming instruction identified to a read-read dependency of the dependency table the data being that data transmitted from the memory in response to execution of the first data consuming instruction; and c) table reviewing circuitry responsive to execution of a second data-consuming instruction to review the dependency table and when the second data-consuming instruction is part of a read-read dependency with the first data consuming instruction, reading the data for that read-read dependency from the storage register.