Patent ID: 6542019
Filing Date: 2003-04-01
Classification: H03D,H03F,H03K

Abstract:
A linearized transconductance circuit for converting an input into an output wherein said input comprises first and second phases having a differential voltage therebetween and wherein said output comprises first and second phases having a differential current therebetween that is proportional to said differential voltage comprising:first, second, third, and fourth MOS transistors, each said transistor having a gate, a drain, and a source, wherein said gates of said first and third MOS transistors are coupled to said input first phase, wherein said drains of said first and third transistors are coupled to said output first phase, wherein said gates of said second and fourth MOS transistors are coupled to said input second phase, and wherein said drains of said second and fourth MOS transistors are coupled to said output second phase; a first constant current source coupled to said sources of said first and fourth MOS transistors; a second constant current source coupled to said sources of second and third MOS transistors; a first capacitor coupled in parallel with said first constant current source; and a second capacitor coupled in parallel with said second constant current source.