Patent ID: 6226737
Filing Date: 2001-05-01
Classification: G06F

Abstract:
A microprocessor for performing single precision floating point multiplication of a multiplicand by a multiplier, the multiplicand and the multiplier being provided in extended precision format, comprising:a translator, configured to receive a single precision multiplication instruction, and configured to decode said single precision multiplication instruction into an associated single precision micro instruction sequence; andextended precision floating point execution logic, coupled to said translator, configured to receive said associated single precision micro instruction sequence, and configured to multiply the multiplicand by the multiplier to generate a single precision product, wherein said extended precision floating point execution logic normally performs a floating point multiplication by generating a low-order partial product followed by generation of a high-order partial product, said low-order partial product representing multiplication of a low-order part of an extended precision multiplier with an extended precision multiplicand, said high-order partial product representing multiplication of a high-order part of said extended precision multiplier with said extended precision multiplicand, wherein said low-order partial product is generated during a first traversal through said extended precision floating point execution logic and wherein said high-order partial product is generated during a second traversal through said extended precision floating point execution logic, and wherein, when said associated single precision micro instruction sequence is received said extended precision floating point execution logic generates said single precision product by executing only said second traversal to generate said high-order partial product, said high-order partial product comprising said single precision product.