Patent ID: 8582382
Filing Date: 2013-11-12
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: memory; a plurality of inputs for receiving from a previous device a command latch enable signal, an address latch enable signal and an information signal; a device identification register for storing register bits that distinguish the memory device from other possible memory devices; circuitry for comparing identification bits in the information signal with the register bits to provide positive or negative indication as to whether the identification bits match the register bits, and if the indication is positive then the memory device is configured to respond as having been selected by a controller, and if the indication is negative then the memory device is configured to respond as having not been selected by the controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry configured to interpret, when the indication is positive, the information signal based on the command latch enable signal and the address latch enable signal; and bypass circuitry configured to transfer, when the indication is negative, the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.