Patent ID: 8468281
Filing Date: 2013-06-18
Classification: G06F

Abstract:
1. A method comprising: applying a first busy read out signal from a first output of a first memory controller directly to a first input of a second memory controller to indicate to the second memory controller when the first memory controller releases an external address bus subsequent to an access to the external address bus and an external data bus by the first memory controller; and applying a first busy write out signal from a second output of the first memory controller directly to a second input of the second memory controller to indicate to the second memory controller when the first memory controller releases the external data bus subsequent to an access to the external address bus and the external data bus by the first memory controller; and applying a second busy read out signal from a third output of the second memory controller directly to a third input of the first memory controller to indicate to the first memory controller when the second memory controller releases the external address bus subsequent to an access to the external address bus and the external data bus by the second memory controller; and applying a second busy write out signal from a fourth output of the second memory controller directly to a fourth input of the first memory controller to indicate to the first memory controller when the second memory controller releases the external data bus subsequent to an access to the external address bus and the external data bus by the second memory controller.