Patent ID: 6279020
Filing Date: 2001-08-21
Classification: H03H

Abstract:
A programmable co-processor circuit intended for use in conjunction with a main processor so as to form a digital filter, which circuit comprises a plurality of filter processing elements controlled by a control unit and each including an input data register having a read output connected to an input of at least one adder, at least one multiplier having an input connected to a result output of the adder and having another input connected to a read output of a coefficient memory, and having a result output connected to an input of a final adder having an output which supplies an intermediate result of the calculation of an equation upon each cycle of a clock, characterized in that, for multiplexing a plurality of different filters, each filter processing element further comprises a number of partial-result registers (y-data), which number is equal to the desired number of filters to be multiplexed, each register has a write input connected to the output of the final adder (6), and each register has a read output connected to one of the inputs (y-old) of the final adder.