Patent ID: 6512262
Filing Date: 2003-01-28
Classification: G11C,H01L

Abstract:
A non-volatile semiconductor memory device comprising:a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region; a floating gate formed above the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer which is located on the device region side; a control gate formed above the floating gate; and a booster electrode having faces opposed to a pair of second surfaces of the floating gate which are substantially perpendicular to the pair of first side faces, wherein a distance between a pair of first side faces of the floating gate is equal or not more than a width of the device region defined by the device isolation insulation layer, and the control gate comprises: a first conductive film formed above the floating gate; and a second conductive film formed on the first conductive film and the device isolation insulation film.