Patent ID: 6373136
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate; an integrated circuit structure formed on said semiconductor substrate; a multi-layer wiring structure formed above said integrated circuit structure; and a number of pads formed on said semiconductor substrate, wherein said multi-layer wiring structure comprises: a lower wiring structure; an interlayer insulating film covering said lower wiring structure; a wiring trench formed in said interlayer insulating film from an upper surface thereof, and a via hole passing through said interlayer insulating film from a lower surface of said wiring trench in an inner area thereof and reaching said lower wiring structure, said via hole having a diameter smaller than a width of said wiring trench; an insulating pillar pattern projecting upward from the lower surface of said wiring trench in an area outside of said via hole, the insulating pillar pattern being made of a same material as said interlayer insulating film, wherein a first occupied area factor of said insulating pillar pattern in a first area of said wiring trench near said via hole is higher than a second occupied area factor of said insulating pillar pattern in a second area of said wiring trench remote from said via hole; and a dual damascene wiring formed by filling said wiring trench and said via hole with conductive material.