Patent ID: 7737779
Filing Date: 2010-06-15
Classification: H03F

Abstract:
1. An integrated circuit having a circuit for reducing distortion in a power amplifier, the integrated circuit comprising: a predistortion circuit coupled to receive a signal to be amplified; sample capture buffers coupled to an output of the predistortion circuit and an input/output port of the integrated circuit; an estimator circuit coupled to the sample capture buffers, wherein the estimator circuit generates parameters for the predistortion circuit based upon a first signal at the output of the predistortion circuit and a second signal at an output of the power amplifier received at the input/output port of the integrated circuit; a memory storing a plurality of parameter sets, wherein a parameter set of the plurality of parameter sets is selected to be applied to the predistortion circuit; and a parameter update controller coupled to the memory, wherein the parameter update controller enables updating parameters in the memory when a detected value associated with the signal to be amplified is within a configurable range of a predetermined value associated with a predetermined parameter set.