Patent ID: 6404229
Filing Date: 2002-06-11
Classification: H03K

Abstract:
A complementary logic circuit having an input, an output and comprising first and second circuit branches, each circuit branch comprising:a first transistor of a first conductivity type having a first terminal connected to a first supply node, a control terminal and a second terminal; a second transistor of the first conductivity type having a first terminal connected to the second terminal of the first transistor, a control terminal connected to a second supply node, and a second terminal; and a third transistor of a second conductivity type different to said first conductivity type, having a first terminal connected to the second terminal of the second transistor, a control terminal, and a second terminal connected to the second supply node, wherein: the control terminals of said first transistors of respective first and second circuit branches are coupled to said input; said output is connected to one of the first and second terminals of one of said second transistors; the control terminals of said third transistors of said first and second circuit branch are connected to the second terminals of said first transistors of said second and first circuit branch respectively; and said first, second, and third transistors are FETS and said first and second transistors of each circuit branch have substantially the same drain to source saturation current and said third transistors have a higher drain to source saturation current than said first and second transistors.