Patent ID: 6800526
Filing Date: 2004-10-05
Classification: H01L

Abstract:
A method for manufacturing a self-aligned split-gate flash memory cell, comprising:providing a semiconductor substrate having an active region; forming a buffer isolation layer; forming a first dielectric layer on said buffer isolation layer; removing part of said first dielectric layer to define an opening; removing said buffer isolation layer within said opening; forming a gate isolation layer on the semiconductor substrate within said opening; forming a silicon layer; implanting ions into said silicon layer to be conductive; removing part of said silicon layer and gate isolation layer, respectively, to form floating gates; forming a source region in said semiconductor substrate; forming opposite second dielectric layers along said floating gates and the sidewall of said first dielectric within said opening; depositing a polysilicon layer wherein the excess polysilicon layer is etched back; forming a conformal protection isolation layer over said polysilicon layer; removing the first dielectric layer and the buffer isolation layer outside said floating gates; forming, in order, a third dielectric layer and a control gate layer; and removing part of the control gate layer to form control gates.