Patent ID: 6077315
Filing Date: 2000-06-20
Classification: G06F

Abstract:
A compiling method for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising the steps of:a) accepting as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements;b) identifying a first configuration of the selectively reconfigurable portion of the processing unit to be used in executing the first subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the first configuration;c) identifying a second configuration of the selectively reconfigurable portion of the processing unit to be used in executing the second subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the second configuration; andcompiling the first subset of instruction statements for execution using the first configuration and compiling the second subset of instruction statements for execution using the second configuration.