Patent ID: 6404840
Filing Date: 2002-06-11
Classification: G06F,H03K

Abstract:
A frequency divider for generating a reduced frequency signal from a clock signal, said frequency divider comprising:a first configurable signal generator having an input for receiving the clock signal, an output, and a configuration port; a second configurable signal generator having an input for receiving the clock signal, an output, and a configuration port; a data source coupled to the configuration ports of said first and second signal generators making configuration data available to said first and second signal generators, said configuration data based on instructions received at an instruction port of said data source; a sequencer generating said instructions coupled between the outputs of said first and second signal generators and the instruction port of said data source, said sequencer generating said instructions based on the outputs of said first and second signal generators and passing said instructions to the instruction port of said data source; and combining logic coupled to the outputs of said first and second signal generators producing the reduced frequency signal.