Patent ID: 6021471
Filing Date: 2000-02-01
Classification: G06F

Abstract:
In a cache controller for a system having a first level cache memory and a second level cache memory, said cache controller comprising:a multiple stage address pipeline for holding at least first and second different addresses;a look-up control system, simultaneously coupled to more than one stage of said address pipeline, configured to, upon a miss of said first address in said first cache, compare said first address with tag addresses in said second cache while concurrently comparing said second address with tags in said first cache;a multiple stage data pipeline for storing data corresponding to said first and second addresses;a fetch stack for holding addresses for data to be fetched from said second level cache into said first level cache;a multiplexer, coupled to said fetch stack and to said multiple stage address pipeline, for selecting between said fetch stack and said multiple stage address pipeline so that a portion of a second level cache line other than an address immediately needed is provided through said multiplexer when no subsequent first level cache miss is pending; anda first level cache address latch coupled to an output of said multiplexer.