Patent ID: 7620828
Filing Date: 2009-11-17
Classification: G06F,Y02D

Abstract:
1. A system for dynamically controlling a clock signal used by a peripheral device that is coupled to a master device, the system comprising: a clock selector having: wherein the first clock signal input receives a first clock signal that is generated by a master device that is coupled to a peripheral device, and wherein the second clock signal input receives a second clock signal that is generated by the peripheral device, and wherein a control signal sent to the control input causes the clock selector to selectively send, via the clock signal output, either the first clock signal or the second clock signal to the peripheral device; wherein the clock selector is controlled by a power state of the master device, and wherein the clock selector sends the second clock signal to the peripheral device when the master device is powered off, and wherein the clock selector sends the first clock signal to the peripheral device when the master device is powered on; wherein the clock selector is further controlled by a reset signal from a controller chip in the master device, and wherein the clock selector sends the first clock signal to the peripheral device when the reset signal is active, and wherein the clock selector sends the second clock signal to the peripheral device when the reset signal is inactive.