Patent ID: 8952535
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a device isolation region formed in a semiconductor substrate; a first transistor including a first gate insulation film formed over a first device region defined by the device isolation region, a first gate electrode formed over the first gate insulation film, and a first diffused regions formed in the first device region on both sides of the first gate electrode; a first insulation film formed over the semiconductor substrate and over the first transistor, and including a first opening reaching one of the first diffusion regions and a second opening reaching the first gate electrode; a first barrier metal which covers an inner wall of the first opening over the one of the first diffused regions; a first conduction layer formed in a lower part of the first opening of which the inner wall is covered with the first barrier metal and formed of a first conductor; a second barrier metal formed on the first barrier metal and the first conduction layer, the second barrier metal covers an upper portion of the inner wall of the first opening of which the inner wall is covered with the first barrier metal; a second conduction layer formed in an upper part of the first opening of which the upper portion of the inner wall is covered with the second barrier metal and formed of a second conductor; a third barrier metal which covers an inner wall of the second opening on the first gate electrode; a fourth barrier metal formed on the third barrier metal, the fourth barrier metal covers the inner wall of the second opening of which the inner wall is covered with the third barrier metal; and a third conduction layer formed in the second opening of which the inner wall is covered with the fourth barrier metal and formed of the second conductor.