Patent ID: 6240536
Filing Date: 2001-05-29
Classification: H03K

Abstract:
A latch circuit comprising:(a) a latch input component connected between a data input node and a data output node, the latch input component receiving data on the data input node, and, in response to a latch input signal, utilizing the data on the data input node to control the signal state at the data output node;(b) a first isolating component having an input coupled to the data output node and an output coupled to a first feedback node on a feedback path of the latch circuit, the first isolating component for utilizing the signal state at the data output node to develop a first feedback signal at the first feedback node;(c) a second isolating component having an input coupled to a second feedback node on the feedback path and an output coupled to the data output node, the second isolating component utilizing a signal state at the second feedback node to control the signal state at the data output node, the first isolating component and second isolating component isolating the feedback path;(d) a scan enable component connected between the first feedback node and the second feedback node, the scan enable component for decoupling the first feedback node from the second feedback node in response to a scan enabling signal and for coupling the first feedback node and second feedback node in response to a scan disabling signal;(e) a scan input component connected between a scan input node and the second feedback node, the scan input component receiving a scan in signal from the scan input node and, in response to the scan enabling signal, utilizing the scan in signal to control a signal state at the second feedback node; and(f) a scan output component connected between the first feedback node and a scan output node, the scan output component for utilizing the first feedback path signal at the first feedback node to produce a scan out signal at the scan output node.