Patent ID: 8405787
Filing Date: 2013-03-26
Classification: G02F,H01L

Abstract:
1. A tri-gate pixel structure formed on a substrate, the substrate comprising three sub-pixel regions, the tri-gate pixel structure comprising: three gate lines disposed along a first direction on the substrate; a data line disposed along a second direction on the substrate; three thin film transistors disposed on each of the sub-pixel regions respectively, each of the thin film transistors comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode of each of the thin film transistors is electrically connected to the corresponding gate line, and the source electrode of each of the thin film transistors is electrically connected to the data line; three pixel electrodes disposed in each of the sub-pixel regions respectively, and electrically connected to the corresponding drain electrode of each of the thin film transistors respectively; and a common line disposed on the substrate, wherein the common line crosses the gate lines, partially overlaps with the gate lines, and the common line and the pixel electrodes partially overlap, forming three storage capacitors, respectively; wherein the common line comprises a first common section disposed along the second direction and a plurality of second common extension parts coupled to the first common section to form three closed patterns substantially surrounding the three sub-pixel regions, and the common line and the data line are made of a same conductive layer.