Patent ID: 6380874
Filing Date: 2002-04-30
Classification: H03M

Abstract:
A method for configuring a digital correction unit for an analog to digital (A/D) converter, wherein the A/D converter includes an internal D/A converter, wherein the internal D/A converter includes a plurality M of current generators, wherein one or more of the current generators produces linearity errors in the A/D converter,wherein the digital correction unit is configurable with a set of correction values, wherein the correction values are determined from coefficients E(n) for n=0 to Mâˆ’1, wherein each coefficient E(n) is associated with one of the current generators in the internal D/A converter, the method comprising: a) for each of a plurality of possible values of a coefficient E(n): configuring the digital correction unit with a current set of correction values, wherein the current set of correction values includes a value based on one of said possible values of E(n); operating the A/D converter, wherein said operating uses dynamic element matching in the internal D/A converter; and determining a noise value from output samples of the A/D converter; and b) selecting one of said possible values for E(n) that produces the least noise value; performing steps a) and b) for a plurality of coefficients E to produce a final set of coefficients E; and configuring the digital correction unit with correction values based on the final set of coefficients E; wherein the digital correction unit is useable in correcting for linearity errors in the A/D converter.