Patent ID: 6456557
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A integrated circuit device comprising:a memory cell; a first clamp transistor; a multiplexing circuit coupled between the first clamp transistor and the memory cell for selectively coupling the first clamp transistor to the first memory cell in response to one or more control signals, wherein the multiplexing circuit generates a first resistance when the memory cell is coupled to the first clamp transistor; and a voltage regulator including: a differential amplifier having a first input terminal connected to a reference voltage; a pull-up transistor having a gate terminal connected to an output terminal of the differential amplifier, a first terminal connected to a first voltage source, and a second terminal coupled to a gate terminal of the first clamp transistor; and a feedback path connected between the gate terminal of the clamp transistor and the second input terminal of the differential amplifier, wherein the feedback path includes an emulated multiplexing circuit having a second resistance that is equal to the first resistance of the multiplexing circuit.