Patent ID: 7139849
Filing Date: 2006-11-21
Classification: G06F

Abstract:
1. A semiconductor integrated circuit device that operates while being connected to an external processing unit, comprising: a plurality of internal memories; a first processing unit for data processing and a second processing unit for data processing; a first data bus connected to the first processing unit; a second data bus connected to the second processing unit; a third data bus dedicated to the external processing unit; a first bus selector for selectively connecting the first processing unit with the first data bus or the second data bus; a second bus selector for selectively connecting the second processing unit with the first data bus or the second data bus; a first memory interface, mediating and controlling DMA data transfer requests from the first processing unit and second processing unit, which is interposed between the memory assigned to the first processing unit and the first data bus; a second memory interface, mediating and controlling DMA data transfer requests from the first processing unit and second processing unit, which is interposed between the memory assigned to the second processing unit and the second data bus; a third memory interface, controlling a data transfer, which is interposed between the memory assigned to the external processing unit and the third data bus; and a memory configuration controller for controlling the assignment of the plurality of internal memories to the first processing unit, the second processing unit and the external processing unit in accordance with an application.