Patent ID: 6538895
Filing Date: 2003-03-25
Classification: G11C,H01L

Abstract:
A configuration, comprising:a rewiring configuration formed as a leadframe having connecting lines with free ends, said free ends having a cross-sectional shape selected from the group consisting of groove-shaped free ends, trough-shaped free ends, u-shaped free ends and v-shaped free ends; and at least two thin small online package (TSOP) memory chip housings having contours of identical cross section, including a first TSOP memory chip housing and a second TSOP memory chip housing, stacked one on another, each of said two TSOP memory chip housings having an interior and at least one memory chip with a number of pins disposed in said interior of each of said two TSOP memory chip housings, said leadframe disposed one of between said two TSOP memory chip housings and at a side between said two TSOP memory chip housings, said pins leading out of said first TSOP memory chip housing being connected through said leadframe to said pins leading out of said second TSOP memory chip housing, said pins having ends leading out of said two TSOP memory chip housings and said ends formed in a shape selected from the group consisting of s-shaped ends in cross-section, step-shaped ends in cross section, kinked over downward ends and kinked over upward ends, and said pins of different ones of said two TSOP memory chip housings disposed one over another and aligned in parallel with one another in space.