Patent ID: 8004886
Filing Date: 2011-08-23
Classification: G11C

Abstract:
1. A multi-bit programming apparatus comprising: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage, wherein the programming unit is configured to program the first data and the second data in the first multi-bit cell and the second multi-bit cell by applying a high voltage to a gate terminal of the first multi-bit cell and the second multi-bit cell, the apparatus is configured to determine the first verification voltage based on a spatial distance between the first multi-bit cell and the programming unit, and the apparatus is configured to determine the second verification voltage based on a spatial distance between the second multi-bit cell and the programming unit, wherein the first verification voltage is different from the second verification voltage.