Patent ID: 8391040
Filing Date: 2013-03-05
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a first memory chip which comprises a first inductor element configured to transmit/receive a signal, and a memory cell; a second memory chip which is disposed on the first memory chip and which comprises a second inductor element configured to transmit/receive a signal, and a memory cell; and a control chip which comprises a control circuit configured to control the operations of the first and second memory chips, and a third inductor element configured to transmit/receive a signal to/from the first and second inductor elements, wherein the outer peripheries of the first and second inductor elements are included in a closed space produced by extending the outer periphery of the third inductor element in a direction perpendicular to a plane that includes the third inductor element, and the inductance of the third inductor element greater than at least one of the inductances of the first and second inductor elements.