Patent ID: 9142775
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, comprising: forming a lower electrode above a substrate; forming a first variable resistance layer above the lower electrode, the first variable resistance layer comprising a first metal oxide; forming a step in a top face of the first variable resistance layer by causing ions excited by plasma to collide with a part of the top face of the first variable resistance layer; removing residue of the first variable resistance layer remaining on the step, after the step is formed; forming a second variable resistance layer covering the step of the first variable resistance layer, after the residue is removed, the second variable resistance layer comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide and having a bend on a surface above the step; forming an upper electrode above the second variable resistance layer; forming a third variable resistance layer above the first variable resistance layer before the step is formed, the third variable resistance layer comprising a third metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and wherein, in the forming of a step, the step is formed by forming an opening penetrating through the third variable resistance layer by causing the ions to collide with a part of a top face of the third variable resistance layer, and causing the ions to collide with the first variable resistance layer exposed at a bottom of the opening, the part being located above the part of the top face of the first variable resistance layer.