Patent ID: 6046088
Filing Date: 2000-04-04
Classification: H01L

Abstract:
A method of fabricating field isolation trenches for isolating field effect transistors (FETs) in semiconductor substrate having selected ones of the trenches extend above the top surface of the substrate comprising the steps of:providing a semiconductor substrate with an upper surface;disposing an etch protective layer having a top surface and a bottom surface on a semiconductor substrate;patterning the etch protective layer and forming openings therein corresponding to the pattern;using the openings in the etch protective layer as a mask to form openings in the semiconductor substrate;filling the openings in the etch protective layer and semiconductor substrate with insulating material to be coplanar with the top surface of the etch protective layer to form field isolation trenches;masking selected sections of said field isolation trenches;planarizing the non-selected isolation trenches to the bottom level of the etch protective layer thereby leaving the selected sections of the field isolation trenches extending above the upper surface of the semiconductor substrate; anddisposing polysilicon on the upper surface of the semiconductor substrate of a thickness so that, after planarization, the polysilicon is essentially coplanar with the selected sections of isolation trenches.