Patent ID: 8253399
Filing Date: 2012-08-28
Classification: H02M,Y02B

Abstract:
1. A regulator system comprising: a high-side power transistor electrically connected between a first node and a second node, the high-side power transistor being controlled by a high-side control signal; a low-side power transistor electrically connected between the second node and a third node, the low-side power transistor being controlled by a low-side control signal; a mode controller configured to provide at least one mode control signal having a value to enable operation of the regulator system in each of a buck switching regulator mode, a boost switching regulator mode, a negative switching regulator mode, and a linear regulator mode, the mode being selected depending on the value of the mode control signal, the regulator system utilizing at least one of the high-side power transistor and the low-side power transistor to operate in the selected mode depending on at least one of an input voltage and an arrangement of external circuitry that are electrically coupled to at least one of the first node, the second node, and the third node to provide a regulated output voltage; a high-side driver configured to generate the high-side control signal as a high-side switching signal that is provided to the high-side power transistor in each of the buck switching, boost switching, and negative switching regulator modes; and a low-side driver configured to generate the low-side control signal as a low-side switching signal that is provided to the low-side power transistor in each of the buck switching, boost switching, and negative switching regulator modes, the high-side power transistor and the low-side power transistor cooperate to regulate the output voltage based on the high-side switching signal and the low-side switching signal, wherein the low-side driver further comprises a level-shifter circuit configured to generate a level-shifted switching signal based on the low-side switching signal, the level-shifted switching signal having a magnitude sufficient to deactivate the low-side power transistor if a source voltage of the low-side power transistor has a magnitude that is less than or equal to zero volts.