Patent ID: 7358577
Filing Date: 2008-04-15
Classification: H01L

Abstract:
1. A high voltage field effect transistor comprising: a p-type low concentration drain region and a low concentration source region formed on both sides of a channel formation region within a n-type region of a semiconductor substrate; a high concentration drain region formed in said low concentration drain region, an impurity concentration of which is higher than that of said low concentration drain region; a gate insulating film that at least covers a surface of said channel formation region; a field oxide film formed on said low concentration drain region so as to be in contact with an end section of said gate insulating film; a gate electrode formed on said gate insulating film and at least a part of said field oxide film so as to cover an entire channel formation region and an end section of said low concentration drain region; and a non-oxide region of said low concentration drain region, located between said gate electrode and said high concentration drain region, the non-oxide region being on a surface different from said high concentration drain region and said field oxide film.