Patent ID: 6907235
Filing Date: 2005-06-14
Classification: H04B,H04L

Abstract:
1. An apparatus for removing DC offset in a data signal comprising: a data input; a summing circuit, having a first input coupled to said data input and a second input coupled to a DC offset calculator circuit and a output coupled to a signal processing circuit, adapted to combining said data signal with a compensation value from said DC offset calculator circuit, removing said compensation value from said data signal; said signal processing circuit, having an input coupled to said summing circuit and an output coupled to a data output, adapted to amplifying, filtering and converting said data signal; said DC offset calculator circuit, having a first input and having a second input coupled to an update timing enable signal line and an output coupled to said summing circuit, adapted to calculating a DC offset from said data signal and generating said compensation value based on said DC offset and outputting said compensation value; said update timing enable signal line, coupled to said DC offset calculator circuit, adapted to providing said DC offset calculator circuit with a signal enabling said DC offset calculator circuit to output said compensation value; and a data output.