Patent ID: 9092217
Filing Date: 2015-07-28
Classification: G06F

Abstract:
1. A power management integrated circuit, comprising: a microprocessor; a non-volatile memory accessible by the microprocessor for storing programs executable by the microprocessor; a random access memory accessible by the microprocessor; and a plurality of power regulators providing a plurality of regulated output voltages from the power management integrated circuit, each power regulator being coupled to a register-controlled bus and thereby to the microprocessor and at least one power regulator providing a regulated output voltage to an external device, and wherein an external interface allows the external device to directly communicate through the register-controlled bus to the plurality of power regulators such that each power regulator is controllable by the microprocessor and the external device over the register-controlled bus, wherein the microprocessor accesses a scripted configuration file descriptive of power requirements of a system in which the power management integrated circuit is deployed, wherein each of the plurality of power regulators is provided a register address and the microprocessor and the external device control register contents sent to the register address through the register-controlled bus; and wherein the microprocessor controls the plurality of power regulators during a power-up sequence of the external device, and the external device controls the plurality of power regulators after the power-up sequence.