Patent ID: 7406654
Filing Date: 2008-07-29
Classification: G11B,H03M

Abstract:
1. A coding circuit for coding digital data that is to be recorded in a record medium, comprising: a temporal storage memory which stores original data to be recorded, intermediate processing results, and final processing results; an identification data (ID) error detection unit which processes all m bytes of an ID at a time to generate an n-byte ID error detection code, wherein m is four, and n is two; an error detection code (EDC) unit which processes the original data m bytes at a time to generate a data error detection code; a scrambling unit which scrambles the original data m bytes at a time; a first parity unit which processes the ID, the ID error detection code, the data error detection code, and the scrambled original data m bytes at a time to generate an inner code (PI) parity; and a second parity unit which includes m operation units, each of which processes the intermediate processing results one byte at a time to generate an outer code (PO) parity, wherein the original data is read from the temporal storage memory in a main scan direction for attaching of the ID, for attaching of the ID error detection code, for attaching of the data error detection code, far scrambling, and for attaching of the PI parity, followed by storage in the temporal storage memory as the intermediate processing results, until an end of an error correction (ECC) block is encountered, and wherein the intermediate processing results are read from the temporal storage memory in a sub-can direction for attaching of the PO parity, followed by storage in the temporal storage memory as the final processing results, until the end of the ECC block is encountered, a first counter which is capable of switching between counting from 0 to 15, counting from 0 to 10, counting from 0 to 13; a second counter which counts from 0 to 5, and counts up in response to a carry from said first counter; a third counter which counts from 0 to 11, and counts up in response to a carry from said second counter; a fourth counter which counts from 0 to 15, and counts up in response to a carry from said third counter, wherein all output bits of said fourth counter, bit a fifth counter which is capable of switching between counting from 0 to 15 and counting from 0 to 11; a sixth counter which counts from 0 to 16, and counts up in response to a carry from said fifth counter; a seventh counter which is capable of switching between counting from 0 to 15 and counting from 0 to 13, and counts up in response to a carry from said sixth counter; and an eighth counter which counts from 0 to 2, and counts up in response to a carry from said seventh counter, wherein all output bits of said sixth counter, all output bits of said eighth counter, all output bits of said fifth counter, and all output bits of said seventh counter are arranged in an order named for use as an address for said temporal storage memory, and bit