Patent ID: 6753707
Filing Date: 2004-06-22
Classification: H03K

Abstract:
A delay circuit, comprising:a first input circuit which receives an input signal; an output arrangement which comprises first and second output circuits to supply an output signal, the first and second output circuits being connected serially between a first power supply source and a second power supply source; a delay element, which is coupled to the output arrangement at a first node and coupled to the first input circuit at a second node, the delay element receiving from the second node a signal having substantially no delay with respect to the input signal and supplying, to the first node, a signal that is delayed with respect to the input signal, wherein the first input circuit comprises a P-type transistor and an N-type transistor connected serially between the first and second power supply sources, wherein the delay element is serially connected between the P-type transistor and N-type transistor in the input circuit, wherein the delay element comprises an N-type transistor, a gate of which is connected to a third power supply source, and a P-type transistor, a gate of which is connected to a fourth power supply source, and wherein electric potential of the third power supply source is lower than that of the first power supply source, and electric potential of the fourth power supply source is higher than that of the second power supply source.