Patent ID: 7171640
Filing Date: 2007-01-30
Classification: G06F

Abstract:
1. A system for operation verification of a semiconductor integrated circuit, the system comprising: a central processing unit; a design layout memory unit which stores therein design layout information including at least a design layout configuration of the semiconductor integrated circuit in which a plurality of semiconductor elements are integrated; a predicted final layout memory unit which stores therein a predicted final layout configuration that has been predicted by the central processing unit by adding at least an optical proximity effect to the design layout configuration; a netlister which describes a procedure for causing the central processing unit to produce, as a net list described based on the predicted final layout configuration to be used to verify a plurality of circuit characteristics, a plurality of net lists in which different physical values are registered for a common element in the predicted final layout configuration; a netlist memory unit for storing the plurality of net lists; a circuit simulator which describes a procedure for causing the central processing unit to perform operation verification of the semiconductor integrated circuit by using an arbitrary one of the plurality of net lists; and a plurality of characteristic libraries for storing characteristics of the semiconductor integrated circuit on a basis of each of the plurality of net lists used in the operation verification; wherein: the netlister describes the procedure for causing the central processing unit to produce at least a first net list for verifying power consumption and a second net list for verifying a delay time, and the plurality of characteristic libraries include a first characteristic library for storing therein the power consumption verified by using the first net list and a second characteristic library for storing therein the delay time verified by using the second net list.