Patent ID: 9195784
Filing Date: 2015-11-24
Classification: G06F

Abstract:
1. An electronic design automation system for verifying a user design, comprising: a computing system including a central processing unit for modeling the user design in a software model; an internal bus system coupled to the computing system; reconfigurable hardware logic coupled to the internal bus system and for generating a hardware model which includes at least a portion of the user design modeled in hardware, wherein the software model and the hardware model are partitioned automatically, the hardware model being partitioned automatically using, at least in part, an automatic component type analysis during a compilation process, wherein the automatic component type analysis includes a register component and a combinational component modeled in hardware; control logic coupled to the internal bus system for controlling the delivery of data between the reconfigurable hardware logic and the computing system; and shared memory for holding a first information of the software model and a second information of the hardware model; wherein the system is configured to detect a clock edge in the software model and to evaluate data with the hardware model in response to the clock edge detection in the software model and in synchronization with a hardware-generated clock; wherein the system is configured to selectively switch between the software model and the hardware model including at least the portion of the user design cycle-by-cycle; wherein the user design includes at least one timing insensitive glitch-free (TIGF) logic device updated by a global trigger signal, wherein the global trigger signal allows each of the at least one TIGF logic devices to keep its state to reach a steady-state during an evaluation period and update its state to store a new input value during a shorter trigger period after each of the at least one TIGF logic devices reach the steady-state, wherein the evaluation period is a time period, wherein the shorter trigger period is a shorter time period than the evaluation period and occurs immediately after and consecutive to the evaluation period, wherein the new input value is propagated to each of the at least one TIGF logic devices during the evaluation period, wherein hold time violations are avoided by each of the at least one TIGF logic devices pre-storing the new input value until updated by the global trigger signal.