Patent ID: 6525612
Filing Date: 2003-02-25
Classification: H03L,Y10S

Abstract:
A mode control circuit for mode controlling a phase-locked loop (PLL) circuit having a high-speed mode in which a high-speed lockup operation is performed and a normal mode in which a normal PLL operation is performed, wherein the PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency,wherein the mode control circuit receives the first and the second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained, and wherein the mode control circuit stops the phase comparison of the first and second pulse signals in response to the mode switch signal representing the normal mode.