Patent ID: 6678952
Filing Date: 2004-01-20
Classification: H01L,H05K,Y10T

Abstract:
A method of forming a microelectronic element, comprising:a) providing a dielectric layer with a top side, a bottom side, a top metal layer on the top side, and a bottom metal layer on the bottom side; b) forming first apertures in the top metal layer and forming vias in the dielectric layer aligned with the first apertures; c) applying a first resist to the top metal layer, applying a second resist to the bottom metal layer and patterning the first resist and second resist in the same step to form first openings in the first resist and second openings in the second resist, d) the first openings leaving uncovered portions of the top metal layer surrounding the vias, and the second openings being aligned with the first openings; e) forming top conductive features from portions of the top metal layer aligned with said first openings and bottom conductive features on portions of the bottom metal layer aligned with said second openings; and f) electrically interconnecting the top conductive features and the bottom conductive features through the vias by depositing electrically conductive material in the vias without seeding the vias.