Patent ID: 6243311
Filing Date: 2001-06-05
Classification: G11C,H01L

Abstract:
A method of reducing differential electrical noise in an integrated circuit memory device comprising:providing an integrated circuit memory device having a plurality of at least four arrays of a plurality of memory cells, each array of memory cells being substantially equally spaced from an adjacent array of memory cells, each array of memory cells including a plurality of memory cells and at least four pairs of digitlines, each pair of digitlines including a first digitline and a second digitline, the first digitline and the second digitline being substantially vertically aligned in an upper conductive level and a lower conductive level of the memory device, the first digitline and second digitline of each pair of digitlines each connected to an equal number of the memory cells in each array of the plurality of memory cells; andelectrically balancing the first digitline and the second digitline of each digitline pair of the at least four pairs of digitlines to balance the electrical noise therebetween by twisting the first digitline and the second digitline of a pair of digitlines of the at least four pairs of digitlines between arrays of the at least four arrays of memory cells in a twist region located between each array of the plurality of at least four arrays of memory cells, the first pair and the third pair of digitlines of the at least four pairs of digitlines twisted in the twist region located between the first array of memory cells and the second array of memory cells and twisted in the twist region located between the third array of memory cells and the fourth array of memory cells while the second pair of digitlines and the fourth pair of the at least four pairs of digitlines are twisted in the twist region located between the second array of memory cells and the third array of memory cells.