Patent ID: 6034911
Filing Date: 2000-03-07
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory blocks each including a plurality of memory cells arranged in a matrix, a plurality of word lines each extending along a corresponding row of said memory cells, a plurality of bit lines each extending along a corresponding column of said memory cells, a row address decoder for controlling the connection of said memory cells in a row with respective said bit lines in accordance with a row address, a sense amp control circuit and a sense amplifier assembly;a common data line connected to said plurality of memory blocks transferring data between said memory blocks and outside the memory device;a column address decoder selectively coupling one of said bit lines with said data lines in accordance with a column address;wherein said column address decoder supplies a common column address to each of said memory blocks; anda block selecting section selectively activating each of said row address decoders and sense amp control circuits in accordance with a block address;wherein only one sense amplifier assembly, corresponding to a respective memory block, is activated at any one time.