Patent ID: 6094389
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A semiconductor memory apparatus having a refresh test circuit, comprising:a data input/output buffer for temporarily storing and outputting data stored in a memory cell;a write control unit for receiving a write enable signal and controlling the data input/output buffer;a row address buffer and a column address buffer for receiving address signals and temporarily storing therein;a refresh address counter for refreshing the memory cell;a refresh control unit for controlling the refresh address counter;a row block decoder and a plurality of row decoders for receiving a row address from the row address buffer and generating a real address for accessing the memory cell;a column decoder for receiving the column address signal from the column address buffer and generating a real address for accessing the memory cell;a plurality of sense amplifier arrays for amplifying the data stored in a selected memory cell or storing an externally amplified data in the memory cell;a plurality of memory cell arrays having memory cells selected by the plurality of row decoders and the column decoder;a refresh test control unit for controlling the row block decoder and the refresh control unit; anda control unit for receiving a row address strobe signal, a column address strobe signal and a write enable signal so as to control respective units.