Patent ID: 6829192
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A semiconductor memory comprising:a first memory cell and a second memory cell; complementary bit lines connected to said first and second memory cells, respectively; a sense amplifier connected to said complementary bit lines; a refresh control circuit for cyclically outputting a refresh control signal for refreshing said first and second memory cells; and an operation control circuit for performing a read operation, a write operation, and a refresh operation on said first and second memory cells, wherein said operation control circuit operates either of said first and second memory cells selected in accordance with an address signal, during normal operation mode in which said read operation and said write operation are performed, and performs, at the start of low power consumption mode, a refresh operation in which data retained in said first memory cell is amplified by said sense amplifier and written to said first and second memory cells, and subsequently refreshes said first and second memory cells simultaneously in response to said refresh control signal.