Patent ID: 6376359
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of manufacturing metallic interconnects comprising the steps of:providing a semiconductor substrate; forming a first silicon-rich oxide layer over the semiconductor substrate; forming a first metallic layer on the first silicon-rich oxide layer; forming a second silicon-rich oxide layer conformal to and directly on the first metallic layer, wherein the first metallic layer is isolated and protected by the first and second silicon-rich oxide layers; forming a glass layer on the second silicon-rich oxide layer, wherein the glass layer fills up gaps of the second silicon-rich oxide layer; forming a dielectric layer over the second silicon-rich oxide layer and on the glass layer; forming a third silicon-rich oxide layer on the dielectric layer; and forming a plug penetrating through the second silicon-rich oxide layer, the dielectric layer and the third silicon-rich oxide layer to couple to the first metallic layer.