Patent ID: 7870217
Filing Date: 2011-01-11
Classification: H04L

Abstract:
1. A programmable TCP/IP chip used for processing Internet Protocol packets in TCP/IP sessions in accordance with TCP/IP session information and configured to be coupled to one or more host processors of a host system, said one or more host processors for processing data transferred using said internet Protocol Packets, said host system comprising host buffers coupled to said one or more host processors, said programmable TCP/IP chip comprising: a. a remote direct memory access (RDMA) capability for performing RDMA data transfers; b. at least one network interface configured to send and/or receive said Internet Protocol packets from or to said TCP/IP chip; c. a memory on said TCP/IP chip for storing said TCP/IP session information or said Internet Protocol packets; d. a memory controller for controlling access to said memory for storing or retrieving said TCP/IP session information or said Internet Protocol packets; e. a TCP checksum generator for checksum generation or verification or a combination thereof; f. a TCP segmentation controller for performing TCP segmentation; g. a TCP/IP header processing engine for processing or generating TCP/IP headers or fields; h. a RDMA header processing engine for generating or processing RDMA headers or fields; i. a transmit engine or a receive engine or a combination thereof for retrieving data from said host buffers or performing direct data placement or zero copy in said host buffers without substantial intervention by said one or more host processors; j. an execution resource to perform TCP/IP operations on said Internet Protocol packets; k. an execution resource to perform RDMA operations on said Internet Protocol packets that require RDMA processing; and l. a host interface controller to couple said TCP/IP chip to said one or more host processors.