Patent ID: 7463530
Filing Date: 2008-12-09
Classification: G11C,H01L

Abstract:
1. An operating method of a memory cell, the operating method comprising: providing a memory cell, the memory cell comprising: performing a first operation, supplying a negative bias to the gate and setting the source/drain regions to be floating, grounded, or 0V, injecting electrons from the gate of the memory cell into the charge storage layer through the multi-layer tunneling dielectric structure by −FN tunneling so as to increase the threshold voltage of the memory cell; and performing a second operation, supplying a positive bias to the gate and setting the source/drain regions to be floating, grounded, or 0V, injecting holes from the gate of the memory cell to the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so as to decrease the threshold voltage of the memory cell.