Patent ID: 8972686
Filing Date: 2015-03-03
Classification: G06F,G11C

Abstract:
1. An integrated circuit comprising: a processing unit configured to access a static random access memory and a flash memory and to output controller output signals to access one of the static random access memory and the flash memory; a memory controller configured to convert the controller output signals into memory input signals corresponding to the one of the static random access memory and the flash memory, the memory input signals including a write enable signal, a write data signal, a first chip select signal and a second chip select signal; a first terminal configured to be connected to the static random access memory and the flash memory via a first common bus, the write enable signal being supplied from the first terminal to the one of the static random access memory and the flash memory via the first common bus; a second terminal configured to be connected to the static random access memory and the flash memory via a second common bus, the write data signal being supplied from the second terminal to the one of the static random access memory and the flash memory via the second common bus; a third terminal configured to be connected only to the flash memory via a first dedicated one, the first chip select signal being supplied from the third terminal to the flash memory via the first dedicated line, and a fourth terminal configured to be connected only to the static random access memory via a second dedicated line, the second chip select signal being supplied from the fourth terminal to the static random access memory via the second dedicated line, wherein the memory controller includes a conversion control unit configured to determine whether to output the memory input signal to the one of the static random access memory and the flash memory or temporarily keep the memory input signal in a period during which another one of the static random access memory and the flash memory is accessed.