Patent ID: 7551489
Filing Date: 2009-06-23
Classification: G11C

Abstract:
1. A memory circuit comprising: a plurality of memory cell transistors having programmable threshold voltages, each of the plurality of memory cell transistors having a gate node and a drain node; a wordline coupled to gate nodes of the plurality of memory cell transistors; a circuit to apply a sequence of voltages on the wordline during a read cycle of the plurality of memory cells, wherein voltages in the sequence of voltages are between the programmable threshold voltages; a plurality of sense amplifiers, wherein each sense amplifier is coupled to a corresponding drain node of the plurality of memory cell transistors; a current mirror circuit coupled to each of the plurality of sense amplifiers to provide a substantially constant current to be compared against currents flowing in the drain nodes of the memory cell transistors during the read cycle; a plurality of latches coupled to store data when output nodes of the plurality of sense amplifiers change state; and a control circuit to control the application of the sequence of voltages on the wordline, and to provide data to the plurality of latches.