Patent ID: 8120398
Filing Date: 2012-02-21
Classification: H03L

Abstract:
1. A delay locked loop circuit comprising: a first delay portion configured to delay a received external clock signal for a fine delay time and then output a first internal clock signal; and a second delay portion configured to delay a second clock signal for a coarse delay time and then output a second internal clock signal; and a phase detection and control unit configured to detect a difference between the phases of the external clock signal and a delayed corrected clock signal (CCLK D), and to control the fine delay time and the coarse delay time, wherein the first delay portion includes first delay cells and the second delay portion includes second delay cells, and the first delay portion and second delay portion are sequentially arranged, and the second clock signal is generated using the first internal clock signal, wherein a type of a delay cell of the first delay portion is different from a type of a delay cell of the second delay portion, wherein the type of delay cell is defined by an amount of delay time produced by the delay cell, and wherein the first delay portion comprises: a first delay circuit including n delay cells connected in series; and a phase mixer configured to output the first internal clock signal, in response to information regarding the detected phase difference and an output of the phase detection and control unit.