Patent ID: 6070234
Filing Date: 2000-05-30
Classification: G06F,Y02D

Abstract:
A cache memory comprising:a data array for holding a plurality of pieces of data corresponding to a plurality of pieces of data held in another memory;an address array for holding a plurality of pieces of address information associated with addresses of said another memory for said plurality of pieces of data held in said data array;a first activating circuit, responsive to a read request which requests readout of data from said another memory, for activating said address array to read a piece of address information therefrom associated with a read address specified by said read request;a hit check circuit for performing hit check on said read address based on said piece of address information read from said address array;a second activating circuit for activating said data array to read data associated with said read address,wherein said data array includes a plurality of data holding ways,wherein said address array includes a plurality of address information holding ways each provided in correspondence to one of said plurality of data holding ways,wherein said hit check circuit executes the hit check on respective ones of said plurality of address information holding ways with respect to said memory read address,wherein said second activating circuit activates said plurality of data holding ways before completion of the hit check; anda circuit for instructing a data holding way corresponding to an address information holding way to stop a data read operation under execution, when said hit check circuit determines that said address information holding way has a mishit.