Patent ID: 6649461
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method to reduce reverse narrow width effect in CMOS devices, comprising the steps of:providing a substrate, said substrate having been provided with a layer of pad oxide over the surface of the substrate; creating a pattern of ion implant barrier material over the surface of said layer of pad oxide, said pattern of ion implant material comprising a first pattern being aligned with a pattern of NMOS devices being created over the surface of said substrate and a second pattern being aligned with a pattern of PMOS devices being created over the surface of said substrate; creating an p-well mask over the surface of said substrate, exposing said first pattern of implant barrier material; performing a first angle implant into the surface of said substrate; removing said p-well mask from the surface of said substrate; creating an n-well mask over the surface of said substrate, exposing said second pattern of implant barrier material; performing a second angle implant into the surface of said substrate; removing said n-well mask from the surface of said substrate; creating a pattern of Shallow Trench Isolation (STI) regions into the surface of said substrate, said pattern of STI regions being interspersed with said pattern of ion implant barrier material; removing said pattern of ion implant barrier material from over the surface of said substrate, thereby reducing a height of said created STI regions down to the surface of said layer of pad oxide; and completing processing of said CMOS devices.