Patent ID: 6074924
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method of forming integrated circuitry comprising the following steps:providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor;masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant providing a p-type first impurity concentration at a first depth within the NMOS substrate area; andin a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant providing an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first depth being greater than the second depth.