Patent ID: 6365521
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method of passivating an integrated circuit comprising:providing an integrated circuit having a top side having a portion including a bond pad having opposing side portions and a top surface defining a first area that are exposed; conformally depositing a first dielectric of a material that is substantially impermeable to moisture over said portion of said top side of said integrated circuit; conformally depositing a second dielectric over said first dielectric: to a thickness substantially equivalent to the step height of the bond pad less the thickness of said first dielectric; planarizing said top side of said integrated circuit to expose a top side portion of said first dielectric over said first area; depositing a third dielectric of a materiel that is substantially impermeable to moisture over said first area; and exposing a second area of said top side of said bond pad.