Patent ID: 8923056
Filing Date: 2014-12-30
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a memory cell block including a plurality of memory cells; a plurality of page buffer groups including a plurality of page buffers coupled to bit lines of the memory cell block; a pass/fail check circuit coupled to the plurality of page buffers and configured to perform a pass/fail check operation of comparing a total amount of current varying according to verify data sensed from the memory cells and stored in the page buffers with an amount of reference current corresponding to the number of allowed bits; and a control circuit configured to control the pass/fail check circuit by stopping, when a fail signal is generated during the pass/fail check operation currently being performed on a page buffer group among the plurality of page buffer groups, the pass/fail check operation on the remaining page buffer groups during a period that the pass/fail check operation is to be sequentially performed on the plurality of page buffers.