Patent ID: 9059307
Filing Date: 2015-06-16
Classification: G06F,H01L

Abstract:
1. A method for implementing an enhanced transistor topology enabling enhanced current capability comprising: forming a fin field effect transistor (FinFET); said FinFET on a semiconductor substrate; forming said FinFET having in-line source and drain regions without a dog-bone shape and forming a gate region on a gate dielectric with first and second gate extensions extending past opposing sides of said in-line source and drain regions; forming a first field effect transistor (FET) in said semiconductor substrate beside and under said FinFET and forming a second FET in said semiconductor substrate beside and under said FinFET; forming each of said first FET and said second FET having buried source and drain diffusions formed in said semiconductor substrate on the opposing sides of said in-line source and drain regions with angled implants used to dope said buried source and drain diffusions and FinFET; and said first and second gate extensions of said FinFET providing a gate of said first FET and said second FET; and forming an electrical bar contact to a common source of said FinFET, said first FET and said second FET.