Patent ID: 7906819
Filing Date: 2011-03-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: first transistors, second transistors, and third transistors lower in threshold voltage than at least the second transistors; each of the first transistors including first source/drain diffusion layers of a second conductivity type and a first doped channel layer of a first conductivity type arranged therebetween and formed in a semiconductor substrate, first source/drain diffusion layers, first pocket regions of the first conductivity type formed between the first doped channel layer and the first source/drain diffusion layers, a first gate insulating layer formed on the first doped channel layer, a first gate electrode formed on the first gate insulating layer; each of the second transistors including second source/drain diffusion layers of the second conductivity type and a second doped channel layer of the first conductivity type arranged therebetween and formed in the semiconductor substrate, second pocket regions of the first conductivity type formed between the second doped channel layer and the second source/drain diffusion layers, a second gate insulating layer formed on the second doped channel layer, and a second gate electrode formed on the second gate insulating layer; each of the third transistors including third source/drain diffusion layers of the second conductivity type and a third doped channel layer of the first conductivity type arranged therebetween and formed in the semiconductor substrate, third pocket regions of the first conductivity type formed between the third doped channel layer and the third source/drain diffusion layers, a third gate insulating formed on the third doped channel layer, and a third gate electrode formed on the third gate insulating layer; a peak concentration of the first conductivity type impurity under a center portion of the first gate electrode being lower than a peak concentration of the first conductivity type impurity under a center portion of the second gate electrode and not higher than a peak concentration of the first conductivity type impurity under a center portion of the third gate electrode; and a peak concentration of the first conductivity type impurity under an edge portion of the first gate electrode being higher than a peak concentration of the first conductivity type impurity under an edge portion of the second gate electrode and higher than a peak concentration of the first conductivity type impurity under an edge portion of the third gate electrode.