Patent ID: 7626879
Filing Date: 2009-12-01
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells including floating bodies in an electrically floating state, logic data according to the number of carriers accumulated in the floating bodies being stored in the memory cells; a plurality of word lines connected to gates of the memory cells; a plurality of bit lines connected to the memory cells and transmitting data stored in the memory cells; and a plurality of sense amplifiers connected to the bit lines, and applying a first voltage to the bit lines when first logic data is written to the memory cells connected to the bit lines, wherein the sense amplifiers apply a second voltage to the memory cells having stored therein the first logic data during a refresh operation in which at least second logic data stored in the memory cells is recovered, the second logic data is opposite in logic to the first logic data, and the second voltage is lower in absolute value than the first voltage and equal to or higher in absolute value than a potential of sources of the memory cells.