Patent ID: 7737040
Filing Date: 2010-06-15
Classification: G03F

Abstract:
1. A method of reducing critical dimension bias during fabrication of a semiconductor structure using a reticle, comprising: (a) providing a reticle comprising at least one hard mask layer having anti-reflective properties, which hard mask layer having said anti-reflective properties overlies a patterned radiation-blocking layer, which overlies a radiation transmitting base substrate layer; and (b) exposing an imaging layer on a surface of said semiconductor structure to radiation passed through said reticle, where said radiation first passes through said radiation transmitting base substrate layer, where a portion of said radiation passes through openings in said patterned radiation-blocking layer, where said radiation passing through said openings strikes a surface of a semiconductor structure and is reflected back toward said reticle; and, (c) employing said hard mask layer having anti-reflective properties present on a reticle surface facing said semiconductor structure to reduce reflection from said reticle back toward said semiconductor structure, whereby critical dimension bias in said semiconductor structure is reduced.