Patent ID: 9207937
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. A data processing apparatus comprising: processing circuitry configured to perform processing operations; and an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said processing operations; wherein: said program instructions include a bitfield manipulation instruction identifying at least a first source data value comprising at least one first source data element each having N bits <N−1:0>, a second source data value comprising at least one second source data element each having N bits <N−1:0>, and a control value; said control value includes information for indicating a bitfield width W, a source bit position A and a result bit position B, where 1≦W≦N, 0≦A≦N−W and 0≦B≦N−W; and said instruction decoder is responsive to said bitfield manipulation instruction to generate control signals for controlling said processing circuitry to generate a result data value comprising at least one result data element, each result data element corresponding to a corresponding first source data element and a corresponding second source data element, each result data element having N bits <N−1:0> comprising: (a) bits <B+W−1:B> having bit values corresponding to bits <A+W−1:A> of said corresponding first source data element; and (b) if B+W<N, bits <N−1:B+W> having bit values corresponding to a prefix value selected, in dependence on said control value, as one of (i) a first prefix value comprising bits each having a zero value, (ii) a second prefix value having the bit values of bits <N−1:B+W> of said corresponding second source data element, and (iii) a third prefix value having bit values corresponding to a sign extension of bits <A+W−1:A> of said corresponding first source data element;