Patent ID: 7894251
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory array including: a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each magnetically storing a data signal; a plurality of digit lines provided in correspondence with the rows; and a plurality of bit lines provided in correspondence with the columns; a row decoder for selecting any digit line in the digit lines in accordance with a row address signal; a column decoder for selecting any bit line in the bit lines in accordance with a column address signal; a digit line driver for making magnetization current flow to the digit line selected by the row decoder to activate memory cells corresponding to the digit line; and a bit line driver for making write current flow in a direction according to logic of a data signal to the bit line selected by the column decoder to write the data signal to the activated memory cell, wherein one ends of the digit lines are commonly coupled to a first node that receives a power supply voltage, and wherein the digit line driver includes: a first transistor which is provided in correspondence with a digit line, coupled between the other end of the corresponding digit line and a second node, and made conductive when the corresponding digit line is selected by the row decoder; a first constant current element coupled between the second node and a line of a reference voltage, and making first constant current flow; and a first precharge circuit for charging the second node to first voltage before the first transistor is made conductive.