Patent ID: 6441665
Filing Date: 2002-08-27
Classification: G06F,H03K

Abstract:
A semiconductor integrated circuit, comprising:a plurality of input terminals to which input data with a plurality of bits are provided in parallel with uniform timing; an input clock terminal to which an input clock signal indicating timing of the input data is provided; a plurality of input data holding circuits, each connected to respective ones of said plurality of input terminals, that hold the input data provided to said input terminals based on timing of a rise or a fall of an internal input clock signal; an input clock distributor that distributes the input clock signal provided to said input clock terminal; and a plurality of adjustable input clock suppliers, each provided between said input clock distributor and respective ones of said input data holding circuits, that generate the internal input clock signals with uniform timing in synchronization with the input data to be provided to said input data holding circuits, by circuit elements that are selectively connectable and disconnectable to correct differences in delay time of said input clock signal occurring in different distribution routes at said input clock distributor.