Patent ID: 6432771
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of manufacturing DRAM cells at a memory side of a semiconductor substrate and logic circuits at a logic side of the substrate, each DRAM cell including a MOS control transistor and a capacitor, and the logic circuit including logic transistors, the method including the steps of:a) forming first openings in a first insulating layer to partially expose source/drain regions of the control transistors and the logic transistors, and filling the first openings with a first conductive material, thereby forming a plurality of contacts of the first conductive material that contact the source/drain regions of the control transistors and the logic transistors, the plurality of contacts including a first subset of contacts that contact a first subset of the source/drain regions of the control transistors, a second subset of contacts that contact a second subset of the source/drain regions of the control transistors, and a third subset of contacts that contact the source/drain regions of the logic transistors; b) depositing a second insulating layer on the contacts that contact the source/drain regions of the control transistors and the logic transistors, forming in the second insulating layer, on the memory side, second openings, to expose the first subset of contacts, successively depositing a second conductive material, then a third insulating layer, defining in the third insulating layer and the second conductive material bit line structures coupled to the first subset of the contacts, and forming lateral spacers on sides of the bit line structures; c) depositing a fourth insulating layer on the second insulating layer above the second and third subsets of contacts; d) forming in the fourth insulating layer third openings, to expose the second subset of contacts; e) depositing and etching a third conductive material, to cover walls and a bottom of the third openings, forming a first electrode of the capacitor; f) conformally depositing a dielectric material forming in insulator of the capacitor; g) depositing a fourth conductive material forming a second electrode of the capacitor; h) depositing another dielectric material on the fourth insulating layer above the logic transistor; and i) forming, on the logic side, fourth openings filled with a conductive material in contact with the third subset of contacts.