Patent ID: 6542428
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A semiconductor memory device for reading and writing storage data in accordance with an address signal, comprising:a plurality of memory cell blocks arranged in a matrix of a first number of columns and a second number of rows, each of said memory cell blocks including a plurality of memory cells arranged in a matrix of memory cell rows and memory cell columns, bit line pairs arranged corresponding to said memory cell columns, respectively, and at least one first data line pair for transmitting read data from one of said memory cells selected according to said address signal; a plurality of read column select lines for instructing selection of at least one of said memory cell columns; a column select circuit for selectively activating at least one of said read column select lines in accordance with said address signal; and a plurality of read data transmitting circuits, provided corresponding to said memory cell blocks, respectively, for transmitting said read data sent from the selected memory cell column onto said first data line pair, each of said read data transmitting circuits including a plurality of first gate circuits provided correspondingly to said memory cell columns, respectively, and each being activated by the corresponding one among said read column select lines, each of said first gate circuits having a first read gate switch to be selectively activated by the corresponding read column select line in accordance with the potential level on one line of said paired bit lines, and a second read gate switch to be selectively activated by the corresponding read column select line in accordance with the potential level on the other line of said paired bit lines.