Patent ID: 6180469
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising sequentially:forming a structure comprising:a silicon-containing substrate;source/drain regions in the substrate with a channel region therebetween;a gate dielectric layer on the substrate over the channel region; a silicon-containing gate electrode, having an upper surface and side surfaces, on the gate dielectric layer; anda dielectric sidewall spacer formed directly on each side surface of the silicon-containing gate electrode, leaving a portion of each source/drain region exposed;selectively depositing a metal layer on the exposed portions of the source/drain regions and directly on the upper surface of the silicon-containing gate electrode with substantially no metal depositing on the dielectric sidewall spacers;forming a barrier layer within and dividing the metal layer into a lower metal portion below and an upper metal portion above the barrier layer; andheating to react the lower metal portion of each metal layer to form a metal silicide layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode.