Patent ID: 6025227
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method for fabricating a capacitor over bit line, (COB), DRAM device, on a semiconductor substrate, comprising the steps of:forming transfer gate structures, comprised of polycide gate structures, encapsulated with silicon nitride, on gate insulator layers, with source and drain regions between the polycide gate structures;forming polysilicon contact plugs, on said source and drain regions, between said polycide gate structures;depositing a first insulator layer;opening a bit line contact hole in said first insulator layer, exposing a first group of polysilicon contact plugs, overlying a first group of source and drain regions;forming a bit line structure with a first portion of said bit line structure, located in said bit line contact hole, and with a second portion of said bit line structure, represented by a straight bit line shape, located on said first insulator layer;forming metal spacers on the sides of said second portion of said bit line structure;depositing a second insulator layer on said straight bit line shape;opening a storage node contact hole in said second insulator layer, in said straight bit line shape, and in said first insulator layer, exposing a second group of polysilicon contact plugs, overlying a second group of source and drain regions, with said storage node contact hole having a wider diameter, in said straight bit line shape, than in said second insulator layer, or in said first insulator layer;forming silicon nitride spacers on sides of said storage node contact hole, with thicker silicon nitride spacers in the wider diameter opening in said straight bit line shape;forming storage node structures, overlying said second insulator layer, completely filling said storage node contact hole, and contacting the top surface of said second group of polysilicon contact plugs;forming a capacitor dielectric layer on said storage node structure; andforming an upper electrode structure.