Patent ID: 6501672
Filing Date: 2002-12-31
Classification: G11C,H01L

Abstract:
A dynamic RAM, comprising:a plurality of dynamic memory cells each comprising a MOSFET and a capacitor, said MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor; a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells; a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells and placed so as to extend in directions opposite to one another with one ends thereof as the centers; and a sense amplifier array which is placed on the one-end side of said complementary bit line pairs and respectively amplifies differences in voltage between said complementary bit lines; and wherein common electrodes provided, so as to be opposed to the storage nodes of the capacitors of said plurality of dynamic memory cells, on both sides of said sense amplifier array are connected to one another by wiring means using the same.