Patent ID: 8136013
Filing Date: 2012-03-13
Classification: H03M

Abstract:
1. An apparatus comprising logic, the apparatus configured to: determine, based on an error location polynomial, an error location syndrome corresponding to an actual location of a burst error in a data block; determine a first error pattern syndrome of the burst error based on an error pattern polynomial; select, based on the first error pattern syndrome, a burst error pattern of length that is less than or equal to M bits, and having no more than Y consecutive zeros within the burst error, where M is greater than the order of the error location polynomial, including being configured to rotate the first error pattern syndrome until a correctable burst error pattern is found; determine a second error pattern syndrome based on the selected burst error pattern and the error location polynomial; and determine an actual location of the burst error in the data block based on the error location syndrome and the second error pattern syndrome.