Patent ID: 8386550
Filing Date: 2013-02-26
Classification: H03H

Abstract:
1. A programmable logic device configured as hybrid finite impulse response (FIR) filter circuitry; wherein: said programmable logic device has a plurality of specialized processing blocks each of which includes a plurality of multipliers and a single adder for simultaneously adding outputs of said multipliers; and said hybrid FIR filter circuitry comprises: a first number of said specialized processing blocks each of which is configured as a respective Direct Form FIR filter circuit in which each respective multiplier in said plurality of multipliers multiplies a respective sample by a respective coefficient and outputs of said respective multipliers are added simultaneously by said single adder to generate a Direct Form FIR output, said hybrid FIR filter circuitry having a second number of taps, each said Direct Form FIR filter circuit comprising a third number of taps, and said second number being a product of said first number and said third number; an adder chain comprising a plurality of additional adders, separate from any adder in said first number of said specialized processing blocks that adds said outputs of said respective multipliers, each of said additional adders having, as one input, one output of one of said respective Direct Form FIR filter circuits, and each of said additional adders other than a first of said additional adders having as one input an output of another one of said additional adders, said adder chain further comprising a respective output delay between (a) each said output of another one of said additional adders, that is an input to one of said additional adders other than a first one of said additional adders, and (b) said one of said additional adders other than a first one of said additional adders, and an input sample chain comprising a number of registers equal to said third number; wherein: each said register provides a sample substantially simultaneously to a corresponding input of each said Direct Form FIR filter circuit, said input sample chain shifts once at every clock cycle, each Direct Form FIR filter circuit generates an output at every said clock cycle, and each said respective output delay has a delay period of a number of said clock cycles equal to said third number.