Patent ID: 7610628
Filing Date: 2009-10-27
Classification: G06F

Abstract:
1. An apparatus for calculating a representation of a result operand of a non-linear logical operation between at least a first operand and a second operand, the first operand being represented by a first auxiliary operand, and a second auxiliary operand, the first and second auxiliary operands resulting in the first operand, when combined using a linear combination, the second operand being represented by a third auxiliary operand and a fourth auxiliary operand, the third and fourth auxiliary operands resulting in the second operand when combined using a linear combination, comprising: a first logic gate implemented on a transistor level using a plurality of transistors, the first logic gate being configured for calculating a fifth auxiliary operand based on at least two auxiliary operands, the at least two auxiliary operands including one of the first and second auxiliary operands and one of the third and fourth auxiliary operands; and a second logic gate implemented on a transistor level using a plurality of transistors, the second logic gate being configured for calculating a sixth auxiliary operand based on at least the first to fourth auxiliary operands, wherein the first and second logic gates are designed such that the fifth and sixth auxiliary operands when linearly combined, result in the result operand, and wherein the first and second logic gates are designed such that an average energy consumption of the first logic gate or an average energy consumption of the second logic gate is substantially equal to a plurality of combinations of auxiliary operands at the beginning of a first operation cycle and auxiliary operands at the beginning of a second operation cycle, the average energy being derivable from a plurality of different orders of occurrences of the first to fourth auxiliary operands.