Patent ID: 6163047
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method of fabricating a capacitor over bitline, (COB), structure, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, comprising the steps of:forming isolation regions in a first region of said semiconductor substrate;forming a gate insulator layer, on a second region of said semiconductor substrate, not occupied by said isolation regions;forming word line structures, overlying portions of said isolation regions, and overlying portions of said gate insulator layer;forming source/drain regions, in a region of said semiconductor substrate, not covered by said word line structures, or by said isolation regions;forming insulator shapes on said isolation regions;forming lower polysilicon plug structures, between said insulator shapes, and between word line structures, overlying, and contacting said source/drain regions;forming bitline structures, on said insulator shapes;forming a planarized insulator layer on underlying, said bitline structures, and on underlying, lower polysilicon plug structures, completely filling spaces between said bitline structures;forming self-aligned contact, (SAC), openings, in said planarized insulator layer, and through said bitline structures, exposing the sidewall of said bitline structures, and exposing the top surface of said lower polysilicon plug structures;forming insulator spacers on the sides of said planarized insulator layer, and on the sides of said bitline structures, exposed in said SAC openings:forming upper polysilicon plug structures, in said SAC openings, overlying and contacting the top surface of said lower polysilicon plug structures; andforming a capacitor structure, overlying and contacting, said upper polysilicon plug structure.