Patent ID: 6177922
Filing Date: 2001-01-23
Classification: G09G,H04N

Abstract:
A format converter for receiving successive input frames of a digital video input signal characterized by a first viewable display resolution, pixel rate and line rate, and in response generating successive output frames of a digital video output signal for viewing on a display characterized by a second viewable display resolution, pixel rate and line rate, said format converter comprising:programming interface means for receiving operating mode information indicative of said first and second viewable resolutions, pixel rates and line rates;memory means for storing said digital video input signal;display processor means for retrieving said digital video input signal from said memory means, performing at least one of de-interlacing, filtering and scaling of said digital video input signal, and in response generating said digital video output signal; anddisplay timing controller means including a free-running display clock, aid display timing controller means deriving synchronization and control information from said digital video input signal based on said operating mode information received by said programming interface means, and in response controlling operation of said display processor means to generate said successive output frames of said digital video output signal synchronous with said free-running display clock and frame locked to respective ones of said successive nput frames for display at said second viewable display resolution, pixel rate and line rate which is a fractional multiple of said first viewable pixel rate.