Patent ID: 6563335
Filing Date: 2003-05-13
Classification: G01R

Abstract:
A semiconductor device including a test cell for performing delay evaluation of a signal input from a first I/O circuit and output to a second I/O circuit, the semiconductor device comprising:first to N-th delay paths for respectively delaying a signal input from the first I/O circuit by first to N-th delay values different from one another and for outputting the delayed signal to the second I/O circuit; a delay path switching circuit that selects one of the first to N-th delay paths through which a signal input from the first I/O circuit is output to the second I/O circuit, wherein an i-th delay path (â€œiâ€  being a natural number equal to or greater that 1 and equal to or smaller that N) includes a delay element which is disposed in such a manner that an input section and an output section of the delay element are positioned close to each other.