Patent ID: 8687681
Filing Date: 2014-04-01
Classification: H04B,H04L

Abstract:
1. A receiver, for receiving a plurality of test signal groups to test the receiver, each of the test signal groups having multi-bit of data, the receiver comprising: a clock/data recovery (CDR) circuit, for receiving the test signal groups inputted in series and following a transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver; a serial-to-parallel converter, coupled to the CDR circuit to receive the test signal groups directly outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data; and a test module, coupled to the serial-to-parallel converter to receive the test bytes, and coupled to the CDR circuit to receive the clock signal, and operating with the clock signal to compare two adjacent test bytes of the test bytes to determine whether the two adjacent test bytes are completely the same for testing the receiver; wherein a bit number of each of the test bytes equals to a bit number of each of the test signal groups.