Patent ID: 6154403
Filing Date: 2000-11-28
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells arranged at intersections of a plurality of bitlines and a plurality of word lines;a sense amplifier and latch circuit that is selectively connected to said plurality of bitlines and senses the bitline voltage corresponding to a data in reading the data in said plurality of memory cells and outputs the voltage corresponding to the writing data onto said plurality of selected bitlines in writing the data into said plurality of memory cells;a precharge circuit that is selectively connected to said plurality of bitlines and outputs a voltage for preventing the change of the data in memory cells onto the bitlines unconnected to the sense amplifier and latch circuit in writing the data into a memory cell; anda control circuit for disconnecting said sense amplifier and latch circuit from all of said plurality of bitlines, connecting said precharge circuit to all of said plurality of bitlines, outputting at least one of a writing voltage and an unwriting voltage onto all of said plurality of bitlines, and simultaneously writing the data into a plurality of memory cells sharing the selected word line.