Patent ID: 8996824
Filing Date: 2015-03-31
Classification: G06F,G11C

Abstract:
1. A method of operating a memory system, the method comprising: a memory controller tracking a time remaining before a scheduled time for initiating a high priority, high latency operation to a first memory rank of the memory system, wherein a plurality of memory ranks are individually accessible by different memory access operations scheduled from a command re-order queue of the memory controller, wherein the scheduled time of the high priority, high latency operation is a future time, and wherein the command re-order queue contains memory access operations targeting the plurality of memory ranks; in response to the time remaining reaching a pre-established early notification time before the schedule time for initiating the high priority, high latency operation: performing the high priority, high latency operation at the first memory rank at the scheduled time; wherein the biasing of the command re-order queue and scheduling of the first memory access operations triggers a faster depletion of first memory access commands remaining within the command re-order queue before the high priority, high latency operation is performed at the first memory rank.