Patent ID: 8975835
Filing Date: 2015-03-10
Classification: G09G,H04N,H05B

Abstract:
1. A backlight dimmer circuit, comprising: a PLL (Phase-Locked Loop) dimming module, which detects a rising edge of a 3-dimentional (3D) synchronous signal in order to generate multiple channels of a 3D mode dimming signal that are in phase with the 3D synchronous signal, the PLL dimming module further determining a duty ratio of a 3D mode according to an analog dimming direct current (DC) duty; a phase delay module, which receives the multiple channels of the 3D mode dimming signal from the PLL dimming module and generates time-divided outputs of the multiple channels of the 3D mode dimming signal in a channel by channel manner according to a delay set value; an external dimming module, which receives an external dimming signal to generate a 2-dimentional (2D) mode dimming signal; and a trigger, which receives the 2D mode dimming signal and the multiple channels of the 3D mode dimming signal that is output in a time-divided and channel by channel manner and determines whether to output the 2D mode dimming signal or the multiple channels of the 3D mode dimming signal that is output in a channel by channel manner according to a 2D/3D conversion signal; wherein the PLL dimming module is an analog PLL, which comprises a phase reference extraction circuit, a voltage controlled oscillator, a phase comparator, and a control circuit, the analog PLL extracting the 3D synchronous signal as a phase reference signal, the voltage controlled oscillator comprising a triangular wave generation circuit, which is compared with an analog dimming level to generate a square wave.