Patent ID: 8928090
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a field effect transistor including a raised source region and a raised drain region and located on a substrate; a gate level dielectric layer comprising a first dielectric material and overlying a gate electrode of said field effect transistor; a contact level dielectric layer comprising a second dielectric material and overlying said gate level dielectric layer; and a contact via structure electrically shorted to one of said raised source region and raised drain region and extending through said contact level dielectric layer and said gate level dielectric layer as a single contiguous structure, wherein a lower portion of said contact via structure embedded within said gate level dielectric layer is narrower than an upper portion of said contact via structure embedded within said contact level dielectric layer along a horizontal direction parallel to a direction of a channel of said field effect transistor, said lower portion of said contact via structure has a lateral width that decreases with an increase in a vertical distance from a horizontal plane including an interface between said substrate and said gate level dielectric layer, said lateral width being measured between sidewalls of said lower portion of said contact via structure along a horizontal direction that is parallel to said horizontal plane.