Patent ID: 8125842
Filing Date: 2012-02-28
Classification: G11C

Abstract:
1. A memory circuit, comprising: a plurality of memory cells; a plurality of bit lines and row lines connected to the memory cells for accessing selected ones of the memory cells; a programmable voltage source adapted for connection to at least one of the bit lines and operative to charge the at least one bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the at least one bit line; a control circuit coupled to the at least one bit line and operative to oppose discharge of the at least one bit line during at least a portion of a given memory read cycle; and a tracking circuit connected to the control circuit and operative to control a delay in activation of the control circuit and a duration of time the control circuit is active as a function of at least one parameter affecting a signal development time of a data signal on the at least one bit line, the data signal being indicative of data stored in the selected one of the memory cells.