Patent ID: 6621753
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A semiconductor device, comprising;a plurality of memory cells, arranged in rows and columns, that need to be refreshed; a plurality of bit lines each coupled to a column of said plurality of memory cells; a plurality of sense amplifiers respectively coupled to said plurality of bit lines, the plurality of sense amplifiers being coupled to a data path for reading out data amplified by the plurality of sense amplifiers; a row selection control circuit for generating both a refresh control signal and a read or write row selection control signal within a single read or write operation cycle responsive to receiving a data read or write control signal; a row selection circuit for selecting a row of the plurality of memory cells in response to the refresh control signal and for selecting a row of the plurality of memory cells in response to the read or write row selection control signal; and a sense amplifier control circuit for activating the plurality of sense amplifiers in response to the refresh control signal and for activating the plurality of sense amplifiers in response to the read or write row selection control signal.