Patent ID: 6715065
Filing Date: 2004-03-30
Classification: G06F

Abstract:
A micro program controller apparatus, comprising:an instruction fetch means for controlling fetch of micro instructions by specifying a start address of a micro program; a read/branch means for controlling reading and branching of micro instructions in each cycle in accordance with the specified start address; and an executing means for executing the read micro instruction wherein said micro instructions includes either (Nâˆ’1)th power of M of fields for specifying the micro instruction branch target address to be read out at following Nth (N&gE;2) cycle from the current read cycle or (Nâˆ’1)th power of M of fields for determining the end of micro program at said following Nth cycle, and a field for controlling execution in the next cycle; said instruction fetch means includes a first register means for storing said start address, and a second register means for storing information used in determining the micro instruction address to be read out in the following 2nd to Nth cycle after starting the micro program and the end of micro program in the following 2nd to Nth cycle after starting the micro program; said read/branch means includes an end judgment means referring to an end judgment field of micro instruction of a preceding cycle for generating an end judgment signal of micro program, an address selector means referring to said end judgment signal for selecting either the starting address of micro program, or the micro instruction address to be read out in the following 2nd to Nth cycle after starting a micro program, or the branch target address at the following Nth cycle of said micro instruction having read out in the preceding cycle, a third register means for storing the selected addresses, a storage means having a first storage part for storing the field specifying the branch target address of said micro instructions in the following Nth cycle and the field for determining the end of micro instruction in the following Nth cycle, and a second storage part for storing a branch condition field of micro instructions and a control field, a reading means for reading the Mth (M&gE;2) micro instruction from one address stored in said third register means into said storage means, a branch judgment means for referring to the branch condition field of the micro instruction read out in the previous cycle and the execution result of the previous cycle to generate a branch judgment signal and a fourth register means for storing control information on the execution in the next cycle; and said execution means includes a means for performing the execution in the next cycle in accordance with said control information.