Patent ID: 6081472
Filing Date: 2000-06-27
Classification: G11C

Abstract:
A cell refresh circuit for a memory device, comprising:a power input circuit that applies a program voltage in a program mode and applies one of a source voltage and pumping voltage based on a reprogram signal in an operation mode;a controller circuit for respectively outputting a read/write enable signal;an address selector circuit that selects one of a first address and a second address and outputting the selected address;clock signal supply circuit that outputs the clock signal to the address selector circuit based on a user mode signal; andtiming circuit that outputs the reprogram signal to the address selector circuit based on the user mode signal and an elapsed prescribed time, wherein the power input circuit comprises,a power selecting controller that outputs one of a program mode signal and a write signal as a power selecting control signal,a power supply unit that outputs the program voltage, the source voltage and the pumping voltage as an output voltage, anda power switching unit that selects the output voltage from the power supply unit based on the power selecting control signal.