Patent ID: 7225300
Filing Date: 2007-05-29
Classification: G06F

Abstract:
1. A multi-processor system comprising: a plurality of snoop tag partitions for storing snoop entries; a plurality of external interconnect buses coupled between a plurality of snoop tag partitions, the plurality of external interconnect buses carrying cache coherency requests that include a snoop address; a plurality of memory controllers coupled to a shared main memory; a plurality of local processors for executing instructions and reading and writing data; a plurality of local caches, coupled to the plurality of local processors, for storing cache entries that contain instructions or data used by the plurality of processors; internal interconnect buses that couple the plurality of snoop tag partitions to the plurality of local caches and to the plurality of external interconnect buses; wherein each snoop tag partition in the plurality of snoop tag partitions contains snoop entries arranged into snoop sets, wherein a snoop index selects one of the snoop sets as a selected snoop set, wherein all snoop entries within a snoop set have a same snoop index but are able to have different snoop tags; wherein each local cache in the plurality of local caches contain cache entries arranged as multi-way cache sets, wherein a cache index selects one of the cache sets as a selected cache set, wherein all cache entries within a cache set have a same cache index but have different cache tags; wherein the snoop address carried over the internal interconnect buses comprises a tag portion for matching with a cache tag, a cache-index portion having the cache index for selecting the selected cache set, and an offset portion of data within a selected cache entry, wherein the cache-index portion further comprises a snoop-index portion having the snoop index for selecting the selected snoop set, a chip-select portion, and an interleave portion; wherein the chip-select portion of the cache-index portion of the snoop address selects a selected group of snoop tag partitions in the plurality of snoop tag partitions; wherein the interleave portion of the cache-index portion of the snoop address selects a selected snoop tag partition in the plurality of snoop tag partitions within the selected group of snoop tag partitions; wherein the selected snoop tag partition responds to the cache coherency request having the snoop address and stores a snoop tag in a snoop entry within the selected snoop set selected by the snoop index; wherein other snoop tag partitions do not respond to the cache coherency request, wherein the selected snoop tag partition is selected by the chip-select portion and the interleave portion of the snoop address which are subsets of the cache index, whereby processing of snoop requests are partitioned across the plurality of snoop tag partitions by the chip-select portion of the snoop address.