Patent ID: 6057704
Filing Date: 2000-05-02
Classification: H03K

Abstract:
A field programmable gate array (FPGA) comprising:a column of configuration memory cells that store configuration data values which are used to configure the FPGA;a plurality of cell access transistors, each having a gate;a plurality of row lines, wherein each row line is coupled to a corresponding one of the configuration memory cells by a corresponding one of the cell access transistors;a row access circuit which provides configuration data values only to a selectable set of the row lines during a write operation;a column select line coupled to the gate of each of the cell access transistors; anda column access circuit for applying a first voltage followed by a second voltage to the column select line during the write operation, wherein both the first voltage and the second voltage are sufficient to turn on the access transistors, and wherein the second voltage turns on the cell access transistors harder than the first voltage.