Patent ID: 6338137
Filing Date: 2002-01-08
Classification: G06F

Abstract:
A data processor operating in instruction cycles including:a data memory having a plurality of address locations, a plurality of data registers, an instruction dispatch/decode unit responsive to a stream of instructions to decode instructions and activate corresponding functional units, said stream of instructions including at least one normal memory access instruction and at least one multiple cycle memory access instruction; a normal memory access unit connected to said data memory, said plurality of data register and said instruction dispatch/decode unit for data transfer between a predetermined address location of said data memory and a predetermined one of said data registers, said normal memory access unit initiating data transfer during an instruction cycle of actuation by said instruction dispatch/decode unit in response to a normal memory access instruction; a multiple cycle memory access unit connected to said data memory, said plurality of data registers and said instruction dispatch/decode unit for data transfer between a predetermined address location of the data memory and a predetermined one of the data registers, the multiple cycle memory access unit delaying a predetermined number of instruction cycles between activation by said instruction dispatch/decode unit in response to a multiple cycle memory access instruction and initial data transfer; wherein the multiple cycle memory access unit performs the data transfers independently and in parallel with the data processor's instruction flow, once the multiple cycle memory access unit has been activated.