Patent ID: 6727741
Filing Date: 2004-04-27
Classification: H03K

Abstract:
A phase-interpolation signal generating device for inputting a first double-level clock signal and a second double-level clock signal and then outputting a third double-level clock signal and a fourth double-level clock signal after processed by the device, phases of the first double-level clock signal and the second double-level clock signal being different and the difference being a constant value, and the difference between the phases of the third and the fourth double-level clock signals being smaller than said constant value; the device comprising five phase-interpolation circuits, each phase-interpolation circuit comprising a first input end and a second input end and an output end respectively, phase of output signal of the output end being between phases of both input signals of the two input ends; wherein said phase-interpolation circuits comprise:a first phase-interpolation circuit having both input ends thereof for receiving the first double-level clock signal; a second phase-interpolation circuit having one input end thereof for receiving the first double-level clock signal and another input end for receiving the second double-level clock signal; a third phase-interpolation circuit having both input ends thereof for receiving the second double-level clock signal; a fourth phase-interpolation circuit having its two input ends separately connected to the output ends of the first and the second phase-interpolation circuits respectively, the output end of the fourth phase-interpolation circuit outputting the third double-level clock signal; and a fifth phase-interpolation circuit having both input ends separately connected to the output ends of the second and the third phase-interpolation circuits respectively, the output end of the fifth phase-interpolation circuit outputting the fourth double-level clock signal; wherein each of the phase-interpolation circuits further comprises: a first inverter having an input end for receiving the double-level clock signal inputted from the first input end of the phase-interpolation circuit; a second inverter having an input end for receiving the double-level clock signal inputted from the second input end of the phase-interpolation circuit, the phase of the double-level clock signal inputted from the first input end thereof leading the double-level clock signal inputted from the second input end thereof when there is a phase difference between the these two double-level clock signals, output end of the second inverter being connected to the output end of the first inverter to form a common output end; a first controlled switch connecting between the first inverter, the second inverter and an electric power source, the first controlled switch being â€œoffâ€  when the double-level clock signal inputted from the first input end is in a first state, and being â€œonâ€  when the double-level clock signal inputted from the first input end is in a second state; and a second controlled switch connecting between the first inverter and the second inverter and a ground point, the second controlled switch being â€œonâ€  when the double-level clock signal inputted from the first input end is in the first state, and being â€œoffâ€  when the double-level clock signal inputted from the first input end is in the second state.