Patent ID: 7903160
Filing Date: 2011-03-08
Classification: H04N

Abstract:
1. A data transfer circuit comprising: a plurality of data transfer lines each used for transferring data; a plurality of data outputting sections each used for detecting said data transferred by one of said data transfer lines and acquiring said detected data synchronously with a data acquiring clock signal; a plurality of data holding sections laid out to form a parallel circuit, each used for holding data according to an input level and each used for transferring said held data to a data transfer line included in said data transfer lines as a data transfer line associated with said held data in response to a select signal; a data-acquiring-clock supplying section configured to supply said data acquiring clock signal to each of said data outputting sections; a clock supplying section configured to generate at least a master clock signal; and a column scan section configured to generate said select signal synchronously with a driving-clock signal and outputting said select signal to each of said data holding sections, wherein: said data transfer lines are laid out in a direction, in which said data holding sections are laid out to form said parallel circuit, and connected to their respective data outputting sections also laid out in the same direction; said column scan section employs: said data-acquiring-clock supplying section supplies said master clock signal or a clock signal taking said master clock signal as a reference signal to each of said data outputting sections as said data acquiring clock signal.