Patent ID: 7615385
Filing Date: 2009-11-10
Classification: H01L

Abstract:
1. A method for fabrication of an integrated circuit having Josephson junctions, comprising the steps of: (a) depositing a Josephson junction trilayer on a substrate; (b) depositing at least one strongly adhering adhesion layer comprising SiO (c) depositing a resist on top of the at least one adhesion layer; (d) exposing the resist to radiation to define a latent pattern therein; (e) selectively removing a first portion of the resist in dependence on the defined latent pattern, a second portion of the resist remaining on the at least one adhesion layer having a strong adhesion thereto; (f) etching a portion of the at least one adhesion layer exposed by removal of the first portion of the resist to form a bilayer mask which selectively exposes portions of the Josephson junction trilayer surrounded by the bilayer mask which masks other portions of the Josephson junction trilayer; and (g) processing exposed portions of the Josephson junction trilayer through the bilayer mask to selectively form circuit elements therefrom.