Patent ID: 8958255
Filing Date: 2015-02-17
Classification: G11C

Abstract:
1. A semiconductor storage apparatus comprising: a plurality of memory cells disposed in a matrix; a plurality of word lines corresponding to rows of the memory cells; a plurality of pairs of bit lines corresponding to columns of the memory cells; a plurality of sense amplifiers configured to amplify a potential difference between the bit lines forming each pair; a pair of common data lines; a data-to-be-written output circuit configured to, in writing data, set voltages of the common data lines forming the pair to values corresponding to the data; a column selection signal output unit configured to output a plurality of column selection signals; and a plurality of column selection gates disposed between the pairs of bit lines and the pair of common data lines and selectively on-off controlled in accordance with the column selection signals, wherein in writing the data, the column selection signal output unit selectively turns on one of the column selection gates by setting each of voltages of the column selection signals to one of a level of a higher-potential power supply voltage and a level of a lower-potential power supply voltage, before activating the sense amplifiers.