Patent ID: 6498066
Filing Date: 2002-12-24
Classification: G11C,H01L

Abstract:
A Read Only Memory (ROM) embedded in a multi-layered integrated circuit, comprising:a semiconductor substrate having a plurality of switching transistors formed thereon in a first direction, wherein each switching transistor of the plurality of switching transistors operates as a memory cell and the plurality of switching transistors in the first direction define a row of memory cells; a plurality of first signal lines coupled to the plurality of switching transistors, each first signal line of the plurality of first signal lines being coupled to an associated first terminal of a corresponding switching transistor of the plurality of switching transistors and each first signal line of the plurality of first signal lines serving as one contact terminal for at least one memory cell in the row of memory cells; a plurality of conductive layers coupled to a second terminal of each associated switching transistor of the plurality of switching transistors and to each other by filled vias, the plurality of conductive layers including a conductive layer defining a plurality of conductive pads, each conductive pad connected to an associated second terminal of a corresponding switching transistor of the plurality of switching transistors; a plurality of second signal lines serving as output terminals for the row of memory cells; and additional filled vias coupling selected ones of the conductive pads to selected ones of the plurality of second signal lines, wherein the plurality of second signal lines serve as output lines of the row of memory cells.