Patent ID: 6088275
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A semiconductor memory device comprising: a pair of bit signal lines; a sense amplifier disposed between the pair of bit signal lines; a ground potential side transistor inserted between the sense amplifier and a ground potential; and a power supply potential side transistor circuit inserted between the sense amplifier and a power supply potential network, wherein when the ground potential side transistor is turned ON, one of the pair of bit signal lines which is closer to the ground potential is pulled into the ground potential via the sense amplifier, and wherein when the power supply potential side transistor circuit is turned ON, the other one of the pair of bit signal lines which is closer to the power supply potential is pulled into the power supply potential via the sense amplifier, thereby amplifying a potential difference between the pair of bit signal lines,wherein the power supply potential network includes a first power supply potential Vpp and a second power supply potential Vcc and Vpp is greater than Vcc,wherein the power supply potential side transistor circuit includes a first power supply potential side transistor inserted between the sense amplifier and the first power supply potential and a second power supply potential side transistor inserted between the sense amplifier and the second power supply potential, andwherein the first power supply potential side transistor is turned ON for a predetermined period of time; the ground potential side transistor is turned ON during the predetermined time period and the ON state of the ground potential side transistor is maintained, and when the predetermined time period ends, the first power supply potential side transistor is turned OFF and the second power supply potential side transistor is turned ON.