Patent ID: 8354324
Filing Date: 2013-01-15
Classification: H01L

Abstract:
1. A method of fabricating a two-terminal mesa phototransistor, comprising: fabricating on a substrate a first semiconductor layer of a first doping type; fabricating a second semiconductor layer of a second doping type on the first semiconductor layer, the second doping type being opposite to the first doping type, the second semiconductor layer forming portions of a first semiconductor junction with the first semiconductor layer; etching the first and the second semiconductor layers to produce a mesa structure comprising mesa sidewalls, residue of the first semiconductor layer, the portions of the first semiconductor junction, and residue of the second semiconductor layer; forming a third doped region within the residue of the second semiconductor layer by introducing a first dopant of the first type into the residue of the second semiconductor layer, thereby creating a second semiconductor junction, wherein the third doped region within the residue of the second semiconductor layer and the second semiconductor junction forms one of an emitter or a collector of the phototransistor; forming a fourth mesa sidewall doped region by doping a region of the sidewalls with a second dopant of the first type, wherein an electrically active doping level of the fourth mesa sidewall doped region is higher than an electrically active doping level of the second semiconductor layer at the time of formation of the second semiconductor layer, wherein the fourth mesa sidewall doped region is electrically directly connected to the residue of the first semiconductor layer, wherein (i) the fourth mesa sidewall doped region and the residue of the first semiconductor layer and (ii) the residue of the second semiconductor layer form the first semiconductor junction; and fabricating a dielectric layer on at least a portion of the residue of the second semiconductor layer; wherein the residue of the first semiconductor layer, the fourth mesa sidewall doped region, the third doped region, and the dielectric layer together completely encapsulate the first semiconductor junction, the residue of the second semiconductor layer without the third doped region, and the second semiconductor junction; wherein the residue of the first semiconductor layer, the fourth mesa sidewall doped region, the residue of the second semiconductor layer, and the dielectric layer together completely encapsulate the first semiconductor junction; wherein the first semiconductor junction, the second semiconductor junction, and the dielectric layer together completely encapsulate the residue of the second semiconductor layer without the third doped region; and wherein the residue of the second semiconductor layer without the third doped region, the third doped region, and the dielectric layer together completely encapsulate the second semiconductor junction.