Patent ID: 8996794
Filing Date: 2015-03-31
Classification: G06F,G11C

Abstract:
1. A Flash memory controller adapted to couple to a first Flash memory package and a second Flash memory package through a first Flash memory interface, the Flash memory controller to receive a first instruction relating to the first Flash memory package and adapted to perform a first process depending on the first instruction, the Flash memory controller to receive a second instruction relating to the second Flash memory package and adapted to perform a second process depending on the second instruction, wherein the Flash memory controller is adapted to split the first process into multiple first sub-steps and adapted to split the second process into multiple second sub-steps, wherein the Flash memory controller is further adapted to interleave execution of the first and second sub-steps during time intervals within a first or second sub-steps in which said first flash memory interface is not-busy; Wherein the flash memory controller is connected to multiple flash memory interfaces, each of which is connected to multiple flash memory packages or chip dies; wherein the Flash memory controller retrieves and stores data from the Flash memory packages by issuing a stream of processes comprising one or more of: a read, write and erase process, wherein every read, write or erase process is split into multiple sub-steps, the Flash memory controller configured to perform sub-steps in a later process before sub-steps of an earlier process have completed, wherein multiple processes can proceed in parallel inside multiple Flash memory packages or chip dies connected to the first Flash memory interface.