Patent ID: 6214670
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A method for manufacturing a short-channel MOSFET device in a semiconductor substrate having a surface and containing shallow trench isolation (STI) regions, comprising the steps of:(a) forming a pad oxide layer on the substrate surface;(b) forming an insulating layer on the first oxide layer;(c) forming a photoresist layer on the insulating layer;(d) forming an etching mask by patterning the photoresist layer to define at least a gate region of the device;(e) forming an opening into the gate region of the substrate by etching the insulating layer and the first oxide layer and into a portion of the substrate, whereby the the gate region is recessed relative to the surface of the semiconductor substrate;(f) removing the photoresist from the substrate;(g) forming a gate oxide layer on the substrate in the recessed gate region opening;(h) depositing a layer of metal over the substrate thereby forming a gate metal conductor in the opening over the gate oxide layer;(i) removing the layer of metal apart from the gate metal conductor from the top surface of insulating layer,(j) removing the insulating layer, thereby exposing the gate metal conductor and the pad oxide surfaces;(k) forming a lightly doped drain (LDD) region in the substrate defined by self alignment with the gate metal conductor by a first ion implantation;(l) then forming silicon dioxide spacers conforming to the gate metal conductor and the pad oxide, wherein the pad oxide layer under the spacers is preserved; and(m) forming a raised source and drain region in the substrate defined by self alignment with the silicon dioxide spacers and the recessed gate metal conductor by a second ion implantation.