Patent ID: 6190959
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of fabricating semiconductor memory cells of an array of semiconductor memory cells, comprising:exposing a photoresist film on a substrate to a source of radiation through a mask having apertures for patterning adjacent trenches, wherein a phase of said radiation transmitted through a first said aperture is varied with respect to a phase of said radiation transmitted through a second said aperture to form adjacent trench patterns in said exposed photoresist film which are separated by a distance which is less than a minimum feature size F;etching portions of said substrate defined by said adjacent trench patterns to form adjacent trenches in said substrate which are separated by a spacing S which is less than said minimum feature size F;forming storage capacitors in said adjacent trenches; andpatterning said substrate to form access transistors coupled to respective ones of said storage capacitors to form memory cells.