Patent ID: 7791581
Filing Date: 2010-09-07
Classification: G09G

Abstract:
1. A shift register block comprising: at least one system of a first shift register comprising a plurality of spaced-apart, cascade-connected first unit circuits and outputting an input signal in response to a clock signal, the first shift register sequentially outputting a selection signal from output-stages comprised of the first unit circuits, wherein: a first circuit which is not one of the first unit circuits of the first shift register is disposed in the physical space between a first unit circuit of a preceding output stage and a first unit circuit of a following output stage; the first circuit comprises (i) a processing circuit which uses output of one of the first unit circuits, (ii) a second unit circuit for a second shift register of a system different from a system of the first shift register, and (iii) a processing circuit which uses output of the second unit circuit of the second shift register; and signal paths for the first and second shift registers are provided separately for each of the first and second shift registers on respective sides of a circuit alignment of the first and second unit circuits of the first and second shift registers.