Patent ID: 6209047
Filing Date: 2001-03-27
Classification: G06F

Abstract:
An apparatus for transmitting data comprising:a first-in first-out (FIFO) memory having a storage capacity, for sequentially receiving data from a data storing unit in response to a write enable signal, wherein the FIFO memory has a first flag, a second flag, and a third flag as outputs, said first flag being generated when data from the data storing unit is written to a first portion of the FIFO memory, said first portion being smaller than said storage capacity of the FIFO memory, said second flag being generated when the data is written so as to fill a second portion of the FIFO memory, said second portion being smaller than said storage capacity of the FIFO memory and larger than said first portion, said third flag being generated when no data is contained in the FIFO memory;controlling means for generating said write enable signal from when said first flag is generated until a time when said second flag is generated, wherein said write enable signal causes data stored in said data storing unit to be written into the FIFO memory, said controlling means disabling said write enable signal after a predetermined period after said second flag is generated; anda host computer for continuously accessing the data written in said FIFO memory,wherein a size of said first portion is adjustable by setting a setting value of said controlling means, so that the generation of said first flag and said second flag are adjustable depending on the size of said first portion, and said adjustable generation of said first flag allows said host computer to continuously access the data in the FIFO memory for a period of time after said second flag is generated and said predetermined period has elapsed, and subsequently until said third flag is generated, said period of time changing depending on said adjustable generation of said first flag and said second flag.