Patent ID: 6209074
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A memory module comprising: a plurality of memory devices associated with the memory module; each of said memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address signals corresponding to N bank memory devices where M and N are integers and can be different; said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device where M and N are different; and a non-volatile memory for storing initial presence detect (PD) data; a volatile memory for storing modified PD data that corresponds to a requested mode of operation of a memory module input by a system controller; and a bus controller for interfacing the memory module with the system controller.