Patent ID: 8232826
Filing Date: 2012-07-31
Classification: H03K

Abstract:
1. A circuit comprising: delay circuits operable to delay an input signal to generate delayed signals; first and second multiplexers, wherein the circuit is operable to provide the delayed signals to inputs of the first and the second multiplexers; third and fourth multiplexers, wherein the circuit is operable to provide an output signal of the second multiplexer to a first input of the third multiplexer and to a first input of the fourth multiplexer; a fifth multiplexer, wherein the circuit is operable to provide an output signal of the first multiplexer to a first input of the fifth multiplexer, and wherein the circuit is operable to provide the output signal of the first multiplexer to a second input of the third multiplexer; and a storage circuit having an input operable to receive an output signal of the third multiplexer.