Patent ID: 6661250
Filing Date: 2003-12-09
Classification: H03H

Abstract:
A programmable impedance control circuit, comprising:a MOS array for receiving a first voltage wherein the drain terminals of each MOS device of said MOS array are coupled together in signal communication with each other; an external resistance having an external impedance equal to N times said external resistance; a pad outputting a second voltage obtained by combination of said MOS array and said external resistance; a reference voltage generator for generating a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for said second voltage wherein M and N represent integer numbers; and wherein M times internal impedance is used for N times external impedance (N=M or N not equal to M); wherein the MOS array is constructed with a plurality of PMOSs and turn on an additionally adjacent PMOS when the turned-on PMOS gate voltage reaches a drain voltage; and wherein the MOS array includes a capacitance inserted between a gate and a source of the PMOSs.