Patent ID: 6487123
Filing Date: 2002-11-26
Classification: B41J,G11C

Abstract:
A semiconductor integrated circuit comprising:a plurality of memory cells arranged in an array of n rows and m columns; a plurality of column signal lines having a one-to-one correspondence with each of said m columns; a program addressing circuit for sequentially charging each of said column signal lines in response to a writing instruction for writing to all memory cells of said array, said program addressing circuit being effective for charging the next column signal line corresponding to the next column of memory cells after writing to all memory cells in a current column is complete, said semiconductor integrated circuit being effective for sequentially writing to each memory cell in the column corresponding to the current column signal line charged by said program addressing circuit; and a delay circuit for delaying an address transition of said program addressing circuit for at least a time equivalent to a discharge time for said column signal lines.