Patent ID: 6541990
Filing Date: 2003-04-01
Classification: G01R

Abstract:
A system for testing an integrated circuit, the integrated circuit having a plurality of pins, each of the pins being configured to electrically communicate with a contact of a circuit assembly, the system comprising:a frame defining an aperture and having a bottom surface, the bottom surface being configured to engage a circuit assembly and having a plurality of recesses formed therein, each of the recesses communicating with the aperture; and a plurality of test probes engaging the bottom surface, each of the probes being received, at least partially, within one of the recesses, each of the probes having a proximal end, a distal end, and an intermediate portion disposed between the proximal end and distal end, each distal end extending, at least partially, into the aperture such that each probe is engagable by a pin of an integrated circuit inserted into the aperture, at least of one of the probes having a longitudinal axis and a first laterally extending portion disposed along the intermediate portion of the probe, the first laterally extending portion engaging a complimentary-shaped portion of the recess engaged by the probe, the first laterally extending portion of the probe and the complimentary-shaped portion of the recess being configured to reduce movement of the probe along the longitudinal axis of the probe as the pin of the integrated circuit engages the distal end of the probe.