Patent ID: 6646932
Filing Date: 2003-11-11
Classification: G11C

Abstract:
A semiconductor memory device comprising:a cell array having a plurality of memory cells; a plurality of first normal elements each defined within said cell array as a group of memory cells arranged in a first direction with a first select line for memory cell selection; a plurality of second normal elements each defined within said cell array as a group of memory cells arranged in a second direction with a second select line for memory cell selection, each said second normal element selecting one or more memory cells in operative association with a corresponding one of said first normal elements; a plurality of first redundant elements disposed for replacement of a defective first normal element within said cell array; a plurality of second redundant elements disposed for replacement of a defective second normal element within said cell array; first repair regions each defined within said cell array as a group of first normal elements with permission of replacement by each said first redundant element; and second repair regions each defined within said cell array as a group of second normal elements with permission of replacement by each said second redundant element, wherein at least two of said plurality of first normal elements are activated simultaneously, whether each of such simultaneously activated at least two first normal elements is replaced by said first redundant element is controlled independently of each other, and at least one of said second redundant elements, which repairs a second normal element having a defect that locates in one of said first repair regions including one of said simultaneously activated at least two first normal elements, does not intersect said one of said simultaneously activated at least two first normal elements.