Patent ID: 8964899
Filing Date: 2015-02-24
Classification: H03L

Abstract:
1. A receiving circuit comprising: a data selection circuit selecting two sampling points between which a center phase of one unit interval of a binary input data is located; a correction circuit correcting the two sampling points selected by the data selection circuit; a phase detection circuit detecting a phase at which a level of the two sampling points changes as a boundary phase in the one unit interval, based on the two sampling points corrected by the correction circuit; an arithmetic unit calculating the center phase of the one unit interval, based on either the boundary phase detected by the phase detection circuit or a first phase detector detecting a phase at which a level of the binary input data changes as a boundary phase in the one unit interval; and a data decision circuit determining and outputting the level of one of the two sampling points, based on the center phase and the boundary phase, the data selection circuit selecting the two sampling points based on the center phase calculated by the arithmetic unit, and the correction circuit correcting the two sampling points based on a correction value corresponding to a past data level output by the data decision circuit.