Patent ID: 8554532
Filing Date: 2013-10-08
Classification: G06F

Abstract:
1. A method comprising: providing a system graph of an electronic circuit; identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph; partitioning the tree into at least a first subtree and a second subtree; forming the first subtree by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a count value; forming the second subtree by repeatedly adding branches of the tree to the second subtree, wherein the branches added to the second subtree have not been not assigned to the first subtree; identifying a first link of the system graph as a first global link when the first link forms a path from a branch of the first subtree to a branch of the second subtree; using at least one processor, calculating a solution to the first subtree independently of the second subtree, while ignoring the first global link; and using at least one processor, calculating a solution to the second subtree independently of the first subtree, while ignoring the first global link.