Patent ID: 8885417
Filing Date: 2014-11-11
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a plurality of memory cells; a plurality of word lines electrically connected to the memory cells, the word lines including a n-th word line, a (n−1)-th word line, and a (n+1)-th word line; and a control circuit configured to perform a first operation, a second operation, and a third operation when the nonvolatile semiconductor memory device receives a write command and a first address, the first address including a first page address, the first page address corresponding to the n-th word line, the control circuit being configured to perform the first operation for a memory cell electrically connected to the (n−1)-th word line, the first operation including a verify operation, the control circuit being configured to perform the second operation for a memory cell electrically connected to the n-th word line, the second operation including a write operation, the control circuit being configured to perform the third operation for a memory cell electrically connected to the (n+1)-th word line, the third operation including a verify operation.