Patent ID: 8607178
Filing Date: 2013-12-10
Classification: G06F

Abstract:
1. A method for automated allocation and insertion of repeaters into a physical design of an integrated circuit (IC) chip, comprising: receiving logical rules regarding a number of repeater flops to be inserted in a pipelined routing of a signal between first and second tiles; and allocating and inserting the repeater flops into a physical design of the IC chip based at least in part on the logical rules, an inter-tile routing distance associated with the pipelined routing of the between the first and the second tiles, and a repeater-flop routing distance associated with the repeater flops, wherein each repeater flop is associated with a different phase of a clock signal, wherein each repeater flop comprises a flip-flop, and wherein the receiving and the allocating are performed by one or more processing devices.