Patent ID: 8645451
Filing Date: 2014-02-04
Classification: G06F

Abstract:
1. A block of circuitry, within an integrated circuit device clocked by a device clock signal, said block of circuitry being clocked by a block clock signal and comprising: block inputs for accepting data, input from outside said block of circuitry, on which arithmetic operations are to be performed; arithmetic operations circuitry having arithmetic inputs coupled to said block inputs, for performing said arithmetic operations on said data; and logical operations circuitry for operating on outputs of said arithmetic operations circuitry; wherein: said arithmetic operations circuitry is configured to operate substantially identically on substantially all clock pulses of said block clock signal; and said logic operations circuitry is configured to operate in a first mode on a first set of clock pulses of said block clock signal, and to operate in a second mode on a second set of clock pulses of said block clock signal interleaved with said first set of clock pulses.