Patent ID: 6345079
Filing Date: 2002-02-05
Classification: H03L,H04N

Abstract:
A clock signal generation apparatus comprising:first means for extracting reference information from an input digital signal; an oscillator for generating a reference clock signal having a frequency depending on a control signal; second means connected to the first means and the oscillator for generating the control signal to the oscillator in response to the reference clock signal generated by the oscillator and the reference information extracted by the first means, and for locking a phase of the reference clock signal to the reference information; a memory; third means connected to the second means for deciding whether or not the phase of the reference clock signal is successfully locked to the reference information, and for storing the control signal generated by the second means into the memory when it is decided that the phase of the reference clock signal is successfully locked to the reference information; and fourth means for selecting one of (1) the control signal currently generated by the second means and (2) the control signal stored in the memory, and for feeding the selected control signal to the oscillator.