Patent ID: 7010668
Filing Date: 2006-03-07
Classification: G06F

Abstract:
1. A system for generating complex conditions formed by a Boolean combination of relations comprising: an arithmetic unit which receives at least two operands from a register file; instruction control lines derived from a registered instruction in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction; the arithmetic unit producing a result and a latched arithmetic scalar condition state; a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state; a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state; an arithmetic condition flag (ACF) generation unit for providing a Boolean combination of a present selected state with a previous state; and an ACF latch for storing the previous state and feeding the previous state back to the ACF generation unit.