Patent ID: 7290233
Filing Date: 2007-10-30
Classification: G06F

Abstract:
1. A method for use in circuit design for a set of netlists, comprising the steps of: employing late mode worst case slack calculation functions inherent in timing path trace algorithms which record a worst case arrival and worst case required arrival times at each netlist node as traced paths, and determining worst case slacks by subtracting the worst case arrival time from the worst case required arrival time, and calculating worst case slack values for an entire set of netlist using said late mode worst case slack calculation functions by querying the worst case slack from varied timing model scenarios at each netlist node under varied timing model scenarios, and thereafter, with the worst case slacks in hand, computing required priority factors, recoverability and path composition factors for the netlists by comparing differences in the worst case slack at each node of said set of netlists.