Patent ID: 6792578
Filing Date: 2004-09-14
Classification: G06F,H01L

Abstract:
A hard macro having an antenna rule violation free input/output port, comprising:an input/output (I/O) port having a port level metallic conductor in a low level metalization layer; an I/O transistor having a gate conductor separated from a diffusion region by a gate oxide layer; a top level metallic conductor of a highest level metalization layer that is electrically coupled to a diffusion region; and an electrical connection between the port level metallic conductor and the gate conductor including a first conducting section extending from the gate conductor to the top level metallic conductor and a second conducting section extending from the top level metallic conductor to the port level conductor; wherein the I/O port is free of antenna rule violations, and the I/O port, the I/O transistor, the top level metallic conductor, and the electrical connection form a predefined circuit element that is droppable into a floor plan of a circuit design.