Patent ID: 6999900
Filing Date: 2006-02-14
Classification: G01R,G06F,G11C

Abstract:
1. A method of testing an apparatus for processing data having a memory operable to store data and a data processing circuit coupled to said memory via a memory access port having a plurality of memory access signal connections, said method comprising the steps of: testing a subset of said plurality of memory access signal connections using respective associated diagnostic serial scan chain cells each operable to perform at least one of steps (i) and (ii): (i) applying a diagnostic signal value to a respective memory access signal connection of said subset; and (ii) capturing a diagnostic signal value from said respective memory access signal connection of said subset; and testing a remainder of said plurality of memory access signal connections by at least one of steps (iii) and (iv): (iii) outputting a diagnostic signal generated by said data processing circuit to said memory from said data processing circuit via a respective memory access signal connection of said remainder; and (iv) capturing with said data processing circuit a diagnostic signal input to said data processing circuit from said memory via a respective memory access signal connection of said remainder.