Patent ID: 7135735
Filing Date: 2006-11-14
Classification: H01L

Abstract:
1. A semiconductor device comprising: a support substrate; an embedded insulating layer formed on the support substrate; a semiconductor layer on the embedded insulating layer; at least an element region formed in the semiconductor layer; a plurality of source/drain regions of a first conductivity type, formed in the element region at predetermined intervals; a plurality of body regions of a second conductivity type, sandwiched between a pair of adjacent ones of the source/drain regions in the element region; and a gate formed on each of the body regions with a gate insulating film being laid between them, each of the source/drain regions including: an inner high-concentration portion extending to the embedded insulating layer, and an outer low-concentration portion surrounding the inner high-concentration portion, having a direct contact with the body regions and extending to the embedded insulating layer.