Patent ID: 6455384
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A method of fabricating a MOSFET device, on a semiconductor substrate, featuring source/drain extension regions, located underlying L shaped spacers, comprising the steps of:forming selectively grown epitaxial (SEG) silicon regions, on a first portion of said semiconductor substrate, with said SEG silicon regions comprised with dopants; forming first insulator spacers on sides of said SEG silicon regions; forming an insulator shape on a second portion of said semiconductor substrate, located between said first insulator spacers; selectively removing said first insulator spacers, resulting in an exposure of third portions of said semiconductor substrate; forming said source/drain extension regions in said third portions of said semiconductor substrate; removing said insulator shape; forming composite insulator spacers on sides of said SEG silicon regions; removing an overlying layer, of said composite insulator spacers, resulting in said L shaped spacers, on sides of said SEG silicon regions, directly overlying said source/drain extension regions; growing a gate insulator layer on regions of said second portion of said semiconductor substrate not covered by L shaped spacers; forming a polysilicon gate structure on said gate insulator layer; and forming metal structures, contacting portions of a top surface of said SEG silicon regions, and a top portion of said polysilicon gate structure.