Patent ID: 9013232
Filing Date: 2015-04-21
Classification: H03L,H05K,Y10T

Abstract:
1. A method of reducing interference present in a circuit formed on an integrated circuit comprising the steps of: placing a first conductive strip above a conductive trace on the circuit adapted to carry high frequency digital current; placing a second conductive strip below the conductive trace; placing a third conductive strip in proximity to the conductive trace, the third conductive strip forming at least a part of a first side of a conduit to shield the conductive trace; and placing a fourth conductive strip in proximity to the conductive trace, the fourth conductive strip forming at least a part of a second side of a conduit to shield the conductive trace, wherein the first, second, third, and fourth conductive strips have first and second opposite ends, wherein the first end makes a connection to a reference voltage, and wherein the second end makes no connection.