Patent ID: 9147613
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A method of manufacture of a plurality of semiconductor structures, comprising: growing a thin gate insulator layer on, and in direct physical contact with, a surface of a semiconductor wafer and a surface of a first well and a second well of a first conductivity type; depositing a first semiconductor substructure on the thin gate insulator layer and over the first well; depositing a first spacer layer on a portion of the thin gate insulator layer and on the first semiconductor substructure; depositing a second semiconductor substructure on the first spacer layer and over the second well; depositing a second spacer layer over the first semiconductor substructure and on the first spacer layer and the second semiconductor substructure; etching and exposing a first surface region including the first spacer layer and the second spacer layer, a second surface region including the thin gate insulator layer, a third surface region including the first semiconductor substructure, and a fourth surface region including the second semiconductor substructure; and thereby: forming the first spacer layer adjacent to and in direct physical contact with a side-wall of the first semiconductor substructure; forming the second spacer layer adjacent to the first spacer layer and over the side-wall of the first semiconductor substructure; and forming the second spacer layer adjacent to a portion of a side-wall of the second semiconductor substructure.