Patent ID: 6177816
Filing Date: 2001-01-23
Classification: H03K

Abstract:
An interface circuit comprising:first and second current mirror circuits each having a current input terminal and a current output terminal;a first input circuit including:a first transistor having a gate to which an input signal is input and a drain connected to said current output terminal of said first current mirror circuit;a second input circuit including a second transistor having a gate, to which a predetermined reference voltage is input, and a drain connected to said current output terminal of said second current mirror circuit; andreference setting means connected to each said current input terminal, comprising:current amount setting means, andlogic level determination means for determining a setting current amount, output from said current amount setting means and for feeding back a result to said current amount setting means based upon that determination;said reference setting means setting an output current amount flowing to each said current output terminal as a logic determination level of said first transistor.