Patent ID: 6791882
Filing Date: 2004-09-14
Classification: G11C

Abstract:
A processing apparatus comprising:a central processing unit; a nonvolatile memory; a volatile memory; a liquid crystal display; an input/output port; and a bus, wherein said central processing unit is capable of designating either one of an erase operation and a program operation to said nonvolatile memory, via said bus, such that (i) when said erase operation is designated, said nonvolatile memory erases data stored therein, and (ii) when said program operation is designated, said nonvolatile memory stores data therein, wherein said erase operation includes a threshold voltage moving operation and a verily operation, wherein said threshold voltage moving operation is that in which a threshold voltage of a memory call in said nonvolatile memory is moved to a threshold voltage range indicating an erase state, wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said erase state is completed, wherein said nonvolatile memory repeats said erase operation when the threshold voltage moving operation of said memory cell to that of an erase state is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase state, and wherein said nonvolatile memory is capable of freeing terminals coupled to said bus and said central processing unit is capable of accessing other component parts of said processing apparatus, via said bus, when said erase operation of data stored in said nonvolatile memory is being performed.