Patent ID: 6599838
Filing Date: 2003-07-29
Classification: H01L

Abstract:
A method for forming a metal filled semiconductor feature including a low dielectric constant CMP polishing stop layer for improving a CMP polishing process comprising the steps of:providing a semiconductor processing surface having a anisotropically etched semiconductor feature opening formed through a thickness including a fluorinated amorphous carbon second dielectric insulating layer overlying a first dielectric insulating layer, the fluorinated amorphous carbon second dielectric insulating layer having a CMP material removal rate in a CMP process less than about Â½ of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature opening with a metal to include covering the fluorinated amorphous carbon second dielectric insulating layer; and, removing according to the CMP process excess material above the opening level including the metal covering the fluorinated amorphous carbon second dielectric insulating layer.