Patent ID: 7352646
Filing Date: 2008-04-01
Classification: G11C

Abstract:
1. A method of arranging a decoupling capacitor of a semiconductor memory device, the semiconductor memory device including a plurality of sub memory cell array blocks including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a plurality of local data I/O line pairs separately arranged between each of the plurality of the sub memory cell array blocks, and a plurality of global data I/O line pairs arranged in a perpendicular direction to the plurality of the local data I/O line pairs, the method comprising: arranging first sense amplifiers on left and right sides of each of first sub memory cell array blocks among the plurality of the sub memory cell array blocks; arranging second sense amplifiers, each having a different layout and construction from that of the first sense amplifiers, on left and right sides of each of second sub memory cell array blocks among the plurality of the sub memory cell array blocks with only the second of the first and second sub memory cell array blocks between the second sense amplifiers; and arranging the decoupling capacitor on an empty region of the plurality of the first and second sense amplifiers and connecting the decoupling capacitor between first and second power voltage lines; wherein of the first and second sense amplifiers, only the first sense amplifiers include local sense amplifiers.