Patent ID: 6379159
Filing Date: 2002-04-30
Classification: H01L,H05K,Y10T

Abstract:
A method for manufacturing an interposer for a chip size package, comprising steps of:(1) forming a first insulating layer on a substrate for a cathode comprising metal usable as the cathode of electroplating; (2) forming a first opening at a position of said first insulating layer corresponding to a conductor portion of an object for connection so that a surface of said substrate is exposed to an inner bottom of the opening; (3) filling said first opening with metal by electroplating using said substrate as a cathode, thereby forming a conductive path in the first opening; (4) forming a circuit pattern in contact with said conductive path on said first insulating layer; and (5) removing said substrate partially or entirely to expose said first insulating layer inclusive of an end surface of the said conductive path.