Patent ID: 6341328
Filing Date: 2002-01-22
Classification: G06F

Abstract:
A microcomputer system, for transferring a data block from a memory to a first and second peripheral device, the system comprising:processing unit initializing first and second DMA controllers for co-dependent operation; said first DMA controller and said second DMA controller coordinating operations by communicating over a DMA communications bus; said first DMA controller reading the data element over a global data bus from an address in the memory and providing control signals to the first peripheral device over a first local control bus; and said first DMA controller writing the data element in a single write cycle over the global data bus to the first peripheral device and the second peripheral device wherein said first and second DMA controllers communicate over the DMA commnunications bus via control signals, said control signals including: a hold signal by which said first DMA controller requests permission to write the data element; a hold-acknowledge signal by which said second DMA controller grants said first DMA controller said permission; and a start signal for said first DMA controller to signal the start of data transfer wherein said first DMA controller also provides address signals to the first peripheral device over a first local address bus, and said second DMA controller provides address signals to said second peripheral device over a second local address bus.