Patent ID: 6636947
Filing Date: 2003-10-21
Classification: G06F

Abstract:
A computer system including a system coherency domain for maintaining data coherency for data transferred within said system coherency domain, and means for maintaining data coherency for data transferred to remote devices outside of said system coherency domain, said computer system comprising:a system bus arranged for connection to at least one processor circuit; a host bridge circuit connecting said system bus to said remote devices outside of said system coherency domain, said remote devices being operable for storing data being transferred, said host bridge circuit being selectively operable for detecting a data invalidate command to invalidate specified data previously stored in said remote devices, said host bridge circuit being further operable for writing to a predetermined address in response to said detecting, said writing to said predetermined address being operable to effect an invalidation of said specified data in said remote devices, said computer system further including a coherency directory for tracking coherency of data transfers outside of said system coherency domain, said detecting including checking said coherency directory to determine that said specified data are stored in said remote devices, wherein all data stored in at least one of said remote devices are invalidated in response to said writing.