Patent ID: 6667979
Filing Date: 2003-12-23
Classification: H04L,H04Q

Abstract:
A method for processing ATM cells in bidirectional, upstream and downstream data streams in messages, wherein said processing is performed in modules each having a processing logic at a processing speed higher than an average cell rate, said upstream and downstream data streams having occurrences of empty cycles without ATM cells, said method comprising the steps of:alternating processing of cells of said upstream and downstream data streams by making upstream and downstream requests for empty cycles in order to receive a processing time; generating downstream empty cycles by separately backing up and releasing cells of said downstream data stream; allowing an upstream empty cycle request with priority over a simultaneous downstream empty cycle request given an occurring upstream empty cycle; releasing a downstream empty cycle delayed by a cycle length given a downstream empty cycle request and a simultaneous upstream empty cycle request and no occurring upstream empty cycle; and releasing a downstream empty cycle immediately given a downstream empty cycle request and no simultaneous upstream empty cycle request.