Patent ID: 6383875
Filing Date: 2002-05-07
Classification: H01L,Y10S

Abstract:
A method of forming a transistor gate construction comprising:providing a semiconductive region of a substrate to be gated; providing a conductive transistor gate proximate the region to be gated; providing a gate dielectric layer intermediate the region to be gated and the transistor gate, the gate dielectric layer being at least partially provided by low pressure chemical vapor deposition of a silicon nitride layer at a pressure of at least 1 Torr, a temperature of less than 700Â° C. and using feed gases comprising a silicon hydride and ammonia; and exposing the substrate with silicon nitride layer to oxidizing conditions comprising at least 700Â° C. to form a silicon dioxide layer over the silicon nitride layer, the providing of at least one of the semiconductive region and the transistor gate occurring after the exposing.