Patent ID: 6569727
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method of manufacturing a single deposition layer metal 224 bit DRAM, comprising:forming a semiconductor die from a wafer having outer dimensions no greater than 300 mils wide by 500 mils long; the forming comprising; fabricating at least 224 memory cells on the semiconductor die and arranged as arrays, each of the arrays containing at least 218 memory cells; placing at least one polysilicon interconnect layer over the semiconductor die to form a plurality of word lines interconnecting the memory cells in the memory arrays; depositing only a single deposition layer metal over the semiconductor die to form a plurality of bit lines interconnecting portions of the memory cells in the memory arrays; singulating the die from the wafer; and inserting the semiconductor die into a cavity of an industry standard package having an outer dimension of approximately 340 mils wide by 675 mils long.