Patent ID: 8946895
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; and at least one layer of Cu wiring provided in the insulating layer via an composite layer including a barrier layer and a seed layer on the barrier layer and provided between the Cu wiring and the insulating layer, wherein the barrier layer includes Ta crystal; the seed layer includes an alloy crystal layer of Cu and Al; the Cu wiring is formed such that 60% or higher of all grain boundaries configuring crystals of the Cu wiring are coincidence boundaries of Sigma value 27 or less in at least one cross section of the Cu wiring and that a total value of orientations of a (111) plane and a (200) plane in the Cu wiring is 94%; the orientation of the (111) plane of Cu wiring is 93% and the orientation of the (200) plane is 1%; and the barrier layer comprises a single layer of Ta crystal, or a composite layer of Ta crystal and TaN crystal.