Patent ID: 6590951
Filing Date: 2003-07-08
Classification: H03M

Abstract:
An address generator for generating available addresses, said available addresses being fewer than 2k+n complete addresses, said complete addresses being divided into 2k groups each having 2n position addresses, without generating unavailable complete addresses, the address generator comprising:a first counter for counting a plurality of clock pulses, for generating a group count consisting of k bits indicating one of the 2k groups at each clock pulse, and for generating a carry after counting 2k clock pulses; a second counter for receiving the carry from the first counter, for counting the carry, and for generating a position count consisting of n bits indicating one of the 2n position addresses; a controller for storing unavailable group count values representing the unavailable groups, partially unavailable group count values representing the groups having both available and unavailable position addresses, and unavailable position count values representing the unavailable position addresses, and for controlling the first and second counters not to output the group count and the position count if the group count is one of the unavailable group count values, or the group count is one of the partially unavailable group count values and the position count is one of the unavailable position count values; a bit reverser for receiving and reversing the k bits from the first counter; an operating device for receiving the group count and the position count, for determining an initial seed value corresponding to the received group count, for determining result bits based on the equation: (initial seed value)*(position count+1) modulo 2n; and a buffer for storing an available address formed out of the reversed bits received from the bit reverser and the result bits received from the operating device.