Patent ID: 6773993
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method for manufacturing a self-aligned split-gate flash memory cell, comprising:providing a semiconductor substrate having an active region; forming a buffer isolation layer and a first dielectric layer sequentially overlying the semiconductor substrate; removal of part of the first dielectric layer and the buffer isolation layer to define an opening; forming a gate isolation layer on the bottom of the opening; forming a polysilicon layer conformally overlying the surface of a first dielectric layer and the opening; etching the polysilicon layer and the gate isolation layer to form sidewalls in the opening and to expose the semiconductor substrate between the sidewalls, wherein the sidewalls serve as floating gates; forming a source region in the semiconductor substrate between the floating gates; filling the opening with a second dielectric layer; removal of the first dielectric layer and the buffer isolation layer outside the floating gates; forming a third dielectric layer and a control gate layer overlying the surface of the semiconductor substrate sequentially and conformally; and self-alignment etching the control gate layer to form sidewalls as control gates outside the third dielectric layer.