Patent ID: 7024615
Filing Date: 2006-04-04
Classification: H03M

Abstract:
1. An arithmetic operation method for a cyclic redundancy check in an arithmetic operation circuit which performs arithmetic operations for error detection on data to be transmitted using a plurality of generative polynomials and is used in a communications system in which transmission of said data is accomplished by adding a result from each of said arithmetic operations to said data, said arithmetic operation method comprising: first arithmetic operation processing by a first arithmetic operation section in which a first arithmetic operation is performed on said data by a specified number of bits using a first generative polynomial; second arithmetic operation processing by a second arithmetic operation section in which a second arithmetic operation is performed on said data by a specified number of bits using at least one piece of a second generative polynomial being same as or different from said first generative polynomial; and third arithmetic operation processing by a third arithmetic operation section in which a third arithmetic operation is performed on said data of a specified number of bits and on at least one piece of an arithmetic operation result being obtained at a midpoint in either of said first arithmetic operation or said second arithmetic operation, or in both said first arithmetic operation and second arithmetic operation.