Patent ID: 6849932
Filing Date: 2005-02-01
Classification: H01L

Abstract:
1. An IC chip package comprising: a substrate having a top and bottom surfaces on which conductive circuit patterns are respectively laid, and an opening extended from the top surface to the bottom surface; an IC chip having an active side and an inactive side, said chip being received in said opening of said substrate in such a way that said active side of said chip and said top surface of said substrate face to a same direction, said active side of the chip being electrically connected to the conductive circuit pattern on the top surface of said substrate through bonding wires; a thermally and electrically conductive adhesive layer disposed on said inactive side of said chip and on said bottom surface of said substrate in a completely enclosing way around said opening; a thermally and electrically conductive planar member having a top and bottom surfaces, said planar member being attached to said thermally and electrically conductive adhesive layer with said top surface thereof; a dielectric encapsulant encapsulating the opening, the bonding wires, a portion of the active side of the chip to which the bonding wires are connected, and a portion of the top surface of the substrate to which the bonding wires are connected; and a thermally and electrically conductive encapsulant covered over the dielectric encapsulant, the other portion of the active side of the chip, and the other portion of the top surface of the substrate.