Patent ID: 9001018
Filing Date: 2015-04-07
Classification: G09G,G11C

Abstract:
1. A liquid crystal display, comprising: a liquid crystal panel comprising a plurality of pixel regions defined by intersections of a plurality of gate lines and a plurality of data lines; a timing controller configured to output a data control signal and a plurality of clock pulses, each of the plurality of clock pulses comprising at least three voltage levels; a gate drive unit configured to drive the gate lines in response to the clock pulses; and a data drive unit configured to drive the data lines in response to the data control signal, wherein: wherein the enable period is divided into: a first period during the entirety of which the second voltage level is maintained, and a second period during the entirety of which the first voltage level is maintained, wherein the first period is longer than the second period: wherein output of the third voltage level is immediately succeeded by output of the second voltage level, and wherein output of the second voltage level is immediately succeeded by output of the first voltage level.