Patent ID: 8928364
Filing Date: 2015-01-06
Classification: G05F,H03F

Abstract:
1. An output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; and a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; wherein the DC offset signal is generated in order to equalise the power dissipated in the first and second transistors.