Patent ID: 6815985
Filing Date: 2004-11-09
Classification: H03K

Abstract:
A clock divider in a DLL circuit for generating an internal clock signal synchronized with an external clock signal, the clock divider comprising:a first clock dividing circuit for generating a first clock signal by dividing an input clock signal having a same period as a period of the external clock signal; a second clock dividing circuit for generating both a second clock signal and a third clock signal by dividing the first clock signal from the first clock dividing circuit; a selection signal generation circuit for generating a selection signal in response to a plurality of control signals; and a clock signal selection circuit for selectively outputting the second clock signal or the third clock signal in response to the selection signal; wherein one period of the first clock signal corresponds to two periods of the input clock signal; and wherein the second clock signal is a one-period-based dividing clock signal in which one period of the one-period-based dividing clock signal corresponds to four periods of the input clock signal, the one-period-based dividing clock signal being maintained in a first logic state for one period of the input clock signal and the one-period-based dividing clock signal being maintained in a second logic state for three periods of the input clock signal.