Patent ID: 7231552
Filing Date: 2007-06-12
Classification: G01R,G11C

Abstract:
1. A Joint Test Access Group (JTAG) compatible integrated circuit to be tested, comprising: a test access port (TAP); a TAP instruction execution disabling logic coupled to the TAP; a non-volatile memory having a first code stored therein, wherein the first code comprises at least one field to identify a first variable for the integrated circuit; a TAP data register coupled to receive a second code via the TAP, wherein the second code comprises at least one field to identify a second variable for the integrated circuit; and a comparison logic coupled to the non-volatile memory and the TAP data register, the comparison logic to compare the first code to the second code, the TAP instruction execution disabling logic to enable the integrated circuit to execute subsequently scanned TAP instructions if the first code matches the second code, and to enable the integrated circuit to ignore subsequently scanned TAP instructions if the first code does not match the second code.