Patent ID: 8151219
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. A method for a computing device the method comprising: providing an identification engine for identifying a pattern within a circuit design layout that does not meet at least one manufacturing constraint; providing a plurality of simulation engines for performing, at the computing device, a plurality of different simulations on a decomposition solution; providing an analyzer for (i) identifying a plurality of different decomposition solutions for the identified pattern, (ii) determining, for each particular decomposition solution in the plurality of decomposition solutions, whether the particular decomposition solution meets the manufacturing constraint by using the plurality of simulation engines on the particular decomposition solution, and (iii) identifying at least one decomposition solution from the plurality of decomposition solutions that meets the manufacturing constraint; and providing a stitching engine for replacing the identified pattern in the circuit design layout with the decomposition solution identified to meet the manufacturing constraint.