Patent ID: 6430097
Filing Date: 2002-08-06
Classification: G11C

Abstract:
A semiconductor memory device having a normal mode and a test mode as an operational mode comprising:a memory array including a plurality of memory cells arranged in rows and columns; a plurality of bit lines arranged along the column direction and for carrying out the writing and reading of data to and from said plurality of memory cells; a plurality of word lines arranged along the row direction and for selecting a particular memory cell among said plurality of memory cells, said plurality of word lines being divided into first to fourth word line groups, said first word line group having word lines which correspond to the (4m +1)th, counting the first word line as the first among said plurality of word lines when m is a nonnegative integer, said second word line group having word lines which correspond to the (4m +2)th, counting said first word line as the first, said third word line group having word lines which correspond to the (4m +3)th, counting said first word line as the first, and said fourth word line group having word lines which correspond to the (4m +4)th, counting said first word line as the first; and a row decode circuit activating said plurality of word lines by using said first to fourth word line groups as a unit of activation in accordance with an address signal in said test mode.