Patent ID: 7415594
Filing Date: 2008-08-19
Classification: G06F,Y02D

Abstract:
1. A system, comprising: a plurality of processors, each comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; wherein said plurality of processors and said plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement; wherein, for each of said processors, said plurality of processor ports are configured for coupling to a first subset of said plurality of dynamically configurable communication elements; wherein, for each of said dynamically configurable communication elements, said plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of said plurality of said processors and a second subset of communication ports configured for coupling to a second subset of said plurality of dynamically configurable communication elements; wherein one of said processors is configurable as a source device to transfer a first plurality of data through an intermediate subset of said plurality of dynamically configurable communication elements to a destination device; wherein, after said source device begins transfer of said first plurality of data through said intermediate subset to said destination device, if either said destination device or one of said intermediate subset stalls, the stalling device is operable to propagate stalling information through one or more of said intermediate subset to said source device; wherein said source device is operable to suspend transfer of said first plurality of data upon receipt of the stalling information, wherein a portion of said first plurality of data transmitted after said stalling and prior to the suspending is buffered in at least one of said intermediate subset.