Patent ID: 8667372
Filing Date: 2014-03-04
Classification: G06F,G11C

Abstract:
1. A memory controller that controls a plurality of memories, the memory controller comprising: an estimating unit that counts a number of occurrences of uncorrectable errors obtained as a result of an error checking when there is a request for data, the memory controller controlling the plurality of memories each of which is a dual memory having an independent address line, the dual memory not recognizing an occurrence of an error on the address line, the estimating unit estimating an error has occurred on the independent address line for data related to the request when the number of occurrences of the uncorrectable errors exceeds a first predetermined threshold; and a control unit that generates error data when it is estimated that an error has occurred on the independent address line and disables one independent address line of the dual memory by switching the data output from the memory controller from data related to the request to the generated error data.