Patent ID: 8006151
Filing Date: 2011-08-23
Classification: G01R

Abstract:
1. An integrated circuit comprising; A. a TCK lead, a TMS lead, a TDI lead, and a TDO lead; B. a test access port circuit having a TCK input connected to the TCK lead, a TMS input connected to the TMS lead, a TDI input connected to the TDI lead, a TDO output connected to the TDO lead, a data register and an instruction register that are connected to the TDI input and that are selectively coupled to the TDO output, and a state machine that is connected to the TCK input, the TMS input, the data register and the instruction register, the state machine changing states upon a rising edge of a clock signal on the TCK lead; C. an inverter having an input connected to the TCK lead and an output; and D. a shadow access port circuit having a TCK input connected to the output of the inverter, a TMS input connected to the TMS lead, a TDI input connected to the TDI lead, a TDO output connected to the TDO lead, a data register and an instruction register that are connected to the TDI input and that are selectively coupled to the TDO output, and a state machine that is connected to the TCK input, the TMS input, the data register and the instruction register, the state machine changing states upon a falling edge of a clock signal on the TCK lead.