Patent ID: 7529324
Filing Date: 2009-05-05
Classification: H03M

Abstract:
1. A decoder including Viterbi decoding means for Viterbi-decoding data and fixed delay tree search decoding means for fixed-delay-tree-search-decoding the data, the decoder comprising: a metric calculation circuit used by both the Viterbi decoding means and the fixed delay tree search decoding means, wherein metric calculation circuit includes a branch metric calculation unit, an add-compare-select unit, a path memory, and a path metric update unit, wherein when comparing path metrics in a minimum path metric selection operation for detecting a minimum state of path metrics calculated by the metric calculation circuit, the fixed delay tree search decoding means divides the path metrics into a plurality of groups, detects a minimum path metric for each of the groups, and compares the minimum path metrics of the respective groups to detect an ultimate minimum state of the path metrics, and wherein, in a group divided for comparing the path metrics, when the number of path metrics input to the group is n, the minimum state of the path metrics is detected by performing a round-robin comparison of available combinations of the n path metrics.