Patent ID: 8237423
Filing Date: 2012-08-07
Classification: G06F,H02J,H02M

Abstract:
1. A system comprising: a communication bus; and a plurality of POL (point-of-load) regulators coupled to the communication bus, each POL regulator of the plurality of POL regulators having a respective output stage configured to provide a regulated output voltage to a common load to provide a respective output current to the common load, wherein each POL regulator is also configured to transmit and receive packets over the bus according to a bus communication protocol corresponding to the bus; wherein the plurality of POL regulators is configured to have one of the plurality of POL regulators operate as a master POL regulator and remaining ones of the plurality of POL regulators operate as slave POL regulators; wherein the master POL regulator is configured to transmit in a packet, over the communication bus, the digitized present value of the respective output current of the master POL regulator; wherein the slave POL regulators are configured to receive the digitized present value of the respective output current of the master POL regulator; wherein the plurality of POL regulators are configured to balance a current loading of each POL regulator of the plurality of POL regulators, through each respective slave POL regulator of the slave POL regulators adjusting a duty cycle of a respective control signal of a high-side field effect transistor (FET) in its output stage, based on a difference between the digitized present value of the respective output current of the master POL regulator and a digitized present value of the respective output current of the respective slave POL regulator.