Patent ID: 6525376
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A high withstand voltage insulated gate N-channel field effect transistor, comprising: a P-type semiconductor substrate; an N-type epitaxial layer formed on the semiconductor substrate; a pair of N-type source regions having a high concentration formed on the epitaxial layer; an N-type drain region having a high concentration and formed on the epitaxial layer between and spaced-apart from the source regions; a pair of channel forming regions each disposed between a respective one of the source regions and the drain region; a first insulating film comprised of a gate insulating film disposed over the source and drain regions and the channel forming regions; a gate electrode formed over the channel forming regions through the gate insulating film so as to encircle the drain region; an N-type low concentration region formed between the drain region and the channel forming regions; a second insulating film formed on the low concentration region and having a thickness greater than that of the gate insulating film; a P-type buried layer formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source regions, the drain region, the channel forming regions, and the second insulating film; and a P-type well layer formed in a region under the source regions and the channel forming regions and formed in only a part of a region under the second insulating film so as to surround the drain region.