Patent ID: 6694417
Filing Date: 2004-02-17
Classification: G06F

Abstract:
A processor comprising:a cache; a memory management unit that records storage attributes in association with address ranges; and an interface unit including a write pipeline, wherein said interface unit selectively utilizes said write pipeline to output data granules onto an interconnect in response to storage attributes within said memory management unit associated with an address range including a single address, wherein said write pipeline includes: an address register that specifies said single address; and a queue including storage locations for a plurality of data granules, wherein said queue, responsive to receipt of a plurality of data granules each associated with the single address specified by said address register, loads said plurality of data granules into sequential storage locations of said queue in order of receipt of said data granules, and wherein said queue, upon containing therein a predetermined amount of data granules, outputs said predetermined amount of data granules on the interconnect at least two at a time according to said order of receipt.