Patent ID: 6202299
Filing Date: 2001-03-20
Classification: H01L,Y10T

Abstract:
A method of fabricating a connection component for a semiconductor chip comprising the steps of:(a) providing a dielectric top layer with a thin, flat layer of a base metal so that a lamination zone of the base metal layer underlies a bottom surface of such top layer and so that said base metal layer also has a connection zone portion;(b) providing a noble metal on said base metal only in said connection zone portion;(c) etching said base metal to form elongated striplike leads of said base metal extending from said lamination zone to said connection zone and, completely removing said base metal during said etching step in said connection zone, whereby each said lead includes a lamination zone portion consisting solely of flat strip of said base metal and an adjacent connection zone portion consisting solely of said noble metal; and(d) after said etching step, applying a second support structure layer on said bottom surface of said top layer so that said flat strips of said base metal are sandwiched between said second support structure layer and said top layer and substantially without voids adjacent said strips.