Patent ID: 7644216
Filing Date: 2010-01-05
Classification: G06F

Abstract:
1. A memory adapter card comprising: two rows of contacts along a leading edge of a length of the card, the two rows of contacts adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface; a socket installed on the trailing edge of the card; and a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a legacy high reliability memory module having a parallel interface that is inserted into the socket, and for calculating error correction code (ECC) check bits for address and command information to be transmitted to the legacy high reliability memory module and retaining ECC information included in the data being transferred to and from the legacy module via the daisy chain high-speed memory bus; thereby retaining the interface and data error detection and reliability of both the daisy chain memory interface and the legacy memory module.