Patent ID: 8067774
Filing Date: 2011-11-29
Classification: H01L

Abstract:
1. A thin film transistor array panel, comprising: a substrate; a gate line disposed on the substrate, including a gate electrode, and having a single-layered structure, and a storage line disposed on the substrate and having a single-layered structure; a gate insulating layer disposed on the gate line; a semiconductor layer disposed on the gate insulating layer; a data line disposed on the semiconductor layer, including a source electrode, and having a single-layered structure; a drain electrode disposed on the semiconductor layer, spaced apart from the source electrode, and having a single-layered structure; a passivation layer disposed on the data line and the drain electrode, and having a first contact hole exposing the drain electrode; a first buffer member in an upper surface of the drain electrode exposed through the first contact hole; and a pixel electrode electrically connected to the drain electrode through the first buffer member.