Patent ID: 7778374
Filing Date: 2010-08-17
Classification: H04L

Abstract:
1. An input receiver that receives an input data signal, the input receiver comprising: a first input buffer that is synchronized with and enabled by a clock signal, that senses a difference between a voltage of the input data signal and a first reference voltage to provide a first sensing result, and that amplifies the first sensing result, the input data signal and the first reference voltage being respectively input to a positive input terminal and a negative input terminal of the first input buffer; a second input buffer that is synchronized with and enabled by the clock signal, that senses a difference between a second reference voltage and the voltage of the input data signal to provide a second sensing result, and that amplifies the second sensing result, the second reference voltage and the input data signal being respectively input to a positive input terminal and a negative input terminal of the second input buffer; and a phase detector that detects a difference between a phase of an output signal of the first input buffer and a phase of an output signal of the second input buffer, and that outputs a detection output signal corresponding to a detection result, wherein the first input buffer comprises: an input reception unit that comprises a first input transistor having a gate to which the input data signal is applied and a second input transistor having a gate to which the first reference voltage is applied; a sense amplification unit that is connected to a first end of the first input transistor and a first end of the second input transistor, that senses a difference between a voltage at the first end of the first input transistor and a voltage at the first end of the second input transistor as the first sensing result, and that amplifies the first sensing result; and a control unit that enables the input reception unit and the sense amplification unit responsive to the clock signal, wherein the gate of the first input transistor is the positive input terminal of the first input buffer, and the gate of the second input transistor is the negative input terminal of the first input buffer.