Patent ID: 6721774
Filing Date: 2004-04-13
Classification: G06F

Abstract:
A Wallace-tree multiplier for multiplying a multiplicand signal and a multiplier signal, comprising:means for generating a plurality of intermediate result signals from said multiplicand signals and said multiplier signals; and a plurality of adder circuits for adding said intermediate result signals to generate result signals representing the result of multiplying said multiplicand and said multiplier, arranged in a Wallace-tree configuration, at least some of said adder circuits being four-input adder circuits having four inputs, each such four-input adder circuit comprising a first three-input adder circuit generating as outputs a first sum signal and a first carry-out signal and receiving as inputs three of the four inputs to said four-input adder circuit, a first delay element having an input and an output and delaying a signal applied to its input by a predetermined time interval less than the period of a clock cycle before providing said signal to its output, receiving as an input the fourth of the four inputs to said four-input adder circuit and providing as an output the signal applied to its input, and a second three-input adder circuit generating as outputs a second sum signal and a second carry-out signal, receiving as inputs a carry-in signal, said first sum signal and the output signal of said delay element, wherein said predetermined time interval is selected to delay the arrival of said fourth input to said second three-input adder circuit by a time selected to cause said fourth input signal to arrive at said second three-input adder circuit closer in time to the time the other two inputs of said second three-input adder circuit arrive at said three-input adder circuit so as to thereby reduce spurious switching of said second three-input adder circuit.