Patent ID: 6449674
Filing Date: 2002-09-10
Classification: G11C

Abstract:
An internal command signal generator, comprising:a first buffer means for buffering an external input command control signal with a signal level suitable to an internal circuit operation; a second buffer means for buffering an external clock signal with an internal clock signal suitable to an internal circuit operation; a delay means for delaying an output signal of the first buffer means by a predetermined time in order to ensure a setup and hold time margin about the internal clock signal; a command decoder means for receiving buffering signals generated from the first buffer means, previously performing a decoding operation by combining the buffering signals during a constant delay time determined by the delay means, and generating an internal command signal; and a latch means for latching an internal command signal generated from the command decoder means, and then synchronizing the internal command signal to the internal clock signal generated from the second buffer means.