Patent ID: 6483338
Filing Date: 2002-11-19
Classification: G01R

Abstract:
A testing system in a chip, for testing a circuit module of the chip, the testing system receiving a reference clock and a test input signal outputted serially from a test machine, the testing system comprising:a serial/parallel converting circuit for receiving the reference clock and the test input signal serially, producing a test command signal in parallel, and sending a test output signal to the test machine; a command port for receiving and storing the test command signal, and for outputting a first test signal and a second test signal; a selector for receiving the second test signal and producing a selection signal for selecting the circuit module of the chip; a test data decoder for receiving the first test signal, and producing a test data signal as an input to the circuit module selected; and a controlling circuit for outputting a controlling signal into the circuit module selected, wherein the circuit module produces the test output signal.