Patent ID: 8250340
Filing Date: 2012-08-21
Classification: G06F

Abstract:
1. A VLIW processor, comprising: fetch means for fetching an instruction that includes a plurality of operation fields; and a decoder unit for decoding the plurality of operation fields in the fetched instruction in parallel with each other; the VLIW processor being characterized in that: the plurality of operation fields are categorized into two types, a first type of operation field and a second type of operation field, the plurality of operation fields includes one operation field of the first type and at least two operation fields of the second type, the first type of operation field is composed of a condition code with no operand thereof, the second type of operation field is composed of an operation code and one or more operands, and wherein the condition code in the first type of operation field controls an execution flow of the instruction which includes the at least two operation fields of the second type.