Patent ID: 6477630
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A memory structure having hierarchical bank control, said memory structure comprising:a plurality of banks, wherein each one of said plurality of banks includes a plurality of word lines, wherein only one of said plurality of word lines within said each one of said plurality of banks can be activated at a time, and wherein each one of said plurality of banks is subdivided into a number of blocks within a bank, wherein each one of said blocks within a bank comprises a subset of said plurality of word lines; a plurality of bank timing lines wherein a respective one of said bank timing lines is coupled to a respective one of said plurality of banks in a one-to-one relationship; and a plurality of block lines, said plurality of block lines being equal in number to said number of said blocks within a bank, wherein each of said plurality of block lines is coupled to and shared with all of said plurality of banks, and wherein within each one of said plurality of banks, each of said blocks within a bank is coupled to and shared with said respective one of said bank timing lines, and a respective one of said plurality of block lines is coupled to said blocks within a bank in a one-to-one relationship with a respective one of said blocks within a bank.