Patent ID: 8271254
Filing Date: 2012-09-18
Classification: G06F

Abstract:
1. A simulation modeling method of BT instability of a transistor in a semiconductor integrated circuit, comprising: setting a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of a simulated model of the transistor as an independent bias condition from other terminals of the simulated model; and calculating BT instability based on simulating the model with a model parameter of the transistor model changed and being operated under the set bias condition; wherein after defining at least one model parameter obtained by relating a surface potential under the gate of the transistor and at least one terminal bias among the drain terminal, the source terminal and the substrate terminal of the transistor, each of the terminal bias conditions is adjusted through the aforementioned model parameter so as to calculate BT instability using a function considered a distribution of a surface potential under a gate of the transistor.