Patent ID: 8468295
Filing Date: 2013-06-18
Classification: G06F,Y02D

Abstract:
1. A method for reducing power consumption in memory, comprising: tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use; setting, by the operating system, a Partial Array Self Refresh field of a mode register, wherein the field indicates a portion of the logical units of the memory system that are in use, wherein each logical unit of the memory system is a bank of the memory system; analyzing the field of the mode register to determine if a particular logical unit is in use; refreshing a particular logical unit, to the exclusion of other logical units, in response to a determination that the particular logical unit is in use; and executing a reliability, availability, and serviceability operation on the particular logical unit in response to a determination that the variable indicated the particular logical unit is in use, wherein the reliability, availability, and serviceability operation includes a patrol scrubbing, sparing, mirroring, or re-silvering operation.