Patent ID: 6420923
Filing Date: 2002-07-16
Classification: H03H

Abstract:
A low supply, current-controlled FET Pi attenuator network, comprising:a first current-controlled FET resistor connected between an input node and a ground node and having a gate terminal connected to a drain terminal; a second current-controlled FET resistor connected between said input node and an output node and having a gate terminal connected to a drain terminal; a third current-controlled FET resistor connected between said output node and said ground node and having a gate terminal connected to a drain terminal; a DC return path connected between said output node and said ground node, with said DC return path being connected in parallel with said third current-controlled FET resistor; a first DC blocking capacitor connected between a Pi attenuator network input and said input node; a second DC blocking capacitor connected between said input node and said first current-controlled FET resistor; and a third DC blocking capacitor connected between said output node and said third current-controlled FET resistor; wherein resistance characteristics of said first, second, and third current-controlled FET resistors vary in relation to input currents flowing into said drain terminal of said first, second, and third current-controlled FET resistors.