Patent ID: 7154772
Filing Date: 2006-12-26
Classification: G11C

Abstract:
1. A memory comprising: an array of random access memory cells having MTJs arranged in a plurality of rows and columns, each intersection of the plurality of rows and columns forming a memory cell; a plurality of write bit lines, each of the plurality of write bit lines used to place a data value in a predetermined memory cell located within a predetermined column of the array of random access memory cells; a plurality of read bit lines, each of the plurality of read bit lines used to read the data value in a predetermined memory cell located within a predetermined column of the array of random access memory cells, the plurality of write bit lines being electrically isolated from the plurality of read bit lines; and a plurality of read word lines, each of the plurality of read word lines used with the read bit lines to read the data value in the predetermined cell located on a predetermined row of the memory cells; and a plurality of write word lines, each of the plurality of write word lines used with the write bit lines to place the data value in the predetermined memory cell located on the predetermined row of the memory cells, the plurality of write word lines being electrically isolated from the MTJs; wherein each of the plurality of write bit lines further comprises a write bit line conductor in close proximity but not in direct contact with a magnetic tunnel junction in a random access memory cell in the array of random access memory cells used for writing a state to the magnetic tunnel junction, the write bit line conductor being electrically isolated from all conductors of data content that are used to read a state of the magnetic tunnel junction.