Patent ID: 8305808
Filing Date: 2012-11-06
Classification: G11C,H01L

Abstract:
1. A low-voltage electrically erasable programmable read only memory array, comprising a plurality of parallel bit lines, including a first bit line; a plurality of parallel word lines extending substantially perpendicular to said bit lines, including a first word line and a second word line; a plurality of parallel common source lines parallel to said word lines, including a first common source line and a second common source line; and a plurality of sub-memory arrays each connecting with one said bit line, two said word lines and two said common source lines, and arranged between two said common source lines, wherein each said sub-memory array includes: a first memory cell connecting with said first bit line, said first common source line and said first word line; and a second memory cell connecting with said first bit line and having a common connection point at said first bit line with said first memory cell, and connecting with said second common source line and said second word line, wherein said first memory cell and said second memory cell are symmetrical and arranged between said first common source line and said second common source line, each of said first and second memory cells having a field effect transistor formed in a substrate or a well, wherein said first and second memory cells of said plurality of sub-arrays are programmably separated into at least one selected memory cell connected to a respective bit line, a respective word line, and a respective common source line, a plurality of parity-bit memory cells connected with said respective bit line, and disconnected from said respective common source line, a plurality of parity-word memory cells connected with said respective word line, and a plurality of unselected memory cells, wherein, when each of said first memory cell and said second memory cell has an n-type field effect transistor formed in p-type substrate or a p-type well, a substrate voltage V first bit voltage V a second word voltage V a second bit voltage V said second bit voltage V wherein said read only memory array operates in a “write” mode and in an “erase” mode, wherein in the “write” mode: said V wherein in the “erase” mode: said V wherein when each of said first memory cell and said second memory cell has a p-type field effect transistor formed in an n-type substrate or an n-type well, a substrate voltage V a first bit voltage V a second word voltage V a second bit voltage V said second bit voltage V wherein in the “write” mode: said V wherein in the “erase” mode: said V