Patent ID: 7129148
Filing Date: 2006-10-31
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device including a trench isolation region, the method comprising: providing a semiconductor substrate having an epitaxial layer thereon; forming a pad layer on the epitaxial layer; forming a polishing stopper layer on the pad layer; forming at least one trench by etching the epitaxial layer while using at least the polishing stopper layer as a mask; forming a dielectric layer in and above the at least one trench; planarizing the dielectric layer using the polishing stopper layer as a stopper; etching the polishing stopper layer after planarizing the dielectric layer; etching the pad layer and exposing the epitaxial layer, after the etching the polishing stopper layer; forming a sacrificial oxide layer on the exposed epitaxial layer, wherein the sacrificial oxide layer consists of an oxide layer formed by thermally oxidizing the exposed epitaxial layer, after the removing the pad layer; wherein the sacrificial oxide layer is not formed on the dielectric layer; thermally treating the dielectric layer at a temperature of at least 1100° C. after the forming the sacrificial oxide layer; after the thermally treating the dielectric layer at a temperature of at least 1100° C., implanting impurity ions in the epitaxial layer; and after the implanting impurity ions, removing the entire sacrificial oxide layer and an upper portion of the dielectric layer using isotropic etching.