Patent ID: 8320173
Filing Date: 2012-11-27
Classification: B60G,G11C,H01L

Abstract:
1. A method of programming a memory cell, the memory cell comprising a transistor which includes a transistor gate spaced from a channel region by at least a gate dielectric, which includes a first source/drain region adjacent one side of the channel region, and which includes a second source/drain region adjacent an opposing side of the channel region from the first source/drain region; wherein the channel region comprises phase change material regions adjacent the first and second source/drain regions and comprises non-phase change material between the phase change material regions, the method comprising: utilizing the first source/drain region as a source and the second source/drain region as a drain to induce one memory state of the memory cell; utilizing the second source/drain region as a source and the first source/drain region as a drain to induce another memory state of the memory cell; and wherein the memory cell is supported by a monocrystalline silicon base.