Patent ID: 8415175
Filing Date: 2013-04-09
Classification: H01L,Y10T

Abstract:
1. A method for identifying a location, relative to a particular wafer edge, in which a die on a semiconductor wafer is fabricated, the wafer including a plurality of dies having locations that form a wafer pattern, the method comprising: providing a pattern layer on the semiconductor wafer; patterning the pattern layer to provide a die identification region adjacent to or on the die on the semiconductor wafer, wherein the die identification region includes a wafer indicator and a duplicate wafer pattern, the wafer indicator indicating an orientation of the duplicate wafer pattern relative to the particular wafer edge; providing a marker layer over the die identification region; providing a die identification marker in the marker layer over a respective die location in the duplicate wafer pattern identifying a location of the die on the semiconductor wafer; separating the die from the semiconductor wafer and the other dies; and thereafter, examining the die identification region on the die to identify the location, relative to the particular wafer edge, in which the die was fabricated based only on the wafer indicator and the respective die location indicated by the die identification marker.