Patent ID: 6130133
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A fabricating method of high-voltage devices, comprising the steps of:providing a first-type substrate;forming a first, second-type doped region and second, second-type doped region in portions of the first-type substrate;forming a first field oxide layer on the first doped region, a second field oxide layer on the second doped region, and a third field oxide layer on the substrate between the first, second-type doped region and the second, second-type doped region;forming a third, second-type doped region and a fourth, second-type doped region in the substrate, wherein the third doped region is between the first field oxide layer and the third field oxide layer, and the fourth doped region is between the second field oxide layer and the third field oxide layer;removing the third field oxide layer;forming a gate oxide layer on the substrate between the first field oxide layer and the second field oxide layer;forming a (gate on the gate oxide layer the first field oxide layer, and the second field oxide layer; andforming a second-type source region in the first-type substrate to the side of the first field oxide layer and a second-type drain region in the first-type substrate to the side of the second field oxide layer.