Patent ID: 7307883
Filing Date: 2007-12-11
Classification: G06F,G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a non-volatile memory cell array having a first storage area and a second storage area, the first storage area storing booting data, and the second storage area storing an address of the first storage area; a data register coupled to the non-volatile memory cell array; a detecting circuit to generate a detection signal indicating turn-on of a power supply; an address register, coupled to the data register, capable of storing the address of the first storage area; a control circuit, in response to the detection signal, to cause the address of the first storage area to be stored in the address register; and a state signal output terminal, wherein the state signal assumes a first logical state, after the booting date has been stored in the data register, to indicate that the non-volatile memory cell array can be accessed.