Patent ID: 6051459
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A method of making N-channel and P-channel IGFETS, comprising:providing a semiconductor substrate with N-type and P-type active regions;forming a gate insulator on the N-type and P-type active regions;forming a gate material over the gate insulator;forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region;introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material;applying a first thermal cycle to activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region;removing the first masking layer;forming a second masking layer over the gate material, wherein the second masking layer includes an opening above a second portion of the gate material over the N-type active region, and the second masking layer covers the first portion of the gate material over the P-type active region;introducing an P-type dopant into the second portion of the gate material without introducing the P-type dopant into the first portion of the gate materialforming a third masking layer over the gate material, wherein the third masking layer covers portions of the first and second portions of the gate material;applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively;forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region, andapplying a second thermal cycle, the second thermal cycle having a lower temperature than the first thermal cycle.