Patent ID: 6150861
Filing Date: 2000-11-21
Classification: G11C,H03K

Abstract:
A flip-flop comprising:a latch circuit having input and output terminals, the latch circuit being operable to receive an input signal at the input terminal and a clock signal, and operable to generate an output signal at the output terminal, the output signal tracking the input signal during a first portion of the clock signal, the output signal being constant during a second portion of the clock signal;a master flip-flop having an input terminal coupled to the output terminal of the latch circuit, the master flip-flop being operable to receive the clock signal and the output signal of the latch circuit, and operable to generate an output signal at an output terminal, the output signal tracking the output signal of the latch circuit during the second portion of the clock signal, the output signal being constant during the first portion of the clock signal;a slave flip-flop having an input terminal coupled to the output terminal of the master flip-flop, the slave flip-flop being operable to receive the clock signal and the output signal of the master flip-flop, and operable to generate an output signal tracking the output signal of the master flip-flop during the first portion of the clock signal, the output signal of the slave flip-flop being constant during the second portion of the clock signal; anda multiplexer operable to receive a data input signal, a mode determining signal and the output signal of the latch circuit, the multiplexer being operable to pass a selected one of the output signal of the latch circuit and that data input signal to the master flip-flop in response to the mode determining signal.