Patent ID: 7623383
Filing Date: 2009-11-24
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a page buffer comprising a lower latch block and an upper latch block; and a memory array connected to the lower latch block via a lower common bit line and connected to the upper latch block via an upper common bit line, the memory array comprising a voltage control block connected to one of the upper even bit line and the lower even bit line to precharge and discharge the upper and the lower even bit lines and connected to one of the upper odd bit line and the lower odd bit line to precharge and discharge the upper and the lower odd bit lines, wherein the lower and the upper even bit lines are electrically connected by the first switch when the voltage control block precharges and discharges the one of the upper and the lower even bit lines and the lower and the upper odd bit lines are electrically connected by the second switch when the voltage control block precharges and discharges the one of the upper and the lower odd bit lines.