Patent ID: 8252639
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A manufacturing method of a thin film transistor array panel, comprising: forming a gate line on an insulating substrate; depositing a gate insulating layer and a first a-Si layer in sequence; depositing a second a-Si layer doped with a conductive impurity on the first a-Si layer and a third a-Si layer including nitrogen on the second a-Si layer; patterning the third a-Si layer, the second a-Si layer, and the first a-Si layer to form a pre-diffusion barrier, pre-ohmic contacts, and a semiconductor layer, respectively; forming a data line and a drain electrode partially overlapping the pre-diffusion barrier; etching the pre-diffusion barrier and the pre-ohmic contacts disposed between the data line and the drain electrode to form diffusion barriers and ohmic contacts, respectively; and forming a pixel electrode electrically connected to the drain electrode.