Patent ID: 7933160
Filing Date: 2011-04-26
Classification: B82Y,G11C

Abstract:
1. A memory device, comprising: a memory cell including a pass transistor and a carbon nanotube storage element, wherein the carbon nanotube storage element is composed of at least a carbon nanotube disposing in between a bottom electrode and a top electrode; and a local sense amp including a local write circuit, a local pre amplifier and a local main amplifier, wherein the local write circuit which includes a first write transistor connecting to the local bit line and a second write transistor connecting to the first write transistor; and the local pre amplifier which includes a local pre-charge transistor for pre-charging a local bit line to a reference voltage for connecting to the memory cell, a local pre-amp transistor for detecting whether the local bit line is higher than the reference voltage or not, and a local pre-amp select transistor for enabling the local pre amp; and the local main amplifier which includes a local pre-set transistor for pre-setting a local pre-amp node which is connected to the local pre-amp select transistor, and a local main-amp transistor for reading the local pre-amp node; and a global sense amp including a data read circuit, a data write circuit, a bypass circuit and a data transfer circuit, wherein the data read circuit is connected to the local main-amp transistor through a read global bit line for reading an output of the local sense amp, the data write circuit is connected to the second write transistor of the local sense amp through a write global bit line for writing an input data, the bypass circuit for bypassing the input data, and the data transfer circuit for transferring an output of the data read circuit or an output of the bypass circuit; and an output latch circuit for receiving an output from the data transfer circuit of the global sense amp; and a latch control circuit generating a locking signal which is generated by a reference signal based on at least a reference memory cell, in order to lock the output latch circuit.