Patent ID: 9191602
Filing Date: 2015-11-17
Classification: H01L,H04N

Abstract:
1. A solid-state imaging device comprising: a photodetecting section having M×N (each of M and N is an integer not less than 2) pixels, each including a photodiode, that are arrayed two-dimensionally in M rows and N columns; N readout wiring lines each arranged for each column, and connected via readout switches with the photodiodes included in the pixels of corresponding columns; a signal connecting section including a plurality of integration circuits each connected to each of the N readout wiring lines, and for outputting a voltage value according to an amount of charge input through the corresponding readout wiring line, a plurality of first holding circuits each connected in series to each of the corresponding integration circuits, and for holding a voltage value output from the corresponding integration circuit, a plurality of second holding circuits each connected in series via a transfer switch to the corresponding first holding circuit, and for holding a voltage value output from the corresponding first holding circuit, and an output switch connected to the corresponding second holding circuit, and for outputting a voltage value held in the corresponding second holding circuit; and a controlling section for controlling an opening and closing operation of the readout switches of the respective pixels and the transfer switches and controlling an output operation of voltage values in the second holding circuits by the output switches to cause voltage values according to amounts of charges generated in the photodiodes of the respective pixels to be sequentially output from the second holding circuits, wherein the controlling section, by bringing the readout switches of respective pixels that compose a certain row out of the M rows into a connected state, causes charges generated in the row to be input to the integration circuits, causes the first holding circuits to hold voltage values output from the integration circuits, and then brings the transfer switches into a connected state to transfer the voltage values to the second holding circuits, and thereafter performs in parallel an operation for causing the voltage values to be sequentially output from the second holding circuits and an operation for, by bringing the readout switches of respective pixels that compose another row out of the M rows into a connected state, causing charges generated in the row to be input to the integration circuits.