Patent ID: 6315883
Filing Date: 2001-11-13
Classification: B23H,H01L

Abstract:
A method of forming conductive features via a damascene process, the method comprising:providing a partially fabricated integrated circuit having a dielectric layer with trenches where said conductive features are to be formed;forming a substantially conformal layer of conductive material over the dielectric layer, whereby the conductive material has a surface comprising recesses over the trenches and substantially flat field regions around the trenches;selectively applying a diffusion barrier film to the recesses;electropolishing the conductive material surface, whereby the conductive material is removed from the recesses more slowly than from the field regions to thereby increase the planarity of the conductive material surface; andremoving the conductive material at a substantially uniform rate over the surface of the conductive material until reaching the dielectric layer, whereby said conductive features remain in said trenches, insulated from one another by regions of the dielectric layer.