Patent ID: 8598641
Filing Date: 2013-12-03
Classification: H01L,Y10S

Abstract:
1. A semiconductor device used in customized applications as a customized semiconductor device, comprising: a silicon (Si) substrate having a transverse x-axis and a longitudinal y-axis; a plurality of parallel oxide isolation regions oriented longitudinally on said Si substrate, each of said plurality of parallel oxide isolation regions being separated one from the other by an equal distance and having an equal height; a plurality of parallel Si fin bodies oriented longitudinally on Si said substrate customized to comprise at least one fin of a fin field effect transistor (FinFET) and at least one electrode of a capacitor, each of said plurality of parallel Si fin bodies interposed midway between adjacent parallel oxide isolation regions, having an equal width and an equal height less than said equal height of said plurality of parallel oxide isolation regions; a dielectric formed on a top surface and lateral surfaces of each of said plurality of parallel Si fin bodies; and a polysilicon layer formed on a longitudinal portion of said top surface and said lateral surfaces corresponding to said longitudinal portion of each of said plurality of parallel Si fin bodies to said Si substrate, a top surface of said polysilicon layer being coplanar with a top surface of said plurality of parallel oxide isolation regions, said polysilicon layer forming a gate of said FinFET, when formed on said at least one fin of said FinFET, and said polysilicon layer forming a top electrode of said capacitor, when formed on said at least one electrode of said capacitor.