Patent ID: 6274412
Filing Date: 2001-08-14
Classification: G02F,G03G,H01B,H01L,H05K

Abstract:
A method for producing an array of one or more Thin Film Transistors comprising the steps of:a) printing a pattern of one or more high conductivity metallic gate lines on a substrate;b) covering said gate lines with a layer having a first sub-layer comprised of a silicon nitride gate dielectric, a second sub-layer comprised of a-Si:H, and a third sub-layer comprised of (n+) a-Si:H;c) printing a pattern of one or more sets of drain, source, and data line conductors;d) depositing one or more Indium Tin Oxide pixels;wherein said gate lines are printed by applying a composition comprising a Reactive Organic Medium (ROM) and metal in a pattern of said one or more gate lines and then heating said pattern to form metal conductors.