Patent ID: 7017139
Filing Date: 2006-03-21
Classification: G06F

Abstract:
1. A method for identifying pin locations to be used for diagonal interconnections in a multi-chip module comprising the steps of: calculating lengths of a plurality of orthogonal interconnections between a first chip and a second chip, wherein said first chip is located adjacent to said second chip; calculating lengths of a plurality of diagonal interconnections between said first chip and a third chip, wherein said first chip is located diagonal to said third chip; receiving an input as to a threshold value, wherein said threshold value is at or below a length of a longest orthogonal interconnection; and tagging with a first value a first particular number of pins of said first chip used for calculating lengths of diagonal interconnections between said first chip and said third chip that are at or below said threshold value, wherein said first particular number of pins tagged with said first value are used for diagonal interconnections.