Patent ID: 8586442
Filing Date: 2013-11-19
Classification: H01L

Abstract:
1. A manufacturing method for a high voltage transistor, the method comprising the steps of: providing a substrate; providing a P-type epitaxial (P-epi) layer above the substrate; forming an N-well in the P-epi layer; forming a P-well in the P-epi layer; forming a plurality of field oxide (FOX) layers above the P-epi layer, wherein a flat surface of the N-well is exposed by one of the FOX layers; forming a gate oxide (GOX) layer between the FOX layers; doping N-type implants into the N-well to adjust an electrical function of the high voltage transistor, wherein the N-type implants are disposed at whole of the flat surface of the N-well; and forming a first N+ region embedded in the N-well.