Patent ID: 6989285
Filing Date: 2006-01-24
Classification: H01L

Abstract:
1. A method of stacking semiconductor wafer segments, each of the semiconductor wafer segments including integrated circuitry, comprising: providing a first semiconductor substrate segment having a first side including integrated circuitry thereon and having a back side; providing at least one second semiconductor substrate segment having a first side including a plurality of integrated circuits thereon, having a back side, and having a notch through the at least one second semiconductor substrate segment, the notch extending between and substantially perpendicular to a circuitry side and a back side of the at least one second semiconductor substrate segment; stacking the first semiconductor substrate segment and the at least one second semiconductor substrate segment in at least partially superimposed relationship to form a multi-level stack of semiconductor substrate segments having portions thereof attached to each other; separating the multi-level stack of semiconductor substrate segments to form at least two semiconductor substrate segment stacks, each multi-level stack of the at least two semiconductor substrate segment stacks comprising a first semiconductor substrate segment having a side including integrated circuitry and a back side and at least one second semiconductor substrate segment having a side including integrated circuitry and a back side; and stacking the at least two semiconductor substrate segments in at least partially superimposed relationship having bond pads on the first semiconductor substrate segment of at least one of the at least two semiconductor substrate segment stacks on a side adjacent the at least one second semiconductor substrate segment of the multi-level semiconductor substrate segment stack at a periphery thereof.