Patent ID: 9043679
Filing Date: 2015-05-26
Classification: G06F,G11C

Abstract:
1. A memory device, comprising: a memory chip that stores data; and an external controller that controls the memory chip, the memory chip comprising: a memory cell array including a plurality of memory cells configured to store data of two or more bits, the memory cells constituting a page as a program unit; and an internal controller that executes a program operation for page data including a lower page program operation and an upper page program operation for the same page of the memory cell array, and executes a read operation for page data including a lower page read operation and an upper page read operation from the memory cell array, the internal controller being configured to output the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation, the external controller being configured to add, to a part of page data to be programmed, identification information for identifying whether the page data is lower page data or upper page data, in the program operation, and to identify whether the read page data is lower page data or upper page data by referring to the identification information, after performing error correction decoding on data read from the memory chip, in the read operation.