Patent ID: 6268660
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A carrier for integrated circuit chips comprising:a semiconductor material having a first planar surface and a second planar surface;a via extending directly through said semiconductor material from said first planar surface to said second planar surface;a conductive material extending through said via from said first planar surface to said second planar surface for passing signals along the vias extending through the semiconductor material;an insulation barrier between said conductive material and an inner surface area of said via to insulate said conductive material from said semiconductor material;a multilevel wiring located at said first planar surface and coupled to said conductive material, wherein said multilevel wiring provides a communication link between multiple integrated circuits on said first planar surface;a first connecting means for electrically coupling integrated circuits to said multilevel wiring; anda second connecting means extending beyond said second planar surface for connecting said conductive material at said second planar surface with external components.