Patent ID: 8489828
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. A control apparatus comprising: a non-volatile Random Access Memory (RAM) divided into a plurality of memory regions including a Read-Only Memory (ROM) region from which data is read and a RAM region where data is read and written; a Central Processing Unit (CPU) capable of executing a plurality of types of access to the non-volatile RAM, the plurality of types of access including writing data to the ROM region; and a protecting portion intervening between the CPU and the non-volatile RAM, wherein the protecting portion comprises: a register for storing address information capable of specifying address ranges corresponding to the ROM region and the RAM region among the memory regions of the non-volatile RAM; access enabling means for enabling the CPU to write data to the ROM region while an enable signal inputted to the protecting portion externally is active, when the CPU performs a write-access to the ROM region; and initializing means for initializing the address information stored in the register to be predetermined address information as an initial value when the enable signal is deactivated after activating the enable signal.