Patent ID: 9196338
Filing Date: 2015-11-24
Classification: G11C

Abstract:
1. A magnetoresistive memory device comprising: first and second bit lines; a memory cell comprising a first magnetoresistive element and a first transistor serially connected between the first bit line and a power supply line, and a second magnetoresistive element and a second transistor serially connected between the second bit line and the power supply line, gate electrodes of the first and second transistors being connected to a word line; third and fourth transistors having current paths inserted in the first and second bit lines, gate electrodes of the third and fourth transistors being connected, respectively, to the second and first bit lines provided on a side opposite to the memory cell; and fifth and sixth transistors connected to the first and second bit lines of the third and fourth transistors on the side opposite to the memory cell, the fifth and sixth transistors being configured to be turned on in response to a signal indicating that data is to be read from the memory cell.