Patent ID: 6259326
Filing Date: 2001-07-10
Classification: H03L,H04L

Abstract:
An apparatus for recovering a clock from an input data signal, said apparatus comprising:means, operative when said input data signal has a first logic level, for generating a first oscillatory signal at a preselected one of at least a first or a second frequency;means, operative when said input data signal has a second logic level complementary to said first logic level, for generating a second oscillatory signal at said preselected one of said at least first or second frequencies; andmeans for generating said recovered clock at said preselected one of said at least first or second frequency by combining said first oscillatory signal and said second oscillatory signal;wherein said first oscillatory signal starts at a particular known phase when said means for generating said first oscillatory signal begins operating to generate said first oscillatory signal; andwherein said second oscillatory signal starts at a particular known phase when said means for generating said second oscillatory signal begins operating to generate said second oscillatory signal.