Patent ID: 6067602
Filing Date: 2000-05-23
Classification: G06F

Abstract:
A memory system for storing a plurality of method frames, each of said method frames containing a plurality of frame components, said memory system comprising:a main memory circuit;a first stack cache management unit coupled to said main memory circuit and configured to cache a first frame component of a first method frame and a second frame component of a second method framewherein said first frame component of said first method frame has a first characteristic with respect to said first method frame; anda second stack cache management unit configured to cache a second frame component of said first method frame and a first frame component of said second method frame,wherein said second frame component of said first method frame is different from said first frame component of said first method frame;said first frame component of said second method frame has a first characteristic with respect to said second method frame and said first characteristic with respect to said first method frame and said first characteristic with respect to said second method frame are a same characteristic; andsaid second frame component of said second method frame is different from said first frame component of said second method frame.