Patent ID: 9166739
Filing Date: 2015-10-20
Classification: H03M,H04L

Abstract:
1. An error correction processing circuit, comprising: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a serial conversion circuit that converts the plurality of pieces of data divided by the division circuit into a plurality of pieces of serial data; a plurality of encoders that are provided in parallel, and that perform encoding for the plurality of pieces of serial data converted by the serial conversion circuit, respectively; a parallel conversion circuit that converts the plurality of pieces of data for which the encoding has been performed by the plurality of encoders, into a plurality of pieces of parallel data such that each of the pieces of parallel data corresponds to a bus width in a state before the serial conversion performed by the serial conversion circuit; a multiplexing circuit that multiplexes the plurality of pieces of parallel data provided in the conversion performed by the parallel conversion circuit; an output circuit that outputs the data multiplexed by the multiplexing circuit; and a control circuit configured to receive frame pulses that indicate beginnings of frames of the input data inputted into the division circuit and to control writing and reading data into/from the division circuit and writing and reading data into/from the multiplexing circuit based on the frame pulses.