Patent ID: 6153453
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in a well of a first conductivity type of a substrate of the second conductivity type, including the steps of:forming a JFET channel region of the second conductivity type at the same time as lightly-doped drain/source regions of the second conductivity type-channel MOS transistors;forming a JFET gate region of the first conductivity type at the same time as lightly-doped drain/source regions of the first conductivity type-channel MOS transistors; and forming JFET drain/source regions of the second conductivity type at the same time as heavily-doped drain/source regions of second conductivity type-channel MOS transistors.