Patent ID: 7709332
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A method for producing a field-effect transistor of planar structure, with double self-aligned gates on each side of a channel and metallic source and drain electrodes, wherein photolithographic steps relating to definition of the gates, source and drain areas and channel areas are all performed before bonding, the method comprising: (a) forming a first gate on a first substrate of semi-conductor on insulator type, (b) depositing on the first gate a hard layer designed to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity, (c) flipping and bonding of an assembly formed from steps (a) and (b) on a second substrate and fabricating a second gate in the gate cavity, (d) etching the assembly to expose a portion of a bounding layer to form a source recess and a drain recess, (e) siliciding the portion of the bounding layer exposed after etching to make an electric connection between the portion of channel situated between the self-aligned gates and the future source and drain electrodes, and (f) depositing a metal in the source recess and the drain recess to form the entirely metallic source and drain electrodes after step (e).