Patent ID: 8492207
Filing Date: 2013-07-23
Classification: H01H,H01L

Abstract:
1. An eFuse circuit for implementing enhanced eFuse blow operation comprising: an independently voltage controlled isolated silicon region; eFuse circuitry disposed above said independently voltage controlled silicon region; said eFuse circuitry including an eFuse and a field effect transistor (FET) connected to the eFuse operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse; and a threshold voltage control function controlling a voltage potential of said independently voltage controlled isolated silicon region; said threshold voltage control function including a time delay string of inverters activated responsive to the blow mode; said threshold voltage control function applying a grounding input signal to said independently voltage controlled silicon region during the sense mode providing a first threshold voltage of the FET; and applying a charging input signal to said independently voltage controlled silicon region during the blow mode providing a second reduced threshold voltage of the FET, providing enhanced FET blow function.