Patent ID: 9159710
Filing Date: 2015-10-13
Classification: B81C,H01L

Abstract:
1. A device comprising: a first insulator layer that defines: (i) the major plane of the device; and (ii) a transverse direction that is normal to the major plane at any given point on the major plane; and a first semiconductor layer; wherein: the first semiconductor layer and the first insulator layer are monolithically integrated into a stack structure; the stack structure includes a first NEMS/MEMS region; the first NEMS/MEMS region of the stack structure is structured, connected, sized, shaped and/or located to operate as a first NEMS/MEMS machine that includes a first moving part; the semiconductor layer includes a first major surface and a second major surface, spaced apart in the transverse direction; the first semiconductor layer includes a first JFET structure; the first JFET structure includes: the following JFET regions: a source region, a drain region, a first gate region and a conductance channel region; the following JFET regions of the first JFET extend entirely across a transverse dimension of the first semiconductor layer; x is a first doping type (either p or n); y is a second doping type (either p or n); the conductance channel region of the first JFET structure is x doped and the first gate is y doped, to an extent so that during operation of the device: (i) the conductance channel of the first JFET structure will develop depleted and undepleted portions, and (ii) the depleted portions will, at times and as determined by operating conditions, pinch off the conductance channel of the first JFET structure; the first JFET is electrically connected to the first NEMS/MEMS machine; the first insulator layer is electrically insulating so that current does not flow in the first insulator layer during operation of the device.