Patent ID: 7754607
Filing Date: 2010-07-13
Classification: G02F

Abstract:
1. A method for manufacturing a liquid crystal display, the method comprising: depositing a transparent conductive layer on a first substrate; defining the transparent conductive layer to form a first pixel electrode, a first bottom layer, a second bottom layer electrically connecting to the first pixel electrode, a third bottom layer, and a fourth bottom layer electrically connecting to the first pixel electrode; depositing a semiconductor insulation layer on the first substrate and the first pixel electrode, the first bottom layer, the second bottom layer, the third bottom layer, and the fourth bottom layer; defining the semiconductor insulation layer to form a first contact opening on the first bottom layer and a second contact opening on the third bottom layer; depositing a metal layer on the semiconductor insulation layer; defining the metal layer to form a first scanning line with a first indentation at an edge thereof, a second scanning line with a second indentation at an edge thereof, a first top layer, and a second top layer, wherein the first scanning line electrically connects to the first bottom layer via the first contact opening, the second scanning line electrically connects to the third bottom layer via the second contact opening, and both the first indentation and the second indentation face the first pixel electrode, wherein the first top layer is disposed on the first substrate and within the first indentation and physically isolated from the first scanning line, and the second top layer is disposed on the first substrate and within the second indentation and physically isolated from the second scanning line; and forming a first metal-insulation-metal diode at an overlapped region between the first bottom layer and the first top layer, a second metal-insulation-metal diode at an overlapped region between the second bottom layer and the first top layer, a third metal-insulation-metal diode at an overlapped region between the third bottom layer and the second top layer, and a fourth metal-insulation-metal diode at an overlapped region between the fourth bottom layer and the second top layer.