Patent ID: 7514309
Filing Date: 2009-04-07
Classification: H01L

Abstract:
1. A method of fabricating a CMOS semiconductor device comprising: providing a semiconductor body; performing well formation and isolation processing in the semiconductor body and defining a first region and a second region; forming a gate dielectric layer on the semiconductor body; forming a gate electrode layer on the gate dielectric layer; forming a protective gate liner on the gate electrode layer; forming a resist mask that defines gate structures; patterning the gate electrode layer to form the gate structures; removing the resist mask wherein the protective gate liner remains on the gate electrode layer of the gate structures; forming a protective region layer over the second region including the remaining protective gate liner of the semiconductor body within the second region; performing a recess etch of active regions within the first region, except on the liner protected gate electrode layer, to form recessed regions within the first region adjacent the liner protected gate electrode layer; forming recess structures within the recessed regions of the first region by forming strain inducing material within the recessed regions subsequent to forming the protective region layer of the second region, the protective gate liner maintaining uniformity of the gate electrode in the first region and the protective region layer maintaining integrity of an entirety of the second region during forming strain inducing material within the recessed regions; removing the protective region layer from the second region; removing the protective gate liner from the first and second regions; and forming source/drain regions within the first and second regions subsequent to removing the protective region layer and the protective gate liner.