Patent ID: 7299458
Filing Date: 2007-11-20
Classification: G06F

Abstract:
1. A method of forming a control-dataflow graph comprising: separating a control flow graph into two or more basic blocks; and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph and wherein nodes in the control-dataflow graph represent functional units and directed edges between the nodes represent data connections that bring output data items from one functional unit to the inputs of other functional units portioning the control-dataflow graph into a reconfigurable hardware portion and an instruction processor portion wherein the reconfigurable hardware portion is converted into a bit-stream data file that can be loaded into individual circuits in a reconfigurable processor and wherein the instruction processor portion is converted into an instruction processor object file; and linking together the bit-stream data file and the instruction processor object file to form a unified executable capable of configuring the reconfigurable processor to run a high level language.