Patent ID: 7885368
Filing Date: 2011-02-08
Classification: H03L

Abstract:
1. A circuit, comprising: a phase detector circuit to receive an input frequency signal and a fedback output frequency signal and to generate at least one phase error signal to indicate a phase relationship between said input and output frequency signals; a phase interpolator to generate the output frequency signal; and a control circuit coupled to the phase interpolator and to the phase detector to control the phase of the output frequency signal based on the at least one phase error signal, the control circuit comprising first and second charge pumps coupled to the at least one phase error signal to generate first and second control signals coupled to the phase interpolator to control the phase of the output frequency signal, wherein the first charge pump is coupled to a first phase direction signal from the phase detector and the second charge pump is coupled to a second phase direction signal from the phase detector, and the control circuit is to control the first control signal based on the sign of the second control signal and to control the second control signal based on the sign of the first control signal.