Patent ID: 9105669
Filing Date: 2015-08-11
Classification: B82Y,H01L

Abstract:
1. A quantum interference metal oxide semiconductor transistor device, comprising a. a semiconductor film comprising n-type source and drain regions or p-type source and drain regions and an n-type channel between said source and drain regions; b. a single protrusion having a width w greater than its height a formed integrally with and extending outwardly from a surface of said semiconductor film located between said source and drain regions, wherein the width of said protrusion terminates with walls perpendicular to said surface and edges of said walls are sharp; c. a layer of an insulating material disposed on a surface of said protrusion outwardly of said semiconductor film contiguous with said protrusion and having a width equal to the width w of said protrusion; d. a layer of a conducting material contiguous with and completely covering said layer of insulating material to form a gate having a width equal to said width w; e. electrical contacts connecting said source region of said semiconductor film to said gate adapted to allow a gate voltage V f. a gate regulated potential energy barrier formed in said semiconductor film channel below said protrusion when said gate voltage is applied, wherein an amount of energy E required for an electron moving through a region of increased Fermi level below said protrusion to overcome the potential energy barrier below said protrusion and continue to move through said channel to the drain region is represented by equation (1): wherein E F is a Fermi level of said semiconductor, ΔE F is a potential energy barrier increased height due to increased Fermi level, and ε/2 is band gap width.