Patent ID: 6233213
Filing Date: 2001-05-15
Classification: G11B,H03M

Abstract:
A method of converting first and second channel bits, modulated by first and second modulation schemes complying with first and second RLL constraints, to first and second output bits respectively, comprising the steps of:(a) identifying a modulation scheme of said first or second channel bits;(b) if said first channel bits are identified in said identifying step (a), then generating said first output bits for representing patterns that correspond to a plurality of patterns represented by said first channel bits other than those patterns being unable to exist under said first RLL constraints, said first output bits having a lesser number of bits than said first channel bits; and(c) if said second channel bits are identified in said identifying step (a), then generating said second output bits for representing patterns that correspond to a plurality of patterns represented by said second channel bits other than those patterns being unable to exist under said second RLL constraints, said patterns represented by said second output bits being located at discontinuous areas of said patterns represented by said first output bits, said second output bits having a lesser number of bits than said second channel bits.