Patent ID: 8159377
Filing Date: 2012-04-17
Classification: H03M

Abstract:
1. A method of estimating timing skew, comprising: performing, on the output of a plurality of interleaved analog-to-digital converter circuits (ADCs), including a reference ADC, a gradient loop from a block of samples of a particular size, the gradient loop including: determining an initial estimate of a timing skew of each of the plurality of ADCs, except the reference ADC, as the product of a function of the gradient of each of the plurality of ADCs, except the reference ADC, and a step size; correcting the output of each of the plurality of ADCs, except the reference ADC, based on the initial estimate of the timing skew of each of the plurality of ADCs, except the reference ADC; and determining a converged estimate of the timing skew of each of the plurality of ADCs, except the reference ADC, by: