Patent ID: 6700187
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A semiconductor package comprising:a semiconductor die having opposed first and second surfaces, a peripheral edge, and a plurality of bond pads disposed on the second surface in close proximity to the peripheral edge; a plurality of leads positioned along and in spaced relation to the peripheral edge of the semiconductor die, each of the leads having: a first surface; a second surface disposed in opposed relation to the first surface; and a third surface disposed in opposed relation to the second surface and oriented between the first and second surfaces; a plurality of conductive bumps electrically and mechanically connecting the bond pads of the semiconductor die to the third surfaces of respective ones of the leads; and an encapsulating portion applied to and at least partially encapsulating the leads, the semiconductor die, and the conductive bumps such that the first and third surfaces of each of the leads are covered by the encapsulating portion and the second surface of each of the leads is exposed therein.