Patent ID: 7889825
Filing Date: 2011-02-15
Classification: G09G,H03M,H04L

Abstract:
1. A sampling clock adjusting device of a sampling circuit, comprising: a difference calculator coupled to the sampling circuit for calculating a plurality of differences between adjacent sampled values of a plurality of sampled values, which are generated from the sampling circuit by sampling an incoming signal based on a sampling clock; a computing unit coupled to the difference calculator for generating a calculated value according to the plurality of differences, which include a first difference with a first absolute value and a second difference with a second absolute value less than the first absolute value, wherein the calculated value is derived from at least a first portion and a second portion, the first portion is contributed by the first difference, the second portion is contributed by the second difference, and a first ratio of the first portion to the second portion is greater than a second ratio of the first absolute value to the second absolute value; and an adjusting circuit coupled to the computing unit and the sampling circuit for adjusting a phase of the sampling clock so that the calculated value generated by the computing unit satisfies a predetermined condition.