Patent ID: 6693818
Filing Date: 2004-02-17
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:first to eighth bit lines; a plurality of memory cells being connected to the first to eighth bit lines, first to eighth column selection transistors, one of a source and drain of each of the first to eighth column selection transistors being connected to a corresponding one of the first to eighth bit lines; ninth to twelfth column selection transistors, one of a source and drain of the ninth column selection transistor being connected to the other of the source and drain of each of the first and second column selection transistors, one of a source and drain of the tenth column selection transistor being connected to the other of the source and drain of each of the third and fourth column selection transistors, one of a source and drain of the eleventh column selection transistor being connected to the other of the source and drain of each of the fifth and sixth column selection transistors, one of a source and drain of the twelfth column selection transistor being connected to the other of the source and drain of each of the seventh and eighth column selection transistors; first and second sense amplifiers, the first sense amplifier being connected to the other of the source and drain of each of the ninth and tenth column selection transistors, and the second sense amplifier being connected to the other of the source and drain of each of the eleventh and twelfth column selection transistors, a first column selection line being connected to gates of the first, third, fifth and seventh column selection transistors, a second column selection line being connected to gates of the second, fourth, sixth and eighth column selection transistors, and third to sixth column selection lines being connected to gates of the ninth to twelfth column selection transistors, respectively.