Patent ID: 6539052
Filing Date: 2003-03-25
Classification: H03G,H03M,H04B,H04L

Abstract:
In a radio frequency transceiver having a digital signal processing circuit including a demodulator circuit for demodulating received digital signals and a modulator circuit for modulating digital signals for transmission, a system for reducing the transceiver down time when switching between different modes of operation when the transceiver is neither transmitting nor receiving, comprising:a clock circuit for the transceiver having a first output clock rate for use during transceiver operation, and a second output clock rate for use when switching between different modes of operation when the transceiver is neither transmitting nor receiving, that has a higher clock rate than the first clock rate, and a control circuit responsive to mode switching commands for substituting the second clock rate for the first clock rate for a predetermined period of time to accelerate the processing of digital signals by the digital processing circuit during the process of switching between modes of operations when the transceiver is neither transmitting nor receiving.