Patent ID: 6643820
Filing Date: 2003-11-04
Classification: G11B

Abstract:
A method for controlling a timing recovery PLL that matches the phase of a clock signal with the phase of a preamble data signal, wherein the preamble data signal is part of a read signal corresponding to data read from a recording medium, the method comprising the steps of:generating a computation read signal by performing a predetermined computation on the read signal; generating a first code data using the computation read signal; comparing the computation read signal and a first reference signal; generating a second code data using the computation read signal; selecting one of the first code data and the second code data on the basis of the comparison result; detecting a phase error between the clock signal and the read signal by using the computation read signal and selected one of the first code data and the second code data; and matching the phase of the clock signal in accordance with the detected phase error.