Patent ID: 6046482
Filing Date: 2000-04-04
Classification: H01L

Abstract:
A mask read-only-memory cell structure for storing data information, the structure comprising:(a) a semiconductor substrate embodying a first type background impurity dopant;(b) a plurality of line regions in said substrate adjacent a top surface of the substrate embodying a second opposite type impurity dopant that constitute a plurality of bitlines;(c) an insulating gate layer over the surface of said substrate;(d) a plurality of insulating lines located on the substrate and aligned with said bitlines;(e) a plurality of conductive wordlines, arranged across said bitlines and over said substrate;(f) a plurality of conductive layers and individually contained between said insulating gate layer and underlying portions of said wordline;(g) a pattern of the cell state deposits of an insulating material, each cell state deposit region selectively located between one of said conductive layers and one of said underlying portions of said word lines, wherein said insulating material of the cell state deposits comprises silicon nitride.