Patent ID: 6362635
Filing Date: 2002-03-26
Classification: G01R

Abstract:
A system for testing an integrated circuit, comprising:a dense pad array having a first pad; a probe tip arrangement coupled to the first pad, the probe tip arrangement having a first probe tip resistor, an access transmission line, and a second probe tip resistor, the first probe tip resistor being adjacent to the first pad, the first probe tip resistor having a first end, a second end, and a first resistance, the first end of the first probe tip resistor being coupled to the first pad, the access transmission line being coupled to the second end of the first probe tip resistor, the access transmission line extending outside of the dense pad array, the second probe tip resistor being arranged outside the dense pad array and being coupled to the access transmission line, the second probe tip resistor having a second resistance, the first resistance and second resistance being configured to reduce conductor loading on the first pad.