Patent ID: 6391711
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method of forming an electrical connection between a stack capacitor and a node location of a substrate, comprising the steps of:forming dielectric material over said node location; depositing a mask layer over said dielectric material; patterning said mask layer to obtain a first opening thereof; etching said dielectric material toward said node location through said first opening until the thickness of said dielectric material left over said node location is in a specified range; expanding said first opening for forming a second opening thereof which is wider than said first opening; etching said dielectric material through said second opening to expose said node location, thereby forming a stud hole with a first end thereof at said node location, and with a second end thereof having a widest cross section relative to all the other parts of said stud hole; removing said mask layer; filling said stud hole with electrically conductive material to form a contact pedestal; and forming a stack capacitor structure which is at the second end of said stud hole and is electrically connected to said node location through said contact pedestal.