Patent ID: 6097766
Filing Date: 2000-08-01
Classification: H03L,H04L

Abstract:
A timing phase synchronization detecting circuit comprising:phase variation amount calculating means for entering thereinto a baseband phase signal of a burst signal constructed of a preamble which contains a ""0.pi."" modulation signal, and also a PSK-modulated random pattern; for differentiating said baseband phase signal sampled at a falling edge of a recovered symbol clock by 1 symbol; and furthermore for converting the 1-symbol-differentiated baseband phase signal into an absolute value thereof to calculate a phase variation amount;averaging means for executing an averaging process operation of a specific symbol of said phase variation amount; andcomparing means for comparing a signal outputted from said averaging means with a specific threshold value to thereby output a timing phase synchronization signal indicative of any one of the following states:such a condition (will be referred to as an ""UNLOCK condition"" hereinafter) that a timing phase difference between a rising edge of the recovered symbol clock and a Nyquist point of the baseband phase signal is large when the ""0.pi."" modulation signal is received; andsuch a condition (will be referred to as a ""LOCK condition"" hereinafter) that the rising edge of the recovered clock impinges at a position near the Nyquist point of the baseband phase signal, or either noise or the PSK-modulated random pattern is received.