Patent ID: 6492718
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A stacked semiconductor device comprising:a plurality of stacked wiring substrates each including a plurality of via-holes in which first connection electrodes are formed and first wires electrically are connected to the first connection electrodes; an uppermost wiring substrate stacked on a top of the stacked wiring substrates and including a plurality of via-holes in which second connection electrodes are formed and second wires are electrically connected to the second connection electrodes; a plurality of semiconductor devices mounted on the respective wiring substrates and electrically connected to the first wires thereof, a plurality of conductive via insulation substrates each having a cavity which is larger than the semiconductor device enclosed therein and each including a plurality of via-holes in which third connection electrodes are formed, one of the conductive via insulation substrates being stacked on one of the stacked wiring substrates; and a plurality of conductive layers formed on a top surface of the uppermost wiring substrate and/or a bottom surface of a lowermost wiring substrate formed under the stacked wiring substrates, wherein an area of said plurality of conductive layers occupying at least one surface of said uppermost and lowermost wiring substrates ranges from 50% to 95%.