Patent ID: 7451420
Filing Date: 2008-11-11
Classification: G06F

Abstract:
1. A processor-implemented method for determining a plurality of reachable pins that are functionally connected to a network of a netlist that describes a programmable logic device (PLD) design, wherein the network and each reachable pin are functionally connected if a logical value of the network is equal to a logical value of the reachable pin during operation of the PLD design, the method comprising: inputting the netlist that describes the PLD design; inputting an identification of the network of the netlist; inputting characterization data for each of at least one repeater module, the characterization data specifying a first set of functionally connected pins including an input pin and at least one output pin of the repeater module, the repeater module repeating a logical value from the input pin at the at least one output pin; initializing a second set with a plurality of pins of the network; for each pin in the second set that is one of the functionally connected pins of the first set of one of the at least one repeater module, adding to the second set an additional pin, which is not already included in the second set, for each of a plurality of pins of a network for each of the functionally connected pins of the first set of the one of the at least one repeater module, and repeating the adding for each additional pin added to the second set that is one of the functionally connected pins of the first set of one of the at least one repeater module; and outputting a specification of the pins from the second set as the reachable pins.