Patent ID: 6867957
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. A cascaded-transistor electro-static-discharge (ESD) protected output buffer comprising: a pull-down cascade between a pad and a ground bus having in series at least a first n-channel transistor and a second n-channel transistor that share an intermediate source/drain node, the pull-down cascade for sinking current from the pad to the ground bus through a first channel between a source and a drain of the first n-channel transistor and through a second channel between a source and a drain of the second n-channel transistor; a coupling capacitor between the pad and a coupled node; and an ESD switch, activated by an ESD pulse applied to the pad and responsive to the intermediate source/drain node, for shunting the pad to the ground bus in response to the ESD pulse coupled to the intermediate source/drain node; wherein the ESD switch comprises; a second trigger gate in series with the first trigger gate, the second trigger gate being coupled to the pad by a coupling capacitor; whereby the intermediate source/drain node triggers the ESD switch to shunt the pad to the ground bus during the ESD pulse.