Patent ID: 6304921
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A serial peripheral interface, comprising:one or more first storage elements serially coupled between an input and an output, wherein the input is coupled for receiving a data signal;one or more second storage elements serially coupled between an input and an output, wherein the input of the one or more second storage elements is coupled to the output of the one or more first storage elements;a device coupled to the input of the second storage elements for establishing a logic level at the input of the second storage elements for providing a first portion of an address for the second storage elements;wherein each of the one or more first storage elements and second storage elements comprises a plurality of serially connected clocked storage devices having a terminal for receiving a clock signal; andlogic means within each of the one or more first storage elements and each of the one or more second storage elements for receiving the data signal and inhibiting clocking of a portion of the plurality of serially connected clocked storage devices until address verification is performed by the logic means using one or more control bits within the data signal.