Patent ID: 8108590
Filing Date: 2012-01-31
Classification: G06F,G06K

Abstract:
1. A multi-channel fragment-accumulating flash-memory system comprising: a multi-channel controller processor coupled to receive host data and a host address; a plurality of channels of flash memory coupled to the multi-channel controller processor; a plurality of Aggregating Flash Blocks (AFBs), including an AFB in each channel of the flash memory, the AFB being a physical block of the flash memory assigned for aggregating data fragments; a page buffer for each channel that accumulates a page of the host data before writing to the flash memory; an AFB tracking table having entries for the plurality of AFBs, an entry storing a physical block number that locates the AFB within the flash memory, a data valid flag indicating when the AFB is storing valid data, and a stored logical address; a multi-AFB manager that compares the host address to the stored logical address in entries in the AFB tracking table to locate a matching entry in the AFB tracking table, the multi-AFB manager assigning an assigned AFB pointed to by the physical block number of the matching entry; a combining process executed by the multi-channel controller processor when a page boundary of the page buffer is reached, the matching entry in the AFB tracking table is found by the multi-AFB manager, and the page buffer is not full, the combining process copying the host data in the page buffer and a data fragment read from the assigned AFB to a target physical block in the flash memory, whereby the data fragment stored in the assigned AFB is combined with the host data in the page buffer when writing to the target physical block.