Patent ID: 8427416
Filing Date: 2013-04-23
Classification: G09G,G11C

Abstract:
1. A display panel, comprising: a substrate; a pixel array disposed on the substrate; a plurality of first shift registers disposed on the substrate for outputting a plurality of first scanning signals sequentially; and a plurality of second shift registers disposed on the substrate for outputting a plurality of second scanning signals sequentially, wherein a j a first transistor, a first terminal of the first transistor being coupled to a control terminal of the first transistor; a second transistor, a first terminal of the second transistor being coupled to the first terminal of the first transistor, a second terminal of the second transistor being coupled to a second terminal of the first transistor; a third transistor, a first terminal of the third transistor being coupled to the second terminal of the first transistor, a second terminal of the third transistor being coupled to a gate low voltage; a fourth transistor, a first terminal of the fourth transistor being coupled to the second terminal of the first transistor, a second terminal of the fourth transistor being coupled to the gate low voltage; a fifth transistor, a first terminal of the fifth transistor being coupled to a control terminal of the fourth transistor, a second terminal of the fifth transistor being coupled to the gate low voltage, a control terminal of the fifth transistor being coupled to the second terminal of the first transistor; a sixth transistor, a control terminal of the sixth transistor being coupled to the second terminal of the first transistor; a seventh transistor, a first terminal of the seventh transistor being coupled to a second terminal of the sixth transistor, a second terminal of the seventh transistor being coupled to the gate low voltage, a control terminal of the seventh transistor being coupled to the control terminal of the fourth transistor; an eighth transistor, a first terminal of the eighth transistor being coupled to the second terminal of the sixth transistor, a second terminal of the eighth transistor being coupled to the gate low voltage; a ninth transistor, a first terminal of the ninth transistor being coupled to the second terminal of the sixth transistor, a second terminal of the ninth transistor being coupled to the gate low voltage; a first capacitor, coupled between a first terminal of the sixth transistor and the first terminal of the fifth transistor; and a second capacitor, coupled between the second terminal of the sixth transistor and the control terminal of the sixth transistor, wherein, in a 1 wherein, in a 2j wherein, in a (2j+1)