Patent ID: 6306777
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method of fabricating a flash memory semiconductor apparatus, said method comprising the steps of:a. providing a semiconductor substrateb. fabricating a silicon dioxide layer on at least one region of said substrate member;c. depositing a silicon material over said silicon dioxide layer;d. forming said silicon material and said silicon dioxide layer into at least one partial stack portion of a flash memory element, said silicon material formed into said at least one stack portion comprising a first polysilicon layer of said flash memory element;e. forming a bottom interpoly dielectric stack member over said first polysilicon layer;f. forming a post-treatment layer over said bottom interpoly dielectric stack member;g. forming at least one other itnerpoly dielectric stack member over said post-treatment layer;h. forming a second polysilicon layer over said interpoly dielectric member;wherein said forming steps e, f, and g comprise:forming a multi-layered interpoly dielectric member, said multi-layered interpoly dielectric member being formed such that said pre-interpoly dielectric treatment layer facilitates a thickness decrease ranging from 5 .ANG. to 30 .ANG. for said dielectric member, thereby increasing a capacitor coupling ration from 5% to 10% and lowering a power supply programming voltage by 2 to 10%.