Patent ID: 6549029
Filing Date: 2003-04-15
Classification: G01R

Abstract:
A circuit for measuring a capacitance of a capacitive load, comprising:a first type-1 MOS transistor, wherein a source of the first type-1 MOS transistor is coupled to a first power source; a second type-1 MOS transistor, wherein a source of the second type-1 MOS transistor is coupled to a second power source, and a first input voltage is applied to the gates of the first and the second type-1 MOS transistor; a first type-2 MOS transistor, wherein a source of the first type-2 MOS transistor is coupled to a third power source, and the drain of the first type-2 MOS transistor is coupled to the drain of the first type-1 MOS transistor; a second type-2 MOS transistor, wherein the source of the second type-2 MOS transistor is coupled to the third power source, and the drain of the second type-2 MOS transistor is coupled to the drain of the second type-1 MOS transistor, and a second input voltage is applied to the gates of the first and the second type-2 MOS transistor; a capacitive load coupled between the drains of the first and the second type-1 MOS transistors; and a pad, coupled to the drain of the second type-1 MOS transistor.