Patent ID: 8115524
Filing Date: 2012-02-14
Classification: G06F

Abstract:
1. A semiconductor device, comprising: a clock input block configured to generate a system clock and a data clock; a clock division block configured to divide the data clock to generate a data division clock, wherein the data division clock is inverted in response to a division control signal; a phase multiplex block configured to generate a plurality of multiple data division clocks having a predetermined phase different from each other in response to the data division clock; a logic level control block configured to set a period, in which a logic level of the division control signal is changeable, depending on a toggling of the data division clock; and a first phase detection block configured to detect a phase of the system clock on the basis of selected clocks of the plurality of multiple data division clocks in the period set by the logic level control block, and to generate the division control signal corresponding to a detection result.