Patent ID: 8725953
Filing Date: 2014-05-13
Classification: G06F,Y02D

Abstract:
1. A method of processing data comprising the steps of: executing respective processing tasks with a plurality of processors responsive to respective streams of program instructions; storing data within a plurality of local cache memories, each of said memories coupled to a respective one of said plurality of processors; maintaining coherency between data stored within said plurality of local cache memories using a cache coherency controller coupled to said plurality of local cache memories; switching, in response to a power down request for at least one of said plurality of processors, said at least one processor to a processor low power state; and maintaining, in response to said power down request for said at least one processor, power to at least one of said local cache memories such that said cache coherency controller continues to have access to data stored within said at least one local cache memory until a predetermined condition is met, wherein meeting of said predetermined condition triggers switching of said at least one local cache memory to a cache low power state in which said data is no longer accessible from said at least one local cache memory, wherein, after said predetermined condition is met, said local cache memory is flushed of any remaining dirty data before being switched to said cache low power state.