Patent ID: 6939763
Filing Date: 2005-09-06
Classification: H01L

Abstract:
1. A method for fabricating a DRAM cell arrangement with vertical MOS transistors, comprising: forming a source/drain material on a substrate; etching trenches to form a plurality of parallel ribs having strips of the source/drain material disposed thereon, wherein the strips provide sites for a plurality of upper source/drain regions of the vertical MOS transistors; depositing a covering layer on a floor of the trenches; depositing a gate dielectric layer on the surfaces of the ribs; filling the trenches whereby gate electrodes for the vertical MOS transistors are produced on either side of the ribs; forming a plurality of word lines over, and cross-wise with respect to, the ribs; depositing a first auxillary layer, capable of wafer bonding, on the plurality of word lines; attaching a first auxiliary carrier substrate to the first auxiliary layer; removing at least the substrate; forming a plurality of lower source/drain regions on the ribs, wherein portions of the ribs disposed between the plurality of lower source/drain regions and the plurality of upper source/drain regions define channel regions for the vertical MOS transistors; and forming shallow isolation trenches to isolate the plurality of lower source/drain regions.