Patent ID: 8219754
Filing Date: 2012-07-10
Classification: G06F,Y02D

Abstract:
1. A self-configuring cache architecture for a digital signal processor, comprising a computational unit, the computational unit comprising: an execution-space decode logic circuit that (i) dynamically determines, during run-time execution of an executable program, whether a current instruction in the executable program is coming from an external memory or an internal memory and (ii) outputs an external execution-space control signal if the current instruction is coming from the external memory and outputs an internal execution-space control signal if the current instruction is coming from the internal memory; and a cache control logic circuit that configures a cache memory to store, in a traditional cache space, a conflict-free instruction from the external memory or to store, in a conflict cache space, a conflicted instruction from the internal memory based on an outcome of the determination, wherein the cache control logic circuit transfers the current instruction to and between the cache memory, the internal memory, and the external memory based on the configuration of the cache memory, thereby avoiding a pipeline stall during a next use of the current instruction, the cache control logic circuit comprising: