Patent ID: 9064723
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate including a first region and a second region; a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, wherein the first lower gate electrode is in direct contact with the first upper gate electrode, and wherein an undercut region is defined by a bottom surface of the first upper gate electrode and at least one of the first sidewall and the second sidewall of the first lower gate electrode; a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, wherein the second lower gate electrode is in direct contact with the second upper gate electrode; a first spacer disposed on a sidewall of the first upper gate electrode; a second spacer disposed on a sidewall of the second upper gate electrode; a third spacer covering the first spacer on the sidewall of the first upper gate electrode, wherein the third spacer extends into the undercut region; a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode and a plurality of device isolation layers defining an active region, wherein the undercut region is further defined by a sidewall of the first gate dielectric layer and a top surface of the plurality of device isolation layers, wherein at least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer, wherein the third spacer is in contact with a bottom surface of the first upper gate electrode, wherein the plurality of device isolation layers includes a first device isolation layer and a second device isolation layer, wherein both of the first and second sidewalls of the first lower gate electrode are overlapped with the first device isolation layer and the second device isolation layer, respectively, and wherein the undercut region is confined by at least one of the first and second sidewalls of the first lower gate electrode.