Patent ID: 6734049
Filing Date: 2004-05-11
Classification: G02F,H01L

Abstract:
A method of fabricating an array substrate for an active matrix type liquid crystal display (LCD) device, the method comprising:a) forming a plurality of parallel, spaced apart gate lines, each gate line having a gate pad on an end, on a substrate by depositing a first metal layer on the substrate and then patterning the first metal layer using a first mask; b) forming a gate insulating layer, a semiconductor layer, an ohmic contact layer, and a second metal layer by sequentially depositing a first insulating material, a semiconductor material, a doped semiconductor layer, and a metallic material on the substrate; c) forming a plurality of data lines having data pads, a plurality of source electrodes, and a plurality of drain electrodes by patterning the second metal layer using a second mask, wherein the data lines cross the gate lines, wherein said source electrodes extend from the data lines adjacent the crossings of the gate lines and the data lines, and wherein the drain electrodes are spaced apart from the source electrodes; d) forming a plurality of channel regions by etching portions of the ohmic contact layer using the patterned second metal layer as a mask, wherein the channel regions are defined on the semiconductor layer between source and the drain electrodes; e) depositing a second insulating layer on the structure that results from step d); f) patterning the second insulating layer to form a passivation layer having a plurality of data pad contact holes that expose data pads and a plurality of drain contact holes that expose drain electrodes, wherein the passivation layer covers the patterned second metal layer and a peripheral portion of the gate lines; and g) forming a plurality of pixel electrodes, data pad electrodes, and gate pad electrodes by depositing a transparent conductive layer on the passivation layer, and then patterning the transparent conductive layer using a fourth mask, wherein portions of the pixel electrodes overlap peripheral portions of gate lines, wherein the pixel electrodes electrically connect with drain electrodes via the drain contact holes, wherein the data pad electrodes electrically connected with data pads via the data pad contact holes, and wherein the gate pad electrodes electrically connect with the gate pads via the gate pad contact holes.