Patent ID: 8698289
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: (a) a semiconductor chip having a quadrangular shape and having a main surface over which a first electrode pad and a second electrode pad are formed, a back surface over which a third electrode is formed opposite the main surface, a first side, a second side which intersects the first side, a third side opposite the first side, and a fourth side opposite the second side; (b) a first metal conductor having a first obverse surface, a first reverse surface opposite the first obverse surface, a first portion located over the first electrode pad of the semiconductor chip and extending in a first direction and a second direction perpendicular to the first direction, a third portion whose first reverse surface is located under the first reverse surface of the first portion in a thickness direction of the semiconductor chip, and a second portion located between the first and third portions in the first direction and interconnected with the first and third portions, wherein the first reverse surface of the first portion of the first metal conductor is electrically connected to the first electrode pad of the semiconductor chip via a first conductive adhesive, and wherein, in a plan view of the main surface of the semiconductor chip, the first portion of the first metal conductor overlaps with a part of each of the first to fourth sides: (c) a second metal conductor having a second obverse surface, a second reverse surface opposite the second obverse surface, a fourth portion located over the second electrode pad of the semiconductor chip and extending in the first direction, a sixth portion whose second reverse surface is located under the second reverse surface of the fourth portion in the thickness direction, and a fifth portion located between the fourth and sixth portions in the first direction and interconnected with the fourth and sixth portions, wherein the second reverse surface of the fourth portion is electrically connected to the second electrode pad of the semiconductor chip via a second conductive adhesive, and wherein, in the plan view, the fourth portion of the second metal conductor overlaps with a different part from the part with which the first portion of the first metal conductor overlaps of the first side and a part of the second sides and does not overlap with the third and fourth sides of the semiconductor chip; (d) a third metal conductor having a third obverse surface over which the semiconductor chip is mounted such that the back surface of the semiconductor chip faces to the third obverse surface and a third reverse surface opposite the third obverse surface, the third obverse surface being electrically connected to the third electrode of the semiconductor chip; and (e) a sealing body having a top surface and a bottom surface opposite the top surface, and sealing the semiconductor chip, the second portion of the first metal conductor, the fifth portion of the second metal conductor, and the third obverse surface of the third metal conductor, wherein a part of the first obverse surface of the first portion of the first metal conductor is exposed from the top surface of the sealing body, wherein the second obverse surface of the fourth portion of the second metal conductor is located under the first obverse surface of the first portion of the first metal conductor and sealed with the sealing body, wherein a part of each of the first reverse surface of the third portion of the first metal conductor, the second reverse surface of the sixth portion of the second metal conductor, and the third reverse surface of the third metal conductor is exposed from the bottom surface of the sealing body, and wherein, in the plan view, the second electrode pad of the semiconductor chip is located in an area provided by the first portion of the first metal conductor and the first and second sides of the semiconductor chip.