Patent ID: 9152517
Filing Date: 2015-10-06
Classification: G01R,G06F

Abstract:
1. A test equipment apparatus for providing interrupt capability for automatic testing, comprises: a computer coupled to memory, the computer being responsive to computer-executable instructions contained in the memory; and a test socket coupled to a device under test for the automatic testing and coupled to the computer; wherein the computer is configured to interrupt an application pattern running on the device under test according to the automatic testing; wherein in response to interrupting the application pattern, the computer is configured to cause a control pattern to run on the device under test according to the automatic testing; wherein in response to completion of the control pattern, the computer is configured to cause the application pattern to restart running from the point of interruption on the device under test according to the automatic testing; wherein the computer is configured to switch, according to a duty cycle for the automatic testing of the device under test, between the application pattern that runs an amount of computational operations and the control pattern that runs a smaller amount of computational operations compared to the application pattern; wherein the duty cycle for the automatic testing of the device under test corresponds to a length of time for the application pattern running the amount of computational operations and also corresponds to a different length of time for the control pattern running the smaller amount of computational operations; wherein when executing the automatic testing under a worst case scenario for the device under test, respective duty cycles are calculated for a first application pattern, a second application pattern, a third application pattern through a last application pattern in order to run each of the first through the last application patterns for their respective duty cycles; wherein the computer is configured to execute the automatic testing for the device under test comprising at least one of a chip, a processor core, and a memory.