Patent ID: 7262635
Filing Date: 2007-08-28
Classification: G06F,H03K

Abstract:
1. A programmable logic integrated circuit device comprising: a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns; a plurality of interconnection conductors associated with each of the rows and configured to convey signals to, from, and/or between the logic regions in the associated row; a first programmable logic connector associated with a first plurality of interconnection conductors associated with a first row of the plurality of regions of programmable logic, the first programmable logic connector configured to selectively apply an output signal of a first region of programmable logic of the first row substantially directly to a conductor of the first plurality of interconnection conductors; and a second programmable logic connector associated with a second plurality of interconnection conductors associated with a second row of the plurality of regions of programmable logic, the second programmable logic connector configured to selectively apply an output signal of the first region substantially directly to a conductor of the second plurality of interconnection conductors.