Patent ID: 6506632
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A method of forming an integrated circuit package having a downward facing chip cavity, comprising the steps of:providing a substrate consisting of an insulating core layer and a conductive layer, wherein the conductive layer is attached to the lower surface of the insulating core layer; forming a first opening in the substrate such that the first opening penetrates the insulating core layer and the conductive layer; attaching an adhesive tape over the conductive layer so that the first opening exposes a portion of the upper surface of the adhesive tape; attaching a silicon chip to the exposed adhesive tape inside the first opening, wherein the silicon chip has an active surface and a backside surface, the active surface further includes a plurality of bonding pads while the backside of the silicon chip adheres to the adhesive tape so that the chip is fixed in position; forming a patterned dielectric layer that fills the first opening and covers a portion of the adhesive tape, the active surface, the bonding pads of the silicon chip and the insulating core layer, wherein the patterned dielectric layer further includes a plurality of second openings and a plurality of third openings, the second openings expose the bonding pads and the third openings pass through the patterned dielectric layer, the insulating core layer and the conductive layer; conducting an electroplating operation to form a metallic layer over the exposed surface of the second openings, the third openings and the patterned dielectric layer; patterning the metallic layer and the conductive layer to form a patterned metallic layer and a patterned conductive layer respectively; forming a patterned solder resistant layer over the patterned metallic layer and the patterned conductive layer, wherein the patterned solder resistant layer has a plurality of fourth openings that expose a portion of the patterned conductive layer; and planting a solder ball on each fourth opening and heating the solder ball to form electrical contact between the solder ball and the patterned conductive layer.