Patent ID: 7671646
Filing Date: 2010-03-02
Classification: H03K

Abstract:
1. A digital duty cycle correction (DCC) circuit of a delay locked loop (DLL), comprising: a duty correction circuit for correcting a duty of a internal clock and outputting an output clock; a phase divider for generating a first clock having the same phase as that of the output clock and a second clock having an opposite phase to that of the first clock in response to the output clock; a compare control unit for generating a pump reset signal and a compare control signal in response to the output clock; a DCC pump for pumping the first clock and the second clock and generating a first pumping clock and a second pumping clock in response to the pump reset signal; a voltage comparator for sensing the compare control signal and the voltage levels of the first pumping clock and the second pumping clock and generating an increment/decrement signal; a counter for outputting a counter signal in response to the increment/decrement signal; and a voltage generator for generating a voltage in response to the counter signal.