Patent ID: 7020334
Filing Date: 2006-03-28
Classification: G06K

Abstract:
1. A circuit for extracting a connected component feature, comprising: an input stage configured to receive an input pattern that can include a plurality of bits in a row and detect as a connected component a contiguous set of one or more of the plurality of bits in the row; a counting stage, coupled to the input stage, configured to count a number of the connected components detected in the input stage and generate a current representing the number of the connected components; a bit-preparing stage, coupled to the counting stage, configured to generate a plurality of currents as a basis for bit-information including more than one bit, based on the current generated in the counting stage, the bit-information uniquely representing the number of the connected components; and an output stage, connected to the bit-preparing stage, configured to convert the plurality of currents generated in the bit-preparing stage into a digital output corresponding to the bit-information.