Patent ID: 6248653
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method of manufacturing a gate structure comprising the steps of:(a) forming a conductor through a gate insulating film, on a semiconductor substrate; said conductor being composed mainly of a semiconductor;(b) forming a first oxide film on said conductor;(c) oxidizing the side of said conductor;(d) forming a second oxide film so as to cover said first oxide film; said second oxide film being an oxide film of a semiconductor; and said first oxide film has a higher impurity concentration than an oxidized side of said conductor and said second oxide film(e) performing a CMP planarization process from said second oxide film side of said semiconductor substrate, thereby to expose said first oxide film;(f) performing, to the structure obtained by said step (e), an etching process using a vapor phase hydrofluoric acid, thereby to selectively remove said first oxide film; and(g) forming a metal film in the region surrounded by said second oxide film and said conductor.