Patent ID: 7958411
Filing Date: 2011-06-07
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a nonvolatile memory including a plurality of blocks as data erase units; a measuring unit which measures an erase time at which data in each block is erased; a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block; a detector which detects blocks in each of which rewrite has frequently occurred within a short period; a first selector which selects a free block having an old erase time as a first block, on the basis of an information in the block table; a second selector which selects a block in use having an old erase time as a second block, on the basis of the information in the block table; and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.