Patent ID: 8773996
Filing Date: 2014-07-08
Classification: H04J,H04L,H04M

Abstract:
1. A system for passing Time Division Multiplexed (TDM) traffic through a packet switch, comprising a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the packet switch routing FSDU packets within the packet switch based on header information within respective FSDU packets; a TDM encapsulation circuit coupled to a data flow of TDM data and having a circuit demultiplexer for processing an incoming data flow of TDM data to buffer data associated with different TDM circuits into different buffer locations, a timer for monitoring a frame boundary, a FSDU generator for generating an FSDU and filling the generated FSDU with data associated with a respective one of the TDM circuits and for generating the header information for allowing the packet switch to route the generated FSDU to a port associated with the respective one of the TDM circuits; a bandwidth allocation process for allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing FSDU traffic through the packet switch; and a jitter buffer for receiving the generated FSDU traffic with the predetermined latency period, the jitter buffer further for reducing variable delays in the FSDU traffic, wherein the jitter buffer has a size selected as a function of a minimum and maximum latency of the FSDU traffic; wherein the jitter buffer has a size selected to maintain jitter below 125 microseconds.