Patent ID: 9047803
Filing Date: 2015-06-02
Classification: G09G

Abstract:
1. A gate drive circuit comprising a signal circuit in which a plurality of driving stages is coupled to each other sequentially, the plurality of driving stages outputting a plurality of gate signals to first terminals of a plurality of gate lines, an n-th driving stage, comprising: a pull-up part configured to output an ON voltage of a first clock signal as an ON voltage of an n-th gate signal, where n is a positive integer; a carry part configured to output an ON voltage of the first clock signal as an ON voltage of an n-th carry signal; a first pull-down part configured to pull down an ON voltage of the n-th gate signal into a first OFF voltage in response to at least one output signal of a previous driving stage and at least one output signal of a following driving stage; a first pull-up/down control part configured to apply a first power signal of an ON voltage to a control terminal of the pull-up part in a forward direction mode, and to apply a first power signal of a second OFF voltage to the control terminal of the pull-up part in a reverse direction mode, in response to the at least one output signal of the previous driving stage; a second pull-up/down control part configured to apply a second power signal of the second OFF voltage to the control terminal of the pull-up part in the forward direction mode, and to apply the second power signal of the ON voltage to the control terminal of the pull-up part in the reverse direction mode, in response to the at least one output signal of the following driving stage; and an inverting part configured to output the first OFF voltage when the carry part outputs an ON voltage, and to output a signal synchronized with the first clock signal when the carry part outputs the second OFF voltage.