Patent ID: 6894518
Filing Date: 2005-05-17
Classification: G01R

Abstract:
1. A method for analyzing a semiconductor die having circuitry therein, the method comprising: applying an electric field to the die via an electric-field tool, separate from the die and using the applied electric field to stimulate circuitry in the die including scanning the electric-field tool across the die wherein prior to applying the electric field to the die, applying signals to inputs of the die and thereby operating the die; detecting a photoemission response of die to the applied electric field wherein detecting a photoemission response includes detecting responses from a plurality of circuit nodes in the die to both the applied signals and to the applied electric field; mapping the responses of the plurality of circuit nodes to a circuit diagram of the die and thereby forming a mapped image of the responses; and using the photoemission response to detect an electrical characteristic of the die including using the mapped image to detect electrical characteristics of at least one of the plurality of nodes.