Patent ID: 7301486
Filing Date: 2007-11-27
Classification: H03M

Abstract:
1. A time-interleaved analog-to-digital converter (ADC) having a timing calibration, said converter being a two-channel time-interleaved ADC, comprising: a calibration processor (CP); a multi-phase clock generator, said clock generator providing a first phase and a second phase; a clock random chopper, said clock random chopper receiving a phase from said clock generator to process a timing change; a first programmable delay unit, said first programmable delay unit receiving a first signal being processed through said timing change; a second programmable delay unit, said second programmable delay unit receiving a second signal being processed through said timing change, said second programmable delay unit receiving an output signal from said CP to process a timing-skew calibration; a first ADC, said first ADC receiving an output signal from said first programmable delay unit; a second ADC, said second ADC receiving an output signal from said second programmable delay unit; a data recovery chopper, said data recovery chopper recovering digital signals from said first ADC and said second ADC to be transferred to said CP; and a random sequence generator, said random sequence generator providing a random signal.