Patent ID: 6794715
Filing Date: 2004-09-21
Classification: H01L

Abstract:
An ESD protection circuit for protecting one or more semiconductor devices in an integrated circuit from damage caused by an ESD pulse, comprising:a first diffusion region having a first conductivity type formed at a surface of a substrate, said first diffusion region being a source or drain region associated with a MOS transistor fabricated on the substrate and having one or more notches at its respective edges; and at least one second diffusion region formed at said surface of said substrate and having a second conductivity type opposite to said first conductivity type, said at least one second diffusion region occupying a respective one of said one or more notches; wherein a pn junction formed between said first diffusion region and said second diffusion region breaks down in response to said ESD pulse thereby causing discharge current to flow across a portion of said substrate.