Patent ID: 6874070
Filing Date: 2005-03-29
Classification: G06F

Abstract:
1. A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space, the method comprising: providing at least one map table, the at least one map table including a plurality of entries, each entry including a plurality of entry items, each entry item identifying one of the memories; receiving a first logical address, the first logical address including a plurality of address bits, the plurality of address bits including a first set of address bits corresponding to a first set of entries in the at least one map table, wherein each entry in the first set includes entry items that are different than entry items of other entries in the first set; identifying a first entry in the first set of entries based on the first set and a second set of the address bits; identifying a first entry item in the first entry based on a third set of the address bits; and accessing the memory identified by the first entry item.