Patent ID: 8442074
Filing Date: 2013-05-14
Classification: H04J,H04L

Abstract:
1. A packet receiver, comprising: receive circuitry configured to receive packets from a packet network, the packets transmitted by a transmitter based on a first clock; a second clock; and a clock synchronization element configured to perform timing measurements, each of the timing measurements indicative of a packet delay for a respective one of the packets, the clock synchronization element having a non-linear filter and a loop filter, the non-linear filter configured to collect the timing measurements into groups and to filter the timing measurements based on packet delay, each of the groups associated with a respective sample period and comprising a plurality of the timing measurements for the associated sample period, wherein the non-linear filter, for each of the groups, is configured to sort the plurality of the timing measurements of the group based on packet delays indicated by the plurality of the timing measurements of the group, the non-linear filter further configured to select a respective timing measurement from each of the groups based on the sorting performed by the non-linear filter and to determine which of the selected timing measurements indicate packet delays within a specified range, the non-linear filter configured to transmit each of the selected timing measurements indicating packet delays within the specified range to the loop filter, wherein the loop filter is configured to update a frequency of the second clock based on the timing measurements transmitted to the loop filter by the non-linear filter such that the second clock is synchronous to the first clock.