Patent ID: 6925543
Filing Date: 2005-08-02
Classification: G11C

Abstract:
1. A burst transfer memory comprising: a first memory having a cell array arranged in a matrix; a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory; write and read data lines each connected to a corresponding column of the first and second memories: and an interface circuit which controls the first and second memories as one burst transfer memory, wherein the second memory cell array is arranged adjacent to the first memory cell array in a bit line direction of the first memory cell array, and wherein the interface circuit allocates addresses to the first and second memories as consecutive addresses, and the interface circuit substantially simultaneously starts a first random access to the first and second memories, accesses the second memory before a word line of the first memory is activated, and consecutively accesses a page of the first memory after the word line of the first memory has been activated, and wherein the number of columns in the first memory cell array in a word line direction thereof is equal to the number of columns in the second memory cell array in a word line direction thereof, and the first memory cell array is wider than the second memory cell array in the word line direction, and wherein a space portion is provided between the first and second memory cell arrays, and the same write and read data lines are connected to each column of the first and second memories, the write and read data lines including those bent in crank form at the position of the space portion.