Patent ID: 8201034
Filing Date: 2012-06-12
Classification: G11C

Abstract:
1. A memory device, comprising: a first storage block; a first PAD; a first reading and writing circuit, coupled to the first storage block and the first PAD, for reading data from the first storage block or writing data into the first storage block; the first reading and writing circuit having a first data read path and a first data write path; a second storage block; a second PAD; a second reading and writing circuit, coupled to the second storage block and the second PAD, for reading data from the second storage block or writing data into the second storage block; the second reading and writing circuit having a second data read path and a second data write path; a test circuit, coupled to the first reading and writing circuit and the second reading and writing circuit, for determining whether an error arises in the memory device; where the second PAD or the test circuit write at least a test data into the first storage block and the second storage block through the first data write path and the second data write path so that a plurality of first time written test data are stored in the first storage block and the second storage block; the plurality of first time written test data including a first writing test data and a second writing test data stored in the first storage block and the second storage block; and a control circuit, coupled to the first reading and writing circuit and the second reading and writing circuit, for controlling the first data read path and the second data read path to selectively transmit data read from the first storage block and the second storage block into the test circuit, the first PAD, or the second PAD, and for controlling the first data write path and the second data write path to selectively write data from the test circuit, the first PAD, or the second PAD into the first storage block and the second storage block; wherein when the memory device switches to a read with write back test mode, the control circuit controls the first data read path and the second data read path to read the first writing test data and the second writing test data from the first storage block and the second storage block and controls the first data write path and the second data write path to write the first writing test data and the second writing test data into the first storage block and the second storage block through the first data write path and the second data write path to generate a plurality of second time written test data including a third writing test data and a fourth writing test data stored in the first storage block and the second storage block; and when the memory device switches to a compress test mode, the control circuit controls the first data read path and the second data read path to read the third writing test data and the fourth writing test data from the first storage block and the second storage block and then transmits the third writing test data and the fourth writing test data into the test circuit, and the test circuit performs a compress test operation to determine whether an error arises in the memory device according to the third writing test data and the fourth writing test data and the test data.