Patent ID: 9148155
Filing Date: 2015-09-29
Classification: G06F,H03L

Abstract:
1. An integrated circuit having a plurality of phase-locked loops (PLLs) connected to a common input port, the integrated circuit, comprising: a first input port that receives a first external reference clock signal; a first PLL, connected to the first input port and having a first clock source specification, that receives the first external reference clock signal and generates a first clock signal; a second PLL, connected to the first input port and having a second clock source specification, that receives the first external reference clock signal and generates a second clock signal; a first circuit module connected to the first PLL and having a first clock source requirement, wherein the first circuit module receives the first clock signal; and a second circuit module connected to the second PLL and having a second clock source requirement different from the first clock source requirement, wherein the second circuit module receives the second clock signal, wherein the first and second PLLs are located at respective first and second routing distances from the first input port, wherein the first and second routing distances are less than respective first and second predetermined maximum routing distances such that the first and second clock source requirements are met, wherein the first and second clock source requirements each include at least one of a frequency, jitter, voltage swing, and duty cycle requirement of the first and second circuit modules respectively, a second input port that receives the first external reference clock signal; a third PLL, connected to the second input port and having a third clock source specification, that receives the first external reference clock signal by way of the second input port and generates a third clock signal; and a third circuit module, connected to the third PLL and having a third clock source requirement different from the first and second clock source requirements, that receives the third clock signal, wherein the third PLL is located at a third routing distance from the second input port, and wherein the third routing distance is less than a third predetermined maximum routing distance, such that the third clock source requirement is met, and wherein the third clock source requirement includes at least one of a frequency requirement, a jitter requirement, a voltage swing requirement, and a duty cycle requirement of the third circuit module, and wherein a routing distance between the first input port and the third PLL is greater than the third predetermined maximum routing distance.