Patent ID: 6411556
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a pair of row decoders; and a pair of memory blocks sandwiching said pair of row decoders therebetween, each of said pair of memory blocks including a plurality of normal memory cells arranged in a matrix of rows and columns and a plurality of redundant memory cells arranged at least in one row; a redundancy determining circuit for replacing, independently in each of said pair of memory blocks, a row of said normal memory cells including a defective memory cell by a row of said redundant memory cells; and a plurality of lines for applying respective ones of a plurality of address signals for selecting a row of said normal memory cells to said redundancy determining circuit; wherein said redundancy determining circuit includes a first redundancy determining circuit unit for the replacement in one of said pair of memory blocks, and a second redundancy determining circuit unit for the replacement in the other one of said pair of memory blocks; and said plurality of lines include a center line extending in an area between said first and second redundancy determining circuit units and connected to said first and second redundancy determining circuit units.