Patent ID: 6681316
Filing Date: 2004-01-20
Classification: G06F

Abstract:
A network of parallel elementary processors tolerant of the faults of these processors comprising said elementary processors (P), spare elementary processors (Sp), interconnecting elements (Cm) of these processors, and a control unit, characterized in that it comprises alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, with the processors lines being elementary processor lines, the last processor line being a spare elementary processor line, the edge network elements being interconnecting elements; and in that the control unit, connected to the processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors, wherein each processor (P) is connected to four interconnecting elements (Cm), two of these diametrically opposed elements being connected to the two inputs of processor (P), the other two elements, also diametrically opposed, being connected to the two outputs of processor (P), these interconnecting elements (Cm) being connected together through vertical or horizontal links.