Patent ID: 9170753
Filing Date: 2015-10-27
Classification: G06F,G11C

Abstract:
1. A method of providing memory accesses for a multi-core processor, comprising: reserving a group of pins of a multi-core processor to transmit either data or address information in communication with one or more memory chips, wherein the multi-core processor comprises a plurality of processor cores; receiving memory access requests from the plurality of processor cores; determining granularity of the memory access requests by a memory controller; dynamically adjusting, by the memory controller, a number of pins in the group of pins to be used to transmit address information based with the granularity of the memory access requests, forming queues of memory access requests each associated with accessing data in one of the memory chips; bundling memory access requests in different queues that share same target addresses in two or more memory chips, which produces bundled memory access requests; simultaneously transmitting the memory addresses to the two or more memory chips associated with the bundled memory access requests; and after the step of simultaneously transmitting the memory addresses, simultaneously transmitting data in the bundled memory access requests to the respective memory chips at the memory address.