Patent ID: 7733950
Filing Date: 2010-06-08
Classification: G11B,H03H,H04B

Abstract:
1. An equalizer comprising: a first biquad circuit including a first input node, a first biquad band pass node, and a first biquad low pass node; a second biquad circuit including a second input node connected to the first biquad low pass node, a second biquad band pass node, and a second biquad low pass node; a first summing circuit summing an output of the second biquad band pass node and an output of the second biquad low pass node; a second summing circuit subtracting an output of the first biquad low pass node from output of the first summing circuit and amplifying the summed result by a constant; and a third summing circuit summing up the output of the second summing circuit and the output of the second biquad low pass node,