Patent ID: 7259582
Filing Date: 2007-08-21
Classification: G01R,H01L

Abstract:
1. A first integrated circuit chip for packaging along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and the second integrated circuit chips, wherein the first and second integrated circuit chips are operable to be placed in stacked arrangement with the semiconductor device, the first integrated circuit chip comprising: a first chip select bonding pad for receiving a first chip select signal for selecting the first integrated circuit chip; a second chip select bonding pad for receiving a second chip select signal for selecting the second integrated circuit chip, wherein the second chip select bonding pad of the first integrated circuit chip is operable to be connected to a chip select bonding pad on the second integrated circuit chip when the first and second integrated circuit chips are packaged together, thereby avoiding a short to a connection for the first chip select signal.