Patent ID: 7380027
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A direct memory access controller that acquires one bus usage right from a CPU to perform one burst data transfer between a memory and a plurality of peripherals that is assigned to a plurality of direct memory access (DMA) channels, respectively, the direct memory access controller comprising: a channel select control unit that determines which DMA channels are active channels immediately before the direct memory access controller acquires the one bus usage right; a data quantity setting unit that determines, for each of the active channels, an amount of data to be transferred through each of the active channels in the one burst data transfer; and a data transfer control unit that performs the one burst data transfer which corresponds to the one bus usage right and in which a k-th data having a k-th amount determined by the data quantity setting unit and a k+1-th data having a k+1-th amount determined by the data quantity setting unit are sequentially transferred through a k-th active channel and a k+1-th active channel, respectively, where k is a positive integer, wherein the data quantity setting unit comprises: