Patent ID: 6635522
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method of forming a MOS transistor comprising:providing a semiconductor substrate of a first conductivity type; forming an insulated gate pattern having sidewalls on a predetermined region of the semiconductor substrate of the first conductivity type so that portions of the semiconductor substrate of the first conductivity type on at least one side of the insulated gate pattern remain uncovered by the gate pattern; forming impurity regions of a second conductivity type on the semiconductor substrate of the first conductivity type at the at least one side of the insulated gate pattern; forming a first interlayer insulating layer on the entire surface of the resultant structure having the impurity regions; forming pad contact holes by patterning the first interlayer insulating layer and by exposing at least a portion of the impurity regions; forming a conformal buffer layer on the entire surface of the resultant structure having the pad contact holes; and forming at least one pad by patterning the conformal buffer layer, whereby the at least one pad covers at least the impurity regions.