Patent ID: 6757857
Filing Date: 2004-06-29
Classification: G11C

Abstract:
A memory subsystem having an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test, comprisinga memory subsystem having a master controller for said memory subsystem having a memory comprising a plurality of commercial memory chips on a plurality of memory modules and having an Alternating Current Built-In-Self-Test (AC BIST) which writes pseudo-random patterns to memory, reads them back and compares the expected results at hardware speeds, including a data generation circuit which provides Built In Self Test data generation as a pseudo-random pattern generator using a series of linear feedback shift registers (LFSR) to provide a register bank equal to the width of the number of data query (DQ) pins to generate a pseudo-random pattern which is written to a commercial memory chip of one of said plurality of memory modules during Alternating Current Built In Self Test (AC BIST), an address generation circuit for providing Built In Self Test address generation for the the address space of said commercial memory chip during AC BIST, a comparison circuit for comparing the expected results, an array of configurable registers including read registers for providing said master controller information such as a seed value for the linear feedback shift registers (LFSR) of said data generation circuit, a starting address for address generation, and the addresses of any devices attached to said master controller, and wherein the results of an initial driver impedance adjustment, and the Alternating Current Built-In-Self-Test (AC BIST) comparison of the expected results are written to the array of configurable registers as they are read or written via system command and address registers through the master controller, and into the configurable registers of the array of configurable registers, and wherein each write to memory, read from memory, and compare cycle is considered an iteration at a constant reference voltage Vref and after an iteration said master controller can then adjust Vref and repeat another iteration.