Patent ID: 6100125
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A process for fabricating an ESD protection device formed of a transistor structure, the process comprising the steps of:a. forming an epitaxial layer of semiconductor material of first conductivity type on a semiconductor substrate;b. forming a retrograde well of second conductivity type in said epitaxial layer;c. forming a low-density drain region of said second conductivity type at a surface of said retrograde well, wherein said low-density drain region is omitted from a region of said epitaxial layer adjacent to a channel region of the transistor structure;d. removing a portion of a spacer oxide on a surface of said low-density drain region and leaving one or more drain blocking regions on said surface of said low-density drain region; ande. forming a drain region of said second conductivity type in exposed portions of said low-density drain region such that said drain region is not formed under remaining portions of said spacer oxide, wherein a charge carrier concentration of said drain region is higher than a charge carrier concentration of said low-density drain region.