Patent ID: 6567954
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A placement and routing method for the semiconductor integrated circuit having circuit elements or function circuit blocks, having transistors, on a semiconductor chip, the placement and routing method being for automatically generating necessary parameterized cells by giving a design rule and a design information including the size of said transistors, the method including:an object describing step for preparing an object description which describes in a predetermined graphic form each of said transistors as a transistor object in the form a cell and each wiring conductor as a separate horizontal wiring object and a separate vertical wiring object and which includes a relative position information of each object in relation to an adjacent object and a connection information indicative of a connection destination of each object; a transistor object processing step for generating said transistors in accordance with the object description and locating the generated transistors by considering said relative position information; a horizontal and vertical wiring object processing step for determining a position of each wiring objects for positioning both horizontal and vertical conductors in one level of a plurality of levels in both a horizontal direction and in a vertical direction by considering said relative position information; an object end point determining step for determining a final position of each transistor object and a final staring point and a final terminating point of each of said horizontal and vertical wiring object; and a wiring post-processing step for wiring each wiring object by a designated wiring layer.