Patent ID: 7274824
Filing Date: 2007-09-25
Classification: G06F,G06T,H04N

Abstract:
1. A digital signal processor comprising: a first buffer for storing data from a reference block; a second buffer for storing data from a search window; a plurality of absolute difference calculation circuits for calculating the absolute difference between the reference block data and the search window data; a multiple input adder for summing outputs from the absolute difference calculation circuits; a plurality of accumulators, each accumulator corresponding to a different search location within the search window and for accumulating the sums of absolute differences corresponding to that search location; a full adder for adding the sums of the absolute differences corresponding to one of the search locations to a value held in the accumulator corresponding to that same search location; a control circuit for determining which portions of data in the first buffer and in the second buffer are transmitted to the absolute difference calculation circuits and for determining to which accumulator the transmitted data corresponds; a multiplexer controlled by the control circuit to select one of the plurality of accumulators so that the value held in the selected accumulator is input to the full adder; and a demultiplexer controlled by the control circuit so that after the value held in the selected accumulator is input to the full adder, an output of the full adder is stored in the selected accumulator.