Patent ID: 6904465
Filing Date: 2005-06-07
Classification: G06F,H04L

Abstract:
1. A multiple-processor system comprising: a) A plurality of nodes, each node including one or more processors, a shared memory space, portions of which are resident in respective nodes; b) an inter-node switch unit linking each of the nodes with other nodes to provide the communication among the nodes, the switch unit serving as an ordering point for memory reference requests; said switch unit comprising: 1. a plurality of input switches, each of which (a) is connected to receive messages transmitted by a different group of processors; (b) and is configured to transmit messages selectively over a plurality of inter-switch output terminals, and (c) issues atomic messages corresponding to each memory reference request from a node connected to that switch; and 2. a plurality of output switches, each of which: (a) is connected to receive messages from an inter-switch output terminal of each of the input switches, (b) selectively transmits outputs to a group of nodes connected to that switch; and (c) follows the same ordering rule relative to input switches from which the messages are received simultaneously.