Patent ID: 9026835
Filing Date: 2015-05-05
Classification: G06F

Abstract:
1. A computer system, comprising: at least two nodes, wherein each of the at least two nodes includes a selecting module and a processor, wherein inputs to the selecting module of any node comprise clock of the node and clock output from another node, and an output terminal of the selecting module is connected to the processor of the node and an input terminal of the selecting module of another node; and a clock controlling module, wherein an output terminal of the clock controlling module is connected to a control terminal of the selecting module, for controlling the clocks of the at least two nodes to have the same clock, wherein the clock controlling module is provided with a clock relation connection table in which clock channels from one of the at least two nodes to any of the rest of the at least two nodes are recorded, and wherein the clock controlling module controls the selecting modules of the at least two nodes to select a clock of one of the at least two nodes as a common clock source for the at least two nodes, and in response to determining that the clock of the selected node becomes abnormal, the clock controlling module controls the selecting modules of the rest of the at least two nodes to select another available common clock source according to the clock channels recorded in the clock relation connection table such that the rest of the at least two nodes are provided with the same clock.