Patent ID: 8022442
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a silicon substrate; trench formed downward from a surface of said silicon substrate, said trench defining active regions in the surface of said silicon substrate; a liner layer of a silicon nitride film covering an inner wall of said trench; an element isolation region of silicon oxide formed on said liner layer, and filling said trench; an n-type well formed in one of said active regions, the n-type well being surrounded, in plan view, with said liner layer of the silicon nitride film; a p-channel MOS transistor formed in and on said n-type well; a contact etch stopper layer formed on said silicon substrate, directly covering said p-channel MOS transistor; a lower interlayer insulating film formed on said contact etch stopper layer; a light shielding film of a Si-rich silicon nitride layer having ultraviolet shielding ability and formed on said lower interlayer insulating layer above said liner layer and said contact etch stopper layer, an intermediate interlayer insulating film formed on said light shielding film, and having a wiring trench; and wiring embedded in said wiring trench; wherein said light shielding film and bottom of said wiring trench have complementary shapes.