Patent ID: 6982485
Filing Date: 2006-01-03
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a substrate having a resin layer with first and second surfaces wherein a plurality of electrically conductive patterns are formed thereon, the resin layer having an aperture formed in a central area thereof; a solder mask formed on the first and second surfaces of the substrate, the solder mask covering the electrically conductive patterns; a first semiconductor chip having first and second surfaces, the second surface having a plurality of input/output pads formed thereon, the first semiconductor chip being placed in the aperture of the substrate; a plurality of first conductive wires for connecting the input/output pads of the first semiconductor chip to the electrically conductive patterns formed on the resin layer; an adhesive attached to the second surface of the first semiconductor chip; a second semiconductor chip having first and second surfaces, the second surface having a plurality of input/output pads formed thereon, the second semiconductor chip being attached to the adhesive; a plurality of second conductive wires for connecting the input/output pads of the second semiconductor chip to the electrically conductive patterns formed on the resin layer; an encapsulate for encapsulating the aperture, the first and second semiconductor chips, and the first and second conductive wires; and a conductive thin film extending across the aperture of the substrate and coupled to the first side of the first semiconductor chip and the solder mask formed on the first surface of the substrate, the conductive thin film electrically coupled to the electrically conductive patterns formed on the first surface of the substrate through openings formed in the solder mask.