Patent ID: 8718224
Filing Date: 2014-05-06
Classification: G09G,G11C

Abstract:
1. A pulse signal output circuit comprising: a first transistor to a tenth transistor each comprising a first terminal, a second terminal, a first gate terminal, and a second gate terminal; a first to fourth input terminals; a first output terminal and a second output terminal; and a first to fourth power supply lines, wherein: the first terminal of the first transistor is electrically connected to the first input terminal, and the second terminal of the first transistor is electrically connected to the first output terminal, the first terminal of the second transistor is electrically connected to the first output terminal, and the second terminal of the second transistor is electrically connected to the first power supply line, the first terminal of the third transistor is electrically connected to the first input terminal, and the second terminal of the third transistor is electrically connected to the second output terminal, the first terminal of the fourth transistor is electrically connected to the second output terminal, and the second terminal of the fourth transistor is electrically connected to the first power supply line, the first terminal of the fifth transistor is electrically connected to the second power supply line, and the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor and the first terminal of the seventh transistor, the second terminal of the sixth transistor is electrically connected to the first power supply line, and the first gate terminal of the sixth transistor is electrically connected to the second terminal of the eighth transistor, the first terminal of the ninth transistor, the first gate terminal of the second transistor, and the first gate terminal of the fourth transistor, the second terminal of the seventh transistor is electrically connected to the first gate terminal of the first transistor and the first gate terminal of the third transistor, and the first gate terminal of the seventh transistor is electrically connected to the second power supply line, the first terminal of the eighth transistor is electrically connected to the second terminal of the tenth transistor, the first gate terminal of the eighth transistor is electrically connected to the second input terminal, and the second gate terminal of the eighth transistor is electrically connected to the third power supply line, the second terminal of the ninth transistor is electrically connected to the first power supply line, the first terminal of the tenth transistor is electrically connected to the second power supply line, the first gate terminal of the tenth transistor is electrically connected to the third input terminal, and the second gate terminal of the tenth transistor is electrically connected to the third power supply line, the first output terminal is electrically connected to the second gate terminal of the first transistor and the second gate terminal of the third transistor, the fourth input terminal is electrically connected to the first gate terminal of the fifth transistor, the second gate terminal of the fifth transistor, and the first gate terminal of the ninth transistor, the third power supply line is electrically connected to the second gate terminal of the second transistor, the second gate terminal of the fourth transistor, the second gate terminal of the sixth transistor, and the second gate terminal of the ninth transistor, and the fourth power supply line is electrically connected to the second gate terminal of the seventh transistor.