Patent ID: 6230278
Filing Date: 2001-05-08
Classification: G06F,Y02D

Abstract:
A data processing device, comprising:a plurality of processing units with at least a first processing unit connected to a first instruction memory and a second processing unit connected to a second instruction memory, wherein the first processing unit is operable execute instructions retrieved from the first instruction memory and wherein the second processing unit is operable execute instructions retrieved from the second instruction memory;a data bus connected to each of the plurality of processing units and to a memory circuit, the data bus operable to transfer data between each of the plurality of processing units and the memory circuit, such that the first of the plurality of processing units is operable to store a first data word in the memory circuit and the second of the plurality of processing units is operable to read the first data word from the memory circuit;a first instruction sequencer in the first processing unit, the first instruction sequencer operable to fetch instructions from the first instruction memory in response to addresses provided by the first instruction sequencer;a second instruction sequencer in the second processing unit, the second instruction sequencer operable to fetch instructions from the second instruction memory in response to addresses provided by the second instruction sequencer; andinstruction interconnect circuitry operable to transfer a first instruction directive from the first instruction sequencer to the second instruction sequencer, the second instruction sequencer in the second processing unit operable to begin processing a first sequence of instructions selected from the second instruction memory in response to the first instruction directive, whereby the first processing unit and the second processing unit selectively operate in a loosely coupled manner.