Patent ID: 7020723
Filing Date: 2006-03-28
Classification: G06F

Abstract:
1. A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first root physical semiconductor chip device to an internal CBA bus segment of at least one second external physical semiconductor chip device comprising: said first root physical device being a communications processor having a first serial communications interface module of varying bit width in said first semiconductor chip device coupled between said internal CBA bus segment and an input and output port of said first device for serializing bus transactions from said first device to said output port of said first device and de-serializing data received at said input port to said internal CBA bus segment of said first device using chip device standard protocols; said second external physical semiconductor chip device including a second serial communications interface module of varying bit width in said second device coupled between said internal CBA bus segment and an input and output port of said second device for serializing bus transactions from said second device to said output port of said second device and de-serializing data received at said input port to said internal CBA bus segment of said second device using said chip device standard protocols; an external serial communications connector coupled to said input and output ports of said first and second semiconductor chip devices for transferring the serialized transactions between said first and second devices using said chip device standard protocols, and an enumerator in said first root semiconductor chip device for automatically configuring for said at least one second serial communications interface module added to the system wherein said enumerator reads a remote device identification register for said at least one second serial communications interface module and locates associated device configuration file and abstracts knowledge of the hardware of said second external device and accompanying register set and creates address and interrupt map between said second interface module and said root semiconductor chip device using said chip device standard protocols.