Patent ID: 8706928
Filing Date: 2014-04-22
Classification: G06F

Abstract:
1. An integrated circuit, comprising: a shared resource for providing data; a buffer for storing the data; a buffer level monitor, coupled to the buffer, for monitoring a monitored level of data in the buffer; a retrieving circuit, coupled to the buffer, for retrieving the data from the buffer, according to a timing constraint; a filling circuit coupled to the buffer for writing the data to the buffer and coupled to the shared resource for receiving the data from the shared resource when the filling circuit has access to the shared resource; an access-requesting circuit coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource; an arbiter, coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource; and a controller, coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of the access requests sent to the arbiter when a condition indicating an anticipated violation of the timing constraint is fulfilled, the condition at least involving the monitored level of data in the buffer.