Patent ID: 6559009
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A method of fabricating a flash memory cell, the method comprising:providing a substrate; forming a gate oxide layer on the substrate; depositing a first polysilicon layer, and a silicon nitride cap layer, respectively, on the gate oxide layer; performing a lithographic process to pattern a first photoresist layer for defining both a memory array and a peripheral region on the silicon nitride cap layer; using the first photoresist layer as a mask to etch the silicon nitride cap layer and the first polysilicon layer to form columns of capped poly lines, wherein a wide gap is formed at the boundary between the memory array area and the peripheral region, and a plurality of gaps are formed in the memory array area; performing a high-density plasma chemical vapor deposition (RDPCVD) process to form an HOP oxide layer over the substrate to coat inner surfaces of the gaps with a bottom thickness; coating a photoresist on the oxide layer such that the gaps are filled with the HDP oxide layer and the photoresist coating; performing an oxide etch beck process to selectively remove a portion of the photoresist coating and a portion of the HDP oxide layer to expose the silicon nitride cap layer; performing an oxygen plasma etching process to remove the photoresist coating; and performing a wet etching process to remove the silicon nitride cap layer and so as to form at least one protruding portion of the HDP oxide layer.