Patent ID: 9070584
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A memory array, comprising: a substrate; a plurality of digitline (DL) trenches in the substrate, the DL trenches extending along a first direction, wherein each of the DL trench comprises an upper portion and a lower, widened portion; a buried digitline disposed in a body portion of the substrate between adjacent two of the DL trenches, wherein the buried digitline and the lower, widened portions of the adjacent two of the DL trenches are situated in a same horizontal plane, and wherein the buried digitline is in direct contact with the lower, widened portions of the adjacent two of the DL trenches; a trench fill material layer in each of the DL trenches, wherein the trench fill material layer completely fills the upper portion of each of the DLtrenches and conformally lines interior surface of the lower, widened portion of each of the DL trenches to thereby seal an air gap within the lower, widened portion; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around a sidewall of the AC trench.