Patent ID: 8023613
Filing Date: 2011-09-20
Classification: G09G,G11C

Abstract:
1. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Mth shift register stage of the shift register stages comprising: an input unit, electrically connected to an (M−1)th shift register stage of the shift register stages for receiving an (N−1)th gate signal, for inputting the (N−1)th gate signal having high voltage level to become a driving control voltage; a first pull-up unit, electrically connected to the input unit and an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to the driving control voltage and a first clock signal, wherein the Nth gate line is employed to deliver the Nth gate signal; a second pull-up unit, electrically connected to the input unit and an (N+1)th gate line of the gate lines, for pulling up an (N+1)th gate signal of the gate signals according to the driving control voltage and a second clock signal, wherein the (N+1)th gate line is employed to deliver the (N+1)th gate signal; a first control unit, electrically connected to the input unit, for generating a first pull-down control signal according to the driving control voltage and a first control signal; a first pull-down unit, electrically connected to the first control unit, the input unit, the Nth gate line and the (N+1)th gate line, for pulling down the driving control voltage, the Nth gate signal and the (N+1)th gate signal according to the first pull-down control signal; and an auxiliary pull-down unit, electrically connected the input unit, the Nth gate line, the (N+1)th gate line and an (M+1)th shift register stage, for pulling down the driving control voltage, the Nth gate line and the (N+1)th gate line according to a gate signal generated by the (M+1)th shift register stage; wherein M and N are positive integers.