Patent ID: 9184168
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including a cell region and a peripheral region; a cell gate electrode buried in a groove crossing a cell active portion of the cell region; a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode; a peripheral gate pattern crossing over a peripheral active portion of the peripheral region; a planarized interlayer insulating layer on the substrate around the peripheral gate pattern; a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer; and a capping line pattern on a top surface of the cell line pattern, a width of a bottom surface of the capping line pattern being substantially equal to a width of the top surface of the cell line pattern, and the capping line pattern including a same material as the capping insulating layer of the peripheral region wherein the cell line pattern includes a cell conductive line and a cell hard mask line which are sequentially stacked, the width of the bottom surface of the capping line pattern being substantially equal to a width of a top surface of the cell hard mask line.