Patent ID: 7729161
Filing Date: 2010-06-01
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a first word line conductor; a second word line conductor; first and second access devices having respective cell contacts and source line contacts, and responsive to the first and second word line conductors; a memory cell comprising a first electrode, a second electrode, and a memory element between the first and second electrodes, the first electrode being in electrical communication with the cell contacts of the first and second access devices, and wherein the memory element has a set state and a reset state, and comprises a phase change material; a bit line in electrical communication with the second electrode of the memory cells; and control circuits arranged to access the memory cell for read operations using the first word line conductor to establish a current path from the bit line through the memory cell to the source line contact of the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second word line conductors to establish a current path from the bit line through the memory cell to both the first and second source line contacts.