Patent ID: 9142179
Filing Date: 2015-09-22
Classification: G09G

Abstract:
1. A liquid crystal display device comprising: a first subpixel and a second subpixel, each provided with an electrode for driving a liquid crystal element; a first circuit, a second circuit, a third circuit, and a fourth circuit; a first wiring group including M wirings for supplying M (M is a natural number of 2 or more) different voltages, a second wiring group including M wirings for supplying M different voltages, a third wiring group including M wirings for supplying M different voltages, and a fourth wiring group including M wirings for supplying M different voltages; N wirings supplying a digital signal with N (N is a natural number of 2 or more) bits, being electrically connected to the first, second, third, and fourth circuit, wherein the first circuit is electrically connected to the first wiring group, wherein the second circuit is electrically connected to the second wiring group, wherein the third circuit is electrically connected to the third wiring group, wherein the fourth circuit is electrically connected to the fourth wiring group, wherein the first and the third circuits are electrically connected to the first subpixel, and wherein the second and the fourth circuits are electrically connected to the second subpixel, wherein the first circuit is configured to connect the first subpixel and one of M wirings of the first wiring group to each other, wherein the second circuit is configured to connect the second subpixel and one of M wirings of the second wiring group to each other, wherein the third circuit is configured to connect the first subpixel and one of M wirings of the third wiring group to each other, wherein the fourth circuit is configured to connect the second subpixel and one of M wirings of the fourth wiring group to each other, wherein the liquid crystal display device is configured to operate corresponding to one of a first mode and a second mode, wherein in the first mode, the digital signal with N bits is converted into a first analog signal and a second analog signal by using the M voltages supplied to the first wiring group and the M voltages supplied to the second wiring group, the first analog signal is input to the first subpixel, and the second analog signal is input to the second subpixel, and wherein in the second mode, the digital signal with N bits is converted into a third analog signal and a fourth analog signal by using the M voltages supplied to the third wiring group and the M voltages supplied to the fourth wiring group, the third analog signal is input to the first subpixel, and the fourth analog signal is input to the second subpixel.