Patent ID: 6194920
Filing Date: 2001-02-27
Classification: H03F

Abstract:
A semiconductor circuit, comprising:first and second input terminals;a PMOS differential circuit having two inputs, one of which is connected to said first input terminal and the other of which is connected to said second input terminal for outputting a first differential output;an NMOS differential circuit having two inputs, one of which is connected to said first input terminal and the other of which is connected to said second input terminal for outputting a second differential output;first and second power supply terminals;an output terminal; andan output circuit operable in response to the first and second differential outputs for (i) preventing, when a first current path is formed between said output terminal and said first power supply terminal, formation of a second current path between said second power supply terminal and said output terminal, but preventing, when the second current path is formed between said output terminal and said second power supply terminal, formation of the first current path between said first power supply terminal and said output terminal, when the input terminals are at high and low levels, and (ii) preventing both the first and second current paths from being formed when the input terminals are at an intermediate level.