Patent ID: 9118698
Filing Date: 2015-08-25
Classification: G06F,H04L

Abstract:
1. A data processing system comprising: a plurality of host CPUs; at least a first and a second Front End SAN controller (FE_SAN), each FE_SAN including a data memory, where each FE_SAN is interconnected to, at least one host CPU by a host system bus; at least a first and a second Back End SAN controller (BE_SAN), each BE_SAN being interconnected via at least one back-end network to a plurality of storage devices; a network fabric interconnecting the FE_SANs with the BE_SANs; and FE_SAN virtualization firmware executing on the FE_SAN controllers and BE_SAN virtualization firmware executing on the BE_SANs; wherein the FE_SAN virtualization firmware and the BE_SAN virtualization firmware are together configured to request data from a particular BE_SAN of the at least a first and a second BE_SANs when data is required by a particular requesting host CPU of the host CPUs; and wherein an operating system (OS) executing on a first host maps a portion of the first FE_SAN controller's physical memory as a first buffer of a first logical block address (LBA) into an application's address space allowing the application to directly access that memory bypassing file system, SCSI driver, and device driver; wherein a copy-on-write method is used to automatically copy data from the first buffer to at least one corresponding buffer allocated on the first BE_SAN; wherein, if an operating system executing a host maps a portion of the second FE_SAN controller's physical memory as a second buffer of the first LBA into an application's address space, and if data of the first buffer is modified by a host coupled to the first FE_SAN, the first BE_SAN controller notifies the second FE_SAN to invalidate data of the second buffer.