Patent ID: 6252430
Filing Date: 2001-06-26
Classification: B82Y,H03K

Abstract:
A latching comparator, comprising:a differential amplifier having a first and second input nodes, having a first and second output nodes, and having an internal track node;a first two-terminal device with a negative differential operating resistance connected between the first output node and a first internal latch node;a second two-terminal device with a negative differential operating resistance connected between the second output node and a second internal latch node;a first cross-coupled resistor connected between the second output node and the first internal latch node;a second cross-coupled resistor connected between the first output node and the second internal latch node;a bias circuit;a first latch switch circuit having a first latch mode signal as an input, the first latch switch circuit being coupled between the first internal latch node and the bias circuit and being configured to control current flow through the first two-terminal device and the first cross-coupled resistor;a second latch switch circuit having a second latch mode signal as an input, the second latch switch circuit being coupled between the second internal latch node and the bias circuit to control current flow through the second two-terminal device and the second cross-coupled resistor; anda track switch circuit having a track mode signal as an input, the track switch circuit being coupled between the internal track node and the bias circuit to control current flow through the differential amplifier.