Patent ID: 7656693
Filing Date: 2010-02-02
Classification: H01L

Abstract:
1. A semiconductor device having a memory cell area for storing data and a peripheral circuit area adjacent thereto on a semiconductor substrate, wherein: in the memory cell area, a cell transistor, a bit wiring line connected to the cell transistor, and a capacitor also connected to the cell transistor are provided in a vertically-layered structure; a first inter-layer insulating film is provided so as to cover the cell transistor; a second inter-layer insulating film is provided so as to cover the bit wiring line which is provided in an upper layer with respect to that of the cell transistor; a third inter-layer insulating film is provided so as to cover the capacitor which is provided in an upper layer with respect to that of the bit wiring line; in the peripheral circuit area, a peripheral-circuit transistor is provided and is covered with the first inter-layer insulating film; a first-layer wiring line connected to the peripheral-circuit transistor is provided on a main surface of the first inter-layer insulating film; the first-layer wiring line is covered with the second inter-layer insulating film; a second-layer wiring line is provided on a main surface of the third inter-layer insulating film which is formed on the second inter-layer insulating film; in the memory cell area, a landing pad is provided on a main surface of the second inter-layer insulating film and at a connection part between the capacitor and a contact plug which is formed for connecting the capacitor to the cell transistor provided in a lower layer; and an assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided.