Patent ID: 6144325
Filing Date: 2000-11-07
Classification: G11C,H03M

Abstract:
A memory element comprising:a first storage element for storing a first bit and its complement;a second storage element, separate from the first storage element, for storing a second bit and its complement;a first write port coupled to the first storage element for (i) receiving the first bit and a first write enable signal, (ii) producing, the complement of the first bit, and (iii) writing, the first bit and its complement into the first storage element in response to the first write enable signal;a second write port coupled to the second storage element for (i) receiving the second bit and a second write enable signal, (ii) producing the complement of the second bit, and (iii) writing the second bit and its complement into the second storage element in response to the second write enable signal;an encoder, coupled to the first and second storage elements, for encoding, the first and second bits and their complements stored in the storage elements into an encoded representation, wherein the encoded representation is produced by the encoder within the same clock cycle as the storage of the first and second bits into the first and second storage elements; anda read port coupled to the encoder for reading the encoded representation in response to a read enable signal.