Patent ID: 6818487
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising:forming a first field-effect transistor comprising a first source, a first drain and a gate; forming a second field-effect transistor above the first field-effect transistor, the second field-effect transistor comprising a second source, a second drain and said gate, wherein said gate is shared by said first field-effect transistor and said second field-effect transistor; wherein said forming of said second field-effect transistor comprises self-aligning said second source and said second drain to said gate in a layer of planarized semiconductor above said first field-effect transistor; and wherein said forming of the second field-effect transistor further comprises providing a doped insulator layer underneath and surrounding multiple sides of the second filed-effect transistor, wherein the second source and the second drain are formed by out diffusion of dopant from the doped insulator layer underneath and surrounding multiple sides of the second filed-effect transistor, and wherein a body of the second field-effect transistor is protected from the out diffusion by said gate.