Patent ID: 6323539
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A high voltage integrated circuit comprising:a first region of first conductivity type;a second region of second conductivity type formed in a selected area of a first major surface of said first region;a third region of first conductivity type formed in a selected area of a surface of said second region;first source region and first drain region of the first conductivity type formed in selected areas of the surface of said second region, apart from said third region;a first gate electrode formed on a surface of said second region between said first source region and said first drain region, through an insulating film;second source region and second drain region of second conductivity type formed in selected areas of a surface of said third region; anda second gate electrode formed on a surface of said third region between said second source region and said second drain region, through an insulating film;wherein said second region is formed such that an edge of a depletion layer appearing in said second region does not reach said third region when a first pn junction between said first region and said second region is reverse biased.