Patent ID: 7853908
Filing Date: 2010-12-14
Classification: G01R

Abstract:
1. A method of simulating an analog integrated circuit design utilizing an algorithmic reactive testbench simulation system, the method comprising: creating at least one unit testbench for the analog integrated circuit design, the unit testbench being represented as a self-contained test object that contains associated test object properties for associated test object operations; initiating performance of the associated test object operations; and in response to the initiated performance of the associated test object operations, making changes in the associated test object properties of the self-contained test object by passing values resulting from performance of the associated test object operations to the unit testbench, wherein the step of initiating performance of the associated test object operations and the step of making changes in the associated test object properties by passing the resulting values to the testbench are prescribed in an algorithmic reactive testbench program that is executed in the algorithmic reactive testbench simulation system.