Patent ID: 7788623
Filing Date: 2010-08-31
Classification: G06F

Abstract:
1. A method of referencing wires of a programmable logic device (PLD), wherein the PLD comprises a plurality of segmented wires arranged in a plurality of tiles, the method comprising: using a computer, identifying a plurality of interface templates corresponding to tiles of the PLD, wherein each interface template corresponds to at least two adjacent tiles of the PLD, and wherein each interface template identifies connections between segmented wires of the corresponding adjacent tiles; associating the segmented wires of the PLD with a plurality of wire index values based on the connections identified by the interface templates; and identifying a plurality of composite wires according to the wire index values, wherein each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values, wherein the composite wires interconnect to programmable logic blocks of the PLD.