Patent ID: 7560302
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A semiconductor device fabricating method comprising: (a) preparing plural semiconductor wafers, each of which includes a first main surface, a second main surface that opposes the first main surface, plural chip regions set in a matrix on the first main surface, precursor through holes that open to the first main surface, embedded electrodes that are embedded in the precursor through holes and include first top surfaces exposed to the first main surface, and first wiring layers that are disposed on the first main surface inside the chip regions and electrically connected to the first top surfaces of the embedded electrodes; (b) mounting the first main surfaces of the plural semiconductor wafers on front surfaces of plural support substrates, each of which includes a front surface and a back surface that opposes the front surface, and adhering the first main surfaces to the front surfaces with an adhesive to form plural precursor support substrate laminates; (c) polishing second main surface sides of the precursor support substrate laminates to expose second top surfaces of the embedded electrodes; (d) forming, on the second main surfaces, second wiring layers disposed electrically connected to the second top surfaces of the embedded electrodes; (e) cutting the semiconductor wafers along boundary lines of the plural chip regions and polishing, without cutting, the support substrates to form plural support substrate laminates including plural semiconductor chips; (f) electrically interconnecting and laminating the second wiring layers of two of the support substrate laminates to form a support substrate laminate composite; (g) separating and removing either one of the support substrates of the two support substrates of the support substrate laminate composite to expose the first wiring layers; (h) electrically connecting the second wiring layers of the other support substrate laminate to the exposed first wiring layers of the support substrate laminate composite and mounting the second wiring layers on the exposed first wiring layers; (i) separating and removing either one of the support substrates of the two support substrates of the support substrate laminate composite to expose the first wiring layers; (j) preparing plural precursor mounting substrates, each of which includes a front surface, a back surface that opposes the front surface, precursor mounting substrate through holes that open to the front surface, and mounting substrate embedded electrodes that are embedded in the precursor mounting substrate through holes and include first top surfaces exposed to the front surface; (k) electrically connecting the first top surfaces of the mounting substrate embedded electrodes of the precursor mounting substrates to the exposed first wiring layers of the support substrate laminate composite and mounting the first top surfaces on the exposed first wiring layers; (l) separating and removing the support substrates of the support substrate laminate composite; (m) exposing the exposed first wiring layers and injecting resin into gaps between the plural semiconductor chips and from end edge sides of the mounting substrate to form a first sealing portion; (n) forming a second sealing portion that seals the exposed first wiring layers and the first sealing portion; (o) polishing the back surface sides of the precursor mounting substrates to expose second top surfaces of the mounting substrate embedded electrodes and form a mounting substrate; (p) forming external terminals on the second top surfaces of the exposed mounting substrate embedded electrodes; and (q) cutting and dicing the first sealing portion, the second sealing portion, and the mounting substrate along boundary lines of the plural chip regions.