Patent ID: 9009395
Filing Date: 2015-04-14
Classification: G06F

Abstract:
1. A storage system comprising: a plurality of flash memory packages, each of the plurality of flash memory packages including a plurality of flash memory chips and a memory controller configured to store data in the plurality of flash memory chips; and storage controller comprising a cache memory and a processor, wherein the cache memory is divided into a plurality of cache slots, the plurality of cache slots being associated with sequential logical block addresses, and wherein the processor is configured to: store update data into one of the plurality of cache slots according to a write request received from a computer, and manage the update data as dirty data, thereby having a dirty status, the write request including the update data and a logical block address indicating a storage area in which the update data is to be stored in a target of the write request; and determine whether the target of the write request is a flash memory package of the plurality of flash memory packages, wherein when it is determined that the target of the write request is the flash memory package, the processor is further configured to: