Patent ID: 8027216
Filing Date: 2011-09-27
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; memory array blocks including memory cells provided corresponding to intersections between the word lines and the bit lines, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data from the memory cells or to write data into the memory cells via the bit lines; and an access counter provided for each memory cell block, the access counter being configured to count the number of times of accessing the memory array blocks in order to read data or write data, and being configured to activate a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of recovering data from degraded data of the memory cells connected to the activated word lines.