Patent ID: 8294275
Filing Date: 2012-10-23
Classification: H01L

Abstract:
1. A chip package, comprising: a semiconductor substrate having a first surface and a second surface; a device region or sensing region and a conducting pad disposed on the first surface; a hole extending from the second surface to the conducting pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface and the insulating layer; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the conducting pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on a surface of the carrier substrate, extending towards the second surface along the sidewall formed by the carrier substrate and the insulating layer, and electrically contacting the exposed edge of the first redistribution layer; and a buffer layer located on the second surface of the semiconductor substrate and located between the second redistribution layer and the semiconductor substrate such that the second redistribution layer does not directly contact with the semiconductor substrate.