Patent ID: 7271497
Filing Date: 2007-09-18
Classification: A61N,H01L

Abstract:
1. A semiconductor die package comprising: (a) a bumped semiconductor die comprising (i) a semiconductor die including a first planar conductive region, and (ii) a conductive stud bump on the first planar conductive region, wherein the conductive stud bump consists of a distinct inner conductive portion comprising copper and a distinct outer oxidation-resistant layer, wherein the inner conductive portion is in direct contact with the outer oxidation resistant layer; and (b) a circuit substrate including a second conductive region, and solder on the second conductive region, wherein the bumped semiconductor die is mounted on the circuit substrate and the conductive stud bump contacts the solder on the second conductive region, wherein the conductive stud bump comprises a base and a head, wherein the base is wider than the head, and wherein the oxidation-resistant layer comprises a noble metal, wherein portions of the oxidation-resistant layer and the inner conductive portion forming the base contact the first planar conductive region.