Patent ID: 6707751
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A semiconductor integrated circuit device, comprising:a plurality of word lines; a plurality of memory cells respectively selected by the plural word lines; a plurality of bit lines to which the plural memory cells are connected respectively; precharge circuits which respectively effect precharge operations on the plural bit lines upon non-selection of the plural word lines and stop the precharge operations when one word line is selected; a plurality of first amplifier circuits which respectively include first MOSFETs of first conductivity type having gates connected to the plural bit lines and held in an off state under precharge voltages supplied to the bit lines by the precharge circuits and which are respectively brought to an operating state in response to select signals for selecting the bit lines to thereby amplify read signals on the bit lines; and a first memory circuit including a second amplifier circuit including a plurality of second MOSFETs of second conductivity type, which have gates to which output signals of the plural first amplifier circuits are connected, and which are connected in parallel configurations and different from the first conductivity type, said second amplifier circuit forming an amplified signal corresponding to signals outputted from the first amplifier circuits.