Patent ID: 7817480
Filing Date: 2010-10-19
Classification: G06F,G11C

Abstract:
1. A nonvolatile memory comprising: a host interface which receives commands issued from an external processor; a sequence circuit which controls operations based on the commands; and a power generating circuit which generates operation power for a nonvolatile memory array, wherein the nonvolatile memory comprises a plurality of nonvolatile memory cells to store data received from the external processor, wherein in response to a first received command, the sequence circuit accesses the nonvolatile memory for reading data stored in ones of the plurality of nonvolatile memory cells, wherein in response to a second received command, the sequence circuit accesses the nonvolatile memory for storing data into ones of the plurality of nonvolatile memory cells, and wherein in response to a third received command, the sequence circuit makes the power generating circuit stop generating the operation power for the nonvolatile memory array.