Patent ID: 8928387
Filing Date: 2015-01-06
Classification: H03K

Abstract:
1. A tunable clock distribution structure, comprising: a clock input; a plurality of flip-flops with clock inputs; and a plurality of buffers, forming a structure configured to distribute clock signals from the clock input through at least one of the plurality of buffers to the clock inputs of the plurality of flip-flops, wherein each of the plurality of buffers comprises an inverter having an output coupled to a programmable variable resistor capable of assuming more than two different non-zero resistance values; wherein the programmable variable resistor comprises: a bit line; a word line; a programming transistor coupled to the word line and to the bit line; and a variable resistor coupled to the programming transistor and the inverter; wherein, in one mode, the programming transistor, the variable resistor and the inverter form a path for current to flow to program the variable resistor's resistance.