Patent ID: 6330173
Filing Date: 2001-12-11
Classification: G05F,G11C,H02M

Abstract:
A semiconductor integrated circuit comprising:a memory cell array area including a plurality of memory cells arranged in rows and columns, a plurality of word lines provided in correspondence to said rows and a plurality of bit lines provided in correspondence to said columns;a voltage generation circuit generating a voltage to be supplied to said memory cell array area; anda step-up voltage generation circuit for generating a step-up voltage, said step-up voltage generation circuit including:a sensing circuit sensing a level of said step-up voltage by comparing a voltage generated in accordance with an output from said voltage generation circuit and a voltage obtained by dividing said step-up voltage, anda circuit operating in accordance with an output of said sensing circuit for raising the level of said step-up voltage, whereinsaid step-up voltage is supplied to a selected word line among said plurality of word lines,said voltage generation circuit generates an array voltage to be written in a selected memory cell among said plurality of memory cells, andsaid sensing circuit includes:a step-up voltage dividing circuit dividing said step-up voltage,an array voltage dividing circuit dividing said step-up voltage,a reference voltage generation circuit generating a reference voltage in accordance with an output of said array voltage dividing circuit, anda compare circuit comparing said reference voltage with an output of said step-up voltage dividing circuit.