Patent ID: 6025267
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method of blocking the formation of a metal silicide layer, on exposed silicon surfaces, in a first region of a semiconductor substrate, while allowing the formation of a metal silicide layer, on exposed silicon surfaces, in a second region of a semiconductor substrate, comprising the steps of:forming shallow trench isolation regions, in said semiconductor substrate;forming a gate insulator layer on said semiconductor substrate;forming a first polysilicon gate structure, and a second polysilicon structure, on said gate insulator layer, in a second region of said semiconductor substrate;forming a third polysilicon gate structure, on said gate insulator layer, in said second region of said semiconductor substrate, with said third polysilicon gate structure located between a first shallow trench isolation region, and a second shallow trench isolation region;forming a fourth polysilicon gate structure, on said gate insulator layer, in said first region of said semiconductor substrate, with said fourth polysilicon gate structure located between said second shallow trench isolation region, and a third shallow trench isolation region;forming lightly doped source/drain regions in areas of said semiconductor substrate, not covered by polysilicon gate structures, and not covered by said shallow trench isolation regions;forming a first insulator spacer on the sides of said polysilicon gate structures, resulting in a first narrow space between said first polysilicon gate structure, and said second polysilicon gate structure;forming heavily doped source/drain regions in an area of said semiconductor substrate, not covered by said polysilicon gate structures, not covered by said shallow trench isolation regions, and not covered by said first insulator spacers;depositing an underlying masking insulator layer;depositing an overlying masking insulator layer;patterning of said overlying masking insulator layer, and of said underlying masking insulator layer, to create a composite insulator shape, overlying said first region of said semiconductor substrate, with the patterning procedure forming a second insulator spacer, comprising said underlying masking insulator layer, on said first insulator spacer, located on the sides of the polysilicon gate structures, in said second region of said semiconductor substrate, and with said second insulator spacer reducing said first narrow space between said first polysilicon gate structure, and said second polysilicon gate structure, to a second narrow space;removing said second insulator spacer, from said first insulator spacer, located on the sides of the polysilicon gate structures, in said second region of said semiconductor substrate, resulting in reestablishment of said first narrow space, between said first polysilicon gate structure, and said second polysilicon gate structure;performing a pre-clean procedure, to the exposed surfaces of the polysilicon gate structures, and exposed surfaces of the heavily doped source/drain region, located in said second region of said semiconductor substrate;depositing a metal layer;performing a first anneal procedure to form said metal silicide layer on the polysilicon gate structures, and on said heavily doped source drain regions, located in said second region of said semiconductor substrate, while leaving said metal layer, unreacted, on said first insulator spacer, on the sides of the polysilicon gate structures, located in said second region of said semiconductor substrate, and leaving said metal layer, unreacted, on the top surface of said composite insulator shape, in said first region of said semiconductor substrate;removing unreacted, said metal layer; andperforming a second anneal procedure to form a lower sheet resistance, metal silicide layer.