Patent ID: 6233655
Filing Date: 2001-05-15
Classification: G06F

Abstract:
A method for selectively storing Quad Words into a two-way interleaved L1 cache of a computer with a Double Word wide execution dataflow comprising the steps of:receiving from an I-unit (instruction unit), of said computer capable of executing Quad Words and Double Words, store, details of an instruction sought to be executed,recognizing with an E-unit (execution unit), of said computer, instructions that could result in having same storing data patterns;calculating address ranges information, with said E-unit, from source and destination address information and from said calculated address ranges information in said instruction sought to be executed, determining whether a corresponding multi-Double Word store with a same byte data will result for said address ranges, and, when a multi-Double Word store could result for said address ranges, then enabling the E-unit to request the writing of an incoming Double Word on a computer's data bus for both Double Word L1 Cache interleaves using the same destination address for both to effectively write two consecutively addressed Double Words for a same cycle to achieve a Quad Word store in said same cycle.