Patent ID: 7820518
Filing Date: 2010-10-26
Classification: H01L

Abstract:
1. A method of fabricating a transistor, the method comprising: forming a gate dielectric material over a workpiece having a first and a second region; forming a gate material over the gate dielectric material; patterning the gate material and the gate dielectric material to form gates and gate dielectrics of a first transistor in the first region and a second transistor in the second region of the workpiece; forming a stress-inducing material over the gates, the gate dielectrics, and the workpiece; forming sidewall spacers from the stress-inducing material on sidewalls of the gate and the gate dielectric of the second transistor by removing the stress inducing material in the second region but not in the first region; and inducing more stress in a first channel region of the first transistor than in a second channel region of the second transistor by annealing the workpiece.