Patent ID: 6449741
Filing Date: 2002-09-10
Classification: G01R

Abstract:
An electronic tester, comprising:a test head to couple to a device under test, wherein the device under test can be system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit; digital test circuitry that applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals; analog test circuitry that applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals; memory test circuitry that applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns; a tester computer that supervises the application of digital, analog, and memory test signals from the digital test circuitry, analog test circuitry, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals, wherein the test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the tester computer are operable as a single platform, wherein the digital test signals, the analog test signals, and the memory test patterns can be applied serially or concurrently to the device under test.