Patent ID: 6799268
Filing Date: 2004-09-28
Classification: G06F

Abstract:
An apparatus comprising:a processor state management circuit to maintain a primary state and a shadow state, each of said primary state and said shadow state including mappings from logical registers to physical registers, said primary state being a speculative state; and a branch ordering circuit to prevent said shadow state from advancing beyond a branch instruction until commitment of said branch instruction; a replay system to perform data speculation and to replay instructions that execute improperly, said replay system to signal said branch ordering circuit when a branch instruction commits, said replay system comprising: a replay loop; a replay queue having a longer delay than said replay loop; a multiplexing circuit coupled to receive instructions from instruction decode and fetch logic, from said replay loop, and from said replay queue; a checker and retirement unit, said checker and retirement unit being coupled to said replay loop and said replay queue to provide a replayed branch instruction to one of said replay loop and said replay queue if said replayed branch instruction is a fencing branch instruction preceded by a non-committed branch instruction.