Patent ID: 6473665
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A defect analysis method of a device which includes an integrated circuit formed on each of a plurality of chips on a wafer through a plurality of processes, said defect analysis method comprising the steps of:(a) after each of at least one process out of said plurality of processes, detecting a new defect due to said at least one process and occurring in a new area of said wafer other than an area of a defect occurring at a previous process and its vicinity; (b) after said plurality of processes are completed, making one of defective and non-defective judgement on said integrated circuit on each of said plurality of chips; (c) judging one of a presence and absence of said new defect satisfying a predetermined identifying condition in each of said plurality of chips, for each of said at least one process; (d) classifying said plurality of chips into four groups including non-defective chip with no said new defect, defective chip with no said new defect, non-defective chip with said new defect and defective chip with said new defect on a basis of a combination of the judgment of said step (b) and the judgment of said step (c), for each of said at least one process; (e) calculating a number of new defective chips considered to be caused only by said new defect of said at least one process, on a basis of the classification of said step (d); (f) calculating a critical rate of said new defect of said at least one process at which a chip is considered to become defective, on a basis of the classification of said step (d); and (g) calculating a number of process defective chips considered to be caused by said at least one process, on a basis of the classification of said step (d) and said critical rate, wherein said step (c) is performed a plurality of times for each of a plurality of detection sizes as a referred detection size, wherein said predetermined identifying condition includes a condition that a defect be of said referred detection size or more; and said steps (d) to (g) are performed said plurality of times corresponding to said step (c) which was performed said plurality of times, so that data for analysis including the number of said new defective chips, said critical rate, and the number of said process defective chips is obtained for each of said plurality of detection sizes for each of said at least one process, said defect analysis method further comprising the step of: (h) after said steps (c) to (g) are performed said plurality of times, recognizing at least one of the following as an analysis result of said at least one process on the basis of said data for analysis: an absolute critical detection size which is a minimum detection size for 100% of said critical rate out of said plurality of detection sizes; the maximum number of process defective chips out of the numbers of said process defective chips obtained for said plurality of detection sizes; an optimum-sensitivity detection size corresponding to said maximum number of process defective chips, out of said plurality of detection sizes; and the number of optimum-sensitivity new defective chips corresponding to said optimum-sensitivity detection size, out of the numbers of said new defective chips obtained for said plurality of detection sizes.