Patent ID: 6812748
Filing Date: 2004-11-02
Classification: H02M

Abstract:
A semiconductor device internally generating a negative substrate potential, comprising:an intermediate potential generation circuit receiving said substrate potential, and outputting an intermediate potential between a power supply potential and a ground potential, said intermediate potential generation circuit including a first P-channel MOS transistor having a source connected to a power supply node applied with said power supply potential, and a drain outputting said intermediate potential, a second P-channel MOS transistor having a source connected to the drain of said first P-channel MOS transistor, a gate connected to a ground node applied with said ground node, and a drain connected to a gate of said first P-channel MOS transistor, and a third P-channel MOS transistor connected between the drain of said second P-channel MOS transistor and said ground node, and having a gate receiving said substrate potential; a determination circuit receiving said intermediate potential, and determining whether said substrate potential is higher or lower than a target potential of said substrate potential; a negative potential generation circuit driving said substrate potential in a negative potential direction in accordance with an output of said determination circuit.