Patent ID: 7020879
Filing Date: 2006-03-28
Classification: G06F

Abstract:
1. A multi-streaming processor comprising: a plurality of hardware streams for streaming one or more instruction threads; a set of functional resources coupled to said hardware streams for processing instructions from said streams; interstream control coupled to said functional resources including a master mode wherein more than one stream is accorded master status, and the streams accorded master status may each run a master thread exercising master control over other streams not under control of another master stream; interrupt detection logic, coupled to interrupt signals, for providing said interrupt signals to the processor; interrupt mapping logic, for providing configurable interrupt mapping of said interrupt signals to ones of said plurality of streams such that at least one of said interrupt signals is mapped to ones of said plurality of streams; and interrupt logic, coupled to said interrupt mapping logic, for interrupting one or more of said streams according to said configurable interrupt mapping provided by said interrupt mapping logic; wherein through said interrupt logic, said interrupts are detected, and at the time of their detection said ones of said plurality of streams are directed to process said interrupts.