Patent ID: 6277720
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method of fabricating an integrated circuit, comprising the steps of:forming active device structures at a surface of a semiconducting body, the active device structures including doped regions at said surface of said semiconducting body;depositing a dopant diffusion barrier layer of silicon nitride over the active device structures and in contact with said surface of the semiconducting body;depositing a heat planarizable layer comprising doped silicon dioxide over and in contact with the silicon nitride layer;then heating the device structures to cause concurrent annealing the structures and planarization of said heat planarizable layer;then plasma etching selected locations of the heat planarized layer with a first etchant that selectively etches the heat planarized layer relative to silicon nitride to expose portions of the silicon nitride layer at the selected locations;then plasma etching the exposed portions of the silicon nitride layer with a second etchant to expose and provide openings to portions of the active device structures; andforming conductive connections to the active device structures through the etched openings in the planarized layer and the silicon nitride layer.