Patent ID: 6421293
Filing Date: 2002-07-16
Classification: G11C,H01L

Abstract:
An OTP memory cell in CMOS technology, comprising a capacitor associated in series with an unbalanced programming transistor, the drain comprising a well that is made of a region deeper and less doped than a source, the drain comprising a first electrode of the capacitor, the capacitor having a second electrode formed over the drain and insulated therefrom by an oxide layer, the capacitor configured to accept a first voltage in a read mode and a second voltage in a write mode, the second voltage having a higher voltage level than the first voltage, the capacitor having the oxide configured to breakdown when subjected to the second voltage, and the transistor is sized to limit current in the memory cell while allowing a breakdown of the oxide of the capacitor, the transistor and the capacitor further sized to limit voltage across the capacitor to less than the capacitor's breakdown voltage when the capacitor is unselected during a write operation.