Patent ID: 8564018
Filing Date: 2013-10-22
Classification: H01L

Abstract:
1. A structure comprising: a crystalline substrate; a first crystalline layer of a first natural crystal lattice constant that is different from a lattice constant of said crystalline substrate, positioned above the crystalline substrate; a second crystalline layer of a second natural crystal lattice constant that is different from the first natural crystal lattice constant of said first crystalline layer, positioned above the first crystalline layer, and comprising an elemental semiconductor, wherein the second crystalline layer is an epitaxial layer of silicon having a thickness of less than 500 Angstroms; a low defect density third crystalline layer of a third natural crystal lattice constant that is different from the second natural crystal lattice constant of said second crystalline layer and comprising a semiconductor alloy, on said second crystalline layer, as to promote creation of defects into at least said second crystalline layer, wherein growth of an initial portion of said low defect density third crystalline layer results in a strained layer however becoming a relaxed layer during growth of a final portion of said low defect density third crystalline layer, wherein the growth of the final portion is a growth provided after a time such that a critical thickness of the low defect density third crystalline layer is less than a physical thickness of the low defect density third crystalline layer, with relaxation of said low defect density third crystalline layer resulting in defects and dislocations induced in said underlying, second crystalline layer converting the second crystalline layer from a relaxed layer to a strained layer; and a strained thin fourth crystalline layer on said low defect density third crystalline layer, wherein a natural crystal lattice constant of said strained thin fourth crystalline layer is different from the third natural crystal lattice constant of said low defect density third crystalline layer and wherein the strained thin fourth crystalline layer includes a channel, a source, and a drain of a metal-oxide-semiconductor field effect transistor (MOSFET) device, and wherein an entirety of at least one of the source and the drain is disposed in the strained thin fourth crystalline layer.