Patent ID: 7586162
Filing Date: 2009-09-08
Classification: H01C,H01L

Abstract:
1. A high value resistive element in an integrated circuit, comprising a pair of resistive channel segments comprising a first resistive channel segment and a second resistive channel segment, wherein each resistive channel segment comprises: a. an elongated resistive semiconductor channel disposed above a substrate having a vertical thickness and a length greater than its width, wherein the resistive semiconductor channel includes a first end contact region and a second end contact region positioned at opposite distal ends of the resistive semiconductor channel; b. an insulator layer disposed proximate and above the resistive semiconductor channel, wherein the insulator layer insulates the resistive semiconductor channel from other integrated circuit elements; c. a first and second well provided within the insulator layer and disposed proximate and above the first and second end contact regions, respectively; d. a first conductive layer extending into the first well and conductively coupled to the first end contact region, wherein the first conductive layer is further disposed above the insulator layer forming an overlay conductive layer extending over both the insulator layer and a portion of the resistive semiconductor channel, wherein the overlay conductive layer extends from the first end contact region toward the second end contact region, and wherein the overlay conductive layer overlays at least approximately half the length of the resistive semiconductor channel as measured from the first end contact region to the second end contact region; and e. a second conductive layer extending into the second well and conductively coupled to the second end contact region, wherein the second conductive layer and the overlay conductive layer are insulated from each other by a gap formed between the two conductive layers; wherein the resistive channel segments are conductively coupled together at either of their first or second end contact regions, and wherein current flows in a first direction along the length of the first resistive channel segment and in a second direction along the length of the second resistive channel segment, and wherein the resistive channel segments are disposed within the integrated circuit such that the direction of current flow in the first segment is opposite the direction of current flow in the second segment.