Patent ID: 6311254
Filing Date: 2001-10-30
Classification: G06F

Abstract:
A cache system comprising:a central processing unit configured to load data from and store data to a data cache;a reload unit comprised of a plurality of entries each including a data buffer wherein each reload unit entry further includes data valid bits indicative of the validity of corresponding portions of the entry's data buffer;wherein the cache system is configured to initiate a data fetch transaction in response to a first store operation that misses in both the data cache and the reload unit, to allocate a first entry in the reload unit, and to write the first store operation's data in the first entry's data buffer;wherein the cache system is further configured to write data from at least one subsequent store operation into the first entry's data buffer if the at least one subsequent store operation misses in the cache and hits in the first entry of the reload unit prior to completion of the data fetch transaction, whereby the first entry's data buffer comprises a composite of the first and at least one subsequent store operations; andwherein the reload unit is configured to reload the data cache from the first reload unit entry if all of the first entry's data valid bits are set prior to completion of the data fetch transaction.