Patent ID: 6442100
Filing Date: 2002-08-27
Classification: G11C

Abstract:
An integrated memory, comprising:a plurality of memory cells and a number m>1 bit lines connected to said memory cells, switching elements connected to said bit lines and each having a control input, a sense amplifier having an input connected via said switching elements to said bit lines for transferring data from or to said memory cells; a circuit unit for influencing write or read operations via said sense amplifier and said bit lines, said circuit unit having an activation input for placing said circuit unit into an activated state; a column decoder having a first decoder stage and m second decoder stages; said first decoder stage having inputs for receiving address signals and an output connected to said activation input of said circuit unit; and said second decoder stages each having an input connected to said output of said first decoder stage, at least one further input for receiving a further address signal, and an output connected to said control input of a respective one of said switching elements.