Patent ID: 6834377
Filing Date: 2004-12-21
Classification: G06F

Abstract:
A method for checking an integrated electrical circuit to be described by a layout including circuit network descriptions of the integrated electrical circuit, each of the circuit network descriptions being in a form of one of a file and a part of a file on a memory unit of a computer system and each of the circuit network descriptions having at least one polygon each representing one circuit element of the integrated electrical circuit and information regarding electrical characteristics of circuit elements of the integrated electrical circuit, the layout having instantiations of at least one circuit network description and information about a geometrical shape and a configuration of the instantiations with respect to one another, the layout being described by a raw data structure associating each instantiation of a circuit network description with only one polygon data structure, which comprises:carrying out the following steps with a computer program: a) selecting a circuit network description from the layout; b) determining the instantiations of the circuit network description in the layout; c) determining the respectively geometrically identical and geometrically different instantiations of the circuit network descriptions by analyzing polygon data structures; d) forming variants for the instantiations of the circuit network descriptions and assigning the instantiations to these variants, geometrically different instantiations being combined into respectively different variants and geometrically matching instantiations being combined into respectively identical variants; e) forming a new data structure associating the circuit network description with only one polygon data structure, geometrical differences between the instantiations of the same circuit network description being taken into account by variants in the polygon data structure; f) storing the formed new data structure as one of a file and a part of a file on the memory unit of the computer system; and g) checking the layout of the integrated electrical circuit using the new data structure stored in step f) for faults caused by a configuration of the integrated electrical circuit.