Patent ID: 6640297
Filing Date: 2003-10-28
Classification: G06F

Abstract:
In combination with a digital processor, an indirect branch address storage and retrieval system for said digital processor, said digital processor for processing a computer program, including execution of instructions of the computer program, at least some of said instructions including indirect branch instructions and the determination of indirect branch addresses to which an indirect branch instruction is to branch for execution by said digital processor, comprising:data bus means for conveying an indirect branch address applied by said digital processor for use in a WRITE operation by said digital processor and for conveying indirect branch addresses for use in a READ operation by said digital processor; register means for storing indirect branch addresses for subsequent output on an immediate first-in first-out basis, said register means including an input, an output and a plurality of registers, each of said registers being sufficient in size to store a single indirect branch address, whereby said register means is capable of storing a plurality of indirect branch addresses equal in number to said plurality of registers; first means coupling said data bus means to said input of said register means for propagating a indirect branch address on said data bus means for storage in said register means in response to a WRITE operation by said digital processor, whereby a plurality of indirect branch addresses applied to said data bus means by said digital processor in a serial order may be stored concurrently in said register means when said digital processor asserts a WRITE operation for each of said plurality of indirect branch addresses; second means coupling said data bus means to said output of said register means for propagating an indirect branch address from said register means to said data bus means in response to a READ operation by said digital processor, each READ operation asserted by said digital processor producing an output of the next indirect branch address stored in said register means, whereby indirect branch addresses first inputted into said register are outputted first from said register means.