Patent ID: 6546410
Filing Date: 2003-04-08
Classification: G06F

Abstract:
Adder circuitry for adding two hexadecimal numbers comprising:a first adder for adding the first least significant hexadecimal digits of two hexadecimal numbers to provide a Digit1 and Dot1, the Digit1 being the first least significant hexadecimal digit of the addition of the two hexadecimal numbers; a second adder for adding the second least significant hexadecimal digits of the two hexadecimal numbers and providing a Sum2 and a CarryA; a generator for receiving the Sum2 and the CarryA and generating a Dot2; a secondary adder for adding the Dot1 and the Sum2 and providing a SumA, the SumA being the second least significant hexadecimal digits of the addition of the two hexadecimal numbers; a detector for receiving the Sum2 and the Dot1 to provide a triggering output in response to a predetermined pattern of the Sum2 and Dot1; and an output device responsive to the presence of the triggering output to provide the Dot2 as the third least significant digit of the addition of the two hexadecimal numbers.