Patent ID: 6043540
Filing Date: 2000-03-28
Classification: G11C,H01L,Y10S

Abstract:
An SRAM comprising:a first load resistor connected between a first power source terminal and a first node;a second load resistor connected between said first power source terminal and a second node;a first drive transistor having a source-drain path connected between said first node and a second power source terminal, and a gate connected to said second node;a second drive transistor having a source-drain path connected between said second node and said second power source terminal, and a gate connected to said first node;a first switching transistor having a source-drain path connected between said first node and a first bit line, and a gate connected to a word line; anda second switching transistor having a source-drain path connected between said first node and a second bit line, and a gate connected to said word line;said first and second drive transistors each having a gate length greater than a gate length of transistors constituting a peripheral circuit other than a sense amplifier circuit and a buffer circuit connected to an external terminal, but smaller than a gate length of said first and second switching transistors.