Patent ID: 8593854
Filing Date: 2013-11-26
Classification: G11C,H01L

Abstract:
1. A resistive random-access memory (RRAM) device comprising: a plurality of bit cells, each including a transistor and resistive element, said bit cells arranged in vertical columns, each said bit cell having said transistor having one source/drain coupled to a vertical bit line and the other source/drain coupled to a first terminal of said resistive element; a plurality of word lines coupled to respective gates of said transistors and arranged in a horizontal direction; and a plurality of source lines arranged in said horizontal direction and each coupled to an opposed terminal of at least one of said resistive elements, wherein a first source line of said source lines is coupled to two adjacent bit cells of said plurality of bit cells and biased at a sufficiently high voltage to enable said resistive elements of said two adjacent bit cells to have a conductive path formed therein, said two adjacent bit cells disposed along a first vertical bit line.