Patent ID: 8307197
Filing Date: 2012-11-06
Classification: G06F

Abstract:
1. A processor, comprising: a Boolean logic unit, wherein the Boolean logic unit is configured to perform a short-circuit evaluation of a Normal Form Boolean expression/operation, wherein performing a short-circuit evaluation comprises halting the evaluation of at least a portion of the Normal Form Boolean expression/operation if the outcome of the portion becomes known based on an outcome of an evaluation of a prior portion of the Normal Form Boolean expression/operation by the Boolean logic unit; a plurality of input/output interfaces in communication with the Boolean logic unit, wherein the plurality of input/output interfaces are configured for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results; and a plurality of registers coupled to the plurality of input/output interfaces, wherein the plurality of registers comprise: wherein the second register is initially set to a default value; wherein, the Boolean Logic unit is further configured to perform the following logic: if the expression is a conjunct and the evaluation of the conjunct expression stored in the first register is zero or its logical equivalent, then the value of the second register is set to a value other than its default value; if the expression is a disjunct and the evaluation of the disjunct expression stored in the first register is one or its logical equivalent, then the value of the second register is set to a value other than its default value; if the value of the second register is set to a value other than its default value, then the processor halts evaluation of the remainder of the expression/operation and provides the result of the expression/operation via one of the input/output interfaces.