Patent ID: 7590214
Filing Date: 2009-09-15
Classification: G11C

Abstract:
1. A shift register apparatus, comprising: a pre-charge circuit, for sampling an input signal according to a first clock signal and a second clock signal to generate a first charging signal and a second charging signal; a pull-up circuit, coupled to the pre-charge circuit, for receiving a third clock signal and the first charging signal and outputting an output signal accordingly; and a pull-down circuit, coupled to the pre-charge circuit and the pull-up circuit, for receiving a fourth clock signal and the second charging signal and determining whether or not to couple the output signal to a common potential accordingly, wherein the input signal, the first clock signal, the second clock signal are enabled in a first period, the third clock signal is enabled in a second period, the fourth clock signal is enabled in a third period, and the second period occurs after the first period, and the third period occurs after the second period.