Patent ID: 6616394
Filing Date: 2003-09-09
Classification: H01L,Y10S

Abstract:
A semiconductor wafer processing apparatus comprising:a first wafer process station including: a first main wafer transporter for handling semiconductor wafers within the first wafer process station, and a first plurality of wafer processing stacks containing process modules that are positioned in a polygonal configuration substantially around the first main wafer transporter; a second wafer process station disposed adjacent to the first wafer process station, and including: a second main wafer transporter for handling semiconductor wafers within the second wafer process station; and a second plurality of wafer processing stacks containing process modules that are positioned in a polygonal configuration substantially around the second main wafer transporter, a cassette end section for storing semiconductor wafers, and having a cassette wafer transporter that bidirectionally transports semiconductor wafers beyond the polygonal configuration of each respective wafer process station, and between at least one wafer processing stack in each wafer process station and the cassette end section; and a stepper interface section having a stepper wafer transporter that bidirectionally transports semiconductor wafers beyond the polygonal configuration of each respective wafer process station, and between at least one wafer processing stack in each wafer process station and the stepper interface section, wherein at least some of the process modules in each wafer process station are directly accessible by the cassette wafer transporter and the stepper wafer transporter.