Patent ID: 6413881
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A process for forming an MOS device of an integrated circuit structure on a silicon substrate, said MOS device characterized by a thin gate oxide and a barrier of nitrogen atoms between said thin gate oxide and a thin polysilicon gate electrode of said MOS device to inhibit passage of dopant from said thin polysilicon gate electrode into said thin gate oxide which comprises:a) growing a blanket layer of silicon oxide over a silicon substrate; b) using a nitrogen plasma in a vacuum chamber to etch a thin gate oxide from an exposed portion of said blanket layer of silicon oxide by: i) introducing said silicon substrate into said vacuum chamber; ii) biasing said silicon substrate in said vacuum chamber; iii) flowing nitrogen into said vacuum chamber; iv) igniting a nitrogen plasma in said vacuum chamber while maintaining said flow of nitrogen into said vacuum chamber and while maintaining said bias on said silicon substrate to thereby etch said exposed portions of said blanket layer of silicon oxide; and v) removing said bias from said silicon substrate when sufficient silicon oxide has been etched from said blanket layer of silicon oxide to achieve the desired thickness of said thin gate oxide; c) then, in the same vacuum chamber, nitridating an upper surface region of said thin gate oxide to form a barrier of nitrogen atoms in said upper surface region of said thin gate oxide by: i) flowing nitrogen into said vacuum chamber; and ii) maintaining a nitrogen plasma in said vacuum chamber while maintaining said flow of nitrogen into said vacuum chamber, but without maintaining a bias on said silicon substrate; and d) then extinguishing said nitrogen plasma used in said vacuum chamber both for forming said thin gate oxide and for nitridating said thin gate oxide; e) forming a thin polysilicon gate electrode over said nitridated gate oxide; f) doping said polysilicon gate electrode and exposed portions of said silicon substrate with dopant to increase the conductivity of said polysilicon gate electrode and to form source/drain regions in said silicon substrate; and g) annealing said silicon substrate to activate said dopant in said source/drain regions and to diffuse said dopant throughout said polysilicon gate electrode whereby said barrier of nitrogen atoms formed by said nitridation of said upper surface region of said thin gate oxide will inhibit passage of said dopant through said barrier of nitrogen atoms further into said thin gate oxide during said annealing; wherein the same vacuum chamber and flow of nitrogen into said vacuum chambers are used for both the step of forming said thin gate oxide and the step of nitridating the upper surface of said thin gate oxide.