Patent ID: 7142222
Filing Date: 2006-11-28
Classification: G09G,H04N

Abstract:
1. An apparatus including a decoder for providing a plurality of digital contrast control signals for a video signal, comprising: a halftone control terminal to convey a halftone control signal with first and second signal statuses corresponding to first and second contrast ranges, respectively, for a video signal; a plurality of contrast control terminals to convey a plurality of contrast control signals including a first portion corresponding to said first video signal contrast range and including, in successive adjacency, a first least significant bit (LSB) signal, at least one first intermediate significance bit (ISB) signal and a first most significant bit (MSB) signal; signal decoding circuitry, coupled to said halftone control terminal and said plurality of contrast control terminals, that responds to reception of said halftone control signal and said plurality of contrast control signals by providing a plurality of decoded control signals which, responsive to said first and second halftone control signal statuses, corresponds to said first and second video signal contrast ranges, respectively, wherein said second video signal contrast range is less than said first video signal contrast range; and buffer circuitry, coupled to said signal decoding circuitry, that responds to reception of said plurality of decoded control signals by providing a like plurality of buffered control signals.