Patent ID: 8599202
Filing Date: 2013-12-03
Classification: G06T

Abstract:
1. A method for performing tessellation operations using a graphics processor, the method comprising: receiving a set of control points defining a three-dimensional surface patch at the graphics processor; determining tessellation level of detail values for the three-dimensional surface patch; computing (u, v) coordinates for each vertex of the surface patch based on the tessellation level of detail values using a symmetric computation, wherein computing the (u, v) coordinates comprises: computing vertex attributes for each vertex of the surface patch based on the (u, v) coordinates and the set of control points, wherein a programmable shader in the graphics processor computes the vertex attributes, and wherein a fixed function computation unit within the graphics processor and not included within the programmable shader performs the symmetric computation; and replicating vertices of an edge of the surface patch having a lower tessellation level of detail value to produce a higher tessellation level of detail value using a vertex insertion pattern as a topology stitching algorithm to produce a consistent topology across level of detail boundaries.