Patent ID: 6559023
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device comprising the steps of:forming a p-type channel diffusion region, an n-type emitter diffusion region, an emitter electrode, a gate-insulating film, and a gate electrode in one principal surface region of an n-type semiconductor substrate that has resistivity uniform in a thickness direction and composes a base layer; implanting phosphorus ions into a shallow portion of a reverse principal surface region of said substrate and implanting boron ions into a portion of said reverse principal surface region shallower than said shallow portion followed by annealing of said substrate, so as to form an n-type impurity diffusion layer having an impurity concentration higher than an impurity concentration in said base layer and to form a p-type collector layer shallower than said impurity diffusion layer, wherein Xfsâˆ’XJ is in a range from 0.5 &mgr;m to 3 &mgr;m, Xfs being a position at which an impurity concentration in said impurity diffusion layer becomes twice an impurity concentration of said base layer and XJ being a position of a junction between said impurity diffusion layer and said collector layer; and forming a collector electrode on said collector layer.