Patent ID: 6389078
Filing Date: 2002-05-14
Classification: H03G,H03M,H04B,H04L

Abstract:
A configurable digital signal processing circuit comprising:a digital bus adapted to receive multi-bit digital signals and digital commands; a plurality of digital signal processing circuits connected to the bus and each digital processing circuit being responsive to digital commands received over the bus for setting the operating parameters of the digital processing circuits; a plurality of control registers connected to the bus and responsive to receiving configuration digital commands from the bus for configuring the interconnection of the multi-bit digital signal flow between the bus and selected ones of the plurality of digital signal processing circuits, for setting the operating parameters of the digital signal processing circuits, and for loading the configuration digital commands into the registers, and a control circuit connected to the bus and responsive to the receipt of configuration digital commands from the bus for transmitting the configuration digital commands to the control registers and for enabling the transfer of configuration digital commands from the control registers to the digital signal processing circuits to configure the interconnection with selected ones of the digital signal processing circuits and set the parameters thereof to process the multi-bit digital signals in accordance with the mode designated by the configuration digital commands received by the control circuit.