Patent ID: 8599642
Filing Date: 2013-12-03
Classification: G06F,G11C

Abstract:
1. A method of generating a dynamic port enable signal for gating memory array data to an output node, the method comprising: generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node; and chopping the leading edge clock signal derivation with a delayed, inverted version thereof such that only a set up time of the static input enable signal is coincident with the leading edge clock signal derivation, and a hold time of the static input enable signal is coincident with the delayed, inverted version of the leading edge clock signal derivation.