Patent ID: 9196553
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A semiconductor package structure, comprising: a first dielectric layer having a plurality of through holes; a second dielectric layer laminated on the first dielectric layer and having a plurality of conductive vias and a chip-containing opening, wherein the second dielectric layer is directly adhered to the first dielectric layer, the conductive vias pass through the second dielectric layer, the conductive vias are disposed correspondingly to the through holes and the chip-containing opening exposes out a partial region of the first dielectric layer; a chip disposed in the chip-containing opening and located on a first surface of the first dielectric layer exposed by the chip-containing opening, wherein the chip has an active surface and a rear surface opposite to the active surface, and the rear surface of the chip adheres onto the first dielectric layer; an adhesive layer disposed between the first dielectric layer and the second dielectric layer and between the chip-containing opening of the second dielectric layer and the chip, wherein the second dielectric layer and the chip adhere onto the first dielectric layer through the adhesive layer; a redistribution circuit layer disposed on the second dielectric layer and extending onto the active surface of the chip and the conductive vias, wherein the chip is electrically connected to the conductive vias through a part of the redistribution circuit layer; and a plurality of solder balls disposed in the through holes on a second surface of the first dielectric layer, wherein the second surface of the first dielectric layer is opposite to the first surface of the first dielectric layer, a part of the solder balls fill into the conductive vias so as to be electrically connected to the chip through the conductive vias and the redistribution circuit layer.