Patent ID: 6189135
Filing Date: 2001-02-13
Classification: B82Y,G03F,H01J

Abstract:
A method of generating electron-beam data used for creating a mask for a layout pattern of a semiconductor integrated circuit, said method comprising:parallel processing a layout pattern of a semiconductor integrated circuit with a parallel data processing unit based on at least one of (i) design layers of the semiconductor integrated circuit, (ii) fabrication processes used in fabricating a mask for the layout pattern, and (iii) segments, each segment being an electron-beam radiation region of the mask, by dividing data processing and assigning divided portions of the data processing to respective parallel-connected processing circuits wherein the parallel data processing unit includes a hierarchy developing unit for developing, in parallel processing, of a hierarchy of the layout pattern for respective design layers by assigning the developing of a hierarchy to respective parallel-connected processing circuits; andconverting format of data processed by parallel processing into electron-beam data and outputting the electron-beam data.