Patent ID: 6172378
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A semiconductor integrated circuit (IC) device comprising:a) a substrate;b) a first insulating layer formed on the substrate;c) a first semiconductor layer formed on the insulating layer;d) one of an N-well and P-well implant layer formed in the first semiconductor layer;e) a first region of one of an N.sup.+ and a P.sup.+ implant formed in the one of an N-well and P-well implant layer;f) a second region of one of an N.sup.+ and a P.sup.+ implant formed in the one of an N-well and P-well implant layer;g) a second insulating layer formed over a selected portion of a surface of the one of an N-well and P-well implant layer;h) a second semiconductor layer formed over a selected portion of a surface of the second insulating layer, and between the first region and the second region, wherein the second semiconductor layer forms one of a P-gate and an N-gate; andi) an isolation region extending from the first insulating layer to the second insulating layer and surrounding and electrically isolating the implant layer, the implant regions, and the second semiconductor layer.