Patent ID: 8980718
Filing Date: 2015-03-17
Classification: H01L,Y10S

Abstract:
1. A method for forming a PMOS transistor, comprising: providing a semiconductor substrate; forming a dummy gate structure having a dummy gate, a high-K dielectric layer, a capping layer, and a sidewall spacer on the semiconductor substrate, wherein the dummy gate is formed directly on the capping layer, which is formed directly on the high-K dielectric layer; forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process; performing a first annealing process to enhance the ion diffusion of the source region and the drain region; forming an interlayer dielectric layer coplanar with the top surface of the dummy gate; removing the dummy gate to form a trench exposing the capping layer and exposing a portion of the sidewall spacer, wherein the sidewall spacer is made of silicon nitride; performing a second annealing process to the exposed capping layer on the high-K dielectric layer, after removing the dummy gate, such that oxygen atoms from an environmental gas of the second annealing process penetrate through the exposed capping layer to react with the high-K dielectric layer underlying the capping layer to repair oxygen vacancies in the high-K dielectric layer for the PMOS transistor; and forming a metal gate in the trench.