Patent ID: 6282614
Filing Date: 2001-08-28
Classification: G06F,Y02D

Abstract:
A method of predicting access hits and misses of a memory cache and determining when to access one or more higher-level memory caches in a cache hierarchy, comprising the steps of:defining a window of size S for information which is sought on a memory cache, wherein S is measured in a number of accesses;detecting whether a hit or a miss occurs after each access of the memory cache;predicting, after each miss is detected, that the next miss will occur in a subsequent S accesses to the memory cache;predicting, if no miss is detected within the subsequent S accesses, that the next access of the cache memory will be a hit; andinhibiting a pre-charging of a plurality of bit lines to one or more higher-level memory caches if a hit is predicted in the cache memory.