Patent ID: 8501606
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. A semiconductor memory wiring method comprising: receiving a substrate having a cell area and a peripheral circuit area; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug comprising a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line comprising the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit area at substantially the same time as forming the first contact plug, the second contact plug comprising the first conductive material extending through the first insulating layer; forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line comprising the first conductive material directly covering and integrated with the second contact plug, and simultaneously silicidating lateral portions along the first elongated conductive line and along the second elongated conductive line.