Patent ID: 8717072
Filing Date: 2014-05-06
Classification: G11C,H03L

Abstract:
1. A semiconductor device comprising: a comparison unit configured to compare the phases of a plurality of clocks having different frequencies and output a phase comparison signal; a phase inversion control unit configured to generate a phase inversion control signal; and a start control unit configured to generate a start control signal in response to a clock enable signal, wherein the comparison unit is configured to start an operation in response to the start control signal and invert, in response to the phase inversion control signal, a phase of an internal clock generated from one of the plurality of clocks when the plurality of clocks have different phases, wherein the comparison unit comprises: a clock reception section configured to receive a system clock and a data clock; a clock division section configured to generate a data division clock by dividing the data clock such that the data division clock has the same frequency as the system clock and generate a phase of the data division clock by inverting the data division clock according to the phase inversion control signal; and a comparison section configured to compare a phase of an internal system clock outputted from the clock reception unit with the phase of the data division clock and output the phase comparison signal.