Patent ID: 6563856
Filing Date: 2003-05-13
Classification: H04W

Abstract:
For use in a digital transmitter, a combiner circuit having a unique word and receiving a predetermined number of data streams, wherein each data stream comprises a plurality of data frames, the combiner circuit comprising:a plurality of digital preamble circuits, each preamble circuit associated with one of the data streams and being capable of appending a predetermined portion of contiguous bits from the unique word to the beginning of each data frame to generate an extended data frame; a plurality of spreader, wherein the extended data frame for a particular data stream utilizes the same predetermined unique word portion; each spreader associated with one of the data streams and being capable of spreading each extended data frame, wherein each spreader receives a spreading code comprising a plurality of chips; a plurality of shifters, each shifter associated with one of the data streams and being capable of shifting the spread extended data frame by a delay equivalent to a multiple of the length of one chip of the spreading code; and a summer receivably connected to the shifters and being capable of summing the plurality of shifted data streams.