Patent ID: 6368922
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A process for manufacturing a bus-to-bus ESD protected structure connected between a first VDD and a second VSS power bus, comprising the steps of:forming a heavily doped polycrystalline silicon region, of a first conductivity type, on a surface of a second conductivity type portion of a substrate and connected to one of said power buses, diffusing impurities from said heavily doped region into said substrate to form a lightly doped region of said first conductivity type below said substrate surface and below said polycrystalline silicon region, forming a first heavily doped region, of said first conductivity type, of a first MOS device below said substrate surface and entirely contained within said lightly doped region, and forming a second heavily doped region, of said first conductivity type, of a second MOS device below said substrate surface at a particular location such that said first and second regions are laterally separated by a portion of said light doped region and at least part of said second conductivity type portion of said substrate, wherein said first heavily doped region and said second heavily doped region are each connected to a different one of said first VDD and second VSS power buses.