Patent ID: 6226778
Filing Date: 2001-05-01
Classification: G06F

Abstract:
A method of determining locations of a multiple circuit elements, whose interconnection relationship is previously determined, in a predetermined area on a substrate based on given positions of input/output (I/O) terminals in designing an integrated circuit so that the circuit elements are placed in the respective determined locations in a subsequent stage of the designing, said method comprising the steps of:(a) determining locations of sequential circuit elements, each of which functions as a sequential logic, of the multiple circuit elements prior to the remaining circuit elements, based on both said predetermined interconnection relationship of the multiple circuit elements and said given positions of the I/O terminals; and(b) determining locations of non-sequential circuit elements which are the remaining circuit elements in accordance with said determined locations of the sequential circuit elements, based on said predetermined interconnection relationship of the multiple circuit elements and said given positions of the I/O terminals.