Patent ID: 9165502
Filing Date: 2015-10-20
Classification: G09G,H01L

Abstract:
1. A display device comprising: a scan line; a signal line; a wiring; and a pixel region comprising: wherein the second transistor comprises a first gate electrode, a second gate electrode and an oxide semiconductor layer, the first gate electrode being electrically connected to the scan line, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the signal line, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the wiring, wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first electrode of the light-emitting element, wherein a first voltage applied to the wiring is greater than a second voltage applied to a second electrode of the light-emitting element, wherein the oxide semiconductor layer includes a channel formation region, wherein when the second transistor is off state, a drain current of the second transistor per a channel width of 1 μm is less than or equal to 1×10 wherein the first gate electrode and the second gate electrode overlap with the channel formation region and sandwich the oxide semiconductor layer.