Patent ID: 7846777
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device package, comprising the steps of: mounting at least two chips on a substrate such that the at least two chips are arranged to be spaced apart from each other to form a first space and to be spaced apart from an edge of the substrate to form a second space; forming an insulating layer on the substrate having the at least two chips mounted thereon; forming via holes exposing portions of the at least two chips and at least two hole patterns in at least one of the first and second spaces by etching the insulating layer selectively; forming a trench between the via holes to connect the via holes by etching the insulating layer selectively; forming a metal layer on the insulating layer including the at least two hole patterns, the via holes, and the trench; and forming a metal wire by polishing a portion of the metal layer formed above the via holes and the trench.