Patent ID: 9210082
Filing Date: 2015-12-08
Classification: H04L

Abstract:
1. An apparatus comprising: a parser circuit configured to parse a packet of a plurality of packets received via one network of a plurality of networks to generate a source address, a destination address, and information for said packet of said plurality of packets received during a single cycle; and a bridge circuit in communication with said plurality of networks and configured to (i) search a plurality of dual-port memories in parallel during the single cycle or a subsequent cycle of operation in said apparatus, wherein said plurality of dual-port memories are searched by (a) a first lookup of a first data set associated with said source address, (b) a second lookup of a second data set associated with said destination address and (c) a third lookup of a third data set associated with said information, and (ii) bridge said packet along a path between at least two networks of said plurality of networks in response to values generated by both said first lookup and said second lookup, wherein said plurality of dual-port memories are configured to be accessed concurrently with said first lookup, said second lookup, or said third lookup to update a respective dual-port memory with results of a learning operation performed after a miss.