Patent ID: 8106376
Filing Date: 2012-01-31
Classification: H01L

Abstract:
1. A memory device comprising: a bottom electrode; a top electrode; a multi-layer stack comprising a plurality of layers, the multi-layer stack contacting the top and bottom electrodes to define an inter-electrode current path through each of said layers between the top and bottom electrodes, the multi-layer stack including a first heater layer and a second heater layer and a memory element comprising a programmable resistive memory material, the memory element being sandwiched by the first heater layer and the second heater layer, the multi-layer stack having a sidewall surface defining a width of the first heater layer and of the second heater layer and of the memory element transverse to the inter-electrode current path which is less than a width of a top surface of the bottom electrode in contact with the multi-layer stack; and an air gap adjacent to the sidewall surface of the memory element, the first heater layer, and the second heater layer and self-aligned to the memory element.