Patent ID: 6147912
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A non-volatile semiconductor memory comprising:a memory cell array including a plurality of memory rows each having a plurality of memory cell transistors serially connected to each other through a plurality of connection nodes;a plurality of word lines each of which commonly connects a plurality of gates of the memory cell transistors of one of the memory rows;a plurality of column lines connected to the connection nodes in a direction substantially perpendicular to the memory rows, said column lines including first column lines and second column lines located between the first column lines, the first column lines including third column lines and fourth column lines located between the third column lines;a bias potential supply line;a plurality of select transistors including first select transistors connected between said bias potential supply line and the third column lines, and second select transistors connected between said bias potential supply line and the fourth column lines, wherein the first select transistors are controlled by a first select signal and the second select transistors are controlled by a second select signal;a data bus;a multiplexer circuit connected to the second column lines and said data bus, said multiplexer circuit selectively connecting one of the second column lines with said data bus; anda sense amplifier connected to said data bus.