Patent ID: 6356110
Filing Date: 2002-03-12
Classification: H03K

Abstract:
A logic array block, comprising:a plurality of logic elements each having a plurality of logic element input leads and a memory element including a plurality of memory cells, each memory cell having addressable write circuitry for writing a bit value to be stored in that memory cell, wherein each logic element is individually configurable to perform any of a plurality of logic functions on a plurality of logic signals applied on its associated logic element input leads; and an address decoder circuit having a plurality of write address leads and a plurality of write control signal leads, wherein the address decoder circuit is configured to decode a set of write address signals applied on the write address leads to generate one of a plurality of write control signals that is conveyed on one of the plurality of write control signal leads to control the associated addressable write circuitry of at least one memory cell within the associated memory element of each logic element in the logic array block.