Patent ID: 6770940
Filing Date: 2004-08-03
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor integrated circuit of a CMOS structure comprising: a first static random access memory (SRAM) operating at a first frequency, power to the first SRAM being shut off as required; a first logic circuit accessing the first SRAM; a second SRAM operating at a second frequency lower than the first frequency, power to the second SRAM being kept supplied during the shutoff of power to the first SRAM; and a second logic circuit accessing the second SRAM,wherein the first SRAM includes a first SRAM cell array and a first peripheral circuit for mediating access to the first SRAM cell array, the second SRAM includes a second SRAM cell array and a second peripheral circuit for mediating access to the second SRAM cell array, and the average channel width of MOS transistors constituting each of the first and second SRAM cell arrays is set at a half or less of the average channel width of MOS transistors constituting each of the first and second peripheral circuits and the first and second logic circuits, and the second SRAM cell array includes a MOS transistor having a channel impurity concentration different from the channel impurity concentration of the MOS transistors of the first SRAM cell array, the first peripheral circuit and the first logic circuit, so that the MOS transistors of the first SRAM cell array have a threshold voltage lower than the MOS transistors of the second SRAM cell array as for at least either N-channel MOS transistors or P-channel MOS transistors.