Patent ID: 6085330
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A computer system comprising:a processor including an internal cache, the processor operating in a plurality of power states including a fully operational state in which the processor is fully operational, a stop grant low-power state in which the internal cache is snooped, and a stop clock low-power state in which the internal cache is not snooped;a clock generator coupled to the processor and generating a clock signal timing operations of the processor; anda state control circuit coupled to the processor and coupled to the clock generator, the state control circuit controlling the processor while operating in the stop clock low-power state to transition to the stop grant low-power state in response to a bus request signal, snoop the processor internal cache, and return from the stop grant low-power state to the stop clock low-power state following the snoops; and whereinthe processor is initialized into the fully operational state and enters the fully operational state upon an occurrence of a predefined resume signal;the processor transitions from the filly operational state to the stop clock low-power state on receipt of an idle determination; andthe state control circuit transitions the processor from the stop grant low-power state to the stop clock low-power state on an occurrence of a bus cycle complete signal.