Patent ID: 7725788
Filing Date: 2010-05-25
Classification: G01R,G06F

Abstract:
1. A processing device comprising: a scan chain comprising an input, an output, and a plurality of latches coupled in series between the input and the output, the plurality of latches comprising a first latch having a reset input to receive a scan reset signal, a data input, and a data output, the first latch configured to reset a first latched data of the first latch to a predetermined value in response to an assertion of the scan reset signal; and a scan controller comprising an input to receive a test mode signal and an output coupled to the reset input of the first latch to provide the scan reset signal, the scan controller configured to assert the scan reset signal in response to an assertion of the test mode signal, the assertion of the test mode signal to enable the processing device to enter a scan test mode to read information that is present in latches of the scan chain other than the first latch prior to the assertion of the test mode signal.