Patent ID: 8339872
Filing Date: 2012-12-25
Classification: G11C

Abstract:
1. A semiconductor memory apparatus, comprising: a bit-line sense amplifier configured to sense and amplify data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmit the amplified data to a memory cell; and a bit-line sense amplification power supply unit configured to supply pull up drive voltage and pull down drive voltage to the pull up and pull down power lines in an active mode and supply an over drive voltage having a higher voltage level than the pull up drive voltage and the pull down drive voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode, wherein the bit-line sense amplification power supply unit includes a power drive signal generator configured to generate a pull up power drive signal, a pull down power drive signal, and a pull up over drive power drive signal, which are activated for a predetermined period, in response to an active pulse signal, a precharge pulse signal and an internal command signal having an activation time point earlier than the precharge pulse signal, wherein the active pulse signal is an activated signal after a predetermined time from an active command applying time point and the precharge pulse signal is an activated signal after a predetermined time from a precharge command applying time point.