Patent ID: 8674494
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a substrate; a first semiconductor chip on the substrate; a support plate on the substrate; a first electrically conductive connection between the first semiconductor chip and the support plate, wherein the first electrically conductive connection is configured to provide electrical connection between the first semiconductor chip and the substrate; and a chip stack on the support plate and on the first semiconductor chip, wherein the chip stack includes a plurality of second semiconductor chips, a first adhesion layer, and a second adhesion layer, wherein the first adhesion layer is between a first of the plurality of second semiconductor chips and the support plate and between the first of the plurality of second semiconductor chips and the first semiconductor chip, wherein the second adhesion layer is between the first of the plurality of second semiconductor chips and a second of the plurality of second semiconductor chips, wherein the first adhesion layer is thicker than the second adhesion layer, wherein the first electrically conductive connection penetrates a portion of the first adhesion layer between the first semiconductor chip and the first of the plurality of second semiconductor chips, wherein the first adhesion layer is in direct contact with the first of the plurality of second semiconductor chips, the support plate, and the first semiconductor chip, and wherein the first adhesion layer has a thickness between the first of the plurality of second semiconductor chips and the support plate and between the first of the plurality of second semiconductor chips and the first semiconductor chip that is substantially uniform.