Patent ID: 9122611
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A method for giving a read command to a flash memory chip having a first buffer region, a second buffer region and a storage region, the method comprising: receiving a host command from a host system by a flash memory controller having a buffer memory, wherein the host command is a host read command and the host command comprises a first logic address, wherein the first logic address maps to a first physical address of the storage region; giving a general read command and a first cache read command to the flash memory chip by the flash memory controller according to the host command so as to sequentially read a first data starting from the first physical address, wherein the first data is moved from the storage region to the second buffer region, moved from the second buffer region to the first buffer region and transferred from the first buffer region to the buffer memory, wherein in response to moving the first data from the storage region to the second buffer region, the flash memory chip is in a busy state, and in response to moving the first data from the second buffer region to the first buffer region, the flash memory chip is changed to be in a ready state, wherein a second data is moved from the storage region to the second buffer region during the first data is transferred from the first buffer region to the buffer memory and after the first data is transferred from the first buffer region to the buffer memory, the second data is moved from the second buffer region to the first buffer region, wherein the second data is not requested by the host command and a logic address corresponding to the second data follows the first logic address; giving a second cache read command to the flash memory chip by the flash memory controller to read a third data, wherein the third data is moved from the storage region to the second buffer region during the second data is transferred from the first buffer region to the buffer memory and after the second data is transferred from the first buffer region to the buffer memory, the third data is moved from the second buffer region to the first buffer region; receiving a next host command from the host system, wherein the next host command comprises a second logic address; determining whether the next host command is the host read command and whether the next host command follows the host command; when the next host command is the host read command and the next host command follows the host command, transmitting the second data from the buffer memory to the host system; and when the next host command is the host read command and the next host command does not follow the host command, giving a first reset command to the flash memory chip and giving the general read command and a third cache read command to the flash memory chip by the flash memory controller to sequentially read a fourth data, from the flash memory chip, corresponding to the next host command from a physical address mapping a fourth logic address.