Patent ID: 6590249
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A method for fabricating a dynamic memory cell, which comprises:in a first semiconductor substrate, forming a trench capacitor having a blocked-type inner electrode, a dielectric intermediate layer surrounding the inner electrode, and an outer electrode at least partly surrounding the electric intermediate layer; forming a dielectric insulator layer by: applying a first thin dielectric insulator layer on the first semiconductor substrate, applying a second thin dielectric insulator layer on a second semiconductor substrate, pressing the second thin dielectric insulator layer of the second semiconductor substrate against the first thin dielectric insulator layer of the first semiconductor substrate, and obtaining a mechanically fixed connection by using a wafer bonding method; in the second semiconductor substrate, forming a selection transistor having a first electrode region configured essentially above the block-type inner electrode of the trench capacitor, a channel region, a second electrode region, a control electrode, and insulator layer isolating the control electrode from the channel region; and forming a contact opening in the dielectric insulator layer and providing the contact opening with an electrically conductive filling layer such that the contact opening connects the first electrode region of the selection transistor to the block-type inner electrode of the trench capacitor; the dielectric insulator layer being located between the selection transistor and the trench capacitor.