Patent ID: 6437768
Filing Date: 2002-08-20
Classification: G09G

Abstract:
A data signal line driving circuit comprising:a shift register circuit for sequentially transmitting a pulse signal in sync with a clock signal, said shift register circuit being composed of a plurality of serially connected latch circuits; and an output circuit for sequentially outputting data signals to data signal lines in sync with output signals outputted from said shift register circuit, wherein,said shift register circuit is divided into a plurality of blocks, each block including a number of stages (stage numbers) of latch circuits, where all the blocks have not-identical number of stages of the latch circuits, while some of the blocks may have an identical number of stages of the latch circuits with each other, and stage numbers of the latch circuits included in said each block is set so as to compensate for a difference between the differing delays of the sequential output signals and the differing delays of the data signals.