Patent ID: 6804164
Filing Date: 2004-10-12
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of unit cells arranged in rows and columns, each of said plurality of unit cells having first and second storage elements, each of said first storage elements including a first capacitor for storing information and first and third access transistors for accessing said first capacitor, each of said second storage elements including a second capacitor and second and fourth transistors for accessing said second capacitor; a plurality of first-port bit line pairs provided corresonding to the respective columns, each of the first-port bit line pairs connecting to the first and second transistors of the unit cells on a corresponding column, and each of said first-port bit line pairs including first and second first-port bit lines respectively coupled to the first and second transistors of the unit cells on the corresponding column; a plurality of second-port bit line pairs provided corresponding to the respective columns, each of the second-port bit line pairs connecting to the third and fourth transistors of the unit cells on a corresponding column, and each of said second-port bit line pairs including first andd second second-port bit lines respectively coupled to the third and fourth transistors of the unit cells on the corresponding column; a plurality of first-port word lines provided corresponding to the respective rows, each of the first-port word lines connecting to the first and second transistors of the unit cells on a corresponding row; a plurality of second-port word lines provided corresponding to the respective rows, each of the second-port word lines connecting to the third and fourth transistors of the unit cells on a corresponding row; a first-port bit-line voltage setting circuit for setting voltages on said first and second first-port bit lines to a prescribed voltage level different from an intermediate voltage level in a standby state in which said first-port word lines are in a non-selected state, the intermediate voltage level being equal to half a sum of voltages respectively corresponding to high-level and low-level data stored in the first and second capacitors of the unit cells; and a second-port bit-line voltage setting circuit for setting voltages on the first and second second-port bit lines of each of said second-port bit line pairs to said prescribed voltage level in a standby state in which said second-port word lines are in the non-selected state.