Patent ID: 6680507
Filing Date: 2004-01-20
Classification: G11C,H01L

Abstract:
A dual floating gate transistor comprising:a substrate; a first bit line oxide disposed on the surface of said substrate; a second bit line oxide disposed on the surface of said substrate; a tunnel layer covering a portion of a region between said first bit line oxide and said second bit line oxide; a first floating gate disposed on the surface of said tunnel layer, and partially overlaying a first drain/source region; a second floating gate disposed on the surface of said tunnel layer, wherein said second floating gate is electrically isolated from said first floating gate; a barrier layer comprising a portion disposed on said substrate between said first floating gate and said second floating gate; an isolation opening disposed above said barrier layer and between said first floating gate and said second floating gate; and a control gate comprising a portion disposed in said isolation opening and in contact with said portion of said barrier layer between said first floating gate and said second floating gate.