Patent ID: 9026761
Filing Date: 2015-05-05
Classification: G06F

Abstract:
1. An interface system for interfacing a synchronous circuit generating a first data signal with an asynchronous circuit generating an encoded second data signal according to an asynchronous communication protocol, said synchronous circuit sampling in response to a clock signal, the encoded second data signal when a first control signal indicates that said encoded second data signal contains valid data, the system comprising: a first-in first-out (FIFO) memory; a control circuit configured to asynchronously write said encoded second data signal in said FIFO memory when said encoded second data signal indicates a start of communications, and synchronously read said encoded second data signal from said FIFO memory in response to said clock signal; a conversion circuit configured to decode, according to said asynchronous communication protocol, said encoded second data signal read from said FIFO memory into a decoded data signal, said decoded data signal corresponding to data in the first data signal, said FIFO memory comprising a comparator configured to compare the write pointer with the read pointer to generate an acknowledgement signal, the acknowledgement signal for disabling communication with the asynchronous circuit so that only the read pointer changes and indicating that either the encoded second data signal has been successfully sampled or that said FIFO memory is full, thereby avoiding glitches in sampling the encoded second data signal.