Patent ID: 6136652
Filing Date: 2000-10-24
Classification: G11C,H01L

Abstract:
A process for fabricating a field-effect semiconductor memory device comprising the steps of:(a) providing a structure including: (i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region and a spaced apart source region of said device, and said channel is situated between said drain region and source region and having a drain area adjacent said drain region and having source area adjacent said source region; (ii) a first member disposed over said drain area and over at least a portion of said drain region of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area;(b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel;(c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall; and(d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area thereby said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of an electrically programmable non-volatile transistor.