Patent ID: 8592276
Filing Date: 2013-11-26
Classification: B82Y,H01L

Abstract:
1. A fabrication method of a vertical silicon nanowire field effect transistor, comprising: a) defining an active region over a silicon substrate and forming a local oxidation of silicon (LOCOS) isolation; b) forming a vertical silicon pillar having a large diameter and a top support structure by performing a photolithography process twice and a dry etching process, so as to fabricate a vertical silicon nanowire, comprising: c) further reducing a size of the silicon pillar to form the vertical silicon nanowire having a diameter of about 10 nm, while remaining a large area of pattern used for the drain on top of the vertical silicon nanowire, so as to reduce a parasitic resistance of the drain, comprising: d) defining and doping a source/drain region and a channel region of the vertical silicon nanowire, comprising: e) forming a contact hole and a metal interconnection.