Patent ID: 6801052
Filing Date: 2004-10-05
Classification: G06F

Abstract:
In an integrated circuit having an FPGA core with core cells, each FPGA core cell comprisinga plurality of core cell input terminals and one or more core cell output terminals; one or more LUTs, each LUT having an output terminal and a plurality of input terminals, each input terminal of each LUT connected to one of said core cell input terminals; a selectable logic gate having an output terminal and a plurality of input terminals, each input terminal connected to one of said LUT output terminals or to any remaining core cell input terminal not connected to an LUT input terminal; and circuitry selectably connecting said output terminals of said LUTs and said selectable logic gate to said core cell output terminals; whereby said core cell is programmed by setting configuration bits in said one or more LUTs, selecting said logic gate and selectably connecting said output terminals of said one or more LUTs and of said selectable logic gate to said core cell output terminals.