Patent ID: 7157757
Filing Date: 2007-01-02
Classification: H01L

Abstract:
1. A semiconductor construction, comprising: a semiconductor substrate having a primary surface defining a horizontal direction: a first gate dielectric region over the semiconductor substrate, the first gate dielectric region comprising a first width and containing a first thin segment of dielectric material between two first thicker segments of dielectric material, the first thin and first thicker segments of dielectric material comprising upper surfaces substantially parallel to the primary surface of the substrate and joining to one another at first steps having primary surfaces substantially orthogonal to the primary surface of the substrate; a first gateline over the first thin and first thicker segments of the first gate dielectric region, the first gateline having a pair of opposing sidewalls; a pair of opposing first source/drains along the opposing sidewalls of the first gateline and joined to one another through a channel controlled by the first gateline; the thicker segments of dielectric material having a first length; a second gate dielectric region having a second width greater than the first width; the second gate dielectric region comprising a second thin segment of dielectric material between second thicker segments of dielectric material, the second thicker segments being about the same length as the first thicker segments but the second thin segment being longer than the first thin segment so that the second gate dielectric region is wider than the first gate dielectric region; a second gateline over the second thin segment and second thicker segments of the second gate dielectric region, the second gateline having a pair of opposing sidewalls and having a width greater than a width of the first gateline; and a pair of opposing second source/drains along the opposing sidewalls of the second gateline and joined to one another through a channel controlled by the second gateline.