Patent ID: 7737533
Filing Date: 2010-06-15
Classification: H01L

Abstract:
1. A semiconductor junction device, comprising: a substrate of low resistivity semiconductor material having a preselected polarity; a tapered recess extending into the substrate and tapering inward as it extends downward from an upper surface of the substrate, wherein the tapered recess is a V-groove; a semiconductor layer disposed within the recess and extending above the upper surface of the substrate, said semiconductor layer having a polarity opposite from that of the substrate, wherein said semiconductor layer is formed by first depositing a layer of undoped polysilicon, implanting a dopant having a polarity opposite to that of the substrate into the polysilicon layer, and using an anneal process to diffuse the dopant into said substrate, such that an electrical field at the bottom tip of the tapered recess is enhanced to lower the breakdown voltage of the device, and wherein said semiconductor layer covers an oxide layer used to form a mask to create the tapered recess; and a metal layer overlying the semiconductor layer.