Patent ID: 7292494
Filing Date: 2007-11-06
Classification: G11C

Abstract:
1. A deep power down circuit to save power in a low power memory chip, comprising: a plurality of internal voltage generators, said internal voltage generators comprising: a first group internal voltage generators which generate voltages related to the voltages of cells of the memory chip, any one of the first group internal voltage generators being in a first predetermined state in a deep power down mode, the first predetermined state being a grounding-level state or a floating-level state; and a second group internal voltage generators which generate voltages not related to the voltages of the cells of the memory chip, any one of the second group internal voltage generators being in a second predetermined state in the deep power down mode, the second predetermined state being selected from the group consisting of a keep-level state, a grounding-level state, and a floating-level state.