Patent ID: 7260495
Filing Date: 2007-08-21
Classification: G06F

Abstract:
1. A method, in a data processing system, for performing a system level verification, comprising: selecting an iterative parallel algorithm for performing the system level verification; separating the iterative parallel algorithm into separate program statements that may be independently executed on separate processors of the data processing system using a parallel compiler to separate the iterative parallel algorithm into separate program statements; executing the iterative parallel algorithm in a serial manner to generate an expected results data set; executing the separate program statements in a parallel manner to generate a system level test results data set; comparing the system level test results data set to the expected results data set; determining if the system operates properly at a system level based on results of the comparison; and providing an output indicative of either an error state or a proper operational state based on results of determining if the system operates properly at a system level.