Patent ID: 6661052
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A semiconductor device comprising:a plurality of trench type device isolation regions formed in a semiconductor substrate; a plurality of semiconductor active regions electrically isolated by the device isolation regions; a first electrode layer self-aligned to the trench type device isolation regions; and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the device isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the semiconductor active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the semiconductor active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.