Patent ID: 6384485
Filing Date: 2002-05-07
Classification: H01L,H05K

Abstract:
A semiconductor device provided with a multi-layer substrate, a semiconductor chip provided above said multi-layer substrate, and external connection electrodes provided below said multi-layer substrate, whereinsaid multi-layer substrate includes: a core layer having a plurality of through holes for electrically connecting an upper side with a lower side; an upper multi-layer portion provided above said core layer; a lower multi-layer portion provided below said core layer; a plurality of chip electrode lands provided on an upper surface of said upper multi-layer portion for electrically connecting to electrodes of said semiconductor chip; and a plurality of signal lines for electrically connecting said chip electrode lands respectively to said external connection electrodes, wherein said upper multi-layer portion and said lower multi-layer portion are each formed by a plurality of component layers and include via holes for electrically connecting said signal lines belonging to different ones of said component layers, said plurality of component layers include a signal layer provided mainly for routing of said signal lines to desired positions in plan view within each same layer, and plane layers provided mainly for disposing conductor planes that sandwich said signal layer, said signal layer in said upper multi-layer portion includes a first specific signal layer and a second specific signal layer provided under said first specific signal layer without providing one of said plane layers therebetween, said signal lines extending from within a projected region of said semiconductor chip toward outside the region in said first specific signal layer are routed to said via holes connected to said through holes respectively selected from among all said through holes such that a distance of longest signal line of all said signal lines routed within said first specific signal layer becomes the shortest possible, and are connected to said lower multi-layer portion via said through holes, and are further routed in said lower multi-layer portion to said via holes leading to said external connection electrodes to which said signal lines are to be connected, said signal lines extending from within the projected region of said semiconductor chip toward outside the region in said second specific signal layer are routed to said via holes leading to said through holes substantially closest, when seen from above, to said external connection electrodes to which said signal lines are to be connected, and are connected to said lower multi layer portion via said through holes, and a conductor plane is disposed in a region other than a portion in which said signal lines are disposed in said first specific signal layer.