Patent ID: 6594275
Filing Date: 2003-07-15
Classification: H04L

Abstract:
A low power, high speed, serial to parallel data converter for converting asynchronous serial data into clock aligned, framed, parallel data, the data converter comprising:a serial in, parallel out register for receiving asynchronous serial data and for providing unframed parallel data, the serial in, parallel out register has a smaller bit size than a bit size of the clock aligned, framed parallel output word; an array of a plurality of parallel in, parallel out registers coupled to receive parallel data from the serial in, parallel out register and configured to move the data in a parallel fashion between parallel in, parallel out registers thereof, each parallel in, parallel out register having the smaller bit size of the serial in, parallel out register; a pattern detection circuit coupled to read data within the array of parallel in, parallel out registers for identifying a location of a delimiter character within the array of parallel in, parallel out registers; a selection circuit coupled to read selected data bits from the array of parallel in, parallel out registers, selection of the data bits to be read being based upon the location of the delimiter character, the selection circuit defining a framed parallel output word; and a data alignment circuit coupled to receive the framed parallel output word from the selection circuit for aligning the framed parallel output word with respect to a clock to define a clock aligned, framed parallel output word.