Patent ID: 6759289
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:forming a first plurality of buried layers of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each of the first plurality of buried layers being disposed it a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type are formed within the first substrate; bonding the first surface of the first substrate to a second substrate of the first conductivity type; thinning the first substrate from the second surface; forming a second plurality of buried layers of the first conductivity type in the first substrate, each of the second plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type are formed within the first substrate.