Patent ID: 9177092
Filing Date: 2015-11-03
Classification: G06F

Abstract:
1. An arrangement and wiring method of a reconfigurable semiconductor device, characterized by comprising: generating a net list based on a circuit description in which a circuit configuration is described; extracting a sequential circuit data set which is to be scanned from the net list; generating a first truth value table data set so as to write into a first set among plurality of memory cell units from the sequential circuit data set which is to be scanned; and generating a second truth value table data set so as to write into a second set among the plurality of memory cell units from a combination logic circuit data set of the net list; wherein the reconfigurable device includes the plurality of memory cell units configuring arrays and are connected to each other, and the memory cell units operate as a logic element when truth value table data is written in configured so as to output a logic calculation of an input value specified by a plurality of addresses to a data line, and/or operate as a connection element when truth value table data is written in configured so as to output an input value specified by a certain address to a data line connected to an address of another memory cell unit, and wherein a memory cell unit to which the first truth value table data set is allotted is simulated with an execution in synchronization with a clock, and/or the plurality of the second truth value table data sets are simulated with an execution in non-synchronization with the clock, and whether the semiconductor device realizes a certain operation speed is evaluated.