Patent ID: 8730954
Filing Date: 2014-05-20
Classification: H04L,H04Q

Abstract:
1. An apparatus, comprising; a switch core defining a single logical entity and having a multi-stage switch fabric physically distributed across a plurality of chassis, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports, the switch core configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed with a second chassis, the switch core configured to provide non-blocking connectivity at line rate between the second peripheral processing device and a third peripheral processing device, the switch core configured to receive a first packet associated with the first peripheral processing device, the switch core configured to send sequentially a second packet to the second peripheral processing device and a third packet to the third peripheral processing device based on cells associated with the first packet, the multi-stage switch fabric configured to send the cells from ingress ports from the plurality of ingress ports to egress ports from the plurality of egress ports.