Patent ID: 7072212
Filing Date: 2006-07-04
Classification: G11C

Abstract:
1. A memory device, comprising: a plurality of memory cells arranged in rows and columns, in NOR configuration, each one of the plurality of memory cells being configured to accept a data bit at a programming input in a presence of an enable voltage at a program enable input, and being configured to store the bit of data as one of a plurality of logic levels, the memory cells including a first group of memory cells; a plurality of bit registers for storing data bits to be programmed in the memory cells of the first group; a program voltage generator having an output at which is supplied a program voltage for programming the memory cells; timing means for supplying a read enable signal to a first enable input of the plurality of bit registers, sequentially, to enable each one of the plurality of bit registers to receive a successive one of a stream of data bits; and enabling means for providing a write enable signal at a second enable input of each of the plurality of bit registers simultaneously, and further, for concurrently providing the enable voltage at the program enable input of each of the plurality of memory cells; and connection means for selectively connecting the output of the program voltage generator to the programming inputs of the memory cells of the first group according to the data bits stored in the bit registers, such that only those memory cells of the first group that require programming according to the data bits stored in the bit registers are connected to the program voltage generator.