Patent ID: 6205523
Filing Date: 2001-03-20
Classification: G11C

Abstract:
A method for accessing a plurality of sets of memories via N data buses, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2 memories, the method comprising providing memory access allowing (i) a plurality of successive read operations to be performed immediately following one another, and at the same time, (ii) a plurality of successive write operations to be performed immediately following one another, wherein:in each write operation, when data is written to a memory in one of said sets of memories, the data is written in parallel to all of the memories in the same set of memories;in each read operation, any N/2 of said memories are allowed to be read in parallel via corresponding N/2 of said data buses selected for the read operation, and in each write operation, N/2 of said memories in respective different N/2 of said sets are allowed to be written in parallel via corresponding N/2 of said data buses selected for the write operation;wherein each of said data buses is provided a read memory access in at least one of said read operations, and a write memory access in at least one of said write operations.