Patent ID: 7605037
Filing Date: 2009-10-20
Classification: G11C,H01L

Abstract:
1. A manufacturing method for an integrated semiconductor memory device comprising the steps of: providing a semiconductor substrate; forming a plurality of active area lines in said semiconductor substrate, each of which active area lines includes a plurality of memory cell selection transistors having a respective wordline contact, bitline contact, and node contact; forming a plurality of filled insulation trenches arranged between said active area lines; forming a plurality of wordlines running perpendicular to said active area lines and being connected to the wordline contacts of the memory cell selection transistors of corresponding active area lines; forming a plurality of rewiring stripes each of which rewires an associated node contact of a memory cell selection transistor from an active area line to above a neighboring filled insulation trench so as to form a respective rewired node contact; forming a plurality of bitlines being aligned with an running above said active area lines and being connected to the bitline contacts of the memory cell selection transistors of the respective active area lines; and forming a plurality of memory cell capacitors each of which is connected to a respective rewired node contact of an associated memory cell selection transistor.