Patent ID: 8809835
Filing Date: 2014-08-19
Classification: H01L,H03B,H03K,H03L

Abstract:
1. A semiconductor structure comprising: a first source region and a second source region in a substrate, the first source region and the second source region being electrically coupled together; a first drain region and a second drain region in the substrate, the first drain region and the second drain region being electrically coupled together, the first drain region being disposed between the first source region and the second source region, and the second source region being disposed between the first drain region and the second drain region; and a first channel region, a second channel region, and a third channel region, the first channel region being disposed between the first source region and the first drain region, the second channel region being disposed between the first drain region and the second source region, the third channel region being disposed between the second source region and the second drain region, each of the first channel region, the second channel region, and the third channel region comprising a strained channel layer disposed on the substrate thereby defining an interface therebetween, the strained channel layer having a proximate region proximate the interface and a distal region away from the interface, wherein the substrate has an impurity with a first concentration, the proximate region has the impurity with a second concentration, the distal region has a third concentration of the impurity substantially equal to zero throughout a thickness of at least 50 Angstroms of the strained channel layer in the distal region, a continuously decreasing concentration of the impurity being from the second concentration in the proximate region to the third concentration in the distal region.