Patent ID: 9007845
Filing Date: 2015-04-14
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells, the memory cells including a first memory cell and a second memory cell; a plurality of bit lines electrically coupled to the memory cells; a first source line electrically coupled to the first memory cell; a second source line electrically coupled to the second memory cell; a driver including a first unit, the first unit including a first differential amplifier, a first transistor, a second transistor, and a third transistor, a first terminal of the first differential amplifier being electrically coupled to the second transistor and the third transistor, a second terminal of the first differential amplifier being electrically coupled to the first source line, and an output terminal of the first differential amplifier being electrically coupled to a gate of the first transistor; a first line electrically coupled to the second transistor; and a second line electrically coupled to the third transistor.