Patent ID: 9123600
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A microelectronic package comprising: (a) a package substrate having upper and lower surfaces and terminals at the lower surface; (b) first and second chips disposed above the package substrate, each of the first and second chips having a front face, a rear face and contacts at the front face disposed in one or more columns extending in a column direction, the first and second chips being offset from one another by a center-to-center offset distance in a lateral direction transverse to the column direction; (c) interconnect pads disposed in an elongated interconnect zone having a width less than the offset distance, the interconnect pads facing toward the package substrate at least some of the interconnect pads being electrically connected to at least some of the contacts of the first and second chips, at least some of the interconnect pads being electrically connected to at least some of the terminals of the package substrate.