Patent ID: 8842793
Filing Date: 2014-09-23
Classification: H04L

Abstract:
1. A communication circuit that receives communication data in asynchronous serial communications, the communication circuit comprising: a start bit detection circuit to detect a start bit of the communication data; a reception control circuit to generate a clock signal that is synchronized with the start bit; a sampling clock generating circuit configured to generate a sampling clock signal according to the clock signal that is generated by the reception control circuit; a sampling circuit configured to sample the communication data based on the sampling clock signal having a frequency that is “m” times greater than a bit rate of the communication data and containing “n” pulses in each bit period of the communication data, “m” being an integer greater than or equal to 4, “n” being an odd number less than “m” to obtain “n” sets of received data; and a majority circuit configured to perform a majority operation on values of “n” sets of received data in each bit period of the communication data to determine a majority value and to output the majority value as received data of the corresponding bit period, wherein the sampling clock generating circuit is configured to delay the sampling clock signal by a predetermined amount relative to the start bit when a value of a first one or more of the “n” sets of received data is different from a value of a rest of the “n” sets of received data, and to advance the sampling clock signal by the predetermined amount relative to the start bit when a value of a last one or more of the “n” sets of received data is different from a value of a rest of the “n” sets of received data.