Patent ID: 9057762
Filing Date: 2015-06-16
Classification: G01R

Abstract:
1. A method, executed by at least one processor of a computer, comprising: identifying no-failing-bits output channels of a compactor based on output data of a test, the no-failing-bits output channels outputting no failing bits during the test; identifying good scan chains based on scan chains associated with the no-failing-bits output channels; and analyzing bits outputted from failing-bits output channels per clock cycle to identify one or more suspected faulty scan chains from scan chains other than the good scan chains, each of the failing-bits output channels outputting at least one failing bit during the test, each of the one or more suspected faulty scan chains solely explaining failing bits outputted from all output channels in the failing-bits output channels that are associated with the each of the one or more suspected faulty scan chains for at least one clock cycle.