Patent ID: 6156665
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A process for the manufacture of semiconductor integrated circuit devices which includes at least one step of forming a metallization pattern on a III-V semiconductor substrate the method comprising:a. depositing a first resist layer of a polymer resist material on said III-V semiconductor substrate,b. depositing by electron beam evaporation an intermediate layer over the first resist layer, said intermediate layer comprising at least SiO.sub.x where x is in the range 1.8-3.0,c. depositing a second resist layer of a polymer resist material on said intermediate layer,d. lithographically patterning said second resist layer with a metallization pattern,e. transferring said metallization pattern to said intermediate layer by etching said intermediate layer using said patterned first resist layer as a mask,f. transferring said metallization pattern to said first resist layer by patterning said first resist layer using said intermediate layer as a mask, thereby exposing regions of said III-V semiconductor substrate,g. depositing a layer of metallization over said second resist layer with portions of said metallization layer depositing on said exposed regions of said III-V semiconductor substrate and portions of said metallization layer depositing on said second resist layer, andh. removing said first and second resist layers, said intermediate layer, and said portions of said metallization layer on said second resist layer by dissolving said first and second resist layers thereby leaving said portions of said metallization layer on said exposed portions of said III-V semiconductor substrate.