Patent ID: 6553446
Filing Date: 2003-04-22
Classification: G06F

Abstract:
A bi-modal peripheral controller for a computer system, comprising:a) at least two high-speed buses; b) at least one low-speed bus; c) a packet switched router of data from a first of the high-speed or low-speed buses to a second of the high-speed or low-speed buses, comprising a plurality of communication paths permitting simultaneous multiple communications between any of the high-speed or low-speed buses; d) a bridge coupled between the router and each low-speed bus; e) a plurality of write buffers, coupled to each bridge, which couple a plurality of write transactions on the low-speed bus coupled to that bridge into a cache line sized transfer to the router; f) a plurality of read buffers, coupled to each bridge, in which each read buffer stores fetched data according to a read request from a device connected to the low-speed bus coupled to that bridge so that the device can access the read buffers multiple times to retrieve the data; g) a prefetcher, coupled to each bridge, which reads sequential cache lines until the read buffers are full, a page boundary is encountered, or the read buffers are caused to be flushed, if the device connected to the low-speed device coupled to that bridge generates a read request and there is no corresponding data contained in the read buffers; and h) means for selecting between first and second modes, in which the first mode permits the router to connect any high-speed bus to any other bus, and the second mode permits the router to connect high-speed buses only to low-speed buses.