Patent ID: 7969760
Filing Date: 2011-06-28
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: (a) a local data line formed along a first direction; (b) a global data line formed over an upper surface of the local data line, the global data line being formed along the first direction; (c) a word line formed along a second direction perpendicular to the first direction; and (d) a charge accumulation portion formed in an intersecting region at which the local data line and the word line intersect in plan view, wherein the semiconductor memory device stores information based on change of an electric current flowing through the local data line corresponding to a charge accumulated in the charge accumulation portion, wherein the semiconductor memory device includes at least two of said local data lines, each being electrically connected to said global data line, wherein said global data line and a first local data line of said at least two local data lines are connected by a first select transistor, and said global data line and a second local data line of said at least two local data lines are connected by a second select transistor, wherein the first select transistor includes: (e1) a first gate electrode layer formed over an upper surface of the first local data line; (e2) a first portion of a first select line formed along the second direction over a first upper surface portion of the first gate electrode layer; and (e3) a first portion of a second select line formed along the second direction over a second upper surface portion of the first gate electrode layer, wherein the second select transistor includes: (f1) a second gate electrode layer formed over an upper surface of the second local data line; (f2) a second portion of the first select line formed along the second direction over a first upper surface portion of the second gate electrode layer; and (f3) a second portion of the second select line formed along the second direction over a second upper surface portion of the second gate electrode layer, wherein the first select line is connected to the first gate electrode layer and selects the first local data line, and wherein the second select line is connected to the second gate electrode layer and selects the second local data line.