Patent ID: 8180976
Filing Date: 2012-05-15
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a memory cell array comprising a plurality of memory cells, wherein each of the memory cells is programmable to store one bit having a first logic value or a second logic value; a data scanning unit configured to search among a plurality of data bits that are to be programmed together at a same address of a plural number (M) of the memory cells to identify individual ones of the data bits having the second logic value among other intervening ones of the data bits having the first logic value; and a program unit configured to program a plural number (N) of the data bits, which have been identified by the data scanning unit as having the second logic value, at a same time into corresponding ones of the addressed memory cells while at that same time not programming the intervening data bits having the first logic value into the corresponding intervening other ones of the addressed memory cells, wherein the number (N) is less than the number (M), wherein the data scanning unit comprises: a scan clock generating unit configured to generate a plurality of scan clock signals in response to an internal clock signal; and a data latch unit configured to search among the plurality of data bits and to identify individual ones of the data bits having the second logic value responsive to the plurality of scan clock signals.