Patent ID: 6307217
Filing Date: 2001-10-23
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit device, comprising:a semiconductor substrate having a main surface;a plurality of memory cells of a static random access memory, said plurality of memory cells being arranged in a row and a column direction, each of said plurality of memory cells including a first driver MISFET and a second driver MISFET and a first load MISFET and a second load MISFET;each of said first and said second driver MISFETs having a gate electrode overlying said main surface and a source region and a drain region in said semiconductor substrate;a first insulating film overlying said first and said second driver MISFETs so as to cover said main surface;first conductive strips overlying said first insulating film, wherein a source region, a drain region and a channel-forming region of each of said first and second load MISFETs are provided in said first conductive strips, and wherein the drain regions of said first and second load MISFETs are electrically connected to the drain regions of said first and second driver MISFETs, respectively;gate electrodes of said first and second load MISFETs, overlying said first conductive strips, wherein said gate electrodes of said first and second load MISFETs are electrically connected to said drain regions of said second and first driver MISFETs, respectively;gate insulating films of said first and second load MISFETs, provided between the channel-forming regions and the gate electrodes thereof;a second insulating film overlying said first conductive strips and said gate electrodes of said first and said second load MISFETs; anda power source applying layer overlying said second insulating film so as to cover said plurality of memory cells, said power source applying layer being electrically connected to the source regions of said first and second load MISFETs of said plurality of memory cells, said gate electrodes of said first and said second load MISFETs, said second insulating film and said power source applying layer constituting capacitor elements.