Patent ID: 7491609
Filing Date: 2009-02-17
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device comprising: forming a plurality of laminated structure layers on a semiconductor substrate, the laminated structure layers each including a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a lower etching rate than that of the first semiconductor layer, wherein the first and second semiconductor layers both have a back surface and a top surface; providing a step to expose the top surface of the second semiconductor layer in the lower laminated structure layer and forming a first groove passing through the first and second semiconductor layers to expose the semiconductor substrate and create first groove sidewalls; forming supports on the first groove side walls of the first and second semiconductor layers in the first groove, for supporting the second semiconductor layers on the semiconductor substrate; forming a second groove to expose at least a portion of the first semiconductor layer, on which the supports have been formed on the side walls, from the second semiconductor layers; selectively etching the first semiconductor layers through the second groove to partially remove the first semiconductor layers and form a first cavity intermediate the semiconductor substrate and second semiconductor layer closer to the semiconductor substate as well as a second cavity intermediate the second semiconductor layers; thermally oxidizing the semiconductor substrate and the second semiconductor layers through the first and second grooves to fill in the cavities and form insulating layers at the back surfaces of the second semiconductor layers; thermally oxidizing the uppermost second semiconductor layer to form a gate insulating film on the top surface of the uppermost second semiconductor layer; forming a gate electrode on the uppermost second semiconductor layer with the gate insulating film formed therebetween; and implanting ions using the gate electrode as a mask to form source and drain layers in the uppermost second semiconductor layer on both sides of the gate electrode.