Patent ID: 6212249
Filing Date: 2001-04-03
Classification: G11B,H03L,H04L

Abstract:
A data separation circuit, comprising:a reference clock generating circuit generating a reference clock according to a data rate at which data is being read;a phase detecting part determining a phase difference state between said reference clock and a window signal;a digital control oscillator generating a pulse of said window signal based on said phase difference state;a phase/frequency controller generating a first count and a second count, said first count representing a total amount of time said phase detecting part determines a first state during a first predetermined period of time, said second count representing a total amount of time said phase detecting part determines a second state during said first predetermined period of time, and said phase/frequency controller generating a control signal based on said first and second counts, wherein said digital control oscillator generating said pulse of said window signal based on said control signal; anda data/clock output unit outputting a data signal and a clock signal based on said read data and said window signal.