Patent ID: 7109746
Filing Date: 2006-09-19
Classification: H03K

Abstract:
1. A programmable logic device, comprising: a configurable logic block, the configurable logic block having function generators, each of the function generators configurable for at least two programmable mode functions; the function generators coupled to an array of memory cells, the array of memory cells for storing configuration bits for configuring the function generators; a primary address line coupled to each memory cell of the array of memory cells in a segment spanning two or more of the function generators; a secondary address line coupled to groups of memory cells of the array of memory cells in separate segments, each of the separate segments spanning only one function generator of the function generators, the groups of memory cells being respectively associated with the function generators; and a mask circuit configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the programmable mode function programmed.