Patent ID: 6821846
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A method of manufacturing a DRAM, comprising:providing a substrate having a cell region and a logic circuit region, wherein the substrate has a first dielectric layer on the cell region and the logic circuit region, and wherein a bit line is formed on the first dielectric layer of the cell region and a first metal layer is formed on the first dielectric layer of the logic circuit region; forming a second dielectric layer on the bit line, the first dielectric layer and the first metal layer; forming a bottom contact in the second dielectric layer of the logic circuit region to electrically connect to the first metal layer, and forming a node contact in the first and second dielectric layers of the cell region to electrically connect to one active device on the substrate; forming a first capacitor on the second dielectric layer of the cell region and a second capacitor on the second dielectric layer of the logic circuit region, the first capacitor electrically connecting to the node contact and the second capacitor electrically connecting to the bottom contact, wherein a top portion of an upper electrode and a portion of the capacitor dielectric layer of the second capacitor are removed, and wherein a remaining portion of the upper electrode of the second capacitor serves as a middle contact electrically connecting the bottom contact; forming a third dielectric layer on the first capacitor, the middle contact and the second dielectric layer; and forming a top contact in the third dielectric layer of the logic circuit region to electrically connect to the middle contact.