Patent ID: 6307786
Filing Date: 2001-10-23
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of memory cells each comprising a first transistor having a first electrode, a second electrode, a gate electrode, and a floating gate electrode between the gate electrode and a first gate oxide film;a plurality of first data lines each connected to the first electrode of at least one first transistor;a second data line;a plurality of second transistors each having a third electrode electrically connected to one of the plurality of first data lines, a fourth electrode electrically connected to the second data line, a gate electrode to which one of a plurality of selection signals is inputted and a second gate oxide film, the second transistor being used to erase data from the memory cells; anda decoder for generating the plurality of selection signals having voltage levels respectively set in response to address information;wherein the plurality of selection signals are rendered a predetermined voltage level when a high voltage, which is higher than a power supply voltage, is applied to desired gate electrodes of the plurality of memory cells and wherein the first and second gate oxide films have the same thickness.