Patent ID: 6754783
Filing Date: 2004-06-22
Classification: G06F,G11C,Y02D

Abstract:
A memory controller for controlling a plurality of dynamic memory devices, comprising:a cache for storing a plurality of entries that indicate a current power state for each of the plurality of the dynamic memory devices, wherein the plurality of entries includes, at most, a first predefined maximum number of entries specifying dynamic memory devices in a predefined mid-power state; device state lookup logic, coupled to the cache, for responding to a memory access request that includes an address that includes a device address by retrieving first information from an entry, if any, in the cache corresponding to the device address, for generating a miss signal when the cache has no entry corresponding to the device address, and for simultaneously retrieving fullness information from the cache indicating whether the cache has stored therein said first predefined maximum number of entries specifying dynamic memory devices in the predefined mid-power state; additional logic for converting the first and fullness information and miss signal into at least one update control signal; and cache update logic for updating information stored in the cache in accordance with the at least one update control signal.