Patent ID: 9099473
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a first conductive line crossing over a field isolation region and crossing over an active region of the device, the first conductive line including a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern, wherein the first conductive line crosses over the field isolation region and over the active region in a cell array region of the device, the device further comprising: a second conductive line crossing over a field isolation region and over an active region in a peripheral region of the device, the second conductive line including a third conductive pattern being doped, and a fourth conductive pattern, and a metal-silicon-nitride pattern between the third and fourth conductive patterns and configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the third conductive pattern and a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the fourth conductive pattern in the peripheral region.