Patent ID: 6830981
Filing Date: 2004-12-14
Classification: B82Y,H01L,Y10S

Abstract:
A process for fabricating a vertical nanotube transistor, comprising the following steps:successively forming a source layer and a catalyst layer on a substrate; forming a dielectric layer on the catalyst layer and the substrate; selectively removing the dielectric layer to form a first dielectric mesa on the catalyst layer, a gate dielectric layer on the substrate to align with a sidewall of the catalyst layer and the first metal layer, and a second dielectric mesa on the substrate, wherein the first dielectric mesa and the gate dielectric layer are spaced apart by a first opening, and the gate dielectric layer and the second dielectric mesa are spaced apart by a second opening; forming a nanotube layer in the first opening; and forming a drain layer on the nanotube layer and the first dielectric mesa and forming a gate layer in the second opening.