Patent ID: 7429765
Filing Date: 2008-09-30
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory comprising a memory cell array and a peripheral circuit: the memory cell array comprises: a first device region and a first device isolating region, which have a striped pattern that extends in a first direction, the first device region and the first device isolating region being alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; a contact of a first conductive material, connected to the first device region and disposed at the first pitch in the second direction, and an extending line, being the same material as the first conductive material and connected to the top of the contact, and the peripheral circuit comprises: a transistor having a diffusion layer disposed in between second device isolating regions; and a peripheral transistor contact connected to the diffusion layer, wherein, on a cross section along the second direction, a bottom width of the contact is longer than the top width of the contact, the bottom width is longer than the width of the first device region, the contact and at least a part of the extending line is formed as a unit, and a height of a top surface of the peripheral transistor contact is higher than a height of a top surface of the contact.