Patent ID: 6803289
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method for fabricating a bipolar transistor, comprising:depositing an intermediate layer above a semiconductor topography; patterning an opening within the intermediate layer using a resist mask; exposing the semiconductor topography to a stripping process to remove the resist mask and expose portions of the intermediate layer, wherein the intermediate layer comprises a material substantially etch resistant to the stripping process; depositing a conductive layer within the opening and upon exposed portions of tie intermediate layer; patterning the conductive layer to form an emitter structure of the bipolar transistor; and patterning the exposed portions of the intermediate layer in alignment with a patterned portion of the conductive layer using substantially similar etch process parameters as used in the step of patterning the conductive layer, wherein the stop of patterning the conductive layer comprises: patterning the conductive layer to form the patterned portion of the conductive layer; and re-patterning the conductive layer subsequent to the step of patterning the intermediate layer in alignment with the patterned portion of the conductive layer to expose portions of the patterned intermediate layer.