Patent ID: 6090653
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method for manufacturing a CMOS device on a semiconductor substrate, the method comprising:forming a gate oxide layer on said semiconductor substrate;forming an undoped polysilicon layer on said gate oxide layer;forming a silicon nitride layer on said undoped polysilicon layer to act as an anti-reflective layer;patterning said silicon nitride layer, said undoped polysilicon layer and said first oxide layer to form gate structures on said semiconductor substrate;performing a first ion implantation to form relatively light doped drain structures adjacent to said gate structures;forming oxide spacers on side walls of said gate structures;performing a second ion implantation with a tilted angle with respect to a normal line of said semiconductor substrate to dope nitrogen into said semiconductor substrate, said oxide spacers and said silicon nitride layer, and to form extended doped regions under a portion of said gate;removing said silicon nitride layer;forming a metal layer on said semiconductor substrate, said oxide spacers and said silicon nitride layer;performing a first thermal process to react said metal layer with said semiconductor substrate and said gates;removing non-reactive portion of said metal layer, thereby forming a self-aligned silicide (SALICIDE) on said semiconductor substrate and a polycide on said gate structures;performing a third ion implantation to dope dopants into said SALICIDE and said polycide; andperforming a second thermal process to form source and drain junction by diffusing dopants in said SALICIDE.