Patent ID: 6373106
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a plurality of element isolation region formed on the substrate; at least one first MOS transistor having first source and drain regions of a first conductive type and a first channel region formed therebetween, and formed between two neighboring element isolation regions on a well region of a second conductive type; at least one second MOS transistor formed on the substrate between two neighboring element isolation regions, and having second source and drain regions of the first conductive type and a second channel therebetween; at least one first sub-well region of the second conductive type formed in the substrate below a top surface of the second channel region; and a plurality of second sub-well regions of the second conductive type formed in the substrate below the element isolation regions and spaced apart from the first sub-well region, the plurality of second sub-well regions partially overlapping the second source and drain regions at edges of the element isolation regions wherein the well region and the first and second sub-well regions have substantially the same impurity concentration of the second conductive type and are of substantially the same depth below an upper surface of the substrate.