Patent ID: 6801067
Filing Date: 2004-10-05
Classification: H03K,H03L

Abstract:
An analog synchronous mirror delay (ASMD) circuit, comprising:a comparator with first and second input terminals end generating an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal; a first precharge circuit connected to the first input terminal and precharging the first input terminal; a second precharge circuit connected to the second input terminal and precharging the second input terminal; a first discharge circuit discharging the first input terminal for a given period within a first cycle of an input clock; a first additional discharge circuit discharging the first input terminal for a first logic-state period of the input clock within first and second cycles of the input clock; a second discharge circuit discharge the second input terminal for the second cycle of the input clock; and a second additional discharge circuit discharging the second input terminal for a second logic-state period of the input clock within the first and second cycles of the input clock.