Patent ID: 9001593
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. An apparatus for use in a memory array, the memory array comprising a plurality of memory elements, with each memory element comprising a read word line and a write word line, wherein each write word line is coupled to a write word line driver and each read word line is coupled to a read word line driver, the apparatus comprising: a predecode stage including: a write NAND gate of a decode stage for the memory array, wherein the write NAND gate is configured to receive the plurality of predecoded write address signals and to provide a write output signal to a write word line driver based on the write address signals, the write output signal selectively enabling the write word line driver to drive the write word line of a particular memory element for a memory write operation; and a read NAND gate of the decode stage configured to receive the plurality of predecoded read address signals and the write output signal and to provide a read output signal to a read word line driver based on the read address signals and the write output signal, wherein the read output signal selectively enables the read word line driver to drive a read word line of the particular memory element for a memory read operation, wherein the read NAND gate is further configured to enable the read word line driver only if the write output signal and the read address signals are at a logic high.