Patent ID: 6610262
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A method of forming a low input capacitance depletion mode SCR and isolated N channel FET ESD protection device on a semiconductor substrate comprising:creating a N-well within said semiconductor substrate; creating multiple STI structures within said substrate bridging said N-well and said substrate boundary in the surface region; creating gate elements on said substrate surface; creating N+ source and drain areas within said substrate on either side of said gate elements forming NFET elements; insuring said gate elements and said NFET N+ drain elements are electrically floating; creating a P+ contact region within said N-well region and creating P+ contact regions within said substrate outside of said N-well region; creating a first and second electrical conductor system for said ESD protection device; creating passivation for said ESD protection device.