Patent ID: 8488403
Filing Date: 2013-07-16
Classification: G11C

Abstract:
1. An offset cancelling sense amplifier configuration comprising: a latch comprising first and second latch node; and first and second bitlines; and first and second column multiplexor transistors; and said first and second latch nodes selectively coupled to said first and second bitlines via said first and second column multiplexor transistor; and column select timing signal; and gates of said first and second column multiplexor transistors selectively coupled to said column select timing signal; and one activation signal; and said latch activated by said activation signal; and first and second circuit configuration; and first and second control signal; and said first circuit configuration capable of discharging said first and second latch nodes and said first and second bitlines to ground voltage level; and said first circuit configuration enabled by first control signal; and said second circuit configuration capable of precharging said first and second latch nodes to VDD and said first and second bitlines to (VDD—threshold voltage) level, wherein threshold voltage is of said first and second column multiplexor transistor; and said second circuit configuration enabled by said second control signal, wherein said second circuit configuration is capable of compensating threshold mismatch of said column multiplexor transistors.