Patent ID: 8043772
Filing Date: 2011-10-25
Classification: G03F

Abstract:
1. A manufacturing method of a semiconductor device comprising an exposure process for forming a predetermined circuit pattern of a semiconductor device on a semiconductor wafer, wherein the exposure process includes: a first process for measuring past resist dimensions of a resist pattern formed on a first semiconductor wafer and a focus position at an exposure processing; a second process for estimating resist dimensions and a focus position of a second semiconductor wafer to which the exposure process will be performed next by using measurement results of the resist dimension and the focus position measured in the first process; after calculating a focus offset value of the second semiconductor wafer, a third process for calculating an exposure dose of the second semiconductor wafer with considering this focus offset value by using estimation values of the resist dimensions and the focus position estimated in the second process; and a fourth process for forming a resist pattern on the second semiconductor wafer by using the exposure dose and the focus offset value calculated in the third process.