Patent ID: 6810514
Filing Date: 2004-10-26
Classification: G06F

Abstract:
A circuit arrangement for partially reconfiguring a programmable logic device (PLD) having a plurality of reconfigurable resources, comprising:a configuration store arranged for storage of configuration data for a selected subset of the reconfigurable resources; a modification store configured with addresses and associated data values, wherein each address references an address in the configuration store, and each associated data value indicates a configuration state for one of the reconfigurable resources of the PLD; and a controller coupled to the configuration and modification stores and to the PLD, the controller arranged to, in response to a reconfiguration signal, read at least one address and at least one associated data value from the modification store, update the configuration store at the at least one address read from the modification store with the at least one associated data value, and download configuration data from the configuration store to the PLD.