Patent ID: 7304874
Filing Date: 2007-12-04
Classification: G11C,H01L

Abstract:
1. A content addressable memory (CAM) cell, comprising: a first static random-access memory (SRAM) bitcell comprising two p-type transistors and four n-type transistors, said first SRAM bitcell being connected to a wordline, a source voltage, a drain voltage, and a first pair of complementary bitlines, such that a first bit can be stored in said first SRAM bitcell, wherein the layout of the first SRAM bitcell is asymmetric; and a first comparison circuit and a second comparison circuit, each comprising two n-type transistors, wherein said first comparison circuit and said second comparison circuit are connected to compare the value of said CAM cell to a value carried by a first and a second hitline; wherein the layout of said first SRAM bitcell and the layout of a second SRAM bitcell that shares a side with said first SRAM bitcell are 180 degree rotations of each other within the plane of the layout such that said first pair of complementary bitlines traverse identical surface structures and have equal capacitance loading.