Patent ID: 7971036
Filing Date: 2011-06-28
Classification: G06F

Abstract:
1. An apparatus for providing a memory hardware assist function, the apparatus comprising: at least one processing element (PE) having a PE interface, a PE address storage unit, a PE data storage unit, and PE execution units for execution of PE instructions, wherein an execution of a PE function instruction functionally operates on data accessed from the PE data storage unit; at least one memory having a first memory interface and a second memory interface, the at least one memory is directly associated with the at least one PE over the first memory interface, wherein an execution of a PE load instruction loads data from the at least one memory at a first address over the first memory interface to the PE data storage unit and an execution of a PE store instruction stores data from the PE data storage unit over the first memory interface to the at least one memory at a second address, wherein the first address and the second address are based on address values selected from the PE address storage unit; an instruction decode function which decodes a memory hardware assist instruction that is an instruction in the instruction set architecture of the at least one processing element, the memory hardware assist instruction specifies an operation that selects a third address from the PE address storage unit, a data value from the PE data storage unit, and causes control signals to be generated and connected to the PE interface; and a memory hardware assist unit coupled to the second memory interface of the at least one memory and coupled to the PE interface of the at least one PE, the memory hardware assist unit, after being initiated by the third address, the data value, and the control signals received from the PE interface, iteratively fetches a plurality of source operands over the second memory interface from the at least one memory to the memory hardware assist unit in parallel with the PE instructions executing on the PE execution units in the at least one PE and the memory hardware assist unit generates at least one result operand that is selectively stored over the second memory interface in the at least one memory.