Patent ID: 7370250
Filing Date: 2008-05-06
Classification: G11C

Abstract:
1. A test pattern for testing a path internal to a memory chip, comprising: a) a test word and a complement test word, wherein said complement test word is a logical complement of said test word; b) said test word comprising a sequence of data bits of a same value followed by a last data bit of opposite value; c) said test word coupled to a conductive element of a data path, wherein said data path comprises a plurality of conductive elements routed in parallel, and wherein each conductive element of said plurality of conductive elements comprise a data driver circuit, a receiver circuit and a wire connecting said driver to said receiver; d) said complement test word coupled to an immediately adjacent conductive element of said data path; e) said test word and said complement test word execute simultaneously and form a test pattern to test said data path; and f) successful receipt of said last data bit by said receiver circuit determines goodness of the element of the data path.