Patent ID: 6489817
Filing Date: 2002-12-03
Classification: H03K

Abstract:
A clock divider comprising:a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, wherein at least one of the first input signal and the second input signal comprises an input clock signal having an input clock signal period, further wherein the third input signals comprise the first output signal and the second output signal, and further wherein the third output signal comprises an output clock signal having an output clock signal period, wherein the output clock signal period is a multiple of the input clock signal period; further wherein at least one of the positive edge triggered state machine and the negative edge triggered state machine comprises a state machine combination logic to determine a next state based on a current state and the input clock signal.