Patent ID: 7516372
Filing Date: 2009-04-07
Classification: G06F

Abstract:
1. A processor control system, for use with a processor, the control system comprising: means for receiving a sequence of addresses, each address comprising first and second pluralities of address bits; a first memory, for containing a set of instructions for the processor at memory locations in said first memory corresponding to all of said addresses; a second memory, suitable for containing only correction instructions for the processor at memory locations in said second memory corresponding to respective combinations of said first plurality of address bits; means for determining, for each received address, when all of said second plurality of address bits in the received address are equal to zero, and, in that event, for determining whether the second memory contains a correction instruction at the memory location corresponding to said first plurality of address bits in said received address; and means for supplying an output instruction in response to each received address, the output instruction being a correction instruction read from the second memory in the event that all of said second plurality of address bits in a received address are equal to zero and it is determined that the second memory contains a correction instruction at the memory location corresponding to said first plurality of address bits in said received address, and the output instruction otherwise being read from the first memory.