Patent ID: 6934196
Filing Date: 2005-08-23
Classification: G06F,G11C

Abstract:
1. A memory module comprising: a memory array including memory cells comprising M columns×N rows; M column lines, each column line being connected with each memory cell configured to each column direction; N row lines, each row line connected with said each memory cell configured to each column direction; a power source line; m column input/output lines to input and output data in a column direction, where m is greater than or equal to 1 and less than M; n row input/output lines to input and output data in a row direction, where n is greater than or equal to 1 and less than N; a column address decoder, for receiving a column address and a column access direction signal, the column address decoder being configured to decode the column address and to selectively connect either between a column line specified by the column address and the power source line or between m column lines specified by the column address and m column input/output lines, according to the column access direction signal; and, a row address decoder, for receiving a row address and a row access direction signal, the row address decoder being configured to decode the row address and to selectively connect either between n row lines specified by the row address and n row input/output lines or between a row line specified by the row address and the power source line, according to the row access direction signal.