Patent ID: 6460110
Filing Date: 2002-10-01
Classification: G11C

Abstract:
A semiconductor memory, having a first address group cell array corresponding to a first address group and a second address group cell array corresponding to a second address group, said semiconductor memory comprising:a first address group redundant cell array, which can be substituted for a defective cell of said first address group cell array; a second address group redundant cell array, which can be substituted for a defective cell of said second address group cell array; a redundant memory, which stores a first address group redundant address and a second address group redundant address corresponding to a defective cell, together with first and second address group selection data corresponding thereto, said redundant memory being provided commonly for said first and second address group redundant cell arrays and providing a redundant address validation signal together, with said redundant address; a first address group redundant address comparator, provided commonly for the redundant memory, which compares a redundant address of said first address group supplied from said redundant memory with an address of a first address group being accessed when said redundant address validation signal being valid, and when they match, effectuates the selection of said first address group redundant cell array; and a second address group redundant address comparator, provided commonly for the redundant memory, which compares a redundant address of said second address group supplied from said redundant memory with an address of a second address group being accessed when said redundant address validation signal being valid, and when they match, effectuates the selection of said second address group redundant cell array.