Patent ID: 6815774
Filing Date: 2004-11-09
Classification: H01L,Y10S

Abstract:
A dielectrically separated wafer having a polysilicon layer and a plurality of monocrystalline silicon islands mutually separated by a dielectrically separating layer consisting of a silicon oxide film which is formed on a surface of a polysilicon layer, wherein:said polysilicon layer is formed by a seed low temperature CVD polysilicon layer grown by a low temperature CVD method on an interface with said dielectrically separating oxide film and a polysilicon layer formed by a high temperature CVD method; and when the surface is measured by a stylus-profilometer, a flatness of the dielectrically separated silicon wafer is less than 0.2 &mgr;m as the absolute roughness between a maximum height and a minimum height.