Patent ID: 7702977
Filing Date: 2010-04-20
Classification: G06F

Abstract:
1. A programmable logic device comprising: a first multiplexer; a first memory adapted to store an identification code of the programmable logic device; a second memory adapted to store an identification code of the programmable logic device; and a second multiplexer having a first input coupled to the first memory, a second input coupled to the second memory, and an output coupled to an input of the first multiplexer, the second multiplexer adapted to select between the identification code stored in the first memory and the identification code stored in the second memory and to provide the selected identification code to the first multiplexer, wherein the second memory is further adapted to store at least one of an identification code and a usercode and is further coupled directly to another input of the first multiplexer to provide a usercode to the first multiplexer.