Patent ID: 9170968
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. An apparatus comprising: a multi-channel data processor to process data of a plurality of channels, said multi-channel data processor is to switch from processing a first channel to processing a second channel of said plurality of channels by performing a context switch during a single clock cycle, the context switch including storing first state context corresponding to a processing state of said first channel and loading previously stored second state context corresponding to a processing state of said second channel; a random-access-memory (RAM) to store a plurality of state contexts corresponding to said plurality of channels; a register to load said second state context from said RAM, prior to said context switch, wherein, at said context switch, said multi-channel data processor is to load said second state context from said register and to store said first state context in said register, and, subsequent to said context switch, said register is to write the first state context to the RAM and to load from said RAM third state context of a third channel to be subsequently processed by said multi-channel data processor; a plurality of input queues to queue input data from said plurality of channels to be processed by said multi-channel data processor; a plurality of output queues to queue output data processed by said multi-channel data processor; and a delay controller to maintain a constant delay between adding an input data sample to an input queue and providing an output data sample corresponding to the input data sample from an output queue, said delay controller to consistently maintain said constant delay after each restart of said multi-channel data processor.