Patent ID: 6157751
Filing Date: 2000-12-05
Classification: G06K,G06T,H04N

Abstract:
A system for processing a group of image pixel data arranged in a grid of rows and columns comprising:a plurality of pairs of random access memories, each of the pairs having an odd random access memory and an even random access memory, each odd random access memory and each even random access memory having identical row address locations and identical column address locations, each of the pairs being constructed and arranged to store the group of image pixel data therein;an image processor that generates address values for accessing the group of image pixel data over a multi-bit address line and that manipulates the image pixel data, the image pixel data being transferred between the image processor and the random access memories over a data line;wherein the column address locations of each odd random access memory store a first set of alternating columns of image pixel data from the group of image pixel data, and the column address locations of each even random access memory store a second set of alternating columns from the group of image pixel data, the second set of alternating columns being located between the first set of alternating columns, whereby the first set and the second set together comprise all pixel data of the group of image pixel data; andwherein the image processor is constructed and arranged to generate address values that access pixel data from each of the first set and the second set in a single addressing cycle.