Patent ID: 7394415
Filing Date: 2008-07-01
Classification: H03M

Abstract:
1. A time-interleaved analog-to-digital converter comprising: an input terminal to input a to-be-measured signal; a signal generator which generates a calibration signal; a plurality of N analog-to-digital converters; a switch which selects one of the to-be-measured signal input from the input terminal and the calibration signal output from the signal generator; a signal divider which divides the signal selected by the switch into a plurality of N components, and causes the plurality of N analog-to-digital converters to input the divided signal components, respectively; a sampling control unit which assigns sampling clocks whose cycle is Ts and whose phase is shifted by Ts/N, respectively, to the plurality of N analog-to-digital converters; a correction information memory which stores correction information required to correct an error between signals output by the plurality of N analog-to-digital converters, the error occurring when a difference exists in at least one of a frequency characteristic of an amplitude and a frequency characteristic of a phase from input to the input terminal to a conversion processing in the plurality of N analog-to-digital converters; a correction processing unit which carries out a correction processing in accordance with the correction information stored in the correction information memory in response to signals output by the plurality of N analog-to-digital converters to receive the to-be-measured signal; and a correction information calculating unit which calculates an amplitude and a phase of the plurality of signal components by carrying out a spectrum analysis with respect to signals output by the plurality of N analog-to-digital converters to receive the calibration signal output from the signal generator, newly obtains the correction information based on a result of the calculation, and updates contents of the correction information memory in accordance with newly obtained correction information, wherein the signal generator is configured to generate the calibration signal to include a plurality of signal components positioned, respectively, at desired frequencies in a bandwidth in which N/2 times of a frequency Fs of the sampling clock assigned to each of the plurality of analog-to-digital converters is defined as an upper limit, the plurality of signal components appearing at frequencies different from each other in a bandwidth in which half of the frequency Fs of the sample clock is defined as an upper limit by sampling of each of the analog-to-digital converters.