Patent ID: 6762630
Filing Date: 2004-07-13
Classification: G11C,H03K

Abstract:
An integrated circuit, comprising:a synchronous circuit; an asynchronous circuit; an input register circuit connected to said synchronous circuit and said asynchronous circuit, said input register circuit having a terminal receiving a first control clock signal for controlling data transfer; an output register circuit connected to said synchronous circuit and said asynchronous circuit, said output register circuit having a terminal receiving a second control clock signal for controlling data transfer; and a sequence controller; said input register circuit storing data of said synchronous circuit for processing in said asynchronous circuit; said output register circuit storing data of said asynchronous circuit for further processing in said synchronous circuit; and said sequence controller connected to said asynchronous circuit for generating the first control clock signal and the second control clock signal in dependence on a duration required for the data to be processed in said asynchronous circuit.