Patent ID: 6820162
Filing Date: 2004-11-16
Classification: H04L

Abstract:
A queue control device comprising:a first storage area configured to store a first and a second queue, said first queue including first elements, each of said first elements having an address specifying a next element of the first elements, and said second queue including second elements, each of said second elements having an address specifying a next element of the second elements, wherein a head address of the second queue is stored in a tail element of the first elements, and a tail address of the first queue is stored in a tail element of the second elements; a second storage area configured to store first pointer information and second pointer information, said first pointer information being a head address specifying a head element of the first elements included in said first queue, and said second pointer information being a tail address specifying a tail element of the second elements included in said second queue; and a controller which is operatively connected to the first and second storage areas, controller sets a head address specifying a head element of the second elements included in said second queue in the tail element of the first elements included in said first queue stored in said first storage area and sets a tail address specifying a tail element of the first elements included in said first queue in a tail element of the second elements included in said second queue when the second queue connects to the first queue, wherein the controller controls said first and second queues according to said first pointer information and second pointer information stored in said second storage area.