Patent ID: 7990754
Filing Date: 2011-08-02
Classification: G11C,H01L

Abstract:
1. A resistance variable memory apparatus including: a memory array including plural first wires provided to extend in parallel with each other within a first plane, plural second wires provided to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first wires, and nonvolatile memory elements which are provided to respectively correspond to three-dimensional cross points between the plural first wires and the plural second wires and have resistance variable layers, a resistance value of each of the resistance variable layers being switchable reversibly in response to an electric signal applied between an associated first wire and an associated second wire, and current suppressing elements which are provided to respectively correspond to the three-dimensional cross points and are connected in series with the resistance variable layers, respectively; a first voltage source for applying a first voltage to the first wires or to the second wires; a second voltage source for applying a second voltage to the first wires or to the second wires; a third voltage source for applying a third voltage to the first wires or to the second wires; and a fourth voltage source for applying a fourth voltage to the first wires or to the second wires; wherein each of the resistance variable layers has a characteristic in which the resistance variable layer switches from a high-resistance state to a low-resistance state in response to a low-resistance state attaining voltage which is a predetermined voltage applied to both ends thereof, when the resistance variable layer is in the high-resistance state, while the resistance variable layer switches from the low-resistance state to the high-resistance state in response to a high-resistance state attaining voltage which is a predetermined voltage applied to both ends thereof, the high-resistance state attaining voltage having a polarity different from a polarity of the low-resistance state attaining voltage, when the resistance variable layer is in the low-resistance state; wherein each of the current suppressing elements has a non-linear and bidirectional current characteristic in which a resistance value thereof rapidly decreases when an absolute value of the voltage applied to both ends thereof exceeds a threshold VF and a current flows therein bidirectionally according to a polarity of the applied voltage; wherein when the first to fourth voltages are expressed as V a controller configured to execute operation A and operation B for a selected nonvolatile memory element which is a nonvolatile memory element to which data is to be written or from which data is to be read: A: the first voltage source is connected to a first wire associated with the selected nonvolatile memory element, the second voltage source is connected to a second wire associated with the selected nonvolatile memory element, the third voltage source is connected to a first wire which is not associated with the selected nonvolatile memory element, and the fourth voltage source is connected to a second wire which is not associated with the selected nonvolatile memory element; and B: the first voltage source is connected to a second wire associated with a selected nonvolatile memory element, the second voltage source is connected to a first wire associated with the selected nonvolatile memory element, the third voltage source is connected to a second wire which is not associated with the selected nonvolatile memory element, and the fourth voltage source is connected to a first wire which is not associated with the selected nonvolatile memory element.