Patent ID: 8977832
Filing Date: 2015-03-10
Classification: G06F,G11C

Abstract:
1. A semiconductor device comprising: a processing unit; a memory controller configured to communicate with at least two different types of memory devices, the memory controller including: a first interface configured to receive control output signals from the processing unit to access at least one of the memory devices, a conversion circuit configured to covert the control output signals to memory input signals in accordance with operation specifications of the memory devices, a second interface configured to connect to the memory devices via a common line, the common line being shared by the memory devices, and configured to output a write enable signal as one of the memory input signals to the common line, and a third interface configured to connect to one of the memory devices via a signal line, the signal line being different from the common line, and configured to output a chip enable signal as one of the memory input signals to the signal line; and a plurality of terminals configured to couple the semiconductor device with any one of the memory devices so that the semiconductor device and the any one of the memory devices are stacked through the plurality of terminals, the semiconductor device being configured to electrically connect to the any one of the memory devices through the plurality of terminals, wherein the conversion circuit is configured to output one of the memory input signals to the one of the memory devices according to one of the operation specifications of the one of the memory devices during a period from a time when the conversion circuit outputs another one of the memory input signals to another one of the memory devices to a time when the conversion circuit receives a memory output signal corresponding to the another one of the memory input signals from the another one of the memory devices.