Patent ID: 7491589
Filing Date: 2009-02-17
Classification: H01L,Y10S

Abstract:
1. A method for forming a semiconductor structure, the method comprising the steps of: (a) providing a semiconductor region directly on an underlying electrically isolating layer, the semiconductor region being covered on top by a mandrel and a spacer, (b) forming a back gate region separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layers, (c) removing a portion of the semiconductor region beneath the mandrel so as to form an active region adjacent to the removed portion of the semiconductor region; and (d) forming a main gate region in place of the removed portion of the semiconductor region and on the inter-gate isolating layer, the main gate region being separated from the active region by a main gate isolating layer and being separated from the back gate region by the inter-gate isolating layer,