Patent ID: 7895490
Filing Date: 2011-02-22
Classification: G01R,G06F

Abstract:
1. A method for testing an electronic circuit, comprising: selecting a plurality of test patterns arranged in an order, wherein each test pattern is associated with an associated circuit input state, and each test pattern causes an associated output of an electronic circuit; selecting a first log interval; storing a plurality of known outputs, wherein the plurality of known outputs comprises a known output associated with each test pattern as applied to the electronic circuit functioning in a known state; testing the electronic circuit in a first test by applying to the electronic circuit a first subset range of the plurality of test patterns sequentially in the order, from a first test pattern to the first log interval after the first test pattern, thereby generating a first associated output; comparing the first associated output with a first known output of the plurality of known outputs, wherein the first known output is associated with the same test pattern as the first associated output; in the event the first associated output matches the first known output, proceeding with additional test procedures; and in the event the first associated output does not match the first known output: