Patent ID: 6667222
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A method of forming an alignment mark and a shallow trench isolation region in the fabrication of an integrated circuit device comprising:providing an etch stop layer on a substrate; forming a photoresist mask overlying said etch stop layer having a first opening for a planned said alignment mark and having a second opening for a planned said shallow trench isolation region; etching away said etch stop layer within said first and second openings and etching into said substrate exposed within said first and second openings to a first depth to form a first trench underlying said first opening and a second trench underlying said second opening; thereafter covering said first trench with a solid cover placed on said photoresist mask, and etching said second trench into said substrate to a second depth greater than said first depth; and removing said solid cover and said photoresist mask and filling said second trench to complete formation of said shallow trench isolation region wherein said first trench completes formation of said alignment mark in the fabrication of said integrated circuit device.