Patent ID: 9075614
Filing Date: 2015-07-07
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a core area including a plurality of cores and coupled to a first voltage regulator, wherein the first voltage is to provide a first regulated voltage (VR) to the core area via a first supply pin of the core area coupled to a first load resistor; and an uncore area having a power management unit and coupled to a second voltage regulator, wherein the second voltage regulator is to provide a second VR to the uncore area independently of the first VR, via a second supply pin of the uncore area coupled to a second load resistor, wherein the power management unit is to detect an event based on which the core area is to enter a deep power saving state in which the first VR is to be substantially cut off and in response provide a first voltage value to the second voltage regulator, the second voltage regulator to decrease the second VR from a first reference voltage value to a second reference voltage value based on the first voltage value, the decrease to cause a reduction in a pin voltage value provided at the second supply pin of the uncore area, wherein the reduction in the pin voltage value is to decrease power consumption of the uncore area, wherein the pin voltage value is to be decreased to a level sufficient to maintain a minimum pin voltage value to operate the processor at a specified frequency value.