Patent ID: 6104643
Filing Date: 2000-08-15
Classification: G11C,H03K

Abstract:
A buffer circuit comprising:an input node for receiving a clock signal;a controllable inverter circuit coupled to the input node, the controllable inverter circuit provides an output signal in response to the clock signal when an enable signal is in a first state, and the controllable inverter circuit is disabled when the enable signal is in a second state;a one-shot latch circuit comprising,a latch circuit comprising a first input node coupled to an output node of the controllable inverter circuit, a second input node, and first and second output nodes,a delayed feedback circuit coupled between the first output node of the latch circuit and the second input node of the latch circuit;a first output circuit coupled to the first output node of the latch circuit; anda second output circuit coupled to the second output node of the latch circuit, the first and second output circuits have adjustable trip points to quickly detect both rising and falling output signals provided on the first and second output nodes of the latch circuit.