Patent ID: 6665206
Filing Date: 2003-12-16
Classification: G11C,H01L

Abstract:
A memory array, comprising:a plurality of ferroelectric floating-gate memory cells arranged in rows and columns; a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level; a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level; and a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level; wherein each program line is isolated from and orthogonal to each word line; wherein each bit line is isolated from and parallel to each program line; wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells; and wherein each program line is laterally offset from its associated bit line.