Patent ID: 6040730
Filing Date: 2000-03-21
Classification: G06G,G11C,H03H

Abstract:
An integrated capacitance multiplier circuit, comprising:an integrated circuit capacitor;first and second field-effect transistors, integrated on a common substrate with said capacitor; said first transistor having a width-to-length ratio which is more than ten times the width-to-length ratio of said second transistor;a biasing circuit connected to bias said first and second transistors, into an ohmic regime of operation, with first and second respective gate voltages which have different temperature dependences;an operational amplifier configured and operatively connected to follow the potential of a first terminal of said capacitor, and to drive a first source/drain terminal of said second transistor with a corresponding voltage;said second transistor having a second source/drain terminal which is connected to a capacitance node;said first transistor being connected in series between said capacitance node and said first terminal of said capacitor;whereby said capacitance node sees an effective capacitance which is much greater than the capacitance of said capacitor.