Patent ID: 7149991
Filing Date: 2006-12-12
Classification: G06F

Abstract:
1. A method of creating a wire load model for an integrated circuit, the method comprising: synthesizing a first netlist of components for the integrated circuit; generating a non-timing driven placement of the first netlist of components; generating a timing driven placement of the first netlist of components; identifying one of several wire load models; calculating first timing data based on the identified wire load model and the non-timing placement of the first netlist components; generating a first histogram from the first timing data; generating a parasitic estimation model from the timing driven placement of the first netlist of components; calculating second timing data based on the parasitic estimation model; generating a second histogram from the second timing data; synthesizing a second netlist of components for the integrated circuit; calculating a wire load model for the second netlist of components; calculating third timing data based on the wire load model for the second netlist of components; generating a third histogram from the third timing data comparing the first and second histograms; comparing the second and third histograms; and creating a calibrated wire load model in response to comparing the first and second histograms and in response to comparing the second and third histograms.