Patent ID: 8164550
Filing Date: 2012-04-24
Classification: G09G

Abstract:
1. A liquid crystal display device comprising: a substrate; a plurality of pixels each including a pixel electrode provided on the substrate; each pixel including a counter electrode disposed opposite to each of the pixel electrodes to receive a first series of periodically oscillating clock pulses; each pixel including a memory element electrically connected to the pixel electrode; each pixel including a first switching element electrically connected to the memory element; an image signal line to supply an image signal to the first switching element; a scan signal line to supply a scan signal that controls the first switching element; a capacitive element provided in the memory element; the memory element including an output circuit comprising a first nMOS switching element and a first pMOS switching element, the first nMOS switching element and the first pMOS switching element having a common control terminal to which a voltage held in the capacitive element is supplied and a common output terminal connected to the pixel electrode, wherein a first input electrode of the first pMOS switching element is supplied with the first series of periodically oscillating clock pulses and a first input electrode of the first nMOS switching element is supplied with a second series of periodically oscillating clock pulses, the first series of periodically oscillating clock pulses and the second series of periodically oscillating clock pulses having opposite phase; the memory element further including a second nMOS switching element and a third nMOS switching element electrically connected between the output circuit and the capacitive element, the second nMOS switching element and the third nMOS switching element being connected in series between the first switching element and the pixel electrode; a display-voltage supply line to supply a display voltage corresponding to the second series of periodically oscillating clock pulses to the input electrode of the first nMOS switching element of the output circuit; and a non-display voltage line to supply a non-display voltage corresponding to the first series of periodically oscillating clock pulses to the input electrode of the first pMOS switching element of the output circuit, wherein: the first switching element is turned on to supply the image signal to the memory element so that the voltage held in the capacitive element indicates one of a display state and a non-display state, wherein the display state is a state in which a potential difference between the counter electrode and the pixel electrode is maximum and the non-display state is a state in which the potential difference between the counter electrode and the pixel electrode is minimum, the first switching element is turned off to supply the voltage held in the capacitive element to the control terminal of the output circuit, when the image signal indicates a display state, the output circuit outputs the display voltage corresponding to the second series of periodically oscillating clock pulses to the pixel electrode, when the image signal indicates a non-display state, the output circuit outputs the non-display voltage corresponding to the first series of periodically oscillating clock pulses to the pixel electrode, when the image signal indicates the display state, the capacitive element holds a voltage that causes the output circuit to output the display voltage, when the image signal indicates the non-display state, the capacitive element holds a voltage that causes the output circuit to output the non-display voltage, and a control electrode of the second nMOS switching element is electrically connected to a first terminal of a first capacitor of the capacitive element and a first control signal line that supplies a first control clock pulse, and a control electrode of the third nMOS switching element is electrically connected to a first terminal of a second capacitor of the capacitive element and a second control signal line that supplies a second control clock pulse having opposite phase of the first control clock pulse, wherein a second terminal of the first capacitor and second terminal of the second capacitor are commonly connected between the second nMOS switching element and the third nMOS switching element, and an output electrode of the third nMOS switching transistor is commonly connected to the pixel electrode and the common output terminal of the output circuit.