Patent ID: 6347062
Filing Date: 2002-02-12
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate; a first word line and a second word line; a first positive-phase bit line and a second positive-phase bit line; a first negative-phase bit line and a second negative-phase bit line; a first CMOS inverter having a first N-channel MOS transistor, a first P-channel MOS transistor, and input and output terminals; a second CMOS inverter having a second N-channel MOS transistor, a second P-channel MOS transistor, and input and output terminals, wherein said input terminal of said second CMOS inverter is connected to said output terminal of said first CMOS inverter as a first memory node, and said output terminal of said second CMOS inverter is connected to said input terminal of said first CMOS inverter as a second memory node; a third N-channel MOS transistor having a gate that is connected to said first word line, having a drain that is connected to said first positive-phase bit line, and having a source that is connected to said first memory node; a fourth N-channel MOS transistor having a gate that is connected to said first word line, having a drain that is connected to said first negative-phase bit line, and having a source that is connected to said second memory node; a fifth N-channel MOS transistor having a gate that is connected to said second word line, having a drain that is connected to said second positive-phase bit line, and having a source that is connected to said first memory node; and a sixth N-channel MOS transistor having a gate that is connected to said second word line, having a drain that is connected to said second negative-phase bit line, and having a source that is connected to said second memory node, wherein said first and second P-channel MOS transistors are located in an N-well area of said semiconductor substrate, said first, third, and fifth N-channel MOS transistors are located in a first P-well area of said semiconductor substrate, and said second, fourth, and sixth N-channel MOS transistors are located in a second P-well area of said semiconductor substrate.