Patent ID: 8780621
Filing Date: 2014-07-15
Classification: G11C,Y10S

Abstract:
1. A semiconductor integrated circuit system, comprising: a memory cell array including a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a phase-change memory cell formed on each of intersections of the plurality of word lines and the plurality of bit lines; a reset current unit configured to apply a reset current to a bit line of the bit lines to control one selected from among the phase-change memory cells to have a amorphous state; a set current unit configured to apply a set current to a bit line of the bit lines to control one selected from the phase-change memory cells to have a crystalline state; and a phase-change compensation unit configured to apply a correction current to a memory cell adjacent to each of the selected phase-change memory cells through a word line of the adjacent memory cell to compensate for a phase-change of the adjacent memory cell.