Patent ID: 6289067
Filing Date: 2001-09-11
Classification: H04B,H04J,H04L

Abstract:
An integrated circuit device for generating a plurality of internal clock signals and synchronizing data signals with one of the generated clock signals, comprising:a FIFO having a data bus output, a data bus input for coupling to an output providing the data signals, an external clock input for coupling to an output providing a first external clock signal for clocking the data signals into the FIFO at a frequency of chiprate(S), and an output clock input coupled to an output providing a FIFO output clock signal for clocking the data signals out of the FIFO at a frequency of chiprate(S), the external clock signal being asynchronous with the FIFO output clock signal;a clock generator, comprising:a PLL having an output, and an input for coupling to an output providing a second external clock signal, the PLL multiplying the frequency of the second external clock signal by p to produce a primary digital transceiver clock signal at the output of the PLL having a frequency of chiprate(S)(n), wherein chiprate, S, and n are numerical values;a first clock divider having an input and an output, the input of the first clock divider being coupled to the output of the PLL, the output of the first clock divider being coupled to the output clock input of the FIFO, the first clock divider producing the FIFO output clock signal at the output of the first clock divider;a pulse swallower having an output, and an input for coupling to an output providing a reference frequency signal from a reference frequency source, the pulse swallower producing a secondary master clock signal at the output of the pulse swallower having a frequency of chiprate(z), wherein z is a numerical value; anda first multiplexer having a first input, a second input, a control input, and an output, the first input of the multiplexer being coupled to the output of the pulse swallower, the second input of the multiplexer being coupled to the output of the PLL; anda controller having a control output coupled to the control input of the first multiplexer, the controller producing a control signal at the control output for selectively providing either the primary digital transceiver clock signal from the output of the PLL or the secondary master clock signal from the output of the pulse swallower at the output of the first multiplexer.