Patent ID: 7335986
Filing Date: 2008-02-26
Classification: H01L

Abstract:
1. A wafer level chip scale package comprising: a semiconductor die comprising a first surface comprising at least one bond pad formed thereon and a first coating layer formed on the outer peripheral edge of the bond pad, a second surface opposing the first surface, and a third surface positioned along the periphery of the first and second surfaces; a first redistribution layer along a surface of the first coating layer and being connected to the bond pad; a first electronic device positioned on the surface of the first coating layer and connected to the first redistribution layer by a first connection member; a first conductive post formed on the first redistribution layer; and a second coating layer formed on the surface of the first coating layer, the first redistribution layer, the first electronic device, the first connection member, and the first conductive post in such a manner that a surface of the first conductive post is exposed to the exterior.