Patent ID: 6029220
Filing Date: 2000-02-22
Classification: G06F

Abstract:
A method of performing a pipeline operation for a processing circuit device synchronously with a clock cycle, the pipeline operation respectively including pipeline stages for a functional process and a transmission process, said method comprising the steps of:ascertaining said processing circuit device to separate said processing circuit device into functional process portions and transmission process portions; andassigning different pipeline stages to each of said separated functional process portions and to each of said separated transmission process portions, respectively,wherein each of said pipeline stages assigned to said transmission process portions includes a transmission line divided into N equal portions, each divided portion having a predetermined transmission time of one clock cycle or less and being sandwiched by two pipeline latches, wherein further N is given by N.gtoreq.tx/{T-(tk+tl+ts)}, where T is a pipeline cycle time, tk is a clock skew, tl is a delay time of pipeline latch, ts is a setup time of pipeline latch, and tx is a total wiring delay time of said signal transmission line.