Patent ID: 8319535
Filing Date: 2012-11-27
Classification: G11C,H03L

Abstract:
1. A delay locked loop (DLL) circuit, comprising: a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code; a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks; a feedback delay configured to delay the delay locked clock and output a feedback clock; and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.