Patent ID: 6849552
Filing Date: 2005-02-01
Classification: H01L

Abstract:
1. A method for fabricating a vertical type transistor in a semiconductor integrated circuit device, the method comprising the steps of: forming an isolation oxide layer formed on a field region in a silicon substrate to expose an active region of the silicon substrate; forming an epitaxial silicon layer on the active region of the silicon substrate; performing an ion implantation to form the source region in the vicinity of the surface of the silicon substrate and the drain region on the epitaxial silicon layer; forming a masking insulator spacer at the side wall of a stair part, the stair part that has a height difference being made by removing the drain region to a desired depth; removing the epitaxial silicon layer exposed through the masking insulator spacer so that the source region can be exposed; forming a gate insulating layer along with the exposed surfaces of the epitaxial silicon layer, the source region, and the drain region after the removal of the masking insulator spacer; forming a gate electrode to contact with the gate insulating layer vertically arranged between the source region and the drain region; forming a planarization insulating layer over whole structure of the produced elements; forming contact holes on the planarization insulating layer to expose the source region, the drain region, and the gate electrode respectively; forming contact plugs in the contact holes so that they are electrically connected with the source region, the drain region, and the gate electrode.