Patent ID: 6768344
Filing Date: 2004-07-27
Classification: H03K

Abstract:
A cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier comprising:a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier, said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal; a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier, said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal; a first clock signal coupled to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; a second clock signal coupled to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal, wherein; said at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal is coupled to said at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal, further wherein; said second clock signal is delayed with respect to said first clock signal, by a predetermined delay time.