Patent ID: 6723604
Filing Date: 2004-04-20
Classification: G11C,H01L

Abstract:
A method of forming an array of floating gate memory cells on a substrate from a plurality of parallel elongated strips of gate material positioned along rows of cells, comprising:separating the strips into segments of a given length with a first set of spaces therebetween, implanting ions into regions of the substrate through said first set of spaces in a manner that said regions are isolated from each other along and between the rows, forming conductive lines in the first set of spaces that individually electrically contact a plurality of said substrate regions in a plurality of rows, separating the strip segments into sub-segments having a second set of spaces therebetween, and forming control gates along the rows over said sub-segments and conductive lines, and which extend into the second set of spaces adjacent to edges of said sub-segments with tunnel dielectric therebetween.