Patent ID: 6222234
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A semiconductor device provided with a partially-depleted SOI MOSFET and a fully-depleted SOI MOSFET on the same substrate; comprising:a silicon substrate;a buried oxide film covering said silicon substrate;an SOI layer formed on said buried oxide film and having a film thickness that is thinner in the fully-depleted SOI MOSFET than in the partially-depleted SOI MOSFET; anda gate oxide film formed on said SOI layer and having a film thickness that is thinner in said fully-depleted SOI MOSFET than in said partially-depleted SOI MOSFET;wherein a channel region impurity concentration is lower in said fully-depleted SOI MOSFET than in said partially-depleted SOI MOSFET.