Patent ID: 8482498
Filing Date: 2013-07-09
Classification: G09G

Abstract:
1. A liquid crystal display panel, comprising: a display region; a periphery circuit region being situated at a periphery of the display region; a joint obligate region being situated in the periphery circuit region; a plurality of first test thin-film transistors being disposed on the joint obligate region according to a regular distance, wherein each of the first test thin-film transistors has a transistor width, the adjacent two first test thin-film transistors have a pitch which has a width being equal to a sum of the transistor width and the regular distance; a plurality of second test thin-film transistors being disposed on the joint obligate region according to the regular distance, wherein each of the second test thin-film transistors has the transistor width, and the adjacent two second test thin-film transistors have the pitch; a plurality of first lines, each having a first terminal and a second terminal, the first terminal being electrically connected to one of the corresponding first test thin-film transistors individually, and the second terminal being electrically connected to the display region individually; a plurality of second lines, each having a first terminal and a second terminal, the first terminal being electrically connected to one of the corresponding second test thin-film transistors individually, and the second terminal being electrically connected to the display region individually; a blank region having a width, wherein the blank region is formed between the first and the second test thin-film transistors; a plurality of first adjustment thin-film transistors, being disposed on the blank region and disconnected with the display region; and a plurality of first adjustment lines, each having a first terminal, the first terminal being electrically connected to one of the corresponding first adjustment thin-film transistors individually, wherein the first adjustment lines have second terminals, the second terminals are connected to each other to form a closed connection terminal, and the closed connection terminal is outside the display region and in the periphery circuit region, such that the first adjustment lines do not enter the display region; wherein the width of the blank region is not smaller than a sum of the twice regular distance and the transistor width.