Patent ID: 6826074
Filing Date: 2004-11-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells each drawing cell current according to data stored therein when selected; a plurality of word lines and a plurality of bit lines selected for accessing data in a specific memory cell among the plurality of memory cells; a power supply for providing a voltage corresponding to a high-level side potential of data in the plurality of memory cells; a word line potential supply source for supplying a potential to the plurality of word lines; and a precharge potential supply source for supplying a precharge potential to the plurality of bit lines, wherein a precharge potential supplied to non-selected bit lines among the plurality of bit lines by the precharge potential supply source is set at a value lower than the voltage of the power supply, a potential supplied to non-selected word lines among the plurality of word lines by the word line potential supply source is set at a predetermined negative value, and a total of the absolute value of the precharge potential of the non-selected bit lines supplied by the precharge potential supply source and the absolute value of the potential of the non-selected word lines supplied by the word line potential supply source is a value less than the voltage of the power supply.