Patent ID: 8601236
Filing Date: 2013-12-03
Classification: G06F

Abstract:
1. A processor chip, comprising: a plurality of processor cores including a first processor core and a second processor core and a plurality of register spaces including a first register space connected to the first core and a second register space connected to the second core, wherein the register space of each respective one of the plurality of cores, when the respective core is in a first vector mode, is configured as a first plurality of registers used as a plurality of sets of vector registers that each includes a plurality of vector registers and a second plurality of registers used as a plurality of sets of address registers that each includes a plurality of address registers, and wherein, when the respective core is in a second vector mode, the register space of the respective core is reconfigured such that at least some of its registers that were used as address registers in the first vector mode are instead used as vector registers in the second vector mode, wherein each one of the plurality of processor cores operates on a plurality of instruction streams, wherein each instruction stream in each respective core operates using one of the plurality of sets of address registers for that respective core and one of the plurality of sets of vector registers for that respective core, wherein each respective processor core has a selectable maximum vector length specifying a maximum number of elements in each vector register in that core, wherein the selectable vector length is one or more elements, and wherein each one of the plurality of processor cores is operable to change between the first vector mode having a first maximum vector length and the second vector mode having a second maximum vector length, and wherein the second maximum vector length is longer than the first maximum vector length.