Patent ID: 8384186
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. Power semiconductor device with an active region comprising: a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side; a second layer of a second conductivity type, which is arranged in a central region on the first main side, wherein the second layer corresponds to an active region; a junction termination region arranged in a circumferential region on the first main side and surrounding the second layer, the junction termination region comprising at least one sub-region of the second conductivity type implemented into a sub-region of the first conductivity type, wherein subsequent spacer sub-regions laterally enclose each other; a third electrically conductive layer, which is arranged on the second layer on a side opposite the first layer; a fourth electrically conductive layer, which is arranged on the second main side; a spacer region arranged in an intermediate region on the first main side between the second layer and the junction termination region and surrounding the second layer, the spacer region comprising a spacer sub-region of the second conductivity type implemented into a sub-region of the first conductivity type, wherein the spacer sub-region of the second conductivity type laterally encloses the sub-region of the first conductivity type, such that the spacer sub-region is electrically disconnected from the second layer; and a lifetime control region comprising defects reducing a carrier lifetime within adjacent semiconductor material, the lifetime control region extending at least throughout the second layer and throughout a portion of the spacer sub-region and not extending into the junction termination region.