Patent ID: 6037814
Filing Date: 2000-03-14
Classification: G09G,H03L

Abstract:
A PLL circuit comprising:frequency detecting means for detecting a variable range of an oscillation frequency of a VCO voltage controlled oscillator (""VCO""),a dividing circuit for dividing the oscillation frequency of said VCO,memory means for storing frequency data of said VCO preliminarily detected by said frequency detecting means, andcontrol means for setting the dividing ratio of said dividing circuit so as to operate said VCO at a frequency near the center of a variable range of oscillation frequency of said VCO on the basis of the frequency data stored in said memory means, wherein the control means is a CPU, the dividing circuit is controlled by the dividing ratio set by said CPU, the frequency detecting means uses a reference signal for test, the frequency of an output signal of the dividing circuit is detected while sequentially changing the dividing ratio of the dividing circuit by said CPU, the CPU judges a locked state of the PLL circuit at the dividing ratio on the basis of the detection, said CPU calculates a range of the dividing ratio that is lockable by the PLL circuit with respect to the reference signal, and the memory means stores the result of calculation.