Patent ID: 6166987
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a nonvolatile memory cell;a word line connected to said nonvolatile memory cell;a decoder to which an address signal is input;a word line driver having a first node, a second node and an output node, a first P-channel transistor and a first N-channel transistor, said first P-channel transistor having a gate terminal and a first current path, a first end of said first current path of said first P-channel transistor being connected to said first node, a second end of said first current path being connected to said output node, said output node supplying a predetermined potential to said word line, and a first power supply potential being supplied to said first node;a second N-channel transistor having a gate terminal and a second current path, a second power supply potential being supplied to said gate terminal of said N-channel transistor, a first end of said second current path of said second N-channel transistor being connected to said decoder, and a second end of said second current path of said second N-channel transistor being connected to said gate terminal of said first P-channel transistor; anda second P-channel transistor having a gate terminal and a third current path, a predetermined signal being applied to said gate terminal of said second P-channel transistor, said first power supply potential being supplied to a first end of said third current path of said second P-channel transistor, and a second end of said third current path of said second P-channel transistor being connected to said gate terminal of said first P-channel transistor,wherein a negative potential is applied to said second node of said word line driver, said first power supply potential includes at least two kinds of potential, and a maximum potential of said first power supply potential is greater than said second power supply potential.