Patent ID: 6548403
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming a silicon gate electrode, having opposing side surfaces, on an upper surface of a semiconductor substrate with a gate insulating layer therebetween; depositing a silicon oxide liner by plasma enhanced chemical vapor deposition, at a thickness of about 200 Ã¥ to about 600 Ã¥, on the opposing side surfaces of the gate electrode and on the upper surface of the semiconductor substrate adjacent the opposing side surfaces of the gate electrode; forming silicon nitride sidewall spacers on the opposing side surfaces of the gate electrode with the silicon oxide liner therebetween; depositing a layer of nickel on the gate electrode and on exposed surfaces of the substrate; and heating to react the layer of nickel with underlying silicon to form a layer of nickel silicide on the gate electrode and layers of nickel silicide on the exposed surfaces of the substrate, wherein: a layer of nickel silicide is formed on the silicon nitride sidewall spacers during heating; and the silicon oxide liner prevents the nickel silicide layer on the sidewall spacers from contacting the nickel layer on the gate electrode and/or contacting the nickel silicide layers on the substrate surface.