Patent ID: 6262446
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A method of forming a conductive interconnection for an integrated circuit device comprising:forming a plurality of conductive plugs in a first insulating layer on a semiconductor substrate, the semiconductor substrate including a cell array region and a peripheral region;forming a first conductive layer, a capacitor dielectric film and a second conductive layer on the first insulating layer including the conductive plugs;patterning the second conductive layer, the capacitor dielectric film and the first conductive layer to define a plurality of capacitors and a plurality of first conductive patterns, the capacitors comprising a portion of the first conductive layer, a portion of the capacitor dielectric film and a portion of the second conductive layer thereon, the first conductive patterns that are free of the capacitor dielectric film and the second conductive layer thereon, such that at least one capacitor at the cell array region is electrically connected to at least one of the conductive plugs, at least one capacitor at the peripheral region is not electrically connected to the conductive plugs, and at least one of the first conductive pattern is electrically connected to at least one of the conductive plugs;forming a second insulating layer on the first insulating layer including the capacitors and the first conductive patterns;forming at least one first level interconnection on the second insulating layer to electrically connect the first conductive patterns and to electrically interconnect selected ones of the first conductive patterns to one another;forming a third insulating layer on the second insulating layer including the first level interconnection; andforming a second level interconnection on the third insulating layer to electrically connect at least one capacitor at the peripheral region to at least one of the first level interconnection.