Patent ID: 7282767
Filing Date: 2007-10-16
Classification: H01L

Abstract:
1. A semiconductor circuit for protecting an input/output (I/O) pad against ESD events, said I/O pad located between a power pad and a ground potential pad, comprising: a pMOS transistor in a first n-well having its source connected to said power pad and said first n-well, and its drain connected to said I/O pad, said transistor having a finger-shaped contact to said first n-well, said first well contact touching said transistor source; and a first finger-shaped diode having its cathode located in a second n-well and connected to said I/O pad, and its anode connected to ground, said anode positioned between said cathode and said first n-well, said finger-shaped anode and cathode oriented approximately perpendicular to said finger-shaped transistor n-well contact.