Patent ID: 6720606
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate; a plurality of trench capacitors formed in said semiconductor substrate and arranged at a regular pitch; a semiconductor layer formed on said semiconductor substrate in which said trench capacitors are formed; an element isolation insulating film buried in said semiconductor layer to define a plurality of active element areas each spreading over two adjacent trench capacitors; a plurality of transistors formed two by two in each of said plurality of active element areas, such that two transistors share one of source/drain diffusion layers, and the other of said source/drain diffusion layers is positioned over trenches of two adjacent trench capacitors, said transistors each having a gate connected to a word line continuous in one direction, each of said trenches of two adjacent trench capacitors is located under the gate of a corresponding transistor; a first contact layer for connecting the other of said source/drain diffusion layers of each of said transistors to a capacitor node layer of corresponding one of said trench capacitors; a bit line provided to intersect said word lines; and a second contact layer for connecting one of said source/drain diffusion layers to said bit line.