Patent ID: 6228680
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method for the fabrication of a semiconductor assembly comprising:providing a semiconductor circuit chip having an integrated circuit;said chip also having at least one layer of insulating material of low dielectric constant, wherein said at least one insulating layer is located in regions of different mechanical stress levels;providing said chip with a first plurality of metal contact pads;providing an electrically insulating substrate;said substrate having a second plurality of metal contact pads; attaching one solder ball to each contact pad of the first plurality and aligning the assembled balls to the respective contact pads of said second plurality; supplying thermal energy to said semiconductor chip and said substrate, whereby the solder is reflowed to form solder joints and said chip is mounted to said substrate spaced apart by a gap, forming an assembly;cooling said assembly from the reflow temperature to a temperature between 90 .degree. and 130 .degree. C. and maintaining said temperature at a substantially constant level, whereby said mechanical stress levels in said at least one dielectric layer and in said solder joints are kept at low values safe for operating said semiconductor assembly;filling said gap with a polymeric precursor at said temperature between 90.degree. C. and 130.degree. C,; supplying additional thermal energy for curing said polymeric precursor, whereby a polymeric encapsulant is formed; and cooling the completed assembly to room temperature at specific rates, whereby said mechanical stress levels remain at low values safe for operating said semiconductor assembly.