Patent ID: 6799280
Filing Date: 2004-09-28
Classification: H04L

Abstract:
An interface circuit for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, the interface circuit comprising:a flip-flop having a data input for receiving a first data signal from a first clock domain, a clock input for receiving a first clock signal, and an output; a latch having a data input coupled to said flip-flop output and a clock input for receiving a gating signal, and an output; a multiplexer having a first data input coupled to said flip-flop output, a second data input coupled to said latch output, and a selector input for selecting one of said first data input or said second data input for transfer to an output of said multiplexer, wherein said first data input of said multiplexer is selected in response to a rising edge of said first clock signal being approximately in phase with a rising edge of said second clock signal; and wherein said second clock signal and said first clock signal are derived from a common core clock.