Patent ID: 8614496
Filing Date: 2013-12-24
Classification: G06F

Abstract:
1. A method to scale down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices, comprising: providing a circuit layout comprising a set of conductive lines comprising a first conductive line and a second conductive line which respectively pass through a first region and a second region, wherein said first conductive line and said second conductive line selectively have a first region original line width, a first region original space and a first region original pitch in said first region and selectively have a second region original line width, a second region original space and a second region original pitch in said second region; performing a sizing-down operation so that said first conductive line and said second conductive line are respectively in accordance with a first region rule and with a second region rule to selectively have a first region scaled-down line width, a first region scaled-down space and a first region scaled-down pitch in said first region, and selectively have said second region original line width, a second region scaled-down space which is smaller than said second region original space and a second region scaled-down pitch which is smaller than said second region original pitch in said second region, wherein said first region scaled-down line width and said second region original line width are substantially different, and said first region scaled-down pitch is smaller than said first region original pitch; and wherein said set of conductive lines have said second region original line width of a pre-determined length in said first region adjacent to said second region and having a turn in said first region; wherein said first region line width is smaller than said second region line width in said first region adjacent to said second region.