Patent ID: 6104724
Filing Date: 2000-08-15
Classification: H04L

Abstract:
An asynchronous data transfer and source traffic control system, comprising:a) a bidirectional data bus;b) a first clock bus having a first clock signal of a first frequency;c) a bus master bidirectionally coupled to said bidirectional data bus, said bus master also being coupled to said first clock bus;d) a plurality of bus users bidirectionally coupled to said bidirectional data bus, each of said bus users also being coupled to said first clock bus and receiving said first clock signal, whereinsaid plurality of bus users are individually granted write access to said bidirectional data bus by said bus master in response to requests made by said plurality of bus users, said requests by said plurality of bus users being made during a request field of a repeating bus frame format and said write access being granted to an individual bus user by said bus master during a grant field of said repeating bus frame format,said repeating bus frame format comprising a predetermined number of cycles of said first clock signal, said predetermined number of cycles defining said request field, a data field, and said grant field,one of said requests made in said request field of a first frame being granted in said grant field of said first frame for write access during said data field of a second frame.