Patent ID: 7374989
Filing Date: 2008-05-20
Classification: H01L

Abstract:
1. A method for fabricating a flash memory comprising: forming a first source in a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; selectively etching the epitaxial layer to form an opening at least partially exposing the first source; sequentially forming a tunneling oxide layer, floating gates and a dielectric layer inside the opening; forming a gate dielectric layer on the epitaxial layer; simultaneously forming a control gate and select gates on the gate dielectric layer, the select gates being positioned at at least one distance from the opening; forming a first drain within the epitaxial layer between the control gate and at least one of the select gates; implanting impurities while using the control gate and the select gates as a mask to form a second source and a second drain within the epitaxial layer.