Patent ID: 8630330
Filing Date: 2014-01-14
Classification: H04J,H04L,H04W

Abstract:
1. An integrated circuit for controlling a process comprising: multiplying an ACK or NACK symbol with an orthogonal sequence, which is one of plural orthogonal sequences, and with a sequence defined by a cyclic shift value, which is one of plural cyclic shift values and which is associated with the orthogonal sequence; and scrambling the ACK or NACK symbol by 1 or e wherein the ACK or NACK symbol is scrambled by 1 when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of two cyclic shift values that are associated with one of the plural orthogonal sequences and that are next to each other at a set interval, and is scrambled by e