Patent ID: 6727156
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device including a ferroelectric capacitor, comprising:forming a conductive plug within a first insulating layer on a semiconductor substrate to be electrically connected to the semiconductor substrate; forming a first lower metal layer which is electrically connected to the conductive plug and prevents diffusion of oxygen into the conductive plug on the first insulating layer; forming a lower metal oxide layer on the first lower metal layer; forming a second lower metal layer, for inducing interface lattice matching, on top of the lower metal oxide layer, thereby forming a lower electrode layer comprised of the first lower metal layer, the lower metal oxide layer, and the second lower metal layer, forming a ferroelectric layer from a ferroelectric material on the lower electrode layer at a crystallizing temperature of approximately 700Â° C.; forming a first upper metal layer, for inducing interface lattice matching, on top of the ferroelectric layer; inducing interface lattice matching at the interfaces between the first upper metal layer and the ferroelectric layer, and between the second lower metal layer and the ferroelectric layer by performing a heat treatment at a temperature higher than the crystallizing temperature after forming the first upper metal layer; forming an upper metal oxide layer on top of the first upper metal layer; and forming a second upper metal layer, for preventing diffusion of a material, on top of the upper metal oxide layer, thereby forming an upper electrode layer comprised of the first upper metal layer, the upper metal oxide layer, and the second upper metal layer.