Patent ID: 7423903
Filing Date: 2008-09-09
Classification: H01L

Abstract:
1. An operation method of a single-gate non-volatile memory, wherein said single-gate non-volatile memory comprises: a P-type semiconductor substrate; a transistor, disposed in said P-type semiconductor substrate, and having a first electrically-conductive gate and a plurality of first ion-doped regions, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain; and a capacitor structure, disposed in said P-type semiconductor substrate, and having a second electrically-conductive gate and a second ion-doped region; wherein said first electrically-conductive gate and said second electrically-conductive gate being electrically interconnected to form a single floating gate; wherein said operation method is characterized in: a substrate voltage V in writing said memory: V V V in erasing said memory: V V