Patent ID: 6072219
Filing Date: 2000-06-06
Classification: H01L

Abstract:
An electrostatic discharge (ESD) protection circuit incorporated between an input pad and an internal circuit of an integrated circuit formed on a substrate, said ESD protection circuit comprising:an input stage connected between the input pad and the internal circuit of the integrated circuit;an NMOS transistor having a drain connected to the input pad, a gate connected to the ground, and a source connected to a common node;a resistor connected between the common node and the ground; andan field oxide device (FOD) having a parasitic lateral bipolar junction transistor (LBJT) formed therein, and said FOD having a drain connected to the input pad and a source connected to the ground;wherein the substrate of said FOD and the source and substrate of said NMOS transistor are connected together to the common node;wherein said parasitic LBJT has a collector formed from the drain of said FOD and an emitter formed from the source of said FOD, and a base formed from the substrate of said FOD; andwherein a breakdown voltage of sad NMOS transistor is lower than a breakdown voltage of said FOD.