Patent ID: 6745353
Filing Date: 2004-06-01
Classification: G06F

Abstract:
An apparatus for link physical error tracking comprising:a first shift register, the first shift register receiving a first status bit for each low byte symbol data of an input data stream denoting whether the low byte symbol data has a link physical error; a second shift register, the second shift register receiving a second status bit for each high byte symbol data of the input data stream denoting whether the high byte symbol data has a link physical error; a first counter, the first counter incrementing a first error count when receiving at least one of the first status bit and the second status bit that denote an error and decrementing the first error count when receiving at least one of the first status bit from the output of the first shift register and the second status bit from an output of the second shift register that denote an error; and a second counter, the second counter incrementing a second error count when receiving at least one of the first status bit and the second status bit that denote an error and decrementing the second error count when receiving at least one of the first status bit from the output of the first shift register and the second status bit from a second output of the second shift register that denote an error; and a comparator, the comparator comparing the first error count and the second error count with a maximum value, a retrain signal being generated if the first error count or the second error count become larger than or equal to the maximum value.