Patent ID: 9093522
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A vertical transistor comprising a semiconductor substrate having a first electrode on its bottom surface; a first layer of a first conductivity type above the substrate, the first layer having a first dopant concentration; a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface; a trench exposing a vertical sidewall of the second layer; a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface; a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate; a conductive gate overlying the channel for creating a lateral conductive path between the first region and the second layer when the gate is biased above a threshold voltage; a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall, the vertical field plate being an extension of the gate, the vertical field plate surrounding the second layer; and a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a substantially vertical current flows between the channel and the substrate.