Patent ID: 8296547
Filing Date: 2012-10-23
Classification: G06F

Abstract:
1. A computer-implemented method for loading entries into a translation lookaside buffer (TLB) residing in hardware via indirect TLB entries, comprising the steps of: checking the TLB for a direct TLB entry associated with a given virtual address, wherein each direct TLB entry contained in the TLB provides a real address associated with a virtual address; if no direct TLB entry associated with the given virtual address is found in the TLB, checking the TLB for an indirect TLB entry associated with the given virtual address, wherein each indirect TLB entry contained in the TLB provides the real address of a page table associated with a specified range of virtual addresses, each page table being comprised of an array of page table entries; if an indirect TLB entry associated with the given virtual address is found in the TLB, generating a computed address by combining a real address field from the indirect TLB entry and bits from the given virtual address, obtaining a page table entry (PTE) by reading a word from a memory at the computed address, and loading the PTE into the TLB as a direct TLB entry; if no indirect TLB entry associated with the given virtual address is found in the TLB, utilizing a hardware mechanism for loading an indirect TLB entry covering the given virtual address into the TLB from a hash table residing in memory, wherein the step of utilizing a hardware mechanism for loading the indirect TLB entry covering the given virtual address into the TLB from the hash table residing in memory comprises the steps of: