Patent ID: 8473695
Filing Date: 2013-06-25
Classification: G06F

Abstract:
1. A memory subsystem, comprising: memory device including one or more memory arrays for storing data; and a control unit coupled to the memory device and configured to read and write the data to the one or more memory arrays in response to receiving memory transactions via a memory interface; wherein the memory transactions include a plurality of memory write command types, wherein each memory write command type corresponds to a different schedule for conveying a corresponding data payload; and wherein the memory transactions further include a plurality of memory read-modify-write command types, wherein each memory read-modify-write command type corresponds to a different operation performed on data read from a particular address within the memory device and subsequently written back to the particular address of the memory device, wherein each read-modify-write command type corresponds to one read-modify-write transaction being sent across the memory interface to the control unit.