Patent ID: 6114869
Filing Date: 2000-09-05
Classification: G01R

Abstract:
A system for interfacing between an integrated circuit die on a semiconductor wafer and (1) an automatic wafer probe machine, and (2) an automatic integrated circuit test system, the interfacing system comprising:(a) an insert ring adapted for attachment to a support of the wafer probe machine;(b) a lid hingeably attached to the insert ring, a first ring section adapted for rigid connection to a POGO tower, and a mounting assembly connecting the first ring section in spring-loaded relationship to the lid;(c) a lock ring assembly includingi. a lock ring rotatably disposed within a first one of the insert ring and the first ring section, the lock ring having an upper camming surface and a lower camming surface, andii. a cam element attached to the lock ring, the cam element having a sloped camming surface;(d) a retaining structure rigidly attached to the first one of the insert ring and the first ring section for engaging the upper and lower camming surfaces to retain the lock ring;(e) a probe card support attached to a bottom portion of the insert ring for supporting a probe card in fixed relation to the insert ring;(f) a POGO tower assembly including a plurality of POGO pins each having a lower spring-loaded contact for contacting the probe card; and(g) a cam follower rigidly attached to a second one of the first ring section and the insert ring for engaging the sloped camming surface when the lid is lowered to position a bottom surface of the POGO tower a predetermined distance above the probe card and following the camming surface lower as the lock ring is rotated in a predetermined direction to force POGO pins at the bottom of the POGO tower against contact pads of the probe card.