Patent ID: 7772689
Filing Date: 2010-08-10
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a resin member having a first surface and a second surface, said first surface defining a cavity in which a semiconductor chip is received such that the semiconductor chip is surrounded by the resin member, said semiconductor chip having a first surface with a plurality of pads and a second surface, said semiconductor chip first surface facing away from said resin member, while said semiconductor chip second surface facing toward and being affixed to said resin member first surface; and a wiring having a pattern wiring part formed directly on the first surface of the resin member, and a post part formed so as to extend in a thickness direction of the resin member, the post part includes one end that is connected to the pattern wiring part and another end that is formed so as to be exposed to the resin member second surface, which is opposite to the resin member first surface; a bonding pad and an electrode are formed on an exposed surface of said pattern wiring part; a wire having a first end electrically connected to said bonding pad and a second end electrically connected to said semiconductor chip; a sealing resin disposed over the first surface of said resin member so as to cover and encapsulate said bonding pad, said wire, and said semiconductor chip; wherein said electrode is exposed from said encapsulate.