Patent ID: 6855957
Filing Date: 2005-02-15
Classification: G02F,H01L

Abstract:
1. A semiconductor device comprising: a gate wiring having a taper shape formed over an insulating surface; an insulating film formed over said gate wiring; an amorphous semiconductor film formed over said insulating film; first and second impurity regions formed over said amorphous semiconductor film; a source wiring including a first portion formed over one of said first impurity region and said second impurity region and a second portion extending in an orthogonal direction with respect to said gate wiring; an electrode formed over the other of said first and said second impurity regions; a pixel electrode formed over said electrode; wherein said amorphous semconductor film and an amorphous semiconductor film containing an impurity element which imports n-type conductivity are laminated under the second portion of said souce wiring, a capacitor portion comprising: a terminal portion comprising: