Patent ID: 6617655
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A semiconductor device having a robust and reliable MOSFET gate external connection, comprising:a semiconductor body having a first surface and a second surface; a source contact area on the first surface of the semiconductor body; a drain contact area on the second surface of the semiconductor body; a gate contact area on the first surface of the semiconductor body and separate from the source contact area; a source contact metallization layer overlying the source contact area; a gate contact metallization layer overlying the gate contact area; a source contact passivation layer overlying the source contact metallization layer and having one or more openings exposing a portion of the surface of the source contact metallization layer; a gate contact passivation layer overlying the gate contact metallization layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer; a first insulating layer overlying the gate contact passivation layer and the source contact passivation layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer; a first conducting metal layer overlying the first insulating layer, connected to the gate contact metallization layer via the one or more openings in the first insulating layer, not overlying exposed areas of the source metallization layer, and partially overlying unexposed areas of the source contact metallization layer; a second insulating layer overlying the first conducting metal layer and the first insulating layer and having two or more openings each overlying the source contact metallization layer wherein each such opening exposes a portion of the surface of the first conducting metal layer; a second conducting metal layer having two or more zones each overlying and in contact with one exposed portion of the first conducting metal layer, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the first conducting metal layer; a metal plating layer having two or more zones each overlying and in contact with one exposed portion of the second conducting metal layer overlying an exposed portion of the first conducting metal layer, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the first conducting metal layer; and two or more solder bumps each overlying one metal plating layer zone, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the metal plating layer.