Patent ID: 7116742
Filing Date: 2006-10-03
Classification: G01R,H04B,H04L

Abstract:
1. A timing recovery system for generating a set of clock signals in a processing system, the set of clock signals comprising a set of sampling clock signals associated with a corresponding plurality of input signals, the processing system comprising a set of processing subsystems, each of the processing subsystems comprising an analog section, each of the analog sections operating in accordance with a corresponding one of the sampling clock signals, the timing recovery system comprising: (a) a set of phase detectors generating phase errors for the set of sampling clock signals; (b) a set of loop filters coupled to the set of phase detectors, the loop filters receiving the phase errors and generating filtered phase errors; (c) a set of digital-to-analog (D/A) converters coupled to the loop filters, the D/A converters receiving the filtered phase errors and generating analog filtered phase errors; and (d) a set of oscillators coupled to the set of D/A converters, the oscillators receiving the analog filtered phase errors and generating the sampling clock signals, wherein the sampling clock signals so generated are transmitted to respective subsystems; wherein the set of clock signals further comprises a receive clock signal and wherein each of the processing subsystems further comprises a digital section, the digital sections operating in accordance with the received clock signal; wherein the receive clock signal is related to one of the sampling clock signals.