Patent ID: 8766709
Filing Date: 2014-07-01
Classification: G05F,G11C

Abstract:
1. A semiconductor integrated circuit, comprising: a first internal voltage generator including a PMOS and a first comparator, the PMOS to receive a first voltage source and to output a first voltage generator output, a gate of the PMOS coupled to receive a first driving voltage from an output of the first comparator; a second internal voltage generator including an NMOS, a second comparator, and a voltage pump generator to provide a pumping power voltage to the second comparator, the NMOS to receive a second voltage source and to output a second voltage generator output, a gate of the NMOS coupled to receive a second driving voltage from an output of the second comparator; and a power control circuit configured to switchably enable the first voltage generator output from the first internal voltage generator during a power-on of the semiconductor integrated circuit or to enable the second voltage generator output from the second internal voltage generator after the power-on.