Patent ID: 7393768
Filing Date: 2008-07-01
Classification: H01L

Abstract:
1. A method for patterning a gate into a stack of layers of a semiconductor device, the method comprising the steps of: depositing a layer on a stack having a topographic step, wherein a thickness of the layer is greater than a final aimed thickness of the layer; contiguously followed by anisotropically etching back the layer to the aimed thickness, whereby a slope of the topographic step is decreased, and wherein an intervening etch-stopping layer is not present under the anisotropically etched back layer; thereafter depositing an anti-reflective coating layer upon the etched back layer; depositing a resist layer atop the stack; patterning the resist layer by lithographically illuminating the resist layer and developing the resist, whereby a resist pattern is obtained; transferring the resist pattern into the stack, whereby a patterned stack of layers is obtained; and thereafter removing the resist layer without leaving residues in the patterned stack of layers.