Patent ID: 6091260
Filing Date: 2000-07-18
Classification: H03K

Abstract:
An integrated circuit output buffer, comprising:an output signal line;a reference signal line;a first switch having a first terminal electrically coupled to said output signal line and a second terminal electrically coupled to said reference signal line;a second switch having a first terminal electrically coupled to said output signal line and a second terminal electrically coupled to said reference signal line; anda control circuit which closes said first and second switches during a first portion of a pull-up/pull-down time interval and opens said second switch while maintaining said first switch closed during a second portion of the pull-up/pull-down time interval, said control circuit having a first output that is electrically coupled to an input of said first switch and a second output that is electrically coupled to an input of said second switch and is fed back as an input of said control circuit.