Patent ID: 7838942
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a substrate including at least one logic device region and at least one SRAM device region, said device regions are separated by an isolation region; at least one double gated logic device within said at least one logic device region, wherein said at least one double gated logic device includes, from bottom to top, a back gate, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said logic device includes a doped channel; and at least one double gated SRAM device within said least one SRAM device region, wherein said at least one double gated SRAM device includes, from bottom to top, a back gate, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said SRAM device includes a non-doped channel and said back gate of said SRAM device has a higher doping level that said back gate of said logic device.