Patent ID: 6667203
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A method of fabricating a metal-oxide semiconductor (MOS) capacitor in a complementary MOS fabrication process with dual-doped gates, the method comprising:providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type; forming a dielectric layer on the substrate; forming a first gate of the first conductive type on the dielectric layer over the first well and a second gate of the second conductive type on the dielectric layer over the second well; after forming the first gate, performing a first channel implantation to form a first channel implantation region in the first well under the first gate abutting the first substrate electrode, wherein the first channel implantation region is implanted with dopants of the first conductive type; after forming the second gate, performing a second channel implantation to form a second channel implantation region in the second well under the second gate abutting the second substrate electrode, wherein the second channel implantation region is implanted with dopants of the second conductive type; forming a first doped region of the first conductive type in the substrate at each side of the first gate; forming a second doped region of the second conductive type in the substrate at each side of the second gate layer; forming a spacer on sidewalls of the first gate and the second gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region; implanting the exposed portion of the first doped region with dopants of the first conductive type to form a first substrate electrode; and implanting the exposed portion of the second doped region with dopants of the second conductive type to form a second substrate electrode.