Patent ID: 7003697
Filing Date: 2006-02-21
Classification: G01R

Abstract:
1. An apparatus for testing a device under test (DUT) having a plurality of pins, the apparatus comprising: a clock having a clock cycle; a plurality of pin electronics channels (PEs) capable of coupling to the plurality of pins on the DUT; a plurality of timing and format circuits (T/Fs) each capable of mapping a signal to one of the plurality of PEs; a pattern memory capable of storing a number of bits for testing the DUT, the pattern memory having a plurality of outputs capable of outputting the bits to test the DUT; and a pattern scrambler coupled between the plurality of outputs and the plurality of T/Fs, the pattern scrambler capable of being programmed to couple bits from any one or more of the plurality of outputs to any one or more of the plurality of T/Fs, to provide a test pattern to the DUT having a programmable width.