Patent ID: 6703284
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:providing a monolithic, epitaxially-grown substrate assembly, wherein the substrate assembly includes: a semi-insulating substrate; an N+ sub-collector layer; an N-type collector layer; a P-type base layer; and an N-type emitter layer; removing selected portions of the N-type emitter layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the N-type emitter layer is used to fabricate emitters for transistors and cathodes for breakdown diodes, wherein the cathodes of the breakdown diodes are coupled to a first reference; removing selected portions of the P-type base layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the P-type base layer is used to fabricate bases for transistors, anodes for steering diodes, and anodes for breakdown diodes, wherein the anodes of the breakdown diodes are coupled to a second reference; removing selected portions of the N-type collector layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the N-type collector layer is used to fabricate collectors for transistors and cathodes for steering diodes; isolating regions into the N+ sub-collector layer such that transistors, steering diodes, and breakdown diodes are electrically isolated; forming an insulating layer on selected portions of the substrate assembly; and forming electrical connections to the transistors, steering diodes, and breakdown diodes.