Patent ID: 8497722
Filing Date: 2013-07-30
Classification: H03K

Abstract:
1. An SR flip-flop configured to be capable of switching its logic priority, the SR flip-flop comprising: an input set terminal configured to receive a set signal as an input signal; an input reset terminal configured to receive a reset signal as an input signal; a control terminal configured to receive, as an input signal, a control signal which is an instruction for the SR flip-flop to switch its mode between a set priority mode and a reset priority mode; an input priority determination circuit configured to receive the set signal, the reset signal, and the control signal, to generate an intermediate set signal and an intermediate reset signal, and to operate such that (i) when the set signal is asserted and the reset signal is negated, the intermediate set signal is asserted, and the intermediate reset signal is negated, (ii) when the set signal is negated and the reset signal is asserted, the intermediate set signal is negated, and the intermediate reset signal is asserted, (iii) when the control signal indicates the set priority mode, and when the set signal and the reset signal are both asserted, the intermediate set signal is asserted, and the intermediate reset signal is negated, and (iv) when the control signal indicates the reset priority mode, and when the set signal and the reset signal are both asserted, the intermediate set signal is negated, and the intermediate reset signal is asserted; and an output SR flip-flop configured to receive the intermediate set signal via its set terminal, to receive the intermediate reset signal via its reset terminal, and to operate such that (i) when the intermediate set signal is asserted, its positive logic output is asserted, and (ii) when the intermediate reset signal is asserted, its positive logic output is negated.