Patent ID: 7343481
Filing Date: 2008-03-11
Classification: G06F

Abstract:
1. Apparatus for processing data under control of a sequence of program instructions stored in a memory, said apparatus comprising: an instruction prefetch unit, coupled to said memory, for prefetching, from a sequence of prefetch addresses within said memory, a sequence of program instructions to be executed; a static branch predictor for detecting an opcode of a branch instruction within said sequence of program instructions read from said memory and for performing a static prediction independent of previous processing activity as to whether said branch instruction will result in a jump to a branch target instruction stored at a branch target address within said memory, said instruction prefetch unit being responsive to a prediction by said static branch predictor that said branch instruction will result in said jump to alter said sequence of prefetch addresses to prefetch a sequence of program instructions starting from said branch target address; a static branch prediction cache, triggered by a static prediction by said static branch predictor of a branch instruction that will result in a jump to a target branch address, for storing said static prediction as a branch instruction address of said branch instruction together with said branch target address, said static prediction stored by said static branch prediction cache being unaltered by whether subsequent execution of said branch instruction does result in said jump; and an address comparitor for comparing a prefetch address of a program instruction being prefetched by said prefetch unit from said memory with said branch instruction address stored in said static branch prediction cache and upon a match to alter said sequence of prefetch addresses to prefetch a sequence of program instructions starting from said associated branch target address stored in said static branch prediction cache.