Patent ID: 7782068
Filing Date: 2010-08-24
Classification: G01R

Abstract:
1. A capacitance measurement circuit comprising: an integrator circuit having an input end and an output end, wherein the output end has an integrated voltage, and the integrator circuit, in response to a control signal, sets the integrated voltage to a start voltage level in a voltage setting period; a first control circuit comprising a first output end and a to-be-measured capacitor, wherein the first output end is electrically coupled to the input end, the first control circuit, in response to a first set of clock signals, switches a voltage on at least one end of the to-be-measured capacitor, and selectively enables one end of the to-be-measured capacitor to be electrically coupled to the first output end so as to control the integrator circuit to perform voltage integration and adjust the integrated voltage from the start voltage level to an end voltage level in a first integration period; a second control circuit comprising a second output end and a passive device, wherein the passive device has a known characteristic parameter, the second output end is electrically coupled to the input end, the second control circuit, in response to a second set of clock signals, switches a voltage on at least one end of the passive device, and selectively enables one end of the passive device to be electrically coupled to the second output end so as to control the integrator circuit to perform the voltage integration and adjust a level of the integrated voltage from the end voltage level to the start voltage level in a second integration period; and a processor circuit for providing the first and second sets of clock signals to drive the first and second control circuits, and for measuring a capacitance of the to-be-measured capacitor according to time lengths of the first and second integration periods and the known characteristic parameter.