Patent ID: 6731539
Filing Date: 2004-05-04
Classification: G11C,H01L

Abstract:
A bank of a memory, comprising:a plurality of memory cells arranged in N columns, wherein N is greater than 2, each memory cell comprising a channel region in a substrate, a floating gate overlaying the channel region, and a control gate overlying the floating gate; and N+1 diffused lines, wherein each of the N columns of memory cells is between in adjacent pair of the N+1 diffused lines, portions of the adjacent pair of diffused lines forming source/drain regions of the memory cells in the column between the adjacent pair of bit lines a plurality of first bank select cells, each first bank select cell comprising a transistor between a corresponding adjacent pair of the diffused lines and contact to a corresponding metal line; and a plurality of second bank cells, each second bank select cell comprising a transistor between a corresponding adjacent pair of the diffused lines and contact to a corresponding one of the metal lines, wherein the adjacent pairs of diffused lines corresponding to the second bank select cells are offset relative to the adjacent pairs of diffused lines corresponding to the first bank select cells.