Patent ID: 7755944
Filing Date: 2010-07-13
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells; a block selection circuit configured to select a memory block from the plurality of memory blocks; a plurality of wordline enable signal lines configured to transmit a voltage to a plurality of wordlines associated with the plurality of memory blocks; and a plurality of transfer transistors each having a current path connected between one of the wordline enable signal lines and a corresponding one of the wordlines and being controlled by an output of the block selection circuit, the plurality of transfer transistors including at least one dummy transfer transistor configured to transmit a dummy wordline enable signal, at least one transfer transistor configured to transmit a wordline enable signal, and at least one transfer transistor configured to transmit a selection gate enable signal; wherein the plurality of transfer transistors are arranged in order and operation of: the at least one transfer transistor configured to transmit the selection gate enable signal, the at least one dummy transfer transistor configured to transmit the dummy wordline enable signal, and the at least one transfer transistor configured to transmit the wordline enable signal, and wherein an isolation gap between the at least one dummy transfer transistor and the at least one transfer transistor configured to transmit the wordline enable signal is less than an isolation gap between the at least one dummy transfer transistor and the at least one transfer transistor configured to transmit the selection gate enable signal.