Patent ID: 6162668
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising the steps of:forming a gate electrode over a gate region on a surface of a semiconductor substrate of a first conductivity type;forming doped source and drain regions within the surface of the semiconductor substrate, wherein said doped source and drain regions together with said gate electrode form a MOSFET of a second conductivity type;forming an interlayer insulating film having respective contact holes with openings exposing the doped source and drain regions;forming a respective highly doped contact impurity region of the second conductivity type within each of said doped source and drain regions below the bottom of each respective contact hole;forming a respective lightly doped contact impurity region of the second conductivity type around each said respective highly doped contact impurity region; andforming a metallic wiring electrically connected to each said respective highly doped contact impurity region and extending onto said interlayer insulating film through each said respective contact hole.