Patent ID: 6458631
Filing Date: 2002-10-01
Classification: H01L

Abstract:
Method for fabricating an integrated circuit, comprising the following steps:preparing a circuit substrate (1); providing a metallization region (10a) comprising a first meal In the circuit substrate (1); providing a first insulator layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15â€²) above the resulting structure, including the base surface and side walls of the opening (13); depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; planarizing polishing-back of the second insulating layer (35) and of the functional layer (15â€²) in order to uncover the surface of the first insulating layer (25), the functional layer (15â€²) remaining only in the opening (13); forming a contact hole (12aâ€²) in the second insulating layer (35) inside the opening (13), which hole extends as far as the surface of the functional layer (15â€²) and filling the contact hole (12aâ€²) with a contact metal in order to form a contact and in order to make contact with the functional layer (15â€²); and providing an interconnect (40a) for electrical connection of the contact (11aâ€²).