Patent ID: 6980042
Filing Date: 2005-12-27
Classification: G06F

Abstract:
1. A method for generating a clock signal, comprising: receiving a first clock signal; generating a second clock signal based on the first clock signal, the second clock signal having a higher clock frequency than the first clock signal and further having a phase relationship with respect to the first clock signal related to a first time delay and relative to a rising or falling edge of the first clock signal; adjusting the first time delay to which the phase relationship between the first and second clock signals is related to a second time delay; monitoring the phase relationship between the first and second clock signals during adjustment of the first time delay to the second time delay; and generating a third clock signal based on the first clock signal, the third clock signal having the clock frequency of the second clock signal and having a phase relationship with respect to the first clock signal related to the second time delay relative to the rising or falling edge to which the first time delay was relative.