Patent ID: 6177812
Filing Date: 2001-01-23
Classification: H03D

Abstract:
A phase detector for detecting a phase difference between a reference clock and an oscillation clock, comprising:a shift register comprising a plurality off flip flops connected in series, for sequentially shifting a state of the reference clock having been inputted to a flip flop connected at a first stage, at either leading edge or trailing edge of the oscillation clock;a first logical gate for detecting either one of coincident and not-coincident states between a state of the reference clock and a state of an output signal of the flip flop connected at a first stage of said shift register;a second logical gate for detecting either a logical product or a logical sum of a state of an output signal of the flip flop connected at a second stage of said shift register and a state of an output signal of the flip flop connected at a third stage of said shift register; and a charge pump driven in response to outputs of said first logical gate and said second logical gate;wherein the shift register includes flip flops connected at three stages, in which a reference clock is input into a data input terminal of a flip flop at a first stage; a positive output from the flip flop at the first stage is input into a data input terminal of the flip flop at the second stage; a negative output of the flip flop at the second stage is input into a data input terminal of the flip flop at the third stage; and an oscillation clock is input into each of the flip flop clock input terminals.