Patent ID: 6252432
Filing Date: 2001-06-26
Classification: H03F,H03K

Abstract:
A translator circuit for translating a differential input signal including a first input signal and a second input signal that is the complement of the first input signal into a single output signal, the translator powered by a high-potential power rail and a low-potential power rail and having an output node, the circuit comprising:a. a first pull-up-facilitating device having a control node coupled to receive the first input signal;b. a second pull-up-facilitating device having a control node coupled to receive the second input signal;c. a first pulldown-facilitating device having a control node coupled to receive the first input signal;d. a second pulldown-facilitating device having a control node coupled to receive the second input signal;e. a first pull-up device having a high-potential node coupled to the high-potential power rail and a low-potential node coupled to the high potential nodes of said first pull-up-facilitating device and said second pull-up-facilitating device;f. a second pull-up device having a high-potential node coupled to the high-potential power rail and a low-potential node coupled to a high-potential node of said first pulldown-facilitating device and to the output node;g. a first pulldown device having a low-potential node coupled to the low-potential power rail and a high-potential node coupled to the low-potential nodes of said first pulldown-facilitating device and said second pulldown-facilitating device; andh. a second pulldown device having a low-potential node coupled to the low-potential power rail and a high-potential node coupled to a low-potential node of said first pull-up-facilitating transistor and to the output node.