Patent ID: 6553529
Filing Date: 2003-04-22
Classification: G01R

Abstract:
A semiconductor tester for testing a device-under-test having a combination of high-speed and low-speed pins, said tester including:a test controller having a pattern memory and a user interface; a pattern generation circuit having respective high-speed and low-speed modes for selectively producing test patterns according to said pattern memory for application to said device-under-test, said device-under-test operating according to a DUT clock period; a system bus connected to said test controller and said pattern generation circuit for routing command and data signals therebetween; drive/compare circuitry adapted for coupling to said device-under-test; a failure processing circuit disposed between said system bus and said drive/compare circuitry; and a timing system to generate event timing signals corresponding to predefined user settings, said timing system including: a timing memory circuit for storing programmed edge timings for said patterns; and timing logic including a master oscillator and a plurality of fixed edge generators, said fixed edge generators responsive to said programmed edge timings to produce said event timing signals.