Patent ID: 6487128
Filing Date: 2002-11-26
Classification: G11C

Abstract:
An integrated memory, comprising:a first pair of bit lines; a plurality of word lines and reference word lines; memory cells respectively arranged at crossing points of said word lines with a bit line of said first pair of bit lines and each having a selection switching element for connecting said memory cell with a respective said bit line and said selection switching element having a control connection connected to a respective said word line; a first differential read amplifier connected to said bit lines of said first pair of bit lines and a second differential read amplifier; two reference cells respectively arranged at a crossing point of one of said bit lines and a reference word line, having a structure substantially corresponding to a structure of said memory cells, and having a selection switching element for connecting said reference cells via a circuit node to a respective said bit line, and said selection switching element having a control connection connected to the respective said reference word line; first switching elements connecting said circuit nodes to said read amplifier; a first potential line for supplying a first potential to be stored in said reference cells; second switching elements connecting said circuit nodes to said first potential line; a second pair of bit lines connected to said second differential read amplifier and, in correspondence with said first pair of bit lines, having memory cells, reference cells, and first and second switching elements; two third switching elements each connecting a respective one of said bit lines of said first pair of bit lines to a bit line of said second pair of bit lines; and a second potential line connected to said circuit nodes of said bit lines of said second bit line pair via corresponding said second switching elements, said second potential line supplying a second potential to be stored in said reference cells of said second pair of bit lines.