Patent ID: 7103758
Filing Date: 2006-09-05
Classification: G06F,Y02D

Abstract:
1. A microcontroller comprising: a central processing unit generating a first address signal and executing a program including an instruction that causes the central processing unit to activate a halt signal, to stop executing the program until an interrupt signal is received, and then to inactivate the halt signal; a memory storm data including said program, receiving a mode signal, outputting the stored data when the mode signal is inactive, and discontinuing output of the stored data when the mode signal is active; and a control circuit receiving the halt signal from the central processing unit, the control circuit including an address control unit generating a second address signal for reading said part of the program, and a selector receiving the first address signal and the second address signal, selecting the first address signal when the halt signal is inactive, selecting the second address signal when the halt signal is active, and supplying the selected address signal to the memory, wherein, when the halt signal is activated, the control circuit reads said part of the program from the memory, internally stores said part of the program, then activates the mode signal, and wherein, when the halt signal is inactivated, the control circuit inactivates the mode signal and supplies the central processing unit with the internally stored part of the program.