Patent ID: 6317821
Filing Date: 2001-11-13
Classification: G06F

Abstract:
A processor comprising:a decode unit for decoding an instruction retrieved from a memory;an execution unit for executing at least a portion of the instruction;a plurality of registers including at least one register associated with the instruction; anda locking mechanism operative to indicate a lock status for each of at least a subset of the plurality of registers, the subset including the register associated with the instruction, the locking mechanism comprising a stored bit vector having a plurality of bits indicative of the lock status for the corresponding registers, wherein the lock status of the register associated with the instruction is checked prior to permitting the instruction to execute, and wherein the instruction is automatically committed to completion of execution if the register lock status when checked indicates that the associated register is unlocked, such that the instruction is thereby permitted to complete execution, relative to other instructions associated with a program containing the instruction, in an order that is different than a dispatch order of the instructions as specified by the program, wherein the completion of execution includes writeback of results of execution of the instruction to one or more destination registers.