Patent ID: 7868411
Filing Date: 2011-01-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a cell array region and a peripheral circuit region; first and second cell gate patterns disposed in the cell array region, and sequentially arranged outwardly from a center of the cell array region; a peripheral gate pattern disposed in the peripheral circuit region; a defining pattern disposed between the cell array region and the peripheral circuit region to surround the cell array region; buried insulating patterns disposed around the first cell gate pattern, between the first and second cell gate patterns, and between the second cell gate pattern and the defining pattern; planarization insulating patterns disposed between the defining pattern and the peripheral gate pattern, and around the peripheral gate pattern; isolation regions disposed in the cell array region and the peripheral circuit region to define a cell active region of the cell array region and a peripheral active region of the peripheral circuit region, wherein the first and second cell gate patterns have a lower cell gate electrode, an upper cell gate electrode and a cell gate capping pattern, which are sequentially stacked and are respectively disposed on the cell active region and the isolation regions and the peripheral gate pattern has a lower peripheral gate electrode, an upper peripheral gate electrode and a peripheral gate capping pattern, which are sequentially stacked, to be disposed on the peripheral active region; cell spacers respectively disposed on sidewalls of the first and second cell gate patterns; and a pair of peripheral spacer patterns disposed on sidewalls of the peripheral gate pattern; wherein one of the cell spacers and one of the peripheral spacer patterns are disposed on sidewalls of the defining pattern, and wherein the defining pattern is a dummy gate pattern disposed on the isolation regions between the second cell gate pattern and the peripheral gate pattern, and the dummy gate pattern is a lower dummy gate, an upper dummy gate and a dummy capping pattern, which are sequentially stacked.