Patent ID: 8036614
Filing Date: 2011-10-11
Classification: H03L

Abstract:
1. A delay-locked loop, comprising: a) a replica delay block having a first delay control input and a second delay control input, said delay block being configured to receive a reference clock signal, a first delay control signal at said first delay control input, and a delay synchronization signal at said second delay control input, and to output a replica-delayed clock signal; b) a phase and/or frequency detector configured to output said delay synchronization signal in response to said reference clock signal and said replica-delayed clock signal; and c) a delay line having a third delay control input and a fourth delay input, said delay line including a plurality of main delay blocks operatively connected in series, said delay line configured to receive said reference clock signal at the first of said delay blocks connected in series, said delay synchronization signal at said third delay control input and a second delay control signal at said fourth delay control input, and configured to output a delayed clock signal.