Patent ID: 6560668
Filing Date: 2003-05-06
Classification: G06F,G11C

Abstract:
An integrated synchronous memory device having a read latency and a write latency wherein the read latency and write latency are equal, comprising:a memory array; an address bus configured to receive read and write addresses; an address path coupled between the address bus and the memory array including an address comparator, the address comparator being operative to provide a control signal in response to a received read address matching a write address received at the address bus and still in the address path; a data bus; an input data path coupled between the data bus and the memory array; an output data path coupled between the data bus and the memory array; and a bypass circuit coupled between the input data path and the output data path and bypassing the memory array, the bypass circuit being responsive to the control signal from the address comparator to provide a bypass path between the input and output data paths.