Patent ID: 6904578
Filing Date: 2005-06-07
Classification: G06F

Abstract:
1. An apparatus for verifying a property associated with a target circuit, comprising: a partitioned ordered binary decision diagram (POBDD) data structure operable to receive information associated with a target circuit, the information identifying a property within the target circuit to be verified, the POBDD data structure executing one or more operations in order to generate a first set of states at a first depth associated with a sub-space within the target circuit; and a bounded model checking (BMC) tool element operable to receive the first set of states from the POBDD data structure, the BMC tool element executing one or more bounded model checking operations using the first set of states in order to generate a second set of states at a second depth associated with the sub-space within the target circuit, the first set of states being used as a basis for the second set of states such that the second depth is greater than the first depth.