Patent ID: 6700429
Filing Date: 2004-03-02
Classification: H03K

Abstract:
A semiconductor device including a differential level converter circuit that receives a first signal and a phase-inverted signal of the first signal and outputs a second signal of a larger amplitude than an amplitude of the first signal, the differential level converter circuit comprises a first MISFET pair for receiving the first signal and a phase-inverted signal of the first signal; a second MISFET pair for improving a withstand voltage of the first MISFET pair; and a third MISFET pair having cross-coupled gates for latching the second signal to output,wherein a film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the first MISFET pair; wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair; wherein an absolute value of a threshold voltage of the second MISFET pair is smaller than an absolute value of a threshold voltage of the third MISFET pair; and wherein an absolute value of a threshold voltage of the first MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair; wherein the level converter circuit further comprises a first gate boosting circuit that boosts the first signal with the amplitude of the first signal to form a third signal with an amplitude bigger than the amplitude of the first signal so as to supply the third signal to one gate of the second MISFET pair; and a second gate boosting circuit that boosts the phase-inverted signal of the first signal with the amplitude of the first signal to form a fourth signal with an amplitude bigger than the amplitude of the first signal so as to supply the fourth signal to the other gate of the second MISFET pair.