Patent ID: 6191976
Filing Date: 2001-02-20
Classification: G11C

Abstract:
A FLASH memory sense circuit comprising:a FLASH memory MOS transistor having source-drain path connected between a first sensing terminal and ground, said FLASH memory MOS transistor storing thereon a charge indicative of a digital state;a fixed load device connected between said first sensing node and a predetermined voltage;a dummy FLASH memory MOS transistor having source-drain path connected between a second sensing terminal and ground;a selectable load device connected between said second sensing terminal and said predetermined voltage, said selectable load providing a selectable resistance between said second sensing terminal and said predetermined voltage; anda sense amplifier connected to said first and second sensing terminals having an output indicative of which of said first or second sensing terminals has a greater voltage, wherein:said selectable load device consists of a plurality of dummy load MOS transistors, each having a source-drain path connected between said second sensing node and said predetermined voltage and a gate connected to receive respective select signals, said selectable load device providing said selectable resistance by predetermined combinations of said select signals turning ON said respective dummy load MOS transistors.