Patent ID: 6297118
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A method for manufacturing a vertical bipolar semiconductor power transistor with an interdigitized geometry, comprising:growing a first epitaxial layer with a first conductivity type;implanting in the first epitaxial layer a base buried region having a second conductivity type and a first doping level, and above this base buried region, an emitter buried region having the first conductivity type and a second doping level;growing a second epitaxial layer having the first conductivity type and a third doping level lower than the second doping level, the second epitaxial layer defining a main surface;forming a sinker base region having the second conductivity type and extending from the main surface to the base buried region and laterally and downwards delimiting, together with the base buried region, one or more finger regions in the second epitaxial layer; andforming a sinker emitter region with the first conductivity type and a fourth doping level higher than the third doping level, said sinker emitter region extending from the main surface to the emitter buried region inside the finger regions, the emitter buried region and the sinker emitter region forming in each finger region pairs of sections which are mutually spaced and delimit therebetween a central region in the second epitaxial layer.