Patent ID: 7397121
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; a MOS device in or on said silicon substrate; a first metal layer over said silicon substrate; a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a passivation layer over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer; a first contact pad exposed by a first opening in said passivation layer; a second contact pad exposed by a second opening in said passivation layer; a third contact pad exposed by a third opening in said passivation layer, wherein said first, second and third contact pads are aligned in a first line, wherein said second contact pad is between said first and third contact pads; a patterned metal layer over said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a first gold layer having a thickness between 1 and 10 micrometers over said passivation layer and over said first, second and third contact pads, and wherein said patterned metal layer comprises a metal trace over said passivation layer, and a fourth contact pad connected to said second contact pad through said metal trace, wherein the position of said fourth contact pad from a top perspective view is different from that of said second contact pad; a first metal bump on said patterned metal layer and over said first contact pad; a second metal bump on said fourth contact pad; and a third metal bump on said patterned metal layer and over said third contact pad, wherein said first and third metal bumps are aligned in a second line parallel with said first line, and wherein said first, second and third metal bumps all comprise a second gold layer, having more than 95 percent by weight of gold and having a height between 1 and 50 micrometers, directly on said first gold layer.