Patent ID: 6437598
Filing Date: 2002-08-20
Classification: H03K

Abstract:
A programmable logic device (PLD) comprising an AND array, the AND array including a first scalable product term (pterm) circuit comprising:a first plurality of logic input lines; a first AND gate comprising a first plurality of input terminals and a first output terminal, each of the first plurality of input terminals being connected to one of the first plurality of logic input lines; a first alternative logic circuit comprising a second plurality of input terminals and a second output terminal, each of the second plurality of input terminals being connected to one of the first plurality of logic input lines, the first alternative logic circuit providing a first logical operation, the first logical operation being different than an AND operation; and a first output control circuit comprising a third plurality of input terminals and a third output terminal, the first output terminal being connected to a first one of the third plurality of input terminals, and the second output terminal being connected to a second one of the third plurality of input terminals.