Patent ID: 9007824
Filing Date: 2015-04-14
Classification: G11C

Abstract:
1. A memory device comprising: memory elements arranged in an array including rows associated with wordlines and columns associated with bitlines, wherein memory elements in a row share a wordline and memory elements in a column share a bitline; a boost circuit that is configured to read a read signal input during a read operation of the memory device and to provide a first negative voltage at an output during the read operation, wherein the boost circuit includes an inverter that is configured to read the read signal input during the read operation, wherein an output of the inverter is coupled to a gate terminal of a transistor and a first plate of a capacitor that are included in the boost circuit, and wherein the transistor and the capacitor are configured to provide the first negative voltage at the output; and a wordline driver circuit that includes a buffer coupled to an associated wordline, wherein the buffer is further coupled to the boost circuit and configured to receive the first negative voltage and to provide an output voltage to the associated wordline such that the associated wordline, when unselected during the read operation, is held at a second negative voltage below a ground potential based on the first negative voltage.