Patent ID: 7864021
Filing Date: 2011-01-04
Classification: H01F,H01L

Abstract:
1. An integrated circuit device in which a first interconnect layer, a first insulating layer, a second interconnect layer, a second insulating layer, and a third interconnect layer are laminated in this order, the integrated circuit device comprising: a main interconnect formed in the third interconnect layer and including a first section extending in a first direction parallel to a surface of the first interconnect layer and a second section extending in the opposite direction of the first direction; a first coil made of an interconnect formed in the first interconnect layer, an interconnect formed in the second interconnect layer, and a via formed in the first insulating layer, the first coil being located directly below the first section and having a central axis extending in a second direction that is parallel to the surface of the first interconnect layer and orthogonal to the first direction; a second coil made of an interconnect formed in the first interconnect layer, an interconnect formed in the second interconnect layer, and a via formed in the first insulating layer, the second coil being located directly below the second section and having a central axis extending in the second direction; a first interconnect formed in one of the first interconnect layer and the second interconnect layer and connecting an end of the first coil on the second section side to an end of the second coil on the side farther from the first section; and a second interconnect formed in the other of the first interconnect layer and the second interconnect layer, one end of the second interconnect being connected to an end of the second coil on the first section side and the other end of the second interconnect being extracted to the side of the first section farther from the second section, the first coil having the same shape and winding direction as the second coil, and as viewed from a direction orthogonal to the surface of the first interconnect layer, the first interconnect crossing the second interconnect, and the area of a region enclosed by the first section, the first interconnect, and the second interconnect being equal to the area of a region enclosed by the second section, the first interconnect, and the second interconnect.