Patent ID: 6609192
Filing Date: 2003-08-19
Classification: G06F

Abstract:
A data processing system comprising:a memory coupled to a plurality of processors via an interconnect; an instruction sequencing unit for fetching an instruction sequence in program order for execution, said instruction sequence including a first and a second load instruction and a barrier instruction, which is between said first and second load instructions in said instruction sequence; and a load/store unit (LSU) including: a load request queue (LRQ) that temporarily buffers load requests associated with said first and second load instructions; a load request arbitration unit coupled to said LRQ, which selects an order of issuing said load requests from said LRQ, wherein said load requests are issued out-of-order with respect to said program order before or after said barrier instruction; and a controller that issues a load request associated with said second load instruction to said memory before completion of a barrier operation associated with said barrier instruction.