Patent ID: 7129566
Filing Date: 2006-10-31
Classification: H01L

Abstract:
1. A semiconductor wafer comprising: a substrate; an interconnect structure located over the substrate; a plurality of die areas; a street located between a first die area of the plurality and a second die area of the plurality; and a separation structure, wherein the separation structure includes at least two rows of a plurality of independent column portions of metal structures located in the interconnect structure, at least a portion of the separation structure is located in a saw kerf of the street, wherein each row of the plurality of independent column portions of metal structures of the separation structure is spaced apart from another row of the plurality of independent column portions of metal structures to provide a potential separation path in between adjacent rows of independent column portions of metal structures for separating the first die area during a singulation process, further wherein each independent column portion of metal structures of a row comprises a selectively reinforced structure, separated from an adjacent selectively reinforced structure of the same row by a non-reinforced region, further wherein a first row of the plurality of independent column portions of metal structures is separated from an adjacent row of the plurality of independent column portions of metal structures by a non-reinforced region, further wherein the potential separation path lies within the non-reinforced region between the adjacent rows of the plurality of independent column portions of metal structures, and further wherein the at least two rows of the plurality of independent column portions of metal structures are configured to produce a predictable, controlled failure mechanism by breaking up into manageable pieces of column portions during the singulation process.