Patent ID: 6552949
Filing Date: 2003-04-22
Classification: G11C

Abstract:
A memory device, comprising:a column of memory cells, each memory cell being arranged to store a data value; a pair of bit lines coupled to said column of memory cells; bit line precharge circuitry for precharging said pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in said column is selected in an evaluate phase following said precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell; power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging said pair of bit lines; and selector circuitry arranged when the memory device is to enter said power down mode to ensure that none of said memory cells in said column are selected.