Patent ID: 9088284
Filing Date: 2015-07-21
Classification: G06F,H03K

Abstract:
1. A system comprising: a main memory; said main memory comprising RAM; a plurality of preliminary counters each fed by a corresponding event source; and a sweeper which repeatedly accesses said preliminary counters and feeds values from said preliminary counters to said RAM in a plurality of continuous successive sweeps using an M-bit free running counter, said plurality of sweeps being conducted at fixed, predetermined intervals of 2**M (2 to the power of M) cycles of incrementing said M-bit free running counter, wherein said sweeper accesses, in each sweep, each counter of said plurality of preliminary counters in a predetermined order, feeds a value of the respective preliminary counter to said RAM, and resets the respective preliminary counter, a single respective counter of said plurality of preliminary counters being selected in each of a plurality of cycles of said 2**M cycles according to a respective corresponding value of said M-bit free running counter, each successive sweep commencing upon completion of an immediately preceding sweep, said fixed, predetermined intervals being sufficiently short to prevent overflow of a count of any event maintained in said preliminary counters; said RAM acting to accumulate counting data relating to the event sources.