Patent ID: 6114892
Filing Date: 2000-09-05
Classification: G01R

Abstract:
A low power scan flop cell, comprising:a scan cell having inputs including a data input pin, a scan input (SI) pin, a scan enable input, and a clock input, and outputs including a Q' output and an NQ' output;a first logic gate having a Q output, and having a first input pin that is connected to the Q' output of the scan cell, and a second input pin;a second logic gate having an NQ output, and having a first input pin that is connected to the NQ' output of the scan cell, and a second input pin;an electrical interconnection being formed between the scan enable input of the scan cell and the second input pin of both the first logic gate and the second logic gate; anda scan output (SO) pin being connected to the Q' output that is coupled to the first input pin of the first logic gate.