Patent ID: 7239997
Filing Date: 2007-07-03
Classification: G06F

Abstract:
1. A statistical LSI delay simulation apparatus comprising: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and obtaining the dependency of a delay variation of each said circuit cell on respective operation conditions under a delay average value and a delay standard deviation value to generate a statistical delay library in which the dependency is described; a delay calculator for calculating a delay amount of each said circuit cell in the LSI by referring to the statistical delay library to generate a statistical LSI delay information file containing delay data for each said circuit cell; and a timing analyzer for simulating, based on the data contained in the statistical LSI delay information file, the operation containing delay variation of the LSI, wherein as the operation conditions, a rise time or fall time of input signal of each said circuit cell or output load capacitance of each said circuit cell are used.