Patent ID: 6249860
Filing Date: 2001-06-19
Classification: G01R,G06F

Abstract:
A system comprising:A. a microprocessor device having data pins carrying data signals, address pins carrying address signals, and control outputs carrying control signals, the microprocessor device being capable of receiving data signals at the data pins a certain period of time after sending address and control signals and being capable of performing a desired number of wait states after sending address and control signals, the microprocessor device including at least two wait state registers, each wait state register containing a number defining a number of wait states, each wait state register being connected to the data signals to receive data signals representing a number defining a number of wait states, and each wait state register being coupled to the address signals;B. at least two external devices external of the microprocessor device, each external device having data pins, address pins and a control input connected to the control outputs of the microprocessor device, each external device producing data at the data pins after receiving address signals in a separate segment of the external memory space;C. an external data bus connecting together the respective data pins of the microprocessor device and the external devices; andD. an external address bus connecting together the respective address pins of the microprocessor device and the external devices.