Patent ID: 8481415
Filing Date: 2013-07-09
Classification: H01L

Abstract:
1. A method of forming a semiconductor device comprising: forming a replacement gate structure on a portion of a substrate, wherein source regions and drain regions are formed in opposing sides of the portion of the substrate that the replacement gate structure is formed on; forming an intralevel dielectric on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure; removing the replacement gate structure to provide an opening to an exposed portion of the substrate; forming a high-k dielectric spacer on sidewalls of the opening; forming a gate dielectric on the exposed portion of the substrate; forming a functioning gate structure within the opening on the gate dielectric, wherein an upper surface of the functioning gate structure is a high-k dielectric capping layer; and forming contact vias through the interlevel dielectric layer to at least one of the source region and the drain region, wherein an etch that provides the opening for the contact via is selective to the high-k dielectric spacer and the high-k dielectric capping layer.