Patent ID: 6373321
Filing Date: 2002-04-16
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a first CMOS circuit including first P and N channel MOS transistors a second CMOS circuit including second P and N channel MOS transistors and having an input coupled to an output of said first CMOS circuit, a third CMOS circuit including third P and N channel MOS transistors and having an input coupled to an output of said second CMOS circuit, a first line coupled to a substrate of each of said first and third P channel MOS transistors, commonly, a second line coupled to a substrate of each of said first and third N channel MOS transistors, commonly, first potential supply means for supplying to said first line a first potential equal to or higher than a potential of a source electrode of each of said first and third P channel MOS transistors when said first and third P channel MOS transistors are turned off, second potential supply means for supplying to said first line a second potential lower than the potential of the source electrode of each of said first and third P channel MOS transistors when said first and third P channel MOS transistors are turned on, third potential supply means for supplying to said second line a third potential equal to or lower than a potential of a source electrode of each of said first and third N channel MOS transistors when said first and third N channel MOS transistors are turned off, and fourth potential supply means for supplying to said second line a fourth potential higher than the potential of the source electrode of each of said first and third N channel MOS transistors when said first and third N channel MOS transistors are turned on.