Patent ID: 6300655
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A semiconductor device comprising:semiconductor substrate having one principal surface and a first conductivity type surface area exposed to the principal surface;an element isolation insulating region formed on the principal surface of said semiconductor device and defining a plurality of active regions in the first conductivity type surface area;a gate insulating film formed on a partial surface of each of the plurality of active regions;a plurality of word lines each partially disposed on said gate insulating film on the principal surface and made of conductive material, each of the plurality of word lines extending in a first direction as a whole;a plurality of bit lines extending in a second direction as a whole intersecting with the first direction on the principal surface;a plurality of capacitors formed on the principal surface; anda plurality of memory cell transistors formed in the plurality of active regions, each memory cell using one word line as a gate electrode and having a pair of source and drain regions of a second conductivity type opposite to the first conductivity type, the source and drain regions being defined by the gate electrode and said element isolation insulating region, one of the pair of source and drain regions being connected to one of the plurality of bit lines, the other of the pair of source and drain regions being connected to one of the plurality of capacitors, three sides of an area of the other of the pair of source and drain regions being defined by said element isolation insulating region, and the other of the pair of source and drain regions including a first impurity doped region extending to a location under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.