Patent ID: 7093060
Filing Date: 2006-08-15
Classification: G06F

Abstract:
1. A method of coupling a host that is equipped with a central processing unit (CPU) level processing capacity, a non-volatile random access memory (NVRAM), and at least a controller together to allow the host to access the NVRAM and the controller, the method comprising: transmitting an instruction and a pragmatic bit from the host to the controller and the NVRAM, wherein the controller is coupled with the host and the NVRAM, respectively via a chip-select line, a system-clock line and a data transmission_wiring ; indicating the instruction either for the NVRAM or for the controller by the pragmatic bit which is accompanied with the instruction; turning either the NVRAM or the controller on/off according to the pragmatic bit; and executing the instruction either at the NVRAM or at the controller to control simultaneously the NVRAM and the controller.