Patent ID: 6852615
Filing Date: 2005-02-08
Classification: H01L,Y10S

Abstract:
1. A process for fabricating a Group III V semiconductor structure comprising the steps of: depositing Group III V elements in three layers, with a first layer, a second layer, and a third layer, wherein said first layer is deposited on a substrate, said second layer is deposited on said first layer, said third layer is deposited on said second layer; patterning and depositing a first photoresist on said third layer; providing an unprotected portion of said third layer, wherein said unprotected portion of said third layer is not in contact with said first photoresist; reducing a thickness of said unprotected portion of said third layer to form a recessed area; removing said first photoresist; patterning and depositing a second photoresist on said third layer; depositing ohmic metal on at least a portion of said third layer, wherein said ohmic metal covers said recessed area; removing said second photoresist; and annealing said semiconductor structure.