Patent ID: 8956973
Filing Date: 2015-02-17
Classification: H01L

Abstract:
1. A method of plating a through-substrate via (TSV) hole in a substrate, the TSV hole comprising an open end terminating at a conductive pad, a stack of wiring levels superimposed to one another positioned on top of the conductive pad, and a plurality of chip interconnects configured on a top surface of an upper wiring level, the method comprising: attaching a handler to the plurality of chip interconnects with a temporary solder contact, the handler comprising a conductive layer in electrical contact with the plurality of chip interconnects via the temporary solder contact; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path comprising the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad, wherein the conductive layer is formed on a top surface of the handler, further comprising forming one or more conductive channels extending from the conductive layer to a bottom surface of the handler.