Patent ID: 7237149
Filing Date: 2007-06-26
Classification: G06F

Abstract:
1. Circuitry used during a debug operation, comprising: debug condition determining circuitry which determines if a debug condition associated with an access has occurred; a first source register; a second source register; a first user-determinable enable/disable mechanism, corresponding to the first source register, said first user-determinable enable/disable mechanism specifying whether to enable/disable the debug operation when the first source register sources at least a portion of access information associated with the access; a second user-determinable enable/disable mechanism, corresponding to the second source register, said second user-determinable enable/disable mechanism specifying whether to enable/disable the debug operation when the second source register sources said at least a portion of access information associated with the access; source determining circuitry which determines if the first source register or the second source register is sourcing said at least a portion of access information associated with the access; and enable/disable circuitry which selectively enables/disables the debug operation, said enable/disable circuitry being coupled to said first user-determinable enable/disable mechanism, to said second user-determinable enable/disable mechanism, to said source determining circuitry, and to said debug condition determining circuitry, wherein the enable/disable circuitry disables the debug operation if wherein the enable/disable circuitry also disables the debug operation if