Patent ID: 7586176
Filing Date: 2009-09-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: an integrated circuit; a plurality of metallization layers, the plurality of metallization layers comprising a first metallization layer and at least one second metallization layer disposed over the first metallization layer, wherein each metallization layer is formed in an insulating layer; a scribe line adjacent the integrated circuit; a seal ring substantially surrounding the integrated circuit; a crack prevention ring disposed around an exterior edge of the integrated circuit, the crack prevention ring being interjacent the seal ring and the scribe line and comprising a conductive material and extending into a plurality of non-conductive layers at least to a depth of the at least one second metallization layer, wherein the crack prevention ring comprises a trench at least partially filled with the conductive material, and wherein the crack prevention ring trench is lined with the conductive material; and a passivation layer disposed over the integrated circuit and the crack prevention ring, wherein the crack prevention ring includes an air pocket disposed beneath the passivation layer.