Patent ID: 6410390
Filing Date: 2002-06-25
Classification: H01L

Abstract:
A method for fabricating a nonvolatile memory device comprising the steps of:defining first and second active regions to be arranged on a semiconductor substrate in one direction; depositing a first gate insulating layer and a floating gate on the first and second active regions in a pattern, and depositing a second gate insulating layer and a control gate line in one direction perpendicular to the first and second active regions to cover the floating gate; forming first impurity regions in the first and second active regions at one side of the control gate line; forming second impurity regions in the first and second active regions at other side of the control gate line; forming a buffer insulating layer on the entire surface of the semiconductor substrate including the first and second impurity regions; forming a first interlayer dielectric on the semiconductor substrate such that first contact holes are provided in the first impurity regions and that a line-type contact hole is formed by connecting and exposing the second impurity regions of the first and second active regions; forming a third impurity region by injecting ions into the first and second impurity regions exposed by the first contact holes and the line-type contact hole; removing the buffer insulating layer from the first contact holes and the line-type contact hole; and forming first contact plugs in the first contact holes and forming a common conductive line in the line-type contact hole.