Patent ID: 7742326
Filing Date: 2010-06-22
Classification: G11C

Abstract:
1. An integrated circuit comprising an SRAM, said SRAM comprising: an array of SRAM cells arranged in rows and columns, each cell including a write transistor and a read transistor; a write word line associated with a row, the write word line directly connected to a control terminal of the write transistor to control access to the cells in the row for write operations but not read operations; a read word line associated with a row, the read word line connected to a control terminal of the read transistor to control access to the cells in the row for read operations; a write bit-line associated with a column operable to provide input to the cells in the column for write operations; and a read bit-line associated with the column operable to receive output from cells in the column during read operations; the elements being dimensioned and configured so that voltage applied at the control terminal of the write transistor to enable write operations is lower than voltage applied at the control terminal of the read transistor to enable read operations.