Patent ID: 6091667
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array having a plurality of word lines a plurality of bit lines, divided into a predetermined number of groups, and a plurality of memory cells, each of which is located at an intersection of said word line and said bit line, said bit lines being grouped based on a residue obtained by dividing a column address designating said bit line by said number of groups;word line selection means for selecting one of said word lines in accordance with a row address signal;bit line selection means for selecting one of said bit lines for each of said groups in accordance with a column address signal and an access order signal designating the access order for said groups;a plurality of latch means, each of which is provided for each of said groups for latching data; andmultiplexer means, connected to said plurality of latch means, for selectively connecting said latch means to input/output terminals wherein, when said access order signal designates the ascending order, said bit line selection means generates a plurality of column addresses corresponding to the group number, said column addresses contiguous in said ascending order with said column address signal serving as a reference, wherein, when said access order signal designates the descending order, said bit line selection means generates column addresses corresponding to the group number, said column addresses contiguous in said descending order with said column address signal serving as a reference, and wherein said bit line selection means respectively connects said bit lines designated by said generated column addresses, to said latch means corresponding to said groups to which said bit lines belong.