Patent ID: 6085269
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A microprocessor host module for a computer system, comprising:a host CPU, for executing program instructions upon digital data, coupled to a module bus; anda configurable expansion bus controller, coupled to the module bus and to first data lines, first control lines, second data lines and second control lines, for communicating signals from the module bus to the first data lines, the first control lines, the second data lines and the second control lines according to one or more selected bus protocols, comprising:configuration logic, for receiving configuration signals indicating the selection of bus protocols; andbridge circuitry, coupled on one side to the module bus and on another side to the first data lines, the first control lines, the second data lines and the second control lines, and coupled to the configuration logic so that, responsive to the configuration signals indicating a first configuration mode, the bridge circuitry communicates signals between the module bus and the first data lines, the first control lines and the second data lines according to a first bus protocol in which data conductors in the first data lines and second data lines cooperate as a single bus, and so that, responsive to the configuration signals indicating a second configuration mode, the bridge circuitry communicates signals between the module bus and the first data lines and first control lines according to a second bus protocol and separately communicates signals between the module bus and the second data lines and second control lines as an independent bus relative to the first data lines and first control lines.