Patent ID: 7901981
Filing Date: 2011-03-08
Classification: H01L

Abstract:
1. A method for packaging integrated circuits, the method comprising: sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, wherein the epoxy layers include a first epoxy layer and a second epoxy layer, the epoxy layers being deposited by spin coating, there being a topmost epoxy layer; photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited, wherein the patterning of the at least one of the epoxy layers includes patterning the first epoxy layer; forming openings in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited, wherein the forming of the openings includes forming an opening in the first epoxy layer; placing a first integrated circuit within the opening in the first epoxy layer, wherein the first integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the first integrated circuit to thereby cover the first integrated circuit; forming at least one conductive interconnect layer, wherein each interconnect layer is formed over an associated epoxy layer; photolithographically patterning the second epoxy layer; forming an opening in the second epoxy layer; placing a second integrated circuit within the opening in the second epoxy layer; and forming a multiplicity of external package contacts, wherein the first integrated circuit is electrically connected to a plurality of the external package contacts at least in part through at least one of the conductive interconnect layers.