Patent ID: 7892910
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: forming at least one pad layer over an active semiconductor area; forming an opening in said at least one pad layer to expose said active semiconductor area; depositing an intrinsic base layer directly on said active semiconductor area and over said at least one pad layer; forming at least one emitter pedestal layer on said intrinsic base layer; forming an emitter pedestal directly on said intrinsic base layer; selectively depositing an extrinsic base layer on exposed portions of said intrinsic base layer and over said at least one pad layer after formation of said emitter pedestal, wherein a semiconductor material of said extrinsic base layer does not grow from surfaces of said emitter pedestal; forming a base cap dielectric layer on said extrinsic base layer; and forming a mesa structure with substantially planar and vertical sidewall surfaces, wherein each of said substantially planar and vertical sidewall surfaces contains said at least one pad layer, said intrinsic base layer and said extrinsic base layer.