Patent ID: 7792139
Filing Date: 2010-09-07
Classification: H04L

Abstract:
1. A synchronized data acquisition system in a processing line having a plurality of stages, each stage separated from adjacent stages by up to 100 meters or more, comprising a plurality of monitoring instruments, one at each of the stages of the processing line, for monitoring selected operating parameters at such stages; a plurality of ethernet interface gates, one associated and communicating with each of said monitoring instruments, said ethernet interface gates being daisy-chained together, each to an immediately adjacent one, said ethernet interface gates having an ethernet input and output, the inputs and outputs of at least certain of said ethernet interface gates being respectively connected to the output and input of adjacent Ethernet interface gates; a data and control buss interconnecting each of said ethernet interface gates with an associated one of said monitoring instruments; a processing unit connected to one of said ethernet interface gates; and wherein each said ethernet interface gate has a phase lock loop clock reconstruction circuit, receiving said clock signal from said ethernet input, applying it to an associated monitoring instrument, and passing it to said ethernet output, and a synchronization circuit, receiving said synchronization signal from said ethernet input, applying it to an associated monitoring instrument, and passing it to said ethernet output, wherein said phase lock loop clock restoration circuit has a crystal oscillator which is adjustably phase-aligned to said clock signal.