Patent ID: 7659757
Filing Date: 2010-02-09
Classification: G06F,H03K

Abstract:
1. A clock regeneration circuit, comprising: an asynchronous clock signal input to a first meta-stability filtering circuit, the first meta-stability filtering circuit including first and second filtering flip flops; a first synchronous clock signal input to the first meta-stability filtering circuit, the first synchronous clock signal having a frequency lower than the asynchronous clock signal, the first synchronous clock signal being over-sampled and re-timed to the asynchronous clock signal by the first meta-stability filtering circuit to produce an over-sampled and re-timed output of the first meta-stability filtering circuit; a second meta-stability filtering circuit, the second meta-stability filtering circuit including third and fourth filtering flip flops that are clocked by the asynchronous clock signal, and receiving an input that is synchronous to the first synchronous clock signal; an edge detector circuit including an edge detecting flip-flop, an inverter, and a first and-gate, the edge detector circuit edge detecting an edge of the output of the first meta-stability filtering circuit, the edge detector circuit producing an edge-detected output; a delay circuit including at least one delay flip flop, the delay circuit receiving the edge-detected output, and each delay flip flop in the delay circuit producing a respectively delayed output; a first regeneration flip flop that is clocked by the asynchronous clock signal, the first regeneration flip flop having an output that is a second synchronous clock signal; a second regeneration flip flop that is clocked by the asynchronous clock signal and receives an input that is the second synchronous clock signal; and a clock regeneration stage including a second and-gate, the clock regeneration stage receiving an input from a last flip flop in the delay circuit, and inputs that are inverted output signals from the first regeneration flip-flop and the second regeneration flip-flop, the output of the clock regeneration stage being an input to the first regeneration flip flop.