Patent ID: 7745325
Filing Date: 2010-06-29
Classification: H01L

Abstract:
1. A method of forming a wiring structure of a semiconductor device, comprising: forming a preliminary insulation interlayer on a substrate; forming a mask pattern on the preliminary insulation interlayer, forming the mask pattern includes: anisotropically etching the preliminary insulation interlayer using the mask pattern as an etching mask to form a preliminary first trench; isotropically etching, with the mask pattern remaining on the preliminary insulation interlayer, the preliminary insulation interlayer exposed through the preliminary first trench to form a linear first trench having a first width; anisotropically etching the preliminary insulation interlayer exposed through the linear first trench using the mask pattern as an etching mask to form a linear second trench having a second width, the first width being wider than the second width; and filling the linear first and second trenches with a conductive layer pattern.