Patent ID: 7977201
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a first interconnect level structure including a first dielectric layer and a first metal line embedded therein; after forming said first dielectric layer and said first metal line, forming a second interconnect level structure including a second dielectric layer and at least one second metal line embedded therein directly on said first interconnect level structure; and after forming said second dielectric layer and said at least one second metal line, forming a doped semiconductor structure by depositing and patterning a semiconductor material directly on said at least one second metal line and said first metal line, wherein said patterned semiconductor material is in physical contact with said first metal line and said second metal line and is an elemental semiconductor material, a compound of at least two elemental semiconductor materials, a III-V compound semiconductor material, or a II-VI compound semiconductor material.