Patent ID: 8942217
Filing Date: 2015-01-27
Classification: H04L,Y02D

Abstract:
1. A system for hierarchical link aggregation, comprising a network interface device communicatively coupled to a processor, the network interface device having a plurality of physical ports comprising: a first plurality of the physical ports designated by the processor as member ports of a first link aggregation group (LAG), a first port of the first plurality of physical ports having a first transmission capacity and a second port of the first plurality of physical ports having a second transmission capacity; and a second plurality of the physical ports designated by the processor as member ports of a second LAG; wherein the first LAG and the second LAG are designated by the processor as member logical ports of a third LAG; wherein data communicated to the third LAG is distributed between the first LAG and the second LAG in accordance with a first hashing algorithm; wherein data communicated to the third LAG and distributed to the first LAG is distributed among the first plurality of ports in accordance with a second hashing algorithm; and wherein data communicated to the third LAG and distributed to the second LAG is distributed among the second plurality of ports in accordance with a third hashing algorithm, wherein the first hashing algorithm is different from the second hashing algorithm and the first hashing algorithm is different from the third hashing algorithm.