Patent ID: 8964556
Filing Date: 2015-02-24
Classification: H04L

Abstract:
1. An apparatus implemented in at least one of a memory or a processing device, comprising: a first flow control module configured to send a first flow control signal based on data flow within a first flow control loop including (1) a first stage of transmit queues fanning into a second stage of transmit queues, (2) the second stage of transmit queues fanning into a physical link, and (3) the physical link; and a second flow control module configured to define a second flow control signal based on data flow within a second flow control loop including (1) the second stage of transmit queues, and (2) the physical link, and excluding the first stage of transmit queues, the second flow control module configured to send the second flow control signal such that a transmit queue from the second stage of transmit queues suspends transmission in response to the second flow control signal.