Patent ID: 8971130
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix; word lines, including a first word line, a second word line and third word lines, connected to the memory cells, and the third word lines located between the first and second word lines; and a control circuit, wherein the memory cell array has blocks, each of the blocks has a NAND string which includes at least two select transistors and memory cells connected in series between the select transistors, the select transistors have gates connected to at least two select lines, the first word line is connected to at least one of the memory cells next to at least one of the select transistors in the NAND string, and the second word line is connected to at least another one of the memory cells next to at least another one of the select transistors in the NAND string, and wherein the control circuit erases one of the blocks in an erase operation, and the control circuit, in the erase operation, sets a first voltage to the first word line, sets a second voltage to the second word line, and sets a third voltage less than the first and second voltages to the third word lines.