Patent ID: 7057915
Filing Date: 2006-06-06
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array which comprises a plurality of blocks in each of which a plurality of nonvolatile memory cells capable of electrically rewriting data are arranged in an array; a first selection circuit configured to select the block; a plurality of word lines which are arranged in each block and each of which is commonly connected to memory cells of the same row; a second selection circuit configured to select several memory cells in the block to erase the memory cells corresponding to a plurality of word lines in the block; a plurality of driving lines each of which is arranged for a corresponding one of said plurality of word lines and supplies a voltage to the corresponding word line; and a plurality of transfer transistors which act as switches that selectively connect, of said plurality of word lines and said plurality of driving lines, word lines and corresponding driving lines for each block, when said plurality of word lines are divided into word lines connected to memory cells to be erased and those connected to memory cells not to be erased, said plurality of transfer transistors being laid out so that the number of transfer transistors connected to the word lines connected to the memory cells to be erased and arranged on both and opposite sides of a transfer transistor of a word line connected to a memory cell not to be erased becomes not more than two.