Patent ID: 8963229
Filing Date: 2015-02-24
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device including: a plurality of memory cell column wirings to which a charge accumulating voltage or a charge accumulating prevention voltage is applied; and a plurality of memory cell transistors having an N-channel type structure and disposed in a row and column matrix with respect to the plurality of memory cell column wirings and a plurality of word lines, the non-volatile semiconductor memory device causing a selected memory cell transistor in the plurality of memory cell transistors to accumulate electric charges based on a voltage difference between the charge accumulating voltage and a voltage to be applied to the word lines, the non-volatile semiconductor memory device comprising: a plurality of first semiconductor switches formed by PMOS transistors, the first semiconductor switches being provided for the respective memory cell column wirings; and a plurality of second semiconductor switches formed by NMOS transistors, the second semiconductor switches being provided for the respective memory cell column wirings, wherein, in a non-selected memory cell column wiring in which only non-selected memory cell transistors except for the selected memory transistor are disposed, the first semiconductor switches are configured to be switched on by means of a first gate voltage and to apply the charge accumulating prevention voltage to the non-selected memory cell transistors whereas, in a selected memory cell column wiring in which the selected memory cell transistor is disposed, the second semiconductor switches are configured to be switched on by means of a second gate voltage and to apply the charge accumulating voltage to the selected memory cell transistor.