Patent ID: 6140684
Filing Date: 2000-10-31
Classification: H01L,Y10S

Abstract:
A static random access memory (SRAM) semiconductor device structure, said structure comprising:a semiconductor substrate having field isolation regions formed within an active well region of a first conductivity type;a first transistor gate stack, the first transistor gate stack including a first gate oxide layer disposed over a first portion of the semiconductor substrate, and a first polysilicon layer disposed over the first gate oxide layer, the first transistor gate stack being patterned and etched wherein the first polysilicon layer forms a gate electrode for a first bulk pull-down transistor of a second conductivity type formed in the semiconductor substrate, and the first bulk pull-down transistor comprising a pull-down transistor of an SRAM cell;dielectric sidewall spacers disposed about side edges of the first transistor gate stack and in contact therewith;diffusion regions of the second conductivity type in the semiconductor substrate relative to the first transistor gate stack so as to form source and drain regions of the first bulk pull-down transistor;a second gate oxide layer formed over the drain region of the first bulk pull-down transistor, the dielectric sidewall spacers and the first transistor gate stack; anda second polysilicon layer formed over the second gate oxide layer, in contact with the second gate oxide layer covering a side of one of the dielectric sidewall spacers and extending along a side of the first transistor gate stack, the second polysilicon layer, the drain region of the first bulk pull-down transistor and the second gate oxide layer forming a channel region, gate region and gate oxide, respectively, of a first thin-film pull-up transistor of the SRAM cell.