Patent ID: 6317371
Filing Date: 2001-11-13
Classification: G11C

Abstract:
A storage device comprising:a system interface unit carrying out interface with a host system via an external bus;a controller coupled with said system interface unit analyzing commands received by said system interface unit from said host system and controlling operations to be performed within said storage device;a non-volatile semiconductor memory coupled with said controller;an error correction unit, coupled with said non-volatile semiconductor memory, performing error detection and error correction for data stored in said non-volatile semiconductor memory; andtwo memories coupled between said system interface and said non-volatile semiconductor memory,wherein said non-volatile semiconductor memory is electrically erasable and electrically programmable and stores data from said host system via said system interface unit,wherein, in response to a read command, received by said system interface unit, for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, said controller carries out selective read operations of blocks of data to said two memories from said non-volatile semiconductor memory and carries out parallel operations of data transferring a first block of data, which has already been subjected to the error detection and error correction operation by said error correction unit, from one of said two memories to said host system via said system interface unit and of data transferring of a second block of data, to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of said two memories.