Patent ID: 6738303
Filing Date: 2004-05-18
Classification: G11C

Abstract:
A memory device comprising:a plurality of memory cells; a bit line, the plurality of memory cells coupled to the bit line, wherein the bit line is configured to provide a voltage level during a read operation of a selected memory cell of the plurality of memory cells, wherein at the beginning of the read operation, the voltage level of the bit line is at a first voltage level and transitions towards a second voltage level at a rate dependent upon a resistance of the selected memory cell; a reference circuit configured to provide a voltage level during a read operation, wherein at the beginning of the read operation, the voltage level of the reference circuit is the first voltage level and transitions towards approximately the second voltage level at a reference rate; a sense amplifier coupled to the bit line and to the reference circuit, wherein during a read operation, the sense amplifier provides an indication of a comparison of the voltage level of the bit line and the voltage level of the reference circuit.