Patent ID: 7207019
Filing Date: 2007-04-17
Classification: G01R

Abstract:
1. A test circuit inserting method for a semiconductor integrated circuit, comprising the steps of: inputting circuit information; calculating controllability probabilities on a basis of the circuit information; performing initial layout on the basis of the circuit information; extracting interconnection pairs from a result of the initial layout; extracting test point insertion candidates on a basis of the controllability probabilities and the interconnection pairs; judging whether the test point insertion candidates exist; selecting test point insertion positions if the test point insertion candidates exist; selecting circuit structures of test points to be inserted at the test point insertion positions; virtually inserting the test points having the selected circuit structures; performing re-layout on a circuit in which the test points have been inserted virtually; judging whether circuit overhead of a result of the re-layout is within a prescribed range; and reducing a number of test points if the circuit overhead exceeds the prescribed range.