Patent ID: 8754683
Filing Date: 2014-06-17
Classification: G11C,H03L

Abstract:
1. An apparatus comprising: a variable delay line; a delay control module coupled to the variable delay line to select an amount of delay to be provided by the variable delay line; a primary phase detector coupled to the delay control module to compare an edge position associated with a variable delay line input clock signal with an edge position associated with a delayed version of a clock signal fed back to the primary phase detector from an output of the variable delay line and to provide at least one phase difference signal to the delay control module, the phase difference signal to cause the delay control module to select the amount of delay such that a selected phase relationship is maintained between the variable delay line input clock signal and the clock signal fed back to the primary phase detector from the output of the variable delay line, the variable delay line, the delay control module, and the primary phase detector to interoperate as a delay locked loop (DLL); and a quiescence control module communicatively coupled to at least one of the variable delay line input clock signal input to the primary phase detector, the clock signal fed back to the primary phase detector from the output of the variable delay line input to the primary phase detector, or a delay control module output, the quiescence control module to break all feedback loops associated with the DLL to prevent all updates to the variable delay line using the clock signal from the output of the variable delay line.