Patent ID: 6917077
Filing Date: 2005-07-12
Classification: H01L,Y10S

Abstract:
1. A semiconductor arrangement comprising: a substrate having a substrate layer with an upper surface and a lower surface, the substrate layer being of a first conductivity type; a first burled layer in the substrate, extending along said lower surface below a first portion of said upper surface of said substrate layer, and a second burled layer in the substrate, extending along said lower surface below a second portion of said upper surface of said substrate layer; a first diffusion region in said first portion of said substrate layer, being of a second conductivity type opposite to said first conductivity type and having a greatest depth at a first point along a width of said first diffusion region and having a lesser depth at a second point along said width; a shallow region in said first portion of said substrate layer, being of said first conductivity type and being on top of said second point of said first diffusion region but not on top of said first point of said first diffusion region; a second diffusion region in said second portion of said substrate layer, being of said second conductivity type; a first polysilicon structure, of the second conductivity type in contact with the first diffusion region; a second polysilicon structure, of the first conductivity type, in contact with the shallow region; and a dielectric spacer disposed between the first and second polysilicon structures.