Patent ID: 6479887
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A circuit pattern tape for wafer-scale production of chip size semiconductor packages, comprising:a plurality of individual, interconnected circuit pattern units arranged in a two-dimensional array and separated from each other in said tape by singulation lines, each said circuit pattern unit comprising: a centrally located opening formation region; bond finger formation regions arranged in opposing relationship on opposite sides of said opening formation region; said opening formation region and said bond finger formation regions each being arranged such that they do not intersect any of said singulation lines; a plurality of conductive metal bond fingers arranged in each of said bond finger formation regions; a plurality of conductive metal solder ball lands arranged outside of said bond finger formation regions; a plurality of conductive metal traces electrically connecting each of said bond fingers to an associated one of said solder ball lands; and, an insulating solder mask formed over said circuit pattern unit and having openings therein respectively exposing said opening formation region, said bond finger formation regions, and said solder ball lands therethrough.