Patent ID: 8575020
Filing Date: 2013-11-05
Classification: G03F,H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps of: forming a dielectric layer over a substrate; defining areas for a plurality of parallel route tracks on a top surface of said dielectric layer, said plurality of parallel route tracks having a pitch distance; forming a first interconnect pattern creating a plurality of first exposed areas including a first lead pattern, wherein said first lead pattern is located in an instance of said plurality of parallel route tracks; performing a first trench etch process to form a plurality of first interconnect trenches in said plurality of first exposed areas; forming a second interconnect pattern creating a plurality of second exposed areas including a second lead pattern, wherein said second lead pattern is located in said instance of said plurality of parallel route tracks, wherein said second lead pattern is separated from said first lead pattern by a distance of one to one and one-half times a space between said first lead pattern and an adjacent lead pattern located in an adjacent instance of said plurality of parallel route tracks; wherein said first interconnect pattern and said second interconnect pattern are formed using two distinct photolithography processes having a dipole illumination source; performing a second trench etch process to form a plurality of second interconnect trenches in said plurality of second exposed areas; and forming metal interconnect lines in said first interconnect trenches and said second interconnect trenches.