Patent ID: 7696608
Filing Date: 2010-04-13
Classification: G03F,H01L

Abstract:
1. A semiconductor integrated circuit device comprising: grooves formed in a semiconductor substrate and defining a first dummy region, second dummy regions, third dummy regions and a fourth dummy region such that a width of the first dummy region is greater than a width of each of the second dummy regions, such that a width of the first dummy region is greater than a width of each of the third dummy region and such that a width of each of the fourth dummy region is greater than a width of the third dummy region; element isolation insulating films filled in the grooves such that the element isolation insulating films serve as an element isolation region; and a conductor pattern formed over the first dummy region and adapted to be used for optical pattern recognition; wherein the first dummy region is formed under the conductor pattern such that the grooves are not formed under the conductor pattern, wherein the first dummy region and the second dummy regions are formed at a scribing area, wherein the second dummy regions are spaced from one another by a predetermined spacing at the scribing area, wherein the third dummy regions and the fourth dummy regions and the dummy conductor patterns are formed at a product area, and wherein the third dummy regions are spaced from one another by a predetermined spacing at the product area.