Patent ID: 6681286
Filing Date: 2004-01-20
Classification: G06F,G11C,H05K

Abstract:
A control chipset having n dual-definition data pins for optimizing a circuit layout such that a jth data pin is defined to be an ath pin of a first data-pin sequence and a bth pin of a second data-pin sequence while a kth data pin is defined to be the bth pin of the first data-pin sequence and a cth pin of the second data-pin sequence, comprising:a first first-in first-out (FIFO) memory for temporarily holding an output data having at least n pin output terminals; a multiplexing device coupled to the first FIFO memory and the n data pins of the control chipset, wherein the multiplexing device includes n first type input terminals, n second type input terminals, n output terminals and a selection input terminal, and whether an xth output terminal of the n output terminals is coupled to an xth input terminal of the n first type input terminals or an xth input terminal of the n second type input terminals is determined by a signal at the selection input terminal, the xth output terminal is connected to an xth data pin of the data pins, a bth pin output terminal of the first FIFO memory is connected to a jth input terminal of the n second type input terminals of the multiplexing device and a kth input terminal of the n first type input terminals of the multiplexing device; a second first-in least n pin input terminals; and a de-multiplexing device coupled to the n data pins of the control chipset, wherein the de-multiplexing device has n first type output terminals, n second type output terminals, n input terminals and a selection input terminal, whether an xth input terminal of the n input terminals is coupled to an xth output terminal of the n first type output terminals or an xth output terminal of the n second type output terminals is determined by a signal at the selection input terminal of the de-multiplexing device, the xth input terminal is connected to an xth data pin of the data pins, and a bth pin input terminal of the second FIFO memory is connected to a jth output terminal of the n second type output terminals of the de-multiplexing device and a kth output terminal of the n first type output terminals of the de-multiplexing device; wherein n is an integral value greater than zero and defines a total number of the data pins, and a, b, c, j, k, x are integral value to indicate a specific pin in the data-pin sequences.