Patent ID: 7130989
Filing Date: 2006-10-31
Classification: G06F

Abstract:
1. A processor having a set of operations made up of all the operations that are executable by the processor, each of said operations being specified by an instruction received by the processor in one of first and second external instruction formats, F 1 and F 2 , and each of said external formats, F 1 and F 2 , having one or more opcode bits in which an opcode, specifying the operation to be executed, appears, and each of said opcode bits in one of said external formats, F 1 and F 2 , that has an individually corresponding opcode bit in the other one of said external formats, F 1 and F 2 , being a common F 1 –F 2 opcode bit in the format concerned so that each of said external formats, F 1 and F 2 , has, among its said one or more opcode bits, the same number C of common F 1 –F 2 opcode bits in total, where C≧1, the processor comprising: at least one execution unit which receives instructions in an internal instruction format and executes the operations specified thereby; and at least one instruction translation unit which employs the opcode bits to translate each instruction received in at least one of said external formats F wherein: all of the operations of said set of operations that are specifiable in said second external format F for every one of the operations of said set of operations that is specifiable both in said first and second external formats , all the mutually-corresponding common F