Patent ID: 6687782
Filing Date: 2004-02-03
Classification: G06F

Abstract:
In a data processing system comprising a processor having a total number of address output terminals and an address bus having a bit width corresponding to a finite address capacity, the bit width equal in number to the total number of processor address output terminals, the processor coupled to a Read Only Memory (ROM) via the address bus for output of bus addresses corresponding to ROM data storage locations, the ROM having a number of addresses greater than the finite address capacity of the address bus, the processor coupled to the ROM via a data bus for receiving from the ROM stored data identified by the ROM addresses, a method for expanding the number of accessible ROM addresses beyond the finite address bus capacity, said method comprising the steps of:allocating a first portion of the bus addresses as random reading mode bus addresses for randomly addressing the ROM for reading data, the random reading mode bus addresses having direct correspondence with ROM addresses; allocating a second portion of bus addresses as sequential reading mode bus addresses for addressing the ROM in sequential ROM address order for reading data; associating at least one of the sequential reading mode bus addresses with a plurality of sequentially numbered ROM addresses; and loading the first numbered address of the plurality of sequentially numbered ROM addresses as data into at least one counter; wherein processor output of the associated sequential reading mode address effectuates application of the contents of the counter as an address to the ROM and increments the counter.