Patent ID: 8828839
Filing Date: 2014-09-09
Classification: H01L,Y10S

Abstract:
1. A method of fabricating an electrically-isolated FinFET semiconductor device, the method comprising the steps of: forming a silicon oxide layer over a semiconductor substrate comprising a silicon material; forming a first hard mask layer over the silicon oxide layer; forming a plurality of sacrificial mandrels over the first hard mask layer; forming a plurality of sidewall spacers along the sides of the plurality of sacrificial mandrels; removing each of the plurality of sacrificial mandrels and portions of the first hard mask layer below the sacrificial mandrels, thereby forming a first plurality of void spaces between the sidewall spacers and remaining portions of the first hard mask layer; forming a second hard mask layer in the first plurality of void spaces; removing the sidewall spacers and the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer; extending the second plurality of void spaces into the silicon oxide layer; and forming a plurality of fin structures in the extended second plurality of void spaces, wherein each fin structure of the plurality of fin structures is electrically isolated by remaining portions of the silicon oxide layer.