Patent ID: 6380585
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions together; a channel region formed in the first surface region of the substrate; source and drain regions formed to interpose the channel region therebetween; a first insulating film formed on the surface of the substrate; and a floating gate formed on the first insulating film, wherein the drain region includes: a low-concentration impurity layer which is formed in the second surface region and which covers a corner portion between the second surface region and the step side region, said low-concentration impurity layer not reaching the first surface region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region, an impurity concentration of the low-concentration impurity layer being lower than that of the high-concentration impurity layer, and wherein the channel region includes a high-concentration impurity region being located close to the step side region and having an impurity concentration higher than that of the channel region in a part thereof adjacent to the source region, and said high-concentration impurity region does not cover the step side region and the corner portion between the second surface region and the step side region, and wherein the floating gate covers substantially all of the channel region, the step side region and at least a part of the low-concentration impurity layer via the first insulating film.