Patent ID: 9070782
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a substrate; a first buried gate disposed in said substrate; a second buried gate disposed in said substrate and adjacent to said first buried gate; a first source disposed between said first buried gate and said second buried gate; a first drain disposed at one side of said first buried gate; a second source disposed at one side of said second buried gate; an interlayer dielectric layer covering said first buried gate, said second buried gate and said substrate; and a core dual damascene plug comprising a first plug, a second plug and an insulating slot, wherein said insulating slot is disposed between said first plug and said second plug and is recessed into a top surface of said interlayer dielectric layer so that said first plug and said second plug are mutually electrically insulated, and said first plug and said second plug respectively penetrate said interlayer dielectric layer to be respectively electrically connected to said first source and to said second source.