Patent ID: 9087917
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: providing a substrate comprising a semiconductor; removing a first sacrificial gate and a first sacrificial gate dielectric layer disposed on said substrate to form a first gate cavity in an area for a first MOS transistor having a first polarity and a second sacrificial gate and a second sacrificial gate dielectric layer disposed on said substrate to form a second gate cavity in an area for a second MOS transistor having a second, opposite, polarity; forming a first liner of dielectric material over a protective dielectric layer adjacent to said first gate cavity and said second gate cavity, said first liner extending into said first gate cavity and said second gate cavity; forming a second liner of a different dielectric material on said first liner, said second liner extending into said first gate cavity and said second gate cavity; removing said second liner from bottoms of said first gate cavity and said second gate cavity, leaving said second liner on vertical surfaces of said first liner in said first gate cavity and said second gate cavity; removing said first liner from a top surface of said protective dielectric layer and from bottoms of said first gate cavity and said second gate cavity so as to expose said substrate; removing said second liner in said first gate cavity and said second gate cavity, leaving said first liner in place in said first gate cavity as a first L-shaped spacer and leaving said first liner in place in said second gate cavity as a second L-shaped spacer; forming a first permanent gate dielectric layer on said substrate and said first L-shaped spacer in said first gate cavity; forming a second permanent gate dielectric layer on said substrate and said second L-shaped spacer in said second gate cavity; forming a first replacement gate on said first permanent gate dielectric layer, said first permanent gate dielectric layer and said first replacement gate overlapping a portion of said first L-shaped spacer contacting said substrate; and forming a second replacement gate on said second permanent gate dielectric layer, said second permanent gate dielectric layer and second first replacement gate overlapping a portion of the second L-shaped spacer contacting said substrate.