Patent ID: 6034901
Filing Date: 2000-03-07
Classification: G11C

Abstract:
A memory system comprising:a plurality of memories;a controller for controlling said memories;a dummy memory having the same storage capacity as said memories with respect to an external clock signal output from said controller;a first line for equalizing a time by which the external clock signal is delayed while supplied from said controller to said memories to a time by which the external clock is delayed while supplied from said controller to said dummy memory;a data bus for supplying data from one of said memories to said controller in synchronism with an internal clock signal which has a specific phase relation with the external clock signal; anda second line for returning the external clock signal from said dummy memory to said controller as a return clock signal,wherein a time by which the data is delayed while supplied from one of said memories to said controller is equal to a time by which the return clock signal is delayed while supplied from said dummy memory to said controller, and said controller receives the data in synchronism with the return clock signal.