Patent ID: 6710991
Filing Date: 2004-03-23
Classification: H01L

Abstract:
An electrostatic-breakdown-preventive and protective circuit for a semiconductor-device, the circuit comprising:a first power-source line and a first ground line for supplying bias to a first internal block; a second power-source line and a second ground line for supplying bias to a second internal block; a third power-source line and a third ground line for supplying bias to an input/output circuit portion; at least one of a first protective transistor provided between the first power-source line and the second power-source line and a second protective transistor provided between the first ground line and the second ground line; third protective transistors respectively disposed at at least two of a position between the first power-source line and the third power-source line, a position between the first ground line and the third ground line, a position between the first power-source line and the third ground line, and a position between the first ground line and the third power-source line; fourth protective transistors disposed at at least two of a position between the second power-source line and the third power-source line, a position between the second ground line and the third ground line, a position between the second power-source line and the third ground line, and a position between the second ground line and the third power-source line; and a connection line for transferring an output signal of the first internal block as an input signal of the second internal block, wherein at least one of the first protective transistor and the second protective transistor is disposed in the vicinity of the connection line.