Patent ID: 6751152
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A memory array comprising:a plurality of memory cells, each memory cell comprising a data storage element and a switching transistor having a threshold voltage Vth, wherein the data storage element is a capacitor and stores either a nearly full first voltage of a data 0 or an insufficient second voltage of a data 1; means for reading the nearly full first voltage of a data 0 through the switching transistor to a bitline while limiting reading the insufficient second voltage of a data 1 by utilizing the threshold voltage Vth of the switching transistor, wherein the switching transistor has a gate connected to a wordline, a drain connected to the bitline, and a source connected to the data storage element, and has the threshold voltage Vth in a read mode, the storage element couples to the bitline through the switching transistor when the wordline goes high, the bitline is precharged to a voltage supply VDD, a wordline boosted voltage is Vpp, wherein the Vpp voltage in a read mode is equal to or smaller than a physical 1 voltage (Vcell-high) written to the memory cell plus the threshold voltage Vth (Vpp=