Patent ID: 6429711
Filing Date: 2002-08-06
Classification: H03K

Abstract:
A circuit comprising:a data signal input to receive a data signal; a clocking circuit to generate control clocks; a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output; at least one stack node pre-charging transistor coupled to a high signal transfer node in the multiple input conditional inverter; at least one stack node pre-discharging transistor coupled to a low signal transfer node in the multiple input conditional inverter; a keeper circuit to receive the output of the multiple input conditional inverter; and a buffer circuit to receive the output of the multiple input conditional inverter and to generate a flip-flop circuit output; wherein the at least one stack node pre-charging transistor comprises a first pre-charging PMOS transistor including a gate, a source and a drain, and a second pre-charging PMOS transistor including a gate, a source and a drain, the source of the first pre-charging PMOS transistor being coupled to a positive supply voltage, the drain of the first pre-charging PMOS transistor being coupled to the source of the second pre-charging PMOS transistor, the drain of the second pre-charging PMOS transistor being coupled to the high signal transfer node.