Patent ID: 9218030
Filing Date: 2015-12-22
Classification: G06F

Abstract:
1. A programming interface, comprising: a system clock input, an interface data bus input, an interface data bus output, an asynchronous reset input and an interface control input; a destination register with a destination register clock input coupled to the system clock input, a destination register data input and a destination register data output; a buffer register with a buffer register clock input coupled to the system clock input, a buffer register data input and a buffer register data output coupled to the interface data bus output; a buffer multiplexer with a buffer multiplexer control input, a buffer multiplexer output coupled to the buffer register data input, a buffer multiplexer first input coupled to the buffer register data output and a buffer multiplexer second input coupled to the destination register data output, wherein the buffer multiplexer couples the buffer multiplexer second input to the buffer multiplexer output when a write signal pulse is applied to the buffer multiplexer control input, otherwise the buffer multiplexer couples the buffer multiplexer first input to the buffer multiplexer output; a tertiary multiplexer with a tertiary multiplexer control input, a tertiary multiplexer output, a tertiary multiplexer first input coupled to the destination register data output and a tertiary multiplexer second input coupled to the buffer register data output; a destination multiplexer with a destination multiplexer control input coupled to the interface control input, a destination multiplexer output coupled to the destination register data input, a destination multiplexer first input coupled to the tertiary multiplexer output and a destination multiplexer second input coupled to the interface data bus input; and a pulse delay module with a pulse delay module clock input coupled to the system clock input, a pulse delay module output coupled to the buffer multiplexer control input and a pulse delay module data input coupled to the interface control input, wherein in operation when an asynchronous register reset signal is applied to the asynchronous reset input the write signal pulse supplied at the interface control input is blocked from being provided at the pulse delay module output.