Patent ID: 8373637
Filing Date: 2013-02-12
Classification: G09G,G11C

Abstract:
1. A shift register for providing a plurality of shift register signals, the shift register comprising: a plurality of shift register units, each shift register unit being provided with one of a first clock signal and a second clock signal, a high-level voltage, and a low-level voltage, each two adjacent shift register units receiving the first and second clock signal respectively, each shift register unit comprising: wherein when the clock unit is switched on, the signal outputting circuit outputs the shift register signal; wherein when the clock unit is switched off, the level unit is switched on by the second inversion circuit and the signal outputting circuit outputs a low-level signal wherein the signal inputting circuit, the first inversion circuit, and the signal outputting circuit are connected to a first common node which is connected to the clock unit, and the second inversion circuit, the third inversion circuit and the signal outputting circuit are connected to a second common node which is connected to the level unit; wherein the signal inputting circuit comprises a first transistor and a second transistor, a gate of the first transistor being applied with the shift register signal of the previous adjacent one of the shift register units, a source of the first transistor being applied with the high-level voltage from the external circuit, a drain of the first transistor being connected a source of the second transistor and further connected to the first common node, a gate of the second transistor being applied with the shift register signal of the next adjacent one of the shift register units, a drain of the second transistor being applied with the low-level voltage, except in the case of the shift register unit being a first one of the shift register units wherein in such case the gate of the first transistor is coupled to the corresponding external circuit; wherein the first inversion circuit comprises a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, a gate of the third transistor being applied with one of the first and second clock signals, a source of the third transistor being connected to a drain of the fourth transistor, a drain of the third transistor being applied with the high-level voltage, a gate of the fourth transistor being connected to the first common node, a source being applied with the low-level voltage, the drain of the fourth transistor being further connected to a gate of the fifth transistor, a source of the fifth transistor being connected to a drain of the sixth transistor, a drain of the fifth transistor being applied with high-level voltage, a gate of the sixth transistor being connected to the gate of the fourth transistor, and a source of the sixth transistor being applied with the low-level voltage.