Patent ID: 6974757
Filing Date: 2005-12-13
Classification: H01L

Abstract:
1. A method of forming silicon-on-insulator comprising integrated circuitry, comprising: forming a silicon-comprising layer of the silicon-on-insulator circuitry; forming an insulator layer of the silicon-on-insulator circuitry, the insulator layer being formed to comprise: forming a pair of source/drain regions in the silicon-comprising layer, each of the source/drain regions extending to the insulator layer; forming a channel region in the silicon-comprising layer which is received intermediate the source/drain regions, the channel region extending less than completely through a thickness of the silicon-comprising layer, the silicon nitride-comprising region running along only a portion of the channel region and the first silicon dioxide-comprising running along at least a portion of the channel region; and forming a transistor gate operably proximate the channel region.