Patent ID: 6289438
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A microprocessor integrated circuit chip, comprising:a processor;a cache memory having a plurality of valid cache memory locations and at least one defective cache memory location;a store buffer having buffer entries and redundancy entries for storing data sent by the processor for storage in the cache memory;a tag RAM having buffer tag entries for storing addresses of data stored in the buffer entries and redundancy tag entries for storing addresses of defective cache memory locations in the cache memory; anda comparator for comparing addresses of data sent by the processor for cache memory storage with addresses stored in the redundancy tag entries;wherein, for each data sent by the processor for cache memory storage, if the data address matches an address stored in one of the redundancy tag entries, then the store buffer stores that data in the corresponding redundancy entry, otherwise the store buffer stores that data in one of the buffer entries; andwherein the store buffer sends data stored in the buffer entries to the cache memory for storage in the valid cache memory locations.