Patent ID: 6724225
Filing Date: 2004-04-20
Classification: H03K

Abstract:
A MOSFET true and complement signal generating logic circuit receiving two input signals comprising a first and second input signal and outputting a true signal and a complement signal indicative of the first input signal to the true and complement signal generating logic circuit, comprising:at least one inverter logic circuit; and first and second MOSFET AND logic circuits; each of the first and second AND logic circuits including three transistors wherein the three transistors receive at least two AND input signals, and output a usable output signal indicative of an AND operation performed on a first and second AND input signal of the at least two AND input signals, wherein the at least two AND input signals to the first and second AND logic circuits include first and second AND input signals and a complement of the second AND input signal, the first AND input signal is provided to a source of first and second transistors of the three transistors, the second AND input signal is provided to a gate of the first transistor, and the complement of the second AND input signal is provided to a gate of the second transistor, wherein for the first AND logic circuit, the first AND input signal is the first input signal to the true and complement signal generating logic circuit after passing through first and second inverter logic circuits of the at least one inverter logic circuit; and wherein for the second AND logic circuit, the first AND input signal is the first input signal to the true and complement signal generating logic circuit after passing through the first and second inverter logic circuits and a third inverter logic circuit of the at least one inverter logic circuit, and wherein for the first and second AND logic circuits, the second AND input signal is the second input signal to the true and complement signal generating logic circuit, and the complement of the second AND input signal is the second input signal to the true and complement signal generating logic circuit after passing through a fourth inverter logic circuit of the at least one inverter logic circuit.