Patent ID: 6262695
Filing Date: 2001-07-17
Classification: G09G

Abstract:
An apparatus for phase-locking a plurality of display devices, each of the display devices displaying an image under the control of a distinct clock having a distinct clock rate, each of the images containing a predetermined periodic indexing event, the apparatus comprising:a designation circuit to receive each of the distinct clocks and to designate one of the distinct clocks to be a master clock and the remaining clocks to be slave clocks;a synchronization circuit to synchronize the distinct clocks, the synchronization circuit including:a clock rate comparison circuit to compare the clock rates of all of the distinct clocks and to determine the greatest difference between the rates of all of the distinct clocks,a control circuit to receive said greatest difference and to cause said greatest difference to be within a predetermined difference rate of one another, anda rate difference circuit to cause said predetermined difference rate to be reduced to zero;a times-of-occurrence comparison circuit to receive the times of occurrence of the indexing events for the images displayed under the control of the master clock and the slave clocks, to compare the times of occurrence of the indexing event for the image displayed under the control of the master clock to the times of occurrence of the indexing events for the images displayed under the control of the slave clocks, and to produce signals indicative of the differences between the time of occurrence of the indexing event for the image displayed under the control of the master clock and the times of occurrence of the indexing events for the images displayed under the control of the slave clocks;a reset circuit to receive the signals indicative of said differences, to compare the signals indicative of said differences, and, if any one of said differences exceeds a predetermined amount of time, to cause said corresponding time of occurrence of said slave clock to occur within the predetermined amount of time of the time of occurrence of the master clock; anda repetition circuit to iteratively cause the times-of-occurrence comparison circuit and the reset circuit to operate until the slave clocks are phase-locked.