Patent ID: 7351597
Filing Date: 2008-04-01
Classification: G01R,Y10T

Abstract:
1. A fabrication method of a semiconductor integrated circuit device, comprising the steps of: (a) providing a semiconductor wafer which has been divided into a plurality of chip regions, each having a semiconductor integrated circuit formed thereover, and has, formed over a main surface thereof, a plurality of first electrodes to be electrically connected with the semiconductor integrated circuit; (b) providing a first card for retaining a first sheet, which has a plurality of contact terminals to be brought into contact with the first electrodes and interconnects to be electrically connected with the contact terminals, so as to cause tip portions of the contact terminals to protrude toward the main surface of the semiconductor wafer; and (c) bringing the contact terminals into contact with the first electrodes to perform an electrical test of the semiconductor integrated circuit device, wherein the tip portions of the contact terminals are disposed over a first surface of the first sheet, and a plurality of second electrodes to be electrically connected with the interconnects are disposed over a second surface which is opposite to the first surface of the first sheet, wherein the first card has a plurality of connection mechanisms to be electrically connected to the second electrodes, wherein the connection mechanisms each comprises: an elastic contact needle for pushing the second electrodes by a load generated upon contact of the contact terminals with the first electrodes; and a retainer member for retaining the contact needle and is disposed to get in touch with the second electrodes over the second surface of the first sheet, and wherein the probe needle pushes the second electrodes before the contact terminals are brought into contact with the first electrodes.