Patent ID: 7817492
Filing Date: 2010-10-19
Classification: G11C

Abstract:
1. A memory circuit, comprising: first and second flip-flop circuits which are connected in parallel between a common write word line and each of first and second read bit lines; a first write control circuit which is connected to said first flip-flop circuit, to be conducted by a write control signal supplied to said common write word line, and supplies to a first write signal to said first flip-flop circuit; and a second write control circuit which is connected to said second flip-flop circuit to be conducted by the write control signal supplied to said common write word line, and to supply a second write signal to said second flip-flop circuit; a first read control circuit which is connected to said first flip-flop circuit to be conducted by a first read control signal supplied to a first read word line, and to read out a read signal to one of first and second read bit lines from said first flip-flop circuit; and a second read control circuit which is connected to said second flip-flop circuit to be conducted by a second read control signal supplied to a second read word line, and to read out a read signal to another one of first and second bit lines from said second flip-flop circuit, wherein the first and second write signals are set, respectively, in the first and second flip-flop circuits at a same time via the common write word line, and the first and second read control circuits supply said first and second read control signals, respectively, to said first and second flip-flop circuits via said first and second read word lines, to readout data from said first and second read bit lines.