Patent ID: 6351570
Filing Date: 2002-02-26
Classification: G06T

Abstract:
An image decoding apparatus which generates a decoded image from a code sequence and comprises a bus, a computer, and a memory, wherein the computer and the memory are connected to each other via the bus, and the code sequence is generated by performing orthogonal transform, quantization, and entropy coding on image data and is stored in the memory, the apparatus comprising:an entropy decoding means, achieved by the computer, for reading one code out of the code sequence, which is stored in the memory, via the bus and performing entropy decoding on the read code to generate a decode value, wherein each decode value is composed of a run length and a non-zero coefficient value, a coefficient generating means, achieved by the computer, for generating at least one orthogonal transform coefficient according to the generated decode value, wherein the coefficient generating means comprises: a zero run generating means for generating a zero run composed of as many bits 0 as specified by a run length of the generated decode value; and a sub-coefficient generating means for generating zero orthogonal transform coefficients according to the generated zero run and generating a non-zero orthogonal transform coefficient by performing dequantization on the non-zero coefficient value of the generated decode value; a writing means, achieved by the computer, for writing the generated at least one orthogonal transform coefficient into the memory via the bus; and a decode controlling means, achieved by the computer, for, after processes of the coefficient generating means and the writing means, instructing the entropy decoding means to process a next code out of the code sequence each code is a bit sequence, the entropy decoding means comprises: a table means storing a primary decoding table and a secondary decoding table, wherein the secondary decoding table stores decode values, and the primary decoding table stores a plurality of sets which are each composed of an evaluation bit pattern length, a limitation value, and a first group address, wherein the evaluation bit pattern length is the number of bits included in an evaluation bit pattern, the evaluation bit pattern is a bit sequence following a different sign bit when a code including the bit sequence is the longest in a code group of a same run length, and the evaluation bit pattern is formed by adding at least one bit to end of a bit sequence following a different sign bit when a code including the bit sequence is shorter than the longest code in a code group of a same length so that the code has a same length as the longest code, the limitation value is either of a maximum value and a minimum value among evaluation bit patterns related to a code group of a same run length and a same code length, and the first group address is related to an address specifying a decode value in the secondary decoding table; a run length detecting means for obtaining a run length of a run which starts from a predetermined position in the code sequence, wherein the predetermined position is called a first bit position; an adding means for adding a constant 1 to the obtained run length to obtain an addition result; a first address determining means for determining a first address using the obtained run length; a first searching means for searching the primary decoding table using the determined first address to obtain an evaluation bit pattern length, a limitation value, and a first group address; a fetching means for fetching a bit sequence as long as the obtained evaluation bit pattern length from the code sequence, the bit sequence starting from a second bit position which is located the obtained addition result from the first bit position; a comparison means for comparing the obtained limitation value with the fetched bit sequence to select either of the primary decoding table and the secondary decoding table; a second searching means for searching the secondary decoding table to obtain a decode value using an address obtained by adding the obtained first group address to the fetched bit sequence; a first address renewing means for adding â€œbit sequenceâ€  to the determined first address; a search controlling means for instructing the second searching means to search the secondary decoding table to obtain the decode value when the comparison means selects the secondary decoding table, and for instructing the first address renewing means, the first searching means, the adding means, the fetching means, and the comparison means to repeat processes until a decode value is obtained from the secondary decoding table when the comparison means selects the primary decoding table.