Patent ID: 9058991
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a substrate, a first well of a first polarity formed in said substrate, a second well of a second polarity different from said first polarity formed within said first well, a voltage terminal formed within the second well, a third well of the second polarity formed within said first well, a protected terminal formed within the third well, a fourth well of the first polarity formed within said second well, a fifth well of the second polarity formed within said third well, and an electric coupling between said fourth well, said fifth well and said first well, wherein a parasitic transistor is formed by the fourth well, the second well and the first well, and the electric coupling biases the first well by said fourth well and said fifth well to prevent the parasitic transistor from conducting on failure of the supply voltage at the voltage terminal.