Patent ID: 6321302
Filing Date: 2001-11-20
Classification: G06F

Abstract:
A system for temporarily storing a block of non cacheable data, comprising:a CPU core;a local bus interface unit coupled between said CPU core and a system bus;a memory device coupled to said system bus, said memory device including addresses which contain non-cacheable data;wherein said local bus interface unit includes:state logic coupled to received control signals produced by the CPU core and indicative of a non-cacheable read cycle directed to a target address within the memory device, wherein the state logic is configured to produce a LOAD signal in response to the control signals;a stream read buffer for temporary storage of non-cacheable data, wherein the stream read buffer is coupled to receive the LOAD signal and configured to respond to the LOAD signal by loading the block of non-cacheable data from the target address via the system bus; andcomparator logic for determining whether an address of a current transaction is targeted to an address which is to be loaded in the stream read buffer; andan instruction counter for counting a number of instructions which have been executed since a previous cycle to the stream read buffer, and wherein the data is flushed from the stream read buffer the count in said instruction counter exceeds a predetermined value.