Patent ID: 6812764
Filing Date: 2004-11-02
Classification: G11C,H03K

Abstract:
A timing circuit for semiconductor device comprising:a signal delay unit for delaying an externally received signal for a delay time and outputting a delayed signal, the signal delay unit comprising: a first delay means having a first delay input and a first delay output; a second delay means having a second delay input connected to the first delay output and a second delay output; a third delay means having a third delay input connected to the second delay output and a third delay output; and a first fuse circuit having a first fuse and being capable of receiving a first enabling signal and, when the first fuse circuit is enabled and the first fuse is cut, being capable of controlling the delay time of the signal delay unit, wherein the first fuse circuit comprises: a first node; a first PMOS transistor having a first source terminal, a first drain terminal, and a first gate terminal, wherein a source voltage VDD is applied to the first source terminal, a signal for a fuse program is applied to the first gate terminal, and the first drain terminal is connected to the first node; the first fuse having a first fuse end connected to the first node and the second fuse end connected to an electrical ground; and a second PMOS transistor having a second source terminal, a second drain terminal, and a second gate terminal, wherein the second drain terminal is connected to the first node and the second source terminal is connected to the source voltage VDD; a first inverter having a first input terminal and a first output terminal; and a second inverter having a second input terminal and a second output terminal, wherein the first input terminal is connected to the first node, wherein the first output terminal is connected to the second input terminal, wherein the first output terminal is also connected to the second gate terminal, and wherein the second output terminal outputs a first fuse circuit output signal for determining the delay time; a second fuse circuit having a second fuse and being capable of receiving a second enabling signal and, when the second fuse circuit is enabled and the second fuse is cut, being capable of controlling the delay time of the signal delay unit, wherein the second fuse circuit comprises: a second node; a third PMOS transistor having a third source terminal, a third drain terminal, and a third gate terminal, wherein a source voltage VDD is applied to the third source terminal, a signal for a fuse program is applied to the third gate terminal, and the third drain terminal is connected to the second node; the second fuse having a third fuse end connected to the second node and the fourth fuse end connected to an electrical ground; and a fourth PMOS transistor having a fourth source terminal, a fourth drain terminal, and a fourth gate terminal, wherein the fourth drain terminal is connected to the second node and the fourth source terminal is connected to the source voltage VDD; a third inverter having a third input terminal and a third output terminal; and a fourth inverter having a fourth input terminal and a fourth output terminal, wherein the third input terminal is connected to the second node, wherein the third output terminal is connected to the fourth input terminal, wherein the third output terminal is also connected to the fourth gate terminal, and wherein the fourth output terminal outputs a second fuse circuit output signal for determining the delay time; and a signal transmission unit comprising: an INV1 inverter having an input to receive the first fuse circuit output signal; a NAND1 nand gate for receiving the second delay output and the output signal of the INV1 inverter; an INV2 inverter having an input to receive the output signal of the NAND1 nand gate; a NAND2 nand gate for receiving the signal from the third delay means output and the second fuse circuit output signal; an INV3 inverter for receiving the output of the NAND2 nand gate; a NOR1 nor gate for receiving the outputs of the INV2 inverter and the INV3 inverter; an INV4 inverter for receiving the output of NOR1 nor gate; a NOR2 nor gate for receiving the output signal of the INV4 inverter and the first delay means output signal; an INV5 inverter for receiving the output of the NOR2 nor gate; and a NOR3 nor gate for receiving the externally received signal and the output signal of INV5 inverter; and outputting the delayed signal.