Patent ID: 7795094
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A method of fabricating an antifuse structure, comprising: forming a recess extending into semiconductor material of a semiconductor substrate, the recess having a curvilinear bottom periphery; the semiconductor substrate having an uppermost surface, and after the recess is formed a first region of the uppermost surface being within the recess, and a second region of the uppermost surface being outside of the recess and elevationally above the first region of the uppermost surface; the recess having a width, and having opposing lateral edges on either side of said width; oxidizing the first region of said uppermost surface to line the recess with a first dielectric layer, the first dielectric layer being entirely along the first region of said uppermost surface, and only partially along the second region of said uppermost surface; the first dielectric layer along the second region of said uppermost surface extending to first lateral distances beyond the lateral edges of the recess; forming a second dielectric layer over the first dielectric layer, the second dielectric layer being entirely along the first and second regions of the semiconductor substrate; the first and second dielectric layers within the recess together forming a recess lining along the curvilinear bottom periphery; forming electrically conductive gate material over the recess lining and within the recess to fill the recess; the electrically conductive gate material being patterned to form a gate having a pair of opposing sidewalls; said sidewalls being over the second region of said uppermost surface; forming sidewall spacers along the gate sidewalls, the sidewall spacers extending laterally outward beyond the first lateral distances of the first dielectric layer; forming heavily doped source/drain regions extending into the semiconductor material of the semiconductor substrate; said heavily doped source/drain regions being laterally outward of the sidewall spacers, and being laterally outward of the first lateral distances of the first dielectric layer; forming lightly doped source/drain regions under the sidewall spacers, and under both of the first and second dielectric layers; forming a first electrically conductive contact to the gate, a second electrically conductive contact to one of the source/drain regions, and a third electrically conductive contact to the other of the source/drain regions; and using at least two of the contacts to provide a voltage differential between the gate and one of the source/drain regions and to thereby form an electrically conductive filament from the gate to one of the lightly doped source/drain regions.