Patent ID: 6424025
Filing Date: 2002-07-23
Classification: H01L

Abstract:
An interlace grid array package structure comprising:a lead frame having a central die paddle and a plurality of leads spaced around the die paddle, wherein the lead frame has a first side and a second side; a wafer chip attached to the die paddle on the first side of the lead frame, wherein the wafer chip is electrically connected to the lead frame; a package material for enclosing the wafer chip and the lead frame on the first side; and a interlace grid array tape attached to the second side of the lead frame, wherein the interlace grid array tape has a plurality of holes arranged alternately into a grid array, and the holes of the interlace grid array tape match in positions to the respective leads of the lead frame, so that the leads are partially exposed through the holes of the cross grid array tape.