Patent ID: 6859083
Filing Date: 2005-02-22
Classification: H03L

Abstract:
1. For use with an operational circuit comprising at least one high-impedance node, a pull-down circuit capable of pulling said high-impedance node down to ground when a pull-down (PD) signal driving said pull-down circuit is Logic 1, said pull-down circuit comprising: a first pull-down N-channel transistor having a drain coupled to said high-impedance node, a gate coupled to said PD signal, and a source coupled to a common node; a second pull-down N-channel transistor having a drain coupled to said common node, a gate coupled to said PD signal, and a source coupled to a ground rail;, wherein said first and second pull-down N-channel transistors are off when said PD signal is Logic 0 and are on when said PD signal is Logic 1; and a gate-biasing circuit driven by said PD signal, wherein said gate-biasing circuit is off when said PD signal is Logic 1 and said gate-biasing circuit applies a Logic 1 bias voltage to said common node when said PD signal is Logic 0, said Logic 1 bias voltage creating a negative Vgs bias on said first pull-down N-channel transistor when said PD signal is Logic 0.