Patent ID: 6441646
Filing Date: 2002-08-27
Classification: H03K

Abstract:
A SOI (silicon-on-insulator) circuit for reducing bipolar current comprising:a first input signal source; a first NFET device coupled to said first input signal source; a first PFET device coupled to said first input signal source; a second input signal source; a second NFET device coupled to said second input signal source; a second PFET device coupled to said second input signal source; a first NFET stack node coupled to said first PFET device, said first NFET device, and said second NFET device; a third input signal source; a third NFET device coupled to said third input signal source; a third PFET device coupled to said second PFET device; a power supply voltage source coupled to said third PFET device; and a second NFET stack node coupled to said second PFET device, said second NFET device, and said third NFET device.