Patent ID: 7277808
Filing Date: 2007-10-02
Classification: G06F

Abstract:
1. An integrated circuit comprising: an input terminal for receiving an input signal; an input register having an input connected to said input terminal, a clock input and an output supplying input data to said integrated circuit, said input register sampling and storing data received at said input upon receipt of a clock pulse at said clock input; a clock distribution spine for distribution of a clock signal, said clock signal having repetitive clock pulses; a write once memory having a at least one input delay bit, each input delay bit having an unprogrammed digital state and capable of being changed once to a programmed digital state; and an input clock delay element having an input receiving said clock signal from said clock distribution spine, a control input receiving said at least one input delay bit and an output connected to said clock input of said input register, said input clock delay element delaying said clock signal an amount corresponding to said digital state of said at least one input delay bit.