Patent ID: 6294448
Filing Date: 2001-09-25
Classification: H01L

Abstract:
A method for manufacturing salicided regions for electrical contact to a semiconductor device, comprising the sequential steps of:providing a silicon semiconductor substrate having a surface whereby said substrate has been provided with a semiconductor device whereby said semiconductor device is a partially completed gate electrode structure;depositing a layer of Resist Protection Oxide (RPO) over a surface of said substrate thereby including a surface of said partially completed gate electrode;patterning and etching said layer of RPO thereby creating openings in said layer of RPO whereby said openings overlay and expose said regions where salicided regions need to be formed whereby said etch is an time-mode etch;performing an impurity implant of arsenic (As) or boron (BF.sub.2) into a surface of said substrate thereby including said exposed surfaces of said regions where salicided regions have to be created;performing a pre-metal wet dip of said substrate; depositing a layer of titanium over a surface of said substrate thereby including said regions where salicided regions have to be created;performing a silicon ion mixing implant into a surface of said substrate thereby including said regions where salicided regions have to be created;performing a first Rapid Thermal Anneal of said surface of said substrate thereby forming reacted and unreacted titanium on said surface of said substrate;removing said unreacted titanium from said surface of said substrate; andperforming a second Rapid Thermal Anneal of said surface of said substrate.