Patent ID: 7747901
Filing Date: 2010-06-29
Classification: G06F

Abstract:
1. A control command receive circuit comprising: a first flip-flop having a D input, a clock input receiving a test mode select signal and an output; a second flip-flop having a D input, a clock input receiving an inverted test mode select signal and an output; a third flip-flop having a D input connected to said output of said first flip-flop, a clock input receiving said test mode select signal and an output; a fourth flip-flop having a D input connected to said output of said second flip-flop, a clock input receiving said inverse test mode select signal and an output; a fifth flip-flop having a D input connected to said output of said first flip-flop, a clock input receiving a test clock signal and an output; a first inverter having an input connected to said output of said fifth flip-flop and an output connected to said D input of said first flip-flop; a sixth flip-flop having a D input connected to said output of said second flip-flop, a clock input receiving said test clock signal and an output; a second inverter having an input connected to said output of said sixth flip-flop and an output connected to said D input of said second flip-flop; a seventh flip-flop having a D input connected to said output of said third flip-flop, a clock input receiving said test clock signal and an output; an eighth flip-flop having a D input connected to said output of said fourth flip-flop, a clock input receiving said test clock signal and an output; a ninth flip-flop having a D input connected to said output of said fifth flip-flop, a clock input receiving said test clock signal and an output; a tenth flip-flop having a D input connected to said output of said sixth flip-flop, a clock input receiving said test clock signal and an output; a first exclusive OR gate having a first input connected to said output of said ninth flip-flop, a second input connected to said output of said fifth flip-flop and an output; a second exclusive OR gate having a first input connected to said output of said tenth flip-flop, a second input connected to said output of said sixth flip-flop and an output; a third exclusive OR gate having a first input connected to said output of said ninth flip-flop, a second input connected to said output of said seventh flip-flop and an output; a fourth exclusive OR gate having a first input connected to said output of said tenth flip-flop, a second input connected to said output of said eighth flip-flop and an output; a first AND gate having a first input connected to said output of said first exclusive OR gate, a second input connected to said output of said second exclusive OR gate and an output forming a first command signal; an OR gate having a first input connected to said output of said third exclusive OR gate, a second input connected to said output of said fourth exclusive OR gate and an output; a second AND gate having a first input connected to said output of said first AND gate, a second input connected to said output of said OR gate and an output forming a second command signal; and a third AND gate having a first input connected to said output of said first AND gate, a second input connected to said output of said third exclusive OR gate, a third input connected to said output of said fourth exclusive OR gate and an output forming a third command signal.