Patent ID: 6502214
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A memory test circuit, comprising:a plurality of mats coupled to local input/output lines; a plurality of mat switches that selectively connect or disconnect corresponding ones of the local input/output lines with global input/output lines, wherein the local input/output lines and the global input/output lines transfer information to the plurality of mats or transfer information stored in the mats; a plurality of main amps that amplify data coupled to the global input/output lines; a mat switch controlling circuit that controls the plurality of mat switches; a latch circuit that latches data amplified by the plurality of main amps to be substantially simultaneously outputted; a mat controlling circuit that controls the plurality of mats to be respectively activated according to each mode of a plurality of modes; and a main amp controlling circuit that controls the plurality of main amps to be sequentially operated.