Patent ID: 6423597
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A process for fabricating a DRAM, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed, the process comprising:forming a plurality of bit line contacts and a plurality of node contacts in electric contact with the source/drain regions; forming a first patterned insulating layer on the substrate, in which a plurality of openings is formed in the insulating layer to expose the bit line contacts; covering a first conductive layer and a second insulating layer in sequence on the substrate to electrically connect the first conductive layer to the bit line contacts; patterning the second insulating layer, the first conductive layer and the first insulating layer in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connected to the bit line contacts, thereby exposing the node contacts, wherein the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines; forming a plurality of spacers on sidewalls of the bit line stacked structures, forming a plurality of second conductive layers conformal to surfaces of the trenches; and patterning the second conductive layers to form a plurality of bottom electrodes connected to the node contacts.