Patent ID: 9110656
Filing Date: 2015-08-18
Classification: G06F

Abstract:
1. A method of handling instructions in a processor comprising: receiving a first instruction of a second instruction type in the processor; decoding the first instruction by a decode/issue unit to determine operands of the first instruction; determining that the operands of the first instruction include a dependency on a second instruction of a first instruction type stored in a first entry of a first execution queue, wherein the first execution queue is configured to provide instructions of the first instruction type to a first execution unit; storing the first instruction in a first entry of a second execution queue, determining whether the operands of the first instruction include a dependency on any instruction stored in the second execution queue; in response to the determining that the operands of the first instruction include the dependency on the second instruction: wherein the first execution unit is further characterized as a load/store execution unit, the second execution unit is further characterized as a complex integer execution unit, the second execution queue is further characterized as a dependent queue and the third execution queue is further characterized as an independent queue.