Patent ID: 6466998
Filing Date: 2002-10-15
Classification: G06F

Abstract:
A mechanism of a host chipset for routing interrupts from a peripheral bus to an interrupt controller, comprising:input terminals coupled to interrupt request lines of input/output (I/O) devices from said peripheral bus, to receive incoming interrupts from said peripheral bus; and logic circuitry arranged to logically combine the interrupts received at the input terminals and to pass an output boot interrupt to the interrupt controller, when an operating system (OS) does not support an advanced peripheral interrupt controller (APIC) integrated in said host chipset, wherein said logic circuitry comprises: one or more first logic gates arranged to receive an individual interrupt from the peripheral bus, and to logically combine all incoming interrupts; and one or more second logic gates arranged to receive outputs from the first logic gates, and to logically combine the outputs from the first logic gates to pass the boot interrupt tote interrupt controller external to said host chipset, when the operating system (OS) is not APIC aware.