Patent ID: 8331157
Filing Date: 2012-12-11
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of first main bit lines corresponding to at least one first memory cell; a plurality of second main bit lines corresponding to at least one second memory cell; at least one sense amplifier configured to output read data according to a difference between a voltage of any one of the plurality of first main bit lines and a voltage of any one of the plurality of second main bit lines; a voltage supply switching section configured to supply a predetermined reference voltage to one of the plurality of first main bit lines corresponding to one of the plurality of second main bit lines in which a current according to a threshold voltage of the at least one second memory cell is generated; and a resistance switching section configured to form electrical connection between a ground node and the one of the plurality of second main bit lines in which the current according to the threshold voltage of the at least one second memory cell is generated with a predetermined resistance value.