Patent ID: 6249891
Filing Date: 2001-06-19
Classification: G01R,G06F

Abstract:
A high speed test pattern evaluation apparatus, comprising:an LSI tester simulator formed of software for simulating an operation of an LSI tester and generating a test pattern for testing a semiconductor device and an expected value pattern for comparing the output of the semiconductor device which is responsive to the test pattern, the test pattern and the expected value pattern being in a cycle base form;a cycle-event converter for converting the test pattern in the cycle base form from the LSI tester simulator to a test pattern of an event base form;a first memory for storing the event based test pattern from the cycle-event converter;a second memory for storing a predetermined amount of simulated input/output data of the semiconductor device from a dump file storing data resulted from executing a logic simulation on the semiconductor device by a testbench as a part of a computer aided design (CAD) process for the semiconductor device; anda comparator for synchronizing the data stored in the first and second memories by comparing a timing relationship between the two corresponding pieces of data and extracting the simulated output data of the semiconductor device from the dump file corresponding to the test pattern from the LSI tester simulators;whereby the test pattern produced by the LSI tester simulator is evaluated with reference to the data from the dump file produced through the logic simulation of the semiconductor device by the testbench, thereby evaluating the test pattern without using an actual LSI tester or a semiconductor device.