Patent ID: 8339873
Filing Date: 2012-12-25
Classification: G11C

Abstract:
1. A device comprising: a memory array including a first sense amplifier including a first input coupled to the first bitline to receive the first information, a second input coupled to the second bitline to receive the second information, a third input coupled to the third bitline to receive the third information, and an output to provide an indicator of the first storage state information based upon the first information, the second information and the third information; a second sense amplifier including a first input coupled to the second bitline to receive the second information, a second input coupled to the fourth bitline to receive the fourth information, a third input coupled to the first bitline to receive the first information, and an output to provide an indicator of the second storage state information based upon the second information, the fourth information and the first information; and a third sense amplifier including a first input coupled to the third bitline to receive the third information, a second input coupled to the first bitline to receive the first information, a third input coupled to the fifth bitline to receive the fifth information, and an output to provide an indicator of the third storage state information based upon the third information, the first information and the fifth information.