Patent ID: 7546516
Filing Date: 2009-06-09
Classification: H03M,H04L

Abstract:
1. A method of transmitting a plurality of data bits over a transmission channel, said method comprising: (a) arranging the plurality of data bits into a sequence of data blocks each composed of an equal number of data bits; (b) arranging a portion of the sequence of data blocks into a first plurality of matrices, n, where each of said matrices has an equal number, y, of columns and rows, numbered 0 through y, where y is equal to twice the number of data bits in each data block plus an odd number equal to at least five, by: (c) generating one set of check bits, in a first processing arrangement, for each matrix having a plurality of data blocks and being a part of the first plurality of matrices and associating a corresponding check bit with the data bits of each block of data of each matrix of the first plurality of matrices; (d) repeating steps (b)-(c) for a second plurality of matrices with the data bits of the first column of the first matrix of the second plurality of matrices arranged as the data bits in the n+1 (e) generating one set of check bits, in the first processing arrangement, for each matrix having a plurality of data blocks and being a part of the second plurality of matrices and associating a corresponding check bit with the data bits of each block of data of each matrix of the second plurality of matrices; (f) repeating steps (d)-(e) for a third plurality of matrices with the data bits of the first column of the first matrix of the second plurality of matrices arranged as the data bits in the n+1 (g) generating one set of check bits, in the first processing arrangement, for each matrix having a plurality of data blocks and being a part of the third plurality of matrices and associating a corresponding check bit with the data bits of each block of data of each matrix of the third plurality of matrices; (h) repeating steps (f)-(g) for additional pluralities of matrices in like manners until sets of check bits are generated for each matrix of all n matrices of all y/n pluralities of matrices; (i) generating a second set of check bits, in a second processing arrangement, for a matrix whose columns correspond to the first columns of all of the matrices processed in steps (b)-(h); (j) generating a second set of check bits, in the second processing arrangement, for a matrix whose columns correspond to the second columns of all of the matrices processed in steps (b)-(h); (k) repeating step (j) for all columns of all matrices in the pluralities of matrices in like manners until y second sets of check bits for all matrices of all pluralities of matrices are generated; (l) transmitting at least an ordered set of pluralities of matrices having an ordered set of data blocks and each data block having two associated check bits in an order that is the same as an order in which the bits of the data blocks of each set of pluralities of data blocks are processed by the first processing arrangement; (m) receiving at least said ordered set of matrices having said ordered set of data blocks and each data block having two associated check bits at a decoder-corrector; (n) detecting and correcting in a first manner, with said decoder-corrector, one or more errors in the data bits or first check bit of the data blocks of said ordered sets of pluralities of matrices initially using the first sets of check bits generated for these data blocks according to the first processing arrangement.