Patent ID: 6388941
Filing Date: 2002-05-14
Classification: G11C

Abstract:
A semiconductor device comprising:a first memory unit and a second memory unit each having a plurality of memory cells; a plurality of first memory elements and second memory elements, which store address information of memory cells to be relieved in said first memory unit and have element structures different from one another; a plurality of first comparators which compare the address information stored in said first memory elements with signal information on an address signal wiring; a plurality of second comparators which compare the address information stored in said second memory elements and the signal information on the address signal wiring; and a relief control circuit which controls switching from an access to said first memory unit to an access to said second memory unit according to the coincidence between the results of comparisons between said first and second comparators, wherein said plurality of first memory elements and first comparators are formed in a first area along the address signal wiring, and said plurality of second memory elements and second comparators are formed in a second area adjacent to the first area.