Patent ID: 7629682
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A wafer level package comprising: a semiconductor chip having a plurality of bonding pads on a front surface thereof; a lower insulation layer formed on the semiconductor chip which expose the bonding pads; re-distribution lines formed on the lower insulation layer to be connected to the bonding pads at first ends thereof; an upper insulation layer formed on the lower insulation layer including the re-distribution lines, with portions of the re-distribution lines exposed; solder balls attached to the exposed portions of the re-distribution lines; and a cap covering a rear surface of the semiconductor chip, wherein the cap and the semiconductor chip are mechanically coupled to each other, and the cap and the semiconductor chip are coupled to each other by a slide type coupling, and wherein the cap is defined with a groove on one surface thereof an plurality of sidewalls, wherein the groove has a similar size to that of the semiconductor chip and is opened on only one sidewall thereof, and the semiconductor chip is slidably fitted into the groove through the opened sidewall of the cap and is fixedly located in the groove.