Patent ID: 6438659
Filing Date: 2002-08-20
Classification: G06F

Abstract:
For use in a data processing system having multiple instruction processors (IPs) and multiple input/output (I/O) systems, a memory system, comprising:a shared main memory to store addressable blocks of data signals; one or more IP caches each coupled to one or more of the IPs and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory; one or more I/O memories each coupled to an associated one or more of the I/O systems and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory; a directory storage device coupled to said shared main memory to store directory information for each associated one of said addressable blocks, said directory information indicating which of said one or more IP caches and which of said one or more I/O memories is storing an associated addressable block of data signals, said directory information further including access privilege indicators for said associated addressable block of data signals, said access privilege indicators being selected from a first set of access privilege indicators if at least one of said IP caches stores said associated addressable block, said access privilege indicators being selected from a second set of access privilege indicators if only said one or more I/O memories stores said associated addressable block, wherein each of said IP caches and each of said I/O memories includes circuits to issue commands to said shared main memory, each of said commands to request a copy of a requested one of said addressable blocks of data signals, and further including a control circuit coupled to ones of said IP caches and ones of said I/O memories to receive said issued commands, and to determine, based on a selected one of said issued commands for said requested one of the addressable blocks of data signals, and further based on said associated one of said access privilege indicators for said requested one of said addressable blocks of data signals, which one of said access privilege indicators is to be associated with said requested one of said addressable blocks of data signals upon completion of execution of said selected one of said issued command, and wherein each of said IP caches and ones of said I/O memories may return modified said requested ones of said addressable blocks of data signals to said shared main memory to be stored during return operations, and wherein said directory storage device includes an error circuit responsive to said return operations such that any of said return operations causes an error signal to be issued if said return operation is performed by any of said IP caches or any of said I/O memories not indicated by said directory information as storing any one of said modified requested ones of said addressable blocks of data signals.