Patent ID: 6576962
Filing Date: 2003-06-10
Classification: G11C,H01L

Abstract:
A CMOS SRAM cell having a prescribed data state upon power-up, comprising:first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (T1/T2;T3/T4) serially connected between a voltage source and a circuit ground to form a first inverter with a first data node (A) between the two transistors (T1/T2) of the first inverter and to form a second inverter with a second data node (B) between the two transistors (T3/T4) of the second inverter, the gates of transistors of the first inverter connected together and the gates of the second inverter connected together, the connected together gates of the first and second inverter cross-coupled to the data node of the other inverter, and a diode (D) connected in the connection between the gates of the transistors of only a selected one of the inverters wherein said diode (D) changes the gate charge time of its inverter to assure that each inverter will assume a pre-determined state upon power-up.