Patent ID: 6127209
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device controlling a flow of majority carriers by a voltage applied to a gate, comprising the steps of:forming in a main surface of a substrate a first conductive layer including impurity of a first conductivity type serving as one source/drain region;forming a first interlayer insulating film on said substrate;forming a gate electrode having an upper surface and a lower surface on said first interlayer insulating film;forming a second interlayer insulating film on said substrate so as to cover said gate electrode;forming a contact hole penetrating through said first interlayer insulating film, said gate electrode, and said second interlayer insulating film into the surface of said first conductive layer;covering a sidewall surface of said contact hole with a gate insulating film;forming a semiconductor layer on said substrate in contact with the surface of said first conductive layer so as to fill said contact hole;implanting impurity of a first conductivity type into the surface of said semiconductor layer; anddiffusing said impurity implanted into the surface of said semiconductor layer in said semiconductor layer, and diffusing said impurity included in said first conductive layer from said first conductive layer to said semiconductor layer, thereby forming in said semiconductor layer the other source/drain region and a channel region sandwiched by said the other source/drain region and said one source/drain region.