Patent ID: 8386747
Filing Date: 2013-02-26
Classification: G06F

Abstract:
1. An apparatus comprising: at least one processor core, the at least one processor core suitable for executing a plurality of processes, wherein each of the processes has a respective address space; and a memory management unit coupled between the at least one core and an interface to memory, the memory management unit configured to map from effective addresses in respective ones of the address spaces to physical addresses in the memory wherein mappings performed by the memory management unit are based on address translation entries of an address translation table, the memory management unit including entry selection logic that, for a first subset of less than all of the processes, selects from amongst plural alternative mappings coded in respective ones of the address translation entries, wherein for at least some effective addresses mapped for a particular process of the first subset, selection of a particular one of the address translation entries is based on one or more externally sourced values.