Patent ID: 6636959
Filing Date: 2003-10-21
Classification: G06F

Abstract:
A processor comprising:a fetch address generation unit configured to generate a fetch address; a line predictor coupled to said fetch address generation unit, said line predictor including a first memory comprising a plurality of entries, each entry storing a plurality of instruction pointers, wherein said line predictor is configured to detect a miss of said fetch address in said line predictor; and a decode unit coupled to receive a plurality of instruction bytes fetched in response to said fetch address and further coupled to said line predictor, said decode unit configured to decode said plurality of instruction bytes in response to said miss to generate said plurality of instruction pointers for a first entry in said first memory, said first entry corresponding to said fetch address, and wherein said decode unit is configured to terminate decode and provide said plurality of instruction pointers to said line predictor in response to detecting a termination condition.