Patent ID: 6223141
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A method of simulating delay-independent functions of an input netlist of Boolean logic gates of a synchronous digital circuit in response to a sequence of input vectors, said gates each having a respective gate fanin of one or more inputs and a respective gate fanout of zero or more outputs, said inputs and said outputs of all said gates defining literals of said netlist, the method comprising:optimizing said input netlist;levelizing said optimized netlist;representing each of said gates of said levelized netlist in software programming statements; andexecuting a computer program, derived from said software programming statements, with said sequence of input vectors as input, to provide for each of said input vectors a corresponding output vector;whereby said output vector represents said delay-independent functions of said input netlist; andwherein said optimizing comprises:eliminating ones of said gates which have, as said respective gate fanin, only one input;eliminating ones of said gates which have, as said respective gate fanout, zero outputs;collapsing ones of said gates, onto said respective gate fanout, when said collapsing reduces an overall number of said literals of said netlist; andfactoring selected ones of said gates from a sum-of-products form to a factored form.