Patent ID: 8988103
Filing Date: 2015-03-24
Classification: H01L,H03K

Abstract:
1. An electronic logic circuit comprising: a. a plurality of interconnected two terminal areal capacitive coupling devices coupled to a set of data inputs; i) a floating gate; and ii) an n-type impurity source coupled to a first terminal; and iii) an n-type impurity drain coupled to a second terminal and wherein the n-type impurity drain overlaps a sufficient portion of said floating gate and is configured to impart an input signal voltage applied to said second terminal of said n-type impurity drain and said first terminal to said floating gate through areal capacitive coupling and cause each of said areal capacitive coupling devices to be placed into a first state; further wherein an output of each two terminal areal capacitive coupling device is related to said first state or said second state, and said plurality of interconnected two terminal areal capacitive devices are configured to generate a plurality of separate outputs;