Patent ID: 6226213
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A reference cell array for providing a reference voltage while reading a normal memory cell in a normal cell array comprising:a plurality of cells classified into first cells, second cells, and third cells, using a common source line as a mirror plane divided said plurality of cells into an upper portion and a lower portion so that said first cells, second cells, and third cells of upper portion mirror symmetry with that of said lower portion, said common source line connected said first cells on said upper portion and said lower portion to a reference ground, said first cells, said second cells and said third cells of said upper portion and of said lower portion each having a respective first word line, a respective second word line and a respective third word line connecting thereto control gates thereof, said respective first word line, said respective second word line coupled to an power source, wherein said plurality of cells are flash memory and have their floating gate connected to said power source;a plurality of reference bit lines, each of said reference bit lines having a bit line contact being interlaced as a black-white grid on a checkerboard so as to connect a drain region of one of said third cells either at said upper portion or at said lower portion, further, each of said reference bit lines having an isolation region at a common source region between one of said second cells and one of said third cells so as to interrupt connection thereof, said isolation region and said bit line contact of each of said reference bit lines being at different portion; anda first decoder connected said third word line in said upper portion and in said lower portion to select one to active.