Patent ID: 7603536
Filing Date: 2009-10-13
Classification: H04N

Abstract:
1. A data processing apparatus comprising: a data processor that issues a plurality of data transfer requests simultaneously and performs a series of data processing; a first memory provided inside a circuit including the data processor; a first memory controller that performs an access control for the first memory; a second memory that exchanges data with the data processor via a bus; a second memory controller that performs an access control for the second memory; and a memory selector that assigns to the second memory a data transfer request from the data processor, assigns, to the first memory, unassigned data transfer requests from the data processor, assigns, to the second memory, in order, on a data transfer request basis, data transfer requests from the data processor whose transfer amount efficiency values are low, assigns, to the second memory, part, corresponding to unused, residual bus bandwidth, of a data transfer request having low transfer amount efficiency among the unassigned data transfer requests, the memory selector assigns the other part of the data transfer request having low transfer amount efficiency among the unassigned data transfer requests to the first memory, and assigns, to the first memory, residual data transfer requests from the data processor.