Patent ID: 6424658
Filing Date: 2002-07-23
Classification: H04L,Y10S

Abstract:
A network switch chip comprising:a plurality of input ports connected to external network nodes to receive packets; a plurality of output ports connected to external network nodes, the output ports for transmitting the packets to the external network nodes; an embedded packet memory for temporarily storing packets received from the input ports for transfer to the output ports for transmission, the embedded packet memory being a dynamic-random-access memory (DRAM) organized into rows and columns; an internal data bus, coupled to the embedded packet memory, for writing packets from the input ports to the embedded packet memory, and for reading the packets from the embedded packet memory to the output ports, the internal data bus being an internal bus without connection to external pins of the network switch chip during normal operating modes when packets are transmitted from input ports to output ports; port controllers, coupled to the input ports and the output ports, for detecting packets received at an input port and writing the packet into the embedded packet memory over the internal data bus, and for reading the packet from the embedded packet memory to an output port; and a message bus, coupled to the port controllers, for sending a message from a port controller for an input port that receives a packet to a port controller for an output port that is a destination indicated by the packet, the message causing the port controller for the output port to read the packet from the embedded packet memory, whereby packets are switched from an input port to an output port by being written to and read from the embedded packet memory using the internal data bus in response to the message sent over the message bus.