Patent ID: 6659512
Filing Date: 2003-12-09
Classification: H01L,H05K

Abstract:
An integrated circuit package comprising:a package substrate having a first surface including a first array of interconnection sites, and a second array of interconnection sites; a first integrated circuit die having a first surface including an array of interconnection sites electrically connected to the second array of interconnection sites of the package substrate; and a second integrated circuit die having a first surface including an array of interconnection sites electrically connected to the first array of interconnection sites of the package substrate, wherein the first integrated circuit die is positioned amid the package substrate and the second integrated circuit die; wherein the first integrated circuit die has a second surface opposite the first surface, the second surface of the first integrated circuit die having an additional array of interconnection sites, wherein the first surface of the second integrated circuit die includes a further array of interconnection sites that is different than the array of interconnection sites of the first surface of the second integrated circuit die, and wherein the further array of interconnection sites of the second integrated circuit die is electrically connected to the additional array of interconnection sites on the second surface of the first integrated circuit die.