Patent ID: 7810000
Filing Date: 2010-10-05
Classification: G01R

Abstract:
1. A digital logic circuit integrated on a die, comprising: a functional logic block operable in a functional operating mode of said digital logic circuit, said functional logic block having a plurality of inputs for receiving corresponding digital input signals and at least one digital output generated in conformity with a logical combination of values of at least two of the digital input signals; a selector circuit responsive to a test mode control signal, wherein said selector circuit de-selects a corresponding one of said at least two digital input signals from one of said plurality of inputs and couples a feedback one of said at least one digital output to said one of said plurality of inputs when said test mode control signal indicates a test mode is selected, wherein a given signal path through said functional logic block oscillates at a frequency dependent on a delay of said given signal path when said test mode is selected, whereby said delay can be determined by measuring a characteristic of oscillation of said given signal path when said test mode is selected, and wherein said selector circuit further de-selects said at least two input signals when said test mode is selected, and asserts predetermined logic values for said at least two digital input signals other than said one of said plurality of inputs; a monitoring circuit having an input coupled to said feedback output, for producing an indication in response to said oscillation, wherein said monitoring circuit comprises an edge detector having a clock input coupled to a functional clock of said digital logic circuit, and a signal input coupled to said feedback output, and an adjustable delay coupled between said signal input and said feedback output, whereby said edge detector provides an indication of a delay between an edge of said functional clock and an edge of said oscillation; a calibration delay line for providing a predetermined delay; a calibration latch coupled between an output of said delay line and an input of said delay line and having a clock input coupled to said functional clock; and a multiplexer having a select input coupled to a calibrate mode selection signal, a first input coupled to said feedback output, a second input coupled to an output of said calibration delay line and an output coupled to an input of said adjustable delay, whereby said edge detector provides an indication of a delay between an edge of said functional clock and an edge of a calibration oscillation occurring through said calibration delay line when said calibrate mode selection signal is asserted.