Patent ID: 6147515
Filing Date: 2000-11-14
Classification: H03K

Abstract:
A differential receiver comprisinga first pair of transistors, each of the first pair of transistors including a drain, a source and a gate, the source of one of the first pair of transistors being coupled to the drain of another of the first pair of transistors, the drain of the one of the first pair of transistors being coupled to a first node, the gate of the one of the first pair of transistors being coupled to a node enable signal, and the gate of the another of the first pair of transistors being coupled to a reference voltage, the first pair of transistors providing a voltage at the first node indicative of the reference voltage when the node enable signal is active;a second pair of transistors, each of the second pair of transistors including a drain, a source and a gate, the source of one of the second pair of transistors being coupled to the drain of another of the second pair of transistors, the drain of the one of the second pair of transistors being coupled to a second node, the gate of the one of the second pair of transistors being coupled to the node enable signal, and the gate of the another of the second pair of transistors being coupled to an input signal, the second pair of transistors providing a voltage at the second node indicative of the voltage of the input signal when the node enable signal is active; anda resolving circuit coupled to the first and second nodes, the resolving circuit being powered by a clock signal, the resolving circuit resolving which of the first and second nodes has a higher voltage when the clock signal is active and the node enable signal is active, the resolving circuit includinga first inverter, the first inverter including first and second transistors, the first and second transistors of the first inverter each including a gate, a source and a drain, anda second inverter, the second inverter including first and second transistors, the first and second transistors of the second inverter each including a gate, a source and a drain,the drains of the first and second transistors of the first inverter being coupled to the gates of the first and second transistors of the second inverter and to the first node; andthe drains of the first and second transistors of the second inverter being coupled to the gates of the first and second transistors of the first inverter and to the second node.