Patent ID: 7437646
Filing Date: 2008-10-14
Classification: G01R,G06F

Abstract:
1. A test pattern generating method for an electronic circuit having XOR (exclusive OR) gates, in which a test pattern is generated for supplying said electronic circuit in order to detect faults of said electronic circuit corresponding to an output pattern of said electronic circuit, comprising: counting the number of undetectable faults occurring, at each input pin being in each of candidate states 0 and 1 of said XOR gates when each of said XOR gates becomes a D frontier (different frontier) or a J frontier (justify frontier); selecting a state in which the number of undetectable faults is smaller from said candidate states 0 and 1 as an allocating state to a respective input pin, based on a counted result at said counting by selecting the candidate state 1 as the allocating state to be allocated to each said input pin when the number of unpredictable faults at each said input pin and the candidate state 0 is larger than that in the candidate state 1 and selecting the candidate state 0 as the allocating state to be allocated to each said input pin when the number of unpredictable faults at each said input pin in the candidate state 1 is larger than that of the candidate state 0; and generating said test pattern based on a selected state at said selecting.