Patent ID: 7582938
Filing Date: 2009-09-01
Classification: H01L

Abstract:
1. A semiconductor device configured to introduce both gate-coupled and substrate-biased effects, formed on a P-type semiconductor substrate, for power pin protection against both positive and negative ESD stress conditions, comprising: a first P-type well formed on the P-type semiconductor substrate, not hard-wired to VSS but shorted to VSS through the P-type semiconductor substrate; a second P-type well formed on the P-type semiconductor substrate and hard-wired to VSS; a plurality of multi-finger nMOS transistors formed on the first P-type well, wherein each multi-finger nMOS transistor comprises a source region, hard-wired to VSS, a drain region, hard-wired to VDD, and a gate region, electrically connected to VSS; a first N-type well ring formed on the P-type semiconductor substrate, hard-wired to VDD, and disposed between the first P-type well and the second P-type well such that the first N-type well ring is next to both the first P-type well and the second P-type well, and separates the first P-type well from the second P-type well; a third P-type well formed on the P-type semiconductor substrate and hard-wired to VSS; a second N-type well ring formed on the P-type semiconductor substrate, hard-wired to VDD, and disposed between the first P-type well and the third P-type well such that the second N-type well is next to both the first P-type well and the third P-type well, and separates the first P-type well from the third P-type well, said first and second N-type well rings configured such that first P-type well is isolated from the second P-type well and the third P-type well other than being shorted through the P-type semiconductor substrate.