Patent ID: 7095249
Filing Date: 2006-08-22
Classification: H03K

Abstract:
1. A semiconductor integrated circuit comprising: a first controlling circuit section having input thereto an input signal having an amplitude between a low voltage and the ground, said first controlling circuit operating with an electricity source of the low voltage, said first controlling circuit outputting a first control signal generated by the input signal, outputting an inverse signal of the first control signal, and putting out a second control signal generated from the first control signal; a level transforming circuit having input thereto the first control signal and the inverse signal, and outputting a first signal having an amplitude between the low voltage and a high voltage higher than the low voltage; a first buffer circuit having input thereto the first p-channel type MOS transistor connected between the electricity source of the high voltage and a first output node, wherein a gate of said first p-channel type MOS transistor with the first supplied signal, said first buffer circuit having a first n-channel type MOS transistor connected between said first output node and the electricity source of the low voltage, which a gate of said first n-channel type MOS transistor is supplied with the first signal, and wherein said first buffer circuit outputs a second signal having an amplitude between the high voltage and the low voltage to said first output node; a second buffer circuit having a second p-channel type MOS transistor connected between the electricity source of the low voltage and a second output node, wherein a gate of said second p-channel type MOS transistor is supplied with the second control signal, and which has second n-channel type MOS transistor connected between said second output node and the ground, wherein a gate of said second n-channel type MOS transistor is supplied with the second control signal, and wherein said second buffer circuit outputs a third signal having an amplitude between the low voltage and the ground to said second output node; and an overvoltage protecting circuit having a drain of a third p-channel type MOS transistor connected with a third output node, wherein a source of said third p-channel type MOS transistor is supplied with the second signal, said overvoltage protecting circuit having a drain of the third n-channel type MOS transistor connected with third output node, wherein a source of said third n-channel type MOS transistor is supplied with the third signal, and wherein each gate of said third p-channel type MOS transistor and said third n-channel type MOS transistor is supplied with the low voltage in common, and wherein said overvoltage protecting circuit outputs a fourth signal having an amplitude between the high voltage and the ground to said third output node.