Patent ID: 8842221
Filing Date: 2014-09-23
Classification: H04N

Abstract:
1. A signal adjusting circuit, comprising: a delay unit, directly coupled to an analog-to-digital converter (ADC), receiving a digital signal from the ADC, and delaying the received digital signal for N periods to output a delay signal, wherein N is greater than or equal to 1; a minimum value acquisition device, directly coupled to the ADC, receiving the digital signal, and acquiring and outputting a minimum value within the received digital signal in every N periods; a first operating unit, coupled to the delay unit and the minimum value acquisition device, receiving the delay signal from the delay unit, receiving the minimum value from the minimum value acquisition device, and operating the received delay signal with the received minimum value to output an adjusting signal; a register, coupled between the minimum value acquisition device and the first operating unit, latching the minimum value output from the minimum value acquisition device in every N periods, and outputting a latching result to the first operating unit for being operated with the delay signal; an average unit, coupled to the register, receiving latching results from the register, and counting an average value of the latching results; and a second operating unit, coupled to the first operating unit and the average unit, and operating the adjusting signal with the average value to obtain a second adjusting signal.