Patent ID: 6310390
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A semiconductor package comprising:a semiconductor die;a plurality of conductors attached to the die having first sides and opposing second sides, the conductors comprising lead fingers of a metal lead frame, each conductor having a first width W1, the first sides including a plurality of first pads wire bonded to the die, the second sides including a plurality of second pads, each second pad having a second width W2, the first width W1 being less than the second width W2 and the second pads configured in a dense array of rows and columns;a polymer tape having configured to attach the die to the conductors, to support the die on the conductors for wire bonding and to electrically insulate the conductors;an encapsulating resin encapsulating the die and the conductors and having a plurality of openings therein aligned with the second pads; anda plurality of ball contacts in the openings attached to the second pads.