Patent ID: 8250429
Filing Date: 2012-08-21
Classification: H03M,H04L

Abstract:
1. A PLL circuit that extracts a synchronizing clock from an analog signal in which a channel frequency changes, said PLL circuit comprising: a phase synchronization loop having a loop gain and comprising: an A/D converter that converts the analog signal into a digital signal; a digital phase comparator that operates in synchrony with the synchronizing clock to output a phase error signal between the analog signal and the synchronizing clock based on the digital signal output from said A/D converter; a digital loop filter that operates in synchrony with the synchronizing clock to output a digital frequency value proportional to the channel frequency based on the phase error signal; and an oscillator that outputs the synchronizing clock having a frequency controlled based on the digital frequency value; and a loop-gain control unit that controls the loop gain of said phase synchronization loop based on said digital frequency value.