Patent ID: 8488368
Filing Date: 2013-07-16
Classification: G11C

Abstract:
1. A static random access memory with write-through capability, comprising: a. a memory cell configured to store a bit of data; b. a write enable signal configured to enable writing a write value from a write line input into the static random access memory cell and to enable reading a read value from the memory cell onto a DOT line; c. a local evaluation circuit configured to place the write value from the write line onto the DOT line during a single clock cycle in which the value is being written into the memory cell; and d. an early read suppression circuit configured to electrically isolate the DOT line from a data out line thereby preventing a leakage current loss from the local evaluation circuit and also configured to make the value placed on the DOT line to be read from the data out line during the single clock cycle.