Patent ID: 6653190
Filing Date: 2003-11-25
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit comprising.depositing a charge-trapping material over a semiconductor substrate; forming first and second bitlines in the semiconductor substrate; depositing a wordline material over the charge-trapping material; depositing a hard mask material over the wordline material; depositing an anti-reflective coating material over the hard mask material; depositing a photoresist material over the anti-reflective coating material; processing the photoresist material and the anti-reflective coating material to form a photomask of a patterned photoresist material and a patterned anti-reflective coating material; processing the hard mask material using the photomask to form a hard mask: removing the patterned photoresist; removing the patterned anti-reflective coating material without damaging at least one of the hard mask, the wordline material, and a combination thereof; processing the wordline material using the hard mask to form a wordline; and removing the hard mask without damaging at least one of the wordline, the charge-trapping material, and a combination thereof.