Patent ID: 8909871
Filing Date: 2014-12-09
Classification: G06F

Abstract:
1. A method of data processing in a data processing system having a system memory and a cache hierarchy that caches contents of said system memory, said method comprising: receiving, at a cache hierarchy, a storage modifying operation having a cacheable target real memory address; determining whether said storage modifying operation is directed to a full cache line; determining whether or not said storage modifying operation has an associated bypass indication; determining whether or not said storage modifying operation hit a cache in the cache hierarchy; in response to determining that said storage modifying operation is directed to a full cache line, has an associated bypass indication, and did not hit a cache in the cache hierarchy, bypassing the cache hierarchy and performing an update indicated by said storage modifying operation in said system memory; in response to determining that said storage modifying operation is directed to a full cache line, has an associated bypass indication, and hit a cache in the cache hierarchy, determining whether the cache that was hit has write ownership; in response to determining that the cache that was hit does not have write ownership, bypassing the cache hierarchy and performing an update indicated by said storage modifying operation in said system memory; in response to determining that the cache that was hit does have write ownership, performing said update indicated by said storage modifying operation in said cache hierarchy; and in response to determining that said storage modifying operation is directed to a full cache line and does not have an associated bypass indication, performing said update indicated by said storage modifying operation in said cache hierarchy.