Patent ID: 6013547
Filing Date: 2000-01-11
Classification: H01L

Abstract:
A method for fabricating a memory device, on a semiconductor substrate, using a self-aligned contact structure for connection between a gate structure and an active device region, in the semiconductor substrate, comprising the steps of:providing an insulator filled, shallow trench isolation region, in said semiconductor substrate;providing transfer gate transistors, comprised of insulator capped, gate structures, on a thin gate insulator layer, with insulator spacers on the sides of said insulator capped, gate structures, and with a lightly doped source and drain region, in a region of said semiconductor substrate not covered by said insulator capped, gate structures;applying an organic coating, comprised of a thick organic coating between said gate structures, and a thin organic coating on the top surface of said insulator capped, gate structures;forming a photoresist shape, with a butt contact opening, in said photoresist shape, exposing a portion of said thin organic coating, overlying a portion of the top surface of a insulator capped, gate structure, and exposing a portion of said thick organic coating, overlying an active device region, between said insulator capped, gate structures;removing said thin organic coating, from the top surface of an insulator capped, gate structure, exposed in said butt contact opening, in said photoresist shape;removing insulator, from the top surface of the portion of said insulator capped, gate structure exposed in said butt contact opening, in said photoresist shape, creating a portion of an uncapped, gate structure;removing said photoresist shape, said thin organic coating, and said thick organic coating;forming heavily doped source and drain regions in a region of said semiconductor substrate, not covered by said insulator capped, gate structures, and not covered by said insulator spacers, on the sides of said insulator capped, gate structures;forming a SAC opening in a composite insulator layer, and in an underlying silicon nitride layer, exposing said portion of uncapped, gate structure, and exposing a portion of said active device region; andforming a metal SAC structure, in said SAC opening, resulting in a connection between a gate structure, and an active device region, in said semiconductor substrate.