Patent ID: 6194939
Filing Date: 2001-02-27
Classification: H04J,H04L

Abstract:
A system for preventing time-walking in a digital switching network when switching from a first clock to a second clock, comprising:a clock divider selection circuit operable to output an on-line divided clock and an off-line clock;an enhanced digital phase aligner operable to receive said on-line divided clock and said off-line clock from said clock divider selection circuit and output an off-line divided clock which is the off-line clock time shifted such that said off-line divided clock is in phase with said on-line divided clock within plus or minus one-half the clock period of said off-line clock; anda clock select control circuit operable to receive said on-line divided clock and said off-line divided clock from said enhanced digital phase aligner, receive a smoothed clock, compare said on-line divided clock and said off-line divided clock to said smoothed clock, and output a clock select control signal to said clock divider selection circuit.