Patent ID: 8893069
Filing Date: 2014-11-18
Classification: G06F

Abstract:
1. A computer-implemented method of generating a layout for a circuit design, the method comprising: receiving a schematic of the circuit design, the circuit design comprising a plurality of sub-circuits, wherein each of the plurality of sub-circuits comprises a plurality of instances arranged according to a topology representing relative positions of the plurality of instances; generating a layout pattern for each sub-circuit in one portion of the schematic; selecting a first layout pattern of a first sub-circuit from said one portion of the schematics; identifying, by using a computer, at least one sub-circuit in another portion of the schematic based on the difference between the topology of the identified sub-circuit and the topology of the first sub-circuit being within a pre-defined tolerance, wherein each instance of the identified sub-circuit has a corresponding instance in the first sub-circuit; and copying the first layout pattern to generate a layout pattern for the at least one identified sub-circuit, wherein the difference between the topology of the identified sub-circuit and the topology of the first sub-circuit satisfies the following: wherein x