Patent ID: 6903978
Filing Date: 2005-06-07
Classification: G11C

Abstract:
1. A method of programming a PMOS stacked-gate memory cell, wherein the memory cell includes a p-type source region formed in n-type semiconductor material, a p-type drain region formed in the n-type semiconductor material and spaced-apart from the p-type source region to define a substrate channel region therebetween, a conductive floating gate electrode formed over the substrate channel region and separated therefrom by gate dielectric material, and a conductive control gate electrode formed over the floating gate electrode and separated therefrom by intergrate dielectric material, the programming method comprising: (a) applying a negative voltage potential to the p-type drain region; (b) applying a voltage pulse to the control gate electrode such that electrons are attached to the floating gate electrode from the p-type drain region through the gate dielectric material; (c) repeating step (b) above to provide a sequence of voltage pulses to the control gate electrode such that sufficient electrons are attached to the floating gate electrode to bring the floating gate electrode from an initial voltage potential to a selected voltage potential that is negative and lower in absolute value than the negative voltage potential applied to the p-type drain region.