Patent ID: 8669163
Filing Date: 2014-03-11
Classification: H01L

Abstract:
1. A method comprising: forming a superlattice region in a substrate, wherein the superlattice region comprises a non-semiconductor monolayer sandwiched between two base semiconductor layers, and wherein the steps of forming the superlattice region comprise: forming a gate dielectric over the superlattice region; forming a gate electrode over the gate dielectric; forming a first source/drain region adjacent the gate dielectric through implanting ions into the first semiconductor region, wherein the first source/drain region is of a first conductive type; and forming a second source/drain region adjacent the gate dielectric through implanting ions into the second semiconductor region, wherein the first and the second source/drain regions are opposite sides of the gate electrode, and wherein the second source/drain region is of a second conductivity type opposite the first conductivity type, wherein a portion of the superlattice layers between the first and the second source/drain regions forms a superlattice channel region.