Patent ID: 8274108
Filing Date: 2012-09-25
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of selection gate electrodes provided on the stacked body and aligned in the first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes and the selection gate electrodes; a plurality of source lines aligned in the first direction and connected to upper end portions of some of the semiconductor pillars; a plurality of bit lines aligned in the second direction and connected to upper end portions of a remainder of the semiconductor pillars; a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to the source line, an upper end portion of the one other of the semiconductor pillars being connected to the bit line; a charge storage layer provided between one of the control gate electrode and one of the semiconductor pillar; and a gate insulating film provided between one of the selection gate electrode and one of the semiconductor pillar, at least some of the control gate electrodes being pierced by two of the semiconductor pillars adjacent to each other in the second direction, two of the semiconductor pillars being connected to each other by the connection member and provided to pierce mutually different control gate electrodes.