Patent ID: 7932563
Filing Date: 2011-04-26
Classification: H01L

Abstract:
1. An integrated circuit comprising: a transistor having an active gate structure overlying an active diffusion area formed in a semiconductor substrate; a contact electrically connected to the active diffusion area, the contact comprising a source/drain contact of the active gate structure; a butting diffusion area formed in the semiconductor substrate adjacent to the active diffusion area, wherein the butting diffusion area is doped different from the active diffusion area; wherein the contact overlies the active diffusion area and does not overlie the butting diffusion area; a dummy gate structure at least partially disposed over the butting diffusion area and separated from the active gate structure by a selected distance, the dummy gate structure being electrically coupled to the contact; and a stress layer overlying the transistor producing stress in a channel region of the transistor.