Patent ID: 7365581
Filing Date: 2008-04-29
Classification: H03L

Abstract:
1. A phase locked loop circuit, comprising: a phase-frequency detector to provide a phase difference signal in response to an input signal and a feedback signal; a first charge-pump, coupled to the phase-frequency detector, to provide a first voltage in response to the phase difference signal; a second charge-pump, coupled to the phase-frequency detector, to provide a second voltage in response to the phase difference signal; a loop resistor, coupled to the first charge-pump, to provide a buffered voltage responsive to the first voltage; a voltage regulator, coupled to the loop resistor and the second charge-pump, to provide a current in response to the buffered voltage and second voltage, wherein the voltage regulator includes a bias-generating device to provide a bias current; a voltage-controlled oscillator, coupled to the voltage regulator, to provide the feedback signal in response to the current; and, an interconnect, coupled to the voltage regulator, the first charge-pump, and the second charge-pump, to transfer the bias current, wherein the bias-generating device in the voltage regulator is a MOSFET device, wherein the MOSFET device is a first p-type transistor having a drain coupled to the interconnect and the first p-type transistor having a source coupled a voltage source, wherein the voltage regulator includes: a second p-type transistor having a gate coupled to a gate of the first p-type transistor and the second p-type transistor having a source coupled to the voltage source; a third p-type transistor having a gate coupled to the gate of the second p-type transistor and the third p-type transistor having a source coupled to the voltage source; a fourth p-type transistor having a gate coupled to the gate of the third p-type transistor and the fourth p-type transistor having a source coupled to the voltage source; a fifth p-type transistor having a gate coupled to the gate of the fourth p-type transistor and the fifth p-type transistor having a source coupled to the voltage source; a first n-type transistor having a drain coupled to a drain of the second p-type transistor, the first n-type transistor having a source coupled to ground and the first n-type transistor having a gate coupled to the drain of the second p-type transistor; a second n-type transistor having a drain coupled to a drain of the third p-type transistor, the drain of the second n-type transistor coupled to the gate of the third p-type transistor and the gate of the fourth p-type transistor, the second n-type transistor having a gate coupled to an input, and the second n-type transistor having a source; a third n-type transistor having a drain coupled to a drain of the fourth p-type transistor and a drain of the fifth p-type transistor, the third n-type transistor having a gate coupled to an output and the gate of the third n-type transistor coupled to the drain of the fourth p-type transistor and the drain of the fifth p-type transistor, and the third n-type transistor having a source; and, a fourth n-type transistor having a drain coupled to the source of the second n-type transistor and the source of the third n-type transistor, the fourth n-type transistor having a source coupled to ground and the fourth n-type transistor having a gate coupled to the gate of the first n-type transistor and the drain of the first n-type transistor.