Patent ID: 6897107
Filing Date: 2005-05-24
Classification: H01L

Abstract:
1. A method of forming a DRAM cell array comprising the steps of: (a) forming a plurality of deep trenches in an array portion of a Si-containing substrate having at least a hard mask formed thereon, said plurality of deep trenches being arranged in rows and columns and including at least collar oxide regions formed on sidewalls of the deep trenches and recessed deep trench conductors formed in the deep trenches and defining capacitor electrodes for a DRAM cells; (b) forming buried-strap outdiffusion regions within portions of said sidewalls; (c) forming a nitride liner layer above horizontal surfaces of said deep trench conductors and enclosing exposed sidewalls said collar oxide regions; (d) depositing a top trench oxide (TTO) layer above said formed nitride liner layer; (e) performing a TTO sidewall etch to remove TTO oxide which has been deposited on the vertical sidewalls of the trenches and said collar oxide regions, said nitride liner acting to protect said collar oxide regions from being etched; (f) performing a nitride liner etch to remove portions of the TTO nitride liner which are exposed after TTO oxide removal; (g) forming a vertical MOSFET by growing a gate dielectric on exposed sidewalls of each of said deep trenches and forming gate conductors above said TTO oxide layer within the sidewalls of the deep trenches lined with said gate dielectric, wherein said formed TTO layer having an underlying nitride liner eliminates possibility of TTO dielectric breakdown between said gate conductors and said capacitor electrodes of a DRAM cells.