Patent ID: 6137712
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A memory configuration, comprising:a multiplicity of memory cells each having at least one ferroelectric storage capacitor and a selection transistor connected to said storage capacitor;a plurality of word lines and bit line pairs connected to said memory cells;a reference cell pair connected to and issuing a reference signal on a bit line pair said plurality of bit line pairs;a sense amplifier connected to compare the reference signal with a read signal, and being assigned two bit line pairs said plurality of bit line pairs; anda short-circuiting component for selectively connecting a bit line of one of said bit line pairs to a bit line of another of said bit line pairs, such that the reference signal is applied via said one bit line pair and, at the same time, the read signal is applied via said other bit line pair to said sense amplifier.