Patent ID: 6509197
Filing Date: 2003-01-21
Classification: G01N,G01R,H01J,H01L

Abstract:
A method of testing a semiconductor die, the semiconductor die having a substrate, a first metal layer and a second metal layer formed over the first metal layer, the method comprising:a. forming a first metal test structure in the first metal layer of the semiconductor die such that the first metal test structure has a first electrical connection; b. forming a second metal test structure in the second metal layer of the semiconductor die such that the second metal test structure has a second portion and a second electrical connection to the first metal test structure; and c. determining whether the first metal test structure is intact between the first electrical connection and the second electrical connection by performing a voltage contrast inspection, wherein the second electrical connection is designed to have a significantly different potential during the voltage contrast inspection than the second portion of the second metal structure.