Patent ID: 6604187
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A processor comprising:a first register configured to store a first value indicative of a first process being executed by said processor; a second register coupled to a translation lookaside buffer (TLB) wherein said second register is configured to store an enable indication indicative of whether or not said first value in said first register is enabled for use; and said TLB coupled to said first register, said TLB including at least a first entry, wherein said first entry is configured to store at least: (i) a portion of a first virtual address; (ii) a second value indicative of a second process being executed by said processor at a time that said first entry is loaded with said first virtual address; and (iii) a first indication from a translation table entry corresponding to said first virtual address; wherein said TLB is configured to selectively include, dependent upon said first indication and said enable indication is in an enabled state, a comparison of said first value to said second value in determining if a second virtual address hits in said first entry; and wherein said TLB is coupled to receive a signal indicating that a base address of a translation table is being updated, and wherein said TLB is configured to selectively invalidate said first entry dependent upon said first indication, said enable indication being in a disabled state, and said signal.