Patent ID: 6229337
Filing Date: 2001-05-08
Classification: H03K

Abstract:
A programmable logic device having a plurality pins comprising:a plurality of programmable logic built-in blocks, each programmable logic built-in block having a plurality of input lines and a plurality of output lines; said plurality of output lines comprising a plurality of input feedback lines and a plurality of macro cell feedback lines, each of said programmable logic built-in blocks containing two sub AND arrays, four sub OR arrays, a plurality of macro cells and a plurality of input/output cells;a programmable global interconnect multiplex matrix, coupled to each of said programmable logic built-in blocks, and having a plurality of input lines and output lines; said plurality of input lines of said programmable global interconnect multiplex matrix being coupled to said plurality of input feedback lines and to said plurality of macro cell feedback lines of said programmable logic built-in block;said plurality of output lines of said programmable global interconnect multiplex matrix being coupled to said plurality of said input lines of said logic built-in block; andsaid programmable global interconnect multiplex matrix selectively connecting and disconnecting signals on said plurality of input lines of said programmable global interconnect multiplex matrix to said plurality of input lines of said plurality of programmable logic built-in blocks.