Patent ID: 6188257
Filing Date: 2001-02-13
Classification: G06F,H03K

Abstract:
Power-on-reset logic within an integrated circuit comprising:a power-on-reset cell, including:a power down input connected to a power-down line, wherein when a power-down signal is not placed on the power-down line, the power-on-reset cell is activated so that the power-on-reset cell issues a first reset signal upon a power signal being connected to the integrated circuit, and wherein when the power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not issue the first reset signal upon the power signal being connected to the integrated circuit;a logic block connected to the power-down line and to a system clock, the logic block issuing a second reset signal when the power-down signal is placed on the power-down line and the system clock is active; and,combining means for generating a power-on-reset signal when the power-on-reset cell issues the first reset signal or the logic block issues the second reset signal.