Patent ID: 6831016
Filing Date: 2004-12-14
Classification: H01L

Abstract:
A method to prevent electrical shorts between adjacent metal lines, comprising the steps of:(a) providing a semiconductor substrate; (b) forming a gate oxide, a gate electrode and an etching stop layer, the etching stop layer being formed on the gate electrode; (c) forming a first insulating layer on the semiconductor substrate and the etching stop layer; (d) planarizing the first insulating layer until the etching stop layer is exposed; (e) forming a second insulating layer on the first insulating layer, wherein the second insulating layer has a recess portion; (f) selectively removing the second insulating layer and the first insulating layer to form a pair of dual damascene structures, the recess portion being located between the pair of dual damascene structures; (g) conformally forming a diffusion barrier layer on the second insulating layer and the recess portion; (h) forming a metal layer on the diffusion barrier layer to fill the pair of damascene structures; (i) chemical mechanical polishing the metal layer to form a metal line; and (l) removing the diffusion barrier layer disposed in the recess portion to expose the second insulating layer by etching.