Patent ID: 6574782
Filing Date: 2003-06-03
Classification: G06F

Abstract:
A method of extracting parasitic capacitance from a multi-layer wiring structure comprising:creating, for each wiring layer in said wiring structure, a wiring density map; measuring, for each of a plurality of metal segments in a wiring layer, an area occupied by each of said metal segments; calculating an up area capacitance component for each of said metal segments by multiplying said area occupied by said metal segments by a wiring density, from said wiring density map, of an overlying wiring layer over said metal segments and by a capacitance coefficient of said overlying wiring layer; calculating a down area capacitance component for each of said metal segments by multiplying said area occupied by said metal segments by a wiring density, from said wiring density map, of an underlying wiring layer under said metal segments and by a capacitance coefficient of said underlying wiring layer; and combining said up area capacitance component and said down area capacitance component to form a vertical coupling capacitance component for each of said metal segments.