Patent ID: 6072722
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A method of driving a nonvolatile semiconductor storage device, wherein said nonvolatile semiconductor storage device comprises a memory cell array in which memory cells, each comprised of a floating gate type MOS transistor, are arrayed in a matrix form, each memory cell having a source and a drain formed on a semiconductor substrate and spaced from each other, a tunnel oxide formed on the source and drain and on a channel region disposed between the source and the drain, a floating gate formed on the tunnel oxide, an interlayer insulating film formed on the floating gate, and a control gate formed on the interlayer insulating film, and said nonvolatile semiconductor storage device further comprises word lines each connected with the control gates of the memory cells in respective rows, local bit lines each connected with the drains of the memory cells in respective columns, main bit lines connected with the corresponding local bit lines via respective first MOS transistors, local source lines each connected with the sources of the memory cells in respective columns, and a common source line connected with the local source lines via respective second MOS transistors, said method comprising:(a) in an programming operation in which electrons are injected into the floating gate of a memory cell to be programmed,applying a first voltage to the drain of the memory cell via the corresponding main bit line, the corresponding first MOS transistor, and the corresponding local bit line, and applying a second voltage to the control gate of the memory cell via the corresponding word line to thereby apply the first voltage to the channel region and the source of the memory cell, so that electrons are injected into the floating gate of the memory cell from the drain, the source and the channel region of the memory cell via the tunnel oxide; and(b) in an erasing operation,applying a third voltage to the semiconductor substrate while applying a fourth voltage to the control gate of the memory cell via the corresponding word line so that electrons are extracted from the floating gate to the channel region of the memory cell via the tunnel oxide.