Patent ID: 9059726
Filing Date: 2015-06-16
Classification: G06F,H03M

Abstract:
1. A data processing apparatus comprising: processing circuitry configured to perform a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value, said floating-point value having a significand and an exponent; wherein said convert-to-integer operation uses round-to-nearest, ties away from zero, rounding in which a fractional floating-point value lying between two adjacent integer values is rounded to the nearest adjacent integer value, with a fractional floating-point value lying halfway between two adjacent integer values being rounded to the one of the two adjacent integer values lying furthest away from zero; said processing circuitry comprises intermediate value generating circuitry configured to generate an intermediate value based on said floating-point value, and adding circuitry configured to add a rounding value to the intermediate value to generate a sum value; said processing circuitry is configured to output the integer-valued bits of the sum value as the rounded two's complement integer value; and if said floating-point value has a negative value, then said intermediate value generating circuitry is configured to generate said intermediate value by inverting the bits of the significand of said floating-point value without adding a bit value of 1 to a least significant bit of the inverted value, wherein the rounding value has the same value irrespective of whether the floating-point value has a positive value or a negative value.