Patent ID: 6310811
Filing Date: 2001-10-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell matrix section including memory cells arranged in a first matrix, wherein when one of said memory cells is selected based on an address signal, a read data signal corresponding to a storage data of said selected memory cell is outputted;a reference memory cell matrix section including a plurality of switchable reference memory cells arranged in a second matrix having a structural aspect substantially identical to said memory cell matrix to ensure that a charging speed for said reference memory cell matrix is essentially identical to a corresponding charging speed for said memory cell matrix for each said address, and outputting a reference data signal for said read data signal outputted from said selected memory cell; anda sensing circuit sensing said storage data based on said read data signal from said memory cell matrix section and said reference data signal from said reference memory cell matrix section,wherein said reference memory cell matrix section outputs said reference data signal to said sensing circuit such that, for each said memory cell matrix address, said reference data signal appears substantially synchronous with said data read signal, wherein said reference memory cell matrix section includes:a reference memory cell matrix including said reference memory cells arranged in said second matrix, a selected one of said reference memory cells being connected to a first digit line, and remaining ones of said reference memory cells;a first selector applying a read bias for said selected reference memory cell, and applying a first reference precharge signal for a second reference digit line connected with a first one of said non-selected reference memory cells to provide a correct current path for said reference data signal;a first blank selector transferring said read bias to said first digit line and said first reference precharge signal to said second digit line;a second selector applying a ground voltage and a second reference precharge signal for said reference memory cell matrix; anda second bank selector transferring said ground voltage to a third digit line connected with said selected reference memory cell and said second reference precharge signal to a fourth digit line connected with a second one of said non-selected memory cells, andwherein said reference data signal corresponds to a current flowing through said first digit line, said selected reference memory cell and said third digit line, when said read bias is applied to said selected reference memory cell.