Patent ID: 9069489
Filing Date: 2015-06-30
Classification: G06F

Abstract:
1. An apparatus for accessing a memory, the apparatus comprising: a buffer comprising (i) a first buffer bank configured to receive and store a first plurality of memory access commands for accessing a first memory bank of the memory and (ii) a second buffer bank configured to receive and store a second plurality of memory access commands for accessing a second memory bank of the memory; a first level of arbiters configured to control an order in which memory access commands are output by individual buffer banks, the first level of arbiters comprising (i) a first arbiter configured to control an order in which the first plurality of memory access commands are output by the first buffer bank and (ii) a second arbiter configured to control an order in which the second plurality of memory access commands are output by the second buffer bank, wherein the first buffer bank is configured to receive and store the first plurality of memory access commands in a first order, wherein the first buffer bank is configured to output the first plurality of memory access commands in a second order that is different from the first order, wherein the second buffer bank is configured to receive and store the second plurality of memory access commands in a third order, and wherein the second buffer bank is configured to output the second plurality of memory access commands in a fourth order that is different from the third order; and a second level of arbiter configured to control an order in which the memory access commands are output from the first and second buffer banks to the memory.