Patent ID: 7017010
Filing Date: 2006-03-21
Classification: G11C

Abstract:
1. An integrated circuit device comprising: a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation, where N is a positive integer, wherein the DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme and wherein the DDR integrated circuit memory device further comprises: a pre-decoder that generates a plurality of pre-decoding signals responsive to a 3-bit column address signal; and a memory cell array including at least one memory cell array block for storing the 2N burst length of data, wherein the pre-decoding signals activate at least one column select line that designates the position of the 2N burst length of data in the at least one memory cell array block of the memory cell array.