Patent ID: 6049868
Filing Date: 2000-04-11
Classification: G06F

Abstract:
A processor, comprising:an instruction fetch unit for fetching instructions for processing;an instruction scheduling unit receiving said instructions and issuing said instructions for execution;an execution unit receiving said issued instructions and executing one or more of said instructions;a table for storing instruction trap information, said table having one or more entries, each entry adapted to specify one or more trap vectors relating to a trap condition of one of said instructions, said one or more trap vectors including a front-end trap created before said instruction is executed, and a back-end trap created during or after said one instruction is executed; anda retirement module for retiring each of said instructions upon completion of execution and for determining when a trap handler should be initiated in said processor, said retirement module signaling that the trap handler should be initiated responsive to said instruction trap information to correct said trap condition, said retirement module also determining whether instructions older than a trap-inducing instruction have been retired, and if so, flushing from the processor any instructions younger than said trap-inducing instruction.