Patent ID: 6434674
Filing Date: 2002-08-13
Classification: G06F

Abstract:
A high-speed, multiport memory architecture for use with a processor, comprising:a) a first interface adapted for bi-directional connection to a first external data bus said first external data bus having a first data path width and a first data bus speed, said bi-directional connection being made through a first I/O port, said first interface having a second, bi-directional I/O port configured for bi-directional communication with a first internal data bus, and said first interface comprising a data sourcing controller; b) a second interface adapted for bi-directional connection to a second external data bus, said second external data bus having a second data path width and a second data bus speed, said bi-directional connection being made through a first I/O port, said second interface having a second, bi-directional I/O port configured for bi-directional communication with a second internal data bus, said second interface comprising a data consuming controller; c) a first plurality of bi-directional FIFO buffers each having a first buffer I/O port operatively connected to a first internal data bus and a second buffer I/O port configured for connection to a multiplexer; d) a second plurality of bi-directional FIFO buffers each having a first buffer I/O port operatively connected to a second internal data bus and a second buffer I/O port configured for connection to a multiplexer; e) a multiplexer having a plurality of inputs, each being connected to respective bi-directional FIFO buffers of said first and second plurality of bi-directional FIFO buffers; f) a memory operatively connected to said multiplexer, said memory having a data path width greater than said data path widths of said first external data bus and said second external data bus and a speed greater than said bus speed of said first external data bus and said external data bus; whereby data on said first external data bus is transferred to said second external data bus through: said first interface, said first internal data bus, at least one of said first plurality of bi-directional FIFO buffers, said memory, at least one of said second plurality of bi-directional FIFO buffers, said second internal data bus and said second interface.