Patent ID: 6815752
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A semiconductor memory device comprising:a substrate; a MOS (metal oxide semiconductor) transistor formed in a surface portion of said substrate, wherein said MOS transistor includes a source, a gate, and a drain; a first inter-level dielectric covering said MOS transistor; a capacitor element including: a bottom electrode, a dielectric layer formed on said bottom electrode, and an upper electrode formed on said dielectric layer; a first contact formed through said first inter-level dielectric to electrically connect said bottom electrode to said source, wherein said first contact includes a first metal portion formed of metal; a second contact formed through said first inter-level dielectric to be connected to said drain, wherein said second contact includes a second metal portion formed of said metal, wherein said bottom electrode comprises a polysilicon layer connected to said dielectric layer, and an electrode barrier layer formed between said first metal portion and said polysilicon layer; and a second inter-level dielectric covering said first inter-level dielectric, wherein a hole is formed through said second inter-level dielectric, wherein said electrode barrier layer includes: a bottom barrier portion formed on said metal portion of said first contact, and a side barrier portion connected to said bottom barrier portion, said side barrier portion being formed on a side surface of said hole to extend towards an upper surface of said second inter-level dielectric, wherein said polysilicon layer includes: a bottom electrode portion formed on said bottom barrier portion, and a side electrode portion connected to said bottom electrode portion, said side electrode portion being formed on said side barrier portion, and wherein an end of said side electrode portion is substantially in alignment with said upper surface of said second inter-level dielectric, while an end of said side barrier portion is out of alignment with said upper surface of said second inter-level dielectric, said side barrier portion not reaching said upper surface of said second inter-level dielectric.