Patent ID: 6484289
Filing Date: 2002-11-19
Classification: G11C

Abstract:
A semiconductor memory device having a parallel data test mode, comprising: an array of memory cells arranged in rows and columns, the array of memory cells being divided into a plurality of array portions;a plurality of compare circuits, each compare circuit receiving a plurality of data bits from a different said array portion and generating a compare output, the compare output having a pass indication if the plurality of data bits have the same logic level and having a fail indication if the plurality of data bits do not have the same logic level; a plurality of ripple circuits, each ripple circuit receiving the compare output from a different one of said compare circuits and generating a ripple output having a pass indication and a fail indication responsive to said compare output; and at least one of the plurality of ripple circuits further receiving a ripple output from another of the plurality of ripple circuits, the ripple output of the at least one ripple circuit being in the fail indication if either the received ripple output or the received compare output are in the fail indication.