Patent ID: 6865112
Filing Date: 2005-03-08
Classification: G11C

Abstract:
1. A data writing method used for a semiconductor memory device in which a collective data writing operation is performed using a plurality of memory cell arrays, said data writing method comprising: latching data at each of a plurality of latch circuits connected to a plurality of bit lines provided on the plurality of memory cell arrays, respectively; executing a first data writing operation in parallel for the plurality of memory cells connected to each corresponding single word line, for each of the plurality of memory cell arrays with respect to which the collective data writing operation is performed; verifying the data written in the first data wiring operation, and stopping a data writing operation with respect to a first memory cell array in which writing is completed in all of the memory cells of the plurality of memory cell arrays, at a first time; executing a second data writing operation for a second memory cell array which is different from the first memory cell array of the plurality of memory cell arrays; and verifying the data written by the second data writing operation, and stopping the second data writing operation with respect to the second memory cell array in which writing is completed in all of the memory cells of the plurality of memory cell arrays, at a second time later than the first time.