Patent ID: 6187672
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method for forming an interconnect structure on a semiconductor body, comprising the steps of:(a) depositing a first metal layer on a semiconductor body;(b) depositing a sacrificial layer on the first metal layer, said sacrificial layer having a height;(c) patterning the sacrificial layer and the first metal layer to form separate metal lines with a sacrificial layer cap on said metal lines;(d) depositing a low-k material to fill gaps between said metal lines and to cover the sacrificial layer;(e) removing the low-k material to a level within the height of the sacrificial layer;(f) removing the sacrificial layer;(g) depositing a protective layer to cover the metal lines and the low-k material(h) depositing an insulator on the protective layer;depositing and patterning a photoresist layer on the insulator;(i) creating vias in the insulator;(j) performing a photoresist strip;(k) performing a set clean; and(l) selectively etching the protective layer using an anisotropic etch configured to leave a spacer on a vertical portion of the low-k material in the vias.