Patent ID: 6963956
Filing Date: 2005-11-08
Classification: G06F,G11C

Abstract:
1. A memory device, comprising: a dynamic memory core having memory cells arranged in rows and columns; a plurality of external connections; and interface circuitry coupled to said memory core and coupled to said external connections to receive row operation and column operation information, wherein said interface circuitry is configured to perform data transfers on said external connections in response to said column operation information, wherein said interface circuitry is configured to receive row operation information concurrently with data transfers on said external connections and wherein said interface circuitry is configured to receive column operation information concurrently with corresponding row operation information, the interface circuitry further including a plurality of transport units for assembling operation commands, wherein the transport units are coupled to the external connections and a plurality of control operations units, and the transport units and the control operations units operate substantially concurrently.