Patent ID: 6269029
Filing Date: 2001-07-31
Classification: G11C

Abstract:
A semi-conductor memory device comprising:global data bus lines and single data strobe lines and reference comparing voltage lines with the number being identical to the number of data being coupled between a bank and an input, output interface circuit part;a clamping means connected every each line for fixing the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines to a regular level of an electric potential;a first to a third driving means connected to every ends of both sides of the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines, for controlling a drive of each lines by a combination of an input, output enable signal and a data output strobe signal and each data signal;a first receiving means connected to ends of both sides of the data strobe lines, for receiving a strobe signal carried on the data strobe lines and comparing it with a reference comparing voltage and thereby outputting the data strobe signal;a second receiving means connected to respective ends of both sides of the numerous global data bus lines, for comparing each data signal with a reference comparing voltage signal and outputting each data value under a control of a data strobe signal being outputted from the first receiving means.