Patent ID: 6262593
Filing Date: 2001-07-17
Classification: H03K

Abstract:
A semi-dynamic, m-of-n threshold gate with hysteresis comprising:a signal node;a GTN circuit driving the signal node to a first predetermined voltage when all of a plurality of threshold gate input signal lines are in a NULL state;a GTD circuit driving the signal node to a second predetermined voltage when at least a threshold number of threshold gate input signal lines is in an ASSERTED state said threshold number being less than the total number of input signal lines;an output circuit driving a threshold gate output signal line to NULL and ASSERTED states in response to voltage states of the signal node; anda feedback circuit driving the signal node to a predetermined voltage state in response to the state of the threshold gate output signal line so as to hold the threshold gate output signal in a prior NULL or ASSERTED state when at least one, but less than the threshold number, of threshold gate input signal lines is in the ASSERTED state, wherein the GTN network comprises:a switching circuit generating a switching signal in response to a plurality of input signals derived from threshold gate input signals; anda switching transistor driving the signal node to a voltage reference in response to the switching signal.