Patent ID: 6417037
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A method for fabricating an integrated circuit device comprising:providing an isolation region separating a first active area from a second active area in a semiconductor substrate; forming a first gate dielectric layer overlying said semiconductor substrate in said first and second active areas wherein said first gate dielectric layer has a first electrical thickness; annealing said first gate dielectric layer using one of the group containing NH3 and N2O to form a nitrogen-rich silicon oxynitride layer; removing said first gate dielectric layer in said second active area; forming a second gate dielectric layer in said second active area wherein said second gate dielectric layer has a second electrical thickness greater than said first electrical thickness and wherein said second gate dielectric layer is nitrided to form an oxygen-rich silicon oxynitride layer; depositing a polysilicon layer overlying said first and second gate dielectric layers; patterning said polysilicon layer and said first and second gate dielectric layers to form a first gate transistor in said first active area having said first gate dielectric layer thereunder and to form a second gate transistor in said second active area having said second gate dielectric layer thereunder; and completing said integrated circuit device.