Patent ID: 7867844
Filing Date: 2011-01-11
Classification: H01L

Abstract:
1. A method of forming a NAND cell unit, comprising: forming a plurality of spaced apart gate stacks over a semiconductor substrate; at least one of the gate stacks being a select gate stack, and at least two of the gate stacks being string gate stacks; the at least one select gate stack comprising a first gate dielectric material, a first gate material over the first gate dielectric material, a first electrically insulative material over the first gate material, and a sacrificial material over the first electrically insulative material; the string gate stacks comprising a second gate dielectric material, a second gate material over the second gate dielectric material, a second electrically insulative material over the second gate material, and the sacrificial material over the second electrically insulative material; removing the sacrificial material from the at least one select gate stack and from the string gate stacks; etching through the first electrically insulative material to the first gate material; and after etching through the first electrically insulative material, forming a conductive material over the at least one select gate stack and over the string gate stacks, the conductive material physically contacting the first gate material and being separated from the second gate material by the second electrically insulative material.