Patent ID: 6567773
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A method for analyzing electrical noise in an integrated circuit fabricated in a silicon-on-insulator process, the method comprising the steps of:a) describing an electrical circuit at a transistor level in a data model, said circuit having at least one transistor, b) determining at least one input voltage for said transistor, said input voltage selected to precondition said circuit for a worse case response to electrical noise; c) selecting a body voltage for said transistor, wherein said body voltage is one that is within normal operational bounds of said transistor and affects a threshold voltage for said transistor such that the said circuit is at its most sensitive state with respect to electrical noise; d) determining if said transistor is in an off mode while said circuit is at its most sensitive state with respect to electrical noise, e) determining if said transistor is susceptible to a parasitic bipolar leakage current; f) simulating the application of a current source across a source and drain node of said transistor in said off mode and is susceptible to said parasitic bipolar leakage current; g) repeating steps (b) through (f) for each of a plurality of transistors in said circuit; h) presenting said circuit to a simulator for a simulation, i) simulating the application of said input voltage to an input of each of said transistors in said circuit; j) measuring an output voltage of said circuit at an output node; k) adjusting said input voltage to simulate electrical noise on said input of said transistor; l) repeating steps (i) through (k) for each of said plurality of transistors in said circuit, m) repeating steps (b) through (l) for each of a plurality of input voltages for each of said plurality of said transistors in said circuit, and n) determining said circuit's worse case response to electrical noise.