Patent ID: 6306700
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate, comprising steps of:forming an oxide layer on a substrate;forming an N well in the substrate by using a mask on one upper-half portion of the substrate;sequentially forming a pad oxide layer and a silicon nitride layer on the substrate;defining said pad oxide layer and said silicon nitride layer to partially expose the substrate;forming a P well opposite to said N well in the substrate by using a mask on said N well in the substrate;using a mask and forming a plurality of N-field regions as drift regions which respectively cover a portion of a channel for an NMOS transistor in said P well and a plurality of N-field regions as isolation regions which respectively neighbor with a source/drain region for a PMOS transistor in said N well;forming a plurality of field oxide regions on exposed portions of the substrate;using a mask and forming an N.sup.- type doped region between two said field oxide regions for enclosing the source/drain region for the NMOS transistor in said P well;using a mask and forming a plurality of P-field regions in said N well as drift regions which respectively cover a portion of a channel for a PMOS transistor in said N well and underlay said field oxide regions adjoining the channel, and a plurality of P-field regions in said P well as isolation regions which respectively underlay said field oxide regions adjoining the source/drain region;forming a gate oxide layer on the substrate;forming a polysilicon gate on said gate oxide layer, said polysilicon gate crossing the channel and a portion of said field oxide regions adjoining thereto, respectively on said P well and said N well;using a mask and forming an N.sup.+ type doped region in said N-type doped region as the source/drain region for the NMOS transistor in said P well; andusing a mask and forming a P.sup.+ type doped region between two said field oxide regions in said N well as the source/drain region for the PMOS transistor in said N well.