Patent ID: 8513813
Filing Date: 2013-08-20
Classification: G11C,H01L

Abstract:
1. A microelectronic package, comprising: a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; a microelectronic element having memory storage array function, the microelectronic element having a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face, a plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the terminals electrically connected with the substrate contacts and including first terminals disposed at locations within first and second parallel grids, each grid disposed on a respective side of an axis, the first terminals in each grid being configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, the first terminals having signal assignments, wherein the signal assignments of the first terminals in the first grid are symmetric about the axis with the signal assignments of the first terminals in the second grid, such that each first terminal of the first grid which is configured to carry address information is configured to carry the same address information as each corresponding first terminal of the second grid at a position symmetric about the axis with respect to such first terminal.