Patent ID: 6507227
Filing Date: 2003-01-14
Classification: G01R,H02M

Abstract:
A circuit for monitoring the current delivered to a load through an output node of a power transistor comprising:a sense transistor that produces, on a sensing node, a scaled-down replica current of the current being delivered through the power transistor; and a disturbances attenuating circuit connected to the sense transistor and the power transistor and including a differential stage including a first pair of identical transistors coupled to the output node and to the sensing node, respectively, and having control terminals connected in common, and a load current mirror including a second pair of identical transistors coupled to a reference voltage, a first stage, a second stage and a third stage referenced to the reference voltage, the respective input nodes of which are connected in common to an output node of the differential stage, the first stage comprising a first transistor identical to the second pair of transistors of the load current mirror, and a diode-connected load transistor identical to the first pair of transistors of the differential stage and forming with them a current mirror referenced to the sensing node, the second stage comprising a second transistor coupled to the sensing node and having a size that is a multiple of the size of the first transistor of the first stage, and the third stage comprising a third transistor identical to the first transistor of the first stage and delivering a current signal proportional to the current being delivered to the load.