Patent ID: 8129840
Filing Date: 2012-03-06
Classification: H01L

Abstract:
1. A semiconductor package comprising: a substrate including a plurality of pads, the pads having a pitch therebetween; a protection layer formed on the substrate and having a plurality of openings to expose the pads at a height lower than a height of the protection layer, the openings having central axes; and a plurality of bumps uniformly disposed at a pitch on an entire region of the substrate regardless of an arrangement of the plurality of pads, the bumps having central axes such that two adjacent first bumps of the plurality of bumps are electrically connected to a pad at the lower height of the pad and at least one of the two adjacent first bumps overlaps and extends beyond a width of the pad and overlaps the protection layer, wherein the pitch between the bumps is smaller than the pitch between the pads, and wherein a central axis of at least one of the bumps disposed within an opening that exposes a pad is not aligned with a central axis of the opening.