Patent ID: 8935645
Filing Date: 2015-01-13
Classification: G06F,H03K

Abstract:
1. A device comprising: a logic block, wherein the logic block includes a plurality of logic elements; configuration logic associated with the logic block, wherein the configuration logic is operable to identify values stored in the plurality of logic elements, and wherein the configuration logic includes a first group of configuration cells in an array; a first memory cell storing a first mode flag value, wherein the mode flag value is operable to identify whether the configuration logic stores a user defined state or a design state, wherein the configuration logic is excluded from a data verification and correction process in response to the configuration logic storing a user defined state, wherein the configuration logic is included in the data verification and correction process in response to the configuration logic storing a design state, and wherein the first memory cell is positioned adjacent to the first group of configuration cells; and a second memory cell storing a first enable read flag value, wherein the enable read flag value is operable to identify whether values stored in the configuration logic are to be read out or whether a known state is to be read out during the data verification and correction process, wherein the second memory cell is positioned adjacent to the first group of configuration cells, wherein the first memory cell is positioned on a first side of the configuration logic, wherein the second memory cell is positioned on a second side of the configuration logic, and wherein the first side is opposite the second side such that a left-to-right or right-to-left setting of values switches the logic block between a look-up-table (LUT) mode and a random access memory (RAM) mode.