Patent ID: 6218866
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A semiconductor device for the prevention of a floating gate condition on an input node of a MOS logic circuit, the semiconductor device comprising:a semiconductor substrate of a first conductivity type having an active area on its surface; anda vertically integrated pinch resistor formed in the semiconductor substrate including:a deep well region of a second conductivity type disposed below the active area of the semiconductor substrate;a first surface well region of the second conductivity type disposed on the semiconductor substrate, the first surface well region circumscribing the deep well region and the active area of the semiconductor substrate;a narrow channel region of the first conductivity type disposed in the semiconductor substrate, the narrow channel region separating the deep well region from the first surface well region;a first contact region disposed in the first surface well region and capable of electrically connecting the first surface well region to an input node of the MOS logic circuit;a second contact region disposed in the active area and capable of electrically connecting the active area to the input node of the MOS logic circuit; anda third contact region disposed in the semiconductor substrate and capable of electrically connecting the semiconductor substrate to ground;whereby, the input node of the MOS logic circuit can be electrically connected to ground and therefore prevented from acquiring a floating gate condition.