Patent ID: 6570208
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A memory cell array comprising:a plurality of memory cells formed in an array portion of a Si-containing substrate which are arranged in rows and columns, each memory cell including a vertical metal oxide semiconductor field effect transistor (MOSFET) having exposed gate conductor regions and two gates formed on opposing sidewalls of said MOSFETs, wherein one of the opposing sidewalls also includes a confined buried-strap; a plurality of wordlines overlaying said vertical MOSFETs and in contact with said exposed gate conductor regions, said wordlines being arranged in said column direction; a plurality of bitlines that are orthogonal to said wordlines; and trench isolation regions formed adjacent to said rows of memory cells, wherein said trench isolation regions have a depth that is deeper than a depth of abutting bitline diffusion regions.