Patent ID: 7542332
Filing Date: 2009-06-02
Classification: G11C

Abstract:
1. A memory device, comprising: a memory cell including an inverter pair and a pass transistor pair, wherein the inverter pair and the pass transistor pair configure a stacked-type memory cell structure having thin film poly crystalline silicon transistor which comprises an upper gate on a thin film layer, and which structure is stacked over a peripheral circuit; and the pass transistor pair is controlled by a word line pair; a memory segment wherein a bit line pair is connected to a memory cell array including a plurality of memory cell, a segment write circuit including a write transfer transistor pair, and a segment pre-charge circuit including a pre-charge transistor pair, and one of bit lines is connected to a segment read circuit; and the segment read circuit including a read transistor and a select transistor, wherein the read transistor receives one of bit line voltage and the read transistor is connected to the select transistor serially, where the read transistor serves as amplifying portion of an amplifier and the select transistor is connected to a block read line; a memory block including at least a memory segment and at least a block read circuit; and the block read circuit wherein a load device is connected to the block read line through a feedback transistor, such that the amplifier is composed of the load device and the read transistor of the segment read circuit; and a current mirror is connected to the load device to receive output of the amplifier and the output of the current mirror is stored to a cross coupled inverter latch; and first pre-charge transistor is connected to the block read line, second pre-charge transistor is connected to the load device, and third pre-charge transistor is connected to the current mirror; and the feedback transistor is controlled by the output of the cross coupled inverter latch; and the output of the cross coupled inverter latch is connected to gate of an output transfer transistor which is connected to output of a tri-state inverter and input of a read inverter; and the read inverter generates a read output; a read path including multiple buffers to transfer the read output of the block read circuit; a latch circuit storing the read output through the read path; a latch control circuit generating a locking signal to lock the latch circuit.