Patent ID: 6448799
Filing Date: 2002-09-10
Classification: G01R

Abstract:
A timing adjustment method for a semiconductor IC tester, which has a plurality of drive-only pins each drive-only pin having driver means but having no comparator means, the method comprising the steps of:a first step of connecting a comparator means to an output end of the driver means of each of the plurality of drive-only pins, one after another, by selection means, a second step of carrying out a signal judgment system deskew on each of said plurality of drive-only pins each having the driver means connected to the comparator means by the selection means, a third step of connecting the comparator means to the output end of the driver means of each of the plurality of drive-only pins, one after another, by the selection means, a fourth step of carrying out a signal supply system deskew to each of said plurality of drive-only pins each having the driver means connected to the comparator means according to a result of said second step of carrying out the signal judgment system deskew.