Patent ID: 6541338
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A method of manufacturing a flash memory Electrically-Erasable Programmable Read-Only Memory (EEPROM) device having a low energy source implant and a high energy VSS connection implant such that the intrinsic source defect density is reduced and the VSS resistance is low, wherein the EEPROM includes a multitude of field effect transistor memory cells each having a source, a drain, a gate and a substrate, the method comprising:(a) forming multiple gates on a substrate defining drain regions and source regions associated with each of the multiple gates; (b) forming a first source mask exposing the source regions and portions of the gates; (c) implanting the exposed source regions with n dopant ions; (d) removing the first source mask; (e) forming a second source mask exposing regions between adjacent source regions and masking drain regions; (f) implanting the exposed regions between adjacent source regions with n+ ions; and (g) removing the second source mask.