Patent ID: 9208853
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A memory cell circuit for storing data, comprising: a pair of cross-coupled inverters for storing states of the memory cell circuit; a plurality of access devices coupled to the pair of cross-coupled inverters, the plurality of access devices to provide access to the pair of cross-coupled inverters; and a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices coupled to the pair of cross-coupled inverters, the set of electrically inactive PMOS devices in combination with a portion of the pair of cross-coupled inverters to enable a continuous p-type diffusion layer for the memory cell circuit, wherein a gate of a first electrically inactive PMOS device is coupled to a gate of a second electrically inactive PMOS device, wherein the first electrically inactive PMOS device is coupled to an access device of the plurality of access devices.