Patent ID: 6181179
Filing Date: 2001-01-30
Classification: G01R,H03K

Abstract:
A scan flip-flop circuit comprising:a first master latch for latching a data input signal and outputting the data input signal to a first output terminal in a normal operation mode;a second master latch for latching a scan input signal and outputting the scan input signal to a second output terminal in a scan test mode;a slave latch for latching an output from said first master latch that is input to a first input terminal, thereby outputting the output to a third output terminal in the normal operation mode, and latching an output from said second master latch that is input to a second input terminal, thereby outputting the output to the third output terminal in the scan test mode, said slave latch comprising an OR logic circuit for logically ORing an output from said third output terminal with a SET signal for setting an output state of said slave latch;first switch means for disconnecting the first output terminal of said first master latch from the first input terminal of said slave latch in the scan test mode;second switch means for disconnecting the second output terminal of said second master latch from the second input terminal of said slave latch in the normal operation mode; andthird switch means which is connected between the first and second input terminals of said slave latch, connects the second output terminal of said second master latch to the first input terminal via the second input terminal of said slave latch upon ON operation in the scan test mode, and disconnects the second output terminal of said second master latch from the first input terminal of said slave latch upon OFF operation in the normal operation mode.