Patent ID: 7117140
Filing Date: 2006-10-03
Classification: G03F

Abstract:
1. A method of evaluating the exposure property of data to a wafer in which pattern data for the production of a photomask, including design data designed for a circuit of a semiconductor device and data in which OPC is applied to design data, are used as pattern data for an object of a process and the exposure property of data to a wafer in case of the production of a photomask of the object of the process is evaluated in a data stage, without producing the photomask from pattern data for the object of the process, wherein the method comprises the steps: performing oversize processing and undersize processing to pattern data of the object of the process by figure operation for all pattern data within a range of errors of the production in the specification of the production of a photomask; carrying out wafer exposure simulation using a simulation model provided in advance as a reference for original pattern data of the object of the process, oversize data in which oversize processing is given to the pattern data and undersize data in which undersize processing is given to the pattern data under conditions of a wafer exposure of a zero defocus or under the respective conditions of a wafer exposure of a zero defocus, a given value minus defocus and a given value plus defocus and; evaluating the exposure property of the data for the wafer from the results of the wafer exposure simulation, and wherein the simulation model is comprised of a group of dimension data obtained by using a test photomask for a test produced on the basis of test pattern data, carrying out the exposure of data to the wafer under conditions of a zero defocus, or under respective conditions of a zero defocus, a given value minus defocus and a given value plus defocus, measuring dimensions of the patterns transferred to the wafer and by relating dimension data on the test pattern data, dimension data on the photomask and dimension data on patterns on the wafer at the corresponding positions with each other for the respective conditions of the wafer exposure.