Patent ID: 6104626
Filing Date: 2000-08-15
Classification: G11C

Abstract:
An analog value memory circuit, comprising:an analog memory circuit including a plurality of memory cells each including a switch element having a terminal connected to a corresponding row line and a memory capacitor connected to a first terminal of said switch element, said memory cells being arranged in a matrix of u columns and v rows, u and v being natural numbers;v row switches arranged for the individual rows and each connected at a terminal thereof to a common input/output node and at a second terminal thereof to a terminal of the corresponding row line;a first scanning circuit for outputting column selection signals for i columns to drive the switch elements of the memory cells for individual columns, i being equal to or larger than 1 but equal to or smaller than u;a second scanning circuit for outputting row selection signals for j rows to drive the switch elements of the memory cells and to drive said row switches for the individual rows, j being equal to or larger than 1 but equal to or smaller than v; anda clock generation circuit for supplying a same clock signal directly to said first and second scanning circuits; wherein, the numbers u and v of said first and second scanning circuits being set so as to not be equal to one another and to have no common divisor other than 1.