Patent ID: 6183122
Filing Date: 2001-02-06
Classification: G06F

Abstract:
In a digital multiplier for multiplying a multiplier by a multiplicand to provide a product wherein said multiplier is parsed on a group basis and each of said groups is decoded to generate a coefficient which is applied to each of a like plurality of copies of the multiplicand to form a first plurality of factored multiplicands, and said factored multiplicands are added together to produce the product, the improvement comprising:a) adding said factored multiplicands while including an additional two bits for at least a second plurality of said factored multiplicands such that the number of individual adder circuits, each having up to three input terminals and up to two output terminals, used for adding together two of said factored multiplicands does not exceed one less than the number of bits of said multiplicand, the first bit of said two bits being the inverse of the sign bit of the factored multiplicand, and the second bit of said two bits being a logic 1, wherein said first bit is placed in the next most significant bit position of the sign bit of the factored multiplicand, and said second bit is placed in the next most significant bit position of said first bit; andb) adding a logic 1 to the sum of said factored multiplicands, said additional logic 1 placed in the bit position corresponding to the least significant sign bit position of said plurality of factored multiplicands.