Patent ID: 6927957
Filing Date: 2005-08-09
Classification: H01L

Abstract:
1. An ESD bus clamp in an integrated circuit, said ESD bus clamp comprising: an inverter having an input and an output; a bipolar transistor having a base, an emitter, and a collector, said base being connected to said output of said inverter, said emitter being connected to a ground of said integrated circuit, said collector being directly connected to a power bus of said integrated circuit; a resistor coupling said input of said inverter to said power bus; a capacitor coupling said input of said inverter to said ground; wherein said bipolar transistor shunts current to said ground when an ESD discharge causes a voltage level on said power bus to increase by approximately 1.0 volt, wherein said ESD bus clamp limits an approximately 2.0 kilovolt discharge to approximately 5.0 volts.