Patent ID: 6989583
Filing Date: 2006-01-24
Classification: H01L

Abstract:
1. A semiconductor device containing a multi-layered wiring structure formed on a semiconductor substrate, the structure including at least two wiring layers formed in an interlayer insulation layer, and each of the wiring layers including a metal wiring made of one of Cu and a Cu alloy; wherein the multi-layered wiring structure comprises: a lower wiring layer formed under the interlayer insulation layer; a via buried in the interlayer insulation layer and connected between an upper wiring layer and a first damaged region formed on the lower wiring layer; and a dummy via buried in the interlayer insulation layer, the dummy via being not connected to the upper wiring layer but connected to a second damaged region formed on the lower wiring layer, wherein voids are generated at the second damaged region in the lower wiring layer of Cu or Cu alloy to cause a contact defect between the dummy via and the lower wiring layer.