Patent ID: 7226634
Filing Date: 2007-06-05
Classification: C25D,H05K

Abstract:
1. A method for designing a plated pattern in a printed wiring board to prevent variance of plating areas when a pattern-providing plating film is formed at a predetermined thickness on a substrate, the method comprising: creating surface data having a same size as that of a plating area of the substrate to be plated; dividing the created surface data in a plurality of zones having a same area, each zone corresponding to surface data of a divided size, by means of a separate picture layer; punching the surface data having the same size as that of the plating area, by the surface data of the divided size; punching the surface data of the plating area of the substrate by the punched surface data obtained; measuring a plating area of each of the punched zones; comparing the measurement values of the plating areas and judging whether variance exists in the plating area in each punched zone; and checking wiring patterns of respective punched zones when variance is judged as existing and conducting a design change of patterns contained in the respective punched zones to eliminate the variance, thereby providing a balanced plating area as a whole in the printed wiring board.