Patent ID: 7944064
Filing Date: 2011-05-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate which has an upper surface including a plurality of semiconductor device formation regions and at least one alignment mark formation region having the same planar size as a planar size of each of the semiconductor device formation regions; a plurality of connection pads formed in each of the semiconductor device formation regions; an insulating film formed on the upper surface of the semiconductor substrate in all of the semiconductor device formation regions, including on the connection pads except for respective central portions thereof, and in the at least one alignment mark formation region; a plurality of post electrodes which are formed on an upper side of the insulating film in each of the semiconductor device formation regions and each of which is electrically connected to at least a corresponding one of the connection pads; at least one alignment post electrode which is formed on an upper side of the insulating film in the alignment mark formation region, and which is smaller in number than the post electrodes formed in each semiconductor device formation region; and a sealing film which is made from an organic resin and which is formed between the post electrodes in each of the semiconductor device formation regions and on an outside of the alignment post in the alignment mark formation region; wherein an upper surface of the alignment post electrode is exposed to outside and is flush with an upper surface of the sealing film; and wherein the semiconductor substrate includes a plurality of non-semiconductor device formation regions around the alignment mark formation region, and each of the non-semiconductor device formation regions has the same planar size as the planar size of each of the semiconductor device formation regions and does not have post electrodes formed thereon.