Patent ID: 7683677
Filing Date: 2010-03-23
Classification: G11C

Abstract:
1. A sample-and-hold amplification circuit, comprising: an amplifier having an input terminal and an output terminal; a first sample-and-hold unit coupled to the input terminal and the output terminal, for performing a sampling operation and a holding operation; and a second sample-and-hold unit coupled to the input terminal and the output terminal, for performing a sampling operation and a holding operation; wherein the first sample-and-hold unit performs the sampling operation and the holding operation according to a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; wherein active periods of the first and second clock signals begin at the same time, and the active period of the first clock signal is longer than the active period of the second clock signal; wherein active periods of the third and fourth clock signals begin at the same time, and the active period of the fourth clock signal is longer than the active period of the third clock signal; wherein the fourth clock signal and the first clock signal are non-overlapping; wherein when the first sample-and-hold unit is arranged to perform the sampling operation, the second sample-and-hold unit performs the holding operation; and wherein when the first sample-and-hold unit is arranged to perform the holding operation, the second sample-and-hold unit performs the sampling operation.