Patent ID: 9189048
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. An integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising: a digital interface; a digital input connected to the digital interface; a configuration memory configured to store configuration information defining a configuration of the IC; primary operation circuitry connected to the digital interface and configured to perform one or more primary tasks, the primary operation circuitry configured for selectively having at least a portion of its power removed during a low power mode; and a first power manager connected to the primary operation circuitry and the digital input, the first power manager configured to receive a set of one or more predefined digital signals over the digital input during the low power mode, change the information stored in the configuration memory, and initiate a power up of the primary operation circuitry in response to the set of predefined digital signals; wherein the primary operation circuitry includes a second power manager configured to be powered down during the low power mode, and further configured to be powered up and perform power up operations on the primary operation circuitry in response to a signal from the first power manager.