Patent ID: 9040315
Filing Date: 2015-05-26
Classification: B24B,H01L

Abstract:
1. A method for planarizing semiconductor devices comprising: forming at least one patterned metal layer on a substrate; providing a material layer having a first area and a second area on the at least one patterned metal layer and the substrate, wherein there is a step height existing between the first area and the second area; performing a first polishing process on the material layer, wherein the first polishing process has a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area; and performing a second polishing process on the material layer, wherein the second polishing process has a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area, and the second selection ratio is greater than the first selection ratio; wherein the second polishing process comprises a second slurry comprising a buffer reagent comprising a re-dispersible polymer.