Patent ID: 7612365
Filing Date: 2009-11-03
Classification: H01L

Abstract:
1. A semiconductor device comprising at least one n-channel MOS field effect transistor and a substrate, the substrate comprising silicon, each of the n-channel MOSFETs comprising: a first layer comprising germanium formed over the substrate, the first layer having a thickness less than a first thickness at which misfit dislocations form in the first layer, the first layer having a first lower interface in-plane lattice spacing matched with a substrate interface lattice spacing characteristic of an interface region of the substrate; a second layer comprising silicon formed over the first layer, the second layer having a second layer thickness, the second layer having a second lower interface in-plane lattice spacing matched with a first layer upper interface in-plane lattice spacing characteristic of an upper interface of the first layer; and a gate dielectric layer on the second layer and separating the second layer from a gate electrode, wherein a concentration of germanium in the first layer is greater than a concentration of germanium in the second layer, the first layer and the second layer having a lateral extent along one direction such that the second layer exhibits in-plane tensile strain over all of the lateral extent through edge relaxation.