Patent ID: 7379351
Filing Date: 2008-05-27
Classification: G11C

Abstract:
1. A programming method for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission transistors for providing predetermined voltages to the memory cells, said method comprising: a primary programming process which includes providing a first program voltage to a selected memory cell to program the selected memory cell; a verify read process which includes reading the selected memory cell to verify a programmed status of the selected memory cell resulting from the primary programming process; and a secondary programming process which includes providing a second program voltage to the selected memory cell so as to reprogram the selected memory cell after the verify read process, wherein, during the verify read process, the transmission transistors are continuously gated by a boosted voltage generated during the primary programming process, the boosted voltage having a voltage level which is sufficient to provide the first and second program voltages to the memory cell.