Patent ID: 6194969
Filing Date: 2001-02-27
Classification: G06F

Abstract:
A system for providing redundant clock signals, comprising:a first clock source configured to provide a first clock signal; anda second clock source configured to provide a second clock signal, wherein said second clock source includes:a phase detector coupled to receive said first clock signal and said second clock signal, wherein said phase detector is configured to output an output signal indicative of a difference between said first clock signal and said second clock signal,a loop filter coupled to receive said output signal indicative of said difference, wherein said loop filter is configured to output a first control signal,a voltage controlled oscillator (VCO) coupled to receive said first control signal, wherein said VCO is configured to output said second clock signal in phase with said first clock signal, and wherein said VCO is further coupled to selectively receive a reference control signal in place of said first control signal; anda switch coupled to selectively provide the first control signal to the VCO.