Patent ID: 6403459
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A process for fabricating a semiconductor integrated circuit device, comprising the steps of:(a) forming a first insulating film over a semiconductor substrate; (b) polishing the surface of said first insulating film; (c) performing an etching in order to form first concave portions in said first insulating film; (d) forming a first conductive film over a surface of said first insulating film and an inside of said first concave portions; (e) forming a second conductive film on said first conductive film; (f) polishing said first and second conductive films to form a first conductive member and a second conductive member in said first concave portions; (g) forming a second insulating film on said second conductive member; (h) forming a third insulating film including a fluid insulating film having self fluidity over said second insulating film and over said first concave portions such that a surface of said third insulating film is planarized; (i) forming a second concave portion in said third insulating film; (j) forming a third conductive film in said second concave portion and over said third insulating film; (k) forming a fourth conductive film on said third conductive film in said second concave portion; and (l) polishing said third and fourth conductive films to form a third conductive member and a fourth conductive member in said second concave portion.