Patent ID: 6429096
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit on a circuit side, the semiconductor device wafer further comprising a back surface that includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit is formed; working the semiconductor device wafer from the back surface to diminish a first thickness of the semiconductor device wafer to at least until the plurality of flaws are removed so as to form a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the thinned wafer; and forming in the hole a wiring plug to join the front and back surfaces of the first coated wafer.