Patent ID: 9077326
Filing Date: 2015-07-07
Classification: G01S,H03K,H03M,H04B,H04L

Abstract:
1. A continuous time counter comprising: a plurality of counter inputs; and a plurality of adding stages, each adding stage comprising a stack of one or more outputs, and each counter input providing an input to an adding stage, wherein the adding stages are arranged successively from a first adding stage to a last adding stage, wherein the first adding stage is arranged to set its single output to a first output value, wherein each succeeding adding stage is arranged to take the outputs from the immediately preceding stage and when the appropriate counter input for the adding stage represents a count, the adding stage is arranged to add a new output at the bottom of the stack and when the counter input represents no count, the adding stage is arranged to add a new output at the top of the stack, and wherein the counter is arranged to apply a compensating delay to each of its inputs to compensate for the propagation delay through the adding stages.