Patent ID: 8835209
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method, comprising: forming a first gate electrode structure on a first active region of a semiconductor device and a second gate electrode structure on a second active region of said semiconductor device, said first and second gate electrode structures each comprising a gate electrode material and a dielectric cap layer formed above said gate electrode material; forming a sidewall spacer structure adjacent to sidewalls of at least said first gate electrode structure, said sidewall spacer structure comprising a spacer element and a liner layer formed between said spacer element and said sidewalls of said first gate electrode structure; forming a first hard mask layer above said first and second gate electrode structures; forming a first spacer structure from said first hard mask layer adjacent to said sidewalls of said first gate electrode structure while preserving said first hard mask layer above said second gate electrode structure and said second active region, said first spacer structure covering said spacer element of said sidewall spacer structure; forming a first semiconductor alloy in said first active region by using said first spacer structure and said preserved first hard mask layer as a first mask; forming a second hard mask layer above said first and second gate electrode structures and said first and second active regions; forming a second spacer structure from said second hard mask layer adjacent to sidewalls of said second gate electrode structure while preserving said second hard mask layer above said first gate electrode structure and said first active region; and forming a second semiconductor alloy in said second active region by using said second spacer structure and said preserved second hard mask layer as a second mask.