Patent ID: 8748239
Filing Date: 2014-06-10
Classification: H01L

Abstract:
1. A method of fabricating a gate, the method comprising: forming a device isolation layer in a substrate, a top surface of the device isolation layer being higher than a top surface of the substrate; sequentially forming a first layer and a second layer on substantially an entirety of the substrate including the device isolation layer, the second layer having a stepped surface on the substrate, the stepped surface overlapping the device isolation layer; planarizing the second layer such that the stepped surface is removed; and forming a plurality of stacked structures spaced apart on the substrate, after planarizing the second layer by patterning the first layer and the second layer to form a plurality of patterned first layers and a plurality of patterned second layers, at least one of the plurality of patterned second layers being on the device isolation layer, a top surface of each of the plurality of patterned second layers being arranged at a same distance from the substrate.