Patent ID: 9018047
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A method for manufacturing a memory device, comprising: forming a plurality of layers of a first conductive material separated by insulating material, on an integrated circuit substrate; etching the plurality of layers to define a plurality of stacks of conductive strips, the stacks including at least a bottom plane (GSL) of conductive strips, a plurality of intermediate planes (WLs) of conductive strips, and a top plane of conductive strips (SSLs); forming a memory layer including charge storage structures on side surfaces of conductive strips in the plurality of stacks, the memory layer contacting side surfaces of the plurality of conductive strips; forming a layer of a second conductive material over and having a surface conformal with the memory layer on the plurality of stacks; etching the layer of second conductive material to define a plurality of bit line structures, and at least one reference line structure, wherein the bit line structures are arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, including inter-stack semiconductor body elements between the stacks, and linking elements over the stacks connecting the inter-stack semiconductor body elements, and wherein the at least one reference line structure is arranged orthogonally over the plurality of stacks, including inter-stack vertical conductive elements between the stacks and linking elements over the stacks connecting the inter-stack vertical conductive elements; and forming sidewall silicide formations on side surfaces of a side of at least one of the conductive strips in the stacks opposite a second side of the at least one of the conductive strips, wherein on the side surfaces of the second side the memory layer is formed.