Patent ID: 6104417
Filing Date: 2000-08-15
Classification: G06F,G06T,G09G

Abstract:
A computer system comprising:a memory controller;a graphics rendering engine coupled to said memory controller;a CPU coupled to said memory controller;an image processor coupled to said memory controller;a data compression/expansion device coupled to said memory controller;an input/output device coupled to said memory controller;a graphics back end device coupled to said memory controller;a system memory, coupled to said memory controller via a high bandwidth data bus, said system memory providing read/write access, through said memory controller, for memory clients including said CPU, said input/output device, said graphics back end device, said image processor, said data compression/expansion device, said rendering engine, and said memory controller, wherein said memory controller is the interface between said memory clients and said system memory; andtranslation hardware for mapping virtual addresses of pixel buffers to physical memory locations in said system memory wherein said pixel buffers are dynamically allocated as tiles of physically contiguous memory.