Patent ID: 7640475
Filing Date: 2009-12-29
Classification: G01R

Abstract:
1. A digital system, comprising: a plurality of scan chains interconnected together with logic circuitry to form at least a portion of a functional circuit, with each scan chain having any number of scan cells, a global scan enable signal and an at-speed local scan enable signal to control a mode of operation, any number of last transition generator cells physically located anywhere in the scan chain and not connected to a circuit-under-test, a clock signal, with each last transition generator cell having: a first flip-flop with an output connected to a second flip-flop input; an input multiplexer to apply any one of a first flip-flop output data and a test data to a first flip-flop input based on a state of the at-speed local scan enable signal; and an OR gate having a first flip-flop output and the global scan enable signal as inputs to generate the at-speed local scan enable signal based on a state of the global scan enable signal and a state of the first flip-flop output data.