Patent ID: 7247543
Filing Date: 2007-07-24
Classification: H01L

Abstract:
1. A method for fabricating a decoupling capacitor with increased resistance to electrostatic discharges on an integrated circuit, the method comprising: forming a well region in a substrate; forming a gate oxide layer above the well region; forming a polysilicon gate structure above the gate oxide layer; forming a source region proximate to the gate oxide layer; forming a drain region proximate to the gate oxide layer and opposite the source region; forming a first node in the well region of a conductivity type opposite to that of the source region; forming a second node in the substrate of a conductivity type opposite to that of the first node; covering the polysilicon gate structure, the source region, the drain region, and the first and second nodes with a dielectric layer; and forming, through the dielectric layer, a first interconnection to the source region and a second interconnection to the polysilicon gate structure, while leaving the dielectric layer above the drain region intact, wherein the drain region is not connected to an interconnection and is floating; forming another polysilicon gate structure for a second decoupling capacitor; and connecting the polysilicon gates with a polysilicon line, so that the two decoupling capacitors are combined into a single decoupling capacitor.