Patent ID: 6185719
Filing Date: 2001-02-06
Classification: G06F

Abstract:
A method of designing a logic circuit for mapping a logical expression, comprising:identifying a first logic group including a first plurality of logic functions and at least one complementary variable shared by the first plurality of logic functions, and a second logic group including a second plurality of logic functions and a common variable shared by the second plurality of logic functions in the logical expression; andmapping the logical expression, including:placing a pass-transistor multiplexer having input terminals, at least one control terminal and an output terminal in the logic circuit;connecting the input terminals and the at least one control terminal of the pass-transistor multiplexer to input the first plurality of logic functions and the at least one complementary variable so that the first logic group is output from the output terminal of the pass-transistor multiplexer;placing a non-pass-transistor multiple-input logic gate having input terminals and an output terminal in the logic circuit; andconnecting the input terminals of the non-pass-transistor multiple-input logic gate to input the common variable and a sum of the second plurality of logic functions so that the second logic group is output from the output terminal of the non-pass-transistor multiple-input logic gate, wherein the pass-transistor multiplexer and the non-pass-transistor multiple-input logic gate are electrically connected together.