Patent ID: 8018257
Filing Date: 2011-09-13
Classification: G11C,H03K,H03L

Abstract:
1. A synchronous memory device for synchronization of an external input clock with an internal input clock comprising: a delay locked loop (DLL) having a clock divider comprising a plurality of clock signal dividers connected in series, a power down controller determining a power down operation based at least on a predetermined state of a clock enable signal that controls whether the memory device excluding the DLL receives the external input clock and that is inputted to the DLL, wherein the clock divider outputs a first clock signal being one of the output signals of the clock signal dividers excluding the last clock signal divider of the series when the synchronous memory device is in the non-power down operation, wherein the clock divider outputs a second clock signal being an output signal of the last clock divider of the series when the synchronous memory device is in a power down operation, and