Patent ID: 7554378
Filing Date: 2009-06-30
Classification: H03K

Abstract:
1. A level translator comprising: a comparator having a first input coupled to a voltage input VIN and a second input coupled to a reference voltage VREF, the comparator having four output terminals, a first terminal that sinks current if the voltage input VIN is greater than the reference voltage VREF, a second terminal that sinks current if the voltage input VIN is less than the reference voltage VREF, a third terminal that sources current if the voltage input VIN is greater than VREF, and a fourth terminal that sources current if the voltage input VIN is less than VREF; a first coupling capacitive element coupled to the voltage input VIN and to the first terminal of the comparator; a second coupling capacitive element coupled to the voltage input VIN and to the fourth terminal of the comparator; a first transistor having drain, gate, and source terminals, the drain of the first transistor coupled to an output of the translator, the gate of the first transistor coupled to the first coupling capacitive element and to the first terminal of the comparator, the first transistor having a predetermined minimum gate to source voltage required for current conduction; a second transistor having drain, gate, and source terminals, the drain of the second transistor coupled to an output of the translator, the gate of the first transistor coupled to the second coupling capacitive element and to the fourth terminal of the comparator, the second transistor having a predetermined minimum gate to source voltage required for current conduction, the gates of the first and second transistors being of complementary conductivity; a first current mirror having one terminal connected to the second terminal of the comparator and a second terminal connected to the gate of the first transistor, and a third terminal connected to the source terminal of the first transistor; a second current mirror having one terminal connected to the third terminal of the comparator, a second terminal connected to the gate of the second transistor, and a third terminal connected to the source terminal of the second transistor; a first clamp circuit for limiting a gate voltage of the first transistor and having a first terminal connected to the gate of the first transistor and a second terminal connected to the source terminal of the first transistor; and a second clamp circuit for limiting a gate voltage of the second transistor and having a first terminal connected to the gate of the second transistor and a second terminal connected to the source terminal of the second transistor.