Patent ID: 8514994
Filing Date: 2013-08-20
Classification: H03K

Abstract:
1. An integrated circuit comprising: a first single data rate portion that contains two or more elements, each element configured to perform one operation per cycle of a clock signal; a double data rate portion that contains one or more elements each configured to perform two operations per cycle of the clock signal, the double data rate portion configured to receive a first input and a second input from the first single data rate portion, wherein the double data rate portion is configured to select the first input upon a first edge of the cycle of the clock signal and select the second input upon a second edge of the cycle of the clock signal to provide a double data rate output; and a second single data rate portion that contains two or more elements each configured to perform one operation per cycle of the clock signal, the second single data rate portion configured to receive an input from the double data rate portion.