Patent ID: 8068188
Filing Date: 2011-11-29
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a gate line formed on an insulating substrate; a storage electrode line formed on the insulating substrate; a gate insulating layer on the gate line; a semiconductor layer on the gate insulating layer; a data line formed on the gate insulating layer and including a source electrode; a drain electrode formed at least in part on the semiconductor layer; a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part and a portion of an upper surface of the gate insulating layer; and a pixel electrode formed on the passivation layer and contacting the drain electrode and the exposed portion of the gate insulating layer through the first contact hole, wherein the first contact hole overlaps the storage electrode line.