Patent ID: 9100002
Filing Date: 2015-08-04
Classification: G06F,H03K

Abstract:
1. An integrated circuit comprising: a digital logic circuit having a plurality of inputs, wherein the digital logic circuit comprises a plurality of logic gates; a first polarization circuit configured to receive a standby signal and a digital input signal comprising a plurality of bits, wherein when the standby signal is deactivated, the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit based on the digital input signal, and wherein when the standby signal is activated the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit; and a first plurality of state elements, wherein the digital logic circuit is configured to generate a digital output signal and to provide the digital output signal to the first plurality of state elements, wherein the integrated circuit is configured such that the first plurality of state elements are inhibited from loading a value of the digital output signal when the standby signal is activated.