Patent ID: 8605491
Filing Date: 2013-12-10
Classification: G11C,H01L

Abstract:
1. A static random access memory (SRAM) cell having a dedicated read port separated from a write port, the SRAM cell comprising: a first bit-line and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port; a third bit-line and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port; a positive voltage supply line disposed between a first ground line and a second ground line placed in parallel, wherein each bit-line is separated by either the positive voltage supply line or one of the ground lines; a first metal line and a second metal line adjacently flanking and in parallel to the first bit-line, the first metal line and the second metal line being formed in the same metal layer as the first bit-line; and a third metal line and a fourth metal line adjacently flanking and in parallel to the second bit-line, the third metal line and the fourth metal line being formed in the same metal layer as the second bit-line, wherein the first metal line and the first ground line disposed next to the first metal line are placed between the first bit-line and the third bit-line, and the third metal line and the second ground line disposed next to the third metal line are placed between the second bit-line and the fourth bit-line.