Patent ID: 9189580
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. A method for developing an integrated circuit device simulation model for an integrated circuit in which a property of a transistor of the circuit will be modified by effects of stress in a channel of the transistor, comprising the steps of: providing a circuit layout for at least a portion of an integrated circuit device, the layout identifying a first transistor for the device, the first transistor having a channel; approximating a first stress, oriented in a longitudinal direction of the channel, induced in at least a portion of the channel; approximating a second stress, induced in the channel portion and oriented laterally across the channel portion and perpendicular to the longitudinal direction; approximating stress-induced variation of a transistor property of the first transistor, in dependence upon both the first and second stress approximations; including in the simulation model transistor property variation information obtained in dependence upon the approximated stress-induced variation of a transistor property of the first transistor; and providing the simulation model for simulating the integrated circuit.