Patent ID: 6424659
Filing Date: 2002-07-23
Classification: H04L

Abstract:
A multi-level packet switching system comprising:at least two first-level switches for packet reception or transmission, each first level switch comprising an integrated switch module that enables multi-layer switching and a processing module coupled to the integrated switch module; and a second-level switch comprising a cross-bar switch coupled to a multi-protocol router, said second level switch also coupled to each of the first-level switches for enabling packet communication between the second-level switch and the first-level switches; wherein: each of said first and second-level switches are configured to determine which of Layer-2 switching and Layer-3 routing needs to be performed based on a Layer-2 lookup of packets received by the switching system and then perform wire-speed routing at Layer-3 and wire-speed switching at Layer-2 according to the Layer-2 lookup; said wire-speed routing and said wire-speed switching are performed at the same time; said integrated switch module comprises, a receive block configured to receive packets from a network communication medium; a content addressable memory (CAM) containing Layer-2 routing information; a CAM interface coupled to said receive block and configured to, retrieve header address information from packets received by said receive block, lookup Layer-2 information stored in said CAM based on the retrieved header address information, and identify whether the packet associated with the retrieved header address information requires Layer-2 switching or Layer-3 routing based on the Layer-2 information; a forwarding engine, coupled to said CAM interface and said receive block, configured to direct each of said Layer-3 routing and Layer-2 switching to be performed on the received packets based on said identification; said processing module includes programming for CAM header processing that assists in source lookup, source port read, and source learning; and said source learning comprises a process for learning Media Access Control (MAC) addresses and parts of data packets arriving from Ethernet ports coupled to the corresponding first level switch and applying the learned addresses and parts in said source lookup and said source port read.