Patent ID: 8621299
Filing Date: 2013-12-31
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising: A. a TDI lead, a TDO lead, a TMS lead, and a TCK lead; B. a test access port controller having inputs connected to the TMS and TCK leads and having a ClockDR output, a ShiftDR output, and an UpdateDR output; C. instruction register circuitry having a Mode- D. data register circuitry having a TDI input connected to the TDI lead, a TDO output selectively coupled to the TDO lead, a Mode- E. ATC gating circuitry having an ATC enable input connected to the ATC enable output, an UpdateDR input connected to the UpdateDR output, an Update input, and a gated UpdateDR output connected to the gated UpdateDR input.