Patent ID: 8687684
Filing Date: 2014-04-01
Classification: H03D,H03M,H04B,H04L

Abstract:
1. A circuit for correcting the phase error between the in-phase and quadrature sampling clocks in a quadrature bandpass-sampling receiver comprising: a test tone generator configured to generate a first multiplier configured to multiply the in-phase test tone with the in-phase sampling clock to generate an up-converted in-phase test tone; a second multiplier configured to multiply the quadrature test tone with the quadrature sampling clock to generate an up-converted quadrature test tone; a first D/A converter configured to receive the up-converted in-phase test tone to generate an in-phase analog test tone; a second D/A converter configured to receive the up-converted quadrature test tone to generate a quadrature analog test tone; a quadrature bandpass sampling delta-sigma analog-to-digital demodulator (QBS-ADD) configured to a digital signal processor (DSP) configured to wherein the DSP further comprises: a sampling clock generator configured to generate the in-phase sampling clock, having an in-phase sampling clock frequency; and a ninety-degree phase shifter configured to