Patent ID: 8988963
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. An intermediate circuit for DRAM, the intermediate circuit coupled between a user interface and the DRAM, the user interface transmitting access commands at a first clock, the DRAM operating at a second clock and being refreshed via a refresh controller, wherein clock cycle of the first clock is greater than clock cycle of the second clock, the intermediate circuit comprising: a first control circuit configured to generate a Command Output Enable signal and a Refresh Enable signal based on the second clock, wherein the Command Output Enable signal has a first state and a second state, wherein a ratio of duration of the first state to that of the second state is the second clock cycle divided by the difference between the first clock cycle and the second clock cycle, and wherein the Refresh Enable signal has a state that is reverse to that of the Command Output Enable signal and is applied to the refresh controller; a command buffer configured to i) store the access commands received from the user interface and ii) output the stored access commands to the DRAM when the Command Output Enable signal is in the first state; and a data buffer configured to read data from the DRAM and output the read data to the user interface.