Patent ID: 6780775
Filing Date: 2004-08-24
Classification: G03F,H01L

Abstract:
A method for producing a semiconductor device having an alignment mark, the method comprising the steps of:forming a first dielectric layer; etching a trench having predetermined dimensions into the dielectric layer; depositing a first layer of metal into the trench; forming a second dielectric layer over the first dielectric layer and over the first layer of metal; depositing a first resist layer over said second dielectric layer; patterning said first resist layer to define a first multiplicity of apertures and an array of openings, said array of openings having a predetermined periodicity and each opening having a selected width; etching, simultaneously, said first multiplicity of apertures and said array of openings into the second dielectric layer a first distance; depositing a second resist layer over said etched second dielectric layer; patterning said second resist layer to define a second multiplicity of apertures; etching said second multiplicity of apertures a second distance; filling the apertures and the array of openings with a metal, the filling step controlled to fill the channels and under fill the array of openings, said selected width of said openings being at least two times the depth of said openings; performing chemical mechanical polishing of the metal; and depositing a non-transparent stack of layers onto the metal to cover the under filled array of openings, resulting in an alignment grating comprised of visible indentations in the non-transparent stack of layers.