Patent ID: 6989691
Filing Date: 2006-01-24
Classification: H03K

Abstract:
1. An apparatus comprising: a converter circuit coupled to receive a plurality of dynamic logic input signals, in which the converter circuit has a plurality of input transitors gated by the plurality of dynamic logic input signals, including a first pair of complementary metal-oxide-semiconductor (CMOS) transistors coupled to be grated by a first of the dynamic logic input signals, to generate a logical combination of the plurality of dynamic logic input signals as a static logic output signal on an output node during an evaluate phase of a clock signal, the static logic output signal having a first state or a second state depending on the dynamic logic input signals, the converter circuit further including a first clocked transistor to be active to enable the first pair of CMOS transistors during the evaluate phase, but to float the output node to retain the state of the static logic output signal during a precharge phase of the clock signal when a precharge voltage is to be applied to gate inputs of the first pair of CMOS transisitors; and a noise suppression circuit, including a second pair of CMOS transistors coupled to be gated by a feedback voltage from the output node, to sustain the state of the output node during the precharge phase, the noise suppression circuit further including a second clocked transistor which is to be active during the precharge phase to couple a first potential onto the output node through the second clocked transistor and one of the second pair of CMOS transistors when the output node is in the first state, but to couple a second potential through the other of the second pair of CMOS transistors and one of the first pair of CMOS transistors of the converted circuit when the output node is in the second state.