Patent ID: 6021465
Filing Date: 2000-02-01
Classification: G06F

Abstract:
An arrangement for connecting peripheral memory devices to at least one higher-level system unit in a data processing system via at least one intermediate data transmission controller which has control devices for controlling data interchange between the memory devices as respective sinks or sources and the at least one higher-level system unit, comprising:the memory devices interconnected to form at least one serially operated device ring;the device ring having a ring connection for the at least one intermediate data transmission controllerthe data transmission controller having a memory access unit for a common first data memory as a communication and wanted data memory for handling control of the data interchange between the higher-level system unit and the memory devices;the data transmission controller being an autonomous computer having a control device with associated internal memories and an internal bus system to which computer the memory access unit, all ring connections linked together and respective system adapters which are provided for signal matching to a respective, connected, higher-level system unit, are connected as autonomous units.