Patent ID: 9191031
Filing Date: 2015-11-17
Classification: G06F,G11B,H03M

Abstract:
1. A circuit, comprising: a decoder configured to receive first codewords and decode the first codewords based on a first error correcting code, and to receive second codewords and decode the second codewords based on a second error correcting code; an error checking module configured to error-check first portions using a first error detecting code in the first portions, each first portion being formed of a plurality of decoded first codewords, and to error-check second portions using a second error detecting code in the second portions, each second portion being formed of a plurality of decoded second codewords; and a controller configured to store in a memory, when the error checking fails for at least one first portion, the decoded first codewords, and to store in the memory, when the error checking of the second portion fails for at least one second portion, the decoded second codewords based on the decoded first codewords stored in the memory so as to combine the decoded first codewords with the decoded second codewords.