Patent ID: 7276425
Filing Date: 2007-10-02
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit, comprising the steps of: providing a semiconductor substrate having a recessed region; forming a first dielectric material within the recessed region; forming a capping layer comprising a semiconductor material overlying the first dielectric material; forming openings in the capping layer to expose portions of the first dielectric material; etching the first dielectric material through the openings to form dielectric pillars while leaving portions of the capping layer overlying top surfaces of the dielectric pillars; growing a second dielectric material to form a seal over the dielectric pillars and voids between the dielectric pillars, wherein the portions of the capping layer are configured to enhance growth of the second dielectc material to form the seal thereby maximizing volume of the voids; and forming a passive component over the second dielectric material.