Patent ID: 9003347
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. An integrated circuit design implementation system comprising: a first database having one or more libraries of standard cells, wherein the one or more libraries comprises a first cell with a first cell height and a second cell with a second cell height different from the first cell height and different from an integer multiple of the first cell height; a synthesis tool communicably coupled to the first database to access the one or more libraries of standard cells, the synthesis tool receiving and synthesizing a behavioral description of a circuit design and generating a logic gate-level circuit description from the behavioral description of the circuit; a place and route tool to generate a layout from the logic gate-level circuit description and to combine the first cell and the second cell into a first cell row by adding one or more extension regions to the second cell, the one or more extension regions connecting well regions of the first cell and implant regions different from the well regions of the first cell to adjacent cells, the one or more extension regions further comprising an implant extension extending across and beyond a first side of the first cell, the implant extension having a different conductivity than a well region that is adjacent to the one or more extension regions in a first direction, the first direction being parallel with a longitudinal axis of the first cell row; and an output tool to output the layout to a manufacturing tool.