Patent ID: 8927199
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method of manufacturing an array substrate, the method comprising: forming gate wiring and gate electrodes connected to the gate wiring, on a base substrate; coating amorphous silicon layers on the gate electrodes; disposing a mask at different positions over the substrate, the mask comprising a central area, a peripheral area disposed around the central area, and lenses disposed in the central area and the peripheral area; irradiating the amorphous silicon layers through the mask, while the mask is at each of the positions, to sequentially crystallize the amorphous silicon layers; and forming source electrodes and drain electrodes on the crystallized silicon layers, wherein the peripheral area is disposed above a group of the same semiconductor layers, while the mask is in a first one of the positions and in a second one of the positions.