Patent ID: 9202880
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method of making a stepped field gate for a field effect transistor (FET) comprising: forming a first set of layers having a first passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer; forming at least one additional set of layers over the first etch stop layer, wherein additional sets of layers each have a passivation layer and an etch stop layer on the passivation layer; forming a top passivation layer over the additional sets of layers; forming a field plate mask on the top passivation layer to define a source side of a stepped field-plate gate; successively removing portions of the top passivation layer and of each set of layers using lithography and reactive ion etching to form stepped passivation layers, wherein the field plate mask defines a boundary for the etching on the source side; applying a mask having an opening defining an extent of the stepped field-plate gate; and forming the stepped field-plate gate by plating through the opening in the mask.