Patent ID: 8654898
Filing Date: 2014-02-18
Classification: H04L

Abstract:
1. A serial interface for an integrated circuit device, said serial interface comprising: a deserializer portion comprising: digitizing circuitry that digitizes received analog serial data, said digitizing circuitry comprising a plurality of analog-to-digital converters that provide a corresponding plurality of reduced-rate data streams of digitized received serial data; digital equalization circuitry that operates on said digitized received serial data to provide equalized digital data; a demultiplexer downstream of said digital equalization circuitry for deserializing said equalized digital data; and a clock recovery unit that provides a clock for said analog-to-digital converters, said digital equalization circuitry and said demultiplexer; wherein: said digital equalization circuitry and said demultiplexer operate at correspondingly reduced rates.