Patent ID: 7356674
Filing Date: 2008-04-08
Classification: G06F,G11C

Abstract:
1. A method implementing a native instruction set architecture (ISA) having an emulation engine and an emulated ISA, wherein a fetch engine fetches instructions of the emulated ISA from a memory subsystem, the method comprising: sending a fetch request signal to the fetch engine; sending a fetch address to the fetch engine; retrieving a line of instructions from the memory subsystem, wherein the line of instructions is associated with the fetch address; storing the fetch address in a fetch address queue; sending the line of instructions to the emulation engine; sending a fetch complete signal from the fetch engine to the emulation engine when the line of instructions is sent to the emulation engine, the fetch complete signal being a signal separate from the line of instructions, wherein the step of storing comprises storing the fetch address in the fetch address queue until the fetch complete signal is sent; storing the fetch address in a queue of the emulation engine, wherein the queue of the emulation engine mirrors the fetch address queue; progressing the fetch address through pipeline stages of the fetch engine and the emulation engine synchronously using pipeline advance logic; receiving, at the pipeline advance logic, a delayed version of the fetch complete signal; and advancing the fetch address through the fetch engine and the emulation engine based on the delayed version of the fetch complete signal.