Patent ID: 9037836
Filing Date: 2015-05-19
Classification: G06F

Abstract:
1. A method for facilitating thread switching in a multi-processor system comprising a plurality of processing elements and a plurality of local memories coupled together by a packet-switched interconnection network, which includes a plurality of network nodes and an end node coupled to an external memory, the method comprising: using a shared load-store unit to monitor activity on the network by monitoring activity flags in the network nodes to determine whether activity on the network has ceased and that an external memory transaction has passed beyond the end node to the external memory; using the shared load-store unit to monitor transaction-enable flags in the processing elements that indicate whether results of the external memory transaction have returned to the processing elements; and upon determining that activity on the network has ceased and that one or more transaction-enable flags remain enabled, determining that the external memory transaction remains in progress, and indicating to a controller that a thread switch may take place.