Patent ID: 7694106
Filing Date: 2010-04-06
Classification: G06F

Abstract:
1. A multiprocessor system comprising: a global address crossbar; a plurality of system boards connected with each other via the global address crossbar, each of which has a CPU, a memory, a data queue provided on the CPU, and a data queue provided on the memory, wherein processing is symmetrically assigned to all the CPUs by inputting addresses to the global address crossbar; a judging unit judging whether a read command issued from a CPU is a read command to a memory on an own system board, the read command being to be inputted to the global address crossbar; an executing unit speculatively executing, in a case that the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar; a setting unit setting, when the read command is speculatively executed, for queuing data read from the memory by the read command speculatively executed in the data queue provided on the CPU without queuing the data in the data queue provided on the memory; and an instructing unit instructing, based on the notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.