Patent ID: 7526776
Filing Date: 2009-04-28
Classification: G11B

Abstract:
1. A method implemented at a computing device having a processor and cache memory communicatively coupled to the processor, the method comprising: generating a source chain for use in a development project, the source chain comprising a plurality of filters each communicatively connected with one another to form a filter chain having an input at a first end and an output at a second end, the plurality of filters being communicatively connected by: coupling the source chain with a matrix switch comprising a scalable plurality of inputs and a scalable plurality of outputs, wherein the matrix switch is configured to receive data from any one or more of the scalable plurality of outputs as one or more of the scalable plurality of inputs; processing media using the source chain and said matrix switch to produce at least one development project; and caching the source chain to the cache memory of the computing device when it is not currently required in the development project, resulting in expedited commencement of the source chain for use when subsequently required and reduction of computational and system requirements placed on the computing device.