Patent ID: 7471546
Filing Date: 2008-12-30
Classification: G11C

Abstract:
1. An SRAM memory array comprising: a plurality of memory cells, each of said plurality of memory cells further comprising: a device, each of said plurality of memory cells having six of said device; a first storage node; a second storage node; a first local bit line; a second local bit line; a first global bit line; and a second global bit line; two of said device arranged as a first pFET device and a second pFET device, said first global bit line and said second global bit line serve as sense lines by way of cross coupled said first pFET device and said second pFET device, wherein said first global bit line is connected to drain on said first pFET device and to the gate on said second pFET device, said second global bit line is connected to the drain of said second pFET device and the gate of said first pFET device, both of said first pFET device and said second pFET device having source connected to a supply voltage, only one of said first global bit line or said second global bit line is set ‘LOW’ on a ‘READ’ and the same polarity sensed on said first local bit line and said second local bit line appears on said second global bit line and said first global bit line respectively, and is sensed by global sense amplifiers.