Patent ID: 7521805
Filing Date: 2009-04-21
Classification: H01L

Abstract:
1. An integrated circuit chip comprising: a silicon substrate; an off-chip driver, receiver or I/O circuit in or on said silicon substrate; an intra-chip driver or receiver in or on said silicon substrate; an internal circuit in or on said silicon substrate, wherein said internal circuit comprises a MOS device; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said off-chip driver, receiver or I/O circuit; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said off-chip driver, receiver or I/O circuit; a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a first terminal of said intra-chip driver or receiver; a fourth interconnecting structure connecting a second terminal of said intra-chip driver or receiver to said internal circuit; a passivation layer over said dielectric layer; a first via in said passivation layer, wherein said first via is connected to said second interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said third interconnecting structure; a fifth interconnecting structure over said passivation layer, wherein said fifth interconnecting structure is connected to said first and second vias, wherein said second terminal of said off-chip driver, receiver or I/O circuit is connected to said first terminal of said intra-chip driver or receiver through, in sequence, said second interconnecting structure, said first via, said fifth interconnecting structure, said second via and said third interconnecting structure, and wherein said fifth interconnecting structure comprises a metal line having a sheet resistance of smaller than 7 milliohms per square, wherein said metal line comprises an adhesion/barrier layer, a seed layer on said adhesion/barrier layer and an electroplated metal layer on said seed layer, wherein the material of said electroplated metal layer is the same as that of said seed layer, wherein said electroplated metal layer has a thickness between 2 and 100 micrometers, and wherein an undercut with an edge of said adhesion/barrier layer recessed from an edge of said electroplated metal layer is between 0.03 and 2 micrometers; and an external connection point connected to said first terminal of said off-chip driver, receiver or I/O circuit through said first interconnecting structure.