Patent ID: 6745318
Filing Date: 2004-06-01
Classification: G06F

Abstract:
A processing unit comprising:a fetch module operably coupled to fetch an instruction; a decoder operably coupled to receive the instruction and to produce, therefrom, a decoded instruction; and a dynamic arithmetic unit operably coupled to receive the decoded instruction such that the dynamic arithmetic unit includes at least one configurable arithmetic logic unit (ALU) having a plurality of modules and a plurality of registers, wherein at least one of the plurality of modules and at least one of the plurality of registers are coupled together in response to the decoded instruction to perform an operation identified by the decoded instruction wherein the at least one configurable ALU further comprises: a formatting module operable to format incoming data; a right shift register; a left shift register; a rounding module operable to providing a rounding signal when a result is to be rounded; an addition module; a subtraction module; leading zero count module; intermediate data registers; multiplier tree; and configuration circuitry operable to couple at least some of the formatting module, the right shift register, the left shift register, the rounding module, the addition module, the subtraction module, the leading zero count module, the intermediate registers, and the multiplier tree together to perform the operation.