Patent ID: 9223743
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A programmable chip, comprising: a plurality of programmable logic elements; a hard-coded multiplier implemented using only AND gates and adders, the hard-coded multiplier configured to receive a first operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines and to provide a first output over a plurality of first output lines, wherein the plurality of first operand input lines and the plurality of second operand input lines are all inputs to the hard-coded multiplier, wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output lines, wherein the hard-coded multiplier uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition to hard-coded two-input logic operations, and wherein a subset of the plurality of output lines provides a plurality of XOR and non-XOR functions.