Patent ID: 6721199
Filing Date: 2004-04-13
Classification: G11C

Abstract:
A nonvolatile ferroelectric memory device comprising:a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells; a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column; a plurality of sub bitlines connected with the unit cells to induce a voltage in the unit cells and arranged along the main bitlines; a plurality of main bitline load controllers respectively arranged at least in the uppermost area and the lowest area of the sub cell array blocks so that one end of each of the main bitline load controllers is connected with the main bitline and the other end of said each of the main bitline load controllers is connected with a high level applying terminal; a sensing amplifier block including a plurality of sensing amplifiers commonly used in the cell array blocks and amplifying signals of the main bitlines; and switching transistors arranged one per sub bitline to sense data values of the unit cells using current by varying a current flow depending on the voltage induced in the sub bitline and a voltage transferred to the main bitlines.