Patent ID: 6740559
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising a MIS field-effect transistor, said MIS field-effect transistor including:a semiconductor substrate; a gate insulation layer formed on said substrate and having a side surface; a gate electrode formed on said gate insulation layer and having a corner portion between a side surface and an upper surface thereof; and a pair of source/drain having a first impurity region and a second impurity region formed in said substrate, said second impurity region formed deeper than said first impurity region, and wherein said method comprises the steps of: forming said gate insulation layer and said gate electrode on said substrate; forming a protection layer for gate insulation layer so as to shield said side surface of said gate insulation layer, said step of forming said protection layer for gate insulation layer comprising the steps of: forming a film that will become said protection layer for gate insulation layer on said substrate, so as to cover said gate insulation layer and said gate electrode; and anisotropically etching said film to form said protection layer for gate insulation layer so as to shield said side surface of said gate electrode and said side surface of said gate insulation layer from a position corresponding to said corner portion and over positions corresponding to said side surface of said gate insulation layer; forming a side-wall insulation layer including an impurity, in such a manner that said protection layer for gate insulation layer is sandwiched between said side-wall insulation layer and said side surface of said gate electrode, said step of forming a side-wall insulation layer comprising a step of over-etching said side-wall insulation layer to form said side-wall insulation layer to be positioned lower than said corner portion; and forming said second impurity region in said substrate, then diffusing said impurity within said side-wall insulation layer by thermal diffusion into said substrate below said side-wall insulation layer to form said first impurity region in said substrate.