Patent ID: 6067037
Filing Date: 2000-05-23
Classification: H03M

Abstract:
A digital-to-analog converter comprisingan operational amplifier having an inverted input node, a non-inverted input node and an output node,a first capacitor connected between said output node and said inverted input node and having a capacitance 2.sup.N times larger than a reference capacitance, said N is a natural number,a first capacitor array connected to said inverted input node and having a plurality of second capacitors equal in number to said N and different in capacitance from one another, the capacitance of said plurality of second capacitors being stepwise varied from 2.sup.0 times larger than said reference capacitance to 2.sup.N-1 times larger than said reference capacitance,a third capacitor connected to said inverted input node and having a capacitance equal to said reference capacitance,a first switching element connected between said output node and said inverted input node and responsive to a first control signal so as to electrically connect said output node to said inverted input node,a switching unit having an input port connected to a source of first voltage, a source of second voltage, a source of third voltage and source of fourth voltage and an output port connected to said plurality of second capacitors, said third capacitor and said non-inverted input node and responsive to a second control signal so as to selectively supply said first voltage level, said second voltage level and said third voltage level to said plurality of second capacitors and said third capacitor, said switching unit continuously supplying said fourth voltage to said non-inverted input node, anda controlling unit connected to said switching unit and responsive to external control signals and a digital signal having data bits equal in number to said N so as to change said first control signal and said second control signal between an active level and an inactive level,said external signals defining a first time period, a second time period next to said first time period, a third time period after said second time period and a fourth time period next to said third time period depending upon the combination of potential levels of said external control signals,said digital signal being indicative of a first analog value in said first and second time periods and a second analog value in said third and fourth time periods,said controlling unit causing said first switching element to electrically connect said output node to said inverted input node in said first time period and said third time period and disconnect said output node from said inverted input node in said second time period and said fourth time period,said controlling unit causing said switching unit to selectively supply said first voltage and said second voltage to said plurality of second capacitors depending upon said data bits and supply said second voltage to said third capacitor in said first time period,said controlling unit causing said switching unit to supply said third voltage to said plurality of second capacitors and said third capacitor in said second time period so that said operational amplifier determines an output potential level at said output node,said controlling unit causing said switching unit to supply said third voltage to said plurality of second capacitors and said third capacitor in said third time period,said controlling unit causing said switching unit to selectively supply said first voltage and said second voltage to said plurality of second capacitors depending upon said data bits and supply said second voltage to said third capacitor in said fourth time period, thereby causing said operational amplifier to determine said output potential level.