Patent ID: 7488634
Filing Date: 2009-02-10
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a flash memory device comprising: forming a sacrificial insulating pattern layer corresponding to a flash memory channel region in a semiconductor substrate; coating a photoresist layer on an entire surface of the semiconductor substrate and selectively patterning the photoresist layer; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer and the photoresist layer as a mask; removing the sacrificial insulating pattern layer and the photoresist layer to expose an entire surface of the semiconductor substrate; sequentially forming a gate dielectric layer and a gate material layer on the entire exposed surface of the semiconductor substrate having source and drain regions formed therein, the gate dielectric layer comprising an ONO structure; forming a gate in the channel region by selectively etching the gate material layer and at least part of the gate dielectric layer; and forming gate sidewall spacers at sides of the gate.