Patent ID: 8593852
Filing Date: 2013-11-26
Classification: G11C

Abstract:
1. A test device for performing an operation verifying test on a resistive random access memory in which a memory element including a rectifier element and a variable resistance element is arranged at each intersection of a plurality of word lines and a plurality of bit lines and which performs activation/deactivation control of the word lines and activation/deactivation control of the bit lines by using a plurality of core control signals synchronized with a write enable signal and changing one of the core control signals corresponding to each start point of a plurality of sequences, the test device comprising: a shift pulse generating circuit that generates a shift pulse based on a first write enable signal that changes with a constant period and a self generated pulse that is self-generated by using a second write enable signal that changes corresponding to a sequence whose limit time is checked among the sequences; a plurality of shift register circuits each of which includes a plurality of stages of registers that perform a shift operation by the shift pulse and in each of which a signal in each of the sequences of the core control signal to be generated is initially set; and a plurality of core control signal generating circuits each of which includes