Patent ID: 8451647
Filing Date: 2013-05-28
Classification: G11C

Abstract:
1. A method of controlling a resistance of a nonvolatile variable resistive element, wherein in a nonvolatile semiconductor memory device including a memory cell array in which a plurality of memory cells is arranged in row and column directions in a matrix, each memory cell being formed by connecting one terminal of the nonvolatile variable resistive element having two terminals in which electrodes are provided at both ends of a variable resistor, to one of other two terminals of a selection element, which has three terminals including a control terminal and the other two terminals that are other than the control terminal, the control terminal being for controlling an amount of current flowing across the other two terminals by current or voltage applied to the control terminal, the nonvolatile variable resistive element is subjected to a forming process, so that its resistive state transitions between two or more different resistive states by applying an electrical stress across the both terminals of the nonvolatile variable resistive element, and one resistive state after the transition is used for storing information, the each memory cell is configured such that the control terminal of the selection element is connected to a first selection line, and one of a terminal of the nonvolatile variable resistive element that is not connected to the selection element and a terminal of the selection element that is other than the control terminal and not connected to the nonvolatile variable resistive element is connected to a second selection line and the other thereof is connected to a third selection line, the first selection line extends in the row direction and connects the memory cells belonging to the same row, the second selection line extends in the column direction and connects the memory cells belonging to the same column, and the memory cells in the memory array are mutually connected by the first selection line, the second selection line and the third selection line, and the method comprises: when one or more first selection lines and a plurality of second selection lines are to be selected, respectively and one of memory operations of a programming process, an erasure process, and the forming process is to be collectively performed on target memory cells that are all of the memory cells selected by the first selection lines and the second selection lines, a first step of selecting the one or more of the first selection lines connected to the target memory cells to be subjected to the memory operation in the memory array and applying a predetermined selection voltage to all of the selected first selection lines; a second step of selecting the plurality of second selection lines connected to the target memory cells in the memory array; and a third step of applying, to each of the selected second selection lines, a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the memory operation of the nonvolatile variable resistive elements, the change in potential being dependent on a maximum number of the target memory cells that are commonly connected to each of the third selection lines to which the respective target memory cells on the selected second selection line are connected, such that the voltage that is necessary for the memory operation is applied to both terminals of all of the target memory cells.