Patent ID: 6569742
Filing Date: 2003-05-27
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor integrated circuit device comprising the steps of:forming an insulating film covering a first gate electrode of a first MISFET and a second gate electrode of a second MISFET, said first and second gate electrodes being formed on a surface of a semiconductor substrate; etching said insulating film by using a mask to form a side wall spacer on side surfaces of said first gate electrode and to leave a portion of said insulating film covering said second gate electrode and exposing a region of semiconductor substrate which is away from said insulating film left on a side surface of said second gate electrode; introducing an impurity in the exposed region of a semiconductor substrate which is not covered by said insulating film to form a first region of said first MISFET and a second region of said second MISFET; wherein said first region is formed in alignment with said side wall spacer of said first gate electrode, wherein said second region is formed in alignment with said insulating film; and forming a first metal-semiconductor reaction layer in said first region aligned with said side wall spacer of said first gate electrode and a second metal-semiconductor reaction layer in said second region aligned with said insulating film.