Patent ID: 7536618
Filing Date: 2009-05-19
Classification: G01R,G06F,G11C,H03K

Abstract:
1. A forward divider circuit, comprising: a divider chain including a plurality of divider circuits coupled in series with each other from a first divider circuit to a last divider circuit, the plurality of divider circuits being structured to receive an input clock signal and to generate from the input clock signal an output clock signal having a frequency that is determined by the frequency of the input clock signal and the number of the divider circuits through which the input clock signal is coupled to generate the output clock signal, the divider chain being structured to adjust the phase of the output clock signal to one of a plurality of phase values; and at least one retimer circuit coupled from an output of one of the divider circuits to an input of another of the divider circuits, the at least one retimer circuit being structured to receive a signal from the output of the one divider circuit and to couple the signal to the input of the other divider circuit in synchronism with a retimer signal.