Patent ID: 6809984
Filing Date: 2004-10-26
Classification: G06F,G11C

Abstract:
A multiport memory circuit comprising:an access address selecting circuit for asserting a word line of an address that is selected by a word selecting signal and a bit selecting signal, and is subjected to one of write operation and read operation; a plurality of memory cells, each of which includes a charge storing capacitor and a write access transistor switched on and off through the word line; sense amplifiers for amplifying data on read bit lines; a write/read switching circuit for selecting one of the write operation and read operation; refresh circuits, each of which is asserted when data of a corresponding memory cell is at an â€œLâ€  level to rewrite the â€œLâ€  level data to the memory cell via the read bit line; a write/read bit-line selecting circuit for selecting, under control of said write/read switching circuit, one of transferring write data to the bit lines and transferring data on the bit lines to said sense amplifiers; a bit line precharge circuit for precharging the bit lines; and a frequency multiplier for generating an internal clock signal used as a reference clock signal of the read operation and write operation, a frequency of the internal clock signal being equal to or greater than double a higher frequency of a write clock signal and a read clock signal.