Patent ID: 8478022
Filing Date: 2013-07-02
Classification: G01R,H01L

Abstract:
1. A failure analysis method, for a semiconductor integrated circuit, said method comprising: deriving a coordinate in a device coordinate system in analysis data for abnormal signal data included in analysis data of a semiconductor integrated circuit obtained from a semiconductor inspection apparatus; deriving a correspondence between a coordinate in said device coordinate system and a coordinate in a design coordinate system in design data of said semiconductor integrated circuit for a plurality of reference points in said semiconductor integrated circuit; deriving a coordinate conversion formula between the device coordinate system and the design coordinate system; deriving a position error between a coordinate in said device coordinate system converted by said coordinate conversion formula and a coordinate in said design coordinate system; and extracting a circuit related to an abnormal signal in said design data based on the coordinates of said abnormal signal in said device coordinate system using said coordinate conversion formula and said position error, and displaying image data of said analysis data and image data of said design data, wherein, said coordinate conversion includes specifying said plurality of reference points, said extracting a circuit includes a signal coordinate calculation that derives a range of the abnormal signal in said design coordinate system using said coordinate conversion formula and said position error, and said specifying lets a user input coordinates of said reference points in said device coordinate system and said design coordinate system using the image data of said analysis data and said design data of said semiconductor integrated circuit.