Patent ID: 6724361
Filing Date: 2004-04-20
Classification: G09G

Abstract:
A shift register comprising:flip-flops of a plurality of stages to which a clock signal is inputted; and switching means that is installed in each of the flip-flops of a plurality of stages and that controls the input of the clock signal, wherein, in response to the output signal of the flip-flop on the i-numbered stage (where i is an arbitrary integer) among the flip-flops of the stages, the switching means on the (i+1)-numbered stage is controlled so that the input of the clock signal to the flip-flop on the (i+1)-numbered stage is controlled and an output pulse having the same width as the pulse width of the clock signal is generated, the switching means on the i-numbered stage is provided on an input side of the flip-flop on the i-numbered stage, an on/off of each switching means is controlled by an output of the flip-flop in a previous stage, and a period in which the switching means is set on by an output of a flip-flop, the clock signal input to the switching means is an output of a shift register on a same stage.