Patent ID: 6658075
Filing Date: 2003-12-02
Classification: H04B,H04L,H04W

Abstract:
A frame timing lock detector circuit for a digital communications system, said frame timing lock detector circuit comprising:a) means for extracting known data sequences from a received signal; b) means for supplying a reference signal, said reference signal comprising symbols of said known data sequences raised to a power of 4k+3, where k is zero or an integer; c) a multiplier receiving said reference signal at a first input, and said known data sequences extracted from said received signal at a second input; d) a phase measurement circuit connected to an output of said multiplier for measuring a phase of a signal output by said multiplier; and e) a detection circuit, connected to an output of said phase measurement circuit, for comparing an average of an absolute value of the measured phase with a threshold, thereby detecting correct frame timing lock.