Patent ID: 7297583
Filing Date: 2007-11-20
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said method comprising: forming a PFET gate stack and an NFET gate stack over a first single-crystal semiconductor region having a first composition, said PFET gate stack and said NFET gate stack each having a gate conductor overlying a gate dielectric formed on a main surface of said first region and first spacers including a first material formed on sidewalls of said gate conductor; forming second spacers on sidewalls of said first spacers of said PFET gate stack and said NFET gate stack, said second spacers including a second material; removing portions of said second material from said second spacers of said PFET gate stack selective to said first material while protecting said second material from being removed from said second spacers of said NFET gate stack; thereafter, growing an epitaxial single-crystal semiconductor layer having a second composition on an exposed area of said first region, said epitaxial semiconductor layer being lattice-mismatched to said first region; forming a PFET source region and a PFET drain region of said PFET including at least a portion of said epitaxial semiconductor layer; and forming an NFET source region and an NFET drain region of said NFET, whereby said epitaxial semiconductor layer applies a stress having a first magnitude to said channel region of said PFET and said epitaxial semiconductor layer does not apply said stress having said first magnitude to said channel region of said NFET.