Patent ID: 8289763
Filing Date: 2012-10-16
Classification: G01R,G11C,H01L,H05K

Abstract:
1. A memory array, comprising: a plurality of bitline combs; the individual combs comprising a horizontally-extending global bitline and a plurality of vertically-extending bitline pillars electrically connected to the global bitline; the bitline combs comprising a first series and a second series; the second series being vertically offset relative to the first series; the bitline combs of the first series alternating with the bitline combs of the second series to form a staggered arrangement of the vertically-extending bitline pillars; the horizontally-extending global bitlines being parallel to one another; wordlines extending orthogonally to the global bitlines; the wordlines being stacked in a two-dimensional array comprising vertical columns and horizontal rows; the vertical columns of the wordline array comprising two or more wordlines; the bitline pillars extending through the wordline array so that bitline pillars are between adjacent vertical columns of the wordline array; and memory cell material directly between the wordlines and the bitline pillars; the memory cell material forming a plurality of memory cells uniquely addressed by wordline/global bitline combinations.