Patent ID: 6819619
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array storing data; a peripheral circuit inputting data to and outputting data from said memory cell array; and a power supply circuit supplying a power supply voltage to said memory cell array and said peripheral circuit, said power supply circuit including: a first power supply circuit group including voltage generating circuits, m (m: natural number) in number, including thick film transistors having a first gate oxide film thickness, each voltage generating circuit generating an internal voltage for inputting the data to and outputting the data from said memory cell array, and a second power supply circuit group including voltage generating circuits, n (n: natural number) in number, including thin film transistors having a second gate oxide film thickness thinner than the first gate oxide film thickness, each voltage generating circuit generating an internal voltage, where said first power supply circuit group corresponds to said memory cell array, and is arranged in a first region neighboring said memory cell array, and said m voltage generating circuits are arranged in said first region in m units; and said second power supply circuit group is arranged in a second region and not in said first region, and said n voltage generating circuits are arranged in said second region in a shuffled fashion.