Patent ID: 6417066
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A method of fabricating a capacitor structure, for a dynamic random access memory (DRAM), device, on a semiconductor substrate, comprising the steps of:forming a storage node plug structure in an opening in a first composite insulator layer, with said storage node plug structure overlying and contacting a source/drain region of a transfer gate transistor; forming a first capacitor opening in a second composite insulator layer, exposing the top surface of said storage node plug structure; forming discrete regions of silicon on the top surface of said second composite insulator layer, and on all exposed surfaces of said first capacitor opening; using said discrete regions of silicon as an etch mask to create horizontal channels in sides of an underlying, thick insulator component of said second composite insulator layer, exposed in said first capacitor opening, resulting in the creation of a second capacitor opening comprised with additional surface area provided by said horizontal channels; depositing an amorphous silicon layer; removal of portions of said amorphous silicon layer, and of portions of said discrete regions of silicon, from the top surface of said second composite insulator layer, to form a storage node structure in said second capacitor opening; forming a capacitor dielectric layer on said storage node structure; and forming a top electrode structure on said capacitor dielectric layer.