Patent ID: 7750481
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. An electronic device comprising: a first semiconductor integrated circuit die having a first plurality of bond pads thereon; a lone spacer that is offset from the center of said first integrated circuit die; a second semiconductor integrated circuit die having a second plurality of bond pads thereon; a third semiconductor integrated circuit die that is the topmost component in a stack; and a substrate having a third plurality of bond pads thereon wherein the first semiconductor integrated circuit die is mounted on the lone spacer, the lone spacer on the second semiconductor integrated circuit die, and the second semiconductor integrated circuit die on the substrate wherein the dimensions of the lone spacer are smaller than those of the first semiconductor integrated circuit die; a first plurality or wires, each connecting a bond pad on the first semiconductor integrated circuit die with a bond pad on the second semiconductor integrated circuit die; and a second plurality of wires, each connecting a bond pad on the second semiconductor integrated circuit die with a bond pad on the substrate.