Patent ID: 6753253
Filing Date: 2004-06-22
Classification: H01J,H01L,Y10S

Abstract:
A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring has thereon a second insulating film, said method comprising the steps of:providing a semiconductor substrate having an integrated circuit formed thereon, said integrated circuit including a semiconductor element having a PN junction, said substrate further having the multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit; selectively removing the second insulating film in said multilayer wiring structure, by machining with a focused ion beam, to form a contact hole which exposes a surface of the upper-level wiring in this region; selectively removing the upper-level wiring, the surface of which is exposed through said contact hole, by an isotropic etching process using said second insulating film as an etching mask, to form an opening region in said upper-level wiring, so as to expose a surface of the first insulating film, said opening region having a larger diameter than that of said contact hole; selectively removing said first insulating film, the surface of which is exposed through said contact hole and said opening region, by machining with a focused ion beam to form an opening portion which exposes a surface of said lower-level wiring; and forming a connecting wiring by a selective CVD method so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole, said opening region and said opening portion, and said connecting wiring being spaced from said upper-level wiring.