Patent ID: 9086439
Filing Date: 2015-07-21
Classification: G01D,G01R,G06F

Abstract:
1. A capacitance sensing circuit, comprising: a plurality of sample and hold (S/H) circuits, each configured to sample and store an analog value corresponding to a capacitance sensed by a corresponding sense channel, each S/H circuit comprising a sample amplifier having a first terminal and a sample capacitor having a first terminal and a second terminal, the first terminal of the sample amplifier coupled to the first terminal of the sample capacitor, each S/H circuit further including switch elements, the switch elements configured to couple the first and second terminals of the sample capacitor to a reference voltage in an idle mode, to couple the first terminal to the corresponding sense channel and the second terminal to the reference voltage in a sample mode, to isolate the first terminal and couple the second terminal to the reference voltage in a wait mode, and to couple the first terminal to an amplifier feedback loop and the second terminal to an amplifier input in a hold mode; and a multiplexer (MUX) circuit having a different input coupled to each S/H circuit and an output coupled to an analog-to-digital converter (ADC), wherein the sample amplifier of each S/H circuit is configured to operate in a low power state when an analog voltage from the corresponding sense channel is stored by the corresponding sample capacitor, and configured to operate in a second power state that is higher than the low power state when the S/H circuit is coupled to the ADC.