Patent ID: 8933752
Filing Date: 2015-01-13
Classification: H03F

Abstract:
1. A power amplifier apparatus comprising: a memory configured to store distortion compensation coefficients and addresses, each of the distortion compensation coefficients respectively corresponding to each of the addresses; a processor that performs first distortion compensation processing on an input signal using at least one distortion compensation coefficient to obtain a first signal, the at least one distortion compensation coefficient being loaded from the memory in accordance with at least one address respectively, the at least one address being generated from the input signal; and an amplifier that amplifies the first signal, wherein the processor further performs a second distortion compensation processing on the amplified signal using the at least one distortion compensation coefficient to obtain a second signal and updates the at least one distortion compensation coefficient to enable convergence between the first signal and the second signal, wherein the processor calculates a difference between the first signal and the second signal using a main component of the first signal and a main component of the second signal, the difference representing error.