Patent ID: 7773441
Filing Date: 2010-08-10
Classification: G06F,G11C

Abstract:
1. A system for predicting malfunctions in an array of memory cells, comprising: a storage device having sufficient capacity to store data stored in a row of the memory cells in the array; refresh circuitry operable to refresh rows of memory cells in the array, the refresh circuitry being operable to refresh a row of memory cells in the array under test with a test refresh rate and to refresh the remaining rows of memory cells in the array with a normal refresh rate that is substantially faster than the test refresh rate; data transfer circuitry coupled to the array of memory cells and the storage device, the data transfer circuitry being operable to copy the data stored in the row under test to the storage device before the refresh circuitry refreshes the row under test with the test refresh rate; data comparison circuitry coupled to the array of memory cells and the storage device, the data comparison circuitry being operable to compare at least some of the data stored in the storage device to at least some of the data stored in the row under test after the row under test has been refreshed with the test refresh rate, the data comparison circuitry being further operable to generate a malfunction indication if the data comparison circuitry determines that at least some of the data stored in the storage device does not match the data stored in the row under test after the row under test has been refreshed with the test refresh rate; and row repair logic coupled to the comparison circuitry, the row repair logic being operable responsive to the malfunction indication to remap accesses to the row under test to a redundant row of memory cells.