Patent ID: 6886146
Filing Date: 2005-04-26
Classification: G06F

Abstract:
1. A method for using timing simulation and authentication software of an EDA tool (electronics design automatic tool) to bypass a plurality of clock trees in the EDA tool, the EDA tool comprising a plurality of clocking devices that prevent the timing simulation and authentication software from changing an order of the plurality of clocking devices, the method comprising: measuring a delay time of the clocking device; providing a first buffer, which is electrically connected to the clocking device, wherein the delay time of the first buffer approximates the delay time of the clocking device; connecting a clock input port of the first buffer to a clock input port of the clocking device; connecting a clock output port of the first buffer and a clock output port of the clocking device to a multiplexer; and controlling the multiplexer to output a clock signal transmitted from the first buffer when executing the timing simulation and authentication software.