Patent ID: 9059174
Filing Date: 2015-06-16
Classification: H01L,Y02E

Abstract:
1. An integrated circuit structure, comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a plurality of first metal interconnect lines overlying the first dielectric layer, the first metal interconnect lines having a first thickness; a plurality of fuse lines formed from the same metal layer as the first metal interconnect lines over the first dielectric layer, the fuse lines each having a second thickness less than the first thickness; a second dielectric layer overlying the first dielectric layer and the first metal interconnect lines and located between the fuses, the second dielectric layer having a first portion having a third thickness over the first metal interconnect lines and a second portion having a fourth thickness between the fuses, the fourth thickness being less than the third thickness, wherein the second thickness is less than the third and fourth thickness of the second dielectric layer; a plurality of second metal interconnect lines on the second dielectric layer; a third dielectric layer over the second dielectric layer and covering the second metal interconnect lines; and a light transparent layer positioned over the fuse lines, the second dielectric layer, the third dielectric layer and in direct contact with the third dielectric layer and the second dielectric layer, wherein the light transparent layer over the third dielectric layer and the second portion of the second dielectric layer has planar upper surfaces and over the fuse lines includes a step feature.