Patent ID: 7702968
Filing Date: 2010-04-20
Classification: H03M

Abstract:
1. An apparatus, comprising: a mapper receiving at least one pair of received symbol values, each pair of received symbol values comprising a first value and a second value, and generating a plurality of third values in response to the at least one pair of received symbol values; a plurality of memory banks, each memory bank adaptable to store one of the third values; and a controller directing each of the plurality of third values to a selected one of the plurality of memory banks for simultaneous storing according to a storing pattern, the storing pattern determined to allow for deinterleaving by retrieving values from the plurality of memory banks; wherein the storing pattern comprises a plurality of cycles, each cycle indicating a selected subset of the plurality of memory banks and an address offset value for each memory bank in the selected subset, each of the memory banks in the selected subset for storing one of the plurality of third values, respectively; wherein the number of cycles is six, and wherein: