Patent ID: 8252675
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A method of forming an insulated-gate transistor, comprising: forming a gate insulating layer on a substrate; forming a metal buffer gate electrode layer on the gate insulating layer; forming a dummy gate electrode layer on the buffer gate electrode layer, said dummy gate electrode layer and said buffer gate electrode layer comprising different materials; patterning the dummy gate electrode layer and the buffer gate electrode layer in sequence to define a buffer gate electrode on the gate insulating layer and a dummy gate electrode on the buffer gate electrode; forming electrically insulating spacers on sidewalls of the dummy gate electrode and on sidewalls of the buffer gate electrode; covering the spacers and the dummy gate electrode with an electrically insulating mold layer; removing an upper portion of the mold layer to expose an upper surface of the dummy gate electrode; removing the dummy gate electrode from between the spacers by selectively etching back the dummy gate electrode using the mold layer and the spacers as an etching mask; depositing a first metal layer onto an upper surface of the mold layer and onto inner sidewalls of the spacers and onto an upper surface of the buffer gate electrode; filling a space between the inner sidewalls of the spacers by depositing a second metal layer onto a portion of the first metal layer extending between the inner sidewalls of the spacers to thereby define a metal gate electrode comprising a composite of the second metal layer, a portion of the first metal layer having a U-shaped cross-section and the buffer gate electrode.