Patent ID: 9224740
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method of deep trench isolation comprising: forming a semiconductor on insulator (SOI) substrate comprising a bulk semiconductor substrate, a buried insulator layer and a semiconductor layer on the buried insulator layer (SOI layer), one portion of the SOI substrate having a dynamic random access memory buried in the bulk semiconductor substrate (eDRAM) and a deep trench fin contacting the eDRAM and a second portion of the SOI substrate having an SOI fin in contact with the buried insulator layer; conformally depositing a layer of oxide on the deep trench fin and the SOI fin; conformally depositing a layer of high-k dielectric material on the oxide; conformally depositing a sacrificial oxide on the high-k dielectric material; stripping the sacrificial oxide over the SOI fin to expose the high-k dielectric material over the SOI fin while avoiding stripping the sacrificial oxide over the deep trench fin contacting the eDRAM; and stripping the exposed high-k dielectric material over the SOI fin to expose the oxide layer over the SOI fin.