Patent ID: 6792501
Filing Date: 2004-09-14
Classification: G06F

Abstract:
A universal serial bus flash memory integrated circuit device comprising:a universal serial bus for connecting the flash memory device to a host computer; at least one flash memory module for storing data; a flash memory interface for controlling read and write commands sending to said at least one flash memory module having at least a mother block; a flash memory extension interface for enabling the universal serial bus flash memory integrated circuit device to be electrically connected to external flash memories, a universal serial bus interface for communication between said at least one flash memory module and the host computer; and a controller for controlling commands and data between the host computer and the universal serial bus flash memory integrated circuit device and for managing data in the flash memory module, said controller comprising: a system buffer for buffering between the host computer and the flash memory device; a microprocessor for executing commands with parameters from the host; and a state machine for creating read and write timing to the system buffer; wherein for writing data into the flash memory module, said controller checks whether or not a child block exist in the flash memory module; if the child block exist in the flash memory module, the controller checks whether or not the data to be written is equal to a last memory logical block that was previously written; if the data to be written is found to be not equal to the last memory logical block, the data is moved from the mother block to the child block, then the mother block is erased then a link table in the controller is undated substituting an original mother block address with a child address and the erased mother block is nut back into FIFO queue as a clean block; if the data to be written is found to be equal to the last memory logical block, the controller checks whether the current flash memory logical page number to check the data to be written is larger than the flash memory logical page; if a current write pane number is equal to a last write ease number plus 1, the data from the host to the flash memory module is written in the system buffer and the sector count is decremented, and if the child block does not exist, a clean block is taken from the FIFO queue to create a child block in response to a write command, the controller checks whether or not the data to be written is equal to 0; if the data to be written is not equal to 0, the controller moves the data from the mother block to the child block between the last page written and the current write page sections and if the sector count number is equal to 0, the writing operation is ended.