Patent ID: 7675125
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A NAND type flash memory device, comprising: a substrate comprising a memory region and a peripheral region; a device isolation layer formed in the substrate to define a string active region extending in a first direction within the memory region and to define a peripheral active region extending in the first direction within the peripheral region; a common source region and a common drain region formed in the string active region, wherein the common source region and the drain region are separated from each other; a first insulating layer formed on the substrate and having a source groove; a source line filling the source groove, the source line being connected to the common source region; a peripheral lower plug penetrating the first insulating layer and connected to the peripheral active region; a second insulating layer covering an entire surface of the substrate; a peripheral upper plug penetrating the second insulating layer and connected to the peripheral lower plug; and a bit line plug filling a bit line contact hole sequentially penetrating the second and first insulating layers and connected to the common drain region, wherein the bit line plug has a top surface with a first width along the first direction and a second width, the second width is perpendicular to the first width, and the first width is greater than the second width, and the peripheral lower plug has a top surface with a width greater than the second width of the top surface of the bit line plug.