Patent ID: 7095817
Filing Date: 2006-08-22
Classification: G06F

Abstract:
1. A high speed digital circuit for use with an N bit digital data signal, where N is an integer, comprising: a. a source device for receiving said N bit digital data signal; b. a sink device coupled to said source device and receiving said N bit digital data signal from said source device, said N bit digital data signal having a skew when received by said sink device; c. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal; said skew detection circuit including a circuit for detecting the skew of each of N bits in said N bit digital data signal, generating N phase detection signals in response thereto, and multiplexing said N phase detection signals as said skew detection signal; d. a compensation circuit in said source device for receiving said skew detection signal and compensating for said skew in said N bit digital data signal in response thereto; and said source device outputs a reference signal to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal.