Patent ID: 6812096
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A fabrication method for a flash memory device that comprises a self-aligned contact, the method comprising:forming a plurality of first stacked layers over a substrate, wherein each of the plurality of first stacked layers is formed with a gate dielectric layer and a conductive layer; forming bit lines in the substrate beside both sides of each of the plurality of first stacked layers; filling a first dielectric layer in between the plurality of first stacked layers; patterning the conductive layer of the plurality of first stacked layers in a direction perpendicular to a direction of the bit lines to form a plurality of floating gates in a plurality of rows; filling a second dielectric layer in between the plurality of floating gates; forming second stacked layers over the plurality of floating gates of a same row, wherein each second stacked layers is formed with a dielectric thin layer, a control gate and cap layer; forming a spacer on a side wall of each second stacked layers; forming a third dielectric layer over the substrate, covering the second stacked layers; patterning the third dielectric layer and the first dielectric layer to form a self-aligned contact opening between two neighboring second stacked layers to expose some of the bit lines; and filling a conductive material in the self-aligned contact opening.