Patent ID: 8055813
Filing Date: 2011-11-08
Classification: G06F

Abstract:
1. A digital circuit for communicating data from a processor to a plurality of register groupings, comprising: a. a plurality of registers in which each register is associated with one of the plurality of register groupings; b. a plurality of register decoding logic entities arranged in a data communication ring and each of the plurality of register decoding logic entities assigned to a register grouping of the plurality of register groupings, each of the register decoding logic entities in data communication with each of the registers associated with the register grouping to which the register decoding logic entity is assigned, the plurality of register decoding logic entities including a first decoding logic entity in communication with the processor, each of the plurality of register decoding logic entities in data communication with two other of the plurality of register decoding logic entities, each register decoding logic entity being configured to: