Patent ID: 6247084
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A unified memory system comprising:a processor;a memory controller;a plurality of bus transactor circuits;a shared memory port, including a memory address interface, a memory control interface and a memory data interface, which are coupled to the memory controller;a processor bus which is coupled between the processor and the memory controller;a first multiple-bit, bidirectional system data bus which is coupled between the memory data interface of the shared memory port, the memory controller and the plurality of bus transactor circuits and which carries memory data between the memory data interface and the plurality of bus transactor circuits; anda second multiple-bit, bidirectional system command bus which is coupled between the memory controller and the plurality of bus transactor circuits and which carries non-memory data, including requests for access to the memory data interface over the data bus and memory addresses related to the memory data, between the memory controller and the plurality of bus transactor circuits.