Patent ID: 6477690
Filing Date: 2002-11-05
Classification: G06F

Abstract:
An in-place method for inserting interconnect repeaters in an integrated circuit, said integrated circuit comprising a silicon layer, an interconnect layer layered over said silicon layer, and zero or more intervening layers layered between said interconnect layer and said silicon layer, said method comprising the steps of:defining a set of legal repeater areas on said interconnect layer; reserving metal on each of said interconnect layer and said zero or more intervening layers for connecting repeaters implemented on said silicon layer to interconnects passing over said defined set of legal repeater areas; routing at least one interconnect without inserting repeaters, said at least one interconnect passing over at least one of said defined set of legal repeater areas; calculating a set of optimal constrained repeater locations for said at least one interconnect, said optimal constrained repeater locations defined by the optimal number and locations of repeaters along said at least one interconnect as constrained to said at least one of said defined set of legal repeater areas over which said at least one interconnect passes and which will result in acceptable timing criteria; and stitching a repeater in-place at each of said optimal constrained repeater locations associated with said at least one interconnect.