Patent ID: 6103577
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of manufacturing flash memory, comprising the steps of:providing a semiconductor substrate, and then forming a pad oxide layer and a mask layer over the substrate;performing a photolithographic and an etching operation to pattern the pad oxide layer and the mask layer, at the same time etching out a shallow first trench in the substrate;performing a first ion implantation using the mask layer as a mask to form a buried doped region in the substrate underneath the first trench;performing a photolithographic and an etching operation to form a deep second trench in the substrate for device isolation, wherein the second trench overlaps with a portion of the first trench, while the first trench is formed only in places where a common source region is ultimately formed;depositing insulating material into the first trench and the second trench, then removing the mask layer and the pad oxide layer so that a planar insulation layer whose upper surface is at the same height level as the top of the substrate is obtained;forming a first polysilicon layer and a dielectric layer over the substrate, and then patterning, the first polysilicon layer and the dielectric layer,forming a second polysilicon layer over the semiconductor substrate, and then patterning the second polysilicon layer such that the second polysilicon layer having a linear structure stretches across the substrate above first polysilicon layer, and the first polysilicon layer, the dielectric layer and the second polysilicon layer together form a stacked gate structure; andperforming a second ion implantation using the second polysilicon layer as a mask, thereby forming a surface source region and a drain region on each side of the second polysilicon layer, such that the surface source region and the buried doped region are joined alternately to form a common source region.