Patent ID: 6272056
Filing Date: 2001-08-07
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a logic circuit generating a clock signal, an address signal and a command signal to transmit and receive a data signal; anda memory circuit in response to activation of said command signal to perform reading and writing operations for said data signal according to said address signal,said memory circuit including:a) a memory cell array having a plurality of normal memory cells arranged in rows and columns;b) a redundant circuit for replacing a normal memory cell having a defect;c) an address decode circuit in response to activation of said clock signal generating an address decode signal for selectively activating one of rows and one of columns of said normal memory cells corresponding to said address signal;d) a redundancy control circuit in response to activation of said clock signal making a redundancy-based judgement for issuing an instruction to perform a redundancy-based repair operation if said address signal is associated with an address of said normal memory cell having the defect;e) a redundant decode circuit in response to result of said redundancy-based judgement for performing said redundancy-based repair operation; andf) an address latch circuit latching, in response to preceding activation of said clock signal before said command signal is activated, said address signal transmitted from said logic circuit, and transmitting said address signal to said address decode circuit and said redundancy control circuit.