Patent ID: 6252801
Filing Date: 2001-06-26
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a semiconductor substrate of a first conductivity type;first and second semiconductor regions of a second conductivity type which is opposite to the first conductivity type, the first and second semiconductor regions being formed in the semiconductor substrate apart from each other;a third semiconductor region of the first conductivity type formed in the first semiconductor region;a memory cell array including memory cells arranged in rows and columns, each memory cell including a transistor having first and second terminals, being capable of electrically erasing and rewriting data, and being formed in the semiconductor substrate;a plurality of word lines each connecting the transistor gates of the memory cells in a respective corresponding row of the memory cell array;a plurality of bit lines each connecting the first terminals of the transistors of the memory cells in a respective corresponding column of the memory cell array; anda word line selection circuit for selecting ones of the plurality of word lines in accordance with address information, whereinthe word line selection circuit comprises:a predecoder circuit having a plurality of output terminals; anda main decoder circuit for selecting ones of the plurality of word lines in response to an output from the plurality of output terminals of the predecoder circuit; andthe predecoder circuit comprises:a first level conversion circuit for receiving the address information, and outputting a first signal based on respective levels of a first logic high level voltage and a first logic low level voltage supplied thereto; anda second level conversion circuit, coupled to the first level conversion circuit, for outputting a second signal based on respective levels of a first voltage as a second logic high level voltage, and a second voltage as a second logic high level voltage supplied thereto, the first voltage having a positive value and the second voltage having a negative value in a data erase mode,the main decoder circuit comprises;a plurality of switches connected between the plurality of output terminals of the predecoder circuit and the plurality of word lines, each of the plurality of switches is a CMOS transfer gate having a first MOS transistor of a first channel type and a second MOS transistor of a second channel type which is opposite to the first channel type, the first MOS transistor being formed in the third semiconductor region and the second MOS transistor being formed in the second semiconductor region.