Patent ID: 6029260
Filing Date: 2000-02-22
Classification: G11C

Abstract:
A memory analyzing apparatus, comprising:a defect cell memory for storing data related to defective bits of a memory to be measured;an X line defect memory for counting the number of defective bits in X line direction for each X line on the basis of data related to the defective bits transferred from said defect cell memory, to label an X line including defective bits more than a previously determined number as a defective line;a Y line defect memory for counting the number of defective bits in Y line direction for each Y line on the basis of data related to the defective bits transferred from said defect cell memory, to label a Y line including defective bits more than a previously determined number as a defective line;a bit detect memory for storing addresses of the defective bits counted by said X line defect memory and said Y line defect memory, respectively;a defect number memory for storing the numbers of defective bits calculated on the basis of values counted by said X line defect memory and said Y line defect memory, respectively, anda processor for executing remedy processing of defective cells on the basis of data stored in said X line defect memory, said Y line defect memory, said bit defect memory, and said defect number memory, respectively.