Patent ID: 6594331
Filing Date: 2003-07-15
Classification: H03D,H03L,H04L

Abstract:
A phase locked loop (PLL) circuit in which a phase of data signal is locked with a first clock of which frequency is the half of said data signal, and a second clock of which phase is shifted by &pgr;/2 compared with said first clock is used for determining phase delay or phase advance of said data signal compared with said first clock, comprising:a voltage controlled oscillator for outputting said first clock and said second clock; a phase comparator for inputting said data signal, said first clock, and said second clock, and for outputting a first data sampled at fall down of said first clock, a second data sampled at rise up of said first clock, a first indication signal indicating said phase delay, and a second indication signal indicating said phase advance; and a filter for inputting said first indication signal and said second indication signal, and for outputting a control voltage which controls the phase of said first clock outputted from said voltage controlled oscillator, wherein said phase comparator comprises a data sampling circuit and a phase determination circuit, wherein said data sampling circuit comprises: a first determination means for outputting said first data, a second determination means for outputting said second data, a first delay flip-flop (DFF), and a second DFF, said data signal and an inverted signal of said first clock being inputted into said first determination means, said data signal and said first clock being inputted into said second determination means, said data signal and said second clock being inputted into said first DFF, and said data signal and an inverted signal of said second clock being inputted into said second DFF, and wherein said phase determination circuit comprises: a first AND circuit, a second AND circuit, a third AND circuit, a fourth AND circuit, a first OR circuit for outputting said first indication signal, and a second OR circuit for outputting said second indication signal, an inverted signal output from said first determination means, a positive signal output from said second determination means, and a positive signal output from said first DFF being inputted into said first AND circuit, the inverted signal output from said first determination means, the positive signal output from said second determination means, and an inverted signal output from said first DFF being inputted into said second AND circuit, the positive signal output from said first determination means, an inverted signal output from said second determination means, and a positive signal output from said second DFF being inputted into said third AND circuit, the positive signal output from said first determination means, the inverted signal output from said second determination means, and the inverted signal output from said second DFF being inputted into said fourth AND circuit, the output from said first AND circuit and the output from said third AND circuit being inputted into said first OR circuit, and the output from said second AND circuit and the output from said fourth AND circuit being inputted into said first OR circuit.