Patent ID: 6154827
Filing Date: 2000-11-28
Classification: G06F,G11C

Abstract:
A data processor having a central processing unit (CPU) capable of accessing larger data capacity than a data output capacity of a memory storing data, comprising:temporary storage means connected to data output terminals of a memory, for respectively storing data from said memory, corresponding respectively to first and second address signals applied sequentially, in first and second storage areas in response to first and second storage control signals sequentially applied, and for outputting the data stored in said first and second storage areas to said CPU via a data bus simultaneously, in response to a data output control signal of said CPU;signal generating means for generating said first and second storage control signals to be applied to said temporary storage means and address extension signals alternately having first and second logic states during a generating period of the data output control signal, in response to a least address signal component of input address signals provided from said CPU via an address bus and a system clock, in order to extend the address for the data; andaddress signal supplying means for providing joined signals by joining said address extension signals and the input address signals except the least address signal component, during said generating period of said data output control signal, and for supplying said joined signals to said memory as said first and second address signals, with said address extension signal having said first logic state being the least address signal of said first address signals and said address signal having said second logic state being the least significant bit of said second address signal.