Patent ID: 6483752
Filing Date: 2002-11-19
Classification: G11C

Abstract:
An erase method for a nonvolatile semiconductor memory device having electrically erasable and programmable floating gate field-effect transistors arranged in a matrix form so as to form a memory cell array, each memory cell having a control gate, a drain and a source, a plurality of word lines connected to the control gates of memory cells in each row, and a plurality of bit lines connected to the drains of memory cells in each column, the memory cell array being divided into a plurality of blocks including the memory cells of a plurality of rows and a plurality of columns, the sources of the memory cells in each block being commonly connected, and the memory cells in each block being commonly connected, and the memory cells in each block being connected together in a NOR type form, said erase method executing an erase operation in blocks and comprising:executing, for the memory cells connected to one word line in a certain block, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application; and executing a soft program operation for the memory cell after the second verify operation and before application of an erase pulse to a next word line when a memory cell that has undergone excessive erasure is found by the second verify operation, said pulse application, said first verify operation, and said second verify operation being executed word line by word line in the block.