Patent ID: 6590425
Filing Date: 2003-07-08
Classification: H03K

Abstract:
A parallel data processing apparatus comprising:a plurality of processors to process plural data in parallel, at least one of said processors including a plurality of series-connected logic circuits, wherein each of said logic circuits includes (i) a PMOS logic block having at least one P-type MOS transistor, (ii) a NMOS logic block coupled thereto and having at least one N-type MOS transistor, and (iii) a precharge circuit coupled solely between a high level source and an output part of said NMOS logic block and of said PMOS logic block, wherein the precharge circuits of said logic circuits, in synchronization with a clock signal, enable outputs of all of said logic circuits to be set to a low level in advance, and wherein each of said logic circuits, in response to an input signal applied thereto, provides an output signal which changes to a high level in accordance with said input signal changing from low level to high level and said at least one N-type MOS transistor turning ON.