Patent ID: 6212592
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A computer system for processing system management interrupt (SMI) requests, comprising:a first system management (SM) requester that asserts SMI requests;a second SM requester that asserts SMI requests;a processor coupled to the first and second SM requesters, the processor activating a system management mode in response to receiving an SMI request from one of the SM requesters;a system memory;a memory controller coupled to the processor and the system memory, the memory controller accessing a first SMI handler routine in the system memory if the processor activates system management mode in response to receiving an SMI request from the first SM requester and accessing a second SMI handler routine in the system memory if the processor activates system management mode in response to receiving an SMI request from the second SM requester, the memory controller includinga first SMI base address register that stores a first SMI base address corresponding to the first SMI handler routine;a second SMI base address register that stores a second SMI base address corresponding to the second SMI handler routine;a memory address register block that stores an address of information that is accessed from the system memory;first and second multiplexers, the first multiplexer having a first input coupled to the first SMI base address register, a second input coupled to the second SMI base address register, and an output coupled to a first input of the second multiplexer, the second multiplexer having a second input coupled to the processor, and an output coupled to the memory address register block; andan SMI state machine coupled to the processor, the first multiplexer, and the SMI base address registers, the SMI state machine causing the first multiplexer to transmit the first SMI base address to the second multiplexer in response to receiving from the processor an indication that the processor received an SMI request from the first SMI requester and causing the first multiplexer to transmit the second SMI base address to the second multiplexer in response to receiving from the processor an indication that the processor received an SMI request from the second SMI requester, the SMI state machine further causing the second multiplexer to load into the memory address register block whichever SMI base address is output by the first multiplexer when the computer system is in system management mode and allowing the second multiplexer to load into the memory address register block an address from the processor when the computer system is not in system management mode.