Patent ID: 6249799
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A multiplier circuit comprising:a first partial product generator for generating a first bit of a first partial product, said first bit having a first weight;a second partial product generator for generating a second bit of a second partial product, said second bit having said first weight;a third partial duct generator for generating a third bit of a third partial product, said third bit having said first weight;a fourth partial product generator for generating a fourth bit of a fourth partial product, said fourth bit having said first weight;an adder configured to receive said first, second, third and fourth bits, said adder configured to generate a first sum bit on a first sum terminal, a first carry bit on a first carry terminal and a second carry bit on a second carry terminal, said first carry bit and said second carry bit each having a second weight one digit more significant than said first weight;a summing circuit receiving said first carry bit and said second carry bit to generate a second sum bit on a second sum terminal;a first logic unit having an instruction terminal, an input terminal, and an output terminal, said input terminal of said logic unit coupled to receive said first carry bit from said first carry terminal, said first logic unit configured to provide said first carry bit on said output terminal in response to a first signal on said instruction terminal, said first logic unit configured to provide a bit on said output terminal that is independent of said carry bit in response to a second signal on said instruction terminal; anda second logic unit having an instruction terminal, an input terminal, and an output terminal, said input terminal of said second logic unit coupled to receive said second carry bit from said carry terminal, said logic unit configured to provide said second carry bit on said output terminal of said second logic unit in response to a third signal on said instruction terminal of said second logic unit, said second logic unit configured to provide a bit on said output terminal of said second logic unit that is independent of said second carry bit in response to a fourth signal on said instruction terminal of said second logic unit.