Patent ID: 7424693
Filing Date: 2008-09-09
Classification: G06F

Abstract:
1. A method for risk estimation comprising: identifying in a circuit a signal path having at least one cell with tied input pins; running a timing analysis on the signal path to determine a hold slack at the end of the signal path, wherein the hold slack is the difference of a worst case delay through the signal path and a cycle time of the circuit; estimating a risk to the signal path of incorrect timing analysis results, the risk related to a ratio of the delay through the at least one cell to the hold slack; generating for a signal path having a plurality of cells with tied input pins, a summation of the delays through the plurality of cells; determining a ratio of the summation to the hold slack, wherein the ratio represents the risk; determining a worst case delay reduction percentage for cells of a selected plurality of cells available in a technology library; selecting a representative worst case delay reduction percentage for the technology library based on the determined worst case delay reduction percentage for the cells; running an analog simulation for each cell with tied input pins in a signal path to determine an analog time delay for each cell; and comparing the analog time delay with a tool time delay associated with each cell, where the tool time delay is determined from the timing analysis tool, the comparison is used to determine the worst case delay reduction percentage.