Patent ID: 7863742
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a dielectric layer; a copper feature in the dielectric layer, wherein a top surface of the copper feature is substantially level with a top surface of the dielectric layer; a passivation layer over, and formed of a different material from, the dielectric layer; a via opening in the passivation layer; a copper-containing via in the via opening and physically contacting the copper feature; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via and a portion of the passivation layer are exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-containing via; and an under-bump metallurgy (UBM) over and electrically coupled to the PPI line.