Patent ID: 6323794
Filing Date: 2001-11-27
Classification: H03M

Abstract:
A .DELTA..SIGMA. modulator comprising:(A) 1-bit first to (k-1)th (k.gtoreq.2) modulators of second-order or less, each m-th (1.ltoreq.m.ltoreq.k-1) modulator comprising, along a first feedback loop, (A-1) an integrator, (A-2) a quantizer for performing quantization by 1-bit, connected to an output of said integrator, and (A-3) a first arithmetic operation unit disposed between an output of said quantizer and an input of said integrator, in which an input signal to said m-th modulator and a reverse signal of a signal from said quantizer are added and, in case that a feedback signal to said m-th modulator is present, said feedback signal is further added to transmit a result to said integrator, said each m-th modulator further comprising (A-4) a delay circuit having a predetermined order which delays signal transmission and is disposed within said first feedback loop, and (A-5) a second arithmetic operation unit which outputs a reverse signal of an error signal of said quantizer, as an input signal of a next stage modulator;(B) a multi-bit k-th modulator of second-order or less, comprising, along a second feedback loop, (B-1) an integrator, (B-2) a quantizer for performing quantization by a multi-bit, connected to an output of said integrator (B-1), and (B-3) a first arithmetic operation unit disposed between an output of said quantizer and an input of said integrator, in which an input signal to said k-th modulator and a reverse signal of a signal from said quantizer (B-2) are added to transmit the result to said integrator (B-1), said k-th modulator further comprising (B-4) a delay circuit having a predetermined order which delays signal transmission and is disposed within said second feedback loop; and(C) first to (k-1)th feedback arithmetic operation units, each i-th (1.ltoreq.i.ltoreq.k-1) feedback arithmetic operation unit being connected to an output of said quantizer of said (i+1)th modulator, comprising (C-1) a leading circuit having an order which cancels sum of orders of delay circuits along a path from said first arithmetic operation unit of said t-th (1.ltoreq.t.ltoreq.i) modulator to said i-th feedback arithmetic operation unit, and (C-2) a differentiator circuit having an order which cancels sum of orders of integrators along a path from said first arithmetic operation unit of said (t+1)th modulator to said i-th feedback arithmetic operation unit, thereby a result of arithmetic operation is transmitted, as said feedback signal, to said first arithmetic operation unit of said t-th modulator.