Patent ID: 6864753
Filing Date: 2005-03-08
Classification: H03K,H03L

Abstract:
1. A phase-locked frequency synthesizer, comprising: a phase-frequency detector (PFD) for comparing a phase of a reference signal with a phase of a feedback signal and generating Up and Down signals, depending on whether the phase of the reference signal leads or lags the phase of the feedback signal; first and second charge pumps (CPs) for generating positive and negative charge pulses in response to the Up and Down signals from the phase-frequency detector; a delay element for delaying the positive and negative charge pulses from the second charge pump; a loop filter for integrating the positive and negative charge pulses from the first charge pump and the delayed positive and negative charge pulses from the second charge pump, and for generating a control voltage in response thereto; a voltage-controlled oscillator (VCO) for accepting the control voltage from the loop filter and for changing a frequency of an output of the VCO in response thereto; and a divider for dividing the output of the VCO and generating the feedback signal therefrom.