Patent ID: 8536622
Filing Date: 2013-09-17
Classification: G05F,H01L

Abstract:
1. A semiconductor device comprising: a first transistor including a first GaN-based semiconductor stacked structure formed over a substrate, a first gate electrode having a plurality of first fingers over the first GaN-based semiconductor stacked structure, a plurality of first drain electrodes provided along the first fingers, and a plurality of first source electrodes provided along the first fingers; a second transistor including a second GaN-based semiconductor stacked structure formed over the substrate, a second gate electrode having a plurality of second fingers over the second GaN-based semiconductor stacked structure, and a plurality of second drain electrodes provided along the second fingers, and a plurality of second source electrodes provided along the second fingers; a drain pad provided over or under the plurality of first drain electrodes, and coupled to the plurality of first drain electrodes; a source pad provided over or under the plurality of second source electrodes, and coupled to the plurality of second source electrodes; and a common pad coupled to the plurality of first source electrodes and the plurality of second drain electrodes; a common interconnection layer coupled to the plurality of first source electrodes and the plurality of second drain electrodes; a plurality of first through holes provided in the substrate and the first GaN-based semiconductor stacked structure; a plurality of first contacts provided, respectively, in the plurality of first through holes and coupled, respectively, to the plurality of first source electrodes; a plurality of second through holes provided in the substrate and the second GaN-based semiconductor stacked structure; and a plurality of second contacts provided, respectively, in the plurality of second through holes and coupled, respectively, to the plurality of second drain electrodes, wherein the common interconnection layer is provided on the substrate under the plurality of first source electrodes and the plurality of second drain electrodes, the common interconnection layer being coupled to the respective first source electrodes via the respective first contacts and coupled to the respective second drain electrodes via the respective second contacts, and the common pad is coupled to the plurality of first source electrodes and the plurality of second drain electrodes via the common interconnection layer.