Patent ID: 6197675
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising the steps of:forming a first conducting layer above a main surface of a semiconductor substrate, the first conducting layer being the same layer as a capacitor upper electrode of a capacitor formed on the semiconductor substrate;forming a third conducting layer above the main surface of the semiconductor substrate;forming a first interlayer insulating film on the first conducting layer;forming a first contact hole in the first interlayer insulating film;forming a first via-conductor in the first contact hole;forming a second interlayer insulating film on the third conducting layer;forming a second contact hole in the second interlayer insulating film;forming a second via-conductor in the second contact hole;forming a second conducting layer on the first interlayer insulating film and the second interlayer insulating film, the second conducting layer being connected to the first conducting layer through the first via-conductor and connected to the third conducting layer through the second via-conductor, andforming a device electrically connecting the capacitor upper electrode to the semiconductor substrate which operates when a voltage over a predetermined voltage is applied to the capacitor upper electrode,wherein the step of forming the first contact hole includes a step of forming at least a lower area of the first contact hole by an etching method free from generating electrical potential variation to the first conducting layer; andthe step of forming the second contact hole includes a step of forming at least a lower area of the second contact hole by an anisotropic etching method.