Patent ID: 6765977
Filing Date: 2004-07-20
Classification: H03J,H03L

Abstract:
A phase locked loop (PLL) frequency synthesizer having a loop divide ratio and comprising:a voltage controlled oscillator (VCO) to provide a VCO frequency signal; a frequency offset circuit including a mixer accepting the VCO frequency signal and a signal from a second oscillator, and producing a shifted-frequency signal having a frequency significantly lower than the VCO output frequency; a programmable divider accepting the shifted-frequency signal and dividing the frequency of the shifted-frequency signal by a settable amount; a phase detector to compare the phase of the output of the programmable divider to that of a reference oscillator and produce a phase difference signal; a loop filter to filter a function of the phase difference to produce a control input to the VCO, and a prescaler connected in parallel with the frequency offset circuit, with one or more switchable elements to switch between using the prescaler or the frequency offset circuit to produce a signal for the divider that has a frequency significantly lower than the VCO output frequency, wherein the offset circuit shifts down the frequency without increasing the divide ratio of the loop as would a prescaler achieving the same frequency conversion as the frequency offset circuit.