Patent ID: 6294438
Filing Date: 2001-09-25
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device comprising:a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated,a step of forming an interlayer insulating layer that covers the capacitor,a step of forming contact holes reaching the integrated circuit, and the top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer,a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, anda step of sequentially forming a passivation layer composed of a phospho-silicate layer and a non-doped silicate layer that covers the interconnections.