Patent ID: 9093319
Filing Date: 2015-07-28
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising a memory cell of a nonvolatile memory, and a capacitive element which are formed over a semiconductor substrate, said memory cell comprising: a first gate electrode formed over the semiconductor substrate and comprised of silicon; a second gate electrode arranged over the semiconductor substrate, formed adjacent to the first gate electrode, and comprised of silicon; a first insulating film formed between the first gate electrode and the semiconductor substrate; and a second insulating film formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode, said second insulating film having therein a charge storing portion, said capacitive element comprising: a first electrode formed over the semiconductor substrate and comprised of silicon; and a second electrode formed over the first electrode via a capacity insulating film and comprised of silicon, wherein a concentration of impurities of the second electrode is higher than that of impurities of the second gate electrode, wherein the first gate electrode and the first electrode are formed of the same layer of a first silicon film, wherein the second gate electrode and the second electrode are formed of the same layer of a second silicon film, wherein a resistance of the second electrode is lower than that of the second gate electrode, wherein the second insulating film and the capacity insulating film are formed of the same layer of an insulating film, wherein the first gate electrode and the first electrode are formed of the first silicon film into which impurities are introduce, wherein a metal silicide layer is formed over each of the second gate electrode and the second electrode, wherein the second gate electrode extends over the semiconductor substrate together with the first gate electrode, wherein the second gate electrode includes a contact extending from a position adjacent to a sidewall of the first gate electrode in a direction away from the first gate electrode, wherein a contact hole is formed in an interlayer insulating film over the contact, wherein a plug embedded in the contact hole is electrically coupled to the contact, and wherein a concentration of impurities of the contact is higher than that of the second gate electrode of the memory cell.