Patent ID: 6665212
Filing Date: 2003-12-16
Classification: G11C

Abstract:
A reference current generation circuit for a multiple bit flash memory having a plurality of reference current generation units, each reference current generation unit comprising:a loading having a first connection terminal and a second connection terminal, wherein the first terminal is connected to an operating power source; and a reference memory cell having a substrate terminal, a gate terminal, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is connected to the second connection terminal of the loading, the second source/drain terminal is connected to ground, the gate terminal is connected to a boosted word-line voltage terminal and the substrate terminal is connected to a substrate voltage terminal; wherein the gate terminal of each reference current generation unit is connected to an identical boosted word-line voltage terminal and the substrate voltage supplied to the substrate terminal of each reference current generation unit depends on the size of reference current that needs to be generated by the reference current generation unit.