Patent ID: 6477081
Filing Date: 2002-11-05
Classification: G11C

Abstract:
An integrated memory, comprising:a plurality of column lines; a plurality of row lines; memory cells each connected between a respective one of said column lines and a respective one of said row lines, said memory cells having a magnetoresistive storage property; a sense amplifier connected to said column lines; a terminal for providing a selection signal; said row lines respectively being connectable to said terminal in order to selectively read a data signal from a selected one of said memory cells and write a data signal to said selected one of said memory cells via one of said column lines connected to said selected one of said memory cells; and a control device controlling said sense amplifier such that at least one of said column lines not connected to said selected one of said memory cells and connected to at least one defective one of said memory cells causing a short-circuit between in each case one of said row lines and one of said column lines is electrically isolated in said sense amplifier for selectively reading and writing the data signal.