Patent ID: 6457101
Filing Date: 2002-09-24
Classification: G06F

Abstract:
For use in a directory-based memory system including a main memory coupled to multiple cache memories, each of the cache memories being capable of generating fetch requests to obtain data signals from the main memory, the main memory being capable of issuing return requests to retrieve a copy of any of the requested data signals from any of the multiple cache memories to be provided to a requesting one of the cache memories, a speculative return system, comprising:a speculative return generation logic circuit coupled to receive a fetch request from any of predetermined ones of the multiple cache memories, and in response to each said fetch request, to generate a speculative return request to a predetermined non-requesting one of the cache memories; and a function processing logic circuit coupled to receive from said speculative return generation logic circuit each said speculative return request, and in response thereto, to cause said predetermined non-requesting one of the cache memories to retrieve from associated other ones of the cache memories coupled to said predetermined non-requesting one of the cache memories any of the data signals requested by said fetch request and that are stored by said associated other ones of the cache memories, whereby any of the data signals transferred to said predetermined non-requesting one of the cache memories is more readily available for retrieval by the main memory in response to an issued return request.