Patent ID: 6815285
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of forming a dual gate, comprising:providing a semiconductor substrate having an NMOS transistor region and a PMOS transistor region; forming a gate insulating layer on the semiconductor substrate; forming an initial metal nitride layer on the gate insulating layer, opposite to the semiconductor substrate; implanting nitrogen ions into the initial metal nitride layer in the PMOS transistor region to form a nitrogen-rich metal nitride layer; patterning the initial metal nitride layer to form an NMOS transistor gate electrode in the NMOS transistor region; and patterning the nitrogen-rich metal nitride layer to form a PMOS transistor gate electrode in the PMOS transistor region, wherein a work function of the nitrogen-rich metal nitride layer is higher than that of the initial metal nitride layer.