Patent ID: 9099338
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, the method comprising: providing a semiconductor substrate having a NMOS region and a PMOS region; forming dummy gate structures having a stacked sacrificial gate material layer over a sacrificial dielectric layer in the NMOS and PMOS regions; concurrently removing the sacrificial gate material layer and the sacrificial dielectric layer to form a groove in the dummy gate structure in the NMOS region and a groove in the dummy gate structure in the PMOS region; forming a first high-K dielectric layer in the grooves of the NMOS and PMOS regions and a first metal gate over the first high-K dielectric layer; forming a hard mask over the NMOS region; removing the first metal gate layer and the first high-K dielectric layer of the dummy gate structure in the PMOS region using the hard mask as a mask to form a channel groove in the semiconductor substrate; forming a second high-K dielectric layer in the channel groove; forming a second metal gate over the second high-K dielectric layer; and removing the hard mask.