Patent ID: 6266717
Filing Date: 2001-07-24
Classification: G06F

Abstract:
A system for controlling an exchange of data between a host bus of a host device and an input/output register of a processing circuit which operates on a plurality of bits organized into subfields of variable size, each subfield comprising a smaller plurality of bits, the system comprising:an interface circuit for connection between the host bus and the input/output register, the interface circuit spreading data when writing data from the host bus into the input/output register, and despreading data when reading data from the input/output register to the host bus; anda control unit connected to the interface circuit for controlling the interface circuit according to a spreading/despreading pattern based on a subfield processing size of the processing circuit,wherein the control unit controls the interface circuit to spread bits of a host bus word from the host bus to bit positions of the input/output register such that bit positions of the input/output register corresponding to a subfield contain as many bits of a host bus word as the subfield processing size of the processing circuit and wherein the control unit controls the interface circuit to despread bits of the input/output register when reading data from the input/output register to the host bus to reconstruct host bus words from bits in the input/output register according the subfield processing size of the processor circuit.