Patent ID: 6374329
Filing Date: 2002-04-16
Classification: G06F,H03K

Abstract:
An external-cache controller for a plurality of processor clusters within a computer having a main memory, each cluster being in inter-cluster communication over a common communication bus, and each cluster having at least one microprocessor having a processor bus and a private processor cache, the contents of each such private cache being unknown externally to its associated microprocessor, the controller comprising:a. an external tag memory for storing a status of the private processor cache associated with a first processor duster, the external tag memory non-hardwired to the private processor cache associated with the first processor cluster; b. a data-request monitor for monitoring a data request from a second processor cluster; and c. a tag controller associated with the first processor cluster for managing the external tag memory, the tag controller deriving the status of the private processor cache associated with the first processor cluster by tracking evicted cache lines and data entering and exiting the first processor cluster, the tag controller checking the tag memory to determine if a response to the request corresponds to data in the private processor cache associated with the first processor duster.