Patent ID: 7667506
Filing Date: 2010-02-23
Classification: G06F,H03K

Abstract:
1. A power-on-reset circuit included in an integrated circuit powered by a supply voltage, the integrated circuit having a first critical sub-circuit that is not part of the power-on-reset circuit, the first critical sub-circuit having a total critical sub-circuit operating voltage drop, the total critical sub-circuit operating voltage drop comprising at least first, second and third operating voltage drops across respective first, second and third critical sub-circuit transistor elements, the first, second and third critical sub-circuit transistor elements being coupled in series, the first, second and third critical sub-circuit transistor elements having desired operating currents that define the first, second and third voltage drops, at least one of the first, second or third critical sub-circuit transistor elements being a PMOS transistor element and at least one being an NMOS transistor element, the power-on reset circuit comprising: first, second and third mimic transistor elements, the first, second and third mimic transistor elements being coupled in series, the first, second and third mimic transistor elements being respective PMOS or NMOS transistor elements so as to correspond to the same type of transistor elements as the respective first, second and third critical sub-circuit transistor elements; and a margin voltage drop portion, wherein: the first, second and third mimic transistor elements provide mimic voltage drops that approximate the voltage drops across the respective first, second and third critical sub-circuit transistor elements; the margin voltage drop portion provides a margin voltage drop; and a total mimic plus margin voltage drop of the power-on reset circuit approximates the total critical sub-circuit operating voltage drop plus the margin voltage drop during operation of the integrated circuit.