Patent ID: 6501699
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of operating modes, comprising:a memory cell array having dynamic memory cells; a refresh controller having a refresh timer for generating a refresh timing signal used to determine timing for performing refresh operations on the memory cell array, the refresh controller performing refresh operations on the memory cell array in response at least to the refresh timing signal; an operating mode input terminal for receiving from an external device an operating mode signal specifying one of the plurality of operating modes of the semiconductor memory device; address input terminals for receiving a multiple-bit address signal from the external device; and an address transition detecting circuit for detecting changes in the multiple-bit address signal to generate an address transition signal; wherein (i) in an event that the operating mode signal specifies a first operating mode, the refresh controller performs an internal refresh operation according to a first refresh mode wherein a refresh operation on the memory cell array is initiated in sync with the address transition signal after the refresh timing signal has been generated; and (ii) in an event that the operating mode signal specifies a second operating mode, the refresh controller performs an internal refresh operation according to a second refresh mode wherein a refresh operation on the memory cell array is initiated in response to generation of the refresh timing signal, regardless of the address transition signal.