Patent ID: 9190130
Filing Date: 2015-11-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first replica delay section configured to delay a write enable signal by a delay time corresponding to arrangement locations of a plurality of unit memory regions to generate a first delay signal; a second replica delay section configured to delay the first delay signal by the delay time to generate a second delay signal; a column source signal generation unit configured to generate a first column source signal, which is delayed by the delay time as compared with the write enable signal, in response to the write enable signal and the first and second delay signals; and a column decoder configured to generate a column selection signal for write operation in response to the first column source signal, wherein the column source signal generation unit comprises: a first logic operation section configured to perform a first logic operation on the write enable signal and the first delay signal to generate a first set signal; a second logic operation section configured to perform a second logic operation on the first delay signal and the second delay signal to generate a first reset signal; and a third logic operation section configured to perform a third logic operation on the first set signal and the first reset signal to generate the first column source signal, wherein the first delay signal has a first delay phase substantially equal to a phase of the write enable signal, and the second delay signal has a second delay phase different from the phase of the write enable signal.