Patent ID: 6727548
Filing Date: 2004-04-27
Classification: G11C

Abstract:
In a memory cell including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising:at least one of the first NDR element and the second NDR element being implemented as an NDR-capable FET, said NDR-capable FET using a charge trapping mechanism to achieve an NDR behavior suitable for storing the data value; wherein charge traps are distributed in a charge trapping layer of said NDR capable FET so as to cause the memory cell to achieve a switching speed between 1 picosecond and 10 nanoseconds and a soft error rate of approximately 1,000 failures-in-time (FITs)/Mbit or less.