Patent ID: 6467057
Filing Date: 2002-10-15
Classification: G09G

Abstract:
A fault detection and correction circuit for determining whether transmitting signal from a first D-type Flip Flop (DFF) at present stage into input terminal of a second DFF at next stage or transmitting signal from a third DFF at present stage through a scan bus into said second DFF, said fault detection and correction circuit comprising:first detecting means for generating a first logic level at output terminal of said first detecting means responding to a stuck-at-zero fault happened in said first DFF, said first DFF, said second DFF, said third DFF, and said scan bus being formed on a substrate, output terminal of a fourth DFF at previous stage being coupled to input terminal of said first detecting means; second detecting means for generating said first logic level at output terminal of said second detecting means responding to a stuck-at-one fault happened in said first DFF; control signal generating means for generating a first control signal when all input terminals of said control signal generating means exhibiting a second logic level, said control signal generating means generating a second control signal when one of input terminals of said control signal generating means exhibiting said first logic level, output terminals of said first detecting means and said second detecting means being coupled to input terminals of said control signal generating means; and transmission control means for transmitting signal from said first DFF to said second DFF and said scan bus responding to said first control signal, said transmission control means cutting off electrical coupling between said first DFF and said second DFF as well as said scan bus responding to said second control signal, and then signal from said third DFF being transmitted through said scan bus to said second DFF, one side of said scan bus being electrically coupled to said first DFF locating at one side of said substrate, the other side of said scan bus being electrically coupled to said second DFF locating at the other side of said substrate, said stuck-at-zero fault being defined as any DFF permanently having output equal to logic zero in spite its input, said stuck-at-one fault being defined as any DFF permanently having output equal to logic one in spite its input, activity of a plurality of thin film transistors being controlled by signal on said scan bus, electricity of said plurality of thin film transistors controlling orientation of polarity of molecules of liquid crystal of said pixel placed over said substrate.