Patent ID: 8560980
Filing Date: 2013-10-15
Classification: G01R

Abstract:
1. A method comprising: identifying, for an integrated circuit chip design for which manufacturing chip testing is to be optimized, at least one target metric; identifying, for said integrated circuit chip design for which manufacturing chip testing is to be optimized, n surrogate metrics in an n-dimensional surrogate metric space, n being at least two; modeling a relationship between said at least one target metric and said n surrogate metrics using a general joint probability density function; determining a chip disposition criterion based on said general joint probability density function, said chip disposition criterion comprising an acceptance region in said n-dimensional surrogate metric space which is unbounded by fixed threshold values and which determines, for a given physical chip putatively manufactured in accordance with said design, based on said n surrogate metrics for said given physical chip, whether said given physical chip is to be accepted or discarded during said manufacturing chip testing; and providing a system, wherein the system comprises at least one distinct software module, embodied in a non-transitory computer-readable storage medium, and wherein the distinct software module comprises a statistical analysis engine module; wherein said determining of said chip disposition criterion is carried out by said statistical analysis engine module executing on at least one hardware processor of a computer.