Patent ID: 8095699
Filing Date: 2012-01-10
Classification: G06F,Y02D

Abstract:
1. An interface adapted to transfer data between a host processor and an external coprocessor, the interface comprising: a master-side interface implemented on the host processor; a slave-side interface implemented on the coprocessor, the master-side interface configured to transfer information to and from a host processor bus internal to the host processor and the slave-side interface, the slave-side interface configured to transfer information to and from the master-side interface and a coprocessor bus internal to the coprocessor, and the interface adapted to perform a first read operation initiated by the master-side interface and a second read operation initiated by the slave-side interface; a first master-side synchronization component adapted to synchronize transfer of data to and from the host processor bus and a first master-side read buffer that stores read addresses and associated read data for use during the first read operation; and a second master-side synchronization component adapted to synchronize transfer of data to and from the first master-side read buffer and the slave-side interface, and to synchronize transfer of data from the slave-side interface to the second master-side read buffer that stores read data for use during the second read operation; a master-side write buffer configured to store a plurality of write addresses associated with locations on the coprocessor and to store write data to be written to the plurality of write addresses, a slave-side write buffer configured to store the write addresses and the write data; a plurality of physical lines for electrically connecting the host processor to the coprocessor over which the write addresses and write data may be transferred, wherein the second master-side synchronization component is adapted to transfer data from the master-side write buffer to the plurality of physical lines according to an interface clock shared by the master-side interface and the slave-side interface, the second master-side synchronization component configured to transfer a write address stored in the master-side write buffer to the plurality of physical lines on a first clock cycle of a write operation and to transfer associated write data stored in the write buffer to the plurality of physical lines on a second clock cycle of the write operation when in a first write mode, and the second master-side synchronization component configured to transfer the write data stored in the master-side write buffer to the plurality of physical lines on the first clock cycle when in a second write mode.