Patent ID: 8407433
Filing Date: 2013-03-26
Classification: G06F,G11C,Y02D

Abstract:
1. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein two or more memory channels make up a first aggregate target of the target IP cores, and the two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores, and the interconnect to implement chopping logic to chop individual two-dimensional (2D) transactions that cross memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, the two or more 2D transactions are chopped to fit within the memory channel address boundaries of the first aggregate target.