Patent ID: 6103592
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of manufacturing a semiconductor FET device employing a Shallow Trench Isolation (STI) method comprising the steps as follows:a) provide a doped silicon semiconductor substrate coated with a plurality of patterned pad layer structures on the surface of said substrate, and provide a patterned masking layer formed on said pad layer, which includes patterns for device mesas and dummy mesas,b) form a raised active silicon device mesa and form a dummy active silicon mesa, with said mesas having top surfaces capped with said pad layer structures, said mesas being formed with said patterns from said doped silicon semiconductor substrate, and said pad layer structures, said pad layer being below said patterned masking layer, then strip said masking layer leaving said pad layer structures on said substrate,c) deposit a conformal blanket silicon oxide layer covering said doped silicon semiconductor substrate and said raised active silicon device areas and said dummy active silicon mesas with said mesas remaining capped with pad structures with conformal projections of said blanket silicon oxide layer above said mesas,d) deposit a conformal blanket sacrificial layer on said blanket silicon oxide layer with additional conformal projections of said sacrificial layer above said mesas,e) initially planarize said blanket sacrificial layer to remove said additional conformal projections until said silicon oxide layer is exposed only over said pad structures,f) selectively RIE etch said blanket conformal silicon oxide layer partially, over said mesas,g) selectively etch away the remainder of said sacrificial layer,h) perform later planarizing of said conformal blanket silicon oxide layer, leaving said conformal blanket silicon oxide layer at a level above said top surface of said mesas and then remove said pad structures forming openings in said conformal blanket silicon dioxide layer, exposing top surfaces of said active silicon device mesas and top surfaces of said dummy active silicon mesas below said openings,i) next form a conventional gate oxide layer on said surface of said device mesas and said dummy mesas,k) form a gate conductor stack for said FET device with source/drain openings therethrough self-aligned with said gate conductor stack over said active silicon device mesas, andl) then form an FET device and a dummy doped region in said dummy active silicon device mesa by implantation of a dose of source/drain dopant ions into said active device areas and said dummy areas in said semiconductor substrate.