Patent ID: 7222272
Filing Date: 2007-05-22
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of memories of different address decode logics; logical circuits for controlling access to said plurality of memories, a common test bus connected to the plurality of memories; and a plurality of bridge circuits which convert test address information from said common test bus to an inherent bit format of each memory and supply said data to a corresponding memory, wherein the common test bus and the plurality of bridge circuits are provided in order to enable parallel tests by supplying in parallel the test address information to the plurality of memories from the common test bus and wherein at least one memory among the plurality of memories is a multi-port memory and the bridge circuit corresponding to said multi-port memory enables selection of a port connected to said common test bus and input of disturb information to the port selected not to be connected to said common test bus.