Patent ID: 9193583
Filing Date: 2015-11-24
Classification: B81C,G01L,H01L,H03H

Abstract:
1. A method comprising: providing a semiconductor substrate having first and second surfaces separated by the thickness of the semiconductor substrate, the first surface of the semiconductor substrate being one having or to have an electronic circuit fabricated within or upon; fabricating through the substrate a via, the via comprising at least a first opening in the first surface of the substrate and a second opening in the second surface of the substrate; filling a first predetermined portion of the via with a first electrically conductive material to provide an electrical connection from the first surface to the second surface and to provide an electrical connection to a microelectromechanical systems (MEMS) device; and after filling the first predetermined portion of the via with the first electrically conductive material, filling a second predetermined portion of the via with an electrically non-conductive filler material with a process having a maximum exposure to the substrate during manufacturing of at least one of 250° C., 300° C., and 350° C., the second predetermined portion of the via being the full interior volume of the via from the first surface of the substrate to a first predetermined depth from the second surface of the substrate.