Patent ID: 9171921
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A method for fabricating a trench MOSFET, comprising: providing a substrate having a body of a first conductivity type and an epitaxy layer of said first conductivity type on said body; forming a trench by etching said epitaxy layer; depositing a first insulating layer and a first polysilicon layer successively on said epitaxy layer, said first polysilicon layer filling said trench; forming a first gate in said trench by etching said first polysilicon layer; etching off an exposed portion of said first insulating layer, and depositing a second insulating layer and a second polysilicon layer successively, said second polysilicon layer filling said trench; forming a second gate in said trench by etching said second polysilicon layer; forming a well of a second conductivity type by performing a first ion implanting after etching off an exposed portion of said second insulting layer to expose said epitaxy layer; forming a source region of said first conductivity type by performing a second ion implanting at said surface of said well; depositing a third insulating layer on said source region and over said trench; forming a gate opening and a source opening by etching, said gate opening extending through said third insulating layer, said second gate, said second insulating layer and into said first gate, and said source opening extending through said third insulating layer, said source region and into said well; and forming metal plugs by filling a metal layer in said gate opening and in said source opening, respectively.