Patent ID: 8575986
Filing Date: 2013-11-05
Classification: H03K

Abstract:
1. A level shift circuit, comprising: an input port configured to receive an input signal; a first signal amplifying unit configured to amplify the received input signal; a node at the first signal amplifying unit to output the amplified signal; a level shift input port configured to receive a level shift voltage for controlling a DC level of the node; a first supply voltage configured to drive the first signal amplifying unit; a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage, wherein the first signal amplifying unit comprises: a second signal amplifying unit including a seventh transistor to which the first output signal is input, an eighth transistor to which the second output signal is input, and ninth and tenth transistors connected to the seventh and eighth transistors so as to be cross-linked; and an output port configured to output a level-shifted output signal from the ninth or tenth transistor side.