Patent ID: 7829953
Filing Date: 2010-11-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including an n-channel metal-oxide semiconductor (NMOS) region and a p-channel metal-oxide semiconductor (PMOS) region; a gate insulating layer formed on the semiconductor substrate; an n-channel metal-oxide semiconductor (NMOS) gate formed on the gate insulating layer of the NMOS region, wherein the NMOS gate consists essentially of a three-layered conductive layer pattern and a first portion of a gate electrode conductive layer pattern formed on the three-layered conductive layer pattern; and a p-channel metal oxide semiconductor (PMOS) gate formed on the gate insulating layer of the PMOS region, wherein the PMOS gate consists essentially of a one-layered conductive layer pattern and a second portion of the gate electrode conductive layer pattern formed on the one-layered conductive layer pattern.