Patent ID: 6144241
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A gate-array cell having large and small transistors, the gate-array cell comprising:a large p-channel active area having a first large p-channel transistor and a second large p-channel transistor, the first large p-channel transistor formed where a first polysilicon line crosses the large p-channel active area, the second large p-channel transistor formed where a second polysilicon line crosses the large p-channel active area;a small p-channel active area having a small p-channel transistor;an N-well tap for providing a substrate bias to bulk terminals of the first and second large p-channel transistors and the small p-channel transistor;a large n-channel active area having a first large n-channel transistor and a second large n-channel transistor, the first large n-channel transistor formed where a third polysilicon line crosses the large n-channel active area, the second large n-channel transistor formed where a fourth polysilicon line crosses the large n-channel active area;a small n-channel active area having a small n-channel transistor;a P-well tap for providing a substrate bias to bulk terminals of the first and second large n-channel transistors and the small n-channel transistor;wherein the small p-channel transistor has a maximum current drive of less than one-quarter of a maximum current drive of the first large p-channel transistor, and wherein a maximum current drive of the first large p-channel transistor is substantially equivalent to maximum current drive of the second large p-channel transistor; andwherein the small n-channel transistor has a maximum current drive of less than one-quarter of a maximum current drive of the first large n-channel transistor, and wherein a maximum current drive of the first large n-channel transistor is substantially equivalent to maximum current drive of the second large n-channel transistor,whereby the gate-array cell contains four large and two small transistors.