Patent ID: 8815663
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor (TFT), comprising: forming a buffer layer, an amorphous silicon layer, an insulating layer, and a first conductive layer on a substrate; forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer; forming a semiconductor layer, a gate insulating layer, and a gate electrode that have a predetermined shape by simultaneously patterning the polycrystalline silicon layer, the insulating layer, and the first conductive layer, wherein the polycrystalline silicon layer is further etched to produce an undercut recessed a distance compared to sidewalls of the insulating layer and the first conductive layer, wherein a width of the gate electrode is greater than a width of the semiconductor layer in a direction (a Y-axis direction) orthogonal to a direction (an X-axis direction) that a source region, a channel region and a drain region are to be arranged; forming the source region and the drain region within the semiconductor layer by doping corresponding portions of the semiconductor layer, the gate electrode corresponding to the channel region of the semiconductor layer that remains undoped, the gate electrode serves as a doping mask during the doping of the semiconductor layer; forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer covering the gate insulating layer; and forming a source electrode and a drain electrode that are electrically connected to the source region and the drain region respectively.