Patent ID: 6798857
Filing Date: 2004-09-28
Classification: H03L,H04L

Abstract:
A clock recovery circuit comprising:a transition detector having an input coupled to a data stream; a gate having a recovered clock as an input and a clock input coupled to an output of said transition detector; an accumulator circuit, coupled to an output of said gate, for accumulating in positive and negative directions based upon each output of said gate, wherein said accumulator circuit comprises a multiplexing circuit having a select input coupled to the output of said gate, a first input connected to a negative one input and a second input connected to a positive one input, and an accumulator having an input coupled to an output of said multiplexing circuit, and a clock input coupled to said output of said transition detector; a comparison circuit for comparing an output of said accumulator circuit to maximum and minimum thresholds; and a phase circuit, having an input coupled to an output of said comparison circuit, for changing a phase of said recovered clock in advance and retard directions responsive to advance and retard signal outputs of said comparison circuit.