Patent ID: 6799292
Filing Date: 2004-09-28
Classification: G01R

Abstract:
A method for generating a test pattern for a semiconductor integrated circuit having a first storage device located at a start point of a path selected from the circuit, and a second storage device located at end point of the path selected from the circuit, said second storage device comprising a scan circuit and said path including said scan circuit, said test pattern determines whether or not said second storage device will operate erroneously due to a hold error, said method comprising the steps of:generating the test pattern so that the path is sensitized and so that a signal, which is transmitted from said first storage device and passes through the path, changes its level within a time period; wherein said time period is a time period before and after a clock timing of a clock signal, and said clock timing of said clock signal is one clock cycle preceding a clock timing at which the data signal is properly received in the second storage device located at the end point of the path; and wherein an effective path in a capture operation is selected, and said clock signal corresponds to a capture clock signal, said capture clock signal causing a transition in the logic level output by said scan circuit.