Patent ID: 8239795
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. A timing analyzing system comprising: an RC extracting section configured to generate an SPEF (Standard Parasitic Exchange Format) file which contains resistance and capacitance components of wirings; a delay calculating section configured to generate an SDF (Standard Delay Format) file based on said SPEF file; a clock mesh calculating section configured to generate a corrected circuit model by simplifying a netlist on a clock path to pass through a clock mesh structure from an input stage; and a timing analysis section configured to perform timing analysis of a semiconductor integrated circuit of an analysis target based on said corrected circuit model, wherein said clock mesh calculating section comprises: a netlist editing tool; an SDF file editing tool; and an SPEF file editing tool, wherein said netlist editing tool specifies a clock mesh net formed of said clock mesh structure in a subsequent stage of an output pin of an instance of an input stage, and an input pin of a driver connected with said clock mesh net as a receiver, and generates a corrected netlist by connecting a pseudo external terminal to said input pin through a new net, wherein said SDF file editing tool reads a clock latency/dullness data indicating that the worst delay value from said instance to said driver and dullness of an input waveform of said driver, and generates a corrected SDF file by giving data contained in said clock latency/dullness data to said corrected netlist, wherein said SPEF file editing tool generates a corrected SPEF file by giving a dummy capacitance and a dummy resistance to a net from a pseudo external terminal to said driver based on said corrected netlist, and wherein said timing analyzing section performs timing analysis of said semiconductor integrated circuit based on said corrected netlist, said corrected SDF file and said corrected SPEF file.