Patent ID: 8650748
Filing Date: 2014-02-18
Classification: H01L,H05K,Y10T

Abstract:
1. A method of forming chip carriers comprising: providing a wire and rod support fixture having spaced apart first and second wire and rod alignment plates, each wire and rod alignment plate having a set of openings, the set of openings arranged in a pattern to define a a plurality of spaced apart two dimensional arrays of device areas; positioning a multiplicity of wires and rods in the fixture such that the wires and rods extend substantially in parallel between the first and second wire and rod alignment plates, each wire being received in an associated opening in each of the first and second wire and rod alignment plates and each rod being received in a corresponding opening in each of the first and second wire and rod alignment plates; encapsulating the wires and rods with an encapsulant material to form an encapsulant block that encases the substantially parallel wires and rods; and slicing the encapsulant block into a multiplicity of chip carrier panels, wherein each chip carrier panel has a plurality of device areas, wherein each device area has a multiplicity of conductive wire vias and rod vias extending therethrough that are formed from sections of the multiplicity of wires and rods.