Patent ID: 7788627
Filing Date: 2010-08-31
Classification: G03F,G06F

Abstract:
1. A computer-implemented method for verifying a lithographic process, comprising: defining a set of guard bands around a target pattern, wherein the target pattern is to be printed on a semiconductor die using a photo-mask in the lithographic process; using a processor to calculate an estimated pattern using a model of the lithographic process, wherein the model of the lithographic process includes a mask pattern corresponding to the photo-mask and a model of an optical path, wherein an inverse optical calculation was used to determine the mask pattern at an object plane in the optical path based at least in part on the target pattern at an image plane in the optical path and the model of the optical path, and wherein the model of the optical path includes information in addition to a magnification of the optical path; and determining if positions of differences between the estimated pattern and the target pattern exceeded one or more guard bands in the set of guard bands.