Patent ID: 7920987
Filing Date: 2011-04-05
Classification: G01R

Abstract:
1. A method, comprising: determining at a processor device a first set of test measurements based on a first test structure; determining at the processor device a first device under test (DUT) measurement based on an open test structure, a short test structure, and a through test structure and based on the first set of test measurements; determining at the processor device a second DUT measurement based on the open test structure and the short test structure and based on the first set of test measurements; calculating at the processor device an imperfection error based on the first DUT measurement and the second DUT measurement; determining at the processor device a set of intrinsic electrical characteristics for a device under test based on the open test structure, the short test structure, the through test structure, a left test structure and a right test structure and based on the imperfection error; and storing the set of intrinsic electrical characteristics.