Patent ID: 8685834
Filing Date: 2014-04-01
Classification: H01L

Abstract:
1. A fabrication method for a package structure, comprising: providing a wafer comprising a plurality of chips and a plurality of saw streets between the chips, the chips respectively comprising an active surface comprising a center region and periphery region, the periphery regions respectively comprising an electrode thereon; forming a patterned cover plate overlying the wafer, the patterned cover plate having a first opening to only expose the electrodes, a second opening to expose the saw streets and a portion of the patterned cover plate formed between the first opening and the second opening, wherein the first opening is formed between the center region of the chip and the second opening; dividing the wafer into independent chips, wherein the portion of the patterned cover plate formed between the first opening and the second opening is disposed apart from an edge of the chip and between the electrodes and the edge of the chip; providing a substrate comprising a terminal; attaching at least one of the chips to the substrate; electrically connecting the electrode and terminal via a conductive material; and forming an encapsulant covering the terminal, conductive material, and the electrode, while leaving the cover plate overlying the center region of the chip exposed.