Patent ID: 7302508
Filing Date: 2007-11-27
Classification: G06F

Abstract:
1. A method of performing a data transfer from an initiator unit to a target unit over a bus interconnecting the initiator unit and target units, the method comprising: providing a starting write address and write length information on the bus synchronously with a clock signal; while the starting write address and write length information are present on the bus, providing a write request signal that is activated and deactivated synchronously with a clock cycle of the clock signal; while the write request signal is deactivated, receiving from the target unit a grant signal that is activated and deactivated synchronously with a clock cycle of the clock signal; and after the grant signal is deactivated, providing a number of write data items on the bus synchronously with the clock for capture by the target unit, one data item provided in each clock cycle of the clock signal, the number of data items being determined by the write length information provided.