Patent ID: 8848767
Filing Date: 2014-09-30
Classification: H04J,H04L

Abstract:
1. A transceiver comprising: a first clock generator configured to locally generate a first clock, the transceiver communicating a digital signal encoded to include information of the first clock through a communication bus; a second clock generator configured to generate a second clock synchronized with the first clock, the second clock having a period corresponding to a duration of one bit of a digital signal on the communication bus; a sampling timing generator configured to, when first transmission data is supplied to the transceiver with being asynchronous to the second clock, detect start data of the first transmission data as a start timing, and generate sampling timings in response to the start timing, the sampling timings having intervals each of which is defined to correspond to the period of the second clock, the first sampling timing in the sampling timings being spaced from the start timing; a first sampling module configured to sample, at each of the sampling timings, the first transmission data, thus generating second transmission data; a second sampling module configured to sample, at each falling edge of the second clock, the second transmission data generated by the first sampling module, thus generating third transmission data synchronized with the second clock; and a transmitter configured to encode the third transmission data to a digital signal including information of the first clock, and transmit the digital signal through the communication bus.