Patent ID: 6541849
Filing Date: 2003-04-01
Classification: G11C,H01L

Abstract:
A memory chip, comprising:a substrate having four quadrants and further having two sides parallel a major axis of the substrate; a memory device fabricated on the substrate; and a plurality of first power input chip bond pads for receiving a first power input, the plurality of first power input chip bond pads fabricated on the substrate along each of the two sides and coupled to the memory device; a plurality of second power input chip bond pads for receiving a second power input, the plurality of second power input chip bond pads fabricated on the substrate along each of the two sides and coupled to the memory device; wherein at least one of the first power input chip bond pads is located in each of at least three of the quadrants of the substrate; wherein at least one of the first power input chip bond pads is located near a center of each of the two sides; wherein at least one of the second power input chip bond pads is located in each of at least three of the quadrants of the substrate; and wherein at least one of the second power input chip bond pads is located near a center of each of the two sides.