Patent ID: 7031200
Filing Date: 2006-04-18
Classification: G11C

Abstract:
1. A data output apparatus for a memory device, comprising: first and second local data lines for receiving data transferred from a pair of bitlines of; an amplifier interposed between the first and second local data lines; a first CMOS buffer means for receiving data on the first local data line; a second CMOS buffer means for receiving data on the second local data line; a first latch means for holding an output signal of the first CMOS buffer means; a second latch means for holding an output signal of the second CMOS buffer means; and a pull-up transistor and a pull-down transistor coupled in series between a driving voltage and a ground terminal; a first switch coupled between an input unit of the first latch means and a ground terminal; a second switch coupled between an input unit of the second latch means and the ground terminal; wherein, during a standby mode, the first and second switches are turned on thereby coupling the input units of the first and second latch means to the ground terminal and during an operating mode, the first and second switches are continually turned off; and wherein an output signal of the first latch means is applied to a gate of the pull-up transistor, while an output signal of the second latch means is applied to a gate of the pull-down transistor.