Patent ID: 7882460
Filing Date: 2011-02-01
Classification: G06F

Abstract:
1. A computer-implemented method of optimizing using a computer-aided design (CAD) tool to optimize a hierarchical circuit design containing at least one reused cell, the method comprising: performing a first optimization on the hierarchical circuit design with the CAD tool to meet a first objective subject to a first constraint that all instances of the at least one reused cell are kept identical, wherein the first objective is meeting a timing constraint and the first optimization is performed on a representative slice of the multi-bit data path; uniquifying the at least one reused cell with the CAD tool to create at least one uniquified instance of the at least one reused cell; and performing a second optimization with the CAD tool to meet a second objective allowing the at least one uniquified instance of the at least one reused cell to be independently modified and subject to a second constraint that the first objective remains met.