Patent ID: 6275901
Filing Date: 2001-08-14
Classification: G06F,Y02D

Abstract:
A computer system comprising a 2.sup.n way set associative cache memory subsystem (n>0) including a data array and a corresponding address tag array, characterized by (a) the two arrays being physically disposed in a chip boundary crossing manner, and (b) the two arrays being accessed in a sequential manner, when responding to a read access, and yet the two arrays function as a set associative cache memory,the chip boundary crossing manner comprising placing the address tag array inside a microprocessor chip while placing the data array outside the microprocessor chip in a single memory bank,the sequential manner comprising accessing the on-chip address tag array first for cache hit/miss determination and for generation of a cache address by combining n address bits with a plurality of set and line denoting address bits in accordance with the results of the cache hit/miss determination, and accessing only one of the 2.sup.n ways of the off-chip data array subsequently using the generated cache address.