Patent ID: 7821299
Filing Date: 2010-10-26
Classification: G09G

Abstract:
1. A matrix decoder, comprising: a plurality of first level shifters, used for boosting the voltages of inputted signals to the voltages required by high voltage components and outputting the boosted signals, one of the first level shifters receiving a first logic state and outputting a fifth logic state, each of the other first level shifters receiving a second logic state and outputting a sixth logic state; a plurality of second level shifters, used for boosting the voltages of inputted signals to the voltages required by high voltage components and outputting the boosted signals, one of the second level shifters receiving a third logic state and outputting a seventh logic state, each of the other second level shifters receiving a fourth logic state and outputting an eighth logic state; and a demultiplexer, used for outputting a ninth logic state and a plurality of tenth logic states according to the logic states outputted by the first level shifters and the second level shifters, wherein the demultiplexer includes a plurality of logic units; each of the logic units is coupled to one of the first level shifters and one of the second level shifters; if one of the logic units receives the fifth logic state and the seventh logic state, then the logic unit outputs the ninth logic state, otherwise the logic unit outputs the tenth logic state; and a plurality of output stages, each of the output stages being coupled to one of the logic units.