Patent ID: 6291898
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A ball grid array package comprising:a substrate having opposing upper and lower surfaces, the upper surface of the substrate being provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring, and the lower surface of the substrate being provided with a plurality of solder pads electrically connected to the ground ring, the power ring, and the conductive traces;a semiconductor chip disposed on the upper surface of the substrate, the chip having a plurality of bonding pads located about the periphery of the chip;the bonding pads of the chip being positioned in first, second, and third rows, the first, second, and third rows comprising, respectively, an inner row, a middle row, and an outer row along the sides of the chip, wherein the outer row of bonding pads consists of power supply pads and ground pads;a plurality of first bonding wires, wherein all of the outer row of bonding pads of the chip are respectively coupled to the power ring or the around ring of the substrate via the plurality of first bonding wires wherein each of the first bonding wires has a loop height of substantially the same value and is bonded to be approximately orthogonal to one side of the chip;a plurality of second bonding wires electrically connecting the middle row of bonding pads of the chip to corresponding conductive traces of the substrate, respectively, wherein each of the second bonding wires has a loop height of substantially the same value;a plurality of third bonding wires electrically connecting the inner row of bonding pads of the chip to corresponding conductive traces of the substrate, respectively, wherein each of the third bonding wires has a loop height of substantially the same value; anda package body formed over the semiconductor chip, the bonding wires and the upper surface of the substrate.