Patent ID: 6122726
Filing Date: 2000-09-19
Classification: G06F,H04N

Abstract:
In a data system for processing data, the system having a first stage and a second stage, an input data storage device (LDIN) and an output data storage device (LDOUT) in each said stage, with the output data storage device of said first stage connected to the input data storage device of said second stage, the combination comprising:electrical validation circuitry in said first stage to generate a validation signal (IN.sub.-- VALID, OUT.sub.-- VALID) for a first state when data stored in said first stage is valid and for a second state when data stored in said first stage is invalid, said state defining said first stage's ability to accept data, said validation circuitry including at least one validation storage device (LVOUT) to store said validation signal;an acceptance signal connecting said stages and conveying an acceptance signal (IN.sub.-- ACCEPT, OUT.sub.-- ACCEPT) indicative of the ability of said second stage to load data stored in said first stage; andenabling circuitry connected to said data storage devices (LDOUT) for generating an enabling signal to enable loading of data and validation signals into the respective storage devices, wherein:said data storage devices include a primary data storage device (LDOUT) and a secondary data storage device (LDIN);said data is loaded into said respective primary data storage devices (LDOUT) and said validation signals are loaded into respective primary validation storage devices (LVOUT) at the same time;data is loaded into each respective primary data storage device (LDOUT) when said acceptance signal assumes an enabling state; andsaid acceptance signal assumes said enabling state only when the acceptance signal associated with the data storage device of said second stage is in said enabling state or said data in said data storage device of said second stage is invalid.