Patent ID: 6864544
Filing Date: 2005-03-08
Classification: H01L

Abstract:
1. A semiconductor device having active regions connected together by interconnect layers comprising: first and second transistors formed spaced apart from each other in a semiconductor substrate, each of the first and second transistors having active regions; an isolation region formed between the first and second transistors in the semiconductor substrate for isolating the first and second transistors from each other; at least one slit formed in the surface of the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, the slit having inner walls and a predetermined width; a conductive layer formed on the inner walls of the slit; and an interconnect layer having first and second portions respectively formed on the paired active regions of the first and second transistors so that each of them is electrically connected with a corresponding one of the paired active regions, and a third portion formed along the slit on the isolation region, the first, second and third portions being made integral with one another, wherein the interconnect layer has a stacked structure including a lower layer of silicon and an upper layer of metal siIicide, and wherein the at least one slit consists of a plurality of slits parallel with one another.