Patent ID: 6455422
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit comprising the steps of:providing a semiconductor substrate having a semiconductor device provided thereon; forming a dielectric layer on the semicondutor substrate; forming a opening in the dielectric layer; deposition a barrier layer to line the opening; depositing a conductor core over the barrier layer to fill the opening and connect to the semiconductor device; planarizing the conductor core and the barrier layer to be co-planar with the dielectric layer; treating the conductor core in a reducing ambient at a temperature below 300Â° C. to reduce oxidants on the conductor core; depositing a capping layer at a temperature below 300Â° C. wherein depositing the capping layer deposits silicon nitride containing hydroxide; and densifying the capping layer at a temperature above 400Â° C.