Patent ID: 6495884
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A vertical MOS transistor comprising:a semiconductor substrate of a first conductivity type; a first epitaxial growth layer of a second conductivity type formed on the semiconductor substrate; a second epitaxial growth layer of the first conductivity type formed on the first epitaxial growth layer; a trench formed through the first and second epitaxial growth layers so as to extend into the semiconductor substrate; a gate oxide film formed on an upper surface of the second epitaxial growth layer and a side wall and bottom wall of the trench; a gate filled in the trench so as to be surrounded by the gate oxide film on the side wall of the trench and having an upper surface coincident with an upper surface of the first epitaxial growth layer; a drain layer of the first conductivity type formed in the upper surface of the second epitaxial growth layer in a region a desired distance away from the gate; a gate electrode connected to the gate; a drain electrode connected to the drain layer; and a source electrode connected to the semiconductor substrate.