Patent ID: 7056802
Filing Date: 2006-06-06
Classification: H01L

Abstract:
1. Method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate and connected via the buried contact having the steps of: (a) providing a trench in the substrate using a hard mask with a corresponding mask opening; (b) providing a capacitor dielectric in the lower and central trench region, the insulation collar in the central and upper trench region and an electrically conductive filling in the lower and central trench region, the top side of the electrically conductive filling being sunk in the upper trench region with respect to the top side of the substrate; (c) providing a silicon nitride liner above the hard mask and in the trench; (d) providing a silicon liner above the silicon nitride liner; (e) carrying out an oblique implantation, as a result of which a shaded region of the silicon liner is made selectively removable with respect to the rest of the silicon liner by means of an etching process; (f) selectively removing the shaded region of the silicon liner by means of the etching process; (g) oxidizing the rest of the silicon liner; (h) carrying out a spacer etching at the oxidized rest of the silicon liner; and (i) depositing and etching back a conductive filling in order to form the buried contact.