Patent ID: 6396127
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A power semiconductor package, comprising:a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a conductive plate coupled to and spanning a substantial part of the first metalized region defining the source connection, the conductive plate including a periphery and at least one chamfered edge at the periphery extending upward and away from the first metalized region; and at least one beam portion being sized and shaped to couple the conductive plate portion to the at least one second terminal such that it is electrically coupled to the source wherein: a plurality of peripheral edges define the periphery of the conductive plate; the at least one beam portion extends from at least one peripheral edge of the metalized plate and is unitarily formed with the at least one second terminal at a distal end; and the at least one chamfered edge being disposed at the least one peripheral edge other than the at least one peripheral edge from which the beam portion extends.