Patent ID: 8735278
Filing Date: 2014-05-27
Classification: H01L

Abstract:
1. A method for forming an interconnect structure, comprising: providing a semiconductor substrate having a conductive region at a surface of the substrate; forming a layer of a low-k dielectric material over the substrate and covering the conductive region; depositing a metal layer of copper or copper alloy overlying the dielectric layer; forming a barrier layer between the low-k dielectric material and the copper or copper alloy metal layer; patterning and etching the copper or copper alloy metal layer to define a first feature having a copper or copper alloy body with first recesses about opposing sidewalls of the body; patterning and etching the copper or copper alloy body to define a second feature having second recesses in an upper portion of the body to define a via, wherein the metal layer is copper and forming the barrier layer comprises forming a first barrier layer overlying the low-k dielectric and subsequently forming a second barrier layer overlying the via.