Patent ID: 9171854
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate including an active region defined by a device isolation pattern; a floating gate on the active region, the floating gate including an upper portion, a lower portion having a width greater than a width of the upper portion, and a step-difference portion between the upper portion and the lower portion; a dielectric pattern on the floating gate; and a control gate on the dielectric pattern, wherein a width of the lower portion of the floating gate becomes progressively wider toward a bottom of the lower portion; wherein the lower portion of the floating gate includes a sidewall making a first inclination angle with an imaginary surface perpendicular to a top surface of the substrate; wherein a width of the step-difference portion of the floating gate becomes progressively wider toward a bottom of the step-difference portion; wherein the step-difference portion of the floating gate includes a sidewall making a second inclination angle with the imaginary surface perpendicular to the top surface of the substrate; wherein a width of the upper portion of the floating gate becomes progressively wider toward a bottom of the upper portion; wherein the upper portion of the floating gate includes a sidewall making a third inclination angle with the imaginary surface perpendicular to the top surface of the substrate; and wherein the second inclination angle is greater than the first or third inclination angles.