Patent ID: 6086628
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the step of parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system, wherein the resource library has different PEs requiring different power supply voltages; and(b) a synthesis phase, following the pre-processing phase, comprising the step of allocating one or more groups of one or more tasks in the task graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the task graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocation for each of the groups and edges in light of the system/task constraints, wherein two or more PEs in the embedded system use two or more different power supply voltages.