Patent ID: 9053765
Filing Date: 2015-06-09
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of memory blocks, including first and second groups of memory blocks, each of the memory blocks including a plurality of memory strings, each memory string including a plurality of memory cells connected in series, a first selection transistor connected to a first end of the plurality of memory cells connected in series, and a second selection transistor connected to a second end of the plurality of memory cells connected in series; a row decoder having transfer transistors through which voltages are supplied to the first and second selection transistors of the memory strings; a block decoder configured to supply a selection signal to the transfer transistors, the selection signal indicating which of the first group of memory blocks and the second group of memory blocks has been selected; a first signal line group connected to the first and second selection transistors of the memory strings that are in first memory blocks of the first and second groups; a second signal line group connected to the first and second selection transistors of the memory strings that are in second memory blocks of the first and second groups; and a switch circuit configured to perform switch control on a first group of control voltages applied to the first signal line group that is connected to the first memory block of the selected group and a second group of control voltages applied to the second signal line group that is connected to the second memory block of the selected group.