Patent ID: 9143117
Filing Date: 2015-09-22
Classification: G11C,H03K

Abstract:
1. A soft error protection device comprising: a soft error resilient latch (SERL) coupled to an electronic element and a clock (CLK) generator, receiving a soft error pulse and a clock (CLK) signal respectively outputted by said electronic element and said CLK generator, and delaying said soft error pulse, and said SERL stores delayed said soft error pulse corresponding to said negative level of said clock signal in a period of said negative level, and said delayed said soft error pulse stored by said SERL is used as a first detection data; a first latch coupled to said electronic element and said clock generator to receive said soft error pulse and said clock signal, and said first latch stores said soft error pulse corresponding to said negative level in said period of said negative level, and said soft error pulse stored by said first latch is used as a second detection data; and a detection device coupled to said SERL, said first latch and said clock generator to receive said clock signal, said first and second detection datum, and comparing said first and second detection datum to send out a detection signal when said clock signal rises from said negative level to a positive level, and said SERL further comprises: