Patent ID: 8701075
Filing Date: 2014-04-15
Classification: G06F

Abstract:
1. A method for recursive hierarchical static timing analysis, comprising: accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form; accessing constraints for the lower-level block; performing static timing analysis on the lower-level block; accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form; accessing constraints for the upper-level block; performing static timing analysis on the upper-level block while incorporating results from the static timing analysis on the lower-level block; and performing, by a computer, recursive static timing analysis on the lower-level block and the upper-level block, the recursive static timing analysis using results from static timing analysis on the upper-level block as feedback for updating the constraints for the lower-level block, and the recursive static timing analysis using results from static timing analysis on the lower-level block as feedback for updating the constraints for the upper-level block.