Patent ID: 8446420
Filing Date: 2013-05-21
Classification: G09G

Abstract:
1. A computer system, comprising: a system processor; a system bus coupled to the system processor; a system memory coupled to the system bus; and a graphics processing system coupled to the system bus, the graphics processing system, comprising: a plurality of memory banks configured to store data; a pipeline processing system coupled to the plurality of memory banks and configured to process graphics data provided from the memory banks and provide processed graphics data to the memory banks; and a memory controller coupled to the plurality of memory banks and configured to coordinate memory access to the plurality of memory banks to provide graphics data retrieved from a first one of the plurality of memory banks to the pipeline processing system for processing, to provide graphics data retrieved from a second one of the plurality of memory banks to the pipeline processing system for processing concurrently with processing graphics data retrieved from a first one of the plurality of memory banks and concurrently with writing processed graphics data from the first one of the plurality of memory banks back to the first one of the plurality of memory banks.