Patent ID: 7312112
Filing Date: 2007-12-25
Classification: G02F,H01L

Abstract:
1. A method for fabricating transistor array substrates on a common glass substrate, the method comprising the steps of: selecting a first area on the common substrate for a first transistor array substrate of a first size; selecting a second area on the common substrate for a second transistor array substrate of a second size, the second size different from the first size; depositing a conductive layer and a photoresist layer on the first and second transistor array substrates; exposing the photoresist layer above transistor channel areas for the first and second transistor array substrates through a transistor channel diffraction slit; etching completely through the photoresist layer in at least one location in each of the first and second transistor array substrates, while removing less than all of the photoresist layer exposed through the diffraction slit, thereby leaving thinner regions in the photoresist layer above the transistor channel areas; removing the thinner regions in the photoresist layer; and etching though the conductive layer above the transistor channel areas to form source electrodes and drain electrodes.