Patent ID: 7304352
Filing Date: 2007-12-04
Classification: G11C,H01L,Y10S

Abstract:
1. A SRAM cell comprising: first and second cross-coupled inverter devices; a bit line connected to the first of said cross-coupled inverter devices through a first access transistor, and a complement bit line connected to the second of said cross-coupled inverter devices through a second access transistor; and, first read port means connected at an internal node of said first of said cross-coupled inverter devices enabling read access to said bitline, and, second read port means connected at an internal node of said second said cross-coupled inverter devices enabling read access to said complement bid me, wherein said first cross-coupled inverter device includes a first pull-up pFET transistor device comprising a gate conductor structure and a drain or source region upon which a first conductive interconnect layer is formed in a semiconductor structure, and said second cross-coupled inverter device includes a second pull-up pFET transistor device comprising a gate conductor structure and a drain or source region upon which a second conductive interconnect layer is formed in said semiconductor structure, wherein a distance between said gate conductor structure of said first pull-up pFET transistor device and said first conductive interconnect layer is substantially equal to the distance between said gate conductor structure of said second pull-up pFET transistor device and said second conductive interconnect layer thereby increasing symmetry between the first and the second cross-coupled inverter devices to improve SRAM cell performance.