Patent ID: 6171893
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method of forming MOS transistors on a semiconductor substrate, said method comprising the steps of:forming isolation regions in said semiconductor substrate, said isolation regions separating said semiconductor substrate into an ESD protective region for at least one transistor and a functional region for a plurality of integrated circuit devices;forming a gate insulator layer on said substrate;forming a polysilicon layer on said gate insulator layer;patterning said polysilicon layer to form gate structures on said ESD protective region and said functional region;doping said semiconductor substrate for forming a first doped region in said semiconductor substrate under a region uncovered by said isolation regions and said gate structures;forming an insulator layer over said semiconductor substrate and said gate structure;removing a portion of said insulator layer and of said gate insulator layer to form spacer structures surrounding said gate structures, and an insulator block aside from said gate structures of said ESD protective region on a lateral side of said gate structures to expose portions of said semiconductor substrate on both sides of said insulator block;doping said semiconductor substrate for forming a second doped region in said semiconductor substrate under a region uncovered by said spacer structures, said gate structures, said isolation regions, and said insulator block, said second doped region having same type dopants with said first doped region;defining an insulator opening within said insulator block;doping said semiconductor substrate for forming a third doped region in said semiconductor substrate under said insulator opening, said third doped region having opposite type dopants with said second doped region and said first doped region;performing a first thermal annealing to said semiconductor substrate to drive-in dopants in said first doped region, said second doped region, and said third doped region;forming a metal layer on said semiconductor substrate;performing a second thermal annealing to said semiconductor substrate to form a metal silicide layer on said gate structures, and on said substrate over said second doped region and said third doped region; andremoving unreacted portions of said metal layer.