Patent ID: 7802217
Filing Date: 2010-09-21
Classification: G06F

Abstract:
1. A method of modifying a design of a block of a chip to reduce a net power consumption of the block, comprising operations of: (1) read in design data of the block; (2) run a static timing engine to calculate path delays and a power estimation tool to calculate power consumption on the design data of the block; (3) select an instance of the block, wherein the selected instance has not been selected before the method starts; (4) determine if the instance is on at least one critical path, (5) determine if the instance meets a criteria of low-AF and a first criteria of high-slack, if the instance does not meet the criteria of low-AF and the first criteria of high-slack, determine if the instance meets a criteria of high-AF and a second criteria of high-slack (6) determine if all instances in the block has been selected, wherein each operation of the method is executed by computer.