Patent ID: 6215702
Filing Date: 2001-04-10
Classification: G11C,H01L

Abstract:
A method of erasing a memory cell that comprises a first region and a second region with a channel therebetween and a gate above said channel, and a charge trapping region that contains a first amount of charge, the method comprising:applying a first voltage across said gate and said first region so that a first portion of said first amount of charge is removed from said charge trapping region;subsequently applying a second voltage across said gate and said first region so that substantially all remaining portions of said first amount of charge is removed from said charge trapping region, wherein the second voltage is different than said first voltage;writing a second amount of charge into said charge trapping region; andapplying a third voltage across said gate and said first region so that that a first portion of said second amount of charge is removed from said charge trapping region, wherein the magnitude of said third voltage is greater than or equal to the magnitude of said second voltage.