Patent ID: 8971115
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a string of memory cell transistors that are connected to each other in series; a first selection transistor that is connected between a first end of the string of the memory cell transistors and a source line, a gate of the first selection transistor being connected to a first line; a second selection transistor that is connected between a second end of the string of the memory cell transistors and a bit line, a gate of the second selection transistor being connected to a second line; a driver configured to generate selected and unselected voltages for the first and second transistors; transfer transistors between the driver and the first and second selection transistors, the transfer transistors being controllable to set at least one of the first and second lines to be in a floating state; a first latch configured to hold information about whether or not a block containing the string of memory cell transistors is a bad block; and a second latch configured to hold information about whether or not one of the first and second lines is to be set in a floating state.