Patent ID: 7301533
Filing Date: 2007-11-27
Classification: G09G,G11C,H03K

Abstract:
1. A buffer circuit comprising: a first transistor coupled between a first power source for supplying a first voltage of a first level and a first node, the first transistor having a gate for receiving a first signal having a first signal level; a second transistor coupled between the first node and a second power source for supplying a second voltage of a second level, the second transistor having a gate for receiving a second signal having a second signal level, which is an inverse of the first signal level; a third transistor having a gate coupled to the first node, the third transistor being coupled between the first power source and a second node; a fourth transistor coupled between the second node and the second power source, the fourth transistor having a gate for receiving the first signal; a fifth transistor having a gate coupled to the second node, the fifth transistor being coupled between the first power source and an output end; and a sixth transistor having a gate coupled to the first node, the sixth transistor being coupled between the output end and the second power source, wherein capacitance is formed between the gate of the sixth transistor and the output end.