Patent ID: 6016534
Filing Date: 2000-01-18
Classification: G11C

Abstract:
A cache memory device comprising:a memory array,an effective content address memory (ECAM);a column decoder for accessing the memory array;a sense amplifier coupled to the column decoder;first logic circuitry for asserting an output signal when all address bits of a read request have been received during an evaluation phase of the cache memory device;circuitry for comparing an address of the read request with entries in the ECAM, wherein a hit results when the address of the read request matches an entry in the ECAM, wherein the hit results in a an ECAM hit signal;second logic circuitry for producing a dummy word line signal in response to the output signal;third logic circuitry for asserting a sense enable signal in response to the ECAM hit signal and the dummy word line signal; andcircuitry for enabling the sense amplifier in response to receipt of the sense enable signal.