Patent ID: 8994704
Filing Date: 2015-03-31
Classification: H03K

Abstract:
1. A latch circuit for receiving and latching data in response to an input scanning signal comprising: a first latch control line receiving a first drive clock; a second latch control line receiving a second drive clock; an input transistor having a gate and first and second electrodes, the first electrode of the input transistor receiving a data signal corresponding to 0 data or 1 data in response to the scanning signal supplied to the gate of the input transistor; a first capacitor retaining a voltage of the data signal received by the input transistor, the first capacitor being directly connected between the second electrode of the input transistor and the first latch control line; a first transistor having a gate and first and second electrodes, the first transistor being a first conductivity type, the first electrode of the first transistor being directly connected to the first latch control line and the gate of the first transistor being directly connected to the second electrode of the input transistor; a second transistor having a gate and first and second electrodes, the second transistor being the first conductivity type, the gate of the second transistor being directly connected to the second electrode of the first transistor and the first electrode of the second transistor being directly connected to the second latch control line; a third transistor having a gate and first and second electrodes, the third transistor being the first conductivity type, the gate of the third transistor being directly connected to the second electrode of the first transistor, the first electrode of the third transistor being connected to the second electrode of the second transistor, and the second electrode of the third transistor being directly connected to an output terminal; a second capacitor directly connected between the second electrode of the first transistor and the second electrode of the second transistor; and a diode directly connected between the second electrode of the first transistor and the first latch control line.