Patent ID: 8446791
Filing Date: 2013-05-21
Classification: G11C

Abstract:
1. A sense amplifier comprising: a top-array multiplexer wherein the top-array multiplexer is configured to input a top-array bit-line signal to a first top-array column select node and to input a top-array bit-line complement signal to a second top-array column select node; a first top-array pre-charge PMOS transistor wherein a source of the first top-array pre-charge PMOS transistor is connected to a voltage supply, a drain of the first top-array pre-charge PMOS transistor is connected to the first top-array column select node, and a gate of the first top-array pre-charge PMOS transistor is configured to receive a top-array pre-charge signal; a second top-array pre-charge PMOS transistor wherein a source of the second top-array pre-charge PMOS transistor is connected to the voltage supply, a drain of the second top-array pre-charge PMOS transistor is connected to the second top-array column select node, and a gate of the second top-array pre-charge PMOS transistor is configured to receive the top-array pre-charge signal; a first top-array write-data NMOS transistor wherein a drain of the first top-array write-data NMOS transistor is connected to the first top-array column select node, a source of the first top-array write-data NMOS transistor is connected to a ground voltage, and a gate of the first top-array write-data NMOS transistor is configured to receive a top-array write-data signal; a second top-array write-data NMOS transistor wherein a drain of the second top-array write-data NMOS transistor is connected to the second top-array column select node, a source of the second top-array write-data NMOS transistor is connected to the ground voltage, and a gate of the second top-array write-data NMOS transistor is configured to receive a top-array write-data complement signal; a first top-array sensing PMOS transistor wherein a source of the first top-array sensing PMOS transistor is connected to the voltage supply, a drain of the first top-array sensing PMOS transistor is connected to a first inverter gating node, and a gate of the first top-array sensing PMOS transistor is connected to the first top-array column select node; a second top-array sensing PMOS transistor wherein a source of the second top-array sensing PMOS transistor is connected to the voltage supply, a drain of the second top-array sensing PMOS transistor is connected to a second inverter gating node, and a gate of the second top-array sensing PMOS transistor is connected to the second top-array column select node; a sense latch comprising: a first inverter comprised of a PMOS transistor and an NMOS transistor, wherein a source of the PMOS transistor is connected to the voltage supply, a drain of the PMOS transistor is connected to a source of the NMOS transistor and the second inverter gating node, and a gate of the PMOS transistor is connected to the first inverter gating node, and wherein a drain of the NMOS transistor is connected a source of a first NMOS transistor of a first NMOS transistor stack, and a gate of the NMOS transistor is connected to the first inverter gating node; a second inverter comprised of a PMOS transistor and an NMOS transistor, wherein a source of the PMOS transistor is connected to the voltage supply, a drain of the PMOS transistor is connected to a source of the NMOS transistor and the first inverter gating node, and a gate of the PMOS transistor is connected to the first inverter gating node, and wherein a drain of the NMOS transistor is connected a drain of a first NMOS transistor of a second NMOS transistor stack, and a gate of the NMOS transistor is connected to the second inverter gating node; the first NMOS stack comprises the first NMOS transistor and a second NMOS transistor, wherein a drain of the first NMOS transistor is connected to a source of the second NMOS transistor, and a gate of the first NMOS transistor is connected to the second top-array column select node, and wherein a drain of the second NMOS transistor is connected to the ground voltage, a gate of the second NMOS transistor is connected to a second bottom-array column select node, the second NMOS stack comprises the first NMOS transistor and a second NMOS transistor, wherein a drain of the first NMOS transistor is connected to a source of the second NMOS transistor, and a gate of the first NMOS transistor is connected to the first top-array column select node, and wherein a drain of the second NMOS transistor is connected to the ground voltage, a gate of the second NMOS transistor is connected to a first bottom-array column select node; a bottom-array multiplexer wherein the bottom-array multiplexer is configured to input a bottom-array bit-line signal to a first bottom-array column select node and to input a bottom-array bit-line complement signal to a second bottom-array column select node; a first bottom-array pre-charge PMOS transistor wherein a source of the first bottom-array pre-charge PMOS transistor is connected to the voltage supply, a drain of the first bottom-array pre-charge PMOS transistor is connected to the first bottom-array column select node, and a gate of the first bottom-array pre-charge PMOS transistor is configured to receive a bottom-array pre-charge signal; a second bottom-array pre-charge PMOS transistor wherein a source of the second bottom-array pre-charge PMOS transistor is connected to the voltage supply, a drain of the second bottom-array pre-charge PMOS transistor is connected to the second bottom-array column select node, and a gate of the second bottom-array pre-charge PMOS transistor is configured to receive the bottom-array pre-charge signal; a first bottom-array write-data NMOS transistor wherein a drain of the first bottom-array write-data NMOS transistor is connected to the first bottom-array column select node, a source of the first bottom-array write-data NMOS transistor is connected to a ground voltage, and a gate of the first bottom-array write-data NMOS transistor is configured to receive a bottom-array write-data signal; a second bottom-array write-data NMOS transistor wherein a drain of the second bottom-array write-data NMOS transistor is connected to the second bottom-array column select node, a source of the second bottom-array write-data NMOS transistor is connected to the ground voltage, and a gate of the second bottom-array write-data NMOS transistor is configured to receive a bottom-array write-data complement signal; a first bottom-array sensing PMOS transistor wherein a source of the first bottom-array sensing PMOS transistor is connected to the voltage supply, a drain of the first bottom-array sensing PMOS transistor is connected to the first inverter gating node, and a gate of the first bottom-array sensing PMOS transistor is connected to the first bottom-array column select node; and a second bottom-array sensing PMOS transistor wherein a source of the second bottom-array sensing PMOS transistor is connected to the voltage supply, a drain of the second top-array sensing PMOS transistor is connected to the second inverter gating node, and a gate of the second bottom-array sensing PMOS transistor is connected to the second bottom-array column select node; wherein the second inverter gating node is configured to output the data value stored in the sense latch.