Patent ID: 6826249
Filing Date: 2004-11-30
Classification: H03K

Abstract:
A synchronous counter for counting through 2N allowed states in response to a sequence of count signals, the synchronous counter comprising:a. a count terminal receiving the sequence of count signals; b. N counter output terminals, including a least-significant-bit (LSB) terminal and a most-significant-bit (MSB) terminal; c. a plurality of sequential storage elements sequentially representing the allowed states in response to the count signals, each storage element having: i. a clock terminal connected to the count terminal; ii. a data input terminal; and iii. a synchronous output terminal connected directly to the data input terminal of a subsequent one of the storage elements; and d. encoding logic having: i. a plurality of encoding-logic input terminals connected to respective ones of the synchronous output terminals; ii. a first encoding-logic output terminal connected to the LSB terminal; and iii. a second encoding-logic output terminal connected to the MSB terminal.