Patent ID: 7965801
Filing Date: 2011-06-21
Classification: H04L

Abstract:
1. A data recovery circuit, comprising: an accumulator coupled to receive oversampled data; the accumulator configured to determine and to accumulate sub-scores from the oversampled data using a sliding window; a bit width of the sliding window being associated with data width of the oversampled data input to the accumulator; the sliding window being sequentially and incrementally shifted to bitwise resolve phases from the oversampled data; the phases in number being associated with an oversampling factor; the accumulator further configured to sum the sub-scores for each of the phases to provide scores for each of the phases; a detector-tracker circuit coupled to receive the scores; the detector-tracker circuit configured to select a phase of the phases responsive at least to the scores and output the phase selected; the detector-tracker circuit further configured to track the phase selected; a delay circuit coupled to receive the oversampled data and configured to output a delayed version of the oversampled data; a sampler coupled to receive the delayed version of the oversampled data and the phase selected; and the sampler configured to sample the oversampled data responsive to the phase selected to provided sampled data for output as a subset of the oversampled data.