Patent ID: 6197673
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method of fabricating passivation of a gate electrode, comprising:providing a substrate covered by a gate oxide layer;forming a conductive layer on the gate oxide layer and a mask layer on the conductive layer;forming a photoresist layer with a pattern on the conductive layer;transferring the pattern from the photoresist layer to the mask layer, wherein the photoresist layer has a sufficient thickness to transfer the pattern onto the mask layer without causing distortion;removing the photoresist layer;transferring the pattern from the mask layer to the conductive layer, and truncating a sharp corner of the mask layer to result in a cap layer with an arc shape corner on the conductive layer;forming a conformal liner oxide layer along a surface of the cap layer and on a sidewall of the conductive layer; andforming a spacer on the liner oxide layer over the sidewall of the conductive layer and extending over a top surface of the gate to cover the liner oxide layer between the spacer and the conductive layer.