Patent ID: 6789222
Filing Date: 2004-09-07
Classification: G01R,G06F

Abstract:
A single-pass method for generating all test patterns for all detectable single stuck-at faults in a combinational circuit, comprising:a step for defining data structures for a single stuck-at fault, a fault-propagation function, and a path-enabling function; a step for defining function combining rules; a step for applying the rules to the data structures, thereby creating new data structures; the rules being applied in a circuit-level-by-circuit-level ascending order starting from the primary input level; a step for attempting to activate and propagate all single stuck-at faults during a single pass through the circuit; a step for determining from the attempt which primary input assignments succeed in activating and propagating a fault to a primary output; a fault reaching a primary output defining a detectable fault; primary input assignments permitting a fault to reach a primary output defining all test patterns for the fault, such that all tests for all detectable single stuck-at faults are generated during the single pass.