Patent ID: 8032815
Filing Date: 2011-10-04
Classification: G06F,H03M

Abstract:
1. A semiconductor memory device configured to execute a standby operation for saving power during standby, the device comprising: a memory cell array including a plurality of memory cells arranged at intersections of bit lines and word lines and operative to store cell data; a redundant memory cell array including a plurality of redundant memory cells arranged at intersections of said bit lines and redundant word lines and operative to store redundant data for error correction of cell data stored in said memory cell array; a sense amplifier operative to sense and amplify the voltage on said bit line to read said cell data or said redundant data from said memory cell array or said redundant memory cell array; a cyclic redundant encoder/decoder operative to encode said cell data through sequential processing to generate said redundant data or operative to decode said cell data and said redundant data through sequential processing to execute error correction of said cell data; a row decoder operative to selectively activate said word line or said redundant word line in accordance with a row address signal; and a column decoder operative to selectively activate a data line to read said cell data or said redundant data in accordance with a column address signal.