Patent ID: 6298369
Filing Date: 2001-10-02
Classification: G06F

Abstract:
A high speed multiplier for calculating the product of a variable N-bit multiplicand and an M-bit constant comprising:(a) a memory for storing a first multiplication result equal to a product of a first N-bit multiplicand and the M-bit constant, said memory further capable of retrieving the first multiplication result using a cache lookup bit (CLB) portion of a second N-bit multiplicand;(b) a lookup table circuit containing a plurality of sub-products, wherein a first sub-product is equal to a product of the M-bit constant and a first difference value, the first difference value associated with a difference between a first table lookup bit (TLB) portion of the first N-bit multiplicand and a second TLB portion of the second N-bit multiplicand; and(c) a summation circuit capable of adding the first sub-product to the first multiplication result to thereby produce a second multiplication result equal to a product of the M-bit constant and the second N-bit multiplicand.