Patent ID: 8848152
Filing Date: 2014-09-30
Classification: G02F,G09G

Abstract:
1. A display substrate comprising: a plurality of spaced apart gate lines each extending in a first direction and formed in a display area of the display substrate; a gate driving circuit formed in a peripheral area surrounding the display area, the gate driving circuit including a plurality of circuit stages connected to the gate lines and a dummy stage connected to a last circuit stage of the circuit stages; a plurality of gate connecting lines connecting the circuit stages to the gate lines and formed in the peripheral area, each of the gate connecting lines including a portion extending in a second direction crossing the first direction so that the gate connecting lines are substantially entirely shifted to the second direction with respect to the gate lines; and a sub-gate line formed adjacent to each of the gate lines in the display area, wherein the circuit stages comprise: first sub-stages formed in the peripheral area and connected to first to m-th gate lines (m is a natural number) of the gate lines; and second sub-stages formed in the peripheral area, connected to (m+1)-th to n-th gate lines (n is a natural number more than m) and connected to first to (n−m)-th sub-gate lines, wherein the gate driving circuit further comprises third sub-stages connected to ((n−m)+1)-th to n-th sub-gate lines.