Patent ID: 7865911
Filing Date: 2011-01-04
Classification: G06F

Abstract:
1. One or more processor-accessible storage media comprising processor-executable instructions that, when executed by a processor of a device, perform acts comprising: parallelizing, according to a hybrid programming model combining aspects of a thread-oriented programming model with aspects of an event-oriented programming model, multiple first synchronous calls within a first barrier time period in a first phase of development of a software program to produce a graphical user interface description of the software program, wherein the multiple first synchronous calls are executed asynchronously after being parallelized; parallelizing, according to the hybrid programming model and in response to executing and affirmatively acknowledging each of the multiple first synchronous calls, multiple second synchronous calls within a second barrier time period in a second phase of development of code of the software program to produce skeleton code of the software program, wherein the multiple second synchronous calls are executed asynchronously after being parallelized; parallelizing, according to the hybrid programming model and in response to executing and affirmatively acknowledging each of the multiple second synchronous calls, multiple third synchronous calls within a third barrier time period in a third phase of development of code of the software program to produce final source code of the software program, wherein the multiple third synchronous calls are executed asynchronously after being parallelized; and compiling the final source code of the software program to produce final executable code of the software program.