Patent ID: 6583400
Filing Date: 2003-06-24
Classification: H03F

Abstract:
A multichannel receiver circuit comprising:first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity; the first to n-th sections receiving first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals; each of the first to n-th sections including an output level fixer circuit that produces an output signal; the output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level; and the output signal of the output level fixer circuit having substantially a same waveform as that of a corresponding one of the first to n-th input signals when a corresponding one of the first to n-th input signals has a level equal to or greater than the specific reference level.