Patent ID: 8683279
Filing Date: 2014-03-25
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead; B. a test access port controller having inputs coupled to the test clock lead and the test mode select lead and having control outputs; C. an instruction register having an input coupled to the test data in lead, an output coupled to the test data out lead, a data register control output, a built in self test output, and a control input connected to a control output of the test access port controller; D. a data register having an input coupled to the test data in lead, an output coupled to the test data out lead, a control input coupled to a control output of the test access port controller, a control input coupled to a control output of the instruction register, and a built in self test input; and E. built in self test circuitry having an input coupled to the built in self test output of the instruction register, and an output coupled to the built in self test input of the data register.