Patent ID: 7570513
Filing Date: 2009-08-04
Classification: G11C

Abstract:
1. A non-volatile memory, comprising: memory cells organized as an array of NAND chains, each NAND chain having a series of memory cell connected in series and accessible at one end via a sourse select transistor and at another end via a drain select transistor; and a switch coupled between said each NAND chain via the drain select transistor to a bit line, said switch responsive to a voltage condition on the bit line to connect said each NAND chain to the bit line when the bit line is substantially at zero voltage and to disconnect said each NAND chain from the bit line when the bit line is substantially at a supply voltage; wherein said switch comprises: an n-channel transistor having a control gate, said n-channel transistor connected in series between said each NAND chain and the bit line; and a p-channel transistor having a control gate, said p-channel transistor connected in series between a supply voltage and the control gate of the n-channel, said control gate of the p-channel being connected to the bit line.