Patent ID: 6151199
Filing Date: 2000-11-21
Classification: H01L,H03K

Abstract:
A semiconductor integrated circuit device comprising:an N-channel MOS transistor having a gate to which a signal voltage is applied and having a source connected to a reference potential point;an output terminal connected to a drain of the N-channel MOS transistor;a P-channel MOS transistor having a source connected to the drain of the N-channel MOS transistor and having a drain connected to the reference potential point; anda resistor formed between the source and a gate of the P-channel MOS transistor,wherein, when a positive electrostatic charge is applied to the output terminal while the gate of the N-channel MOS transistor is receiving no input voltage and thus the semiconductor integrated circuit is not in operation, the P-channel MOS transistor is turned on so that the electrostatic charge is bypassed to the reference potential point.