Patent ID: 9099313
Filing Date: 2015-08-04
Classification: H01L,H05K

Abstract:
1. An embedded package, comprising: a package substrate having a core having a first circuit wire pattern and a second circuit wire pattern formed on outer surfaces of the core, wherein the first circuit wire pattern formed on a first surface of the core and the second circuit wire pattern formed on a second surface that opposes the first surface of the core; a semiconductor chip formed on the first surface of the core of the package substrate; first and second bonding pads formed on the semiconductor chip; a dielectric layer having a first metal pattern formed on one surface of the dielectric layer and, the dielectric layer configured to cover the semiconductor chip, wherein the dielectric layer comprise open regions through which parts of the first and the second circuit wire patterns are exposed; a first connection wire pattern directly connects between the first bonding pad and the first circuit wire pattern of the core, wherein the first connection wire pattern contacts with the first bonding pad and vertically extends along the outer surface of the semiconductor chip to contact with the first circuit wire pattern; and a second connection wire pattern directly connects between the second bonding pad and the first metal pattern of the dielectric layer, wherein the second connection wire pattern vertically penetrates the dielectric layer.