Patent ID: 6237108
Filing Date: 2001-05-22
Classification: G06F

Abstract:
A multiprocessor system having a redundant shared memory configuration, comprising:processor modules each having a central processing unit processing data and a first system bus controller connecting each of said processor modules to a shared system bus; andshared system memory modules each having a shared system memory unit commonly used by said processor modules and a second system bus controller connecting each of said shared system memory modules to said shared system bus,wherein a first processor module of said processor modules writes data directly in first and second shared system memory modules of said shared system memory modules, to ensure that said data respectively written in the first and second shared system memory modules are equivalent to each other,wherein a second processor module among said processor modules monitors a status of the first processor module, and discriminates whether a write operation for the second shared system memory module is finished via a normal termination or an abnormal termination where the first processor module stops operation,wherein the second processor module reads out an address corresponding to a first data in said data which failed to be normally written in the second shared system memory module when said write operation for the second shared system memory module finishes in the abnormal termination at a time when the first processor module stops operating, andwherein the second processor module copies said data starting from the address corresponding to the first data in the first shared system memory module to the second shared system memory module.