Patent ID: 7768057
Filing Date: 2010-08-03
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: memory cell units each including a plurality of memory cells connected in series and a first select transistor connected to one edge portion of the series-connected plurality of memory cells; a memory cell array including the memory cell units arranged to form an array; control gate lines each including control gates of memory cells connected continuously in a row direction of the memory cell array; and a select gate line including gates of the first select transistors connected continuously in the row direction of the memory cell array; wherein a first voltage is supplied to a control gate of a first memory cell included in a selected memory cell unit, a second voltage is supplied to a control gate of a second memory cell included in the selected memory cell unit, a third voltage is supplied to a gate of the first select transistor in the selected memory cell unit, thereby at least one of an ordinary data read operation and a verify read operation is performed, all of the first voltage, the second voltage and the third voltage are higher than 0V, the first voltage is lower than the second voltage, and the second voltage is higher than the third voltage.