Patent ID: 8369458
Filing Date: 2013-02-05
Classification: H04B

Abstract:
1. A circuit comprising: a controller; and an analog to digital converter (ADC) coupled to the controller, wherein the ADC includes at least a bias block circuit and a mode control unit, wherein in response to a high data rate, the ADC is configured instantly to a high speed mode by the bias block circuit adjusting, via the mode control unit, a bias current and voltage using a high rate clock signal, and the ADC is configured instantly to a high resolution mode by turning on all functions of the ADC, wherein in response to any of early data detection and a low data rate, the ADC is configured instantly to a low speed mode by the bias block circuit adjusting, via the mode control unit, the bias current and voltage using a low rate clock signal, and the ADC is configured instantly to a low resolution mode by turning off some functions of the ADC.