Patent ID: 6806120
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A method of creating a stack of integrated circuits selectively connected to provide increased memory density in an application, the method comprising the steps of:providing a carrier frame configured to have a plurality of members emergent into a window within the carrier frame; applying a first portion of a solder-containing compound to the first side of the plurality of members; after applying said first portion of solder-containing compound, placing a first packaged integrated circuit in contact with the plurality of members; processing the first integrated circuit and the carrier frame with a heat source to create a first set of solder connections between the plurality of members and the first packaged integrated circuit; after said processing step, applying a second portion of a solder-containing compound to the second side of the plurality of members of the carrier frame; after applying the second portion of solder-containing compound, placing a second packaged integrated circuit in contact with the plurality of members; and processing the second integrated circuit and the carrier frame with a heat source to create a second set of solder connections between the plurality of members and the second integrated circuit.