Patent ID: 9159735
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A memory device comprising: a first pair of split gate flash memory cells residing within a first active region, the first active region having an upper surface in a semiconductor body, wherein the first pair of split gate flash memory cells share a first shared erase gate having a dish shaped surface that extends below the upper surface of the first active region; a first shared common source region disposed below the dish shaped surface of the first erase gate in the first active region; a second pair of split gate flash memory cells residing within a second active region, the second active region having an upper surface in the semiconductor body, wherein the second pair of split gate flash memory cells share a second shared erase gate having a dish shaped surface that extends below the upper surface of the second active region; a second shared common source region disposed below the dish shaped surface of the second erase gate in the second active region; an isolation region disposed within a trench in the semiconductor body separating the first and second active regions; and a buried doped conductive path disposed beneath the isolation region extending between the first and second shared common source regions, wherein the buried doped conductive path has an undulating shape, following an inner profile of the trench.