Patent ID: 6465283
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A structure using latch-up implantation to improve latch-up immunity in CMOS fabrication process, the structure comprising:a substrate, having a first conductive type; a well, formed in the substrate and having a second conductive type; a first MOS transistor formed in the second conductive type well, having a first source and a first drain regions with a first conductive type and a gate; a second MOS transistor formed in the first conductive type substrate, having a second source and a second drain regions with a second conductive type and a gate; a first lightly doped region surrounding a bottom and edges of the first source region in the well, the edges of the first source region excluding the edge at a near side of the first drain region, and the first lightly doped region having a first conductive type; a second lightly doped region surrounding a bottom and edges of the second source region in the substrate, the edges of the second source region excluding the edge at a near side of the second drain region, and the second lightly doped region having a second conductive type; a first heavily doped region with a second conductive type in the second conductive type well, the first heavily doped region being near and with a distance to the first lightly doped region; and a second heavily doped region with a first conductive type in the first conductive type substrate, the second heavily doped region being near and with a distance to the second lightly doped region.