Patent ID: 7895509
Filing Date: 2011-02-22
Classification: H03M

Abstract:
1. A decoder, comprising: syndrome logic coupled to receive a plurality of words of a data vector and configured to compute a plurality of partial syndromes for the plurality of words; storage devices coupled to the syndrome logic to store the plurality of partial syndromes computed responsive to a clock signal; a feedback filter coupled to receive the plurality of partial syndromes stored and to provide the plurality of partial syndromes stored to the syndrome logic; and a controller coupled to the feedback filter and to the syndrome logic, the controller having a counter, the counter configured to count responsive to the clock signal to provide a count indicative of a word number of the plurality of words, the controller configured to provide an initial word control signal and a parity word control signal, the controller configured to count beginning at an initial word number and ending with a last word number for the data vector, the controller configured to increment a count and to skip a reserved word number; the feedback filter coupled to receive the initial word control signal and configured to preclude providing the partial syndromes stored to the syndrome logic responsive to the initial word control signal; and the syndrome logic coupled to receive the parity word control signal for computation of the plurality of partial syndromes and coupled to receive the plurality of partial syndromes stored for inclusion with a partial syndrome for another word of the data vector.