Patent ID: 8159051
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first semiconductor layer of a first conductivity type and having a main surface that has a first plane orientation; a second semiconductor layer of the first conductivity type and having a main surface that has a second plane orientation exhibiting lesser channeling effect compared to the first plane orientation, the second semiconductor layer being directly provided on the first semiconductor layer; a third semiconductor layer having a main surface that has the first plane orientation, and being formed on the first semiconductor layer and on a side face of the second semiconductor layer; a gate electrode formed on the second semiconductor layer via a gate insulating film; first impurity diffusion regions of a second conductivity type serving as source drain extensions, and being formed in the second semiconductor layer so that the gate electrode is located on a region sandwiched in a gate length direction between the first impurity diffusion regions, the first impurity diffusion regions extending to an interface between the first and second semiconductor layers; and second impurity diffusion regions of a second conductivity type, and being formed in the first semiconductor layer and the third semiconductor layer, and being formed so as to extend from the third semiconductor layers to the first semiconductor layer, respectively, so that both the first impurity diffusion regions are sandwiched in the gate length direction between the second impurity diffusion regions.