Patent ID: 7098156
Filing Date: 2006-08-29
Classification: G05B,H01L,Y02P,Y10S

Abstract:
1. A fabrication method of a semiconductor integrated circuit device, comprising forming integrated circuits over one or plural wafers by a semiconductor production line including: (a) a plurality of bay areas within a clean room, each bay area having a plurality of semiconductor integrated circuit manufacturing apparatuses; (b) a plurality of rail guided vehicles provided in each bay area, each rail guided vehicle conveying the one or plural wafers accommodated in a sealed conveying container to one of the semiconductor integrated circuit manufacturing apparatuses by travelling on a lower track laid on a floor; (c) rail guided vehicle traveling area partition provided in each bay area, surrounding the lower track for the rail guided vehicles to separate from human working areas; (d) a bay-to-bay conveyance mechanism for conveying the one or plural wafers accommodated in the sealed conveying container between the bays; and (e) a plurality of bay stations respectively provided corresponding to the plural rail guided vehicles within each bay so as to act as intermediary between the rail guided vehicles in each bay and the bay-to-bay conveyance mechanism.