Patent ID: 7064601
Filing Date: 2006-06-20
Classification: G05F

Abstract:
1. A reference voltage generating circuit comprising an active resistance part having a plurality of MOS transistors connected between an external voltage and a ground voltage, each of the plurality of MOS transistors having a gate electrode which receives an enable voltage at a potential higher than a voltage potential between drain and source electrodes of each of the plurality of MOS transistors to operate in a linear current-voltage region, a current mirror circuit comprising first and second PMOS transistors, a source of each of the first and second PMOS transistors receiving the external voltage, wherein the current mirror circuit is electrically connected to the active resistance part, and a voltage supply circuit comprising a third PMOS transistor and a plurality of NMOS transistors, wherein the voltage supply circuit supplies the enable voltage to the plurality of MOS transistors, wherein the enable voltage is determined by the NMOS transistors, wherein a gate of the third PMOS transistor is connected to a drain of the first PMOS transistor, a source of the third PMOS transistor receives the external voltage and is connected to a back gate of the third PMOS transistor, and a drain of the third PMOS transistor is connected to a drain and a gate of a first NMOS transistor of the plurality of NMOS transistors.