Patent ID: 8981750
Filing Date: 2015-03-17
Classification: G05F,G11C,H02M

Abstract:
1. A method of operating a voltage regulator circuit to provide an output voltage level on an output node, where the voltage regulator circuit includes a pass transistor connected between a supply level and the output node of the voltage regulator circuit and has a gate connected to an output node of an op-amp having first and second inputs, where the first input of the op-amp is connected to receive a reference voltage, the method comprising: operating the voltage regulator in a standby mode, wherein the op-amp's output node is connected to receive the supply level; and subsequently operating the voltage regulator circuit in an active mode, wherein the op-amp's output node is not connected to receive the supply level, the output node of the voltage regulator circuit is connected to ground through a resistive voltage divider, and the second input of the op-amp is connected to a node of the resistive voltage divider, wherein, in transitioning from the standby mode to the active mode, the connection of the second input of the op-amp to the node of the resistive voltage divider is delayed relative to disconnecting of the op-amp's output node from the supply level and the connecting of the voltage regulator circuit's output node to ground through the resistive voltage divider.