Patent ID: 6578176
Filing Date: 2003-06-10
Classification: G06F,G06N

Abstract:
In a computer implemented synthesis system, a method of optimizing power dissipation for a design of an integrated circuit device by applying a genetic algorithm, comprising the computer implemented steps of:a) accessing a circuit netlist, the circuit netlist representing an integrated circuit design to be realized in physical form; b) building an objective function from functions of circuit parameters that describes the power dissipation for the integrated circuit design with respect to stimulation inputs for the integrated circuit design; c) applying a first primary input vector to a set of primary inputs, and applying a pseudo-primary input vector to a set of pseudo-primary inputs, at a beginning of a first clock cycle; d) applying a second primary input vector to the set of primary inputs at a beginning of a second clock cycle; e) applying a third primary input vector to the set of primary inputs at a beginning of a third clock cycle; f) measuring power consumption in said third clock cycle; g) maximizing the function by repeating steps b) through f); and h) optimizing power dissipation for the circuit netlist by optimizing at least one portion of the circuit netlist identified by the set of stimulation inputs.