Patent ID: 6567067
Filing Date: 2003-05-20
Classification: G09G,H03K

Abstract:
A level shifter comprising:a first MOS transistor of a first conductive type having a source connected to a first power source, and a gate to which a first input signal is inputted; a second MOS transistor of a same conductive type as said first conductive type, having a source connected to said first power source, and a gate to which a second input signal is inputted, wherein said second input signal is an inverted signal of said first input signal; a third MOS transistor of a second conductive type different from said first conductive type, having a drain connected to a drain of said first MOS transistor, and a gate to which said first input signal is inputted; a fourth MOS transistor of a same conductive type as said second conductive type, having a drain connected to a drain of said second MOS transistor, and a gate to which said second input signal is inputted; a fifth MOS transistor of a same conductive type as said second conductive type, having a drain connected to a source of said third MOS transistor, and a gate connected to a drain of said second MOS transistor; a sixth MOS transistor of a same conductive type as said second conductive type, having a drain connected to a source of said fourth MOS transistor, and a gate connected to a drain of said first MOS transistor; a first voltage regulating circuit connected between a source of said fifth MOS transistor and a second power source; and a second voltage regulating circuit connected between a source of said sixth MOS transistor and said second power source, wherein said first and second input signals of a first voltage amplitude is converted to a signal of a second voltage amplitude to thereby output a signal from at least one of said drains of said first MOS transistor or said second MOS transistor.