Patent ID: 8014477
Filing Date: 2011-09-06
Classification: H01L,H03M

Abstract:
1. A receiver comprising: a tuner circuit providing an analog signal received on a selected channel; a converter circuit configured to: for a plurality of different sample clock frequencies. a master clock generator that generates the master clock signal and provides the master clock signal to the converter circuit, and where the converter circuit further comprises: where the sample clock generator further comprises channel converter logic responsive to the selected channel to select the control integer value by which the master clock signal is divided to generate the sample clock signal; where the tuner circuit comprises: where the sample clock generator comprises a frequency counter disposed to generate a frequency value from a signal in the tuner circuit, where the frequency value corresponds to a frequency of the selected channel, and where the channel converter logic is responsive to the frequency value in order to select the control integer value; and where the frequency counter generates the frequency value from an input signal to the local oscillator circuit that is used by the local oscillator circuit to generate the mixing signal.