Patent ID: 7675106
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A non-volatile memory point comprising: a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, wherein: at least the main part of the active portions has a P-type doping and the inactive portions comprise at least one N-type doped area forming a portion of a PN junction; first and second wells of a first doping type are placed in an upper portion of the substrate of a second doping type; the floating gate comprises a ring-shaped active portion placed above the first well, a non-active portion placed above an insulating area placed in the upper portion of the substrate between the first and second wells, and an active end portion placed above the second well; and drain and source areas of the second doping type are placed at the surface of the first well respectively inside and outside, in top view, of the active ring-shaped portion.