Patent ID: 6344754
Filing Date: 2002-02-05
Classification: G09G

Abstract:
A semiconductor device package, said package being arranged to facilitate testing and comprising:a substrate; a plurality of semiconductor chips with each one of said plurality of semiconductor chips being rectangular and having a plurality of input terminals 1-n (where n is an integer) along one side and a plurality of output terminals 1-N (where N is an integer) along a side opposite to said one side; said plurality of semiconductor chips being mounted on said substrate with adjacent ones of said plurality of semiconductor chips being rotated 180Â° from each other so that: (1) input terminal 1 of a first one of said plurality of semiconductor chips faces opposite to input terminal n of an adjacent one of said plurality of semiconductor chips and input terminal 2 of said first one of said plurality of semiconductor chips faces opposite to input terminal nâˆ’1 of said adjacent one of said plurality of semiconductor chips with such pairings continuing for all of said input terminals of said first one and said adjacent one of said plurality of semiconductor chips, and (2) output terminal 1 of said first one of said plurality of semiconductor chips faces opposite to output terminal N of another adjacent one of said plurality of semiconductor chips and output terminal 2 of said first one of said plurality of semiconductor chips faces opposite to output terminal Nâˆ’1 of said another adjacent one of said plurality of semiconductor chips with such pairings continuing for all of said output terminals of said first one and said another adjacent one of said plurality of semiconductor chips each of said paired input terminals of said first one and said adjacent one of said plurality of semiconductor chips are interconnected by respective input leads; and each of said paired output terminals of said first one and said another adjacent one of said plurality of semiconductor chips are interconnected by respective output leads.