Patent ID: 6483152
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate of a first conductivity type, wherein isolation regions and a device region between said isolation regions are defined; field oxides formed over said respective isolation regions of said substrate; an active element formed in said device region of said substrate; a resistor having a predetermined width, formed over one of said field oxides; a dummy gate electrode formed over at the predetermined portion of said resistor, said dummy gate electrode having a width smaller than that of said resistor; an analog capacitor formed over another field oxide, said analog capacitor including lower and upper plates having predetermined widths and a dielectric film between said lower and upper plates; and a metal silicide layer formed over said active element, over said resistor only where said dummy gate electrode is not formed, over said dummy gate electrode, and over said lower and upper plates of said analog capacitor, respectively, wherein said dummy gate electrode is not formed over a part of the resistor that is contacted with a metal interconnection layer.