Patent ID: 8241984
Filing Date: 2012-08-14
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising: providing a first insulating film and a first electrode layer in a stacked form over both an area where a memory cell is formed and an area where a peripheral circuit is formed, which are provided on a semiconductor substrate, and forming, at a plurality of positions, element separation areas which penetrate through the first electrode layer and the first insulating film and reach inside of the semiconductor substrate; retracting an upper surface of the first electrode layer in the memory cell forming area to a position lower than the upper surface of the first electrode layer in the peripheral circuit forming area, and retracting an upper surface of each of the element separation areas in the memory cell forming area to a position further lower than the upper surface of the retracted first electrode layer; providing a second insulating film on the each element separation area and the first electrode layer, and forming openings, which penetrate through the second insulating film and reach inside of the first electrode layer, in each of the memory cell forming area and the peripheral circuit forming area in parallel; and providing a second electrode layer on the second insulating film, and connecting the second electrode layer to the first electrode layer by burying a part of the second electrode layer in each of the openings.