Patent ID: 8572543
Filing Date: 2013-10-29
Classification: G06F

Abstract:
1. A method of designing an integrated circuit, comprising the steps of: (A) generating a design layout of said integrated circuit in a computer, said design layout comprising (i) a plurality of common cells each configured to perform a logical operation and (ii) a logic gate having a logic input fixed to a logic level; (B) replacing at least one of said common cells proximate said logic gate with a special cell configured to (i) perform said logical operation and (ii) generate a signal at said logic level; (C) removing a connection that fixes said logic input of said logic gate to said logic level; (D) routing said signal from said special cell to said logic input of said logic gate, wherein (i) said logic gate resides inside a first of a plurality of boundaries in said design layout, (ii) said design layout further comprises a scan chain having a scan cell within said first boundary, (iii) an additional logic gate resides in a second of said boundaries and (iv) said second boundary adjoins said first boundary; and (E) marking said second boundary as full in response to said second boundary lacking available space to place another scan cell.