Patent ID: 6079005
Filing Date: 2000-06-20
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache configured to receive a first virtual index, wherein said instruction cache is configured to store a plurality of physical tags and is further configured to select at least one of said plurality of physical tags in response to said first virtual index; anda branch prediction unit coupled to said instruction cache, wherein said branch prediction unit includes a current page register coupled to receive a virtual page number and a corresponding physical page number from a translation lookaside buffer (TLB) included in said branch prediction unit, and wherein said branch prediction unit is configured to form a branch target address for a branch instruction from said first virtual index and said virtual page number from said current page register, and wherein said branch prediction unit further includes a comparator coupled to said current page register and to receive said one of said plurality of physical tags, and wherein said comparator is configured to compare said one of said plurality of physical tags to said corresponding physical page number stored in said current page register, and wherein said branch prediction unit is configured to verify said branch target address responsive to a signal from said comparator.