Patent ID: 7456467
Filing Date: 2008-11-25
Classification: G11C,H01L

Abstract:
1. A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organized in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a cell selection transistor, the process providing the following steps: defining on a semiconductor substrate one or more active areas for said byte selection transistor and for a floating gate transistor and cell selection transistor of at least one of said memory cells, the active areas having portions of an insulating layer adjacent thereto; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer and a second polysilicon layer; removing, through a photolithographic technique, portions of said multilayer structure to form at least two bands, a portion of the first band being effective to define the gate regions of said byte selection transistor and of said cell selection transistor, the second band being effective to define the gate region of said floating gate transistor, a portion of said first band further extending on a portion of said insulating layer adjacent to said byte selection transistor; forming an opening in said portion of said first band to expose said first polysilicon layer; and forming a conductive layer in said opening to put said first polysilicon layer in electrical contact with said second polysilicon layer.