Patent ID: 8125552
Filing Date: 2012-02-28
Classification: H04N

Abstract:
1. A solid-state imaging device having an imaging area with K imaging blocks arranged therein, each imaging block including N pixel columns arranged adjacently, the device comprising: an image data arithmetic section for specifying a partial readout area in accordance with an input digital video signal; a row selecting circuit for selecting a pixel row corresponding to the partial readout area; a column selecting circuit for selecting a pixel column corresponding to the partial readout area; a timing generating circuit for generating a control signal for selection by the row and column selecting circuits based on an output from the image data arithmetic section; and N processing circuits connected to the respective N pixel columns via switches that are turned on through the selection by the column selecting circuit, wherein the n-th processing circuit can be connected to the n-th pixel columns in the respective imaging blocks via the switches, and the N processing circuits are adapted to generate the digital video signal from a signal for each pixel column selected by the row and column selecting circuits, wherein N≧2, and K≧2, the solid-state imaging device further comprising a plurality of holding circuits connected to the respective pixel columns, wherein the switches are adapted to connect charges accumulated in the holding circuits for the respective pixel columns to the processing circuits corresponding to the respective pixel columns synchronously with the control signal input from the timing generating circuit to the column selecting circuit.