Patent ID: 6153448
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device comprising the steps of:forming a plurality of chip regions including a plurality of electrode pads on a semiconductor wafer;forming a barrier metal layer on said semiconductor wafer and performing etching to selectively leave the barrier metal on the electrode pad in each of said chip region and in a predetermined region surrounding the same;forming line grooves to a depth which is halfway the thickness of the substrate between the chip regions of said semiconductor wafer;forming an insulation layer serving also as a sealing layer having openings for via holes in correspondence to the arrangement of said barrier metal;forming wiring patterns including via hole wiring portions connected to said barrier metal at the bottom of said openings for via holes and including land portions connected thereto and arranged regularly in the form of a matrix in positions on the tape insulation layer offset from said via hole portions;mounting external electrodes in the form of balls on the land portions of said wiring patterns; andcutting the wafer with a dicing saw along the center lines of said line grooves to divide it into semiconductor devices in a chip-size package structure including a ball grid array electrode.