Patent ID: 7494876
Filing Date: 2009-02-24
Classification: H01L

Abstract:
1. A method of fabricating an MIS device comprising: forming a trench in a semiconductor chip comprising an N-epi layer atop an N+ substrate, the trench having a sidewall and a bottom, wherein the trench is formed in the N-epi layer and does not extend to the N+ substrate; growing a first oxide layer on the sidewall and bottom of the trench; depositing undoped polysilicon in the trench; etching a portion of the undoped polysilicon to expose a portion of the first oxide layer while leaving a plug of undoped polysilicon at the bottom of the trench; etching the exposed portion of the first oxide layer to expose a portion of a sidewall of the trench; growing a gate oxide layer on the exposed portion of the sidewall; growing a second oxide layer on the undoped polysilicon plug; depositing a polysilicon layer in the trench that overflows onto a top surface of the N-epi layer, the polysilicon layer for forming a gate and is adjacent to the gate oxide and the second oxide layer; and etching back the polysilicon layer until its top surface is approximately level with the top surface of the N-epi layer.