Patent ID: 6319783
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method of fabricating a metal oxide semiconductor field effect transistor, (MOSFET), device, on a semiconductor substrate, featuring a source/drain extension region formed in an area of said semiconductor substrate not covered by a polysilicon gate structure or by a selectively grown epitaxial shape, comprising the sequential steps of:forming an insulator shape on a first portion of said semiconductor substrate;forming selectively grown epitaxial, (SEG), silicon shapes, on second portions of said semiconductor substrate, not covered by said first insulator shape, with said SEG silicon shapes comprised with dopants;removing said insulator shape, exposing a top surface of said first portion of said semiconductor substrate;forming first insulator spacers directly on sides of said SEG silicon shapes;growing a gate insulator layer on the exposed surface of said first portion, of said semiconductor substrate, and forming heavily doped source/drain regions, in said second portion of said semiconductor substrate, resulting from out diffusion of a portion of said dopants, in said SEG silicon shapes, during said gate insulator layer formation;forming said polysilicon gate structure on said gate insulator layer, with said polysilicon gate structure located between said first insulator spacers, and with said polysilicon gate structure at a same height as said SEG silicon shapes;removing said first insulator spacers exposing third portion of said semiconductor substrate, with said third portion of said semiconductor substrate not covered by said SEG silicon shapes or by said polysilicon gate structure;forming source/drain extension regions in said third portion of said semiconductor substrate;forming second insulator spacers between said SEG silicon shapes, and said polysilicon gate structure, with said second insulator spacers overlying said source/drain extension regions;depositing an interlevel dielectric, (ILD), layer;forming contact holes in said ILD layer exposing a portion of a top surface of said SEG silicon shapes, and a top portion of said polysilicon gate structure; andforming metal structures in said contact holes.