Patent ID: 6583657
Filing Date: 2003-06-24
Classification: H03K

Abstract:
A duty cycle correction circuit comprising:a delay-control circuit configured to receive a first clock signal and generate a delay-control voltage, wherein the first clock signal consists of a train of clock pulses, each of which clock pulses has a rising clock edge and a falling clock edge, the delay-control circuit including: a first voltage divider configured to receive the first clock signal and generate a first output voltage representing a dc average of the first clock signal; a second voltage divider configured to generate a second output voltage; a differential amplifier having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the first voltage divider to receive the first output voltage, wherein the second input terminal is coupled to the second voltage divider to receive the second output voltage, and wherein the output terminal outputs a third output voltage; and a stability circuit coupled to the output terminal to receive the third output voltage and generate the delay-control voltage by stabilizing the third output voltage; and a clock-inverter circuit configured to receive a second clock signal and the delay-control voltage and to generate a third clock signal, wherein the clock-inverter circuit is biased with first and second bias voltages, the clock-inverter circuit including: a first field effect transistor (FET) having a source, a gate, and a drain, wherein the gate of the first FET is coupled to the delay-control voltage, and wherein the source of the first FET is coupled to the first bias voltage; a second FET having a source, a gate, and a drain, wherein the source of the second FET is coupled to the first bias voltage, wherein the gate of the second FET receives the second clock signal, and wherein the drain of the second FET outputs the third clock signal; a third FET having a source, a gate, and a drain, wherein the source of the third FET is coupled to the drain of the first FET, wherein the gate of the third FET is coupled to the gate of the second FET, and wherein the drain of the third FET is coupled to the drain of the second FET; and a fourth FET having a source, a gate, and a drain, wherein the source of the fourth FET is coupled to the second bias voltage, wherein the gate of the fourth FET is coupled to the gates of the second and third FETs, and wherein the drain of the fourth FET is coupled to the drains of the second and third FETs.