Patent ID: 7453752
Filing Date: 2008-11-18
Classification: G11C

Abstract:
1. A memory device having plural DRAM sub-array groups, each DRAM sub-array group comprising plural DRAM sub-arrays, and each DRAM sub-array comprising plural array rows, comprising: an address decoder for decoding an address of a memory access request and indicating which of the plural DRAM sub-arrays are referenced by the memory access request; and refresh circuitry to perform a refresh contemporaneously with the memory access request of at least one array row of at least one of the plural DRAM sub-arrays not referenced by the memory access request, comprising a refresh counter and a missed refresh counter for each DRAM sub-array, wherein the refresh is performed by refreshing at least one DRAM sub-array in each DRAM sub-array group during a refresh cycle and refreshing plural, but not all DRAM sub-arrays in at least one DRAM sub-array group during the refresh cycle.