Patent ID: 6622274
Filing Date: 2003-09-16
Classification: G01R,G11C

Abstract:
A BIST frontend state machine comprising:a shift register responsive to values inputted by a user for generating output register signals corresponding to which one of a plurality of sets of tests are to be executed; clock means for generating two-phase non-overlapping clock signals; backend state machine for generating controls signals indicative of whether an individual test is still being executed, has been completed, or has failed; state controller responsive to said clock signals, said control signals, and said output register signals for generating output state signals based upon a fixed number of states utilizing logic transitions of a limited number so as to sequence through said one of said plurality of sets of tests until each individual test has been completed or failed; a logic module responsive to said output register signals and said output state signals for generating output test signals required for each individual test of said one of the plurality of sets of tests being sequenced through; the output register signals from said shift register being formed of a plurality of bits, said each bit of said plurality of bits corresponding to an individual test in said one of the plurality of sets of test; each bit of said plulrality of bits being checked sequentially by said state controller to determine whether the individual test is to be executed or not; the individual test being executed when the bit being checked is equal to a logic â€œ1â€  and the individual test being not executed when the bit being checked is equal to a logic â€œ0â€ ; the individual test being executed continuously by said state controller until one of the first and second control signals goes to a logic â€œ1â€ , the first control signal corresponding to a â€œpassedâ€  test signal, the second control signal corresponding to a â€œfailedâ€  test signal; and the next bit of each bit of said plurality of bits being checked by said state controller on the next clock signal from said clock means when the â€œpassedâ€  test signal goes to a logic â€œ1â€  to determine whether a next individual test is to be executed or not.