Patent ID: 9098628
Filing Date: 2015-08-04
Classification: G06F,H04N

Abstract:
1. An apparatus comprising: a memory module comprising a plurality of memory blocks; an address decoder module that decodes one or more address lines of the plurality of memory blocks, wherein an address output of the address decoder module corresponds to each memory block of the plurality of memory blocks; a BWE module comprising a block write enable (“BWE”) signal corresponding to each memory block of the plurality of memory blocks, wherein each BWE signal has a block write enable state and a block write disable state; a MUX module that passes, to a write enable input of each memory block of the plurality of memory blocks, one of a BWE sequence module that changes each BWE signal in sequence from the block write enable state to the block write disable state wherein a first state of the sequence comprises each BWE signal in the block write enable state and a final state of the sequence comprises each BWE signal in the block write disable state and each intermediate state of the sequence between the first state and the final state transitions a single BWE signal from the block write enable state to the block write disable state; and a data update module that, in response to the BWEC signal being in the state trace mode, writes, during a write operation, data to each memory block that has a BWE signal in the block write enable state, and does not write the data to each memory block that has a BWE signal in the block write disable state.