Patent ID: 6301310
Filing Date: 2001-10-09
Classification: H04L

Abstract:
A circuit for modulating the frequency of a carrier signal for data transmission, comprising:a minimum shift key (MSK) generator for generating a series of in-phase (I) signals and an associated series of quadrature (Q) signals corresponding to the data signals to be transmitted;a first shift register for receiving binary input from the I signals generated with the MSK generator, said binary input being indicative of the sign orientation of the generated I signals from the MSK generator, said first shift register comprising a single bit shift register for receiving the most significant bit of digital data of said I signals;a second shift register for receiving binary input from the Q signals generated with the MSK generator, said binary input being indicative of the sign orientation of the generated Q signals from the MSK generator, said second shift register comprising a single bit shift register for receiving the most significant bit of digital data of said Q signals;a first finite impulse response (FIR) filter for summing a series of delayed binary input received from the I signals at said first shift register to generate filtered I signals;a second FIR filter for summing a series of delayed binary input received from the Q signals at said second shift register to generate filtered Q signals;a local oscillator (LO) for generating a carrier signal; andan I/Q modulator for modulating the phase shift of the LO signal according to the filtered I signals and the filtered Q signals from said first FIR filter and said second FIR filter respectively.