Patent ID: 6171947
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A submicron semiconductor technology process for minimizing thermal stress-induced voids in electrical interconnect line structures, said process comprising the steps of:a) providing at least one semiconductor substrate having a plurality of transistor gate structures, each transistor gate structure of said plurality of transistor gate structures having a width less than or equal to 0.25 .mu.m, and also having at least one pattern of electrical interconnect line structure formed thereon with a line spacing less than 0.35 .mu.m;b) preventing said electrical interconnect line structure from experiencing yield stress, due to restricted plastic deformation, and hydrogen embrittlement, and thereby minimizing thermal stress-induced voids in said electrical interconnect line structure by annealing said at least one semiconductor substrate for plastically deforming said electrical interconnect line structure, and then setting PECVD deposition parameters comprising a deposition temperature in a range of 350.degree. C. to 450.degree. C. and further setting a chamber pressure in a range of 2.5 Torr to 6.0 Torr, a plurality of gas flow rates for producing a plasma, and a plasma-energizing power setting in a range of 285 W to 330 W for producing a stoichiometric silicon oxynitride layer having a refractive index in a target range of 1.63 to 1.71, and then depositing a stoichiometric silicon oxynitride layer between and on top of said electrical interconnect line structure using PECVD techniques,wherein said depositing step includes forming said plasma comprising nitrogen, nitrous oxide, and silane gases being dispensed at said set flow rates and being energized at said set plasma-energizing power setting by a radio frequency power source,wherein said nitrogen gas flow rate is set at approximately 2000 standard cubic centimeters per minute,wherein said silane gas flow rate is set less than 75 standard cubic centimeters per minute,wherein said gas flow rates facilitate producing said stoichiometric silicon oxynitride layer having said refractive index in said range of 1.63 to 1.71;c) testing said stoichiometric silicon oxynitride layer and determining that its refractive index is in said refractive index target range of 1.63 to 1.71;d) repeating said steps a) through c) if said target range is not met; ande) depositing a layer of silicon dioxide on top of said stoichiometric silicon oxynitride layer, only if said target range is met.