Patent ID: 6320423
Filing Date: 2001-11-20
Classification: H03K

Abstract:
A MOS logic circuit, comprising:a pass-transistor logic circuit for performing a predetermined logic operation to provide an output, said pass-transistor logic circuit including a first DTMOS transistor having a threshold voltage; andan amplifying circuit for enhancing a driving capability of said output without employing a pull-up PMOS transistor, said amplifying circuit including a second DTMOS transistor having an absolute value of a threshold voltage higher than that of said first DTMOS transistor when said second DTMOS transistor is in an off state and said first DTMOS transistor is in an on state to prevent leakage of a stationary penetrating current through said amplifying circuit, thereby lowering power consumption of the MOS logic circuit,wherein each of said DTMOS transistors have a gate connected to an associated well in which a channel thereof is formed, said gate and associated well short-circuited to prevent an increase in threshold voltage due to a back gate effect, thereby reducing the number of pass-transistor and amplifier elements required in the MOS logic circuit.