Patent ID: 8692317
Filing Date: 2014-04-08
Classification: H01L

Abstract:
1. A semiconductor storage device comprising a plurality of static random access memory cells, wherein each of the cells comprises a first access transistor, a second access transistor, a first driving transistor, a second driving transistor, a first load transistor and a second load transistor; each of the transistors comprises a column portion including a semiconductor projecting from a base portion surface, an underside conductive area provided in the base portion and serving as one of a source and a drain, an upper-side conductive area provided in an upper part of the column portion and serving as the other of the source and the drain, a gate electrode provided on a side surface of the column portion, and a gate insulating film interposed between the gate electrode and the column portion side surface; in each of the cells, the base portion of the first access transistor and the base portion of one of the first driving transistor and the first load transistor are integrally coupled together to form a first coupled base portion; the gate electrode of the first driving transistor and the gate electrode of the first load transistor are integrally coupled together to form a first coupled gate electrode comprising a first gate extension extending in the coupling direction; the base portion of the second access transistor and the base portion of one of the second driving transistor and the second load transistor are integrally coupled together to form a second coupled base portion; the gate electrode of the second driving transistor and the gate electrode of the second load transistor are integrally coupled together to form a second coupled gate electrode comprising a second gate extension extending in the coupling direction; a first local interconnect is provided coupling the second gate extension, the base portion of the other of the first driving transistor and the first load transistor, and the first coupled base portion together; and a second local interconnect is provided coupling the first gate extension, the base portion of the other of the second driving transistor and the second load transistor, and the second coupled base portion together.