Patent ID: 9190150
Filing Date: 2015-11-17
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a memory cell array including a plurality of stacked memory cells; a plurality of first wirings electrically connected to the plurality of stacked memory cells; a plurality of first contacts electrically connected to part of the plurality of first wirings and arranged in a first direction parallel to the semiconductor substrate; a plurality of second contacts electrically connected to part of the plurality of first wirings and arranged in the first direction alternately with the plurality of first contacts; a plurality of third contacts electrically connected to the plurality of first contacts and displaced from the plurality of first contacts in the first direction; a plurality of fourth contacts electrically connected to the plurality of second contacts and displaced from the plurality of second contacts in a second direction perpendicular to the first direction; a third wiring connected between a first contact and a third contact and shaped like a rectangle with a longitudinal direction directed in the second direction; and a fourth wiring connected between a second contact and a fourth contact and shaped like a rectangle with a longitudinal direction directed in the first direction.