Patent ID: 6194258
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A method of forming an image sensor cell, and a CMOS logic circuit region, on a semiconductor substrate, comprising the steps of:forming a P well region, in a top portion of said semiconductor substrate;forming a first gate structure, on a gate insulator layer, on a first region of said semiconductor substrate, to be used for said image sensor cell, and simultaneously forming a second gate structure, on said gate insulator layer, on a second region of said semiconductor substrate, to be used for said CMOS logic circuit region;simultaneously forming: a first source/drain region in an area of said semiconductor substrate not covered by said first gate structure, in said first region of said semiconductor substrate; a second source/drain region in an area of said semiconductor substrate not covered by said second gate structure, in said second region of said semiconductor substrate; and a photodiode element, comprised of an N type region, in a portion of said P well region, located in said first region of said semiconductor substrate; depositing a thin silicon oxide layer; removing said thin silicon oxide layer from said CMOS logic circuit region; applying a thick organic layer; etching portions of said thick organic layer to expose said first gate structure and said second gate structure; removing an unetched portion of the thick organic layer; andforming a metal silicide layer on a top surface of said second gate structure, and on said second source/drain region, in said second region of said semiconductor substrate, while simultaneously forming a metal silicide layer on a top surface of said first gate structure, in said first region of said semiconductor substrate.