Patent ID: 6070180
Filing Date: 2000-05-30
Classification: G06F

Abstract:
A digital arithmetic integrated circuit, comprising:an arithmetic data storing memory for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string comprising m bits and the second arithmetic data string comprising m times n bits such that the second arithmetic data string is n-times longer than the first arithmetic data string;first and second arithmetic operand storing registers for respectively storing the first and second arithmetic data strings output by said arithmetic data storing memory and for respectively outputting a first and second operand;an arithmetic logic unit for executing an arithmetic operation on the basis of the first and second operands output by said first and second arithmetic operand storing registers and for outputting arithmetic results of the arithmetic operation, in one instruction cycle; andan arithmetic result storing register for storing the arithmetic results output by said arithmetic logic unit,wherein the arithmetic data storing memory comprises a first unit for outputting the first arithmetic data string and a second unit for outputting the second arithmetic data string, wherein the second unit includes m data circuits each having a memory cell array constructed by k bit lines and a selector for selecting in of the k-bit lines to output data through the selected bit lines.