Patent ID: 6073151
Filing Date: 2000-06-06
Classification: G06T,H03H

Abstract:
A bit-serial linear interpolator with sliced output comprising:a bit-serial controller for receiving a clock signal and producing multiple control signals;delay circuitry for receiving an input sequence and the clock signal, the delay circuitry producing delayed versions of the input sequence;adder circuitry coupled to receive the input sequence and the delayed versions of the input sequence for producing addition terms in response to the clock signal and a first portion of the multiple control signals;a multiplexer coupled to receive multiple input terms including at least one of the delayed versions of the input sequence and the addition terms for sequentially producing at its output, in response to a second portion of the multiple control signals, a multiplexed signal that has a sign bit of each of the multiple input terms;logic circuitry coupled to receive a third portion of the multiple control signals for producing a latch control signal; anda latch coupled to receive the multiplexed signal and producing a final output signal in response to the clock signal and the latch control signal.