Patent ID: 6765419
Filing Date: 2004-07-20
Classification: H03L

Abstract:
A delay lock loop circuit receiving a reference clock signal, said delay lock loop (DLL) circuit for aligning in time the reference clock signal and an internal feedback clock signal, said DLL circuit comprising:a forward delay circuit receiving said reference clock signal, said forward delay circuit including a forward delay line having a plurality of electrically interconnected delay blocks, each of said delay blocks including predetermined number of electrically interconnected delay units; and disabling means deactivating at least one of said delay blocks when said at least one delay block is not needed in order to align in time said reference clock signal and said internal feedback clock signal, wherein said disabling means issues a respective enable signal to each of said delay blocks, each of said delay blocks being effectively connected to and disconnected from the reference clock signal dependent at least in part upon said enable signals; and wherein each of said delay blocks include a respective block output, each of said delay blocks receiving a respective block select signal, said block outputs being selected dependent at least in part upon a corresponding one of said block select signals, said block select signals being received by said disabling means, said disabling means generating each respective enable signal dependent at least in part upon a corresponding one of said block select signals.