Patent ID: 6870785
Filing Date: 2005-03-22
Classification: G11C

Abstract:
1. A nonvolatile ferroelectric memory device having a multi-bit function, comprising: a plurality of cell array blocks for generating a plurality of different sensing critical voltages in a reference timing strobe interval, and for comparing the plurality of sensing critical voltages with a plurality of cell data sensing voltages applied from a main bitline, wherein each of the plurality of cell array blocks comprises a nonvolatile ferroelectric memory; a data register array unit for storing the plurality of bit data applied from the plurality of cell array blocks in different timing intervals and for converting a plurality of inputted bit data or the plurality of bit data into analog reference level signals; and a common data bus unit, connected in common to the plurality of cell array blocks, for controlling data exchange between the plurality of cell array blocks and the data register array unit.