Patent ID: 7739443
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A memory controller for controlling a nonvolatile semiconductor memory which writes data in a second data write-in unit and erases data in an erase unit including a plurality of second data write-in units, comprising: a host interface configured to be connectable to a host apparatus and to receive a first data write-in unit of reception data from the host apparatus; a memory interface configured to be connected to the nonvolatile semiconductor memory in which the second data write-in unit of data larger in size than the first data write-in unit of reception data is written; and a central processing unit configured to write the reception data via the memory interface as write-in data of the first data write-in unit in a temporary write-in block which is provided in the nonvolatile semiconductor memory, read out write-in data corresponding to a plurality of area data from the temporary write-in block when a total amount of reception data has reached an amount of the second data write-in unit, and write the plurality of area data including the, write-in data into a target block which is a different block from the temporary write-in block and provided in the nonvolatile semiconductor memory.