Patent ID: 6349362
Filing Date: 2002-02-19
Classification: G06F

Abstract:
A storage cache comprising:one or more memory arrays that are of sufficient size to define an n-way associative cache and having an (nâˆ’p)-way associative data cache portion of said n-way associative cache wherein (nâˆ’2)&gE;p&gE;1, such that p associative columns not contained in said data cache portion of the storage cache are not used as a data cache, and the p associative columns are organized as an independent m-way associative logical translation look-aside buffer (TLB) for at least some data in the data cache portion where m>p. a cache directory that indexes data values contained in the data cache portion; and a cache controller that processes references to the p associative columns not contained in said data cache portion as a TLB reference rather than a data reference to produce at least a portion of a real address output from at least a portion of a virtual address input, and thereby operates the p associative columns not contained in the data cache portion in a TLB mode rather than a data mode.