Patent ID: 6407595
Filing Date: 2002-06-18
Classification: G06F,Y02D

Abstract:
A digital clock throttling means for regulating a frequency of a clock signal of a circuit, the digital clock throttling means comprising:an accumulator transmitting an internal output signal responsive to a throttling value for generating a first output signal, the first output signal being divided into a throttling signal with a most significant bit of the first output signal and a feedback signal with rest bits of the first output signal except for the most significant bit, the feedback signal being sent to the accumulator back for accumulating to the throttling value as the first output signal; and a gating circuit coupling with the accumulator responsive to the throttling signal and the clock signal for gating out some clock cycles of the clock signal wherein the gating circuit comprises at least an OR gate, thereby providing a gated clock signal in an adjusted frequency.