Patent ID: 7027544
Filing Date: 2006-04-11
Classification: H03L,H04L

Abstract:
1. A data clock recovery circuit comprising a controllable quadrature clock oscillator operating at half the data rate of data input to said circuit, and a phase detector logic having detector inputs coupled to the data input and having a detector output coupled to a frequency control input of the quadrature clock oscillator, characterized in that the data clock recovery circuit further comprises a parallel arrangement of sampling devices each having a clock input which is coupled to the controllable quadrature clock oscillator, a data input for the data input to said circuit, said clock inputs being connected directly together and said data inputs being connected directly together, and a data output coupled to the phase detector, and further characterized in that the data outputs of the respective sampling devices are coupled to controllable switches each having a switch control input coupled to the quadrature clock oscillator, two data inputs coupled to a respective pair of said data outputs, and switch outputs for providing either serial output data or control signal output.