Patent ID: 8649217
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: a memory cell section including a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first wiring, and a memory layer in which a non-volatile memory cell is arranged so as to be sandwiched by the first and second wirings at an intersecting position of the first and second wirings, the memory layer being stacked in plurals while sharing the first or second wiring with the memory layer adjacent to a thickness direction; a first contact section arranged in the extending direction of the first wiring of the memory cell section; a second contact section arranged in the extending direction of the second wiring of the memory cell section; a first drawing section configured to connect the memory cell section and the first contact section with the first wiring; and a second drawing section configured to connect the memory cell section and the second contact section with the second wiring, wherein a dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.