Patent ID: 6066525
Filing Date: 2000-05-23
Classification: H01L

Abstract:
A method of forming a DRAM cell, the method comprising:(a) on a semiconductor substrate, forming an electrical isolation region about an active region on which the DRAM cell is formed;(b) forming a layer of high dielectric constant material on the active region of the semiconductor substrate;(c) removing the high dielectric constant material from an access transistor region of the active region while leaving the high dielectric constant material at a capacitor region of the active region;(d) forming a gate dielectric layer over the access transistor region and over the high dielectric constant material layer on the capacitor region; and(e) from a single layer of conductive material, forming a gate electrode on the gate dielectric at the access transistor region and forming a capacitor plate on the gate dielectric at the capacitor region.