Patent ID: 6377489
Filing Date: 2002-04-23
Classification: G11C

Abstract:
A method of erasing a first cell in a flash memory device, the first cell of the flash memory device having associated therewith a source, a drain, a floating gate, a control gate and a select gate, the method comprising the steps of:applying a high negative voltage to the control gate; applying a high positive voltage to the select gate; applying a power supply voltage to the source; and floating the drain, all substantially simultaneously, wherein the flash memory device comprises a second cell having associated therewith a second control gate, a second select gate, a second source and a second drain, the second cell being adjacent to said first cell, and the method further comprises the steps of: applying a high negative voltage to the second control gate; applying a voltage of 0 V to the second select gate; applying a power supply voltage to the second source; and floating the second drain, all substantially simultaneously.