Patent ID: 6111773
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A memory circuit, comprising:a semiconductor structure;a first amplifier stage disposed in a first region of the semiconductor structure;a second amplifier stage disposed in a second region of the semiconductor structure;a memory array disposed in the semiconductor structure, the memory array having a plurality of memory cells arranged in rows and columns, each cell operable to store a data bit;a first set of digit lines coupled to the memory array, extending from the memory array and into the first region, and coupled to the first amplifier stage; a second set of digit lines coupled to the memory allay, extending from the memory array through the first region and into the second region, coupled to the second amplifier stage, and electrically isolated from the first amplifier stage;an addressing circuit disposed in the semiconductor structure and coupled to the memory array, the addressing circuit operable to receive row and column addresses and to activate a corresponding memory cell in the memory array; anda data path circuit coupling the first and second amplifier stages to a data bus terminal.