Patent ID: 6173408
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A processor comprising:an operation unit having the functions of performing operation processing on data and supplying a status signal representing the status of the operation processing;a microcontroller having the function of generating an operation initiating signal;an operation controller for asserting a request signal when the operation controller receives the operation initiating signal generated from the microcontroller, for determining whether or not the status signal supplied from the operation unit satisfies a predetermined end condition, and for negating the request signal if the status signal satisfies the end condition; anda clock controller for supplying a clock signal to the operation unit such that the operation unit is allowed to perform the operation processing if the request signal has been asserted, and for stopping the supply of the clock signal to the operation unit if the request signal has been negated, wherein the clock controller comprises;a request register for latching the request signal in synchronism with a system clock signal supplied thereto;means for transmitting the system clock signal to the operation unit if the output of the request register has been asserted, and for stopping the transmission of the system clock signal to the operation unit if the output of the request register has been negated; andmeans for always transmitting the system clock signal to the operation controller.