Patent ID: 6613606
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A method of creating a circuit assembly, comprising the steps of:providing a semiconductor substrate, having been provided with at least one active surface region wherein at least one semiconductor circuit has been created, with at least one first electrical point of contact having been provided in said at least one active surface region of said semiconductor substrate; providing a first interface created overlying said surface of said semiconductor substrate comprising a first layer of dielectric having openings whereby at least one of said openings is filled with a conductive material that contacts at least one of said at least one electrical contacts provided in said surface of said semiconductor substrate, thereby creating second electrical contacts in the surface of said first interface; providing at least one semiconductor die having been provided with active circuits, further having been provided with at least one first contact ball or contact point forming at least one third electrical contact; providing electrical contact between at least one of said third electrical contacts of said at least one semiconductor die and at least one of said second electrical contacts; providing an underfill for said at least one semiconductor die, curing said underfill; depositing a second layer of dielectric over the surface of said at least one semiconductor die, planarizing said deposited second layer of dielectric; creating at least one via opening penetrating said second layer of dielectric and said first layer of dielectric, exposing at least one of said first electrical contacts provided in said at least one active region in said surface of said semiconductor substrate; depositing and patterning a first layer of conductive material over the surface of said second layer of dielectric, filling said at least one via opening created in said second layer and first layer of dielectric with a conductive material, further creating a first interconnect network over the surface of said second layer of dielectric, thereby contacting at least one of said at least one via openings created in said second layer of dielectric, thereby establishing electrical contact between said first interconnect network and at least one of said first electrical contacts in said at least one active region in the surface of said semiconductor substrate; providing second contact balls with at least one of said second contact balls contacting said first interconnect network, thereby including at least one of said at least one vias; and separating said at least one semiconductor device from its surrounding region by die sawing said semiconductor substrate without affecting any interconnect metal that is connected to said at least one semiconductor device, creating an intermediate semiconductor package.