Patent ID: 7579877
Filing Date: 2009-08-25
Classification: H03K

Abstract:
1. A comparator, comprising: first and second input terminals; first and second output terminals; a first inverter having an input directly connected to the first input terminal; a second inverter having an input directly connected to the second input terminal; a third inverter having an output directly connected to an output of the first inverter and the first output terminal; a fourth inverter having an output directly connected to an output of the second inverter and the second output terminal; and a bias circuit, directly connected between the respective outputs of the third and fourth inverters, to provide first and second bias voltages, an input of the third inverter directly connected to the bias circuit to receive the first bias voltage, an input of the fourth inverter directly connected to the bias circuit to receive the second bias voltage; wherein the bias circuit includes a plurality of transistors, coupled between the respective outputs of the third and fourth inverters, to provide the first and second bias voltages; and the plurality of transistors include a first pair of transistors, a second pair of transistors, and a third pair of transistors, the first, second, and third pairs of transistors coupled in series, a node between the first and second pairs of transistors for providing the first bias voltage, a node between the second and third pairs of transistors for providing the second bias voltage.