Patent ID: 6367039
Filing Date: 2002-04-02
Classification: G01R

Abstract:
An integrated circuit, comprising:a voltage regulator operable to produce an output voltage, the voltage regulator being further operable to receive a plurality of regulator trimming signals, each having first and second logic states, the magnitude of the output voltage being determined by the combination of logic states of the regulator trimming signals; a programmable trimming circuit coupled with the voltage regulator and operable to produce a first set of trimming signals, the programmable trimming circuit having a plurality of programmable elements, each having first and second programmed states, the logic state of each of the first set of trimming signals being determined by the programmed state of a corresponding one of the programmable elements; a trim test circuit coupled with the voltage regulator and operable to receive a plurality of test signals and to produce a second set of trimming signals in response thereto; and wherein the combination of logic states of the regulator trimming signals corresponds with the combination of logic states of one of the first and second sets of trimming signals.