Patent ID: 7355248
Filing Date: 2008-04-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first semiconductor layer that is formed over a first insulating layer; a second insulating layer that is formed over the first semiconductor layer; a second semiconductor layer that is formed over the second insulating layer; a first gate electrode that is formed over the second semiconductor layer; first conductive source and drain layers that are formed in the second semiconductor layer and are arranged at sides of the gate electrode; a first wiring layer that electrically connects the first gate electrode to the first semiconductor layer; a third insulating layer that is formed over the first semiconductor layer; a third semiconductor layer that is formed over the third insulating layer; a second gate electrode that is formed over the third semiconductor layer; second conductive source and drain layers that are formed in the third semiconductor layer and are arranged at sides of the second gate electrode; and a second wiring layer that electrically connects the first conductive drain layer to the second conductive drain layer, wherein the first wiring layer electrically connects the first semiconductor layer to both the first gate electrode and the second gate electrode.