Patent ID: 6356123
Filing Date: 2002-03-12
Classification: H03K

Abstract:
A non-integer frequency divider for dividing an original clock into a target clock by a non-integer number of m/n, where m and n are integer numbers and m>n, the non-integer frequency divider comprising:a phase-oscillating device for converting the original clock into a predetermined number of phase-shifted versions of the original clock with a phase difference of 360Â°/2n; a plurality of edge-triggered clock signal generators, each edge-triggered clock signal generator receiving the original clock or a corresponding phase-shifted version for generating responsively a plurality of edge-triggered signals, each of the edge-triggered signals having a period of 2m times of that of the original clock and respectively having a rising edge or a falling edge synchronized with a rising edge or a falling edge of the signal input to the edge-triggered clock signal generator; and a synthesis circuit, receiving the edge-triggered signals from the plurality of edge-trimmed clock signal generator, for synthesizing the edge-triggered signals into the target clock.