Patent ID: 6610574
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A process for the manufacture of a MOSgated power device; said process comprising the steps of diffusing a channel region of one conductivity type into a surface of a substrate of the other conductivity type to a first depth; diffusing a source region of the other conductivity type to a second depth which is less than said first depth; etching a plurality of spaced and generally U-shaped trenches into the surface of said silicon substrate to a third depth which is greater than said first depth; forming a gate oxide over the interior surfaces of said trenches and forming an insulation oxide over the surface areas between said trenches; and then depositing a continuous layer of conductive polysilicon into each of said trenches and over said insulated surface between said trenches; and forming a source contact to at least said source region at a location laterally removed from the space between said trenches.