Patent ID: 6601204
Filing Date: 2003-07-29
Classification: G11C

Abstract:
A pattern generator for a memory tester which writes pattern data in a memory under test, then reads out thereof the written pattern data, and compares the read-out data with expectation data, said pattern generator comprising:address generating means for generating a sequence of addresses to be applied to said memory under test; pattern data generating means for generating parallel pattern data in which pieces of parallel data of plural bytes to be written, on a byte-wise basis, in memory cells of said memory under test specified by said sequence of addresses are arranged in time sequence in the order of burst addresses that are generated in said memory under test; mask data generating means for generating parallel mask data which masks, on a byte-wise basis, plural-byte parallel data of said parallel pattern data generated by said pattern data generating means; burst address generating means for generating, based on said address generated by said address generating means, burst addresses equivalent to burst addresses which are generated in said memory under test; parallel-serial converting means for converting said parallel mask data from said mask data generating means to plural pieces of serial mask data in accordance with said burst addresses generated by said burst address generating means; and expectation data generating means for deciding, based on the logic of each bit of said plural pieces of serial mask data, whether each byte of said plural-byte parallel data is write-enabled, and for generating, based on the decision result, parallel expectation data of plural bytes from said plural-byte parallel data and initialization data of said memory under test.