Patent ID: 6620668
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of fabricating a MOS transistor comprising:forming gate patterns on a semiconductor substrate; forming a diffusion source layer on the entire surface of the semiconductor substrate; implanting the same type or different type of impurities into the diffusion source layer according to a plurality of implantation angles relative to the semiconductor substrate so that the impurity concentration of portions of the diffusion source layer on upper surfaces of the gate patterns and the semiconductor substrate is higher than the impurity concentration of portions of the diffusion source layer on sidewalls of the gate patterns due to a shadow effect; and diffusing impurities contained in the diffusion source layer into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions underneath the sidewalls of the gate patterns and highly doped source/drain regions by a self-alignment method.