Patent ID: 6795946
Filing Date: 2004-09-21
Classification: H04L

Abstract:
An apparatus for performing a cyclic redundancy code check on a receivedbinary digital signal comprising a variable multiplicity (M) of data bytes, comprising means for temporarily storing in succession segments each comprising an integral plurality (N) of bytes and for loading each successive segment into a cyclic redundancy checker which produces a remainder after performing polynomial division of the received binary digital signal, means operable, when the number of bytes of the received binary digital signal in the last segment is less than said integral plurality (N), to pad that last segment only at its end with constant data prior to loading into the cyclic redundancy checker and means for determining whether said remainder matches any of a plurality of predetermined remainders each one of which corresponds to the operation of the cyclic redundancy checker on a valid digital signal padded with a different number from zero to (Nâˆ’1) bytes of the constant data.