Patent ID: 6717886
Filing Date: 2004-04-06
Classification: G11C

Abstract:
A control circuit for a data path of an S-DRAM which is clocked by a clock signal, the control circuit comprising:a programmable mode register for storing a latency value; a latency generator for temporally delaying, with a switchable latency, a data path control signal, generated by an internal sequence controller; a latency decoder which is functionally connected to and switches the latency generator in a manner dependent on the latency value stored in the mode register; and at least one signal delay element, which is operable to be switched in by the latency decoder to cause a signal delay of a specific delay time in the data path control signal so that the latency decoder switches in the at least one signal delay element when the stored latency value is a high latency value such that there is a risk of signal propagation times being longer than a cycle time of the clock signal if the signal delay were not present, and wherein the latency decoder otherwise switches out the at least one signal delay element.