Patent ID: 8796777
Filing Date: 2014-08-05
Classification: G11C,H01L

Abstract:
1. An apparatus comprising: a plurality of bit cell memory transistors, wherein each bit cell memory transistor of the plurality of bit cell memory transistors is configured to store a single data bit, a first gate write and hold logic control circuit configured to control the first gate of each bit cell memory transistor; a second gate write and hold logic control circuit configured to control the second gate of each bit cell memory transistor; and a third gate write and hold logic control circuit configured to control the third gate of each bit cell memory transistor, wherein, when a particular bit cell memory transistor operates in the hold phase, the first gate write and hold logic control circuit, the second gate write and hold logic control circuit, and the third gate write and hold logic control circuit are configured to apply low values of the first gate voltage, the second gate voltage, and the third gate voltage to the particular bit cell memory transistor.