Patent ID: 8554967
Filing Date: 2013-10-08
Classification: G06F

Abstract:
1. A method of controlling transaction flow in an event-based coherency interconnect operatively coupled between devices to support operations amongst the devices relative to a coherency domain of addressable memory locations, the method comprising: associating class of transaction (CoT) labels with constituent transactions of the supported operations, wherein the CoT labels associated with respective constituent transactions of a particular supported operation differ, but are in accordance with an acyclic precedence order of the constituent transactions; receiving transaction requests from devices linked to the coherency interconnect, wherein, for at least address-type ones of the received transaction requests, the received transaction requests each specify a CoT label; the coherency interconnect supplying CoT labeled grant indications in correspondence with, and responsive to, a subset of the received, CoT labeled transaction requests, wherein by supplying a particular CoT labeled grant indication to a particular requesting device, the coherency interconnect grants unconditional availability of a buffer for a transaction of the corresponding class from the particular requesting device.