Patent ID: 7396737
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a pad oxide layer on a semiconductor substrate; forming a nitride layer pattern on the pad oxide layer; forming a spacer oxide layer pattern on the side wall of the nitride layer pattern; removing the nitride layer pattern so as to expose the spacer oxide layer pattern and the pad oxide layer; forming a nitride layer on the spacer oxide layer pattern and the pad oxide layer; forming a groove in the nitride layer by selectively removing the spacer oxide layer pattern; forming a trench in a region of the semiconductor substrate where the groove is formed above the region of the semiconductor substrate; and filling the trench with a thermal oxide layer so as to form a shallow trench isolation (STI) layer, wherein the formation of the spacer oxide layer pattern comprises: forming an oxide layer on the nitride layer pattern; and forming a spacer oxide layer pattern by anisotropically etching the oxide layer.