Patent ID: 6815329
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method for forming an interconnect structure comprising a lower via level and an upper line level, comprising the steps of:forming a via level dielectric layer on a substrate, said via level dielectric layer including one or more dielectric materials, forming a layer of sacrificial material on said via level dielectric layer, patterning said sacrificial material to form slightly oversized wiring-shaped cavities for line level wiring structures, said patterning including a step of stopping at a first via level dielectric layer, forming a thin conformal layer of a sidewall spacer dielectric in said wiring-shaped cavities previously formed in said step of patterning, etching said thin conformal layer sidewall spacer dielectric to form sidewall spacers on said sacrificial material, patterning said via level dielectric with via-shaped cavities for via structures, forming a thin conformal layer of a conductive liner material to provide a diffusion barrier, adhesion layer, and/or seed layer; overfilling said via-shaped and wiring-shaped cavities with a conductive material, removing said overfill of conductive material by chemical mechanical polishing, leaving a planar structure, forming one or more layers on said planar structure to form a bridge structure, the bottom-most layer of said bridge structure being dielectric, at least bottom-most portion of said bottom-most dielectric layer remaining in the bridge structure as part of the via level dielectric for the next via level, removing said sacrificial material, and removing upper portions of said bridge layer whereby said removed upper portions are not in the final structure.