Patent ID: 8618591
Filing Date: 2013-12-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having a base and a pillar array, said pillar array including a plurality of pillars extending upwardly from said base and arranged in rows and columns, said pillars of each of said columns of said pillar array being disposed along a column direction; a plurality of bit lines, each of which extends in the column direction and each of which is disposed between two adjacent ones of said columns of said pillar array; a plurality of word lines, each of which extends in a row direction transverse to said column direction and each of which is electrically connected to a corresponding one of said rows of said pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns, said bit line contacts of each of said columns of said contact array being disposed along the column direction, being embedded in said base, and being electrically connected to a respective one of said bit lines, each of said bit line contacts of each of said columns of said contact array intersecting the respective one of said bit lines and extending between and being electrically connected to two adjacent ones of said pillars.