Patent ID: 9064954
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; and source and drain regions and a gate stack formed on the substrate, wherein the gate stack comprises: wherein the gate conductor has a first sidewall on the one side and a bottom surface thereof covered by the gate dielectric layer, and a second sidewall opposite to the first sidewall covered by a further dielectric layer different from the gate dielectric layer, wherein one of the source and drain regions is on the same side as the first sidewall with respect to the gate stack and another of the source and drain regions is on the same side as the second sidewall with respect to the gate stack, wherein the gate conductor faces a channel region defined between the source and drain regions via the gate dielectric layer on the bottom surface thereof, and wherein the one of the source and drain regions on the one side of the gate stack is stressed.