Patent ID: 7417278
Filing Date: 2008-08-26
Classification: H01L

Abstract:
1. A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with a floating gate of the cell comprising: two trenches in a substrate; a source region between said two trenches; an isolation layer in said trenches, said isolation layer filling a bottom portion of said trenches, wherein said isolation layer in the trench does not cover an upper portion of said trench; a three-dimensional coupling region surrounding the upper portions of said trenches; a floating gate dielectric covering the substrate between said two trenches, including side-walls of the upper portion of said trenches; a floating gate with side-walls reaching into said three-dimensional coupling region in said trench; an inter-gate dielectric covering the side-walls of said floating gate; a conductive layer covering said inter-gate dielectric to form a control gate; and drain regions of said split-gate flash memory cell.