Patent ID: 6243797
Filing Date: 2001-06-05
Classification: G11C

Abstract:
A multiplexing arrangement for transferring data retrieved from a memory array of a semiconductor memory to data outputs of the semiconductor memory, said multiplexing arrangement comprising:a data output register coupled to the memory array, said data output register including a plurality of data storage circuits for storing data retrieved from the memory array;a timing signal generator for generating a plurality of phased timing signals for reading data from said data storage circuits of said data output register; anda multiplexing circuit responsive to said phased timing signals for loading data retrieved from the memory array into said data storage circuits of said data output register;wherein said phased timing signals cause the multiplexing circuit to load data into said data output register in a first predetermined sequence and cause the data stored in the data output register to be passed from the data output register to the data outputs in a second predetermined sequence.