Patent ID: 9111013
Filing Date: 2015-08-18
Classification: G06F,H04L

Abstract:
1. A method comprising: providing a hierarchical, associative memory structure; examining a plurality of addresses of network devices and identifying coordinate sub-fields of the addresses, each address including a plurality of bit positions, each coordinate sub-field being a range of bit positions within the addresses where the bit positions in each address hold either a distinct value for the entire range of bit positions or a don't care value for the entire range of bit positions, wherein the plurality of addresses include Internet Protocol (IP) addresses in hexadecimal format; determining the number of distinct values represented in each coordinate sub-field of the addresses; for each coordinate sub-field of the addresses, computing a minimum number of bits needed to represent the number of distinct values and a don't care value, if present; assigning a unique coordinate value (UCV), that falls within the previously computed minimum number of bits, for each distinct value and the don't care value, if present, with each UCV being shorter than the corresponding value that the UCV replaces; for each address, generating a unique coordinate value sequence (UCVS) by concatenating the UCVs assigned to the distinct values and the don't care value, if present, of the respective address; and loading the hierarchical, associative memory structure with the generated UCVSs.