Patent ID: 6686241
Filing Date: 2004-02-03
Classification: H01L

Abstract:
A method of forming low-resistivity connections in a non-volatile memory formed on a substrate of semiconductor material including memory cells arranged in rows and columns to form a matrix with row lines and column lines, each cell having a first terminal connected to a row line, a second terminal connected to a column line, and a third terminal connected to a common node by means of connection strips of a first, a second and a third plurality of connection strips, respectively, comprising:forming a layer of dielectric material which covers the connection strips of at least one of the first, second and third pluralities of connection strips wherein each connective strip has a first resistivity; selectively removing the dielectric material of the layer of dielectric material so as to form therein channels each of which extends along one of the connection strips of at least one of the first, second and third pluralities of connection strips and is delimited at a bottom surface of the dielectric thereby exposing a surface of the connection strip; and filling the channels with a material having a second resistivity lower than the first resistivity of each of the connection strips of the first, second and third pluralities of connection strips.