Patent ID: 6222763
Filing Date: 2001-04-24
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of data lines;a plurality of source lines;a plurality of memory cells each of which has a threshold voltage corresponding to data of at least two bits, and each of which is coupled to a corresponding data line of said plurality of data lines and which is coupled to a corresponding source line of said plurality of source lines;wherein each of said plurality of memory cells is programmed with data by using a tunnel effect in a program mode, and wherein a threshold voltage of each of said plurality of memory cells is distributed in one of at least four threshold voltage distributions; anda word driver circuit applying a read voltage to one or more selected memory cells a plurality of times in a read mode,wherein said read voltage has at least three voltage levels,wherein, in said read mode, each of source lines coupled to said selected memory cells is coupled so as to be applied with a predetermined potential; andwherein a first read voltage is first applied to said selected memory cells, and then at least two other read voltages at levels higher than said first read voltage are successively applied to said selected memory cells in order to successively read data starting with data corresponding to a lowest threshold voltage distribution and ending with data corresponding to a highest threshold voltage distribution.