Patent ID: 6016070
Filing Date: 2000-01-18
Classification: H03K

Abstract:
A pulse extending circuit comprising:an input terminal receiving an input signal;a first delay circuit having an input coupled to said input terminal and receiving said input signal, and having an output providing a delayed input signal;a first NAND circuit having a first input terminal coupled to said output of said first delay circuit and receiving said delayed input signal, a second input terminal coupled to said input terminal and receiving said input signal, and an output providing a first NAND output signal;a second delay circuit having an input coupled to said output of said first NAND circuit and receiving said first NAND output signal and having an output providing a delayed first NAND output signal;a first inverter having an input coupled to said input terminal and receiving said input signal, and having an output providing an inverted input signal; anda second NAND circuit having a first input terminal coupled to said output of said second delay circuit and receiving said delayed first NAND output signal, and having a second input terminal coupled to said output of said first inverter and receiving said inverted input signal.