Patent ID: 8502349
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. A manufacturing method of PN-junction varactor in a BiCMOS process, the method comprising the following steps: step 1: forming shallow trenches and an active area in a P-type silicon substrate; step 2: forming N-type pseudo buried layers by performing N-type ion implantation to bottoms of the shallow trenches on both sides of the active area; step 3: forming shallow trench field oxide regions by filling silicon oxide into the shallow trenches; step 4: forming an N-type region by performing N-type ion implantation to the active area; the depth of the N-type region is larger than those of bottoms of the shallow trench field oxide regions; the bottom of the N-type region laterally extends into the bottoms of the shallow trench field oxide regions on both sides of the active area and contacts with the N-type pseudo buried layers; step 5: forming a P-type region by performing P-type ion implantation to the active area; the P-type region is situated in an upper part of the N-type region and contacts with the N-type region to form a PN-junction; step 6: performing drive-in annealing to the N-type region, the P-type region and the N-type pseudo buried layers; step 7: forming deep hole contacts on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region; forming a metal contact on top of the P-type region to pick up the P-type region.