Patent ID: 6278964
Filing Date: 2001-08-21
Classification: G01R,G06F

Abstract:
A method for simulating hot carrier effects in an integrated circuit (IC) that contains a plurality of semiconductor devices, the method comprising the steps of:receiving IC cell data that specifies a set of one or more cells in the IC, each cell containing one or more of the plurality of semiconductor devices;generating delay data and unscaled timing data of the set of one or more cells;generating, based upon the delay data and switching activity of each cell, aged delay data that reflects time-based performance degradation of time delays for the set of one or more cells; andgenerating, based upon unscaled timing data that specifies timing delays associated with the set of one or more cells, scaled timing data by scaling the unscaled timing data with a delay ratio, whereinsaid delay data and said aged delay data are used to determine said delay ratio.