Patent ID: 7102389
Filing Date: 2006-09-05
Classification: H03K

Abstract:
1. A voltage translator with data buffer comprising: an input inverter receiving a data input signal at a first voltage level; a level shifting cross-coupled NOR circuit coupled to said input inverter for translating said data input signal at a second voltage level, said level shifting cross-coupled NOR circuit being formed by first and second cross-coupled NORs, said first cross-coupled NOR having a first NOR output and said second cross-coupled NOR having a second NOR output, said first cross-coupled NOR receiving inputs of said data input signal and said second NOR output, and said second cross-coupled NOR receiving inputs of an inverted data input signal and said second NOR output; and an output stage formed by a series connected output P-channel field effect transistor (PFET) and an output N-channel field effect transistor (NFET), each of said output PFET and said output NFET driven by said cross-coupled NOR circuit for providing a data output signal at said second voltage level; said output PFET having a gate directly connected to said first NOR output; and said output NFET having a gate connected via an inverter to said second NOR output.