Patent ID: 6664167
Filing Date: 2003-12-16
Classification: H01L

Abstract:
A semiconductor memory, comprising:a substrate; at least two memory cells, each of said memory cells disposed at least partly in said substrate and each of said memory cells having: a transistor having: a drain region; a source region; and a channel; a first word line disposed between said source region and said drain region; a trench capacitor having: an inner electrode; an outer electrode; and a dielectric layer disposed between said inner electrode and said outer electrode; a trench disposed in said substrate and filled with a conductive trench filling forming said inner electrode of said trench capacitor; an insulating covering layer disposed on said conductive trench filling; an epitaxial layer disposed on said substrate and at least partly on said insulating covering layer; said source region, said drain region, and said channel of said transistor disposed in said epitaxial layer; a trench isolation disposed in said substrate and in said epitaxial layer, said trench isolation insulating adjacent ones of said memory cells from one another, said trench isolation respectively extending into said inner electrode of each of two adjacent ones of said memory cells; said first word line disposed on said epitaxial layer and partly covering said trench; a first insulation encapsulation surrounding said first word line; a second word line disposed on said trench isolation; a second insulation encapsulation surrounding said second word line; a contact trench having a self-aligned connection electrically connecting said conductive trench filling to said drain region, said contact trench disposed between said first word line with said first insulation encapsulation and said second word line with said second insulation encapsulation; and said trench isolation bounding said contact trench.