Patent ID: 6423992
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A semiconductor integrated circuit device, comprising:memory cell selection MISFETs formed in a memory cell array region on a semiconductor substrate; peripheral circuit MISFETs formed in a peripheral circuit region around said memory cell array region; a first interlayer insulating film which covers said memory cell selection MISFETs and said peripheral circuit MISFETs; bit lines formed over said first interlayer insulating film lying in said memory cell array region; at least one information storage capacitive element provided with a lower electrode electrically connected to a source-to-drain region of a memory cell selection MISFET; and a second interlayer insulating film including: a first portion formed in the same layer as that for said information storage capacitive element so as to substantially eliminate a steplike offset between said memory cell array region and said peripheral circuit region, which steplike offset is caused by the height of said information storage capacitive element; and a second portion which covers said information storage capacitive element, wherein the surface of said second interlayer insulating film is flattened and interconnection grooves are defined in the vicinity of the surface thereof, and interconnections having surfaces within the same plane as said surface of said second interlayer insulating film are formed inside said interconnection grooves.