Patent ID: 6629289
Filing Date: 2003-09-30
Classification: G06F

Abstract:
A method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including said object logic cell, comprising:(a) determining first delay data of said first signal from a first external input terminal to said object logic cell, first waveform slew data of said first signal to said object logic cell and first signal data indicating a frequency, duty ratio and jitter of said first signal, and a second delay data, a second waveform slew data and second signal data indicating a frequency, duty ratio and jitter of said second signal to said object logic cell; (b) calculating in time, a first portion of a first waveform of said first signal at said object logic cell based on said first delay data, said first waveform slew data and said first signal data; (c) calculating in time, a second portion of a second waveform of said second signal at said object logic cell based on said second delay data, said second waveform slew data and said second signal data; and (d) evaluating whether said first portion of said first waveform overlaps said second portion of said second waveform.