Patent ID: 6505332
Filing Date: 2003-01-07
Classification: G06F

Abstract:
An apparatus for generating a logic cell library which stores a calculation result of a delay time of each wire and which is used in performing layout of wiring including a plurality of wires, said apparatus comprising:a sectional shape file for storing a sectional shape of each wire; a material data file for storing property information of a material of the wiring; a wiring information file for storing wiring information representing a relationship of connection of the respective wires; a device simulator for referring to the stored contents in said sectional shape file, said material data file and said wiring information file to derive capacitance values and resistance values at respective positions of the respective wires; an adjacent wire information file for storing different wiring resistance values for respective positions of the respective wires depending on information regarding distance to an adjacent wire on one side or both sides of each wire, wherein, in said adjacent wire information file, said wiring resistance values are defined for each small incremental section of said wire such that a largest value is provided when adjacent wires exist each within a predetermined distance on both sides of said wire, a second largest value is provided when an adjacent wire exists within the predetermined distance on only one side of said wire, and a smallest value is provided for an isolated said wire with no adjacent wires within the predetermined distance on either side thereof; a layout verification tool for receiving output from said device simulator, a provided mask layout pattern and the stored contents in said adjacent wire information file to verify wiring layout for deriving input loads and output driving capability; a circuit simulator for performing a simulation of circuit operations based on output from said layout verification tool, a provided net list and a test standard; and a delay calculator for calculating a basic delay time obtained from wiring resistance for each position of each wire based on the output from said circuit simulator, wherein said basic delay is stored in said logical cell library.