Patent ID: 6940762
Filing Date: 2005-09-06
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array which has memory cells arranged in a matrix, each memory cell having a first MOS transistor with a stacked gate including a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer with an inter-gate insulating film interposed therebetween; bit lines each of which connects one end of the current path of each of the first MOS transistors in the same column in common electrically; first word lines each of which connects the second semiconductor layers of the first MOS transistors in the same row in common; a column selector which selects any one of the bit lines; a column decoder which controls the column selector; and a first row decoder which selects any one of the first word lines, at least one of the column decoder and the first row decoder including a level shift circuit which includes: