Patent ID: 8315104
Filing Date: 2012-11-20
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell string comprising memory cells connected in series; a bit line electrically connected to one end of a current path of the memory cell string; a source line electrically connected to the other end of the memory cell string; a control circuit configured to perform a verify operation to check a write result after data is written to a memory cell of the memory cells connected in series; and a voltage setting circuit connected to the bit line through a transistor, the voltage setting circuit being configured to set a charging voltage for the bit line in a verify operation and a read operation and to make a first charging voltage in a read operation higher than a second charging voltage in a verify operation, the first and second charging voltages being higher than a ground voltage, wherein the control circuit determines whether the bit line has been discharged by the memory cell after the bit line has been charged to the first and second charging voltages in a read operation and verify operation, respectively.