Patent ID: 6975555
Filing Date: 2005-12-13
Classification: G11C

Abstract:
1. A magnetic random access memory circuit, comprising: a plurality of magnetic memory cells, each of the memory cells comprising a magnetic storage element having an easy axis and a hard axis associated therewith; a plurality of column lines, each of the memory cells being electrically connected to one of the plurality of column lines at a first terminal of the memory cell; a plurality of write row lines and read row lines for selectively writing and reading, respectively, a logical state of one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the write row lines, each of the memory cells being electrically connected to one of the read row lines at a second terminal of the memory cell; at least one row line circuit configurable for generating a write current for writing the logical state of one or more of the memory cells, the at least one row line circuit being operatively coupled to the write row lines and read row lines, the write row lines conveying the write current; and at least one column line circuit configurable for generating at least one of a sense current and a sense voltage for reading the logical state of one or more of the memory cells, the at least one column line circuit being operatively coupled to the column lines, the column lines conveying the sense current; wherein each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of the sense current and the hard axis is substantially parallel to a direction of flow of the write current.