Patent ID: 6671846
Filing Date: 2003-12-30
Classification: G01R,G06F

Abstract:
A method of identifying failed cells of a plurality of connected logic cells in a circuit having a plurality of output signal pads upon which pad output signals are supplied, the logic cells and waveforms from the logic cells described by using a simulation tool, the waveforms including input and output waveforms to and from each logic cell, the output waveform from a logic cell connected to the output signal pad constituting the pad output signal, the simulation tool describing a transition and a transition time point when the transition occurs, said method comprising the steps of:selecting an output waveform and a transition time point of the selected output waveform delivered from a selected logic cell; identifying a predictive input waveform and a transition time of the predictive input waveform to the selected logic cell which causes the transition of the output signal from the selected logic cell at the selected transition time; identifying a predictive logic cell connected to the selected logic cell which supplies the output waveform to the selected logic cell which constitutes the predictive input waveform identified in the preceding step; performing at least one new repetition of the aforesaid three steps to accomplish the selecting and identifying steps under circumstances where the predictive logic cell identified in a previous repetition becomes the selected logic cell for the new repetition and the transition time point of the predictive input waveform to the selected logic cell of the previous repetition becomes the selected transition time of the output waveform of the selected logic cell for the new repetition; defining a logic cone formed from each of the logic cells selected and identified by performing the repetitions; using the pad output signal from a selected output pad as the output waveform for performing the repetitions to define the logic cone from that selected output pad; defining different logic cones from the different output pads from multiple selected output pads which the pad output signals are selected; and identifying the logic cells which are common to the multiple logic cones.