Patent ID: 6088284
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A multiple input/output memory chip which is capable of being used as each of a .times.n, .times.2n or .times.4n I/O system, wherein ""n"" is a prescribed number of bits, comprising:a block selecting unit for receiving a source voltage or a column address lowest bit and thereby selectively activating a first block selection signal or a second block selection signal;a column control unit for receiving a source voltage or a column address lowest bit and thereby selectively activating a first column control signal or a second column control signal;a first bank for reading or writing each of n-bit or 2n-bit data in accordance with the first or second column control signal and the first block selection signal;a second bank for reading or writing each of n-bit or 2n-bit in accordance with the first or second column control signal and the second block selection signal; anda data bus coupled to the first bank and the second bank and dividable into up to four parts, wherein based on the first bank and the second bank, the chip is capable of operating as said each of the .times.n, .times.2n or .times.4n I/O system.