Patent ID: 6303417
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method of forming a self-aligned planarization twin-well with reducing masks for CMOS transistor, said method comprising the steps of:forming a first pad oxide layer on a semiconductor substrate;forming a nitride layer on said first pad oxide layer;patterning a first photoresist layer to define a first well region;performing a first ion implantation in said first well region by using said first photoresist layer as a mask;removing said first photoresist layer;performing a second ion implantation in said substrate to define a second well region;removing said nitride layer and said first pad oxide layer;performing a first thermal process on said substrate to form a twin-well;patterning a second photoresist layer to define a plurality of trenches;forming a plurality of trenches in said substrate using said second photoresist layer as a mask to define active regions;forming a LPD oxide layer to refill in said plurality of trenches by liquid phase deposition;removing said second photoresist layer;performing a second thermal process on said LPD oxide layer to densify said LPD oxide layer, wherein said second thermal process also serves as an in-situ thermal anneal to said twin-well;etching back a portion of said LPD oxide layer to a top surface of said substrate;forming a second pad oxide layer on said substrate; andforming said CMOS transistor on said first well region and said second well region.