Patent ID: 6216223
Filing Date: 2001-04-10
Classification: G06F

Abstract:
An apparatus for dynamically expanding an instruction pipeline with a second fetch cycle for a VLIW memory access when required for indirect accessing of very long word instruction words (VLIWs) in a VLIW processor comprising:a plurality of instruction decode units;a plurality of execute units;a first random access memory for storing short instruction words (SIWs);a program flow control unit to control fetching of SIWs from the first random access memory;a first instruction register for storing one or more of the SIWs fetched from the first random access memory;a second random access memory for storing VLIWs used in operations involving execution of two or more of said plurality of execute units in parallel;a VLIW memory control unit for reading VLIWs from the second random access memory;a second instruction register for storing the one or more of the SIWs in an expanded pipeline mode of operation;a VLIW instruction register for storing one or more VLIWs fetched from the second random access memory; anda pipeline control unit that decodes the one or more SIWs in the first instruction register and controls data flow paths to the decode units and the execute units for the purposes of reconfiguring the instruction pipeline in an expanded or a compressed mode of operation.