Patent ID: 6608344
Filing Date: 2003-08-19
Classification: H01L

Abstract:
A structure of a semiconductor device, in which at least a conductive layer is formed on an impurity diffusion layer in which a source and a drain of at least one transistor are formed, and a lower electrode of a memory cell capacitor part of a stacked capacitor type memory cell composed of 1T1C (one transistor one capacitor) is formed by removing a part of said conductive layer, wherein:said lower electrode, comprising: two kinds of spaces at said conductive layer, wherein: one of said two kinds of spaces is a small space and is disposed at the center part in said conductive layer; and the other of said two kinds of spaces is a large space and is disposed at the outer part in said conductive layer in a state that side surfaces of said large space have a difference in level at its middle part and the bottom surface of said large space reaches to an interlayer, wherein: the surface of said lower electrode has an uneven surface by the structure mentioned above.