Patent ID: 9183898
Filing Date: 2015-11-10
Classification: G11C

Abstract:
1. A circuit device, comprising: a multiple data rate transmission circuit having at least two clocked inputs, the multiple date rate transmission circuit configured to generate a single encoded output that reduces a toggle rate between the at least two clocked inputs, wherein the multiple data rate transmission circuit includes an encoder configured to generate an encoded output with respect to a current state and a previous state of a clocked input of the at least two clocked inputs, an another encoder configured to generate an another encoded output with respect to a current state and a previous state of another clocked input of the at least two clocked inputs and a multiplexer configured to generate the single encoded output from the encoded output and the another encoded output; and a multiple data rate receiver circuit, wherein the multiple data rate receiver circuit is clocked to decode the at least two clocked inputs from the single encoded output.