Patent ID: 7937561
Filing Date: 2011-05-03
Classification: G06F

Abstract:
1. An out-of-order execution microprocessor for processing a non-memory access macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register of the microprocessor, the microprocessor comprising: an instruction translator, configured to translate the non-memory access macroinstruction into a single microinstruction, wherein the single microinstruction is a merge microinstruction, wherein the merge microinstruction specifies an N-bit first source register, an 8-bit second source register, and an N-bit destination register to receive an N-bit result, wherein said N-bit first source register and said N-bit destination register are the N-bit architected general purpose register specified by the macroinstruction; and an execution unit, coupled to the instruction translator, configured to receive the merge microinstruction and to responsively generate the N-bit result to be subsequently written to the N-bit architected general purpose register specified by the macroinstruction even though the macroinstruction only instructs the microprocessor to write the 8-bit result into the lower 8 bits of the N-bit architected general purpose register, wherein in order to generate said N-bit result said execution unit is configured to direct the 8-bit result into the lower 8 bits of the N-bit result and to direct the upper N-8 bits of the N-bit first source register specified by the merge microinstruction into corresponding upper N-8 bits of the N-bit result.