Patent ID: 8940565
Filing Date: 2015-01-27
Classification: G02F,H01L

Abstract:
1. A method of manufacturing a thin-film transistor array substrate, the method comprising: providing a plurality of gate lines and a plurality of data lines on a first substrate; providing an organic layer on the gate lines and the data lines; providing a first electrode on the organic layer; providing a passivation layer on the first electrode; providing a second electrode on the passivation layer; providing a first cover layer on the second electrode to cover the second electrode; providing a plurality of first photosensitive layer patterns on the first cover layer; providing a plurality of first cutout patterns in the first cover layer and a plurality of second cutout patterns in the second electrode using the first photosensitive layer patterns as an etch mask; and providing a plurality of third cutout patterns in the passivation layer using the first cover layer as an etch mask.