Patent ID: 9106265
Filing Date: 2015-08-11
Classification: H03M,H04L

Abstract:
1. A receiver comprising: a frequency deinterleaver (FDI) coupled to receive data and control information including transmission parameters associated with the data and supply frequency deinterleaved cells corresponding to the data and frequency deinterleaved cells corresponding to the control information; a time deinterleaver (TDI) to generate forward error correction (FEC) blocks based on the frequency deinterleaved cells; a forward error correction (FEC) circuit coupled to the time deinterleaver to apply forward error correction to the FEC blocks and coupled to the frequency deinterleaver to apply forward error correction to the control information; and control logic to control outputs from the frequency deinterleaver and the time deinterleaver to prioritize processing of the control information in the FEC circuit over processing of FEC blocks.