Patent ID: 9202531
Filing Date: 2015-12-01
Classification: G11C

Abstract:
1. A sense amplifier, comprising: a first PMOS transistor configured to connect a complementary sensing bitline with a line of a first control signal in response to a sensing bitline; a second PMOS transistor configured to connect the sensing bitline with the line of the first control signal in response to the complementary sensing bitline; a first NMOS transistor configured to connect the complementary sensing bitline with a line of a second control signal in response to a bitline; a second NMOS transistor configured to connect the sensing bitline with the line of the second control signal in response to a complementary bitline; a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal; a second isolation switch configured to connect the complementary bitline with the complementary sensing bitline in response to the isolation signal; a first offset cancellation switch configured to connect the bitline with the complementary sensing bitline in response to an offset cancellation signal; and a second offset cancellation switch configured to connect the complementary bitline with the sensing bitline in response to the offset cancellation signal.