Patent ID: 9076685
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a lower gate layer; a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer; a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer; and a memory film provided between the electrode layer and the channel body, the memory film including a charge storage film, wherein the plurality of electrode layers has a first electrode layer and a second electrode layer below the first electrode layer, each of the first electrode layer and the second electrode layer including a lower step portion, an upper step portion, and an intermediate portion between the lower step portion and the upper step portion, the channel body and the memory film extending in the intermediate portion in a stacking direction of the stacked body, and a first distance between a bottom surface of the lower step portion of the first electrode layer and a top surface of the upper step portion of the second electrode layer is less than a second distance between the lower step portion of the first electrode layer and the lower step portion of the second electrode layer, and between the upper step portion of the first electrode layer and the upper step portion of the second electrode layer.