Patent ID: 6083847
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method for manufacturing local interconnects, comprising:providing a substrate with an isolating structure formed, a gate oxide layer over the substrate, a gate electrode above the gate oxide layer wherein the gate electrode has opposite sidewalls, a first spacer on one of the gate electrode sidewalls, and a second spacer on the other of the gate electrode sidewalls;providing a layer of photoresist over the gate electrode, the gate oxide layer and the second spacer, while leaving the first spacer exposed;removing the first spacer to expose the one sidewall of the gate electrode while leaving the other sidewall of the gate electrode covered by the second spacer;removing the photoresist layer; andperforming a self-aligned silicide processing operation to form a continuous metal silicide layer simultaneously over the gate electrode, the one sidewall of the gate electrode and portions of the substrate leading to a local interconnect termination region, while leaving the other sidewall of the gate electrode covered by the second spacer.