Patent ID: 6919616
Filing Date: 2005-07-19
Classification: G02B,H01L

Abstract:
1. A chip, comprising: a first chip section comprising first and second sides, a first device region disposed between said first and second sides, a plurality of first off-chip electrical contacts disposed between said first device region and said first side, a plurality of first electrical contacts disposed between said first device region and said second side, a plurality of first electrical traces that each is electrically interconnected one of said first off-chip electrical contacts and one of said first electrical contacts, a plurality of second electrical traces that each is electrically interconnected with one of said first off-chip electrical contacts and extends into said first device region where said plurality of second electrical traces each terminate, and a plurality of third electrical traces that each is electrically interconnected with one of said first electrical contacts and extends into said first device region where said plurality of third electrical traces each terminate, wherein each of said plurality of first off-chip electrical contacts and said plurality of electrical contacts are structurally different than said plurality of first, second, and third electrical traces; a second chip section comprising third and fourth sides, a second device region disposed between said third and fourth sides, a plurality of second electrical contacts disposed between said second device region and said third side, a plurality of third electrical contacts disposed between said second device region and said fourth side, a plurality of fourth electrical traces that each is electrically interconnected with one of said second electrical contacts and one of said third electrical contacts, a plurality of fifth electrical traces that each is electrically interconnected with one of said second electrical contacts and extends into said second device region where said plurality of fifth electrical traces each terminate, and a plurality of sixth electrical traces that each is electrically interconnected with one of said third electrical contacts and extends into said second device region where said plurality of sixth electrical traces each terminate, wherein each of said plurality of second and third electrical contacts are structurally different than said plurality of fourth, fifth, and sixth electrical traces, and wherein said second side of said first chip section is disposed against said third side of said second chip section; and a plurality of inter-section electrical traces each extending between one of said first and third electrical traces and one of said fourth and fifth electrical traces.