Patent ID: 6314489
Filing Date: 2001-11-06
Classification: H04L,H04Q

Abstract:
A data cell storage system comprising:a plurality of memory units for storing data cells, wherein each memory unit has a corresponding set of memory addresses;means for outputting a memory address of one of the plurality of memory units;a memory selecting unit for selecting one of the plurality of memory units based on the outputted memory address and the corresponding sets of memory addresses of the plurality of memory units; andmeans for performing a read or write operation at the memory address of the selected memory unit,wherein the outputting means further includes a free list memory for storing write addresses of the plurality of memory units at which the read or write operation performing means may write a data cell into one of the plurality of memory units, and wherein the memory address corresponds to a write address stored in the free list memory, andwherein the outputting means outputs a control signal to indicate whether the system can store an input data cell, and wherein the free list memory further includes:a first free list memory unit for storing write addresses of a first memory unit of the plurality of memory units at which the read or write operation performing means may write a data cell into the first memory unit;a second free list memory unit for storing write addresses of a second memory unit of the plurality of memory units at which the read or write operation performing means may write a data cell into the second memory unit; anda free list memory selecting unit for selecting one of the free list memory units based on the control signal.