Patent ID: 6888196
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. A vertical MOSFET comprising: a semiconductor layer ( 1 , 2 , 9 , 10 ) having first and second surfaces opposite to each other and a pair of trenches ( 6 ) formed on said first surface; a pair of trench gates ( 8 ) formed in said pair of trenches; a unit cell formed in a region of said semiconductor layer surrounded by said pair of trench gates, said unit cell comprising a base layer ( 9 ) and a source layer ( 10 ) formed on said base layer and having said first surface as a principal semiconductor surface, said unit cell having a contact hole ( 12 ) formed on a center of said principal semiconductor surface and extending from said principal semiconductor surface through said source layer to an inside of said base layer; a contact ( 17 ) formed in said contact hole; a source electrode ( 18 ) formed on said contact; and a drain electrode ( 19 ) formed on said second surface; wherein said contact is formed to a depth different to a peak depth which is a position having a maximum impurity-concentration in a depth direction of said base layer, said unit cell further comprising a base contact layer ( 14 ) formed within said base layer so as to enclose a bottom of said contact and to bring said base contact layer into contact with the bottom of said contact.