Patent ID: 6801706
Filing Date: 2004-10-05
Classification: H04N

Abstract:
A jitter correcting apparatus for correcting jitter of an input video signal in a video signal reproduction system including a digital video decoder for demodulating the video signal and a first clock circuit for generating a first clock signal synchronized with the video signal, the jitter correcting apparatus comprising:an address generator for generating a write address for writing the video signal in response to the first clock signal, for generating a read address for reading the video signal in response to a second clock signal having a fixed frequency, and for correcting the write and read addresses in response to first and second comparison signals; a comparator for comparing the write address with the read address and for generating the first comparison signal and the second comparison signal according to a result of the comparison; and a dual port memory device for storing the video signal at a location corresponding to the write address in response to the first clock signal and for outputting a video signal stored at a location corresponding to the read address in response to the second clock signal.