Patent ID: 6376328
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method for producing capacitor elements constructed of a lower electrode, a dielectric body layer and an upper electrode, which are formed on a semiconductor substrate, comprising:a first silicon layer forming step for forming a first amorphous silicon layer at an appointed area on the semiconductor substrate, a lower electrode surface rinsing step for rinsing the surface of said first silicon layer, a nucleus forming step for selectively forming a second amorphous silicon layer including microcrystal on the surface of said first silicon layer, an HSG forming step for growing HSGs (hemispherical Grains) using microcrystal included in said second silicon layer as a nucleus by annealing said first and second silicon layer at a low pressure or in the atmosphere of an inactive gas, and forming HSGs on the surface of said first silicon layer, an impurity diffusing step for forming a lower electrode by annealing while said HSGs are being exposed to a source gas including impurities and thermally diffusing said impurities in said HSGS, a dielectric body layer forming step for forming a dielectric body layer on said first silicon layer having said HSGs on the surface thereof, and an upper electrode forming step for forming an upper electrode on said dielectric body layer, wherein the partial pressure of oxygen and water is maintained at 1Ã—10âˆ’6 Torr or less at least between said HSG forming step and said impurity diffusing step.