Patent ID: 7563683
Filing Date: 2009-07-21
Classification: H01L

Abstract:
1. A method of fabricating a transistor comprising: forming an isolation trench defining an active region in a semiconductor substrate while allowing an isolation hard mask pattern to remain on the active region; isotropically etching the isolation hard mask pattern to expose a boundary portion of said active region, to form a mesa hard mask pattern on a central portion of the active region, and to concurrently form an extended opening defined by the mesa hard mask pattern over the isolation trench; forming a buried insulating layer to fill the isolation trench and the extended opening; removing the buried insulating layer to expose the boundary portion of the active region, and concurrently to form a buried insulating layer pattern on the inside of the isolation trench; anisotropically etching the exposed boundary portion of the active region by using the buried insulating layer pattern and the protrusion hard mask pattern as etch masks to form a mesa in the active region; removing the overall mesa hard mask pattern and the upper portion of the buried insulating layer pattern; and forming a gate electrode to cross over the active region along the direction across the mesa.