Patent ID: 6351037
Filing Date: 2002-02-26
Classification: H01L

Abstract:
An improved electrical contact between patterned polycide layers for interconnections on integrated circuits, comprised of:a semiconductor substrate having field oxide regions surrounding and electrically isolating device areas; a doped first polysilicon layer on said field oxide regions and said device areas, and a silicide layer on said first polysilicon layer, both patterned to provide a first polycide interconnection; an insulating layer on said patterned first polycide layer thereby electrically insulating said patterned first polycide layer; said insulating layer having contact openings, said contact openings extending through said first silicide layer and through said first polysilicon layer to surface of said field oxide regions; a doped second polysilicon layer over said insulating layer and in said contact openings contacting said first polysilicon layer, thereby forming improved electrical contacts between said first and second polysilicon layers; a second silicide layer on said second polysilicon layer, said second silicide layer and said second polysilicon layer patterned to provide a second polycide interconnection.