Patent ID: 6066563
Filing Date: 2000-05-23
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device having a complementary MOS transistor, comprising the steps of:forming a poly-crystalline semiconductor film serving as a gate electrode on one major surface of a semiconductor substrate via a gate insulation film;forming a first solid phase diffusion source containing an impurity of a first conduction type selectively on a portion of said poly-crystalline semiconductor film corresponding to a first channel MOS transistor forming region;forming a second solid phase diffusion source containing an impurity of a second conduction type on an entire surface including a surface of said first solid phase diffusion source and a surface of said poly-crystalline semiconductor film corresponding to a second channel MOS transistor forming region;polishing said second solid phase diffusion source by a, chemical mechanical polishing technique to a position where said first solid phase diffusion source is exposed; andpatterning said poly-crystalline semiconductor film together with said first solid phase diffusion source and said second solid phase diffusion source to attain a gate electrode pattern.