Patent ID: 6632591
Filing Date: 2003-10-14
Classification: H05K,Y10T

Abstract:
A method of forming a structure which provides capacitance electrical pathways and resistance electrical pathways, the method comprising:depositing on a substrate a first outer layer of resistive material between about 10 and about 250 nanometers thick, depositing thereon a layer of dielectric material between about 10 and about 750 nanometers thick, optionally depositing thereon alternating layers of resistive material, each between about 10 and about 250 nanometers thick, and dielectric material layers, each between about 10 and about 750 nanometers thick, depositing a second outer layer of resistive material between about 10 and about 250 nanometers thick, patterning said second outer layer of resistive material to form resistive material patches and providing electrical connects to said resistive material patches, laminating said second outer layer of resistive material to laminate-supportive dielectric material, removing said substrate from said first outer layer, patterning said first outer layer of resistive material to form resistive material patches and providing electrical connects to said resistive material patches, resistive material patches on opposed sides of said laminate providing capacitance electrical pathways, and providing electrical connects so as to form resistance electrically pathways horizontally through a resistive material layer(s) of said laminate.