Patent ID: 8877568
Filing Date: 2014-11-04
Classification: H01L,Y10S

Abstract:
1. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising: forming a gate dielectric layer on the substrate; forming a first conductive layer on the gate dielectric; patterning the first conductive layer over the NVM region and removing the first conductive layer over the logic region; forming a dielectric layer over the NVM region including the first conductive layer and over the logic region; forming a protective layer over the dielectric layer; removing the dielectric layer and the protective layer from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region; forming a high-k dielectric layer over the logic region and the remaining portion of the protective layer; forming a first metal layer over the high-k dielectric layer; removing the first metal layer, the high-k dielectric, and the remaining portion of the protective layer over the NVM region to leave a remaining portion of the first metal layer and a remaining portion of the high-k dielectric layer over the logic region; forming a second conductive layer over the remaining portion of the dielectric layer and over the first metal layer; and forming the NVM cell and the logic transistor including patterning the second conductive layer to leave a first portion of the second conductive layer over the remaining portion of the first metal layer and a second portion of the second conductive layer over the remaining portion of the dielectric layer.