Patent ID: 8892917
Filing Date: 2014-11-18
Classification: G06F,Y02B,Y02D

Abstract:
1. A memory system comprising: a memory chip which has a high power consumption operation mode and a low power consumption operation mode in accordance with internal operation of the memory chip, wherein power consumption of the memory chip is lower in the low power consumption operation mode than in the high power consumption operation mode, and the memory chip asserts a high-power-consumption operation output when the memory chip is in the high power consumption operation mode which indicates the memory chip is in the high power consumption operation mode; and a controller chip which is communicatively coupled to the memory chip, and which has an interface function between a host and the memory chip and receives the high-power-consumption operation output, the controller chip switching an operation mode thereof from a high power consumption mode to a low power consumption mode in response to receiving the high-power-consumption operation output from the memory chip, the power consumption of the controller chip being lower in the low power consumption mode than in the high power consumption mode, wherein the controller chip includes an operation mode switching signal generating circuit which generates a switching signal for switching the operation mode of the controller chip in accordance with the high-power-consumption operation output, and a memory chip interface circuit, and the switching signal is supplied to the memory chip interface circuit, and the memory chip interface circuit halts data transfer with the memory chip when the switching signal has asserted the low power consumption mode.