Patent ID: 7424581
Filing Date: 2008-09-09
Classification: G06F

Abstract:
1. An integrated circuit active memory comprising: a memory interface coupled to receive externally generated commands and addresses through an external port, the memory interface further being operable to transmit data to and from the external port, the memory interface being operable to select a processing element operation and to output memory control signals and processor control signals responsive to the externally generated commands, and to output processing element array addresses and memory device addresses responsive to the externally generated addresses; an array of processing elements coupled to the memory interface, the processing elements in the array being selected by the processing element array addresses, the selected set of processing elements being further operable to receive data from the memory interface and to transmit the data received from the memory interface to an internal data port responsive to the processor control signals, the selected set of processing elements further being operable to receive data at the internal data port and to transmit the data received at the internal data port to the memory interface responsive to the processor control signals; a memory device coupled to the memory interface and to the array of processing elements through the internal data port of the processing elements, the memory device being operable responsive to the memory control signals to receive data from the internal data port, and to store the data received from the internal data port at a location in the memory device selected by the memory device addresses, the memory device further being operable responsive to the memory control signals to receive data stored in the memory device at a location selected by the memory device addresses and to transmit the data stored in the memory device to the internal data port; and a control logic unit included in the memory interface, the control logic unit being coupled to the external port to receive externally generated commands and addresses, the control logic unit being coupled to the memory device to apply the memory control signals and memory device addresses to the memory device responsive to the externally generated commands and addresses, the control logic unit further being coupled to the array of processing elements to apply the processor control signals and the Processing element array addresses to the set of processing elements responsive to the externally generated commands and addresses, the control logic unit comprising: