Patent ID: 6727956
Filing Date: 2004-04-27
Classification: H04N

Abstract:
A sync signal generator circuit which receives a first sync signal to generate a second sync signal, comprising:a first counter which counts predetermined clock pulses to output a counted value and which resets the counted value of said first counter each time said first counter detects a reference edge of the first sync signal; a first register which holds a first value Ni which is the counted value of said first counter immediately before said first counter is reset; a reset signal generator which generates a reset pulse; a second counter which counts predetermined clock pulses to output a counted value and which resets the counted value of said second counter each time said second counter receives the reset pulse; a second register which holds a second value No which is the counted value of the second counter immediately before said second counter is reset; and a sync pulse generator which generates the second sync signal on the basis of the reset pulse; wherein said reset signal generator generates the reset pulse each time the counted value of said second counter matches a predetermined value Np or each time the first counter detects the reference edge of the first sync signal while an absolute value of a difference between the counted value of said second counter and the second value No is not greater than a predetermined permissible value Nj of a period fluctuation of the second sync signal, the predetermined value Np being equal to a reference value Nr if the reference value Nr, which is predetermined on the basis of the first value Ni, is equal to the second value No, the predetermined value Np being greater than the second value No and not greater than a value No+Nj if the reference value Nr is greater than the second value No, the predetermined value Np being not smaller than a value Noâˆ’Nj and smaller than the second value No if the reference value Nr is smaller than the second value No.