Patent ID: 6339245
Filing Date: 2002-01-15
Classification: H01L

Abstract:
A MOS transistor having shallow source/drain junctions with low leakage current comprising:silicon source/drain regions having horizontal top surfaces, and edges around the perimeter of said top surfaces; field oxide regions with boundaries adjacent at least part of said top surface perimeter; source/drain junction areas with metallurgical edges at a predetermined junction depth from said respective source/drain top surfaces; a gate electrode having vertical sidewalls adjacent said source/drain regions; nitride overhang structures overlying said gate electrode vertical sidewalls and said field oxide boundaries, adjoining said source/drain top surfaces, said nitride overhang structures having a first gap between said overhang structures and said source/drain top surfaces; and low resistance silicide layers overlying said source/drain top surfaces, said suicide layers having a predetermined nominal silicide layer thickness and a predetermined silicide thickness tolerance, whereby the spacing between said metallurgical edges and said silicide layer is maximized by prevention silicide perturbations on said silicon top surfaces.