Patent ID: 9077323
Filing Date: 2015-07-07
Classification: H03K

Abstract:
1. A comparator circuit comprising: an amplifier having an output; and a latching circuit having an input coupled to the output of the amplifier, wherein the latching circuit includes a first transistor that is coupled between a first power supply line and a first node, a second transistor that is coupled between the first power supply line and a second node, a third transistor that is coupled between the first and second nodes and that receives a clock signal, a first input transistor that is coupled in series with the first transistor, a second input transistor that is coupled in series with the second transistor, and an additional transistor that is coupled in series between the first transistor and the first input transistor and that has a gate that receives a control signal that is different than the clock signal, wherein the first transistor has a gate that is coupled to the second node, wherein the second transistor has a gate that is coupled to the first node, and wherein the first and second input transistors have gates that receive signals generated at the output of the amplifier.