Patent ID: 6567295
Filing Date: 2003-05-20
Classification: G11C

Abstract:
An addressing circuit for addressing a cross-point memory array having first and second sets of electrodes arranged so that each electrode in the first set crosses over each electrode in the second set and a respective memory element is formed at each crossing point of the electrodes from the first and second sets, the addressing circuit comprising:a first set of address lines and a plurality of first diode elements coupled between the first set address lines and the first set electrodes, wherein each of said first set electrodes are coupled by said first diode elements to a respective unique subset of the first set address lines; and a second set of address lines and a plurality of second diode elements coupled between the second set address lines and the second set electrodes, wherein each of said second set electrodes are coupled by said second diode elements to a respective unique subset of the second set address lines.