Patent ID: 8726089
Filing Date: 2014-05-13
Classification: G06F

Abstract:
1. A system error analysis method suitable for a system error analysis device, wherein the system error analysis device is capable of receiving an interrupting signal and including a top unit, the system error analysis method comprises: storing N pieces of input data, M pieces of output data and P pieces of bus data transmitted by the top unit, wherein, N, M and P are positive integers; determining whether the positive integer N, M or P is larger than or equal to 2 when the interrupting signal is received; outputting an Nth piece of input data and an (N−1)th piece of input data, if N is larger than or equal to 2, wherein the Nth piece of input data is stored when the interrupting signal is received; outputting an Mth piece of output data and an (M−1)th piece of output data, if M is larger than or equal to 2, wherein the Mth piece of output data is stored when the interrupting signal is received; and outputting a Pth piece of bus data and a (P−1)th piece of bus data, if P is larger than or equal to 2, wherein the Pth piece of bus data is stored when the interrupting signal is received.