Patent ID: 8111596
Filing Date: 2012-02-07
Classification: G11B

Abstract:
1. A phase error detection apparatus comprising: a signal generation circuit for sampling two signal sequences whose phases mutually change, thereby generating digital signals; a zerocross point detection circuit for detecting a zerocross point where the digital signal of each sequence crosses a center level of the digital signal, from an output signal of the signal generation circuit; a phase difference detection circuit for performing phase comparison between the two sequences of digital signals by using a distance between the zerocross points of the two digital signals, and outputting a phase comparison result obtained between the respective zerocross points, as a pulse corresponding to one sampling clock, and further, outputting a phase comparison completion signal indicating that the phase comparison has completed; a reference interval generation circuit for outputting a reference signal for each predetermined interval; an effective phase difference detection circuit for outputting a control signal indicating whether a phase comparison completion signal from the phase difference detection circuit is detected or not within the interval of the reference signal from the reference interval generation circuit; an offset control circuit for outputting an offset correction amount when a phase comparison completion signal is detected, and outputting 0 when no phase comparison completion signal is detected, according to the control signal from the effective phase difference detection circuit; a low-pass filter for performing band limitation on a phase comparison result output signal from the phase difference detection circuit; an addition circuit for adding an output of the offset control circuit to an output of the low-pass filter to obtain a phase error signal; and an offset correction circuit for detecting an offset amount of the phase error signal from the output of the low-pass filter, adjusting the offset correction amount on the basis of the detected offset amount, and outputting the offset correction amount to the offset control circuit.