Patent ID: 6501317
Filing Date: 2002-12-31
Classification: H03H

Abstract:
A delay circuit for an oscillator comprising:a differential pair of transistors (102,103) connected in a common source configuration with gates of first and second transistors of the differential pair forming complementary inputs to the delay circuit, and drains of the first and second transistors of the differential pair forming complementary outputs of the delay circuit; a first load comprising third and fourth transistors (104,106) having source-drain paths connected in parallel to couple a first voltage supply (VDD) to the drain of the first transistor (102) of the differential pair; a second load comprising fifth and sixth transistors (105,107) having source-drain paths connected in parallel to couple the first voltage supply (VDD) to the drain of the second transistor (103) of the differential pair; and a bias circuit comprising: an amplifier (130) having a first input connected to a voltage reference, a second input and an output; a third load comprising seventh and eighth transistors (113,114) having source drain paths coupled between the first voltage supply (VDD) and the second input of the amplifier, wherein gates of the third, fifth and seventh transistors are coupled to the output of the amplifier.