Patent ID: 8946782
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A field effect transistor (FET) device, comprising: at least one active area formed in a wafer; gates over the active area, wherein the gates cover portions of the active area that serve as channel regions of the device and wherein portions of the active area that extend out from under the gates serve as source and drain regions of the device; a dielectric gap fill material in between the gates; one or more keyholes in the dielectric gap fill material, wherein the keyholes are defined by a gap in the dielectric gap fill material, and wherein the keyholes are present in between the gates and extend parallel to the gates through the dielectric gap fill material; a mask that i) is perpendicular to the gates and divides at least one of the gates and ii) blocks off one or more of the keyholes by filling at least a portion of one or more of the keyholes; one or more interconnect structures of the device formed in one or more of the keyholes; and contacts formed in the dielectric gap fill material, wherein the interconnect structures connect at least two of the contacts.