Patent ID: 6476668
Filing Date: 2002-11-05
Classification: H03F

Abstract:
A single-ended circuit, having an input node, an output node, a power supply rail and ground, comprising:(a) a first inductor coupled to the input node; (b) a first capacitor coupled between the first resistor and ground; (c) a blocking capacitor coupled in series to the first inductor; (d) a biasing circuit comprising: (i) a first transistor, having a base, emitter and collector, the collector of the first transistor coupled to the power supply rail; (ii) a first current source coupled between the emitter of the first transistor and ground; (iii) a reference current source coupled between the power supply rail and the base of first transistor; (iv) a second transistor, having a base, emitter and collector, the collector of the second transistor coupled to the reference current source, and the emitter of the second transistor coupled to ground; (v) a second capacitor coupled between the emitter of the first transistor and the base of the second transistor; (vi) a third transistor, having a base, emitter and collector, the collector coupled to the power supply rail, the base coupled to the collector of the first transistor; and (vii) a second resistor coupled between the base of the second transistor and the emitter of the third transistor; (e) a third resistor coupled between the second resistor and the blocking capacitor; (f) a fourth transistor, having a base, emitter and collector, the base coupled to the third, the collector coupled to the output node; (g) a second inductor coupled between the emitter of the fourth transistor and ground; and (h) a third resistor inductor coupled between the power supply rail and the output node.