Patent ID: 8293578
Filing Date: 2012-10-23
Classification: H01L

Abstract:
1. A method of manufacturing a multi-layer circuit arrangement, the method comprising: physically and electrically coupling first and second semiconductor dies with one another using a wafer-wafer bonding process to form a first electrical/physical interconnect between the first and second semiconductor dies; and physically and electrically coupling a third semiconductor die with the second semiconductor die to form a second electrical/physical interconnect between the second and third semiconductor dies; wherein each semiconductor die includes opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer, wherein each semiconductor die includes an array of conductive through vias extending through such semiconductor die, wherein physically and electrically coupling the first, second and third semiconductor dies together forms a multi-layer semiconductor stack, wherein each semiconductor die includes an array of contact pads disposed on at least one face of such semiconductor die and topographically aligned with the array of conductive through vias, wherein the first electrical/physical interconnect includes a first array of electrical conductors extending between topographically aligned contact pads on the first and second semiconductor dies, wherein the second electrical/physical interconnect includes a second array of electrical conductors extending between topographically aligned contact pads on the second and third semiconductor dies, wherein the array of contact pads disposed on each semiconductor die is a regular array, wherein a first subset of the contact pads in the array of contact pads on each semiconductor die are configured as data-carrying contact pads that are electrically coupled to data-carrying through vias, wherein a second subset of the contact pads in the array of contact pads on each semiconductor die are configured as power-carrying contact pads that are electrically coupled to power-carrying through vias, and wherein a third subset of the contact pads are dummy contact pads that are not topographically aligned with any of the conductive through vias.