Patent ID: 8219952
Filing Date: 2012-07-10
Classification: G06F

Abstract:
1. A method to analyze a design of an integrated circuit (IC) device, said design comprising a layout and parasitics for the IC device, the method comprising: at a computer, using a static timing analysis tool to generate a plurality of timing windows of a corresponding plurality of nets in said design based on the layout and said parasitics of the IC device, wherein said plurality of nets are included in each die of a plurality of dies in a wafer; identifying a plurality of pairs of timing windows from said plurality of timing windows each pair of timing windows comprising a victim timing window representing a variation in arrival time of a victim signal at an input or output of a victim net in said plurality of nets and an aggressor timing window for arrival representing a variation in arrival time of an aggressor signal at an input or output of an aggressor net in said plurality of nets; moving said victim timing window by an amount for said die based on a position of one or more edges of said victim timing window for said die relative to corresponding victim timing windows of other dies of said plurality of dies; forming for said victim net, a combined victim window representing a plurality of arrival times of said victim signal in said die and said other dies of said plurality of dies, based at least partially on a moved victim timing window; forming for said aggressor net, a combined aggressor window representing a plurality of arrival times of said aggressor signal in said die and said other dies of said plurality of dies, based at least partially on a moved aggressor timing window; determining overlap between said combined victim window and said combined aggressor window; and determining a delay of the victim signal when an overlap is determined to occur between said combined victim window and said combined aggressor window.