Patent ID: 8578196
Filing Date: 2013-11-05
Classification: G06F,Y02D

Abstract:
1. In a data processor, a method for reducing power consumption when processing mathematical operations by utilizing processor hardware devices that receive one or more operands from an execution unit, the method comprising: detecting when at least one operand of multiple operands is one of a zero operand and an unordered operand before the operand is forwarded to an execution component for completing a mathematical operation; in response to at least one operand being a zero operand or being unordered, setting a first flag that triggers a gating of a clock signal to reduce an active floating point unit (FPU) data path by disabling select processing devices/stages of one or more processing stages/devices within the FPU data path and to enable a bypassing of the completion of the mathematical operation, wherein an operand is unordered if the operand is one of a non-number or infinity, wherein the first flag is one of an FE flag or an FU flag and is set in a processor, wherein the FE flag is set responsive to detecting that one of the operands is a zero, and wherein the FU flag is set responsive to one of the operands being unordered; in response to the first flag being set, gating the clock signal to disable only select processing stages/devices of the one or more processing stages/devices within the FPU data path, wherein the select processing stages/devices are not needed to calculate a result of the mathematical operation, and wherein processing stages/devices that are needed for calculating the result are left active; and reusing the FE/FU flags for gating of the clock signal in subsequent instructions.