Patent ID: 8381224
Filing Date: 2013-02-19
Classification: G06F

Abstract:
1. A device comprising: a multi-core hardware processor having a plurality of execution cores; an in-memory database comprising data stored within a plurality of memory partitions, wherein each of the memory partitions is associated with a different one of the execution cores; a data ingest engine that establishes a plurality of concurrent network connections to external devices to receive incoming transactions; and a parallelization engine that decomposes incoming transactions for the in-memory database into sub-transactions, deploys the sub-transactions to the execution cores associated with the respective memory partitions that store data for the sub-transactions, and concurrently executes the sub-transactions of the incoming transactions on the respective execution cores to which the sub-transactions are deployed, wherein the incoming transactions include a first transaction and a second transaction, wherein the first transaction and the second transaction include first data and second data, respectively, for insertion to the in-memory database, wherein the parallelization engine comprises a first compiler task and a second compiler task that execute concurrently to decompose, respectively, the first transaction into a first set of sub-transactions and the second transaction into a second set of sub-transactions; a first statement execution task that applies an assignment algorithm to the first data to identify a first one of the execution cores to execute one of the first set of sub-transactions; and a second statement execution task that applies the assignment algorithm to the second data to identify a second one of the execution cores to execute one of the second set of sub-transactions, wherein the one of the first set of sub-transactions and the one of the second set of sub-transactions execute concurrently on the first one of the execution cores and the second one of the execution cores, respectively.