Patent ID: 7170817
Filing Date: 2007-01-30
Classification: G11C

Abstract:
1. A method for controlling access of two synchronous busses with asynchronous clocks to a single port Random Access Memory (RAM), said method comprising the steps of: providing a synchronization system comprising the two synchronous busses each being controlled by one of the clocks, and a control flip-flop that is clocked by the clock of one of the two busses so that the one bus is in control of the control flip-flop, and the other of the two busses is not in control of the control flip-flop; providing a change signal to the control flip-flop for requesting a change of the clock of the RAM, so as to produce a control flip-flop output signal; supplying the control flip-flop output signal to an inverter circuit that yields a first signal, and to a synchronization circuit that synchronizes the control flip-flop output signal to the clock of the bus that is not in control of the control flip-flop, so as to produce a second signal; supplying the first signal to a first circuit to synchronize to the clock of the other bus yielding a third signal, and the second signal to a second circuit to synchronize to the clock of the other bus yielding a fourth signal; supplying the first signal and the fourth signal to a first combinatorial block that outputs a fifth signal, and the second signal and the third signal to a second combinatorial block that outputs a sixth signal; supplying the fifth signal to a first falling edge sampling flip-flop to yield a seventh signal, and the sixth signal to a second falling edge sampling flip-flop to yield a eighth signal; supplying the seventh signal and the clock of the bus in control of the control flip-flop to a first AND gate, the eighth signal and the clock of the other bus to a second AND gate, and the outputs of the first and second AND gates to an OR gate; and using the output signal of the OR gate as the clock signal of the RAM.