Patent ID: 8518824
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A method for patterning a self-aligned via in a dielectric, the method comprising the steps of: forming a metal hard mask, having a metal containing layer between a first and second oxide layer, on top of a dielectric; etching a first trench through the first oxide layer and the metal containing layer, but not through the second oxide layer; etching a second trench, intersecting at least a portion of the first trench, selective to the metal containing layer such that the second trench stops at the metal containing layer except where the metal containing layer has been removed for forming the first trench thereby extending the second trench to expose a first area of the dielectric at the intersection of the first and second trench; etching the exposed first area of the dielectric to create a via hole extending into the dielectric; exposing a second area of the dielectric by re-etching the first trench to extend through the depth of the metal hard mask, wherein the exposed second area of the dielectric includes the via hole; etching the exposed area of the dielectric corresponding to the first trench to create a wiring path in the dielectric, wherein the wiring path extends partially through a depth of the dielectric and wherein the wiring path intersects the via hole; and depositing a conductive material into the via hole and wiring path of the dielectric to form a metal layer.