Patent ID: 6570213
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A self-aligned split-gate flash memory cell, comprising:a semiconductor substrate of a first conductivity type; a cell region having an active region and two shallow-trench-isolation regions formed on said semiconductor substrate and being divided into three regions: a common-source region, a gate region, and a common-drain region, wherein said gate region is located between said common-source region and said common-drain region with an elongated control-gate being defined by a sidewall dielectric spacer formed on top of said elongated control-gate; a self-aligned split-gate structure being formed in said gate region with said elongated control-gate being formed on top of and said self-aligned split-gate structure being divided into two subregions: a floating-gate region and a select-gate region, wherein said floating-gate region comprising an integrated floating-gate layer with a floating-gate transistor being formed on a thin tunneling-dielectric layer is located near said common-source region and said select-gate region comprising a select-gate transistor being formed on a gate-dielectric layer is located near said common-drain region; a common-source diffusion region of a second conductivity type being formed in said semiconductor substrate by implanting doping impurities in a self-aligned manner into said active region is said common-source region; and a common-drain diffusion region of a second conductivity type being formed in said semiconductor substrate by implanting doping impurities in a self-aligned manner into said active region is said common-drain region.