Patent ID: 7035962
Filing Date: 2006-04-25
Classification: G06F

Abstract:
1. A memory system comprising: a memory controller; a separate unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus; a separate bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation; a plurality of N memory modules, wherein each of the memory modules includes: a socket adapted to receive the memory module and to couple the memory module to the unidirectional command and address bus and to the bidirectional data bus; and wherein a first load on the command and address bus is equal to N devices and a second load on the data bus is equal to N devices where the total number of memory devices is N*M.