Patent ID: 6196849
Filing Date: 2001-03-06
Classification: H05K

Abstract:
A method for aligning an integrated circuit chip in a socket having a base, a first wall disposed along one of the edges of the base, a second wall disposed along one of the edges of the base and being abutted to and perpendicular to the first wall, a third wall disposed along one of the edges of the base and being abutted to and perpendicular to said second wall, and a fourth wall disposed along one of the edges of the base and being abutted to and perpendicular to said first wall and said third wall, comprising the steps of:establishing a first point of alignment on said first wall;establishing second and third points of alignment on said second wall;applying a plurality of forces to the integrated circuit chip in a direction from the third wall toward the first wall to maintain contact between the integrated circuit chip and the first point of alignment;applying a plurality of forces to the integrated circuit chip in a direction from the fourth wall toward the second wall to maintain contact between the integrated circuit chip and the second and third points of alignment.