Patent ID: 7517740
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method of fabricating a polysilicon thin film transistor, the method comprising: depositing an amorphous silicon layer on a substrate; forming a gate dielectric material on the amorphous silicon layer; forming a gate metal material on the gate dielectric material; forming a gate metal electrode by partially etching the gate metal material, wherein the amorphous silicon layer is defined to have a channel region, a source region and a drain region, the channel region being under the gate metal electrode, and the source region and the drain region being on both sides of the channel region, and wherein the gate metal material partially remains on the source region and the drain region as a remained gate metal material layer; doping the source and drain regions of the amorphous silicon layer by applying an ion implantation process; crystallizing a channel region of the amorphous silicon layer and activating the source and drain regions of the amorphous silicon layer by irradiating the gate, source and drain regions with a laser beam simultaneously; removing the gate metal material remaining on the source and drain regions; and forming a source electrode and a drain electrode by forming an interlayer dielectric layer with a contact hole, wherein the gate metal material has a deposited thickness of 1,000 Å through 5,000 Å and the remained gate metal material layer thickness of 10 Å through 1,000 Å.