Patent ID: 9093472
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a P-type well having a first sun P-type well and a plurality of second sub P-type wells in a substrate, wherein the first sub P-type well is continuously extended in a first direction and wherein each pair of the plurality of second sub P-type wells is extended from both sides of the first sub P-type well in a second direction crossing the first direction and is arranged at a regular interval in the first direction; forming a P-type body region having a first region and a second region in the substrate, wherein the P-type body region is extended in the first direction, wherein the first rat region of the P-type body region is formed on the first sub P-type well, wherein the second region of the P-type body region is surrounded by the each pair of the plurality of the second sub P-type wells, and wherein the P-type body region includes a source region and a body contact region; and forming a gate line on the substrate, wherein the gate line is extended in the first direction.