Patent ID: 6694385
Filing Date: 2004-02-17
Classification: G06F

Abstract:
A data processing apparatus comprising:a configuration bus having a write data bus, an address bus, and a module select bus having a line for each of said plurality of configurable peripheral device interfaces; a plurality of configurable peripheral device interfaces, each configurable peripheral device having at least one memory mapped register storing data controlling a configuration of said configurable peripheral device and operable to connect to a corresponding peripheral device, said configurable peripheral device interfaces connected to said configuration bus in a chain, each of said plurality of configurable peripheral device interfaces being responsive to a signal in a first digital state on a corresponding line of said module select bus to read data on said data bus of said configuration bus and store said read data in a memory mapped register corresponding to an address on said address bus of said configuration bus as to a signal in a second digital state opposite to said first digital state on said corresponding line of said module select bus to ignore signals on said data bus and address bus of said configuration bus; and a configuration controller connected to said configuration bus, said configuration controller operable to write configuration data to said at least memory mapped register of each of said plurality of configurable peripheral device interfaces via write data bus of said configuration bus.