Patent ID: 7427546
Filing Date: 2008-09-23
Classification: H01L

Abstract:
1. A method for fabricating a transistor comprising: forming a first insulation layer and a second insulation layer over a semiconductor substrate; selectively etching the first and second insulation layers and semiconductor substrate to form a recess; depositing a gate insulation layer and a gate conductor layer; planarizing the gate insulation layer and the gate conductor layer to form a gate structure filling the recess; removing the second insulation layer; forming a spacer over a side wall of the gate; implanting ions into the semiconductor substrate near the spacer to form source and drain regions; wet etching the first insulation layer and the gate insulation layer to expose an upper side wall of the gate and upper portions of the source and drain regions; and forming a salicide layer on the exposed surface of the gate and over the source and drain regions.