Patent ID: 6989810
Filing Date: 2006-01-24
Classification: G09G

Abstract:
1. A data latch circuit comprising: a memory circuit which has first and second inverters having one output terminal connected to the other input terminal and the other output terminal connected to one input terminal and stores therein digital data which is a latch target; first and second switch devices configured to switch and controlling whether a power supply voltage is supplied to said first and second inverters; a third switch device configured to switch and controlling whether said digital data is inputted to said memory circuit; and an output circuit configured to read digital data stored in said memory circuit, said first and second switch devices being turned on in a period other than a cyclic sampling period to supply a power supply voltage to said first and second inverters, said third switch device being turned on in said sampling period to input digital data to said memory circuit, said output circuit having a passing electric current prevention unit which prevents a passing electric current to flow from a power supply terminal of said output terminal to a group terminal in said sampling period.