Patent ID: 6316304
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing a semiconductor substrate;providing a first and second gate structure on said semiconductor substrate;implanting ions into said substrate not covered by said first and second gate structures to form source/drain extensions;forming an insulating layer overlying said first and second gate structures and said substrate not covered by said first and second gate structures;depositing an etch stop layer overlying said insulating layer;depositing a first oxide layer overlying said etch stop layer;patterning and etching away said first oxide layer overlying said first gate structure;depositing a second oxide layer overlying said first oxide layer and overlying said etch stop layer where said first oxide layer has been etched away over said first gate structure;anisotropically etching a portion of said first oxide layer and said second oxide layer to said etch stop layer thereby forming spacers along the sidewalls of said first and second device structures wherein said spacers on sidewalls of said second device structure have a width greater than the width of said spacers on sidewalls of said first device structure; andetching away said etch stop layer not covered by said spacers to said insulating layer thereby completing fabrication of said integrated circuit device.