Patent ID: 8928398
Filing Date: 2015-01-06
Classification: H03M

Abstract:
1. A differential analog signal processing stage comprising: a plurality of resistors connected in series, a first resistor in the series being connected to a positive path node, a last resistor in the series being connected to a negative path node; a plurality of resistor switches that are connected to the plurality of resistors such that each resistor switch is connected to two adjacent resistors in the series; a plurality of positive capacitor circuits that are each connected to the positive path node and ground, each positive capacitor circuit having a positive capacitor and a positive switch connected to the positive capacitor; a plurality of negative capacitor circuits that are each connected to the negative path node and ground, each negative capacitor circuit having a negative capacitor and a negative switch connected to the negative capacitor; and a control circuit connected to each resistor switch, each positive switch, and each negative switch, the control circuit outputting signals that individually open and close each resistor switch, each positive switch, and each negative switch, wherein each resistor switch is connected to receive a bias voltage.