Patent ID: 6208163
Filing Date: 2001-03-27
Classification: H03K

Abstract:
A programmable logic device including a plurality of configurable logic blocks and interconnect resources for transmitting signals to the configurable logic blocks, each configurable logic block including a logic/memory circuit comprising:a plurality of input terminals including a first input terminal for receiving an input signal from the interconnect resources;an input control circuit connected to the first input terminal;an array including:a first programmable element including a first latch for storing a first bit value,a first bit line connected to the first latch via a first pass transistor, said first bit line also being connected to the input control circuit;a second programmable element including a second latch for storing a second bit value, anda second bit line connected to the second latch via a second pass transistor, said second bit line also being connected to the input control circuit; anda product term circuit connected to the first and second bit lines and to the first and second latches for generating a product term in response to the input signal transmitted onto the first and second bit lines via the input control circuit, and in response to the first and second bit values stored in the first and second latches.