Patent ID: 8719481
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A circuit arrangement comprising a plurality of functional units, each unit comprising a plurality of data processing modules and a local controller, said plurality of data processing modules running a common system clock and being connected by a streaming data bus running a handshake-type streaming data transfer protocol which comprises three control signals including first and second handshake-type control signals and a third control signal which marks a beginning and an end of a frame comprised of a logical group of data elements within the data stream, wherein at least one of said functional units further comprises a profiling module which receives at least one set of said first, second, and third control signals tapped at a predefined link of said streaming data bus during real time operation, for determining link performance and communication patterns of said streaming data stream for profiling and debugging purposes; wherein said profiling module comprises at least one link selection means, a respective profiler unit connected to each of said at least one link selection means and adapted to receive the system clock signal and the set of control signals tapped from the selected link to extract link performance parameters therefrom, and a software accessible set of control registers for defining a link to be assessed, a link performance acquisition mode, and a time period of the control signals to be assessed, and for storing link performance output parameters from said profiler units; and wherein said profiler unit comprises a first counter for determining a number of frames that passed since a last clear operation, a second counter for determining a duration of the sampled frame, a third counter for determining a number of data beats of the sampled frame, and a counter control logic for controlling said first, second, and third counters for a selected frame to be sampled.