Patent ID: 9019765
Filing Date: 2015-04-28
Classification: G11C

Abstract:
1. A device comprising: a non-volatile memory array in which a program operation including a plurality of phases is performed, the non-volatile memory array including, first and second circuit nodes; a first selection circuit selecting whether to make a first connection path between the first bit line and the first circuit node, and selecting whether to make a second connection path between the first bit line and the second circuit node; a power supplying circuit coupled to the first circuit node and supplying a power supply voltage to the first circuit node, the power supply voltage being, when the first connection path is selected to be made by the first selection circuit, supplied to the first bit line; and a first voltage supplying circuit coupled to the second node and supplying a first voltage to the second circuit node, the first voltage being, when the second connection path is selected to be made by the first selection circuit, supplied to the first bit line, the first voltage and the power supply voltage being higher than a ground potential, and the first voltage being higher than the power supply voltage, wherein the first selection circuit selects the second connection path to supply the first voltage to the first bit line when or after the first selection circuit selects the first connection path to supply the power supply voltage to the first bit line, further wherein the supplying the power supply voltage to the first bit line and the supplying the first voltage to the first bit line are performed during a single phase of the program operation.