Patent ID: 8357977
Filing Date: 2013-01-22
Classification: G02F,H01L

Abstract:
1. A manufacturing method for semiconductor device having at least two thin film transistors and a diode on a same substrate, comprising the steps of: (a) forming island-shaped first and second semiconductor layers for formation of thin film transistors, and an island-shaped third semiconductor layer for formation of a diode; (b) forming a gate insulating film covering said first, second, and third semiconductor layers; (c) forming a mask layer having openings exposing portions of said gate insulating film that are located over portions of said first and second semiconductor layers, which portions are destined to become low-concentration impurity regions, and source and drain regions, respectively; (d) forming first conductivity type implantation regions in said first and second semiconductor layers, by implanting a first conductivity type impurity to said first and second semiconductor layers through the openings of said mask layer from above said gate insulating film; (e) forming on said gate insulating film a first gate electrode and a second gate electrode covering portions of said first conductivity type implantation region and regions that are destined to become channel regions of said first and second semiconductor layers, respectively; (f) forming another mask layer having openings exposing portions of said gate insulating film, which exposed portions are located over two end portions of said first conductivity type implantation region of said first semiconductor layer, the entire said second semiconductor layer, and over a portion of said third semiconductor layer; and (g) implanting said first conductivity type impurity into said first, second and third semiconductor layers, through the openings in said another mask from above said gate insulating film to form source and drain regions in said first semiconductor layer, source and drain regions in portions of said second semiconductor layer that are not covered by said second gate electrode, and a first conductivity type region in said third semiconductor layer, regions of said first conductivity type implantation regions where said source and drain regions are not formed becoming low-concentration impurity regions.