Patent ID: 9105738
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; an element isolation region defined in the semiconductor substrate and having an element isolation insulating film formed therein; an active region defined in the semiconductor substrate delineated by the element isolation region; a gate insulating film formed in the active region; a charge storage layer formed above the gate insulating film; a multilayered interelectrode insulating film formed in a first region above an upper surface portion of the element isolation insulating film, a second region along a sidewall portion of the charge storage layer, and a third region above an upper surface portion of the charge storage layer; the interelectrode insulating film including a stack of first silicon oxide film, a silicon nitride film, and a second silicon oxide film, and the silicon nitride film being thicker in the third region compared to the first region and compared to at least a portion of the second region; and a control electrode layer formed above the interelectrode insulating film, the charge storage layer having a sharp pointed structure, a cross section of an upper portion of the charge storage layer being semielliptical, wherein a portion of the silicon nitride film formed along an entire extent of the sharp pointed structure in the upper portion of the charge storage layer having the cross section being semielliptical is thicker than a portion of the silicon nitride film of the first region, and wherein a portion of the silicon nitride film in the second region and portion of the silicon nitride in the first region have substantially equal thicknesses.