Patent ID: 6420216
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method of forming an electrical fuse on a semiconductor structure comprising:providing a semiconductor substrate; depositing on said semiconductor substrate at least one electrically insulating layer having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; polishing said at least one electrically insulating layer such that there is formed over the portion thereof substantially free of electrical wiring a depression having a lower surface level than the adjacent portion thereof containing electrical wiring; optionally depositing over said at least one electrically insulating layer a further electrically insulating layer and polishing said further electrically insulating layer such that there is formed therein over the portion of said at least one electrically insulating layer substantially free of electrical wiring a depression having a lower surface level than an adjacent portion of the further electrically insulating layer; depositing a fuse insulator in the depression over the portion of said at least one electrically insulating layer substantially free of electrical wiring, the fuse insulator having a surface level which is substantially the same as the adjacent surface level of the electrically insulating layer; and forming a fuse over said fuse insulator.