Patent ID: 6144223
Filing Date: 2000-11-07
Classification: G06F,H03K

Abstract:
In a high speed SCSI input receiver, an input buffer circuit comprising:a switching circuit, connected to receive an input signal, the switching circuit including an input inverter defining an output at a common drain node thereof and first and second current sources connected to respectively source and sink current to and from the common drain node, the switching circuit configured to switch between low and high output states in response to the input signal traversing the input inverter's switching threshold voltage; anda threshold setting master circuit, including circuitry that substantially matches the operative circuitry of the switching circuit, the threshold setting master circuit connected to a reference voltage source and operative to define a control voltage for biasing the master circuit's current sources such that a switching threshold voltage of the master circuit's inverter element equals a precision voltage reference, wherein said control voltage further biases the current sources of the switching circuit so as to condition the switching circuit's inverter to exhibit a switching threshold voltage equal to the precision reference voltage.