Patent ID: 6125412
Filing Date: 2000-09-26
Classification: G06F

Abstract:
A system including a microprocessor having a memory, a means for executing a series of instructions, and a plurality of input/output ports each capable of connection to an input/output device, said series of instructions including input and output instructions, the system comprising:instruction means within said microprocessor for entering a super state mode of operation from a normal mode of operation;input/output control code stored in said memory beginning at a particular address, said input/output control code for controlling input and output between said microprocessor and said ports;a super state block register within said microprocessor for storing said particular address;instruction means within said microprocessor for generating an interrupt each time said microprocessor encounters an input or an output instruction in said series of instructions while in said super state mode, said interrupt causing said microprocessor to access said super state block register and execute said input/output control code.