Patent ID: 6304116
Filing Date: 2001-10-16
Classification: H03L

Abstract:
A delay locked loop circuit, comprising:a delay circuit that receives an input clock signal and produces an output clock signal and an intermediate clock signal that are delayed with respect to the input clock signal responsive to a delay control signal applied to the delay circuit, the intermediate clock signal being delayed less than the output clock signal;a delay control circuit, responsive to the input clock signal, the intermediate clock signal and the output clock signal, that applies the delay control signal to the delay circuit based on a comparison of a transition of the output clock signal, a transition of the input clock signal and a transition of the intermediate clock signal, the delay control circuit comprising a phase detector circuit that receives the input clock signal, the intermediate clock signal and the output clock signal and generates a first phase comparison signal when, following the transition of the intermediate clock signal, the transition of the output clock signal lags the transition of the input clock signal and a second phase comparison signal when the transition of the output clock signal leads the transition of the input clock signal; andwherein the phase detector circuit asserts the first phase comparison signal for a time extending substantially from the transition of the input clock signal to the transition of the output clock signal, and wherein the phase detector circuit asserts the second phase comparison signal for a time extending substantially from the transition of the output clock signal to the transition of the input clock signal.