Patent ID: 7932557
Filing Date: 2011-04-26
Classification: H01L

Abstract:
1. An integrated memory circuit device, comprising: an array of memory cells, wherein each of the memory cells includes a gate, a source junction and a drain junction; a first layer including discrete and self-aligned source and drain metal contacts made from at least one material selected from the group consisting of tungsten, aluminum, copper, titanium, tantalum, cobalt, molybdenum, tungsten silicide, titanium silicide, tantalum silicide, cobalt silicide, and molybdenum silicide, wherein each of the drain contacts electrically couple to each of the drain junctions in the array; a second layer disposed over the first layer, wherein the second layer includes self-aligned local area interconnects made from at least one material selected from the group consisting of tungsten, aluminum, copper, titanium, tantalum, cobalt, molybdenum, tungsten silicide, titanium silicide, tantalum silicide, cobalt silicide, and molybdenum silicide, wherein each of the local area interconnects electrically shunt all of the source junctions through the formed source contacts in each row in a block of the array such that the self-aligned local area interconnects are arranged to provide a common source region between each of the cells, within each of the rows in the block of the array, each self-aligned local area interconnect coupled to provide electrical coupling to the source junctions at two locations per row within the block of the memory array, one location at a first edge of the self-aligned local area interconnect block and the other location at a second edge of the self-aligned local area interconnect opposite the first edge, such that a resistance of a source rail for the source junctions in the row shunted by a self-aligned local area interconnect is essentially not dependant on the doping profile of the source junction; a third layer disposed over the second layer, wherein the third layer includes discrete drain connections to electrically connect the exposed drain extensions in the second layer; and a first level metallization over the third layer to electrically connect all of the drain contacts in the array; wherein the array includes doped oxide layers made from materials selected from the group consisting of BPSG, BSG, and PSG in the range of about 5000 to 18000 Angstroms.