Patent ID: 6233297
Filing Date: 2001-05-15
Classification: H03L,H04J

Abstract:
A PDH (Plesiochrounous Digital Hierarchy) low speed signal switching DPLL (Digital Phase-Locked Loop) system comprising a destuff circuit using a complete secondary DPLL (Digital Phase-Locked Loop) system comprising a primary loop and a secondary loop,said primary loop comprising:a frequency regulator for regulating a frequency so as to add or eliminate a pulse to or from a reference clock signal;an R frequency divider for outputting a low speed side clock signal while dividing said reference clock signal being subjected to frequency regulation by R;a first and a second N frequency divider for dividing a high speed side clock signal and the low speed side clock signal, respectively, by N;a multi-valued phase comparator for comparing phase outputs from the first and the second N frequency dividers to output a leading phase pulse which represents a number of phase leads accumulating to a phase difference of 180.degree. and a lagging phase pulse which represents a number of phase lags accumulating to a phase difference 180.degree.;a primary random walk filter for dividing a difference between pulse numbers of the leading phase and lagging phase output from the multi-valued phase comparator by N1; andan adder-subtractor circuit for providing said frequency regulator with a control pulse,said secondary loop comprising:a secondary random walk filter for dividing a pulse number output from said primary random walk filter by N2;a Q counter for storing an output of said secondary random walk filter;a rate multiplier for producing increment pulses or decrement pulses according to the low speed side clock signal and a central frequency of the system, and in accordance therewith selecting the increment pulses and decrement pulses, and outputting a selected pulse according to a value written in the Q counter; andsaid adder-subtractor for increasing or decreasing the pulse number output of the primary random walk filter in accordance with the output of the rate multiplier to provide the frequency regulator with the control pulse,wherein said destuff circuit includes a selector which implements changes of counter value of said primary random walk filter, counter value of said secondary random wall filter, counter stage numbers of said Q counter, and a change of rate length of said rate multiplier, pursuant to a signal which implements switching of DPLL parameters for respective PDH signals.