Patent ID: 6033999
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A method of forming an interlevel dielectric (ILD) layer using TEOS over an uneven surface having a straight contact hole comprising:a) providing a semiconductor structure over said substrate; said semiconductor structure has an uneven surface with high areas and low areas;b) forming a first insulating layer over said semiconductor structure;c) forming an interlevel dielectric layer composed of silicon oxide formed by a plasma enhanced chemical vapor deposition process using TetraEthylOrthoSilicate;d) planarizing said interlevel dielectric layer;e) performing a first rapid thermal anneal of said interlevel dielectric layer before a contact hole is formed in said interlevel dielectric layer wherein the first rapid thermal anneal prevents the interlevel dielectric layer from shifting and;f) forming a contact hole through said first insulating layer and said interlevel dielectric layer exposing a portion of said substrate.