Patent ID: 9070445
Filing Date: 2015-06-30
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array having a plurality of electrically rewritable memory transistors arranged therein; and a control unit configured to govern control that, in order to erase data of a selected memory transistor, repeats a voltage application operation and a step-down operation, the voltage application operation applying an erase voltage to a body of the selected memory transistor to change a threshold voltage at which the selected memory transistor is conductive, and the step-down operation, in the case where a threshold voltage of the selected memory transistor has not changed to a desired value, decreasing the erase voltage by an amount of a certain step-down value, the control unit being configured to control the step-down operation to monotonically decrease the step-down value so as to reduce the value of the erase voltage close to zero as the number of times of the voltage application operations increases.