Patent ID: 6553533
Filing Date: 2003-04-22
Classification: G06F,G11B,H03M

Abstract:
A machine-implementable method for detecting and correcting errors and erasures by a processor in systematic product linear block or cyclic error correction-coded (ECC) data arrays written into a memory, said processor accessing said memory, comprising the steps of:(a) iteratively syndrome processing the array data in row major order and (1) forming a first map classifying each row containing location indicia of random errors, their correction patterns, and pointers to rows containing erasure errors; and (2) effectuating row array random error corrections in place in memory according to the first map; and (b) iteratively syndrome processing the array data in column major order and (1) forming a second map containing location indicia and correction patterns for each pair adjacent position within each column containing erasure errors as indexed by a counterpart row pointer and location indicia within each column containing random errors and their correction patterns; and (2) effectuating column array erasure corrections and random error corrections in place in memory according to the second map.