Patent ID: 6292818
Filing Date: 2001-09-18
Classification: G06F

Abstract:
An apparatus for performing a sum-and-compare operation to determine whether an equation A+B>=K is true, where A is a first operand, B is a second operand, and K is a constant, the apparatus comprising:a propagate/generate logic block which receives the first operand, A, comprised of a plurality of bits, the second operand, B, comprised of a plurality of bits and a third operand, J, comprised of a plurality of bits, the first operand A corresponding to an addend, the second operand B corresponding to an augend, the third operand J corresponding to a twos compliment of the constant K, the propagate/generate logic block comprising logic configured to add the operand A to the operand B to obtain a first sum, the propagate/generate logic block comprising logic configured to add the first sum to the operand J to obtain a plurality of propagate signals and a plurality of generate signals, the propagate and generate signals being output from the propagate/generate logic block; anda carry-lookahead tree structure which receives the propagate and generate signals output from the propagate/generate logic block, the carry-lookahead tree structure comprising logic configured to operate on the propagate and generate signals to produce an output, Gout, wherein the output, Gout, can be analyzed to determine whether the equation A+B>=K is true.