Patent ID: 8959471
Filing Date: 2015-02-17
Classification: G06F,Y02P

Abstract:
1. An integrated circuit product comprising: a plurality of essentially irregularly placed active devices; one or more metal layers comprising metal lines; one or more dielectric layers insulating between said metal layers and said active devices; a first plurality of single via structures having a first predetermined hole size associated with a first via hole size in a design layout in one or more said dielectric layers; and a second plurality of single via structures comprising distortion corrected via holes having one or more hole sizes larger than said first predetermined hole size in at least one of said one or more said dielectric layers; wherein said second plurality of single via structures have via hole sizes essentially matching one or more predetermined sizes associated with one or more via hole sizes larger than said first hole size in said design layout; wherein said first plurality of single via structures and said second plurality of single via structures connect said metal lines and said active devices through said dielectric layers.