Patent ID: 8558312
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising: (a) a semiconductor chip having a first main surface and a second main surface; (b) an SOI region provided on the first main surface of the semiconductor chip; (c) a first N-channel MISFET region and a first P-channel MISFET region provided within the SOI region; (d) a first gate insulating film having a high-k insulating film and a first gate electrode film having a metal layer provided within the first N-channel MISFET region on the side of the first main surface of the semiconductor chip; (e) a second gate insulating film having a high-k insulating film and a second gate electrode film having a metal layer provided within the first P-channel MISFET region on the side of the first main surface of the semiconductor chip; (f) an N-type MISFET back gate impurity-doped semiconductor region provided in the first N-channel MISFET region inside the semiconductor chip; (g) a P-type MISFET back gate impurity-doped semiconductor region provided in the first P-channel MISFET region inside the semiconductor chip; (h) a bulk region provided on the first main surface of the semiconductor chip; (i) a second N-channel MISFET region and a second P-channel MISFET region provided within the bulk region; (j) a third gate insulating film and a third gate electrode film having a metal layer, the third gate insulating film and the third gate electrode film being provided within the second N-channel MISFET region on the side of the first main surface of the semiconductor chip; and (k) a fourth gate insulating film and a fourth gate electrode film having a metal layer, the fourth gate insulating film and the fourth gate electrode film being provided within the second P-channel MISFET region on the side of the first main surface of the semiconductor chip, wherein the N-type MISFET back gate impurity-doped semiconductor region or the P-type MISFET back gate impurity-doped semiconductor region is set to a potential other than a reference potential and a power source potential, and wherein the first gate insulating film and the third gate insulating film have a lanthanum-doped high-k insulating film, the second gate insulating film and the fourth gate insulating film have an aluminum-doped high-k insulating film, and the first gate electrode film, the second gate electrode film, the third gate electrode film, and the fourth gate electrode film have the same stacked structure.