Patent ID: 7183611
Filing Date: 2007-02-27
Classification: G11C,H01L,Y10S

Abstract:
1. An SRAM construction comprising: a p-type doped base containing, in ascending order, a first silicon-germanium-containing layer, and a first silicon-containing layer; the first silicon-germanium-containing layer having a relaxed crystalline lattice, and the first silicon-containing layer having a strained crystalline lattice; a transistor gate over the p-type doped base; an n-type doped structure over the transistor gate, the n-type doped structure containing, in ascending order, a second silicon-germanium-containing layer, and a second silicon-containing layer; n-type doped source/drain regions extending downwardly and into the p-type doped base on opposing sides of the transistor gate, with the n-type doped source/drain regions within the p-type doped base extending through the first silicon-containing layer, and into the first silicon-germanium-containing layer; p-type doped source/drain regions extending upwardly and into the n-type doped structure on opposing sides of the transistor gate, with the p-type doped source/drain regions within the n-type doped structure extending into the second silicon-germanium-containing layer; an n-type doped semiconductive material pillar extending from one of the n-type doped source/drain regions to the second silicon-germanium-containing layer; and wherein an inverter of the SRAM includes a PFET device comprising the p-type source/drain regions and the transistor gate, and includes an NFET device comprising the n-type source/drain regions and the transistor gate.