Patent ID: 8223112
Filing Date: 2012-07-17
Classification: G09G,G11C

Abstract:
1. A shift register configured by connecting unit circuits in multiple stages and operating based on two-phase clock signals, including first and second clock signals, the unit circuits being configured by transistors of the same conductivity type, wherein, each of the unit circuits includes wherein the unit circuit is configured such that when an active all-on control signal is provided to the unit circuit, the first output signal generation circuit stops outputting the first on-voltage as the first output signal at the same time as the all-on output signal generation circuit outputs the third on-voltage to the first output terminal as the first output signal and the second output signal generation circuit outputs the second off-voltage to the second output terminal as the second output signal, wherein the first output signal generation circuit includes wherein the second output signal generation circuit includes wherein the all-on output signal generation circuit includes a third output control transistor configured such that a fourth on-voltage is provided to a first conducting terminal of the all-on output signal generation circuit, and a second conducting terminal of the all-on output signal generation circuit is connected to the first output terminal, and wherein the unit circuit is configured such that when the active all-on control signal is provided to the unit circuit, the first and second output control transistors and the first output reset transistor are each brought into off-state, and the second output reset transistor and the third output control transistor are each brought into on-state.