Patent ID: 7795082
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A method of fabricating a CMOS thin film transistor, comprising: providing a substrate having first and second regions; forming an amorphous silicon layer on the substrate; forming a capping layer on the entire top surface of the amorphous silicon layer; depositing a metal catalyst on the capping layer; performing a first annealing process on the substrate to diffuse the metal catalyst through the capping layer to an interface of the amorphous silicon and the capping layer, and to crystallize the amorphous silicon layer into a polysilicon layer using the diffused metal catalyst; removing the capping layer; patterning the polysilicon layer to form first and second semiconductor layers in the first and second regions, respectively; forming a gate insulating layer and a gate electrode on the first and second semiconductor layers; implanting first impurities into the first and second semiconductor layers; implanting second impurities into the first or second semiconductor layer; and performing a second annealing process on the first and second semiconductor layers to remove the metal catalyst remaining in the first or second semiconductor layer having the implanted second impurities, wherein the first impurities are implanted at a dose of 6×10