Patent ID: 7139964
Filing Date: 2006-11-21
Classification: G11B,H03M,H04L

Abstract:
1. An encoder that performs both LDPC (Low Density Parity Check) encoding and modulation encoding on a binary sequence to generate an LDPC coded modulation signal, the encoder comprising: an LDPC encoder that performs LDPC coding on the binary sequence to generate an LDPC codeword that includes a plurality of LDPC coded bits; an S/P (Serial to Parallel) mapping functional block that divides the LDPC codeword into a plurality of paths such that each path of the plurality of paths outputs selected LDPC coded bits of the plurality of LDPC coded bits; wherein LDPC coded bits that are output from the plurality of paths are grouped together to form a plurality of LDPC coded symbols; a plurality of modulation encoders operating cooperatively such that each modulation encoder of the plurality of modulation encoders selectively receives certain LDPC coded symbols of the plurality of LDPC coded symbols according to a predetermined cycle; wherein each modulation encoder of the plurality of modulation encoders performs modulation encoding on the LDPC coded symbols of the plurality of LDPC coded symbols that it receives thereby generating corresponding pluralities of LDPC coded modulation symbols; and wherein LDPC coded modulation symbols are selected from the corresponding pluralities of LDPC coded modulation symbols to form the LDPC coded modulation signal that is an LDPC variable modulation signal.