Patent ID: 6169500
Filing Date: 2001-01-02
Classification: H03K,H03M

Abstract:
A frequency divider for use in a serial-parallel or parallel-serial converter for dividing a frequency of an incoming clock signal, said frequency divider including clock inputs coupled to the incoming clock signal, said frequency divider comprising: at least two circuits that perform the function of AND-gates with clocked memory circuits, each of said at least two circuits comprises: a clock input, a first AND-input, a second AND-input, and a plurality of outputs, at least one of which outputs a value of the logical AND-function of the first and second AND-inputs; wherein the first AND-inputs are connected to each other and to an inverted signal from a last one of the plurality of outputs, the second AND-inputs, except on a first of said at least two circuits, are connected together and to an output of another circuit that performs the function of an AND-gate, and a frequency divided clock signal is taken out from a second one of the plurality of outputs.