Patent ID: 7720165
Filing Date: 2010-05-18
Classification: H03M

Abstract:
1. A demapper, applied to a quadrature amplitude modulation trellis coded modulation (QAM-TCM) decoder, for generating in-phase more significant bits and quadrature-phase more significant bits of a QAM signal according to the QAM signal, at least an in-phase less significant bit of the QAM signal, and at least a quadrature-phase less significant bit of the QAM signal, the demapper comprising: an in-phase threshold value comparing and mapping unit, for generating at least an in-phase more-significant-bit buffered value according to a comparing result of a value of an in-phase component of the QAM signal and at least an in-phase threshold value of the QAM signal; a quadrature-phase threshold value comparing and mapping unit, for generating at least a quadrature-phase more-significant-bit buffered value according to a comparing result of a value of a quadrature-phase component of the QAM signal and at least a quadrature-phase threshold value of the QAM signal; a sign bit decider, for determining an in-phase sign and a quadrature-phase sign according to signs of the in-phase component and the quadrature-phase component; a multiplexer, coupled to the sign bit decider, the in-phase threshold value comparing and mapping unit and the quadrature-phase threshold value comparing and mapping unit, for generating a first more-significant-bit estimated value and a second more-significant-bit estimated value according to the in-phase sign, the quadrature-phase sign, the in-phase more-significant-bit buffered value and the quadrature-phase more-significant-bit buffered value; and an operating unit, coupled to the sign bit decider, for determining a third more-significant-bit estimated value and a fourth more-significant-bit estimated value according to the in-phase less significant bits, the quadrature-phase less significant bits, the in-phase sign and the quadrature-phase sign; wherein the first more-significant-bit estimated value, the second more-significant-bit estimated value, the third more-significant-bit estimated value, and the fourth more-significant-bit estimated value correspond to different bits of the in-phase more significant bits or the quadrature-phase more significant bits; when the in-phase sign equals the quadrature-phase sign, the multiplexer makes the first more-significant-bit estimated value equal to the in-phase more-significant-bit buffered value and makes the second more-significant-bit estimated value equal to the quadrature-phase more-significant-bit buffered value; and when the in-phase sign does not equal the quadrature-phase sign, the multiplexer makes the first more-significant-bit estimated value equal to the quadrature-phase more-significant-bit buffered value and makes the second more-significant-bit estimated value equal to the in-phase more-significant-bit buffered value.