Patent ID: 7745915
Filing Date: 2010-06-29
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a mounting board including a wiring layer, a main surface, and a back surface opposing to the main surface; a first semiconductor device including a first data input/output terminal, a first data strobe terminal, a first address input terminal and a first clock input terminal, and mounted over the main surface of the mounting board; a second semiconductor device including a second data input/output terminal, a second data strobe terminal, a second address input terminal and a second clock input terminal, and mounted over the main surface of the mounting board such that the second semiconductor device is arranged next to the first semiconductor device in a plane view; a third semiconductor device including a third data input/output terminal, a third data strobe terminal, a third address input terminal and a third clock input terminal, and mounted over the main surface of the mounting board such that the third semiconductor device is arranged next to the first and second semiconductor devices in a plane view; and a plurality of bump electrodes formed on the back surface of the mounting board; wherein the second semiconductor device is the same type of device as the first semiconductor device; wherein the first and second semiconductor devices are operated in sync with a clock signal; wherein the third semiconductor device accesses to each of the first and second semiconductor devices, and controls each of the first and second semiconductor devices; wherein the wiring layer includes a first wiring electrically connecting the third clock input terminal with each of the first and second clock input terminals; and wherein the first wiring is divided, at an area between the first and second semiconductor devices, into a first part connecting with the first clock input terminal and a second part connecting with the second clock input terminal.