Patent ID: 8963643
Filing Date: 2015-02-24
Classification: H03F,H03G

Abstract:
1. An RF amplifier circuit comprising: FET for receiving a RF input signal and generating an amplified RF output signal, the FET having a gate, drain, and source; control circuit, connected to the gate and drain of the FET, for controlling the current at the drain; dividing circuit comprising a means for biasing and variably compensating drift in the gate threshold voltage required to set the quiescent drain current, the dividing circuit being connected to the control circuit and controlling operation of the control circuit to maintain an essentially constant current at the drain in connection with a wake-up transition wherein the wake-up transition is the transistor operation or the overall circuit operation which occurs at initial start-up or a sleep or stand-by mode; detecting means, operably connected to the RF output signal, for detecting the power level of the RF output signal and supplying a DC voltage representative of the detected output power level; means for producing a variable reference voltage; and adjusting means, connected to the detecting means, the variable reference voltage and the dividing circuit, for automatically adjusting the drain current based at least in part on a comparison of the supplied DC voltage and the reference voltage by an amount necessary to maintain essentially constant output RF power.