Patent ID: 6720598
Filing Date: 2004-04-13
Classification: H01L

Abstract:
An integrated circuit comprising:a plurality of memory cells coupled in series to form a series group, the memory cells of a group are arranged in memory cell pairs, a memory cell pair of the group comprises; a first memory cell having a first transistor having a gate and first and second diffusion regions and a first capacitor having first and second plates separated by a first capacitor dielectric; a second memory cell having a second transistor having a gate and first and second diffusion regions and a second capacitor having first and second plates separated by second capacitor dielectric; the second diffusion regions of the first and second transistors of the memory cell pair is a common second diffusion region; the first and second capacitors are arranged in a stack in which the second plates of the capacitors is a common second plate; the first plate of the first capacitor is coupled to the first diffusion region of the first transistor; the first plate of the second capacitor is coupled to the first diffusion region of the second transistor; and the common second plate is coupled to the common second diffusion region.