Patent ID: 6221564
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method for forming a transistor having salicided source/drain regions on a semiconductor wafer, comprising:forming at least one gate on the semiconductor wafer, over a defined active area;doping the source/drain regions;coating the gate and the wafer with a uniform layer of photosensitive material suitable for use as a spacer alongside the gate;forming at least one photosensitive material spacer alongside the gate, wherein forming at least one photosensitive material includes exposing the photosensitive material for a controlled exposure time without any use of a photo mask, wherein exposing the photosensitive material for the controlled exposure time includes exposing the photosensitive material such that diffraction along an edge of the gate causes the photosensitive material along the edge of the gate to receive a lower exposure than the photosensitive material covering the gate or other areas of the wafer;forming silicide on the source/drain regions; anddepositing an insulator layer onto the semiconductor wafer.