Patent ID: 7457901
Filing Date: 2008-11-25
Classification: G06F

Abstract:
1. A microprocessor, comprising: processor logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, wherein said cache line memory write transaction comprises sending an entire cache line to memory, and wherein individual data elements within said cache line are enabled to be written to said memory with one of a plurality of granularities; and sparse write logic, coupled to said processor logic, which causes said processor logic to provide one of a plurality of sparse memory write transactions on said request signals and to provide a corresponding plurality of enable bits on said address signals; wherein each of said plurality of sparse memory write transactions corresponds with said one of a plurality of granularities, and wherein said corresponding plurality of enable bits determines which portions of said cache line are to be written to said memory, in accordance with said one of a plurality of granularities; and wherein said spare write logic causes said processor logic to replace an attribute value and byte enable bits on said address signals with said corresponding plurality of enable bits.