Patent ID: 7434124
Filing Date: 2008-10-07
Classification: G01R

Abstract:
1. A test system comprising: a plurality of interface circuits, wherein the test system is configured to communicate with a device under test (DUT) through the plurality of interface circuits; a first memory configured to store a plurality of test vectors, wherein each of the plurality of test vectors includes a plurality of bits; a second memory configured to store a plurality of selection codes; and a third memory configured to store a plurality of configuration sets, wherein each of the plurality of selection codes indicates an association between one of the plurality of test vectors and one of the plurality of configuration sets, wherein each configuration set is associated with one or more of the plurality of test vectors, wherein each configuration set includes configuration information for configuring each of the plurality of interface circuits for an associated test vector during communications with the DUT, and wherein each of the plurality of configuration sets is unique with respect to other ones of the plurality of configuration sets; wherein the number of configuration sets stored in the third memory is less than a number of test vectors stored in the first memory.