Patent ID: 6232164
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A method of fabricating a CMOS device having an anti-short channel effect (anti-SCE) region below a channel region of said CMOS device; comprising the steps of:a) forming isolation regions in said substrate defining active regions;b) forming a sacrificial oxide layer over said active areas;c) forming a masking layer over said substrate; said masking layer having a first opening defining a channel region in said substrate; said first opening has a width between 0.9 and 0.13 .mu.m;d) performing an Anti-SCE block implant through said first opening to create an anti-SCE region doped with a first conductivity type impurity; said anti-SCE region has a concentration profile: at a depth between 75 and 200 .ANG., a concentration between 0.5E15 to 1.5E15 atoms/cm.sup.3, at a depth between 400 and 600 .ANG., a concentration between 0.5E18 and 1.5E18 atoms/cm.sup.3, and at a depth between 900 and 2100 .ANG. a concentration between 0.5E15 and 1.5E15 atoms/cm.sup.3 ;e) removing said sacrificial oxide in first opening;f) forming a gate dielectric layer on said substrate in said first opening;g) forming a gate over said gate dielectric layer;h) planarizing said gate stopping on said masking layer;i) removing said masking layer and said sacrificial layer;j) performing a LDD Implant by implanting ions into said substrate in said active areas adjacent to said gate to form LDD regions doped with ions having a second conductivity type doping;k) forming a spacer on said sidewall of said gate;l) performing a S/D implant to form Source/Drain regions adjacent to said gate; said source/drain regions having a second conductivity type doping.