Patent ID: 6453450
Filing Date: 2002-09-17
Classification: G06F

Abstract:
A method for generating executable timing diagrams for a logic design for verifying logic designs comprising, providing a user acting as a designer with a simulation drive tool set including, a program in the form of a timing diagram editor enabling a graphical input for laying out and editing a timing diagram for a logic design to be simulated after a graphical input provided by said designer describing a logic design to be verified which the designer provides in a general timing diagram format, and including a support function library, and one or more executable test cases as timing diagram test cases for use in verification of the logic design, and having a timing diagram compiler function which generates an executable timing diagram for the graphical input provided by the designer, whereupon the designer enables by describing a logic design in a general timing diagram format the creation of one or more executable irritator programs for said logic designs by generating an executable timing diagram for selected logic designs using a timing diagram compiler function for said simulation drive tool set which generates an executable timing diagram for the graphical input provided by the designer and effectively compiling the behavior of signals of said selected logic design at a designer selected given time into an executable irritator program for logic verification simulation, and wherein the steps for generating executable timing diagrams include:(a) generating from a graphical representation of a timing diagram a header file containing an object definition for each executable timing diagram containing information about the signals to be used in said logic design and defining memory requirements for each timing diagram enabling a new instance of said object definition to be generated on activation of a timing diagram; (b) generating a source file for each of said executable timing diagrams containing a code representation of a timing diagram; and (c) generating an executable timing diagram by compiling the source file with a compiler; and (d) translating a selected timing diagram into a function to be simulated by using a programming loop created by a call twice per simulation cycle, once to drive signals, and once to check signals, and wherein the signals are set and/or checked in each cycle according to the values specified in the timing diagram editor and each cycle is represented by a code block.