Patent ID: 7518947
Filing Date: 2009-04-14
Classification: G11C

Abstract:
1. A memory comprising: a memory array having a plurality of memory cells; an address decoder for selecting a memory cell in response to an address; a data input/output circuit for transmitting data to or from the selected memory cell; a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an operation of the address decoder and the data input/output circuit during an access to the memory array; and a timing control circuit, coupled to the plurality of clock driver circuits, the timing control circuit having a first latch coupled to each of the plurality of clock driver circuits, the first latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a predetermined edge of a clock signal, the timing control circuit having a second latch coupled to the first latch, the second for restoring the first latch to an initial condition at the end of the memory access in response to a recovery signal.