Patent ID: 6687890
Filing Date: 2004-02-03
Classification: G01R,G06F

Abstract:
A method for layout design and timing adjustment of a logically designed integrated circuit comprising a first logic circuit, said first logic circuit comprising a plurality of flip-flops, each having a master latch circuit and a slave latch circuit, said method comprising:preparing cell data of first and second scan flip-flops, said second scan flip-flop comprising said master latch circuit, said slave latch circuit cascaded to said master latch circuit, and a latch circuit connected to said slave latch circuit, wherein said latch circuit operates in a reverse state of said slave latch circuit of said second scan flip-flop with respect to holding and capturing; producing a second logic circuit from said first logic circuit by replacing said plurality of flip-flops with respective said second scan flip-flops, and by connecting said plurality of second scan flip-flops in cascade to each other to construct a first scan circuit; designing a layout of said second logic circuit; obtaining a third logic circuit from said second logic circuit by replacing said second scan flip-flops with respective said first scan flip-flops to form a second scan circuit; and performing a static timing analysis on said third logic circuit to adjust timing.