Patent ID: 6426285
Filing Date: 2002-07-30
Classification: H01L

Abstract:
A method of forming a composite intermetal dielectric, (IMD), layer, featuring low tensile stress, on a semiconductor substrate, comprising the steps of:providing metal interconnect structures, overlying, and contacting, conductive regions, on, or in, said semiconductor substrate; depositing a first silicon oxide layer on said metal interconnect structures, wherein said first silicon oxide layer is comprised with a compressive stress between about âˆ’0.5 to 1.5E8 dynes/cm2; depositing a second silicon oxide layer on said first silicon oxide layer, wherein said second silicon oxide layer is comprised with a tensile stress between about 3.5 to 4.0E9 dynes/cm2; and depositing a third silicon oxide layer on said second silicon oxide layer, wherein said third silicon oxide layer is deposited to a thickness between about 17000 to 19000 Angstroms, using an initial power between about 700 to 1000 watts, and an initial frequency between about 13 to 14 MHZ, then using a final power between about 200 to 1000 watts, at a final frequency between about 100 to 400 kHz, resulting in a compressive stress between about âˆ’2.0 to âˆ’3.0E9 dynes/cm2 for said third silicon oxide layer.