Patent ID: 6750087
Filing Date: 2004-06-15
Classification: H01L,Y10S

Abstract:
A fabrication method of a thin film transistor array substrate, comprising:a step of forming a gate line on an insulating substrate; a step of forming a gate insulation film, a semiconductor layer, an ohmic layer, and a metal film on the insulating substrate on which the gate line is formed; a step of forming a pattern of a resist on the metal film by a photolithography process to cover at least a source line, a source electrode, a drain electrode, and a corresponding section to a semiconductor active layer of a thin film transistor which are to be formed on the ohmic layer in following steps, the resist being thinner on the corresponding section to the semiconductor active layer than on other sections; a step of etching the metal film to form the source line, the source electrode and the drain electrode; a step of making the resist thinner to remove the resist on the corresponding section to the semiconductor active layer; a step of removing the ohmic layer and the semiconductor layer of a section excluding the source line, the source electrode, the drain electrode, and the corresponding section to the semiconductor active layer by etching, after removing the resist on the corresponding section to the semiconductor active layer; a step of removing the metal film on the corresponding section to the semiconductor active layer by etching; and a step of removing the ohmic layer on the corresponding section to the semiconductor active layer by etching.