Patent ID: 9082825
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A manufacturing method for a semiconductor package comprising: a covering step of forming a covering insulating layer that covers a surface of a semiconductor element on which electrodes are formed, the semiconductor element including the electrodes on a principal plane thereof; a film-forming step of forming a resin film on a surface of the covering insulating layer on the electrodes side of the semiconductor element; a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching surfaces of the electrodes and a circuit groove having a desired shape and a desired depth, by applying laser processing or embossing to the covering insulating layer from an outer surface side of the resin film; a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on a surface of the circuit pattern portion and a surface of the resin film; a film-separating step of separating the resin film from the covering insulating layer; and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated.