Patent ID: 6154416
Filing Date: 2000-11-28
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array including a plurality of memory cells for storing data;a plurality of bit line pairs connected to the memory cells;a plurality of input and output line pairs;a plurality of switching means connected between the bit line pairs and the input and output line pairs; andan address decoder for decoding addresses received as input from the outside, simultaneously activating at least two switching means among the plurality of switching means, and electrically connecting corresponding bit line pairs and input and output line pairs, said address decoder comprising a predecoder for predecoding the address and a main decoder for decoding the predecoded address output from the predecoder and selecting the switching means from the plurality of switching means;wherein the predecoder comprises an even predecoder for receiving the less significant bits of the address and predecoding the less significant bits when the least significant bit is a logic 0, an odd predecoder for receiving the less significant bits of the address and predecoding the less significant bits when the least significant bit is a logic 1 and a main predecoder for predecoding the more significant bits of the address.