Patent ID: 8470645
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A method for forming a memory cell comprising a selection MOS transistor ( 11 ) and an antifuse MOS transistor, from standard elementary cells of a technological process, these cells corresponding respectively to a first type of MOS transistors (NMOSGO 1 , PMOSGO 1 ) of a first gate thickness (e 1 ), adapted to implement logic functions of integrated circuits, and to a second type of MOS transistors (NMOSGO 2 ) of a second gate thickness (e 2 ) greater than the first thickness, adapted to implement power functions of integrated circuits, this method comprising the steps of: forming the selection transistor according to the steps of manufacturing of an N-channel transistor of the second type (NMOSGO forming the antifuse transistor essentially according to the steps of manufacturing an N-channel transistor of the first type (NMOSGO