Patent ID: 6262938
Filing Date: 2001-07-17
Classification: G11C

Abstract:
A synchronous DRAM (SDRAM), operating in synchronization with a clock signal, the SDRAM comprising:a memory bank having a plurality of memory cells arranged in rows and columns;a column decoder for selecting a column of the memory bank;a column address input port for inputting a column address that selects the column of the memory bank;a first shift register for delaying the column address by a first number of delay clock cycles between the column address input port and the column decoder; anda delay counter for sensing the number of clock cycles RCL of the clock signal from the application of the row access command to the application of the column access command with respect to the same bank, and for providing a first delay clock control signal to the first shift register,wherein RL.sub.min is the minimum number of clock cycles of the clock signal required from the application of a row access command to the output of the data of the memory and CL.sub.min is the minimum number of clock cycles of the clock signal required from the application of a column access command to the output of the data of the memory cell, andwherein the first delay clock control signal has information on the difference between RCL and (RL.sub.min -CL.sub.min), and the first number of delay clock cycles is determined in response to the difference between RCL and (RL.sub.min -CL.sub.min).