Patent ID: 7835206
Filing Date: 2010-11-16
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of banks, each of said plurality of banks including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells disposed at intersections of the plurality of word lines and the plurality of bit lines; a plurality of defect relief circuits that relieve defective bits included in the plurality of memory cells, each assigned to an associated one of a plurality of main amplifiers that access the memory cells; a plurality of defective-address storing circuits that store defective addresses, each assigned to an associated one or more of the plurality of defect relief circuits; a plurality of comparing circuits, each assigned to an associated one or more of the plurality of defect relief circuits; and a switch that connects either the plurality of defect relief circuits or the plurality of main amplifiers to a data input/output terminal based on an output signal of the plurality of comparing circuits, wherein each one of the plurality of comparing circuits includes: an X address comparing block that compares a first X address to be accessed with a second X address stored in the defective-address storing circuits, said X address comparing block being assigned to an associated one of the plurality of banks; a Y address comparing block that compares a first Y address and a first bank address to be accessed with a second Y address and a second bank address stored in the defective-address storing circuits, the Y address comparing block being assigned to an associated more than one of the plurality of banks; a selection block that selects output signals of the X address comparing block based on the bank address stored in the defective-address storing circuits; and a logic block that compares an output signal of the selection block with an output signal of the Y address comparing block.