Patent ID: 6633296
Filing Date: 2003-10-14
Classification: G06F,G09G

Abstract:
An apparatus for providing data to a plurality of graphics processors, the apparatus comprising:a first device bus interface having a first port to interface to a system bus port of first graphics processor, and a second port; a first memory interface having a first port to interface to a memory port of the first graphics processor, and a second port; a second device bus interface having a first port to interface to a system bus port of a second graphics processor, and a second port; a second memory interface having a first port to interface to a memory port of the second graphics processor; a memory having a first access port; a memory controller having: a first port coupled to the second port of the first memory interface; a second port coupled to the first access port of the memory; and a third port coupled to the second port of the second memory interface.