Patent ID: 6754746
Filing Date: 2004-06-22
Classification: G06F,H04L,Y02D

Abstract:
A memory array comprising a plurality of independently addressable memory modules, wherein each memory module comprises:a plurality of memory cells arranged in rows and columns; a plurality of sense amplifier latches, wherein each column of said memory cells is coupled to a corresponding one of said sense amplifier latches; a plurality of decoder circuits coupled to said sense amplifier latches; a plurality of data amplifiers coupled to said decoder circuits, wherein said data amplifiers amplify data signals read from said memory cells; and a plurality of data lines coupling said data amplifiers to a set of bus lines, wherein the set of bus lines is commonly coupled to each of the plurality of memory modules, and wherein the set of bus lines transfers data signals to and from said memory modules, and wherein each of the memory modules further comprises a clock generating circuit configured to generate local control signals for the data amplifiers in response to a system clock signal.