Patent ID: 6027243
Filing Date: 2000-02-22
Classification: G06F

Abstract:
A parity check circuit, comprising:a plurality of successive check stages, each check stage having a plurality of Exclusive-OR circuits (XORs), a plurality of input ports for receiving bits of binary data and at least one output port for providing a check stage result, wherein each successive check stage of the plurality of successive check stages has a smaller number of XORs than a previous successive check stage;a plurality of data register circuits interleaved between the plurality of check stages, the data register circuits having a plurality of data input ports for receiving check stage results from a previous check stage, a plurality of output ports, and a clock input port for receiving a clock signal, wherein the data register circuits are responsive to the clock signal for providing the received check stage results to a next successive check stage; andan error check circuit having at least one input port for receiving the check stage results of a final check stage, and an output port for providing an error signal based on the final check stage result.