Patent ID: 6442098
Filing Date: 2002-08-27
Classification: G11C

Abstract:
A memory device, comprising:a plurality of input/outputs (I/Os); and a memory core having a plurality of memory cells coupled to the plurality of I/Os arranged to store data as at least a first data word and a second data word, wherein the memory core includes, a first bank segment arranged to store a first portion of the first data word, a second bank segment arranged to store a first portion of the second data word, wherein the first bank segment and the second bank segment are logically separate and distinct such that the first bank segment is activated only in response to a first bank select signal and wherein the second bank segment is activated only in response to a second bank select signal, a first segmented sense amp coupled to the first bank segment by way of a first bit line and to the second bank segment by way of a second bit line, wherein the first segmented sense amp responds to the first bank select signal by sensing the first portion of the data word using the first bit line and responds to a second bank select signal by sensing the first portion of the second data word using the second bit line such that a first bit line sensing delay associated with the first bit line is less than a second bit line sensing delay associated with the second bit line, and a first data line coupling the segmented sense amp to a nearest located one of the plurality of I/Os.