Patent ID: 7589377
Filing Date: 2009-09-15
Classification: H01L

Abstract:
1. A gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device, comprising: a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region; a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region, the doped poly-silicon layer having side walls and a floor surrounding a doped poly-silicon layer interior region; a first metal layer deposited adjacent to the doped poly-silicon layer and in the doped poly-silicon layer interior region on a side opposite from the dielectric layer, the first metal layer having side walls and a floor surrounding a first metal layer interior region; and an undoped poly-silicon layer deposited to fill the first metal layer interior region, wherein: