Patent ID: 6114746
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A vertical PNP transistor integrated in a semiconductor material wafer with a surface comprising:a P-type buried collector region,an N-type base region contacting said collector region, anda P-type emitter region,said base region comprising an N-type buried base region contiguous with said buried collector region and said emitter region, said buried base region having an area and a doping concentration,said PNP transistor having a pre-selected gain determined by pre-selecting the area of the buried base region, the doping concentration of the buried base region, or a combination thereof;wherein said base region comprises an N-type epitaxial portion and said buried base region is contiguous with said buried collector region and said epitaxial portion; andwherein said emitter region is a single region extending from the wafer surface to the N-type buried base region.