Patent ID: 8375247
Filing Date: 2013-02-12
Classification: G06F

Abstract:
1. A computer processor-error controller, the controller comprising: a monitoring circuit configured to monitor a processor that has an adjustable operating parameter and configured to detect an incidence of an operating-parameter-caused error corresponding to an execution of a second instruction by the processor, the processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction; and an error recovery circuit configured to determine the first instruction in response to the incidence of the detected operating-parameter-caused error, configured to designate the first instruction as an instruction separated by a plurality of instructions in instruction space from the second instruction by a determinable number of instructions after the execution of the second instruction is at least commenced by the processor, configured to restore an execution of the sequence of program instructions to the first instruction in response to the incidence of the detected operating-parameter-caused error, and configured to adjust the adjustable operating parameter of the processor in response to an error-tolerant performance criterion corresponding to the incidence of the detected operating-parameter-caused error, wherein the error-tolerant performance criterion comprises at least one of: