Patent ID: 6453401
Filing Date: 2002-09-17
Classification: G06F,G11C

Abstract:
A memory controller for tracking and checking timing constraints of a specific timing constraint type that are imposed by respective issued commands to access a memory, the memory controller comprising:a command issue unit to issue the issued commands; a constraint tracking and checking unit comprising: a constraint tracking subunit comprising multiple tracking circuits and an allocation circuit, the allocation circuit being configured to allocate a selected tracking circuit from among the multiple tracking circuits each time that a specific command of the issued commands is issued, the allocated tracking circuit being configured to track a timing constraint imposed by the specific command and to generate a timeout status signal for each tracked timing constraint; and a constraint checking subunit, coupled to receive the timeout status signals generated by the constraint tracking subunit, and configured to generate a blocking signal when at least one tracked timing constraint is pending against issuance of a generated command to access the memory; and a command generation unit to generate the generated command; wherein the command issue unit is configured to receive the blocking signal generated by the constraint checking subunit.