Patent ID: 9001562
Filing Date: 2015-04-07
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array; and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use, wherein each of the plurality of element blocks is composed of at least two sub-elements, the dummy block is composed of one or more sub-elements, and a number of the sub-element in the dummy block is fewer than a number of the sub-element in each of the plurality of element blocks, wherein each of the plurality of element blocks is a memory cell including a select transistor and a capacitor, wherein a contact wiring of the capacitor extends away from the end portion of the memory array, and wherein the at least one dummy block includes a dummy gate formed by extending a gate of the select transistor away from the end portion of the memory array.