Patent ID: 6934192
Filing Date: 2005-08-23
Classification: G11C

Abstract:
1. An electrically programmable and erasable memory comprising: at least one word line; a plurality of memory cells connected to said at least one word line and defining a plurality of words, a plurality of gate control transistors; each memory cell comprising a floating gate transistor and an access transistor, said floating gate transistor comprising a control terminal and first and second conduction terminals, and said access transistor comprising a control terminal and a first conduction terminal connected to the second conduction terminal of said floating gate transistor; each gate control transistor comprising a control terminal and a first conduction terminal connected to the control terminals of said floating gate transistors within a same word; first and second signal means for applying, during an erasing phase, a first signal to the control terminals and a second signal to the second conduction terminals of said floating gate transistors within a word to be erased, the first signal being applied through said gate control transistor corresponding to the word to be erased; and third signal means for applying, to the control terminals of the corresponding access transistors for accessing the memory cells of the word to be erased, a third signal having a voltage that is different from a voltage of the first signal and that is substantially the same as a voltage of the second signal.