Patent ID: 8964487
Filing Date: 2015-02-24
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of bit lines and a plurality of word lines intersecting each other and a plurality of nonvolatile memory cells at intersections of the bit lines and the word lines; and a page buffer for each bit line including a latch configured to store one of data to be written to a nonvolatile memory cell selected by each word line and data read from the nonvolatile memory cell, wherein before reading out data from a first nonvolatile memory cell connected to a selected word line, the page buffer is configured to store in a replica capacitor a voltage value of a word line adjacent to the selected word line when a second nonvolatile memory cell is turned on, the second nonvolatile memory cell connected to the adjacent word line and written later than the first nonvolatile memory cell, the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell connected to the selected word line according to the voltage value of the adjacent word line stored in the replica capacitor, and the replica capacitor includes a first capacitor and a second capacitor connected in parallel, the first capacitor having a capacitance value scaled from a capacitance between a floating gate of the first nonvolatile memory cell and a floating gate of the second nonvolatile memory cell, and the second capacitor having a capacitance value scaled from a capacitance between the floating gate of the first nonvolatile memory cell and ground.