Patent ID: 7586797
Filing Date: 2009-09-08
Classification: G11C

Abstract:
1. A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function, each pipelatch comprising: a data switching section receiving N bits data, determining the outputting order of the N bits data depending upon a starting column address applied by a read command and a data output mode, and outputting the N bits data; a data selection section receiving the N bits data outputted from the data switching section, selecting some of the N bits data in response to first and second data selection signals, and outputting the N bits data in response to a first output enable signal; and a shifter receiving a signal selected by the second selection signal of data outputted from the data selection section and outputted, and outputting a received signal with a delay of prescribed time in response to the first outputting enable signal.