Patent ID: 6111533
Filing Date: 2000-08-29
Classification: H03M

Abstract:
An analog-to-digital converter for converting slow-varying analog voltage signals into digital signals, comprising:first and second analog multiplexers; said first analog multiplexer receiving an input voltage Vin and a reference voltage Vref, and being controlled by a control signal Phase, said second analog multiplexer also receiving said signals Vin and Vref, and being controlled by the complement of said signal Phase, such that while said control signal Phase is high, the output signals of said first and second analog multiplexers are Vin and Vref respectively, while said control signal Phase is low; the output signals of said first and second analog multiplexers are Vref and Vin, respectively;first and second voltage controlled oscillators; said first and second voltage controlled oscillators receiving the output signals of said first and second analog multiplexers, respectively, and outputting said first and second pulse trains P1 and P2, respectively;first and second digital multiplexers; said first digital multiplexer receiving said pulse trains P1 and P2, and being controlled by said control signal Phase, said second digital multiplexer also receiving said pulse trains P1 and P2, and being controlled by the complement of said signal Phase, such that while said control signal Phase is high, the output signals of said first and second digital multiplexers are P1 and P2, respectively, while said control signal Phase is low; the output signals of said first and second digital multiplexers are P2 and P1, respectively;first and second counters; said first counter receiving the output signal of said first digital multiplexer, said second counter receiving the output signal of said second digital multiplexer; anda digital average circuit which receives the output signals of said first and second counters, and also receives said control signal Phase, said digital average circuit operating as described in the following: (1) said Phase being high, the count value of said first counter being stored whenever the count value of said second counter reaches a fixed number, then said two count values being reset to zero; (2) said Phase being low, the count value of said second counter being added to said stored count value of the first counter whenever the count value of said first counter reaches said fixed number, then the count values of said first and second counters being reset to zero after the sum is read, this readout count representing a digital signal corresponding to the input analog signal.