Patent ID: 6697406
Filing Date: 2004-02-24
Classification: H01S

Abstract:
A semiconductor device comprising:a contact layer, current blocking regions contiguous to and located at opposite ends of said contact layer; a metal electrode layer electrically coupled to said contact layer and to each of said current blocking regions and having a thickness w; and a plated layer on said metal electrode layer, said plated layer having a thickness D and first and second end faces spaced from respective boundaries between said contact layer and said current blocking regions, wherein, if the boundary between said contact layer and any of said current blocking regions is taken as an origin, a direction from the origin toward any of said current blocking regions is a negative direction, and a direction from the origin toward said contact layer is a positive direction, then the distance d between the origin and each of the end faces of said plated layer satisfies (d/w)[1âˆ’w/(w+D)]<20.