Patent ID: 6506633
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A method of a multi-chip module (MCM) package, comprising:providing a substrate, the substrate having an insulating core and a conductive layer, wherein the conductive layer covers a bottom surface of the insulating core; forming a first opening in the substrate to penetrate through the insulating core and the conductive layer; adhering an adhesive tape to cover a surface of the conductive layer, wherein the first opening exposes a portion of a top surface of the adhesive tape; adhering a first chip onto the exposed top surface of the adhesive tape, wherein the first chip has an active surface and a back surface, and a plurality of bonding pads are formed on the active surface of the first chip, the back surface of the first chip is adhered onto the adhesive tape such that the first chip is located firmly on the adhesive tape; forming a patterned dielectric layer to fill into the first opening in order to cover a portion of the exposed top surface of the adhesive tape, the active surface of the first chip, the bonding pads of the chip and the insulating core, a plurality of second openings and third openings formed in the patterned dielectric layer, wherein the second openings expose the bonding pads of the first chip and the third openings penetrate through the patterned dielectric layer, the insulating core and the conductive layer; electroplating a metal layer on sidewalls of the second openings and the third openings, and to cover the patterned dielectric layer; after the electroplating process, removing the adhesive tape to expose the conductive layer, the back surface of the first chip and a portion of the patterned dielectric layer; patterning the metal layer and the conductive layer to form a patterned metal and a patterned conductive layer are formed; forming a patterned solder mask layer to cover surfaces of the patterned metal layer and the patterned conductive layer, wherein a plurality of fourth openings and fifth openings are formed on the patterned solder mask layer to expose respectively a portion of the patterned metal layer and a portion of the patterned conductive layer; performing a solder ball process to form a plurality of solder balls on the fifth openings, wherein a reflow process is carried out to electrically connect the solder balls to the patterned conductive layer; and performing a die adhering process to electrically connect at least a second chip to the patterned metal layer via the fourth openings.