Patent ID: 9159447
Filing Date: 2015-10-13
Classification: G09G,G11C

Abstract:
1. A shift register unit comprising a sampling part, an output part and a reset part, wherein the sampling part includes a first switching transistor and a second switching transistor, the output part includes a fifth switching transistor, a sixth switching transistor, a first capacitor and a second capacitor, and the reset part includes a third switching transistor and a fourth switching transistor; a source of the first switching transistor is connected to an input terminal of the shift register unit and is configured to receive an input signal from the input terminal, and the gate of the first switching transistor is configured to receive a first clock signal; a gate and a source of the second switching transistor are configured to receive a second clock signal whose phase is inverted to that of the first clock signal; a gate and a source of the third switching transistor are configured to receive the first clock signal; a gate of the fourth switching transistor is configured to receive the second clock signal, and a source of the fourth switching transistor is configured to receive a power supply input signal; a source of the fifth switching transistor is configured to receive the second clock signal, a gate of the fifth switching transistor is connected to a drain of the first switching transistor and a drain of the second switching transistor, and a drain of the fifth switching transistor is connected to the output terminal of the shift register unit; a gate of the sixth switching transistor is connected to drains of the third switching transistor and the fourth switching transistor, a source of the sixth switching transistor is configured to receive the power supply input signal, and a drain of the sixth switching transistor is connected to the output terminal of the shift register unit; one terminal of the first capacitor is connected to the gate of the fifth switching transistor, and the other terminal of the first capacitor is connected to the output terminal of the shift register unit; and one terminal of the second capacitor is connected to the gate of the sixth switching transistor, and the other terminal of the second capacitor is configured to receive the power supply input signal.