Patent ID: 8132086
Filing Date: 2012-03-06
Classification: G06F,H03M

Abstract:
1. A semiconductor memory device comprising: a memory cell array that stores bits of normal data and parity data therein; an error correction code (ECC) engine that calculates the parity data using the normal data; a mode selection unit that selects one of a masking mode and a normal mode in response to a mode selection signal; a first column selection line for updating a first section of the normal data; and a second column selection line for reading a second section of the normal data, wherein the ECC engine calculates the parity data using the normal data that includes the first section that is to be updated and the second section that is to be saved by a masking operation during the masking mode in which the masking operation is performed, wherein the ECC engine reads the second section when the mode selection signal is enabled to select the masking mode, wherein the mode selection signal is enabled before a masking signal is enabled, thereby indicating that the masking mode is activated, and wherein the second column selection line is enabled before the first column selection line is enabled when the mode selection signal is enabled.