Patent ID: 6735685
Filing Date: 2004-05-11
Classification: G06F

Abstract:
A superscalar microprocessor for executing instructions obtained from an instruction store, said microprocessor comprising:a fetch circuit to fetch a plurality of instructions from said instruction store, the plurality of instructions being in program order; a first in first out (FIFO) buffer to buffer said plurality of instructions from said fetch circuit; a dispatch circuit to concurrently decode and concurrently dispatch more than one of said plurality of instructions buffered by said FIFO buffer; and an execution unit comprising: a load store unit adapted to make load requests out-of order and store requests in-order, a plurality of functional units, each of said plurality of functional units executing one of said plurality of instructions dispatched by said dispatch circuit out of the program order, and a register file comprising temporary registers for temporarily storing out-of-order execution results from said plurality of functional units and a register array for storing results from said temporary registers; and a plurality of data routing paths, and wherein said register file communicates with said plurality of functional units via said plurality of data routing paths for concurrently providing data to more than one of said plurality of functional units and thereby enabling concurrent execution of more than one of said plurality instructions by said plurality of functional units.