Patent ID: 8151152
Filing Date: 2012-04-03
Classification: H03K

Abstract:
1. A latch circuit, comprising: a first latch including a data input terminal, a clock input terminal, a scan data input terminal, and a first scan clock input terminal, the first latch storing data provided from the data input terminal when a clock is provided from the clock input terminal, and storing scan data provided from the scan data input terminal when a first scan clock is provided from the first scan clock input terminal; a logical circuit including a second scan clock input terminal and an operation mode input terminal, the logical circuit performing a logical operation for a second scan clock provided from the second scan clock input terminal and for an operational mode signal provided from the operation mode input terminal, and generating an update clock; and a second latch including an update input terminal connected to an output terminal of the first latch, and an update clock input terminal connected to an output terminal of the logical circuit, the second latch holding the data or the scan data provided from the update input terminal when the update clock is provided from the update clock input terminal.