Patent ID: 8105892
Filing Date: 2012-01-31
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region; forming a thin gate oxide pFET within said thin gate oxide pFET device region and a thick gate oxide pFET within said thick gate oxide pFET device region, wherein said thin gate oxide pFET includes a layer of SiGe on an upper surface of said thin gate oxide gate pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer, and said thick gate oxide pFET includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.