Patent ID: 6677210
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A method of forming an integrated circuit comprising at least one high voltage transistor in a semiconductor, the method comprising:forming a gate on the semiconductor, wherein the gate lies entirely within a plane that is parallel to a surface of the semiconductor; forming a source region in the semiconductor; forming a drain region in the semiconductor by diffusing a first concentration of dopant into the semiconductor; forming a first doped well by diffusing a second concentration of dopant into the semiconductor, wherein a first portion of the drain region overlaps the first doped well to form a first drain extension region, and the second concentration of dopant reduces majority carriers in the first drain extension; and forming a second doped well by diffusing a third concentration of dopant into the semiconductor, wherein a second portion of the drain region overlaps the second doped well to form a second drain extension region, and the third concentration of dopant reduces majority carriers in the second drain extension less than the second concentration of dopant reduces majority carriers in the first drain extension, wherein the drain region has a graded concentration of majority charge carriers that laterally increases across the first portion, the second portion, and a third portion of the drain region moving farther away from the gate.