Patent ID: 6032225
Filing Date: 2000-02-29
Classification: G06F

Abstract:
A microprocessor-based data processing system, comprising:a microprocessor, for executing data processing instructions, and connected to a bus with which the microprocessor communicates data, control and address signals, said control signals including an I/O control signal for indicating an input or output operation, a memory access control signal for indicating a memory access, and a burst request signal for indicating a request to access a plurality of addressable memory locations with the presentation of one address value, said microprocessor having a cache memory;an output device;an input/output device controller, coupled to the bus and to the output device, for receiving data from the microprocessor for output by the output device responsive to the microprocessor presenting an address value on the bus in combination with the I/O control signal;a main read/write memory, for storing digital data corresponding to inputs and outputs to and from the microprocessor, said main read/write memory having an address space;a memory controller, connected to the bus and to the main read/write memory, for controlling access to the main read/write memory responsive to the microprocessor presenting an address value on the bus by the signals in combination with the memory access control signal;wherein the memory controller prevents cache access to a non-cacheable portion of main memory;and wherein the memory controller enables a burst memory access to the non-cacheable portion of the main read/write memory responsive to the microprocessor presenting the I/O control signal in combination with the burst request signal.