Patent ID: 7772879
Filing Date: 2010-08-10
Classification: G06F,H03K

Abstract:
1. A logic module including: N data inputs; a carry input; a logic output; a sum output; a carry output; a group of 2 an N-input LUT formed from an N-level tree of 2:1 multiplexers, each multiplexer in a level of the tree having multiplexer select inputs coupled together to a unique one of the N data inputs and having first and second multiplexer data inputs and a multiplexer output, the first and second multiplexer data inputs in each level of the tree being connected in a tree structure to multiplexer outputs of the next higher level of the tree, the first and second multiplexer data inputs of each of the multiplexers in the Nth level of the tree being connected to the output of a different one of the configuration memory cells, and the output of the multiplexer in the first level of the tree being coupled to the logic output; a carry multiplexer having a first data input coupled to the carry input, a second data input coupled to a first multiplexer output internal to the N-input LUT, a select input coupled to the logic output, and an output coupled to the carry output; and an XOR gate having a first input coupled to the logic output, a second input coupled to the carry input, and an output coupled to the sum output.