Patent ID: 6709904
Filing Date: 2004-03-23
Classification: H01L

Abstract:
An integrated circuit structure comprising:a semiconductor substrate having a major surface formed along a plane; a multi-layer stack overlying the major surface and having a window formed therein, wherein the window defines an interior region bounded by upstanding sidewalls extending from a bottom wall; a relatively thin first vertical layer of single crystalline material adjacent a sidewall, wherein said first layer of single crystalline material comprises a first, a second, and a third doped region, wherein said second doped region is disposed between said first and said third doped regions, and wherein said first and said third doped regions are doped a first conductivity type and said second doped region is doped a second conductivity type; a dielectric layer extending from at least the first and the third doped regions toward the window interior region; an oxide layer adjacent said second doped region and extending away from the interior region; and a gate over said oxide layer.