Patent ID: 8970277
Filing Date: 2015-03-03
Classification: G06F,H03L

Abstract:
1. An integrated circuit device comprising: a first oscillator that generates a first clock signal; a second oscillator that generates a second clock signal; a first frequency monitor unit that monitors whether or not the frequency of the first clock signal is within a specified frequency tolerance range, and generates a first clock normal signal showing whether or not the frequency of the first clock signal is within the frequency tolerance range; a second frequency monitor unit that monitors whether or not the frequency of the second clock signal is within the frequency tolerance range, and generates a second clock normal signal showing whether or not the frequency of the second clock signal is within the frequency tolerance range; a comparator circuit that compares the frequency of the first clock signal with the frequency of the second clock signal, and generates a selection signal that selects either of the first clock signal or the second clock signal in response to the results of the clock signal frequency comparison; and a selector configured to output an output clock signal selected from among the first clock signal and the second clock signal in response to the first clock normal signal, the second clock normal signal, and the selection signal.