Patent ID: 7504891
Filing Date: 2009-03-17
Classification: H03L

Abstract:
1. A phase-locked loop (PLL), comprising: a phase frequency detector having a first input coupled to receive a reference signal; a charge-pump coupled to the phase frequency detector, wherein the charge-pump generates a first control and a second control; a loop-filter having an input coupled to selectively receive one of the first control and the second control; a controlled oscillator coupled to the loop filter, the controlled oscillator comprising a current controlled oscillator; a divider circuit coupled between an output of the controlled oscillator and a second input of the phase frequency detector; and a decision circuit having first and second inputs coupled to receive the first control and the second control, having a decision circuit output coupled to the input of loop-filter, and having a select input, wherein when operating the PLL in a first mode corresponding to the loop-filter input receiving the first control, the controlled oscillator generates a constant frequency, wherein when operating the PLL in a second mode corresponding to the loop-filter input receiving the second control, the controlled oscillator generates a frequency tracking the reference signal, and wherein a decision select control signal coupled to the select input selectively couples one of the first control and the second control to the decision circuit output.