Patent ID: 7799673
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. A semiconductor device manufacturing method comprising: sequentially forming first to fourth insulating films and first to third hard masks on a substrate in which a wiring layer serving as a lower embedded wiring line is formed; aligning a mask in which a mask pattern corresponding to a via pattern is formed with the embedded wiring layer to selectively remove the third hard mask and the second hard mask in order to form the via pattern; aligning a mask in which a mask pattern corresponding to a wiring groove pattern is formed with the via pattern to selectively remove the third hard mask and part of the second hard mask in order to form the wiring groove pattern; selectively removing the first hard mask and the fourth insulating film using the second hard mask as an etching mask to form a via pattern in the first hard mask and the fourth insulating film in a self-aligning manner, and also removing part of the second hard mask remaining under the bottom surface of the wiring groove pattern; selectively removing the first hard mask using the second hard mask in which the wiring groove pattern is formed as an etching mask after the removal of the third hard mask to form a wiring groove pattern in the first hard mask in a self-aligning manner; selectively removing the third insulating film using the fourth insulating film having the via pattern as an etching mask to form a via pattern in the third insulating film in a self-aligning manner; selectively removing the fourth insulating film using the first hard mask having the wiring groove pattern as an etching mask to form a wiring groove pattern in the fourth insulating film in a self-aligning manner, and also selectively removing the second insulating film using the fourth insulating film having the via pattern as an etching mask to form a via pattern in the second insulating film in a self-aligning manner; selectively removing the first insulating film using the third insulating film having the via pattern as an etching mask to form an opening reaching the wiring layer, after the removal of the second hard mask; selectively removing the third insulating film using the first hard mask having the wiring groove pattern as an etching mask to form a wiring groove pattern in the third insulating film in a self-aligning manner; and embedding conductors in the wiring groove pattern and the via pattern to form a via and an upper wiring line connected to the lower embedded wiring line through the via.