Patent ID: 7868892
Filing Date: 2011-01-11
Classification: G06T

Abstract:
1. A graphic data processor formed on a semiconductor chip, comprising: a central processor; a first bus coupled to said central processor; a direct memory access controller for controlling data transfer using said first bus; a bus bridge device for transmitting/receiving data to/from said first bus; a three-dimensional graphics device coupled to the first bus for receiving a command from said central processor via said first bus and performing a three-dimensional graphic process; a second bus coupled to said bus bridge device and a plurality of first circuit devices; a third bus coupled to said three-dimensional graphics device; a fourth bus which is coupled to said bus bridge device and is capable of being used for register setting from said central processor to the plurality of first circuit devices; and memory interface means coupled to said first bus, said second bus, and said three-dimensional graphics device via said third bus directly, and capable of being coupled to a memory, wherein said bus bridge device is capable of controlling a direct memory access transfer between a device coupled to the outside of the semiconductor chip and said second bus, wherein said memory interface means arbitrates access between said memory and said central processor for transferring data to/from said memory, between said memory and said three-dimensional graphics device for receiving data from said memory via said third bus independently from said first bus and said second bus, and between said memory and one of said first circuit devices for receiving data from said memory via said second bus independently from said first bus and said third bus, and wherein said three-dimensional graphics device receives graphics data via said third bus.