Patent ID: 6557137
Filing Date: 2003-04-29
Classification: G06T,H03M

Abstract:
A bit-error resistant arithmetic encoding apparatus for generating an encoded bit stream by compressing a plurality of input binary symbols, the arithmetic encoding apparatus comprising:a symbol distribution unit for dividing the plurality of input binary symbols into a plurality of segments and determining the length of a code stream corresponding to each divided segment; a first encoding unit for arithmetically encoding each of the symbols of a divided segment until the encoded length of the code stream is a predetermined length, for each divided segment; a symbol accumulation unit for accumulating binary symbols that are not encoded by the first encoding unit; a second encoding unit for generating a code stream by arithmetically encoding binary symbols stored in the symbol accumulation unit until the encoded length of a code stream is a predetermined length, for each divided segment in which the encoded length of the code stream is less than the predetermined length among the segments arithmetically encoded by the first encoding unit; and a code multiplexing unit for generating the encoded bit stream by multiplexing the plurality of code streams.