Patent ID: 9183923
Filing Date: 2015-11-10
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a plurality of word lines; a plurality of bit lines including a first bit line and a second bit line; a plurality of memory cells including a plurality of first-column memory cells provided between and connected to the first bit line and the second bit line and connected to the plurality of word lines, respectively; and a plurality of memory cell power supply circuits including a first-column memory cell power supply circuit, the first-column memory cell power supply circuit configured to supply a same memory cell power supply to the plurality of first-column memory cells, wherein: the first-column memory cell power supply circuit includes a first PMOS transistor, a second PMOS transistor and a first NMOS transistor connected together in series between a first and a second power supply, the memory cell power supply is output at a connection point between the first and second PMOS transistors, a control signal which is based on a column select signal and a write control signal is input to a gate terminal of the first PMOS transistor and a gate terminal of the first NMOS transistor, and a drain terminal of the first NMOS transistor is connected to a gate terminal of the second PMOS transistor.