Patent ID: 8966428
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. A method for fabricating an integrated circuit (IC) chip with mixed-size modules, including soft and hard modules under fixed-outline constraints, and comprising computer floorplanning steps of: step one: evenly distributing circuit modules over whole chip area under the control of a computer; step two: generating a slicing tree by applying a recursive partition based approach to module positions obtained in the step one, where partitioning stops on a pre-determined condition; and step three: removing overlaps between the circuit modules and finding a feasible solution in conformity with the fixed-outline constraints by bottom-up merging of shape curves of nodes in the slicing tree and then top-down back tracing of the same nodes to determine shapes and locations of the circuit modules, wherein each shape curve is composed of points representing dimensions of possible floorplans for fabricating the IC chips using said computer.