Patent ID: 6979851
Filing Date: 2005-12-27
Classification: H01L

Abstract:
1. An integrated circuit having a dynamic random access memory (DRAM), said DRAM having a memory cell including: a storage capacitor having a capacitor dielectric disposed along a sidewall of a trench extending into a region of substrate, said region consisting essentially of semiconductor; a node conductor provided within said trench, said node conductor conductively contacting said storage capacitor from above; a buried strap outdiffusion (BSOD) disposed adjacent to said trench in said region, said BSOD being conductively coupled to said node conductor; an isolation collar disposed along said sidewall of said trench, said isolation collar separating said node conductor from said region, said isolation collar having a reduced thickness where said isolation collar contacts said BSOD and having at least a second thickness substantially greeter than said reduced thickness other than where said isolation collar contacts said BSOD.