Patent ID: 7505340
Filing Date: 2009-03-17
Classification: G11C

Abstract:
1. A method for implementing static random access memory (SRAM) cell write performance evaluation using a SRAM cell write performance evaluation circuit including a SRAM core, said SRAM core including a plurality of wordlines, each wordline being connected to connected to one SRAM cell from only one bit column, said method comprising the steps of: providing a ring oscillator circuit coupled to said SRAM core for selectively generating wordline pulses; providing an output logic coupled to said SRAM core and ring oscillator circuit, said output logic selectively providing an output oscillator signal to identify a minimum wordline pulse width to write said SRAM cell; and providing a state machine coupled to said ring oscillator circuit and said input logic, said state machine controlling said ring oscillator circuit to enable incrementally vary a wordline pulse width and said state machine controlling write and read operations to said SRAM core for implementing SRAM cell write performance evaluation.