Patent ID: 6622279
Filing Date: 2003-09-16
Classification: G06F,H03M

Abstract:
A computer for processing data, the data being generated with a reversible code and including bit sequences having various lengths, the computer comprising:memory; a register; a data buffer coupled to the register so that a bit sequence of data transmitted from the data buffer to the register is reversed, the register being coupled to the data buffer so that a bit sequence of data transmitted from the register to the data buffer is maintained, wherein a group of data is enclosed by synchronization bit sequences; and at least one arrangement that performs the steps of: transferring the data of a group from the data buffer into the register when an erroneous bit is recognized in a bit sequence of the data of the group, retransferring the data from the register into the data buffer, the data being retransfered so that the bits in the data buffer have the same sequence as in the register, and comparing and decoding bit sequences up to the erroneous bit using stored bit sequences for decoding bit sequences having bits in reversed sequence.