Patent ID: 6458643
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method of fabricating a MOS device with an ultra-shallow junction (USJ) as a source extension or a drain extension, the method comprising:providing a semiconductor substrate, the semiconductor substrate comprising at least a gate; performing a first ion implantation process to form a pocket implant region of a first conductive type within the semiconductor substrate beneath the gate; performing a first rapid thermal annealing (RTA) process immediately after the first ion implantation process to reduce transient enhanced diffusion (TED) effects resulting from the first ion implantation process; and performing a second implantation process to form a source extension doping region and a drain extension doping region of a second conductive type within the semiconductor substrate adjacent to the gate; wherein the first ion implantation process uses an implantation energy that greater than an implantation energy of the second ion implantation process.