Patent ID: 8912042
Filing Date: 2014-12-16
Classification: H01L

Abstract:
1. A manufacturing method for a plurality of layered chip packages, each of the plurality of layered chip packages including a main package, at least one of the plurality of layered chip packages being a composite layered chip package, the composite layered chip package further including an additional package stacked on the main package, wherein: the main package includes a main body and wiring; the main body includes: a main part having a top surface and a bottom surface and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top surface and the bottom surface of the main part; the wiring is electrically connected to the plurality of main terminals; each of the plurality of layer portions includes a semiconductor chip; the plurality of layer portions of the main part include at least one first-type layer portion; the main body of the main package in the composite layered chip package is a specific main body, and, in the specific main body, the plurality of layer portions of the main part further include at least one second-type layer portion; the semiconductor chip of the first-type layer portion is non-malfunctioning and electrically connected to the wiring; the semiconductor chip of the second-type layer portion is malfunctioning and not electrically connected to the wiring; the additional package includes: an additional semiconductor chip to substitute for the semiconductor chip of the second-type layer portion; and a plurality of additional terminals; and at least one of the plurality of additional terminals is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals, the manufacturing method comprising the steps of: fabricating a layered substructure by stacking a plurality of substructures each of which includes a plurality of preliminary layer portions that are arrayed, each of the plurality of preliminary layer portions being intended to become any one of the layer portions included in the main part, the plurality of substructures being intended to be cut later at positions of boundaries between every adjacent ones of the preliminary layer portions; joining at least one additional package to the layered substructure; and producing the plurality of layered chip packages from the layered substructure with the at least one additional package joined thereto, wherein: the layered substructure includes a plurality of main bodies that are to be separated from each other later; at least one of the plurality of main bodies included in the layered substructure is the specific main body; in the step of joining the at least one additional package to the layered substructure, the at least one additional package is joined to the at least one specific main body included in the layered substructure; and the step of producing the plurality of layered chip packages includes the step of separating the plurality of main bodies from each other by cutting the layered substructure with the at least one additional package joined thereto.