Patent ID: 9116407
Filing Date: 2015-08-25
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: a plurality of gate scanning lines and a plurality of data signal lines, crossing one another; a plurality of pixel regions, defined by crossing of the plurality of gate scanning lines and the plurality of data signal lines and arranged in a matrix; a plurality of thin film transistors, each comprised in each of the plurality of pixel regions; a plurality of pixel electrodes, each covering each of the plurality of pixel regions, and comprising a plurality of first pixel electrodes and a plurality of second pixel electrodes, wherein the plurality of pixel regions are divided into a plurality of first pixel regions and a plurality of second pixel regions, each of the plurality of pixel regions is defined by crossing of two adjacent gate scanning lines and two adjacent data signal lines, the plurality of first pixel regions are provided at intervals, and each of the first pixel regions is covered with a corresponding first pixel electrode, and the first pixel electrodes are located in a first layer, the plurality of second pixel regions are provided at intervals, and each of the second pixel regions is covered with a corresponding second pixel electrode, and the second pixel electrodes are located in a second layer, and an insulating layer is provided between the first layer and the second layer, and wherein “being provided at intervals” refers to being provided at intervals of one pixel region, wherein there is one second pixel region between any two adjacent first pixel regions of the plurality of first pixel regions, and there is one first pixel region between any two adjacent second pixel regions of the plurality of first pixel regions.