Patent ID: 7433912
Filing Date: 2008-10-07
Classification: G06F

Abstract:
1. A multiplication unit comprising: a partitionable multiplier structure partitionable into two or more sub-tree structures, the multiplication unit responsive to an indication of a first instruction type to be partitioned into the two or more sub-trees structure to perform multiple multiplication operations in parallel, and responsive to an indication of a second instruction type to configure the subtree structures into a single data flow to perform a single multiplication operation; an input format stage coupled to receive one or more first input operands and to format the one or more first input operands according to a type of multiply operation being performed; an encoder circuit coupled to receive the one or more formatted first input operands and supply control signals to multiplexer circuits used in generating partial products in the partitioned sub-tree structure; and wherein the input format stage formats bits corresponding to edges of each partitionable sub-tree structure according to the instruction type specifying the multiply operation being performed.