Patent ID: 8633587
Filing Date: 2014-01-21
Classification: H01L,H05K

Abstract:
1. A package structure, comprising: a core board having a first surface, an opposite second surface, and at least a through cavity penetrating the first and second surfaces; a semiconductor chip received in the through cavity and having an active surface and an opposite inactive surface, the active surface and the inactive surface having a plurality of first electrode pads and a plurality of second electrode pads, respectively, wherein the semiconductor chip has a plurality of through-silicon vias, and a portion of the through-silicon vias penetrate the semiconductor chip for electrically connecting the first and second electrode pads, and only a portion of the through-silicon vias extend to an interior of the semiconductor chip; a first dielectric layer disposed on the first surface of the core board and the active surface of the semiconductor chip; a first wiring layer disposed on the first dielectric layer; a second dielectric layer disposed on the second surface of the core board and the inactive surface of the semiconductor chip; a second wiring layer disposed on the second dielectric layer; and a plurality of bumps disposed in the first and second dielectric layers so as for the first and second electrode pads to be electrically connected to the first and second wiring layers, respectively, via the bumps.