Patent ID: 6440641
Filing Date: 2002-08-27
Classification: H01L,H05K

Abstract:
A method for forming a high density interconnect printed wiring board substrate having a first patterned conductive layer having a first thickness, including a plurality of conductive lines having edges that define boundaries of said conductive lines, formed over an upper surface of the substrate, said method comprising:(a) forming a stress buffer layer directly on said first patterned conductive layer and between the edges of said first patterned conductive layer, wherein said stress buffer layer is between 20 and 35 microns thick in areas directly above said first patterned conductive layer and wherein said stress buffer layer is a single layer of either a composite dielectric layer having particles suspended in said layer or a homogenous dielectric layer having an elongation percentage of at least 10%; (b) forming a thin film conductive layer having a second thickness directly on said stress buffer layer, wherein a ratio of said first thickness to said second thickness is at least 3:1; and (c) forming a thin film dielectric layer over said thin film conductive layer.