Patent ID: 7730366
Filing Date: 2010-06-01
Classification: G11B,H03L,H04N

Abstract:
1. A signal processing method having N phase clocks used in a digital phase-locked loop system, said method comprising the steps of: inputting an asynchronous signal; generating N phase clocks with a VCO that receives a reference clock as an input, the reference clock being derived from the asynchronous signal, the VCO output frequency is altered to be substantially coincident with the frequency of the asynchronous signal; detecting a pulse length of the asynchronous signal by using the n-phase clocks to generate pulse-length data based on a timing relationship for changing points of the asynchronous signal determined with reference to the n-phase clocks; and thereby determining phase differences with the asynchronous signal and altering a voltage controlled oscillator based on the identified changing points for the asynchronous signal.