Patent ID: 6643789
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A synchronous memory device comprising:a data bus having a plurality of data bus terminals; an address decoder; a control logic circuit structured to generate control signals responsive to memory commands; a memory-cell array coupled to the address decoder and the control logic circuit; a data path coupled between the memory-cell array and the data bus; and a data delay circuit coupling a digital signal from a first location to a second location, the data delay circuit comprising: an adjustable time delay circuit having a delay control input, the delay control input being coupled to receive a delay control signal, the time delay circuit coupled to receive a first clock signal and to generate a delayed clock signal, the time between when the first clock signal changes state and when the delayed clock signal changes state being determined by the delay control signal; and a data passing circuit having a data input terminal coupled to the first location and a data output terminal coupled to the second location, the data passing circuit receiving the delayed clock signal and being structured to pass the digital signal from the data input terminal to a data output terminal responsive to the delayed clock signal changing state.