Patent ID: 6015749
Filing Date: 2000-01-18
Classification: H01L

Abstract:
A method for forming a metal interconnect structure, on a semiconductor substrate, comprising the steps of:providing a insulator layer, on said semiconductor substrate, and providing a contact hole in said insulator layer, exposing underlying conductive elements;depositing a barrier layer;depositing a copper seed layer;ion implanting germanium ions into a first region of said copper seed layer, in which said copper seed layer, and said barrier layer, reside on the top surface of said insulator layer, and ion implanting said germanium ions into a second region of said copper seed layer, in which said copper seed layer, and said barrier layer reside on the top surface of said conductive elements, located at the bottom of said contact hole;depositing a thick copper layer;annealing, before or after deposition of said thick copper layer, to form a Cu.sub.3 Ge intermetallic layer, with the formation of said Cu.sub.3 Ge intermetallic layer consuming all of said germanium ions, and consuming a bottom portion of said copper seed layer, and with said Cu.sub.3 Ge intermetallic layer forming in said first region of said copper seed layer, and forming said Cu.sub.3 Ge intermetallic layer in said second region of said copper seed layer; andpatterning, via use of dry etching or damascene procedures, of said thick copper layer, of said copper seed layer, of said Cu.sub.3 Ge intermetallic layer, and of said barrier layer, to form said metal interconnect structure.