Patent ID: 8782379
Filing Date: 2014-07-15
Classification: H03M,H04N

Abstract:
1. A device comprising: a processing circuit operative to implement a set of instructions to decode multiple bins simultaneously and renormalize an offset register and a range register, wherein the renormalization occurs in intervals of bytes, and wherein renormalizing the offset register and the range register comprises a first type of renormalization process employed by a bypass decoding mode process and a second type of renormalization process employed, after normal decoding, by a normal decoding mode process, wherein the first type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a first threshold, and wherein the second type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a second threshold; and a memory coupled to the processing circuit.