Patent ID: 6684074
Filing Date: 2004-01-27
Classification: H04W

Abstract:
In a digital unit of a multi-sector base station system including at least one code division multiple access (CDMA) channel card assembly having at least two cell site modems, and a controller adapted to control the overall operation of the CDMA channel card assembly, at least one baseband and intermediate frequency conversion card assembly, and at least one shelf control and routing card assembly, a switching device comprising a switching element coupled between the cell site modems, the switching element comprising:a function decoder for receiving an address signal and a write/read signal acquired from the controller of the CDMA channel card assembly, decoding the received signals, and transmitting an enable signal to each block of the switching element, based on the decoding result; first and second switch controllers adapted to decode a switch control command outputted from the CDMA channel card assembly, thereby generating switch control signals, respectively; first and second forward switch sections adapted to distribute 3-sector forward signals outputted from the two cell site modems, into 6-sector signals, in accordance with the switch control signals outputted from the first and second switch controllers, respectively; first and second reverse switch sections adapted to connect 6-sector reverse signals, received from the baseband and intermediate frequency conversion card assembly, to respective sectors of the 3-sector cell site modems, based on respective switch control signals outputted from the first and second switch controllers; first and second digital summing sections adapted to adding the 6-sector data outputted from the first and second forward switch sections to 6-sector data received from a preceding switching element stage, respectively; first and second parity generating sections adapted to check respective parities of forward data outputted from the first and second digital summing sections, each of the first and second parity generating sections inserting an odd parity into the last bit of each unit data; a timing generating section for generating a timing clock in response to every system clock in sync with an input even second clock, and transmitting the timing clock to each block of the switching element; first and second parity error checking sections each adapted to check whether or not the parity of digital sum data transmitted from the preceding switching element stage is an odd parity, and to activate a parity error signal when it is determined that a parity error is generated; first and second interrupt generating sections respectively adapted to generate interrupt signals when parity errors are detected by the first and second parity error checking sections; and first and second preceding switching element data input cut-off sections adapted to cut off the data, outputted from the preceding switching element stage, in response to the generation of the parity errors, thereby preventing the data from being inputted to the first and second digital summing sections, respectively.