Patent ID: 7020752
Filing Date: 2006-03-28
Classification: G06F

Abstract:
1. In a data cache memory interacting with a first execution unit and a second execution unit; a valid bit array unit, the unit comprising: a group of addressable storage cells, the data cache memory including a tag unit, each storagc cell storing a valid/invalid bit signal; a first address port for accessing a plurality of storage cells during a read and a write operation in response to an address signal group, the valid bit array unit retrieving a plurality of valid bit signals from the accessed location in response to read operation address signal group, the valid bit array unit storing a valid bit; a second address port for accessing a plurality of storage cell location in response to a snoop address signal group; a control signal port having a control signal generated from the from the tag unit applied thereto, wherein the application of the control signal specifies the storage cell of the valid bit to be changed to an invalid bit; and wherein the tag unit is divided into a first plurality of independently addressable subunits, wherein application of an address signal group to the address port in a read operation causes the retrieval of the plurality of signals in valid/invalid bit locations associated with each tag subunit; and, the valid bit array unit is located between the tag subunits to minimize difference in transit time between signals of the tag subunits.