Patent ID: 7428615
Filing Date: 2008-09-23
Classification: G06F

Abstract:
1. A data processing system comprising a processor and a memory hierarchy, wherein the highest ranked level in the hierarchy is a cache coupled to the processor, wherein a higher ranked cache in the memory hierarchy has a cache controller operating according to a write allocate scheme, a lower ranked cache is coupled to the higher ranked cache and has a cache controller, wherein the size of the higher ranked cache is smaller than the size of the lower ranked cache, wherein both caches administrate auxiliary information indicating whether data present therein is valid, wherein, the line size of the lower ranked cache is an integer multiple of the line size of the higher ranked cache, wherein the auxiliary information in the higher ranked cache concerns data elements at a finer granularity than the auxiliary information in the lower ranked cache and wherein the higher ranked cache is arranged for transmitting a write mask to the lower ranked cache in conjunction with a line of data for indicating which data in the lower ranked cache is to be overwritten at the finer granularity, the cache controller of the lower ranked cache being arranged for fetching a cache line from the next lower ranked level in the memory hierarchy if the cache line is not cached yet and the write mask indicates that the data in the line provided by the higher ranked cache is only partially valid, and wherein fetching the cache line from said next lower ranked level is suppressed if the write mask indicates that the line provided by the higher ranked cache is valid in accordance with the courser granularity of the auxiliary information in the lower ranked cache, in which case, the controller of the lower ranked cache allocates the cache line in the lower ranked cache without fetching the cache line from the next lower ranked level.