Patent ID: 6587996
Filing Date: 2003-07-01
Classification: G01R,G11C

Abstract:
A device to test a circuit on a chip having memory using a scan circuit, comprising:a memory embedded in the chip, the memory having a plurality of address, data and control inputs, and a plurality of output bits; a scan bypass circuit to logically combine at least ones of the plurality of address, data and control inputs to obtain a substantially equal plurality of scan bypass bits as the plurality of output bits output by the memory; and a multiplexer connected to receive the plurality of output bits of the memory and the substantially equal plurality of scan bypass bits of the scan bypass circuit, wherein when a scan test is run the multiplexer will multiplex pass the substantially equal plurality of scan bypass bits of the scan bypass circuit and not the output bits from the memory, and when the scan test is not run the multiplexer will multiplex pass the plurality of output bits from the memory and not from the scan bypass circuit.