Patent ID: 6287939
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method for fabricating a shallow trench isolation which is not susceptible to the buried contact trench problem, comprising the steps of:a) providing a semicoductor substrate having active areas wherein a pad oxide layer overlies said semiconductor substrate and a nitride layer overlies said pad oxide layer;b) forming trenches in said nitride layer, said pad oxide layer, and said semiconductor substrate;c) depositing a fill oxide in said trenches and planarizing said fill oxide to form fill oxide regions co-planar with said nitride layer;d) forming a buried oxynitride layer in said fill oxide regions; said buried oxynitride layer having a thickness of between about 100 angstroms and 200 angstroms and being partially above the level of the top surface of said semiconductor substrate and partially below the level of the top surface of said semiconductor substrate; said buried oxynitrde layer dividing said fill oxide region into an upper portion overlying said buried oxynitride layer and a lower portion underlying said buried oxynitride layer;e) removing said nitride layer; andf) etching said pad oxide layer and said upper portions of said fill oxide regions stopping on said buried oxynitride layer leaving a portion of said buried oxynitride layer and said lower portion of said fill oxide region; thereby forming shallow trench isolations which are not susceptible to the buried contact trench problem.