Patent ID: 6137478
Filing Date: 2000-10-24
Classification: G01B,G06F,G09B

Abstract:
A pin matrix I/O device comprising, in combination:a housing with a rectangular configuration having a bottom face, a top face and a peripheral side wall coupled therebetween for defining an interior space, the top face having a matrix of bores formed therein;a plurality of pin solenoids each having a unique address and including:a pin casing having a hollow cylindrical configuration and coupled to the bottom face of the housing within the interior space thereof and in alignment with one of the bores thereof, each pin casing having a circular bottom face, a circular top face, a cylindrical side wall mounted between the top face and the bottom face, and an aperture formed in the top face of the pin casing for defining an inwardly extending lip,a transducer slidably situated within the pin casing and extending front the aperture thereof and the associated bore of the housing,a coil spring wrapped about the transducer and residing exterior of the pin casing, the coil ring having a first end connected to the top face of the pin casing and second end connected to the transducer for urging the transducer into a neutral position with a top end of the transducer extended a predetermined distance above the top face of the housing, anda pin coil mounted within a bottom extent of the pin casing for urging the transducer a predetermined distance from the top face of the housing upon the receipt of an activation signal, wherein an extent to which the transducer extends above the top face of the housing is a function of a magnitude of the activation signal;a plurality of pin position potentiometers each mounted on an associated one of the pin solenoids for generating a position signal which is representative of a current position of the corresponding transducer with respect to the top face of the housing; andinterface logic connected to the relay coils of the pin solenoids with digital-to-analog converters connected therebetween for transmitting activation signals to the pin solenoids upon the receipt of a digital input signal with an associated address, wherein the activation signals are each transmitted to one of the pin solenoids with an address corresponding with that of input signal and the activation signals each have a magnitude dictated by the input signal, the interface logic connected to the pin position potentiometers with analog-to-digital converters connected therebetween for generating digital output signals each including the address of a designated one of the pin solenoids and the current position of the designated one of the pin solenoids as indicated by the position signal.