Patent ID: 8106424
Filing Date: 2012-01-31
Classification: H01L,Y10S

Abstract:
1. A field effect transistor with a heterostructure, comprising: a carrier material, wherein the carrier material includes a relaxed monocrystalline semiconductor layer made of a first semiconductor material as a topmost layer; a strained monocrystalline semiconductor layer formed on the relaxed monocrystalline semiconductor layer and including a semiconductor alloy comprising the first semiconductor material and at least one second semiconductor material, where a proportion of the second semiconductor material is settable; a gate insulation layer formed on the strained monocrystalline semiconductor layer; and a gate layer formed on the gate insulation layer; and drain/source regions, are formed laterally with respect to the gate layer at least in the strained semiconductor layer to define an undoped channel region, wherein the relaxed monocrystalline semiconductor layer has a thickness of approximately 3 to 5 nm, and the strained monocrystalline semiconductor layer has a thickness of approximately 3 to 5 nm.