Patent ID: 8964442
Filing Date: 2015-02-24
Classification: G11C,H01L

Abstract:
1. A method for manufacturing a memory device, comprising: forming an array of access devices; forming a plurality of conductive layers under or over the array of access devices, separated from each other and from the array of access devices by insulating layers; forming an array of pillars extending through the plurality of conductive layers, the pillars in the array contacting corresponding access devices in the array of access devices, and defining interface regions between the pillar and conductive layers in the plurality of conductive layers; forming memory elements in the interface regions including a current path between corresponding pillars and conductive layers, each of said memory elements comprising a phase change material; and forming circuitry coupled to the array of access devices and the plurality of conductive layers configured to program data in the memory elements, the data having one of N data values represented by N non-overlapping ranges of resistance; wherein N is greater than or equal to two; wherein N different thicknesses of amorphous phase of the phase change material in the memory elements correspond to the N data values; and wherein a state of the memory cell comprising no volume of amorphous phase of the phase change material in the current path does not correspond to a stored data value.