Patent ID: 8343807
Filing Date: 2013-01-01
Classification: B81B,H01L

Abstract:
1. A process, comprising: providing an apparatus including a chip substrate having a first chip surface, an array of sensors or optoelectronic devices being on the first chip surface, and an array of conductors, each of the conductors being located within the chip substrate and having a first end located at the first chip surface, each of the first ends of the conductors being in direct physical contact at the first chip surface with one of the sensors or optoelectronic devices, and each of the conductors having a second end buried within the chip substrate; providing a temporary support carrier having a first carrier surface, a second carrier surface facing away from the first carrier surface, and an array of perforations each reaching both of the first and second carrier surfaces; bonding the first carrier surface of the temporary support carrier onto the array of sensors or optoelectronic devices; removing a portion of the chip substrate, thereby forming a second chip surface facing away from the first chip surface and exposing the second ends of the conductors through the second chip surface; and forming a plurality of direct chip attachment pads at the second chip surface, wherein each of the direct chip attachment pads is in communication with the second end of one of the conductors.