Patent ID: 8329510
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A method of making a semiconductor chip assembly, comprising: providing a post, a base, an ESD protection layer, a metal layer, an adhesive and a conductive layer, wherein the metal layer extends below the ESD protection layer and extends laterally beyond the post, the adhesive is mounted on and extends above the base, is sandwiched between the base and the conductive layer and is non-solidified, and the conductive layer is mounted on and extends above the adhesive; then flowing the adhesive into and upward in a gap located in the aperture between the post and the conductive layer; solidifying the adhesive; then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, wherein providing the pad includes: providing a heat spreader that includes the post, the base, the ESD protection layer and an underlayer that includes at least a portion of the metal layer; then mounting a semiconductor device on the post, wherein the semiconductor device overlaps the post, the base, the ESD protection layer and the underlayer, the semiconductor device, the post and the base are electrically isolated from the underlayer and the underlayer covers the post in the downward direction; electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and thermally connecting the semiconductor device to the post, thereby thermally connecting the semiconductor device to the underlayer.