Patent ID: 6965525
Filing Date: 2005-11-15
Classification: G11C

Abstract:
1. A nonvolatile memory apparatus comprising: a control circuit; a plurality of terminals including a clock terminal, a command terminal and other terminal; a clock generator; and a plurality of nonvolatile memory cells, wherein said clock terminal receives a first clock signal, wherein said command terminal receives commands which comprise a read command and a program command, wherein said clock generator is controlled by said control circuit for generating a second clock signal, wherein said control circuit reads out operation steps from a program memory for controlling an operation of a received command by executing said operation steps, wherein in an operation in response to said read command received from said command terminal, said control circuit controls, based on operation steps corresponding to said read command, reading data from ones of said nonvolatile memory cells, and outputting data via said other terminal not said command terminal in response to said first clock signal, wherein in an operation in response to said program command received from said command terminal, said control circuit controls, based on operation steps corresponding to said program command, receiving data via said other terminal not said command terminal in response to said first clock signal, and writing data to ones of said nonvolatile memory cells, and wherein said data writing to ones of said nonvolatile memory cells is performed using said second clock signal.