Patent ID: 6087215
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method of fabricating a DRAM device comprising the steps of:forming a well region of a first conductivity type in a semiconductor substrate;forming a mask pattern which exposes a portion of the semiconductor substrate having the well region;ion implanting an impurity of the second conductivity type in an exposed region to form an impurity region in the semiconductor substrate;removing the mask pattern;forming a gate electrode on a selected portion of a top surface of the semiconductor substrate having the well region formed therein;forming source region and drain region both of a second conductivity type at both sides of the gate electrode within the well region, the source region formed between the impurity region and the surface of the semiconductor substrate;forming an interlayered insulating layer all over the surface of the semiconductor substrate having the gate electrode, the source region and the drain region;etching a selected portion of the interlayered insulating layer such that the source region is exposed, to form a contact hole for a storage node;plug ion implanting an impurity of a second conductivity type in the source region; andforming a storage node electrode which contacts the source region on a top surface of the interlayered insulating layer.