Patent ID: 8791719
Filing Date: 2014-07-29
Classification: H03F,H03G,H03K,H03L,H04B

Abstract:
1. A digital control interface comprising: a voltage input/output (VIO) pin configured to receive a VIO signal; a front end core configured to provide a serial interface, the front end core in an active state when the VIO signal satisfies a first logic level and in an inactive state when the VIO signal satisfies a second logic level, the digital control interface configured to provide a general purpose input/output (GPIO) interface when the front end core is set to the inactive state; a combinational logic block configured to provide an enable signal to an enable level shifter and a mode signal to a mode level shifter; a clock/mode pin configured to provide a clock signal to the front end core when the front end core is set to an active state and a mode signal to the combinational logic block when the front end core is set to an inactive state; a data/enable pin configured to provide a data signal to the front end core when the front end core is set to an active state and an enable signal to the combinational logic block when the front end core is set to an inactive state; and a power on reset block configured to select, based on the VIO signal, a source of the enable signal and the mode signal provided to the enable level shifter and the mode level shifter respectively.