Patent ID: 9123554
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A semiconductor device comprising: a wiring board; a first semiconductor chip mounted over the wiring board; and a second semiconductor chip mounted in a central part located over the first semiconductor chip, wherein the wiring board includes: a plurality of external coupling electrodes disposed in an array form at a bottom surface of the wiring board; a plurality of substrate electrodes disposed in an array form at a top surface of the wiring board in pitches smaller than those of the external coupling electrodes; and in-substrate wirings for coupling the external coupling electrodes and the substrate electrodes to one another respectively, wherein the first semiconductor chip includes: first internal circuits integrated by a semiconductor integrated circuit technology; a plurality of first chip bottom surface electrodes which are coupled to their corresponding substrate electrodes and coupled to required circuit nodes of the first internal circuits respectively and which are disposed in an array form at a bottom surface of the first semiconductor chip; and a plurality of first chip top surface electrodes coupled to the required circuit nodes of the first internal circuits respectively and disposed in an array form at a top surface of the first semiconductor chip, wherein the second semiconductor chip includes: second internal circuits integrated by a semiconductor integrated circuit technology; a plurality of second chip bottom surface electrodes which are coupled to their corresponding first chip top surface electrodes and coupled to required circuit nodes of the second internal circuits respectively and which are arranged in an array form at a bottom surface of the second semiconductor chip; and a plurality of second chip top surface electrodes coupled to the required circuit nodes of the second internal circuits respectively and arranged in an array form at a top surface of the second semiconductor chip, wherein the corresponding electrodes for signals and power and ground systems in the second chip bottom surface electrodes and the second chip top surface electrodes are coupled through second silicon through vias, and the second silicon through vias for the power system and the second silicon through vias for the ground system are arranged so as to pair up with each other in a required combination based on one unit or plural units, wherein the power and ground system electrodes coupled to the second silicon through vias are gathered in the central part of the first semiconductor chip within the first chip bottom surface electrodes and the first chip top surface electrodes, the first chip bottom surface electrodes of the power and ground systems gathered in the central part and the first chip top surface electrodes corresponding to the first chip bottom surface electrodes are coupled through first silicon through vias, and the power system first silicon through vias and the ground system first silicon through vias are arranged so as to pair up with each other in a required combination based on one unit or plural units, and wherein the electrodes related to the power and ground systems, which are coupled to the first silicon through vias, are gathered in the central part of the wiring board within the external coupling electrodes and the substrate electrodes, and the power system electrodes and the ground system electrodes gathered in the central part are arranged so as to pair up with each other in a required combination based on one unit or plural units.