Patent ID: 6801988
Filing Date: 2004-10-05
Classification: G06F

Abstract:
A data buffer for block-unit data transfer, comprising:an initial address register for holding a transfer destination address input via a data bus as an initial address; an input data register for holding maximum k pieces (k is an integer equal to or more than 2) of M-byte data (M is an integer equal to or more than 1) input via the data bus; an address decoder for decoding an address on an address bus so that the transfer destination address on the data bus is written into the initial address register if the address on the address bus is an address designating the initial address register and that the M-byte data on the data bus is written into the input data register if the address on the address bus is an address designating the input data register when a data buffer write signal is provided; an accumulated data size register for holding an accumulated data size representing the size of a data block of maximum N bytes (N=kM) accumulated in the input data register; an output data register for holding a data block to be transferred; a block address register for holding a head address of the data block to be transferred; a block size register for holding the block size representing the size of the data block to be transferred; a block address counter for setting the initial address transferred from the initial address register as an initial value and holding a block address updated according to the block size; and a sequence controller for updating the accumulated data size by M byte(s) every time the M-byte data on the data bus is written into the input data register, setting the block size in the block size register at N bytes if the initial address is an N-byte boundary address (an address divisible by N), waiting until the accumulated data size reaches N bytes, transferring the data block of N bytes accumulated in the input data register to the output data register, transferring the block address held by the block address counter to the block address register, asserting a block data write request signal so that the data block of N bytes held by the output data register is transferred, resetting the accumulated data size at 0, and updating the block address held by the block address counter by N bytes.