Patent ID: 6178121
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word lines;a plurality of bit line pairs;a plurality of memory cells, each of the memory cells being connected to one of the word lines and also to one of the bit line pairs;a plurality of potential-control circuits; anda plurality of sense amplifiers which amplify data read-out from the plurality of memory cells through the plurality of bit line pairs to output the amplified data;wherein each of the memory cells comprises:a transistor comprising a control electrode and two input/output electrodes, the control electrode being connected to one of the word lines, and one of the input/output electrodes being connected to a bit line of one of the bit line pairs; anda data-storing capacitor further comprising a first electrode and a second electrode, the first electrode being connected to the other of the input/output electrodes of the transistor, and the second electrode being connected to one of the potential control circuits;wherein each of the plurality of potential control circuits changes the potential of the second electrode of the data-storing capacitor in response to and based on data stored in a memory cell in the plurality of memory cells after data-writing and data-reading operations for the memory cell has been completed.