Patent ID: 6537734
Filing Date: 2003-03-25
Classification: B41J,G03F,Y10S

Abstract:
A method of forming resist patterns, comprising the steps of:providing an integrated circuit wafer; forming a layer of resist on said integrated circuit wafer; selectively exposing said layer of resist; placing said integrated circuit wafer in a chamber; placing developer on said selectively exposed layer of resist after said integrated circuit wafer has been placed in said chamber; placing cleaning liquid in said chamber thereby immersing said integrated circuit wafer in said cleaning liquid after said developer has been placed on said selectively exposed layer of resist for a first time; removing said cleaning liquid from said chamber after said integrated circuit wafer has been immersed in said cleaning liquid for a second time; sealing said chamber; evacuating said sealed chamber to a pressure of about 1Ã—10âˆ’2 Torr or less after removing said cleaning liquid from said chamber; and opening said sealed chamber and removing said integrated circuit wafer after said integrated circuit wafer has been in said sealed chamber at a pressure of about 1Ã—10âˆ’2 Torr or less for a second time.