Patent ID: 8705673
Filing Date: 2014-04-22
Classification: H04L

Abstract:
1. A method for utilizing data decoding circuitry to determine clock phase, the method comprising: providing a matched filter bank, wherein the matched filter bank is operable to receive a series of symbols at a rate corresponding to a sample clock, wherein the matched filter bank includes a first matched filter and a second matched filter, wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and wherein the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence; receiving a timing pattern; re-tuning the first matched filter to detect a first pattern corresponding to the timing pattern sampled using a first phase of the sample clock; and re-tuning the second matched filter to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock.