Patent ID: 9064547
Filing Date: 2015-06-23
Classification: G11C,H01L

Abstract:
1. A memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate, the memory further comprising: a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes, wherein the bit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes; a non-volatile re-programmable memory element in contact with a bit line pillar and a word line at individual ones of the crossings; said non-volatile re-programmable memory element having a tubular shell with an outer surface, a first portion of the outer surface acts as a first electrode for the bit line pillar and a second portion of the outer surface acts as a second electrode for the word line; and wherein the tubular shell has a thickness that controls an electrical conductance of said non-volatile re-programmable memory element across the bit line pillar and the word line.