Patent ID: 8471343
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A method of making a MOSFET semiconductor structure having reduced parasitic capacitance comprising: (a) obtaining a MOSFET device comprising: (b) depositing a contact etch stop liner over the gate stack structure, nitride spacers and silicide layers that are adjacent to each of the nitride spacers; (c) depositing a sacrificial interlayer dielectric material over the contact etch stop liner; (d) masking and etching the interlayer dielectric material to pattern a plurality of apertures corresponding to a plurality of contacts to the source/drain and gate stack structures; (e) depositing a lining material in the apertures corresponding to the contacts to the source/drain and gate stack structures; (f) forming a plurality of contacts to the source/drain and gate stack structures by depositing a conductive material in the lined apertures corresponding to the contacts to the source/drain and gate stack structures; (g) forming spaces between the contacts to the source/drain and gate stack structure by removing the sacrificial interlayer dielectric material; (h) selectively removing the contact etch stop liner and the oxide spacers; (i) selectively removing the nitride spacers; (j) forming voids between the contacts and the gate stack structure by depositing a non-conformal oxide, or a low dielectric material, in the spaces between the contacts and the gate stack structure; and (k) planarizing the non-conformal oxide, or low dielectric material, using chemical mechanical polishing.