Patent ID: 7990757
Filing Date: 2011-08-02
Classification: G11C,H01L

Abstract:
1. A method of operating a memory circuit having: a plurality of bit line structures comprising true and complementary bit lines; a plurality of word line structures comprising READ and WRITE word lines; and a plurality of cells selectively coupled to a corresponding one of said bit line structures under control of a corresponding one of said word line structures, each of said cells in turn comprising: said method comprising the steps of: activating said READ word line but not said WRITE word line during a READ operation for a given one of said cells, so that said first and second access devices of said given one of said cells operate in a single-gate mode while said double-gate pull-down devices of said given one of said cells operate in a double gate mode; and activating both said READ word line and said WRITE word line during a WRITE operation for said given one of said cells, so that said first and second access devices of said given one of said cells operate in a double-gate mode.