Patent ID: 6437618
Filing Date: 2002-08-20
Classification: H03L

Abstract:
A delay locked loop for use in a semiconductor memory device, comprising:an input circuit for receiving an external clock signal and producing a clock input signal; a delay monitoring circuit for receiving a clock output signal to monitor a time delay of the clock output signal relative to the clock input signal; a phase detection circuit for receiving the clock input signal of the input circuit and an output signal of the delay monitoring circuit, and for determining a difference in phase between the clock input signal and the output signal of the delay monitoring circuit to produce a shift control signal; a shift register for controlling the adjustment of the time delay based on the shift control signal from the phase detection circuit, the shift register having a ring configuration in order than an output of the shift register is fed back to its input; a digital delay line for adjusting the time delay based on an output signal from the shift register, the digital delay line having a ring configuration in order that an output of the digital delay line is fed back to its input; a first counter for counting an output signal from the digital delay line; a second counter for counting a number of signals circulated via the ring configuration of the shift register; a comparing circuit for comparing an output of the first counter and an output of the second counter; and an output circuit for receiving an output signal from the digital delay line and an output signal from the comparing circuit to selectively produce the clock output signal.