Patent ID: 6603698
Filing Date: 2003-08-05
Classification: G11C

Abstract:
A memory device, comprising:an address decoder coupled to an address bus; a read/write circuit coupled to a data bus; a control circuit coupled to a control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array storing dynamic data; and a refresh controller coupled to the memory-cell array, control circuit and address decoder for controlling a refresh rate of the dynamic data, the refresh controller being adapted to receive a supply voltage and including a refresh oscillator that generates a refresh clock signal having a frequency that is a function of a bias voltage, the refresh controller operable in a normal mode when the magnitude of the supply voltage is greater than a minimum value to apply a substantially constant bias voltage to the refresh oscillator and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a first refresh rate having a value determined by the frequency of the refresh clock signal, and the refresh controller operable in a low-power mode when the magnitude of the supply voltage is less than or equal to the minimum value to vary the bias voltage as a function of the magnitude of the supply voltage and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a second refresh rate having a variable value that is a function of the frequency of the refresh clock signal.