Patent ID: 6463013
Filing Date: 2002-10-08
Classification: G06F,H03L

Abstract:
A clock generating apparatus for receiving a main clock signal and a reset signal and outputting a plurality of clock signals, wherein the main clock signal is provided with m phase signals, the m phase signals are enabled in turn during the m periods of the main clock signals, each of the m phase signals is enabled in one period of the main clock signal, m is a integer, and the reset signal is enabled when the mth phase signal of the main clock signal is enabled, the clock generating apparatus comprising:a first divider for receiving the main clock signal and the reset signal, wherein after the first divider is reset by the reset signal, on condition that the first phase signal is enabled, the first divider divides the main clock signal and outputs a reference clock signal; a first phase-locked loop (PLL) for receiving the reference clock signal and a first feedback clock signal and outputting a first clock signal; a second phase-locked loop (PLL) for receiving the reference clock signal and a second feedback clock signal and outputting a second clock signal; a second divider for receiving the reset signal and the first clock signal, wherein after the second divider is reset by the reset signal, on condition that the first phase signal is enabled, the second divider divides the first clock signal and outputs a third clock signal; a third divider for receiving the reset signal and the second clock signal, wherein after the third divider is reset by the reset signal, on condition that the first phase signal is enabled, the third divider divides the second clock signal and outputs a forth clock signal; a forth divider for receiving the reset signal and the third clock signal, wherein after the forth divider is reset by the reset signal, on condition that the first phase signal is enabled, the forth divider divides the third clock signal and outputs the first feedback clock signal; and a fifth divider for receiving the reset signal and the forth clock signal, wherein after the fifth divider is reset by the reset signal, on condition that the first phase signal is enabled, the fifth divider divides the forth clock signal and outputs the second feedback clock signal; wherein the frequency of the first feedback clock signal and the second feedback clock signal are the same as that of the reference clock signal, and the third clock signal, the forth clock signal, and the main clock signal are in phase alignment.