Patent ID: 9207944
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. A method for managing thread execution in a processor, the method comprising: fetching a first multiple of instructions using multiple fetch queues, each instruction handling a first number of bits, from an instruction cache in a processor designed to handle a second multiple of threads of a second number of bits in size, where the first multiple is greater than the second multiple and the second number of bits is greater than the first number of bits; decoding the first multiple of instructions received from the fetch queues; dividing the first multiple of instructions received from the fetch queues into a second multiple of groups of instructions by issuing instructions to dispatch queues, each of the groups of instructions being instructions handling the first number of bits; processing each group of instructions through a respective integer processing pathway provided by the processor that processes operands of the second number of bits in size, wherein for each pathway the respective first number of bits are used to process instructions from the respective group in the pathway, and wherein each group of instructions are mapped to its respective integer pathway such that each pathway operates simultaneously and processes information independently in separate threads; and outputting the results of the processing of each group of instructions.