Patent ID: 7151399
Filing Date: 2006-12-19
Classification: G06F,H03L

Abstract:
1. A multi-level clock generating system, comprising: a first digital divider and multiplier for receiving a common clock signal and producing a first clock output, the first digital divider and multiplier comprises a first counter and a first decoder coupled in series with the first counter; a second digital divider and multiplier for receiving the common clock signal and producing a second clock output, the second clock output being at a different frequency than the first clock output, the second digital divider and multiplier comprises a second counter and a second decoder coupled in series with the second counter; and a third digital divider and multiplier for receiving the common clock signal and producing a third clock output, the third clock output being at a different frequency than the first clock output and the second clock output, the third digital divider and multiplier comprises a third counter and a third decoder coupled in series with the third counter.