Patent ID: 6333895
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A clock synchronous semiconductor memory device comprising:an internal power supply circuit for producing an internal power supply voltage at a level not higher than a level of an external power supply voltage from said external power supply voltage;a memory cell array having a plurality of memory cells;internal circuitry receiving the internal power supply voltage from said internal power supply circuit as one operation power supply voltage for operation, for selecting an addressed memory cell in said memory cell array and reading memory cell data from the selected memory cell;amplitude expanding circuitry receiving, in a form of complementary data signals, the memory cell data read by said internal circuitry for producing a pair of complementary internal read data signals of an amplitude of the level of said external power supply voltage received as an operation power supply voltage thereof, said amplitude expanding circuitry including a circuit for enlarging the amplitude of each of said complementary data signals;a transfer circuit receiving a voltage at a level not lower than said internal power supply voltage as one operation power supply voltage for operation, for transferring the internal read data signals outputted from said amplitude expanding circuitry in synchronization with an output clock signal;an output data latch circuit receiving a voltage not lower than said internal power supply voltage as one operation power supply voltage for operation, for latching the data outputted from said transfer circuit; andan output buffer receiving an output power supply voltage supplied independently of said external power supply voltage as operation power supply voltage for operation, for buffering the latch data of said output data latch circuit to output external read data onto an output node.