Patent ID: 7612580
Filing Date: 2009-11-03
Classification: H03K

Abstract:
1. A clock driving circuit for a PC architecture including: a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances, wherein the output lines are driven differentially at an output voltage lower than a supply voltage; a voltage node having a voltage node impedance, wherein the voltage node is maintained at substantially the output voltage; and a current sinking transistor that sinks current from the voltage node, wherein the current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor; a current sourcing transistor that supplies current to the voltage node, wherein the drain of the current sourcing transistor is maintained at a reference voltage that is lower than the supply voltage; wherein the impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.