Patent ID: 6256604
Filing Date: 2001-07-03
Classification: G11C,Y10S

Abstract:
A semiconductor chip comprising:a memory macro; anda logic section, wherein the memory macro comprises a control block including an address buffer circuit for generating an internal address signal in response to an external address signal inputted from the logic section and a switch circuit for fixing a portion of the internal address signal at a predetermined value, at least one memory array block having a plurality of data lines, and an input/output data buffer block for outputting data from a memory cell of the at least one memory array block through the data lines to the logic section, and whereinthe memory macro further comprises a plurality of memory array power source driver blocks each corresponding to a predetermined number of memory array blocks, each of the memory array power source driver blocks comprising an internal power source generating circuit for receiving an external power source voltage and generating an internal power source voltage which drives a memory cell array of the memory array block.