Patent ID: 7064395
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A semiconductor device comprising a memory cell including a first inverter including a first load transistor and a first driver transistor; and a second inverter including a second load transistor and a second driver transistor, the semiconductor device further comprising: a first gate interconnection formed over a semiconductor substrate and including a gate electrode of the first load transistor and a gate electrode of the first driver transistor; an insulation film formed over the first gate interconnection and having a first groove-shaped opening formed in the first groove-shaped opening integrally exposing the first gate interconnection, one of source/drain diffused layer of the second load transistor and one of source/drain diffused layer of the second driver transistor; and a first contact layer buried in the first groove-shaped opening, wherein the semiconductor device further comprises a second gate interconnection formed over the semiconductor substrate and including a gate electrode of the second load transistor and a gate electrode of the second driver transistor, and a second groove-shaped opening is formed in the insulation film, the second groove-shaped opening integrally exposing the second gate interconnection, one of source/drain diffused layer of the first load transistor and one of source/drain diffused layer of the first driver transistor, and a second contact layer is buried in the second groove-shaped opening.