Patent ID: 6064077
Filing Date: 2000-05-16
Classification: H01L

Abstract:
An integrated circuit device, comprising:a substrate having a doped region therein, said doped region having a first doping level;an epitaxial silicon region overlying the doped substrate region, said epitaxial silicon region having a second doping level that is less than said first doping level;a gate insulating layer and gate electrode overlying the epitaxial silicon region, wherein a channel region is formed under the gate electrode in said epitaxial silicon region;sidewall insulating regions disposed alongside said gate electrode;lightly doped source/drain regions in said epitaxial silicon region and said substrate underneath said sidewall insulating regions and adjacent the channel region;highly doped source/drain regions in said doped substrate region and said epitaxial silicon region adjacent the lightly doped source/drain regions, each of said highly doped source/drain regions extending from an upper surface of said epitaxial silicon region into said doped substrate region; anda threshold adjust impurity region within the channel region.