Patent ID: 8176461
Filing Date: 2012-05-08
Classification: G06F

Abstract:
1. A method for determining a design-specific timing specification for elements of a target device, comprising: inputting a placed-and-routed circuit design for a target device; inputting a timing specification of delays for elements in different regions of the target device; inputting an expected timing yield corresponding to the timing specification for a plurality of the target device; wherein the expected timing yield is a first proportion of a total number of the plurality of the target device having all elements that satisfy the timing specification; determining with a programmed processor a design-specific timing yield for the placed-and-routed circuit design as a function of amounts by which the delays of the timing specification are less than required delays of paths of the design; wherein the design-specific timing yield is an expected second proportion of a total number of the plurality of the target device that, when configured with the circuit design, have all elements satisfying the timing specification; selecting a path of the circuit design that uses elements in a first one of the regions; and reducing respective delays of a first set of one or more elements in the timing specification by respective amounts that maintain the design-specific timing yield at a level greater than or equal to the expected timing yield to produce a design-specific timing specification, the one or more timing elements being on the selected path in the first region.