Patent ID: 6204195
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A process for preventing overpolishing during CMP, comprising:providing means for measuring polishing rate during CMP;providing a dielectric layer having a upper surface;coating said upper surface with a polysilicon layer;patterning and etching the polysilicon layer thereby forming a step on the upper surface of the dielectric layer;coating said upper surface and said patterned polysilicon layer, including the step, with a layer of a hard dielectric material;depositing a planarizing layer on said layer of hard material;heating said planarizing layer to a temperature sufficient to cause reflow, thereby forming a planar top surface;by means of CMP, etching the planar top surface while measuring the polishing rate; andterminating CMP when said polishing rate is measured to have decreased by a preset amount.