Patent ID: 8501574
Filing Date: 2013-08-06
Classification: G11C,H01L

Abstract:
1. A method of manufacturing resistive memory device, comprising: forming a first implanted stacked structure in a substrate, wherein the first implanted stacked structure has a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers of the second implanted stacked structures are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures that are arranged in the form of a matrix, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers in accordance with the third implanted stacked structures and electrically coupled to the third impurity diffusion layers; forming a patterned photo-resist layer on the first insulating layers, the second insulating layers and the memory material layers, wherein the patterned photo-resist layer exposes some of the memory material layers; etching the exposed memory material layers; and after the step of forming the patterned photo-resist layer and the step of etching the exposed memory material layers, forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.