Patent ID: 6696724
Filing Date: 2004-02-24
Classification: H01L

Abstract:
A semiconductor device comprising in a semiconductor substrate containing a first dopant type, a first non-volatile memory cell for storing a bit, comprising a first drain region in said substrate, a first floating gate, a first control gate, a first thin gate isolation layer, and an insulating layer, said insulating layer being positioned on top of said first floating gate, said first control gate being positioned on top of said insulating layer, said first floating gate being positioned on top of said first thin gate isolation layer, and further comprising a first access transistor for controlling access to said first non-volatile memory cell,wherein said semiconductor device comprises a buried layer in said substrate which contains both a second dopant type and a first source region, said first access transistor is formed in a first trench on said substrate, said first trench extending substantially from said first source region to said surface of said substrate, said first trench being adjacent to said first floating gate and directed in a first direction parallel to said surface of said substrate.