Patent ID: 6159851
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises:forming a first dielectric layer on a substrate;forming a first patterned metal layer having gaps on the first dielectric layer, wherein the first patterned metal layer comprises a first metal feature with an upper surface and side surfaces;forming a second dielectric layer on the first patterned metal layer;etching to:form a through-hole having an internal surface in the second dielectric layer;expose a portion of the upper surface of the first metal feature; andexpose, and etch to form an undercut concave portion in, a side surface of the first metal feature;depositing a layer of barrier material by chemical vapor deposition to line the:internal surface of the through-hole;exposed portion of the upper surface of the first metal feature; andundercut concave portion of the first metal feature; anddepositing a conductive material in the lined opening filing the through-hole and forming a borderless via.