Patent ID: 6598190
Filing Date: 2003-07-22
Classification: G11C

Abstract:
A memory device compiler arranged in a computer aided design environment having a central processing unit, a keyboard, a monitor, a mass storage device wherein the central processing unit is in communication with the keyboard, the monitor and the mass storage device comprising:a plurality of standard memory cells arranged in a library stored on the mass storage device, accessible by the central processing unit, and viewable on the monitor; a memory compiler algorithm stored on the mass storage device, accessible by the central processing unit and responsive to input commands from a user via the keyboard to define a physical configuration of a memory representation such that the memory representation is composed of a content-addressable-memory cell and memory array formed of a subset of cells of the plurality of standard memory cells of the library; and a built in self test structure capable of addressing and testing both the memory array and the content-addressable memory cell.