Patent ID: 6822903
Filing Date: 2004-11-23
Classification: B82Y,G11C

Abstract:
A method for programming a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode of anode regions being configured to inject charge to the other region when forward biased, said method comprising:driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line; and driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the first array line; then driving the first array line to an unselected bias voltage for the first array line; and driving the second array line to an unselected bias voltage for the second array line wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.