Patent ID: 7528405
Filing Date: 2009-05-05
Classification: G11C,H01L

Abstract:
1. A conductive memory device comprising: a bottom electrode including a top face; a top electrode located above the bottom electrode and including a bottom face having a second surface area; and a multi-resistive state element sandwiched between the bottom electrode and the top electrode and including a bottom face and a top face, the top face having a fourth surface area, the second surface area is smaller than the fourth surface area, the multi-resistive state element's bottom face being in contact with the bottom electrode's top face, the multi-resistive state element's top face being in contact with the top electrode's bottom face, wherein the bottom electrode, the top electrode and the multi-resistive state element each have sides that are adjacent to their faces, and wherein the sides are at least partially covered by a sidewall layer.