Patent ID: 8507333
Filing Date: 2013-08-13
Classification: H01L

Abstract:
1. A method of forming a device, said method comprising: forming multiple gates on a semiconductor layer to define channel regions in said semiconductor layer for multiple planar field effect transistors; after said forming of said gates, forming source/drain regions within said semiconductor layer on opposing sides of each of said channel regions such that each portion of said semiconductor layer between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor; forming, over said gates and on a top surface of said semiconductor layer at opposing ends and between adjacent gates, a conformal conductive layer that is electrically isolated from said gates and that physically contacts said source/drain regions such that said conformal conductive layer is electrically connected to said source/drain regions; and after said forming of said conformal layer, forming a blanket interlayer dielectric on said conformal conductive layer over said gates and said top surface of said semiconductor layer at said opposing ends and between said adjacent gates.