Patent ID: 6031771
Filing Date: 2000-02-29
Classification: G11C,H01L

Abstract:
A read-only memory device, comprising:an array of read-only memory cells having a memory cell structure, the array including word lines and bit lines, the read-only memory cells arranged in a plurality of rows coupled to respective word lines in the array and in a plurality of columns coupled to respective bitlines in the array;an additional row or column of electrically programmable memory cells having a memory cell structure different than the memory cell structure of the array of read-only memory cells, the electrically programmable memory cells in the additional row or column associated with at least one of a word line and a bit line in the array;a row or column decoder, coupled to the word lines and bit lines in the array of read-only memory cells, responsive to addresses corresponding to rows or columns in the array for selecting addressed rows or columns;control circuitry including a programmable store to identify a defective row or column in the array to be replaced by the additional row or column, which in response to an address corresponding to the defective row or column, couples the additional row or column in place of the defective row or column to said associated at least one of a word line and a bit line; andcircuitry providing access to the additional row or column for programming the additional row or column with data of the defective row or column.