Patent ID: 6754785
Filing Date: 2004-06-22
Classification: G06F,Y10S

Abstract:
A memory system for use in a data network, the memory system comprising:a memory matrix unit having a memory matrix capable of storing data therein; a non-volatile storage unit capable of storing data therein; a management unit configured to couple the data network to the memory matrix unit via a primary network interface and to the non-volatile storage unit via a secondary network interface, the management unit further configured to enable the data network to access the memory matrix during normal operation to provide a primary memory, and to stream data from the data network to the non-volatile storage unit to provide a backup memory; wherein the memory matrix comprises: a plurality of Random Access Memory (RAM) devices each capable of storing data therein, the memory devices arranged in a plurality of banks each having a predetermined number of memory devices; a memory controller coupled to each of the banks and capable of accessing the memory devices; and a cache coupled to the memory controller, the cache having stored therein one or more copies of a Data Allocation Table (DAT) adapted to describe data stored in the memory devices; and wherein the management unit further comprises: a primary processor coupled to the memory controller of a memory matrix; a read-only memory (ROM) device coupled to the Primary processor, the ROM device having stored therein an initial boot sequence to boot the management unit; a memory device coupled to the primary processor to provide a buffer memory to the primary processor; a switch coupled to the primary processor through a network interface controller and through the network to a plurality of data Processing systems; one or more secondary processors coupled to the memory controller; a second ROM device coupled to each secondary processor, the second ROM device having stored therein an initial boot sequence to boot the secondary processor; a second memory device coupled to each secondary processor to provide a buffer memory to the secondary processor; a wireless network unit coupled to the primary processor through a bus; and a security processor coupled to the primary processor through a bus.