Patent ID: 7383409
Filing Date: 2008-06-03
Classification: G06F

Abstract:
1. A multi-processor system that conforms to a cache coherency protocol, the system comprising: a processor that transmits a source request for a data fill associated with a cache line in response to a cache miss, the processor having a processor pipeline that executes program instructions with data from at least one of a plurality speculative fills received from two or more other processors of the multi-processor system in response to a source request, the speculative fills being copies of a requested data fill that have undetermined coherency states; and a non-retired store cache that retains non-retired store data based on program instructions to store data into a data cache associated with the processor, the non-retired store data being written to the data cache if data of a speculative fill of the plurality of speculative fills associated with the non-retired store data is determined to be coherent, the processor pipeline initiating a the source request in response to a cache miss if a cache line in the data cache is not available before the non-retired store data is written to the data cache.