Patent ID: 8446199
Filing Date: 2013-05-21
Classification: G11C

Abstract:
1. A duty cycle correction (DCC) circuit, comprising: a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal; a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts; a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal; and a duty cycle correcting unit configured to output the output clock by driving an input clock with a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code, wherein the duty signal is activated when the high duration of the output clock is longer than the low duration of the output clock, and the duty signal is inactivated when the high duration of the output clock is shorter than the low duration of the output clock.