Patent ID: 6337806
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A semiconductor device comprising:a dynamic random access memory (DRAM) cell array capable of inputting or outputting MÃ—N data signals in parallel; a logic circuit having a control function; and a memory unit connected between the DRAM cell array and the logic circuit, wherein the memory unit transmits or receives MÃ—N data signals to or from the DRAM cell array and transmits or receives M data signals to or from the logic circuit, in response to an address signal, wherein the memory unit comprises: at least M memory blocks each for receiving N data signals from the DRAM cell array and transmitting at least one data signal to the logic circuit, and for receiving at least one data signal from the logic circuits and transmitting N data signals to the DRAM cell array; and a write/read word line driver connected to the at least M memory blocks, wherein the write/read word line driver decodes the address signal, selectively activates operations that write the data signals input from the DRAM cell array and the logic circuit to the memory blocks, and selectively activates operations that read of each memory block to transmit the data signals to the DRAM cell and the logic circuit.