Patent ID: 7345933
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. A circuit that generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module, comprising: a delay module that receives the start burst signal and that generates a delayed start burst signal; an enable signal generator that receives the delayed start burst signal and that generates an enable signal; and a first circuit that generates the qualified data read strobe signal based on the enable signal and the bidirectional data strobe signal, wherein the delay module is part of an application specific integrated circuit (ASIC) and comprises a circuit board trace having a length L that is substantially equal to a sum of a first length of a first circuit trace carrying a clock signal between the DDR memory control module and a DDR memory and a second length of a second circuit trace carrying the bidirectional data strobe signal between the DDR memory and the DDR memory controller.