Patent ID: 7545701
Filing Date: 2009-06-09
Classification: G11C

Abstract:
1. A sub-word line driving circuit, comprising: a first transistor configured to pre-charge a boost node to a first voltage in response to a main word line driving signal; a second transistor configured to boost the boost node to a second voltage in response to a sub-word line driving signal, and configured to provide the sub-word line driving signal to word line; a third transistor configured to provide the main word line driving signal to the word line in response to a third voltage that has a lower level than a logic “high” state of the sub-word line driving signal; a fourth transistor configured to pull down the word line when the sub-word line driving signal is disabled; and a control signal generating circuit configured to generate the third voltage when the sub-word line driving signal is enabled, the control signal generating circuit comprising: