Patent ID: 6310402
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A semiconductor device including a semiconductor chip having a central area, a peripheral area that surrounds said central area and four sides that bound said peripheral area, said semiconductor chip comprising:a main circuit region formed in the central area of said semiconductor chip;a plurality of input/output cells in said peripheral area of said semiconductor chip, wherein said input/output cells a re arranged in rows that are each parallel to a respective one of said four sides of said semiconductor chip, and each of said input/output cells has a width of a length n that extends in the direction in which the respective row extends;a plurality of pads in an exterior portion of said peripheral area of said semiconductor chip beyond said input/output cells, wherein said pads are arranged in rows that are parallel to respective rows of said input/output cells, and wherein a layout interval between the center of adjacent pads in each of said rows is a distance m; anda plurality of interconnections, each of which electrically connects one of said plurality of pads to one of said plurality of input/output cells.