Patent ID: 7026674
Filing Date: 2006-04-11
Classification: H01L

Abstract:
1. A semiconductor memory device having a capacitor which comprises a ferroelectric layer with the perovskite crystal structure which, being expressed by the general formula ABO 3 , contains lead (Pb) as the element A occupying lattice A and zirconium (Zr) and titanium (Ti) as the element B occupying lattice B, and a lower electrode and an upper electrode which are disposed to sandwich said ferroelectric layer; wherein said ferroelectric layer has, both on the side of said lower electrode and on the side of said upper electrode, a region each, in which a ratio of Zr to Ti (a Zr/Ti ratio) is equal to or greater than a Zr/Ti ratio of the central section of said ferroelectric layer in the direction of thickness, and the Zr/Ti ratio of at least one of the regions on the side of said lower electrode and on the side of said upper electrode is from 1.05 to 2.0 times the Zr/Ti ratio of said central section.