Patent ID: 8416598
Filing Date: 2013-04-09
Classification: G11C

Abstract:
1. An integrated circuit, comprising: at least one latch circuit comprising: input circuitry for setting the state of the at least one latch circuit; output circuitry for sensing the state of the at least one latch circuit; a first plate line coupled to the second plate of the first ferroelectric capacitor; a second plate line coupled to the second plate of the second ferroelectric capacitor; and plate line driver circuitry for applying low and high bias voltages to each of the second plates of the first and second ferroelectric capacitors to polarize the first and second ferroelectric capacitors to opposite polarization states, corresponding to the state of the latch circuit, and for biasing, in a test operation, a first bias voltage to the second plate of the first ferroelectric capacitor and a second bias voltage to the second plate of the second ferroelectric capacitor, the second bias voltage lower than the first bias voltage by a selected differential.