Patent ID: 6855978
Filing Date: 2005-02-15
Classification: H01L

Abstract:
1. A gate-contact structure comprising: a device isolation layer pattern at a semiconductor substrate, the device isolation layer pattern defining an active region; a gate electrode on the semiconductor substrate, the gate electrode crossing the device isolation layer pattern and the active region; a capping pattern on the gate electrode, the capping pattern having a first gate contact hole that exposes a predetermined region of the gate electrode; an interlayer insulation layer pattern covering the gate electrode and the capping pattern, the interlayer insulation layer pattern having a second gate contact hole that penetrates the first gate contact hole to expose a top surface of the gate electrode, the second gate contact hole having a width that is less than a width of the first gate contact hole; and a gate contact plug connected to the top surface of the gate electrode through the second gate contact hole.