Patent ID: 6913989
Filing Date: 2005-07-05
Classification: H01L,Y10S

Abstract:
1. An exposure method for manufacturing a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate comprising the steps of: forming a first pattern through exposure, said first pattern is partitioned by a plurality of device regions, in which each said device region a device group and a local interconnect are disposed, said device group including one or more semiconductor devices among said plurality of semiconductor devices and said local interconnect connecting said semiconductor devices included in said device group; and after forming said first pattern, forming a second pattern through exposure, said second pattern is partitioned by a routing region in which a global routing is disposed, said global routing connecting said device group disposed in each said device region to each other, wherein said global routing is disposed on said local interconnect, wherein said local interconnect is provided only within each said device region and said global routing is provided only within said routing region, wherein said routing region crosses each boundary between said plurality of device regions and is shifted from said plurality of device regions by a distance.