Patent ID: 6624522
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A semiconductor device package comprising a semiconductor device die having parallel top and bottom surfaces; said top surface having a first planar metallic electrode, said bottom surface having a solderable planar metal electrode; at least one solderable conductive layer formed on at least a first portion of said first planar metallic electrode, said at least one solderable conductive layer having an upper planar surface; a metal clip having a flat web portion and at least one peripheral rim portion extending from an edge of said flat web portion; said bottom surface of said web being electrically connected in surface to surface contact to said solderable planar metal electrode on the bottom surface of said die; said peripheral rim portion of said clip being extended over and spaced from an edge of said die and terminating in a clip rim surface which is in plane parallel to the plane of said upper planar surface of said at least one solderable conductive layer and being insulated therefrom, whereby said clip rim surface and said at least one solderable conductive layer are mountable to metallized patterns on a support surface, wherein a plurality of spaced solderable planar metal post-shaped electrodes are connected to said planar metallic electrode and all terminate in the plane of said upper planar surface.