Patent ID: 7611943
Filing Date: 2009-11-03
Classification: H01L

Abstract:
1. A process for making an integrated circuit comprising a PMOS transistor with a gate and an NMOS transistor with a gate, the process comprising: forming a gate dielectric relative to a semiconductor region; forming a first metal layer adjacent the gate dielectric, wherein forming a precursor layer comprising silicon adjacent the first metal layer; doping the precursor layer with a first dopant in a first area corresponding to the NMOS transistor; doping the precursor layer with a second dopant, different than the first dopant, in a second area corresponding to the PMOS transistor; forming a second metal layer in a fixed position relative to the doped precursor layer; and after the doping steps, forming a silicide by siliciding the second metal layer with the doped precursor layer to totally consume the doped precursor layer and drive dopants from the doped precursor layer into and to be retained in the first metal layer; wherein in response to the siliciding step: