Patent ID: 6487108
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A magneto-resistive random access memory (MRAM) configuration, comprising:a memory chip, containing: lines including bit lines and word lines; a memory cell array subdivided into a plurality of memory cell blocks and connected to said lines running through said memory cell array, said bit lines and word lines running through said memory cell blocks have input sides and output sides with regards to each of said memory cell blocks; and a voltage stabilizer device receiving a supply voltage, said voltage stabilizer device connected to at least one of said bit lines and said word lines, said at least one of said bit lines and said word lines connected to said voltage stabilizer device functioning as supply lines supplying fixed operating voltages to said memory cell array, a voltage drop occurs between said input sides of said supply lines and said output sides of said supply lines running through each of said memory cell blocks, said voltage stabilizer device having a plurality of voltage stabilizers and each of said memory cell blocks is respectively connected to one of said voltage stabilizers, said voltage stabilizers connected to said supply lines and supplying said memory cell blocks with the fixed operating voltages that differ from one another in each case.