Patent ID: 7890900
Filing Date: 2011-02-15
Classification: G11C

Abstract:
1. An apparatus, comprising: an electronic design tool configured with at least one of logic, software, and a combination of software and logic, that is programmed to perform an algorithm to find an optimal configuration of memory instances to be fabricated with built-in repair components and memory instances that are non-repairable which provides a highest number of good chip dies per wafer, where the algorithm is linear with respect to a number of memory instances used in a given integrated circuit design, and the electronic design tool determines an amount of memory instances to be fabricated with built-in repair components as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design to achieve the highest number of good chip dies per silicon wafer for a given defect density and die area, and where the software portions of the electronic design tool are stored on a computer readable storage device and executable by a computing device; a threshold calculator to calculate a threshold-value that-is-expressed-in-area-units for each memory instance and comparing the threshold-value by a comparator to both a maximum and minimum die area values which are representative of the actual area occupied by every memory instance in that design plus an area occupied by the logic components in that design; a good die per wafer calculator to calculate an amount of good dies produced per fabricated silicon wafer for each instance of the design starting with all of the memory instances that are projected to be fabricated as repairable via the results of the comparison by the comparator of the threshold-value to the minimum die area value, and then recalculated for each design instance all the way up to all of the memory instances that are projected to be fabricated as repairable based on results of the comparison by the comparator of the threshold-value to the maximum die area value; and where the electronic design tool presents the highest number of projected good chip dies per fabricated silicon wafer as an optimal design of the integrated circuit design with its subset of the memory instances being chosen to be populated as memory instances having built-in repair components as well as the remaining amount of memory instances to be fabricated without any built-in repair components.