Patent ID: 8159276
Filing Date: 2012-04-17
Classification: H03L

Abstract:
1. A digital phase locked loop circuit, comprising: at least one input for receiving a reference signal; a phase frequency detector for determining a phase difference between the reference signal and a feedback signal and generating a digital representation of an amount of the phase difference between the reference signal and the feedback signal; a digital filter circuit for generating a counter value responsive to the digital representation of the phase difference; a counter circuit for generating an output pulse including coarse phase information and fine phase information each time the counter circuit goes below a predetermined value, wherein an initial counter value is established responsive to the counter value; wherein the feedback signal is established responsive to the coarse phase information; an analog phase interpolator for generating a synchronization signal responsive to the coarse phase information and the fine phase information; and an output for providing the synchronization signal to a switching voltage regulator to enable generation of a PWM signal at the switching voltage regulator.