Patent ID: 6573773
Filing Date: 2003-06-03
Classification: H03K

Abstract:
A Single Event Upset (SEU) resistant latch circuit SERT-1 comprising:(a) a first circuit module having a first group of four cross-coupled p-channel (PMOS) transistors wherein a first and second p-channel transistor of the first group are coupled in series with a single first n-channel transistor such that the first p-channel transistor from the first group is coupled more closely to a positive voltage supply and a third and fourth p-channel transistor from the first group are coupled in series with a single second n-channel transistor such that the third p-channel transistor from the first group is coupled more closely to the positive voltage supply and further wherein the gate of the first p-channel transistor of the first group is connected to the gate of the fourth p-channel of the first group and the gate of the second p-channel transistor of the first group is connected to the gate of the third p-channel of the first group, and having two output terminals y0, y1, each output terminal having a low impedance logic 1 state, a low impedance logic 0 state, and a high impedance state Z, wherein the first and second n-channel (NMOS) transistors are connected directly to a ground potential; and (b) a second circuit module having a second group of four cross-coupled p-channel (PMOS) transistors wherein a first and second p-channel transistor of the second group are coupled in series with a single third n-channel transistor such that the first p-channel transistor from the second group is coupled more closely to a positive voltage supply and a third and fourth p-channel transistor from the second group are coupled in series with a single fourth n-channel transistor such that the third p-channel transistor from the second group is coupled more closely to the positive voltage supply and further wherein the gate of the first p-channel transistor of the second group is connected to the gate of the fourth p-channel of the second group and the gate of the second p-channel transistor of the second group is connected to the gate of the third p-channel of the second group and the second group is also coupled to the two output terminals of the first circuit module, and having two output terminals y2, y3 coupling to the four cross-coupled p-channel (PMOS) transistors of the first circuit module, each output terminal having a low impedance logic 1 state, a low impedance logic 0 state, and a high impedance state Z.