Patent ID: 7519090
Filing Date: 2009-04-14
Classification: H04J

Abstract:
1. A very high speed arbitrary number of multiple signal multiplexer circuit comprising: an overlapped data generator, which takes in n-bits of parallel data on an input data bus and outputs even and odd signals to a selective mux, said selective mux, which receives even and odd internal data bits from said overlapped data generator and which outputs one single bit primary output, a phase locked loop/delay locked loop, PLL/DLL, which receives a set of n-primary input phase clocks and which outputs n evenly-phase-distributed clock signals to a data select signal generator, and said data select signal generator, which receives said n evenly-phase-distributed clock signals and which generates a ten-bit data select signal bus wherein said overlapped data generator, said selective mux, said phase locked loop/delay locked loop, and said data select generator are used to facilitate the time domain design of said multiple signal multiplexed circuit.