Patent ID: 9160372
Filing Date: 2015-10-13
Classification: H03M,H04L

Abstract:
1. A bit interleaving method for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme, including a repeat-accumulate quasi-cyclic low-density parity check coding scheme, the bit interleaving method comprising: a cyclic block permutation step of applying a cyclic block permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the cyclic blocks in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks; a bit permutation step of applying a bit permutation process to the codeword after the cyclic block permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; and a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, wherein N is a multiple of M, the bit permutation rule defines the reordering of the bits of the codeword after the cyclic block permutation process, such that the Q bits in each of the N cyclic blocks are each allocated to a bit of an identical bit index in Q constellation words and the Q constellation words are each made up of one bit in each of M cyclic blocks, the M cyclic blocks being common to the Q constellation words, and the bit index of the bit in each of the constellation words to which the bits in each of the cyclic blocks are allocated is determined in accordance with the cyclic block permutation rule.