Patent ID: 8569089
Filing Date: 2013-10-29
Classification: B81B,B81C,B82Y,H01L

Abstract:
1. A method of forming a semiconductor device, comprising: forming a bottom gate electrode in a substrate; forming a first insulating layer over the substrate covering the bottom gate electrode; etching a first cavity in the first insulating layer, wherein the first cavity is aligned with the bottom gate electrode; filling the first cavity with a second layer of insulating material; planarizing the second layer of insulating material using the first insulting layer as an etch stop to form a first planarized surface, forming a graphene layer on the first planarized surface; forming one or more sense electrodes on the graphene layer, wherein the one or more sense electrodes are disposed on the graphene layer adjacent to the first cavity; forming a third insulating layer over the graphene layer and covering the one or more sense electrodes; etching a second cavity in the third insulating layer, wherein the second cavity is aligned with the first cavity; filling the second cavity with a fourth layer of insulating material; planarizing the fourth layer of insulating material stopping on the third insulting layer to form a second planarized surface; forming a fifth insulating layer over the second planarized surface, forming a top gate electrode over the fifth insulating layer, the top gate electrode aligned with the first and second cavities; dicing the substrate to form an individual semiconductor nano-structure; removing the second and fourth layers of insulating material from the first and second cavities, respectively, to form first and second open cavities, and mounting an elongated nano-structure to a portion of the graphene layer that is suspended between the first and second open cavities.