Patent ID: 7013368
Filing Date: 2006-03-14
Classification: G06F

Abstract:
1. An arbitration apparatus comprising: a plurality of memory masters each outputting a request signal for requesting a memory use right; and a memory arbitration circuit for giving the memory use right to one of the memory masters selected from the memory masters which have output the request signals, wherein the memory masters each output signals that indicate access attributes to the memory when outputting the request signal, wherein when plural memory masters have output the request signals, the memory arbitration circuit gives the memory use right to a memory master selected from the memory masters based on the signals indicating the access attributes. wherein the memory arbitration circuit assigns low priority to a first memory master outputting the address signal indicating a first memory bank that is the same as the one that has been accessed up to that time, assigns high priority to a second memory master outputting the address signal indicating a memory bank different from the one that has been accessed up to that time and, when only one memory master is given high priority, gives the memory use right to the one memory master.