Patent ID: 6825699
Filing Date: 2004-11-30
Classification: H03K

Abstract:
A buffer comprising:a) an input node; b) an output node; a first transistor comprising a first transistor first node connected to said input node, a first transistor second node connected to said output node, and a first transistor control node; a second transistor comprising a second transistor first node connected to a first predetermined voltage node, a second transistor second node connected to said first transistor control node, and a second transistor control node connected to said first predetermined voltage node; a capacitive element connected between said second transistor first node and said output node; and a third transistor comprising a third transistor first node connected to said second transistor, second node, a third transistor second node connected to a second predetermined voltage node, and a third transistor control node connected to a third preselected voltage node.