Patent ID: 6341084
Filing Date: 2002-01-22
Classification: G11C

Abstract:
A magnetic random access memory circuit comprising:a memory cell array having a plurality of sense lines, a plurality of word lines intersecting said plurality of sense lines, a number of magneto-resistive elements located at intersections between said plurality of sense lines and said plurality of word lines, each of said magneto-resistive elements being connected between one sense line and one word line; a plurality of capacitors of the number corresponding to the number of said plurality of sense lines, said plurality of capacitors being previously charged to a high voltage before a reading operation is carried out, each of said plurality of capacitors being connected to a corresponding sense line of said plurality of sense lines through a voltage drop means so that a voltage lower than said high voltage charged in said capacitors is applied to said plurality of sense lines; and means for equalizing the potential of all said plurality of sense lines and all not-selected word lines of said plurality of word lines and for grounding a selected word line of said plurality of word lines so that an electric charge previously stored in said capacitor connected through said voltage drop means to a selected sense line is discharged through said voltage drop means, said selected sense line, a selected magneto-resistive element, and said selected word line, whereby information stored in said selected magneto-resistive element is read out by a potential on said capacitor.