Patent ID: 9087173
Filing Date: 2015-07-21
Classification: G06F

Abstract:
1. A method comprising: providing a device model for a semiconductor device, wherein the device model includes a plurality of sliced gate regions representing a non-rectangular gate structure of the semiconductor device; calibrating the device model against a predictive technology model (PTM); after calibrating the device model, estimating an impact of narrow width related edge effects on the calibrated device model by performing two-dimensional (2D) and three-dimensional (3D) device simulations; after estimating the impact of narrow width related edge effect on the calibrated device model, identifying a plurality of location-dependent weighting parameters for accurate extraction, after the identifying of the plurality of location-dependent weighting parameters, generating an accurate device model, by a computer, for the semiconductor device by applying the plurality of location-dependent weighting parameters to the calibrated device model,