Patent ID: 6061707
Filing Date: 2000-05-09
Classification: G06F

Abstract:
An apparatus for generating an end-around carry for an end-around carry adder in a floating-point pipeline within a computer system, wherein said floating-point pipeline includes a first operand, a second operand, and a third operand, said apparatus comprising:shift-comparison logic for providing a shift-count signal in response to exponent bits of each of said first, second, and third operands;sign-comparison logic for providing an effective operation signal in response to a sign bit of each of said first, second, and third operands; anda logic gate, coupled to said shift-comparison logic and said sign-comparison logic, for combining said shift-count signal and said effective operation signal with a carry-out signal generated by said end-around carry adder to provide an end-around carry signal for said end-around carry adder.