Patent ID: 6628489
Filing Date: 2003-09-30
Classification: H02J

Abstract:
A low drop-out voltage regulator circuit with battery reversal protection, the circuit comprising:first and second input terminals for receiving a power supply voltage; an output terminal for outputting a regulated voltage; a voltage reference circuit having first and second supply terminals and an output terminal, where the second supply terminal of the voltage reference circuit is coupled to the second input terminal; an error amplifier having first and second supply terminals, first and second input terminals, and an output terminal, where the second supply terminal of the error amplifier is coupled to the second input terminal, the first input terminal of the error amplifier is coupled to the output terminal of the voltage reference circuit, and the second input terminal of the error amplifier is coupled to the output terminal through a resistive divider; a power transistor having a control terminal, a bulk terminal, and first and second current terminals, where the control terminal of the power transistor is coupled to the output terminal of the error amplifier, and the second current terminal of the power transistor is coupled to the output terminal; a first transistor having a control terminal and first and second current terminals, where the first current terminal of the first transistor is coupled to the first input terminal and the second current terminal of the first transistor is coupled to the first supply terminal of the voltage reference circuit and the first supply terminal of the error amplifier; a resistor coupled between the control terminal of the first transistor and the second input terminal; and a second transistor having a control terminal and first and second current terminals, where the control terminal is coupled to the first input terminal, the bulk terminal of the second transistor is coupled to the output terminal, the first current terminal of the second transistor is coupled to the output terminal, and the second current terminal of the second transistor is coupled to the control terminal of the first transistor; and a third transistor having a control terminal and first and second current terminals, the control terminal of the third transistor being coupled to the second current terminal of the second transistor, the first current terminal of the third transistor being coupled to the first input terminal, and the second current terminal of the third transistor being coupled to the bulk terminal of the power transistor.