Patent ID: 6525407
Filing Date: 2003-02-25
Classification: H01L,Y10T

Abstract:
An integrated circuit package, comprising:a semiconductor chip having a first and a second side, the first side defining an inner region and a peripheral region, the inner region being surrounded by the peripheral region; an interposer having a substantially similar coefficient of thermal expansion to the semiconductor chip, the interposer being configured to bond to the inner region of the semiconductor chip; a dielectric region surrounding the interposer, the dielectric region accommodating a partially elastic dielectric medium; and a plurality of posts extending transversely through the dielectric region, the posts having first and second ends, the first ends being configured to be attached to the peripheral region of the first side of the semiconductor chip, the second ends being configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.