Patent ID: 6046103
Filing Date: 2000-04-04
Classification: H01L

Abstract:
A method of fabricating a borderless contact opening, to a portion of an active device region, of a semiconductor substrate, comprising the steps of:forming an isolation region in said semiconductor substrate, and forming a transfer gate transistor, comprised of: a gate structure, on an underlying gate insulator layer, insulator spacers on sides of said gate structure, and a source/drain region, located between said isolation region and said gate structure, overlaid with a metal silicide layer;depositing an insulator stop layer;depositing a thick insulator layer;forming said borderless contact opening, in said thick insulator layer, and in said insulator stop layer, exposing a portion of said metal silicide layer, located on said source/drain region, and exposing a portion of said isolation region, via use of a first anisotropic RIE procedure, for said thick insulator layer, using CHF.sub.3 as an etchant, with an etch rate ratio of said thick insulator layer to said stop layer, of about 7 to 1, and via a second anisotropic RIE procedure, for said insulator stop layer, using CO--O.sub.2 --C.sub.2 F.sub.6 as an etchant; andforming a metal structure in said borderless contact opening, overlying, and contacting a portion of said metal silicide layer, overlying said source/drain region.