Patent ID: 8233323
Filing Date: 2012-07-31
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor storage device comprising: a plurality of memory strings each including a plurality of memory transistors connected in series; a plurality of first selection transistors each having one end connected to one end of a respective one of the memory strings, each of the first selection transistors being conductive when selecting one of the memory strings; a plurality of second selection transistors each having one end connected to the other end of a respective one of the memory strings, each of the second selection transistors being conductive when selecting one of the memory strings; and a control circuit performing an erase operation to erase data from a selected one of the memory transistors included in the selected one of the memory strings connected to one end of a selected one of the first selection transistors, each of the memory strings comprising: each of the first selection transistors comprising: each of the second selection transistors comprising: the second semiconductor layer having a p-type layer in contact with one end of the columnar portion, and an n-type layer located on the p-type layer, the third semiconductor layer having an n-type layer in contact with the other end of the columnar portion, a p-type layer located below the n-type layer, and another n-type layer located below the p-type layer, the control circuit applying a first voltage to the other end of the selected one of the first selection transistors, then applying a second voltage to the gate of the selected one of the first selection transistors, and then causing the memory transistors other than the selected memory transistor to turn on, and also applying a third voltage to the gate of the selected memory transistor, such a potential difference between the first voltage and the second voltage causing a first current flowing from the n-type layer of the second semiconductor layer located near the first gate insulation layer into the p-type layer of the second semiconductor layer, and such a potential difference between the first voltage and the third voltage causing holes generated by the first current to be injected into the electric charge storage layer of the selected memory transistor.