Patent ID: 8890729
Filing Date: 2014-11-18
Classification: H03M

Abstract:
1. A time interleaving Analog-to-Digital Converter (ADC), comprising: a plurality of ADCs; a timing generator that generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and independently adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are equally spaced in time and occur at a rate of 1/N times a desired sampling rate, a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs, wherein the bandwidth of each of the plurality of ADC's is independently adjusted in conjunction with adjustment to the clock signals such that samplings of said input signal are equally spaced in time.