Patent ID: 7706484
Filing Date: 2010-04-27
Classification: G06F,H03K

Abstract:
1. A method for reducing electromagnetic interference in a clocked circuit, comprising the actions of: a. generating a base clock signal; b. generating a first copy of the base clock signal, a second copy of the base clock signal and a third copy of the base clock signal; c. transmitting the first copy of the base clock signal to a first output; d. comparing a first transition in the first copy of the base clock signal to a second transition in the second copy of the base clock signal; e. transmitting the second copy of the base clock signal to a second output when the first transition is not concurrent with the second transition and generating a delayed copy of the second copy of the base clock signal when the first transition is concurrent with the second transition; f. comparing the first transition in the first copy of the base clock signal to a third transition in the third copy of the base clock signal; g. transmitting the third copy of the base clock signal to an intermediate node when the first transition is not concurrent with the third transition and generating a delayed copy of the third copy of the base clock signal when the first transition is concurrent with the third transition; h. comparing a fourth transition in a signal at the second output to a fifth transition in a signal at the intermediate node; i. transmitting the signal at the intermediate node to a third output when the fourth transition is not concurrent with the fifth transition and generating a delayed copy of the signal at the intermediate node and transmitting the delayed copy of the signal at the intermediate node to the third output when the fourth transition is concurrent with the fifth transition.