Patent ID: 6649955
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A ferroelectric memory device comprising:a semiconductor substrate having a cell array region where at least one cell transistor is arranged and a peripheral circuit region where at least one peripheral circuit transistor is arranged; first, second, third, and fourth interlayer dielectric layers sequentially stacked on the cell array and peripheral circuit regions; a gate contact pad and source/drain contact pad respectively connected to a gate electrode and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer; a gate contact plug and source/drain contact plug respectively connected to the gate contact pad and the source/drain contact pad through the second interlayer dielectric layer; first via holes exposing the gate contact plug and the source contact plug through the third interlayer dielectric layer; and a first interconnection extending between the third and fourth interlayer dielectric layers, covering the sidewalls of the first via holes and being connected to at least one of the gate contact plug and the source/drain contact plug, wherein the first interconnection comprises a portion having a uniform thickness extending between the sidewall and a central opening in each first via hole.