Patent ID: 8381162
Filing Date: 2013-02-19
Classification: G06F

Abstract:
1. A method of adapting a layout of a standard cell of an integrated circuit comprising the steps of: identifying a current collection path in said standard cell, said current collection path configured to connect components within said standard cell to an output connection, wherein said current collection path is arranged to collect current from said components at a plurality of current collection points arranged along a length of said current collection path; determining, one or more computers, a maximum current location on said current collection path at which a maximum possible current flow in said current collection path will occur when said output connection is connected to said maximum current location, said maximum possible current flow being a sum of current contributions from said current collection points; determining a maximum width of said current collection path at said maximum current location such that said maximum width satisfies a minimum path width requirement with respect to said maximum possible current flow; and selectively sizing a local width of said current collection path at a selected distance from said maximum current location, said local width being less than or equal to said maximum width, such that said local width satisfies said minimum path width requirement with respect to a maximum local current that will occur at said selected distance, said maximum local current being a sum of said current contributions from those current collection points which contribute to said local current.