Patent ID: 6760876
Filing Date: 2004-07-06
Classification: G01R

Abstract:
A scan test interface comprising:a scan test interface register for storing information related to scan test operations; a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices; a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register; a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain; and a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain, wherein said scan test interface supports scan test operations on multiple separate downstream scan test chains and concatenates scan test information from said separate down stream scan test chains.