Patent ID: 7467368
Filing Date: 2008-12-16
Classification: G06F

Abstract:
1. A method of clustering a circuit design, comprising the steps of: selecting a configurable logic block comprising a first slice and a second slice, wherein the first slice is connected to at least a first load slice through a first critical connection and the second slice is connected to at least a second load slice through a second critical connection; determining that the first critical connection and the second critical connection have equivalent critical attractions; determining fanout of the first slice and fanout of the second slice; selecting the first slice or the second slice according to lowest fanout; locating each load slice of the selected slice within the configurable logic block when the total number of inputs and outputs of the resulting configurable logic block do not exceed a threshold number of inputs and outputs, and wherein the threshold number of inputs and outputs is less than the number of inputs and outputs that physically be accommodated by the configurable logic block so as to leave white space in the configurable logic block for post-placement circuit optimizations; and combining slices that share control signals and clock sources such that the total number of components of the combined slice does not exceed a threshold number of components.