Patent ID: 7148111
Filing Date: 2006-12-12
Classification: H01L

Abstract:
1. A method of manufacturing a trench transistor comprising: providing a semiconductor substrate having dopants of a first conductivity type; forming a plurality of trenches extending from a first surface of the substrate to a first depth into the semiconductor substrate; lining each of the plurality of trenches with a gate dielectric material; substantially filling each dielectric-lined trench with conductive material; forming a doped well in the substrate to a second depth that is less than said first depth of the plurality of trenches, the doped well having dopants of a second conductivity type opposite to said first conductivity type; forming a source region inside the doped well and extending to a third depth that is less than the second depth, the source region having dopants of the first conductivity type; and forming a heavy body inside the doped well, the heavy body having dopants of the second conductivity type with a peak concentration occurring at a fourth depth below the third depth of the source region and above the second depth of the doped well.