Patent ID: 6291338
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A fabrication method for a via plug, comprising:forming a first polysilicon layer and a silicon oxide layer in sequence on an inter-polysilicon dielectric (IPD) layer;forming a patterned first photoresist layer on the silicon oxide layer;removing a part of the silicon oxide layer until the first polysilicon layer is exposed so as to form a first opening in the form of a trench, with the patterned first photoresist serving as a mask;removing the patterned first photoresist layer;forming a second polysilicon layer in the first opening;forming a patterned second photoresist layer on the silicon oxide layer and the second polysilicon layer so as to form a second opening in the patterned second photoresist for exposing a part of the second polysilicon layer and a part of the silicon oxide layer, wherein the second opening is perpendicular to the second polysilicon layer;removing the exposed part of the second polysilicon layer and a part of the first polysilicon layer, with the patterned second photoresist layer and the silicon oxide layer serving as a mask, so that a third opening is formed through the second polysilicon layer and the first polysilicon layer for exposing a part of the IPD layer;removing the patterned second photoresist layer and the silicon oxide layer;after removing the silicon oxide layer, removing the exposed part of the IPD layer for forming a fourth opening, with the first polysilicon layer and the second polysilicon layer serving as a mask;forming a third polysilicon layer on the first polysilicon layer and the second polysilicon layer, so that the fourth opening is filled with the third polysilicon layer; andremoving the third polysilicon layer, the first polysilicon layer, and the second polysilicon layer until the IPD layer is exposed, whereby the via plug is formed.