Patent ID: 6746927
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A method, comprising:forming at least one feature of a silicon-containing semiconductive material on a substrate, said feature having sidewalls and an upper surface; forming a dielectric layer on said sidewalls of said at least one feature, said dielectric layer covering portions of said substrate adjacent said sidewalls; introducing dopant material into at least the portions of said substrate not covered by said feature and said dielectric layer on said sidewalls; removing said dielectric layer so as to expose the sidewalls of said feature; and forming spacer elements adjacent to a portion of said sidewalls, said elements covering less than all of said sidewalls and defining exposed upper sidewall portions, wherein forming said spacer elements comprises forming an underlying oxide liner of a first predefined thickness on at least the upper surface and the sidewalls of said at least one feature and depositing thereon a nitride layer of a second predefined thickness and selectively anisotropically overetching said nitride layer and said oxide liner until at least the upper surface and the upper sidewall portions of said at least one feature are exposed.