Patent ID: 8937390
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first substrate having a upper surface and a bottom surface; a first semiconductor memory element comprising a stack of a plurality of semiconductor memory elements including a second semiconductor memory element and a third semiconductor memory element stacked on the second semiconductor memory element, provided above said upper surface of said first substrate, a first primary connecting bump being provided between the second semiconductor memory element and the third semiconductor memory element, and a second primary connecting bump provided between the second semiconductor memory element and said first substrate, the third semiconductor memory element being electrically connected to said first substrate through a through electrode formed inside the second semiconductor memory element, an uppermost semiconductor memory element of the first semiconductor memory element having no through electrode; a plurality of secondary connecting bumps directly connected to said bottom surface of said first substrate, such that a space is formed between the plurality of secondary connecting bumps; and a cooling module comprising a heat receiving section disposed on the bottom surface of the first substrate and in the space formed between the plurality of secondary connecting bumps, the cooling module further comprising a refrigerant flowing through the heat receiving section.