Patent ID: 8089155
Filing Date: 2012-01-03
Classification: H01L

Abstract:
1. An integrated circuit chip comprising: a silicon substrate; a transistor in and on said silicon substrate; a first metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a first metal interconnect over said silicon substrate; a passivation layer over said first metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening; a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said polymer layer is over said first contact point; a passive device over said polymer layer and vertically over said first contact point; a second metallization structure on said first contact point, wherein said second metallization structure comprises a glue layer, a copper-containing seed layer on said glue/barrier layer, and an electroplated copper layer on said copper-containing seed layer; and a solder between said first contact point and said passive device and over said second metallization structure, wherein said passive device is connected to said first contact point through said solder and said second metallization structure.