Patent ID: 6877084
Filing Date: 2005-04-05
Classification: G06F

Abstract:
1. A central processing unit (CPU) comprising: a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register; wherein the number of standard registers is less than or equal to a number of general purpose registers defined by a CPU architecture, and wherein the number of extended registers is greater than the number of general purpose registers defined by the CPU architecture.