Patent ID: 9104636
Filing Date: 2015-08-11
Classification: G06F

Abstract:
1. A processor sharing a shared memory shared by a plurality of processors, the shared memory comprising an allocation memory block and a management memory block, the processor comprising: an allocator configured to secure a memory area in the shared memory allocated to each of the processors based on a request of each of the processors, and register a plurality of reference counters corresponding one-to-one to the processors; an updater configured to add 1 to a value of the reference counter corresponding to the processor managing the memory area when the memory area is allocated to each of the processors and subtract 1 from the value of the reference counter corresponding to the processor managing the memory area when the memory area is released from the processor to which the memory area is allocated; a releaser configured to release the memory area from the processor to which the memory area is allocated when a sum of the values of the reference counters in the memory area updated by the updater is 0; and a searcher configured to determine a scale of the memory area, wherein in a tail end of the memory area, the allocator registers an entry pointer with respect to an entry corresponding to an allocation unit appropriate for a head address of the memory area and the reference counters in front of the entry pointer, and wherein the searcher determines a reference scale, calculates a tentative tail address of a tentative entry corresponding to the reference scale using the reference scale and a head address of an unused entry, calculates a tentative entry pointer with respect to the tentative entry and a tentative head address of the tentative entry based on the tentative tail address, compares a set of the tentative head address and the head address of the unused entry with a set of the reference scale and a tentative scale of the tentative entry, and determines the scale of the memory area.