Patent ID: 8860459
Filing Date: 2014-10-14
Classification: G11C,H01L,H03K

Abstract:
1. A semiconductor integrated circuit comprising: nonvolatile memory areas, each comprising a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor comprising a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor comprising a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected to the first drain diffusion region and the second drain diffusion region; and logic transistor areas, each comprising a logic transistor whose conductive type is same as the first nonvolatile memory transistor, the logic transistor comprising a third source diffusion region, a third drain diffusion region and a first gate electrode, wherein the nonvolatile memory areas and the logic transistor areas are arranged on a substrate, a height of a lower surface of the first gate electrode from an upper surface of the substrate is lower than a height of each of lower surfaces of the first and second control gate electrodes from the upper surface of the substrate, and a length of an overlapping area of the first source diffusion region and the first control gate electrode in a direction parallel to a channel of the first nonvolatile memory transistor is larger than a length of an overlapping area of the third source diffusion region and the first gate electrode in a direction parallel to a channel of the logic transistor, when seen from the upper surface of the substrate.