Patent ID: 8953463
Filing Date: 2015-02-10
Classification: H04L

Abstract:
1. A serial communication system, comprising: a controller; a channel interleaved multiplexed data bus coupled to the controller, the channel interleaved multiplexed data bus being arranged as a two dimensional array of time domain interleaved data channels on a backplane of the communication system to receive a data signal, the two dimensional array being based on a number of channels available on the backplane and a fixed pattern sequence of data transmitted on the backplane, the two dimensional array having an initial channel reserved as a loopback bit test channel that includes a plurality of test logic gates configured to transmit a test pattern therethrough, the channel interleaved multiplexed data bus also transmitting the data signal through each channel available on the backplane of the communication system based on a channel select signal of a respective channel; and a transceiver coupled to the channel interleaved multiplexed data bus, wherein the controller being configured to provide a data signal for transmission on the channel interleaved multiplexed data bus and is configured to multiplex the data signal on a sequential channel-by-channel basis, and, wherein the data signal is presented to each of the time domain interleaved data channels, and upon completing loopback of the test pattern, performing a verification that each received data bit of the data signal is received at an appropriate portion of a respective time domain interleaved data channel.