Patent ID: 7739433
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. An apparatus for sharing bandwidth of a single port static random access memory (SRAM) between at least one direct memory access (DMA) peripheral and a central processing unit (CPU) operating with a quadrature clock, said apparatus comprising: a central processing unit (CPU) having a first memory interface; a direct memory access (DMA) peripheral having a second memory interface; a single port static random access memory (SRAM) having a third memory interface; and a dual access interface having fourth, fifth and sixth memory interfaces, wherein the fourth memory interface is coupled to the first memory interface, the fifth memory interface is coupled to the second memory interface, and the sixth memory interface is coupled to the third memory interface, wherein the dual access interface enables the CPU to perform read, write, and read-modify-write transactions with the single port SRAM during DMA transactions with the single port SRAM, wherein when the CPU issues a read transaction to the dual access interface, the dual access interface: waits one memory cycle; generates a read cycle to the single port SRAM through a link between said sixth memory interface and the third memory interface; latches read data from the single port SRAM after a memory access time has finished and frees the link between said third memory interface and the sixth memory interface; and makes the latched read data from the single port SRAM available to the CPU.