Patent ID: 7571304
Filing Date: 2009-08-04
Classification: G06F

Abstract:
1. A method for creating multiple checkpoints in a processor that supports speculative-execution, comprising: issuing instructions for execution in program order during execution of a program in a normal-execution mode; upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, performing an initial checkpoint and commencing execution of instructions in a execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; upon encountering a non-data-dependent stall condition in normal-execution mode or in execute-ahead mode, commencing execution of instructions in scout-mode, wherein instructions are speculatively executed to prefetch future loads without committing the results of the instructions to the architectural state of the processor; wherein the processor includes N copies of a register file, wherein each register has a HR pointer that indicates which copy of the register file contains the architecturally committed version of the register and an HW variable for each potential checkpoint, wherein the processor sets a corresponding HW variable when the register is speculatively written following the generation of a checkpoint; wherein reading from a register in normal-execution mode, execute-ahead mode, or scout mode involves determining which register to read from by computing (HR+HW) % N, wherein HW is either zero or equal to a value of a checkpoint after which a most recently set HW variable was set for the register.