Patent ID: 6229757
Filing Date: 2001-05-08
Classification: G11C

Abstract:
A semiconductor memory device comprising:a data strobe signal processing circuit for detecting at least one of a rise edge of a data strobe signal and a fall edge thereof to thereby produce at least a first one-shot pulse signal;a clock signal processing circuit for detecting a rise edge of a clock signal to thereby produce a second one-shot pulse signal; anda data-in processing circuit for latching input data by using said first one-shot pulse signal produced from said data strobe signal, and further for latching said latched input data by using said second one-shot pulse signal produced from said clock signal, and also for simultaneously writing both the latched data into a memory cell in a parallel manner, wherein:said data-in processing circuit controls a delay amount of said first one-shot pulse signal and another delay amount of said second one-shot pulse signal so as to secure a latch margin of said input data.