Patent ID: 8811053
Filing Date: 2014-08-19
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a system clock terminal provided to receive a system clock; a data terminal provided to transfer a data therethrough in synchronization with the system clock; a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough; a command terminal provided to receive a command to communicate the data with an outside thereof; and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data, the length of the preamble being either a first length corresponding to the preamble length information or a second length; and control circuitry configured to control a dynamic change of the length of the preamble between the first and second lengths based on a change of operation within the semiconductor device, and wherein one of the first length and the second length is at least substantially larger than the other length.