Patent ID: 7076709
Filing Date: 2006-07-11
Classification: G01R

Abstract:
1. An electronic circuit comprising: clock circuitry; a first sub-circuit comprising a first clocked data storage element and a first clock gate circuit that is coupled between an output of the clock circuitry and a clock input of the first data storage element; a second sub-circuit comprising a second data storage element, within a different clock domain as the first data storage element, and a second clock gate circuit that is coupled between an output of the clock circuitry and a clock input of the second data storage element; a data path between the first clocked storage element and the second clocked storage element; a detector circuit, coupled between the first sub-circuit and the second sub-circuit, that flags an invalid data write operation in the second data storage element in relation to the first clocked gate circuit receiving a gate signal that commands blocking passage of a first clock signal from the clock circuitry.