Patent ID: 8604621
Filing Date: 2013-12-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; first and second penetration electrodes each penetrating the semiconductor substrate; a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure comprising a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring; a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode; a second wiring pad formed as the upper-level wiring; a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads; a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode; a fourth wiring pad formed as the upper-level wiring; and a plurality of second through electrodes each formed in the interlayer insulating film to form an electrical connection between the third and fourth wiring pads, wherein a number of the first through electrodes is greater than a number of the second through electrodes.