Patent ID: 6704231
Filing Date: 2004-03-09
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells storing charge according to storage data; a bit line connected to a selected memory cell of said plurality of memory cells in a data readout mode; a peripheral circuit connected to said bit line in said data readout mode to execute data reading with respect to said selected memory cell; an isolation unit to electrically isolate, as necessary, said bit lines into first and second regions of a bit line corresponding to said plurality of memory cells and said peripheral circuit respectively; a first voltage supply line provided corresponding to a bit line in said first region; a second voltage supply line provided corresponding to said peripheral circuit; and a voltage control circuit controlling a voltage to be supplied to said first and second voltage supply lines, said voltage control circuit supplying the same voltage to said first and second voltage supply lines in an operation mode, and supplying different voltages to said first and second voltage supply lines in a test mode.