Patent ID: 7968946
Filing Date: 2011-06-28
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a semiconductor substrate having a (110) surface; and at least one nFET and at least one pFET located on said semiconductor substrate, wherein both of said at least one nFET and said at least one pFET both have a strained channel along a <100> channel direction, and both of said at least one nFET and said at least one pFET are located on the (110) surface, wherein said strained channel is a result of a single tensile stressed liner over said at least one nFET and said at least one pFET and a compressively stressed STI region between said at least one nFET and said at least one pFET, wherein carrier mobility in the strained channel for both the at least one nFET and the at least one pFET is increased when compared to a similar device in which the tensile stressed liner and the compressively stressed STI region are removed.