Patent ID: 8736069
Filing Date: 2014-05-27
Classification: H01L

Abstract:
1. An integrated circuit including a multi-level vertical plug formation with stop layers of increasing thicknesses, comprising: a substrate within which a pit is formed; a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers within the pit such that an uppermost one of the conductive layers is below a top surface of the substrate; landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack; etch stop layers over corresponding landing areas, the etch stop layers having thicknesses that correlate with depths of the corresponding landing areas; a plurality of vias extending through the etch stop layers to the landing areas in the plurality of conductive layers; interlayer connectors connected to respective conductive layers in the stack through the plurality of vias; and an isolation region extending into the substrate separating the stack from an array periphery region.