Patent ID: 6531359
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A method for fabricating a memory cell array, which comprises the following steps:a) burying insulation zones on a silicon substrate by applying STI (Shallow Trench Isolation) technology; b) forming word lines on the insulation zones; c) covering the word lines with a hard mask and side wall oxides; d) CVD depositing a material laterally onto the hard mask and onto the side wall oxides to define spacers; e) etching the spacers to form spacer channels in the insulation zones between adjoining word lines; f) applying and patterning an SAS (Self Aligned Source) resist mask to mask each two adjacent coated word lines in regions, including the spacer channel located between the word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked in regions, including the spacer channel lying between the word lines; g) exposing the SAS resist mask; h) anisotropically etching regions of the insulation zones not covered by the SAS resist mask and lowering a bottom of uncovered spacer channels down at least to a surface of the silicon substrate; i) removing the SAS resist mask to uncover a resultant structure; j) depositing a PSG (phosphorus-doped glass) layer onto the uncovered structure; and k) heat treating a resultant structure to defuse the phosphorus doping into the uncovered silicon substrate as a source doping process step.