Patent ID: 7072210
Filing Date: 2006-07-04
Classification: G11C,H01L

Abstract:
1. A memory array, comprising: a plurality of word lines; a plurality of first source/drain lines; a plurality of second source/drain lines; and a plurality of memory units, comprising: a gate electrode, coupled to one of the word lines; a gate dielectric layer laid below the gate electrode; a first source/drain region, coupled to one of the first source/drain lines or first bit lines, further comprising a first multi-layer dielectric spacer formed between the first source/drain region and the gate electrode to store electrons or electric charges; and a second source/drain region, coupled to one of the second source/drain lines or second bit lines, further comprising a second multi-layer dielectric spacer formed between the second source/drain region and the gate electrode to store electrons or electric charges; a metal-semiconductor compound layer formed over the gate electrode, first source/drain region and second source/drain region; a semiconductor channel formed between said first source/drain region and second source/drain region.