Patent ID: 8289792
Filing Date: 2012-10-16
Classification: G11C

Abstract:
1. A memory test circuit which tests a test target memory including an actual array portion and a redundancy portion, comprising: an input data selector configured to output first test data excluding data for said redundancy portion in test data representing data for said actual array portion and said redundancy portion as input selecting data in a redundancy memory BIST (Built In Self Test) mode; an input data switching circuit configured to output said test data as output test data to said test target memory in a direct memory BIST mode, and output data obtained by adding redundancy bits to said input selecting data as said output test data to said test target memory based on said input selecting data and output redundancy codes representing redundancy codes in said redundancy memory BIST mode; an output data switching circuit configured to output data obtained by removing said redundancy bits from read data as output selecting data based on said read data from said test target memory and said output redundancy codes in said redundancy memory BIST mode; and a memory BIST comparator configured to check a value of said read data with a checking expectation value to output a result of said checking as a test result in said direct memory BIST mode, and check a value of said output selecting data with an expectation value for said actual array portion in said checking expectation value to output a result of said checking as said test result in said redundancy memory BIST mode.