Patent ID: 8489788
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. A data processor comprising: a central processing unit configured to execute at least one instruction; a plurality of circuit modules coupled to the central processing unit; a first controller which outputs a request for interruption to the central processing unit in response to a generated event signal; and a second controller which outputs a start control signal to each circuit module in response to a generated event signal, wherein each circuit module is capable of producing the event signal, wherein upon receiving a first event signal from a first one of said circuit modules, the second controller outputs a first start control signal to cause a second one of said circuit modules to perform a given operation, and wherein upon receiving a second event signal produced in response to completion of a data operation from the second circuit module, the second controller outputs a second start control signal to cause a third one of said circuit modules to output data to outside of the data processor.