Patent ID: 8916470
Filing Date: 2014-12-23
Classification: H01L

Abstract:
1. A method of manufacturing sidewall spacers on a memory device, comprising providing a substrate including a peripheral circuit region and a memory array region, wherein at least one electronic component layer is defined in the peripheral circuit region and the memory array region, and the electronic component layer includes at least one transistor and at least one word line; depositing a first dielectric layer in the peripheral circuit region and the memory array region; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer to expose the first dielectric layer; depositing a third dielectric layer in the peripheral circuit region and the memory array region; coating a masking layer in the peripheral circuit region; etching the third dielectric layer in the memory array region to expose the second dielectric layer and the first dielectric layer; etching all of the second dielectric layer in the memory array region; removing the masking layer in the peripheral circuit region; etching the first dielectric layer and the third dielectric layer on the electronic component layer to expose the transistor and the word line, wherein a composite spacer is formed adjacent to the transistor, a spacer is formed adjacent to the word line, and the spacer has a first thickness; and removing the second dielectric layer and the third dielectric layer in the peripheral circuit region to define an L-shaped cross section of the first dielectric layer having a second thickness in the peripheral circuit region, wherein the second thickness is greater than the first thickness.