Patent ID: 6559697
Filing Date: 2003-05-06
Classification: H03L

Abstract:
A multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M, comprising:a frequency divider circuit which is configured to generate a feedback clock signal by dividing said output clock signal by a factor M; a phase comparator circuit which is configured to receive said input clock signal and said feedback clock signal as generated by said frequency divider circuit, to compare the phase of said input clock signal with the phase of said feedback clock signal and to output a phase displacement signal indicative of the phase relationship between said input clock signal and said feedback clock signal; a comparator which is configured to receive said phase displacement signal, to count said output clock signal within each cycle of said feedback clock signal while said phase displacement signal is indicative that there is a phase displacement between said feedback clock signal and said input clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, and to output a delay time adjustment signal on the basis of the result of the comparison; and an oscillator circuit which is capable of controlling said output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of said delay time adjustment signal and outputting said output clock signal as controlled.