Patent ID: 8565014
Filing Date: 2013-10-22
Classification: G11C

Abstract:
1. An SMT MRAM device comprising: SMT MRAM memory cells arranged in an array of rows and columns such that each of the columns of SMT MRAM cells is associated with one of its adjacent columns of SMT MRAM cells; a plurality of true data bit lines where each of the true data bit lines is connected to one adjacent column; a plurality of complement data bit lines, wherein each of the plurality of complement data bit lines are connected with each SMT MRAM cell of a pair of columns of the SMT MRAM cells such that each of the plurality of complement data bit lines is shared with the pair of columns of the SMT MRAM cells; and a plurality of shunting switch devices, wherein each of the shunting switch devices is connected between one of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.