Patent ID: 6295231
Filing Date: 2001-09-25
Classification: G11C

Abstract:
A high-speed cycle clock-synchronous memory device comprising:a plurality of cell arrays, each comprising a plurality of memory cells;a sense amplifier circuit section shared by said cell arrays; anda cell array control circuit to which row and column addresses are inputted to designate an arbitrary one of said memory cells and which controls an access to each of said plurality of cell arrays, independently of any other cell array,wherein the cell arrays have such an address configuration that a first address obtained according to a first command is compared with a second address obtained according to a second command received after the first command and whether an access is made to the memory cells of the same cell array, of neighboring cell arrays, or of remote cell arrays in accordance with the first and second commands is determined from a difference between the first and second addresses in terms of specific bits.