Patent ID: 6436767
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A process for manufacturing a semiconductor memory device comprising the steps of:(a) forming a gate dielectric layer on a silicon substrate; (b) forming a floating gate on said gate dielectric layer; (c) causing a first member to grow as a film on at least upper and lateral sides of said floating gate; (d) depositing a second member which will become a sidewall over an entire surface of said silicon substrate; (e) forming said sidewall by etching back said second member by using said first member as an etching stop so that said second member remains only on the lateral sides of said floating gate; (f) removing said first member which is exposed on an upper surface of said floating gate; (g) causing an interlayer dielectric to grow as a film on upper surfaces of said floating gate and said first and second members; (h) forming a control gate on said interlayer dielectric; and (i) forming a silicide layer on a surface of said control gate.