Patent ID: 8884411
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first semiconductor element; a first thick plate portion that is electrically connected to an electrode on a lower surface side of the first semiconductor element, and that is formed by a conductor; a second semiconductor element, wherein the second semiconductor element is disposed to face the same direction as the first semiconductor element and the lower surface side of the second semiconductor element is substantially flush with the lower surface side of the first semiconductor element; a second thick plate portion that is electrically connected to an electrode on a lower surface side of the second semiconductor element, and that is formed by a conductor; a third thick plate portion that is electrically connected to an electrode on an upper surface side of the first semiconductor element, and that is formed by a conductor; a fourth thick plate portion that is electrically connected to an electrode on an upper surface side of the second semiconductor element, and that is formed by a conductor; a first thin plate portion that is provided on the second thick plate portion, is formed by a conductor, and is thinner than both the first thick plate portion and the second thick plate portion; and a second thin plate portion that is provided on the third thick plate portion, is formed by a conductor, and is thinner than both the third thick plate portion and the fourth thick plate portion, wherein the first thin plate portion and the second thin plate portion are fixed together and electrically connected, and wherein the first thin plate portion is provided on the first thick plate portion side of the second thick plate portion; the second thin plate portion is provided on the fourth thick plate portion side of the third thick plate portion; and the first thin plate portion and the second thin plate portion are electrically connected in a position between a position of the first thick plate portion and a position of the third thick plate portion, in a thickness direction of the first semiconductor element.