Patent ID: 9018758
Filing Date: 2015-04-28
Classification: C23C,C25D,H01L

Abstract:
1. An integrated circuit device, comprising: a semiconductor substrate; a pad over the semiconductor substrate; a passivation layer over the pad and exposing at least a portion of the pad; an under-bump-metallurgy (UBM) layer over the pad and the passivation layer; a conductive pillar formed on the UBM layer, and having a top surface and a sidewall surface, wherein the sidewall surface has a first portion adjacent to the top surface and a second portion adjacent to the UBM layer, the first portion and the second portion are coplanar, and the first portion and the top surface are not coplanar; a non-metal protection structure formed on the second portion of the sidewall surface of the conductive pillar; and a metal cap layer formed on the top surface of the conductive pillar and extending to cover the first portion of the sidewall surface of the conductive pillar.