Patent ID: 8008723
Filing Date: 2011-08-30
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first-conductivity-type well; a plurality of first diffusion layers formed in said well, having a second conductivity type, and connected to a signal input/output terminal; a plurality of second diffusion layers formed in said well, arranged alternately with said plurality of first diffusion layers, and connected to a power source or to ground; and a diffusion resistance layer formed in said well, having a second conductivity type, located adjacent to said plurality of second diffusion layers, connected to said input/output terminal, and connecting an internal circuit and said input/output terminal, wherein in a plan view, in each row and each column of a matrix of said plurality of second diffusion layers and said plurality of first diffusion layers, said plurality of second diffusion layers are placed alternately with respect to said plurality of first diffusion layers.