Patent ID: 6271083
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A method of forming a DRAM capacitor, comprising the following steps in the sequence set forth:forming a first silicon oxide layer on a substrate;forming a nitride layer on said first silicon oxide layer;patterning said nitride layer and said first silicon oxide layer to form a contact hole through said nitride layer and said first silicon oxide layer to said substrate;filling a polysilicon layer into said contact hole;removing a top part of said polysilicon layer in said contact hole to form a blank part of said contact hole;filling a W-metal (selective tungsten metal) in said blank part to form a contact plug,forming a second silicon oxide layer on the surfaces of said nitride layer and said W-metal (selective tungsten metal);patterning said second silicon oxide layer to form a trench, and said W-metal (selective tungsten metal) being exposed in said trench;forming a barrier metal layer on a surface of said trench and said second silicon oxide in contact with said W-metal;forming a first metal layer on said barrier metal layer;forming a dielectric layer on said first metal layer and said second silicon oxide layer; andforming a second metal layer on said dielectric layer.