Patent ID: 6531362
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, the method comprising:preparing a semiconductor substrate divided into a peripheral region and a cell region provided with a first metal pattern formed thereon, wherein the regions are adjacent to each other; forming a first and a second insulating layers on top of the first metal pattern, a portion of the cell region and the peripheral region, wherein the second insulating layer is formed with a borophosphosilicate glass (BPSG) and the first insulating layer is formed with an undoped silicate glass by controlling a deposition condition of the BPSG layer during an initial preset time; planarizing the second insulating layer to a predetermined thickness for smoothing a step contour between the cell region and the peripheral region; and forming a second metal pattern on top of the planarized second insulating layer, thereby preventing a bridge between the first and the second metal patterns.