Patent ID: 7917567
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. A floating-point processing unit, comprising: an exponent adjustor coupled to receive numerical inputs, the exponent adjustor configured to generate first adjusted values from the numerical inputs; the first adjusted values having equivalent exponents as between corresponding first adjusted values; a first operation specific floating-point processing unit (OFPU) coupled to receive the first adjusted values; the first OFPU including first arithmetic circuitry configured for a first floating-point operation on the first adjusted values to provide first numerical results; a second OFPU coupled to receive the first numerical results; the second OFPU including second arithmetic circuitry configured for a second floating-point operation on the first numerical results to provide second numerical results; a second exponent adjustor configured to provide second adjusted values from the numerical inputs; a third OFPU coupled to receive the second numerical results and further coupled to receive the numerical inputs, the third OFPU including third arithmetic circuitry configured for a third floating-point operation on the second numerical results and the numerical inputs to provide third numerical results; and the first numerical results not being normalized prior to the second floating-point operation.