Patent ID: 6329852
Filing Date: 2001-12-11
Classification: H03K

Abstract:
A power on reset circuit, comprising:a first means for controlling a potential of a first node to a first potential according to a potential of a second node;a second means for supplying a power supply voltage to be ramped up to the second node according to the potential of the first node;a third means for determining a potential of a third node by inverting and delaying the potential of the second node;a fourth means for controlling a potential of a fourth node to a second potential according to the potential of the third node;a fifth means for inverting and delaying the potential of the fourth node;a sixth means for outputting the potential of the third node to an output terminal according to an output signal from said fifth means and its inverted signal; anda seventh means for controlling a signal of the output terminal according to the inverted signal of the output signal from said fifth means.