Patent ID: 8252646
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit, comprising: providing a polysilicon layer across a periphery and an array region of a substrate; etching trenches through the polysilicon layer and into the substrate in the array region; filling the trenches with a metallic material; depositing a metallic layer over the polysilicon layer; forming a cap layer over the metallic layer; patterning gate stacks comprising the cap layer, the metallic layer and the polysilicon layer in the periphery; recessing the metallic material within the trenches; forming an insulating material across the periphery and across the array region, the insulating material filling recesses within the trenches in the array region; and performing a directional etch to produce sidewall spacers comprising the insulating material along sidewalls of the patterned gate stacks and to produce an insulating cap comprising the insulating material over the metallic material within the trenches in the array.