Patent ID: 6061811
Filing Date: 2000-05-09
Classification: G06F

Abstract:
A microprocessor operating in response to a clock signal having a clock period, said microprocessor comprising:a readable memory, wherein said readable memory stores code for performing diagnostic evaluations of said microprocessor, wherein said diagnostic evaluations comprises a first evaluation to occur under non-failure operation at a first clock period and a last evaluation to occur under non-failure operation at a last clock period;circuitry for issuing a series of predetermined addresses to said readable memory to address said code for performing diagnostic evaluations of said microprocessor,a conductor externally accessible and for providing a signal from said microprocessor,circuitry for outputting a diagnostic signal on said conductor during performance of said diagnostic evaluations, wherein divergence of said diagnostic signal from a predetermined pattern before said last clock period indicates a failure of said diagnostic evaluations before said last clock period; andwherein said diagnostic signal comprises a portion of each of said series of predetermined addresses of said code.