Patent ID: 7328299
Filing Date: 2008-02-05
Classification: H03M,H04L,H04N

Abstract:
1. An interface circuit providing parallel data to a serializer/deserializer modulator and receiving parallel data from a serializer/deserializer demodulator, the interface circuit comprising: a parallel data bus for sending and receiving compressed data, the parallel data bus having a parallel data bus width; a plurality of data lines and signal lines from at least one of the following groups including: a first group of at least one clock line and a second group of at least one control line for interfacing with a host system, the data lines comprising a host data bus having a host data bus width; a concatenation block capable of receiving multiple data cycles from the host data bus and combining into parallel data; and a configuration block to accept one or more configuration bits which configure the interface circuit to operate as a receive device for receiving data from the parallel data bus.