Patent ID: 8929141
Filing Date: 2015-01-06
Classification: G11C

Abstract:
1. A method of operating a three dimensional nonvolatile memory array comprising: performing a first plurality of erase operations on a block during a first period of operation of the three dimensional nonvolatile memory using a first set of erase conditions, the first set of erase conditions assigning a predetermined first voltage to a line supplying a gate of a select transistor; subsequently determining that an erase operation using the first set of erase conditions does not fully erase at least some memory cells of the block; subsequently replacing the first set of erase conditions with a second set of erase conditions for the block, the second set of erase conditions assigning a second voltage to the line supplying the gate of the select transistor, the second voltage having a fixed offset from a drain voltage that is observed on a line connected to the drain of the select transistor; and subsequently performing a second plurality of erase operations on the block during a second period of operation of the three dimensional nonvolatile memory using the second set of erase conditions.