Patent ID: 6294799
Filing Date: 2001-09-25
Classification: H01J,H01L

Abstract:
A semiconductor device comprising:a transistor comprising a source region, a drain region, a channel formation region provided between said source region and said drain region, and a gate electrode provided adjacent to said channel formation region with a gate insulating film therebetween;a multilayer dielectric film provided over said transistor and including an insulating layer comprising silicon and a top layer made of a resinous material provided on said insulating layer comprising silicon;a contact hole provided in said insulating layer comprising silicon and said top layer, a part of said contact hole provided in said top layer being provided over a part of said contact hole provided in said insulating layer comprising silicon; anda wiring extending in said part of said contact hole provided in said top layer and extending in said part of said contact hole provided in said insulating layer comprising silicon, and extending over said top layer, said wiring being connected with one of said source region and said drain region,wherein said part of said contact hole provided in said top layer provides a wider opening than said part of said contact hole provided in said insulating layer comprising silicon,wherein said insulating layer comprising silicon has an upper face within said contact hole, and said wiring is provided on said upper face within said part of said contact hole provided in said top layer, andwherein said part of said contact hole provided in said insulating layer comprising silicon is concentric with said part of said contact hole provided in said top layer.