Patent ID: 6999087
Filing Date: 2006-02-14
Classification: G06T,G09G

Abstract:
1. A graphics system comprising: a frame buffer, wherein the frame buffer includes a sample buffer and a double-buffered display area; a hardware accelerator coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area; wherein the hardware accelerator includes a frame buffer address unit configured to map fragment coordinates to memory addresses of the frame buffer, wherein the frame buffer address unit includes dynamically programmable registers which control the mapping between fragment addresses and memory addresses; wherein a program executing on a host computer is configured to dynamically update the programmable registers to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters, wherein the program reallocates the sample buffer so as to achieve a maximum sample density.