Patent ID: 8704352
Filing Date: 2014-04-22
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first substrate; a second substrate provided above said first substrate; a first semiconductor memory element comprising a stack of a plurality of semiconductor memory elements including a second semiconductor memory element and a third semiconductor memory element stacked on the second semiconductor memory element, provided above said second substrate, a first primary connecting bump being provided between the second semiconductor memory element and the third semiconductor memory element and a second primary connecting bump provided between the second semiconductor memory element and said second substrate, the third semiconductor memory element being and electrically connected to said second substrate through a through electrode formed inside the second semiconductor memory element, an uppermost semiconductor memory element of the first semiconductor memory element having no through electrode; a plurality of secondary connecting bumps directly connecting said first substrate and second substrate, such that a space is formed between said first substrate and said second substrate; and a cooling module comprising a heat receiving section disposed in the space formed between said first substrate and said second substrate.