Patent ID: 7539065
Filing Date: 2009-05-26
Classification: G11C,H01L

Abstract:
1. A method of programming a non-volatile memory, in particular, a memory cell array having at least two memory cells, a first memory cell and a second memory cell such that each memory cell comprises: a first gate disposed on a substrate, a pair of storage units disposed on the respective sidewalls of the first gate, a second gate and a third gate disposed on the respective sides of the first gate and adjacent to the storage units on the sidewalls of the first gate, wherein the first gate, the storage units, the second gate and the third gate are electrically isolated from one another, and the third gate of the first memory cell is the second gate of the second memory cell, the method comprising the steps of: programming the storage unit in the first memory cell close to the second memory cell by forming a first inversion region in the substrate underneath the first gate of the second memory cell and the third gate of the second memory cell, forming a second inversion region in the substrate underneath the third gate of the first memory cell, forming a third inversion region in the substrate underneath the second gate of the first memory cell, applying a first voltage to the first inversion region, applying a second voltage to the third inversion region such that the first voltage is smaller than the second voltage, applying a third voltage to the first gate of the first memory cell so that source side injection is triggered to program data into the selected storage unit.