Patent ID: 8907708
Filing Date: 2014-12-09
Classification: H03L

Abstract:
1. A method for generating an output clock signal from a reference clock signal using an all digital phase locked loop (ADPLL), the method comprising: generating a frequency control word from a binary encoded frequency control word using a thermometer pulse coder, where the thermometer pulse coder includes a plurality of frequency control word signal lines and the frequency control word includes a plurality of thermometer coded signals and a pulse modulated dither signal; and selecting, using the thermometer pulse coder, one of the plurality of frequency control word signal lines and transmit the pulse modulated dither signal over the selected frequency control word signal line and transmit the thermometer coded signals over a plurality of the other frequency control word signal lines; receiving by a digitally controlled oscillator a frequency control word comprising a combined thermometer and pulse modulated signal via the plurality of frequency control world signal lines and generating an output clock signal at a frequency determined using at least the frequency control word; receiving by a feedback divider the output clock signal from the digitally controlled oscillator and generating a feedback signal; and receiving by a phase detector a reference clock signal and a feedback signal from the feedback divider and generating a phase error signal, which is provided to a digital loop filter configured to generate a binary encoded frequency control word that is input to the thermometer pulse coder.