Patent ID: 6256003
Filing Date: 2001-07-03
Classification: G09G,H04N

Abstract:
A jitter correction circuit comprising:a jitter detection period setting circuit to generate a jitter detection signal at a timing offset relative to an edge of a reference signal and to set a jitter detection period of said detection signal relative to said reference signal;a delayed signal generator to receive a correction subject signal and to generate a plurality of delayed signals of said correction subject signal in which,(a) the total delay time of said plurality of delayed signals of said correction subject signal is substantially shorter than a repetition period of said reference signal and greater than a total possible variation in phase of the correction subject signal, and(b) the time duration of the jitter detection period is greater than a delay introduced between each of said delayed signals and shorter than the total delay time of the delayed signals;an edge detection circuit to detect from said delayed signals of said correction subject signal any of delayed signals having an edge occurring during said jitter detection period; andan output circuit to output said correction subject signal corrected in accordance with detection by said edge detection circuit of the delayed signals having an edge occurring during the jitter detection period.