Patent ID: 6092139
Filing Date: 2000-07-18
Classification: G06F,H05K

Abstract:
A computer system comprising:a passive backplane including a local bus having a primary bus and a secondary bus, a memory bus having a maximum number of data lines, an input/output bus, and an expansion bus, the primary and secondary bus including a peripheral component interconnect (PCI) bus architecture, wherein the primary bus and secondary bus communicate with each other through a PCI to PCI bridge;a pluggable central processing unit circuit board including a microprocessor and having a first mating connector of a first pair unit, the pluggable central processing unit circuit board having a predetermined data width;a pluggable memory circuit board coupled to the central processing unit circuit board through the memory bus unit, and having a first mating connector of a second pair unit;a pluggable bridge circuit board coupled to the central processing unit circuit board and having a first mating connector of a third pair unit; whereinthe passive backplane having a plurality of connectors includes:a second mating connector of the first pair unit for receiving the first mating connector of the first pair unit in the pluggable central processing unit circuit board;a second mating connector of the second pair for receiving the first mating connector of the second pair unit in the pluggable memory circuit board; anda second mating connector of the third pair unit for receiving the first mating connector of the third pair unit in the pluggable bridge circuit board, wherein a subset of the first pair unit have predefined contacts and respectively coupled to a subset of the third pair unit through the primary bus and the expansion bus unit; anda plurality of peripheral devices coupled to the bridge circuit board through the input/output bus; whereinthe memory bus of the bus system is capable of being configured to a variable data path width corresponding to a data size of a central processing unit of the central processing unit circuit board and accommodates for the central processing unit circuit board having the predetermined data width, the predetermined data width being less than or equal to the maximum number of data lines.