Patent ID: 8781211
Filing Date: 2014-07-15
Classification: G03F,G06T

Abstract:
1. A semiconductor target for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, the target comprising: a plurality of first structures that are invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures; and a plurality of second structures that are invariant for a plurality of second rotation angles with respect to a second COS of the second structures, wherein the first rotation angles differ from the second rotation angles such that the first structures are invariant without the second structures being invariant at the first rotation angles and such that the second structures are invariant without the first structures being invariant at the second rotation angles, wherein the first structures and the second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate.