Patent ID: 6480420
Filing Date: 2002-11-12
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, each of the memory cells comprising:a source area formed adjacent to a channel area in said semiconductor substrate; a drain area formed opposite said source area with said channel area therebetween in said semiconductor substrate, the drain area being connected to one of said bit lines; a tunnel insulating film formed on said channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon; a floating gate formed on said tunnel insulating film so as to overlap neither said source area nor said drain area; a gate insulating film formed on said floating gate so as to cover said floating gate; and a control gate formed on said gate insulating film so as to partially overlap both of said source area and said drain area, the control gate being connected to one of said word lines, wherein the source areas of the memory cells are connected to each other so that a common voltage is supplied to each of the source areas, and wherein the memory cells arranged along a selected column are connected to other memory cells arranged along columns other than the selected column.