Patent ID: 6459108
Filing Date: 2002-10-01
Classification: H01L,H02H

Abstract:
A passive semiconductor configuration, comprising:a first electrode and a second electrode; a first semiconductor region having a first surface formed with at least one contact region in contact with said first electrode, having a second surface in contact with said second electrode, and defining a current path between said first and second electrodes; a second semiconductor region disposed to form a first p-n junction with said first semiconductor region and an associated depletion zone; a third semiconductor region disposed to form a second p-n junction with said first semiconductor region and an associated depletion zone, said third semiconductor region having a top surface not adjoining said first semiconductor region; and an insulator region covering said top surface of said third semiconductor region and insulating said third semiconductor region for charge storage charges in said third semiconductor region; said first semiconductor region being formed with at least one channel region in said current path between said first and second electrodes and, upon attaining a predetermined saturation current between said first and second electrodes, said depletion zones of said first and second p-n junctions passively pinching off said channel region and limiting the current to a value below the saturation current.