Patent ID: 8922184
Filing Date: 2014-12-30
Classification: G05F,H02M

Abstract:
1. An apparatus comprising: a switch-capacitor network receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1; a load capacitor for holding the load voltage; a feedback network generating a feedback voltage proportional to the load voltage; and a controller receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks, wherein the switch-capacitor network comprises a parallel connection of N switch units controlled by the N-bit control code, respectively, wherein each of said N switch units comprises: a charging capacitor coupled to the source voltage via a first switch and coupled to the load voltage via a second switch, wherein the first switch and the second switch are controlled by a two-phase non-overlapping clock, wherein each of said N switch units further comprises: