Patent ID: 9136278
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method of forming vertically-stacked memory cells, comprising: forming a source-side select-gate material over a source material; forming a stack of alternating silicon dioxide levels and conductively-doped silicon levels over the source-side select-gate material; forming a metal-containing drain-side select-gate material over the stack; forming a first opening to extend through the drain-side select-gate material, the stack and the source-side select-gate material; the first opening not extending into the source material; forming cavities extending into the conductively-doped silicon levels along sidewalls of the first opening; forming charge-blocking dielectric and charge-storage structures within the cavities; a second opening remaining after forming the charge-blocking dielectric and the charge-storage structures; the second opening having sidewalls extending along the source-side select-gate material, the drain-side select-gate material, and the charge-storage structures; lining the sidewalls of the second opening with gate dielectric; punching through a bottom of the lined second opening to extend the second opening into the source material; and forming channel material within the extended second opening.