Patent ID: 6195292
Filing Date: 2001-02-27
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising:a semiconductor substrate;a source region and a drain region formed in a surface layer of said semiconductor substrate on both sides of a channel region defined in the surface layer, said source and drain regions being of a first conductivity type;a tunneling insulating film formed on the channel region of said semiconductor substrate, said tunneling insulating film having a thickness which allows carriers to tunnel therethrough by a tunneling phenomenon;a floating gate electrode formed on said tunneling insulating film, said floating gate electrode being disposed so as to overlap neither said source region nor said drain region as viewed along a substrate normal direction;a gate insulating film formed over the channel region and covering said floating gate electrode; anda control gate electrode formed on said gate insulating film, said control gate electrode being disposed so as to become in contact with, or partially overlap, said source and drain regions as viewed along the substrate normal direction, wherein materials of said floating gate electrode and the channel region are selected so that a Fermi level of said floating gate electrode is positioned inside an energy band gap of the channel region when an external voltage is not applied between the channel region and said control gate electrode.