Patent ID: 6385071
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A dual mode CAM logic redundant scheme for an ASIC, comprising:a plurality of banks of normal CAM memory address rows; a normal encoder logic, configured to encode a normal CAM memory address row; a plurality of redundant replacement CAM memory address rows; a redundant encoder logic, configured to enable the CAM to bypass the normal encoder logic and encode a redundant CAM memory address row; a CAM fuse comparator logic having a fuse address list, configured to receive a bank address request having a plurality of bits, compare said bank address request to the fuse address list, and choose a normal CAM memory address row or request a redundant CAM memory address row responsive to said comparison; a redundant replacement CAM memory address selector logic, configured to assign a redundant replacement CAM memory address for each of said bank address request bits responsive to said CAM fuse comparator logic redundant CAM memory address row request and thereby provide a redundant replacement CAM memory address row; and an address out logic, configured to pass only one of said normal CAM memory address row and said redundant replacement CAM memory address row.