Patent ID: 9214482
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. An array substrate, comprising: a base substrate; and a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, wherein the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact with the active layer through a first via hole and a second via hole passing through the gate isolation layer and the second insulating layer, respectively; the pixel electrode is in contact with the drain electrode, and wherein the array substrate further includes a nickel layer, and the nickel layer is disposed between the source electrode and the active layer and/or between the drain electrode and the active layer.