Patent ID: 6442656
Filing Date: 2002-08-27
Classification: G06F

Abstract:
A memory gateway comprises:a read buffer having a plurality of addressable read buffer lines; a write buffer having a plurality of addressable write buffer lines; a transaction processing module operably coupled to a bus to receive memory transactions requests, wherein each of the memory transaction requests includes identity of an entity that initiated the memory transaction request, wherein the transaction processing module processes each of the memory transaction requests based on the identity of the requesting entity; an address/control buffer operably coupled to the transaction processing module, wherein the address control buffer stores an address and control information for each of the memory transaction requests when the transaction processing module indicates that each of the memory transaction request is to be fulfilled; and a memory access path operably coupled to enable, for a write transaction of the memory transaction requests in the address/control buffer, writing of data from the write buffer to an external memory, and operably coupled to enable, for a read transaction of the memory transaction requests in the address/control buffer, reading of data from the external memory to the read buffer.