Patent ID: 6766507
Filing Date: 2004-07-20
Classification: G03F

Abstract:
A method of data placement of a measurement process limiting structure (PLS) on a photolithograph mask and a semiconductor chip, in a compliant grid comprising:analyzing the design and nature of the semiconductor chip to determine a suitable PLS control structure size, desired placement frequency of the PLS control structures, and parameters describing placement criteria of the PLS control structures, wherein each PLS control structure contains multiple representative structures and measurement targets for both the photolithographic mask and production of the semiconductor chip using the photolithographic mask; determining the available space on the semiconductor chip in which PLS control structures can be placed by using the placement criteria of the analyzing step; creating a regular grid of PLS control structure placement points over the semiconductor chip at the desired placement frequency; maintaining each PLS control structure placement point of the regular grid that falls within the determined available space on the semiconductor chip; determining the nearest available space within surrounding PLS control structure placement points for each PLS control structure placement point of the regular grid that falls outside the determined available space on the semiconductor chip; if no space is available within the surrounding PLS control structure placement points, deleting that PLS placement point; if a space is available within the surrounding PLS control structure placement point, moving the PLS control structure placement point to the nearest available space, to design a compliant grid for the photolithograph mask and the semiconductor chip; and wherein the step of determining the nearest available space includes determining a chord to the nearest available space.