Patent ID: 8237487
Filing Date: 2012-08-07
Classification: G09G,H03K

Abstract:
1. A level shift circuit, comprising: a level shifter, the level shifter configured to receive at least one input signal and generate level-shifted signals by level-shifting the input signal; an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power; and a buffer coupled between the level shifter and the output buffer, the buffer configured to provide a first driving signal determined by the level-shifted signals to the first sourcing circuit and provide a second driving signal determined by the level-shifted signals to the first sinking circuit, the buffer including first and second transistors coupled in series with each other, the first transistor receiving one of the generated level-shifted signals and the second transistor receiving another one of the generated level-shifted signals, the buffer further including a third transistor and a fourth transistor coupled in series with each other, wherein the third transistor receives the same one of the generated level-shifted signals as the first transistor and the fourth transistor receives the another one of the generated level-shifted signals.