Patent ID: 6559508
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A circuit formed on a semiconductor chip, the chip having a plurality of pads where external signal connections can be made to the chip and the two power supply points, Vss and Vdd, wherein the improvement comprises:a multi-cell open drain driver FET, wherein a cell comprises a source diffusion for a first FET, a source diffusion for a second FET, a drain diffusion common to the first and second FETs, a gate and an underlying channel for the first FET and a a gate and an underlying channel for the second FET, the two source diffusions being connected to Vss, the common drain diffusion being connected to an associated pad, and the two gates being connected to receive a signal for turning the driver on and off, each cell having a frame of the opposite conductivity type to the drain and source diffusions located around the first and second FETs, the frame being connected to Vss, the cells of the open drain driver being located closely adjacent to an associated pad, the open drain driver FET having the property of conducting between the pad and Vss when one of the junctions of the channel with the source and drain is reverse biased to break down by an ESD voltage between the pad and Vss, and a Vss to Vdd FET comprising at least one cell having the source and gates connected to Vss, the Vss to Vdd FET having the property of conducting between Vss and Vdd when the driver conducts between the pad and Vss in response to an ESD voltage between the pad and Vdd, the driver array and the Vss to Vdd FET being located closely adjacent and wherein the frame has segments shared by the driver array and the Vss to Vdd FET.