Patent ID: 8176209
Filing Date: 2012-05-08
Classification: G06F

Abstract:
1. A data communication system, comprising: a main processor; and at least one sub-processor or at least one peripheral device connected with the main processor according to a serial peripheral interface (SPI) method, and performing an operation corresponding to a command transferred from the main processor, wherein the connection according to the SPI method is made by one or more bus lines, and the one or more bus lines include: a master in slave out (MISO) line and master out slave in (MOSI) line for data transfer; a slave select (SS) line for transferring a signal selecting one of the sub-processor or the peripheral device and switching the selected sub-processor or peripheral device to an operable state; an interrupt line branching from the SS line, and transferring the signal transferred through the SS line as wake-up signal and a state machine initialization signal of the selected sub-processor or peripheral device; a clock transfer line; and wherein the one or more bus lines further include a data-ready line for transferring a signal indicating that there is data to be transferred from the sub-processor or the peripheral device to the main processor.