Patent ID: 9094011
Filing Date: 2015-07-28
Classification: G06F,H03K

Abstract:
1. A semiconductor circuit, comprising: a plurality of rows of logic cells; a real power strap disposed over the plurality of rows of logic cells; a virtual power strap disposed over the plurality of rows of logic cells and adjacent to the real power strap; a first power switch cell disposed over a first portion of the real power strap and a first portion of the virtual power strap, and collinear with a first row from among the plurality of rows of logic cells; a second power switch cell disposed over a second portion of the real power strap and a second portion of the virtual power strap, and collinear with another row from among the plurality of rows of logic cells; and a plurality of tap cells disposed over portions of the real power strap and portions of the virtual power strap, wherein two or more rows of logic cells from among the plurality of rows of logic cells are between the first row of logic cells and the another row of logic cells.