Patent ID: 8379474
Filing Date: 2013-02-19
Classification: G11C

Abstract:
1. A word line selection circuit comprising: an inverter circuit that drives a boosted power supply potential VPP as a power supply, an output node of the inverter circuit being connected to a word line; and a final stage row decoder that has a control output node output-wired to an input node of the inverter circuit, and that changes a potential of the control output node based on a result of having decoded groups of address control signals from a preceding stage row decoder, wherein the final stage row decoder is provided with variable resistance means between the boosted power supply potential VPP and the control output node, a resistance value of the variable resistance means is controlled by at least one of the groups of the address control signals, and the groups of the address control signals from the preceding stage row decoder are signals of a non-boosted power supply potential, wherein the variable resistance means is a PMOS transistor in which a source is connected to the boosted power supply potential VPP, a drain to the control output node, and in which one of the groups of the address control signals is applied to a gate, wherein the final stage row decoder comprises an NMOS transistor whose gate is in common with the gate of the PMOS transistor, and wherein the NMOS transistor is connected in series with the PMOS transistor through the control output node, and the groups of address control signals from the preceding stage row decoder are applied to the common gate and a source of the NMOS transistor.