Patent ID: 7433528
Filing Date: 2008-10-07
Classification: G06T,H04N

Abstract:
1. An image processing apparatus that carries out encoding of a macro block comprised of a plurality of steps, the apparatus comprising: dynamically reconfigurable circuits; a reconfiguration information memory unit configured to store a plurality of pieces of circuit information used to configure the dynamically reconfigurable circuits; a reconfiguration timing detection unit configured to detect the timing of a reconfiguration that changes a circuit comprised of the dynamically reconfigurable circuits; and a control unit configured to read out circuit information corresponding to the circuit that is to be reconfigured by the dynamically reconfigurable circuits from the reconfiguration information memory unit and reconfigure the dynamically reconfigurable circuits in response to a detection of a reconfiguration, wherein the reconfiguration timing detection unit detects, out of the plurality of steps, the start or the finish of the steps having independent processing times, and at least the start of the encoding of a macro block, and wherein the control unit reduces the number of dynamic reconfigurations within a predetermined processing time cycle when a throughput required by the encoding process is low and increases the types of circuits to be dynamically reconfigured with each reconfiguration, and increases the number of dynamic reconfigurations within the predetermined processing time cycle when the throughput is high and decreases the types of circuits to be dynamically reconfigured with each reconfiguration.