Patent ID: 7286569
Filing Date: 2007-10-23
Classification: H04J

Abstract:
1. Apparatus for use in providing full-rate clock data retiming in a time division multiplexer, wherein the time division multiplexer includes an N to 1 time division multiplexer circuit and a retiming circuit, the apparatus comprising: first circuitry for generating a half-rate clock from a full-rate clock used by the retiming circuit and for providing selective adjustment of a phase associated with the half-rate clock within a range of D degrees; and second circuitry, coupled to the first circuitry, for generating a set of sub-rate clocks from the phase-adjustable half-rate clock for use by the N to 1 time division multiplexer circuit in generating a multiplexed data stream from N parallel data streams, such that the retiming circuit is able to operate within a clock phase margin associated therewith.