Patent ID: 6798005
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a semiconductor substrate; a plurality of dielectric films stacked on a main surface of said semiconductor substrate; a memory cell area in which a field-effect transistor provided with a diffusion region and a conductive type of which is reverse to that of said semiconductor substrate, a gate electrode, a gate insulating film and, a capacitor are formed; and a peripheral circuit area and a first wiring formed in said peripheral circuit area, wherein: said capacitor circuit is formed in a concave portion which is bored through more than two dielectric films of said plurality of dielectric films in said memory cell area; a plurality of second wirings located over said stacked dielectric films in said peripheral circuit area and one of said second wirings is connected to said first wiring by a plurality of plugs, which plugs are connected by stacking thereof; and an upper face of said stacked dielectric films in extended from said peripheral circuit area to said memory cell area, and is in contact with the side face of a storage electrode of said capacitor.