Patent ID: 7568060
Filing Date: 2009-07-28
Classification: G06F

Abstract:
1. A system for interfacing two components of a computing system, wherein the system comprises: a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of a computing system and a slave bus controller of a processor unit of the computing system absent bus selection arbitration, wherein the pair of unidirectional, point-to-point buses comprises means for transmitting a command packet, comprising a command, an address and any data, the address being associated with data pertaining to the command, from the master bus controller to the slave bus controller on the unidirectional, point-to-point output bus; means for determining by the slave bus controller whether the slave bus controller can accept the command; and means for transmitting during a first input bus signaling interval one of an acknowledgement (ACK) signal or a non-acknowledge (NACK) signal from the slave bus controller to the master bus controller via the unidirectional, point-to-point input bus responsive to the slave bus controller receiving a first output bus signaling interval comprising command and control information for the command packet on the unidirectional, point-to-point output bus and before the slave bus controller receives a subsequent output bus signaling interval comprising data of the command packet on the unidirectional, point-to-point output bus, wherein the acknowledge (ACK) signal is transmitted if the determining indicates that the slave bus controller can accept the command packet and the not-acknowledge (NACK) signal is transmitted if the determining indicates that the slave bus controller can not accept the command packet.