Patent ID: 6160456
Filing Date: 2000-12-12
Classification: H03L

Abstract:
A phase-locked loop having an adjustable delay element comprising:a divided-by-N counter for receiving a first input clock signal and generating a first output clock signal having a frequency 1/N that of said first input clock signal;a divided-by-M counter for receiving a second input clock signal and generating a second output clock signal having a frequency 1/M that of said second input clock signal;the adjustable delay element comprising a delay array circuit, a selection switching unit, and a clock counter, wherein said delay array circuit receives the second output clock signal of said divided-by-M counter, said selection switching unit selects an output path of said delay array circuit, and said clock counter provides a clock signal to said selection switching unit for controlling a switching time of said selection switching unit;a phase frequency detector for generating control signals in response to the phase difference and frequency difference between said output signal of said selection switching unit and said first output clock signal of said divided-by-N counter;a charge pump for receiving said control signals of said phase frequency detector;a loop filter coupled to said charge pump for generating a voltage signal in response to the control signals of said phase frequency detector; anda voltage controlled oscillator for generating a clock signal to said divided-by-M counter in response to said voltage signal.