Patent ID: 6956858
Filing Date: 2005-10-18
Classification: H04L

Abstract:
1. A routing table circuit for a router having one or more input ports for receiving a message having a destination address, the router having a plurality of output ports for transmitting the message, the routing table circuit comprising: one or more routing table memories to store a plurality of routing table arrays, said plurality of routing table arrays being arranged hierarchically in a plurality of levels, wherein each of said plurality of routing table arrays is associated with a predetermined subset of prefixes of said destination address, and has entries, said entries including a block default route pointer field to store a block default route pointer and a routing field, wherein said routing field stores a route pointer or a next level pointer pointing to one of said plurality of routing table arrays in a next level; and a route engine to select said block default route pointer or said route pointer as a return route pointer based on said destination address, wherein said return route pointer determines one of said plurality of output ports for routing said message, said route engine to access said plurality of routing table arrays in said plurality of levels.