Patent ID: 6134177
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A redundancy decoding circuit for use in a semiconductor memory device comprising:a comparator for decoding a redundant address and outputting a status signal, wherein the comparator includes internal fuses coupled to an output terminal thereof; and wherein the internal fuses are configured to be selectively cut in order to determine the redundant address;a drive circuit coupled to the comparator for supplying a drive current to the output terminal of the comparator in response to a switching control signal and a pulse signal;a switching control signal generator coupled to the drive circuit for generating the switching control signal, wherein the switching control signal generator includes a master fuse, and wherein a logic level of the switching control signal is determined in accordance with a state of the master fuse; anda pulse generator coupled to the drive circuit for generating the pulse signal in response to a chip select signal, wherein the pulse signal has a width corresponding to a normal read/write operation period of the memory device.