Patent ID: 7613884
Filing Date: 2009-11-03
Classification: G06F

Abstract:
1. A multiprocessor having a shared main memory, which includes a plurality of nodes connected to one another, each node comprising: a main memory having a plurality of memory regions for storing data; a cache memory for storing a copy of data obtained from said main memory; a CPU for accessing said main memory and said cache memory and processing data; a directory for storing directory information on the plurality of memory regions of the main memory, a same directory bit being assigned to the plurality of memory regions having a same cache index of an address for accessing the main memory and the cache memory, wherein the directory includes a plurality of directory entries, the directory entries each including a directory bit having one bit per a plurality of the memory regions having the same cache index and the directory bit indicating whether the cache memory of another node stores a copy of at least a part of memory regions in said main memory of one node being managed by the directory bit; and a memory control unit for checking, when the node accesses said main memory, the directory bit corresponding to a memory region to be accessed; and multicasting or broadcasting an access address to all other nodes to perform coherency control if said directory bit is set to a predetermined value and, if none of said directory bit is set to said predetermined value, performing no coherency control.