Patent ID: 6864169
Filing Date: 2005-03-08
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor integrated circuit device, comprising the steps of: (a) forming a first interconnection groove in a first interlayer insulating film over a first main surface of a wafer; (b) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection groove; (c) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove; (d) removing the first interconnection metal film outside the first interconnection groove by first chemical mechanical polishing using slurry containing abrasive grains in an amount of less, than 0.5 wt. %; (e) removing the first barrier metal film outside the first interconnection groove by second chemical mechanical polishing; and thereafter (f) performing ammonia plasma treatment to the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film; and thereafter (g) forming a copper diffusion barrier insulating film over the first main surface.