Patent ID: 7171576
Filing Date: 2007-01-30
Classification: G06F

Abstract:
1. A clock circuit, comprising: a duration timer for counting to a predetermined duration using a reference clock signal, the duration timer issuing a stop signal when the predetermined duration is reached; a bus clock determining circuit, coupled to the duration timer, the bus clock determining circuit providing a bus clock determination value by monitoring a bus clock until the duration timer issues the stop signal; a controller, coupled to the bus clock determining circuit, the controller receiving the bus clock determination value and generating independent control signals based on the determined bus clock determination value and predetermined clock frequency targets; and a clock signal generator, coupled to the controller, for receiving the independent control signals from the controller and generating a plurality of clock signals at predetermined clock frequency targets in response to the independent control signals; wherein the bus clock determining circuit further comprises a reference clock for generating the reference clock signal and wherein the controller monitors whether a reset is received, re-initiates the duration timer and resets the bus clock determining circuit after the bus clock determining circuit is signaled to stop monitoring the bus clock when a reset is received, and determines whether the counter value has changed.