Patent ID: 6370621
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A multiprocessing computer system comprising:a plurality of processing nodes interconnected through an interconnect structure, wherein said plurality of processing nodes includes: a first processing node configured to initiate a first read operation to read data from a designated memory location; a second processing node configured to respond to said first read operation by initiating a second read operation to read and transfer said data from said designated memory location to said first processing node; and a third processing node configured to transmit a memory cancel response to said second processing node upon detecting within said third processing node a modified copy of said designated memory location, and wherein said memory cancel response causes said second processing node to abort further processing of said second read operation; wherein said second processing node is configured to transfer said data read during said second read operation by transmitting a first read response to said first processing node, and wherein said memory cancel response causes said second processing node to cancel transmission of said first read response when said second processing node receives said memory cancel response prior to transmitting said first read response.