Patent ID: 6218254
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide and a second layer of silicon carbide, the method comprising:forming a trench in the second silicon carbide layer, the trench having a bottom wall and opposing side walls;conformally depositing a spacer layer having a predetermined thickness on the second semiconductor layer, including the bottom wall and side walls of the trench;anisotropically etching the spacer layer from a portion of the bottom wall of the trench between the side walls, thereby exposing a portion of the bottom wall of the trench while at least a portion of the spacer layer remains on the side walls;doping a region below the exposed portion of the bottom wall with a dopant to create a doped well region below the bottom wall; andremoving the spacer layer.