Patent ID: 7500124
Filing Date: 2009-03-03
Classification: G06F

Abstract:
1. A method of operating an electronic device that includes a Central Processing Unit (CPU) and a main system bus, the method comprising: decreasing an operational clock frequency of the CPU from a first clock frequency and of the main system bus from a second clock frequency that is lower than the first clock frequency, to a third clock frequency that is lower than the second clock frequency, and decreasing an operating voltage of the CPU, responsive to an operational mode of the CPU switching to an idle mode, wherein the switching of the operational mode of the CPU to an idle mode triggers the decreasing of the operational clock frequency of the CPU and of the main system bus; and increasing the operational clock frequency of the CPU and of the main system bus from the third clock frequency to the first clock frequency and to the second clock frequency, respectively, and increasing the operating voltage of the CPU, responsive to the operational mode of the CPU switching to an active mode, wherein the electronic device further includes a display and wherein increasing the operational clock frequency of the CPU and of the main system bus and increasing the operating voltage of the CPU are performed during an interrupt service routine generated in synchronization with a vertical synchronization signal of the display, and further wherein increasing the operational clock frequency of the CPU and of the main system bus and increasing the operating voltage of the CPU are performed during a horizontal scan period of the display.