Patent ID: 6184548
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A twin bit DRAM cell fabricated on a semiconductor substrate having a surface implanted with a material of a first conductivity type, to retain two bits of digital data, comprising:a) a first pass transistor having a source connected to a first bit line voltage generator, a gate connected to a word line voltage generator, and a drain;b) a trench capacitor in close proximity of said first pass transistor formed within the semiconductor substrate, whereby said trench capacitor includes a top plate connected to said drain of said first pass transistor, a bottom plate connected to a first biasing voltage source, and a first capacitor dielectric separating said top and bottom plates;c) a second pass transistor having a source connected to a second bit line voltage generator, a gate connected to a word line voltage generator, and a drain;d) a stack capacitor formed above the semiconductor substrate, having a first plate connected to the drain of the second pass transistor, a second plate connected to a second biasing voltage source, and a second capacitor dielectric separating said first and second plates; ande) an insulating layer placed between said trench capacitor and said stack capacitor to electrically isolate the trench capacitor from the stack capacitor.