Patent ID: 6232636
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A lateral thin-film Silicon-On-Insulator (SOI) device comprising a semiconductor substrate, a buried insulating layer on said substrate, and a lateral MOS device on said buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, a lateral drift region of said first conductivity type adjacent said body region, a drain region of said first conductivity type and laterally spaced apart from said body region by said lateral drift region, and a gate electrode over a part of said body region in which a channel region is formed during operation and over at least a part of said lateral drift region adjacent said body region, said gate electrode being insulated from said body region and drift region by an insulation region, said lateral drift region having a graded lateral doping profile, a first portion of said lateral drift region adjacent said body region having a first substantially linearly graded lateral doping profile having a first doping profile slope, and a second portion of said lateral drift region adjacent said drain region having a second substantially linearly graded lateral doping profile having a second doping profile slope which is greater than that of said first doping profile slope, wherein said insulation region has a discontinuity in thickness at a point above said drift region and adjacent said body region, and a transition from said first doping profile slope to said second doping profile slope in said lateral drift region occurs in a region of said drift region approximately beneath said discontinuity.