Patent ID: 7360009
Filing Date: 2008-04-15
Classification: G06F

Abstract:
1. A data transfer apparatus comprising: an externally-writable memory including primary memory areas corresponding to the first and second buses; registering means for registering relay information showing an amount of data to be relayed from a target to a master, in a primary memory area, the target being one of the first and second devices that is a data source whereas the master being a different one of the first and second devices that is a data destination, wherein the relay information shows one out of (a) a number of sets of data to be relayed, each set of data having a bit length equivalent to a width of the bus, and (b) a total size of data to be relayed, storing means for storing data read from the target, into a temporary storage; and master functioning means for reading data from the target while occupying the bus to which the target is connected, until an amount of data stored in the temporary storage reaches the amount shown by the relay information in the primary memory area before releasing the bus.