Patent ID: 7962702
Filing Date: 2011-06-14
Classification: G06F

Abstract:
1. An integrated circuit for executing a sequence of data loaded from an external storage element and ensuring authenticity of the sequence of data, the sequence of data including a first set of instructions having a first classification level and subsequent sets of instructions having other classification levels, the integrated circuit comprising: an interface that connects to segregated storage locations of the external storage element and loads the first set of instructions from a first storage location of the external storage element and the subsequent sets of instructions from other storage locations of the external storage element, the first set of instructions having a first classification level and subsequent sets of instructions having other classification levels; a first memory bank disposed on the integrated circuit and coupled with the interface that stores the first and subsequent sets of instructions; a second memory bank disposed on the integrated circuit and coupled with the interface that stores the second and subsequent sets of instructions; a zeroizer coupled with the first memory bank and the second memory bank that zeroizes the first memory bank before storing the first set of instructions and zeroizes the second memory bank before storing the second set of instructions and then alternatingly zeroizes the first and second memory banks for subsequent sets of instructions, the zeroizer configured to delete and erase data stored within said first memory bank and the second memory bank, the zeroizer configured to write a continuous pattern of at least one of ones or zeros within a memory bank to remove residual information retained in the memory bank; and a processor alternately coupled with the first memory bank that executes the first set of instructions and the second memory bank that executes the second set of instructions and alternates between the first and second memory banks for subsequent sets of instructions, the processor having partition switching capability for enforcing the first classification level and subsequent classification levels, wherein the second set of instructions is loaded into the second memory bank while the first set of instructions is being executed by the processor, and the processor performs a partition switch before executing the second set of instructions for ensuring the authenticity of the sequence of data, the processor writes at least one of unexecuted code or data entered by a user from at least one of the first memory bank or the second memory bank to said external storage element, while the second set of instruction is being executed, prior to zeroizing the at least one of the first memory bank or the second memory bank.