Patent ID: 6753623
Filing Date: 2004-06-22
Classification: H02M

Abstract:
A switched capacitor array circuit coupled between an input node and an output node and capable of providing multiple gain state values, said array circuit including:an L bank of capacitor positions disposed intermediate the input node and a third node, with the L bank capacitor bank positions consisting of series capacitor positions and parallel capacitor positions; an M bank of capacitor positions disposed intermediate the input node and the output node, with the M bank capacitor bank positions consisting of series capacitor positions and parallel capacitor positions; an N bank of capacitor positions disposed intermediate the output node and the third node, with the N bank capacitor bank positions consisting of series capacitor positions and parallel capacitor positions; first, second and third capacitors; switching circuitry coupled to the capacitors and to the input node, the output node and third node; and control circuitry coupled to the switching circuitry and configured to switch the switched capacitor array circuit between a common phase configuration and a gain phase configuration so as to provide a gain state value, with the first and second capacitors being disposed in one of the L, M and N bank of capacitor positions and the third capacitor is disposed in a different one of the L, M and N bank of capacitor positions in the common phase configuration, wherein when switching from the common phase configuration to the gain phase configuration, at least one of the first, second and third capacitors is moved to a different capacitor position and wherein capacitors that are disposed in the series capacitor position in the common phase configuration are disposed in the parallel capacitor position in the gain phase configuration and wherein capacitors that are disposed in the parallel capacitor position in the common phase configuration are disposed in the series capacitor position in the gain phase configuration.