Patent ID: 8525552
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising: a first standard cell which has a first cell width and in which a MOS transistor constituting a circuit has a first gate length; a second standard cell which has the same logic as that of the first standard cell and has a second cell width larger than the first cell width, and in which a MOS transistor constituting a circuit has the first gate length; and a third standard cell which has the same logic as that of the first and second standard cells and has the second cell width, and in which a shape of a gate of a MOS transistor constituting a circuit is different from that of the second standard cell, wherein the third standard cell includes at least one MOS transistor having a second gate length larger than the first gate length.