Patent ID: 8738350
Filing Date: 2014-05-27
Classification: G06F

Abstract:
1. A method of simulating a design specified through a hardware description language (HDL), the method comprising: running an integrated logic simulator, the integrated logic simulator including a serial simulation engine and a concurrent simulation engine, each of the serial simulation engine and the concurrent simulation engine for performing logic simulations; partitioning the design into two groups of modules executed by the integrated logic simulator, the two groups including a first group of modules for evaluation on the serial simulation engine and a second group of modules for evaluation on the concurrent simulation engine; performing simulation using the serial simulation engine, which performs one simulation at a time; performing simulation using the concurrent simulation engine, which performs multiple, concurrent simulations; and using a computer, synchronizing simulations of the serial simulation engine and the concurrent simulation engine based on classes of events defined by an execution model of the HDL.