Patent ID: 6414875
Filing Date: 2002-07-02
Classification: G11C

Abstract:
A nonvolatile memory having NOR architecture, comprising:a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration; a plurality of bit lines; the memory cells arranged in a same column being connected to one of the plurality of bit lines; a column decoder, said column decoder including: a programming voltage source stage; a decoder stage generating first bit line addressing signals; a plurality of selection stages, each of which is connected to respective bit lines and receives said first bit line addressing signals, said selection stages each having word programming selectors controlled by said first bit line addressing signals and connecting said programming voltage source stage to only one of said bit lines; a string decoding circuit generating second bit line addressing signals, each said selection stage having a string programming selection circuit controlled by said second bit line addressing signals and simultaneously connecting said programming voltage source stage to a plurality of said respective bit lines.