Patent ID: 7317228
Filing Date: 2008-01-08
Classification: H01L

Abstract:
1. Silicided NMOS fingers comprising: gates; a source between the gates; drains; and at least one segmented drain diffusion proximate at least one of the drains, disposed generally between the at least one drain and at least one of the gates, wherein said segmented drain diffusion comprises a plurality of self-ballasting resistors, and wherein each of said drains includes drain contacts and wherein each self-ballasting resistor is aligned with a drain contact, wherein a segmented diffusion width ratio is defined as where N is the number of self-ballasting resistors in each NMOS finger, Wsb is the width of each self-ballasting resistor, Wg is a width of the gate, and wherein said self-ballasting resistors are sized and configured such that k<0.5.