Patent ID: 6537861
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A method for fabricating an SOI field effect transistor having a source and a drain separated by a gate disposed along a gate axis, a body region disposed below said gate and a body contact, in which said body contact is isolated from said gate, said source and said drain by a body isolation trench located in a body isolation trench region of said transistor, characterized by the steps of:a) preparing an SOI substrate including a device layer, having a device layer thickness, disposed above and in contact with a buried insulating layer having a buried layer thickness; b) depositing a trench pattern layer on the surface of said device layer; c) etching a shallow trench isolation pattern covering shallow isolation trenches and said body isolation trench region into said pattern layer, thereby exposing said device layer in said shallow trench isolation pattern; d) depositing a blocking layer above said body isolation trench region; e) etching said device layer in said shallow trench isolation pattern down to a first depth less than said device layer thickness by an amount substantially equal to a body isolation depth of said body isolation trench; f) removing said blocking layer and etching said device layer down to said buried layer in said shallow isolation trenches, whereby, simultaneously with the etching of said shallow isolation trenches, said body isolation region is etched to said body isolation depth less than said device layer thickness, so that a conductive path extends in said device layer along said gate axis from said body region to said body contact; g) filling the trenches formed in said etching step with an insulating material and planarizing the surface of the resulting structure; and h) completing said transistor.