Patent ID: 9106238
Filing Date: 2015-08-11
Classification: G06F,H03M,Y02D

Abstract:
1. A sorting decoder comprising: a dynamic reference generator configured to generate a monotonic dynamic reference signal; a set of n comparators, each comparator configured to operate on (i) a respective input signal and (ii) the monotonic dynamic reference signal, the set of n comparators configured to form a set of n comparator outputs; and, a set of n single wire rank decoders (SWRD), each SWRD configured to receive (i) an associated clock signal corresponding to a comparator output of a unique comparator and (ii) n−1 data inputs corresponding to comparator outputs not used as the associated clock, and wherein each SWRD is configured to output a snapshot vector comprising values of the n−1 comparator outputs present during a rising and/or falling edge of the associated clock signal, wherein the snapshot vector corresponds to an amplitude ranking of the input signal of the unique comparator.