Patent ID: 6825086
Filing Date: 2004-11-30
Classification: H01L

Abstract:
In a strained-silicon channel CMOS device using a relaxed silicon germanium (SiGe) layer, a method for forming a sacrificial shallow trench isolation (STI) oxide liner, the method comprising:forming a silicon (Si) substrate; forming a relaxed-SiGe layer overlying the Si substrate; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.