Patent ID: 6563155
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A dynamic random access memory (DRAM) device comprising:(a) a substrate of semiconductor material having a main outer surface; (b) a plurality of substantially parallel word lines located outwardly of said main outer surface of said substrate, each of said word lines having a word line width defined by first and second word line edges and being separated from adjacent word lines by a word line separation distance; (c) a plurality of substantially parallel bit lines located outwardly of said main outer surface of said substrate, each of said bit lines having a bit line width defined by first and second bit line edges and being separated from adjacent bit lines by a bit line separation distance, said bit lines being substantially perpendicular to said word lines; and (d) a plurality of memory cells each associated with an intersection of a given one of said first and second word line edges of a given one of said word lines and a given one of said first and second bit line edges of a given one of said bit lines, each of said memory cells in turn comprising: (i) a pillar of semiconductor material extending outward from said main outer surface of said substrate and being electrically isolated from adjacent memory cells, said pillar having a pillar outer surface, said pillar forming an active region substantially centered at said intersection, said pillar including a hole region with a hole floor and at least one hole wall, said hole floor being located outwardly of said main outer surface of said substrate and said at least one hole wall forming the channel of a MOS transistor; (ii) a storage node offset from said active region of said pillar in a direction away from said given one of said word lines and said given one of said bit lines; (iii) a storage node plug extending from said storage node through said hole region in said pillar to contact said hole floor and form thereat a storage node contact and one of a drain and a source of a MOS transistor, said storage node plug being electrically isolated from said at least one hole wall; (iv) a bit line plug extending from said given one of said bit lines inwardly to contact said pillar outer surface and form thereat a bit line contact and another of a drain and a source of said MOS transistor; and (v) a word line plug extending from said given one of said word lines through said hole region in said pillar and terminating outwardly of said hole floor, said word line plug being electrically isolated from said at least one hole wall and said hole floor such that a portion of said word line plug adjacent to and electrically isolated from said at least one hole wall forms a gate of said MOS transistor.