Patent ID: 7977763
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A chip package comprising: a first polymer layer; a semiconductor die between a first portion of said first polymer layer and a second portion of said first polymer layer, wherein said semiconductor die has a top surface substantially coplanar with a top surface of said first polymer layer; a second polymer layer on said semiconductor die and said first polymer layers, wherein said second polymer layer has a thickness between 5 and 100 micrometers; a first patterned metal layer over said semiconductor die, said second polymer layer and said first polymer layer, wherein said first patterned metal layer is connected to said semiconductor die through an opening in said second polymer layer, wherein said first patterned metal layer comprises an electroplated metal and has a thickness between 1 and 150 micrometers, wherein said first patterned metal layer comprises a piece as a part of a capacitor; a third polymer layer on said first patterned metal layer and over said second polymer layer, said semiconductor die and said first polymer layer, wherein said third polymer layer has a thickness between 1 and 150 micrometers; and a metal bump vertically over said first polymer layer, wherein said metal bump is connected to said semiconductor die through said first patterned metal layer.