Patent ID: 6246087
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A memory cell structure for a semiconductor memory device, comprising:a semiconductor substrate having a first conductivity type;a plurality of active regions and isolation regions in the semiconductor substrate, the active regions each having first and second diffusion regions to form a transistor;a plurality of word lines on the semiconductor substrate and each acting as a gate electrode of a corresponding transistor;a first insulation layer on the semiconductor substrate including the word lines;a plurality of contact holes each exposing one of the first diffusion regions through the first insulation layer;a plurality of bit lines crossingly arranged over the word lines and contacting a corresponding first diffusion region through the contact hole, wherein each bit line includes a first extension portion extended from the bit line contacting the first diffusion region and a second extension portion extended from the bit line over the isolation regions;a second insulation layer on the plurality of bit lines and the first insulation layer;an electrode contact hole exposing the second diffusion region through the first and the second insulation layers;a plurality of capacitor lower electrodes on the second insulation layer and contacting a corresponding second diffusion region through the electrode contact hole;a capacitor dielectric layer on the capacitor lower electrode; anda capacitor upper electrode on the capacitor dielectric layer.