Patent ID: 8935584
Filing Date: 2015-01-13
Classification: G01R,G11C

Abstract:
1. A system for performing a scan test and memory built-in self test (BIST) on an integrated circuit (IC), the system comprising: a bypass-signal generator that generates a first bypass signal based on a chip package information, the first bypass signal indicating whether a first scan chain associated with a first non-common functional circuit block of the IC is to be bypassed; and a first scan-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for bypassing the first scan chain in response to the first bypass signal; a first built-in self test (BIST) controller associated with a first non-common memory block of the IC; and a first BIST-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for gating off an output of the first BIST controller in response to the first bypass signal.