Patent ID: 6391731
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method to form MOS transistors in the manufacture of an integrated circuit device comprising:providing conductive gates overlying a semiconductor substrate; forming temporary sidewall spacers on said gates; thereafter implanting ions into exposed said semiconductor substrate to form a first amorphous layer having a first depth; thereafter implanting ions into said first amorphous layer to form pre-annealed source and drain junctions; thereafter removing said temporary sidewall spacers; thereafter implanting ions into exposed said semiconductor substrate to form a second amorphous layer having a second depth shallower than said first depth; thereafter implanting ions into said second amorphous layer to form pre-annealed source and drain extensions; and thereafter irradiating said semiconductor substrate with laser light to melt said first and second amorphous layers while crystalline regions of said semiconductor substrate remain in solid state to thereby diffuse ions in said pre-annealed source and drain junctions into said first amorphous layer and to diffuse ions in said source and drain extensions into said second amorphous layer and to complete formation of said MOS transistors.