Patent ID: 7386768
Filing Date: 2008-06-10
Classification: G06F,Y02D

Abstract:
1. A memory buffer comprising: an inbound redrive circuit to receive and redrive signals on an inbound path, the inbound redrive circuit having a plurality of input/output (I/O) cells, each I/O cell providing, at least in part, a bit-lane for a unidirectional point-to-point channel between a first memory agent and a second memory agent a failover circuit coupled with the inbound redrive circuit, the failover circuit capable of redirecting a signal from a first bit-lane of the unidirectional point-to-point channel to a second bit-lane of the unidirectional point-to-point channel; an outbound redrive circuit to receive and redrive signals on an outbound path; a memory interface to couple the memory buffer to a plurality of memory devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit; and deskew logic coupled between the outbound redrive circuit and the memory interface to reduce skew between bits of data received from the outbound redrive circuit, wherein the memory buffer is capable of selectively disabling the outbound redrive circuit if it is the last agent on the channel.