Patent ID: 7898871
Filing Date: 2011-03-01
Classification: G11C

Abstract:
1. A flash memory device capable of running in a single speed operating mode and a double speed operating mode, and comprising: a memory cell array comprising a plurality of bit lines associated with a first mat and a second mat; first and second read/write (R/W) circuits respectively performing an operation with respect to the first and second mats, wherein the operation comprises a bit line set-up interval during which a precharge operation is performed and at least one additional interval; and a controller controlling operation of the first and second R/W circuits during the double speed operating mode, such that during the bit line set-up interval, the precharge operation is carried out in a time division approach with respect to the first and second mats, wherein the operation is one of a read operation, a program operation, and an erase operation, the bit lines associated with each of the first and second mats are divided into a first group and a second group, and bit lines of the first group in the first and second mats are pre-charged in a time division approach with respect to the bit lines of the second groups in the first and second mats.