Patent ID: 6184075
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of forming a portion of a semiconductor device, wherein the formed semiconductor device has at least one storage cell disposed in a cell array portion of a semiconductor memory device, and also has a peripheral circuit area disposed in a peripheral portion of the semiconductor memory device over a semiconductor substrate, the method comprising the steps of:forming a storage electrode in the cell array portion;forming a first conductive layer over the storage electrode, wherein the storage electrode and the first conductive layer comprise a storage cell capacitor for the semiconductor device, and the first conductive layer is patterned to form an interconnect line of the semiconductor device;forming an insulation layer overlying the first conductive layer;forming a contact hole extending from the top surface of the insulation layer, through the first conductive layer to the surface of the semiconductor substrate in the peripheral surface area in the semiconductor memory device; andforming a second conductive layer filling the contact hole so as to provide an electrical connection with the first conductive layer and the semiconductor substrate in the peripheral circuit area.