Patent ID: 8149626
Filing Date: 2012-04-03
Classification: G11C

Abstract:
1. A memory integrated circuit comprising: a memory array, wherein the memory array includes a plurality of memory cells arranged along a wordline within the memory array, and wherein each memory cell respectively comprises a transistor having a threshold voltage; a wordline decoder configured to input a ramp voltage to the wordline so that the ramp voltage is applied to gates of the plurality of transistors on the wordline, wherein the ramp voltage being applied to the gates of the plurality of transistors is configured to increase based on an incrementing digital code; a plurality of current sensing amplifiers, wherein each current sensing amplifier is respectively in communication with a corresponding transistor in the memory array along a respective bit line within the memory array, and wherein each current sensing amplifier is configured to generate a control signal in response to sensing a predetermined threshold current along the respective bitline; and a plurality of registers, wherein each register corresponds respectively to a corresponding transistor in the memory array, and wherein each register is configured to latch a current value of the incrementing digital code in response to the current sensing amplifier in communication with the corresponding transistor generating the control signal, wherein the current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor.