Patent ID: 6339541
Filing Date: 2002-01-15
Classification: G11C,H01L

Abstract:
A memory integrated circuit comprising:(a) a plurality of memory cells associated together in a memory cell array; (b) a sense amp band associated with said memory cell array and having a plurality of sense amplifiers positioned therein, said sense amp band extending in a first direction; (c) a column decoder circuit associated with at least some of said sense amplifiers and having a column select line electrically coupled thereto as an output thereof, said column select line extending in said first direction through said sense amp band and further being electrically coupled to one of said sense amplifiers in said sense amp band; (d) a local data line coupled to a plurality of said sense amplifiers and extending in said first direction through said sense amp band; (e) a global data line coupled to said local data line and extending in a second direction across said memory cell array, said second direction being generally transverse to said first direction; (f) a power line extending in said second direction across said memory cell array to provide power for said memory integrated circuit; and (g) a ground line extending in said second direction across said memory cell array to provide a reference voltage for said memory integrated circuit.