Patent ID: 7266580
Filing Date: 2007-09-04
Classification: G06F

Abstract:
1. A binary multiplier for a super-scalar processor comprising: an input merge register configured to receive a first operand comprising multiplicand data of up to m bits in length, wherein m bits includes at least one of a full width of a register for the processor or a maximum width of an operand data for a selected binary multiplication instruction; recording logic configured to receive a second operand comprising one of a multiplier value and a multiplier value subgroup comprising a partition of said multiplier value of n bits in length, wherein n is less than or equal to a maximum width an operand data for a selected binary multiplication instruction; transform logic configured to receive a first control signal indicative of a size of said multiplicand data that enables said multiplier to select from said multiplicand data input relevant bits to form an effective multiplicand and zeroing out of unused bits of said multiplicand data input; and said transform logic further configured to receive a second control signal indicative of whether said multiplicand operation is signed or unsigned, and configured to enable said multiplier to sign-extend said effective multiplicand.