Patent ID: 7058665
Filing Date: 2006-06-06
Classification: G06F,Y10S

Abstract:
1. A computer-implemented method for testing data coherency in a file system implemented on a data processing arrangement, comprising the steps: maintaining a record of file addresses not targeted by write operations; selecting a word address range for each write operation from the record of file addresses not targeted by other write operations; allocating a plurality of I/O packets and respectively associated I/O buffers; creating at least one I/O group that includes a plurality of I/O packets associated with respective I/O buffers, each I/O group having an associated group address range, wherein the I/O packets in the group are configured with write operations that address overlapping subranges of the group address range, and each respective I/O buffer contains data different from data in the other respective I/O buffers; selecting a group address range for an I/O group from the record of file addresses not targeted by other write operations; issuing a plurality of asynchronous write operations that specify word address ranges and data to be written, wherein each write operation in an I/O packet is issued with data to be written to a file stored in the associated I/O buffer; for each completed write operation, issuing an asynchronous read operation in the I/O packet used for the write operation and referencing the address range of the completed write operation and providing the associated I/O buffer for data read from the file; when write operations within an I/O group are complete, issuing an asynchronous read operation referencing the address range of the I/O group; verifying data returned from the read operation against data issued in the completed write operation; and updating the record of file addresses not targeted by write operations when the verifying step is complete.