Patent ID: 6168999
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET), comprising the sequential steps of: (a) providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; (b) forming a spacer at the spacer area; (c) performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, wherein the spacer facilitates formation of a lateral asymmetric channel; (d) forming heavily doped extensions in the source side and the drain side, wherein the spacer prevents doping in the spacer area; (e) removing the spacer; and (f) forming a lightly doped extension in the drain side, wherein the heavily doped extensions and the lightly doped extension prevent hot carrier injection.