Patent ID: 6483331
Filing Date: 2002-11-19
Classification: G01R

Abstract:
A tester for a semiconductor device comprising:a test board having a first electrode pad, a first power source pad and a second power source pad, the first electrode pad being arranged in correspondence to a signal pin of the semiconductor device, the first and the second power source pads being arranged in separation from the first electrode pad; a first intermediate board having a third power source pad, a fourth power source pad and a first hole, the third power source pad corresponding to the first power source pin of the semiconductor device, the fourth power source pad being electrically connected to the third power source pad and corresponding to the first power source pad of the test board, the first hole corresponding to the second power source pin of the semiconductor device; a second intermediate board having a fifth power source pad, a sixth power source pad and a second hole, the fifth power source pad being arranged between the first intermediate board and the test board and being in correspondence to the second power source pin of the semiconductor device, the sixth power source pad being electrically connected to the fifth power source pad and being in correspondence to the second power source pad of the test board, the second hole being in correspondence to the fourth power source pad; a first conductive sheet arranged between the first intermediate board and the semiconductor device, the first conductive sheet electrically connecting the first power source pin of the semiconductor device and the third power source pad of the first intermediate board; a second conductive sheet arranged between the first intermediate board and the second intermediate board, the second conductive sheet electrically connecting the second power source pin of the semiconductor device and the fifth power source pad of the second intermediate board via the first hole of the first intermediate board and the first conductive sheet; and a third conductive sheet arranged between the second intermediate board and the test board, the third conductive sheet electrically connecting the sixth power source pad of the second intermediate board and the second power source pad of the test board, and electrically connecting the fourth power source pad of the first intermediate board and the first power source pad of the test board via the second hole of the second intermediate board and the second conductive sheet.