Patent ID: 8497174
Filing Date: 2013-07-30
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a plurality of first device isolation layers in a substrate as a pattern of lines, the plurality of first device isolation layers extending in a first direction and having a first depth from an upper surface of a substrate, to define a plurality of active regions that extend in the first direction as a pattern of lines; forming a plurality of trenches that extend in a second direction perpendicular to the first direction and that have a second depth smaller than the first depth, and a first width; etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth; forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches; and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches.