Patent ID: 6404697
Filing Date: 2002-06-11
Classification: G11C

Abstract:
An apparatus for outputting data included in a synchronous memory device, the apparatus comprising:first storage moans for storing in sequence even data provided by a first sense amplifier coupled to a selected even bank; second storage means for storing in sequence odd data provided by a second sense amplifier coupled to a selected odd bank; third storage means for storing data and for providing data in synchronization with a rising edge of a clock signal; fourth storage means for storing data and for providing data in synchronization with a falling edge of the clock signal; selection means coupled to the first storage means, the second storage means, the third storage means, and the fourth storage means; the selection means for receiving at substantially the same time even data from the first storage means and odd data from the second storage means and selectably driving the even data to one of the third storage means and the fourth storage means while driving the odd data to the other of the third storage means and the fourth storage means; and data output means for driving data from the third storage means and data from the fourth storage means to an output node.