Patent ID: 6194307
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A method for forming copper damascene conducting lines on the surface of a semiconductor substrate, a layer of intra-level dielectric having been deposited on the surface of said substrate with a pattern of copper damascene conducting lines created within the layer of intra-level dielectric, said layer of intra-level dielectric having a partially exposed surface, said pattern of copper damascene conducting lines comprising a barrier layer of TaN/Ta having a thickness within the range of between 150 and 500 Angstrom in addition to a seed layer of copper having a thickness within the range of between 1000 and 2200 Angstrom, said barrier and seed layers to be formed between sidewalls and bottom of holes for said pattern in said intra-level dielectric and sidewalls and bottom of said pattern of copper damascene conducting lines, said pattern of copper damascene conducting lines having been polished by applying methods of Chemical Mechanical Polishing, said method comprising the steps of:depositing a layer of Ta or TaN/Cu over said pattern of copper damascene conducting lines, said depositing to include said partially exposed surface of said intra-level dielectric;depositing a thin layer of copper to a thickness between about 1000 and 3000 Angstrom over said layer of Ta or TaN/Cu; andpolishing said thin layer of copper by applying methods of Chemical Mechanical Polishing.