Patent ID: 9130547
Filing Date: 2015-09-08
Classification: H03K

Abstract:
1. A circuit comprising: a PMOS (p-channel metal oxide semiconductor) transistor pair receiving a first voltage at a first circuit node and a second voltage at a second circuit node and outputting a third voltage at a third circuit node and a fourth voltage at a fourth circuit node; an NMOS (n-channel metal oxide semiconductor) transistor pair receiving the third voltage at the third circuit node and the fourth voltage at the fourth circuit node and outputting the first voltage at the first circuit node and the second voltage at the second circuit node; a first voltage-controlled resistor (VCR) controlled by a first control voltage and a second control voltage in accordance with a first clock signal providing a coupling between the third voltage at the third circuit node and the second voltage at the second circuit node; and a second VCR controlled by the second control voltage and the first control voltage in accordance with a second clock signal providing a coupling between the fourth voltage at the fourth circuit node and the first voltage at the first circuit node.