Patent ID: 6294960
Filing Date: 2001-09-25
Classification: H03L,H04L

Abstract:
A phase lock loop circuit using a signal estimator, for detecting and correcting a phase shift contained in a received signal and, in addition, removing transmission path distortion, said phase lock loop comprising:a signal estimator for estimating a transmission signal series using a Viterbi algorithm from the received signal and outputting the transmission signal series as an estimated signal and, in addition, outputting a minimum path metric history signal obtained as a result of temporary estimation of the signal from the current path status without traceback in the Viterbi algorithm;switching means which, when a control signal is active, selectively outputs the estimated signal, and, when the control signal is inactive, selectively outputs the minimum path metric history signal;replica generating means for generating a replica signal using a signal selected by the switching means;feedback loop means for detecting a phase difference contained in the received signal from the replica signal and the received signal to correct the phase difference; andcontrol signal generating means for rendering the control signal inactive only for a predetermined certain period from the start of the operation of the feedback loop means.