Patent ID: 7515594
Filing Date: 2009-04-07
Classification: H04L,H04Q

Abstract:
1. A method of assigning paths through an interconnection network consisting of a plurality of switching elements and a plurality of links coupling the switching elements, the method comprising the steps of: using physical restrictions of the interconnection network to arrive at a logical representation of an architecture of the interconnection network; determining traffic patterns of the interconnection network to balance the data traffic through the links coupling the switching elements; using the logical representation and traffic patterns of the interconnection network to setup a virtual circuit identifier table that represent path selection formulas so that duplex data traffic is more evenly distributed through the interconnection network; and determining, based on packet header information, whether a data path controller, which will be using the virtual circuit identifier table, is on a high speed board that performs traffic stripping or on a low speed board; wherein the switching elements are arranged in rows and columns, and each column represents a stage, wherein the interconnection network includes four stages; and wherein if the data path controller is not on a high speed board that performs traffic stripping, then the path selection formula as: ^ is an exclusive OR; a, b, c, d, e are binary bits (0 or 1) defining a path selection value; i is an input link number in a first-stage switching element, wherein i[x] is a binary bit and [x] represents a bit position selected from possible bit positions (0 to 6); and j is an output link number in a last-stage switching element, wherein j[y] is a binary bit and [y] represents a bit position selection from seven possible bit positions (0 to 6).