Patent ID: 6415190
Filing Date: 2002-07-02
Classification: G06F

Abstract:
Method for the execution by a single processor of several functions each grouping together several tasks, the processor having addressing access to an addressable space including memories for a program and for data, and input and output registers allowing the processor to communicate with its environment, wherein the method comprises the steps of:allocating a right of access to each function to be executed by the processor, dividing the space addressable by the processor into addressable partitions and associating each addressable partition with the access right of one of the functions, in such a way as to allow each function to access at least one addressable partition, dividing the time of use of the processor into cyclic time slices, and associating each cyclic time slice with the access right of one of the functions, in such a way that each function is executed in the course of at least one time slice, at the start of each new time slice, confirming that the processor has terminated the execution of the previous function, and transmitting an error signal to the processor if the execution of the previous function has not terminated, updating a current access right corresponding to the access right associated with the new time slice, and activating the tasks of the corresponding function, and during each access by the processor to an addressable partition, reading the access right associated with the accessed partition, comparing this access right with the access right associated with the current time slice, and transmitting an error signal to the processor in the case in which the comparison reveals an inconsistency.