Patent ID: 8243504
Filing Date: 2012-08-14
Classification: G11C

Abstract:
1. A phase change memory device comprising: a cell array block comprising one or more phase change resistance cells, each phase change resistance cell being formed at an intersection of one or more word lines and one or more bit lines; a reference cell array block configured to output a reference current, the reference cell array block comprising one or more reference cells, each reference cell being formed at an intersection of a word line and a reference bit line; a column selecting unit connected to each of the one or more bit lines of the cell array block and configured to select one or more of the one or more bit lines connected to the cell array block; a reference column selecting unit connected to the reference bit line of the reference cell array block and configured to select the reference bit line; and a sense amplifier connected to the column selecting unit and the reference column selecting unit and amplifying according to the reference current of the reference cell array block and a cell data current of a bit line selected by the column selecting unit.