Patent ID: 7525746
Filing Date: 2009-04-28
Classification: G11B

Abstract:
1. An apparatus for removing dc offset from a digital signal, the apparatus comprising: a first detector responsive to a corrected digital signal, wherein the first detector provides a first output comprising binary signals and a second output comprising a substantially error free detector input; a circuit to produce an error signal, wherein the error signal is the difference between the second output and the sum of an uncorrected digital signal and a dc offset correction signal, wherein the uncorrected digital signal is delayed by a first amount; and a dc offset correction feedback loop responsive to a first loop input and a second loop input, the dc offset correction feedback loop further comprising a loop filter; wherein the dc offset correction signal is the output of the dc offset correction feedback loop, wherein the first loop input is the error signal, wherein the second loop input is one of the corrected digital signal, the uncorrected digital signal, or the first output, and wherein the dc offset correction signal is added to the digital signal to provide the corrected digital signal.