Patent ID: 6829684
Filing Date: 2004-12-07
Classification: G06F

Abstract:
A computer processing apparatus comprising:effective address generating logic, said effective address generating logic generating effective addresses to be accessed, wherein at least some of said effective addresses are real addresses; at least one state register for recording processor operating parameters, said at least one state register including a mode designator, said mode designator designating an operating mode; real address range checking logic, said real address range checking logic generating an error signal responsive to detecting a real address outside a predetermined range when said real address is associated with a first operating mode, and not generating an error signal responsive to detecting a real address outside said predetermined range when said real address is associated with a second operating mode; a plurality of sets of registers for supporting the execution of a plurality of threads, each set of registers corresponding to a respective one of said plurality of threads; wherein said at least one state register for recording processor operating parameters comprises a respective mode designator associated with each thread, said mode designator designating, for each of said threads independently, a respective operating mode; and wherein said real address range checking logic generates an error signal responsive to detecting a real address outside said predetermined range when said real address is generated on behalf of a thread in said first operating mode, and does not generate an error signal responsive to detecting a real address outside said predetermined range when said real address is generated on behalf of a thread in said second operating mode.