Patent ID: 6503823
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A method for manufacturing a capacitive element integrated on a semiconductor substrate, the method comprising:forming a first dielectric layer on the semiconductor substrate; forming a first metallization layer on the first dielectric layer to include a lower plate of the capacitive element and an interconnection pad therein; forming a second dielectric layer over the first dielectric layer and at least a portion of the first metallization layer; forming a first opening through the second dielectric layer and aligned with the lower plate; forming a third dielectric layer on the second dielectric layer and the lower plate and covering sidewalls of the first opening; forming a second opening through the third dielectric layer and aligned with the interconnection pad; forming a fourth dielectric layer on the second dielectric layer and the third dielectric layer, the fourth dielectric layer being selectively etchable relative to the third dielectric layer; forming a third opening through the fourth dielectric layer to the third dielectric layer and aligned with the lower plate; forming a fourth opening through the fourth dielectric layer and through the second dielectric layer to the interconnection pad, the fourth opening being aligned with the second opening; and forming a second metallization layer in the third and fourth openings to respectively provide an upper plate for the capacitive element and an interconnection to the interconnection pad.