Patent ID: 8185711
Filing Date: 2012-05-22
Classification: G06F

Abstract:
1. A memory module, comprising: a plurality of memory units, each of the plurality of memory units including an interface receiving a packet command to generate a command signal and an address, extracting write data from the received packet command and transferring the extracted write data to memory during a write operation and receiving read data during a read operation and at least one memory device receiving the extracted write data during the write operation, and configured to output the read data during the read operation, wherein the interface transfers the extracted write data via an n-bit data line, where n is greater than zero, during the write operation, the interface receives the read data via the n-bit data line during the read operation and transmits the received read data via read data lines, the at least one memory device including at least two first memories, each of the at least two first memories directly receiving the command signal and the address in common and outputting the read data via the n-bit data line during the read operation, wherein the at least one memory device further includes at least two second memories, each of the at least two second memories directly receiving the command signal and the address in common, receiving the write data transmitted to the n-bit data line during the write operation, and transmitting the read data to the n-bit data line during the read operation.