Patent ID: 7027329
Filing Date: 2006-04-11
Classification: G11C

Abstract:
1. A semiconductor memory having a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors serially connected along a column-direction and a select transistor configured to select the memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix, the peripheral circuit comprising: a leading program circuit configured to write first data into memory cell transistors in the first cell columns; a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written into the memory cell transistors in the first cell columns; and a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns, the variation ascribable to amount of electric charges in the memory cell transistors of the second cell columns.