Patent ID: 6150198
Filing Date: 2000-11-21
Classification: G11C,H01L

Abstract:
A method for fabricating a ROM device of the type having a plurality of MOS-transistor memory cells, comprising the steps of:(1) preparing a semiconductor substrate of a first type;(2) forming a plurality of substantially parallel-spaced diffusion regions of a second type in the substrate, the plurality of diffusion regions serving as a plurality of bit lines;(3) forming a gate dielectric layer and a first conductive layer successively over the substrate;(4) performing a first photolithographic and etching process so as to remove selected parts of the first conductive layer to form a plurality of gate electrodes, each of the gate electrodes functionally connecting each neighboring pair of the bit lines, the combination of each neighboring pair of the bit lines and the associated gate electrode forms one memory cell for the ROM device;(5) forming an insulating layer over the gate dielectric layer and the plurality of gate electrodes;(6) performing a second photolithographic and etching process so as to remove selected parts of the insulating layer to expose those gate electrodes that are associated with those memory cells that are to be set to a permanently-ON state, with the unexposed gate electrodes being associated with those memory cells that are to be set to a permanently-OFF state; and(7) forming a plurality of second conductive layers over the insulating layer, the second conductive layers being substantially parallel-spaced and intercrossing the plurality of diffusion regions to serve as a plurality of word lines for the ROM device.