Patent ID: 8024697
Filing Date: 2011-09-20
Classification: G06F

Abstract:
1. A method for estimating characteristics of an electronic design system, comprising: creating a populated initial model for two or more intellectual property (IP) sub components in an IP design based on a user-supplied file having data describing a configuration of the IP design as well as user-supplied technology parameters that describe parameters of a cell based implementation technology, wherein a first IP sub component is composed of a heterogeneous mixture of processing logic, storage logic, or communications logic and is represented at least one layer of abstraction higher than a predicted Register Transfer Level (RTL) design making up the first IP sub component block; aggregating an area estimate from each IP sub-component to generate an aggregate area consumption estimate of the IP design prior to performing logic synthesis of the electronic system design; and providing the aggregate area estimate of all the IP sub components to the user via a graphic user interface prior to a RTL design file of the IP design being transformed into the gate-level circuit design.