Patent ID: 8527823
Filing Date: 2013-09-03
Classification: G01R

Abstract:
1. An electrical device comprising: A. a test data in lead, a test clock lead, a test mode select lead, and a test data out lead; B. a test access port including a test data in input coupled to the test data in lead, a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, a test data out output coupled to the test data out lead, a scan data input, a scan clock output, and a scan enable output, the test access port including: C. a test compression architecture circuit having a compressed data input coupled to the test data in lead, a compressed data output coupled to the scan data input of the test access port, a scan clock input coupled to the scan clock output from the test access port, and a scan enable input coupled to the scan enable output from the test access port.