Patent ID: 6166952
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A read-only memory, comprising:word lines, bit lines and source lines, each of said bit lines having a bit line potential;a multiplicity of memory cells connected to said word lines, said bit lines and said source lines, said memory cells having data contents and the data contents being read out with appropriate addressing of said word lines, said bit lines and said source lines, said memory cells addressed by an individual word line;said memory cells divided into a multiplicity of memory cell groups, each of said memory cell groups having a separate common source line, said memory cell groups forming a memory cell array;common data output lines, each memory cell group connected to a respective one of said common data output lines; andconnecting devices connected between said bit lines of said memory cells of said memory cell groups and said common data output lines for outputting the data contents stored in said memory cells, each of said connecting devices for putting a potential that is on one of said bit lines onto one of said common data output lines at the beginning of a read cycle while said one bit line is discharging and for subsequently actively driving said one bit line.