Patent ID: 6530002
Filing Date: 2003-03-04
Classification: G06F

Abstract:
In a computer system having a first plurality of processors, a second plurality of mass storage devices, a third plurality of adapters for providing communication between the processors and the mass storage devices, a binding mechanism for determining relationships between the processors and the adapters and a switch mechanism for establishing communication paths between the adapters and the mass storage devices, a mechanism for providing access between the processors and the mass storage devices, comprising:a binding mapper communicating with the binding mechanism for determining the mass storage devices of the plurality of mass storage devices with which each processor is to communicate, and a device driver stack address mapper responsive to the binding mapper for constructing an address map, wherein the address map contains a processor set for each mass storage device wherein each processor set includes at least one address map entry for each processor that is to communicate with the corresponding mass storage device and each address map entry defines a communication path through an adapter and the switch between a processor and a mass storage device with which the processor is to communicate.