Patent ID: 6284551
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method for fabricating a capacitor, comprising the steps of:(1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer;(2) forming a second insulating layer on an entire surface inclusive of the bitline;(3) depositing a first conductive material on the second insulating layer;(4) etching the first conductive material to form a first electrode with a sloped etch surface;(5) depositing a dielectric film on the first electrode;(6) etching the second insulating layer and the first insulating layer in succession to form a contact hole exposing the substrate;(7) depositing and etching a second conductive in the contact hole, to form a node contact; and,(8) depositing and etching a third conductive material on the node contact, to form a second electrode.