Patent ID: 6856550
Filing Date: 2005-02-15
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix; a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells; a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells; and a control circuit for performing a writing operation on said plurality of memory cells at the time of a writing operation, wherein each of said plurality of memory cells includes: first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines; and an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and said control circuit applies at least one pulse voltage to a selected memory cell in said plurality of memory cells, the memory device further comprising a counter for counting the number of times said control circuit has performed the writing operation since the memory device was shipped, wherein said control circuit varies the magnitude of a pulse voltage to be applied to a selected memory cell based on the number of times counted by said counter.