Patent ID: 9059051
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A structure for determining depth of a through-silicon via, comprising: a plurality of through-silicon via (TSV) bars formed in a semiconductor wafer, wherein the plurality of TSV bars are formed with a uniform length and interspacing; a first set of metallization lines connecting a first group of the plurality of TSV bars, wherein the first group of TSV bars forms a first capacitor node of the structure; and a second set of metallization lines connecting a second group of the plurality of TSV bars, wherein the second group of TSV bars forms a second capacitor node of the structure; and wherein the first group of TSV bars is interleaved with the second group of TSV bars, such that there is an interspacing between each TSV bar, and wherein each TSV bar has at least one neighboring TSV bar from another group.