Patent ID: 9223578
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A method for coalescing memory barrier instructions across multiple parallel execution threads, comprising: receiving a global memory barrier instruction for a first one of the multiple parallel execution threads; blocking the execution of memory transactions for the first thread that are after the global memory barrier instruction in program order; receiving a system memory barrier instruction for a second one of the multiple parallel execution threads, wherein the second thread is executed independently from the first thread; blocking the execution of memory transactions for the second thread that are after the system memory barrier instruction in program order; combining the global memory barrier instruction with the system memory barrier instruction to produce a coalesced memory barrier instruction; determining that all memory transactions for the first thread and the second thread that occur prior to the coalesced memory barrier instruction are committed to memory; and releasing the coalesced memory barrier to allow execution of the memory transactions for the first thread that are after the global memory barrier instruction in program order and for the second thread that are after the system memory barrier instruction in program order.