Patent ID: 8350832
Filing Date: 2013-01-08
Classification: G09G

Abstract:
1. A semiconductor integrated circuit device for display control comprising: a memory cell array in which a plurality of memory cells capable to store display data are arranged in an array; peripheral circuits located in the periphery of the memory cell array to enable writing of display data into the memory cell array and reading of the display data from said memory cell array; and a control circuit which is able to control read and write operations from/to the memory cell array via said peripheral circuits, wherein the memory cell array comprises a plurality of memory blocks each including a corresponding portion of the plurality of memory cells, the memory blocks being capable of storing the display data, and wherein the control circuit comprises a control logic which enables row-wise time-staggered parallel processing of write operations to the memory blocks in such a manner that, after starting and before completion of writing of data to one of the memory blocks, writing of data to another memory block is started, wherein the semiconductor integrated circuit device further comprises: a plurality of first latch circuits configured to read data from corresponding memory blocks, a transfer control circuit to rearrange output data from the plurality of memory blocks in a sequence of data line by line to be displayed by a display unit, the transfer control circuit including a selector to selectively transfer data from one of the first latch circuits; a second latch circuit configured to read data transferred from the first latch circuits through the selectors; and a source line driving circuit to drive the display unit according to the display data, wherein, when N denotes an internal memory address sequentially selected during transfer of the display data, address N and address N+1 are allocated to memory cells located in different memory blocks, and wherein the selector selects an output of one of the first latch circuits according to each memory address so as to transfer data to the second latch circuit in a time division manner according to the numerical order of memory addresses N and N+1, such that data is transferred in an alternating fashion from the different memory blocks.