Patent ID: 8685844
Filing Date: 2014-04-01
Classification: B82Y,H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a blanket layer of graphene on an exposed surface of a copper substrate; forming a blanket layer of aluminum on an exposed surface of the blanket layer of graphene; pre-patterning the blanket layer of aluminum to form a plurality of regularly spaced pits within the blanket layer of aluminum; converting the pre-patterned blanket layer of aluminum having said plurality of regularly spaced pits into a layer of porous anodized alumina, said layer of porous anodized alumina comprising a plurality of alumina portions of a first density and having an ordered lattice arrangement, and amorphous alumina portions of a second density that are adjacent to said alumina portions of the first density, wherein said first density is greater than the second density; removing the adjacent amorphous alumina portions from said layer of porous anodized alumina, wherein the remaining plurality of alumina portions each has a width of less than 10 nm; removing exposed portions of the blanket layer of graphene using said plurality of alumina portions as an etch mask to provide a graphene lattice comprising an ordered array of graphene nanoribbons, each graphene nanoribbon within said ordered array having a width of less than 10 nm; removing said etch mask; and transferring said ordered array of graphene nanoribbons to a substrate.