Patent ID: 8078898
Filing Date: 2011-12-13
Classification: G01R,G06F,H04L

Abstract:
1. A target system comprising: A. a communications link that includes a test data input signal, a test data output signal, a test clock signal, and a test mode select signal; B. scan test logic including a test access port controller having a test clock input and a test mode select input, the test access port controller including a state machine having the states of TEST LOGIC RESET, RUN TEST IDLE, SELECT-DR, CAPTURE-DR, SHIFT-DR, EXIT1-DR, PAUSE-DR, EXIT2-DR, and UPDATE-DR; and C. adapter circuitry including a test access port controller having a test clock input and a test mode select input, the adapter circuitry being connected to the communications link signals and selectively coupling the scan test logic to the communications link signals, the test access port controller including a state machine having the states of TEST LOGIC RESET, RUN TEST IDLE, SELECT-DR, CAPTURE-DR, SHIFT-DR, EXIT1-DR, PAUSE-DR, EXIT2-DR, and UPDATE-DR, the adapter circuitry at power up connecting the test clock signal to the test clock inputs of the controllers of the adapter circuitry and the scan test logic and connecting the test mode select signal to the test mode select inputs of the controllers of the adapter circuitry and the scan test logic, causing the test access port controllers to cycle to the IDLE state, and then decoupling the controller of the scan test logic from the test clock signal while recognizing a serial, synchronization point sequence on the test mode select input.