Patent ID: 6060349
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A planarization method for an embedded dynamic random access memory (DRAM), which has a logic region comprising a first metal-oxide semiconductor (MOS) transistor, and a memory region comprising a second MOS transistor and a capacitor, the planarization method comprising:forming a first inter-layer dielectric (ILD) layer over the substrate, wherein a difference in height exists between the logic region and the memory region, and the logic region has a lower height;forming a first metal layer over the logic region, wherein the first metal layer is electrically coupled to one of two interchangeable source/drain regions of the first MOS transistor through a first contact opening, patterned on the first ILD layer;forming a second ILD layer over the logic region to compensate for the difference in height;performing planarization on the substrate, wherein after planarization, the logic region and the memory region have no difference in height; andforming a second metal layer over the substrate, wherein the second metal layer above the memory region is electrically coupled to one of two interchangeable source/drain regions of the second MOS transistor through a second contact opening patterned on the first ILD layer, and the second metal layer above the logic region is electrically coupled to the first metal layer through a via opening patterned on the second ILD layer.