Patent ID: 6221717
Filing Date: 2001-04-24
Classification: H01L

Abstract:
Process for manufacturing an integrated structure comprising at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, comprising at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second layer of polysilicon on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage a mask with an opening on a channel region of said selection transistor is used for etching and removing said intermediate dielectric layer also in said channel region that is destined to form a channel of a second type of conductivity for said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.