Patent ID: 7514991
Filing Date: 2009-04-07
Classification: G01R,G11C,H03L,H04L

Abstract:
1. A signal sampling circuit comprising: a primary differential input stage to receive a first input signal and a second input signal, the primary differential input stage being enabled responsive to a first control signal to couple a first current through a first output node and couple a second current through a second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node and to limit the combination of the first current and the second current according to a bias signal; a secondary differential input stage to receive a third input signal and a fourth input signal, the secondary differential input stage being enabled by asserting a second control signal to couple a third current through the first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node and to limit the combination of the third current and the fourth current according to the bias signal; first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage.