Patent ID: 6324226
Filing Date: 2001-11-27
Classification: H03M

Abstract:
A Viterbi decoder, comprising:a branch metric operation section for calculating branch metrics based on input codes;an add-compare-select (ACS) operation section for calculating path metrics of respective states by time-sharing processing based on the branch metrics calculated by the branch metric operation section, selecting a maximum likelihood path in combination with a path metric at a preceding time point, and generating a path selection signal as information of the maximum likelihood path thus selected (a surviving path);a path metric permutation section for temporarily delaying the path metrics sequentially calculated by and output from the ACS operation section and permutating the path metrics to have different time series from those of the path metrics output from the ACS operation section;a path metric/path selection signal common memory for storing path metrics and path selection signals;a trace-back operation section for searching past state transition using a past path selection signal read out from the path metric/path selection signal common memory and outputting decoded data, the trace-back operation section including:a Viterbi state memory for storing a Viterbi state following the surviving path based on the path selection signal obtained from the path metric/path selection signal common memory;a Viterbi state prediction section for predicting a part of a Viterbi state to be updated next based on contents of the Viterbi state memory; anda path selection signal memory address calculation section for calculating an address of the path selection signal memory storing the path selection signal based on the part of the Viterbi state predicted by the Viterbi state prediction section; andan address generation/memory control section for receiving path metrics from the path metric permutation section and the path selection signal from the ACS operation section, generating and writing a specific address with respect to the path metric/path selection signal common memory, reading out the path metrics and the path selection signal that are stored in the path metric/path selection signal common memory, and supplying the path metrics to the ACS operation section and the path selection signal to the trace-back operation section,wherein the ACS operation section, the path metric operation section, and the trace-back operation section access the path metric/path selection signal common memory in a time sharing manner under control by the address generation/memory control section.