Patent ID: 9218978
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A method, comprising: forming a dielectric stack on a wafer, wherein the dielectric stack includes tunneling dielectric on the wafer, a charge-trapping layer, and a cap layer overlaying the charge-trapping layer; patterning the dielectric stack to form a non-volatile (NV) gate stack of a non-volatile memory (NVM) transistor in a first region of the wafer while concurrently removing the dielectric stack in a second region of the wafer; and performing a two-step gate oxidation process to concurrently oxidize at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the two-step gate oxidation process.