Patent ID: 6469374
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A semiconductor device comprising a superposed structure formed by superposing a plurality of superposed substrates each including a wiring printed substrate loaded with a semiconductor element and an inner conductive-via provided insulating substrate, whereinsaid wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes formed in said wiring printed substrate in such a manner that said contact electrodes are buried in said via holes, and has a plurality of wiring conductors electrically connected to said contact electrodes, said semiconductor element loaded on said wiring printed substrate is electrically connected to said wiring conductors provided on said wiring printed substrate, said conductive-via provided insulating substrate has a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on said wiring printed substrate and a plurality of contact electrodes formed in a plurality of via holes formed in said conductive-via provided insulating substrate in such a manner that said contact holes are buried in the via holes, and said conductive-via provided insulating substrate and said wiring printed substrate are superposed in such a manner that said contact electrodes in said conductive-via provided insulating substrate and said contact electrodes in said wiring printed substrate are electrically connected to each other and in such a manner that said semiconductor element loaded on said wiring printed substrate is accommodated in said chip cavity in said conductive-via provided insulating substrate to constitute a superposed substrate.