Patent ID: 6782007
Filing Date: 2004-08-24
Classification: H04J,H04L

Abstract:
For use in a communications device, a data transfer system comprising:a frame data interface circuit capable of receiving incoming data frames from a plurality of frame data sources; a transmit buffer coupled to said frame data interface circuit and capable of receiving said incoming data frames therefrom, wherein said transmit buffer is capable of dividing a first selected incoming data frame into a plurality of N-bit data fields and attaching to each of said plurality of N-bit data fields an M-bit control field comprising a synchronization indicia associated with said first selected incoming data frame, said each N-bit data field and said attached M-bit control field comprising a data record; and a receive buffer coupled to said transmit buffer and capable of receiving said data records therefrom, wherein said receive buffer is capable of re-assembling said first selected incoming data frame from selected ones of said received data records and generating from said synchronization indicia therein a timing signal associated with said first selected incoming data frame.