Patent ID: 7794897
Filing Date: 2010-09-14
Classification: G03F,G06F

Abstract:
1. A pattern correcting method for correcting design patterns to form a desired pattern on a wafer, the method comprising: defining an allowable dimensional change quantity for each of a plurality of design patterns included in a design layout; selecting one of a plurality of circuit models previously prepared for the design patterns having different allowable dimensional change quantities, based on the allowable dimensional change quantity defined for each design pattern, the allowable dimensional change quantity of the selected one circuit model corresponding to the allowable dimensional change quantity of said each design pattern; defining a pattern correction condition for said each design pattern based on the allowable dimensional change quantity defined for said each design pattern; carrying out a simulation of an operation, using the selected one circuit model; and determining, based on the simulation, whether or not a predetermined operation margin is attained for the selected one circuit model, and performing correction for said each design pattern based on the pattern correction condition until it is determined that the predetermined operation margin is attained.