Patent ID: 8222683
Filing Date: 2012-07-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of memory cells that respectively includes a capacitor structure formed above a semiconductor substrate and constituted by sandwiching a dielectric film with a lower electrode and an upper electrode, and a transistor for selecting the capacitor structure, wherein the capacitor structure of the respective memory cells is respectively formed in either one layer of at least two layers of interlayer insulating films having different heights from a surface of the semiconductor substrate; wherein, between two layers of the interlayer insulating films having been laminated adjacently, a first protective film is formed between the lower electrode and a first plug, a second protective film is formed between the upper electrode and the first plug, and a third protective film is formed between a second plug and a third plug located lower in position than the second plug in a height, wherein the first protective film, the second protective film, and the third protective film are formed at the same position in height from the surface of the semiconductor substrate.