Patent ID: 8817901
Filing Date: 2014-08-26
Classification: H04J,H04L

Abstract:
1. A channel estimate interpolation circuit comprising: an arithmetic unit that selectively performs an FFT (Fast Fourier Transform) operation or an inverse-FFT operation; a first buffer that stores first channel estimate values estimated based on reference signals discretely arranged in subcarriers within a predetermined bandwidth; a second buffer that stores a result of the operation obtained by the arithmetic unit; and a converter that is connected to the arithmetic unit, and the first and second buffers, wherein the converter is configured to execute: (A) a process to estimate second channel estimate values corresponding to subcarriers outside the bandwidth, by performing a linear interpolation between channel estimate values corresponding to reference signals arranged at both ends of the bandwidth among the first channel estimate values stored in the first buffer; (B) a process to cause the arithmetic unit to perform the inverse-FFT operation for channel estimate values obtained by merging the first and second channel estimate values, and to store a first delay profile obtained by the inverse-FFT operation in the second buffer; (C) a process to replace data components with zero, the data components delayed for a predetermined threshold time or more in the first delay profile stored in the second buffer; (D) a process to cause the arithmetic unit to perform the FFT operation for a delay profile obtained by the replacement, to store third channel estimate values obtained by the FFT operation in the second buffer; and (E) a process to extract channel estimate values corresponding to the subcarriers outside the bandwidth from the third channel estimate values stored in the second buffer, wherein the converter is configured to repeatedly execute the processes (B) to (E) while treating the extracted channel estimate values as the second channel estimate values.