Patent ID: 9047979
Filing Date: 2015-06-02
Classification: G06F,G11C,H01L

Abstract:
1. A method for accessing a plurality of DRAM devices each of the plurality of DRAM devices having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals, the method comprising: determining an operating mode for the plurality of DRAM devices; providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated: activating a first bank in a second one of the plurality of DRAM devices if the operating mode is determined to be a physical rank address mode; not activating a first bank in any of the plurality of DRAM devices other than the first one of the plurality of DRAM devices if the operating mode is determined to be a logical rank address mode; and subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices.