Patent ID: 9035383
Filing Date: 2015-05-19
Classification: B82Y,H01L,Y10S

Abstract:
1. An electronic device, comprising: at least one first set of nanowires and first set of pads etched in an SOI layer of an SOI wafer and at least one second set of nanowires and second set of pads etched in the SOI layer, wherein the first set of pads are attached at opposite ends of the at least one first set of nanowires in a ladder-like configuration, wherein the second set of pads are attached at opposite ends of the at least one second set of nanowires in another ladder-like configuration, and wherein the at least one first set of nanowires and the first set of pads correspond to a capacitor device and the at least one second set of nanowires and the second set of pads correspond to a FET device, the capacitor device and the FET device both being present on the SOI wafer; a first gate stack that surrounds at least a portion of each of the at least one first set of nanowires that serves as a channel region of the capacitor device, wherein portions of the at least one first set of nanowires extending out from the first gate stack and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are undoped; a second gate stack that surrounds at least a portion of each of the at least one second set of nanowires that serves as a channel region of the FET device, wherein portions of the at least one second set of nanowires extending out from the second gate stack and the second set of pads serve as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped; first spacers on opposite sides of the first gate stack and second spacers on opposite sides of the second gate stack, wherein the first spacers have a width wa and the second spacers have a width wb, and wherein wa<wb; a first silicide formed on the source and drain regions of the capacitor device; and a second silicide formed on the source and drain regions of the FET device, wherein an amount of the first silicide formed on the source and drain regions of the capacitor device is greater than an amount of the second silicide formed on the source and drain regions of the FET device such that first silicide formed on the source and drain regions of the capacitor device extends at least to an edge of the first gate stack while the second silicide formed on the source and drain regions of the FET device remains within the source and drain regions of the FET device.