Patent ID: 7134061
Filing Date: 2006-11-07
Classification: G01R

Abstract:
1. A scan test circuit design imbedded within an integrated circuit chip having a test clock signal, comprising: at least one scan-in terminal coupled to receive a test stimulus input data; at least one scan-out terminal to output testing resultant data; at least one scan chain group each having a clock domain, the at least one scan chain group coupled between one of the at least one scan-in terminal and one of the at least one scan-out terminal, wherein the test clock signal enables the testing of each of the at least one scan chain group, each scan chain group has a corresponding test mode signal to shift the test stimulus input data at a shift clock rate derived from the corresponding clock domain, wherein each at least one scan chain group comprises, a demultiplexer unit, having an input, an enable input, a first output and a second output, the input coupled to receive the test stimulus input data, the enable input coupled to receive the test clock signal, the first output coupled to a functional input for the portion of the integrated circuit chip being tested, a first multiplexer unit, having a first input, a second input, an enable input, and an output, the first input coupled to the second output of the demultiplexer unit, the enable input coupled to receive a simultaneous test mode signal, a scan chain, having an input, a control input, and an output, the input coupled to the output of the first multiplexer unit, the scan chain having a corresponding scan chain clock domain at a predetermined frequency, and a second multiplexer unit, having a first input, a second input, an enable input, and an output, the first input coupled to the output of the scan chain, the second input coupled to receive functional output data from the portion of the integrated circuit chip being tested to supply testing resultant data at the output; a controlling demultiplexer coupled to the second output of one demultiplexer unit and coupled to receive the simultaneous test mode signal and a plurality of test mode signals for each scan chain group to generate control signals to be coupled to the second input of each first multiplexer unit to control the concurrent shifting of the test stimulus input data into each scan chain at the predetermined frequency; a clock control mechanism coupled to receive the test clock signal, a plurality of test mode select pin inputs, a scan enable signal, functional clock and function enable signals corresponding to each of the at least one scan chain groups to generate the control input signal for each scan chain, the plurality of test mode signals for each scan chain group and the simultaneous test mode signal, wherein the clock control mechanism coupled to the control input of each scan chain of the at least one scan chain group to enable one scan chain to shift test stimulus input data when the scan enable signal is enabled and the test clock signal is enabled, the clock control mechanism coupled to each scan chain to enable simultaneous capture of each of the at least one scan chain group when the scan enable, the test clock, and the simultaneous test mode signal are enabled; and a controlling multiplexer coupled to the output of each scan chain and coupled to receive each test mode signal to generate a control signal for the second multiplexer of the least significant of the at least one scan chain group.