Patent ID: 9203409
Filing Date: 2015-12-01
Classification: H03K

Abstract:
1. A wafer-level stacked chip assembly comprising two or more vertically stacked chip layers, wherein each chip layer includes a switching mechanism for selectively bypassing chip coding sequence, a plurality of vertical download terminals, a plurality of vertical upload terminals, and an IC circuitry area, moreover the switching mechanism is built inside each corresponding chip layer and comprises: a plurality of vertically interconnected input terminals and output terminals, whereas each transmitted path between the input terminals and the correspondingly output terminals is divided into a coding path and a non-coding bypass; a sequence generator connected to the coding paths to define the corresponding identification code of an allocated one of the chip layers; a decoder connected to a plurality of I/O gates disposed between the sequence generator and the IC circuitry area, wherein the decoder has a plurality of first input nodes to receive a corresponding identification code generated by the corresponding sequence generator; a plurality of multiplexers connected between the output terminals and the input terminals, wherein each multiplexer has a second input node connected to the sequence generator through the coding path and a third input node connected to the non-coding bypass respectively, an output node of each multiplexer is connected to the corresponding one of the output terminals; and a chip shutter disposed inside the corresponding chip layer for closing the I/O gates of the IC circuitry area with a closing priority comparing to the decoder, wherein the chip shutter is also connected to a select node of each multiplexer to switch the selection of the multiplexers between the coding paths and the non-coding bypasses.