Patent ID: 6353872
Filing Date: 2002-03-05
Classification: G06F,G11C

Abstract:
A memory interface circuit for controlling and refreshing a semiconductor memory device, comprising:a memory bus arbitrating circuit which receives a plurality of request signals and which selects a request signal of highest priority among two or more simultaneously received request signals, wherein the plurality of request signals include a first refresh request signal, a second refresh request signal having a priority which is lower than that of the first refresh request signal, and at least one third request signal each having a priority which is lower than that of the first refresh request signal and higher than that of the second refresh request signal; a memory controlling circuit which controls the semiconductor memory device in accordance with the request signal of highest priority selected by said memory bus arbitrating circuit; a logical counter which generates a count value corresponding to an elapsed time, and which is reset when the semiconductor memory device is refreshed; a first monitoring circuit which outputs the first refresh request signal to said memory bus arbitrating circuit when the count value of said logical counter exceeds a first comparison value; and a second monitoring circuit which outputs the second refresh request signal to said memory bus arbitrating circuit when the count value of said logical counter exceeds a second comparison value that is smaller than the first comparison value.