Patent ID: 7350173
Filing Date: 2008-03-25
Classification: G06F

Abstract:
1. A method to layout an integrated circuit, the method comprising: analyzing timing to identify a set of cells on a path; splitting the path into segments at a plurality of nets that includes determining the plurality of nets of the path; generating a plurality of placement designs for the path, wherein each of the placement designs is generated from placing and routing cells of a first segment of the path near a first location that includes placing a cell of the first segment at a permissible location out of a plurality of permissible locations; routing the cell from the permissible location; and determining a timing parameter associated with the cell already placed and routed, and subsequently, after the routing of the cells of the first segment, placing and routing cells of a second segment of the path near a second location, the first segment and the second segment being connected by one of the plurality of nets; routing at least one of the nets of the path for each of the plurality of placement designs; and selecting a first design from the plurality of placement designs, wherein said selecting is based on actual routes of the at least one of the nets routed for each of the plurality of placement designs.