Patent ID: 6654858
Filing Date: 2003-11-25
Classification: G06F

Abstract:
A multi-processor computer system, comprising:a first group of processors coupled together; a second group of processors coupled together and coupled to said first group of processors; one or more input/output devices coupled to at least one of said processors in said first or second group; wherein each processor in said first and second groups has a cache subsystem and an associated main memory; each of said processors in said first and second groups maintaining a multi-entry, read/writeable directory in its associated main memory wherein each entry specifies a coherence state of a data block in the main memory; wherein a memory write reference between processors in said first group does not initiate a directory write of the block associated with the memory write reference, but a memory write reference between a processor in said second group and a processor in said first group causes a directory read and a cache hit/miss determination to occur and initiates a directory write of the block associated with the memory write reference.