Patent ID: 7405443
Filing Date: 2008-07-29
Classification: H01L,H02M,Y02B

Abstract:
1. A transistor, comprising: a source region including a first impurity region of a first conductivity type, a second impurity region of a second conductivity type and a third impurity region of the first conductivity type, the first impurity region being implanted into a surface of a substrate, the second impurity region being implanted within the first impurity region, the third impurity region being implanted into the first impurity region adjacent to the second impurity region, the third impurity region having a higher impurity concentration than the first impurity region, the second and third impurity regions providing ohmic contacts for the transistor; a dual gate including a first gate and a second gate, the first gate including a first gate oxide layer formed over the substrate, the second gate including a second gate oxide layer formed over the substrate, the first gate being laterally separated from the second gate by a non-zero distance; and a drain region including a fourth impurity region being of the second conductivity type, the fourth impurity region providing an ohmic contact for the transistor, the fourth impurity region having an offset spacing from the first gate and being self aligned with respect to the second gate.