Patent ID: 6603828
Filing Date: 2003-08-05
Classification: G11C

Abstract:
A signal converting device in a chipset, converting an input signal, which refers to a first clock, into an output signal, which refers to a second clock, m cycle(s) of the first clock being equal to n cycle(s) of the second clock, wherein m and n are both positive integers satisfying 2n>m>n, the signal converting device comprising:a first flip-flop, receiving the first clock and a first ready head signal of the input signal, and outputting a delayed ready head signal which is the result of the first ready head signal being delayed for one first clock cycle; a second flip-flop, receiving the first clock and a first ready tail signal of the input signal, and outputting a delayed ready tail signal which is the result of the first ready tail signal being delayed for one first clock cycle; a logic gate, receiving the delayed ready tail signal and a phase signal, and outputting an extension signal, wherein the extension signal is enabled when both the delayed ready tail signal and the phase signal are enabled; a first multiplexer, receiving the first ready tail signal, the delayed ready tail signal and the extension signal, and outputting an extension ready tail signal under the control of the extension signal; a second multiplexer, receiving the first ready head signal, the delayed ready head signal and the extension signal, and outputting an extension ready head signal under the control of the extension signal; and a signal converter, receiving the extension ready tail signal, the extension ready head signal, the first clock and the second clock, and outputting a second ready head signal and a second ready tail signal of the output signal; wherein the first clock and the second clock are in pseudo synchronization; one cycle of the phase signal is m times of one first clock cycle; and one period for the enabled phase signal is equal to one first clock cycle.