Patent ID: 6295587
Filing Date: 2001-09-25
Classification: G06F

Abstract:
For use in a computer system having a first plurality of processors and a second plurality of mass storage devices, an interprocessor bus interconnecting the processors, and a plurality of adapters connected from the interprocessor bus for providing communication between the processors and the mass storage devices, an operating system with a device driver stack, and a binding utility for communicating with the processors and the adapters to generate pairings between the processors and the adapters wherein each processor/adapter pairing is an association of a processor with an adapter, an improved mechanism for providing access between the processors and the mass storage devices, comprising:a switch connected between the adapters and the mass storage devices for connecting each adapter to each mass storage device,a binding mapper communicating with the binding utility at each binding of the adapters and the processors for,at each binding of a processor/adapter pair,enumerates the connected mass storage devices with which the processor of the processor/adapter pair is to communicate and determining, for each such mass storage device, a mass storage identifier by which the processor identifies the mass storage device, andan address mapper incorporated into the operating system device driver stack for constructing and storing an address map, whereinthe address map contains a processor set for each mass storage device whereineach processor set includes an address map entry for each processor in the system, whereineach processor set is indexed by a processor number and contains the mass storage device identifier corresponding to an optimal path of access to the corresponding mass storage device, andthe address mapper is responsive to a request for access to a mass storage device by a processor, wherein the request includes a processor name, by providing the corresponding address map entry from the processor set corresponding to the requesting processor, whereinthe requesting processor completes the access to the mass storage device by directing the request through the adapter paired with the processor as determined by the returned address map entry.