Patent ID: 6027965
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit comprising MOS transistors and resistors on a substrate of semiconductor material having a first conductivity type, the method comprising the steps of:(a) forming a dielectric layer on a principal surface of the substrate for gate dielectrics of the MOS transistors;(b) forming a polycrystalline silicon layer on the dielectric layer;(c) selectively removing portions of the polycrystalline layer to define an implantation mask comprising portions of polycrystalline silicon each intended to form respective gate electrodes of the MOS transistors and to form portions which define resistor openings each intended for the formation of a respective resistor;(d) subjecting the principal surface of the substrate to a first implantation through the implantation mask with ions of a dopant of a predetermined type to form, in the substrate on two opposite sides of each gate electrode, a pair of regions with a second type of conductivity separated from one another by a channel, and to form, through each of the resistor openings, a resistive region with the second type of conductivity;(e) forming a layer of insulating material which covers a structure resulting from steps (a) through (d);(f) subjecting the layer of insulating material to anisotropic etching to remove the insulating material until areas of the substrate not covered by the implantation mask are uncovered, and leaving a residue of insulating material along edges of the polycrystalline silicon so as to produce a modified implantation mask;(g) subjecting the principal surface of the substrate after step (f) to a second implantation through the modified implantation mask with ions of a dopant of the predetermined type with a dose and an energy such as to produce a predetermined surface resistivity for the resistive regions; and(h) selectively subjects the principal surface of the substrate to further implantation.