Patent ID: 7566620
Filing Date: 2009-07-28
Classification: H01L

Abstract:
1. A method of forming a vertical memory cell, the method comprising: forming a vertical memory cell comprising: depositing a dielectric to cover a horizontal upper surface of the polysilicon surround gate; forming a trench extending along the surround gate so as to expose a vertical surface of the surround gate; depositing a thin metal on the exposed vertical surface of at least the polysilicon surround gate while the horizontal upper surface of the polysilicon surround gate remains covered by the dielectric; exposing the thin metal to heat that is sufficiently high to react at least a portion of the thin metal with at least a portion of the polysilicon gate in order to form a silicided gate extending along a vertical length of the formerly exposed vertical surface of the polysilicon surround gate; forming a spacer arranged to cover at least the silicided gate contact; and forming a second separate generally vertical conductive path extending from a drain contact upwards to above the surround gate, wherein the drain contact is arranged adjacent the lower end of the vertically extending channel region.