Patent ID: 6715105
Filing Date: 2004-03-30
Classification: G01R,G11C

Abstract:
A test apparatus for testing a digital circuit comprising:a scan data in (SDI) port for serially receiving input scan data; a first linear feedback shift register which is operable to receive and shift said input scan data to produce a serial stream of pseudorandom scan data in response to only a test clock signal; a scan-in selector which couples one of said input scan data or said serial stream of pseudorandom scan data to serially load a plurality of scanpaths, each of which produces a respective scan-out signal; a multiple input signature register coupled to receive said respective scan-out signals and to generate a respective signature corresponding to a function of said respective scan-out signals; a scan data out (SDO) port; and an output selector which couples one of said scan-out signals or said signature to said SDO port.