Patent ID: 6496968
Filing Date: 2002-12-17
Classification: G06F

Abstract:
A computer-implemented method for hierarchically wiring a semiconductor integrated circuit in a hierarchical implementation design of the semiconductor integrated circuit, comprising the steps of:extracting, when wiring an intra-block net to establish connections in a block in a lower layer, block edge terminals from an input logic file of an upper layer, the terminals being terminals of a net to be connected to a position external to the block; obtaining a rectangle circumscribing the block in accordance with allocating positions beforehand determined in the block and defining the rectangle as a boundary of the block; disposing, on four edges of the rectangular boundary of the block, block edge virtual terminals connected to block edge terminals respectively associated therewith; automatically conducting wirings between the block edge terminals to the associated virtual terminals prior to an intra-block net; automatically wiring thereafter all remaining intra-block nets; deleting, after the intra-block wirings are completely finished, all wiring patterns of nets connected to the virtual terminals, to thereby provide wiring pattern spaces; and performing an inter-block wiring using said wiring pattern spaces, when wirings of inter-block nets for connection between blocks in the upper layer are carried out.