Patent ID: 8098524
Filing Date: 2012-01-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of blocks including a plurality of memory cells which are arranged in a matrix form and connected in series, the plurality of memory cells being connected with word lines and bit lines; a plurality of selection transistors which select the word lines; and a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, and read and erase operations of data with respect to the memory cells, wherein the plurality of selection transistors are formed on a well, and in read operation a first negative voltage is supplied to the well, a first group of the plurality of selection transistors connected to a non-selected of the plurality of blocks block is turned off, a second group of the plurality of selection transistors connected to a selected of the plurality of blocks block is turned on, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line.