Patent ID: 8937009
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A method comprising: forming, above a semiconductor layer, a stack of interlayer dielectrics and metal structures extending through said stack of interlayer dielectrics; forming a passivation layer above a top surface of said stack of interlayer dielectrics; forming first openings in a passivation layer, said first openings exposing tops of said metal structures, respectively; forming a mask layer above said passivation layer; forming second openings in said mask layer aligned above said first openings so as to form two-tier openings extending vertically through said mask layer and said passivation layer, said two-tier openings being aligned above said metal structures; depositing metal layers into said two-tier openings so as to essentially simultaneously form: removing said mask layer; forming an additional mask layer on said passivation layer over said under-bump pad and said additional metal feature; forming a third opening extending vertically through said additional mask layer to expose said under-bump pad; depositing solder material in said third opening on said under-bump pad immediately adjacent one of said two first metal cap layers, said additional mask layer preventing deposition of said solder material on said additional metal feature; and removing said additional mask layer.