Patent ID: 7359271
Filing Date: 2008-04-15
Classification: G11C

Abstract:
1. A method for reducing gate induced leakage current associated with circuits in a semiconductor memory integrated circuit device, comprising: a. during a standby mode of the device, reducing a voltage supplied to a transistor in a plurality of wordline driver circuits from a normal operating voltage level used for accessing memory cells to a lower voltage level so as to reduce gate induced leakage current associated with said plurality of wordline driver circuits while at said lower voltage level during said standby mode; b. during each of a plurality of time intervals while in said standby mode, increasing said voltage from the lower voltage level to the normal operating voltage level supplied to a subset of said plurality of wordline driver circuits and then reducing said voltage to the lower voltage level for said subset of wordline driver circuits; and c. determining in advance of a refresh function for memory cells associated with a particular wordline whether said particular wordline is replaced by a redundant wordline corresponding to a different subset of wordline driver circuits, and if so, increasing the voltage of said wordline driver circuits in said different subset from the lower voltage level to the normal operating voltage level to prepare for the refresh function of memory cells associated with said redundant wordline.