Patent ID: 7983073
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A static random access memory device, comprising: a first memory cell coupled to a read word line, a write word line, a first read bit line, a first write bit line and a first complementary write bit line; a second memory cell coupled to the read word line, the write word line, a second read bit line, a second write bit line and a second complementary write bit line; a word line driving unit coupled to the read word line and the write word line; and first and second multiplexing units coupled to the first and second the memory cells, wherein the word line driving unit activates the read word line for a first time interval when the second memory cell is selected to be written by an input signal from a data driver and the word line driving unit then activates the write word line in the first time interval to write the input signal from the data driver to the second memory cell.