Patent ID: 6826073
Filing Date: 2004-11-30
Classification: G11C

Abstract:
A combination of static random access memory (SRAM) and mask read only memory (MROM) cells, including a SRAM unit and a ROM unit, wherein the static random access unit as a random access memory unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the first transistor, the second transistor, the third transistor, and the fourth transistor forming an inverter; the first transistor being complementary to the third transistor, the second transistor being complementary to the fourth transistor, which is characterized in that:the ROM unit being a MROM is used to permanently store data and has a seventh transistor, with the feature that the ROM unit is embedded inside the SRAM unit, the ROM unit is in a cross region formed by an intersection of a polysilicon area and a source Vss of the fifth transistor and the sixth transistor with a ROM bit line contact next to the ROM unit.