Patent ID: 6114232
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method for forming a circuit component in electrical connection with a lower node location, comprising:forming upper and lower photosensitive material masking blocks over the node location, and wherein the step of forming the upper and lower photosensitive masking blocks comprises separately providing and patterning first and second layers of photosensitive material, and wherein, the lower photosensitive masking block comprises a positive image of a contact opening to the node location, and the upper photosensitive masking block comprising a positive image of a circuit component;forming dielectric material around the upper and lower photosensitive masking blocks, and wherein the step of forming the dielectric material comprises separately providing first and second layers of dielectric material, and wherein the lower masking block remains in covering relation over the node location after providing the first and second dielectric layers;removing the upper and lower photosensitive masking blocks in a single operation from the dielectric material to leave a contact opening void and an overlying circuit component void; andfilling the contact opening void and overlying circuit component void with electrically conductive material to form a circuit component in electrical connection with the node location.