Patent ID: 9006804
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a metal gate electrode, disposed on a substrate; a first interlayer dielectric, surrounding a periphery of the metal gate electrode; a patterned mask layer, disposed on the metal gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric; a spacer disposed on the sidewalls of the patterned mask layer, wherein a bottom surface of the spacer is leveled with the bottom surface of the patterned mask layer; a second interlayer dielectric, covering a top surface and the sidewalls of the patterned mask layer; and a self-aligned contact structure disposed in the first interlayer dielectric and the second interlayer dielectric, and electrically connecting the substrate.