Patent ID: 7573295
Filing Date: 2009-08-11
Classification: H03K

Abstract:
1. An integrated circuit, comprising: a core located in the integrated circuit as an application specific circuit block; the core having a transaction interface; the transaction interface having a first bit width; programmable logic capable of being programmed to instantiate user logic, the user logic having a user interface of a second bit width substantially less than the first bit width; a wrapper circuit coupling the user interface and the transaction interface for coupling the core to the user logic; the wrapper circuit configured to couple first information of the first bit width from the transaction interface to the user interface; and the wrapper circuit configured to couple second information of the second bit width from the user interface to the transaction interface; wherein the wrapper circuit is configured to provide a phase signal to the user logic as part of the user interface; and wherein the phase signal is provided as an output of a first control flip-flop, the first control flip-flop being clocked responsive to a first clock signal.