Patent ID: 6460065
Filing Date: 2002-10-01
Classification: G06F

Abstract:
A circuit for generating partial product bits in a squaring circuit for a binary number, receiving a first bit of weight 2(kâˆ’1) and a second bit of weight 2k of said binary number, comprising:a first partial product bit generator configured to generate a first partial product bit of weight 22k such that the first partial product bit has a 1 value only if the first bit of weight2(kâˆ’1) has a 0 value while the second bit of weight 2k has the 1 value, the first partial product bit generator comprises: a first AND gate configured to receive and logically AND the first bit of weight 2(kâˆ’1) and the second bit of weight 2k to generate an intermediate bit; and an XOR gate configured to receive and logically XOR the intermediate bit and the second bit of weight 2k to generate the first partial product bit of weight 22k; and a second partial product bit generator configured to receive the intermediate and second bits and configured to provide a second partial product bit of weight 22k+1 such that the second partial product bit has the 1 value only if the first bit of weight 2(kâˆ’1) and the second bit of weight 2k both have the 1 value.