Patent ID: 8051123
Filing Date: 2011-11-01
Classification: G06F

Abstract:
1. A multipurpose functional unit for a processor, the functional unit comprising: an input section configured to receive an opcode designating one of a plurality of supported operations to be performed and one or more operands on which the designated operation is to be performed, the operations including a linear filtering (FILT) operation and a double-precision multiplication (DMUL) operation, the input section being further configured to generate a plurality of control and data signals in response to the received opcode and operands; a multiplication pipeline including a plurality of sub-product blocks, each including a plurality of multiplier circuits, the multiplication pipeline being configured to receive a first subset of the control and data signals from the input section, the multiplication pipeline being configured to select a plurality of factors based on the received control and data signals and to operate the plurality of multiplier circuits to compute one or more products from the plurality of factors, wherein in the event the opcode designates the FILT operation, a first multiplier circuit in a first sub-product block receives a first filter coefficient A0 and a first coordinate w0 to compute a first product A0*w0, a second multiplier circuit in the first sub-product block receives a second filter coefficient A1 and a second coordinate w1 to compute a second product A1*w1, an adder in the first sub-product block computes a first sum A0*w0+A1*w1, a first multiplier circuit in a second sub-product block receives a third filter coefficient B0 and a third coordinate w2 to compute a third product B0*w2, a second multiplier circuit in the second sub-product block receives a fourth filter coefficient B1 and a fourth coordinate w3 to compute a fourth product B1*w3, and an adder in the second sub-product block computes a second sum B0*w2+B1*w3, wherein in the event that the opcode designates the DMUL operation, for each of a plurality of iterations within the functional unit: a first portion and a second portion of a mantissa of a first input operand are selected as inputs M2 and M1, respectively; a portion of a mantissa of a second input operand is selected as both of inputs μ2 and μ1, wherein a different portion of the mantissa of the second input operand is selected for each of the plurality of iterations; and a pair of multiplier circuits in the functional unit compute products of the form M2*μ2 and M1*μ1 from the selected inputs M2, μ2, M1, and μ1, and an addition pipeline configured to selectively receive one or more products from the multiplication pipeline and to perform an addition operation using the one or more products to produce an operation result, wherein in the event the opcode designates the FILT operation, the addition pipeline adds the first sum, the second sum, and an operand C, wherein in the event the opcode designates the DMUL operation, the addition pipeline adds the products M2*μ2 and M1*μ1 to a running sum, wherein the FILT operation is executed in a single pass through the multiplication pipeline and the addition pipeline and the DMUL operation is executed using multiple iterations through at least a portion of the multiplication pipeline and at least a portion of the addition pipeline, wherein each of the multiplier circuits has a width less than half of a double-precision mantissa size.