Patent ID: 9196318
Filing Date: 2015-11-24
Classification: G11C

Abstract:
1. A voltage reference circuit, comprising: a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground, wherein the first depletion-mode PMOS transistor has shorted gate and source; a second depletion-mode PMOS transistor having a source coupled to the gate of the first enhancement PMOS transistor at a first node, the second depletion-mode PMOS transistor also having a gate coupled to a drain of the first enhancement-mode PMOS transistor at a second node, forming a feedback circuit; a first resistive device coupled between the voltage supply and the first node; a second resistive device, which has one end coupled to the drain of the second depletion-mode PMOS transistor at a third node and has the other end coupled to the ground; and a bias circuit coupled to a gate of the first enhancement-mode NMOS transistor; wherein the first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region, and a first reference voltage between the voltage supply and the first node is independent of the magnitude of the voltage supply.