Patent ID: 8592237
Filing Date: 2013-11-26
Classification: G02F,H01L

Abstract:
1. A method for manufacturing a thin film transistor substrate having a low resistance bus line structure comprising: forming bus lines by etching a surface of a substrate to form bus line patterns and filling the bus line patterns with a bus line metal; forming a semiconductor channel layer at one portion of a pixel area defined by the bus lines; and forming source-drain electrodes on the semiconductor channel layer, a pixel electrode extending from the drain electrode within the pixel area, and a common electrode parallel with the pixel electrode, wherein forming the bus lines includes forming a data line having a plurality of segments perpendicular to the gate line between the gate line and the common line, the data line is buried into the substrate, wherein forming the bus lines further includes forming the gate line extending in one direction on the substrate, the common line extending parallel with the gate line, and a gate electrode branching from the gate line to the pixel area, wherein forming the semiconductor channel layer includes: forming the semiconductor channel layer overlapping with the gate electrode, by sequentially depositing an insulating material, a semiconductor material and an impurity dopped semiconductor material and patterning the impurity dopped semiconductor material and the semiconductor material; and forming a gate pad contact hole exposing a gate pad, a data pad contact hole exposing a data pad, a common line contact hole exposing some portions of the common line, and data line contact holes exposing both ends of the segments of the data line, by sequentially patterning the insulating material.