Patent ID: 6714043
Filing Date: 2004-03-30
Classification: H03K

Abstract:
A buffer comprising:an output signal node for receiving a signal to be provided to an external circuit; an output pad for connecting to an external circuit; an driver transistors having a source-drain path coupling the output pad to a first power supply terminal, and having a gate forming a first node; and a switching circuit driving the gate of one the driver transistor, each of the switching circuit comprising: a voltage reference for providing a first voltage reference signal to a first voltage reference signal node, and for providing a second voltage reference signal to a second voltage reference signal node; a first reference enabling transistor having a source-drain path coupling the first reference signal node to the first node, and having a gate; a second reference controlled switch transistor having a source-drain path coupling a first power supply terminal to the first node and having a gate connected to the second voltage reference signal node; a second reference enabling transistor having a source-drain path coupling the source-drain path of the first switch transistor to the first power supply terminal, and having a gate; and a logic gate connecting an output signal port to the gate of the first reference enabling transistor and the gate of the second reference enabling transistor.