Patent ID: 8299593
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A stack package including two or more area array type chip scale packages, each chip scale package comprising: a substrate; a plurality of ball land pads formed on a lower surface of the substrate; a plurality of circuit patterns terminating in a plurality of connection pads formed outside the area in which the ball land pads are formed, the circuit patterns and the plurality of connection pads formed on the lower surface of the substrate and electrically connected to the ball land pads; and one or more chips installed on an upper surface of the substrate and electrically connected to the circuit patterns, wherein each chip scale package of an adjacent pair of chip scale packages is attached to the other, wherein the circuit patterns on the lower surface of the substrate of an upper stacked chip scale package are electrically connected to the circuit patterns on the lower surface of the substrate of a lower stacked chip scale package by ends of stack package side-connecting boards having wiring patterns electrically connected to the plurality of connection pads of the circuit patterns on the lower surface of the substrate on the upper stacked chip of the upper stacked chip scale package and to the plurality of the connection pads of the circuit patterns on the lower surface of the substrate of the lower stacked chip of the lower stacked chip scale package.