Patent ID: 6778000
Filing Date: 2004-08-17
Classification: G11C,H03K

Abstract:
A delay circuit comprising:an input terminal that receives an input signal; a first inverter that inverts the input signal; first and second resistors that are electrically coupled in series between an output of the first inverter and an internal node; a capacitor that is electrically coupled between the internal node and a ground voltage; a PMOS transistor that is electrically connected between a power supply voltage and the internal node and is controlled by the input signal; a detector having an input coupled to the internal node that detects whether a voltage of the internal node reaches a threshold voltage; and an output circuit that receives an output of the detector and the input signal and outputs a signal delayed by a time with respect to the input signal, wherein a resistance value of the first resistor varies in proportion to temperature variation and a resistance value of the second resistor varies in inverse proportion to the temperature variation.