Patent ID: 6304957
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A multitask processing unit comprising:a program memory storing programs of first and second tasks;first and second address registers provided in correspondence with each of said programs of said first and second tasks;means for generating a switching signal to switch alternately said first and second address registers in a certain time division ratio;means for executing an instruction, which fetches the instruction of said program of said first task or second task based on one of said first or second address register selected by said switching signal from said generating means and executes the fetched instruction; andmeans for memorizing a cycle condition of said instruction when switched by said generating means,wherein said program of said first task is prohibited from branch instructions, and is composed to be executed fix-looped from its start address to a specific address;wherein each instruction of the programs of said first and second tasks includes a task identification bit to indicate the kind of task, and further comprising a task discrimination means for checking a content of said task identification bit before an execution of the instruction by the executing means;wherein said task discrimination means checks an execution task based on said switching signal from said generating means and the content of said task identification bit; andfurther comprising means for sending prohibition instruction which is sending a no-operation instruction in place of each instruction of said programs to the executing means, when said task discrimination means judges that the content of the task identification bit and the execution task does not conform.