Patent ID: 7932756
Filing Date: 2011-04-26
Classification: H03L

Abstract:
1. A delay lock loop circuit, the circuit comprising: at least a first delay stage and a second delay stage, wherein each of the first delay stage and the second delay stage includes a plurality of selectable delay elements, wherein an input of the first delay stage is selectably driven by one of a first signal and a reference signal, wherein the first delay stage provides a first stage output, wherein an input of the second delay stage is selectably driven by one of a second signal and the first stage output, and wherein the second delay stage provides a second stage output; a mode signal, wherein: a feedback loop, wherein the reference signal and a derivative of the second stage output are provided as inputs to the feedback loop, wherein the feedback loop is operable at least when the mode signal is in the second state to determine a program number corresponding to a number of the plurality of selectable delay elements utilized in the first delay stage and the second delay stage to delay the derivative of the second stage output relative to the reference signal; and a selection register, wherein the selection register is communicably coupled to both the first delay stage and the second delay stage, wherein a value stored in the selection register corresponds to the program number, and wherein the value determines the number of the plurality of selectable delay elements utilized to delay the first stage output relative to the input of the first delay stage, and to delay the second stage output relative to the input of the second stage, wherein the circuit further comprises: a third delay stage, a fourth delay stage and a fifth delay stage, wherein each of the third delay stage, the fourth delay stage and the fifth delay stage includes the plurality of selectable delay elements; wherein an input of the third delay stage is selectably driven by one of a third signal and the second stage output, wherein the third delay stage provides a third stage output, wherein an input of the fourth delay stage is selectably driven by one of a fourth signal and the third stage output, wherein the fourth delay stage provides a fourth stage output, wherein an input of the fifth delay stage is selectably driven by one of a fifth signal and the fourth stage output, and wherein the fifth delay stage provides a fifth stage output; wherein the selection register is further communicably coupled to the third delay stage, the fourth delay stage and the fifth delay stage; and wherein the program number determines the number of the plurality of selectable delay elements utilized to delay the third stage output relative to the input of the third delay stage, to delay the fourth stage output relative to the input of the fourth stage, and to delay the fifth stage output relative to the input of the fifth stage.