Patent ID: 8927339
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method of making a thermally enhanced semiconductor assembly, comprising: providing a bump, a flange, an adhesive and a conductive layer with an aperture, wherein the bump defines a cavity that faces in a first vertical direction, covers the cavity in a second vertical direction opposite the first vertical direction, is adjacent to and integral with the flange and extends from the flange in the second vertical direction, and the flange extends laterally from the bump in lateral directions orthogonal to the vertical directions; then attaching the flange and the bump to the conductive layer via the adhesive between the flange and the conductive layer and between the bump and the conductive layer, including aligning the bump with the aperture; then mounting a semiconductor device that includes a contact pad on the bump at the cavity; and providing a build-up circuitry and a base, wherein the build-up circuitry extends from the semiconductor device and the flange in the first vertical direction and is electrically connected to the semiconductor device and the base covers the bump in the second vertical direction, is adjacent to the bump, extends laterally from the bump and includes a portion of the conductive layer that is adjacent to the aperture and spaced from the bump.