Patent ID: 8044514
Filing Date: 2011-10-25
Classification: H01L

Abstract:
1. A semiconductor integrated circuit comprising: a first wiring layer; a first dielectric layer arranged adjacent to the first wiring layer; and a ground layer arranged adjacent to a surface of the first dielectric layer opposing a surface to which the first wiring layer is adjacent, wherein the ground layer includes a second wiring layer including a ground conductor having a plurality of openings formed therein, the plurality of openings removing mechanical stress from the second wiring layer; a second dielectric layer arranged adjacent to the second wiring layer, and a third wiring layer arranged adjacent to a surface of the second dielectric layer opposing a surface to which the second wiring layer is adjacent, and including a plurality of patch conductors each of which overlaps the corresponding opening, and each of the plurality of patch conductors is electrically connected to the ground conductor by at least one via hole included in the second dielectric layer.