Patent ID: 6990538
Filing Date: 2006-01-24
Classification: H04L

Abstract:
1. A system receiving a first input stream of data, the system comprising: a plurality of deserializers generating a second input stream of data in response to the first input stream of data and generating stripped data in response to the first input stream of data; a system FIFO memory coupled to the plurality of deserializers, the system FIFO memory receiving the second input stream of data and receiving the stripped data, the system FIFO comprising a plurality of individual FIFO memories, each of the individual FIFO memories corresponding to one of the plurality of deserializers; a system state machine controlling the system FIFO memory, the system state machine comprising, a first state machine controlling one of the individual FIFO memories which corresponds with one of the plurality of deserializers, the first state machine operating in deskew disabled mode where deskewing is disabled causing said one of the plurality of individual FIFO memories under control of the first state machine to receive the second input stream of data; a second state machine controlling the system FIFO, the second state machine operating in deskew disabled mode where deskewing is disabled causing each of the plurality of individual FIFO memories to receive the stripped data; and a reset state machine controlling transition between the deskew enabled mode and the deskew disabled mode.