Patent ID: 6777280
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A method for fabricating an integrated circuit, the method comprising:introducing a dopant of a first conductivity type into a semiconductor substrate to form a first well; introducing a dopant of a second conductivity type into the first well to form a second well inside the first well; introducing a dopant of the first conductivity type into the semiconductor substrate to form a third well of the first conductivity type, wherein the third well is for holding second-conductivity-type electrodes of one or more transistors, and wherein the third well does not overlap with the first well; introducing a dopant D of the second conductivity type into a substrate region, wherein the dopant D is blocked from the third well and at least a portion of the first well, which portion is for including a low-resistance contact region for contacting the first well; forming a transistor T1 having first and second electrodes of the first conductivity type, the first electrode having at least a portion inside the first well; wherein the first electrode is connected to a voltage for: (1) biasing the first well, and (2) coupling the voltage to the second electrode when the transistor is on; and forming one or more transistors T2 having electrodes of the first conductivity type in the second well.