Patent ID: 8749287
Filing Date: 2014-06-10
Classification: H03K

Abstract:
1. A semiconductor device comprising: a first latch circuit; a second latch circuit coupled to the first latch circuit, and for receiving an output of the first latch circuit; a first switching element provided between the first latch circuit and the second latch circuit; a feedback line for feeding data held by the second latch circuit to the first latch circuit; a second switching element provided on the feedback line; an input line coupled to the first latch circuit; a third switching element provided on the input line; and a clock generating circuit for controlling operations of the first switching element, the second switching element, and the third switching element, wherein the second switching element is in an ON state during at least a part of a period during which the third switching element is in an OFF state, wherein the second switching element is in the OFF state during a part of a period during which the first switching element is in the ON state, wherein the clock generating circuit generates a first clock signal to be supplied to the first switch element and generates a second clock signal to be supplied to the second switch element by delaying the first clock signal by a certain delay.