Patent ID: 8516214
Filing Date: 2013-08-20
Classification: G06F

Abstract:
1. A memory access control device for controlling access to a plurality of memory devices with differing latency, comprising: an access unit configured to access the plurality of memory devices; and a control unit configured to control, in a case where a first access and then a second access are performed by the access unit, the timing of performing the second access by the access unit in accordance with a memory device accessed in the first access, a memory device accessed in the second access, and each of access types of the first and second accesses, wherein the access type indicates whether the access is a read access or a write access, wherein the timing between the first access and the second access is controlled independently based on an access type of the first access and a target device of the first access and an access type of the second access and a target device of the second access, and wherein a storage unit holds one or more minimum command issuing intervals corresponding to combinations of access devices and reading or writing directions of a prior command and access devices and reading or writing directions of a next command, and the control unit controls the timing based on the interval for a combination corresponding to the first access and the second access.