Patent ID: 6950491
Filing Date: 2005-09-27
Classification: H03K

Abstract:
1. A fractional divide circuit for generating a periodic fractional clock comprising: a base clock for generating a pre-divide clock at a base clock frequency; a period counter for counting cycles of said base clock; a select register for storing constants that define parameters for a fractional divide ratio, there being at least four; a positive edge flip flop and wherein two of said constants are associated therewith; a negative edge flip flop, and wherein the other of said two constants are associated therewith; a matching device for; setting on the negative edge of said base clock of said negative flip flop when the first of said two associated constants matches the output of said period counter and clearing said negative flip flop when the other of said two associated constants matches the outputs of said period counter; and ANDing the outputs of said negative and positive flip flops to provide the fractional clock output.