Patent ID: 6282686
Filing Date: 2001-08-28
Classification: G06F

Abstract:
A memory system comprising:a plurality of memory devices configured to store a data block, wherein said data block includes a plurality of data bits and a plurality of check bits and wherein each bit of said data block is assigned to one of said plurality of memory devices, wherein said bits of said data block are allocated to a plurality of logical groups, and wherein each of said plurality of logical groups includes at most one bit assigned to one of said memory devices; andan error detection circuit coupled to said plurality of memory devices, wherein said error detection circuit is configured to generate one global check bit for said data block and a plurality of check bits for said plurality of logical groups prior to storing said data block in said plurality of memory devices, wherein one of said plurality of check bits is generated for each of said plurality of logical groups, and said error detection circuit is configured after reading said data block from said plurality of memory devices to detect one or more bit errors within each of said plurality of logical groups using single error correction codes, and to determine whether said one or more bit errors detected using said error correction codes are single bit errors using said global check bit, and to correct said bit errors if said bit errors are single bit errors;wherein if said global check bit indicates an even number of errors within said data block and said error correction codes detect no errors within said plurality of logical groups, said data block is used without correction.