Patent ID: 8607024
Filing Date: 2013-12-10
Classification: G06F,Y02D

Abstract:
1. A virtual address cache memory comprising: a Translation Lookaside Buffer (TLB) virtual page memory configured to hold entry data comprising a virtual page tag, the virtual page tag being a predetermined high-order bit (most significant bit side) of a virtual address for a process, to output a hit signal when the virtual page tag corresponds to a virtual page tag from a processor, and to rewrite the entry data when a rewrite to a TLB occurs; a data memory configured to hold cache data using the virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to hold a physical address corresponding to the virtual address held in the TLB virtual page memory, and to rewrite the held physical address when the rewrite to the TLB occurs; and a second physical address memory configured to hold a physical address for the cache data held in the data memory, and to rewrite the held physical address when the cache data is written to the data memory after the occurrence of the rewrite to the TLB.