Patent ID: 6016078
Filing Date: 2000-01-18
Classification: H03F,H03K

Abstract:
A MOS technology integrated multistage differential single ended amplifier circuit comprising an input circuit composed of two differential input stages (M8, M9, M14, M15, M10, M11, M12, M13, M4, M5, M6, M7) of complementary symmetry provided with biasing means (M20, M19, M2, M3, M21) including two complementary current generators (M3, M21), referred to the supply voltage and to ground potential, respectively, and having two lines of differential output (diffA, diffB), and an output circuit (M5, M6, M67, M68, M19, M64, M69, M71) comprising a current mirror circuit (M5, M6) on the two branches of which are injected currents (Ia2, Ib2), each corresponding to the difference between a bias current generated by a respective current generator (M19, M64) and a respective differential current (Ia1, Ib1) output by said input circuit, through said output lines (diffA, diffB), characterized in that said output circuit further comprises:two diode-connected MOS transistors (M18, M65), referred to ground potential and forming respective current mirrors with said current generators (M19, M64) of said current mirror circuit, also referred to ground potential, through which said output currents (Ia1, Ib1) are respectively forced, mirroring said output currents (Ia1, Ib1) on said current generators (M19, M64) respectively, with a certain mirroring ratio, and permitting an increase of the signal currents (Ia2, Ib2) through said current mirror circuit (M5, M6) without any increase of said currents (Ia1, Ib1) output by said differential input stages;the injection nodes of said output currents (Ia1, Ib1) of said input stages on said diode-connected MOS transistors (M18, M65) been coupled to the gates of two MOS transistors (M69, M70), respectively, referred to ground potential, that provide a voltage reference to a single load S transistor (M71) of said current mirror circuit.