Patent ID: 9006817
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A semiconductor device comprising: four semiconductor pillars extending in a direction perpendicular to a substrate; a connection channel formed on the substrate and connected to one ends of the four semiconductor pillars; a source line connected to the other ends of first and second semiconductor pillars adjacent to each other among the four semiconductor pillars; a bit line connected to the other ends of third and fourth semiconductor pillars among the four semiconductor pillars; first to fourth stack structures, which are formed along the first to fourth semiconductor pillars, respectively, between the source and bit lines and the substrate and each includes a pass word line, at least one word line and a select line which are stacked over the substrate; a memory layer interposed between the word line and each of the first to fourth semiconductor pillars; and a gate insulating layer interposed between the pass word line and each of the first to fourth semiconductor pillars and between the select line and each of the first to fourth semiconductor pillars.