Patent ID: 7215188
Filing Date: 2007-05-08
Classification: H03K

Abstract:
1. An integrated circuit comprising: a first power supply bus for providing a first power supply voltage to a first plurality of circuit elements; and a second power supply bus for providing a second power supply voltage to a second plurality of circuit elements, the second power supply voltage being lower than the first power supply voltage; wherein the first power supply bus provides the first power supply voltage to the first plurality of circuit elements during a normal operating mode of the integrated circuit, and wherein the second power supply voltage is not provided to the second plurality of circuit elements during the normal operating mode of the integrated circuit, wherein the second power supply bus provides the second power supply voltage to the second plurality of circuit elements during a low power operating mode of the integrated circuit, and wherein the first power supply voltage is not provided to the first plurality of circuit elements during the low power operating mode of the integrated circuit; and wherein when the integrated circuit is transitioning from the normal operating mode to the low power operating mode the first and second power supply voltages are provided by the first and second power supply buses at the same time for a first predetermined length of time.