Patent ID: 6964896
Filing Date: 2005-11-15
Classification: H01L

Abstract:
1. A method of forming semiconductor logic circuitry, comprising: providing a first semiconductor structure; the first semiconductor structure comprising a first monocrystalline semiconductor substrate; bonding a second semiconductor structure onto the first semiconductor structure; the second semiconductor structure comprising a second monocrystalline semiconductor substrate; forming a pair of electrically conductive interconnects extending through the second monocrystalline semiconductor substrate to electrically connect with a pair of electrical nodes supported by the first monocrystalline semiconductor substrate; the pair of electrically conductive interconnects being a first electrically conductive interconnect and a second electrically conductive interconnect; forming a third electrically conductive interconnect; the third electrically conductive interconnect being in electrically connection with an electrically node supported by the second monocrystalline semiconductor substrate; and connecting the first, second and third electrically conductive interconnects to Vcc, output and ground, respectively, of a semiconductor logic circuit.