Patent ID: 6980018
Filing Date: 2005-12-27
Classification: H03K

Abstract:
1. A reduced leakage logic circuit having a first logic input and a logic output comprising: a low leakage logic path receiving the first logic input and generating a holding output coupled to the logic output; a feedback circuit having a feedback input coupled to the logic output and a first feedback output generating a first feedback signal in response to logic states of the logic output; a first high leakage logic path receiving the first logic input and generating a first drive output coupled to the logic output, the first drive output enhancing a current drive capability of a first logic state of the logic output in response to a first logic state of the logic input and a first logic state of the first feedback signal; and first power gating circuitry for coupling a first voltage potential of a power supply to the first high leakage logic path in response to the first logic state of the first feedback signal thereby enabling the first drive output and decoupling the first voltage potential from the first high leakage logic path in response to a second logic state of the first feedback signal thereby disabling the first drive output.