Patent ID: 6445250
Filing Date: 2002-09-03
Classification: H03F

Abstract:
An amplifier comprising:a plurality of cascaded NMOS differential amplifier stages, wherein a first one of said plurality of cascaded NMOS differential amplifier stages is coupled to at least one input signal; a PMOS differential amplifier stage having a first input coupled to a first NMOS differential output of a last one of said plurality of cascaded NMOS differential amplifier stages and a second input coupled to a second NMOS differential output of said last cascaded NMOS differential amplifier stage, wherein said PMOS differential amplifier comprises a first diode-connected PMOS load transistor having a gate and a drain connected to ground and a second diode-connected PMOS load transistor having a gate and a drain connected to ground; and an output differential amplifier stage comprising: load transistors comprising a first PMOS transistor having a gate and a drain connected together and a source connected to a power supply rail and a second PMOS transistor having a gate coupled to said third PMOS transistor gate and a source connected to said power supply rail; and a first differential transistor pair comprising a first NMOS transistor having a gate coupled to a source of said first diode-connected PMOS load transistor and a drain coupled to a drain of said first PMOS transistor and a second NMOS transistor having a gate coupled to a source of said second diode-connected PMOS load transistor and a drain coupled to a drain of said second PMOS transistor.