Patent ID: 7539876
Filing Date: 2009-05-26
Classification: G06F,H04L

Abstract:
1. An apparatus for performing cryptographic operations, comprising: an x86-compatible microprocessor; a control word, configured to prescribe that a provided cryptographic key be expanded into a corresponding key schedule for employment during execution of one of the cryptographic operations, wherein said control word is stored in memory, and wherein a memory location of said control word is prescribed by contents of a register that is referenced by a single atomic cryptographic instruction, wherein said single atomic cryptographic instruction is arranged according to the instruction format for execution on said x86-compatible microprocessor; fetch logic, disposed within said x86-compatible microprocessor, configured to receive said single atomic cryptographic instruction as part of an instruction flow executing on said x86-compatible microprocessor, wherein said single atomic cryptographic instruction prescribes said one of the cryptographic operations, and wherein said single atomic cryptographic instruction references said control word; translation logic, coupled to said fetch logic, configured to translate said single atomic cryptographic instruction into a sequence of micro instructions that directs said x86-compatible microprocessor to perform said one of the cryptographic operations; keygen logic, disposed within said x86-compatible microprocessor and operatively coupled to said single atomic cryptographic instruction, configured to direct said x86-compatible microprocessor to expand said provided cryptographic key into said corresponding key schedule; and execution logic, disposed within said x86-compatible microprocessor and operatively coupled to said keygen logic, configured to expand said provided cryptographic key into said corresponding key schedule, said execution logic comprising: