Patent ID: 9053681
Filing Date: 2015-06-09
Classification: G06F,G06T,G09G,H04N

Abstract:
1. An apparatus comprising one or more hardware processors, memory, and one or more modules configured to: process, in a dynamically reconfigurable heterogeneous systolic array, a first image frame to generate a plurality of image processing primitives from the first image frame; wherein the plurality of image processing primitives comprises at least one image map; store the plurality of image processing primitives and the first image frame in a memory store; based, at least in part, on the plurality of image processing primitives, determine one or more characteristics of the first image frame; based on the one or more characteristics determined for the first image frame, reconfigure the dynamically reconfigurable heterogeneous systolic array; and process, using the reconfigured dynamically reconfigurable heterogeneous systolic array, a second image frame based on the one or more characteristics.