Patent ID: 6115789
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A system for determining which memory location has been accessed in a self-timed cache, the system comprising:a content addressable memory included in the self-timed cache;a secondary memory coupled to the content addressable memory and included in the self-timed cache, wherein the secondary memory includes a plurality of memory locations, wherein an access to the self-timed cache includes asserting an address, and wherein in response to a match between the asserted address and information in the content addressable memory a match valid line is asserted and a selected memory location of the plurality of selected memory locations is accessed; andtest circuitry coupled to the content addressable memory, the test circuitry including a register file, wherein the register file stores a pointer which points to the selected memory location in response to the match valid line being asserted.