Patent ID: 6335696
Filing Date: 2002-01-01
Classification: H03M

Abstract:
A parallel-serial conversion circuit comprising:a frequency divider circuit into which a clock signal is input; a positive edge triggered flip-flop and a negative edge triggered flip-flop into which data and a dichotomized signal output by said frequency divider circuit are input; a tap signal generator into which the clock signal is input; a selection signal generator into which a pulse signal generated by said tap signal generator by delaying is input; an inverter circuit into which the dichotomized signal output by said frequency divider circuit is input; and a 10-bit parallel-serial converter into which data output by said positive edge triggered flip-flop, a signal output by said inverter circuit, data output by said negative edge triggered flip-flop, and the pulse signal output by said selection signal generator and having a width equivalent to 1 bit of serial data are input and which outputs the serial data.