Patent ID: 8841937
Filing Date: 2014-09-23
Classification: G11C,H03K

Abstract:
1. An analog sample circuit, comprising: an operational amplifier having a non-inverse input terminal coupling to a reference voltage, an inverse input terminal and an output terminal; an integration capacitor coupled between the inverse input terminal and the output terminal of the operational amplifier; a switch circuit having one terminal coupling to a first node and another terminal coupling to the reference voltage and controlled by a first clock signal; a fifth switch circuit having one terminal coupling to the first node and another terminal coupling to the inverse input terminal of the operational amplifier and controlled by a second clock signal; a sample capacitor coupled between the first node and a second node; a first switch circuit comprising a first switch control module coupled between a third node and an input signal, a constant voltage module coupled between the third node and the input signal and a first PMOSFET switch having a source coupling to the input signal, a drain coupling to the second node and a gate coupling to the third node, the first switch control module outputting a first switch signal to the third node under the control of the first clock signal, the constant voltage module generating a constant voltage as a gate-source voltage of the first PMOSFET switch when the first PMOSFET switch turns on under the control of the first switch signal, arid the first PMOSFET switch turning on and off under the control of the first switch signal; and a second switch circuit comprising a third PMOSFET switch having a source coupling to a ground, a drain coupling to the second node and a gate, and a second switch control module coupled between the gate of the third PMOSFET switch and the ground, the second switch control module outputting a second switch signal to the gate of the third PMOSFET switch under the control of the second clock signal, and the third PMOSFET switch turning on and off under the control of the second switch signal.