Patent ID: 7839706
Filing Date: 2010-11-23
Classification: G11C

Abstract:
1. A dual mode accessing signal control apparatus for use in a dummy cells set of a memory comprising a plurality of dummy cells, the dual mode accessing signal control apparatus comprising: a write delay circuit, being configured to receive an actuating signal and a pulse start signal and generate a write delay signal to the dummy cells set after the pulse start signal is transited to an accessible state and the actuating signal is transited to a writable state; an activating circuit, being configured to receive the actuating signal and the pulse start signal and generate a read signal to the dummy cells set after the pulse start signal is transited to an accessible state and the actuating signal is transited to a readable state; wherein the write delay signal is adapted to make the dummy cells set generate a first voltage decrease to induce the memory to start a write process and the write delay signal is adapted to make the dummy cells set generate a first end indication signal after a first time interval to induce the memory to end the write process; the read signal is adapted to make the dummy cells set generate a second voltage decrease to induce the memory to start a read process and the read signal is adapted to make the dummy cells set generate a second end indication signal after a second time interval to induce the memory to end the read process.