Patent ID: 8587068
Filing Date: 2013-11-19
Classification: H01L

Abstract:
1. An SRAM structure comprising: a semiconductor on insulator (SOI) substrate comprising a semiconductor substrate, an insulating layer and a semiconductor on insulator (SOI) layer, the SOI layer having a first thickness; a FinFET transistor formed on the SOI substrate comprising a first defined portion of the SOI layer of the first thickness forming an active layer of the FinFET transistor and a gate dielectric on the first defined portion of the SOI layer, the first defined portion of the SOI layer having a first width; a planar transistor formed on the SOI substrate comprising a second defined portion of the SOI layer of a second thickness forming an active layer of the planar transistor and a gate dielectric on the second defined portion of the SOI layer, the second defined portion of the SOI layer having a second width; wherein the first thickness is greater than the second thickness and wherein the first width equals the second width; and a gate electrode on the FinFET transistor and the planar transistor.