Patent ID: 7638863
Filing Date: 2009-12-29
Classification: H01L,H05K,Y02P

Abstract:
1. A method of forming a semiconductor package comprising: forming a die attach area on an intermediate substrate; forming a first plurality of connection terminals on the intermediate substrate; forming a tamper barrier on the intermediate substrate wherein the first plurality of connection terminals is between the tamper barrier and the die attach area; attaching a semiconductor die to the die attach area and electrically connecting connection points on the semiconductor die to the first plurality of connection terminals; encapsulating the semiconductor die and at least a portion of surfaces of both the first plurality of connection terminals and the tamper barrier wherein the tamper barrier is positioned between an edge of the semiconductor package and the first plurality of connection terminals and wherein a length of the tamper barrier is greater than a total width of all of the plurality of connection terminals plus an inner terminal spacing of the plurality of connection terminals; and removing the intermediate substrate.