Patent ID: 7606993
Filing Date: 2009-10-20
Classification: G06F

Abstract:
1. A memory controller for controlling access from a computer to a flash memory having a plurality of physical blocks based on address data from the computer, wherein each of the plurality of physical blocks is a minimum erasing unit and divided into a plurality of physical pages each of which is a processing unit in data reading operation and data writing operation carried out in the flash memory, the memory controller comprising: a buffer which stores data read from the flash memory or data to be written to the flash memory, wherein a range of a plurality of memory addresses corresponding to capacity of said buffer is assigned to said buffer within a memory address space of the computer; an address buffer which stores one of the plurality of memory addresses corresponding to a first portion of the address data; a first interface module which provides the computer with random access to each of all data regions of said buffer within the range of memory addresses assigned to said buffer in an access unit of the memory address space of the computer, by referring to said address buffer; an address register which stores a logical page address corresponding to a second portion of the address data, wherein the logical page address indicates a logical page for reading data from the flash memory to said buffer or for writing data from said buffer to the flash memory; a maintaining module which maintains a correspondence between at least parts of a plurality of logical block addresses and at least parts of a plurality of physical block addresses wherein the plurality of logical block addresses are allotted to all of a plurality of logical blocks respectively, each of the plurality of logical blocks is divided into a plurality of logical pages, the plurality of physical block addresses are allotted to all of the plurality of physical blocks respectively, and the correspondence between the logical block addresses and the physical block addresses dynamically changes each time data is re-written in the flash memory; an address generating module which generates a physical page address in accordance with the logical page address stored in said address register based on the correspondence maintained by said maintaining module; and a second interface module which controls data transfer between said buffer and one of the plurality of physical pages corresponding to the physical page address generated by said address generating module, wherein the data transfer is carried out with one of the plurality of physical pages as one unit.