Patent ID: 7427813
Filing Date: 2008-09-23
Classification: H01L

Abstract:
1. A semiconductor package comprising: a die having a plurality of layers of low-K dielectric material in the die, the die having a top surface including circuitry fabricated thereon, a non-active surface not including circuitry, and a plurality of side surfaces, each surface having associated corner and edge regions; a wire bonding packaging substrate having a plurality of electrical contacts, the packaging substrate being positioned under the die; a plurality of interconnects electrically connecting the die to the plurality of electrical contacts; a molding interface material applied to at least a portion of the top surface of the die, the molding interface material being configured to control at least one of tensile and shear stresses experienced by the die in the proximity of the active surface; and a molding cap including a molding compound covering at least a portion of the die, packaging substrate, interconnects, and the molding interface material; wherein the molding interface material is a discrete layer separate from the molding compound and formed between the molding cap and the die.