Patent ID: 6493817
Filing Date: 2002-12-10
Classification: G06F

Abstract:
A floating-point unit for performing arithmetic operations on data, the floating-point unit comprising:a register file configured to store and read data; a first multiply accumulate unit configured to perform arithmetic operations on a plurality of data type formats; a second multiply accumulate unit configured to perform arithmetic operations on a plurality of data type formats; a first bypass component configured to receive data from the register file and to transmit the data to the first multiply accumulate unit, the first bypass component further configured to receive results of arithmetic operations performed by the first multiply accumulate unit and to transmit the results from the first multiply accumulate unit to the register file; and a second bypass component configured to receive data from the register file and to transmit the data received by the second bypass component to the second multiply accumulate unit, the second bypass component further configured to receive results of arithmetic operations performed by the second multiply accumulate unit and to transmit the results of the arithmetic operations performed by the second multiply accumulate unit to the register file, wherein each of the multiply accumulate units receives a 64-bit word and wherein the first multiply accumulate unit selects the upper 32 bits of the 64-bit word to operate on and wherein the second multiply accumulate unit selects the lower 32 bits of the 64-bit word to operate on and wherein each of the multiply accumulate units is provided with one or more bits which the multiply accumulate units use to determine which 32-bit portions of the 64-bit word are to be operated on by the respective multiply accumulate unit.