Patent ID: 8942036
Filing Date: 2015-01-27
Classification: G11C,H01L

Abstract:
1. A method for achieving four-bit storage using a flash memory having a splitting trench gate, wherein the flash memory having the splitting trench gate is based on a planar structure including: a tunneling oxide layer, a silicon nitride trap layer, a blocking oxide layer and a control gate sequentially disposed over a channel; two trenches having an identical structure each disposed between a source and the channel and between a drain and the channel, respectively, wherein one side of each of the trenches contacts the channel, and the other side of each of the trenches contacts the source or the drain; a splitting trench gate structure formed in the channel, which is formed by a planar channel in the middle and two non-planar channels corresponding to the trenches; the trenches and the channel completely covered by the control gate and a gate stack structure that includes the tunneling oxide layer, the silicon nitride trap layer and the blocking oxide layer; and the control gate having two protruding portions corresponding to the trenches, the method comprising: achieving the storing of first and second bits by programming electrons at one side of each of the two trenches that contacts the channel by using a channel hot electron injection method; achieving the storing of third and fourth bits by programming electrons at the other side of each of the two trenches that contacts the source or the drain by using an FN tunneling injection method, wherein the tunneling oxide layer is configured as a tunneling channel and the silicon nitride trap layer is configured to store electrons; and determining storage states of the third and fourth bits by reading a gate-induced drain leakage current at the other side of each of the two trenches that contacts the source or the drain.