Patent ID: 7126829
Filing Date: 2006-10-24
Classification: H01L,H05K

Abstract:
1. A multi-chip package comprising: an upper arrayed package having a two-dimensional array of electrical connections with at least four rows and four columns; a lower arrayed package having a two-dimensional array of electrical connections with at least four rows and four columns; an intermediate adapter card between the upper arrayed package and the lower arrayed package; a bottom adapter card between the lower arrayed package and a circuit board; first metal contacts on a first surface of the intermediate adapter card, the first metal contacts disposed in an array to match the two-dimensional array of electrical connections of the upper arrayed package; lead frame pins that wrap around edges of the intermediate adapter card from the first surface to below a second surface of the intermediate adapter card; first metal traces on the first surface of the intermediate adapter card to electrically connect the first metal contacts to the lead frame pins; peripheral pads around a periphery of a first surface of the bottom adapter card, the peripheral pads disposed to make electrical contact with the lead frame pins from the intermediate adapter card; second metal contacts on the first surface of the bottom adapter card, the second metal contacts disposed in an array to match the two-dimensional array of electrical connections of the lower arrayed package; second metal traces on the first surface of the bottom adapter card to electrically connect the second metal contacts to the peripheral pads; and final bonding pads on a second surface of the bottom adapter card, for making electrical contact with the circuit board, whereby the upper arrayed package and the lower arrayed package are stacked together using the intermediate adapter card and the bottom adapter card to route arrayed electrical connections to the periphery.