Patent ID: 8132128
Filing Date: 2012-03-06
Classification: G03F

Abstract:
1. A method for performing lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout, the method comprising: receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process, wherein the first mask and the second mask are obtained by partitioning the mask layout; receiving an evaluation point on the mask layout; determining whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere; and computing, by computer, a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere.