Patent ID: 8386209
Filing Date: 2013-02-26
Classification: G01R,H03M

Abstract:
1. A test system comprising: a memory for storing sample data and instructions; a dynamic test engine adapted to control input of dynamic test waveforms including sinusoidal waveforms to a device under test and to determine device under test dynamic parameters by analysing the samples; a linear test engine adapted to determine device under test static parameters, and to control input of ramp input waveforms to the device under test; a test controller adapted to perform finite state machine control of testing of an ADC device under test by the linear test engine and by the dynamic test engine, a programmable digital to analog converter for controlled waveform generation under instructions from the linear test engine and the dynamic test engine; and an interface for communication with an external host, wherein the linear and dynamic test engines are adapted to perform parallel linear and dynamic testing in which dynamic testing sample processing takes place during application of a ramped input for linear testing, wherein the linear test engine is adapted to extract static parameters from a device under test over a single ramp period on-the-fly as dynamic test samples are being processed, wherein the linear test engine is adapted to determine ADC static parameters by keeping a record of ADC code counts including unstable code transition points using a single increasing ramp voltage which is clock synchronized with an ADC under test.