Patent ID: 6031260
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A semiconductor memory device comprising:a substrate;a first insulation layer formed on said substrate;a plurality of separated bit lines arranged to extend in one direction on said first insulation layer;a second insulation layer formed over all of said plurality of bit lines and having a plurality of openings extending through the second insulation layer;a plurality of via conductive layers buried into at least said plurality of openings;an element isolating region formed on said second insulation layer;a plurality of element forming semiconductor regions each of said element forming semiconductor regions being formed as an island surrounded by said element isolating region;a plurality of transistors formed in said plurality of element forming semiconductor regions, each of said plurality of transistors including,a gate electrode formed on an insulating layer over a corresponding one of said plurality of element forming semiconductor regions, said gate electrode extending in a direction crossing said plurality of bit lines and serving as a word line,a gate side wall insulator provided on each of two opposite facing side walls of said gate electrode,a first and second diffusion region formed in said corresponding one of said plurality of element forming semiconductor regions, each said first and second diffusion region being adjacent to one of the two opposite facing side walls of said gate electrode and extending in a direction crossing said word line, said first diffusion region being connected to a corresponding one of said plurality of bit lines through a corresponding one of said plurality of via conductive layers;a plurality of capacitors corresponding to said plurality of transistors, each of said plurality of capacitors including,a storage electrode formed on said second diffusion region, said storage electrode being electrically connected to said second diffusion region,a capacitor insulation film formed on said storage electrode, anda plate electrode formed on said capacitor insulation film, said plate electrode being connected in common to said plurality of capacitors; andwherein each of said plurality of openings has a side wall having a portion which is vertically aligned with an outer surface of a corresponding said gate side wall insulator of a corresponding one of said plurality of transistors.