Patent ID: 6418045
Filing Date: 2002-07-09
Classification: G11C

Abstract:
A Programmable Logic Array (PLA) having an operating voltage of Vcc, and a configuration memory comprising:a plurality of memory cells each having first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage-controlled Vmm line; a passgate transistor for each of the plurality of cells, the passgate transistor connected source-to-drain from a BIT line to the first inverter output, the passgate having a strength sufficiently low that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch; and circuitry for reducing the voltage of Vmm during write operations so a signal on the BIT line may flip the latch through the passgate; wherein the weak passgates reduce effect on the Q and QB nodes of the memory cells during read operations sufficiently that the PLA can be operated during configuration memory read operations.