Patent ID: 8453102
Filing Date: 2013-05-28
Classification: G06F,Y02P

Abstract:
1. A method comprising: providing an extraction of an integrated circuit design; using the extraction, compiling an interconnect model comprising circuit blocks of the integrated circuit design arranged in a hierarchical tree structure; allowing selecting of a netlist element parameter for variation, wherein the netlist element parameter comprises at least one of an impedance value, voltage source value, or current source value; calculating a first value for the netlist element parameter for variation; calculating a second value for the netlist element parameter for variation; using at least one processor, using the interconnect model and the first value for the netlist element parameter, performing a first circuit simulation of the integrated circuit design and saving results for each of the circuit blocks of the hierarchical tree structure; with the second value, identifying circuit blocks of the hierarchical tree structure that are affected by the change in the netlist element parameter, including circuit blocks in a dependency path of the affected circuit blocks, as affected circuit blocks, wherein other blocks which are not affected are unaffected circuit blocks and the affected circuit blocks are a subset of a total number of circuit blocks; and using at least one processor, using the interconnect model and the second value, performing a second circuit simulation of the integrated circuit design, the second circuit simulation being subsequent to the first circuit simulation, by calculating results for the affected circuit blocks while reusing the results for unaffected blocks from the first circuit simulation, wherein the allowing selecting of a netlist element parameter for variation, wherein the netlist element parameter comprises at least one of an impedance value, voltage source value, or current source value comprises: allowing selecting of two or more netlist element parameters for variation, wherein the netlist element parameter is a first netlist element for variation, and the first value and second values are for the first netlist element; calculating a third value for a second netlist element parameter for variation; calculating a fourth value for the second netlist element parameter for variation, wherein for the first circuit simulation, the first value is used for the first netlist element parameter and the third value is used for the second netlist element parameter, and for the second circuit simulation, the second value is used for the first netlist element parameter and the third value is used for the second netlist element parameter; with the first and fourth values, identifying circuit blocks of the hierarchical tree structure that are affected by the change in the netlist element parameter, including circuit blocks in a dependency path of the affected circuit blocks, as affected circuit blocks, wherein other blocks which are not affected are unaffected circuit blocks and the affected circuit blocks are a subset of a total number of circuit blocks; using the interconnect model and the first and fourth values, performing a third circuit simulation of the integrated circuit design, the second circuit simulation being subsequent to the first circuit simulation, by calculating results for the affected circuit blocks while reusing the results for unaffected blocks from at least one of the first or second circuit simulations; with the second and fourth values, identifying circuit blocks of the hierarchical tree structure that are affected by the change in the netlist element parameter, including circuit blocks in a dependency path of the affected circuit blocks, as affected circuit blocks, wherein other blocks which are not affected are unaffected circuit blocks and the affected circuit blocks are a subset of a total number of circuit blocks; and using the interconnect model and the second and fourth values, performing a fourth circuit simulation of the integrated circuit design, the second circuit simulation being subsequent to the first circuit simulation, by calculating results for the affected circuit blocks while reusing the results for unaffected blocks from at least one of the first, second, or third circuit simulations.