Patent ID: 9160388
Filing Date: 2015-10-13
Classification: H03D,H03F,H04B,Y10T

Abstract:
1. A circuit for a low-power and blocker-tolerant mixer-amplifier stage, the circuit comprising: a complementary mixer formed by transmission gates having complementary structures, the complementary mixer being configured to receive one or more radio-frequency (RF) signals and to convert the one or more RF signals to intermediate frequency (IF) current signals; and a complementary TIA coupled to the complementary mixer and configured to receive the IF current signals and to provide IF voltage signals, the complementary TIA being formed by coupling an NMOS-TIA and a PMOS-TIA to a common load, wherein a first portion of the complementary mixer is coupled to the NMOS-TIA and a second portion of the complementary mixer is coupled to the PMOS-TIA.