Patent ID: 6310300
Filing Date: 2001-10-30
Classification: H01L,Y10S

Abstract:
An integrated circuit structure, comprising:a substrate;a patterned metallization formed on said substrate;a fluorine-containing insulator layer formed on said substrate and adjacent said patterned metallization, wherein fluorine migrates from said fluorine-containing insulator layer during formation on said substrate;first fluorine-free barrier means for preventing fluorine induced corrosion of said patterned metallization during formation of said flourine-containing insulator layer, said first flourine-free barrier means being located between said fluorine containing insulator layer and said patterned metallization;an opening formed through said fluorine-free barrier layer and said fluorine containing insulator layer and communicating with a surface of said patterned metallization;metal located within said opening and contacting side walls of said fluorine-free barrier layer and said fluorine containing insulator layer and the surface of said patterned metallization; andsecond fluorine-free barrier means for preventing fluorine induced corrosion of a second patterned metallization formed on said second flourine-free barrier means, said second flourine-free barrier means formed on said fluorine-containing insulator layer.