Patent ID: 6426912
Filing Date: 2002-07-30
Classification: G11C

Abstract:
A test circuit for testing a semiconductor memory comprising a memory cell array having first and second memory cell blocks, comprising:a register which holds first and second test data; a data-writing circuit which simultaneously writes the first test data to a first memory cell in said first memory cell block and the second test data to a second memory cell in said second memory cell block; a data-reading circuit which simultaneously reads first read data stored in said first memory cell and second read data stored in said second memory cell; a comparing circuit which compares the first read data with the first test data and outputs first output data, and which compares the second read data with the second test data and outputs second output data; and a determining circuit which determines whether the first and second memory cells are flawless based on the first and second output data, and said determining circuit outputs one-bit data which shows defective when at least one of the first and second output data shows that the at least one of the first and second memory cells is defective, wherein said determining circuit outputs a first signal which shows whether the first memory cell is flawless and a second signal which shows whether the second memory cell is flawless, when at least one of the first and second output data shows that the at least one of the first one of the first and second memory cells is defective.