Patent ID: 6156601
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A method of forming a cell array of a DRAM having a semiconductor substrate having a first impurity region, a second impurity region, and a third impurity region, a first word line electrically connected to the first and second impurity regions, a second word line electrically connected to the second and third impurity regions, a first insulating layer having a second contact hole, a second insulating layer having a first contact hole and a third contact hole, a bit line electrically connected to the second impurity region through the second contact hole, a first capacitor, on the second insulating layer, with a hexagon-shaped planar portion above the first region, electrically connected to the first impurity region through the first contact hole, and a second capacitor, on the second insulating layer, with a hexagon-shaped planar portion above the second region, electrically connected to the third impurity region through the third contact hole, the method comprising the steps of:arranging the contact holes such that a respective first contact hole, second contact hole, and third contact hole are connectable by the imaginary straight line;arranging the first word line between the first contact hole and the second contact hole;arranging the second word line between the second contact hole and the third contact hole so as to be symmetric with the first word line relative to the central point of the second contact hole;disposing the central point of the second contact hole to be on the central line of the bit line;arranging the bit line to be a straight line forming an angle .theta..sub.21 of 0.degree.<.theta..sub.21 <90.degree. counterclockwise and an angle .theta..sub.22 of 90.degree.<.theta..sub.22 <180.degree. clockwise against the respective center lines of the first and second word lines; andarranging the first and second capacitors such that the respective central points of the first and third contact holes are aligned with the central lines of the first and second capacitors, respectively, and so that one side of the hexagon-shaped planar portion of the second capacitor is parallel to one side of the hexagon-shaped planar portion of the first capacitor.