Patent ID: 9123570
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a substrate, comprised of silicon having a first crystal lattice orientation; a layer of directly bonded silicon (DSB) having a second crystal lattice orientation located on a top surface of said substrate; a layer of selective epitaxial growth (SEG) silicon having said first crystal lattice orientation on said top surface of said substrate in a first region for a first type of MOS transistor wherein an interface between said layer of SEG silicon and said substrate is lower than an interface between said layer of DSB and said substrate; a region of STI field oxide located between said layer of DSB and said layer of SEG silicon such that the field oxide extends into said substrate; a first type of well formed in said SEG layer and said substrate in said first region; a second type of well formed in a second region for a second type of MOS transistor in said DSB layer and said substrate that is different than said first region; a first type of MOS transistor formed on and in said first type of well; a second type of MOS transistor formed on and in said second type of well.