Patent ID: 8258629
Filing Date: 2012-09-04
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; the top low-k dielectric layer comprising a first portion and a second portion horizontally aligned with the first portion, wherein a mechanical strength of the first portion is greater than a mechanical strength of the second portion, wherein the first portion and the second portion are formed of a same material; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; a first reflective metal pad in the second low-k dielectric layer and completely enclosed by the second low-k dielectric material and an etch stop material, wherein the first reflective metal pad is electrically floating; and a bond pad overlying the first reflective metal pad, wherein the bond pad and the first reflective metal pad are substantially vertically aligned and wherein the first portion is substantially aligned with the bond pad and the first reflective metal pad.