Patent ID: 6238983
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method of providing a code implant for a read-only memory (ROM), comprising the steps of:providing on a semiconductor wafer partially completed semiconductor devices each with at least a gate electrode, a channel region, and a source and a drain;forming a polyoxide layer overlying said gate electrodes;dipping back said polyoxide layer over selected gate electrodes, where said polyoxide layer after dip back ranges from 200 to 500 .ANG.ngstrom to improve the implant process window;double charge implanting code information into said polyoxide layer over said selected gate electrodes, said polyoxide thus providing a conductive channel extending from said source to said drain; anddouble charge implanting code information below said selected gate electrodes thereby converting an enhancement mode transistor to a depletion mode transistor.