Patent ID: 8629861
Filing Date: 2014-01-14
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer disposed on the gate line; a data line including a source electrode, and a drain electrode facing the source electrode and disposed on the gate insulating layer; a passivation layer disposed on the gate insulating layer, the data line, and the drain electrode; an insulating layer including an organic material having negative photosensitivity disposed on the passivation layer, and including a first portion of a first thickness and a second portion of a second thickness which is smaller than the first thickness, the thicknesses taken perpendicular to the substrate; and a pixel electrode, a first contact assistant, and a second contact assistant disposed on the insulating layer, wherein the pixel electrode is disposed on the first portion of the insulating layer, the first and second contact assistants are disposed on the second portion of the insulating layer, and the second thickness of the second portion is less than about 1.5 micrometers.