Patent ID: 7884414
Filing Date: 2011-02-08
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a first memory cell transistor, the first memory cell transistor comprising: a second memory cell transistor which is disposed to neighbor the first memory cell transistor in the wiring direction of the first control electrode, with a first device isolation insulation film being interposed, the first floating electrode portion of the first memory cell is in contact with the first device isolation insulation film, the second memory cell transistor comprises: a third memory cell transistor which is disposed to neighbor the first memory cell transistor in the wiring direction of the first control electrode, with a second device isolation insulation film being interposed, and the second floating electrode portion of the first memory cell is in contact with the second device isolation insulation film, the third memory cell transistor comprises: wherein the first memory cell transistor and the second memory cell transistor are located mirror-symmetrical in the wiring direction of the first control electrode, and the first memory cell transistor and the third memory cell transistor are mirror-symmetrical in the wiring direction of the first control electrode, and an upper surface of the second device isolation insulating is higher than that of the first device isolation insulation, and a bottom surface of the control electrode provided on the second device isolation insulation is higher than an upper surface of the second floating electrode.