Patent ID: 6657735
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A critical location evaluation method for a semiconductor apparatus pattern, comprising:comparing first pattern data corresponding to no critical location with second pattern data corresponding to a critical location with respect to said same semiconductor apparatus pattern; extracting a difference between said first pattern data and said second pattern data as characteristic information indicating a characteristic of said critical location and coordinate information indicating a coordinate of said critical location, with respect to a location causing said difference; visually displaying a first pattern corresponding to said first pattern data, said coordinate information about said critical location obtained from said extraction step, and said characteristic information indicating said characteristic of said critical location; obtaining an actual pattern image by means of a microscope based n said coordinate information about said critical location; overlapping said first pattern with said actual pattern image; and measuring a divergent distance between said first pattern and said actual pattern image at said critical location and determining whether the divergent distance satisfies a rated value.