Patent ID: 6168959
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method of manufacturing a ferroelectric memory device, comprising the steps of: providing a substrate in which a device separation film and a transistor are formed; forming a first interlayer insulating film on the entire structure and then forming a contact hole for bit lines and a contact hole for contact leading pad; forming and patterning a first conductive layer on the entire structure to form a bit line and a contact leading pad, respectively; forming a second interlayer insulating film on the entire structure including said bit line and said contact leading pad, sequentially forming materials for a lower electrode, ferroelectric materials and materials for upper electrode on the entire structure and then patterning it to form a capacitor consisting of the lower electrode, the ferroelectric film and the upper electrode; forming a third interlayer insulating film on the entire structure, and then etching a portion of said third interlayer insulating film on said capacitor and some portion of said third and second interlayer insulating films on said contact leading pad to form a contact hole for connecting the capacitor through which said upper electrode of said capacitor and the upper portion of said contact leading pad can be exposed; and forming a second conductive layer on the entire structure so that said contact hole for connecting said capacitor can be entirely buried, and then patterning it to forming a local interconnection line.