Patent ID: 8055809
Filing Date: 2011-11-08
Classification: G06F

Abstract:
1. An apparatus for distributing at least one signal over a microprocessor, the apparatus comprising: a performance monitoring unit (PMU) of the microprocessor, the PMU controlled by content of a monitor control register of the microprocessor; at least one unit of the microprocessor monitored by the PMU, wherein each unit of said at least one unit comprises a respective bus ramp associated with a respective base address that identifies said each unit, wherein said at least one unit is selected from a group consisting of an instruction scheduling unit (ISU), an instruction fetch unit (IFU), a vector/scalar unit (VSU), a load/store unit (LSU), and combinations thereof; a configuration bus coupling the PMU to said at least one unit in a first daisy chain passing a sequence of configuration signals unidirectionally from the PMU toward said at least one unit via a respective bus ramp of said at least one unit such that the PMU sends the sequence of configuration signals comprising a first base address to said at least one unit via the configuration bus in selectively controlling a destination unit of said at least one unit that has a first base ramp identified by the first base address; and an event bus coupling said at least one unit to the PMU in a second daisy chain passing a sequence of event signals unidirectionally from said at least one unit toward the PMU via the respective bus ramp of said at least one unit such that the PMU receives the sequence of event signals from said at least one unit via the event bus, wherein the PMU uniquely identifies a source unit of said at least one unit that had sent the received event signals by examining a second base address associated with a second base ramp of the source unit.