Patent ID: 8106437
Filing Date: 2012-01-31
Classification: H01L

Abstract:
1. A semiconductor storage device comprising: an active region defined by a trench formed in an upper portion of a semiconductor substrate and where a memory cell is formed; an element isolation insulating film formed in said trench; a MOS transistor formed in said active region; and a capacitor having a lower electrode which is an impurity diffusion layer connected to a source or drain region of said MOS transistor, a dielectric layer formed on a surface of said impurity diffusion layer, and an upper electrode formed on said dielectric layer, wherein said element isolation insulating film having a recess therein between adjacent memory cells in an extended direction of a gate electrode of said MOS transistor which exposes an inner wall of said trench, said impurity diffusion layer and said dielectric layer extend from an upper surface of said active region along the inner wall of said trench which is exposed in said recess, said upper electrode has a first portion buried in said recess and a second portion which is not buried in said recess, said second portion extends closer to a gate electrode of said MOS transistor than said recess at an element isolation region between adjacent memory cells in the extended direction of said gate electrode in a cross-sectional view perpendicular to the extended direction of said gate electrode, and a step is formed in a portion of the lower electrode and dielectric layer underlying the second portion of the upper electrode.