Patent ID: 9152423
Filing Date: 2015-10-06
Classification: G06F

Abstract:
1. A computer-implemented method in which a computer system performs operations comprising: saving Program Counter content to a register; scanning a bit vector wherein said computer system comprises a multi-threaded packet processor, wherein a bit of said bit vector correlates to a packet processing feature and wherein said packet processing feature comprises one of the group consisting of packet mirroring, packet re-mark, IP fix and packet policing; detecting the presence of a bit of said bit vector set to a first state; setting said bit to a second state; using a bit position of said bit that was set to a first state to look up an instruction address for a routine corresponding to said bit set to a first state; executing said routine; and repeating said scanning, said detecting, said setting and said using until there are no remaining bits of said bit vector set to said first state, wherein said repeating said scanning, said detecting, said setting and said using comprises performing a branch to said register in order to execute said instruction again.