Patent ID: 8384648
Filing Date: 2013-02-26
Classification: G09G,G11C

Abstract:
1. A driving unit for a liquid crystal display device which includes a plurality of gate lines and data lines arranged horizontally and longitudinally on a substrate, and a plurality of pixels arranged on the substrate along each gate line, comprising: a first group of driving stages made of odd numbered stages being disposed in odd numbered rows for receiving a high potential voltage and a low potential voltage, being set by a first gate start voltage from the exterior, and applying a scanning signal to the gate lines of odd numbered row by being synchronized with a first clock signal and a second clock signal, the first and second clock signals alternately applied to the odd numbered row, the first and second clock signals having two horizontal periods; and a second group of driving stages made of even numbered stages being disposed in even numbered rows for receiving the same high potential voltage and low potential voltage, being set by a second gate start voltage from the exterior, and applying a scanning signal to the gate lines of even numbered row by being synchronized with a third clock signal and a fourth clock signal, the third and fourth clock signals alternately applied to the even numbered row, the third and fourth clock signals having two horizontal periods, wherein the odd numbered stages and the even numbered stages are alternatingly disposed with respect to each other in parallel so that one odd numbered stage is immediately positioned below or above one even numbered stage, wherein all the odd numbered stages and the even numbered stages receive the same high potential voltage through a single high potential voltage line, and all the odd numbered stages and the even numbered stages receive the same low potential voltage through a single low potential voltage line, wherein the first group and the second group are individually driven by the first gate start voltages and the second gate start voltage, wherein the first gate start voltage and the second gate start voltage are simultaneously applied to the first stage of the first group and the first stage of the second group, wherein the first gate start voltage is applied two horizontal periods prior to the first clock signal of the first group and the first clock signal of the first group is applied two horizontal periods prior to the second clock signal of the first group, and the second gate start voltage is applied two horizontal periods prior to the third clock signal of the second group and the third clock signal of the second group is applied two horizontal periods prior to the fourth clock signal of the second group, wherein the first, second, third and fourth clock signals all have a same polarity, wherein each of the odd and even numbered stages outputs scanning signals to sequentially drive the gate lines by being synchronized with the first and second clock signals, and the third and fourth clock signals, wherein each of the odd and even numbered stages except for the first stage of the first group and the first stage of the second group uses a scanning signal of the previous stage in the same group as a gate start voltage by being arranged alternately each other, and wherein each of the odd and even numbered stages except for the last stage of the first group and the last stage of the second group uses a scanning signal of the next stage in the same group as a gate stop voltage by being arranged alternately each other, wherein a scanning signal output from one of the driving stages in the first or second group is output to one of the gate lines and at the same time, is input directly to a transistor of the next stage in the same group, wherein said transistor is directly connected to a gate electrode of a different transistor, and said different transistor turns a corresponding stage scanning signal into the low potential.