Patent ID: 6362045
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method to form non-volatile memory cells in the manufacture of an integrated circuit device comprising:providing a semiconductor substrate; growing a tunneling oxide layer overlying said semiconductor substrate; depositing a polysilicon layer overlying said tunneling oxide layer; implanting nitrogen into said polysilicon layer to form a nitridized surface region; thereafter patterning said polysilicon layer and said tunneling oxide layer to form floating gates; growing a bottom silicon dioxide layer overlying said floating gates where said growing is by thermal oxidation of said polysilicon layer and wherein said nitridized surface region reduces the rate of said thermal oxidation and cause a smooth surface to be grown; depositing a silicon nitride layer overlying said bottom silicon dioxide layer; forming a top silicon dioxide layer overlying said silicon nitride layer; depositing a conductive layer overlying said top silicon dioxide layer; and patterning said conductive layer, said top silicon dioxide layer, said silicon nitride layer, and said bottom silicon dioxide layer to form control gates and to complete said non-volatile memory cells in the manufacture of the integrated circuit device.