Patent ID: 7795097
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a patterned sacrificial gate layer on a semiconductor substrate; forming source/drain extension regions in the semiconductor substrate adjacent the patterned sacrificial gate layer; forming sidewall spacers on sidewalls of the patterned sacrificial gate layer, the source/drain extension regions extending under the sidewall spacers; forming deep source/drain regions in the semiconductor substrate adjacent the sidewall spacers; performing at least one activation anneal to activate the source/drain extension regions and the deep source/drain regions; after performing the at least one activation anneal, removing the sidewall spacers; forming a nitride layer on sidewalls and on top of the patterned sacrificial gate layer subsequent to removing the sidewall spacers; forming a dielectric layer over the nitride layer; removing upper portions of the nitride layer and the dielectric layer to expose a top of the patterned sacrificial gate layer, wherein sidewall portions of the nitride layer remain on sidewalls of the patterned sacrificial gate layer; after exposing the top of the patterned sacrificial gate layer, removing the patterned sacrificial gate layer to form a cavity between the sidewall remaining portions of the nitride layer; and forming at least one metal gate layer within the cavity.