Patent ID: 6031249
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A semiconductor device having a CMOS structure, said semiconductor device comprising:an n-channel semiconductor device;a p-channel semiconductor device which is complementarily combined with said n-channel semiconductor to form said CMOS structure, said p-channel semiconductor device having an active layer including a channel region; anda substrate having an insulating surface on which said n-channel semiconductor device and said p-channel semiconductor device are formed;wherein at least the channel region of the active layer of only said p-channel semiconductor device is doped with a p-type impurity element;wherein the distribution of concentration of said p-type impurity element depth wise tends to decrease in the inside of the active layer approaching the interface between said channel region and a thermal oxide film formed on said active layer; andwherein said p-type impurity element in said interface is used to control a threshold voltage.