Patent ID: 8994098
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first pillar transistor including a first diffusion layer on an upper portion of a first silicon pillar formed on a substrate, a second diffusion layer on a lower portion of the first silicon pillar, and a first gate electrode formed via a first gate insulator film so as to cover a surface of the first silicon pillar between the first diffusion layer and the second diffusion layer; a second pillar transistor including a third diffusion layer on an upper portion of a second silicon pillar formed on the substrate, a fourth diffusion layer on a lower portion of the second silicon pillar, and a second gate electrode formed via a second gate insulator film so as to cover a surface of the second silicon pillar between the third diffusion layer and the fourth diffusion layer; a third pillar transistor including a fifth diffusion layer on an upper portion of a third silicon pillar formed on the substrate, a sixth diffusion layer formed on a lower portion of the third silicon pillar, and a third gate electrode formed via a third gate insulator film so as to cover a surface of the third silicon pillar between the fifth diffusion layer and the sixth diffusion layer; a first node to which the first diffusion layer and the third diffusion layer are connected in common and to which the fifth diffusion layer is not connected; and a second node to which the first gate electrode and the second gate electrode are connected in common and to which the third gate electrode is not connected, wherein the first pillar transistor and the second pillar transistor are arranged with no other pillar transistor therebetween, and a distance between the first silicon pillar and the second silicon pillar is smaller than a distance between the third silicon pillar and the first silicon pillar.