Patent ID: 7605663
Filing Date: 2009-10-20
Classification: H03L

Abstract:
1. A Phase Lock Loop (PLL), comprising: a phase frequency detector, used for receiving a feedback signal and a reference signal and outputting a pull-up signal and a pull-down signal after comparing the feedback signal to the reference signal; a device for stabilizing the output of the PLL, used for receiving the reference signal and for outputting a frequency control signal in response to the reference signal with a frequency lower than or equal to a default value, wherein the device for stabilizing the output of the PLL comprises: a charge pump, having an output end for outputting a voltage signal, used for receiving the pull-up signal and the pull-down signal and the frequency control signal and to output the voltage signal according to the pull-up signal, the pull-down signal and the frequency control signal, comprising: a voltage control oscillator VCO, receiving the voltage signal and used for outputting an oscillating signal according to the voltage signal; and a frequency divider, used for dividing frequency of the oscillating signal and then for outputting the frequency-divided oscillating signal as the feedback signal.