Patent ID: 6303275
Filing Date: 2001-10-16
Classification: G03F

Abstract:
A method of resist filling and planarization for the fabrication of semiconductor devices comprising the steps of:providing a wafer having a plurality of recesses in a surface of the wafer;applying to said surface of said wafer and the surfaces of said recesses a layer of a selected material having an affinity to a resist coat to be applied subsequently over said selected material layer;applying a resist coat over said selected material layer;allowing said selected material layer to diffuse partially into said resist coat to condition a portion of said resist coat closest to said wafer to be insoluble in the presence of a developer applied subsequently to said resist coat; andapplying a developer to said resist coat to remove portions of said resist coat:(a) spaced from said wafer by said portion of said resist coat into which said selected material layer has diffused and which has been conditioned to be insoluble in the presence of said developer, and(b) into which said selected material layer has not diffused and which has not been conditioned to be insoluble in the presence of said developer.