Patent ID: 6434727
Filing Date: 2002-08-13
Classification: G06F

Abstract:
A method of making a hard macro cell, said hard macro cell having a data input end, a clock input end, and an internal synchronous flip-flop, said data input end of said hard macro cell being connected to a data input end of said internal synchronous flip-flop directly or by way of a combinational circuit, said method comprising the steps of:specifying an interval between an edge time point of a signal at said data input end of said hard macro cell and an active edge time point of a signal at said clock input end of said hard macro cell; and connecting a delay cell between said data input end of said hard macro cell and said data input end of said internal synchronous flip-flop so that no timing error occurs in said internal synchronous flip-flop, if said specified interval is satisfied; whereby said hard macro cell having said specified interval is made and it is ensured that no timing error occurs in said internal synchronous flip-flop, if said specified interval is satisfied.