Patent ID: 6150206
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method of forming an integrated circuit capacitor, comprising the steps of:forming a first electrically insulating layer on a semiconductor substrate;forming a recess in the first electrically insulating layer;forming a contact hole which expose the semiconductor substrate, in the first electrically insulating layer;forming a first electrically conductive layer on a sidewall and bottom of the recess and in the contact hole;forming a dielectric layer on the first electrically conductive layer;forming a second electrically conductive layer, on the dielectric layer; opposite the first electrically conductive layer;planarizing the first and second electrically conductive layers simultaneously to define first and second capacitor electrodes in the recess and define a conductive plug in the contact hole that is electrically disconnected from the first capacitor electrode; and thenforming a first wiring layer which electrically connects the conductive plug to the first capacitor electrode, on the first electrically insulating layer.