Patent ID: 6115792
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A cache, comprising:a tag array storing a plurality of tags, said tag array coupled to receive an input address and configured to select a first tag row storing a first tag subset of said plurality of tags, each tag in said first tag subset stored in a respective way of said first tag row;a data array comprising storage locations arranged in a plurality of rows and a plurality of columns, wherein one of said storage locations is located at each intersection of one of said plurality of rows and one of said plurality of columns;a first decoder coupled to receive said input address and configured to assert a first decoder signal indicative of a selection of a first row subset of said plurality of rows in response to said input address;a way prediction array configured to store a plurality of way predictions, said way prediction array comprising a plurality of entries, each entry corresponding to a respective tag row in said tag array, wherein said way prediction array is configured to output a first way prediction from a first entry of said plurality of entries in response to said input address, and wherein said first way prediction is indicative of a first way of said first tag row which is predicted to be a hit for said input address, said first way storing a first tag of said first tag subset, and wherein said first entry corresponds to said first row subset; andcircuitry coupled to receive said first decoder signal and said first way prediction, wherein said circuitry is configured to select a first row from said first row subset responsive to said first way prediction, said first row including a first storage location storing data from a first cache line corresponding to said first tag.