Patent ID: 6247155
Filing Date: 2001-06-12
Classification: G01R

Abstract:
A method of simulating an integrated circuit die, comprising:providing a software model of the integrated circuit die having a plurality of input/output pads;providing a first bonding pattern between the input/output pads and a first integrated circuit package with a first plurality of I/O pins;providing a second bonding pattern between the input/outputs pads and a second integrated circuit package with a second plurality of I/O pins;maintaining a database comprising a first pin map describing a coupling between the first plurality of I/O pins and pins of a tester and a second pin map describing a coupling between the second plurality of I/O pins and the tester pins;selecting one of the first and second integrated circuit packages for testing the integrated circuit die; andcoupling the I/O pins of the selected integrated circuit package to the tester pins according to the first pin map if the first integrated circuit package is selected and according to the second pin map if the second integrated pin map is selected.