Patent ID: 6097637
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A memory system comprising:a plurality of memory cells for storing one of a plurality of threshold levels in said memory cells, wherein said threshold levels demarcate 2.sup.n number of windows for designating states to represent storage of ""n""-bits of data for said memory cells;a switch control for permitting selection of an operating mode for said memory system including a multi-level cell mode and a standard cell mode;a reading circuit coupled to said switch control and said memory cells for reading a single bit per cell when said switch control indicates selection of said standard cell mode, and for reading multiple bits of data per memory cell when said switch control indicates selection of said multi-level cell mode; anda program circuit coupled to said switch control and said memory cells for programming a single bit of data per memory cell when said switch control indicates selection of said standard cell mode, and for programming multiple bits of data per memory cell when said switch control indicates selection of said multi-level cell mode, wherein said program circuit comprises a program aligner coupled to said memory cells and said switch control for selectively programming a first set of memory cells to accommodate storing multiple bits per cell when said switch control indicates selection of said multi-level cell mode, and for selectively programming a second set of addressed memory cells when said switch control indicates selection of said standard cell mode.