Patent ID: 6101230
Filing Date: 2000-08-08
Classification: H04L

Abstract:
A sample clock signal recovery device for recovering a sampling clock signal in a receiving terminal of a discrete multitone (DMT) system, the sample clock signal recovery device comprising:an analog-to-digital converter for converting a transmitted analog signal, loaded on a multicarrier, into a digital signal;a fast Fourier transformer for fast Fourier transforming the digital signal and outputting a resultant signal;a frequency-domain equalizer for adjusting the resultant signal by a delay time associated with transmission of the transmitted analog signal and outputting a signal;a phase detector for detecting a phase error in a signal from the frequency-domain equalizer and for calculating a plurality of decision error values;an average value calculator for calculating an average value of a selected number of the plurality of decision error values;a determining means for determining whether the phase error is less than a predetermined threshold value; anda selector means responsive to the determining means for selectively outputting either the phase error, or the average value, in order to recover the sampling clock signal.