Patent ID: 8283957
Filing Date: 2012-10-09
Classification: H03L

Abstract:
1. A phase-locked loop circuit comprising: a reference signal source configured to generate a reference signal having cycles; a voltage-controlled oscillator configured to generate a first signal and a second signal having a phase reverse to that of the first signal, frequencies of the first signal and the second signal being controlled depending on control voltages; a sub-sampling phase comparator configured to generate a first sampled voltage and a second sampled voltage by sampling voltages of the first signal and the second signal in each cycle of the reference signal; a current generating circuit having a first charge pump configured to generate a first current signal depending on a supply voltage and a second charge pump configured to generate a second current signal having a polarity reverse to that of the first current signal depending on a supply voltage, and configured to generate a composite current signal of the first current signal and the second current signal; a selection controller configured to selectively carry out a first supply mode for supplying the first and second sampled voltages to the second and first charge pumps respectively and a second supply mode for supplying the first and second sampled voltages to the first and second charge pumps respectively; and a loop filter configured to generate the control voltages supplied to the voltage-controlled oscillator by smoothing the composite current signal.