Patent ID: 6897506
Filing Date: 2005-05-24
Classification: H01L

Abstract:
1. A non-volatile memory system, comprising: a transistor having a source and a drain, the transistor formed from a short-range atomic order substrate, the source and drain configured to alternately receive a first bias voltage creating a potential difference between the source and the drain; a dielectric for storing charge; and a non-floating gate positioned adjacent to the dielectric and configured to receive a threshold bias voltage to enable movement of the charge between the source and the drain and the dielectric, wherein the transistor, the dielectric, and the non-floating gate comprise a first row, and further comprising a second row positioned adjacent to the first row, the second row comprising a second transistor that includes a second source and a second drain, the second transistor formed from a second short-range atomic order substrate, a second dielectric for storing charge, a second non-floating gate on the second dielectric for receiving a threshold bias voltage to enable movement of the charge between the second source and the second drain and the second dielectric, wherein the second source and the second drain of the second row are separated from the non-floating sate of the first row by an isolation layer.