Patent ID: 6391726
Filing Date: 2002-05-21
Classification: H01L,Y10S

Abstract:
A method of fabricating integrated circuitry comprising:forming a pair of transistor gates having respective opposing sidewalls over a semiconductor substrate, one sidewall of one of the transistor gates facing one sidewall of the other transistor gate; depositing an insulating layer over the substrate and between the pair of transistor gates to fill an area extending therebetween; etching a contact opening into the insulating layer to proximate the substrate between the pair of transistor gates, the contact opening in at least one cross section spanning entirely between the pair of transistor gates; depositing an insulating spacer forming layer within the contact opening to less than completely fill the contact opening; and anisotropically etching the spacer forming layer to form a pair of insulating sidewall spacers over the one sidewalls of the pair of transistor gates.