Patent ID: 6384674
Filing Date: 2002-05-07
Classification: G11C,H02J

Abstract:
A semiconductor device comprising:a first main power supply line supplied with a first power supply potential; a second main power supply line supplied with a second power supply potential lower than said first power supply potential; a first sub power supply line provided in correspondence to said first main power supply line; a second sub power supply line provided in correspondence to said second main power supply line; a first internal circuit having first and second power supply nodes connected to said first and second sub power supply lines, respectively, for receiving at least one input signal and performing a prescribed operation; a first connection circuit connecting said first main power supply line and said first sub power supply line with each other in an operating mode and separating said first main power supply line and said first sub power supply line from each other in a standby mode; a second connection circuit connecting said second main power supply line and said second sub power supply line with each other in said operating mode and separating said second main power supply line and said second sub power supply line from each other in said standby mode; a power supply noise reduction circuit connected to said first and second main power supply lines and said first and second sub power supply lines, said power supply noise reduction circuit including: a first capacitor connected between said first main power supply line and said second sub power supply line, and a second capacitor connected between said first sub power supply line and said second main power supply line; and a first signal line transmitting a first control signal, wherein said first connection circuit includes: a first P-channel MOS transistor connected between said first main power supply line and said first sub power supply line with a gate receiving said first control signal of which a logical level is inverted in response to switching between said operating mode and said standby mode, a second P-channel MOS transistor having a source connected to said first main power supply line, and a first switching circuit selectively connecting a drain of said second P-channel MOS transistor to either one of said first main power supply line and said first sub power supply line, and a second switching circuit selectively connecting a gate of said second P-channel MOS transistor to either one of said second sub power supply line and said first signal line and said first signal line.