Patent ID: 6043537
Filing Date: 2000-03-28
Classification: H01L

Abstract:
An embedded memory logic device comprising:a semiconductor substrate including first and second regions;a first gate electrode formed on the first region;a first drain region formed in the semiconductor substrate on one side of said first gate electrode, and doped with a first impurity;a first source region formed in the semiconductor substrate on the other side of said first gate electrode, and doped with a second impurity;a second gate electrode formed on said second region of said semiconductor substrate;second source/drain regions formed in the semiconductor substrate on both sides of said second gate electrode, and doped with a third impurity;a third gate electrode formed on said second region of said semiconductor substrate;third source/drain regions formed in the semiconductor substrate on both sides of said third gate electrode, and doped with a fourth impurity;silicide layers formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions; andan insulating layer formed only over the first source region.