Patent ID: 7109766
Filing Date: 2006-09-19
Classification: H03K,H03L

Abstract:
1. A delay-locked loop (DLL) comprising: an adjustable frequency source for generating a clock signal having a frequency that can be adjusted to one of at least two different frequencies; an adjustment and tap selection controller for determining a first frequency as a function of a second frequency and for causing said frequency source to adjust the frequency of said clock signal to substantially said first frequency, said second frequency being the desired frequency of a first output signal; a delay line configured to receive the clock signal for generating a plurality of phase-shifted clock signals, each phase-shifted clock signal having substantially said first frequency and being shifted in phase with respect to the clock signal and with respect to the other phase-shifted clock signals; and a first selection circuit for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating said first output signal having substantially said second frequency.