Patent ID: 8658543
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit, comprising: providing a semiconductor substrate configured for forming an integrated circuit comprising a p-type field effect transistor (pFET), the semiconductor substrate having formed thereon a shallow trench isolation feature dividing a first semiconductive region from a second semiconductive region, the first semiconductive region configured for the formation of the pFET transistor thereon and the second semiconductive region configured for the formation of an nFET transistor thereon, the first semiconductive region comprising an active surface and a native oxide layer formed over the active surface, and the second semiconductive region comprising an active surface and an oxide masking layer formed over the active surface, wherein the active surface of the first semiconductive region is substantially parallel to the active surface of the second semiconductive region, and wherein the masking layer extends to a height above the active surface of the second semiconductive region that is higher than a height above the active surface of the first semiconductive region to which the native oxide layer extends; applying a hydrogen fluoride etching solution to the first and second semiconductive regions of the semiconductor substrate comprising removing the native oxide layer from the first semiconductive region, exposing the active surface of the first semiconductive region, and reducing the height of the oxide masking layer over the second semiconductive region; applying an APM etching solution to the first and second semiconductive regions of the semiconductor substrate comprising recessing the active surface of the first semiconductive region configured for the formation of the pFET transistor thereon, wherein the APM etching solution comprises an ammonia-hydrogen peroxide-water solution which, when applied to the first semiconductive region forms a recessed pFET surface region and which, when applied to the second semiconductive region does not etch the oxide masking layer, wherein the APM etching solution is defined by the formula “1:x:y”, wherein the number “1” represents a molar ratio of ammonia in the APM etching solution, wherein the letter “x” represents a molar ratio of hydrogen peroxide in the APM etching solution, wherein the letter “y” represents a molar ratio of water in the APM etching solution, wherein “x” is from about 1 to about 10, and wherein “y” is from about 2 to about 20; wherein applying the APM etching solution comprises applying the APM etching solution at a temperature of about 40° C. to about 80° C. and for a time period of about 5 minutes to about 60 minutes; wherein applying the APM etching solution comprises applying the APM etching solution comprising recessing the active surface of the first semiconductive region to a depth of about 2 nm to about 20 nm to form the recessed pFET surface region; and depositing by epitaxial growth a silicon-based SiGe material in the first semiconductive region to form a channel region on the recessed pFET surface region; wherein depositing the silicon-based material comprises depositing the silicon-based material to a height that is approximately parallel with the active surface of the second semiconductive region.