Patent ID: 6765515
Filing Date: 2004-07-20
Classification: H03M,H04N

Abstract:
An arithmetic coding/decoding apparatus of the MQ-CODER system comprising renormalization means for performing renormalization processing in coding and renormalization processing is decoding based on the MQ-CODER system with reference to the values of an augend register A, a code register C and a free byte counter CT,the renormalization means comprising: a number-of-shift calculation step of calculating the number of times of shift in the case where left shift of the value of the augend register A by 1 bit is performed until MSB reaches 1, and outputting the number of times as the number of shifts SHIFT_A; a first left bit shift step of performing left shift of the value of the augend register A by bits of the value indicated by the number of shifts SHIFT_A; a subtraction step of subtracting the value of the free byte counter CT from the number of shifts SHIFT_A; a byteout/bytein step of performing byteout processing in the case where the result of subtraction of the subtraction step is not negative at the time of coding, and performing bytein processing in the case where the result of subtraction of the subtraction step is not negative at the time of decoding and in the case where the value of the free byte counter CT is not 0 and the value of the free byte counter CT and the number of shifts SHIFT_A are the same value and normalization is carried out, at the time of decoding; a second left bit shift step of performing left shift of the code register C by bits of the value indicated by the free byte counter CT in the case where byteout processing or bytein processing is performed at the byteout/bytein step, and performing left shift of the code register C by bits of the value indicated by the number of shifts SHIFT_A in the case where byteout processing or bytein processing is not performed at the byteout/bytein step; a CT value selection step of setting the absolute value of the result of subtraction of the subtraction step as the value of the free byte counter CT in the case where byteout processing or bytein processing is not performed at the byteout/bytein step, and setting the value of the free byte counter CT at 0 in the case where byteout processing or bytein processing is performed at the byteout/bytein step; and a number-of-remaining-loop selection step of setting the value of the number of shifts SHIFT_A at 0 in the case where byteout processing or bytein processing is not performed at the byteout/bytein step, and setting the absolute value of the result of subtraction of the subtraction step as the number of shifts SHIFT_A in the case where byteout processing or bytein processing is performed at the byteout/bytein step, wherein the renormalization means ends the processing if the value of the number of shifts SHIFT_A outputted from the number-of-remaining-loop selection step is 0, and repeats the processing from the subtraction step if the value of the number of shifts SHIFT_A is not 0.