Patent ID: 7152176
Filing Date: 2006-12-19
Classification: G01R,H03L,H04L

Abstract:
1. A method of resynchronizing a clock signal to a data stream comprising: receiving said clock signal by a first delay line, said clock signal having a frequency equivalent to one-half a frequency of said data stream; receiving said clock signal by a second delay line; generating a first delayed clock signal from said first delay line using a first control signal, said first control signal effecting a first delay such that said first delayed clock signal is characterized by a level transition aligned approximately at a midpoint of a valid data period of said data stream; generating a second delayed clock signal from said second delay line using a second control signal, said second control signal used to effect a second delay to said second delayed clock signal; clocking said data stream using a first pair of first digital logic devices to generate a first data sequence, said clocking performed using said first delayed clock signal; clocking said data stream using a second pair of first digital logic devices to generate a second data sequence, said clocking performed using said second delayed clock signal; generating an output based on said first data sequence and said second data sequence; clocking said output using a second digital logic device to generate an indicator, said clocking performed by said first delayed clock signal; and evaluating said indicator.