Patent ID: 8120955
Filing Date: 2012-02-21
Classification: G11C,H03K

Abstract:
1. In a non-volatile memory array including a plurality of push-pull memory cells, each memory cell having a unique pair of transistors including an n-channel non-volatile pull-down transistor having a source coupled to ground, a control gate and a drain, and a p-channel volatile pull-up transistor having a drain directly connected to the drain of the n-channel non-volatile pull-down transistor, a control gate and a source, the array arranged in rows and columns, the array including a non-volatile transistor row line associated with each row of the array, each non-volatile transistor row line coupled to the control gates of each n-channel non-volatile pull-down transistor in the row with which it is associated, a volatile transistor row line associated with each row of the array, each volatile transistor row line coupled to the control gates of each p-channel volatile pull-up transistor in the row with which it is associated, and a column line associated with each column in the array, each column line coupled to the source of each p-channel volatile pull-up transistor in the column with which it is associated, a method for programming and reading cells in the array, comprising: controlling the voltages on the individual column lines; controlling the voltage on the individual non-volatile transistor row lines; and controlling the voltages on the individual volatile transistor row lines.