Patent ID: 7602223
Filing Date: 2009-10-13
Classification: H03L

Abstract:
1. A delay-locked loop circuit comprising: a phase detector generating a detection signal by detecting a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling a level of a voltage signal VCON in response to the detection signal; a frequency detector detecting the frequency domain of the external clock signal; and a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal by means of the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal, wherein the voltage-controlled delay line operates by dividing the detected frequency domain into two or more frequency domains relative to reference frequencies, and wherein the multiplied clock signal is generated by multiplying the external clock signal an integer number of times and wherein the feedback clock signal is delayed from the plurality delay clock signals by a cycle period of the external clock signal, wherein the detection signal of the phase detector includes up and down signals, wherein the voltage-controlled delay line generates the plurality of delay clock signals using a plurality of delay cells, wherein the voltage-controlled delay line comprises 2m delay cells (m is a positive integer), sequentially generates 2m delay clock signals with predetermined delay times each through a respective one of the plurality of delay cells, and determines to generate the multiplied clock signal by means of m delay clock signals or 2m delay clock signals, according to a delayed sequence, in response to a selection signal, wherein the m delay clock signals are used when the external clock signal has a high frequency, and 2m delay clock signals are used when the external clock signal has a low frequency, as determined by the frequency detector, wherein the voltage-controlled delay line comprises: a first multiplied clock generator operating to generate a first multiplied clock signal by means of the m-numbered delay clock signals sequentially delayed from the external clock; a second multiplied clock generator operating to generate a second multiplied clock signal by means of the 2m-numbered delay clock signals; and a multiplied clock selector operating to select one of the first and second multiplied clock signals in response to the selection signal.