Patent ID: 7300853
Filing Date: 2007-11-27
Classification: H01L

Abstract:
1. A process for manufacturing a semiconductor structure comprising providing a first substrate and a second substrate, the first substrate comprising a semiconductor surface layer, manufacturing layers comprising the manufacturing of a first layer providing thermal conductivity on the semiconductor surface layer or on the second substrate and the manufacturing of a second layer of an electric insulating material of low dielectric constant on the semiconductor surface layer or on the second substrate such that if the first substrate is bonded to the second substrate, the layers are sandwiched between the semiconductor surface layer and the second substrate with the first layer closer to the first substrate than the second layer, the said layers providing an intermediate zone, bonding the first substrate to the second substrate such that the layers are sandwiched between the semiconductor surface layer and the second substrate with the first layer closer to the first substrate than the second layer, reducing the thickness of the first substrate to provide the semiconductor surface layer of the semiconductor structure, wherein the intermediate zone electrically insulates the semiconductor surface layer from the second substrate and the second layer of the intermediate zone provides bonding by molecular adhesion between the intermediate zone and the second substrate.