Patent ID: 6525414
Filing Date: 2003-02-25
Classification: H01L,H05K

Abstract:
A semiconductor device comprising:a first multi-layer wiring board having a first side and a second side, and including a plurality of insulation layers and a plurality of circuit pattern layers alternately laminated with said insulation layers, one of said circuit pattern layers being formed on a first side and a second side of each of said insulation layers, each of said insulation layers having a plurality of inner via holes extending between said first side and said second side of each of said insulation layers and electrically connecting said circuit pattern layers so as to form a three-dimensional wiring pattern; a first semiconductor element including electrodes and being mounted on said first side of said first multi-layer wiring board; a second semiconductor element including electrodes and having a front surface and a back surface, said front surface of said second semiconductor element being mounted on said second side of said first multi-layer wiring board opposite said first semiconductor element such that said electrodes of said second semiconductor element and said electrodes of said first semiconductor element are electrically connected by said three-dimensional wiring pattern of said first multi-layer wiring board; and a second multi-layer wiring board mounted on said back surface of said second semiconductor element opposite said first multi-layer wiring board, said first multi-layer wiring board being bent toward said second multi-layer wiring board so as to be electrically connected to said second multi-layer wiring board.