Patent ID: 6636441
Filing Date: 2003-10-21
Classification: G11C

Abstract:
A semiconductor memory device comprising:a semiconductor substrate of a first conductive type; a first well region of a second conductive type formed on the semiconductor substrate; a second well region of a first conductive type formed in the first well region; a third well region of a first conductive type formed in the first well region; a memory cell array which is formed in each of the second well region and the third well region and which has a plurality of memory cells with a MOS structure; a first decoding circuit for selectively supplying a rewriting voltage signal to at least one of the second and third well regions and a corresponding source region of the memory cell at the time of rewriting data of the memory cell array; and a second decoding circuit configured to decode address signals supplied to the semiconductor memory device for selectively supplying the rewriting voltage signal to the first well region.