Patent ID: 6675338
Filing Date: 2004-01-06
Classification: G01R,G06F

Abstract:
A microchip test design for internally generating test vectors during a burnin test including:a Test Access Port (TAP) controller having a first input, a second input, and an output; a Linear Feedback Shift Register (LFSR) having an input and an output, said input of said LFSR coupled to said output of said TAP controller, wherein said LFSR further includes an XOR gate having five inputs and an output, an output on each of a last, second-to-last, third-to-last, twenty-second-to-last, and first LFSR flip-flops coupled to an input of said XOR gate, said output of said XOR gate coupled to an input of said first LFSR flip-flop; one or more flip flops organized in an internal scan chain, a first of said one or more flip-flops having an input coupled to said output of said LPSR, a last of said one or more flip-flops having an output coupled to said second input of said TAP controller; and said TAP controller further including a test data output (TDO).