Patent ID: 6828637
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A NOR flash memory device comprising:a semiconductor substrate having a main memory cell array region and a dummy cell array region surrounding the main memory cell array region; a plurality of parallel main active regions arranged at the substrate in the main memory cell array region, the main active regions extending along the substrate through the dummy cell array region; a dummy active region coupled to ends of the main active regions, the dummy active region crossing the main active regions; a plurality of common source lines crossing over the main active regions in the main memory cell array region; plural parallel wordlines intervened between the common source lines; at least one dummy wordline crossing over the main active regions in the dummy cell array region; and a plurality of parallel bitlines electrically connected to the main active region between the plural wordlines, wherein the plurality of the bitlines cross over the common source lines, the wordlines, and the at least one dummy wordline.