Patent ID: 6094083
Filing Date: 2000-07-25
Classification: H03K

Abstract:
A voltage converting buffer circuit comprising:an inverter section, connected between a first source line and a second source line, for receiving an input data signal to output an inverted data signal;a flip-flop latch circuit having first and second branches both connected between a third source line and the second source line so as to implement a flip-flop function between said first branch and said second branch, each of said branches including a p-channel transistor and an n-channel transistor, said first and second branches receiving the input data signal and the inverted data signal, respectively, to output a level shifted data signal from a first node connecting said p-channel transistor and said n-channel transistor in said second branch; anda delayed driving section including first and second pull transistors connected between said second source line or said third source line and said first node, each of said first and second pull transistors having a conductivity same as a conductivity of one of said p-channel transistor and said n-channel transistor having a smaller driving capability compared to the other in each of said first and second branches, said first pull transistor having a gate for receiving an output from a second node connecting said p-channel transistor and said n-channel transistor in said first branch, and a delay block for receiving an output from said first node to deliver a delayed output to a gate of said second pull transistor.