Patent ID: 7944239
Filing Date: 2011-05-17
Classification: G06F

Abstract:
1. An integrated circuit comprising: a first port configured to be electrically coupled to a pad, the first port including a first connection, a second connection, and a third connection; a first resistor having a first terminal and a second terminal; a second resistor having a third terminal and a forth terminal; a voltage source configured to provided a first voltage; a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal; a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; a third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; a first NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal; an I/O pad comprising a plurality of connectors, the plurality of connectors including a ground connector, a voltage connector, and an I/O connector; a first control circuit providing a first control signal, the first control signal being associated with the I/O pad; a second control circuit providing a second control signal and a third control signal; wherein: