Patent ID: 8830993
Filing Date: 2014-09-09
Classification: H04L

Abstract:
1. A time-space switch, comprising: input circuitry comprising N links each receiving M timeslots; a two-dimensional matrix of a plurality of switching circuits, wherein the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner; output circuitry comprising N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix; and a Switch Link Protocol for link encoding over the input circuitry, the two-dimensional matrix, and the output circuitry; wherein the Switch Link Protocol comprises selectable forward error correction and a flexible number of timeslots; wherein the two-dimensional matrix is arranged in an architecture on a same integrated circuit layout; and wherein the architecture comprises: duplex serializer-deserializer links; a plurality of Memory Tiles interconnected therebetween; a Configuration Tile disposed to a first set of the Memory Tiles; and a Frame Input Engine and a Frame Output Engine interconnected to the plurality of Memory Tiles and the duplex serializer-deserializer links.