Patent ID: 7895460
Filing Date: 2011-02-22
Classification: G06F

Abstract:
1. A method comprising: providing an incrementally delayed clock signal to a plurality of serially connected processing elements, wherein the plurality of serially connected processing elements form an array having a forward path and a reverse path and wherein the processing elements have a forward processing time interval in the forward path and a reverse processing time interval in the reverse path; in response to receiving the incrementally delayed clock signal at an individual processing element, initiating the forward and reverse processing time intervals of the individual processing element; and terminating the forward processing time interval of the individual processing element based on when a subsequent adjacent processing element in the forward path receives the incrementally delayed clock signal and terminating the reverse processing time interval of the individual processing element based on when a subsequent adjacent processing element in the reverse path receives the incrementally delayed clock signal such that one of the forward processing time interval or the reverse processing time interval is greater than the other.