Patent ID: 7164296
Filing Date: 2007-01-16
Classification: G06F

Abstract:
1. A multiplexer circuit for selecting one of a first input signal and a second input signal as a first output signal based on a first input select signal, the multiplexer circuit comprising: a multiplexer having a first input terminal for receiving the first input signal and a second input terminal for receiving the second input signal, the multiplexer having a select input terminal receiving a second input select signal, the multiplexer providing a second output signal being the first input signal when the second input select signal has a first logical state and the second input signal when the second input select signal has a second, opposite logical state; a control circuit coupled to receive the second output signal and the first input select signal, the control circuit generating the second input select signal and an enable signal, wherein the transitions of the second input select signal and the transitions of the enable signal are synchronized to a first transition of the second output signal; and an enable buffer coupled to receive the second output signal and the enable signal, the enable buffer providing the second output signal as the first output signal when the enable signal is asserted and the enable buffer holding the first output signal at a first logical state when the enable signal is deasserted, wherein in response to a transition on the first input select signal, the enable signal is deasserted at a next first transition of the second output signal and in response to the enable signal being deasserted, the second input select signal transitions to the same logical state as the first input select signal, thereby causing the second output signal to switch from the currently selected input signal to the to-be-selected input signal, and the enable signal is asserted on a next first transition of the second output signal subsequent to the switching of second output signal to the to-be-selected input signal; and wherein the control circuit comprises: