Patent ID: 7908453
Filing Date: 2011-03-15
Classification: G06F

Abstract:
1. A semiconductor device having a circuit configuration dynamically reconfigurable for each clock in accordance with configuration information, comprising: a plurality of memories; a plurality of arithmetic devices each having a circuit configuration that is dynamically reconfigurable in accordance with the configuration information; a control circuit outputting a first configuration information and a second configuration information and controlling a configuration of the semiconductor device; a memory reconfiguring circuit connected to said plurality of memories and reconfiguring a memory area formed by said plurality of memories in accordance with the second configuration information; and a bus connected to the plurality of arithmetic devices and connected to a plurality of host memory ports connected to the memory reconfiguring circuit in accordance with said first configuration information, wherein said memory reconfiguring circuit dynamically changes an allocation of said memories to said host memory ports for each clock in accordance with the second configuration information.