Patent ID: 8410961
Filing Date: 2013-04-02
Classification: H03M

Abstract:
1. A semiconductor integrated circuit comprising a plurality of high-speed external terminals, a plurality of low-speed external terminals, a plurality of high-speed analog switches, a plurality of low-speed analog switches, and an A/D converter, wherein each terminal of the high-speed external terminals is connectable to an input terminal of the A/D converter via each switch of the high-speed analog switches, wherein each terminal of the low-speed external terminals is connectable to the input terminal of the A/D converter via each switch of the low-speed analog switches, wherein a plurality of input terminals of a plurality of low-speed digital input buffer circuits and a plurality of output terminals of a plurality of low-speed digital output buffer circuits are coupled to the low-speed external terminals, respectively, wherein a plurality of output terminals of any digital output buffer circuit is not coupled, but a plurality of input terminals of a plurality of high-speed digital input buffer circuits is coupled to the high-speed external terminals, and wherein between each of the terminals of the low-speed external terminals and each of the switches of the low-speed analog switches, a low-speed separating resistor set to resistance value higher than a resistance value between each of the terminals of the high-speed external terminals and each of the switches of the high-speed analog switches is coupled.