Patent ID: 7239187
Filing Date: 2007-07-03
Classification: G06F

Abstract:
1. A reset circuit supplied with a reset trigger signal output from a general-purpose input/output port of a processor to generate a reset output signal to output said reset output signal to other circuits inclusive of said processor, said reset circuit comprising: first mask means for masking said reset trigger signal, supplied thereto as an input, during the time which elapses after an external power-on reset signal indicating the current power supply state indicates power supply on until a clock stop detection signal indicating the operating state of clocks indicates for the first time that the clocks are operating normally; a reset extension circuit for detecting an edge of the reset trigger signal as entered from said first mask means when the reset trigger signal becomes asserted and for generating and outputting a signal which becomes asserted for a prescribed period of time as from said edge; initializing means for initializing said reset extension circuit in case said external power-on reset signal indicates power supply off, or in case said clock stop detection signal indicates that said clocks are stopped; second mask means for masking said reset trigger signal from said first mask means in case said clock stop detection signal indicates that the clocks are operating normally; and reset output signal generating means for setting said reset output signal to an asserted state in case one of said signal from said reset extension circuit and the reset trigger signal from said second mask means is in an asserted state.