Patent ID: 6492841
Filing Date: 2002-12-10
Classification: H03K

Abstract:
A combination NAND and flip-flop circuit comprising:a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate, the plurality of signals comprising signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal; a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit; a first transmission gate and a first inverter, the first transmission gate receiving the output of the NAND gate and the first inverter receiving the output of the first transmission gate; and wherein the pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as follows: when the scan-enable signal is equal to a logical one then (i) the first output signal and the second output signal are both equal to the scan-in signal; or (ii) the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal; and when the scan-enable signal is equal to a logical zero then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal.