Patent ID: 8542178
Filing Date: 2013-09-24
Classification: G09G

Abstract:
1. A display driving circuit, in which a gate driver including a plurality of shifter register stages for shifting and outputting an input signal is embedded, comprising: a first transistor whose drain terminal and gate terminal are connected in common to an output terminal of an (N−1)th or (N−2)th gate line; a second transistor whose drain terminal is connected with a source terminal of the first transistor to form a first node, and whose source terminal is connected to a VGL terminal; a first capacitor whose first electrode receives a clock signal and whose second electrode is connected to the first node; a third transistor whose gate terminal is connected to the first node, whose drain terminal receives an inverted signal of the clock signal, and whose source terminal is connected to an N-th gate line; a fourth transistor whose gate terminal is connected with a gate terminal of the second transistor to form a second node, whose drain terminal is connected to the N-th gate line, and whose source terminal is connected to the VGL terminal; a fifth transistor whose gate terminal and drain terminal are connected in common to a Vbias terminal, and whose source terminal is connected to the second node; a sixth transistor connected between the second node and the VGL terminal, and whose gate terminal is connected to the drain terminal of the first transistor; a second capacitor formed between the second node and the gate terminal of the sixth transistor; and a ninth transistor whose gate terminal is connected to the first node, whose drain terminal is connected to the second node, and whose source terminal is connected to an LVGL terminal having a lower voltage than the VGL terminal.