Patent ID: 6331999
Filing Date: 2001-12-18
Classification: H03L,H04J,H04L

Abstract:
A serial data transceiver formed upon a monolithic semiconductor substrate, said transceiver including a receiver comprising:a deserializer coupled to receive a serial data stream comprising data windows separated by data transition periods, wherein the serial data stream has sufficient timing information to recover a transmit clock signal therefrom, and wherein the deserializer is configured to sample the serial data stream within each data window dependent upon the duty cycle of a timing signal in order to recover data from the serial data stream, and wherein the deserializer comprises:a phase comparator coupled to receive the serial data stream and the transmit clock signal, wherein the phase comparator is configured to produce an a.c. error signal having a short term average value substantially proportional to the phase difference between the serial data stream and the transmit clock signal;a loop filter coupled to receive the a.c. error signal and configured to produce a filtered error signal which is substantially the short term average value of the a.c. error signal;a voltage-controlled oscillator (VCO) coupled to receive the filtered error signal and a control signal, wherein the VCO is configured to produce a clock signal, and wherein the frequency of the clock signal is dependent upon the filtered error signal and substantially equal to a number n times a frequency of the transmit clock signal, and wherein the VCO is configured to produce the timing signal, and wherein the duty cycle of the timing signal is dependent upon the value of the control signal; anda divide-by-n circuit coupled to receive the clock signal and configured to divide the frequency of the transmit clock signal by the number n to produce the transmit clock signal, wherein n is an integer greater than or equal to 1, whereinthe VCO comprises a ramp generator coupled to a Schmitt trigger circuit, and wherein the ramp generator produces an output voltage which alternately increases and decreases linearly with time, and wherein the Schmitt trigger circuit is configured to produce the clock signal and the timing signal in response to the ramp generator output voltage.