Patent ID: 6495432
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method of reducing a boron-penetrating effect in a MOS transistor, comprising the steps of:(a) providing a silicon substrate which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active area; (b) depositing a polysilicon layer on the silicon substrate; (c) doping boron ions (B+) into the polysilicon layer; (d) forming a gate photoresist with a predetermined gate pattern on the polysilicon layer; (e) etching the polysilicon not covered by the gate photoresist to form a polysilicon gate; (f) using the gate photoresist as a mask to dope boron difluoride ions (BF2+) into the silicon substrate; (g) removing the gate photoresist; and (h) performing a tempering procedure to form a shallow junction area of a source/drain region in the silicon substrate.