Patent ID: 7485578
Filing Date: 2009-02-03
Classification: H01L

Abstract:
1. A method comprising: forming a first metal layer over a substrate; forming an interlayer dielectric layer over the substrate including the first metal layer; forming a via hole in the interlayer dielectric layer exposing the first metal layer; forming a second metal layer in the via hole on sidewalls of the interlayer dielectric layer; forming spacers in the via hole and contacting at least a portion of the exposed first metal layer by etching back the second metal layer exposing a portion of the sidewalls of the interlayer dielectric layer; forming a third metal layer over the spacers and the exposed portion of the sidewalls of the interlayer dielectric layer and the exposed first metal layer; and forming a fourth metal layer by depositing a conductive metal over the third metal layer to fill the via hole.