Patent ID: 7667448
Filing Date: 2010-02-23
Classification: G05F

Abstract:
1. A reference voltage generation circuit, comprising: a current mirror circuit including a first current mirror MOS transistor provided along a first current path extending from a first node to a second node, and a second current mirror MOS transistor for conducting, through a second current path extending from the first node to the second node, a current being a multiple of that flowing through the first current path; and a reference current generation circuit including a first reference current MOS transistor or a first reference current diode provided along the first current path and a second reference current MOS transistor or a second reference current diode provided along the second current path, whereby each of currents flowing through the first and second current paths is a constant reference current according to a gate-source voltage difference occurring in the first and second reference current MOS transistors or an anode-cathode voltage difference occurring in the first and second reference current diodes, wherein: a source of at least one of the first and second current mirror MOS transistors and the first and second reference current MOS transistors is connected to the second node; a resistive load circuit including a load section MOS transistor whose source is connected to the second node and whose gate and drain are connected to each other, and a resistive element connected between the drain of the load section MOS transistor and a third node; and a reference voltage output stage for outputting a voltage at an output node as a reference voltage, including a first output stage MOS transistor and a second output stage MOS transistor, wherein the first output stage MOS transistor has a drain connected to the first node, a source connected to the output node, and a gate connected to the gate of the MOS transistor whose source is connected to the second node, and the second output stage MOS transistor has a source connected to the output node, a drain connected to the third node, and a gate connected to the gate of the load section MOS transistor.