Patent ID: 6636111
Filing Date: 2003-10-21
Classification: H03F

Abstract:
A circuit (200) to cancel an input bias current of a differential amplifier, the circuit (200) comprising:an input stage of the differential amplifier including first and second PNP transistors (Q21 and Q22), the collector of the first PNP transistor (Q21) coupled to a first electronic load (240), the collector of the second PNP transistor (Q22) coupled to a second electronic load (250), and the first and second electronic loads (240 and 250) coupled to a negative supply rail (230); a tail current circuit (272) coupled to a positive supply rail (220) and the emitters of the first and second PNP transistors (Q21 and Q22); a compensating current circuit (Q24) coupled to the tail current circuit (272) and the positive supply rail (220); a third PNP transistor (Q25), the emitter of the third PNP transistor (Q25) coupled to the compensating current circuit (Q24), and the collector of the third PNP transistor (Q25) coupled to the negative supply rail (230); a first diode-connected NPN transistor (Q26), the collector of the first diode-connected NPN transistor (Q26) coupled to the base of the third PNP transistor (Q25); a first NPN transistor (Q27), the base of the first NPN transistor (Q27) coupled to the base of the first diode-connected NPN transistor (Q26), the emitter of the first NPN transistor (Q27) coupled to the emitter of the first diode-connected NPN transistor (Q26), and the collector of the first NPN transistor (Q27) coupled to the base of the second PNP transistor (Q22); a second NPN transistor (Q28), the bases of the second and first NPN transistors (Q28 and Q27) coupled to each other, the collector of the second NPN transistor (Q28) coupled to the base of the first PNP transistor (Q21), and the emitters of the second and first NPN transistors (Q28 and Q27) coupled to each other; and a bootstrap circuit (295) coupled to the emitters of the first and second PNP transistors (Q21 and Q22), the tail current circuit (272), the emitters of the first and second NPN transistors (Q27 and Q28) and the emitter of the first diode-connected NPN transistor (Q26); wherein the tail current circuit (272) generates a tail current for the first and second PNP transistors (Q21 and Q22); wherein the compensating current circuit (Q24) supplies a current such that the third PNP transistor (Q25) has a base current proportional to the input bias current; wherein the third PNP transistor (Q25) supplies the first diode-connected NPN transistor (Q26) with an input bias cancellation current; wherein the first and second NPN transistors (Q27 and Q28) supply the bases of the second and first PNP transistors (Q22 and Q21) with the input bias cancellation current respectively; wherein the bootstrap circuit (295) senses the emitters of the first and second PNP transistors (Q21 and Q22) and provides a bias to the first diode-connected NPN transistor (Q26); and wherein the circuit (200) can cancel the input bias current for common-mode voltages ranging up to within 0.2 direct current voltage (VDC) of the negative supply rail (230) voltage.