Patent ID: 7095655
Filing Date: 2006-08-22
Classification: G11C

Abstract:
1. A method for operating a non-volatile memory cell device, the method comprising: providing an array of memory array cells connected to word lines and local bit lines, said local bit lines being connected to global bit lines via select transistors, said array being divided into isolated sectors; providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX (Y multiplexer); providing a reference cell located in a reference mini-array, said reference cell being connected to said YMUX and being connected to said sense amplifier via another sensing path; driving both the memory array cells and the reference cell with a common bit line (BL) driver connected to the memory array cells and the reference cells via said YMUX through accessed global bit lines; and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier.