Patent ID: 7764758
Filing Date: 2010-07-27
Classification: H03L,H04L

Abstract:
1. An apparatus comprising: a first circuit configured to generate a phase signal having a sequence of phase values that form an oscillating waveform, wherein said phase values (i) have a change rate that matches a frequency of an input clock and (ii) convey a plurality of respective phase positions in each cycle of an output clock; a second circuit configured to (i) generate a sampled data signal by sampling an input data signal with said input clock and (ii) generate an intermediate data signal by interpolating said sampled data signal in response to respective pairs of said phase values, wherein said input data signal comprises an analog signal; and a third circuit configured to generate an output data signal by sampling said intermediate data signal with said output clock, wherein said first circuit comprises a phase detector configured to generate an error signal by detecting a phase error between said output clock and said phase signal.