Patent ID: 6018178
Filing Date: 2000-01-25
Classification: H01L

Abstract:
A non-volatile, EEPROM structure, on a semiconductor substrate, comprising:a control gate structure, on an underlying gate oxide layer, in the center of an EEPROM cell, comprised of a composite insulator layer on a polysilicon layer;silicon oxide spacers on the sides of said control gate structure;polysilicon, floating gate spacer structures, on the sides of said silicon oxide spacers, overlying a thin tunnel insulator layer;insulator gate spacers on the sides of said floating gate spacer structures;two, select gate structures, on an underlying gate oxide layer, comprised of a composite insulator layer on a polysilicon layer, located on each side of said control gate structure, resulting in said control gate structure being located between said select gate structures;insulator gate spacers on the sides of said select gate structures;two, N type source and drain node regions, in said semiconductor substrate, each located between a polysilicon floating gate structure, and a select gate structure; andtwo, N type bit line regions, in said semiconductor substrate, each located butting the outside shape of said select gate structure.