Patent ID: 8004929
Filing Date: 2011-08-23
Classification: G11C

Abstract:
1. A semiconductor device, comprising: terminals supplied selectively with an address signal or a mode signal; an address latch circuit coupled, when selected, to the terminals to latch the address signal; and a mode latch circuit coupled, when selected, to the terminals to latch the mode signal, wherein the terminals are supplied with the address signal when the semiconductor device is in a first mode, the terminals being supplied with the mode signal when the semiconductor device is in a second mode, the address latch circuit latching the address signal in the first mode, and the mode latch circuit latching the mode signal in the second mode, and wherein the address signal is latched in synchronization with an internal clock signal in the first mode, the internal clock signal being generated by causing a first delay in an external clock signal, and an amount of the first delay being controlled by the mode signal.