Patent ID: 6893918
Filing Date: 2005-05-17
Classification: H01L

Abstract:
1. A method of fabricating a flash memory, comprising the steps of: providing a substrate having a tunneling dielectric layer and a patterned mask layer sequentially formed thereon; removing portions of the tunneling dielectric layer and the substrate using the patterned mask layer as an etching mask to form a plurality of trenches in the substrate; depositing an insulating material into the trenches to form a plurality of device isolation structures; forming a sacrificial material layer over the substrate, covering the patterned mask layer and the isolation structure; patterning the sacrificial material layer for forming a plurality of sacrificial layers on the isolation structures; removing the patterned mask layer for exposing the tunneling dielectric layer; forming a first conductive layer over the substrate; removing a portion of the first conductive layer to expose top sections of the sacrificial layers to form a plurality of floating gates; removing the sacrificial layers; forming a inter-gate dielectric layer over the substrate, covering the floating gate; forming a control gate over the inter-gate dielectric layer; and forming a source region and a drain region in the substrate on each side of the control gate.