Patent ID: 9105301
Filing Date: 2015-08-11
Classification: G11B,H03M

Abstract:
1. A signal processing apparatus to receive an input signal and to output a first processing result, the signal processing apparatus comprising: a Viterbi decoder configured to calculate a branch metric based on the input signal and a first parameter; a processor comprising at least one of an automatic gain control circuit, a phase locked loop, and an asymmetry correction circuit and configured to output a second processing result based on the input signal, the input signal being supplied to the Viterbi decoder through the processor, and the second processing result being correlated with the first processing result, wherein a latency of the processor is lower than a latency of the Viterbi decoder; and an adjuster configured to adjust the first parameter for the Viterbi decoder based on the second processing result and to supply the adjusted first parameter to the Viterbi decoder, wherein the second processing result comprises at least one of: the adjuster is further configured to adjust the first parameter for data sectors comprising encoded data, adjust a second parameter for calculating the branch metric before the branch metric is calculated for a first data sector of the data sectors, and adjust the first parameter for the first data sector based on the second processing result.