Patent ID: 9123825
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising: providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer; exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer; etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions; depositing a first dielectric material over the semiconductor substrate and into the extended parallel linear void regions to fill the extended parallel linear void regions with the first dielectric material; depositing and patterning a photoresist material over the semiconductor substrate to cover a plurality of regions of the semiconductor substrate, the plurality of regions defining active regions of the integrated circuit; etching portions of the pad layer, the first dielectric material, and the semiconductor substrate not covered by the photoresist material to form further void regions; depositing a second dielectric material into the further void regions to fill the further void regions; and removing the pad layer to expose the semiconductor substrate outside of the filled further void regions.