Patent ID: 6018815
Filing Date: 2000-01-25
Classification: G01R

Abstract:
An integrated circuit comprising:a plurality of function blocks; anda configurable scan chain circuitry for testing said plurality of function blocks such that:in a first test mode, said configurable scan chain circuitry provides a plurality of scan chains, wherein each scan chain is for scanning data in and/or out of corresponding one or more of said plurality of function blocks, such that in a testing operation any of said scan chains is operable to be selected and scanned without any other one of said scan chains being scanned and said integrated circuit is operable to be tested without any other one of said scan chains being scanned;in a second test mode, said configurable scan chain circuitry provides a plurality of scan chains, wherein each scan chain is for scanning data in and/or out of corresponding one or more of said plurality of function blocks such that in a testing operation all of said scan chains for all of said function blocks are scanned in parallel.