Patent ID: 7189619
Filing Date: 2007-03-13
Classification: H01L

Abstract:
1. A method for producing vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which includes an insulating layer, on which a first active semiconductor region having a first thickness in a layer of active semiconductor material is arranged, and a second active semiconductor region that has a smaller thickness than the first active semiconductor regions, the second active semiconductor region being formed by the following steps: partially or completely covering the SOI wafer with a protective layer; providing, in covered regions, a trench structure, which cuts through the protective layer and extends into a depth of the layer of the active semiconductor material; covering the trench structure with an oxide layer; defining a subregion of the trench structure by a lithography-masking step; providing at least one seed opening within the trench structure by anisotropic etching of the oxide layer within the defined subregion; filling the trench structure with selective epitaxial growth, proceeding from the seed opening of semiconductor material for the second active semiconductor areas; planarizing the resulting structure and reducing a thickness thereof until the second active semiconductor regions do not project beyond the walls of the trench structure; reopening the seed opening by a further lithography and masking etching step; and sealing the opened seed opening by an insulating intermediate layer, so that the second semiconductor regions are insulated laterally and vertically completely dielectrically from the first semiconductor regions.