Patent ID: 6452411
Filing Date: 2002-09-17
Classification: G01R

Abstract:
A test system comprising:a tester; a reference device; a communication channel communicatively interconnecting said tester and said reference device; interface circuitry communicatively coupled to said channel and a plurality of semiconductor devices; a state machine communicatively coupled to said interface circuitry, said state machine comprising: a monitor state in which said interface circuitry monitors said communication channel, a write state, said state machine entering said write state upon detecting a write operation by said tester of test data to said reference device on said communication channel, said interface circuitry writing said test data detected on said communication channel to each of said semiconductor devices while said state machine is in said write state, and a read state, said state machine entering said read state upon detecting a read operation by said tester of response data from said reference device, said interface circuitry reading said response data detected on said communication channel and reading corresponding response data from each of said plurality of semiconductor devices while said state machine is in said read state; and a comparator configured to compare said response data read from said reference device with said response data read from each of said semiconductor devices.