Patent ID: 8307233
Filing Date: 2012-11-06
Classification: G06F,Y02D

Abstract:
1. A data controller system configured to operate in active and sleep modes, said data controller system having interfaces to receive external signals over an external bus, said data controller system comprising: a) a core processor configured to operate alternatively in an active mode and in a sleep mode, wherein during said sleep mode at least a portion of said core processor is deactivated; b) a communications port operatively connected to said core processor and said external bus, wherein said communications port is alternatively operable to be in an active mode and a sleep mode; and c) a signal identifier unit connected to said external bus, and configured to continuously monitor for external signals on said external bus, wherein said signal identifier unit is operable to stall receipt of said external signals on said external bus at said communications port responsive to identifying external signals on said external bus when said communications port is in said sleep mode, said signal identifier unit being operable to wake said core processor, and said signal identifier unit being operable to wake said communications port into said active mode responsive to at least receipt of said external signals on said external bus.