Patent ID: 8304891
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A semiconductor package device, comprising: a silicon substrate having a first surface and an opposed second surface and a plurality of Through Silicon Vias; a semiconductor chip disposed on the first surface of the silicon substrate and electrically connected to the Through Silicon Vias; an encapsulant formed on the first surface of the silicon substrate to encapsulate the semiconductor chip, wherein the encapsulant is free from being formed on a side surface of the silicon substrate; a hard component disposed on the encapsulant and free from being electrically connected to the semiconductor chip and the silicon substrate, wherein the encapsulant is formed between the hard component and the semiconductor chip and is free from being formed on an outside surface of the hard component so as to expose the hard component; and a plurality of conductive elements disposed on the second surface of the silicon substrate and electrically connected to the Through Silicon Vias.