Patent ID: 6047386
Filing Date: 2000-04-04
Classification: G06F,G11C

Abstract:
In a microprocessor having an SRAM, the SRAM having scannable data lines, address lines, control lines and outputs, the control lines including a scan-enable signal and a write-enable signal, an apparatus for allowing a RAM array to be tested via scan ATPG, the apparatus comprising:means for scanning the address lines, the control lines, and data from the data lines into the RAM array when the scan-enable signal is high and the write-enable signal is low in response to a clock transition in a first direction;means for writing the data in the RAM array when the scan-enable signal is low and the write-enable signal is high in response to a clock transition in a second direction opposite to that of the first direction;means for forcing the write-enable signal low when the scan-enable signal is low in response to an assertion of a clock transition in the first direction;means for storing the data in the RAM array when the scan-enable signal is low response to an assertion of a clock transition in the second direction; andmeans for scanning the data out of the RAM array when the scan-enable signal is high and the write-enable signal is low in response to an assertion of a clock transition in the first direction.