Patent ID: 6885052
Filing Date: 2005-04-26
Classification: H01L

Abstract:
1. A semiconductor memory device having a plurality of self-aligned contacts comprising: a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, each gate electrode pattern comprising a mask and a gate; a plurality of first spacers formed along a plurality of sidewalls of the gate electrode patterns; a first interdielectric layer formed on an entire surface of a resultant in which the first spacers are formed; a plurality of bit line patterns arranged in parallel on the first interdielectric layer, perpendicular to the gate electrode patterns, each bit line pattern comprising a mask layer and a bit line; a plurality of contact plugs for bit lines, which are self-aligned with the first spacers, for electrically connecting at least two active regions of the semiconductor device formed around the surface of the semiconductor substrate, to the bit line patterns, wherein the contact plugs for bit lines are formed on a portion of the masks of adjacent gate electrode patterns; a plurality of second spacers formed along a plurality of sidewalls of the bit line patterns; a second interdielectric layer formed on an entire surface of a resultant in which the second spacers are formed; and a plurality of storage electrode contact plugs, formed as a single unit structure, aligned with the second and first spacers, for electrically connecting the active regions of the semiconductor device formed around the surface of the semiconductor substrate, to a plurality of storage electrodes of a capacitor, wherein the storage electrode contact plugs are projected to a predetermined height greater than a height of the bit line patterns, wherein the storage electrode contact plugs do not contact the contact plugs for bit lines.