Patent ID: 6448115
Filing Date: 2002-09-10
Classification: H01L,Y10S

Abstract:
A method for manufacturing a semiconductor device having an SOI structure comprising:forming a porous silicon pattern over a lower silicon substrate; forming an upper silicon pattern over the a porous silicon pattern; forming a hole in the upper silicon pattern and the porous silicon pattern to expose the lower silicon substrate; forming a reverse T-type hole and an undercut porous silicon pattern under the upper silicon pattern by partially etching the porous silicon pattern, the resulting undercut porous silicon pattern partially electrically contacting the lower silicon substrate and the upper silicon pattern; partially electrically isolating the lower silicon substrate from the upper silicon pattern by forming an isolating insulation layer in the reverse T-type hole; forming a gate insulation layer and a gate electrode over the upper silicon pattern; and forming source and drain regions in the upper silicon pattern.