Patent ID: 6275121
Filing Date: 2001-08-14
Classification: H01P

Abstract:
A microwave circuit for changing the phase of a microwave signal comprising:a first transmission route comprising a first transmission line having a first length and through which microwave signals may be transmitted, and first and second FET switch elements having respective first electrodes, second electrodes, and control electrodes, wherein the first electrode of the first FET switch element is connected to a first end of the first transmission line and the first electrode of the second FET switch element is connected to a second end of the first transmission line;a second transmission route comprising a second transmission line having a second electrical length, different from the first electrical length, and through which microwave signals may be transmitted, and third and fourth FET switch elements having respective first electrodes, second electrodes, and control electrodes, wherein the first electrode of the third FET switch element is connected to a first end of the second transmission line and the first electrode of the fourth FET switch element is connected to a second end of the second transmission line;an input terminal connected to the second electrodes of the first and third FET switch elements and an output terminal connected to the second electrodes of the second and fourth FET switch elements whereby the first and second transmission routes are connected in parallel;first, second, third, and fourth signal transmission lines for receiving control signals for selecting the first transmission route or the second transmission route for transmitting an input microwave signal; andfirst, second, third, and fourth signal waveform transforming circuits respectively connecting the first, second, third, and fourth signal transmission lines to the control electrodes of the first, second, third, and fourth FET switch elements, wherein each of the first, second, third, and fourth waveform transforming circuits includes respective first and second dividing circuits,each first dividing circuit having a first terminal connected to the control electrode of the corresponding first, second, third, and fourth FET switch element, a second terminal connected to the corresponding first, second, third, and fourth signal transmission lines, and a respective FET element having gate, source, and drain electrodes, each gate electrode of an FET element being directly connected to one of the source and drain electrodes of said corresponding FET element, andeach second dividing circuit including a first terminal connected to the control electrode of the corresponding first, second, third, and fourth FET switch element, and a second terminal connected to a constant voltage line.