Patent ID: 6081143
Filing Date: 2000-06-27
Classification: G06F

Abstract:
An integrated processor configured to receive a reference clock signal and an external clock signal and comprising:a processor core;a peripheral bus interface coupled to said processor core; anda clock circuit coupled to said processor core, wherein said processor core, peripheral bus interface, and clock circuit are formed on a single monolithic substrate;wherein said clock circuit is configured to compare a frequency of said reference clock signal to a frequency of said external clock signal and to output an internal clock signal, wherein said clock circuit is configured to generate said internal clock signal with a frequency equal to said frequency of said reference clock signal in response to detecting a first frequency relationship between said reference clock signal and said external clock signal, and wherein said clock circuit is configured to generate said internal clock signal with a frequency which is a multiple of said frequency of said reference clock signal in response to detecting a second frequency relationship between said reference clock signal and said external clock signal, wherein said multiple is not equal to one;wherein said clock circuit comprises a comparator circuit that compares said frequency of said reference clock signal to said frequency of said external clock signal and outputs a control signal indicative of whether said frequency of said reference clock signal equals said frequency of said external clock signal; and a phase-locked loop configured to receive said control signal of said comparator circuit and said reference clock signal and configured to output said internal clock signal.