Patent ID: 9071470
Filing Date: 2015-06-30
Classification: H04L

Abstract:
1. A tuner comprising: an analog front end block; an analog-to-digital converter responsive to the analog-front end block; a digital signal processor responsive to said analog-to-digital converter and adapted to output in-phase and quadrature data via a first terminal, wherein said digital signal processor is further configured to interleave the in-phase and quadrature data, said first terminal carrying a first subset of bits associated with the in-phase and quadrature data; a serial communication interface block receiving a first gain control signal via a second terminal, said serial communication interface block being further configured to supply the first gain control signal to the analog front end block when a switch is in a first position; a gain control block adapted to receive a second gain control signal from the analog-to-digital converter and to supply the second gain control signal to the analog front end block when the switch is in a second position; and a third terminal carrying a second subset of bits associated with the in-phase and quadrature signals, said first and second subsets representing an entire set of bits associated with the in-phase and quadrature data, wherein the first subset of bits associated with the in-phase and quadrature data is transmitted in a first data packet having a synchronization header, and the second subset of bits associated with the in-phase and quadrature data is transmitted in a second data packet, the first and second data packets sharing a same clock signal.