Patent ID: 6165815
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method of fabricating a multi-level stack of semiconductor substrate elements, each of said elements including integrated circuitry, comprising:providing a first semiconductor substrate wafer having a first side including integrated circuitry thereon and having a back side;providing at least one second semiconductor substrate wafer having a first side including a plurality of integrated circuits thereon and having a backside; andstacking said first semiconductor substrate wafer and said at least one second semiconductor substrate wafer in at least partially superimposed relationship having the back side of the first semiconductor substrate wafer facing the back side of the at least one second semiconductor substrate wafer; aligning vertically said first semiconductor substrate wafer and the at least one second semiconductor substrate wafer, thereby vertically aligning integrated circuitry on the first semiconductor substrate wafer and at least one of the plurality of integrated circuits on said at least one semiconductor substrate wafer; and severing from said stack traversely at least one dice pair comprising a die from said first semiconductor substrate wafer and an aligned die including at least one of said plurality of integrated circuits from said at least one second semiconductor substrate wafer.