Patent ID: 8461697
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a peripheral I/O region in which I/O cells are arranged; a gate region surrounded by the peripheral I/O region; a plurality of power area pads arranged in the gate region; and first and second power source lines, wherein: the plurality of power area pads are arranged in a matrix along a raw direction and a column direction, and include first power area pads connected to the first power source line and second power area pads connected to the second power source line, the gate region comprises a peripheral portion and a center portion, the peripheral portion being adjacent to the peripheral I/O region and the center portion being not adjacent to the peripheral I/O region, the plurality of power area pads in the peripheral portion is arranged such that the first power area pads and the second power area pads are alternately disposed in a direction of a boundary between the peripheral I/O region and the peripheral portion of the gate region, and the plurality of power area pads in the center portion include at least one row or column that includes either (i) only the first power area pads or (ii) only the second power area pads, as the power area pads.