Patent ID: 8129754
Filing Date: 2012-03-06
Classification: G06F,H01L

Abstract:
1. A method for creating a layout of an integrated circuit, comprising: operating a computer to define at least six linear conductive structure shapes in a gate electrode level region layout, the at least six linear conductive structure shapes each formed to extend lengthwise in a first direction, the at least six linear conductive structure shapes including— wherein the second linear conductive structure shape is substantially co-aligned with the third linear conductive structure shape along a common line of extent in the first direction, and wherein the second linear conductive structure shape is separated from the third linear conductive structure shape by a first line end spacing distance, wherein the fourth linear conductive structure shape is substantially co-aligned with the fifth linear conductive structure shape along another common line of extent in the first direction, and wherein the fourth linear conductive structure shape is separated from the fifth linear conductive structure shape by a second line end spacing distance, wherein the first, second, third, fourth, fifth, and sixth linear conductive structure shapes are defined such that the first, second, third, and fourth transistors of the first transistor type are separated from the first, second, third, and fourth transistors of the second transistor type by a non-active portion of a substrate region over which the gate electrode level region layout is to be fabricated, wherein a first end of the second linear-shaped conductive structure is positioned over the non-active portion of the substrate region, wherein a first end of the third linear-shaped conductive structure is positioned over the non-active portion of the substrate region, wherein a first end of the fourth linear-shaped conductive structure is positioned over the non-active portion of the substrate region, wherein a first end of the fifth linear-shaped conductive structure is positioned over the non-active portion of the substrate region, and wherein either the first ends of the second and fourth linear-shaped conductive structures are, offset from each other in the first direction, or the first ends of the third and fifth linear-shaped conductive structures are offset from each other in the first direction, or the first ends of the second and fourth linear-shaped conductive structures are offset from each other in the first direction and the first ends of the third and fifth linear-shaped conductive structures are offset from each other in the first direction.