Patent ID: 8418113
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A method of establishing global wiring connections for an integrated circuit design, comprising: receiving a description of the circuit design including pin locations and interconnections, by executing first instructions in a computer system; partitioning the circuit design into a plurality of global tiles having one or more global edges defined by boundaries between adjacent global tiles, each global edge having wiring tracks and a wiring track capacity, by executing second instructions in the computer system; computing pin information for a given global edge based on pins located within at least one tile associated with the given global edge, by executing third instructions in the computer system; reducing the wiring track capacity for the given global edge based on associated pin information to yield reduced wiring track capacities, by executing fourth instructions in the computer system; and routing global connections between tiles using the reduced wiring track capacities, by executing fifth instructions in the computer system.