Patent ID: 8482984
Filing Date: 2013-07-09
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a block including a plurality of memory cell units formed in a well, each memory cell unit including a plurality of electrically rewritable nonvolatile memory cells connected in series, a first select gate transistor coupled to a memory cell at one end of the memory cell unit and coupled to a bit line, and a second select gate transistor coupled to the memory cell at the other end of the memory cell unit, a first memory cell as one of the memory cells located at an end of the memory cell unit being used in a different way from the other memory cells; plural word lines each coupled to a corresponding one of the memory cells in the memory cell units; a first selection gate line coupled to the first select gate transistor; a second selection gate line coupled to the second select gate transistor; and a control circuit configured to control a block erase operation that erases data from all the memory cells in a memory cell unit, the block erase operation includes applying a first voltage to a word line of the first memory cell, applying a second voltage to word lines of the memory cells in the memory cell unit other than the first memory cell, and applying to the well an erase voltage greater than the first voltage and the second voltage.