Patent ID: 6339822
Filing Date: 2002-01-15
Classification: G06F

Abstract:
A microprocessor configured to cache basic blocks of instructions comprising:decoding logic coupled to receive and decode variable-length instructions into padded instructions that have one of a predetermined number of predetermined lengths, wherein said decoding logic is further configured to form basic blocks of instructions from said padded instructions; a basic block cache coupled to said decoding logic and comprising a plurality of cache lines, wherein each cache line is configured to store an address tag, a link bit, and at least a portion of one basic block, wherein said link bit indicates whether the basic block stored in said storage location extends into a different storage location; and a branch prediction unit coupled to said basic block cache and having a branch prediction array with a plurality of storage locations, wherein each storage location corresponds to a particular cache line within said basic block cache and stores branch prediction information corresponding to said particular cache line.