Patent ID: 6385700
Filing Date: 2002-05-07
Classification: G06F,Y02D

Abstract:
A cache-management method for a system including a processor, main memory, and a set-associative cache having plural sets of cache locations containing copies of data stored in said main memory, said method comprising the steps of:during a first request cycle in which said processor issues a first request to read first data from a first main-memory location, providing said first data to said processor from a first set of said plural sets; during a second request cycle in which said processor issues a second request to write second data to a second main-memory location, determining a second set of said plural sets in which said second main-memory location is represented; during a third request cycle in which said processor issues a third request to write third data to a third main-memory location, determining a third set of said plural sets in which said third main-memory location is represented, and writing said second data to said second set; and during a fourth request cycle in which said processor issues a fourth request to read fourth data from a fourth main-memory location, writing said third data to said third set and determining a fourth set of said plural sets in which said fourth main-memory location is represented; and during a fifth request cycle, providing said fourth data to said processor from said fourth set.