Patent ID: 7521811
Filing Date: 2009-04-21
Classification: H01L,H05K

Abstract:
1. A substrate for packaging a semiconductor chip, comprising: a dielectric layer; a plurality of conductive circuits formed on the dielectric layer; a plurality of bonding pads formed on the dielectric layer, the bonding pad having opposing first and second ends, the first end of the bonding pad extending from the conductive circuits; at least one thin metal deposition layer formed on the bonding pads and connected with the conductive circuits, wherein the thin metal deposition layer has at least one portion to protrude from the conductive circuits and the bonding pads so that the protruding portion of the thin metal deposition layer is not supported by the conductive circuits and the bonding pads; and a solder mask formed on the dielectric layer and the conductive circuits, wherein the bonding pad is exposed from the solder mask except that the second end of each bonding pad is covered by the solder mask to have the protruding portion of the thin metal deposition layer embedded in the solder mask.