Patent ID: 6459753
Filing Date: 2002-10-01
Classification: H03K,H03L

Abstract:
A device for generating a second signal (Fo) having a frequency equal to a frequency of a first signal (Fi) divided by a rational, non-integer number, which rational number is greater than one and, when written as a fraction, can only be written with a denominator not equal to one, characterized by means for supplying the first signal (Fi) to a first (a) of a number of delay elements (a, b, . . . , R) connected in series for the purpose of further delaying the first signal (Fi) per delay element each time by a time period equal to a period time of the first signal (Fi) divided by the denominator of the fraction of the rational number, and by a combinatorial circuit which comprises a counter (2) for counting pulses of the first signal (Fi), which counting takes place via a counting modulo of the rational number and in increments of the denominator of the rational number and results in counter scores which combinatorial circuit (6, 7, 9, 10, 11, 12, 13) comprises a decoder circuit (6) for decoding counter scores on the basis of an algorithm determined by the rational number, said decoded counter scores appearing as an output signal each time at one output (6a, . . . , 6e), determined by the counter score and the algorithm, of the decoder circuit (6), and which combinatorial circuit (6, 7, 8, 10, 11, 12, 13) comprises means (7, 8, 10, 11, 12, 13) for combining output signals of the number of delay elements determined by the algorithm with output signals of the decoder circuit so as to obtain the second signal (Fo).