Patent ID: 8107582
Filing Date: 2012-01-31
Classification: H03L

Abstract:
1. A circuit for recovering a clock signal, comprising: a phase frequency detector that is configured to provide a phase error signal based, at least in part, on a difference between a first clock signal and a feedback signal; a loop filter that is configured to provide a filtered signal based, at least in part, on scaling the phase error signal by a first scaling factor and on filtering the scaled phase error signal; a compressor that is configured to provide a clock generator control signal based, at least in part, on scaling the filtered signal by a second scaling factor; and a clock generator that is configured to generate an output clock signal based, at least in part, on the clock generator control signal, wherein the feedback signal is based, at least in part, on the output clock signal, wherein the loop filter is further configured to scale the phase error signal by multiplying the phase error signal with the first scaling factor, wherein the compressor is further configured to scale the filtered signal by dividing the filtered signal by the second scaling factor, wherein the first scaling factor and the second scaling factor are positive integers, and wherein the first scaling factor is equal to the second scaling factor.