Patent ID: 6103617
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A fabricating method of a multi-level wiring structure for a semiconductor device, comprising:sequentially forming a first insulating film, a first etching stop film, a second insulating film and a second etching stop film on a conductive layer pattern;forming a trench by etching the second etching stop film, the second insulating film and the first etching stop film;forming a photoresist film in the trench and on an upper surface of the second etching stop film, wherein a thickness of the photoresist film ranges between 1000-3000 .ANG.;exposing an upper surface of the first insulating film by forming an opening in the photoresist film formed in the trench;forming a via hole by etching the exposed portion of the first insulating film to thereby expose a portion of the conductive layer pattern; andfilling a conductive material in the via hole and the trench.