Patent ID: 6477088
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A method of erase of a nonvolatile memory structured from twin MONOS cells, comprising:a) biasing a first conductivity region on the first side of a channel region to a first positive voltage, b) biasing a second conductivity region on the second side of a channel region to a second positive voltage, c) biasing a first conductive gate to a first negative voltage, d) biasing a second conductive gate to said first negative voltage, e) biasing a third conductive gate coupled to a selected word line to zero volts or a second negative voltage, f) biasing said third conductive gate coupled to a unselected word line to a fourth positive voltage, g) creating an electric field in an insulator under said first conductive gate of memory cells coupled to the selected word line.