Patent ID: 8020020
Filing Date: 2011-09-13
Classification: G06F

Abstract:
1. A processor comprising: at least one processor time stamp counter (TSC) corresponding to a TSC that is defined to increment at a TSC clock frequency even though the processor is configurable to operate at one of a plurality of clock frequencies; a control unit coupled to the at least one processor TSC and configured to maintain the processor TSC, wherein the control unit is configured to update the processor TSC, wherein the processor is operating at a current clock frequency of the plurality of clock frequencies, and wherein the update comprises adding a value to the processor TSC, wherein the value is based on the ratio of the TSC clock frequency and the current clock frequency, and wherein the ratio comprises an integer portion and a fractional portion, and wherein the value comprises the integer portion and a carry from a running sum corresponding to the fractional portion.