Patent ID: 6137736
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A semiconductor memory device having a block selective line structure comprising a plurality of block selective common lines, each of which is commonly connected to both corresponding normal and redundant memory cell blocks in normal and redundant memory cell arrays,wherein said plurality of block selective common lines are connected to a block selective line selecting circuit, which is operated to select a first one of said plurality of block selective common lines when a non-defective normal memory cell belonging to said first one of said plurality of block selective common lines is selected in said normal memory cell array, and also which is operated to select a second one of said plurality of block selective common lines when a defective normal memory cell belonging to said second one of said plurality of block selective common lines is selected in said normal memory cell array,wherein said block selective line selecting circuit is switched into a first state to permit transmission of decoded normal row address signals having information designating a normal row address to which a normal memory cell to be selected belongs when said non-defective normal memory cell is selected, and also switched into a second state to permit transmission of decoded redundant row address signals having information designating a redundant row address to which a redundant memory cell to be selected belongs when said defective normal memory cell is selected.