Patent ID: 8233334
Filing Date: 2012-07-31
Classification: G11C

Abstract:
1. A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device, the circuit comprising: a first circuit having a first codec configured to generate a first internal command signal that maintains a high level in response to a first external input reset signal that is inputted to the semiconductor memory device after a power-on and a first delay circuit configured to receive and delay the first internal command signal and change the first internal command signal to a low level from the high level; a second circuit having a second codec configured to generate a second internal command signal that maintains a high level in response to the first internal command signal and a second delay circuit configured to receive and delay the first internal command signal and change the first internal command signal to a low level from the high level; a signal generation unit configured to generate an internal ready/busy signal when the first internal command signal and the second internal command signal have a low level; a CAM cell read circuit configured to start a read operation for reading a data stored in a CAM cell in response to the internal ready/busy signal.