Patent ID: 8847861
Filing Date: 2014-09-30
Classification: G09G

Abstract:
1. An active matrix EL display device comprising: a pixel portion which includes a plurality of pixels, a plurality of signal lines and a plurality of scan lines; a signal line driver circuit comprising a pulse output circuit, a first latch circuit, a second latch circuit, and an output control circuit which is electrically connected to the signal lines; and a scan line driver circuit which is electrically connected to the scan lines, a determination circuit configured to compare data of a first video signal input to pixels of a single row during a subframe period with data of a second video signal input to the pixels of the single row during a subsequent period to write video signals to the pixels; wherein each of the plurality of pixels includes an EL element, wherein the scan line driver circuit does not output a selecting pulse to select a pixel row to a scan line corresponding to the pixel row when a signal to be written to the pixel row is identical with a signal stored in the pixel row, wherein the output control circuit does not output a video signal held in the second latch circuit to the signal lines to make the signal lines in a floating state when a signal to be written to the pixel row is identical with a signal stored in the pixel row, wherein a frame period is divided into a plurality of subframe periods according to an overlapped time gray scale method, wherein the overlapped time gray scale method is a driving method expressing a gray scale by a difference in total time of light emitting time of each pixel by dividing one frame period into a plurality of subframe periods and controlling lighting and non-lighting of each pixel in each subframe period, wherein the overlapped time gray scale method is a driving method expressing a gray scale by sequentially adding the number of times lighting is carried out in each subframe period, wherein each subframe period has a signal writing time and a data hold period, wherein a first data hold period in one of the subframe periods and a second data hold period in a subsequent subframe period is substantially the same, wherein a first luminance of emitted light from a pixel in the first data hold period and a second luminance of emitted light from the pixel in the second data hold period are different from each other, and wherein inputting a clock signal and an inverted clock signal to the signal line driver circuit is stopped when the signal to be written to the pixel row is identical with the signal stored in the pixel row.