Patent ID: 7443251
Filing Date: 2008-10-28
Classification: H03L

Abstract:
1. A digital phase-frequency detector, comprising: an input circuit for receiving first and second input signals during a plurality of cycles and for generating a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during a given one of said cycles; an output circuit for receiving the intermediate signals generated by the input circuit, and for outputting, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle; and a reset circuit connected to the input circuit for applying a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles; and wherein: the input circuit is adapted to generate (i) the first intermediate signal when, during said one cycle, the first input signal is received before the second input signal, and (ii) the second intermediate signal when, during said one cycle, the second input signal is received before the first input signal; the output circuit is adapted to output (i) the first output signal when the output circuit receives the first intermediate signal, and (ii) the second output signal when the output circuit receives the second intermediate signal; the reset circuit includes, a completion circuit connected to the input circuit for receiving the intermediate signals generated by the input circuit, and connected to the output circuit for receiving the output signals output by the output circuit, and for generating a completion signal when, during said one cycle, the input circuit generates one of the intermediate signals, and the output circuit generates one of the output signals; a reset element connected to the completion circuit for receiving the completion signal therefrom, and wherein one of said defined conditions is that the reset element receives said completion signal during said one cycle; and the output circuit includes a first gate for receiving the first intermediate signal from the input circuit; and a second gate for receiving the second intermediate signal from the input circuit; wherein the first gate is a NAND gate, and the second gate is a NAND gate; the input circuit includes: a first latch for receiving and latching the first input signal, and for outputting a first latch signal when said first input signal is received; a second latch for receiving and latching the second input signal and for outputting a second latch signal when the second input signal is received; a mutex for receiving the first and second latch signals, and for generating, during said one cycle, (i) the first intermediate signal when the mutex receives the first latch signal before the second latch signal, and (ii) the second intermediate signal when the mutex receives the second latch signal before the first latch signal; said mutex including a pair of NAND gates and a filter; and the reset circuit is connected to the first and second latches, and one of said defined conditions is that the reset circuit receives the first latch signal and receives the second latch signal during said one cycle; the completion circuit includes: the first completion gate is a NOR gate, the second completion gate is a NOR gate, and the third completion gate is an OR gate.