Patent ID: 8199574
Filing Date: 2012-06-12
Classification: G11C

Abstract:
1. A memory device comprising: a memory array having a plurality of memory cells coupled to word lines and bit lines; a plurality of cache registers for inhibiting a program operation of a column of memory cells, each cache register coupled to a pair of bit lines; and a memory controller circuit coupled to the memory array, the controller circuit configured to execute a method for programming the plurality of memory cells such that the controller circuit generates a series of program and verify pulses to program original data into a row of memory cells, sets a cache register, reads the row of memory cells after verifying successful programming of the original data to determine sensed data state values using a voltage that is the same as a voltage of the verify pulses, compares the sensed data state values to the original data, and performs a post-programming program operation on the row of memory cells if the sensed data state values do not match the original data.