Patent ID: 6161174
Filing Date: 2000-12-12
Classification: G06F

Abstract:
In a processor including: a pipeline adapted to simultaneously perform one of a plurality of successive operations on each of a plurality of successive instructions within the pipeline, the successive operations including at least an instruction fetch stage, an operand address stage, an operand fetch stage, an execution stage and a result handling stage; and a plurality of indicators, which indicators are selectively updated during the result handling stage for a given instruction to reflect the results obtained during the execution stage of the given instruction; the improvement comprising:A) first decode means for determining which indicators may be affected by the execution of the first instruction of first, second and third successively fetched instructions;B) second decode means for determining if the second instruction of the first, second and third successively fetched instructions is a conditional transfer instruction which tests an indicator and which indicator it tests;C) compare means for determining if the indicator identified by the second decode means matches one of the indicators identified by the first decode means; andD) delay means for holding the second instruction and third instruction of the first, second and third successively fetched instructions at a predetermined stage in the pipeline for a predetermined period if the compare means determines that the indicator identified by the second decode means matches one of the indicators identified by the first decode means.