Patent ID: 7994542
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a logic circuit to which a power supply voltage and a sub-power supply voltage lower than said power supply voltage are supplied at a power supply side and to which a ground voltage and a sub-ground voltage higher than said ground voltage are supplied at a ground side; a driver for generating said sub-power supply voltage based on said power supply voltage and for generating said sub-ground voltage based on said ground voltage; a first wiring layer including a sub-power supply line for supplying said sub-power supply voltage and a sub-ground line for supplying said sub-ground voltage; a second wiring layer including source/drain lines for PMOS and NMOS transistors included in said logic circuit and said driver; a third wiring layer including a main power supply line for supplying said power supply voltage and a main ground line for supplying said ground voltage and arranged opposite to said first wiring layer in a stacking direction to sandwich said second wiring layer; first via structures for connecting said source/drain lines of said second wiring layer to said sub-power supply line or said sub-ground line of said first wiring layer in said stacking direction; and second via structures for connecting said source/drain lines of said second wiring layer to said main power supply line or said main ground line of said third wiring layer in said stacking direction, wherein said logic circuit comprises an inverter circuit in which pairs of a PMOS transistor and an NMOS transistor are connected in a predetermined number of stages, wherein said driver comprises one or more PMOS transistors and one or more NMOS transistors, and an operation of each of the PMOS and NMOS transistors is controlled by a control voltage applied to each gate thereof, wherein the PMOS transistors included in said inverter circuit and the PMOS transistors included in said driver are alternately arranged with a predetermined spacing, and the NMOS transistors included in said inverter circuit and the NMOS transistors included in said driver are alternately arranged with a predetermined spacing.