Patent ID: 7509457
Filing Date: 2009-03-24
Classification: G06F,H04L

Abstract:
1. A system comprising: one or more first processors with a first cache memory and a first address translation mechanism that translates addresses consistent with a set of page table entries, wherein each of the first processors include a reduced instruction set computer architecture with memory access governed by page and segment tables, and the set of page table entries is consistent with the reduced instruction set computer architecture; a system memory that is directly accessible by the one or more first processors; one or more second processors with an attached direct memory access controller with a second address translation mechanism that translates addresses consistent with the set of page table entries, wherein the second processors are single instruction multiple data processors with a unified register file and sequential instruction set semantics, and wherein each of the second processors include a local memory that is a non-cache type of memory; wherein the direct memory access controller transmits commands between the first processors and the second processors with the second processors accessing the system memory by issuing direct memory access commands that specify virtual memory addresses with the direct memory access controller translating between the virtual memory addresses and real memory addresses; wherein the direct memory access controller provides synchronization between the one or more first processors and the one or more second processors; wherein at least one of the commands is selected from the group consisting of copying data to a local storage area included in the second processors, initiating execution on the second processors at a specific address location, copying data from the local storage are included in the second processor to a main memory location, transmitting a notification event from the second processor to the first processor, and suspending execution of one of the second processors; and a bus interconnecting the first processors and the second processors, the bus supporting coherent direct memory access, wherein the first processors, the second processors, and the bus are implemented on a single silicon die substrate.