Patent ID: 6992319
Filing Date: 2006-01-31
Classification: B82Y,H01L

Abstract:
1. A field effect transistor (FET) comprising: a substrate, a source, a gate and a drain; multiple channels in said substrate between said drain and said source to improve the linearity of drain current vs drain voltage characteristics when a gate voltage exceeding the threshold voltage is applied at the gate, said multiple channels alternaing layers of undoped layers of first kind of semiconductor and doped layers of second kind of semiconductor, and said doped layers having doping concentrations which decrease with depth from said gate, wherein the channels are selected from the group consisting of uniformly doped, delta coped, spiked, InAs sub-well, TIP (TIAs) sub-well, InN sub-well and InAs, TIP, TIAs, InN self assembled quantum dots for III-V compound semiconductors, wherein the channels are selected from the group consisting from the group consisting of uniformly doped delta doped, spiked doped, Ge sub-well, Sn sub-well, Sn sub-well and self assembled ciuantum dots selected from the group consisting of Ge and Sn for IV—IV compound semiconductor; and wherein said FET is an Insulated Gate Field Effect Transistor (IGFET).