Patent ID: 7492192
Filing Date: 2009-02-17
Classification: G06F

Abstract:
1. A logic processing circuit comprising: a plurality of flip-flops including a front stage flip-flop and a rear stage flip-flop; a logic gate circuit network adapted to process data stored in the front stage flip-flop, a result of the process being stored in the rear stage flip-flop; and switching means for switching between a power-on and a power-off of the logic gate circuit network based on a clock signal, the power-on being an operation in which power is being provided to the logic gate circuit network, the power-on corresponding to either a low-level state of the clock signal or a high-level state thereof, the power-off being an operation in which the power is off, the power-off corresponding to the state other than the state corresponding to the power-on; wherein in both the power-on and power-off, the plurality of flip-flops are provided with power; in synchronization with the switching from the power-on to the power-off the plurality of flip-flops store data inputted thereto; only within the power-on, the logic gate circuit network processes the data stored in the front stage flip-flop and outputs a result of the processing to the rear stage flip flop.