Patent ID: 7200036
Filing Date: 2007-04-03
Classification: G11C,H01L

Abstract:
1. A memory comprising: a control signal line for receiving a control signal having a first polarity during operation of the memory; a first word line connected to the control signal line; an inverter connected to the control signal line; a second word line connected to the inverter; a transfer gate connected to the first word line and to the second word line so the transfer gate receives the control signal by way of the control signal line and the first word line and the transfer gate receives an inverted control signal having a second polarity opposite said first polarity by way of the control signal line, the inverter, and the second word line during operation of the memory; and a storage element connected to the transfer gate including: a magnetization fixed layer provided on said storage layer through the intermediate layer; wherein the control signal and the inverted control signal are joined in the transfer gate to form a combined signal having both the first polarity and the second polarity and the combined signal is applied to the storage element during operation of the memory.