Patent ID: 8330752
Filing Date: 2012-12-11
Classification: G09G

Abstract:
1. A circuit, comprising: a plurality of output circuits each configured to output a data voltage supplied when a bias power is supplied; a bias circuit configured to generate the bias power; a bias wiring coupled to the bias circuit to supply the bias power to the output circuits; and a plurality of switches configured to cut off the bias power to at least a portion of bias wiring in response to a control signal, the plurality of switches being in series on the bias wiring, wherein at least a portion of the bias wiring is coupled to at least one of the output circuits to supply the bias power, wherein said bias wiring is configured such that a first one of the plurality of output circuits is directly connected to the bias circuit via the bias wiring and a bias signal control circuit without one of the plurality of switches being provided therebetween, and wherein respective ones of the plurality of switches and the plurality of output circuits are provided on the bias wiring in an alternating order from the bias circuit.