Patent ID: 7977197
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A method for fabricating a high-voltage transistor, comprising the steps of: forming, in a substrate, a first deep well having a first conductivity type and a second deep well having a second conductivity type; performing, via a mask, a first implantation of dopant for the second conductivity type, with which a doped region is formed on a top side of the substrate lateral to the second deep well; performing, via another mask, a second implantation of dopant for the second conductivity type at a distance from the second deep well, the first and second implantations forming a channel zone adjacent to the second deep well and a lightly doped drain (LDD) region adjacent to the channel zone on a side facing away from the second deep well; producing a gate oxide; producing a gate electrode arranged above the gate oxide in an area of the channel zone; and after fabrication of the gate electrode, producing a doped region for a body contact via an implantation of dopant for the first conductivity type and a doped region for a source contact via the implantation of the dopant for the second conductivity type.