Patent ID: 6074923
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method of manufacturing a metal-oxide-semiconductor (MOS) transistor, the method comprising the steps of:providing a semiconductor substrate;forming a gate oxide layer, a polysilicon layer and a silicon nitride layer over the substrate;patterning the gate oxide layer, the polysilicon layer and the silicon nitride layer to form a gate structure;forming spacers over the sidewalls of the gate oxide layer, the polysilicon layer and the silicon nitride layer;forming a dielectric layer over the substrate, the silicon nitride layer and the spacers;planarizing the dielectric layer by removing a portion of the dielectric layer until a surface of the silicon nitride is exposed;removing the silicon nitride layer to expose the polysilicon layer;implanting ions into the polysilicon layer to lower its resistance;forming a glue layer over the dielectric layer and the polysilicon layer; andforming a conductive layer over the glue layer.