Patent ID: 6898110
Filing Date: 2005-05-24
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit device comprising regular circuits and redundant circuits for use in relief of any fault arising in said regular circuits, wherein a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines constituting said regular circuits are arranged on the same wiring layer in the same direction, and wherein said plurality of second wiring lines are arranged adjacent to one another, and wherein the first wiring lines constituting said regular circuits comprise a plurality of main word lines extending in a first direction, and a plurality of sub-word line groups are provided, each group matching one or another of said plurality of main word lines, wherein said plurality of second wiring lines constituting said regular circuits are provided in common for said plurality of sub-word line groups, and are a plurality of signal lines for selecting a sub-word line out of one sub-word line group, wherein both said plurality of main word lines and said plurality of signal lines are provided in a layer above said plurality of sub-word line groups over a semiconductor substrate, and wherein two or more of said plurality of signal lines are adjacent to one another and extend in said first direction.