Patent ID: 8932917
Filing Date: 2015-01-13
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, comprising: forming a gate electrode including a metal that can be combined with silicon to form silicide; forming a first silicon nitride layer on the gate electrode by supplying a gas which includes silicon and a gas which includes nitrogen; forming a second silicon nitride layer by supplying a gas which includes silicon and a gas which includes nitrogen on the first silicon nitride layer, wherein a flow amount ratio of the two gases is different from a flow amount ratio supplied for forming the first silicon nitride layer; forming a semiconductor on the second silicon nitride layer; forming a data line and a drain electrode on the semiconductor; and forming a pixel electrode connected to the drain electrode, wherein a [N—H]/[Si—H] binding number ratio of the second silicon nitride layer is less than that of the first silicon nitride layer.