Patent ID: 9105588
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A semiconductor component, comprising: a first passivation layer over a substrate; a bond pad overlying the first passivation layer; a second passivation layer overlying the first passivation layer and the bond pad, the second passivation layer having a first opening and a plurality of second openings, wherein the first opening overlies the bond pad, the plurality of the second openings exposes a top surface of the first passivation layer, and each second opening of the plurality of second openings is spaced from the first opening and from a conductive interconnect connected to the bond pad, wherein a region of the second passivation layer disposed between a first opening and a second opening of the plurality of second openings has a contiguous dielectric composition interfacing the first passivation layer and extending from the first opening to the second opening; at least one conductive interconnect underlying the second passivation layer, the at least one conductive interconnect connected to the bond pad and extending laterally away from the bond pad to a plurality of conductive vias disposed a distance from the bond pad, wherein a first group of the plurality of second openings surrounds the conductive interconnect and plurality of conductive vias; a buffer layer overlying the second passivation layer and filling the plurality of second openings, the buffer layer having a third opening overlapping the first opening and together exposing a portion the bond pad, wherein the combined first opening and third opening has sidewalls; and a conductive feature overlying the portion of the bond pad.