Patent ID: 6774695
Filing Date: 2004-08-10
Classification: H03K

Abstract:
A level conversion circuit comprising:a first circuit including a first input terminal for receiving a first signal having a first signal amplitude, a first output terminal for supplying a second signal having a second signal amplitude greater than said first signal amplitude and being in the same phase as said first signal, and a second output terminal for supplying a third signal having said second signal amplitude and being in a phase reverse to said first signal; and a second circuit including a first p-channel type MOS transistor, a second p-channel type MOS transistor, a first n-channel type MOS transistor, a second n-channel type MOS transistor and, a third output terminal, a source of said first p-channel type MOS transistor being coupled to a first voltage terminal, a drain of said first p-channel type MOS transistor being coupled to a source of said second p-channel type MOS transistor, a drain of said second p-channel type MOS transistor and a drain of said first n-channel type MOS transistor being coupled to said third output terminal, a source of said first n-channel type MOS transistor being coupled to a drain of said second n-channel type MOS transistor and a source of said second n-channel type MOS transistor being coupled to a second voltage terminal, wherein said second circuit is configured to form a fourth signal outputted from said third output terminal, said fourth signal having a signal level of said second signal amplitude and changing on the basis of the signal variation of said second signal supplied from said first output terminal of said first circuit or of said third signal supplied from said second output terminal of said first circuit whichever signal level changes faster to vary a logical threshold of said second circuit so as to accelerate the variation of said fourth signal.