Patent ID: 6118169
Filing Date: 2000-09-12
Classification: H01L

Abstract:
An integrated circuit, comprising:a semiconductor wafer;a plurality of functional blocks implemented in said semiconductor wafer with space between said plurality of functional blocks;a capacitor array comprising a plurality of capacitors cells implemented in said space between said plurality of functional blocks;a conductive layer laminated over of said semiconductor wafer, said conductive layer comprising:a plurality of functional block interconnect areas, with space therebetween, each of which comprises a plurality of intra-block conductive interconnects which connect components within said respective functional blocks, wherein each of said functional block interconnect areas is of approximately equal functional block conductor-to-nonconductor density defined by a ratio of said intra-block conductive interconnects to the area of said functional block interconnect area; anda plurality of capacitor array conductive interconnects laminated in said space between said functional block interconnect areas, so as to provide approximate uniformity in an overall conductor-to-non-conductor density across said conductive layer, wherein said overall conductor-to-nonconductor density is defined by a ratio of said functional block conductive interconnects and said capacitor array conductive interconnects to the area of the conductive layer.