Patent ID: 7969205
Filing Date: 2011-06-28
Classification: H04B,H04L

Abstract:
1. A peak power reduction circuit comprising: a synthesized signal generating unit to generate a synthesized signal in a time domain from input signals taking different modulation methods; a peak power detecting unit to detect at least one region, exceeding a threshold value, of the synthesized signal to generate a peak power signal corresponding to the at least one region and power of the synthesized signal in the at least one region; a reduction signal generating unit to convert the peak power signal into a signal in a frequency domain, to make at least one signal of the signal in a frequency domain, and to organize at least one signal into at least one reduction signal; and a reducing unit to reduce the power by adding the at least one reduction signal with a reduction quantity differentiated on a per-modulation-method basis to at least one of the input signals.