Patent ID: 6838908
Filing Date: 2005-01-04
Classification: H03K

Abstract:
1. A buffer circuit connectable to a power supply voltage, comprising: a node; a driver circuit coupled to the node and comprising at least a first PMOS transistor, the first PMOS transistor having a substrate, a drain, and a parasitic diode between the drain and the substrate, the driver circuit having an on state and an off state; a first part to provide a first bias to the substrate of the first PMOS transistor when a first signal having a voltage level higher than the power supply voltage appears at the node; and a second part to provide a second bias to the substrate of the first PMOS transistor when a second signal having a voltage level less than the power supply voltage appears at the node, wherein the second bias has a voltage level approximately equal to the power supply voltage when the driver circuit is in the off state.