Patent ID: 7723756
Filing Date: 2010-05-25
Classification: H01L

Abstract:
1. A memory array comprising: a semiconductor substrate; a first set of trenches etched a first amount to a first depth in the semiconductor substrate; a second set of trenches etched the first amount and a second amount to a second depth in the semiconductor substrate, wherein the second set of trenches is substantially orthogonal to the first set of trenches, and wherein the first depth is approximately equal to the difference between the second depth and the second amount; wherein the first and second sets of trenches define an array of vertically extending pillars, wherein each pillar in the array of vertically extending pillars comprises a drain region and a body region to form a vertical transistor; a plurality of wordlines formed within at least a portion of the first set of trenches and between adjacent vertical transistors; a plurality of body lines formed within at least a portion of the first set of trenches and between vertical transistors, wherein the wordlines and body lines are alternatingly disposed within the array; and a plurality of bit lines formed within at least a portion of the second set of trenches.