Patent ID: 8112266
Filing Date: 2012-02-07
Classification: G06F,G11C

Abstract:
1. An apparatus comprising: an interface circuit operable to: receive, from a system, (1) write data to be stored on at least one physical memory device of a plurality of physical memory devices, and (2) a first refresh control signal; communicate the write data, after a first delay, to the at least one physical memory device; and in response to receiving the first refresh control signal, communicate within a first time span a distinct second refresh control signal to each of a first subset of the plurality of physical memory devices and a second subset of the plurality of physical memory devices, wherein the interface circuit includes: where the interface circuit is operable to emulate one or more memory devices based on the emulated memory attributes, where the emulated memory attributes include a first latency and the physical memory attributes include a second latency, the first latency being greater than the second latency, where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC, where the first delay is based on the first latency and the second latency, and where the first time span is specified by a refresh latency (tRFC) associated with the one or more emulated memory devices.