Patent ID: 9070599
Filing Date: 2015-06-30
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: a substrate; a plurality of data lines, formed on the substrate and extending in a first direction; a plurality of gate lines, formed on the substrate, crossing the plurality of data lines, and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines and the plurality of data lines crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode, wherein, the thin film transistor comprises: a passivation layer, provided on the source electrode, the drain electrode and the active layer, wherein from a top-down perspective, at a position directly facing the gate line, the passivation layer is provided with a passivation layer through hole configured to perform a connection between the drain electrode and the pixel electrode, wherein the active layer positioned in the channel region and the filling layer are directly formed on the gate insulating layer and positioned in a same plane.