Patent ID: 7954075
Filing Date: 2011-05-31
Classification: G06F

Abstract:
1. A method comprising: receiving, at a processing system, a first data representative of a first set of illegal vector sequences for a circuit design; for each pairing of illegal vector sequences of the first set that differ at only one bit position, inserting, at the processing system, a substitute illegal vector sequence into the first set, the substitute illegal vector having a Boolean variable at the one bit position; removing from the first set each pairing of illegal vector sequences that differ at only one bit position while maintaining each inserted substitute illegal vector sequence to generate a second set of illegal vector sequences at the processing system; sorting, at the processing system, the second set of illegal vector sequences based on sort criteria to generate a third set of illegal vector sequences having a first sort order; for each illegal vector sequence of the third set of illegal vector sequences, identifying, at the processing system, the illegal vector sequence for removal in response to determining that a binary decision diagram (BDD) that is a union of each BDD of each illegal vector sequence preceding the illegal vector sequence in the first sort order is inclusive of a BDD of the illegal vector sequence; removing from the second set of illegal vector sequences illegal vector sequences identified for removal to generate a fourth set of illegal vector sequences at the processing system; and determining, at the processing system, a relationship between the first set of illegal vector sequences and a fifth set of illegal vector sequences for the circuit design based on the fourth set of illegal vector sequences.