Patent ID: 6541842
Filing Date: 2003-04-01
Classification: H01L

Abstract:
An integrated circuit having(i) a subassembly of solid-state devices (ii) metal wiring formed from conductive metals wherein the metal wiring connects the devices within the subassembly (iii) a porous dielectric layer formed over the conductive metals wherein said porous dielectric layer contains pores (iv) interconnect openings formed in the porous dielectric layer (v) a sealing dielectric layer covering pores of the porous dielectric within the interconnect opening (vi) a metal diffusion barrier within the interconnect opening â€ƒwherein said sealing dielectric layer is selected from (1) SixCy:Hz where x has a value of 10-50, y has a value of 1-66, z has a value of 0.1-66 and x+y+z&gE;90 atomic %; (2) SiaObCc:Hd where a has a value of 10 to 33, b has a value of 1 to 40, c has a value of 1 to 66, d has a value of 0.1 to 60, a+b+c+d&gE;90 atomic % and C/Si<0.5 and H/C>0.5; or (3) SieNfCg:Hh where e has a value of 10 to 33, f has a value of 1 to 50, g has a value of 1 to 66, h has a value of 0.1 to 60, e+f+g+h&gE;90 atomic %; and C/Si<0.5 and H/C>0.5.