Patent ID: 8941632
Filing Date: 2015-01-27
Classification: G09G

Abstract:
1. A LCD device, comprising: a timing control unit; an oscillator which is included in the timing control unit and generates a clock frequency; a frequency divider which is included in the timing control unit and reduces the clock frequency supplied from the oscillator by dividing the clock frequency by at least 2; and a mode selection part which is included in the timing control unit and changes at least one driving mode of internal logic circuits by using the divided clock frequency supplied from the frequency divider, wherein the mode selection part changes a driving mode to switch a power control signal outputted from the timing control unit from a normal power state to an ultra low power state when a data signal is a non-signal image; wherein the mode selection part generates a divided clock frequency supplied from the frequency divider as a vertical synchronous signal and uses a count value of the vertical synchronous signal as a control signal for changing at least one driving mode of the internal logic circuits; and wherein the mode selection part does not change at least one driving mode of the internal logic circuits when the count value is “0” and changes at least one driving mode of the internal logic circuits when the count value is “1”.