Patent ID: 7588985
Filing Date: 2009-09-15
Classification: H01L

Abstract:
1. A method for fabricating a fin transistor, the method comprising: forming a pad layer including a first pad layer and a second pad layer over a substrate with a major axis of an active region; patterning the second pad layer provided over the first pad layer using an isolation mask; etching the substrate using the isolation mask and the second pad layer to form trenches; filling the trenches with an insulating material to form isolation structures; forming a plurality of masks defining an opening over the resultant structure including the isolation structures, the opening exposing portions of the active region and the isolation structures; etching the isolation structures within the trenches using the plurality of masks as etch masks and a gas having a high selectivity ratio of the insulating material to the second pad layer to form fin structures, wherein the insulating material remains on sidewalls of the trenches in a direction of the major axis of the active region; forming a gate insulating layer over the fin structures; and forming a conductive layer over the gate insulating layer.