Patent ID: 8242541
Filing Date: 2012-08-14
Classification: H04B

Abstract:
1. A semiconductor device comprising a plurality of I/O cells having: a first I/O area which receives a first supply voltage; a second I/O area which receives a second supply voltage which is lower than the first supply voltage; a core area which receives a third supply voltage; a first circuit included in the first I/O area; a second circuit included in the second I/O area; first and second signal wires; and first and second shield wires each running parallel to the first and second signal wires respectively, wherein the first circuit receives first and second signals outputted from the second circuit via the first and second signal wires respectively and outputs a signal which is level shifted from the second supply voltage to the first supply voltage, wherein the second signal is an inverted signal of the first signal, wherein the first signal wire is a part of a first surrounding wire which surrounds the core area, wherein the second signal wire is a part of a second surrounding wire which surrounds the core area, wherein the first signal wire and the first shield wire pass over the plurality of I/O cells, and wherein the second signal wire and the second shield wire pass over the plurality of I/O cells.