Patent ID: 8115215
Filing Date: 2012-02-14
Classification: G02F,H01L

Abstract:
1. An array substrate comprising: a substrate; a gate metal layer disposed on the surface of the substrate and serving as a gate and a scan line; a gate insulation layer disposed on the substrate and covering on the gate metal layer; a semiconductor layer disposed on the surface of the gate insulation layer and over the gate; a patterned metal layer disposed on the surface of the semiconductor layer and the surface of the gate insulation layer, wherein the patterned metal layer formed on the surface of the semiconductor layer comprises a source and a drain, the patterned metal layer formed on the surface of the gate insulation layer comprises a storage capacitor line and a data line, and the storage capacitor line has a main portion and an extending portion substantially perpendicular to the main portion, wherein the main portion is substantially parallel to the data line and the extending portion is substantially parallel to the scan line; a flat layer covering over the substrate; and a pixel electrode disposed on the surface of the flat layer, which connects with the drain, and overlapping parts of the scan line, parts of the data line, parts of the storage capacitor fine, and parts of the extending portion.