Patent ID: 6055653
Filing Date: 2000-04-25
Classification: G01R,G11C

Abstract:
A gangSIMM memory device for testing a plurality of SIMMs in parallel, the device comprising:a plurality of SIMM slots directly connected to a memory bus extending from a CPU;a plurality of gangSIMM memory tester PWAs where each one is inserted into one of the plurality of SIMM slots; anda plurality of SIMM slots where each one includes a SIMM mounted thereon is mounted upon each one of the plurality of gangSIMM memory tester PWAs, wherein a memory test performed by the CPU of a SIMM slot directly connected to the memory bus extends in parallel to the SIMM of each one of the SIMM slots where each one of the SIMM slots is mounted on one of the plurality of gangSIMM memory tester PWAs.