Patent ID: 6335874
Filing Date: 2002-01-01
Classification: G11C,H01L

Abstract:
A symmetric memory array for dual bit memory cells, the array comprising:a multiplicity of repeating segments, wherein said segments are formed into rows and columns and each segment includes: a cell area formed of four alternating even and odd segmented cell bit lines and having dual bit memory cells formed between neighboring cell bit lines; an even select area located at a first end of said cell area and including a segmented even contact bit line and two select transistors coupled to said even contact bit line and to the even cell bit lines of said segment; an odd select area located at an end opposite to said first end of said cell area and including a segmented odd contact bit line and two select transistors coupled to said odd contact bit line and to the odd cell bit lines of said segment; one even contact coupled to the even contact bit lines of two neighboring even select areas; one odd contact coupled to the odd contact bit lines of two neighboring odd select areas; and alternating even and odd metal lines coupled to said even and odd contacts, respectively; wherein each said select transistor is operative to carry reading, programming, or erasure voltages, and is formed within the pitch of four said memory cells.