Patent ID: 6436763
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method for fabricating embedded dynamic random access memory (DRAMA) circuits with logic integrated semiconductor circuits comprising the steps of:providing a semicondutor substrate having a logic region and a memory region having device areas, said device areas surrounded and electrically isolated from each other by field oxide areas; forming FETs having gate electrodes formed from a first polysilicon layer on said device areas, and having source/drain areas adjacent to said gate electrodes; depositing a first etch-stop layer, and forming a planar first insulating layer thereon; etching contact openings in said first insulating layer and sad first etch-stop layer to said source/drain areas in said memory regions for capacitor node contacts and bit line contacts and depositing a second polysilicon layer and polishing back to form poly-silicon plugs in said contact openings; depositing a second etch-stop layer, and forming a planar second insulating layer, and forming capacitors for said embedded DRAM circuits by: etching capacitor openings in said second insulating and said second etch-stop layers over and to said polysilicon plugs in said contact openings for said capacitor node contacts, and depositing and polishing back a conformal third polysilicon layer to said second insulating layer to form capacitor bottom electrodes in said capacitor openings; removing said second insulating layer selectively and forming an interdielectric layer on said capacitor bottom electrodes; depositing a blanket conformal fourth polysilicon layer sufficiently thick to fill said capacitor openings and to form capacitor top electrodes for said capacitors; depositing a bottom antireflecting coating (BARC) sufficiently thick to fill spaces between said capacitors; forming a patterned photoresist layer on said BARC to pattern said capacitor top electrodes, whereby said BARC reduces the topography of said photoresist layer resulting in improved photoresist resolution over said spaces between said capacitors; plasma etching said BARC and etching said fourth polysilicon layer and said second etch-stop layer to for said capacitor top electrodes, and concurrently exposing said polysilicon plugs in said bit line contacts; forming a planar third insulating layer over said capacitors; etching via holes in said third insulating layer to said polysilicon plugs in said bit line contact openings, to said capacitor top electrodes and concurrently etching via holes to said source/drain areas and said gate electrodes in said logic regions; forming metal plugs in said via holes; depositing and patterning a metal layer to form bit lines for said embedded DRAM circuits and first level of metal interconnections for said logic region.