Patent ID: 8812797
Filing Date: 2014-08-19
Classification: G06F

Abstract:
1. A memory controller for use in a System-on-Chip connected to an off-chip volatile memory, wherein the System-on-Chip includes a plurality of agents, which need access to the volatile memory, wherein the memory controller comprises; a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, and a first time-division multiplexer (CNC wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving the refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the first time-division multiplexer (CNC wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same.