Patent ID: 8947141
Filing Date: 2015-02-03
Classification: H03F,H03K,H03L

Abstract:
1. A clock generator, comprising: an input buffer configured to receive a clock signal at a signal input node and to output the clock signal at an output node; a delay line including an input node coupled to the output node of the input buffer, an output node, and a duty cycle control node, the delay line being configured to be responsive to a duty cycle control signal applied to the duty cycle control node to adjust a duty cycle of the clock signal being coupled through the delay line, wherein the delay line further comprises a gain control node, and wherein the delay line is configured to have a gain that is adjustable responsive to a signal applied to the gain control node; a phase detector having a first input node coupled to the signal output node of the delay line, a second input node coupled to receive the clock signal applied to the signal input node of the input buffer, and an output node, the phase detector being configured to adjust a delay of delay line based on a phase difference between a signal applied to the first input node and the clock signal applied to the second input node; and a duty cycle control circuit having an input node coupled to the output node of the delay line and an output node coupled to the duty cycle control node of the delay line, the duty cycle control circuit being configured to provide at the output node the duty cycle control signal corresponding to the duty cycle of the clock signal being coupled through the delay line from the input node of the delay line to the output node of the delay line.