Patent ID: 6136655
Filing Date: 2000-10-24
Classification: H01L,Y10S

Abstract:
A process for fabricating an active FET body device comprising an active FET region including a gate; a body region and electrical connection between said gate and said body region located within said active region, wherein said electrical connection extends over substantially the entire width, which process comprises:providing a structure comprising a semiconductor substrate, active device regions and isolation regions;providing an insulating pad structure on said substrate;defining openings in said pad structure down to said substrate for determining the shape of the subsequent gate contact;providing a sacrificial oxide layer;implanting dopants for adjusting V.sub.t ;removing said sacrificial oxide layer and forming a gate insulator layer;depositing a doped polysilicon layer and etching the doped polysilicon layer to create doped polysilicon spacers on the sidewalls of said openings in said pad structure;depositing a conformal layer of a material selected from the group consisting of conductive diffusion barrier material, doped amorphous silicon, and doped polysilicon;depositing at least one material selected from the group consisting of a metallic silicide and silicide forming metal, and wherein when said material is said silicide forming metal, reacting said silicide forming metal with polysilicon or amorphous silicon in contact with said metal to form a metallic silicide over polysilicon or amorphous silicon;planarizing said metallic silicide to the top of said isolation pad and filling the cavity bounded by said conductive diffusion barrier material;etching portions of the doped polysilicon, conductive diffusion barrier material and metallic silicide that are unprotected by said isolation pad;removing said isolation pad; andimplanting source and drain regions.