Patent ID: 8405131
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming at least one field effect transistor (FET) in a semiconductor substrate, the at least one FET including a first FET comprising a first source region, a first drain region, a first channel region, a first gate dielectric layer, a first gate electrode, and one or more first gate sidewall spacers, and a second FET comprising at least a second gate electrode and one or more second gate sidewalls spacers that are in direct contact with the second gate electrode; forming an intrinsically stressed first metal silicide layer in a surface of the first gate electrode, wherein said intrinsically stressed first metal silicide layer is laterally confined by the first gate sidewall spacers and is arranged and constructed for creating stress in the first channel region of the first FET, said intrinsically stressed first gate metal silicide layer is comprised of a nickel containing silicide, a cobalt containing silicide or a combination thereof to provide a compressive stress in said first channel region of the first FET or said intrinsically stressed first gate metal silicide layer is comprised of palladium containing silicide to provide a tensile stress in said first channel region of the first FET, and wherein said intrinsically stressed first gate metal silicide layer does not protrude above an upper most surface of said one or more first gate sidewall spacers; and forming a second gate metal silicide layer in a surface of the second gate electrode, wherein the second gate metal silicide layer protrudes above the one or more second gate sidewall spacers.