Patent ID: 8358010
Filing Date: 2013-01-22
Classification: B82Y,H01L

Abstract:
1. A method for forming a nanometric circuit architecture in a semiconductor device, the method comprising: forming a plurality of active areas on a substrate of said semiconductor device; forming on said substrate a seed layer of a first material; forming a mask-spacer of a second material on said seed layer in a region comprised between said active areas, said mask-spacer being realized by a spacer patterning technique and having an end portion extending beyond said region; forming a mask overlapping said mask-spacer and extending in a transverse direction to said mask-spacer; obtaining a seed-spacer by selectively removing exposed portions of the seed layer that are not covered by the mask-spacer and mask, the seed-spacer comprising a linear portion extending in said region and a portion transverse to the linear portion; removing said mask and said mask-spacer; and forming at least one nano-wire of conductive material based on said seed-spacer by a spacer patterning technique, said at least one nano-wire comprising a first portion at least partially extending in said region and a second portion in contact with one of the active areas, said second portion being transverse to said first portion.