Patent ID: 6433422
Filing Date: 2002-08-13
Classification: H01L,H05K,Y02P

Abstract:
A semiconductor integrated circuit including a pair of semiconductor packages, comprising:a pair of chips provided in the semiconductor packages, respectively: a plurality of integrated circuits provided in each of the chips so as to be disposed in a plurality of rows and in a plurality of stages, each of said integrated circuits sending and receiving signals; a plurality of electrode pads provided on a principal plane of said chip so as to be disposed in a plurality of rows and in a plurality of stages, each of said electrode pads being connected to said integrated circuits; a plurality of electrode bumps provided on a surface of each of the semiconductor packages so as to be connected to said electrode pads to form external electrodes for said integrated circuits; wherein one of said pair of semiconductor packages is in a first state in which said electrode bumps are placed on predetermined positions while the other of said pair of semiconductor packages is in a second state in which said electrode bumps are flipped from corresponding positions in the first state; said integrated circuits and said electrode bumps are interconnected differently between said first state and said second state, in such a manner that, when viewing from the principal plane, in a row J and a stage K of said pair of chips are all located identical integrated circuits and that the electrode bumps connected to the integrated circuits located in said row J and said stage K are all located symmetrically with respect to one another.