Patent ID: 9160518
Filing Date: 2015-10-13
Classification: H03L,H04L

Abstract:
1. A circuit comprising: a half-rate phase detector receiving a received signal comprising a stream of binary symbols alternating between an even symbol and an odd symbol, and further receiving a four-phase clock comprising a first phase, a second phase, a third phase, and a fourth phase, said half-rate phase detector outputting a phase error signal; a phase error dissect circuit receiving the phase error signal and outputting an even-symbol phase error signal and an odd-symbol phase error signal; a first 2-bit ADC (analog-to-digital converter) receiving the received signal and outputting an even-symbol data in accordance with the second phase of the four-phase clock; a second 2-bit ADC receiving the received signal and outputting an odd-symbol data in accordance with the fourth phase of the four-phase clock; a first filter receiving the even-symbol phase error signal and outputting a first control signal; a first vertical eye monitor circuit receiving the even-symbol data and outputting a second control signal; a second filter receiving the odd-symbol phase error signal and outputting a third control signal; a second vertical eye monitor circuit receiving the odd-symbol data and outputting a fourth control signal; and a quadrature clock generator receiving the first control signal, the second control signal, the third control signal, and the fourth control signal and outputting the four-phase clock.