Patent ID: 8085573
Filing Date: 2011-12-27
Classification: G11C

Abstract:
1. A ferroelectric memory comprising a plurality of units, each unit comprising a ferroelectric capacitor and a transistor connected in parallel, the memory comprising: first and second memory cell arrays; first and second bit lines in the first and second memory cell arrays, respectively; first and second blocks connected to the first bit line, and comprising N a first plate line in the first memory cell array, and connected to the first and second blocks in common; third and fourth bit lines in the first and second memory cell arrays, respectively; third and fourth blocks connected to the third bit line, and comprising N a second plate line in the first memory cell array, and connected to the third and fourth blocks in common; a first redundant block connected to the first bit line, comprising N a second redundant block connected to the second bit line, comprising N a third redundant block connected to the third bit line, comprising N a fourth redundant block connected to the fourth bit line, comprising N first to fourth redundant plate lines connected to the first to fourth redundant blocks, respectively; and a sense amplifier selectively connectable to one of the first and second bit lines, and selectively connectable to one of the third and fourth bit lines, wherein: