Patent ID: 9054094
Filing Date: 2015-06-09
Classification: H01L,H03H,H05K

Abstract:
1. A method for making a conductive pathway arrangement connected to an integrated circuit wafer, said method comprising: connecting a first conductive pathway, a third conductive pathway and a fifth conductive pathway to one another to form a plurality of conductive containers; arranging dielectric between a fourth conductive area of a fourth conductive pathway and a fifth conductive area of said fifth conductive pathway; arranging dielectric between a third conductive area of said third conductive pathway and said fourth conductive area of said fourth conductive pathway; arranging dielectric between a second conductive area of a second conductive pathway and said third conductive area of said third conductive pathway; arranging dielectric between a first conductive area of said first conductive pathway and said second conductive area of said second conductive pathway; stacking said fourth conductive area of said fourth conductive pathway above said fifth conductive area of said fifth conductive pathway; stacking said third conductive area of said third conductive pathway above said fourth conductive area of said fourth conductive pathway; stacking said second conductive area of said second conductive pathway above said third conductive area of said third conductive pathway; stacking said first conductive area of said first conductive pathway above said second conductive area of said second conductive pathway; positioning said third conductive area as both a centered and shared conductive structure of all conductive containers of said plurality of conductive containers; arranging said plurality of conductive containers such that said plurality consists essentially of an upper conductive container connected to a lower conductive container; electrically insulating said second conductive pathway and said fourth conductive pathway from said plurality of conductive containers and one another; positioning within said upper conductive container a portion of said second conductive area that is smaller in size than said third conductive area; positioning within said lower conductive container a portion of said fourth conductive area that is substantially the same size as said portion of said second conductive area; positioning said portion of said second conductive area and said portion of said fourth conductive area to overlap one another; conductively connecting said second conductive pathway to a first portion of an integrated circuit wafer; and conductively connecting said fourth conductive pathway to a second portion of said integrated circuit wafer.