Patent ID: 6798075
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A grid array (GA) package integrated circuit(IC), the integrated circuit comprising:a substrate; and a chip on the substrate, the chip comprising: a core circuit; a plurality of I/O devices, each I/O device comprising a plurality of I/O units; a plurality of bonding pads arranged in a multi-tier structure surrounding said I/O device; a plurality of traces and a plurality of vias on a plurality of metal layers of the chip for selectively electrically connecting each I/O device and each bonding pad; a plurality of rings and a plurality of fingers surrounding the chip on the substrate; and a plurality of bonding wires for electrically connecting each bonding pad to a corresponding finger or to a corresponding ring; wherein different bonding pads selectively share a same I/O device through the traces.