Patent ID: 6556164
Filing Date: 2003-04-29
Classification: H03M

Abstract:
An analog/digital converter for successive approximation conversion of an analog input signal into a digital output signal, comprising:a clocked successive approximation register buffer storing a digital value; a digital/analog converter converting said digital value buffer-stored in said register to form an analog comparison signal, said digital/analog converter connected to said register and outputting said analog comparison signal; at least one comparator having: at least one linear input stage connected to said digital/analog converter; and an output stage; said at least one comparator: comparing the analog input signal with said analog comparison signal; outputting: a comparator output signal for setting said register; and at least one overdrive indicator signal; and indicating with said at least one overdrive indicator signal an overdriving of said at least one linear input stage; and an acceleration circuit connecting said at least one comparator to said register, said acceleration circuit outputting a switchable clock signal to said register based upon said at least one overdrive indicator signal.