Patent ID: 8143132
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A method, comprising: forming a gate electrode structure of a transistor above a semiconductor region of a semiconductor device, said gate electrode structure comprising a gate insulation layer comprising a high-k dielectric material, a metal-containing cap material formed on said gate insulation layer, an electrode material formed above said cap material and a dielectric cap layer; forming a protective sidewall spacer structure adjacent sidewalls of said gate electrode structure; performing an implantation process to introduce a dopant species for forming halo regions in said semiconductor region by using said dielectric cap layer and said protective sidewall spacer structure as an implantation mask; forming a second spacer on said sidewall spacer structure; performing an etch process so as to remove said dielectric cap layer by using said second spacer as an etch stop material while preserving at least a portion of said protective sidewall spacer structure; removing said second spacer; forming a third spacer after removing said second spacer; and forming drain and source regions in said semiconductor region by using said third spacer as an implantation mask.