Patent ID: 7855118
Filing Date: 2010-12-21
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: forming a first substantially amorphized region in a source area and a second substantially amorphized region in a drain area of a semiconductor region having formed thereon a gate electrode structure comprising a gate electrode and a first non-electrode material formed on a first sidewall of the gate electrode facing a source side of said transistor and a second non-electrode material formed on a second sidewall facing a drain side of said transistor, a lateral distance of said second substantially amorphized region from said gate electrode being greater than a width of said first non-electrode material, wherein forming said first and second substantially amorphized regions comprises forming said second non-electrode material with a second width that is greater than said width, and performing an ion implantation process; and forming drain and source regions in said semiconductor region by implanting at least one dopant species.