Patent ID: 7539927
Filing Date: 2009-05-26
Classification: H03M

Abstract:
1. A decoder suitable for use in a digital communications system utilizing an RS(n′, k′) code modified from an RS(n, k) code, wherein the decoder receives n′-symbol vectors each including k′ message symbols and r′=n′−k′ parity symbols and decodes the n′-symbol vectors to correct errors therein, wherein n, k, n′, and k′ are integers, and k′<n′<n, k′<k <n, and wherein the decoder stores one erasure locator polynomial σ 0 (x), the decoder comprising: a syndrome calculator for receiving the n′-symbol vectors and for calculating syndromes of each n′-symbol vector, wherein the i-th syndrome S an index adjustment circuit for generating an adjusted error/erasure locator polynomial {tilde over (σ)}(x) and an adjusted error/erasure evaluator polynomial {tilde over (ω)}(x) based on the syndromes calculated by the syndrome calculator; a memory device for storing the one erasure locator polynomial σ means for finding the locations and values of the errors in each n′-symbol vector based on the adjusted error/erasure locator polynomial {tilde over (σ)}(x) and the adjusted error/erasure evaluator polynomial {tilde over (ω)}(x), using the look-up table.