Patent ID: 6622291
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A method of determining a budgeted floorplan of a circuit, comprising the steps of:initializing timing of said circuit; performing a physical budgeting of said circuit; partitioning said circuit into blocks of gates; identifying placement of said blocks; and budgeting time to each of said blocks; wherein: said step of initializing timing comprises the steps of, creating a set of flexible timing models from a high level description of said circuit, and creating a set of general constraints that apply to said circuit; and wherein said step of creating a set of flexible timing models comprises the steps of; developing an un-optimized netlist from said high level description, and producing a set of logic cones, each logic cone representing a set of gates from the un-optimized netlist and identifying timing arcs (paths) defined by the set of gates.