Patent ID: 7036103
Filing Date: 2006-04-25
Classification: G06F

Abstract:
1. A method for placing cells of a netlist, comprising the steps of: receiving the netlist, wherein the netlist describes a circuit to be fabricated on a semiconductor chip, and wherein the netlist specifies a particular group of cells and wire connections between the cells; receiving a specification of a placement area describing a plurality of sites on the semiconductor chip where the cells may reside, wherein a circuit density of a ratio of total cells area to total available site area is one hundred percent; performing a coarse placement process that assigns initial locations to the cells; and performing a detailed placement process that assigns a final location to each of the cells by optimizing a cost function dependent on the sites in pairs of rows, thereby allowing swapping of cells between the pairs of rows based on the cost function, wherein each cell location is aligned with a valid site boundary, wherein no two cells are overlapping, and wherein each cell is assigned to a group of legal sites so that each cell is placed on the legal sites without violating constraints set forth in the specification of the placement area.