Patent ID: 7035135
Filing Date: 2006-04-25
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device having a memory cell region in which a statistic memory cell is formed, comprising: a first inverter formed of a first driver transistor of a first conductive type and a first load transistor of a second conductive type; a second inverter formed of a second driver transistor of the first conductive type and a second load transistor of the second conductive type, an output terminal of said first inverter and an input terminal of said second inverter being electrically connected to each other, thereby forming a first storage node, and an output terminal of said second inverter and an input terminal of said first inverter being electrically connected to each other, thereby forming a second storage node; first and second access transistors of the first conductive type having sources electrically connected to said first and second storage nodes, and drains electrically connected to a pair of bit lines; a first transistor of the first conductive type having a gate electrically connected to said first storage node and a source electrically connected to one of search lines as a pair; a second transistor of the first conductive type having a gate electrically connected to said second storage node, a source electrically connected to the other search line of the pair of search lines, and a drain electrically connected to the drain of said first transistor; and a third transistor of the first conductive type having a gate electrically connected to the drains of said first and second transistors and a drain electrically connected to a match line, said first and second access transistors and said first driver transistor being disposed on one side of a region in which said first and second load transistors are formed, said second driver transistor and said first, second and third transistors being disposed on the other side of the region in which said first and second load transistors are formed, and gates of all of transistors disposed in said memory cell region extend in the same direction.