Patent ID: 6620698
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of manufacturing a flash memory, said method comprising:providing a substrate, wherein said substrate comprises a first dielectric layer; forming a trench into said substrate to form a isolation region therein; forming a photoresist layer over said substrate; transferring a line pattern of said substrate into said photoresist layer to expose said substrate and implanting a first ion into said substrate with a tilt angle to form a buried conductive line therein; removing said photoresist layer; forming a second dielectric layer on said buried conductive line and filling of said trench; forming a first gate on said first dielectric layer; forming an oxide/nitride/oxide layer on said first gate; forming a source region and a second region in said substrate which is on both sides of said first dielectric layer; removing said partial second dielectric layer to form a contact therein, wherein a sidewall of said contact is on a slant and a bottom of said contact connects to said buried conductive line; bombarding said sidewall and said bottom of said contact by using a second ion; forming a polysilicon layer on said substrate, said oxide/nitride/oxide layer, and in said contact and filling of said contact; and removing said partial polysilicon layer to form a second gate on said oxide/nitride/oxide layer and to form a connected region on said contact.