Patent ID: 6426901
Filing Date: 2002-07-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of sub memory macros arranged on a semiconductor substrate, the plurality of sub memory macros being collectively accessed during read-out operation and during writing operation; and an operation control circuit for collectively accessing the plurality of sub memory macros during the read-out operation and during the writing operation, wherein each of the plurality of sub memory macros comprises: a plurality of memory cell arrays each comprising-a plurality of memory cells; a data line arranged over the plurality of memory cell arrays, for transmitting write data to be written in a desired one of the memory cells and read-out data read out from a desired one of the memory cells; a DQ buffer circuit for holding the write data and the read-out data to be transmitted through the data line; and an input/output data line for transmitting the write data from outside, and transmitting the read-out data to the outside; an I/0 buffer circuit for holding the write data and the read-out data transmitted through the input/output data line; a fuse circuit provided for the plurality of memory cell arrays, for storing a defective column address of a defective one or ones of the memory cells in the plurality of memory cell arrays, the fuse circuit being located opposite to the input/output data line with respect to the plurality of memory cell arrays; a DQ switch circuit for switching a connection state between the DQ buffer circuit and the I/0 buffer circuit, the DQ switch circuit being located between the DQ buffer circuit and the I/0 buffer circuit; and a switching control circuit for comparing the defective column address stored in the fuse circuit with an input column address which is externally input, and controlling switching of the connection state by the DQ switch circuit based on a result of the comparing.