Patent ID: 7956662
Filing Date: 2011-06-07
Classification: H03K

Abstract:
1. A flip-flop circuit that receives an input signal and a clock signal and generates an output signal and an inverted output signal, the flip-flop comprising: a clock input stage that receives the clock signal and the input signal, wherein the clock signal controls the input signal, and generates a clocked input signal; an inverter that receives the clocked input signal and generates an inverted clocked input signal; an output stage connected to the inverter for generating the output signal and the inverted output signal, the output stage comprising a first field effect transistor (FET) and a second FET connected in series, wherein the inverted input signal is applied to the gate of the second FET, and the inverted output signal is generated at the drain of the second FET; and a level shifting stage connected to the inverter and the output stage, comprising: