Patent ID: 9112023
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A method for forming a multi-gate vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor, comprising: providing a substrate having a first surface and a second surface opposite to the first surface; forming a drift layer on the first surface of the substrate; forming an epitaxial layer having a first conductivity type on the drift layer; etching the epitaxial layer and a thickness portion of the drift layer to form a plurality of trenches; forming a plurality of gate structures, each gate structure of the plurality of gate structures substantially entirely filling each trench of the plurality of trenches, an arrangement of the plurality of gate structures forms a polygonal shape or a concentric circular shape by lines connecting centers of the plurality of gate structures; forming a plurality of doped regions having a second conductivity type opposite to the first conductivity type in the epitaxial layer, each doped region of the plurality of doped regions partially surrounding a top portion of a sidewall of each gate structure of the plurality of gate structures such that each gate structure of two adjacent gate structures has a first half of the top portion of the sidewall surrounded by a doped region of the plurality of doped regions and a second half of the top portion of the sidewall exposed to the epitaxial layer, and two doped regions of the plurality of doped regions are located between the two adjacent gate structures in a cross section vertical to the first surface or the second surface of the substrate; forming a source metal layer on a planar surface of the epitaxial layer, the source metal layer electrically connecting the plurality of doped regions; and forming a drain metal layer on the second surface of the substrate.