Patent ID: 8878311
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A structure comprising: at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack, the gate stack and raised source drain structures being disposed on a surface of a semiconductor material, where the surface of the semiconductor material is a surface of a silicon-on-insulator layer disposed over a layer of buried oxide; a layer of field dielectric overlying the gate stack and raised source drain structures; and first contact metal and second contact metal extending through the layer of field dielectric, the first contact metal terminating in a first trench formed through a top surface of a first raised source drain structure, the second contact metal terminating in a second trench formed through a top surface of a second raised source drain structure, each trench comprising silicide formed on sidewalls and a bottom surface of at least a portion of the trench, where the bottom surface of each trench extends at least to the layer of buried oxide.