Patent ID: 7952186
Filing Date: 2011-05-31
Classification: G01R,H01L

Abstract:
1. A semiconductor package, comprising: at least one bare chip comprising a plurality of external electrodes; a land grid array substrate having an edge, a first surface and a second surface, said first surface including a first portion apart from said edge and a second portion adjacent to said edge, said first portion of said first surface mounting said bare chip and covered with a resin to seal said bare chip with said resin, said second portion of said first surface and said second surface including a non-sealed region which is uncovered with said resin; a plurality of first electrodes arranged on said non-sealed region and connected to said external electrodes; and a plurality of second electrodes arranged on said second surface and connected to said external electrodes, wherein said first electrodes are arranged on said second portion of said first surface, and wherein said first electrodes are arranged on a portion of said second surface corresponding to said first portion of said first surface for connecting a socket with said first electrodes of said first and second surfaces.