Patent ID: 9111934
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including a first side and a second side perpendicular to the first side when seen in a plan view; a first layer including a first large area wiring over the substrate, wherein the first large area wiring for applying a first voltage to said electric fuse; a second layer including a second large area wiring over the first layer, wherein the second layer is different from the first layer, and the second large area wiring for applying a second voltage to said electric fuse; an electric fuse formed over the substrate and between the first layer and the second layer; wherein a first direction of each of the first large area wiring and the second large area wiring aligned with the first side; wherein said electric fuse includes: wherein the maximum width of said first lead-out wiring is greater than the maximum width of said first fuse wiring, and wherein the maximum width of the said second lead-out wiring is greater than the maximum width of said second fuse wiring.