Patent ID: 8533655
Filing Date: 2013-09-10
Classification: G01R

Abstract:
1. A method of testing a circuit design using a programmable integrated circuit (IC), comprising: implementing the circuit design in programmable logic of the programmable IC, the circuit design having a set of test nodes at designated locations in the programmable IC; implementing a sampling circuit having a set of input nodes at designated locations in the programmable IC, the sampling circuit being configured and arranged to sample signals from the set of input nodes; implementing a first routing circuit in the programmable IC, the first routing circuit being configured and arranged to route signals from the designated locations of a first subset of the set of the test nodes to the designated locations of the set of input nodes of the sampling circuit; sampling signals from the first subset of test nodes using the sampling circuit; partially reconfiguring the programmable IC to implement a second routing circuit that replaces the first routing circuit, the second routing circuit being configured and arranged to route signals from the designated locations of a second subset of the set of test nodes to the set of input nodes of the sampling circuit; and sampling signals from the second subset of test nodes using the sampling circuit.