Patent ID: 8300459
Filing Date: 2012-10-30
Classification: G11C

Abstract:
1. A nonvolatile memory, comprising: a group of memory cells accessible by associated bit lines; a group of sensing circuits for sensing the group of memory cells in parallel to determine the conduction currents of the memory cells relative to a first reference current; a controller for controlling operations of the memory; a selected demarcation threshold voltage relative to which the sensing is to be performed, said demarcation threshold voltage is associated with a first demarcation conduction current; a precharge circuit controlled to precharged the group of memory cells via the associated bit lines for a minimum period of time sufficient for performing accurate sensing relative to a second demarcation conduction current, but insufficient for performing accurate sensing relative to said first demarcation conduction current, said second demarcation conduction current being larger than said first one by a predetermined offset; said sensing circuits controlled to sense the group of cells in parallel to identify those memory cells having conduction currents higher than said second demarcation conduction current; those memory cells among the group identified to have conduction currents greater than said second demarcation conduction current are turned off; the remaining cells in the group are precharged by said precharge circuit for a period of time sufficient for performing accurate sensing relative to said first demarcation conduction current; and said sensing circuits controlled to sense the remaining cells in the group relative to said first demarcation conduction current.