Patent ID: 8560999
Filing Date: 2013-10-15
Classification: G06F

Abstract:
1. A method for routing in an electronic circuit, the method comprising: determining, by using at least one processor, at least one hold violation in a net routing in the electronic circuit, the at least one hold violation comprising a time delay in transmission of data in a first path between a start point and an end point in the net routing after a clock transition; inserting a routing blockage associated with the at least one hold violation by defining a boundary between the start point and the end point, the boundary defining an area within which no routing path from the start point to the end point is allowed in the net routing; de-routing the net routing to remove the first path in the net routing between the start point and the end point associated with the at least one hold violation; and re-routing the net routing to detour around the routing blockage so that the start point and the end point are connected via a second path in the net routing, wherein the second path is longer than the first path.