Patent ID: 6479852
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A semiconductor memory cell, comprising:a substrate having a plurality of deep trenched arranged in array; a deep trench capacitor formed in each deep trench, wherein the deep trench capacitor comprises a storage node formed in the substrate and surrounding the deep trench, a capacitor dielectric formed on the sidewall of the deep trench, and an electrode plate filling the deep trench; an isolating layer covering the deep trench capacitor and having a first contact hole to expose a predetermined region of the electrode plate, wherein the exposed region of the electrode plate is a first doped region; a control gate electrode patterned on the isolating layer over the deep trench capacitor, wherein the first doped region is formed at one side of the control gate electrode; a gate insulating layer covering the sidewall and top of the control gate electrode; and a well Si layer covering the isolating layer, the gate insulating layer and the exposed electrode plate to fill the first contact hole, wherein the well Si layer comprises a second doped region formed at the other side of the control gate electrode.