Patent ID: 7412473
Filing Date: 2008-08-12
Classification: G06F

Abstract:
1. A functional unit for digital signal processing comprising: first, second and third adders, each having first and second inputs and an output that is a sum of said first and second inputs and a carry-in bit, wherein an output of said first adder is coupled to a first input of said third adder, and an output of said second adder is coupled to a second input of said third adder; a first multiplexer having at least a first input to receive said output of said first adder right shifted by 1 bit, and a second input to receive least significant bits of an output of said third adder right shifted by 2 bits; and a second multiplexer having at least a first input to receive said output of said second adder right shifted by 1 bit and a second input to receive most significant bits of said output of said third adder right shifted by 2 bits.