Patent ID: 8024522
Filing Date: 2011-09-20
Classification: G06F,Y02D

Abstract:
1. A circuit for tracking memory operations in an out-of-order and speculative processor, wherein the circuit is adapted for use with a trace unit and with an execution unit of the processor, where the trace unit sequences traces for execution thereby forming a trace sequence order, where each of the traces includes a sequence of operations that includes zero or more of the memory operations, where the execution unit executes the operations and has an architectural state, and where the circuit comprises: a memory configured to cache at least some of the data accessed by the memory operations, a sub-circuit configured to hold memory operation ordering information corresponding to the active memory operations, and configured to detect a violation of the ordering constraints; wherein none of the operations of a first particular one of the traces has any effect on the architectural state prior to a commitment of the first particular trace, and where the first particular trace becomes eligible for the commitment after the execution completes for all operations of the first particular trace; and wherein the sub-circuit is further configured to invalidate all of the memory operation ordering information associated with the first particular trace after the commitment of the first particular trace, provided that the first particular trace does commit.