Patent ID: 7973579
Filing Date: 2011-07-05
Classification: H03L,H04L

Abstract:
1. A phase-locked loop controller device, comprising; a phase comparator configured to generate a voltage in response to receiving an output clock pulse signal and a synchronous clock pulse signal associated with an input data stream, wherein the voltage is based on a phase difference between the output clock pulse signal and the synchronous clock pulse signal; and a microcontroller configured to receive a clock pulse at a clock input, wherein a frequency of the clock pulse is based on the voltage, and wherein the microcontroller is further configured to generate the output clock pulse signal in response to receiving the clock pulse; wherein the phase comparator is further configured to generate a lock signal that indicates when a phase difference between the synchronous clock pulse signal and the output clock pulse signal is below a threshold value; and wherein the microcontroller is further configured to output a sampling clock signal synchronized with the input data stream and in phase with the output clock pulse signal.