Patent ID: 6396088
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A semiconductor memory including a plurality of memory cells formed on a semiconductor substrate, a first bit line, a second bit line adjacent to said first bit line, a third bit line adjacent to said second bit line, a fourth bit line adjacent to said third bit line, first and second MOSFETs connected in series between said first and second bit lines, a third MOSFET connected between said first and second bit lines, fourth and fifth MOSFETs connected in series between said third and fourth bit lines and a sixth MOSFET connected between said third and fourth bit lines, comprising:a first active region formed on the main surface of said semiconductor substrate, in order to form said first, second and third MOSFETs; a first, a second and a third semiconductor regions formed in said first active region; a second active region formed on the main surface of said semiconductor substrate, in order to form said fourth, fifth and sixth MOSFETs; a fourth, a fifth and a sixth semiconductor regions formed in said second active region; an insulating layer formed between said first, second, third, fourth, fifth and sixth semiconductor regions and said first, second, third and fourth bit lines; a first conductive portion, formed through said insulating layer, for connecting said first semiconductor region and said first bit line; a second conductive portion, formed through said insulating layer, for connecting said second semiconductor region and said second bit line; a third conductive portion, formed through said insulating layer, over said third semiconductor region; a fourth conductive portion, formed through said insulating layer, for connecting said fourth semiconductor region and said third bit line; a fifth conductive portion, formed through said insulating layer, for connecting said fifth semiconductor region and said fourth bit lines; and a sixth conductive portion, formed through said insulating layer, over said sixth semiconductor region, wherein said first, second, third, fourth, fifth and sixth MOSFETs has a common gate electrode, wherein said first, second and third conductive portions corresponds to vertices of a first triangle from a plane view of said semiconductor substrate, wherein said fourth, fifth and sixth conductive portions corresponds to vertices of a second triangle from a plane view of said semiconductor substrate, and wherein said first triangle has mirror symmetrical relationship with said second triangle.