Patent ID: 8664050
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: providing a wafer including a plurality of regions comprising at least a first semiconductor layer overlying a buried oxide layer overlying a second semiconductor layer; forming one or more pad layers over the wafer; forming a trench in the wafer, the trench extending through the first semiconductor layer, through the buried oxide layer, and partially into the second semiconductor layer; filling the trench with a first dielectric so as to form a shallow trench isolation; removing the one or more pad layers, wherein the removal of the one or more pad layers results in partial removal of the first dielectric so as to create a divot at a side of the shallow trench isolation; forming a gate structure directly over the first semiconductor layer, wherein following the forming the gate structure, the divot extends into the first dielectric of the shallow trench isolation so as to expose sidewalls of the first semiconductor layer, the buried oxide layer, and the second semiconductor layer; depositing a second dielectric uniformly over the semiconductor device, including the divot; etching a hole adjacent and parallel to the gate structure into the second dielectric, wherein the hole is not fully landed and extends at least partially into the shallow trench isolation so as to re-expose at least a portion of the divot; and depositing an insulating material film that can be etched selective to the second dielectric in the hole, wherein at least the portion adjacent to and below said first semiconductor layer the exposed portion of the divot is completely filled to the first semiconductor layer.