Patent ID: 6365467
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method of forming a gate oxide layer with a stacked layer of a bottom oxide layer, a medium oxide layer and a top oxide layer in a semiconductor, comprising the steps of:forming a NO-oxynitride layer as the bottom oxide layer on a semiconductor substrate, wherein the NO-oxynitride layer is formed under NO gas at a flow rate of 5 to 20 l/min; forming a tantalum oxide layer as the medium oxide layer on the NO-oxynitride layer, wherein the tantalum oxide layer is formed to a thickness of 30 to 150 Ã¥, and the effective oxide thickness of the tantalum oxide layer is substantially 5 to 20 Ã¥; forming the top oxide layer on the tantalum oxide layer; and thermal-treating the substrate under a N2O gas atmosphere. wherein the effective gate oxide thickness of the gate oxide layer is 40 Ã¥ or less.