Patent ID: 6583511
Filing Date: 2003-06-24
Classification: H01L

Abstract:
A semiconductor device comprising:a laminated semiconductor chip assembly including a first semiconductor chip and a second semiconductor chip, having respective principal surfaces having pads and back surfaces, the back surface of the first semiconductor chip being laminated to the back surface of the second semiconductor chip with a first joining material; a lead frame integrally having an inner lead with first and second surfaces and an outer lead; a second joining material; metallic wires; and a sealing resin, wherein a second surface of the inner lead is fixed to the principal surface of the first semiconductor chip with the second joining material, a first of the metallic wires is bonded to the second surface of the inner lead and to a pad on the second semiconductor chip by reverse wire bonding, a second of the metallic wires is bonded to a pad on the first semiconductor chip and the first surface of the inner lead by forward wire bonding, the inner lead, the semiconductor chip assembly, the metallic wires, and the second joining material are covered by the sealing resin, and the outer lead protrudes from the sealing resin.