Patent ID: 7433404
Filing Date: 2008-10-07
Classification: H03K

Abstract:
1. An apparatus for generating a phase offset pulse width modulation (PWM) signal, comprising: an offset register having an M-bit offset value; a duty cycle register having an M-bit duty cycle value; a first comparator having a first input coupled to the least significant N bits of the offset register and a second input coupled to the least significant N bits of the duty cycle register, wherein N is less than M, and carry-in output whenever the least significant N-bits of the offset value is greater than the least significant N-bits of the duty cycle value; an adder having a first input coupled to the most significant M-N bits of the offset register, a second input coupled to the carry-in output of the first comparator, and a most significant M-N bit output of the adder; a first counter having a data input coupled to the most significant M-N bit output of the adder and a clock input coupled to a first clock, and a most significant M-N bit output of the first counter; a second counter having a data input coupled to the least significant N bits of the offset register and a clock input coupled to a second clock and a least significant N bit output, wherein the second clock is at a higher frequency than the first clock; a period register having a most significant M-N bit period value; a second comparator having a first input coupled to the most significant M-N bit period value of the period register and a second input coupled to the most significant M-N bit output of the first counter, wherein when most significant M-N bits of the period value in the period register is equal to the most significant M-N bit output of the first counter the second comparator has an output that resets the first counter; a third comparator having a first input coupled to the most significant M-N bit output of the first counter and a second input coupled to the most significant M-N bits of the duty cycle register, wherein the third comparator has a first output indicating when the most significant M-N bits of the first counter is equal to the most significant M-N bits of the duty cycle value, and a second output indicating when the most significant M-N bits of the first counter is less than the most significant M-N bits of the duty cycle value; a fourth comparator having a first input coupled to the least significant N bit output of the second counter and a second input coupled to the least significant N bits of the duty cycle register, wherein the fourth comparator has an output indicating when the least significant N bits of the second counter is equal to the least significant N bits of the duty cycle value; and a logic for generating the phase offset PWM signal from the third and fourth comparator outputs.