Patent ID: 7453255
Filing Date: 2008-11-18
Classification: G01R

Abstract:
1. A circuit for measuring a time interval between transitions of periodic signals at nodes of a circuit-under-test (CUT), the signal having a clock frequency f D , and the circuit comprising: an input for an undersampling clock signal having a sampling frequency f a first latching circuit for periodically latching a digital value of a periodic signal at a first node of said CUT and at edges of said undersampling clock signal; a second latching circuit for periodically latching a digital value of a periodic signal at a second node of said CUT and at edges of said undersampling clock signal, said periodic signals having the same period; means for combining said first and second latching circuit outputs to produce a combined output whose duty cycle is proportional to the time interval between a median edge of said first latch output and a median edge of said second latch output; and a counter circuit for determining an average signal propagation delay based on the number of logic ones in said combined output which occur in a predetermined time interval.