Patent ID: 7673267
Filing Date: 2010-03-02
Classification: G06F

Abstract:
1. A method for reducing jitter in an integrated circuit (IC), comprising: partitioning, by a processor a design block of the IC into a plurality of partitioned design blocks; coupling a core clock to each of the plurality of partitioned design blocks; generating a plurality of mutually exclusive enable signals; coupling one of the plurality of mutually exclusive enable signals to each of the plurality of partitioned design blocks; and gating the core clock for each of the plurality of partitioned design blocks with a corresponding mutually exclusive enable signal which enables a partitioned design block of the plurality of partitioned design blocks to process data when the corresponding mutually exclusive enable signal is asserted, wherein only one partitioned design block of the plurality of partitioned design blocks is enabled at a given time, and jitter of at least one output of the IC is reduced.