Patent ID: 6476653
Filing Date: 2002-11-05
Classification: H03L

Abstract:
A delayed lock loop (DLL) circuit, connected to an output buffer, that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, in which the output buffer supplies an output signal to an output terminal in response to the control clock, said DLL circuit comprises:a first variable delay circuit that receives said reference clock and outputs the control clock and a first delayed clock delayed from the reference clock by a controlled delay time; a second variable delay circuit that receives the first delayed clock of said first variable delay circuit and outputs a second delayed clock delayed from the first delayed clock by a prescribed delay time; a phase comparison/delay control circuit that compares the phase of said reference clock and said second delayed clock and controls the amount of delay of said first variable delay circuit such that the phase of said reference clock and of the second delayed clock are in a prescribed relationship; and a delay measurement circuit that measures an operating delay time of said output buffer and sets the delay amount of said second variable delay circuit in accordance with the measured operating delay time.