Patent ID: 7805697
Filing Date: 2010-09-28
Classification: G06F

Abstract:
1. A method for generating a design for logic circuitry, the method comprising: arranging a plurality of rotary traveling wave oscillators (RTWO) into a number of rows and a number of columns to form a rotary oscillator array, each RTWO having a signal path providing a clock with multiple phases; interconnecting adjacent array elements so that the RWTO in each array element is phase synchronous with the RTWO in an adjacent element; placing a number of clocked devices along the signal path of each array element, each clocked device having a clock input, a data input and a data output; connecting each clock input of the plurality of clocked devices in each element to one of the multiple phases provided by the RTWO element; partitioning the logic circuitry into a number of partitions and mapping each partition to one or more RTWO array elements such that the number of interconnects between partitions, according to a netlist, is minimized and such that partition boundaries are at the data outputs of clocked devices; placing the logic circuitry partitions into regions corresponding to areas bounded by the one or more RTWO elements of the array to which the partition is mapped; and connecting the circuitry in the partition between the clocked devices in the element of the array according to the net list by determining the worst-case logic delays of the partitioned circuitry, and selecting the clocked devices between which the partitioned circuitry is connected based on the worst-case logic delays.