Patent ID: 6496441
Filing Date: 2002-12-17
Classification: G11C

Abstract:
A semiconductor memory device formed in a memory region of a main surface of a semiconductor substrate, comprising:first and second input/output (I/O) terminal groups each provided in a central region of said memory region; a plurality of first memory blocks provided in a peripheral region surrounding said central region, for receiving and outputting data from and to said first I/O terminal group; a plurality of second memory blocks provided in said peripheral region, for receiving and outputting data from and to said second I/O terminal group, the plurality of second memory blocks each being located symmetrically to a corresponding one of said first memory blocks with respect to said central region, and also being arranged so as to surround said central region together with said first memory blocks; a first data bus for connecting said first I/O terminal group to said plurality of first memory blocks; and a second data bus for connecting said second I/O terminal group to said plurality of second memory blocks.