Patent ID: 8450852
Filing Date: 2013-05-28
Classification: H01L

Abstract:
1. A wiring substrate comprising: a plurality of wiring layers and a plurality of insulation layers being alternately stacked one on top of the other; a first main surface; and a second main surface that is positioned on a side opposite of the first main surface; wherein the plurality of insulation layers include wherein the plurality of wiring layers include wherein a pitch between the plural second electrode pads is greater than a pitch between the plural first electrode pads, wherein the plurality of insulation layers are formed with an insulation resin having the same composition, wherein the plurality of insulation layers are formed with a filler having the same composition, wherein the filler content of each of the plurality of insulation layers ranges from 30 vol % or more to 65 vol % or less, and wherein the thermal expansion coefficient of each of the plurality of insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.