Patent ID: 7983112
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A semiconductor device which transmits or receives a signal to or from an external memory by a DDR system, comprising: a DLL circuit, which determines a phase shift amount; an arithmetic circuit, which is connected to said DLL circuit and shifts said phase shift amount by a predetermined phase based upon a test mode signal at test mode time; first to fourth registers, which are connected to said arithmetic circuit and set said phase shift amount shifted by said predetermined phase; and a transmission circuit, which is connected to said first to fourth registers and a first terminal and a second terminal that transmit or receive a signal to or from said external memory, and shifts a phase based upon said phase shift amount set in said first to fourth registers to transmit or receive a signal, wherein said transmission circuit includes: a first phase shifter, which is connected to said first register and phase-shifts a first signal to be outputted to said first terminal based upon said phase shift amount set in said first register; a first bidirectional buffer, which is connected to said first phase shifter and said first terminal, and outputs or inputs said first signal or a second signal to or from said external memory, or loops back said first signal at said test mode time; a second phase shifter, which is connected to said first bidirectional buffer and phase-shifts said first signal or said second signal based upon said phase shift amount set in said second register; a third phase shifter, which is connected to said third register and phase-shifts a third signal to be outputted to said second terminal based upon said phase shift amount set in said third register; a second bidirectional buffer, which is connected to said third phase shifter and said second terminal, and outputs or inputs said third signal or a fourth signal to or from said external memory, or loops back said third signal at said test mode time; a fourth phase shifter, which is connected to said second bidirectional buffer and said fourth register, and phase-shifts said third signal or said fourth signal based upon said phase shift amount set in said fourth register; and a FIFO, which is connected to said second and fourth phase shifters, and takes out said first or second signal correspondingly to said third or fourth signal.