Patent ID: 8688894
Filing Date: 2014-04-01
Classification: G06F

Abstract:
1. A data storage system comprising: an array of nonvolatile memory devices comprising multiple blocks of sub-arrays that are comprising a plurality of sub-blocks where each sub-block comprises a plurality of sectors and each sector comprising a plurality of bytes of memory cells; a management processor in communication with the array of nonvolatile memory devices to provide control signals for programming of selected sub-blocks, erasing selected blocks, and reading selected sub-blocks of the array of nonvolatile memory devices; a sub-block buffer in communication with the array of nonvolatile memory devices and the management processor and partitioned into sub-block segments for temporarily storing data that is read from or to be transferred to the array of nonvolatile memory devices as determined by control signals received from the management processor; a logical-to-physical translation table that receives a requested logical sub-block address and translates the logical sub-block address to a physical sub-block address and in communication with the management processor to transfer the physical sub-block address to the management processor for identifying a physical location of a desired sub-block within the array of nonvolatile memory devices, wherein the logical-to-physical translation table comprises a cache flag table identifying if the requested logical sub-block address is present in the sub-block buffer; an input/output adapter connected between an external port and the sub-block buffer and the management processor to receive a logical address, control, and sectors of data encoded in a communication format and translating the logical address, control, and data encoded in the communication format to a format acceptable by the array of nonvolatile memory devices; a physical address decoder in communication with the input/output adapter to receive the logical address, in communication with the logical-to-physical translation table to transmit the logical address to the logical-to-physical translation table and receive a physical address from the logical-to-physical translation table, and in communication with the management processor to identify that a requested sub-block of data is resident in the sub-block buffer or the array of nonvolatile memory devices; and sub-block buffer cache table in communication with the management processor and comprising a physical sub-block number identifying a physical location within the array of nonvolatile memory devices associated with a sub-block location within the sub-block buffer, a cache type entry designating a cache type occupied by the physical location, and a status entry classifying the sectors of the sub-block according to a validity status.