Patent ID: 6031428
Filing Date: 2000-02-29
Classification: H03L,H04L

Abstract:
A steered frequency phase locked loop (SFPLL) comprising:a phase loop having a first input signal and an output signal and which is adapted to lock the phase of the output signal to that of the input signal, wherein said phase loop includes a phase detector a first signal filtering means coupled to the output of said phase detector for filtering the output signal from said phase detector and a voltage controlled oscillator operatively coupled to an output of said phase detector, an output of said voltage controlled oscillator being connected to an input of said phase detector to complete the phase loop;a frequency loop operatively coupled to the phase loop and having a second input signal providing a reference frequency, wherein said frequency loop includes a frequency detector and a second signal filtering means coupled to an output of said frequency detector for filtering the output signal of said frequency detector, the output of said voltage controlled oscillator is connected to an input of said frequency detector to complete the frequency loop;means for summing the respective output signals of said phase detector and said frequency detector and supplying the sum to said voltage controlled oscillator; anda third signal filtering means connected between said summing means and said voltage controlled oscillator;wherein said reference frequency competes at all times with said first input signal for control of said voltage controlled oscillator, and wherein said frequency loop uses said reference frequency to dynamically steer said phase loop and effectively confines the range of frequencies to which said phase loop can lock close to said reference frequency.