Patent ID: 8884422
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A wafer, comprising: a rigid redistribution layer on the wafer having a plurality of sections, each section including: a plurality of semiconductor dice, each of the semiconductor die having a third plurality of contact pads on a first surface, the semiconductor die being positioned with its first surface facing the first side of a respective section of the redistribution layer, with a fan-out portion of the redistribution layer extending beyond the respective semiconductor die in at least one direction parallel to the first side, each fan-out portion of the redistribution layer including a first set of contact pads of the first plurality of contact pads, wherein a second set of contact pads of the first plurality of contact pads is located proximate the semiconductor die, and wherein the first set of contact pads are electrically isolated from the third plurality of contact pads on the first surface of the respective semiconductor die; a plurality of solder connectors placing each of the third plurality of contact pads of a respective die in electrical communication with a respective one of the second set of the first plurality of contact pads; a plurality of solder balls coupled to the second plurality of contact pads, respectively, on the fan-out portion of the redistribution layer; an encapsulating layer positioned on the first side of the redistribution layer and encapsulating side surfaces of the semiconductor die, side surfaces of the plurality of solder balls, and entire side surfaces of the plurality of solder connectors, each of the plurality of solder balls having an upper surface that is coplanar with an upper surface of the encapsulating layer and a second surface of the semiconductor die and a spacing between each of the semiconductor die indicative of a kerf line for separating the semiconductor die into individual packages.