Patent ID: 8787088
Filing Date: 2014-07-22
Classification: G11C

Abstract:
1. A method for erasing a block, the block is formed on a substrate and comprises a string of non-volatile storage elements, and a plurality of word lines are connected to the non-volatile storage elements, the word lines extend from a lowest word line at a source side of the block to a highest word line at a drain side of the block, the method comprising: in connection with an erase operation, determining a degree of partial programming of the block, the determining a degree of partial programming of the block comprises performing one or more read operations to identify a highest programmed word line among predetermined word lines of the plurality of word lines which are progressively further apart from one another, relative to the source side of the block; and in response to the determining the degree of partial programming of the block, applying an erase voltage to the substrate and subsequently performing an erase-verify test which tests at least one of a resistance or a current in the string of non-volatile storage elements, the erase-verify test is configured according to the degree of partial programming of the block, such that the erase-verify test is relatively stricter when the degree of partial programming of the block is relatively low.