Patent ID: 8988925
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a plurality of first lines; a plurality of second lines extending so as to intersect the first lines; a plurality of memory cells disposed at intersections of the first lines and the second lines, each of the memory cells including a variable resistor; and a control circuit for controlling a voltage applied to the memory cells, the plurality of memory cells being able to change from a write state to an erase state in which resistance value of the memory cell is higher than that of in the write state and being able to change from the erase state to the write state, the control circuit applying a first pulse voltage to the variable resistor in an initial state in which resistance value of the memory cell is higher than that of in the erase state during a forming operation to change the memory cell from the initial state to the erase state, applying a second pulse voltage to the variable resistor in the erase state during a setting operation to change the memory cell from the erase state to write state, the setting operation being performed subsequent to the forming operation, and the second pulse voltage having a polarity opposite to the first pulse voltage.