Patent ID: 9195617
Filing Date: 2015-11-24
Classification: G06F,G11C

Abstract:
1. A semiconductor system comprising: a controller configured to generate a first command signal, a foreground control signal for controlling a drivability of a foreground data and a second command signal; and a semiconductor memory device configured to output a pattern data as the foreground data through a foreground input/output (I/O) line in response to the first command signal, configured to store the foreground control signal therein in response to the second command signal, and configured to control the drivability of the foreground data according to the foreground control signal, wherein the drivability of the foreground data is controlled by a plurality of drivers according to the foreground drive signal, and wherein the foreground control signal is configured to be varied a level combination of the foreground control signal according to a delay time of the foreground data outputted through the foreground I/O line.