Patent ID: 8183642
Filing Date: 2012-05-22
Classification: H01L

Abstract:
1. A CMOS circuit, comprising: a first type device, said first type device comprises a first type channel hosted in a Si based material, and a first gate stack overlapping said first type channel, wherein said first gate stack comprises a first gate layer of a gate metal material, said first type device further comprises a first gate insulator in-between said first gate stack and said first type channel, wherein said first gate insulator comprises at least two layers: a first dielectric layer of a high-k insulator material and a first interfacial control layer, wherein said first dielectric layer is in-between and in direct contact with said first gate layer and with said first interfacial control layer; a second type device, said second type device comprises a second type channel hosted in said Si based material, and a second gate stack overlapping said second type channel, wherein said second gate stack comprises a second gate layer of said gate metal material, said second type device further comprises a second gate insulator in-between said second gate stack and said second type channel, wherein said second gate insulator comprises at least two layers: a second dielectric layer of said high-k insulator material and a second interfacial control layer, wherein said second interfacial control layer is in-between and in direct contact with said second gate layer and with said second dielectric layer; and wherein said first interfacial control layer is of a different material than said second interfacial control layer, and wherein said first interfacial control layer is absent in said second type device, and said second interfacial control layer is absent in said first type device.