Patent ID: 7342423
Filing Date: 2008-03-11
Classification: G06F,H03K

Abstract:
1. A circuit for calculating a logical combination of two input operands, comprising: a first input for receiving a first dual rail signal comprising data values of the first input in a calculation cycle and precharge values in a precharge cycle; a second input for receiving a second dual rail signal comprising data values of the second input in the calculation cycle and precharge values in the precharge cycle; an output for outputting a third dual rail signal comprising result values in the calculation cycle and precharge values in the precharge cycle; a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output; and a precharge circuit capable of impressing precharge values in the output already when precharge values are detected at a single input, or capable of terminating impressing the precharge values only when the first dual rail signal and the second dual rail signal comprise data values.