Patent ID: 6693569
Filing Date: 2004-02-17
Classification: H03M

Abstract:
A decoding circuit, receiving as an input a 2N-bit signal composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, said decoding circuit being adapted to generate 2N types of decoded signals on inverting one bit in said 2N-bit signal received, wherein on the premise that the number 2N bit and a first bit composing respectively one and other ends of the 2N-bit signal are adjacent to each other, among the 2N-bits of said decoded signal, one bit is, if N being equal to 2, or neighboring plural (Nâˆ’1) bits are, if N being greater than 2, of a first value, with the remaining bits being of a second value.