Patent ID: 6259647
Filing Date: 2001-07-10
Classification: G11C

Abstract:
A synchronous semiconductor memory device for taking in an address signal and a control signal in synchronization with an external clock signal comprising:a memory cell array having a plurality of memory cells arranged in rows and columns;a first internal clock producing circuit for controlling a synchronous operation of said semiconductor memory device,said first internal clock producing circuit receiving complementary clock signals including first and second clock signals having a constant phase difference therebetween, and producing an internal clock signal having an active period corresponding to said phase difference;a memory cell select circuit for selecting said memory cell in synchronization with said internal clock signal; andan I/O circuit for transmitting data to and from said memory cell selected by said memory cell select circuit;wherein said first internal clock producing circuit includes an oscillator circuit responding to activation of said complementary clock signal by producing the internal clock signal having a predetermined number of active periods each corresponding to said phase difference during one period of said complementary clock signal;said memory device further comprising:(a) a second internal clock signal producing circuit for producing a clock signal synchronized with said external clock signal;(b) a select circuit for receiving the outputs of said first and second internal clock signal producing circuits, and issuing, as the internal clock signal, the output of said second internal clock signal producing circuit in the normal operation mode and the output of said first internal clock signal producing circuit in the test operation mode; and(c) a clock signal input terminal for receiving said external clock signal in said normal operation mode and receiving said complementary clock signal in said test operation mode.