Patent ID: 6403433
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit including a substrate and a plurality of transistors, the plurality of transistors including a first transistor having a gate structure disposed on a film, the film having a thickness of 150-200 Ã¥, the first transistor having a channel thickness of 150-200 Ã¥, the gate structure being located between a pair of isolation structures, the method comprising:providing the pair of isolation structures in the film, the isolation structures extending from a top surface of the film to a bottom surface of the film; forming an elevated source region and an elevated drain region on the film by selective silicon epitaxy, wherein silicon material is not provided above the isolation structures, the elevated source region and the elevated drain region being between the pair of isolation structures, the gate structure being between the elevated source region and the elevated drain region; amorphizing the elevated source region and the elevated drain region and a portion of the film; providing dopants to the elevated source region and the elevated drain region and the film; and annealing the elevated source region and the elevated drain region to recrystallize the elevated source region and the elevated drain region, wherein a transistor source region extends from a top surface of the elevated source region to the bottom surface of the film and a transistor drain region extends from a top surface of the elevated drain region to the bottom surface of the film.