Patent ID: 6779062
Filing Date: 2004-08-17
Classification: G06F

Abstract:
A platform comprising:a central processing unit; a controller coupled to the central processing unit through a system bus; a register device coupled between the central processing unit (CPU) and said controller, said register device receives commands from said CPU and said controller receives said commands from said register device, said register device disposed externally to said CPU and said controller; and a bus coupled to said controller having an end that is adapted to receive a device, wherein a shadow register space of said controller and said register device allows completion of an input/output (I/O) cycle to said device during a condition when a task-file register is written and said CPU must wait until the I/O cycle out to said task-file register is completed, and said register device receives said commands from said CPU at a higher rate than said controller receives said commands from said register device.