Patent ID: 6349376
Filing Date: 2002-02-19
Classification: G06F,G11C

Abstract:
A method for decoding an address specifying a destination for a data transfer operation in a system having an address decoder that in a normal decode operation finds a match with one of a plurality of addressable ranges in the system address space, wherein at least one of the plurality of addressable ranges is not normally decodable in a single clock cycle, comprising:receiving at the address decoder a first address to be decoded and determining decode results by finding in a normal decode operation that the first address matches one of said plurality of addressable ranges; following the first address normal decode operation, storing the first address decode results and storing the addressable range matched in the first address normal decode operation as a bypass address range; receiving at the address decoder a next address to be decoded; in the first clock cycle of the next address decode operation, initiating a normal decode operation and checking the next address against the bypass address range, and selecting the stored first address decode results if the next address to be decoded matches the bypass address range from the first address decode operation, otherwise decoding the next address to be decoded in a normal decode operation to produce normal decode operation results; and providing the selected, stored first address decode results to routing logic if the next address to be decoded matches the bypass address range, otherwise providing to the routing logic the normal decode operation results for the next address.