Patent ID: 6372640
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of locally forming metal silicide layers, said method comprising the steps of:providing a silicon substrate, and said silicon substrate is divided into at least two regions: one is an array region, the other is a peripheral region forming a first dielectric layer on said silicon substrate within said array region and a plurality of first transistors on said first dielectric layer, wherein there is a first spaced region between any two neighboring gates of said plurality of first transistors; forming a plurality of second transistors on said silicon substrate within said peripheral region, wherein there is a second spaced region between any two neighboring gates of said plurality of second transistors, and said second spaced region is larger than said first spaced region; conformally depositing a nitride layer to cover said silicon substrate, said array region, and said peripheral region; performing a first selective etching process to remove a partial said nitride layer, so that a plurality of first sidewalls of said plurality of first transistors and a plurality of second sidewalls of said plurality of second transistors are formed, wherein a partial region of said first spaced region is covered by said plurality of first sidewalls and a partial region of said second spaced region is covered by said plurality of second sidewalls; depositing a first oxide layer to cover said array region, said peripheral region, said plurality of first transistors, said plurality of second transistors, said plurality of first sidewalls, and said plurality of second sidewalls; performing an ion implantation to form drains and sources of said plurality of first transistors and said plurality of second transistors; depositing a second oxide layer on said first oxide layer; performing a second selective etching step to remove a part of said first oxide layer and a part of said second oxide layer, so that the surface of the gates of said plurality of first transistor and the gates of said plurality of second transistor is exposed, but the surface of the substrate within said first spaced region can not be exposed; depositing a photoresist layer to cover overall said array region and overall said peripheral region; removing a part of said photoresist layer within said peripheral region; performing a third selective etching process to completely remove said first oxide layer and second oxide layer within said peripheral region by using said photoresist layer as a mask; removing said photoresist layer; depositing a metal layer to cover said silicon substrate, overall said array region, and overall said peripheral region; performing a heating process to form metal silicide; and removing said metal layer.