Patent ID: 6285053
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A capacitor formed over a semiconductor substrate, comprising:a first insulating layer on said substrate;first and second self-aligned contact pads formed in the first insulating layer on said substrate;a second insulating layer formed over said first insulating layer;a landing pad formed in said second insulating layer and electrically connected to said first self-aligned contact pad;a third insulting layer formed over said second insulating layer and having a trench exposing said landing pad;a capacitor lower electrode formed in said trench to be electrically connected to said landing pad wherein said capacitor lower electrode is formed on sidewalls of said trench and extended toward said landing pad to overlap an edge part of said landing pad and expose a center part thereof; anda dielectric layer formed on said capacitor lower electrode, wherein said dielectric layer is in direct contact with said landing pad, and wherein a portion of said dielectric layer is formed directly on said exposed landing pad.