Patent ID: 6870397
Filing Date: 2005-03-22
Classification: H03K

Abstract:
1. An input/output circuit for an integrated circuit comprising: an input pad; a pull-up circuit coupled to the input pad; a first multiplexer having a control terminal receiving values from a first plurality of memory cells, the first multiplexer having a first output signal coupled to a control terminal of the pull-up circuit; a pull-down circuit coupled to the input pad; a second multiplexer having a control terminal receiving values from a second plurality of memory cells, the second multiplexer having a second output signal coupled to a control terminal of the pull-down circuit; a tri-state buffer coupled to the input pad; a third multiplexer having a control terminal receiving a value from a first memory cell at a first input terminal and receiving a first user-defined value at a second input terminal, the third multiplexer having a third output signal coupled to an enable terminal of the tri-state buffer; and a fourth multiplexer having a control terminal receiving a value from a second memory cell at a first input terminal and receiving a second user-defined value at a second input terminal, the fourth multiplexer having a fourth output signal coupled to a data output terminal of the tri-state buffer; wherein a configuration signal from a user-defined logic circuit is provided to the control terminals of the first, second, third, and fourth multiplexers.