Patent ID: 8097516
Filing Date: 2012-01-17
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure comprising: providing a hybrid substrate comprising a first lower semiconductor layer of a first crystallographic orientation and a second upper semiconductor layer of a second crystallographic orientation which differs from the first crystallographic orientation, wherein a conductive bonding interface separates said semiconductor layers from each other; providing at least one opening of a first depth in said hybrid substrate which exposes said first lower semiconductor layer; forming a spacer having said first depth within said at least one opening; regrowing a semiconductor material on an exposed portion of said first lower semiconductor layer, said semiconductor material having said first crystallographic orientation; planarizing said semiconductor material to an upper surface of said second upper semiconductor layer to provide a structure having at least two coplanar surfaces of different crystallographic orientation; and forming trench isolation regions having a second depth which is shallower than the first depth within said structure having the at least two coplanar surfaces of different crystallographic orientation, wherein said spacer isolates the semiconductor material formed in said at least one opening from at least the second upper semiconductor layer, and wherein said second upper semiconductor layer defines a first device region and said semiconductor material formed in said at least one opening defines a second device region.