Patent ID: 6391698
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for forming a transistor with a gradient doped source/drain, said method comprising:providing a substrate; forming two first N-wells in said substrate, wherein said first N-wells are separated in both sides of said substrate; forming two second N-wells in said substrate, wherein said second N-wells overlie said first N-wells, wherein an implanting concentration of said first N-wells is smaller than an implanting concentration of said second N-wells; forming a field oxide region in said substrate between said first N-wells, wherein said field oxide region overlies on a portion of said second N-wells; removing a portion of said field oxide region and said substrate to form a trench in said substrate, wherein said remained field oxide region overlies on said second N-wells; forming a gate oxide layer on a bottom surface and a sidewall of said trench; forming a polysilicon gate on said substrate, wherein said trench is filled with said polysilicon gate and said polysilicon gate overlies on a portion of said remained field oxide region; and forming a N+-type source/drain in said substrate, wherein said N+-type source/drain is adjacent to said remained field oxide region and overlies said second N-wells.