Patent ID: 8133786
Filing Date: 2012-03-13
Classification: H01L

Abstract:
1. A method of fabricating a transistor, the method comprising: forming an isolation trench in a substrate to define an active region, the isolation trench comprising an upper isolation trench having sidewalls including, at least in part, a negative profile and a lower isolation trench formed through a bottom surface of the upper isolation trench, wherein the lower isolation trench has a width less than or equal to a minimal width of the upper isolation trench, and wherein the upper isolation trench defines an upper active region in the active region and the lower isolation trench defines a lower active region in the active region having a width greater than or equal to the width of the upper active region; filling the isolation trench with an insulating material; forming a gate electrode extending through the upper active region into the lower active region; and forming source/drain regions in the active region on respective sides of the gate electrode.