Patent ID: 9153562
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. An in-process unit including upper and lower dielectric substrates and a plurality of microelectronic elements disposed between a surface of the upper dielectric substrate and a surface of the lower dielectric substrate facing the surface of the upper dielectric substrate, each of the microelectronic elements comprising a semiconductor chip, and each of the upper and lower dielectric substrates including a plurality of regions, each region of the upper dielectric substrate being aligned with a corresponding region of the lower dielectric substrate with at least one of the microelectronic elements disposed therebetween, and each region of the upper dielectric substrate and each region of the lower dielectric substrate having interlayer connection terminals at the surface thereof, the in-process unit further including vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and having an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.