Patent ID: 6718411
Filing Date: 2004-04-06
Classification: G06F

Abstract:
An application specific integrated circuit which includes(a) a multiplicity of functional cores which generate data transfer transactions; (b) at least one memory controller for controlling at least one memory in accordance with said data transfer transactions; (c) a common memory bus system coupling the cores and the memory controller, and (d) at least one aggregator in said memory bus system, said aggregator being coupled to a multiplicity of memory bus sections extending in a sense towards the cores and including means for placing data transfer transactions on any of the multiplicity of memory bus sections on a common memory bus section extending in a sense towards said at least one memory controller, said aggregator being operative to place on said common memory bus section a data write transaction received by said aggregator on any of said multiplicity of memory bus sections and to direct to one of said multiplicity of memory bus sections a data read transaction received by said aggregator on said common memory bus section.