Patent ID: 6078941
Filing Date: 2000-06-20
Classification: G06F

Abstract:
A pipelined computational structure comprising:a first stage which comprises a first adder and a second adder capable of operating in parallel;a first multiplexing circuit coupled to the first stage, wherein the first multiplexing circuit selects addend signals applied to the first stage, the first multiplexing circuit selecting from a first set of signals including signals from a register file;a second stage having input ports coupled to output ports of the first stage, wherein the second stage comprises a third adder and a fourth adder which are capable of operating in parallel;a second multiplexing circuit coupled to the first stage and the second stage, wherein the second multiplexing circuit selects addend signals applied to the second stage, the second multiplexing circuit selecting from a second set of signals including output signals from the first stage and the signals from the register file; anda first multiplexer having input ports coupled to the first, second, third, and fourth adders, wherein the first multiplexer selects a signal representing the result of an arithmetic operation performed by the structure.