Patent ID: 7652318
Filing Date: 2010-01-26
Classification: H01L

Abstract:
1. A split-gate memory cell, comprising: a plurality of continuous linear isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region along a second direction formed in the semiconductor substrate without disrupting the continuous linear isolation regions; a pair of floating gates disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions; a pair of control gates self-aligned with the floating gates and disposed on the floating gates along a second direction; a pair of ONO stack layers interposed between the pair of floating gates and the pair of control gates, wherein the pair of floating gates, ONO stack layers, and control gates have equal width along the second direction; a source line between the pair of control gates along the second direction; an oxide layer disposed on sidewalls of the pair of floating gates, ONO stack layers, and control gates and with an opening area on the source region; and a pair of select gates disposed on the outer sidewalls of the pair of control gates respectively along the second direction.