Patent ID: 7095649
Filing Date: 2006-08-22
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a main memory cell array having memory cells arranged in a matrix form and including at least one magneto-resistance effect element; a redundant memory cell array having memory cells arranged in a matrix form and including at least one magneto-resistance effect element used to compensate for a fault occurring in the main memory cell array, the redundant memory cell array being formed independently of the main memory cell array and arranged in a position apart from the main memory cell array; main write wirings arranged on the main memory cell array; redundant write wirings arranged on the redundant memory cell array; a write current source; a common node connected to the write current source; a first selector connected between the common node and one-side ends of the main write wirings; a second selector connected between the common node and one-side ends of the redundant write wirings; a third selector connected to the other ends of the main write wirings; and a fourth selector connected to the other ends of the redundant write wirings.