Patent ID: 6081474
Filing Date: 2000-06-27
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising:a memory cell array including a number of memory cells formed of MOS transistors and located in the form of a matrix;a plurality of bit line terminals for supplying a sense amplifier current to one electrode of a pair of electrodes of each of the memory cells arranged in a column direction;a plurality of ground line terminals for reading data from the other electrode of each of the memory cells arranged in a column direction;a plurality of word lines each connected in common to gates of the memory cells arranged in a row direction;a plurality of first sub-bit lines connected to said bit line terminals and individually connected to the one electrode of the memory cells;a plurality of second sub-bit lines each connected to said ground line terminals and individually connected to the other electrode of the memory having the one electrode connected to said first sub-bit lines; anda plurality of bank selection transistors connected between said bit line terminals and said ground line terminals and said first sub-bit lines and said second sub-bit lines, and selectively turned on by bank selection signals,the number of said first sub-bit lines connected to one of said bit line terminals being different from the number of said second sub-bit lines connected to one of said ground line terminals.