Patent ID: 8603875
Filing Date: 2013-12-10
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps: providing a semiconductor substrate; forming an element of field oxide at a top surface of said substrate in an SRAM PMOS area of an SAR SRAM area of said integrated circuit; forming a logic PMOS gate dielectric layer on said substrate in a CMOS area of said integrated circuit, said CMOS area being separate from said SAR SRAM area; forming an SRAM NMOS gate dielectric layer on said substrate in an SRAM NMOS area of said SAR SRAM area; forming an SRAM PMOS gate dielectric layer on said substrate proximate to said field oxide in said SRAM PMOS area; forming a logic PMOS gate on said logic PMOS gate dielectric layer; forming an SRAM NMOS gate on said SRAM NMOS gate dielectric layer; forming an SRAM PMOS gate on said SRAM PMOS gate dielectric layer; forming an SRAM gate extension on said field oxide; forming a conformal layer of sidewall spacer material over an existing top surface of said integrated circuit; forming a localized SRAM etchback mask over said layer of sidewall spacer material so as to expose said layer of sidewall spacer material layer at said SRAM gate extension and at said substrate in an SRAM PMOS drain region between said SRAM PMOS gate and said field oxide; performing a localized etchback process on said integrated circuit which removes between 3 and 30 nanometers of said sidewall spacer material in an area exposed by said localized SRAM etchback mask; removing said localized SRAM etchback mask; performing a sidewall spacer etch process on said integrated circuit which removes sidewall spacer material from said layer of sidewall spacer material and leaves sidewall spacer material on vertical surfaces at said logic PMOS gate, said SRAM NMOS gate, said SRAM PMOS gate and said SRAM gate extension to form: forming p-type logic PSD layers in said substrate adjacent to said logic PMOS gate; forming n-type SRAM NSD layers in said substrate adjacent to said SRAM NMOS gate; forming a p-type drain node SRAM PSD layer in said substrate in said SRAM PMOS drain region; forming a p-type source node SRAM PSD layer in said substrate adjacent to said SRAM PMOS gate opposite from said drain node SRAM PSD layer; forming a PMD layer over an existing top surface of said integrated circuit; and forming a stretch contact in said PMD layer which overlaps and makes electrical contact to said drain node SRAM PSD layer and said SRAM gate extension; so that: