Patent ID: 7566627
Filing Date: 2009-07-28
Classification: H01L

Abstract:
1. A method of making an integrated circuit comprising: (a) forming a first level of a semiconductor structure, wherein forming the first level comprises: (b) forming an inter-level dielectric layer over the first level, wherein the one or more vias extend through the inter-level dielectric layer; (c) repeating steps (a) and (b) as desired to form one or more levels of semiconductor structure; (d) forming an extraction via through the one or more intra-metal dielectric layers and one or more inter-level dielectric layers; (e) forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process; and (f) forming a non-conformal layer disposed on an etch stop layer to hermetically seal an opening of the extraction via, wherein the copper bulk head structure seals the supercritical fluid from adjacent portions of the semiconductor structure.