Patent ID: 6956805
Filing Date: 2005-10-18
Classification: G11B

Abstract:
1. A signal processing circuit extracting a signal superimposed on a reference signal varying in level at a given frequency, the superimposed signal being inserted into the reference signal at given positions of a given level thereof and having a peak level higher than a level of the reference signal by a value greater than a given value, the signal processing circuit comprising: a first pulse generation part generating a first binary signal by binarizing a composite signal of the reference signal and the superimposed signal by using a given reference level as a threshold value; a noise elimination part eliminating noise from the first binary signal by using a cumulative length of time of each of polarities of the first binary signal; a second pulse generation part generating a second binary signal by binarizing the composite signal by using, as a threshold value, a level higher than the level of the reference signal by a value smaller than or equal to the given value; and a gate part outputting the second binary signal based on a signal output from said noise elimination part.