Patent ID: 8892811
Filing Date: 2014-11-18
Classification: G06F

Abstract:
1. An apparatus comprising: a memory circuit comprising (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses; and a manager configured to (i) receive a plurality of data items and respective host addresses in a random order from one or more applications, (ii) transform said respective host addresses to said memory addresses, (iii) write said data items in an active one of a plurality of regions in said memory circuit and (iv) mark said memory addresses in said active region that store said data items as used, wherein (a) said applications are executed in one or more computers, (b) said memory addresses in said active region are accessed in a sequential order while writing said data items to minimize a write amplification and (c) said random order is preserved between said data items while writing in said active region.