Patent ID: 7466617
Filing Date: 2008-12-16
Classification: G11C

Abstract:
1. A dynamic random access memory circuit comprising: at least one write bit line; at least one read bit line; a capacitive storage device; a write access device, said write access device being operatively coupled to said capacitive storage device and said at least one write bit line; a sense amplifier, said sense amplifier being operatively coupled to said at least one read bit line and configured to generate an output signal; a refresh bypass device, said refresh bypass device being operatively associated with said sense amplifier and said at least one write bit line so as to selectively pass said output signal to said at least one write bit line; and a write-read bypass device, said write-read bypass device being operatively coupled to said at least one write bit line and said at least one read bit line and being configured to selectively pass a write signal from a write bit line signal point along said at least one write bit line to a read bit line signal point along said at least one read bit line for output to a data output.