Patent ID: 6615289
Filing Date: 2003-09-02
Classification: G01R,H01L

Abstract:
An intergrated semiconductor chip configuration of the type having a semiconductor chip with a plurality of bonding pads for an exchange of input data and output data, said plurality of bonding pads including a first group of bonding pads being used for the exchange of input data output data in a selected normal mode selected from a plurality of normal modes and a second group of bonding pads not being used for the exchange of input data and output data in the selected normal mode, and a third group pf bonding pads with a least one bonding option pad for selecting a data input/data output organizational form out of a plurality of dasta input/data output organizational forms, wherein the improvement comprises:said first group, said second group, and said third group of bonding pads being connected to respective external terminals; and said semiconductor chip being operable in a test mode and having an altered data input/data output organizational form during the test mode, causing said second group of bonding pads to be used in test mode for the exchange of input data and output data; and a number of bonding pads of said first group and a number of said second group being, respectively, variable without changing the respective internal and external interconnections, depending on said selection of the data input/data output organizational form.