Patent ID: 8171234
Filing Date: 2012-05-01
Classification: G06F

Abstract:
1. A memory system comprising: a plurality of ports, wherein each of the ports receives access requests, and wherein each of the ports registers the received access requests in response to a first clock signal; a memory core that includes a plurality of memory banks; a broadcast network that transmits each of the access requests received by each of the ports to each of the memory banks, wherein each of the access requests includes a bank address that specifies one of the memory banks, whereby a plurality of different memory banks are concurrently accessed in response to access requests received on a plurality of different ports; and a bank address remapping register that stores a bank address remapping value that identifies a location of the bank addresses within the received access requests, wherein the bank address remapping register stores different bank address remapping values to identify different locations of the bank addresses within the received access requests for different applications of the memory system.