Patent ID: 6184086
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method for forming a memory device comprising the following steps:forming a transistor source having a lower surface and a transistor drain having a lower surface, said source and drain formed in a semiconductor substrate;forming a trench in said semiconductor substrate having, in cross-section, a ""V"" shape and a bottom, said trench separating said source and said drain wherein said bottom of said trench is below said lower surface of at least one of said source and said drain;providing a first insulation layer over said semiconductor substrate within said trench;forming a floating gate layer at least partially within said trench wherein said first insulation layer separates said floating gate layer from said semiconductor substrate;forming a second insulation layer over said floating gate layer;forming a control gate layer over said floating gate layer and separated from said floating gate layer by said second insulation layer;forming a patterned mask over said control gate layer, said second insulation layer, said floating gate layer and said first insulation layer; andetching said control gate layer, said second insulation layer, said floating gate layer, and said first insulation layer using said mask as a pattern,wherein said step of forming said source and said drain comprises the step of forming said source and drain subsequent to said step of etching said floating gate layer such that said both of said source and drain are self aligned to said floating gate layer.