Patent ID: 6366527
Filing Date: 2002-04-02
Classification: G11C

Abstract:
In combination with a memory chip, a circuit configuration for generating a local output clock signal for controlling an instant at which data are output from an output delay device at an output of a cell array of the memory chip onto a data highway, the circuit configuration comprising:outputs; and a clock ratio compensator formed of two coupled, mutually symmetrical paths for generating the local output clock signal and receiving a differential input clock signal, each of said two coupled, mutually symmetrical paths has switches connected to one of said outputs and a multiplexer formed of at least two programmable signal feed-in points connected to said switches, said multiplexer providing the local output clock signal in a manner dependent on a switch-over signal and is connected through said switches to one of said outputs, said switches being opened and closed in a manner dependent on the differential input clock signal, and an outputting of the data onto the data highway is synchronized with one of whole clock cycles of the data highway and integer fractions of the whole clock cycles.