Patent ID: 8667250
Filing Date: 2014-03-04
Classification: G06F

Abstract:
1. A processor for executing a machine instruction combining data format conversion with at least one vector operation, the processor comprising: hardware control logic to execute processor instructions comprising a vector-load-convert-compute-and-write instruction having a format conversion indicator and a vector register indicator; wherein, in response to the vector-load-convert-compute-and-write instruction, the control logic is to: convert data from a first format to a second format, wherein based at least in part on the format conversion indicator, the first format is a 16 bit floating-point format and the second format is a floating-point format other than the 16 bit floating-point format; perform a vector arithmetic operation, based at least in part on the data in the second format; and save a result of the vector arithmetic operation to a plurality of N elements of a vector register identified by the vector register indicator, wherein N is the number of elements of the plurality and N varies between at least two different pluralities responsive to the vector-load-convert-compute-and-write instruction executed.