Patent ID: 6678811
Filing Date: 2004-01-13
Classification: G06F

Abstract:
Memory controller driver circuitry comprising:a) a data pad; b) N data propagation circuits (N&gE;2); c) a multiplexing stage which provides data to at least Nâˆ’1 of the N data propagation circuits, said multiplexing stage enabling a coupling of a first data input stream to each of the N data propagation circuits when the multiplexing stage is configured in a 1x mode, and said multiplexing stage enabling a coupling of different data input streams to various of the N data propagation circuits when the multiplexing stage is configured in an Mx mode (1d) output merging circuitry which alternately couples the N data propagation circuits to the data pad to thereby generate either a 1x or Mx stream of data bits at the data pad; e) a phase delay circuit; f) a first phase delay multiplexer which enables a coupling of said first data input stream to the phase delay circuit when the first phase delay multiplexer is configured in a 1x mode, and which enables a coupling of an Nth data input stream to the phase delay circuit when the first phase delay multiplexer is configured in an Nx mode; and g) a second phase delay multiplexer which couples an output of a first of the N data propagation circuits, an output of the phase delay circuit, and an input of the output merging circuitry, said second phase delay multiplexer coupling said output of the first of the N data propagation circuits to said output merging circuitry when said second phase delay multiplexer is configured for no write phase delay, and said second phase delay multiplexer coupling said output of the phase delay circuit to said output merging circuitry when said second phase delay multiplexer is configured for a write phase delay.