Patent ID: 6381167
Filing Date: 2002-04-30
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cell blocks arranged in a matrix, each of said plurality of memory cell blocks including a plurality of memory cells arranged in a matrix; a plurality of read data lines shared between a plurality of said memory cell blocks adjacent in a column direction, each read data line being arranged for every L (L is a natural number) memory cell columns to transmit read data read out from said memory cell array; a plurality of write data lines shared between the plurality of said memory cell blocks adjacent in the column direction, each write data line being arranged for every M (M is a natural number different from L) memory cell columns to transmit write data to be written into said memory cell array; a plurality of read column select lines each transmitting a read column select signal to select one said memory cell column out from said L memory cell columns in each said memory cell block; a plurality of write column select lines each transmitting a write column select signal to select one said memory cell column from said M memory cell columns in each said memory cell block; a read select gate provided for every said L memory cell columns in each said memory cell block to transmit said read data of a memory cell column selected in response to said read column select signal to a corresponding one of said plurality of read data lines; and a write select gate provided for every said M memory cell columns in each said memory cell block to transmit said write data transmitted by a corresponding one of said plurality of write data lines to a memory cell column selected in response to said write column select signal.