Patent ID: 7688627
Filing Date: 2010-03-30
Classification: G11C

Abstract:
1. A flash memory array comprising: a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising: a plurality of word lines each electrically connected to the coupling capacitor in each of the memory cells in a respective row; a first set of bit lines each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column; a plurality of high voltage access transistors each electrically connected to a bit line in the first set of bit lines; and a second set of bit lines each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column; wherein various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.