Patent ID: 6319780
Filing Date: 2001-11-20
Classification: H01L,Y10S

Abstract:
A process for forming an integrated circuit comprising at least one low voltage MOS transistor, at least one high voltage MOS transistor, and at least one EPROM cell, the process comprising:a) defining on a silicon substrate at least one low voltage MOS transistor area, at least one high voltage MOS transistor area, and at least one EPROM cell area;b) forming a body region for the at least one low voltage MOS transistor area, a body region for at least one high voltage MOS transistor area, and a body region for the at least one EPROM cell area;c) forming a first dielectric layer on the silicon substrate;d) forming a first conducting layer on the first dielectric layer;e) removing the first conducting layer from the at least one EPROM cell area for forming a floating gate;f) forming source and drain regions in the body region for the at least one EPROM cell area;g) removing the first conducting layer and the first dielectric layer from the at least one high voltage MOS transistor area;h) forming a second dielectric layer on the silicon substrate for the at least one high voltage MOS transistor area, on the floating gate and the first dielectric layer for the at least one EPROM cell area, and on the first conducting layer for the at least one low voltage MOS transistor area;i) removing the second dielectric layer, the first conducting layer and the first dielectric layer from the at least one low voltage MOS transistor area;j) forming a third dielectric layer on the silicon substrate for the at least one low voltage MOS transistor area;k) forming a second conducting layer on the third dielectric layer, and on the second dielectric layer for the at least one EPROM cell area and the at least one high voltage MOS transistor area;l) selectively removing the second conducting layer to form a gate for the at least one low voltage MOS transistor, to form a gate for the at least one high voltage MOS transistor, and to form a control gate for the at least one EPROM cell; andm) forming source and drain regions in the body region for the low voltage MOS transistor area for the at least one low voltage MOS transistor, and in the body region for the high voltage MOS transistor area for the at least one high voltage MOS transistor.