Patent ID: 6819730
Filing Date: 2004-11-16
Classification: H03L,H04J

Abstract:
A filtering method for a digital phase lock loop, comprising:providing a first-in-first-out memory and defining an ideal phase difference value between an input clock and a local recovery clock based upon a half-full memory; calculating a read and write address difference of the first-in-first-out memory to define a phase difference between the input clock and the local recovery clock; comparing the phase difference with the ideal phase difference value; and adjusting the local recovery clock in segments by taking the ideal phase difference value as a center, wherein at the segment where the ideal phase difference value is located, the local recovery clock follows the phase difference with a minimum changing speed, and at other segments, the local recovery clock follows the phase difference with a changing speed increased segment by segment based upon a distance of the phase difference from the ideal phase difference value, and wherein at the segment apart farthest from the ideal phase difference value, the local recovery clock follows the phase difference with a maximum changing speed, and wherein adjusting the local recovery clock in segments comprises calculating an accumulated value by a loop filter, and wherein calculating the accumulated value comprises sampling the phase difference by a phase sampling circuit to generate a phase difference value and calculating the accumulated value in segments by the loop filter based upon a difference between the phase difference sampled value and the ideal phase difference value.