Patent ID: 6134623
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A system for coupling at least a host processor to a memory subsystem and for enabling efficient transfer of data between said host processor and said memory subsystem, said memory subsystem responding to a data block read request for a designated data block by dispatching at least said designated data block and N check data segments for use in determining an integrity of transfer of said data block, said system comprising:a first bus system, operated in accord with a first protocol, coupled to said memory subsystem;controller means coupled to said host processor and responsive to a read request for a first data block from said host processor to create first modified read requests for said first data block and said N check data segments, and transferring said first modified read requests to said first bus system; anda bridge circuit coupled to said first bus system and responsive to said first modified read requests to:i) transfer said first modified read requests to said memory subsystem, andii) transfer said first data block provided in response to said first modified read requests from said memory subsystem, along said first bus system, to said controller means and to discard said N check data segments;said controller means operative to transfer said first data block to said host processor;said bridge circuit, upon receiving further modified read requests for a next data block that is sequential to said first data block, recognizing a continuity of sequential data block addresses with respect to said first modified read requests.