Patent ID: 8971092
Filing Date: 2015-03-03
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array comprising first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, memory cells having a variable resistance element; and a control circuit configured to control voltages of selected first and second wiring lines, the first wiring lines being arranged at a first pitch in a first direction perpendicular to a substrate, the first wiring lines extending in a second direction parallel to the substrate, the second wiring lines being arranged at a second pitch in the second direction, the second wiring lines extending in the first direction, the control circuit configured to change voltages applied to a selected first wiring line of the first wiring lines according to the positions of the selected first wiring lines in the first direction, and the memory cell array further comprising: a selection transistor having a first end connected to one end of the second wiring lines; a select gate line connected to a gate of the selection transistor; and a fourth wiring line connected to a second end of the selection transistor.