Patent ID: 8095843
Filing Date: 2012-01-10
Classification: H03K

Abstract:
1. A method for the acquisition/confirmation of a plurality of m-bit logic signals, m≧1, making it possible to verify for each signal that a current logic state of this signal has remained in this state for at least a non-zero determined confirmation duration, before authorizing an update of an output register with said current logic state, wherein said method is programmable, by means of a parameter memory associated with each signal, making it possible to associate a non-zero confirmation duration with one or more logic states to be confirmed of this signal, and to indicate the logic states of this signal which would not have to be confirmed, the method comprising an endless loop for sequential sampling of said signals, the sampling of each signal activating a loop for the confirmation of the current logic state of the sampled signal, in order to update or not update the output register associated with said current logic state, and in which said confirmation loop uses a dating mechanism supplying a current date, and, for each signal to be processed, there is provided an associated parameter memory and a status memory containing at least two items of information, a first item of information indicating the last logic state seen for said signal, and a date of transition into this state.