Patent ID: 7870177
Filing Date: 2011-01-11
Classification: G06F

Abstract:
1. A method for controlling processing elements in a multiprocessor architecture to provide improved throughout for Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT) computations, the method comprising the steps of: computing, on a multiprocessor architecture including “P” processing elements each butterfly of the first “log distributing the computations of the butterflies in all the subsequent stages of the FFT/IFFT among the “P” processing elements such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together is processed by the same processing element to thereby eliminate the need for inter-processor communication among the processing elements after the computation of the first “log2P” stages of the FFT/IFFT; wherein the distributing of the computation of the butterflies subsequent to the first “log wherein the desired assignment of operand addresses is achieved by deriving the address of the first operand in the operand pair corresponding to the “i