Patent ID: 6586802
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A semiconductor device comprising:an SOI substrate including a silicon layer over a bottom substrate with an insulating layer therebetween; a plurality of active regions which are horizontally arranged in said silicon layer; and a plurality of element isolating trenches, each containing an insulator formed in said silicon layer and extending into said insulating layer, wherein each active region of said plurality of active regions bas a substantially flat bottom surface and includes two opposing side portions each abutting said insulator in a corresponding neighboring element isolating trench of said plurality of element isolating trenches, and a first hollow space and a second hollow space formed respectively directly under bottom surfaces of said two opposing side portions of said each active region, wherein each of said first and second hollow spaces abuts a portion of a top surface of said insulating layer and a side surface of a bottom portion of said insulator in said corresponding neighboring element isolating trench.