Patent ID: 6563730
Filing Date: 2003-05-13
Classification: G11C

Abstract:
A static RAM bit cell for storing binary data, comprising:a storage cell including a plurality of transistors configured to store data; a first word line pass transistor coupled to the storage cell, wherein the first word line pass transistor is also coupled to a word line such that the first word line pass gate transistor can be opened and closed in response to a signal on the word line; a second word line pass transistor coupled to the storage cell, wherein the second word line pass transistor is coupled to the word line such that the second word line pass transistor can be opened and closed in response to a signal on the word line; a first column select pass transistor coupled to the first word line pass transistor wherein the first column select pass transistor is coupled to a column select pass line such that the first column select pass transistor can be opened and closed in response to a signal on the column select line; and a second column select pass transistor coupled to the second word line pass gate transistor wherein the second column select pass transistor is coupled to the column select line such that the second column select pass transistor can be opened and closed in response to a signal on the column select line.