Patent ID: 8252641
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a cell transistor in a memory region of a semiconductor substrate, and forming a logic device in a logic region of said semiconductor substrate; forming a first insulating film for coating both said cell transistor and said logic device over said semiconductor substrate; forming a bit line interconnect groove by selectively processing said first insulating film by etching; forming a first contact hole reaching a first diffusion region of said cell transistor by selectively processing said first insulating film by etching, and forming a bit line contact hole which reaches a second diffusion region of said cell transistor and communicates with said interconnect groove; forming a first contact plug by burying a conductive material in said first contact hole, and forming a bit line contact plug and a bit line, respectively, by burying a conductive material in said bit line contact hole and said interconnect groove; forming a second insulating film for coating said first contact plug and said bit line over said first insulating film; forming a first opening reaching said first contact plug by selectively processing said second insulating film by etching; forming a third insulating film over said second insulating film after forming said first opening; forming a concave portion communicating with said first opening by processing said third insulating film by etching; and forming a capacitor, which is electrically connected to said first contact plug through said first opening, in said concave portion.