Patent ID: 8067281
Filing Date: 2011-11-29
Classification: H01L

Abstract:
1. A method of fabricating a CMOS device, comprising: forming an isolating structure in the substrate to define a first type metal-oxide-semiconductor region and a second type metal-oxide-semiconductor region, wherein a first gate, a first offset spacer and a first lightly-doped region are formed in the first type metal-oxide-semiconductor region, a second gate, a second offset spacer and a second lightly-doped region are formed in the second type metal-oxide-semiconductor region, and a mask layer is respectively formed on the first gate and the second gate; removing a portion of the substrate on two sides of the second gate to form a ditch; filling an epitaxial layer into the ditch; forming a first spacer on a sidewall of the first gate to cover the first offset spacer, and forming a second spacer on a sidewall of the second gate to cover the second offset spacer; performing a doping process to form a first doped region on two sides of the first spacer and form a second doped region on two sides of the second spacer; removing a portion of the first spacer to expose a portion of a surface of the first lightly-doped region, thereby forming a first slimmed spacer; forming a coating layer containing silicon to cover the exposed first lightly-doped region, the first doped region and the second doped region; removing the mask layer; and forming a metal silicide layer on the first gate, the second gate and the silicon layer.