Patent ID: 6352891
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:(a) providing a semiconductor substrate having first and second semiconductor element formation regions; (b) forming a plurality of first gate electrodes of first MOS transistors in said first semiconductor element formation region in a state that said second semiconductor element formation region is masked; (c) forming first source/drain regions of said first MOS transistors in said first semiconductor element formation region in the state that said second semiconductor element formation region is masked; (d) forming first side wall insulating film spacers on side portions of said first gate electrodes in the state that said second semiconductor element formation region is masked; (e) forming a second gate electrode of a second MOS transistor in said second semiconductor element formation region in a state that said second semiconductor element formation region is masked; (f) forming a second insulating film on an entire surface of said substrate; (g) etching back the entire surface of the second insulating film to form second side wall insulating film spacers on side portions of said second gate electrode, while leaving unetched the second insulating film on said first source/drain regions; (h) forming second source/drain regions of said second MOS transistor in said second semiconductor formation region in the state that said first semiconductor element formation region is masked; and (i) selectively forming a silicide layer on said second source/drain regions, wherein said first source/drain regions are masked with said leaving portions of said second insulating film.