Patent ID: 6483763
Filing Date: 2002-11-19
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of CMOS sense amplifiers each of which includes both PMOS and NMOS transistors; a PMOS sense amplifier drive transistor that is provided for every predetermined number of the plurality of CMOS sense amplifiers, connected to sources of PMOS transistors of the corresponding predetermined number of the CMOS sense amplifiers and driven by a sense amplifier driving signal; an NMOS sense amplifier drive transistor that is provided for every predetermined number of the plurality of CMOS sense amplifiers, connected to sources of NMOS transistors of the corresponding predetermined number of the CMOS sense amplifiers and driven by another sense amplifier driving signal; multiple first independent power lines for supplying a given power source to the plurality of CMOS sense amplifiers through the respective PMOS sense amplifier drive transistors; multiple second independent power lines for supplying another given power source to the plurality of CMOS sense amplifiers through the respective NMOS sense amplifier drive transistors; and a plurality of global data lines respectively coupled to the plurality of CMOS sense amplifiers via a plurality of decoding switches for transferring data signals amplified by the plurality of CMOS sense amplifiers to a plurality of main amplifiers, each of the plurality of global data lines being disposed between adjacent ones of the multiple first independent power lines and the multiple second independent power lines.