Patent ID: 7206370
Filing Date: 2007-04-17
Classification: H03L,H04L

Abstract:
1. A clock recovery circuit comprising: a phase comparator which detects a difference in phase between input data and a plurality of sampling clocks, and outputs a detected result as a pair of first frequencies consisting of pulse signals with two values of an advanced signal and a delayed signal; a low-pass filter which reduces the pair of first frequencies in accordance with a frequency reducing control signal which specifies a frequency reduction ratio, and outputs a pair of second frequencies, wherein the low-pass filter has a frequency reduction ratio register which specifies the frequency reduction ratio; a control signal generator which monitors the pair of second frequencies, and generates a phase control signal used to finely adjust phases of the sampling clocks when the advanced signal and the delayed signal are substantially evenly outputted as the pair of second frequencies, and to roughly adjust the phases of the sampling clocks when one of the advanced signal and the delayed signal is larger in number than the other; a phase interpolator which receives the phase control signal, adjusts the phases of the sampling clocks, and outputs the sampling clock adjusted; and a frequency divider which divides one of the sampling clocks having the adjusted phases by a predetermined frequency division ratio and outputs a frequency divided output, and controls operations of the low-pass filter and the control signal generator by using the frequency divided output.