Patent ID: 6252301
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A semiconductor chip assembly comprising:a semiconductor die having a face surface bearing a plurality of contacts thereon;a dielectric substrate wiring layer juxtaposed with the die, the dielectric substrate having a first surface having a plurality of conductive bond pads in rough alignment with the contacts on the die and a second surface having a plurality of conductive terminals, the bond pads being electrically connected to the terminals; anda compliant interposer layer mechanically coupling the face surface of the die and the first surface of the dielectric substrate, wherein the compliant interposer layer is at least partially comprised of a flexible conductive polymer electrically connecting the contacts on the die to respective bond pads on the first surface of the dielectric substrate, whereby the compliant interposer layer is compliant enough to substantially mechanically decouple the shear forces due mainly to the CTE mismatch acting on a resulting chip package during operation.