Patent ID: 6507928
Filing Date: 2003-01-14
Classification: G06F,H03M

Abstract:
For use in a data processor, a cache memory comprising:a first static random access memory (SRAM) capable of receiving on a plurality of inputs up to N incoming bytes of data and storing said up to N incoming bytes of data in a plurality of N-byte addressable locations, wherein M incoming bytes of data may be written in each of said plurality of N-byte addressable locations during a write operation, and wherein M written bytes of data and Nâˆ’M unwritten bytes of data are output from each N-byte addressable location on a plurality of outputs of said first SRAM during said write operation; and a parity generator coupled to said first SRAM capable of receiving during said write operation said M written bytes of data and said Nâˆ’M unwritten bytes of data and generating therefrom at least one write parity bit associated with said M written bytes of data and said Nâˆ’M unwritten bytes of data.