Patent ID: 6448826
Filing Date: 2002-09-10
Classification: G06F,H03K,H03L

Abstract:
A semiconductor device operating in synchronization with an input clock, comprising:a control clock generating circuit generating a control clock synchronously with said input clock repeating first and second state transitions between a first sate and a second state in a certain period, said control clock generating circuit including a period detecting circuit receiving said input clock and detecting said certain period of said input clock, a first pulse generating circuit activated in response to said first state transition of said input clock to generate a reference clock pulse for which an activation state is maintained for a predetermined set in a accordance with said certain period, a first delay circuit delaying stepwise said reference clock pulse from said first pulse generating circuit to output a plurality of delayed clock pulses, and a second pulse generating circuit generating said control clock based on at least two of said plurality of delayed clock pulses; and an internal circuit performing a predetermined operation in response to said control clock.