Patent ID: 6304499
Filing Date: 2001-10-16
Classification: G11C

Abstract:
An integrated dynamic semiconductor memory, comprising:a plurality of first memory cells combined to form individually addressable normal units;a plurality of second memory cells combined to form individually addressable redundant units for replacing respective ones of said normal units;memory units each associated with redundant units for storing in each case one address of a normal unit to be replaced;a self-test unit,connected to said first memory cells for performing a functional test of said first memory cells at a defined memory-retention time for the contents of said memory cell, and for carrying out an analysis as to which of said normal units are to be replaced by which of said redundant units;connected to said memory units for programming said memory units in accordance with a result of the analysis;configured to increase the memory-retention time following a programming of said memory units; andconfigured to repeat the functional test, the analysis, and the programming of said memory units until all said memory units are programmed.