Patent ID: 7737504
Filing Date: 2010-06-15
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: (a) a semiconductor substrate; (b) a P well, an N well, and an N band region in the semiconductor substrate, wherein the P well comprises a first shallow trench isolation (STI) region and a first doped region, and wherein the N well comprises a second STI region and a second doped region; and (c) a well isolation region sandwiched between and only in direct physical contact with the P well, the N well, the first doped region, the second doped region, and the N band region, wherein a the horizontal bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions, wherein the horizontal bottom surface of the well isolation region is only in contact with the N band region and the N well; wherein when going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function, wherein said well isolation region comprises vertical side surfaces formed entirely perpendicular to a horizontal top surface of said well isolation region and said horizontal bottom surface, and wherein each vertical side surface of said vertical side surfaces consists of a single planer surface.