Patent ID: 6836828
Filing Date: 2004-12-28
Classification: G06F

Abstract:
An instruction cache apparatus using the instruction read buffer, comprising:an instruction read buffer, used to temporarily store an instruction word replied by a bus interface unit; a first cache instruction word memory, used to store the instruction word replied by the bus; a second cache instruction word memory, used to store the instruction word replied by the bus; an instruction hit analysis unit, wherein the instruction hit analysis unit receives an output signal of a programmable counter, after comparing and analyzing with a plurality of tags, outputs an instruction hit signal of the instruction read buffer and an instruction hit signal of the first cache instruction word memory; a first multiplexer, wherein the first multiplexer receives a plurality of instruction word output signals of the instruction read buffer, and via the control according to a control signal of the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory, writes an instruction line including the instruction word and contained in the instruction read buffer to the first cache instruction word memory, or writes the instruction line into the second cache instruction word memory, or outputs the instruction word contained in the instruction read buffer directly to a second multiplexer, wherein the second multiplexer, connected to the first cache instruction word memory and the second cache instruction word memory and the instruction read buffer, receives and reads the expected instruction word from the first cache instruction word memory or the second cache instruction word memory or the instruction read buffer according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory.