Patent ID: 6271567
Filing Date: 2001-08-07
Classification: H01L

Abstract:
An integrated circuit with junction isolation comprising:a substrate having a first conductivity type;at least one first and at least one second DMOS power transistors formed in respective first and second regions of a second conductivity type on said substrate, said at least one first DMOS power transistor being connected to a voltage supply and said at least one second DMOS power transistor being connected to ground;at least one circuit formed in a third region on said substrate, said at least one circuit being sensitive to oversupply and belowground effects induced by said at least one first and at least one second DMOS power transistors; anda belowground protection circuit for controlling the belowground effects induced by said at least one second DMOS power transistor;the second region being interposed between the third region and the first region and having a predetermined shape so that the oversupply effects induced by said at least one first DMOS power transistor in the first region to said at least one circuit in the third region are attenuated by a layout separation resulting from the predetermined shape of the interposed second region.