Patent ID: 6344371
Filing Date: 2002-02-05
Classification: H01L,H05K,Y10T

Abstract:
A method for forming a dimensionally stable core for a chip package, said method comprising the steps of:a) forming a metal core with clearances therein; b) placing a first dielectric layer on a top surface of the metal core and placing a second dielectric layer on a bottom surface of the metal core, said first and second dielectric layers having top and bottom surfaces, respectively, said first and second dielectric layers each comprising an expanded polytetrafluoroethylene material having an initial void volume and a mean flow pore size, a mixture substantially evenly distributed throughout said initial void volume of said expanded polytetrafluoroethylene material, said mixture containing a particulate filler and an adhesive resin, said particulate filler being a collection of individual particles having an average particle size, wherein a ratio of said mean flow pore size to said average particle size is greater than about 1 4; and c) placing a metal cap layer on each of, and in direct contact with, the top surface of the first dielectric layer and the bottom surface of the second dielectric layer.