Patent ID: 8722478
Filing Date: 2014-05-13
Classification: B82Y,H01L

Abstract:
1. A method to provide a transistor or memory cell structure comprising: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material on the Si material by growing a Si/Si1-xGex superlattice on the lower Si substrate and creating a Si/Si1-xGex fin from the superlattice; exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region, wherein the second projection is a multilevel core structure, the center region including a plurality of center subregions comprising respective floating nanowires, and the covering region including an insulation covering surrounding the nanowires and electrically insulating each of the nanowires.