Patent ID: 6553430
Filing Date: 2003-04-22
Classification: G06F

Abstract:
A computer system, comprising:a processing subsystem including a plurality of processing nodes interconnected via coherent communication links, and wherein one of the processing nodes comprises a host bridge; an input/output (I/O) node coupled to the processing node including the host bridge via a non-coherent communication link; wherein the host bridge is configured to generate a second posted write command within the processing subsystem in response to a first posted write command received from the I/O node; and wherein the host bridge is configured to respond to: (i) a flush command received from the I/O node, wherein the flush command is issued to ensure that previously-issued posted write commands have reached a point of coherency in the processing subsystem, and (ii) a first target done response received from within the processing system and corresponding to the second posted write transaction, by issuing a second target done response to the I/O node, the second target done response corresponding to the flush command.