Patent ID: 8681919
Filing Date: 2014-03-25
Classification: H03D,H03L

Abstract:
1. A phase detection system, the system comprising: a phase detector configured to determine a phase difference between a data stream and a first control signal; a numerically controlled oscillator configured to generate the first control signal responsive to a second control signal; a memory device comprising a plurality of memory cells correlated with a cycle of the data stream, wherein the memory device is configured to increment a current memory cell of the plurality of memory cells according to a clock signal synchronized with the data stream; an attenuator configured to attenuate the phase difference and generate an attenuated phase difference; and a first adder coupled to the memory device, wherein the first adder is configured to generate a first sum of the attenuated phase difference and a value read from the current memory cell according to the clock signal synchronized with the data stream, wherein the first adder is configured to store the first sum in the current memory cell.