Patent ID: 8289261
Filing Date: 2012-10-16
Classification: G02F,G09G,G11C

Abstract:
1. A gate driving circuit comprising a shift register having a plurality of stages dependently connected to one another, wherein each stage comprises: a pull-up unit to output a first clock signal as a gate signal in response to a signal of a first node, the first node to receive a first input signal; a pull-down unit to discharge the gate signal to a gate-off voltage in response to a second input signal; a discharging unit to discharge the signal of the first node to the gate-off voltage in response to the second input signal; a holding unit to maintain the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal; and wherein the holding unit comprises a transistor having a gate electrode to receive the delay signal of the first clock signal, a drain electrode connected to the first node, and a source electrode connected to a gate line.