Patent ID: 6762626
Filing Date: 2004-07-13
Classification: H03D

Abstract:
An apparatus comprising:at least one of: a first storage unit operable for sampling a first data stream in response to a first clock; and a second storage unit operable for sampling a second data stream in response to a second clock, wherein said second data stream comprises a delayed data stream derived from said first data stream; a third storage unit operable for sampling said first data stream in response to said second clock, wherein said first clock comprises a delayed clock derived from said second clock; and at least one of: a first comparison logic operable for receiving sampled data from said first storage unit and sampled data from said third storage unit, an output of said first comparison logic having a first logic state when said sampled data from said first storage unit and sampled data from said third storage unit compare, and a second logic state when said sampled data from said first storage unit and sampled data from said second storage unit miscompare; and a second comparison logic operable for receiving sampled data from said second storage unit and sampled data from said third storage unit, an output of said second comparison logic having a first logic state when said sampled data from said second storage unit and sampled data from said third storage unit compare, and a second logic state when sampled data from said second storage unit and sampled data from said third storage unit miscompare.