Patent ID: 7428693
Filing Date: 2008-09-23
Classification: H03M,H04L

Abstract:
1. An error-detecting decoding apparatus for applying error-detecting processing to an input data string to which parity bits have been appended and detecting error in the input data string, comprising: data segmenting means for segmenting said input data string into a plurality of sub-data strings; dividing means for dividing the segmented sub-data strings by a generator polynomial and calculating first remainders; converting means for applying conversion processing, which conforms to a segmentation position of the sub-data strings, to said first remainders on a per-remainder basis; combining means for combining the converted values, which have been obtained by said conversion processing, and outputting parity bits; and an error detector for detecting whether or not input data is erroneous depending upon whether said parity bits output from the combining means and said parity bits that have been appended to the input data coincide, wherein data strings are obtained by appending a single “0” to the ends of said segmented sub-data strings and divided by said generator polynomial, the remainders of the division being adopted as second remainders, and if a transformation matrix for converting said first remainders to the second remainders is represented by matrix A and the segmentation position of said sub-data string is an Sth bit, then said converting means executes said conversion processing by multiplying a matrix A