Patent ID: 6770926
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A semiconductor device comprising:a first metal wiring on a semiconductor substrate serving as a first electrode of a metal-insulator-metal (MIM) capacitor; a dielectric film pattern on the first metal wiring; a first via-contact plug on the dielectric film pattern contacting the first metal wiring; an interlayer insulation film having a plurality of second via-contact plugs in a parallel array structure, the plurality of second via-contact plugs contacting the dielectric film pattern and serving as a second electrode of the MIM capacitor, wherein a width of the first via-contact plug is greater than a width of the plurality or second via-contact plugs; and a second metal wiring formed on the interlayer insulation film to contact the first via-contact plug and the plurality of second via-contact plugs.