Patent ID: 6255154
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising a gate electrode patterned on a gate insulating film on a first conduction type semiconductor; a first conduction type body region formed adjacent to the gate electrode; a second conduction type source region and a channel region which formed within said first conduction type body region; a drain region formed apart from said first conduction type body region; and a second conduction type drift region formed between the channel region and drain region so as to be shallow below the gate electrode and deep in the vicinity of the drain region,wherein forming said first conduction type body region comprises the steps of forming the gate electrode with a tapered side wall such that the gate electrode becomes narrower toward the top, and implanting first conduction type impurities by using said gate electrode as a mask, whereby some of the impurities penetrate below the gate electrode based on its tapered shape.