Patent ID: 6629205
Filing Date: 2003-09-30
Classification: G06F

Abstract:
A cache memory system comprising:a cache controller; and a cache memory coupled to said cache controller for storing a plurality of cache lines, wherein said cache memory includes a plurality of memory sections, wherein each of said memory sections is separately addressable through separate address lines couple to said cache controller; wherein said cache controller is configured to store a portion of each of said plurality of cache lines in each of said plurality of memory sections, and wherein said cache controller is further configured to control accesses to said cache memory such that a first set of address tags corresponding to a first subset of said plurality of cache lines is stored in a first of said plurality of memory sections and such that a second set of address tags corresponding to a second subset of said plurality of cache lines is stored in a second of said plurality of memory sections; and wherein each of said plurality of cache lines includes a tag field to store a corresponding address tag and a data field to store corresponding data.