Patent ID: 9204158
Filing Date: 2015-12-01
Classification: H04N

Abstract:
1. A hardware multi-standard video decoder device comprising: a hardware command parser configured to: wherein said hardware command parser is operable to activate said first subset of hardware decoding blocks and said second subset of hardware decoding blocks, and deactivate hardware decoding blocks not involved in decoding said first video stream and said second video stream, wherein said hardware command parser is operable to deactivate one or more hardware decoding blocks that were previously activated based on the one or more hardware decoding blocks not being involved in decoding a portion of said first video stream and a portion of said second video stream, and wherein said hardware command parser is operable to deactivate hardware decoding blocks within one stage of said multiple stage macroblock level pipeline if no data of said interleaved video data is received at said stage, and wherein the hardware multi-standard video decoder device further comprises a hardware post-processing block for post-processing a decoded video stream, wherein said hardware command parser is further configured to deactivate said plurality of hardware decoding blocks if said interleaved video data received at said hardware command parser is a decoded video stream such that said hardware post-processing block performs said postprocessing operation on said decoded video stream.