Patent ID: 7646650
Filing Date: 2010-01-12
Classification: G06F,G11C

Abstract:
1. A buffer component located on a memory module having a plurality of memory components, comprising: a first data interface for receiving an item of access information in accordance with a data transmission protocol, wherein the access information includes address, clock, control and command signals; a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of memory components from the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signal; and a control unit configured to apply the address and command signals to the plurality of memory components during a first clock period of the clock signal and to apply the control signal for activating the group of the plurality of memory components, to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the respective memory components of the group of the plurality of memory components.