Patent ID: 6282556
Filing Date: 2001-08-28
Classification: G06F

Abstract:
A pipelined data path circuit comprising:a pipelined partitioned multiplier circuit receiving a multiply instruction designating first and second operands and for generating, with two clock cycle latency, a result based on said first and second operands, said pipelined partitioned multiplier circuit operable in a first mode to perform four simultaneous 32.times.32 bit multiplications generating four 64-bit results, operable in a second mode to perform eight simultaneous 16.times.16 bit multiplications generating eight 32-bit results and operable in a third mode to perform sixteen simultaneous 8.times.8 bit multiplication operations generating sixteen 16-bit results; andpipelined logic circuitry to execute a sum of absolute differences instruction which designates a first and a second operand, wherein said pipelined logic circuitry computes a result sum with two clock cycle latency and wherein said sum of absolute differences instruction and said multiply instruction are executed with one clock cycle throughput due to pipelining.