Patent ID: 9170955
Filing Date: 2015-10-27
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a cache memory including a plurality of entries each to store data and metadata associated with the data, each entry including a first metadata field to store a multi-bit replacement state indicator to indicate one of a plurality of levels of suitability of the data for replacement, wherein multiple ways of a set can be at the same level of the plurality of levels; and control logic coupled to the cache memory to store the replacement state indicator when the data is stored in the entry and to update the replacement state indicator of a first way of a set when second data is to be written into a second way of the set, wherein the control logic is to store a replacement state indicator of a highest level of the plurality of levels responsive to a first user-level instruction that encodes a type of operation and a replacement state indicator of the highest level to indicate that the corresponding data is to be strongly resident, and store a replacement state indicator of a lowest level of the plurality of levels responsive to a second user-level instruction that encodes a type of operation and a replacement state indicator of the lowest level to indicate that the corresponding data is streaming data.