Patent ID: 8659336
Filing Date: 2014-02-25
Classification: G06F,H03K,H03L,H04L

Abstract:
1. An electronic circuit comprising: an apparatus for synchronising a plurality of interrupts to a common clock domain, each interrupt being as asynchronous signal indicating a need for attention, a processor, and an interrupt controller that receives the synchronised interrupts from the apparatus and sends the synchronised interrupts to the processor, the apparatus comprising: a plurality of signal synchronisers, at least one of the signal synchronizers receiving a respective one of the interrupts in a clock domain as an input signal that is different than a clock domain of one of the interrupts being received by another of the signal synchronizers; each of the signal synchronisers comprising a first flip flop and a second flip flop arranged in series with the first flip flop such that output of the first flip flop is directed to the second flip flop; the first flip flop of each of the signal synchronisers having an input at which the input signal is received and the second flip flop having an output, each of the signal synchronisers being operable to synchronise the input signal received at the input of the first flip flop with a clock signal of a common clock domain received at an input of both of the first and second flip flops of the signal synchroniser to provide an output signal at the output of the second flip flop that is synchronised to the common clock domain such that the input signals received by all of the signal synchronisers are synchronised to the common clock domain; each of the signal synchronisers being connected to a respective first gate arrangement such that the input to the first flip flop of the signal synchroniser is also provided to a first input of the first gate arrangement and the output of the second flip flop of the signal synchroniser is connected to a second input of the first gate arrangement, the first gate arrangement comprising an exclusive-OR gate and operating to provide an output signal only if (i) there is an input signal on the first input and no input signal on the second input of the first gate arrangement or (ii) there is an input signal on the second input and no input signal on the first input of the first gate arrangement; and the outputs of each of the first gate arrangements being connected to respective inputs of a second gate arrangement, the second gate arrangement being operable to provide an output signal if there is an input signal on any of its inputs; the output of the second gate arrangement being connected to a third gate arrangement to gate the clock signal passed to the signal synchronisers such that the clock signal to the signal synchronisers is only enabled when there is a change to the state of a signal received at the input of at least one of the signal synchronisers.