Patent ID: 6172932
Filing Date: 2001-01-09
Classification: G11C

Abstract:
An on-chip voltage generating device for a semiconductor memory comprising:an oscillating means for outputting a clock pulse of a certain frequency in accordance with a self refresh signal;a first on-chip voltage detecting means for detecting a level of an on-chip voltage during an active mode, the first on-chip voltage detecting means being controlled by a memory activating signal;a second on-chip voltage detecting means for detecting a level of the on-chip voltage during stand-by mode, the second on-chip voltage detecting means being controlled by the clock pulse from the oscillating means;a first on-chip voltage generating means for outputting the on-chip voltage in response to an output signal from the first on-chip voltage detecting means; anda second on-chip voltage generating means for outputting the on-chip voltage in response to an output signal from the second on-chip voltage detecting means;wherein the second on-chip voltage detecting means detects the level of the on-chip voltage when the self refresh signal is disabled, and is turned on/off periodically in response to the clock pulse when the self refresh signal is enabled during stand-by mode.