Patent ID: 7328384
Filing Date: 2008-02-05
Classification: G01R

Abstract:
1. A method for providing an identifier for an integrated circuit, comprising; writing data to memory of the integrated circuit; wherein the integrated circuit is a field programmable gate array (FPGA) and the writing data to memory of the integrated circuit comprises loading configuration data into configuration memory cells of the FPGA that controls interconnect multiplexors and forms paths through multiple interconnect multiplexors of the FPGA; identifying defects based upon the writing of the data; wherein the identifying includes generating a set of bits that identifies cells of the memory that are defective; the identifying defects based upon the writing of the data further comprises checking signals transmitted on the paths through the multiple interconnect multiplexors and identifying each path failing to transmit a signal; deriving an identifier for the integrated circuit using the identification of the defects; wherein the deriving includes generating a value from the set of bits that identifies defective memory cells, wherein the value is represented with fewer bits than the set of bits; and wherein the deriving an identifier for the FPGA using the identification of the defects comprises generating an identifier for the FPGA using the identification of each path failing to transmit a signal; and storing the value.