Patent ID: 7449744
Filing Date: 2008-11-11
Classification: H01L

Abstract:
1. An electrically alterable non-volatile memory device provided between a first deep trench isolation region and a second deep trench isolation region, each deep trench isolation region being filled with a dielectric material, comprising: a first semiconductor layer being doped with a first dopant of a first conductivity type in a first concentration; a second semiconductor layer adjacent the first semiconductor layer, the second semiconductor layer being doped with a second dopant of a second conductivity type opposite the first conductivity type, the second semiconductor layer further having a top side; first and second diffusion regions embedded in the top side of the second semiconductor layer spaced apart from each other by a first channel, wherein the first diffusion region is formed adjacent to and along the length of the first deep trench isolation region and the second diffusion region is formed adjacent to and along the length of the second deep trench isolation region, each diffusion region being doped with dopants of the first conductivity type in a second concentration greater than the first concentration; a floating gate disposed above the first channel region and separated therefrom by a first insulator region; and a control gate disposed above and electrically isolated from the floating gate; wherein the first and second diffusion regions are self-aligned to edges of the floating gate, and wherein the first and second deep trench isolation regions each have a width that is less than the minimum feature size.