Patent ID: 6087709
Filing Date: 2000-07-11
Classification: H01L

Abstract:
An integrated circuit comprising:a semiconductor substrate;at least one trench formed in the semiconductor substrate so that the surface of the semiconductor substrate has at least two high regions and at least one low region, the at least one low region defining the at least one trench;an insulation layer substantially filling the at least one trench, the insulation layer having a polished upper surface; andthe at least two high regions defining peripheral regions of the semiconductor substrate and extending along the peripheries of the at least one trench of the semiconductor substrate so that an upper surface of the substantially filled at least one trench and the peripheral regions thereof in combination provide a substantially planar surface and so that the polished upper surface of the insulation layer substantially filling the at least one trench of the substrate is substantially devoid of dishing and so that corners of the peripheral regions extending along the peripheries of the at least one trench have relatively sharp edges and are substantially devoid of corner erosion.