Patent ID: 8745552
Filing Date: 2014-06-03
Classification: G06F,H01L

Abstract:
1. A method comprising: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one; for at least one set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, inserting at least N−1 stitches in each polygon within that set of polygons to divide each polygon within that set into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other, the parts of each stitched polygon are assigned to respective photomasks according to a sequence, and within each of the sets of polygons, each polygon has the same sequence, and each polygon has a different sequence offset from an adjacent one of the set of polygons; and storing data representing assignment of each of the parts in each set to respective photomasks in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.