Patent ID: 8554991
Filing Date: 2013-10-08
Classification: G11C

Abstract:
1. An interface for a dynamic random access memory (DRAM), comprising: an interface element coupled to a DRAM chip using a first planar attachment structure comprising microbumps, a first plurality of microbumps in the first planar attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second plurality of microbumps in the first planar attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element located over and situated within a periphery of the DRAM chip, the DRAM chip being located over and situated within a periphery of a DRAM package, the interface element configured to convert serial address information to parallel address information, convert serial data to parallel data and convert parallel data to serial data.