Patent ID: 7064979
Filing Date: 2006-06-20
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being connected to one of the row lines, the memory cells in the same column being connected to one of the column lines; a row decoder, connected to the row lines, for selecting the row line; a column decoder for selecting the column line; and means for latching data, wherein the memory cell is programmed in accordance with the latched data of the means for latching data, after the memory cells, which are programmed, have been set at the same logic level; wherein, when the data is latched by the means for latching data, the memory cells, which are programmed, have been set at the same logic level.