Patent ID: 8949479
Filing Date: 2015-02-03
Classification: G06F,Y02D

Abstract:
1. An information processing apparatus comprising: a wide IO memory device stacked over an SoC die that includes a CPU; a plurality of functional modules configured to each execute a separate function; a specifying unit configured to, upon being instructed to execute a function, specify one or more available memory channels based on a status of use of a plurality of memory channels corresponding to a plurality of memories included in the wide IO memory device; an evaluation unit configured to, for each of a plurality of memory channel groups composed of possible combinations of the memory channels specified by the specifying unit, evaluate power consumption of the wide IO memory device in a case where the memory channel group is used at an operation voltage and an operation frequency that correspond to a number of memory channels in the memory channel group and a data transfer rate needed for execution of the function; and a selection unit configured to select, out of the plurality of memory channel groups, a memory channel group for which power consumption of the wide IO memory device is lowest, as a memory channel group to be used by the functional module corresponding to the function.