Patent ID: 8970466
Filing Date: 2015-03-03
Classification: G09G

Abstract:
1. A timing controller, comprising: a frequency change sensing unit configured to measure a length of an (n−1)th frame period and a length of an nth frame period, where n is a natural number equal to or greater than 2, and output timing signals of a low logic level when a difference between the length of the (n−1)th frame period and the length of the nth frame period is greater than a predetermined first threshold value; a scan timing control signal output unit configured to output a scan timing control signal for controlling a scan driving circuit of a display panel based on the timing signals output from the frequency change sensing unit; and a data timing control signal output unit configured to control a data driving circuit of the display panel and a polarity of a data voltage based on the timing signals received from a host computer, wherein the timing signals include a data enable signal indicating whether or not data having a predetermined frequency exists, a main clock having a predetermined frequency, and an internal clock having a predetermined frequency. wherein when a count value of the number of data enable signals generated during the (n−1)th frame period and a count value of the number of data enable signals generated during the nth frame period are equal to or greater than a predetermined second threshold value, the frequency change sensing unit outputs the timing signals without changes in the timing signals.