Patent ID: 6405324
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A memory device, comprising:an array of memory cells, at least one of the memory cells being a live memory cell and at least one of the memory cells being a dormant memory cell; a storage circuit coupled to the array of memory cells; a write circuit coupled to the array of memory cells and operable to receive write data and couple the write data to the array of memory cells; a read circuit coupled to the array of memory cells and operable to receive read data from the array of memory cells and to couple the read data from the read circuit; an addressing circuit coupled to the array of memory cells, the addressing circuit being operable to receive a memory address and access at least one of the memory cells in the array corresponding to the received memory address; and a control circuit coupled to the array of memory cells, the write circuit, the read circuit, the addressing circuit and the storage circuit, the control circuit being operable to enable the write circuit to write data to the addressed memory cell if the addressed memory cell is a live memory cell, to enable the write circuit to write data to the storage circuit if the addressed memory cell is a dormant redundant memory cell, to enable the read circuit to read data from an addressed memory cell if the addressed memory cell, and to enable the read circuit to read data from the storage circuit if the addressed memory cell is a dormant redundant memory cell so that read data is provided by the memory cell if the memory cell is a live memory cell and the read data is provided by the storage circuit if the memory cell is a dormant redundant memory cell.