Patent ID: 7460401
Filing Date: 2008-12-02
Classification: G11C

Abstract:
1. A method for checking a state of a set of memory cells of a memory including memory cells arranged in a memory array according to word lines and according to bit columns transverse to the word lines, row and column decoders for selecting a memory cell, and a sense amplifier for supplying a unique signal representative of a conductive or non-conductive state of one the memory cells, the memory cells of a bit column being coupled to a common bit line, each memory cell having a floating-gate transistor and an access transistor coupled to the floating-gate transistor, the method comprising: selecting at least one word line; selecting several bit lines so that all of the memory cells, each having the floating-gate transistor and the access transistor coupled to the floating-gate transistor, coupled to the selected bit lines and belonging to the selected word lines are selected; coupling the sense amplifier simultaneously to all of the selected bit lines; and supplying by the sense amplifier a global state of all of the memory cells coupled to said selected bit lines to which the sense amplifier is coupled, if the memory cells coupled to said selected bit lines are all simultaneously in said non-conductive state.