Patent ID: 6809973
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A word line repair circuit in a flash memory device, comprising:a main cell array in which a plurality of cell are classified in a I/O block unit; a redundancy cell array consisting of repair blocks in which the number of word lines is equivalent to the number of columns constituting the I/O block and the number of cells connected to the word line is equivalent to the number of the I/O block; a CAM cell array for storing information including information on a fail word line of the main cell array and connection information on the repair block instead of the fail word line; a word line voltage switching unit for transferring a word line voltage applied to the fail word line to the redundancy cell array according to information on the fail word line; and a word line select means enabled by the connection information, for selecting a word line of the repair block corresponding to a column of the I/O block according to the column select signal of the main cell array and then applying the word line voltage to the selected word line, wherein data to be stored through the fail word line are sequentially stored through a corresponding column of the repair block in a I/O block unit, thereby repairing the fail word line.