Patent ID: 6518652
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A semiconductor package comprising:a semiconductor chip, a die pad, a die bonding material fixing the semiconductor chip to the die pad, lead-on-chip (LOC) inner leads having tips spaced from and extending across the semiconductor chip, standard inner leads, respective metal wires connecting the tips of the LOC inner leads to electrode pads on the semiconductor chip and tips of the standard inner leads to electrode pads on the semiconductor chip, a sealing resin encapsulating the semiconductor chip, the die pad, the tips of the LOC and the standard inner leads, and the metal wires, and respective outer leads extending successively from the LOC inner leads and the standard inner leads and protruding outwardly from the sealing resin, wherein the LOC inner leads and the standard inner leads are co-planar.