Patent ID: 7848367
Filing Date: 2010-12-07
Classification: H04J,Y10S

Abstract:
1. A deserializer comprising: an input receiver circuit for receiving an input data signal and for adjusting said input data signal, said input receiver circuit comprising: a clock and data recovery circuit (CDR) coupled to said input receiver circuit, said CDR for recovering clock and data signals; a demultiplexing circuit coupled to said CDR, said demultiplexing circuit for receiving one or more data channels from said CDR and splitting said one or more data channels into a first set of data channels; a serdes framer interface (SFI) circuit coupled to said demultiplexing circuit, said SFI circuit for generating a reference channel, for generating a second set of data channels based on said first set of data channels, and for sending said second set of data channels and said reference channel to a framer, wherein said one or more data channels have less number of channels than said first set of data channels, wherein a data rate of said one or more data channels is higher than a data rate of said first set of data channels.