Patent ID: 7535788
Filing Date: 2009-05-19
Classification: G11C

Abstract:
1. A writing dynamic power control circuit comprising: a bit-line (BL) and a bit-line-bar (BLB) complementary to each other; at least one memory cell coupled to both the BL and BLB; a first NMOS transistor having a source, a drain and a gate coupled to the BL, a low voltage power supply (Vss) and a first data signal, respectively; a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal; a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively; a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively; and a third PMOS transistor having a source, a drain and a gate coupled to a chip level high voltage power supply (VDD), the CVDD node and a first power control node, respectively, wherein a write operation is accomplished through applying a data at the first and second data signals, and the first power control node is coupled to the CVDD node.