Patent ID: 8762908
Filing Date: 2014-06-24
Classification: G06F

Abstract:
1. A method of analysis of a circuit design, the method comprising: receiving a netlist of an integrated circuit design having a plurality of data paths; receiving a process corner library; receiving a first design-specific on-chip-variation (DS-OCV) de-rating factor associated with all logic gate circuitry of the netlist of the integrated circuit design, wherein the first design-specific on chip variation de-rating factor accounts for first process variations that are design specific to the netlist of the integrated circuit design, wherein the first design-specific on-chip-variation de-rating factor is determined by at least comparing timing results of a static timing analysis and timing results of a statistical static timing analysis of at least one data path of the plurality of data paths; with a processor, performing a static timing analysis of the entire netlist or portions thereof in response to the process corner library and the first design-specific on chip variation de-rating factor, wherein the static timing analysis generates design specific timing results of the netlist accounting for design-specific on-chip-variation; and outputting the design specific timing results associated with the first design-specific on-chip-variation (DS-OCV) de-rating factor.