Patent ID: 7684968
Filing Date: 2010-03-23
Classification: G06F

Abstract:
1. A processor-implemented method for generating a hybrid simulation model for a design block in an electronic system, comprising: reading a first high-level modeling language description of a data path function, wherein the first high-level modeling language description of the data path function is without a control function that provides a cycle-accurate simulation of the data path function; reading a hardware description language (HDL) specification of the design block, wherein the HDL specification of the design block includes an HDL description of the control function and an HDL description of the data path function; converting the HDL specification of the design block to a high-level modeling language description of the design block, wherein the high-level modeling language description of the design block includes a second high-level modeling language description of the data path function and a high-level modeling language description of the control function; determining the high-level modeling language description of the control function from the high-level modeling language description of the design block, wherein the description of the control function specifies cycle-accurate behavior of the design block without reference to functions in the design block that transform data; and combining the high-level modeling language description of the control function in the high-level modeling language with the first high-level modeling language description of the data path function into a bit-true and cycle-accurate hybrid simulation model in the high-level modeling language, wherein the first high-level modeling language description of the data path function is a bit-true specification of functions of the design block that transform data.