Patent ID: 7627033
Filing Date: 2009-12-01
Classification: H03M,H04N

Abstract:
1. A video encoder device that implements a model-based rate control mechanism for encoding of bit planes, the video encoder device comprising: one or more processors; and one or more processor-accessible storage media storing processor-executable instructions for implementing a plurality of modules for implementing the model-based rate control mechanism for encoding of bit planes, the plurality of modules comprising: a pre-encoding module for accepting a current bit plane and a model parameter, the model parameter reflecting a less probable symbol (LPS) reduction ratio with respect to bits of a bit plane and a bit-count reduction ratio due to bit plane encoding, wherein the pre-encoding module produces a value for a threshold band half-width using the model parameter to determine a desired LPS reduction ratio; an encoding module that receives the value for the threshold band half-width produced by the pre-encoding module, and that also receives the current bit plane for producing an encoded bit plane having a reduced bit count based on the value for the threshold band half-width produced by the pre-encoding module using the model parameter; and a post-encoding module for accepting the encoded bit plane from the encoding module, the encoded bit plane having been encoded responsive to the value for the threshold band half-width produced by the pre-encoding module using the model parameters, wherein the post-encoding module updates the model parameter based on an actual bit-count reduction ratio derived from the encoded bit plane and provides the updated model parameter to the pre-encoding module for use in processing a next bit plane.