Patent ID: 6255214
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method of forming ultra-shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process, comprising the steps of:forming a gate and source/drain junctions by doping a semiconductor material;amorphizing a region of the formed gate and source/drain junctions to form amorphous regions within the formed gate and source/drain junctions including controlling the roughness of an interface between the amorphous regions and the semiconductor material by implanting ions of non-dopant material into the semiconductor material to amorphize the semiconductor material;depositing a cobalt layer over the gate and source/drain junctions; andannealing to form low resistivity cobalt silicide regions on the gate and source/drain junctions;wherein the non-dopant material includes at least one of silicon and germanium and wherein the non-dopant material ions are implanted at a concentration of between about 10.sup.14 ions/cm.sup.2 and about 10.sup.16 ions/cm.sup.2.