Patent ID: 6832270
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A virtual input/output (I/O) interconnect mechanism for use in a computer system having a plurality of I/O devices and a plurality of processing units, wherein I/O devices and processing units are coupled by one or more bridge units, the mechanism comprising:an address decode block, comprising: a multiplexer that multiplexes inputs to produce an address, wherein the address relates to a transaction related to a processor unit, a range register decoder that receives the address and provides a destination address of a module to receive the transaction related to the address, and a reroute module identification block that receives the destination address, the reroute module identification block, comprising: an original module identification that provides an address of one or more original modules in the computer system, and a remapped module identification that provides logical destination module identifications of substitute modules in the computer system, wherein a substitute module replaces functions of an original module in the computer system.