Patent ID: 9158874
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A computer-implemented method for circuit design verification, comprising: performing a process using at least one processor of a computing system, the process comprising: receiving a property defined for a circuit design, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property; performing reachability analysis for the circuit design against a set of cover items through a coverage reachability module coupled with the at least one processor of the computing system; classifying the set of cover items into multiple groups of classified cover items based on results of the reachability analysis through a coverage classification module coupled with the coverage reachability module; and generating a coverage graph indicating an amount of formal verification coverage provided by the property based on a first set of the classified cover items through a coverage information mechanism coupled with the coverage classification module, wherein