Patent ID: 8209139
Filing Date: 2012-06-26
Classification: G01R,H03K

Abstract:
1. A capacitance evaluation circuit, comprising: a capacitive voltage divider comprising a switch circuit, a first capacitor and a second capacitor, wherein the switch circuit is coupled to the first and second capacitors, the switch circuit is controlled by a first clock signal and a second clock signal, which is an inversion signal of the first clock signal, and a voltage variation of a first terminal of the first capacitor is coupled to a first terminal of the second capacitor based on a conduction state of the switch circuit; an analog-to-digital converter (ADC), coupled to the capacitive voltage divider, converting a voltage of the first terminal of the second capacitor into a first digital signal; and a processing module, coupled to the ADC, detecting a capacitance of the second capacitor and a capacitance variation of the second capacitor according to the first digital signal of the ADC and a parameter of the ADC; wherein the ADC comprises: