Patent ID: 7958318
Filing Date: 2011-06-07
Classification: G06F

Abstract:
1. A coherency maintaining device that maintains coherency between a first cache memory and a second cache memory that stores data in the first cache memory, the device comprising: a first memory unit that has a predetermined number of entries and stores part of registration information of data for the first cache memory; a second memory unit that has entries less than the entries of the first memory unit and stores remaining part of the registration information; and a coherency maintaining unit that maintains coherency between the first cache memory and the second cache memory, wherein the part of the registration information stored in the first memory unit includes share information indicating whether data corresponding to a read request received by the second cache memory is shared by a plurality of first cache memories, and upon receipt of a read request, the coherency maintaining unit acquires the share information of data corresponding to the read request and, when the data is shared, the coherency maintaining unit maintains the coherency based on the remaining part of the registration information stored in the second memory unit.