Patent ID: 7872516
Filing Date: 2011-01-18
Classification: H03K

Abstract:
1. An electronic circuit comprising: a precharge circuit, wherein the precharge circuit is coupled to receive a clock signal, wherein the clock signal alternates between a first logic level and a second logic level; a storage circuit, wherein the storage circuit includes a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level; a logic circuit having an output, a first input coupled to receive the clock signal, and a second input coupled to the storage node, wherein the logic circuit is configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level; and a discharge circuit including first and second transistors coupled in series between the storage node and a ground node, wherein the discharge circuit is configured to discharge the storage node when both the first and second transistors are active, wherein the second transistor is configured to be activated responsive to receiving a feedback signal, wherein the storage node is discharged at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node, and wherein the feedback signal is generated responsive to the logic circuit producing the pulse.