Patent ID: 8675002
Filing Date: 2014-03-18
Classification: G06F,G06K,G06T

Abstract:
1. A method comprising: reserving a first range in a first Video RAM (VRAM) area allocated to a first processor and a second range in a second VRAM area allocated to a second processor, wherein the first range and second range correspond to identical ranges of the respective first VRAM area and second VRAM area; reserving a third range in both the first VRAM area and the second VRAM area: storing identical data in both the third range in, the first VRAM area and in the third range in the second VRAM area: storing an identification tag in the first range in the first VRAM area, wherein the identification tag identifies the first processor; and sending instructions to a command buffer, at least one of the instructions being designated for the first processor; and wherein the designated instruction comprises a designation tag that uses the identification tag from the first range in the first VRAM area to designate that the instruction is to be read by the first processor.