Patent ID: 6376345
Filing Date: 2002-04-23
Classification: G09G,H01L,Y10S

Abstract:
A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:(a) forming an insulating film over a first major surface of a wafer; (b) forming a wiring groove in the insulating film by patterning the insulating film; (c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove; (d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove; (e) after step (d), transferring the wafer to a wafer storage portion, while keeping the first major surface of the wafer shaded such that an illuminance of the first major surface of the wafer is 500 lux or less; (f) keeping the first major surface of the wafer wet with flowing water in the wafer storage portion, while keeping the first major surface of the wafer shaded such that an illuminance of the first major surface of the wafer is 500 lux or less; (g) after step (f), performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical, while keeping the first major surface of the wafer shaded such that an illuminance of the first major surface of the wafer is 500 lux or less; and then (h) making the first major surface of the wafer dry, while keeping the first major surface of the wafer shaded such that an illuminance of the first major surface of the wafer is 500 lux or less.