Patent ID: 7796066
Filing Date: 2010-09-14
Classification: H03M

Abstract:
1. A continuous-time sigma-delta analog-to-digital converter (CT SD ADC) comprising: a loop filter having an input resistor-capacitor (RC) network coupled to a differential signal input; a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, the GQD configured to evaluate an input signal provided by the input RC network, compute a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measure the error signal, and compensate for the error signal with sigma-delta noise-shaping; a common mode level adjust circuit coupled to signal inputs of the GQD, the common mode level adjust circuit configured to alter a common mode level of a differential input signal to be substantially equal to a desired common mode level; and a tuning circuit coupled to the GQD and to the common mode level adjust circuit, the tuning circuit configured to provide a compensation voltage to the common mode level adjust circuit based on a difference between the common mode level of the differential input signal and the desired common mode level.