Patent ID: 7653789
Filing Date: 2010-01-26
Classification: G06F

Abstract:
1. A method for reducing coherence traffic in a multiprocessor system by supporting both coherent memory accesses and non-coherent memory accesses, the method comprising: receiving a request to perform a memory access; obtaining a page table entry (PTE) associated with the memory access; determining if the memory access is a coherent memory access or a non-coherent memory access by examining an indicator bit in the PTE, wherein during a coherent memory access, memory is accessed using a cache-coherence protocol, which generates coherence traffic, and wherein during a non-coherent memory access, memory is accessed without performing a cache-coherence operation, which does not generate coherence traffic; if the indicator bit indicates that the memory access is a coherent memory access, performing the memory access using a coherence protocol; and if the indicator bit indicates that the memory access is a non-coherent memory access, performing the memory access without generating coherence traffic, which further involves: