Patent ID: 7476582
Filing Date: 2009-01-13
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, said method comprising the following steps: (a) a step whereby a dummy gate pattern which consists of multiple layers and which possesses a first electroconductive layer as the lowermost layer is formed on a memory cell region and a peripheral transistor region which has been defined above a semiconductor substrate, (b) a step whereby a coating film which covers said dummy gate pattern is formed; (c) a step whereby said coating film is dry-etched in such a way that a gate side wall film will selectively remain on the side plane of said dummy gate pattern; (d) a step whereby an interlayer insulating film is formed blanketwise on the remainder of the structure formed through the preceding processes; (e) a step whereby the surface of said interlayer insulating film is etched back based on the chemical mechanical polish method until the surface of said intermediate insulating film and the surface of said dummy gate pattern become virtually continuous and flat; (f) a step whereby said dummy gate pattern is partially removed in such a way that said dummy gate pattern will be removed from said peripheral transistor region but will remain in said memory cell region and that said gate side wall film will remain in both said memory cell region and said peripheral transistor region; (g) a step whereby a second electroconductive layer is formed blanketwise on the remainder of the structure which has been formed through the preceding processes and which includes the region from which said dummy gate pattern has been removed; and (h) a step whereby the surface of said interlayer insulating film is etched back based on the chemical mechanical polish method until the surface of said interlayer insulating film and the surface of said second electroconductive layer become virtually continuous and planarized.