Patent ID: 6251712
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method for fabricating a CMOS transistor having an n-channel thin film transistor and a p-channel thin film transistor, said method comprising:forming a semiconductor film on a insulating surface;providing said semiconductor film with a catalyst for promoting crystallization thereof;crystallizing said semiconductor film;etching said crystallized semiconductor film to form at least first and second semiconductor islands on an insulating surface;forming a gate insulating film covering each of said first and second semiconductor islands;forming first and second gate electrodes over each of said first and second semiconductor islands respectively with said gate insulating film interposed therebetween;first anodizing each of said first and second gate electrodes to form a first anodic oxide film on side surfaces of each said of said first and second gate electrodes;selectively removing exposed portions of said gate insulating film using each of said first and second gate electrodes and said first anodic oxide film as a mask;removing said first anodic oxide films after said selectively removing said exposed portions of said gate insulating film, in order to expose other portions of said gate insulating film on each of said first and second semiconductor islands;forming a first pair of regions in said first semiconductor island by introducing an n-type impurity to form first source and drain regions in said first semiconductor island wherein said n-type impurity is phosphorous;forming a second pair of regions in said first semiconductor island by introducing said n-type impurity to form lightly doped drain regions in said first semiconductor island, said second pair of the regions in said first semiconductor island being located adjacent to said first pair of the regions in said first semiconductor island;forming a third pair of regions in said second semiconductor island by introducing said n-type impurity;forming a fourth pair of regions in said second semiconductor island by introducing said n-type impurity, said fourth pair of the regions being located adjacent to said third pair of the regions;masking only said first semiconductor island with a resist;inverting a conductivity type of said third pair of regions by introducing a p-type impurity to form second source and drain regions of said second semiconductor island;inverting a conductivity type of said fourth pair of regions by introducing said p-type impurity to form second lightly doped drain regions, to thereby form a CMOS transistor having said n-channel thin film transistor in said first semiconductor island and said p-channel thin film transistor in said second semiconductor island; andactivating said n-type impurity and said p-type impurity in said first and second semiconductor islands so that the catalyst is gettered by said n-type impurity.