Patent ID: 6661053
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A memory cell with a storage transistor, comprising:a semiconductor body having a top surface, a source zone doped from said top surface, a drain zone doped from said top surface, and a trench formed therein between said source zone and said drain zone and having walls, said trench being formed along a longitudinal direction; a junction of said source zone being defined beneath said source zone and intersecting a region of a respective one of said walls of said trench; a junction of said drain zone being defined beneath said drain zone and intersecting region of a respective one of said walls of said trench; a gate electrode on aid top surface of said semiconductor body being disposed in said trench; a dielectric layer isolating said gate electrode from said semiconductor body an acting as a storage medium; and a spacing being defined across said trench between said junctions; said regions of said walls being located where said walls have a cross section transverse to said longitudinal direction with a curve radius equaling at most two-thirds of said spacing.