Patent ID: 6141713
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A bus arbitration apparatus for processing bus requests from M number of bus request units, said bus arbitration apparatus also operating as a highest level hierarchical arbitrator, comprising:Q number of lower level hierarchical arbitrators, each of said lower level hierarchical arbitrators being connected to P number of bus request units, wherein M, Q and P are positive integers greater than 1, each hierarchical arbitrator including,a selector for generating a selection signal based on bus requests from said lower level hierarchical arbitrators and priorities of the lower level hierarchical arbitrators, wherein the selection signal represents a selected lower level hierarchical arbitrator, said selector for generating a bus request from the selected lower level hierarchical arbitrator; anda multiplexer, in response to the selection signal for providing bus cycle information from the selected hierarchical arbitrator;wherein said selector includes,a N-state block, receiving the bus requests, the priorities and a current signal, for generating a next signal representing a selected lower level hierarchical arbitrator, at a next cycle;an OR gate for ORing the bus requests to generate the bus request generated by the selector which is coupled to a higher level hierarchical arbitrator;a control signal generation block, receiving the next signal and a previous control signal from the higher level hierarchical arbitrator, for generating next control signals; anda current signal generation block, receiving the next signal and the previous control signal, for generating the current signal at a falling edge of the previous control signal and for generating the next signal as the selection at a rising edge of the previous control signal.