Patent ID: 8477538
Filing Date: 2013-07-02
Classification: G11C

Abstract:
1. A flash memory device, comprising: a memory cell array comprising a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.