Patent ID: 8269290
Filing Date: 2012-09-18
Classification: B81B,B81C,G01P,H01L

Abstract:
1. A semiconductor device comprising: a first semiconductor substrate having a first surface and a second surface, the first semiconductor substrate including a first element on a first-surface side of the first semiconductor substrate; a second semiconductor substrate having a first surface and a second surface, the second semiconductor substrate including a second element and a wiring part on a first-surface side of the second semiconductor substrate, the second semiconductor substrate attached with the first semiconductor substrate in such a manner that the first surface of the second semiconductor substrate is opposite the first surface of the first semiconductor substrate; a hole provided from the second surface of the first semiconductor substrate to the wiring part on the first-surface side of the second semiconductor substrate through the first semiconductor substrate, the hole having an insulated sidewall; and a drawing wiring part made of a conductive member and filling the hole, wherein the first element is a dynamic quantity sensor element, which includes a movable electrode and a fixed electrode; the second element is an element configured as a control circuit of the sensor element; the first semiconductor substrate includes a silicon-on-insulator substrate having a buried oxide layer; the movable electrode is formed by a sacrifice-layer etching of a part of the buried oxide layer; the movable electrode has a surface that is opposite a surface of the fixed electrode; the movable electrode is movable in a direction perpendicular to the opposite surfaces of the movable and fixed electrodes in accordance with a dynamic quantity applied to the dynamic quantity sensor element; the dynamic quantity sensor element is configured to detect a change in an electrostatic capacity provided between the opposite surfaces of the movable electrode and the fixed electrode for detecting the dynamic quantity; the wiring part includes a third wiring layer and a fourth wiring layer; the third wiring layer is disposed at a first depth from the first surface of the second semiconductor substrate; the fourth wiring layer is disposed at a second depth from the first surface of the second semiconductor substrate; the second depth is deeper than the first depth, increasing depth being in the direction of the second surface of second substrate from the first surface of the second substrate; the drawing wiring part includes a third drawing wiring layer that reaches the fourth wiring layer through a part of the third wiring layer; and the third drawing wiring layer is coupled with the third wiring layer and the fourth wiring layer.