Patent ID: 6025612
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A NAND type compound semiconductor memory comprising:a substrate;a p type fifth semiconductor layer formed on said substrate,a first semiconductor layer formed on said fifth semiconductor layer, a channel being formed by said first semiconductor layer,a plurality of devices formed on said substrate and connected in series to one another, each device including,a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer,an n type third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer,a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer,a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel,a source electrode formed on the first semiconductor layer and electrically connected to said channel, anda drain electrode formed on the first semiconductor layer and electrically connected to said channel;a switch element, connected in series to the plurality of devices, for transferring an externally supplied potential to said devices, anda first control electrode electrically connected to said fifth semiconductor layer.