Patent ID: 7941648
Filing Date: 2011-05-10
Classification: G06F

Abstract:
1. A multithreaded processor comprising: a very long instruction word (VLIW) processor running a first thread of execution and a second thread of execution, wherein each VLIW in a sequence of VLIWs is subset into a first set of instructions associated with the first thread of execution and a second set of instructions associated with the second thread of execution; a plurality of register files having a first portion and a second portion, wherein each register file has write and read ports and is operable to hold a plurality of entries and each entry having a plurality of bits; and a control unit receiving the first set instructions from the first thread of execution and the second set of instructions from the second thread of execution, in response to the control unit receiving the first set of instructions, wherein the control unit configures the addressability of the plurality of register files to access a first set of entries stored in the first portion and in response to the control unit receiving the second set of instructions, the control unit configures the addressability of the plurality of register files to access a second set of entries, wherein for one or more VLIWs of the sequence of VLIWs, an entry spans across the first and second portions.