Patent ID: 8247300
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit including a vertical bipolar transistor, comprising: providing a silicon-on-insulator substrate including a silicon thin film layer disposed over a buried oxide layer; selectively implanting the silicon thin film layer with boron to form a relatively heavily doped p-type buried collector region; forming an epitaxial silicon layer with a relatively lightly doped p-type subcollector region over the silicon thin film layer including over the buried collector region, by first growing a diffusion barrier over the silicon thin film layer through epitaxial growth of silicon in the presence of a source of carbon or silicon-germanium-carbon, and then continuing the epitaxial growth of silicon to define the subcollector region over the diffusion barrier in the absence of the source of carbon or silicon-germanium-carbon; forming a deep trench isolation structure in the epitaxial silicon layer and the silicon thin film layer, down to the buried oxide layer, to surround and isolate a surface region of the epitaxial silicon layer located over the buried collector region; forming a shallow trench isolation structure in the surrounded surface region in the subcollector region of epitaxial silicon layer, down to a depth less than the depth of the diffusion barrier, to provide first and second isolated surface portions in the surrounded surface region; selectively implanting the first isolated surface portion with p-type dopant to form a relatively heavily doped p-type collector sinker structure; forming an n-type doped silicon or silicon-germanium epitaxial layer disposed at the second isolated surface portion to define an intrinsic base region; and forming a relatively heavily doped p-type polysilicon structure over the silicon-germanium epitaxial layer to define an extrinsic emitter.