Patent ID: 7082550
Filing Date: 2006-07-25
Classification: G06F

Abstract:
1. A processor responsive to a clock cycle, comprising: a plurality of base units, each for providing an output signal in response to an input signal; a plurality of mirror units, each for providing an output signal in response to the input signal, the mirror-unit being a duplicate instance of the base-unit; a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle; a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clack cycle; and a non-duplicated-unit in signal communication with a plurality of base units and a plurality of mirror units, the non-duplicated-unit having a comparator for comparing the output signals of the plurality of base and mirror units; wherein the plurality of mirror units are utilized for detecting errors within the processor and are located away from the plurality of base units to improve cycle time with minimal wire congestion.