Patent ID: 6169431
Filing Date: 2001-01-02
Classification: H03K

Abstract:
In combination with a semiconductor component having a first main terminal connected to a first reference potential, a second main terminal connected to a second reference potential via a load, and a control terminal, a drive circuit for driving the semiconductor component, the drive circuit comprising: a control signal generating device generating a control signal for switching the semiconductor component on and off, said control signal generating device having a circuit section operating according to a bootstrap principle and serving for switching on the semiconductor component; a diode having a first terminal connected to the first reference potential and a second terminal; a capacitor device having a first terminal connected to said second terminal of said diode for charging said capacitor device via the first reference potential and a second terminal connected to the second main terminal of the semiconductor component; a series circuit formed of a series resistor and a first controllable NMOS transistor having a control terminal receiving the control signal from said control signal generating device, said series circuit connected between said first terminal of said capacitor device and the second reference potential; a controllable PMOS transistor having a control terminal connected to a junction point between said series resistor and said first controllable NMOS transistor, a first main terminal connected to a junction point between said diode and said capacitor device, and a second main terminal; an NPN bipolar transistor having a collector terminal connected to said first terminal of said capacitor device, an emitter terminal connected to the control terminal of the semiconductor component, and a base terminal connected to said second main terminal of said controllable PMOS transistor; an inverter receiving said control signal from said control signal generating device and outputting an inverted control signal; and a resistor device having a second controllable NMOS transistor with a first main terminal connected to said base terminal of said NPN bipolar transistor, a second main terminal connected to the second main terminal of the semiconductor component, and a control terminal receiving the inverted control signal from said inverter.