Patent ID: 6937494
Filing Date: 2005-08-30
Classification: G11C

Abstract:
1. A memory module comprising: a module substrate; at least one command-address signal register; a plurality of memory chips provided on a top face and under face of the module substrate, each of the plurality of memory chips having a command-address signal terminal with an active-termination circuit; and command-address signal wiring; wherein the command-address signal register is internally wired and connected to the plurality of memory chips; wherein the plurality of memory chips is divided so as to form at least one 1-ranked memory group including two or three memory chips that are provided on one face and the other face of the module substrate and near and adjacent to each other and at least one 2-ranked memory group including two or three memory chips that are provided on one face and the other face of the module substrate and near and adjacent to each other; wherein the 1-ranked memory group is paired with the 2-ranked memory group adjacent thereto so that this pair of memory groups has four or five memory chips; wherein the command-address signal wiring has a T-branch structure and is used for connecting the command-address signal register to the pair of memory groups corresponding thereto; and wherein when access is made, one of the pair of memory groups is used during the access and the other is not used and the command-address signal terminals of the memory chips of the memory group that is not used during the access are actively terminated.