Patent ID: 6407612
Filing Date: 2002-06-18
Classification: H03K

Abstract:
In an integrated circuit device receiving an input signal, the input signal including sporadic irregularities during transitions between high and low signal levels, a circuit for suppressing the irregularities and forwarding an improved input signal without substantially delaying propagation of the input signal to the device, the circuit comprising:a delay element in electrical communication with the input signal, the delay element forwarding to an output node a version of the input signal delayed by a time duration X; and logic means, positioned between the delay element output node and a latch, for selectively forwarding the logical signal level of either of the input signal or the delayed version of the input signal to the latching element, the latch latching a first transition of the input signal, thereby suppressing irregularities in the input signal during the time duration X after the first transition of the input signal.