Patent ID: 6738258
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A power semiconductor module comprising:a first main module electrical connection arranged on a first main surface of the module and a second main module electrical connection arranged on a second main surface of the module wherein the first and second main surfaces of the module are mutually opposite and essentially parallel, and wherein the first main module connection is in the form of an electrically conductive covering panel; an electrically insulating housing which is connected to the covering panel and arranged between the two main module electrical connections; first and second submodules, each submodule including first and second main submodule electrical connections arranged on mutually opposite and essentially parallel main surfaces of the submodule, at least one semiconductor chip having a first main electrode electrically conductively connected to the first main submodule electrical connection and a second main electrode electrically conductively connected to the second main submodule electrical connection; wherein the first and second submodules are arranged alongside one another; the first and second submodules are pressed toward the covering panel by a contact force applied to the first and second submodules; and the first and submodules are electrically connected in series.