Patent ID: 6624667
Filing Date: 2003-09-23
Classification: H03K

Abstract:
A comparator comprising:a first switch provided between an output for a signal voltage and one end of a first capacitor; a first inverter having an input connected to the other end of said first capacitor; a second switch provided between the input and an output of said first inverter; a tri-state inverter having an input connected to the output of said first inverter; a first latch unit having an input connected to an output of said tri-state inverter; a third switch having one end provided between an output of said first latch unit and an input of a second latch unit; a fourth switch provided between an output for a reference voltage and one end of a second capacitor; a fourth inverter having an input connected to the other end of said second capacitor; a fifth switch provided between the input and an output of said fourth inverter; a sixth switch provided between said one end of said first capacitor and said one end of said second capacitor; a seventh switch and a third capacitor connected in series between the input of said first inverter and the output of said fourth inverter; and an eighth switch and a fourth capacitor connected in series between the input of said fourth inverter and the output of said first inverter, wherein: the signal voltage and reference voltage are simultaneously output to said one end of said first capacitor and to said one end of said second capacitor respectively while said seventh and eighth switches are turned on, and further said first switch is turned on to hold a difference voltage between the signal voltage and an offset voltage of said first inverter on both ends of said first capacitor, and said fifth switch is turned on to hold a difference voltage between the reference voltage and an offset voltage of said fourth inverter on both ends of said second capacitor, after the signal voltage and reference voltage are simultaneously output to said one end of said first capacitor and to said one end of said second capacitor respectively, said third, fourth, seventh, eighth switches are turned off while said sixth switch is turned on and said first and fifth switches are turned off to amplify approximately one half voltage of a difference voltage between the signal voltage and reference voltage using said first inverter, and after said first and fifth switches are turned off, said seventh and eighth switches are turned on while said tri-state inverter operates as an inverter to output an output voltage of said first inverter on the output of said tri-state inverter.