Patent ID: 7184294
Filing Date: 2007-02-27
Classification: G11C,H01L

Abstract:
1. A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit; said first memory unit having; a first bit line, one or more first transistors for selection, first sub-memory units each of which is composed of memory cells, and plate lines which are shared between or among the first sub-memory units, and said second memory unit having; a second bit line, one or more second transistors for selection, second sub-memory units each of which is composed of memory cells, and the plate lines which are shared between or among the second sub-memory units, and which are shared with the plate lines which constitute said first memory unit, wherein one of the first sub-memory units and one of the second sub-memory units are formed on a same first insulating layer, another one of the first sub-memory units and another one the second sub-memory units are stacked over the sub-memory units formed on the first insulating layer via a second insulating layer, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, in the first memory unit, a plurality of the first electrodes of the memory cells constituting the first sub-memory unit formed on the first insulating layer are in common and constitute a first common electrode, said first common electrode is connected to the first bit line through one of said first transistors for selection, and the second electrode of each memory cell is individually connected to one of said shared plate lines, in the second memory unit, a plurality of the first electrodes of the memory cells constituting the second sub-memory unit formed on the first insulating layer are in common and constitute a second common electrode, said second common electrode is connected to the second bit line through one of said second transistors for selection, and the second electrode of each memory cell is individually connected to one of said shared plate lines, the memory cells constituting the first sub-memory unit formed on the first insulating layer and the memory cells constituting the second sub-memory unit formed on the first insulating layer have the same thermal history with regard to their production processes, the memory cells constituting the first sub-memory unit formed on the first insulating layer and the memory cells constituting the second sub-memory unit formed on the first insulating layer have the thermal history different from the thermal history of the memory cells constituting the first sub-memory unit and the memory cells constituting the second sub-memory unit formed on the second insulating layer, a first reference potential is provided to the second bit line when data stored in the memory cell constituting the first sub-memory unit formed on the first insulating layer in the first memory unit is read out, a second reference potential is provided to the first bit line when data stored in the memory cell constituting the second sub-memory unit formed on the second insulating layer in the second memory unit is read out, and the first reference potential differs from the second reference potential.