Patent ID: 9147034
Filing Date: 2015-09-29
Classification: G06F

Abstract:
1. A method for operating a data processing system to detect layout errors, said method comprising: receiving a schematic of a circuit, said schematic comprising a plurality of schematic devices, each schematic device being characterized by a unique schematic device name; receiving user input defining a physical layout for said circuit, said physical layout comprising a plurality of layout devices, each layout device being characterized by a unique layout device name; causing said data processing system to generate a graphical representation of said circuit from said physical layout, said graphical representation having one layout device corresponding to each of said plurality of schematic devices, said schematic device name for each schematic device matching said layout device name of a corresponding one of said layout devices; causing said data processing system to generate a first netlist from said graphical representation of said circuit; causing said data processing system to generate a second netlist generated from said schematic; and causing said data processing system to generate a report specifying any differences in said first netlist and second netlist, wherein each schematic device name matches said corresponding one of said layout device names prior to said data processing system generating said first and second netlists.