Patent ID: 7867825
Filing Date: 2011-01-11
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor wafer, the method comprising: forming a first interlayer insulator; forming a first conductive line by patterning a first conductive line material layer formed on the first interlayer insulator; patterning a second interlayer insulator formed on the first conductive line to expose an upper surface portion and a side surface of the first conductive line; forming a second conductive line characterized by an inclined side surface on the exposed upper surface portion and side surface of the first conductive line; forming a first protective layer on the second conducting line; forming a recess region in the first interlayer insulator using first and second etching processes, wherein the first etching process is adapted to form a fuse window using the first protective layer as an etch mask, and the second etching process is adapted to expose a bonding pad, and wherein the recess region defines a scribe line; and forming a second protective layer on the inclined side surface of the first protective layer and on at least one surface of the recess region.