Patent ID: 6791526
Filing Date: 2004-09-14
Classification: G09G

Abstract:
A drive circuit for sequentially supplying a drive voltage to a plurality of output lines, said drive circuit comprising:a first shift register provided with m (where m is an integer of 2 or greater) serially connected bit circuits and designed to shift a drive data input away from the first bit circuit toward the m-th bit circuit on the basis of a clock signal in a first state, and to shift the drive data input away from the m-th bit circuit toward the first bit circuit on the basis of a clock signal in a second state; a first output circuit with m output units that correspond to the bit circuits of the first shift register and that present a first output line with a drive voltage based on data from the bit circuits in the first state; and a second output circuit with m output units that correspond to the bit circuits of the first shift register and that present a second output line with a drive voltage based on data from the bit circuits in the second state.