Patent ID: 6735652
Filing Date: 2004-05-11
Classification: G06F

Abstract:
A detection circuit for detecting the occurrence of a one of a plurality of desired values on a multibit bus, said detection circuit comprising:a random access memory (RAM) receiving a first subset of plural bits of the multibit bus, said random access memory having a plurality of locations addressed by said first subset of plural bits, each of said plurality of locations storing a plurality of bits, said random access memory outputting said plural bits stored at said location addressed by a current value of said first subset of plural bits of the multibit bus, said random access memory storing at a location addressed by said first subset of plural bits of each desired value plural bits corresponding to a second subset of plural bits of said desired value, said second subset of plural bits not overlapping said first subset of plural bits; and a comparator receiving said second subset of plural bits of the multibit bus and said plural bits output by said random access memory, said comparator generating a match output indicating a match whenever each bit of said plural bits output by said random access memory matches a corresponding bit of said second subset of plural bits of the multibit bus.