Patent ID: 9047831
Filing Date: 2015-06-02
Classification: G02F,G09G

Abstract:
1. A liquid crystal display panel, comprising: a plurality of data lines; a plurality of scan lines; a plurality of common electrode lines; a plurality of pixel units coupled to the data lines and the scan lines, wherein each of the pixel units comprises a storage capacitor; a plurality of voltage buffer circuits, wherein each of the voltage buffer circuits comprises an output end, a first input end, a second input end and a third input end, the output end of each voltage buffer circuit is coupled to one of the common electrode lines, the first input end of each voltage buffer circuit is coupled to a first common voltage source, and the second input end of each voltage buffer circuit is coupled to a second common voltage source; and a plurality of common electrode controller units, wherein each of the common electrode controller units comprises an output end, a first input end, a second input end and a third input end, the output end of each common electrode controller unit is coupled to the third input end of one of the voltage buffer circuits, the first input end and the second input end of each common electrode controller unit are respectively coupled to two adjacent scan lines, and the third input end of each common electrode controller unit is coupled to a common electrode controller signal source; wherein each voltage buffer circuit comprises a complementary metal oxide semiconductor switch and a capacitor component, the complementary metal oxide semiconductor switch comprises a high voltage input end, a low voltage input end, a control end and an output end, the high voltage input end of the complementary metal oxide semiconductor switch is coupled to the first input end of the voltage buffer circuit, the low voltage input end of the complementary metal oxide semiconductor switch is coupled to the second input end of the voltage buffer circuit, the control end of the complementary metal oxide semiconductor switch is coupled to the third input end of the voltage buffer circuit, and the output end of the complementary metal oxide semiconductor switch is coupled to the output end of the voltage buffer circuit, and the capacitor component is coupled to the control end of the complementary metal oxide semiconductor switch, and the capacitor component stores the input signal of the control end of the complementary metal oxide semiconductor switch to keep the operation state of the voltage buffer circuit, thereby maintaining a voltage level of the common electrode line.