Patent ID: 8098466
Filing Date: 2012-01-17
Classification: H01L

Abstract:
1. A transient voltage suppressing (TVS) circuit formed in a semiconductor substrate of a first conductivity type comprising: a first doped well of a first conductivity type and a second doped well of a second conductivity type disposed under a top surface in the semiconductor substrate and an inter-well doped region of the second conductivity type disposed between the first doped well and the second doped well immediately below the top surface of the substrate; wherein first doped well further includes a first dope region of the first conductivity type below said inter-well doped region constituting a triggering diode; the second doped well further encompassing a first silicon controlled rectifier (SCR) doped region of the first conductivity type and a second SCR doped region of a second conductivity type immediately below the top surface of the semiconductor substrate wherein the first and second SCR doped regions encompassed in the second doped well above the substrate of the first conductivity type functioning as a silicon controlled rectifier (SCR) electrically connected to and triggered by the triggering diode encompassed in the first doped well disposed next to the SCR in said semiconductor substrate.