Patent ID: 7403411
Filing Date: 2008-07-22
Classification: G11C

Abstract:
1. A radiation tolerant static random access memory (SRAM) cell and deglitching circuit, including: a configuration memory cell storing a configuration bit and comprising a first inverter having an input and an output and a second inverter having an input and an output, the output of the first inverter forming an output of the memory cell and coupled to the input of the second inverter, the output of the second inverter forming a complementary output of the memory cell and coupled to the input of the first inverter; a radiation hardened latch having an output and a complementary output; a first AND gate having a first input coupled to the output of the configuration memory cell, a second input coupled to a write-control line, and an output coupled to the complementary output of the latch; a second AND gate having a first input coupled to the complementary output of the configuration memory cell, a second input coupled to the write-control line, and an output coupled to the output of the radiation hardened latch; a write data line coupled to the output of the configuration memory cell through a first write transistor having a gate coupled to the write control line; and a write complementary data line coupled to the complementary output of the configuration memory cell through a second write transistor having a gate coupled to the write control line.