Patent ID: 6343075
Filing Date: 2002-01-29
Classification: H04Q

Abstract:
A switch, comprising:a first stage having a plurality of first switch circuits, each of said plurality of first switch circuits having a plurality of inputs and a plurality of outputs; a second stage having a plurality of second switch circuits, each of said plurality of second switch circuits having a plurality of inputs, each of which being respectively coupled to one of said plurality of outputs of each of said plurality of first switch circuits, and a plurality of outputs, a number of said plurality of second switch circuits equaling N, where N is an integer other than a power of 2; and a third stage having a plurality of third switch circuits, each of said plurality of third switch circuits having a plurality of inputs and a plurality of outputs, each of said plurality of inputs of each of said plurality of third switch circuits being coupled to a respective one of said plurality of outputs of each of said plurality of second switch circuits, wherein each of said plurality of outputs of said plurality of first switch circuits, outputs of respective one of a plurality of data signals, said data signals being time-division multiplexed, wherein said each of said plurality of data signals includes a plurality of groups of time slots, each of said plurality of groups further including a plurality of subgroups of time slots, and wherein at least some of said plurality of second switch circuits are configured to be represented as n logical sub-switch circuits where n is a power of 2, each of said sub-switch circuits being configured to direct selected subgroups of time slots among different groups to one of said plurality of outputs of said plurality of second switch circuits.