Patent ID: 6728159
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A multibank DRAM macro allowing concurrent operations to independent banks, said macro comprising:(a) a plurality of DRAM memory banks, each bank respectively comprising: (i) an array of DRAM memory cells, (ii) bitlines and wordlines, respectively defining columns and rows of the array, (iii) a dedicated row address decoder circuit, (iv) dedicated spare rows and columns for redundancy, (b) at least one column address decoder circuit shared by at least two of said banks, (c) a dedicated bank select input pin for each respective bank, each bank select input pin being brought out as a control pin at an interface to said macro, each bank select input pin controlling operation of its respective bank and allowing concurrent operations to independent banks, and (d) a data path receiver/driver shared by at least two banks.