Patent ID: 6424195
Filing Date: 2002-07-23
Classification: G11C

Abstract:
A dynamic flip-flop circuit comprising:a first latch having a first input lead, a second input lead, a third input lead, and an output lead, said first latch including a shutoff circuit, wherein said first input lead of said first latch is coupled to receive a clock signal; said second input lead of said first latch is coupled to receive a data signal; said third input lead of said first latch is coupled to receive a compare enable signal; said first latch is operative to output a signal of a first logic level at said output lead of said first latch when said clock signal is low; said first latch is operative to sample a logic level at said second input lead of said first latch when said data signal is high and said clock signal is high; and said first shutoff circuit is operative to cause said first latch to stop sampling when said data signal is high and said clock signal is high, unless said compare enable signal is low; a second latch having a first input lead, a second input lead, and an output lead, said second latch including a second shutoff circuit, wherein said second latch is operative to output a signal of said first logic level at said output lead of said second latch when said clock signal is low; said first input lead of said second latch is coupled to receive said clock signal; and said second input lead of said second latch is coupled to receive a complement of said data signal; said second latch is operative to output a signal of a first logic level at said output lead of said second latch when said clock signal is low; said second latch is operative to sample a logic level at said second input lead of said second latch when said data signal is high and said clock signal is high; and said second shutoff circuit is operative to cause said second latch to stop sampling when said data signal is high and said clock signal is high, unless said compare enable signal is low; a first output latch having an input lead and an output lead, said input lead of said first output latch coupled to said output lead of said first latch; and a second output latch having an input lead and an output lead, said input lead of said second output latch coupled to said output lead of said second latch.