Patent ID: 8519875
Filing Date: 2013-08-27
Classification: H03M

Abstract:
1. An interleaved analog-to-digital converter (ADC) comprising: a reference ADC coupled to receive an analog signal, the reference ADC generates a digital reference output; a plurality of sub-ADCs coupled to receive the analog signal, the plurality of sub-ADCs samples the analog signal at sample locations responsive to a clock and generates a plurality of digital signals corresponding to a sampled portion of the analog signal; a calibration block coupled to receive the plurality of digital signals and the digital reference output, the calibration block identifies at least one error value between the plurality of digital signals and the digital reference output; and wherein a correlation basis function is applied to the at least one error value to generate an error estimate signal that is used to compensate for the at least one error value, the error value is determined from a difference between at least one of the plurality of digital signals and the digital reference output.