Patent ID: 6323791
Filing Date: 2001-11-27
Classification: H03M

Abstract:
A control system for reducing residue signal offset errors in subranging analog-to-digital converters that have at least one combination of a prior converter stage and a subsequent converter stage wherein said prior converter stage includes a prior analog-to-digital converter and a corresponding prior digital-to-analog converter, the control system comprising:a residue amplifier in said prior converter stage that generates, in response to an input signal, a residue signal with a common-mode level that is responsive to an offset signal;a residue sampler in said subsequent converter stage that samples said residue signal to produce a sampled residue signal; anda feedback loop around said residue sampler and said residue amplifier that includes:a) a feedback sampler that resamples said sampled residue signal to produce a resampled residue signal; andb) an offset signal generator that delivers said offset signal to said residue amplifier with a signal magnitude that is responsive to said resampled residue signal.