Patent ID: 8228110
Filing Date: 2012-07-24
Classification: H04L

Abstract:
1. A phase interpolator, comprising: a first output terminal and a second output terminal to provide an interpolated output signal; and a first interpolator module having a first set of transistors in communication with a first plurality of input phase signals and a first set of select signals, the first set of transistors having a first group of transistors coupled to the first output terminal and a second group of transistors coupled to the second output terminal, wherein the first group includes multiple, separate first pairs of transistors, the second group includes multiple, separate second pairs of transistors, each transistor of the first pairs of transistors is different from each transistor of the second pairs of transistors, respective transistors of each of the separate first pairs and the separate second pairs are coupled in series with no other circuit elements connected at each respective node between the respective transistors coupled in series, each gate of each first transistor in each pair of the first pairs of transistors and the second pairs of transistors is enabled by a select signal of the first set of select signals, and each gate of each second transistor in each pair of the first pairs of transistors and the second pairs of transistors is enabled by an input phase signal of the first plurality of input phase signals, wherein the first interpolator module is configured to receive at least one of the first set of select signals to: wherein the interpolated output signal is generated based on the outputs provided at the first output terminal and the second output terminal.