Patent ID: 7783939
Filing Date: 2010-08-24
Classification: G11C

Abstract:
1. A cache memory built in a processor, comprising: a first area and a second area each having a plurality of independent memory blocks; a pass/fail information memory unit to memorize, for each of the memory blocks, information indicating a presence or an absence of a failure having occurred in each of said memory blocks; and a screening control unit to substitute a failed memory block within either one of the first area or the second area with a sound memory block within the other one of the first area or the second area based on a content of said pass/fail information memory unit, the substitution causes the sound memory block to function in place of the failed memory block; wherein the screening control unit substitutes the failed memory block within the second area with the sound memory block based on the content of said pass/fail information memory unit; and the plurality of independent memory blocks included in the second area other than the failed memory block and the sound memory block in the first area are usable memory blocks of the cache memory.