Patent ID: 9190526
Filing Date: 2015-11-17
Classification: G02F,H01L

Abstract:
1. A thin film transistor, comprising: a gate electrode provided on a substrate; a gate insulating film covering the gate electrode; a semiconductor layer made of an oxide semiconductor provided on the gate insulating film, and having a channel region overlapping the gate electrode; a source electrode and a drain electrode provided on the semiconductor layer via metal layers which are more easily reduced than the semiconductor layer, and spaced apart from each other, with the channel region interposed therebetween; a conductive region provided on the semiconductor layer, and reduced by contact with the metal layers; and a diffusion reducing portion provided in the semiconductor layer to limit an amount of diffusion of the conductive region into the channel region; wherein the diffusion reducing portion is configured to reduce a contact area between the semiconductor layer and the metal layers; the metal layers are provided on the semiconductor layer so as to be opposite to the substrate; the semiconductor layer is provided with a first opening and a second opening which expose the gate insulating film from the semiconductor layer and each of which serves as the diffusion reducing portion; the metal layers are in contact with the semiconductor layer via side walls of the first opening and the second opening; and the first opening and the second opening are completely surrounded by the semiconductor layer when viewed from a top view.