Patent ID: 9209029
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method of making an asymmetric gate MOS device comprising: providing a semiconductor substrate, fabricating a gate oxide layer on the semiconductor substrate; fabricating a gate comprising metal over the gate oxide layer, and implanting dopant ions into the gate to cause the gate to have different work functions on its two sides; forming sidewalls on the two sides of the gate; and performing source/drain implant to form source/drain regions in the semiconductor substrate; wherein fabricating the gate over the gate oxide layer further comprises: forming consecutively a polycrystalline semiconductor layer and an insulator layer over the gate oxide layer; consecutively etching the insulator layer and the polycrystalline semiconductor layer to remove portions of the insulator layer and the polycrystalline semiconductor layer on two sides; depositing metal films on sidewalls of the two sides of the polycrystalline semiconductor layer, metal in the metal films diffusing toward the polycrystalline semiconductor layer; removing the metal films remaining on surfaces of the sidewalls of the polycrystalline semiconductor layer; performing annealing on the polycrystalline semiconductor layer to form metal-semiconductor-compound nanowires on the sidewall surfaces of the polycrystalline semiconductor layer; removing the insulator layer and the polycrystalline semiconductor layer; etching the gate oxide layer using the metal-semiconductor-compound nanowires as a mask; and implanting dopant ions into the metal-semiconductor-compound nanowires to cause each metal-semiconductor-compound nanowire to have different work functions on its two sides.