Patent ID: 7741153
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A method of integrating chips, chip macros or at least one chip in combination with at least one chip macro, the method comprising the steps of: assembling the chips, chip macros or at least one chip in combination with at least one chip macro on a single carrier platform; providing one or more signal inputs and outputs to each of the chips, chip macros or at least one chip in combination with at least one chip macro through the carrier platform; providing one or more power and ground inputs and outputs to each of the chips, chip macros or at least one chip in combination with at least one chip macro through the carrier platform; and segmenting the power and ground inputs and outputs to one or more of the chips, chip macros or at least one chip in combination with at least one chip macro from the power and ground inputs and outputs to at least one other of the chips, chip macros or at least one chip in combination with at least one chip macro so as to form a plurality of voltage islands.