Patent ID: 8603866
Filing Date: 2013-12-10
Classification: G02F,H01L

Abstract:
1. A method of manufacturing an array substrate, comprising: forming a gate line on a substrate; forming a data line crossing the gate line to define a pixel region; forming a thin film transistor connected to the gate and data lines; forming a pixel electrode in the pixel region; and forming a common electrode including first, second, third, fourth and fifth portions, wherein the first and second portions are respectively disposed at opposite sides of the data line, wherein the first and second portions are connected by each of the third and fourth portions only, and the fifth portion is directly connected to only the second portion in each pixel region and extends into a next pixel region adjacent to the pixel region, wherein the fifth portion is spaced apart from the first portion, and wherein the third and fourth portions are electrically connected to the fifth portion only through the second portion.