Patent ID: 6498093
Filing Date: 2002-12-24
Classification: H01L,Y10S

Abstract:
A method for filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, the method comprising the steps of:A. forming an underlying material at any exposed walls of said interconnect opening; B. forming a sacrificial layer of protective material on said underlying material at said walls of said interconnect opening; wherein said step A and said step B are performed without a vacuum break between said step A and said step B; and wherein said protective material of said sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer; C. immersing said semiconductor substrate having said interconnect opening within an acidic catalytic solution for depositing a catalytic seed layer after said steps A and B; wherein said sacrificial layer of protective material is dissolved away from said underlying material by said acidic catalytic solution such that said underlying material is exposed to said acidic catalytic solution; and D. depositing a catalytic seed layer formed from said acidic catalytic solution on said exposed underlying material at said walls of said interconnect opening while said semiconductor substrate is immersed within said acidic catalytic solution during said step C; wherein said sacrificial layer of protective material is dissolved away and said catalytic seed layer is formed on said underlying material all the while said semiconductor substrate is immersed within said same acidic catalytic solution during said step C.