Patent ID: 7352629
Filing Date: 2008-04-01
Classification: G11C

Abstract:
1. A non-volatile memory system, comprising: a set of non-volatile storage elements; and managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry programs said set of non-volatile storage elements in a process where each non-volatile storage element of said set is intended for programming to one of one or more target states, said managing circuitry inhibits programming of each non-volatile storage element that reaches a respective verify level corresponding to said target state to which it is intended to be programmed, said managing circuitry enables a first rate of programming of each non-volatile storage element that reaches a respective verify level corresponding to said target state to which it is intended to be programmed and that subsequently falls below said respective verify level corresponding to said target state to which it is intended to be programmed, said managing circuitry enables a second rate of programming of each non-volatile storage element that has not yet reached a respective verify level corresponding to said target state to which it is intended to be programmed.