Patent ID: 8689066
Filing Date: 2014-04-01
Classification: G01R,G06F

Abstract:
1. A method of implementing integrated circuit device testing using adaptive test pattern selection, the method comprising: performing an initial baseline testing of a first group of chips to be tested using a full set of test patterns; for each of the first group of chips identified as failing at least one of the full set of test patterns, determining, by a computing device, a score for each test pattern in the full set, the score indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns, and keeping a running average of the score for each test pattern as subsequent failed chips are identified; following the initial baseline testing, performing streamlined testing on a second group of chips for a first duration, the streamlined testing comprising using a reduced set of the test patterns, the reduced set comprising test patterns having highest scores as determined by the initial baseline testing; following the streamlined testing, performing full testing on a third group of chips for a second duration, the full testing comprising using the full set of the test patterns and, during the full testing, resuming determining a score for each test pattern in the full set for each failing device in the third group of chips and updating the running average of the score for each test pattern; and alternating between the streamlined testing and the full testing for additional groups of chips.