Patent ID: 6212665
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A method for evaluating power dissipation of an electronic circuit design having at least one cell, the method comprising:receiving input information descriptive of the electronic circuit design, said input information including a power model for each cell instance used in the electronic circuit design;simulating the electronic circuit design so as to generate a simulated logic transition within the at least one cell;storing said simulated logic transition in a first-in-first-out (FIFO) manner in a first queue and a second queue, if said simulated logic transition occurs at an input pin of one of the cells used in the electronic circuit design;storing said simulated logic transition in a FIFO manner in said second queue, if said simulated logic transition occurs at an output pin of one of the cells used in the electronic circuit design;searching a power model for a simple arc that corresponds to said simulated logic transition, said power model corresponding to a cell instance which corresponds to the cell in which said simulated logic transition occurred in said simulating; andgenerating an energy value using said simple arc.