Patent ID: 8149973
Filing Date: 2012-04-03
Classification: H03L,H04L

Abstract:
1. A clock recovery circuit for generating a recovery clock from an input data signal, comprising: a first circuit that detects a phase difference between the input data signal and the recovery clock and outputs the phase difference; a second circuit that averages the output of the first circuit and outputs the average; a third circuit that samples and holds the output of the first circuit and outputs the held value; and a fourth circuit that generates a clock having a phase corresponding to the sum of the integral value of the output of the second circuit and the output of the third circuit and outputs the clock as the recovery clock, wherein the third circuit receives a burst transmission start signal, samples and holds the output of the first circuit, and outputs the held value, and wherein the third circuit receives a burst transmission end signal, and resets the held value to an initial value.