Patent ID: 6799287
Filing Date: 2004-09-28
Classification: H03M

Abstract:
An apparatus for verifying an error correcting code (ECC) operating in an ECC circuit, comprising:an encoder that encodes data bits to produce an encoded signal, the encoded signal comprising the data bits and check bits; an error injection module coupled to the encoder and capable of injecting an error signal into the encoded signal, the error injection module producing an output signal comprising one of a no error condition, a single error condition, and a multiple error condition; a decoder coupled to the error injection module that decodes the output signal to produce one or more decoded output signals, the decoded output signals comprising a no error signal, a single error signal, and a multiple error signal; and a monitor module that reads the decoded output signals, wherein when a no error condition is produced, the no error signal equals one of a binary 0 and 1.