Patent ID: 6498530
Filing Date: 2002-12-24
Classification: H03F

Abstract:
A ping-pong amplifier, comprising:first and second differential amplifiers, each of which have differential inputs connected to receive a differential input signal and differential outputs, a common-mode reference (CMR) voltage input, and a common-mode feedback circuit arranged to nominally set the differential amplifier's common-mode output voltage to a voltage applied to said CMR input when its differential output voltage is zero, a switching network, a control circuit which operates said switching network, said differential amplifiers, said control circuit, and said switching network arranged to form a ping-pong amplifier having an output which is alternately connected to the outputs of said first and second differential amplifiers to provide an amplified version of said differential input signal, an error amplifier having first and second inputs which produces an output that varies with the difference between its inputs, said first input connected to receive a predetermined common-mode reference voltage (VCMR) and said second input switchably connected to the common-mode output of one of said first and second differential amplifiers, said error amplifier output switchably connected to one of said CMR inputs, first and second memory capacitors connected to the CMR inputs of said first and second differential amplifiers, respectively, said control circuit and switching network arranged such that, periodically, the common-mode output of said first differential amplifier is connected to said error amplifier's second input and said error amplifier's output is connected to said first differential amplifier's CMR input such that a closed-loop is formed which forces said first differential amplifier's common-mode output voltage to be equal to VCMR and said error amplifier's output voltage to be stored on said first memory capacitor, and said control circuit and switching network further arranged such that, periodically, the common-mode output of said second differential amplifier is connected to said error amplifier's second input and said error amplifier's output is connected to said second differential amplifier's CMR input such that a closed-loop is formed which forces said second differential amplifier's common-mode output voltage to be equal to VCMR and said error amplifier's output voltage to be stored on said second memory capacitor.