Patent ID: 6498357
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, comprising:a P type silicon substrate; a plurality of shallow trench isolations formed in said substrate; a N well and a P well adjacent thereto formed between one pair of said shallow trench isolations in said substrate; a dummy gate formed on said N well; a N type polysilicon gate formed on said P well and connected to a cathode terminal; two first N+ diffusion region respectively formed beside each side of said N type polysilicon gate, one said first N+ diffusion region between said N type polysilicon gate and said dummy gate and across one portion of said N well and one portion of said P well, while the other said first N+ diffusion region connected to said cathode terminal; a first P+ diffusion region formed beside one side of said dummy gate with opposite to said first N+ diffusion region formed beside the other side thereof, said first P+ diffusion region connected to an anode terminal; a second P+ diffusion region formed between said first N+ diffusion region connected to said cathode terminal and one said shallow trench isolation in said P well, said second P+ diffusion region connected to said cathode terminal; and a second N+ diffusion region formed between said first P+ diffusion region and one said shallow trench isolation in said N well, said second N+ diffusion region connected to said anode terminal.