Patent ID: 7426663
Filing Date: 2008-09-16
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of memories included a multi-port memory and a single-port memory, address decode logics of the memories; logical units for controlling access to said plurality of memories, a common test bus coupled to the plurality of memories, and sent test information to the memories, respectively; and a plurality of bridge units each coupling between a respective one of the memories and the common test bus and providing said test information from said common test bus to the respective one of said memories, wherein said test information includes test address information, and said test address information converted into predetermined bit arrangement of said memories are provided to corresponding memories, wherein said plurality of memories includes different address decode units respectively, wherein said test information is provided to each of the memories via said common test bus, and then the memories are operable to test in parallel, wherein each of the bridge units develops said test information into a plurality of bits according to a data width of the memories, and wherein the bridge unit of said multi-port memory selects a port to be connected to said common test bus and inputs disturb information to a non-select port not connecting to said common test bus.