Patent ID: 7977789
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A semiconductor package comprising: an electrode pad formed above a semiconductor chip; a passivation layer disposed over the electrode pad and having an opening that exposes a portion of the electrode pad; a first polymer layer directly formed on the passivation layer and the electrode pad, the first polymer layer having a first plurality of vias formed therethrough overlying the electrode pad; a redistribution electrode layer having a first end and a second end, the redistribution electrode layer overlying the first polymer layer, the first end of the redistribution electrode layer being electrically connected to the electrode pad through the first plurality of vias, a second polymer layer overlying the redistribution electrode layer, the second polymer layer having a second plurality of vias at the second end of the redistribution electrode layer; an under bump metal formed on the second polymer layer and being electrically connected to the second end of the redistribution electrode layer through the second plurality of vias; and a metal bump coupled to the under bump metal.