Patent ID: 7944265
Filing Date: 2011-05-17
Classification: H03L

Abstract:
1. A clock generator, comprising: a delta-sigma modulator configured to sequentially generate a plurality of variable parameters and a counting value according to a predetermined value and a first input clock signal; a counter coupled to the delta-sigma modulator for generating an output clock signal according to the counting value and a second input clock signal, wherein the delta-sigma modulator does not reactivate output of the variable parameters until the output clock signal is fed back to the delta-sigma modulator; and a phase lock loop coupled to the counter for generating an objective clock signal according to the output clock signal, comprising: a charge pump configured to provide a first current with a current level; and an additional current source coupled to the charge pump for providing a second current, wherein the current level is affected by the second current for generating a direct current offset such that the clock generator averts from a non-linear region, the objective clock signal is not fed back to the delta-sigma modulator and the counter.