Patent ID: 6337825
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array in which a plurality of bit lines and a plurality of word lines are arranged to cross each other and current read-out type memory cells are arranged at crossing points thereof; a decoding circuit for selecting a predetermined number of bit lines and a word line of said memory cell array; a plurality of sense amplifiers for detecting and amplifying data read out on the predetermined number of bit lines selected from the plurality of bit lines, said sense amplifiers being provided for every I/O line of said memory cell array, said each sense amplifier having a sense node as one input terminal and a reference node as the other input terminal; and a reference voltage generating circuit for providing a reference voltage having a level between voltages of two-valued data output to said sense node, wherein said sense node of each sense amplifier is connected to a corresponding I/O line and at least two reference nodes of sense amplifiers is commonly connected to said reference voltage generating circuit.