Patent ID: 6073231
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A pipelined processor having an execution pipeline that processes at least some instructions that reference a set of logical registers, comprising:(a) the execution pipeline including at least (i) an instruction decode stage, (ii) an execution stage, (iii) pipeline control circuitry, and (iv) microcontrol circuitry, wherein at least some of the instructions that reference the logical registers are microcontrolled instructions;(b) the microcontrol circuitry providing, for each of the microcontrolled instructions, one or more microinstructions controlling execution of the microcontrolled instruction in the execution stage of the execution pipeline;(c) a register file with a plurality of physical registers for storing information associated with the logical registers; and(d) register translation circuitry that allocates physical registers in the register file to the logical registers, the register translation circuitry being controllable either by (i) hardware control signals generated by the instruction decode stage or the pipeline control circuitry, or (ii) for a predetermined type of microcontrolled instruction, microcode control signals generated by one or more microinstructions associated with the predetermined type of microcontrolled instruction;(e) for each of the predetermined type of microcontrolled instruction, the microcontrol circuitry provides the microcode control signals to the register translation circuitry during execution of such predetermined type of microcontrolled instruction.