Patent ID: 6429068
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A method of forming a memory array and support transistors on a semiconductor substrate, the method comprising:providing a memory structure having an array region and a support region separated by an isolation region, wherein the array region includes a plurality of dynamic random access memory cells embedded in the substrate, wherein adjacent dynamic random access memory cells are connected to each other through bitline diffusion regions, wherein the memory structure is capped with a top oxide layer; applying a block mask to protect the array region while stripping the top oxide layer from the support region; forming support implants, forming a support gate oxide layer and patterning a first polysilicon layer onto the support gate oxide layer; forming a conductive nitride barrier layer, a metal layer and a dielectric capping layer on all exposed surfaces of the substrate; removing portions of the nitride barrier layer, the metal layer and the dielectric capping layer from the support region to form a support gate structure and removing the nitride barrier layer, the metal layer and the dielectric capping layer from the isolation region, wherein the support gate structure comprises the gate oxide layer, the first polysilicon layer, the nitride barrier layer, the metal layer and the dielectric capping layer; forming an insulated spacer on sidewalls of the gate structure; forming a protective layer on all exposed surfaces of the substrate; forming an array gate structure in contact with the memory cell and exposing a portion of the bitline diffusion region by removing portions of the protective layer, the nitride barrier layer, the metal layer and the dielectric capping layer from the array region, wherein the array gate structure comprises the oxide layer, the nitride barrier layer, the metal layer and the dielectric capping layer, and simultaneously removing the protective layer from the isolation region; forming a spacer layer on sidewalls of the array gate structure; depositing a second polysilicon layer onto the substrate; selectively patterning and etching the second polysilicon layer in the isolation region to form a landing pad while removing the polysilicon layer from the support regions; and simultaneously forming silicide layers on an exposed portion of the source and drain regions in the support region, on the second polysilicon layer overlaying the bitline diffusion regions in the array region, and on the second polysilicon layer defining the landing pad.