Patent ID: 6599823
Filing Date: 2003-07-29
Classification: H01L

Abstract:
A method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric, said method comprising:providing a semiconductor substrate with a layered structure having a top interconnection line layer, a bottom interconnection line layer and a plurality of alternative interconnection line layers and via layers formed therebetween, each of said vias being in alignment with one adjacent upper interconnection line and one adjacent lower interconnection line, wherein a low K dielectric material is filled in said layered structure as an inter-metal dielectric; patterning said layered structure to form a trench between each pair of said adjacent interconnection lines on one layer of said layered structure; forming a first oxide layer over said layered structure to fill said trench formed therein and then planarizing said first oxide layer; forming a second oxide layer over said first oxide layer; patterning said second oxide layer to form a plurality of openings each of which being in alignment with each of said top interconnection lines; forming a conductive layer over said second oxide layer to fill said openings to form a plurality of plugs; and patterning said conductive layer to form a conductive pad across over each pair of said plugs formed within said second oxide layer.