Patent ID: 6076139
Filing Date: 2000-06-13
Classification: G06F,G09G

Abstract:
A memory system for a computer system, the computer system having a processor and at least one bus master coupled to an input/output device, the processor having a cache, the memory system comprising:a plurality of memory devices;a memory controller coupled to said plurality of memory devices, including:at least one bus interface, said bus interface for communicating data between said input/output device and said memory devices;a processor interface for communicating data between said processor and said memory devices, including:a central snoop arbiter for receiving snoop requests from a plurality of sources to snoop the processor cache, said central snoop arbiter determining priority among the snoop requests received and granting highest priority to one of the snoop requests; anda memory interface, including:a plurality of concurrently accessible memory channels, each memory channel communicating with a corresponding one of the plurality of memory devices, each memory channel corresponding to a unique address range, each memory channel being independently coupled to said processor interface and said at least one bus interface, each said memory channel including:a snoop controller for generating a snoop request to the processor cache and receiving a snoop acknowledge; andan arbiter receiving memory access requests from said processor and said at least one bus master.