Patent ID: 8195858
Filing Date: 2012-06-05
Classification: G06F

Abstract:
1. A method for scheduling a write data transmission on a bus that couples an intermediary cache to frame buffer logic, wherein the frame buffer logic couples the intermediary cache to an external memory, and the write data transmission involves transmitting write data associated with a write command from the intermediary cache to the frame buffer logic, the method comprising: determining a target clock cycle at which the write data transmission should be scheduled on the bus; determining that a first conflict on the bus exists between the write data transmission and a second data transmission at the target clock cycle; resolving the first conflict by consuming at least a portion of memory space available in a first buffer, a second buffer or a third buffer in the frame buffer logic, wherein the first buffer stores read return data, and the second buffer and the third buffer store requests; and after resolving the first conflict, transmitting a write data request to the intermediary cache for retrieving the write data so that the write data can be transmitted on the bus to the frame buffer logic via the write data transmission, and updating a bus schedule to schedule the write data transmission on the bus.