Patent ID: 8664081
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A method for fabricating a 3D integrated circuit structure, the method comprising the steps of: providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias; providing a first active circuitry layer wafer including active circuitry; bonding the first active circuitry layer wafer face down to the interface wafer; after bonding the first active circuitry layer wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer; providing a base wafer, the base wafer including a second wiring layer; bonding a stack structure face down to the base wafer, the stack structure including the interface wafer and the second portion of the first active circuitry layer wafer; and after bonding the stack structure, thinning the interface wafer so as to form an interface layer, and forming metallizations on the interface layer, the metallizations being coupled through the through-silicon vias in the interface layer to the first wiring layer, wherein the first active circuitry layer wafer comprises an SOI wafer.