Patent ID: 7308523
Filing Date: 2007-12-11
Classification: G06F

Abstract:
1. An enhanced switch with reduced head-of-line blocking comprising: an uplink port for sending substitute request packets toward a root complex and for receiving substitute reply packets from the root complex, the substitute reply packets containing reply data read from a memory in response to the substitute request packets; a plurality of downlink ports for connecting to a plurality of peripheral endpoint devices, each downlink port for receiving original request packets from a peripheral endpoint device with a request to read the memory through the root complex, each downlink port also for receiving altered reply packets containing reply data read from the memory in response to the request; and a multiple packet generator that generates a plurality of substitute request packets from an original request packet, each substitute request packet containing a request to read a subset of data requested by the original request packet, whereby head-of-line blocking between first and second peripheral endpoint devices is reduced.