Patent ID: 6504770
Filing Date: 2003-01-07
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising:a plurality of first word lines extending in a first direction in a memory cell array; a plurality of second word lines extending in said first direction in said memory cell array; a plurality of third word lines provided between said first word lines and said second word lines in said memory cell array; a first drive circuit connected to said first word lines; a second drive circuit connected to said second word lines; a third drive circuit connected to said third word lines; a plurality of first bit lines extending in a second direction crossing said first direction in said memory cell array; a plurality of second bit lines extending in said second direction in said memory cell array; a plurality of third bit lines provided between said first bit lines and said second bit lines in said memory cell array; a first sense circuit connected to said first bit lines; a second sense circuit connected to said second bit lines; and a third sense circuit connected to said third bit lines, wherein each of said first, second and third drive circuits is a unit having a common layout, wherein said first and second word lines are normal word lines, wherein some of said third word lines are redundant word lines and the others of said third word lines are normal word lines, wherein each of said first, second and third sense circuits is a unit having a common layout, wherein said first and second bit lines are normal bit lines, and wherein some of said third bit lines are redundant bit lines and the others of said third bit lines are normal bit lines.