Patent ID: 7886143
Filing Date: 2011-02-08
Classification: G09C,H04L

Abstract:
1. A microchip security architecture comprising: a microchip having at least first and second stages of cipher round logic, each stage configured to perform cryptographic processing of plaintext data in a counter mode and output ciphertext data; at least first and second multipliers, each multiplier configured to receive the ciphertext data output from at least one associated stage of the first and second stages of cipher round logic and continue the cryptographic processing to output at least a portion of an integrity check value (ICV); and control logic configured to provide a selection between a first data path, a second data path, and a third data path, wherein the first, second, and third data paths are different data paths; the first data path including performing the cryptographic processing at a first data rate using the first stage and the first multiplier; the second data path including performing the cryptographic processing at the first data rate using the second stage and the second multiplier; and the third data path including performing the cryptographic processing at a second data rate using at least the first stage and the second stage and at least the first multiplier and the second multiplier, the second data rate being higher than the first data rate.