Patent ID: 8822282
Filing Date: 2014-09-02
Classification: H01L

Abstract:
1. A method comprising: providing a gate stack disposed above a first area of a substrate, the gate stack comprising a gate oxide disposed beneath a conductive gate material, the substrate comprising a strained layer over a first relaxed layer; epitaxially depositing a SiGe layer in at least one area of said substrate adjacent to the first area of said substrate; providing a metal layer over said SiGe layer, said metal layer comprising Ni; and reacting said metal layer with said SiGe layer to form a region comprising at least one of silicide or silicide/germanicide disposed over and in direct contact with unreacted SiGe, wherein the region comprising at least one of silicide or silicide/germanicide forms a contact region for a source or a drain of a FET, and wherein a channel region of the FET comprises a portion of the strained layer.