Patent ID: 6930056
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A process for forming an integrated circuit structure having at least one layer of low k dielectric material therein and a layer, formed from said low k dielectric material, suitable for use as an etch stop and/or an etch mask which consists essentially of: a) forming a first layer of low k dielectric material over a previously formed integrated circuit structure; and b) then, prior to any exposure of said first layer of low k dielectric material to etchants, treating the upper surface of said first layer of low k dielectric material with a plasma formed from a non-oxidizing gas to form a first layer of densified dielectric material over the remainder of the underlying first layer of low k dielectric material; whereby said first layer of densified dielectric material is capable of serving as a etch stop and/or an etch mask for subsequent etching of said underlying first layer of low k dielectric material.