Patent ID: 6496076
Filing Date: 2002-12-17
Classification: G11B,H03L

Abstract:
A PLL (Phase-Locked Loop) circuit comprising;an A/D converter which quantizes an input signal substantially being equalized into a waveform conforming to a partial-response system; and a phase-error detection circuit including a pattern detector which detects a pattern of a waveform of the input signal to said A/D converter, which extracts phase error data from output data from said A/D converter in accordance with a result of detection by said pattern detector, wherein: said PLL circuit executes phase locking by causing the phase error data output from said phase-error detection circuit to be fed back to said A/D converter, wherein said phase-error detection circuit further includes a selector which, based on the result of detection by said pattern detector, selects the phase-error data from the output data from said A/D converter.