Patent ID: 9160350
Filing Date: 2015-10-13
Classification: G11C,H03K,H03L

Abstract:
1. An integrated circuit (IC), comprising: first circuitry to generate a first clock signal by delaying an input clock signal by a first delay; a set of delay elements to generate a set of delayed versions of the input clock signal, wherein each delayed version of the input clock signal has a different delay; a time-to-digital converter (TDC) to generate a code based on the first clock signal and the set of delayed versions of the input clock signal; one or more injection-locked oscillators (ILOs) having a set of injection locations, wherein an output of an ILO in the one or more ILOs is provided as the output clock signal; and a de-multiplexer to inject an injection signal into an injection location that is selected from the set of injection locations based on the code, wherein the injection signal is generated based on the input clock signal.