Patent ID: 7843044
Filing Date: 2010-11-30
Classification: H01L,H01M,Y02E

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; first and second field effect transistors which are formed over a main surface of the semiconductor substrate; a first source electrode and a first gate electrode which are respectively electrically connected with a source and a gate of the first field effect transistor and are formed over the main surface of the semiconductor substrate; a second source electrode and a second gate electrode which are respectively electrically connected with a source and a gate of the second field effect transistor and are formed over the main surface of the semiconductor substrate; a drain electrode which is electrically connected with drains of the first and second field effect transistors and is formed over a back surface of the semiconductor substrate; a plurality of first source bump electrodes disposed over the first source electrode; a first gate bump electrode disposed over the first gate electrode; a plurality of second source bump electrodes disposed over the second source electrode; a second gate bump electrode disposed over the second gate electrode; a first source conductor portion which is electrically connected with the first source electrodes via the plurality of first source bump electrodes, formed over the semiconductor substrate; a first gate conductor portion which is electrically connected with the first gate electrodes via the first gate bump electrode, formed over the semiconductor substrate; a second source conductor portion which is electrically connected with the second source electrodes via the plurality of second source bump electrodes, formed over the semiconductor substrate; a second gate conductor portion which is electrically connected with the second gate electrodes via the second gate bump electrode, formed over the semiconductor substrate; a drain conductor portion which is electrically connected with the drain electrode formed over the back surface of the semiconductor substrate, and a sealing portion which covers the first and second source conductor portions, the first and second gate conductor portions, a portion of the drain conductor portion and the semiconductor substrate, wherein respective portions of the first and second source conductor portions, the first and second gate conductor portions and the drain conductor portion are exposed from the sealing portion, wherein an exposed portion of the first source conductor portion, an exposed portion of the first gate conductor portion, an exposed portion of the second gate conductor portion and an exposed portion of the second source conductor portion from the sealing portion are arranged in order in one direction, wherein the first and second source conductor portions and the first and second gate conductor portions have other portions thereof extended over the main surface of the semiconductor substrate, wherein a portion of the first source electrode which extends over the main surface of the semiconductor substrate is also present in a first extending direction that the first gate conductor portion extends from a portion thereof which is exposed from the sealing portion to a portion thereof in the inside of the sealing portion, wherein a portion of the first source conductor portion which extends over the main surface of the semiconductor substrate is also present in the first extending direction that the first gate conductor portion extends from a portion thereof which is exposed from the sealing portion to a portion thereof in the inside of the sealing portion, wherein a portion of the second source electrode which extends over the main surface of the semiconductor substrate is also present in a second extending direction that the second gate conductor portion extends from a portion thereof which is exposed from the sealing portion to a portion thereof in the inside of the sealing portion, wherein a portion of the second source conductor portion which extends over the main surface of the semiconductor substrate is also present in the second extending direction that the second gate conductor portion extends from a portion thereof which is exposed from the sealing portion to a portion thereof in the inside of the sealing portion, wherein, in the first extending direction, one of the plurality of the first source bump electrodes is present between the first gate bump electrode and another one of the plurality of the first source bump electrodes, and wherein, in the second extending direction, one of the plurality of the second source bump electrodes is present between the second gate bump electrode and another one of the plurality of the second source bump electrodes.