Patent ID: 7932845
Filing Date: 2011-04-26
Classification: H03M,H04N

Abstract:
1. An integrated circuit device comprising: a plurality of analog to digital converter (ADC) circuits to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each ADC circuit having a gain setting that controls a magnitude of the digital representations; a timing signal generator to generate the timing signals; a calibration signal generator to generate a calibration signal that constitutes at least part of the input signal during at least part of a time interval over which the ADC circuits are enabled to generate respective digital representations of the input signal; and correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal, the correction circuitry to adjust the gain settings of the ADC circuits and phases of the timing signals generated by the timing signal generator based at least in part on the FFTs.