Patent ID: 7704832
Filing Date: 2010-04-27
Classification: H01L

Abstract:
1. A method of fabricating non-volatile memory, comprising: forming a first layer of dielectric material over a surface of a substrate; forming a layer of charge storage material over the surface of the substrate; etching the layer of charge storage material to form a set of charge storage regions over the first layer of dielectric material at a first portion of the substrate, the charge storage regions including sidewalls elongated in a first direction with spaces between opposing sidewalls of storage regions adjacent in a second direction substantially perpendicular to the first direction; removing the layer of charge storage material from a second portion of the substrate; forming a second layer of dielectric material over the surface of the substrate; forming a layer of gate material over the surface of the substrate; etching the layer of gate material at the first portion of the substrate to form a set of control gates for the set of charge storage regions, the control gates at least partially occupying the spaces between adjacent charge storage regions; and etching the layer of gate material at the second portion of the substrate to form a gate region of a select transistor for the set of charge storage regions.