Patent ID: 6789175
Filing Date: 2004-09-07
Classification: G06F,G11C

Abstract:
A method of synchronously reading and writing data in a memory device having a memory array according to a clock signal defining a series of operational intervals, comprising the steps of:providing a read command during a first operational interval; providing a write command at a second operational interval immediately following the first operational interval; in response to the read command, completing a read operation by coupling read data to data bus terminals at an Nth operational interval following the first operational interval by Nâˆ’1 operational intervals, where the N is greater than or equal to 2; in response to the write command, coupling write data from the data bus terminals at an (N+1)th operational interval following the first operational interval by N operational intervals; and completing a write operation using the write data coupled from the data bus terminals at the (N+1)th operational interval.