Patent ID: 6593622
Filing Date: 2003-07-15
Classification: H01L

Abstract:
A power MOSFET with an integrated P channel driver FET and an N channel driver FET in a common package; said common package comprising a conductive support having extending terminals; said power MOSFET having a drain electrode fixed to said conductive support; said P channel and N channel driver FETs having respective gate, source and drain electrodes, one of said source or drain electrodes of said driver FETs connected at a node to define a series totem pole arrangement with the others of said source or drain electrodes of said driver FETS at the outer ends of said totem pole; the outer terminals of said totem pole circuit connected between a Vcc terminal and a ground terminal; and a driver input control terminal connected to said gate electrodes of said P and N channel driver FETs; said power MOSFET having a source electrode connected to said ground terminal; said node between said N and P channel drivers connected to the gate electrode of said power MOSFET; and a single, common insulation housing enclosing said power MOSFET, said conductive support and said N and P channel FETs; said extending terminals including a drain terminal which is connected to said power MOSFET drain electrode, said ground terminal, said Vcc terminal and said driver input control terminal.