Patent ID: 6417101
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device for use in a memory cell, the method comprising steps of:a) preparing an active matrix provided with at least one transistor, at least one conductive plug electrically connected to each transistor and an insulating layer formed around the conductive plug; b) patterning the insulating layer into a first predetermined configuration to form contact holes; c) forming a diffusion barrier layer on an entire surface including the contact holes; d) forming a seed layer on top of the diffusion barrier layer; e) forming a first conductive layer on top of the seed layer, said first conductive layer forming a conductive plug; f) carrying out a thermal treatment for changing grains of the conductive plug into a granular type; g) removing the first conductive layer, the diffusion barrier layer and the seed layer until a top surface of the insulating layer is exposed; h) forming a second conductive layer on the conductive plug and the insulating layer; i) patterning the second conductive layer into a second predetermined configuration to form a bottom electrode; and j) forming a dielectric layer and a third conductive layer on the bottom electrode and the insulating layer, subsequently.