Patent ID: 7899089
Filing Date: 2011-03-01
Classification: H04N

Abstract:
1. A device, comprising: an input buffer to store a plurality of packets and at least two Program Clock References of an input transport stream; a comparator coupled to the input buffer to determine if a complete Program Clock Reference (PCR) interval has been stored; an arithmetic unit coupled to the comparator to compute a number of null packets (NP) to insert to an output transport stream after a complete PCR interval has been stored; a PCR restamper coupled to the arithmetic unit to restamp the at least two PCRs; an output generator coupled to the PCR restamper to control the output of the output transport stream; and wherein if R T (PI i+1 −PO i )−BI is greater than zero, wherein R T is the target bit rate of an output transport stream, wherein PI i is the i th input PCR value, wherein PI i+1 is the i+1 th input PCR value, PO i is an i th output PCR value, wherein BI is the number of bits between the i th input PCR and the i+1 th input PCR, and wherein PO i is set equal to PI i .