Patent ID: 6407608
Filing Date: 2002-06-18
Classification: H03K

Abstract:
A clock buffer circuit comprising:a first buffer circuit for generating logic transitions at a first output node in response to logic transitions in an external clock signal; a pulse generator for generating a boost pulse at a pulse node in response to the first buffer circuit driving the first output node to a first logic level, comprising: a first IGFET and a second IGFET having source-drain paths coupled in series between the pulse node and a second power supply voltage, a non-delay path coupled between the first output node and the gate of the first IGFET, and a delay path coupled between the first output node and the gate of the second IGFET and a boost circuit coupled between the first output node and a first power supply voltage corresponding to the first logic level, and coupled to the pulse node, the boost circuit for providing a low impedance path between the first output node and the first power supply voltage responsive to the boost pulse.