Patent ID: 7418068
Filing Date: 2008-08-26
Classification: F04D,F24F,G06F,G09G,H04L,H05K,Y02B

Abstract:
1. A data capture method to allow optimal sampling and capture of an asynchronous data stream without sending a clock signal with the data stream comprising: capturing the data by sending serial data bits of the data stream down a clocked delay line with a series of delay taps; sampling all of the delay taps with a clock; comparing each delay tap output with a neighbor delay tap output to determine if it is the same; using the comparisons to form a clocked string to generate a data history record; examining the data history record to determine optimal data capture eyes by looking for data capture eyes where the data does not transition between adjacent delay taps, which are detected as optimal data capture eyes, wherein the serial data enters the clocked delay line, and is clocked through a combinatorial series of inverters, each of which adds an increment of delay, wherein the clocked delay line comprises a delay tap register at the output of each inverter, and, the output of each delay tap register is directed to an exclusive OR gate XOR which also receives an input from the next delay tap register in the clocked delay line, and since the data bit is inverted by the next delay line inverter before it enters the next delay tap register, and if the data bit does not undergo a transition between the consecutive stages, each delay tap register and the next delay tap register will hold opposite values, such that the XOR gate will produce a 1, indicating there was no data transition between the consecutive stages, and conversely, if the data bit undergoes a transition between the consecutive stages, each delay tap register and the next delay tap register will hold the same value, such that each stage XOR gate will produce a 0, indicating there was a data transition between the consecutive stages, wherein the output of each XOR gate is input to an AND gate, the output of which is input to a first history register, which is the first of a series of four history registers, and the first history register is sampled and reset to high at first clock rate, and the second, third and fourth history registers are sampled and updated at a slower second clock rate.