Patent ID: 6477103
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A reprogrammable fuse comprising:a first non-volatile memory cell of the type having a first terminal and a second terminal in a substrate with a channel therebetween, a floating gate for storing charges and overlying a first portion of said channel and capacitively coupled to said first terminal, and a control gate overlying a second portion of said channel and for removing charges stored on said floating gate; a second non-volatile memory cell of the type having a first terminal and a second terminal in a substrate with a channel therebetween, a floating gate for storing charges and overlying a first portion of said channel and capacitively coupled to said first terminal, and a control gate overlying a second portion of said channel and for removing charges stored on said floating gate; a first bitline connected to the second terminal of said first non-volatile memory cell; a second bitline connected to the second terminal of said second non-volatile memory cell; a word line commonly connected to said control gates of said first and second non-volatile memory cells; a source line commonly connected to said first terminals of said first and second non-volatile memory cells; a precharging and equalization circuit commonly connected to said second terminals of said first and second non-volatile memory cells; and an output terminal connected to one of said first or second bitlines for supplying an output signal indicative of the state of said fuse; wherein said fuse is erased by supply erase voltages to said word line and said source line; and wherein said fuse is programmed by supplying programming voltages to said source line, word line, and said first bitline and said second bitline, wherein said fuse is programmed to one state when said floating gate of said first non-volatile memory cell stores more charges than said floating gate of said second non-volatile memory cell; and wherein said fuse is programmed to another state when said floating gate of said first non-volatile memory cell stores less charges than said floating gate of said second non-volatile memory cell; and wherein the programmed state of said fuse is read by supplying a precharging voltage to said first and second bitlines and differentially sensing said first and second bitlines.