Patent ID: 6756678
Filing Date: 2004-06-29
Classification: H01L,Y10T

Abstract:
An integrated circuit comprising:integrated circuit wiring over a semiconductive substrate; an insulation layer enclosing the wiring and a bond pad opening extending into the insulation layer, the bond pad opening having sidewalls and partially exposing the wiring along the sidewalls; a conductive layer comprising copper over the substrate and only partially filling the bond pad opening, the layer being on and in contact with the wiring where partially exposed from the insulation layer; a layer of intermetallic material within the layer comprising copper, the intermetallic material layer comprising copper and palladium, having a thickness of from about 50 to about 150 Angstroms, and defining a bond pad with an outermost surface that is topographically below an outermost surface of the insulation layer immediately surrounding the bond pad opening; and a conductive connection on the intermetallic layer.