Patent ID: 6429692
Filing Date: 2002-08-06
Classification: H03K

Abstract:
A data sampling circuit comprising:a data tracking circuit that receives a data signal, representing a sampled data value, at a data input transistor at a first sequence of one or more data sampling times and that receives a clock signal at a first clock input transistor at a second sequence of one or more selected times; a data latching circuit that receives the sampled data value from the data tracking circuit, that receives the clock signal at the second sequence of times at a second clock input transistor that has a first state and a second state, and, in response thereto, that provides a data output signal; wherein the first clock input transistor is weaker by a selected amount than the second clock input transistor so that the data latching circuit cannot manifest metastability when a voltage associated with the second clock input transistor moves beyond a selected voltage value in a transition from the first state to the second state.