Patent ID: 6820213
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A fault-tolerant computer system suitable for exchanging data with peripheral devices, said computer system comprising:a first central processing unit (CPU) having at least one first CPU buffer, a second CPU having at least one second CPU buffer, said second CPU being operationally coupled to said first CPU, such that the output of said second CPU is essentially identical to the output of said first CPU; a voter delay buffer having a first FIFO buffer and a second FIFO buffer; an I/O module connected to receive data output streams from said first CPU and said second CPU, said I/O module having, a comparator for comparing said first CPU data output stream to said second CPU data output stream so as to produce a comparison reading; transmission means responsive to said comparator, for sending said first CPU data output stream to the peripheral devices, if said comparison reading indicates no difference between said first CPU data output stream and said second CPU data output stream; and routing means responsive to said comparator, for routing said first CPU data output stream to said first FIFO buffer if said comparison reading indicates a difference between said first CPU data output stream and said second CPU data output stream, and for routing said second CPU data output stream to said second FIFO buffer if said comparison reading indicates a difference between said first CPU data output stream and said second CPU data output stream, wherein said first FIFO buffer buffers said first CPU data output stream and said second FIFO buffer buffers said second CPU data output stream; a priority module for receiving first error correction information from said first CPU and second error correction information from said second CPU; and priority logic for assigning relative priorities to said CPUs, said assigned relative priorities being determined as a function of said first and second error correction information.