Patent ID: 7602783
Filing Date: 2009-10-13
Classification: H04L

Abstract:
1. A packet switch comprising: a plurality of input interfaces; a plurality of output interfaces; and a transmission unit for transmitting variable length packets input from each of the input interfaces to an output interface of the plurality of output interfaces, wherein the output interface corresponds to a destination address of each of the variable length packets, wherein each of the plurality of output interfaces comprises: a buffer memory for reserving the variable length packets in a plurality of queue groups, each of which includes a plurality of queues, and each the queue groups being assigned a first bandwidth respectively, and each of the queues being assigned a transmission priority, and at least one of the queues being assigned a second bandwidth, a queuing controller for assigning to each of the variable length packets one of the queue groups according to header information of each of the variable length packets, assigning to each of the variable length packets one of the queues in the assigned queue group according to the header information of each of the variable length packets, and queuing each of the variable length packets in the assigned queue, a packet read-out controller for reading out the variable length packets according to the transmission priority while guaranteeing the first bandwidth assigned to each of the queue groups, and a packet transmission unit for transmitting each of the variable length packets read out by the packet read-out controller to an output port, wherein the packet read-out controller reads out the variable length packets, thereby further guaranteeing the second bandwidth.