Patent ID: 7307352
Filing Date: 2007-12-11
Classification: H01L

Abstract:
1. A semiconductor package comprising: a substrate having a plurality of first printed circuit bond fingers formed on the surface of the substrate; a semiconductor chip having a plurality of bond pads formed thereon; a plurality of first printed circuit solder ball pads formed on the surface of the substrate; a first printed circuit pattern formed on the surface of the substrate and electrically connecting each of a group of first printed circuit bond fingers and a corresponding first printed circuit solder ball pad; a wire bond electrically connecting each of the group of first printed circuit bond fingers and a corresponding bond pad thereby electrically connecting each of the corresponding bond pads to a first printed circuit solder ball pad; a second printed circuit bond finger formed on the surface of the substrate, there being no wire bond directly connected between the second printed circuit bond finger and any of the bond pads; a second printed circuit solder ball pad formed on the surface of the substrate; a second printed circuit pattern formed on the surface of the substrate and directly connecting the second printed circuit bond finger and the second printed circuit solder ball pad; a third printed circuit bond finger formed on the surface of the substrate, there being no printed circuit pattern directly connected to the third printed circuit bond finger; a first wire bond having one end affixed to the third printed circuit bond finger and the other end affixed to one of the bond pads; and a second wire bond directly connecting the second printed circuit bond finger and the third printed circuit bond finger thereby electrically connecting said one of the bond pads to said second printed circuit solder ball pad, the second printed circuit bond finger having no direct connections to any structure other than the second printed circuit solder ball pad and the third printed circuit bond finger.