Patent ID: 8239747
Filing Date: 2012-08-07
Classification: G06F,H03M

Abstract:
1. A memory device comprising: an array of multi-bit nonvolatile memory cells; an error detector configured to detect a first error in a first page of first-bit data read from a first plurality of multi-bit nonvolatile memory cells in said array during a first error detection operation and further configured to perform a second error detection operation on a second page of second-bit data read from the first plurality of multi-bit nonvolatile memory cells using an estimate of a second-bit datum in the second page of the second-bit data as a read data value having a higher priority of accuracy relative to other read data values within the second page of second-bit data; and an estimator configured to identify a first multi-bit cell in the first plurality of multi-bit nonvolatile memory cells containing the first error and further configured to generate the estimate as a value of a second bit of data in the first multi-bit cell that is predicted by the first error.