Patent ID: 6272594
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A method of assigning bank bits to memory interleaving schemes in a computer system that supports multi-cache line interleaving and cache effect interleaving, wherein the computer system includes a memory organization having a plurality of memory busses, wherein two or more memory busses can each perform independent memory transactions simultaneously, with each memory bus coupled to a plurality of memory bus segments, wherein a read operation on a memory bus segment coupled to a first memory bus can be overlapped with write operation on another memory bus segment coupled to the first memory bus, and each memory bus segment is coupled to one or more memory banks, the method comprising:assigning one or more bank bits that differentiate between memory banks coupled to different memory busses to multi-cache line interleaving; andassigning one or more bank bits that differentiate between memory banks coupled to different memory bus segments but the same memory bus to cache-effect interleaving.