Patent ID: 8435848
Filing Date: 2013-05-07
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising: providing a substrate; forming a gate dielectric layer on a top surface of said substrate in an area defined for an n-channel metal oxide semiconductor (NMOS) transistor and in an area defined for a p-channel metal oxide semiconductor (PMOS) transistor; forming a polysilicon gate layer on a top surface of said gate dielectric layer; performing a blanket gate ion implant operation which ion implants a first set of gate dopants into said polysilicon gate layer in said NMOS transistor area and in said PMOS transistor area; forming a gate doping photoresist pattern on a top surface of said polysilicon gate layer which exposes said top surface of said polysilicon gate layer in exactly one of said NMOS transistor area and said PMOS transistor area; performing a patterned gate ion implant operation which ion implants a second set of gate dopants into said polysilicon gate layer in said area exposed by said gate doping photoresist pattern; removing said gate doping photoresist pattern; forming a lower hard mask layer on said polysilicon gate layer; forming an upper hard mask layer on said lower hard mask layer; performing a gate etch process on said upper hard mask layer, said lower hard mask layer and said polysilicon gate layer to form an NMOS gate structure in said NMOS transistor area and a PMOS gate structure in said PMOS transistor area, said NMOS gate structure including an n-type doped polysilicon gate, said lower hard mask layer and said upper hard mask layer, and said PMOS gate structure including a p-type doped polysilicon gate, said lower hard mask layer and said upper hard mask layer; forming source/drain sidewall spacers on lateral surfaces of said n-type doped polysilicon gate and on lateral surfaces of said p-type doped polysilicon gate; performing an NMOS source/drain (NSD) ion implant operation which ion implants an NSD set of dopants into said substrate in said NMOS transistor area to form NSD implanted regions in said substrate adjacent to said source/drain sidewall spacers in said NMOS transistor area; performing a PMOS source/drain (PSD) ion implant operation which ion implants a PSD set of dopants into said substrate in said PMOS transistor area to form PSD implanted regions in said substrate adjacent to said source/drain sidewall spacers in said PMOS transistor area; removing said source/drain sidewall spacers so that a thickness of said lower hard mask layer is not reduced; removing any remaining said upper hard mask layer after said step of removing said source/drain sidewall spacers, so that a portion of said lower hard mask layer remains on said n-type doped polysilicon gate and said p-type doped polysilicon gate; performing a PMOS lightly doped drain (PLDD) ion implant operation which ion implants a PLDD set of dopants into said substrate to form PLDD implanted regions in said substrate adjacent to said p-type doped polysilicon gate in said PMOS transistor area; performing an NMOS lightly doped drain (NLDD) ion implant operation which ion implants an NLDD set of dopants into said substrate to form NLDD implanted regions in said substrate adjacent to said n-type doped polysilicon gate in said NMOS transistor area; performing a lightly doped drain (LDD) anneal on said integrated circuit which forms NMOS source/drain diffused regions in said substrate adjacent to said n-type doped polysilicon gate in said NMOS transistor area and forms PLDD source/drain diffused regions in said substrate adjacent to said p-type doped polysilicon gate in said PMOS transistor area, after said steps of performing said NSD ion implant operation, performing said PSD ion implant operation, performing said PLDD ion implant operation and performing said NLDD ion implant operation; forming a silicon-germanium (SiGe) blocking layer on an existing top surface of said integrated circuit in said NMOS transistor area so that said PMOS transistor area is exposed; forming SiGe recesses in said substrate adjacent to said p-type doped polysilicon gate in said PMOS transistor area, after said step of performing said LDD anneal; and forming SiGe source/drain epitaxial regions in said SiGe recesses, so that SiGe epitaxial material is not formed on said p-type doped polysilicon gate.