Patent ID: 6052777
Filing Date: 2000-04-18
Classification: G06F

Abstract:
A method for tracking traps within a processor, the method comprising the steps of:fetching one or more instructions from an instruction cache;providing an instruction scheduling unit having a plurality of entries with each entry corresponding to a live instruction;assigning a first of said instructions to an entry in the instruction scheduling unit;in response to said first instruction incurring a front end trap, associating the first instruction with said front end trap in the assigned entry of the instruction scheduling unit;in response to a back-end trap associated with said first instruction, associating said first instruction with said back-end trap in the assigned entry of the instruction scheduling unit;retiring said first instruction when all older instructions in the pipeline have been retired, wherein the retiring includes flushing instruction scheduling unit when the first instruction is associated with a front end or back end trap; andwhen the first instruction is associated with a front end or back end trap, invoking a trap handler.