Patent ID: 7890703
Filing Date: 2011-02-15
Classification: G06F

Abstract:
1. A method in a superscalar processor for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction, the method comprising: determining a start of a semi-synchronous memory copy operation associated with a section of a single memory, wherein the semi-synchronous memory copy operation operates semi-synchronously with the superscalar processor to provide maximum processor utilization such that the superscalar processor is able to execute at least one additional instruction on another section of the single memory during the semi-synchronous memory copy operation, and wherein the semi-synchronous memory copy operation takes virtual addresses as arguments to provide non-pinning of virtual memory pages that tolerate page faults referenced by the virtual addresses; checking the semi-synchronous memory copy operation for a given value in at least one cache injection bit, wherein the cache injection bit is associated with a given value indicating a given number of lines of destination data to be transferred; copying, based on the cache injection bit, a predefined number of lines of destination data into at least one level of cache memory; and executing at least one subsequent instruction on the memory during the copying of the predefined number of lines of destination data into the at least one level of cache memory.