Patent ID: 8737151
Filing Date: 2014-05-27
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a plurality of bit lines; a plurality of word lines; a plurality of re-writeable non-volatile resistive state memory elements (ME's), each ME is positioned at an intersection of one of the word lines with one of the bit lines, each ME including a first terminal electrically coupled with its respective word line and a second terminal electrically coupled with its respective bit line, and each ME configured to store at least one-bit of non-volatile data; pre-charge circuitry operative to apply a first voltage to the plurality of bit lines; word line circuitry operative to apply a second voltage to only one of the plurality of word lines and to apply the first voltage to a remainder of the plurality of word lines, wherein the word line having the second voltage applied to it is a selected word line and the word lines having the first voltage applied to them are un-selected word lines; bit line circuitry operative to temporarily electrically disconnect the first voltage from the plurality of bit lines during a sensing window, each bit line charged by a select current flow between the selected word line and each bit line and through a respective one of the MEs while the second voltage is applied to the selected word line, the select current flow operative to charge each bit line, to a third voltage; and sense amp circuitry operative to sense the third voltage on each bit line and to output read data indicative of the third voltage on each bit line.