Patent ID: 7783813
Filing Date: 2010-08-24
Classification: G06F

Abstract:
1. A system, comprising: a first midplane having a first and second processor cards, each of the first and second processor cards having a processor fabric; a second midplane having a third and fourth processor cards, each of the third and fourth processor cards having a processor fabric; a first node comprising the first and third processor cards in the first and second midplanes, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising the second and fourth processor cards in the first and second midplanes wherein the processor cards in the second node connect via their processor fabrics; a first cable connecting the processor fabrics of the processor cards in the first node; a second cable connecting the processor fabrics of the processor cards in the second node; and a first and second communication interfaces, wherein the first communication interface connects the first and second processor cards and wherein the second communication interface connects the third and fourth processor cards, wherein the first and second communication interfaces enable communication between the connected processor cards in the first and second nodes to coordinate processor operations between the connected processor cards in the first and second nodes, wherein the communication interfaces and processor fabrics utilize different technologies, wherein the processor cards in each of the first and second nodes that communicate over their processor fabrics function as first and second symmetrical multi-processors, wherein each processor card includes management code executed by the processor card to perform: