Patent ID: 6775752
Filing Date: 2004-08-10
Classification: G06F

Abstract:
A system comprising:a plurality of memory banks; a plurality of ports for receiving multiple entries, in a concurrent manner, to be stored in said plurality of memory banks, wherein each entry uniquely identifies a register of a processor; and match propagation logic for directing entries from said plurality of ports to respective ones of said plurality of memory banks, wherein said match propagation logic is operable to direct entries such that each received entry is directed to a respective memory bank when a previous entry identifying a matching register was stored in said respective memory bank, each received entry not directed according to matching registers is directed to a default memory bank when an entry is received by each of said plurality of ports, and an entry is randomly directed to an available memory bank when not directed according to matching registers or default memory banks, wherein when multiple concurrent entries are not directed to a same memory bank of said plurality of memory banks due to matching registers, said multiple concurrent entries are stored in said plurality of memory banks, within a same cycle, when one entry of said multiple concurrent entries identifies a matching register and the other entry of said multiple concurrent entries does not identify a matching register.