Patent ID: 7973418
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a device pad on a substrate; an under bump metal pad (UBM) on the device pad; a passivation layer on the surface of the substrate, the passivation layer having an opening to expose a portion of the device pad; a polymer layer on the passivation layer, the polymer layer extending outward away from the device pad beyond an outer edge of the UBM, wherein the UBM extends onto a top surface of the polymer layer and electrically connects to the device pad through an opening in the polymer layer; and a solder bump on the UBM, the solder bump having a generally spherical shape and having an outer surface extending beyond the outer edge of the UBM; wherein the polymer layer is fully separated from the device pad by the passivation layer and has a thickness of 10 microns or less, and a bottom surface of the UBM is in contact with a portion of the passivation layer that overlies the device pad; and wherein a shortest distance from a center of the device pad to an outer edge of the device pad, and a shortest distance from a center of the UBM to the outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.