Patent ID: 9082647
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including a first region and a second region; a plurality of contact plugs contacting the substrate in the first region; an insulation layer pattern on the substrate in the first region between ones of the plurality of contact plugs, the insulation layer pattern having a top surface that is lower than top surfaces of ones of the plurality of contact plugs relative to the substrate; a first metal oxide layer pattern on the insulation layer pattern, the first metal oxide layer pattern having a dielectric constant that is higher than that of silicon oxide; a first metal pattern on the first metal oxide layer pattern, the first metal pattern contacting sidewalls of the plurality of contact plugs; a metal line contacting top surfaces of the plurality of contact plugs and the first metal pattern; and a first planar transistor including a first gate structure containing a second metal oxide layer pattern, a second metal pattern and a third metal pattern sequentially stacked, the second metal oxide layer pattern, the second metal pattern and the third metal pattern including materials substantially the same as those of the first metal oxide layer pattern, the first metal pattern and the metal line, respectively.