Patent ID: 6414957
Filing Date: 2002-07-02
Classification: H04L

Abstract:
A parallel processor of a distributed sample scrambler, comprising:first pseudo random bit stream production means for producing a first pseudo random binary bit stream within a word parallel clock according to a predetermined ATM (Asynchronous Transfer Mode) cell supplied from the external; second pseudo random bit stream production means for producing a second pseudo random binary bit stream within a word parallel clock according to the predetermined ATM cell; selection means for selectively producing one of the first and the second pseudo random binary bit streams according to an external signal; storing means for temporally storing an output signal from the selection means to produce a temporally stored output signal to both the first pseudo random binary bit stream production means and the second pseudo random binary bit stream production means; first exclusive-OR means for performing an exclusive-OR operation with two inputs, wherein one input is an output signal from the storing means and the other input is the predetermined ATM cell; head error control signal production means for producing a head error control signal after receiving an output signal from the first exclusive-OR means; sampling means for sampling an output signal from the storing means to produce a sample value; and second exclusive-OR means for performing an exclusive-OR operation with two inputs, wherein one input is the sample value from the sampling means and the other input is the head error control signal, to produce a final ATM cell.