Patent ID: 8543774
Filing Date: 2013-09-24
Classification: G06F

Abstract:
1. A programmable logic apparatus comprising: a shared memory comprising a first port, a second port and a third port; a first vital processor interfaced to the first port of said shared memory; and a non-vital communications processor separated from said first vital processor in said programmable logic apparatus and interfaced to the second port of said shared memory, wherein the third port of said shared memory is an external port structured to interface an external second vital processor, wherein said shared memory further comprises a first memory and a second memory; wherein each of said first memory and said second memory comprises a first port and a second port; wherein the first ports of the first memory and the second memory are part of the second port of said shared memory; wherein the second port of the first memory is part of the first and third ports of said shared memory; wherein the second port of the second memory is part of the first and third ports of said shared memory; and wherein both of said first vital processor and said external second vital processor are structured to cooperatively agree that first data in said first memory corresponds to second data in said second memory, and responsively cause said non-vital communications processor to employ part of said first data and part of said second data as third data, and to output serial data based upon said third data.