Patent ID: 6271128
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A method for fabricating a transistor, comprising:providing a substrate having a sacrificial layer, a metal layer and an insulating layer in turn formed thereon;forming a patterned masking layer over the insulating layer for defining a first gate window;removing a portion of the insulating layer and the metal layer using the patterned masking layer as a mask to formed the first gate window, and a portion of the sacrificial layer is exposed to the first gate window;laterally removing a portion of the patterned masking layer;laterally removing a portion of the remained insulating layer using the remained masking as a mask to form a second gate window, wherein the width of second gate window is greater than the width of the first gate window, and the first and the second gate windows form a T-shape gate window;completely removing the patterned masking layer;performing a thermal process to form a source and a drain regions by a reaction between the metal layer and the sacrificial layer under the metal layer;removing the sacrificial layer within the T-shape gate window;forming a gate dielectric layer over the remained insulating layer and the source and drain regions; andforming a gate electrode within the T-shape gate window.