Patent ID: 6216146
Filing Date: 2001-04-10
Classification: G06F,G11C,H03K

Abstract:
An apparatus that adds two N-NARY addends that comprise 1 of N signals to produce an N-NARY sum that comprises a 1 of N signal, comprising:a 1-of-P first addend input coupled to receive the first addend wherein said 1 of P first addend input comprises a 1 of N signal where N is greater than 2;a 1-of-Q second addend input coupled to receive the second addend wherein said 1 of Q second addend input comprises a 1 of N signal where N is greater than 2; andan adder circuit that adds the addends to produce the sum, said adder circuit is coupled to said first addend input and to said second addend input, said adder circuit is further coupled to a 1-of-R sum output that is configured to deliver the sum where in said 1 of R sum output comprises a 1 of N signal where N is greater than 2.