Patent ID: 8835900
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A floating body memory cell, comprising: a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor, the first semiconductor and the second semiconductor having different energy band gaps; a buried insulator layer; a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer; a first raised source drain including a first bottom surface positioned above the bi-layer heterojunction, the first raised source drain including a first raised source drain height; a second raised source drain including a second bottom surface positioned above the bi-layer heterojunction, the second raised source drain including a second raised source drain height; and a front transistor gate including a third bottom surface positioned above the bi-layer heterojunction and between the first raised source drain and the second raised source drain, a height of the front transistor gate being greater than the first raised source drain height and the second raised source drain height; and wherein the bi-layer heterojunction extends along the first raised source drain the front transistor gate and the second raised source drain, and is in contact with the first, second and third bottom surfaces over their entire length, and wherein a first source/drain region of the floating body memory cell extends from a top surface of the first raised source drain through each of the first and second semiconductors of the bi-layer heterojunction, and wherein a second source/drain region of the floating body memory cell extends from a top surface of the second raised source drain through each of the first and second semiconductors of the bi-layer heterojunction.