Patent ID: 7968929
Filing Date: 2011-06-28
Classification: H01L

Abstract:
1. An on-chip decoupling capacitor structure, comprising: at least one deep trench capacitor having a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between said doped region and said inner electrode, said dielectric having an upper edge that terminates at a lower surface of said shallow trench isolation region; a first back-end-of-line wiring level in electrical communication with said at least one deep trench capacitor; and a second back-end-of-line wiring level being vertically electrically connected to said first back-end-of-line wiring level by vertical connectors, said first and second back-end-of-line wiring levels and vertical connectors defining at least two interdigitated electrodes so as to form a passive capacitor.