Patent ID: 6133604
Filing Date: 2000-10-17
Classification: G11C,H01L

Abstract:
A NOR array architecture allowing single bit, row, and column programming and erase operations, said NOR array architecture comprising:a plurality of ETOX cells formed in a deep n-well, each of said ETOX cell having:(1) a control gate;(2) a floating gate insulated from and formed substantially underneath said control gate;(3) a p-well in said n-well and underneath said floating gate and said control gate;(4) a drain implant formed in said p-well adjacent to said floating gate; and(5) a source implant formed in said p-well adjacent to said floating gate;wherein said ETOX cells are formed into a two-dimensional array including a plurality of rows and a plurality of columns;further wherein each of said control gates of said ETOX cells sharing a common row are connected to a row wordline;further wherein each of said source implants of said ETOX cells sharing a common row are connected to a row sourceline;further wherein each of said drain implants of said ETOX cells sharing a common column are connected to a column bitline; andfurther wherein each of said p-wells of said ETOX cells in a common column are connected together to a common p-well bias line.