Patent ID: 8279699
Filing Date: 2012-10-02
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal; and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal, wherein the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period, wherein the controller sets a level of the clock control signal corresponding to the first external command to be different than a level of a clock control signal corresponding to a second external command other than the chip enable signal, wherein the internal clock generator comprises an oscillator configured to change the first clock period of the internal clock signal in response to the clock control signal corresponding to the first external command and output a first resultant internal clock signal as the internal clock signal with the changed clock period.