Patent ID: 6812569
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A semiconductor device comprising a wiring board formed with a plurality of electrodes, a semiconductor integrated circuit chip formed with a plurality of bumps, and a sealing resin for bonding the electrodes and bumps at corresponding positions and further surrounding the bonding portions of the electrodes and bumps to adhere said wiring board and semiconductor integrated circuit chip, whereineach individual bump and adjacent bumps are formed under the condition that quantities &PHgr;A and L are in the region defined by the following formula B, (b1Ã—L/2)(b2Ã—L/2)â€ƒâ€ƒ(B) where,&PHgr;A denotes a lop diameter of a bump bonded with an electrode; L denotes an interval (distance) between adjacent bumps; b1 denotes a first coefficient; and b2 denotes a second coefficient; wherein said first coefficient b1 is about 0.75, and said second coefficient b2 is about 0.85.