Patent ID: 6815287
Filing Date: 2004-11-09
Classification: H01L,Y10S

Abstract:
A method of reducing leakage currents in a DRAM device, the method comprising:selectively implanting complementary dopant atoms within a first region of the substrate, wherein the concentration of dopant atoms in the first region of the substrate is greater than the concentration of dopant atoms outside of the first region of the substrate; and forming a plurality of field effect transistors each comprising first and second active nodes and a channel extending therebetween, wherein the field effect transistors are formed so as to overlie the first region of the substrate, and wherein the first active node is disposed in the substrate so that a substantial portion of the first active node is disposed outside of the first region of the substrate so as to reduce a junction leakage current, and wherein the channel and second active node are disposed within the first region of the substrate so as to reduce a subthreshold leakage current.