Patent ID: 8130872
Filing Date: 2012-03-06
Classification: H04B

Abstract:
1. A filter circuit comprising: an input node having a first terminal and a second terminal, wherein the input node is configured to receive a differential input signal; first, second, third, fourth, fifth, sixth, seventh, and eighth switches configured to communicate with the input node; a first load having a first terminal and a second terminal, wherein the first load is configured to selectively communicate with the input node via the first, second, third, and fourth switches; and a second load having a first terminal and a second terminal, wherein the second load is configured to selectively communicate with the input node via the fifth, sixth, seventh, and eighth switches, wherein the first terminal of the first load connects to the first terminal of the input node and the second terminal of the first load connects to the second terminal of the input node when the first and fourth switches are turned on by a first clock signal, wherein the first terminal of the first load connects to the second terminal of the input node and the second terminal of the first load connects to the first terminal of the input node when the second and third switches are turned on by a second clock signal and the first and fourth switches are turned off by the first clock signal, wherein the first terminal of the second load connects to the first terminal of the input node and the second terminal of the second load connects to the second terminal of the input node when the fifth and eighth switches are turned on by a third clock signal, and wherein the first terminal of the second load connects to the second terminal of the input node and the second terminal of the second load connects to the first terminal of the input node when the sixth and seventh switches are turned on by a fourth clock signal and the fifth and eighth switches are turned off by the third clock signal.