Patent ID: 7208364
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A method of fabricating a drain extended semiconductor device comprising: forming isolation structures on a semiconductor substrate; forming n-well regions within a DEPMOS region and p-well regions within an DENMOS region; forming a gate dielectric layer over the device; forming a gate electrode layer on the gate dielectric layer; patterning the gate dielectric layer and the gate electrode layer to form gate structures; forming n-type drain extension regions within the p-well regions; forming p-type drain extension regions within the n-well regions; forming n-type source regions within the p-well regions and n-type drain regions within the n-type drain extension regions; forming p-type source regions within the n-well regions and p-type drain regions within the p-type drain extension regions; forming a blocking layer over the n-type and p-type drain extension regions and a portion of the gate structures; forming a capacitor plate over the semiconductor substrate outside of the DENMOS and DEPMOS regions; and forming field plates over the blocking layer over a portion of the gate structures and the n-type drain extension regions within the DENMOS region and over a portion of the gate structures and the p-type drain extension regions within the DEPMOS region, wherein the field plates are formed simultaneously with forming the capacitor plate.