Patent ID: 7644388
Filing Date: 2010-01-05
Classification: G03F,H01L

Abstract:
1. A method of reducing layout printability effects on semiconductor device performance, comprising: performing a printability simulation on a mask layout over a range of lithography process conditions; identifying a layout configuration in the mask layout that is operable to induce functional or parametric failure in a semiconductor device; obtaining a test structure that is representative of the identified layout configuration, wherein a design of experiment is associated with the test structure, the design of experiment is defined to investigate effects of variations of one or more layout attributes in the test structure; fabricating multiple instances of the test structure on a wafer according to the design of experiment; measuring one or more electrical performance characteristics of the fabricated test structures; and based on the measured electrical performance characteristics, determining one or more layout attributes of the test structure that are operable to cause functional or parametric failure.