Patent ID: 6084275
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A mask ROM (mask read only memory) device on a substrate having a NMOS device region and a NMOS cell region for coding, said mask ROM comprising:an isolation structure formed between said NMOS device region and said NMOS cell region;a gate oxide with a thickness of about 15 to 200 angstroms formed on said NMOS device region;a coding oxide formed on said NMOS cell region, wherein a thickness of said coding oxide is about 200 to 800 angstroms;a polysilicon layer formed on said gate oxide of said NMOS device region;gates respectively formed on said polysilicon layer and said coding oxide;spacers formed on side walls of said gates;first N type doped ion regions formed right underneath said spacers;second N type doped ion regions with relatively heavy doped dopant to said first N type doped ion regions formed next to said first N type doped ion regions for serving as source and drain regions; anda p type conductive region formed between said first N type doped ion regions of said NMOS cell region and right underneath said coding oxide, wherein a dopant concentration of said p type conductive region is about 5E11 to 5E14 atoms/cm.sup.3.