Patent ID: 7243329
Filing Date: 2007-07-10
Classification: H03K

Abstract:
1. A method of designing an ASIC that is equivalent to an FPGA that has been programmed to implement a user's logic design, the FPGA having an architecture that includes a plurality of instances of identical logic elements (LEs), each of which has an LE architecture that includes a plurality of circuit elements, and each of which LEs has a maximum logic capability, the ASIC having an ASIC architecture that includes a plurality of instances of identical hybrid logic elements (HLEs), each of which has an HLE architecture that includes a plurality of circuit elements but that is different from the LE architecture or any portion of the LE architecture, and each of which HLEs has a maximum logic capability that is only a fraction of the maximum logic capability of one LE of the FPGA, multiple ones of the HLEs being usable together, if necessary, to perform substantially any of the functions that can be performed by any one of the LEs, comprising: synthesizing the user's logic design; mapping the synthesized logic design to an FPGA implementation of that design in which each of a plurality of portions of the synthesized logic design is implemented in a respective one of the LEs; and re-mapping each of said portions of the synthesized logic design to an ASIC implementation of that portion, the ASIC implementation of each such portion employing one or more of the HLEs.