Patent ID: 6150841
Filing Date: 2000-11-21
Classification: H03K

Abstract:
A monolithic, Complex Programmable Logic Device (CPLD) for programmably implementing designs having parallel data words that are at least B bits wide, where B is an integer equal to or greater than 32, said CPLD having a plurality of more than B I/O terminals for communicating with external circuitry, said CPLD further comprising:a plurality of macrocell modules operatively coupled to at least a subset of said I/O terminals, wherein each macrocell module includes:(a) at least first through fifth product term generators for producing respective and local first through fifth product term signals, where each product term signal can represent at least up to B times 112.5%, independent input terms or more;(b) a local SoP-producing gate, operatively coupled to receive a selected subset or all of the local product term signals and to produce therefrom a local SoP signal representing a Boolean sum-of-products of one or more of the respective and local product term signals (PT0-PT4);(c) at least first through fifth PT steerers respectively coupled each to an output of a respective one of the first through fifth product term generators, wherein each PT steerer may be programmably configured to either direct to the local SoP-producing gate or steer-away the respective one of the local product term signals (PT0-PT4);(d) a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules;(e) a post-SoP steerer that can be programmably configured to direct to the local SoS-producing gate or steer-away to SoS-producing gates of neighboring macrocell modules, the local SoP signal; and(f) a local storage or storage plus combinatorial-pass-through element having an IN terminal, internal storage operatively coupled for receiving and storing a signal applied to the IN terminal, and a Q output terminal operatively coupled for outputting a signal stored in said storage, where said IN terminal of said local storage/pass-through element is operatively coupled to receive IN signals from one or more of said local SoS-producing gate and said PT steerers.