Patent ID: 6197691
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method to fabricate shallow trench isolations in the manufacture of an integrated circuit device comprising:providing a semiconductor substrate;depositing a first etch stop layer overlying said semiconductor substrate;etching said first etch stop layer and said semiconductor substrate to form trenches;depositing a gap fill layer overlying said first etch stop layer and filling said trenches wherein said depositing is stopped before the planar top surface of said gap fill layer overlying said trenches reaches the level of the top surface of said first etch stop layer bordering said trenches;etching said gap fill layer so that said gap fill layer overlying said trenches does not contact said gap fill layer overlying said first etch stop layer;depositing a second etch stop layer overlying said gap fill layer and said first etch stop layer wherein said depositing is stopped before the planar top surface of said second etch stop layer overlying said trenches reaches the level of said top surface of said first etch stop layer;polishing down said second etch stop layer to selectively expose said gap fill layer in areas not overlying said trenches;etching away said exposed gap fill layer; andetching away said second etch stop layer and said first etch stop layer to complete fabrication of said shallow trench isolations in the manufacture of said integrated circuit device.