Patent ID: 9189245
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. A server, comprising: a first motherboard module comprising: a second motherboard module comprising: wherein the second motherboard is coupled to the first motherboard when the second QPI connector is electrically coupled to the first QPI connector; wherein when the second motherboard is not coupled to the first motherboard and when the server is powered on, the BIOS unit initiates the first CPU, the at least one first memory module, and the input/output units and sets an operation mode of the server in a first mode; wherein when the server is operated in the first mode, the first CPU processes a plurality of data processing tasks issued by input/output units; wherein when the second motherboard is coupled to the first motherboard and when the server is powered on, the BIOS unit detects the second CPU, and the BIOS unit initiates the first CPU, the at least one first memory module, the input/output units, the second CPU, and the at least one second memory module, and sets an operation mode of the server in a second mode; wherein when the server is operated in the second mode, the first CPU receives a plurality of data processing tasks issued by input/output units and the first CPU assigns one or more data processing tasks to the second CPU through the second QPI bus, and after the second CPU finishes processing the one or more data processing tasks, the second CPU sends corresponding one or more data processing results to the first CPU, and the first CPU transfers the one or more data processing results to corresponding input/output units.