Patent ID: 8996773
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A computer apparatus, comprising: a plurality of CPUs; and a chipset electrically coupled to the CPUs, wherein the chipset is configured for receiving an interrupt request sent from an external hardware device and judging whether or not a task type corresponding to the interrupt request has ever been performed by any one of the CPUs; if a judging result thereof is yes, the chipset assigns the interrupt request to the CPU that has ever performed the task type to perform a corresponding interrupt task, wherein the chipset further stores an execution-status recording list, and the execution-status recording list is configured for recording whether each of the task types has ever been performed by any one of the CPUs, wherein the chipset further stores a task-distribution recording list, the task-distribution recording list is configured for recording each of the task types corresponding to the interrupt requests that have ever been performed by which of the CPUs, when the chipset judges that the task type corresponding to the interrupt request has ever been performed by one of the CPUs, the chipset selects the CPU that has ever performed the task type from the task-distribution recording list, so as to assign the interrupt request to the selected CPU to perform the corresponding interrupt task, and wherein the corresponding task type comprises an interrupt vector.