Patent ID: 7723778
Filing Date: 2010-05-25
Classification: H01L

Abstract:
1. A non-volatile memory device, comprising: a channel region; a drain on one end of the channel region; a source on the other end of the channel region; a first trapping structure above the channel region, the first trapping structure comprising an AC side configured to constantly store an assisted charge during operation of the device that causes an abrupt electric field in the channel region; a first control gate formed over the first trapping structure; a second trapping structure below the channel region, the second trapping structure comprising an AC side configured to constantly store an assisted charge during operation of the device that causes an abrupt electric field in the channel region; and a second control gate formed below the second trapping structure, wherein each of the first and second trapping structures further comprises a data side configured to store first and second bits of information, respectively, while the AC sides of the first and second trapping structures store their assisted charges, wherein the AC side and the data side have a first threshold value and a second threshold value, respectively, and wherein the second threshold value of the data side is varied corresponding to stored data, and the first threshold value of the AC side is a near-fixed value.