Patent ID: 6477639
Filing Date: 2002-11-05
Classification: G06F

Abstract:
A method of providing a branch control instruction for use by a processor, the branch control instruction being associated with a branch instruction used for effectuating a branch operation in the processor, the method including the steps of:(a) providing a first portion in the branch control instruction for specifying a target address for the branch instruction, said first portion including a variable amount of space as needed to define said target address; and (b) providing a second portion in the branch control instruction for specifying a target address register for storing said target address; and (c) providing a third portion in the branch control instruction for specifying a prediction of whether the branch instruction is likely to need a particular target instruction; wherein the branch control instruction is locatable in advance of the branch instruction within a program so that the processor can compute said target address before the branch instruction is executed.