Patent ID: 8395253
Filing Date: 2013-03-12
Classification: H01L

Abstract:
1. A semiconductor package comprising: a substrate having a recess, a first surface coinciding with a bottom of said recess, and a second surface spaced above said first surface; a plurality of laterally spaced electrical terminals bulk metallized onto said second surface of said substrate and contained within boundaries of said substrate; an electrical conductor disposed on said first surface of said substrate, said electrical conductor including a die receiving surface electrically connected to one of said plurality of laterally spaced electrical terminals; at least one semiconductor die, said semiconductor die including a first electrode on one surface thereof and a second electrode on an opposing surface thereof, said first electrode being electrically connected to another one of said plurality of laterally spaced electrical terminals and said second electrode being electrically and mechanically coupled to said die receiving surface by a conductive adhesive; and a cover including an enclosure and a lid attached to said enclosure disposed over and enclosing said semiconductor die hermetically; wherein said plurality of laterally spaced electrical terminals is disposed along one side of said at least one semiconductor die, and extends along said second surface and under said enclosure from an interior of said enclosure to an exterior thereof.