Patent ID: 6537883
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) wafer, the MOS transistor positioned on a substrate of a semiconductor wafer, the method comprising:forming a dielectric layer covering the MOS transistor on the substrate; etching the dielectric layer to form a first contact hole through to a surface of the MOS transistor, and to form a second contact hole through to a doped region in the substrate; forming a bypass circuit on the dielectric layer and in the first and second contact hole, and a fusion area electrically connecting with the bypass circuit to electrically connect the MOS transistor and the doped region, the fusion area comprising polysilicon; and disconnecting the fusion area after formation of the MOS transistor; wherein ions in the gate oxide are transmitted to the doped region via the conductive wire so as to reduce plasma damage to the gate oxide.