Patent ID: 8658509
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, the method comprising: forming a recess in a resistor region of said semiconductor device; after forming said recessed resistor region, forming a high-k gate insulation layer and a metal-containing cap material above a transistor region of said semiconductor device and above said recessed resistor region; forming a semiconductor layer above said transistor region and said recessed resistor region, said semiconductor layer extending to a first height level above said transistor region and extending to a second height level above said recessed resistor region, said second height level being less than said first height level; forming a gate electrode structure above said transistor region and a resistive structure above said recessed resistor region by patterning said semiconductor layer; providing an insulating material above and laterally adjacent to said gate electrode structure and said resistive structure; exposing a top surface of said semiconductor layer of said gate electrode structure without exposing said semiconductor layer of said resistive structure; and removing said semiconductor layer of said gate electrode structure to thereby form a gate opening and forming a metal-containing electrode material in said gate opening while preserving said semiconductor layer of said resistive structure.