Patent ID: 6288594
Filing Date: 2001-09-11
Classification: G11C

Abstract:
A selector integrated monolithically to a CMOS technology circuit for electrically programmable memory cell devices having first and second input terminals for coupling to first (HV) and second (LV) voltage generators, respectively, the voltages from said generators being respectively a higher and a lower one, an output terminal (OUT), and first (program) and second (verify) control terminals for connection said output terminal (OUT) to the first and the second voltage generators respectively, characterized in that it comprises first circuit means (N1,N2) adapted to form a low-impedance discharge path between the output terminal (OUT) of the selector and a circuit ground, and circuit means of detecting the voltage at the output terminal of the selector (P1,N3,N4) which are coupled to the second voltage generator (LV) and adapted to deactivate said first circuit means upon the voltage at the output terminal falling to a predetermined value close to that of the voltage from the second voltage generator and adapted to send a control signal to the second control terminal through a phase generator (PHG) coupled to the first and second control terminals.