Patent ID: 6017819
Filing Date: 2000-01-25
Classification: H01L,Y10S

Abstract:
A process of fabricating an integrated circuit comprising the steps of:depositing a first layer comprising a single layer of polysilicon above a substrate;depositing a second layer comprising a single layer of amorphous silicon directly on said first layer, to a thickness of approximately 1800-3000 .ANG., wherein said amorphous silicon is used to eliminate the surface roughness of polysilicon layer and permit linewidth control during gate patterning;growing an oxide layer on said second layer;performing an anneal at a temperature of approximately 750.degree. C. and for a period of approximately 30 seconds, wherein said steps of growing an oxide layer and performing an anneal are performed to maintain the smooth surface of said amorphous silicon; andpatterning said first layer, said second layer, and said oxide layer into a composite gate electrode.