Patent ID: 6742133
Filing Date: 2004-05-25
Classification: G06F,H03K,H03L

Abstract:
A clock control circuit comprising:a delay circuit sequence including a plurality number of cascaded stages of delay circuit units, each made up of a first circuit receiving an input signal to output said input signal with a first delay time and a second circuit receiving an output signal from said first circuit to output said signal with a second delay time; a phase difference detection circuit receiving an input clock fed to said delay circuit sequence and an output clock output from said delay circuit sequence to detect a time difference between a clock period of said input clock and a delay time of said delay circuit sequence as a phase difference of said received two clocks; and a plurality of third circuits, each receiving an output signal of said first circuit of each of said delay circuit units to delay and output transition edge of said output signal of said first circuit with respective different delay time, depending on a stage number of said delay circuit unit to which belongs said first circuit in said delay circuit sequence, in terms of time obtained on equally dividing said phase difference by the number of said delay circuit units in said delay circuit sequence, as a unit; wherein said third circuits output a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of said input clock by the number of said delay circuit units in said delay circuit sequence.