Patent ID: 6654909
Filing Date: 2003-11-25
Classification: G06F

Abstract:
An apparatus comprising:an error detection component to control detection of errors in information stored in a processor resource and to output a next-entry-to-read-out signal and a parity bit signal, said error detection component including a timer, to periodically output the next-entry-to-read-out signal to the processor resource; a next pointer coupled to the timer, the next pointer to contain a pointer value, which specifies a specific piece of information to be read out from the processor resource; a move-to-processor-resource logic component coupled to the timer, the move-to-processor-resource logic component to prevent the next-entry-to-read-out signal from being sent by the timer, if information is being moved into the processor resource; a counter coupled to the move-to-processor-resource logic component, the counter to count the number of shifts needed to compute the proper parity bit; and a parity and valid bits register coupled to the counter, the parity and valid bits register to store at least one valid bit and parity bit pair; and a comparison component coupled to the error detection component, the comparison component to receive the information from the processor resource, to determine whether the information is valid, and to output a signal to indicate an error condition, if the information is invalid.