Patent ID: 6649515
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method of forming an interconnection comprising:depositing a masking material over a first conductive region of an integrated circuit substrate; depositing a dielectric material over the masking material; forming a via through the dielectric material to expose the masking material; depositing a first photoimageable material in a portion of the via over the exposed masking material such that the via is partially filled with the first photoimageable material; after depositing said first photoimageable material depositing a second photoimageable material and patterning said second photoimageable material over the dielectric material defining an area for a trench after patterning the second photoimageable material, forming a trench in the dielectric material over a portion of the via; removing the first photoimageable material from the via; extending the via through the masking material; and depositing a conductive material in the via.