Patent ID: 8006146
Filing Date: 2011-08-23
Classification: G11C

Abstract:
1. A test apparatus for testing a plurality of memories under test, wherein each of the plurality of memories under test reads or writes data corresponding to one memory block, in response to a read command or a write command, the test apparatus comprises: a failure block storage that stores, for each of the plurality of memories under test, acceptability information respectively of a plurality of memory blocks included in the memory under test; a data input/output section that is bus connected to data input/output terminals respectively of the plurality of memories under test, and communicates data with the respective data input/output terminals; a data supplying section that concurrently supplies test data to the plurality of memories under test via the data input/output section; and a writing control section that concurrently writes the test data to the plurality of memories under test, by concurrently supplying write enable signals to the plurality of memories under test in synchronization with the supply of the test data, and the writing control section, a) when concurrently writing the test data to the plurality of memories under test, reads acceptability information of a memory block corresponding to a writing address, from each of the plurality of failure block storages, and b) when the acceptability information read from the failure block storage indicates that the memory block corresponding to the writing address is a failure, masks the write enable signal to a corresponding memory under test, thereby prohibiting writing to the memory under test.