Patent ID: 7445986
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A method for fabricating a memory cell with vertical capacitor and transistor, comprising: providing a substrate with a trench; forming a capacitor at the bottom of the trench; forming a first conductive layer electrically coupled to the capacitor, the first conductive layer being isolated the substrate by a collar dielectric layer; forming a trench top oxide (TTO) layer disposed on the first conductive layer; conformably forming a gate dielectric layer disposed on the sidewalls of the upper portion of the trench; forming a doped polysilicon layer on the gate dielectric layer filling the trench; etching the doped polysilicon layer until lower the level of the substrate; forming a collar spacer on the sidewall of the trench above the doped polysilicon layer; anisotropically etching the doped polysilicon layer to expose the TTO layer employing the collar spacer as a mask; forming a metal gate filling the upper portion of the trench.