Patent ID: 9196701
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A high density trench-gated MOSFET array, expressed in an X-Y-Z coordinate system with an X-Y plane parallel to its major semiconductor chip plane, comprising: a semiconductor substrate lying parallel to the X-Y plane and partitioned, in the X-Y plane, into a MOSFET array area and a gate pickup area, wherein the MOSFET array area comprises: an epitaxial region overlying the semiconductor substrate, a body region overlying the epitaxial region, and a source region overlying the body region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array, wherein each ANCTGS comprises a stack of: each SGCEP comprises: over the MOSFET array area, a patterned dielectric region atop the MOSFET array, and a patterned metal layer atop the patterned dielectric region, whereby the patterned metal layer forms, with the MOSFET array, self-guided source and body contacts through the SGCEP, hence the LTMSRG does not affect device performance of the MOSFET array.