Patent ID: 7447058
Filing Date: 2008-11-04
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a plurality of memory cells each having a pair of inverters whose inputs and outputs are connected to each other, and holding complementary data respectively in storage nodes which are the outputs of the inverters; a power control circuit which sets a power supply voltage of the inverter having a storage node to which low level is written, to be lower than a power supply voltage of the inverter having a storage node to which high level is written, in a write operation during which the complementary data are written to said storage nodes, respectively; and complementary bit lines connected to the storage nodes of said inverters via transfer switches, respectively; wherein: said power control circuit receives write voltages supplied to said bit lines, to supply the power supply voltage to each of said inverters according to the received write voltages; said power control circuit has a pair of power control units connected to power supply terminals of each of said inverters, respectively; and each of said power control units has an nMOS transistor and a pMOS transistor arranged in parallel between an external power supply line and each of the power supply terminals and receiving at their gates a voltage that is an inverted voltage level of each of the bit lines.