Patent ID: 8149609
Filing Date: 2012-04-03
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including plural first and second wirings intersecting one another, and memory cells each provided at individual intersection between the first wiring and the second wiring, the memory cell comprising a variable resistive element, and predetermined numbers of the memory cells sharing the same first wiring to configure a page; a first control circuit configured to select a page of the memory cell array subjected to data-writing based on an address, and to supply a constant voltage to the first wiring belonging to the selected page; a writing-voltage generating circuit configured to generate plural kinds of writing voltages for programming a resistance of the variable resistive element to one of three or more values based on a write-in data specifying three or more values; and a second control circuit configured to select the page of the memory cell array subjected to data-writing based on the address, and to supply the writing voltages generated by and output from the writing-voltage generating circuit to predetermined numbers of the respective second wirings belonging to the selected page.