Patent ID: 6358833
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A method of fabricating a chip scale package for at least one semiconductor die, comprising:fabricating an integrated circuit on at least one die formed of a semiconductor material, the integrated circuit including external electrical connections on an active surface of the at least one semiconductor die; providing a discrete preformed blank made of the same semiconductor material as the at least one semiconductor die is made and having preselected surface dimensions not in excess of surface dimensions of the active surface of the at least one semiconductor die; forming a plurality of apertures in the discrete preformed blank at predetermined positions; providing a die-attach material; aligning the discrete preformed blank with the at least one semiconductor die; and bonding the discrete preformed blank with the die-attach material to the active surface of the at least one semiconductor die so that the integrated circuit may be electrically accessed through the plurality of apertures.