Patent ID: 6606575
Filing Date: 2003-08-12
Classification: G01R

Abstract:
A method for calibrating TEST signal timing of an integrated circuit (IC) tester having a plurality of probes with tips for contacting input/output (I/O) terminals on a surface of an IC, and having a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel, the method comprising the steps of, for each said tester channel:a. providing the input programming data to the tester channel so that the tester channel responds to the CLOCK signal by generating a TEST signal having a repetitive edge timing pattern at the tester channel's corresponding probe tip, b. supplying the input drive calibration data to the tester channel to adjust said delay with which the tester channel produces said TEST signal in response to the CLOCK signal, c. generating a periodic reference (REF) signal having said repetitive edge timing pattern, and d. cross-correlating the TEST signal generated at step b to said REF signal over a finite time interval to produce cross-correlation data indicating how closely the TEST signal matches the REF signal in phase.