Patent ID: 7616470
Filing Date: 2009-11-10
Classification: H01L

Abstract:
1. A method of arranging bits within a cache hierarchy implemented on multiple physical planes such that horizontal wiring distances in intra-level busses are minimized, said method comprising: co-designing physical structures of cache levels for optimizing interconnections between logically adjacent levels of said cache hierarchy, wherein said cache levels are positioned over each other; physically partitioning each said cache level into cache islands, each said cache island including a subset of congruence classes, wherein said bits within said cache hierarchy are arranged to minimize horizontal transfers between said cache levels in the cache hierarchy, wherein adjacent cache levels are arranged to include different capacities, wherein one of said cache levels in the cache hierarchy comprises a plurality of physical planes, wherein areas of each cache level are arranged to be substantially the same, and wherein said partitioning is selected to optimize a size of each said cache island.