Patent ID: 6337274
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method of forming buried bit line memory circuitry comprising:forming a word line having a pair of opposing source/drain regions on a substrate; forming a silicon comprising region over and in electrical connection with one of the pair of source/drain regions; depositing a TiNx comprising layer over the silicon comprising region, where â€œxâ€  is greater than 0 and less than 1; annealing the TiNx comprising layer in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN; after the annealing, forming an elemental tungsten comprising layer on the TiN and patterning at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer into a bit line in electrical connection with the one source/drain region; and forming a capacitor received at least partially outwardly of the bit line and in electrical connection with another of the pair of source/drain regions.