Patent ID: 7821330
Filing Date: 2010-10-26
Classification: G05F

Abstract:
1. A method of extending a semiconductor chip lifetime comprising: monitoring a chip degradation by assessing chip performance parameters or device characteristics; increasing at least one internal power supply voltage to be activated when the chip degradation reaches an end of lifetime stage; and tuning said at least one internal power supply voltage by adding discrete increments as a function of the chip degradation, said monitoring the chip degradation being performed by a threshold voltage monitor attached to a power supply voltage and outputting a control signal received by a reference voltage regulator, said reference voltage regulator having a reference voltage, an external supply voltage and a control signal as inputs, and an internal supply voltage as an output; said voltage regulator further comprising: a differential amplifier comprising a first input node, a second input node and an output node, said first input node receiving said reference voltage and said second input node connected to a first set of resistive elements; said output node connected to the gate of a second nMOSFET device; said first set of resistive elements further connected to the source of said second nMOSFET device; a current mirror circuit comprising a first pMOSFET device and a second pMOSFET device, said first pMOSFET device connected to said second nMOSFET device; both said first pMOSFET device and said second pMOSFET device connected to said external supply voltage; said second pMOSFET device connected to a second set of resistive elements; and a current switch module comprising a first current switch with a nMOSFET and a pMOSFET, a second current switch with a pMOSFET and a nMOSFET, a first adjustable current source, a second adjustable current source, and an inverter, said control signal from said threshold voltage monitor connected to the input of said inverter, said nMOSFET of said first current switch and said pMOSFET of said second current switch, the output of said inverter connected to said pMOSFET of said first current switch and said nMOSFET of said second current switch, the input of said first current switch connected to said external supply voltage, and the output of said first current switch connected the input of said first adjustable current source, the output of said first adjustable current source connected to said internal supply voltage; the input of said second current switch connected to an internal supply voltage, and the output of said second current switch connected to said second adjustable current source, and the output of said second adjustable current switch connected to ground.