Patent ID: 6445125
Filing Date: 2002-09-03
Classification: H01J

Abstract:
A flat panel display having a first substrate and a second substrate spaced apart at a predetermined interval to form a vacuum sealed cell gap and including a plurality of spacers interposed therebetween, the second substrate including a plurality of anode electrodes formed in a predetermined pattern on one side thereof and a phosphor layer formed on the pattern of the anode electrodes, the flat panel display comprising:a plurality of cathode electrodes formed in a predetermined pattern on the first substrate; an insulating layer disposed on the cathode electrodes and having a plurality of apertures formed therein; a plurality of field emission cathodes provided in the apertures of the insulating layer contacting the cathode electrodes; a gate electrode pattern comprising a plurality of gate electrodes, the gate electrode pattern being disposed on the insulating layer and having openings corresponding, in size and location, to the apertures of the insulating layer; and a plurality of focusing electrodes provided between the gate electrode pattern and the cathode electrodes, and which control the flow of electrons emitted by the field emission cathodes; wherein the focusing electrodes are formed in a predetermined shape and are disposed within the field emission cathodes.