Patent ID: 8230410
Filing Date: 2012-07-24
Classification: G06F

Abstract:
1. A computer-implemented method, comprising the steps of: before execution of a program, identifying a stretch of code within the program as an opportunity for microparallelization; before execution of the program, inserting, at the start of the stretch of code, at least one PushAndBidForParallelExecution (PABFPE) instruction; before execution of the program, inserting, at a suitable point within the stretch of code, at least one PopAndReleaseParallelExecution (PARPE) instruction; commencing execution of the program in a current paired unit comprising an execution unit and a half set of registers; when the program executes the PABFPE instruction, the PABFPE instruction determining whether or not at least one additional paired unit is available, each additional paired unit comprising an additional execution unit and an additional half set of registers; if it is determined by the PABFPE instruction that at least one additional paired unit is available, allocating an available additional paired unit for parallel execution of a portion of the identified stretch of code, continuing execution of the program in the current paired unit, and commencing parallelism work with the additional execution unit of the allocated paired unit, wherein the parallelism work includes executing the portion of the identified stretch of code; if it is determined by the PABFPE instruction that at least one additional paired unit is not available, continuing execution of the program in the current paired unit including executing the identified stretch of code.