Patent ID: 8054700
Filing Date: 2011-11-08
Classification: G11C

Abstract:
1. A semiconductor device that operates in synchronization with a system clock supplied from an outside, comprising: a synchronous circuit that generates output signals phase aligned with the system clock; a synchronous circuit selection circuit that performs switching between a synchronous circuit selection mode and a synchronous circuit non-selection mode, wherein read data is outputted by adjusting a phase deviation of an internal clock with respect to the system clock supplied from the outside, using said synchronous circuit in said synchronous circuit selection mode, and wherein the read data is output in synchronization with the internal clock without using said synchronous circuit in said synchronous circuit non-selection mode; and a reference edge specifying register that specifies an edge of the internal clock in said synchronous circuit non-selection mode, the edge of the internal clock serving as a reference for outputting the read data.