Patent ID: 6559675
Filing Date: 2003-05-06
Classification: H03K

Abstract:
A data processing system comprising:a control unit for receiving data from a main core and outputting given control signals; a level shifter for amplifying the electric potential of said given control signals and outputting corresponding driving signals; and a data output buffer for receiving said driving signals from said level shifter and outputting a driving voltage having a voltage range defined in the PCI or/and PCI-X specifications, to an input/output pad, wherein said data output buffer, being in a high impedance state to prevent a PCI mode voltage inputted to said pad from being leaked to a power source terminal when said data processing system is operated in PCI mode, comprises: a pull-up transistor having one end connected to a power source terminal; a first resistor coupled between said pad and the other end of said pull-up transistor for controlling a current flowing from said power source terminal to said pad to have a current range that complies with the PCI and PCI-X specifications; a second resistor having one end connected to said pad, for controlling a current flowing from said pad to a ground terminal to have a current range that complies with the PCI and PCI-X specifications; a pull-down transistor having one end connected to said ground terminal; a pull-down transistor protection unit coupled between the other end of said second resistor and the other end of said pull-down transistor, for controlling said pull-down transistor to make an electric potential of said other end of said pull-down transistor to come to VDD (power source voltage)â€”VTH (threshold voltage of said pull-down transistor protection unit) in said PCI mode; a leak prevention unit coupled between said pad and a gate of said pull-up transistor, for controlling said pull-up transistor to prevent said current from being leaked from said pad to said power source terminal in said PCI mode; and a pass transistor coupled between said power source terminal and said pad, for passing said driving signals generated from said level shifter, to said gate of said pull-up transistor.