Patent ID: 6580323
Filing Date: 2003-06-17
Classification: H03F

Abstract:
A circuit (1) comprising a first (6) and second (21) input terminals for receiving a differential signal and a buffer circuit, which buffer circuit comprises an input stage with a first (2, 13) and second (8,18) differential amplifiers, a first current source (22) for supplying a first current of a first polarity to the first differential amplifier (2,13), a second current source (24) for supplying a second current of opposite polarity to the second differential amplifier (8,18), in which each of the differential amplifiers (2,13; 8, 18) has a first input (5,7) coupled to the first input terminal (6) of the circuit and a second input (14,19) coupled to the second input terminal (21) of the circuit, a combination stage including a single transistor (47, 52) the combination stage comprising at least one chain with a first node (57,58) coupled to an output (4,15) of the first differential amplifier (2,13) and a second node (83,84) coupled to an output (9,41) of the second differential amplifier (8,18) and the combination stage (47,52), includes a respective main current path of the combination stage (47 or 52) being coupled between one of the first (57,58) and the second (83,84) respective nodes, a control electrode (50,55) of said combination stage (47,52) being coupled to a bias voltage (51,56), wherein the combination stage comprises a single transistor (47,52), the bias voltage (51,56) is a fixed voltage, and at least one of the two outputs (57,58,83,84) to which a node is coupled, is one output (57,58, 83, 84) of the buffer circuit.