Patent ID: 6610578
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A process of manufacturing a vertical bipolar transistor, the process comprising the steps of:providing a substrate having a surface; producing a first doped region at the surface of the substrate, the first doped region being of a first doping type; producing thick field oxide at a surface of the first doped region, the thick field oxide extending laterally outward from an opening in the field oxide to form a boundary region around the opening, the surface of the first doped region being exposed in the opening; producing a first electrically isolating layer over at least the boundary region and the surface of the first doped region exposed in the opening in the field oxide; removing a portion of the first electrically isolating layer inside the opening in the field oxide to form an extrinsic base opening exposing the surface of the first doped region, the extrinsic base opening being located at a first distance from the edges of the opening in the field oxide whereby a second portion of the first electrically isolating layer remains in contact with at least the surface of the first doped region along the edges of the opening in the field oxide; applying a doped, electrically conducting silicon layer of a second doping type opposite the first doping type over at least a portion of the boundary region, the second portion of the first electrically isolating layer, and the surface of the first doped region exposed in the extrinsic base opening; producing a second electrically isolating layer on top of the doped, electrically conducting silicon layer; removing a portion of the doped, electrically conducting silicon layer and the second electrically isolating layer inside the extrinsic base opening to form an intrinsic base opening exposing the surface of the first doped region, the intrinsic base opening being located at a second distance from the edges of the opening in the field oxide greater than the first distance whereby a second portion of the doped, electrically conducting silicon layer and the second electrically isolating layer remains in contact with at least the surface of the first doped region along the edges of the extrinsic base opening; depositing a first thin silicon dioxide layer to cover the intrinsic base opening and at least one of vertical free side walls and edge surfaces of the doped, electrically conducting silicon layer; doping by ion implantation a surface layer of the surface of the first doped region through the first thin silicon dioxide layer in the intrinsic base opening using the second doping type to produce a base doping; removing a portion of the first thin silicon dioxide layer inside the intrinsic base opening to produce an emitter opening; and doping a surface layer of the surface of the first doped region exposed in the emitter opening using the first doping type to produce an emitter doping.