Patent ID: 6628157
Filing Date: 2003-09-30
Classification: H03H,H03K

Abstract:
A delay element, comprising:an input that receives an input signal, an output, a plurality of delay stages mutually interconnected in a cascaded relationship, each stage to impose an incremental delay upon the input signal when included in a path of propagation of the input signal between the input and the output, and a selection input for a selection signal, the selection signal to determine how many of the delay stages are included in the path of propagation, at least one delay stage comprising an inverter buffer, and a delay block coupled to the inverter buffer, wherein the inverter buffer and the delay block combine to impose the incremental delay upon the input signal, and wherein an input of the inverter buffer is coupled to an input to the delay stage, and an output of the inverter buffer is coupled to an input of the delay block.