Patent ID: 6542982
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A data processor, comprising:an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions; and a bus controller for controlling access to an external bus in response to a command from said instruction execution unit, said bus controller having a plurality of instruction buffers, a flag specific to each of instruction buffers, and a buffer controller circuit; said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take, prefetching instructions to the instruction buffers each corresponding to a respective addresses designated to by said plural lower bits, from the address following a predetermined fetch address, setting the appropriate flag to valid in correspondence with the instruction prefetch, and setting the appropriate flag to invalid in response to the output of instructions prefetched.