Patent ID: 8520453
Filing Date: 2013-08-27
Classification: G11C

Abstract:
1. A device for generating a test pattern of a memory chip, the device comprising: a first logic circuit having a first input terminal for receiving a first pattern signal, a second input terminal for receiving a second pattern signal, and an output terminal for outputting a pattern enabling signal, wherein the first logic circuit is used for generating and outputting the pattern enabling signal according to the first pattern signal and the second pattern signal; a second logic circuit having a first input terminal for receiving a memory bank signal, a second input terminal for receiving a section signal, a third input terminal coupled to the output terminal of the first logic circuit for receiving the pattern enabling signal, a first output terminal for outputting a first pre-input-output signal, and a second output terminal for outputting a second pre-input-output signal, wherein the second logic circuit is used for generating the first pre-input-output signal and the second pre-input-output signal according to the memory bank signal and the section signal, and outputting the first pre-input-output signal and the second pre-input-output signal according to the pattern enabling signal; a first exclusive-OR gate having a first input terminal for receiving a third input-output signal, a second input terminal coupled to the second input terminal of the first logic circuit for receiving the second pattern signal, and an output terminal for outputting a first enabling signal, wherein the first exclusive-OR gate is used for executing an exclusive-OR logic operation on the third input-output signal and the second pattern signal to generate and output the first enabling signal; and a third logic circuit having a first input terminal coupled to the output terminal of the first exclusive-OR gate for receiving the first enabling signal, a second input terminal coupled to the first output terminal of the second logic circuit for receiving the first pre-input-output signal, a third input terminal coupled to the second output terminal of the second logic circuit for receiving the second pre-input-output signal, a first output terminal for outputting a first input-output signal, and a second output terminal for outputting a second input-output signal, wherein the third logic circuit is used for generating and outputting the first input-output signal and the second input-output signal according to the first enabling signal, the first pre-input-output signal, and the second pre-input-output signal; wherein the first input-output signal and the second input-output signal are used for writing a predetermined logic voltage to each memory cell of the memory chip.