Patent ID: 9075946
Filing Date: 2015-07-07
Classification: G01R,G06F,H03K

Abstract:
1. A method for designing a semiconductor integrated circuit comprising: creating a logical network after DFT insertion and DFT information indicating a connection state of flip-flops configuring a scan chain by performing a design for testability of inserting a DFT circuit on a logical network of the semiconductor integrated circuit; generating a test pattern using information related to the logical network after the DFT insertion and the DFT information; acquiring a maximum effective data continuing number in which a product of a same data continuing number and number of occurrences of the same data continuing number becomes maximum by analyzing the test pattern; calculating a number of grouped elements based on the maximum effective data continuing number; creating DFT information after grouping by adding grouping information for dividing the flip-flops into a plurality of groups to the DFT information using the number of grouped elements; and dividing the scan chain into a plurality of flip-flop groups according to the DFT information after grouping, and updating the logical network so as to insert a lower power consumption test circuit to each flip-flop group, the lower power consumption test circuit being configured not to provide a clock signal to the flip-flop other than a head flip-flop of the flip-flops configuring the flip-flop group in the next cycle if same data is stored in all the flip-flops configuring the flip-flop group in a certain cycle.