Patent ID: 9008261
Filing Date: 2015-04-14
Classification: G06F,H03K

Abstract:
1. A fractional frequency divider, comprising: a first divider having a divide-by ratio N, the first divider being configured to (i) receive an incoming clock signal and (ii) output a first divided clock signal having a plurality of phases; a flying-adder circuit configured to (i) fractionally divide said first divided clock signal, and (ii) output a fractionally divided, time-average-frequency clock signal, said flying-adder circuit comprising a multiplexer receiving said first divided clock signal and outputting one of said phases of said first divided clock signal, one or more registers configured to store a multi-bit value that selects said one of said phases of said first divided clock signal output by said multiplexer, and an adder or accumulator that adds a frequency control word to the multi-bit value in the register, the frequency control word F having an integer part and a fractional part, and the time-average-frequency clock signal having one or more cycles of a first length and one or more cycles of a second length; and a second divider having a divide-by ratio M, M being an integer of at least 2, the second divider being configured to (i) receive said fractionally divided clock signal, and (ii) output a second divided clock signal having only cycles of a single length, wherein for every M cycles of the time-average-frequency clock signal, the fractional part of the frequency control word defines a number of cycles of the first length and the second length.