Patent ID: 6324235
Filing Date: 2001-11-27
Classification: H03H,H04L

Abstract:
An asynchronous digital sample rate tracking apparatus for use with an asynchronous digital rate converter, the asynchronous digital rate converter having an internal data rate, the apparatus comprising:a serial buffer receiving input data at an input data rate;a write pointer at a first buffer position, the write pointer moving to a second buffer position at an input sample rate;a read pointer at a third buffer position, the read pointer moving to a fourth buffer position at a read rate, the read pointer being separated from the write pointer by a phase angle;a buffer phase detector detecting the first buffer position and the third buffer position and producing a phase error signal, the phase error signal indicating the difference between the phase angle and a desired phase angle;a differentiator receiving the phase error signal on a first cycle and a second phase error signal on a second cycle and producing a phase error rate signal, the phase error rate signal having a phase error rate signal amplitude;a pitch correction step size register providing a current pitch step size signal;a scaler receiving the phase error rate signal and the current pitch step size signal and producing a new estimated pitch correction step size based on the phase error rate signal amplitude and the current pitch step size signal; anda step size adjuster, the step size adjuster receiving the phase error rate signal, the phase error rate signal having a phase error rate sign, wherein the step size adjuster includes:a first counter responding to the phase error rate sign when the phase error rate sign is the same as a prior phase error rate sign, and producing a step size increase signal when the first counter reaches a first counter limit;a second counter responding to the phase error rate sign when the phase error rate sign is different from the prior phase error rate sign, and producing a first step size decrease signal when the second counter reaches a second counter limit; anda third counter responding to the phase error rate sign when the phase error rate sign is zero, and producing a second step size decrease signal when the third counter reaches a third counter limit,wherein the step size increase signal, the first step size decrease signal, and the second step size decrease signal are provided to the step size register to produce the current pitch step size signal.