Patent ID: 6124166
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A method of forming a lower electrode of a capacitor on a DRAM cell in a semiconductor wafer, the semiconductor wafer comprising:a Si substrate;a first dielectric layer positioned on the Si substrate, the dielectric layer comprising a contact hole extending down to the Si substrate; anda first polysilicon layer positioned on the first dielectric layer and completely filling the contact hole;the method comprising:forming a second dielectric layer on the first polysilicon layer which comprises a plurality of doped horizontal layers along a vertical direction, and the dopant densities of the plurality of doped horizontal layers being alternatively in a high and low sequence;performing a dry etching process to the second dielectric layer to form a dielectric block on the second dielectric layer above the contact hole, the periphery of the dielectric block containing a vertical side wall;forming a second polysilicon layer on the semiconductor wafer, the second polysilicon layer formed on the vertical side wall of the dielectric block comprising many hemispheric grains due to the different dopant densities of the plurality of doped horizontal layers in the dielectric block;performing an etching back process to vertically remove the second polysilicon layer on top of the dielectric block and on the first dielectric layer outside the dielectric block while maintaining the second polysilicon layer on the vertical side wall; andperforming a wet etching process to remove the dielectric block wherein the first polysilicon layer on the contact hole and the remaining second polysilicon layer is used as the lower electrode of the capacitor.