Patent ID: 6262914
Filing Date: 2001-07-17
Classification: G11C

Abstract:
A FLASH memory system comprising:an array of memory cells arranged in segments, each segment comprising:a plurality of local source lines;a plurality of local sub-bit lines arranged so that one local sub-bit line is formed between each adjacent pair of local source lines;a plurality of word lines for each of the N words per segment;a plurality of FLASH memory cells connected in an array of local rows and local columns, each memory cell having a first terminal and a second terminal;each local row connected at the drain of each memory cell to the drain of a segment switch transistor whose control gate is driven by the segment local bit line select signal, and whose source is connected to the global bit line;each local row connected at the source of each memory cell to the drain of a segment switch transistor whose control gate is driven by the segment local source line select signal, and whose source is connected to the local virtual ground;a plurality of global source lines;a plurality of virtual ground switch N-channel transistors, 945, 965 each having a first source-drain terminal coupled to said first terminal of a corresponding memory cell, a second source-drain terminal coupled to ground and a control gate receiving a corresponding segment select signal;a plurality of global bit lines;a plurality of bit select N-channel transistors, each having a first source-drain terminal coupled to said second terminal of a corresponding memory cell, a second source-drain terminal connected to a corresponding global bit line and a control gate receiving said corresponding segment select signal wherein:said FLASH memory array being arranged on a three level metal process, wherein:said global bit lines and said global source lines are placed on metal level three at the top level of the metal-oxide-semiconductor sandwich furthest from said array of memory cells,said word lines are placed on metal level two at intermediate level of the metal-oxide-semiconductor sandwich, andsaid local sub-bit lines are placed on metal level one at the bottom level of the metal-oxide-semiconductor sandwich closest to said array of memory cells.