Patent ID: 8120382
Filing Date: 2012-02-21
Classification: H03K

Abstract:
1. A programmable integrated circuit (IC), comprising: a plurality of arrangements horizontally arranged in the programmable IC, each arrangement including a first logic column, an interconnect column, and a second logic column horizontally arranged in that order within the arrangement, wherein: each interconnect column includes a plurality of programmable interconnect blocks vertically arranged in the interconnect column; each of the first and second logic columns includes a plurality of programmable logic blocks vertically arranged in the logic column; the plurality of programmable interconnect blocks in the interconnect column is equal in number to the plurality of programmable logic blocks in the first logic column; each of the programmable interconnect blocks provides a plurality of first input and output ports at a first side of the programmable interconnect block and a plurality of second input and output ports at a second side of the programmable interconnect block; each of the programmable logic blocks provides a plurality of third input and output ports on one side of the programmable logic block, the one side of each programmable logic block in the first logic column faces the one side of a corresponding programmable logic block in the second logic column and faces the first side of a corresponding one of the programmable interconnect blocks, and the one side of the corresponding programmable logic block in the second logic column faces the second side of the corresponding programmable interconnect block; the first ports and the first side of each of the programmable interconnect blocks physically mirror the second ports and the second side of the programmable interconnect block; the first ports of the programmable interconnect blocks in the interconnect column of each arrangement are coupled to the third ports of the programmable logic blocks in the first logic column of the arrangement; and the second ports of the programmable interconnect blocks in the interconnect column of each arrangement are coupled to the third ports of the programmable logic blocks in the second logic column of the arrangement.