Patent ID: 6727596
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A semiconductor integrated circuit comprising:a semiconductor chip having a periphery and a chip core spaced from the periphery; a plurality of I/O buffers located along the periphery of said semiconductor chip, each I/O buffer buffering signals input to and output from said chip core; a pair of lines including a power line and a ground line, said I/O buffers crossing and receiving power from said power line and said ground line; a plurality of input/output pads disposed on said I/O buffers, between said pair of lines and the periphery of said chip, each input/output pad outputting a signal transmitted from said chip core via a corresponding one of said I/O buffers or supplying a received signal to said chip core via the corresponding I/O buffer; a plurality of first signal bumps disposed on an inner side with respect to said pair of lines, each first signal bump being connected to at least one of said input/output pads; and a plurality of second signal bumps disposed between the periphery of said semiconductor chip and said pair of lines, each second signal bump being connected to one of said input/output pads.