Patent ID: 8132139
Filing Date: 2012-03-06
Classification: G06F

Abstract:
1. A method of designing a semiconductor device, said semiconductor device comprising an interconnect structure, wherein said interconnect structure comprises: a main interconnection formed in an interconnection layer; and a contact structure electrically connected to said main interconnection and extending from said main interconnection toward a semiconductor substrate, wherein a plurality of parameters contributing to parasitic capacitance and interconnect resistance of said interconnect structure comprise: a plurality of main parameters including a width and a thickness of said main interconnection; and at least one sub parameter different from said plurality of main parameters, wherein variation of each of said plurality of parameters from a design value caused by manufacturing variability is represented within a predetermined range, and wherein a maximum value and a minimum value of the parasitic capacitance of said interconnect structure are a maximum capacitance value and a minimum capacitance value, respectively, and a maximum value and a minimum value of the interconnect resistance of said interconnect structure are a maximum resistance value and a minimum resistance value, respectively, the method comprising: reading an interconnect structure data indicating said interconnect structure from a memory device; calculating said maximum capacitance value, said minimum capacitance value, said maximum resistance value and said minimum resistance value under a condition that respective variation amplitudes of said plurality of main parameters do not simultaneously take maximum values and variation of said sub parameter is fixed to a predetermined value; generating by using a computer, by using said maximum capacitance value, said minimum capacitance value, said maximum resistance value and said minimum resistance value, a CR-added netlist in which the parasitic capacitance and the interconnect resistance are added to a net of said interconnect structure; and performing operation verification of said semiconductor device by using said CR-added netlist.