Patent ID: 6034921
Filing Date: 2000-03-07
Classification: G11C

Abstract:
An apparatus for accessing information in at least one memory unit, comprising:a) a central processing unit for providing at least one addressing signal, a change of flow signal, and a memory request signal; andb) at least one memory unit having a memory cell array, wherein when the memory request signal is asserted, the at least one memory unit sequentially selects a plurality of memory cells in the memory cell array for accessing information therein, and wherein when the change of flow signal is asserted, a sequential selection of the plurality of memory cells by the at least one memory unit is inhibited and a predetermined memory cell is selected, determined by the at least one addressing signal, for accessing information in the predetermined memory cell; andc) a sequential select unit comprising a row sequential select unit coupled to a column sequential select unit, wherein each of the row sequential select unit and the column sequential select unit are responsive to the change of flow signal and the memory request signal for sequentially selecting the plurality of memory cells in the memory cell array.