Patent ID: 7307867
Filing Date: 2007-12-11
Classification: G11C

Abstract:
1. A plate-line driven access method for use in a ferroelectric memory having a memory unit, including a positive bit line and a negative bit line which are parallel to each other; a word line which is virtually perpendicular to the positive and the negative bit lines; a memory cell having a first transistor, a second transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor, wherein the first transistor is coupled to the word line and the positive bit line, one end of the first ferroelectric capacitor is coupled to the first transistor, the first ferroelectric capacitor being electrically coupled to the positive bit line through the first transistor when the word line is enabled, the second transistor is coupled to the word line and the negative bit line, one end of the second ferroelectric capacitor is coupled to the second transistor, the second ferroelectric capacitor being electrically coupled to the negative bit line through the second transistor when the word line is enabled, one of the first ferroelectric capacitor and the second ferroelectric capacitor is of positive polarity initially, and the other of the first ferroelectric capacitor and the second ferroelectric capacitor is of negative polarity initially; a plate line which is coupled to the other end of the first ferroelectric capacitor and the other end of the second ferroelectric capacitor; and a sense amplifier having a first phase inverter whose outlet and input ends are coupled to the positive and the negative bit lines respectively, outputting the voltage in the positive bit line after having inverted the phase of the voltage in the negative bit line, comprising a first P-type transistor and a first N-type transistor, wherein the gates of the first P-type transistor and the first N-type transistor are coupled to the negative bit line while the drain of the first P-type transistor and the drain of the first N-type transistor are coupled to the outlet end of the first phase inverter; a second phase inverter whose input and outlet ends are coupled to the positive and the negative bit line respectively, outputting the voltage in the negative bit line after having inverted the phase of the voltage in the positive bit line, comprising a second P-type transistor and a second N- type transistor, wherein the gates of the second P-type transistor and the second N-type transistor are coupled to the positive bit line while the drain of the second P-type transistor and the drain of the second N-type transistor are coupled to the outlet end of the second phase inverter; a P-switch with one end coupled to the sources of the first and the second P-type transistors and the other end coupled to a first voltage supply; an N-switch with end coupled to the drains of the first and the second N-type transistors and the other end coupled to a second voltage supply which is lower than the first voltage supply, the plate-line driven access method comprising the steps of: enabling the word line; enabling the plate line so that the first ferroelectric capacitor and the second ferroelectric capacitor have different capacitances and a first voltage difference between the positive bit line and the negative bit line is generated; enabling the N-switch so that the currents in the positive bit line and the negative bit line flow out through the first N-type transistor, the second N-type transistor, and the N-switch to generate over-driven currents and a second voltage difference between the positive bit line and the negative bit line is generated due to the different capacitances of the first ferroelectric capacitor and the second ferroelectric capacitor, the second voltage difference is larger than the first voltage difference; enabling the P-switch to have the sense amplifier be totally enabled to generate a third voltage difference between the positive bit line and the negative bit line by raising the higher voltage among the voltage in the positive bit line and the voltage in the negative bit line to high level but reducing the lower voltage to low level, the third voltage difference is larger than the second voltage difference; and enabling the sense amplifier so that the third voltage difference between the positive bit line and the negative bit line is sensed and the content stored in the memory cell is outputted accordingly, wherein the word line remains enabled after being enabled until data is outputted from the memory cell.