Patent ID: 8564346
Filing Date: 2013-10-22
Classification: H03K,H03L,H03M

Abstract:
1. An integrated circuit (IC) including a non-overlapping clock generation circuit, the non-overlapping clock generation circuit comprising: a delay lock loop (DLL) circuit having a voltage-controlled delay circuit with a delay time set by a control voltage, and the DLL circuit configured to receive an input clock signal having a given duty cycle and to generate, in response, an extended duty cycle clock signal having an extended duty cycle that varies in accordance with the delay time, and the DLL having circuitry configured to generate the control signal to set the delay time at a value at which the extended duty cycle has a predetermined value greater than the duty cycle of the input clock signal, and a clock generator circuit, configured to receive the control voltage and the input clock signal and to generate, in response, a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (t