Patent ID: 6496034
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A programmable logic array, comprising:a first logic plane that receives a number of input signals, the first logic plane having a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and wherein each of the logic cells includes; a vertical pillar extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer; and at least one single crystalline ultra thin vertical transistor that is selectively disposed adjacent the vertical pillar, wherein each single crystalline vertical transistor includes; an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer; an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer; and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.