Patent ID: 6072739
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A semiconductor memory device transmitting and receiving storage data, comprising:a) a memory cell array including first and second memory mats one of which is selected in a mutually exclusive way, each of said first and second memory mats havinga plurality of memory cells arranged in rows and columns, anda first data line for transmitting storage data stored in said memory cells;andb) an equalization circuit for setting said first data lines of said first and said second memory mats at a prescribed potential, said equalization circuit includinga switch circuit for connecting said first data line of said first memory mat and said first data line of said second memory mat,a first transfer circuit for driving a potential level of said first data line in said second memory mat to a level corresponding to an inverted logical level of said first data line in said first memory mat while said first memory mat is selected, anda second transfer circuit for driving a potential level of said first data line in said first memory mat to a level corresponding to an inverted logical level of said first data line in said second memory mat while said second memory mat is selected.