Patent ID: 6359483
Filing Date: 2002-03-19
Classification: G06F,H03L

Abstract:
A clock distribution system for synchronizing a reference clock signal of a multi-block network, the system comprising:a network that includes a plurality of circuit blocks, each of said circuit blocks having a corresponding load tap signal, said circuit blocks comprising a previous slowest circuit block and a subsequent circuit block; a phase comparator for comparing a load tap signal of said previous slowest circuit block with a delayed reference clock signal which is produced by delaying said reference clock signal and is applied to said subsequent circuit block, said phase comparator means providing a first enabling signal when said load tap signal of said previous slowest circuit block and said delayed reference clock signal are out of synchronization; an enabling circuit responsive to said first enabling signal for sequentially shifting a delay line enable command between a plurality of positions; a plurality of cascaded delay circuits arranged to delay said reference clock signal; and a multiplexer for outputting said delayed reference clock signal having a magnitude of delay determined by the position of the delay line enable command with respect to an associated one of said delay circuits; wherein, upon reaching synchronization between said load tap signal of said previous slowest circuit block and said delayed reference clock signal, said first enabling signal is removed to maintain the previously selected one of said delay circuits in operation.