Patent ID: 6275080
Filing Date: 2001-08-14
Classification: G11C,H03K

Abstract:
An enhanced single event immune latch comprising:a first PMOS transistor and a first NMOS transistor coupled together at a first drain-source region of said first PMOS transistor and a first drain-source region of said first NMOS transistor;a first PMOS isolation transistor and a first NMOS isolation transistor coupled together at first source-drain regions of said first PMOS isolation transistor and said first NMOS isolation transistor, and coupled at a second drain-source region of said first PMOS isolation transistor to a second drain-source region of said first PMOS transistor and at a second drain-source region of said first NMOS isolation transistor to a second drain-source region of said first NMOS transistor, wherein a gate of said first PMOS isolation transistor is coupled to low voltage and a gate of said first NMOS isolation transistor is coupled to high voltage;a second PMOS transistor coupled at a gate to said second drain-source region of said first PMOS and to said second drain-source region of said first isolation PMOS, wherein said second PMOS transistor is coupled at a first drain-source region to V.sub.DD ;a second NMOS transistor coupled at a gate to said second drain-source region of said first NMOS and to said second drain-source region of said first isolation NMOS, wherein said second NMOS transistor is coupled at a first drain-source region to GND;a second PMOS isolation transistor and a second NMOS isolation transistor coupled together at first source-drain regions of said second PMOS isolation transistor and said second NMOS isolation transistor, and coupled at a second drain-source region of said second PMOS isolation transistor to a second drain-source region of said second PMOS transistor and at a second drain-source-region of said second NMOS isolation transistor to a second drain-source region of said second NMOS transistor, wherein a gate of said second PMOS isolation transistor is coupled to low voltage and a gate of said second NMOS isolation transistor is coupled to high voltage;a feedback PMOS transistor coupled at a first drain-source region to said second drain-source region of said first PMOS transistor;a feedback NMOS transistor coupled at a first drain-source region to said second drain-source region of said first NMOS transistor;a third PMOS transistor coupled at a first drain-source region to a second drain-source region of said feedback PMOS transistor, and at a gate to said second drain-source region of said second PMOS isolation transistor, and at a second drain-source region to V.sub.DD ;a third NMOS transistor coupled at a first drain-source region to a second drain-source region of said feedback NMOS transistor, and at a gate to said second drain-source region of said second NMOS isolation transistor, and at a second drain-source region to GND;a data input that is coupled to said first drain-source region of said first PMOS transistor and said first drain-source region of said first NMOS transistor;a clock coupled to a gate of said first NMOS transistor and a gate of said feedback PMOS transistor; anda complementary clock of said clock coupled to a gate of said first PMOS transistor and a gate of said feedback NMOS transistor.