Patent ID: 8972790
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. A memory controller which performs data input/output with a memory, comprising: a controller section configured to transmit/receive data to/from circuit blocks and generate and output a first signal and a second signal holding a predetermined phase relationship with the first signal; an error detecting section having a FIFO memory configured to receive as an input the second signal outputted from the controller section; and a memory I/F section configured to receive as inputs the first signal outputted from the controller section and the second signal outputted from the FIFO memory of the error detecting section, perform timing adjustment for the first and second signals, and output the first and second signals after the timing adjustment to the memory, wherein the second signal outputted from the memory I/F section is outputted to the memory and is looped back to the error detecting section, and the error detecting section includes: wherein the controller section outputs a block identifying signal indicating one of the circuit blocks which is an output source of the second signal to the error detecting section, and when the comparison result of the data comparator is mismatch, the error detecting section stores the block identifying signal with the comparison result in the register.