Patent ID: 8759168
Filing Date: 2014-06-24
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: providing a semiconductor substrate; forming a buried oxide layer having a thickness of from 10 to 50 nm within the semiconductor substrate; forming a gate structure on the semiconductor substrate; defining a channel region having a thickness of from 5 to 10 nm between the gate structure and the buried oxide layer; forming a recess adjacent to the gate structure, wherein the recess extends through the buried oxide layer into the semiconductor substrate; forming a dielectric layer at a sidewall of the recess, wherein the dielectric layer at least partially covers a side of the buried oxide layer; epitaxially growing a first region within the recess wherein the first region has a lattice constant different from the lattice constant of the semiconductor substrate; and epitaxially growing a second region on the first region: wherein the first region is undoped or has a dopant concentration of less than 1·10