Patent ID: 8271765
Filing Date: 2012-09-18
Classification: G06F,Y02D

Abstract:
1. A method for managing instructions, the method comprising: receiving a first instruction at a port; responsive to determining, by a load/store unit in a processor unit, that the first instruction has a first reject condition, rejecting the first instruction; responsive to rejecting the first instruction, activating a first bit, wherein the first instruction is blocked from reissue while the first bit is activated; determining, by the processor unit, a class of rejection of the first instruction; starting a timer, wherein a length of the timer is set based on the class of rejection of the first instruction, wherein the timer is associated with the class of rejection of the first instruction; receiving a second instruction at the port; responsive to determining, by the load/store unit in the processor unit, that the second instruction has a second reject condition, rejecting the second instruction; responsive to rejecting the second instruction, activating a second bit, wherein the second instruction is blocked from reissue while the second bit is activated; responsive to the timer expiring, resetting the first bit; responsive to the timer expiring and the class of rejection of the first instruction and a class of rejection of second instruction are the same, resetting the second bit; and responsive to resetting the first bit and the second bit, allowing the first instruction and the second instruction to become eligible for reissue.