Patent ID: 6184077
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method for fabricating a crown-type capacitor of a semiconductor device, comprising the steps of:forming a plurality of bit lines on the interlevel dielectric layer in a cell region and a periphery region of a substrate;forming a third oxide layer to fill gaps existing between said plurality of bit lines in the cell region, said third oxide layer covering on the sidewalls of the bit lines;forming an etch-blocking layer using CVD and a first oxide layer over the entire structure obtained by forming said third oxide layer;forming a plurality of via-holes by anisotropically etching said first oxide layer, said etch-blocking layer and said third oxide layer, to expose said interlevel dielectric layer in said cell region;forming a silicon conductive layer, for forming a lower electrode of the crown-type capacitor, over the cell region of the structure having said plurality of via-holes to make electrical contact with said interlevel dielectric layer, and then forming a second oxide layer to fill interspaces of said silicon conductive layer in the cell region;completing said lower electrode by anisotropically etching said second oxide layer and said silicon conductive layer, to expose said first oxide layer; andremoving said first and second oxide layers.