Patent ID: 7093055
Filing Date: 2006-08-15
Classification: G06F

Abstract:
1. A semiconductor integrated circuit comprising: a first bus; a second bus; a data transfer unit to transfer data between the first bus and the second bus; a central processing unit connected to the first bus; a first module connected to the first bus; a second module connected to the second bus; and a bus control unit controlling bus arbitration for the first bus and the second bus, the data transfer unit requesting a bus access right of one of the buses for reading to the bus control unit, accessing the one bus for reading data, and releasing the bus access right of the one bus, and requesting a bus access right of the other bus for writing to the bus control unit after releasing the bus access right of the one bus and accessing the other bus for writing the data in response to one data transfer start request, the central processing unit being capable of bus access to the first module using the first bus in parallel with bus access to the second module using the second bus by the data transfer unit in response to one data transfer start request.