Patent ID: 6593817
Filing Date: 2003-07-15
Classification: H03K,H03L

Abstract:
A circuit for minimizing glitches in a phase-locked loop circuit comprising:a circuit input terminal; a phase detector having a first input and a second input, the first input coupled to the circuit input terminal; a charge pump generator coupled to the phase detector, the charge pump generator including a first and second output terminals; a signal filter coupled to the charge pump generator, the signal filter having an output; a voltage controlled oscillator having an input coupled to the output of the signal filter, and having an output terminal; a frequency divider coupled in feedback between the output terminal of the voltage controlled oscillator and the second input of the phase detector; and a compensation circuit connected between the first output terminal of the charge pump generator and the signal filter and structured to absorb an amount of the charge passed therethrough, the compensation circuit including a first switch having a first conduction terminal coupled to the first output terminal of the charge pump generator, a second conduction terminal coupled to the signal filter, and a control terminal coupled to the second output terminal of the charge pump generator such that the first switch couples the charge pump generator to the signal filter based on a control signal received from the second output terminal of the charge pump generator.