Patent ID: 6365942
Filing Date: 2002-04-02
Classification: H01L,Y10S

Abstract:
An improved MOS-gated power device on a substrate having an upper layer, said substrate comprising in said upper layer doped monocrystalline silicon of a first conduction type and including a doped well region of a second conduction type, said substrate further comprising at least one heavily doped source region of said first conduction type disposed in said well region at an upper surface of said upper layer, a gate region comprising a conductive material electrically insulated from said source region by a dielectric material, a patterned interlevel dielectric layer on said upper surface overlying said gate and source regions, and a heavily doped drain region of said first conduction type;wherein the improvement comprises: At least one body region of said second conduction type disposed in said well region at said upper surface of said substrate, said body region comprising heavily doped polysilicon.