Patent ID: 7561243
Filing Date: 2009-07-14
Classification: G02F,H01L

Abstract:
1. A liquid crystal display device comprising: a pair of substrates facing each other in an opposed manner while sandwiching liquid crystal therebetween; a plurality of gate signal lines arranged in parallel and a plurality of drain signal lines arranged in parallel while crossing the respective gate signal lines; a plurality of pixel regions each surrounded by one of the gate signal lines and one of the drain signal lines; a plurality of thin film transistors each driven by a scanning signal supplied from said one of the gate signal lines; and a plurality of pixel electrodes to each of which a video signal is supplied from said one of the drain signal lines through a respective thin film transistor formed in a pixel region thereof, wherein said respective thin film transistor includes a drain electrode connected to said one of the drain signal lines, a source electrode electrically connected to one of the pixel electrodes thorough a contact hole and spaced from said one of the drain signal lines, said source electrode is elongated in parallel with said drain signal line, said one of the gate signal lines has a first projection portion projecting towards said one of the pixel electrodes, said first projection portion is elongated in parallel with said drain signal line and arranged between said source electrode and another drain signal line without overlapping therewith in plan view, said another drain signal line is located across said pixel electrode from said drain signal line, said first projection portion has a first overlapping region overlapping with said one of the pixel electrodes and electrically insulated from said one of the pixel electrodes, and said one of the pixel electrodes has a second projection portion projecting toward a neighboring gate signal line of said one of the gate signal lines, said second projection portion has a second overlapping region overlapping with the neighboring gate signal line of said one of the gate signal lines, the first overlapping region is separated from the source electrode without overlapping in plan view, a conductive layer is formed on said one of the gate signal lines, a width of the conductive layer is wider than a width of said one of the gate signal lines, and the conductive layer is arranged across both sides of said one of the gate signal lines, a columnar spacer which is arranged to overlap with the second overlapping region and the conductive laver, the conductive layer is electrically connected with said one of the pixel electrodes through a contact hole, and a width of the columnar spacer is wider than a width of the contact hole.