Patent ID: 6707714
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A nonvolatile memory, comprising:a memory cell array, which has a plurality of bit lines, a plurality of word lines, and a segment, which is connected to said bit lines and in which a plurality of memory cells are connected in series, said word lines being connected to gates of said memory cells; and a word driver circuit, which applies a selected word line voltage to a selected memory cell word line within said segment, and applies a non-selected word line voltage, which causes the memory cells to conduct, to a non-selected memory cell word line, wherein said memory cell array is divided into a first memory cell array and a second memory cell array, and said non-selected word line voltage in said first memory cell array is set as a first voltage, and said non-selected word line voltage in said second memory cell array is set as a second voltage which is lower than said first voltage.