Patent ID: 6500716
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A method for fabricating a high voltage transistor comprising the steps of:forming a plurality of drift regions on a semiconductor substrate of a first conductive type; implanting drift ions of a second conductive type into surfaces of the drift regions of the semiconductor substrate at a first depth; implanting drift ions of the second conductive type into the surfaces of the drift regions of the semiconductor substrate at a second depth, the second depth being deeper than the first depth; implanting first conductive channel stop ions into the semiconductor substrate, thereby forming a space between the semiconductor substrate and the drift regions; forming a device isolation film on a surface of the semiconductor substrate into which the channel stop ions are implanted; forming a gate electrode by inserting a gate insulating film on the semiconductor substrate between the drift regions; and forming a source/drain impurity diffusion region of a second conductive type in the surface of the semiconductor substrate at both sides of the gate electrode.