Patent ID: 6754115
Filing Date: 2004-06-22
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory array including a plurality of first memory blocks including memory cells having a high data rewrite frequency, a second memory block including memory cells having a low data rewrite frequency and a redundancy memory block for use in substitution for a defective memory block among said plurality of first memory blocks; a control circuit determining whether or not a defect arises in each of said plurality of first memory blocks, which is an object for data writing, when data writing is performed on each of said plurality of first memory blocks, and storing defect information for indicating said defective memory block into a first region of said second memory block if a defect is detected; and a select circuit for selecting said redundancy memory block in association with selection of said defective memory block based on said defect information stored in said first region of said second memory block and select information for indicating selection of each of said plurality of first memory blocks.