Patent ID: 6927143
Filing Date: 2005-08-09
Classification: H01L

Abstract:
1. A method of manufacturing a capacitor of an integrated circuit device comprising: forming a first insulation layer on a semiconductor substrate; forming a buried contact hole in the first insulation layer; forming a buried contact plug in the buried contact hole to partially fill the buried contact hole; forming a diffusion barrier spacer on the contact plug and on an inner side surface of an upper portion of the buried contact hole above the buried contact plug; subsequently forming an etching stop layer and a second insulation layer on the semiconductor substrate including the buried contact hole and the buried contact plug; partially etching the second insulation layer and the etching stop layer to form a through hole to expose a top surface of the buried contact plug and the diffusion barrier spacer, the through hole having a diameter that is larger than of the buried contact hole; forming a barrier layer on a bottom and a side surface of the through hole along a surface profile of the through hole; forming a lower electrode on the barrier layer; forming a dielectric layer on the lower electrode and an upper surface of the second insulation layer; heat treating the dielectric layer in an oxidation atmosphere to crystallize the dielectric layer; and forming an upper electrode on the dielectric layer.