Patent ID: 6374370
Filing Date: 2002-04-16
Classification: G06F,G11C

Abstract:
A method of debugging and monitoring the performance of a microprocessor having a built-in-self-test (BIST) engine, comprising the steps of:defining an event by configuring an on-chip state machine to detect when a combination of state machine inputs is asserted, said combination of state machine inputs corresponding to said event, wherein said event may occur at any time during operation of the microprocessor and wherein the combination of state machine inputs may be asserted at any place on the microprocessor; defining an action to be taken when said event occurs by configuring said on-chip state machine to drive control information onto a state machine output bus when said event occurs, said control information corresponding to said action; executing instructions on said microprocessor until said event occurs; and in response to said event occurring, controlling one or more monitor-and-debug elements of the microprocessor within the BIST engine with the control information to perform one or more monitor or debug operations.