Patent ID: 6693634
Filing Date: 2004-02-17
Classification: G06T

Abstract:
A processing circuit for performing the operation shown in the following equation M=log2q+maxe using binary data q having an integer part and a decimal part and data maxe comprised by only an integer part and calculating a reduction ratio LOD using the data M, comprising:a normalization circuit for normalizing the data q to generate an exponent qe and a mantissa qm; a data outputting means for receiving as its input the mantissa qm and outputting data &mgr; indicating â€œlog2({1, qm})âˆ’qmâ€  where {1, qm} indicates a bit coupling where â€œ1â€  is the integer part and â€œqmâ€  is the decimal part; a first adder circuit for adding data obtained by bit coupling of the data qe and the qm and data obtained by bit coupling of the data maxe and the data &mgr; and outputting data M; a shift circuit for receiving data M and shifting the data M toward the MSB by a number indicated by data L; a second adder circuit for adding the data from the shift circuit and data K; and a clamp circuit for clamping the data from the adder circuit to a predetermined number of bits to generate the reduction ratio LOD.