Patent ID: 7395418
Filing Date: 2008-07-01
Classification: G06F

Abstract:
1. A method for improving the performance of a processor that supports speculative execution, wherein when a first thread encounters a halt sequence which is used by the first thread to wait for data that is to be generated by a second thread, the method comprises: starting a transactional memory operation by generating a checkpoint and entering transactional-execution mode, wherein instructions are speculatively executed but results are not committed to the architectural state of the processor until the transaction completes without interference; loading from a mailbox address associated with the halt sequence so that a transactional memory system can detect a subsequent interference with the load from the mailbox address, wherein the subsequent interference with the load from the mailbox address indicates that the halt sequence is to be terminated; and while executing in a speculative-execution mode, stalling execution of the first thread, so that the processor does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads; wherein when the second thread has completed generating the data required by the first thread, the second thread performs a store operation to the mailbox address and a transactional-memory mechanism within the processor terminates the halt sequence by: continuing execution of instructions following the halt sequence.