Patent ID: 6777295
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A method of fabricating trench power MOSFET, comprising the steps of:providing a silicon substrate; forming an epitaxial silicon layer on the substrate, wherein the epitaxial silicon layer serves as a drain region; forming a field oxide layer on the epitaxial silicon layer; removing a portion of the field oxide layer to form a device region; performing a first implanting step on the device region to form a first doped region; performing a second implanting step on the first doped region of the device region to form a second doped region in a portion of the first doped region; performing a first patterned etching to form a plurality of trenches in the device region, wherein a depth of the trenches is greater than that of the first doped region; sequentially forming a gate oxide layer and a polysilicon layer on the second doped region to fill the trenches defining a gate region; performing a second patterned etching to form a gate mask layer and to cover the polysilicon layer of the trenches, wherein a portion of the second doped region between the trenches is exposed and defines a base region, and a width of the gate mask layer is greater than that of the base region; stripping the gate mask layer to expose the polysilicon layer in the trenches; etching a portion of the polysilicon layer to expose the gate oxide layer and simultaneously etching the base region to expose the first doped region to form an aligned source region, wherein the source region is positioned between the base region and the gate region; and forming a contact region in the source region and performing a metallization step to connect source region and the base region.