Patent ID: 9052993
Filing Date: 2015-06-09
Classification: G06F

Abstract:
1. A multi-core processor system comprising: a memory unit configured to store, for each input destination thread defined as a thread to which given data is input, identification information of an assignment destination core for the input destination thread; an updating unit configured to update, if assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; a detecting unit configured to detect a writing request for the given data; an identifying unit configured to identify based on the given data for which the writing request is detected by the detecting unit, the updated identification information among information stored in the memory unit; and a storing unit configured to store the given data to a memory of the assignment destination core for which the updated identification information is identified by the identifying unit, the assignment destination core being among cores making up the multi-core processor.