Patent ID: 9015397
Filing Date: 2015-04-21
Classification: G06F

Abstract:
1. A system for optimizing direct memory access (DMA) data transfer from a single source device to a plurality of destination devices on a computer bus, the system comprising: a first DMA control circuit configured to transfer a payload of data from the source device to a first destination device, the payload of data divided into a plurality of chunks of data; a second DMA control circuit configured to transfer the payload of data from the source device to a second destination device, and configured to perform a logical operation on the data transferred to the second destination device; a synchronization controller operatively coupled to the first DMA control circuit and to the second DMA control circuit, and configured to control each DMA control circuit to independently transfer the chunk of data, wherein the synchronization controller is configured to receive a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data; and the synchronization controller configured to facilitate transfer of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data.