Patent ID: 6756630
Filing Date: 2004-06-29
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a semiconductor substrate including a memory cell region and a peripheral circuitry region; a first transistor placed at said memory cell region and on said semiconductor substrate; and second and third transistors placed at said peripheral circuitry region and on said semiconductor substrate and formed in a well region of a first conductivity type, said first transistor serving as a nonvolatile memory device capable of writing, erasing and reading information by being applied with a predetermined voltage, said second and third transistors each including a gate electrode formed on a main surface of said semiconductor substrate, a first pair of diffusion layers formed in respective active regions adjacent to two lateral sides respectively of said gate electrode and having a first impurity concentration of impurities of a second conductivity type different from said first conductivity type, an interlayer insulating film formed to cover said gate electrode and said first pair of diffusion layers, and paired contacts electrically connected respectively to the diffusion layers of said first pair of diffusion layers through said interlayer insulating film, said paired contacts including respective contact bodies extending upward from said main surface and respective contact-connected diffusion layers locally having a second impurity concentration higher than said first impurity concentration in respective regions in the vicinity of respective contact regions between said contact bodies and said semiconductor substrate, said second and third transistors are identical in terms of the death of said first pair of diffusion layers from said main surface, said second and third transistors are identical in terms of the depth of said contact-connected diffusion layers from said main surface, said first pair of diffusion layers and said contact-connected diffusion layers of said third transistor are in direct contact with each other at said main surface, said second and third transistors are different from said first transistor in terms of the structure of the diffusion layers formed at said main surface with the sate electrode interposed between the paired diffusion layers, said second transistor being connected to an interconnection to which a voltage of at most a predetermined first level is applied, said third transistor being connected to an interconnection to which a voltage of a second level higher than said first level is applied, the distance between the contact body of said third transistor and the gate electrode thereof is longer than the distance between the contact body of said second transistor and the gate electrode thereof, and the distance between the contact-connected diffusion layer of said third transistor and the gate electrode thereof is longer than the contact-connected diffusion layer of said second transistor and the gate electrode thereof.