Patent ID: 6610570
Filing Date: 2003-08-26
Classification: H01L,Y10S

Abstract:
A method of forming a double-bit non-volatile memory, comprising the steps of:providing a substrate; forming a plurality of isolation lines on the substrate; forming a multi-layered structure over the substrate, wherein the multi-layered structure includes, from bottom to top, a tunnel layer, a first conductive layer, an inter-gate dielectric layer and a second conductive layer; patterning the multi-layered structure to form a plurality of linear multi-layered structures, wherein the linear multi-layered structures all run in a direction perpendicular to the isolation lines, and each pair of neighboring linear multi-layered structures forms a linear unit; forming a plurality of bit lines and a plurality of source/drain regions over the substrate between the linear units and forming a plurality of doped regions in the substrate in the area between the two linear multi-layered structures within each linear unit, wherein the bit lines and the isolation lines cross each other to form a plurality of grid units, and the doped regions and the source/drain regions are doped identically; patterning the linear multi-layered structures to form a plurality of stacked gate structures so that each grid unit includes a pair of stacked gate structures, wherein each stacked gate structure includes a floating gate obtained from the first conductive layer and a control gate obtained from the second conductive layer; and forming a plurality of word lines over the stacked gate structures, wherein the word lines run in a direction perpendicular to the bit lines, and the two control gates within each grid unit are respectively connected to a neighboring word line.