Patent ID: 8717218
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A regular expression pattern matching circuit for use with a data processing system for processing an input code sequence to check whether the input code sequence is matched to a pattern predefined by a regular expression, which comprises: an input interface having a data input port, an enable signal input port, and a clock signal input port; a comparator circuit module, which includes multiple layers of logic circuits and a plurality of output ports, wherein the multiple layers of logic circuits are used to perform predefined comparison operations on each character of the input code sequence to thereby determine the meaning of each character in the input code sequence; a data signal delay circuit module, which includes at least one stage of buffer array coupled to the output of at least one layer of the multiple layers of logic circuits in the comparator circuit module for providing a pipeline architecture in the comparator circuit module; an enable signal delay circuit module, which includes at least one stage of buffer unit that is at the same stage as the buffer array of the data signal delay circuit module and coupled to the enable signal input port for providing a synchronized pipeline architecture with the pipeline architecture in the comparator circuit module; and a regular expression pattern matching module, which is connected to the output of the buffer array of the data signal delay circuit module and includes an array of pattern matching units each of which is preset to one regular expression defined pattern for comparing whether the output of the comparator circuit module is matched to the predefined pattern.