Patent ID: 6287967
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A self-aligned silicide process, comprising the steps of:providing a semiconductor substrate comprising a transistor formed thereon, wherein the transistor has a polysilicon gate on the semiconductor substrate, a spacer on the side-wall of the gate, and source/drain regions within the semiconductor substrate beside the gate;forming a metal layer over the semiconductor substrate;performing a first rapid thermal process to make the metal layer react with the gate and the source/drain regions to form a first metal silicide layer;removing a part of the metal layer, which does not react with the gate and the source/drain regions;selectively forming a second metal silicide layer on the first metal silicide layer; andperforming a second rapid thermal process to transform the first metal silicide layer and the second metal silicide layer from a high-resistance phase into a low-resistance phase.