Patent ID: 6401233
Filing Date: 2002-06-04
Classification: G06F

Abstract:
A wiring condition processing method for a semiconductor integrated circuit, the method comprising:creating layout information to determine a layout of devices on the semiconductor integrated circuit based on logic information describing connections of the devices on the semiconductor integrated circuit; determining a virtual wiring path from the layout information; calculating a wiring delay value based on the virtual wiring path; upon the calculated wiring delay value of the virtual wiring path exceeding a predetermined reference value, calculating a wiring delay value of the virtual wiring path when a wide wiring line is used at a predetermined usage ratio; upon the wiring delay value of the virtual wiring path when the wide wiring line is used at the predetermined usage ratio not exceeding the predetermined reference value, calculating a minimum usage ratio of the wide wiring line such that the wiring delay value satisfies the predetermined reference value; and adding information on the calculated minimum usage ratio of the wide wiring line to information on the virtual wiring path to create wiring condition information.