Patent ID: 8134382
Filing Date: 2012-03-13
Classification: G01R,G06F,H01L

Abstract:
1. A semiconductor wafer, comprising: a plurality of integrated circuit (IC) die areas for accommodating IC die that implement a circuit function comprising at least a first subcircuit that includes at least one matched component portion comprising at least two matched devices, wherein said first subcircuit is arranged in a layout on said IC die; a plurality of scribe line areas having a scribe line width dimension interposed between said plurality of IC die areas, and at least one subcircuit-based test module (TM) positioned within respective ones of said plurality of scribe line areas, said subcircuit-based TM implementing a schematic for said first subcircuit with a TM layout that copies said layout on said IC die for at least said two matched devices in said matched component portion and alters said layout on said IC die for a portion of said first subcircuit other than said two matched devices to fit said TM layout of said first subcircuit within said scribe line width dimension.