Patent ID: 6578169
Filing Date: 2003-06-10
Classification: G01R,G11C

Abstract:
A semiconductor test system for testing a semiconductor device under test (DUT), comprising:a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT for testing the DUT; means for evaluating an output signal of the DUT by comparing the output signal with an expected signal and producing failure data when there is a mismatch therebetween; a data failure memory for storing the failure data caused by the mismatch between the output signal and the expected signal; compaction means for assigning a plurality of series addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred in response to the test pattern produced by the pattern data within each group of the plurality of series addresses of the pattern memory is stored in a corresponding single address of the data failure memory in a predetermined compaction ratio, and means for executing a second test operation by the test pattern produced only by a group of plurality of addresses of the pattern memory for which the failure data is detected in the data failure memory without an address compaction between the pattern memory and the data failure memory and storing failure data occurred with respect to an address of the pattern memory in a corresponding address of the data failure memory.