Patent ID: 6034912
Filing Date: 2000-03-07
Classification: G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit device, comprising:a first logic circuit block formed on a main surface of a semiconductor substrate;a second logic circuit block formed on said main surface of said semiconductor substrate;a first memory block formed on said main surface of said semiconductor substrate; anda second memory block formed on said main surface of said semiconductor substrate, said first logic circuit block being arranged, in a first direction, between said first memory block and said second memory block, said second memory block being arranged, in said first direction, between said first logic circuit block and said second logic circuit block, data processing for said first memory block and said second memory block being performed by said first logic circuit block, each of said first and second memory blocks including:a plurality of memory cells;a plurality of word and data lines electrically coupled to said plurality of memory cells;a sense circuit; andan address decoder;wherein each of said logic circuit blocks includes a plurality of basic cells; anda clock distributing circuit board formed on said main surface of said semiconductor substrate and arranged, in said first direction, between said second memory block and said second logic circuit block, the clock signal being distributed from said clock distributing circuit to said first and said second logic circuit block.