Patent ID: 6323074
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A method of constructing a high voltage electrostatic discharge (ESD) protection device using a modified drain of an n-channel metal oxide semiconductor (NMOS), comprising the steps of:providing a semiconductor wafer with a p-substrate;providing a first n-channel transistor with a first n+ source, an n-type doped drain (ndd) area, and a first polysilicon gate;starting said ndd area where said polysilicon gate ends;implanting first and second n+ drains in said ndd area;implanting a first p+ diffusion between said first and said second n+ drain, said p+ diffusion separated by spaces from said first and said second n+ drain;implanting an n-well in said ndd area, said n-well extending from under said first n+ drain to under said second n+ drain, said n-well extending, in addition, below the depth of said ndd area;implanting a second p+ diffusion adjacent to said first n+ source;connecting said second p+ diffusion and said first n+ source to a reference voltage;forming a second n-channel transistor comprised of a second n+ source, a second polysilicon gate and said second n+ drain by implanting said second n+ source in said p-substrate and disposing said second polysilicon gate between said second n+ source and where said ndd area ends;connecting by conductive means said first, said second n+ drain, and said first p+ diffusion;protecting said first and said second n-channel transistor by utilizing an intrinsic parasitic silicon controlled rectifier (SCR) as said ESD protection device, said SCR further comprised of:a parasitic pnp bipolar transistor formed by said first p+ diffusion, said n-well, and said p-substrate; anda parasitic npn bipolar transistor formed by said second n+ source, said p-substrate, and said ndd area.