Patent ID: 7242738
Filing Date: 2007-07-10
Classification: G11B,H03L

Abstract:
1. A Phase detector for a phase-locked loop for digital input signals in which the digital summed value for a particular number of bits is equivalent to zero, said phase detector having a plurality of sampled and digitized digital sample value being supplied to said phase detector, comprising a delay stage for delaying the digital sample values by one or more sampling clock periods, a subtraction stage, to which the undelayed and the delayed digital sample values are supplied to produce a differential value, and a filter or control stage, to which the output of the subtraction stage is supplied at the output of the filter or control stage which a phase error can be tapped off, characterized in that a processing stage is provided, located between the subtraction stage and the filter or control stage, which assigns one of a plurality of possible output values, to the differential value, wherein a full differential value range is subdivided in a number of sub-ranges corresponding to the plurality of possible output values, so that each differential value falling within one of the sub-ranges will get a same output value assigned.