Patent ID: 6229861
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A clock distribution network for an integrated circuit (IC) comprising:a clock synthesizer coupled to receive an external clock signal and generate an internal clock signal therefrom;a conductivity tree comprising a passive network having a root node and a plurality of branch interconnects, the root node of the conductivity tree being coupled to the clock synthesizer with the plurality of branch interconnects being distributed about the IC, the branch interconnects each having a characteristic impedance that is substantially matched to one another;a plurality of local deskewing clock generators (DCGs) distributed about the IC, each DCG being coupled to a corresponding branch interconnect of the conductivity tree and functioning as a zero-delayed buffer for generating a local clock signal from the internal clock signal, the local clock signal driving logic circuitry of the integrated circuit in temporal proximity to the DCG.