Patent ID: 7528009
Filing Date: 2009-05-05
Classification: H01L

Abstract:
1. A wafer-leveled chip packaging method, comprising following steps: (A) providing a wafer having an integrated circuit, wherein said wafer has a first surface on which a plurality of pads is mounted; (B) forming a first insulating layer on said first surface of said wafer; (C) forming a plurality of first conductive vias penetrating said first insulating layer, wherein parts of said first conductive vias are connected with said pads; (D) forming a first conductive pattern layer on the surface of said first insulating layer which is opposite to said wafer, wherein said first conductive pattern layer is electrically connected with said first conductive vias; (E) forming a plurality of through holes penetrating said wafer so that parts of said first conductive vias contacting with said wafer are exposed; (F) filling a second insulating layer in said through holes; and (G) forming a plurality of second conductive vias in said second insulating layer within said through holes, and said second conductive vias are electrically connected with said first conductive vias.