Patent ID: 6148348
Filing Date: 2000-11-14
Classification: G06F

Abstract:
A bridge for a multi-processor system, the bridge comprising a first processor bus interface for connection to an I/O bus of a first processing set, a second processor bus interface for connection to an I/O bus of a second processing set, and a device bus interface for connection to a device bus, wherein the device bus interface is operable to convey transactions initiated by the first and second processing sets on the device bus, and wherein the bridge further comprises a bridge control mechanism configured to be operable to monitor operation of the first and second processing sets in a combined, lockstep, operating mode and to detect a lockstep error, wherein in response to detection of the lockstep error the bridge control mechanism causes the bridge to be operable in an error mode in which write accesses initiated by the processing sets are stored in a bridge buffer pending resolution of the error mode.