Patent ID: 6037220
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating a stacked capacitor structure, for a DRAM device, on a semiconductor substrate, comprised of a polysilicon storage node structure, a dielectric layer, and an upper polysilicon electrode, with the storage node structure exhibiting a smooth top surface topography, and hemispherical grain, (HSG) polysilicon sidewalls, comprising the steps of:providing a transfer gate transistor, on said semiconductor substrate, comprised of a polysilicon, or polycide gate structure, on a gate insulator layer, with source and drain regions in said semiconductor substrate;forming a composite insulator layer on said transfer gate transistor;planarizing said composite insulator layer;opening a storage node contact hole, in said composite insulator, exposing the top surface of a source and drain region, of said underlying transfer gate transistor;depositing a polysilicon layer on top surface of said composite insulator layer, completely filling said storage node contact hole;depositing a capping insulator layer on said polysilicon layer;patterning to create a polysilicon shape, comprised of the overlying capping insulator layer, contacting said source and drain region, in said storage node contact hole;depositing an HSG polysilicon layer;anisotropic etching to remove said HSG polysilicon layer from the top surface of said composite insulator layer, and from top surface of said capping insulator layer, creating said polysilicon storage node structure with HSG polysilicon sidewalls on said polysilicon shape, and with said capping insulator layer on said polysilicon shape;removing said capping insulator layer from top surface of said polysilicon shape;forming said dielectric layer on said polysilicon storage node electrode; andforming said upper polysilicon electrode structure, on said dielectric layer.