Patent ID: 6609241
Filing Date: 2003-08-19
Classification: G06F

Abstract:
A method of designing a wiring comprising: classifying a functional block into a top level and a macro, said top level being at a higher level than said macro; arranging a top level wiring connecting said top level and said macro; providing a delay model of said macro; calculating a delay between said top level and said macro based on said delay model; and arranging a macro wiring in said macro based on said delay; wherein said macro comprises a first macro and a second macro, and wherein the step of providing a delay model comprises providing a first delay model corresponding to said first macro and providing a second delay model corresponding to said second macro; defining an output terminal of said top level that outputs a signal to said first macro and said second macro, wherein the step of calculating a delay between said top level and said macro further comprises calculating a first delay for a path between said output terminal and said first macro and a second delay for a path between said output terminal and said second macro, the calculating of first and second delays being based on said first delay model and said second delay model.