Patent ID: 6285574
Filing Date: 2001-09-04
Classification: G11C,H01L

Abstract:
A memory array comprising:a plurality of groups of memory cells, each group of memory cells comprising:a first bit line, a second bit line, a third bit line, and a fourth bit line;a first metal line and a second metal line for allowing selected voltages to be supplied to said first, second, third, and fourth bit lines;a first two-terminal select transistor and a second two-terminal select transistor, wherein a first terminal of each first and second select transistor is electrically connected to said first metal line;a third two-terminal select transistor and a fourth two-terminal select transistor, wherein a first terminal of each third and fourth select transistor is electrically connected to said second metal line;first, second, third, and fourth material electrically connecting a second terminal of each of said first, said second, said third, and said fourth select transistors to said first, said third, said second, and said fourth bits lines, respectively;first, second, third, and fourth select lines for supplying selected voltages to a conductive gate of each of said first, said second, said third, and said fourth select transistors respectively;a first plurality of memory cells connected between said first, and second bit lines, a second plurality of memory cells connected between said second and third bit lines, a third plurality of memory cells connected between said third and fourth bit lines, and a fourth plurality of memory cells connected between said fourth bit line and a fifth bit line, wherein said fifth bit line is a first bit line in a next group of memory cells in a same row, or is an extra bit line adjacent a last group of memory cells in the same row;wherein said array is configured such that to write to, read, or erase a selected memory cell in said first, said second, said third, or said fourth plurality of memory cells, selected voltages are supplied to said first and said second metal lines, and a combination of said first, second, third, and fourth select transistors is turned on to pass the voltages on said first and second metal lines to said selected memory cell.