Patent ID: 9136393
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method comprising: forming a selection gate and a control gate for a flash memory cell in a memory device region, wherein the selection gate and the control gate are over a semiconductor substrate; forming a protection layer to cover the selection gate and the control gate; forming stacked layers in a logic device region, wherein the stacked layers are over the semiconductor substrate, and wherein the stacked layers extend to overlap the selection gate and the control gate; patterning the stacked layers to form a gate stack for a logic device in the logic device region; after the patterning, performing an etching step to etch a residue of the stacked layers in a boundary region of the memory device region; after the etching step, removing the protection layer from the memory device region; and forming source and drain regions for each of the flash memory cell and the logic device.