Patent ID: 9021279
Filing Date: 2015-04-28
Classification: G06F

Abstract:
1. A multi-core processor comprising: a first processing core comprising an out-of-order execution core having a first plurality of pipeline stages to process instructions out-of-order, the first plurality of pipeline stages including but not limited to a decode stage and an execution stage, a first voltage modification circuit, a first clock modification circuit, and a first power control logic to control at least one of the first voltage modification circuit and the first clock modification circuit based on a combination of conditions of the first processing core including a thermal condition; a second processing core comprising an in-order execution core having a second plurality of pipeline stages to process instructions in-order, a second voltage modification circuit, a second clock modification circuit, and a second power control logic to control at least one of the second voltage modification circuit and the second clock modification circuit based on a combination of conditions of the second processing core including a thermal condition; wherein the first clock modification comprises a first phase-locked loop (PLL) to adjust a first clock frequency for the first processing core responsive to the first power control logic; and wherein the second clock modification comprises a second PLL to adjust a second clock frequency for the second processing core responsive to the second power control logic, independently from the first clock frequency.