Patent ID: 8046727
Filing Date: 2011-10-25
Classification: G06F

Abstract:
1. A system for organizing IP cores in three dimensional FPGAs in a three dimensional system on a chip (3D SoC), comprising: a multi-layer FPGA; a multi-layer hybrid IC; SRAM memory components on at least one FPGA layer; LUTs in FPGA SRAM components; soft IP cores; wherein the IP cores include netlists; wherein at least one IP core accesses a memory component to change an FPGA layer program code; wherein an IP core program code is forwarded to a switch matrix apparatus on a FPGA layer; wherein the IP core program code activates at least one logic block array on a FPGA layer tile to reconfigure its interconnects from one ASIC position to another ASIC position when specific criteria are satisfied; and wherein when the FPGA layer in at least one logic block array are activated, they change their interconnection configuration to a new geometric position.