Patent ID: 6097665
Filing Date: 2000-08-01
Classification: G11C,H03K

Abstract:
A semiconductor memory device comprising:a plurality of memory cells arranged in a matrix of rows and columns;a plurality of word lines arranged corresponding to said plurality of rows, respectively, and each of the word lines connected to the memory cells in the corresponding row;voltage generating means for generating a voltage of a first polarity;first decoding means for decoding a first address signal and generating a word line group specifying signal specifying a word line group including a predetermined number of word lines among said plurality of word lines;second decoding means for decoding a second address signal and generating a word line specifying signal having an amplitude between a voltage of the first polarity and a voltage of a second polarity and specifying one word line among said word line group; anda plurality of word line drivers provided corresponding to said plurality of word lines, respectively, and divided into groups each corresponding to said predetermined number of word lines, each of the word line drivers including a first node receiving an output of said second decoding means, a second node receiving a voltage generated by said voltage generating means, a third node receiving a corresponding word line group specifying signal, a first drive element applying the signal applied to said first node onto a corresponding word line when said output applied to said third node is active, and a second drive element transmitting said voltage of said first polarity applied to said second node onto the corresponding word line when said output applied to said third node is inactive.