Patent ID: 8649241
Filing Date: 2014-02-11
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a bus master which transmits data by way of a bus; a bus slave receiving the data by way of the bus; and a memory device to which the data received in the bus slave is transferred, wherein the bus master transmits the data in synchronism with a first clock, the memory device operates in synchronism with a second clock which is in an asynchronous relation with the first clock and which is faster than the first clock, and the bus slave includes: a synchronizing unit connected to the bus, the synchronizing unit receiving the data in synchronism with a third clock which is in synchronous relation with the second clock and which is slower than the first clock; and a speed-enhancing unit which enhances a transfer speed from a speed corresponding to the third clock to a speed corresponding to the second clock, by transferring the data received in the synchronizing unit to the memory device in synchronism with the second clock.