Patent ID: 6556492
Filing Date: 2003-04-29
Classification: G11C

Abstract:
A system for testing fast synchronous semiconductor circuits, comprising:a testing device connected via a signal path to a semiconductor circuit to be tested, the semiconductor circuit to be tested being connected to receive test signals selected from the group consisting of test data signals, control signals, address signals and timing reference and clock signals generated in dependence on signal conditions defined by said testing device, and the semiconductor circuit to be tested generating response signals in response to the test signals; a semiconductor circuit chip connected in said signal path between said testing device and the semiconductor circuit to be tested and spatially associated with the semiconductor circuit to be tested, said semiconductor circuit chip containing a timing reference circuit for generating timing reference signals with a programmable phase angle and forming a timing reference for the test signals and the response signals, and circuits for generating the test signals and for evaluating the response signals received from the semiconductor circuit being tested, said timing reference circuit including first and second DLL circuits with programmable delay; a tap in close vicinity to the semiconductor circuit to be tested, said tap carrying the clock signal generated by said semiconductor circuit chip and sent to the semiconductor circuit to be tested; and a feedback circuit for feeding the clock signal back from said tap to said second DLL circuit.