Patent ID: 7630389
Filing Date: 2009-12-08
Classification: H04L

Abstract:
1. A computer-implemented method for configuring a multi-threaded first-in-first-out (FIFO) memory, wherein the multi-threaded FIFO memory includes a sender interface, a storage resource, and a receiver interface, the method comprising: generating a first portion of the synthesizable code, wherein the first portion represents the sender interface with a first thread identifier input port and a write data input port that is configured to receive data for multiple execution threads; generating a second portion of the synthesizable code, wherein the second portion represents the storage resource configured to store the data for the multiple execution threads in a shared memory; generating a third portion of the synthesizable code, wherein the third portion represents the receiver interface with a second thread identifier input port and a read data output port that is configured to output the data for the multiple execution threads that corresponds to a thread identifier received by the second thread identifier input port; and configuring the multi-threaded FIFO memory based on at least one of the first portion, the second portion, or the third portion.