Patent ID: 7561464
Filing Date: 2009-07-14
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: first and second cell arrays each having a plurality of electrically rewritable memory cells arranged therein; and a sense amplifier circuit configured to read out data of the first and second cell arrays, wherein plural information cells are set in the first cell array, and at least one reference cell are set in the second cell array, one of four data levels L0, L1, L2 and L3 (where, L0<L1<L2<L3<) being written into an information cell, reference level Lr (where, L0<Lr<L1) being written into the reference cell to be used for detecting the data level of the information cell, wherein the sense amplifier circuit is configured to detect a cell current difference between the information cell and the reference cell selected from the first and second cell arrays, respectively, wherein the four data levels L0, L1, L2 and L3 of the information cell are threshold voltage levels with a relationship as follows: L0 is an erase state with a certain threshold voltage; and L1, L2 and L3 are write states with threshold voltages with a relationship of L1<L3-L2, and L2-L1<L3-L2, and wherein the reference level Lr is a write state with a threshold voltage lower than L1.