Patent ID: 6538291
Filing Date: 2003-03-25
Classification: H01L

Abstract:
An input protection circuit comprising:a MOS transistor for discharging a high voltage applied to an electrode pad by a forward bias to a PN junction; a resistance increasing element or device arranged on a part of a current path in said MOS transistor under said forward bias, whereby local current concentration on said PN junction is prevented; and wherein said MOS transistor includes: a lightly-doped one conductivity type semiconductor layer; a heavily-doped opposite conductivity type drain region having a rectangular pattern, formed in said semiconductor layer; source regions formed in said semiconductor layer on both sides of and a predetermined distance from said drain region; and a heavily-doped single conductivity type backgate contact region formed in said semiconductor layer, patterned like a frame parallel to said rectangular pattern so as to surround said drain region and said source regions; wherein said resistance increasing element or device includes a lightly-doped opposite conductivity type diffusion layer formed between said source regions and said backgate contact region in said semiconductor layer, in the vicinity of a first longitudinal end of said drain region at a predetermined distance from said drain region, wherein said diffusion layer forms a first U-shape which extends around first longitudinal ends of said source regions and said first longitudinal end of said drain region.