Patent ID: 7531866
Filing Date: 2009-05-12
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a substrate having a surface; a plurality of memory cells formed in a matrix on the substrate, said memory cell including: a plurality of pairs of lines that include a bit line and a control line formed in parallel with the channel on said substrate, the pairs including a first pair, wherein: said memory cells include a plurality of memory cells that collectively form a row extending in a direction parallel to the bit line, the memory cells in the row being disposed between the bit line and the control line of the first pair, each memory cell in the row having both the first and second impurity regions, each memory cell in the row being alternately connected with the bit line or the control line of the first pair, the first gate electrode and the second gate electrode in each memory cell in the row being formed in strips in a direction perpendicular to the channel in each memory cell in the row; and two adjacent memory cells in the row are disposed, such that the second impurity region of one memory cell is disposed next to and connected with the first impurity region of the adjacent memory cell.