Patent ID: 6087210
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method of manufacturing a CMOS transistor, comprising the steps of:forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors;forming a P-well region and a N-well region in said first and second regions, respectively;forming a gate oxide film and a gate electrode on selected regions of said first and second regions;implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within said first and second regions;forming spacers at the side walls of said gate electrode and the gate oxide film;forming a high concentration implantation region in said first and second regions; andimplanting N-type impurity ions into said second region to form a punch stop doping layer below said low concentration impurity implantation region of said second region.