Patent ID: 6881671
Filing Date: 2005-04-19
Classification: H01L,Y02E

Abstract:
1. A process for the metallising of one or more contacts of a buried grid solar cell having a body of doped semiconductor material, which body has two major opposing surfaces forming a light incident surface and a backside both provided with one or more electrical contacts, and which body further has one or more edges between the major opposing surfaces, wherein the electrical contact or contacts at the light incident surface is/are formed by conducting material being arranged in a pattern of one or more grooves into the semiconductor material at the light incident surface, comprising the steps of a) providing the semiconductor body with a p/n-junction and an electrically insulating layer on the light incident surface and optionally on other surfaces, which layer is light transparent and not catalytic for electroless plating, b) providing an exposed surface on one or more of the edges, c) providing one or more grooves with a depth of 20-50 μm from the light incident surface through the insulating layer and into the semiconductor body and a width of 10-30 μm at the level of the light incident surface, d) doping the exposed material in the grooves obtained in step c) to reestablish the p-n-junction in the material below the surface in the grooves, e) applying a seed layer on the exposed semiconductor material in the grooves by electroless plating followed by sintering, f) applying an electrically conducting base layer by electroless plating on top of the seed layer obtained in step e), and g) filling the grooves with an electrically conducting contact forming material by electrolytic plating using an electrolytic bath further comprising a levelling additive to ensure a laminate growth during a build up of the electroplated layer, and a suppressing additive to inhibit a build up of the electroplated layer in areas having a higher field intensity, and using substantially constant cell voltage.