Patent ID: 8558232
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A top-gate thin film transistor formed on an insulated substrate, comprising: a source electrode and a drain electrode; a first and a second impurity-doped semiconductor layers containing one of first and second electrically conductive impurities, and electrically connected to the source electrode and drain electrode respectively; a first semiconductor layer including microcrystalline semiconductor regions formed on the first and the second impurity-doped semiconductor layers respectively, and an amorphous semiconductor region formed on an area not formed with the microcrystalline semiconductor regions; a second semiconductor layer of a microcrystalline semiconductor formed on the first semiconductor layer; and a gate insulation film formed on the second semiconductor layer; the first and the second impurity-doped semiconductor layers being provided by a microcrystalline semiconductor and electrically connected to the second semiconductor layer, with the microcrystalline semiconductor regions of the first semiconductor layer sandwiched therebetween.