Patent ID: 7259065
Filing Date: 2007-08-21
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming an isolation region in a substrate having a defined upper surface, such that the isolation region has an upper surface co-planar with the defined upper surface; defining a plurality of active regions in the substrate, each active region having an upper surface co-planar with the defined upper surface and extending lengthwise along a first diagonal direction, the plurality of active regions being arranged in parallel and separated one from another within the isolation region; providing an etching mask pattern disposed on the defined upper surface of the substrate to define a plurality of open regions that expose at least a portion of each one of the plurality of active regions and at least a portion of the isolation region, wherein each one of the plurality of open regions extends lengthwise along a second vertical direction at an angle with respect to the first diagonal direction, and at least one open region extends across at least one active region and over a portion of the isolation region; and etching the portion of each one of the plurality of active regions exposed through the plurality of open regions to form respective trenches having an upper surface below the defined upper surface of the substrate.