Patent ID: 7807528
Filing Date: 2010-10-05
Classification: H01L

Abstract:
1. A method comprising: (a) depositing a dielectric over a gate electrode, wherein the gate electrode extends in a first dimension; (b) depositing a silicon material over the dielectric; (c) depositing a spacer material over the silicon material; (d) etching the spacer material anisotropically to form a sidewall spacer; (e) etching the silicon material anisotropically to form an outrigger beneath the sidewall spacer, wherein the outrigger extends parallel to the gate electrode in the first dimension, wherein the outrigger is separated from the gate electrode by at most approximately 0.4 microns, and wherein the gate electrode is part of an electrostatic discharge (ESD) transistor structure; and (f) covering the outrigger with a passivation layer.