Patent ID: 6509774
Filing Date: 2003-01-21
Classification: H03H,H03K

Abstract:
A delay circuit comprising:a current source having metal oxide semiconductor (MOS) transistors of which gates are connected to each other, the current source generating a constant current by controlling sizes of the MOS transistors; and a unit delay circuit having a complementary MOS (CMOS) inverter with p-channel MOS (PMOS) transistors and n-channel MOS (NMOS) transistors, wherein non-adjacent PMOS: and NMOS transistors are controlled to charge or discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged, wherein the current source comprises: a supply voltage being connected with respective sources of first through fourth PMOS transistors, gates of the first through fourth PMOS transistors being commonly connected with an output of a comparator, a drain of the first PMOS transistor being connected with a first voltage and a diode, and a drain of the second PMOS transistor being connected with a second voltage and a resistor; the resistor being connected to diodes connected to each other in parallel having a third voltage; and the fourth PMOS transistor having a drain connected to a drain of the third PMOS transistor, wherein the constant current output from the drain of the third PMOS transistor is supplied to the unit delay circuit.