Patent ID: 6204711
Filing Date: 2001-03-20
Classification: H03K

Abstract:
A cascaded delay circuit for generating asynchronous clock signals for operating control logic (16) to process an event signal, the circuit comprising:a flip-flop (15) for receiving said event signal and generating a clock enable signal;a logic gate (14) connected to said flip-flop (15) for receiving said clock enable signal and generating a clock signal, said clock signal being communicated to said control logic (16); anda plurality of cascaded delays (10) connected in series, the first of said plurality of cascaded delays (10) connected to receive as an input said clock signal, the last of said plurality of cascaded delays (10) further connected to said logic gate (14), wherein the output of each of said plurality of cascaded delays (10) is fed back to said control logic (16) to generate timing signals.