Patent ID: 9024372
Filing Date: 2015-05-05
Classification: H01L

Abstract:
1. A nonvolatile memory device comprising: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer perpendicular to the surface of the substrate; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the stack structure includes a first portion of the plurality of the floating gate electrodes and each floating gate electrode in the first portion is arranged between two control gate electrodes, and wherein a lowermost floating gate electrode of the plurality of floating gate electrodes is positioned at a lowermost part of the stack structure and an uppermost floating gate electrode of the plurality of floating gate electrodes is positioned at an uppermost part of the stack structure, and each of the plurality of floating gate electrodes has constant thickness, in a direction perpendicular to the surface of the substrate, throughout its left edge to its right edge and the lowermost and the uppermost floating gate electrodes have a smaller horizontal width in a direction parallel to the surface of the substrate, than a horizontal width of each floating gate electrode of the first portion of the plurality of floating gate electrodes.