Patent ID: 9030888
Filing Date: 2015-05-12
Classification: G11C

Abstract:
1. A semiconductor device comprising: a data terminal; a first power supply line supplying a first potential; a second power supply line supplying a second potential different from the first potential; a first buffer circuit coupled between a first power supply line and the data terminal; a second buffer circuit coupled between a second power supply line and the data terminal; a first control circuit activating the first buffer circuit and deactivating the second buffer circuit during a period before a start timing when an output operation of a data signal from the data terminal is started, and activating one of the first and second buffer circuits and deactivating the other of the first and second buffer circuits based on a logic level of the data signal to be outputted from the data terminal during a period after the start timing; a second control circuit controlling an impedance of the first buffer circuit to a first value in a first control state, and controlling an impedance of the activated one of the first and second buffer circuits to a second value in a second control state; and a third control circuit bringing the second control circuit into the first control state before preparation timing prior to the start timing, and bringing the second control circuit into the second control state after the start timing, the third control circuit changing the second control circuit from the first control state to the second control state during a period from the preparation timing to the start timing.