Patent ID: 8185371
Filing Date: 2012-05-22
Classification: G06F

Abstract:
1. A method of modeling half cycle clock variation: performing, by a static timing analyzer, a first static timing analysis (STA-1) on a design model that includes a launch storage element (LSE) and a capture storage element (CSE) with combinational logic therebetween, the design model including full cycle data paths and half cycle data paths, a main clock signal being applied to the launch storage element (LSE) and the capture storage element (CSE), wherein the first static timing analysis (STA-1) is performed using a shortened clock period to model full clock cycle variability (FCV) to provide slack information including worst case slack information (WS) and half clock cycle variability information (HCV); determining, by the static timing analyzer, a clock period extension (CPE) value from the worst case slack (WS) information and the half clock cycle variability (HCV) information; performing, by the static timing analyzer, a second static timing analysis (STA-2) using the clock period extension (CPE) value applied to the main clock signal to generate an extended clock signal and corresponding second static timing analysis (STA-2) slack information; and identifying, by the static timing analyzer, failing half cycle data paths from the second static timing analysis (STA-2) slack information.