Patent ID: 7538999
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first terminal which receives a first potential; a second terminal which receives a second potential different from the first potential; an I/O terminal which inputs/outputs data; a first buffer MOSFET of a first conductivity type, which has a current path connected between the first terminal and the I/O terminal and drives the I/O terminal by the first potential; a second buffer MOSFET of a second conductivity type, which has a current path connected between the I/O terminal and the second terminal and drives the I/O terminal by the second potential; a first ESD protection circuit configured to protect an internal circuit from an ESD surge; an external input terminal which capacitively couples to one of the second terminal and the first terminal and receives one of the first potential and the second potential in a normal operation mode; and a control circuit including a first prebuffer which is configured to receive a signal that controls a gate potential of each of the first buffer MOSFET and the second buffer MOSFET, control a gate of each of the first buffer MOSFET and the second buffer MOSFET to a potential corresponding to the signal in the normal operation mode on the basis of one of the first potential and the second potential applied to the external input terminal, and fix the external input terminal to one of the second potential and the first potential by capacitive coupling upon ESD surge application, thereby fixing the gate of the second buffer MOSFET to one of the second potential and the first potential and turning off the second buffer MOSFET, in which the first prebuffer includes a 3-input NAND circuit which operates at a voltage between the first potential applied to the first terminal and the second potential applied to the second terminal and has a first input terminal connected to the external input terminal, and second and third input terminals which receive a gate potential control signal and an enable signal, respectively, and an inverter circuit which operates at a voltage between the first potential applied to the first terminal and the second potential applied to the second terminal and causes an input terminal to receive an output signal from the 3-input NAND circuit and an output terminal to supply an inverted signal to the gate of the second buffer MOSFET, and which further comprises a capacitive element which is connected between the second terminal and the external input terminal to make the second terminal capacitively couple to the external input terminal.