Patent ID: 9153672
Filing Date: 2015-10-06
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a collector region formed in a semiconductor substrate, the collector region having a first conductivity type and coupled to a source line of the memory device; first and second base regions disposed in the semiconductor substrate and spaced apart over the collector region and having a second conductivity type, the first base region corresponding to a first pair of memory cells and the second base region corresponding to a second pair of memory cells; a gate structure which extends directly over an upper surface of the semiconductor substrate continuously between the first and second base regions and which acts as a shared word line for the first and second pairs of memory cells of the memory device; first and second emitter regions disposed in the substrate over the first base region and having the first conductivity type, the first and second emitter regions arranged on opposite sides of the gate structure and corresponding to first and second memory cells that make up the first pair of memory cells; and first and second contacts extending upwardly from upper regions of the first and second emitter regions, respectively, and coupling the first and second emitter regions to lower regions of first and second data storage elements, respectively, of the first and second memory cells, respectively.