Patent ID: 6172923
Filing Date: 2001-01-09
Classification: G11C

Abstract:
A dummy circuit for providing a load equivalent and in-phase to that of a bitline for precharging and sensing of logic level within a read only memory (ROM) circuit, said dummy circuit comprising:a dummy circuit enable lead;a column select circuit having a grounding transistor and a precharge transistor, said grounding transistor coupled to said dummy circuit enable lead, said grounding transistor coupled to ground, said precharge transistor coupled to said dummy circuit enable lead, and said precharge transistor coupled to a dummy-circuit side of a precharge circuit and to a dummy-circuit side of a cross-coupled sense amplifier;a dummy bitline, said dummy bitline coupled to said grounding transistor and to said precharge transistor in said column select circuit, said dummy bitline having at least one memory cell transistor, said dummy bitline having a loading and capacitance approximately equal to that of a bitline to be compared for logic levels with said dummy bitline, said memory cell transistor having a faster voltage level response than that of a memory cell transistor in said bitline; anda dummy column-select-load circuit coupled to said precharge transistor of said column-select circuit, said dummy column-select-load circuit having a loading and capacitance almost equal to that of the sum of column-select transistors on bitlines to which said dummy bitline is coupled and would be compared against.