Patent ID: 7215154
Filing Date: 2007-05-08
Classification: H03K

Abstract:
1. A dynamic logic circuit having a plurality of data inputs, one or more of the data inputs are maskable data, comprising: a clock block having a system clock input that receives a system clock, a mask input that receives a mask, a first clock output that drives a first clock, and a second clock output that drives a second clock; a precharge device coupled to the first clock output, the precharge device precharging a dynamic node responsive to the first clock being in a precharge state; one or more stacks of switches, each particular stack able to discharge the dynamic node if all switches in the particular stack are conducting, each stack in the stack of switches further comprising: a first switch in each stack coupled to the second clock output and being turned on by the second clock responsive to the second clock being in an evaluate state; and a second switch in each stack coupled to a particular maskable data input, the second switch being turned on by an active value on the particular maskable data input; wherein the first clock is a buffered copy of the system clock, and the second clock is a logical derivative of the system clock and the mask.