Patent ID: 7242081
Filing Date: 2007-07-10
Classification: H01L

Abstract:
1. A stacked package structure, comprising: a first chip package structure comprising: a first substrate having a first surface and a second surface in opposition to each other; at least one first chip deposed on and electrically connected to the first surface of the first substrate; a plurality of first electrical connection devices directly attached to the first surface and periphery of the first substrate, wherein each first electrical connection device is higher than the at least one first chip in altitude, and the first electrical connection devices are a plurality of passive devices; a first encapsulant covering the first surface of the first substrate, the at least one first chip and the first electrical connection devices, wherein a top end of each first electrical connection device is exposed at a surface of the first encapsulant; and a plurality of first connections deposed on the second surface of the first substrate, wherein the at least one first chip and the first electrical connection devices are electrically connected to the first connections respectively; a second chip package structure stacked on the first chip package structure, and the second chip package structure comprising: a second substrate having a first surface and a second surface in opposition to each other; at least one second chip deposed on the first surface of the second substrate; and a second encapsulant covering the first surface of the second substrate and the at least one second chip; and a plurality of second connections respectively deposed on the top end of each first electrical connection device, and jointed with the second surface of the second substrate, wherein the at least one second chip is electrically connected to the second connections respectively.