Patent ID: 7700983
Filing Date: 2010-04-20
Classification: H01L

Abstract:
1. An integrated circuit including a transistor comprising: a channel region disposed in a semiconductor substrate between a first and a second source/drain region, wherein the first and the second source/drain region are formed adjacent to an upper surface of the semiconductor substrate and wherein the channel region has horizontal and vertical components with respect to the upper surface of the semiconductor substrate; a gate groove formed in the upper surface of the semiconductor substrate adjacent to the channel region, the gate groove comprising an upper portion and a lower portion, the upper portion being adjacent to the lower portion; and sidewall spacers made of an insulating material, wherein the lower portion of the gate groove is filled with polysilicon and a metal or a metal compound is disposed in the upper portion of the gate groove, thereby forming a gate electrode; wherein an entire interface between polysilicon of the lower portion of the gate groove and the metal or metal compound is disposed below the upper surface of the semiconductor substrate; and wherein the sidewall spacers are disposed on the sidewalls of the upper portion of the gate groove, a bottom side of the sidewall spacers being disposed above an upper side of the lower portion of the gate groove.