Patent ID: 8649224
Filing Date: 2014-02-11
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising; a semiconductor substrate; a memory string stacked above the semiconductor substrate and comprising a plurality of memory cells connected in series; a drain-side select transistor connected to a first end of the memory string; a source-side select transistor connected to a second end of the memory string; a plurality of word lines connected to the memory cell; a plurality of bit lines connected to the drain-side select transistor; a source line connected to the source-side select transistor; and a control circuit configured to control a voltage supplied to the drain-side select transistor, the source-side select transistor, the word lines, and the bit lines, the control circuit being capable of performing a data variation determination operation of determining whether a plurality of memory cells connected to a selected word line each have a threshold voltage equal to or less than a certain value, and whether the number of memory cells where data variation has occurred is not less than a certain number.