Patent ID: 6046491
Filing Date: 2000-04-04
Classification: H01L,H03M

Abstract:
A semiconductor device comprising:(a) a semiconductor substructure;(b) a first insulator layer formed on said substructure to selectively expose an area of said substructure;(c) at least one resistor element, each said resistor element comprising first, second, and third resistor regions;said first resistor region being formed in the exposed area of said substructure;said first resistor region having a first doping concentration, said second resistor region having a second doping concentration higher than said first doping concentration, said third resistor region having a third doping concentration equal to said second doping concentration;said second and third resistor regions being spaced apart from and electrically connected to respective ends of said first resistor region;(d) a second insulator layer formed over said first, second and third resistor regions;said second insulator layer having first and second contact holes for said resistor element;(e) a first wiring conductor formed on said second insulator layer;said first wiring conductor being contacted with and electrically connected to said second resistor region of said resistor element through said first contact hole of said second insulator layer;said first wiring conductor being formed not to overlap with said first resistor region of said resistor element; and(f) a second wiring conductor formed on said second insulator layer;said second wiring conductor being contacted with and electrically connected to said third resistor region of said resistor element through said second contact hole of said second insulator layer;said second wiring conductor being formed not to overlap with said first resistor region of said resistor element;wherein said second and third resistor regions are formed under said second insulator layer;and wherein said second resistor region is not in direct contacte with said first resistor region and is electrically connected to said first resistor region through a first interconnection conductor;and wherein said third resistor region is not in direct contact with said first resistor region and is electrically connected to said first resistor region through a second interconnection conductor.