Patent ID: 6265263
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method for forming a capacitor of a dynamic random access memory cell, said method comprising:forming a first dielectric layer over a semiconductor substrate;forming a second dielectric layer over said first dielectric layer;forming a third dielectric layer over said second dielectric layer;patterning said third dielectric layer, said second dielectric layer, and said first dielectric layer to have a contact hole within said third dielectric layer, said second dielectric layer, and said first dielectric layer;forming a doped polysilicon layer within said contact hole and over said third dielectric layer;forming a fourth dielectric layer over said doped polysilicon layer;patterning said fourth dielectric layer and said doped polysilicon layer to define a storage node;forming a hemispherical grained silicon layer on said fourth dielectric layer, on sidewalls of said storage node, and on said third dielectric layer;etching said hemispherical grained silicon layer to define a plurality of cavities between grains of said hemispherical grained silicon layer and expose said fourth dielectric layer through said plurality of cavities;etching said fourth dielectric layer and said doped polysilicon layer underlying said cavities to form a porous storage node;removing said fourth dielectric layer and said third dielectric layer;forming a fifth dielectric layer on said porous storage node and said substrate; andforming a conductive layer on said fifth dielectric layer.