Patent ID: 6350642
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising:forming a first interlayer dielectric layer which surrounds and insulates a plurality of conductive plugs formed on a semiconductor substrate and exposes the top surfaces of the plurality of conductive plugs; forming a bit line electrically connected to a first conductive plug of the plurality of conductive plugs, wherein the bit line includes a spacer on a sidewall thereof, a capping insulating layer at one portion of the top surface of the bit line, and a first etch stop pattern having a thickness smaller than the capping insulating layer at another portion of the top surface of the bit line; forming a second etch stop pattern which covers the surface of a second conductive plug of the plurality of conductive plugs; forming a second interlayer dielectric layer that overlies the capping insulating layer and the first and second etch stop patterns; etching the second interlayer dielectric layer using the first and second etch stop patterns as an etch stop point and forming a plurality of contact holes aligned to the bit line and the second conductive plug, respectively; etching portions of the first and second etch stop pattens exposed by the plurality of contact holes and exposing the top surfaces of the bit line and the second conductive plug; and forming a plurality of conductive contact studs electrically connected to the bit line and the second conductive plug, respectively, by filling the plurality of contact holes.