Patent ID: 7631211
Filing Date: 2009-12-08
Classification: G06F,G11C

Abstract:
1. An integrated circuit, comprising: a first timing circuit; a first selection circuit having an output coupled with an input of the first timing circuit, wherein the first selection circuit receives a first input data signal and a first output data signal, wherein during an input function the first selection circuit sends the first input data signal to the first timing circuit and during an output function the first selection circuit sends the first output data signal to the first timing circuit; a second selection circuit having an output coupled with the first timing circuit, wherein the second selection circuit is coupled with a first signal line and a clock enable line capable of carrying a first clock enable signal, wherein the first signal line is capable of carrying a data signal or a second clock enable signal; and a second timing circuit, wherein the first and second timing circuits are capable of being used together to perform at least one multiple data-rate input or output function.