Patent ID: 6924083
Filing Date: 2005-08-02
Classification: G03F

Abstract:
1. An exposing method that reduces diffraction effects in the process of semiconductor production, comprising: providing a mask having two sections with pattern matching being equally divided on said mask, only the light of specific energy produced by an exposer being able to go through according to a layout pattern on a mask section in an exposing process; performing a first exposure on a chip using said mask, wherein said first exposure being carried out to a first shot by said exposer to expose a pattern of a second section of said mask on a half of said first shot; moving said exposer for a distance of half of a shot in continual exposing procedure; and performing a second exposure on said chip using said mask, wherein said second exposure being carried out by said exposer to expose a pattern of a first section of said mask on said half of said first shot to finish a complete pattern.