Patent ID: 6140231
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method of copper metallization in the fabrication of an integrated circuit device comprising:providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization;covering said semiconductor device structures with an insulating layer;opening a via through said insulating layer to one of said underlying semiconductor device structures;conformally depositing a stacked mode tantalum nitride barrier layer within said via wherein said stacked mode tantalum nitride barrier layer comprises a first layer of TaN and a second layer of Ta.sub.2 N and wherein grain boundaries of said TaN layer and said Ta.sub.2 N layer are misaligned; anddepositing a layer of copper overlying said stacked mode tantalum nitride barrier layer to complete said copper metallization in the fabrication of said integrated circuit device.