Patent ID: 6282210
Filing Date: 2001-08-28
Classification: G06F,G11C,H03L

Abstract:
A clock driver for generating, from an input clock signal, an output clock signal having a phase-offset that is selectable for each output clock period, said clock driver circuit comprises:a zero-delay-loop circuit coupled to receive said input clock signal, for delaying said input clock signal by a controllable quantum of time to generate a reference clock signal having a controllable phase-offset in relationship to said input clock signal;a first delay circuit coupled to receive said reference clock signal, said first delay circuit providing an input feedback signal derived by delaying said reference clock signal by a first quantum of time;wherein said zero-delay-loop circuit receives said feedback signal, for determining the magnitude of said controllable quantum of time that said reference clock signal is delayed from said input clock signal, such that said input feedback signal is in-phase with said input clock signal;one or more offset delay circuits, each offset delay circuit receiving said reference clock signal and providing an offset signal derived by delaying said reference clock signal by a desired quantum of time, and wherein said one or more offset signals are offset in time from one another and said reference signal; anda multiplexer coupled to receive said reference signal and said one or more offset signals, for routing one of said received signals to an output clock signal.