Patent ID: 6426662
Filing Date: 2002-07-30
Classification: H03K,H03L

Abstract:
A multi-phase clock generator comprising:a plurality of delay stages, each delay stage generating a true delay output and a complement delay output in response to a true input and a complement input; a pair of differential toggle flip-flops attached to each delay stage including a first flip-flop receiving the true delay output at a positive-clock input and receiving the complement delay output at a negative-clock input, the first flip-flop changing a state of a true output and a complement output when a rising edge of the true delay output and a falling edge of the complement delay output occurs; a second flip-flop receiving the complement delay output at a positive-clock input and receiving the true delay output at a negative-clock input, the second flip-flop changing a state of a true output and a complement output when a rising edge of the complement delay output and a falling edge of the true delay output occurs; and a plurality of buffers, each buffer receiving a true output and a complement output from either a first flip-flop or from a second flip-flop in the pair of differential toggle flip-flops for a delay stage, each buffer outputting an output clock generated from the true and complement outputs; wherein a plurality of the output clocks are generated by the buffers, the output clocks being delayed by different phases but having a same output period, whereby multiple phases of output clocks are generated using differential flip-flops.