Patent ID: 6023441
Filing Date: 2000-02-08
Classification: G11C

Abstract:
A memory comprising:(a) a register array of an N word wide set of data word resisters arranged for parallel accessing of a read or write operation, said array having a plurality of registers arranged in a plurality of rows and columns, wherein each row includes N sets of data word registers, said accessing being performed simultaneously on said N sets of data word registers originating from a starting address specified by an address pointer register and delivering a remaining N-1 sets of data words from contiguous addresses, and further wherein said accessing delivers a contiguous N sets of data words even when said starting address is unaligned with the physical starting address of the selected row, causing said data words to be accessed from a next physical row to complete a simultaneous delivery of said N set of data words;(b) N set selecting enable lines for each row of registers, each of said set selecting enable lines coupled to one set of registers in said N sets of data word registers in a row; and(c) a set selector coupled to the N set selecting lines for selectively enabling a particular set of registers by supplying an enable signal on the enable line that couples said set selector to said particular set of registers, said set selector positioned in middle of said rows of registers such that, in each row, N/2 sets of registers are to a first side of said set selector and N/2 sets of registers are to a second side of said set selector and said set selector emulating N set selecting lines per row by employing N/2 lines per side of said set selector.