Patent ID: 6333881
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of word lines;a plurality of bit lines;memory cells disposed at intersections of the word lines and the bit lines;a write circuit for rewriting data in a desired memory cell by setting the bit line at a low potential;a first precharge circuit for putting the bit line back at a high potential after completion of at least a read operation; anda second precharge circuit which begins a precharge operation upon detection of completion of a write operation and which stops the precharge operation upon detection that the bit line is precharged to the high potential, wherein the second precharge circuit comprises:a first logic circuit which enters a selection mode when the bit line signal is not precharged to the high potential;a second logic gate which enters a selection mode when a write operation is not performed and the first logic gate is in the selection mode; anda transistor for precharging the bit line at the high potential when the second logic gate is in the selection mode.