Patent ID: 8698786
Filing Date: 2014-04-15
Classification: G09G

Abstract:
1. A driving circuit for a display apparatus in which the number of outputs from a gate driver that drives gate lines of a display panel is greater than the number of display lines of the display panel in the vertical direction, wherein a gate start pulse signal for a next frame is output at (m−n+k+1)-th line from a beginning of a display period for a previous frame where m denotes the number of the display lines, n denotes the number of extra outputs from the gate driver at a side from which the scan is performed, k denotes a positive integer of at least 1, and a scan of the gate driver is performed from a side at which there is an extra output from the gate driver; k pulses of a gate driver clock signal are output during a vertical blank period; input of a gate driver clock signal is restarted from a beginning of a display period for the next frame; and the gate start pulse signal is generated in response to a display data enable signal, the driving circuit comprising: an internal reference signal generation circuit that receives the display data enable signal and generates an internal reference signal having a same period as the display data enable signal; a V line counter that counts the number of pulses included in the internal reference signal; a V blank decision circuit that recognizes a vertical blank period by determining whether there is the display data enable signal and generates a V blank decision signal that remains active during the vertical blank period; a comparison unit that outputs a control signal when a count value of said V line counter reaches (m−n+k+1); a VSP generation circuit that generates a gate start pulse signal when receiving the control signal; a VCK termination decision circuit that causes a VCK termination signal to become active when the count value of said V line counter reaches (m+k+1) and causes the VCK termination signal to become inactive when the V blank decision signal becomes inactive; and a VCK generation circuit that generates a gate driver clock signal in response to the internal reference signal only when the VCK termination signal is inactive.