Patent ID: 6205514
Filing Date: 2001-03-20
Classification: G11C

Abstract:
A system comprising:a processor having a plurality of byte enable outputs;cache control logic connected to the processor; anda synchronous SRAM connected to the cache control logic and to the processor, the SRAM including:an SRAM core having a memory array of a plurality of bytes, wherein individual bytes are selectably written to, but multiple bytes are simultaneously selected when it is desired to read from the bytes, for improved speed, the SRAM core further having a plurality of byte write drivers, having sense amplifiers, and having I/O buffers;a plurality of byte write registers respectively connected to the write drivers, the byte write registers selectively activating corresponding byte write drivers to input data into the memory array during a write operation;a plurality of data inputs organized into bytes and connected to the processor;a byte write enable input connected to the cache control logic;a plurality of byte write inputs respectively directly connected to the byte enable outputs of the processor;byte write enable circuitry connecting the byte write inputs and the byte write enable input to the byte write registers and selectively causing individual bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the byte write enable input and also depending on the asserted logic level on the individual byte write inputs;ony a global write input selectively causing all bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the global write input, the global write input being connected to the cache control logic; andglobal write circuitry connecting the global write input to the byte write registers.