Patent ID: 6737682
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A method to form a LVT-SCR device in the manufacture of an integrated circuit device comprising:providing a SOI substrate comprising a silicon layer overlying a buried oxide layer wherein said silicon layer further comprises a first well of a first type and a second well of a second type; forming first and second gates overlying said first well; forming first and second doped regions of said first type wherein said first doped region is in said first well and wherein said second doped region is in said second well and form an anode; and forming third, fourth, and fifth doped regions of said second type wherein said third and fourth doped regions are in said first well, wherein said fifth doped region is partly in said first well and partly in said second well, wherein said first and third doped regions form a cathode, wherein said first gate is between said third and fourth doped regions, wherein said second gate is between said fourth and fifth doped regions, and wherein said doped regions are not separated by isolation oxide.