Patent ID: 6745379
Filing Date: 2004-06-01
Classification: G06F,G11B

Abstract:
A hierarchical method of routing nets within a particular region of a circuit layout, each net having a set of pins, the method comprising:a) partitioning the particular region into a first set of sub-regions; b) for each net, identifying a first route that connects a group of first-set sub-regions containing the first net's pins; wherein some of the routes have at least one route-edge that is at least partially diagonal; c) partitioning the sub-regions into a second set of smaller sub-regions; d) for a first net, identifying a propagation of the first-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions; e) adjusting the congestion between the second set sub-regions based on the identified propagation; f) for a second net, identifying a propagation of the second-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions.