Patent ID: 6466621
Filing Date: 2002-10-15
Classification: H04N

Abstract:
A video coder for encoding digital signals corresponding to interlaced-field picture sequences in which each picture is divided into subpictures called macroblocks, comprising a first coding sub-system for carrying out a first coding step at the macroblock level and a second coding sub-system for carrying out a second coding step at the end of which an output coded bitstream is generated, characterized in that:(A) said first sub-system comprises a first encoding channel, which channel comprises a series arrangement of a first section for compressing interlaced data and an encoding section, and, in parallel therewith, a second encoding channel, which channel comprises a series arrangement of a second section for compressing non-interlaced data and an encoding section, a first prediction channel on the basis of output signals of said first section and, in parallel therewith, a second prediction channel on the basis of output signals of said second section, said second section including at its input side a circuit for de-interlacing the fields and said second prediction channel including a circuit for re-interlacing the fields, a decision sub-assembly comprising means for comparing the output signals of the first and second encoding channels and means for counting the number of macroblocks coded in accordance with the field mode, a computation circuit for counting the number of macroblocks that have been predicted according to the field motion compensated mode, and a processor for receiving said macroblock numbers and storing also the average quantization steps of the current and last picture; (B) said second sub-system comprises a third encoding channel, which channel comprises a series arrangement of a third section for compressing interlaced data and an encoding section, and, in parallel therewith, a fourth encoding channel, which channel comprises a series arrangement of a fourth section for compressing non-interlaced data and an encoding section, a third prediction channel on the basis of output signals of said first section and, in parallel therewith, a fourth prediction channel on the basis of output signals of said fourth section, said fourth section including at its input side a circuit for de-interlacing the fields and said fourth prediction channel including a circuit for re-interlacing the fields, a decision sub-assembly comprising means for comparing the output signals of the first and second encoding channels and means for selecting the prediction and encoding channels in accordance with the result of said comparison, and a selection stage comprising means for connecting the pictures to be coded to the input of said second sub-system either directly or via a circuit for suppressing the field interlacing, according to the value of an output flag delivered by the processor on the basis of statistical results constituted by its input signals.