Patent ID: 7838421
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A method of forming metal lines of a semiconductor device, the method comprising: providing a semiconductor substrate comprising a cell area and a peripheral area, each of said cell area and said peripheral area comprising a plurality of gates and a plurality of junctions formed between the gates; forming a first insulating layer over the semiconductor substrate including the gates; forming a second insulating layer over the first insulating layer; forming an etch protection layer over the second insulating layer; forming first contact holes including sidewalls by etching the etch protection layer and the second insulating layer to expose the junctions of the cell area; forming contact plugs contacting the junctions of the cell area to fill a portion of the first contact holes with conductive material; forming second contact holes by etching the etch protection layer and the second insulating layer to expose the junctions of the peripheral area; forming a spacer on sidewalls of a remaining portion of the first contact holes; forming first metal lines contacting the contact plugs; forming second metal lines contacting the junctions of the peripheral area; removing the etch protection layer; and forming a third insulating layer on the second insulating layer including the first and second metal lines, wherein cleaning processes are performed between forming the contact plugs and forming the first and second metal lines and the etch protection layer prevents etching of the second insulating layer from being etched during the cleaning processes.