Patent ID: 6838900
Filing Date: 2005-01-04
Classification: H04L,H05K

Abstract:
1. A bus structure for transmitting data between a first circuit with a first I/O pin and a second circuit with a second I/O pin, comprising: a transmission line connected between the first I/O pin of the first circuit and the second I/O pin of the second circuit; a middle resistor having a first end coupled to a middle point of the transmission line and having a second end coupled to a voltage source; the first circuit having a first pull-up resistor with a first end coupled to the first I/O pin of the first circuit and a second end coupled to the voltage source, the resistance of the first pull-up resistor being higher than a characteristic impedance of the transmission line; and the second circuit having a second pull-up resistor with a first end coupled to the second I/O pin of the second circuit and a second end coupled to the voltage source, the resistance of the second pull-up resistor being higher than the characteristic impedance of the transmission line.