Patent ID: 8395233
Filing Date: 2013-03-12
Classification: H01F,H01L,Y10T

Abstract:
1. An integrated circuit (IC) device comprising: at least one base layer including a substrate and at least one ground plane layer; at least a first upper layer disposed on said base layer; at least a second upper layer disposed on said first upper layer, said substrate having at least one cavity region extending through at least said base layer, said first upper layer, and at least a portion of said second upper layer; wherein at least a portion of said second upper layer in said cavity region comprises at least one planar inductive element substantially parallel to a major surface of said base layer, said planar inductive element formed of at least one inductive trace and having a first contacting end and a second contacting end; at least one side wall partially enclosing said at least one cavity region, formed of portions of said base layer and said first upper layer defining said cavity, and extending transverse to said major surface of said base layer and a plane defined by said planar inductive element; and at least one support member which extends in a direction from said at least one sidewall to project at least partially into said cavity region in at least a first direction parallel to said major surface of said base layer, wherein said support member intersects said inductive trace at a plurality of distinct locations along a length of said at least one inductive trace intermediate of said first contacting end and said second contacting end.