Patent ID: 8725987
Filing Date: 2014-05-13
Classification: G06F

Abstract:
1. A system for caching data, comprising: a cache memory within a cache, the cache memory configured to store a copy of one or more portions of data stored in a system memory; a cache load circuit within the cache, the cache load circuit configured to retrieve portions of data from the system memory and to store a copy of the retrieved portions of data in the cache memory; a pre-fetch register within the cache, the pre-fetch register configured to be accessed by the cache load circuit and to store a value written to the pre-fetch register by any of multiple modules external to the cache, wherein the external modules include at least a processor; and a monitoring component within the cache, the monitoring component configured to determine when a value has been written to the pre-fetch register and to signal the cache load circuit when a value has been written to the pre-fetch register, wherein the cache load circuit is configured, in response to the monitoring component determining that a value has been written to the pre-fetch register,