Patent ID: 6987314
Filing Date: 2006-01-17
Classification: H01L

Abstract:
1. A stackable semiconductor package comprising: a substrate comprising a first side surface including metal first circuit patterns, and a second side surface opposite the first side surface and including metal second circuit patterns, wherein each of the first circuit patterns includes a respective one of a plurality of first pads, the first pads are aligned in a plurality of rows, each of the first pads is a lateral distance “a” from immediately adjacent ones of said first pads, and at least some of the first circuit patterns are electrically coupled through the substrate to at least some of the second circuit patterns; a semiconductor die electrically coupled to the first circuit patterns; an encapsulant covering the semiconductor die and a portion of the first side surface of the substrate, wherein the encapsulant has substantially vertical sidewalls extending a vertical distance “d” from the first side surface of the substrate, all of the first pads are external to the encapsulant, and each of the first pads that is immediately adjacent to one of the sidewalls of the encapsulant is a lateral distance “b” from the respective sidewall; and a plurality of layers of a solder, wherein each of the layers of the solder is fused to a respective one of the first pads, and has an exposed exterior surface portion that faces in a same direction as the first side surface of the substrate and extends a maximum vertical distance “c” from the first side surface of the substrate, wherein each of the solder layers is adapted to be soldered to a respective solder ball of another semiconductor package that is to be stacked on the stackable semiconductor package over the first side surface of the substrate, and wherein a>b and c<d.