Patent ID: 9171621
Filing Date: 2015-10-27
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory comprising: a plurality of memory cells, wherein each of the memory cells comprises: wherein at least one of the first and second wells is shared between adjacent memory cells in the nonvolatile memory; and wherein the nonvolatile memory applies a first voltage for recording data to at least one of a source region, a drain region and a well region of the first MOSFET so as to record data in the memory, applies a preset voltage to the second well shared between a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell, applies a preset voltage to at least one of a source region and a drain region of the second MOSFET, and controls to 0 V or float a source region and a drain region of a second MOSFET included in a memory cell not selected for recording the data, so that electrons are injected into a floating gate of the second MOSFET by tunneling.