Patent ID: 6873532
Filing Date: 2005-03-29
Classification: G11C

Abstract:
1. A content addressable memory (CAM) cell comprising: a cross-coupled inverter pair formed from a first pair of adjacent insulated gate transistors of a first conductivity type coupled to a second pair of adjacent insulated gate transistors of a second conductivity type; a pair of complementary bitlines coupled to said cross-coupled inverter pair by a third pair of adjacent insulated gate transistors of said first conductivity type; a comparison circuit formed from a fourth pair of adjacent insulated gate transistors of said second conductivity type and coupled to said cross-coupled inverter pair and a search line for comparing data stored in said cross-coupled inverter pair to a search data value provided on said search line; wherein said first pair of adjacent insulated gate transistors is positioned adjacent to said second pair and said first and second pairs are positioned adjacent to said third and four pairs, respectively, to form an 4×2 or 2×4 transistor matrix.