Patent ID: 6340829
Filing Date: 2002-01-22
Classification: H01L

Abstract:
A semiconductor device, comprising:an underlying layer being an insulator; a semiconductor layer provided on a surface of said underlying layer; a gate insulating film provided on a first region in a surface of said semiconductor layer; a gate electrode provided on a surface of said gate insulating film; a side wall spacer provided only on second and third regions adjacent to said first region in said surface of said semiconductor layer, covering side surfaces of said gate insulating film and side surfaces of said gate electrode; a first insulating film contacting only fourth and fifth regions adjacent to said second and third regions, respectively, in said surface of said semiconductor layer, on surfaces of said side wall spacer and on a surface of said gate electrode; a second insulating film provided only on a surface of said first insulating film, being different in material from said first insulating film; a first impurity layer of the first conductivity type extending from a center portion of said first region to the inside of said semiconductor layer; a second impurity layer of the second conductivity type adjacent to said first impurity layer, extending from said first region, said second region, said fourth region, a sixth region externally adjacent to said fourth region to the inside of said semiconductor layer; a third impurity layer of the second conductivity type adjacent to said first impurity layer, extending from said first region, said third region, said fifth region, a seventh region externally adjacent to said fifth region to the inside of said semiconductor layer; a first silicide layer provided only on said sixth region and inside said second impurity layer located below said sixth region, of which a bottom surface is located inside said second impurity layer; and a second silicide layer provided only on said seventh region and inside third impurity layer located below said seventh region, of which a bottom surface is located inside said third impurity layer; wherein a portion of said second and third impurity layers are formed below respective bottom surfaces of said first and second silicide layers, and said first and second silicide layers do not contact said underlying layer.