Patent ID: 7466599
Filing Date: 2008-12-16
Classification: G11C,H01L

Abstract:
1. A semiconductor device equipped with a memory cell having a data writing element and a capacitive element, comprising: a first well of a second conductivity type formed in a semiconductor substrate of the second conductivity type; a second well of the second conductivity type formed in the semiconductor substrate; and a first conductive film extending over the first well and the second well via a first insulating film; wherein a semiconductor isolation layer of a first conductivity type is formed in the semiconductor substrate, wherein the first and second wells are formed in the semiconductor isolation layer and are separated from each other, wherein the data writing element is arranged in the first well, wherein the capacitive element is arranged in the second well, wherein the data writing element includes the first insulating film, the first conductive film and a first impurity region of the first conductivity type formed in the first well, wherein the capacitive element includes the first insulating film, the first conductive film and a second impurity region of the second conductivity type formed in the second well, wherein the planar size of the first conductive film of the capacitive element is larger than the planar size of the first conductive film of the data writing element, wherein the first conductive film is adapted to be used as a charging storage film of the memory cell, and wherein the second impurity region is adapted to be used as a control gate of the memory cell.