Patent ID: 8952976
Filing Date: 2015-02-10
Classification: G06F,G06T

Abstract:
1. Parallel processor comprising: an array comprising processing elements, data storage components and access means; a control processor; memory control means configured to enable addressing of at least one of the access means of the array by the control processor; and connecting means configured to connect the memory control means to at least one of the access means of the array; wherein each access means is configured to enable write access to a single corresponding data storage components having a single corresponding processing element, and wherein the write access to at least one of the data storage components comprises a write mask mode, wherein, if the access means determine that a first write mask mode is requested, the write mask mode comprises setting individual bits and clearing remaining bits and, if the access means determine that a second write mask mode is requested, the write mask mode comprises setting individual bits and leaving other bits unchanged.