Patent ID: 7017133
Filing Date: 2006-03-21
Classification: G06F,H01L

Abstract:
1. A designing method of an electronic device, comprising: a first extraction step that extracts a first sub-region from a layout region, said layout region including easy-to-polish regions showing a large polishing rate in a chemical mechanical polishing process and hard-to-polish regions showing a smaller polishing rate in said chemical mechanical polishing process; a first layout step comprising the steps of: obtaining a ratio of an area of said first sub-region occupied by said hard-to-polish regions to an area of said first sub-region as a first coverage ratio; comparing said first coverage ratio with a first allowable coverage ratio, said first allowable coverage ratio indicating an allowable area of said first sub-region occupied by said hard-to-polish regions to said area of said first sub-region for achieving a flatness after said chemical mechanical polishing process; and increasing an area of said easy-to-polish regions when said first coverage ratio exceeds said first allowable coverage ratio, increasing an area of said hard-to-polish regions when said first coverage ratio is smaller than said first allowable coverage ratio; a second extraction step that extracts a second sub-region larger than said first sub-region from said layout region; and a second layout step comprising the steps of: obtaining a ratio of an area of said second sub-region occupied by said hard-to-polish region to an area of said second sub-region as a second coverage ratio; comparing said second coverage ratio with a second allowable coverage ratio, said second allowable coverage ratio indicating an allowable area of said second sub-region occupied by said hard-to-polish regions to said area of said second sub-region for achieving a flatness after said chemical mechanical polishing process; and increasing said area of said easy-to-polish regions when said second coverage ratio exceeds said second allowable coverage ratio, increasing said area of said hard-to-polish regions when said second coverage ratio is smaller than said second allowable coverage ratio, said designing method further comprising a step, before said first and second extraction steps, of excluding easy-to-polish regions having an edge length of 5 μm or less for a shorter edge thereof from said layout region.