Patent ID: 6507524
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A memory array comprising:a plurality of data inputs-outputs; a first zone of memory elements arranged in rows and columns, wherein each column in the first zone has a respective bit line, the columns in the first zone are arranged in a plurality of input-output sets, and the respective bit line input-output nodes of each set are multiplexed into a respective one of the data inputs-outputs; and a plurality of bit line input-output nodes which are each switchably coupled to either a respective one of the bit lines in the first zone or another one of the bit lines in the first zone, wherein at least one of the bit line input-output nodes is switchably coupled to either a respective one of the bit lines in one of the input-output sets or another of the bit lines in another one of the input-output sets.