Patent ID: 6858893
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A semiconductor memory comprising: a first-conductivity-type silicon substrate having a cell array region in which a plurality of rectangular silicon pillars are formed in rows and columns by a trench having a width of a storage node formed of a second-conductivity-type semiconductor layer on at least a surface of a lower portion of each of the plurality of silicon pillars; a first-conductivity-type well region formed in an upper half above the storage node of each of the plurality of silicon pillars, a portion of the well region present on one side surface of each of the silicon pillars functioning as channel portion of a vertical MIS transistor; a second-conductivity-type diffusion layer formed on an upper surface of the well region; a capacitor insulating film formed on the storage node so as to surround the lower portion of each of the plurality of silicon pillars; a plate electrode buried in a lower portion of the trench to substantially the same level as an upper end of the storage node; a first gate insulating film of the vertical MIS transistor formed on a surface of the channel portion; a first gate electrode formed on the first gate insulating film so as to oppose the channel portion; and a collar insulating film so formed as to fill a portion of the trench above the plate electrode, wherein the first gate electrode is buried in the trench such that a lower end of the first gate electrode is in contact with the collar insulating film and opposing main surfaces of the first gate electrode are in contact with the first gate insulating film and the collar insulating film, and is linearly formed in a first direction along the one side surface of each of the plurality of silicon pillars in the same row.