Patent ID: 6258646
Filing Date: 2001-07-10
Classification: H01L,Y10S

Abstract:
A method for forming an integrated circuit, comprising in sequence:providing a first gate conductor laterally spaced from a second gate conductor upon respective first and second channel areas of a semiconductor topography;patterning a spacer dielectric upon opposed sidewall surfaces of said first and second gate conductors;implanting an n-type species of a first concentration into said semiconductor topography a spaced distance from only said first channel area;removing said spacer dielectric;annealing said semiconductor topography at a first temperature;implanting n-type species of a second concentration less than the first concentration into said semiconductor topography substantially adjacent only said first channel area;annealing said semiconductor topography at a second temperature less than said first temperature;implanting a p-type species of a third concentration into said semiconductor topography substantially adjacent only said second channel area;annealing said semiconductor topography at a third temperature less than said first and second temperatures;re-patterning another spacer dielectric upon opposed sidewall surfaces of said first and second gate conductors;implanting p-type species of a fourth concentration greater than the third concentration into said semiconductor topography a spaced distance from only said second channel area; andannealing said semiconductor topography at a fourth temperature less than said first and second temperatures.