Patent ID: 8775996
Filing Date: 2014-07-08
Classification: G06F

Abstract:
1. A method comprising: determining, within a sector in a clock network design for a microprocessor, combinations of candidate sink locations for sector buffers, wherein the candidate sink locations comprise candidate connection points for connecting output terminals of the sector buffers to wire structures of the sector; for each of the combinations of candidate sink locations, storing, by a computer, the results of the direct current circuit analysis for the combinations of candidate sink locations; determining, with the results of the direct current circuit analysis, which of the combination of candidate sink locations has at least one of the minimum variance of voltage and the minimum of the maximum values of currents; and selecting, as connection points for the output terminals of the sector buffers, the combination of candidate sink locations that has at least one of the minimum variance of voltage and the minimum of the maximum values of currents.