Patent ID: 8571847
Filing Date: 2013-10-29
Classification: G06F,Y02D

Abstract:
1. A processor-implemented method for improving efficiency of a core turn-off in a physical multi-core processor with variation, wherein the physical multi-core processor is based upon a multi-core processor design, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor design at a design stage, wherein the turn-off analysis of the multi-core processor design includes a first output corresponding to a core of the multi-core processor design to turn off; conducting a turn-off analysis of the physical multi-core processor at a testing stage, wherein the turn-off analysis of the physical multi-core processor includes a second output corresponding to a core of the physical multi-core processor to turn off; comparing the first output and the second output to determine if the core referred to by the first output is the same core as the core referred to by the second output; and outputting a third output corresponding to the core referred to by both the first output and the second output if the comparing indicates that the core referred to by the first output is the same core as the core referred to by the second output.