Patent ID: 7283419
Filing Date: 2007-10-16
Classification: G11C

Abstract:
1. An integrated semiconductor memory device that can be operated in a first and second memory configuration, the integrated semiconductor memory device comprising: a plurality of memory cells that are arranged in a first memory zone and in a second memory zone; a register that stores a signaling bit for identifying an access to the first memory zone or the second memory zone; a plurality of first address connections that apply first address signals so as to select one of the memory cells within the first or second memory zone for access via the first address signals; a second address connection that applies a second address signal; and a control circuit to control the integrated semiconductor memory device; wherein the control circuit is configured to access the first memory zone or the second memory zone based upon the second address signal present at the second address connection in the first memory configuration of the integrated semiconductor memory device, and the control circuit is configured to access the first memory zone or the second memory zone based upon a state of the signaling bit in the second memory configuration of the integrated semiconductor memory device.