Patent ID: 7411815
Filing Date: 2008-08-12
Classification: G11C

Abstract:
1. A memory device comprising: a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each memory cell in the plurality of memory cells having a first connection coupled to one of the bitlines, a second connection coupled to one of the word lines and a ground connection; wherein each memory cell is electrically connected such that current is capable of flowing through the memory cell between the first connection and the ground connection in a positive direction and in a negative direction; wherein each memory cell in the plurality of memory cells is configured so that a first logical value is written to the memory cell by application of a current in the positive direction through the memory cell, and a second logical value is written to the memory cell by application of a current in the negative direction through the memory cell; and wherein the ground connection of each memory cell in the plurality of memory cells is electrically connected to a fixed ground.