Patent ID: 6067263
Filing Date: 2000-05-23
Classification: G11C

Abstract:
A dynamic random access memory circuit including a first memory cell and a first dummy cell coupled to a first bit line, a second memory cell and a second dummy cell coupled to a second bit line, and a sense amplifier for sensing a voltage differential appearing between the first bit line and the second bit line, said dynamic random access memory circuit comprising:a testing system operable to test the sensitivity of said sense amplifier by independently controlling the voltage differential appearing between the first bit line and the second bit line and by monitoring at least one input/output signal in response to sensing the voltage differential, wherein said testing system independently controls the voltage differential appearing between the first bit line and the second bit line by enabling the first dummy cell to transfer a predetermined first reference charge onto the first bit line and by enabling the second dummy cell to transfer a predetermined second reference charge onto the second bit line during which said first and second memory cells are disabled.