Patent ID: 8037441
Filing Date: 2011-10-11
Classification: G06F

Abstract:
1. A method for designing an integrated circuit, the method comprising: using a computer for providing a circuit description; providing a plurality of cells comprising pre-determined circuit parts, each cell having at least one circuit pin providing electrical connection from the cell to a wiring element; forming a placement layout of cells from said plurality of cells that represents said circuit description and satisfies pre-determined technological design rules, wherein each cell within the placement layout comprises a pin region within which said at least one circuit pin may be legally connected to a wiring element according to said technological design rules; providing a routing grid for designing routing paths of interconnections between cells; identifying an offending cell of said plurality of cells within said placement layout wherein said pin region of said offending cell does not legally align with a location on said routing grid; prior to performing a routing of interconnections between cells in said placement layout, moving the location of said offending cell so that said pin region of said offending cell is legally aligned with said routing grid while continuing to satisfy said technological design rules, wherein said routing grid is characterized by a routing grid spacing and said placement layout is arranged on a placement grid having a placement grid spacing that is different than said routing grid spacing, and determining a greatest common divider of said placement grid spacing and said routing grid spacing.