Patent ID: 9058902
Filing Date: 2015-06-16
Classification: G11C

Abstract:
1. A method of detecting the transistor mismatch in a SRAM cell, wherein the SRAM cell comprises a first and a second pass-gate transistors (PG 1 , PG 2 ), and a bi-stable circuit which includes a first and a second pull up transistors (PU 1 , PU 2 ) and a first and a second pull down transistors (PD 1 , PD 2 ); wherein, the gate electrodes of the first and the second pass-gate transistors are connected to a first word line (WLA), the source electrodes thereof are connected to the outputs of the bi-stable circuit respectively, and the drain electrodes thereof are connected to a first and a second bit line (BL, BL ) respectively; the method comprises: step a, providing a first and a second measuring transistors (PM step b, enabling the second word line (WLB) and disabling the first word line (WLA); step c, determining the value of the data stored in the SRAM cell, if the data is “0”, turning to step d step d step d step e, determining whether the voltage-current curves of the first and second pull down transistors (PD step f, enabling the first word line (WLA) and disabling the second word line (WLB), and writing a complementary data into the SRAM cell and turning to step a; step g, determining the transistor mismatch according to the voltage-current curves of the first and second pull down transistors (PD