Patent ID: 6975143
Filing Date: 2005-12-13
Classification: H01L,H03K

Abstract:
1. A static logic circuit on a SOI substrate comprising: a pull-up network comprising a plurality of parallel connected MOS transistors with a first and second common node, wherein at least one of said plurality of parallel connected MOS transistors is a NMOS transistor and at least one of said plurality of parallel connected MOS transistors is a PMOS transistor; a circuit supply voltage which is connected to said first common node of said pull-up network; a pull-down network which is connected to said second common node of said pull-up network wherein said pull-down network comprises a plurality of series connected MOS transistors connected to a circuit ground, and wherein at least one of said plurality of series connected MOS transistors is a NMOS transistor and at least one of said plurality of series connected MOS transistors is a PMOS transistor; and an output node which is connected to said second common node of said pull-up network.