Patent ID: 9170907
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. A method of providing synchronization and integrity checking in a high integrity processing system having at least two redundant processing lanes, with each lane having an application processor (AP), with the APs running the same application software in a non-lockstep configuration, and outputting transactions requiring access to an addressable space, the method comprising: outputting a first transaction from a first AP in a first processing lane and running application software in a non-lockstep configuration; storing the first transaction in a second buffer of a second processing lane and associated with a second AP; effecting a processing of the first transaction in the first processing lane; storing the effected processing of the first transaction in the second buffer; outputting a second transaction from the second AP running the same application software in a non-lockstep configuration; storing the second transaction in the second buffer; comparing the first and second transactions to determine if they match; and returning the effected processing of the first transaction to the second AP from the second buffer when the first and second transactions match.