Patent ID: 6466049
Filing Date: 2002-10-15
Classification: H03K

Abstract:
A clock enable control circuit for controlling a flip flop, the flip flop having a data input terminal, a set terminal, a reset terminal, a data output terminal, and a clock input terminal, the clock enable control circuit comprising:a data multiplexer having a first input terminal connected to the data output terminal of the flip flop, a second input terminal for receiving a data signal, an output terminal connected to the data input terminal of the flip flop, and a select terminal; and a switching circuit including means for selectively passing a set control signal either to the set terminal of the flip flop or to the select terminal of the data multiplexer, and means for selectively passing a reset control signal either to the reset terminal of the flip flop or to the select terminal of the data multiplexer, wherein the data multiplexer is selectively controlled using either of the set control signal or the reset control signal to feed back a data value stored in the data output terminal to the data input terminal of the flip flop, thereby effectively disabling a clock signal applied to the clock input terminal of the flip flop.