Patent ID: 8943114
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. An apparatus comprising: a first circuit configured to receive a first 2N-bit complex number and a second 2N-bit complex number, each having a first format in which each real and imaginary part of each 2N-bit complex number has a sign portion, comprising one or more most significant bits, and a magnitude portion, comprising all remaining bits, and to reformat the first and the second 2N-bit complex numbers to a second format such that each real and imaginary part of each reformatted 2N-bit complex number comprises a signed upper portion and a signed lower portion and the signed lower portion of each real and imaginary part of each reformatted 2N-bit complex number is positive; and a second circuit configured to multiply the reformatted first and the reformatted second 2N-bit complex numbers using at least one N-bit signed complex multiplier, wherein N is an integer.