Patent ID: 6191998
Filing Date: 2001-02-20
Classification: G11C

Abstract:
A programmable logic device comprising:a plurality of programmable logic regions wherein the plurality of programmable logic regions are arranged in intersecting rows and columns;a plurality of first combinable single-port memory arrays each having a plurality of rows and columns of memory cells for storing data;a plurality of second combinable single-port memory arrays each associated with a respective one of the first combinable single-port memory arrays and each having a plurality of rows and columns of memory cells for storing data, wherein the first and second combinable single-port memory arrays are combinable to form a plurality of dual-port memory arrays and wherein the first and second combinable single-port memory arrays are arranged in intersecting rows and columns; anda plurality of interconnects for routing signals between the programmable logic regions and the first and second combinable single-port memory arrays.