Patent ID: 8569161
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a dielectric layer on an active side of a semiconductor substrate, wherein the dielectric layer has openings at least partially aligned with corresponding copper terminals at the active side of the substrate, and wherein the copper terminals are electrically coupled to an integrated circuit in the substrate; depositing a liner on the dielectric layer and the copper terminals; depositing a copper layer on the liner; removing portions of the liner and the copper layer until the dielectric layer is exposed in areas between the openings, wherein adhesion elements having discrete portions of the liner and copper deposits remain in individual openings, and wherein the individual adhesion elements each include a depression at least partially extending into the corresponding opening of the dielectric material; forming individual nickel deposits on the corresponding adhesion elements, wherein the individual nickel deposits at least substantially fill the depressions in the adhesion elements; forming individual wirebond films on corresponding nickel deposits, wherein the individual nickel deposits each have a volume in the depression greater than that of the wirebond film in the depression, and wherein the wirebond films and the nickel deposits define wirebond elements that are electrically isolated from each other; and attaching wirebonds to corresponding wirebond films.