Patent ID: 8604359
Filing Date: 2013-12-10
Classification: H01L,H05K,Y10T

Abstract:
1. A package substrate, comprising: a core layer having a first circuit pattern on its first surface; a first dielectric layer covering the first circuit pattern; a second circuit pattern on the first dielectric layer, the second circuit pattern comprising an interconnect circuit pattern located in a chip mounting area; a first solder mask covering the second circuit pattern outside the chip mounting area, the first solder mask having a top surface; an insulation layer covering the chip mounting area and the interconnect circuit pattern; and a plurality of embedded bond pads disposed in a top surface of the insulation layer, wherein one of the plurality of embedded bond pads is electrically connected to the interconnect circuit pattern through a via plug in the insulation layer, and the interconnect circuit pattern, the via plug, and the insulation layer constitute an interposer, wherein the top surface of the insulating layer is higher than the top surface of the first solder mask.