Patent ID: 6643163
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A semiconductor memory device comprising:a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells arranged in a matrix form each constituted of a cell transistor and a ferroelectric capacitor having a first end connected to a source of the cell transistor, a plurality of word lines connected to gates of the cell transistors of the memory cells, a plurality of pairs of bit lines connected to drains of the cell transistors of the memory cells, a plate line connected to a second end of the ferroelectric capacitor, and a plurality of sense amplifier circuits each connected to a corresponding pair of bit lines; and a control circuit which controls the semiconductor memory circuit in an operation time to raise the word lines to be selected from a first potential to a second potential to read cell data from the memory cells onto the bit lines, thereafter set the bit lines to a high level to write â€œ1â€  data into the memory cells regardless of a logic level of data to be written, thereafter set the selected word lines to a third potential lower than the second potential and higher than the first potential, set the bit lines to a low level with â€œ0â€  data to be written to write â€œ0â€  data into the memory cells, and thereafter to lower the selected word lines to the first potential.