Patent ID: 7132869
Filing Date: 2006-11-07
Classification: H03L

Abstract:
1. A power-down enable zero idle time Z-state circuit for making three systems become three zero idle time systems, comprising: a feedback line connected with the output and input of the power-down enable zero idle time Z-state circuit; a sensing inverter for sensing a voltage at the feedback line and generating a midpoint voltage decided by the device aspect ratios of the sensing inverter; a power-down inverter for forcing the feedback line to be at ground so that no current flows during power-down mode; a two-input CMOS NAND gate for being used as an enabling inverter with one input serving as an inverting power-down input and the other used as the inverting sensing input; a lower PMOS transistor for being completely turned off during normal mode and being completely turned on during power-down mode, wherein its gate terminal is coupled to the output of the power-down inverter; and an upper PMOS transistors for being incompletely turned off during normal mode, in response to the output of the CMOS NAND gate.