Patent ID: 8738977
Filing Date: 2014-05-27
Classification: G11C

Abstract:
1. In a system including a processor and memory coupled to the processor, a method of device failure analysis, the method comprising the steps of: performing a plurality of tests on a device; detecting a first error at a given address of the device in a first one of the plurality of tests, the first error being associated with a first set of bit positions corresponding to the given address; storing in a table a first entry for the given address, the first entry identifying the first set of bit positions; detecting a second error at the given address of the device in a second one of the plurality of tests, the second error being associated with a second set of bit positions corresponding to the given address; storing in the table a second entry for the given address, the second entry identifying the second set of bit positions; determining whether the second set of bit positions comprises any bit positions which are not in the first set of bit positions; responsive to determining that at least one bit position in the second set of bit positions is not in the first set of bit positions, modifying the first entry in the table to identify a third set of bit positions, the third set of bit positions comprising the first set of bit positions and the at least one bit position in the second set of bit positions which is not in the first set of bit positions; and determining that the device fails the plurality of tests if a number of bit positions in the third set of bit positions exceeds an error correction capability of error correction circuitry associated with the device; wherein modifying the first entry in the table comprises applying one or more logical functions to the first entry and the second entry.