Patent ID: 8952555
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: (1) a glass substrate having an electrode, and (2) a semiconductor chip disposed on the glass substrate, the semiconductor chip including: (a) a semiconductor substrate including an alignment mark formation region and an integrated circuit formation region; (b) a MISFET formed over the semiconductor substrate, the MISFET being formed in the integrated circuit formation region; (c) a first wiring layer formed over the MISFET, the first wiring layer formed in the integrated circuit formation region; (d) a plurality of first patterns formed over the semiconductor substrate and in the same layer as the first wiring layer, the plurality of first patterns being formed in the alignment mark formation region; (e) a first interlayer insulating film formed over the semiconductor substrate to cover the first wiring layer and the plurality of first patterns; (f) a second wiring layer formed over the first interlayer insulating film, the second wiring layer being formed in the integrated circuit formation region; (g) a plurality of second patterns formed over the first interlayer insulating film and in the same layer as the second wiring layer, the plurality of second patterns being formed in the alignment mark formation region; (h) a second interlayer insulating film formed over the semiconductor substrate to cover the second wiring layer and the plurality of second patterns; (i) a third wiring layer formed over the second interlayer insulating film, the third wiring layer being formed in the integrated circuit formation region; (j) an alignment mark formed over the second interlayer insulating film and in the same layer as the third wiring layer, the alignment mark being formed in the alignment mark formation region; (k) a further insulating film formed over the semiconductor substrate to cover the third wiring and the alignment mark, the further insulating film having an opening at an upper side of the third wiring layer; and (l) a bump electrode formed over the further insulating film and electrically connected to the third wiring layer via the opening, wherein the plurality of first patterns and the plurality of second patterns are formed so as to be shifted from each other in a plan view, wherein the first wiring, the second wiring and the third wiring are electrically connected to the MISFET, wherein the plurality of first patterns and the plurality of second patterns are not electrically connected to the MISFET, and wherein the bump electrode of the semiconductor chip and the electrode of the glass substrate are electrically connected via an anisotropic conductive film formed between the semiconductor chip and the glass substrate.