Patent ID: 6229360
Filing Date: 2001-05-08
Classification: G06F,H03K

Abstract:
A synchronization circuit comprising:a first latching circuit having an input terminal, an output terminal and a clock terminal, transferring an input signal from said input terminal to said output terminal for a predetermined period in response to a level transition timing of one direction of a clock signal input to said clock terminal, and maintaining a signal condition of said output terminal in the remaining period;a second latching circuit having an input terminal, an output terminal and a clock terminal, transferring an input signal from said input terminal to said output terminal for a predetermined period in response to a level transition timing of the other direction of said clock signal input to said clock terminal, and maintaining a signal condition of said output terminal in the remaining period; anda logic circuit connected between said first and second latching circuit,a common clock signal being supplied to said clock terminals of said first and second latching circuits;wherein assuming a period of a first level of said clock signal being Tch, a period of a second level being Tcl, and a period of sum of a skew and a jitter of said clock signal being Ts,in said first latching circuit, a minimum value of a period for transferring said input signal of said input terminal being said output terminal being Twh and a maximum value being k.times.Twh (k is an actual number greater than one),in said second latching circuit, a maximum value of a period for transferring said input signal of said input terminal to said output terminal being Twl and a maximum value being k.times.Twl, setting satisfyingTs<Twh<(Tch-Ts)/kTs<Twl<(Tch-Ts)/kbeing established.