Patent ID: 6496429
Filing Date: 2002-12-17
Classification: G11C

Abstract:
A semiconductor memory device comprising:a normal array having normal memory cells arranged in rows and columns and divided into column blocks in a unit of a predetermined number of columns; a spare array having spare memory cells arranged in rows and columns, for repairing a defective cell in said normal memory cells by replacement; a plurality of normal internal data lines, disposed in correspondence with said column blocks, each coupled to a selected column of a corresponding column block; a spare internal data line disposed in correspondence with said spare array and coupled to a selected column of said spare array; a plurality of normal data terminals disposed in correspondence with said plurality of normal internal data lines, for receiving external data; a spare data terminal disposed in correspondence with said spare internal data line, for receiving external data; and test control circuitry for electrically coupling said plurality of normal data terminals and said plurality of normal internal data lines and for electrically coupling said spare internal data line and said spare data terminal in response to a test mode instruction signal.