Patent ID: 7558890
Filing Date: 2009-07-07
Classification: G06F,H04L

Abstract:
1. A device comprising: a scheduler configured to schedule queues of data in a memory based on at least one of: rate and bandwidth guarantee; an execution unit comprising an input bus and decode logic coupled to the input bus, the decode logic being configured to decode from the input bus at least a set of instructions related to queuing; wherein the set of instructions related to queuing comprises: wherein the execution unit executes the first operation code in response to identification of the first operation code by the decode logic and executes the second operation code in response to identification of the second operation code by the decode logic; and a network processor coupled to the input bus, the network processor comprising a processing unit programmed to identify a queue number and generate at least one instruction for each unit of data to be transmitted on the input bus, the processing unit in the network processor comprising another decode logic different from said decode logic of the execution unit; wherein the network processor transmits at least the queue number to the execution unit on the input bus; and wherein the execution unit and the scheduler are included in a traffic manager, the traffic manager being coupled to the network processor by the input bus.