Patent ID: 6456147
Filing Date: 2002-09-24
Classification: H03K

Abstract:
An output interface circuit comprising:(a) a first output buffer circuit for receiving an output signal of an internal circuit to output a first output signal; (b) a second output buffer circuit for receiving the output signal of the internal circuit to output a second output signal; and (c) an output-level adjusting circuit for receiving the second output signal outputted from the second output buffer circuit and for adjusting a level of the second output signal thus received to output a third output signal corresponding to the second output signal to an external output terminal; wherein the first output buffer circuit outputs the first output signal to the external output terminal responsive to a first control signal that represents an external supply voltage having a first relationship with a specific value; and wherein the second output buffer circuit outputs the second output signal to the output-level adjusting circuit responsive to a second control signal that represents the external supply voltage having a second relationship with the specific value opposite to the first relationship, the first control signal and the second control signal bypassing the internal circuit.