Patent ID: 6927483
Filing Date: 2005-08-09
Classification: H01L

Abstract:
1. A semiconductor package comprising: a semiconductor die; a plurality of first leads defining an inner set which extends at least partially about the semiconductor die in spaced relation thereto, each of the first leads defining opposed, generally planar top and bottom surfaces and a partially etched surface which is recessed relative to the bottom surface; a plurality of second leads defining an outer set which extends at least partially about the inner set in spaced relation thereto, each of the second leads defining opposed, generally planar top and bottom surfaces and a partially etched surface which is recessed relative to the bottom surface, the semiconductor die being electrically connected to at least one of each of the first and second leads; an encapsulant for encapsulating the semiconductor die and the first and second leads such that the bottom surfaces of the first and second leads are at least partially exposed in the encapsulant; and a channel disposed in the encapsulant and separating the inner and outer sets from each other, the partially etched surfaces of the first and second leads extending to the channel.