Patent ID: 6433601
Filing Date: 2002-08-13
Classification: H03K

Abstract:
A circuit comprising:a first network configuration that is configured to provide a first node state corresponding to a data input state, second network configuration that is configured to provide a second node state corresponding to an inversion of the data input state, a pulse generator that is responsive to an external clock signal and is configured to enable a propagation of the data input state and the inversion of the data input state to the first node state and to the second node state, for a predefined duration after an active edge of the clock signal, and a latch that is operably coupled between the first network configuration and the second network configuration, and is configured to store an internal state corresponding to the data input state, for producing an output state for a continuous duration, until a subsequent rising edge of the clock signal; wherein: the first network configuration comprises a first series arrangement of switches, responsive to the clock signal, that includes an input and an output, and the input of the first series arrangement corresponds to the data input state, and the output of the first series arrangement provides the first node state, and the second network configuration comprises a second series arrangement of switches, responsive to the clock signal, that includes an input and an output, and the input of the second series arrangement corresponds to an inversion of the data input state, and the output of the second series arrangement provides the second node state.