Patent ID: 6366509
Filing Date: 2002-04-02
Classification: G11C

Abstract:
In a memory device including an array of memory cells arranged in rows and columns, the array being divided into first and second sub-arrays each of which contains a digit line for each column of memory cells, the memory device further comprising a plurality of column circuits each of which is associated with a respective digit line in the first and second sub-arrays, a method of coupling data signals between each column circuit and the associated digit line in the first sub-array or the associated digit line in the second sub-array, the method comprising:if neither of the digit lines associated with the column circuit is affected by a defect in the respective sub-arrays, allowing the column circuit to be coupled to the associated digit line in the first sub-array and the associated digit line in the second sub-array; if the digit line in the first sub-array that is associated with the column circuit is affected by a defect in the first sub-array, preventing the column circuit from being coupled to the associated digit line in the first sub-array and allowing the column circuit to be coupled to the associated digit line in the second sub-array; and if the digit line in the second sub-array that is associated with the column circuit is affected by a defect in the second sub-array, preventing the column circuit from being coupled to the associated digit line in the second sub-array and allowing the column circuit to be coupled to the associated digit line in the first sub-array.