Patent ID: 6955967
Filing Date: 2005-10-18
Classification: B82Y,G11C,H01L

Abstract:
1. A process for forming a nonvolatile memory comprising: providing a substrate; identifying a first area of the substrate for a memory array and a second area of the substrate for a reference transistor; forming a first dielectric layer overlying the substrate; forming a storage material layer overlying the first dielectric layer; forming a second dielectric layer overlying and surrounding the storage material layer; forming a first barrier layer overlying the second dielectric layer; providing a pattern to selectively remove the first barrier layer, the first and second dielectric layers and the storage material layer from all areas except above the first area of the substrate; forming a third dielectric layer overlying the second area of the substrate and overlying the first barrier layer above the first area of the substrate; forming a fourth dielectric layer overlying the third dielectric layer above the first area of the substrate and the second area of the substrate; forming a second barrier layer overlying the fourth dielectric layer; selectively removing the second barrier layer, the third dielectric and the fourth dielectric everywhere except overlying the second area of the substrate; removing the first barrier layer overlying the first area of the substrate and removing the second barrier layer overlying the second area of the substrate; forming a conductive gate layer overlying the second dielectric in the first area of the substrate and overlying the fourth dielectric in the second area of the substrate; patterning gate stacks of transistors in the first area of the substrate and a reference gate stack in the second area of the substrate; and forming current electrode regions in the first area of the substrate and the second area of the substrate to form memory cells in the first area of the substrate and a reference transistor in the second area of the substrate.