Patent ID: 7601549
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method of processing semiconductor wafers wherein lots of wafers are processed in a sequence of processing steps that includes at least one epitaxy step performed in the same processing chamber for all of said lots, comprising the steps of: a) prior to said epitaxy step, forming a pattern of recesses in an exposed surface of each wafer in a lot; b) including at least one recessed test structure in the pattern of recesses; c) determining at least one dimension of the recessed test structure prior to said epitaxy step; d) measuring a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step; e) determining a deviation between the dimension determined in step c) and the dimension measured in step d); f) from the deviation determined in step e), determining the process temperature at which the epitaxy step was performed; g) in case the deviation determined in step f) exceeds a predetermined limit, adjusting the temperature in said processing chamber for a subsequent lot of wafers to be processed.