Patent ID: 6014738
Filing Date: 2000-01-11
Classification: G06F

Abstract:
In a computer having a memory and an incoming signal, a method for processing the incoming signal comprising:packing a first plurality of integers into contiguous memory space to produce a first 32-bit word, wherein each integer has a defined number of bits between one and eight;packing a second plurality of integers into contiguous memory space to produce a second 32-bit word, wherein each integer has said defined number of bits;replicating said first plurality of integers into contiguous memory space to produce a first 32-bit mask with a third plurality of integers, said first plurality of integers having a most significant bit (MSB) for each byte in said first 32-bit word forming an MSB plurality of integer positions, said first 32-bit mask having said MSB plurality of integer positions and a non-MSB plurality of integer positions corresponding to the remaining bits of each byte in said first 32-bit word and setting each bit in said MSB plurality to low and each bit in said non-MSB plurality to high in said 32-bit mask;conducting a first bitwise AND of said second 32-bit word with said 32-bit mask to produce a first result;conducting a first bitwise OR of said first 32-bit word with the compliment of said first 32-bit mask to produce a second result;conducting a first EXCLUSIVE OR of said first 32-bit word and the compliment of said second 32-bit word to produce a third result;conducting a second bitwise AND of said third result and the compliment of said compliment of said 32-bit mask to produce a fourth result;subtracting said second result from first result to produce a fifth result; andconducting a second EXCLUSIVE OR of said fifth result and said fourth result to produce a sixth result.