Patent ID: 8412886
Filing Date: 2013-04-02
Classification: G06F

Abstract:
1. A cache controller that controls access requests to a cache shared by plural threads that are simultaneously executed, the cache controller comprising: a port unit provided in a form shared by a plurality of threads, the port unit having plural entries and holding access requests to the entries; a measuring unit to measure a frequency of access requests issued by each of the threads; a control unit to divide the port unit dynamically into one or a plurality of port sections based on a measurement result of the measuring unit, allocating the threads into the divided one or the plurality of port sections respectively, registering an access request issued by one of the threads with a port section allocated to an issuer thread; a first selecting unit provided in association with each of the threads, the first selecting unit receiving, as input, access requests registered with one of the port sections and selecting an access request among the received access requests according to a specified priority control; and a second selecting unit to receive, as input, the access requests selected by the first selecting unit and selecting a final access request among the selected access requests according to a thread selection signal.