Patent ID: 6563506
Filing Date: 2003-05-13
Classification: G06F,G09G

Abstract:
An integrated circuit comprising:a plurality of clients; a plurality of timers, wherein each of the plurality of timers corresponds to one of the plurality of clients; wherein, for each of client of the plurality of clients, a corresponding timer determines a memory access limit and a memory access interval, wherein the memory access interval determines the minimum length of an interval between memory accesses for the corresponding client and wherein the memory access limit determines the maximum protected length of a memory access for the corresponding client, wherein the maximum protected length is a duration during which the memory access cannot be interrupted by another access of similar or lower priority and during which the memory access of a client is capable of being interrupted by another access of a higher priority client; a memory; a memory controller operably coupled to the memory and the plurality of clients, wherein the memory controller receives memory access request from the plurality of clients, and wherein the memory controller selectively grants the memory access request.