Patent ID: 7382645
Filing Date: 2008-06-03
Classification: G11C

Abstract:
1. A memory comprising: a memory array that includes a plurality of two-terminal memory cells, each two-terminal memory cell including a non-ohmic device; a plurality of array lines that access the memory array; at least one reference cell external to the memory array and accessed by at least some of the array lines, the reference cell including the non-ohmic device, and wherein the reference cell is a two-terminal memory cell and contributes to a reference level; and a substrate positioned below the memory array and the reference cell, the substrate including, wherein the two-terminal memory cells are operative to be reversibly written to a first non-volatile resistive state when the selected array lines are at the first write voltage, are operative to be reversibly written to a second non-volatile resistive state when the selected array lines are at the second write voltage, and produce a read output when the selected array lines are at the read voltage, and wherein the sensing circuitry is operative to compare the read output to the reference level and produce data signals.