Patent ID: 7608494
Filing Date: 2009-10-27
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate wire on an insulating substrate, the gate wire including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line; forming a gate insulating layer; forming a semiconductor layer; depositing a conductive layer and patterning the conductive layer to form a data wire including a data line intersecting the gate line, a data pad connected to the data line, a source electrode connected to the data line and placed close to the gate electrode, and a drain electrode opposite the source electrode with respect to the gate electrode; forming a protective layer; patterning the protective layer together with the gate insulating layer to form a plurality of contact holes respectively exposing the gate pad, the data pad and the drain electrode; and depositing a transparent conductive layer and patterning the conductive layer to form a subsidiary gate pad, a subsidiary data pad and a pixel electrode respectively connected to the gate pad, the data pad, and the pixel electrode, wherein at least one of the formation of the gate wire and the formation of the data wire comprises: forming a Ag alloy layer by sputtering Ag and an additive including at least one selected from the group consisting of Zn, In, Sn and Cr; patterning the Ag alloy layer; and heat-treating the Ag alloy layer.