Patent ID: 6011728
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A semiconductor memory device that accesses a memory cell in synchronization with a clock signal, comprising the following:at least two mode signal inputs that input operation mode signals that designate one of a read mode, a write mode, and an operation mode provided with a read-and-write mode;an input data latch circuit that temporarily stores data to be written into a memory cell; andan operation control circuit that evaluates the operation mode designated by said operation mode signals, and, when an operation mode designated by said operation mode signals is evaluated to be said read-and-write mode, controls successive operations of a read-out operation, that is the same as that of said read mode, in a first step within one clock cycle, and during this operation, temporarily stores data that is to be written in a memory cell in said input data latch circuit, and next, in a second step of the same clock cycle, writes-in data temporarily stored in said input data latch circuit to a memory cell selected in said first step.