Patent ID: 7947549
Filing Date: 2011-05-24
Classification: H01L

Abstract:
1. A method for fabricating a CMOS circuit, comprising: PFET and NFET devices, wherein said PFET and NFET devices are both characterized as being metal gate devices with high-k gate insulators; blanket disposing over a PFET region and a NFET region a high-k insulator material; blanket disposing over said high-k insulator material a gate metal material; concomitantly patterning a PFET gate layer and a NFET gate layer and a PFET gate dielectric layer a NFET gate dielectric layer out of said gate metal material and said high-k insulator material; in said PFET device, forming a first interfacial control layer in such manner to have said PFET gate dielectric layer in-between and in direct contact with said first interfacial control layer and said PFET gate layer, wherein selecting said first interfacial control layer to be between about 0.1 nm and about 1 nm thick and to consist essentially of aluminum oxide; and in said NFET device, forming a second interfacial control layer in such manner to have said second interfacial control layer in-between and in direct contact with said NFET gate dielectric layer and said NFET gate layer, wherein selecting said second interfacial control layer to be an oxide of at least one element selected from the combination of groups IIA and IIIB.