Patent ID: 8607174
Filing Date: 2013-12-10
Classification: G06F

Abstract:
1. A system for designing and emulating a user design, which system comprises: (i) a verification module and system controller comprising: (a) an interface to a user workstation; (b) at least one field programmable logic device configured as an conventional embedded logic analyzer IP circuit description; and (c) at least one first clock and user signal compression tunnel portal; and (ii) at least one SoC partition logic module coupled to the first clock and user signal value compression tunnel portal of the verification module, each partition logic module comprising: (d) a plurality of field programmable logic devices for emulating the user design wherein each field programmable logic device comprises, in addition to the user design, a circuit for a user signal compression tunnel, the circuit for a user signal compression tunnel coupled to at least one second clock and user signal compression tunnel portal, whereby a portion of the user design assigned to the programmable logic device communicates with portions of the user design assigned to other programmable logic devices; and (iii) off chip storage wherein the embedded logic analyzer is coupled to: a circuit to receive a user signal compression address and to read signal values from off-chip storage and to transfer signal values to a user workstation; and wherein the circuit for a user signal compression tunnel transfers an address when a signal value has been previously stored in off-chip storage.