Patent ID: 7561472
Filing Date: 2009-07-14
Classification: G11C

Abstract:
1. A method of operating a non-volatile memory, comprising: placing a bit line precharge voltage on a first and second bit lines, wherein the first and second bit lines are from differing array banks of a non-volatile memory array, where the non-volatile memory array contains a plurality of non-volatile memory cells coupled into a plurality of array banks; placing a read voltage on a control gate of a selected non-volatile memory cell; coupling the selected non-volatile memory cell to a source line and the first bit line; placing a read voltage on a control gate of a selected reference non-volatile memory cell of a reference NAND architecture memory string, wherein the selected reference non-volatile memory cell has a threshold voltage corresponding to a particular logic state and wherein one or more unselected reference non-volatile memory of cells of the reference NAND architecture memory string have threshold voltage corresponding to logic states different than the particular logic state; coupling the selected reference non-volatile memory cell to a source line and the second bit line; and sensing the difference between a voltage level of the first bit line and a voltage level of the second bit line to determine whether a threshold voltage level of the selected non-volatile memory cell corresponds to the particular logic state.