Patent ID: 8510503
Filing Date: 2013-08-13
Classification: G06F

Abstract:
1. A ring buffer circuit, comprising: a read and write memory having addresses specified by N bits (N is an integer equal to or larger than two); a write address counter pointer for counting an (N+1)-bit Gray code, the write address counter pointer being a counter pointer having an address which is updated for each writing into the read and write memory and returned to a first address to continue counting when the address reaches a final address; a read address counter pointer for counting an (N+1)-bit Gray code, the read address counter pointer being a counter pointer having an address which is updated for each reading from the read and write memory and returned to the first address to continue counting when the address reaches the final address; a write address converter circuit for converting the (N+1)-bit Gray code output from the write address counter pointer into an N-bit Gray code address which may be directly designated as a write address of the read and write memory; and a read address converter circuit for converting the (N+1)-bit Gray code output from the read address counter pointer into an N-bit Gray code address which may be directly designated as a read address of the read and write memory.