Patent ID: 7111033
Filing Date: 2006-09-19
Classification: G06F

Abstract:
1. A carry save adder circuit for reducing the number of inputs to a lower number of outputs, said carry save adder circuit comprising four carry save adders, said four carry save adders being arranged in two layers with the first and second carry save adders being arranged in a first of said layers and the third and fourth carry save adders being arranged in a second of said layers, said third and fourth carry save adders being arranged to provide said outputs, two of the said outputs having a equal weight, said third and fourth carry save adders each receiving at least one output from each of said first and second carry save adders and the first and second carry save adders being arranged to receive at least some of said inputs; wherein the carry save adder circuit is a 9 to 4 carry save adder circuit; and wherein the first carry save adder is a 5 to 3 carry save adder and the second, third and fourth carry save adders are 3 to 2 carry save adders.