Patent ID: 8195845
Filing Date: 2012-06-05
Classification: G06F

Abstract:
1. A memory system comprising: a host controller including a register set configured to control command issue to a device, and a direct memory access (DMA) unit configured to access a system memory, the host controller controlling data transfer between the system memory and the device; a first descriptor stored in the system memory, the first descriptor including a set of a plurality of pointers indicating a plurality of second descriptors; a third descriptor forming each of the plurality of second descriptors, the third descriptor including a command number, a command operation mode, and an argument as information necessary to issue a command to the device, and a block length and the number of blocks as information necessary for data transfer; and a fourth descriptor forming each of the plurality of second descriptors, the fourth descriptor including information indicating addresses and sizes of a plurality of data arranged in the system memory, wherein the DMA unit sets, in the register set, contents of the third descriptor forming the second descriptor, from a head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with contents of the fourth descriptor.