Patent ID: 6269468
Filing Date: 2001-07-31
Classification: G06F

Abstract:
A method for optimizing a design of a circuit, the method comprising the steps of:a) identifying a circuit element that drives both a critical circuit path and a non-critical circuit path, which critical path fails a timing requirement of the circuit,b) replacing the circuit element with a split I/O circuit, said split I/O circuit comprising:i) a logic stage for receiving input signals and performing a logic evaluation in response to the input signals; and,ii) an output stage coupled to the logic stage and to a plurality of outputs for driving a results of the logic evaluation therethrough, the outputs coupled to circuit paths having varying levels of criticality and load magnitudes, and wherein the output stage includes a plurality of drive circuits; and,c) selectively coupling together one or more of said plurality of drive circuits to simultaneously drive an output net sink based on a criticality level of a circuit path coupled to the individual output sink and on a load magnitude of the output sink.