Patent ID: 9094237
Filing Date: 2015-07-28
Classification: H04L

Abstract:
1. A network device comprising: a switching memory comprising a plurality of switching memory queues associated with a plurality of ports of the network device, each switching memory queue being mapped to a corresponding one of the plurality of ports; one or more processors to examine a header of a received packet to determine a destination address that identifies one or more network destinations to which the packet is to be routed via the network device, form a packet context from at least a portion of the header of the received packet, wherein the packet context includes at least the destination address of the received packet, determining whether a destination queue selected from the plurality of switching memory queues can be assigned to the packet based at least on a portion of the packet context, if a destination queue can be assigned to the packet based at least on the portion of the packet context then assigning the destination queue to the packet, if a destination queue cannot be assigned to the packet based at least on the portion of the packet context then stroking the packet context associated with the packet, determining the destination queue from the stroked packet context, and assigning the destination queue determined from the stroked packet context to the packet; a striper to divide the packet into multiple cells after the destination queue has been assigned to the packet; and a memory control unit to write the multiple cells of the packet to contiguous locations in the destination queue, so that the multiple cells for the packet are stored contiguously in the switching memory as a function of the destination address of the packet.