Patent ID: 6820188
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A circuit for providing an instruction stream to a processing device, comprising:an input to receive an external instruction stream for provision of a first set of instruction values; a memory adapted to contain a second set of instruction values; two or more outputs for provision of output instruction streams to the processing device; a control input; and a selection means adapted to distribute the first set of instruction values and the second set of instruction values between the two or more outputs according to the control input; wherein the selection means provides for a bitwise selection of values between the first set of instruction values and the second set of instruction values, wherein for each selection of a value one bit from either of the first set of instruction values and the second set of instruction values is directed to one of the two or more outputs, and a corresponding bit from the other of the first set of instruction values and the second set of instruction values is directed to another of the two or more outputs; and wherein the control input provides a value with the same number of bits as the external instruction stream, and said bitwise selection of values is made with reference to a bit of the control input value corresponding to an equally significant bit of the external instruction stream.