Patent ID: 6114221
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method for fabricating an interconnected multiple circuit chip structure comprising the steps of:step 1, etching a first silicon substrate to form at least one protrusion on a surface of the first substrate;step 2, preferentially etching the at least one protrusion to produce a selected shape for providing a first alignment structure element;step 3, preferentially etching at least one cavity in the surface of a second substrate to form at least one alignment recess element having a selected shape that is the complement of the selected shape of the at least one protrusion;step 4, coating the at least one protrusion and the at least one recess with an electrically conductive metal to provide first and second electrical and thermal connectors on the alignment structure elements;step 5, joining and aligning the first substrate and the second substrate together wherein the at least one protrusion mates and aligns with the at least one recess and the metal coatings thereon come into contact to form an electrical circuit connection.