Patent ID: 6332000
Filing Date: 2001-12-18
Classification: H03H,H04L

Abstract:
An adaptive equalizer comprising:a plurality of first delaying means for delaying input data in response to a symbol clock signal;a clock generating means receiving a system clock signal for producing a plurality of control signals using the system clock signal which is faster than the symbol clock signal, for classifying the delayed data;a plurality of selecting means for selecting output data from the first delaying means in response to the control signals provided by the clock generating means;a plurality of coefficient value updating means for receiving a previous error value and alternatively receiving the delayed and selected input data and then updating a coefficient value in response to the system clock signal;a convolutional operating means for receiving outputs of the coefficient value updating means and alternatively receiving the delayed and selected input data; andan error value generating means for calculating an error value from an output of the convolutional operating means and providing the calculated error to the plurality of coefficient value updating means.