Patent ID: 6136640
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A process for fabricating a metal-metal capacitor within an integrated circuit, the integrated circuit comprising a lower insulating layer, a first metal layer which is on top of the lower insulating layer, and an upper insulating layer which is on top of the first metal layer; and the capacitor comprising a first metal electrode, a second metal electrode, and a dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer, the process comprising the steps of:depositing the first metal layer on top of the lower insulating layer;etching the first metal layer so as to form the first metal electrode;depositing the dielectric layer on top of the etched first metal layer;producing the second metal electrode on top of the lower insulating layer; anddepositing the upper insulating layer on top of the two metal electrodes and the dielectric layer.