Patent ID: 6265275
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method for making a selectively doped intrinsic collector of a vertical bipolar transistor comprising an extrinsic collector layer, an offset extrinsic collector well, an emitter and a base, the method comprising:forming an intrinsic collector on the extrinsic collector layer buried in a semiconductor substrate;forming a side insulation region surrounding an upper part of the intrinsic collector and the offset extrinsic collector well; andforming a silicon/germanium heterojunction base above the intrinsic collector and the side insulation region byperforming a first implantation of dopants in the intrinsic collector through a first implantation window formed above the intrinsic collector,nonselectively epitaxially growing a stack of layers including silicon and silicon/germanium above the first implantation window, the side insulation region and the offset extrinsic collector well, andperforming a second implantation of dopants in the intrinsic collector with a lower energy and lower implantation dose through the epitaxially grown stack through a second implantation window lying inside the first implantation window formed above the stack and self-aligned with the emitter.