Patent ID: 6469562
Filing Date: 2002-10-22
Classification: G09G,H03F

Abstract:
A source follower with Vgs compensation and offset voltage cancellation, comprising:a CMOS circuit having a MOSFET M1 and a MOSFET M2, the drain terminal of the MOSFET M1 being connected with a supply voltage, and the drain terminal of the MOSFET M2 being connected with ground, the gate terminal of the MOSFET M1 being connected with a capacitor Cs, and the gate terminal of the MOSFET M2 being connected with a terminal of a first switch SW1, the other terminal of the first switch SW1 being connected with an input voltage Vin and a second switch SW2, the source terminal of the MOSFET M1 being connected with a first constant current source and the gate terminal of the MOSFET M2, the source terminal of the MOSFET M2 being connected with a second constant current source and a load to provide an output voltage Vout, a third switch SW1 being provided between the output voltage Vout and the capacitor Cs, one terminal of the capacitor Cs being connected with the first switch SW1 and the other terminal of the capoacitor Cs being connected with the second switch SW2 and the first switch SW1; wherein the output voltage Vout can be obtained when the following steps are completed in sequence: a. the first switch SW1 and the third switch SW1 are switched on while the second switch SW2 is switched off; b. the second switch SW2 is switched on while first switch SW1 and the third switch SW1 are switched off.