Patent ID: 7515159
Filing Date: 2009-04-07
Classification: G06T

Abstract:
1. A reconfigurable address generation circuit for image processing, which is configured to an arbitrary state based upon configuration data, and which generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data of an enlarged block, having a block including at least a partial pixel group within a frame, and pixels surrounding the block, wherein as the configuration data, there are set a X count end value corresponding to a number of columns of the read out pixel unit and a Y count end value corresponding to a number of rows of the read out pixel unit, a width value which indicates the number of columns of the enlarged block, and edge information which indicates an edge, for which clip processing is performed on the read out pixel unit, the address generation circuit comprising: an X counter which counts repeatedly up to the X count end value; a Y counter which counts up to the Y count end value in response to a carry signal of the X counter; an X clip processing circuit which converts the count value of the X counter according to the left and right edge information; a Y clip processing circuit which converts the count value of the Y counter according to the top and bottom edge information; and an address calculation circuit which generates the reading out address, based upon the count values from the X and Y clip processing circuits and the width value.