Patent ID: 7881413
Filing Date: 2011-02-01
Classification: H03L,H04J

Abstract:
1. A phase locked loop, comprising: a phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal; a loop filter having an input for receiving the error signal and an output for providing a control signal; an oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal; a processor coupled to the oscillator, wherein the processor is further coupled to receive a status message from a source of the reference clock signal indicative of a quality level of the reference clock signal; and a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon capable of causing the processor to monitor the status message and to selectively place the phase locked loop in a holdover condition in response to the status message; wherein the instructions stored on the machine-readable medium are capable of causing the processor to place the phase locked loop in the holdover condition when a quality level of the reference clock signal indicated by the status message is less than an expected quality level of the phase locked loop in the holdover condition.