Patent ID: 6195304
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A semiconductor memory device in which memory cells are periodically refreshed to an activated level, comprising:a memory cell array having a number of memory cells configured in a square or rectangular formation, the memory cell array having predetermined capacitive loads which are different at different memory locations, the capacitive loads including a smallest capacitive load and a largest capacitive load;a refresh address counter which outputs a number of bit signals which constitute a refresh address signal, the refresh address signal indicating an address of a memory cell to be refreshed in the memory device, the bit signals having predetermined high/low-state change periods which are different from each other, the bit signals including a first bit signal corresponding to the smallest capacitive load and a second bit signal corresponding to the largest capacitive load; anda selector, provided to connect the outputs of the refresh address counter to the memory cell array, which assigns the predetermined high/low-state change periods for the respective bit signals of the refresh address signal in accordance with a correspondence between the bit signals and the capacitive loads such that a smallest high/low-state change period is assigned for the first bit signal corresponding to the smallest capacitive load and a largest high/low-state change period is assigned for the second bit signal corresponding to the largest capacitive load.