Patent ID: 7924632
Filing Date: 2011-04-12
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier detecting a voltage or a current of the bit line, and which decides the read data from each of the memory cells; a clamping transistor connected between the sense amplifier and the bit lines, and which determines a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; a clamp voltage generation circuit generating the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer; and wherein the memory cell array is divided into a plurality of blocks in a direction in which the bit lines extend, and the clamp voltage generation circuit determines the clamp voltage on the basis of an address of the block to which the selected memory cell belongs.