Patent ID: 8253441
Filing Date: 2012-08-28
Classification: H03K

Abstract:
1. A circuit comprising: a first latch having a first input and a first output, the first input of the first latch to receive a first digital signal, wherein the first latch receives a first power supply voltage and a second power supply voltage, wherein the first power supply voltage is greater than the second power supply voltage; a second latch having a first input and a first output, wherein the first input of the second latch is coupled to the first output of the first latch, wherein the second latch receives a third power supply voltage and a fourth power supply voltage, wherein the third power supply voltage is greater than the fourth power supply voltage, and wherein at least one of the first power supply voltage and the second power supply voltage is different than at least one of the third power supply voltage and the fourth power supply voltage; a third latch having a first input and a first output, the first input of the third latch to receive a second digital signal, wherein the third latch receives the first power supply voltage and the second power supply voltage; a fourth latch having a first input and a first output, wherein the first input of the fourth latch is coupled to the first output of the third latch, wherein the fourth latch receives a fifth power supply voltage and a sixth power supply voltage, wherein the fifth power supply voltage is greater than the sixth power supply voltage, and wherein at least one of the first power supply voltage and the second power supply voltage is different than at least one of the fifth power supply voltage and the sixth power supply voltage; a first transistor having at least a first terminal and a second terminal, wherein the first terminal of the first transistor is coupled to the first output of the second latch, and wherein the second terminal of the first transistor receives a first voltage; a second transistor having at least a first terminal and a second terminal, wherein the first terminal of the second transistor is coupled to the first output of the fourth latch, and wherein the second terminal of the second transistor receives a second voltage, wherein the first transistor has a first safe operating range, and wherein a first voltage range of the first output of the second latch is within the first safe operating range of the first transistor, and wherein the second transistor has a second safe operating range, and wherein a second voltage range of the first output of the fourth latch is within the second safe operating range of the second transistor.