Patent ID: 6131173
Filing Date: 2000-10-10
Classification: G01R

Abstract:
Integrated circuit comprising a first and a second clock domain being respectively controlled by a first and a second clock signal, the first clock domain and the second clock domain being interconnected via a set of interface signal paths, each of which comprising a respective string of flip-flops, an initial flip-flop of the string being located in the first clock domain and a final flip-flop of the string being located in the second clock domain, the string being arranged for serially moving a data bit along its flip-flops from the first to the second clock domain under control of the first and the second clock signals, characterized in that each one of the interface signal paths includes a first seam circuit that is configured to facilitate testing of the integrated circuit, the first seam circuit comprising: a seam input; a seam output coupled to the final flip-flop; a feedback loop having a seam multiplexer and a seam flip-flop being part of the relevant string and being part of a scan test chain, the seam flip-flop feeding a first input of the multiplexer, a second input of the multiplexer representing the seam input, an output of the feedback loop representing the seam output; so that a first state of the multiplexer allows loading of a data bit into the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop.