Patent ID: 6249144
Filing Date: 2001-06-19
Classification: H01L,H03K

Abstract:
A method for configuring a field programmable gate array (FPGA) wherein said FPGA has variably granulatable building elements provided in respective building block regions such that the building elements can be folded-together during configuration to define differently-sized logic-implementing units and wherein said FPGA further has Configurable Sequential Elements (CSE's) associated with the building blocks for storing and outputting respective result signals to adjacent interconnect lines, wherein each CSE includes a plurality of registers where at least two of the registers of a given CSE can be each configurably coupled to receive and store a respective logic result signal produced by one or a folded-together combination of said building elements, and where said configuring method comprises:(a) causing a given building block to acquire an input signal from an adjacent interconnect line and to forward the acquired input signal to a corresponding CSE;(b) causing the corresponding CSE to return the forwarded input signal to at least one building element of the building block for processing by the at least one building element; and(c) causing the processed signal to be sent back to the corresponding CSE for output by the corresponding CSE to an adjacent interconnect line.