Patent ID: 7332400
Filing Date: 2008-02-19
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: sequentially forming a gate insulation layer and a gate electrode on a substrate, an active region being defined on the substrate; forming a first gate spacer along a side surface of the gate electrode, wherein the first gate spacer includes a first insulation layer and a second insulation layer formed on the first insulation layer; forming a planarized layer on the substrate including the gate electrode and the first gate spacer; removing a first portion of the planarized layer, so that an upper portion of the gate electrode is exposed; selectively forming a silicon epitaxial layer on the exposed upper portion of the gate electrode, wherein a side surface of the silicon epitaxial layer is substantially aligned with an upper side surface of the first insulation layer; removing a remaining portion of the planarized layer; forming a second gate spacer along side surfaces of the silicon epitaxial layer and the first gate spacer; and forming a source/drain region on a surface portion of the active region corresponding to the gate electrode.