Patent ID: 6487210
Filing Date: 2002-11-26
Classification: H04L

Abstract:
An output buffer of a switch core, comprising:a chain master queuing element, wherein the chain master queuing element includes a first data input and a daisy chain output, wherein the chain master queuing element receives data from a first source via the first data input, wherein the chain master queuing element inserts the data from the first source into a data stream provided on the daisy chain output based on arbitration information; and a plurality of queuing elements, wherein each queuing element of the plurality of queuing elements includes a first data input, a daisy chain input, and a daisy chain output, wherein the plurality of queuing elements are intercoupled in a daisy chain such that the daisy chain input of each succeeding queuing element is operably coupled to the daisy chain output of each preceding queuing element, wherein the daisy chain input of a first queuing element in the daisy chain is operably coupled to the daisy chain output of the chain master queuing element, wherein the daisy chain output of a last queuing element in the daisy chain provides an output signal from the output buffer, wherein each of the plurality of queuing elements receives data on the data input from a first corresponding source of a first plurality of corresponding sources, wherein each corresponding source of the first plurality of corresponding sources corresponds to one of the plurality of queuing elements, wherein each of the plurality of queuing elements inserts the data from the first corresponding source into the data stream based on the arbitration information.