Patent ID: 8625379
Filing Date: 2014-01-07
Classification: G11C

Abstract:
1. A circuit semiconductor storage device comprising: a plurality of memory macros coupled in series, each of the plurality of memory macros including a plurality of memory cell arrays; a high-potential power supply step-down circuit provided for each of the plurality of memory cell arrays, the high-potential power supply step-down circuit provided between a high-potential power supply and a respective memory cell array, the high-potential power supply step-down circuit being configured to couple the high-potential power supply to the respective memory cell array in a normal mode and configured to couple the respective memory cell array to a voltage level lower than the high-potential power supply in a sleep mode; a virtual power control circuit provided for each of the plurality of memory cell arrays, the virtual power control circuit including a plurality of switches provided in parallel with the high-potential power supply step-down circuit, each of the plurality of switches supplying an output to the high-potential power supply step-down circuit independent of every other one of the plurality of switches, the plurality of switches being configured to be turned on when a mode control signal indicates to switch from the sleep mode to the normal mode and configured to be turned off when a mode control signal indicates to switch from the normal mode to the sleep mode; and a sleep cancellation detecting circuit configured to receive the mode control signal and to output a subsequent mode control signal to a subsequent memory macro subsequent to one of the plurality of memory macros when the mode control signal supplied to the plurality of switches of one of the plurality of memory cell arrays in the one of the plurality of memory macros indicates to switch from the sleep mode to the normal mode.