Patent ID: 6785863
Filing Date: 2004-08-31
Classification: H03M

Abstract:
A method for operating a transmitter that generates parity check bits (p1. . . , pm) based on a current symbol set (s1, . . . , sk), the method comprising the steps of:receiving the current symbol set (s1, . . . , sk); using a transformation of a matrix to determine the parity check bits, wherein the first N2 columns of the matrix is defined by: a deterministic section with N2 columns of weight-2; for column i, 1&lE;i&lE;&boxur;m/2&boxul;, assign a value of 1 to row position i and a value of 1 to row position i+&boxur;m/2&boxul;, all other row positions have a value of 0; for column i, &boxur;m/2&boxul;+1&lE;i&lE;N2a non-deterministic section with most columns of weight greater than or equal to 2; transmitting the parity check bits along with the current symbol set; and wherein the matrix is equal to: [I(m/2)Ã—(m/2)I(N2-m/2)Ã—(N2-m/2)0(m-N2)Ã—(N2-m/2)C(m/2)Ã—(n-N2)I(m/2)Ã—(m/2)01Ã—(N2-m/2)I(N2-m/2)Ã—(N2-m/2)0(m-N2-1)Ã—(N2-m/2)D(m/2)Ã—(n-N2)]&it;â€ƒ&it;or&it;&NewLine;[I&LeftFloor;m/2&RightFloor;Ã—&LeftFloor;m/2&RightFloor;I(N2-&LeftFloor;m/2&RightFloor;)Ã—(N2-&LeftFloor;m/2&RightFloor;)0(m-1-N2)Ã—(N2-&LeftFloor;m/2&RightFloor;)C&LeftFloor;m/2&RightFloor;Ã—(n-N2)I&LeftFloor;m/2&RightFloor;Ã—&LeftFloor;m/2&RightFloor;01Ã—&LeftFloor;m/2&RightFloor;01Ã—(N2-&LeftFloor;m/2&RightFloor;)I(N2-&LeftFloor;m/2&RightFloor;)Ã—(N2-&LeftFloor;m/2&RightFloor;)0(m-N2-1)Ã—(N2-&LeftFloor;m/2&RightFloor;)D(m+1)/2Ã—(n-N2)]wherein C and D comprise a non-deterministic section of the matrix.