Patent ID: 6334190
Filing Date: 2001-12-25
Classification: B41J,B82Y,G03B,G06F,G06K,G06Q,G06T,G07F,G09G,G11B,G11C,H01L,H04L,H04N,H05K,Y02D,Y10S

Abstract:
A system for the manipulation of secure data having electronics or software, or both, that are designed to operate within a specific clock speed range; the system being provided with a clock frequency limiter in the clock signal line, upstream of elements that are to be protected, where the limiter involves an enable gate having an input port, an output port and a control port, and is located in the clock signal line to pass the clock signal from the input port to the output port only when it is enabled by a signal at the control port; clock signal taps are connected to pass clock signals from upstream and downstream of the enable gate to an edge detector, and the output of the edge detector is passed through a delay to the control port of the enable gate.