Patent ID: 6143596
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A method of planarizing a wafer having a device area and a periphery area, the method comprising the steps of:forming a first dielectric layer over said device area and said periphery area;etching said first dielectric layer to create a pattern having holes on said device area;forming a polysilicon layer along the surface of said pattern;forming a first photoresist in said holes;removing a part of said polysilicon layer being formed over the top surface of said first dielectric layer;stripping said first photoresist, thereby forming a pattern array and a dummy pattern around said pattern array;forming a second photoresist on said first dielectric layer that on said periphery area and said second photoresist covering a portion of said dummy pattern;removing said first dielectric layer on said device area and leaving said first dielectric layer on said periphery area; andforming a second dielectric layer on said pattern array and said first dielectric layer.