Patent ID: 7584448
Filing Date: 2009-09-01
Classification: G06F

Abstract:
1. A processor-implemented method for constructing a model of a programmable logic device (PLD) design, comprising: inputting a netlist that describes the PLD design, the netlist including a plurality of instances of a plurality of modules, and the modules including a plurality of programmable tile modules and the instances including a plurality of tile instances of the programmable tile modules; inputting an identification of each of the programmable tile modules, each programmable tile module including at least one programmable resource, each programmable resource being one of a programmable interconnect resource configurable to implement a plurality of routing arcs and a programmable logic resource configurable to implement a plurality of logic functions; generating a first map from the netlist, the first map linking each of the routing arcs to at least one bit of configuration data for programming the programmable interconnect resources of the programmable tile modules; and generating a second map from the netlist, the second map linking each of the logic functions to at least one bit of configuration data for programming the programmable logic resources of the programmable tile modules wherein the inputting a netlist, the inputting an identification, the generating a first map, and the generating a second map are implemented on the processor.