Patent ID: 7473964
Filing Date: 2009-01-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: an insulating layer; a semiconductor fin protruding from the insulating layer, extending in a first direction parallel to a major surface of the insulating layer, and having a source region, a channel section, and a drain region arranged in the first direction; a gate electrode opposed at least to a side face of the channel section in the semiconductor fin and extending in a second direction that is substantially orthogonal to the first direction and parallel to the major surface of the insulating layer; an insulating film interposed between the semiconductor fin and the gate electrode; a spacer layer provided on the channel section; a sidewall insulating layer provided adjacent to a side face of the spacer layer substantially parallel to the second direction; and a stress liner covering the sidewall insulating layer and the spacer layer and having an intrinsic stress for distorting the semiconductor fin, the sidewall insulating layer having a thickness of 45 nanometers (nm) or more in the first direction, and the spacer layer having a height of 105 nanometers (nm) or more.