Patent ID: 8427888
Filing Date: 2013-04-23
Classification: G11C

Abstract:
1. A circuit device comprising: a local control circuit having a level shifter configured to shift a first address signal received from a main control circuit from a first voltage level to a second voltage level to provide a level shifted first address signal; and a word-line driver configured to receive at least one signal from the main control circuit and to receive the level shifted first address signal from the local control circuit, and the word line driver including an output that is electrically coupled to a word line of a memory cell array, wherein the word-line driver includes at least two-gate delays comprising a first gate having a first transistor for receiving the level shifted first address signal from the level shifter and a second transistor for receiving the first address signal, which reduces gate delay from the level shifter, wherein the second transistor is provided between a power supply terminal and an output of the first gate and is coupled in series with the first transistor, and wherein the first gate includes the second transistor that, when outputting a low signal responsive to receiving a high signal from the first address signal, turns off prior to the first transistor to reduce the gate delay from the level shifter.