Patent ID: 8664055
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A manufacturing process of a fin field-effect transistor structure, the manufacturing process comprising steps of: providing a substrate; forming a fin channel on the substrate; forming a pseudo gate structure on a surface of the fin channel; performing a lightly doped drain implantation process on the fin channel, so as to form a lightly doped drain region in the fin channel; forming a source/drain region in the fin channel; forming a first dielectric layer over the fin channel having the source/drain region, the pseudo gate structure and the substrate; performing a first planarization process until the pseudo gate structure is exposed; removing the pseudo gate structure to form a receiving space; forming a high-k dielectric layer and a metal gate layer on the substrate having the receiving space; and performing a second planarization process on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.