Patent ID: 6795869
Filing Date: 2004-09-21
Classification: H04L

Abstract:
A communication system having a communication channel with at least two ends, one end of said channel being connected to a transmission device with relatively limited computational capacity and an other end of said channel being connected to a computer having relatively large computational capacity, wherein:said transmission device comprising: (a) a signal source node; (b) a set of Mâˆ’1 delay buffers connected in series and defining a set of M progressively delayed signal nodes, M being a positive integer, one end of said series of M delay buffers being connected to said signal source node; (c) a set of M parallel downsampling operators connected to said M progressively delayed signal nodes; (d) a parallel-to-serial converter having M parallel inputs and a single serial output, said M parallel inputs being connected to the outputs of said M parallel downsampling operators and said single serial output being coupled to the one end of said communication channel; said computer having communication architecture comprising: (a) a serial-to-parallel converter having a single serial input and M parallel outputs, said single serial input being coupled to the other end of said communication channel; (b) a set of M parallel filter coefficient multipliers having respective inputs and outputs and corresponding to the respective coefficients Hi(zâˆ’1) of an anti-aliasing filter H(z)=&Sgr;i=0Mâˆ’1zâˆ’iHi(zâˆ’M), the inputs of said multipliers being connected to respective ones of the M parallel outputs of said serial-to-parallel converter; (c) a set of Mâˆ’1 adders connected in series to define a set of M inputs and a single output, the outputs of said M multipliers being connected to respective ones of said set of M inputs defined by the series of adders, said single output of the series of adders being a received signal output.