Patent ID: 7570507
Filing Date: 2009-08-04
Classification: G11C

Abstract:
1. A resistive memory device, comprising: an array portion of resistive memory cells, wherein a resistive memory cell is coupled between a pair of bit lines; and a read circuit operably associated with the bit line pair in the array portion configured to read a data state of the resistive memory cell associated with the respective bit line pair, wherein the read circuit comprises a precharge circuit configured to charge a first bit line of the respective bit line pair at a first rate, and charge a second bit line of the respective bit line pair at a second rate, wherein the first and second charge rates are based on a state of a memory cell coupled between the respective bit line pair, wherein a time constant TC of the first charge rate of the first bit line with the resistive memory cell in a SET state is about the same as the second charge rate of the second bit line with the resistive memory cell in the SET state.