Patent ID: 6326651
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A field-programmable gate array comprising:first and second basic cells, each of which includes a plurality of logic circuits and is formed on a semiconductor substrate; anda program element for connecting/disconnecting the first and second basic cells to/from each other responsive to a program externally input and for storing thereon the connection or disconnection state between the first and second cells,wherein the program element includes:a switching device, which is formed on the semiconductor substrate and turns ON/OFF to connect/disconnect the first and second basic cells to/from each other; anda nonvolatile memory device for storing thereon the ON/OFF states of the switching device, the memory device including a lower electrode, a capacitive insulating film made of a ferroelectric thin film, and an upper electrode, andwherein an interlevel insulating film is formed over the first and second basic cells and the switching device, andwherein a buffer layer for matching a lattice constant of the interlevel insulating film with that of the ferroelectric thin film is formed on the interlevel insulating film, andwherein the nonvolatile memory device is formed on the buffer layer.