Patent ID: 7962719
Filing Date: 2011-06-14
Classification: G06F

Abstract:
1. An apparatus operable to process a Fast Fourier Transform (FFT) on an array processor, the apparatus comprising: a plurality of processing elements (PEs), each PE comprising a data memory, a very long instruction word (VLIW) memory, a multiply complex execution unit, an instruction port, and a data port, wherein said data memory is operable to store a subset of input data, wherein said VLIW memory is operable to store multiply complex instructions in one or more VLIWs, wherein said multiply complex execution unit is operable to multiply two complex number input operands both of a first data format to form a complex number result of the first data format in response to each of the multiply complex instructions; an interconnection network coupled to the data port of each PE operable to communicate data between PEs selected from the plurality of PEs; and a control processor operable to fetch a sequence of instructions, wherein said control processor is further operable to distribute the sequence of instructions to the instruction port of each of the PEs to calculate an FFT on the input data, wherein each PE is operable to fetch a sequence of the one or more VLIWs from the VLIW memory based on said sequence of instructions, wherein the multiply complex execution unit on each PE is operable to calculate a local FFT on the subset of input data in response to the sequence of the one or more VLIWs and to calculate distributed FFTs on the results of the local FFTs using the interconnection network to communicate data between the selected PEs.