Patent ID: 8022552
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. An IC chip comprising: a semiconductor substrate; a transistor having a portion in said semiconductor substrate; a first dielectric layer over said semiconductor substrate; a first patterned metal layer over said first dielectric layer; a second dielectric layer over said first patterned metal layer and said first dielectric layer; a second patterned metal layer over said second dielectric layer; a third dielectric layer over said second dielectric layer and said second patterned metal layer, wherein a first opening through said third dielectric layer is over a first contact point of said second patterned metal layer, and said first contact point is at a bottom of said first opening, wherein a second opening through said third dielectric layer is over a second contact point of said second patterned metal layer, and said second contact point is at a bottom of said second opening, wherein a third opening through said third dielectric layer is over a third contact point of said second patterned metal layer, and said third contact point is at a bottom of said third opening, and wherein a fourth opening through said third dielectric layer is over a fourth contact point of said second patterned metal layer, and said fourth contact point is at a bottom of said fourth opening; a third patterned metal layer comprising a first interconnect on said third dielectric layer and said first and second contact points and a second interconnect on said third dielectric layer and said third and fourth contact points, wherein said first contact point is connected to said second contact point through said first interconnect, and wherein said third contact point is connected to said fourth contact point through said second interconnect, wherein said third patterned metal layer comprises a first copper layer; a nitride layer on a top surface and a sidewall of said first interconnect, on a top surface and a sidewall of said second interconnect and on said third dielectric layer; a first polymer layer over said nitride layer, wherein a fifth opening through said first polymer layer and said nitride layer is over a fifth contact point of said first interconnect, and said fifth contact point is at a bottom of said fifth opening, and wherein a sixth opening through said first polymer layer and said nitride layer is over a sixth contact point of said second interconnect, and said sixth contact point is at a bottom of said sixth opening, wherein said fifth contact point is connected to said first contact point through said first opening, wherein said fifth contact point is connected to said second contact point through said second opening, wherein said sixth contact point is connected to said third contact point through said third opening, and wherein said sixth contact point is connected to said fourth contact point through said fourth opening; and a fourth patterned metal layer on said first polymer layer and said fifth and sixth contact points, wherein said fifth contact point is connected to said sixth contact point through said fourth patterned metal layer, wherein said fourth patterned metal layer comprises a second copper layer.