Patent ID: 8705579
Filing Date: 2014-04-22
Classification: H04L,H04M,H04N,Y02D

Abstract:
1. A state machine for use in obtaining synchronization in an electronic system transferring digital data at a high rate between a host device and a client device over a communication path, the state machine configured to have at least one Acquiring Sync States synchronization states, and at least two In-Sync States synchronization states, comprising: a circuit to change synchronization states, the synchronization states comprising the at least one Acquiring Sync States synchronization states and at least two In-Sync States synchronization states; the circuit to change synchronization states comprising configuring the circuit for changing from a first Acquiring Sync State to a first In-Sync State comprising a no-sync state transitioning to the first In-Sync State based on detecting a presence of a synchronization pattern and a good CRC at a subframe boundary; the circuit to change synchronization states comprising configuring the circuit for changing from the first In-Sync State to a next In-Sync State comprising detecting the presence of a single bad CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data; and the circuit to change synchronization states comprising configuring the circuit for changing from the next In-Sync State to the first In-Sync State comprises detecting a presence of a single good CRC value without using a synchronization pattern, based on a calculated CRC value for every packet of the transferred digital data.