Patent ID: 6190966
Filing Date: 2001-02-20
Classification: H01L,Y10S

Abstract:
A process for fabricating a semiconductor structure having a local interconnect, comprising the steps of:(a) providing a semiconductor substrate;(b) forming a semiconductor device having an interconnect area on a surface of the substrate;(c) forming a silicon nitride etch stop layer over the surface of the substrate and the device using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least approximately 480.degree. C., wherein step (c) comprises forming the etch stop layer using Plasma Enhanced Chemical Vapor Deposition (PECVD) with:an SiH.sub.4 flow rate of approximately 55.+-.5 sccm;an NH.sub.3 flow rate of approximately 12.+-.2 sccm; andan RF power of approximately 375.+-.10 watts;(d) forming an insulator layer over the etch stop layer;(e) etching a first hole through the insulator layer to the etch stop layer in alignment with the interconnect area;(f) etching a second hole through the etch stop layer to the interconnect area; and(g) filling the first and second holes with an electrically conductive material which ohmically contacts the interconnect area to form the local interconnect.