Patent ID: 8497175
Filing Date: 2013-07-30
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming an isolation layer on a substrate, the isolation layer defining a plurality of active regions; forming first, second and third device regions on the substrate, the first, second and third device regions comprising a first, second and third active region, respectively; forming first, second and third gate structures extending over the first, second and third active regions, respectively, wherein the first active region comprises a first side surface connected to a second side surface by an upper surface, wherein the first gate structure is disposed between the first side surface of the first active region and the isolation layer, and is also disposed between the second side surface of the first active region and the isolation layer, wherein the second active region comprises an upper surface having a trench defined therein and at least one side surface, wherein the second gate structure covers at least a portion of the upper surface of the second active region and is disposed within the trench and between the at least one side surface of the second active region and the isolation layer, and wherein the third gate structure is disposed on an upper surface of the third active region.