Patent ID: 8003896
Filing Date: 2011-08-23
Classification: H05K,Y10T

Abstract:
1. A multi-layer printed wiring board comprising: a core substrate having a plurality of through-hole structures formed through the core substrate; a first interlayer insulation layer formed over the core substrate; a plurality of first filled vias formed in the first interlayer insulation layer and each having a bottom portion having a first diameter; a second interlayer insulation layer formed over the first interlayer insulation layer; a plurality of second filled vias formed in the second interlayer insulation layer and each having a bottom portion having a second diameter smaller than the first diameter; a plurality of pad structures formed on the second interlayer insulation layer and connected to the second filled vias, respectively; a solder resist layer formed over the second interlayer insulation layer and having a plurality of opening portions each exposing at least a portion of each of the pad structures; and a plurality of bump structures formed in the opening portions of the solder resist layer, respectively, and positioned to be connected to an IC chip, wherein each of the through-hole structures includes a sidewall conductor layer extending through the core substrate, the second filled vias are connected to the first filled vias, respectively, and positioned such that the second filled vias are under the IC chip, the first filled vias and second filled vias include ones positioned over the through-hole structure and on or inside an area over which the sidewall conductor layer of the through-hole structure is formed and ones positioned offset from the through-hole structure and outside the area, and the bump structures are connected to the second filled vias by the pad structures formed outside of the sidewall conductor layer, respectively; wherein the core substrate has a plurality of through-hole openings each having a radius of 100 μm or less, formed at a pitch of 385 μm or less, and the plurality.