Patent ID: 6847533
Filing Date: 2005-01-25
Classification: G11C

Abstract:
1. A memory system, comprising: a plurality of content addressable memory (CAM) cells arranged into an array, each of said CAM cells further comprising a storage element and a match detection circuit for detecting a match between incoming data and data stored in said storage element, said match detection circuit further comprising, a logic switch; a current sensing amplifier for detecting a current flow state between a first and second terminals, said current sensing amplifier also indicating said current flow state on a data terminal; a first current limiter having a third and fourth terminals and a first control terminal for accepting a first control signal to controllably limiting current flow between said third and fourth terminals, said first current limiter being coupled in series with the current sensing amplifier between said second and third terminals; a voltage regulator having a fifth and sixth terminals, said voltage regulator being coupled in series with said first current limiter between said fourth and fifth terminals and said sixth terminal being adapted to be coupled to the logic switch; and a current limit control circuit coupled to said first control terminal and for supplying said first control signal.