Patent ID: 8619937
Filing Date: 2013-12-31
Classification: H03L

Abstract:
1. An integrated Complementary Metal-Oxide-Semiconductor (CMOS) clock generator with a self-biased phase locked loop circuit comprising: a phase-frequency detector with a reference signal input, a feedback signal input and an output; a first charge pump with an input connected to the output of the phase-frequency detector and an output that supplies a control current; a loop capacitor connected to the output of the first charge pump; a second charge pump with an input connected to the output of the phase-frequency detector and an output; a first oscillator block including: a first bias generator that has an input connected to the output of the first charge pump and an output; a capacitor connected to the output of the first bias generator; a second bias generator that has an input connected to the output of the first bias generator and an output; and a voltage controlled oscillator with a control input connected to the output of the second bias generator and an output; a second oscillator block including: a first bias generator that has an input connected to the output of the first charge pump and an output; a capacitor connected to the output of the first bias generator; a second bias generator that has an input connected to the output of the first bias generator and an output; and a voltage controlled oscillator with a control input connected to the output of the second bias generator and an output; a first switch selectively connecting the output of the second charge pump with the input of the second bias generator in the first oscillator block or with the input of the second bias generator in the second oscillator block; a second switch with a first input connected to the output of the voltage controlled oscillator in the first oscillator block and a second input connected to the output of the voltage controlled oscillator in the second oscillator block and a clock output; a third switch for selectively connecting an output of the first bias generator in the first oscillator block or an output of the first bias generator in the second oscillator block with parallel inputs of the first and second charge pumps; and an oscillator select circuit controlling the first, second and third switches to select the voltage oscillator in either of the first and second oscillator blocks.