Patent ID: 7839680
Filing Date: 2010-11-23
Classification: G11C,H01L

Abstract:
1. An EEPROM cell comprising: a memory transistor including a first gate structure, a first source region and a first drain region, the first gate structure including a tunnel oxide layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate pattern, sequentially stacked; a selection transistor, connected in series to the memory transistor, the selection transistor including a second gate structure, a second source region and a second drain region, the second gate structure including a gate oxide layer pattern and a gate electrode, sequentially stacked; a charge pumping circuit connected to the gate electrode of the second gate structure and applying a boosted voltage to the gate electrode of the second gate structure; and a resistance line connected between the charge pumping circuit and the control gate pattern, the resistance line having a resistor for decompressing the boosted voltage.