Patent ID: 8363480
Filing Date: 2013-01-29
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor storage device, comprising: a semiconductor substrate having a surface layer; a NAND cell unit including a first select gate transistor electrically connected to a bit line; a second select gate transistor electrically connected to a source line; a plurality of memory cell transistors series connected between the first select gate transistor and the second select gate transistor, the memory cell transistors being coupled to corresponding word lines; and a peripheral circuit that performs an erase verify operation of the NAND cell unit, after an erase voltage is applied on the NAND cell unit, by turning on the first and the second select gate transistors, applying a first predetermined voltage level on the source line, making a voltage level applied on one or more of the word lines coupled to the memory cell transistors situated relatively closer to the second select gate transistor larger than a voltage level applied on one or more of the word lines coupled to the memory cell transistors situated relatively closer to the first gate transistor, and verifying data erase of the memory cell transistors.