Patent ID: 6078087
Filing Date: 2000-06-20
Classification: H01L,Y10S

Abstract:
A MOSFET device comprising:a semiconductor SRAM device including NMOS FET devices including pass transistors and latch transistors with a dielectric layer formed over surfaces thereof,a thin film transistor gate electrode and an interconnection line formed on said dielectric layer, said gate electrode having a top surface,a gate oxide layer covering said gate electrode and said interconnection line and said dielectric layer,a polysilicon conductive layer formed over said gate oxide layer including therein a TFT channel region formed over said gate electrode and a source region and a drain region and an interconnect conductor formed therein, said polysilicon conductive layer having a top surface,a channel mask comprising a silicon oxide structure formed above said channel region and self-aligned with said channel region,said channel mask and said channel region being formed over at least a portion of said top surface of said gate electrode,said source region and said drain region being juxtaposed with said channel region proximate to the edges of said gate electrode, andan electrical contact formed extending through said gate oxide layer between said interconnection line and said polysilicon conductive layer.