Patent ID: 6249169
Filing Date: 2001-06-19
Classification: H03K

Abstract:
An output circuit comprising: a PMOS transistor and a NMOS transistor connected in series and a potential control circuit connected to the gate and source of the PMOS and the NMOS transistor, for receiving power from a high potential power supply and a low potential power supply, and controlling the voltage applied to the gate and the source of the PMOS transistor and the NMOS transistor in response to an input signal having one of a first level and a second level,wherein the potential control circuit applies a reference voltage to the gates of the PMOS transistor and the NMOS transistor, the reference voltage being between the high potential power supply level and the low potential power supply voltage level,wherein the potential control circuit applies the high potential power supply voltage to the source of the PMOS transistor in response to said input signal with the first level and applies a first voltage to the source of the NMOS transistor to make the NMOS transistor nonconductive, so that an output signal with the high potential power supply voltage is output from a node between the PMOS transistor and the NMOS transistor, andwherein the potential control circuit applies the low potential power supply voltage to the source of the NMOS transistor in response to said input signal having the second level and applies a second voltage to the source of the PMOS transistor to make the PMOS transistor nonconductive, so that an output signal having the low potential power supply voltage is output from the node between the PMOS transistor and the NMOS transistor, and wherein an amplitude of the output signal exceeds a breakdown voltage of the PMOS transistor and the NMOS transistor.