Patent ID: 8735796
Filing Date: 2014-05-27
Classification: H04N

Abstract:
1. A solid-state imaging device comprising: a pixel array in which unit pixels are arranged in a two-dimensional matrix, the pixel array having N columns where N is a natural number, and the unit pixels each including a photoelectric conversion element; readout signal lines each of which is provided for each of the pixel columns, for reading out a pixel signal from the unit pixels; and a ramp-type analog-to-digital (AD) converter which is provided adjacent to the pixel array and performs AD conversion on the pixel signal with ramp waves, the pixel signal being outputted via the readout signal lines, wherein the ramp-type AD converter includes: a digital-to-analog (DA) conversion circuit which generates the ramp waves; column comparison circuits each of which is provided for a corresponding one of the pixel columns, and compares the pixel signal with the ramp waves and detects a timing at which a voltage of the pixel signal and a voltage of the ramp waves match; column counter circuits each of which is provided for a corresponding one of the pixel columns and measures a period of time from a start of comparison in the column comparison circuit to the timing by being supplied with a clock signal; and M first inverters which are connected in series at substantially equal intervals such that all of the column counter circuits are along a direction in which all of the column counter circuits are one-dimensionally arranged, the M first inverters being included in an upper clock stage, and M being less than N, wherein the column counter circuit belongs to one of M column counter circuit groups which correspond one-to-one to the M first inverters, an odd-numbered group of the column counter circuits has second inverters each of which is for each of the column counter circuits, the second inverters being disposed in a lower clock stage and being between an output terminal of one of the first inverters corresponding to the column counter circuit group and one of the column counter circuits belonging to the column counter circuit group, an even-numbered group of the column counter circuits has buffers each of which is for each of the column counter circuits, the buffers being disposed in the lower clock stage and being between the output terminal of one of the first inverters corresponding to the column counter circuit group and one of the column counter circuits belonging to the column counter circuit group, and the clock signal is distributed to the column counter circuit in an order of the upper clock stage and the lower clock stage.