Patent ID: 6319772
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method for fabricating dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer formed over a first insulating layer on a semiconductor substrate comprising the steps of:forming said first insulating layer on said substrate;depositing a hard-mask layer on said first insulating layer;patterning said hard-mask layer and leaving portions over device areas, and using said hard mask for etching shallow trenches in said substate;depositing a second insulating layer to fill said shallow trenches and polishing hack to said hard-mask layer to form shallow trench isolation;selectively removing said hard-mask layer and forming recesses over and self-aligned to said device areas and exposing said first insulating layer in said recesses;etching openings in said first insulating layer over device areas to said substrate;growing selectively said epitaxial layer from said openings and extending laterally over said first insulating layer in said recesses;forming a gate oxide on said epitaxial layer;forming a doped polysilicon layer on said substrate;patterning said polysilicon layer to form FET gate electrodes over said openings, and implanting to form lightly doped source/drain areas in said epitaxial layer adjacent to said gate electrodes;forming insulating sidewall spacers on said gate electrodes, and implanting to form first and second source/drain contact areas adjacent to said sidewall spacers;forming capacitors electrically contacting said first source/drain contact areas and bit lines electrically contacting said second source/drain contact-areas to complete said DRAM cells.