Patent ID: 8595467
Filing Date: 2013-11-26
Classification: G06F

Abstract:
1. A method, in a data processing system, for performing a floating point collect and operate for a summation across a vector, the method comprising: routing, by a routing network in a first cycle, a first vector element from a first input vector register to a first input of a first floating point adder of a single instruction multiple data (SIMD) unit, a second vector element from the first input vector register to a second input of the first floating point adder, a third vector element from the first input vector register to a first input of a second floating point adder of the SIMD unit, and a fourth vector element from the first input vector register to a second input of the second floating point adder; routing, by the routing network in the first cycle, a first vector element from a second input vector register to a third floating point adder of the SIMD unit, a second vector element from the second input vector register to a second input of the third floating point adder, a third vector element from the second input vector register to a first input of a fourth floating point adder of the SIMD unit, and a fourth vector element from the second input vector register to a second input of the fourth floating point adder; performing, by the SIMD unit in the first cycle, a first addition operation and a second addition operation such that the first floating point adder adds the first vector element and the second vector element to form a first result and the second floating point adder adds the third vector element and the fourth vector element to form a second result; performing, by the SIMD unit in the first cycle, a fourth addition operation and a fifth addition operation such that the third floating point adder adds the first vector element and the second vector element from the second input vector register to form a third result and the fourth floating point adder adds the third vector element and the fourth vector element to form a fourth result; storing, by the SIMD unit in a first cycle, the first result into a first element of a result vector register and the second result into a second element of the result vector register; storing, by the SIMD unit in the first cycle, the third result into a third element of the result vector register and the fourth result into a fourth element of the result vector register; routing, by the routing network in a second cycle, the first element of the result vector register to the first input of a first selected floating point adder selected from the first floating point adder or the second floating point adder, and the second element of the result vector register to the second input of the first selected floating point adder; routing, by the routing network in the second cycle the third element of the result vector register to the first input of a second selected floating point adder selected from the third floating point adder or the fourth floating point adder, and the second element of the result vector register to the second input of the second selected floating point adder; performing, by the SIMD unit in the second cycle, a third addition operation such that the first selected floating point adder adds the first result and the second result to form a summation across the first input vector register; performing, by the SIMD unit in the second cycle, a sixth addition operation such that the second selected floating point adder adds the third result and the fourth result to form a summation across the second input vector register; storing, by the SIMD unit in the second cycle, the summation across the first input vector register into an element of the result vector register; and storing, by the SIMD unit in the second cycle, the summation across the second input vector register into an element of the result vector register.