Patent ID: 8691684
Filing Date: 2014-04-08
Classification: H01L

Abstract:
1. A method of making a power transistor layout, comprising: forming a first source pad; forming a first drain pad disposed substantially parallel to the first source pad to facilitate uniform power dissipation; forming a first source metal base coupled to the first source pad, wherein a first side of the first source metal base includes interleaving metal fingers; forming a first drain metal base coupled to the first drain pad, wherein a side of the first drain metal base adjacent to the first source metal base includes interleaving metal fingers protruding from the first drain metal base, the interleaving metal fingers of the first drain metal base being interleaved with the interleaving metal fingers of the first side of the first source metal base; forming a lower metal layer below the first drain metal base and the first source metal base without the use of a via or intermetal connector, the first drain metal base being positioned directly on a first portion of the lower metal layer and the first source metal base being positioned overlying a second portion of the lower metal layer, the second portion of the lower metal layer being a metal finger that partially extends beneath the first source metal base; forming a second drain pad coupled to the first drain metal base and spaced apart from the first drain pad; forming a second source pad disposed substantially parallel to the second drain pad, the first drain pad being closer to the first source pad than to the second source pad, the second drain pad being closer to the second source pad than to the first source pad; and a second source metal base coupled to the second source pad.