Patent ID: 7426679
Filing Date: 2008-09-16
Classification: H03M

Abstract:
1. A circuit for detecting and correcting errors in a bit stream, said circuit including at least two logical gates that determine if at least one of a plurality of conditions is present, each one of said plurality of conditions indicating at least one error in said bit stream and activation of at least one of said at least two logical gates changes a state of a specific bit in said bit stream to correct at least one error; wherein each one of said plurality of conditions is a specific bit pattern denoting a unique error pattern in said bit stream, each bit in said specific bit pattern resulting from bitwise operations between specific selected bits in said bit stream; wherein said plurality of conditions are divided into two groups, a first group which indicates a first type of error in said bit stream and a second group which indicates a second type of error in said bit stream; and wherein said at least two logical gates include a first logic gate associated with said first group and a second logic gate associated with said second group, such that said first logic gate is activated if a bit error pattern from said first group is detected and said second logic gate is activated if a bit pattern from said second group is detected.