Patent ID: 7724574
Filing Date: 2010-05-25
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory banks; an address input portion which receives an external address through address pins and generates a row address and a column address during a normal mode operation and a test mode operation, and which receives a first write data through the address pins and outputs the first write data during a test mode operation; an address decoder which accesses a selected memory bank of the plurality of memory banks during the normal mode operation and which accesses simultaneously at least one data write memory bank for a write operation and at least one data read memory bank for a read operation among the plurality of memory banks in response to the row address and the column address during the test mode operation; a data input portion which inputs second write data applied through data pins to the selected memory bank during the normal mode operation and which inputs the first write data outputted from the address input portion to the data write memory bank during the test mode operation; and a data output portion which outputs read data outputted from the selected memory bank to the data pins during the normal mode operation and which outputs read data from the data read memo bank to the data pins during the test mode operation.