Patent ID: 7843750
Filing Date: 2010-11-30
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a first sub memory cell array including a plurality of first memory cells connected between a plurality of first word lines and a plurality of bit lines, the plurality of first memory cells each including at least one transistor having a vertical channel structure; a second sub memory cell array including a plurality of second memory cells connected between a plurality of second word lines and a plurality of inverted bit lines, the plurality of second memory cells each including at least one transistor having a vertical channel structure; and a precharge portion disposed at both sides of each bit line and each inverted bit line and precharging each bit line and each inverted bit line to a precharge voltage level at both sides thereof in response to a precharge control signal, wherein each of the plurality of bit lines and the plurality of inverted bit lines is extended in a bit line direction, and the first memory cell array and the second memory cell array are arranged in the bit line direction, wherein the precharge portion includes