Patent ID: 6044124
Filing Date: 2000-03-28
Classification: H03C,H03L,H04N

Abstract:
A phase lock loop circuit for generating a clock signal, comprising:a frequency generator that generates a reference signal having a plurality of pulses with a pulse occurring at a first frequency with a first period being defined as the time between a start of a first pulse and a start of a next following pulse;a phase detector that detects phase differences between the reference signal and a feedback signal;a voltage control oscillator operatively connected to the phase detector and in response to an output from the phase detector provides the clock signal,a programmable divider operatively connected to receive the clock signal, the programmable divider divides the clock signal by N+m to provide the feedback signal where N is an integer and m is a variable having a range of selectable values and where the division occurs within the first period of time; anderror detection means for detecting speed errors in the clock signal and to select values for m based upon the detected errors,wherein the error detection means includes:a memory connected to receive data at a first rate and to transfer the data in response to the clock signal;overflow detect means for detecting an increase in the rate of loading data into the memory and to generate an overflow detect signal in response to the detected increase in rate of loading data into the memory;a first accumulator having a first input, a second input and a first output with the first input being connected to receive the overflow detect signal and the second input being connected to receive the first output and wherein the accumulator accumulates the combination of the overflow detect signal with the first output and provides an accumulated signal; anda decoder operatively connected to receive the accumulated signal and to decode each value of m from the accumulated signal.