Patent ID: 6313674
Filing Date: 2001-11-06
Classification: G06F,G11C,H03K,H03L

Abstract:
A synchronizing circuit comprising:an output circuit for outputting high level data and low level data, said output circuit having a first circuit for outputting said high level data in response to a first start signal having a period equal to a period of a clock signal and a second circuit for outputting said low level data in response to a second start signal having a period equal to the period of said clock signal;a first signal generation circuit supplied with said clock signal, said first signal generation circuit advancing a phase of said clock signal substantially by a total of a first delay time caused when said first circuit outputs high level data and a second delay time caused when said second circuit outputs low level data;a second signal generation circuit having a delay time substantially equal to said second delay time of said second circuit, said second signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said first start signal for starting said first circuit of said output circuit by using the delayed signal; anda third signal generation circuit having a delay time substantially equal to said first delay time of said first circuit, said third signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said second start signal for starting said second circuit of said output circuit by using the delayed signal.