Patent ID: 6771546
Filing Date: 2004-08-03
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory cell array which includes a plurality of memory cells arranged in a matrix form, each of the memory cells including a transistor which has a source, a drain and a channel body between the source and the drain, each of the memory cells storing data depending on whether or not majority carriers are accumulated in the channel body; a plurality of word lines, each of which is connected to gate electrodes of the memory cells arranged in a first direction; a plurality of bit lines, each of which is connected to the memory cells arranged in a second direction which intersects the first direction and configured to read data stored in the memory cells; a decoding circuit which is supplied with an address signal and a first control signal, the decoding circuit driving a selected word line which is the word line specified by the address signal or an adjacent word line which is the word line adjacent to the selected word line on the basis of the first control signal; and a sense unit which is connected to a bit line and reads data stored in the memory cell which is connected to the word line driven by the decoding circuit.