Patent ID: 6496042
Filing Date: 2002-12-17
Classification: H03D

Abstract:
A phase comparator, comprising:a flip-flop circuit which receives input data and a clock signal as input, and stores the input data in response to the clock signal; a delay circuit which receives the input data and delays said input data by a predetermined angle of 0Â° through 180Â°, a data input of said flip-flop circuit being connected to a data input of said delay circuit; a first logic gate which receives the input data and an output signal of said flip-flop circuit and which outputs a first output signal by taking an exclusive OR or exclusive NOR of the input data and the flip-flop output signal; a second logic gate which inputs the input data and the output signal of said delay circuit and which outputs a second output signal by taking an exclusive OR or exclusive NOR of the input data and the delay circuit output signal; and a converter comprising (a) a third logic gate which inputs the first output signal and the second output signal, and takes an exclusive OR or exclusive NOR of the two output signals; (b) a first output circuit which inputs the first output signal and an output signal of said third logic gate, and detects whether or not said two signals match, so as to output a phase-delay signal in the event that said two signals match; and (c) a second output circuit which outputs the second output signal and an output signal of sail third logic gate, and detects whether or not said two signals match, so as to output a phase-forward signal in the event that said two signals match.