Patent ID: 7286401
Filing Date: 2007-10-23
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device that includes a nonvolatile semiconductor memory array comprising nonvolatile memory cells, wherein said memory array further includes: refreshing blocks, each including a plurality of erasure blocks for erasing a respective plurality of said nonvolatile memory cells collectively; and counter areas, wherein the number of counter areas equals the number of refreshing blocks, and wherein each said counter area stores a number of programming/erasing operations performed in a corresponding one of said refreshing blocks; and wherein data in each refreshing block is stored in a buffer memory each time the number of programming/erasing operations stored in the corresponding counter area reaches a predetermined value, then the data in said refreshing block is erased completely and the data stored in the buffer memory is programmed back to each said refreshing block; wherein if a plurality of said counter areas reach a predetermined count value, data in the corresponding refreshing blocks are then stored sequentially in a temporary storing memory, then the data in each of the corresponding refreshing blocks are erased, and said temporarily stored data are programmed back to the corresponding refreshing blocks.