Patent ID: 6697297
Filing Date: 2004-02-24
Classification: G11C

Abstract:
An electronic system comprising:a processor; at least one of an input device, an output device and a storage device associated with the processor; a memory device coupled to the processor for storing data and instructions for use by the processor, the memory device comprising a write/valid indicator circuit comprising: a clock input to receive a clock signal; at least one command input to receive at least one command signal; at least one signal delay circuit coupled to receive at least one of the clock signal and the at least one command signal, wherein the at least one signal delay circuit comprises: a first signal delay circuit coupled to receive the clock signal; and a second signal delay circuit coupled to receive the at least one command signal; and at least one priority circuit coupled to the at least one signal delay circuit and coupled to receive at least one of the clock signal and the at least one command signal, the at least one priority circuit comprising an output and configured to produce a valid latency setting signal on the output if the output from the at least one signal delay circuit, the at least one command signal and the clock signal each transition in a predetermined order, the at least one priority circuit further comprising at least one register.