Patent ID: 7245239
Filing Date: 2007-07-17
Classification: G11C,H03M

Abstract:
1. A synchronous parallel/serial converter that receives a parallel n-bit input signal, comprising: a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with one of the front and rear flank of a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal in synchronism with the respective other of the front and rear flank of the clock signal and provides a serial output as a second one-bit signal sequence, wherein the first and second load signals have a fixed phase difference between them, and wherein a phase angle of the first load signal and of the second load signal varies relative to the front and/or rear flank of the clock signal; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.