Patent ID: 7750399
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A MOS transistor comprising: an isolation region formed in a semiconductor substrate to define an active region; a source region and a drain region disposed in the active region and spaced apart from each other; a gate trench structure disposed in the active region between the source and drain regions, wherein the gate trench structure includes an upper gate trench crossing the active region and a lower gate trench disposed under the upper gate trench and having a width greater than the upper gate trench; a gate electrode disposed in the gate trench structure; a gate dielectric layer interposed between the gate trench structure and the gate electrode; and a semiconductor region disposed between an inner wall of the lower gate trench structure and the gate dielectric layer and formed of a different material than the active region, wherein the semiconductor region does not extend to a sidewall portion of the upper gate trench.