Patent ID: 7382049
Filing Date: 2008-06-03
Classification: H01L,H05K,Y02P

Abstract:
1. A chip package, comprising: a chip having an active surface, at least a chip pad disposed on the active surface, and a passivation layer disposed on the active surface and exposing the chip pad; a carrier having a carrier surface, at least a carrier pad disposed on the carrier surface, and a solder mask layer disposed on the carrier surface and exposing the carrier pad; and at least a bump connecting structure, wherein the chip and the carrier are electrically connected through the bump connecting structure, comprising: a first metal bump disposed on the chip pad and having a first height relative to a surface of the passivation layer; a second metal bump disposed on the carrier pad and having a second height relative to a surface of the solder mask layer, wherein the first metal bump has a first pit facing the second metal bump and the second metal bump has a second pit facing the first metal bump; and a middle metal part disposed between the first metal bump and the second metal bump, wherein the melting point of the middle metal part is lower than that of the first metal bump and the second metal bump.