Patent ID: 7710377
Filing Date: 2010-05-04
Classification: G09G

Abstract:
1. A liquid crystal display (LCD) panel having gate drivers, the LCD panel comprising: a plurality of pixels formed at intersections of a plurality of gate lines and a plurality of data lines, respectively; and a gate line shift circuit setting a gate line scanning order such that the gate lines are sequentially scanned in units of n gate lines with k−1 gate lines between each pair of adjacent gate lines in each unit according to an interleaving method, in response to a gate line-on signal received from a timing control unit outside the LCD panel, wherein the LCD panel reproduces source data output from a source driver outside the LCD panel in the gate line scanning order set by the gate line shift circuit; wherein the LCD panel inverts the polarity of a gate electrode each time the LCD panel finishes scanning one unit of n gate lines; wherein n=3 and k=2, the gate line shift circuit repeats sequentially scanning three 2k-th (k denotes a constant) gate lines after sequentially scanning three (2k+1)-th gate lines, and the LCD panel inverts the polarity of the gate electrode whenever three gate lines are scanned; wherein the gate line shift circuit comprises a plurality of gate line switch blocks, each of the gate line switch blocks comprises six switches operating in synchronization with a clock signal and an inverted clock signal, each of the six switches is connected to a corresponding gate line, and a first switch in a first switch block is controlled by the gate line-on signal input from the timing control unit and a first switch in a next switch block is controlled by an output signal of a last switch in a previous switch block; and wherein each of the switch blocks comprises: a first switch corresponding to a first gate line; a second switch corresponding to a second gate line; a third switch corresponding to a third gate line; a fourth switch corresponding to a fourth gate line; a fifth switch corresponding to a fifth gate line; and a sixth switch corresponding to a sixth gate line, wherein the first switch is turned on in response to the clock signal and the gate line-on signal or the output signal of the sixth switch in the previous block and turned off in response to an output signal of the third switch, the second switch is turned on in response to the inverted clock signal and an output signal of the fifth switch and turned off in response to an output signal of the fourth switch, the third switch is turned on in response to the inverted clock signal and an output signal of the first switch and turned off in response to the output signal of the fifth switch, the fourth switch is turned on in response to the clock signal and an output signal of the second switch and turned off in response to an output signal of the sixth switch, the fifth switch is turned on in response to the clock signal and the output signal of the third switch and turned off in response to the output signal of the second switch, and the sixth switch is turned on in response to the inverted clock signal and the output signal of the fourth switch and turned off in response to an output signal of the first switch in the next switch block.