Patent ID: 6778170
Filing Date: 2004-08-17
Classification: G09G

Abstract:
A display unit receiving a display signal, said display signal containing each of display data, synchronization signals and display enable (DE) signal, said display data encoding a plurality of image frames, each of said plurality of image frames being represented by a plurality of active pixel data elements, said synchronization signals indicating the transitions across horizontal lines and image frames in said display data, said DE signal indicating a time duration in which said plurality of active pixel data elements are present in said display data, said display unit comprising:a receiver receiving said display signal and generating a plurality of pixel data elements from said display data, wherein said plurality of pixel data elements contain said plurality of active pixel data elements; a regeneration circuit receiving said DE signal and generating alternative synchronization signals based on said DE signal, wherein said alternative synchronization signals also indicating the transitions across horizontal lines and image frames; a source timing measurement circuit receiving said alternative synchronization signals and generating a HDISP signal and a VDISP signal based on said alternative synchronization signals, wherein said HDISP signal indicates a time duration in which active pixel data elements are received and wherein said VDISP signal indicates a time duration in which an active horizontal line is received; a scaler coupled to said source timing measurement circuit, said scaler receiving said plurality of pixel data elements and said HDISP signal and said VDISP signal, said scaler identifying said plurality of active pixel data elements in said plurality of pixel data elements based on said HDISP signal and said VDISP signal; a display screen; a panel controller coupled to said scaler and said display screen, said panel controller causing said plurality of image frames to be displayed on said display screen according to said plurality of active pixel data elements identified by said scaler; and a multiplexor located between said regeneration circuit and said source timing measurement circuit, said multiplexor receiving said synchronization signals received in said display signal and said alternative synchronization signals, said multiplexor providing either said synchronization signals or said alternative synchronization signals to said source timing measurement circuit, wherein said source timing measurement circuit generates said HDISP and VDISP signals based on the signals provided by said multiplexor, whereby said HDISP and VDISP signals to be generated based on either said synchronization signals or said alternative synchronization signals.