Patent ID: 6326269
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A method of fabricating a mask read only memory (ROM), comprising:forming a gate oxide layer on a substrate;forming a polysilicon layer and a silicon nitride layer in sequence on the substrate;defining the silicon nitride layer and the polysilicon layer;performing a doping process to form a buried bit line in the substrate by using the silicon nitride layer and the polysilicon layer as a mask;defining the silicon nitride layer and the polysilicon layer to form a plurality of stacked gate layers;forming a plurality of gate spacers around and on the sidewall of the stacked gate layers;forming a silicon oxide layer over the silicon nitride layer, the polysilicon layer and the substrate;removing portion of the silicon oxide layer until exposing the top of the silicon nitride layer;forming a first patterned photoresist layer on the substrate to cover parts of the silicon nitride layer, wherein the first patterned photoresist layer includes a pattern of first ROM code programmed with removing the exposed silicon nitride layer;removing the exposed silicon nitride layer by using the first patterned photoresist layer as a mask;removing the first patterned photoresist layer;forming a second patterned photoresist layer;performing an ion implantation process to form a doped region in the substrate under the exposed polysilicon layer by using the second patterned photoresist layer as a mask;removing the second patterned photoresist layer; andforming a conductive layer on the substrate to electrically connect to the exposed polysilicon layer.