Patent ID: 6272035
Filing Date: 2001-08-07
Classification: G11C

Abstract:
An integrated memory, comprising:a bidirectional data connection;two cell groups located adjacent to one another and having memory cells;a first local data line and a second local data line for a respective bidirectional data transfer from and to said memory cells of a respective one of said two cell groups;a first global data line and a second global data line for a respective bidirectional data transfer between said data connection and said first and second local data lines;an output circuit for performing a read access to said two cell groups, said output circuit being located adjacent to said data connection;said first and second global data lines being connected to said data connection via said output circuit, said output circuit having two operating states for feeding two items of data respectively provided on said first and second global data lines to said data connection in a respective different order;an input circuit for performing a write access to said two cell groups, said input circuit being located adjacent to said two cell groups;a receiving unit located at said data connection;said data connection being connected to said first and second global data lines via said receiving unit, said data connection, in the event of the write access to said two cell groups, being fed a first datum and subsequently a second datum, said receiving unit, in the event of the write access, feeding the first datum to said first global data line and feeding the second datum to said second global data line; andsaid first and second global data lines being connected to said first and second local data lines via said input circuit, said input circuit having two operating states for feeding the first datum and the second datum in a respectively different assignment to said first and second local data lines.