Patent ID: 6388493
Filing Date: 2002-05-14
Classification: G06F,H03K

Abstract:
A clock control circuit of a semiconductor integrated circuit device to which an external clock is input for generating an internal clock, comprising:(a) a synchronous delay circuit which includes: (b) a first delay circuit chain through which a pulse or pulse edge is caused to travel for a fixed period of time; (c) a second delay circuit chain capable of passing a pulse or pulse edge along a length thereof equal or proportional to the length along which the pulse or pulse edge traveled through said first delay circuit chain; (d) a clock driver outputting the internal clock from an output of said second delay circuit chain; and (e) a timing averaging circuit, to which are input a clock signal from an input buffer and a signal obtained by passing an internal clock signal, which is output via said clock driver, through an input buffer dummy circuit having a delay time equivalent to that of said input buffer, to generate and output a signal having a time difference obtained by internally dividing, at a prescribed ratio, a time difference between the two signals; (f) wherein said first delay circuit chain is supplied with the output of said timing averaging circuit via a dummy delay circuit.