Patent ID: 6681288
Filing Date: 2004-01-20
Classification: G11C

Abstract:
method of operation of a semiconductor memory device, wherein the memory device receives an external clock signal and includes an array of memory cells, wherein the method comprises:receiving a plurality of control signals which specify that the memory device perform a memory write operation; receiving a first mask bit during a first half of a first clock cycle of an external clock signal, wherein the first mask bit indicates whether to write a first data value to the array; receiving a second mask bit during a second half of the first clock cycle of the external clock signal, wherein the second mask bit indicates whether to write a second data value to the array; receiving the first and second data values during a second clock cycle of the external clock signal, wherein the second clock cycle is temporally offset with respect to the first clock cycle, and wherein: the first data value is received during a first half of the second clock cycle of the external clock signal; and the second data value is received during a second half of the second clock cycle of the external clock signal; writing the first data value to the array during the memory write operation if the first mask bit indicates that the first data value is to be written to the array; and writing the second data value to the array during the memory write operation if the second mask bit indicates that the second data is to be written to the array.