Patent ID: 7009906
Filing Date: 2006-03-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising a plurality of memory banks each having rows that can be activated independently of another memory bank, wherein a first memory bank of said plurality of memory banks includes first to N-th sub-memory blocks, where N is a natural number greater than two, an M-th sub-memory block, where M is a natural number equal to or greater than two and equal to or smaller than N−1, of said first to N-th sub-memory blocks includes a first memory cell array including a plurality of memory cells arranged in rows and columns and a first local control circuit, in a refresh mode, starting an operation of successively selecting rows of said first memory cell array in response to a first refresh end signal received from an (M−1)th sub-memory block and instructing a refresh start to an (M+1)th sub-memory block when said operation of successively selecting rows ends, and said first memory bank further includes a plurality of sense amplifier bands each shared by adjacent two of said first to N-th sub-memory blocks.