Patent ID: 7330911
Filing Date: 2008-02-12
Classification: G06F

Abstract:
1. A method of accessing a memory through a circuit, comprising the steps of: (A) buffering both a first read data and a second read data received within a plurality of first transfers from said memory to a read input register of said circuit in response to a first read command that has a first read address of said first read data; (B) loading said first read data, from said read input register to a read output register of said circuit; (C) transmitting said first read data in a second transfer from said read output register to outside of said circuit; (D) buffering a first write data received in a third transfer to a write input register of said circuit; (E) loading said first write data from said write input register to a write output register of said circuit; (F) transmitting said first write data within a plurality of fourth transfers from said write output register to said memory; and (G) loading said second read data from said read input register to said read output register after said second transfer of said first read data from said read output register in response to a second read command that has a second read address matching a first read address tag of said first read data.