Patent ID: 7801205
Filing Date: 2010-09-21
Classification: G01R

Abstract:
1. A jitter injection circuit that injects jitter having a predetermined amplitude to a transmission signal outputted from a transmission circuit, and inputs the resulting transmission signal to a reception circuit, the jitter injection circuit comprising: a retiming section that receives the transmission signal from the transmission circuit, and performs retiming on an edge timing of the received transmission signal in accordance with a given clock signal; a jitter injection section that injects the jitter having the predetermined amplitude to the transmission signal outputted from the retiming section, and inputs the resulting transmission signal to the reception circuit; a PLL circuit that generates the clock signal based on a given reference signal; and a phase adjusting section that adjusts a phase of the clock signal outputted from the PLL circuit, wherein the retiming section performs retiming on the transmission signal, by receiving the clock signal whose jitter amplitude is smaller than a jitter amplitude of the transmission signal, sampling a logical value of the transmission signal using the clock signal, and outputting the resulting logical value, and the jitter injection section receives the transmission signal outputted from the retiming section, injects the jitter having the predetermined amplitude to the received transmission signal, and inputs the resulting transmission signal to the reception circuit.