Patent ID: 6765280
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A semiconductor isolation structure comprising:a substrate, the substrate comprising a surface; a first device and a second device formed within the substrate; an isolation region formed within the substrate between the first device and the second device, the isolation region comprising: a single deep region which extends into the substrate, the deep region comprising a deep region cross-sectional area, the deep region abutting only the substrate and a single shallow region; the single shallow region extending to the surface of the substrate, the shallow region comprising: a protective outer wall adjacent to the substrate and extending to the surface of the substrate; an inner sealing wall located exclusively within the shallow region and adjacent to the protective outer wall, extending to th surface of the substrate; and the shallow region having a shallow region cross-sectional area; wherein the deep region cross-sectional area is greater than the shallow region cross-sectional area, the deep region abutting only a single shallow region.