Patent ID: 6377065
Filing Date: 2002-04-23
Classification: G01R

Abstract:
A semiconductor test system for testing a semiconductor device, comprising:an event memory for storing event data regarding events in intended signals to be generated for testing a semiconductor device under test (DUT); an event generator for producing the intended signals which are test patterns, strobe signals and expected patterns based on the event data from the event memory; a pin electronics provided between the event generator and the DUT for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals from the event generator; a pattern comparator for comparing sampled output data from the pin electronics with the expected patterns and producing a failure signal when there is a mismatch therebetween; and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing the number with an expected number of edges.