Patent ID: 7100063
Filing Date: 2006-08-29
Classification: G06F,Y02D

Abstract:
1. A low power operation control unit mounted in a microprocessor having an instruction condition executing function using a condition flag, the control unit controlling a low power operation of the microprocessor, the control unit comprising a first instruction set including instruction execution control function information in a specific bit field of an instruction code inputted to a microprocessor, the information being used for selecting a flag for an instruction execution control function, and one or more second instruction sets including control specification information for low power control in the specific bit field, wherein the control unit comprises: an operation mode switching circuit for switching the instruction sets to execute the first instruction set during a normal operation and execute the second instruction set during a low power operation; a predicate decision circuit for reading a flag corresponding to the instruction execution control function information in a first instruction set mode to discriminate an instruction execution control operation; a control specification information extraction circuit for extracting control specification information of a control circuit for reading the control specification information in a second instruction set mode and performing a low power operation; and a controlling unit for performing a low power operation of each control circuit by using the control specification information, wherein the instruction execution control function information and the control specification information are provided beforehand in each program for executing an instruction, and a low power operation of each control circuit is performed for each instruction according to the control specification information, thereby controlling a low power operation of the microprocessor for each instruction.