Patent ID: 6226695
Filing Date: 2001-05-01
Classification: G06F

Abstract:
An information handling system, comprising:a processor, including a cache;a memory system;a memory controller for controlling said memory system, and including an auxiliary function processor;a processor bus, connecting said processor to said memory controller;a memory bus, connecting said memory controller to said memory system;means within said processor for building one or more command blocks, wherein each command block contains one or more commands to be executed by the auxiliary function processor;means for storing the command blocks in the cache;means for writing a starting address of each command block to an address FIFO associated with the auxiliary function processor;means for reading the starting address of each command block by the auxiliary processor;means for successively accessing each command block using its starting address, and then processing the commands in each command block by the auxiliary function processor;means for recognizing a command block read by said memory controller;means for issuing a coherent read for a select queued command block with intervention enabled;means for flushing, by said processor, a copy of the select queued command block to said memory system if a copy of the select queued command block is in the cache; andmeans for intercepting, by said memory controller, the flushed copy of the select queued command block from cache to the memory system and then canceling a read to memory.