Patent ID: 6891494
Filing Date: 2005-05-10
Classification: H03M

Abstract:
1. A layout method of a comparator array of a flash type analog to digital converting circuit, the flash type analog to digital converting circuit including: (i) a reference voltage for generating (2 n −1 ) voltages and being arranged to be folded; (ii) a comparator array including (2 n −1) comparators for comparing voltage differences between the respective (2 n −b 1 ) voltages and an analog input signal to generate a digital thermometer code having (2 n −1) bits; and (iii) an encoder for encoding the digital thermometer code having (2 n −1) bits to generate an n-bit of digital signal, the layout method comprising: arranging the comparators such that the comparators of (2 arranging the comparators such that the neighboring comparators adjacent to the respective (2