Patent ID: 6791133
Filing Date: 2004-09-14
Classification: H01L

Abstract:
An interposer located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, the interposer comprising:an oxide layer formed on a substantially planar surface of a silicon substrate; a thin film dielectric capacitor, having a first electrode, a dielectric, and a second electrode, formed on the oxide layer; a plurality of metallized vias including a first metallized via in electrical contact with the first electrode and a second metallized via in electrical contact with the second electrode, the plurality of metallized vias extending from the first electrode and the second electrode to a surface of the interposer, the surface being adjacent to the integrated circuit; and a plurality of vias including a first via that conducts power between the ceramic substrate and the integrated circuit, a second via that conducts ground between the ceramic substrate and the integrated circuit, and a third via that conducts signals between the ceramic substrate and the integrated circuit.