Patent ID: 7253678
Filing Date: 2007-08-07
Classification: G05F,H03F,H03K

Abstract:
1. A bias network, comprising: a first transistor; a second transistor with its gate coupled to its drain and the gate of said first transistor, and its source coupled to the drain of said first transistor; a voltage-drop generator with first and second ports with said first port coupled to the drain of said first transistor; a third transistor with its source coupled to the second port of said voltage-drop generator; and a first gate-bias regulator coupled to the gate of said third transistor; and further including: a fourth transistor whose source is coupled to the source of said first transistor; a fifth transistor with its gate coupled to the gate of said third transistor and its source coupled to the drain of said fourth transistor; and a current source arranged to pass a current through said fifth transistor; and a conducting path coupling the drain of said fifth transistor to the gate of said fourth transistor.