Patent ID: 6690750
Filing Date: 2004-02-10
Classification: H03M

Abstract:
A decoder system, comprising:a State Metric Update unit including a state metric memory; a cascaded Add/Compare/Select (ACS) unit, comprising: a plurality of serially coupled ACS stages arranged in a sequence, a first ACS stage having an input coupled to the state metric memory and a last ACS stage having an output coupled to the state metric memory, each ACS stage for computing an accumulated state metric from a prior state metric and a branch metric, and for identifying a path decision, each ACS stage forwarding the accumulated state metric and an appended indicator of the path decision along the sequence, so that the path decisions are accumulated along the sequence of ACS stages; and routing circuitry disposed between ACS stages in the sequence, for routing the accumulated state metric and appended indicators from one ACS stage to a next ACS stage in the sequence; a Traceback unit, comprising: a traceback memory for storing the accumulated path decisions from the last ACS stage in the sequence; and traceback logic circuitry for generating decoded output bits from the accumulated path decisions.