Patent ID: 7790506
Filing Date: 2010-09-07
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device, in which a wafer is provided having a surface, on which a plurality of integrated circuits are formed and electrically connected to a plurality of rewires via a plurality of pad electrodes, and in which a plurality of electrode terminals are formed on the plurality of rewires, and then the wafer is divided into a plurality of individual pieces, said manufacturing method comprising the steps of: forming a first resin layer for sealing a backside of the wafer before formation of the rewires and the electrode terminals or after the formation of the rewires and the electrode terminals; performing primary dicing on the surface of the wafer toward the backside of the wafer after the formation of the rewires and the electrode terminals and after formation of the first resin layer so that the first resin layer is partially cut out, thus forming a plurality of dicing channels partitioning the plurality of integrated circuits; forming a second resin layer for continuously sealing the plurality of dicing channels and the surface of the wafer after formation of the plurality of dicing channels; dicing the backside of the wafer so as to form a plurality of V-shaped channels in the first resin layer after the formation of the first resin layer and after formation of the second resin layer in such a way that the plurality of V-shaped channels overlap with the plurality of dicing channels in a thickness direction of the wafer; and performing secondary dicing on the surface of the wafer such that the second resin layer sealing side faces of the wafer subjected to partitioning due to the primary dicing still remains and such that the plurality of V-shaped channels partially remain so as to form a plurality of slopes, which are inclined from a backside of the first resin layer sealing the backside of the wafer, thus dividing the wafer into the plurality of individual pieces.