Patent ID: 7779288
Filing Date: 2010-08-17
Classification: G03G,H02P

Abstract:
1. A timer circuit comprising: a storage unit configured to store a series of first data content relating to a time into a specified address area; a target value generation unit configured to read the first data content from a read address of the storage unit and to generate, as a target value, third data content in which second data content is added to the first data content; a counter to perform counting and to output a count-up signal when the counting is performed up to the target value; and a control unit configured to sequentially designate a next read address of the storage unit at each count-up and to cause a series of operations of the target value generation unit and the counter to be executed, wherein the target value generation unit includes: a read unit configured to designate the read address of the storage unit and to read the first data content; a comparison unit configured to compare magnitudes between the first data content read at this time and the first data content read at the last time; and an operation unit configured to increase or decrease the second data content by a specified value when a relation of the magnitudes is reversed differently from a specified increase or decrease tendency.