Patent ID: 7948013
Filing Date: 2011-05-24
Classification: G06F,H01L

Abstract:
1. A layout of an integrated circuit device, comprising: a gate electrode level layout portion including five or more adjacently positioned linear shaped layout features each formed to have a respective length and a respective width when viewed from above, wherein a size of the length of a given linear shaped layout feature is greater than or equal to a size of the width of the given linear shaped layout feature, wherein the five or more adjacently positioned linear shaped layout features are formed to have their lengths extend in a first direction in a parallel manner, wherein the five or more adjacently positioned linear shaped layout features are formed to have a substantially equal centerline-to-centerline spacing between each pair of adjacently positioned linear shaped layout features as measured perpendicular to the first direction, and wherein the region of the gate electrode level includes six linear shaped layout features each formed to have their lengths extend in the first direction in the parallel manner, wherein the six linear shaped layout features include,