Patent ID: 6521941
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A non-volatile memory device comprising:first and second active regions formed in a semiconductor substrate and defined by an isolation region; a control gate electrode disposed across the first active region; a floating gate electrode intervening between the control gate electrode and the first active region; a first inter-gate insulating layer intervening between the control gate electrode and the floating gate electrode; a gate electrode being across the second active region; a dummy gate electrode on the gate electrode; a second inter-gate insulating layer intervening between the gate electrode and the dummy gate electrode, wherein the second inter-gate insulating layer is thicker than the first inter-gate insulating layer; an inter-layer insulating layer formed on the gate electrode; and a contact hole formed through the inter-layer insulating layer, wherein the contact hole exposes a portion of the gate electrode.