Patent ID: 6475841
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A method for forming a transistor, comprising the steps of:providing a substrate having at least a semiconductor portion, the semiconductor portion having a top surface; forming an insulating layer on the top surface; forming a polysilicon layer overlying the insulating layer, wherein the polysilicon layer contains an impurity which has an effect on an etch rate of polysilicon, wherein the impurity has a concentration profile which varies with distance from the top surface; providing a mask over the polysilicon layer to define a gate under the mask, wherein the gate has an upper region near the mask and a lower region near the top surface; selecting an etching material which has an etch rate of polysilicon which is affected by the impurity; etching the polysilicon layer around the gate with the etching material so that after etching the polysilicon layer, the upper region of the gate is wider than the lower region of the gate; performing a halo implant at a tilt angle using the lower region of the gate to mask the halo implant; performing a relatively light dose implant through the top surface to form a light implant region aligned with an edge of the upper region of the gate; forming a sidewall spacer adjacent to the gate portion; performing a relatively heavy dose implant through the top surface using the sidewall spacer to mask the relatively heavy dose implant; and heating the substrate so that the light implant region diffuses to have a relatively small overlap with the lower region of the gate.