Patent ID: 6239452
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A MOS device having a self-aligned silicide gate structure for eliminating poly-Si depletion and for suppressing the penetration of boron ions comprising:a semiconductor substrate;a gate oxide formed on a surface of said semiconductor substrate;a polycrystalline silicon gate electrode formed on a surface of said gate oxide;shallow source/drain extension regions formed at a self-aligned position on opposite sides of said gate electrode and in said semiconductor substrate;sidewall spacers formed on sidewalls of said gate electrode;highly-doped source/drain regions formed at a self-alianed position on opposite sides of said sidewall spacers and in said semiconductor substrate;a first Nickel disilicide layer formed between said gate oxide and said polycrystalline silicon gate oxide for suppressing the penetration effects of the boron ions into said silicon substrate; andsecond Nickel monosilicide layers having relatively low sheet resistance and low contact resistance and being formed over said highly-doped source/drain regions.