Patent ID: 7435649
Filing Date: 2008-10-14
Classification: H01L

Abstract:
1. A floating gate non-volatile memory comprising: a semiconductor substrate within which active regions and isolation dielectrics are alternately arranged in a first direction; a word line extending in said first direction to intersect with said active regions and said isolation dielectrics, a plurality of floating gates disposed between said respective active regions and said word line; and a plurality of contacts connected with diffusion layers formed within said active regions respectively, said plurality of contacts being arranged in said first direction, wherein said plurality of contacts include drain contacts and a source contact, and said diffusion layers includes drain diffusion layers connected with said drain contacts and a source diffusion layer connected with said source contact, wherein said semiconductor substrate includes: a conductive source region extending in said first direction, said source region being positioned opposing said plurality of contacts across said word line; and an embedded diffusion layer extending from said source region in a second direction perpendicular to said first direction, connected with said source diffusion layer.