Patent ID: 7326983
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a top surface; a first region of said substrate having a first N-well or P-well extending into said semiconductor substrate from said top surface of said substrate and bounded in a direction perpendicular to said top surface by a first trench isolation, said first trench isolation consisting of a first vertical portion extending perpendicular to said top surface of said substrate into said substrate; a source and a drain of a first NFET or PFET formed respectively in said first P-well or N-well of said first region and abutting said vertical portion of said first trench isolation; a second region of said substrate having a second N-well or P-well extending into said semiconductor substrate from said top surface and bounded in a direction perpendicular to said top surface by a second trench isolation, said second trench isolation having a second vertical portion extending perpendicular to said top surface into said substrate and a lateral portion extending from said second vertical portion in a direction parallel to said top surface of said substrate; a source and a drain of a second NFET or PFET formed respectively in said second P-well or N-well of said second region, a source and a drain of a second NFET or PFET abutting both said second vertical portion and said lateral portion of said second trench isolation, said source and said drain of said second NFET or PFET intervening between said lateral portion and said top surface of said substrate; and a buried oxide layer in said substrate below said first and second trench isolations.