Patent ID: 7784006
Filing Date: 2010-08-24
Classification: G06F

Abstract:
1. A method of implementing a circuit design for an integrated circuit, comprising: identifying matching elements between a modified version of the circuit design and an implemented version of the circuit design, the modified version of the circuit design including at least one of an element or a connection that is different from the implemented version of the circuit design; identifying a placement in the implemented version of the circuit design for each of the matching elements; applying a weak lock to each of the matching elements with respect to the identified placement, wherein the weak locks establish recommended placements for the matching elements based on the identified placement; generating an initial placement of the modified version of the circuit design using the recommended placements; wherein, while generating the initial placement, placement of the matching elements having the weak lock is subject to change; identifying timing-critical elements in the initial placement; transforming the weak lock to a strong lock on the initial placement of each of the matching elements that is not identified as timing-critical; and generating, using a computer, an optimized placement of the modified version of the circuit design from the initial placement having the weak and strong locks; wherein the generating of the optimized placement includes, in response to the optimized placement not meeting timing constraints and having elements with strong locks on the initial placement, removing the strong lock on the initial placement of at least one of the elements, and generating a new optimized placement while permitting the at least one element to be moved from the initial placement to meet timing constraints.