Patent ID: 6337501
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A semiconductor device circuit comprising:a substrate; an element region formed in the substrate, and isolated and insulated from other element regions formed in the substrate; a semiconductor layer formed in the element region and having a first conductivity type; a bipolar transistor formed in the semiconductor layer comprising: a base region formed in the semiconductor layer and having a second conductivity type; an emitter region formed in the base region and having the first conductivity type; and a collector region formed in the semiconductor layer and having the first conductivity type; an insulated gate transistor formed in the semiconductor layer in which the bipolar transistor is formed and using the base region as one of a source and a drain thereof, the insulated gate transistor comprising: a source-drain region formed in the semiconductor layer and having the second conductivity type, for use as another of the source and the drain of the insulated gate transistor; and a gate formed on the surface of the semiconductor layer between the base region and the source-drain region with a gate oxide film interposed therebetween; an excess carrier removing region, formed in the semiconductor layer and having the second conductivity type for defining a parasitic transistor with the semiconductor layer and the base region, the parasitic transistor for removing excess carriers in the base region; and a circuit portion connected to the bipolar transistor and the insulated gate transistor for inputting an abnormality signal to the gate of the insulated gate transistor so that the bipolar transistor is turned off by activation of the insulated gate transistor.