Patent ID: 9082467
Filing Date: 2015-07-14
Classification: G11C

Abstract:
1. A sub word line driver of a semiconductor integrated circuit device, comprising: a semiconductor substrate configured to comprise an N-well having PMOS transistors formed therein and a P-well having NMOS transistors formed therein; four sub word lines configured to be extended in parallel over the N-well and P-well; a sub word line selection line configured to be extended in a direction parallel with the four sub word lines; first and second VSS lines configured to be formed on the P-well, extended in a direction vertical to the extended direction of the sub word lines, and spaced apart from each other at a predetermined interval; a first main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the first VSS line; a second main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the second VSS line; a third main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the first VSS line; and a fourth main word line configured to comprise a pair of bar electrodes substantially intersecting with the four sub word lines and a branch electrode intersecting with the second VSS line, wherein the sub word line driver further comprises a first keeper transistor positioned between the branch electrodes of the first and third main word lines and a second keeper transistor positioned between the branch electrodes of the second and fourth main word lines.