Patent ID: 6732208
Filing Date: 2004-05-04
Classification: G06F

Abstract:
A bus interface for a computing environment comprising:split transaction tracking and control for establishing transaction ID's for transactions to be presented on a computing bus having address and data buses, wherein said transactions have split address and data portions; and flow control logic, coupled to said split transaction tracking and control, for determining whether devices being read from, or written to, by said transactions, have buffers currently available to respond to said transactions, wherein said flow control logic comprises: a plurality of credit read counters, for tracking the number of available read buffers in said devices; and a plurality of credit write counters, for tracking the number of available write buffers in said devices; wherein if said flow control logic determines that said devices do not have buffers currently available to respond to said transactions, said flow control logic causes said transactions to not be presented until said buffers are available.