Patent ID: 6232551
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A substrate board structure for packaging a silicon chip that has a plurality of bonding pads, comprising:a plurality of circuit layers, wherein each of the circuit layer has a plurality of circuit lines; andan insulation layer between each pair of neighboring circuit layers, wherein the insulation layer further includes a plurality of vias for electrically connecting the circuit layers, an interior surface of each via has an electroplated metallic film, and a remaining interior space of the vias is filled with a filler material; whereinthe substrate board is formed by joining a circuit layer and an insulation layer alternately and cutting a portion of the substrate board to form a slot, wherein the circuit layer on the substrate board surface further includes circuit lines that are connected to a plurality of first contact points and a plurality of second contact points, the first contact points are closer to the slot, the circuit line that connects to the first contact point extends forward to reach a via, and the vias are positioned along the edge of the slot so that a portion of the metallic film inside the via is exposed through the cut surface of the slot.