Patent ID: 7705666
Filing Date: 2010-04-27
Classification: H03K

Abstract:
1. A filler circuit cell, comprising: a decoupled capacitor comprising a first n-type metal-oxide semiconductor (NMOS) transistor and a first p-type metal-oxide semiconductor (PMOS) transistor, wherein the source and drain of the first NMOS transistor is connected to a second voltage source and the source and drain of the first PMOS transistor is connected to a first voltage source; a tie low circuit disposed between the first voltage source, a gate of the first PMOS transistor and the second voltage source, wherein the tie low circuit comprises a second NMOS transistor and a second PMOS transistor; and a tie high circuit disposed between the first voltage source, a gate of the first NMOS transistor and the second voltage source, wherein the tie high circuit comprises a third NMOS transistor and a third PMOS transistor.