Patent ID: 9099023
Filing Date: 2015-08-04
Classification: G09G

Abstract:
1. A display driver circuit, comprising: a source driver configured to drive source lines of a display panel; and a timing controller configured to transfer image data to the source driver and to control the source driver such that the transferred image data is displayed via the display panel, the timing controller also being configured to transfer to the source driver a control signal and a test pattern, which are used to test a bit error rate of a channel between the timing controller and the source driver, and the source driver being configured to test the bit error rate of the transferred test pattern in response to the transferred control signal, the test of the bit error rate producing a result indicative of whether the image data transferred from the timing controller to the source driver is within a predetermined limit of error, the error based on signal delay or electromagnetic interference in the channel between the timing controller and source driver, wherein the timing controller includes a pattern generator configured to generate the test pattern, wherein the test pattern is randomized by a scrambler, and wherein the transferred test pattern is de-randomized by a de-scrambler, wherein the test pattern is a pseudo random binary sequence signal to be transferred after configuration signals configuring the test of the bit error rate and before wait signals indicating a transfer wait time, wherein the configuration signals are transferred to the source driver after a start of line signal SOL indicating data corresponding to a gate line, have a BER test start signal BEREN, a de-scrambler signal DSEN, and a de-scrambler reset signal DSRST, and wherein the transferred test pattern subject to the bit error rate test has a size corresponding to a number of pixels connected to a gate line.