Patent ID: 6988151
Filing Date: 2006-01-17
Classification: G06F

Abstract:
1. A storage control device comprising: a first channel control section for receiving data input and output requests from a first information processing device, and transmitting and receiving data, to and from said first information processing device; a second channel control section for receiving data input and output requests from a second information processing device, and transmitting and receiving data, to and from said second information processing device; a disk control section for reading and writing data, from and to a storage volume storing data, in accordance with said data input and output requests; and a cache memory for storing data transmitted and received between said first channel control section, said second channel control section and said disk control section; wherein said first channel control section comprises: a first memory; a first input/output control section for receiving data input and output requests from said first information processing device and controlling transmission and reception of data between said first memory and said first information processing device; a first processor for controlling said first memory and said cache memory; and a first data transfer device having a first memory controller for reading and writing data from and to said first memory, and a first data transfer control section for controlling data transfer between said first memory and said cache memory; and said second channel control section comprises: a second memory; a second input/output control section for controlling said second memory, receiving data input and output requests from said second information processing device and controlling transmission and reception of data between said second memory and said second information processing device; a second processor for controlling said cache memory; a second data transfer device having a second memory controller for reading and writing data from and to said second memory, and a second data transfer control section for controlling data transfer between said second memory and said cache memory; and in said first channel control section; in cases where said data input or output request received by said first input/output control section from said first information processing device is a first data write request; said first input/output control section transmits said first data write request to said first processor; said first processor transmits first storage position information containing information indicating a storage position in said first memory for the first write data transmitted by said first information processing device, to said first input/output control section; said first input/output control section starts to transmit information indicating the storage position in said first memory for said first write data, and said first write data, to said first memory controller; said first memory controller starts to write said first write data into said first memory; said first processor transmits first data transfer information containing information indicating the storage position in said first memory of said first write data, and information indicating a storage position in said cache memory for said first write data, to said first data transfer control section; said first data transfer control section transmits a read request for said first write data written to said first memory, to said first memory controller, on the basis of said first data transfer information; said first memory controller starts to read out said first write data from said first memory; and said first data transfer control section starts to transfer said first write data read out from said first memory, to said cache memory; and in said second channel control section; in cases where said data input and output request received by said second input/output control section from said second information processing device is a second data write request; said second input/output control section starts to transmit information indicating a storage position in said second memory for said second write data transmitted by said second information processing device, and said second write data, to said second memory controller; said second memory controller starts to write said second write data into said second memory; said second input/output control section transmits second storage position information containing information indicating the storage position in said second memory for the second write data, to said second processor; said second processor transmits second data transfer information containing information indicating the storage position in said second memory of said second write data, and information indicating a storage position in said cache memory for said second write data, to said second data transfer control section; said second data transfer control section transmits a read request for said second write data written to said second memory, to said second memory controller, on the basis of said second data transfer information; said second memory controller starts to read out said second write data from said second memory; and said second data transfer control section starts to transfer said second write data read out from said second memory, to said cache memory.