Patent ID: 6292012
Filing Date: 2001-09-18
Classification: G06F,G11C

Abstract:
A device for preventing loss of data from a programmable non-volatile memory, comprising:a first combinatorial logic circuit with a plurality of input terminals for receiving a first set of input signals and an output terminal for issuing a memory write enable signal;a second combinatorial logic circuit with a plurality of input terminals for receiving a second set of input signals and an output terminal for issuing a reset signal;a delay circuit with an input terminal coupled to a source voltage and an output terminal for issuing an enable signal;a low-enable latching device with reset capability, wherein the low-enable latching device has two input terminals, a control terminal and an output terminal, the input terminals are coupled to the source voltage and the output terminal of the delay circuit, respectively, the control terminal is coupled to the output terminal of the second combinatorial logic circuit and the output terminal is used for issuing an output signal;an AND gate whose input terminals are coupled to the output terminal of the first combinatorial logic circuit and the low-enable latching device, respectively, and whose output terminal is used for issuing a memory re-program control signal; anda memory cell array coupled to the output terminal of the AND gate for storing program code;wherein when the first and the second set of input signals received by the respective first and second combinatorial logic circuit match their preset internal parameters, a logic `true` signal is issued on the memory write enable signal line and the reset signal line by the respective first and second logic circuit, and when the first and the second set of input signals received by the respective first and second combinatorial logic circuit do not match their preset internal parameters, a logic `false` signal is issued on the memory write enable signal line and the reset signal line by the respective first and second logic circuit, such that when the memory re-program control signal line receives a logic `false` signal, the memory cell array is in a non-programmable state, and conversely, when the memory re-program control signal line receives a logic `true` signal, the memory cell array is in a programmable state.