Patent ID: 9006052
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A method comprising: forming a Si film on an insulator layer; thinning the Si film; forming an epitaxial stress layer on an upper surface of the thinned Si film; forming a masking layer on the epitaxial stress layer and providing an opening therein; foaming a trench in the epitaxial stress layer through the opening of the masking layer, the trench ending at the upper surface of the thinned Si film; embedding a Si layer in the trench of the epitaxial stress layer, through the opening in the masking layer, the Si layer, which forms an active channel region of a gate structure, having a stress imposed thereon by the epitaxial stress layer; and forming the gate structure on the Si layer and within the opening formed in the masking layer, wherein the method further comprises, after the thinning the Si film, forming isolation regions having bottom surfaces directly on the insulator layer and top surfaces level with a top surface of the epitaxial stress layer.