Patent ID: 6738291
Filing Date: 2004-05-18
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array region in which a plurality of nonvolatile memory cells are arranged, each of the nonvolatile memory cells comprising a control gate; and a control gate voltage generation section which generates a voltage driving the control gate of each of the nonvolatile memory cells in the memory cell array region, wherein the control gate voltage generation section includes: a booster circuit which generates a plurality of voltages; and a voltage control circuit which comprises a plurality of voltage input terminals and a plurality of voltage output terminals, the voltage control circuit switching and outputting the voltages from the booster circuit through the voltage input terminals to the voltage output terminals in accordance with a selection state of the nonvolatile memory cells, and wherein the voltage control circuit is set to a disconnection state, in which no voltage is outputted from the voltage raising circuit to any of the voltage output terminals, before the voltages are outputted from the voltage output terminals.