Patent ID: 6223332
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A method for refining the positions of linearly aligned cells on the surface of a semiconductor chip, comprising the steps of:(a) defining an array of spaces between the linearly aligned cells;(b) establishing a minimum spacing and a maximum spacing between the cells;(c) processing each space in the array of spaces as follows:(c1) if a first condition is satisfied, increasing the space, wherein the first condition includes a condition that the space is less than the minimum spacing;(c2) if a second condition is satisfied, increasing the space, wherein the second condition includes a condition that the first condition has failed and a condition that the space is less than the maximum spacing; and(c3) if a third condition is satisfied, decreasing the space, wherein the third condition includes a condition that the second condition has failed and a condition that the space is greater than the maximum spacing; and(d) adjusting the positions of the cells based on the spaces determined in accordance with steps (a) through (c).