Patent ID: 6813703
Filing Date: 2004-11-02
Classification: G06F

Abstract:
A data-driven processor emulation system which, using real data-driven processors, emulates virtual data-driven processors each organized as a pipeline consisting of a sequence of stages, each stage having a data latch for holding a packet, a logic circuit for processing the packet held in said data latch, a self-timed transfer control mechanism for supplying a synchronizing signal to said data latch, and an optional gate logic for controlling, based on processing results from said logic circuit, a SEND signal and an ACK signal transferred between said self-timed transfer control mechanism in said stage and a self-timed transfer control mechanism in a downstream stage, wherein each of said real data-driven processors comprises:data path emulation means for expressing a virtual packet, to be processed in said virtual data-driven processors, as a PACKET message which is a packet to be processed in said real data-driven processor, and for evaluating processing operation of said virtual packet for each functional block within said virtual data-driven processors; and timing path emulation means for expressing said SEND signal and said ACK signal, to be controlled by said self-timed transfer control mechanism and said gate logic, as a SEND message and an ACK message, respectively, which are packets to be processed in said real data-driven processor, and for evaluating stage-to-stage transfer operations of said SEND signal and said ACK signal.