Patent ID: 8189414
Filing Date: 2012-05-29
Classification: G11C

Abstract:
1. A method of operating a memory device, the method comprising: activating a first transistor of a pair of parallel coupled transistors in response to a potential of a first data line, wherein the first transistor of the pair of parallel coupled transistors has a gate coupled to the first data line, a first source/drain region coupled to a second data line, and a second source/drain region coupled to receive a first control signal; activating another transistor in response to activating the first transistor of the pair of parallel coupled transistors, wherein the another transistor has a gate coupled to the second data line, a first source/drain region coupled to the first data line, and a second source/drain region coupled to a voltage source; activating a second transistor of the pair of parallel coupled transistors after activating the another transistor and while maintaining activation of the first transistor of the pair of parallel coupled transistors, wherein the second transistor of the pair of parallel coupled transistors has a gate coupled to the first data line, a first source/drain region coupled to the second data line, and a second source/drain region coupled to receive a second control signal; and deactivating the first transistor of the pair of parallel coupled transistors while maintaining activation of the second transistor of the pair of parallel coupled transistors and maintaining activation of the another transistor.