Patent ID: 6025247
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method for manufacturing a capacitor structure of a semiconductor device, comprising the steps of:a. forming a first insulating layer over a substrate having a transistor structure;b. forming a first and a second contact holes on said first insulating layer;c. forming a first conducting layer over said first insulating layer for forming a first and a second contact plugs in said first and second contact holes respectively;d. forming a silicide layer over said first conducting layer, and defining a pattern of a bit line structure over said silicide layer, and etching to form said bit line structure according to said pattern of said bit line structure;e. forming an etching stop layer and a second insulating layer over said substrate, and removing a portion of said etching stop layer and said second insulating layer for forming a capacitor area wherein said second contact plug is exposed;f. forming a second conducting layer over said substrate, and forming a sacrificial layer in said capacitor area for covering a portion of said second conducting layer;g. removing a portion of said second conducting layer above said second insulating layer so that a remaining portion of the second conducting layer covered by said sacrificial layer forms a first electrode;h. removing said sacrificial layer and forming a third insulating layer along a remaining portion of said second insulating layer and the remaining portion of said second conducting layer to serve as a dielectric layer; andi. forming a third conducting layer above said dielectric layer to serve as a second electrode layer of said capacitor structure and to result in a substantially smooth topography about said capacitor.