Patent ID: 7656212
Filing Date: 2010-02-02
Classification: H03K

Abstract:
1. A stacked inverter delay chain, comprising: a plurality of stacked inverter delay elements coupled in series with each stacked inverter delay element having a plurality of n-type transistors coupled with a plurality of p-type transistors in series; a switch circuit comprising a plurality of AND gates and NOR gates coupled to the plurality of stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path having an amount of delay in accordance with a selected number of the plurality of stacked inverter delay elements; an input coupled to a first one of the plurality of stacked inverter delay elements of the delay signal path to receive an input signal; an output coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path; and a plurality of turnoff devices coupled to inputs of the plurality of stacked inverter delay elements and coupled to the switch circuit, wherein the switch circuit activates at least one of the plurality of turnoff devices coupled to at least one unused one of the plurality of stacked inverter delay elements that is not on the delay signal path.