Patent ID: 7054213
Filing Date: 2006-05-30
Classification: G11C

Abstract:
1. A dynamic random access memory circuit capable of operating in either a test mode or a normal mode, the dynamic random access memory circuit comprising: a first memory cell, a first characterization cell, and a second characterization cell coupled to a first bit line; a second memory cell, a third characterization cell, and a fourth characterization cell coupled to a second bit line; and a sense amplifier for sensing a voltage differential appearing between the first bit line and the second bit line and outputting a signal indicative of the sensed voltage differential; wherein during the normal mode the first memory cell is selectively enabled to transfer a first memory charge onto the first bit line and the second memory cell is selectively enabled to transfer a second memory charge onto the second bit line, and the output signal provides a logic level relating to the transferred memory charge; wherein during a first test mode the first characterization cell is selectively enabled to transfer a predetermined first reference charge onto the first bit line and the third characterization cell is simultaneously selectively enabled to transfer a predetermined second reference charge that is different from the first reference charge by an increment onto the second bit line, and the output signal provides information relating to a sensitivity of the sense amplifier; and wherein during a second test mode the second characterization cell is selectively enabled to transfer a predetermined third reference charge onto the first bit line and the fourth characterization cell is simultaneously selectively enabled to transfer a predetermined fourth reference charge that is different from the third reference charge by an increment onto the second bit line, and the output signal provides information relating to a sensitivity of the sense amplifier.