Patent ID: 8929165
Filing Date: 2015-01-06
Classification: G11C

Abstract:
1. A memory device comprising: a memory cell array comprising normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, wherein the rows are divided into a plurality of segments; a segment match determining circuit configured to compare a segment address received at the memory device with row address information corresponding to a failed segment and to generate a load control signal; and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address received at the memory device and to generate a column address replacement control signal, wherein the memory device is configured to replace at least one of normal memory cells connected to the failed column of the failed segment with at least one corresponding spare memory cell connected to the at least one spare column in response to the column address replacement control signal, and wherein the segment match determining circuit comprises: