Patent ID: 7493579
Filing Date: 2009-02-17
Classification: G06F

Abstract:
1. A generation method of static noise check data for a hierarchical layout design of a semiconductor device having a plurality of cores each including same sub-chips, wherein the semiconductor device comprising a sub-chip level hierarchy, a core level hierarchy, and a chip level hierarchy as a layout hierarchy of the layout design and the generation method comprising: inputting a design data of the core level hierarchy of one of the plurality of cores of the semiconductor device; generating a static noise check data of the core level hierarchy of one of the plurality of cores; copying the inputted design data of the core level hierarchy of one of the plurality of cores; performing inversion or rotation processing of the copied design data of the core level hierarchy; converting coordinates of the inverted or the rotated design data of the core level hierarchy to the design data of the chip level hierarchy, and generating a design data of the chip level hierarchy; adding a chip wiring data of the chip level hierarchy on the design data of the chip level hierarchy, and generating a merged design data of the chip level hierarchy; and generating the static noise check data of the chip level hierarchy.