Patent ID: 6931505
Filing Date: 2005-08-16
Classification: G06F

Abstract:
1. A memory controller, comprising: an array of tag address storage locations; and a command sequencer and serializer unit coupled to the array of tag address storage locations to receive information regarding whether there is a cache hit from the array of tage address storage locations, the command sequencer and serializer unit to control a data cache located on a memory module using the received information, the command sequencer and serializer unit to control the data cache located on the memory module by delivering a plurality of commands over a plurality of command and address lines, the commands sequentially delivered over a plurality of transfer periods of a memory access transaction and each command being delivered within one of the transfer periods, the plurality of commands including an activate command and a cache fetch command, the activate and cache fetch commands differing in format only in the information delivered during a last transfer period of the plurality of transfer periods.