Patent ID: 7305586
Filing Date: 2007-12-04
Classification: G06F

Abstract:
1. A microprocessor, comprising: a serial communication bus including an address line and a data line, the serial communication bus being within the processor and accessible through an external port; an execution pipeline; a pipeline satellite circuit coupling the pipeline to the address and data lines of the communication bus and being addressable on the communication bus via a first unique address, wherein the satellite circuit enables an external agent to provide an executable instruction directly to the execution pipeline via the communication bus; and a dedicated register and register satellite circuit, the register satellite circuit coupling the register to the communication bus via the address and data lines of the communication bus and being addressable on the communication bus via a second unique address, wherein the register satellite circuit and the pipeline satellite circuit each include a two-wire serial bus data unit and a two-wire serial bus address unit, wherein each two-wire serial bus address unit is connected to the address line, each two-wire serial bus data unit is connected to the data line, and wherein each two-wire serial address unit further includes: wherein the execution pipeline is enabled to access the dedicated register during execution of the instruction and wherein the pipeline satellite circuit and the register satellite circuit enable access of architected registers in the microprocessor through the external port, wherein the pipeline satellite bypasses an instruction decode stage of the pipeline and enables direct access to an execution stage of the pipeline such that the set of instructions the execution pipeline is capable of executing is greater than the set of instructions capable of being produced by the decode stage., wherein the provided instruction enables access of a next instruction address (NIA) of the processors to control execution flow.