Patent ID: 8379432
Filing Date: 2013-02-19
Classification: G11C

Abstract:
1. A nonvolatile semiconductor storage device comprising: a plurality of first wires and a plurality of second wires intersecting each other; a plurality of memory cells which is disposed at each intersection of the plurality of first wires and the plurality of second wires and having a variable resistor and a rectifying device are connected in series; and a control circuit which applies a voltage to the first and second wires, wherein the control circuit applies a reference voltage to a selected second wire of the plurality of second wires and non-selected first wires of the plurality of first wires, applies a standby voltage larger than the reference voltage to non-selected second wires of the plurality of second wires, and applies a program voltage to selected first wires of the plurality of first wires, and the control circuit precharges the non-selected second wires up to the standby voltage prior to a plurality of verify operations to the variable resistor and maintains the non-selected second wires at the standby voltage during the plurality of verify operations.