Patent ID: 6820181
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A memory module, comprising:a plurality of memory devices; and a memory hub, comprising: a memory request queue storing a least one memory request received through an input port, the memory request queue being coupled to the memory devices to transmit each memory request stored in the memory request queue to the memory devices, the memory request queue being operable to output a respective read released signal identifying each read memory request transmitted to the memory devices and to output a respective write released signal identifying each write memory request transmitted to the memory devices; a flow control unit coupled to the memory request queue, the flow control unit being operable to receive the read released signal and the write released signal from the memory request queue, the flow control unit being operable to output status signals corresponding to the released signals; a memory read queue coupled to the memory devices, the memory read queue receiving read data from the memory devices and storing the read data for coupling to an output port; a memory write queue coupled to receive a signal indicating that each write memory request has been coupled from the memory request queue to the memory devices, the memory write queue storing signals indicating that a write request has been transmitted to the memory devices; and a response generator coupled to the flow control unit, the memory read queue and the memory write queue, the response generator being operable to generate and transmit from an output port read responses each containing the read data from the read data queue and a read status signal corresponding to a status signal from the flow control unit, the response generator further being operable to transmit from the output port write responses each containing a write status signal corresponding to a status signal from the flow control unit.