Patent ID: 8742564
Filing Date: 2014-06-03
Classification: H01L

Abstract:
1. A chip package, comprising: a semiconductor substrate having a first surface and a second surface; a conducting pad structure located on the first surface of the semiconductor substrate; a dielectric layer located on the first surface of the semiconductor substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; a cap layer located on the dielectric layer and filled into the opening; a conductive bump located on the second surface of the semiconductor substrate, wherein the semiconductor substrate is located between the cap layer and the conductive bump; a hole extending from the second surface toward the first surface of the semiconductor substrate and exposing a portion of the conducting pad structure; an insulating layer located on a sidewall of the hole; and a conducting layer located on the insulating layer on the sidewall of the hole, wherein the conducting layer electrically contacts with the conducting pad structure.