Patent ID: 6560768
Filing Date: 2003-05-06
Classification: B82Y,H01J

Abstract:
A circuit pattern design method which uses a plurality of standard cells having circuit patterns optimized for function units on the basis of a logic description which describes circuit operation of a semiconductor device, and which forms a circuit pattern corresponding to charged-particle beam exposure using both a character projection exposure method and a variable shaped beam exposure method, the method comprising:generating one or more provisional circuit patterns while gradually decreasing a number of standard cells to be used; determining whether the generated one or more provisional circuit patterns satisfy a design constraint condition; calculating a number of charged-particle beam shots when at least one of said one or more provisional circuit patterns which satisfies the design constraint condition is exposed with a charged-particle beam; and selecting a circuit pattern to be used for exposure from the at least one provisional circuit pattern determined as satisfying the design constraint condition.