Patent ID: 6054356
Filing Date: 2000-04-25
Classification: H01L

Abstract:
A process of forming a transistor, comprising:providing a semiconductor topography;patterning a gate conductor upon a select region of said semiconductor topography, wherein said gate conductor includes opposed sidewall surfaces which extend substantially perpendicular to said semiconductor topography;depositing a spin-on material across said gate conductor and said semiconductor topography, wherein portions of said spin-on material are in contact with the opposed sidewall surfaces and an uppermost surface of said gate conductor;heating said spin-on material to form a spin-on dielectric having a meniscus extending in a lateral direction from said sidewall surfaces,performing a first implant through said spin-on dielectric and into said semiconductor topography to form a source region and a drain region aligned with said sidewall surface wherein a doping profile of said source region and said drain region correspond to an upper surface contour of said meniscus, and wherein an entirety of a dielectric mask through which the first implant is performed consists of the spin-on dielectric.