Patent ID: 6033232
Filing Date: 2000-03-07
Classification: H01L,Y10S

Abstract:
A method of fabricating a photodiode, a first MOS device and a second MOS device within a first active region, a second active region and a third active region, respectively, of a substrate, comprising the following steps of:(a) forming a first gate structure and second gate structure on said substrate within said second active region and said third active region, respectively;(b) forming first lightly-doped regions by introducing first dopants into said substrate throughout said second active region by said first gate structure as masking;(c) forming a diffusion region in said substrate within said first active region;(d) forming second lightly-doped regions by introducing second dopants into said substrate throughout said third active region by said second gate structure as masking;(e) forming an insulating layer overlying said first, second and third active regions;(f) thinning said insulating layer;(g) patterning one portion of said insulating layer within said second active region to first sidewall spacers on the sidewalls of said first gate structure;(h) forming first heavily-doped regions by introducing third dopants throughout said second active region into said substrate by said first gate structure and said first sidewall spacers as masking;(i) patterning another portion of said insulating layer within said third active region to second sidewall spacers on the sidewalls of said second gate structure; and(j) forming second heavily-doped regions by introducing fourth dopants throughout said third active region into said substrate by said second gate structure and said second sidewall spacers as masking.