Patent ID: 6184093
Filing Date: 2001-02-06
Classification: H01L,Y10S

Abstract:
A method of forming a semiconductor device comprising:providing a semiconductor substrate including a memory region and a periphery region;forming a first gate oxide layer having a first thickness on said semiconductor substrate;forming a first conducting layer on said first gate oxide layer;masking and patterning said first conducting layer and said first gate oxide layer to form a first memory gate electrode in said memory region and a first periphery gate electrode in said periphery region;forming by thermal oxidation a second gate oxide layer over a portion of said periphery region exclusive of said first periphery gate electrode, said second gate oxide layer having a second thickness different than said first thickness;forming a second conducting layer on at least said second gate oxide layer;masking and patterning said second conducting layer and said second gate oxide to form a second memory gate electrode in said memory region and a second periphery gate electrode in said periphery region.