Patent ID: 6651205
Filing Date: 2003-11-18
Classification: G01R

Abstract:
A test pattern converter for converting test pattern data described in a cycle format for testing a semiconductor device to test pattern data in an event format, comprising:a pattern controller for sequentially reading out pattern count data indicating a pattern number assigned to specify a test cycle in a test pattern described in the cycle format and timing set data specifying a type of time length of the test cycle indicated by the pattern number; a cycle generator for reading out, based on the timing set data from the pattern controller, a value of the time length of the test cycle corresponding to the pattern number; a pattern data generator for reading out, based on the pattern count data from the pattern controller, a logic value (pattern data) of a test pattern waveform corresponding to the pattern number; a waveform data generator for reading out, based on the timing set data from the pattern controller, format data indicating a type of the test pattern waveform in the test cycle corresponding to the timing set data and timing data indicating a delay time of a rising edge or a falling edge of the test pattern waveform from a start point of the test cycle; and a calculation unit for forming the test pattern in the event format based on the data from the pattern data generator and from the waveform data generator wherein the event format test pattern describes the events by combinations of change points of the test waveform and time differences of the change points from a reference point.