Patent ID: 6137126
Filing Date: 2000-10-24
Classification: H01L,Y10S

Abstract:
A method for manufacturing a semiconductor device, the method comprising:forming a field dielectric region on a main surface of a semiconductor substrate isolating an active region;forming a transistor in the active region, the transistor comprising:a first gate electrode, having side surfaces, on the main surface with a gate dielectric layer therebetween;silicon carbide sidewall spacers on the side surfaces of the gate electrode; andsource/drain regions having shallow extensions in the substrate with a channel region therebetween and underlying the gate electrode;forming a second gate electrode extending on the field dielectric region;depositing an inter-dielectric layer over the transistor, field dielectric region and second gate electrode;etching to form an opening in the inter-dielectric layer exposing a portion of a source/drain region, field dielectric region and second gate electrode; andfilling the opening with a conductive material to form a local interconnect between the source/drain region and second gate electrode, wherein the composite dielectric constant between the first gate electrode and local interconnect is about 4.2 to about 4.7.