Patent ID: 9171838
Filing Date: 2015-10-27
Classification: H01L,H03F

Abstract:
1. An integrated semiconductor device comprising: a substrate layer, an n-port, n being an integer equal to or larger than 2, having a first port terminal, a second port terminal and a ground terminal, said n-port being formed within said substrate layer on a first side of said substrate layer, an insulating layer formed on a surface on said first side of said substrate layer, a ground plane layer formed between said substrate layer and said insulating layer, said ground plane layer being in contact with one terminal of said n-port, a signal plane layer formed on a surface of said insulating layer facing away from said substrate layer, a via hole formed through said insulating layer and electrically contacting said signal plane layer with another terminal of said n-port than said ground plane layer, a terminal formed within said insulating layer and electrically contacting said terminal of said n-port that is neither in contact with said ground plane layer nor with said signal plane layer, and a resistor formed within said ground plane layer.