Patent ID: 6077748
Filing Date: 2000-06-20
Classification: H01L

Abstract:
A method for fabricating an IGFET device, the method comprising the steps of:forming a first and a second trench in a substrate;fabricating a first and a second isolation structure, said first and second isolation structure filling said first and second trenches, said first and said second isolation structures extending a predetermined distance above a surface of said substrate, wherein fabricating the first and the second isolation structure includes:forming a silicon oxide layer over said substrate;forming a mask layer, said mask layer aligned with said trenches; andremoving said oxide layer in a region between said trenches;forming a plurality of doped regions in said substrate;providing a gate structure between said first and said second isolation structures and separated therefrom, said gate structure extending above said surface of said substrate by said predetermined distance;forming source/drain regions in said substrate in between gate structure and said isolation structures;forming an insulating layer between said gate structure and said isolation structures, andforming conducting vias in said insulating layer, said conducting vias electrically coupled to said source/drain regions.