Patent ID: 7816771
Filing Date: 2010-10-19
Classification: H01L

Abstract:
1. A chip-stacked package structure with a leadframe having inner leads, each inner lead having a plurality of transfer pads, comprising: the leadframe, composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein said die pad is provided between said plurality of inner leads arranged in rows facing each other and vertically distant from said plurality of inner leads, positions of a top surface of each of said inner leads being partially coated with an insulation layer and a plurality of metal pads being selectively formed on said insulation layer to define said respective pads; an offset chip-stacked structure formed with a plurality of chips stacked together, said offest chip-stacked structure being set on said die pad and electrically connected to said plurality of inner leads arranged in rows facing each other; an encapsulant partially covering said offset chip-stacked structure and said leadframe, said plurality of outer leads extending out of said encapsulant; and at least a bus bar being provided between said plurality of inner leads arranged in rows facing each other and said die pad, said bus bar being further coated with an insulation layer and a plurality of metal pads being selectively formed on said insulation layer to define said respective pads.