Patent ID: 6532507
Filing Date: 2003-03-11
Classification: G06F

Abstract:
A system, including:a first bus; a second bus; a first processor connected along the first bus, wherein the first processor operates in response to a first clock having a first frequency; a device connected along the second bus; a second processor connected along the second bus, wherein the second processor operates in response to a second clock having a second frequency lower than the first frequency, and wherein the second processor is configured to contend for access to the second bus and thus for access to the device connected along the second bus; and a communication device connected between the first bus and the second bus, wherein the communication device is configured to provide the first processor continuous access to the second bus for a limited time interval in response to grant of a request by the first processor for access to the second bus, a first time is required for a word transfer between the first processor and the device connected along the second bus, the limited time interval is longer than the first time, and the communication device is configured to continue to provide the first processor continuous access to the second bus, after initial transfer of a word is accomplished between the first processor and the device, for an additional time interval that does not exceed a predetermined maximum time.