Patent ID: 6287956
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method of forming a multilevel interconnecting structure, comprising the steps of:forming a first interconnecting layer via an insulating film on a semiconductor substrate:forming an SiOF film as a fluorine-doped oxide film on said first interconnecting layer and said insulating film;forming an intermediate insulating film as an oxide film not containing fluorine on said SiOF film;planarizing a surface of said intermediate insulating film by an SOG film formed by coating an entire surface of said intermediate insulating film with an SOG coating solution;etching back surfaces of said SOG film and said intermediate insulating film by dry etching using a fluorine-based gas wherein the etching rates on a surface of said SOG film and a surface of said intermediate insulating film are set to be substantially equal to each other;forming a through hole reaching said first interconnecting layer in a predetermined position; andforming a second interconnecting layer above said intermediate insulating film and electrically connected to said first interconnecting layer.