Patent ID: 6168991
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method for forming a capacitor in a DRAM cell, the DRAM cell comprising a transistor and first and second plugs through a first dielectric layer, the first dielectric layer and a second dielectric layer disposed over the transistor, the first and second plugs electrically connected to the transistor, comprising the steps of: forming a first opening in the second dielectric layer exposing a portion of the first plug; depositing a first electrode layer on exposed surfaces of the first opening and the first plug; depositing a high dielectric film over the first electrode layer; forming a second opening through the first electrode layer and the high dielectric film into the second dielectric layer after said step of depositing the high dielectric film, the second opening exposing the second plug; and, depositing a second electrode layer over the high dielectric film forming a capacitor structure in the first opening and a barrier layer in the second opening over the second plug.