Patent ID: 9141120
Filing Date: 2015-09-22
Classification: G05F

Abstract:
1. A voltage regulator, comprising: a first power source terminal at which an input voltage can be applied; a second power source terminal at which a power source reference voltage can be applied; an output terminal at which an output voltage can be output; an operational amplifier configured to compare a predetermined reference voltage to a feedback voltage that is proportional to the output voltage and output an output signal corresponding to the comparison of the predetermined reference voltage and the feedback voltage; a detecting circuit configured to detect an operating state of the operational amplifier and output a control signal according to the operating state detected; and an output transistor connected between the first power source terminal and the output terminal, a conductance state of the output transistor being changeable based on the output signal of the operational amplifier and the control signal from the detecting circuit, wherein the control signal from the detecting circuit changes the conductance state of the output transistor to a non-conductive state when the operational amplifier is not operating while the input voltage is being applied to the first power source terminal, wherein the output transistor comprises a first p-channel metal oxide semiconductor (PMOS) transistor that has a source electrode connected to the first power source terminal and a drain electrode connected to the output terminal, wherein the control signal from the detecting circuit is supplied to a gate electrode of the first PMOS transistor, and wherein the operation amplifier includes: a second PMOS transistor that has a source electrode connected to the first power source terminal; a third PMOS transistor that has a gate electrode at which the predetermined reference voltage is applied and a source electrode connected to a drain electrode of the second PMOS transistor; a fourth PMOS transistor that has a gate electrode at which the feedback voltage is applied and a source electrode connected to the drain electrode of the second PMOS transistor; a first n-channel metal oxide semiconductor (NMOS) transistor that has a drain electrode connected to a drain electrode of the third PMOS transistor and a source electrode connected to the second power source terminal; and a second NMOS transistor that has a drain electrode connected to a drain of the fourth PMOS transistor, a source electrode connected to the second power source terminal, and a gate electrode connected to a gate electrode of the first NMOS transistor.