Patent ID: 8058169
Filing Date: 2011-11-15
Classification: H01L,Y10S

Abstract:
1. A method of forming a semiconductor memory device, comprising: providing a substrate including an inner region with a plurality of memory cells, an intermediate region located aside the inner region, and an outer region on a side of the intermediate region opposite to the inner region; forming an insulating layer, a conductive layer and a sacrificial layer sequentially on the substrate patterning the sacrificial layer to form a sacrificial pattern including at least one rectangular opening across the inner region and the intermediate region through which the conductive layer is partially exposed, the rectangular opening including a first opening in the inner region and a second opening in the intermediate region, a size of the second opening greater than a size of the first opening; forming at least a pair of spacer lines on a sidewall of the sacrificial pattern along the rectangular opening, a first gap distance of the pair of the spacer lines in the inner region less than a second gap distance of the pair of spacer lines in the intermediate region; removing the sacrificial pattern; and patterning the conductive layer using the spacer lines as an etch mask to form a plurality of conductive lines extending across the inner region and the intermediate region, a pair of the conductive lines being spaced apart by the first gap distance in the inner region and by the second gap distance in the intermediate region.