Patent ID: 6704878
Filing Date: 2004-03-09
Classification: G06F

Abstract:
An apparatus for minimizing power dissipation in a semiconductor device, comprising:a first register for accepting a plurality of input signals; a first computation circuit coupled to the first register for computing output signals according to the plurality of input signals; a second register for accepting at least one of the input signals; a pre-computation circuit coupled to the second register for computing a pre-determined output signal if a pre-determined set of input signals is detected and wherein the second computation circuit is smaller and has less logic than the first computation circuit; a decision circuit coupled to the second register which determines whether it is possible to perform precomputation, wherein if precomputation is possible, the decision circuit causes the first register to be disabled which deactivates the first computation circuit while the second register is enabled and the pre-computation circuit generates the pre-determined output signal and wherein if precomputation is not possible, the second register is disabled which deactivates the pre-computation circuit while the first register is enabled such that the first computation circuit generates the output signals.