Patent ID: 7805623
Filing Date: 2010-09-28
Classification: G06F,Y02D

Abstract:
1. A circuit adopted in a computer, comprising: a power supply with an output for providing a standby voltage supply; a motherboard with a pin for receiving the standby voltage supply; a switch circuit connected between the power supply and the motherboard, the switch circuit having a control terminal fed with a S5# signal which is at high level to turn on the switch circuit when the computer is at S0, S1, S2, S3, or S4 power state such that the standby voltage supply is supplied to the motherboard via the switch circuit, and at low level to turn off the switch circuit when the computer is at S5 power state to cut off the standby voltage supply from the power supply to the motherboard for reducing power consumption of the motherboard; the control terminal of the switch circuit further being supplied with an inverted PWRBTN# signal for turning on the switch circuit when the PWRBTN# signal is at low level for switching on or off the computer; the control terminal of the switch circuit further being supplied with a GPIO signal; and an OR gate comprising three input terminals and one output terminal, the S5# signal, the PWRBTN# signal and the GPIO signal connected to the three input terminals, and the control terminal of the switch circuit connected to the output terminal to achieve the S5# signal, the PWRBTN# signal and the GPIO signal supplied to the control terminal of the switch circuit, any one of the S5# signal, the PWRBTN# signal and the GPIO signal respectively and singly controlling turning on the switch circuit.