Patent ID: 8183631
Filing Date: 2012-05-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having an upper main surface and a lower main surface, said semiconductor substrate including: a first main electrode connected to said main base region, said peripheral base region and said source region and not connected to said underpad base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an exposed surface of said underpad base region in said upper main surface with an insulating layer interposed therebetween and said conductive gate pad is connected to said gate electrode; a conductive layer buried in the insulating layer to be opposed to said upper main surface in a vertical position closer to the upper main surface than the conductive gate pad, the conductive layer being extended to reach a location above the peripheral base region; and a second main electrode connected to said lower main surface, wherein a maximal depth of the main base region from the upper main surface of the substrate is shallower than a maximal depth of the underpad base region.