Patent ID: 6971081
Filing Date: 2005-11-29
Classification: G06F,H01L,H05K

Abstract:
1. In a substrate having an electrically nonconductive core with vias disposed therein and an electrically conductive reference layer formed on the electrically nonconductive core with voids in the electrically conductive reference layer that are formed around the vias in the electrically nonconductive core and electrically conductive traces on a routing layer overlying the electrically conductive reference layer, and a contact layer with electrically conductive contacts disposed in a contact pattern, the improvement comprising the core logically divided into sections, the vias within a given one of each of the sections aligned in rows substantially along a first direction and not aligned with the contact pattern, the voids in the reference layer within the given one of each of the sections also aligned in rows substantially along the first direction and aligned with the vias, and the traces within the given one of each of the sections also aligned substantially along the first direction between the rows of voids and not substantially overlying the rows of voids.