Patent ID: 6789219
Filing Date: 2004-09-07
Classification: G01R

Abstract:
An arrangement for testing an integrated circuit comprising at least two circuit sections (1, 2) which in normal operation operate with at least two different clock signals, characterized in that the integrated circuit to be tested is formed in such a way that each clock signal can be individually switched on and off during a test by test software provided in the arrangement, in that a software model of the circuit to be tested is provided in the arrangement, which software model comprises an X generator (38, 40) for those circuit components (33, 35) whose mode of operation is influenced by a plurality of clock signals and their skew behavior, which X generator is activated and supplies an X signal when more than one clock signal influencing the mode of operation of the circuit components (33, 35) during testing is activated, in that, during testing, the test software initially activates all clock signals and evaluates test results for those circuit components (3, 5) for which no X signal appears in the software model (33, 35), and in that for those circuit components (3, 5) for which an X signal appeared in the software model (33, 35) during testing with all clock signals, the test software performs a plurality of test runs in which each time only one or more of the clock signals influencing the mode of operation of the circuit component (3, 5) is/are activated and evaluates only those tests of the circuit components (3, 5) of the circuit for which no X signal appears in the software model (33, 35).