Patent ID: 9171862
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A method of forming a three-dimensional memory, comprising: forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of semiconductor layers and a plurality of insulating layers arranged alternately; patterning the stacked structure to form a mesh structure, wherein the mesh structure has a plurality of first strips extending in a first direction and a plurality of second strips extending in a second direction, and the first strips and the second strips intersect with each other, and wherein the mesh structure has a plurality of first holes; forming a dielectric layer in each of the first holes; after the step of patterning the stacked structure, removing at least a portion of the first strips of the mesh structure, so as to form a plurality of second holes and a plurality of bit line stacked structures, wherein the bit line stacked structures are separated from each other by the second holes; forming a charge storage layer on a sidewall and a bottom of each of the second holes; forming a gate pillar extending in a third direction on each charge storage layer in the corresponding second hole; and forming a plurality of word lines extending in the first direction on the gate pillars.