Patent ID: 9190503
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. An IGBT that is equipped with a semiconductor substrate, the IGBT comprising: an n-type emitter region that is formed in such a range as to be exposed to an upper face of the semiconductor substrate; a p-type top body region that is formed below the emitter region; an n-type floating region that is formed below the top body region and separated from the emitter region by the top body region; a p-type bottom body region that is formed below the floating region and separated from the top body region by the floating region; a trench that is formed in the upper face of the semiconductor substrate and penetrates the emitter region, the top body region, the floating region, and the bottom body region; a gate insulating film that covers an inner face of the trench; and a gate electrode that is arranged inside the trench, wherein when a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of the semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and reaches a local minimum value at a predetermined depth in the floating region.