Patent ID: 6233193
Filing Date: 2001-05-15
Classification: G11C

Abstract:
A memory comprising:an array of rows and columns of dynamic memory cells, said cells of each said row coupled to an access wordline and a refresh wordline and said cells of each said column coupled to an access bitline and a refresh bitline, said access and refresh bitlines being independently prechargeable;refresh circuitry for refreshing a selected one of said rows of cells using a corresponding refresh wordline and a corresponding refresh bitline;access circuitry for accessing selected cells of a selected one of said rows of cells using a corresponding one of said access wordlines and corresponding one of said access bitlines, said access circuitry comprising:a new address detector for detecting receipt of a new address by said memory;a row decoder for selecting said access wordline in response to receipt of said new address;access sense amplifiers and an access column decoder for accessing at least one cell along said selected access wordline using said corresponding access bitline; andprecharging circuitry for precharging said access bitlines concurrent with refreshing of a said row of cells using a corresponding refresh bitline and precharging said refresh bitlines concurrent with accessing selected cells of a selected one of said rows using corresponding ones of said access bitlines .