Patent ID: 7054219
Filing Date: 2006-05-30
Classification: G11C,H01L

Abstract:
1. An integrated circuit comprising: a memory array comprising a plurality of memory blocks, said memory array having a plurality of array lines traversing horizontally across at least one memory block; a plurality M of vertical active area stripes disposed at least partially beneath a first memory block; a respective plurality of gate electrodes intersecting each respective active area stripe to define individual source/drain regions, every other source/drain region being coupled to a respective bias node for the respective active area stripe, and remaining source/drain regions being respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line; and a connection area along one side of the first memory block for making a vertical connection from a respective array line associated with the first memory block to a respective electrode on a lower interconnection level which is coupled to the corresponding first driver transistor for said array line.