Patent ID: 6084484
Filing Date: 2000-07-04
Classification: H03K

Abstract:
A programmable digital frequency divider, comprising:an oscillating circuit with a crystal for providing an oscillating signal at a system frequency;a preset code memory for storing a set of preset codes, wherein each of the preset codes is associated with the ratio between an output frequency to be supplied by the frequency divider and the system frequency;a programmable preset code loader for loading and latching one of the preset codes from the preset code memory and then supplying a latched preset code;register means having a first input terminal coupled to the oscillating circuit for receiving the oscillating signal from the oscillating circuit, a second input terminal, a current value output termnal for supplying a current value registered in the register, and a clock signal output terminal;adding means for adding the latched preset code from the programmable preset code loader and the current value from the current value output terminal of the register and thereby supplying a resultant value to the second input terminal of the register; andaccumulating means provided in said register means which accumulates the resultant value from the adding means to the oscillating signal generated by the oscillating circuit and then supplies an output clock signal at the clock signal output terminal of the register;wherein:(a) the preset code is a binary code determined by the following formula: ##EQU7## wherein N is the number of bits of the preset code; (b) said register means comprises N register, said adder means comprises N addres, and said N registers are connectes to said N addres, respectively;'(c) each adder contains first input means to receive a corresponding ""0"" or ""1"" binary bit from said preset code loader; and(d) said preset code, said adder means, said register means and said accumulating means collectively convert the system frequency to an output frequency according to the following equation: ##EQU8##