Patent ID: 7943461
Filing Date: 2011-05-17
Classification: H01L

Abstract:
1. A method for manufacturing a high-voltage semiconductor device, comprising: forming a first N type well in the semiconductor substrate; forming (i) one or more second N type wells in the first N type well and (ii) a third N type well in the semiconductor substrate outside the first N type well; forming a first P type well in a central portion of the first N type well such that the first P type well is isolated from the second N type well(s), the second N type well(s) being along a periphery of the first P type well; after forming the first P type well, forming a second P type well in the semiconductor substrate outside the first N type well, wherein the first P type well and the second P type well have a same concentration; forming a gate insulating film and a gate electrode on the first P type well; and forming first heavily-doped N type impurity regions in the first P type well at opposite sides of the gate electrode.