Patent ID: 9007049
Filing Date: 2015-04-14
Classification: G05F

Abstract:
1. A current source circuit with temperature compensation, comprising: a power supply terminal; a reference current source unit connected to said power supply terminal; a feedback control unit connected to said power supply terminal and said reference current source unit; a current source generating unit connected to said feedback control unit; and a ground terminal connected to said current source generating unit; wherein said reference current source unit is a current source connected to said power supply terminal; said feedback control unit comprises a first switching element, connected to a first terminal of said current source, and an inverting amplifier, connected between a second terminal of said current source and said first switching element; and said current source generating unit comprises a second switching element which is connected to said first switching element, said current source and said inverting amplifier, and a first resistor which is connected to said first switching element, said second switching element and said ground terminal; wherein said first switching element is a first field effect transistor (FET) and said second switching element is a second FET, wherein further said first FET is a PMOS and said second FET is an NMOS; wherein said inverting amplifier comprises a third FET which is connected to said second FET, and a fourth FET which is connected to said third FET; a gate electrode of said first FET is connected to a drain electrode of said third FET and a drain electrode of said fourth FET; and a drain electrode of said first FET is connected to a first terminal of said first resistor and a gate electrode of said second FET; and wherein said current source comprises a fifth FET, a sixth FET, a seventh FET, an eighth FET, a ninth FET, a second resistor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, an eighth diode and a ninth diode; a drain electrode of said second FET and a drain electrode of said fifth FET are both connected to a gate electrode of said third FET; a gate electrode of said fifth FET, a gate electrode of said sixth FET, a drain electrode of said eighth FET and a gate electrode and a drain electrode of said ninth FET are all connected to a gate electrode of said fourth FET; a drain electrode of said sixth FET and a gate electrode and a drain electrode of said seventh FET are all connected a gate electrode of said eighth FET; a source electrode of said seventh FET is connected to an input terminal of said first diode; a source electrode of said eighth FET is connected to a first terminal of said second resistor; and an input terminal of said second diode, an input terminal of said third diode, an input terminal of said fourth diode, an input terminal of said fifth diode, an input terminal of said sixth diode, an input terminal of said seventh diode, an input terminal of said eighth diode and an input terminal of said ninth diode are all connected to a second terminal of said second resistor.