Patent ID: 6564301
Filing Date: 2003-05-13
Classification: G06F

Abstract:
A data processing apparatus, comprising:a cache having a plurality of cache lines for storing data values retrieved from a plurality of memory regions of a memory, a first memory region being such that when a data value from that first memory region is stored in the cache and is subsequently updated within the cache by a new data value, the new data value is not transferred to memory until that new data value is removed from the cache; a marker associated with each cache line and being settable to indicate that the data values stored in the corresponding cache line are from said first memory region; a protection unit for determining control parameters for controlling the transfer of data values between the cache and the memory, and being arranged, when said data values are to be loaded from the memory into a cache line of the cache, to determine whether said data values are from said first memory region and to cause the marker to be set accordingly; and a processor core arranged to output a new data value for storage; the cache being arranged to determine if the new data value output by the processor core is to replace a data value stored in a cache line of the cache, and if so to update the corresponding cache line with the new data value, and to apply predetermined criteria to determine whether to set an update identifier indicating that the data value has been updated by the new data value, such that when the new data value is subsequently removed from the cache it can be determined whether to transfer that new data value to the memory.