Patent ID: 7787273
Filing Date: 2010-08-31
Classification: H02M

Abstract:
1. An inverter circuit, comprising: a direct current input terminal connected to a direct current power supply; a first transformer comprising a first primary winding, a second primary winding, and a secondary winding configured for outputting an alternating current voltage; a second transformer comprising a third primary winding, a fourth primary winding, and a secondary winding configured for outputting an alternating current voltage; a pulse width modulation circuit comprising a first output terminal to output a first square wave signal and a second output terminal to output a second square wave signal with an inverse phase relative to the first square wave signal; a first switch circuit comprising a first transistor and a second transistor; and a second switch circuit comprising a third transistor and a fourth transistor; wherein a gate electrode of the first transistor is connected to the first output terminal, and a source electrode of the first transistor is connected to ground; a gate electrode of the second transistor is connected to the second output terminal, and a source electrode of the second transistor is connected to ground; a gate electrode of the third transistor is connected to the first output terminal, and a source electrode of the third transistor is connected to ground; a gate electrode of the fourth transistor is connected to the second output terminal, and a source electrode of the fourth transistor is connected to ground; a drain electrode of the third transistor is connected to a drain electrode of the first transistor, and a drain electrode of the fourth transistor is connected to a drain electrode of the second transistor; the first primary winding and the second primary winding share a first tap, the first tap is connected to the direct current input terminal, the other tap of the first primary winding is connected to the drain electrode of the first transistor, and the other tap of the second primary winding is connected to the drain electrode of the second transistor; and the third primary winding and the fourth primary winding share a second tap, the second tap is connected to the direct current input terminal, the other tap of the third primary winding is connected to the drain electrode of the first transistor, and the other tap of the third primary winding is connected to the drain electrode of the second transistor.