Patent ID: 6103581
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method for isolating selected areas on an integrated circuit semiconductor device with trench filled isolation structures having reduced edge leakage comprising;forming a a surface oxide layer on a top surface of a monocrystalline semiconductor body;forming a non-crystalline silicon buffer layer on the top surface of said surface oxide layer;anisotropically forming openings said non-crystalline silicon layer and said surface oxide layer and forming underlying trenches around selected areas in said semiconductor body;forming a lining oxide layer on the surfaces of said trenches, on the side walls of said openings in said moncrystalline layer, and on the remaining top surface of said moncrystalline silicon layer;filling said trenches and covering said moncrystalline silicon buffer layer with an anisotropically deposited second sillcon oxide layer;removing portions of said second oxide layer and portions of said moncrystalline silicon layer by chemical mechanical polish planarizing to a level above the surface of said surface oxide layer, leaving a portion of said overlying monocrystalline silicon layer;selectively removing the exposed silicon layer thereby exposing the underlying surface oxide layer; andanisotropically removing the exposed surface oxide layer portions on said semiconductor body.