Patent ID: 7333200
Filing Date: 2008-02-19
Classification: G03F,H01L

Abstract:
1. A method of controlling the lithography process used to fabricate patterns on layers of a semiconductor wafer comprising the steps of: providing at least two scatterometry targets on said wafer, each target having a first pattern formed in an upper layer aligned with a second pattern formed in a lower layer, said targets for diffracting light; optically inspecting the targets to determine the optical response of the targets; creating a theoretical model for each target, said models including a plurality of unknown parameters defining the target and wherein at least one of the parameters is common to each of the targets; performing a regression analysis wherein the measured optical response of the targets is compared to calculated optical responses of the targets generated by varying the values of the parameters applied to the models, said regression analysis including maintaining a common value for the common parameter, said regression analysis producing a best fit for a combination of the models; and using the result of the regression analysis to control the lithography process.