Patent ID: 9070433
Filing Date: 2015-06-30
Classification: G11C

Abstract:
1. A method to generate timing control for an SRAM circuit operating with dual power supplies, the method comprising: generating a voltage signal by a programmable local clock buffer that receives power from a first voltage level; shifting the voltage signal higher by a level shifter that receives power from both the first voltage level and a second voltage level; delaying the voltage signal by a delay clock chopper circuit that receives power from the second voltage level, the delay clock chopper circuit including a programmable pulse width variation circuit; varying a pulse width of the voltage signal by the programmable pulse width variation circuit that receives power from the second voltage level; and driving a global bitline of the SRAM circuit with the voltage signal, the voltage signal having timing sensitive to both the first voltage level and the second voltage level and the pulse width sensitive to the second voltage level.