Patent ID: 8415735
Filing Date: 2013-04-09
Classification: H01L

Abstract:
1. A dual conductive floating spacer memory cell, comprising: a semiconductor substrate having impurities of a first conductivity type, the semiconductor substrate having a first surface at which is formed a first source/drain region, a second source/drain region and a channel region between the first source/drain region and the second source/drain region, each of the first and second source/drain region having impurities of a second conductivity type; a control gate formed above the channel region, electrically isolated therefrom by a gate dielectric layer; a first conductive floating spacer and a second conductive floating spacer each having a first side and a second side, each conductive floating spacer being formed adjacent the control gate on the first side and each being electrically isolated by a dielectric layer from the control gate, such that the control gate and the dielectric layer form a substantially vertical sidewall on the second side of each of the first and second conductive floating spacers, the first and second conductive floating spacers being formed above the channel region and overlapping the first and second source/drain regions, respectively, each separated therefrom by a tunnel oxide region; and dielectric spacers formed along the substantially vertical sidewalls.