Patent ID: 8689166
Filing Date: 2014-04-01
Classification: G06F

Abstract:
1. A modeling method comprising: accessing, by a computer from a memory, a design for a multi-fin field effect transistor, said multi-fin field effect transistor comprising: determining, by said computer, a first total parasitic resistance associated with a first source/drain region of said multi-fin field effect transistor on said first side of said gate structure and a second total parasitic resistance associated with a second source/drain region on said second side of said gate structure, said first total parasitic resistance comprising being equal to a sum of the following: representing, by said computer in a netlist, said multi-fin field effect transistor as a simple field effect transistor; and representing, by said computer in said netlist, said first total parasitic resistance by a first resistive element connected to a first source/drain node of said simple field effect transistor and said second total parasitic resistance by a second resistive element connected to a second source/drain node of said simple field effect transistor.