Patent ID: 7379068
Filing Date: 2008-05-27
Classification: G09G

Abstract:
1. A memory system for a graphics processing system having a graphics processing pipeline for processing pre-processed graphics data to generate post-processed graphics data, the memory system having: at least three memory banks for storing graphics data, each of the memory banks having command and address terminals and further having data output terminals and data input terminals, each memory bank configured to provide read data at the data output terminals and store write data provided to the input data terminals responsive to command and address signals applied to the command and address terminals; a read data bus coupled to the output data terminals; a write data bus coupled to the input data terminals; a pre-processed data buffer having an input coupled to the read data bus and an output coupled to the graphics processing pipeline, the read buffer configured to temporarily store pre-processed graphics data read from a memory bank and provide the same to the graphics processing pipeline; a post-processed data buffer having an input coupled to the graphics processing pipeline and further having an output coupled to the write data bus, the post-processed data configured to temporarily store the post-processed graphics data and provide the same to the output to be written to the memory banks; and a memory controller coupled to the command and address terminals of the memory banks, the memory controller configured to generate command and address signals to coordinate reading pre-processed graphics data from a first of the memory banks concurrently with writing post-processed graphics data to a second of the memory banks, the post-processed graphics data written to the same locations in the second of the memory banks from which the corresponding pre-processed graphics data was originally read.