Patent ID: 7093209
Filing Date: 2006-08-15
Classification: G01R,H01L

Abstract:
1. A method for testing the design of an integrated circuit (system IC) comprising the steps of: (a) designing the system IC to have a predetermined number and pattern for its chip I/O pads; (b) designing a packaging module to fan-out the I/O of the system IC to an expanded pitch of packaging I/O pads having a correspondence to said chip I/O pads; (c) partitioning circuitry of said system IC into a functional circuit; (d) designing said functional circuit as a corresponding test IC, wherein said test IC I/O pads conform to one of a sub-set of the number and pattern of said chip I/O pads; (e) attaching said test IC to said packaging module with conductive material; (f) exercising said test IC by applying signals and power to inputs of said packaging module at packaging I/O pads corresponding to said sub-set of chip I/O pads; and (g) collecting test data corresponding to said test IC.