Patent ID: 7705647
Filing Date: 2010-04-27
Classification: H03K

Abstract:
1. A device comprising: a first circuit configured to adjust duty cycle of an input clock signal based on a common control voltage and provide an output clock signal having adjustable duty cycle; and a second circuit configured to detect error in the duty cycle of the output clock signal and to generate the common control voltage in response to the detected error in the duty cycle; wherein the first circuit comprises a first inverter and a second inverter configured to adjust the duty cycle of the input clock signal, a pull-up transistor coupled to the first inverter and configured to adjust rising edge slew rate of the first inverter based on a first control voltage, and a pull-down transistor coupled to the first inverter and configured to adjust falling edge slew rate of the first inverter based on a second control voltage; and the second circuit comprises a control generator configured to generate the first and second control voltages as level shifted versions of the common control voltage, the first control voltage being lower than the second control voltage.