Patent ID: 6401226
Filing Date: 2002-06-04
Classification: G01R

Abstract:
An electronic system with a self-test function comprising:a pseudo-random test pattern generator for serially outputting data constituting a pseudo-random test pattern; a scan-path circuit for capturing the pseudo-random test pattern by receiving the data serially output from the pseudo-random test pattern generator, for supplying the pseudo-random test pattern in parallel to a tested circuit, for receiving in parallel an operation result of the tested circuit, and for serially outputting data constituting the operation result; a data compression circuit for compressing the operation result by receiving the data serially output from said scan-path circuit; and a memory for storing, when said pseudo-random test pattern generator begins to serially output the data constituting the pseudo-random test pattern, a seed of a 1-bit shifted pseudo-random test pattern that is obtained by shifting the pseudo-random test pattern that is obtained by shifting the pseudo-random test pattern by one bit, wherein said pseudo-random test pattern generator serially supplies said scan-path circuit with data constituting the 1-bit shifted pseudo-random test pattern when said scan-path circuit loads the operation result of the tested circuit in parallel.