Patent ID: 6169011
Filing Date: 2001-01-02
Classification: H01L

Abstract:
In an integrated circuit, a method for isolating transistors on a silicon substrate with a trench structure, the method comprising the steps of: a) forming a layer of gate insulator material having a first uniform thickness overlying the silicon substrate; b) forming a first layer of gate electrode material having a surface and a second thickness overlying the date insulator layer; c) etching a predetermined area of the silicon substrate, to form a trench having a third thickness, through the overlying gate insulator and first gate electrode layers, and forming a trench with first gate electrode sidewalls, which overlie gate insulator sidewalls, which overlie silicon substrate sidewalls; d) oxidizing exposed surfaces to a fourth thickness, including the silicon substrate sidewalls and first gate electrode sidewalls of the trench; e) filling the trench with oxide; f) planarizing to remove oxide and a portion of the first gate electrode material from the surface of the first gate electrode layer, forming a first gate electrode layer fifth thickness, whereby a uniformly thick gate insulator is formed; g) depositing a second layer of gate electrode material, of the same material as the first gate electrode layer, having a sixth thickness overlying the surface of the first gate electrode layer and the oxide-filled trench; and h) selectively etching a predetermined area of the second gate electrode layer, and underlying first gate electrode layer to form a gate electrode overlying predetermined areas of the gate insulator layer and trench, whereby a transistor gate electrode is formed with a large breakdown voltage and low leakage currents.