Patent ID: 6618801
Filing Date: 2003-09-09
Classification: G06F

Abstract:
A method for implementing two architectures on a chip, comprising:decoding a macroinstruction into one or more microinstructions, through the use of an emulation engine, converting the one or more microinstructions into a bundle, using a bundler, the bundle having at least one syllable and having a template that specifies a type of data included in the bundle, wherein the emulation engine delivers a pre-decode bit to the execution engine along with the bundle, and wherein the bundler receives at least one sequence of instructions (an â€œXUOPâ€ ), determines how many of the at least one XUOP are received, and when more than one XUOP is received, determines whether the XUOPs must be issued in parallel, and when the XUOPs must be issued in parallel, issues a plurality of the bundles containing the XUOPs to the execution engine in parallel, when the XUOPs need not be issued in parallel, determines whether a particular problem exists, and when the problem does not exist, dispatches a plurality of the bundles containing the XUOPs to the execution engine in parallel, when the problem does exist, dispatches a plurality of the bundles containing one of the XUOPs to the execution engine, when only one XUOP is received, determines whether the one XUOP must be issued in parallel with another XUOP, and when the one XUOP must be issued in parallel, dispatches nothing to the execution engine, when the one XUOP need not be issued in parallel, dispatches the bundle containing the one XUOP to the execution engine, and dispatching the bundle to an execution engine together with a pre-decode bit.