Patent ID: 7617340
Filing Date: 2009-11-10
Classification: G06F

Abstract:
1. A method of isolating a plurality of I/O adapter units of a data processing system, said data processing system comprising a set of processors, content addressable memory (CAM), and a translation validation table (TVT), said method comprising: the processors assigning to each of the I/O adapter units a respective identifier; the I/O adapter units sending memory requests to the set of processors, each request including said respective identifier; the processors indexing in the TVT a memory space requested by said each request based on an index value provided by the CAM in response to the respective identifier; and the processors using the respective identifier as an index into the TVT pointing to translation validation entries (TVE) containing a translation address register (TAR) comprising a base address to identify a unique and independent memory space in system memory associated with the one of I/O adapter units.