Patent ID: 8841766
Filing Date: 2014-09-23
Classification: H01L

Abstract:
1. An integrated circuit device, comprising: a semiconductor substrate; a pad region formed on the semiconductor substrate; a first under-bump-metallurgy (UBM) layer formed on the pad region, wherein sidewalls of the first UBM layer; a second UBM layer formed on the first UBM layer and having a sidewall surface, wherein an area of the first UBM layer is greater than an area of the second UBM layer; a conductive pillar formed on the second UBM layer, and having a sidewall surface and a top surface; and a protection structure formed on the sidewall surface of the conductive pillar and an entirety of the sidewall surface of the second UBM layer, without covering the sidewalls of the first UBM layer; wherein the protection structure is formed of a non-metal material, and the conductive pillar is formed of a copper-containing layer.