Patent ID: 6816425
Filing Date: 2004-11-09
Classification: G11C

Abstract:
A two-stage memory device control circuit comprising:a first signal node disposed on a first side of an array of memory devices; a second signal node disposed on a second side of said array of memory devices; a first logic gate circuit having a first output coupled to said first signal node; a second logic gate circuit having a second output coupled to said second signal node; a third logic gate circuit having a third output coupled to a first input of said first logic gate circuit; a fourth logic gate circuit having a fourth output coupled to a second input of said second logic gate circuit; a section selection signal node mutually coupled to a third input of said third logic gate circuit and to a fourth input of said fourth logic gate circuit; and a global signal node mutually coupled to a fifth input of said third logic gate circuit and to a sixth input of said fourth logic gate circuit, wherein said global signal node is signalingly equidistant from said fifth and sixth inputs.