Patent ID: 7287142
Filing Date: 2007-10-23
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of word lines; an arbiter configured to receive a first entry signal for entering the first access mode and a second entry signal for entering the second access mode, to determine priority of the first and second access modes, and to generate a first mode trigger signal corresponding to a first entry mode and a second mode trigger corresponding to a second entry mode; and a signal generating circuit, configured to generate an internal operation signal in accordance with at least one of the first mode trigger signal and the second mode trigger signal, wherein the arbiter gives priority to the first access mode when the arbiter receives the first entry signal during the time after the second entry signal is supplied and before a predetermined word line of the plurality of word lines is enabled in the second access mode. wherein the predetermined period comprises a period from a point at which the second entry signal is enabled to a point at which a predetermined word line of the plurality of word lines is enabled in the second access mode.