Patent ID: 8324603
Filing Date: 2012-12-04
Classification: G02B,Y10T

Abstract:
1. A system for galvanic isolation of a first electrical system formed in a semiconductor substrate and that includes first electrical circuitry that operates at a first voltage level and a second electrical system formed in the semiconductor substrate and that includes second electrical circuitry that operates at a second voltage level that is different than the first voltage level, the system comprising: a dielectric galvanic isolation barrier formed in the semiconductor substrate between the first electrical system and the second electrical system; one or more optical emitters formed in the semiconductor substrate as part of the first electrical system and that generate light pulses that are transmitted through the dielectric galvanic isolation barrier to the second electrical system; one or more optical receivers formed in the semiconductor substrate as part of the second electrical system and adapted to receive the light pulses transmitted through the dielectric galvanic isolation barrier; a clock generator formed in the semiconductor substrate as part of the first electrical system and that provides a clock signal to the one or more optical emitters to define the light pulses generated by the one or more optical emitters; power circuitry formed in the semiconductor substrate as part of the first electrical system and that provides a power signal; and a transformer structure formed on the semiconductor substrate and adapted to transmit the clock signal and the power signal from the first electrical system to the second electrical system.