Patent ID: 6667511
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A NAND-type flash memory device, comprising:a core region comprising a stacked gate flash memory cell structure and a select gate transistor; and a periphery region comprising a low voltage transistor and a high voltage transistor, wherein the stacked gate flash memory cell structure includes a tunnel oxide layer, a poly1 layer overlying the tunnel oxide layer, an interpoly dielectric layer formed of an insulating material overlying the poly1 layer, and a poly2 layer overlying the interpoly dielectric layer, and wherein the select gate transistor structure includes a gate insulator formed of the same insulating layer used to form the interpoly dielectric layer, thus providing for the formation of the interpoly dielectric layer and the gate insulator in a single formation step, and a gate electrode formed of the poly2 layer overlying the gate insulator.