Patent ID: 6742074
Filing Date: 2004-05-25
Classification: G06F

Abstract:
A method to operate a computer system bridge circuit comprising:enqueueing a plurality of delayed read requests, wherein each read request is associated with a peripheral component interconnect device; retrieving data, by a memory interface in the bridge circuit, from system memory in response to the delayed read requests; and performing arbitration, by an arbiter, of a subsequent request from one of the plurality of peripheral component interconnect devices in response to determining that data for enqueued delayed read request of the one peripheral component interconnect device has been retrieved by the memory interface from the system memory, but not performing arbitration, by the arbiter, of the subsequent request received by the arbiter from the one peripheral component interconnect device in response to determining that data for the enqueued delayed read request of the one peripheral component interconnect device has not been retrieved by the memory interface from the system memory.