Patent ID: 8035355
Filing Date: 2011-10-11
Classification: G01R,H02J,H03K

Abstract:
1. A charge-controlling semiconductor integrated circuit comprising: a current-controlling MOS transistor connected between a voltage input terminal and an output terminal, which current-controlling MOS transistor controls current flowing from the voltage input terminal to the output terminal; a current detection circuit including a current-detecting MOS transistor of 1/N size of the current-controlling MOS transistor, a source terminal of which current-detecting MOS transistor is connected to a source terminal of the current-controlling MOS transistor, and to a gate terminal of which current-detecting MOS transistor, gate voltage same as gate voltage of the current-controlling MOS transistor is applied; and a gate voltage control circuit to control the gate voltage of the current-controlling MOS transistor depending on a current value detected by the current detection circuit, wherein the current detection circuit includes an operational amplifier circuit to which drain voltage of the current-controlling MOS transistor and drain voltage of the current-detecting MOS transistor are input, the current detection circuit is configured so that a bias condition of the current-detecting MOS transistor becomes same as a bias condition of the current-controlling MOS transistor based on an output of the operational amplifier circuit, the current detection circuit is set so that voltage drops in lines from drain electrodes of the current-controlling MOS transistor and the current-detecting MOS transistor to a corresponding input point of the operational amplifier circuit become the same by a parasitic resistance, the current detection circuit includes a bias condition controlling transistor which is connected between the current-detecting MOS transistor and a current-voltage conversion member connected to a ground point, the current detection circuit is configured so that when the output of the operational amplifier circuit is applied to a control terminal of the bias condition controlling transistor, the drain voltages of the current-controlling MOS transistor and the current-detecting MOS transistor become the same potential, and the line from the drain electrode of the current-detecting MOS transistor to the input point of the operational amplifier circuit is formed to be redundantly arranged inside the chip so that a parasitic resistance becomes a predetermined value.