Patent ID: 6905946
Filing Date: 2005-06-14
Classification: H01L

Abstract:
1. A method for a semiconductor wafer in a manufacturing process during the manufacture of semiconductor dice thereon, said semiconductor wafer having an active surface and an inactive surface, said active surface having a plurality of circuitry elements forming a plurality of semiconductor dice thereon, at least one semiconductor die of said plurality of semiconductor dice formed on said active surface of said semiconductor wafer having a plurality of spaced apart bond pads located on an active surface thereof; said method comprising: forming electrically conductive bumps on at least some of said plurality of spaced apart bond pads on said active surface of said at least one semiconductor die of said plurality of semiconductor dice on said active surface of said semiconductor wafer, said electrically conductive bumps having a height thereof extending above said plurality of spaced apart bond pads on said active surface of said at least one semiconductor die of said plurality of semiconductor dice; covering a portion of said height of said electrically conductive bumps; applying a structurally supportive compound to at least a portion of said active surface of said semiconductor wafer, said structurally supportive compound being disposed between at least some of said electrically conductive bumps configured to expose a portion of said height of said electrically conductive bumps to extend above said structurally supportive compound for connecting said electrically conductive bumps to at least one circuit of a substrate; and subjecting said inactive surface of said semiconductor wafer to a thinning process.