Patent ID: 6010959
Filing Date: 2000-01-04
Classification: H01L,Y10S

Abstract:
A method of forming a contact or via of an integrated circuit, comprising the steps of:forming a first dielectric layer on the integrated circuit wherein the dielectric layer has a dopant concentration sufficient to allow the layer to be reflowed at a temperature between approximately 850.degree. C. and 900.degree. C., including approximately a 2-4% boron concentration and approximately a 4-7% phosphorus concentration; andforming a second undoped dielectric layer on the first dielectric layer;forming and patterning a photoresist layer on the second undoped oxide layer; andforming an opening in the first and second dielectric layers exposing a portion of an underlying conductive structure wherein a portion of the dielectric layers has outwardly sloping sidewalls at the opening.