Patent ID: 7170776
Filing Date: 2007-01-30
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a plurality of memory cells arranged in a matrix, and each having an electric resistance varying according to storage data written in a non-volatile manner by a data write current; a plurality of word lines provided corresponding to memory cell rows respectively; a plurality of bit lines provided corresponding to memory cell columns respectively; and a control circuit for conducting one of data write operation and data read operation wherein each of data write operation and data read operation is divided into a plurality of cycles, said control circuit conducts a part of said one of data write operation and data read operation in each of said cycles by pipeline processing, in response to activation of a word line corresponding to a selected memory cell row, memory cells of the selected memory cell row are electrically coupled to corresponding bit lines respectively, and said non-volatile memory device further comprises a mask circuit for stopping, in response to an instruction, a part of passing currents flowing respectively through said corresponding bit lines that are electrically coupled to said memory cells respectively of said selected memory cell row.