Patent ID: 6380798
Filing Date: 2002-04-30
Classification: H03K

Abstract:
A semiconductor device comprising:a circuit including a PMOS transistor and a NMOS transistor; a power supply voltage control circuit for supplying first and second power supply voltages to said PMOS transistor and said NMOS transistor, the second power supply voltage being lower than the first power supply voltage; and a substrate bias control circuit for supplying a first substrate bias voltage to said PMOS transistor and a second substrate bias voltage to said NMOS transistor; wherein the gate oxide thickness of said PMOS transistor and said NMOS transistor are not more than 5 nm; wherein in a first mode, said substrate bias control circuit controls the first substrate bias voltage being a first voltage and the second substrate bias voltage being a second voltage, and said power supply voltage control circuit controls the first power supply voltage being a third voltage and the second power supply voltage being a fourth voltage; wherein in a second mode, the first substrate bias voltage is controlled by said substrate bias control circuit to a voltage higher than the first voltage, the second substrate bias voltage is controlled by said substrate bias control circuit to a voltage lower than the second voltage, and said power supply voltage control circuit controls said first power supply voltage to a voltage lower than the third voltage, wherein in said second mode, said power supply voltage control circuit controls said second power supply voltage being the fourth voltage.