Patent ID: 9040416
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, comprising: forming a first lower layer on a substrate; forming a first middle layer on the first lower layer; forming a first upper layer on the first middle layer; forming a photoresist pattern on the first upper layer using a first developing process; forming a first signal line by etching the first upper layer, the first middle layer, and the first lower layer by using the photoresist pattern as a mask; forming a thin film transistor connected to the first signal line; forming a second signal line connected to the thin film transistor; and forming a first electrode connected to the second signal line, wherein: the first upper layer covers an end of the first middle layer; the first lower layer, the first middle layer, and the first upper layer are formed in a sputtering device including a mask aligned with edges of the substrate; the mask is aligned to overlap the substrate by a first width when forming the first middle layer; the mask is aligned to overlap the substrate by a second width when forming the first upper layer; and the first width is less than the second width.