Patent ID: 8168537
Filing Date: 2012-05-01
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor component, comprising the steps: providing a substrate; depositing a resist layer on the substrate; fabricating a one-dimensional or two-dimensional array of openings in the resist layer, which are laterally separated from each other, thus defining shapes of a one-dimensional or two-dimensional array of sub-electrodes of a projecting electrode to be fabricated, at least a first of said openings exposing an electrical connection to an electronic circuit element on the substrate and at least a second of said openings being electrically isolated from any electronic circuit element on the substrate; depositing an electrically conductive electrode material in the array of openings, thus forming the sub-electrodes of the projecting electrode, at least one of said sub-electrodes being formed on the first of said openings and at least another one of sub-electrodes being formed on the second of said openings; and removing the resist layer and providing an electrically insulating fluid between the sub-electrodes.