Patent ID: 6284626
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method for fabricating a filled isolation trench as part of an integrated circuit on a semiconductor wafer, the method including the steps of:A. etching an isolation trench within a layer of semiconductor material, said isolation trench having at least one side wall comprised of said semiconductor material, and said isolation trench having a bottom wall, wherein said step A further includes the steps of:depositing a nitride layer onto said layer of semiconductor material; andetching said isolation trench in said layer of semiconductor material through said nitride layer;B. implanting nitrogen ions into said at least one side wall of said isolation trench and etching said nitride layer away from said layer of semiconductor material;C. thermally growing simultaneously a layer of an insulator material from said at least one side wall and said bottom wall of said isolation trench and a pad oxide layer onto said layer of semiconductor material; andD. filling said isolation trench with said insulator material using a deposition process to form said filled isolation trench,wherein said nitrogen ions implanted into said at least one side wall of said isolation trench reduces a radius of a bird's beak formed on said at least one side wall of said isolation trench, andwherein said nitrogen ions implanted into said at least one side wall of said isolation trench reduces mechanical stress on said at least one side wall of said isolation trench from said insulator material filling said isolation trench.