Patent ID: 6498502
Filing Date: 2002-12-24
Classification: G01R,Y10S

Abstract:
A method for evaluating properties of a semiconductor device comprising:a. forming a plurality of semiconductor devices on a semiconductor substrate, the devices having geometric dimensions, the geometric dimensions being formed according to design rules including a minimum design rule, at least one of the devices having at least one geometric dimension approximately equaling the minimum design rule; b. measuring an electrical property of the plurality of devices related to a selected geometric dimension using a scanning probe microscopy based technique, the measurement being associated with the selected geometric dimension, including the dimension approximately equaling the minimum design rule; c. determining a relationship between the measured electrical property and the selected geometric dimension of the plurality of semiconductor devices; d. determining a relationship between the measured electrical property and at least one semiconductor fabrication process; and e. evaluating the semiconductor fabrication process based on the relationship between the measured electrical property and the geometric dimension of the semiconductor devices.