Patent ID: 6901118
Filing Date: 2005-05-31
Classification: H03M

Abstract:
1. A decoder system, comprising: a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit, wherein the cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory, wherein an ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto; and a Traceback unit including a partial pretraceback for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions, wherein an ACS data path is widened to receive a Yamamoto quality flag for determining whether an encoded frame contains an error or for use in subsequent quality processing, and wherein said partial pretraceback performs a partial traceback for each trellis stage prior to storing the oath decision information for later traceback completion.