Patent ID: 8607116
Filing Date: 2013-12-10
Classification: H03M

Abstract:
1. A readdressing decoder for decoding a quasi-cyclic low-density parity-check (QC-LDPC) code, comprising: a memory that stores a QC-LDPC matrix comprising a plurality of sub-matrices each having a corresponding address; a controller that respectively readdresses the sub-matrices into a plurality of divided matrices, and defines the divided matrices into a first address group or a second address group; and a plurality of parallel processors, coupled to the controller, that performs a correction process on the divided matrices of the first address group and the divided matrices of the second address group to generate a first correction result and a second correction result; wherein, a ratio between a number of the divided matrices of the first address group or a number of the divided matrices of the second address group and a number of the parallel processors is an integer.