Patent ID: 6412097
Filing Date: 2002-06-25
Classification: G06F

Abstract:
A method of compacting a circuit layout having a plurality of layers on which moving objects form layer patterns, the moving objects comprising components and wires, ones of the wires being laid on the respective layers in bundles to form wire bundles, each of the wires having a wire width and a pattern shape as a wire pattern shape, each of the wire bundles having a pattern shape as a bundle pattern shape and a bundle width defined by a total width of wires of each wire bundle, said method comprising, for each of the layer patterns on each of the layers:assuming a graph problem where a graph comprises nodes corresponding to the components and edges corresponding to moving vectors of the components under first through fourth condition; the first condition being that the wire widths of the wires are fixed at constant wire width values; the second condition being that belt widths of wire belts are fixed at constant belt width values, the wire belts defined by adding predetermined margins to both sides in a width direction of each of the wire bundles in compliance with a design rule, each of the belt widths being equal to a sum of each of the bundle widths and the predetermined margins; the third condition being that component-wire spaces are variable, each of the component-wire spaces being defined to be a distance from the component to edges in the width direction of the wire belts and/or the wires; and the fourth condition being that wire pattern shape and the bundle pattern shape are changeable for compacting; solving the graph problem to determine a moving order, a moving direction, and a moving distance of each component for moving the components to thereby perform the compacting the circuit layout; and moving each components according to the moving order, the moving direction and the moving distance.