Patent ID: 8799553
Filing Date: 2014-08-05
Classification: G06F,Y02D

Abstract:
1. An electronic device, comprising: a plurality of memory banks having hardware memory locations, wherein at least one of the plurality of memory banks is configured to be selectively deactivated; one or more processors capable of issuing memory requests via physical memory addresses; and a memory controller configured to dynamically map the physical memory addresses to the hardware memory locations using a first mapping equation when three memory banks are active and a second mapping equation when two memory banks are active, wherein the first mapping equation comprises the following relationships: BankIndex=Floor(PAddr/TotalBanks) and DIMMAddr=MOD(PAddr*BankSize, TotalMemory)+BankIndex, where PAddr represents a physical memory address, DIMMAddr represents the hardware memory location to which the physical memory address is mapped when three memory banks of the plurality of memory banks are active, BankSize represents a quantity of physical memory addresses of each of the plurality of memory banks, TotalBanks represents a total number of active memory banks of the plurality of memory banks, and TotalMemory represents a total number of hardware memory locations among the active memory banks of the plurality of memory banks; wherein the second mapping equation comprises the following relationships: where ALT DIMMAddr3 — 2 represents a storage cell to which a physical address is mapped when two memory banks are active, ReducedMemory3 — 2 represents a quantity of hardware memory locations available across the active two memory banks, and ReducedBanks3 — 2 represents a number of the active two memory banks.