Patent ID: 7689770
Filing Date: 2010-03-30
Classification: G06F

Abstract:
1. A cache memory control circuit that controls a cache memory when a cache miss occurs for a first move-in request that precedes a second move-in request to the cache memory and a move-in buffer is being acquired, the circuit comprising: a first determination section that determines, before a tag search, whether a second index and upper address section of a second request address related to the second move-in request do not correspond respectively to a first index and upper address section of a first request address which is related to the preceding first move-in request and which has been registered in the move-in buffer; a tag search section that performs a tag search related to the second move-in request; a second determination section that determines whether an index in the second request address related to the second move-in request and a way in a cache hit and an index in the first request address related to the preceding first move-in request and a replace way in a cache that have been registered in the move-in buffer do not correspond respectively to each other in a case where the tag search section has determined a cache hit; and a first replacing section that replaces a replace destination for the second move-in request in a case where the first determination section determines that the second request address does not correspond to the first request address which has been registered in the move-in buffer and the move-in buffer includes information indicating that the replace destination is a clean victim block that need not to be written back and is valid, wherein the replacing for the second move-in request is continued in a case where the second determination section determines that the index in the second request address related to the second move-in request and the way in the cache hit and the index in the first request address related to the preceding first move-in request and the replace way in the cache that have been registered in the move-in buffer do not correspond respectively to each other.