Patent ID: 6259620
Filing Date: 2001-07-10
Classification: G11C

Abstract:
A content addressable memory, comprising:a matrix of cells having (n+1) columns and m rows, wherein n and m are each integers greater than or equal to 1, and wherein each row of cells comprises:n data storage cells, each comprising:storage logic for storing a respective one of n data signals;an input for receiving a respective one of n comparand data signals; andbit compare logic that generates a bit compare signal that indicates whether the stored one of the n data signals matches the received one of the n comparand data signals;a carry storage cell comprising:a first input for receiving a carry data signal;storage logic for storing the carry data signal;a second input for receiving a carry comparand data signal; andcarry compare logic that generates a carry compare signal that indicates whether the stored carry data signal matches the received carry comparand data signal;word compare logic that generates a word compare signal that indicates whether each of the bit compare signals in the row indicates that the stored one of the n data signals matches the received one of the n comparand data signals and that the carry compare signal in the row indicates that the stored carry data signal matches the received carry comparand data signal; andcarry write logic that generates a carry storage cell write signal only if the word compare signal generated by the word compare logic in a previous row of cells indicates that each of the bit compare signals in the previous row indicates that the stored one of the n data signals matches the received one of the n comparand data signals and that the carry compare signal in the previous row indicates that the stored carry data signal matches the received carry comparand data signal.