Patent ID: 7292091
Filing Date: 2007-11-06
Classification: H03L,H05K,Y10T

Abstract:
1. A method of reducing interference present in a circuit formed on a multi-layer integrated circuit, wherein the circuit includes a conductive trace that carries high frequency digital current, the conductive trace being formed on a first layer of the integrated circuit, the method comprising: placing a first conductive strip in the proximity of the conductive trace to help contain the high frequency digital current flowing through the conductive trace, wherein the first conductive strip is formed on a second layer of the integrated circuit; placing a second conductive strip in the proximity of the conductive trace, wherein the second conductive strip is formed on one of the layers of the multi-layer integrated circuit; and placing a third conductive strip in the proximity of the conductive trace, wherein the third conductive strip is formed on one of the layers of the multi-layer integrated circuit.