Patent ID: 7818878
Filing Date: 2010-10-26
Classification: H01L,H05K,Y10T

Abstract:
1. A method, comprising: folding a foldable area of a substrate having a first plurality of interconnects disposed in a first interconnect area of said substrate and having a second plurality of interconnects disposed in a second interconnect area of said substrate wherein said substrate has a plurality of conductors passing through said foldable area and interconnecting said first interconnect area and said second interconnect area; connecting substrate interconnects of said first substrate interconnect area to interposer interconnects on a first side of an interposer having a core and a plurality of said interposer interconnects disposed within said interposer core; and connecting interconnects of said second substrate interconnect area to said interposer interconnects on a second side of said interposer; wherein the interposer interconnects have a resistance lower than that of the conductors passing though said foldable area and wherein the interposer interconnects have a current carrying capability higher than that of the conductors passing though said foldable area.