Patent ID: 8139011
Filing Date: 2012-03-20
Classification: G02F,G09G

Abstract:
1. A liquid crystal display device comprising: a display part comprising: a plurality of scanning lines arranged in rows, the rows being numbered from the top consecutively starting with 1 and ending with m, a plurality of signal lines arranged in columns, the columns being numbered from the left consecutively staring with 1 and ending with n, switching elements disposed at respective intersections of said scanning lines and said signal lines, a pixel electrode connected to an output end of the respective switching element, counter electrodes capacitively coupled with the respective pixel electrodes, liquid crystal cells disposed between said pixel electrodes and said counter electrodes, thereby defining a matrix of m rows and n columns of pixels, an auxiliary capacitance whose one end is connected to an output end of each of said switching elements, and a plurality of auxiliary capacitance lines arranged in rows, each of the auxiliary capacitance lines being connected to a corresponding row of the auxiliary capacitances; a scanning line driving circuit for providing each row of said scanning lines with a scanning line driving signal having an on time and a holding time in which the switching element in each row can be turned on and off, respectively; a signal line driving circuit for providing a signal line driving signal for each column of said signal lines; a counter electrode driving circuit for providing said counter electrodes with a counter electrode driving signal having a set frequency and a set cycle; and an auxiliary capacitance line driving circuit for providing an auxiliary capacitance line driving signal for each row of said auxiliary capacitance lines, wherein said auxiliary capacitance line driving circuit is adapted to apply a first voltage to the auxiliary capacitance lines in a first half cycle of said counter electrode driving signal during the on time of said scanning line driving signal and apply a second voltage in a (p+½)th cycle after said first half period of said counter electrode driving signal where p is 0 or a natural number, said auxiliary capacitance line driving circuit making the auxiliary capacitance line in a floating condition after said (p+½)th cycle during the remaining holding time.