Patent ID: 7640449
Filing Date: 2009-12-29
Classification: G06F,Y02D

Abstract:
1. A circuit for generating multiple clocks for a computer system, comprising: a first programmable clock divider configured to accept a clock source and output a first clock signal; a first non-programmable divider circuit configured to accept the first clock signal and output a first divided clock signal of a lower frequency relative to the first clock signal; a first switching circuit configured to accept the first divided clock signal and the first clock signal as inputs and output one of the inputs as a first output clock in response to a first switching signal; a second programmable clock divider configured to accept the first clock signal and output a second divided clock signal; a second non-programmable divider circuit configured to accept the second clock signal and output a second divided clock signal of a lower frequency relative to the second clock signal; and a second switching circuit configured to accept as inputs the second divided clock signal and the second clock signal and output one of the inputs as a second output clock in response to a second switching signal.