Patent ID: 6703876
Filing Date: 2004-03-09
Classification: H03L,Y10S

Abstract:
A clock generation system for generating, from a given first reference clock, having a first clock frequency, a second reference clock, having a second clock frequency which is related to said first reference clock frequency by a predetermined ratio, said clock generation system comprising:three PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first reference clock and the last PLL circuit stage outputting said second reference clock, each of said three PLL circuit stages having a first frequency divider for frequency dividing the input thereto by a fixed predetermined frequency division ratio; a second frequency divider for frequency dividing the output of the respective PLL circuit stage by another fixed predetermined frequency division ratio; a phase comparator for comparing the frequency divided output of said first frequency divider and the frequency divided output of said second frequency divider; a filter for filtering the output of said comparator; and a voltage controlled oscillator controlled by the output of said filter for supplying said second frequency divider with a signal having a controlled frequency, wherein said first reference clock, has a 54 MHz High Vision signal system frequency, and said second reference clock, has a 54/1.001 MHz signal frequency which is related to said first reference clock frequency by a predetermined ratio 1000/1001, and wherein, said fixed predetermined frequency division ratios of said first and second frequency dividers are adapted to perform frequency division assigned to the respective PLL circuit stage.