Patent ID: 8095779
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. A method of scheduling execution of an instruction in a processor having at least one cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other, the method comprising: receiving an issue group of instructions; implementing a first prioritization scheme for the issue group of instructions using a class type priority by prioritizing classes of instructions in the order of, from highest to lowest priority: load instructions, floating point instructions, ALU instructions, store instructions, compare instructions, and remaining instructions; implementing a second prioritization scheme for each class of instructions resulting from the first prioritization scheme, in the priority order of the first prioritization scheme, the second prioritization scheme comprising scheduling instructions of the class in descending order of longest dependency chain depth to shortest dependency chain depth in, respectively, a shortest delayed pipeline in the cascaded delayed execution unit to a longest delayed pipeline in the cascaded delayed execution unit; forming target dependencies of all instructions and instruction queues; prioritizing the target dependencies in an upper left most of an instruction queue ensemble; determining a number of pipeline bubbles in undelayed pipelines as from the target dependencies; shifting a pipeline number right until the number of pipeline bubbles becomes less than zero; and executing the issue group of instructions in the cascaded delayed execution pipeline unit.