Patent ID: 6337822
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of write bit lines; a plurality of write word lines; a plurality of write drivers, wherein each of the write drivers is connected to an associated one of the write bit lines, receives input data, a write enable signal and a write masking signal, outputs the input data when the write enable signal is activated and the write masking signal is deactivated, and does not output the input data when the write masking signal is activated; a plurality of MOS transistors, wherein each of the MOS transistors is connected to an associated one of the write bit lines and to an associated one of the write word lines, and gated by a signal applied to the associated write word line; a plurality of latch circuits respectively connected to the plurality of MOS transistors, wherein each of the latch circuits comprises a first inverter and a second inverter, the first inverter having a driving capacity that is larger than that the second inverter; and a plurality of precharge controllers, wherein each of the precharge controllers is connected to an associated one of the write bit lines, receives a precharge signal, and precharges the write bit line to a logic threshold voltage of the first inverter when the precharge signal is activated.