Patent ID: 6031570
Filing Date: 2000-02-29
Classification: H04N

Abstract:
An image acquisition and processing system comprising:a plurality of photo-sensors arranged in an array;a plurality of signal processing devices each periodically coupled to at least one of said photo-sensors, each of said signal processing devices comprising:an integrator containing an operational amplifier, said integrator generating a voltage related to charges applied thereto, said voltage further containing a component related to an offset voltage of said operational amplifier;a dual sampling circuit connected to said integrator and having a first and a second output terminals, said dual sampling circuit sampling voltage generated by said integrator at a first predetermined time interval and generating a first voltage at said first output terminal, said dual sampling circuit sampling voltage generated by said integrator at a second predetermined time interval and generating a second voltage at said second output terminal;a first transistor coupled to said first output terminal of said dual sampling circuit, said first transistor being configured as a source follower, said source follower having a first threshold voltage between its input and output terminals;a second transistor coupled to said second output terminal of said dual sampling circuit, said second transistor being configured as a source follower, said source follower having a second threshold voltage between its input and output terminals, said first and said second threshold voltages having a differential value; andmeans for applying a common voltage to said first and said second transistors for a third predetermined time period; andmeans for coupling one of said photo-sensors to one of said integrators during said second predetermined time period, resulting in said second voltage being related to intensity of radiation received by said one photo-sensor;a first summation device periodically coupled to said first transistor of at least one of said signal processing devices for determining a difference between outputs of said first transistor when said first voltage is applied thereto and when said common voltage is applied thereto;a second summation device periodically coupled to said second transistor of at least one of said signal processing devices for determining a difference between outputs of said second transistor when said second voltage is applied thereto and when said common voltage is applied thereto; anda third summation device for forming a difference between outputs of said first an d said second summation devices, thereby substantially eliminating said differential value.