Patent ID: 7595537
Filing Date: 2009-09-29
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a well region formed in said semiconductor substrate; a transistor-formation region defined in said well region; an electrostatic discharge protection device produced in said transistor-formation region and featuring a multi-finger structure including a plurality of fingers, said fingers respectively including elongated gate electrodes arranged in parallel to each other, a plurality of first regions exhibiting a first conductivity type and a plurality of second regions exhibiting a first conductivity type being alternately arranged with respect to said elongated gate electrodes; a guard-ring formed in said well region so as to surround said transistor-formation region; a well blocking region formed in said well region between said transistor-formation area and said guard-ring, said well blocking region substantially but incompletely surrounding said transistor-formation area; and a substrate resistance determination system associated with said electrostatic discharge protection device and configured to determine a substrate resistance distribution at said transistor-formation area such that snapbacks occur in all said fingers in a chain-reaction manner, and such that occurrence of a latch-up state is suppressed.