Patent ID: 7829998
Filing Date: 2010-11-09
Classification: H01L

Abstract:
1. A semiconductor wafer, comprising: a plurality of semiconductor die each with a plurality of contact pads disposed on a first surface of the semiconductor; a trench formed between the semiconductor die; an organic material deposited in the trench; a plurality of conductive vias formed through the organic material, wherein a width of the conductive vias is less than a width of the organic material in the trench; a plurality of conductive traces formed over the first surface electrically connecting a first portion of the conductive vias to the contact pads, wherein a second portion of the conductive vias is electrically isolated from the conductive traces; a plurality of redistribution layer (RDL) nodes formed over a second surface of the semiconductor die opposite the first surface, the RDL nodes extending across the second surface of the semiconductor die to route electrical signals to areas on the second surface including a central region of the semiconductor die for vertical electrical interconnect, wherein a first portion of the RDL nodes is electrically connected to the conductive vias and a second portion of the RDL nodes is electrically isolated from the conductive vias; and a plurality of repassivation layers formed on the second surface of the semiconductor die for electrical isolation between the RDL nodes.