Patent ID: 7924084
Filing Date: 2011-04-12
Classification: H03K

Abstract:
1. A semiconductor device which comprises an output MOS transistor formed in a semiconductor substrate of a first conductivity type and a diffusion region of a second conductivity type formed in the semiconductor substrate forming a pn-junction therebetween, the semiconductor substrate being connected to a power supply terminal, the diffusion region being connected to a ground terminal, comprising: a switching MOS transistor including a source-drain path connected between a gate and a source of the output MOS transistor, and a gate, the source of the output MOS transistor being connected to an output terminal; an internal ground wire connected between the gate of the switching MOS transistor and the ground terminal; and an electric potential difference generating circuit connected to the internal ground wire and the gate of the switching MOS transistor at a first end thereof and connected to the source of the switching MOS transistor at a second end thereof, wherein the switching MOS transistor is configured to be turned ON when a potential of the internal ground wire is raised due to a parasitic capacitance existing between the power supply terminal and internal ground wire caused by the pn-junction.