Patent ID: 8634466
Filing Date: 2014-01-21
Classification: H04N

Abstract:
1. An apparatus comprising: a decoder that receives control circuitry which receives the prediction mode flag, wherein the prediction mode flag indicates which one of a plurality of intra prediction modes has been selected, said control circuitry providing one or more control signals; computation circuitry coupled to the control circuitry to receive the one or more control signals, said computation circuitry also receiving the prediction macroblock, when a first one of the plurality of intra prediction modes has been selected said computation circuitry performing a first plurality of computations on the prediction macroblock to produce a DCT of the prediction macroblock, when a second one of the plurality of intra prediction modes has been selected said computation circuitry performing a second plurality of computations on the prediction macroblock to produce the DCT of the prediction macroblock, wherein the first plurality of computations and the second plurality of computations are different; and addition circuitry coupled to the computation circuitry to receive the DCT of the prediction macroblock, the addition circuitry adding the DCT of the prediction macroblock to the DCT of a residual macroblock to produce a DCT of the macroblock.