Patent ID: 9202683
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method of forming a transistor device, comprising: forming a gate electrode over a substrate; forming a gate dielectric layer over at least said gate electrode; depositing a functional layer over at least a portion of said substrate, said gate electrode, and said gate dielectric; selectively depositing a patterned contact layer over said functional layer, said patterned contact layer defining first and second electrodes of said active device, wherein said first electrode is a source electrode, said second electrode is a drain electrode; selectively additively depositing, by printing, insulating material over at least a portion of said patterned contact layer to form first and second wall structures such that at least a portion of said patterned contact layer over said first electrode and at least a portion of said patterned contact layer over said second electrode are exposed, said first and second wall structures defining a well region therebetween, and said exposed portions of said patterned contact layer over said first and second electrodes are within said well region; and selectively depositing a semiconductor layer from a solution within said well region such that said first and second wall structures confine said semiconductor layer therein, and said semiconductor layer within said well region is in physical and electrical contact with said exposed portion of said patterned contact layer over said first and second electrodes.