Patent ID: 6018811
Filing Date: 2000-01-25
Classification: G11C

Abstract:
A semiconductor device, comprising:a plurality of primary and redundant circuit elements, the plurality of primary circuit elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality of primary and redundant circuit elements being divided into at least first and second sets wherein primary and redundant circuit elements in the first and second sets are not simultaneously active, wherein the first and second sets of redundant circuit elements can substitute for defective circuit elements in the first and second sets of primary circuit elements, respectively, and wherein the redundant circuit elements are divided into at least a plurality of columns;control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary circuit elements based on the external address word supplied thereto;at least first and second sets of fuse banks for storing addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively; anda number of electrically conductive intercoupling lines equal to a number of columns of redundant circuit elements in the first set of redundant circuit elements, the intercoupling lines being coupled to the first and second sets of fuse banks and to both the first and second sets of redundant circuit elements, and wherein the intercoupling lines are shared by the first and second sets of fuse banks and by first and second sets of redundant elements as the first and second sets of redundant elements are not simultaneously active.