Patent ID: 6560674
Filing Date: 2003-05-06
Classification: G06F

Abstract:
In a multimedia processor, having a plurality of modules including a processor, a main memory, a data cache and a plurality of I/O devices, a data cache system comprises:a cache data memory directly coupled to said processor for providing data to said processor in response to a load operation and for writing data from said processor in response to a store operation; an internally disposed refill controller coupled to said cache data memory for controlling the operation of said cache data memory in accordance with a specifiable policy; an internally disposed external access controller coupled to said cache data memory, said cache data memory operating as a slave, where said external access controller is coupled to an internal memory bus such that the contents of said cache data memory are accessible without the use of the processor for read and write operations in response to read and write request issued by said modules coupled to said internal memory bus; and a data streamer coupled to said cache data memory via an internal bus for mediating external data to said cache data memory, such that modules coupled to said internal bus function as bus masters to provide data to said cache data memory.