Patent ID: 6291860
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor wafer having a surface, said semiconductor wafer comprising:a pair of spaced apart isolation regions formed in said wafer surface and extending from said surface to a depth below said surface;a pair of spaced apart source and drain regions formed in the space between said isolation regions;a patterned thin gate insulating layer formed on the portion of said wafer surface intermediate said source and drain regions and on portions of said wafer surface intermediate the source and drain regions and their respective adjacent isolation regions;a gate electrode formed over and in contact with said gate insulating layer intermediate said source and drain regions, with insulative sidewall spacers formed on opposite side surfaces thereof;source and drain electrodes each comprising side surfaces, a top surface, and a bottom surface, formed over respective portions of said source and drain regions, over said portions of the gate insulating layer intermediate the source and drain regions and their respective adjacent isolation regions, and over at least a portion of the adjacent isolation regions;insulative sidewall spacers formed on opposite side surfaces of each of said source and drain electrodes; andelectrical conductors each in ohmic contact with the top surfaces of respective source and drain electrodes and with said surfaces thereof through selectively formed openings in said insulative sidewall spacers, and extending down to and over at least a portion of the associated source or drain region.