Patent ID: 6117756
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method for forming a memory cell, said method comprising the steps of:providing a semiconductor substrate with an isolation region formed upon, said semiconductor substrate having a pad oxide layer and a first nitride layer formed over, said pad oxide layer formed on a region uncovered by said isolation region on said semiconductor substrate, and said first nitride layer formed over said pad oxide layer;removing a portion of said first nitride layer and of said pad oxide layer to define a gate region;forming a first oxide layer on a region uncovered by said gate region and said isolation region on said semiconductor substrate;forming a sidewall structure on said gate region;doping said semiconductor substrate with first type dopants;performing a first thermal process to form a second oxide layer on a region uncovered by said sidewall structure, said gate region, and said isolation region, and to drive in said first type dopants;removing said sidewall structure and said first nitride layer;forming a first conductive layer over said semiconductor substrate;doping said pad oxide layer, said first oxide layer, and said second oxide layer by implanting second type dopants through said first conductive layer into said pad oxide layer, said first oxide layer, and said second oxide layer, said second type dopants being selected from the group consisting of nitrogen, argon, arsenic, and the combination thereof;performing a second thermal process to said semiconductor substrate;removing a portion of said first conductive layer to define a floating gate;forming a dielectric layer over said semiconductor substrate; andforming a second conductive layer over said semiconductor substrate.