Patent ID: 7236014
Filing Date: 2007-06-26
Classification: H03K

Abstract:
1. A peak detection circuit comprising: an input section for receiving a differential input signal; a gain stage coupled to the input section that is fully differential and offset error compensated for providing an amplified differential signal; a plurality of capacitors coupled to the gain stage, each of the plurality of capacitors having a first electrode for receiving one of two outputs of the gain stage and having a second electrode; a voltage reference coupled to the plurality of capacitors for placing one of two predetermined reference voltages on the second electrode of each respective one of the plurality of capacitors; at least one comparator coupled to the plurality of capacitors, the at least one comparator providing a signal for indicating when the amplified differential signals exceeds a differential of the two predetermined reference voltages; a digital peak sample and hold circuit coupled to the at least one comparator for providing a predetermined data output value for a predetermined amount of time in response to the signals provided by the at least one comparator; and error compensation circuitry coupled to the digital peak sample and hold circuit and the gain stage, the error compensation circuitry provides selective automatic zeroing of offset error voltages of the gain stage when the digital peak sample and hold circuit has a predetermined transition of its digital output, said automatic zeroing occurs concurrently with placing the predetermined one of the two reference voltages on each respective second electrode of the plurality of capacitors.