Patent ID: 8250341
Filing Date: 2012-08-21
Classification: G06F,G06Q

Abstract:
1. A method, comprising: sending, via a communication bus, first data and a second data to first and second ones, respectively, of a plurality of pipeline units, each pipeline unit including a respective hardwired pipeline; processing the first data with the first pipeline unit synchronized to a first clock signal; processing the second data with the second pipeline unit synchronized to a second clock signal and asynchronously relative to the first pipeline unit while the first pipeline unit is processing the first data, the second clock signal being unrelated to the first clock signal; generating a message that includes the first data and that identifies the first pipeline unit as a recipient of the message, wherein sending the first data to the first pipeline unit comprises determining from an address in a header of the message that the first pipeline unit is a recipient of the message; receiving the first data from the communication bus with a hardwired-pipeline circuit; processing the received first data in response to a synchronization signal to cause the first pipeline unit to process the data if the first pipeline unit is the recipient of the message; and loading the processed first data into a memory.