Patent ID: 9026832
Filing Date: 2015-05-05
Classification: G06F,H04L

Abstract:
1. A method for selecting a sampling clock signal, wherein the method is applied to a receiver device, the receiver device comprising a logic chip, a selector, a receive data line RXD and a receive clock line RXC, wherein the logic chip is connected to the selector, and wherein the logic chip is connected to the RXD and the RXC respectively; the selector is a 2-to-1 selector, and the selector is connected to the RXC through an inverter; wherein the method for selecting a sampling clock signal comprises: obtaining, by the logic chip, a data signal from the RXD and a clock signal from the RXC; obtaining, by the logic chip, a data edge of the data signal and a clock edge of the clock signal, selecting a rising edge or a falling edge nearest to a middle position of a data pulse from the clock edge as a sampling edge by detecting only once, relative position of the data edge and the clock edge, and sending a selecting signal corresponding to the sampling edge to the selector; and selecting, by the selector, the clock signal obtained from the RXC or an inverted clock signal obtained from the inverter as a sampling clock signal according to the selecting signal.