Patent ID: 6731170
Filing Date: 2004-05-04
Classification: G09G

Abstract:
A source drive amplifier of a liquid crystal display comprising:a first input circuit controlled by a polarity switching signal for being selectively switched into an NMOS differential amplifying circuit and a bias circuit; a second input circuit controlled by a polarity switching signal for being selectively switched into a bias circuit and a PMOS differential amplifying circuit, wherein, when the polarity switching signal is in a first state, the first and second input circuits are switched into an NMOS differential amplifying circuit and a bias circuit, respectively, and when the polarity switching signal is in a second state, the first and second input circuits are switched into a bias circuit and a PMOS differential amplifying circuit; and an output transistor pair having an NMOS transistor and a PMOS transistor, wherein, an output of the first input circuit switched into an NMOS differential amplifying circuit drives the PMOS transistor of the output transistor pair for being used as a source out amplifying output stage, and a current provided by the NMOS transistor is used as a bias: and an output of the second output circuit switched into a PMOS differential amplifying circuit drives the NMOs transistor of the output transistor pair for being used as a sink in amplifying output state, and a current provided by the PMOS transistor is used as a bias, wherein the first input circuit is formed by first, second, and third NMOS transistors, and fourth, fifth, sixth, and seventh PMOS transistors; the sources of the first and the second NMOS transistors are connected to the drains of the third NMOS and the seventh PMOS transistors; the drains of the first NMOS, the sixth and the fourth PMOS transistors are connected together; the gate and the drain of the fifth PMOS transistor are connected together and further connected to the gate of the fourth PMOS transistor, the sources of the sixth and seventh PMOS transistors, and the drain of the second NMOS transistor; the gates of the first and second NMOS transistors are connected to a first and a second differential voltage input terminal, respectively; the gate of the third NMOS transistor is connected to a first bias end, and the source thereof is connected to a system low voltage; the sources of the fourth and fifth PMOS transistors are connected to a voltage source; and the gates of the sixth and seventh PMOS transistors are connected to a polarity switching signal end.