Patent ID: 8248355
Filing Date: 2012-08-21
Classification: G09G,G11C

Abstract:
1. A shift register, comprising: a plurality of shift register units being controlled by a low level voltage signal, and two clock signals being inversed of each other; wherein the two clock signals are a first clock signal and a second clock signal, each of the shift register units comprises a plurality of N-channel metal oxide semiconductor transistors to form an output circuit, an input circuit, a first logic circuit, and a second logic circuit, the input circuit, the first logic circuit, and the output circuit are coupled to a first node, and the first logic circuit and the second logic circuit are coupled to a second node; wherein the input circuit controls the first logic circuit to output the low level voltage signal or the clock signals, and controls the output circuit to output clock signals; and the second logic circuit controls the output circuit to output the low level voltage signal; wherein the first logic circuit comprise a first transistor, a second transistor, and a third transistor, a gate of the first transistor is connected to the first node, and a source of the first transistor receives the low level voltage signal, a drain of the first transistor is connected to a source of the second transistor, a gate and a drain of the second transistor receive the second clock signal, a gate of the third transistor receives the first clock signal, a source of the third transistor is connected to the second node, and a drain of the third transistor is connected to a next adjacent shift register unit.