Patent ID: 6938145
Filing Date: 2005-08-30
Classification: G06F

Abstract:
1. A computer system including a central processing unit (CPU) and an addressable main memory storing data pages, at least one data page storing a page table, said CPU comprising: A) a processor coupled to said main memory; B) an associative memory storing a plurality of entries, each entry in said associative memory being stored in accordance with a low order virtual address component issued by said processor, each entry in said associative memory including fields respectively holding: C) a multi-digit counter storing a current validity count; D) a comparator coupled to receive: said processor also sending a low order virtual address component of the requested data page to said associative memory to specify an entry therein; E) a switch coupled to receive the real page address read from the specified associative memory entry and, when enabled, issue the real page address; and F) said comparator issuing a signal to enable said switch when: