Patent ID: 6169699
Filing Date: 2001-01-02
Classification: G11C

Abstract:
A semiconductor memory device comprising: an interface circuit having a first side and a second side along a lengthwise direction of the interface circuit; a first memory cell array placed along the first side of said interface circuit and having a plurality of banks, each of which is formed of a column of cell array units placed along a direction perpendicular to the lengthwise direction of said interface circuit, a cell array unit activated by a bank address being included at least in one of said plurality of banks; and a second memory cell array placed along the second side of said interface circuit and having a plurality of banks, each of which is formed of a column of cell array units placed along a direction perpendicular to the lengthwise direction of said interface circuit, a cell array unit activated by said bank address being included at least in one of said plurality of banks.