Patent ID: 8936976
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: forming a III-V semiconductor stack by epitaxially forming a first III-V layer directly on a III-V channel layer, said III-V channel layer epitaxially formed directly on a III-V buffer layer; etching said first III-V layer where said transistor's gate electrode is to be placed, said etching creating a void within said first III-V layer, said III-V buffer layer not acting as an etch stop for said etch; epitaxially forming a barrier layer in said void that fills said void; forming a gate electrode over said barrier layer wherein an end of said gate electrode that is closest to said III-V channel layer extends into said barrier layer; and, forming source and drain electrodes over said first III-V layer.