Patent ID: 6255181
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method for fabricating a metal oxide semiconductor (MOS) transistor, comprising:forming a gate pattern on a semiconductor substrate of a first conductivity type, said gate pattern including a gate insulating layer and a polysilicon gate sequentially formed thereon;injecting low concentration impurity ions of a second conductivity type into the semiconductor substrate, using the gate pattern as a mask, to form lightly doped regions at both sides of the gate pattern;forming an insulating layer on the semiconductor substrate, including the gate pattern;anisotropically etching the insulating layer to form sidewall spacers on both sidewalls of the gate pattern and to leave a portion of the insulating layer on the semiconductor substrate, wherein the gate pattern and the sidewall spacers constitute a gate structure;injecting high concentration impurity ions of the second conductivity type into the semiconductor substrate, using the gate structure as a mask, to form heavily doped regions at both sides of the gate structure;removing said portion of the insulating layer to expose an upper surface of the heavily doped region, wherein the lightly and heavily doped regions constitute a source/drain;forming a transition metal layer over the semiconductor substrate, including the gate structure; andannealing the semiconductor substrate to form a silicide layer on an upper surface of the polysilicon gate and on the heavily doped regions based on reaction of the transition metal layer with the polysilicon gate and the heavily doped regions.