Patent ID: 6121108
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method for forming a cylinder capacitor on a field effect transistor (FET), which is formed on a semiconductor substrate, the FET comprising a gate structure, two interchangeable source/drain regions respectively on each side of the gate, the method comprising:sequentially forming a dielectric layer, an etching stop layer, and a first insulating layer over the substrate;patterning the dielectric layer, the etching stop layer, and the first insulating layer to form an opening that exposes one of the interchangeable source/drain regions of the FET;forming a conductive layer over the substrate so that the opening is also filled;forming a second insulating layer on the conductive layer;removing a top portion of the second insulating layer, other than the region above the opening, so as to form a convex layer on top;forming two sidewall spacers respectively on each sidewall of the convex layer;using the sidewall spacers as a mask, removing a portion of the second insulating layer so that a concave structure is formed on the conductive layer, wherein the concave structure is a remaining portion of the second insulating layer, and the conductive layer is exposed at a portion other than the concave structure;using the concave structure as a mask, removing the exposed portion of the conductive layer so as to expose a portion of the first insulating layer;using the sidewall spacers as a mask, removing the concave structure at a portion without being covered by the sidewall spacers so as to expose the conductive layer, and a remaining portion of the concave structure under the sidewall spacers forms two pillars;forming a plurality of conductive spacers respectively on each sidewall of the pillars, wherein the conductive spacers electrically contact the conductive layer; andremoving the pillars and the first insulating layer to expose the conductive spacers and a portion of the conductive layer.