Patent ID: 7330379
Filing Date: 2008-02-12
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array composed of a plurality of memory cells whose addresses are represented by a plurality of row addresses and a plurality of column addresses; a row selecting unit which selects the memory cells at the specified rows from among the memory cells; a column selecting unit which selects the memory cells at the specified columns from among the memory cells; a data writing unit which writes data into the specified memory cells selected by the row selecting unit and the column selecting unit; a data reading unit which reads the data from the specified memory cells; and a data logic forcefully controlling unit, the data logic forcefully controlling unit forcefully controlling the logic of the write data into the memory cells selected by using a specified address signal or of the read data, wherein: the data logic forcefully controlling unit is included in a data input and output buffer cell block.