Patent ID: 6209113
Filing Date: 2001-03-27
Classification: G06F,G11C

Abstract:
A method of operating a multistate memory cell, the cell having one of 4 states, the method comprising:reading the cell to generate a voltage signal indicative of the state of the cell, the voltage signal being in one of a sequence of voltage subranges L.sub.i <H.sub.i in a voltage range of X volts defined from a minimum voltage, wherein i is an integer from 1 through 4, and wherein L.sub.1 is approximately 0 percent of X volts, H.sub.1 is approximately 24 percent of X volts, L.sub.2 is approximately 25 percent of X volts, H.sub.2 is approximately 49 percent of X volts, L.sub.3 is approximately 50 percent of X volts, H.sub.3 is approximately 74 percent of X volts, L.sub.4 is approximately 75 percent of X volts, and H.sub.4 is approximately 100 percent of X volts;encoding the voltage signal into one of a sequence of encoded signals E.sub.1, E.sub.2, E.sub.3, and E.sub.4, each of the encoded signals representing a unique ordered set of binary bits; andperforming error detection and correction on the encoded signal to detect errors in the encoded signal and to correct correctable errors in the encoded signal.