Patent ID: 8330588
Filing Date: 2012-12-11
Classification: G01R

Abstract:
1. A circuit comprising: an input circuit coupled to receive a data input signal and a clock signal; an output circuit coupled to the input circuit, wherein the output circuit is configured to, when activated, drive an output signal on an output node, and wherein the input circuit is configured to, responsive to a logical transition of the input signal, activate the output circuit in order to initiate a logical transition of the data output signal; a deactivation circuit configured to deactivate the output circuit at a delay time subsequent to activation of the output circuit; and a latch coupled the output circuit, wherein the latch circuit is configured to change a latch output state responsive to activation of the output circuit, and wherein the latch is further configured to hold a state of the output circuit on the output node subsequent to deactivation of the output circuit; wherein the input circuit is configured to activate the output circuit dependent on the clock signal, and wherein the deactivation circuit is configured to deactivate the output circuit independent of the clock signal.