Patent ID: 6226207
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A semiconductor memory device comprising:a cell array block which has a plurality of memory cells;a bit line sense-amplifier for sensing and amplifying a cell charge transmitted to a true bit line or a complement bit line; andan electric charge amplifier connected between the cell array block and the bit line sense-amplifier, for amplifying the cell charge transmitted to the true bit line or the complement bit line with a sufficient potential difference by using a capacitance component, and then transmitting the amplified cell charge to the bit line sense-amplifier, wherein the electric charge amplifier includes,a first transistor positioned between a true bit line and a complement bit line, of which a drain, gate and source are each connected to the complement bit line, the true bit line and a first node;a second transistor positioned between the true bit line and the complement bit line, of which a drain, gate and source are each connected to the true bit line, the complement bit line and a second node; anda third transistor of which a drain, gate and source are each connected to the second node, a control signal and the first node.