Patent ID: 6557144
Filing Date: 2003-04-29
Classification: G06F

Abstract:
A method for automatically improving an accepted netlist and global placement of logic nodes and physical placement for an integrated circuit (IC), comprising:A) receiving an accepted netlist and global placement from a design process for the IC design; B) identifying critical nodes based on delay time calculated from the physical placement; C) selecting a set of critical nodes comprising critical fanins and non-critical fan-ins in an uncollapsed sub-netlist, and optimally collapsing the critical fan-ins to form a collapsed sub-netlist so that the collapsed sub-netlist is remapped better than before the collapsing; D) building a subject graph and covering the subject graph with a pattern graph to remap the collapsed sub-netlist; and E) returning to C) if the collapsed sub-netlist is unacceptable, returning to B) if the collapsed sub-netlist is acceptable, and exiting at B) when no more critical nodes are identified at B).