Patent ID: 8029660
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor integrated circuit device comprising the steps of: (a) forming a resist film having a plurality of openings over a first main surface of a wafer; (b) introducing the wafer having the resist film into a single-wafer plating apparatus having a plating cup; (c) loading, in the single-wafer plating apparatus, the wafer having the resist film in the plating cup so as to place the wafer with the first main surface down and opposite to a plating tank of the plating cup; (d) after the step (c), introducing a plating solution into the plating tank with the first main surface of the wafer down; (e) after the step (d), stirring clockwise and anticlockwise the plating solution in the plating tank with the first main surface of the wafer down; (f) after step (e), inverting the plating cup; (g) after step (f), stirring clockwise and anticlockwise the plating solution in the plating tank with the first main surface of the wafer up; (h) after the step (g), forming a gold bump electrode with the first main surface of the wafer up by electroplating in the opening portions over the first main surface; (i) after step (h), re-inverting the plating cup; and (j) after step (i), unloading the wafer from the plating cup.