Patent ID: 6744672
Filing Date: 2004-06-01
Classification: G11C,H01L

Abstract:
A non-volatile semiconductor device, where n is a natural number of at least 3 and m is a natural number smaller than n, comprising:a first word line; first to nth bit lines crossing said first word line and positioned successively in order; and first to nâˆ’1th non-volatile memory cells positioned respectively in nâˆ’1 areas between said first and nth bit lines and connected to said first word line together; wherein each of said first to nâˆ’1th non-volatile memory cells is connected between a higher order bit line and a lower order bit line as two corresponding bit lines among said first to the nth bit lines, and includes a memory transistor having its control electrode connected to said first word line, storing one bit depending on whether a first current can flow or not from said higher order bit line to said lower order bit line on activation of said first word line, and storing the other bit depending on whether a second current can flow from said lower order bit line to said higher bit line on activation of said first word line; said non-volatile semiconductor memory device further comprising a potential supply circuit, to check whether said first current flows through an mth non-volatile memory cell, supplying ground potential to an mth bit line, supplying a read power source potential higher than said ground potential to an m+1th bit line, and supplying a bias power source potential higher than said ground potential to an m+2th bit line independent of said read power source potential; wherein said potential supply circuit includes a current sense circuit provided on a path thorough which said first current flows from said read power source potential to said ground potential for sensing said first current.