Patent ID: 9142611
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a plurality of transistors contributing to a logical operation; an element that does not contribute to the logical operation; and first, second, and third substrate contact regions supplying a substrate potential to the plurality of transistors, wherein the semiconductor integrated circuit device includes a plurality of transistor arrays extending in a first direction and being disposed in a line in a second direction orthogonal to the first direction, wherein each of the plurality of transistor arrays includes the plurality of transistors, the element that does not contribute to the logical operation, the first substrate contact region, the second substrate contact region, and the third substrate contact region disposed between the first substrate contact region and the second substrate contact region, a substrate contact region is disposed in a region adjacent to the first substrate contact region in the second direction and in a region adjacent to the first substrate contact region in a direction opposite to the second direction, a substrate contact region is disposed in a region adjacent to the second substrate contact region in the second direction and in a region adjacent to the second substrate contact region in a direction opposite to the second direction, no substrate contact region is disposed in a region adjacent to the third substrate contact region in the second direction and in a region adjacent to the third substrate contact region in a direction opposite to the second direction, and the element that does not contribute to the logical operation is disposed in a region adjacent to the third substrate contact region in the first direction.