Patent ID: 7698677
Filing Date: 2010-04-13
Classification: G06F

Abstract:
1. An article of manufacture comprising machine-readable medium including program logic embedded therein that when executed by a machine cause a method of reducing the dynamic noise of a power network of a semiconductor circuit ( 100 ), comprising the steps of: a) dividing a semiconductor circuit ( b) determining a violation group of said plurality of tiles ( c) determining wire constraints for wires ( d) determining decap constraints for a value of decap to be added to circuitry within said determined violation region ( e) determining an optimal decap/wire value which determines a value of decap and a value of wire enhancement, where said decap and wire enhancement values are used to add power/ground wires ( f) modifying the semiconductor circuit design based on said decap and wire enhancement values to add power/ground wires and decap within at least a portion of said semiconductor circuit within said determined violation region of said plurality of tiles to reduce said dynamic noise.