Patent ID: 8384147
Filing Date: 2013-02-26
Classification: G11C,H01L

Abstract:
1. An electrically programmable and erasable memory cell comprising: a substrate of semiconductor material of a first conductivity type; a first storage transistor of the type having a first region and a second region in said substrate each of a second conductivity type, with the first and second regions spaced apart from one another with a first channel region therebetween, defined in a first direction; a first floating gate over at least a portion of said first channel region, insulated therefrom, to control the conduction of current through the first channel region; a first control gate capacitively coupled to the first floating gate; wherein said first storage transistor is read by applying a first voltage to said first region; a second storage transistor of the type having a third region and a fourth region in said substrate each of a second conductivity type, with the third and fourth regions spaced apart from one another with a second channel region therebetween, defined in the first direction; with the second storage transistor adjacent and spaced apart from the first storage transistor in a second direction substantially perpendicular to the first direction, with the third region laterally spaced apart from the first region in the second direction and the fourth region laterally spaced apart from the second region in the second direction; said second storage transistor further comprising a second floating gate over at least a portion of said second channel region, insulated therefrom, to control the conduction of current through the second channel region; a second control gate capacitively coupled to the second floating gate; wherein said second storage transistor is programmed by applying a first current to said third region; wherein the first floating gate is electrically connected to the second floating gate; wherein the first region is insulated from the third region in the substrate; and wherein the memory cell is programmed by applying the first current to the third region, and read by applying the first voltage to the first region.