Patent ID: 8533568
Filing Date: 2013-09-10
Classification: H03M

Abstract:
1. A Low Density Parity Check (LDPC) encoder comprising: a memory module including at least N×L×K storage locations, where N and L are positive integers and K is an integer >1; a controllable permuter for performing element re-ordering operations on at least N elements coupled to said memory module; a vector accumulator module including N accumulators arranged in parallel, said vector accumulator module including: a controllable storage device including N×K storage locations, said controllable storage device including a block select control signal input for receiving a signal indicating a block of at least N storage locations to be accessed and a storage device output at least N bits wide for outputting values read from said storage devices; and a block selection module coupled to said controllable storage device for supplying a block selection control signal to said controllable storage device.