Patent ID: 7323916
Filing Date: 2008-01-29
Classification: H03K,H03L

Abstract:
1. A frequency synthesis circuit comprising: clock synthesis circuit for receiving a reference clock signal and for generating a first clock signal at a first frequency; phase locked loop circuit, coupled to said clock synthesis circuit, for receiving said first clock signal and a feedback clock signal and for generating a second clock signal comprising a second frequency, wherein said first and second frequencies are different frequencies; interpolator circuit, coupled in a feedback path to said phase locked loop circuit, for receiving said second clock signal and for generating said feedback clock signal by introducing a time delay in said second clock signal that varies over time so as to change said second frequency of said second clock signal; and interpolator control circuit, coupled to said interpolator circuit, for controlling said variable time delay introduced by said interpolator, said interpolator control circuit comprising a digital circuit for generating an interpolator control word that controls said variable time delay in said interpolator, and wherein said interpolator control word comprises a clock offset word to define an offset between said first frequency and said second frequency.