Patent ID: 9128125
Filing Date: 2015-09-08
Classification: G01R,H01L

Abstract:
1. An integrated circuit package including a current sense resistor integrated with an integrated circuit die, the integrated circuit die being housed in a flip-chip semiconductor package, the integrated circuit package comprising: the integrated circuit die having a passivation layer being an insulating layer formed on a first surface of the integrated circuit die to protect circuitry formed on the first surface of the integrated circuit die, the passivation layer having openings formed therein to expose one or more bond pads also formed on the first surface of the integrated circuit die for forming electrical connections to the circuitry of the integrated circuit die; the current sense resistor comprising a metal layer formed over and on the passivation layer of the integrated circuit die and being insulated from the circuitry formed on the first surface of the integrated circuit die by the passivation layer, the metal layer having an array of metal pillars being formed on the metal layer and on the passivation layer of the integrated circuit die and extending in a direction away from the first surface of the integrated circuit die, the metal pillars being electrically and physically connected to a first leadframe portion and a second leadframe portion of a leadframe of the flip-chip semiconductor package, the first leadframe portion and the second leadframe portion being electrically isolated from each other in the leadframe of the flip-chip semiconductor package and physically separated by a separation of a first distance in the leadframe of the flip-chip semiconductor package, wherein the current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor; wherein the flip-chip semiconductor package further comprises at least one metal pillar bump being formed on a first bond pad of the one or more bond pads of the integrated circuit die, the at least one metal pillar bump extending in the same direction away from the first surface of the integrated circuit die as the array of metal pillars and being electrically connected to a lead of the leadframe of the flip-chip semiconductor package; and wherein the integrated circuit package is formed having the metal layer with the array of metal pillars and the at least one metal pillar bump formed sandwiched between the passivation layer formed on the first surface of the integrated circuit die and the leadframe of the flip-chip semiconductor package.