Patent ID: 6417032
Filing Date: 2002-07-09
Classification: H01L,Y10S

Abstract:
A method of forming an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device comprising:forming an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage (Vcc), forming a plurality of dielectric layers containing metal conductor lines over the transistors, the gate conductors and the interconnection lines, forming a conductive reference potential node electrically connected to the source region of each of the pull-down transistors, said metal conductor lines including a first Vss strap/conductor line oriented in a first direction in a first one of the dielectric layers and a second Vss strap/conductor line oriented in a second direction in a second one of the dielectric layers, and forming a VIA/contact between the conductive reference potential node and the first and second Vss strap/conductor lines.