Patent ID: 7451288
Filing Date: 2008-11-11
Classification: G06F

Abstract:
1. An apparatus for generating an individual key for accessing a predetermined addressable unit of a memory divided into addressable units, wherein the addressable units are combined into pages in groups, wherein a unique address is associated with the predetermined addressable unit, which is made up of a page address indicating the page to which the addressable unit belongs, and a unit address identifying the addressable unit among the other addressable units belonging to the page, comprising: a calculator configured to calculate a page pre-key based on the page address; a determiner configured to determine the individual key based on the page pre-key and the unit address; a memory configured to store the calculated page pre-key; and a checker configured to check whether during a next access to a further predetermined unit to which a further unique address is associated, an already calculated page pre-key exists in a temporary memory, which has been calculated based on a page address of a unique address, which is identical to the page address of the further unique address, and, if this is the case, transmitting the already calculated page pre-key to the determiner by bypassing the calculator, and, if this is not the case, transmitting the page address of the further unique address to the calculator, with at least one of, the calculator comprising more chip area than the determiner, and the calculator using a longer processing run time than the determiner.