Patent ID: 6360243
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A task scheduling accelerator device for determining and controlling multi-tasking, comprising:a synchronous task command interface, coupled to a host processor, an interrupt service routine interface and a bus, for receiving commands from tasks on the host processor; an asynchronous task command interface, coupled to the host processor and the bus, for receiving commands from tasks and interrupt service routines on the host processor; an interrupt service routine interface, coupled to the host processor, a status register and the bus, for specifying and controlling a task switch; a semaphore post queue interface, coupled to the host processor, for specifying and determining, to a computational unit, a status of a data queue stored in the host processor; the status register, coupled to the host processor and the bus, for specifying a status of the task scheduling accelerator device; the computational unit, coupled to the bus, the status register, the synchronous task command interface and the semaphore post queue interface for computing task scheduling decisions; and a bus, coupled to the synchronous task command interface, the asynchronous task command interface, the interrupt service routine interface, the status register and the computational unit, for moving data between registers/interfaces and the computational unit.