Patent ID: 6292930
Filing Date: 2001-09-18
Classification: H03K

Abstract:
A machine-implemented method for preparing to configure an FPGA having general interconnect with plural lines, a shareable line driver and a share-enabling dynamic multiplexer (DyMUX) that is connectable to an input of the line driver without using said general interconnect, said method comprising:(a) searching a supplied design definition for the presence of two or more design components that are defined to output signals at different and mutually exclusive times; and(b) if two or more such searched-for design components are found, modifying place-and-route definitions of such found design components so as to urge such found design components towards placement in using-enabled proximity of the shareable line driver and of the share-enabling dynamic multiplexer (DyMUX) so that if two or more of the found and urged design components are ultimately implemented as respective components in the FPGA and the so-ultimately implemented components are placed in said using-enabled proximity of the shareable line driver and of the share-enabling DyMUX, the so-ultimately implemented and placed components can, without consuming additional general interconnect for shared use of the shareable line driver and of the share-enabling DyMUX, share use of the shareable line driver and of the share-enabling DyMUX to output their respective signals at different times onto a shared fine within the general interconnect.