Patent ID: 6744125
Filing Date: 2004-06-01
Classification: H01L

Abstract:
An ultra-thin semiconductor package, comprising:a semiconductor substrate, said semiconductor substrate having a first and a second surface, points of electrical contact having been provided in the second and the first surface of said semiconductor substrate, said semiconductor substrate having been provided with a cut-out through said semiconductor substrate of a size allowing insertion of a semiconductor die therein, said insertion leaving a measurable distance between sidewalls of said die and an internal perimeter of said cut-out through said semiconductor substrate; an interconnect substrate comprising copper traces, said interconnect substrate having a first and a second surface, said first surface of said interconnect substrate being in contact with the second surface of the semiconductor substrate, points of electrical interconnect being provided in the first surface of said interconnect substrate, said points of electrical interconnect provided on said first surface of said interconnect substrate being in electrical contact with copper traces provided in said interconnect substrate, copper traces of said interconnect substrate being connected with points of electrical contact in or on the second surface of said interconnect substrate; a solder mask having been provided on the first surface of said semiconductor substrate, said solder mask exposing points of electrical contact provided in the first surface of said semiconductor substrate; a semiconductor die being inserted in said opening provided in said semiconductor substrate, said semiconductor die having a first and a second surface, said first surface been provided with points of electrical contact, said second surface of said die being in contact with said first surface of said interconnect substrate, said second surface of said semiconductor die being about in a plane of said second surface of said semiconductor substrate; wire bond connections having been provided between points of electrical contact provided in said first surface of said semiconductor die and said points of electrical contact provided in or on said first surface of said semiconductor substrate; contact balls attached to said contact points provided in said first surface of said semiconductor substrate, said contact balls having been inserted through openings provided in said solder mask; a copper foil attached to the second surface of said interconnect substrate; and said semiconductor die and said wire bond connections and said first surface of said solder mask partially and in the immediate surroundings of said opening created in said semiconductor substrate being embedded in a mold cap, said mold cap further penetrating between sidewalls of said semiconductor die and surrounding sidewalls of said opening created in said semiconductor substrate.