Patent ID: 7826497
Filing Date: 2010-11-02
Classification: H03K,H04J

Abstract:
1. A data receiving circuit having a data input terminal, a conversion circuit configured to convert an input signal received via said data input terminal, and a decision circuit configured to make a decision on an output of said conversion circuit, wherein said conversion circuit comprises a demultiplexer configured to convert said input signal into a signal of a lower frequency than the frequency thereof at said data input terminal, wherein an output of said demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source, wherein said data receiving circuit further comprises an integrating circuit configured to receive the output of said demultiplexer and integrate temporally consecutive multiple bit data by 1-bit data of said input signal, integrated values of said temporally consecutive multiple bit data are accumulated, and an accumulated value of said integrated values is obtained as a weight of sign and magnitude that differs for each bit of said input signal.