Patent ID: 6204564
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A semiconductor device comprising:A film substrate having an upper surface and a lower surface, the upper surface being provided with a plurality of wiring patterns, the lower surface being provided with a plurality of external terminal portions which are arranged in a matrix pattern and connected with the wiring patterns;a semiconductor chip having a main surface provided with a plurality of bump terminal pads, and an upper surface opposite to the main surface, the semiconductor chip being mounted on the film substrate with the bump terminal pads held in facing relation to the wiring patterns;a connection layer made of an anisotropic conductive adhesive arranged between the semiconductor chip and the film substrate for mechanically connecting the chip to the substrate and for electrically connecting the bump terminal pads to the wiring pattern; andan insulating film formed on the upper surface of the film substrate for covering at least part of the wiring patterns in a manner avoiding the bump terminal pads.