Patent ID: 8089159
Filing Date: 2012-01-03
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a die pad having opposed first and second pad surfaces, and a third pad surface extending between the first and second pad surfaces; a conductive ring having opposed first and second ring surfaces, and a third ring surface extending between the first and second ring surfaces; a plurality of I/O pads which each have opposed first and second surfaces, and a third surface which extends between the first and second surfaces, the I/O pads being segregated into at least an inner set which extends at least partially about the conductive ring and an outer set which extends at least partially about the inner set, the third surface of each of the I/O pads being inclined such that the first surface is of a first area and the second surface is of a second area which exceeds the first area, the first surface of each of the I/O pads further defining a peripheral edge and including a first plated layer which is formed thereon and protrudes beyond the peripheral edge; at least one semiconductor die attached to the first pad surface of the die pad and electrically connected to the die pad, the conductive ring and at least one of the I/O pads; and a package body at least partially encapsulating the die pad, the conductive ring, the I/O pads and the semiconductor die such that at least the second pad surface of the die pad, the second ring surface of the conductive ring and the second surfaces of each of the I/O pads are each exposed in a common exterior surface of the package body.