Patent ID: 7348246
Filing Date: 2008-03-25
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor memory device, the method comprising: forming first and second charge storage layers on a channel region between first and second source/drain regions in a semiconductor substrate; forming first and second control gate electrodes on the respective first and second charge storage layers; forming a first insulating layer on the channel region between the first and second charge storage layers; forming second and third insulating layers extending from adjacent inner sidewalls of the first and second charge storage layers beyond the first and second charge storage layers; forming a lower gate electrode on the first insulating layer opposite the channel region and between the inner sidewalls of the first and second charge storage layers, wherein the lower gate electrode extends away from the substrate beyond the first and second charge storage layers; and forming an upper gate electrode on the lower gate electrode between the first and second control gate electrodes.