Patent ID: 6611439
Filing Date: 2003-08-26
Classification: H02M

Abstract:
A PWM controller for controlling an output power limit of a power supply, comprising:a current divider, having a first terminal connected to a line input voltage of the power supply via a startup resistor, a second terminal coupled to a supply voltage, and a third terminal; a mirror resistor, having a first terminal coupled between the third terminal of the current divider, and a second terminal coupled to a ground voltage; an adder, with a negative input terminal coupled between the third terminal of the current divider and the first terminal of the mirror resistor, a positive input terminal coupled to a reference voltage, and an output terminal; a first comparator, with a positive input terminal coupled to the output terminal of the adder, a negative input terminal, and an output terminal; a second comparator, with a positive input terminal coupled to the supply voltage, a negative terminal coupled to the negative terminal of the first comparator, and an output terminal; a NAND gate, with two input terminals coupled to the output terminals of the first and second comparators, and an output terminal; a flip flop, coupled to the output terminal of the NAND gate; and an oscillator, coupled to the flip flop.