Patent ID: 7923644
Filing Date: 2011-04-12
Classification: G11B,H05K,Y10T

Abstract:
1. A printed circuit board comprising: an insulating layer; first and second wiring patterns that are formed on one surface of said insulating layer and constitute a signal line pair; first and second electrode pads that are formed on one surface of said insulating layer and are connected to said first wiring pattern; third and fourth electrode pads that are formed on one surface of said insulating layer and are connected to said second wiring pattern; a first connecting layer that is provided on the other surface of said insulating layer, wherein said first wiring pattern has first, second, third and fourth lines, said second wiring pattern has fifth, sixth, seventh and eighth lines, one ends of said first and second lines are electrically connected to each other and the other ends of said first and second lines are electrically connected to each other, said third line extends to be branched from the one end of said first line or the one end of said second line and is connected to said first electrode pad, said fourth line extends to be branched from the other end of said first line or the other end of said second line and is connected to said second electrode pad, one ends of said fifth and sixth lines are electrically connected to each other and the other ends of said fifth and sixth lines are electrically connected to each other, said seventh line extends to be branched from the one end of said fifth line or the one end of said sixth line and is connected to said third electrode pad, said eighth line extends to be branched from the other end of said fifth line or the other end of said sixth line and is connected to said fourth electrode pad, said first and second lines of said first wiring pattern and said fifth and sixth lines of said second wiring pattern are arranged such that any one of said first and second lines is located between said fifth and sixth lines and any one of said fifth and sixth lines is located between said first and second lines, a first intersection region in which said first or second line of said first wiring pattern and said fifth or sixth line of said second wiring pattern intersect with each other is provided, a second intersection region in which said first or second line of said first wiring pattern and said fifth or sixth line of said second wiring pattern intersect with each other is provided, a portion of said first or second line of said first wiring pattern positioned in said first intersection region is divided, a portion of said fifth or sixth line of said second wiring pattern positioned in said first intersection region is arranged on said insulating layer to pass through a portion in between divided portions of said first or second line of the first wiring pattern, said insulating layer has first and second through holes in said first intersection region, one of said divided portions of said first or second line of the first wiring pattern is electrically connected to said first connecting layer through said first through hole, and the other of said divided portions of said first or second line of the first wiring pattern is electrically connected to said first connecting layer through said second through hole.