Patent ID: 6438732
Filing Date: 2002-08-20
Classification: G06F

Abstract:
A method of estimating charges within a DCVSL structure which includes a plurality of different MOS devices, the method comprising the steps of:(A) determining a gate capacitance of each of the MOS devices that comprise the DCVSL structure by using circuit models that simulate a set of signals including signals at a gate, a source and a drain of each of said MOS devices, and selecting at least one simplified DCVSL model to account for the complementary switching behavior of a DCVSL structure, and after determining the gate capacitance of each individual MOS device, performing an estimating step, including: (i) estimating a maximum charge based upon one DCVSL model; (ii) estimating a minimum charge based upon another DCVSL model; (iii) estimating a charge corresponding to a rising gate input based upon one DCVSL model by determining a maximum capacitance by having the source/drain of a first MOS device falling and the source/drain of a paired MOS device being held constant VSS, and by determining a minimum capacitance by having the source/drain of said first MOS device rising and the source/drain of the paired MOS device being held at VDD; and (B) combining said gate capacitance for each individual MOS device to determine the gate capacitance of the DCVSL structure.