Patent ID: 6356514
Filing Date: 2002-03-12
Classification: G01R

Abstract:
A delay circuit comprising:a. a chain of at least first and last synchronous circuits, each synchronous circuit having: 1. a clock terminal; 2. a synchronous input terminal; 3. an asynchronous input terminal; 4. an output terminal; and 5. a delay element having an input terminal connected to the output terminal of the synchronous circuit and an output terminal connected to the asynchronous input terminal; b. an inverting element having an inverting element output terminal connected to the first synchronous circuit clock terminal and an inverting element input terminal connected to last synchronous circuit output terminal; and c. at least one connector connecting the output terminal of a synchronous circuit in the chain other than the last synchronous circuit to the clock terminal of a next synchronous circuit, thereby forming the chain.