Patent ID: 6232670
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A semiconductor memory device including: a semiconductor substrate having a main surface; and first and second load transistors and first and second driver transistors formed on the main surface, the semiconductor memory devise comprising:(a) first and second memory cells each of which comprises:a first load transistor active region formed on the main surface and to be an active region for the first load transistor;a second load transistor active region formed on the main surface and to be an active region for the second load transistor;a first driver transistor active region formed on the main surface and to be an active region for the first driver transistor;a second driver transistor active region formed on the main surface and to be an active region for the second driver transistor;a first element isolation region formed on the main surface and isolating the first load transistor active region from the first driver transistor active region;a first conductive layer extending from an area on the first load transistor active region to an area on the first driver transistor active region, and to be a gate electrode for the first load transistor and the first driver transistor;a second conductive layer which diverges from the first conductive layer on the first element isolation region and is electrically connected to the second driver transistor active region; anda third conductive layer being electrically connected to the first load transistor active region and extending to an area on the second driver transistor active region across an area on the second load transistor active region, and to be a gate electrode for the second load transistor and the second driver transistor, and(b) a second element isolation region formed on the main surface and isolating the first and second load transistor active regions of the first memory cell from the first and second load transistor active regions of the second memory cell,wherein a pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers of the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface.