Patent ID: 7395398
Filing Date: 2008-07-01
Classification: G06K,G11C

Abstract:
1. A memory controller for controlling one of a read operation and a write operation of a memory, comprising: a central processing unit (CPU) for outputting a read command signal in response to a data read request signal and outputting a write command signal in response to a data write request signal; a memory interface for outputting a plurality of control signals in response to one of the read command signal and the write command signal, generating a memory clock signal having a variable frequency by dividing a system clock signal, and changing the frequency of the memory clock signal based on a frequency change control signal; and a frequency change controller for outputting the frequency change control signal in response to the plurality of control signals, the memory clock signal, and a reset signal, wherein the frequency change controller comprises an address comparator for comparing a current row address of the memory with an immediately preceding row address and producing a comparison signal that is a logic high level when the current row address is different than the immediately preceding row address, and a frequency change control signal output unit receiving the comparison signal and a reset detection signal produced when a read operation is requested after the reset signal is received, wherein the frequency change control signal is enabled when the comparison signal is a high level or the reset detection signal is a high level.