Patent ID: 8076191
Filing Date: 2011-12-13
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having, on a semiconductor substrate, a first region, the first region including therein a memory cell formation region having a plurality of memory cells formed therein, the method comprising the steps of: (a) forming a first insulation film over the semiconductor substrate; (b) forming a first conductive film over the first insulation film; (c) patterning the first conductive film, and thereby forming a pair of first dummy gate pairs being in the first region and interposing the memory cell formation region, and extending in a first direction, and a pair of second dummy gate pairs being in the first region and interposing the memory cell formation region, and extending in a second direction crossing with the first direction, and further leaving a portion of the first conductive film formed outside the first region; (d) after the step (c), forming a first well of a first conductivity type in the semiconductor substrate; (e) after the step (d), forming a second insulation film over the semiconductor substrate including over the first dummy gate pairs and the second dummy gate pairs; (f) forming a second conductive film over the second insulation film; (g) forming an antireflection film over the second conductive film; (h) forming a first resist film over the antireflection film; (i) patterning the first resist film; and (j) processing the second conductive film using the first resist film patterned as a mask, and thereby forming a memory gate electrode in each of the memory cells, and wherein the method further comprises the steps of: (k) before the step (a), forming a second well of a second conductivity type opposite to the first conductivity type in a region in the semiconductor substrate and deeper than the first well, and forming a third well of the second conductivity type in such a manner as to reach the second well in a portion of the semiconductor substrate overlapping in plan view with a region including the first dummy gate pairs formed therein; (l) after the step (j), forming an opening in a part of the first dummy gate pairs, and exposing the third well through the bottom of the opening; (m) after the step (l), forming a second semiconductor region of the second conductivity type in the third well exposed through the opening; (n) forming a second silicide layer over the surface of the second semiconductor region; (o) after the step (n), forming an interlayer insulation film over the semiconductor substrate; (p) forming a second contact hole penetrating through the interlayer insulation film through the inside of the opening, and reaching the second silicide layer at the bottom; and (q) embedding a conductive film in the second contact hole, and thereby forming a second plug electrically coupled with the second silicide layer formed over the surface of the second semiconductor region.