Patent ID: 6529040
Filing Date: 2003-03-04
Classification: H03K

Abstract:
A lookup table comprising:a plurality of memory circuits, each having a memory circuit output terminal providing a memory circuit output signal; a read decoder tree having at least two stages of multiplexers separated by a stage of buffers comprising: a first stage of multiplexers comprising a plurality of first stage multiplexers each first stage multiplexer receiving as input signals at least two of the memory circuit output signals and providing a first stage multiplexer output signal; a second stage of multiplexers comprising at least one second stage multiplexer having a plurality of input terminals for receiving second stage multiplexer input signals; and a buffer stage comprising a plurality of buffers, each buffer having an input terminal connected to receive one of the first stage multiplexer output signals and having an output terminal connected to provide one of the second stage multiplexer input signals.