Patent ID: 7271060
Filing Date: 2007-09-18
Classification: H01L

Abstract:
1. A semiconductor processing method comprising: providing a semiconductor substrate comprising a memory array region and a peripheral region proximate the memory array region; forming spaced nitride-containing masking structures over the substrate, some of the nitride-containing masking structures being first nitride-containing masking structures over the memory array region and others of the nitride-containing masking structures being second nitride-containing masking structures over the peripheral region; forming trenches in the substrate between the spaced nitride-containing masking structures, some of the trenches being first trenches associated with the memory array region and others being second trenches associated with the peripheral region, the second trenches being formed to be substantially deeper than the first trenches; after forming the first and second trenches, laterally recessing the second nitride-containing masking structures to a degree greater than any lateral recessing of the first nitride-containing masking structures; and after the lateral recessing of the second nitride-containing masking structures, oxidizing the substrate within the first and second trenches, and then depositing insulative material within the first and second trenches; and wherein the lateral recessing of the second nitride-containing structures is a second lateral recessing; wherein the oxidizing of the substrate within the first and second trenches is a second oxidizing; and further comprising: