Patent ID: 6627511
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A method for fabricating a reduced stress isolation structure for a SOI device comprising the steps of:providing a semiconductor substrate having a buried region of silicon dioxide below a major surface and a silicon layer below the major surface and above the buried region of silicon dioxide; disposing a first layer on the major surface; disposing a second layer overlying the first layer, wherein the second layer has a first portion and a second portion; disposing a third layer overlying the second layer, wherein the third layer has a first portion and a second portion; removing the first portion of the third layer; removing the first portion of the second layer; oxidizing the semiconductor substrate to form an isolation structure, a portion of the isolation structure protrudes above the major surface of the semiconductor substrate and is overlying an edge of the silicon layer; removing the second portion of the third layer; and removing the second portion of the second layer.