Patent ID: 9094142
Filing Date: 2015-07-28
Classification: H04J,H04L

Abstract:
1. A method of providing a path delay asymmetry for time synchronization between a master clock at a first client node and a slave clock at a second client node across server communications network, the method comprising: mapping a first time protocol signal carrying time protocol data of the master clock onto a first transmission signal for transmission across the server communications network to the second client node, determining a forward mapping delay incurred as a result of said mapping and providing the forward mapping delay to a path delay asymmetry calculation element; mapping a second time protocol signal carrying time protocol data of the slave clock onto a second transmission signal for transmission across the server communications network to the first client node, determining a reverse mapping delay incurred as a result of said mapping and providing the reverse mapping delay to the path delay asymmetry calculation element; applying forward error correction, FEC, to the first transmission signal before said transmission, determining a forward FEC delay incurred as a result of applying said FEC to the second transmission signal, and providing the forward FEC delay to the path delay asymmetry calculation element; applying FEC to the second transmission signal before said transmission, determining a reverse FEC delay incurred as a result of applying said FEC to the second transmission signal, and providing the reverse FEC delay to the path delay asymmetry calculation element; at the path delay asymmetry calculation element, calculating a path delay asymmetry in dependence on the forward mapping delay, the reverse mapping delay, the forward FEC delay and the reverse FEC delay; and providing the path delay asymmetry to a time protocol client at the second client node.