Patent ID: 6281075
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A method of making a flash EEPROM system on an integrated circuit substrate, comprising:forming parallel source and drain regions in the substrate that are elongated in a first direction and spaced apart in a second direction that is orthogonal to the first direction,oxidizing a first exposed surface area of the substrate to grow a layer of floating gate oxide thereon,depositing on the gate oxide a conductive material to form an array of memory cell floating gates that individually extend at least a portion of the space between the source and drain regions in said second direction,depositing a layer of dielectric material over the floating gate array in a manner to present a barrier to oxygen migration to the gate oxide as the structure is oxidized during subsequent processing,oxidizing a second exposed surface of the substrate adjacent the floating gate array to grow a layer of gate oxide of peripheral transistors with the dielectric barrier layer in place, thereby preventing further growth of the floating gate oxide while the peripheral transistor gate oxide is being grown, andthereafter removing a majority of the oxygen barrier layer by anisotropically etching said layer in a manner that leaves a portion of the layer as dielectric spacers along edges of the memory cells.