Patent ID: 9087605
Filing Date: 2015-07-21
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit device, comprising: a wiring pair; a first transistor group having a source or a drain coupled to one of the wiring pair; a second transistor group having a source or a drain coupled to the other of the wiring pair; a first diffusion layer group in which the first transistor group is formed; a second diffusion layer group in which the second transistor group is formed, wherein the first diffusion layer group includes a first common diffusion layer group that is included in the first transistor group and in which a plurality of transistors sharing a source or a drain is formed, wherein the second diffusion layer group includes a second common diffusion layer group that is included in the second transistor group and in which a plurality of transistors sharing a source or a drain is formed, and wherein a first capacitive load of the one of the wiring pair is balanced with a second capacitive load of the other of the wiring pair; and a plurality of memory cell arrays aligned in a first direction, wherein the first and second diffusion layer groups are alternately arranged in the first direction, and wherein total number of wirings coupling the first transistor group and the second transistor group with the one of the wiring pair and the other of the wiring pair, respectively, has an antisymmetric relationship.