Patent ID: 6087220
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method of forming a memory array, comprising the steps of:etching with a substantially nonselective etch process a semiconductor substrate having a first conductive layer formed outwardly from a surface of the semiconductor substrate and a second conductor layer formed outwardly from the first conductive layer wherein the first conductive layer is discontinuous such that portions of the second conductive layer are not separated from the surface of the semiconductor substrate by the first conductive layer, the first and second conductive layers separated by an interstitial dielectric layer, the substantially nonselective etch process operating to create a substantially planar layer having exposed portions of the first and second conductive layers through the nonselective etching of the first conductive layer, the interstitial dielectric layer and the second conductive layer; andetching the substantially planar outer surface with a second etch process highly selective to dielectric material such that the remaining portions of the first and second conductive layer are removed, the first conductive layer separated from the substrate surface by a gate dielectric layer, the second etch process operable to expose but not substantially etch the gate dielectric layer.