Patent ID: 7180966
Filing Date: 2007-02-20
Classification: H04L

Abstract:
1. A transition detection, validation and memorization circuit for detecting a transition in an incoming serial binary data stream that is over sampled to produce a set of over sampled signals and for generating a control signal indicating which sampled signal is the best for subsequent processing, comprising: a data input for receiving a set of over sampled signals obtained from a stream of binary data serially transmitted on a high speed serial communication link at a specified data rate that is over sampled by n phases of a reference clock signal generated by a multiphase clock signal generator having a determined clock period; n transition detection means, coupled to said multiphase clock signal generator and to said data input, for detecting a transition at a position of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on five consecutive over sampled signals; n validation means, coupled to said multiphase clock signal generator and to said transition detection means, for validating the position of the latest detection as the transition position; and, n memorization means, coupled to said multiphase clock signal generator and to said validation means, for memorizing the position of said latest detection to generate corresponding select signals, only one of which representing a determined delay with respect to the memorized transition position, thereby indicating which sampled signal is the best to be retained; and wherein the specific signal processing comprises rules such that if for an over sampled signal S are verified, thereby, that a transition has occurred for over sampled signal S i and another will be detected for over sampled signal S i+1 .