Patent ID: 7447842
Filing Date: 2008-11-04
Classification: G06F

Abstract:
1. A method for operating a mass memory device having a plurality of mass memories and at least two bridge controllers which can be used to address the mass memories, the method comprising the steps of: providing a first common cache memory unit associated with the at least two bridge controllers and a second common cache memory unit associated with the first common cache memory unit, each of said first and second common cache memory units being not internal to any of the at least two bridge controllers; initially storing on the first common cache memory unit all data to be stored in the mass memories; and then storing in the mass memories the data initially stored in the first common cache memory unit, wherein the data to be stored in the first common cache memory unit are mirrored on the second common cache memory unit, and wherein the second common cache memory unit adopts the functionality of the first common cache memory unit transparently and without delay in the event of failure of the first common cache memory unit.