Patent ID: 7057223
Filing Date: 2006-06-06
Classification: H01L

Abstract:
1. A memory device comprising: a substrate; a plurality of memory cells, each of the memory cells including capacitor, and a transistor formed vertically from the substrate, the transistor including a first source/drain region, a body region, and a second source/drain region, the capacitor including a first capacitor plate integral with the second source/drain region, and a second capacitor plate separate from the first capacitor plate; a metal contact for providing an ohmic contact for the second capacitor plate on a surface of the substrate; a plurality of trenches dividing the memory cells into rows and columns, wherein the second capacitor plate of the capacitor of each of the memory cells is formed in the trenches; a plurality of word lines for accessing the memory cells; and a plurality of bit lines for exchanging data with the memory cells.