Patent ID: 6281061
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A method for fabricating an isolation trench applied in BiCMOS processes on a semiconductor substrate, comprising the following steps of:forming a first oxide layer on the semiconductor substrate to isolate a bipolar junction transistor (BJT) region, a first MOS transistor region, and a second MOS transistor region, wherein the second MOS transistor region is formed between the BJT region and the first MOS transistor region;forming a buried layer of a first conductivity type in the BJT region and the first MOS transistor region, and forming a buried layer of a second conductivity type in the second MOS transistor region;forming an epitaxy layer on the buried layers of the first and the second conductivity type, and forming a polysilicon layer on the first oxide layer;forming a second oxide layer on the polysilicon layer;forming a first well and a second well of a first conductivity type in the epitaxy layer above the BJT region and the first MOS transistor region;forming a collector region in the first well;forming a third well of a second conductivity type in the epitaxy layer above the second MOS transistor region;forming an etching stop layer on the second oxide layer, the first well and the second well, conformally;forming a first trench and a second trench exposing the surface of the first oxide layer by removing the etching stop layer, the second oxide layer, and the polysilicon layer, and forming a third trench by removing the etching stop layer adjacent to the collector region in the first well;filling a third oxide layer into the first, the second, and the third trench for isolating; andremoving the remaining etching stop layer.