Patent ID: 8183611
Filing Date: 2012-05-22
Classification: G11C,H01L,Y10S

Abstract:
1. A spin transistor, comprising: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having a gate voltage applied thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes, a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.