Patent ID: 9088610
Filing Date: 2015-07-21
Classification: H04L

Abstract:
1. An apparatus for accelerating communications over the Ethernet between a first processor and a second processor where the communications include CIP messages, the apparatus comprising: a network accelerator that includes memory locations, the network accelerator in communication with the first processor and the second processor and programmed to, when the second processor transmits a data packet to the first processor over the Ethernet: (a) intercept the data packet at a first processor end of the Ethernet; (b) extract a CIP message from the data packet; (c) parse the CIP message to generate application specific data; (d) store the application specific data in the memory locations; and (e) provide a signal to the first processor indicating that the application specific data for the first processor is stored in the memory locations; wherein the memory locations include dual port shared buffers, the dual port shared buffers include at least first and second different classes of shared buffers, and different priority data is stored in the at least first and second different classes of shared buffers; the first processor to access the application specific data in the dual port shared buffers after receiving the signal from the network accelerator indicating that the application specific data for the first processor is stored in the dual port shared buffers, the first processor to then generate data to be transmitted to the second processor and stores the generated data in the dual port shared buffers, the shared buffers further including at least three mailboxes, the at least three mailboxes for storing at least three data classes, the at least three data classes selected from at least three of cyclic data, event data, service data and explicit data; and the network accelerator to receive a signal from the first processor indicating that the generated data is in the dual port shared buffers, the network accelerator to then retrieve the generated data from the dual port shared buffers and transmit the generated data to the second processor.