Patent ID: 6557158
Filing Date: 2003-04-29
Classification: G06F

Abstract:
A scheduling method for high-level synthesis of a circuit which is represented by an operation description, the method comprising the steps of:(a) calculating a probability for each of a plurality of nodes included in a control flow graph to be assigned to a time step; (b) calculating a sum of the probabilities for each time step; (c) calculating, for each node having a scheduling candidate in a time step for which the sum of probabilities is maximum, an estimated value of an area of the circuit with the node having been temporarily assigned to the scheduling candidate; (d) retrieving a combination of a node and a scheduling candidate for which the estimated value is maximum; and (e) narrowing down a list of scheduling candidates of the node in the combination by excluding the scheduling candidate in the combination from the list of scheduling candidates of the node in the combination.