Patent ID: 6081872
Filing Date: 2000-06-27
Classification: G06F

Abstract:
A computer memory system having a hierarchy comprising:a level one (L1) cache with access/cycle time equal to or faster than a processor cycle time which can deliver at least a logical word or words needed by the processor on each cycle for an L1 HIT; andan L2 cache including a directory and data array in which the L2 directory is accessed for a MISS to the L1 cache, the L2 data array having a mapping from the L2 directory to the data array such that at least one block needs to be accessed from the data array, the L2 directory performing required address translation and, upon a HIT, enables the L2 array for a specific block required for reloading into the L1 cache, and upon a MISS, the L2 cache requests a block reload from a next level of the hierarchy, wherein the L2 cache directory has an access time greater than one processor cycle and a cycle time equal to one processor cycle, the directory and associated logic of the L2 cache being a pipelined design to allow a new access to start each cycle by starting the L2 cache data array and the L2 cache directory at the same time as an L1 cache access, the L2 data array implementing an early-select structure and organization to allow the array to start an access on each L1 cache cycle, to abort data array access at an end of one cycle if a HIT in L1 cache or MISS in L2 cache directory with no cast out, and to continue and complete a block access for a MISS in L1 cache and a HIT in L2 cache directories, thereby saving at least one cycle or more of data array access for a block reload access.