Patent ID: 8638931
Filing Date: 2014-01-28
Classification: G06F

Abstract:
1. A system, comprising: a controller component configured to control at least one memory device to facilitate communication of data between a host processor and the at least one memory device, wherein the at least one memory device includes a predefined number of data lines utilized to communicate data signals; and a descrambler component configured to receive pattern information that facilitates a determination of a bit order of the data signals associated with the at least one memory device from the at least one memory device, determine the bit order of the data signals associated with the at least one memory device in order of relative bit significance of the data signals to each other from a most significant bit down to a least significant bit based at least in part on the pattern information, and generate a transformation function based at least in part on the bit order of the data signals associated with the at least one memory device, wherein the transformation function facilitates rearrangement of the data signals from an original order to a transformed order that results in the data signals associated with the at least one memory device being arranged from the most significant bit down to the least significant bit to correspond with a bit order of the host processor, in accordance with the bit order of the data signals, to enable the data signals to be presented in parallel in the transformed order from the most significant bit down to the least significant bit, and wherein the descrambler component is configured to be associated with the controller component.