Patent ID: 6154083
Filing Date: 2000-11-28
Classification: H03K,H03L

Abstract:
A ground bounce control circuit for reducing ground and/or power supply bounce in an integrated circuit wherein a plurality of output drivers, each of said output drivers being associated with a corresponding I/O cell included in the integrated circuit are connected to an output pad of the integrated circuit, the ground bounce control circuit comprising:a replica I/O cell that delays a test signal clock by a desired delay amount based upon a bias signal provided to the replica I/O cell;a precision delay control that delays the test signal clock by a precision delay amount;a delay locked loop (DLL) that compares the desired delay amount and the precision delay amount and generates a digital control signal that corresponds to a difference between the desired delay amount and the precision delay amount;a digital-to-analog converter that converts the digital control signal to the bias signal provided to the replica I/O cell; anda current mirror circuit that responds to the bias signal by generating a plurality of bias current signals, each of said bias current signals being provided to a corresponding one of the I/O cells of the integrated circuit to control the delay through said corresponding I/O cell.