Patent ID: 6909312
Filing Date: 2005-06-21
Classification: H03L

Abstract:
1. A synchronization circuit, comprising: a reference pulse; a first variable delay circuit for generating a first pulse to be synchronized with said reference pulse, a second pulse which is leading in phase for a certain period relative to said first pulse, and a third pulse which is delayed in phase for a certain period from said first pulse; a first phase comparing circuit for comparing said reference pulse with said first pulse; a second phase comparing circuit for comparing said reference pulse and said second pulse and said third pulse; and a control voltage generating circuit for generating a control voltage for controlling said first variable delay circuit in response to a comparison output of said first phase comparing circuit and a comparison output of said second phase comparing circuit; wherein said control voltage generating circuit generates said control voltage by giving priority to the comparison output of said second phase comparing circuit with respect to the comparison output of said first phase comparing circuit, and also generates, after said reference pulse and said second pulse or third pulse are matched in phase at said second phase comparing circuit, said control voltage by the comparison output of said first phase comparing circuit.