Patent ID: 6153483
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method for manufacturing MOS device, comprising the steps of:providing a substrate that has a gate and an isolation structure thereon and a lightly doped source/drain region already defined;forming a film silicon nitride layer over the substrate;carrying out an anisotropic etching operation to remove a portion of the silicon nitride film layer, thereby reducing a thickness of the silicon nitride film layer; andcarrying out an isotropic etching operation to remove another portion of the silicon nitride film layer, thereby forming spacers on sidewalls of the gate, wherein each spacer has a wall section that implanted ions can penetrate through a far side away from the gate; andforming a source/drain region having a graded cross-sectional doping profile in the substrate on each side of the gate, wherein the source/drain region comprises a heavily doped region extending under the wall section of the spacer.