Patent ID: 9041181
Filing Date: 2015-05-26
Classification: H01L,Y10S

Abstract:
1. A land grid array (LGA) package, comprising: a substrate comprising a plurality of lands formed on a first surface of the substrate; a semiconductor chip mounted on a second surface of the substrate; a connection portion connecting the semiconductor chip and the substrate; a first solder resist formed on a surface of a first land at a first end of the first land and a second solder resist formed on the surface of the first land at a second end of the first land, wherein the first and second ends are opposite each other; and a support layer formed on part of the surface of the first land between the first solder resist and the second solder resist, wherein the support layer comprises a plurality of separate layers, and wherein a width of the first land between the first solder resist and the second solder resist is about 0.7 mm or higher.