Patent ID: 6856184
Filing Date: 2005-02-15
Classification: G06F

Abstract:
1. A system comprising: a first circuit configured to receive a first clock signal and generate a first set of encoded signals in response to a positive edge of the first clock signal; a second circuit configured to receive the first clock signal and configured to generate a second set of encoded signals in response to a negative edge of the first clock signal; a third circuit configured to receive the first set of encoded signals and the second set of encoded signals and configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals; and a fourth circuit configured to receive the first pulse signal and the second pulse signal, and configured to generate a second clock signal in response to the first pulse signal and the second pulse signal; wherein the first set of encoded signals and the second set of encoded signals each include n encoded signals, wherein the second clock signal has a frequency that is one divided by n of a frequency of the first clock signal, and wherein n is an integer greater than or equal to one.