Patent ID: 6555467
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A method of forming an inter-level insulator structure comprising the steps of:a) providing a first metal layer overlying a substrate; b) depositing a first sacrificial layer overlying the first metal layer; c) depositing an etch stop overlying the first metal layer; d) depositing a second sacrificial layer overlying the etch stop; e) forming a double layer hard mask overlying the second sacrificial layer; f) patterning the double layer hard mask to produce a via mask and a trench mask; g) etching the second sacrificial layer to form a partial via down to the etch stop; h) etching an exposed portion of the etch stop; i) etching the first sacrificial layer to form a via, whereby the first metal layer is exposed; j) etching the second sacrificial layer to form a trench; k) depositing a barrier metal and copper; l) planarizing the barrier metal and copper to form a second metal layer; and m) decomposing the first and second sacrificial layer, whereby the first sacrificial layer and the second sacrificial layer are replaced by air gaps.