Patent ID: 6191762
Filing Date: 2001-02-20
Classification: G09G

Abstract:
A timing control circuit for a plasma display panel which includes at least a frame memory means, a data interfacing means and an address electrode driving means, comprising:a first pulse signal generating means for generating a first pulse signal whose level is periodically logic-high with correspondence to a first time interval within which the data interfacing means receives a video data of a whole horizontal line of a plasma panel from the frame memory means;a second pulse signal generating means for generating a second pulse signal whose level is periodically logic-high with correspondence to a second time interval within which the data interfacing means transfers the video data of the whole horizontal line of the plasma panel to the address electrode driving means;a third pulse signal generating means for generating a third pulse signal whose level is periodically logic-high with correspondence to a third time interval within which the data interfacing means receives the video data of the whole horizontal line of the plasma panel from the frame memory means and transfers the video data of whole horizontal line of the plasma panel to the address electrode driving means;a clock signal generating means for generating a first clock signal which includes an N+1 number of pulses, where the numerical value N is the number of the whole horizontal line of the plasma panel, during a time when a level of the third pulse signal is logic-high;a first logic-ANDing means for producing a second clock signal by logically multiplying the first pulse signal by the first clock signal; anda second logic-ANDing means for producing a third clock signal by logically multiplying the second pulse signal by the first clock signal,wherein the second clock signal, the third clock signal and the first clock signal are provided to the frame memory means, the address electrode driving means and the data interfacing means, respectively, and the data interfacing means simultaneously performs an operation of receiving a data of one horizontal line per a period from the frame memory means and an operation of transferring a data received during a previous period from the frame memory.