Patent ID: 6404242
Filing Date: 2002-06-11
Classification: H03K

Abstract:
A comparator circuit, comprising:an input for receiving an input signal; an output terminal outputting an output signal; a first comparator connected to said input and receiving the input signal, when the input signal exceeds a threshold value T1, said first comparator generates a first output signal switching from a first logic signal to a second logic signal, in which case a switching of the output signal from the first logic signal to the second logic signal can be initiated only by said first comparator switching from the first logic signal to the second logic signal; a monitoring circuit connected between said input and said output terminal, said monitoring circuit, including: a second comparator connected to said input and has a switching hysteresis with a switching-on threshold T2 and a switching-off threshold T3, where T2>T3, said second comparator and said first comparator each have an output; an output circuit; and a logic circuit connected to said output circuit, to said output of said first comparator, and to said output of said second comparator, said logic circuit links said output of said first comparator and said second comparator to said output circuit in such a manner that, when the input signal exceeds the threshold value T1, said output circuit emits the second logic signal and then remains inhibited against returning to the first logic signal until the input signal has once again fallen below the threshold value T1, after exceeding the switching-on threshold value T2; and a reset circuit connected to said output circuit and said logic circuit, said reset circuit able to reset said output circuit to a quiescent state irrespective of a state of said first comparator and said second comparator, and in the quiescent state the output signal at said output terminal is at the first logic signal, and the output circuit maintains its present state until said first comparator and said second comparator output signals being the first logic signal.