Patent ID: 6304943
Filing Date: 2001-10-16
Classification: G06F,G11C,Y02D

Abstract:
A semiconductor storage device comprising a memory cell array including memory cells aligned in an array, each of said memory cells connected with each interconnection point between plural word lines extending in a row direction and plural bit line pairs extending in a column direction,wherein one word line is selected among said plural word lines for selecting memory cells aligned in one row connected with said selected word line, and data are read from and written in said selected memory cells through bit line pairs connected with said selected memory cells,said memory cell array is provided with a specific memory cell row including at least one row of memory cells extending in the row direction, andsaid semiconductor storage device is further provided with writing means for writing all data of said memory cells aligned in one row and selected by said selected word line in said specific memory cell row through said bit line pairs connected with said selected memory cells;wherein the data of said memory cell aligned in one row and selected by said selected word line are read through said bit line pairs connected with said selected memory cells regardless of an operation of Said writing means, andsaid writing means selects said specific memory cell row in reading the data of said selected memory cell aligned in one row, and writes all the data of said selected memory cells aligned in one row in said one row of memory cells included in said specific memory cell row through said bit line pairs connected with said selected memory cells.