Patent ID: 6987300
Filing Date: 2006-01-17
Classification: H01L

Abstract:
1. An ESD-protection structure, comprising: an integrated circuit having a lighter doped p-silicon well (P-well); a first lighter doped n-silicon well (first N-well) in the P-well; a plurality of first heavier doped p-silicon diffusions (first P+ diffusions) in the first N-well; a first heavier doped n-silicon diffusion (first N+ diffusion) in the first N-well, wherein the first N+ diffusion surrounds the plurality of first P+ diffusions; a second lighter doped n-silicon well (second N-well) in the P-well, the second N-well adjacent to the first N-well; a second heavier doped n-silicon diffusion (second N+ diffusion) in the second N-well, the second N+ diffusion is connected to the first N+ diffusion; a second heavier doped p-silicon diffusion (second P+ diffusion) in the second N-well; a third heavier doped p-silicon diffusion (third P+ diffusion) in the P-well, the third P+ diffusion is connected to the second P+ diffusion, wherein the third P+ diffusion surrounds the first N+ diffusion, the plurality of first P+ diffusions, the second N+ diffusion and the second P+ diffusion; a bond pad connected to the plurality of first P+ diffusions.