Patent ID: 6054871
Filing Date: 2000-04-25
Classification: G06F

Abstract:
A method of operating a field programmable gate array (FPGA), the method comprising the steps of:loading a first set of configuration data and a second set of configuration data into a local memory of the FPGA, wherein the local memory simultaneously stores the first and second sets of configuration data;configuring a function generator of the FPGA as a read only memory (ROM) look up table in response to the first set of configuration data, wherein the function generator provides an output signal which is a predetermined first function of a plurality of input signals, the first function being defined by a first set of state data values stored in the function generator;reconfiguring the function generator as a writable user RAM in response to the second set of configuration data;writing a second set of state data values to the function generator; and thenreconfiguring the function generator as a ROM look up table in response to the first set of configuration data, wherein the ROM look up table provides an output signal which is a predetermined second function of the plurality of input signals, the second function being defined by the second set of state data values.