Patent ID: 8892935
Filing Date: 2014-11-18
Classification: G06F,Y02D

Abstract:
1. A dynamic bus clock rate adjusting method to be executed by a bus controller and a central processing unit (CPU) that are electrically coupled together, the bus controller being further coupled electrically with a bus that is coupled electrically with a plurality of slave devices, and being able to control an operating clock rate of the bus, the method comprising the steps of: configuring the bus controller to generate, upon receipt of a request signal from one of the slave devices and according to the request signal, an access instruction including an address from which the request signal is sent; and configuring the CPU to determine, according to the access instruction, which of the slave devices the address of the access instruction corresponds so as to obtain a working clock rate thereof, and to set the bus controller according to the working clock rate thus obtained for the bus controller to adjust the operating clock rate of the bus according to the working clock rate, and to perform the access instruction on the slave device via the bus.