Patent ID: 9223665
Filing Date: 2015-12-29
Classification: G06F,G11C

Abstract:
1. An apparatus comprising: a first interface to communicate with a processing unit; a second interface to communicate with a memory device; a module coupled to the first and second interfaces and configured to obtain test information stored in the memory device and perform a testing of a memory structure of the memory device based at least in part on the test information, the module including an algorithmic pattern generator to generate test data for the testing of the memory structure, wherein the module is also configured to obtain repair information stored in the memory device and to replace accessing of a portion of the memory device during an operation with accessing of a spare portion during the operation based at least in part on the repair information; and conductive connections to couple to conductive paths of a base to allow the module to communicate with at least one of the processing unit and the memory device through the conductive connections and the conductive paths of the base.