Patent ID: 7487338
Filing Date: 2009-02-03
Classification: G06F

Abstract:
1. A data processor for executing an instruction including a first operation code and a second operation code, comprising: an instruction fetch unit fetching an instruction code; an instruction decode unit decoding the instruction code fetched by said instruction fetch unit; and an instruction execution unit executing the instruction in response to a result of decoding by said instruction decode unit, wherein said instruction decode unit includes: a first decoder decoding said first operation code; and a second decoder decoding said second operation code in parallel to decoding of said first operation code, said instruction execution unit includes: a first instruction execution unit executing the first operation code in response to a result of decoding by said first decoder; and a second instruction execution unit executing the second operation code in response to a result of decoding by said second decoder in parallel to execution of said first operation code, and said data processor further comprises a circuit, in the case that said second operation code indicates a modification of a content of an operation indicated by said first operation code, allowing said first instruction execution unit to execute a modified operation indicated by said first operation code, wherein said first operation code is capable of specifying an operation independent of said second operation code.