Patent ID: 9059208
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a first disposable gate stack structure comprising a first disposable gate material portion and a second disposable gate stack structure comprising a second disposable gate material portion in a first device region and in a second device region, respectively, on a semiconductor substrate, wherein said forming said first disposable gate stack structure and said second disposable gate stack structure comprises providing a first disposable gate material layer in said first device region and a second disposable gate material layer in said second device region, wherein one of said first disposable gate material layer or said second disposable gate material layer has a protruding portion, performing a touch-up planarization process to remove said protruding portion and to provide said first disposable gate material layer and said second disposable gate material layer with topmost surfaces that are coplanar to each other, and patterning said first disposable gate material layer and said second disposable gate material layer to provide said first disposable gate material portion and said second disposable gate material portion; depositing a planarization dielectric layer over said first and second disposable gate stack structures; physically exposing top surfaces of said first and second disposable gate stack structures by planarizing said planarization dielectric layer; replacing said first disposable gate stack structure with a first replacement gate stack structure employing a step of removing said first disposable gate stack through a simultaneous exposure of said first disposable gate structure and said second disposable gate structure to a same etch chemistry in an etch process, wherein at least a predominant portion of said second disposable gate stack structure remains within said planarization dielectric layer after said etch process; and replacing said second disposable gate stack structure with a second replacement gate stack structure while said first replacement gate stack structure remains within said planarization dielectric layer.