Patent ID: 6212491
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A method for adjusting a counting rate of an instrumentation entity during simulation of a digital circuit design,wherein said digital circuit design including a design entity that is sequenced in accordance with a design cycle, wherein said design cycle is a multiple of a simulator cycle, said method comprising the steps of:asserting a count event signal within said instrumentation entity in response to an occurrence of an event within said design entity;generating a sampling signal having a cycle period equal to a period of said design cycle, wherein each cycle of said sampling signal includes a sampling pulse during which said sampling signal is asserted;comparing said sampling signal with said count event signal over said design cycle to determine whether both said sampling signal and said count event signal are asserted; andin response to detecting that both said sampling signal and said count event signal are asserted, incrementing a counter, such that said counter is incremented in accordance with said design cycle rather than said simulator cycle.