Patent ID: 6320575
Filing Date: 2001-11-20
Classification: G09G

Abstract:
A memory controller comprising a first counter and a second counter, each having reset and enable functions, a vertical synch signal detector and a horizontal synch signal detector, wherein a reset signal for said first counter is controlled by a signal detected by said vertical synch signal detector, an enable signal for said first counter and a reset signal for said second counter are controlled by a signal detected by said horizontal synch signal detector, an enable signal for said second counter is controlled in accordance with a signal indicating an image effective period, and a memory address is controlled by said first and second counters,wherein when the signal indicating an image effective period is LOW, said second counter starts to increment, carries out an increment of one line, and, when the signal indicating an image effective period is HIGH, finishes the increment, and before data input of next line starts, a horizontal synch signal is inputted into said second counter, and then when the reset signal is LOW, said second counter is reset and said first counter starts to increment, and next, when the signal indicating an image effective period is LOW, said second counter starts to increment again.