Patent ID: 7551499
Filing Date: 2009-06-23
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory core; a multi-step data input/output circuit that transfers data written to the memory core through one data path or that transfers data read from the memory core through the one data path; a normal-frequency clock unit that receives an external clock signal and outputs an internal normal-frequency clock signal; a command interpreter that receives a plurality of external control signals and generates a control command; an MRS command processor that outputs a low-frequency operation control signal when an MRS command included in the control command designates a low-frequency test operation; a low-frequency command generator that converts the control command into a low-frequency control command and that outputs the low-frequency control command to the multi-step data input/output circuit; a command path selector that transfers the control command to the multi-step data input/output circuit, or that transmits the control command to the low-frequency command generator in response to the low-frequency operation control signal; and a low-frequency clock unit that generates an internal low-frequency clock signal in response to the low-frequency operation control signal and that provides the internal low-frequency clock signal to the multi-step data input/output circuit, wherein the low-frequency clock unit controls a phase of the internal low-frequency clock signal to synchronize the internal low-frequency clock signal with the low-frequency control command, and wherein the one data path receives the data, the control command and the internal normal-frequency clock signal when a normal-frequency operation is performed, and the one data path receives the data, the low-frequency control command and the internal low-frequency clock signal when the low-frequency test operation is performed.