Patent ID: 7095653
Filing Date: 2006-08-22
Classification: G11C

Abstract:
1. A flash memory device comprising: a plurality of n-wells comprising an n-type conductivity material formed in a p-type substrate; a plurality of p-wells comprising a p-type conductivity material, each p-well located within a different n-well; a plurality of flash memory array blocks, each comprising a plurality of flash memory cells arranged in rows that are coupled together by a first set of wordlines of a plurality of sets of wordlines, each flash memory array block located within a different p-well of the plurality of p-wells wherein a voltage differential of 5V is applied between the n-well and the p-well of an unselected flash memory array block during an erase operation; and a first row decoder coupled to the plurality of memory array blocks through the first set of wordlines, external address signals coupled to the first row decoder such that a wordline of the first set of wordlines is selected in response to the address signals.