Patent ID: 6514673
Filing Date: 2003-02-04
Classification: B24B,H01L

Abstract:
A method for predicting an optimum thickness, OT, of dielectric material that is to be removed from an integrated circuit wafer, said wafer having a total area, active areas, and shallow trenches that have been overfilled with said dielectric, comprising:providing a first mask, suitable for photolithography, that defines the shallow trenches and the active areas; determining the percentage, PA, of said active areas relative to the total area; providing a second mask, suitable for photolithography, whereby sub-areas, wholly within and of lesser area than, said active areas may be selectively etched away; determining the percentage, PS, of said sub-areas relative to the total area; and computing OT from a formula OT={K1Ã—PAÃ—(100âˆ’PS)}+K2, where K1 and K2 are slope and Y intercept, respectively, read off an experimental plot of OT versus PAÃ—(100âˆ’PS).