Patent ID: 8751995
Filing Date: 2014-06-10
Classification: G06F

Abstract:
1. A non-transitory computer-readable medium containing instructions, which when read and executed by a computer, cause the computer to execute a method of common-centroid IC layout, wherein the method comprises steps of: acquiring a netlist of an circuit-element set, the netlist at least containing the number of unit element corresponding to each element of the circuit-element set; summing up the numbers of the unit elements of all elements of the circuit-element set to get the total number of the unit elements and, based on said total number of the unit elements, determining a unit element array, having an aspect ratio closest to 1 by an algorithm, the aspect ratio being a ratio of the number of the unit elements at a column of the unit element array to the number of the unit elements at a row of the unit element array; generating multiple common-centroid placements according to the umnnlement array and applying global routing assignment to each of the common-centroid placements where each of the common-centroid placements is formed of multiple nets, each of which is formed of multiple unit element; performing cost evaluation by applying a cost calculation to each common-centroid placement to get a corresponsive value, which can be used for evaluating matching quality of each common-centroid placement and the induced parasitics incurred by the global routing assignment; and comparing the values acquired from all of the common-centroid placements according to the cost evaluation and select the common-centroid placement to which one of the values corresponds according to a predetermined condition for detailed routing assignment.