Patent ID: 6146955
Filing Date: 2000-11-14
Classification: H01L

Abstract:
A method for forming a dynamic random access memory device, comprising the following steps:providing a substrate with an isolation structure;forming a first oxide layer with a first opening exposing a first portion of the substrate on the substrate;forming a pad oxide layer on the first portion of the substrate;forming a first spacer on a sidewall of the first opening;removing a portion of the pad oxide layer to expose a second portion of the substrate;forming a gate oxide layer on the second portion of the substrate;forming a first conductive layer within the first opening, wherein a surface of the first conductive layer is as high as that of the first oxide layer;forming a silicide layer on the first conductive layer;forming a second opening in the first oxide layer to expose a third portion of the substrate;forming a second oxide layer on the third portion of the substrate;forming a second spacer on a sidewall of the second opening;removing a portion of the second oxide layer to form a first contact opening, wherein the first contact opening exposes the substrate;forming a first doped region under the first contact opening in the substrate;forming a second conductive layer within the first contact opening, wherein a surface of the second conductive layer is as high as that of the first oxide layer;removing the first oxide layer and the first spacer;performing an ion implantation process to form a second doped region and a third region in the substrate;forming a first dielectric layer with a second contact opening exposing the second conductive layer over the substrate;forming a bitline within the second contact opening, wherein the bitline couples with the first doped region via the second conductive layer;forming a second dielectric layer over the substrate;forming a storage node opening in the second dielectric layer and the first dielectric layer to expose the third doped region; andforming a storage node within the storage node opening, wherein the storage node couples with the third doped region.