Patent ID: 6025728
Filing Date: 2000-02-15
Classification: G01R,H01L

Abstract:
A semiconductor package comprising:a base for retaining a semiconductor die comprising a plurality of contacts, the base comprising a plurality of first conductors;an interconnect on the base comprising a plurality of contact members for electrically contacting the contacts on the die, and a plurality of second conductors in electrical communication with the contact members;a plurality of wires bonded to the base and to the interconnect for electrically connecting the first conductors to the second conductors;a cover and a force applying member on the base configured to bias the die and the interconnect together; anda plate on the base comprising an opening aligned with the interconnect, the opening larger than the die but smaller than the interconnect to permit placement of the die on the interconnect, the base and the plate substantially enclosing the wires.