Patent ID: 6177298
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method of manufacturing an electrostatic discharge (ESD) protection circuit for an integrated circuit comprising the steps of:providing a semiconductor substrate of a first conductivity type;doping a portion of the semiconductor substrate with a dopant of a second conductivity type to form a first doped region;doping a portion of the semiconductor substrate and a portion of the first doped region with a dopant of the second conductivity type to form a second doped region;doping a portion of the first doped region with a dopant of the first conductivity type to form a third doped region that is an emitter of a first transistor, the base of the first transistor formed by the first doped region and the collector formed by the substrate;doping portions of the semiconductor substrate with a dopant of the second conductivity type to form a fourth doped region that is an emitter of a second transistor, the base of the second transistor formed by the substrate and the collector formed by the first doped region; anddoping portions of the semiconductor substrate with a dopant of the first conductivity type to form a fifth doped region for contacting an anode of the diode formed between the substrate and the second doped region.