Patent ID: 6327179
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A semiconductor memory device comprising a memory cell array having arranged memory transistors and selecting gate transistors of nonvolatile memory cells,each said memory transistor and each said selecting gate transistor having a first-layer gate electrode material film which is formed on a semiconductor substrate via a gate insulating film, and second-layer and third-layer gate electrode material films which are stacked on said first-layer gate electrode material film via an interlayer dielectric film,each said memory transistor having a floating gate which is formed of said first-layer electrode material film, and a control gate which is formed of a laminated film of said second-layer and third-layer gate electrode material films, andeach said selecting gate transistor having a gate electrode which is formed of said first-layer to third-layer electrode material films while said third-layer gate electrode material film contacts said first-layer gate electrode material film via an opening which is formed in said second-layer gate electrode material film and said interlayer insulating film.