Patent ID: 6822900
Filing Date: 2004-11-23
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array region in which are disposed a plurality of memory cells in both a column direction and a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates; and a control gate drive section which drives the first and second control gates of the memory cells within the memory cell array region, wherein the memory cell array region is divided in the row direction into a plurality of sector regions;wherein each of the sector regions is divided into a plurality of blocks in the row direction; and wherein the control gate drive section has a plurality of control gate drivers for each of the sector regions, and each of the control gate drivers is disposed to correspond to at least one block of the plurality of blocks, to set the potentials of the first and second control gates of all the memory cells within the corresponding block.