Patent ID: 6475890
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A method for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, the method including the steps of:A. forming a pillar of semiconductor material on a layer of buried insulating material, wherein said pillar has a top surface and first and second side surfaces, and wherein said pillar has a width, a length, and a height; B. forming a masking structure on a center portion of said top surface of said pillar along said length of said pillar; C. etching a top portion of said height of said pillar from exposed surfaces of said top surface of said pillar down to a bottom portion of said height of said pillar to form an upside down T-shape for said pillar; D. removing said masking structure from said top of said pillar to expose said top surface of said upside down T-shaped pillar; E. depositing a gate dielectric material on any exposed surface of said semiconductor material of said upside down T-shaped pillar for a gate length along said length of said upside down T-shaped pillar; wherein said semiconductor material of said upside down T-shaped pillar adjacent said gate dielectric material forms a channel region of said field effect transistor; F. depositing a gate electrode material on said gate dielectric material to surround said upside down T-shaped pillar for said gate length of said upside down T-shaped pillar; and G. implanting a drain and source dopant into exposed regions of said upside down T-shaped pillar to form a drain of said field effect transistor on a first side of said gate electrode material along said length of said upside down T-shaped pillar and to form a source of said field effect transistor on a second side of said gate electrode material along said length of said upside down T-shaped pillar.