Patent ID: 9006872
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A semiconductor chip package comprising: an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed on the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part; and a molding layer that is formed on a top surface of the insulation frame and a top surface of the semiconductor chip and allows the insulation frame and the semiconductor chip to be integrally formed with each other, wherein the molding layer is filled only in a space between the insulation frame and the semiconductor chip so that the top surface of the insulation frame, a top surface of the conductive part, and the top surface of the semiconductor chip are exposed.