Patent ID: 8773157
Filing Date: 2014-07-08
Classification: G01R,H01L

Abstract:
1. A method of performing at least one fault mode test on at least one of a plurality of through-silicon-vias arranged on a substrate in an integrated circuit, the method comprising: a) selecting, by a controller, a through-silicon-via to be tested from the plurality of through-silicon-vias; b) selecting, by the controller, a calibration mode (“CALIBRATE”) for the selected through-silicon-via, wherein the calibration mode comprises: d) selecting, by the controller, a measurement mode (“MEASURE”) for the selected through-silicon-via, wherein the measurement mode comprises: f) determining, by the test circuit, an actual measurement current using the determined calibration current measurement and the determined measurement current; and g) comparing, by the test circuit, the actual measurement current to a threshold in accordance with a screening condition for the selected through-silicon-via.