Patent ID: 6376346
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of fabricating a plurality of high voltage electrical devices, the method comprising:providing a substrate layer of a semiconductor material having a predetermined substrate layer conductive type, said substrate layer having upper and lower spaced and generally parallel surfaces; forming a second layer contiguous with the upper surface of said substrate layer said second layer having a predetermined second layer conductive type; forming a top layer containing dopant material in a predetermined pattern upon the upper surface of said second layer; heating the substrate layer, second layer, and top layer to form a diffusion region in said second layer, said diffusion region having a correlation to the predetermined pattern of the dopant material; thereby forming a pn junction between the substrate layer and said second layer; removing the top layer containing dopant material; and dividing the resultant substrate layer and second layer to form separate electrical devices.