Patent ID: 7994049
Filing Date: 2011-08-09
Classification: C23C,H01L

Abstract:
1. A manufacturing method of a semiconductor device in which a first field effect transistor having a first gate electrode is electrically isolated by an element isolation from a second field effect transistor having a second gate electrode, and a lead portion of the second gate electrode extending over the element isolation is electrically coupled, via a conductive member, to a semiconductor region serving as a source or drain of the first field effect transistor, the method comprising the steps of: (a) forming, in a main surface of a semiconductor substrate, the element isolation, first and second active regions of the semiconductor substrate being electrically isolated by the element isolation; (b) forming the first gate electrode of the first field effect transistor in the first active region, forming the second gate electrode of the second field effect transistor in the second active region, and extending the lead portion of the second gate electrode over the element isolation; (c) after the step (b), forming a first insulating film over the main surface of the semiconductor substrate and anisotropically etching the first insulating film to form sidewalls made of the first insulating film over respective side walls of the first and second gate electrodes; (d) after the step (c), forming a silicide layer over surfaces of the first gate electrode and the semiconductor region serving as a source or drain of the first field effect transistor and over surfaces of the second gate electrode and a semiconductor region serving as a source or drain of the second field effect transistor; (e) after the step (d), depositing a second insulating film over the main surface of the semiconductor substrate; (f) forming an opening portion from which a portion of the silicide layer over the semiconductor region serving as the source or drain of the first field effect transistor, a portion of the silicide layer over the lead portion of the second gate electrode of the second field effect transistor, and a sidewall portion of the second field effect transistor are exposed, by etching the second insulating film in a region extending over both a portion of the semiconductor region serving as the source or drain of the first field effect transistor and a portion of the lead portion of the second gate electrode of the second field effect transistor; (g) forming a first metal film over a bottom portion of the opening portion by a thermal reaction using a first reaction gas; (h) forming, over the first metal film, a second metal film by a plasma reaction using the first reaction gas; (i) subjecting a surface of the second metal film to thermal nitridation with a third reaction gas containing nitrogen; and (j) subjecting the surface of the second metal film to a plasma treatment with the third reaction gas to form a first metal nitride film over the surface of the second metal film, wherein the thermal nitridation time in the step (i) is from 10 to 75 seconds, and wherein the plasma treatment time in the step (j) is from 25 to 75 seconds.