Patent ID: 6342823
Filing Date: 2002-01-29
Classification: G06F

Abstract:
A method for reducing the computation complexity and improving the accuracy of delay and crosstalk calculations for transmission-lines of on-chip interconnections with frequency-dependent losses, comprising the steps of:providing a wiring plan for an integrated circuit having interconnected circuits and transmission lines; identifying a group of constituent parts of the integrated circuit, each of said parts having a restricted topology; defining a unique distributed network for each of said parts, each of said networks including dc resistance and high-frequency inductance values; associating an R(f) matrix and an L(f) matrix with each of the distributed networks, where the R(f) matrix is a matrix of frequency dependent resistance values, and the L(f) matrix is a matrix of frequency dependent inductance values; estimating delay and crosstalk of the interconnection on the basis of said associated R(f) and L(f) matrices; allowing a range of line dimensions within each of said constituent parts; and defining each distributed network in terms of unique two-dimensional to three-dimensional scaling constants.