Patent ID: 9224750
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A memory array, comprising: a plurality of ridge-shaped multi-layer stacks extending along a first direction; a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks, the hard mask layer including a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes; a memory layer disposed within trenches between the plurality of ridge-shaped multi-layer stacks, and covering sidewalls of the ridge-shaped multi-layer stacks; a plurality of conductive pillars disposed within the trenches, extending along a vertical direction of the ridge-shaped multi-layer stacks, and vertically aligned with the plurality of hard mask through holes, respectively; and a plurality of conductive stripes disposed on the hard mask layer and extending along the second direction, each conductive stripe being connected with a row of conductive pillars formed along the second direction.