Patent ID: 6711170
Filing Date: 2004-03-23
Classification: G06F,H04L

Abstract:
A switch comprising:a plurality of ingress ports; a plurality of egress ports; a memory shared by the plurality of ingress ports and the plurality of egress ports which stores an input data stream received from any of the plurality of ingress ports and provides an output data stream to any of the plurality of egress ports; and a packet storage manager which schedules a memory read operation for one of the plurality of egress ports and concurrently schedules a memory write operation for one of the plurality of ingress ports, a memory read operation and a memory write operation being scheduled for different portions of the memory in a single port cycle, the packet storage manager comprising: read address logic which selects a read address for a first location in the memory for the memory read operation dependent on the port cycle, the read address logic comprises: a port queue for each of the plurality of egress ports, the port queue storing the memory addresses of locations of data written to the memory by the packet storage manager dependent on the network destination in an incoming packet; and port queue select logic which selects a port queue from which to remove a memory read address dependent on the port cycle, the memory portion from which to read dependent on the memory read address removed from the head of the selected port queue; and write address logic which selects a write address for a second location in the memory for the memory write operation dependent on the read address selected by the read address logic.