Patent ID: 7159098
Filing Date: 2007-01-02
Classification: G06F

Abstract:
1. A microprocessor having an instruction cache for providing a plurality of instruction bytes in response to a fetch address, the microprocessor also having a branch predictor for predicting in response to the fetch address whether a branch instruction is present in the plurality of instruction bytes provided by the instruction cache and for providing a prediction of whether or not the branch instruction will be taken, the microprocessor also having branch control logic that provides an indication of whether or not the microprocessor fetched a plurality of instruction bytes from the instruction cache at a target address of the branch instruction in response to the prediction, comprising: an instruction buffer, comprising a plurality of stages each for buffering a plurality of instruction bytes received from the instruction cache; a branch indicator associated with each of said plurality of stages, for storing the indication of whether or not the microprocessor fetched a plurality of instruction bytes for storage in said instruction buffer from the instruction cache at the target address of the branch instruction buffered in said associated stage; instruction format logic, for examining said plurality of instruction bytes stored in a first at least one of said plurality of instruction buffer stages during a first clock cycle, for outputting a length of an instruction currently being formatted by said instruction format logic comprised in said first at least one of said plurality of instruction buffer stages, and for examining said plurality of instruction bytes stored in a second at least one of said plurality of instruction buffer stages during a second clock cycle subsequent to said first clock cycle; and a multiplexer, coupled between said instruction buffer and said instruction format logic, for selecting said first at least one of said plurality of stages for said instruction format logic to examine during said first clock cycle, and for selecting said second at least one of said plurality of stages for said instruction format logic to examine during said second clock cycle based on said branch indicator associated with said first at least one of said plurality of stages and based on said length of said currently formatted instruction output by said instruction format logic.