Patent ID: 8673722
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A fabrication method of a field effect transistor comprising a substrate, a source/drain, a gate dielectric laver, and a gate, wherein, an “L” shaped composite isolation laver, which envelops a part of a side face of the source/drain adjacent to a channel and a bottom of the source/drain, is arranged between the source/drain and the substrate, the composite isolation layer being divided into two layers, that is, an “L” shaped thin insulation layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source/drain, the method comprising the following steps: 1) forming a silicon oxide sacrificial gate on the substrate by deposition and etching, and etching the substrate by using the silicon oxide sacrificial gate as a mask to obtain a source/drain region recess; 2) forming a recess-shaped insulation thin layer on a surface of the source/drain region recess by means of low temperature thermal oxidation or deposition, and depositing a high stress material on the recess-shaped insulation thin layer to form a high stress layer; 3) depositing a polysilicon sacrificial layer on the high stress layer, and selectively etching the polysilicon sacrificial layer to a position that is a designed height of the “L” shaped composite isolation layer; 4) selectively etching the high stress layer by using the polysilicon sacrificial layer as a protection layer, removing the polysilicon sacrificial layer, and selectively etching the insulation thin layer by using the high stress layer as a protection layer to expose a channel region window, so as to obtain the “L” shaped composite isolation layer consisted of the thin insulation layer and the high stress layer; 5) epitaxially growing a source/drain region by using the exposed channel region window as a seed layer, performing an implantation for light doped drain, and then depositing a silicon nitride layer and performing a source/drain implantation by using the silicon nitride layer as a protection layer so as to form the source/drain; 6) continuously depositing the silicon nitride layer, and performing chemical mechanical polishing on the silicon nitride layer by using the silicon oxide sacrificial gate as a stop layer; 7) removing the silicon oxide sacrificial gate, performing a low temperature thermal oxidation to obtain a gate dielectric layer, depositing a polysilicon layer, and performing a chemical mechanical polishing by using the silicon nitride layer as a stop layer to obtain a polysilicon gate, so as to form the gate.