Patent ID: 8779476
Filing Date: 2014-07-15
Classification: G06F,H01L

Abstract:
1. A junction field effect transistor (JFET) having an upper surface, the JFET comprising: a source region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the source region having an inner edge and an outer edge; a drain region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the drain region having an inner edge and an outer edge; a channel region disposed under the source region and the drain region; a shallow trench isolation (STI) region comprising an insulator material, the STI region having an upper surface substantially coplanar with the upper surface of the JFET, the upper surface of the STI region extending from the inner edge of the source region to the inner edge of the drain region; and a quasi-buried upper gate disposed in the channel region, the quasi-buried upper gate positioned partially under the STI region, wherein the quasi-buried upper gate does not extend under a portion of the STI region proximate to the drain region, and wherein the quasi-buried upper gate extends at least partially along a substantially vertical sidewall of the STI region proximate to the source region.