Patent ID: 6130856
Filing Date: 2000-10-10
Classification: G11C

Abstract:
A synchronous dynamic random access memory integrated circuit responsive to a clock signal, comprising:a latency select circuit coupled to receive a first signal and producing a first latency select signal in response to the first signal;a plurality of latency circuits each coupled to receive the clock signal, commands and the first latency select signal, a first of the plurality of latency circuits producing a first set of control signals in response to the commands, the clock signal and the first latency select signal;a memory array;a data bus for providing data to and receiving data from the memory array; andan interface circuit coupled between the memory array and the data bus, the interface circuit further being coupled to receive the first set of control signals, the interface circuit controlling transfer of data between the data bus and the memory array in response to the received set of control signals.