Patent ID: 9082761
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a metal pad; a passivation layer comprising a portion over the metal pad; a first polymer layer over the passivation layer; a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer, wherein the first PPI is electrically connected to the metal pad; a dummy metal pad in the first polymer layer; a second polymer layer over the first polymer layer, the dummy metal pad, and the first PPI; an Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad; a package component comprising a surface conductive feature; and a solder region bonded to the surface conductive feature in the package component, wherein the solder region is electrically coupled to the dummy metal pad, and wherein the dummy metal pad and the solder region are electrically floating.