Patent ID: 6911964
Filing Date: 2005-06-28
Classification: G09G

Abstract:
1. An analog frame buffer pixel system, comprising: a first storage unit for storing first analog data; a first controller for enabling storage of the first analog data in the first storage unit; a second storage unit for storing a second analog data proportional to the first analog data and corresponding to a grayscale pixel value to be displayed; a display for displaying the pixel value corresponding to the second analog data stored in the second storage unit; a second controller to enable storage of the second analog data into the second storage unit; a drain unit for draining voltage from the second storage unit after the pixel value is displayed, wherein the first storage unit includes a transistor having a first terminal for storing the first analog data, a second terminal coupled to a supply potential, and a third terminal coupled to the second storage unit, said first terminal coupled to the first controller and corresponding to a gate of the transistor; and a capacitor coupled between the fist terminal of the transistor and a reference potential.