Patent ID: 6320785
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of data lines;a plurality of word lines;a plurality of memory cells, each of which is coupled to a corresponding data line and a corresponding word line, each of which includes a control gate and a floating gate, and each of which has a threshold voltage corresponding to data,wherein each of said plurality of memory cells has a threshold voltage in a first threshold voltage region as an erase state by executing an erase operation and has the threshold voltage in one of said first threshold voltage region, a second threshold voltage region and a third threshold voltage region by executing a write operation, andwherein an absolute value of the threshold voltage of said second threshold voltage region is between an absolute value of the threshold voltage of said first threshold voltage region and an absolute value of the threshold voltage of said third threshold voltage region;a plurality of data latch each of which is coupled to a corresponding data line and each of which store data to be written in memory cells coupled to a selected word line; anda write control circuit, which brings a threshold voltage of a first memory cell in said erase state and coupled to the selected word line to the threshold voltage in said third threshold voltage region and brings a threshold voltage of a second memory cell in said erase state and coupled to said selected word line in said second threshold voltage region thereafter, in accordance with data stored in said plurality of data latch, thereby to write in data corresponding to the threshold voltage in said third threshold voltage region to said first memory cell in said plurality of memory cells and to write in data corresponding to the threshold voltage in said second threshold voltage region to said second memory cell in said plurality of memory cells.