Patent ID: 9129981
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A method for fabricating a microelectronic package, comprising: producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within at least one redistribution layer built over a molded panel containing a plurality of semiconductor die, the molded panel having a frontside at which the plurality of semiconductor die is exposed, the at least one redistribution layer produced over the frontside of the molded panel and the plurality of semiconductor die; forming a molded radiofrequency (RF) stand-off layer over the frontside of the molded panel and on the at least one redistribution layer such that the plurality of vertically-elongated contacts extends through the molded RF stand-off layer; and providing a plurality of antenna structures over the molded RF stand-off layer and electrically coupled to the plurality of semiconductor die through the plurality of vertically-elongated contacts; wherein the at least one-redistribution layer comprises a plurality of redistribution layers having an outer dielectric layer in which openings are formed exposing regions of the interconnect lines, and wherein producing a plurality of vertically-elongated contacts comprises depositing electrically-conductive bodies in the openings and in ohmic contact with the exposed regions of the interconnect lines.