Patent ID: 6121669
Filing Date: 2000-09-19
Classification: H01L

Abstract:
An integrated resistor-capacitor network implemented on a wafer of an integrated circuit, said wafer having a low resistivity substrate disposed under an epitaxial layer, said low resistivity substrate being of a first type and said epitaxial layer being of a second type different from said first type, said integrated resistor-capacitor network including plurality of thin film protected capacitor structures, each of said plurality of thin film protected capacitor structures comprising:a first heavily doped region in and through said epitaxial layer, said first heavily doped region being of said first type;an oxide layer having a first oxide region disposed above said first heavily doped region, said first heavily doped region being in electrical contact with both said first oxide region and said low resistivity substrate to form a conducting path between an underside of said first oxide region and said low resistivity substrate through said epitaxial layer, whereby said first heavily doped region and said low resistivity substrate represent a first plate of a thin film capacitor of each of said plurality of thin film protected capacitor structures;a metal layer disposed above said first oxide region, a portion of said metal layer forming a second plate of said thin film capacitor, whereby said first oxide region representing an insulating dielectric between said first plate and said second plate; anda second heavily doped region formed in said epitaxial layer, said second heavily doped region having a thickness that is less than the thickness of said epitaxial layer, said second heavily doped region being of said first type and in electrical contact with said metal layer, whereby said second heavily doped region, said epitaxial layer, and said low resistivity substrate form a protection device for said thin film capacitor.