Patent ID: 7627744
Filing Date: 2009-12-01
Classification: G06F

Abstract:
1. A parallel integrated circuit that accesses an external memory, comprising: a control processor; a plurality of parallel connected Vector Processing Engines (VPEs), wherein each one of the VPEs comprises a plurality of Vector Processing Units (VPUs), a plurality of VPU Control Units (VCUs), a Direct Memory Access (DMA) controller, and a VPE messaging unit (VMU) that is coupled between the plurality of VPUs, the plurality of VCUs, the DMA controller, and the control processor, wherein the VMU includes a first scheduler that is configured to schedule transfers of messages between the plurality of VPUs and the plurality of VCUs and a second scheduler that is configured to schedule transfers of DMA requests received from the plurality of VPUs and the plurality of VCUs to the DMA controller based on occupancy levels of DMA completion notification receive queues to prevent DMA completion notifications from blocking the DMA requests; and, an External Memory Unit (EMU) that is coupled between the external memory, the control processor, and the DMA controller within each VPE in the plurality of VPEs.