Patent ID: 8924679
Filing Date: 2014-12-30
Classification: G06F,G11C

Abstract:
1. A memory device, comprising: a first bank group; a second bank group, wherein the first and second bank groups are each configured to alternately output multi-bit data in parallel whenever a read command is applied; a data transferor configured to output the multi-bit data at a time interval corresponding to an operation mode in response to the multi-bit data outputted in parallel from the first bank group or the second bank group; and a parallel-to-serial converter configured to convert the multi-bit data outputted from the data transferor into serial data according to the operation mode, wherein during a first burst mode operation, whenever the read command is applied, parallel data of a first burst length are outputted from a bank group selected between the first bank group and the second bank group, and during a second burst mode operation, whenever the read command is applied, parallel data of a second burst length are outputted alternately from the first bank group and the second bank group, wherein the second burst length is a half of the first burst length.