Patent ID: 8271853
Filing Date: 2012-09-18
Classification: G06F

Abstract:
1. A memory access method comprising: receiving a reading instruction and a reading address from a processor; comparing an address stored in an address area of each of multiple cache lines included in a cache memory with the reading address; reading error-correction-coded data corresponding to the reading address which is stored in a main memory if the address stored in the address area does not correspond to the reading address; performing error correction decoding of the error-correction-coded data; detecting presence or absence of an error in the error-correction-coded data; correcting the error-correction-coded data if there is an error in the error-correction-coded data to yield corrected data, and outputting a correction execution signal indicating that correction has been performed; storing the corrected data in a data area of one of the multiple cache lines; storing the reading address in the address area of the one of the multiple cache lines; setting a dirty bit of the one of the multiple cache lines to 1 based on the correction execution signal; and transmitting the corrected data stored in the data area to the processor.