Patent ID: 7194057
Filing Date: 2007-03-20
Classification: H04L

Abstract:
1. An oversampling high speed clock/data recovery system, comprising: an analog circuit, used to oversample the incoming high speed data, and serially output 4*i oversampled data; wherein i is an integer equals to or greater than 2; a serial/parallel conversion unit, including at least an internal global clock synchronizer, an inverted internal global clock synchronizer and a converter, said internal global clock synchronizer, and said inverted internal global clock synchronizer are used to synchronize the 2*i signals respectively and output them serially, and said converted converts them into 4*i parallel data bus; a phase selector, used to receive said parallel data bus, and generate 4*i phase selection signals based on the phase selection mechanism; a delaying device, used to compensate the time delay caused by phase selector; and a data multiplexer, used to select i bits of data from said parallel data bus as the high speed recovery data by making use of the recovered clock phase determined by said phase selector.