Patent ID: 9152424
Filing Date: 2015-10-06
Classification: G06F

Abstract:
1. A computer system for mitigating instruction prediction latency, the system comprising: a processor, the processor including a processor pipeline having an instruction stream, an instruction cache, a prediction presence predictor and a branch target buffer (BTB); wherein the prediction presence predictor further comprises: the system configured to perform a method comprising: receiving the instruction address in the instruction cache for fetching instructions in the processor pipeline; receiving the instruction address in the prediction presence predictor coupled to the processor pipeline; based on receipt of the combined indication from the prediction presence predictor, holding instructions extracted from the instructions being fetched when they are determined to be BTB predictable by opcode, but such a prediction is not yet available; and based on the receipt of a branch prediction from a branch target buffer, releasing said held instructions to the processor pipeline for execution.