Patent ID: 6658524
Filing Date: 2003-12-02
Classification: G06F,G11C

Abstract:
A memory system comprising: a) an array of memory cells, each memory cell having a Bit Mask circuit, b) a bus circuit with a set of Address Bus lines, a set of Data Bus lines, a set of Origin Bus lines a set of Control lines, each memory cell being connected to each of said sets of lines, said Control lines comprising means to put the system in one of three operating modes as well as means to select one of a predefines set of relationships used for a search operation wherein:in a first operating mode, the system stores data applied on said Data Bus lines in the memory cells having positions defined by data applied on said Address Bus lines, in a second operating mode, a memory cell having a position defined by the Address Bus lines outputs on the Data Bus lines data stored in that memory cell, and in a third operating mode, applying a searched data on the Address Bus lines and performing a search process wherein each memory cell with data matching the searched data outputs on the Data Bus lines a value representing the Address of the memory cell that matched the searched data, the memory cell verifies a previously selected relationship with address bytes applied on the Address Bus lines by the other memory cells having data that matches the searched data whereupon the bits of the memory cell are masked by said Bit Mask circuit such that the memory cell address is presented on the Data Bus lines only where the position of that particular memory cell is the closest, in a predefined direction, to the data set on the Origin Bus lines among all the memory cells with matching data.