Patent ID: 6223309
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A method of verifying error correction circuitry in a computer system, said method comprising:determining a physically unavailable memory address;disabling system interrupts;forcing a memory data bus of said computer system to assume a test state, said memory data bus comprising a plurality of data bit lines and a plurality of check bit lines, wherein said test state of said check bit lines varies from an expected state of said check bit lines, said expected state comprising a state of said check bit lines that would be produced by an error correction circuit of said computer system coupled to said memory data bus in response to receiving said test state of said data bit lines; andwhile maintaining said test state of said memory data bus, executing a read cycle of said unavailable memory address, wherein said error correction circuit, if functioning properly, receives said test state of said check bit lines and said data bit lines, generates said expected state of said check bit lines in response to receiving said test state of said data bit lines, performs a comparison between said expected state and said test state of said check bit lines, and detects a variation between said test state and said expected state.