Patent ID: 7313021
Filing Date: 2007-12-25
Classification: G11C

Abstract:
1. A nonvolatile memory circuit, characterized by comprising: a first bit line; a second bit line; a first power supply line; a second power supply line; a first word line; a second word line; a flip-flop coupled to the first and second power supply lines and including MIS transistors; a first switch controlled through the first word line and coupled between a first output terminal of said flip-flop and said first bit line; a second switch controlled through the second word line and coupled between the first output terminal of said flip-flop and said first bit line; a third switch controlled through the first word line and coupled between a second output terminal of said flip-flop outputting an inverse of an output of the first output terminal and the second bit line; a fourth switch controlled through the second word line and coupled between the second output terminal of said flip-flop and the second bit line; and a row signal driver configured to, in a write mode, activate the first word line to turn on the first and third switches and drive the first and second power lines by write voltage levels to create a nonreversible hot-carrier-effect-based degradation in one of the MIS transistors that is selected in response to voltage levels of the first and second bit lines, said row signals driver further configured to, in a read mode, activate the second word line to turn on the second and fourth switches and drive the first and second power lines by read voltage levels to read, through the first and second bit lines, data responsive to the nonreversible hot-carrier-effect-based degradation created in one of the MIS transistors.