Patent ID: 6822922
Filing Date: 2004-11-23
Classification: G11C,H03K

Abstract:
A clock synchronous circuit to perform a synchronous operation which is a first clock synchronized with a second clock, comprising:a delay line for a forward pulse, which includes a plurality of stages of forward delay units, and uses the forward pulse to monitor a delay time necessary for said synchronous operation; a state-holding section which includes a plurality of stages of state-holding units, and holds said delay time in accordance with set/reset states of said plurality of stages of state-holding units; and a delay line for a backward pulse, which includes a plurality of stages of backward delay units, and uses the backward pulse to copy said delay time, wherein each of said plurality of stages of state-holding units is reset on a condition that the state-holding unit of a subsequent stage is in the reset state in a reset period.