Patent ID: 6693460
Filing Date: 2004-02-17
Classification: G01R,H03K

Abstract:
A scan flip-flop having a normal operation and a scan test operation, the scan flip-flop comprising:a master latching circuit that latches a data input in response to a normal clock in the normal operation and latches a scan-in signal in response to a first scan clock in the scan test operation; a slave latching circuit that provides the latched data input from the master latching circuit in synchronism with the normal clock in the normal operation and provides the latched scan-in signal from the master latching circuit in synchronism with a second scan clock in the scan test operation; and a clock circuit coupled to receive a first switching signal that sets the master latching circuit and slave latching circuit to operate as a positive flip-flop or a negative flip-flop in the normal operation.