Patent ID: 6707332
Filing Date: 2004-03-16
Classification: G06F,H03K

Abstract:
A clock generating circuit, suitable for generating a first output clock from a system clock, wherein a frequency ratio between the first output clock and the system clock is a value of a first preset value divided by a second preset value, and the clock generating circuit comprises:a register, used to temporarily store a data value according to a trigger of the system clock; a first adder, coupled to the register, used to receive the data value and obtain a sum of the data value and the first preset value, so as to output a first result; a first comparator, coupled to the first adder, used to compare the first result with a reference value, so as to generate a first output clock; a second adder, coupled to the first adder, used to receive the first result and obtain a sum of the first result and the second preset value, so as to output a second result; and a multiplexer, coupled to the first adder, the second adder, the first comparator, and the register, used to select the data value that should be stored into the register from the first result and the second result at the next system clock according to the level of the first output clock.