Patent ID: 7345716
Filing Date: 2008-03-18
Classification: G02F

Abstract:
1. A manufacturing method comprising: forming first and second gate lines extending in a first direction on a substrate; forming a data line extending in a second direction on the substrate, the data line crossing the first and second gate lines to define first and second pixel regions adjacent along the first direction; forming first and second driving thin film transistors in the first and second pixel regions, respectively, the first and second driving thin film transistors connected to the first gate line and the data line; forming a synchronization adjusting thin film transistor in the first pixel region, the synchronization adjusting thin film transistor connected to the second gate line; forming a connection line connected to the first driving thin film transistor and the synchronization adjusting thin film transistor, the connection line disposed over the data line; and forming first and second pixel electrodes in the first and second pixel regions, respectively, the first pixel electrode connected to the synchronization adjusting thin film transistor, the second pixel electrode connected to the second driving thin film transistor.