Patent ID: 6732913
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method for forming a wafer level chip scale semiconductor package, the method comprising the steps of:a) providing a semiconductor wafer having a surface with a plurality of pads, wherein each of the pads has a conductor extending a first predetermined distance away from the surface; b) forming a layer of conductive etch resistant material on free ends of the conductors; c) disposing electrically insulating material on the surface of the semiconductor wafer, wherein the layer of electrically insulating material has an exposed surface a second predetermined distance from the surface of the semiconductor wafer, wherein the second predetermined distance is less than the first predetermined distance, and wherein portions of the electrically insulating material are disposed on the layer of conductive etch resistant material and on side surfaces of at least some of the conductors; and d) removing substantially all the portions of the electrically insulating material disposed on the layer of conductive etch resistant material and on the side surfaces of some of the conductors.