Patent ID: 6032275
Filing Date: 2000-02-29
Classification: G01R,G11C

Abstract:
A test pattern generator for generating test data, expected value data and mask data for testing a memory device, comprising:an instruction memory for storing instructions and for generating the instructions to perform a test process for a memory device under test;a first data generator for generating test data and expected value data;a second data generator for generating mask data for inhibiting the test data to be written in the memory device under test;an exclusive OR (XOR) controller for generating a control signal based on the instructions from the instruction memory;an exclusive OR (XOR) gate for performing an exclusive OR logic for the test data from the first data generator and the mask data from the second data generator in response to an output signal of the XOR controller; anda logic comparator for comparing an output signal of the memory under test with the expected value data from the first data generator when the memory under test has no write enable/disable function.