Patent ID: 8787102
Filing Date: 2014-07-22
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a logic circuit configured to store data, the logic circuit including a first node and a second node; a first memory circuit electrically connected to the first node; a second memory circuit electrically connected to the second node; and a precharge circuit electrically connected to the first node, the second node, the first memory circuit, and the second memory circuit, wherein the first memory circuit comprises a first transistor and a first capacitor, and the second memory circuit comprises a second transistor and a second capacitor, each of the first transistor and the second transistor comprising an oxide semiconductor film having low off-state current, wherein the precharge circuit is configured to output a first precharge potential to the first node and a second precharge potential to the second node, and wherein off-state current density of the first transistor and the second transistor having the low off-state current is less than or equal to 100 zA/μm.