Patent ID: 6243804
Filing Date: 2001-06-05
Classification: G06F

Abstract:
A system for handling interrupts within a microcontroller comprising:interrupt signal generator logic circuit means for generating an interrupt enter signal responsive to an external event;means for initiating an interrupt service routine in response to the interrupt enter signal;pipeline means having a plurality of stages coupled to a memory for processing instructions;means for coupling a first primary register containing program address data to a corresponding shadow register responsive to receiving the generated interrupt enter signal;means for coupling a second primary register containing data memory address data to a corresponding shadow register responsive to receiving the generated interrupt enter signal;means for storing the data in the coupled primary registers into the corresponding shadow registers;means for decoupling the coupled primary registers from the corresponding shadow registers;means for coupling a third primary register containing central processing unit status information to a corresponding shadow register responsive to receiving the generated interrupt enter signal;means for coupling a fourth primary register containing accumulator data to a corresponding shadow register responsive to receiving the generated interrupt enter signal;interrupt service routine means for entering a first interrupt service routine of an interrupt service routine into the pipeline means responsive to the generated interrupt enter signal;interrupt signal generator logic circuit means for generating an interrupt exit signal responsive to completion of the interrupt service routine;responsive to receiving the generated interrupt exit signal, means for coupling the first primary register to the corresponding shadow register;responsive to receiving the generated interrupt exit program signal, means for coupling the second primary register to the corresponding shadow register;means for transferring the data in the corresponding shadow registers into the coupled primary registers; andmeans for decoupling the corresponding registers from the coupled primary registers;whereby the contents of the primary registers are stored within one clock cycle of the interrupt enter cycle and restored within one clock cycle of the interrupt exit signal.