Patent ID: 8391093
Filing Date: 2013-03-05
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first word line and a second word line; a plurality of first SRAM cells, each configured to include said first word line and said second word line and be connected to said first word line; a plurality of second SRAM cells, each configured to include said first word line and said second word line and to be connected to said second word line; and a mediating cell configured to be arranged between and adjacent to one of said plurality of first SRAM cells and one of said plurality of second SRAM cells and to be connected to said first word line and said second word line, wherein, in said mediating cell and said plurality of first SRAM cells, cells adjacent to each other share a first contact for said first word line, and wherein, in said mediating cell and said plurality of second SRAM cells, cells adjacent to each other share a second contact for said second word line.