Patent ID: 7577811
Filing Date: 2009-08-18
Classification: G06F

Abstract:
1. A memory controller for controlling a daisy chain of self timed memory chips comprising: a processor bus control configured to receive a request from a processor for a memory access to a memory and further configured to receive a data from the processor when the request is a write, and to transmit data to the processor when the request is a read; a bus clock output that determines a rate of transmission on an address/command bus and on a data bus; an address/command generator configured to transmit an address/command word on the address/command bus, the address/command word further comprising: a data send/receive configured to transmit a write data to the daisy chain of self timed memory chips, the data send/receive further configured to receive a read data word and to associate the received data word with the request from the processor; a sequencer configured to receive and store information of signal transmission times and array access times of each memory chip in the daisy chain of self timed memory chips, the sequencer further configured to use the information of signal transmission times and array access times to time transmissions of address/command words such that collisions of data words in the daisy chain of self timed memory chips does not occur; wherein the array access times of each memory chip in the daisy chain of self timed memory chips is determined by the each memory chip;