Patent ID: 8611169
Filing Date: 2013-12-17
Classification: G11C

Abstract:
1. A device, comprising: a memory array comprising a plurality of cells arranged in rows and columns, a plurality of true bit lines each connected to a column of the memory array and a plurality of complement bit lines each forming a differential pair with, and in the same column as one of the plurality of true bit lines, a plurality of word lines each connected to a row of the memory array, a plurality of power supply lines disposed in a horizontal dimension of the memory array parallel to the plurality of word lines, each of the plurality of power supply lines shared by adjacent cells in the memory array, wherein power supply lines that activate a row selected by one of the plurality of word lines are at a full power voltage value and power supply lines that activate rows adjacent to the selected row are at a half-power voltage condition, while cells in other rows and columns in the memory array are at a power-gated voltage value.