Patent ID: 6825121
Filing Date: 2004-11-30
Classification: H01L

Abstract:
A method of manufacturing a capacitor of a semiconductor device, the method comprising the steps of:i) sequentially depositing a first insulating layer, an etching stop layer, and a second insulating layer on a semiconductor substrate; ii) etching a predetermined portion of the second insulating layer to form a preliminary hole for exposing the etching stop layer; iii) forming a first hole by transversely expanding the preliminary hole in the second insulating layer; iv) forming a second hole by etching a predetermined portion of the etching stop layer and the first insulating layer at a bottom surface of the first hole, the second hole making contact with an electrode area of the semiconductor substrate and having an area narrower than the first hole; v) forming a first conductive layer pattern uniformly on sidewalls of the first and second holes and on a bottom surface of the second hole; and vi) sequentially depositing a dielectric layer and a second conductive layer pattern on the first conductive layer pattern.