Patent ID: 8564305
Filing Date: 2013-10-22
Classification: G11C,H01L

Abstract:
1. A 3D-IC detector for each layer of a stacked device with N layers, comprising: a dividing-two circuit coupled to a (N−1) signal; a first comparator coupled to said dividing-two circuit, wherein an input A is coupled to an initial layer number signal, an input B of said first comparator is coupled to an output of said dividing-two circuit; a second comparator coupled to said initial layer number signal by an input A of said second comparator, and a num is coupled to an input B of the second comparator; a first Add/sub circuit coupled to said num via an input A of said first Add/sub circuit, and coupled to said first comparator via an input B of said first Add/sub circuit, to said second comparator via an input “+/−” signal of said first Add/sub circuit; and a second Add/sub circuit coupled to said first comparator via an input A of said second Add/sub circuit, to said num via an input B of said second Add/sub circuit; wherein said detector redefines a layer ID by gradually increasing or decreasing even and odd numbers based on said input “+/−” signal, thereby separating said layer ID with two groups to form discontinuous type layer ID.