Patent ID: 6771241
Filing Date: 2004-08-03
Classification: G09G

Abstract:
A liquid crystal display device including two substrates which face each other in an opposed manner with one of two substrates being transparent and a liquid crystal layer which is sandwiched between a pair of two substrates, wherein said liquid crystal display device includes a plurality of pixels which have a function of holding video signals until said video signals are selected and rewritten next time,a plurality of signal lines which apply video signals to a plurality of said pixels, signal line drive means for supplying video signals to said signal lines, a plurality of selection signal lines for selecting pixels to which said video signals are applied, and a plurality of alternating voltage lines which supply a pair of alternating voltages to one of electrodes which sandwich a liquid crystal such that a fixed voltage which is selected for each pixel in accordance with said video signals and two kinds of voltages which differ for each field are made different from each other, the liquid crystal display device includes a first inverter in which a function to hold said video signals which said pixels hold until said video signals are rewritten next time sets a potential of said video signals selected by said selection signal lines and written in the inside of said pixels as an input gate potential and to which electrodes or diffusion regions which constitute respective sources or drains of a pair of p-type and n-type field effect transistors are electrically connected, a pair of p-type and n-type field effect transistors which constitute a second inverter which is similar to said first inverter, said second inverter setting a potential of an output portion to which said electrodes or diffusion regions which constitute respective sources or drains of a pair of p-type and n-type field effect transistors of said first inverter as an input gate potential of said second inverter, and a pair of p-type and n-type field effect transistors constituting a third inverter similar to said first and second inverters, said third inverter setting an output of a pair of p-type, n-type field effect transistors which constitutes said second inverter as an input gate potential thereof, outputs of a pair of p-type and n-type field effect transistors which constitute said second inverter are simultaneously electrically connected to an input gate of said first inverter, electrodes or diffusion regions of n-type field effect transistors of said first and second inverters which form sources or drains which are not outputs of inverters are connected to one of an alternating voltage line which supplies a pair of said alternating voltages, electrodes or diffusion regions of p-type field effect transistors of said first and second inverters which form sources or drains which are not outputs of inverters are connected to an alternating voltage line which forms a pair with said alternating voltage line to which said electrodes or said diffusion regions of n-type field effect transistors of said first and second inverters which form sources or drains which are not outputs of inverters are connected, one of an electrode or a diffusion region of n-type field effect transistor of said third inverter which forms a source or a drain which is not an output of inverter is connected to either one of said alternating voltage lines and the other of said alternating voltage lines is connected to a fixed voltage.