Patent ID: 7426136
Filing Date: 2008-09-16
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory comprising: one or more non-volatile memories; a capacitor; and a controller, wherein a power-supply voltage of a first level is supplied from an external source, wherein said capacitor is coupled to said external source, wherein said controller issues an operation command making a request for a read operation, a write operation or an erase operation to said non-volatile memory, wherein said non-volatile memory has a plurality of memory cells and carries out an operation in accordance with an operation command received from said controller, wherein, in a read operation, said nonvolatile memory carries out an operation to read data from said memory cells particularly pertaining to a first group and outputs said data to said controller, wherein, in a write operation, said non-volatile memory carries out an operation to receive data from said controller and writes said data into said memory cells particularly pertaining to said first group, wherein, in an erase operation, said non-volatile memory carries out an operation to erase data from said memory cells particularly pertaining to said first group, and wherein, when if a drop of said power-supply voltage to a second level lower than said first level is detected in the course of said write or erase operation, said non-volatile memory discontinues said write or erase operation currently being executed and carries out a first operation, for writing information to a memory cell coupled to a same word line as was selected for said write or erase operation, using electric charge in said capacitor to supply power for said first operation.