Patent ID: 7503029
Filing Date: 2009-03-10
Classification: G06F,Y02P

Abstract:
1. A computer-implemented method of matching a range pattern to a block of a layout of a material in a layer in an integrated circuit (IC) chip, the method comprising: slicing the range pattern into a plurality of pattern slices oriented parallel to one another, wherein location of presence of the material within each pattern slice differs from an adjacent pattern slice; slicing the block of the layout into a plurality of layout slices oriented parallel to one another, wherein location of presence of the material within each layout slice differs from an adjacent layout slice; comparing a sequence of widths of the layout slices obtained from slicing the block, to a sequence of width ranges of the pattern slices obtained from slicing the range pattern; if said comparing indicates the width of any layout slice falls outside the width range of a corresponding pattern slice then marking in a memory the block of the layout as not matching the range pattern and alternatively marking in said memory a first match; if said first match is determined, comparing a sequence of lengths of a plurality of layout fragments in a layout slice in the block to a sequence of length ranges of a plurality of pattern fragments in the corresponding pattern slice in the range pattern and if the length of any layout fragment falls outside the length range of the corresponding pattern fragment then marking in said memory the block of the layout as not matching the range pattern and alternatively marking in said memory a second match.