Patent ID: 6794920
Filing Date: 2004-09-21
Classification: H03K,H04L

Abstract:
A circuit for reducing direct-current (DC) offset in a differential signal line pair, the circuit comprising:a first set of storage elements responsive to a first signal line of the differential signal line pair, and configured to generate a DC offset level indication for the first signal line; a second set of storage elements responsive to a second signal line of the differential signal line pair, and configured to generate a DC offset level indication for the second signal line; a switch circuit that is configured to selectively electrically connect and electrically isolate the first and second set of storage elements with the corresponding first and second signal lines based on a control signal; and an offset correction loop circuit that is configured to combine the DC offset level indications from the first and second set of storage elements and a DC offset correction signal, and that is configured to recursively modify the DC offset correction signal to reduce a difference between the DC offset correction signal and the DC offset level indications from the first and second set of storage elements while the switch circuit electrically isolates the first and second set of storage elements from the first and second signal lines, and that is configured to reduce DC offset in a signal from the differential signal line pair based on the DC offset correction signal.