Patent ID: 9003346
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. A method for reducing post-routing delay variance, the method comprising: receiving a first netlist, wherein the netlist comprises first multiple instances that represent digital components of an electronic design; assigning a base signature to each instance on the first netlist, wherein the base signature is based on two or more design or connectivity attributes of said each instance; generating a first instance ordering based on first base signatures assigned to the first netlist, wherein the first instance ordering represents an order of the first multiple instances on the first netlist; receiving a second netlist that represents the electronic design, wherein the second netlist comprises second multiple instances, the second multiple instances including one or more instances that differ from the first multiple instances on the first netlist; assigning second base signatures to the second multiple instances on the second netlist; and generating a second instance ordering based on the second base signatures assigned to the second netlist, wherein the second instance ordering preserves the same order as the first instance ordering for those instances that are included in both the first netlist and the second netlist; wherein generating the second instance ordering is performed before any placement and routing has been performed; wherein the method is performed by one or more computer systems.