Patent ID: 7768860
Filing Date: 2010-08-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a bank controller that, respectively, enables first and second cell mats corresponding to a row address at different time during a refresh operation, wherein the first cell mat is firstly enabled in response to a first cell mat enable signal and the second cell mat is enabled in response to a second cell mat enable signal after a predetermined time during the refresh operation, and wherein the second cell mat enable signal is generated by delaying the first cell mat enable signal, wherein the bank controller includes: a first control unit configured to receive a bank address and to generate the first cell mat enable signal in response to the bank address; a refresh period setting unit configured to receive a refresh signal and to generate a refresh period setting signal in response to the refresh signal: and a second control unit configured to receive the first cell mat enable signal and the refresh period setting signal and to generate the second cell mat enable signal without delay during a data access operation and by delaying the first cell mat enable signal in response to the refresh period setting signal during the refresh operation.