Patent ID: 6229845
Filing Date: 2001-05-08
Classification: H04L

Abstract:
A transceiver circuit for transmitting a data signal having first and second logic levels over a communications bus at a predefined bit rate, comprising:a transmitter configured to receive and modify the data signal and to feed the modified data signal to the communications bus, the transmitter comprising:a drive circuit configured to receive the data signal and a clock signal, and to generate at least first and second control signals which depend on the logic level of the data signal, the first and second control signals being sequentially generated when the data signal has consecutive bits of the same logic level; andan output circuit configured to receive the at least first and second control signals and the data signal and to generate an output signal having a logic level responsive to the data signal, where the output circuit decreases a drive strength in response to said first control signal and further decreases the drive strength in response to the second drive signal while maintaining said logic level of said output signal.