Patent ID: 6986086
Filing Date: 2006-01-10
Classification: G01R

Abstract:
1. Method for simultaneous testing of a plurality of integrated circuits being equal in construction, at a testing device, each integrated circuit of the plurality of integrated circuits including a test mode, in which a test sequence is executed in the integrated circuits, and a pin for outputting test data produced in the test mode, the method comprising: receiving the test data of the plurality of integrated circuits at a plurality of test interfaces of the testing device being connected with the pin of the plurality of integrated circuits; receiving a synchronization signal, which is synchronous with the test sequence, at an interface of the testing device being connected to a synchronization interface of an integrated reference circuit, in which a test sequence is executed which is identical with the test sequence of the plurality of integrated circuits; evaluating the test data of the plurality of integrated circuits in the testing device so as to test the plurality of integrated circuits; and synchronizing the evaluation of the test data of the plurality of integrated circuits on the basis of the synchronization signal of the integrated reference circuit.