Patent ID: 6570235
Filing Date: 2003-05-27
Classification: G11C,H01L

Abstract:
A cell of mask read only memory, comprising:a gate, said gate being located on a substrate and being divided into at least a gate dielectric layer, a gate conductor layer and a spacer, said spacer being higher than other portions of said gate; a first doped region, said first doped region being located in said substrate; a second doped region, said second doped region being located in said substrate, wherein said first doped region and said second doped region being located on opposite sides of said gate; a first polysilicon layer, said first polysilicon layer being located on said first doped region, wherein said first polysilicon layer is higher than said gate; and a second polysilicon layer, said second polysilicon layer being located on said second doped region, wherein said second polysilicon layer is higher than said gate.