Patent ID: 9135200
Filing Date: 2015-09-15
Classification: G06F

Abstract:
1. An extended peripheral component interconnect express (PCIe) topology comprising: a host PCIe fabric comprising a host root complex, the host PCIe fabric having a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host central processing unit (CPU); and an extended PCIe fabric comprising a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric, the extended PCIe fabric having a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively, wherein the second MMIO space of the extended PCIe fabric is mapped to a physical address space on the host CPU, wherein the host PCIe fabric is a bridge between the extended PCIe fabric and the host CPU, and wherein the second set of bus numbers allows additional devices to be connected to the host CPU beyond a capacity of the host PCIe fabric as provided by resources of the host root complex.