Patent ID: 7650558
Filing Date: 2010-01-19
Classification: G06F,G11C,H03M

Abstract:
1. A memory device comprising: a mode indicator bit for specifying that the memory device is operating in an error check mode or a non-error check mode; a partitioned memory, a fraction of which is allocated for error check code (ECC) if the mode indicator bit specifies that the memory device is operating in the error check mode; and an output, coupled with the partitioned memory, having N error check bit paths for the ECC for every group of M data bit paths, the output to transfer N error check bits, with a corresponding group of M data bits, to a memory controller if the mode indicator bit specifies that the memory device is operating in the error check mode, wherein M is greater than N, and wherein the fraction of the partitioned memory allocated for the ECC is partitioned into chucks, the partitioned chunks located to cover every group of the M data bit paths.