Patent ID: 7354819
Filing Date: 2008-04-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming a complementary type MISFET circuit including an n-channel MISFET and a p-channel MISFET on a surface region of a silicon semiconductor substrate; forming an insulation film on the silicon semiconductor substrate in which the complementary type MISFET circuit is formed; forming a first contact hole and a second contact hole in the insulation film, an n-channel impurity diffused region of the n-channel MISFET being exposed at a bottom of the first contact hole, a p-channel impurity diffused region of the p-channel MISFET being exposed at a bottom of the second contact hole; forming a first conductive layer on the bottom of the second contact hole; forming a second conductive layer on the first and second contact holes; and heating the silicon semiconductor substrate to cause the second conducive layer react with the n-channel impurity diffused region to provide a first metal silicide layer at the bottom of the first contact hole and to cause the first and second conducive layers react with the p-channel impurity diffused region to provide a second metal silicide layer at the bottom of the second contact hole; in which a work function of the second metal silicide layer is higher than that of the first metal silicide layer.