Patent ID: 6995425
Filing Date: 2006-02-07
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor layer including an element region; a first conductive layer formed above said element region via a first insulating film; a second conductive layer formed on said first conductive layer; a trench extending from a top surface of the second conductive layer to an inside of the element region though the first insulating film and the first and second conductive layers; an element isolating layer formed in the trench; a second insulating film formed on said second conductive layer, said second insulating film permitting the top surface of said second conductive layer to be partially exposed; a third conductive layer formed on said second insulating film; a fourth conductive layer formed on an exposed top surface of said second conductive layer, said fourth conductive layer being electrically insulated from the third conductive layer, and a top surface of the fourth conductive layer being flush with a top surface of the third conductive layer; and a contact region electrically connected to said fourth conductive layer, wherein said first and second conductive layers form a gate electrode of at least one element comprised in a peripheral circuit arranged near a memory cell.