Patent ID: 7865650
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A processor comprising: a substrate including a perimeter; a plurality of compute elements situated on the substrate; a plurality of off-chip I/O interfaces distributed along the perimeter of the substrate; a primary interconnect trunk, situated along a first axis of the substrate and coupled to the compute elements, that communicates information to and from the compute elements; a secondary interconnect trunk, situated along a second axis of the substrate and intersecting the primary interconnect trunk to form an intersection with the primary interconnect trunk, the secondary interconnect trunk communicating information to and from the plurality of off-chip I/O interfaces to enable off-chip communication, the second axis being substantially perpendicular to the first axis; and a bus control element, situated at the intersection of the primary and secondary interconnect trunks, the bus control element including a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk, the bus control element including a secondary trunk interface that couples to the secondary interconnect trunk at the intersection to enable the bus control element to control off-chip communication via coherency signals on the secondary interconnect trunk.