Patent ID: 6701468
Filing Date: 2004-03-02
Classification: H03M

Abstract:
A code error correcting circuit for interleaving original data comprising a sequence of bit data having a length of p bits (p: natural number) by arranging the bit data of the original data into a hypothetical matrix of I (I: natural number not less than 2) rows and J (J: natural number not less than 2) columns and then selecting the bit data positioned on the ith (i: natural number, 1&lE;i&lE;I) row along an order of the jth (j: natural number, 1&lE;j&lE;J) column, said code error correcting circuit comprising:a memory unit having a plurality of memory areas each having a length of 2n bits (n: natural number); a controller for storing the original data to be interleaved into the memory areas respectively; a first data generating device for generating a first data indicating a position of the ith row in the hypothetical matrix; a second data generating device for generating a second data indicating a position of the jth column in the hypothetical matrix; an address decoding device for generating address data indicating one of the memory areas, in which the bit data positioned on the jth column are stored, on the basis of the first data and the second data; and a select data decoding device for generating a bit select data indicating the bit data positioned on the ith row among the bit data stored in said one of the memory areas, which is indicated by the address data, on the basis of the first data and the second data, said controller controlling said first data generating device, said second data generating device, said address decoding device and said select data decoding device so that the bit data, which are indicated by the bit select data, stored in said memory unit are sequentially outputted along an order of the ith row and the jth column in the hypothetical matrix as the interleaved original data.