Patent ID: 6597041
Filing Date: 2003-07-22
Classification: H01L,Y10S

Abstract:
A semiconductor memory device comprising:memory cells each including first and second access MOS (Metal Oxide Semiconductor) transistors, first and second driver MOS transistors, and first and second load MOS transistors; a first well region of a first conductivity type for forming said first driver MOS transistor and said first access MOS transistor thereon; a second well region of the first conductivity type for forming said second driver MOS transistor and said second access MOS transistor thereon; a third well region of a second conductivity type formed between said first and second well regions for forming said first and second load MOS transistors thereon; a first gate forming gates of said first driver MOS transistor and said first load MOS transistor; a second gate for forming gates of said second driver MOS transistor and said second load MOS transistor; a first contact hole formed in a self-aligned manner with respect to said first and second gates, and reaching one of impurity regions of said first driver MOS transistor, one of impurity regions of said first load MOS transistor and said second gate; a first local interconnection formed in said first contact hole, and electrically connected to said first driver MOS transistor, said first load MOS transistor and said second gate; a second contact hole formed in a self-aligned manner with respect to said first and second gates, and reaching one of impurity regions of said second driver MOS transistor, one of impurity regions of said second load MOS transistor and said first gate; and a second local interconnection formed in said second contact hole, and electrically connecting said second driver MOS transistor, said second load MOS transistor and said first gate.