Patent ID: 7415581
Filing Date: 2008-08-19
Classification: G11C

Abstract:
1. A semiconductor memory chip, comprising: transmission and reception interface sections for respectively transmitting and receiving data, command, and address signals in serial signal frames configured in accordance with a predefined protocol via respective data, command, and address signal lines to/from a memory controller and/or to/from another same memory chip; an intermediate data buffer configured for intermediate storage of write data; a memory core including a bank-organized memory cell array and address decoder for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from at least one memory bank of the memory cell array in accordance with a write/read command within one or more received signal frames; a system mode register configured to store command-relevant timing parameters not being supplied in an actual frame from the memory controller, the timing parameters respectively indicating a number of clock cycles of a synchronizing decoder clock signal; and a frame decoder providing an interface between the memory core and the reception interface section and receiving frame signals from and the reception interface section, the frame decoder including: a command type decoding section arranged configured to decode a command type of one or more commands included in one or more frames and outputting control signals in accordance with each decoded type of the commands; a memory command evaluator/generator section configured to schedule and prepare commands for the memory core; an intermediate data buffer command evaluator/generator section configured to schedule and prepare control signals for the intermediate data buffer; and a system command evaluator/generator section configured to prepare and schedule system commands, wherein: the memory command evaluator/generator, intermediate data buffer command evaluator/generator, and system command evaluator/generator sections are operated by control signals received from the command type decoding section in accordance with the decoded type of the commands; and at least the memory command evaluator/generator section, the intermediate data buffer, and the intermediate data buffer command evaluator/generator section are operable in synchronism with the synchronizing decoder clock signal.