Patent ID: 8441110
Filing Date: 2013-05-14
Classification: H01L

Abstract:
1. A semiconductor package comprising: a generally planar die paddle defining opposed top and bottom paddle surfaces and multiple peripheral edge segments; a plurality of first leads which each define opposed top and bottom lead surfaces and each including a downset connected thereto, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle; a plurality of second leads segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle; a semiconductor die attached to the top paddle surface of the die paddle and electrically connected to at least one of each of the first and second leads; and a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the downsets connected to each of the first leads are covered by the package body, at least portions of the bottom paddle surface of the die paddle and the bottom lead surfaces of the first leads are exposed in and substantially coplanar with the bottom surface of the package body, and portions of the second leads protrude from respective ones of the side surfaces of the package body.