Patent ID: 6184729
Filing Date: 2001-02-06
Classification: H03K,H04L

Abstract:
An output driver comprising:a first delay circuit having:an input connected to receive a first input signal, the first input signal having a logic state, anda plurality of first delay stages that output a corresponding plurality of delayed first signals which change logic states at different times after the logic state of the first input signal changes state, a first delay stage of the plurality of first delay stages having:a first inverter, the first inverter having a first transistor and a second transistor connected to the first transistor, the first transistor having a width-to-length (W/L) ratio, the second transistor having a W/L ratio, the W/L ratio of the first transistor being greater than the W/L ratio of the second transistor;a second inverter connected to the first inverter, the second inverted having a first transistor and a second transistor connected to the first transistor of the second inverter, the first transistor of the second inverter having a W/L ratio, the second transistor of the second inverter having a W/L ratio, the W/L ratio of the first transistor of the second inverter being substantially equal to the W/L ratio of the second transistor of the second inverter;a plurality of first driver transistors which are each connected to receive a delayed first input signal;a second delay circuit having:an input connected to receive a second input signal, the second input signal having a logic state, anda plurality of second delay stages that output a corresponding plurality of delayed second signals which change logic states at different times after the logic state of the second input signal changes state; anda plurality of second driver transistors which are each connected to the first driver transistors and to receive a delayed second input signal.