Patent ID: 6960479
Filing Date: 2005-11-01
Classification: B82Y,G11C,H01L

Abstract:
1. A process of forming a memory device, comprising: forming a first topology over a substrate; forming a first ferroelectric memory structure at the first topology and after forming the first topology; and forming at least one subsequent ferroelectric memory structure over the first ferroelectric memory structure, wherein forming a first topology includes: forming a first dielectric layer over the substrate; forming a first metal layer over the first dielectric layer, wherein first metal layer has thickness ranging from about 0.1 micron to about 1 micron; forming a second dielectric layer over the first metal layer; forming a first electrode adjacent to the second dielectric layer; forming a second metal layer over the second dielectric layer; forming a third dielectric layer over the second metal layer; forming a third metal layer over the third dielectric layer; and forming a first-filed via between the first metal layer and the second metal layer.