Patent ID: 9015453
Filing Date: 2015-04-21
Classification: G06F

Abstract:
1. A processor comprising: a register file including at least a first register to hold a first byte, a second byte a third byte, and a fourth byte, a second register to hold a fifth byte, a sixth byte, a seventh byte, and an eighth byte, and a third register, wherein the first byte is in a least significant byte position of the first register, the second byte is in a second-most least significant byte position of the first register, the third byte is in a third-most least significant byte position of the first register, the fourth byte is in a fourth-most least significant byte position of the first register, the fifth byte is in a least significant byte position of the second register, the sixth byte is in a second-most least significant byte position of the second register, the seventh byte is in a third-most least significant byte position of the second register, and the eighth byte is in a fourth-most least significant byte position of the second register; a decoder to decode an instruction, the instruction to identify the first and the second registers as source registers and the third register as a destination register; and a functional unit coupled to the register file and the decoder, the functional unit, responsive to the instruction being decoded, to store the fifth byte to a least significant portion of the third register, the seventh byte to a second least significant portion of the third register, the first byte to a third least significant portion of the third register, and the third byte to a fourth least significant portion of the third register.