Patent ID: 9088522
Filing Date: 2015-07-21
Classification: G01R,G06F,H04L

Abstract:
1. A method of test scheduling, comprising: receiving test data for testing a plurality of cores in a circuit and information of TAM (test access mechanism) for the circuit, the information of TAM comprising information of an input switching network that connects circuit input channels to core input channels for each of the plurality of cores, and information of an output switching network that connects circuit output channels to core output channels for each of the plurality of cores; encoding the test data to derive compressed test patterns that require small numbers of the core input channels, each of the compressed test patterns being associated with one or more cores in the plurality of cores and with core input channel requirement information; determining core output channel requirement information for each of the compressed test patterns; grouping the compressed test patterns into test pattern classes based on cores associated with each of the compressed test patterns, the core input channel requirement information and the core output channel requirement information; and allocating, based on the information of TAM, test application time slots and the circuit input channels which deliver the test pattern classes to the plurality of cores and the circuit output channels which collect test response data for the test pattern classes.