Patent ID: 6459307
Filing Date: 2002-10-01
Classification: H03K

Abstract:
An input buffer of a semiconductor device, comprising:an input terminal configured to receive an external input signal; a first buffer circuit having an input coupled to the input terminal; a second buffer circuit having an input coupled to the input terminal, wherein the first and the second buffer circuits are configured to transfer the external input signal via respective transfer paths; a control signal generating circuit configured to receive output signals from the first and second buffer circuits and to generate a control signal to control the transfer paths of the first and the second buffer circuits, wherein the control signal generating circuit includes: a first logic circuit for-logically combining the output signal of the first buffer circuit and a delayed output signal of the first buffer circuit; a second logic circuit for logically combining the output signal of the second buffer circuit and a delayed output signal of the second buffer circuit; and a first latch circuit for latching the output signal of the first logic circuit and the output signal of the second logic circuit; and a second latch circuit configured to receive transferred external input signals from the first and the second buffer circuits and to generate an internal operation signal of the semiconductor device.