Patent ID: 8816739
Filing Date: 2014-08-26
Classification: H03K

Abstract:
1. A semiconductor device comprising: a latch circuit including a first data holding node and a second data holding node; a first capacitance element; a first switch element that couples the first data holding node to the first capacitance element; a second switch element that couples a data input terminal to one of the first data holding node and the second data holding node; and a clock generation circuit configured to control the first switch element and the second switch element, wherein the first capacitance element is coupled to the data input terminal through at least one of the first data holding node and the second data holding node, wherein the clock generation circuit generates a first clock for controlling the first switch element and generates a second clock for controlling the second switch element, and the first clock and the second clock have the same frequency, wherein the clock generation circuit turns off the first switch element in at least part of a time period during which the second switch element is in an ON state, and the clock generation circuit turns on the first switch element in at least part of a time period during which the second switch element is in an OFF state, wherein, in the time period during which the second switch element is in the ON state, a second electrical path between the data input terminal and the one of the first data holding node and the second data holding node is made conductive and data of the data input terminal is written into the one of the first data holding node and the second data holding node, and wherein, in a time period during which the first switch element is in the OFF state, a first electrical path between the capacitance element and the first data holding node is made non-conductive and no data is written into the capacitance element.