Patent ID: 8988059
Filing Date: 2015-03-24
Classification: G05F,H02J,H02M,H03K,Y02B

Abstract:
1. An apparatus, comprising: a high-side switch coupling a source voltage to an inductor, wherein the inductor is further coupled to an output voltage, and wherein a size of the high-side switch is adjustable; a low-side switch coupling the inductor to ground, wherein a size of the low-side switch is adjustable; and a control logic block, wherein a driving capability of at least one of the high-side switch and the low-side switch is adjusted based on a target output voltage to which the output voltage is driven, wherein the driving capability of at least one of the high-side switch and the low-side switch corresponds to the size of said at least one of the high-side switch and the low-side switch, wherein the size of the high-side switch is adjustable by selectively enabling a plurality of parallel-coupled PMOS transistors, and the size of the low-side switch is adjustable by selectively enabling a plurality of parallel-coupled NMOS transistors, wherein the control logic block is configured to generate a plurality of gate control voltages for controlling each of the plurality of parallel-coupled PMOS transistors and the plurality of parallel-coupled NMOS transistors, and wherein the high-side switch is adjustable, in response to the target output voltage being increased, by increasing a quantity of the plurality of parallel-coupled PMOS transistors that are selectively enabled, and wherein the low-side switch is adjustable, in response to the target output voltage being decreased, by increasing a quantity of the plurality of parallel-coupled NMOS transistors that are selectively enabled.