Patent ID: 6323800
Filing Date: 2001-11-27
Classification: H03M

Abstract:
A pipeline analog to digital converter for converting an analog input signal into a digital representation of the analog input signal comprising:a sample and hold stage, the sample and hold stage sampling an analog input signal during a pulse of a primary clock signal and holding a sampled voltage signal during a pulse of a secondary clock signal; anda first analog signal converter stage, the first analog signal converter stage converting and latching the sampled and held voltage signal into a digital output during the pulse of the secondary clock signal, at least a most significant bit of the digital representation of the analog input signal being derived from the digital output, and the first analog signal converter stage generating a residue signal based on a comparison of the sampled and held voltage signal and from an analog representation of the digital output, the first analog signal converter stage sampling the sampled and held voltage signal during the pulse of the secondary clock signal and holding the residue signal during the pulse of a second cycle of the primary clock signal;wherein the primary and secondary clock pulse signals together form a two phase nonoverlapping clock having a regular clock period, a length of the period being defined by a duty cycle of the primary clock signal plus a duty cycle of the secondary clock signal, and the duty cycle of the primary clock signal being less than the duty cycle of the secondary clock signal.