Patent ID: 7913070
Filing Date: 2011-03-22
Classification: G06F

Abstract:
1. A processor comprising: first issue queue circuitry used to dual-issue instructions from a first issue queue to a plurality of units, wherein one of the units is a second issue queue managed by a second issue queue circuitry; a plurality of execution unit pipelines connected to the second issue queue circuitry, each of the execution unit pipelines connected to an execution unit; a plurality of instructions in each of the plurality of execution unit pipelines; a plurality of counters, each counter corresponding to one of the plurality of instructions, wherein each counter is initialized to an initial value by the first issue queue circuitry, and wherein the initial value for each counter is set to a commit point for its corresponding instruction, the commit point being a number of instruction cycles after which the corresponding instruction can not be flushed; decrementing logic that decrements each of the counters during each of a plurality of instruction cycles; comparison logic that compares each of the counters with an exception value, wherein the exception value is one; first flush logic that flushes instructions with counters greater than the exception value from the execution unit pipelines, wherein instructions with counters equal to zero are not flushed; read logic that reads an age attribute associated with instructions with counters equal to one, wherein each instruction with a counter equal to one has an associated age value; and second flush logic that flushes instructions with counters equal to one based upon the instructions' age attributes.