Patent ID: 6683350
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor layer formed over a substrate and having a protrusion, said semiconductor layer comprising a pair of impurity regions and a channel region located in said protrusion between said pair of impurity regions; a gate electrode provided adjacent to said channel region with a gate insulating layer interposed therebetween; and at least one electrode connected to at least one of said pair of impurity regions; wherein at least one junction interface between said channel region and at least one of said pair of impurity regions is aligned with a side of said gate electrode, and said at least one of said pair of impurity regions has a substantially constant impurity concentration distribution in a direction parallel to said substrate, wherein said protrusion is provided adjacent to said gate electrode, and wherein edges of said gate electrode, said gate insulating layer and said protrusion are aligned.