Patent ID: 6724683
Filing Date: 2004-04-20
Classification: G06F,H04L

Abstract:
An apparatus comprising a data synchronizer comprising:data storage entries; a first circuit for selecting the entries to store data therein; a second circuit for selecting the entries to read data therefrom such that if any given data item d1 is stored in any entry e1 earlier than another data item d2 is stored in any other entry e2, then d1 is read from e1 earlier or at the same time as d2 is read from e2; wherein the entries have outputs for providing the stored data, and at least a plurality of the entries have their outputs connected to the second circuit, wherein each of said entries is to hold its data item on its output longer than an interval of time between selection of different entries by the first circuit; wherein the synchronizer further comprises: one or more inputs for receiving a first clock signal or signals which synchronize the operation of the first circuit and the storing of data in the entries; and one or more inputs for receiving a second clock signal or signals which synchronize the operation of the second circuit.