Patent ID: 6635527
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method for forming an interconnection wiring system containing at least one capacitor comprising the steps of:(a) forming a first level of interconnection wiring positioned atop a planar surface of a substrate; (b) forming a first dielectric layer over said first level of interconnection wiring; (c) forming an upper electrode layer for said at least one capacitor over said first dielectric layer; (d) etching a portion of said upper electrode layer selective to said first dielectric layer to form an upper electrode for said at least one capacitor; (e) etching said first dielectric layer selective to said first level of interconnection wiring to form a dielectric for said at least one capacitor; (f) etching said first level of interconnection wiring to form a base electrode for said at least one capacitor; and (g) depositing a second dielectric layer atop said upper electrode and atop said dielectric and over said upper electrode.