Patent ID: 6760738
Filing Date: 2004-07-06
Classification: G06F

Abstract:
An exponent unit adapted to receive an operand and to output an exponent of the operand, comprising:a detection device adapted to detect a number of consecutive bits of the operand having a same value as a most significant bit (MSB) of the operand, and to output a detection value corresponding thereto; a mantissa and carry control device adapted to output the detection value as a mantissa signal in at least one of a single precision mode and, when a previous first status bit is set and the MSB is identical to a previous second status bit, in a double precision mode, and to generate a carry signal in the double precision mode, when the previous first status bit is set and the MSB is identical to the previous second status bit; an augend control device adapted to output an exponent of a previous operand as an augend signal; a logic circuit adapted to set a first status bit and to set a second status bit to a lowest bit of the operand, when all bits of the operand have an identical value; and an adder adapted to add the mantissa signal, the augend signal, and the carry signal to obtain a sum thereof, and to output the sum as the exponent of the operand, wherein the single precision mode and the double precision mode are sequentially generated, and the exponent of the operand is equal to the number of consecutive bits of the operand having the same value as the MSB of the operand.