Patent ID: 6225673
Filing Date: 2001-05-01
Classification: H01L

Abstract:
An integrated circuit, comprising:first and second transistors which are field effect switching transistors and which are coupled in series between a supply voltage and ground;a third transistor which is a parasitic PNP bipolar junction transistor, which has an emitter coupled to a node between said first and second transistors, which has a collector coupled to ground, and which has a base coupled to the supply voltage;a fourth transistor which is a parasitic NPN bipolar junction transistor, which has an emitter coupled to said node, which has a collector coupled to ground, and which has a base coupled to ground;a p-type semiconductor substrate;first and second n-type isolation layers buried in said substrate, said first and second isolation layers having first and second portions of said p-type substrate respectively disposed therein; andfirst and second spaced n-type regions disposed in each of said first and second portions, said first and second n-type regions in said first portion respectively being a source and a drain of said first transistor, and said first and second n-type regions in said second portion respectively being a source and a drain of said second transistor;said first isolation layer being coupled to ground, said second isolation layer being coupled to the supply voltage, and said semiconductor substrate being coupled to ground at a location external to said first and second isolation layers;wherein said location at which said substrate is coupled to ground is disposed between said first and second isolation layers, is closely adjacent said first isolation layer, and is spaced from said second isolation layer; andwherein said first portion includes a p-well having therein said first n-type region of said first portion, said p-well being closer than said second n-type region of said first portion to said first isolation layer, and being disposed closely adjacent said first isolation layer.