Patent ID: 6856540
Filing Date: 2005-02-15
Classification: G11C

Abstract:
1. A programmable memory cell useful in a memory array having column bitlines and row wordlines, the memory cell comprising: a transistor having a gate, a gate dielectric between the gate and over a substrate such that there is a stack comprising said gate, gate dielectric, and substrate, without any intervening conductive material, and first and second doped semiconductor regions formed in said substrate adjacent said gate and in a spaced apart relationship to define a channel region therebetween and under said gate, the gate being formed from one of said column bitlines; a row wordline segment coupled to the second doped semiconductor region of the transistor, said row wordline segment connected to one of said row wordlines; and a programmed doped region formed in said substrate in said channel region when said memory cell has been programmed.