Patent ID: 6075741
Filing Date: 2000-06-13
Classification: G11C

Abstract:
A complementary metal-oxide semiconductor (CMOS) memory integrated circuit being powered by a supply voltage comprising:n memory array portions including a first memory array portion and a second memory portion, each memory array portion having memory cell capacitors organized in rows and columns for storing data;control circuitry generating a first powerup control signal when the supply voltage is first applied to the CMOS memory integrated circuit, and further generating a second powerup control signal which is active a selected time delay after the first powerup control signal is active;a first switch responsive to the first powerup control signal to couple the supply voltage to the first memory array portion when the first powerup control signal is active to cause the first memory array portion to be activated; anda second switch responsive to the second powerup control signal to couple the supply voltage to the second memory array portion when the second powerup control signal is active to cause the second memory array portion to be activated.