Patent ID: 8161639
Filing Date: 2012-04-24
Classification: H05K,Y10T

Abstract:
1. A method for fabricating an interlayer conducting structure of an embedded circuitry, comprising: forming a first circuitry and at least one target point on a first lamination plate; forming a second circuitry on a second lamination plate; laminating the second lamination plate on the first lamination plate, wherein the second lamination plate overlaps the first circuitry and the at least one target point; targeting the at least one target point for positioning; executing a boring method to form a via hole through the second lamination plate positioned on a stop pad of the first circuitry; providing a photoresist layer on a part of the second lamination layer and a part of the second circuitry; executing an electroplating process to form a conductive layer in the via hole and on the rest part of the second lamination plate which is uncovered by the photoresist layer for electrically connecting the first circuitry with the second circuitry; and removing the photoresist layer; wherein the boring method to form the via hole through the second lamination plate is accomplished by targeting and according the at least one target point for positioning without forming a conforming mask on the second lamination plate.