Patent ID: 6930004
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A method of formation of a trench vertical transistor in a semiconductor substrate having a surface and a trench with a sidewall formed in said semiconductor substrate, said semiconductor substrate being doped with a dopant, a counterdoped drain region in the surface of said substrate and a channel alongside said sidewall, said drain region having a top level and a bottom level, a counterdoped source region formed in the substrate juxtaposed with said sidewall below said channel, a gate oxide layer formed on the sidewalls of said trench, and a gate conductor formed in said trench, said method including the steps as follows: recessing said gate conductor below said surface of said semiconductor substrate; performing angled ion implantation at a greater angle θ+δ with respect to vertical of a counterdopant into said channel below the location of said drain region; and performing angled ion implantation at a lesser angle θ with respect to vertical of a dopant into said channel below said location of said drain region.