Patent ID: 8447911
Filing Date: 2013-05-21
Classification: G06F

Abstract:
1. A method for comprising: fetching instructions of a program from an instruction storage, and staging fetched instructions in a dispatch store for issuing, wherein the program comprises a plurality of instructions, including a plurality of load or store instructions; issuing staged instructions from the dispatch store out-of-program-order to one or more execution units of a processor for out-of-program-order execution, wherein the issuing includes inserting in execution order, which is out-of-program-order, load or store instructions being issued into one or more combined load/store queues for staging issued load and store instructions for execution, wherein each combined load/store queue is configured to store load instructions and store instructions; searching a memory of the one or more combined load/store queues to identify any address with one of a same address or an overlapping address of one of a load instruction or a store instruction to be executed; searching said memory to identify any sequence numbers that are one of younger or older than a sequence number of one of said load instruction or said store instruction to be executed, wherein a sequence number of a load or store instruction comprises a program location of the load or store instruction in the program in program order; and performing a logical AND function on outputs of said searches.