Patent ID: 8780615
Filing Date: 2014-07-15
Classification: G11C

Abstract:
1. A method of writing data to a memory device comprising a plurality of bitlines, a plurality of wordlines, and a matrix of memory cells, said matrix of memory cells comprising a plurality of memory cells arranged in a plurality of rows and columns, each of said bitlines being electrically coupled to memory cells in one of said columns, each of said wordlines being electrically coupled to memory cells in one of said rows, said method comprising: applying a bitline write voltage to a first bitline; applying a wordline voltage to a first wordline for writing data to a first memory cell coupled to said first wordline and said first bitline; electrically coupling said first bitline and a second bitline for charge sharing between said first bitline and said second bitline; electrically disconnecting said first and said second bitline and applying said bitline write voltage to said second bitline; and applying said wordline voltage to a second wordline for writing data to a second memory cell coupled to said second wordline and said second bitline.