Patent ID: 6169456
Filing Date: 2001-01-02
Classification: G05F,H03F

Abstract:
An auto-biased cascode current circuit, comprising: a current mirror having a reference leg and an output leg, wherein a reference current flows within the reference leg and wherein the output leg includes: a first output transistor having a first drain-to-source saturation voltage and a threshold voltage; a second output transistor, which operates as a cascode transistor, having a second drain-to-source saturation voltage; and an output terminal having an output potential; and a bias circuit for biasing the reference leg of the current mirror, wherein: the output potential is substantially equal to the first drain-to-source saturation voltage plus the second drain-to-source saturation voltage plus a predetermined overdrive voltage, the predetermined overdrive voltage is less than the threshold voltage, andthe bias circuit is responsive to changes in the reference current; wherein the reference leg includes: a first reference transistor having: a first source terminal, a first drain terminal, and a first gate terminal; and a second reference transistor having: a second source terminal, a second drain terminal, and a second gate terminal; wherein the bias circuit includes: a first bias transistor having: a fifth source terminal, a fifth drain terminal, and a fifth gate terminal; a second bias transistor having: a sixth source terminal, a sixth drain terminal, and a sixth gate terminal; a third bias transistor having: a seventh source terminal, a seventh drain terminal, and a seventh gate terminal; and a fourth bias transistor having: a eighth source terminal, a eighth drain terminal, and a eighth gate terminal the fifth gate terminal is connected to the second drain terminal and the first gate terminal, the fifth source terminal is connected to the first drain terminal and the second source terminal, the eighth gate terminal is connected to the eighth drain terminal and the second gate terminal.