Patent ID: 6411233
Filing Date: 2002-06-25
Classification: H03M

Abstract:
An ADC calibration circuit comprising:a) a plurality of comparators; b) MÃ—N selector elements arranged in M rows and N columns, each of said MÃ—N selector elements having first and second terminals; c) a plurality of first wirings, each of said plurality of first wirings being in communication with said first terminals of N of said MÃ—N selector elements for each corresponding one of the M rows, wherein each of said plurality of first wirings is in communication with a corresponding a second input of each of said plurality of comparators; d) a plurality of second wirings, each of said plurality of second wirings being in communication said second terminals of X of said MÃ—N selector elements and to only one of said MÃ—N selector elements on each one of the M rows, wherein X is at most M, wherein each of said plurality of second wirings is in communication with a corresponding one of a plurality of reference voltages.