Patent ID: 6982610
Filing Date: 2006-01-03
Classification: H03H

Abstract:
1. An impedance adjustment system, comprising: a current source adapted to provide a predetermined stabilized current corresponding to a current through a first resistor having across it a predetermined stabilized voltage; a first series connected string of a first predetermined number of resistors coupled between the current source and ground, being coupled to the current source at a sense node; a first switch network adapted to select ones of the first predetermined number of resistors for inclusion in the first series connected string; a first logic circuit adapted to control the first switch network to incrementally change the total resistance of the first series connected string; a comparator having a first input coupled to the predetermined stabilized voltage and having a second input coupled to the sense node, and having an output representing the direction of difference in voltage between the first input and the second input of the comparator; a second logic circuit responsive to the output of the comparator, adapted to hold a state of the first switch network to maintain a coarse resistance value of the first series connected string at a value corresponding to a value before which the comparator changes state when the first logic circuit incrementally changes the resistance of the first series connected string, while disconnecting the first series connected string from ground; a second series connected string of a second predetermined number of resistors having a first end coupled to ground, the second logic circuit being adapted to couple a second end of the second series connected string to the end of the portion of the first series connected string that provides the coarse resistance value; a second switch network adapted to select ones of the second predetermined number of resistors for inclusion in the second series connected string; and a third logic circuit adapted to control the second switch network to incrementally change the total resistance of the second series connected string, wherein the second logic circuit is responsive to the output of the comparator and adapted to hold a state of the second switch network to maintain a fine resistance value of the first series connected string at a value corresponding to a value at which the comparator changes state when the third logic circuit incrementally changes the resistance of the first series connected string.