Patent ID: 6248661
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method for monitoring pinholes and bubble defects formed over a spin-on glass layer during deposition of a superjacent layer comprising:(a) providing a silicon wafer;(b) forming a first insulative layer on said silicon wafer;(c) depositing and patterning a metal layer on said first insulative layer, thereby forming a metal pattern;(d) conformally depositing a second insulative layer on said metal pattern;(e) performing an initial scan of the surface of said wafer with a white light scanning tool and recording initial surface profile data;(f) depositing a spin-on glass layer over said metal pattern thereby forming a planar surface;(g) curing said spin-on glass layer;(h) plasma etching said spin-on glass layer;(i) depositing a third insulative layer on said spin-on glass layer;(j) etching said wafer with an aqueous oxide etchant, thereby decorating pinholes and micro bubbles in said third insulative layer by penetrating and enlarging said pinholes and micro bubbles and forming subjacent discrete etched out pockets in said spin-on-glass layer which can be observed with said scanning tool;(k) performing a final scan of the surface of said wafer with said scanning tool and recording final surface profile data; and(l) forming a wafer map of the differences between said final surface profile data and said initial surface profile data whereby said wafer map reveals said etched out pockets under pinholes and bubble defects incurred in said third insulative layer.