Patent ID: 9047954
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A method for compensating for variability in bit line resistance, comprising: identifying a first zone within a memory array corresponding with a first group of storage elements, the memory array includes the first zone and a second zone, the first zone corresponds with a first plurality of bit line segments derived from a first feature, the second zone corresponds with a second plurality of bit line segments derived from the first feature, the first plurality of bit line segments includes a first segment, the second plurality of bit line segments includes a second segment, the first group of storage elements includes a first storage element in communication with a first bit line, the first bit line includes the first segment and the second segment, the first segment is associated with a first track and the second segment is associated with a second track different from the first track; performing a read operation on the first group of storage elements, the performing a read operation includes determining a bit line read voltage based on a location of the first zone within the memory array and applying the bit line read voltage of the first bit line; and outputting data stored in the first storage element based on the performing a read operation.