Patent ID: 6950368
Filing Date: 2005-09-27
Classification: G11C

Abstract:
1. A memory device, comprising: a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device; a column address circuit operable to receive and decode column address signals applied to the external address terminals; at least one array of memory cells arranged in rows and columns, each of the memory cells being operable to store a data bit written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals; a plurality of sense amplifiers provided for respective columns of memory cells in the at least one array, each of the sense amplifiers comprising: a data path circuit operable to couple data signals corresponding to the data bits between the sense amplifiers and external data terminals of the memory device; and a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.