Patent ID: 6606347
Filing Date: 2003-08-12
Classification: H04B

Abstract:
A multistage interference canceller for extracting each user signal from a received signal containing spectrum spread signals of a plurality of users by removing signal components of the users other than said each user, which comprises:a first stage comprising: a plurality of first interference estimation units provided for respective users, each of said first interference estimation units generating a first symbol replica signal and a first chip replica signal from said received signal on the basis of primary path timings, said first symbol replica signal being the same as a signal component of said each user, and said first chip replica signal being a respread signal from said first symbol replica signal; a first delay circuit for outputting said received signal after delaying said received signal by a first prescribed period; and a first subtractor for subtracting a sum of a plurality of said first chip replica signals which are outputted from a plurality of said first interference estimation units from said received signal which is outputted from said first delay circuit to output the residual as a first residual signal; a plurality of path search units provided for respective users, each of said path search units comprising: means for setting path timings which are obtained by performing path search on said received signal using a spread signal as said primary path timings; means for setting path timings which are obtained by performing path search on said first residual signal supplied from said first stage as temporal secondary path timings of paths having said primary path timings; and means for setting said temporal secondary path timing as a secondary path timing for each path of which signal-to-interference ratio measured is lower than a first prescribed threshold and of which a time difference between said primary path timing thereof and said temporal secondary path timing thereof is shorter than a second prescribed threshold, and for setting said first path timing as a secondary path timing for each path of which signal-to-interference ratio measured is not lower than said first prescribed threshold or of which a time difference between said primary path timing thereof and said temporal secondary path timing thereof is not shorter than said second prescribed threshold; a second stage comprising: a plurality of second interference estimation units provided for respective users, each of said second interference estimation units generating a second symbol replica signal and a second chip replica signal from said first residual signal supplied from said first stage and said first symbol replica signal on the basis of secondary path timings, said second symbol replica signal being the same as a signal component of said each user, and said second chip replica signal being a respread signal from said second symbol replica signal; a second delay circuit for outputting said first residual signal after delaying said first residual signal by a second prescribed period; and a second subtractor for subtracting a sum of a plurality of said second chip replica signals which are outputted from a plurality of second interference estimation units from said first residual signal which is outputted from said second delay circuit to output the residual as a second residual signal to be supplied to a third stage; and a third stage comprising: a plurality of third interference estimation units provided for respective users, each of said third interference estimation unit generating said user signal from said second residual signal supplied from said second stage and said second symbol replica signal supplied from said second stage.