Patent ID: 6239472
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A semiconductor transistor structure defined on a substrate having an active region that is isolated by shallow trench isolation oxide, the semiconductor transistor structure comprises:a gate stack of the semiconductor transistor structure being disposed over a gate oxide that is in turn disposed over the active region of the substrate;a pair of shallow trenches defined on either side of the gate stack;an intrinsic silicon material being disposed within the pair of shallow trenches up to a top surface of the gate stack and the shallow trench isolation oxide;source and drain implanted impurities being defined in an upper portion of the intrinsic silicon material, the upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack;pocket implant regions; andlightly doped drain (LDD) regions;wherein portions of the pocket implant regions and the LDD regions are defined between the intrinsic silicon material and slightly under the gate oxide of the gate stack.