Patent ID: 6815330
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A manufacturing method of a semiconductor integrated circuit device, comprising:(a) forming a first interconnection groove in a first insulating film over a first main surface of a wafer; (b) forming a barrier metal film over an upper surface of the first insulating film and an inner surface of the first interconnection groove; (c) forming a first metal film having copper as a main component over the barrier metal film so as to embed the first interconnection groove with the first metal film; (d) removing the first metal film and the barrier metal film outside the first interconnection groove by chemical-mechanical polishing to form a first copper-containing interconnection embedded in the first interconnection groove; and thereafter (e) subjecting the first main surface of the wafer to ammonia plasma treatment in a gas-phase atmosphere, thereby subjecting both an upper surface of the first copper-containing interconnection embedded in the first interconnection groove and the upper surface of the first insulating film to reducing and nitriding treatment; and thereafter (f) forming, by plasma CVD, a cap insulating film, which has inhibitory action against diffusion of copper atoms or copper-containing ions into an insulating film, over the first insulating film and the embedded first copper-containing interconnection.