Patent ID: 9166770
Filing Date: 2015-10-20
Classification: G06F,H03K,H03L,H04L

Abstract:
1. A clock-generation device comprising: a signal selector that receives a feedback clock, an edge signal having an edge at a timing according to a bit rate, and an edge detection signal that is at a significance level over a certain period of time including a timing of the edge of the edge signal, selects and outputs the edge signal when the edge detection signal is at the significance level, and selects and outputs a signal obtained by logically inverting the feedback clock when the edge detection signal is at a non-significance level; a phase delay unit including a plurality of cascaded delay elements, the signal output from the signal selector being input to the delay element of a first stage among the plurality of delay elements, and signals having amounts of delay according to respective positions being output from the plurality of respective delay elements; a time measurement unit that measures a unit interval time from a timing of a certain edge of the edge signal to a timing of an edge when a time corresponding to one bit lapses, based on levels of the signals output from the plurality of respective delay elements; and a phase selector that selects the signal output from the delay element in a position corresponding to the unit interval time measured by the time measurement unit among the plurality of delay elements, outputs the signal as the feedback clock, selects the signal output from any delay element among the plurality of delay elements, and outputs the signal as a clock at a frequency corresponding to the bit rate of the edge signal.