Patent ID: 7797519
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. A processor apparatus comprising: an instruction memory that stores therein an instruction set, the instruction set including: a complex condition setting storage unit that stores one or more complex conditions, and that, sets a plurality of conditions of each of the one or more complex conditions, upon execution of a plurality of the condition setting instructions; a condition comparison unit that performs, upon execution of said complex conditional branch instruction, comparison operations on the plurality of conditions that make up the complex condition in the destination of storage, of the complex conditional branch instruction, and that outputs results of the comparison operations; and a complex condition branching decision unit that compares the results of the comparison operations with the branching condition value of the complex conditional branch instruction, that determines whether or not branching to the branch target, of the complex conditional branch instruction, is to be performed, and that outputs a true or false.