Patent ID: 6944807
Filing Date: 2005-09-13
Classification: G11C

Abstract:
1. A circuit for obtaining a functional fractional on-chip cache comprising: a set of functional sub-arrays selected from a cache; a CPU initialized to address said set of functional sub-arrays; a set of decoders configured to select only rows from said set of functional sub-arrays; wherein a decoder from said set of decoders logically comprises: at least one address-select block, with three inputs and a complementary output, that selects an address bit or a first programmed fractional bit based on the binary value of a second programmed fractional bit, the first input connected to said address bit, the second input connected to said first programmed fractional bit, the third input connect to said second programmed fractional bit and said complementary output connected to a first and a second node; a least one logical NAND block, with at least two inputs and one output; wherein the output nodes of said address-select blocks are electrically connected to the inputs of said NAND blocks such that only one output of said NAND blocks is active.