Patent ID: 6389531
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A processor comprising:(a) an instruction buffer for storing instructions associated with a program executed by the processor, said instructions including: [i] a program branch control instruction, which includes a field for address information used for computing a target address for a branch instruction, and further includes a field specifying a target address storage location for storing said target address, and said program branch instruction further including a branch target instruction prediction field for indicating whether a branch target instruction associated with said program branch control instruction is likely to be executed; and [ii] a first type of program branch instruction, said first type of program branch instruction including a field identifying said target address storage location as containing a target address for an unconditional branch target instruction that is to be executed unconditionally for a program branch; [iii] a second type of program branch instruction, said second type of program branch instruction identifying said target address storage location as containing a target address for a conditional branch target instruction that is to be executed when a condition specified by said second type of program branch is satisfied, and said second type of program branch instruction further including a program branch prediction field for indicating whether a program branch is to be taken; and (b) a target instruction memory, said target instruction memory being randomly accessible and capable of containing a plurality of branch target instructions, including both said unconditional branch target instruction and said conditional branch target instruction, and wherein said branch target instructions constitute a target instruction of a corresponding program branch, and each have a target address stored in a target address storage location; (c) an instruction decoder which is configured: [i] for decoding said instructions and passing said instructions on to an execution unit in the processor, such that: 1) when said program branch control instruction is decoded, said target address is computed by said execution unit and stored in said target address storage location; 2) when said first type of program branch instruction is decoded, said target address storage location is used to identify said unconditional branch target instruction, and if said unconditional branch target instruction is in said target instruction memory, said unconditional branch target instruction is prepared for loading into said instruction decoder; when said second type of program branch instruction is decoded, said target address storage location is used to identify said conditional branch target instruction, and if said conditional branch target instruction is in said target instruction memory, and said program branch is predicted to be taken based on an evaluation of said program branch prediction field, said conditional branch target instruction is prepared for loading into said instruction decoder; and further wherein when said unconditional branch target instruction and/or said conditional branch target instruction is not in said target instruction memory, said unconditional branch target instruction and/or said conditional branch target instruction is fetched for loading into said target instruction memory and said instruction decoder.