Patent ID: 6658074
Filing Date: 2003-12-02
Classification: H03L,H04J

Abstract:
A clock signal reproducing circuit in a pulse stuffed synchronizing system which reproduces a lower order group signal from a higher order group signal, comprising:a destuffing circuit removing stuff pulses and unnecessary bits from said higher order group signal to output said lower order group signal, and outputting stuff data indicating existence or non-existence of positive stuff or negative stuff in said higher order group signal, said lower order group signal being accommodated in said higher order group signal by inserting said stuff pulses in said lower order group signal; a storage circuit storing said lower order group signal outputted from said destuffing circuit; a stuff rate determining circuit determining a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of said higher order group signal based on said stuff data outputted from said destuffing circuit; a control circuit outputting a control signal indicating a frequency division ratio based on said stuff rate; a variable frequency divider frequency dividing a clock signal of said higher order group signal based on said control signal outputted from said control circuit; and a phase synchronization oscillation circuit reproducing a clock signal of said lower order group signal based on said frequency-divided clock signal outputted from said variable frequency divider, said lower order group signal being read out from said storage circuit in response to said reproduced clock signal of said lower order group signal.