Patent ID: 9164910
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A data processing apparatus comprising: at least one processor; at least one dedicated data store for storing only data processed by said at least one processor; a shared data store for storing data processed by said at least one processor and at least one further device; and coherency control circuitry responsive to a write request from said at least one further device to determine if data related to an address targeted by said write request is stored in said at least one dedicated data store, and if it is, to force an eviction of said data stored in said at least one dedicated data store and to write said evicted data into said shared data store prior to performing said write request from said at least one further device to said shared data store; wherein said data is stored in said at least one dedicated data store in conjunction with an indicator indicating if said data stored in said at least one dedicated data store is consistent with data stored in a corresponding address in a further data store, and said coherency control circuitry, in response to said write request from said at least one further device, is configured to force eviction of said data stored in said at least one dedicated data store regardless of whether said data stored in said at least one dedicated data store is indicated as being consistent or inconsistent.