Patent ID: 6871298
Filing Date: 2005-03-22
Classification: G06F

Abstract:
1. A processor verification test apparatus that uses a golden model to generate a test program that verifies that a processor system under test properly executes two or more instructions issued and executed in parallel, comprising: a user preference queue that comprises queue entries wherein each queue entry further comprises an instruction to be tested, a group or tree of instructions to be tested, or a test generator control command; a plurality of resource-related data structures, wherein each said resource-related data structure comprises information concerning selected system resources of the golden model, wherein said information comprises two or more of the following: actual past state, actual present state, actual future state, predicted past state, predicted present state, or predicted future state; an instruction packer coupled to said user preference queue and said resource-related data structures, said instruction packer creates a group of N instructions valid for parallel execution by the golden model and the processor system under test, where N equals 1 or more; and an instruction generator and simulator that generates and simulates instructions that correspond to said group of N instructions created by said instruction packer, evaluates the updated architectural state of the golden model, and updates said resource-related data structures.