Patent ID: 6496920
Filing Date: 2002-12-17
Classification: G06F

Abstract:
A microprocessor comprising:(a) first processing unit having a plurality of input ports; (b) second processing unit having a plurality of input ports; (c) a first plurality of registers (d) a first plurality of multiplexers, directly coupled to the first and second processing units and to the first plurality of registers, such that the inputs to each of the first plurality of registers may be coupled by the first plurality of multiplexers directly to the outputs of either the first or second processing unit; (e) a second plurality of multiplexers, directly coupled to the first and second processing units and to the first plurality of registers, such that the outputs to each of the first plurality of registers may be coupled by the second plurality of multiplexers directly to any of the inputs of either the first or second processing unit; and, (f) a second plurality of registers, at least one of the second plurality of registers being coupled to the first processing unit, but not to the second processing unit and at least one of the second plurality of registers is coupled to the second processing unit but not to the first processing unit.