Patent ID: 8530960
Filing Date: 2013-09-10
Classification: H01L

Abstract:
1. A semiconductor device comprising a static memory cell having six MOS transistors arranged on a substrate, the six MOS transistors including wherein a length between an upper end of the third diffusion layer and a lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors is shorter than a length between an upper end of the first diffusion layer and a lower end of the second diffusion layer of each of the first and second NMOS access transistors, and a length between the upper end of the third diffusion layer of each of the third and fourth NMOS driver transistors and a lower end of the gate is different from a length between the lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors and an upper end of the gate.