Patent ID: 6513094
Filing Date: 2003-01-28
Classification: G06F

Abstract:
A processor-based device that supports both volatile memory devices and non-volatile memory devices on a shared data bus, the processor-based device comprising:a data bus; a processor coupled to the data bus; a non-volatile memory controller coupled to the data bus for controlling the non-volatile memory devices; a volatile memory controller coupled to the data bus for controlling the volatile memory devices; a non-volatile memory busy signal coupled between the non-volatile memory controller and the volatile memory controller to indicate the non-volatile memory controller is busy with the data bus; a non-volatile memory request signal coupled between the non-volatile memory controller and the volatile memory controller to indicate the non-volatile memory controller is requesting access to the data bus; and a volatile memory busy signal coupled between the volatile memory controller and the non-volatile memory controller to indicate the volatile memory controller is busy with the data bus.