Patent ID: 7750618
Filing Date: 2010-07-06
Classification: G01R,H03L

Abstract:
1. A method of testing a clock circuit having an output clock signal based on an input clock signal and a feedback clock signal, the method comprising: identifying a first frequency for the input clock signal; identifying a first tolerance for the first frequency, the first tolerance being a percentage of the first frequency, the first frequency and the first tolerance defining a first threshold frequency for the feedback clock signal and an output threshold frequency for the output clock signal; selecting a second frequency, the second frequency being higher than the first frequency; selecting a second tolerance for the second frequency, the second tolerance being a percentage of the second frequency, the second tolerance being higher than the first tolerance and defining a second threshold frequency being equal to or higher than the first threshold frequency; setting the input clock signal to the second frequency; determining a number of clock cycles of the input clock signal in an interval to within the second tolerance of the second frequency by starting a first counter at a start of the interval and stopping the first counter at an end of the interval; determining a number of clock cycles of the feedback clock signal in the interval by starting a second counter at the start of the interval and stopping the second counter at the end of the interval; and determining whether a frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.