Patent ID: 7084797
Filing Date: 2006-08-01
Classification: H03M

Abstract:
1. A delta sigma modulating apparatus comprising: a first delta sigma modulator including a first and a second adder, a first and a second integrator, a first quantizer, a first digital-to-analog converter, and first, second, and third computing elements; a second delta sigma modulator including a third and a fourth adder, a third and a fourth integrator, a second quantizer, a second digital-to-analog converter, and fourth, fifth, sixth, and seventh computing elements; and a signal synthesizer that includes an eighth computing element and synthesizes an output signal of said first delta sigma modulator with an output signal of said second delta sigma modulator, wherein: said first adder subtracts an analog output signal of said first digital-to-analog converter through said first computing element, from an externally inputted analog input signal, said first integrator integrates an analog output signal of said first adder through said second computing element, said second adder subtracts the analog output signal of said first digital-to-analog converter through said third computing element, from an analog output signal of said first integrator, said second integrator integrates an analog output signal of said second adder, said first quantizer outputs a digital signal corresponding to an analog output signal of said second integrator, said first digital-to-analog converter outputs an analog signal corresponding to the digital output signal of the first quantizer to said first and third computing elements, said third adder subtracts an analog output signal of said second digital-to-analog converter through said fifth computing element and an analog output signal of said fourth integrator from the analog output signal of said second integrator through said fourth computing element, said third integrator integrates an analog output signal of said third adder through said sixth computing element, said fourth adder subtracts an output signal of said second digital-to-analog converter through said seventh computing element from an analog output signal of said third integrator, said fourth integrator integrates an analog output signal of said fourth adder said second quantizer outputs a digital signal corresponding to an analog output signal of said fourth integrator, said second digital-to-analog converter outputs an analog signal corresponding to the digital output signal of said second quantizer to said fifth and seventh computing elements, said signal synthesizer adds a signal obtained by delaying the digital output signal of said first quantizer to a signal obtained by differentiating the digital output signal of said second quantizer and performing scaling through said eighth computing element, and outputs a result of the addition, and when a feedback amount of an analog signal inputted from said first quantizer to said first adder is the same as a feedback amount of an analog signal inputted from said second quantizer to said third adder, the following relationship is satisfied: a a c a b a c a