Patent ID: 6928596
Filing Date: 2005-08-09
Classification: G11C

Abstract:
1. A test circuit of a semiconductor integrated circuit comprising internal circuits in a semiconductor chip comprising: a test mode control circuit arranged in the vicinity of a pad for inputting a test code into the semiconductor chip for judging on the basis of the test code whether or not the mode is a test mode and outputting a test decode signal when the mode is the test mode; test code latch circuits provided in correspondence to the internal circuits for latching the test decade signal while decoding the test decode signal to select one of the internal circuits and outputting a test select signal for changing the characteristics of the selected internal circuit out of the internal circuits; test decode lines for transmitting the test decode signal from the test mode control circuit to the test code latch circuits; and test select signal lines for transmitting the test select signal from the test code latch circuit to the internal circuits; wherein the test code latch circuits are dispersed in the semiconductor chip and at least one of the test decode lines is longer than an average length of the test select signal lines.