Patent ID: 6621385
Filing Date: 2003-09-16
Classification: H01P

Abstract:
A balanced line network for use with lossy semiconductor substrates, comprising:first and second spaced apart parallel balanced conductive lines directed from a first end to a second end of said substrate and positioned on a top surface of said substrate, each line coupled to a symmetrically positioned transverse high impedance line which, as positioned, are shielded by said first and second lines, and are positioned to form first symmetrical inductive reactances for said lines, an insulating layer formed on said substrate and having a metallized area located thereon and symmetrically positioned between said first and second lines and said high impedance lines to provide a balanced capacitive reactance for said lines, said metallized area connected to said symmetrical high impedance lines which are positioned to co-act with said high impedance lines on a top surface of said layer to form second symmetrical inductive reactance for said lines, wherein said inductive reactances and said capacitive reactances resonate at a desired frequency and where the reactances are all referenced to a virtual ground as the space between said parallel balanced lines, and a bias line connected to said virtual ground.