Patent ID: 7961121
Filing Date: 2011-06-14
Classification: H03M

Abstract:
1. A semiconductor memory device, comprising: an input buffer configured to receive, in parallel, encoded data information from a plurality of external data information transmission lines of an external bus, the input buffer including a preamble detection circuit operable to detect a preamble having at least a first part and second part provided sequentially on the plurality of external data information transmission lines, the first part comprising first logic levels received from a first subset of n of the external data information transmission lines and second logic levels received from a second subset of (x-n) of the external data information transmission lines, where x is the number of data information transmission lines of the data bus and n is an integer less than x, and the second part comprising first logic levels received from a third subset of m of the external data information transmission lines and second logic levels received from a fourth subset of (x-m) of the external data information transmission lines, where m is an integer less than x, and wherein the first logic level is different from the second logic level and m is different from n.