Patent ID: 8530346
Filing Date: 2013-09-10
Classification: H01L

Abstract:
1. A process of forming an electronic device comprising: forming an interconnect level over a substrate, wherein the interconnect level further includes a bonding pad region; forming an insulating layer overlying the interconnect level; forming an opening in the insulating layer to expose the bonding pad region; forming a first barrier layer within the opening; forming a conductive stud within the opening, wherein from a top view, substantially all of the conductive stud lies within the opening; and forming a second barrier layer overlying the conductive stud, wherein the conductive stud is substantially encapsulated by the first and second barrier layers; and forming a solder bump over the second barrier layer, the conductive stud, and the bonding pad region of the interconnect level, wherein the solder bump is spaced apart from the conductive stud and the bonding pad region of the interconnect level.