Patent ID: 7496921
Filing Date: 2009-02-24
Classification: G06F

Abstract:
1. An apparatus comprising: a memory configured to store a thread switching structure; an execution block configured to execute instructions; and a thread management block coupled to the memory and the execution block, the thread management block equipped to maintain a thread switching structure in the memory to facilitate interleaving execution of a plurality of threads of instructions by the execution block, with the thread switching structure including a current thread identifier identifying one of the plurality of threads as a current thread being currently executed by the execution block, and a thread array of thread entries, one per thread, describing at least a plurality of registers of an external set of registers, on which the corresponding described thread depends, each thread entry being created and added to the thread array by the thread management block as part of the execution of a create thread instruction of a thread to spawn execution of another thread, and wherein the thread management block is further equipped to select a non-current one of the plurality of threads to be the new current thread to be executed on one of a round-robin basis, a fixed priority basis, or a rotating priority basis and switch execution to a first instruction of the new current thread as part of a thread switching instruction of a thread to instruct the execution block to switch execution to another thread.