Patent ID: 8310886
Filing Date: 2012-11-13
Classification: G11C,H03L

Abstract:
1. A delay locked loop (DLL) circuit comprising: a phase control circuit including a voltage-controlled delay line (VCDL) configured to generate an output signal based on a feedback signal output in response to a plurality of control signals, and an input signal; a plurality of phase detection circuits, each phase detection circuit configured to compare a phase of a signal selected from a signal set, the signal set including signals with different phases, with a phase of a reference signal and configured to output a control signal of the plurality of control signals that corresponds to a phase difference between the selected signal and the reference signal; a multiphase generation circuit configured to output the signal set based on the signal output from the phase control circuit, the input signal, and a first frequency-divided signal obtained by dividing a frequency of the input signal; and a sigma-delta (ΣΔ) modulation circuit configured to output a plurality of delay selection control signals having different phases and transmit the plurality of delay selection control signals to the plurality of phase detection circuits, the plurality of delay selection control signals output in response to a second frequency-divided signal having a phase different from a phase of the first frequency-divided signal.