Patent ID: 6690202
Filing Date: 2004-02-10
Classification: H03K

Abstract:
A circuit comprising:first and second supply nodes having first and second voltage levels, respectively; an amplifier having first and second differential outputs for providing a clock signal; a digital circuit having first and second differential inputs; a first capacitor having first and second nodes, with the first node coupled to the first output of the amplifier and the second node coupled to the first input of the digital circuit; a second capacitor having first and second nodes, with the first node coupled to the second output of the amplifier and the second node coupled to the second input of the digital circuit; first and second subcircuits for setting a DC voltage at the first input of the digital circuit to a third voltage level that is between the first and second voltage levels; wherein the first subcircuit is coupled between the second node of the first capacitor and the first supply node; and wherein the second subcircuit is coupled between the second node of the first capacitor and the second supply node; and third and fourth subcircuits for setting a DC voltage at the second input of the digital circuit to a fourth voltage level that is between the first and second voltage levels; wherein the third subcircuit is coupled between the second node of the second capacitor and the first supply node; and wherein the fourth subcircuit is coupled between the second node of the second capacitor and the second supply node.