Patent ID: 6351143
Filing Date: 2002-02-26
Classification: G11C

Abstract:
A system comprising:a. a programmable logic device (PLD) having: i. a PLD configuration port adapted to receive configuration data; ii. configuration memory cells connected to the configuration port and to the configurable logic resources, the configuration memory containing a first set of configuration data defining a content-addressable memory (CAM), the CAM including: (1) a data bus having a plurality of data lines; (2) a first configurable look-up table (LUT) having a first plurality of LUT input terminals and a first LUT output terminal, wherein the first LUT input terminals connect to respective ones of the data lines, and wherein the first LUT is configured to output a first match signal on the first LUT output terminal in response to a first bit pattern presented on the data bus; (3) a second configurable look-up table (LUT) having a second plurality of LUT input terminals and a second LUT output terminal, wherein the second LUT input terminals connect to respective ones of the data lines, and wherein the second LUT is configured to output a second match signal on the second LUT output terminal in response to a second bit pattern presented on the data bus; and b. a processor having a configuration output port connected to the PLD configuration port, the processor adapted to present a second set of configuration data to the PLD configuration port; c. wherein the configuration memory, upon being presented the second set of configuration data on the configuration port, stores the second set of configuration data; and d. wherein the second set of configuration data configures the first LUT to output the first match signal on the first LUT output terminal in response to a third bit pattern presented on the data bus.