Patent ID: 6701509
Filing Date: 2004-03-02
Classification: G06F,H01L

Abstract:
A method of designing the conductor layout for an integrated circuit, the method comprising:selecting a plurality of electrically insulated layers of conductors to be placed adjacent to cells that occupy area in a substrate level of the integrated circuit, the plurality of electrically insulated layers including: a first layer being immediately adjacent to a substrate level, a second layer adjacent the first layer, a third layer adjacent the second layer, and one or more upper layers that are farther removed from the substrate level than the third layer; the plurality of electrically insulated layers being used to provide power conductors, ground conductors, and signal conductors, placing the power conductors and ground conductors substantially only in a the first layer and the one or more upper layers, thereby allowing the signal conductors to be substantially freely placed in the second layer and the third layer; placing at least one of the signal conductors in any of the plurality of layers and the power and around conductors in the first layer based on the placing of the power and ground conductors in the upper layers; and placing stacked vias connecting the power and ground conductors of the upper layers to respective power and ground conductors of the first layer.