Patent ID: 7401278
Filing Date: 2008-07-15
Classification: G01R,G11C,H03K

Abstract:
1. A binary latch using only one system clock having an output comprising: an edge-triggered master flip-flop having a first input connected to the system clock and a second input connected to a data input and an output; a level sensitive scan design (LSSD) slave latch which is used only in a test mode with its input connected to the output of the edge-triggered master flip-flop; and a first NAND gate having a first input connected to the system clock a second input connected to a test input and an output connected to an LSSD slave latch clock input which controls the output of the binary latch to be either a scan output in test mode or to follow the contents of the edge-triggered master flip-flop depending if the LSSD latch clock input is high or low.