Patent ID: 8629699
Filing Date: 2014-01-14
Classification: H03L,H04L

Abstract:
1. A clock data recovery circuit comprising: a sampling circuit; an edge detector; a phase selection signal generating circuit; and a clock data generating circuit, wherein the sampling circuit samples a received data signal with the use of multi-phase clock signals, and generates a plurality of sampling signals, wherein the edge detector responds to the sampling signals and the multi-phase clock signals, and generates a plurality of edge detection signals, wherein the phase selection signal generating circuit responds to the edge detection signals and the multi-phase clock signals, and generates a plurality of phase selection signals, wherein the clock data generating circuit responds to the sampling signals, the phase selection signals, and the multi-phase clock signals, and generates a reproduction clock and reproduction data, wherein the edge detector comprises a plurality of edge detection circuits which respond to the sampling signals and the multi-phase clock signals and generate the plural edge detection signals, wherein each of the plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit, wherein when the first edge detection circuit detects that an data edge of the received data signal supplied currently is leading more than −1 phase of the multi-phase clock signals from an edge detection phase of one edge detection clock signal corresponding to the data edge detection phase of the each edge detection circuit among the multi-phase clock signals, the first edge detection circuit generates a first edge detection output signal, wherein when the second edge detection circuit detects that the data edge of the received data signal supplied currently is lagging more than +1 phase of the multi-phase clock signals from the edge detection phase of one edge detection clock signal corresponding to the data edge detection phase of the each edge detection circuit among the multi-phase clock signals, the second edge detection circuit generates a second edge detection output signal, wherein, in response to the first edge detection output signal or the second edge detection output signal, a next edge detection phase of the edge detector is changed by the amount of −1 phase or +1 phase from the edge detection phase of the one edge detection clock signal, wherein the first edge detection circuit and the second edge detection circuit are operable to detect that the data edge of the received data signal supplied currently lies in the range of ±1 phase of the multi-phase clock signals from the edge detection phase of one edge detection clock signal corresponding to the data edge detection phase of the each edge detection circuit among the multi-phase clock signals, and wherein when the first edge detection circuit and the second edge detection circuit detect that the data edge of the received data signal supplied currently lies in the range of ±1 phase, the next edge detection phase of the edge detector is maintained at the edge detection phase of the one edge detection clock signal.