Patent ID: 9147446
Filing Date: 2015-09-29
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array including a plurality of memory cells, a first power supply line supplied with a first potential; a second power supply line supplied with a second potential higher than the first potential; a third power supply line supplied with a third potential higher than the second potential; a level conversion circuit coupled to the first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between the first and second potentials, and outputting a second signal having an amplitude between the first and third potentials, wherein the first signal is an internal data signal read from the memory cell array; a delay circuit, coupled to the first and second power supply lines, and outputting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.