Patent ID: 6897520
Filing Date: 2005-05-24
Classification: H01L

Abstract:
1. A nonvolatile EPROM or EEPROM memory cell formed using a vertical MOS transistor comprising: a semiconductor substrate doped to have a first conductivity type so as to act as a source region of said nonvolatile memory cell, said first conductivity type being either N-type or P-type, and having a top surface which extends horizontally and a depth which extends vertically; a vertical MOS transistor formed by alternating, abutting N-type and P-type doped layers in said substrate which have junctions therebetween to form a channel region and a drain region of said vertical MOS transistor with said drain region having A, said first conductivity type and said channel region having a second conductivity type which is P-type if said first conductivity type is N-type and is N-type if said first conductivity type is P-type, said substrate forming a source region of said first conductivity type of said vertical MOS transistor, said source regions having a junction with said channel region, and wherein a well with one or more walls is etched vertically down through said top surface of said substrate and through said channel and drain regions and at least partially into said source region such that at least said drain and channel regions surround said well and form at least a portion of said one or more walls of said well, said well having a bottom and having formed therein a self aligned floating gate of conductive material which does not have any horizontal component on said top surface of said substrate through which said well was etched nor on said bottom of said well and which does not extend laterally beyond a perimeter of said well, said perimeter of said well being defined by an intersection of said one or more walls of said well and said surface of said substrate into which said well was etched, and said self aligned floating gate insulated from said channel and drain regions and said substrate by a layer of insulating material, said floating gate being laterally adjacent to at least said portion of said wall of said well formed by said channel region of said vertical MOS transistor such that differing levels of trapped charge in said floating gate affects the conductivity of said channel region and a threshold of said nonvolatile memory cell; a word line contact which also functions as a control gate of said nonvolatile memory cell comprising a layer of conductive material formed on said substrate so as to extend vertically down into said well and lie laterally adjacent to said floating gate but be X; insulated therefrom by an insulation layer such that voltage applied to said control gate affects the charge on said floating gate; a spacer insulating layer formed on top and side surfaces of said word line contact, with an edge of said spacer insulating layer defining an inner edge of a contact hole to said drain region, said inner edge being an edge of said contact hole closest to said well; and a self aligned bit line and contact to the drain area of said vertical MOS transistor, said self aligned bit line comprising a layer of conductive material formed on said substrate so as to be in electrical contact with said drain region of said vertical MOS transistor via a self aligned contact hole.