Patent ID: 6630706
Filing Date: 2003-10-07
Classification: H01L,Y10S

Abstract:
A memory array of a DRAM device, the memory array comprising:a plurality of memory cells for storing information, wherein the memory cells are arranged into a plurality of cell pairs such that each pair includes first and second cells each comprising a storage element for storing charge and a valve element for controlling the flow of charge to and from the corresponding storage element, wherein the valve elements of each cell pair are disposed adjacent each other and the charge storage elements of the cell pair are outwardly disposed from the valve elements of the cell pair; and a substrate comprising a plurality of valve regions and a plurality of storage regions, wherein the valve regions are disposed between the storage regions so as to define an active region interposed between first and second channel regions, and wherein the first and second valve elements of each cell pair overlie the first and second channel regions, respectively, and wherein the first and second storage elements of each cell pair are electrically coupled to respective first and second storage regions of the plurality of storage regions, and wherein the defined valve regions of the substrate include a first concentration of complementary dopant atoms and the storage regions of the substrate include a reduced second concentration of complementary dopant atoms, thereby reducing the rate at which charge escapes from the charge storing elements during quiescent periods.