Patent ID: 9146707
Filing Date: 2015-09-29
Classification: G06F

Abstract:
1. A 3× generation circuit comprising: an input for receiving a single n-bit multiplicand comprising bits a[n−1:0]; logic device for isolating groups of adjacent bits of said single n-bit multiplicand, wherein adjacent bits of each group includes a bit a[i] corresponding to a bit location of said single n-bit multiplicand, an adjacent bit a[i+1] of said group corresponds to a bit shifted representation of said single n-bit multiplicand, and an adjacent bit a[i−1], said groups of adjacent bits being obtained for i=0, 1, . . . n−2; a parallel prefix adder device employing levels of logic gates forming a carry tree circuit, a first level of logic gates receiving said groups of obtained adjacent bits a[i+1], a[i], a[i−1] for bits i=0, 1, . . . n−2 of said single n-bit multiplicand input, successively generating at each level corresponding Generate terms, Propagate terms and corresponding carry bits resulting from processing said groups at said one or more processing logic levels, said parallel prefix adder device performing an addition based on said generated Generate terms, Propagate terms and corresponding carry bits, wherein an output of said addition comprise bits of a value corresponding to 3× said single n-bit multiplicand.