Patent ID: 6195302
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A memory device comprising:a plurality of sense amplifiers distributed about an integrated circuit chip, each sense amplifier having a power node for receiving current;a low-impedance power supply conductor;at least one drive transistor having a first current carrying electrode coupled to the power supply conductor, a second current carrying electrode coupled to the power nodes of a preselected number of the sense amplifiers, and a control electrode;a control line coupled to the control electrode;a timer unit having an output coupled to the control electrode and generating a control signal;a first component within the timer unit causing the control signal to change from a first logic level towards a second logic level at a first rate; anda second component within the timer unit causing the control signal to change to the second logic level at a second rate, wherein the second rate is greater than the first rate such that the first component and the second component are concurrently activated to cumulatively affect the rate of change to the second logic level.