Patent ID: 9191193
Filing Date: 2015-11-17
Classification: H03L,H04L

Abstract:
1. A clock synchronization circuit, comprising: a multi-phase clock generator configured to generate a plurality of delayed clocks from a source clock, each delayed clock having a unique delay with regard to the source clock; and a selector circuit configured to select one of the delayed clocks based upon a phase error, the selector circuit being further configured to launch the selected one of the delayed clocks through a clock path so as to receive a local clock from the clock path, the selector circuit being further configured to compare the received local clock from the local clock path to a reference clock to determine the phase error, and wherein the selector circuit includes a multi-phase detector configured to compare the received local clock to the plurality of delayed clocks to determine a first digital word and to compare the reference clock to the plurality of delayed clocks to determine a second digital word, and wherein the multi-phase detector is further configured to compare the first and second digital words to determine the phase error.