Patent ID: 6430654
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A cache memory system comprising:a first non-blocking cache receiving access requests from a plurality of functional units in a processor, said first non-blocking cache being a multi-port write through cache including at least one read port and at least one write port; a first miss queue dedicated to storing entries corresponding to access requests not serviced by said first non-blocking cache; a first cache controller, said first cache controller including an arbiter, said first cache controller for controllably prioritizing between said functional units requesting access to said first non-blocking cache; a second non-blocking cache adapted to receive access requests from said first miss queue and from said functional units said second non-blocking cache being a muti-port write back cache including at least one read port and at least one write port; a second miss queue independent of the first miss queue and dedicated to storing entries corresponding to access requests not serviced by said second non-blocking cache; a first victim queue, said first victim queue dedicated to storing entries that have been evicted from said second non-blocking cache due to a fill operation until a write back operation is performed; a first write queue, said first write queue storing a write request for said second non-blocking cache until a write hit is achieved and the address needed to write into said second non-blocking cache is obtained; a second cache controller, said second cache controller including an arbiter, said second cache controller for controllably prioritizing between said functional units requesting access to said second non-blocking cache; a third non-blocking cache receiving access requests from said second miss queue, said third non-blocking cache being a multi-port write back cache including at least one read port and at least one write port; a third miss queue storing entries corresponding to access requests not serviced by said third non-blocking cache; a second victim queue, said second victim queue dedicated to storing entries that have been evicted from said third non-blocking cache due to a fill operation until a write back operation is performed; a second write queue, said second write queue storing a write request for said third non-blocking cache until a write hit is achieved and the address needed to write into said third non-blocking cache is obtained; and a third cache controller, said third cache controller including an arbiter, said third cache controller for controllably prioritizing between said functional units requesting access to said third non-blocking cache.