Patent ID: 6976130
Filing Date: 2005-12-13
Classification: G06F

Abstract:
1. A cache controller unit (CCU) architecture with dirty line write-back auto-adjustment, suitable for high performance microprocessor systems having a write-back cache memory, a tag memory, a central processing unit (CPU), and a bus interface unit (BIU) with a write buffer, the architecture comprising: a cache data control unit to access data between the cache memory and the CPU; a tag compare unit to compare an address output sent by the CPU and a tag address output sent by the tag memory and thus produce a cache hit signal; a CCU state machine to control the access direction of the cache data control unit according to the tag compare result, write a dirty line to the write buffer if a dirty flag is set and the write buffer is empty, issue a fill request to the BIU in order to request the BIU to fetch data of a new cache line if the dirty flag is not set, or set the dirty flag and continue the CPU operation if the write buffer is not empty so that the replace line becomes a new dirty line; and a fill buffer to store information sent by the BIU and provide the information to the CCU state machine for operation, wherein the information includes data and addresses of a miss line.