Patent ID: 8582373
Filing Date: 2013-11-12
Classification: G11C

Abstract:
1. A device, comprising: a stack of memory dies directly connected to one another; a command die coupled to communicate with the stack of memory dies; and a first buffer die stacked within the stack of memory dies, and coupled between the command die and a downstream memory die in the stack of memory dies, wherein the first buffer die is configured to communicate with the command die, and repeat a signal between the command die and a downstream memory die in the stack of memory dies; a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies; wherein at least one of the first and second buffer dies is configured to communicate with a memory die above the respective buffer die in the stack of memory dies and is configured to communicate with a memory die below the respective buffer die in the stack of memory dies, and wherein the first and second buffer dies are configured to repeat memory signals.