Patent ID: 7899145
Filing Date: 2011-03-01
Classification: H03K,H04J

Abstract:
1. An apparatus, comprising: a plurality of power supply domains; and a plurality of logic components, each of the plurality of logic components within a different one of the plurality of power supply domains, wherein each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains, wherein the plurality of power supply domains comprises first, second, third and fourth power supply domains, wherein a plurality of logic components comprises: a first logic gate arranged within the first power supply domain and configured to operate with a first clock signal; a second logic gate arranged within the second power supply domain and configured to operate with a second clock signal; a first logic block arranged within the third power supply domain and coupled to the first and second logic gates; and a second logic block arranged within the fourth power supply domain and coupled to the first and second logic gates.