Patent ID: 6200834
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method of forming a semiconductor device, comprising:forming a substrate with a memory array region and a logic device region;growing a thick gate dielectric over said substrate;forming a gate stack, including a first polysilicon layer, over the thick gate dielectric for the memory array region;removing the thick gate dielectric over said logic device region;forming a thin gate dielectric on said substrate over said logic device region, wherein layers of the gate stack in the memory array region protect the thick gate oxide during the forming of the thin gate dielectric;forming a second polysilicon layer for a gate stack in the logic device region, to produce a resulting structure, wherein a thickness of the second polysilicon layer is at least as thick as the gate stack in the memory array region;planarizing the structure using chemical mechanical polishing (CMP); andpatterning the gate stacks in said memory array region and said logic device region such that a planar surface is provided during all of said patterning of the gate stacks and said gate stacks each have a planar gate stack.