Patent ID: 7843005
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming at least one field effect transistor on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, said SOI substrate further comprising a bottom semiconductor layer having a doping concentration; forming a shallow trench isolation structure in said top semiconductor layer, wherein said shallow trench isolation structure laterally abuts and surrounds said at least one field effect transistor; forming a doped semiconductor region in said bottom semiconductor layer, wherein said doped semiconductor region abuts said buried insulator layer and has a doping of a same conductivity type as said bottom semiconductor layer, and further wherein said doped semiconductor region has a doping concentration greater than a doping concentration of said bottom semiconductor layer, said doped semiconductor region located in a region that is not below said at least one field effect transistor; forming a middle-of-line (MOL) dielectric layer over said at least one field effect transistor and said shallow trench isolation structure; and forming at least one conductive via extending from a top surface of said MOL dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to said doped semiconductor region, wherein said at least one conductive via comprises a contact via of unitary construction and laterally surrounding an entirety of said at least one field effect transistor.