Patent ID: 6847238
Filing Date: 2005-01-25
Classification: H03K

Abstract:
1. An output circuit for outputting data with reduced simultaneous switching output skew, said output circuit comprising: N counts of output buffers receiving N counts of bit signals, respectively, at least one of said output buffers comprising a delay unit for processing one of said bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to said delay unit and a source voltage, and selectively enabled to output said delayed bit signal as a high level, and a pull-down unit electrically connected to said delay unit and a ground voltage, and selectively enabled to output said delayed bit signal as a low level; and a comparator in communication with said N counts of output buffers, comparing said N counts of bit signals sampled at a first time spot and a second time spot, and generating said delay signal according to the comparing result.