Patent ID: 6100133
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method for manufacturing a capacitor with metallic conducting electrodes during the manufacturing of an integrated circuit intended for preferably high-frequency applications comprising the steps of:a) depositing a first metal layer on a layer structure comprising lowermost a substrate and uppermost a first insulating layer to form a lower electrode;b) depositing a second insulating layer over the first metal layer;c) etching a via hole through said second insulating layer to provide an electrical connection path to said lower electrode;d) plugging said via hole with a conductive material;e) uncovering the first metal layer by etching the second insulating layer to form a capacitor opening;f) forming a capacitor dielectric in the capacitor opening by depositing a dielectric layer over the structure formed by steps a)-e), including patterning and etching said dielectric layer so that the capacitor dielectric overlaps said second insulating layer; andg) depositing a second metal layer on the structure formed by said steps a)-f) to form an upper electrode and a connecting layer; including patterning and etching said second metal layer so that the upper electrode overlaps said second insulating layer and so that the connecting layer overlaps the plugged via hole.