Patent ID: 8754914
Filing Date: 2014-06-17
Classification: G09G

Abstract:
1. A testing circuit of a dual gate cell panel, the testing circuit being installed on the dual gate cell panel, and the testing circuit comprising: a first group of data lines, electrically coupled to a first test pad, and coupled to a plurality of first sub-pixels and a plurality of second sub-pixels; a second group of data lines, electrically coupled to a second test pad, and coupled to a plurality of third sub-pixels and a plurality of fourth sub-pixels; a third group of data lines, electrically coupled to a third test pad, and coupled to a plurality of fifth sub-pixels and a plurality of sixth sub-pixels; a first group of scan lines, electrically coupled to a fourth test pad, and coupled to the first sub-pixels, the third sub-pixels and the fifth sub-pixels; and a second group of scan lines, electrically coupled to a fifth test pad, and coupled to the second sub-pixels, the fourth sub-pixels and the sixth sub-pixels; wherein, the first sub-pixels and the fourth sub-pixels are first color sub-pixels, and the second sub-pixels and the fifth sub-pixels are second color sub-pixels, and the third sub-pixels and the sixth sub-pixels are third color sub-pixels, wherein, each of the first sub-pixels, each of the second sub-pixels, each of the third sub-pixels, each of the fourth sub-pixels, each of the fifth sub-pixels and each of the sixth sub-pixels are individually displayed in response to a first to a fifth periodic signals respectively inputted into the fourth, the fifth, the first, the second and the third test pads, wherein the phase of one of the first and second periodic signals is opposite to the phase of another one of the first and second periodic signals and the phases of the third, fourth, and fifth periodic signals.