Patent ID: 6365471
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method for producing PMOS devices, said method comprising:providing a n-type semiconductor substrate; forming a gate oxide layer on said n-type semiconductor substrate; forming a gate layer on said gate oxide layer; patterning both said gate layer and said gate oxide layer to define a gate; firstly implanting said n-type semiconductor substrate using said gate as a mask to form at least two high doped drain regions (HDDs), and forming a silicon nitride layer on top of the exposed surface of said gate and on said n-type semiconductor substrate, wherein said silicon nitride layer can be formed either before said semiconductor substrate is firstly implanted or after said semiconductor substrate is firstly implanted, wherein available dopants of said firstly implantation comprise boron and boron fluoride, and said silicon nitride layer could be used to prevent boron segregation and out diffusion; forming a first dielectric layer on said silicon nitride layer; forming a dielectric spacer on sidewall of said gate layer and said gate oxide layer by anisotropically etching portion of said first dielectric layer; secondly implanting said n-type semiconductor substrate to form source/drain regions having a conductivity type opposite to the semiconductor substrate by using said gate and said dielectric spacer as a mask; annealing the resulting structure; etching isotroptically said silicon nitride layer, for reducing fringing capacitance; and forming silicide on said source/drain regions and said gate.