Patent ID: 6586833
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A packaged power device, comprising:an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange; an electrically conductive substrate mounted within the slot; a dielectric layer on said electrically conductive substrate; a gate electrode strip line that is patterned on said dielectric layer and extends opposite the electrically conductive substrate, said gate electrode strip line having an upper surface that is coplanar with the primary surface of said electrically conductive flange; and a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of the primary surface of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to the upper surface at a first end of said gate electrode strip line and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface.