Patent ID: 7692644
Filing Date: 2010-04-06
Classification: G09G

Abstract:
1. A display apparatus comprising: a display panel including a plurality of pixels; and a driving circuit to drive the display panel; the driving circuit including a register in which a set value for generating gradation voltages corresponding to display data inputted from an external system is stored, a reference ladder circuit to generate reference voltages in accordance with the set value, a buffer circuit to buffer the reference voltages to be outputted, a gradation voltage ladder circuit to generate gradation voltages on the basis of the reference voltages and an output control circuit to select gradation voltages corresponding to the display data from the gradation voltages to be outputted; the reference ladder circuit including fixed resistors and variable resistors having resistance values to be controlled by the set value; the fixed resistors including switches, wherein the reference ladder circuit includes: a first variable resistor having one end connected to a reference high voltage source, a first fixed resistor connected in series to the first variable resistor and a first switch connected in parallel to the first fixed resistor; a second variable resistor connected in series to the first fixed resistor, a second fixed resistor connected in series to the second variable resistor and a second switch connected in parallel to the second fixed resistor; a third variable resistor connected in series to the second fixed resistor, a third fixed resistor connected in series to the third variable resistor and a third switch connected in parallel to the third fixed resistor; a fourth variable resistor connected in series to the third fixed resistor, a fourth fixed resistor connected in series to the fourth variable resistor and a fourth switch connected in parallel to the fourth fixed resistor; a fifth variable resistor connected in series to the fourth fixed resistor, a fifth fixed resistor connected in series to the fifth variable resistor and a fifth switch connected in parallel to the fifth fixed resistor; a sixth variable resistor connected in series to the fifth fixed resistor, a seventh variable resistor connected in series to the sixth variable resistor and a sixth fixed resistor connected in series to the seventh variable resistor; an eighth variable resistor connected in series to the sixth fixed resistor; a ninth variable resistor connected in series to the eighth variable resistor, a seventh fixed resistor connected in series to the ninth variable resistor and a sixth switch connected in parallel to the seventh fixed resistor; a tenth variable resistor connected in series to the seventh fixed resistor, an eighth fixed resistor connected in series to the tenth variable resistor and a seventh switch connected in parallel to the eighth fixed resistor; an eleventh variable resistor connected in series to the eighth fixed resistor, a ninth fixed resistor connected in series to the eleventh variable resistor and an eighth switch connected in parallel to the ninth fixed resistor; a twelfth variable resistor connected in series to the ninth fixed resistor, a tenth fixed resistor connected in series to the twelfth variable resistor and a ninth switch connected in parallel to the tenth fixed resistor; a thirteenth variable resistor connected in series to the tenth fixed resistor, an eleventh fixed resistor connected in series to the thirteenth variable resistor and a tenth switch connected in parallel to the eleventh fixed resistor; and a fourteenth variable resistor connected in series to the eleventh fixed resistor and a twelfth fixed resistor connected in series to the fourteenth variable resistor and having one end connected to a reference low voltage source; and a first reference voltage is generated from a junction between the first variable resistor and the first fixed resistor; a second reference voltage being generated from a junction between the second variable resistor and the second fixed resistor; a third reference voltage being generated from a junction between the third variable resistor and the third fixed resistor; a fourth reference voltage being generated from a junction between the fourth variable resistor and the fourth fixed resistor; a fifth reference voltage being generated from a junction between the fifth variable resistor and the fifth fixed resistor; a sixth reference voltage being generated from a junction between the sixth variable resistor and the seventh variable resistor; a seventh reference voltage being generated from a junction between the eighth variable resistor and the ninth variable resistor; an eighth reference voltage being generated from a junction between the seventh fixed resistor and the tenth variable resistor; a ninth reference voltage being generated from a junction between the eighth fixed resistor and the eleventh variable resistor; a tenth reference voltage being generated from a junction between the ninth fixed resistor and the twelfth variable resistor; an eleventh reference voltage being generated from a junction between the tenth fixed resistor and the thirteenth variable resistor; a twelfth reference voltage being generated from a junction between the eleventh fixed resistor and the fourteenth variable resistor.