Patent ID: 6218271
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method of forming a landing pad on the drain and source of a metal oxide semiconductor (MOS) transistor, the MOS transistor being formed on a silicon substrate of a semiconductor wafer and comprising a gate positioned on the silicon substrate with a spacer positioned around its periphery portion, a drain and a source formed on the surface of the silicon substrate and positioned at two opposite sides of the gate, the method comprising:forming a conductive layer of an uniform thickness above each of the drain and source of the MOS transistor wherein the two conductive layers are used as the landing pads of the drain and source, and the height of each of the two conductive layers is lower than that of the spacer surrounding the periphery portion of the gate so that the gate and the two conductive layers are electrically isolated by the spacer.