Patent ID: 7372745
Filing Date: 2008-05-13
Classification: G11C

Abstract:
1. A dynamic random access memory (DRAM) comprising: a data signal input circuit configured to input a data signal in response to a data control signal; a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control signal; a control circuit configured to separately generate said data control signal and said data strobe control signal; a data latch circuit configured to latch said data signal from said data signal input circuit in response to said data strobe signal from said data strobe signal input circuit; a memory cell array having a plurality of memory cells arranged in a matrix, wherein said latched data signal is stored in a selected one of said plurality of memory cells through said data buffer; an amplifier circuit configured to amplify a data signal read out from said selected memory cell; and an output circuit configured to output the amplified data signal.