Patent ID: 7359273
Filing Date: 2008-04-15
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of sub-arrays, each including a plurality of memory cells; a plurality of sense amplifier regions, each disposed between two sub-arrays that are adjacent to each other in a direction of bit lines of the memory cells, wherein, in each of the sense amplifier regions, a plurality of bit line sense amplifiers for sensing and amplifying data on a pair of bit lines of a corresponding sub-array is arranged; and a plurality of word line driver regions, each disposed between two sub-arrays that are adjacent to each other in a direction of word lines of the memory cells, wherein, in each of the word line driver regions, a plurality of sub-word line drivers operated to drive a word line specified by a word line enable signal and a delayed decoding signal and an inverted decoding signal, which form a pair, is arranged, the word line enable signal specifying a word line group composed of a plurality of word lines, and the pair of decoding signals specifying a single word line from the specified word line group, wherein decoding drivers for generating the delayed decoding signal and the inverted decoding signal in response to corresponding pre-decoding signals are arranged in the sense amplifier regions.