Patent ID: 6730583
Filing Date: 2004-05-04
Classification: H01L

Abstract:
A method for fabricating a semiconductor memory device having a p-type source/drain, the method comprising the steps of:forming a first amorphous layer in a p-type source/drain region by implanting first dopants including fluorine and boron; implanting second dopants including boron in the first amorphous layer formed in the p-type source/drain region; performing a plurality of subsequent processes accompanying a thermal treatment; performing a first rapid thermal annealing process for activating the first dopants and the second dopants; forming the p-type source/drain by performing a thermal treatment for activating the first dopants and the second dopants; forming a contact hole that exposes the p-type source/drain region by selectively removing an insulating layer covering the P-type source/drain region; forming a second amorphous layer in a second p-type source/drain region exposed under the contact hole by implanting third dopants including fluorine and boron; implanting fourth dopants including boron in the second amorphous layer; and performing a thermal treatment for activating the third dopants and the fourth dopants.