Patent ID: 6887748
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. A mixed-mode process for integration circuits comprising: providing a semiconductor substrate, a surface of the semiconductor substrate comprising at least a first conductor formed in a first conductive region, at least a second conductor formed in a second conductive region, at least a metal-oxide-semiconductor (MOS) transistor formed in a MOS transistor region, and at least a capacitor formed in a capacitor region; forming a mask on the semiconductor substrate to cover the MOS transistor, the first conductor, and the capacitor and to expose the second conductor; performing a first etching process to remove a specific thickness of the second conductor; and performing a first ion implantation process to dope the second conductor with first type dopants; wherein the order of the first etching process and the first ion implantation process can be switched.