Patent ID: 8379786
Filing Date: 2013-02-19
Classification: H03L

Abstract:
1. A Delay-lock Loop (DLL) comprising: a) a phase detector for comparing a phase of a system clock and a feedback clock and for providing up and down control signals, b) an adjustable coarse delay circuit and an adjustable fine delay circuit connected in series for delaying the system clock and for providing the feedback clock, c) a fine delay counter for providing a fine delay count value for controlling a delay of the adjustable fine delay circuit, the fine delay counter being updatable based on the up and down control signals and overflow and underflow conditions of the fine delay counter, d) a coarse delay counter providing a coarse delay count value to control the delay of the adjustable coarse delay circuit, the coarse delay counter being updatable based on the up and down control signals, and the overflow and underflow conditions of the fine delay counter, e) a delay compensation circuit for providing either a multi-bit value or a complement of the multi-bit value to the fine delay counter, wherein, when no fine delay counter overflow condition is present and the up control signal is detected, incrementing the fine delay counter; when no fine delay counter underflow condition is present and the down control signal is detected, decrementing the fine delay counter; when a fine delay counter underflow condition is present and the down control signal is detected, decrementing the coarse delay counter and adding the multi-bit value to the fine delay counter; and when a fine delay counter overflow condition is present and the up control signal is detected, incrementing the coarse delay counter and adding the complement of the multi-bit value to the fine delay counter.