Patent ID: 7412586
Filing Date: 2008-08-12
Classification: G06F

Abstract:
1. A machine with switch memory architecture comprising: a d-dimensional grid of N processing elements (PEs), where d and N are arbitrary integers; at least one d-dimensional grid of N memory banks (MBs); and at least one programmable interconnection switch (ISWITCH) having a (d+1)-dimensional grid of switching elements (SEs) configurable to interconnect the N PEs to N MBs, such that each memory bank (MB) of the N MBs is mapped local to one processing element (PE) of the N PEs, wherein the ISWITCH being reconfigurable to remap the interconnection of N PEs to N MBs such that each memory bank (MB) becomes local to a different PE of the N PEs; wherein each SE transfers its state to a neighbor SE to remap the interconnection of N PEs to N MBs in a single clock cycle.