Patent ID: 6950902
Filing Date: 2005-09-27
Classification: G06F

Abstract:
1. A cache memory system including a small-capacity cache memory which enables high-speed access and is provided between a processor and a main memory, comprising: a software cache controller which performs software control for controlling data transfer to the cache memory in accordance with a preliminarily programmed software; and a hardware cache controller which performs hardware control for controlling data transfer to the cache memory by using a predetermined hardware; wherein the processor causes the software cache controller to perform the software control but causes the hardware cache controller to perform the hardware control when it becomes impossible to perform the software control, when a cache miss happens at the time of the software control, the processor automatically causes the hardware cache controller to perform the hardware control, and the hardware cache controller performs line management of the cache memory by using a set-associative method for multiple ways, and the software cache controller performs line management of the cache memory by using a fully associative method for at least one way of said multiple ways and by using the set-associative method for at least another one way of said multiple ways.