Patent ID: 7511334
Filing Date: 2009-03-31
Classification: H01L

Abstract:
1. A SONOS memory, comprising: a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions; twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers including a first ONO dielectric layer on the channel region and the source region and a second ONO dielectric layer on the channel region and the drain region; a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate; a gate dielectric layer extending below the control gate between the twin ONO dielectric layers, wherein a portion of the gate dielectric layer directly contacts the semiconductor substrate; at least one insulating spacer spaced apart from the gate dielectric layer and directly contacting at least a portion of one upper oxide layer of the twin ONO dielectric layers; a conductive spacer on the one upper oxide layer and contacting the gate dielectric layer; and a conductive layer contacting the at least one insulating spacer, the conductive spacer, the gate dielectric layer and the control gate, wherein: at least one of the source and drain regions includes a first impurity region and a second impurity region, the first impurity region being in direct contact with the second impurity region, the first and second impurity regions having different impurity concentrations, the first impurity region extends under at least one of the first and second ONO dielectric layers, and the second impurity region extends under the at least one insulating spacer and laterally away from the channel region, such that part of the second impurity region is not under the at least one insulating spacer.