Patent ID: 7409486
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. A storage system which can receive and process IO commands from an external device, which is a device that is present externally, comprising: a plurality of storage devices; and a storage control device which communicates with at least one storage device among said plurality of storage devices, according to IO commands from said external device, wherein said storage control device comprises: a protocol chip, which receives IO commands from said external device, which has a storage resource, and which is a circuit for controlling sending and receiving of data according to a predetermined protocol; a micro processor which creates parameter information for said protocol chip; a local memory, which is a memory that can be accessed by said micro processor; a bridge circuit which mediates communication between said protocol chip and said micro processor; a first bus which is connected to said protocol chip and to said bridge circuit; and a second bus which is connected to said bridge circuit and to said micro processor, wherein when receiving an IO command from said external device, said protocol chip writes said IO command into said local memory, wherein said micro processor reads said IO command from said local memory, generates parameter information for said protocol chip, writes said generated parameter information into said local memory, and issues to said protocol chip a write command which includes access destination information, which is information indicating a destination for access to said parameter information, thereby said write command is transferred to said protocol chip via said second bus, said bridge circuit, and said first bus, wherein when receiving said specified write command via said bridge circuit from said micro processor, said protocol chip issues a read command for the access destination which is indicated by said access destination information within said specified write command, thereby said read command is transferred to said bridge circuit via said first bus, wherein said bridge circuit has a storage resource, and monitors write commands which are transferred to said protocol chip from said micro processor via itself, and if it is determined, as a result of monitoring, that said write command is a specified write command, pre-fetches said parameter information from said local memory into said storage resource using the access destination information within said write command, and when receiving a read command for said access destination from said protocol chip, transmits said parameter information which has been pre-fetched to said protocol chip via said first bus, without passing said read command through to said micro processor, wherein, in said write command which is issued from said micro processor to said protocol chip, there is included an issue destination address for said write command, and wherein said bridge circuit has a first comparison circuit, and by means of said first comparison circuit, inputs said issue destination address in said write command which passes through said bridge circuit and compares said issue destination address which has been input and a predetermined address, and if a match is obtained, pre-fetches said parameter information from said local memory into said storage resource, using said access destination information within said write command.