Patent ID: 6748579
Filing Date: 2004-06-08
Classification: G06F

Abstract:
A method of fabricating photolithography masks for an integrated circuit, the method comprising:(a) fabricating a set of routing layer masks, which define conductive segments including signal segments, power supply segments and filler segments on various routing layers of the integrated circuit, wherein the filler segments are located in areas unused by the signal segments and the power supply segments; (b) fabricating a first via mask, which defines electrical connections between the conductive segments on at least two of the routing layers, including connections between the filler segments on one of the layers and the power supply segments on another of the layers; (c) changing a signal net on the integrated circuit after fabricating at least one of the routing layer masks and the first via mask; and (d) fabricating a second via mask to replace the first via mask, which decouples a first of the filler segments from a first of the power supply segments and couples the first filler segment into the signal net.