Patent ID: 6763513
Filing Date: 2004-07-13
Classification: G06F

Abstract:
A method for balancing a clock tree design describing a clock tree as having a plurality of branches for distributing at least one clock signal to a plurality of sinks within an integrated circuit layout, wherein the clock tree includes at least one multiplexer, each multiplexer having a plurality of inputs for receiving the at least one clock signal via separate ones of the plurality of branches and having an output linked through a corresponding subtree of the clock tree to a subset of the sinks, the method comprising the steps of:a. selecting a multiplexer of the clock tree, b. altering the clock tree design to substantially balance the selected multiplexer's corresponding subtree; and c. altering the clock tree design so that it represents the selected multiplexer and its substantially balanced corresponding subtree as a set of macros, each macro corresponding to a separate input of the multiplexer and representing an estimated path delay from the corresponding multiplexer input to the subset of sinks linked to the multiplexer output.