Patent ID: 7994009
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A process of forming an integrated circuit, comprising the steps of: forming a layer of field oxide in a surface of said integrated circuit, such that a symmetric transistor area and an asymmetric transistor area are defined at said surface by being free of said field oxide; forming a first gate dielectric layer on the surface of said integrated circuit in said symmetric transistor area; forming a second gate dielectric layer on the surface of said integrated circuit in said asymmetric transistor area; forming a first MOS gate on the first gate dielectric layer, such that said first MOS gate has a first longitudinal axis, and such that said symmetric transistor area includes a first source area adjacent to said first MOS gate and a first drain area adjacent to said first MOS gate opposite said first source area; forming a second MOS gate on the second gate dielectric layer, such that said second MOS gate has a second longitudinal axis perpendicular to said first longitudinal axis, and such that said asymmetric transistor area includes a second source area adjacent to the second MOS gate and a second drain area adjacent to the second MOS gate opposite said second source area; and performing a first implant process comprising a first angled sub-implant wherein said first angled sub-implant is tilted from an axis perpendicular to said surface in a first direction, such that: