Patent ID: 6734738
Filing Date: 2004-05-11
Classification: G04G,H03L

Abstract:
A low power stable oscillator circuit comprising:a first oscillator that outputs a first oscillation signal, a second oscillator that outputs a second oscillation signal at a precise frequency, a frequency divider that performs frequency division for the first oscillation signal at a frequency dividing value and outputs an output signal at a prescribed frequency, a frequency dividing value setting circuit that sets the frequency dividing value of the frequency divider based on the first oscillation signal and the second oscillation signal, and a wake-up circuit that controls the operation of the second oscillator and the frequency dividing value setting circuit such that the second oscillator and the frequency dividing value setting circuit work intermittently; wherein the output frequency of the low power stable oscillator circuit is taken as the output of the frequency divider, the output frequency being set to a frequency of the second oscillator when the second oscillator and the frequency dividing value setting circuit are operative, and maintaining that frequency when the frequency dividing value setting circuit and the second oscillator are inoperative.