Patent ID: 6097435
Filing Date: 2000-08-01
Classification: H04N

Abstract:
An apparatus for processing a plurality of program signals including a first program signal having a first data rate and a second program signal having a second data rate, said apparatus comprising:a rate controller for generating a rate reduction factor based upon said data rates of said first and second program signals;a first channel processor coupled to receive said first program signal, said first program signal including a first audio signal and a first video signal, said first channel processor comprising:a first data path providing a first bit reduction rate;a second data path providing a second bit reduction rate which is greater than said first bit reduction rate; anda channel controller for selectively causing said first video signal to pass through one of said first and second data paths without passing through the other of said first and second data paths in response to said rate reduction factor generated by said rate controller;a second channel processor coupled to receive said second program signal, said second program signal including a second audio signal and a second video signal, said second channel processor comprising:a first data path providing a first bit reduction rate;a second data path providing a second bit reduction rate which is greater than said first bit reduction rate of said first data path of said second channel processor; anda channel controller for selectively causing said second video signal to pass through one of said first and second data paths of said second channel processor without passing through the other of said first and second data paths of said second channel processor in response to said rate reduction factor generated by said rate controller.