Patent ID: 6502179
Filing Date: 2002-12-31
Classification: G06F

Abstract:
A processor for performing calculations based on a plurality of instruction codes, wherein each of the instruction codes includes a higher order bit and lower order bits, the number of lower order bits being an integer multiple of one byte, the processor comprising:a memory for storing the instruction codes, wherein the memory includes a lower order bit storage section, for storing the lower order bits of each of the instruction codes, and a higher order bit storage section, for storing the higher order bit of each of the instruction codes; an instruction code generation circuit connected to the memory, wherein the instruction code generation circuit receives a first address signal including data corresponding to an address of the memory, reads the lower order bits and the higher order bit of the instruction code located at the address corresponding to the first address signal, and generates the instruction code; and an arithmetic unit connected to the instruction code generation circuit to provide the first address signal to the instruction code generation circuit, to receive the instruction code generated by the instruction code generation circuit, and to perform a predetermined calculation.