Patent ID: 6078632
Filing Date: 2000-06-20
Classification: G08C,H04B,H04J

Abstract:
A hardware device dedicated to decommutation, and sorting by time position, the reconstruction and reinterpretation of multiple streams of serial data, from the general form of a received clock and data signal pair, representing data from one of plural receivable synchronous data transmitters each having interleaved analog and digital data bytes, said device comprising the combination of:a serial input data register for each of said serial clock and data byte signals, said serial input data registers being coupled by a two byte input serial data path to a receiver of said streams of serial data;a synchronization word recognizer coupled by a parallel data bus to said serial input data registers output and generating a sync detected output signal in response to synchronization word recognition;digital to analog converter output apparatus controllably coupled to most significant bits portions of said serial input data registers by a data path inclusive of a twos complement data approximation generating apparatus;digital data storage output apparatus controllably coupled to least significant bits portions of said serial input data registers;control means connected to each of said output apparatus and responsive to said sync detected output signal for enabling transmitter input timing-determined updating of each said output apparatus;said control means including memory means inhibiting data updates to said output apparatus between said sync detected output signal and a next ensuing serial data word;said control means also including control gate means enabling update of each said output apparatus at mid clock cycle times following data settlement;said control means also including control gate means precluding update of each said output apparatus with incomplete data byte pairs from said serial input data registers;said control means also including control gate means precluding update of each said output apparatus with synchronization word data from said serial input data registers;said control means also including control gate means terminating update of each said output apparatus from said serial input data registers prior to commencement of a next following clock cycle;said control means also including counting means tracking time position of input data bytes in said serial input data registers and means for resetting said counting means in response to said sync detected output signal;said control means also including counter means for determining completed receipt of said input data signal byte pairs in said serial input data registers;said control means also including counter means for distinguishing between said analog and digital data signal byte pairs and controlling loading of said interleaved analog and digital data bytes into said output apparatus.