Patent ID: 6490700
Filing Date: 2002-12-03
Classification: G01R,G11C

Abstract:
A memory device testing apparatus for testing a packet system memory device, comprising:a pattern generator that generates a selection signal and a pattern signal, said pattern signal comprising a plurality of signal components, said selection signal selecting a signal component and expectation value data; a pin data selector that comprises a plurality of selection elements each corresponding to said signal components of said pattern signal respectively, said pin data selector outputting said signal component selected by said selection signal and generating expectation value data selected by said selection signal; a memory device socket which holds said memory device, writes test data into said memory device, and reads said test data from said memory device according to said signal component outputted from said pin data selector; and a comparator that compares said expectation value data generated by said pin data selector with said test data read out from said memory device.