Patent ID: 8999766
Filing Date: 2015-04-07
Classification: G06F,H01L

Abstract:
1. A method for laying out a circuit design, for use in forming a lithographic mask set for use in fabricating an integrated circuit on a substrate, the method being for use by a computer system having a processor and memory, the method comprising: the computer system identifying a position on the integrated circuit at which a TSV is to be placed; the computer system determining an exclusion zone surrounding the TSV laterally; the computer system laying out a transistor having a diffusion region in the substrate, a gate conductor and a gate dielectric separating the gate conductor from the substrate, the diffusion region being disposed outside the exclusion zone; the computer system laying out a first region in the substrate and at least partially within the exclusion zone, the first region being doped to exhibit a first conductivity type, the substrate in at least a second region adjacent to the first region being doped to exhibit a second conductivity type opposite the first conductivity type; and the computer system laying out an M1 layer conductor interconnecting the TSV, the first region, and a member of the group consisting of the diffusion region and the gate conductor.