Patent ID: 6833285
Filing Date: 2004-12-21
Classification: H01L

Abstract:
A process for forming an interposer element for use as a chip carrier comprising the steps of:providing an insulating layer on at least one surface of a silicon substrate; and processing said insulating layer to produce at least one passive circuit element on or within said insulating layer, said at least one passive circuit element being separated from said silicon substrate by a portion of said insulating layer, said portion of said insulating layer having a thickness such that said at least one passive circuit element is electrically shielded from said silicon substrate, solder bonding at least one integrated circuit chip to said interposer element, by forming a plurality of individual solder ball leads, wherein two or more of said individual solder ball leads use differing types of solder having differing melting points, such that said at least one integrated circuit chip is electrically connected to said at least one passive circuit element; and forming a metallization pattern on or within said insulating layer, said metallization pattern being connected with said at least one passive circuit element.