Patent ID: 6041389
Filing Date: 2000-03-21
Classification: G11C

Abstract:
A memory comprising:an array of addressable memory cells;addressing circuitry for accessing selected ones of said memory cells in response to received location address bits said address circuitry including a row decoder for selecting a row of said memory cells of said array in response to a row address and a column decoder for accessing selected cells along a said selected row in response to a column address;an address buffer for selectively passing said received address bits to said addressing circuitry; anda content addressable memory cell including latching circuitry for storing a select bit associated with the array and an exclusive-NOR gate for comparing a received select bit with the stored select bit associated with said array, said exclusive-NOR gate having an output coupled to an enable line coupled to said address buffer for selectively enabling presentation of said address bits through said address buffer to said addressing circuitry for accessing addressed ones of said memory cells, said content addressable memory cell having a first input for receiving a signal to enable writing said stored select bit into said latching circuitry, and having one or more content inputs for receiving a bit to be stored.