Patent ID: 6798686
Filing Date: 2004-09-28
Classification: G11C

Abstract:
A semiconductor memory device comprising:a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells in a matrix form each constituted of a cell transistor and a ferroelectric capacitor connected in parallel between source and drain terminals of the cell transistor, a plurality of word lines connected to gates of the cell transistors, a plurality of pairs of bit lines, a plurality of block selection transistors each connected between one end of the memory cells connected in series in a corresponding row and a corresponding bit line, a plurality of plate lines each connected to the other end of the memory cells connected in series in the corresponding row, and a plurality of sense amplifier circuits each connected to a corresponding pair of bit lines; and a control circuit which controls the semiconductor memory circuit in an operation time to raise gate potentials of the block selection transistors to be selected from a first potential to a second potential to read cell data from the memory cells of the selected block selection transistors onto the bit lines, thereafter set the bit lines to a high level to write â€œ1â€  data into the memory cells regardless of a logic level of data to be written, thereafter set the gate potentials of the selected block selection transistors to a third potential lower than the second potential and higher than the first potential, set the bit line to a low level with â€œ0â€  data to be written to write â€œ0â€  data into the memory cells, and thereafter to lower the gate potentials of the selected block selection transistors to the first potential.