Patent ID: 8667349
Filing Date: 2014-03-04
Classification: G01R

Abstract:
1. A scan flip-flop circuit comprising: an input stage for providing a data signal to a data node, wherein the input stage comprises first and second stacks of transistors devices coupled to the data node, the first stack receiving a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node; a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module, the scan and clock control logic module controlling the first stack to input the data input signal to the data node during normal operation mode.