Patent ID: 6136693
Filing Date: 2000-10-24
Classification: C23C,H01L

Abstract:
A method of fabrication of integrated circuit interconnection vias on a semiconductor substrate having an insulating layer, said insulating layer having contact openings etched therein, comprising the steps of:providing said semiconductor substrate having an insulating layer containing contact openings etched therein;forming a barrier layer, comprising TiN, WN or TaN onto the surface of the insulating layer and into the contact openings, forming said barrier layer onto the sidewalls and bottom of said contact openings;using a first CMP (Chemical Mechanical Polishing) to remove said barrier layer from the surface of said insulating layer, leaving contact openings lined with said barrier layer;cleaning said semiconductor substrate;forming an activation layer comprising Pd or Pt onto the barrier layer lining said contact openings;depositing copper by electroless plating onto said activation layer as formed onto said barrier layer lining said contact openings;continuing deposition of copper by electroless plating to fill said contact openings and result in an overgrowth of copper above the surface of the insulating layer; andusing a second CMP (Chemical Mechanical Polishing) to remove said overgrowth of copper, thereby producing coplanar surfaces of copper and insulating layer materials.