Patent ID: 8148726
Filing Date: 2012-04-03
Classification: G02F,H01L

Abstract:
1. A display device which includes thin film transistors on a substrate, each thin film transistor comprising: a gate electrode; a gate insulation film which is formed so as to cover the gate electrode; a semiconductor layer which is formed on the gate insulation film in a state where the semiconductor layer straddles the gate electrode; a pair of electrodes which is connected with the semiconductor layer; and an interlayer insulation film which is formed over the semiconductor layer, wherein a plurality of contact holes for connecting the semiconductor layer and the pair of electrodes are formed in the interlayer insulation film, the plurality of contact holes respectively have a region where the contact hole overlaps with the gate electrode as viewed in a plan view and a region where the contact hole does not overlap with the gate electrode as viewed in a plan view, the semiconductor layer includes a first layer, a pair of second layers and a pair of third layers, a portion of the first layer is a channel region of the thin film transistor, the pair of second layers is formed of an impurity layer doped with predetermined impurity ions, the pair of third layers is formed of a low-concentration impurity layer with impurity concentration lower than impurity concentration in the second layers, the second layers respectively have connection portions which are connected with the pair of electrodes respectively via the contact holes, the third layers are respectively formed so as to annularly surround the pair of second layers respectively, a channel-region-side edge portion out of edge portions of the third layer is brought into contact with the first layer as viewed in a plan view, the edge portions of the third layer except for the channel-region-side edge portion are brought into contact with the interlayer insulation film, the second layers respectively have a first region where the second layer overlaps with the gate electrode as viewed in a plan view and a second region where the second layer does not overlap with the gate electrode as viewed in a plan view, and the connection portion is formed in the second region.