Patent ID: 6232867
Filing Date: 2001-05-15
Classification: H01C,Y10T

Abstract:
A method of fabricating a monolithic chip varistor comprising the steps of:preparing a varistor body comprising a plurality of varistor layers comprising a zinc oxide-based ceramic material and at least one pair of internal electrodes opposed to each other with one of the varistor layers therebetween;forming a first layer for each of a pair of external electrodes by applying a metal component and a glass component to respective exterior portions of the varistor body so as to be electrically connected to a respective internal electrode, followed by a first heat treatment;forming a second layer for the external electrode on the first layer by applying a glass component, followed by a second heat treatment;forming a third layer for the external electrode on the second layer by applying a glass component which is different from the glass component used for forming the second layer, followed by a third heat treatment;forming a fourth layer for the external electrode on the third layer by applying a metal component which is different from the metal component used for forming the first layer, followed by a fourth heat treatment under the same heat treatment conditions as those used for the first heat treatment; andforming a fifth layer for the external electrode by forming an electroplating layer comprising a metal having a desired solderability,wherein during the heat treatment for forming the fourth layer, the metal component contained in the fourth layer is diffused into the second layer and the third layer.