Patent ID: 7420868
Filing Date: 2008-09-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array which includes a plurality of subarrays arranged in the form of a matrix, and a plurality of word lines and a plurality of bit lines connected to the subarrays, the subarray comprising a bit line driving transistor which drives the bit line, a sub-bit line connected to the gate of the bit line driving transistor, and a plurality of memory cell transistors which are connected to the sub-bit line and drive the sub-bit line according to signals from the word lines, wherein: the bit line driving transistor has a drain connected to the bit line and a source connected to a first power potential supply line, the memory cell array further includes a plurality of block selection lines connected to the subarrays, and the subarray further has a resetting transistor having a gate connected to the block selection line, a source connected to the first power potential supply line, and a drain connected to the sub-bit line.