Patent ID: 7038966
Filing Date: 2006-05-02
Classification: G11C

Abstract:
1. A data path for coupling data between a memory array and a plurality of data bus terminals, the data path comprising: M*N flip-flops coupled to the memory array to receive respective read data bits from the memory array; an M*N-bit data bus coupled to the M*N flip-flops; a first set of N parallel-to-serial converters coupled to the M*N-bit data bus, each of the parallel-to-serial converters in the first set being operable to receive either M or M/2 parallel data bits from the M*N flip-flops, to convert the M or M/2, respectively, parallel data bits to M or M/2, respectively, serial data bits, and to couple the M or M/2, respectively, serial data bits to a respective one of N data bus terminals; a second set of N parallel-to-serial converters coupled to the M*N-bit data bus, each of the parallel-to-serial converters in the second set being operable to receive M/2 parallel data bits from the flip-flops, to convert the M/2 parallel data bits to M/2 serial data bits, and to couple the M/2 serial data bits to a respective one of N data bus terminals; and a control circuit operable in a first operating mode to cause M*N bits of data from the M*N flip-flops to be coupled through the M*N-bit bus in parallel and to cause M of the parallel data bits to be coupled to each of the N parallel-to-serial converters in the first set, and being operable in a second operating mode to cause M*N bits of data from the M*N flip-flops to be coupled through the M*N-bit bus in parallel and to cause M/2 of the parallel data bits to be coupled to each of the N parallel-to-serial converters in the first set and to each of the N parallel-to-serial converters in the second set.