Patent ID: 6678205
Filing Date: 2004-01-13
Classification: G11C

Abstract:
A synchronous semiconductor device operable in a normal mode of operation and an alternative mode of operation, comprising:a first input terminal for receiving a first asynchronous input signal; a second input terminal for receiving a second asynchronous input signal, said second asynchronous input signal and said first asynchronous signal not asserted concurrently during operation of said device in said normal mode; at least one input buffer for receiving a synchronous input signal; at least one clock terminal for receiving an external clock signal; a delay lock loop circuit, coupled to said clock terminal and responsive to said external clock signal to generate at least one internal clock signal to be applied to said at least one input buffer, said delay lock loop circuit adapted to be activated during said normal mode of operation and to be deactivated during said alternative mode of operation; control circuitry, coupled to said first and second input terminals and to said delay lock loop circuit, said control circuitry being responsive to concurrent assertion of said first and second asynchronous input signals to deactivate said delay lock loop circuit, thereby placing said device into said alternative mode of operation.