Patent ID: 7571216
Filing Date: 2009-08-04
Classification: G06F

Abstract:
1. An interface for a network device and a CPU, with the interface including a shared memory comprising: a Rx buffer pool, maintained in the shared memory and which is write-only by the CPU and read-only by the device, comprising a plurality of buffer pool entries, each entry holding an address and length value of a scatter-gather buffer; a transmit FIFO pool which is write-only by the CPU and read-only by the device, with each FIFO pool entry holding a buffer length, start field, end field, and buffer address field; a status ring, maintained in shared memory, separate from the Rx buffer pool and transmit FIFO pool, and which is read-only by the CPU and write-only by the device, with each status ring entry holding status information written by the device and a toggle bit which holds a value which is changed by the device each time the device accesses the status ring; and a private memory, accessible only by the CPU, with the private memory holding a shadow copy of the scatter/gather buffers, in software-friendly form, included in the received buffer pool and a shadow count of the number of available of Tx FIFO entries.