Patent ID: 6166590
Filing Date: 2000-12-26
Classification: G05F

Abstract:
A current mirror circuit comprising two reference transistors (first and second), three mirror transistors (first, second, and third), three buffer transistors (first, second, and third,) two amplifier circuits (first and second), and two power supply lines (high voltage and low voltage), wherein:(a.) said reference transistors are transistors that have the drain thereof connected to gate thereof and that has the source thereof connected to one of the said two power supply lines,(b.) said mirror transistors are transistors that has the gate thereof connected to the drain of one said reference transistors, and that has the source thereof connected to the same power supply line as the source of the reference transistor to which the gate of said mirror transistor is connected to,(c.) said buffer transistors are transistors that have either the source or the drain thereof connected to the drain of one of said mirror transistors and to the gate of another transistor which provides an input of an amplifier which has the output thereof connected to the gate of said buffer transistor, and where the said amplifier is either of said first or second amplifiers,(d.) the gates of said first and second mirror transistors are connected to the gate of said first reference transistor,(e.) a load of said first buffer transistor is said second reference transistor,(f.) a load of said second buffer transistor is the drain of a load transistor that has the source thereof connected to the same power supply line as said second reference transistor,(g.) said first amplifier is connected between the drain of said first mirror transistor and the gate of said first buffer transistor,(h.) the gate of said third mirror transistor is connected to the gate of said second reference transistor,(i.) the gate of said load transistor is connected to the drain of said third mirror transistor and to either the drain or the source of said third buffer transistor,(j.) the gate of said second buffer transistor is connected to the gate of said first buffer transistor, and(k.) said second amplifier is connected between the drain of said second mirror transistor and the gate of said third buffer transistor,(l.) whereby when said first reference transistor receives a constant input current I.sub.in, said third buffer transistor generates a constant output current I.sub.out on a variable load.