Patent ID: 6265744
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate of a first conductivity type serving as a drain region of a MOS transistor;a base region of the MOS transistor formed in a surface area of the semiconductor substrate and consituted of a semiconductor layer of a second conductivity type;a source region of the first conductivity type and a gate leading region of the first conductivity type both formed in a surface area of the base region seperately from each other;trench sections formed in the source region and the gate leading region to such a depth as to penetrate the base region;a gate insulation film formed on inner walls of the trench sections and a surface of the semiconductor substrate;polysilicon buried into the trench sections and thermally treated;an interlayer insulation film deposited on the semiconductor substrate and located at least in the gate leading region; anda gate electrode which is connected to both the gate leading region and the polysilicon of the trench sections formed in the gate leading region through a gate electrode contact hole, said gate electrode contact hole being formed in the interlayer insulation film and the gate insulation film formed thereunder.