Patent ID: 6807082
Filing Date: 2004-10-19
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a substrate; a plurality of memory cell transistors formed on said substrate and arranged in arrays in a first direction and in a second direction different from the first direction, and each of the memory cell transistor being provided with a first and a second diffusion region; a ferroelectric capacitor connected to said first diffusion region in each of said memory cell transistors via a first contact plug; a plurality of bit lines formed above said ferroelectric capacitor, and connected to said second diffusion regions of said memory cell transistors arranged in said first direction via a second contact plug, each bit line being extended in said first direction and arranged next to each other in said second direction; a plurality of word lines formed between said first and second contact plugs of each memory cell transistor, each word line being extended in said second direction and arranged next to each other in said first direction; and a plurality of plate lines each being extended in said second direction and arranged next to each other in said first direction, the plate lines being connected to upper electrodes of a group of the ferroelectric capacitors arranged in said second direction through a plurality of contact holes; whereineach of said word lines is bent away from an opposing other word line in areas near said second contact plug, and toward said other word line in other areas; and said plurality of contact holes is displaced alternately with respect to a longitudinal centerline of said plate line.