Patent ID: 7190626
Filing Date: 2007-03-13
Classification: G11C

Abstract:
1. A memory system comprising: one or more memory cells; at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to the one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal; at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell; and at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal by a predetermined time margin so that the voltage level of the bit-line is discharged to reach a high or low read margin for allowing an accelerated reading of the data.