Patent ID: 7064020
Filing Date: 2006-06-20
Classification: G02F,H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising the steps of: forming a semiconductor layer over a substrate having an insulating surface; forming a gate insulating film in contact with said semiconductor layer; forming a first conductive layer; forming a second conductive layer on the first conductive layer; etching said second conductive layer to form a second layer of a gate electrode; doping a selected region of said semiconductor layer with an impurity element of one conductivity type; forming a third conductive layer on an upper surface of said first conductive layer and an upper surface of said second layer of said gate electrode; etching said third conductive layer and said first conductive layer, thereby forming a third layer of said gate electrode and a first layer of said gate electrode; and doping a selected region of said semiconductor layer with an impurity element of said one conductivity type, wherein both edges of said first layer of said gate electrode are coplanar to those of said third layer of said gate electrode.