Patent ID: 7189435
Filing Date: 2007-03-13
Classification: B82Y,G03F,H01J,H01L

Abstract:
1. A method of interfacing an electrical connection with a multilayer nanostructure, the method comprising: preparing a diblock copolymer layer on a substrate surface, wherein the diblock copolymer layer comprises a matrix component and a core component, and at least a portion of the substrate surface is conductive or semiconductive; depositing a metal layer on at least a portion of the diblock copolymer layer; orienting the core component of the diblock copolymer layer to form a plurality of nanoscopic cylinders parallel to each other within the diblock copolymer layer and oriented with respect to the substrate surface; removing at least a portion of the oriented core component from the diblock copolymer layer to form a patterned array of nanopores in the diblock copolymer layer, wherein the diblock copolymer layer comprises a first region comprising nanopores and a second region comprising no nanopores to form the patterned array of nanopores; and at least partially filling at least some of the nanopores with a material.