Patent ID: 8787515
Filing Date: 2014-07-22
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit, comprising: a phase detector, comparing a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal; a first integration module, coupled to the phase detector, and performing an integration process on the adjusting signal to output a first integration phase error; an operation unit, coupled to the first integration module, and operating the first integration phase error and the adjusting signal to obtain an operation value; a second integration module, coupled to the operation unit, and performing an integration process on the operation value to output a phase control signal; a third integration module, coupled to the first integration module, and performing an integration process on the first integration phase error to output a frequency control signal; an oscillation circuit, coupled to the third integration module, and generating at least one reference clock according to the frequency control signal; and a phase converter, coupled to the oscillation circuit, the second integration module and the phase detector, and outputting the data-recovery clock to the phase detector according to the phase control signal and the reference clock.