Patent ID: 7650584
Filing Date: 2010-01-19
Classification: G06F,G11C,H01L

Abstract:
1. An application specific integrated circuit comprising: a first wire which is extended in a first direction and a second wire which is extended in a parallel direction to this first wire and both of which are placed on a first wire layer; and a third wire which is placed on a second wire layer above said first wire layer and is extended above said first wire and above said second wire in a second direction which intersects to said first direction and passing through a first via-hole is connected to said first wire, and a fourth wire which is separated from said third wire and is extended in a parallel direction above said first wire and above said second wire and a fifth wire which is separated from both said third wire and said fourth wire and is extended in a parallel direction in a smallest space and passing through a second via-hole is connected to said second wire, wherein one end of said fifth wire is extended to the center between said second wire and said first wire from above said second wire; a sixth wire which is extended in a said first direction and placed on said first wire layer and a seventh wire which is extended in a parallel direction to this sixth wire; an eighth wire which is placed on said second wire layer and is extended above said sixth wire and above said seventh wire and passing through a third via-hole is connected to said sixth wire, and a ninth wire which is separated from said eighth wire and is extended in a parallel direction in a space more than a smallest space above said sixth wire and above said seventh wire; and a contact overlay margin which is placed on the said ninth wire side of said eight wire in the proximity of said third via-hole.