Patent ID: 7375580
Filing Date: 2008-05-20
Classification: G06F,H03K

Abstract:
1. A semiconductor integrated circuit comprising: a circuit block comprising a MOS transistor having a bias input terminal, a source, and a substrate, said MOS transistor being operable to receive a bias voltage applied through said bias input terminal to at least one of said source and said substrate; a setting unit operable to set applying timing, including a time at which the bias voltage is applied to said MOS transistor, and operable to set releasing timing, including a time at which the bias voltage is released from said MOS transistor; and a bias voltage-applying unit operable to apply the bias voltage to said MOS transistor through said bias input terminal according to the applying timing and the releasing timing, wherein said setting unit is operable to set the releasing timing to include a time at which the bias voltage is released prior to, by a predetermined time period, an activation time included in activation timing, and wherein an operation-requesting signal for controlling an operation state of said circuit block is transmitted to said circuit block by said setting unit at an activation time included in the activation timing.