Patent ID: 6515357
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A semiconductor package comprising:a complete interposer, in which a wiring layer having a prescribed wiring pattern is formed on an insulating base material and an adhesive layer having holes is formed on said wiring layer, and a semiconductor chip, in which bumps are arranged on electrodes are adhered together such that said adhesive layer confronts the electrode formation surface of said semiconductor chip; said bumps are inserted into said holes of said adhesive layer and electrodes of said semiconductor chip and said wiring layer are electrically connected by way of said bumps according to the flip-chip method; and external connectors are provided on the surface of said wiring layer that is opposite from the surface that is adhered to said semiconductor chip; wherein said insulating base material extends completely beneath at least one of said adhesive layer holes; and wherein said wiring layer is supported by said insulating base material at least within an area in which electrodes of said semiconductor chip are connected.