Patent ID: 8951836
Filing Date: 2015-02-10
Classification: B81B,H01L

Abstract:
1. A method for forming a chip package, comprising: providing a substrate having an upper surface and a lower surface, wherein the substrate comprises: a plurality of conducting pads located below the lower surface of the substrate; and a dielectric layer located between the conducting pads; removing a portion of the substrate from the upper surface of the substrate to form a hole extending towards the conducting pads; after the hole is formed, removing a portion of the substrate from the upper surface of the substrate to form a trench extending towards the lower surface of the substrate, wherein the trench connects with the hole; forming an insulating layer on a sidewall of the trench and a sidewall and a bottom of the hole; removing a portion of the insulating layer and a portion of the dielectric layer to expose a portion of the conducting pads; and forming a conducting layer on the sidewall of the trench and the sidewall and the bottom of the hole, wherein the conducting layer electrically contacts with the conducting pads.