Patent ID: 8426960
Filing Date: 2013-04-23
Classification: H01L

Abstract:
1. A method for making back-to-front electrical connections in a wafer level chip scale packaging process, comprising: a) mounting a wafer containing a plurality of semiconductor chips on a package substrate, wherein each semiconductor chip in the plurality includes one or more electrodes on an exposed back side; b) removing scribe lines between two or more adjacent chips on the wafer to form relatively wide gaps therebetween; c) applying an uncovered layer of conductive material to the back side of the semiconductor chips and in the gaps coating over the exposed back side and side wall surfaces of each semiconductor chip forming an outmost surface, wherein side layers of conductive material further extend to the edges of a front side of each semiconductor chip; and d) cutting through the conductive material in the gaps between two or more of the chips leaving conductive material on the back side and on side walls of the two or more chips,