Patent ID: 6514812
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A manufacturing method of a semiconductor device, in which at least a conductive layer is formed on an impurity diffusion layer in which a source and a drain of at least one transistor are formed, and a lower electrode of a memory cell capacitor part of a stacked capacitor type memory cell composed of one transistor and one capacitor is formed by removing a part of said conductive layer, comprising the steps of:forming a first insulation film on said conductive layer; applying a first etching for removing a part of said first insulation film and a part of said conductive layer to its middle part, for forming spaces of different sizes; forming a second insulation film on the whole surface formed by mentioned above steps so that a small size space of said spaces is filled with said second insulation film; applying an etching back for forming an exposed part of said conductive layer at a large size space of said spaces; and applying a second etching for removing said conductive layer at said exposed part of said conductive layer.