Patent ID: 6269440
Filing Date: 2001-07-31
Classification: G06F

Abstract:
A processor for processing vector data, said processor comprising:a plurality of functional units;a register by-pass network connected to each of said plurality of functional units, said register by-pass network allowing a result produced by one of said plurality of functional units to be used as an operand by said one of said plurality of functional units or another of said plurality of functional units in an immediate succeeding cycle;a register file connected to said register by-pass network, said register file adapted to store a result produced by each of said plurality of functional units;an instruction decode and dispatch unit connected to said register file and each of said plurality of functional units; anda vector zero overhead loop control circuit connected to said instruction decode and dispatch unit to receive instructions from said instruction decode and dispatch unit, said vector zero overhead loop control circuit comprising:a plurality of instruction sequencers, one of said plurality of instruction sequencers being adapted to start iteration N+1 of a program loop before iteration N of said program loop is completed by another of said plurality of instruction sequencers; andan iteration counter connected to said plurality of instruction sequencers, said iteration counter being adapted to store a value representing a number of iterations that have been processed in whole or in part by said plurality of instruction sequencers.