Patent ID: 6331948
Filing Date: 2001-12-18
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device for making efficient error correction in a method of adjusting the distribution of threshold of cells after erasing, comprising:an error correction code generating circuit for generating an error correction code necessary for carrying out error correction corresponding to each information data to be inputted, according to check bit generation matrix, said check bit generation matrix being so formed that the factors of ""1"" in respective rows satisfy the quantity absolutely necessary for generating an error correction code of a necessary bit length and the quantity of the factors of ""1"" is a odd number;a holding unit in which said information data and error correction code generated by said check bit generating circuit are written and the written information data and the error correction code are held;a write circuit for writing said information data and said error correction code into said holding unit;an erasing circuit for erasing said information data and said error correction code held by said holding unit;a readout circuit for reading out said information data and said error correction code held by said holding unit;a detection circuit for detecting whether or not there is any error in information data read out by said readout circuit based on said error correction code read out by said readout circuit; anda correction circuit for if there is any error in a detection result of said detection circuit, correcting information data having the error.