Patent ID: 7904703
Filing Date: 2011-03-08
Classification: G06F

Abstract:
1. An apparatus comprising: a scheduler configured to determine a bandwidth request mode of a plurality of instruction execution threads, wherein for each of the plurality of instruction execution threads: the multithread processing core operatively coupled to the scheduler, the multithread processing core configured to execute instructions of the plurality of instruction execution threads according to allocation of the execution cycles of the instruction execution period of the multithread processing core provided by the scheduler; and a plurality of registers, each register (i) associated with a corresponding instruction execution thread and (ii) configured to store the corresponding bandwidth request mode, wherein the plurality of instruction execution threads includes at least (i) a first instruction execution thread associated with a first register of the plurality of registers, and (ii) a second instruction execution thread associated with a second register of the plurality of registers, wherein the first instruction execution thread is configured to access the first register and the second register to respectively modify (i) the bandwidth request mode of the first instruction execution thread and (ii) the bandwidth request mode of the second instruction execution thread, and wherein the second instruction execution thread is prohibited from accessing the first register to modify the bandwidth request mode of the first instruction execution thread.