Patent ID: 7323409
Filing Date: 2008-01-29
Classification: H01L

Abstract:
1. A process for fabricating a semiconductor integrated circuit device, comprising a. providing a semiconductor substrate having a top surface and a bottom surface, b. forming a first dielectric layer on the top surface of the semiconductor substrate, c. forming a metal stack on the surface of the first dielectric layer, the metal stack including d. forming a second dielectric layer overlying the metal stack and a portion of the first dielectric layer, the second dielectric layer having a top surface, e. forming a via region in the second dielectric layer having a wall region and a bottom region, the bottom region being in contact with the second intermetallic compound layer, the via region being free of dielectric material, and f. forming a seed layer overlying at least a portion of the wall region and the bottom region, the thickness of the seed layer being between 40 and 100 angstroms.