Patent ID: 9082962
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A method for manufacturing a memory device, comprising: depositing a second insulating layer on a bottom metal and on a first insulating layer; patterning the second insulating layer to expose the bottom metal; depositing a bottom electrode material on the bottom metal and on the second insulating layer after patterning the second insulating layer; planarizing the bottom electrode material to form a bottom electrode having a top surface coplanar with a top surface of the second insulating layer; depositing a material stack comprising magnetic tunnel junction layers over the bottom electrode; patterning the material stack on the bottom electrode, the material stack being smaller than the bottom electrode; depositing a third insulating layer on the bottom electrode and on the second insulating layer, the third insulating layer contacting the bottom electrode and the second insulating layer, the third insulating layer surrounding and abutting the material stack; depositing a top electrode material on the material stack and on the third insulating layer; patterning the top electrode material to form a top electrode, the top electrode abutting the material stack and abutting the third insulating layer; and depositing a fourth insulating layer on the second insulating layer, the fourth insulating layer surrounding and contacting the third insulating layer and contacting both the top electrode and third insulating layer.