Patent ID: 6043675
Filing Date: 2000-03-28
Classification: G06F,H03K,H03M

Abstract:
A logic circuit comprising:a plurality of input terminals, to which binary input is provided;a plurality of input capacitors having first electrode respectively connected to one of said plurality of input terminals and second electrode connected in common, said input capacitors having almost the same capacitance;a fixed capacitor having a first electrode which is fixed at level H or level L and a second electrode which is connected to said second electrodes connected in common, said fixed capacitor having almost the same capacitance as the plurality of input capacitors; andan inverter circuit, for receiving a voltage from the second electrode connected in common and having a threshold value so that the inverter circuit is inverted when a voltage corresponding to logic 1 is applied to a predetermined number of input terminals of said plurality of input terminals, and generating a binary output.