Patent ID: 8116154
Filing Date: 2012-02-14
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of memory cell arrays, each of which includes a plurality of memory cells and a write amplifier that performs a data write operation upon a selected one of the memory cells in response to an active state of a write signal; and a write control circuit that supplies the write signal in common to the memory cell arrays and includes a plurality of flags provided respectively for the memory cell arrays, each of the flags being brought into a set state when an associated one of the memory cell arrays is subject to the data write operation, the write control circuit bringing the write signal from the active state to an inactive state in response to a new data write request which is issued for a first one of the memory cell arrays during the data write operation being performed upon a second one of the memory cell arrays, and then bringing the write signal from the inactive level to the active level again to perform the data write operation upon the first and second ones of the memory cell arrays in response to the new data write request and to the set state of one of the flags which corresponds to the second one of the memory cell arrays.