Patent ID: 6128723
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A computer system comprising a superscalar microprocessor for executing instructions obtained from an instruction store to process data, said superscalar microprocessor comprising:a fetch circuit to fetch a plurality of instructions from said instruction store, the plurality of instructions being in program order;a first in first out (FIFO) buffer to buffer said plurality of instructions from said fetch circuit;a dispatch circuit to concurrently decode and dispatch more than one of said plurality of instructions buffered by said FIFO buffer; andan execution unit comprising:a plurality of functional units, each of said plurality of functional units executing one of said plurality of instructions dispatched by said dispatch circuit out of the program order, anda register file comprising temporary registers to temporarily store out-of-order execution results from said plurality of functional units and a register array to store results from said temporary registers,a plurality of data routing paths, and whereinsaid register file communicates with said plurality of functional units via said plurality of data routing paths to supply data to more than one of said functional units and thereby enabling concurrent execution of more than one of said plurality instructions by said plurality of functional units.