Patent ID: 8250304
Filing Date: 2012-08-21
Classification: G06F

Abstract:
1. Memory device comprising: a cache memory (CACHE) with a predetermined amount of cache sets (CS), each cache set comprising a predetermined amount of cache lines (CL), each cache line (CL) configured to indicate a cache data injection into the particular cache line triggered by a bus-actor (IO, PU); more than one control bits (CB) associated with a particular cache line; and at least one injection-bit (IB) associated with a particular cache line, wherein the memory device is operable to store supplemental information different from the current state of the data of the particular cache line (CL) in the more than one control bit (CB) while the at least one injection-bit (IB) is set, and otherwise to store the current state of the cache line data in the more than one control bit (CB); and the memory device is configured to set the at least one injection-bit (IB) if data is pushed from a bus-actor into the particular cache line.