Patent ID: 8754507
Filing Date: 2014-06-17
Classification: H01L

Abstract:
1. A method for vertically integrating plural semiconductor wafers, each semiconductor wafer including one or more integrated circuits, one or more through vias and a metal layer electrically connecting the integrated circuits with vias fabricated thereon comprising: aligning at least first and second silicon wafers such that a center of each of the one or more through vias of the first wafer aligns with a center of each of corresponding through vias in the second wafer; bonding at least the first and second silicon wafers to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of via centers of at least the first and second wafers; forming a metal seed layer on at least a portion of each of the one or more stack vias; electroplating the stack via using the metal seed layer to form a continuous and homogeneous metallization path through the three-dimensional wafer stack; and forming individual three-dimensional semiconductor elements from the three-dimensional wafer stack.