Patent ID: 7271639
Filing Date: 2007-09-18
Classification: H03K

Abstract:
1. A voltage level converter circuit comprising: a first transistor of a first polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals being connected to a supply terminal having a first power source voltage, the other of the source and drain terminals being connected to a signal output node, and the gate terminal being supplied with one input signal of differential signals which perform level conversion; a second transistor of the first polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals being connected to the supply terminal having the first power source voltage, and the gate terminal being supplied with the other input signal of the differential signals which perform level conversion; a third transistor of a second polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals and the gate terminal being connected to the signal output node; a fourth transistor of the second polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals and the gate terminal being connected to the other of the source and drain terminals of the second transistor; a fifth transistor of the second polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals being connected to a supply terminal having a second power source voltage, the other of the source and drain terminals being connected to the other of the source and drain terminals of the third transistor, and the gate terminal being connected to the gate terminal of the fourth transistor; a sixth transistor of the second polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals being connected to the supply terminal having the second power source voltage, the other of the source and drain terminals being connected to the other of the source and drain terminals of the fourth transistor, and the gate terminal being connected to the gate terminal of the third transistor; a seventh transistor of the second polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals being connected to the supply terminal having the second power source voltage, the other of the source and drain terminals being bonded to the signal output node, and the gate terminal being connected to the gate terminal of the fifth transistor; an eighth transistor of the second polarity which has source and drain terminals and a gate terminal, one of the source and drain terminals being connected to the supply terminal having the second power source voltage, the other of the source and drain terminals being bonded with the other of the source and drain terminals of the second transistor, and the gate terminal being connected to the gate terminal of the sixth transistor.