Patent ID: 6674134
Filing Date: 2004-01-06
Classification: H01L

Abstract:
An integrated circuit comprising:a semiconductor substrate or wafer having a plurality of active device regions located in raised portions of said substrate or wafer, each of said active device regions being electrically isolated from each other by shallow trench isolation regions, and said plurality of active device regions each having opposing edges abutting its corresponding shallow trench isolation region; selected ones of said active device regions having a preselected first channel width and a first gate oxide formed thereon; and selected other ones of said active device regions having a preselected second channel width and a second gate oxide formed thereon, wherein said first channel width is wider than said second channel width and said first gate oxide over said preselected first channel width has a thickness of from about 2.5 to about 4 nm and said second gate oxide formed over said preselected second channel width has a thickness of from about 5 to about 14 nm.