Patent ID: 6148356
Filing Date: 2000-11-14
Classification: G06F

Abstract:
A computer system comprising:a host processor coupled to a host bus;a bridge controller coupled to the host bus and including a plurality of ports, at least two of said bridge controller ports each being configurable in either an independent mode in which each port operates as an independent bus interface, or a combined mode in which two or more bridge controller ports are combined to create a single bus interface having a greater bandwidth than one bus interface in independent mode;a bus bridge coupled to at least one of said bridge controller ports via one or more first buses, the bus bridge connected to one or more second buses; and wherein said bus bridge is configurable in either an independent mode in which each said second bus operates independently or in a combined mode in which two or more second buses are combined to create a single bus having a greater bandwidth than one second bus operating in independent mode;the bus bridge comprising:a first set of data queues for routing data between one of the first buses and one of the second buses, and a second set of data queues for routing data between another of the first buses and another of the second buses;a first controller for controlling operation of the first set of data queues; anda second controller for controlling operation of the second set of data queues; andwherein one of the first and second controllers is disabled and a remaining one of the first and second controllers controls both the first and second sets of data queues when said bus bridge is configured in the combined mode.