Patent ID: 7582903
Filing Date: 2009-09-01
Classification: G02F

Abstract:
1. A thin film transistor array panel comprising: an insulating substrate; a gate wire from a plurality of gate wires formed on the insulating substrate, the gate wire including a plurality of gate line portions and a gate connection connecting the gate line portions; a data wire from a plurality data wires insulated from the gate wires and intersecting the gate wires, the data wire comprising a plurality of data line portions and a data connection connecting the data portions; a gate insulating layer insulating the gate wire and the data wire, a portion of the gate insulating layer being disposed between the plurality of gate line portions and the gate connection; a thin film transistor including a gate electrode of the gate wire and a source electrode connected to the data wire; and a pixel electrode connected to a drain electrode of the thin film transistor, wherein the gate electrode, the gate line portions and the data connection are formed from a same first layer; and the gate connection, the source electrode, the drain electrode and the data line portions are formed from a same second layer; wherein at least a portion of the gate insulating layer is formed on the first layer; and wherein the gate connection is formed between two of the plurality of data wires; and the data connection is formed between two of the plurality of gate wires.