Patent ID: 6779171
Filing Date: 2004-08-17
Classification: G03F

Abstract:
An electronic system, comprising:a processor; and at least one circuit module, wherein the at least one circuit module comprises: a support; a plurality of leads extending from the support and coupled to the processor; and at least one semiconductor die contained on the support and coupled to the plurality of leads, wherein the at least one semiconductor die comprises an integrated circuit, further wherein the integrated circuit is produced by a process comprising the use of a mask, still further wherein the mask is produced by a method comprising: determining overlay error variation across a field of the mask; defining at least two zones within the field of the mask, wherein each zone is a continuous portion of the field containing substantially similar overlay error values, and wherein each zone has a nominal overlay error value; defining a correction for each of the at least two zones, wherein the correction for each zone is approximately the nominal overlay error value for that zone; mapping each of a plurality of features to one of the at least two zones; and modifying coordinates of each of the plurality of features in response to the correction for the zone in which each feature is mapped.