Patent ID: 8098533
Filing Date: 2012-01-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of static memory cells arranged in rows and columns; a plurality of bit line pairs arranged corresponding to the respective memory cell columns, each connected to the memory cells in a corresponding column; a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row, wherein each memory cell from the plurality of static memory cells includes: a plurality of word line drivers, arranged corresponding to said word lines, each for driving a corresponding word line to a selected state when the corresponding word line is addressed; a plurality of driver precharge circuits arranged corresponding to respective groups each including a predetermined number of the word lines of said plurality of word lines, each for supplying a voltage at a first voltage level to the word line drivers in a corresponding word line group when the corresponding word line group is selected; and a plurality of level shift circuits arranged corresponding to the respective driver precharge circuits, each for shifting the voltage at the first voltage level supplied from a corresponding driver precharge circuit to a second voltage level lower than the first voltage level, each of the plurality of word line drivers supplying the voltage at the second voltage level to the corresponding word line when the corresponding word line is addressed and supplying a voltage at a third voltage level lower than the second voltage level to the corresponding word line when the corresponding word line is not addressed, wherein each of the level shift circuits includes a transistor coupled between the respective driver precharge circuits and a ground node.