Patent ID: 7263585
Filing Date: 2007-08-28
Classification: G06F

Abstract:
1. An apparatus in a pipeline microprocessor, for ensuring coherency of instructions within stages of the pipeline microprocessor, the apparatus comprising: instruction cache management logic, configured to receive an address corresponding to a next instruction to be fetched, and configured to detect that a part of a memory page corresponding to said next instruction to be fetched cannot be freely accessed without checking for coherency of the instructions within said part of said memory page and, upon detection, configured to provide said address, wherein said instruction cache management logic evaluates an instruction translation lookaside buffer (ITLB) entry corresponding to said address to detect that said part cannot be freely accessed; and synchronization logic, configured to receive said address from said instruction cache management logic, and configured to direct data cache management logic to check for coherency of the instructions within said part of said memory page, and, if the instructions are not coherent within said part of said memory page, said synchronization logic is configured to direct the pipeline microprocessor to stall a fetch of said next instruction to be fetched until the stages of the pipeline microprocessor have executed all preceding instructions, wherein said data cache management logic evaluates a data translation lookaside buffer (DTLB) entry corresponding to said address to detect that the instructions are not coherent within said part of said memory page; wherein if said instruction cache management logic detects that said part cannot be freely accessed, regardless of whether said instructions are coherent or not, said DTLB entry contents are copied into said ITLB entry by said synchronization logic so that an address translation lookup sequence is avoided.