Patent ID: 6510098
Filing Date: 2003-01-21
Classification: G11C

Abstract:
A memory system, comprising:a first array of memory cells having a first plurality of rows and a first plurality of columns, wherein a first one of the first plurality of rows corresponds to a first predetermined wordline and a first one of the first plurality of columns corresponds to a first predetermined bit line; a second array of memory cells having a second plurality of rows and a second plurality of columns, wherein a first one of the second plurality of rows corresponds to a second predetermined wordline and a first one of the second plurality of columns corresponds to a second predetermined bit line; first control circuitry for receiving a first plurality of address bits and a first plurality of control signals for independently accessing said first array; second control circuitry for receiving a second plurality of address bits and a second plurality of control signals for independently accessing said second array; a first column decoder coupled to the first bit line of the first array to selectively access the first array of memory cells; a second column decoder coupled to the second bit line of the second array to selectively access the second array of memory cells; a transfer gate having a first terminal coupled to the first predetermined bit line, a second terminal coupled to the second predetermined bit line, and a third terminal coupled to a source of the transfer control signal, the transfer gate selectively transferring a first data accessed by the first column decoder to the second column decoder and selectively transferring a second data accessed by the second column decoder to the first column decoder in response to a logic state of the transfer control signal.