Patent ID: 8648444
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A semiconductor wafer having a multi-layer wiring structure, said wafer comprising: a plurality of chip die areas arranged on the wafer in an array, wherein each of said plurality of chip die areas having a structure comprising: scribe line areas between the chip die areas, wherein the first and second set of wiring conductor metal features do not extend into the scribe line areas and the scribe line areas comprise: the first dielectric material and the second dielectric material in the corner region during wafer dicing operation; and a conductive structure of a seal ring located in a perimeter of the chip die area, the conductive structure of the seal ring extending through the top-level passivation layer to connect to the second set of one or more wiring layers, the conductive structure of the seal ring having a tops surface that is at least partially planar with a top surface of at least one of the plurality of metal film structures.