Patent ID: 7973864
Filing Date: 2011-07-05
Classification: G02F

Abstract:
1. A liquid crystal display, comprising: a substrate; a first gate line, a second gate line, and a third gate line formed on the substrate adjacent to each other; a first data line and a second data line adjacent to each other and insulated from and crossing the first gate line, the second gate line, and the third gate line; a storage electrode line insulated from and crossing the first gate line, the second gate line, and the third gate line; a first thin film transistor comprising a control terminal connected to the first gate line and an input terminal connected to the first data line; a second thin film transistor comprising a control terminal connected to the first gate line and an input terminal connected to the first data line; a first sub-pixel electrode connected to the output terminal of the first thin film transistor; a second sub-pixel electrode connected to the output terminal of the second thin film transistor; a third thin film transistor comprising a control terminal connected to the second gate line and an input terminal connected to the first sub-pixel electrode; a first capacitive conductor connected to the output terminal of the third thin film transistor, the first capacitive conductor being formed from the same layer as the first sub-pixel electrode and the second sub-pixel electrode and overlapping a portion of the storage electrode line to form a first voltage reducing capacitor; a first buffer electrode connected to the output terminal of the third thin film transistor and overlapping the portion of the second sub-pixel electrode to form a first voltage increasing capacitor; a fourth thin film transistor comprising a control terminal connected to the second gate line and an input terminal connected to the second data line; a fifth thin film transistor comprising a control terminal connected to the second gate line and an input terminal connected to the second data line; a third sub-pixel electrode connected to the output terminal of the fourth thin film transistor; a fourth sub-pixel electrode connected to the output terminal of the fifth thin film transistor; a sixth thin film transistor comprising a control terminal connected to the third gate line and an input terminal connected to the third sub-pixel electrode; a second capacitive conductor connected to the output terminal of the sixth thin film transistor, the second capacitive conductor being formed from the same layer as the third sub-pixel electrode and the fourth sub-pixel electrode and overlapping a portion of the storage electrode line to form a second voltage reducing capacitor; and a second buffer electrode connected to the output terminal of the sixth thin film transistor and overlapping a portion of the fourth sub-pixel electrode to form a second voltage increasing capacitor, wherein the storage electrode line includes a first portion disposed at equal distances from the first data line and the second data line, a second portion connected to the first portion and detouring around the right side of the third thin film transistor, and a third portion connected to the first portion and detouring around the left side of the sixth thin film transistor, and wherein an interval between the first data line and the second data line is wider than an interval between the first gate line and the second gate line.