Patent ID: 9208858
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A static random access memory (SRAM), comprising: a first port word line; a second port word line; a first port bit line and a first port complementary bit line; a second port bit line and a second port complementary bit line; a memory cell having a data node coupled to the first and second port bit lines and a complementary data node coupled to the first and second port complementary bit lines, wherein the first and second port word lines control access to the memory cell; and a first circuit configured to couple the second port bit line to a high voltage supply node during a write logic high operation to the data node through the first port bit line and couple the second port complementary bit line to the high voltage supply node during a write logic high operation to the complementary data node through the first port complementary bit line.