Patent ID: 6642600
Filing Date: 2003-11-04
Classification: H01L

Abstract:
An insulated gate semiconductor device which comprises an MOS transistor structure, comprising:a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction; a base layer of a second conductivity type formed from a cell region in said first main surface and a region in said first main surface which is defined by one end which is a boundary between said cell region and a terminal region adjacent to said cell region and the other end away from said boundary towards said terminal region by a first distance along a first direction, towards an inside of said semiconductor substrate along said third direction; a first trench formed from said cell region in said first main surface, through said base layer, up to said inside of said semiconductor substrate along said third direction; a first gate insulating film formed entirely on a bottom surface and side surfaces of said first trench; and a first main electrode formed on said second main surface, wherein said first direction is parallel to said first main surface and orthogonal to said third direction, a first depth from said first main surface to a bottom surface of said base layer is smaller than a second depth from said first main surface to said bottom surface of said first trench, said first trench has a plurality of first portions and a plurality of second portions, said plurality of first portions are arranged along a second direction orthogonal to said first direction and said third direction, each of said plurality of first portions has one end portion located on said boundary between said cell region and said terminal region and extends towards said one end portion along said first direction, and each of said plurality of second portions is located between adjacent first portions out of said plurality of first portions and extends along said second direction to connect said adjacent first portions to each other, said insulated gate semiconductor device further comprising: a plurality of second main electrode regions of said first conductivity type, each of which is formed from a region in said cell region of said first main surface which is surrounded by said adjacent first portions and adjacent second portions out of said plurality of second portions corresponding to said adjacent first portions towards an inside of said base layer along upper portions of side surfaces of said adjacent first portions and upper portions of side surfaces of said adjacent second portions; a first gate control electrode so formed inside said first trench as to be located beneath an upper surface of said first trench, said first gate control electrode filling said first trench with said first gate insulating film interposed therebetween; a second trench formed from a region in said first main surface which is defined by one end which is said boundary and the other end away from said boundary toward said terminal region by a second distance shorter than said first distance along said first direction, through said base layer, up to said inside of said semiconductor substrate along said third direction, said second trench having a third depth larger than said first depth and extending along said second direction while being connected to said one end portion which each of said plurality of first portions has; a second gate insulating film formed entirely on a bottom surface and side surfaces of said second trench; a second gate control electrode so formed inside said second trench as to be located beneath an upper surface of said second trench, said second gate control electrode filling said second trench with said second gate insulating film interposed therebetween and being electrically connected to said first gate control electrode at said one end portion which each of said plurality of first portions has; an insulating layer formed on an upper surface of said base-layer, an upper surface of said first gate control electrode, an upper surface of said first gate insulating film, an upper surface of said second gate control electrode, an upper surface of said second gate insulating film and a region in said terminal region of said first main surface which is located outside an end of said base layer; a plurality of first contact portions each so formed in said insulating layer as to expose part of an upper surface which each of said plurality of second main electrode regions has and an upper surface of a portion in said base layer which is surrounded by each of said plurality of second main electrode regions; a plurality of second contact portions each so formed in said insulating layer as to expose part of an upper surface of a portion in said base layer which is surrounded by a side surface of said second trench on the side of said boundary, side surfaces of said adjacent first portions and a side surface of an outermost second portion of said plurality of second portions which faces said second trench; a second main electrode formed in said plurality of first contact portions and said plurality of second contact portions and on a portion in said insulating layer which is located on said cell region of said first main surface, said second main electrode extending along said second direction and being electrically connected to each of said plurality of second main electrode regions and said base layer; a third contact portion so formed in said insulating layer as to expose part of said upper surface of said second gate control electrode; and a gate electrode formed inside said third contact portion, on a portion in said insulating layer which is defined by said boundary and a location away from said boundary towards said cell region along said first direction by a third distance not reaching an end portion of said second main electrode and on a portion in said insulating layer which is defined by said boundary and a location away from said boundary towards said terminal region along said first direction by a fourth distance longer than said first distance, said gate electrode extending along said second direction and being electrically connected to said second gate control electrode through said third contact portion.