Patent ID: 6636444
Filing Date: 2003-10-21
Classification: G11C

Abstract:
A semiconductor memory device having a read data line and a write data line, comprising:an address information holding circuit holding address information that is input in relation to write data, wherein when an access occurs to the address held in said address information holding circuit, data held on said write data line is written into a memory cell corresponding to the address; a write amplifier outputting write data on said write data line, and holding said write data; an address comparator comparing received address information with the address information held in said address information holding circuit; a data selector selecting the data output from said memory cell or the data output from said write amplifier, based on the result of the comparison supplied from said address comparator, wherein said data selector selects the data output from said memory cell or the data output from said write amplifier, based on mask information indicating enable/disable of said write data.