Patent ID: 7630255
Filing Date: 2009-12-08
Classification: G11C

Abstract:
1. A method for erasing data of a NAND flash memory device including memory cell blocks, each block including a plurality of cell strings, each string including drain and source selection transistors and a plurality of memory cells, the method comprising: applying a first erase voltage to memory cells of a block to be erased; performing a first verification to verify erased states of the memory cells of the block using a first verify voltage higher than a second verify voltage; grouping the memory cells that have not passed the first verification as a first group and verifying the memory cells that have passed the first verification using the second verify voltage; grouping the memory cells that have passed the second verification as a second group and grouping the memory cells that have not passed the second verification as a third group; and erasing the first, second, and third groups of the memory cells using the first, second and third erase voltage having a first, a second, and the third step voltage, respectively, wherein the first, second and third step voltage and the first, second and third erase voltage are different from each other.