Patent ID: 8438431
Filing Date: 2013-05-07
Classification: G11C

Abstract:
1. A method of verifying an array repair code solution, the method comprising: initiating an office mode support element on a computing device; performing an initial microcode load on the office mode support element, the initial microcode load including a memory test that applies a wafer test repair algorithm to product data related to a memory on a multichip module to generate a wafer repair solution and a system test repair algorithm to the product data to generate a system test repair solution, wherein the initial microcode load is performed each time the computing device is powered on or started up; storing the wafer test repair solution in a first repair ring and the system test repair solution in a second repair ring; and comparing the first repair ring to the second compare ring to determine if the wafer test repair algorithm matches the system test repair algorithm and, thereby verify the array repair code solution.