Patent ID: 6025736
Filing Date: 2000-02-15
Classification: H03K

Abstract:
A field programmable gate array, comprising:a plurality of logic blocks that needs to be connected together in a programmable way to implement a desired function for said field programmable gate array;a plurality of input/output pins;a connection matrix coupling said logic blocks together or to said input/output pins in a programmable manner to form a circuit capable of carrying out a desired function specified by a user of said field programmable gate array, said connection matrix characterized by a plurality of conductors coupled to signal inputs and signal outputs of said logic blocks or to said input/output pins and programmably coupled to each other at every one of a plurality of programmable connection sites by programmable active links, each active link being programmable to present either a high impedance path or a low impedance path between two or more circuit nodes or conductors coupled to said active link, and each active link comprised of enabling circuitry including a memory cell for holding a programming bit that defines whether said active link is enabled or disabled by said enabling circuitry and one or more MOS transistors coupled to an external power supply and arranged to perform a repeater function on the input signal propagating through said active link, each said active link using the transconductance of its one or more transistors and transistor action of at least one or MOS transistors to turn on or turn off said at least one or more MOS transistors in response to the state said input signal thereby causing said external power supply to charge or discharge any parasitic capacitance load coupled to an output of said active link thereby substantially reducing the rise times and fall times of said input signal as it propagates through said active link.