Patent ID: 6021461
Filing Date: 2000-02-01
Classification: G06F,Y02D

Abstract:
A method of reducing power consumption in a memory system by differentiating between first and subsequent incremental fetch requests, while maintaining memory access times, comprising the steps of:providing a first and subsequent incremental fetch requests to a memory array that stores a plurality of data blocks, said plurality of data blocks being subdivided into sets, each set having at least one sense amplifier dedicated to the retrieval of said data blocks within it;generating an external address for storing and retrieving said data blocks from said memory array, wherein said first fetch or said incremental fetch request retrieves said data blocks, said first fetch request generating a set selection address in a second half of a memory cycle to be used for early set selection in subsequent incremental fetch requests;enabling one or enabling each of a plurality of sets of sense amplifiers used to retrieve said data blocks within said memory, said incremental fetch request enabling a single set of sense amplifiers corresponding to said set selection address, said first fetch enabling each of said sets of sense amplifiers, wherein a portion of address bits from said first fetch arrives in said second half of said cache memory cycle; andchoosing a set to be output from said plurality of sense amplifiers with said set selection address.