Patent ID: 9036411
Filing Date: 2015-05-19
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of memory strings including a plurality of memory transistors connected in series and stacked above the semiconductor substrate; a plurality of bit lines respectively connected to one ends of the memory strings, the bit lines including a first bit line, a second bit line, a third bit line, and a fourth bit line, the first bit line being adjacent to the second bit line, the second bit line being adjacent to the third bit line, the third bit line being adjacent to the fourth bit line; and a control circuit configured to perform an erase operation for the memory transistors electrically connected to the first bit line and the memory transistors electrically connected to the second bit line on the condition that a first voltage is applied to both the first bit line and the second bit line, and a second voltage is applied to both the third bit line and the fourth bit line, the first voltage being higher than the second voltage, wherein during the erase operation, the control circuit is configured to apply the first voltage to a source line and apply a third voltage to gates of source side selection transistors, each of the source side selection transistors being electrically connected between the memory strings and the source line, the third voltage being lower than the first voltage.