Patent ID: 8420473
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A method of simultaneously fabricating n-type and p type field effect transistors, comprising: (a) removing first and second sacrificial gates from within first and second openings in a dielectric region overlying first and second active semiconductor regions of a substrate, wherein source/drain regions are disposed within the first and second active semiconductor regions adjacent the first and second openings; (b) then forming first and second replacement gates within the first and second openings, respectively, including forming the first replacement gate having a first gate metal layer adjacent a gate dielectric layer within the first opening overlying the first active semiconductor region and forming the second replacement gate having a second gate metal layer adjacent a gate dielectric layer within the second opening overlying the second active semiconductor region, wherein the step of forming includes stacking at least portions of the first and second gate metal layers in a direction of their thicknesses with at least a barrier metal layer separating the at least portions of the gate metal layers; and (c) then completing the n-type and p-type field effect transistors, the n-type field effect transistor including the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the p-type field effect transistor including the second active semiconductor region, the source/drain regions therein and the second replacement gate.