Patent ID: 6611458
Filing Date: 2003-08-26
Classification: B82Y,C04B,G11C,H01L

Abstract:
A semiconductor integrated circuit device comprising:a volatile memory cell array including volatile memory cells; volatile redundant memory cells to substitute for a deficient memory cell when there is such a deficient memory cell which is a volatile memory cell having a defect in the volatile memory cell array; a nonvolatile memory to store redundant address information based on the deficient memory cell; and a redundant decoder coupled to the nonvolatile memory to replace an output from the deficient memory cell with an output from the redundant memory cells based on the redundant address information stored in the nonvolatile memory, wherein the nonvolatile memory includes a first semiconductor area of a first conductivity type formed in a main surface of a semiconductor substrate, a second semiconductor area of a second conductivity type provided adjacent to the first semiconductor area in said main surface of said semiconductor substrate and a floating gate arranged to interpose an insulating film of the nonvolatile memory between the first and the second semiconductor areas and the floating gate, and wherein a source area of the second conductivity type and a drain area of the second conductivity type are provided in the first semiconductor area; wherein data can be erased or written by applying a predetermined voltage to the second semiconductor area and to at least one of the source area and the drain area.