Patent ID: 8643180
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having a through-hole at a position opposed to the internal pad; an under-bump layer formed so as to cover a face exposed in the through-hole on the internal pad, an inner face of the through-hole and a circumference of the through-hole on the stress relaxation layer; a protective layer formed on the stress relaxation layer, encompassing a periphery of the under-bump layer and covering directly the under-bump layer while preventing a side face of the under-bump layer from being exposed; a connection pad composed of a buried portion completely filling the through-hole and a protruding portion including an upper protruding portion protruding on the stress relaxation layer and a lower protruding portion formed on and narrower than the upper protruding portion; and a solder terminal for electrical connection with outside formed on the connection pad so as to cover an entire surface of the protruding portion, wherein a width of an opening of the through-hole in the stress relaxation layer is smaller than a width of the circumference of the through-hole covered by the protruding portion, wherein the protective layer is formed only at a circumference of the under-bump layer on a side toward the stress relaxation layer with respect to a center position of the solder terminal in a laminating direction of the semiconductor chip and the stress relaxation layer, wherein a height of the protective layer measured from the stress relaxation layer is larger than a height of the protruding portion of the connection pad measured in the same way, and wherein the protective layer is formed only at a region between a circumference of the solder terminal and a circumference of the protruding portion when viewed in plan.