Patent ID: 6281737
Filing Date: 2001-08-28
Classification: H03K

Abstract:
An apparatus for reducing parasitic bipolar current in a field effect transistor (""FET""), comprising:a first FET, having a body disposed, at least in part, on an insulator; andcontrol circuitry coupled to the body and a gate electrode of the first FET, for controlling charge on the body responsive solely to a single control circuitry input voltage, the voltage also being applied directly to the gate electrode, wherein the first FET is operable to turn on and off responsive to the voltage applied to the gate electrode, and wherein the control circuitry has a discharge path and the control circuitry is operable to turn on the path and discharge at least a portion of any charge on the body when the first FET is turned off, and to turn off the path and allow the body to float and charge to accumulate on the body when the first FET is turned on.