Patent ID: 7948414
Filing Date: 2011-05-24
Classification: H03M

Abstract:
1. A delta-sigma analog-to-digital conversion (DSADC) apparatus for receiving an analog input signal to generate a digital output signal, comprising: a subtracting unit, for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal; a quantizer, coupled to the subtracting unit, for performing quantization to generate a quantized signal according to the subtracted signal; a feedback unit, coupled between the subtracting unit and the quantizer, for providing the feedback signal to the subtracting unit according to the quantized signal; and a transfer function compensation unit, coupled to the quantizer, for generating the digital output signal according to the quantized signal, the transfer function compensation unit compensates the quantized signal for a transfer function variation generated by subtracting the feedback signal from the analog input signal to generate the digital output signal, and the transfer function compensation unit comprises: wherein the subtracting unit is arranged to reduce signal input swing of the quantizer.