Patent ID: 6026037
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A programmable logic circuit, comprising:a flip-flop having two cross-coupled first 2-input logic gate and second 2-input logic gate, each said logic gate having a reset input and a cross-coupled input,said first 2-input logic gate having an output precharged to a first logic level before a reset signal is applied to said first logic gate, and having a load device comprising a plurality of parallel branches, each having a fuse in series with a switch,each of said switch being controlled by an address signal, andeach said fuse corresponding to each said address signal being cut off by a previous program such that the branch controlled by said address signal is open-circuited and causing the flip-flop to remain in a condition where the output of said first 2-input logic is precharged to said first logic level, andan output terminal coupled to said second logic gate to reflect said condition.