Patent ID: 7615843
Filing Date: 2009-11-10
Classification: H01G,H01L

Abstract:
1. A semiconductor device, comprising: a memory chip including a voltage pad, the voltage pad comprising a ground voltage pad for supplying a ground voltage and a power voltage pad for supplying a power voltage; and a guard ring device in which an N number of conductive layers are electrically connected with the ground voltage pad and the power voltage pad and stacked, the N conductive layers comprising X odd conductive layers and Y even conductive layers stacked in an alternating fashion, wherein a capacitor is formed by supplying the ground voltage to the X odd conductive layers and supplying the power voltage to Y even conductive layers, wherein the N number of conductive layers are sequentially stacked and comprise an active region guard ring, a gate guard ring, a bit line guard ring, a first metal guard ring, and a second metal guard ring, wherein the active region guard ring, the bit line guard ring, and the second metal guard ring are electrically connected, and wherein the gate guard ring and the first metal guard ring are electrically connected.