Patent ID: 6882570
Filing Date: 2005-04-19
Classification: G11C

Abstract:
1. A power detecting circuit which initializes logic circuits in a flash memory chip at power-on and commences a stable read operation of the flash memory device, comprising: a latch having a first input terminal, a second input terminal, and an output terminal connected to the memory chip, the output terminal outputting a power-on read signal for triggering a read operation of the memory chip; and a voltage detector connected to the first and second input terminals of the latch and the logic circuits, wherein when a power supply voltage is lower than a first voltage the voltage detector resets the latch so that the power-on read signal is established to a logically inactivated state, and initializes the logic circuits; and wherein when the power supply voltage is over a second voltage higher than the first voltage, the voltage detector sets the latch so that the power-on read signal is established to a logically activated state to trigger the stable read operation.