Patent ID: 7525145
Filing Date: 2009-04-28
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a memory cell transistor; and a peripheral circuit transistor, wherein said memory cell transistor includes, in a memory cell forming region of a semiconductor substrate, a source region, a drain region, a channel region interposed between said source region and said drain region, a first gate electrode and a second gate electrode disposed on said channel region, a first gate insulating film formed between said channel region and said first gate electrode, a nonconductive charge trap film as a charge storage region formed between said channel region and said second gate electrode, and an insulating film for electrically isolating said first gate electrode from said second gate electrode, wherein said insulating film is formed between one side surface of said first gate electrode and one side surface of said second gate electrode, wherein said second gate electrode is formed over said one side surface of said first gate electrode through said insulating film, wherein said peripheral circuit transistor has a gate electrode and is formed over a peripheral circuit transistor forming region of said semiconductor substrate, and wherein said first gate electrode has a thickness different from that of said gate electrode of said peripheral circuit transistor.