Patent ID: 8775902
Filing Date: 2014-07-08
Classification: G06F,H03M,H04L

Abstract:
1. A memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device, the memory controller comprising: an external interface configured to transmit and receive the write data/the read data to and from the host device; a first ECC generating unit configured to generate parity data and a first ECC code for the write data; an access unit configured to control writing and reading of the write data/the read data or parity data to and from the memory; a first ECC correcting unit configured to correct an error of read data, by using data and parity data read from the memory via the access unit; and a control unit configured to control the external interface, the first ECC generating unit, the access unit, and the first ECC correcting unit, wherein the control unit