Patent ID: 6171908
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method of forming a non-volatile memory device having a split-gate structure, comprising:providing a semiconductor substrate;forming a first isolation region and a second isolation region in said semiconductor substrate, said isolation regions having an active region defined in a recessed region between said first isolation region and said second isolation regions;a first doped region and a second doped region provided within the active region, the first and second doped regions being separated by an area having a first portion and a second portion;forming a dielectric layer overlying said active region;forming a thickness of material overlying said first isolation region, said second isolation region, and said active region;selectively removing portions of said thickness of material overlying portions of said first isolation region and said second isolation region leaving a substantially planar material region in said recessed region, said substantially planar material region being self-aligned into said recessed region;selectively etching said substantially planar material region to form a floating gate overlying said first portion of said area but not said second portion of said area; andforming a control gate overlying said second portion of said area and a portion of said first portion of said area.