Patent ID: 6553460
Filing Date: 2003-04-22
Classification: G06F

Abstract:
In a data processing system executing instructions and storing and receiving data from a memory having locations in a memory space, the data processing system also having a cache memory, the cache memory having a number of entries, wherein the entries of the cache memory arc in locations in a control/configuration register space addressable separate from the memory space, a method comprising the steps of:A. executing a first instruction to obtain address information from at least one entry of the cache memory, wherein the first instruction operates only on locations in control/configuration register space but not on locations in memory space; B. comparing the obtained address information with target address information; C. if the comparison between the obtained address information and the target address information results in a correspondence, then a first operation is performed on the at least one entry of the cache memory; and D. if the comparison between the obtained address information and the target address information does not result in a correspondence, then the first operation is not performed on the at least one entry of the cache memory; wherein management operations are performed on the cache memory without using locations in memory space.