Patent ID: 7793081
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. A method for register renaming in an out-of-order processor, comprising: translating at least one of a plurality of non-contiguous register specifiers included in a fixed-width instruction set into a contiguous logical register specifier, wherein the at least one non-contiguous register specifier is at least partially encoded in a deeply encoded field of a fixed-width instruction, the deeply encoded field used to encode both the at least one non-contiguous register specifier and an additional portion of the instruction; and remapping a logic register name to a physical register using the contiguous logical register specifier, wherein the logic register name is specified in the fixed-width instruction set using non-contiguous fields, wherein said at least one non-contiguous register specifier comprises at least a first set of contiguous bits specified directly in an instruction field and a second set of contiguous bits specified in the deeply encoded field, said first and second sets being separated by at least one bit which is not part of the encoding of the at least one of the plurality of non-contiguous register specifiers.