Patent ID: 7648878
Filing Date: 2010-01-19
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a pad oxide layer on a substrate; forming a pad nitride layer on the pad oxide layer; patterning the pad nitride layer and the pad oxide layer; etching predetermined portions of the substrate using the patterned pad nitride layer as an etch barrier to thereby form trenches; filling an insulation layer into the trenches to thereby form device isolation regions, wherein the patterned pad nitride layer and the patterned pad oxide layer are interposed between the device isolation regions and the device isolation regions are exposed; simultaneously removing the pad nitride layer while removing a portion of the insulation layer for the device isolation regions and a portion of the pad oxide layer, wherein a thickness of the removal portion of the device isolation regions is smaller than a thickness of the removal portion of the pad oxide layer due to a different etching rate between the insulation layer and the pad oxide layer; forming recesses by etching predetermined portions of the pad oxide layer and the substrate; removing the pad oxide layer; forming a gate oxide layer along a profile of the resultant structure having recesses; and forming gate structures of which bottom portions are buried in the recesses on the gate oxide layer, wherein a whole top surface of the insulation layer for the device isolation regions remains higher than a top surface of the substrate.