Patent ID: 6495907
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A metallization structure on a semiconductor device, said structure comprising:(a) a plurality of first conducting regions formed on a substrate, at least one of said first conducting regions being a non-reticulated conductor and at least one of said first conducting regions being a reticulated conductor, said reticulated conductor comprising a set of conducting segments connected to provide multiple conducting paths between opposing ends of said reticulated conductor; (b) at least one insulating layer overlying said first conducting regions and said substrate, the uppermost of said insulating layers providing a top surface which is locally planar to at least 3000 Ã¥; and (c) a plurality of second conducting regions formed over said insulating layers, at least one of said second conducting regions electrically connected to at least one of said first conducting regions through said insulating layers; whereby planarity of said insulating layers is at least partially effected by use of said reticulated conductor instead of a non-reticulated conductor of equivalent resistivity and length.