Patent ID: 7936200
Filing Date: 2011-05-03
Classification: G01R,G06F

Abstract:
1. A clock circuit, including: a first clock input for receiving a first clock signal; a second clock input for receiving a second clock signal; a clock calibration unit connected to said first clock input and said second clock input, for calibrating the second clock signal relative to said first clock signal, said clock calibration unit having a calibration output for outputting a calibrated clock signal; a switch unit connected to said first clock input and said calibration output, for selecting a selected clock signal selected from said first clock signal and said calibrated clock signal, said switch unit having a switch output for outputting said selected clock signal; a switch control unit connected to said switch unit for controlling which signal is selected based on at least one selection criterion; a clock circuit output connected to said switch unit for outputting said selected clock signal.