Patent ID: 8301434
Filing Date: 2012-10-30
Classification: G06F

Abstract:
1. A computer program product for emulating execution of Guest processor instructions on a Host processor, the Host processor configured to execute Host instructions of a Host instruction set, wherein the Guest instructions to be emulated are not instructions of the Host instruction set, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: creating, by the Host processor, a cell association wherein each of m Guest cells of Guest addressable memory are associated with a corresponding Host cell of m Host cells of Host addressable memory, said m Guest cells comprising first Guest cells, each first Guest cell corresponding to a beginning portion of a Guest instruction to be emulated, wherein long Guest instructions occupy a plurality of Guest cells consisting of said first Guest cell and one or more second Guest cells, wherein each Guest cell is x bytes of memory, wherein each Host cell is y bytes of memory, wherein each first Host cell comprises a semantic routine for performing function of an Guest instruction of a corresponding first Guest cell, wherein each second Host cell comprises a wild branch handling routine for performing a wild branch function according to a Guest computer architecture; based on the specified Host cell being a first Host cell corresponding to a first Guest cell, executing the semantic routine of the specified Host cell to perform function of the Guest instruction; and based on the specified Host cell being a second Host cell corresponding to a second Guest cell, executing the wild branch handling routine of the specified Host cell to perform the wild branch function.