Patent ID: 6848027
Filing Date: 2005-01-25
Classification: G06F

Abstract:
1. A data processor for use with a main memory which stores data and instructions, said data processor comprising: an instruction processor for processing said data in accordance with said instructions; a cache memory part connected between said main memory and said instruction processor, including first and second cache memories, said first cache memory and said second cache memory having different storage capacities; and a controller, included in said cache memory part, which in response to an address to be accessed, selects one of said first and second cache memories and stores data in the selected cache memory, wherein said controller includes a storage having stored therein a plurality of addresses and information, each of said addresses being stored in corresponding relation to a portion of said information which indicates one of said first and second cache memories to be accessed, and wherein said controller reads out data from the main memory and stores the data into one of said first and second cache memories indicated by said portion of said information when the data is not stored in said first and second cache memories.