Patent ID: 7332787
Filing Date: 2008-02-19
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer which contacts and is electrically connected to the N-type semiconductor and the P-type semiconductor; a dielectric layer disposed on an upper surface of the first conductive layer; and a second conductive layer disposed on an upper surface of the dielectric layer, wherein the second conductive layer, the first conductive layer and the dielectric layer form a capacitor, wherein the first conductive layer and the P-type semiconductor form a first Schottky diode connected in series to the capacitor, and the first conductive layer and the N-type semiconductor form a second Schottky diode connected in parallel to the capacitor.