Patent ID: 6654309
Filing Date: 2003-11-25
Classification: G11C

Abstract:
In a semiconductor memory, a circuit for generating an output signal to one or more memory cells of the memory, the output signal corresponding to a global word line input signal, the circuit comprising:a first switch having an input coupled with the global word line input signal, the first switch having a control and an output; a second switch having an input coupled with the output of the first switch at an output node, the second switch having a control and an output; a third switch having an input coupled with the global word line input signal, the third switch having a control and an output, the output of the third switch being coupled with the output of the first switch at the output node; a fourth switch having an input coupled with the output of the third switch at the output node, the fourth switch having a control and an output, said output of the fourth switch coupled with the output of the second switch; a first block select line coupled with the control of said first switch; a second block select line coupled with the control of said fourth switch, the second block select line being a complement of the first block select line; a third block select line coupled with the control of said second switch; and a fourth block select line coupled with the control of said third switch, the fourth block select line being a complement of the third block select line.