Patent ID: 6184902
Filing Date: 2001-02-06
Classification: G06F,G06T

Abstract:
A method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing centralized branching intelligence, comprising the steps of:implementing a plurality of control units in a read-only memory (ROM) via microcode instructions;implementing a stack of a plurality of processing elements;executing said microcode instructions with said processing elements in order to modify image data;after execution of each microcode instruction, enabling branching to one of a plurality of possible microcode locations based upon a next address associated with said each microcode instruction;tracking operation of said control units with a branch central intelligence mechanism;implementing a plurality of branch logic mechanisms corresponding respectively with said control units; andwith each said branch logic mechanism, defining said next address for corresponding instructions based upon state data received from said stack, said branch central intelligence mechanism, and a corresponding ROM-based control unit.