Patent ID: 6661731
Filing Date: 2003-12-09
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction; a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays; a plurality of word lines connected to said memory cells in said sub-memory arrays; a plurality of global bit lines connected in parallel to said local bit lines in said sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction; a plurality of read/write circuits connected to said global bit lines, and reading and writing information from and into said memory cells; a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus; a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to said first read/write circuit, and a second sub-memory cell array on a second global bit line connected to said second read/write circuits; and an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.