Patent ID: 6303418
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method of forming a first type gate structure, for a first type complimentary metal oxide semiconductor device, (CMOS), device, and simultaneously forming a second type gate structure, for a second type CMOS device, on a semiconductor substrate, comprising the steps of:forming a first dummy gate structure on a first region of said semiconductor substrate, to be used for said first type CMOS device, and forming a second dummy gate structure on a second region of said semiconductor substrate, to be used for said second type CMOS device;forming a first lightly doped source/drain region, of a first conductivity type, in an area of said first region of said semiconductor substrate not covered by said first dummy gate structure, and forming a second lightly doped source/drain region, of a second conductivity type, in an area of said second region of said semiconductor substrate not covered by said second dummy gate structure;forming insulator spacers on the sides of said first dummy gate structure, and on the sides of said second dummy gate structure;forming a first heavily doped source/drain region, of a first conductivity type, in an area of said first region of said semiconductor substrate not covered by said first dummy gate structure or by said insulator spacers, and forming a second heavily doped source/drain region, of a second conductivity type, in an area of said second region of said semiconductor substrate not covered by said second dummy gate structure or by said insulator spacers;forming a planarized, composite insulator layer, between dummy gate structures, with a top surface of said first dummy gate structure, and with a top surface of said second dummy gate structure, exposed;selectively removing said first dummy gate structure, exposing a first channel region, located between said first lightly doped source/drain regions, and selectively removing said second dummy gate structure, exposing a second channel region, located between said second lightly doped source/drain regions;depositing a high dielectric constant, (high k), gate insulator layer;depositing a doped polysilicon layer;removing a portion of said polysilicon layer from the top surface of said high k gate insulator layer, in said second region of said semiconductor substrate;depositing a metal layer, completely filling spaces created by removal of said dummy gate structures; andremoving a first portion of said metal layer, from the top surface of said high k gate insulator layer to form said second type gate structure, comprised of metal, on said high k gate insulator layer, on said second channel region in said second region of said semiconductor substrate, and removing a second portion of said metal layer, and a portion of said polysilicon layer, from the top surface of said high k gate insulator layer, to form said first type gate structure, comprised of metal-polysilicon, on said high k gate insulator layer, in said first region of said semiconductor substrate.