Patent ID: 6237054
Filing Date: 2001-05-22
Classification: G01R

Abstract:
A microcontroller formed upon a single monolithic semiconductor substrate, comprising:an execution unit, comprising:a processor core configured to execute instructions and to produce output signals during instruction execution;a plurality of configurable logic blocks coupled to receive the output signals;wherein during a programming operation the output signals comprise programming signals, and wherein the programming signals configure each of the configurable logic blocks to perform a selected function; andwherein following the programming operation each of the configurable logic blocks performs the selected function in response to the output signals;an operand bus having a plurality of signal lines, wherein the processor core and each of the plurality of configurable logic blocks are coupled to the operand bus, and wherein the operand bus conveys output signals from the processor core to each of the plurality of configurable logic blocks;a result bus having a plurality of signal lines, wherein the processor core and each of the plurality of configurable logic blocks are coupled to the result bus, and wherein the result bus conveys signals from each of the plurality of configurable logic blocks to the processor core;a control bus having a plurality of signal lines, wherein the processor core and each of the plurality of configurable logic blocks are coupled to the control bus, and wherein the control bus conveys control signals between the processor core and each of the plurality of configurable logic blocks; anda test/program bus having a plurality of signal lines, wherein the processor core and each of the plurality of configurable logic blocks are coupled to the test/program bus, and wherein the test/program bus conveys testing signals used to assess proper operation of the plurality of configurable logic blocks, and wherein the test/program bus also conveys the programming signals from the processor core to each of the plurality of configurable logic blocks.