Patent ID: 7594100
Filing Date: 2009-09-22
Classification: G06F

Abstract:
1. An apparatus that implements a store queue which holds pending stores and applies the stores to a memory subsystem of a processor in program order, the apparatus comprising: a content-addressable memory (CAM) which holds the stores that are pending and facilitates looking up the stores based on addresses for the stores; wherein the CAM does not keep track of program order between stores to different addresses; and a program-order queue that is organized as a first-in-first-out (FIFO) buffer, wherein each entry in the program-order queue contains an address for a store and an index into the CAM which specifies where an entry for the store is located in the CAM; wherein the program-order queue is configured to send to the CAM a request which includes the index into the CAM, and in response to the request, the CAM is configured to send data for the store associated with the index, wherein the data for the store associated with the index is committed to memory; and wherein the program-order queue keeps track of program order between the stores in the CAM and thereby facilitates applying the stores to the memory subsystem in program order.