Patent ID: 6249127
Filing Date: 2001-06-19
Classification: G01R,H04L

Abstract:
A method for checking lead defects in a two-wire bus system, comprising the steps of:detecting a voltage level of a first wire and a voltage level of a second wire of said two wire bus system;comparing the voltage level detected on the first wire and the voltage level detected on the second wire with a threshold voltage level that is greater than a predetermined maximum voltage level on the two wires in the dominant and recessive states during normal operation;comparing the voltage level detected on the first wire and the voltage level on the second wire with a second threshold voltage that is between a first voltage value on a first wire of the two wires and a second voltage value on a second wire of said two wires in the dominant and recessive states during normal operation; andsubtracting the results of the comparisons of the voltage level of the first wire and the voltage level of the second wire with said second threshold voltage.