Patent ID: 6584015
Filing Date: 2003-06-24
Classification: G06F,G11C

Abstract:
A storage apparatus to be coupled with a system bus for receiving a write request accompanied with data through said system bus from a host system comprising:a nonvolatile flash semiconductor memory comprising a plurality of memory blocks and a management area, and a controller unit which is coupled with said system bus and said nonvolatile flash semiconductor memory, and which carries out error detection and correction operations with respect to read data from one of said plurality of memory blocks of said nonvolatile flash semiconductor memory; wherein said controller unit keeps count of the error correction operation of the read data for each block to determine whether the count reaches a predetermined value and if it determines that the count of the error correction operation has not yet reached said value, the control unit carries out a recording operation of data after the error correction operation in the same memory block of said plurality of memory blocks.