Patent ID: 6563737
Filing Date: 2003-05-13
Classification: G11C

Abstract:
A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, comprising: current/voltage conversion circuits receiving at the input thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first node a first selected cell voltage and on a second node a second reference cell voltage; at least one differential amplifier having inputs connected to the first and second nodes and having an output terminal effective to supply a logic signal correlated to the information contained in said selected cell; at least one first voltage-controlled discharge switch circuit connected to the input of said first node and to a voltage reference, a second voltage-controlled discharge switch circuit connected to the input of said second node and to the voltage reference; and at least a first and a second voltage comparator circuit receiving at the input thereof said first selected cell voltage and said second reference cell voltage, said comparator circuits are configured for controlling voltage in said first and second voltage-controlled discharge switch circuits.