Patent ID: 7443450
Filing Date: 2008-10-28
Classification: G09G,H04N

Abstract:
1. A sync processor of a flat panel display (FPD) device, comprising: a digital horizontal/vertical signal generator that generates a digital horizontal/vertical sync signal in response to a data enable signal; a first selector that selects the digital horizontal/vertical sync signal or a horizontal/vertical sync signal received from a digital video interface (DVI), in response to a first selection signal; a digital horizontal/vertical signal detector that detects a signal transmitted by the first selector and that generates a digital horizontal/vertical signal; a horizontal/vertical polarity determination unit that receives the horizontal/vertical sync signal, that counts a number of cycles of low duration of the horizontal/vertical sync signal and a number of cycles of high duration of the horizontal/vertical sync signal, and that generates a horizontal/vertical polarity signal in response; and a horizontal/vertical frequency determination unit that receives the digital horizontal/vertical signal, that counts a number of cycles of a clock signal occurring in low durations of the digital horizontal/vertical signal and a number of cycles of the clock signal occurring in high durations of the digital horizontal/vertical signal, and that generates a horizontal/vertical frequency signal in response.