Patent ID: 8338235
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. A package process, comprising: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has a first surface facing the carrier and plural contacts on the first surface, and the semiconductor substrate is bonded to the carrier with a passivation layer on the first surface; thinning the semiconductor substrate from a back side of the semiconductor substrate in opposite to the first surface, wherein the thinned semiconductor substrate has a second surface opposite to the first surface; forming plural through silicon vias in the thinned semiconductor substrate, wherein the through silicon vias respectively correspond to and connect to the contacts; forming plural first pads on the second surface of the semiconductor substrate, wherein the first pads respectively correspond to and connect to the through silicon vias; bonding plural chips to the second surface of the semiconductor substrate, wherein the chips respectively electrically connect to the corresponding first pads; forming a molding compound on the second surface of the semiconductor substrate, wherein the molding compound covers the chips and the first pads; separating the semiconductor substrate and the carrier, wherein the passivation layer is remained on the first surface of the semiconductor substrate; forming a redistribution layer on the passivation layer after the semiconductor substrate and the carrier are separated, wherein a surface of the redistribution layer has plural second pads, and the second pads respectively electrically connect to the contacts; forming plural solder balls on the first surface of the semiconductor substrate, wherein the solder balls respectively electrically connect to the corresponding contacts; and simultaneously sawing the molding compound and the semiconductor substrate to form a plurality of package units.