Patent ID: 8026577
Filing Date: 2011-09-27
Classification: H01L

Abstract:
1. A semiconductor apparatus comprising: a semiconductor substrate that is entirely a first conductive type; a first well-region of a second conductive type that is formed in a surface layer of the semiconductor substrate; a second well-region of the first conductive type that is formed in the surface layer of the semiconductor substrate, a bottom surface of the second well-region and a side surface of the second well-region being in contact with the first well-region; a transistor that is formed in the second well-region, the transistor being an MOS transistor having a source region and a drain region; and a through-hole region that is formed to be pierced through the first well-region, and enables the bottom surface of the second well-region to be electrically conductive to the semiconductor substrate, wherein the MOS transistor is arranged above the through-hole region, the MOS transistor being arranged planarily inside of the through-hole region, the border of the through-hole region is arranged to be planarily apart from the MOS transistor, and the source region and the drain region of the MOS transistor is arranged to be apart from the first well-region.