Patent ID: 6119211
Filing Date: 2000-09-12
Classification: G11C

Abstract:
A circuit for controlling writing data into an address of a memory, said data and address being transmitted from a central processing unit, said circuit comprising:(a) a judgement circuit for judging whether writing data into an address is completed, said judgement circuit invalidating a first signal transmitted therefrom while a second signal introduced thereto from said central processing unit is valid, and validating said first signal only if a period of time necessary for writing data into an address has passed and if a reset signal is received by said judgement circuit while said second signal is valid; said second signal being a signal instructing to write data into an address and said first signal being a signal instructing to terminate writing data into an address;(b) a status flag for transmitting a third signal which is a signal to allowing write data into an address, said status flag being set on receiving said second signal from said central processing unit thereby validating said third signal, and being reset on receiving a valid first signal from said judgement circuit thereby invalidating said third signal;(c) address latch and data latch latching am address transmitted from said central processing unit and data to be written into the thus transmitted address, respectively, said address and data latches writing said data into said address by valid third signal, wherein even if said reset signal is received by said judgement circuit, said address and data latches retain address and data that exist therein before said reset signal is received; and(d) a reset signal transmitter transmittance a reset signal to reset circuit elements required to be reset other than said judgement circuit, said status flag and said address and data latches.