Patent ID: 7425396
Filing Date: 2008-09-16
Classification: G03F,H01L,Y10S

Abstract:
1. A method for reducing an overlay error between structures of two photolithographic planes during the transfer of a respective circuit pattern by photo masks onto a semiconductor substrate in a projection system for fabricating integrated components, comprising: a1) transferring a first standard measurement mark for determining the overlay error into a reference layer; a2) transferring a second standard measurement mark assigned to the first standard measurement mark into a further layer on the semiconductor substrate; a3) transferring at least one first further measurement mark assigned to the second standard measurement mark for determining an additional imaging error of the projection system into the further layer on the semiconductor substrate, the first further measurement mark having a geometry such that, during the transfer, the further measurement mark experiences the same lateral shift as one of the structures of a circuit pattern transferred into the further layer together with the first further measurement mark, b) measuring a first positional deviation between the mutually assigned standard measurement marks of the reference layer and the further layer; c) measuring a second positional deviation between one of the standard measurement marks and the first further measurement mark; d) calculating the overlay error from the measured first and the measured second positional deviation; e) determining a correction value for an alignment of the semiconductor substrate during the transfer of the circuit pattern into the further layer; and f) transferring the circuit pattern onto the semiconductor substrate with application of the correction during the alignment.