Patent ID: 6529045
Filing Date: 2003-03-04
Classification: H03K

Abstract:
A circuit, comprising:an n-channel clock transistor coupled between a dynamic output node and a first supply voltage, a gate of the n-channel clock transistor coupled to receive an inverse clock signal; a first inverter and a second inverter connected in series, an input of the first inverter connected to an output of the second inverter, and an input of the second inverter connected to the dynamic output node; an n-channel level keeper transistor coupled between the dynamic output node and the first supply voltage, a gate of the n-channel level keeper transistor coupled to the output of the first inverter; a pull-down circuit connected between the dynamic output node and a second supply voltage; and a p-channel standby transistor coupled between the first voltage supply and the dynamic output node, a gate of the p-channel standby transistor coupled to receive an inverse standby signal.