Patent ID: 7085993
Filing Date: 2006-08-01
Classification: H04L

Abstract:
1. A system for dynamically optimizing a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device comprising: a transmitter means for successively transmitting data signals for receipt by a receiver device within said IC; a clock generator circuit for providing a clock timing signal to respective said transmitter means and said receiver device, said clock timing signal used for timing said data signal transmission and reception within said IC at successively different clock speeds, each said successive data signal transmission transmitted at a different clock speed; a monitoring circuit means for receiving successive data signal transmissions generated at different clock speeds and detecting when a data signal transmission fail point is achieved at a particular clock speed; and, means for adjusting said clock timing signal provided to respective said transmitter means and said receiver device at each clock speed, said means adjusting said clock timing signal to achieve a maximum speed allowed for the IC that avoids said data transmission fail point during real-time operation.