Patent ID: 6399483
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method of forming a dual damascene opening, said dual damascene opening containing an upper or interconnect line portion and a lower or plug portion, comprising:providing a semiconductor substrate; depositing a first stop layer over the surface of said substrate; depositing a first layer of dielectric over said first stop layer; depositing a second stop layer over said first layer of dielectric; depositing a second layer of dielectric over said second stop layer; creating an opening having sidewalls and a bottom through said first and second dielectric, thereby including said second stop layer; depositing a layer of ARC over said second layer of dielectric, thereby including the sidewalls and the bottom of said opening; etching said interconnect line pattern of said dual damascene structure, thereby partially removing said ARC from inside of said opening, thereby furthermore leaving remnants of chemical materials in place around an upper perimeter of said lower portion of said dual damascene opening, said etching said interconnect line pattern of said dual damascene structure is etching using a polymer rich etchant containing C4F8/CO/Ar, thereby protecting said sidewalls of said opening; removing said remnants of chemical materials from around said upper perimeter of said lower portion of said dual damascene opening; and removing said ARC from said sidewalls and said bottom of said opening, thereby simultaneously removing final remnants of said chemical materials in place around said upper perimeter of said lower portion of said dual damascene opening.