Patent ID: 9207958
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. A hardware coprocessor, comprising: an abstract machine instruction interface that receives abstract machine instructions; coprocessor core logic coupled to the abstract machine instruction interface, the coprocessor core logic operable to receive abstract machine instructions and to generate at least one native machine instruction; and a microcode store, coupled to the coprocessor logic, that is operable to provide microinstructions to the coprocessor logic to facilitate generation of the at least one native machine instruction; and a native machine instruction interface that provides the at least one native machine instruction for execution by a processor; wherein the coprocessor includes at least one register that stores a value to control a state of the coprocessor, and wherein at least one generated native machine instruction, when executed by the processor, modifies the value in at least one of the at least one register to control the coprocessor in accordance with the modified value prior to further generation of native machine instructions from abstract machine instructions.