Patent ID: 6621545
Filing Date: 2003-09-16
Classification: G02F,H01L

Abstract:
A thin film transistor array panel, comprising:an insulating substrate; a gate wire including a gate line, a gate electrode and a gate pad and formed on the insulating substrate; a gate insulating layer pattern having a contact hole exposing the gate pad and formed on the gate wire; a semiconductor layer pattern formed on the gate insulating layer pattern; an ohmic contact layer pattern formed on the semiconductor layer pattern; a data wire formed on the ohmic contact layer pattern, having a boundary line substantially matching that of the ohmic contact layer pattern, and including a source electrode, a data line and a data pad; a passivation layer pattern formed on the data wire, having contact holes exposing the gate pad, the data pad and the drain electrode, having a boundary line substantially matching that of the semiconductor layer pattern except for portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire; an electrode pattern electrically connected to the exposed gate pad, data pad and drain electrode.