Patent ID: 7061015
Filing Date: 2006-06-13
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel for liquid crystal display comprising: gate wire formed on a substrate, and including a gate line, a gate electrode connected to the gate line and a gate pad connected to one end of the gate line; a gate insulating film covering the gate wire; a semiconductor layer formed on the gate insulating layer; data wire formed on the gate insulating film or on the semiconductor layer, and including a data line, a source electrode connected to the data line and adjacent to the gate electrode, a drain electrode placed apposite to the source electrode in relation to the gate electrode and a data pad connected to one end of the data line; an interlayer insulating film covering the semiconductor layer and first contact holes for exposing the gate pad or the data pad; and an assistant pad formed on the interlayer insulating film and connected to the gate pad or the data pad via the first contact holes, wherein, the interlayer insulating film is made of a lower insulating film and an upper insulating film formed on the lower insulating film, and, in the first contact holes, borderlines between the lower insulating film and the first contact holes are formed within borderlines between the upper insulating film and the first contact holes to expose upper surfaces of portions of the lower insulating film adjacent to the borderlines between the lower insulating film and the first contact holes.