Patent ID: 6762633
Filing Date: 2004-07-13
Classification: H03L

Abstract:
A delay locked loop circuit with an improved jitter performance, comprising:a variable delay circuit for receiving a reference clock signal and generating a delayed output clock signal, based at least on a predetermined variable delay from the reference clock signal; a main phase determining circuit for receiving the reference clock signal and the output clock signal, and generating a phase pull signal and a phase push signal, the main phase determining circuit comprising: a first delay circuit for receiving the reference clock signal and delaying the reference signal by a first predetermined time period; a second delay circuit for receiving the output clock signal and delaying the output clock signal by a second predetermined time period; a first phase determining circuit for receiving the delayed reference clock signal and the output clock signal, and for generating a first phase pull signal when the phase of the delayed input clock signal leads the phase of the output clock signal, and a first phase push signal when the phase of the delayed input clock signal lags behind the phase of the output clock signal; a second phase determining circuit for receiving the reference clock signal and the delayed output clock signal, and for generating a second phase pull signal when the phase of the input clock signal leads the phase of the delayed output clock signal, and a second phase push signal when the phase of the input clock signal lags behind the phase of the delayed output clock signal; wherein the phase pull signal is generated when both the first and second pull signals are logically high, and wherein the phase push signal is generated when both the first and second push signals are logically high; and a delay control circuit for generating a delay control signal for controlling the predetermined variable delay.