Patent ID: 6262921
Filing Date: 2001-07-17
Classification: G11C,H03K,H03L

Abstract:
A variable delay circuit for a delay-locked loop, comprising:an input terminal;an output terminal;a reference terminal;a first buffer having a first input coupled to the input terminal and a first buffer output;a second buffer having a second input coupled to the first buffer output, and a second buffer output coupled to the output terminal;a first capacitor selectively coupleable between the first buffer output and the reference terminal;a second capacitor selectively coupleable between the first buffer output and the reference terminal;a first isolation switch serially coupled with the first capacitor, between the first output and the reference terminal, the first isolation switch having a first switching input and being responsive to a selection signal at the first switching input to selectively couple the first capacitor between the first buffer output and the reference terminal; anda model circuit serially coupled with the first and second buffers having a model circuit delay corresponding to the delay of an input signal relative to a reference input signal, the model circuit comprising:a serially connected chain of delay elements, serially coupled to the first and second buffers; anda programmable bypass circuit selectively programmable to bypass one or more of the delay elements.