Patent ID: 6167503
Filing Date: 2000-12-26
Classification: G06F

Abstract:
A superscalar processor comprising:an instruction cache for storing instructions, some of the instructions including at least one operand, each operand having a virtual register address;a plurality of execution clusters for executing instructions, each execution cluster comprising a plurality of execution units, each including at least one arithmetic unit and one or more memory access units, and each execution cluster further including a plurality of registers having disjoint physical register addresses, each register corresponding to a unique one of the virtual register addresses;an instruction partitioning and distribution unit for fetching instructions from the instruction cache, partitioning instructions into a plurality of sets of instructions and distributing each instruction that includes at least one operand to the one of the plurality of execution clusters having the register corresponding to the virtual register address of the operand, addresses of data stored in the plurality of registers accessed by a plurality of instructions being disjoint among said plurality of execution clusters, instructions with virtual register addresses having operands assigned to corresponding physical register addresses at the time instructions are issued for execution, the instruction partitioning and distribution unit further comprising:a distribution buffer, the distribution buffer having a plurality of locations for storing instructions for distribution to the plurality of execution clusters; andmeans for assigning a unique serial number to each of the plurality of instructions stored in the distribution buffer, the serial numbers assigned in the order that the plurality of instructions are fetched from the instruction cache, and the serial numbers distributed to the execution clusters with the instructions;a central controller, connected in a communicating relationship with the instruction partitioning distribution unit and the plurality of execution clusters for distributing instructions, dependent on a predicted behavior of execution flow based on previously executed instructions, for coordinating the functioning of the superscalar processor and for monitoring the serial number of each instruction in each of the execution clusters.