Patent ID: 8051401
Filing Date: 2011-11-01
Classification: G06F,H01L

Abstract:
1. A method of generating a layout for an integrated circuit having at least a substrate upon which a plurality of gates are formed, a first metal layer overlying said substrate and a second metal layer overlying said first metal layer, said method comprising the steps of: selecting a placement upon said integrated circuit of a plurality of power connection conductors to be formed as part of said first metal layer, a plurality of routing connection conductors to be formed as part of said first metal layer and a plurality of power rail conductors to be formed as part of said second metal layer, such that: extending said power connection conductors disposed at least partially overlaid by said at least one power rail conductor so as to close at least one of said plurality gaps not having a routing connection conductor running therethrough, said steps implemented on a general purpose computer.