Patent ID: 7118925
Filing Date: 2006-10-10
Classification: H01F,H01L

Abstract:
1. A method of manufacturing an integrated circuit on a semiconductor wafer comprising: forming a FEOL structure over said semiconductor wafer; forming a first metal interconnect layer over said FEOL structure, said first metal interconnect layer containing a bottom plate of a capacitor and a bottom portion of an induction coil; forming an etch stop layer of a second metal interconn ect layer over said first metal interconnect layer; forming a ferromagnetic layer over said etch stop layer; forming a photoresist layer over said ferromagnetic layer; patterning said photoresist layer; etching said ferromagnetic layer to form a top plate of said capacitor and also a core that is proximate to said bottom portion of an induction coil; forming a dielectric layer of said second metal interconnect layer over said semiconductor wafer; and forming within said dielectric layer of said second metal interconnect layer a top portion of said induction coil plus vias that couple said top portion of said induction coil to said bottom portion of said induction coil.