Patent ID: 9000574
Filing Date: 2015-04-07
Classification: G06F,H01L

Abstract:
1. A semiconductor device, comprising: a first semiconductor chip having a main surface, a first side, a second side which intersects with the first side, and a plurality of the pads formed over the main surface thereof; a second semiconductor chip having a main surface, a first side, a second side which intersects with the first side, and a plurality of the pads formed over the main surface thereof; a chip mounting portion being mounted the first and second semiconductor chips; first and second leads being arranged nearby the chip mounting portion; a sealing body sealing the first and second semiconductor chips, the chip mounting portion and parts of the first and second leads; and wherein the first semiconductor chip includes: a first pad supplied with an external power supply voltage from the first lead; a regulator circuit which is electrically connected with the first pad and generates an internal power supply voltage by stepping down the external power supply voltage according to a reference voltage and an input voltage to be compared with this reference voltage; a second pad which is electrically connected to the regulator circuit and from which the internal power supply voltage is output; and a third pad which is electrically connected to an input part of the regulator circuit to which the input voltage is input; wherein the second semiconductor chip includes: a fourth pad to which the internal power supply voltage is input from the second pad; wherein the second semiconductor chip is mounted over the chip mounting portion such that the second side of the second semiconductor chip intersects with the first side of the first semiconductor chip in a plan view, wherein the second and third pads are arranged along the first side of the first semiconductor chip, wherein the fourth pad is arranged along the first side of the second semiconductor chip, wherein the second lead is arranged near the first side of the first semiconductor chip rather than the second side of the first semiconductor chip in the plan view, and wherein the second, third, and fourth pads are electrically connected to the second lead via a plurality of wires, respectively.