Patent ID: 6249481
Filing Date: 2001-06-19
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array having a plurality of memory cells arranged in rows and columns;counting means for receiving a clock signal, counting cycles of the clock signal and determining a location of a head of a data segment which is to be transmitted in or out;controlling means for fetching, in accordance with a count result of said counting means, a first control information segment which includes a control signal, a second control information segment which includes row address signals and a third control information segment which includes column address signals and for controlling an operation of inputting/outputting, in synchronism with the clock signal in a time-sharing manner, a plurality of data items stored in the memory cell array at addresses which are designated by the row address signals and the column address signals, a time at which the controlling means fetches the row addresses, a time at which the controlling means fetches the column addresses and a time at which the data items are input or output being sequentially determined by causing said counting means to count a predetermined number of cycles;specification means for decoding the row addresses included in the second control information segment fetched by the controlling means and also decoding the column addresses included in the third control information segment, thereby designating memory cells in the memory cell array; anddata input/output means for inputting a data segment into the memory cells designated by said specification means and outputting a data segment from the memory cells designated by said specification means, wherein both of said data segments are input/output in a time-sharing manner.