Patent ID: 6433786
Filing Date: 2002-08-13
Classification: G09G

Abstract:
A memory architecture for a video graphics controller comprising:a dynamic random access memory (DRAM) having a data port, an address decoder that can receive an address to select a memory location in said DRAM, and a command instruction bus that can receive instructions for data transfer; a static random access memory (SRAM) having a first data port to transfer data with said DRAM, a second data port to transfer data with a plurality of data requesters, a first address decoder that can receive an address to select a memory location in said SRAM for data transfer with said DRAM, a first read/write input that can receive a signal for data transfer with said DRAM, a second address decoder that can receive an address to select a memory location in a page of said SRAM to transfer data to one or more of said plurality of data requestors, and a second read/write input that can receive a signal for data transfers from another of said plurality of data requestors, wherein said SRAM is partitioned into portions, wherein each portion is allocated to a separate data requestor; and a bus coupled between said data port of said DRAM and said first data port of said SRAM for data transfer between said DRAM and said SRAM.