Patent ID: 6400603
Filing Date: 2002-06-04
Classification: G11C

Abstract:
An array of non-volatile floating gate memory cells arranged in a plurality of one or more rows and columns, a plurality of one or more of said cells electrically coupled to form a plurality of one or more pages, each of said cells having a first region, a spaced apart second region, a channel region between said first and second regions, a floating gate, and a control gate, said array comprising:a plurality of page-word lines, each said page-word line connects to said control gate of one or more of said memory cells in one of said pages; a plurality of page-source lines, each said page-source line connects to said second region of all of said memory cells in one of said pages; a plurality of bit lines, each said bit line connects to said first region of all of said memory cells in one of said memory-cell-columns; a plurality of control circuits arranged in rows and columns, each said control circuit selectively couples signals to said page-word lines and said page-source lines of said pages; a plurality of control-circuit-row lines, each said control-circuit-row line connects to all of said control circuits in a control-circuit-row, each said control-circuit-row line enables said selective coupling in all of said control circuits in said control-circuit-row; a plurality of word lines, one or more of said word lines connect to all of said control circuits in each of said control-circuit-columns, said plurality of word lines are selectively coupled to said page-word lines by said control circuits; a plurality of source lines, one or more of said source lines connect to all of said control circuits in each of said control-circuit-columns, said plurality of source lines are selectively coupled to said plurality of page-source lines by said control circuits.