Patent ID: 6455888
Filing Date: 2002-09-24
Classification: A61K,H01L

Abstract:
A group of memory cells, comprising:a first memory cell and a second memory cell, the first and second memory cells each including a poly silicon (poly I) layer, the poly I layers serving as floating gates; and a gap having gently sloped sidewalls to isolate the floating gate of the first memory cell from the floating gate of the second memory cell, the gap being formed by transforming an unmasked portion of the poly I layer into an electrically nonconductive medium via thermal oxidation and etching the electrically nonconductive medium so as to form the gap between the floating gate of the first memory cell and the floating gate of the second memory cell, wherein the slope of the gap sidewalls is such that a layer of material deposited over the floating gates and the gap will be substantially free of abrupt steps.