Patent ID: 6308251
Filing Date: 2001-10-23
Classification: G06F

Abstract:
A parallel processor apparatus comprising: data inputting means of a plurality of blocks each including a shift register having a plurality of first storage means connected in series so that pointer data is input to a first storage means of a first stage and so that the output of a first storage means of a previous stage is input to the first storage means of a latter stage, a plurality of second storage means provided corresponding to the plurality of first storage means, and a plurality of switching means provided corresponding to the plurality of first storage means and supply one partial data in a plurality of partial data constituting serial data to the corresponding ones of the plurality of second storage means at a timing corresponding to the output from the corresponding ones of the plurality of first storage means;a plurality of processing means provided corresponding to the plurality of second storage means and performing processing using the partial data stored in the corresponding second storage means;a plurality of detection circuits for detecting the input timing and output timing of pointer data in the data inputting means; anda switching circuit for connecting the data inputting means and serial data input line only in the period from the input to output of the pointer data detected by the detection circuit.