Patent ID: 7349288
Filing Date: 2008-03-25
Classification: G11C

Abstract:
1. An ultra high speed address decoder comprising: a number P first dynamic NOR logic gates each having a number M inputs coupled to one of a number P unique sets of M bits selected from a number N true and N complements of the N address bits and an output generating one of P bits of a first bit group having P unique combinations of one bit with a logic true state, wherein the first dynamic NOR logic gates have a dynamic node that is pre-charged when a clock signal has a logic zero state and evaluated to a Boolean combination of the M bits coupled to its inputs and a logic state of the output is latched when the clock signal has a logic one state; a number K second dynamic NOR logic gates each having (N−M) inputs coupled to one of K unique sets of (N−M) bits selected from the N true address bits and the N complements address bits and an output generating one of K bits of a second bit group having K unique combinations of one bit with a logic true state, wherein the second dynamic NOR logic gates have a dynamic node that is pre-charged when the clock signal has a logic zero state and evaluated to a Boolean combination of the (N−M) bits coupled to its inputs and a logic state of the output is evaluated to the logic state of the dynamic node when the clock signal has the logic one state and the output is a logic zero when the clock signal has the logic one state; and a number 2