Patent ID: 8482980
Filing Date: 2013-07-09
Classification: G11C,H01L

Abstract:
1. A memory device comprising: at least one memory array on a semiconductor substrate; each said memory array comprises a page control line, a plurality of page control transistors, a plurality of word lines, a plurality of bit lines, and a plurality of pages, each said page is arranged in a row comprising a plurality of bytes which couple to a page control transistor of the plurality of page control transistors with its drain terminal connected to the page control line and with its gate connected to the word line; each said byte includes at least one memory cell; said memory array further comprises a plurality of source control devices and source lines, said source control devices are configured to provide either predetermined biases or floating potentials to source lines, each said source line couples to all the bytes on the same byte segment of the memory array; wherein, said memory cell comprises a memory transistor and a bit select transistor without well bias; the source terminal of the memory transistor connects to the source line on the same byte segment, the gate terminal of the memory transistor connects to the source terminal of the page control transistor on the same row, and the drain terminal of the memory transistor connects to the source terminal of the bit select transistor in the memory cell; the gate terminal of the bit select transistor connects to the gate terminal of the page control transistor on the same row and the word line, and the drain terminal of the bit select transistor connects to a bit line which couples to all the memory cells on the same column of the memory array.