Patent ID: 6289412
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A process of generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive sub-circuits, the process comprising the steps of:receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of said cells including a plurality of polygons;identifying a plurality of repetitive cells of said input layout database, said repetitive cells being associated with the repetitive sub-circuits;recognizing at least one pattern of said repetitive cells;defining at least one cut region of said input layout database, said cut region being defined by physical layout coordinates, said cut region intersecting a corresponding pattern of said repetitive cells; andgenerating a synoptic layout database, said generating step including the sub-steps of,accessing at least a portion of said geometric objects of said input layout database, anddetermining relationships between each of said geometric objects and said cut region.