Patent ID: 7184503
Filing Date: 2007-02-27
Classification: H03L

Abstract:
1. A multi-loop circuit comprising: a first switching device, the first switching device receiving a first clock pulse and a second delayed pulse and producing a first output pulse comprising one of the first clock pulse and the second delayed pulse; a first delay device, the first delay device receiving the first output pulse and producing a first delayed pulse; a second switching device, the second switching device receiving a second clock pulse and the first delayed pulse and producing a second output pulse comprising one of the second clock pulse and the first delayed pulse; a second delay device, the second delay device receiving the second output pulse and producing the second delayed pulse; a third switching device, the third switching device receiving the first delayed pulse and the second delayed pulse and producing a first output signal; a fourth switching device, the fourth switching device receiving the first delayed pulse and the second delayed pulse and producing a second output signal; and a controller, the controller controlling the first switching device, second switching device, third switching device, and fourth switching device.