Patent ID: 6461925
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A method of manufacturing a heterojunction BiCMOS integrated circuit comprising:forming a gate electrode over a semiconductor substrate; forming a protective layer over the gate electrode and the semiconductor substrate, the protective layer having a hole, comprising the steps of; forming an insulating layer over the gate and the semiconductor substrate; forming an amorphous silicon layer over the insulating layer; and forming the hole in the protective layer; forming a semiconductor layer over the protective layer, the semiconductor layer comprised of a different semiconductor material than the semiconductor substrate; forming an electrically insulative layer over the semiconductor layer; doping a portion of a collector region in the semiconductor substrate; self-aligning a hole in the electrically insulative layer to the portion of the collector region; forming an electrically conductive layer over the semiconductor layer and the hole in the electrically insulative layer; defining an emitter region in the electrically conductive layer; and self-aligning an extrinsic base region in the semiconductor layer to the emitter region.