Patent ID: 6380593
Filing Date: 2002-04-30
Classification: G06F,H01L

Abstract:
A method for placement of substrate contacts and well-ties in a standard cell ASIC place and route flow comprising the steps of:(1) generating a plurality of standard cells, said standard cells comprising first standard cells including substrate contacts and/or well-ties and second standard cells not including substrate contacts and/or well-ties; (2) preliminarily placing a plurality of said standard cells for interconnection among said standard cells for a desired circuit function; (3) detecting where said preliminary placing of said standard cells violates a maximum spacing rule for substrate contacts; (4) replacing standard cells to remedy any detected violation of said maximum spacing rule for substrate contacts; (5) detecting where said preliminary placing of said standard cells violates a maximum spacing rule for well-ties; (6) replacing standard cells to remedy any detected violation of said maximum spacing rule for well-ties; (7) repeating steps (3) to (6) until no violations of either said maximum spacing rule for substrate contacts or said maximum spacing rule for well-ties is detected.