Patent ID: 7514792
Filing Date: 2009-04-07
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first wiring buried in a first interlayer insulation film; a second wiring formed above said first wiring and buried in a second interlayer insulation film; and a via plug electrically connecting said first wiring and said second wiring to each other and buried in a third interlayer insulation film, said first wiring and said via plug being electrically connected to each other, with a lower surface of said via plug being in contact with an upper surface of said first wiring and an upper surface of the first interlayer insulation film, and a side surface of said first wiring and a side surface of said via plug being in contact with each other, and said via plug and said second wiring being electrically connected to each other, with a lower surface of said second wiring being in contact with an upper surface of said via plug and an upper surface of the third interlayer insulation film, and a side surface of said via plug and a side surface of said second wiring being in contact with each other.