Patent ID: 6284613
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method of forming a T-gate used with a salicide process for a semiconductor devices, comprising the steps of:a) patterning an insulating layer to form a dummy gate over a substrate; said substrate having a substrate surface;said insulation layer is patterned by forming a dummy gate resist pattern over said insulating layer using a first gate optical mask; said dummy gate resist pattern is exposed using said first optical mask, and etching said insulating layer using said dummy gate resist pattern as an etch mask;b) forming LDD regions adjacent to said dummy gate by ion implanting (I/I) impurity ions into said substrate using said dummy gate as a mask;c) forming a pad oxide layer over said substrate surface;d) forming a dielectric layer over said pad oxide layer and said dummy gate and removing said dielectric layer from over said dummy gate;e) removing said dummy gate forming a gate opening exposing said substrate surface;f) forming a gate dielectric layer over said substrate surface in said gate opening;g) forming a gate layer over said dielectric layer and said substrate surface in said gate opening;h) patterning said gate layer to form a T-gate; said T-gate filling said gate opening and extending laterally over a portion of said dielectric layer;said gate layer is patterned by using a T-gate resist pattern formed by using said first gate optical mask by over exposing a resist layer through said first optical gate mask so that the T-gate resist pattern is between 60% and 100% wider than said dummy gate resist; andi) removing said dielectric layer and said pad oxide layer leaving said T-gate over said substrate.