Patent ID: 8711604
Filing Date: 2014-04-29
Classification: B82Y,G06F,G11C

Abstract:
1. A non-volatile semiconductor memory comprising: a data storage unit including a memory cell array that includes a plurality of memory cells and a writing circuit that performs an operation of writing write data to the memory cell array; an encoder that generates the write data from information data and directs the writing circuit to write the write data to the memory cell array; a writing determining circuit that determines whether the writing of the write data to the memory cell array within a predetermined number of writing operations fails or succeeds, inverts the write data to generate new write data when the writing of the write data fails, and directs the writing circuit to write the new write data to the memory cell array; a switching circuit that inverts read data which is read from the memory cell to generate new read data when the writing determining circuit determines that the writing of the write data fails; and a decoder that receives the read data which is read from the memory cell array through the switching circuit and decodes the read data into the information data.