Patent ID: 9152207
Filing Date: 2015-10-06
Classification: G06F,H04L,H04W,Y02D

Abstract:
1. A system for receiving a data packet from a source device and transmitting the data packet to a destination device, comprising: an input/output (I/O) pad for receiving the data packet from the source device; a wakeup source, coupled to the I/O pad, for processing the data packet, wherein the wakeup source initiates a wakeup sequence when the data packet includes a predetermined code, and transmits the data packet to the destination device; clock gating logic, coupled to the wakeup source, for switching on the wakeup source when the I/O pad receives the data packet and switching off the wakeup source when the I/O pad is idle for a first predetermined time period; and at least one buffer circuit, coupled between the I/O pad and the wakeup source, for delaying transmission of the data packet to the wakeup source by a second predetermined time period, wherein the wakeup source is switched on within the second predetermined time period.