Patent ID: 9159457
Filing Date: 2015-10-13
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a plurality of bit lines; a plurality of page buffers corresponding to the bit lines, respectively, and configured to each store a write data; and a control circuit configured to control at least one page buffer of the plurality of page buffers to store the write data of a first logic level and control other ones of the plurality of page buffers to store the write data of a second logic level, wherein the control circuit is further configured to select the at least one page buffer based on an address inputted to the control circuit, wherein the control circuit controls the write data stored in odd-numbered page buffers among the plurality of page buffers and the write data stored in even-numbered page buffers among the plurality of page buffers to have a different value by using one address bit of the address.