Patent ID: 7268025
Filing Date: 2007-09-11
Classification: G02F

Abstract:
1. A method of fabricating a pixel structure, comprising forming a gate electrode a gate line and a common line on a substrate, wherein the gate line is electrically connected to said gate electrode; forming a gate insulating layer on said substrate to cover said gate electrode, said gate line and said common line; forming a channel layer above said gate insulating layer and said gate electrode; simultaneously forming a data line on said gate insulating layer, a source electrode and a drain electrode on said channel layer, and a conducting layer on said gate insulating layer, said data line being electrically connected to said source electrode, said conducting layer including a coupling portion and a connecting portion, said coupling portion being formed above and overlapping said common line, said connecting portion connecting said coupling portion and said drain electrode; forming a passivation layer above said substrate covering said data line, said conducting layer, said source electrode and said drain electrode; forming a contact window in said passivation layer exposing said connecting portion; and forming a pixel electrode on said passivation layer, said pixel electrode being electrically connected to said conducting layer through said contact window.