Patent ID: 8242811
Filing Date: 2012-08-14
Classification: G06F,H03K,Y02D

Abstract:
1. A method for transmitting signals on a wire within a chip, comprising: receiving an input voltage signal; generating one or more modified voltage signals from the input voltage signal; driving each of the input voltage signal and the one or more modified voltage signals through a respective capacitor to a first end of the wire; combining a voltage signal on the output of each of the capacitors to obtain a combined voltage signal at the first end of the wire, wherein combining the voltage signals comprises combining the voltage signals so that the combined voltage signal at the first end of the wire has a predetermined first pulse shape so that a transmitted combined voltage signal at a second end of the wire comprises a return-to-zero (RZ) pulse with a predetermined second pulse shape; and transmitting the combined voltage signal from the first end of the wire to the second end of the wire, wherein transmitting the combined voltage signal comprises, when a consecutive data transition occurs for the combined voltage signal, combining two negative or two positive adjacent portions for the consecutive data transition to obtain twice a pre-emphasis for the combined adjacent portions than a pre-emphasis for the consecutive data transition when the adjacent portions are not combined.