Patent ID: 9018691
Filing Date: 2015-04-28
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory structure, comprising: a semiconductor substrate of a first conductivity type having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row along a first direction, wherein the first, second, and third OD regions are separated from one another by an isolation region, and wherein the isolation region comprises a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region; a select gate transistor on the first OD region, wherein the select gate transistor comprises a select gate extending along a second direction; and a floating gate transistor on the second OD region, the floating gate transistor comprising a first well of the second conductivity type that partially overlaps with the floating gate in the second OD region, wherein the first well encompasses the first intervening isolation region, wherein the floating gate transistor is serially coupled to the select gate transistor through the first well, and wherein the floating gate transistor comprises a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions, wherein the first well partially overlaps with the drain region in the first OD region, wherein a second well of the second conductivity type is provided in the semiconductor substrate, and wherein the second well encompasses the second intervening isolation region, wherein the first conductivity type is P type, the second conductivity type is P type, and the third conductivity type is N type, and wherein a deep N type region is provided in the semiconductor substrate to isolate the first and second wells of the second conductivity type.