Patent ID: 8654055
Filing Date: 2014-02-18
Classification: G09G,H03K

Abstract:
1. A gate driving circuit comprising: a first shift register having a first plurality of cascade-connected stages configured to sequentially output a plurality of first gate signals, each stage having a forward-input terminal and an output terminal, and receiving a first vertical start signal as its start signal at the forward-input terminal its first stage, and outputting the first gate signals based on its received start signal and a received first clock signal and a received second clock signal; and a second shift register having a second plurality of cascade-connected stages configured to sequentially output a plurality of second gate signals, each stage having a forward-input terminal and an output terminal, and outputting the second gate signals based on its received start signal and a received third clock signal and a received fourth clock signal, wherein the received start signal of the second shift register is delayed with respect to the received start signal of the first shift register, wherein the received second clock signal has a phase opposite to the received first clock signal, and wherein the received third clock signal is delayed by 2H with respect to the received first clock signal and the received fourth clock signal has a phase opposite to the received third clock signal.