Patent ID: 6507938
Filing Date: 2003-01-14
Classification: G06F

Abstract:
A method comprising:placing cells of a circuit design in a placement of an integrated circuit; analyzing the placement for timing performance comprising: routing wires between the cells to complete a layout of the integrated circuit having a plurality of nets and signal paths, each signal path comprising a sequential ordering of one or more of the nets and cells occurring alternately, each net and each cell being included in one or more of the signal paths; defining critical signal paths in the layout as being one or more of the signal paths having respective timing constraints; and for each net in the layout, calculating an effective delay caused by the net to a signal propagating through one of the critical signal paths having a slack that is less than a slack of other critical signal paths that also include the net comprising: calculating a slack for each critical signal path in the layout including the net; selecting one of the critical signal paths including the net and having a slack that is less than the slack of each other critical signal path that also includes the net; calculating an effective delay to a propagation of an input signal through the selected critical signal path caused by the net in the selected critical signal path; and selecting the effective delay caused by the net to the propagation of the input signal through the selected critical signal path as a delay caused by the net in the layout; and rearranging the cells to improve a timing performance of the integrated circuit based on the analysis of the placement.