Patent ID: 6803254
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method comprising:providing a substrate having a chip mounting region, a plurality of electrically conductive circuit patterns proximate to said chip mounting region, and an electrically conductive first transfer pattern that is separate from the circuit patterns; stacking a first semiconductor chip and a second semiconductor chip one over the other in the chip mounting region, the first and second semiconductor chips each including a plurality of conductive pads, with the conductive pads of the first semiconductor chip being oriented in a same direction as the conductive pads of the second semiconductor chip; electrically connecting a first end of a metal first wire to one of the conductive pads of the first semiconductor chip and an opposite second end of the first wire to the first transfer pattern; electrically connecting a first end of a metal second wire to one of the conductive pads of the second semiconductor chip and an opposite second end of the second wire to the first transfer pattern, whereby the first and second semiconductor chips are electrically connected through the first transfer pattern; and electrically connecting a first end of a metal third wire to another one of the conductive pads of the first or second semiconductor chips and an opposite second end of the third wire to one of the circuit patterns.