Patent ID: 6163181
Filing Date: 2000-12-19
Classification: H03K,H03L

Abstract:
A frequency divider circuit comprising:a first frequency divider including a plurality of first storage circuits connected in series and formed as a frequency divider being driven in response to an input signal as a first reference clock signal and dividing said input signal by a frequency division ratio selected by a frequency division ratio determining signal to produce a first divided signal;a second frequency divider including a plurality of second storage circuits connected in series and formed as a frequency divider,said second frequency divider being driven in response to said first divided signal as a second reference clock signal, each of said plurality of second storage circuits being supplied with the second reference clock signal, and dividing said first divided signal by a frequency division ratio corresponding to the number of said second storage circuits connected in series to produce a second divided signal; anda frequency division ratio determining means for producing said frequency division ratio determining signal on the basis of outputs of said second storage circuits of said second frequency divider.