Patent ID: 6862207
Filing Date: 2005-03-01
Classification: G11C

Abstract:
1. A memory cell comprising: a pass transistor, a pull-down transistor, a first power supply, a second power supply, a precharge circuit, and a decoder circuit, each transistor having a threshold voltage, a gate and a channel, the channel having a first end and a second end, the second end of the channel of the pass transistor coupled to the first end of the channel of the pull-down transistor, and the second end of the channel of the pull-down transistor coupled to a ground connection, the first end of the channel of the pass transistor coupled to the first power supply via the precharge circuit and the gate of the pass transistor coupled to the second power supply via the decoder circuit, the first power supply and the second power supply each having a different power supply voltages, wherein the ground connection is coupled to a global ground connection when a memory block comprising the memory cell is in an active mode, and the ground connection is a virtual ground connection when the memory block is in a standby mode.