Patent ID: 8265216
Filing Date: 2012-09-11
Classification: H04L

Abstract:
1. A data recovery circuit, comprising: a pulse width indicator circuit configured to receive, at an input, a data stream and provide, at respective outputs, pulses that are indicative of a logic level of respective data bits in the received data stream; an edge detection circuit having respective inputs coupled to the respective outputs of the pulse width indicator circuit, wherein the edge detection circuit is configured to receive, on the respective inputs, the pulses from the pulse width indicator circuit and provide, on respective outputs, respective storage signals responsive to the pulses; and a first storage having respective storage inputs coupled to the respective outputs of the edge detection circuit, wherein the first storage is configured to receive and store the respective storage signals, and wherein the pulse width indicator circuit includes a first inverter chain that detects positive pulses and a second inverter chain that detects negative pulses, wherein the first and second inverter chains each include a series of alternating imbalanced inverter stages.