Patent ID: 6225855
Filing Date: 2001-05-01
Classification: G05F,G11C

Abstract:
A reference voltage generation circuit comprising:load means having one end thereof connected to a higher voltage power supply line;an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of said load means, and a source thereof connected to a lower voltage power supply line; anda source follower circuit using an MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of said enhancement type n-channel MIS transistor and having an output end thereof connected to a gate of said enhancement type n-channel MIS transistor,wherein a reference voltage is obtained at the drain of said enhancement type n-channel MIS transistor, andwherein said source follower circuit comprises:a first depletion type p-channel MIS transistor having a source thereof connected to said higher voltage power supply line, and a gate thereof connected to the source; anda second depletion type p-channel MIS transistor having a source thereof connected to a drain of said first depletion type p-channel MIS transistor and to the gate of said enhancement type n-channel MIS transistor, a gate therof connected to the drain of said enhancement type n-channel MIS transistor, and a drain thereof connected to said lower voltage power supply line.