Patent ID: 6373286
Filing Date: 2002-04-16
Classification: G06F,H03K

Abstract:
An integrated circuit comprising first and second power supply buses with at least three circuits coupled via conductors, which each have a resistance, between the first and second power supply buses, each circuit comprising:an input and an output; a first capacitor having a first terminal coupled between the output terminal of the circuit and a first terminal of the circuit which is coupled to a conductor which couples the circuit to the first power supply bus; and a second capacitor having a first terminal coupled between the output terminal of the circuit and a second terminal of the circuit which is coupled to the conductor which couples the circuit to the second power supply bus wherein the resistance of each of the conductors between the circuits and the first power supply bus is substantially greater than the resistance of the first power supply bus, the resistance of each of the conductors between the circuits and the second power supply bus being essentially equal and being substantially greater than the resistance of the second power supply bus.