Patent ID: 7001811
Filing Date: 2006-02-21
Classification: G11C,H01L

Abstract:
1. A method comprising: fabricating a memory cell of a device, the memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type, wherein the body region, the source region, and the drain region are oriented in a first direction, wherein the body region and the source region form a first junction, wherein the body region and the drain region form a second junction, and wherein a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased; fabricating a transistor of the device, the transistor oriented in a second direction, wherein the second direction is not parallel to the first direction; and fabricating a halo implant within the transistor, wherein a halo implant is not fabricated in the memory cell.