Patent ID: 6052009
Filing Date: 2000-04-18
Classification: H03K

Abstract:
A D-type flipflop which is realized in an ECL or CML technique, comprising a first pair of transistors constituting a first semi-flipflop, supplying first logic signals at a first couple of logic connections, a second pair of transistors constituting a second semi-flipflop, supplying second logic signals at a second couple of logic connections, the two pairs being coupled together for jointly constituting a complete flipflop, the second couple of logic connections constituting internal outputs of the flipflop in a symmetrical mode, characterized in that the flipflop comprises a pair of two-transistor followers for supplying two output signal components from the internal outputs, and each of these two-transistor followers is having an enforcing transistor, and the base of the other transistor of the pair is connected to a test signal input.