Patent ID: 6838708
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. An ESD protection circuit, comprising: a VDD bus; a VSS bus; an IC pad; a PMOS transistor coupled to the IC pad and the VDD bus, and having a plurality of gate fingers, a plurality of source contacts, and a plurality of drain contacts; an NMOS transistor coupled to the IC pad and the VSS bus, and having a plurality of gate fingers, a plurality of source contacts, and a plurality of drain contacts; wherein the pitch of the PMOS is smaller than the pitch of the NMOS, with the pitch being defined as the distance between the center of a drain contact and the center of an adjacent source contact for the particular transistor; and wherein each gate finger has a length, and wherein the length of the gate fingers of the NMOS is greater than the length of the gate fingers of the PMOS.