Patent ID: 7113020
Filing Date: 2006-09-26
Classification: H03H

Abstract:
1. A monolithic capacitance multiplier circuit comprising: a first FET device for supplying a bias current, a gate terminal of said first FET device being connected to a source of bias voltage; a current source connected between a source of operating voltage and a drain terminal of said first FET device; a second FET device connected in cascode to said first FET device; a third FET device; a capacitor connected between drain terminals of said second and third FET devices; a current summing node, formed at a connection of a source terminal of said first FET device, said drain terminal of said second FET device, and one plate of said capacitor, at which a capacitive current flowing from said capacitor is summed with said bias current, a resulting total current flowing into said drain terminal of said second FET device; a control node, formed at a connection of said current source, a gate terminal of said second FET device, and a gate terminal of said third FET device; and an output node, formed at a connection of a drain terminal of said third FET device and the other plate of said capacitor.