Patent ID: 6500120
Filing Date: 2002-12-31
Classification: G01S,G10K

Abstract:
A receive beamformer in an ultrasound imaging system comprising a delay element including analog random access memory (RAM), wherein the delay element further comprises:a write shift register including a plurality of write shift register memory locations, the write shift register arranged as a circular shift register; an input line receiving an input analog electrical signal representing a received acoustic signal; a plurality of write switches connected to said input line, each of the write switches operably controlled by one of the plurality of write shift register memory locations of the write shift register, wherein, when a logical one is in a particular write shift register memory location, the write switch operably controlled by said particular write shift memory location is closed; a plurality of capacitive elements, each of the capacitive elements connected to one of the plurality of write switches, wherein, when a write switch is closed, the connected capacitive element stores a substantially instantaneous value of the received input electrical signal on the input line; a read shift register including a plurality of read shift register memory locations, the read shift register arranged as a circular shift register; a plurality of read switches, each of the read switches connected to one of the plurality of capacitive elements and operably controlled by one of the plurality of read shift register memory locations of the read shift register, wherein, when a logical one is in a particular read shift register memory location, the read switch operably controlled by said particular read shift memory location is closed; and an output line outputting an output analog electrical signal and connected to said plurality of read switches, wherein, when a read switch is closed, the value of the stored electrical signal on the connected capacitive element is read out to said output line; wherein the analog RAM is comprised of the input line, the plurality of write switches, the plurality of capacitive elements, the plurality of read switches, and the output line.