Patent ID: 8938586
Filing Date: 2015-01-20
Classification: G06F

Abstract:
1. A memory system comprising: a cache memory that stores write data using a sector unit; a nonvolatile semiconductor memory that performs data writing using a page unit and performs data erasing using a block unit which is twice, or a larger natural number times, as large as the page unit; and a controller that includes a first management table that manages, using a cluster unit which is a natural number times as large as the sector unit, data in the nonvolatile semiconductor memory, and a second management table that manages, using a track unit which is twice, or a larger natural number times, as large as the cluster unit, data in the nonvolatile semiconductor memory, wherein the controller includes a third management table that manages, using an address of a cluster unit, data stored in the cache memory, and a fourth management table that manages, using an address of a track unit, data stored in the cache memory, and the controller performs data flushing processing from the cache memory to the nonvolatile semiconductor memory when the number of track units registered in the cache memory exceeds a predetermined threshold.