Patent ID: 7362614
Filing Date: 2008-04-22
Classification: G11C

Abstract:
1. A non-volatile semiconductor storage apparatus comprising: a memory cell array including at least one memory cell unit in which multiple electrically rewritable non-volatile memory cell transistors are serially connected; multiple control gate lines connecting to a control terminal for the multiple memory cells; a bit line connecting to the memory cell unit; means for selecting the control gate line; means for selecting the bit line; an externally input single power supply terminal; and an externally input ground potential terminal, wherein, when stored data of the memory cell transistors is defined by binary of logics “1” and “0”, the threshold voltage of the memory cell transistors storing logic “1” is defined lower than the ground voltage while the threshold voltage of the memory cell transistors storing logic “0” is defined higher than the ground voltage and lower than externally input single power supply voltage, wherein, in accordance with an externally input command, the binary of logic “1” and logic “0”, the quadrature of logic “11”, logic “10”, logic “01” and logic “00” or more logic values are selectable for the stored data in the memory cell transistors and further comprising: multiple driving voltage supply lines for supplying a driving voltage to the corresponding control gate line; and a transfer gate connecting the multiple driving voltage supply lines to the corresponding control gate line in accordance with a select signal, wherein the select signal is defined at the externally input single power supply voltage when a reading operation is started and is self-boosted when the driving voltage to be supplied to the driving voltage supply lines rises to the single power supply voltage.