Patent ID: 6331949
Filing Date: 2001-12-18
Classification: G11C

Abstract:
A circuit for storing and latching defective address data representing an address of a defective portion occurring in a memory cell array of a nonvolatile semiconductor memory device having a redundant function, comprising:floating gate field effect transistors for storing defective address data, each floating gate field effect transistor being electrically erasable and programmable and having a control gate, a drain, and a source;a word line connected to the control gates of the floating gate field effect transistors;bit lines connected to the drains of the floating gate field effect transistors;a source line connected to the sources of the floating gate field effect transistors; andlatch means for latching the data stored in the floating gate field effect transistors,wherein each floating gate field effect transistor assumes one of a high-threshold state and a low-threshold state, and has a threshold of 0 volts or less when in the low-threshold state.