Patent ID: 6148357
Filing Date: 2000-11-14
Classification: G06F

Abstract:
An integrated circuit comprising:a central processing unit (CPU);a memory controller circuit for interfacing to a system memory;an interconnect bus controller for interfacing to an interconnect bus, the interconnect bus controller coupled to transfer data in asynchronous priority mode during a first part of a predetermined time period, the first part being at the beginning of the predetermined time period and wherein in asynchronous priority mode, asynchronous traffic is transferred preferentially over isochronous traffic, the interconnect bus controller being coupled to selectively switch to isochronous priority mode during another part of the predetermined time period after the asynchronous priority mode, according to an amount of isochronous data remaining to be transferred during the predetermined time period; and whereinthe CPU and the memory controller circuit are coupled to the interconnect bus controller.