Patent ID: 6791860
Filing Date: 2004-09-14
Classification: G11C

Abstract:
A read-only memory including a plurality of word lines and K memory banks, each word line being parallel to each other and one of the K memory banks being an nth memory bank, the nth memory bank comprising:a first main bit line BL(n); a first selecting line and a second selecting line, which are perpendicular to the first main bit line BL(n); a plurality of first selecting switches and a plurality of second selecting switches that are controlled by the first selecting line and second selecting line respectively; a first sub-bit line SB1(n), a second sub-bit line SB2(n), a third sub-bit line SB3(n), and a fourth sub-bit line SB4(n), wherein when the first selecting switches are turned on, the first main bit line BL(n) is electrically connected to the second sub-bit line SB2(n) and the third sub-bit line SB3(n); when the second selecting switches are turned on, the first main bit line BL(n) is electrically connected to the third and fourth sub-bit lines SB3(n) and SB4(n) respectively; a plurality of first auxiliary switches and a plurality of second auxiliary switches, wherein the first auxiliary switches are controlled by a first auxiliary line SL1 and the second auxiliary switches are controlled by the second auxiliary line SL2, and wherein at least some of the first and the second auxiliary switches have low threshold voltage; and a plurality of memory cells, which are controlled by a plurality of word lines, and each memory cell is connected between two adjacent sub-bit lines; wherein when a current flows through one of the memory cells, the current at least flow through one of the first or the second auxiliary switches that are turned on.