Patent ID: 8209652
Filing Date: 2012-06-26
Classification: H01L

Abstract:
1. A semiconductor device including a decoupling capacitor, the device comprising: a main power voltage supplying line arranged in a first direction and configured to supply a power voltage; a main ground voltage supplying line arranged in the first direction and configured to supply a ground voltage; a plurality of decoupling capacitor cells arranged between the main power voltage supplying line and the main ground voltage supplying line in the first direction and in a second direction perpendicular to the first direction, and configured to reduce power noise generated by the power voltage and the ground voltage; a plurality of sub power voltage supplying lines connected to the main power voltage supplying line and arranged in the second direction in borders of the plurality of decoupling capacitor cells and configured to supply the power voltage to the plurality of decoupling capacitor cells; and a plurality of sub ground voltage supplying lines connected to the main ground voltage supplying line and arranged in a grid form defined by the first and second directions in the borders of the plurality of decoupling capacitor cells and configured to supply the ground voltage to the plurality of decoupling capacitor cells, wherein each of the plurality of decoupling capacitor cells has a first active region and a second active region, the first active region disposed to receive the ground voltage, the second active region disposed to receive the power voltage and to avoid a region where an inversion is formed in the decoupling capacitor, wherein the plurality of decoupling capacitor cells further comprises: