Patent ID: 6403423
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method for defining gate conductors in both array and support device regions of a semiconductor integrated circuit, comprising:(a) forming a gate conductor stack on a surface of a gate dielectric, said gate dielectric is formed on a surface of a semiconductor substrate having at least one array device region and at least one support device region; (b) forming a first gate dielectric cap on at least the gate conductor stack in said at least one array device region; (c) selectively patterning and etching the first gate dielectric cap in said at least one array device region, said first gate dielectric cap not being present in said at least one support device region after said etching; (d) forming a second gate dielectric cap on all exposed surfaces in said at least one array device region and in said at least one support device region, said second gate dielectric cap being thinner than said first gate dielectric cap; (e) selectively etching said second gate dielectric cap in said at least one array device region and in said at least one support device region, wherein said second etched gate dielectric cap in said at least one support device region serves as a gate conductor mask; and (f) simultaneously etching exposed surfaces of said gate conductor stack in both said at least one array device region and said at least one support device region stopping on said gate dielectric, wherein said simultaneous etching provides a plurality of patterned gate stacks in both said at least one array device region and said at least one support device region.