Patent ID: 6457166
Filing Date: 2002-09-24
Classification: G06F

Abstract:
A logic synthesis constraint generating device for generating a delay constraint for a logical circuit having a hierarchical structure of blocks, comprising:input means for receiving information describing features of a logical circuit including a hierarchical structure of blocks of the logical circuit, an internal delay of each block, and a delay between each of the blocks, and for receiving a delay distributing constraint of the logical circuit, and target library information of the logical circuit; storing means for storing the received information, the delay distributing constraint, and the target library information; timing analyzing means for performing a timing analysis using the information describing the features of the logical circuit and the delay distributing constraint of the logical circuit; and delay constraint distributing means for distributing the delay distributing constraint of the logical circuit as logic synthesis delay constraints among the blocks of the logical circuit by subtracting a delay not to be optimized of the circuit from the delay distributing constraint and distributing a remaining amount of the delay distributing constraint to the blocks of the logical circuit in proportion to their respective internal delays.