Patent ID: 6185667
Filing Date: 2001-02-06
Classification: G06F

Abstract:
A parallel processor, comprising:a plurality of processing elements (PEs) arranged in an array to form a PE array having a plurality of rows and columns, such that each PE has a north neighbor, a south neighbor, a west neighbor and an east neighbor, further wherein said PE array encompasses a plurality of sections, each section containing a group of PEs;logic, within each PE, for generating an output signal;a command generator for broadcasting a control word into the array, wherein said control word is received by each said PE within said array, and is used by each said PE to govern the manner in which it processes information; andat least one section OR logic, each for computing for one section, the logical OR of said PE output signals generated only by PEs within said one section, wherein the logical OR of said PE output signals generated only by PEs within said at least one section indicates whether any of said PEs within said at least one section generated a signal having a predetermined value.