Patent ID: 8338919
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having an n-channel type transistor region and a p-channel type transistor region; an element isolation region formed in said semiconductor substrate, said element isolation region defining an n-MOS active region in said n-channel type transistor region and a p-MOS active region in said p-channel type transistor region; an n-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said n-MOS active region and defining an n-MOS channel region under said n-MOS gate electrode structure; a p-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said p-MOS active region and defining a p-MOS channel region under said p-MOS gate electrode structure; a first contact etch stopper film having a tensile stress, formed above said semiconductor substrate and covering said n-channel type transistor region and at least first portions of said element isolation region in said p-channel type transistor region on both sides of the p-MOS active region in gate width direction; and a second contact etch stopper film having a compressive stress, formed above said semiconductor substrate and covering said p-MOS active region between portions of the first contact etch stopper film covering said at least first portions of said element isolation region; and wherein said first contact etch stopper film exerts a tensile stress on said n-MOS channel region along a gate length direction, said second contact etch stopper film above said p-MOS active region exerts a compressive stress on said p-MOS channel region along a gate length direction, and said portions of the first contact etch stopper film above said element isolation region in said p-channel type transistor region and said second contact etch stopper film above said p-MOS active region exert a tensile stress on said p-MOS channel region along a gate width direction.