Patent ID: 7676621
Filing Date: 2010-03-09
Classification: G06F

Abstract:
1. A computer system comprising: a system bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the system bus and to a first internal bus; a send machine coupled between a host processor and the bus controller over a second internal bus; a first first-in first-out (FIFO) buffer coupled to the send machine, the first FIFO further coupled in parallel with the send machine between the host processor and the bus controller over the first internal bus but not over the system bus; a receive machine coupled between the host processor and the bus controller, the receive machine comprising means for generating a message checksum for a message while the message is being received by the bus controller over the system bus; and a second FIFO buffer coupled to the receive machine and coupled between the host processor and the bus controller.