Patent ID: 6359827
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A memory device comprising:an address pipeline, said pipeline receiving address signals corresponding to a memory location and decoding the address signals into a word line address, said address pipeline driving an activation signal on a word line corresponding to said word line address; and a memory core having a memory array, said memory core receiving said activation signal and accessing memory cells from its memory array at said memory location, said address pipeline comprising a decode circuit, said decode circuit decoding the address signals into said word line address and driving said activation signal on said word line, and first and second pipeline stages, said first pipeline stage receiving the address signals and outputting them to said second pipeline stage, said second pipeline stage receiving the address signals from said first pipeline stage and outputting them to said decode circuit, said memory core comprising: a third pipeline stage connected to said decode circuit by a plurality of first word lines, said third pipeline stage receiving said activation signal on said word line corresponding to said word line address and outputting a pipelined activation signal on one of a plurality of second word lines, and wherein said memory array receives said pipelined activation signal from said third pipeline stage and accesses said memory cells based on said pipelined activation signal.