Patent ID: 6433602
Filing Date: 2002-08-13
Classification: H03K

Abstract:
A CMOS Schmitt Trigger device comprising:an input stage forming an inverter, having a pair of input stage CMOS devices, for receiving an input signal; and an output stage, having a first output stage device in parallel with the input stage, the first output stage device having a pair of first output stage CMOS devices coupled to the input stage CMOS devices such that the pair of first output stage CMOS devices add to the respective input stage CMOS devices only one at a time for changing the trip point of the Schmitt Trigger device, and having a second output stage device connected to the first output stage device for driving an output node; the input stage further includes a first p-channel MOSFET having a first p-channel width, and a first n-channel MOSFET having a first n-channel width, wherein a gate electrode of each said first p-channel MOSFET and said first n-channel MOSFET is individually connected to a device input trace, a source electrode of each said first p-channel MOSFET and said first n-channel MOSFET is connected to a source of electrical potential, and drain electrodes of each said first p-channel MOSFET and said first n-channel MOSFET are connected in series such that said first p-channel MOSFET and said first n-channel MOSFET form said inverter: and the output stage includes a second p-channel MOSFET having a second p-channel width, and a second n-channel MOSFET having a second n-channel width, wherein a gate electrode of said second p-channel MOSFET is connected to the gate of said first p-channel MOSFET and a gate electrode of said second n-channel MOSFET is connect to the gate electrode of said first n-channel MOSFET, and drain electrodes of each of said second p-channel MOSFET and second n-channel MOSFET are connected in series and to the drain electrodes of the first p-channel MOSFET and the first n-channel MOSFET, and a source electrode of said second p-channel MOSFET and second n-channel MOSFET is connected to a source of potential such that the second p-channel MOSFET and the second n-channel MOSFET form a second stage of said inverter; wherein the output stage has a third p-channel MOSFET having a third p-channel width, and a third n-channel MOSFET having a third n-channel width, wherein a gate electrode of each said third p-channel MOSFET and third n-channel MOSFET is separately connected to said output node, a source electrode of each said third p-channel MOSFET and third n-channel MOSFET is separately connected to said source of electrical potential, and a drain of each said third p-channel MOSFET and third n-channel MOSFET is respectively connected to a source electrode of said second p-channel MOSFET and second n-channel MOSFET, wherein the third n-channel width is approximately twice the second n-channel width, and the third p-channel width is approximately twice the second p-channel width.