Patent ID: 7486584
Filing Date: 2009-02-03
Classification: G11C

Abstract:
1. A semiconductor memory device in which refresh operation for a memory cell array including a plurality of memory cells is performed, comprising: refresh control means for switchingly controlling a first refresh mode in which access to the memory cell array from outside is prohibited while retaining data and a second refresh mode in which access to the memory cell array from outside is permitted while retaining data and for performing the refresh operation of the memory cells corresponding to a selected word line; and designating means for individually designating a portion to be refreshed in the first refresh mode and a portion to be refreshed in the second refresh mode, wherein, in controlling the first or second refresh mode, said refresh control means performs the refresh operation when the portion to which the selected word line belongs is designated to be refreshed, and does not perform the refresh operation when the portion to which the selected word line belongs is not designated to be refreshed.