Patent ID: 6789223
Filing Date: 2004-09-07
Classification: G01R,G06F

Abstract:
A method to produce a set of vectors for use in testing a digital integrated circuit (IC) having a plurality of gates, each gate having at least one input pin and one output pin, each said pin definable as a fault site and said IC is definable as having branch depths and branch widths, the method comprising:for each said fault site, determining a delay metric that identifies the longest delay accumulated in a forward direction and in a reverse direction through said IC; wherein said delay metric is obtained by calculating and assigning an accumulated forward direction delay value and an accumulated reverse direction delay value through each said fault site for each said gate; for each said fault site, summing accumulated forward direction delay value and reverse direction delay value to provide a measure of maximum delay through each said fault site in said IC; wherein data associated with said measure of maximum delay is useable to define a longest physical path through said IC associated with said maximum delay; and iteratively using a set of longest physical paths defined by said measure of maximum delay to generate said set of vectors; wherein said set of vectors is useable by a tester apparatus to physically test said IC.