Patent ID: 9025407
Filing Date: 2015-05-05
Classification: G11C

Abstract:
1. An apparatus comprising: a first operational amplifier having a non-inverting input, an inverting input, and an output, wherein the non-inverting input is configured to receive a first reference voltage; a first N-type insulated-gate field effect transistor (IGFET) having a gate, a drain, and a source, wherein the gate of the first N-type IGFET is coupled to the output of the first operational amplifier; a first voltage divider having a first end, a second end, and at least one tap, wherein the first end is coupled to the source of the first N-type IGFET and the at least one tap is coupled to the inverting input of the first operational amplifier; a first buffer amplifier having an input and an output, wherein the input is coupled to the gate of the first N-type IGFET; a second buffer amplifier having an input and an output, wherein the input is coupled to the source of the first N-type IGFET; a second N-type IGFET having a gate, a drain, and a source, wherein the gate of the second N-type IGFET is operatively coupled to the output of the first buffer amplifier in a first mode; and a P-type IGFET having a gate, a drain, and a source, wherein the gate of the P-type IGFET is operatively coupled to the output of the second buffer amplifier in the first mode, wherein the source of the P-type IGFET is coupled to the source of the second N-type IGFET and to an output node, wherein the output node is configured to provide a bias for a memory access line.