Patent ID: 6888366
Filing Date: 2005-05-03
Classification: G01R,G06F

Abstract:
1. A semiconductor chip test system, comprising: a tester having a plurality of data input/output pins for inputting/outputting data through the plurality of data input/output pins; a plurality of semiconductor chips to be tested by the tester; and a control circuit for sequentially outputting the data output from each of the plurality of semiconductor chips to the tester during a read operation and supplying the data input from the tester to the plurality of semiconductor chips during a write operation, wherein the control circuit, comprises: a clock signal generating means for generating a first clock signal in response to a rising edge of a clock signal input from the tester and generating a second clock signal in response to a falling edge of the clock signal input from the tester; a control signal generating means for generating a read command and a write command by inputting a command input from the tester; a read control signal generating means for sequentially generating a plurality of a read control signals in response to the read command and the second clock signal; a write control signal generating means for generating a write control signal in response to the write command; a read data control means for sequentially outputting the output data from each of the plurality of semiconductor chips in response to the plurality of read control signals to the tester; and a write data control means for simultaneously outputting the data input from the tester to the plurality of semiconductor chips in response to the write control signal.