Patent ID: 6292025
Filing Date: 2001-09-18
Classification: H03K

Abstract:
An integrated circuit device comprising:a first power supply terminal to which a first fixed potential is supplied;a second power supply terminal to which a second fixed potential is supplied;a third power supply terminal to which a third fixed potential that can be powered down is supplied;an output terminal;a first conductivity type MOS transistor having its source and backgate connected to said second power supply terminal, and its drain connected to said output terminal;a second conductivity type MOS transistor having its drain connected to said output terminal, and its backgate and source connected to said first power supply terminal;a potential difference detector connected to said second power supply terminal and said third power supply terminal for detecting a potential difference between them; anda CMOS level converter for converting outputs of said potential difference detector, and for supplying a converted signal to at least one of a gate of said first conductivity type MOS transistor and a gate of said second conductivity type MOS transistor.