Patent ID: 8115253
Filing Date: 2012-02-14
Classification: H01L

Abstract:
1. An ultra high voltage metal-oxide-semiconductor (MOS) transistor device, comprising: a substrate having a first conductive type; a first well having a second conductive type formed in the substrate; a drain region having the second conductive type formed in the first well; a source region having the second conductive type formed in the substrate; an insulating layer formed on a surface of the first well; a first recess formed in the substrate, the insulating layer being formed in the first recess; a second recess formed in the substrate in the first well, wherein the first recess is formed in the substrate between the source region and the second recess; a gate positioned in the first recess and extending to cover a portion of the insulating layer; and a recessed channel region formed in the substrate under the gate and under a bottom of the first recess.