Patent ID: 8089298
Filing Date: 2012-01-03
Classification: G06F,G11C,H03K

Abstract:
1. An integrated circuit device comprising: a set of data inputs; a set of termination circuits coupled respectively to the data inputs, each termination circuit having a plurality of controllable termination impedance configurations; a termination control signal input to receive an indication that the integrated circuit device is to apply one of the controllable termination impedance configurations at each of the data inputs; and logic to apply one of a first and a second of the controllable termination impedance configurations at the data inputs based on the indication received at the termination control signal input and an internal state of the integrated circuit device, such that during a first internal state corresponding to the reception of write data on the data inputs, the first of the controllable termination impedance configurations is applied at each of the data inputs, and during a second internal state following the first internal state, the second of the controllable termination impedance configurations is applied at each of the data inputs.