Patent ID: 6338154
Filing Date: 2002-01-08
Classification: G11C

Abstract:
An apparatus for generating memory addresses in a dynamic memory testing circuit for testing a dynamic memory using all available addresses of the dynamic memory, comprising:a single N-bit binary counter for performing counting operation and for generating a first sequence of N-bit counted value words as addresses used by the dynamic memory, wherein N is the number obtained by adding the number of bits of the row address of the dynamic memory to the number of bits of the column address of the dynamic memory, values of counted value words in the first sequence of counted value words changing in succession in a first direction; inverting means for inverting the counted value words to generate a second sequence of N-bit inverted value words, values of inverted value words in the second sequence of inverted value words changing in succession in a second direction opposite to the first direction, such that the first and second sequences of words changing in the first and second directions are generated using the single counter; and first selecting means for selectively forwarding to the dynamic memory one of an inverted value word from the second sequence and a counted value word from the first sequence in response to a first select signal used to control the first selecting means.