Patent ID: 6492228
Filing Date: 2002-12-10
Classification: G11C,H01L

Abstract:
A method of forming a memory cell comprising the steps of:forming a first floating gate region on a silicon substrate; forming a second floating gate region on said silicon substrate; said second floating gate region being adjacent to and electrically isolated from said first floating gate region; forming an insulating layer over said first and second floating gate regions; forming a control gate region over said insulating layer and over said first and second floating gate regions; forming source and drain regions in said substrate such that said first and second floating gate regions are located at least in part between said source and drain regions; forming an electrically conductive region extending from a position adjacent to at least one of said first and second floating gate regions to at least one of said source and drain regions such that said electrically conductive region is coupled to a dielectric region located on a sidewall of said at least one of said first and second floating gate regions; and forming electrical interconnects with said source, drain and control gate regions.