Patent ID: 7482835
Filing Date: 2009-01-27
Classification: H03K

Abstract:
1. An integrated circuit including a field programmable gate array (FPGA), the FPGA comprising: a plurality of FPGA tiles, each FPGA tile including a plurality of functional groups (FGs) arranged in rows and columns, each of the FGs being configurable to receive regular input signals, perform a logic operation, and generate regular output signals; a regular routing structure in each FPGA tile coupled to the FGs and configurable to receive the regular output signals, route signals within the FPGA tile, and provide the regular input signals to the FGs; a plurality of interface groups (IGs) surrounding the plurality of FGs in each FPGA tile such that one IG is positioned at each end of each row and column, each of the IGs being coupled to the regular routing structure and configurable to transfer signals from the regular routing structure to outside of each of FPGA tile, at least one IG for each FPGA tile coupled to at least one IG of at least one other FPGA tile, each of the IGs having a plurality of input multiplexers configurable to select signals received from outside of the FPGA tile and provide signals to the regular routing structure inside the tile; and a plurality of input/output pads (I/Os) coupled to at least one of said input multiplexers of at least one of said IGs.