Patent ID: 6570947
Filing Date: 2003-05-27
Classification: H03L

Abstract:
A phase lock loop comprising:a controlled oscillator, adapted to receive a control signal and to provide an output signal ICOS having a frequency Fico, Fico is responsive to the control signal; a frequency divider, coupled to the controlled oscillator, for receiving ICOS and producing an output signal PD, having a frequency Fpd, wherein Fpd=Fico/N; a phase detector, adapted to receive a reference clock signal REF, having frequency Fref, the phase detector is coupled to the frequency divider, for producing an error signal ER proportional to the phase difference between REF and PD; and an adjustable converter, coupled to the phase detector and to the controlled oscillator, for receiving ER and providing to the controlled oscillator a control signal representative of a product of ER and a reference signal such that Fico is within a local range and Fref is statistically located in the middle of the local range.