Patent ID: 8406034
Filing Date: 2013-03-26
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a plurality of first word lines extending in a first direction and arranged having a certain pitch in a second direction orthogonal to the first direction; a plurality of bit lines extending in the second direction and arranged having a certain pitch in the first direction, the bit lines being configured to intersect the first word lines such that a first surface of the bit lines faces the first word lines; a resistance varying material disposed at respective intersections of the first word lines and the bit lines; a plurality of second word lines extending in the first direction and arranged having a certain pitch in the second direction, the second word lines being configured to intersect the bit lines so as to face a second surface of the bit lines, the second surface of the bit lines being on an opposite side of the first surface of the bit lines; and an insulating film disposed at respective intersections of the second word lines and the bit lines, one of the first word lines and one of the second word lines having a position substantially identical in the second direction and being disposed so as to sandwich the bit lines, the second word lines, the bit lines, and the insulating film configuring a field-effect transistor at respective intersections of the second word lines and the bit lines, the field-effect transistor having one of the second word lines as a control electrode and one of the bit lines as a channel region, and the field-effect transistor and the resistance varying material configuring one memory cell.