Patent ID: 9018045
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A method for fabricating a microelectronic package, comprising: encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body, the outer molded body having a portion circumscribing the core redistribution layers; producing one or more topside redistribution layers over the core redistribution layers; and forming a contact array over the topside redistribution layers and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers; wherein the first semiconductor die is embedded within an inner molded body, wherein encapsulating comprises forming an outer molded body around the inner molded body and the core redistribution lavers, and wherein a second semiconductor die is embedded within the inner molded body and electrically interconnected with the first semiconductor die by the core redistribution layers.