Patent ID: 6586312
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A method for improving the charge storage capacity of a DRAM capacitor comprising the steps of:providing a pre-processed semi-conducting structure having a gate structure formed on top, depositing a first layer of a BPTEOS oxide material on top of said gate structure, depositing a first layer of a PETEOS oxide material on top of said layer of BPTEOS oxide material, depositing a second layer of a BPTEOS oxide material on top of said first layer of PETEOS oxide material, depositing a second layer of PETEOS oxide material on said second layer of BPTEOS oxide, anisotropically etching by a reactive ion etching method a contact hole having substantially vertical sidewalls exposing edges of said PETEOS oxide and BPTEOS oxide layers, wet etching said semi-conducting structure with an etchant which has a sufficiently high etch selectivity toward said PETEOS oxide layers such that a zig-zag sidewall is formed in said contact hole, and depositing and forming subsequent polysilicon and dielectric layers forming said DRAM capacitor.