Patent ID: 6111835
Filing Date: 2000-08-29
Classification: G11B

Abstract:
A partial response maximum likelihood decoder comprising:branch metric calculator for receiving an input bit sequence having a multi-level multi-state characteristic precoded in a particular channel code and producing a set of branch metrics corresponding in number to amplitude levels which the input bit sequence assumes;add/compare/select (ACS) circuitry including a plurality of ACS circuits, a plurality of adders and a plurality of unit delay elements connected respectively to the ACS circuits and the adders, the ACS circuitry being arranged to respond to a channel code indication indicating a type of said particular channel code such that, when said particular channel code is of a first type, the ACS circuits and the associated unit delay elements combine to produce a first path indication and most recent path metrics from the branch metrics and previous path metrics, and when said particular channel code is of a second type, the ACS circuits, the adders and the associated unit delay elements combine to produce a second path indication and most recent path metrics from the branch metrics and previous path metrics; anda path memory responsive to said first and second path indications and said channel code indication for producing an output bit sequence.