Patent ID: 6026022
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array in which a plurality of memory cells corresponding to pluralities of bits, pages, and addresses are arranged in a matrix;a plurality of word lines each commonly connected to the memory cells of a corresponding page;a plurality of digit lines each commonly connected to the memory cells of a corresponding bit and address;data setting means for inverting input data of a plurality of bits in an erase mode and directly outputting input data in a write mode;data latch means for latching data output from said data setting means in correspondence with a bit and address designated by an address signal;row selection means for selecting a word line corresponding to a page designated by an address signal out of said word lines upon reception of a simultaneous write start signal;write means for selecting a digit line in accordance with an output from said data latch means upon reception of the simultaneous write start signal; andcontrol means for reading out data in accordance with an external instruction, controlling the write and erase modes, and outputting the simultaneous write start signal after input data to a plurality of addresses are sequentially latched by said data latch means.