Patent ID: 6862222
Filing Date: 2005-03-01
Classification: G11C

Abstract:
1. A method for performing an erase verification operation on a non-volatile memory device having a plurality of blocks of memory each having groups of memory sub-blocks, each memory sub-block comprising a plurality of memory cells and an erase indication register, the method comprising: loading a memory sub-block start address of a first memory sub-block having an erase indication register that indicates the first memory sub-block is not erased; sequentially reading the plurality of memory cells of the memory sub-block; if a first memory cell is not erased, storing an address of the first memory cell into a verification address pointer for the memory sub-block; if the first memory cell is not erased, jumping to a second memory sub-block; if the first memory cell is erased, sequentially reading the plurality of memory cells until either an end of the first memory sub-block occurs or a second memory cell is not erased; and if the end of the first memory sub-block occurs with each of the plurality of memory cells erased, setting the erase indication register to indicate that the first memory sub-block is erased.