Patent ID: 9037893
Filing Date: 2015-05-19
Classification: G06F,H04B,H04J

Abstract:
1. An apparatus for interfacing a digital core with at least one physical interface, comprising: a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate, the first clock configured to: physical interface circuitry having a second data input coupled to the data output of the macro, and a reset sampling input coupled to the sync reset output of the macro, the physical interface circuitry comprising a clock generator and clocked by a second clock having a second clock rate, and a third clock having a third clock rate, the second clock clocking data in from the macro into the physical interface, and the third clock sampling the synchronized reset signal from the macro at a rate greater than a rate of the first and second clocks, wherein when a transition is detected on the synchronized reset signal the clock generator resets the second clock to a predetermined state.