Patent ID: 6504756
Filing Date: 2003-01-07
Classification: G11C,H01L

Abstract:
A method of operating a memory cell comprising at least one floating gate region, a control gate region, active doped regions, a word line connected to said control gate region, first and second digit lines respectively connected to said active doped regions, and an electrical interconnect between one of said digit lines and at least one of said active doped regions which connects with a sidewall of said at least one floating gate region through a sidewall insulator to form a capacitor across said sidewall insulator between said at least one floating gate region and said at least one active region, said method comprising the steps of:(a) controlling the selective storage of charges in said at least one floating gate region to store a value in said memory cell, said connection of said electrical interconnect with said sidewall assisting in storing charge in said floating gate region by increasing capacitance between said at least one floating gate region and said at least one active region; and (b) selectively reading the charges stored in said floating gate region and using the read charges to determine a value stored in said memory cell.