Patent ID: 6762958
Filing Date: 2004-07-13
Classification: G11C

Abstract:
A semiconductor memory, comprising:a memory cell array having a multiplicity of word lines, a multiplicity of bit lines, and a multiplicity of memory cells each connected to one of said word lines and to one of said bit lines, said word lines having an active level at which memory cell access is possible and a nonactive level at which memory cell access is not possible; a control device connected to said word lines; at least one sense amplifier; said bit lines being disposed in pairs and each two of said bit lines being connected to a respective sense amplifier; a reference sense amplifier; first and second reference bit lines each switchably connected to a respective terminal to carry a mutually different reference potential, said first and second reference bit lines being connected to said reference sense amplifier; and a comparison device having an input connected to at least one of said reference bit lines and an output connected to said control device, said comparison device generating a control signal causing said control device to apply the nonactive level to said word lines.