Patent ID: 8811559
Filing Date: 2014-08-19
Classification: H03L,H04L

Abstract:
1. A timing recovery circuit for controlling a timing of latching a received data signal, the timing recovery circuit being allowed to switch between a first operation mode and a second operation mode, the circuit comprising: a clock generation circuit configured to generate n clock signals having phases separated by T/n from each other, where T is the period of the n clock signals, n is an integer of D or more, and D is an integer of two or more, wherein the period T is D times as long as the 1-bit length of the data signal in the first operation mode and is equal to the 1-bit length of the data signal in the second operation mode; at least D phase interpolation circuits each configured to select two of the n clock signals as a first and a second clock signal, and generate a sample timing signal having a phase adjusted to fall between the phases of the first and second clock signals in the first operation mode, and output one of the first and second clock signals as a sample timing signal in the second operation mode; a plurality of sampler circuits provided, respectively corresponding to the at least D phase interpolation circuits, and each configured to latch the data signal in synchronization with the sample timing signal output from a corresponding one of the at least D phase interpolation circuits; and a phase control circuit configured to determine the phases of the sample timing signals based on outputs of the plurality of sampler circuits, and instruct the at least D phase interpolation circuits to select the first and second clock signals based on the result of the phase determination, and instruct the at least D phase interpolation circuits to adjust the phases of the sample timing signals in the first operation mode, and to select one of the first and second clock signals in the second operation mode.