Patent ID: 8106458
Filing Date: 2012-01-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first complementary metal-oxide-semiconductor (CMOS) circuit located on a semiconductor-on-insulator (SOI) substrate, wherein said first CMOS circuit comprises at least one first n-FET and at least one first p-FET; a second CMOS circuit located on said SOI substrate, wherein said second CMOS circuit comprises at least one second n-FET and at least one second p-FET, wherein said SOI substrate includes: a first voltage applicator configured to electrically bias said at least one first n-FET and said at least one first p-FET by applying a first common substrate bias voltage to said first substrate region; and a second voltage applicator configured to electrically bias said at least one second n-FET and said at least one second p-FET by applying a second common substrate bias voltage to said second substrate region, wherein said first common substrate bias voltage and said second common substrate bias voltage are different.