Patent ID: 6067083
Filing Date: 2000-05-23
Classification: G09G

Abstract:
A video graphics processing circuit comprises:memory for storing display data as digital words;controller that generates synchronization information, control information, and address information;address generation unit operably coupled to the controller and the memory, wherein the address generation unit generates addresses based on the address information, wherein the addresses are used to retrieve the digital words from the memory to produce retrieved digital words;a look-up table DAC operably coupled to receive the retrieved digital words and to produce therefrom pixel information;a synchronization circuit operably coupled to receive the synchronization information and to produce therefrom synchronization signals; andclock circuit operably coupled to the synchronization circuit and to the look-up table DAC, wherein the clock circuit generates a first clock signal having a first clock rate and a second clock signal having the first clock rate, wherein the first clock signal is provided to the synchronization circuit and the second clock signal is provided to the look-up table DAC, and wherein the clock circuit disables the second clock signal based on the control information.