Patent ID: 6380811
Filing Date: 2002-04-30
Classification: H03L

Abstract:
A signal generator that receives an input clock signal at a first frequency and derives an output clock signal at a second frequency, said second frequency being higher than said first frequency, said signal generator comprising:an arrangement using a first intermediate clock signal, said arrangement receiving said input clock signal and providing a second intermediate clock signal by selectively providing transitions of said second intermediate clock signal at time intervals that are determined by a variable number of periods of said first intermediate clock signal, said second intermediate clock signal having a third frequency with an average higher than said first frequency, said average of said third frequency being related to said first frequency by a first factor; and a phase-looked loop circuit that locks at said average of said third frequency and provides said output clock signal, said second frequency of said output signal being related to said average of said third frequency of said second intermediate clock signal by a second factor.