Patent ID: 8811554
Filing Date: 2014-08-19
Classification: G09G,H04L

Abstract:
1. An interface circuit to receive and decode data signals, the interface circuit comprising: a multi-phase clock generating circuit arranged and configured to generate a multi-phase sampling clock signal with n different phases by delaying a sampling clock signal, wherein the sampling clock signal is asynchronous to at least one interface clock signal, by which the interface circuit is arranged and configured to receive, and to the data signals, a sampling circuit arranged and configured to receive the multi-phase sampling clock signal, and sample the data signals with the n difference phases of the multi-phase sampling clock signal, and wherein the data signals are received and decoded by measuring a run-length or measuring a run-time to determine a fractional position of the data signals; and characterized in that the sampling circuit further comprises at least one first sampler unit arranged and configured to receive the multi-phase sampling clock signal from the multi-phase clock generating circuit and the at least one interface clock signal, and at least one second sampling unit arranged and configured to receive the multi-phase sampling clock signal from the multi-phase clock generating circuit and the data signals.