Patent ID: 7840000
Filing Date: 2010-11-23
Classification: G06F,G09C,H04L

Abstract:
1. A cryptography system, comprising: a processor; a memory coupled to said processor; and a plurality of field programmable gate array blocks coupled to said processor, the plurality of field programmable gate array blocks including a first field programmable gate array block and a second field programmable gate array block, the first field programmable gate array block being configured for being programmed to execute a first crypto algorithm, the first field programmable gate array block being further configured for executing the first crypto algorithm, the second field programmable gate array block being configured for being programmed to execute at least one of the first crypto algorithm and a second crypto algorithm, the second field programmable gate array block being further configured for executing the at least one of the first crypto algorithm and the second crypto algorithm, wherein the system is configured for allowing said programming of the first field programmable gate array block and said execution of at least one of the first crypto algorithm and the second crypto algorithm by the second field programmable gate array block to occur concurrently, the second field programmable gate array block being further configured for programming the first field programmable gate array block.