Patent ID: 6154223
Filing Date: 2000-11-28
Classification: G06T,G09G

Abstract:
A graphics processing subsystem, comprising:at least four functionally distinct processing units, each including hardware elements which are customized to perform a pixel rendering operation which is not performed by at least some others of said processing units; at least some ones of said processing units being connected to operate asynchronously to one another;a frame buffer, connected to be accessed by at least one of said processing units;said processing units being mutually interconnected in a pipeline relationship, such that said processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture;wherein individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units;wherein at least some of individual ones of said processing units are seperated by data buffering logic.