Patent ID: 7055087
Filing Date: 2006-05-30
Classification: G06F,G11C,H03M

Abstract:
1. A pipelined Reed-Solomon decoder comprising: a plurality of pipelined processors including a number of pipeline processor stages for receiving an input Reed-Solomon code word and calculating error locations and error values which are included in the input code word; and a buffer circuit for temporarily storing the input code word while the plurality of pipelined processors calculates error locations and error values, wherein the buffer circuit comprises: a random access memory (RAM) including a plurality of banks; and a circular buffer controller for setting a first bank pointer that selects a first bank from the plurality of banks, and a second bank pointer that selects a second bank from the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset per frame of data and the offset is one less than the number of pipeline processor stages.