Patent ID: 8994420
Filing Date: 2015-03-31
Classification: H03L,H03M

Abstract:
1. An apparatus comprising: a fractional-N divider in a feedback path of a phase-locked loop (PLL) responsive to an output of the PLL and a divide control signal to generate a frequency-divided version of the output of the PLL; a phase interpolator in the feedback path of the PLL responsive to the frequency-divided version of the output of the PLL and a phase interpolation control signal to generate a phase-adjusted version of a feedback signal of the PLL; a frequency modulator comprising a first sigma-delta modulator configured to generate a second divide control signal and a digital quantization error signal in response to a digital divide ratio, the divide control signal being based on the second divide control signal; and a phase modulator comprising a second sigma-delta modulator configured to generate the phase interpolation control signal based on the digital quantization error, the second sigma-delta modulator having a high bandwidth signal transfer function and being an n-order sigma-delta modulator module, n being an integer greater than one.