Patent ID: 6122656
Filing Date: 2000-09-19
Classification: G06F

Abstract:
A processor comprising:a map unit coupled to receive a plurality of destination register numbers and a plurality of source register numbers, said map unit including:a register scan unit coupled to receive said plurality of source register numbers and said plurality of destination register numbers, wherein said register scan unit is configured to assign a plurality of virtual register numbers, wherein each one of said plurality of virtual register numbers corresponds to a different one of said plurality of source register numbers, and wherein a particular virtual register number within said plurality of virtual register numbers identifies a source of a particular physical register number corresponding to a particular source register number within said plurality of source register numbers; anda virtual/physical register map unit coupled to said register scan unit, wherein said virtual/physical register map unit is configured to map said particular physical register number to said particular source register number responsive to said particular virtual register number.