Patent ID: 6633996
Filing Date: 2003-10-14
Classification: G06F

Abstract:
A maintenance bus architecture for a fault-tolerant computer system having a plurality of circuit board assemblies and maintenance bus-compatible subsystem components thereon comprising:a first parent maintenance bus and a second parent maintenance bus interconnecting to each of the plurality of circuit board assemblies; a command module interconnected with each of the first parent maintenance bus and the second parent maintenance bus, the command module being constructed and arranged to transmit and receive control and monitor data over the first parent maintenance bus and the second parent maintenance bus in a predetermined format; a first bridge and a second bridge associated with each of the plurality of circuit boards; each first bridge being interconnected with the first parent maintenance bus and each second bridge being connected with the second parent maintenance bus; a child maintenance bus interconnected between the first bridge and the second bridge, the child maintenance bus being interconnected to predetermined ports on each of the maintenance bus-compatible subsystem components; and wherein each of the first bridge and the second bridge are constructed and arranged to transfer the control and monitor data addressed thereto between the child maintenance bus and the first parent maintenance bus and second parent maintenance bus, respectively, only one of the first bridge and the second bridge being active to transfer the control and monitor data at a given time.