Patent ID: 9081743
Filing Date: 2015-07-14
Classification: G06F

Abstract:
1. A communication system for testing field programmable gate arrays (FPGA) comprising a first interface module located in one of a computer and FPGA which is coupled to a message generating unit; a second interface module located in the other one of the computer and the FPGA which is coupled to a message processing unit; the first and second interface modules being interconnected by a virtual channel over a routing network; the first interface module is configured to receive messages from the message generating unit and to send the received messages over the virtual channel to the second interface module; the second interface module is configured to receive the messages over the virtual channel and to transmit the received messages to the message processing unit; the second interface module is further configured to receive a processing complete signal from the message processing unit when the received messages have been processed in the message processing unit and is further configured to send an acknowledgement signal to the first interface module after reception of the processing complete signal, wherein the first interface module comprises a memory for storing an information about a maximum number of messages allowed to be send to the second interface module prior to receive an acknowledgement signal; the first interface module further comprises an evaluation unit for evaluating how many messages have been transmitted since the last acknowledgement signal; and the first interface module being configured to refuse messages from the message generating unit, when the maximum number has been reached.