Patent ID: 9159709
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A stacked semiconductor package comprising: a plurality of semiconductor chips each including a substrate, through-electrodes passing through the substrate and a dielectric layer with a reduced dielectric constant formed between the substrate and the through-electrodes where the dielectric layer with a reduced dielectric constant has at least one air gap, and stacked such that through-electrodes of the plurality of semiconductor chips are connected with one another, Wherein the semiconductor chips includes a first semiconductor chip, a second semiconductor chip which is stacked under the first semiconductor chip, and a third semiconductor chip which is stacked under the second semiconductor chip, and wherein the dielectric layer with a reduced dielectric constant of the third semiconductor chip has a highest dielectric constant among the semiconductor chips, dielectric constants of dielectric layers with a reduced dielectric constant gradually decrease toward the first semiconductor chip, and the dielectric layer with a reduced dielectric constant of the first semiconductor chip has a lowest dielectric constant, Wherein the dielectric layer of the third semiconductor chip comprises a double-layered structure of a porous dielectric layer which has a plurality of air gaps therein and an air gap-free dielectric layer which has no air gap therein, the dielectric layer of the second semiconductor chip comprises a single-layered structure of a porous dielectric layer, and the dielectric layer of the first semiconductor chip comprises a single-layered structure of a hollow type dielectric layer which has an air gap defined in a center portion thereof.