Patent ID: 8159008
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method of fabricating a device structure using a layer stack that includes a semiconductor layer, a handle substrate composed of a semiconductor material of a first conductivity type, and an insulating layer between the semiconductor layer and the handle substrate, the method comprising: forming a first trench and a second trench each extending from a top surface of the semiconductor layer through the semiconductor layer and the insulating layer into the handle substrate; at least partially filling the first trench and the second trench with a doped material containing a dopant having a second conductivity type in the semiconductor material that is opposite to the first conductivity type; transporting a concentration of the dopant outwardly from the doped material into the semiconductor material of the handle substrate surrounding the first trench to define a first doped region of the second conductivity type and into the semiconductor material of the handle substrate surrounding the second trench to define a second doped region of the second conductivity type; and forming a gate electrode aligned with a channel region defined in the semiconductor material of the handle substrate between the first and second doped regions.