Patent ID: 6834087
Filing Date: 2004-12-21
Classification: H03L

Abstract:
In a receiver operable to receive a receive signal transmitted thereto during operation of a radio communication system, an improvement of a delay lock loop circuit that synchronizes the receiver with the receiver signal transmitted thereto, said delay lock loop circuit comprising:a sample selection signal generator adapted to receive sampled representations of the receive signal, said sample selection signal generator for generating a sample-selection signal, the sample-selection signal calculated over a selected sampling period, the sample-selection signal of a value responsive to the sampled representations of the receive signal over selected sample period lengths, each sampled representation represented in terms of a positive offset, a negative offset, and a zero offset; and a selector coupled to said sample selection signal generator, said selector for selecting operation of said sample selection signal generator alternately in a first mode and at least a second mode, when operation in the first mode is selected, said selector selects the selected sampling period to be of first sample period lengths, and when operation in the second mode is selected, said selector selects the selected sampling period to be of second sample period lengths.