Patent ID: 8897069
Filing Date: 2014-11-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array configured to include plural memory cells; page buffer groups coupled to at least one of bit lines coupled to the memory cells, configured to have page buffers in order to program or read the memory cells, and selected by select signals; a sensing circuit configured to perform program verifying of the page buffer group selected by the select signal, and configured to output a pass/fail signal corresponding to the page buffer group; a verifying result signal generation section configured to output one or more of a first verifying signal and a second verifying signal in accordance with pass or fail of the program for total page buffer groups by using the pass/fail signal; and a control circuit configured to output the select signals to verify the program after the program is performed, and control operation of the program in response to an output signal of the verifying result signal generation section.