Patent ID: 7242227
Filing Date: 2007-07-10
Classification: H04L

Abstract:
1. A differential bus network output driver for supplying a high-side differential output signal and a low-side differential output signal through a high-side differential output terminal and a low-side differential output terminal to a two-wire link in response to an input signal, the differential bus network having a first and a second power supply rail, comprising: a high-side driver that comprises, a first p-channel transistor, having a source, a gate, a backgate, and a drain, a second p-channel transistor, having a source, a gate, a backgate, and a drain, the backgate coupled to the source, the source coupled to the backgate of the first p-channel transistor, the drain coupled to the source of the first p-channel transistor, the gate coupled to receive a first voltage reference, a third p-channel transistor, having a source, a gate, a backgate, and a drain, the backgate coupled to the source, the drain coupled to the drain of the first p-channel transistor to form the high side differential output terminal, the gate coupled to receive a second voltage reference, a first diode coupled between the first power supply rail and the source of the third p-channel transistor, a first comparator, having a first input, a second input, and an output, the first and second inputs of the first comparator being coupled to receive the high-side differential output signal and a high-side voltage reference, respectively, a first latch, having a clear input, a clock input, and an output, the clear input coupled to the output of the first comparator, the clock input coupled to receive-the input signal, and a first level-shifter coupled between the output of the first latch and the gate of the first p-channel transistor; and a low-side driver that comprises, a fourth p-channel transistor, having a source, a gate, a backgate, and a drain, the source coupled to the source of the first p-channel transistor to form a common-mode voltage reference node to receive a common-mode voltage reference, a fifth p-channel transistor, having a source, a gate, a backgate, and a drain, the source coupled to the backgate and the backgate of the fourth p-channel transistor, the drain coupled to the source of the fourth p-channel transistor, the gate coupled to receive a third voltage reference, a second diode coupled to the drain of the fourth p-channel transistor to form the low-side differential output terminal, a first n-channel transistor, having a source, a gate, a backgate, and a drain, the drain coupled to the second diode, the backgate coupled to the source, the source coupled the second power supply rail, the gate coupled to receive a fourth voltage reference, a second comparator, having a first input, a second input, and an output, the first and second inputs of the second comparator being coupled to receive the low-side differential output signal and a low-side voltage reference, respectively, a second latch, having a clear input, a clock input, and an output, the clear input coupled to the output of the second comparator, the clock input coupled to receive the input signal, and a second level-shifter coupled between the output of the second latch and the gate of the fourth p-channel transistor.