Patent ID: 6352917
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A method to form metal interconnect levels in the manufacture of an integrated circuit device comprising:depositing a first dielectric layer overlying a semiconductor substrate wherein said semiconductor substrate comprises all layers and devices formed prior to said depositing of said first dielectric layer and wherein said first dielectric layer may comprise a stack of dielectric materials; patterning said first dielectric layer to form trenches for planned damascene interconnects; depositing an insulating layer overlying said first dielectric layer and lining said trenches; anisotropically etching down said insulating layer to form insulating layer spacers on the sidewalls of said trenches wherein the presence of said insulating layer spacers prevents metal diffusion into said first dielectric layer; depositing a conductive barrier layer overlying said first dielectric layer and lining said trenches; depositing a metal layer overlying said conductive barrier layer and filling said trenches; polishing down said metal layer and said conductive barrier layer to confine said metal layer and said conductive barrier layer to said trenches and to thereby said damascene interconnects; patterning said damascene interconnects to form via plugs in an upper portion of said damascene interconnects wherein said patterning comprises partially etching down said damascene interconnects, wherein a via mask overlies and protects portions of said damascene interconnects from said etching down, wherein a trench mask overlies and protects said first dielectric layer from metal contamination during said etching down, and wherein portions of said damascene interconnects partially etched down form conductive lines; depositing a nonconductive barrier layer overlying said first dielectric layer, said conductive lines, and said via plugs; and depositing a second dielectric layer overlying said non-conductive barrier layer and filling gaps caused by said patterning of said copper layer to complete said metal interconnect level in the manufacture of said integrated circuit device.