Patent ID: 8971145
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A memory system, comprising: a multi-port memory having a first port and a second port asynchronous with a master clock having a first edge and a second edge; first input registers synchronous with a first clock having a first edge and a second edge in which the first input registers output a valid address responsive to the first edge of the first clock, wherein the first clock may be asynchronous respective to the master clock; second input registers synchronous with a second clock having a first edge and a second edge in which the second input registers output a valid address responsive to the first edge of the second clock, wherein the second clock may be asynchronous with respect to the master clock; wherein: a first FIFO coupled to the multi-port memory for the first port, wherein the first FIFO is pushed in synchronization with the master clock and pops in synchronization with the first clock; and a second FIFO coupled to the multi-port memory for the second port, wherein the second FIFO is pushed in synchronization with the master clock and pops in synchronization with the second clock.