Patent ID: 6268252
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method of forming an integrated circuit structure, comprising the steps of:forming first and second spaced-apart electrically conductive lines that each comprise an electrically insulating capping layer, on a semiconductor substrate;forming an electrically insulating layer having an opening therein that exposes the semiconductor substrate and the first and second electrically conductive lines, on the semiconductor substrate; thenforming an electrically conductive layer that covers and extends between the first and second electrically conductive lines and electrically contacts the semiconductor substrate, in the opening;simultaneously etching back the electrically conductive layer and the electrically insulating layer using a first etchant that selectively etches the electrically conductive layer at a first rate and the electrically insulating layer at a second rate less than the first rate; andforming first and second contact pads that electrically contact the semiconductor substrate, are self-aligned to the first and second electrically conductive lines, respectively, and are electrically isolated from each other, by selectively etching the electrically conductive layer at a third rate while simultaneously etching the capping layers associated with the first and second electrically conductive lines at a fourth rate greater than the third rate.