Patent ID: 8982659
Filing Date: 2015-03-17
Classification: G11C

Abstract:
1. A memory device, comprising: a memory array having a plurality of memory cells, each for storing a bit of information; a bitline precharging circuit for precharging a bitline associated with a column of the memory array; a bitline floating circuit having a logic gate for qualifying a precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state; sleep/shut-off circuitry including a first transistor for disconnecting nominal power provided by a nominal power supply from input/output circuitry of the device when the memory array is not being accessed or is permanently disabled for yield recovery, the sleep/shut-off circuitry including a node coupled to the input/output circuitry including at least one of a read/write column multiplexer, a sense amplifier, a write driver, and the bitline precharging circuit; and wherein the sleep/shut-off circuitry further comprises bias circuitry coupled to the node and the nominal power supply, the bias circuitry including a second transistor for providing a virtual power level to the input/output circuitry by limiting the nominal power supply voltage, the virtual power level being lower than the nominal power, wherein the second transistor to receive a shut off signal to turn off the second transistor for at least a portion of the memory array that is permanently disabled for yield recovery, wherein the second transistor prevents generation of the virtual power level when the second transistor is off, wherein the second transistor is the only transistor of the bias circuitry.