Patent ID: 8358558
Filing Date: 2013-01-22
Classification: G11C

Abstract:
1. An address control circuit comprising: an enable signal generator configured to generate a read enable signal that is activated in response to a read command and configured to be inactivated in response to a burst end signal or a burst command, wherein the burst end signal appears in pulse patterns at times according to burst lengths determined by a mode register set that is executed at the initial operation, and the burst command acts as an interrupt signal that is applied in a pulse pattern for suspending a burst operation in a first burst period; an address decoder configured to generate a decoded address signal by decoding an address; an address buffer configured to output a read column address by buffering the decoded address signal in response to the read enable signal; and a write column address control circuit configured to generate a write column address from the address during a second burst period for a write operation mode.