Patent ID: 7373489
Filing Date: 2008-05-13
Classification: G06F

Abstract:
1. A processor, comprising: instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of said plurality of threads; floating-point arithmetic logic configured to execute a floating-point instruction issued by said instruction fetch logic from a given one of said plurality of threads, and further configured to determine whether said floating-point instruction generates an exception; and exception prediction logic configured to generate a prediction that said floating-point instruction will generate said exception, wherein said prediction is generated before said floating-point arithmetic logic determines whether said floating-point instruction generates said exception; wherein in response to said exception prediction logic generating said prediction that said floating-point instruction will generate said exception, one or more instructions from said given thread that are subsequent in program order to said floating-point instruction are flushed from said processor while an instruction from a thread other than said given thread continues to execute.