Patent ID: 6338128
Filing Date: 2002-01-08
Classification: G06F

Abstract:
A processor comprising:an effective address to real address translation unit; circuitry for selectively invalidating entries in the effective address to real address translation unit, wherein the invalidating circuitry is operable for invalidating less than all of the entries in the effective address to real address translation unit, wherein the invalidating circuitry further comprises: one or more class bits associated with each of the entries in the effective address to real address translation units; and circuitry for invalidating only those entries in the effective address to real address translation unit having selected class bits; a segment lookaside buffer having entries operable for translating effective addresses pertaining to a program being executed by the processor to virtual addresses; a particular set of one or more class bits assigned to the entries in the segment lookaside buffer; circuitry for invalidating the entries in the segment lookaside buffer; circuitry for comparing the particular set of one or more class bits to the one or more class bits associated with each of the entries in the effective address to real address translation unit; and circuitry for invalidating only those ones of the entries in the effective address to real address translation unit having one or more class bits matching the particular set of one or more class bits assigned to the entries in the segment lookaside buffer.