Patent ID: 6021514
Filing Date: 2000-02-01
Classification: G01R

Abstract:
A method for LBIST testing chips having an LBIST test circuit, comprising the steps of: using a PRPG (Pseudo-Random Pattern Generator) (10) to generate test pattern data for chip testing, and passing said test pattern data through multiple parallel scan chains (14), applying clocks to the system logic (13), then unloading multiple parallel scan chains (14) to a MISR (Multiple Input Signature Register) (12) to compress the test results and in the process with a STCM (Self-Test Control Macro) applying clocks and linehold control signals of LBIST control logic to the PRPG, MISR and chip system logic to perform the test, said PRPG applying test pattern data including linehold states generated by said LBIST control logic to the system logic which then passes through said scan chains to said MISR to provide a test signature, said LBIST control logic being programmed to generate said linehold states to be applied to specified scan chain latches whereby latches of said scan chains are program specified and can be lineheld to a specified state as lineholding latches in order to diagnose and characterize any chip problems, and in the even that intermittent faults are found to exist on the chip during testing, said latches can be lineheld to prevent switching or invalid states in the logic from producing intermittent faults and generating intermittent signatures.