Patent ID: 7934135
Filing Date: 2011-04-26
Classification: G01R

Abstract:
1. A computer-implemented method for testing one or more timed signal transitions within a device during a logic built-in self-test, the method comprising: generating a pseudo-random value using a pseudo-random pattern generator included in the device; storing a portion of the pseudo-random value into a capture register included in the device, the stored portion of the pseudo-random value being a captured pseudo-random value; invoking a transition test select signal from a logic built-in self-test controller, the logic built-in self-test controller controlling the logic built-in self test; in response to invoking the transition test select signal, loading the captured pseudo-random value from the capture register into an untimed logic path, wherein the loading results in stabilizing the untimed logic path to a static state; in response to the untimed logic path stabilizing to a static state, issuing a functional clock; and testing one or more timed signals that transition state according to the issued functional clock, wherein the one or more timed signals are dependent upon the stabilized untimed logic path.