Patent ID: 6075749
Filing Date: 2000-06-13
Classification: G11C

Abstract:
A semiconductor memory device, comprising:an internal clock signal generating circuit that generates first and second internal clock signals for internal timing control in response to an external clock;a first latch circuit that includes a first switching means to operate in synchronization with said first internal clock signal and latches a plurality of command control signals for the internal operation control and outputs a plurality of latch command signals;a command decoding circuit that decodes said plurality of latch command signals and outputs a plurality of command decode signals; anda second latch circuit that includes a second switching means to operate in synchronization with said second internal clock signal, latches said plurality of command decode signals and outputs a plurality of predetermined mode signals;wherein said internal clock signal generating circuit comprises a timing setting means for setting a timing between said first and second internal clock signals, and a clock width adjusting means for adjusting a pulse width of said first internal clock signal according to timing of said second internal clock signal,said first latch circuit sets a hold time required from a time that said first switching means is turned on to a time that an input signal of said first latch circuit starts varying from a certain determined level, andsaid second latch circuit sets a setup time required from a time that an input signal of said second latch circuit reaches a certain determined level to a time that said second switching means starts turning off.