Patent ID: 6567898
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A memory controller, comprising:a memory unit having an n-byte memory data width; a register unit consecutively reading out, in response to an enable signal supplied thereto, data from said memory unit with every n-byte size, said register unit further recording therein said data read out from said memory unit in the form of continuous data of 2nâˆ’1 bytes including last data read out from said memory unit; a shifter unit selecting consecutively, in response to a shift signal supplied thereto, a block of continuous n-byte data from said continuous data of 2nâˆ’1 bytes stored in said register unit, said shifter unit supplying said continuous n-byte data block to an output terminal; and a control unit controlling said memory unit, said register unit and said shifter unit, wherein said register unit includes a first register and a second register, said first register storing said data read out from the memory unit having n byte size, said second register extracting and storing therein nâˆ’1 byte data from said data held in said first register with a delay of one operational cycle with respect to an operation of said first register storing said data therein, said shifter extracting n byte data consecutively from said 2nâˆ’1 byte data continuously stored in said first and second registers.