Patent ID: 8341379
Filing Date: 2012-12-25
Classification: G06F

Abstract:
1. A processor comprising: circuitry configured to execute software instructions defined in an instruction set architecture implemented by the processor, wherein the circuitry is configured to generate load/store operations; a memory management unit (MMU) coupled to the circuitry, wherein the MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates, wherein the PTEs are stored in a software-created page table in memory during use, and wherein the MMU further comprises a table walk unit configured to read a translation from the PTEs in response to a translation buffer miss for a load/store operation, and wherein the hardware-generated PTE updates comprise one or more reference bit updates generated by the table walk unit in response to detecting valid translations in the page tables for translation buffer misses and further in response to a clear reference bit in the PTEs storing the translations, wherein the reference bit updates are defined to set the reference bit in the PTE without changing the translation defined by the PTE during use; and an interface unit coupled to the MMU and to an external interface of the processor, wherein the processor is configured to communicate with other agents on the external interface, and wherein the interface unit is configured to receive a synchronization operation on the external interface from another agent on the external interface, wherein the synchronization operation is defined to cause the pending hardware-generated PTE updates in the queue, if any, to be written to memory, and wherein the interface unit is configured to prevent the synchronization operation from completing on the interface in response to one or more hardware-generated PTE updates pending in the queue that were in the queue prior to receiving the synchronization operation; and wherein the MMU is configured to permit the synchronization operation to complete responsive to detecting that all pending hardware generating PTE updates that were in the queue prior to receiving the synchronization operation have completed, and wherein the MMU is configured to permit subsequent hardware-generated PTE updates into the queue as new pending hardware-generated PTE updates prior to the synchronization operation completing on the interface, and wherein the interface unit is configured to permit the synchronization operation to complete even though the new pending hardware-generated PTE updates are in the queue.