Patent ID: 7035998
Filing Date: 2006-04-25
Classification: G06F

Abstract:
1. A pipelined multistreaming processor, comprising: an instruction cache having a plurality of ports: a first cluster of a plurality of instruction streams, said first cluster fetching instructions from said instruction cache; a second cluster of a plurality of instruction streams, said second cluster fetching instructions from said instruction cache; a plurality of instruction queues, one for each of said instruction streams in each of said first and second clusters; a first dispatch stage, coupled to said first cluster, for dispatching to execution units instructions from said instruction streams in said first cluster; and a second dispatch stage, coupled to said second cluster, for dispatching to execution units instructions from said instruction streams in said second cluster; wherein said first and second clusters operate independently, with said first and second dispatch stages taking instructions only from said plurality of instruction queues which are in said clusters to which said dispatch stages are dedicated; and wherein said first and second clusters are coupled to said plurality of ports on said instruction cache, and can each utilize one or more of said plurality of ports.