Patent ID: 6207508
Filing Date: 2001-03-27
Classification: H01L

Abstract:
Forming a vertical MOSFET device, comprising the steps of:forming a semiconductor substrate having first and second opposing major surfaces;growing a first oxide layer on the first surface;depositing polysilicon on the first oxide layer;defining a polysilicon layer from the polysilicon;forming a body region of second conductivity type extending into the substrate and under the polysilicon layer from the first surface and defining a drain region having an extended drain portion bounded by the body region;forming a source region of first conductivity type extending into the substrate from the first surface within the boundaries of the body region;forming a channel portion, defined at the first surface by the source region and the extended drain portion, wherein the polysilicon layer overlays a portion of the source region, the channel portion, and at least a portion of the extended drain portion adjacent the channel portion;forming a drain electrode contacting the drain region on the second surface;selectively doping the polysilicon layer to form a polysilicon gate electrode disposed on the first surface over the channel portion and at least a portion of the extended drain portion adjacent the channel portion and an undoped polysilicon region disposed on the first surface adjacent to the polysilicon gate electrode over a substantial portion of the extended drain portion;growing a second oxide layer disposed over the polysilicon gate electrode and the undoped polysilicon region;forming a first window in the second oxide layer over the polysilicon gate electrode so as to expose a top surface of the polysilicon gate electrode, wherein a portion of the second oxide layer that overlays the undoped polysilicon region is not effected by forming the first window; and placing a layer of metal in the first window in the second oxide layer over the polysilicon gate electrode and over the second oxide layer to form a metal gate electrode having electrical contact with the polysilicon gate electrode, wherein the portion of second oxide layer over the undoped polysilicon region protects the undoped polysilicon region from the layer of metal.