Patent ID: 6790754
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method for forming contact electrodes in a semiconductor device comprising:sequentially forming a pad oxide layer, a pad nitride layer, a dummy oxide layer and a capping nitride layer on a semiconductor substrate; patterning the capping nitride layer, the dummy oxide layer, the pad nitride layer and the pad oxide layer; etching the semiconductor substrate to a predetermined depth to form a trench in the semiconductor substrate; filling the trench with an insulating material to form a device isolation stripe; patterning the capping nitride layer, the dummy oxide layer, and a portion of the pad nitride layer, wherein a remaining portion of the pad nitride layer has a thickness of tens of angstroms to form a second trench where a gate electrode will be positioned; forming spacers on sidewalls of the capping nitride layer, the dummy oxide layer and the pad nitride layer; implanting ions through the remaining portion of the pad nitride layer and the pad oxide layer to form a local channel portion in the semiconductor substrate; sequentially forming a gate insulating layer and a gate electrode on the remaining portion of the pad nitride layer between the spacers; etching the capping nitride layer, the dummy oxide layer and the device isolation stripe until the pad nitride layer is exposed; and implanting ions through the pad nitride layer and the pad oxide layer to form a source/drain portions in the semiconductor substrate.