Patent ID: 6569762
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method of stacking integrated circuit chips to form a three dimensional integrated circuit module, comprising:a) creating a stack of integrated circuit chips of different sizes with solder bumps on a front surface of each chip electrically connected to solder bumps located on a back surface of each chip, whereby there is electrical connectivity between solder bumps on said front and back surfaces and between internal circuitry of said integrated circuit chips and said solder bumps, b) ordering said stack of chips according to size with a smallest chip on top and a largest chip on bottom, c) aligning said chips such that the solder bumps on the back surface of a first chip align with the solder bumps on the front surface of a second chip that is below said first chip, d) aligning solder bumps on the back surface of said largest chip to solder bumps on a front side of a substrate that is larger than said largest chip and that has a pin array on a back side of said substrate, e) pressing together said stack of integrated circuit chips and said substrate, and heating said stack to reflow said solder bumps, f) soldering a heat sink to an area of solder bumps on each chip and said substrate that extends outward from the edge of a smaller chip mounted above.