Patent ID: 7939392
Filing Date: 2011-05-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: providing a semiconductor substrate; forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure; forming an inter-layer dielectric (ILD) over the substrate and the transistor; performing a first chemical mechanical polishing (CMP) on the ILD to expose a top surface of the dummy gate structure; removing a portion of the ILD such that a top surface of the ILD is at a distance below the top surface of the dummy gate structure; forming a material layer over the ILD and dummy gate structure; performing a second CMP on the material layer to expose the top surface of the dummy gate structure; removing the dummy gate structure thereby forming a trench; forming a metal layer to fill in the trench; and performing a third CMP that substantially stops at the top surface of the ILD.