Patent ID: 8470640
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor die from a semiconductor wafer having a top and bottom surface, the method comprising the steps of: (a) defining an integrated circuit on a portion of the semiconductor wafer; (b) forming a localized cavity in the bottom surface of the wafer and extending partway to the top surface, the localized cavity providing space for receiving a wire bond, the wire bond extending from a second semiconductor die affixed beneath the semiconductor die, and the wire bond not contacting the semiconductor die, the semiconductor die having a first thickness, away from the localized cavity, between top and bottom surfaces of the semiconductor die, and the semiconductor die having a second thickness, at the localized cavity, between the top and bottom surfaces, the second thickness being less than the first thickness; and (c) singulating the semiconductor die from the semiconductor wafer so that the localized cavity resides in two adjacent sides of the singulated semiconductor die, the localized cavity taking up less than an entire side of the semiconductor die, and the localized cavity comprising an enclosed tunnel through a bottom portion of the semiconductor die having openings on the two adjacent sides of the semiconductor die, a corner where the two adjacent sides of the semiconductor die come together having the first thickness.