Patent ID: 6670845
Filing Date: 2003-12-30
Classification: G05F

Abstract:
A high DC voltage to low DC voltage circuit converter, for receiving a high DC voltage and for generating a low DC voltage in response thereto, comprising:a first NMOS transistor having a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal; said first terminal connected to said high DC voltage and said second terminal providing said low DC voltage; a resistor divider circuit having a first node, a middle node and a second node, said first node connected to said high DC voltage, said middle node connected to said gate of said first NMOS transistor; said resister divider circuit further comprising a first resistor having a first end and a second end with said first end as said first node; said resister divider circuit further comprising a second resister having a first end and a second end with said first end connected to said second end of said first resistor, as said middle node, and said second end as said second node; a plurality of serially connected NMOS transistors having a first end and a second end; each of said serially connected NMOS transistors having a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal; said first terminal of each of said serially connected NMOS transistors being connected to its gate and its second terminal connected to said first terminal of an adjacent NMOS transistor; said first terminal of one of said plurality of NMOS transistors being said first end and connected to said second node, and said second end connected to ground; and a first semiconductor capacitor made of a NMOS transistor having a first terminal, a second terminal and a gate, said connected to said second node, and said first terminal and said second terminal connected together to one of the junctions of said first and second terminals in said plurality of serially connected NMOS transistors.