Patent ID: 9224836
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer having a lattice constant that is larger than a lattice constant of the semiconductor substrate; forming a second semiconductor layer on the first semiconductor layer; patterning the second semiconductor layer, the first semiconductor layer, and the semiconductor substrate to form a preliminary pillar; forming a third semiconductor layer surrounding an outer circumference of the preliminary pillar to define a pillar; forming a gate insulating layer on the pillar and the semiconductor substrate; forming a drain in the second semiconductor layer; forming, below the pillar, a source in the semiconductor substrate; and forming a gate surrounding an outer circumference of the pillar, wherein each of the second semiconductor layer and the third semiconductor layer has a lattice constant that is smaller than a lattice constant of the first semiconductor layer.