Patent ID: 6703270
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:forming a patterned masking layer of insulating material at a surface of a semiconductor body, etching the semiconductor body through the patterned masking layer so as to form a trench in the semiconductor body, applying an insulating layer which fills the trench in the semiconductor body, the insulating layer exhibiting a trough above the trench, which trough has a bottom area lying substantially above the surface of the semiconductor body, subjecting the semiconductor body to a planarizing treatment so as to form a substantially planar surface, subjecting the semiconductor body to a further treatment so as to expose the semiconductor body and form a field isolating region, wherein the insulating layer is removed substantially to the bottom area of the trough by means of chemical mechanical polishing (CMP) using fixed abrasives in a CMP polishing pad during the planarizing treatment.