Patent ID: 8234319
Filing Date: 2012-07-31
Classification: G06F

Abstract:
1. A method of completing a two's complement operation, the method comprising: receiving a plurality of byte values; splitting, by a splitting logic, the plurality of byte values into a first portion and a second portion; inputting the first portion to a first segment of a first four-to-two compressor, wherein the first portion occupies the least significant bits of each row of the first four-to-two compressor; inputting a first bit value of one as a carry-in value to the first four-to-two compressor to perform a first stage of a two's complement operation; performing, by a compression logic, a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row, the second row offset one bit from the first row, wherein the first row includes a first bit corresponding to at least part of a sum of each low order bit of each byte value of the first portion; and inputting a second bit value of one to an offset bit position of the second row of the first set of results in order to perform a second stage of the two's complement operation.