Patent ID: 8658487
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device comprising: providing a first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate; providing a second dummy gate simultaneously with the provision of the first dummy gate, wherein the second dummy gate has a second high-k gate insulator layer, a second composite sacrificial layer, and a second dummy gate electrode sequentially stacked on the substrate; removing the first dummy gate electrode to expose the first composite sacrificial layer; removing the second dummy gate electrode simultaneously with the step of removing the first dummy gate electrode to expose the second composite sacrificial layer; forming a first patterned photo-resist layer to cover the exposed second composite sacrificial layer, removing the first composite sacrificial layer; forming a first work function layer on the first high-k gate insulator layer; and forming a first metal gate electrode on the first work function layer.