Patent ID: 7417915
Filing Date: 2008-08-26
Classification: G11C

Abstract:
1. A multiport memory device, comprising: an input data selector for selecting one of input data from a first input port and input data from a second input port; a memory cell array to/from which data is written/read based on the input data from the input data selector; an output data selector for selecting one of a first output port and a second output port to output read data from the memory cell array; and a clock doubling circuit for supplying a doubled clock to the input data selector, the output data selector, and the memory cell array, wherein the clock doubling circuit multiplies a frequency of a higher-frequency clock out of a first clock corresponding to data input from only the first input port and a second clock corresponding to data input from only the second input port by 2 or more to obtain and supply the doubled clock.