Patent ID: 7523290
Filing Date: 2009-04-21
Classification: G06F

Abstract:
1. A computing system for performing high speed data page operations having a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, said system comprising: a plurality of memory blocks in said real memory system for storing said data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each said real memory block partitioned into one or more sectors, each comprising contiguous bytes of said physical memory; a translation table structure in said physical memory storage having entries for associating a real address with sectors of said physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, said table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by said processor; a control device for directly manipulating entries in said translation table structure for performing block swap, block move and block clear page operations for all blocks in a page without actually accessing physical memory data contents.