Patent ID: 7332800
Filing Date: 2008-02-19
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first wiring substrate having a first main surface and a second main surface opposing the first main surface; a first semiconductor chip having a logic circuit, and mounted on the second main surface of the first wiring substrate, and electrically connected to the first wiring substrate; a second wiring substrate having a first main surface and a second main surface opposing the first main surface, the second wiring substrate being stacked over the first main surface of the first wiring substrate, and electrically connected to the first wiring substrate through a plurality of salient electrodes; a second semiconductor chip having a memory circuit, and mounted on the second main surface of the second wiring substrate, and electrically connected to the second wiring substrate; and a plurality of external terminals formed over the second main surface of the first wiring substrate, wherein the number of wiring layers in the first wiring substrate is larger than that in the second wiring substrate; wherein the plurality of salient electrodes is arranged around the second semiconductor chip; and wherein the plurality of external terminals is arranged around the first semiconductor chip.