Patent ID: 6535963
Filing Date: 2003-03-18
Classification: H04L

Abstract:
Apparatus for a memory system useable in connection with a multicasting switch comprising:a main memory array having a plurality of memory subarrays, each memory subarray from the plurality of memory subarrays having separate address decoder and sense amp arrays; frame allocation logic circuitry which includes circuitry for associating any or all of said plurality of memory subarrays with any of a plurality of output ports, wherein said circuitry is configured to permit allocation of at least one of said plurality of memory subarrays with a first of said plurality of output ports during a first time period and allocation of said at least one of said plurality of memory subarrays with a second of said plurality of output ports during a second time period; and at least first and second different address lines coupled to address decoders of at least first and second different memory subarrays from the plurality of memory subarrays, wherein data, received in a least a first input port, may be written, in parallel, to the first and second different memory subarrays.