Patent ID: 6143603
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A method for manufacturing a dual-cylinder bottom electrode of a capacitor on a substrate having an isolation region and a transistor formed thereon, wherein the transistor has a gate electrode and a source/drain region, the method comprising the step of:forming a first silicon oxide layer over the substrate;forming a silicon nitride layer on the first silicon oxide layer;forming a first doped polysilicon layer on the silicon nitride layer;forming a second silicon oxide layer on the first doped polysilicon layer; forming an opening to penetrate through the second silicon oxide layer, the first doped polysilicon layer and the silicon nitride layer and expose a portion of the first silicon oxide layer, the opening being aligned over the source/drain region;patterning the second silicon oxide layer and the first doped polysilicon layer into a ring-type protuberance around the opening;forming a first spacer on the sidewall of the opening and forming a second spacer on an exterior sidewall of the ring-type protuberance, simultaneously;removing the second silicon oxide layer and a portion of the first silicon oxide layer exposed by the first spacer to form a node contact hole, wherein the node contact hole exposes a portion of the source/drain region;forming a second doped polysilicon layer over the substrate and filling the node contact hole; andremoving a portion of the second doped polysilicon layer to expose the silicon nitride layer and to form a bottom electrode.