Patent ID: 9224473
Filing Date: 2015-12-29
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a plurality of stacks of conductive strips alternating with insulating strips, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, a top plane of conductive strips, and an additional intermediate plane of conductive strips; a plurality of vertical structures arranged orthogonally to the plurality of stacks; memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of vertical structures; a stack of linking elements separated by insulating layers, and connected to conductive strips in respective intermediate planes in the plurality of intermediate planes and to the additional intermediate plane; and decoding circuitry coupled to the plurality of intermediate planes and the additional intermediate plane, and configured to replace an intermediate plane indicated to be defective with the additional intermediate plane.