Patent ID: 7231509
Filing Date: 2007-06-12
Classification: G06F

Abstract:
1. An extended register processor, comprising: a register file including a legacy register set and an extended register set comprising a plurality of physical extended registers arranged in N banks with M registers per bank, wherein the extended register set is accessible only with an extended register instruction; an instruction decoder enabled to detect an extended register instruction containing a virtual reference to an extended register; an extended register mapping unit, accessible to the instruction decoder, enabled to map the virtual reference to one of the physical extended registers; and means for processing an extended register allocation instruction in a code block by allocating a portion of the extended register set to the code block and configuring the extended register mapping unit to reflect the allocation, wherein the means for processing the extended register allocation instruction includes means for modifying an extended register mask, wherein the mask includes N fields each indicating the allocation status of a respective one of the extended register banks.