Patent ID: 7250350
Filing Date: 2007-07-31
Classification: H01L

Abstract:
1. A method for manufacturing integrated circuit device memory structures, the method comprising: forming a transistor structure overlying a semiconductor substrate, the transistor structure including a landing plug, the landing plug being coupled to a portion of the semiconductor substrate; forming a high density plasma oxide layer overlying the transistor structure; forming an overlying nitride layer overlying the high density plasma oxide layer; forming a doped glass layer overlying the nitride layer, the doped glass layer having a predetermined thickness, the predetermined thickness being substantially a height of a capacitor structure; patterning an trench opening within the doped glass layer to the nitride layer; forming a polysilicon layer within the trench opening including sides of the trench opening and overlying a surface of the doped glass layer, the polysilicon layer having a thickness to cover sides of the trench opening; removing a portion of the polysilicon layer overlying a bottom portion of the trench opening; removing a portion of nitride layer and removing a portion of the high density oxide layer to form an opening overlying the landing plug while the portion of polysilicon within the sides of the opening define a width of an opening through the nitride layer and the high density oxide layer; filling the trench opening with polysilicon material to a level above the surface of the doped glass layer; and planarizing the polysilicon material until the level of the doped glass layer is exposed, while maintaining the polysilicon material in the trench opening; and selectively removing the polysilicon material in the opening to a vicinity above the nitride layer.