Patent ID: 6263404
Filing Date: 2001-07-17
Classification: G06F

Abstract:
A method of controlling a memory cache and cache buffer to forward memory contents being delivered to the memory cache via the cache buffer to a processor awaiting return of those memory contents, comprisingproviding a plurality of sequencers, each sequencer storing information used in managing linefilling of memory contents into the cache in response to a cache miss generated by the processor,storing in each sequencer an indication of the range of memory addresses that are to be linefilled into the memory cache in response to the cache miss the sequencer is managing,in response to a request from the processor, determining a location in said cache or cache buffer that would contain the memory contents that the processor is awaiting if those memory contents were in the memory cache or cache buffer,speculatively forwarding memory contents from the determined location in either the cache buffer or memory cache to the processor, andverifying that the speculatively forwarded memory contents are the memory contents that the processor is awaiting.