Patent ID: 6445634
Filing Date: 2002-09-03
Classification: G06F,G11C

Abstract:
A serial access memory comprising:plural memory cells which are arranged at each of intersections formed by plural word lines and plural bit lines; a first register having a capacity capable of storing a data of one word to be stored in said plural memory cells and being connected with each of said plural bit lines, said first register storing an input serial data of one word and transferring the one word stored in said first register to the plural memory cells connected with one word line selected from among said plural word lines; a second register having a capacity capable of storing a data of one word to be stored in said plural memory cells and being connected with each of said plural bit lines, said second register receiving the one word from said plural memory cells connected with the one word line and outputting the one word received by said second register as an output serial data of one word; a third register having a capacity capable of storing a data of one word to be stored in said plural memory cells, said third register storing the input serial data of the one word and outputting the one word stored in said third register as another output serial data of one word; and a common address selector that provides address signals, the one word received by said second register and the one word stored in said third register being serially output according to the address signals provided from said common selector.