Patent ID: 6529054
Filing Date: 2003-03-04
Classification: G11C,H04J,H04L

Abstract:
In an integrated circuit, a synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal, comprising:a timer generator having a first timer generator output, said timer generator being coupled to receive said first plurality of timing signals and to serially output on said first timer generator output, as a first high frequency timing pulse stream, first timing pulses responsive to timing pulses of said plurality of timing signals, said first high frequency timing pulse stream having a timing pulse stream frequency that is higher than a timing input frequency associated with one of said first plurality of timing signals; a first plurality of data driver circuits coupled to receive said first plurality of data signals and said plurality of timing signals, said first plurality of data driver circuits are configured to serially output, as a first high frequency data stream, first data pulses responsive to said timing pulses of said plurality of timing signals and data pulses of said first plurality of data signals; said first high frequency data stream having a data stream frequency that is higher than a data input frequency associated with one of said first plurality of data signals; and a first data clocking circuit coupled to receive said first high frequency data stream and said first high frequency timing pulse stream to synchronize capture of data in said first high frequency data stream using said first high frequency timing pulse stream to output said synchronized data capture signal, wherein said synchronized data capture signal has a data output frequency that is higher than said timing input frequency and said data input frequency.