Patent ID: 6545933
Filing Date: 2003-04-08
Classification: G11C

Abstract:
A semiconductor memory comprising:a first memory mat including a plurality of first bit lines, a plurality of first word lines, and a plurality of first memory cells respectively connected to the plurality of first bit lines and the plurality of first word lines; a second memory mat including a plurality of second bit lines, a plurality of second word lines, and a plurality of second memory cells respectively connected to point where the plurality of second bit lines and the plurality of second word lines intersect; and a plurality of sense amplifiers formed in an area defined between said first memory mat and said second memory mat, wherein each of said plurality of sense amplifiers is connected to the corresponding one of said plurality of first bit lines and the corresponding one of said plurality of second bit lines, wherein each of said plurality of first memory cells includes a first capacitor having a first and a second electrodes, and a first transistor having a gate connected to the corresponding one of said plurality of first word lines and source-drain paths one of which is connected to the corresponding one of said plurality of first bit lines and the other of which is connected to the first electrode of the first capacitor, wherein each of said plurality of second memory cells includes a second capacitor having a third and a fourth electrodes, and a second transistor having a gate connected to the corresponding one of said plurality of second word lines and source-drain paths one of which is connected to the corresponding one of said plurality of second bit lines and the other of which is connected to the third electrode of the second capacitor, wherein each of the second electrodes of the first capacitors included in said plurality of first memory cells and each of the fourth electrodes of the second capacitors included in said plurality of second memory cells are connected to one conductive layer placed over said second memory mat and said plurality of sense amplifiers, and wherein two mats provided adjacent to each other constitute one of a plurality of banks, and respective word-line selecting addresses with respect to two banks away from each other with one of said plurality of banks interposed therebetween are independently set.