Patent ID: 6442597
Filing Date: 2002-08-27
Classification: G06F,H04Q

Abstract:
A data processing system comprising:a plurality of master devices; a plurality of node controllers, wherein a node controller organizes a subset of one or more of the plurality of master devices into a node; a plurality of memory subsystems; an address switch, wherein the address switch connects to each of the node controllers and to each of the memory subsystems, and wherein each of the memory subsystems connects to the address switch and to each of the node controllers; and a response combination block, wherein the response combination block connects to the address switch, to each master device, to each node controller, and to each memory subsystem in order to receive, from the plurality of master devices, the plurality of node controllers, the plurality of memory subsystems, and the address switch, command status signals and command response signals associated with commands issued by master devices and in order to generate command status signals and command response signals associated with commands issued by master devices.