Patent ID: 6204113
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method of forming a data storage capacitor in a DRAM cell, comprising the steps of:(a) providing a semiconductor substrate having at least one MOS transistor including a pair of source/drain regions formed thereon, and a first insulating layer formed over the said MOS transistor, with said first insulating layer having an opening to expose one of said source/drain regions;(b) forming a first conductive layer over said first insulating layer and completely filling said opening;(c) forming an insulating hump directly on said first conductive layer and centered over said opening;(d) forming a second conductive layer on the outer surface of the substrate to cover said first conductive layer and said insulating hump;(e) on the second conductive layer, forming only one pair of insulating material spacers which are disposed on and adjacent to sidewalls of a protruding part of said second conductive layer that covers said insulating hump;(f) using said spacers and said insulating hump as an etching mask, anisotropically etching exposed portions of said second conductive layer and an underlying portion of said first conductive layer to remove all parts of said first and second conductive layers which are outside of said spacers and to form only one pair of trenches extending into said first conductive layer to a given depth inside a region surrounded by the spacer;(g) removing said spacers and said insulating hump;(h) forming a dielectric layer on the outer surface of said substrate to cover remaining parts of said first and second conductive layers; and(i) forming a third conductive layer over said dielectric layer, whereby remaining parts of said first and second conductive layers, said dielectric layer, and said third conductive layer in combination constitute a data storage capacitor of a DRAM cell.