Patent ID: 7058834
Filing Date: 2006-06-06
Classification: G06F

Abstract:
1. A circuit having scan circuitry comprising: a constant power area that receives constant power; a switched power area that receives interruptible power; wherein the switched power area includes an input for receiving a normal mode clock signal; and an inactive state power reduction manager disposed in the constant power area for receiving a sleep signal and responsive thereto for asserting a stop clock signal to stop the normal mode clock, for performing a scan-based state-save by employing the scan circuitry, and for asserting a power control signal that is used to disconnect the switched power area from a power supply pad; and a selection unit that includes a first input for receiving signals from a source external to the circuit, a second input for receiving signals from the inactive state power reduction manager, a control input for receiving a save-state mode signal, and an output that is coupled to the scan circuitry; wherein the inactive state power reduction manager performs a scan-based state-save by generating the save-state mode signal and by providing signals to the second input of the selection unit.