Patent ID: 6507900
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A memory device comprising a plurality of blocks, wherein each block comprises:an array of memory cells arranged in a matrix and having a plurality or word lines and a plurality of bit lines; a word-line selecting circuit selecting one of the word lines; a row-address-register circuit storing an address of the selected word line; sense amplifiers connected to said memory cells through the bit lines and storing data of said memory cells of the selected word line; a precharge circuit precharging the bit lines; a data bus for reading the data from or writing the data to said sense amplifiers; a global row scheduler for successively selecting two or more blocks so that the selected two or more blocks simultaneously perform respective operations, wherein the respective operations include at least two of a first operation that selects one of the word lines in a first selected block, a second operation that transfers data between said amplifiers of a second selected block and said data bus, and a third operation that precharges the bit lines of a third selected block; and a check unit for detecting consecutive accesses that are made by said global row scheduler to a single block, thereby causing said global row scheduler to delay or ignore the block selection of the single block.