Patent ID: 6297083
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A method of fabricating a field effect transistor (FET) and an amorphous silicon load resistor in the same amount of silicon substrate space as a FET comprising the steps of:forming a FET with a level of metallization of a first conductive line;forming a first barrier metal layer on the first conductive line;forming a amorphous silicon layer on the first barrier metal layer;forming a second barrier metal layer on the amorphous silicon layer, said first and second barrier layers and the amorphous silicon layer comprising a resistor;patterning the amorphous silicon layer and the second barrier layer to form coextensive layers;forming an interlevel insulating layer on the first and second barrier layers;forming a via opening in the insulation layer of a size smaller than said coextensive layers and having a bottom adjacent the second barrier layer;filling the via opening with a conductive metal; andforming a level of metallization of a second conductive line adjacent the top of the filled via.