Patent ID: 6092223
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A redundancy circuit for a semiconductor integrated circuit including a cell sub-array, a redundancy cell block having column and row redundancy cell blocks for substituting a predetermined number of cells including an error cell in the cell sub-array, and a sense amplifier block for amplifying a data outputted from the cell sub-array and the redundancy cell block and outputting an amplified data through an input/output bus and an input/output bar bus, comprising: each cell of one of the row redundancy cell block and the column redundancy cell block corresponding to each of said substituted predetermined number of cells including the error cell of the cell sub-array and wherein a bit line of the cell sub-array is connected with the input/output bus, a bit bar line of the cell sub-array is connected with the input/output bar bus, a bit line of the redundancy cell block is connected with the input/output bar bus, and a bit bar line of the redundancy cell block is connected with the input/output bus.