Patent ID: 6269021
Filing Date: 2001-07-31
Classification: G11C

Abstract:
A semiconductor memory device comprising a memory cell array, wherein said memory cell array further comprises:a plurality of blocks, each block including:a plurality of memory cells arranged in a matrix form having rows and columns, each of said memory cells comprising a transistor, said transistor having a gate, a source and a drain, and said transistor storing data;row line means, wherein each row line means is connected to the gates of said transistors in one of said rows;row selection means for selecting a row line in response to an address signal for addressing each of said memory cells, connected to said row line means, wherein unselected row lines are unaffected by operations on said selected row line, and a decoding signal is independently applied to said selected row line by said row selection means; andblock selection means for selecting said block, including a plurality of block select transistors and a block select line, each block select transistor having a source, a drain and a gate, wherein said block select line is connected to the gates of said plurality of block select transistors, and the source of said block select transistor is connected to said memory cells; anda plurality of lines, wherein each line is coupled to the drain of one block select transistor in each of said blocks so that the stored data is read from said memory cell through said block select transistor and said line when a first predetermined signal on said block select line for selecting said block is applied to the gate of said block select transistor.