Patent ID: 7127693
Filing Date: 2006-10-24
Classification: G06F

Abstract:
1. A device for creating timing constraints for a semiconductor integrated circuit designed using a hierarchical design, the device comprising: a datapath extraction unit that extracts datapaths on which a timing verification is to be performed, wherein the datapath extraction unit extracts the datapaths, which are established between at least two child blocks in a parent block, from a cell library that includes description of logic function and timing information of each cell in the parent block, timing constraints that include definitions of any clocks of the semiconductor integrated circuit, and a netlist that includes connection information between cells in the parent block; a datapath output unit that creates a datapath list which allows a user to selectively specify a timing exception corresponding to a datapath extracted, and displays the datapath list, for the user; and a timing constraints modification unit that creates new timing constraints by modifying existing timing constraints based on the timing exception specified by the user.