Patent ID: 9147672
Filing Date: 2015-09-29
Classification: H01L,H05K

Abstract:
1. An apparatus comprising: a multichip package including a plurality of chip stacks including chips in a plurality of chip layers, each of the chip stacks including: two or more chips, each chip being inside vertical projection of at least another chip in the chip stack, each chip being disposed in a respective one of the chip layers; one or more horizontal conductive lines extending into perimeter regions around the chip stacks, the chips in a particular chip layer being electrically connected to horizontal conductive lines disposed in the particular chip layer; one or more vertical conductive lines in the perimeter regions electrically connected to one or more of the horizontal conductive lines in at least two chip layers; and a controller electrically connected to at least one chip in the plurality of chip stacks, the controller including circuits configured to deactivate one or more of the chip stacks.