Patent ID: 6903384
Filing Date: 2005-06-07
Classification: H01L

Abstract:
1. A dual gate CMOSFET device with thin silicon germanium (SiGe) dislocation regions, the CMOSFET comprising: a silicon substrate including n-doped and p-doped substrate regions; a first high defect region including ions selected from the group including H, H+, H2, HE+, and B overlying the n-doped substrate; a second high defect region including ions selected from the group including H, H+, H2, HE+, and B overlying the p-doped substrate; a first layer of relaxed SiGe overlying the first defect region; a second layer of relaxed SiGe overlying the second defect region and adjacent to the first layer of SiGe; an n-doped well (n-well) formed from the n-doped substrate, first defect region, and the first SiGe layer; a p-doped well (p-well) formed from the p-doped substrate, second defect region, and the second SiGe layer; a first layer of strained-Si overlying the first SiGe layer; a second layer of strained-Si overlying the second SiGe layer; a first channel region formed in the first layer of strained-Si; and, a second channel region formed in the second layer of strained-Si.