Patent ID: 6258626
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of making a stacked chip package comprising the steps of:providing a substrate having opposing upper and lower surfaces, the upper surface of the substrate being provided with a plurality of flip-chip pads and a plurality of wire-bondable pads arranged about the periphery of the flip-chip pads;providing a first chip having a plurality of solder bumps on the active surface thereof;placing the first chip onto the substrate in a manner that the solder bumps of the first chip are aligned with the flip-chip pads of the substrate;reflowing the solder bumps so as to mechanically and electrically attach the first chip to the substrate;providing a second chip having a plurality of bonding pads formed on the active surface thereof;attaching the second chip to the first chip through an adhesive layer;curing the adhesive layer;forming an underfill between the first chip and the substrate;curing the underfill;electrically coupling the second chip to the wire-bondable pads; andencapsulating the first chip and the second chip against a portion of the upper surface of the substrate.