Patent ID: 7386659
Filing Date: 2008-06-10
Classification: G06F,G11C

Abstract:
1. A common memory controller capable of controlling chips including a respective memory among different types of memories operating with different specifications, comprising: a first interface portion for receiving a control output signal to access said chips chip from a controller, and outputting a control input signal to the controller; a conversion control portion for converting said control output signal into one of at least two differing memory input signals in response to specifications of the memories to which the memory controller is connected, and converting a memory output signal respectively output from the memories into the control input signal receivable to said controller; and a second interface portion for outputting the memory input signal through a common bus terminal portion connected to the chips and receiving the memory output signal through the common bus terminal portion, wherein the second interface portion is capable of commonly connecting at least one of the chips including the respective memory among different types of memories, wherein each of said at least two differing memory input signals corresponds to a different one of the plurality of different types of memories.