Patent ID: 9003163
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. A computer-implemented method that combines a remote TLB lookup and a subsequent cache miss into a single coherence operation, wherein the method operates in a shared-memory multiprocessor system which partitions a virtual address space and a physical address space across two or more nodes of the shared-memory multiprocessor system, wherein a last-level TLB structure in each node is responsible for TLB entries for a subset of the virtual address space, and wherein the last-level TLB structures of the nodes collectively form a distributed, shared last-level TLB, the method comprising: receiving a memory operation with a virtual address in a first node; determining that one or more TLB levels in the first node miss for the virtual address; using the virtual address to determine a second node that is responsible for the subset of the virtual address space that includes the virtual address; sending a TLB request for the virtual address to the second node; and upon determining a hit for the virtual address in the last-level TLB structure of the second node, ensuring that a corresponding TLB entry is sent to the first node in parallel with initiating an operation to translate the virtual address into a physical address at the second node and determine whether a cache line associated with the translated physical address is available in the cache structures of any of the nodes.