Patent ID: 9176669
Filing Date: 2015-11-03
Classification: G06F

Abstract:
1. A computer system having hardware-based non-uniform memory access, the computer system comprising a plurality of nodes, each node having a volatile memory and at least one computing processor, each computing processor being capable of addressing a maximum amount of volatile memory that is less than the collective amount of volatile memory in the plurality of nodes, wherein at least one node also includes an I/O device having I/O memory, each node being configured to calculate a memory layout that includes a portion of the volatile memory of each of a plurality of nodes in the computer system, the memory layout being calculated to minimize an amount of unmapped memory as a function of 1) the number of nodes in the computer system, 2) the amount of volatile memory in each node, 3) the number of nodes that include an I/O device having I/O memory, and 4) the amount of I/O memory in each such I/O device, wherein the computing processor of each node is further configured to access the memory of another node using the calculated memory layout.