Patent ID: 8716795
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device having an n-type lateral double-diffused metal oxide semiconductor (N-LDMOS) transistor, a p-type LDMOS (P-LDMOS) transistor, an n-type MOS (NMOS) transistor, and a p-type MOS (PMOS) transistor, each of said N-LDMOS transistor and said P-LDMOS transistor having a source region, a drain region, and a gate region on a substrate, the method comprising: a) implanting p-type dopants into a surface of said substrate to form a p-type buried layer (PBL) region, and implanting n-type dopants into said surface of said substrate to form an n-type buried layer (NBL) region; b) growing an n-type epitaxial (N-EPI) layer on said NBL and PBL regions, wherein said N-EPI layer is shared by said N-LDMOS transistor and said P-LDMOS transistor; c) implanting p-type dopants into said surface of said substrate to form a p-doped deep p-well (DPW) region on said PBL region; d) forming a p-type well region (PWELL) and an n-type well region (NWELL) in said N-EPI layer, wherein said NWELL is shared by said N-LDMOS transistor and said PMOS transistor, and said PWELL is shared by said P-LDMOS transistor and said NMOS transistor; e) implanting dopants into said source region to form a doped body region; f) after said doped body region formation, forming an active area and a field oxide (FOX) region for isolation of at least one of said N-LDMOS transistor and said P-LDMOS transistor, and forming a drain oxide between said source region and said drain region of each of said N-LDMOS transistor and said P-LDMOS transistor; g) after said doped body region formation, forming a gate oxide adjacent to said source and drain regions, and forming a gate by covering said gate oxide and a portion of said drain oxide with a conductive material; and h) implanting dopants into said drain and source regions to form a doped drain region, and first and second doped source regions.