Patent ID: 6728846
Filing Date: 2004-04-27
Classification: G06F

Abstract:
A method of performing an atomic multiple word write to a memory for use in a processor that does not provide an atomic multiple word write to the memory capability, wherein said method comprises:A) attempting to set a gate flag associated with a first location in the memory to a first state when in a second state; B) testing whether the attempt in step (A) was successful; C) repeating steps (A) and (B) if the testing in step (B) failed; D) writing a second register to a second location in the memory after the test in step (B) succeeds; E) writing a first register to the first location in the memory after writing the second register in step (D); and F) setting the gate flag associated with the first location in the memory to the second state after completing writing the second register to the second location in step (D) and not before completing writing the first register in step (E).