Patent ID: 7482827
Filing Date: 2009-01-27
Classification: G01R

Abstract:
1. A testable integrated circuit, comprising a test interface circuit arranged to switch the integrated circuit between a functional operating mode and a test mode an internal clock circuit with a clock output for clocking functional circuits of the integrated circuit at least in the functional operating mode; a test circuit comprising a pulse counting circuit with a clock input coupled to the clock output; a state holding circuit that is coupled to the pulse counting circuit or is part of the pulse counting circuit, arranged so that the state holding circuit will lock into a predetermined state when a threshold number of clock pulses has bean applied to the clock input following a start of a time interval defined by the test interface circuit; the test interface circuit being coupled to the state holding circuit for reading out information from the integrated circuit about whether the state holding circuit has reached the predetermined state before the end of the time interval.