Patent ID: 7024509
Filing Date: 2006-04-04
Classification: G06F,H03K

Abstract:
1. A method for preventing passive release of interrupts within a computer system, the computer system having at least one processor for servicing the interrupts, one or more input/output (I/O) devices configured to issue interrupts, and an I/O bridge having a plurality of ports to which I/O devices are coupled and configured to interface between the I/O devices and the processor, the method comprising the steps of: asserting an interrupt signal by a subject I/O device coupled to a given port of the I/O bridge; forwarding an interrupt message corresponding to the interrupt signal to the processor for servicing; setting an interrupt pending flag in response to assertion of the interrupt signal; in response to the interrupt being serviced, generating a first ordered message, the first ordered message notifying the subject I/O device that the interrupt has been serviced; generating a second ordered message for clearing the interrupt pending flag; sending the first ordered message to the given port of the I/O bridge; sending the second ordered message to the given port of the I/O bridge after the first message has been sent; deasserting the interrupt signal in response to the first message; and clearing the interrupt pending flag in response to the second ordered message.