Patent ID: 6597038
Filing Date: 2003-07-22
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a semiconductor substrate having a channel region; a gate insulating film formed on said channel region; a gate electrode formed on said insulating film, said gate electrode having side surfaces; side walls, each side wall formed on an associated one of said side surfaces of said gate electrode; source and drain regions formed in said semiconductor substrate, each of said source and drain regions having a heavily doped region; and lightly doped drain (â€œLDDâ€ ) regions formed in said semiconductor substrate and contacting an associated heavily doped region, each of which LDD regions is covered with an associated one of said side walls; each of said LDD regions including a first region of a first impurity of a first conductivity type and a second region of a second impurity of the first conductivity type, said first region having a first impurity concentration distribution that has a concentration peak at a first depth from a surface of said channel, said second region having a second impurity concentration distribution that has a concentration peak at said first depth substantially from said surface of said channel, each of said source and drain regions including a third region of a third impurity of the first conductivity type and a fourth region of a fourth impurity of the first conductivity type, the diffusion coefficient of the first impurity being different from the diffusion coefficient of the second impurity, and the diffusion coefficient of the third impurity being different from the diffusion coefficient of the fourth impurity.