Patent ID: 6707325
Filing Date: 2004-03-16
Classification: H03K

Abstract:
An output circuit comprising:a first PMOS transistor and a first NMOS transistor connected in series between a high potential side power source and a low potential side power source; a second PMOS transistor and a second NMOS transistor connected in series between said high-potential side power source and said low potential side power source; an output terminal connected to a junction between said first PMOS and first NMOS transistors, and to a junction between said second PMOS and second NMOS transistors, for outputting an output signal; a first logic circuit for switching ON both of said first PMOS and second PMOS transistors, or both of said first NMOS and second NMOS transistors in response to a logic level of said output signal; a second logic circuit for switching OFF said first PMOS and second PMOS transistors in response to a mode control signal; and a third logic circuit for detecting a logic state of said output signal and outputting a feedback signal, wherein said first logic circuit switches OFF one of said first PMOS and second PMOS transistors, or one of said first NMOS and second NMOS transistors in response to the feedback signal.