Patent ID: 7227214
Filing Date: 2007-06-05
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; Nth number of metallic wiring layers (provided that N is an integer equal to or greater than 3) laminated respectively via an insulating film above the upper portion of said semiconductor substrate; a capacitor element composed of a lower electrode, a capacitance insulating film, and an upper electrode formed above said semiconductor substrate, wherein the lower electrode of said capacitor element is formed in an (Nth−1) wiring layer which is immediately under the uppermost wiring layer, said capacitance insulating film and said upper electrode are formed between said (Nth−1) wiring layer and said Nth wiring layer, and said upper electrode is formed via the insulating film under the uppermost wiring layer, and said upper electrode is in electrical connection with a wiring of said (Nth−1) wiring layer without said Nth wiring layer interposed therebetween; and a shield fully covering the upper portion of said capacitor element and the shield is formed in said Nth wiring layer which is an uppermost layer, and not electrically connected to the upper electrode and the lower electrode of the capacitor, wherein a wiring which is electrically connected to the upper electrode and the lower electrode of the capacitor does not exist above the capacitor, and wherein said shield is retained at a fixed voltage that is greater than zero.