Patent ID: 9164853
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A multi-core re-initialization system comprising: a processor, including a plurality of cores, a re-initialization logic element configured to re-initialize one or more cores of a multi-core processor in an idle mode, and an error capture register configured to capture an error code upon a re-initialization failure; and a hypervisor, communicatively coupled with the processor, configured to detect the re-initialization failure, to determine from the error code of the error capture registers whether the re-initialization failure is a permanent failure, to determine which of the plurality of cores are initialized and which of the plurality of cores are indeterminate, and to allocate the re-initialized cores to one or more virtual machines, wherein the hypervisor configured to determine which of the plurality of cores are initialized and which of the plurality of cores are indeterminate includes determining whether the permanent failure is related to the re-initialization logic element; if the permanent error is related to the re-initialization logic element, then the core being re-initialized and remaining uninitialized cores are considered indeterminate; if the permanent failure is not related to the re-initialization logic element and related to the core being re-initialized, then the core being re-initialized may be considered indeterminate.