Patent ID: 6574133
Filing Date: 2003-06-03
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cell blocks each including a serial connection of at least a plurality of memory cells each including a cell transistor and a ferroelectric capacitor connected in parallel between source and drain terminals of said cell transistor; a plurality of word lines connected to said cell transistors; a plurality of bit line pairs connected to said memory cell blocks; a plurality of amplifier circuits connected to said bit line pairs to amplify a signal difference between bit lines in each of said bit line pair; and a dummy cell circuit to generate a potential for one of said bit line pair, which is a reference bit line to which data is not read out from said memory cells, said dummy cell circuit including at least one paraelectric capacitor; wherein in a standby mode, a first terminal of said paraelectric capacitor is pre-charged to a first potential higher than ground potential, and a second terminal of said paraelectric capacitor is pre-charged to ground potential; and in an active mode, said first terminal is connected to said reference bit line, and said second terminal is raised from ground potential to a second potential higher than ground potential.