Patent ID: 6163584
Filing Date: 2000-12-19
Classification: H03K,H04L

Abstract:
A synchronization element for converting an asynchronous pulse signal into a synchronous pulse signal which receives an input signal, a clock signal and a reset signal and transmits an output signal, the synchronization element comprising:a first flip-flop having a data input terminal electrically connected to a high logic level, a clock input terminal electrically connected to the input signal, a rest data input terminal electrically connected to the rest signal and an output terminal;a second flip-flop having a data input terminal electrically connected to the output terminal of the first flip-flop, a clock input terminal electrically connected to the clock signal, a reset input terminal electrically connected to the reset signal and an output terminal;a first AND gate having a first data input terminal electrically connected to the output terminal of the second flip-flop, a second data input terminal and an output terminal;a third flip-flop having a data input terminal electrically connected to the output terminal of the first AND gate, a clock input terminal electrically connected to the clock signal, a reset input terminal electrically connected to the reset signal and an output terminal electrically connected to the output signal;an inverter having a data input terminal electrically connected to the clock signal and an output terminal;a fourth flip-flop having a data input terminal electrically connected to the output terminal of the third flip-flop, a clock input terminal electrically connected to the output terminal of the inverter, a reset input terminal electrically connected to the reset signal and a complementary output terminal electrically connected to the second data input terminal of the first AND gate;an NAND gate having both input terminals electrically connected to the output terminal of the third flip-flop and the complement output terminal of the fourth flip-flop, respectively, and an output terminal; anda second AND gate having both input terminals electrically connected to the reset signal and the output terminal of the NAND gate, respectively, and an output terminal.