Patent ID: 6693461
Filing Date: 2004-02-17
Classification: H03K

Abstract:
A domino circuit having an evaluation phase and a pre-charge phase, the domino circuit comprising:a second stage comprising a n-logic block, the n-logic block comprising a nMOSFET having a gate and a source; and a first stage to drive the nMOSFET ON and OFF, the first stage comprising a p-logic block and a pulldown to pull the gate of the nMOSFET to a first voltage during the pre-charge phase, wherein the source of the nMOSFET is at a second voltage during the evaluation phase, wherein the second voltage is greater than the first voltage; and a third stage comprising a p-logic block, the p-logic block of the third stage comprising a pMOSFET having a gate and a source, wherein the pMOSFET source is at a third voltage during the evaluation phase; wherein the second stage further comprises a pullup to pull the gate of the pMOSFET to a fourth voltage during the pre-charge phase, wherein the fourth voltage is greater than the third voltage, and the third voltage is greater than the second voltage.