Patent ID: 7478373
Filing Date: 2009-01-13
Classification: G06F

Abstract:
1. A processor coupled to a computer memory, the processor configured to: determine a target platform of a non-native program module, the non-native program module having non-native instructions associated therewith, determine the type of non-native instructions and CPU simulator of a non-native kernel emulator associated with the target platform, constrain the memory addressable by the non-native program module such that the non-native program module may only address a portion of the memory, wherein the processor is further configured to establish data structures for target process environment blocks (PEBs) and target thread environment block (TEBs), the target PEBs and TEBs being in a format of the non-native program module, and further synchronize native and target TEBs and PEBs, and execute the non-native instructions by translating at least one of the non-native instructions into a corresponding native instruction by the non-native kernel emulator, and kernel communicating the corresponding native instruction to a native kernel by the non-native kernel emulator so that kernel calls from the non-native program module are dynamically converted into native kernel calls.