Patent ID: 7977962
Filing Date: 2011-07-12
Classification: G01R,G11C,H01L

Abstract:
1. An apparatus, comprising: a floating potential reference, the floating potential reference being a first voltage reference source; a plurality of operational amplifiers in a first chip of a plurality of chips, the plurality of chips arranged in a vertical stack, each one connected between the floating potential reference and a top portion of one of a plurality of series connected electrical through substrate vias in the vertical stack; a plurality of enable switches in a second chip of the plurality of chips in the vertical stack, each connected between a bottom portion of the plurality of series connected electrical through substrate vias and a second potential reference, the second potential reference being a second voltage reference source; a first resistor connected between the second potential reference and a power supply; and a second resistor connected between the second potential reference and a bottom portion of a test series connected electrical through substrate vias, where a top portion of the test series connected electrical through substrate vias are connected to the floating potential reference.