Patent ID: 6323125
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A method of using a dual damascene technique to form a conductive contact to a semiconductor device comprising:providing a substrate having a first insulating layer thereon;depositing a second insulating layer over said first insulating layer;patterning and etching of said second insulating layer to form via opening through said second insulating layer;depositing a first conductive metal layer into second insulating layer;removing the excess first conductive metal layer by CMP;depositing a third insulating layer over said second insulating layer patterning and etching said third insulating layer to form trench openings;depositing a layer of Plasma Polymerized Methylsilane (PPMS), a photosensitive polymer;exposing PPMS to UV light to form Plasma Polymerized Methylsilane Oxide (PPMSO), while blocking out the UV light in the trench and via openings;removing unexposed PPMS from the trench and via opening;depositing a barrier conducting layer which lines trench and via region and whereby said layer acts as a diffusion barrier and a CMP etch stop;depositing a second conductive metal layer to fill the remaining trench and via region and planarizing the excess second metal conductive layer by CMP without metal dishing.