Patent ID: 6088517
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A master device for providing a processor access to a shared register at a compatible address, the shared register being shared by at least two slave devices, each slave device providing access to the shared register at a unique address, the master device for coupling between the processor and the slave devices, the master device comprising:cycle decoder logic receiving a cycle from the processor requesting access to the shared register at the compatible address;transaction initiator logic coupled to the cycle decoder logic, the transaction initiator logic translating the received cycle into a transaction, the transaction having a unique address corresponding to a slave device shared register;initiator logic coupled to the transaction initiator logic, the initiator logic providing the transaction;decoder logic coupled to the transaction initiator logic, the decoder logic receiving a response from the slave device; andretry request logic coupled to the decoder logic, the retry logic providing a response to the processor after the decoder logic receives the response.