Patent ID: 7477186
Filing Date: 2009-01-13
Classification: G01S,G11C

Abstract:
1. A memory system, comprising: an array of storage cells arranged in a row and column arrangement; a plurality of data write lines coupled to the array and configured to supply data into a selected row of the array; a plurality of data read lines coupled to the array and configured to receive data from a plurality of cells of a selected column of the array in a single read operation; an arithmetic operation circuit coupled to the plurality of data read lines that is configured to generate a result value based on data read from the storage cells of a selected column of the array, wherein the arithmetic operation circuit comprises a pattern detector configured to detect a pattern based on a comparison of the data read from the storage cells of the selected column of the array to a candidate pattern and to provide a pattern detect signal as the result value; and a control circuit configured to select the storage cells in a selected row of the array responsive to a write address input signal by coupling the data write lines to the storage cells in the selected row and to select the storage cells in a selected column of the array responsive to a read address input signal by coupling the data read lines to the storage cells in the selected column to provide data from the storage cells in the selected column to the arithmetic operation circuit.