Patent ID: 6252264
Filing Date: 2001-06-26
Classification: H01L

Abstract:
An integrated circuit chip having a first i/o set associated with a first edge of a chip and a second i/o set associated with a second edge of the chip,wherein with other such chips disposed on a carrier, a physical arrangement of the first and second i/o sets is such that the first i/o set of the chip is capable of being aligned with the second i/o set of a first one of the other chips, and the second i/o set of the chip is capable of being aligned with the first i/o set of a second one of the other chips, so that the chip is capable of being electrically interconnected to the first and second other such chips by substantially straight buses disposed on the carrier;wherein the chip has a bus disposed on the chip and the first and second i/o sets each have a respective first i/o subset coupled to the chip-disposed bus and for coupling to a respective one of the carrier-disposed buses so that signals between the first and second ones of the other chips may traverse the chip.