Patent ID: 9207261
Filing Date: 2015-12-08
Classification: G01R,Y10T

Abstract:
1. A probe card for wafer level test, comprising: a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes a first surface having a first pitch and a second surface having a second pitch substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board; and a second power plane disposed on a surface of the printed circuit board and patterned to couple the power line and the ground line of the space transformer to the printed circuit board, wherein the second power plane is in electrical connection with the first power plane, the first and second power planes each include a plurality of conductive plates, and the conductive plates each have a greater contact area than a structure coupling the signal lines of the spacer transformer.