Patent ID: 6539072
Filing Date: 2003-03-25
Classification: G06F,G11C,H03K,H03L,H04L

Abstract:
A clock alignment circuit, comprising:a first adjustable delay circuit having a plurality of delay elements to output a plurality of clock signals, each clock signal having a delay time with respect to a reference clock signal, and a respective phase controlled by a delay adjustment signal; first detector circuitry coupled to the first adjustable delay circuit to compare a phase of a first clock signal of the plurality of clock signals with a phase of the reference clock signal, and to output phase differential information which is representative of a phase differential between the first clock signal and the reference clock signal; a first control circuit coupled to the first detector circuitry to output the delay adjustment signal, wherein the delay adjustment signal is representative of the phase differential information of the first detector circuitry; interpolator circuitry to generate a second clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the second clock signal is interpolated from respective phases of the pair of clock signals in response to a phase adjustment signal; a second adjustable delay circuit to output a third clock signal having a delay time with respect to the second clock signal, wherein the delay time of the third clock signal is responsive to the delay adjustment signal; second detector circuitry coupled to the second adjustable delay circuit to compare the phase of the third clock signal with the phase of an input clock signal, and to output phase differential information which is representative of a phase differential between the third clock signal and the input clock signal; and a second control circuit coupled to the second detector circuitry to output the phase adjustment signal, wherein the phase adjustment signal is representative of the phase differential information of the second detector circuitry.