Patent ID: 9006108
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A method of forming a Field Effect Transistor (FET) device, the method comprising: forming a gate stack comprising a gate dielectric, a conductive material, and a spacer, the gate stack formed over a channel region having a thickness of less than 40 nanometers (nm), the channel region defined in a silicon layer disposed over a buried oxide layer; forming a first recess adjacent the gate stack, said first recess having sidewalls and a bottom surface through a first portion of the silicon layer; passivating the bottom surface of the first recess to form a first passivating layer, the first passivating layer having a thickness that is less than a depth of the first recess such that a portion of the sidewall of the first recess remains exposed and unobscured by the first passivating layer; etching the exposed sidewall of the first recess in the silicon layer for a predetermined lateral distance underneath the gate stack; removing the first passivating layer from the first recess; etching said bottom surface of the first recess to a target vertical etch depth; forming a second recess adjacent the gate stack, opposite the first recess, the second recess having sidewalls and a bottom surface through a second portion of the silicon containing region; passivating the bottom surface of the second recess to form a second passivating layer, the second passivating layer having a thickness that is less than a depth of the second recess such that a portion of the sidewall of the second recess remains exposed and unobscured by the second passivating layer; etching the exposed sidewall of the second recess in the silicon layer for a predetermined lateral distance underneath the gate stack; removing the second passivating layer from the second recess; and etching the bottom surface of the second recess to a target vertical etch depth; wherein both the first and second recesses are equidistant in both horizontal and vertical directions and are less than 40 nanometers (nm) equidistant in both horizontal and vertical directions, and wherein the horizontal direction begins at an outer edge of the sidewall of the gate stack and ends at a location beneath the gate stack.