Patent ID: 6279106
Filing Date: 2001-08-21
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache configured to receive and store instruction bytes, wherein the instruction cache is configured to receive a fetch address and in response thereto output one or more of the instruction bytes corresponding to the fetch address,a branch selector array configured to store a plurality of selector bits, wherein each selector bit corresponds to a particular instruction byte stored in the instruction cache, wherein the branch selector array is configured to receive the fetch address and in response thereto output one or more corresponding selector bits that are indicative of a source for a predicted next fetch address,a sequential address adder configured to sum the fetch address with a fetch block size to generate a next sequential address,an indirect branch target cache configured to store predicted branch target addresses for indirect branch instructions stored in the instruction cache, wherein the indirect branch target cache is configured to receive the fetch address and output a corresponding indirect branch address,a direct branch adder configured to sum the fetch address with an offset from the instruction bytes output by the instruction cache to calculate a direct branch address, anda multiplexer configured to receive the one or more corresponding selector bits from the branch selector array, wherein the multiplexer is configured to select either the next sequential address, the direct branch address, or the indirect branch address based on the selector bits.