Patent ID: 7557400
Filing Date: 2009-07-07
Classification: H01L,H02M

Abstract:
1. A semiconductor device comprising: a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting the drain region and source region of said MOS capacitor, and the MOS structure has a first conductivity type well formed on a second conductivity type semiconductor substrate, second conductivity type diffusion layers serving as the drain region and the source region which are selectively formed in the surface of the first conductivity type well, a gate insulating film provided on a region between the second conductivity type diffusion layers, the gate electrode provided on the gate insulating film, and a first conductivity type diffusion layer for applying a voltage to a back gate which is formed in the first conductivity type well so as to surround the second conductivity type diffusion layers.