Patent ID: 8928083
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. An electronic device, comprising: a semiconductor-on-insulator (SOI) wafer having a SOI layer on a buried oxide (BOX) and an oxide layer on a side of the SOI layer opposite the BOX, and wherein at least one first set of fins is patterned in the SOI layer and the oxide layer and at least one second set of fins is patterned in the SOI layer and the oxide layer such that the first set of fins and the second set of fins each includes multiple fins with each of the fins having a SOI portion on the BOX and an oxide portion on a side of the SOI portion opposite the BOX; a conformal gate dielectric layer on a portion of each of the first set of fins that serves as a channel region of a transistor device; a first metal gate stack on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device; and a second metal gate stack on a portion of each of the second set of fins that serves as a channel region of a diode device.