Patent ID: 6212596
Filing Date: 2001-04-03
Classification: G06F,G11C

Abstract:
A synchronous memory, comprising:a memory array arranged in rows and columns of memory cells, each memory cell arranged to store a respective data bit;a control circuit coupled to receive a system clock signal and a binary select signal, the control circuit arranged to produce a control signal;a row address circuit arranged to latch a row address signal in response to the system clock signal and the binary select signal, the row address circuit arranged to select at least one row from the rows of memory cells; anda column address circuit arranged to latch a column address signal in response to the system clock signal and the binary select signal, the column address circuit arranged to produce a number of column address signals corresponding to the control signal, wherein the column address signals are produced in synchronization with the system clock signal, and wherein each column address signal corresponds to at least one column of memory cells from the columns of memory cells.