Patent ID: 6090679
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method for forming a bottom storage node of a DRAM capacitor on a substrate, the method comprising the steps offorming a first insulating layer onto said substrate;forming a barrier layer onto said first insulating layer;patterning and etching said first insulating layer and said barrier layer, and stopping at said substrate, to form a contact opening;forming an amorphous silicon plug into said contact opening;forming a second insulating layer onto said amorphous silicon plug and said barrier layer;patterning and etching said second insulating layer, stopping at said barrier layer, to form a trench above said amorphous silicon plug;forming a bottom amorphous silicon layer along the bottom and sidewalls of said trench;forming a middle amorphous silicon layer atop said bottom amorphous silicon layer;forming a top amorphous silicon layer atop said middle amorphous silicon layer, wherein said top amorphous silicon layer is undoped, and wherein said middle amorphous silicon layer and said bottom amorphous silicon layer have different dopant concentrations greater than zero;removing said second insulating layer;removing said barrier layer to expose a portion of said amorphous silicon plug; andforming a hemispherical grain (HSG) polysilicon layer on surfaces of said top amorphous silicon layer and said bottom amorphous silicon layer and on exposed portion of said amorphous silicon plug.