Patent ID: 8199572
Filing Date: 2012-06-12
Classification: G11C

Abstract:
1. A memory array, comprising: a number of strings of memory cells each including a number of memory cells coupled in series between a first select gate at a first end of the string and a second select gate at a second end of the string; wherein for each of the strings of memory cells: wherein the number of memory cells operated as multiple level memory cells are configured to have a lower page programming process and an upper page programming process performed thereon; wherein the number of memory cells operated as multiple level memory cells are comprised of a lower page and at least one upper page of data and the first and second memory cells operated as single level memory cells are comprised of a single page of data; and wherein the first memory cell operated as a single level cell has a programmed voltage that is less than a lowest programmed voltage of the at least one upper page of data of the number of memory cells operated as multiple level memory cells and that is greater than a resting voltage of the first select gate.