Patent ID: 6621744
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A semiconductor memory device, comprising:memory cells; reference cells; sub-bit lines, at least the memory cells or the reference cells being connected to the sub-bit lines; a first selection gate; a second selection gate; a main bit line, the sub-bit lines being connected via the first selection gate to the main bit line; complementary sub bit lines, at least the other of the memory cells and the reference cells being connected to the complementary sub-bit line; a complementary main bit line, the complementary sub-bit lines being connected via the second selection gate to the complementary main bit line; word lines corresponding to the memory cells; reference word lines corresponding to the reference cells; a word line driving section for selectively activating at least one of the word lines; a reference word line driving section for selectively activating at least one of the reference word lines; and a control section for outputting a selection gate signal to the first and second selection gates, the selection gate signal activating the first and second selection gates, the time of activating the first and second selection gates being delayed from the time of activating the word lines and the reference word lines to an extent that potential inversion does not occur between the main bit line and the complementary main bit line, wherein information is read from the memory cells via the main bit line and the complementary main bit line.