Patent ID: 8304875
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A semiconductor package comprising: a first semiconductor sub-package having a connection face with connectors that are un-supported by protective encapsulation material depending therefrom arranged to electrically connect an active surface of a first semiconductor device contained therein to an external circuit, and at least one second semiconductor sub-package also having connectors that are un-supported by protective encapsulation material depending therefrom arranged to electrically connect a second semiconductor device contained therein to an external circuit, the second semiconductor sub-package also having an attachment face, on an opposite side thereof from the connection face; wherein the second semiconductor sub-package is mounted on the first semiconductor sub-package such that its attachment face is coupled to the connection face of the first semiconductor sub-package, and wherein the first semiconductor sub-package is a Wafer Level Chip-Scale Package comprising the first semiconductor device with packaging layers deposited on its active surface.