Patent ID: 6753236
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method for equalizing different levels on a surface of an isolating layer deposited on a semiconductor body of an integrated semiconductor circuit configuration, the surface lying at a higher level in first zones of the integrated semiconductor circuit configuration than in second zones of the integrated semiconductor circuit configuration, which comprises the steps of:providing active zones separated by a shallow trench insulation (STI) layer configured as the isolating layer to the surface on the semiconductor body in each of the first zones and the second zones; forming a first level and a second level between an upper edge of the active zones and an upper edge of the STI layer in each of the first zones and the second zones, the first level of the first zones being greater than the corresponding second level of the second zones; covering the second zones with a block mask; and etching the isolating layer in the first zones until achieving an equalization between the first level and the second level.