Patent ID: 7423899
Filing Date: 2008-09-09
Classification: G11C

Abstract:
1. A static random access memory (SRAM) device comprising: a first transistor pair to couple between a supply voltage line and GROUND; a second transistor pair to couple between the supply voltage line and GROUND, the supply voltage line to receive a first supply voltage when the SRAM memory device is in an ACTIVE mode and to receive a second supply voltage when the SRAM memory device is in a STANDBY mode, the second supply voltage being different than the first supply voltage; a first access transistor to couple to a word line, a first bit line and a common node of the second transistor pair; a second access transistor to couple to the word line, a second bit line and a common node of the first transistor pair; and a bias transistor to couple to a body of one of the transistors of the first transistor pair and to a body of one of the transistors of the second transistor pair, the bias transistor to apply a forward body bias to the one transistor of the first transistor pair and to the one transistor of the second transistor pair when the SRAM memory device is in the STANDBY mode, wherein a gate of the bias transistor is coupled to a signal line to receive a STANDBY signal indicative of the STANDBY mode of the SRAM memory device.