Patent ID: 6192433
Filing Date: 2001-02-20
Classification: G06F

Abstract:
A processing system including a pair of central processing units (CPUs) and a storage unit interconnected for data communication by first and second small computer system interface (SCSI) bus segments that respectively connect each of the pair of CPUs to the storage unit, the first and second SCSI bus segments carrying termination power signals, apparatus for providing impedance terminations at the storage unit in the event the SCSI bus connecting the storage unit to one of the pair of CPUs is disconnected, or one of the pair of CPUs losses power, the apparatus comprising:first and second bus switch units respectively coupling the first and second SCSI bus segments to a third SCSI bus segment, the first and second bus switch units being connected to receive the termination power signals;a SCSI termination circuit coupled to receive the termination power signals;whereby, when the termination power signal is absent from the first SCSI bus segment, the first bus switch unit de-couples the first SCSI bus from the storage unit and the SCSI termination circuit couples a SCSI termination impedance to the third SCSI bus segment.