Patent ID: 8836019
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A recessed channel transistor, comprising: a gate structure on a substrate, the gate structure filling a recess in the substrate; a first impurity region at a first upper portion of the substrate adjacent to the gate structure, the first impurity region including a plurality of first impurities; and a second impurity region at a second upper portion of the substrate contacting the gate structure, the second impurity region including a plurality of second impurities having a conductive type different from that of the plurality of first impurities, and the first impurity region surrounding the second impurity region, wherein the first and second impurity regions are at an upper surface of the substrate, wherein the second impurity region is in the first impurity region, and a bottom of the first impurity region is lower than a bottom of the second impurity region, wherein the gate structure includes, wherein the gate insulation layer and the gate electrode are on an upper surface of the substrate adjacent to the recess such that both ends of the gate electrode and both ends of the gate insulation layer are aligned with a peripheral edge of the second impurity region.