Patent ID: 8856480
Filing Date: 2014-10-07
Classification: G06F,G11C

Abstract:
1. A memory device, comprising: at least two electrically isolated memory portions, each portion including banks of memory and circuitry to write and read data to the respective bank in association with memory write and read transactions; interface circuitry to receive commands and to exchange the write and read data external to the apparatus in association with the memory write and read transactions; and logic to identify based on the commands one of the at least two electrically isolated portions that is the target of each transaction of the memory write and read transactions, and to route said each write and read transaction to said target; wherein each given portion of the at least two electrically isolated portion is characterized by a timing constraint that must elapse between row activations within the given portion, and wherein the memory device is characterized as having no timing constraint imposed on when a first portion of the at least two electrically isolated portions can be accessed relative to a second portion of the at least two electrically isolated portions.