Patent ID: 6707738
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cell arrays arranged in a matrix, each of the plurality of memory cell arrays having a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells; a plurality of bit line precharge circuit units for precharging and equalizing corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages; and a first precharge voltage line and a second precharge voltage line arranged in each region between the plurality of memory cell arrays, wherein during a first mode of operation, the first precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second mode of operation, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages.