Patent ID: 6529049
Filing Date: 2003-03-04
Classification: G11C

Abstract:
A buffered sample-and-hold circuit for sampling an analog voltage, comprising in combination:a. a source of an analog voltage to be sampled; b. a first sampling capacitor; c. a first switch interposed between the analog voltage source and the first sampling capacitor for selectively coupling the analog voltage sourced by the analog voltage source to the first sampling capacitor; d. an amplifier having an input terminal and an output terminal; e. a second switch interposed between the first sampling capacitor and the input terminal of the amplifier for selectively coupling a voltage stored on the first sampling capacitor to the input terminal of the amplifier; f. a second sampling capacitor; g. a third switch interposed between the analog voltage source and the second sampling capacitor for selectively coupling the analog voltage sourced by the analog voltage source to the second sampling capacitor; h. a fourth switch interposed between the second sampling capacitor and the input terminal of the amplifier for selectively coupling a voltage stored on the second sampling capacitor to the input terminal of the amplifier; and i. control means for closing the first and third switches, and opening the second and fourth switches, to sample the sourced analog voltage across the first and second sampling capacitors, said control means thereafter temporarily closing the fourth switch to pre-charge the input terminal of the amplifier with the analog voltage sampled by the second sampling capacitor, said control means thereafter opening the fourth switch and closing the second switch to couple the analog voltage sampled by the first sampling capacitor to the input terminal of the amplifier.