Patent ID: 8010853
Filing Date: 2011-08-30
Classification: G11C

Abstract:
1. A semiconductor storage device, comprising: a plurality of memories comprising one memory having a large number of bits and at least two or more memories having a small number of bits, where the total number of bits of the at least two or more memories having a smaller number of bits is smaller than the number of bits of the one memory having a large number of bits; a plurality of nonmatching detection circuits, each of which is provided for every single bit of the one memory having the large number of bits and the two or more memories having the small number of bits, compares bit output of each of the plurality of memories with an expected value corresponding to the bit output, and each of which outputs a nonmatching detection signal when the bit output and the expected value do not match each other; a selection circuit selecting and holding either a nonmatching detection signal that corresponds to a bit belonging to the first group of the bits of the one memory having the large number of bits or a nonmatching detection signal that corresponds to a bit of a memory out of the two or more memories having the small number of bits; the selection circuit selecting and holding separately a nonmatching detection signal that corresponds to a bit belonging to a second group different from the first group of the bits of the memory having the large number of bits or a nonmatching detection signal that corresponds to a bit of another memory out of the two or more memories having the small number of bits; and a plurality of nonmatching result holding circuits adapted to store a plurality of bit outputs from different memories, each of the nonmatching result holding circuits holding the nonmatching detection signal output from a corresponding one of the nonmatching detection circuits selected by the selection circuit.