Patent ID: 8970313
Filing Date: 2015-03-03
Classification: H03K

Abstract:
1. A method to achieve CMOS oscillators enabled for small technology nodes below 250 nm comprising the steps of (1) providing a relaxation oscillator comprising only one capacitive element, a current source configured to providing current for charging the capacitive element, a comparator, a logic circuitry, and a CMOS switching network, configured to alternatingly charging one terminal of the capacitive element up to a level of a reference level and connecting another terminal of the capacitive element to VSS voltage; (2) implementing the CMOS switching network built by a triple-well P-substrate CMOS process preventing any leakage to substrate, allowing nodes at a first and a second terminal of the capacitive element to rise and fall alternatingly between the reference voltage and VSS voltage; (3) eliminating latch-up risks by forming all NMOS devices in local p-wells which sit in an isolating deep N-well; (4) starting a first of two symmetrical phases wherein a node at a first terminal of the capacitive element is switched to VSS voltage and a node at a second terminal of the capacitive element is charged to the reference voltage; (5) starting a second of the two symmetrical phases when the node at the second terminal of the capacitive element reaches a potential equal to the reference voltage, wherein in the second phase the node at the second terminal is switched to VSS voltage and the node at the first terminal of the capacitive element is charged up to a potential equal of the reference voltage; and (6) going back to step (3) when the node of the first terminal reaches the reference voltage and repeat a cycle of the first and the second phases.