Patent ID: 6969651
Filing Date: 2005-11-29
Classification: B82Y,G11C,H01L,Y10S

Abstract:
1. A method of forming a nanotube memory cell on a semiconductor substrate, the method comprising: forming a first silicon filled chamber overlying a first and second contact formed in the substrate; forming a nanotube layer on the first silicon filled chamber, the nanotube layer overlying the first contact and not overlying a second portion of the first silicon filled chamber, the second portion overlying the second contact; forming a second silicon filled chamber directly on the nanotube layer; forming a dielectric layer on the second silicon filled chamber; patterning the dielectric layer to form an access contact hole exposing the second silicon filled chamber, the contact hole formed to overlay the second portion of the first chamber; etching the first and second silicon filled chambers using the contact hole to remove the silicon; and depositing a conductive material on the dielectric layer such that the conductive material makes contact with the second contact and closes the aperture created by the contact hole.