Patent ID: 9015369
Filing Date: 2015-04-21
Classification: G06F

Abstract:
1. A data transferring apparatus comprising: a processor that generates data to be processed; a first memory that stores the data generated by the processor; a processing unit that processes the data generated by the processor; a transferring unit that burst transfers the data from the first memory to the processing unit; a second memory that stores information concerning time that the processing unit consumes to process the data; a third memory that stores a prescribed value for a burst width set based on an access capability of the processor when accessing the first memory; a calculating unit that calculates time that the transferring unit is allowed to consume for transfer of the data, based on the information that concerns the time that the processing unit consumes to process the data and is stored in the second memory; and a determining unit that based on an estimated time that the transferring unit is expected to consume for the transfer of the data, determines a burst width to be used for the transfer of the data by the transferring unit to be a value that is greater than or equal to the prescribed value for the burst width stored in the third memory and that is as close as possible to the prescribed value for the burst width, within a range in which the transfer of the data is finished within the time allowed for the transfer of the data calculated by the calculating unit, wherein the prescribed value for the burst width is a burst width at which a sum of the access capability of the processor when accessing the first memory and a capability of the transferring unit when burst transferring the data from the first memory becomes maximum, the burst width being calculated in advance in an environment in which the processor and the transferring unit access the first memory.