Patent ID: 6677798
Filing Date: 2004-01-13
Classification: H03K

Abstract:
A voltage level shifter comprising:an input terminal, for receiving a non-inverted input signal having a first voltage level and a second voltage level, wherein the first voltage level is a reference voltage level and the second voltage level is higher than the first voltage level; a boost circuit receiving the non-inverted input signal, for producing a boosted signal in accordance with the non-inverted input signal, the boosted signal at a third voltage level when the non-inverted input signal is at the first voltage level, and at the first voltage level when the non-inverted input signal is at the second voltage level, wherein the third voltage level is higher than the second voltage level; a voltage shifting stage coupled to the boost circuit, for producing an output signal in response to an inverted input signal and the boosted signal, the output signal at a fourth voltage level when the inverted input signal and the boosted signal are both at the first voltage level, and at the first voltage level when the inverted input signal is at the second voltage level and the boosted signal is at the third voltage level, the voltage shifting stage comprising: a first N-type transistor having a gate, a source and a drain, where the source of the first N-type transistor is connected to a first node to receive the inverted input signal, the gate of the first N-type transistor is coupled to a first power source having the second voltage level; a second N-type transistor having a gate, a source and a drain, where the source of the second N-type transistor is coupled to the first voltage level, the gate of the second N-type transistor is disconnected from the drain of the first N-type transistor and connected to the boost circuit to receive the boosted signal; a first P-type transistor having a gate, a source and a drain, where the source of the first P-type transistor is coupled to a second power source having the fourth voltage level, the drain of the first P-type transistor is connected to the drain of the first N-type transistor, and the gate of the first P-type transistor is connected to the drain of the second N-type transistor; and a second P-type transistor having a gate, a source and a drain, where the source of the second P-type transistor is coupled to the second power source, the drain of the second P-type transistor is connected to the drain of the second N-type transistor, and the gate of the second P-type transistor is connected to the drain of the first N-type transistor; and an output terminal coupled to the drain of the second N-type transistor and the drain of the second P-type transistor, for providing the output signal which has an output voltage swing between the first voltage level and the fourth voltage level.