Patent ID: 6117790
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method for fabricating a capacitor for a semiconductor memory configuration, which comprises:a) providing a semiconductor body formed of a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, and a conductive support layer disposed on the insulating layer, the insulating layer having a contact hole formed therein connecting the semiconductor substrate to the conductive support layer;b) applying a selectively etchable material to the conductive support layer;c) patterning the selectively etchable material resulting in a patterned material;d) applying a first conductive layer to the patterned material for forming at least part of a first capacitor electrode;e) patterning the first conductive layer;f) forming an opening in the first conductive layer covering the patterned material formed from the selectively etchable material;g) etching out the selectively etchable material resulting in a cavity formed under the first conductive layer;h) coating an inner surface of the cavity and an outer surface of the first conductive layer with a dielectric layer;i) applying a second conductive layer to the dielectric layer for forming a second capacitor electrode; andj) patterning the second conductive layer.