Patent ID: 6060753
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A low-noise output stage for an electronic circuit integrated on a semiconductor substrate having a first terminal for connecting to a first reference potential and a second terminal for connecting to a second reference potential, the low noise output stage comprising:an output terminal to connect to an external load;a CMOS transistor pair including a P-channel pull-up transistor and an N-channel pull-down transistor, the P-channel pull-up transistor being coupled between the first terminal and the output terminal and the N-channel pull-down transistor being coupled between the output terminal and the second terminal; andwherein the pull-down transistor is formed in a three-well structure to prevent propagation of a discharge current from the external load through the semiconductor substrate;wherein a first contact region of an N+ type for connecting to the first terminal is formed between the first and second wells on a surface of the substrate.