Patent ID: 7242241
Filing Date: 2007-07-10
Classification: G05F

Abstract:
1. A reference circuit comprising first and second field effect transistors connected to form a first current mirror, and third and fourth field effect transistors connected to form a second current mirror, the drains of the first and second transistors being coupled to the drains of the third and fourth transistors respectively, wherein a property of the first transistor is mismatched relative to the second transistor such that the threshold voltage of the first transistor is significantly higher than the threshold voltage of the second transistor, and the drain current versus gate-source voltage responses of the first and second transistors have substantially different gradients for current levels at which the reference circuit is operated so that, for a particular voltage applied to the common gate of the first transistor and the second transistor, the second transistor operates substantially in its strong inversion saturation region whilst the first transistor operates substantially in its weak inversion saturation region to allow a constant current to be generated.