Patent ID: 7420791
Filing Date: 2008-09-02
Classification: G01R

Abstract:
1. A power management integrated circuit (IC), comprising: a dual purpose pin that performs a power management function during normal operation; a fault detection system that senses a plurality of fault conditions and that provides a corresponding plurality of fault indicator signals, each fault indicator signal indicating a corresponding fault condition; a fault signature system, coupled to said dual purpose pin, that generates a selected one of a plurality of fault signature signals on said dual purpose pin in response to said fault detection system providing a corresponding one of said plurality of fault indicator signals, each fault signature signal having a characteristic uniquely identifying only one of said plurality of fault conditions; at least one external component coupled to said dual purpose pin; a plurality of internal components, each corresponding to one of said plurality of fault conditions; and a switch circuit which internally couples said dual purpose pin to a corresponding one of said plurality of internal components in response to assertion of a corresponding one of said plurality of fault indicator signals; wherein each of said plurality of fault signature signals, when generated, is generated only said dual purpose pin.