Patent ID: 8896358
Filing Date: 2014-11-25
Classification: H03K

Abstract:
1. A phase interpolator, comprising: an adaptively biased phase mixer having mixing transistor circuitry configured to provide an output phase signal corresponding to a selected phase in response to a plurality of phase control signals, a bias current, and a plurality of phase input signals offset in phase from one another, the adaptively biased phase mixer further having adjustable bias transistor circuitry configured to adjust the bias current provided to the mixing transistor circuitry in response to an adaptive bias signal, the adaptively biased phase mixer comprising a plurality of buffer circuits, each buffer circuit receiving one of the plurality of phase input signals and the adaptive bias signal, each buffer circuit comprising a plurality of mixing transistors of the mixing transistor circuitry and a plurality of bias transistors of the adjustable bias transistor circuitry, the plurality of mixing transistors comprising a first group of mixing transistors connected in series with each other, the plurality of bias transistors comprising a first group of bias transistors connected in series with each other, the first group of mixing transistors connected in series with the first group of bias transistors; phase control circuitry providing the plurality of phase control signals to the adaptively biased phase mixer in response to a phase selection signal corresponding to the selected phase; and an adaptive bias generator configured to generate the adaptive bias signal in response to at least one mixer operating condition and to provide the adaptive bias signal directly to the adjustable bias transistor circuitry of the phase mixer.