Patent ID: 6147394
Filing Date: 2000-11-14
Classification: G03F,H01L

Abstract:
An integrated circuit including isolation regions formed by a method for defining three regions on a semiconductor wafer, the method comprising the steps of:a) depositing a layer of pad oxide on said wafer and a layer of pad nitride on said pad oxideb) depositing a layer of hybrid resist on said pad nitride;c) exposing said hybrid resist layer through a mask containing a plurality of shapes such that first portions of said hybrid resist exposed to substantially no exposure and remain photoactive, second portions of said hybrid resist are exposed to an intermediate exposure and become soluble in developer and third portions of said hybrid resist are fully exposed and become insoluble in developer;d) developing said hybrid resist layer such that said second portions of said hybrid resist are removed, said removal defining a first region on said wafer, said first region on said wafer comprising a looped shape defining an exterior perimeter of an isolation structure;e) etching pad nitride selective to said pad oxide and hybrid resist such that said pad nitride in said first region is removed;f) blanket exposing said hybrid resist to an intermediate exposure such that said first portions of said hybrid resist become soluble in developer;g) developing said wafer such that said first portions are removed, said removal defining a second region on said wafer, said second region comprising an interior region of said defined exterior perimeter of the isolation structure;h) etching silicon selective to pad nitride and said third portions of said hybrid resist, said etching forming edge isolation troughs in said wafer;i) removing said pad nitride and said pad oxide in said second region;j) grow oxide in said first and second region on said wafer;k) conformally deposit nitride and directionally etch said nitride to form nitride spacers in said edge isolation troughs;l) conformally deposit oxide such that said edge isolation troughs are filled, said filled isolation troughs forming looped, relatively deep edge isolation structures with relatively shallow isolation structure in the interior of the isolation structure;m) remove remaining nitride; andn) planarizing the wafer.