Patent ID: 6675337
Filing Date: 2004-01-06
Classification: G01R

Abstract:
A built-in verification circuit of an integrated circuit having an input terminal and an output terminal, comprising:a circuit-under-test circuit; a detachable test pattern generator for generating test patterns wherein the test patterns produced by the test pattern generator are based on an input/output port order fault (POF) model; a bi-directional signal flow switch positioned between the input terminal of the built-in verification circuit and an input of the circuit-under-test circuit; a first unidirectional signal flow switch positioned between the input of the circuit-under-test circuit and the test pattern generator for controlling a signal flow from the test pattern generator to the circuit-under-test circuit; a second unidirectional signal flow switch positioned between an output of the circuit-under-test circuit and the output terminal of the built-in verification circuit for controlling a signal flow from the circuit-under-test circuit to the output terminal of the built-in verification circuit; and a third unidirectional signal flow switch positioned between the test pattern generator and the output terminal of the built-in verification circuit for controlling a signal flow from the test pattern generator to the output terminal of the built-in verification circuit, wherein the bi-directional signal flow switch and the first unidirectional signal flow switch arc used for controlling signal flow direction at the input terminal and the test pattern generator, and the second unidirectional signal flow switch and the third unidirectional signal flow switch are used for controlling an output signal to the output terminal of the built-in verification circuit.