Patent ID: 9213063
Filing Date: 2015-12-15
Classification: G01R

Abstract:
1. An integrated circuit (IC) including functional signal pins and test logic, the IC comprising: at least one test instruction register, and a plurality of test data registers including a scan control register; a test access port (TAP) controller that resets outputs of the test instruction register when the test logic is in a Test-Logic-Reset state; a TAP having pins for connection to automatic test equipment (ATE) for input and output signals to and from the TAP controller, the test instruction register and the test data registers; and a reset generation circuit that resets the scan control register when the test logic is in test mode and receives a conjunction of a RESET_B signal on at least one of the functional signal pins and a data input signal from the ATE on at least one other of the functional signal pins, wherein the reset generation circuit receives from the test instruction register a scan mode signal that is asserted when the test logic is enabled.