Patent ID: 8724370
Filing Date: 2014-05-13
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which transitions the variable resistance element from a low resistance state to a high resistance state, to a selected memory cell through a selected first wiring and a selected second wiring, wherein, when applying the control voltage to the memory cell plural times, the control circuit is configured to be capable of changing a value of the control voltage applied in each of control voltage application operations, the control circuit is operable to perform a plurality of control voltage application operations by increasing the value of the control voltage by a first value in each of second and subsequent control voltage application operations, and the control voltage initially applied is substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array for transitioning the resistance state of the variable resistance element in the memory cell from the high resistance state to the low resistance state, and is measured in advance by a die sort test.