Patent ID: 8826035
Filing Date: 2014-09-02
Classification: G06F

Abstract:
1. A processor comprising: a circuit based cryptographic engine to encrypt data to be written to memory, to decrypt data read from memory, to generate read message authentication codes (MACs) and write MACs for read and write memory accesses, to create a cumulative read MAC and a cumulative write MAC by XORing the generated read MAC and the generated write MAC with a current read MAC and a current write MAC respectively, and to validate data integrity by comparing the cumulative read MAC and the cumulative write MAC, wherein for write operations to a memory address the cryptographic engine is to generate the read MAC based on current data stored at the memory address and a currently stored counter value associated with the memory address and the write MAC based on data written to the memory address and a new counter value associated with the write to the memory address, and wherein for read operations to a memory address the cryptographic engine is to generate the read MAC based on current data stored at the memory address and the currently stored counter value associated with the memory address and the write MAC based on current data stored at the memory address and the new counter value associated with the read from the memory address; a register to store the cumulative read MAC; a register to store the cumulative write MAC; and a register to maintain a counter value for memory accesses, wherein the new counter value includes an unpredictable randomly generated portion.