Patent ID: 6657308
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A partially fabricated contact well for a semiconductor device comprising:a substrate having a doped region extending to a surface of said substrate; a gate insulating layer disposed adjacent said doped region and overlying said surface of said substrate; a gate disposed over said gate insulating layer; a first insulating layer etchable by a first etchant completely enclosing said gate in conjunction with said gate insulating layer; a second insulating layer etchable by said first etchant overlying a first portion of said first insulating layer and a first portion of said gate insulating layer and having an aperture therein extending to a second portion of said first insulating layer and a second portion of said gate insulating layer; and a third insulating layer disposed within said aperture, said third insulating layer being removable through etching by a second etchant other than carbon monoxide gas, said second etchant being selective to said third insulating layer relative to said first and second insulating layers, wherein said third insulating layer is in direct contact with said second portion of said gate insulating layer and is separated from said substrate by said second portion of said gate insulating layer; and wherein said second insulating layer is silicon oxide and said third insulting layer is silicon nitride.