Patent ID: 6065104
Filing Date: 2000-05-16
Classification: G06F

Abstract:
A method of embedding page address translation entries within a sequentially accessed data buffer comprising the steps of:storing the data buffer in at least a first page of memory, a second page of memory, and a third page of memory, the first, second and third page of memory being contiguous in virtual memory but non-contiguous in physical memory;storing a first page address translation entry for a virtual address of the second page of memory in the first page of memory;storing a second page address translation entry for a virtual address of a third page of memory in the second page of memory;storing a third page address translation entry for the virtual address of the second page of memory in the third page of memory;reading the first, second and third pages of memory;extracting the first page address translation entry from the first page of memory;translating the virtual address of the second page of memory into a physical address of the second page of memory using the first page address translation entry;extracting the second page address translation entry from the second page of memory;translating the virtual address of the third page of memory into the physical address for the second page of memory using the second page address translation entry;extracting the third page address translation entry from the third page of memory; andtranslating the virtual address of the second page of memory into the physical address for the second page of memory using the third page address translation entry.