Patent ID: 6747322
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A semiconductor device having a memory cell including a first load transistor, a second load transistor, a frat driver transistor, a second driver transistor, a first transfer transistor, and a second transfer transistor, the semiconductor device comprising:a first gateâ€”gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor; a second gateâ€”gate electrode layer including a gate electrode of the second load transistor and a gate electrode of the second driver transistor; a first drainâ€”drain wiring layer that forms a part of a connection structure that electrically connects a drain of the first load transistor and a drain of the fret driver transistor; a second drainâ€”drain wiring layer that forms a part of a connection structure that electrically connects a drain of the second load transistor and a drain of the second driver transistor; a first drain-gate wiring layer that forms a part of a connection structure that electrically connects the first gateâ€”gate electrode layer and the second drainâ€”drain wiring layer; and a second drain-gate wiring layer that forms a part of a connection structure that electrically connects the second gateâ€”gate electrode layer and she first drainâ€”drain wiring layer, wherein the first drain-gate wiring layer and the second drain gate wiring layer are located in different layers, the first drain-gate wiring layer is located in a layer below the first drainâ€”drain wiring layer, and the second drain gate wiring layer is located in a layer entirety above the first drainâ€”drain wiring layer.