Patent ID: 8381151
Filing Date: 2013-02-19
Classification: G06F

Abstract:
1. A computer implemented method for optimizing placement of one or more decoupling capacitors in an electronic design, comprising: using at least one processor that is to perform a process, the process comprising: placing and routing one or more decoupling capacitors to stabilize one or more local supply voltages for one or more individual instances; determining a value of effectiveness, I, of at least one of the one or more decoupling capacitors by using a result of one or more multi-level hierarchical power distribution analyses that provides transistor level resolution for a gate level electronic design comprising a plurality of hierarchical levels, wherein identifying or determining a first optimization cost function, Φ, representing a first placement and routing of the one or more decoupling capacitors; identifying or determining a second optimization cost function, Φ′, capturing the effectiveness of the at least one of the one or more decoupling capacitors by using at least the first optimization cost function; and defining a target threshold of a convergence criterion, below which a final placement and routing of the one or more decoupling capacitors is determined, by using at least the second optimization cost function.