Patent ID: 8350307
Filing Date: 2013-01-08
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device formed on a substrate divided into a core area and a peripheral area, and comprising: a capacitor structure extending over the core and peripheral areas, wherein respective portions of the capacitor structure function as memory cell capacitors in the core area, and as first and second capacitors in the peripheral area; and an N-well region formed in the peripheral area, wherein a combination of the first and second capacitors functions as a first power decoupling capacitor, a transistor disposed in the peripheral area functions as a second power decoupling capacitor, and the transistor is a P-type transistor formed in the N-well region; and wherein the P-type transistor is configured such that a ground voltage is applied to its gate and a power supply voltage is applied to its drain and source, such that the second power decoupling capacitor suppresses fluctuations in the power supply voltage.