Patent ID: 9158700
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A method comprising: dynamically allocating logical zones within a non-volatile, solid-state memory device, each of the logical zones being differentiated based on any combination of retention, performance, and reliability constraints of physical storage to which the logical zones are mapped, the non-volatile, solid-state memory device comprising an over-provisioned portion that minimizes write amplification in the non-volatile, solid-state memory device, the over-provisioned portion being selected from one of the logical zones; detecting a power loss condition affecting volatile data that is cached in preparation for storage in the non-volatile, solid-state memory device; storing the volatile cached data in the over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition; and upon resumption of power, moving the stored cached data from the over-provisioned portion of the non-volatile, solid-state memory device to a provisioned portion of the non-volatile, solid-state memory device to thereafter free the over-provisioned portion for purposes of minimizing write-amplification.