Patent ID: 8305802
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: a memory cell formed over a memory cell formation area of a semiconductor substrate, wherein the memory cell includes: (a) the semiconductor substrate; (b) a first gate insulating film formed over the semiconductor substrate; (c) a control gate electrode formed over the first gate insulating film; (d) a first insulating film formed over the control gate electrode; (e) a boost gate electrode formed over the first insulating film; (f) a first potential barrier film formed over respective side walls of the control gate electrode and the boost gate electrode and over the semiconductor substrate; (g) a charge accumulation film formed over the first potential barrier film; (h) a second potential barrier film formed over the charge accumulation film; (i) a memory gate electrode formed over the second potential barrier film; (j) a first source region formed in the semiconductor substrate; and (k) a first drain region formed in the semiconductor substrate, and wherein a height of a surface of the control gate electrode from a surface of the semiconductor substrate is lower than a height of a surface of the memory gate electrode from the surface of the semiconductor substrate.