Patent ID: 7822912
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A flash array storage system, comprising: a plurality of flash storage chips, arranged as an array, each of the flash storage chips comprising: a single circuit board; a microcontroller, embedded on the single circuit board and having a flash memory interface, a PCI Express interface, and a virtual integrated device electronics (IDE) module, the virtual IDE module having an IDE master port for receiving an IDE instruction and an IDE device port for executing the IDE instruction, the virtual IDE module being implemented by a firmware which can be executed by the microcontroller; at least one flash memory, embedded on the single circuit board and coupled to the microcontroller for storing data; and a PCI Express connecting interface, embedded on the single circuit board and coupled to the microcontroller for connecting to a host; and a flash array driving program, installed in the host and executed by the host for controlling data access to the flash storage chips; wherein when the host writes a data into the flash array storage system, the flash array driving program designates at least one of the flash storage chips to write the data and records designating information and the virtual IDE module of the designated flash storage chip receives and executes the IDE instruction issued by the host, and the data is received by the PCI Express connecting interface and the PCI Express interface and converted into formats acceptable to the flash memories by the flash memory interfaces to be written into the flash memories, wherein when the host reads the data from the flash array storage system, the flash array driving program searches for the flash storage chip which stores the data based on the designating information, and the virtual IDE module of the flash storage chip which stores the data receives and executes the IDE instruction issued by the host, and the data is read by the flash memory interfaces and converted into formats acceptable to the PCI Express connecting interfaces by the PCI Express interfaces to be transmitted.