Patent ID: 6826741
Filing Date: 2004-11-30
Classification: H03K

Abstract:
A peripheral bus comprising:pluralities of line segments on a periphery of an electronic device, wherein: line segments of the pluralities of line segments are staggered such that positions of start and end points of line segments of one plurality of line segments correspond to different portions of I/O circuitry of the electronic device than do positions of start and end points of line segments of another plurality of line segments; at least some line segments of the pluralities of line segments are coupled to receive signals from the I/O circuitry of the electronic device, from a core of the electronic device, and from at least one other line segment of the pluralities of line segments; at least some line segments of the pluralities of line segments are coupled to provide a signal to the I/O circuitry of the electronic device, to the core of the electronic device, and to at least one other line segment of the pluralities of line segments.