Patent ID: 7528047
Filing Date: 2009-05-05
Classification: H01L

Abstract:
1. A method of forming a split gate memory device in and on a semiconductor layer, comprising: forming an insulating layer over the semiconductor layer; patterning the insulating layer to leave a pillar of insulating material, wherein the pillar has a first side and a second side; forming a gate dielectric over the semiconductor layer; forming a charge storage layer over the gate dielectric and along the first and second sides of and over the pillar; after forming the charge storage layer, forming a gate material layer over the gate dielectric and the pillar; performing an etch to leave a first portion of the gate material layer laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material layer laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate; and forming source/drain regions in the semiconductor layer spaced apart to form a channel under the first and second portions of the gate material layer.