Patent ID: 7812339
Filing Date: 2010-10-12
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a surface; a shallow trench isolation (STI) region in said semiconductor substrate and extending above the surface thereof; a superlattice layer adjacent the surface of said semiconductor substrate and comprising a plurality of stacked groups of layers; each group of layers of said superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer; and a lateral spacer between said superlattice layer and said STI region and comprising a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.