Patent ID: 6787419
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A method of forming a metal oxide semiconductor (MOS) transistor of an embedded memory comprising the following steps:providing a semiconductor wafer comprising a substrate, the substrate being defined with a first region and a second region; forming an oxide-nitride-oxide (ONO) layer, a first silicon layer, and a first dielectric layer sequentially on the surface of the semiconductor wafer; performing a first photo-etching process to remove the first dielectric layer, the first silicon layer, and the ONO layer in the second region; forming at least one gate oxide layer in the second region on the surface of the substrate; forming a second silicon layer on the semiconductor wafer; performing a second photo-etching process to remove the second silicon layer and the first dielectric layer in the first region; forming the third silicon layer on the semiconductor wafer; performing a third photo-etching process to form a gate of the MOS transistor in the first region and the second region respectively; performing at least one first region ion implantation process to form a source and a drain of the MOS transistor in the first region; and performing at least one second region ion implantation process to form a source and a drain of the MOS transistor in the second region.