Patent ID: 6469647
Filing Date: 2002-10-22
Classification: H03M

Abstract:
A digital-analog converter circuit, characterized in that comprises:a high-order D-A converter circuit unit for receiving a high-order i bit signal (ia low-order D-A converter circuit unit for receiving the first and second output node voltages of the high-order D-A converter circuit unit as reference voltages of an Râˆ’2R ladder circuit, and conducting D-A conversion of remaining low-order j bitsa sample-and-hold unit for selectively sampling and holding the voltage on the third output node, i.e., the D-A conversion output of the n-bit digital input code, according to a value of the n-bit digital input code; and an output unit for multiplying the sampled and held D-A conversion output voltage by a gain with respect to an arbitrary central voltage.