Patent ID: 9065457
Filing Date: 2015-06-23
Classification: H03L,H04L,H04W

Abstract:
1. A phase locked loop (PLL) circuit for a frequency synthesizer of a wireless device, the PLL circuit comprising: a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal; a compensation circuit including a charging circuit in communication with the PFD, a charge pump, and a voltage-to-current converter in communication with the charging circuit and positioned between the charging circuit and the charge pump, the charging circuit including a capacitance element and configured to charge the capacitance element in response to the first signal, the voltage-to-current converter configured to generate a control signal in response to a voltage the charged capacitance element, the voltage representative of the phase difference, the compensation circuit configured to generate a compensation signal based on the control signal; and a voltage-controlled oscillator (VCO) in communication with the compensation circuit, the VCO configured to generate an output signal based on the compensation signal, the compensation signal including at least one feature for substantially eliminating one or more reference spurs associated with the PLL.