Patent ID: 8664640
Filing Date: 2014-03-04
Classification: B82Y,G11C,H01L

Abstract:
1. A memory device comprising a source drain channel and a layer including a plurality of a charge trapping material, wherein at least one of the charge trapping material includes a core including an overcoating layer, and an outer layer on the core, wherein the outer layer includes a semiconductor material selected from Group II-VI compounds, Group II-V compounds, Group III-VI compounds, Group III-V compounds, Group IV-VI compounds, Group I-III-VI compounds, Group II-IV-VI compounds, and Group II-IV-V compounds, the charge trapping material is selected to decrease lateral conductivity within the layer relative to a layer of the core without the outer layer, and the plurality of the charge trapping material has a size dispersity of less than 50%, wherein the plurality of charge trapping nanoparticles includes a plurality of nanocrystals, wherein the plurality of nanocrystals is colloidally-grown and each nanocrystal has a surrounding ligand shell, wherein the ligand shell includes exposed ligand moieties.