Patent ID: 6334173
Filing Date: 2001-12-25
Classification: G06F

Abstract:
An N-way cache memory system including N cache memory blocks receiving a tag field and an offset field of an address bus, a logic OR means for performing a logic OR operation with way hit signals from each cache memory block and for generating a cache hit signal when a way hit signal is produced in one of the cache memory blocks, and a first selection means for outputting to a data bus a data which is resulted from the cache memory blocks in response to the way hit signal, wherein each cache memory blocks comprising:a second selection means for selectively outputting the tag field received from the address bus when a data from a main memory is loaded into the cache memory system and a value which is set to each cache memory block, in response to a cache/memory signal;a tag register for storing a tag value from the second selection means;a comparison means for comparing the tag value stored in the tag resister with the tag field on the address bus which is provided for reading out a data from the cache memory system;a tag latch circuit for storing a result of the comparison means as a tag hit signal;a plurality of data registers for storing data loaded from the main memory;a third selection means for selectively outputting data stored in the plurality of data registers in response to the offset field on the address bus which is provided for reading out data from the cache memory system;a plurality of valid bit registers for storing valid bits indicative of a validity of data stored in the plurality of data registers;a fourth selection means for selectively outputting the valid bits stored in the plurality of valid bit registers in response to the offset field of the address bus; anda logic operation means for performing a logic AND operation with the tag hit signal from the tag hit latch circuit and the valid bit from the fourth selection means.