Patent ID: 6405289
Filing Date: 2002-06-11
Classification: G06F

Abstract:
A method of maintaining cache coherency in a multiprocessor computer system including a plurality of memory arrays and a plurality of processing units that each have at least one cache, said method comprising:designating a memory array that contains a memory block as a lowest point of coherency for the memory block; designating a single cache containing a valid value corresponding to the memory block as a highest point of coherency for the memory block; issuing a request for the value from a master device of the computer system; in response to the request: the memory array designated as the lowest point of coherency first protecting the memory block from any conflicting operation; and the cache designated as the highest point of coherency sending a snoop response indicating that the cache is currently the highest point of coherency for the memoryblock and can service the request and thereafter protecting the memory block from any conflicting operation until completion of a transaction associated with the request.