Patent ID: 9157958
Filing Date: 2015-10-13
Classification: G01R,G06F

Abstract:
1. A system on a chip comprising: A. a communications link including a serial test data in lead and a serial test data out lead; B. a port coupled to the communications link including the serial test data in lead and the serial test data out lead, and having a chip serial test data in lead, a chip serial test data out lead, and a select output lead; C. a first component separate from the port, the first component including an embedded TAP controller, the first component having a test data input coupled to the chip serial test data in lead, a component serial test data output lead, an override output, and a one bit status register coupled to the embedded TAP controller and coupled between the test data input and the component serial test data output lead, the one bit status register being additional to the embedded TAP controller; D. multiplexer circuitry having a first input coupled to the chip serial test data in lead, a second input coupled to the component serial test data output, an output, and a control input; and E. gating circuitry having a first input coupled to the select output lead, a second input coupled to the override output, and an output coupled to the control input of the multiplexer circuitry.