Patent ID: 6223196
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A shared multiply accumulate (MAC) system comprising:a host processor;a sub-processor including multiply accumulate (MAC) unit;a host bus interface forming a connection between said host processor and said sub-processor;a first register set in which a multiplier, a multiplicand, a product and a status are written in order for the performance of a multiply accumulate (MAC) operation required by said host processor;a second register set in which a multiplier, a multiplicand, a product and a status are written in order for the performance of a multiply accumulate (MAC) operation required by said sub-processor; andselection means for selecting said first register set or said second register set upon receipt of a frequency division signal obtained by the division of an internal clock in said shared MAC system, wherein said MAC unit in said sub-processor performs said MAC operation in accordance with the contents of said first register set or of said second register set that is selected.