Patent ID: 8320181
Filing Date: 2012-11-27
Classification: G11C,H01L

Abstract:
1. A memory array, comprising: a first tier comprising a first plurality of memory cells, a first plurality of source select gates, and a first plurality of drain select gates, wherein a string of memory cells of the first tier comprises one or more of the plurality of memory cells disposed between one of the plurality of source select gates and one of the plurality of drain select gates; a second tier formed at least partially over the first tier and comprising a second plurality of memory cells, a second plurality of source select gates, and a second plurality of drain select gates, wherein each of a string of memory cells of the second tier comprises one or more of the second plurality of memory cells disposed between one of the second plurality of source select gates and one of the second plurality of drain select gates; a first contact extending at least partially through the first tier and the second tier, the first contact coupling the first plurality of source select gates to the second plurality of source select gates and to a common source line; wherein the first tier comprises a first plurality of digitlines, wherein each of the first plurality of drain select gates is coupled to a respective one of the first plurality of digitlines, and wherein each of the first plurality of digitlines is coupled to a respective one of a second plurality of contacts adjacent to the first tier and the second tier and each of the first plurality of digitlines is laterally insulated from a respective one of the second plurality of contacts by an insulator disposed between a horizontal end of each of the first plurality of digitlines and the respective one of the second plurality of contacts; and wherein the second tier comprises a second plurality of digitlines, wherein each of the second plurality of drain select gates is coupled to a respective one of the second plurality of digitlines, and wherein each of the second plurality of digitlines is coupled to a respective one of the second plurality of contacts and each of the second plurality of digitlines is laterally insulated from a respective one of the second plurality of contacts by an insulator disposed between a horizontal end of each of the second plurality of digitlines and the respective one of the second plurality of contacts.