Patent ID: 6507052
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A semiconductor memory device comprising:a memory cell array section having a plurality of memory cell blocks arranged in a matrix, said memory cell blocks each including a plurality of memory cells; and a reference section for generating a reference current for use in identification of data in said memory cells; said reference section including a plurality of diffusion layers arranged parallel to each other, a plurality of word lines arranged parallel to each other along a direction orthogonal to said diffusion layers, a plurality of MOS transistors having sources and drains made of the intersections of said diffusion layers and said word lines, and channels made of the portions sandwiched between said sources and drains, and first contact diffusion regions and second contact diffusion regions for connecting said diffusion layers with a bit line and a virtual ground line; wherein each of said second contact diffusion regions is provided with a contact to said virtual ground line.