Patent ID: 6731709
Filing Date: 2004-05-04
Classification: H03L

Abstract:
A phase-locked loop (PLL), comprising:a phase detector coupled to receive an input clock signal from a first one of a plurality of clock sources and a feedback signal, wherein said phase detector outputs a phase error signal indicative of a comparison between said input clock signal and said feedback signal; a loop filter coupled to receive said phase error signal and to output an error correction signal; a voltage controlled oscillator coupled to receive said error correction signal and to generate an output signal, wherein said feedback signal has a frequency dependency upon said output signal; switching logic coupled to monitor said input clock signal from said first one of said plurality of clock sources for a failure, wherein said switching logic is configured to cause said input clock signal from a second one of said plurality of clock sources to be provided to said phase detector in response to said failure; wherein the phase detector includes a supplemental pulse generator configured to provide a supplemental pulse to the loop filter in response to said failure.