Patent ID: 6161166
Filing Date: 2000-12-12
Classification: G06F

Abstract:
A multithreaded computer processing apparatus, comprising:a plurality of sets of registers for supporting the execution of a plurality of threads, each set of registers corresponding to a respective one of said plurality of threads;an instruction unit, said instruction unit comprising decode logic for decoding instructions and sequence logic for generating effective addresses of instructions to be executed; andan instruction cache, said instruction cache providing an instruction responsive to a desired effective address generated by said instruction unit, said instruction cache comprising:(a) a directory array having a plurality of entries, each entry containing a portion of a real address of an instruction, wherein an entry in said directory array is selected using said desired effective address;(b) an instruction array having a plurality of entries, each instruction array entry being associated with an entry in said directory array and comprising at least one instruction, wherein an entry in said instruction array is selected using said desired effective address; and(c) a plurality of line fill registers, each of said line fill registers corresponding to a respective one of said plurality of threads, each line fill register storing at least a portion of a respective real address of a desired instruction to be retrieved in response to an instruction cache miss.