Patent ID: 6667921
Filing Date: 2003-12-23
Classification: G11C

Abstract:
A bitline precharge circuit in a semiconductor memory device, the circuit comprising:a driving control unit configured to output a VDD driving signal and a VPP driving signal in response to a bitline precharge enable signal; a precharge circuit driving unit configured to output a bitline precharge signal of a power supply voltage VDD level or a boosted voltage VPP level in response to the VDD driving signal or the VPP driving signal; and a bitline precharge unit configured to precharge bitlines in response to the bitline precharge signal, wherein a voltage level of the bitline precharge signal reaches the VDD level for a predetermined time from an enabled starting point of the bitline precharge enable signal, and then the voltage level of the bitline precharge signal reaches the VPP level after the predetermined time.