Patent ID: 6927998
Filing Date: 2005-08-09
Classification: G11C,H01L

Abstract:
1. A semiconductor device having a non-volatile memory, comprising: a memory cell array including a plurality of memory cells, each of the memory cells having positive ternary or more data “m”, the plurality of memory cells arranged in the shape of a matrix; a plurality of word lines connected to said memory cells, extending over said memory cell arrays in a first direction, and arranged in a second direction; a plurality of bit lines connected to said memory cells, extending over said memory cell arrays in the second direction, and arranged in the first direction; a plurality of sense amplifiers provided for said bit lines on one to one basis; and a plurality of latch circuits provided for said sense amplifier on one to one basis, wherein the positive ternary or more data “m” are simultaneously written into adjacent memory cells and the data are sequentially written into memory cells having lower threshold voltages.