Patent ID: 6034554
Filing Date: 2000-03-07
Classification: H03D,H03L,H04L

Abstract:
A phase detector circuit for detecting a phase difference between an information signal and a clock signal and for producing a phase error signal representative of said phase difference, said clock signal and said information signal being pulse waveforms having first and second levels and having first and second edges, said information signal containing data at a certain data rate and said first and second edges of said information signal being data transitions, said phase detector circuit comprising:(a) divider circuit for dividing said information signal into a plurality N of divided signals, N being equal to 2.sup.M where the number M is a positive integer greater than or equal to one, and the data rate of each of said divided signals being the data rate of said information signal divided by N;(b) pulse signal circuit coupled to said divider circuit for producing a plurality N of variable width difference pulse signals, each of said difference pulse signals being responsive to the phase difference between one of said divided signals and said clock signal, the width of each of said difference pulse signals being not less than the width between said first and second edges of said clock signal, said pulse signal circuit further producing one or more fixed width reference pulse signals and the width of each of said one or more reference pulse signals being proportional to the width between said first and second edges of said clock signal; and(c) a phase error signal circuit coupled to said pulse signal circuit for producing said phase error signal in response to said plurality of difference pulse signals and said one or more reference pulse signals.