Patent ID: 7307021
Filing Date: 2007-12-11
Classification: H01L

Abstract:
1. A method of planarizing a layer of semiconductor material formed on a wafer, the wafer having a top surface, the top surface having a first region and a second region that lies above the first region, the first region being equal to a lowest part of the top surface, the second region being equal to a highest part of the top surface, the method comprising: forming a layer of first material to contact the top surface of the wafer, the layer of first material having a top surface, the top surface of the layer of first material having a first region and a second region that lies above the first region of the layer of first material, the first region of the layer of first material being equal to a lowest part of the top surface of the layer of first material, the second region of the layer of first material being equal to a highest part of the top surface of the layer of first material; forming a layer of second material to contact the top surface of the layer of first material, the layer of second material having a top surface, the top surface of the layer of second material having a first region and a second region that lies above the first region of the layer of second material, the first region of the layer of second material being equal to a lowest part of the top surface of the layer of second material, the second region of the layer of second material being equal to a highest part of the top surface of the layer of second material, the first region of the top surface of the layer of second material lying above the second region of the top surface of the layer of first material; and performing a chemical-mechanical polish of the layer of second material and the layer of first material, the chemical-mechanical polish continuing until the layer of second material has been substantially all removed from the layer of first material, thereby forming the layer of first material to have a substantially planar top surface, the substantially planar top surface of the layer of first material lying over the first region and the second region of the top surface of the wafer.