Patent ID: 6765252
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A DRAM cell comprising:a device isolation film for defining en active region on a semiconductor substrate; a well region formed inside the semiconductor substrate corresponding to the active region; a plurality of channel layers formed in selected portions of the well region; a field stop layer underlying the well region in the substrate; a plurality of gates formed on the channel layers; source and drain junctions respectively formed between the gates inside the semiconductor substrate, the source and drain junctions having an asymmetric junction structure; a source spacer formed on the top surface of the gate and a selected portion of lateral surface of the gate adjacent the source junction and contacting the source junction; a drain spacer formed on the surfaces of the source spacer and directly on the side surface of the gate adjacent the drain junction, the drain spacer contacting the drain junction, wherein the source spacer is thicker than the drain spacer, and contact plugs respectively contacting with the source and drain junctions.