Patent ID: 6785700
Filing Date: 2004-08-31
Classification: G06F

Abstract:
An architecture component for use in performing a wavelet transform of a sampled signal, the component including at least one multiplier, and a respective multiplexor to multiplex a number n of filter coefficients onto the respective multiplier, in which the or each multiplier processes n consecutive samples with consecutive coefficients, the or each multiplier and respective multiplexor implementing a number m of processing stages for each sample, the architecture component further including an accumulator for summing the or each multiplier output for each processing stage; and a buffering stage for storing summed multiplier outputs, an output comprising summed multiplier outputs being generated after every n samples, and wherein a delay line is provided between processing stages, the delay line causing sample data to be conveyed from each processing stage to a subsequent processing stage with a delay of n times a sampling period of the signal.