Patent ID: 6094669
Filing Date: 2000-07-25
Classification: G06F

Abstract:
A method of using a CPU to generate a quotient and a remainder the combination of which represents a result of dividing a 2n bit signed numerator by a n signed denominator, and to generate an overflow signal when the quotient exceeds n bits, the method comprising:initializing a partial remainder to a first value dependent upon the n most significant bits of the numerator;initializing a partial quotient to a first value dependent upon the n least significant bits of the numerator;generating a second value of the partial remainder and a second value of the partial quotient dependent upon the first values of the partial remainder and the partial quotient;generating the overflow signal if the second value of the partial quotient is equal to zero;generating the quotient and the remainder dependent upon the second values of the partial remainder and the partial quotient; andgenerating the overflow signal dependent upon the quotient.