Patent ID: 6396316
Filing Date: 2002-05-28
Classification: H03K

Abstract:
A buffer circuit for reducing clock jitter comprising:a buffer having at least one input for receiving at least one input clock signal having a nominal clock frequency and further having a buffer output, said buffer being operative to provide an output clock signal at said buffer output responsive to the receipt of said at least one input clock signal; at least one inductive element having an inductance value, said at least one inductive element being coupled between said buffer output and a first low impedance node of said buffer circuit; and at least one capacitive element having a capacitance value, said at least one capacitive element being coupled between said buffer output and a second low impedance node of said buffer circuit; said at least one inductive element and said at least one capacitive element having a resonant frequency and said inductance value and said capacitance value being specified such that said resonant frequency corresponds to said nominal clock frequency; wherein said buffer includes an amplifier stage having an output coupled to an input of a first buffer stage, said at least one input of said buffer comprises at least one input to said amplifier stage and said buffer output comprises an output of said first buffer stage.