Patent ID: 6456116
Filing Date: 2002-09-24
Classification: G06F

Abstract:
A dynamic comparator circuit for comparing first and second words having one or more comparative bit pairs, comprising:one or more asynchronous XOR devices, each XOR device having inputs for receiving at least one of the comparative bit pairs from said first and second words and an output providing an XOR value that indicates whether any of the received comparative bit pairs has unequal bit values; and a precharge NOR circuit having one or more substantially parallel pull-down transistors connected between a common storage node and a DNG transistor, which turns off during a precharge phase, each of said pull-down transistors having an input coupled to the output of an associated separate one of the one or more asynchronous XOR devices for receiving its XOR value and discharging the storage node during an evaluate phase if the comparative word bit pairs input to its associated XOR device have unequal bit values, wherein the storage node evaluates to a charged value when all of the one or more comparative bit pairs have equivalent bits.