Patent ID: 6986001
Filing Date: 2006-01-10
Classification: G06F

Abstract:
1. A system for cache memory management, the system comprising: a cache memory, wherein the cache memory comprises memory blocks allocated into sets of N memory blocks, and wherein the N memory blocks are allocated as M super-ways of N/M memory blocks, wherein N is greater than M; an index, wherein the index identifies the set of N memory blocks; a super-way hit/replacement tracking state machine, wherein the super-way hit/replacement tracking state machine tracks hits and replacements to each super-way and maintains state corresponding to an order of hits and replacements to each super-way, wherein the state orders the super-ways from the MRU to the LRU; state bit storage associated with each index entry, wherein the state bits include code bits associated with a memory block to be replaced within a LRU super-way; LRU logic coupled to the super-way hit/replacement tracking state machine, wherein the LRU logic selects an LRU super-way as a function of the super-way hit and replacement history; and block selection logic coupled to the LRU logic, wherein the block selection logic selects a memory block to be replaced within the LRU super-way as a function of predefined selection criteria.