Patent ID: 6175266
Filing Date: 2001-01-16
Classification: G05F

Abstract:
A power converter comprising:an operational amplifier having a noninverting input for receiving a voltage reference, an inverting input and an output, the operational amplifier comprising:a first NMOS transistor having a gate providing the noninverting input, a source, and a drain;a second NMOS transistor having a gate providing the inverting input, a source, and a drain;a third NMOS transistor having a source coupled to a first voltage potential terminal, a drain coupled to the source of the first and second NMOS transistors, and having a gate;a first PMOS transistor having a drain and gate coupled to the drain of the first NMOS transistor, and having a source coupled to a second voltage potential terminal;a second PMOS transistor having a drain and a gate coupled to the drain of the second NMOS transistor, and having a source coupled to the second voltage potential terminal;a third PMOS transistor having a source coupled to the second voltage potential terminal, a gate coupled to the gate of the first PMOS transistor, and having a drain;a fourth PMOS transistor having a source coupled to the second voltage potential terminal, a gate coupled to the gate of the second PMOS transistor, and having a drain;a fourth NMOS transistor having a source coupled to the first voltage potential terminal, and a drain and gate coupled to the drain of the fourth PMOS transistor; anda fifth NMOS transistor having a source coupled to the first voltage potential terminal, a gate coupled to the gate of the fourth NMOS transistor, and a drain coupled to the drain of the third PMOS transistor and to an output of the operational amplifier, wherein the fifth NMOS transistor comprises a plurality of parallel connected transistors forming a channel width larger than a channel width of the fourth NMOS transistor;a first output control transistor having a source to drain path coupling a second voltage potential terminal to an output node, and having a gate coupled to the output of the operational amplifier; anda resistor divider comprising a first resistor coupling the output node to the inverting input of the operational amplifier, and a second resistor coupling the second input of the operational amplifier to the first voltage potential terminal.