Patent ID: 8707223
Filing Date: 2014-04-22
Classification: G06F

Abstract:
1. A process of forming an integrated circuit, comprising the steps: defining a preferred direction for an interconnect level; drawing a first interconnect geometry and second interconnect geometry separated in said preferred direction by a same color interconnect geometry design rule space; drawing a third interconnect geometry in said preferred direction separated by said second interconnect geometry by a different color interconnect geometry design rule space; drawing a color cover over said third geometry; drawing additional DPT compatible interconnect geometries on said interconnect level using a double pattern technology (“DPT”) compatible electronic design automation (“EDA”) software program to complete layout of said interconnect level; using software program to decompose autorouted metal of said interconnect level into a first color DPT interconnect pattern and a second color DPT interconnect pattern; and using said software program to assign said first color to said first and said second interconnect geometries and to assign said second color to said third interconnect geometry underlying said color cover.