Patent ID: 6442666
Filing Date: 2002-08-27
Classification: G06F

Abstract:
An apparatus for reducing memory access latency in a virtual memory based system, comprising:a processor arranged to perform executable instructions; a memory array formed of DRAM devices each of which includes a sense amp coupled to a data bus suitably coupled to the processor arranged to store executable instructions that are performed by the processor; a cache memory coupled to the processor and the main memory arranged to store a subset of recently used instructions, wherein the cache memory is located temporally closer to the processor than the main memory; a TLB page cache suitably arranged to store a TLB page, wherein under the direction of the processor, a new TLB page corresponding to a new TLB entry is moved temporally closer to the processor by moving from the main memory to the TLB page cache, wherein the TLB page cache is proximally closer to the processor than the main memory, and wherein a TLB page cache entry in the TLB page cache points to an associated TLB page, and wherein the TLB page is distributed amongst the sense amps associated with the memory array.