Patent ID: 6136643
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) cells on a semiconductor substrate, comprising the steps of:providing said semiconductor substrate having device areas surrounded by field oxide regions;depositing and patterning a first polycide layer having a cap oxide to form field-effect-transistor (FET) gate electrodes on said device areas and to form word lines extending over said field oxide regions;forming doped source/drain areas adjacent to said gate electrodes in said substrate;depositing a conformal first etch-stop layer on said substrate and anisotropically plasma etching back partially to form sidewall spacers on said gate electrodes, while leaving portions of said first etch-stop layer over said source/drain areas;depositing and planarizing a first insulating layer on said substrate;etching self-aligned contact holes in said first insulating layer to said etch-stop layer over said source/drain areas;selectively removing said etch-stop layer over said source/drain areas;depositing a conductively doped first polysilicon layer and etching back to form polysilicon landing plugs in said contact holes to said source/drain areas for capacitor node contacts and for bit-line contacts;depositing a second insulating layer on said substrate;etching bit-line contact holes to portions of said polysilicon landing plugs for said bit-line contacts;depositing a second polycide layer;depositing a second etch-stop layer on said second polycide layer;patterning said second etch-stop layer and said second polycide layer to form bit lines extending over said bit-line contact holes;depositing a conformal third etch-stop layer;patterning said third etch-stop layer to form openings over said landing plugs for said capacitor node contacts, while said third etch-stop layer protects remaining surface of said substrate from etching;depositing and planarizing a third insulating layer;etching selectively capacitor openings in said third insulating layer aligned over and larger than said openings in said third etch-stop layer and to said capacitor node contacts, while said third etch-stop layer in said capacitor openings prevents overetching;depositing a conformal first conducting layer over third insulating layer and in said capacitor openings;spin coating a polymer layer to form a planar surface, and etching back said polymer layer and said first conducting layer on top surface of said third insulating layer to form an array of capacitor bottom electrodes in said capacitor openings;removing remaining said polymer layer in said capacitor openings and selectively removing said third insulating layer to said third etch-stop layer;forming an interelectrode dielectric layer on said bottom electrodes;depositing and patterning a second conducting layer to form capacitor top electrodes and to complete said DRAM cells.