Patent ID: 9136849
Filing Date: 2015-09-15
Classification: H03K

Abstract:
1. An integer frequency divider, comprising: a clock input end, configured to provide a clock; N latches, where N is a positive integer greater than or equal to 2, the latches connected in series according to a connection order, the latches comprising a first latch and a plurality of candidate latches, each of the latches comprising: a selection circuit, coupled to the signal output stages of each of the candidate latches, configured to select a second latch from the candidate latches according to a selection signal; wherein: the signal input stage of the first latch comprises a positive signal input unit and an inverted signal input unit that respectively receive the input signal and an inverted signal of the input signal; the signal output stage of the second latch comprises a positive signal output end and an inverted signal output end that respectively output the output signal and an inverted signal of the output signal; and the selection circuit couples the positive signal input unit of the first latch to the inverted signal output end of the second latch, and couples the inverted signal input unit of the first latch to the positive signal output end of the second latch.