Patent ID: 6094440
Filing Date: 2000-07-25
Classification: H04L,Y10S

Abstract:
A multiplex type signal transmission apparatus, comprising:a plurality of slow signal receiving/transmitting sections which receives and transmits a slow signal;a multiplex separation converting section; anda fast signal receiving/transmitting section which receives and transmits a fast signal, said fast signal receiving/transmitting section including:a receiving processing section which receives said fast signal from a transmission path,an internal SS bits setting unit selected from one of a first internal SS bits setting unit, a second internal SS bits setting unit, and a third internal SS bits setting unit,wherein said first internal SS bits setting unit, with respect to each SS bit set A of a plurality of H1 bytes existing in a same frame of the received fast signal, when the SS bits B received at a first time are a value of either ""10"" or ""00"", sets the internal SS bits to said value, and otherwise the internal SS bits hold a previous state, andwherein said second internal SS bits setting unit, with respect to each SS bit set C having value of either ""10"" or ""00"" among said SS bit set A, compares the number of M of the SS bits having value of ""10"" with the number L of the SS bits having value of ""00"", and sets the internal SS bits to ""10"" when said M is larger than said L, sets the internal SS bits to ""00"" when said M is smaller than said L, and sets the internal SS bits to hold a previous state when said M is equal to said L or there are no elements of the SS bits set C, andwherein said third internal SS bits setting unit, with respect to each SS bit set D not included in concatenation indicator and having value of either ""10"" or ""00"" among said SS bit set A, compares the number of N of the SS bits having value of ""10"" with the number K of the SS bits having value of ""00"", and sets the internal SS bits to ""10"" when said N is larger than said K, sets the internal SS bits to ""00"" when said N is smaller than said K, and sets the internal SS bits to hold a previous state when said N is equal to said K or there are no elements of the SS bits set D, anda transmission processing unit on a transmitting side which transmits the fast signal into said transmission path as keeping the plurality of SS bits of the signal from said multiplex separation converting section identical with the internal SS bits set by said internal SS bits setting section.