Patent ID: 6473324
Filing Date: 2002-10-29
Classification: G11C

Abstract:
A sense amplifier for a semiconductor memory, comprising:a plurality of read/write amplifiers extending as strips in rows one under another and having NMOS and PMOS transistors; two driver transistors connected to said read/write amplifiers, said two driver transistors being strip shaped and extending perpendicularly to said read/write amplifiers in a form of columns over said rows of said read/write amplifiers, at least one of said two driver transistors having doping in regions disposed between associated ones of one of said NMOS transistors and said PMOS transistors of said read/write amplifiers, and said at least one of said two driver transistors having a gate formed as a two-strip gate with two strips; and non-inverted and inverted bit lines extending in said rows of said read/write amplifiers.