Patent ID: 7791102
Filing Date: 2010-09-07
Classification: H01L

Abstract:
1. A device, comprising: a silicon-on-insulator substrate comprising: a carrier wafer, an insulating layer overlying the carrier wafer; and a layer of silicon on the insulating layer, wherein layer of silicon includes a first PN junction diode and a second PN junction diode; a P a first N-well device region disposed within the layer of silicon and extending to the insulating layer, the first N-well device region in series with the P+-type anode region such that the first PN junction diode is formed between the P a first P-well device region disposed within the layer of silicon and extending to the insulating layer, the first P-well device region in series with the first N-well device region wherein the first P-well device region is electrically floating; an N a first gate electrode disposed at least substantially overlying the first N-well and P-well device regions of the silicon-on-insulator substrate; an input-output pad coupled to the P an RC-triggered sensing circuit coupled to the gate electrode, wherein the RC-triggered sensing circuit is designed to sense an electrostatic discharge event applied to the input-output pad, and upon sensing the electrostatic discharge event, to communicate a voltage to the gate electrode to invert one of the first N-well device region and the first P-well device region to short out one of the first PN junction diode and the second PN junction diode.