Patent ID: 6115833
Filing Date: 2000-09-05
Classification: G01R,G11C

Abstract:
A semiconductor memory testing apparatus including a failure analysis memory for storing failure data resulting from the test results of a semiconductor memory under test, said failure analysis memory comprising a plurality of memory blocks the number of which is equal to the number of semiconductor memories of high operating rate that said testing apparatus can test at the same time in a high rate test mode in which said testing apparatus tests said semiconductor memories of high operating rate, and a plurality of banks provided in each of said plurality of memory blocks and the number of which corresponds to the number of ways of an interleave operation,said semiconductor memory testing apparatus being characterized in that in a low rate test mode in which said semiconductor apparatus tests semiconductor memories of low operating rate, each of said plurality of banks of each memory block in said failure analysis memory is designated as an area in which is stored failure data of one of semiconductor memories under test that said testing apparatus tests at the same time, and failure data of each semiconductor memory under test is stored in the corresponding one bank.