Patent ID: 7893718
Filing Date: 2011-02-22
Classification: H03K

Abstract:
1. A multiplexer, comprising: a first N-to-1 selection circuit configured to route a true or complementary version of a selected first input signal to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one; a second N-to-1 selection circuit configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal; and an output driver comprising a pull-up circuit responsive to a signal generated at the output of said first N-to-1 selection circuit and a pull-down circuit responsive to a signal generated at the output of said second N-to-1 selection circuit; wherein said pull-down circuit comprises a first NMOS pull-down transistor having a gate terminal responsive to the signal generated at the output of said second N-to-1 selection circuit; and wherein said pull-up circuit comprises: