Patent ID: 6545348
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A package for a semiconductor device comprising:a substrate having a center portion on which a semiconductor chip is to be mounted; a first interconnection pattern formed on said substrate at a position around said semiconductor chip and having a continuous first interconnection main portion and a plurality of first projections protruding from said first interconnection main portion at approximately equal intervals; a second interconnection pattern formed on said substrate at a position around said semiconductor chip and spaced apart from said first interconnection pattern by a predetermined distance and having a continuous second interconnection main portion and a plurality of second projections so formed as to protrude from said second interconnection main portion at approximately equal intervals and to be engaged with said first projections of said first interconnection pattern in a non-contact manner, said second interconnection pattern being formed in a region at a same level as said first interconnection pattern; and a third interconnection pattern formed on said substrate at a position around said semiconductor chip, said third interconnection pattern being spaced apart from the second interconnection pattern at a predetermined distance, said third interconnection pattern being formed in a region at a same level as said first and second interconnection patterns.