Patent ID: 6323670
Filing Date: 2001-11-27
Classification: G01R

Abstract:
A chip failure analysis assembly for mounting and performing failure analysis of an integrated circuit die having a plurality of leads, said failure analysis assembly comprising:a printed circuit board;a location or position on top of said printed circuit board for mounting said semiconductor die that is to be analyzed, a die that is to be analyzed being mounted on the surface of a printed circuit board with a backside of the die in a plane of the surface of the printed circuit board, the die that is to be analyzed being mounted on a glass surface where the glass surface is inserted in a cut out provided in the printed circuit board;a clamping arrangement for said printed circuit board;an electrical interface of said clamping arrangement with electrical power supplies or electrical stimulus or electrical response analysis apparatus;a means for distributing electrical signals from said clamping arrangement to said location of said die to be examined;contact points between said clamping arrangement and said means for distributing electrical signals; anda means for establishing electrical connections between said means for distributing electrical signals and said die to be analyzed, said means comprising jumper wires.