Patent ID: 6281707
Filing Date: 2001-08-28
Classification: G06F,H03K

Abstract:
A two-stage Muller C-element having a pair of input lines and one output line, said two-stage Muller C-element comprising:a first stage comprising:a first intermediate output line;a second intermediate output line;a NAND gate having a pair of input lines inputs and one output, wherein each of said pair of input lines is connected to one of said pair of inputs of said NAND gate, and wherein said output of said NAND gate is connected to said first intermediate output line with the NAND gate including first and second input line n-channel transistors in series, wherein a gate terminal of each of said n-channel transistors in series is connected to a different one of said inputs to said NAND gate, a first source/drain terminal of the first n-channel transistor in series is connected to said first intermediate output line, and a second source/drain terminal of the second n-channel transistor in series is connected to ground; andfirst and second input line p-channel transistors in parallel, wherein a gate terminal of each of said p-channel transistors in parallel is connected to a different one of said inputs to said NAND gate, a first source/drain terminal of each of said p-channel transistors in parallel is connected to a power supply, and a second source/drain terminal of each of said p-channel transistors in parallel is connected to said first intermediate output line;a NOR gate having a pair of input lines inputs and one output, wherein each of said pair of input lines is connected to one of said inputs of said NOR gate, and wherein said output of said NOR gate is connected to said second intermediate output line with the NOR gate including first and second input line p-channel transistors in series, wherein a gate terminal of each of said p-channel transistors in series is connected to a different one of said inputs to said NOR gate, a first source/drain terminal of the first p-channel transistor in series is connected to a power supply, and a second source/drain terminal of the second p-channel transistor in series is connected to said second intermediate output line; anda pair of input line n-channel transistors in parallel, wherein a gate terminal of each of said n-channel transistors in parallel is connected to a different one of said inputs to said NOR gate, a first source/drain terminal of each of said n-channel transistors in parallel is connected to ground, and a second source/drain terminal of each of said n-channel transistors in parallel is connected to said second intermediate output line;where the widths of the transistors are chosen such that:each of said n-channel transistors in series in the NAND gate and each of said p-channel transistors in series in the NOR gate has substantially the same width;each of said p-channel transistors in parallel in the NAND gate has a width equal to about one fourth of the product of said width of any one of said n-channel transistors in series in the NAND gate times a chosen ratio of widths of p-type to n-type transistors;and each of said n-channel transistors in parallel in the NOR gate has a width equal to about one fourth of the quotient of said width of any one of said p-channel transistors in series in the NOR gate divided by said chosen ratio of widths of p-type to n-type transistorsa second stage comprising:a first output transistor having a gate connected to said first intermediate output line, a first source/drain terminal connected to a power supply, and a second source/drain terminal connected to said output line;a second output transistor having a gate connected to said second intermediate output line, a first source/drain terminal connected to said output line, and a second source/drain terminal connected to ground; anda keeper connected to said output line and retaining the value of said output line when neither of said first or second output transistors conducts.