Patent ID: 8397003
Filing Date: 2013-03-12
Classification: G06F

Abstract:
1. A CPU connection circuit comprising two buffers, the circuit being connected between two CPUs for relaying data transfer from at least one of the CPUs to the other one thereof, the CPU connection circuit comprising: a monitoring unit which monitors whether or not an amount of data stored by a transmission-side CPU in either one of the buffers reaches a predetermined threshold value; and a requesting unit which requests, when the amount of data stored by the transmission-side CPU in the buffer reaches the threshold value, a reception-side CPU to acquire the data stored in the buffer and changing the data storage destination of the transmission-side CPU to the other one of the buffers, the threshold value being a value more than a unit quantity of data which the transmission-side CPU sends to the buffer, wherein the transmission-side CPU's storing the data to the other one of the buffers and the reception-side CPU's acquiring the data from the buffer are carried out concurrently.