Patent ID: 7923768
Filing Date: 2011-04-12
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a source area at a first exposed surface of the semiconductor substrate, a drain area at a second exposed surface of the semiconductor substrate opposite from the first exposed surface, and a vertical channel between the source and drain areas; a plurality of trenches in the semiconductor substrate, through the source area and the channel, and at least partially through the drain area; a floating gate in each of the plurality of trenches, overlapping the source and drain areas, configured to control a current flow between the source and drain areas in accordance with a programmed or erased state of the floating gate; an insulating layer on an outer surface of each of the floating gates; a tunneling gate directly on the insulating layer, intersecting and overlapping each of the plurality of floating gates, the tunneling gate adapted to program and/or erase the floating gates; a control gate intersecting and overlapping each of the plurality of the floating gates, spaced apart from and not overlapping with the tunneling gate.