Patent ID: 8723193
Filing Date: 2014-05-13
Classification: H01L,H05K

Abstract:
1. A multiple-layer wiring substrate having a first conductive layer formed on the substrate; an interlayer insulating layer formed on the first conductive layer; and a second conductive layer formed on the interlayer insulating layer, and having a structure in which the first conductive layer and the second conductive layer arc electrically connected via a contact hole formed in the interlayer insulating layer, wherein the interlayer insulating layer includes a material whose surface energy is changed by receiving energy, and has a first region which does not include the contact hole and a second region which is formed such that its surface energy is higher than that of the first region, wherein a region within the contact hole of the first conductive layer has surface energy which is higher than surface energy of the second region of the interlayer insulating layer, and wherein the second conductive layer is formed by laminating, wherein the second conductive layer is in contact with the second region of the interlayer insulating layer along the second region, and is connected to the first conductive layer via the contact hole, wherein the first conductive layer has multiple crystal grains in a region within the contact hole, and wherein at least one of surface roughness and grain diameter is larger in a central portion within the contact hole of the first conductive layer than in the vicinity of an end of the contact hole.