Patent ID: 6342789
Filing Date: 2002-01-29
Classification: G01R,H01L,H05K

Abstract:
An apparatus for testing an array of semiconductor dice in wafer form, comprising:a first rigid support member configured to receive the array of semiconductor dice in wafer form in a predetermined orientation, the first rigid support member having a plurality of contact members formed directly thereon and having electrical connectors electrically connected to the contact members and configured to establish electrical communication with test circuitry; a second rigid support member configured to selectively engage the first rigid support member to retain the array of semiconductor dice in wafer form therebetween, one of the first rigid support member and the second rigid support member including a single cavity for retaining the array of semiconductor dice in wafer form therein during testing; and a single biasing assembly including a single floating platform of a preselected area substantially sized and configured to correspond with said single cavity, the single biasing assembly mounted to one of the first rigid support member and second rigid support member, the single biasing assembly sized and configured to uniformly bias the array of semiconductor dice located in wafer form against the contact members.