Patent ID: 7141727
Filing Date: 2006-11-28
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of fabricating a nanotube field effect transistor, comprising: (a) providing a back gate layer; (b) forming a gate dielectric layer on the back gate layer; (c) forming a local gate electrode and an insulating layer on the gate dielectric layer; (d) forming a nanotube on the insulating layer and the gate dielectric layer, where said nanotube has a central region disposed on the insulating layer and a first end and a second end disposed on the gate dielectric layer; (e) forming a source electrode on the first end of the nanotube, where the source electrode is separated from the central region by a first region of the nanotube; (f) forming a drain electrode on the second end of the nanotube, where the drain electrode is separated from the central region by a second region of the nanotube; (g) doping the nanotube in the first region and in the second region; and (h) forming in the gate dielectric layer and the back gate layer at least one trench beneath the nanotube in at least one of the first region and the second region.