Patent ID: 7418684
Filing Date: 2008-08-26
Classification: G06F

Abstract:
1. A method comprising: automatically determining a plurality of sensitization conditions of a multi-mode clock circuit network to one or more clock signals, wherein the multi-mode clock circuit network is operable in a plurality of modes with a plurality of clock signals and a sensitization condition with respect to a clock signal is an input signal logic condition to the multi-mode clock circuit network under which the respective clock signal is active to affect an output of the multi-mode clock circuit network, wherein at least one sensitization condition of the multi-mode clock circuit network is automatically determined by computing cofactor operations of an output signal of the multi-mode clock circuit network with respect to a polarity of one of the plurality of clock signals, wherein the output signal is represented by a Boolean logic function of one or more input signals of the multi-mode clock circuit network; and automatically eliminating false paths from a plurality of clock paths in the multi-mode clock circuit network in response to the plurality of sensitization conditions.