Patent ID: 6778444
Filing Date: 2004-08-17
Classification: G11C

Abstract:
A differential driver circuit, comprising:a first sense amplifier, coupled to a cache memory, to sense a first cache line and a second cache line from the cache memory; a first input driver circuit, coupled to the first sense amplifier, to receive the sensed first cache line and the sensed second cache line from the first sense amplifier, and to store the received first cache line in a split buffer; a second sense amplifier, coupled to the split buffer, to sense the stored first cache line from the split buffer; a second input driver circuit, coupled to the second sense amplifier, to receive the sensed data from the second sense amplifier; a control logic circuit, coupled to the first and second sense amplifiers, to compare the sensed first and second cache lines, and to send a command signal to the first and second input driver circuits based on the outcome of the comparison, wherein the first and second input driver circuits outputs substantially simultaneously the received first and second cache lines, respectively; and a cache output bus circuit, coupled to the first and second input drivers, to deliver the outputted first and second cache lines, respectively.