Patent ID: 6456135
Filing Date: 2002-09-24
Classification: H04N

Abstract:
In a mixed signal integrated circuit characterized by analog signal circuitry and digital signal circuitry, a method of resetting both the analog signal circuitry and the digital signal circuitry comprising:providing a master reset signal to the integrated circuit; generating a clock reset signal of a first predetermined duration in response to the master reset signal, the clock reset signal operable to cease generation of a plurality of system clocks by the analog signal circuitry during the first predetermined duration and to allow generation of the plurality of system clocks by the analog signal circuitry after the first predetermined duration; and generating a digital reset signal of a second predetermined duration in response to the master reset signal, the digital reset signal operable to maintain the digital signal circuitry in an idle state during the second predetermined duration and to cause the digital signal circuitry to start up in a known state after the second predetermined duration, the second predetermined duration being greater than the first predetermined duration.