Patent ID: 7987591
Filing Date: 2011-08-02
Classification: G01R,Y10T

Abstract:
1. A method of forming a silicon chicklet pedestal for use in a wafer-level test probe from a silicon wafer having first and second opposing faces, the method comprising: forming a first layer at the first and second faces; forming a second layer, including an array of pre-vias, on the first layer at the first face and forming a third layer on the first layer at the second face; etching an array of vias, as respective extensions of each of the pre-vias, through the first layer at the first face and through the silicon wafer; removing the first, second and third layers from the silicon wafer; introducing at least a conductive material in each of the vias by insulating sidewalls of each, depositing a fourth layer to the insulated sidewalls, removing a liner of the silicon wafer, filling remaining space in each of the vias with a filling and curing the filling; and forming a pair of leads for each of the vias at the first and second faces, the leads of each pair being electrically connectable by the conductive material of the corresponding via.