Patent ID: 7227809
Filing Date: 2007-06-05
Classification: G11C,H03K,H03L

Abstract:
1. A clock generator, comprising: a delay locked loop having first and second inputs to which first and second input clock signals are respectively applied, the first and second input clock signals complementary, the delay locked loop further having first and second outputs at which the first and second output clock signals are provided and first and second adjustable delay circuits coupled to respective inputs and outputs, the delay locked loop configured to adjust the first adjustable delay circuit to generate a first output clock signal synchronized with the first input clock signal and configured to adjust the second adjustable delay circuit to provide a delay equal to the first adjustable delay circuit; and a duty cycle correction circuit coupled to the first and second inputs of the delay locked loop and further coupled to the second adjustable delay circuit, the duty cycle correction circuit configured to determine a duty cycle error of at least one of the first and second input clock signals and adjust the second adjustable delay circuit to provide a corrected delay compensating for the duty cycle error.