Patent ID: 6825704
Filing Date: 2004-11-30
Classification: H03K

Abstract:
A pulse generation circuit for generating an output pulse with an activated level in response to a leading edge of a set pulse, the pulse generation circuit comprising:an output stage gate having a first output transistor for setting the output pulse to be activated level and a second output transistor for setting the output pulse to be deactivated level, wherein a drain of the first output transistor and a drain of the second output transistor are each connected to an outout of the output stage gate; a first inverter array, including a plurality of inverters connected in series, for propagating the set pulse and driving the first output transistor; a second inverter array, including a plurality of inverters connected in series, for propagating a reset pulse controlling deactivation of the output pulse and for driving the second output transistor; and at least one reset transistor, wherein a drain of the at least one reset transistor is connected to an output of a corresponding one of the plurality of inverters of the first inverter array, for driving the pulse edge at the inverter output corresponding to a trailing edge of the set pulse, in response to the reset pulse propagating through the second inverter array.