Patent ID: 6218977
Filing Date: 2001-04-17
Classification: H03M

Abstract:
An apparatus for distributing mismatched error associated with a plurality of data converter elements, comprising:a first plurality of shifting units forming a first shifting column, said first shifting column configured to receive an n-bit binary word;a first input for each of said first plurality of shifting units, said first input receiving a single bit of said n-bit binary word;a second input for each of said plurality of shifting units, said second input connected to said first input of another one of said first plurality of shifting units; anda first output for each of said first plurality of shifting units;a first select line configured to apply a first switch signal to said first plurality of shifting units that results in said plurality of shifting units effectuating a shift of said n-bit binary word received by said first input such that the mismatched error associated with the plurality of data converter elements is distributed; and whereinthe first input and second input of each shifting unit are uniquely configured such that each shifting unit receives a unique combination of inputs.