Patent ID: 9135389
Filing Date: 2015-09-15
Classification: G06F,H01L,H03K

Abstract:
1. An adjusting method of clock transmission applied to integrated circuit design, the integrated circuit design includes a substrate and a wiring, the adjusting method comprising steps of: providing a timing path to the substrate including at least a clock source and a sequential logic cell, the clock source and the sequential logic cell electrically connected with each other through the wiring so as to form the timing path; and inserting at least one non-active wire delay module on the substrate in the timing path for adjusting the clock transmission time to approach a predetermined clock arrival time through the non-active wire delay module; wherein the non-active wire delay module is implemented by a multi-layer wiring structure on the substrate of the integrated circuit; wherein the multi-layer wiring structure comprises a plurality of wires allocated on different wiring layers; wherein two of the plurality of wires allocated on different wiring layers are electrically connected to each other through a via or a via array.