Patent ID: 6060922
Filing Date: 2000-05-09
Classification: H03K

Abstract:
A duty cycle control buffer, comprising:an edge detector circuit, for receiving an input clock signal at a frequency f, and for outputting a one shot pulse signal for each transition cycle of said input clock signal, wherein: said one shot pulse signal comprising a pulse train at a frequency equal to f, and with a duty cycle less than 50%,a monostable multivibrator circuit, for receiving said one shot pulse signal from said edge detector circuit, and for generating therefrom rectangular output pulse signals having a controllable pulse width, said controllable pulse width being controlled by a feedback circuit element within said monostable multivibrator circuit, wherein said feedback circuit element comprises a CMOS transistor,an inverter circuit, for receiving said rectangular output pulse signals from said monostable multivibrator circuit, and for inverting said rectangular output pulse signals, such that the duty cycle of the inverted rectangular output pulse signals is the complement of the duty cycle of said rectangular output pulse signals from said monostable multivibrator circuit,an integrator circuit, for receiving said inverted rectangular output pulse signals from said inverter circuit, and for generating an output representing an average voltage of said inverted rectangular output pulse signals,an operational amplifier circuit, for receiving the average voltage output from said integrator circuit at one differential input, and for receiving a reference voltage at the other differential input, said operational amplifier outputs a control signal proportional to the difference between said average voltage and the reference voltage,wherein said control signal is fed back to said feedback circuit element within said monostable multivibrator circuit for controlling the pulse width of said rectangular pulse output signals.