Patent ID: 7118953
Filing Date: 2006-10-10
Classification: H01L

Abstract:
1. A process of fabricating a termination region for a trench MIS device comprising: providing a semiconductor wafer, said wafer comprising a first layer of a first conductivity type and a second layer of a second conductivity type overlying said first layer; forming a first trench in said wafer, said first trench coinciding with a scribe line bordering a die of said wafer, a bottom of said first trench being located in said second layer; introducing a dopant of said first conductivity type through a bottom of said first trench to form a region of said first conductivity type extending from said bottom of said first trench to said first layer; forming an insulating layer in said first trench and over a surface of said layer of second conductivity type; forming a termination metal layer over said insulating layer in said first trench and over said surface of said layer of second conductivity type; etching an opening in said metal layer at a bottom of said first trench, said scribe line intersecting said opening; and sawing said wafer at said scribe line.