Patent ID: 6096642
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A method for forming self-aligned silicide in an integrated circuit without causing a bridging effect, the method comprising the steps of:preparing a semiconductor substrate;forming a gate oxide layer at a selected location over the substrate;forming a polysilicon gate over the gate oxide layer;forming an etch-end layer over the polysilicon gate;forming a sacrificial layer over the etch-end layer;forming a spacer structure on the sidewall of the stacked structure of the gate oxide layer, the polysilicon gate, the etch-end layer, and the sacrificial layer;forming source/drain regions in the substrate;performing an etching process to remove the entire sacrificial layer so that the etch-end layer is exposed;removing the entire etch-end layer;forming a metallization layer over the entire wafer;performing a thermal annealing process to allow those portions of the metallization layer that are laid directly over the polysilicon gate and the source/drain regions to be converted into silicide; andremoving all the unreacted part of the metallization layer.