Patent ID: 8588221
Filing Date: 2013-11-19
Classification: H04L

Abstract:
1. An interface for interfacing a radio frequency transceiver with a baseband processor, the interface comprising: a first sub-interface configured to receive a first inbound IQ data stream, packetize the first inbound IQ data stream to obtain first inbound IQ data packets, and transmit the first inbound IQ data packets to the baseband processor via a first set of RX lanes, wherein each first inbound IQ data packet comprises a data packet identifier out of a common set of possible data packet identifiers; a second sub-interface configured to receive a second inbound IQ data stream, packetize the second inbound IQ data stream to obtain second inbound IQ data packets, and transmit the second inbound IQ data packets to the baseband processor via a second set of RX lanes, wherein each second inbound IQ data packet comprises a data packet identifier out of the common set of possible data packet identifiers; and a third sub-interface configured to receive outbound IQ data packets from the baseband processor via a TX lane, and depacketize the outbound IQ data packets to obtain an outbound IQ data stream; wherein the third sub-interface is configured to further receive an RX not-acknowledge signal from the baseband processor via the TX lane, wherein the RX not-acknowledge signal identifies a defective first or second inbound IQ data packet within the first and second inbound IQ data packets by indicating the data packet identifier of the defective first or second inbound IQ data packet and the first or second set of RX lanes via which the defective first or second inbound IQ data packet is transmitted.