Patent ID: 6560305
Filing Date: 2003-05-06
Classification: H03L

Abstract:
A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data, comprising:(A) a voltage controlled oscillator for producing the clock pulses, the frequency of such clock pulses changing in accordance with a control signal, each one of the clock pulses having four sequential, one-quarter period phases, adjacent phases being separated by boundaries; (B) a frequency detector fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data, such frequency detector comprising: (i) a pair of clock pulse/detected data edge latches fed by the clock pulses and the detected edges of the stream of binary data, one of such latches storing a binary signal indicating when a detected edge occurs during one of a first pair of sequential phases of the four phases of the clock pulse and another one of latches producing a binary signal indicating when a detected edge occurs during the other one of the first pair of sequential phases of the four phases of the clock pulse; (ii) a network, fed by the clock pulse/detected data edge latches, the clock pulses produced by the voltage controlled oscillator, and a block/unblock control signal, adapted to produce the control signal when a detected edge crosses the boundary between first and second quadrants and when the block/unblock control signal is in an unblock condition; (iii) a lock-out circuit adapted to produce the block/unblock control signal to place the network in a block condition to prevent subsequent production of the control signal and to maintain such block condition until a subsequently detected edge crosses a different one of the boundaries to thereby place the network in the unblock condition.