Patent ID: 9123561
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A superjunction semiconductor device comprising: a first conductivity type semiconductor substrate having two main surfaces; a first conductivity type drift layer having two regions comprising a plurality of first conductivity type drift regions and second conductivity type partition regions disposed in alternate contact between the two main surfaces of the first conductivity semiconductor substrate; an element active portion through which a main current flows, with a first region of the drift layer which is in the element active portion including first parallel pn layers; and a ring-like element peripheral portion having inner and outer peripheral portions, the ring-like element peripheral portion encircling the element active portion, with a second region of the drift layer which is in the peripheral portion having second parallel pn layers the peripheral portion further comprising a first conductivity type surface layer region which covers the surface of the second parallel pn layers, the first conductivity type surface layer region having an impurity concentration lower than that of the drift layer, the ring-like element peripheral portion further comprising second conductivity type partition regions, wherein all partition regions in the outer peripheral portion of the ring-like peripheral portion have a depth which is less than the depth of partition regions in the inner peripheral portion of the ring-like peripheral portion, and two or more second conductivity type guard ring regions disposed in the inner peripheral portion of the element peripheral portion and distanced from each other so as to surround the outer periphery of the first parallel pn layer in the surface layer of the low concentration first conductivity type surface layer region, wherein the two regions in the drift layer each have a width such that a depletion layer spreading in the two regions from the pn junction between the two regions when an off-state voltage is applied to the main junction can deplete the drift layer, wherein the repeating pitch interval of the second parallel pn layers in the ring-like element peripheral portion encircling the element active portion is smaller than the repeating pitch interval of a first parallel pn layers in the element active portion, and wherein the depth of the second conductivity type partition regions in the outer peripheral portion are the same.