Patent ID: 8407650
Filing Date: 2013-03-26
Classification: G06F

Abstract:
1. A computer-implemented method for designing an integrated circuit, the method comprising: identifying, with one or more processors associated with one or more computer systems, one or more instances of a repeated block within the integrated circuit; shaping layout, with the one or more processors associated with the one or more computer systems, for each instance of a repeated block; performing, with the one or more processors associated with the one or more computer systems, repeated block placement on the one or more instances of a repeated block; performing, with the one or more processors associated with the one or more computer systems, repeated block flyover implementation in the layout for each instance of a repeated block such that flyovers for each instance of a repeated block accommodate global routing requirements; and performing, with the one or more processors associated with the one or more computer systems, repeated block buffer insertion.