Patent ID: 6333226
Filing Date: 2001-12-25
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory device, comprising:forming a transistor having a first conductive layer, a second conductive layer and a gate electrode on a semiconductor substrate;forming a first insulating film and a stopper insulating film on said transistor;forming a first opening in said first insulating film and said stopper insulating film so as to expose a portion of said first conductive layer;forming a first conductive film serving as a first electrode over a range from a portion of an exposed surface of said stopper insulating film to said first conductive layer exposed in said first opening;forming a sacrifice film on said first conductive film;forming a second conductive film serving as said first electrode on said sacrifice film;removing said sacrifice film;forming a second insulating film so as to cover exposed portions of said first and second conductive films;forming a third conductive film serving as a second electrode on said second insulating film;forming a second opening in said insulating film and said stopper insulating film so as to expose a portion of said second conductive layer; andembedding a conductive substance in said second opening so that a height from the second conductive layer to a top of the conductive substance is higher than a height from the first conductive layer to a top of the stopper insulating film and lower than a height from the first conductive layer to a top of the third conductive film.