Patent ID: 6175905
Filing Date: 2001-01-16
Classification: G11C

Abstract:
A memory device command generator adapted to receive a command packet indicative of a memory command, the command generator comprising:a command unit coupled to receive at least a portion of the command packet, the command unit being constructed to output a command signal corresponding to the portion of the command packet received by the command unit, the timing at which the command unit outputs the command signal being determined by a latency command corresponding to a latency that is greater than a minimum latency of the command unit; anda bypass circuit coupled to receive at least a portion of the command packet, the bypass circuit being constructed to generate the command signal corresponding to the command packet received by the bypass circuit, the bypass circuit being constructed to respond to a latency command that is shorter than the minimum latency of the command unit by outputting the command signal at a time corresponding to the latency command.