Patent ID: 6174773
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A method of manufacturing a vertical trench MISFET, comprising the steps of:preparing a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer disposed on the first conductivity type semiconductor;forming a trench extending from a surface of said semiconductor substrate to reach said first conductivity type semiconductor;forming a second conductivity type base region in a top portion of said semiconductor substrate;forming a first conductivity type source region in a part of a surface layer of said second conductivity type base region;forming an impurity diffused layer by obliquely implanting ions into a side wall of said trench, which is then subjected to heat treatment, thereby to form a first conductivity type drain drift region in a surface layer of the side wall of the trench, said first conductivity type drain drift region having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;forming a gate electrode on an exposed surface of said second conductivity type base region, through a gate insulating film;forming a source electrode in contact with surfaces of both of said first conductivity type source region and said second conductivity type base region; andforming a drain electrode in contact with a rear surface of said first conductivity type semiconductor.