Patent ID: 6020261
Filing Date: 2000-02-01
Classification: H01L,H05K

Abstract:
A method of forming high resolution circuit features on a substrate, comprising the following steps in the order named:providing a dielectric substrate having an electrically conductive layer deposited thereon;depositing a dielectric film on the electrically conductive layer;depositing a metal film on the dielectric film;depositing a photoresist layer on the metal film;selectively removing portions of the photoresist layer such that portions of the metal film are revealed;removing the revealed portions of the metal film by etching, so as to reveal underlying portions of the dielectric film;removing the remaining portions of the photoresist layer and the revealed underlying portions of the dielectric film so as to expose portions of the electrically conductive layer;removing the remaining portions of the metal film;plating copper onto the exposed portions of the electrically conductive layer;removing the remaining portions of the dielectric layer so as to expose additional portions of the electrically conductive layer;removing the exposed portions of the electrically conductive layer.