Patent ID: 8522066
Filing Date: 2013-08-27
Classification: G06F

Abstract:
1. An apparatus comprising: a non-volatile storage to store semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer, the SIC including an embedded processor logic to initialize a processor and at least one communication link that couples the processor to a system memory, and an embedded memory logic to initialize the system memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to pre-boot code of an original equipment manufacturer (OEM), wherein the SIC is provided as a binary to the OEM for inclusion in the non-volatile storage, the non-volatile storage including OEM basic input/output system (BIOS), wherein responsive to a system restart, a firmware integration table (FIT) is to be accessed to determine whether a SIC entry in the FIT corresponds to a maximum revision of the SIC, an initial program loader (IPL) is to be executed, the SIC is to be executed if the IPL is executed successfully to initialize the processor, wherein a boot failure is to occur responsive to at least one of the FIT is not able to be accessed, the SIC entry does not correspond to the maximum revision, the SIC is non-authenticated, and the processor is not properly initialized.