Patent ID: 6137164
Filing Date: 2000-10-24
Classification: H01L,H05K

Abstract:
A thin face-to-face stacked integrated circuit packaging structure comprising:a rigid interposer board having a first surface and a second surface with printed wiring circuits disposed on each surface for mounting an integrated circuit chip on each surface; andsaid two integrated circuit chips having an array of electrical terminals connected electrically and mechanically to contact pads on the first and the second surfaces of said interposer board by a conductor having low alpha emissivity; andsaid integrated circuits terminals electrically interconnected by printed metal traces on said interposer board to conductive vias between the first and second surfaces; andsaid vias terminate in external connectors which comprise solder on the lower (or second) surface of the structure which comprise solder balls; andsaid structure having perimeters slightly greater than the larger chip, and the thickness of the structure is in the range of 1.25 mm to 1.5 mm, and the space between said chips and interposer filled with an underfill polymer formulated with an electrically insulating, thermally conductive powder.