Patent ID: 8924606
Filing Date: 2014-12-30
Classification: G06F

Abstract:
1. A storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor configured to process data requested to be input or output; a plurality of transfer controllers configured to transfer data between memories in the storage system; and at least one transfer sequencer configured to request a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor; wherein: the processor is configured to transmit a series of data transfer requests to the at least one transfer sequencer; the at least one transfer sequencer is configured to request a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests; and each transfer controller is configured to transfer data between the memories in accordance with an instruction from the at least one transfer sequencer, wherein a data transfer request includes an address where DMA control parameters are stored, and wherein DMA control parameters include address of a transfer source, address of a transfer destination, length of data to be transferred, transfer path, protection code, and end status storage address.