Patent ID: 6828651
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A Bipolar-CMOS-DMOS (BCD) integrated circuit comprising:a substrate having a first conductivity type; an epitaxial layer on said substrate and having the first conductivity type and a conductivity less than a conductivity of said substrate; first and second regions in said epitaxial layer each having a second conductivity type opposite the first conductivity type, said first and second regions extending from a surface of said epitaxial layer opposite said substrate into said epitaxial layer to form respective first and second normally reverse-biased junctions therewith; the first region defining a power section integrated in said epitaxial layer, and the second region defining a signal processing section integrated in said epitaxial layer, at least one of said power section and said signal processing section including at least one of a bipolar transistor and a DMOS transistor; first and second electrodes for independently biasing the first and second junctions, respectively; and an isolating element positioned between said first and said second regions and extending from the surface of said epitaxial layer at least as far as a top surface of said substrate for reducing an injection of current through said epitaxial layer from said first region to said second region when the first junction is biased to cause the injection of current, said isolating element comprising a dielectric material adjacent said epitaxial layer and polycrystalline silicon spaced apart from said epitaxial layer by said dielectric material, said isolating element also surrounding said first region on all lateral sides terminating above a bottom surface of said substrate.