Patent ID: 6385672
Filing Date: 2002-05-07
Classification: G06F,H04L

Abstract:
An apparatus for partitioning a buffer memory in an interface to a network, comprising:a memory comprising, a transmit buffer that includes addresses designated by a start of read packet pointer, a read pointer, and an end of read packet pointer, wherein the read pointer progresses in a first direction through the addresses, wherein the end of read packet pointer includes an address; and a receive buffer that includes addresses designated by a start of write packet pointer, and a write pointer, wherein the write pointer progresses in a second direction through the addresses toward the read pointers; wherein an address at which the read pointer and the write pointer meet is a boundary between the transmit buffer and the receive buffer that determines a size of the transmit buffer and a size of the receive buffer, wherein the memory is configurable to preselect a size range of the transmit buffer and a size range of the receive buffer; and a controller coupled to the memory, comprising, first circuitry for generating a new write pointer, comprising an arithmetic and logic unit that performs operations on the start of write packet pointer, and the write pointer; and second circuitry for generating a new read pointer, comprising an arithmetic and logic unit that performs operations on the start of read packet pointer, the end of read packet pointer, and the read pointer.