Patent ID: 8907413
Filing Date: 2014-12-09
Classification: H01L

Abstract:
1. A dual trench MOS transistor comprising of: a plurality of trenches formed in an n− epitaxial layer on a heavy doped n+ semiconductor substrate and spaced with each other with one of mesas, wherein each the trench has a trench oxide layer formed on a bottom and sidewalls thereof, a first polysilicon layer with a conductive impurity is formed in the plurality of trenches; a plurality of recesses formed in the mesas, wherein each the recess has a recess oxide layer formed on a bottom and sidewalls thereof, a second polysilicon layer with a conductive impurity for serving as a gate is formed in the plurality of recesses to form MOS structures, wherein each the MOS structure includes the second polysilicon layer, the recess oxide layer and the n− epitaxial layer; ion implanted areas formed in the n− epitaxial layer below the mesas at two sides of the MOS structures; an interconnect dielectric layer formed on the first polysilicon layer, the MOS structures and the ion implanted areas; a plurality of through holes formed in the interconnect dielectric layer, wherein a first group of the through holes connect the first polysilicon layer formed in the plurality of the trenches and the ion implanted areas which are applied to serve as a source and a second group of the through holes connect the gate of the MOS structures; an interconnect metal layer formed on the interconnect dielectric layer and in the plurality of the through holes and patterned to connect the source and the gate respectively through the first group and the second group of the through holes; and a metal layer formed on a rear surface of the heavy doped n+ semiconductor substrate for serving as a drain.