Patent ID: 8924690
Filing Date: 2014-12-30
Classification: G06F,Y02D

Abstract:
1. A semiconductor die, comprising: a first processing core and a second processing core both coupled to a processor controller; said first processing core having a first register, a bit position of said first register to indicate whether said first processing core is permitted to issue an instruction in a given cycle, said first register's contents being writable to define a first percentage of cycles in which said first processing core is permitted to process a next instruction over the course of said first processing core's operation until such time that said first register's contents are changed; said second processing core having a second register, a bit position of said second register to indicate whether said second processing core is permitted to issue an instruction in a given cycle, said second register's contents being writable to define a second percentage of cycles in which said second processing core is permitted to process a next instruction over the course of said second processing core's operation until such time that said second register's contents are changed; and wherein said processor controller is to prioritize an issuance of an instruction by said first processing core over an issuance of an instruction by said second processing core when said first percentage is greater than said second percentage.