Patent ID: 7617432
Filing Date: 2009-11-10
Classification: H03M

Abstract:
1. An apparatus for performing a low density parity check decoding operation, the apparatus includes: a hierarchical arrangement of variable node processing elements, said first hierarchical arrangement including variable node processing elements arranged into a plurality of first clusters, the variable node processing elements in each of said first clusters having in common at least a portion of a bus that is shared by the processors in the cluster on a time shared basis, each cluster including at least one shared pipeline register, said first clusters arranged to form a second cluster, said second cluster being a cluster of said first clusters; a hierarchical arrangement of check node processing elements, said hierarchical arrangement of check node processing elements including check node processing elements arranged into a plurality of first check node clusters which are arranged grouped together to form a higher level cluster; and a switching fabric for coupling said second cluster to said hierarchical arrangement of check node processors, said switching fabric being implemented as a series of multiple combinational switches coupled in series by pipeline registers.