Patent ID: 6177341
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for forming interconnections in semiconductor devices, comprising the following steps:(a) providing a semiconductor substrate;(b) forming a first conductive layer on the semiconductor substrate;(c) forming a dielectric layer on the first conductive layer;(d) forming a first hole through the dielectric layer, wherein the bottom of the first hole contacts the first conductive layer;(e) forming a contact layer on the dielectric layer and on the contact surface of the first hole and the first conductive layer, wherein the first hole is reduced to a second hole;(f) forming a barrier layer on the contact layer, wherein the second hole is reduced to a third hole;(g) carrying out a rapid thermal annealing process, comprising the following steps:placing the semiconductor substrate, which is at ambient temperature, into a quartz heating chamber, wherein the chamber is filled with nitrogen gas at a first flow rate;reducing the first flow rate to a second flow rate, rapidly heating the semiconductor substrate to a high temperature and lasting for a period of time; andincreasing the second flow rate to a third flow rate, rapidly reducing the semiconductor substrate temperature, and taking the semiconductor substrate out of the quartz heating chamber;(h) filling the third hole with a second conductive layer; and(i) forming a third conductive layer on the second conductive layer, wherein the third conductive layer connects the first conductive layer by the second conductive layer.