Patent ID: 7818550
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A method of processing an instruction stream, comprising: fetching, by a fetch stage, a stream of instructions from an instruction source, thus providing a fetched stream of instructions; decoding, by a decoder, the fetched stream of instructions, thus providing a decoded stream of instructions; detecting, by a detector, a first latency instruction in the decoded stream of instructions followed by a second latency instruction, the second latency instruction exhibiting a latency less than the first latency instruction exhibits, the detector detecting if the second latency instruction is dependent on the first latency instruction and destructive of a result of the first latency instruction; dynamically fusing, subsequent to the detecting step, the second latency instruction with the first latency instruction to execute the second latency instruction with the first latency instruction if the detector detects that the second latency instruction is dependent on the first latency instruction and is destructive of the result of the first latency instruction, the dynamic fusing being performed during execution of the second latency instruction and the first latency instruction; sending, by an issue queue, the first latency instruction to a secondary execution stage, the secondary execution stage exhibiting a latency greater than a primary execution stage; sending, by the issue queue, the second latency instruction to the primary execution stage if the detector determines that the second latency instruction is not dependent on, or is not destructive of, the first latency instruction; and sending, by the issue queue, the second latency instruction to the secondary execution stage for dynamic fusing with the first latency instruction during execution if the detector determines that the second latency instruction is dependent on, and destructive of, the first latency instruction.