Patent ID: 7596041
Filing Date: 2009-09-29
Classification: G06F,G11C

Abstract:
1. A nonvolatile memory system comprising: one or more nonvolatile semiconductor memories; an internal power supply line which supplies an internal power source voltage to said one or more nonvolatile semiconductor memories based on an external power source voltage; a capacitor electrically coupled between said internal power supply line and a ground voltage; an information processor to provide to said one or more nonvolatile memories a data writing operation instruction, said information processor being electrically coupled to said internal power supply line; a first voltage monitoring unit to output a power-on reset signal when the internal power source voltage reaches a first voltage level; and a second voltage monitoring unit to output an emergency stop signal when the external power source voltage reaches a second voltage level, wherein, when said information processor receives the emergency stop signal output from said second voltage monitoring unit, said information processor stops a data writing operation being performed and enters a no-response state in which a process request from outside is not granted, and wherein, when said information processor receives the power-on reset signal output from said first voltage monitoring unit, said information processor performs a reset operation.