Patent ID: 8765551
Filing Date: 2014-07-01
Classification: H01L

Abstract:
1. A method of manufacturing a non-volatile memory device having a vertical structure, the method comprising: stacking a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately on a substrate; forming a stacking structure by etching a first portion of the plurality of sacrificial layers and the interlayer insulating layers to form a plurality of sacrificial layer patterns and a plurality of interlayer insulating layer patterns, the plurality of sacrificial layer patterns and the plurality of interlayer insulating layer patterns defining first openings in the stacking structure that expose an upper portion of the substrate; forming semiconductor layer patterns in the first openings of the stacking structure; etching a second portion of the stacking structure to define a second opening in the stacking structure that is between the semiconductor layer patterns; etching the plurality of sacrificial layer patterns to define a plurality of rib grooves; forming a storage structure on the semiconductor layer patterns in the plurality of rib grooves, the storage structure including at least one blocking insulating layer recessed a first distance in a direction from a sidewall defined by the plurality of interlayer insulating layer patterns to the semiconductor layer patterns; and forming a plurality of gate patterns on the semiconductor layer patterns in the plurality of rib grooves, the plurality of gate patterns being recessed a second distance in the direction from the side-wall defined by the plurality of interlayer insulating layer patterns to the semiconductor layer patterns, the second distance being greater than the first distance.