Patent ID: 6041167
Filing Date: 2000-03-21
Classification: G06F

Abstract:
A processing system, comprising:sequencer circuitry for initiating a plurality of processing stages of first, second and third instructions, said second instruction being an execution serialized instruction;execution circuitry coupled to said sequencer circuitry; anddispatch circuitry coupled to said execution circuitry for:finishing a dispatch processing stage of said first instruction so that said first instruction is dispatched to said execution circuitry;in response to finishing said dispatch processing stage of said first instruction, finishing a dispatch processing stage of a second instruction so that said second instruction is dispatched to said execution circuitry; andin response to finishing said dispatch processing stage of said second instruction, finishing a dispatch processing stage of a third instruction so that said third instruction is dispatched to said execution circuitry; andsaid execution circuitry being operable to reorder an execution sequence of said first, second and third instructions subsequent to said first, second and third instructions being dispatched to said execution circuitry and to initiate an execution processing stage of said dispatched third instruction prior to initiating an execution processing stage of said dispatched second instruction.