Patent ID: 6028497
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A multi-chip module, comprising:a substrate for supporting a plurality of RF electronic circuits; said substrate comprising a dielectric material, a rigid physical characteristic, and a flat geometry;said substrate including a first ground plane conductor on an upper surface and a second ground plane conductor on a bottom surface, said second ground plane conductor being connected to said first ground plane conductor to place said ground plane conductors electrically in common;said substrate further including a first plurality of electrical vias extending through said substrate;a metal seal ring;said metal seal ring being attached to an upper surface of said substrate in contact with said first ground plane conductor;said metal seal ring providing a peripheral wall about an upper surface of said substrate for walling in a predefined region of said substrate's upper surface, said seal ring further providing a plurality of subsidiary walls connected to said peripheral wall and located in said predefined region for dividing said predefined region into a plurality of separate compartments;said first plurality of electrical vias being spacially distributed about said substrate to define a first spacial array of vias, and wherein at least one of said plurality of separate compartments contains at least one of said plurality of electrical vias;said substrate further including a plurality of electrical transmission lines, said transmission lines being distributed amongst said separate compartments; at least one of said plurality of transmission lines being electrically connected to respective ones of a first portion of said plurality of electrical vias, each of said transmission lines having a characteristic impedance Z.sub.0 ;a first plurality of conductive pins of a first predetermined length; said first plurality of pins having a first end attached to respective ones of said first portion of said plurality of electrical vias, leaving a second end thereof extending from said substrate;a second plurality of conductive pins of a second predetermined length; said second plurality of conductive pins having a first end attached to respective ones of a second portion of said plurality of electrical vias, leaving a second end thereof extending from said substrate;a metal base plate, said metal base plate being positioned in abutment with an underside surface of said substrate in contact with said second ground plane conductor to place said metal base plate, said second ground plane conductor, said first ground plane conductor and said seal ring electrically in common;said metal base plate including a plurality of passages there through, said passages in said metal base plate being spatially distributed about said base plate in said spacial array, wherein said passages are in alignment with said electrical vias;said passages in said metal base plate being of a third predetermined length, said third predetermined length being greater than said first and second predetermined lengths, wherein said first and second plurality of conductive pins are received within respective ones of said passages in said metal base plate and said second end of said first plurality of conductive pins is positioned within an associated one of said passages in said metal base plate;a plurality of metal shrouds, each comprising a hollow cylindrical portion, and a washer shaped end to said cylindrical portion, defining a central circular opening; andsaid plurality of metal shrouds being positioned within those of said passages in said metal base plate containing conductive pins from said first plurality of conductive pins for surrounding said conductive pins without physical contact therebetween;each said shroud and associated conductive pin defining a coaxial transmission line having a characteristic impedance of said Z.sub.0.