Patent ID: 8101982
Filing Date: 2012-01-24
Classification: H01L

Abstract:
1. A memory device comprising: a plurality of memory cells, each memory cell including a plurality of ferrocapacitors; at least two layers of ferroelectric material arranged in a stacked configuration; an isolation layer separating the at least two layers of ferroelectric material; a plurality of parallel bit lines embedded between the ferroelectric material layers; and a plurality of parallel word lines extending across a respective outer surface of each of the ferroelectric material layers, the word lines arranged orthogonally with respect to the bit lines, wherein each memory cell and the respective ferrocapacitors are located at an intersection of at least two of the word lines and at least one of the bit lines, information is stored via application of an electric field larger than a coercive field of the ferroelectric material between the word lines and the bit lines, and the same voltage level is applied to at least one pair of respective word lines to generate the electric field, wherein a first part of the isolation layer contacts the at least two layers of ferroelectric material, and opposite sides of a second part of the isolation layer, at the intersection of the at least two of the word lines and the at least one of the bit lines, contact at least one of the bit lines and one of the ferroelectric material layers; and wherein at least two adjacent surfaces of each of the bit lines contact one of the ferroelectric material layers.