Patent ID: 8407714
Filing Date: 2013-03-26
Classification: G06F

Abstract:
1. An arithmetic device, comprising: an instruction execution circuit configured to execute a multi-thread mode in which the instruction sequences of a plurality of threads are concurrently executed and a single thread mode in which the instruction sequence of a single thread is executed, configured to reassign hardware resources to a single thread when executing in the single thread mode and divide the hardware resources between the threads active when executing in the multi-thread mode, and configured to place in an offline state an erroneous thread in which a hardware error has occurred during the execution of instruction sequence of the thread when the error is detected; and a switch indication circuit having a thread mode control circuit configured to store a state of a thread in the offline state as an inactive state in a state storage device for storing a state of a thread, and further configured to issue an indication to the instruction execution circuit to switch between the multi-thread mode and the single thread mode depending on the change of the number of threads in the active state, the switch indication circuit including,