Patent ID: 9018065
Filing Date: 2015-04-28
Classification: C23C,H01L

Abstract:
1. A method comprising: forming an n-channel region and a p-channel region in a front side of a wafer, the n-channel and p-channel regions corresponding to locations for forming a negative field-effect transistor (NFET) and a positive field-effect transistor (PFET), respectively; placing the wafer in a wafer holder inside a horizontally oriented furnace having a top surface, a bottom surface, and a gas exhaust, with the wafer oriented vertically between the top and bottom surfaces, the wafer holder being spaced from the bottom surface; recessing the p-channel region of the wafer, by etching the p-channel to a depth of no more than 90 angstroms (Å), inside the furnace; removing any metallic contaminants produced by the recessing step via the gas exhaust; baking the wafer in the furnace after recessing the p-channel region; and epitaxially growing channel silicon germanium (cSiGe) in the recessed p-channel region inside the furnace after baking.