Patent ID: 7636001
Filing Date: 2009-12-22
Classification: G11C,H03L

Abstract:
1. A digital DLL circuit comprising: a first register configured to hold a first delay specifying value to specify a delay value of a rising edge side of a signal; a second register configured to hold a second delay specifying value to specify a delay value of a falling edge side of a signal; a digitally-controlled variable delay circuit configured to be allowed to individually control delays of a rise side and a fall side of a signal; a control circuit configured to implement control so that a rise-side delay and a fall-side delay by the variable delay circuit are kept at the first delay specifying value of the first register and the second delay specifying value of the second register, respectively; a third register configured to hold a delay target value; and a digitally-controlled second variable delay circuit, wherein the control circuit is configured to subject a reference signal and the delay target value of the third register to an arithmetic operation, and supply the second variable delay circuit with a result of the arithmetic operation as a delay control value.