Patent ID: 6246631
Filing Date: 2001-06-12
Classification: G11C

Abstract:
A semiconductor memory device having a block set consisting of a plurality of blocks which are aligned in a vertical direction and which consist of a plurality of cell arrays aligned in a horizontal direction, comprising:a unit for receiving and buffering a block set division address, a refresh mode designating signal and a refresh request signal;a unit for receiving the block set division address to be compressed among the output signals from the buffering unit and a block selection address, and selecting one of the plurality of blocks;a unit for decoding modified signals outputted from the buffering unit, and selecting a right-side or left-side cell array group of a main word line having a double word line structure from the selected block; anda unit for buffering and decoding word line selection address signals, and driving a corresponding main word line, the block set being divided into the identical number of the cell array groups symmetrically from a sub-word line driver positioned at the centers of each block, the right-side cell array groups and the left-side cell array groups being connected respectively to the main word line driving units through the different main word lines.