Patent ID: 7250654
Filing Date: 2007-07-31
Classification: H01L

Abstract:
1. A non-volatile memory device, comprising: a memory cell unit disposed in a memory array region of the non-volatile memory device, the memory cell unit comprising a single-poly PMOS access transistor and a single-poly PMOS storage transistor serially connected to the single-poly PMOS access transistor through a floating P type doping region commonly shared by the single-poly PMOS access transistor and the single-poly PMOS storage transistor, wherein the single-poly PMOS access transistor comprises an access gate, an access gate dielectric of single silicon oxide layer, a P type source doping region and the floating P type doping region acting as a drain of the single-poly PMOS access transistor; the single-poly PMOS storage transistor comprises a control gate, a charge storage structure, a P type drain doping region and the floating P type doping region acting as a source of the single-poly PMOS storage transistor; and a high-voltage MOS transistor disposed in a peripheral circuit region of the non-volatile memory device, the high-voltage MOS transistor comprising a high-voltage gate and a high-voltage gate dielectric layer having a thickness equal to that of the access gate dielectric of single silicon oxide layer.