Patent ID: 6522184
Filing Date: 2003-02-18
Classification: H03K

Abstract:
A static CMOS flip-flop circuit that is composed of a master latch and a slave latch and that operates on a data input signal and a clock input signal fed thereto,wherein the master latch comprises: a data input circuit that, when the clock input signal is at a first level, reads the data input signal; a first data holding circuit that, when the clock input signal is at a second level, holds the data read by the data input circuit; and a signal switching circuit that, when the clock input signal is at the first level, outputs a predetermined level and that, when the clock input signal is at the second level, outputs the data held by the first data holding circuit after inverting it, and the slave latch comprises: a data output circuit that, when the clock input signal is at the second level, reads an output of the signal switching circuit after inverting it; and a second data holding circuit that, when the clock input signal is at the first level, holds the data read by the data output circuit; wherein an output of the data input circuit and an output of the first data holding circuit appear at a first node, and wherein the signal switching circuit comprises: a first P-channel MOS transistor having a gate connected to the first node, having a source connected to a power source, and having a drain connected to a second node; a second P-channel MOS transistor having a gate receiving the clock input signal, having a source connected to the power source, and having a drain connected to the second node; a first N-channel MOS transistor having a gate receiving the clock input signal and having a drain connected to the second node; and a second N-channel MOS transistor having a gate connected to the first node, having a source connected to ground, and having a drain connected to a source of the first N-channel MOS transistor.