Patent ID: 6552574
Filing Date: 2003-04-22
Classification: H03K

Abstract:
A logic circuit comprising:a discharge path connected between a clock line and an output node, the discharge path including one or more transistors configured to evaluate a logic function of at least one input during an evaluation phase; a precharge path connected between the clock line and the output node, the precharge path including a PMOS transistor having a gate and a channel between a source and drain region of the PMOS transistor, the drain being connected to the output node and the source being connected to the clock line; and a control circuit having an output connected to the gate of the precharge path transistor, the control circuit configured to maintain a source-to-gate voltage on the precharge path transistor such that, independent of the states of the inputs and the output node, the channel of the precharge path transistor provides a conductive path between the clock line and the output node during a precharge phase.