Patent ID: 7958421
Filing Date: 2011-06-07
Classification: G01R

Abstract:
1. A single-pass method for generating test pattern sequences for sequential circuits, comprising the steps of: (a) receiving a model of a sequential circuit expressed as a combinational part and a feedback storage part; (b) forming a sequence of time-frames by interconnecting copies of the combinational part; (c) defining a stuck-at fault for a net of the circuit model and inserting a copy of the fault on the net for an initial time-frame; (d) searching the initial time-frame for circuit model present-state and primary input vectors that will activate the fault, and propagate the fault to circuit model next-state lines; (e) defining a fault pattern to represent at which next-state lines the fault arrived; (f) determining a good output level and a faulty output level for each circuit model primary output line; (g) determining whether any primary output line has a good output level that differs from its faulty output level, and if so, flagging the detection of a valid test pattern sequence, and continuing from step (n), else, continuing from step (h); (h) mapping the present state and input vector of step (d) to a good next-state; (i) forming a fault propagation function including the good next-state and a don't-care primary input vector; (j) constructing a new fault including the formed fault propagation function; (k) passing the new fault to a next time-frame by placing the new fault upon present-state lines corresponding to the fault pattern; (l) inserting the new fault at the net of the next time-frame, defining a replacement local fault; (m) searching said next time-frame for the good next-state and a primary input vector that will propagate the fault to next-state lines, and continuing from step (e); (n) extracting the valid test pattern sequence; (o) providing the extracted test pattern sequence to a user and halting.