Patent ID: 6392270
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate; first insulating films formed on element forming regions on the semiconductor substrate; element isolating layers formed on the semiconductor substrate for isolating each of the element forming regions set at regular intervals in the semiconductor substrate, upper surfaces of the element isolating layers being located at a higher level than an upper surface of the semiconductor substrate; first conductive layers formed at regular intervals on the first insulating films, each of the first conductive layers having raising side portions extended up to the surfaces of the element isolating layers to form first stepped portions between edges of the raising side portions and the surfaces of the element isolating layers; a second insulating film formed on the element isolating films and the first conductive layers for electrically isolating each of the first conductive layers by the element isolating layers and the first and second insulating films, the second insulating film including second stepped portions at positions corresponding to the first stepped portions; a second conductive layer formed on the second insulating film, having a lower surface with irregularities corresponding to the configurations of the element isolating layers and the second insulating film formed on the first conductive layers, the second conductive layer being formed of a polysilicon layer having an flat upper surface irrespective of the configurations of the element isolating layers and the first conductive layers; and a flat wiring layer formed on the second conductive layer and containing a high-melting point metal.