Patent ID: 6617899
Filing Date: 2003-09-09
Classification: H03K,H03M

Abstract:
An analog latch, comprising:a first preamplifier and a second preamplifier, series connected and receiving a differential voltage signal and acting to amplify the differential voltage signal, and to output the differential voltage signal; at least one differential clocked analog latch stage, the at least one differential clocked analog latch stage comprising no more than six transistors, receiving the differential voltage signal from the first and second preamplifiers and producing a high signal or a low signal dependent on the differential voltage signal received, an RS latch, connected in series to the at least one differential analog latch stage, receiving and holding the high signal or low signal from the at least one analog latch stage, and a clock generator, producing control signals for the first preamplifier, the second preamplifier, and the at least one analog latch stage, wherein the clock generator generates control signals for the first preamplifier, the second preamplifier, and the at least one analog latch stage, the control signals including timing signals, autozero signals and reset signals.