Patent ID: 8341560
Filing Date: 2012-12-25
Classification: G06F,Y02P

Abstract:
1. A method of designing a semiconductor device comprising: arranging, by using a computer, a plurality of cells used for an electric circuit and a plurality of wirings respectively connected to a plurality of gates of said plurality of cells in a coordinate region to create chip layout data including said plurality of cells, said plurality of gates and said plurality of wirings; checking whether or not each of said plurality of gates included in said chip layout data is in antenna violation; storing antenna violation information in an error-remaining portion library, said antenna violation information representing an antenna violation gate group, in which gates in said antenna violation are contained, in said plurality of gates included in said chip layout data; performing lithography simulation for said chip layout data to create predicted layout data after photoresist exposure; selecting said antenna violation gate group represented by said antenna violation information from said plurality of gates included in said predicted layout data, with reference to said error-remaining library; calculating a calculated value representing a ratio of an area of a wiring of said plurality of wirings with respect to an area of a gate of said antenna violation gate group, selected from said plurality of gates included in said predicted layout data, connected to said wiring, for each gate of said antenna violation group; and adjusting a size of said gate of said antenna violation gate group, when said calculated value of said antenna violation group included in said predicted layout data is in a range between a first setting value and a second setting value larger than said first setting value.