Patent ID: 6396729
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A memory device comprising:a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, with the system bus interface including a bi-directional data bus interface to be coupled to the data bus and a tag bus interface to be coupled to the tag bus; an array of memory cells; a memory operation manager operably coupled to the system bus interface and to the array of memory cells, with said memory operation manager being configured to carry out memory read operations on the array in response to receipt of a memory read command set which includes at least one command and to carry out memory program operations on the array in response to receipt of a memory program command set which includes at least one command and a bus direction controller configured to cause the data bus interface to be set to a direction for transfer of data read from the memory array during the memory read operations and to cause the data bus interface to be set to a direction for transfer of data to the memory device for programming into the array during the memory program operations.