Patent ID: 6119240
Filing Date: 2000-09-12
Classification: G06F,Y02D

Abstract:
A data processor, comprising:a bus having a plurality of bus signals; anda system integration unit coupled to the bus, the system integration unit comprising:a plurality of terminals,a bus coupling circuit to couple the plurality of bus signals to the plurality of terminals, anda first control register containing a set of device attribute bits that selects one of a plurality of pairs of voltage levels as a selected pair of voltage levels, wherein:the plurality of pairs of voltage levels comprises a first pair of voltage levels selected by a first data attribute value and a second pair of voltage levels selected by a second data attribute value;each of the plurality of pairs of voltage levels includes a first voltage level and a second voltage level;a difference between the first voltage level and the second voltage level for each of the plurality of pairs of voltage levels forms a voltage swing;the first pair of voltage levels contains at least one voltage level different than the second pair of voltage levels; andthe selected pair of voltage levels is applied to the bus.