Patent ID: 9177802
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps: providing a substrate comprising semiconductor material at a top surface of said substrate; forming a gate of an analog metal oxide semiconductor (MOS) transistor over said substrate, said analog MOS transistor having a first source/drain gate edge at said top surface of said substrate directly under a first lateral surface of said gate and having a second source/drain gate edge at said top surface of said substrate directly under a second lateral surface of said gate, so that said first source/drain gate edge and said second source/drain gate edge are on opposite sides of said gate; forming an implant mask over said substrate so as to expose at least a portion of said gate and expose a portion of said substrate adjacent to said gate, so that said implant mask is separated from said first source/drain gate edge, and is separated from said second source/drain gate edge, by substantially equal lateral spaces; and forming drain extensions in said substrate adjacent to, and partially underlapping, said gate at said first source/drain gate edge and said second source/drain gate edge by implanting dopants in four sub-implants, wherein: