Patent ID: 7027352
Filing Date: 2006-04-11
Classification: H03L

Abstract:
1. A delay locked loop (DLL) block to generate a delay locked clock signal by delaying an external clock signal in a semiconductor device, comprising: a clock buffer to receive the external clock signal and an inverted signal of the external clock signal to generate a plurality of internal clock signals; a clock divider to receive one of the internal clock signals and a control signal based on a column address strobe (CAS) signal to generate a plurality of divided signals, each having a predetermined pulse width adjusted by the control signal, and output a selected divided signal as the divided signal; and a DLL circuit to receive the plurality of internal clock signals and the divided signal to generate the delay locked clock signal, wherein the clock divider includes: a first divider to receive the one of the internal clock signals to generate a first divided signal having a first pulse width and a first period; a second divider to receive the first divided signal to generate a second divided signal having the first pulse width and a second period and a third divided signal having a second pulse width and the second period; a selector to selectively output the second divided signal and the third divided signal according to the control signal; and a third clock divider to receive an output of the selector to generate the divided signal.