Patent ID: 7043670
Filing Date: 2006-05-09
Classification: H03K

Abstract:
1. An apparatus comprising: a circuit configured to (i) monitor a plurality of signals for transitions and (ii) invert said signals only when at least a predetermined number of said signals transition to a particular logic state; and a plurality of buffers configured to present said signals on a transmission bus, wherein said circuit comprises (i) a transition checker circuit directly receiving said signals and configured to present a plurality of transition signals each indicating a transition direction of one of said signals, (ii) a control circuit configured to present a flag signal when at least said predetermined number of said transition signals indicate said transition direction is to said particular logic state and (iii) an inverter circuit configured to invert said signals in response to said flag signal, wherein said transition checker circuit comprises (i) a plurality of flip-flops directly receiving said signals and configured to present said signals as a plurality of sampled signals, (ii) a plurality of inverters configured to present said signals as a plurality of inverted signals, and (iii) a plurality of logic gates configured to present said transition signals in response to said sampled signals and said inverted signals.