Patent ID: 7523424
Filing Date: 2009-04-21
Classification: G06F

Abstract:
1. A method for representing analog connectivity in a design written in a hardware description language, comprising: detecting a circuit component that does not have explicit connection path in the design, wherein the circuit component includes a Verilog-AMS out-of-module-reference, a Verilog-AMS defined parameter, and a VHDL-AMS package reference, and wherein the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph, representations of a lower-level circuit instance vary from one branch to another branch due to out-of-module-reference, automatic inserted connection module, Verilog-AMS defined parameter, VHDL-AMS package reference, VHDL-AMS entity, VHDL-AMS architecture, and VHDL-AMS instance; creating one or more instances of the circuit component having at least one additional port than the circuit component; creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path; and simulating the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances.