Patent ID: 6094073
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A predecoding circuit of a memory-line decoder for an electrically programmable memory device, the predecoding circuit comprising:a logic circuit operable to receive an address signal, to generate a first signal having a first voltage level in response to a predetermined address, and to generate the first signal having a second voltage level in response to other addresses;a first circuit coupled to the logic circuit and operable during a first operational mode to generate a predecode signal having the same voltage level as the first signal; anda second circuit coupled to the logic circuit and operable during a second operational mode to generate the predecode signal having a third voltage level when the first signal has the first voltage level and to generate the predecode signal having the second voltage level when the first signal has the second voltage level, the third voltage level being higher than the first voltage level.