Patent ID: 6383864
Filing Date: 2002-05-07
Classification: H01L

Abstract:
In a process for making a memory cell the improvement comprising the steps of:I) forming a trench in a silicon chip of one conductivity type; II) forming a dielectric layer over walls of the trench; III) filling the trench with polysilicon of a conductivity type opposite that of the chip; IV) growing an epitaxial silicon layer over the surface of the chip of sufficient thickness for forming over the top of the trench a layer of essentially monocrystalline silicon of a conductivity that is opposite that of a chip for serving as a first source/drain; V) patterning the eptaxial silicon layer to form a mesa over the trench; VI) forming a first dielectric layer over the surface of the chip, covering the epitaxial silicon mesa; VII) forming spacers on the side of the mesa, the mesa comprising a material in which the first dielectric layer can be removed selectively to the spacers; VIII) removing the first dielectric layer from the surface of the chip and top of the epitaxial silicon mesa, wherein the spacers protect the first dielectric layer from being removed from the sides of the mesa; IX) forming a second dielectric layer over the surface of the chip; X) removing the sidewall spacers, leaving the first dielectric layer on the side of the mesa, the first dielectric layer on the sides of the mesa serving as gate oxide; XI) forming a first polysilicon layer of the conductivity type opposite that of the chip over the surface of the second dielectric layer; XII) forming a third dielectric layer over the surface of said polysilicon layer; XIII) planarizing the third dielectric layer to expose the surface of the epitaxial silicon mesa; and XIV) forming and patterning a second polysilicon layer of the conductivity opposite that of the chip to form a polysilicon mesa over the epitaxial silicon mesa.