Patent ID: 7893738
Filing Date: 2011-02-22
Classification: H03K,H03L

Abstract:
1. A DLL circuit comprising: a first clock signal dividing block configured to selectively divide a frequency of a delay clock signal according to whether a lock completion signal is enabled; a delay compensating block configured to generate a feedback clock signal by delaying a clock signal transmitted from the clock signal dividing block, for a predetermined time; and an operation mode setting block configured to generate the lock completion signal according to information of phases of a reference clock signal and the feedback clock signal, wherein the first clock signal dividing block is configured to transmit the delay clock signal to the delay compensating block when the lock completion signal is disabled, and when the lock completion signal is enabled, to generate a first divide clock signal by dividing the frequency of the delay clock signal according to a predetermined divide ratio and to transmit the first divide clock signal to the delay compensating block, and the delay compensating block is configured to generate the feedback clock signal by delaying the delay clock signal when the lock completion signal is disabled, and to generate the feedback clock signal by delaying the first divide clock signal when the lock completion signal is enabled.