Patent ID: 6074906
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A process of fabricating a CMOS semiconductor device having at least one NMOS region and at least one PMOS region, comprising:(a) forming at least one NMOS gate electrode over a substrate in the NMOS region and at least one PMOS gate electrode over the substrate in the PMOS region;(b) selectively implanting a first n-type dopant into an NMOS active region of the substrate adjacent the NMOS gate electrode to form a first n-doped region in the NMOS active region;(c) forming a first NMOS spacer on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of the PMOS gate electrode;(d) selectively implanting a second n-type dopant into the NMOS active region using the first NMOS spacer as a mask, the second n-type dopant implant forming, in the NMOS active region, a second n-doped region deeper than the first n-doped region and then heating the substrate at a first temperature;(e) after heating the substrate, selectively implanting a p-type dopant, using the first PMOS spacer as a mask, the into a PMOS active region of the substrate adjacent the PMOS gate electrode to form a first p-doped region in the PMOS active region;(f) forming a second NMOS spacer and a second PMOS spacer adjacent the first NMOS spacer and first PMOS spacer; and(g) selectively implanting a third n-type dopant, using the second NMOS spacer as a mask, into the NMOS active region to form a third n-doped region deeper than the second n-doped region in the NMOS active region; and(h) selectively implanting a second p-type dopant, using the second PMOS spacer as a mask, into the PMOS active region to form a second p-doped region deeper than the first p-doped region in the PMOS active region and then heating the substrate at a second temperature after implanting the third n-type dopant and the first and second p-type dopants, wherein the second temperature is lower than the first temperature.