Patent ID: 7288949
Filing Date: 2007-10-30
Classification: G01R

Abstract:
1. A semiconductor test interface for interfacing a DUT (Device Under Test) to a pin card using one or more cables, the test interface comprising: a DUT board including one or more first connectors for electrically connecting one or more test sockets for mounting the DUT to the one or more cables, and a circuit wiring for electrically connecting the one or more test sockets to the one or more first connectors; and the one or more cables including a second connector for an electrical connection to the one or more first connectors, and a third connector for an electrical connection to the pin card, wherein the one or more first connectors correspond to the one or more cables by 1:1, wherein the pin card comprises one or more fourth connectors corresponding to the third connector by 1:1, the one or more fourth connectors corresponding to the one or more first connectors through the one or more cables by 1:1, and wherein each of the one or more fourth connectors comprises two or more fifth connectors for connecting a plurality of the third connectors thereto, the one or more fourth connectors corresponding to the one or more first connectors through the one or more cables by 1:(2 or more).