Patent ID: 7400200
Filing Date: 2008-07-15
Classification: H03F,H03G

Abstract:
1. A distributed amplifier, comprising: an input impedance matching circuit configured to receive an input signal; a plurality of amplification stages, each stage being operably connected to said input impedance matching circuit; and an output impedance matching circuit operably connected to each amplification stage of said plurality of amplification stages; and wherein at least one of said plurality of amplification stages comprises: an amplification FET having a gate, a source, and a drain, the gate being operably connected to said input impedance matching circuit; a feedback FET having a gate, a source, and a drain, the gate being configured to receive a control signal, the drain being operably connected to the drain of said amplification FET, and the source being operably connected to the gate of said amplification FET, and a common gate FET having a gate, a source, and a drain, the gate of the common gate FET being operably connected to ground, the source of the common gate FET being operably connected to the drain of the amplification FET, and the drain of the common gate FET being operably connected to the output impedance matching circuit.