Patent ID: 7985656
Filing Date: 2011-07-26
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit, the method comprising: etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage transistor regions of the substrate, wherein the first trench has an opening at the top surface of the substrate; oxidizing the substrate to form a silicon dioxide layer lining the first and second trenches, the layer having a first thickness; depositing a silicon nitride layer on the silicon dioxide layer in the first and second trenches; etching the silicon nitride layer from the first trench but not from the second trench, thereby exposing the silicon layer in the first trench but not the second trench; oxidizing the exposed silicon dioxide layer in the first trench sufficiently to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second trench and to round corners of the exposed silicon dioxide layer at the opening of the first trench; filling the first and second trenches with a dielectric material; etching the substrate to create a third trench between a high voltage transistor region and a low voltage transistor region of the substrate; oxidizing the substrate to form a silicon dioxide layer lining the third trench; depositing a silicon nitride layer on the silicon dioxide layer in the third trench; etching the silicon nitride layer from a first portion of the third trench adjacent to the high voltage transistor region but not from a second portion of the third trench adjacent to the low voltage transistor region, thereby exposing the silicon dioxide layer in the first portion but not in the second portion of the third trench; oxidizing the exposed silicon dioxide layer in the first portion of the third trench to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second portion of the third trench; and filling the third trench with the dielectric material.