Patent ID: 6407946
Filing Date: 2002-06-18
Classification: G11C

Abstract:
An electrically erasable and programmable nonvolatile semiconductor memory device comprising:a memory cell transistor including a control gate, a floating gate, a drain and a source and being either in OFF state, in which charge is stored on the floating gate, or in ON state, in which charge has been removed from the floating gate; a reference transistor with a MOS structure; a gate voltage generator for generating a gate voltage for the reference transistor in a read cycle; a bit line connected to the drain of the memory cell transistor; a reference line connected to the drain of the reference transistor; and a differential sense amplifier that compares a bit line voltage with a reference line voltage so as to sense the state of the memory cell transistor, the bit line voltage being determined by a drain current of the memory cell transistor, the reference line voltage being determined by a drain current of the reference transistor, wherein the gate voltage generator comprises: a dummy cell transistor including a control gate, a floating gate, a drain and a source as the memory cell transistor does; a current mirror for creating a current proportional to a drain current of the dummy cell transistor; and transistor means for generating a gate voltage for the reference transistor in accordance with a current created by the current mirror; and wherein the reference transistor comprises a control gate, a floating gate, a drain and a source as the memory cell transistor does, the control and floating gates of the reference transistor being shortcircuited with each other.