Patent ID: 7034596
Filing Date: 2006-04-25
Classification: H03K,H03L,H04L

Abstract:
1. A circuit comprising: a delay circuit adapted to receive a first signal and apply a selectable delay to the first signal to provide a delayed first signal comprising a plurality of delayed versions of the first signal each simultaneously available from the delay circuit with a different delay and having a timing relationship relative to a clock signal; a first register, coupled to the delay circuit, adapted to receive the delayed first signal and the clock signal and store the delayed first signal based upon a timing of the clock signal; a first multiplexer coupled to the first register; a second register, coupled to the delay circuit, adapted to receive the delayed first signal and the clock signal and store the delayed first signal based upon a timing of the clock signal; a second multiplexer coupled to the second register; and a control circuit, coupled to the delay circuit, the first and second registers, and the first and second multiplexers, adapted to monitor the clock signal and the plurality of delayed versions of the first signal and determine the selectable delay to apply by the delay circuit and which of the plurality of delayed versions of the first signal, each having a different amount of delay, to select by the first multiplexer from the first register and provide as a first output signal and to select by the second multiplexer from the second register and provide as a second output signal.