Patent ID: 8972688
Filing Date: 2015-03-03
Classification: G06F,G11C

Abstract:
1. An integrated circuit, comprising: a controller configured to output controller output signals to access one of a plurality of memory chips, the plurality of memory chips being configured to operate with different operation specifications; a memory controller configured to convert the controller output signals into memory input signals according to the operation specification of the one of the plurality of memory chips; a first terminal configured to be connected to the plurality of memory chips via a first common bus, a first subset of the memory input signals being supplied from the first terminal to the one of the plurality of memory chips via the first common bus, the first subset including a write enable signal; a second terminal configured to be connected to the plurality of memory chips via a second common bus, a second subset of the memory input signals being supplied from the second terminal to the one of the plurality of memory chips via the second common bus, the second subset including a write data signal; and a third terminal configured to be connected only to the one of the plurality of memory chips via a dedicated line, a third subset of the memory input signals being supplied from the third terminal to the one of the plurality of memory chips via the dedicated line, the third subset including a chip enable signal, wherein the memory chips include a static random access memory and a flash memory, and the memory controller includes a conversion control unit configured to determine, in accordance with the different operation specifications, whether to output the memory input signal to the one of the plurality of memory chips or temporarily keep the memory input signal in a period during which another one of the plurality of memory chips is accessed.