Patent ID: 6836875
Filing Date: 2004-12-28
Classification: G06F

Abstract:
A method for designing an integrated circuit having interconnect lines interconnecting at least two functional blocks on a semiconductor die, the method comprising:operating a processing device to create a logic design to be incorporated onto said die, the logic design including a plurality of levels of logical hierarchy, a first level of said logical hierarchy being made up of at least first and second functional blocks, wherein a logical representation of at least a first interconnect couples said first and second functional blocks; operating said processing device to create a new level of logical hierarchy, said new level of logical hierarchy being subordinate to said first level; and operating said processing device to automatically insert a logical representation of at least one repeater cell between an output port of said new level and an output port of said first functional block, such that said output port of said first functional block is coupled to both said logical representation of said at least one repeater cell and said logical representation of said first interconnect.