Patent ID: 8525314
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. An in-process unit including upper and lower dielectric substrates and a plurality of microelectronic elements disposed between said upper and lower dielectric substrates, each said microelectronic element comprising a semiconductor chip, each of said upper and lower dielectric substrates including a plurality of regions, each region of said upper dielectric substrate being aligned with a corresponding region of the lower dielectric substrate with at least one said microelectronic element disposed therebetween, each of said regions of said upper and lower dielectric substrates having electrically conductive elements thereon, said in-process unit further including wire bonds having first ends joined to at least some of said conductive elements of each said region of said upper dielectric substrate and second ends joined to the electrically conductive elements of the corresponding region of said lower dielectric substrate, said wire bonds electrically connecting said regions of said upper substrate with said corresponding regions of said lower substrates such that each said wire bond has a first end joined to one said conductive element of one said region of said upper dielectric substrate and has a second end joined to one said conductive element of one said region of said lower dielectric substrate.