Patent ID: 7705665
Filing Date: 2010-04-27
Classification: H03H

Abstract:
1. A digital tuning circuit of a G m -C filter, comprising: a switched capacitor configured to operate in a capacitance tuning mode to charge/discharge a predetermined first reference voltage according to a clock signal, and output a first current incorporating process variations of a capacitance; a G a load resistor configured to convert the first current output from the switched capacitor to a first voltage in the capacitance tuning mode, and convert a second current output from the G a D/A converter configured to vary a predetermined second reference voltage according to a DAC tuning coefficient, and convert the varied second reference voltage to a third voltage which is an analog voltage; an error detector configured to control capacitance tuning using a first difference voltage between the first voltage and the third voltage in the capacitance tuning mode, and control the G a DAC tuner configured to output to the D/A converter the DAC tuning coefficient corresponding to the first difference voltage according to the capacitance tuning control of the error detector in the capacitance tuning mode.