Patent ID: 6621156
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A semiconductor device, comprising:a substrate having a first surface with a periphery that has a wiring pattern thereon; a first semiconductor device attached to said first surface inside said periphery; a second semiconductor device mounted on said first surface; a spacer on said first surface between said first semiconductor device and said periphery, said spacer extending from said first surface to a height greater than a height of said first semiconductor device and being attached to said second semiconductor device, said spacer holding said second semiconductor device spaced from said first semiconductor device and so that said first semiconductor device is sandwiched between said second semiconductor device and said first surface; first conductors that electrically connect said first semiconductor device to said wiring pattern on said periphery; and second conductors that electrically connect said second semiconductor device to said wiring pattern on said periphery.