Patent ID: 6230178
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A modular arithmetic coprocessor comprising:circuit for computation of an error correction parameter H=2.sup.x mod N associated with the Montgomery method, with x and N being non-zero integers, the circuit comprisinga first shift register for holding intermediate values of H,a second shift register for holding values of N,first means connected to an output of said first shift register for providing a result for a series subtraction of either zero, N, twice N, or three times N from the intermediate values of H held in said first shift register,a multiplication circuit connected to an output of said first means for multiplying by four the result provided by said first means,second means connected to an output of said multiplication circuit for determining whether a result provided by said multiplication circuit is greater or smaller than N, twice N or three times N, andthird means connected to an output of said second shift register for providing values of twice N and three times N.