Patent ID: 7076613
Filing Date: 2006-07-11
Classification: G06F

Abstract:
1. A processor comprising: a bus interface to provide communication with other processors; a local cache; a cache invalidation history table associated with the local cache; and a cache controller associated with the local cache, the cache controller to track invalidated cache lines by recording the line addresses of invalidated cache lines and an indicator indicating whether each of the invalidated cache lines recorded was invalidated via a clean-invalidate or a dirty-invalidate in the invalidation history table, the cache controller further to revalidate only those invalidated cache lines recorded in the invalidation history table as having been clean-invalidate invalidated, wherein the revalidate includes monitoring the bus for cache line addresses of clean-invalidate invalidated cache lines recorded in the invalidation history table and for associated cache line data, and includes updating the invalidated cache line data with the cache line data associated with the recorded cache line addresses.