Patent ID: 7685438
Filing Date: 2010-03-23
Classification: G06F,G11C,H01L,Y10S

Abstract:
1. An integrated circuit chip arrangement comprising: an integrated circuit chip having circuitry therein including a plurality of magnetically-responsive nodes configured to store bits; a package having magnetic material and covering at least a portion of circuitry in the integrated circuit chip; and a cryptographic circuit configured to store selected bits of the plurality of magnetically-responsive nodes in an enable register, the value of the bits being responsive to the magnetic material in the package, wherein the integrated circuit chip is configured to encrypt data as a function of cryptographic key data in the enable register, to mask an output read from the magnetically-responsive nodes using data stored in the enable register and to store the masked output in an output register wherein the package and the plurality of magnetically-responsive nodes are arranged such that removing a portion of the package alters at least one bit of the plurality of magnetically-responsive nodes having a bit stored in the enable register, wherein in response to the at least one bit of the plurality of magnetically-responsive nodes being altered, the data stored in the output register is different than the data stored in the enable register.