Patent ID: 7560998
Filing Date: 2009-07-14
Classification: H03K

Abstract:
1. A circuit for outputting a clock signal with a predetermined frequency regardless of voltage variation and temperature variation, comprising: a first terminal to be connected to an electrode of a direct power source; a second terminal to be connected to another electrode of the direct power source; a third terminal for outputting the clock signal; a parallel circuit comprising 1 wherein each pair of transistors comprises an upper transistor and a lower transistor connected in series between the first terminal and the second terminal, the number “n” of the pair of transistors is odd, a point between the upper transistor and the lower transistor of each pair of transistors is connected to a gate of the lower transistor of the pair of transistors subsequent to the preceding pair of transistors, and a point between the upper transistor and the lower transistor of one of the pairs of transistors is connected to the third terminal, wherein each pair of transistors having a number lower than n precedes the pair of transistors subsequent to the pair of transistors having the number lower than n and having a higher number than the pair of transistors having the number lower than n, and the n a capacitor is inserted between the gate of the lower transistor of each pair of transistors and the second terminal, the upper transistors have the same specification, the lower transistors have the same specification, and the capacitors have the same specification, and a current regulating circuit is connected to the gates of the upper transistors of the pairs of transistors, wherein the current regulator supplies a gate voltage to each gate of each upper transistor of the pairs of transistors, the magnitude of the gate voltage being adjusted to cause a magnitude of current to flow between the source and drain of an upper transistor from amongst the upper transistors of the pairs of transistors, and the magnitude of the current between the source and drain of the upper transistor being proportional to a voltage between the source and gate of the lower transistor from the pair of transistors including the upper transistor when the lower transistor is turned on, the current regulating circuit comprising: a threshold voltage generation circuit, circuit that comprises an additional pair of transistors, wherein the additional pair of transistors has an upper transistor and a lower transistor connected in series between the first terminal and the second terminal, the drain and the gate of the lower transistor of the additional pair of transistors are connected, and the threshold voltage generation circuit outputs a magnitude of a voltage proportional to the voltage between the gate and source of the lower transistor when the lower transistor is turned on; and a bias voltage generation circuit, that comprises a series circuit and an operational amplifier, wherein the series circuit is connected between the first terminal and the second terminal, and comprises an upper transistor and a resistance, a point between the upper transistor and the resistance of the series circuit is connected to a non-inverted input terminal of the operational amplifier, and the output terminal of the operational amplifier is connected to the gates of all the upper transistors of the series circuit and the pairs of transistors, and a voltage conversion circuit, wherein the voltage conversion circuit divides a magnitude of a voltage of a point between the upper transistor and the lower transistor of the additional pair of transistors to one-m wherein an output terminal of the threshold voltage generation circuit is connected to an input terminal of the bias voltage generation circuit, and the bias voltage generation circuit outputs the magnitude of the gate voltage for causing the current to pass through the upper transistor where the current is proportional to the voltage between the source and gate of the lower transistor when the lower transistor is turned on.