Patent ID: 8045662
Filing Date: 2011-10-25
Classification: H03K

Abstract:
1. An apparatus for sampling the stages of a binary ripple counter, comprising: a plurality of sampling stages having respective data inputs for receiving data from respectively corresponding stages of the binary ripple counter, said sampling stages having respective sample control inputs that receive respective sample control signals, said sampling stages responsive to the respective sample control signals for sampling the data at said data inputs thereof; and a sampling controller coupled to said sample control inputs for providing said sample control signals, said sampling controller configured to produce respective ones of said sample control signals by delaying a sample signal by respectively corresponding amounts of time, said sampling controller having a delay control input for receiving a delay control signal, and said sampling controller further configured to adjust said amounts of time based on said delay control signal; wherein said sampling controller includes a plurality of adjustable delay elements arranged in a series configuration that is coupled to receive said sample signal, wherein said delay control signal has a plurality of constituent delay control signal components, and wherein said adjustable delay elements are respectively coupled to receive said delay control signal components from said delay control input; wherein each of said delay control signal components is a bit from a respectively corresponding one of the stages of the binary ripple counter; wherein each of said adjustable delay elements is configured to impose a first amount of delay if the corresponding delay control signal component is 0, and a second amount of delay if the corresponding delay control signal component is 1, and wherein said first and second amounts of delay differ from one another.