Patent ID: 8539390
Filing Date: 2013-09-17
Classification: G03F,G06F,G16Z,G21K

Abstract:
1. A method comprising: selecting, by a processor of a computing device, a plurality of target edge pairs from mask layout data of a lithographic mask, for determining a manufacturing penalty in making the lithographic mask, the lithographic mask employed in fabricating instances of a semiconductor device, the mask layout data comprising a plurality of polygons, each polygon having a plurality of edges, each target edge pair defined by two of the edges of one or more of the polygons; determining, by the processor of the computing device, a manufacturability of the lithographic mask, including determining the manufacturing penalty in making the lithographic mask, where determining the manufacturing penalty is based on the target edge pairs as selected; outputting, by the processor of the computing device, the manufacturability of the lithographic mask, where the manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask; and, performing, by the processor of the computing device, an optimization process in relation to the lithographic mask, comprising iteratively performing one or more times: wherein determining the manufacturability of the lithographic mask, including determining the manufacturing penalty in making the lithographic mask, comprises: wherein the manufacturability of the lithographic mask is determined based on edge information regarding a plurality of edges including the first edge and the second edge, the edge information regarding other edges connected to pairs of the plurality of edges, wherein the manufacturability of the lithographic mask is determined for a plurality of jogs that have a size smaller than a predetermined scale of smoothness, by considering one or more scale assessment factor functions and by removing edges of the jogs that are shorter than a predetermined size.