Patent ID: 6163052
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A vertical combination MOSFET and JFET device, comprising:a substrate;a semiconductor layer formed on said substrate to be of a first conductivity type and having a surface;a buried gate region formed in said semiconductor layer to be spaced from said surface of said semiconductor layer and to be of a second conductivity type opposite said first conductivity type, said buried gate region having a boundary, a channel region of said device at least partly disposed adjacent to said boundary of said buried gate region;a drain region formed adjacent said surface of said semiconductor layer to be spaced from said buried gate region by said channel region and to be of said second conductivity type;a trench formed to extend downwardly from said surface of said semiconductor layer and having sidewalls, a bottom of said trench spaced above said boundary of said buried gate region;a gate insulator formed to adjoin said sidewalls and said bottom of said trench;a conductive top gate formed in said trench;a source region formed at said surface of said semiconductor layer to be insulatively spaced from said drain region, said channel region extending from said source region to said drain region and disposed adjacent at least one of said sidewalls and adjacent said bottom of said trench, said channel region interposed between said drain region and said buried gate region, said channel region further interposed between said source region and said buried gate region; andmeans for impressing a buried gate voltage on said buried gate region.