Patent ID: 6414890
Filing Date: 2002-07-02
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a boost signal generator for generating a boost signal; a drive signal generator for generating, in accordance with said boost signal, a drive signal changing complementarily to said boost signal, said drive signal generator including a gate circuit for driving said drive signal to a low level in response to a wafer burn-in signal designating a burn-in mode at a wafer level; a plurality of word lines each connecting a plurality of memory cells; and a plurality of word drivers coupled to said plurality of word lines for driving corresponding word lines to a selected state in accordance with at least said boost signal, each of said plurality of word drivers including a first drive transistor for transmitting said boost signal to a corresponding word line, and a second drive transistor for coupling said corresponding word line to a reference potential source node in response to said drive signal.