Patent ID: 6993691
Filing Date: 2006-01-31
Classification: G11C

Abstract:
1. A test method for a ferroelectric memory including a circuit of a plurality of series-connected memory cells which is connected at one end to a plate line, each of said plurality of series-connected memory cells including a first MIS transistor which has a gate electrode connected to a corresponding one of plural word lines, a source terminal and a drain terminal and a ferroelectric capacitor connected between said source terminal and said drain terminal, and a second MIS transistor having a current path which is connected at one end to the other end of said circuit of said plurality of series-connected memory cells and connected at the other end to a bit line, said test method comprising: lowering a potential of a word line connected to any selected one of said memory cells and raising a potential of word lines connected to non-selected memory cells; raising a potential of said plate line from a first potential to a second potential and then lowering said potential of said plate line from said second potential to said first potential; raising a potential of said bit line from a third potential to a fourth potential and then lowering said potential of said bit line from said fourth potential to said third potential; and reading data from said memory cells after said potentials of said plate line and said bit line have been raised and lowered at least one time, to determine attenuation of polarization in said ferroelectric capacitor, wherein said bit line remain at said third potential while said plate line is maintained at said second potential, and said plate line is maintained at said first potential while said bit line remains at said fourth potential.