Patent ID: 6456547
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of memory cells and pairs of bit lines, the plurality of memory cells being connected with a pair of bit lines, the semiconductor memory device comprising:a pre-charging part for pre-charging one pair of the pairs of bit lines in response to a first state control signal output at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating the first state control signal in response to a pre-charge relating signal and generating a second state control signal, the second state control signal being generated when a stand-by current failure occurs due to a detect in the one pair of bit lines, wherein the second state control signal is independent of the pre-charge relating signal and when activated, causes a circuit in the pre-charging part to cut-off supply voltage from being applied to the one pair of bit lines; and a bit line floating prevent part for compensating potential values of the one pair of bit lines having the defect so that each bit line of the one pair has a fixed potential value, wherein a memory cell connected to the one pair of bit lines is disconnected to a cell supply voltage in response to the fixed potential values of the bit lines, thereby preventing the cell supply voltage from being applied to the one pair of bit lines during a memory access mode of the semiconductor memory device.