Patent ID: 8471591
Filing Date: 2013-06-25
Classification: H01L,H03K,H04L

Abstract:
1. A termination circuit for a terminal of a semiconductor device, the terminal associated with an expected voltage swing, the termination circuit comprising: a plurality of NMOS transistors directly connected to the terminal and connected to a power supply at a supply voltage; a plurality of PMOS transistors directly connected to the terminal and connected to the power supply; and control circuitry for controllably enabling and disabling on-die termination, wherein when on-die termination is enabled, the control circuitry is configured to drive at least one of the NMOS transistors with a corresponding NMOS gate voltage that is greater than the supply voltage and greater than the maximum voltage of the expected voltage swing, and is further configured to drive at least one of the PMOS transistors with a corresponding PMOS gate voltage that is less than the supply voltage and less than the minimum voltage of the expected voltage swing.