Patent ID: 8423876
Filing Date: 2013-04-16
Classification: H03M

Abstract:
1. A Low-Density Parity-Check Convolutional Code (LDDC-CC) encoder comprising: a plurality of shift registers; a plurality of weight multipliers that multiply outputs of the shift registers by a weight; an exclusive OR computing circuit that finds an exclusive OR of outputs of the plurality of weight multipliers; a bit counter that counts a number of input bits that are encoded; and a weight controller that controls weights of the plurality of weight multipliers according to the number of bits, wherein: the plurality of shift registers includes a shift register for information sequence and a shift register for parity; the shift register for parity inputs an output from the exclusive OR computing circuit; and the weight controller stores a first weight pattern conforming to a parity check matrix of a LDPC-CC and a second weight pattern conforming to a deformed parity check matrix obtained by deforming the parity check matrix of the LDPC-CC, and uses the first weight pattern when an information sequence of the input bits is input into an earliest shift register of the shift register for information sequence, and uses the second weight pattern when a predetermined input termination sequence for creating an encoded termination sequence is input into an earliest shift register of the shift register for information sequence.