Patent ID: 6044474
Filing Date: 2000-03-28
Classification: G06F

Abstract:
A computer system including an apparatus for reducing clock-to-signal skew comprising:a) a clock generating a clock signal;b) a bus master operatively coupled to receive the clock signal and to generate an address signal;c) a memory controller operatively coupled to the clock and the bus master to receive the clock signal and the address signal, and configurable to be operated in at least one of a high-performance mode and a normal mode wherein:i) in the high-performance mode, the memory controller generates at least one high-performance memory control signal, andii) in the normal mode, the memory controller generates at least one normal memory control signal at least one clock cycle later than a corresponding high-performance memory control signal would have been generated;d) a register operatively coupled to receive the clock signal and a high-performance memory control signal and configured to generate a buffered memory control signal; ande) a memory array having an I/O line and stored data, the memory array operatively coupled to receive the buffered memory control signal and to route a portion of the data when it is sampled by the clock signal.