Patent ID: 7263478
Filing Date: 2007-08-28
Classification: G06F

Abstract:
1. A system for verifying a circuit represented with a circuit description including a plurality of descriptions, the system comprising: a simulator configured to carry out a logic simulation of the circuit description with the use of a test bench for the circuit description; an extractor configured to extract descriptions unexecuted in the logic simulation according to code coverage information for the circuit description; an examiner configured to examine whether or not there is a possibility of executing the extracted unexecuted descriptions; and a prohibited-input-checker generator configured to generate a test pattern to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing, wherein the simulator carries out a second logic simulation using the test pattern generated by the prohibited-input-checker generator, wherein the prohibited-input-checker generator determines that the test pattern is prohibited by specifications of the circuit if a result of the second logic simulation using the test pattern does not satisfy the specifications and if there are no bugs in the circuit description, and generates a prohibited-input checker that checks whether or not an input pattern of a subsequent logic simulation is equal to the test pattern determined to be prohibited by the specifications; wherein the simulator informs a user if the input pattern of the subsequent logic simulation and the test pattern are the same.