Patent ID: 6223322
Filing Date: 2001-04-24
Classification: G11B

Abstract:
A machine-implementable method for enhancing the data transfer rate in an arrangement formed by an ECC processor coupling a first memory, said arrangement detecting and correcting errors and erasures responsive to a source of error correction-coded (ECC) product data arrays, each product-coded array having a first predetermined number of rows of Y bytes per row and a second predetermined number of columns, said arrangement writing each data array into a first memory, transferring data from the array in the first memory to the ECC processor, transferring corrected data from the ECC processor, and writing said transferred corrected data back into the first memory, comprising the steps of:(a) transferring each row of the data array from the source in row major order in blocks of 2.sup.N bytes per block and (2 m+1) blocks per row, and writing consecutive blocks (1.sup.st row--A.sub.0, B.sub.0, A.sub.1 ; 2.sup.nd row--B.sub.1, A.sub.2, B.sub.2, . . . ) into successive alternate addresses (A.sub.0, A.sub.1, A.sub.2 ; B.sub.0, B.sub.1, B.sub.2) in a pair of independently accessible linear address spaces in the first memory operated in an interleaved manner, N and m being positive integers satisfying the constraint Y.ltoreq.2.sup.N.times.(2 m+1); and(b) extracting data, ECC correcting the extracted data, and rewriting corrected data to and from successive addresses in the linear address spaces in the first memory in block interleave array row major order and then in block interleave array column major order.