Patent ID: 6571325
Filing Date: 2003-05-27
Classification: G06F

Abstract:
In a memory system comprising:a pipelined memory controller receiving a memory access request, each memory access request including a memory address; a memory device; and, a memory bus connecting the memory controller and the memory device; wherein the memory controller further comprises: a first pipeline stage, comprising, an address extractor receiving the memory address in the memory access request and decoding from the memory address a memory bank address for a target memory bank in the memory device; a bank state cache lookup receiving the memory bank address and generating in response thereto a memory bank state for the target memory bank, a hazard detector receiving the memory access request and the memory bank state for the target memory bank, detecting hazard conditions for the memory access request, and in response to the detected hazard conditions, outputting stall commands; and a second pipeline stage, comprising, a command sequencer receiving the memory access request and the stall commands and in response thereto generating sequenced control commands for accessing the memory device, a timing coordinator receiving the sequenced control commands from the command sequencer, timing the sequenced control commands to satisfy memory system timing requirements, and generating timed and sequenced control commands, and a physical layer manager receiving the timed and sequenced control commands from the timing coordinator and communicating the timed and sequenced control commands via the memory bus to the memory device.