Patent ID: 6191459
Filing Date: 2001-02-20
Classification: H01L

Abstract:
An electrically programmable memory cell array, comprising:a semiconductor substrate having a main face, and a cell field with a plurality of memory cells disposed on said main face of said semiconductor substrate, said semiconductor substrate being doped, at least in a region of said cell field, with a first conductivity type, said cell field having a plurality of substantially parallel strip-shaped insulation trenches formed therein, said insulation trenches each having a bottom, said cell field having a length extending entirely across said cell field;strip-shaped doped zones disposed between adjacent said insulation trenches on said main face, and on said bottom of said insulation trenches, said doped zones disposed on said bottom of said insulation trenches being disposed within said insulation trenches, said doped zones being doped with a second conductivity type, opposite said first conductivity type, and extending substantially parallel to said insulation trenches, said doped zones extending entirely across said length of said cell field;said insulation trenches being filled with insulating material forming a planar surface on said main face of said semiconductor substrate;each of said memory cells being disposed on mutually opposite edges of said insulation trenches;said memory cells including at least one MOS transistor having a gate electrode disposed vertically relative to said main face, said MOS transistor having a gate dielectric formed of a material with charge carrier traps;word lines extending transversely to said insulation trenches, each of said word lines connected to said gate electrode of a respective said vertical MOS transistor disposed below a respective said word line;each of said memory cells formed with a hole extending from one edge of one of said insulation trenches inward into said insulation trench, whose surface being provided with said gate dielectric, said hole being filled with said gate electrode such that said strip-shaped doped zones adjoining the edge form source/drain zones of said vertical MOS transistor; andsaid doped zones disposed on said main face and on said bottom of said insulation trenches connecting respective source/drain zones of said vertical transistors disposed adjacent to one another along an edge of a respective one of said insulation trenches.