Patent ID: 6221703
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method of ion implantation for adjusting the threshold voltage and reducing the interface capacitance and interface leakage around S/D region obviously of a metal-oxide semiconductor (MOS) transistor, the MOS transistor being employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprising a substrate, a gate insulating layer positioned on the substrate, and a gate conducting layer with a rectangular-shaped cross section positioned on the gate insulating layer, the method comprising:performing an ion implantation process at a predetermined dosage and ion energy to implant dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the surface portion of the substrate below the gate insulating layer;wherein the ion implantation process will not affect the impurity concentration of the source and drain, and the saturated drain current (I.sub.dsant) of the MOS transistor is not reduced so as to reduce the interface capacitance and interface leakage around S/D region.