Patent ID: 7136443
Filing Date: 2006-11-14
Classification: H04L

Abstract:
1. A sample selection and data alignment circuit for selecting a selected over sampled signal among a plurality of over sampled signals (S 0 , . . . , S n−1 ) obtained by over sampling an incoming serial data stream of bits at n clock phase signals (C 0 , . . . , C n−1 ) of a multiphase clock signal, according to a corresponding select signal, and synchronously aligning said selected over sampled signal relative to a predefined phase of said multiphase clock signal to produce a recovered data, the circuit comprising: n logic blocks, connected serially, each block comprising: an output latch coupled to said last logic block, said output latch having an output latch data input, an output latch clock input and an output latch data out, wherein said first logic block 0 includes a level sensitive latch 0 receiving over sampled signal S wherein said last logic block n−1 includes a multiplexer n−1 and a level sensitive latch n−1 that are serially connected, said multiplexer n−1 having a first and second multiplexer input n−1 and a multiplexer output n−1, said level sensitive latch n−1 having a latch data input n−1, a latch clock input n−1 and a latch output n−1, wherein the first multiplexer input n−1 is connected to the level sensitive output n−2 of the level sensitive latch of the preceding logic block and the second multiplexer input n−1 receives sampled signal S wherein each of said intermediate logic blocks having label i, includes a multiplexer i and a level sensitive latch i that are serially connected, said multiplexer i having a first and second multiplexer input i, and said level sensitive latch i having a latch data input i, a latch clock input i and a latch output i, wherein the first multiplexer input i is connected to the level sensitive latch output i−1 of the level sensitive latch of the preceding logic block i−1 and wherein the second multiplexer input i receives over sampled signals S