Patent ID: 6529409
Filing Date: 2003-03-04
Classification: G11C

Abstract:
An integrated memory circuit comprising:a first array having a first amount of non-volatile memory cells; a second array having a second amount of non-volatile memory cells; a third array having a third amount of non-volatile memory cells; and a fourth array having a fourth amount of non-volatile memory cells; wherein said third amount is different from said first amount, and said first, second, third and fourth arrays are cooperatively linked in a manner which allows a first bank of memory cells including at least one of said first, second, third and fourth arrays to be read, while a second bank of memory cells including the remaining of said first, second, third and fourth arrays is simultaneously programmed or erased, and wherein each of said first, second, third and fourth arrays is dynamically selectable for read and program or erase operations.