Patent ID: 7935610
Filing Date: 2011-05-03
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, comprising: providing a first integrated device region on a substrate; providing a second integrated device region on the substrate that is spaced apart from the first integrated device region, wherein at least one of the first integrated device region and the second integrated device region includes a plurality of device recesses; interposing an isolation region between the first integrated device region and the second integrated device region, wherein the isolation region includes an isolation recess that projects into the substrate to a first predetermined depth; forming a conformal dielectric layer that covers a floor portion and interior wall portions of the isolation recess; spacer etching the conformal dielectric layer to expose the floor portion of the isolation recess, wherein the conformal dielectric layer that covers the interior wall portions of the isolation recess is retained; and extending the isolation recess to a second predetermined depth.