Patent ID: 7194717
Filing Date: 2007-03-20
Classification: G06F,G11C

Abstract:
1. A layout method for a top module including instances of a base module in a memory matrix, said top module and said base module each including data pins and at least one control pin, data pins of said instances being replicated in said top module, a control signal being shared among said instances and said top module by tying together corresponding control pins of said instances and a corresponding control pin of said top module, comprising steps of: extending, at a library preparation stage, data pins and control pins of standard cells in said top module vertically for easy access; assigning positions for said data pins of said top module and said at least one control pin of said top module in said top module; arranging said instances within said top module; implementing signal routing for said instances and said top module; and performing power routing for said instances and said top module, wherein said assigning step comprises: