Patent ID: 6487671
Filing Date: 2002-11-26
Classification: G06F

Abstract:
A method for data read operations between an initiator device and a target device coupled to a bus carrying a clock signal, wherein the clock signal includes a plurality of clock cycles and wherein each clock cycle includes a first and second phase, wherein each of said initiator and target devices includes a three mode bus driver having three selectable output modes of operation: the first mode being a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance, the second mode being a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance, and a third mode having high output impedance, said method comprising the steps of:for the driver for the target device, selecting the third mode of operation during a first clock cycle; for the driver for the initiator device, selecting the first mode of operation during the first phase of the first clock cycle and driving a first address onto the bus; for the driver for the initiator device, selecting the second mode of operation during the second phase of the first clock cycle while driving the first address onto the bus; for the driver for the initiator device, selecting the third mode of operation during a second clock cycle; for the driver for the target device, selecting the first mode of operation during the first phase of the second clock cycle and driving first data onto the bus; and for the driver for the target device, selecting the second mode of operation during the second phase of the second clock cycle while driving the first data onto the bus.