Patent ID: 8832508
Filing Date: 2014-09-09
Classification: G11C

Abstract:
1. A memory element comprising: a first array of one or more memory cells coupled to a first bit line node; a second array of one or more memory cells coupled to a second bit line node; access circuitry for accessing a first memory cell in the first array, the access circuitry comprising write driver circuitry configured to provide a first voltage indicative of a write data bit value at a first node; a first transistor including a first terminal coupled to the first node and a second terminal coupled to the first bit line node; a second transistor including a third terminal coupled to the first node and a fourth terminal coupled to the second bit line node; and a controller coupled to a control terminal of the first transistor and a control terminal of the second transistor, wherein the controller is configured to concurrently activate the first transistor and the second transistor to enable the access circuitry to access the first memory cell by applying a first column select signal to the control terminal of the first transistor to activate the first transistor and concurrently applying a second column select signal to the control terminal of the second transistor to activate the second transistor, wherein concurrently activating the first transistor and the second transistor results in the first voltage at the first bit line node and the second bit line node.