Patent ID: 6246633
Filing Date: 2001-06-12
Classification: G11C

Abstract:
A semiconductor memory device performing an operation cycle to input/output a data signal in response to a command signal and an address signal received at signal input nodes, comprising:a memory cell array having a plurality of memory cells arranged in rows and columns;an address decode circuit responsive to said address signal for selecting at least one of said memory cells;a control circuit responsive to said command signal for activating an address buffer activation signal to start an operation for receiving said address signal; andan address buffer circuit provided between said signal input nodes and said address decode circuit, for performing transmission of said address signal from said signal input nodes to said address decode circuit when said address buffer activation signal is in an active state to execute said operation for receiving said address signal, and for stopping the transmission of said address signal to said address decode circuit when said address buffer activation signal is in an inactive state,said address buffer circuit transmitting said address signal to said address decode circuit after a lapse of a first delay time when said address buffer circuit is unready to start said operation for receiving said address signal at a start of said operation cycle, and transmitting said address signal to said address decode circuit after a lapse of a second delay time that is longer than said first delay time when said address buffer circuit is ready to start said operation for receiving said address signal at the start of said operation cycle.