Patent ID: 8275936
Filing Date: 2012-09-25
Classification: G06F

Abstract:
1. A memory system which includes a plurality of DIMMs, each of which includes a plurality of random access memory (RAM) chips and a memory buffer circuit arranged to buffer and select/distribute a certain subset of data bytes being written to or read from said plurality of DIMMs, said system organized such that the bytes of a given data word are conveyed to said DIMMs via respective byte lanes that are not routed to all DIMMs and stored in a given distributed rank consisting of RAM chips on several DIMMs, comprising: a host controller; a plurality of DIMM slots for receiving respective DIMMs, said host controller arranged to write data to and read data from DIMMs plugged into said slots; and wiring which provides byte lanes between said host controller and said plurality of DIMM slots via which data is written to and read from said DIMMs such that individual bytes may be read or written to RAM chips of different DIMMs as a function of said byte lane routing; said system arranged such that the RAM chips that constitute a given rank are re-mapped across the available DIMMs plugged into said slots such that a data word to be stored in a given rank is striped across the available DIMMs so as to reduce the loading on a given byte lane that might otherwise be present.