Patent ID: 8854100
Filing Date: 2014-10-07
Classification: G06F,H03K

Abstract:
1. An apparatus comprising: a delay circuit coupled to receive an input clock signal and supply a delayed clock signal; a first transistor coupled to receive a first pulse control signal as a first gate signal and supply an output clock node to generate an output clock signal based in part on the first pulse control signal, wherein an asserted edge of the first pulse control signal is responsive to a falling edge of the delayed clock signal; and a second transistor coupled to receive a second control signal as a second gate signal and to supply the output clock node to generate the output clock signal based in part on the second control signal, wherein an asserted edge of the second pulse control signal is responsive to a rising edge of the delayed clock signal, wherein the first and second pulse control signals are generated independently of the output clock signal; and wherein the first pulse control signal is deasserted responsive to a rising edge of the input clock signal and wherein the second pulse control signal is deasserted responsive to a falling edge of the input clock signal.