Patent ID: 6040238
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A method of fabricating gate electrodes in the manufacture of an integrated circuit device comprising:growing a layer of gate silicon oxide over the surface of a semiconductor substrate;depositing a polysilicon layer overlying said gate silicon oxide layer;forming a tungsten silicide layer overlying said polysilicon layer;thermally annealing said tungsten silicide layer at a temperature of 750 to 850.degree. C. for 20 to 60 seconds whereby said tungsten silicide layer is stabilized and stress relaxed;thereafter depositing a hard mask layer overlying said tungsten silicide layer wherein said annealing step prevents silicon atoms from diffusing out of said polysilicon layer into said tungsten silicide layer and causing voids in said polysilicon layer and wherein the absence of said voids prevents the formation of silicon pits in said semiconductor substrate; andpatterning said hard mask, said tungsten silicide, said polysilicon and said gate silicon oxide layers to complete fabrication of said gate electrodes in the manufacture of said integrated circuit device.