Patent ID: 7453118
Filing Date: 2008-11-18
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a first conductivity type semiconductor substrate (SUB); a first conductivity type inversion layer-forming region (CH second conductivity type accumulation layer-forming regions (ACLa, ACLb) formed at least at one side of said inversion layer-forming region (CH a channel-forming region (CH) including said inversion layer-forming region (CH a first second conductivity type region (S/D a second second conductivity type region (S/D an insulating film (GD a first conductive layer (CL) formed on said insulating film (GD a charge accumulation film (GD) having a charge accumulation faculty formed directly on an upper surface of said first conductive layer (CL), a side surface of a stacked portion of said insulating film (GD a second conductive layer (WL) formed directly on said charge accumulation film (GD), said second conductive layer (WL) being a part of a word line, and said first and second second conductivity type regions (S/D wherein said first conductivity type is p-type and second conductivity type is n-type.