Patent ID: 8026707
Filing Date: 2011-09-27
Classification: H01H,H02M,Y10S

Abstract:
1. A circuit, comprising: an output stage including a first transistor and a second transistor, wherein the first transistor is connected to a voltage source, the first transistor and the second transistor are interconnected at an output; and a control circuit in communication with the output stage, the control circuit capable of controlling a duration during which the second transistor is turned on to shorten the duration gradually for reducing an in-rush current, wherein the control circuit is configured to gradually shorten the duration during which the second transistor is turned on thereby reducing the in-rush current, wherein the control circuit includes a control circuit comparator, wherein the control circuit comparator controls when an oscillator comparator communicates with the output stage, wherein the control circuit comparator includes a first input for receiving a ramp down signal, and wherein the control circuit comparator includes a second input for receiving a saw tooth signal.