Patent ID: 8309417
Filing Date: 2012-11-13
Classification: H01L

Abstract:
1. A method of manufacturing a vertical-type non-volatile memory device, comprising: forming an insulation layer structure including a trench on a substrate, the trench having a linear shape to partially expose a surface of the substrate; forming an insulation layer pattern having a linear shape in the trench, the insulation layer pattern being spaced apart from a sidewall of the trench; forming a preliminary single-crystalline semiconductor pattern on both sidewalls of the trench to fill the trench, the preliminary single-crystalline semiconductor pattern having a pillar shape; forming a tunnel oxide layer on a sidewall of the preliminary single-crystalline semiconductor pattern; forming a charge-trapping layer and a blocking dielectric layer on the tunnel oxide layer; forming a control gate pattern on the blocking dielectric layer to face the sidewall of the preliminary single-crystalline semiconductor pattern, the control gate pattern having a linear shape; and partially removing the insulation layer pattern and the preliminary single-crystalline semiconductor pattern, to form single-crystalline semiconductor patterns having pillar shapes.