Patent ID: 6051878
Filing Date: 2000-04-18
Classification: H01L,H05K,Y10S,Y10T

Abstract:
A semiconductor assembly, comprising:a base substrate having a first surface including a plurality of bond pads;a first stacked substrate having a first surface and a second surface wherein at least one of said first stacked substrate first surface and second surface includes a plurality of bond pads;at least one first semiconductor die disposed on said first surface of said first stacked substrate, wherein said at least one first semiconductor die includes a plurality of bond pads;an at least one second semiconductor die having a first surface facing said base substrate first surface and having a plurality of bond pads on said at least one second semiconductor die first surface, said at least one second semiconductor die disposed on said second surface of said first stacked substrate;at least one first intercoupler electrically coupled between at least one of said plurality of first stacked substrate first surface bond pads and first stacked substrate second surface bond pads, and at least one of said plurality of first semiconductor die bond pads;at least one second intercoupler extending between and electrically coupling said base substrate and said first stacked substrate, wherein said at least one second intercoupler physically positions said first stacked substrate in a substantially parallel spaced relationship relative to said base substrate;a second stacked substrate having a first surface and a second surface, each including a plurality of bond pads;at least one third semiconductor die disposed on said first surface of said second stacked substrate, said at least one third semiconductor die having a plurality of bond pads located thereon;at least one fourth semiconductor die disposed on said second surface of said second stacked substrate, said at least one fourth semiconductor die having a plurality of bond pads located thereon;at least one fourth intercoupler electrically coupled between at least one of said plurality of second stacked substrate first surface bond pads and said plurality of second stacked substrate second surface bond pads, and at least one of said plurality of fourth semiconductor die bond pads; andat least one fifth intercoupler extending between and electrically coupling said second stacked substrate and one of said first stacked substrate first surface, said first stacked substrate second surface, and said base substrate first surface, wherein said at least one fifth intercoupler separates said second stacked substrate from said first stacked substrate first surface, said first stacked substrate second surface, or said base substrate first surface.