Patent ID: 6613648
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A method for shallow trench isolation, said method comprising:depositing a layer of polysilicon over a semiconductor substrate; depositing a layer of tetraethylorthosilicate over said layer of polysilicon; etching said layer of tetraethylorthosilicate and said layer of polysilicon such that an opening is formed that extends through said layer of tetraethylorthosilicate and said layer of polysilicon, said opening exposing side surfaces of said layer of polysilicon; etching said side surfaces of said layer of polysilicon such that said side surfaces are extended laterally; and wherein, upon subsequently forming a trench beneath said opening, and subsequently depositing dielectric material such that said dielectric material fills said opening and fills said trench, said lateral extension of said side surfaces reducing dishing of said dielectric material during chemical mechanical polishing of said dielectric material.