Patent ID: 9142642
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate structure on a semiconductor substrate; and a source region and a drain region recess formed in the semiconductor substrate on opposing sides of the gate structure; wherein each of the source region and the drain region recesses is filled with a plurality of doped stressor layers, comprising a first layer of undoped stressor material layer, a second layer of lightly doped stressor material including dopant atoms, a highly doped layer of stressor material having a concentration of dopant atoms greater than the lightly doped second layer, a cap layer over the highly doped layer and having a concentration of dopant atoms greater than the highly doped layer, and a third undoped layer of stressor material free from dopant atoms disposed between the second layer and the highly doped layer; wherein the second layer is disposed over the first layer and extends into a recess formed by an upper surface of the first layer; and wherein the highly doped layer is disposed over the second layer and extends into a recess formed by an upper surface of the second layer.