Patent ID: 8405222
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A method of manufacture of an integrated circuit system comprising: providing a bulk substrate; forming an interlayer dielectric directly on the bulk substrate; forming a contact of a first conductive material in the interlayer dielectric; forming an etch stop layer over the bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a recess through the etch stop layer; forming an insulator in the recess and over the etch stop layer; forming a barrier layer over the insulator; depositing a second conductive material different from the first conductive material of the contact over the barrier layer; applying a first planarization force to remove portions of the first conductive material, the barrier layer, and the insulator until the hard mask is reached; applying a second planarization force to remove the hard mask and the buffer layer such that a top surface of the etch stop layer is coplanar with top surfaces of the insulator, the liner, and the second conductive material; and forming a passivation layer directly on the top surfaces of the second conductive material and the etch stop layer, the second conductive material and the etch stop layer having uniform surface planarity.