Patent ID: 6373413
Filing Date: 2002-04-16
Classification: G11B,H03M

Abstract:
A data decoding apparatus which receives an input signal produced by assigning an intercode interference every predetermined length unit of a digital signal having a binary logic level, and identifies the digital signal having a binary logic level from this input signal, comprising:equalizing means for outputting an equalized signal by applying an equalization having predetermined equalization characteristics to said input signal, binarizing means for outputting a binary signal by binarizing said equalized signal, provisional identifying means for identifying the logic level of said binarized signal with an identifying error of effectively one clock of a clock signal based on said binarized signal, and outputting this identification result as a provisional identification result, correcting means for detecting a timing with which the logic level of said binarized signal inverts in one clock interval of said clock signal, and correcting said provisional identification result by this detection result, analog/digital conversion means for analog/digital conversion of said equalized signal, digital equalizing means for outputting a digital equalized signal by applying an equalization having equalization characteristics depending on said assigned intercode interference method to the output of said analog/digital conversion means, and identifying means for limiting the state transitions which can be obtained from the logic level of said digital equalized signal based on said provisional identification result corrected by said clock signal and said correcting means, detecting the most probable state transition from these limited state transitions, and identifying and outputting said digital signal from said digital equalized signal based on the detected state transition.