Patent ID: 6434078
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A semiconductor device comprising:a first power supply terminal receiving a first power supply potential; a second power supply terminal receiving a second power supply potential; a control circuit for generating a test mode signal; and a voltage down converter for receiving the first and second power supply potentials and lowering the first and second power supply potentials to generate first and second internal potentials, said voltage down converter including a first reference potential generator for generating a first reference potential as a reference for the first internal potential, a first comparator for comparing the first internal potential with the first reference potential, said first comparator being disabled in response to the test mode signal, and a first drive circuit for supplying a current from a first node receiving the first power supply potential to a first output node outputting the first internal potential according to an output of said first comparator when the test mode signal is inactivated and connecting the first output node to the first node when the test mode signal is activated.