Patent ID: 6256259
Filing Date: 2001-07-03
Classification: G11C,H03K,H03L

Abstract:
A method of locking a delay-locked loop to an input clock signal, comprising the acts of:providing a digital count;producing a pulse in response to an edge of the input clock signal;delaying the pulse with a delay circuit having a delay time determined by the count to produce a feedback clock signal, the pulse being delayed by the acts of:charging a capacitance to a selected voltage;controllably charging or discharging the capacitor in response to the pulse;detecting when the capacitor voltage passes a threshold voltage; andproducing a delayed pulse in response to the capacitor voltage passing the threshold voltage;comparing the feedback clock signal to the input clock signal to determine the phase of the feedback clock signal leading or lagging the input clock signal;producing a signal indicative of the feedback clock signal leading or lagging the input clock signal the feedback signal changing in a first direction if the feedback clock signal leads the input clock signal and in a second direction opposite the first direction if the feedback clock signal lags the input clock signal;if feedback signal changes in the first direction responsive to the feedback clock signal leading the input clock signal, adjusting the count in a first direction; andif feedback signal changes in the second direction responsive to the feedback clock signal lagging the input clock signal, adjusting the count in the second direction;increasing the delay time in response to the count being adjusted in the first direction; anddecreasing the delay time in response to the count being adjusted in second direction.