Patent ID: 6324116
Filing Date: 2001-11-27
Classification: G06F

Abstract:
A semiconductor device including a DRAM having a plurality of first memory cells which are arranged in rows and columns, a pair of input and output lines for transferring data in a selected one of the first memory cells, an input and output sense amplifier coupled to the pair of input and output lines for amplifying data on pair of input and output lines in a first mode, and a write driver for driving received data to the pair of input and output lines in a second mode; and an SRAM comprising:a plurality of second memory cells which are arranged in rows and columns, a write bit line for transferring data output from the DRAM in the first mode, a write word line for controlling the data on the write bit line to be transmitted to a selected one of the second memory cells in the first mode, a read word line for controlling data to be read from the selected second memory cell in the second mode, and a read bit line for transmitting the data read from the second memory cell to the DRAM, wherein the reading operation of the DRAM and the writing operation of the SRAM are simultaneously controlled by a first control signal in the first mode, and the reading operation of the SRAM and the writing operation of the DRAM are simultaneously controlled by a second control signal, and wherein the SRAM comprises: a write word line control unit for generating a DRAM read control signal for driving the write word line; and a read word line control unit for generating a DRAM write control signal for driving the read word line.