Patent ID: 6014039
Filing Date: 2000-01-11
Classification: H03K

Abstract:
An integrated circuit including a CMOS high voltage drive output buffer comprisinga resistor divider tree disposed between ground (VSS) and a high voltage reference potential (VDD5) for generating a plurality of intermediate reference voltage potentials VL1, VL2, VL3, VH1, VH2, VH3, where VL3 is defined as one-third of the value of the high voltage reference potential; anda tapered inverter chain network for receiving an input signal and comprising a series of inverter stages, each stage biased by a pair of reference voltage potentials generated by the resistor divider tree (VL1 and VH1, VL2 and VH2, VL3 and VH3), for generating a pair of outputs P and N related to the input signal;CHARACTERIZED IN THAT the high voltage drive output buffer further comprises a drive circuit comprisinga first P-channel device and a transmission gate, the input of the transmission gate coupled to output signal P from the tapered inverter chain and the output of the transmission gate coupled to the gate of the first P-channel device;a second, clamping, P-channel device and a pair of N-channel devices, the pair of N-channel devices coupled in series between the gate of the second P-channel device and the VL3 intermediate reference voltage, the source of the second P-channel device coupled to the drain of the first P-channel device, defining the connection as node C, and the drain of the second P-channel device coupled to a voltage potential, the gate of the first N-channel device controlled by a reference voltage VDD, where VDD<VDD5 and the gate of the second N-channel device controlled by a generated voltage VDD2, where VDD2 is defined as a predetermined voltage drop below when VDD is not present and VDD2=VDD when VDD is present;a third P-channel device and a fourth P-channel device coupled in series between the gate of the second P-channel device and the voltage potential, the gate of the third P-channel device coupled to a reference voltage TUB1, where TUB1=VDD5 when VDD5 is present and TUB1=VDD2 when VDD5 is not present, and the gate of the fourth P-channel device coupled to generated voltage VDD2, the third and fourth P-channel devices for turning ""off"" the second P-channel device when VDD5 is not present; anda fifth P-channel device and a sixth P-channel device, the gates of the fifth and sixth devices controlled by VDD5 and the sources of the fifth and sixth devices coupled to the generated voltage VDD2, the drain of the fifth device coupled to the gate of the first P-channel device and the drain of the sixth device coupled to node C, the fifth and sixth devices for turning ""on"" in the absence of VDD5 and clamping the gate of the first P-channel device and node C to generated voltage VDD2 in the absence of VDD5.