Patent ID: 8705680
Filing Date: 2014-04-22
Classification: H03L,H04J

Abstract:
1. A CDR circuit comprising: a recovered clock generation circuit which receives a first reference clock having the same frequency as a data rate frequency of input data and generates a recovered clock in phase with the input data; and a data write/read circuit which writes the input data using the recovered clock as a write clock, and reads out the input data using, as a read clock, a clock which has the same frequency as the recovered clock and is asynchronous to the recovered clock, wherein said recovered clock generation circuit comprises: a first VCO which generates the recovered clock, the first VCO having an oscillation frequency controlled in accordance with a first frequency control signal and an oscillation phase controlled at a voltage transition point of the input data; and a frequency comparator which compares the frequency of the first reference clock with the frequency of the recovered clock and outputs a signal of a comparison result as the first frequency control signal; a first frequency divider which frequency-divides a second reference clock having a frequency equal to or different from the data rate frequency of the input data; a second VCO which outputs, as the read clock of said data write/read circuit, an output clock whose oscillation frequency is controlled in accordance with a second frequency control signal; a second frequency divider which frequency-divides an output clock from said second VCO; and a phase comparator which compares a phase of a clock input from said first frequency divider with a phase of a clock input from said second frequency divider, and outputs a signal of a comparison result as the second frequency control signal.