Patent ID: 8356239
Filing Date: 2013-01-15
Classification: G06F

Abstract:
1. A data processing system comprising: cache circuitry having a plurality of ways; mirroring control logic coupled to the cache circuitry, the mirroring control logic indicating a mirrored way pair of the plurality of ways and a non-mirrored way of the plurality of ways, wherein the mirrored way pair comprises a first way and a second way of the plurality of ways, and the second way is configured to store cache data fields redundant to cache data fields of the first way; and comparison logic which, in response to an access address hitting in the first way or the second way within the mirrored way pair, performs single-bit error detection by performing a bit comparison between cache data from the first way addressed by an index portion of the access address with cache data from the second way addressed by the index portion of the access address to provide a bit parity error signal, and in response to an access address hitting in the non-mirrored way of the plurality of ways, the data processing system performs multiple-bit error checking.