Patent ID: 8027206
Filing Date: 2011-09-27
Classification: G11C

Abstract:
1. A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), comprising: a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line; a clamping circuit coupled to the bit line, the clamping circuit being configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level, wherein the desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM; and a read isolation element interposed between the bit cell and the clamping circuit, the isolation element being configured to selectively isolate the clamping circuit from the bit line during a write operation.