Patent ID: 7293156
Filing Date: 2007-11-06
Classification: G06F

Abstract:
1. A storage system, comprising: one or more slow-access-time-mass-storage nodes, coupled to store data at respective first ranges of logical block addresses (LBAs); a plurality of interim-fast-access-time nodes, configured to operate independently of one another, each interim-fast-access-time node being assigned a respective second range of the LBAs and coupled to receive data from and provide data to the one or more slow-access-time-mass-storage nodes having LBAs within the respective second range, all of the second ranges of LBAs comprising a total LBA range; and one or more interface nodes, which are adapted to receive input/output (IO) requests from host processors directed to specified LBAs and to direct all the IO requests to the interim-fast-access-time node to which the specified LBAs are assigned; wherein each interim-fast-access-time nodes is configured to be reassignable to a new respective second range of the LBAs, all of the new respective second ranges of LBAs comprising the total LBA range.