Patent ID: 6771103
Filing Date: 2004-08-03
Classification: G01S

Abstract:
A shift clock signal generating apparatus for generating a shift clock signal having a prescribed phase difference from a reference clock signal, comprising:a delay line receiving the reference clock signal and including a plurality of unit delay elements connected in cascade, wherein each of the unit delay elements provides a prescribed signal delay time, and the reference clock signal propagates in the delay line while being successively delayed by the unit delay elements; a shift clock signal output path; a group of switches having first ends connected with output terminals of the unit delay elements respectively, and second ends connected with the shift clock signal output path, wherein when specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as the shift clock signal; and switch controlling means for determining the specified one among the switches on the basis of data representing a phase difference of the shift clock signal from the reference clock signal, and for setting the specified switch in its on position, wherein the switch controlling means operates for determining the specified one among the switches on the basis of period data and ratio data, the period data representing a numeric value of a period of the reference clock signal while a time resolution is given by the prescribed signal delay time provided by each of the unit delay elements, the ratio data representing a ratio between a delay time of the shift clock signal relative to the reference clock signal and the period of the reference clock signal.