Patent ID: 9071231
Filing Date: 2015-06-30
Classification: H03K

Abstract:
1. An apparatus comprising: a plurality of logic gates coupled in series; a first pull-down circuit coupled to a first node between two adjacent logic gates of the plurality of logic gates and controlled responsive to a first control signal; a pull-up circuit coupled to a second node between two adjacent logic gates of the plurality of logic gates, wherein the first node is coupled to a logic gate output after a first odd number of the logic gates and the second node is coupled to a gate output after a second odd number of the logic gates where the second odd number is greater than the first odd number; and a second pull-down circuit coupled to an output of one of the logic gates and controlled responsive to a second control signal, wherein a duty cycle of a signal provided by the plurality of logic gates is increased responsive to the first control signal and decreased responsive to the second control signal.