Patent ID: 8207744
Filing Date: 2012-06-26
Classification: G01R,H01L

Abstract:
1. A testing apparatus comprising: a plurality of test units for testing a plurality of wafers under test in parallel, the number of test units being a multiple or divisor of the number of wafers stored in a wafer cassette; a storage that is shared by the plurality of test units, the storage storing therein the wafers under test to be tested by the plurality of test units; a transport mechanism that transports the wafers under test between the storage and each of the plurality of test units; a mainframe that specifies a test procedure for each of the plurality of test units; a power source that is shared by the plurality of test units, the power source supplying power to each of the plurality of test units; and a pressure source that is shared by the plurality of test units, the pressure source supplying a pressure to each of the plurality of test units, wherein each of the plurality of test units includes: when supplied with a negative pressure, the holding member attracts by suction the wafer under test to bring the wafer under test into contact with the connector, the holding member contacts airtight with a smooth region of the wafer under test, at a peripheral edge portion of the wafer under test, that is adjacent to a circuit region in which the plurality of circuits are formed, in a vicinity of the circuit region, to attract the wafer under test by suction.