Patent ID: 9176880
Filing Date: 2015-11-03
Classification: G06F,G06T,Y02D

Abstract:
1. A cache memory system, the system comprising: a first associative cache unit configured to search for a cache line corresponding to an access-requested address, among a stored set of one or more first cache lines that include delayed-replacement information, wherein the delayed-replacement information indicates whether or not texture data that is referred to at a position of an edge of a tile is included in the respective cache line; and a second associative cache unit configured to store one or more second cache lines, and to search among the one or more second cache lines, for a cache line corresponding to the access-requested address; wherein the first associative cache unit is further configured to, when no cache line corresponding to the access-requested address is found in any of the first associative cache unit and the second associative cache unit: