Patent ID: 9053939
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. A device comprising: a crystalline silicon substrate layer of a heterojunction bipolar transistor (HBT); an n-type doped crystalline collector of said HBT in an upper portion of said crystalline silicon substrate layer; a p-type doped crystalline layer above said n-type doped crystalline collector, said p-type doped crystalline layer comprising a p-type doped internal base of said HBT; a crystalline silicon cap on said p-type doped crystalline layer, said crystalline silicon cap including an n-type impurity and comprising an n-type doped emitter of said HBT; an external base layer and an insulating layer on said crystalline silicon cap, said external base layer and said insulating layer having an opening extending down to an upper surface of said crystalline silicon cap; insulating sidewalls disposed on said opening; and an n-type doped crystalline silicon emitter stack within said insulating sidewalls of said opening, said n-type doped crystalline silicon emitter stack having an upper surface that is lower than or equal to an upper surface of said insulating layer and a lower surface that is co-planar with said upper surface of said crystalline silicon cap and a lower surface of said insulating sidewalls.