Patent ID: 6704221
Filing Date: 2004-03-09
Classification: G11C

Abstract:
A floating gate programmable device cell comprising:a negative injection transistor having drain, source, bulk, and gate, wherein said source is coupled to ground and wherein said drain forms an output of said cell; a positive injection transistor having drain, source, bulk, and gate, wherein said drain, source, and bulk are coupled to a programming voltage and wherein said gate is coupled to said negative injection transistor gate to form a floating gate node; and a capacitor having a first terminal coupled to said floating gate node and a second terminal coupled to a control voltage wherein the states of said programming voltage and said control voltage determine negative charge injection onto said floating gate node and positive charge injection onto said floating gate node and wherein a voltage on said floating gate node comprises a nonvolatile memory state that is detectable by the impedance of said output.