Patent ID: 6813697
Filing Date: 2004-11-02
Classification: G06F

Abstract:
A data processor comprising:a data processing unit; a memory; and a transfer control unit to selectively set a first mode or a second mode, wherein said data processing unit is capable of accessing the entire part of the memory by making access with an address signal having the length of first bits in said first mode and is capable of accessing a first area as a part of the memory through the access with the address signal having the length of second bits that is less than the length of first bits in the second mode, wherein said transfer control unit executes a transfer control of information using the address signal having the length of first bits also in the second mode, and wherein said transfer control unit in the second mode executes transfer control of information, from the first area of the memory, to a second area other than said first area, in the address space accessed with the address signal having the length of first bits or executes transfer control to said first area of the information stored in the second area.