Patent ID: 9111506
Filing Date: 2015-08-18
Classification: G09G,H04N

Abstract:
1. A display device, comprising: a plurality of pixels; a plurality of gate lines; a plurality of data lines; and a gate driver connected to the plurality of gate lines, wherein the gate driver receives a first scan start signal, a second scan start signal and clock signals, and outputs a gate-on voltage to each of the plurality of gate lines, wherein the gate driver outputs a gate-on voltage to the plurality of gate lines such that the gate-on voltages do not overlap with each other when the gate driver receives the first scan start signal, and wherein the gate driver outputs a gate-on voltage to at least two of the gate lines at substantially the same time during a first period when the gate driver receives the second scan start signal, wherein the gate driver outputs a gate-on voltage to another at least two of the gate lines at substantially the same time during a second period after the first period in response to a delayed version of the second scan start signal, wherein the at least two gate lines and the another at least two gate lines are either both consecutive odd lines or both consecutive even lines of the gate lines, wherein the plurality of data lines transfer a black data voltage when the gate driver receives the second scanning start signal, wherein the gate driver includes a plurality of stages connected to the gate lines, respectively, each of the plurality of stages includes a control terminal, an input terminal, and an output terminal, the input terminal receives the clock signals and the output terminal is connected to the corresponding gate line, the control terminal of the first stage of the plurality of stages receives the scan start signals, and the control terminals of the remaining stages are connected to output terminals of previous stages, wherein the clock signals include a first clock signal and a second clock signal, a phase difference between the first clock signal and the second clock signal is 180 degrees, and input terminals of odd numbered stages of the plurality of stages receive the first clock signal and input terminals of even-numbered stages of the plurality of stages receive the second clock signal, wherein control terminals of the odd numbered stages receive the second scan start signal, wherein the gate driver receives the second scan start signal when the first clock signal is at a low level, and wherein the gate driver further includes a plurality of AND gates, output terminals of the plurality of AND gates are connected to control terminals of the even numbered stages, and first input terminals of the plurality of AND gates receive the second scan start signal and second input terminals of the plurality of AND gates are connected to output terminals of a corresponding one of the odd numbered stages.