Patent ID: 6495467
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method of fabricating a non-volatile memory device, comprising the steps of:forming a device isolation layer in a predetermined region of a semiconductor substrate to define active regions; forming a floating gate pattern covering each of the active regions, a gap region exposing the device isolation layer being formed between the active regions; forming an insulation material pattern filling each of the gap regions, the insulation material pattern having a projection higher than an upper surface of the floating gate pattern, the width of the projection being wider than the width of an upper portion of the gap region; etching the floating gate pattern using the insulation material pattern as an etching mask to form a modified floating gate pattern having a U-shaped cross section on the active regions; removing the insulation material pattern; and forming a gate interlayer dielectric layer and a control gate electrode layer on a surface of the semiconductor substrate in which the insulation material pattern is removed.