Patent ID: 7364981
Filing Date: 2008-04-29
Classification: H01L

Abstract:
1. A method of fabricating memory circuitry, comprising: forming isolation trenches within semiconductive material of a memory array area of a semiconductor substrate and within semiconductive material of a peripheral circuitry area of the semiconductor substrate; depositing a first insulative material to within the isolation trenches of the memory array area and to within the isolation trenches of the peripheral circuitry area, the first insulative material less than filling remaining volume of the isolation trenches within the semiconductive material of the peripheral circuitry area; and after depositing the first insulative material, depositing an insulative nitride-comprising layer to within the isolation trenches within the semiconductive material of the peripheral circuitry area but not to within the isolation trenches within the semiconductive material of the memory array area, the insulative nitride-comprising layer comprising opposing sidewalls that face one another within the semiconductive material and a base surface extending from and between the opposing and facing sidewalls within the semiconductive material.