Patent ID: 6453406
Filing Date: 2002-09-17
Classification: H04L

Abstract:
Apparatus for communicating messages between at least three multiprocessor groups, each of the multiprocessor groups including a plurality of processor units coupled to one another for interprocessor communication by an interprocessor bus, the messages including information identifying a one of the plurality of processor units of a one of the multiprocessor groups as a destination processor unit for receiving the message, the apparatus comprising:each of the multiprocessor groups including interface means coupled to the interprocessor bus of that multiprocessor group for receiving messages communicated thereon by a processor unit of that multiprocessor group to the destination processor unit; link means intercoupling the interface means of each multiprocessor group in a ring configuration for communicating data thereon; the interface means of each of the multiprocessor groups including first circuit means for communicating all data received from the link means to the interprocessor bus in the form of a message, second circuit means for retrieving and storing messages communicated on the interprocessor bus having information identifying the destination processor unit as not being a one of the plurality of processor units of that multiprocessor group, and third circuit means for transmitting the messages from the second circuit means onto the link means in the form of data; and configuration means for determining which processor unit is located with which multiprocessor group of processor units.