Patent ID: 7634639
Filing Date: 2009-12-15
Classification: G06F

Abstract:
1. A method for avoiding a live-lock state in a processor that supports speculative-execution, comprising: issuing instructions for execution in program order during execution of a program in a normal-execution mode; upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode; checking status indicators in a forward progress buffer, wherein the forward progress buffer is a hardware structure separate from a cache, wherein the forward progress buffer and the cache both receive a copy of a cache line that is returned during speculative execution for the launch instruction, and wherein the copy of the cache line in the cache is used for execution of instructions other than the launch instruction, while the copy of the cache line in the forward progress buffer is not used for execution of instructions other than the launch instruction, but is used only to supply data for the launch instruction upon re-executing the launch instruction; wherein if the status indicators in the forward progress buffer indicate that the forward progress buffer contains data for the launch instruction, the method further comprises; otherwise, continuing executing in the speculative-execution mode.