Patent ID: 8975665
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A method of manufacture of an integrated circuit packaging system comprising: forming a first metal layer on a carrier, the first metal layer having a component attachment pad and a first redistribution layer; forming an insulation layer directly on the first metal layer, the insulation layer formed from a fiber fabric pre-impregnated with resin (PPG) material; exposing a portion of the first metal layer and a portion of the insulation layer by removing the carrier, the exposed portion of the component attachment pad and the first redistribution layer facing away from the insulation layer and coplanar with a component side of the insulation layer, and the exposed portion of the first meal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier, the second metal layer having a vertical interconnect within a vertical opening in the insulation layer, and the vertical interconnect directly on the first metal carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the PPG material of the insulation layer and the second metal layer forming a mold lock with the protective layer for resisting delamination, and the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.