Patent ID: 6577194
Filing Date: 2003-06-10
Classification: H03F,H03K

Abstract:
A method for switching a switch from a first logic state to a second logic state, the switch comprising a gate terminal having a gate capacitance and a resistance associated therewith, the gate terminal also having a series inductance coupled thereto, the method comprising, while the switch is in the first logic state, applying a pulse corresponding to the second logic state to the inductance, the pulse having a first level of energy associated therewith, the first level of energy being sufficiently high to overcome damping by the resistance and allow the gate terminal to reach a signal level corresponding to the second logic state thereby switching the switch to the second logic state, the first level of energy also being sufficiently low to mitigate oscillation due to the inductance and the gate capacitance such that the gate terminal settles at the signal level before a subsequent transition of the switch to the first logic state, the method further comprising applying an additional transition to the inductance following the pulse and before the subsequent transition.