Patent ID: 6448644
Filing Date: 2002-09-10
Classification: H01L

Abstract:
An integrated circuit assembly, comprising:a dielectric substrate having first and second opposite surfaces and a plurality of via holes between the first and second surfaces; a metallic film deposited on and attached to sidewalls of the via holes that extends along the sidewalls to the first and second surfaces, wherein the metallic film initiates deposition of an electroless plating; a plurality of conductive traces on the first surface and adjacent to the via holes; an integrated circuit chip having a plurality of input/output terminal pads, wherein the integrated circuit chip is attached to the second surface of the dielectric substrate, the terminal pads are aligned with the via holes, and the terminal pads initiate deposition of the electroless plating; and the electroless plating simultaneously formed on the metallic film in the via holes, on the terminal pads and on the conductive traces, wherein each one of the terminal pads is connected to one of the conductive traces by one continuous portion if the electroless plating in one of the via holes.