Patent ID: 7675771
Filing Date: 2010-03-09
Classification: G11C

Abstract:
1. A semiconductor integrated circuit, comprising: a plurality of word lines; a plurality of source lines; a plurality of bit lines intersecting with the plurality of word lines; a plurality of memory cells formed at intersections of the plurality of word lines and the plurality of bit lines, each of the plurality of memory cells being a floating body cell, a gate of each floating body cell connected to one of the word lines, a drain of each floating body cell connected to one of the bit lines, and a source of each floating body cell connected to one of the source lines; at least one bit line and source line selecting circuit, being responsive to a common select signal, configured to selectively connect at least one of the plurality of bit lines to a first output bit line and to selectively connect at least one source line of the plurality of source lines corresponding to the at least one bit line to a source voltage; and at least one sense amplifier configured to sense data based on a voltage on the first output bit line.