Patent ID: 9018708
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate including a cell region and a peripheral circuit region; buried gates formed in the substrate of the cell region; a bit line formed over the cell region between the buried gates and including a first barrier layer; and a gate formed over the peripheral circuit region and including a second barrier layer and a third barrier layer, wherein the second barrier layer has a thickness greater than that of the first barrier layer to allow the bit line to have a height lower than that of the gate, wherein each of the first barrier layer, the second barrier layer, and the third barrier layer comprises a stack layer including a titanium layer, a tungsten nitride layer, and a tungsten silicon nitride layer, wherein a thickness of the tungsten nitride layer and the tungsten silicon nitride layer included in the second barrier layer is greater than a thickness of the tungsten nitride layer and the tungsten silicon nitride layer included in the first barrier layer.