Patent ID: 7598112
Filing Date: 2009-10-06
Classification: H01L

Abstract:
1. A method of fabricating a phase change memory device, comprising: preparing a semiconductor substrate of a first conductivity type; forming a first interlayer insulating layer on the semiconductor substrate; patterning the first interlayer insulating layer to form a plurality of diode holes in the first interlayer insulating layer; forming first semiconductor Patterns in lower regions of the diode holes; forming second semiconductor patterns on the first semiconductor patterns; forming cell electrodes on the second semiconductor patterns; forming insulating contact spacers in the diode holes, wherein the insulating contact spacers are formed on sidewalls of the diode holes and on the cell electrodes; forming lower electrodes in the diode holes, wherein the lower electrodes are formed on the insulating contact spacers and on the cell electrodes and wherein top surfaces of the lower electrodes are lower than a top surface of the first interlayer insulating layer and higher than a bottom surface of the first interlayer insulating layer; forming phase change material patterns filling the diode holes, wherein the phase change material patterns are formed on the cell electrodes and on the insulating contact spacers, wherein the phase change material patterns extend over the top surface of the first interlayer insulating layer; and forming upper electrodes on the phase change material pattern, wherein the first semiconductor patterns are formed to have the first conductivity type or a second conductivity type different from the first conductivity type, and the second semiconductor patterns are formed to have the first conductivity type, wherein forming the first and second semiconductor patterns comprises: forming recessed semiconductor patterns filling lower regions in the diode holes; doping lower regions of the recessed semiconductor patterns with impurities of the first conductivity type or impurities of the second conductivity type; and doping upper regions of the recessed semiconductor patterns with impurities of the first conductivity type, and wherein forming the recessed semiconductor patterns comprises: forming a single crystalline semiconductor layer filling the diode holes using a selective epitaxial growth technique; planarizing the single crystalline semiconductor layer to form single crystalline semiconductor patterns with flat top surfaces having the same level as a top surface of the first interlayer insulating layer; and after forming the single crystalline semiconductor patterns, partially etching the single crystalline semiconductor patterns to recess the single crystalline semiconductor patterns.