Patent ID: 9041444
Filing Date: 2015-05-26
Classification: H03L

Abstract:
1. A circuit that compensates for an undesired fractional spur in a baseband signal due to a fractional phase lock loop (PLL), the circuit comprising: a time-to-digital converter (TDC) configured to determine a phase difference between a reference frequency received by the fractional PLL and an output oscillating signal generated by the fractional PLL, the output oscillating signal including an output frequency and the undesired fractional spur, the output oscillating signal used to convert a first signal to the baseband signal; a digital signal processor (DSP) configured to estimate an amplitude and a phase of the undesired fractional spur based on the determined phase difference, and to construct an estimate of the fractional spur; and combination logic configured to apply the constructed estimate of the fractional spur to the baseband signal to generate a compensated baseband signal.