Patent ID: 7245155
Filing Date: 2007-07-17
Classification: H03K,H04L

Abstract:
1. A data output circuit comprising: first and second differential MOS transistors receiving first and second input voltages, respectively, sources of said differential MOS transistors being commonly connected; first and second outputs; a first cascade MOS transistor connected between said first differential MOS transistor and said first output; a second cascade MOS transistor connected between said second differential MOS transistor and said second output, gates of said first and second cascade MOS transistors being commonly connected; a first resistive element connected between a ground line and said commonly connected gates; a second resistive element connected between a power supply line and said commonly connected gates; a first MOS transistor connected between said first output and a gate of said first cascade MOS transistor, having a gate connected to said power supply line; and a second MOS transistor connected between said second output and a drain and a gate of said second cascade MOS transistor, having a gate connected to said power supply line.