Patent ID: 6034885
Filing Date: 2000-03-07
Classification: G11C

Abstract:
A DRAM memory structure capable of storing up to four (4) different signal values in each memory cell, comprising:a plurality of memory cells, each memory cell being capable of storing up to four (4) different voltage values, said four (4) different voltage values being a strong one V11 a weak one V10, a weak zero V01 and a strong zero V00, with the values of voltages stored being set forth in the following TABLE,TABLE  RANGE OF VALUES FIRST SECOND VOLTAGE FOR VOLTAGE NAME BIT BIT STORED STORED  Strong one 1 1 V11 V10 < V11 .ltoreq. Vcc Weak one 1 0 V10 V01 < V10 < V11 Weak zero 0 1 V01 V00 < V01 < V10 Strong zero 0 0 V00 GND .ltoreq. V00 < V01  a first sense amplifier coupled to said plurality of memory cells, said first sense amplifier being capable of detecting whether the signal level stored in a selected memory cell is greater than or less than a first reference voltage; anda second sense amplifier coupled to said plurality of memory cells, said second sense amplifier being capable of detecting whether said signal level in said selected memory cell is on one or the other side of a second reference voltage or a third reference voltage, said second reference voltage being between said first reference voltage and the supply voltage and said third reference voltage being between said first reference voltage and a system ground.