Patent ID: 6057192
Filing Date: 2000-05-02
Classification: H01L

Abstract:
A process of manufacturing cross-point matrix memory devices which have floating gate memory cells formed on a semiconductor substrate by a plurality of continuous bit lines laid across the substrate into discrete parallel strips, separated by active areas having a source channel self-aligned to one of the bit lines and/or an isolation field oxide, the process comprising the steps of:growing a thin layer of tunnel oxide a the matrix region;depositing a stack structure that includes a first conductive layer, an intermediate dielectric layer, and a second conductive layer;photolithographing with a Poly 1mask to define a plurality of parallel floating gate regions in said stack structure;self-aligned cascade etching of said stack structure, above the active areas, to define said continuous bit lines;implanting, to confer predetermined conductivity on the active areas;wherein said implantation step is carried out in the presence of field oxide over the source active areas and the self-aligned cascade etching step removes parallel strips from multiple layers, down to the active areas of the substrate, and is discontinued before the field oxide is removed.