Patent ID: 6581195
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A parasitic element extracting apparatus comprising:wire congestion calculating means for calculating a degree of wire congestion in a wiring area, which is placed in a layout of a semiconductor circuit, according to both the number of wires arranged in the wiring area and the number of wires possible to be arranged in the wiring area; dummy wiring area judging means for pre-setting a reference degree of the wire congestion relating to the arrangement of dummy wire, and comparing the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means with the reference degree of the wire congestion to judge whether or not dummy wire is arranged in the wiring area for which the degree of the wire congestion is calculated by the wire congestion calculating means; dummy wiring assuming means for setting an additional amount of the dummy wire according to the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means in cases where it is judged by the dummy wiring area judging means that the dummy wire is arranged in the wiring area, and assuming a circuit layout of the wiring area on condition that the dummy wire, of which the additional amount is set, is arranged in the wiring area; and parasitic element extracting means for extracting information of a parasitic element of the semiconductor circuit from a layout of the semiconductor circuit in which the circuit layout of the wiring area assumed in the dummy wiring assuming step is included.