Patent ID: 9197247
Filing Date: 2015-11-24
Classification: G06F,H03M

Abstract:
1. A nonvolatile memory device comprising: a memory cell array including a plurality of blocks having a plurality of strings connected between a bit line and a common source line, each of the plurality of strings including at least one string selection transistor, first memory cells and at least one ground selection transistor connected in series, each of the first memory cells being connected with word lines stacked in a direction perpendicular to a substrate, wherein second memory cells connected with one word line of the word lines constitute one page; an address decoder configured to select one of the plurality of blocks based on an address; an input/output circuit configured to connect to the memory cell array through bit lines and the word lines, and to store program data in a page connected to a selected word line of the word lines in the selected block at a program operation; and a control logic configured to control the address decoder and the input/output circuit at the program operation, wherein the program data include first data and second data, wherein the first data includes meta data including a seed for randomizing user data, a first parity for a first ECC (error correction code) operation regarding the meta data, and a second parity for a second ECC operation regarding the user data, wherein the second data include the user data.