Patent ID: 7148572
Filing Date: 2006-12-12
Classification: H01L

Abstract:
1. A multilayer wiring structure of a semiconductor device comprising: a substrate; two or more wiring layers formed on said substrate; an upper plug for electrically connecting a wiring formed at one of said wiring layers to the upper wiring layer; and a lower plug opposite to said upper plug with said wiring interposed, for electrically connecting said wiring to the lower wiring layer or to said substrate, said lower plug and said upper plug overlapping when viewed in the perpendicular direction to said substrate; wherein said upper plug is sunk into said one wiring layer, wherein said one wiring layer has a layer of a high-melting-point metal or an alloy of high-melting-point metal on the top surface thereof, and said wiring is in contact with said upper plug through said layer of a high-melting-point metal or an alloy of high-melting-point metal.