Patent ID: 9124256
Filing Date: 2015-09-01
Classification: H03K

Abstract:
1. A method for determining one or more delays in a clock distribution structure connected to a plurality of flip-flops, the method comprising: a) setting a current clock period to an initial value, and recording maximum delay values between source flip-flops and target flip-flops in a flip-flop pair table; b) setting a current table of target flip-flop incremental delays to zero; c) for each target flip-flop, setting a next table entry to a maximum of zero and an incremental source delay associated with the target flip-flop, where the incremental source delay associated with the target flip-flop is computed by taking the maximum, over all source flip-flops for the target flip-flop, of delay values from the flip-flop pair table, subtracting the current clock period, and adding the incremental delay, from the current table, associated with the source flip-flop corresponding to the maximum delay value for the target flip-flop from the flip-flop pair table; d) if the maximum of the entries in the next table is greater than or equal to the current clock period, incrementing the current clock period and going to b); e) if the current table is different from the next table, transferring the next table contents to the current table and going to c); and f) setting a respective delay value of a respective inverter in the clock distribution structure in order, beginning with a closest inverter to an input buffer, with a value equal to minimum of the next table entries for all the flip-flops that the inverter drives, and subtracting the respective delay value of the respective inverter from all the next table entries of flip-flops driven by the respective inverter.