Patent ID: 6486546
Filing Date: 2002-11-26
Classification: H01L,H05K,Y02P,Y10T

Abstract:
A package comprising:a substrate having a plurality of circuits; a plurality of encapsulated semiconductor devices, each encapsulatedsemiconductor device having an upper surface, a lower surface, a first lateral edge located between said upper surface and said lower surface, a second lateral edge located between said upper surface and said lower surface, and a plurality of outer leads extending from said first lateral edge and said second lateral edge; a cage for partially enclosing and retaining said plurality of encapsulated semiconductor devices in a stack, said cage having a wall located adjacent said plurality of encapsulated semiconductor devices in said stack, said cage including: a flexible member generally perpendicular to said upper surface and said lower surface of said encapsulated semiconductor device of said stacked plurality of encapsulated semiconductor devices, said flexible member comprising a layer of material on an inner surface of a portion of said cage, a second flexible member overlying said layer of material attached thereto, and at least one node on an interior of said cage wall adjacent said plurality of encapsulated semiconductor devices retaining said plurality of encapsulated semiconductor devices in said stack in said cage, said at least one node comprising a removable polymeric adhesive attaching said plurality of encapsulated semiconductor devices in said stack to said cage; and a conductive bus line formed on said flexible member, said conductive bus line extending substantially perpendicular to said plurality of encapsulated semiconductor devices in said stack, contacting an equivalent outer lead of said plurality of outer leads of each encapsulated semiconductor device of said plurality of encapsulated semiconductor devices, and connecting to said at least one circuit of said substrate.