Patent ID: 8638142
Filing Date: 2014-01-28
Classification: H03L

Abstract:
1. A method of an auto frequency select operation of an all digital phase lock loop (ADPLL) including a circuit, a digital phase detector and a digitally controlled oscillator, comprising: (a) inputted an ON signal to the circuit, (b) outputting a first shift amount of a phase error in a beginning of starting of the auto frequency select operation between a frequency division signal dividing an output of the digitally controlled oscillator and a reference signal from the digital phase detector to the circuit, (c) storing the first shift amount of the phase error in the beginning of starting of the auto frequency select operation in a flip-flop, (d) detecting a second shift amount of a phase error between a frequency division signal dividing an output of the digitally controlled oscillator and the reference signal in the digital phase detector after a reference time elapses, and (e) outputting the second shift amount from the digital phase detector to the circuit, wherein the first shift amount and the second shift amount are digital values.