Patent ID: 8976595
Filing Date: 2015-03-10
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a cell array connected to a plurality of bit lines in an all bit line structure; a page buffer circuit connected to the plurality of bit lines; and control logic configured to control the page buffer circuit, wherein the control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode; and wherein a sensing operation is performed at least twice in the first read mode and once in the second read mode, wherein in the first read mode, a first read voltage and a second read voltage different from the first read voltage are provided to a word line of memory cells in the selected page, and wherein when a sensing operation is performed using the second read voltage, memory cells identified as off cells by the first read voltage are sensed.