Patent ID: 6600200
Filing Date: 2003-07-29
Classification: H01L

Abstract:
A MOS transistor, comprising:a semiconductor substrate; a well doped by a first conductivity type in said semiconductor substrate, said doped well having a surface; an epitaxial layer having a dopant concentration of less than 1017 cmâˆ’3 and a given thickness, said epitaxial layer disposed on said surface of said doped well; source/drain regions doped by a second conductivity type opposite to said first conductivity type, said source/drain regions disposed in said epitaxial layer, and said source/drain regions having a depth at most equal to said given thickness; a channel region disposed in said epitaxial layer; a first doped layer doped by said first conductivity type and disposed in said epitaxial layer between said source/drain regions, said first doped layer having a depth smaller than said depth of said source/drain regions and a thickness smaller than said given thickness of said epitaxial layer; and a second doped layer doped by said first conductivity type and disposed underneath said first doped layer in said epitaxial layer.