Patent ID: 6260167
Filing Date: 2001-07-10
Classification: H04B,H04L

Abstract:
A system for testing a networking device comprising:a pattern generator for generating a known valid bit pattern for a data packet; anda physical layer (PHY) device configured for outputting a data signal and a receive clock signal in response to the known valid bit pattern and based on a prescribed operation of the PHY device, the PHY device comprising an error checking circuit configured for detecting an error in a received data frame, whereinthe error checking circuit selectively outputs a pass signal indicating operation of the PHY device in accordance with the prescribed operation based on the data signal, andthe PHY device comprises:a translation logic for converting a tri-level signal to a serial bi-level signal,a phase-locked loop (PLL) for generating the receive clock signal based upon the bi-level signal,a deserializer for converting the serial bi-level signal to a first bit sequence of a first length,a descrambler for processing the first bit sequence of a first length to descramble the bits, anda bit decoder for decoding the descrambled first bit sequence of a first length to a second bit sequence of a second length, the second bit sequence containing information associated with the known bit pattern and being outputted as the data signal.