Patent ID: 7872351
Filing Date: 2011-01-18
Classification: H01L

Abstract:
1. A multi-layered metal line of a semiconductor device, comprising: a semiconductor substrate; a lower metal line formed on the semiconductor substrate, wherein a portion of the surface of the lower metal line is recessed below the surface of the remaining portion of the lower metal line; an insulation layer formed on the semiconductor substrate including the lower metal line, wherein the insulation layer has a damascene pattern exposing the recessed portion of the lower metal liner and by which an upper metal line forming region is defined; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.