Patent ID: 6078079
Filing Date: 2000-06-20
Classification: H01L

Abstract:
A semiconductor device having a field effect transistor,said field effect transistor comprising:a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface;a gate electrode being formed on said semiconductor substrate with a gate insulating film interposed therebetween;a first side wall spacer, being formed on one side wall surface of said gate electrode consisting of insulating films of a prescribed number and having a prescribed width;a second side wall spacer, being formed on another side wall surface of said gate electrode, consisting of insulating films of a number being larger than that of said insulating films forming said first side wall spacer and having a width being larger than that of said first side wall spacer;a pair of second conductivity type source/drain regions being formed on said surface of said semiconductor substrate between portions close to those located immediately under both side walls of said gate electrode and outer sides;a first conductive layer doped with second conductivity type impurities and contacting one of said pair of source/drain regions located in said first side wall spacer side;a second conductive layer doped with second conductivity type impurities, covering a surface of said second side wall spacer and contacting another one of said pair of source/drain regions located in said second side wall spacer side,wherein said pair of source/drain regions include:a pair of low-concentration second conductivity type impurity regions being formed in the vicinity of portions immediately under both side ends of said gate electrode;a high-concentration second conductivity type impurity region being formed only in said one of said pair of source/drain regions located in said first side wall spacer side, being connected to one of said pairs of low-concentration second conductivity type impurity regions and extending toward a side being separated from said gate electrode so that said pair of source/drain regions constitute an LDD structure asymmetric with respect to said gate electrode;a first high-concentration second conductivity type layer contacting said first conductive layer and being formed in said high concentration second conductivity type impurity region in a self-aligned manner by the diffusion of the second conductivity type impurities from said first conductive layer;a second high-concentration second conductivity type layer contacting said second conductive layer and being formed in said another one of said source/drain regions in said second side wall spacer side in a self-aligned manner by the diffusion of the second conductivity type impurities from said second conductive layer.