Patent ID: 6448825
Filing Date: 2002-09-10
Classification: H03L

Abstract:
A circuit for generating a signal synchronized to an incoming periodic signal, said circuit comprising:a first node disposed for coupling to said incoming periodic signal; a second node disposed for coupling to an incoming clock; a sequence of modules, each said module comprising a latch, a logic gate, and a time delay, wherein an output of said latch is coupled to said logic gate; and a summing node coupled to an output of said logic gate of each said module, the summing node generating an analog sum; wherein said first node is coupled to a clock input of each said latch; and wherein said second node is coupled to an input of said latch of a first said module and an input of said time delay of said first said module, and wherein an output of said time delay of each said module is coupled to an input of said latch of a next said module, an input of said logic gate of a next said module, and an input of said time delay of a next said module.