Patent ID: 6101550
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A computer system, comprising:a computer;at least one peripheral unit;a signal bus connecting the computer to the at least one peripheral unit; anda controller configured to send periodic polling signals to the at least one peripheral unit, each polling signal having a specified bandwidth, the controller including;an allocation unit configured to allocate bandwidths to a plurality of nodes in a polling list, each node being capable of storing at least one descriptor representing a respective polling signal;the nodes being arranged in a tree structure having a plurality of leaf nodes, a root node, and at least one level of intermediate nodes which are successor nodes for the leaf nodes and predecessor nodes for the root node;the allocation unit being configured to store variables P and S for each node, where P is a maximum bandwidth of polling signals entering a node from predecessor nodes, and S is a sum of bandwidths of polling signals represented by descriptors stored in the node and all successor nodes thereof; andthe allocation unit being configured to allocate bandwidths to the nodes such that a maximum value of P+S for the nodes at each level is minimized.