Patent ID: 8972812
Filing Date: 2015-03-03
Classification: G01R,G06F,Y02D

Abstract:
1. A pipelined processor, comprising: a) a combinational logic of several stages; b) a voltage regulator; c) a counter; d) a comparator; and e) a plurality of stage registers, said stage registers being double latch (DL) registers and each being disposed between two adjacent stages of said combinational logic; wherein said DL register comprises a flip-flop, a latch, an XOR gate, and a MUX module; when a high level of a register clock CLK said data, latched by said flip-flop and said latch respectively, are compared by said XOR gate: if they are same, an output Error of said XOR gate is low level, and an output A of said flip-flop is delivered to a next stage; if they are different, the output Error of said XOR gate is high level, and an output B of said latch is delivered to the next stage; the output Error of a last DL register is inverted, then AND with a clock CLK of said processor to obtain said register clock CLK the result E