Patent ID: 7230847
Filing Date: 2007-06-12
Classification: G11C

Abstract:
1. A re-programmable non-volatile memory system, comprising: a plurality of memory cells that individually have at least one charge storage element positioned over a channel region between source and drain regions, wherein the source and drain regions are of a first conductivity type within a well of a second conductivity type that is opposite to the first conductivity type, the well being formed within a body of the first conductivity type with a junction therebetween, a plurality of control gate lines extending across the charge storage elements of the plurality of memory cells, a first address decoding and voltage supply circuit connected with the plurality of control gate lines and responsive to an address that applies a programming voltage for a time period to an addressed one of the control gate lines, and a second address decoding and voltage supply circuit connected with the source and drain regions that (a) allows the source and drain regions of those of the memory cells along the addressed control gate line that are being programmed to electrically float during the time period that the programming voltage is applied to the addressed control gate line, and (b) connects at least one of the source and drain regions of those of the memory cells along the addressed control gate line that are being inhibited from programming to a voltage source external of the plurality of memory cells during at least a portion of the time period that the programming voltage is applied to the addressed control gate line.