Patent ID: 6448146
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method of forming an integrated circuit capacitor, comprising the steps of:forming a first electrically insulating layer having an opening therein, on a semiconductor substrate; forming an electrically conductive electrode layer on an upper surface of the first electrically insulating layer and on a sidewall of the opening within the first electrically insulating layer; covering the electrically conductive electrode layer with a second electrically insulating layer; planarizing the second electrically insulating layer and the electrically conductive electrode layer to expose the upper surface of the first electrically insulating layer and define a capacitor electrode layer on the sidewall of the opening; selectively etching back the capacitor electrode layer to expose the sidewall of the opening and define a lower capacitor electrode that is recessed relative to the upper surface of the first electrically insulating layer, using the planarized second electrically insulating layer and the first electrically insulating layer as an etching mask; removing the planarized second electrically insulating layer while simultaneously removing the upper surface of the first electrically insulating layer, to expose the lower capacitor electrode; and forming hemispherical silicon grains (HSGs) on an inner surface of the exposed lower capacitor electrode.