Patent ID: 6668361
Filing Date: 2003-12-23
Classification: G06F

Abstract:
An application specific integrated circuit (ASIC) comprising:a standard cell array, the standard cell array comprising a plurality of logic functions; an input/output (I/O) configuration block coupled to at least a portion of the logic functions; and a field programmable gate array (FPGA) function coupled to the I/O configuration block, wherein the FPGA function controls the I/O configuration block based upon configuration information provided thereto, wherein the configuration information comprises a configuration file, wherein the I/O configuration block is adapted to be coupled to signals of an external chip and the configuration file provides timing information to the I/O configuration block to ensure appropriate timing characteristics between the external chip and the ASIC, wherein the configuration information is tuned utilizing an electro-magnetic compatibility (EMC) analyzer to monitor magnetic compatibility of the pinouts of the external chip and the ASIC and to modify the configuration file.