Patent ID: 6163049
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A semiconductor device comprising:a tunnel oxide layer on a channel region of a semiconductor substrate;a floating gate on the tunnel oxide layer;a control gate formed above the floating gate and spaced apart from the floating gate at least a predetermined distance; anda composite dielectric layer between the control gate and the floating gate, the dielectric layer comprising:a first oxide layer on the floating gate, the first oxide layer having a first thickness;a nitride layer on the first oxide layer, the nitride layer having a second thickness; anda second oxide layer having a dielectric constant about equal to or greater than 10 and having a third thickness;wherein the sum of the first, second and third thicknesses corresponds to at least a minimum design data retention; andwherein the first and second oxide layers and the nitride layer have a combined capacitance corresponding to the design rule of the semiconductor device.