Patent ID: 7298157
Filing Date: 2007-11-20
Classification: G01R,G11C

Abstract:
1. An internal voltage generator for a burn-in test in a semiconductor memory device, comprising: at least two transistor switches each of which receiving an external voltage, a word line driver connected to the first transistor switch and receiving a word line driving voltage, wherein the word line driver outputs the word line driving voltage to a word line, and when the first and second transistor switches are in the first predetermined state during a burn-in test mode the first external voltage is outputted to the word line to carry out a burn in test; a bit line driver connected to the second transistor switch and generating a bit line driving voltage, wherein the bit line driver outputs the bit line driving voltage to a bit line, and when the first and second transistor switches are in the first predetermined state during a burn-in test mode the bit line driver outputs a bit line driving voltage generated based on the second external voltage to the bit line to carry out the burn in test.