Patent ID: 8330204
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising a semiconductor substrate; first gate electrodes formed above the semiconductor substrate; second gate electrodes formed above the semiconductor substrate; first diffusion layers each formed in the semiconductor substrate below respective ones of side surfaces of the first gate electrodes; second diffusion layers each formed in a portion of the semiconductor substrate which lies between a portion lying below respective other side surfaces of the first gate electrodes and a portion lying below respective ones of the side surfaces of the second gate electrodes; contact electrodes electrically connected to the first diffusion layers; a first insulating film which is formed into a shape to have concaves between the first gate electrodes and the second gate electrodes; a second insulating film which is formed on the first insulating film to fill the concaves and a portion between the first and second gate electrodes, the first insulating film having an etching rate lower than an etching rate of the second insulating film; a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in at least a partial region, a position of the lowest portion of the third insulating film which lies on the second diffusion layer is set higher than a position of the lowest portion of a portion of the third insulating film which is formed in contact with the contact electrodes on the first diffusion layers; and an inter-level insulating film formed on the third insulating film and formed of a material different from the third insulating film, wherein the upper surfaces of the first and second insulating films between the first gate electrodes and the second gate electrodes are recessed.