Patent ID: 8010872
Filing Date: 2011-08-30
Classification: G06F,G11C

Abstract:
1. An electronic controller comprising a microprocessor in which electricity is supplied from an external electric power source and the operation of an electric load group is controlled in accordance with an operating situation of an input sensor group, and constructed such that a control program including a control constant is transferred and written from an external tool to a nonvolatile program memory cooperated with the microprocessor; wherein the microprocessor is operated on the basis of the control program stored to MRAM (Magnetic Random Access Memory) as the nonvolatile program memory electrically read and written; MRAM is dividedly stored into different address areas comprising a program memory area mainly constructed by an input-output control program not rewritten and changed during the operation of the microprocessor after being transferred and written from the external tool, and a data memory area rewritten and changed at any time during the operation of the microprocessor; the MRAM further includes: a correction code adding writing circuit for writing stored data adding an error correction code to a memory cell of a designation address in accordance with a writing command signal from the microprocessor; a decoding reading-out circuit for decoding and reading-out the stored data from the memory cell of the designation address in accordance with a reading-out command signal from the microprocessor; an error register arranged in the data memory area; and a control program as a confirmation reading-out means and an overlapping abnormality judging means arranged in the program memory area; and the writing command signal from the microprocessor is constructed so as to be supplied to the MRAM through a writing inhibition/releasing means; the error register stores an address number generating an error as error data when there is a code error in the stored data of the memory cell; the stored error data are error data first generated after being reset or transfer-escaped by the microprocessor, or are a memory of a specific address for storing error data sequentially updated if there is a code error with respect to a new address by sequentially reading-out contents of each address of the memory cell; the confirmation reading-out means is operated in accordance with storage of the error data to the error register, and is a means for again reading-out and confirming contents of the error register after the error data are reset or transfer-escaped and the error generating address is then again accessed; the overlapping abnormality judging means is a means for judging that the contents of a memory of the same address are a continuation abnormality when the contents of the error register read out by the confirmation reading-out means include the same error data; the writing inhibition/releasing means inhibits that the writing command signal provided by the microprocessor is supplied to the MRAM with respect to the program memory area of the MRAM in which the control program is stored; the writing inhibition/releasing means releases the writing inhibition function when the external tool is connected to the microprocessor and the control program is ready to write with respect to the MRAM; the writing inhibition/releasing means also releases the writing inhibition function as an exception even when restoring writing of the control program is performed when the external tool is not connected to the microprocessor; and abnormality processing including at least one of abnormality notification and storage of abnormality generation information is executed when the overlapping abnormality judging means makes an abnormality judgment, or is executed in accordance with the execution of abnormality judgments made plural times.