Patent ID: 7644220
Filing Date: 2010-01-05
Classification: G05B

Abstract:
1. A programmable controller comprising: a CPU unit including a microprocessor, a system memory operating in corporation with the microprocessor, a program memory for storing a sequential program, and a device memory for storing I/O information and control information; and at least one I/O unit connected to the CPU unit through a bus, at least one of the I/O units comprising a special unit including an integrated circuit element for sharing a special I/O processing function to complement a control function of the microprocessor, wherein: the special unit includes an electronic substrate, on which a multi-channel input interface circuit and a multi-channel output interface circuit each connected to external connection terminals, and the integrated circuit element used for I/O control whose control specifications can be partially variably set are provided; the integrated circuit element includes a parameter memory corresponding to each channel number and a logic circuit unit whose operation specifications for I/O processing are determined by circuit organization data transmitted from the microprocessor to the parameter memory corresponding to each channel number; the logic circuit unit includes a notification bit memory for counting a logic input signal obtained through the input interface circuit at high speed to transmit a count-up output as a notification signal to the microprocessor, a calculation register for transmitting count data as computational data to the microprocessor, a setting register for storing set data received from the microprocessor, a command latch memory for storing a command signal received from the microprocessor, and a reversible counter for feeding a high-speed pulse output based on contents of the setting register and the command latch memory to the output interface circuit; whether the reversible counter constitutes a high-speed counter circuit for an input signal fed from the input interface circuit to perform high-speed input processing for transmitting the count-up output to the CPU unit or constitutes a high-speed pulse output circuit based on the set data received from the CPU unit to perform high-speed output processing for feeding a predetermined pulse output to the output interface circuit is determined for each channel according to a content of a special instruction included in a control program stored in the program memory; a plurality of types of the high-speed input processing and a plurality of types of the high-speed output processing are performed by the circuit organization data transmitted to the parameter memory; and the input interface circuit feeds a pulse having a frequency proportional to an input signal to the integrated circuit element when the input signal from an external sensor connected to the external connection terminal is an analog signal, whereas the integrated circuit element generates a pulse output at a commanded ON/OFF ratio as an output signal and the output interface circuit smoothes the received pulse output signal to feed the smoothed pulse output signal to an external load when the external load is an analog load.