Patent ID: 6549485
Filing Date: 2003-04-15
Classification: G11C

Abstract:
A timing and control structure for a memory that has a pair of memory banks each of which is associated with respective circuits for selecting the memory locations of the bank and respective circuits for reading the contents of the locations selected, and an internal addressing structure for executing random-access readings by accessing locations corresponding to addresses supplied to the memory from the exterior, and sequential readings by accessing, in sequence, starting from an origin memory location the address of which is supplied to the memory from the exterior, memory locations succeeding the origin location and belonging to one and to the other of the memory banks, the timing and control structure comprising:first circuit means for recognizing, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals comprising a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal which, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings; second circuit means that are controlled by the first circuit means and which, for a random-access reading, generate a first synchronism signal in response to a transition of the first type in the second control signal; third circuit means that are sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon transitions of the second type; and fourth circuit means that are controlled by the first circuit means and which supply a stimulus signal to a timing circuit of the memory, the stimulus signal corresponding to the first synchronism signal for a random-access reading, or to the second synchronism signal for a sequential reading.