Patent ID: 6038164
Filing Date: 2000-03-14
Classification: H01L

Abstract:
An SRAM cell configuration, comprising:a plurality of memory cells each including at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;said first transistor, said second transistor, said third transistor, and said fourth transistor forming a flip-flop circuit connected between a first voltage terminal and a second voltage terminal, and being driven via said fifth transistor and via said sixth transistor;said third transistor and said fourth transistor being complementary to said first transistor and to said second transistor;a first bit line, a second bit line, and a word line, said first bit line and said second bit line extending transversely with respect to the word line;said fifth transistor and said sixth transistor being driven via said word line;said fifth transistor having a second source/drain region connected to said first bit line; said sixth transistor having a second source/drain region connected to said second bit line;said first transistor, said second transistor, said third transistor, and said fourth transistor being arranged at corners of a quadrilateral whereby said first transistor and said fourth transistor is disposed at diagonally opposite corners thereof;said third transistor being arranged between said first transistor and said fifth transistor; andsaid second transistor being arranged between said fourth transistor and said sixth transistor.