Patent ID: 7713824
Filing Date: 2010-05-11
Classification: G03F,H01L

Abstract:
1. A method for controlling etching during photolithography in the fabrication of features on an integrated circuit, comprising: depositing a layer of photoresist on the integrated circuit; selectively exposing portions of the photoresist through a first photolithography mask having a pattern comprising a first shape of a first polarity corresponding to a first feature and a second feature with a gap there between, the first shape having a length in a first direction corresponding to a combined length of the first feature, the gap, and the second feature in the first direction and a width transverse the first direction; selectively exposing portions of the photoresist through a second mask comprising a pattern for a second shape of a second polarity opposite the first polarity, the second shape positioned to correspond to the gap and having a width transverse the first direction that is greater than the width of the first shape and a length in the first direction corresponding to the length of the gap; and developing the photoresist after the selective exposing steps; wherein the second mask further comprises at least one third shape of the second polarity parallel to the second shape, the third shape having a length transverse the first dimension less than a resolution of a photolithography system used in connection with the first and second masks.