Patent ID: 7425739
Filing Date: 2008-09-16
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array composed of a plurality of memory cells located in a matrix; a word line extending in a row direction on the memory cell array; a bit line extending in a column direction on the memory cell array; a shunt area which is located in the memory cell array and extends in the column direction, and in which locations of the plurality of memory cells are forbidden; a first line, at least a portion of which is located in the shunt area, and which is connected to a first area on which the plurality of memory cells are formed; a second line, at least a portion of which is located in the shunt area, which is located above the first line, and which is connected to a source line; and a connection section between the first line and the first area, wherein the first area is a well or a substrate on vhich the plurality of memory cells is formed, at least one memory cell is connected between the bit line and the source line, a first voltage is supplied to the first area through the first line and the connection section, a second voltage is supplied to the source line through the second line, a source and a drain of the memory cell is of a first conductivity type, and the frst area is of a second conductivity type which is oppposite to the first conductivity type.