Patent ID: 6058053
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory blocks, each includinga normal block including a plurality of normal memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to said rows and a plurality of bit lines arranged corresponding to said columns, anda redundant block including a plurality of redundant cells arranged in rows and columns, a plurality of redundant word lines arranged corresponding to said rows and a plurality of bit lines arranged corresponding to said columns,the redundant cells being used as substitution for a normal memory cell belonging to any of said plurality of memory blocks;determining means for determining whether redundancy is to be used or not, in response to an external address signal;first control means responsive to said external address signal for setting a corresponding word line to a selected state, independent from result of determination by said determining means; andsecond control means, receiving result of determination of said determining means, for setting a corresponding redundant word line to a selected state based on said external address signal; whereinsaid first control means sets said corresponding word line to a non-selected state, in response to result of determination that redundancy is to be used by said determining means.