Patent ID: 6222397
Filing Date: 2001-04-24
Classification: H03K

Abstract:
An output circuit receiving an external input signal and a control signal, comprising:an input circuit generating an internal input signal in response to the external signal;an output circuit including a first pMOS transistor coupled between a positive potential source and an output terminal and a first nMOS transistor coupled between a reference potential source and the output terminal, a gate of one of the transistors receiving the internal input signal;a first control circuit receiving the internal input signal and the control signal and outputting a first internal signal in response to the internal input signal and the control signal to a gate of the other one of the transistors, said first control circuit outputting the internal input signal as the first internal signal when the control signal has a first level, and outputting a predetermined level signal as the first internal signal when the control signal has a second level so that the other one of the transistors has a predetermined state;a second nMOS transistor coupled between the reference potential source and the output terminal; anda second control circuit receiving the internal input signal and the control signal and outputting a second internal signal in response to the internal input signal and the control signal to a gate of said second nMOS transistor, said second control circuit outputting the internal input signal as the second internal signal when the control signal has the first level and outputting a low level signal as the second internal signal when the control signal has the second level so that said second nMOS transistor is in an OFF state.