Patent ID: 7995370
Filing Date: 2011-08-09
Classification: G11C,H01L

Abstract:
1. A ferroelectric memory comprising: a memory cell array including a first unit block, a second unit block, and a plurality of dummy cells, and the plurality of dummy cells being arranged toward a column direction, and being disposed between the first unit block and the second unit block, the first unit block including a plurality of first memory cells arranging in t rows, and including a plurality of first plate lines arranging toward a row direction, the second unit block including a plurality of second memory cells arranging in t rows, and including a plurality of second plate lines arranging toward a row direction, u-th (1≦u<t) first plate line among the plurality of first plate lines being electrically connected to the (u+1)-th (1≦u<t) second plate line among the plurality of second plate lines, t-th first plate line among the plurality of first plate lines being electrically connected to first second plate line among the plurality of second plate lines, each of the plurality of dummy cells including a ferroelectric capacitor, and either of the first second plate line or the t-th second plate line of the second unit block extending above the plurality of dummy cells.