Patent ID: 7256627
Filing Date: 2007-08-14
Classification: G06F,H04L

Abstract:
1. An integrated circuit having a phase alignment circuit, the phase alignment circuit comprising: a phase selection circuit configured for outputting a local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value; a synchronizer configured for digitally sampling a received reference clock of a synchronous communications system relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock; and a counter configured for selectively performing one of incrementing or decrementing a counted value based on the digital phase bit, the counted value having a first prescribed number of bits, the counter configured for outputting to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value, the prescribed number of most significant bits from the counted value less than the first prescribed number of bits, the phase selection circuit configured for aligning the phase-adjusted local clock toward the received reference clock based on the phase selection value, wherein the phase selection value specifies one of a plurality of available digital phase increments across a period of a single clock cycle.