Patent ID: 6228700
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method for manufacturing dynamic random access memory (DRAM), comprising the steps of:forming a shallow trench isolation (STI) structure in a substrate such that a plurality of active regions is patterned out, wherein each active region occupies an area having a definite width and length;sequentially forming a gate oxide layer, a conductive layer and a barrier layer over the substrate;removing a portion of the barrier layer and the conductive layer so that a plurality of bit line contact openings and a plurality of node contact openings are formed above the substrate, wherein a length of each bit line contact opening is greater than the width of each active region and a length of each node contact opening is greater than the width of each active region, each node contact opening covers a portion of the STI structure outside the active region, the bit line contact openings and the node contact openings pattern out a plurality of word line structures over a portion of the active region and a portion of the STI structure just outside the active region, and a plurality of junction areas connects neighboring word line structures;forming a plurality of spacers on the sidewalls of bit line contact openings and the node contact openings;removing a portion of the gate oxide layer at a bottom of each bit line contact openings and each node contact openings not covered by the spacers so that a portion of the substrate is exposed;forming a source terminal in the substrate exposed at the bottom of each bit line contact opening and forming a drain terminal in the exposed substrate at the bottom of each node contact opening;forming a bit line plug inside each bit line contact opening;forming a landing pad inside each node contact opening;forming an oxide layer over the bit line plugs and the landing pads;performing word line patterning by removing the junction areas between neighboring word line structures;forming a first dielectric layer over the substrate;forming a plurality of first contact openings in the first dielectric layer and removing a portion of the oxide layer to expose the bit line plugs;forming a bit line structure above the first dielectric layer such that the bit line structure fills the first contact opening and connects the bit line plugs electrically;forming a second dielectric over the substrate;forming a plurality of second contact openings in the first and the second dielectric layer and removing a portion of the oxide layer to expose the landing pads, wherein the second contact openings have no direct connection with the bit line structures;forming a plurality of node contacts inside the second contact openings so that the node contacts and the landing pads are connected electrically; andforming a plurality of capacitors above the second dielectric layer such that each capacitor is electrically connected to a node contact.