Patent ID: 6198306
Filing Date: 2001-03-06
Classification: H03K

Abstract:
A CMOS logic circuit having input and output stages coupled to prevent the output stage from remaining in an ambiguous logic state including in combination:positive and negative power supplies;a CMOS input stage having a first P-type MOS transistor and a first N-type MOS transistor, each having a source, a drain and a gate, with the drain of said P-type MOS transistor connected at a first junction with the drain of said first N-type MOS transistor, placing the source-drain channels of said first transistors in series circuit with one another;a source of input signals coupled in common to the gates of said first P-type MOS transistor and said first N-type MOS transistor;a CMOS output stage having a second P-type MOS transistor and a second N-type MOS transistor, each having a source, a drain and a gate, with the drain of said second P-type MOS transistor coupled at a second junction with the drain of said second N-type MOS transistor placing the source-drain channels of said second transistors in series circuit with one another;the gates of said second transistors coupled in common to said first junction;an output terminal coupled with said second junction;a positive feedback circuit coupled between said second transistors and said first transistors to ensure precise signal switching at said second junction even for slowly changing signals at said source of input signals, said positive feedback circuit including a third P-type MOS transistor and a third N-type MOS transistor, each having a source, a drain and a gate, with the gates of said third transistors coupled in common to the gates of said second transistors, with the source of said third P-type MOS transistor connected to said positive power supply, the drain of said third P-type MOS transistor coupled with the sources of said first and second P-type MOS transistors, the drain of said third N-type MOS transistor coupled with the sources of said first and second N-type MOS transistor, and the source of said third N-type MOS transistor coupled with the negative power supply.