Patent ID: 7477566
Filing Date: 2009-01-13
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a memory cell array including a plurality of memory cells, a first bit line pair connected to the plurality of memory cells and performing write-in or read-out of complementary data for the plurality of memory cells in the memory cell array, a second bit line pair performing write-in or read-out of complementary data for the plurality of memory cells in the memory cell array, a plurality of first word lines provided to the plurality of memory cells for selecting a first memory cell from the memory cell array, a plurality of second word lines provided to the plurality of memory cells for selecting a second memory cell from the memory cell array, a first pull-up circuit that, when data is written in the first memory cell from the first bit line pair, pulls up low level of a lower-level line of the first bit line pair, and a plurality of first regulator circuits each connected to a corresponding one of the plurality of memory cells, wherein the first regulator circuit places the first memory cell in a floating state when the first memory cell is selected, and connects the first memory cell to a predetermined voltage when the first memory cell is not selected.