Patent ID: 7172908
Filing Date: 2007-02-06
Classification: H01L

Abstract:
1. A method of forming an interconnect between a magnetoresistive memory element of a memory cell and a conductive memory line comprising: forming a magnetoresistive memory element to a final width; forming a mask layer over and around the magnetoresistive memory element to a predetermined height over the magnetoresistive memory element; forming a first insulating layer over the mask layer; removing portions of the first insulating layer using a surface planarization process and using the mask layer as a stop, the surface planarization process reducing the first insulating layer to substantially the predetermined height thereby exposing at least a portion of the mask layer; forming a conductive via through the mask layer at the exposed portion(s) to contact the magnetoresistive memory element; and forming the conductive memory line on the conductive via.