Patent ID: 7279754
Filing Date: 2007-10-09
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising an SRAM memory cell including first and second drive MISFETs and first and second vertical MISFETs disposed at an intersection of a pair of complementary data lines and a word line, said first drive MISFET and second drive MISFET being cross-coupled such that a gate electrode of said first drive MISFET is electrically connected to a drain region of the second drive MISFET and a gate electrode of said second drive MISFET is electrically connected to a drain region of said first drive MISFET, wherein said first and second vertical MISFETs are formed over said first and second drive MISFETs formed on a principal surface of a semiconductor substrate, wherein said first and second vertical MISFETs each comprise a source region, channel region and drain region formed in a laminate in a perpendicular direction from said principal surface of said semiconductor substrate, and a gate electrode formed via a gate insulating film on a side wall of said laminate, wherein said complementary data lines are formed over said first and second vertical MISFETs, wherein one of said source region and drain region of each of said first and second vertical MISFETs are respectively electrically connected to said complementary data lines, wherein the other of said source region and drain region of said first vertical MISFETs is electrically connected to said gate electrode of second drive MISFET and said drain region of said first drive MISFET, and wherein the other of said source region and drain region of said second vertical MISFETs is electrically connected to said gate electrode of first drive MISFET and said drain region of said second drive MISFET.