Patent ID: 6682977
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A method for fabricating a gate of a flash memory, the method comprising:providing a substrate; forming a tunneling oxide layer on the substrate; forming a first conductive layer on the tunneling oxide layer; forming a dielectric layer on the first conductive layer; forming a plurality shallow trench isolation (STI) structures in the substrate, wherein an active area, defined by every two shallow trench isolation structures, is simultaneously formed; removing a top portion of the shallow trench isolation structures to expose a sidewall of the dielectric layer and portion of a sidewall of the first conductive layer; a first etching process to remove part of the dielectric layer; forming a second conductive layer on the active area and the shallow trench isolation structures; a second etching process to remove the second conductive layer to expose a top face of the shallow trench isolation structures; removing the dielectric layer; forming a conformal insulation layer over the substrate; and forming a third conductive layer on the conformal insulation layer.