Patent ID: 6281114
Filing Date: 2001-08-28
Classification: H01L,Y02P

Abstract:
A process for planarization of an insulation layer disposed on a semiconductor wafer and having a surface containing a downwardly stepped chemically mechanically polished arrangement of metal lines in corresponding trenches defined in the insulation layer between intervening insulation portions;including a first pattern portion of metal lines separated by intervening insulation portions and defining a first pattern factor having a first value, and an adjacent second pattern portion of metal lines separated by intervening insulation portions and defining a second pattern factor having a second value different from the first value;the second pattern portion being located at a step depth relative to the insulation layer surface different from the step depth of the first pattern portion relative to said layer surface;the process comprising chemically mechanically polishing the insulation layer surface and the first and second pattern portions sufficiently to reduce the step depths of the first and second pattern portions relative to the insulation layer surface and relative to each other, for planarization of the insulation layer surface and first and second pattern portions relative to each other.