Patent ID: 6961841
Filing Date: 2005-11-01
Classification: G06F

Abstract:
1. A system for processing data using a plurality of reconfigurable processors, the system comprising: a memory subsystem coupled to a data processor and including an addressable memory array; a first reconfigurable processor within the memory subsystem and coupled to a first address in the addressable memory array, wherein responsive to a first data value being written at the first address, the first reconfigurable processor performs a first configured function, generates a second data value, and writes the second data value to a second address in the addressable memory array; a second reconfigurable processor within the memory subsystem and coupled to the second address in the addressable memory array, wherein, responsive to the second data value being written at the second address, the second reconfigurable processor retrieves the second data and performs a second configured function; a control logic block in the memory subsystem in the communication path between the data processor and the addressable memory array for accessing data at specified addresses within the addressable memory array; a data bus and an address bus connecting the control logic block and the addressable memory array; a communication oath between the first reconfigurable processor and the address bus; and a control block in the communication path between the first reconfigurable processor and the address bus, wherein the control block comprises a command decoder for decoding commands from the data processor, a pipeline counter for counting clock cycles, an equality comparator for determining whether the output of the pipeline counter corresponds to a predetermined number of clock cycles, and status registers for receiving an output from the equality comparator.