Patent ID: 6272619
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A computer system, comprising:a memory;a superscalar microprocessor for executing instructions obtained from an instruction store; anda bus coupled between said microprocessor and said memory, wherein said microprocessor comprises:a fetch circuit to fetch a plurality of instructions from said instruction store during a first processor cycle, the plurality of instructions being in program order;a first in first out (FIFO) buffer to buffer at most four of said plurality of instructions from said fetch circuit during a second processor cycle;a dispatch circuit to concurrently decode, during said second processor cycle and then concurrently dispatch during a third processor cycle, four of said plurality of instructions buffered by said FIFO buffer; andan execution unit comprising:a plurality of functional units, each of said plurality of functional units executing one of said plurality of instructions dispatched by said dispatch circuit out of the program order, anda register file comprising temporary registers for temporarily storing out-of-order execution results from said plurality of functional units and a register array for storing results from said temporary registers,a plurality of data routing paths, and whereinsaid register file communicates with said plurality of functional units via said plurality of data routing paths for concurrently providing data to more than one of said plurality of functional units and thereby enabling concurrent execution of more than one of said plurality instructions by said plurality of functional units.