Patent ID: 8446765
Filing Date: 2013-05-21
Classification: G11C

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having first and second edge lines opposing to each other; a plurality of address pads arranged along said first edge line; a plurality of memory mats, each including a plurality of normal memory blocks, a spare memory block substituting a normal memory block when said normal block is defective, wherein each of said plurality of normal memory blocks has a plurality of nonvolatile memory cells and is a unit of batch erase, and said plurality of memory mats arranged in a U-shaped area having a hollow portion facing said second edge line on a main surface of said semiconductor substrate; a plurality of column decoders arranged correspondingly to said plurality of memory mats; an analog/logic circuit arranged in said hollow portion; a power supply pad arranged between said analog/logic circuit and said second edge line, said analog/logic circuit including a charge pump circuit that receives power supply voltage from said power supply pad and generates a high potential voltage; a first power supply interconnection supplying power supply voltage to said charge pump circuit from said power supply pad; and a second power supply interconnection supplying power supply voltage to said plurality of column decoder from said power supply pad, different from said first power supply interconnection.