Patent ID: 7218152
Filing Date: 2007-05-15
Classification: H03K

Abstract:
1. A multiplexer comprising: a plurality of dynamic input selection circuits; and control circuitry coupled to the input selection circuits and configured to select one of the input selection circuits to provide a corresponding input at an output of the multiplexer; wherein a clock signal is selectively provided to a first subset of the input selection circuits that includes the selected one of the input selection circuits; and wherein the clock signal is selectively inhibited to a second subset of the input selection circuits that does not include the selected one of the input selection circuits further comprising a plurality of AND gates, wherein each of the AND gates receives the clock signal on a first input and a control signal on a second input, wherein the AND gate is configured to selectively provide the clock signal at an output when the received control signal is asserted, wherein the control signal for a first one of the AND gates comprises a most significant bit of an encoded select signal that is received by the multiplexer and wherein the control signal for a second one of the AND gates comprises an inverse of the most significant bit of the encoded select signal that is received by the multiplexer.