Patent ID: 7272742
Filing Date: 2007-09-18
Classification: G06F

Abstract:
1. A synchronous memory device having an output data bus for outputting a plurality of output data signals in response to a data read command, comprising: a clock input buffer configured to receive a system clock signal and to generate a buffered clock signal; a delay line coupled to the clock input buffer, the delay line configured to receive the buffered clock signal and to generate a delayed clock signal; an output circuit coupled to the delay line, the output circuit including a plurality of output data paths configured to output the plurality of output data signals synchronously with the system clock signal by using the delayed clock signal; and wherein each of the output data paths includes a variable delay circuit and an output buffer coupled to the variable delay circuit, wherein each variable delay circuit is connected to a delay control circuit which determines an amount of delay required for at least one of the plurality of output data paths based upon feedback from the plurality of output data paths, and wherein each delay circuit is configured to provide an independent variable delay to the delayed clock signal to generate a unique delayed clock signal used for clocking data into the respective output buffer.