Patent ID: 6144608
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A first-in/first-out memory, comprising:dual-port memory cells disposed in columns;one output line per column connected to each cell of the column by a read transistor that is controlled by a respective read line;one input line per column connected to each cell of the column through a write transistor that is controlled by a respective write line;a first circular shift register whose outputs respectively control the read lines, the shifting of the first circular shift register being controlled by a complement of a read selection signal; anda second circular shift register whose outputs respectively control said write lines, the shifting of said second circular shift register being controlled by a complement of a write selection signal wherein, the first and second circular shift registers each includes a plurality of interleaved flip-flopswherein, in each plurality of flip-flops, each flip-flop is assigned a respective rank value in a range from a lowest rank value to a highest rank value and the first and second pluralities of flip-flops are each physically linearly arranged such that flip-flops of rank values consecutively descending from the highest rank value are alternately interleaved with flip-flops of rank values consecutively ascending from the lowest rank value,whereby connections between consecutive rank value flip-flops within each plurality of flip-flops have substantially a same length.