Patent ID: 6124622
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate having, on a major surface thereof, a device formation region;a device isolation film comprising:a first layer made of an insulating material and formed on the major surface of the semiconductor subtrate so as to have an opening that surrounds the device formation region;a second layer made of a material different than that of the first layer, and formed on the first layer so as to have an opening that surrounds the device formation region; anda third layer made of a material that is insulative and different from that of the second layer, and formed on the second layer so as to have an opening that surrounds the device formation region; anda MIS transistor in the device formation region, comprising source and drain regions formed so as to be spaced from each other with a channel region interposed in between, and having PN junction ends that are in contact with the first layer of the device isolation film, wherein the MIS transistor comprises:a gate electrode formed on the channel region through a gate oxide film; andsource and drain electrodes formed within the openings of the device isolation film, and electrically connected to the source and drain regions, respectively, while being electrically insulated from the gate electrode, and wherein the second layer of the device isolation film is made of a conductive material, and side surfaces of the second layer facing the device formation region are covered with an oxide film.