Patent ID: 7382022
Filing Date: 2008-06-03
Classification: H01L

Abstract:
1. A boost circuit comprising: a first n-channel fully depleted silicon-on-insulator transistor in which a first pulse is emitted into a gate; a first p-channel fully depleted silicon-on-insulator transistor in which the first pulse is emitted into a gate, connected serially to the first n-channel fully depleted silicon-on-insulator transistor; a second n-channel fully depleted silicon-on-insulator transistor where a gate thereof is connected to a drain of the first n-channel fully depleted transistor; a second p-channel fully depleted silicon-on-insulator transistor, connected serially to the second n-channel fully depleted silicon-on-insulator transistor; a third p-channel fully depleted silicon-on-insulator transistor in which a second pulse which is in an opposite phase to the first pulse is emitted into a gate, a source thereof is connected to a drain of the second n-channel fully depleted silicon-on-insulator transistor; a third n-channel fully depleted silicon-on-insulator transistor in which the second pulse is emitted into a gate, connected serially to the third p-channel fully depleted silicon-on-insulator transistor, and a source thereof being connected to a source of the second n-channel fully depleted silicon-on-insulator transistor; a fourth n-channel fully depleted silicon-on-insulator transistor where a source thereof is connected to the source of the second n-channel fully depleted silicon-on-insulator transistor, and where a gate thereof is connected to a drain of the third n-channel fully depleted transistor; a fourth p-channel fully depleted silicon-on-insulator transistor which is connected serially to the fourth n-channel fully depleted silicon-on-insulator transistor, a gate thereof being connected to a source of the third p-channel fully depleted silicon-on-insulator transistor, a source thereof being connected to the source of the second p-channel fully depleted silicon-on-insulator transistor, and a drain thereof being connected to a source of the first p-channel fully depleted silicon-on-insulator transistor; a first capacitor to which the first pulse is input, connected to the drain of the second n-channel fully depleted silicon-on-insulator transistor; and a second capacitor to which the second pulse is input, connected to a drain of the fourth n-channel fully depleted silicon-on-insulator transistor.