Patent ID: 7835187
Filing Date: 2010-11-16
Classification: G11C

Abstract:
1. A method for boosting seed voltage in a memory device, the method comprising: grounding a first bitline; ramping up a voltage of a second bitline to substantially a predetermined voltage, the second bitline being adjacent to and being capacitively coupled with the first bitline; floating the second bitline; ramping up a voltage of the first bitline to substantially the predetermined voltage; locking in a seed voltage by raising a select gate drain (SGD) voltage to at least a voltage sufficiently high to allow an SGD device coupled to the second bitline to pass the SGD voltage from a drain of the SGD device to a source of the SGD device, and lowering the SGD voltage to at most a voltage sufficiently low to prevent the SGD device from pulling down a voltage of a string coupled to the SGD device if the voltage of the second bitline voltage is lowered from a boosted value or an intermediate value.