Patent ID: 6261918
Filing Date: 2001-07-17
Classification: G03F,H01L

Abstract:
A method for aligning mask layers in the formation of integrated circuits on semiconductor wafers comprising the steps of:a) forming at least one first mark in a reference layer;b) forming at least one second mark in said reference layer at a position substantially perpendicular to said first mark and overlapping said first mark;c) etching said reference layer to create a checkerboard-type pattern from said first and second marks;d) depositing a first predetermined layer over said reference layer to fill in any open recessed portions contained within said checkerboard-type pattern;e) planarizing said first predetermined layer; andf) depositing a second predetermined layer over said reference layer and said first predetermined layer by aligning recessed portions of said first mark located within said reference layer with at least one alignment mark in a predetermined pattern.