Patent ID: 8069300
Filing Date: 2011-11-29
Classification: G06F

Abstract:
1. A solid state storage device controller comprising: a primary DRAM sequencer for generating DRAM signals for a primary DRAM; a secondary DRAM sequencer for generating DRAM signals for an expansion DRAM; at least one non-volatile memory sequencer for generating non-volatile memory signals for a plurality of non-volatile memory devices; and a plurality of non-volatile memory communication channels that couple the at least one non-volatile memory sequencer to the plurality of non-volatile memory devices, each communication channel configured to couple a different group of non-volatile memory devices of the plurality of non-volatile memory devices wherein, in response to an expansion mode, at least one of the plurality of non-volatile communication channels couples only the expansion DRAM to the secondary DRAM sequencer; and an interface for coupling the solid state storage device to an external system.