Patent ID: 7704825
Filing Date: 2010-04-27
Classification: G11C,H01L,Y10S

Abstract:
1. A method of fabricating a memory, comprising steps of: forming a first conductive type first impurity region functioning as a first electrode of a diode included in a memory cell by introducing a first conductive type impurity into a memory cell array region on the main surface of a semiconductor substrate, wherein said step of forming said first impurity region includes steps of forming a low-concentration impurity region and forming a high-concentration impurity region so as to reach a deeper region than said low-concentration impurity region; and forming a plurality of second conductive type second impurity regions each functioning as a second electrode of said diode with respect to one said first conductive type first impurity region by introducing a second conductive type impurity into prescribed regions of the surface of said first impurity region.