Patent ID: 6274483
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method of creating interconnecting conductive lines and conductive vias in a layer of insulating material, comprising the steps of:providing a semiconductor substrate;depositing a layer of dielectric over a surface of said substrate;planarizing a surface of said layer of dielectric;creating trenches or openings in said layer of dielectric for deposition of metal thereby creating a pattern of interconnect lines or interconnect vias;sputter etching said created trenches or openings thereby faceting sidewalls of said trenches or openings by developing an ever-increasing facet or incline of sidewalls of said trenches or openings;depositing a barrier layer over a surface of said layer of dielectric thereby including inside surfaces of said trenches or openings;depositing a seed layer over a surface of said barrier layer;depositing a layer of copper over a surface of said seed layer; andpolishing said layer of copper thereby forming a pattern of interconnect lines or interconnect vias.