Patent ID: 6972980
Filing Date: 2005-12-06
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device including a word line, a bit line and a plate line; a sense amplifier and a precharge circuit connected to the bit line; a plate line driving portion having a control transistor that has a control electrode and a main current path and is connected to a plate line; a selection transistor that has a control electrode and first and second main current path ends disposed at both ends of the main current path, the control electrode being connected to the word line and the first main current path end being connected to the bit line; a ferroelectric capacitor that has first and second electrodes, the first electrode being connected to the second main current path end and the second electrode being connected to the plate line; a first power supply that is connected to the sense amplifier and the precharge circuit; a second power supply that is connected to the plate line driving portion, disposed in a separate system from the first power supply and is insulated from the first power supply at the time of non-operation; a first ground line that is connected to the sense amplifier and the precharge circuit; and a second ground line that is connected to the plate line driving portion and insulated from the first ground line: wherein the semiconductor memory device includes a first semiconductor region where a main current path of the selection transistor is formed; and a second semiconductor region where a main current path of the control transistor is formed and that is insulated through an insulating film from the first semiconductor region.