Patent ID: 6714046
Filing Date: 2004-03-30
Classification: G09G,H03K

Abstract:
A level shifter, comprising:a first capacitor having a first end and a second end, a low-amplitude logic signal being input to the first end of the first capacitor; a first offset circuit to apply a first offset voltage to the second end of the first capacitor; a second capacitor having a first end and a second end, the low-amplitude logic signal being input to the first end of the second capacitor; a second offset circuit to apply a second offset voltage to the second end of the second capacitor; and first and second switching elements connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, the first switching element being connected to the second end of the first capacitor, the second switching element being connected to the second end of the second capacitor, the first switching element being a P-channel transistor and the second switching element being an N-channel transistor, the first offset circuit being implemented by a P-channel transistor and an N-channel transistor connected in series between the supply line of the power supply voltage and the supply line of the reference voltage, a voltage at a node therebetween serving as the first offset voltage and as gate voltages of the P-channel transistor and the N-channel transistor, and the second offset circuit being implemented by a P-channel transistor and an N-channel transistor connected in series between the supply line of the power supply voltage and the, supply line of the reference voltage a voltage at a node therebetween serving as the second offset voltage and as gate voltages of the P-channel transistor and the N-channel transistor.