Patent ID: 9146846
Filing Date: 2015-09-29
Classification: G06F

Abstract:
1. A memory comprising: a set of memory cells arranged as a plurality of rows and one or more banks; address decode logic having programmable physical address mapping, the address decode logic to select a bank and a row of the selected bank for a memory access based on the programmable physical address mapping and a physical address associated with the memory access, the address decode logic comprising: access analysis logic to determine an access pattern of memory accesses to the memory, to select a physical address mapping based on the access pattern, and to program the address decode logic to implement the selected physical address mapping, wherein the access analysis logic is to select a column-major address mapping as the physical address mapping responsive to the access pattern identifying a stride patterns greater than one and to select a row-major address mapping as the physical address mapping responsive to the access pattern identifying a stride, pattern equal to one.