Patent ID: 6493284
Filing Date: 2002-12-10
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a plurality of sub-array blocks; wherein each of the sub-array blocks includes a plurality of sub-arrays; a plurality of main wordlines arranged through the sub-arrays; a plurality of sub-wordlines arranged in each of the sub-arrays, corresponding to each of the main wordlines; and driving means having a plurality of sub-wordline drive units; wherein each of the sub-wordline drive units drives one of the sub-wordlines in each of the sub-arrays corresponding to a selected main wordline in response to sub-wordline activation signals; and wherein the sub-wordline activation signals are irregularly arranged in the sub-wordline drive units of each of the sub-array blocks such that power consumption is uniformly distributed when each of the sub-wordline activation signals is enabled.