Patent ID: 6924760
Filing Date: 2005-08-02
Classification: H03M

Abstract:
1. A digital to analog converter (DAC) comprising: a first capacitance and a second capacitance configured in a first switching circuit; wherein the first switching circuit is configured as an input capacitance of a switched capacitor integrator; wherein the first switching circuit is operable to redistribute charge stored on the first capacitance, to be shared substantially equally by the first capacitance and the second capacitance; wherein the first switching circuit is further operable to redistribute charge stored on the second capacitance, to be shared substantially equally by the first capacitance and the second capacitance; wherein applying a first-pass switching sequence to the first switching circuit for converting a binary number results in a first voltage across the first capacitance and across the second capacitance; wherein applying a complementary switching sequence corresponding to the first-pass switching sequence to the first switching circuit for converting the binary number results in a second voltage across the first capacitance and across the second capacitance; wherein, in applying the first-pass switching sequence, the first capacitance is charged to a conversion level a first number of times and the second capacitance is charged to the conversion level a second number of times; wherein in applying the complementary switching sequence, the first capacitance is charged to the conversion level the second number of times and the second capacitance is charged to the conversion level the first number of times; wherein, in applying the first-pass switching sequence, if the first capacitance is charged to the conversion level for a respective bit of the binary number then the second capacitance is not charged to the conversion level for the respective bit, and in applying the complementary switching sequence the first capacitance is not charged to the conversion level for the respective bit, but the second capacitance is; wherein, in applying the first-pass switching sequence, if the second capacitance is charged to the conversion level for the respective bit, then the first capacitance is not charged to the conversion level for the respective bit, and in applying the complementary switching sequence the second capacitance is not charged to the conversion level for the respective bit, but the first capacitance is; wherein the first-pass switching sequence and the corresponding complementary switching sequence form a conversion sequence for the binary number, wherein for each bit of the binary number, charge is redistributed between the first capacitance and the second capacitance; wherein an integrated sum of the first voltage and the second voltage comprises a DAC output voltage free of odd-order errors, wherein if the first voltage is obtained from the first capacitance then the second voltage is obtained from the second capacitance, and if the first voltage is obtained from the second capacitance then the second voltage is obtained from the first capacitance; wherein performing the conversion sequence a specified number of times and integrating the DAC output voltage at the end of each conversion sequence results in a final DAC output voltage; wherein the final DAC output voltage is free of odd-order capacitor mismatch errors; and wherein the final DAC output voltage is free of second-order capacitor mismatch errors for up to a specified number of bits.