Patent ID: 8935489
Filing Date: 2015-01-13
Classification: G06F,Y02D

Abstract:
1. A method for processing memory references in a system which includes multiple processor cores, the method comprising: receiving a first plurality of memory references from a first processor core; receiving, interleaved with said first plurality of memory references, a second plurality of memory references from at least a second processor core, each of said first plurality of memory references and said second plurality of memory references causing, in a given memory bank, a selected one of a page-hit, an empty access, and a page-miss, said page-hit being a memory access to an open page of a memory bank, said empty-access being a memory access to a memory bank with no open page, and said page-miss being a memory access to a closed page of a memory bank that has another page that is open; determining whether said first plurality of memory references would have caused fewer page-misses if the second plurality of memory references were not interleaved with the first plurality of memory references; and in response to determining that said first plurality of memory references would have caused fewer page-misses if the second plurality of memory references were not interleaved with the first plurality of memory references, time-multiplexing the processing of a third plurality of memory references received from the first processor core such that a first block of at least two consecutive memory references of the third plurality of memory references are processed without being interleaved with other memory references received from said at least second processor core.