Patent ID: 6635936
Filing Date: 2003-10-21
Classification: H01L,Y10S

Abstract:
A layout for an SRAM device having source regions drain regions formed in adjacent active areas in a doped semiconductor substrate, a first wordline conductor parallel to a second wordline conductor, and contacts comprising:said active areas being formed in a doped semiconductor substrate with a layout with 90Â° transitions in the profile of the active area in critical locations where said source regions are formed, means formed in said silicon substrate between STI trench isolation regions filled with STI isolation material with each of said mesas having a flat top surface and sidewalls with said flat top having edges between said sidewalls and said flat top, a dielectric layer formed above said active areas covering said STI regions and covering said edges of said flat top surfaces of said mesas and covering said edges between said sidewalls and said flat tops of said mesas, said active areas crossing said first wordline conductor and said second wordline conductor at right angles thereto, with double back patterns including transverse regions of said active areas located between said first wordline conductor said second wordline conductor and with said transverse regions extending in parallel to said first wordline conductor said second wordline conductor where said active areas cross said first wordline conductor and said second wordline conductor, at least one of said first and second wordline conductors being formed above said active area transverse to said active area, a source region formed in said critical locations in said active areas juxtaposed with said wordline conductor forming pass gate transistors while simultaneously forming drain regions in said active areas juxtaposed with said wordline conductor on the opposite side from said source region to form a pass gate transistors, said source regions having sidewalls, said contacts being aligned with said mesas with lower ends of said contacts having a narrower width than the flat top surface of said mesas centered over said mesas and isolated from a <110> silicon (Si) plane of said substrate by the STI isolation material and the dielectric material covering the upper edges of the mesa and the upper edges of the sidewalls of the mesa, and at least one of said contacts to said drain region being formed extending down from one of said wordline conductors through said dielectric layer to said drain region.