Patent ID: 7433233
Filing Date: 2008-10-07
Classification: G11C,H01L

Abstract:
1. A method of operating an integrated circuit having a three-dimensional memory array including at least two planes of memory cells, said memory cells comprising thin film switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of: biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and then capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell; wherein the biasing step comprises: (a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string; (b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and (c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string, said turning on step comprising driving the word lines associated with any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string to a first passing voltage sufficient to turn on both programmed and unprogrammed memory cells to bias the half-selected memory cell channel to the first voltage; and then (d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage, said decoupling step comprising driving the unselected word lines associated with the unselected NAND string to a second passing voltage different than the first passing voltage, said second passing voltage chosen such that both programmed and unprogrammed memory cells in the unselected NAND string are turned off, and such that voltage stress across unselected memory cells in a selected NAND string is reduced.