Patent ID: 8171445
Filing Date: 2012-05-01
Classification: G06F

Abstract:
1. A method of designing a semiconductor integrated circuit, the method comprising: allocating, via a computer, a rough wiring path to a wiring region having a plurality of layers; estimating, via the computer, the number of vias generated in the rough wiring path; calculating, via the computer, necessary wiring resource consuming information indicating a number of adjacent wiring paths which can be consumed when a multi-cut via is used; calculating, via the computer, a wiring congestion degree for each of a plurality of rectangular regions obtained by dividing the wiring region; equalizing, via the computer, the wiring congestion degree including a provision of the multi-cut via; assigning, via the computer, the rough wiring path; providing, via the computer, a detailed wiring in the wiring region by using the wiring resource consuming information; and replacing, via the computer, a via connecting the wiring region with the multi-cut via.