Patent ID: 6458657
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method of fabricating a gate over a substrate which comprising a device structure, the device structure including a source/drain region, a gate dielectric layer, a first gate conductive layer, and a first dielectric layer encompassing the first gate conductive layer, the method comprising:forming a plurality of second dielectric layers on the first dielectric layer and the first gate conductive layer; forming a first etching mask on a topmost second dielectric layer, the etching mask comprising a first opening expose a portion of the topmost second dielectric layer; performing an anisotropic etching step to form a second opening that exposes the first gate conductive layer performing an isotropic etching step on the second dielectric layers exposed within the second opening with the etching mask remaining on the topmost second dielectric layer, so that a third opening having an uneven surface since the second dielectric layers have different etching rates from each other is formed; removing the first etching mask.