Patent ID: 8495438
Filing Date: 2013-07-23
Classification: G06F,G11C,H03M

Abstract:
1. A method, comprising: storing a data value in a memory word comprising one or more memory cells; storing an inversion condition bit in a memory location operably associated with the memory word, wherein the inversion condition bit indicates if the associated memory word currently stores an actual data value or an inverted data value; providing an inversion status bit that comprises information associated with an inversion status of the memory array; providing an address counter value from an address counter configured to advance through a plurality of address counter values, so that each memory word in the memory array is associated with a particular address counter value; reading the data value and the inversion condition bit from the memory location associated with the address counter value; inverting the data value inverting the inversion condition bit; re-writing the inverted data value and the inverted inversion condition bit to the memory location associated with the address counter value; incrementing the address counter value; and toggling the inversion status bit and resetting the address counter to the lowest numbered memory address once the memory address counter has addressed the plurality of memory addresses; providing a control circuitry by which an error correction code (an ECC) can be implemented; storing at least one ECC syndrome bit and a parity bit in a first additional memory location; and a read operation of the method comprising: