Patent ID: 9147693
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A memory array, comprising: a substantially vertical conductive pillar; a plurality of first memory cells on a first side of the substantially vertical conductive pillar coupled in series by the substantially vertical conductive pillar, each first memory cell comprising a respective portion of a first charge trap adjacent to the first side of the substantially vertical conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap; a plurality of second memory cells on a second side of the substantially vertical conductive pillar, opposite to the first side of the substantially vertical conductive pillar, coupled in series by the substantially vertical conductive pillar, each second memory cell comprising a respective portion of a second charge trap adjacent to the second side of the substantially vertical conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap; and a single select transistor that selectively electrically couples both the plurality of first memory cells and the plurality of second memory cells to a data line; wherein each first control gate is electrically isolated from each second control gate; and wherein respective ones of the first memory cells of the plurality of first memory cells are respectively at same vertical levels as respective ones of the second memory cells of the plurality of second memory cells.