Patent ID: 6647488
Filing Date: 2003-11-11
Classification: G06F

Abstract:
A processor comprising:instruction code holding means for fetching and holding a basic instruction code capable of issuing an instruction per cycle or an expanded instruction code not capable of issuing an instruction per cycle; a first instruction decoder for issuing an instruction by decoding the basic instruction code held in said instruction code holding means; a second instruction decoder for decoding the expanded instruction code held in said instruction code holding means, and for issuing one instruction per cycle by translating said expanded instruction code into a sequence of multiple instructions; a counter for counting the number of instructions to be issued by said second instruction decoder, and for outputting a signal indicating that said expanded instruction code is being executed; instruction selecting means for selecting the instruction issued from said first instruction decoder when executing said basic instruction code and the instruction issued from said second instruction decoder when executing said expanded instruction code; execution instruction holding means for holding the instruction output from said instruction selecting means; and instruction executing means for executing the contents of the instruction held in said execution instruction holding means.