Patent ID: 6173023
Filing Date: 2001-01-09
Classification: H04J

Abstract:
Synchronization equipment comprising:a timing source interface section for interfacing with multiple kinds of timing sources;a timing source switching section for outputting one timing source by switching its input between a plurality of timing sources which have been selected in said timing source interface section and assigned prescribed priority;a PLL section for generating an equipment clock by synchronizing to the timing source selected and output from said timing source switching section;a failure detection section for detecting a failure of each of said plurality of timing sources assigned said prescribed priority;a failure monitoring section for monitoring failure detection information from said failure detection section, and for outputting in the event of detection of a timing source failure a timing source switching control signal directing switching to a timing source having the highest priority among the timing sources other than the failure-detected timing source;an SSMB interface section for interfacing with an SSMB bus;an SSMB-to-quality conversion section for converting SSMB information supplied from said SSMB interface section into corresponding synchronization quality information;a timing source selection section for outputting a timing source switching control signal based on the synchronization quality information supplied from said SSMB-to-quality conversion section; anda selection section for selecting either the timing source switching control signal from said failure monitoring section or the timing source switching control signal from said timing source selection section in accordance with an instruction from prescribed selection instruction means.