Patent ID: 8997033
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A method of compiling an integrated circuit design, comprising: with a computer-aided design tool implemented on computing equipment, identifying a plurality of dynamic configuration regions in the integrated circuit design; for each identified dynamic configuration region of the plurality of dynamic configuration regions in the integrated circuit design, generating a partial configuration file; combining at least two partial configuration files to obtain a single partial configuration file for at least two respective dynamic configuration regions in the plurality of dynamic configuration regions; for each identified dynamic configuration region of the plurality of dynamic configuration regions, generating a settings file prior to generating the partial configuration file; and generating a full-chip binary configuration file based on the integrated circuit design prior to combining the at least two partial configuration files, wherein generating the partial configuration file comprises combining at least a portion of the full-chip binary configuration file and the settings file to obtain the partial configuration file for each identified dynamic configuration region.