Patent ID: 7545896
Filing Date: 2009-06-09
Classification: H04L

Abstract:
1. An electronic circuit in a first clock domain, the electronic circuit capable of: receiving a signal sequence; outputting a first signal from the signal sequence to a plurality of other clock domains in dependence upon a clock signal of the first clock domain; receiving from each of the plurality of other clock domains an output of the first signal in dependence upon a clock signal of the other clock domain; outputting a next signal from the signal sequence in dependence upon the clock signal of the first clock domain, wherein the next signal is output upon detecting that all of the plurality of other clock domains have output the first signal; wherein detecting that all of the plurality of other clock domains have output the first signal by: generating an update signal when all of the plurality of other clock domains have output the first signal; and gating the next signal from the signal sequence to be output in dependence upon the update signal; and further wherein the electronic circuit is further capable of synchronizing at least one of the outputs received from the plurality of other domains with the clock signal of the first domain using a circuit capable of reducing metastability in the synchronized output.