Patent ID: 8836393
Filing Date: 2014-09-16
Classification: H03L

Abstract:
1. A method to synchronize a clock signal comprising: determining a first and a second phase difference between a first signal and a second signal, the second phase difference being a complement of the first phase difference; determining an initial amount of enabled delay; when the second phase difference is less than the first phase difference and when the initial amount of enabled delay is greater than the second phase difference, selecting the second phase difference to determine a collective amount of delay; and reducing the second phase difference by the collective amount to adjust the first signal by shifting a phase of the first signal by the collective amount during a phase comparison cycle; wherein the collective amount is determined by one or more feedback cycles and based at least in part on a plurality of delay adjustments, each delay adjustment associated with a delay adjustment value and a phase adjustment window, the collective amount determined by iteratively shifting, for the plurality of delay adjustments, the first signal by each delay adjustment value when the associated delay adjustment is enabled and the selected phase difference is outside the associated phase adjustment window and updating the selected phase difference based on each shifting.