Patent ID: 6333725
Filing Date: 2001-12-25
Classification: G09G

Abstract:
A data interfacing apparatus for interfacing RGB data of a frame memory means to each of an upper address electrode driving means for driving odd-numbered electrodes in a direction of row of an AC type PDP system and a lower address electrode driving means for driving even-numbered electrodes in the direction of row of the AC type PDP system, comprising:a first provisional storing means including N number of M-bits shift registers, input terminals of which are connected to output terminals of the frame memory by N number of lines one-to-one;a second provisional storing means including N number of M-bits shift registers, input terminals of which are connected to the output terminals of the frame memory by the N number of lines one-to-one; anda shift signal generating means including a first means for generating M number of shift signals by using a first signal indicating a start of every horizontal line and a second signal which is a system reference clock; and a second means for alternately providing M number of shift clocks through first and second output terminals thereof to the first and second provisional storing means by using a third signal whose logical level is alternately inverted by the horizontal line and the M number of shift clocks,wherein in response to the M number of shift clocks, each of the first and second provisional storing sections receives in parallel N-bits RGB data from the frame memory M times are every horizontal line period while shifting the received N-bits RGB data in respective M-bits shift register.