Patent ID: 6653693
Filing Date: 2003-11-25
Classification: H01L,H03K

Abstract:
A semiconductor integrated circuit device comprising:an internal circuit section in which an integrated circuit is formed, the integrated circuit including at least MOS transistors of same conductivity type, a plurality of terminal pads arranged in a direction, including at least a power source pad which receives a power voltage and signal pads, and a plurality of buffer regions arranged laid out in a line, wherein a switch MOS transistor is formed in at least one of said plurality of buffer regions and is electrically connected between the power source pad and the internal circuit when said switch MOS transistor is conductive, and buffer circuits are formed in others of said plurality of buffer regions and connected to the signal pads, respectively, each buffer circuit including at least one of an input buffer circuit and an output buffer circuit, the input buffer circuit connected between the internal circuit and one of the signal pads and transfers a signal from the one signal pad to the internal circuit, and the output buffer circuit connected between the internal circuit and the one signal pad and transfers a signal from the internal circuit to the one signal pad, wherein the switch MOS transistor has a threshold voltage whose absolute value is higher than that of each of the MOS transistors in said internal circuit section.