Patent ID: 6041427
Filing Date: 2000-03-21
Classification: G06F,Y10S

Abstract:
A scan testable circuit arrangement, comprising:a bus;a plurality of logic circuits, each logic circuit having a plurality of scan test ports and a plurality input/output ports;a first plurality of switches, each having a first terminal coupled to a predetermined signal line of the bus and a second terminal coupled to a respective one of the scan test ports of the logic circuits;a second plurality of switches, each having a first terminal coupled to a predetermined signal line of the bus and a second terminal coupled to a respective one of input/output ports of the logic circuits;a plurality of command decoders, coupled to the bus to receive bus commands and coupled to the gates of the first and second plurality of switches, configured and arranged to couple the scan test ports to the bus for a first operational mode responsive to a first set of the bus commands, and couple the input/output ports to the bus for a second operational mode responsive to a second set of commands anda buffer circuit arranged to couple the bus to a local bus; anda bypass circuit coupled to the bus and arranged to couple the bus to the local bus and bypass the buffer circuit during the first operational mode.