Patent ID: 8940604
Filing Date: 2015-01-27
Classification: G11C,H01L

Abstract:
1. A method, comprising: manufacturing, on a semiconductor substrate, an integrated circuit that includes a nonvolatile memory comprising memory cells, each including a charge accumulation transistor and a selection transistor, the manufacturing including: implanting a doped first isolation layer in the substrate; forming, in the substrate, conductive trenches reaching the isolation layer, the conductive trenches forming gates of selection transistors of memory cells; forming, in the substrate, second isolation layers respectively isolating the conductive trenches from the substrate; forming, in the substrate, isolation trenches perpendicular to the conductive trenches, and reaching the isolation layer; forming, on the substrate, conductive lines parallel to the conductive trenches, the conductive lines forming control gates of charge accumulation transistors of the memory cells; and implanting doped regions on opposite sides of the conductive trenches and on opposite sides of the conductive lines parallel to the conductive trenches, the doped regions forming drain and source regions of the charge accumulation transistors and of the selection transistors; the isolation trenches and the conductive trenches delimiting a plurality of mini wells in the substrate, the mini wells being electrically isolated from each other, each being configured to have a floating electrical potential and including two of the memory cells.