Patent ID: 8806395
Filing Date: 2014-08-12
Classification: G06F,H01L

Abstract:
1. A method of fabricating an integrated circuit including a bit cell comprising: determining a size of each transistor in a first bit cell design, each of the transistors having a threshold voltage; producing a second bit cell design based on the first bit cell design, the second bit cell design having target transistors, the target transistors including at least one deeply depleted channel (DDC) transistor, the second bit cell design having initial threshold voltage value assigned to each of the target transistors; determining targets for a read margin, a write margin, a read current and a cell leakage for the second bit cell, such targets defining set of design constraints; optimizing the threshold voltage values of the target transistors using an optimization method based upon solving objective functions within the set of design constraints; selectively doping a semiconductor substrate to form a highly-doped screening region over which a transistor gate will be formed; selectively doping the semiconductor substrate in regions that are associated with the target transistors to dopant concentrations that set the threshold voltage values for each of the target transistors to the desired range of values; and forming a substantially undoped semiconductor layer above the highly doped screening region.