Patent ID: 9070624
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A method, comprising: forming a polysilicon layer on a semiconductor substrate; etching the polysilicon layer to form a first region having a first height from a top surface of the semiconductor substrate and a second region having a second height from the top surface of the semiconductor substrate, wherein the second height is less than the first height; forming a first gate structure on the semiconductor substrate, wherein the first gate structure is formed of the second region of the etched polysilicon layer and is disposed over an isolation region of the substrate; forming a sacrificial gate structure on the semiconductor substrate adjacent the first gate structure, wherein the sacrificial gate structure is formed using the first region of the etched polysilicon layer and is disposed over an active region of the substrate adjacent the isolation region; and forming a dielectric layer overlying the first gate structure and the sacrificial gate structure, wherein the dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness above a top surface of the sacrificial gate structure, wherein the second thickness is less than the first thickness; after forming the dielectric layer, performing a planarization process on the dielectric layer to expose the top surface of the sacrificial gate structure, wherein after performing the planarization process a portion of the dielectric layer having a third thickness remains above the first gate structure; after the planarization process, removing the sacrificial gate structure to form a trench; forming a metal gate structure in the trench; and forming a first contact to the first gate structure and forming a second contact to the metal gate structure.