Patent ID: 6115768
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A memory control system employing pipeline-controlled bus comprising: a main memory including a plurality of banks which are composed of RAM (Random Access Memory); two or more requesters each of which includes an MPU or an I/O means which outputs a request that is addressed to a bank of a main memory; and a pipeline-controlled system bus which connects the main memory and each of the requesters, wherein:each of the requesters includes:a request sending control means for receiving the request from the MPU or the I/O means, executing a system bus acquisition request to a system bus arbitration means of the requester itself and system bus arbitration means of other requesters after confirming that the bank to which the request has been addressed is not busy for the request by referring to a bank busy status of the bank which is supplied from a bank busy management means of the requester, and sending the request to the main memory via the pipeline-controlled system bus if the system bus acquisition request could acquire the right to use the pipeline-controlled system bus in consequence of distributed arbitration which is executed by the system bus arbitration means which are provided in each of the requesters;the system bus arbitration means for receiving the system bus acquisition requests from the request sending control means of the requesters, executing the distributed arbitration between the system bus acquisition requests, informing a request type and a bank number concerning a system bus acquisition request that could acquire the right to use the pipeline-controlled system bus in consequence of the distributed arbitration to the bank busy management means of the requester, and informing the request sending control means of the requester that the requester itself could acquire the right to use the pipeline-controlled system bus if the system bus acquisition request from the requester could acquire the right to use the pipeline-controlled system bus in consequence of the distributed arbitration; andthe bank busy management means for storing the bank busy statuses of the banks in the main memory with regard to each of the request types, managing the bank busy statuses of the banks based on the request type and the bank number which are informed by the system bus arbitration means of the requester, and informing the bank busy statuses to the request sending control means,and the main memory includes a bank control means for controlling access to the banks according to a request type and an address which are included in the request that is supplied from the request sending control means of the requester via the pipeline-controlled system bus.