Patent ID: 7242211
Filing Date: 2007-07-10
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a wrapper serial input, a wrapper serial output, and wrapper control inputs including a clock input, a shift input, a capture input, an update input, and a reset input; B. input circuitry having a serial input coupled to the wrapper serial input, select serial outputs selectively coupled to the wrapper serial input, and link control inputs; C. output circuitry having a serial output coupled to the wrapper serial output, select serial inputs selectively coupled to the serial output, and link control inputs; D. a link instruction circuit having a serial input and a serial output coupled in series with the wrapper serial input and the wrapper serial output, control inputs connected to the wrapper control inputs, link control outputs connected to the link control inputs, a first enable output, a second enable output, and an embedded enable output, and an instruction register connected to the serial input, the link control outputs, the enable outputs, and selectively coupled to the serial output; E. a first IP core having a first wrapper, the first wrapper having a serial input connected to a select serial output, a serial output connected to a select serial input, a first enable input connected to the first enable output, and control inputs connected to the wrapper control inputs; and F. test architecture circuitry, including: