Patent ID: 6571266
Filing Date: 2003-05-27
Classification: G06F

Abstract:
In a floating-point multiply accumulate unit for performing the accumulate operation (A*B)+C, wherein A, B, and C each comprise an m-bit mantissa and an exponent, and an (A*B) result comprises a â€œ2m+1â€ -bit mantissa and an exponent, a method of adding C to the (A*B) result to acquire a final mantissa result that is rounded to a lower precision, comprising:comparing the exponents of (A*B) and C to determine whether there is an overlapping range of the (A*B) and C mantissas; transferring any part of the C mantissa which exceeds a range of the (A*B) mantissa to a CHI register; shifting any part of the C mantissa which overlaps the range of the (A*B) mantissa, so as to align the bits of the (A*B) and C mantissas according to their respective magnitudes; adding the shifted part of the C mantissa to the (A*B) mantissa to generate a Temp. Result; if a portion of the C mantissa was transferred to the CHI register, shifting one or more least significant bits corresponding to a number of bits transferred to the CHI register out of the Temp. Result; merging with a merge mask the bits of the C mantissa which were transferred to the CHI register with one or more most significant bit positions of the shifted Temp. Result to generate an accumulated mantissa result; acquiring a leading bit (L) from a selected one of an Lbit value of the CHI register and an Lbit value of the Temp. Result based on the bit value of the merge mask corresponding to the Lbit position; and rounding the mantissa result to the lower precision using one or more rounding parameters including said leading bit (L).