Patent ID: 6320804
Filing Date: 2001-11-20
Classification: G11C

Abstract:
An integrated semiconductor memory which can be subjected to a memory cell test for determining operative and defective memory cells, the integrated semiconductor memory comprising:addressable normal memory cells;addressable redundant memory cells for replacing one of said normal memory cells; anda test circuit including:a device for determining addresses of defective ones of said normal memory cells,a memory unit for storing addresses of the defective ones of said normal memory cells, said memory unit having a control input for controlling a storing operation of said memory unit and an output for outputting a content of said memory unit, anda preprocessing device including at least one memory device for storing a fixed number of addresses of defective ones of said normal memory cells, said preprocessing device having a comparison device for a comparison between the addresses stored in said memory device, said preprocessing device having an output for outputting an output signal in accordance with a result of the comparison, said output of said preprocessing device connected to said control input of said memory unit.