Patent ID: 6026036
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A synchronous semiconductor memory device operating in synchronization with an external clock signal, comprising:a memory cell array;a redundant memory cell array;a clock buffer generating first and second internal clock signals complementary to each other in response to said external clock signal;a first latch circuit latching an address signal in response to said first internal clock signal;a predecoder generating a predecode signal in response to the address signal from said first latch circuit;a second latch circuit latching the predecode signal from said predecoder in response to said second internal clock signal;a decoder accessing said memory cell array in response to the predecode signal from said second latch circuit;a program circuit programmable of a defective address and generating an enable signal when the address signal from said first latch circuit designates the programmed defective address;a third latch circuit latching said enable signal in response to said second internal clock signal; anda redundancy decoder accessing said redundant memory cell array in response to the enable signal from said third latch circuit.