Patent ID: 6580660
Filing Date: 2003-06-17
Classification: G11C

Abstract:
A digital circuit for synchronizing a plurality of sets of digital data signals, with each of the sets of digital data signals having a clock signal, the circuit comprising:a plurality of dual-port memories, each memory being independently associated with one of the sets of digital data signals, each memory having write address inputs, read address inputs, write data inputs, a write clock input, and read data outputs, the write data inputs of each dual-port memory being coupled with one of the sets of digital data signals; a plurality of write address counters, each counter being independently associated with one of the dual-port memories, each counter being configured to drive the write address inputs of the associated dual-port memory, each counter having a clock input driven by the clock signal associated with the set of digital data signals that drive the write data inputs of the associated dual-port memory, each counter having a reset signal input that, when activated, resets the value of the counter; a plurality of programmable delay registers, each delay register being independently associated with one of the dual-port memories; and a plurality of arithmetic units, each arithmetic unit being independently associated with one of the dual-port memories, each arithmetic unit having a first input and a second input, each arithmetic unit configured to subtract the value of the first input from the value of a second input, each arithmetic unit having an output representing the difference between the first and second inputs, the first input of each arithmetic unit being driven by the programmable delay register associated with the memory that is associated with the arithmetic unit, the second input of all arithmetic units being driven by one of the write address counters, the output of each arithmetic unit driving the read address inputs of the memory associated with the arithmetic unit.