Patent ID: 6734459
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A semiconductor memory cell, comprising:a substrate having a surface; a transistor including a doped region disposed in said substrate; an insulation layer disposed on said substrate and on said transistor; an electrically conductive contact extending from said doped region through said insulation layer; a conductive contact layer disposed on said insulation layer, said conductive contact layer having a first surface facing said surface of said substrate, having a second surface averted from said surface of said substrate, and having a lateral surface connecting to said first surface of said conductive contact layer and to said second surface of said conductive contact layer; said electrically conductive contact touching said lateral surface of said conductive contact layer; a capacitor including a bottom capacitor electrode disposed above said insulation layer, a capacitor insulator disposed on said bottom capacitor electrode, and a top capacitor electrode disposed on said capacitor insulator; and said electrically conductive contact conductively connecting, via said conductive contact layer, said bottom capacitor electrode to said doped region disposed in said substrate.