Patent ID: 7714668
Filing Date: 2010-05-11
Classification: H03L

Abstract:
1. A PLL circuit comprising: a voltage-controlled oscillator having a plurality of oscillation frequency bands; an oscillation frequency band selection circuit for detecting a required oscillation frequency band from the plurality of oscillation frequency bands of the voltage-controlled oscillator; a variable frequency divider for dividing a frequency of a PLL output signal, which is an output signal from the voltage-controlled oscillator, by a frequency divisor number to output a PLL frequency-divided signal; a TDC circuit for detecting and outputting a phase difference between a predetermined reference signal and the PLL frequency-divided signal from the variable frequency divider; and a frequency counter for counting the number of rising edges of the PLL frequency-divided signal from the variable frequency divider for a specified period of time and outputting the count number, wherein the oscillation frequency band selection circuit detects and selects an optimum oscillation frequency band corresponding to a predetermined PLL output frequency by using a signal indicating the phase difference between the reference signal and the PLL frequency-divided signal detected by the TDC circuit.