Patent ID: 7375574
Filing Date: 2008-05-20
Classification: H03K

Abstract:
1. A semiconductor device including a differential level converter circuit that receives a first signal and a phase-inverted signal of the first signal and outputs a second signal of a larger amplitude than an amplitude of the first signal, wherein the differential level converter circuit comprises a first MISFET pair of a first conductivity type for receiving the first signal and the phase-inverted signal; of the first signal; a second MISFET pair of the first conductivity type for improving a withstand voltage of the first MISFET pair; a third MISFET pair of a second conductivity type having cross-coupled gates for latching the second signal to output; and a forth MISFET pair of the second conductivity type for ensuring the withstand voltage of the first MISFET pair; wherein a film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the first MISFET pair; wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair; wherein an absolute value of a threshold voltage of the second MISFET pair is smaller than an absolute value of a threshold voltage of the third MISFET pair; wherein an absolute value of a threshold voltage of the first MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair; wherein a drain of one of the fourth MISFET pair is coupled to a drain of one of the first MISFET pair, and the first signal is inputted to a gate of the one of the fourth MISFET pair; and wherein a drain of another of the fourth MISFET pair is coupled to a drain of another of the first MISFET pair, and the phase-inverted signal of the first signal is inputted to a gate of the another of the fourth MISFET pair.