Patent ID: 7613850
Filing Date: 2009-11-03
Classification: G06F

Abstract:
1. A computer system for controlling ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered memory read responses, the system comprising: a memory and/or cache memory including a memory/cache controller; an I/O device for communicating memory access requests from system data sources, where each memory access request is associated with a configured ordering class value; wherein the I/O device comprises at least one register for storing ordering class values provided by the system data sources with the memory access requests; and a memory controller I/O interface for processing each memory access request communicated through the I/O device to the memory in coordination with the ordering class protocol, comprising: an incoming request buffer for storing incoming memory access requests from the I/O device in a received order, wherein the memory access requests include an ordering class value; and a next request selector and ordering table with rules for implementing the ordering class protocol, wherein the next request selector processes each stored memory access request based on its ordering class value, a rule from the table associated with said ordering class value and a listing of ordering dependencies for the stored memory access requests to control timing of communicating the memory access request to the connected memory.