Patent ID: 6667235
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device wherein a wiring pattern, one end of which is connected electrically to an electrode terminal formed on an electrode terminal forming surface of a semiconductor element, and the other end of which forms a land connected to an externally connecting terminal, is formed over the semiconductor, comprising:forming an insulation coating over the electrode terminal forming surface, exposing the electrode terminal; forming a metal film on the insulation coating and the electrode terminal; forming a resist pattern on the metal film in such a way that sites for forming the wiring pattern are exposed; forming the wiring pattern by laminating metal layers comprising a plurality of different metals formed by electrolytic plating in a layered form; and removing the resist pattern after forming the wiring pattern; and etching the metal film and the side surface part of the wiring pattern by performing wet etching, using the wiring pattern as a mask, so that the side surface part has an undercut portion, and the metal film that has been exposed, is removed at the same time.