Patent ID: 6671797
Filing Date: 2003-12-30
Classification: G06F

Abstract:
A digital system comprising a microprocessor having an instruction execution pipeline with a plurality of pipeline phases, wherein the microprocessor comprises:program fetch circuitry operable to perform a first portion of the plurality of pipeline phases; instruction decode circuitry connected to receive fetched instructions form the program fetch circuitry, the instruction decode circuitry operable to perform a second portion of the plurality of pipeline phases; and at least a first functional unit connected to receive a plurality of control signals from the instruction decode circuitry, the functional unit operable to perform a third portion of the plurality of pipeline phases, the third portion being execution phases, wherein the first functional unit comprises mask circuitry responsive to the plurality of control signals, the mask circuitry operable to select a first operand bit from a source operand and to selectively connect the first bit to a first plurality of destination operand bit lines, such the first operand bit is expanded to form a mask in a selected portion of the destination operand, wherein the mask circuitry is connected to select a plurality of source operand bits from the source operand and to selectively connect each selected source operand bit to selected sets of destination operand lines, such that each selected source operand bit is selectively connected to a different set of destination operand lines.