Patent ID: 7564094
Filing Date: 2009-07-21
Classification: H01L

Abstract:
1. A method of manufacturing a non-volatile memory device comprising: forming a tunnel insulating layer on a channel region of a substrate; forming a charge-trapping layer on the tunnel insulating layer; forming a blocking layer on the charge-trapping layer; forming a gate electrode on the blocking layer; patterning the blocking layer to form a first blocking layer pattern between the charge-trapping layer and the gate electrode and to expose portions of the charge-trapping layer to form a charge-trapping layer pattern under the first blocking layer pattern between the exposed portions of the charge-trapping layer that extend laterally therefrom; and oxidizing the exposed portions of the charge-trapping layer to form second blocking layer patterns proximate sidewalls of the charge-trapping layer pattern to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern.