Patent ID: 6801060
Filing Date: 2004-10-05
Classification: G05F

Abstract:
A semiconductor integrated circuit comprising:a power supply voltage detecting circuit which, when a power supply voltage is higher than a first voltage, outputs a high level voltage, and when the power supply voltage is lower than the first voltage, outputs a low level voltage; and a detection signal output circuit which receives the output voltage of said power supply voltage detecting circuit, and outputs a first detection signal when said power supply voltage is increased to be equal to or higher than the first voltage, and a second detection signal when the power supply voltage is decreased to a second voltage lower than the first voltage, the detection signal output circuit comprising a Schmitt trigger circuit, wherein the Schmitt trigger circuit comprises: an input CMOS inverter comprised of an N channel MOS transistor and a P channel MOS transistor; an output CMOS inverter comprised of an N channel MOS transistor and a P channel MOS transistor; and a feed-back circuit, which is comprised of N channel MOS transistors connected in parallel between an input terminal of the output CMOS inverter and a reference potential, in which an output terminal of the output CMOS inverter is connected to gates of the N channel MOS transistors connected in parallel so that an input signal of the output CMOS inverter is fed back to the input terminal of the output CMOS inverter.