Patent ID: 8324058
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A method for contacting an FET device, comprising: receiving said FET device with a source and a drain consisting of a semiconductor material and with an isolation surrounding said FET device, furthermore said FET device comprises a body having an upper surface, wherein said upper surface of said body defines a principal surface for said FET device; recessing vertically said isolation relative to said principal surface using a selective etch exposing a sidewall surface on both said source and said drain; performing silicidation, after which silicide is covering top surfaces on both said source and said drain and said sidewall surface of both said source and said drain, wherein said top surfaces are substantially parallel with said principal surface; applying metallic contacts to said source and to said drain in such manner that said metallic contacts engage said silicide on said top surfaces and on said sidewall surface of at least one of said source and of said drain; and wherein said FET device further comprises a gate-stack having a portion overlaying said isolation, wherein said portion of said gate-stack protects said isolation during said recessing, and wherein a part of said isolation underneath said gate-stack is essentially even with said principal surface.