Patent ID: 6806129
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A method for forming a heterojunction bipolar transistor, comprising:forming a sub-collector layer; forming a collector layer atop the sub-collector layer; forming a base layer atop the collector layer; forming an emitter layer atop the collector layer; forming a cap layer atop the emitter layer, wherein the base layer comprises a different material than at least one of the emitter layer and the collector layer; forming an etch mask atop the cap layer to expose a portion of the cap layer; selectively etching the exposed portion of the cap layer to form a sidewall with at reentry feature comprising an undercut profile and to expose a portion of the emitter layer; selectively etching the exposed portion of the emitter layer to expose a portion of the base layer; and forming metal contacts on the exposed portion of the base layer and the exposed portion of the cap layer.