Patent ID: 7714637
Filing Date: 2010-05-11
Classification: G11C

Abstract:
1. A negative potential discharge circuit, comprising: an internal voltage generating circuit configured to generate a regulated output voltage based on a power supply voltage; and a discharge unit configured to discharge a negative potential using the regulated output voltage, the discharge unit includes a level shifter configured to shift a level of a first discharge timing signal by dividing the regulated output voltage; an inverter inverting an output of the level shifter; a first PMOS transistor including a source connected to the internal voltage generating circuit and a gate connected to the inverter; a second PMOS transistor including a source connected to a drain of the first PMOS transistor and a gate connected to a ground terminal; a first NMOS transistor including a drain connected to a drain of the second PMOS transistor and a gate connected to the ground terminal; a second NMOS transistor including a drain connected to a source of the first NMOS transistor, a gate receiving a second discharge timing signal, and a source connected to a ground terminal; and an output terminal connected to the drain of the second NMOS transistor.