Patent ID: 6442072
Filing Date: 2002-08-27
Classification: G11C

Abstract:
A row selection/deselection circuit for a nonvolatile memory comprising:a decoding line connected between a voltage supply and ground, and comprising a series of decoding the same-conductivity-type transistors controlled by respective selection signals, and a load transistor of opposite type of conductivity connected in series to the decoding transistors and biased by a control voltage, and having a terminal coupled to the voltage supply and another terminal connected to a last one of the series of decoding transistors, and for generating an activating/deactivating voltage signal of a word line of the memory; and a circuit for controlling the load transistor comprising a sensing element in series to the decoding transistors and to the load transistor for producing a sensing signal which switches between a first level when only one memory word line is selected and a second level when a plurality of memory word line are selected; an inverter for receiving the sensing signal and outputting a first signal; and a high pass filter for receiving the first signal and producing the control voltage to bring the load transistor to a fully conductive state when the sensing signal switches from the first level to the second level.