Patent ID: 6190911
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method for fabricating a semiconductor devise having a wiring part connected, via an opening portion formed in an insulating film on a semiconductor region, to said semiconductor region, wherein said wiring part comprises a polycrystalline semiconductor layer and a metal or metal silicide on said polycrystalline semiconductor layer, comprising the steps, in forming said wiring part, of:depositing a first layer of polycrystalline semiconductor over said opening portion of said semiconductor region, said first layer having a surface side opposite to a side facing said opening portion and further having first grains;injecting as a first impurity an ion selected from a group consisting of Ge, Sn, P, As, Sb, Ga and In in a manner of an ion-implantation into said first layer so as to amount to more than 5.times.10.sup.19 atoms/cm.sup.3 to convert at least a part of the polycrystalline semiconductor of said first layer at said surface side into an amorphous state;injecting, into the first layer of said polycrystalline semiconductor, second impurities which have a projection range shorter than that of the first impurities, and which operate as p-type or n-type impurities having a lower mass or lower energy than that of an element of the first impurities, so that a desired region with a high concentration of p-type or n-type impurities is formed, at said surface, wherein the total concentration of impurities is greater than 5.times.10.sup.19 atoms/cm.sup.3 at a depth of 1000 .ANG. from the surface of said semiconductor layer;conducting heat treatment, after the injection of said impurities, whereby the size of the crystal of said first layer at the side wherein at least said metal or metal silicide is brought into contact and located is made larger than the size of said polycrystalline semiconductor layer before said introduction of the impurity; anddepositing the metal or metal silicide containing a low-melting metal on the region having the second impurity in the more enlarged grains on said polycrystalline semiconductor layer so as to use the region as a contact portion after the heat treatment.