Patent ID: 6011285
Filing Date: 2000-01-04
Classification: C23C,H01L

Abstract:
A ferroelectric memory (FEM) cell comprising:a single-crystal silicon substrate including an active region therein;a source junction region and a drain junction region located in said active region, doped with doping impurities of a first type to form a pair of conductive channels of a first type;a gate junction region located in said active region between said source junction region and said drain junction region, doped to form a conductive channel of a second type;a FEM gate unit including a lower electrode, a c-axis oriented Pb.sub.5 Ge.sub.3 O.sub.11 FE layer and an upper electrode; wherein said FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance ""D"" from the edges of said source junction region and said drain junction region, where ""D"" is between about 50 nm and 300 nm.an insulating layer, having an upper surface, overlying said junction regions, said FEM gate unit and said substrate;a source electrode and a drain electrode, each located on the upper surface of said insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper electrode of said FEM gate unit.