Patent ID: 7126193
Filing Date: 2006-10-24
Classification: H01L

Abstract:
1. A metal-oxide-semiconductor (MOS) device, comprising: a semiconductor layer of a first conductivity type; a first source/drain region of a second conductivity type formed in the semiconductor layer; a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region; a gate formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions; and at least one contact, the at least one contact comprising: a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate; and at least one insulating layer formed directly on the silicide layer; wherein the first source/drain region comprises an n-type region and a p-type region formed adjacent to said n-type region and extending laterally away from said gate, and wherein the silicide layer is formed substantially proximate the n-type and p-type regions such that the silicide layer forms a substantially low-resistance electrical path in parallel with an electrical path formed between the n-type and p-type regions.