Patent ID: 7779272
Filing Date: 2010-08-17
Classification: H04L

Abstract:
1. A hardware cryptographic engine for encrypting transmission data, the hardware cryptographic engine comprising: a first ciphertext engine that receives a second intermediate ciphertext output from a second ciphertext engine, generates a first intermediate ciphertext, and uses the first intermediate ciphertext to generate and output a first final ciphertext; the second ciphertext engine that outputs the second intermediate ciphertext, and uses the second intermediate ciphertext to generate and output a second final ciphertext; a comparison unit that generates and outputs a control signal having a logic state depending on whether the first final ciphertext is the same as the second final ciphertext; and an encryption data output unit that responds to the logic state of the control signal, and outputs a final ciphertext when the first final ciphertext is the same as the second final ciphertext; wherein the second ciphertext engine receives the first intermediate ciphertext output from the first ciphertext engine and generates a subsequent second intermediate ciphertext, and wherein each of the first ciphertext engine and the second ciphertext engine comprises a plurality of round blocks and a logic circuit that detects if fault occurs in the round blocks and the logic circuit receives a respective first intermediate ciphertext and a respective second intermediate ciphertext, each of the round blocks of the first ciphertext engine generates the respective first intermediate ciphertext, and each of the round blocks of the second ciphertext engine generates the respective second intermediate ciphertext.