Patent ID: 8987689
Filing Date: 2015-03-24
Classification: B82Y,H01J

Abstract:
1. A method for exposing a wafer substrate, comprising: receiving an IC design layout data; modifying the IC design layout data using an electron proximity correction (EPC) technique; arranging the modified IC design layout data for a scanning lane comprising original integrated circuit (IC) fields having an original IC field width less than a maximum electron beam width of an electron beam writer; converting the modified IC design layout data to electron beam format data; rearranging the electron beam format data for a scanning lane having a scanning lane width that matches the maximum electron beam width; locating a repetitive scanning lane having the same electron beam format data by finding a least common multiple (LCM) of a value of the maximum electron beam width and a value of the original IC field width; and writing the rearranged electron beam format data on a substrate using the electron beam writer, wherein the maximum electron beam width spans a plurality of original IC fields in a direction perpendicular to a scan direction.