Patent ID: 8881089
Filing Date: 2014-11-04
Classification: G06F

Abstract:
1. A method of optimizing a design for an integrated circuit for a physical synthesis stage of an integrated-circuit design process, the method comprising: selecting one of a plurality of solutions for optimization of the design for the integrated circuit; performing, via at least one processor, an evaluation of the one of the plurality of solutions for a non-sensitive metric without modification to a netlist for the integrated circuit, wherein the netlist would require modification if the one of the plurality of solutions were to be evaluated for a sensitive metric, wherein the non-sensitive metric is metric that changes by less than approximately ten percent when any of the plurality of solutions is evaluated, and wherein the sensitive metric is a metric that changes by more than approximately ten percent when any of the plurality of solutions is evaluated; determining, based on the evaluation of the one of the plurality of solutions for the non-sensitive metric, that the non-sensitive metric exceeds an optimization limit associated with the non-sensitive metric for the integrated circuit design; and in response to the determining that the non-sensitive metric exceeds the optimization limit, rejecting the one of the plurality of solutions without performing evaluation of the one of the plurality of solutions for the sensitive metric.