Patent ID: 6690213
Filing Date: 2004-02-10
Classification: G11C,H03K

Abstract:
A chopper type comparator comprising:a first switch device including a PMOS transistor and an NMOS transistor for switching a voltage to be compared; a second switch device including a PMOS transistor and an NMOS transistor for switching a reference voltage; a capacitor connected to an output side of both the first and second switch devices for storing a charge according to the voltage; an amplification inverter connected to an output side of the capacitor and amplifying a capacitor output signal of the capacitor; a first control driver circuit outputting a clock signal for controlling both the first and second switch devices; and a second control driver circuit outputting a clock signal for controlling the amplification inverter, wherein the first control driver circuit is provided with two output devices, one output side of the first control driver circuit connects to a gate terminal of the PMOS transistor of the first switch device and a gate terminal of the NMOS transistor of the second switch device, or to a gate terminal of the NMOS transistor of the first switch device and a gate terminal of the PMOS transistor of the second switch device, and another output side of the first control driver circuit connects to a gate terminal of the NMOS transistor of the first switch device and a gate terminal of the PMOS transistor of the second switch device, or to a gate terminal of the PMOS transistor of the first switch device and a gate terminal of the NMOS transistor of the second switch device, wherein an intersection of a rising part and a falling part of drive output control signals of at least one of the first control driver circuit and the second control driver circuit defines a center of an amplitude of a drive signal; wherein, in at least one of the first control driver circuit and the second control driver circuit, a drive input control signal that is inputted in the driver circuits is branched to two output circuits, wherein one of the two output circuits is provided with a plurality of first control inverters, and another of the two output circuits is provided with a plurality of second control inverters, the number of second control inverters being less than the number of first control inverters, wherein an L-size (transistor length) of transistors that form the second control inverters is two times an L-size of transistors that form the first control inverters.