Patent ID: 8436400
Filing Date: 2013-05-07
Classification: G06F,H01L

Abstract:
1. A semiconductor device, comprising: a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively; at least six linear shapes extending along a first reference direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first reference direction, wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including, (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor, (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor, such that,