Patent ID: 6093633
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A semiconductor device manufacturing method comprising:a step forming a first insulation film over a semiconductor substrate or over a wiring layer and forming a plurality of grooves in locations of said first insulation film corresponding to a wiring pattern;a step depositing a conductor over the entire surface of said first insulation film, including within said grooves;a step forming said wiring pattern by removing the conductor in parts other than within said grooves, leaving said conductor only within said grooves;a step selectively removing said first insulation film corresponding to a narrow wiring space, and selectively maintaining said first insulation film corresponding to a wide wiring space, in which the removing of said first insulation film exposes said wiring pattern; anda step forming a void in a second insulation film provided in an area of said narrow wiring space by forming said second insulation film over said first insulation film corresponding to said wide wiring space and the entire surface of said wiring pattern.