Patent ID: 6245607
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A method for forming a buried channel lateral quasi-unipolar transistor having low 1/f noise comprising the steps of:implanting a material of a first conductivity type to a low concentration into a surface of a semiconductor substrate to form a bulk region that is a base of a quasi-unipolar transistor;implanting a material of a second conductivity type to a high concentration into the surface of the semiconductor substrate to form a drain region that is a drain/collector and a source region that is a source/emitter of the quasi-unipolar transistor, whereby the drain region is separated distally from the source region;implanting the material of the second conductivity type to a low concentration into the surface of the semiconductor substrate to form a channel region between the drain region and the source region, whereby said channel region is a low resistivity path between the drain/collector and the source/emitter;implanting the material of the first conductivity type to a low concentration between the channel region and the surface of the semiconductor substrate to form an overlayer;forming a gate oxide on the surface of the semiconductor substrate above the channel region between the drain region and the source region;placing a conductive material on the gate oxide above the channel region to form the gate electrode of the quasi-unipolar transistor; andconnecting a biasing voltage source between the gate electrode and the bulk region to lower a built-in voltage of said quasi-unipolar transistor.