Patent ID: 8779434
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A thin film transistor array, comprising: a plurality of gate electrodes formed on an insulation substrate; a plurality of source electrodes formed above or under the gate electrodes via a gate insulation film so that the source electrodes cross the gate electrodes in a planar view; a plurality of drain electrodes formed at corresponding positions surrounded by the gate electrodes and the source electrodes in a planar view in the same layer as that of the source electrodes; semiconductor layers formed via the gate insulation film to face the gate electrodes for forming corresponding channel regions between the source electrodes and the drain electrodes; wherein the plural gate electrodes are linearly formed, and the channel regions are disposed to face the gate electrodes, wherein common electrodes are formed under the source electrodes and the drain electrodes and in the same layer as that of the gate electrodes via the gate insulation film at positions facing the drain electrodes, wherein the common electrodes include incision parts disposed parallel to the gate electrodes and formed in regions overlapping the source electrodes in a planar view, and wherein the common electrode includes a corner part in a planar view and is formed under the source electrode and the drain electrode, and the corner part is formed not to overlap the source electrode and the drain electrode in a planar view.