Patent ID: 8458282
Filing Date: 2013-06-04
Classification: G06F,H04L

Abstract:
1. A computing apparatus for reducing the amount of processing in a network computing system, comprising: a network system device of a receiving node for receiving electronic messages including data, the electronic messages being transmitted from a sending node, and the network system device determining when more data of a specific electronic message is being transmitted; a memory device for storing the electronic message data and communicating with the network system device; a memory subsystem communicating with the memory device, and the memory subsystem storing a portion of the electronic message when more data of the specific message is being transmitted, a buffer included in the memory subsystem wherein the buffer includes a first holding time for storing non tagged data, the buffer combining the portion with later received data and moving the combined data to the memory device for accessible storage; a pre-fetch device for pre-fetching identified metadata stored in the memory device from a selected data packet of the electronic message using the network system device, the identified metadata being additionally stored in a cache memory, the identified metadata being stored in the cache memory and being used when the buffer combines the portion with the later received data; and a flag being included in the specific electronic message being transmitted from the sending node, the flag indicating that more data of the specific electronic message is being transmitted, the flag tagging the stored data in the buffer resulting in the tagged stored data being stored for a second holding time, and the second holding time being greater than the first holding time for non tagged stored data; wherein, after the second holding time has elapsed, a processor moves the tagged stored data from the buffer to the memory device using a Read-Modify-Write cycle.