Patent ID: 8629016
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A method of forming a plurality of transistor device types on an integrated circuit, the transistors having a gate disposed over a semiconductive channel, comprising: doping selected portions of a wafer to form a first plurality of wells of a first conductivity type; doping selected portions of the first plurality of wells to form a first plurality of screen layers of the first conductivity type, the screen layers being disposed closer to a surface of the wafer than the wells; doping selected portions of the first plurality of screen layers to introduce diffusion-inhibiting dopant species; growing a substantially undoped epitaxial layer over the screen layer to a defined thickness and uniformity; out-diffusing dopants from the screen layer into the epitaxial layer to result in discrete threshold voltage devices by way of a thermal cycling process to result in defined degrees of out-diffusion of dopants that are differentiated by distance of dopant mitigation toward the gate; and forming an anti-punchthrough layer between at least one of the first plurality of wells and at least one of the first plurality of screen layers that overlies the at least one of the first plurality of wells; wherein the anti-punchthrough layer has a doping concentration greater than a doping concentration of the at least one well, and less than a doping concentration of the overlying screen layer.