Patent ID: 7785955
Filing Date: 2010-08-31
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor structure comprising: forming a first mesa and a second mesa within a semiconductor substrate; forming a dielectric layer covering the sidewall surfaces of the first mesa and the second mesa; etching back the dielectric layer to expose the sidewall surfaces of at least the first mesa, thus providing the first mesa with a lower ratio of channel effective horizontal surface area to channel effective vertical surface area than the second mesa; and forming a first device of a first polarity using the first mesa as a first channel and a second device of a second polarity using the second mesa as a second channel, where the first polarity is selected to benefit from a vertical crystallographic orientation in comparison with a horizontal crystallographic orientation of the first mesa and the second polarity is selected to benefit from a horizontal crystallographic orientation in comparison with a vertical crystallographic orientation of the second mesa.