Patent ID: 7646440
Filing Date: 2010-01-12
Classification: G02F,H01L

Abstract:
1. A method of fabricating pixel structure, comprising: sequentially forming a first metal layer, a first dielectric layer, and a silicon layer on a substrate; patterning the first metal layer, the first dielectric layer, and the silicon layer to define a transistor stack, a data line and a first electrode, wherein the transistor comprises the first metal layer, the first dielectric layer, and the silicon layer, and the data line and the first electrode are made by the first metal layer; sequentially forming a gate dielectric layer and a second metal layer on the substrate, the transistor stack, the data line and the first electrode; patterning the second metal layer to define a gate on the transistor stack and a second electrode on the first electrode; doping the silicon layer to form a first and a second heavily doped regions on two sides of the silicon layer by using the gate as a mask; forming a second dielectric layer on the gate dielectric layer, the gate and the second electrode; patterning the second dielectric layer to form a first, a second, a third and a fourth openings to respectively expose the data line, the first heavily doped region, the second heavily doped region and the first electrode; forming a third metal layer over the second dielectric layer; patterning the third metal layer to define a first and a second conductive lines, wherein the first conductive line connects the data line and the first heavily doped region through the first and the second openings, the second conductive line connects the second heavily doped region and the first electrode through the third and the fourth openings, and a part of the second conductive line overlaps the second electrode, wherein the part of the second conductive line, the second electrode, and the first electrode compose a storage capacitor; forming a transparent conductive layer on the second dielectric layer, the first and the second conductive lines; and patterning the transparent conductive layer to define a pixel electrode on the second conductive line and the second dielectric layer.