Patent ID: 9142266
Filing Date: 2015-09-22
Classification: G11C

Abstract:
1. Memory circuitry comprising: an array of bit cells; a plurality of bit lines, each of said plurality of bit lines coupled to a column of bit cells within said array; write driver circuitry selectively coupled to each of said bit lines through a respective column select transistor controlled by a column select signal, said write driver circuitry supplying write signal with a write voltage level outside of a voltage range between a first voltage level and a second voltage level in order to perform a write operation within said array; column select circuitry coupled to a power supply via a first power supply rail at said first voltage level and a second power supply rail at said second voltage level, said first voltage level being higher than said second voltage level, said column select circuitry being configured to select one or more target columns of bit cells within to which a write operation is to be performed by: wherein at least one of said selected signal level and said unselected signal level is outside of said voltage range between said first voltage level and said second voltage level.