Patent ID: 8471608
Filing Date: 2013-06-25
Classification: H03K

Abstract:
1. A clock divider that receives m input clock signals each of the same frequency, each input clock signal after the first having a phase offset of 2 π/m, with 2 π radians being the phase change in one period of the clock, from the previous input clock signal, and divides the frequency of the input clock signals by an integer of division K, the divider comprising: a counter that receives the first input clock signal and provides one or more count signals; and m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal, and each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2 πK/m phase offset from the previous clock output signal, each flip-flop having a D input that receives a D-input signal comprising one of (1) a count signal and (2) a clock output signal from one of the other flip-flops wherein: the integer of division is 2; the counter provides zero-count and one-count signals; the clock inputs of the first and (m/2) flip-flop receives the first input clock signal; the clock inputs of the second and (m/2)+1 flip-flops receive the third input clock signal; the clock inputs of the third and (m/2)+2 flip-flops receive the fifth input clock signal; the clock inputs of the fourth and (m/2)+3 flip-flops receive the seventh input clock signal, and so on for any remaining flip-flops and odd-numbered input clock signals; the D input of the first flip-flop receives the zero-count signal; the D inputs of the next (m/2)−1 flip-flops receive the first clock output signal; the D input of the next flip-flop receives the one-count signal; and the D inputs of the remaining flip-flops receive the (m/2)+1 clock output signals, whereby each clock output signal has a frequency one-half that of the input clock signals and each clock output signal after the first has a phase offset of 2 π/m from the previous clock output signal.