Patent ID: 8250496
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: designing a circuit layout; setting light exposure conditions to be used for transfer of the circuit layout; obtaining an inverse layout of the circuit layout; reducing the inverse layout in an X-axis direction by a first reduction width set after reflecting the light exposure conditions in association with the X-axis direction, thereby obtaining a first reduced layout; reducing the first reduced layout in a Y-axis direction by a second reduction width set after reflecting the light exposure conditions in association with the Y-axis direction, thereby obtaining a second reduced layout; reducing the second reduced layout by a third reduction width in the X-axis direction and by a fourth reduction width in the Y-axis direction, thereby obtaining a third reduced layout; deducting the third reduced layout from the second reduced layout, thereby obtaining a dummy pattern layout self-assembled to the circuit layout; combining the dummy pattern layout and the circuit layout; and transferring the combined layout to a semiconductor substrate.