Patent ID: 6297832
Filing Date: 2001-10-02
Classification: G06T,G09G

Abstract:
A video graphics circuit comprising:a memory having at least a first bank and a second bank;at least one linear memory client, wherein linear memory clients store and retrieve data stored in the memory in a linear formatat least one tiled memory client, wherein tiled memory clients store and retrieve data stored in the memory in a tiled format; anda memory controller operably coupled to the memory, the linear memory client, and the tiled memory client,wherein when the memory controller receives a set of data from linear memory clients to store in the memory, the memory controller stores the set of linear data in the memory in a burst interleaved format such that successive portions of the set of linear data are stored in alternating banks of the memory, wherein size of the successive portions is determined based on a page fault time,wherein when the memory controller receives a set of data from tiled memory clients to store in the memory, the memory controller stores the set of tiled data in the memory in a tiled format such that successive tiles of the set of tiled data are stored in alternating banks of the memory, wherein a dimension of the tiles is determined based on the page fault time,wherein when the memory controller receives a request to retrieve data from linear clients and from tiled clients, the memory controller structures reads from the memory such that page faults are hidden.