Patent ID: 6985382
Filing Date: 2006-01-10
Classification: G11C

Abstract:
1. A latching circuit that senses and latches the magnetic states of a first bit line and a second bit line in a magnetoresistive random access memory (MRAM), the latching circuit comprising: a first n-type transistor with a gate, a drain, and a source, the source of the first n-type transistor is operatively coupled to a first portion of the first bit line; a second n-type transistor with a gate, a drain, and a source, the gate of the second n-type transistor is operatively coupled to the drain of the first n-type transistor, the drain of the second n-type transistor is operatively coupled to the gate of the first n-type transistor, the source of the second n-type transistor is operatively coupled to a first portion of the second bit line; a first p-type transistor with a gate, a drain, and a source, the gate of the first p-type transistor is operatively coupled to the gate of the first n-type transistor, the drain of the first p-type transistor is operatively coupled to the drain of the first n-type transistor, the source of the first p-type transistor is operatively coupled to a second portion of the second bit line; a first output operatively coupled to the drain of the first p-type transistor; a second p-type transistor with a gate, a drain, and a source, the gate of the second p-type transistor is operatively coupled to the gate of the second n-type transistor, the drain of the second p-type transistor is operatively coupled to the drain of the second n-type transistor, the source of the second p-type transistor is operatively coupled to a second portion of the first bit line; and a reset switch with a first terminal, a second terminal, and a third terminal, the first terminal is operatively coupled to an input signal, the second terminal is operatively coupled to the gate of the first n-type transistor, the third terminal is operatively coupled to the gate of the second n-type transistor, the reset switch at least partially responsive to a first state and to a second state of the input signal such that in the first state, the reset switch is configured to operatively couple the second terminal to the third terminal, and where in the second state, the reset switch is configured to operatively decouple the second terminal from the third terminal.