Patent ID: 6748592
Filing Date: 2004-06-08
Classification: G06F

Abstract:
An apparatus comprising:one or more memory modules; a processor coupled to the one or more memory modules to execute programming instructions using said memory module(s), with the processor being equipped to provide a hardware facilitated privilege protection for programming instructions being executed using said memory modules, with at least two privilege levels; a plurality of programming instructions including a first and a second subset of said programming instructions implementing a first and a second memory manager to manage usage of said memory, with the first memory manager managing the hardware facilitated privilege level to be afforded by the processor for different subsets of said programming instructions to be executed, and the second memory manager managing and further facilitating a software facilitated privilege protection for some of the different subsets of said programming instructions to be executed for at least one of said hardware facilitated privilege levels, the software facilitated privilege protection having also at least two sub-privilege levels; and wherein the programming instructions further comprises a third subset implementing a program loader equipped to fix up each subset of said programming instructions it loads for execution by the processor to afford the second memory manager the opportunity to administer the software facilitated privilege protection.