Patent ID: 6323867
Filing Date: 2001-11-27
Classification: G06F

Abstract:
An apparatus for queuing commands to be executed by a processor comprising:first memory for storing data structures wherein each data structure comprising a header and at least one data word, the header comprising information indicating the number of data words in the data structure and information indicating whether the data words to be followed represent a command or data to be used with a command;a data manager coupled to the first memory, the data manager retrieving a data structure from the first memory;a command parser coupled to the data manager, the command parser receiving a header associated with the data structure retrieved by the data manager, the command parser parsing information in the header and providing parsed information to the data manager;second memory coupled to the data manager, the command parser, and the processor, if data words in the data structure retrieved by the data manager represent a command, the data manager sending the command to the second memory for queuing; andthird memory coupled to the data manager, the command parser, and the processor, if data words in the data structure retrieved by the data manager represent data to be used with a command, the data manager sending the data to the third memory for queuing.