Patent ID: 8970025
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a first semiconductor package, the first semiconductor package including a first semiconductor chip having a plurality of through silicon vias (TSVs) extending therethrough, a first plurality of internal connection terminals in a form of a conductive bump or a solder ball on the plurality of TSVs; and a second semiconductor package on the first semiconductor package, the second semiconductor package including a second semiconductor chip having a second plurality of internal connection terminals in a form of a conductive bump or a solder ball on the plurality of TSVs, a plurality of external connection terminals, and an epoxy molding compound on the second semiconductor chip and the second plurality of internal connection terminals, wherein the plurality of external connection terminals electrically connects the first semiconductor chip to the second semiconductor chip, a sidewall of the epoxy molding compound is coplanar with a sidewall of the second semiconductor chip, and a top of the epoxy molding compound is higher than the second plurality of internal connection terminals.