Patent ID: 7315597
Filing Date: 2008-01-01
Classification: H03H

Abstract:
1. A sampling frequency conversion device, comprising: an internal circuit configured to execute in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data; a clock generation circuit configured to generate from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more); a first counter configured to count the counter clock and to subtract the integer n from a counted counter value in synchronization with the input word clock; and a register configured to hold the counter value of the first counter in synchronization with the input word clock, and to output a flag signal to the internal circuit when the held counter value becomes a value out of a predetermined range, wherein the internal circuit executes a thinning-out processing for one sample of the output data as the correction processing of the output data when the flag signal shows that the input data is delayed by one sample behind the output data, and the internal circuit executes an interpolation processing for one sample of the output data as the correction processing of the output data when the flag signal shows that the input data advances by one sample ahead of the output data.