Patent ID: 7732855
Filing Date: 2010-06-08
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor substrate; at least one control gate electrode recessed into the semiconductor substrate; at least one storage node layer between a sidewall of the at least one control gate electrode and a sidewall portion of the semiconductor substrate; at least one tunneling insulating layer between the at least one storage node layer and the sidewall portion of the semiconductor substrate; at least one blocking insulating layer between the at least one storage node layer and the at least one control gate electrode; and first and second channel regions between the at least one tunneling insulating layer and the sidewall portion of the semiconductor substrate; wherein the first and second channel regions are separated from each other, wherein the at least one blocking insulating layer has a dielectric constant greater than a dielectric constant of the at least one tunneling insulating layer, and wherein for a given control gate electrode, the first and second channel regions are separated by a pair of separating insulating layers that face each other.