Patent ID: 7102874
Filing Date: 2006-09-05
Classification: H01G,H05K

Abstract:
1. A capacitive apparatus for a built-in capacitor with at least one pair of electrodes having sizes that are non-symmetrical, wherein the non-symmetric electrodes are employed in a PCB to minimize the capacitance inaccuracy due to PCB alignment deviation in a lamination process thereof, said capacitive apparatus comprising: a plurality of said first plates are interposed with a plurality of said second plates; wherein each first plate is separated from each second plate by a distance containing a dielectric, wherein said first plate and said second plate are different in size, said first plate is smaller than said second plate, and said second plate covers said first plate; and said dielectric being located between said first plate and said second plate; wherein both of said first plate and said second plate comprise conductive patterns; wherein said first plate and said second plate have a one-to-one relation and form a two-port capacitor, wherein said first plate connects to other components through wiring and/or vias as one port of the two-port capacitor, and said second plate connects to the other components through the wiring and/or vias as another port of the two-port capacitor; and wherein said plurality of said first plates interposed with said plurality of said second plates form a multi-layer built-in capacitor with non-symmetric electrodes, wherein each said first plates is one-to-one interposed with each said second plates.