Patent ID: 6697910
Filing Date: 2004-02-24
Classification: G11C

Abstract:
A semiconductor memory device having an operation state where a read operation and a write operation for data are executable and a standby state where said data is retained, comprising:a memory cell array including a plurality of memory cells arranged in a matrix; and a complete hidden refresh circuit for performing a refresh operation without being externally commanded for said data stored in said plurality of memory cells; wherein said complete hidden refresh circuit executes said refresh operation according to the condition of said semiconductor memory device; and wherein said complete hidden refresh circuit includes: a refresh circuit for outputting a refresh command signal for execution of said refresh operation; and a control circuit for executing said refresh operation in response to said refresh command signal; and wherein said refresh circuit includes: a timer circuit for outputting a cycle signal at a time interval necessary for refreshing data stored in said plurality of memory cells; a command-signal activating circuit for activating said refresh command signal in response to said cycle signal; and a determination circuit for determining as to whether or not said refresh command signal activated is to be output.