Patent ID: 6614278
Filing Date: 2003-09-02
Classification: H03H,H03K

Abstract:
An integrated circuit comprising:an input node for receiving an input signal; a floating node; a buffer coupled between the input node and the floating node, the buffer coupled between a first reference operating voltage and a second reference operating voltage; a detector coupled to the floating node and for outputting an output voltage of a first level when a voltage at the floating node is below a threshold, and of a second level otherwise; a first reference terminal carrying a first reference adjusting voltage, the first reference adjusting voltage having a value between the first and second operating voltages; a first capacitor coupled between the floating node and the first reference terminal; a first switch coupled between the floating node and the first capacitor, the first switch opening and closing responsive to the first and second levels of the output voltage; and a first precharge switch controlled by the output voltage for selectively shorting a node between the first switch and the first capacitor.