Patent ID: 6816827
Filing Date: 2004-11-09
Classification: G06F

Abstract:
A design verification method capable of verifying designs with one or more combinational loops, said method comprising the steps of:(a) determining the location of a combinational loop within a design; (b) providing a model of the design by breaking the combinational loop, wherein said model comprises at least one finite state machine, each finite state machine comprising at least one original state; (c) providing a twin-state for each original state within each of said finite state machines such that each twin state has the same fanout and output function as its corresponding original state, and each original state maintains its respective output function but fans out only to its corresponding twin state; (d) inserting at least one flip-flop within said design at the location where the combinational loop was broken, and making a simple two-state model for the flip-flop; (e) combining the model of the design with the model of the flip-flop by taking the product of the two finite state machines to generate an overall modified model; (f) checking correctness properties on the modified model.