Patent ID: 6487654
Filing Date: 2002-11-26
Classification: G06F

Abstract:
In a computer system incorporating a memory system, a processor, and input/output devices, where said processor is responsive to interrupts and comprises first and second register sets with the first register set in an active state and the second register set in a shadow state, an active register set switch command, and a DMA/DRA controller operative to transfer data between the shadow register set and memory, a method of reducing context switching in response to interrupts, the method comprising:issuing an interrupt request by a device in said computer system; categorizing interrupts into at least two classes, a first class being a conventional interrupt, and a second class being a delayed interrupt; when said interrupt request is categorized as a delayed interrupt, automatically issuing shadow register to and from memory transfer instructions from said processor to said DMA/DRA controller; and when the DMA/DRA controller indicates said transfer is complete: finishing the current instruction and stacking return information in a conventional manner; and passing control to an associated interrupt service routine.