Patent ID: 7365586
Filing Date: 2008-04-29
Classification: H03K

Abstract:
1. A hysteresis-type input circuit comprising: a hysteresis circuit, which has a first trip point that has a first prescribed value at which voltage of an output signal with respect to voltage of an input signal is changed from a second logic level to a first logic level, and a second trip point that has a second prescribed value at which the output voltage of the output signal is changed from the first logic level to the second logic level, and which undergoes bidirectional transition with a time-delay between a first state in which operation is performed at said first trip point and a second state in which operation is performed at said second trip point; a transmission control part that, when transition in the output voltage occurs from said first state to said second state or from said second state to said first state, prohibits or delays transmission of the output signal of said hysteresis circuit to a downstream circuit before said transition has been substantially completed wherein said transmission control part detects the timing at which said transition has been essentially completed according to the potential of a prescribed node in said hysteresis circuit; and wherein said transmission control part comprises a first inverter, having a first inversion threshold corresponding to said first trip point, and which outputs the first logic level when the potential of said prescribed node is lower than said first inversion threshold, and outputs the second logic level when said potential of said prescribed node is higher than said first inversion threshold, and a second inverter, having a second inversion threshold corresponding to said second trip point, and which outputs the first logic level when the potential of said prescribed node is lower than said second inversion threshold, and outputs the second logic level when said potential of said prescribed node is lower than said second inversion threshold; and a timing at which the outputs of said first inverter and second inverter are changed from the same logic level to different logic levels is adopted as the first timing; another timing at which the outputs of said first inverter and second inverter are changed from different logic levels to the same logic level is adopted as a second timing, and, with said second timing, the timing is adopted as that at which said transition has been substantially completed.