Patent ID: 6026483
Filing Date: 2000-02-15
Classification: G06F

Abstract:
A multiplier capable of multiplying one pair of N-bit operands or two pairs of N/2-bit operands simultaneously comprising:a multiplier input configured to receive a multiplier operand, wherein said multiplier operand comprises one N-bit value or two N/2-bit values;a multiplicand input configured to receive a multiplicand operand, wherein said multiplicand operand comprises one N-bit value or two N/2-bit values;a partial product generator coupled to said multiplicand input, wherein said partial product generator is configured to generate a plurality of partial products based upon said multiplicand operand;a selection logic unit coupled to said partial product generator and said multiplier input, wherein said selection logic unit is configured to select a plurality of partial products from said partial product generator based upon said multiplier operand; andan adder coupled to said selection logic unit, wherein said adder is configured to sum the partial products selected by said selection unit to form a final product, wherein said final product comprises either one 2N-bit value or two N-bit values.