Patent ID: 6581087
Filing Date: 2003-06-17
Classification: G06F

Abstract:
A floating point adder comprising:a preprocessing unit receiving first and second floating point data and outputting an exponent part comparison result and a fraction part comparison result and a clip code, said preprocessing unit including an exponent part compare unit comparing an exponent part of said first floating point data and an exponent part of said second floating point data with each other and outputting said exponent part comparison result, a fraction part compare unit comparing a fraction part of said first floating point data and a fraction part of said second floating point data with each other and outputting said fraction part comparison result, and a clip code generation unit receiving the exponent part comparison result and the fraction part comparison result and generating the clip code; a digit match unit matching a digit of the fraction part of said first floating point data and a digit of the fraction part of said second floating point data depending on said fraction part comparison result and said exponent part comparison result; an operation unit adding together the fraction parts of said first and second floating point data having the digits matched by said digit match unit; and a normalization unit receiving and normalizing an operation result output from said operation unit.