Patent ID: 8154922
Filing Date: 2012-04-10
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell unit having a plurality of memory cells connected in series, a first select transistor and a second select transistor, the plurality of memory cells being located between the first select transistor and the second select transistor, the memory cell unit being arranged in an array form; a bit line, the first select transistor being located between the bit line and the plurality of memory cells; and a programming circuit for programming into a selected memory cell among the plurality of memory cells in a selected memory cell unit; wherein at a time of programming, the programming circuit applies a first voltage to a gate electrode of the selected memory cell, applies a second voltage to a gate electrode of a first memory cell located between the selected memory cell and the first select transistor, applies a third voltage to a gate electrode of a second memory cell located between the selected memory cell and the second select transistor, applies a fourth voltage to a gate electrode of a third memory cell located between the selected memory cell and the second select transistor, the third memory cell being different from the second memory cell, and applies a fifth voltage to a gate electrode of the first select transistor; and wherein all of the selected memory cell, the first memory cell, the second memory cell and the third memory cell are included in the selected memory cell unit, the first voltage is higher than both the second voltage and the fourth voltage, both the second voltage and the fourth voltage are higher than the third voltage and higher than the fifth voltage, and when the first voltage is applied to the gate electrode of the selected memory cell, the third voltage is lower than a voltage applied to a memory cell located between the select memory cell and the first select transistor and adjacent to the selected memory cell.