Patent ID: 8918597
Filing Date: 2014-12-23
Classification: G06F

Abstract:
1. An integrated circuit comprising: an array of memory cells; and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number, wherein the digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits configured to receive the data word directly from the array of memory cells, wherein each of the binary logic circuits is configured to receive a different subset of the data word directly from the array of memory cells, wherein each of the binary logic circuits includes at least one of a 3-input NAND circuit and a 3-input NOR circuit, wherein the at least one of a 3-input NAND circuit and a 3-input NOR circuit in each of the binary logic circuits is configured to receive two bits of the data word, perform a binary logic operation on the two bits, and generate two binary output signals, and wherein the binary output signals for each binary logic circuit are indicative of a number of logical zero bits contained in the two bits received by the binary logic circuit.