Patent ID: 7084032
Filing Date: 2006-08-01
Classification: H01L

Abstract:
1. A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising: forming source and drain regions in a semiconductor substrate; and forming a gate stack on the semiconductor substrate by steps including: depositing a thin oxide layer onto the semiconductor substrate; depositing a silicon layer onto said thin oxide layer to form a floating gate region of the memory cell, the floating gate region including an entire top surface; directly nitriding the entire top surface of said floating gate region, thereby forming a barrier layer of silicon nitride oxide on the entire top surface of the floating gate region; depositing a dielectric layer directly on the barrier layer formed by directly nitriding the entire top surface of the floating gate region such that no portion of the dielectric layer contacts the silicon layer; and forming a conductive layer on the dielectric layer; wherein a nitrogen distribution inside the silicon nitride oxide layer, formed by direct nitridation, is no less than 1e22 at/cm