Patent ID: 8539388
Filing Date: 2013-09-17
Classification: G06F

Abstract:
1. A layout system comprising: a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine a corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell, the modified library cell comprises a reduced gate width with respect to the corresponding library cell, wherein the library cell modifying unit is configured to maintain features touching an edge of the corresponding library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell.