Patent ID: 7702883
Filing Date: 2010-04-20
Classification: G06F,Y02D

Abstract:
1. An apparatus, comprising: a plurality of parallel memory units adapted to i) store a full-length number of words and ii) output in parallel an entry, wherein said entry comprises a variable length number of words including a first word including a fixed-length prefix portion comprising entry length information of said entry; an address generator to receive an address of said entry to be read from said plurality of memory units, said address generator coupled to said plurality of memory units to control said plurality of parallel memory units based on the address of said entry to be read and control information, the control information comprising said entry length information; a prefix processor to examine said prefix portion of said first word of said entry stored in said memory units to generate said control information based on said prefix portion, said prefix processor coupled to said address generator to provide said address generator with said control information; and a plurality of output registers coupled to said plurality of memory units to receive a number of words of data read from said memory units equal to said entry length information.