Patent ID: 6704832
Filing Date: 2004-03-09
Classification: G06F

Abstract:
For a peripheral bus interconnect system to be interfaced with a computer and including at least first and second independent peripheral bus signal paths, each of the first and second peripheral bus signal paths having an input and an output peripheral bus connector, and at least one computer peripheral device coupled to each of the first and second peripheral bus signal paths, the improvement comprising a peripheral bus jumper block having a pair of peripheral bus connectors to be respectively mated to the output peripheral bus connector of the first peripheral bus signal path and the input peripheral bus connector of the second peripheral bus signal path, whereby to link said first and second peripheral bus signal paths together so as to be the functional equivalent of a single, continuous peripheral bus signal path, whereby each of the computer peripheral devices coupled to said first and second peripheral bus signal paths can be operated by the computer to which the peripheral bus interconnect system is interfaced.