Patent ID: 6690214
Filing Date: 2004-02-10
Classification: H03K,H03L,Y10S

Abstract:
A delay locked loop (DLL) circuit, comprising:an external clock having a first external clock edge and a second external clock edge; an internal clock having a first internal clock edge and a second internal clock edge; a first phase decision circuit coupled to receive the external clock and the internal clock and providing a first phase decision signal based on a phase relationship between the first external clock edge and the first internal clock edge; a second phase decision circuit coupled to receive the external clock and the internal clock and providing a second phase decision signal based on a phase relationship between the second external clock edge and the second internal clock edge; an arbitrary phase generator circuit coupled to receive the first phase decision signal and provide an adjusted reference clock having a phase based on the value of the first phase decision signal; and a variable pulse width circuit coupled to receive the second phase decision signal and the adjusted reference clock and provide the internal clock having a pulse width based on the value of the second phase decision signal.