Patent ID: 7167943
Filing Date: 2007-01-23
Classification: G06F,G06Q,G07F

Abstract:
1. A memory apparatus attachable to and detachable from a host device, the memory apparatus comprising: an irreversibly writeable memory; and a control circuit that controls operations of writing to and reading from the irreversibly writeable memory; a data area of the irreversibly writeable memory including a plurality of one-time writeable data units for storing data, the data being written to the irreversibly writeable memory by some of the plurality of one-time writeable data units being changed from an initial state and by remaining ones of the plurality of one-time writeable data units remaining in the initial state; the control circuit, in response to receiving a read request, (i) reads all of the data from the data area of the irreversibly writeable memory and then (ii) changes all of the remaining ones of the plurality of one-time writeable data units of the data area from their initial state so that the data cannot be further read.