Patent ID: 6681373
Filing Date: 2004-01-20
Classification: G06F

Abstract:
A method for optimizing an integrated circuit design, said method comprising the following steps:a. identifying a buffer tree in the integrated circuit design, the buffer tree having a plurality of vertices, each representing one of a buffer and an inverter, and also having branches between the vertices, each representing an electrical connection; and b. applying a plurality of optimization devices in a random sequence to the vertices of the buffer tree, wherein said plurality of optimization devices comprises at least two of the following devices: cell type modification device; insertion of one buffer device; insertion of several buffers device, interchange of two grandchildren device; tuminq a grandchild into a child device; turning a child into a grandchild device; interchanging a child and a grandchild device; eliminating two inverters device; removing one buffer device; removing more than one buffer device; and removing two inverters device.