Patent ID: 6172554
Filing Date: 2001-01-09
Classification: G05F

Abstract:
A circuit for providing a bias voltage V1 which is substantially insensitive to variations of a power supply voltage powering the circuit, the circuit comprising:a detector circuit for generating a signal from the power supply voltage and the bias voltage V1, wherein said signal is substantially insensitive to variations in the power supply voltage while being responsive to the bias voltage V1; anda voltage generator for generating the bias voltage V1 on an output terminal, wherein the voltage generator is responsive to said signal such that the detector circuit and the voltage generator are operable to maintain the bias voltage V1 at a substantially constant value over power supply voltage variations;wherein the detector circuit comprises:a bias circuit for biasing a first node to a node voltage, the bias circuit receiving the power supply voltage and the bias voltage V1; anda sensing circuit for generating said signal in response to the node voltage at the first node;wherein the power supply voltage is provided across a power supply terminal and a reference terminal, and the bias circuit comprises:a current source connected between the power supply terminal and the first node, the current source being substantially insensitive to power supply voltage variations; anda resistor connected between the first node and the output terminal of the voltage generator circuit;wherein the current source comprises a first transistor connected between the power supply terminal and the first node, the first transistor being biased such that a current through the first transistor is substantially insensitive to power supply voltage variations;wherein the gate to source voltage of the first transistor is made substantially insensitive to power supply voltage variations;wherein the first transistor is a field effect transistor biased in the saturation mode;wherein the sensing circuit comprises an inverter having an input terminal connected to the first node, the inverter possessing a trip point which is substantially insensitive to power supply voltage variations, whereby the bias voltage V1 is obtained when the node voltage and the trip point of the inverter are substantially the same.