Patent ID: 8909823
Filing Date: 2014-12-09
Classification: G06F

Abstract:
1. A data processing device comprising: a memory; a direct memory access controller comprising a receiving module configured to receive data coming from outside the device and for writing the data in a predetermined portion of the memory, as a main buffer memory; a processing unit programmed to read and process data written by the receiving module in the main buffer memory area as a work area, wherein: the main buffer memory is divided between used space and free space; the processing unit is further programmed to define the work area; the direct memory access controller comprises a buffer memory manager configured to free data written in the main buffer memory, by defining a location of this data as a free space, only when this data is outside the work area; and the direct memory access controller is configured to write data to the free space in parallel with the processing unit accessing data in the work area.