Patent ID: 7109537
Filing Date: 2006-09-19
Classification: H01L

Abstract:
1. A pixel circuit, comprising: a P an N a first P a first PMOS transistor having a source, a drain, and a channel formed in said N a second PMOS transistor having a source, a drain, and a channel formed in said N a first gate electrode formed over a gate oxide over said channel of said first PMOS transistor forming the gate of said first PMOS transistor; a second gate electrode formed over a gate oxide over said channel of said second PMOS transistor forming the gate of said second PMOS transistor; a first NMOS transistor having a drain connected to a first output node, a gate, and a source connected to said source of said first PMOS transistor; a first N a second NMOS transistor having a source connected to said first N a third NMOS transistor having a drain connected to a second output node, a gate, and a source connected to said source of said second PMOS transistor; a second N a fourth NMOS transistor having a source connected to said second N