Patent ID: 6084933
Filing Date: 2000-07-04
Classification: G06F,H03K

Abstract:
A clock generating system comprising:an oscillator located on a chip, for generating a signal having a nominal frequency;a reference clock located off the chip having said nominal frequency;a comparator, having a first input coupled to the oscillator and a second input coupled to the reference clock, for comparing the frequency of the oscillator to the frequency of the reference clock and providing an output signal indicating the difference therebetween; anda clock generator coupled to the comparator and having an input for receiving the output signal from the comparator, wherein the clock generator includes:a plurality of serially connected delay cells having respective output taps; anda multiplexer having inputs coupled to the output taps of the serially connected delay cells and being responsive to the output signal from the comparator for generating a clock signal for use on the chip.