Patent ID: 6031262
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A semiconductor memory device comprisinga plurality of switching transistors each includinga source region formed in a semiconductor substrate,a drain region formed in said semiconductor substrate and spaced from said source region by a channel region, anda gate insulating layer covering said channel region,a plurality of word lines selectively extending over the gate insulating layers of said plurality of switching transistors for serving as respective gate electrodes of said plurality of switching transistors,a plurality of bit lines extending over said plurality of switching transistors and selectively connected to the drain regions of said plurality of switching transistors,an inter-level insulating structure covering said plurality of bit lines and having a plurality of node contact holes open to the source regions of said plurality of switching transistors, respectively, anda plurality of storage capacitors provided over said inter-level insulating structure, each of said plurality of storage capacitors includingan storage electrode electrically connected through one of said plurality of node contact holes to said source region of associated one of said plurality of switching transistors,a dielectric film structure covering said storage electrode, anda counter electrode held in contact with said dielectric film structure,the storage electrodes of said plurality of storage capacitors having respective centers, the center of each storage electrode being substantially equally spaced from the centers of adjacent four storage electrodes.