Patent ID: 6369425
Filing Date: 2002-04-09
Classification: H01L,Y10S

Abstract:
A high-density MOS-technology power device integrated structure comprising a plurality of elementary functional units formed in a semiconductor material layer of a first conductivity type covered by a conductive insulated gate layer sandwiched between two insulating layers, wherein each elementary functional unit comprises:an elongated window formed in said insulated gate layer and in said two insulating layers, having two elongated edges and two short edges, said edges being sealed by insulating material sidewall spacers; a heavily doped elongated deep body region of a second conductivity type formed in the semiconductor material layer and substantially aligned with the edges of the window; two elongated channel regions of the second conductivity type formed in said semiconductor material layer and extending along the elongated edges of said window; and two elongated source regions of the first conductivity type formed in the deep body region along said elongated edges of the window so as not to extend under the insulated gate layer.