Patent ID: 6031407
Filing Date: 2000-02-29
Classification: H03K

Abstract:
A current limiting circuit comprising:a first inverting circuit having an input for receiving an input signal, a fist output for outputting a first output signal and a second output for outputting a second output signal, said second output being distinct from said first output,wherein said first inverting circuit includes a first inverter and a second inverter,said first inverter being coupled to receive said input signal and output said first output signal and having a first p channel transistor, a first n channel transistor and a second n channel transistor coupled between a first potential and a second potential, wherein said first potential is also applied to a gate of said second n channel transistor, andsaid second inverter being coupled to receive said input signal and output said second output signal and having a third n channel transistor, a second p channel transistor and a third p channel transistor coupled between a first potential and a second potential, wherein, the second potential is applied to a gate of said third p channel transistor;a second inverting circuit coupled to said first inverting circuit, said second inverting circuit having a first input for receiving said first output signal, a second input for receiving said second output signal wherein said second input is distinct from said first input and a third output for outputting a third output signal; anda latch circuit coupled to the output of said second inverting circuit, said latch circuit comprising a third inverter and a fourth inverter, each inverter having an input and an out put.