Patent ID: 9170879
Filing Date: 2015-10-27
Classification: G06F,G11C

Abstract:
1. A data scrubbing apparatus for correcting disturb data errors occurring in an array of SMT MRAM memory cells, the data scrubbing apparatus comprising: an error flag bus in communication with error correcting circuitry within the array of memory cells configured for providing an error flag signal indicating a number of detectable and correctable errors occurring in data accessed during one data read operation in a grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells; an error flag detector in communication with error flag bus for receiving the error flag signal and configured for accumulating an error count of detected and corrected errors during one data read operation of the grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells; an address generator configured for regenerating an original address of the data having the error in the grouping of the SMT MRAM memory cells within the SMT MRAM memory array and error correction code bits covering the grouping of SMT MRAM memory cells; and a write back control device in communication with the error flag detector to receive the error count and configured for comparing the error count with a received scrub threshold signal that provides a threshold value for the number of errors within the grouping of SMT MRAM memory cells that are to be tolerated before scrubbing the grouping of the array of SMT MRAM memory cells, wherein the scrub threshold value is less than or equal to a maximum number of errors that are detectable and correctable by an error correction/detection circuit and in communication with the address generator to receive the regenerated original address and wherein the write back control device is configured for controlling writing back of data corrected subsequent to the one data read operation to the grouping of the SMT MRAM memory cells.