Patent ID: 8139433
Filing Date: 2012-03-20
Classification: G06F,Y02D

Abstract:
1. Apparatus comprising a memory controller for controlling a memory device having a clock enable (CKE) input, the memory controller comprising: first circuitry adapted to apply a first CKE signal to the CKE input during a normal operating mode; and second circuitry adapted to apply a second CKE signal to the CKE input during a self-refresh operating mode, wherein, during the self-refresh operating mode: the first circuitry comprises (i) a first output buffer connected to drive the first CKE signal to the CKE input and (ii) first logic circuitry connected to control operations of the first output buffer; the second circuitry comprises (i) a second output buffer connected to drive the second CKE signal to the CKE input and (ii) second logic circuitry connected to control operations of the second output buffer; and the memory controller is adapted to support a power-down transition from the normal operating mode to the self-refresh operating mode, wherein: