Patent ID: 7689880
Filing Date: 2010-03-30
Classification: G11C

Abstract:
1. A test apparatus for testing a plurality of memories under test, comprising: a plurality of test signal feeding sections that are provided in a one-to-one correspondence with the plurality of memories under test, each of the plurality of test signal feeding sections feeding a test signal designed to test a corresponding one of the plurality of memories under test to the corresponding memory under test; a plurality of defect detecting sections that are provided in a one-to-one correspondence with the plurality of memories under test, each of the plurality of defect detecting sections detecting a defect in a corresponding one of the plurality of memories under test when data read from the corresponding memory under test in response to the test signal is different from an expected value; a plurality of first calculating sections that are provided in a one-to-one correspondence with the plurality of memories under test, each of the plurality of first calculating sections calculating a remedy solution for a corresponding one of the plurality of memories under test, the remedy solution remedying the defect in the corresponding memory under test by replacing a defective storage cell in the corresponding memory under test with a backup cell of the corresponding memory under test; and a second calculating section that takes over, from one or more of the plurality of first calculating sections which have not finished calculating the remedy solutions, the unfinished remedy solution calculations, in response to a start of calculations by the plurality of first calculating sections for remedy solutions for a different group of memories under test, and performs the taken over remedy solution calculations.