Patent ID: 7129861
Filing Date: 2006-10-31
Classification: H03H

Abstract:
1. A method for implementing an L:M Fractional Sample Rate Converter (F-SRC), for controlled and direct insertion and cancellation of samples in a processed data stream, the method comprising: receiving an input data stream (DATA_IN) by an input block, processing L signal samples (x(m)) having an input data rate (f generating an interpolated data stream (DATA_IN generating an intermediate data stream (DATA_IMD delivering an output data stream (DATA_OUT) with a low pass and P:1 decimation filter receiving the signal samples from the rate adapting stage, including M signal samples, z(k), having a desired output sample rate (f adapting the input data rate in the rate adapting stage to the output data rate by a direct insertion of repeated samples into the interpolated stream (DATA_IN generating the intermediate stream (DATA_IMD