Patent ID: 6292410
Filing Date: 2001-09-18
Classification: G11C

Abstract:
An apparatus for receiving an external data strobe signal in a high-speed memory device to generate internal data strobe signals used in a write operation therein, comprising:first buffering means, activated by an enable signal, for receiving the external data strobe signal having a series of pulses to output a first internal data strobe signal having a series of pulses, each pulse of the first internal data strobe signal corresponding to a rising edge of each pulse of the external data strobe signal, wherein the first buffering means includes a first delay means for delaying the enable signal in order to generate the first internal data strobe signal; andsecond buffering means, activated by the enable signal, for receiving the external data strobe signal having a series of pulses to output a second internal data strobe signal having a series of pulses, each pulse of the second internal data strobe signal corresponding to a falling edge of each pulse of the external data strobe signal, wherein the second buffering means includes a second delay means for delaying the enable signal in order to generate the second internal data strobe signal and wherein a delay to a corresponding pulse of the first internal data strobe signal from a rising edge of each pulse of the external data strobe signal is substantially identical to a delay to a corresponding pulse of the second internal data strobe signal from a falling edge of each pulse of the external data strobe signal.