Patent ID: 6194953
Filing Date: 2001-02-27
Classification: G05F

Abstract:
A circuit configuration, comprising:a memory cell array having a voltage supply input;a reference voltage generator including:a first constant voltage source having an output supplying a first constant reference voltage;a second constant voltage source having an output supplying a second constant reference voltage; anda switching circuit having a first input connected to said output of said first constant voltage source, a second input connected to said output of said second constant voltage source, and an output;said switching circuit having a first switching state for providing said first constant reference voltage to said output of said switching circuit and a second switching state for providing said second constant reference voltage to said output of said switching circuit;said output of said switching circuit for supplying an internal voltage to said voltage supply input of said memory cell array, said internal voltage being proportional to a voltage selected from the group consisting of said first constant reference voltage and said second constant reference voltage.