Patent ID: 7611956
Filing Date: 2009-11-03
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming a lower insulating layer on a semiconductor substrate; forming a lightly doped semiconductor layer on the lower insulating layer; sequentially forming a dielectric layer and a metal layer on the lightly doped semiconductor layer; forming a metal gate electrode, a capacitor dielectric layer, and an active semiconductor plate having extended portions by patterning the metal layer, the dielectric layer, and the lightly doped semiconductor layer within a first region of the lower insulating layer; forming a metal resistor on the same plane as the metal gate electrode by patterning the metal layer within a second region of the lower insulating layer at the same time the metal layer, the dielectric layer, and the lightly doped semiconductor layer within the first region of the lower insulating layer are patterned; and forming highly doped regions within the active semiconductor plate by implanting impurity ions into the active semiconductor plate, using the metal gate electrode as an ion implantation mask.