Patent ID: 6797542
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A method of fabricating a semiconductor integrated circuit device, comprising the steps of:(a) providing a multi-chip substrate on which a plurality of device forming regions are arranged in a matrix form, the device forming regions each having a chip mounting region and a plurality of leads; (b) mounting semiconductor chips respectively onto the chip mounting regions of the multi-chip substrate; (c) disposing the multi-chip substrate with the semiconductor chips mounted thereon onto a mold surface of a molding die, which mold surface includes a single cavity, and thereafter closing the molding die, while allowing the single cavity to cover all of the plural device forming regions; (d) pressurizing the interior of the cavity upon charging of a sealing resin into the thus-pressurized cavity; and (e) after the step (d), dividing the multi-chip substrate into individual device forming regions.