Patent ID: 9136474
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming semiconductor patterns at regular intervals on a semiconductor substrate, such that spaces between the semiconductor patterns are filled with a lower interlayer insulating layer; forming a lower insulating layer covering the semiconductor patterns and the lower interlayer insulating layer; removing a portion of the lower insulating layer and the lower interlayer insulating layer; forming a contact structure where the portion of the lower insulating layer and the lower interlayer insulating layer was removed, an upper surface of the contact structure being higher than the semiconductor pattern; forming an upper insulating layer that covers the contact structure and the lower insulating layer; selectively removing the upper and lower insulating layers to expose the semiconductor patterns without exposing the contact structure; and forming metal-semiconductor compounds on the exposed semiconductor patterns after removing the upper and lower insulating layers, wherein the selectively removing the upper and lower insulating layers forms first insulating patterns formed between the semiconductor patterns, and a second insulating pattern formed on the contact structure, and wherein a distance spaced between the first insulating patterns is greater than a distance spaced between the semiconductor patterns.