Patent ID: 7159017
Filing Date: 2007-01-02
Classification: H04L

Abstract:
1. In a computer system partitioned into at least two domains, a first domain having at least a first and a second chassis coupled by an intra-domain cable, and a second domain having at least one chassis, each chassis of the first domain coupled to the chassis of the second domain by a first inter-domain cable and a second inter-domain cable, each chassis including a plurality of processor nodes, I/O nodes, and memory nodes, a method for balancing message traffic comprising: receiving a message; identifying, from the message, a destination node and an I/O bit having a specified value indicating whether a source node is an I/O node; responsive to the I/O bit indicating that the source node is an I/O node, routing the message from the first chassis to the second chassis exclusively via the first inter-domain cable and the second inter-domain cable; responsive to the I/O bit indicating that the source node is a non-I/O node and the destination node is a non-I/O node, routing the message from the first chassis to the second chassis via the intra-domain cable.