Patent ID: 7396747
Filing Date: 2008-07-08
Classification: H01L,Y10S

Abstract:
1. A method of forming a semiconductor structure comprising: forming at least one discrete and isolated damaged region beneath a surface of a Si-containing substrate; forming a strained SiGe alloy on at least a portion of said surface of said Si-containing substrate containing said underlying at least one discrete and isolated damaged region; annealing at a temperature of about 700° C. or above to cause substantial relaxation of the strained SiGe alloy above said at least one discrete and isolated damaged region via defect initiated strain relaxation, while leaving said strained SiGe alloy unchanged in regions not directly above said at least one discrete and isolated damaged region, wherein during said annealing platelets and dislocation loops are formed that extend to a bottom surface of the strained SiGe alloy; and forming a strained semiconductor cap on said strained SiGe alloy that has been substantially relaxed and an unstrained semiconductor cap on said remaining strained SiGe alloy.