Patent ID: 8887106
Filing Date: 2014-11-11
Classification: G03F,G06F

Abstract:
1. A method of generating a bias-adjusted layout design of a conductive feature, the conductive feature being a portion of an integrated circuit, the method comprising: receiving a layout design of the conductive feature; determining, by a hardware processor, if a geometry configuration of the layout design of the conductive feature is within a first set of predetermined criteria or a second set of predetermined criteria different from the first set of predetermined criteria, wherein at least one of the first set of predetermined criteria or the second set of predetermined criteria comprises a threshold ratio or a feature width of a layout design of a neighboring conductive feature; generating the bias-adjusted layout design of the conductive feature according to a first layout bias rule after a determination that the geometry configuration of the layout design of the conductive feature is within the first set of predetermined criteria; and generating the bias-adjusted layout design of the conductive feature according to a second layout bias rule different from the first layout bias rule after a determination that the geometry configuration of the layout design of the conductive feature is within the second set of predetermined criteria.