Patent ID: 6291852
Filing Date: 2001-09-18
Classification: B82Y,G11C,H01L

Abstract:
A semiconductor memory cell array comprising:a plurality of data lines;a plurality of word lines; anda plurality of memory cells, each of said memory cells comprising:a first field effect transistor having a first source region connected to a corresponding data line of said plurality of data lines, a first drain region, a first channel region between said first source region and said first drain region, and a first gate electrode located opposite to said first channel region, said first gate electrode being connected to a corresponding word line of said plurality of word lines; anda second field effect transistor having a second source region connected to said first drain region, a second drain region, a second channel region between said second source region and said second drain region, a second gate electrode located opposite to said second channel region, and a carrier confinement region controlled by said second gate electrode, said second gate electrode being connected to said first drain region.