Patent ID: 6756827
Filing Date: 2004-06-29
Classification: H03K

Abstract:
An integrated circuit comprising:an oscillator coupled to receive a reference clock signal and to generate pulses having a frequency which is a multiple of a frequency of the reference clock signal; a storage device coupled to receive a clock control signal that is used to mask a clock output signal, the storage device also coupled to receive the pulses from the oscillator to synchronize the clock control signal with the pulses from the oscillator for output from the storage device; a logic circuit coupled to receive the synchronized clock control signal output from the storage device and also to receive the pulses from the oscillator and to output pulses from the oscillator as the clock output signal, but to mask the clock output signal if the clock control signal indicates a mask condition, the synchronizing of the clock control signal to the pulses to maintain constant pulsewidth of the pulses of the clock output signal independent of timing of the clock control signal received; and a core coupled to receive and to be clocked by the clock output signal.