Patent ID: 7376794
Filing Date: 2008-05-20
Classification: G06F

Abstract:
1. A multi-processor system that conforms to a cache coherency protocol, the system comprising: a plurality of data fills provided to a source processor from a plurality of processors of the multi-processor system in response to a source request for a data fill associated with a cache line and in response to a cache miss by the source processor, at least two of the plurality of data fills being speculative fills that are provided from at least two different processors; a coherent signal generated by the multi-processor system that provides an indication of which data fill of the plurality of data fills is the coherent data fill; and wherein the speculative fills are copies of the requested data fill that have an undetermined coherency states, the source processor continuing execution of program instructions employing a given speculative fill of the at least two speculative fills prior to receipt of the coherent signal.