Patent ID: 6662133
Filing Date: 2003-12-09
Classification: G06F

Abstract:
A method for repairing a plurality of arrays on a processor with an on chip built in self test engine on the processor, the method comprising the steps of:selecting a subset of the plurality of arrays for testing; sending data patterns from the on chip built in self test engine to the subset of the plurality of arrays on the processor at a plurality of operating parameters; receiving a response at the on chip built in self test engine from the subset of the plurality of arrays at the plurality of operating parameters; comparing the response from the subset of the plurality of arrays to an expected response using the on chip built in self test engine; determining a failing subset of arrays in response to the response from the subset of the plurality of arrays being different from the expected response; and in response to determining the failing subset of arrays, repairing said failing subset of arrays by scanning data into the failing subset of arrays, wherein the scanned data is used to establish repair values for the failing subset of arrays.