Patent ID: 8234431
Filing Date: 2012-07-31
Classification: G06F

Abstract:
1. A method for handling interrupts within a multi-core processor having a plurality of processor cores, the method comprising: initializing a core interrupt mask to specify each of the plurality of processor cores as either an available processor core or an unavailable processor core based on a status associated with each of the plurality of processor cores; setting the core interrupt mask to specify one or more of the plurality of processor cores as unavailable processor cores based on one or more setting criteria; receiving an interrupt associated with an interrupt service routine; evaluating the core interrupt mask to identify one or more available processor cores from the plurality of processor cores; and assigning the interrupt service routine associated with the received interrupt to at least one of the one or more available processor cores; wherein setting the core interrupt mask to specify one or more of the plurality of processor cores as unavailable processor cores based on one or more setting criteria comprises at least one of