Patent ID: 8598466
Filing Date: 2013-12-03
Classification: G01R,H05K,Y10T

Abstract:
1. A laminar circuit interconnect device comprising: a first laminar structure including an insulative fiber layer and at least one first conductive layer, a selectively patterned release layer overlying the first laminar structure; and a second laminar structure including an insulative fiber layer and at least one second conductive layer, the second conductive layer including plural conductive pads located on an outer surface of the device to provide a circuit interconnect; the selectively patterned release layer extending substantially coextensive with the first laminar structure except in a bounded region thereof configured to define a contact array boss, the first laminar structure, the second laminar structure, and the release layer being stacked and adhered together into a parallel planar unitary structure, wherein a perimetric portion of the second laminar structure is configured to be routed and removed from the second laminar structure to leave a boss extending upwardly from the first laminar structure, the boss and the first laminar structure remaining adherently intact to form an embossed unitary interconnect device configured to interconnect with an external circuit via the plural conductive pads.