Patent ID: 6181757
Filing Date: 2001-01-30
Classification: G06F,H03L,H04L

Abstract:
Retiming means for retiming an incoming data stream, the retiming means comprising:a clock circuit adapted to produce a plurality of clock signals having the same frequency but differing phases, wherein said same frequency is substantially equal to the frequency of the incoming data stream; andsignal processing means for receiving both the incoming data stream and the plurality of clock signals and for outputting a retimed data signal corresponding to the incoming data stream retimed in accordance with a selected one of the plurality of clock signals, wherein the signal processing means comprises:a first plurality of flip-flops each having a clock input for receiving the incoming data stream and a data input for receiving a respective clock signal of the plurality of clock signals, and an output;a plurality of logic circuits each having a pair of inputs coupled to outputs of respective pairs of flip-flops of the first plurality of flip-flops, and an output;a first selection circuit coupled to the outputs of the plurality of logic circuits and to the plurality of clock signals and providing the selected one of the plurality of clock signals;a second plurality of flip-flops each having a data input for receiving the incoming data stream and a clock input for receiving a respective clock signal of the plurality of clock signals, and an output; anda second selection circuit coupled to the outputs of the second plurality of flip-flops and to the outputs of the plurality of logic circuit and providing the retimed data signal.