Patent ID: 6266733
Filing Date: 2001-07-24
Classification: G06T

Abstract:
A method for arranging voxel data in DRAM memory modules to avoid idle cycles during data transfer in a volume rendering system, thereby permitting real time volume rendering by data transfer at the maximum burst rate of the DRAM memory modules, comprising the steps of:arranging voxel data from a volume data set into mini-blocks;providing a number of DRAM modules each having a number of DRAM memory banks; and,within each DRAM module, assigning mini-blocks to the memory banks thereof so that consecutively accessed mini-blocks are assigned to different banks within the associated DRAM module, said mini-blocks being assigned both to a specific DRAM and a specific bank within a DRAM in a two-level storage system, such that upon consecutive accessing of said banks, idle cycles during data transfer from the associated DRAM module are avoided.