Patent ID: 7180972
Filing Date: 2007-02-20
Classification: G06F

Abstract:
1. Interface circuitry for conveying data signals from an input port to utilization circuitry comprising: phase compensation circuitry having first and second clock inputs, and being constructed to store, in synchronism with a first clock signal applied to the first clock input, data derived from the input port, and to subsequently output that data to the utilization circuitry in synchronism with a second clock signal applied to the second clock input, wherein the utilization circuitry comprises clock signal distribution circuitry, and wherein the interface circuitry further comprises: first circuitry that is able to apply a clock signal from the interface circuitry to the clock signal distribution circuitry for distribution by that circuitry; and second circuitry that is able to apply a clock signal that has been distributed by the clock signal distribution circuitry to the phase compensation circuitry as the second clock signal.