Patent ID: 7925840
Filing Date: 2011-04-12
Classification: G06F,Y02D

Abstract:
1. A data processing apparatus comprising: a plurality of processing units for performing data processing operations requiring access to data in shared memory; at least two of said processing units having a cache associated therewith for storing a subset of said data for access by that processing unit; cache coherency circuitry for employing a snoop-based cache coherency protocol to ensure data accessed by each processing unit is up-to-date, on issuance of an access request by one of said processing units, the cache coherency circuitry determining whether a snoop process is required having regard to the snoop-based cache coherency protocol; snoop control storage for defining a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches; and a snoop unit, responsive to the cache coherency circuitry determining that said snoop process is required, to reference the snoop control storage to identify, having regard to one or more properties of the access request, the snoop scheme to be employed to perform said snoop process.