Patent ID: 8487400
Filing Date: 2013-07-16
Classification: H01L,Y10S

Abstract:
1. An integrated circuit chip comprising: a silicon substrate; multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer; a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and a capacitor on said polymer layer, wherein said capacitor comprises a lower conductive plate on said polymer layer, a third dielectric layer on said lower conductive plate, and an upper conductive plate on said third dielectric layer, wherein said lower plate is connected to said contact point through said second opening, wherein said lower conductive plate has a thickness between 0.5 and 20 micrometers, wherein said upper conductive plate has a thickness between 0.5 20 micrometers.