Patent ID: 6242283
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A wafer level packaging process of semiconductor, comprising:providing a substrate, having a first surface and a second surface wherein the substrate is comprised of a plurality of carriers densely disposed in series, and each of the carriers has an opening located at a center portion of the carrier, and a plurality of bonding fingers is disposed on the second surface at a periphery of the opening, and a plurality of connecting points is disposed on outer edges of the bonding fingers which are electrically connected to the connecting points;providing a wafer comprised of a plurality of dies wherein an active surface of the die has a plurality of bonding pads;providing an adhesive layer to bond the first surface of the substrate to the active surface of the die wherein each of the carriers corresponds to each of the dies, and the bonding pads correspond to the openings of the carriers;performing a wire bonding process to form a plurality of bond wires to make electrical connections between the bonding pads of the dies and their corresponding bonding fingers of the carriers;performing an encapsulating process by using a molding compound to fill the openings and to encase the bond wires, the bonding pads, and the bonding fingers; andperforming a die sawing process to form a plurality of complete packages of a wafer level packaging.