Patent ID: 6492236
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising the steps of:patterning a gate electrode formed on a thin insulating film on a silicon substrate, into a predetermined shape and a predetermined size and then forming source and drain regions having a relatively low concentration by an ion implantation method using the gate electrode as a mask; forming a thick insulating film on the gate electrode, thickly applying a positive resist onto an entire surface of the thick insulating film, and then exposing the positive resist at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developing the exposed positive resist; etching the thick insulating film by an amount substantially corresponding to a film thickness thereof by anisotropic etching, using as a mask portions of the positive resist partially remaining in a step portion; removing the remaining portions of the positive resist and then introducing an impurity having a high concentration into the gate electrode and the source and drain regions of an MOS transistor using a remaining portion of the thick insulating film as a mask; and forming a silicide layer on exposed portions of the gate electrode and the source and drain regions of the MOS transistor, respectively, in a self-alignment manner to thereby obtain a high-melting metallic silicide structure.