Patent ID: 6549469
Filing Date: 2003-04-15
Classification: G06F

Abstract:
A semiconductor memory system having a set of semiconductor memory devices of which the read and write operations can be controlled by commands received from an external CPU, comprising:a semiconductor memory device having a chip select signal input, an output enable signal input, a write enable signal input, address inputs and data I/O ports, and arranged so that data reading and writing at high speeds is performed through the interface of the buses connected to the address inputs and the data I/O ports; a semiconductor memory device having a chip select signal input, an output enable signal input, a write enable signal input, address inputs and data I/O ports, and arranged so that data reading and writing is controlled by commands provided via the data I/O ports; and a controller arranged responsive to commands from the CPU for controlling the read and write operation of each of the semiconductor memory devices, wherein a single write operation of the CPU to the controller can simultaneously write the same data into the semiconductor memory devices.