Patent ID: 6510013
Filing Date: 2003-01-21
Classification: G11B,H03L

Abstract:
A phase-synchronizing circuit, comprising:a clock generator generating a clock signal; a phase-error detection circuit detecting a first phase-error of said clock signal based on an output signal formed in response to said clock signal; a phase control circuit controlling the phase of said clock signal in response to a phase-error supplied thereto; a phase-error value creation circuit creating a second phase-error value, said second phase-error value being determined so as to minimize a time needed for establishing a phase synchronization of said clock signal; and a selection circuit selectively supplying said first phase-error value or said second phase-error value to said phase control circuit as an output signal representing said phase-error, said phase control circuit thereby adjusting a phase of said clock signal in response to said output signal of said selection circuit, wherein said selection circuit selectively supplied a fixed phase-error value to said phase control circuit during a first interval, said selection circuit further supplying second phase-error value to said phase control circuit during a second interval after said first interval, said selection circuit further supplying said fixed phase error value selectively to said phase-control circuit during a third interval after said second interval, and said selection circuit further supplying said first phase-error value to said phase control circuit during a fourth interval after said third interval.