Patent ID: 9053805
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells; a plurality of bit lines, each of which is electrically connected to a string of the memory cells; a sense module provided for each of the bit lines, wherein each sense module includes a sense transistor that is configured to be turned on and off during a reading operation according to whether or not data is stored in a memory cell that is targeted by the reading operation, the sense transistor having a gate that is electrically connected to a sense node, the sense node being electrically connected to a first node to which a first signal is applied and to a second node, which is at a voltage level different from that of the first node, through a series of transistors including the sense transistor and first and second transistors, which when turned on, cause the sense node to be discharged to a voltage level that is equal to a first voltage level plus a threshold voltage level of the sense transistor; and a control circuit configured to turn on the first and second transistors and then, when the sense node has been discharged to the first voltage level plus the threshold voltage level of the sense transistor, to electrically connect the sense node to a corresponding bit line.