Patent ID: 7529137
Filing Date: 2009-05-05
Classification: G11C,H01L

Abstract:
1. A method of operating a memory array comprising a plurality of memory cells disposed on a semiconductor substrate, wherein each of said memory cells comprises: a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a multilayer tunnel dielectric structure, having a bottom layer in contact with the channel region, the tunnel dielectric structure comprising at least one layer having a hole tunneling-barrier height smaller than that of the bottom layer; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer; the method comprising: applying a bias arrangement including a negative gate voltage on the gate electrode to induce hole tunneling through the tunnel dielectric structure to lower a threshold voltage of at least one of the plurality of memory cells to an erase state level; programming at least one of the plurality of memory cells by applying a biasing arrangement to induce electron tunneling through the tunnel dielectric structure to increase a threshold voltage to a program state level; and reading at least one of the plurality of memory cells by applying a voltage between the erased state level and the programmed state level.