Patent ID: 7930165
Filing Date: 2011-04-19
Classification: G06F

Abstract:
1. A method for emulation of a target programmable unit, which has at least one CPU, by means of an external emulation device, which is coupled to the target programmable unit by means of a communication link, the method comprising the following steps: transferring predetermined initialization data through the communication link to the emulation device, with which initialization data the target programmable unit has initialized itself and/or has been initialized, for initializing the emulation; transferring through the communication link to the emulation device, a CPU clock signal and, in a defined relationship with the CPU clock signal, the following emulation data: data read by the CPU from a data bus of the target programmable unit, those external events that have an influence on a program counter, optionally, periodically created complete or partial copies of the register memory, and, optionally, one or more data type signals; emulating the target programmable unit in the external emulation device using the transferred emulation data; ascertaining respective trace data from the emulation in the external emulation device; storing and/or outputting the trace data; deriving, in the target programmable unit and in the external emulation device, respective target integrity-control data and emulation integrity-control data from respective target-internal data and emulation-internal data, the target-internal data comprising or being indicative of data transferred on a target-internal bus connecting the CPU in the target programmable unit with a memory and peripheral units in the target programmable unit, and the emulation-internal data comprising data transferred on an emulation-internal bus connecting the CPU in the emulation device with a memory in the emulation device; transferring the derived target integrity-control data from the target programmable unit to the external emulation device; and providing the target programmable unit with a multiply redundant processing system that has a plurality of at least two redundant control units in a parallel configuration, each control unit comprising one CPU and associated peripheral units; providing a corresponding number of redundant emulation devices connected in parallel in a corresponding multiply redundant emulation processing system, each emulation device being connected with one corresponding control unit; generating computing results in parallel at each of the redundant control units and allocated emulation devices; deriving respective target integrity-control data and emulation integrity-control data at each of the redundant control units and allocated emulation devices; comparing the respective target integrity-control data and the respective emulation integrity-control data for each combination of one control unit and its allocated emulation device; generating a respective integrity-warning signal if the respective target integrity-control data and the corresponding emulation integrity-control data is not identical for a combination of one control unit and its allocated emulation device; selecting a computing result generated at one of the redundant control units for outputting, using a selection criterion that excludes any computing result, which is associated with the integrity-warning signal.