Patent ID: 6271087
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device on a semiconductor substrate, comprising the steps of:forming a plurality of multi-layer structures on the semiconductor substrate to form core and peripheral regions, the plurality of multi-layer structures including local interconnect gate contacts;forming sidewall spacers around the plurality of the multi-layer structures;forming source and drain regions in the semiconductor substrate adjacent the sidewall spacers;forming a stop layer over the semiconductor substrate, including the plurality of multi-layer structures, the sidewall spacers, and the source and drain regions;forming a dielectric layer over the stop layer,depositing a first contact mask over the dielectric layer;processing the first contact mask over the core and peripheral regions to expose portions of the dielectric layer;removing portions of the dielectric layer and portions of the stop layer to expose the semiconductor substrate between the plurality of multi-layer structures and portions of the plurality of multi-layer structures in the core and peripheral regions to form core and peripheral contact openings;removing the first contact mask;depositing a second contact mask over the dielectric layer and in the core and peripheral contact openings;processing the second contact mask to reopen portions of the multi-layer structures and the peripheral contact openings in the peripheral region and to cover the multi-layer structures in the core region;removing portions of the multi-layer structures in the peripheral region using the second contact mask to expose the local interconnect gate contacts;removing the second contact mask;depositing a conductive material over the dielectric layer and in the core and peripheral contact openings; andremoving the conductive material over the dielectric layer whereby the conductive material is left isolated in the core and peripheral contact openings to respectively form core contacts and peripheral local interconnects.