Patent ID: 6440841
Filing Date: 2002-08-27
Classification: H01L,Y10S

Abstract:
A method of fabricating an interconnect, comprising:providing a semiconductor substrate having a conducting area; forming a dielectric layer on the semiconductor substrate, the dielectric layer having a via opening exposing the conducting area; forming a conformal wetting layer comprising titanium on the via opening; forming an Alâ€”Siâ€”Cu alloy layer on the conformal wetting layer by a sputtering process at a temperature in a range from about 0Â° C. to about 200Â° C., the Alâ€”Siâ€”Cu alloy layer containing about 0.5 weight % to about 1 weight % of silicon and about 0.4 weight % to about 0.6 weight % of copper, and the Alâ€”Siâ€”Cu alloy layer being formed without any significant generation of AlTi3 byproducts; and forming an Alâ€”Cu alloy layer on and adjacent to the Alâ€”Siâ€”Cu alloy layer to fill the via opening by a sputtering process at a temperature in a range from about 380Â° C. to about 450Â° C., the Alâ€”Cu alloy layer containing about 0.4 weight % to about 0.6 weight % of copper, wherein the aluminum in the Alâ€”Cu alloy layer does not react with titanium in the wetting layer to form AlTi3 byproducts.