Patent ID: 6330202
Filing Date: 2001-12-11
Classification: G11C

Abstract:
A data-rewritable semiconductor memory device comprising:a memory array including a plurality of memory cells arranged in a matrix of rows and columns, word lines provided correspondingly to respective rows, and pairs of bit lines provided correspondingly to respective columns;a sense amplifier provided correspondingly to each pair of bit lines to amplify potential difference generated between bit lines of the corresponding bit line pair;first and second transistors provided correspondingly to each pair of bit lines and having respective first electrodes connected to respective ends of bit lines of the corresponding bit line pair;a third transistor provided correspondingly to each first transistor and having a first electrode connected to a second electrode of the corresponding first transistor and a second electrode receiving a write mask signal;a write data line provided commonly to a plurality of said second and third transistors and connected to a second electrode of each second transistor and an input electrode of each third transistor;a row decoder selecting any of said word lines according to a row address signal to activate each memory cell corresponding to the selected word line;a column decoder selecting any of said pairs of bit lines according to a column address signal to render conductive the first and second transistors corresponding to the selected pair of bit lines; anda write control circuit writing external data into the memory cell activated by said row decoder via the first and second transistors rendered conductive by said column decoder;said write control circuit setting both of said write mask signal and said write data line at a first logic level to render said third transistor nonconductive when said external data is a first logic,said write control circuit setting said write mask signal and said write data line at first and second logic levels respectively to render said third transistor conductive when said external data is a second logic, andsaid write control circuit setting both of said write mask signal and said write data line at the second logic level to render said second and third transistors nonconductive if writing of said external data is not performed.