Patent ID: 6239649
Filing Date: 2001-05-29
Classification: H01L,H03K

Abstract:
A complementary pass gate logic circuit including a plurality of switched body SOI unit cells comprising:at least four switched body SOI unit cells each including at least two FET devices with the gate of one FET device connected to the gate of a second FET device;a first logic signal A input means connected to a first one of said switched body SOI unit cells;a second logic signal B input means connected to said first one and to second and a third ones of said switched body SOI unit cells;a third logic signal NOT A input signal means connected to said third switched body SOI unit cell;a fourth logic signal NOT B input means connected to said second and to a fourth one of said switched body SOI unit cells;a first inverter buffer circuit connected to the output of said first and second switched body SOI unit cells to provide a NOT Q=(NOT A).times.(NOT B) output logic signal; anda second inverter buffer circuit connected to the output of said third and fourth switched body SOI unit cells to provide a Q=(A).times.(B) output logic signal.