Patent ID: 6513087
Filing Date: 2003-01-28
Classification: G06F

Abstract:
A bus transfer apparatus for receiving a packet and repeating the received packet, wherein the packet comprises a PREFIX portion indicating the head of the packet, a DATA portion storing data, and an END portion indicating the end of the packet,the apparatus comprising: a control circuit for receiving the packet and outputting the PREFIX portion of the packet as a control signal; a counter for counting a time period during which the control circuit outputs the PREFIX portion, and outputting a counter full signal when the time period reaches a predetermined lower limit; an address pointer for determining a read address in response to the counter full signal; a data buffer for holding the DATA portion of the packet and outputting the DATA portion in accordance with the read address; an encoder for converting the DATA portion output from the data buffer to a predetermined format; and a first selector for selecting either the PREFIX portion output from the control circuit or the DATA portion output from the encoder, wherein the output signal from the first selector is switched from the PREFIX portion of the packet to the DATA portion of the packet after the counter full signal is output from the counter.