Patent ID: 9171861
Filing Date: 2015-10-27
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a first select transistor; a first dummy transistor coupled between a bit line and the first select transistor; a second select transistor; a second dummy transistor coupled between a common source line and the second select transistor; and main cell transistors coupled between the first and second select transistors, wherein each of the first and second dummy transistors, the first and second select transistors and the main cell transistors includes a portion of a vertical channel layer, a tunnel insulating layer surrounding the vertical channel insulating layer surrounding the charge storage layer and a conductive layer surrounding the blocking insulating layer, the vertical channel layer being extended in a direction intersecting a substrate, and wherein an impurity concentration of a first portion of the vertical channel layer, included in each of the first and second dummy transistors, is different from an impurity concentration of a second portion of the vertical channel layer, included in each of the first and second select transistors and each of the main cell transistors.