Patent ID: 9076847
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. A method of forming a wiring structure for an integrated circuit device, the method comprising: forming one or more copper lines within an interlevel dielectric (ILD) layer; masking selected regions of the one or more copper lines such that first portions of the one or more copper lines are covered and second portions of the copper lines are not covered so as to define exposed regions, the masking selected regions comprising forming a sacrificial hardmask layer over the ILD layer and one or more copper lines, and patterning and removing portions of the sacrificial hardmask layer; selectively plating metal cap regions over only the exposed regions of the one or more copper lines such that the metal cap regions are not initially plated over the covered portions of the one or more copper lines; following the plating of the metal cap regions over the exposed regions of the one or more copper lines, removing remaining portions of the sacrificial hardmask layer; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines, and the ILD layer.