Patent ID: 6451669
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A method of forming a metallization level of an integrated circuit, comprising acts of:forming metal areas of a metallization level, including a first metal area and a second metal area, laterally separated by a first insulating layer; removing at least a portion of the first insulating layer, through a mask, to leave in place guard areas of the first insulating layer laterally surrounding the first metal area and so that the second metal area is not laterally surrounded by the first insulating layer and; depositing the second insulating layer, wherein the act of depositing includes one of depositing a second insulating layer so that gaps are formed between neighboring metal areas and depositing a second insulating layer of porous material; forming at least one via through the second insulating layer; and contacting the first metal area, but not the second metal area, to the at least one via.