Patent ID: 6521540
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A method of fabricating self-aligned contacts (SAC) to source/drain of field effect transistors (FET's) on a semiconductor substrate, for closely spaced gates and widely spaced gates, the method comprising:providing a semiconductor substrate having device areas; forming a gate oxide on said device areas; depositing a polysilicon layer on said device areas and elsewhere on the substrate, the polysilicon layer being doped and activated; providing appropriate patterning, etching, and depositions to form a stacked gate electrode polycide structure, consisting of gate oxide, polysilicon gate and metal silicide; providing formation of gate insulating sidewall spacers; forming by ion implantation lightly doped source/drain areas; providing a salicidation process for source/drains and polysilicon gates; depositing simultaneously a non-conformal refractory insulating layer over said stacked gate electrode structures that are closely spaced, and, at the same time, a conformal refractory insulating layer over said stacked gate electrode structures, that are widely spaced; depositing simultaneously a conformal thick layer of refractory insulating layer on said non-conformal insulating layer, and, at the same time, on said conformal insulating layer to planar the entire substrate surface simultaneously; patterning the widely spaced gates and self-aligned contacts (SAC) with a unique photolithography mask used for this purpose; opening the widely spaced self-aligned contacts (SAC) to source/drain and gates by a two step etch; etching in step one the thick conformal insulating layer, while stopping on the conformal insulating layer; etching in step two, using different etch chemistry, the conformal insulating layer over the widely spaced source/drain areas, as well as, removing said insulator over the widely spaced gate stack; patterning the closely spaced gates and closely spaced self-aligned contacts (SAC) with a special photolithography mask for this purpose; opening the closely spaced self-aligned contacts (SAC) to source/drain and gates by a two step etch; etching in step one the thick conformal insulating layer, while stopping on the non-conformal insulating layer; etching in step two, using different etch chemistry, the non-conformal insulating layer over the closely spaced source/drain areas, while leaving sufficient insulator over the closely spaced gate stack for isolation; providing patterning and etching to open contact to the polysilicon gate electrodes; depositing by preferential or selective chemical vapor deposition (CVD) a metal layer, forming metal plugs, in the open silicon areas; thus self-aligned electrical contacts (SAC) are formed to the source/drain areas and to the gate electrodes thereby completing said field effect transistors.