Patent ID: 6310378
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A high voltage, semiconductor-on-insulator electronic device, comprising:a substrate;a buried oxide layer formed on the substrate, the buried oxide layer having a buried oxide layer thickness;a semiconductor layer formed on the buried oxide layer, wherein the semiconductor layer further comprises in lateral sequence a source region, a body region, an offset region, a thin drift region and a drain region;a drift region insulating layer formed on the drift region next to the gate oxide layer;a further insulating layer formed on the source, body and offset regions next to the drift region insulating layer, which further insulating layer forms a gate oxide layer on at least the source and body regions;a gate region formed on the further insulating layer and a portion of the drift region insulating layer;the drift region having a lateral length L and the offset region having a lateral length D; the length L+D approximately describing the lateral distance between the body and drain regions; the drift region having a thickness T.sub.drift, and the offset region having a thickness T.sub.offset, both thicknesses T.sub.drift and T.sub.offset substantially perpendicular to said lateral dimension of said semiconductor layer; the thickness of the offset region T.sub.offset being thicker than the thickness of the drift region T.sub.drift ; and the semiconductor layer having a substantially linear doping profile between the body and drain regions, from a minimum value in the offset region adjacent to the body region, to a maximum value in the thin drift region adjacent to the drain region.