Patent ID: 7336137
Filing Date: 2008-02-26
Classification: H03L

Abstract:
1. A PLL frequency setting circuit in which a channel number and a frequency set value has a relation such that the frequency set value of k+m+n bits set in a PLL circuit increases in accordance with an increase in a channel number and, every time the channel number increases by x (x is an integer equal to or larger than 2), a value of lower-order n bits of the frequency set value returns to an initial value and a value of intermediate m bits thereof increases by one, the PLL frequency setting circuit comprising: a table constituted by a memory in which a quotient and a remainder calculated by dividing a number, which is calculated by adding the channel number to an integer “a” defined based on the relation between the channel number and the frequency set value, by x are set as y and z, respectively, the channel number is set as an address, and y and z are stored as data of the address; an adding unit that adds the data y read out from the table when the channel number is given as an address signal and an initial value of the intermediate m bits of the frequency set value and outputs an added value as a signal of the intermediate m bits of the frequency set value; and a selecting unit that selects a corresponding value out of the x kinds of values defined in advance as a value of the lower-order n bits of the frequency set value in accordance with the data z read out from the table when the channel number is given as an address signal and outputs the value as a signal of the lower-order n bits of the frequency set value.