Patent ID: 7115472
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. A process for manufacturing an array of electrically programmable dual charge storage location memory cells, comprising the steps of: forming insulated gate stripes over a semiconductor substrate; forming charge-storage elements over the substrate surface and adjacent to sides of the insulated gate stripes, the charge-storage elements comprising a layer of charge-trapping material sandwiched between opposing layers of a dielectric material; forming side control gates over each of the charge-storage elements; forming bit line diffusions in the substrate between the insulated gate stripes extending parallel thereto; forming word lines transversal to the insulated gate stripes electrically connecting the side control gates and the insulated gate stripes; and removing the insulated gate stripes and the charge-storage elements in regions between the word lines to form physically separated insulated gates and charge-storage elements for the memory cells of the array.