Patent ID: 9197224
Filing Date: 2015-11-24
Classification: H03L,H04L

Abstract:
1. A circuit for a combined phase detector, comprising: a tri-state phase frequency detector that includes: a charge pump that receives the first output signal and the second output signal, and that outputs a fourth output signal; and a sub-sampling phase detector that receives the reference signal and a fourth input signal, and that outputs a fifth output signal, wherein the fifth output signal and the fourth output signal are coupled together, wherein the fourth output signal changes in response to changes in the first output signal and the second output signal when a time difference between corresponding edges of the first input signal and the reference input signal is less than one-half T wherein the tri-state phase frequency detector and charge pump and the sub-sampling phase detector are configured so that, at all times, a maximum current of the fifth output signal is smaller than three times a charge pump current of the tri-state phase frequency detector and charge pump divided by the value of four times the ratio of the frequency of the fourth input signal and the frequency of the reference signal.