Patent ID: 6219756
Filing Date: 2001-04-17
Classification: G06F,G11C

Abstract:
Addressing circuitry for a register file having a plurality of register arrays, and having a multiport configuration in which a read port and a write port are mounted, and a plurality of read accesses and a plurality of write accesses independently and concurrently are made through the ports, wherein the plurality of register arrays are classified into a plurality of banks every predetermined number of words, and the plurality of banks being respectively provided with a sense amplifier, said addressing circuitry comprising:an in-bank word selecting decoder, directly connected to each one of the plural banks, to decode partial bits of an address for specifying a word to be read, and select a word corresponding to a result of decoding so as to read the word from the register array in each of the banks;a bank selecting decoder to decode remaining bits of the address so as to specify the bank corresponding to a result of decoding; anda multiplexer to take the word selected by the in-bank selecting decoder and amplified by the sense amplifier from each of the plurality of banks, and select a word from the bank specified by the bank selecting decoder from among the words input by the number of banks so as to output the word to the read port.