Patent ID: 7725665
Filing Date: 2010-05-25
Classification: G06F

Abstract:
1. A data processor comprising: a central processing unit; and a memory controller capable of controlling an external memory, wherein the memory controller is adapted to be coupled to the memory which has a buffer to store predetermined size data, the predetermined size data includes data from an address range corresponding to low order side bits of an address signal, the memory controller being further adapted to perform a burst operation between the buffer and the data processor, wherein the memory controller outputs a chip enable signal, an output enable signal, and the address signal to the memory via an external bus to control the memory, wherein the memory controller continuously outputs the chip enable signal to the memory, even when the memory controller detects an access request exceeding the address range of data stored in the buffer, wherein the memory controller includes a register having: a field to specify a burst frequency, a field to specify a bus width of the external bus, a field to specify an access time after a first burst, a field to specify a memory type of the memory, a field to specify a first number of wait cycles to be inserted between assertion of the chip enable signal and assertion of the output enable signal, and a field to specify a second number of wait cycles to be inserted between assertion of the output enable signal and a read of data, wherein the memory controller includes a burst counter to count address increments, and wherein when an access request exceeding the address range of the data in the buffer is detected, the burst operation is temporarily stopped to wait for data to be read into the buffer.