Patent ID: 9088287
Filing Date: 2015-07-21
Classification: H03K

Abstract:
1. A divided clock generation device, comprising: a chip selection flip-flop to generate a chip selection signal synchronized with an internal clock signal; a clock divider to generate second divided clock signals including a second divided even clock signal and a second divided odd clock signal, the clock divider to generate the second divided clock signals based on a first divided clock signal; and a clock comparator to select one of the second divided clock signals based on the chip selection signal, wherein the clock divider is to divide the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals, wherein the clock divider is to generate the second divided clock signals in synchronization with a predetermined edge of the first divided clock signal or a first divided clock bar signal, the first divided clock bar signal complementary to the first divided clock signal.