Patent ID: 6101625
Filing Date: 2000-08-08
Classification: H03M

Abstract:
An error correcting system comprising:a data supplying unit for continuously supplying a subframe data corresponding to a half of each of frames, wherein a frame data for one frame is formed of bit data of N rows and N columns and said subframe data is formed of bit data of N/2 rows and N columns and is composed of a data section and an error correction code section for said data section;a frame memory unit including first to third subframe memories; and;an error detecting/correcting unit for storing said subframe data, which is supplied continuously from said data supplying unit and which is subjected to a first row direction error detecting and correcting process, sequentially and circularly in said first to third subframe memories, for performing a column direction error detecting and correcting process to first and second subframe data respectively stored in said first and second subframe memories as first and second halves of a frame data for a first frame, and then performing a second row direction error detecting and correcting process to a part of said first subframe data stored in said first subframe memory, while said first row direction error detecting and correcting process is performed to a third subframe data as a first half of a frame data for a second frame to store in said third subframe memory, and for performing said second row direction error detecting and correcting process to a remaining part of said first subframe data and said second subframe data, while said first row direction error detecting and correcting process is performed to a fourth subframe data as a second half of the frame data for the second frame to store in said first subframe memory from a head location.