Patent ID: 7256655
Filing Date: 2007-08-14
Classification: G11B,H03L

Abstract:
1. A phase-locked loop (PLL) apparatus, comprising: a first digital phase frequency detector (PFD) for generating a first phase frequency detection signal according to a first signal; a second digital PFD for generating a second phase frequency detection signal according to a second signal; a switching unit coupled to the first and second digital PFDs for selectively outputting the first phase frequency detection signal or the second phase frequency detection signal according to a selection signal; a digital loop filter (LF) coupled to the switching unit for filtering the signal outputted by the switching unit; a DAC, for performing a digital to analog conversion to a filtered result from the digital loop filter to generate an analog signal; and an oscillator coupled to the digital LF for generating an oscillation signal according to the analog signal.