Patent ID: 6603178
Filing Date: 2003-08-05
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit device, comprising:a first n-channel MISFET and a second n-channel MISFET, each having a gate electrode; a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode; a first insulating film formed on said gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs; a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET: a dielectric film formed on said first conductive film and having a thickness less than that of said first conductive film; and a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET, wherein a capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film, and wherein said second conductive film is formed over said first conductive film to substantially completely cover said first conductive film.