Patent ID: 6341095
Filing Date: 2002-01-22
Classification: G11C

Abstract:
An memory device comprises:a pair of complementary differential bitlines, wherein each of said complementary differential bitlines is connected to a precharge transistor; a plurality of storage cells connected between said pair of complementary differential bitlines; a first discharge transistor connected to a first one of said complementary differential bitlines for increasing pulldown rate of said first one of said complementary differential bitlines during a read operation by sending a voltage to a body of said first discharge transistor to lower a threshold voltage of said first discharge transistor; and a second discharge transistor connected to a second one of said complementary differential bitlines for increasing pulldown rate of said second one of said complementary differential bitlines during said read operation by sending a voltage to a body of said second discharge transistor to lower a threshold voltage of said second discharge transistor.