Patent ID: 6586805
Filing Date: 2003-07-01
Classification: G11C,H01L,Y10S

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell formed on a semiconductor substrate, the memory cell including a first gate insulating film, a first conductor serving as a floating gate layer, a second conductor serving as a control gate layer, a first insulating film covering an upper surface of the second conductor, an interlayer-insulating film electrically insulating the first conductor from the second conductor, a side surface insulating film, source/drain diffusion layers, silicide layers formed on surfaces of the source/drain diffusion layers; the first conductor, the second conductor, the first insulating film, and the interlayer-insulating film having a self-aligned structure; and a transistor formed on the semiconductor substrate, the transistor including a second gate insulating film, a gate electrode, source/drain diffusion layers, a silicide layer formed on an upper surface of the gate electrode and silicide layers formed on surfaces of the source/drain diffusion layers, the gate electrode comprising a third conductor, wherein the side surface insulating film covers a side wall of the first conductor, a side wall of the second conductor, and a side wall of the first insulating film.