Patent ID: 7065666
Filing Date: 2006-06-20
Classification: G06F,G11C

Abstract:
1. A clock signal generator having an input at which an input clock signal is applied and having an output at which an output clock signal is provided, the clock signal generator comprising: a synchronizing circuit having an input terminal at which the input clock signal is applied and having an output terminal at which a first clock signal is provided, the synchronizing circuit generating the first clock signal based on the input clock signal; and a plurality of delay circuits, each having an input coupled to the output terminal of the synchronizing circuit, and having an activation terminal at which a selection signal is applied and further having an output terminal at which a respective delayed output clock signal is provided, each of the plurality of delay circuits having a respective time delay and operable to generate the respective delayed output clock signal having the respective time delay relative to the first clock signal when activated by the selection signal, one of the plurality of delay circuits activated by the selection signal to provide the respective delayed output clock signal as the output clock signal of the clock signal generator.