Patent ID: 6570811
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A writing operation control circuit for a semiconductor memory, comprising:a write control terminal, to which a write controlling signal indicating enable or disable of writing is supplied; a writing data terminal, to which a writing data signal is supplied; a driving circuit which operates to perform a writing operation in response to the writing data signal, the driving circuit having a specific threshold voltage; a first voltage control circuit which selectively outputs first and second supply voltages to the driving circuit in response to a logical level of the write controlling signal; and a second voltage control circuit which selectively outputs third and fourth supply voltages to the driving circuit in response to a logical level of the write controlling signal, wherein the second supply voltage is higher than the first supply voltage, the first supply voltage is higher than the fourth supply voltage, the fourth supply voltage is higher than the third supply voltage.