Patent ID: 6432754
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of forming a ground-plane SOI device comprising the steps of:(a) forming a back oxide layer in a Si-containing layer of a silicon-on-insulator (SOI) wafer so as to separate said Si-containing layer into a top Si-containing layer and a bottom Si-containing layer, said SOI wafer having a buried oxide layer formed on a Si substrate and said Si-containing layer formed on said buried oxide layer; (b) forming a ground-plane doping region into a top portion of said bottom Si-containing layer; (c) forming a gate region on a portion of said top Si-containing layer, said gate region including a gate dielectric formed on said top Si-containing layer, a gate conductor formed on said gate dielectric and a hard mask formed on said gate conductor; (d) forming halo and source/drain extension regions in said top Si-containing layer; (e) forming spacers on a portion of said gate dielectric so as to protect vertical sidewalls of said gate conductor and said hard mask; (f) removing all exposed portions of said top Si-containing layer so as to expose a portion of said back oxide layer underlying said top Si-containing layer; (g) removing said exposed portions of said back oxide layer; (h) forming source and drain regions in said bottom Si-containing layer; (i) growing Si on all exposed Si surfaces; and (j) forming salicide regions on all exposed silicon surfaces.