Patent ID: 8421222
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A chip package comprising: a carrier comprising a glass substrate; a first chip over said carrier and an opening in said glass substrate, wherein said opening passes completely through said glass substrate; a first metal bump between said first chip and said carrier, wherein said first metal bump comprises a first copper pillar between said first chip and said carrier and a solder between said first copper pillar and said carrier, wherein said first copper pillar has a height greater than a vertical distance between a bottom end of said first copper pillar and said carrier; a second chip located in said opening in said glass substrate, and a second metal bump located between said first chip and said second chip, wherein said second chip is connected to said first chip only through said second metal bump, wherein a first end of said second metal bump physically connects to said first chip and a second end of said second metal bump physically connects to said second chip; an encapsulating material between said first chip and said glass substrate, wherein said encapsulating material covers said second chip and a top surface of said glass substrate, wherein said encapsulating material exposes a bottom surface of said glass substrate; and multiple solder balls under said carrier.