Patent ID: 8411482
Filing Date: 2013-04-02
Classification: G11C

Abstract:
1. An apparatus comprising: a plurality of interconnected cells arranged as a column, wherein respective ones of the plurality of cells includes a fuse and a first transistor of a first type, the first transistor including a first terminal, a second terminal, and a third terminal, and the fuse including a fourth terminal and a fifth terminal; and a column selection logic coupled to the plurality of cells configured to facilitate selective programming of one or more fuses correspondingly associated with one or more of the plurality of cells, wherein the first terminal is coupled to a voltage supply terminal, the second terminal is coupled to the fourth terminal, and the fifth terminal is coupled to the column selection logic, wherein the column selection logic includes a second transistor of a second type, and wherein one or more first transistors associated with the one or more of the plurality of cells are respectively conductively coupled to the second transistor during programming of the one or more fuses to form one or more conductive paths with reduced parasitic resistances.