Patent ID: 6378072
Filing Date: 2002-04-23
Classification: G06F,H04L

Abstract:
A cryptographic system comprising:a bus interface for transferring data between the cryptographic system and an external source; a processor, the processor receiving data from the bus interface, and constructing from the data a plurality of exponentiation tasks; a plurality of exponentiation units, the processor transferring each of the plurality of exponentiation tasks to a corresponding one of the plurality of exponentiation units so that the plurality of exponentiation tasks can be performed substantially in parallel by the plurality of exponentiation units in order to speed up system operations, and the plurality of exponentiation units returning results of the plurality of exponentiation tasks to the processor; and initialization means operatively coupled to the processor and configured to place the cryptographic system in a secure state after system reset and allow execution of a secure program, but prior to each execution the secure program is verified and authenticated via the processor.