Patent ID: 8667454
Filing Date: 2014-03-04
Classification: G06F

Abstract:
1. A computer-implemented method for synthesis of device I/O associated with a printed circuit board (PCB) design comprising: generating, using one or more processors, a first programmable device model and a second device model; determining, using the one or more processors, one or more pin assignments associated with the first programmable device model and the second device model based upon, at least in part, one or more of a breakout location, and a fanout location, the one or more pin assignments configured to minimize one or more crossovers, wherein determining is based upon, at least in part, an assigned PCB layer and a three-dimensional optimization analysis; automatically assigning one or more bundles of nets to a preferred PCB layer based upon, at least in part, an overall PCB layer congestion level and the three-dimensional optimization analysis, while minimizing the one or more crossovers; and performing a rotation and a shift of a virtual component on the PCB board based upon, at least in part, an expected breakout direction.