Patent ID: 7910956
Filing Date: 2011-03-22
Classification: H01L,Y02P

Abstract:
1. A semiconductor integrated circuit device, comprising: a core comprising a plurality of core device features arranged such that at least 90% of said core device features are substantially parallel, wherein the core device features are gates; and a plurality of uniform I/O cells having substantially matching device feature layouts, each uniform I/O cell comprising a plurality of I/O cell device features arranged such that at least 90% of said I/O cell device features are substantially parallel and at least 90% of said I/O cell device features are substantially parallel to the same edge of the core, wherein the I/O cell device features are gates, wherein each of the uniform I/O cells comprises a first cell edge arranged substantially perpendicular to a second cell edge, wherein a first cell edge of a first uniform I/O cell corresponds to a first cell edge of a second uniform I/O cell, wherein said first cell edge of said first uniform I/O cell and said second uniform I/O cell are oriented along a horizontal edge of the core device, wherein a second cell edge of a third uniform I/O cell corresponds to a second cell edge of a fourth uniform I/O cell, wherein said second edge of said third uniform I/O cell and said fourth uniform I/O cell are oriented along a vertical edge of the core device.