Patent ID: 7888151
Filing Date: 2011-02-15
Classification: G02F,H01L

Abstract:
1. A method of fabricating an array substrate for an LCD device, comprising: forming first, second and third semiconductor layers on a substrate having a non-display region and a display region, the first and second semiconductor layers in the non-display region, the third semiconductor layer in the display region; forming a gate insulating layer on the first, second and third semiconductor layers; forming first, second and third gate electrodes and a gate line on the gate insulating layer, the first gate electrode directly over the first semiconductor layer, the second gate electrode directly over the second semiconductor layer, the third gate electrode directly over the third semiconductor layer, the gate line in the display region; forming a first protrusion extending from the first gate electrode along an edge of the first semiconductor layer, a second protrusion extending from the second gate electrode along an edge of the second semiconductor layer, a third protrusion extending from the third gate electrode along an edge of the third semiconductor layer; forming an interlayer insulating layer on the first, second and third gate electrode, the first, second and third protrusions and the gate line, the interlayer insulating layer having first and second contact holes exposing the first semiconductor layer, third and fourth contact holes exposing the second semiconductor layer, and fifth and sixth contact holes exposing the third semiconductor layer, respectively; forming first, second and third source electrodes, first, second and third drain electrodes and a data line on the interlayer insulating layer, wherein the first source electrode and the first drain electrode are connected to the first semiconductor layer through the first and second contact holes, and the second source electrode and the second drain electrode are connected to the second semiconductor layer through the third and fourth contact holes, and the third source electrode and the third drain electrode are connected to the third semiconductor layer through the fifth and sixth contact holes, respectively, and the data line crosses the gate line to define a pixel region in the display region; forming a passivation layer on the first, second and third source electrodes, the first, second and third drain electrodes and the data line, the passivation layer having a drain contact hole exposing the third drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the third drain electrode through the drain contact hole, wherein at least one of the first, second and third gate electrodes has first and second sides opposite to each other, and a corresponding protrusion of the first, second and third protrusions to the at least one of the first, second and third gate electrodes is disposed at both of the first and second sides.