Patent ID: 7791403
Filing Date: 2010-09-07
Classification: H03K,Y10T

Abstract:
1. A digital circuit comprising: a semiconductor substrate; at least one n-channel transistor having a gate, a drain and a source disposed at least partially in at least one p-type well in the semiconductor substrate; at least one p-channel transistor having a gate, a drain and a source disposed at least partially in at least one n-type well in the semiconductor substrate; a backgate control circuit electrically coupled to the at least one p-type well and to the at least one n-type well via a first control switch and a second control switch, respectively; a shunt switch electrically connected between the at least one n-type well and the at least one p-type well, the backgate control circuit being coupled to the shunt switch for closing the shunt switch when facilitating transitioning of the at least one n-channel transistor and the at least one p-channel transistor from standby mode to active mode, resulting in shunting of charge from the at least one n-type well to the at least one p-type well, and for opening the shunt switch when a well voltage of the at least one n-type well or the at least one p-type well reaches a threshold voltage indicative of a transition of the at least one p-channel transistor or the at least one n-channel transistor to active mode; and wherein subsequent to reaching active mode, and opening the shunt switch, the backgate control circuit closes at least one of the first control switch or the second control switch to actively maintain during active mode at least one of voltage of the p-type well at a first voltage level or voltage of the n-type well at a second voltage level, wherein the first voltage level and the second voltage level are different active mode voltage levels.