Patent ID: 9030340
Filing Date: 2015-05-12
Classification: H03M

Abstract:
1. A method of performing background corrections for an n-path interleaving analog-to-digital converter (ADC), the method comprising: accepting an analog input signal s generating a clock having a clock frequency fs; creating n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/n, where n is an integer greater than 2; generating a first tone signal s combining the analog input signal and the first tone signal, creating a combination signal; sampling the combination signal using the n sample clocks, creating n digital sample signals per clock period 1/fs; interleaving the n digital sample signals, creating an interleaved signal; applying corrections that minimize errors in the interleaved signal to obtain a corrected digital output; and, for a pair of digital sample signals, determining errors at an alias frequency f3, associated with the second frequency f2, to obtain correction information.