Patent ID: 6228730
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method of fabricating a field effect transistor, comprising steps of:providing a substrate comprising a gate thereon, wherein the gate includes a dielectric layer on the substrate and an electrode on the dielectric layer;forming a liner oxide layer adjacent to and covering a sidewall of the gate;forming a first spacer adjacent to the liner oxide layer;forming an epitaxial silicon layer aside of the first spacer on the substrate;forming a shallow source/drain (S/D) extension junction in the substrate below the epitaxial silicon layer, wherein the epitaxial silicon layer is formed before the shallow S/D extension junction is formed;forming a second spacer covering the first spacer;forming a S/D region aside of the second spacer in the substrate below the epitaxial silicon layer; andtransforming a part of the epitaxial silicon layer into a metal silicide layer.