Patent ID: 6207516
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A method of fabricating a gate oxide layer with different thickness, wherein a gate oxide layer and a gate are provided on a substrate, comprising:removing a portion of the gate oxide layer;forming a first thermal oxide layer to cover the surface of the substrate and the gate;forming a masking layer to cover the first thermal oxide layer;defining the masking layer and removing a portion of the first thermal oxide layer to expose a portion of the surface of the gate and the substrate;forming a drain region at one side of the gate on the substrate by performing a first implantation;forming a second thermal oxide layer to cover the exposed substrate and the gate;removing the masking layer and etching back the second thermal oxide layer and the first thermal oxide layer, the surface of the gate is exposed, the first thermal oxide layer becomes a first spacer structure adjacent to a subsequently formed source region and the second thermal oxide layer becomes a spacer structure adjacent to the drain region; andforming a source region at the other side of the gate by performing a second implantation, wherein a doped concentration of the drain region adjacent to the gate and beneath the second spacer is lighter.