Patent ID: 7535239
Filing Date: 2009-05-19
Classification: G01R

Abstract:
1. An apparatus, comprising: a probe card circuit board; and a substrate having a first interface coupled to the probe card circuit board and a second interface having a plurality of die patterns respectively corresponding to die patterns of a plurality of integrated circuits (ICs) under test, the plurality of die patterns being arranged with respect to the substrate in a plurality of probe pin configurations, the plurality of die patterns including separations of a first scribe width and a second scribe width, the first scribe width being different from the second scribe width, wherein a first pair of die patterns of the second interface having the separation of the first scribe width corresponds to a pair of probe pin configurations of a first probe head for testing a pair of ICs on a first wafer from a first foundry, and a second pair of die patterns of the second interface having the separation of the second scribe width corresponds to a pair of probe pin configurations of a second probe head for testing a pair of ICs on a second wafer from a second foundry.