Patent ID: 6163184
Filing Date: 2000-12-19
Classification: H03L

Abstract:
A phase locked loop (PLL) comprising:a frequency multiplier circuit having first and second inputs and an output, said frequency multiplier circuit being responsive to the application to the first input of an input signal having a frequency, fref, for producing at said output an output signal, fo, having a frequency which is a function of the product of N and said frequency fref;a programmable frequency divider network programmable to divide by any number ""N"", where N is a number greater than 1, said divider network being connected between the output and the second input of the frequency multiplier so as to feed back to the second input a signal equal to fo/N;wherein the frequency multiplier circuit includes programmable circuitry, programmed to be a function of N, for selectively modifying the transfer function of the frequency multiplier as a function of the divider ratio N.