Patent ID: 7616267
Filing Date: 2009-11-10
Classification: G02F

Abstract:
1. A pixel structure of a flat panel display for arrangement on a substrate, comprising: a storage capacitor disposed on the substrate, comprising a lower metal layer, an upper metal layer, and a capacitor dielectric layer disposed therebetween; a thin film transistor, disposed on the substrate and electrically connected to the storage capacitor, comprising an active layer, a gate electrode, and a gate dielectric layer disposed therebetween; and a data line disposed on the substrate and electrically connected to the thin film transistor; a first interconnect structure electrically connecting the active layer and the lower metal layer; and a second interconnect structure electrically connecting the active layer and the data line; wherein the upper metal layer and the gate electrode are formed by the same metal layer and the lower metal layer and the data line are formed by the same metal layer.