Patent ID: 8108621
Filing Date: 2012-01-31
Classification: G06F

Abstract:
1. A cache memory system, comprising: a first array of storage elements, each configured to store a cache line; a second array of storage elements corresponding to the first array of storage elements, each configured to store a first partial status of the cache line in the corresponding storage element of the first array; and a third array of storage elements corresponding to the first array of storage elements, each configured to store a second partial status of the cache line in the corresponding storage element of the first array, wherein the second partial status indicates whether or not the cache line has been modified; wherein when the cache memory system modifies the cache line within a storage element of the first array, the cache memory system writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array; wherein the cache memory system reads both the first partial status and the second partial status of the cache line from corresponding storage elements of the second array and the third array, respectively, to determine the full status of the cache line.