Patent ID: 7817659
Filing Date: 2010-10-19
Classification: H04L

Abstract:
1. A circuit for aggregating a plurality of input data streams from first processors into one data stream for a second processor, said circuit comprising: a plurality of ingress data ports, each said ingress data port coupled to a corresponding first processor and adapted to receive an input data stream from the corresponding first processor, each input data stream comprising ingress data packets, each ingress data packet comprising at least one priority factor coded therein; an aggregation module coupled to said plurality of ingress data ports and configured to receive the plurality of input data streams from the first processors using the plurality of ingress data ports, wherein an input data stream from a first processor is received via the ingress data port coupled to the first processor, said aggregation module adapted to analyze and combine the plurality of input data streams into one aggregated data stream in response to the at least one priority factor and to generate a packet descriptor comprising a reference to a memory location of its analyzed data packet; a memory coupled to said aggregation module, said memory adapted to store analyzed data packets; said memory comprising a plurality of priority queues each provided for a corresponding priority class, adapted to store the packet descriptor of each of the analyzed data packets classified to the corresponding priority class, the packet descriptor containing a reference to the memory location of its analyzed data packet in said memory; and an output data port coupled to said aggregation module, said output data port adapted to output the aggregated data stream to the second processor.