Patent ID: 6366228
Filing Date: 2002-04-02
Classification: H03M

Abstract:
A selecting circuit comprising:a logic circuit adapted to receive an n-bit (2p+1)-valued (2n&gE;2p&gE;2, n and p being an integer) input signal m (m being an integer satisfying the requirement of 2p&gE;m&gE;0), generate a pair of internal signals having a value produced by halving the value obtained on the basis of the upper (nâˆ’1) bits of the input signal m, neglecting the least significant bit of said input signal m, and then, in the case of an input signal m having an odd number value, generate first and second signals by alternately adding 1 to said two internal signals for each input of signal m having an odd number value; a first signal processing circuit having p first output terminals and adapted to select a number of output terminals corresponding to the value of said first signal out of said p first output terminals on the basis of said first signal so as to make said p output terminals to be selected with a same and identical probability of selection; and a second signal processing circuit having p second output terminals and adapted to select a number of output terminals corresponding to the value of said second signal out of said p second output terminals on the basis of said second signal so as to make said p output terminals to be selected with a same and identical probability of selection.