Patent ID: 6230241
Filing Date: 2001-05-08
Classification: G06F

Abstract:
An apparatus comprising:a source memory unit;a destination memory unit;a cache memory unit;a system bus interconnecting the source memory unit, the destination memory unit and the cache memory unit; anda central processing unit coupled to the system bus, having a programmed input/output loop coupled to the cache memory unit, the central processing unit, prior to transferring data, instructing the cache memory unit to map a source location and a destination location in the cache memory unit to respective portions of the source and destination memory units in order to configure a cacheable view of the source and destination memory units, the source and destination locations mapped to respective portions of the source and destination memory units being large enough to accommodate a single bursting memory transfer, the programmed input/output loop performing (i) a transfer of input/output data from the source memory unit to the source location in the cache memory unit, (ii) a transfer of the input/output data from the source location in the cache memory unit to the destination location in the cache memory unit, and (iii) a transfer of the input/output data from the destination location in the cache memory unit to the destination memory unit.