Patent ID: 9204560
Filing Date: 2015-12-01
Classification: H01L,H05K,Y10T

Abstract:
1. A manufacturing method of a package carrier, comprising: providing an insulation substrate, the insulation substrate having an upper surface, a lower surface opposite to the upper surface, a plurality of cavities and a plurality of through holes, wherein the cavities are located at the lower surface, and the through holes pass through the insulation substrate and respectively communicate with the cavities to define a plurality of vias, and a diameter of each of the through holes is substantially less than a diameter of each of the cavities; performing an electroless plating process to form a conductive material on the upper surface, the lower surface and in the vias of the insulation substrate, wherein the conductive material covers the upper surface and the lower surface of the insulation substrate and fills up the vias; removing a portion of the conductive material on the upper surface and the lower surface of the insulation substrate to expose the upper surface and the lower surface of the insulation substrate, wherein the conductive material fills up the vias to define a plurality of conductive posts; forming an insulation layer on the upper surface of the insulation substrate, wherein the insulation layer has a top surface relatively far from the upper surface of the insulation substrate and a plurality of blind vias extending from the top surface to the conductive posts; forming a patterned circuit layer on the top surface of the insulation layer, wherein the patterned circuit layer fills up the blind vias and is connected to the conductive posts, and the patterned circuit layer exposes a portion of the top surface of the insulation layer; and forming a solder mask layer on the patterned circuit layer, the solder mask layer covering the patterned circuit layer and the exposed portion of the top surface of the insulation layer, the solder mask layer having a plurality of openings, wherein the openings expose a portion of the patterned circuit layer to define a plurality of pads.