Patent ID: 6121145
Filing Date: 2000-09-19
Classification: G03F,H01L

Abstract:
A method of fabricating a via and an interconnection, on a substrate comprising a semiconductor device and a first metal layer, comprising:forming a first inter-metal dielectric layer on the first metal layer;forming a photo-resist layer on the first inter-metal dielectric layer;performing a single step of photolithography to simultaneously define the photo-resist layer into a via hole region, an interconnection window region, and an isolation region, wherein the via hole region is a thoroughly developed region, the interconnection window region is a partly developed region, and the isolation region is a completely undeveloped region;removing portions of the photo-resist layer in the via hole region and the interconnection window region to form the photo-resist layer with a profile corresponding to a profile of a via hole and an interconnection window to be formed in the first inter-metal dielectric layer;using the photo-resist layer as a mask to simultaneously etch the first inter-metal dielectric layer and the photo-resist layer to transfer the profile of the photo-resist layer to the first inter-metal dielectric layer by forming a via hole, and an interconnection window in the first inter-metal dielectric layer,removing the photo-resist layer and filling the via hole and the interconnection window with a second metal layer;etching the second metal layer until the inter-metal dielectric layer under the isolation region is exposed; andforming a second inter-metal dielectric layer,wherein the photo-resist layer is defined by a mask having a clear area, a grey area and a dark area; andwherein the mask is composed of a quartz glass substrate defining the clear area, an amorphous silicon layer disposed on the quartz glass substrate and defining the gray area, and a chromium layer disposed on the amorphous silicon layer and defining the dark area.