Patent ID: 7504270
Filing Date: 2009-03-17
Classification: G03F,H01L

Abstract:
1. A method, comprising: forming a plurality of test structures on a semiconducting substrate, each of said test structures having a first member and a second member at least partially overlapping the first member, wherein at least one physical dimension of each test structure associated with the overlapping varies relative to the other of said plurality of test structures to affect the proximity of one of the first and second members in the particular one of the plurality of test structures to a region of manufacturing-induced corner rounding present at an inside corner defined in the other of the first and second members in the particular one of the test structures; forming at least one reference test structure; performing at least one electrical test on said plurality of test structures and on said at least one reference test structure to thereby produce electrical test results; and analyzing said test results to determine an impact of said manufacturing-induced corner rounding on the performance of said plurality of test structures.