Patent ID: 6681312
Filing Date: 2004-01-20
Classification: G06F,G11C,Y02D

Abstract:
An address translation buffer comprising:a first memory array having a plurality of content-addressable memories, each memory storing a previous process identifier for comparing the previous process identifier with a new process identifier which identifies a currently executed process and producing a first output signal when a coincidence is detected between the previous and new process identifiers and a second output signal when said coincidence is not detected; a plurality of drivers associated respectively with the memories of the first memory array, each of the drivers having an output line and pulling the output line to a first voltage level only when the first output signal from the associated memory coincides with a precharge signal to produce a match signal and pulling the output line to a second voltage level in response to a discharge signal for discharging energy from the output line when the corresponding memory of the first memory array produces said second output signal; a second memory array having a plurality of content-addressable memories corresponding respectively to the drivers, each memory of the second memory array storing a previous virtual address for comparing the previous virtual address with a new virtual address associated with said new process identifier in response to said match signal of the corresponding driver and producing an output signal when a coincidence is detected between the previous and new virtual addresses; and a third memory for storing a plurality of physical addresses associated respectively with the memories of the second memory array and delivering one of the physical addresses in response to the output signal of the associated memory of the second memory array.