Patent ID: 8351239
Filing Date: 2013-01-08
Classification: G11C

Abstract:
1. An electronic circuit for characterizing a resistive memory array, said circuit comprising: a first current mirror sub-circuit, said first current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control; a second current mirror sub-circuit, said second current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control; a reference current terminal to apply an external reference current to said first current mirror sub-circuit to generate a first current through said first current mirror sub-circuit; an interconnection to couple said first current to said second current mirror sub-circuit; a sense current terminal to apply a sense current passed through said second current mirror sub-circuit to a memory cell under test; and a digital circuit element to generate a digital signal indicative of electrical current flowing through said memory cell under test.