Patent ID: 7839207
Filing Date: 2010-11-23
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a power gated circuit that is shut down during a low-power period; a retention circuit, coupled to the power gated circuit during at least a portion of a non- low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; a first portion of a power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period; wherein the first portion of the power grid is characterized by intrinsic capacitance that is larger than an intrinsic capacitance of the second portion of the power grid; and wherein the integrated circuit comprises multiple metal layers; wherein a topmost metal layer of the integrated circuit comprises only conductors of the first portion of the power grid.