Patent ID: 8542032
Filing Date: 2013-09-24
Classification: G06F,H03K

Abstract:
1. An integrated circuit comprising: at least first and second interconnects; circuitry including a plurality of logic regions that produce output signals; a first selection stage circuitry that receives the output signals and selects at least two output signals from the output signals; a second selection stage circuitry that receives the at least two output signals, wherein the second selection stage circuitry provides a first output signal of the at least two output signals to the first interconnect and provides a second output signal of the at least two output signals to the second interconnect in a first configuration mode, and wherein the second selection stage circuitry provides the second output signal to the first interconnect and provides the first output signal to the second interconnect in a second configuration mode; and an input selection circuit that provides a plurality of input signals to the plurality of logic regions of the circuitry.