Patent ID: 6287926
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method of forming a semiconductor for use with a gate electrode damascene process, comprising:providing a semiconductor silicon substrate;forming a thin dielectric layer on top of said substrate;depositing a thick layer of oxide on top of said thin dielectric layer;creating a trench pattern, said trench pattern to penetrate and go through said thick layer of oxide, furthermore to penetrate and go through said thin dielectric layer, furthermore to penetrate the surface of said silicon substrate to form a shallow trench in said substrate, said trench pattern having sidewalls in addition to having a bottom surface, said bottom surface being bordered by corners;forming a thin layer of oxide at the bottom of said trench pattern;performing a channel implant in said silicon substrate, said channel implant being self-aligned with said trench pattern, said channel implant penetrating said substrate to a depth between about 0.02 and 1.5 .mu.m;forming Lightly Doped Drain (LDD) areas in said silicon substrate, said LDD areas being self-aligned with the corners of said bottom surface of said trench pattern by an angle implantation;forming a pocket implant in said silicon substrate, said pocket implant being self-aligned with said trench pattern;forming spacers on the sidewalls of said trench pattern;removing said thin layer of oxide from the bottom of said trench pattern where said thin layer of oxide is not covered by said spacers;forming a gate dielectric at the bottom of said trench pattern where said thin layer of oxide has been removed;forming a gate electrode in said trench pattern;removing said thick layer of oxide from the top of said thin dielectric layer;removing said thin dielectric layer from the top of said substrate; andperforming source and drain implant in the surface of said silicon substrate, said source and drain implant to be substantially self-aligned with said spacers.