Patent ID: 8144481
Filing Date: 2012-03-27
Classification: H05K

Abstract:
1. A memory system comprising: a main board comprising memory bus having a plurality of wiring lines communicating signals from a memory controller mounted on the main board; first and second module sockets mounted on the main board and configured to connect the wiring line to first and second memory modules respectively inserted into the first and second module sockets, wherein the first module socket comprises a first plurality of electrodes and the second module socket comprises a second plurality of electrodes opposing the first plurality of electrodes; first and second stub resistors disposed on the main board and respectively arranged as dual-branching stub resistors, each forming a T-branch connection structure between one of the first electrodes and one of the second electrodes and a branching node connecting one of the plurality of wiring lines; and a third stub resistor disposed between the branching node and either one of the first and second electrodes.