Patent ID: 7118983
Filing Date: 2006-10-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising steps of: (a) forming a gate electrode of an n-channel MISFET over a main surface of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over a main surface of a second semiconductor region of n-type conductivity formed in said semiconductor body; (b) after said step (a), implanting ions in said first semiconductor region to form a third semiconductor region of n-type conductivity; (c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes; (d) after said step (c), implanting ions in said first semiconductor region to form a fourth semiconductor region of n-type conductivity; (e) after said step (c), implanting ions in said first semiconductor region to form a fifth semiconductor region of n-type conductivity; and (f) after said steps (d) and (e), forming a cobalt silicide layer in said fourth semiconductor region, wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region, wherein a depth of said fifth semiconductor region is greater than a depth of said fourth semiconductor region, wherein said gate electrode of said n-channel MISFET is an N-type gate electrode, and wherein said gate electrode of said p-channel MISFET is P-type gate electrode.