Patent ID: 8085893
Filing Date: 2011-12-27
Classification: H03D,H03L,H04L

Abstract:
1. A clock recovery circuit comprising: (a) a clock supply circuit for generating a first clock signal; (b) a control signal circuit including a first phase detector connected to the clock supply circuit for providing a first phase difference signal representing a difference in phase between the first clock signal and a data signal applied to the first phase detector, the first control signal circuit providing a first control signal which is a function of the first phase difference signal; (c) a phase shifter, the phase shifter being operative to apply a phase shift to an input clock signal and thereby provide a second clock signal and to vary the phase shift responsive to the first control signal; (d) a second phase detector connected to the clock supply circuit and to the first phase shifter for providing a second phase difference signal representing a difference in phase between the second clock signal and the first clock signal and (e) a filter connected to the second phase detector for filtering the second phase difference signal to thereby provide a second control signal, the clock supply circuit being responsive to the second control signal to advance or retard the first clock signal.