Patent ID: 8643100
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A field effect transistor (FET), comprising: a first source/drain (S/D) terminal; a second S/D terminal spaced apart from the first S/D terminal; a channel region disposed between the first S/D terminal and the second S/D terminal; a gate dielectric structure disposed superjacent the channel region; and a gate electrode disposed superjacent the gate dielectric structure; wherein the gate dielectric structure has a first region adjacent to the first S/D terminal having a first thickness and a second region adjacent to the second S/D terminal having a second thickness; wherein the channel region has a first portion adjacent to the first S/D terminal having a first doping profile, and the channel region further has a second portion adjacent to the second S/D terminal having a second doping profile different from the first doping profile; wherein the first thickness is less than the second thickness; wherein the first portion of the channel region has a net concentration of dopants of a first conductivity type that is lower than a net concentration of dopants of the first conductivity type in the second portion of the channel region.