Patent ID: 8330216
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a plurality of memory strings in which a plurality of memory cells that are electrically rewritable and a plurality of selection transistors are connected in series, the plurality of memory strings comprising: a plurality of first conductive layers laminated in a laminating direction perpendicular to a semiconductor substrate with a plurality of first interlayer insulating layers each sandwiched therebetween, each of the first conductive layers serving as a gate electrode of each of the memory cells; a plurality of first holes each formed to penetrate the plurality of first conductive layers and the plurality of first interlayer insulating layers to extend in the laminating direction; a plurality of charge storage layers each formed on an inner wall of a respective of the first holes, the charge storage layers each serving as a charge accumulation layer of the memory cells; a plurality of first columnar semiconductor layers each formed in a respective of the first holes, the first columnar semiconductor layers each serving as a channel region of the memory cells; a plurality of second conductive layers formed over the plurality of first conductive layers, the second conductive layers each serving as a gate electrode of a selection gate transistor of each of the memory strings, the second conductive layers each being provided in a line form extending along a first direction perpendicular to the laminating direction such that each of the second conductive layers surrounds a plurality of second columnar semiconductor layers formed along the first direction; a plurality of second holes each formed to penetrate the second conductive layers to extend in the laminating direction and reach the upper side of the first columnar semiconductor layers; a plurality of insulation layers each formed on an inner wall of a respective of the second holes and serving as a gate insulating film of the selection gate transistor; the plurality of second columnar semiconductor layers each formed in a respective of the second holes to contact the second conductive layers via the insulation layer, the second columnar semiconductor layers being in contact with an upper side of the first columnar semiconductor layers, the second columnar semiconductor layers each serving as a channel region of the selection gate transistor; a plurality of first sidewall conductive layers each formed against a sidewall of each of the second conductive layers and formed to extend in the first direction, the sidewall being an outer wall apart from the inner wall of the second holes and formed in a straight line along the first direction; and a second interlayer insulating layer formed below the second conductive layers, wherein the first sidewall conductive layers are each formed also in contact with a sidewall of the second interlayer insulating layer.