Patent ID: 6285609
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A test apparatus for testing a first memory device, the first memory device having a plurality of memory cells each of which is structured to store a data bit, one data bit per memory cell, the test apparatus comprising:a processor having a processor bus;an input device coupled to the processor through the processor bus and structured to allow data to be entered into the test apparatus;an output device coupled to the processor through the processor bus and structured to allow data to be output from the test apparatus;a second memory device coupled to the processor through the processor bus, the second memory device structured to store a plurality of data bits; anda test circuit coupled to the processor, the test circuit comprising:a memory loader circuit coupled to the first memory device, the memory loader circuit structured to cause a plurality of data bits having a first logic level to be stored in the memory cells;a memory reader circuit coupled to the first memory device, the memory reader circuit structured to serially read a plurality of data bits from the memory cells after the memory loader circuit causes the plurality of data bits to be stored in the memory cells, and structured to output a plurality of the data bits read; anda comparator circuit coupled to the memory reader circuit to receive the plurality of data bits output, the comparator circuit structured to sequentially compare, for a predetermined duration of time, the plurality of data bits output with the first logic level.