Patent ID: 9208271
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. A method of automated debugging of a design verification environment, the method comprising: identifying a plurality of attributes of the design verification environment; performing a plurality of simulation runs of the design verification environment; recording a plurality of samples for each of the plurality of attributes from the plurality of simulation runs, wherein each sample includes a plurality of values of the plurality of attributes; determining a subset of the simulation runs that fail; determining a subset of simulation runs that pass; identifying a subset of the plurality of attributes such that a distribution of values of the subset of attributes for the passing runs is different from a distribution of values of the subset of attributes for the failing runs; generating a log of the plurality of simulation runs; generating a tabular description based upon the log, wherein identifying the subset is based upon, at least in part, the tabular description; utilizing a plurality of flattened tables as an input to a transaction correlation algorithm to determine one or more bugs in the design verification environment; determining a measure for each passing run, wherein each measure for each passing run is based on a measure of the values sampled in the respective passing run; determining a measure for each failing run, wherein each measure for each failing run is based on a measure of the values sampled in the respective failing run; wherein the measure of the respective value sampled in the passing run is proportional to (A+C/D)/(B+1)−(C−C/D)/(D−1) and the measure of the respective value sampled in the failing runs is proportional to (A+1)/(B+1)−(C−1)/(D−1), wherein: A=the number of failing runs with the respective value; B=the number of failing runs; C=the number of passing runs with the respective value; and D=the number of passing runs.