Patent ID: 6410425
Filing Date: 2002-06-25
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit, said method comprising the steps of:depositing first and second stop layers on a first dielectric layer that covers metallization lines of a first metallization level; selectively etching the second stop layer with respect to the first stop layer; selectively etching the first stop layer with respect to the first dielectric layer; depositing a second dielectric layer so as to cover the first and second stop layers and the first dielectric layer; selectively etching the first and second dielectric layers with respect to the first and second stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer; and depositing metal in the holes and trenches so as to form vias in the holes and metallization lines of a second metallization level in the trenches, each of the vias connecting at least one of the metallization lines of the first metallization level and at least one of the metallization lines of the second metallization level.