Patent ID: 6380087
Filing Date: 2002-04-30
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the steps of:providing a semiconductor wafer structure having at least an upper and a lower dielectric layer; said semiconductor wafer structure having a bonding pad area and a interconnect area; forming, at least one active interconnect having a first width, in said interconnect area, through said dielectric layers, and a plurality of adjacent dummy plugs each having a second width, in said bonding pad area, through a portion of said dielectric layers; patterning and etching said semiconductor wafer structure to form trenches through said upper dielectric layer; said trenches surrounding each of said at least one active interconnect and said dummy plugs whereby said upper dielectric level between said adjacent dummy plugs is removed; depositing a metallization layer over said lower dielectric layer, filling said trenches at least to the upper surface of the remaining upper dielectric layer; and planarizing said metallization layer to remove the excess of said metallization layer forming a continuous bonding pad within said bonding pad area and including said plurality of adjacent dummy plugs; and forming at least one damascene structure including said at least one respective active interconnect.