Patent ID: 6559059
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A method of fabricating a metal oxide semiconductor (MOS) transistor of an embedded memory, the method comprising:providing a semiconductor wafer having a memory array area and a periphery circuit region defined on the surface of the semiconductor wafer; forming a first dielectric layer, a polysilicon layer, and a second dielectric layer in order on the surface of the semiconductor wafer; performing a first ion implantation process on the polysilicon layer above the memory array area so as to form a doped polysilicon layer above the memory array area; removing the second dielectric layer above the memory array area; forming a metallic silicide layer, a passivation layer, and a first photoresist layer in order on the surface of the semiconductor wafer; performing a first photolithographic process so as to define a plurality of gate patterns in the first photoresist layer; using the gate patterns in the first photoresist layer as a hard mask to etch the portions of the passivation layer, the metallic silicide layer, and the doped polysilicon layer that are above the memory array area down to the surface of the first dielectric layer, and an in-situ etching of the portions of the passivation layer and the metallic silicide layer that are above the periphery circuit region down to the surface of the second dielectric layer; performing a second ion implantation process to form a lightly doped drain (LDD) for each MOS transistor in the memory array area; removing the first photoresist layer and the second dielectric layer above the periphery circuit region; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second photolithographic process to define a plurality of gate patterns in the second photoresist layer above the periphery circuit region; using the gate patterns of the second photoresist layer as a hard mask to etch the polysilicon layer above the periphery circuit region down to the surface of the first dielectric layer so as to form gates for each MOS transistor in the periphery circuit region; performing a third ion implantation to form a lightly doped drain (LDD) for each of the MOS transistors in the periphery circuit region; removing the second photoresist layer; forming a silicon nitride layer to cover the surface of each gate; performing an etching process to remove portions of the silicon nitride layer in the periphery circuit region so as to form a spacer adjacent to each gate in the periphery circuit region; and performing a forth ion implantation process to form a source and a drain for each MOS transistor.