Patent ID: 7173473
Filing Date: 2007-02-06
Classification: H03K

Abstract:
1. A level shifting circuit comprising: a first reference voltage node carrying a voltage at a first voltage level; a second reference voltage node carrying a voltage at a second voltage level, the second voltage level being different than the first voltage level; a third reference voltage node carrying a voltage at a third voltage level, the third voltage level being different than the first voltage level and the second voltage level; an input node to receive an input signal, the input signal discretely switching between the first voltage level and the second voltage level; a first n-channel transistor having a first source/drain region, a second source/drain region and a gate, the gate being coupled to the input node; a second n-channel transistor having a first source/drain region coupled to the second source/drain region of the first n-channel transistor, a second source/drain region coupled to the second reference voltage node and a gate coupled to a first enable signal node; a first p-channel transistor having a first source/drain region coupled to the first source/drain region of the first n-channel transistor, a second source/drain region and a gate coupled to the input node; a second p-channel transistor having a first source/drain region coupled to the second source/drain region of the first p-channel transistor, a second source/drain region coupled to the third reference voltage node and a gate coupled to a second enable signal node; and an output node coupled to the first source/drain region of the first n-channel transistor and the first source/drain region of the first p-channel transistor, the output node carrying an output signal, the output signal discretely switching between the third voltage level and the second voltage level.