Patent ID: 6103565
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A semiconductor processing method of forming a capacitor construction, comprising:providing an electrically conductive line over a semiconductive substrate, the line having an electrically insulated outermost surface;providing a sidewall spacer having an inner surface laterally adjacent the conductive line and the spacer having an uppermost surface, and the inner surface extending upwardly from laterally adjacent the conductive line to the uppermost surface of the spacer;forming a recess over the conductive line and extending to beneath the uppermost surface of the sidewall spacer, and the recess exposing an exposed portion of the inner surface of the sidewall spacer between the electrically insulated outermost surface of the conductive line and the uppermost surface of the sidewall spacer;providing a node to which electrical connection to a capacitor is to be made proximate the conductive line, the node comprising a diffusion region in the semiconductive substrate;forming an electrically conductive first capacitor plate layer over the node, the sidewall spacer, and within the recess, the first capacitor plate layer contacting a surface of the semiconductive substrate at the node to contact the diffusion region of the node, and the first capacitor plate layer contacting the exposed portion of the inner surface of the sidewall spacer; andproviding a capacitor dielectric layer and a second capacitor plate layer over the first capacitor plate layer.