Patent ID: 6060778
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A packaged integrated circuit device, comprising:an interconnection substrate having at least one conductive trace layer and at least one insulating layer and also having a first surface and a second surface having a plurality of electrical contacts thereon, opposite to the first surface of the interconnection substrate;a dielectric layer attached to an outer portion of the first surface of the interconnection substrate;a metal thermal conductive layer having a first surface and a second surface opposite to the first surface thereof, the first surface of the metal thermal conductive layer being attached to an internal portion of the first surface of the interconnection substrate and also being in contact with the internal end portion of the dielectric layer;a hole region which is formed at the central portion of the interconnection substrate and which exposes the first surface of the metal thermal conductive layer;an integrated circuit chip disposed within the hole region, the integrated circuit chip having a first surface attached the first surface of the interconnection substrate and a second surface opposite to the first surface of the integrated circuit chip, the second surface of the integrated circuit chip having a plurality of bonding pads formed thereon;a plurality of bond wires for electrically connecting the bond pads with the conductive trace layer; andan encapsulant material enclosing bond wires and the integrated circuit chip, the hole region being filled with the encapsulant material.