Patent ID: 8013810
Filing Date: 2011-09-06
Classification: G09G,G11C

Abstract:
1. A scan driver, comprising: a shift register; a first signal processor adapted to receive an initializing signal, a base clock signal, a base negative clock signal and a feedback signal, and to generate a first output signal, wherein the first signal processor includes a first transmission gate adapted to receive the base clock signal and the base negative clock signal and to transfer the feedback signal to a first inverter, a second transmission gate adapted to receive the base clock signal and the base negative clock signal and to transfer the output signal of a second inverter to the first inverter, the first inverter adapted to receive the output signal of the first and the second transmission gates and to generate the first output signal, the second inverter adapted to invert the first output signal and to transfer an inverted first output signal to the second transmission gate; a second signal processor adapted to receive the initializing signal, the first output signal, the base clock signal and the base negative clock signal, and to generate a second output signal and a second negative output signal; a first logic gate adapted to receive the base clock signal and the second output signal, and to generate a first clock signal; and a second logic gate adapted to receive the base clock signal and the second negative output signal, and to generate a second clock signal.