Patent ID: 6515495
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A test structure, comprising:a wafer having a plurality of sets of at least two transistors, each one of said at least two transistors of said plurality of said sets defining a test component; a plurality of contact areas disposed on said wafer, said at least two transistors of each one of said plurality of said sets disposed between and connected to a respective pair of adjacent ones of said plurality of said contact areas for receiving a voltage that can be applied to said respective pair of adjacent ones of said plurality of said contact areas; a plurality of additional contact areas disposed on said wafer; one of said at least two transistors of each one of said plurality of said sets including a gate connection connected to a respective one of said plurality of said additional contact areas for receiving a switching current; and another one of said at least two transistors of each one of said plurality of said sets including a gate connection connected to another respective one of said plurality of said additional contact areas for receiving another switching current such that said at least two transistors of each one of said sets can be switched on alternately from each other.