Patent ID: 6621741
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A method for performing program verification of memory cells in a NAND memory device to achieve selected Vt levels, the NAND memory device includes page buffers having disable gates that operate to enable or disable the method comprising steps of:(a) performing a programming cycle to program the memory cells to have the selected Vt levels; (b) setting a first verification level; (c) verifying that the memory cells have the selected Vt levels using the first verification level, wherein passed and failed memory cells are determined; (d) inhibiting, using the disable gates, the passed memory cells from further programming; (e) setting a second verification level; (f) verifying that the failed memory cells have a second selected Vt level using the second verification level, wherein second passed and second failed memory cells are determined; (g) adjusting a programming pulse to have a first strength level when the second passed memory cells are determined; (h) adjusting the programming pulse to have a second strength level when the second failed memory cells are determined; (i) re-programming the failed memory cells with the programming pulse; and (j) repeating steps (b) through (i) above until the memory cells have the selected Vt levels.