Patent ID: 6208558
Filing Date: 2001-03-27
Classification: G11C

Abstract:
In a non-volatile memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to the respective rows of the memory cells, a plurality of bit lines coupled to the respective columns of the memory cells, each of the memory cells comprising a source and a drain, the bit lines arranged in a plurality of sets, and an internal voltage supply pump for generating an internal pump voltage to provide a pump current for programming the memory cells on the bit lines one set at a time in an embedded program mode, an acceleration circuit for fast programming of the memory cells comprising:(a) an acceleration input for providing an acceleration voltage to supply a current for programming the memory cells on all sets of the bit lines at a time in a fast program mode, the acceleration voltage being greater than the internal pump voltage; and(b) a triggering circuit, coupled to the acceleration input, for causing the acceleration voltage to be supplied to the memory cells on all sets of the bit lines at a time in response to a presence of the acceleration voltage at the acceleration input.