Patent ID: 7045829
Filing Date: 2006-05-16
Classification: H01L,H01S

Abstract:
1. A Group III nitride compound semiconductor comprising: a substrate, an n-type cladding layer formed on or above said substrate, an emission layer formed on or above said n-type cladding layer, and a p-type cladding layer formed on or above said emission layer, said emission layer satisfying the formula where 0≦x1≦1, 0≦y1≦1, and 0≦x1+y1≦1, and having a thickness 0.1 μm to 1.0 μm which is larger than diffusion length of holes into which electrons are injected from said n-type cladding layer and holes are injected from said p-type cladding layer; said n-type cladding layer satisfying the formula where 0≦x2≦1, 0≦y2≦1, and 0≦x2+y2≦1, being doped with a donor impurity, having a forbidden band wider than a forbidden band of said emission layer and having a lattice constant substantially equal to a lattice constant of said emission layer but being not matched with the lattice of said substrate; and said p-type cladding layer satisfying the formula where 0≦x3≦1, 0≦y3≦1, and 0≦x3+y3≦1, being doped with an acceptor impurity, having a forbidden band wider than said forbidden band of said emission layer; wherein the relative amounts of the constituent materials in each of said n-type cladding layer, said p-type cladding layer, and said emission layer are selected such that upon applying an external driving voltage to the semiconductor, said external driving voltage sufficient to bias said semiconductor above a threshold voltage: