Patent ID: 7831653
Filing Date: 2010-11-09
Classification: H04L

Abstract:
1. A template of integrated circuit for a plurality of data transmission protocols, the template comprising: (a) a plurality of input/output (I/O) blocks; (b) a plurality of data register transfer level logic (RTL) shells encapsulating the I/O blocks, the plurality of RTL shells encapsulating logic of a diffused hardmac and including: serializer/deserializer (SERDES) hard macro components, clock generators, microprocessors, a peripheral component interconnect (PCI) bus controller and a universal serial bus (USB) bus controller, wherein the plurality of RTL shells are configured for providing a logical interface for connecting signals to external chip I/Os; (c) a plurality of physical layers (PHYs) connected to each of the plurality of I/O blocks; and at least one of the plurality of I/O blocks and the connected one of the plurality of PHYs are established to transmit and receive data in a first protocol, and at a second one of the plurality of I/O blocks and a connected second one of the plurality of PHYs are established to transmit and receive data in a second protocol, wherein at least one of the plurality of PHYs is stubbed; (d) a plurality of configurable gate arrays, a first portion of which is configured into a first protocol layer connected to at least one of the plurality of PHYs consistent with the first protocol, and a second portion of the plurality of gate arrays is programmed to establish a second protocol layer connected to at least a second one of the plurality of PHYs consistent with the second protocol; (e) a plurality of memory arrays generated from diffused memory and/or gate array configured to establish the first protocol layer and a second portion of which is configured to establish the second protocol layer,