Patent ID: 6134677
Filing Date: 2000-10-17
Classification: G11C

Abstract:
In a testing system having a processor and an output device, an apparatus for identifying errors in a semiconductor device, wherein the semiconductor device has a plurality of circuit locations addressable by logical addresses, the apparatus comprising:an error memory for storing error data corresponding to a comparison between data applied to the plurality of circuit locations in the semiconductor device and data read from the plurality of circuit locations, wherein the error memory is addressable by physical addresses; anda programmable router circuit coupled to the error memory and the semiconductor device, wherein the programmable router circuit converts the logical addresses to physical addresses and causes the error data from the plurality of circuit locations in the semiconductor device to be routed to selected locations in the error memory, wherein the error memory provides error data corresponding to selected physical addresses to the processor in response to spatial addresses from the processor, and wherein the error data corresponds to the spatial addresses capable of being visually output by the output device.