Patent ID: 6480425
Filing Date: 2002-11-12
Classification: G11C

Abstract:
A semiconductor device having a memory circuit comprising:a plurality of first bit line pairs; a plurality of word lines; a plurality of dynamic memory cells each disposed at the intersection of one bit line of the first bit line pair and the word line; amplifying circuits each formed of a CMOS latch circuit having a pair of input/output nodes corresponding to the first bit line pair; a second bit line pair provided commonly to the input/output node pairs of the CMOS latch circuits; and pairs of MOSFETs which connect the input/output node pair of the CMOS latch circuits to the second bit line pair in response to the reception of a selection signal, wherein said selection signal has a signal amplitude greater than a voltage difference of the input/output node pair of the CMOS latch circuit in its latched state.