Patent ID: 7940093
Filing Date: 2011-05-10
Classification: H03K

Abstract:
1. An output circuit with overshoot-reducing function, the output circuit comprising: an input end for receiving an input signal; an output end; a PMOS comprising: an NMOS comprising: a rising-edge trigger biasing circuit coupled between the input end and the output end for outputting a third voltage to the output end so as to reduce overshoot on the output end according to a rising edge of the input signal, the rising-edge trigger biasing circuit comprising: a falling-edge trigger biasing circuit coupled between the input end and the output end for outputting a fourth voltage to the output end so as to reduce overshoot on the output end according to a falling edge of the input signal, the falling-edge trigger biasing circuit comprising: an inverter coupled to the input end for generating an inverted input signal according to the input signal; a first delay circuit coupled between the inverter and the control end of the PMOS for delaying the inverted input signal for a first predetermined period; and a second delay circuit coupled between the inverter and the control end of the NMOS for delaying the inverted input signal for a second predetermined period; wherein the second predetermined period is different from the first predetermined period; wherein the third voltage is higher than the second voltage, and the fourth voltage is lower than the first voltage.