Patent ID: 8949490
Filing Date: 2015-02-03
Classification: G09G,H04N

Abstract:
1. A data reception circuit comprising, a clock generation block configured to divide a first clock based on clock information, said first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, said clock information indicating a cyclical relationship between said first clock and a second clock serving as the clock of predetermined data, said clock generation block further outputting the divided clock as said second clock, wherein said transmission stream has said video data, said predetermined data, and said clock information multiplexed therein, said transmission stream being transmitted in synchronism with said first clock generated by amplifying by a predetermined scaling factor a clock for the transfer of said video data within an apparatus for transmitting said transmission stream; said data reception circuit further comprising a demultiplexing block configured to demultiplex said transmission stream having been transmitted into said video data, said predetermined data, and said clock information; said clock generation block generating said second clock by dividing said first clock based on the demultiplexed clock information.