Patent ID: 6366109
Filing Date: 2002-04-02
Classification: G01R

Abstract:
A semiconductor device testing system for testing a semiconductor device with a plurality of pins by applying a test signal, comprising:a tester controller to output generation data for generating said test signal, a pin designating bit which designates a logical pin number of a pin to which said test signal is applied, and pin assignment data denoting a relationship between said logical pin number and a physical pin number of said semiconductor device to which said test signal is applied; a pin assignment converter to receive said logical pin number and to convert said logical pin number into said physical pin number based on said pin assignment data; and a test unit to prepare said test signal according to said generation data for application to a physical pin designated by said physical pin number, wherein said pin assignment converter includes: a pin map memory which stores said pin assignment data, having address terminals for inputting said pin designating bit, and data terminals for outputting output data; and a multiplexer which receives said output data from said pin map memory and said pin designated bit from said tester controller, and outputs either said output data or said pin designating bit as said physical pin number; wherein said tester controller outputs to said pin assignment converter a recognition bit used for determining whether or not said logical pin number and said physical pin number are converted.