Patent ID: 6417045
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device having bit lines, word lines and memory cells each including a MISFET and a capacitor element, each memory cell being connected to one of said word lines and said bit lines, comprising the steps of:(a) forming a gate electrode, a source region and a drain region for said MISFET, on a surface of a semiconductor substrate; (b) forming a first insulating film over said gate electrode; (c) performing a polishing of the surface of said first insulating film; (d) forming a second insulating film over said first insulating film; (e) forming grooves in said second insulating film; (f) forming a first conductive film in said grooves, for forming said bit lines; (g) forming a third insulating film over said second insulating film; (h) forming openings in said second insulating film and said third insulating film; (i) forming second conductive films over said openings, wherein one of said second conductive films is connected to one of said source and drain regions of said MISFET; (j) forming a dielectric film on said second conductive films; and (k) forming a third conductive film over said dielectric film.