Patent ID: 6615385
Filing Date: 2003-09-02
Classification: H03M

Abstract:
An iterative decoder comprising:a first adder having a first port for receiving information symbols and a second port for receiving an extrinsic information signal EXT2; a first component decoder for receiving first parity symbols, and for decoding the information symbols using the first parity symbols and an output signal of the first adder; a first subtractor having a third port for receiving an output of the first component decoder, and a fourth port for receiving an inverted signal of the extrinsic information signal EXT2; an interleaver coupled to an output of the first subtractor, for interleaving the decoded information symbols received from the first component decoder; a second component decoder for receiving an output of the interleaver and second parity symbols, and for decoding the information symbols from the interleaver output using the received signals; a deinterleaver for deinterleaving an output of the second component decoder; a second subtractor having a fifth port for receiving an output of the deinterleaver and a sixth port for receiving an inverted output of the first subtractor, said second subtractor having output to the second port and inverted output to the fourth port; a hard decision device for converting output received from the first component decoder to binary information bits by hard decision decoding; an error detector for checking for errors in the binary information bits received from the hard decision device and for generating a no error signal if no errors are detected; and an output buffer for storing the binary information bits received from the hard decision device and for outputting the stored binary information bits in response to the no error signal.