Patent ID: 8838950
Filing Date: 2014-09-16
Classification: G06F,H04L

Abstract:
1. A secure processing system, comprising: a main processor unit (MPU) coupled to a processor bus; an attached processor complex (APC) coupled to the processor bus and comprising: wherein the APC is configured to receive commands from the MPU via the processor bus and to operate in a non-isolated state and an isolated state; and wherein in response to a LOAD command to operate in the isolated state received from the MPU, the APC is configured to partition the unpartitioned local store into a general access section accessible by the MPU and an isolated section accessible only by the APU, to transition from the non-isolated state to the isolated state, to transfer a set of computer instructions or data into the isolated section of the local store, and to use the master key in the isolated section of the local store to extract and decrypt a portion of the computer instructions or data stored in the isolated section of the local store, thereby producing another cryptographic key, and wherein in response to producing the another cryptographic key, the master cryptographic key is erased from the isolated section of the local store, and wherein the MPU can issue commands to the local store when not in the isolated state and is restricted to the general access section of the local store in the isolated state, and when the APC is operating in the isolated state, the APC is configured to respond to an EXIT command received from the MPU by clearing the isolated section of the local store and eliminating the isolated section of the local store, thereby causing the general access section to occupy the entire local store, and wherein the another cryptographic key is used to authenticate a secondary application loaded, in segments, in the isolated section of the local store, and wherein the EXIT command is issued after authentication of the secondary application, and wherein an isolate enable bit is used to control issuance of the LOAD command, and wherein during a transition to the isolated state, MPU requests to write to the isolated section of the local store are disregarded by the APU and MPU requests to read from the isolated section of the local store return a null value.