Patent ID: 7829421
Filing Date: 2010-11-09
Classification: H01L

Abstract:
1. A method, comprising: forming a recess adjacent to a gate electrode structure including a sidewall spacer within a semiconductor layer formed on a buried insulating layer; introducing a P-type dopant into said semiconductor layer at a bottom surface thereof after forming said recess; forming a first strained silicon germanium material in said recess after introducing said P-type dopant, wherein said first strained silicon germanium material is a substantially undoped material; forming a second strained silicon germanium material on said first strained silicon germanium material, said second strained silicon germanium material comprising a P-type dopant introduced during the forming of the second strained silicon germanium material; forming drain and source extension regions adjacent to said gate electrode structure by an ion implantation process; and performing an anneal process for defining respective PN junctions with a floating body region to cause said P-type dopant in said semiconductor layer at said bottom surface and said P-type dopant in said second strained silicon germanium material to diffuse into said first strained silicon germanium material to define a first portion of said PN junctions located within said first strained silicon germanium material and spanning between said second strained silicon germanium material and said bottom surface, and wherein a second portion of said PN junctions is located within one of said first or second strained silicon germanium materials.