Patent ID: 9076552
Filing Date: 2015-07-07
Classification: G11C,H01L

Abstract:
1. A device, comprising: a substrate comprising an N-well region, a first P-well region and a second P-well region, the first and second P-well regions being arranged on opposite sides of the N-well region and spaced apart along a width direction; a dual port static random access memory cell comprising a first pull-up transistor and a second pull-up transistor provided in said N-well region, a first pair of pull-down transistors and a first pair of access transistors provided in said first P-well region, and a second pair of pull-down transistors and a second pair of access transistors provided in said second P-well region; wherein each of said first pair of pull-down transistors and said second pair of pull-down transistors comprises a first pull-down transistor and a second pull-down transistor, wherein an active region of said first pull-down transistor and an active region of said second pull-down transistor are spaced apart along said width direction.