Patent ID: 9100042
Filing Date: 2015-08-04
Classification: H03M

Abstract:
1. An apparatus for decoding data, comprising: processing circuitry including a pre-processing engine and a decoding pipeline, the processing circuitry configured to perform: receiving a data stream, the data stream encoded by an encoding algorithm and transmitted as a plurality of variable length symbols; dividing the data stream into a sequence of blocks, each block having a sequence of adjacent bit positions starting with a first bit position and ending with a last bit position; pre-processing each block prior to fully decoding each block by the pre-processing engine, wherein pre-processing includes, for each block, selecting a bit position in a current block and determining a starting position of a first symbol in an adjacent block based on the selected bit position, wherein determining is initially performed for the last bit position in the current block, and is repeated sequentially for each preceding bit position through and including the first bit position; and inputting the data stream into the pipeline and fully decoding each block by decoding a first block starting at the first bit position and decoding each adjacent block starting at the starting position.