Patent ID: 7439774
Filing Date: 2008-10-21
Classification: H03K

Abstract:
1. A multiplexing circuit, comprising: a plurality of multiplexing units, each of the plurality of multiplexing units receiving a input signal, an initialization signal, and a selection control signal and outputting a selection output signal, each of the multiplexing units comprising: a multiplexing output unit for performing a logic operation on the selection output signals received from each of the plurality of multiplexing units, wherein each of the plurality of multiplexing units is initialized in response to the initialization signal and outputs the input signal as the selection output signal in response to the selection control signal; and the initialization signal is shared by two of the plurality of multiplexing units, and the initialization signal which is input to one of the two multiplexing units is the selection control signal to be input to the other of the two multiplexing units.