Patent ID: 6108771
Filing Date: 2000-08-22
Classification: G06F

Abstract:
An out-of-order processing system which processes instructions out of the sequential order of the instruction stream, said instructions addressing logical registers, said out-of-order processing system comprising:a physical register array for storing physical registers that represent instances of the logical registers,an in-order list of registers having a plurality of logical register elements, said logical register elements each including a representation of one of said physical registers, said physical register representation corresponding to the architected state of said logical register element in the out-of-order processing system, said in-order list of registers being arranged in the sequential order of the logical registers for directly, sequentially relating each logical register to the physical register representing the architected state of the logical register in the out-of-order processing system, anda link list providing a link between a physical register representing an instance of a logical register and the physical register representing the preceding instance of the same logical register, in order to provide a concatenation of the physical registers according to the order of the corresponding logical register's instances in the instruction stream.