Patent ID: 7853634
Filing Date: 2010-12-14
Classification: G06F,G06K,H03K

Abstract:
1. An Integrated circuit(IC) having a single-instruction-multiple-data (SIMD) circuit, the SIMD circuit comprising: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the arithmetic logic unit comprises a plurality of adders, the plurality of adders controlled by at least some bits of the second opcode, wherein a first adder of the plurality of adders adds a first plurality of input bits to produce first summation bits and a first carry bit, wherein a second adder of the plurality of adders adds a second plurality of input bits to produce second summation bits and a second carry bit, and wherein a third adder of the plurality of adders adds a third plurality of input bits to produce third summation bits and a third carry bit, and the first, second, and third adders operate concurrently with each other.