Patent ID: 6212591
Filing Date: 2001-04-03
Classification: G06F,H03K

Abstract:
In an integrated circuit of the type having a bus of a fixed bit width for transmission of information, a plurality of input/output terminals and a plurality of physical ports, each of the physical ports having a fixed bit width and connecting the bus to a corresponding set of input/output terminals, configuration circuitry defining one or more virtual ports comprising:a plurality of configurable input/output interface elements, each interface element including a storage means and connecting one of a plurality of bits of the bus to a corresponding one of the input/output terminals;at least one selectable clock connected to the storage means of each interface element;at least one programmable enable connected to each interface element, wherein multiple clocks and program enables may be connected to different ones of the interface elements and wherein each of the clocks and programmable enables are configured to control the activation of the interface element to which it is connected; andwherein the activated input/output elements make up a virtual port, the virtual port being of an arbitrary bit width that is less than or equal to the fixed bit width of the physical ports.