Patent ID: 6604060
Filing Date: 2003-08-05
Classification: G06F

Abstract:
In a data processing system having a plurality of processors, a method of dynamically calculating a difference between a time it takes a signal to travel between a first test processor and a second test processor and a time it takes a signal to travel between the first test processor and a third test processor, the first test processor being one of a first pair of test processors, the second test processor being one of the first pair of test processors, and the third test processor being one of a second pair of test processors,said method comprising:A) calculating a first delay time for the time it takes the signal to travel between the first test processor and the second test processor by: 1) providing a Synchronize signal to each of the first and second test processors; 2) waiting for the Synchronize signal by each of the first and second test processors; 3) providing a local copy of a specified cache line in a local cache memory of the first test processor before the synchronize signal is provided in substep A)1); 4) signaling the first test processor to invalidate the local copy of the specified cache line in the local cache memory of the first test processor after both the first and second test processors complete the waiting in substep A)2); 5) recording the invalidating in substep A)4) in a trace entry in a trace in the first test processor; and 6) finding the trace entry in the trace containing the invalidating in substep A)4); B) calculating a second delay time for the time it takes the signal to travel between the first test processor and the third test processor by: 1) providing a Synchronize signal to each of the first and third test processors; 2) waiting for the Synchronize signal by each of the first and third test processors; 3) providing a local copy of a specified cache line in a local cache memory of the first test processor before the synchronize signal is provided in substep B)1); 4) signaling the first test processor to invalidate the local copy of the specified cache line in the local cache memory of the first test processor after both of the test processors complete the waiting in substep B)2); 5) recording the invalidating in substep B)4) in a trace entry in a trace in the first test processor; and 6) finding the trace entry in the trace containing the invalidating in substep B)4); and C) calculating the difference by subtracting the first delay time from the second delay time.