Patent ID: 8956916
Filing Date: 2015-02-17
Classification: H01L,H05K

Abstract:
1. A method of fabricating a microelectronic assembly, comprising: providing an interconnection substrate having a first surface, a second surface remote from the first surface in a vertical direction, conductive structure thereon, and terminals exposed at the second surface for connection with a component; electrically connecting signal contacts of at least two logic chips to one another through the conductive structure of the substrate for transfer of signals between the logic chips, the signals representing at least one of data or instructions, the logic chips being adapted to simultaneously execute a set of instructions of a given thread of a process, each logic chip having a front surface confronting the first surface of the interconnection substrate; and electrically connecting contacts exposed at a front surface of a memory chip to the signal contacts of at least one of the at least two logic chips through the conductive structure of the substrate, the front surface of the memory chip confronting the rear surface of each of the at least two logic chips.