Patent ID: 6154831
Filing Date: 2000-11-28
Classification: G06F

Abstract:
A device, comprising:a first register partitioned into a plurality of first slots; andan instruction decode unit for decoding an instruction to specify operands and operations to be performed on the operands, wherein the instruction comprises:a first field of bits within said coded instruction for encoding a first pair of slots within said plurality of first slots and a specific value within a plurality of values;a second field of bits within said coded instruction for encoding a second pair of slots within said plurality of first slots and a specific value within a plurality of values, wherein said second field of bits is less in number than the combination of said plurality of first slots and said plurality of values;an operation encoded plurality of bits within said coded instruction comprising a first portion and a second portion of bits, said first portion of bits are used for selecting a first operation upon an operand within one of said plurality of first slots or one of said plurality of values, and said second portion of bits are used for selecting a second operation upon an operand within one of said first slots or one of said plurality of values.