Patent ID: 6677795
Filing Date: 2004-01-13
Classification: H03K

Abstract:
A flip-flop circuit, comprising:a master flip-flop coupled to receive a data input; a slave flip-flop coupled to provide a data output; a first inverter coupled to receive a clock signal and providing an inverted clock signal; a second inverter coupled to receive the inverted clock signal and providing a normal clock signal; and a data transfer circuit that provides a data path between the master flip-flop and the slave flip-flop, the data transfer circuit includes a first transfer gate of a first conductivity type providing a first controllable impedance path between the master flip-flop and the slave flip-flop and having a first control terminal connected to receive the clock signal; a second transfer gate of the first conductivity type providing a second controllable impedance path in parallel with the first controllable impedance path and having a second control terminal coupled to receive the normal clock signal; and a third transfer gate of a second conductivity type providing a third controllable impedance path in parallel with the first controllable impedance path and having a third control terminal coupled to receive the inverted clock signal.