Patent ID: 8117483
Filing Date: 2012-02-14
Classification: G06F

Abstract:
1. A method for operating a memory comprising: performing a read test for each of a plurality of memory devices to generate a read delay time of each of the plurality of memory devices, wherein the plurality of memory devices includes a prime memory device and a subset of memory devices not including the prime memory device, wherein the subset includes at least one memory device; for each memory device of the subset, comparing the read delay time for the prime memory device with the read delay time of the each memory device of the subset of memory devices to generate a differential delay for the each memory device of the subset; for each memory device of the subset, combining a write test start time of the prime memory device and a differential delay of the each memory device to generate a write test start time for the each memory device of the subset; for each memory device of the subset, performing a write test for the each memory device using the write test start time for the each memory device of the subset to generate a write launch time for the each memory device of the subset.