Patent ID: 9076878
Filing Date: 2015-07-07
Classification: G11C,H01L

Abstract:
1. A method, comprising: manufacturing on a semiconductive substrate an integrated circuit with a non-volatile memory including memory cells each including a charge accumulation transistor and a selection transistor, the manufacturing including: forming in the substrate a deep first doped region, the first doped region forming a source region of common selection transistors of a pair of the memory cells, forming a buried gate in the substrate, the buried gate including deep parts extending between an upper face of the substrate and the first doped region, forming between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of the selection transistors of the pair of the memory cells, such that the selection transistors of the pair of the memory cells have channel regions extending between the first doped region and the second doped region, along opposite faces of the two adjacent deep parts of the buried gate, the faces extending in planes parallel to a channel direction of the charge accumulation transistors, and forming along opposite upper edges of the buried gate, third doped regions forming source regions of the charge accumulation transistors of the pair of memory cells, each third doped region being electrically coupled to the second doped region.