Patent ID: 6017794
Filing Date: 2000-01-25
Classification: H01L

Abstract:
A method of fabricating a thin film semiconductor circuit including a plurality of thin film transistors at least some of which are floating gate thin film transistors in a high density integrated circuit configuration comprising the steps of:depositing and patterning a lower metallization layer of chromium in which the pattern includes formation of control gates for the thin film transistors and at least some interconnections and contacts for the control gates;depositing a dielectric layer on the patterned chromium layer with metallic floating gates embedded in at least some of the transistors over the control gates in the formation of the floating gate transistors;depositing a layer of .alpha.-Si:H and doping the top portion of the layer to form source and drain regions for the thin film transistors;depositing and patterning chromium caps over the source and drain regions;using the chromium caps as an etching mask, etching channels in the thin film transistors by removing the doped portion of the layer between the source and drain regions;patterning and etching isolating trenches around the transistors by removing the amorphous silicon layer between transistors;filling the trenches with an insulating layer to form a planar surface;patterning the surface and etching to the chromium caps and chromium contacts in the lower metallization using the chromium as an etch stop; anddepositing metal connections in the etched vias to form connections with the chromium caps and also to form an interconnecting metallization layer on said planar surface.