Patent ID: 8745200
Filing Date: 2014-06-03
Classification: G01R,G06F

Abstract:
1. A system to test processors, said system comprising: a plurality of testers, wherein each tester comprises a processor to be tested, and wherein a subset of said plurality of testers is configured to operate in a mode of a plurality of modes during testing, and wherein said processor is operable to be configured in each of said plurality of modes, and wherein said plurality of modes comprises a first addressing mode of a first number of bits and a second addressing mode of a second number of bits; a plurality of user systems, wherein a user system of said plurality of user systems is operable to select a mode from said plurality of modes for testing of a respective processor included in a respective tester, and wherein said user system of said plurality of user systems is operable to send a test request comprising said selected mode; and a scheduler system operable to receive said test request and responsive thereto select a tester from said plurality of tester systems to carry out said testing according to said selected mode and further according to said test request, wherein said scheduler system is operable to select said tester based on said selected mode of said processor of said tester, wherein the scheduler system maintains configuration information indicating which processors are setup to test which modes, and also status information indicating which tester systems are presently available for testing.