Patent ID: 7749827
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A method of manufacturing a Thin Film Transistor (TFT), the method comprising: forming an active layer and a gate electrode insulated from each other by a gate insulating layer on a substrate and forming an InterLevel Dielectric (ILD) layer to cover the active layer and the gate electrode, at least one of the gate insulating layer and the ILD layer containing silicon nitride; thermally treating the ILD layer; forming source/drain contact holes in at least one of the gate insulating layer and the ILD layer; and forming source/drain electrodes, the source/drain electrodes being arranged on the ILD layer, contacting the active layer through the source/drain contact holes, wherein forming the source/drain electrodes comprises: forming a first metallic layer pattern arranged on the ILD layer and contacting the active layer through the source/drain contact holes, said first metallic layer formed of Cr, Cr alloy, Mo, or Mo alloy; forming a second metallic layer pattern on said first metallic layer and formed of Al, AlSi, AlNd, or AlCu; and forming a third metallic layer pattern on said second metallic layer and formed of Ti, Ti alloy, Ta, or Ta alloy, wherein the active layer comprises a poly silicon, wherein the thermally treating of the ILD laver must be performed prior to forming the source and drain electrodes.