Patent ID: 6768182
Filing Date: 2004-07-27
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a first well of a first conductivity type and a second well of a second conductivity type opposite to the first conductivity type, said first and second wells being disposed adjacent to each other; a straight well isolation structure comprising a shallow trench formed on a boundary of said first and second wells; a first device region of the second conductivity type provided in said first well; a second device region of the first conductivity type provided in said second well, said first and second device regions being disposed to oppose each other face-to-face, with a first section of said well isolation structure disposed between said first and second device regions; a third device region of the second conductivity type provided in said first well, said third device region being positioned separately from and adjacent to said first device region; a fourth device region of the first conductivity type provided in said second well, said third and fourth device regions being disposed not to oppose each other face-to-face, with a second section of said well isolation structure disposed between said third and fourth device regions, said fourth device region being positioned separately from and adjacent to said second device region; wherein said second section of said well isolation structure is wider than said first section of said well isolation structure.