Patent ID: 7986556
Filing Date: 2011-07-26
Classification: G11C,H01L

Abstract:
1. A bandgap engineered, dielectric charge trapping non-volatile memory device, comprising: a semiconductor body including a channel region having an n-type doping; a tunnel dielectric structure on the channel; a dielectric charge trapping layer on the tunnel dielectric structure; a blocking dielectric layer on the charge trapping layer; a gate on the blocking dielectric layer; wherein the charge trapping structure adapted to trap charge to establish a threshold voltage for a high threshold state in a charge storage site in the dielectric charge trapping layer; and the tunnel dielectric structure includes a bottom dielectric layer having a hole tunneling barrier height, a middle dielectric layer having a hole tunneling barrier height less than that of the bottom dielectric layer, a top dielectric layer having a hole tunneling barrier height greater than that of the middle dielectric layer to isolate the middle dielectric layer from charge trapping layer; and circuitry to induce band to band tunneling hot electron injection into the charge trapping structure to establish the high threshold state; and to induce FN tunneling of holes into the charge trapping structure to lower the threshold voltage to a low threshold state.