Patent ID: 7788439
Filing Date: 2010-08-31
Classification: G06F,Y02D

Abstract:
1. A bus interface, comprising: a plurality of receivers to establish simplex connections with corresponding transmitters of another bus interface; a plurality of transmitters to establish simplex connections with corresponding receivers of said another bus interface; a link control module to negotiate a bidirectional link with said another bus interface in which a selected set of said receivers are configured into a first uni-directional sub-link in a downstream direction and a selected set of said transmitters are configured into a second uni-directional sub-link in an upstream direction, where the number of active simplex connections in each of said first uni-directional sub-link and said second un-directional sub-link are independently selectable; the bus interface having a symmetric mode in which the upstream bandwidth and downstream bandwidth are equal and an asymmetric mode in which the upstream bandwidth and downstream bandwidth are selected to be asymmetric in order to reduce bus power consumption when bus traffic patterns are asymmetric.