Patent ID: 6021453
Filing Date: 2000-02-01
Classification: H04L,H04Q

Abstract:
A microprocessor unit for connection between means forming an upstream input channel for communicating address and control signals and including a first bi-directional data bus, and means forming a downstream output channel for communicating address and control signals and including a second bi-directional data bus, said microprocessor unit comprising:a multiport memory means having at least a first port and a second port, said first port being connectable to said upstream input channel;local processor means coupled to said second port and having a third port, said third port being connectable to said downstream output channel, said local processor means being capable of reading from and writing to an external memory through said third port; andinterface means associated with said first port for selectively bringing said input channel into congruence with said output channel, whereby a plurality of said units can be linked together, with said first port being connectable to either a host computer or an upstream unit through the upstream input channel and said third port being connectable to a downstream unit through the downstream output channel.