Patent ID: 6222396
Filing Date: 2001-04-24
Classification: H03K

Abstract:
An electronic system comprising:a plurality of delay stages, each delay stage of the plurality having a first control signal input terminal, a first control signal output terminal, and a second control signal input terminal except for a first delay stage;the first control signal input terminal of each delay stage of the plurality, except for the first delay stage of the plurality, coupled to the first control signal output terminal of another delay stage of the plurality, and the first control signal input terminal of the first delay stage and the second control signal input terminals are for receiving a first input control signal from a signal source;a plurality of output buffer drivers, each output buffer driver of the plurality having a first control terminal and having a first output terminal for coupling to a load;the first control terminal of one of the plurality of output buffer drivers coupled to the first control signal output terminal of one delay stage of the plurality; andat least one switch interposed between at least one of the second control signal input terminals and the first input control signal from the signal source, said at least one switch to either activate or deactivate at least one of the plurality of output buffer drivers.