Patent ID: 7157787
Filing Date: 2007-01-02
Classification: H01L

Abstract:
1. A wafer system, comprising: a first wafer, the first wafer having a front side and a back side; a first tapered via formed in the first wafer through an active layer of the back side of the first wafer and an interlayer dielectric layer of the front side of the first wafer, the first tapered via having a larger face and a smaller face, the larger face located at the back side of the first wafer; a second wafer, the second wafer having a front side and a back side, the back side of the second wafer facing the back side of the first wafer; and a second tapered via formed in the second wafer, the second tapered via having a larger face and a smaller face, the larger face located at the back side of the second wafer and bonded to the larger face of the first tapered via.