Patent ID: 7619439
Filing Date: 2009-11-17
Classification: H03K

Abstract:
1. A semiconductor device comprising: a voltage generation circuit which generates reference voltages; a dummy buffer circuit; a comparison circuit which compares the reference voltages and an output voltage of said dummy buffer circuit; a counter which counts a clock signal until a comparison result of said comparison circuit is matched, wherein said dummy buffer circuit adjusts its own output impedance based on a count value of said counter; n (n being an integer greater than or equal to 2) adjustment value holding circuits which hold count values when a comparison result of said comparison circuit is matched; and n output buffer circuits which respectively adjust their own output impedances, based on count values respectively held by said adjustment value holding circuits; wherein said voltage generation circuit generates the reference voltages respectively corresponding to said n output buffer circuits, said n adjustment value holding circuits hold respective count values when a comparison result, obtained based on respectively corresponding reference voltages, matches, and said dummy buffer circuit adjusts its own output impedance corresponding respectively to said n output buffer circuits.