Patent ID: 8278983
Filing Date: 2012-10-02
Classification: H03L

Abstract:
1. A phase locked loop (PLL) circuit, comprising: a phase comparator to compare a phase of a reference signal with a phase of a feedback signal; a voltage/current converter to convert a voltage in accordance with an output of the phase comparator; a current controlled oscillator to convert a current output of the voltage/current converter into an output signal at a frequency in accordance with the output of the phase comparator; a feedback loop to return the output signal of the current controlled oscillator and supplying the output signal as the feedback signal; and a delay circuit to delay the phase of the output signal output from the current controlled oscillator to a load circuit; wherein the delay circuit is provided outside the feedback loop; wherein the current controlled oscillator includes a ring circuit including an odd number of inverter circuits respectively coupled to one another via transfer gates of the inverter circuits in a ring shape; wherein a control voltage generated by converting the output current of the voltage/current converter is input to gate terminals of the transfer gates included in the current controlled oscillator; wherein the delay circuit includes an inverter circuit and a transfer gate, respectively, having similar configurations to the respective inverter circuit and transfer gate of the current controlled oscillator; and wherein the control voltage is input to the gate terminals of the transfer gates included in the delay circuit.