Patent ID: 8836449
Filing Date: 2014-09-16
Classification: H03H

Abstract:
1. An integrated wafer level package, comprising: (a) a first wafer having a first surface and an opposite, second surface; (b) a second wafer having a first surface and an opposite, second surface, wherein the first wafer and the second wafer are spaced apart such that the second surface of the first wafer faces the first surface of the second wafer, defining a first gap therebetween; (c) a first bulk acoustic wave (BAW) filter disposed on the second surface of the first wafer; (d) a second BAW filter disposed on the first surface of the second wafer, wherein the first BAW filter faces directly the second BAW filter, defining a second gap therebetween; (e) a seal ring disposed between the first wafer and the second wafer such that a seal is formed surrounding the first BAW filter and the second BAW filter and defining a cavity between the seal ring and the first BAW filter and the second BAW filter; (f) at least one external contact that is accessible externally to the wafer level package and is electrically coupled to at least one of the first BAW filter and the second BAW filter; (g) a first protective layer surrounding the first BAW filter and defining a cavity therebetween; and (h) a second protective layer surrounding the second BAW filter and defining a cavity therebetween.