Patent ID: 7333374
Filing Date: 2008-02-19
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array having a standard memory cell array part in which dynamic memory cells are arranged in a matrix pattern, and a redundant memory cell array having a redundant memory cell set up to replace a defective memory cell in the standard memory cell array part; an access control part controlling external access operation and refresh access operation regarding the memory cell array; and a redundancy judgment circuit executing redundancy judgment for the external access operation and the refresh access operation to determine whether a subjected memory cell is the redundant memory cell or not, controlling so as to access the redundant memory cell if the subjected memory cell is the redundant memory cell, and controlling so as to access the memory cell in the standard memory cell array if the subjected memory cell is not the redundant memory cell, wherein the refresh access operation is executed according to generation of a refresh access request indicating a start of the refresh access operation, an external access request indicating a start of the external access operation generates during a time from start of a redundancy judgment for the refresh access operation until completion of the refresh access operation, and the access control part makes the redundancy judgment circuit execute the redundancy judgment for the external access operation in parallel to the refresh access operation, and execute the external access operation after completion of the refresh access operation.