Patent ID: 6177307
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for fabricating an integrated circuit having a cell area and a peripheral circuit area in a semiconductor substrate, said method comprising the following steps of:(a) forming a memory device and a transistor within said cell area and said peripheral circuit area, respectively, wherein said memory device has a doped region formed in said semiconductor substrate;(b) forming a first insulating layer overlying said cell area and said peripheral circuit area;(c) patterning said first insulating layer to form a trench over said doped region and a recess in said peripheral circuit area;(d) patterning said first insulating layer through said trench to form a contact window;(e) forming a landing plug in said contact window in contact with said doped region;(f) sequentially forming a second insulating layer and a third insulating layer overlying said cell area and said peripheral circuit area;(g) patterning said second insulating layer and said third insulating layer to form an opening over said doped region;(h) forming a first conductive layer on the bottom and sidewall of said opening in contact with said landing plug;(i) removing said third insulating layer in said cell area by a planarization process;(j) removing said second insulating layer in said cell area;(k) forming a dielectric layer on said first conductive layer; and(l) forming a second conductive layer on said dielectric layer.