Patent ID: 8268710
Filing Date: 2012-09-18
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate including a memory cell region and peripheral circuit regions; forming gate electrodes including gate conductive patterns and capping patterns on the memory cell region and the peripheral circuit regions; forming an interlayer dielectric covering the gate electrodes; patterning the interlayer dielectric to form first contact holes in the memory cell region exposing the semiconductor substrate along side of the gate electrode and second contact holes in the peripheral circuit regions exposing a portion of the capping pattern to space apart a bottom surface of the second contact hole from a top surface of the gate conductive pattern; filling a first plug conductive layer in the first contact holes and a second plug conductive layer in the second contact holes; and performing a planarizing process to expose the capping patterns to form first contact plugs in the memory cell region and second contact plugs in the peripheral circuit region.