Patent ID: 6228719
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A process for the manufacturing of a MOS-gated power device, comprising the steps of:a) forming a heavily doped semiconductor substrate;b) forming a semiconductor layer of a first conductivity type and with a first resistivity value;c) selectively introducing into the semiconductor layer a dopant suitable for forming first regions of the first conductivity type and with a second resistivity value, intercalated by second regions of the first conductivity type with the first resistivity value;d) forming on the semiconductor layer a conductive insulated gate layer;e) selectively removing the conductive insulated gate layer to open windows over selected portions of a surface of the semiconductor layer, said selected portions of the surface being located over those among the first regions and the second regions which have a higher resistivity value;f) forming at said selected portions of the surface of the semiconductor layer body regions of a second conductivity type;g) forming in the body regions source regions of the first conductivity type.