Patent ID: 8981490
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) integrated circuit (IC), comprising: implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface of a substrate having a first gate stack thereon for forming n-type lightly doped drain regions (NLDD regions) to provide n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on said IC; implanting a p-type dopant at second masking level that exposes an n-region of said substrate surface having a second gate stack thereon for forming p-type lightly doped drain regions (PLDD regions) to provide p-source/drain extension regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on said IC, and retrograde implanting a second n-type dopant including through said first gate stack to form a deep nwell (DNwell) for said portion of said plurality of NMOS transistors, wherein a depth of said DNwell is shallower below said first gate stack as compared to a depth of said DNwell under said NLDD regions, and wherein said retrograde implanting is also performed with a mask used for said first masking level.