Patent ID: 6429502
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A semiconductor integrated circuit (IC) device comprising:a) a substrate; b) an insulating layer formed on the substrate; c) additional semiconductor layers formed on the insulating layer; d) a first isolation trench formed in the additional semiconductor layers that extends to the insulating layer and that surrounds a first selected surface area of the additional semiconductor layers, wherein the first isolation trench comprises a plurality of first isolation walls and a plurality of first isolation chambers, wherein the plurality of first isolation chambers comprises conductive material, and wherein the plurality of first isolation walls comprises non-conductive material; e) a second isolation trench formed in the additional semiconductor layers that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench, wherein the second isolation trench comprises a plurality of second isolation walls and a plurality of second isolation chambers, wherein the plurality of second isolation chambers comprises conductive material, and wherein the plurality of second isolation walls comprises non-conductive material; and f) a ground conductor which couples the guard ring region to a ground node.