Patent ID: 6492709
Filing Date: 2002-12-10
Classification: H01C

Abstract:
An arrangement for compensating for temperature dependent variations and process variations in surface resistance of a first resistor (R1) on a chip (1), characterized inthat said first resistor (R1) is connectable between a first terminal (N1) and a second terminal (N2) directly via a normally open first switch (SR1) and indirectly in series with at least one compensating second resistor (R11, R12 . . . R1n) on the chip (1) via a normally open second switch (SR11, SR12 . . . SR1n), that a first comparator (K1) is adapted to compare a reference voltage (VR3), generated by a reference current (I) across a precision resistor (R3) external to the chip (1), with a first voltage (VR2) generated by a current identical to the reference current (I) across a third resistor (R2) on the chip (1), proportional to said first resistor (R1), and generate an output signal to close said normally open first switch (SR1) to connect said first resistor (R1) directly to said second terminal (N2) if the reference voltage (VR3) is lower than said first voltage (VR2), and that at least one second comparator (K11, K12 . . . K1n) is adapted to compare the fixed reference voltage (VR3) with a second voltage generated by said current identical to the reference current (I) across the third resistor (R2) in series with at least one fourth resistor (R21, R22 . . . R2n) on the chip (1), proportional to said at least one compensating second resistor (R11, R12 . . . R1n), and generate an output signal to close said normally open second switch (SR11, SR12 . . . SR1n) to connect said first resistor (R1) in series with said at least one compensating second resistor (R11, R12 . . . R1n) to said second terminal (N2) if the reference voltage (VR3) is lower than the voltage across the third resistor (R2) in series with said at least one fourth resistor (R21, R22 . . . R2n).