Patent ID: 6467020
Filing Date: 2002-10-15
Classification: G06F

Abstract:
A method of processing a plurality of bits stored in a memory, comprising the steps of:(a) providing an associative processor including: (i) a first array of content addressable memory (CAM) cells, said first array including a plurality of columns of said CAM cells, (ii) a second array of said CAM cells that includes at least one column of said CAM cells, and (iii) a plurality of tabs registers; (b) writing a first subplurality of the bits from the memory to a first said column of said CAM cells, each bit of said first subplurality being written to a respective CAM cell of said first column; (c) copying said first subplurality of bits from said first column to a second said column of said CAM cells; (d) writing a second subplurality of the bits from the memory to said first column of said first array, each bit of said second subplurality being written to a respective CAM cell of said first column of said first array; (e) copying said second subplurality of bits from said first column of said first array to one of said at least one column of said CAM cells of said second array; (f) designating a first of said tags registers as a first processing tags register; (g) designating a second of said tags registers as a second processing tags register; (h) executing a first operation on each of at least one of said CAM cells of said first column of said first array with reference to said first processing tags register; and (i) executing a second operation on each of at least one of said CAM cells of said column of said second array with reference to said second processing tags register.