Patent ID: 6391706
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for manufacturing an array of deep trench capacitors for DRAM devices having reduced overetch of deep trenches at a substrate edge and a more uniform pad silicon nitride layer across a substrate comprising the steps of:providing a silicon substrate; forming a hard-mask layer consisting of a pad silicon nitride layer and a first insulating layer, wherein said pad silicon nitride layer is deposited to a thickness sufficient to prevent overetching at edge of said substrate; forming an array of openings in said hard-mask layer to said substrate, and using said hard-mask to etch deep trenches in said substrate; forming trench capacitors in said deep trenches; etching shallow trench openings in said substrate over and between pairs of said trench capacitors in said deep trenches; depositing a conformal insulating liner, and depositing a second insulating layer sufficiently thick to fill said shallow trench openings; polishing back said second insulating layer to form shallow trench isolation in said shallow trench openings; depositing a mask layer; patterning said mask layer to leave blanket portions over center of said substrate while exposing said pad silicon nitride layer on edge of said substrate; partially etching said pad silicon nitride layer on said substrate edge to improve uniformity of said pad silicon nitride layer across said substrate.