Patent ID: 8158515
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method of making 3D integrated circuits, comprising the steps of: (a) forming at least one trench in a first semiconductor wafer; (b) filling the at least one trench with an insulator to form a filled trench; (c) forming devices and back end of the line (BEOL) wiring on a first side of the first semiconductor wafer with at least one pad in the BEOL wiring aligned with the at least one filled trench; (d) joining the first semiconductor wafer to a second semiconductor wafer having at least one landing pad aligned with the at least one filled trench in the first semiconductor wafer; (e) etching the at least one filled trench to remove the insulator; (f) forming an insulative spacer on the walls of the at least one trench; (g) continuing etching the at least one trench until the at least one pad and the at least one landing pad are exposed; and (h) filling the at least one trench with an electrical conductor to simultaneously connect the at least one pad and the at least one landing pad with the electrical conductor.