Patent ID: 8959277
Filing Date: 2015-02-17
Classification: G06F

Abstract:
1. A computing device that facilitates providing precise exception semantics for a virtual machine, wherein the computing device comprises a processor configured to: receive native instructions for a program, wherein the native instructions correspond to a native instruction set architecture (ISA) for a processor and correspond to virtual instructions for a virtual ISA that is different from the native ISA; receive a store instruction in the native instructions that writes a value to a memory; delay writing the value to the memory until after a speculatively-optimized region of the program commits by writing the value to a gated store buffer; determine whether a load instruction in the native instructions that follows the store instruction attempts to access, prior to the speculatively-optimized region committing, a memory address that is aligned with a byte-width of the value, the memory address in a region of the memory accessed by the store instruction; when the load instruction attempts to access a memory address that is not aligned with the byte-width, roll back execution of the program to a preceding point in the program by signaling an exception, wherein, while rolling back the execution, the processor is configured to use a virtual machine to re-execute the speculatively-optimized region by using the virtual machine to execute instructions in the virtual instructions that correspond to native instructions in the speculatively-optimized region; and otherwise, when the load instruction attempts to access a memory address that is aligned with the byte-width, use a bypass mechanism for the gated store buffer to provide the value to the load instruction instead of performing the rolling back.