Patent ID: 7849125
Filing Date: 2010-12-07
Classification: G06F

Abstract:
1. A system for computing A mod(2 n −1), wherein A is an m-bit quantity, wherein m is an integer greater than or equal to two, wherein n is a positive integer less than or equal to m, the system comprising: a plurality of adder circuits, wherein each of the adder circuits is configured to operate on two n-bit operands in order to produce an n-bit output, wherein the plurality of adder circuits are coupled to form a tree structure, wherein the quantity A is partitioned into a plurality of sections, wherein each of the sections includes up to n consecutive bits of the quantity A, wherein each of the sections is supplied to exactly one of the adder circuits in order to determine one of the two n-bit operands of that adder circuit, wherein each of the adder circuits includes: