Patent ID: 6479871
Filing Date: 2002-11-12
Classification: H01L

Abstract:
An ESD protective circuit for an integrated circuit in a semiconductor substrate having a doping of a first doping type, comprising:a â€œlatch-upâ€  protective structure constructed mirror-symmetrically from two lateral bipolar transistors formed by two laterally adjacent regions doped with the first doping type and a central region doped with a second doping type and disposed between said two laterally adjacent regions; said two laterally adjacent regions and said central region being disposed within a well and each being connected to a first pole of a supply voltage via a connection electrode; by two regions doped with the second doping type and respectively disposed laterally adjacent said two laterally adjacent regions outside the well in the semiconductor substrate; and a highly doped zone formed of a plurality of mutually spaced-apart pads with a doping of the second doping type, said pads being disposed to partly overlap said well and to cover a well boundary along a section of a well periphery running between a first region and a second region; said highly doped pads being disposed with an intermediate spacing along two laterally mirror-symmetrically opposite sections of the periphery of the well.