Patent ID: 6677792
Filing Date: 2004-01-13
Classification: H03K,H03L

Abstract:
A digital DLL apparatus for correcting a duty cycle, comprising:a buffer for orderly outputting a first internal clock signal which is activated at an edge of clock by receiving an external clock signal; a delay line unit for receiving the first internal clock signal from the buffer, a first detection signal and a second detection signal and outputting a first delayed internal clock signal and second delayed internal clock signal by delaying the first internal clock signal as much as a predetermined delay amount according to the first and second detection signals; a blend circuit for bypassing the first delayed internal clock signal during the second delayed internal clock signal is not activated and blending the first delayed internal clock signal and the second delayed internal clock signal in order to produce a blended clock signal when the second delayed internal clock signal is activated, wherein the blended clock signal has a phase of a falling edge mediated between falling edges of the first and second delayed internal clock signals; a delay model unit for estimating a delay amount generated during the blended clock signal travels to a data input/output pin (DQ pin) and outputting a compensated clock signal by compensating the blended clock signal based on the estimated delay amount; a direct phase detector for receiving the external clock signal, generating the first detection signal by comparing the external clock signal and the first compensated clock signal and outputting the first detection signal to the delay line unit; and a phase detector for receiving the first delayed internal clock signal and the second delayed internal clocks signal and generating the second detection signal by detecting phases of the first and second delayed internal clock signals.