Patent ID: 6865665
Filing Date: 2005-03-08
Classification: G06F

Abstract:
1. A data processor comprising: an instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing one of a plurality of execution steps associated with a pending instruction being executed by said instruction execution pipeline; a data cache capable of storing data values used by said pending instruction; a plurality of architectural registers capable of receiving said data values from said data cache; bypass circuitry capable of transferring a first data value regardless of a cache miss from said data cache directly to a functional unit in one of said N processing stages without first storing said first data value in a destination one of said plurality of architectural registers; and a cache refill controller capable of detecting that a cache miss has occurred at a first address associated with said first data value, receiving a missed cache line from a main memory coupled to said data processor, and causing a second data value to be transferred from said missed cache line to said functional unit to replace said first data value.