Patent ID: 7202536
Filing Date: 2007-04-10
Classification: H01L

Abstract:
1. A CMOS arrangement of transistors formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said CMOS arrangement comprising a CMOS pair, said CMOS pair comprising a PMOS and an NMOS, said PMOS comprising: a P well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions of said P well underlying said field oxide layer, said relatively deep central portion of said P well underlying a second opening in said field oxide layer; a second gate overlying a channel region of said P well and separated from said substrate by a second gate oxide layer; an N-type source region located at the surface of said substrate on one side of said second gate; and an N-type drain region located at the surface of said substrate on an opposite side of said second gate from said N-type source region; and electrical contacts connected to said second gate, N-type source region, N-type drain region and P well of said NMOS; wherein said P well comprises an implanted P layer, said P layer comprising a deep section in said central portion of said P well, shallow sections in said side portions of said P well, and transition sections connecting said deep sections and said shallow sections of said P layer, each vertical cross-section of said P layer comprising a location of peak doping concentration; said locations of peak doping concentration being relatively deep in said substrate in said deep section of said P layer and being at a shallower level in said substrate in said shallow sections of said P layer, the doping concentration of said P well at said surface of said substrate in said side portions of said P well being higher than the doping concentration of said P well at said surface of said substrate in said central portion of said P well.