Patent ID: 6621444
Filing Date: 2003-09-16
Classification: H03M

Abstract:
A switched capacitor digital-to-analog converter for providing analog output signals corresponding to input digital codes, comprising:an input terminal and at least one output terminal; a first voltage generator for providing first and second reference voltages on first and second reference terminals, respectively; a second voltage generator for providing third and fourth reference voltages on third and fourth reference terminals, said third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, respectively; at least one array of binary weighted capacitors, each capacitor having a first electrode connected to a common circuit node, which is connected to said at least one output terminal, and a second electrode selectively connected through associated first switching means to one of the first and second reference terminals or, through associated second switching means, to one of the third and fourth reference terminals; means for monitoring the values of each bit of the input digital codes, and control means coupled to the first and second switching means associated with each capacitor of the array to open or close selectively during a bit clock period the connections to the first, second, third and fourth terminals according to the following criterion: when the monitoring means detects a bit value of a current input digital code Bj to be equal to the corresponding bit value of a previous input digital code Bjâˆ’1, the first switching means are enabled and the second switching means are disabled during a whole bit clock period, and when the monitoring means detects a bit value of the current input digital code Bj to be different from the corresponding bit value of the previous input digital code Bjâˆ’1, the first switching means are disabled and the second switching means are enabled during a starting time portion of the bit clock period, while the first switching means are enabled and the second switching means are disabled during the remaining portion of the bit clock period.