Patent ID: 6624454
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A semiconductor device, comprising:a support substrate formed of a Si slab; a high-frequency transmission line structure provided on said support substrate, said high-frequency transmission line structure including a ground plane layer, a dielectric layer and a single layer of signal conductor patterns, said signal conductor patterns being provided and exposed at a top surface of the high-frequency transmission line structure; a semiconductor chip mounted on said top surface in a facedown state in electrical contact with said high-frequency transmission line structure, said semiconductor chip thereby having a bottom surface facing said support substrate, said semiconductor chip carrying a coplanar strip line and an air bridge structure on said bottom surface; a solder bump provided on said bottom surface of said semiconductor chip in electrical and mechanical contact with said high-frequency transmission line structure; and a depression formed in said support substrate through said high-frequency transmission line structure and into at least a portion of said support substrate, said depression being formed in correspondence to said semiconductor chip, a space formed between said bottom surface of said semiconductor chip and said signal conductor patterns, said depression having a depth z, as measured from a top surface of said high-frequency transmission line structure, determined so as to satisfy a relationship z&gE;yâˆ’(x+d), wherein y represents the height of said air bridge structure, x represents the height of said solder bump, and d represents the thickness of said coplanar strip line.