Patent ID: 8000429
Filing Date: 2011-08-16
Classification: H04L

Abstract:
1. A jitter correction method comprising: a first step of generating per clock cycle, combination data combined by adding, to referenced data within input data oversampled, an end bit of data one clock prior to and a head bit of data one clock subsequent to the referenced data and outputting the referenced data and the combination data; a second step of detecting a change between each bit referred to as a referenced bit of the combination data and a bit directly adjoining the referenced bit using a change bit monitoring circuit, initializing a number of reference times when the change is detected, incrementing the number of reference times when the change is not detected while the number of reference times does not reach a multiplication number of the oversampling, and generating change position display data in which the bit directly adjoining the referenced bit is regarded as a change bit of the referenced data when the number of reference times reaches the multiplication number of the oversampling and when no change between at least three adjoining bits including the referenced bit is detected; and a third step of extracting all the change bits from the referenced data by referring to the change position display data, and performing a data reproduction of the extracted change bits corresponding to the multiplication number, wherein the third step includes a step of storing the extracted change bits in a buffer per clock cycle, and reading per clock cycle, from the buffer the change bits stored by a bit number required for the data reproduction.