Patent ID: 6377634
Filing Date: 2002-04-23
Classification: H04L

Abstract:
A circuit for reproducing bit timing, comprising:(a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase; (b) a second analog-digital converter for converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal; (c) a first detector for receiving said real part digital signal and said imaginary part digital signal, detecting a phase angle of said complex modulation in signal on a complex plane, and transmitting a first signal indicative of said phase angle; (d) a delay circuit for delaying said first signal by a symbol interval; (e) a second detector for detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval; (f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase, detected by said second detector, and transmitting a second signal indicative of said timing gap; and (g) a signal converter for converting each of said real part digital signal and said imaginary part digital signal into a signal associated with said optimum sampling point, based on said second signal.