Patent ID: 6093603
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of fabricating a semiconductor memory device in which respective semiconductor memory elements are arranged in a matrix, characterized by each semiconductor memory element having a floating-gate formed through a first insulating film on a semiconductor substrate, a line-shaped control gate which covers said floating-gate through a second insulating film, a line-shaped select gate arranged perpendicularly to said control gate and extending on top and side surfaces of a laminated stacked gate structure including said floating-gate and said control gate through an insulating film and extending on a part of the substrate through the first insulating film on the substrate, and line-shaped source and drain regions arranged alternately and in parallel with said control gate, one of the source region and the drain region being arranged offset to said control gate or said stacked gate structure (hereinafter, the offset portion is referred to as a selection transistor) so as to allow a matrix selection for respective semiconductor memory element regions by use of the control gate and the select gate, said method comprising steps of:forming LOCOSs in forms of stripes in parallel with a direction in which a select gate is formed, the LOCOSs for separating respective semiconductor memory elements;forming said stacked gate structures each including the floating-gate and the control gate perpendicularly to the LOCOSs;forming stripe-shaped resist layers in parallel with the control gate so as to cover portions to be selection transistors and a selection transistor side of said stacked gate structures;etching the LOCOSs by using said resist layers and said stacked gate structures as masks;forming impurity diffusion layers to be source lines and drain lines by using said resist layers and said stacked gate structures as masks; andforming select gates.