Patent ID: 7532053
Filing Date: 2009-05-12
Classification: H03H,H03K,H03L

Abstract:
1. A phase interpolator circuit comprising: a multiplexer circuit (MUX) to receive a plurality of clock signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other; a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents is a substantially constant current value, wherein the first clock signal is to be weighted according to the first DAC output current and the second clock signal is to be weighted according to the second DAC output current; and a weighted averager circuit coupled to the MUX and the DAC, wherein the weighted averager circuit is to sum weighted first and second clock signals to output a phase interpolated clock signal.