Patent ID: 7698611
Filing Date: 2010-04-13
Classification: G01R,H03K

Abstract:
1. A control circuit, comprising: a first latch having first, second, third and fourth inputs and first and second outputs; a second latch having first, second, third and fourth inputs and first and second outputs; a third latch having first, second and third inputs and an output; combinational logic having a test signal input, a test clock input, a functional clock signal input, a first control signal output and a second control signal output; said first output of said first latch connected to said first input of said second latch, said first output of said second latch connected to said first input of said third latch, said second output of said second latch connected to said first input of said first latch, and said output of said third latch connected to said third inputs of said first latch and second latches; said combinational logic connected to said first, second and fourth inputs and said second output of said first latch, to said second and fourth inputs and said second output of said second latch and to said second and third inputs of said third latch; wherein said combinational logic couples said second output of said first latch to said second control signal output, couples said second output of said second latch to said first control signal output, couples said second input of said first latch, said second input of said second latch and said second input of said third latch to said functional clock signal input, and couples said fourth input of said first latch, said fourth input of said second latch and said third input of said third latch to said test signal input; and wherein said combinational logic couples said test clock input, said test signal input and said second output of said first latch to said second control signal output, and couples said test clock input and said second out put of said second latch to said first control signal output.