Patent ID: 6226764
Filing Date: 2001-05-01
Classification: G11C

Abstract:
An integrated circuit memory device comprising:a memory cell array in the integrated circuit memory device; anda stress voltage generator in the integrated circuit memory device that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during stress built-in self test of the memory cell array;wherein the stress voltage generator is responsive to a built-in self test request signal and to a stress test signal that are applied from external of the integrated circuit memory device, to apply the stress voltage to the memory cell array and to perform a built-in self test of the memory cell array, and is responsive to the built-in test request signal and absence of the stress test signal, to apply the internal supply voltage to the memory cell array and to perform the built-in self test of the memory cell array.