Patent ID: 6108233
Filing Date: 2000-08-22
Classification: G11C

Abstract:
An integrated circuit having a memory cell for storing a data bit corresponding to one of a low and a high voltage, comprising:(a) a memory element coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit;(b) a single-ended, bidirectional access port comprising only one access switch having a first terminal coupled to a data line, a second terminal coupled to the data node, and a control terminal coupled to an access control line which provides an access control signal for switching the access switch on or off to selectively couple the data line to the data node to either write a write-data bit to the memory cell in a write phase, or to read a read-data bit from the memory cell, in a read phase; and(c) a preset switch having a first terminal coupled to one of the data node and the inverse data node, a second terminal coupled to one of a logic-1 voltage source and a logic-0 voltage source, respectively, and a preset control terminal coupled to a preset control line which provides a write preset control signal that switches the preset switch on to couple the first terminal of the preset switch to the second terminal of the preset switch, before each write of a write-data bit to the memory cell via the access port, to precharge the data node to the high voltage before writing the write-data bit to the memory cell.