Patent ID: 6281557
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A read-only memory cell array, comprising:a semiconductor substrate;a cell matrix formed in said semiconductor substrate, said cell matrix having a plurality of strip-shaped trenches running essentially parallel with each other, said trenches having trench walls, said cell matrix including a first type of memory cells each having a MOS transistor disposed vertically with respect to said semiconductor substrate, and a second type of memory cells without any vertical MOS transistors, said first type and said second type of memory cells disposed on predetermined sections of said trench walls;a gate dielectric and a gate electrode covering said trench walls in a region of said first type of memory cells, said MOS transistor disposed on said trench walls;a first insulation material covering said trench walls in a region of said second type of memory cells;a second insulation material and said gate dielectric disposed in said trenches between an adjacent two of said memory cells located along one of said trench walls, at least one of said adjacent two memory cells being of first type of memory cells; andword lines running transversely with respect to said trenches and connected to said gate electrode respectively lying under said word lines.