Patent ID: 7181714
Filing Date: 2007-02-20
Classification: G06F

Abstract:
1. A scheduler for partitioning behavioral operations of a logic circuit under design into groups executed in each clock cycle, the behavioral operations with a hierarchical structure being described in behavioral descriptions, the scheduler comprising: a schedule information acquisition section configured to acquire a number of first clock cycles and a number of second clock cycles as schedule information of a function belonging to a lower-hierarchy described in the behavioral descriptions, the number of the first clock cycles being the number of clock cycles after an execution of the function is started until an input data of the function is used in the function, the number of the second clock cycles being the number of clock cycles after an output data of the function is outputted until the execution of the function is completed; and a scheduling processing section configured to obtain operations executable within a range of the first clock cycles and operations executable within a range of the second clock cycles from among operations belonging to an upper-hierarchy for calling the function, based on the acquired schedule information of the lower-hierarchy, the scheduling processing section further configured to schedule the upper-hierarchy in order that the obtained operations belonging to the upper-hierarchy execute in parallel with the function belonging to the lower-hierarchy within the range of the first clock cycles and the second clock cycles while maintaining the hierarchical structure of the behavioral descriptions.