Patent ID: 7902645
Filing Date: 2011-03-08
Classification: G09G,H01L

Abstract:
1. A semiconductor device having a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal, wherein the semiconductor element comprises: a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage; a plurality of electrodes for the reference voltage formed in a neighborhood of the grayscale voltage generating unit; an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes; a plurality of first electrodes formed along a first edge of the semiconductor element; a plurality of second electrodes formed along an edge of the semiconductor element opposite to the first edge; a plurality of third electrodes formed in a neighborhood of a functional block; and an internal wiring for connecting the first electrodes and the third electrodes, and wherein the substrate comprises a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes; a first wiring pattern for connecting the external input terminal and the first electrodes; a second wiring pattern for connecting the external output terminal and the second electrodes; and a third wiring pattern for connecting the first electrodes and the third electrodes, wherein the semiconductor element further comprises a signal input electrode formed in a neighborhood of the first electrodes and along the first edge, and the substrate further comprises an input signal wiring pattern for connecting the signal input electrode and the external input terminal, wherein the first wiring pattern and the input signal wiring pattern are disposed in a line, the input signal wiring pattern is disposed at an outer side of the first wiring pattern, the signal input electrode is disposed closer to a central part of the first edge than the first electrodes, the input signal wiring pattern connects to the signal input electrode via an outer side of the first electrodes as viewed from the first edge, and the third wiring pattern detours around the input signal wiring pattern and is connected to the third electrodes.