Patent ID: 9171590
Filing Date: 2015-10-27
Classification: G11C

Abstract:
1. A sensing margin expanding scheme for a memory, comprising: a sense amplifier, having a first input terminal, a second input terminal and an output terminal; a first capacitor, a first terminal of the first capacitor coupled to at least a bit line of the memory, a second terminal of the first capacitor coupled to a pre-sense amplifier; a second capacitor, a first terminal of the second capacitor coupled to a reference voltage, a second terminal of the second capacitor coupled to the pre-sense amplifier; a first common switch, coupled to the second terminal of the first capacitor and the first terminal of the second capacitor; a second common switch, coupled to the first terminal of the first capacitor and the second terminal of the second capacitor; and a controller, coupled to the first common switch, the second common switch and the pre-sense amplifier; wherein, in a first phase, the controller controls the first common switch to short the second terminal of the first capacitor and the first terminal of the second capacitor and controls the second common switch to short the first terminal of the first capacitor and the second terminal of the second capacitor; wherein, in a second phase, the controller controls the first common switch to open the second terminal of the first capacitor and the first terminal of the second capacitor, and controls the second common switch to open the first terminal of the first capacitor and the second terminal of the second capacitor, and then controls the pre-sense amplifier to couple the second terminal of the first capacitor and the second terminal of the second capacitor to a common voltage.