Patent ID: 6074912
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method for forming different area vias of dynamic random access memory, said method comprise:forming a plurality of cell gates in a cell region and a plurality of periphery circuit gates in a periphery circuit region, each said gates is formed on a substrate and comprises a conductive layer, a polycide layer and a passivation layer in sequence;forming a first dielectric layer over said substrate and covering said cell gates and said periphery circuit gates;forming a second dielectric layer over said first dielectric layer;etching back part said second dielectric layer and forming spacers in sidewalls of said periphery circuit gates;forming a third dielectric layer over said substrate and covering said cell gates and said periphery circuit gates;forming a photoresist layer on said third dielectric layer, said photoresist layer defines vias regions in said cell region and said periphery circuit region;etching part of said third dielectric layer, said part of said third dielectric layer is uncovered by said photoresist layer;etching part of said first dielectric layer and part of said passivation layer of periphery circuit gates, where said part of said third dielectric layer and part of said passivation layer are uncovered by said photoresist layer; andremoving excess said photoresist layer and then said vias are formed.