Patent ID: 6157055
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A semiconductor memory device comprising:a plurality of active regions formed on a semiconductor substrate;a metal oxide semiconductor transistor formed on said plurality of active regions;a separation insulating film formed between adjacent ones of said plurality of active regions for electrically separating the same from each other;a lower electrode of a storage capacitor, said lower electrode being electrically connected to one of a pair of diffused layers of said metal oxide semiconductor transistor formed in a surface region of said plurality of active regions and having a conductor type reverse to that of said semiconductor substrate, said lower electrode extending over to one of said plurality of active regions and said separation insulating film;a dielectric film and an upper electrode of said storage capacitor, said dielectric film and said upper electrode being stacked on said lower electrode; anda conductive film arranged in a rim portion in said separation insulating film in a manner opposed to said semiconductor substrate with an insulating film in between;wherein the lower end portion of said lower electrode is electrically connected to the upper end portion of said conductive film.