Patent ID: 8501581
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. A method of forming a semiconductor construction, comprising: providing a substrate comprising first semiconductor material over an electrically insulative mass, the first semiconductor material having a thickness; providing a patterned mask over the first semiconductor material, the mask comprising a layer of silicon nitride over a layer of silicon dioxide; forming a plurality of first trenches extending into the first semiconductor material, but not entirely through the thickness of the first semiconductor material; the first trenches being U-shaped and extending primarily linearly along defined latitudinal directions; forming one or more second trenches which extend entirely through the first semiconductor material and into the insulative mass; the forming of the second trenches leaving a plurality of spaced regions of the first semiconductor material extending along and under the first trenches; the individual spaced regions of first semiconductor material being trough-shaped with sidewalls of the troughs being along opposing sides of the first trenches, and bottoms of the troughs being under the first trenches; overfilling the second trenches with electrically insulative material; planarizing the electrically insulative material by polishing utilizing the layer of silicon nitride as a stop during the polishing; after filling the second trenches, forming a plurality of third trenches entirely through the first semiconductor material and into the insulative mass extending primarily linearly along longitudinal directions substantially orthogonal to the latitudinal directions, the third trenches extending across the trough-shaped regions of the first semiconductor material and across the electrically insulative material, and thus having peripheries comprising insulative material regions and first semiconductor material regions; the third trenches dividing the trough-shaped first semiconductor material into trough-shaped slices; lining the first semiconductor material regions of the third trench peripheries with dielectric material; after the lining, forming conductive material within the third trenches; removing the patterned mask and replacing the mask with a second semiconductor material, the second semiconductor material being the same composition as the first semiconductor material; conductively doping the second semiconductor material to form source regions and drain regions; conductively doping at least portions of the sidewalls of the trough-shaped regions of the first semiconductor material; and wherein the conductive material within the third trenches forms a plurality of front-gate/back-gate pairs, with each pair sandwiching a single of the trough-shaped slices therebetween; each sandwich of a front-gate/trough-shaped first semiconductor material slice/back-gate being a floating body transistor unit cell.