Patent ID: 9064579
Filing Date: 2015-06-23
Classification: G06F,G11C

Abstract:
1. A semiconductor memory apparatus comprising: a non-volatile semiconductor memory which includes a plurality of blocks having an upper limit in the number of rewrite times; a time measurement unit which measures a total operation time counted from a start time of a guaranteed period; a first capacity measurement unit which measures a first capacity which is an actual value of an accumulated amount of data written in the non-volatile semiconductor memory; a second capacity calculation unit which calculates a second capacity which is an accumulated amount of data which is writable in the non-volatile semiconductor memory in a remaining time interval of the guaranteed period based on the number of remaining rewritable times of existing blocks among the plurality of the blocks; and a speed control unit which calculates a time-varying behavior of a permissible value of the accumulated amount of data written in the non-volatile semiconductor memory, where, after the start of the guaranteed period, data is written in the non-volatile semiconductor memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of the first capacity and the second capacity, and which controls a transmission speed of transmission data from outside so that the first capacity does not exceed the permissible value at the timing of measuring the first capacity.