Patent ID: 6782492
Filing Date: 2004-08-24
Classification: G06F

Abstract:
A memory error processing method in a cluster computer comprising:a plurality of nodes that each includes a memory having an error correction function and at least one processor connected together by an interconnection network, and each node comprising a proper area and a common communication area, which are set on a memory of each node, and the common communication area of each node is logically common to the common communication areas of said plurality of nodes, the memory error processing method comprising: each node sending the memory access origin a system error stop notification, in the case of accessing a proper memory of the same node when an irrecoverable error has occurred in said memory of the same node; and each node sending the memory access origin a common communication area error notification through the intercommunication network to the common communication area of the memory installed in another node, when an irrecoverable error has occurred in said memory area of another node.