Patent ID: 8952733
Filing Date: 2015-02-10
Classification: H03B

Abstract:
1. A frequency multiplier circuit, comprising a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to said first signal input terminal, said second signal input terminal, said power source terminal and said ground terminal, a reference circuit which is connected to said power source terminal and said ground terminal, and a frequency synthesis circuit which is connected to said main control circuit, said reference circuit, said output terminal, said power source terminal and said ground terminal; wherein said main control circuit comprises a first FET connected to said first signal input terminal, a second FET connected to said second signal input terminal, a third FET which is connected to said first FET and said second FET, a fourth FET which is connected to said first FET, said third FET and said power source terminal, and a fifth FET which is connected to said second FET, said third FET, said fourth FET and said power source terminal; said reference circuit comprises a sixth FET connected to said ground terminal, a seventh FET connected to said sixth FET, an eighth FET which is connected to said sixth FET, said seventh FET and said power source terminal; and said frequency synthesis circuit comprises a comparator which is connected to said third FET, said fourth FET, said fifth FET, said sixth FET, said seventh FET, said eighth FET and said output terminal.