Patent ID: 6266799
Filing Date: 2001-07-24
Classification: H03L,H04L

Abstract:
A method for implementing a data/clock recovery system in a network device receiver, the network device receiver being configured to receive a serial data stream, comprising:producing a plurality of clock phases for every two bits of the serial data stream;selecting four clock phases from the plurality of clock phases, the four clock phases having a predetermined separation;analyzing the serial data stream that corresponds to the selected four clock phases to determine whether a new four clock phases should be selected from the plurality of clock phases; andselecting the new four clock phases when the analyzing indicates that the selected four clock phases and the serial data stream are not synchronized, the new four clock phases are selected to prevent the selected four clock phases from leading or lagging the serial data stream.wherein the serial data stream is continually analyzed for each of the every two bits of the serial data stream and the new four clock phases are only selected when the analyzing indicates that the selected four clock phases and the serial data stream are not synchronized.