Patent ID: 6797608
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A method of preventing copper diffusion in the fabrication of an integrated circuit by means of a composite diffusion barrier layer, and forming conducting inlaid copper, the method comprising the following steps:(a) providing a substrate or wafer having an insulator layer deposited upon said substrate; (b) providing a first level of conducting wiring over said insulator layer; (c) depositing a first and second dielectric layer over said first level of conducting wiring; (d) patterning and etching the dielectric layers forming dual damascene trench/via openings; (e) depositing a WN first barrier layer over said dielectric layers covering and lining said trench/via; (f) soaking said WN first barrier layer in a reactive silane gas mixture forming a WSiN layer on the WN; (g) depositing a W barrier layer over the WN first barrier layer and on the WSiN layer, forming over dual damascene trench/via openings, by the above process steps (a) to (g), a composite diffusion barrier layer comprised of W/WSiN/WN, with a WN first barrier layer, followed by a WSiN layer on the WN first barrier layer, and then followed by a W barrier layer on the WSiN layer; (h) depositing by electrochemical deposition a copper seed layer over the diffusion barrier layer; (i) depositing by electrochemical deposition a copper conducting material on the copper seed layer forming an excess of copper, and removing the excess material, thus forming conducting inlaid copper.