Patent ID: 6603688
Filing Date: 2003-08-05
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory mats arranged in a direction of bit-line which including bit lines, word lines and memory cells coupled to said bit lines and said word lines; a MOSFET included in each of said memory cells and having a capacitance having first and second electrodes, a gate coupled to a corresponding one of said word lines and source-and-drain paths one of which is coupled to a corresponding one of said bit lines and the other is coupled to said first electrode of said capacitance; and a amplifier circuit provided in a region between said memory mats arranged in a direction of said bit line and having unit-amplifier circuits connected to bit line pairs separately provided to two of said memory mats, wherein the number of said unit-amplifier circuits being less than the number of said bit line pairs; and wherein a failed bit line of said bit line pairs can be replaced, on a unit-amplifier basis, with a redundant bit line pair and a corresponding unit-amplifier circuit.