Patent ID: 6539508
Filing Date: 2003-03-25
Classification: G01R

Abstract:
A circuit for testing a plurality of uniquely addressed memory elements in a random-access memory (RAM), the circuit comprising:a. a circuit clock terminal; b. a first counter having: i. a first counter input terminal connected to the circuit clock terminal; and ii. a first plurality of counter output terminals; c. a first linear-feedback shift register including the RAM and having: i. a first RAM clock terminal connected to the circuit clock terminal; ii. a plurality of address terminals connected to respective ones of the first plurality of counter output terminals; iii. a data input terminal adapted to receive data to be stored in an addressed one of the memory elements; and iv. a RAM output terminal adapted to provide data stored in the addressed memory element; and d. a comparator having a first comparator input terminal connected to the RAM output terminal, a second comparator input terminal adapted to receive a reference number, and a comparator output terminal.