Patent ID: 8547775
Filing Date: 2013-10-01
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of chips stacked with one another, each of the semiconductor chips including a first storage circuit storing an individual chip address allocated thereto and a second storage circuit, each of the semiconductor chips being configured to receive a row command accompanying a first layer address and to receive a column command accompanying a second layer address, the individual chip address comprising first and second parts, wherein each of the semiconductor chips is configured to execute the row command when the first part of the individual chip address is coincident with the first layer address accompanied by the row command, to store hit information into the second storage circuit in response to execution of the row command, and to execute the column command when the second storage circuit maintains the hit information and the second part of the individual chip address is coincident with the second layer address accompanied by the column command.