Patent ID: 6292871
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A cache memory system for facilitating access by a processor to lines of data stored in a memory, the system comprising:a cache for storing lines of data for access by the processor;a prefetch store for storing lines of data to be transferred to the cache; anda memory controller for receiving processor requests for access to lines of data and retrieving lines of data from the memory, the memory controller maintaining priority data indicative of the relative priority of lines of data stored in the cache;wherein the memory controller is configured to respond to receipt of a processor request for access to data in a line N such that:in the case of a cache hit, the memory controller controls supply of that data from the cache to the processor;in the case of a cache miss when line N is not stored in the prefetch store, the memory controller retrieves line N from the memory, and controls storage of the line in the cache and supply of the data to the processor, the priority data for line N being set to a high relative priority;in the case of a cache miss when line N is stored in the prefetch store, the memory controller transfers line N from the prefetch store to the cache and controls supply of the data to the processor, the priority data for line N being set to a low relative priority, andfor both a cache hit and a cache miss, the memory controller prefetches the sequentially next line N+1 from the memory to the prefetch store.