Patent ID: 7151684
Filing Date: 2006-12-19
Classification: G11C,H01L

Abstract:
1. A semiconductor memory comprising: a plurality of bit lines, a plurality of word line groups orthogonal to the plurality of bit lines, and a plurality of source lines that are respectively arranged adjacent and parallel to the word line groups; a pair of bit line side select gate lines formed between a pair of word line groups of the plurality of word line groups, and aligned parallel to the word line groups; a pair of source line side select gate lines formed between a word line group adjacent to the pair of word line groups and the pair of word line groups, and aligned parallel to the word line groups; memory cell transistors arranged at an intersections of the bit lines and the word lines, and select gate transistors arranged at an intersections of the bit lines and the select gate lines; a bit line contact arranged between the pair of bit line side select gate lines; and a source line contact arranged between the pair of source line side select gate lines, wherein in a periodic symmetrical pattern with the center line between the pair of bit line side select gate lines as a first line of symmetry and the center line between the pair of source line side select gate lines as a second line of symmetry, an interval between the pair of bit line side select gate lines is greater than an interval between the pair of source line side select gate lines.