Patent ID: 6059836
Filing Date: 2000-05-09
Classification: G06F

Abstract:
An apparatus for simulating a logic circuit according to simulated clock cycles initiated by clock signals, said apparatus comprising:a first plurality of logic block circuits for simulating portions of said logic circuit upon receipt of a clock signal for a simulated clock cycle, said logic block circuits further having a predetermined number of signal inputs and outputs;at least one routing block for routing signals between said logic block circuits between said simulated clock cycles; andeach of said logic block circuits further including:a first series of output scan chain units for capturing and storing each of the signal outputs of a corresponding said logic block circuit at an end of said simulated clock cycle; and a second series of input scan chain units for storing and inputting a signal for each of said logic block units at a beginning of said simulated clock cycle;each of said scan chain units being further interconnected to said routing logic block for storing of said input signals and said output signals to and from said routing; logic block between said simulated clock cycles.