Patent ID: 6420232
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method for simultaneously fabricating scalable split-gate flash memory devices having a sidewall erase cathode and peripheral CMOS devices comprising:providing a semiconductor substrate with isolations; forming a multilayer structure of a first thermal silicon-oxide layer, a first polycrystalline-silicon layer, a first dielectric layer and a first masking silicon-nitride layer; patterning said multilayer structure using a first masking photoresist by selectively removing said first masking silicon-nitride layer, said first dielectric layer and said first polycrystalline-silicon layer, wherein said patterning is used to define the virtual gate length of flash memory devices and said virtual gate length includes two floating-gate lengths and one common source width of a scalable split-gate flash memory device; oxidizing said patterned multilayer structure to form a first poly-oxide layer on the etched sidewalls of said first polycrystalline-silicon layer and a thicker second thermal silicon-oxide layer over said semiconductor substrate outside said patterned multilayer structure, wherein said first poly-oxide layer is used as the tunneling-oxide layer for erasing the stored charges from said first polycrystalline-silicon layer to the control gate and said thicker second thermal silicon-oxide layer is used as the gate insulator of the control-gate device in said scalable split-gate flash memory device and the gate insulator of said peripheral CMOS devices in peripheral integrated circuits; implanting doping impurities through said thicker second thermal silicon-oxide layer into said semiconductor substrate to adjust the threshold voltage and the punch-through voltage of said peripheral CMOS devices and the control-gate device in said scalable split-gate flash memory device, wherein two different channel types use a second and a third masking photoresists; depositing a first conformable polycrystalline-silicon layer followed by anisotropically etching said first conformable polycrystalline-silicon layer to form a first polycrystalline-silicon spacer on the sidewalls of said oxidized and patterned multilayer structure, wherein the width of said first polycrystalline-silicon spacer is mainly controlled by the thickness of said first conformable polycrystalline-silicon layer; removing said first masking silicon-nitride layer using a wet-chemical solution of hot phosphoric acid; depositing a second conformable polycrystalline-silicon layer followed by depositing a second masking silicon-nitride layer and then implanting phosphorous impurities into said second conformable polycrystalline-silicon layer, wherein the dose of said implant is between about 1015 to 5Ã—1015 Atoms/cm2; defining the gate lengths of said peripheral CMOS devices using a fourth masking photoresist followed by etching said second masking silicon-nitride layer and anisotropically etching said second conformable polycrystalline-silicon layer to form first polycrystalline-silicon gates for said peripheral CMOS devices and second polycrystalline-silicon spacers on both sides of said first polycrystalline-silicon spacer; implanting boron impurities through said second thermal silicon-oxide layer into said semiconductor substrate in n-wells in a self-aligned manner to form lightly-doped source and drain diffusion regions of p-channel MOS devices using a fifth masking photoresist, wherein the dose of implant is between about 1013 to 1014 Atoms/cm2; oxidizing said second polycrystalline-silicon spacers and the sidewalls of said first polycrystalline-gates in a dry oxygen or steam ambient to form second thermal poly-oxide layers having a thickness of between about 200 to 300 Angstroms; etching said first dielectric layer and said first polycrystalline-silicon layer in a self-aligned manner to form common source diffusion windows of said scalable split-gate flash memory devices by using a non-critical sixth masking photoresist to protect the non-etching area; implanting phosphorous impurities through said second thermal silicon-oxide layer and said first thermal silicon-oxide layer into said semiconductor substrate in p-wells in a self-aligned manner to form lightly-doped source and drain diffusion regions of n-channel MOS devices, lightly-doped source and drain diffusion regions of said scalable split-gate flash memory devices by using a seventh masking photoresist, wherein the dose of the implant is between about 1013 to 1014 Atoms/cm2; removing said second masking silicon-nitride layer on said first polycrystalline-silicon gates of said peripheral CMOS devices using dry etch followed by oxidizing said first polycrystalline-silicon gates and the sidewalls of said etched first polycrystalline-silicon layer to form third thermal poly-oxide layers; depositing a first conformable silicon-nitride layer followed by anisotropically etching said first conformable silicon-nitride layer to form first silicon-nitride spacers on the sidewalls of said scalable split-gate flash memory devices and the sidewalls of said peripheral CMOS devices; implanting boron impurities across said second thermal silicon-oxide layer into said semiconductor substrate in said n-wells to form heavily-doped source and drain diffusion regions of said p-channel MOS devices using a eighth masking photoresist, wherein the dose of implant is between about 1015 to 5Ã—1015 Atoms/cm2; removing the field oxide of isolation and said first thermal silicon-oxide layer over the lightly-doped source diffusion regions of said scalable split-gate flash memory array using a non-critical ninth masking photoresist to form common buried source windows in a self-aligned manner using buffered hydrofluoric acid followed by oxidizing the exposed semiconductor surface to form a third thermal silicon-oxide layer having a thickness of approximately 100 Angstroms; implanting arsenic impurities across said second and third thermal silicon-oxide layers into the semiconductor regions in said p-wells in a self-aligned manner to form heavily-doped source and drain diffusion regions of said n-channel MOS devices and heavily-doped drain and common-buried source diffusion regions of said scalable split-gate flash memory array using a tenth masking photoresist; performing a thermal annealing to activate implanted doping impurities and to eliminate implant-induced defects; removing said second and third thermal silicon-oxide layers over said heavily-doped source and drain diffusion regions of all devices, said third poly-oxide layers over said first polycrystalline-silicon gates of said peripheral CMOS devices, and said second poly-oxide over said second polycrystalline-silicon spacers of said scalable split-gate flash memory devices using dilute hydrofluoric acid or buffered hydrofluoric acid or anisotropic dry etch; sputtering a titanium metal layer over all the structure surface followed by annealing in a nitrogen ambient to form a titanium-disilicide layer over exposed monocrystalline and polycrystalline silicon regions and a first titanium-nitride layer over all the structure surface; patterning the contact regions for inter-metal interconnect using an eleventh masking photoresist by selectively etching said first titanium-nitride layers using a NH4OH:H2O2:H2O (1:1:5) solution followed by heating in an argon ambient to reduce the resistivities of said first titanium-nitride layer and said titanium-disilicide layer; depositing a thick dielectric layer using low-temperature CVD system followed by chemical-mechanical polishing to planarize all the structure surface, wherein said thick dielectric layer is made of CVD silicon-oxide or borophosphosilicate glass; patterning said thick dielectric layer using a twelfth masking photoresist to form contact holes followed by reflowing said contact holes to round up the corners; depositing a second titanium-nitride layer known as the barrier metal and a tungsten layer known as the plug metal followed by chemical-mechanical-polishing to planarize the whole structure surface by removing said second titanium-nitride and said tungsten layer on the flat surface of said thick dielectric layer; depositing a M1 metal layer followed by patterning said M1 metal layer using a thirteenth masking photoresist to form a M1 metal interconnect known as a first-level M1 metal interconnect; depositing a first intermediate dielectric layer over said first-level M1 metal interconnect followed by CMP, first via patterning using a fourteenth masking photoresist and etching, the barrier metal deposition and the plug metal deposition, CMP, a M2 metal layer deposition and patterning using a fifteenth masking photoresist to form a second-level M2 metal interconnect; repeating the above processes to form an N-level MN metal interconnect, wherein said N-level MN metal can be aluminum, aluminum alloy or copper; said intermediate dielectric layer can be a CVD oxide layer or low dielectric-constant dielectric layer; said titanium metal can be replaced by cobalt or tantalum or molybdenum etc.; said tungsten plug can be replaced by aluminum; depositing a thick passivation layer followed by patterning said thick passivation layer using a sixteenth masking photoresist to open the bonding pads, wherein said thick passivation layer is made of phosphorous-doped glass and/or silicon-nitride layer.