Patent ID: 7251162
Filing Date: 2007-07-31
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a memory cell array having a plurality of nonvolatile memory cells; and a voltage generator for generating an operation voltage to be supplied to one of said nonvolatile memory cells for storing data to said one nonvolatile memory cell, wherein said voltage generator comprises: a clock signal controller for generating a first clock signal and a second clock signal having a frequency higher than that of said first clock signal and selecting and outputting one of said first and second clock signals; and a charge pump circuit for boosting a voltage by pumping operation using either said first clock signal or said second clock signal output from said clock signal controller, thereby generating said operation voltage, wherein said clock signal controller outputs said first clock signal and then said second clock signal to said charge pump circuit, and wherein when the operation voltage level is between a first voltage level and a second voltage level, said charge pump circuit uses said first clock signal, and after that, when the operation voltage level is between said second voltage level and a third voltage level, said charge pump circuit uses said second clock signal, and wherein said voltage generator controls so that a first boost ratio of said operation voltage generated using said first clock signal is lower than a second boost ratio of said operation voltage generated using said second clock signal.