Patent ID: 6556060
Filing Date: 2003-04-29
Classification: H03K

Abstract:
In a latch that transitions from an acquire mode to a latch mode in response to a latch command signal and has cross-coupled first and second isolation transistors that have first and second current terminals with said first current terminals coupled to receive a differential input signal, cross-coupled first and second latch transistors that provide collectors, and first and second current-limiting transistors that are each coupled between a respective one of said second current terminals and a respective one of said collectors and that each provide an impedance that transitions from an acquire impedance to a greater latch impedance in response to a respective one of control signals Scntrl; the improvement comprising:at least one switch coupled to provide currents to said first current terminals in response to said latch command signal; and a controller that responds to complementary metal-oxide-semiconductor (CMOS) signals and is coupled to receive CMOS-level sense signals Ssns from at least one of said second current terminals and, in response, provide at least one of said control signals Scntrl.