Patent ID: 9093989
Filing Date: 2015-07-28
Classification: H03K

Abstract:
1. A clock signal generator module arranged to generate at least one clock signal for a plurality of functional modules of an integrated circuit, the clock signal generator module comprising: a first clock source component and at least one further clock source component, each associated with at least one associated functional module out of said functional modules, and arranged to generate a respective clock signal for said associated functional module; and at least one management unit arranged to controllably enable signal generation by the first and at least one further clock source components in accordance with at least one operating characteristic of the at least one associated functional module associated with the respective clock source, said characteristic being related to an ageing of a behaviour of the at least one associated functional module, the at least one management unit to cause the performance of the first clock source component and the performance of the at least one further clock source component to reduce at substantially the same rate as that of the respect associated functional module.