Patent ID: 6165692
Filing Date: 2000-12-26
Classification: G03F

Abstract:
A method for manufacturing a semiconductor device comprising the steps of:preparing an exposure mask in which repeat pattern portions having shifter portions and non-shifter portions alternately and repeatedly arranged and non-repeat pattern portions having irregularly arranged patterns are separately formed in a plurality of regions of one exposure mask, light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions;preparing a semiconductor wafer having a plurality of chip areas;aligning a pattern on one of the plurality of regions of the exposure mask with each of the plurality of chip areas on the semiconductor wafer;effecting an exposing process in an illuminating condition corresponding to the pattern on the one region, each time after aligning the pattern with each of the plurality of chip areas;aligning a pattern on a different one of the plurality of regions on the exposure mask with each of the plurality of chip areas on the semiconductor wafer; andeffecting an exposing process in another illuminating condition corresponding to the pattern on the different one region, each time after aligning the pattern with each of the plurality of chip areas,wherein the step of effecting an exposing process corresponding to the pattern on the different one of the plurality of regions on the exposure mask is repeatedly effected until the exposing process for all of the plurality of regions of the exposure mask is completed.