Patent ID: 9158500
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A data processing device comprising: a single pseudo random number generator including a series connection of plural shift registers; a polynomial coefficient controller configured to generate a memory parameter MP referring to data stored in a table and transmit the memory parameter MP for determining a feedback polynomial of the single pseudo random number generator to the single pseudo random number generator; a selector configured to receive an output from each of the plural shift registers, and to select an output from one of the plural shift registers excluding a last shift register of the series connection as a pseudo random number sequence; and a conversion circuit which receives the pseudo random number sequence from the selector, and which converts first data to second data using the received pseudo random number sequence, wherein the selector is configured to select the output from the one of the plural shift registers responsive to the memory parameter MP, and wherein the memory parameter MP comprises a memory access parameter of the first or second data, and wherein the memory parameter MP is configured for accessing a flash memory including a block including a plurality of pages, and wherein the memory access parameter is at least one of a block address, a page address, a word line address, a bit line address, a chip identification (ID) of the flash memory, a program count and an erase count.