Patent ID: 6157232
Filing Date: 2000-12-05
Classification: H03L,H04J

Abstract:
A system for generating a clock output signal whose frequency and phase are synchronized to the frequency and phase of an external input clock reference signal, comprising:a. a numerically controlled signal generator for generating the clock output signal whose frequency and phase are determined by a control input signal;b. an input frequency divider for dividing the external input clock reference signal by a first constant k.sub.12 or a second constant k.sub.22 ;c. an output frequency divider for dividing the output signal by a first constant k.sub.11 or a second constant k.sub.21 ;d. a relay-phase detector, receiving output signals from the input frequency divider and the output frequency divider, for producing a 0 or a 1 output, which output controls the input frequency divider to divide by k.sub.12 or k.sub.22 and controls the output frequency divider to divide by k.sub.11 or k.sub.21, causing the input frequency divider and the output frequency divider to shift from one set of constants k.sub.12 and k.sub.11 to the second set of constants k.sub.22 and k.sub.21 upon a change in state of the output signal of the relay-phase detector; andf. a phase accumulator, coupled to the output of the relay-phase detector, for detecting an accumulated count of the phase outputs of the relay-phase detector, wherein the output of the phase accumulator controls the numerically controlled signal generator.