Patent ID: 6088788
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A data processing system, comprising:a plurality of execution units forming a plurality of processing pipelines, said plurality of processing pipelines processing instructions and including a storage pipeline;an instruction unit outputting instructions to said plurality of execution units, and controlling execution of multiple threads by said plurality of execution units, a thread currently being executed by said plurality of execution units referred to as a foreground thread, and a thread not currently being executed by said plurality of execution units referred to as a background thread, having at least one background instruction;a storage control unit capable of receiving both a data fetch request resulting from a data cache miss, and an instruction fetch request resulting from an instruction cache miss either or both of said cache misses occurring when said background thread was a previously executing foreground thread,said storage control unit monitoring said storage pipeline to determine when said storage pipeline during the execution of said foreground thread to determine when said instruction unit does not dispatch an instruction from said foreground thread to said storage pipeline and hence said storage pipeline becomes available,in the case of said data fetch request, said storage control unit, routing said background instruction to said storage pipeline when said storage control unit determines that said storage pipeline is available and directly outputting requested data associated with said background instruction to said plurality of execution units; andin the case of said instruction fetch request, said storage control unit directly outputting said requested instruction to said instruction unit.