Patent ID: 7102403
Filing Date: 2006-09-05
Classification: H03L

Abstract:
1. A clock recovering circuit for generating an output clock that is locked to an analog input signal, comprising: a phase detection unit for generating a phase error signal representing a phase error between the analog input signal and the output clock; a loop filter coupled to the phase detector for filtering the phase error signal and generating a control signal; a numerically controlled oscillator coupled to the loop filter for generating a first clock and an index signal according to the control signal, wherein the numerically controlled oscillator is clocked by a reference clock having a preset frequency; a delay locked loop coupled to the numerically controlled oscillator for receiving the first clock and generating a plurality of second clocks; and a multiplexer coupled to the numerically controlled oscillator and the delay locked loop for selecting one of the second clocks as the output clock according to the index signal.