Patent ID: 7912166
Filing Date: 2011-03-22
Classification: G01R

Abstract:
1. A built-in jitter measurement circuit, for measuring a jitter of a clock signal output by a circuit under test relative to a reference clock signal, the jitter measurement circuit comprising: a synchronous dual-phase detector, coupled to the circuit under test, for delaying the clock signal and the reference clock signal and detecting a phase relationship between the delayed clock signal and the delayed reference clock signal, wherein the delays of the clock signal and the reference clock signal are different; and a decision circuit, coupled to the synchronous dual-phase detector, for performing logic operations, data latching, and counting on the phase relationship detected by the synchronous dual-phase detector to obtain a counting value related to the jitter of the clock signal, wherein the synchronous dual-phase detector comprises: a first delay buffer, delaying the reference clock signal to generate a first delayed reference clock signal; a second delay buffer, delaying the reference clock signal to generate a second delayed reference clock signal; a third delay buffer, delaying the clock signal to generate the delayed clock signal; a first phase detector, coupled to the first delay buffer and the third delay buffer for detecting a phase relationship between the first delayed reference clock signal and the delayed clock signal; and a second phase detector, coupled to the second delay buffer and the third delay buffer for detecting a phase relationship between the second delayed reference clock signal and the delayed clock signal; wherein the delay of the third delay buffer is between the delay of the first delay buffer and the delay of the second delay buffer; and the first phase detector and the second phase detector are reset after every sampling.