Patent ID: 7391636
Filing Date: 2008-06-24
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising sub memory cell array regions comprising memory cells connected between bit lines arranged in a perpendicular direction to word lines and sub word lines arranged in the same direction as the word lines, sub word line driver regions arranged on first and second areas between the sub memory cell array regions, sense amplifier regions arranged on third and fourth areas between the sub memory cell array regions, and conjunction regions arranged on left and right sides between the sub word line driver regions, the device comprising: column selecting signal lines arranged in a perpendicular direction to the word lines on a different layer from the word lines above the sense amplifier regions and the sub memory cell array regions; local data IO signal lines arranged in the same direction and on the same layer as the word lines above the sense amplifier region and the conjunction region; sub word line driver control signal lines arranged in the same direction as the column selecting signal lines on a different layer from the word lines above the conjunction regions and the sub word line driver regions; and global data IO signal lines arranged in the same direction as the column selecting signal lines on a different layer from the word lines and the sub word line driver control signal lines above the conjunction regions and the sub word line driver regions, wherein a local global IO MUX which transmits data between the local data IO signal lines and the plurality of global data IO signal lines is arranged in the conjunction region.