Patent ID: 6331963
Filing Date: 2001-12-18
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of first memory cell array blocks connected to n/2 column select signal lines among n column select signal lines arranged in the same direction as word lines, including a plurality of memory cells connected between a plurality of the word lines and a plurality of bit line pairs;a plurality of second memory cell array blocks connected to the remaining n/2 column select signal lines among said n column select signal lines, including identical memory cell array blocks to said plurality of first memory cell array blocks;a plurality of first column decoders for generating (i) first decoding output signals for selecting the plurality of first memory cell array blocks and the plurality of second memory cell array blocks by decoding a first bit of a plurality of bits of a column address and (ii) second decoding output signals for selecting n/4 column select signal lines disposed at a top and a bottom side of each of the plurality of memory cell array blocks by decoding second bits except a first bit among the plurality of bits of a column address; anda plurality of second column decoders for selecting n/4 column select signal lines of corresponding memory cell array blocks in response to corresponding block select signals among a plurality of block select signals for selecting said plurality of first and second memory cell array blocks, and said first decoding and second output signals;wherein said n/4 column select signal lines are commonly connected to adjacent memory cell array blocks.