Patent ID: 6515521
Filing Date: 2003-02-04
Classification: G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit comprising a p-channel FET, and an n-channel FET,a first circuit for generating a first pulse signal; and a second circuit for generating a second pulse signal, wherein: said first pulse signal is supplied to a gate of said p-channel FET; said second pulse signal is supplied to a gate of said n-channel FET; HIGH of said first pulse signal is different from HIGH of said second pulse signal; LOW of said first pulse signal is different from LOW of said second pulse signal; timing of changing said first pulse signal from HIGH to LOW is synchronized with timing of changing said second pulse signal from HIGH to LOW; and timing of changing said first pulse signal from LOW to HIGH is synchronized with timing of changing said second pulse signal from LOW to HIGH; said first circuit includes p-channel and n-channel FET's having source-drain paths connected in series; and said second circuit includes p-channel and n-channel FET's having source-drain paths connected in series; said series connected source-drain paths of said p-channel and n-channel FET's of said first circuit are connected between a first potential and a first node; said series connected source-drain paths of said p-channel and n-channel FET's of said second circuit are connected between a second potential and a second node; either one of said second potential and a third potential is supplied to said first node through a first selector; and either one of said first potential or a fourth potential is supplied to said second node through a second selector.