Patent ID: 7143304
Filing Date: 2006-11-28
Classification: G06F

Abstract:
1. A synchronous bus system comprising: a phase-locked loop (PLL); a buffer element; a Bus Application Specific Integrated Circuit (Bus ASIC), said Bus ASIC including a speed enhancement circuit; said PLL being coupled to said speed enhancement circuit such that a first clock signal is provided to said speed enhancement circuit by said PLL; said PLL being coupled to said speed enhancement circuit such that a second clock signal is provided to said speed enhancement circuit by said PLL; said PLL being coupled to said buffer element such that said first clock signal is provided to said buffer element by said PLL; and said buffer element being coupled to said speed enhancement circuit such that data is transferred between said buffer element and said speed enhancement circuit, wherein; said data is held in said speed enhancement circuit for at least two cycles of said second clock signal.