Patent ID: 6445419
Filing Date: 2002-09-03
Classification: H04N

Abstract:
An image processing apparatus, comprising:a decoding circuit block decoding a coded image signal of MPEG specified by an NTSC system with a frame rate of the NTSC system and writing a decoded image signal of the MPEG in an image memory as MPEG image data; and a display-image producing circuit block performing a frame rate transformation from the NTSC system to a PAL system with the MPEG image data, skipping a field at intervals of some fields, when reading the MPEG image data from the image memory with a frame rate of the PAL system, and thereby producing MPEG image data; and an inverted line correcting filter for correcting image mutilation caused by inverted lines, the MPEG image data, in which a field at intervals of some fields is skipped, read out from the image memory is inverted in order of a top field and a bottom field.