Patent ID: 7550330
Filing Date: 2009-06-23
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a patterned dummy gate region atop a semiconductor substrate; forming a first buried insulating region in the semiconductor substrate utilizing the patterned dummy gate region as an ion implantation mask; providing a planarizing material which exposes a top surface of the patterned dummy gate region; removing the patterned dummy gate region to expose a portion of the semiconductor substrate which is located between the first buried insulating region; forming a second buried insulating region having a shallower depth than the first buried insulating region into the exposed portion of the semiconductor substrate; forming body contacts into the semiconductor substrate in areas above and below the second buried insulating region, said body contacts having a dopant concentration of about 10 forming a gate dielectric and gate conductor above said second buried insulating region; removing the planarizing material; and forming source/drain diffusion regions into the semiconductor substrate above the first buried insulating region.