Patent ID: 8742845
Filing Date: 2014-06-03
Classification: H03F

Abstract:
1. An amplifier circuit comprising: an input differential circuitry comprising a first output terminal and a second output terminal, configured to provide a pair of differential current signals at the first output terminal and the second output terminal in response to a pair of input differential voltage signals; a cascode circuitry comprising a first cascode transistor having a terminal coupled with the first output terminal and a second cascode transistor having a terminal coupled with the second output terminal, the cascode circuitry configured to mirror the pair of differential current signals received from the first output terminal and the second output terminal to an output terminal of the first cascode transistor and an output terminal of the second cascode transistor; and a current control circuit coupled with the first output terminal and the second output terminal, configured to divert an amount of bias current so as to reduce a current through the cascode circuitry to thereby reduce a load of the amplifier circuit, wherein the reduction in the load of the amplifier circuit allows reduction in a current through the input differential circuitry for maintaining a predetermined bandwidth of the amplifier circuit, said current control circuit comprising: a first transistor having a first terminal, a second terminal and a third terminal, the first terminal of the first transistor coupled with the first output terminal, the second terminal of the first transistor configured to receive a first signal of the pair of input differential voltage signals; a second transistor having a first terminal, a second terminal and a third terminal, the first terminal of the second transistor coupled with the second output terminal, the second terminal of the second transistor configured to receive a second signal of the pair of input differential voltage signals; and a current source for biasing the first transistor and the second transistor, the current source coupled between a power supply terminal and the third terminal of the first transistor and the second transistors; and wherein the amount of the bias current that is diverted is based on at least one of a maximum slew rate of the amplifier circuit and a predetermined location of a cascode pole of the amplifier circuit.