Patent ID: 7676650
Filing Date: 2010-03-09
Classification: G06F

Abstract:
1. An apparatus for controlling instruction fetch, comprising: an instruction buffer unit having a plurality of instruction buffers and a plurality of pointer units, wherein each of the plurality of pointer units corresponds to each of the instruction buffers and indicates a connection relation of the instruction buffers via numerical instruction buffer IDs, each of the plurality of pointer units including a valid flag for indicating that the corresponding instruction buffer is validated; a connection relation establishment unit establishing the connection relation between instruction buffers different from another connection relation established by an instruction fetch request, whereby the connection relation establishment unit reuses a fetched instruction in one of the instruction buffers; and a loop-state structure connecting unit connecting the instruction buffers into a loop by the plurality of pointer units, wherein each of the pointer units points to any one of the instruction buffers, and once the loop-state structure connecting unit connects the loop, the validated instruction buffer is not invalidated until the loop is released.