Patent ID: 6470292
Filing Date: 2002-10-22
Classification: G01D

Abstract:
A position detection apparatus comprising:a recording medium on which a periodic position signal is recorded; a detection section having a first detection head that moves relative to said recording medium along a recording direction of said periodic position signal for detecting said periodic position signal and producing a first detection signal, and a second detection head disposed apart from said first detection head by a predetermined distance in said recording direction that moves relative to said recording medium, operating with said first detection head, for detecting said periodic position signal and producing a second detection signal; a polar conversion section for converting said first detection signal detected by said first detection head and said second detection signal detected by said second detection head into a 2-bit quadrant signal representing a relative position of said recording medium and said detection section in a quadrant in one period of said periodic position signal and an in-quadrant angle signal showing a relative position of said recording medium and said detection section as an angle in each quadrant; and an output section for outputting a two-phase increase and decrease pulse, based on said 2-bit quadrant signal, said in-quadrant angle signal, and a division number signal showing a number of divisions in said quadrant of said periodic position signal, such that one said pulse is generated when said recording medium and said detection section move relative to each other for a distance obtained by dividing said quadrant of said periodic position signal by said number of divisions, wherein said output section comprises: a first multiplier for multiplying said in-quadrant angle signal and said division number signal, and extracting a bit number equal to said division number signal from an upper bit in a multiplication result to generate an in-quadrant division address signal; a second multiplier for multiplying a lower 2 bits of said division number signal and said quadrant signal; an adder for adding a lower 2 bits of said in-quadrant division address signal output from said first multiplier and a lower 2 bits of a multiplication result of said second multiplier; and an increase and decrease pulse generator for generating said two-phase increase and decrease pulse by encoding a lower 2 bits of a multiplication result of said adder.