Patent ID: 6043522
Filing Date: 2000-03-28
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a P-type substrate set at a potential lower than a around potential of a power supply connected to said semiconductor device; andat least two cells, each of said cells including:an N-type well in said substrate;a P-type well in said substrate;a P-type diffused region in said N-type well;an N-type diffused region in said P-type well; andan isolation region in said substrate isolating the one of said N-type and P-type wells having the same conductivity type as said substrate, from said substrate,wherein any two cells which are adjacent in a direction of alignment intersecting both N-type wells and P-type wells are disposed such that two wells of the same conductivity type are disposed successively in two adjacent cells, andwherein said isolation region extends across two adjacent cells and encloses two successive wells of the same conductivity type, collectively isolating said two successive wells from said substrate, said two successive wells having the same conductivity type as said substrate.