Patent ID: 6166574
Filing Date: 2000-12-26
Classification: G06F,H03K,Y02D

Abstract:
A clock control circuit, comprising:a first storage element for receiving a direct input first signal, a periodic signal and a second signal and having an output Q.sub.1, wherein a change in said first signal is indicative of the start of a clock signal, and wherein said periodic signal is for triggering the storage of said second signal in said first storage element;a second storage element for receiving said direct input first signal, said periodic signal and said output Q.sub.1 of said first storage element and having an output Q.sub.2 ; anda logic gate for receiving the output Q.sub.2 of the second storage element as a first input and having an output Q.sub.3 which is connected through a delay line to a second input of the logic gate in a feedback arrangement, wherein said output Q.sub.3 is said clock signal.