Patent ID: 7043729
Filing Date: 2006-05-09
Classification: G06F

Abstract:
1. A system having reduced system management interrupt (SMI) latency while pullng in system management mode, comprising: a central processing unit (CPU) coupled to a memory and comprising a system clock, a SMI handler, a flags register, a delay queue for storing a list of delay threads and a list of delayed threads, a suspended queue for storing a list of suspended threads, a ready queue for storing a list of threads ready for execution, and a stack, which CPU is capable of responding to a system management interrupt and, at this time, changing its execution location to a previously defined location; a software SMI generator for generating software SMI's; hardware SMI generator for generating SMI at predetermined intervals; thread detector for detecting the source of the SMI; an elapsed time detector for reading the system clock to determine the amount of elapsed time since the last time the system clock was read; a thread generator for creating different execution threads that include at least the current execution location, their own general purpose registers and their own stack and for creating, suspending, resuming and destroying execution threads; a thread delay generator for delaying a thread for at least a predetermined period of time, and for delaying a thread for at most the predetermined period of time; an SMI source detector for detecting a source of the SMI an for creating an appropriate thread to handle the SMI, and for detecting whether the CPU entered the SMI handler using a software SMI; an idle thread that runs at a lowest thread priority, and which exits the SMI handler to either schedule a recurring SMI or modify the saved flags register of the CPU; normal-node code for using the software SMI generator to create an SMI thread that executes at a specified address, with the specified contents in the general-purpose registers; a thread transfer mechanism by which threads in the delay queue are moved into the ready queue so that they are ready for execution; and software code comprising: a code segment that generates a system management interrupt; a code segment that saves the state of the CPU; a code segment that creates an idle thread derived from the saved state; a code segment that exits system management mode during a time period prior to a hardware polling event; a code segment that services pending lower-priority interrupts during the time period prior to the hardware polling event; a code segment that re-enters system management mode once the lower priority interrupts are serviced; and a code segment that resumes polling.