Patent ID: 8835251
Filing Date: 2014-09-16
Classification: H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor device comprising: depositing a polysilicon layer on top of a semiconductor substrate followed by patterning and doping said polysilicon layer into a transistor gate, a bottom conductive layer for a capacitor and a first and second high resistance (HR) contact regions; depositing, etching and patterning a spacer layer of a dielectric material to form a high resistance (HR) segment between the first and second HR contact regions and spacers surrounding sidewalls of the transistor gate, sidewalls of the bottom conductive layer of the capacitor and sidewalls of the first and second HR contact regions; and depositing and patterning an insulator layer on top of said bottom conductive layer of said capacitor as a capacitor dielectric layer and on top of the HR segment between the first and second HR contact regions as a resistor segment followed by depositing, patterning and annealing a Ti/TiN layer to form a top conductive layer for said capacitor with a lateral extension beyond the bottom conductive layer for the capacitor to function as an electrode contact layer for contacting an external electrode of the capacitor thus forming said capacitor as a single polysilicon layer metal-insulator-polysilicon (MIP) structure and said step of depositing, patterning and annealing the Ti/TiN layer further comprising patterning and annealing the Ti/TiN layer on top of the HR segment between the first and second HR contact regions to function as electrodes to contact the HR segment and the resistor segment.