Patent ID: 9013468
Filing Date: 2015-04-21
Classification: G09G

Abstract:
1. A display device, comprising: a data driver for applying a data signal to a data line; a gate driver for applying a gate signal to a gate line; a level shifter for shifting a voltage level of a signal applied to the gate driver; and a signal controller, for controlling the data driver, the level shifter, and the gate driver, wherein when a signal exchange between the data driver and the signal controller has an abnormality, the signal controller maintains a control signal applied to the level shifter in an off level, wherein the control signal includes a vertical synchronization start signal and vertical clock signals, wherein the signal controller outputs a gate driver off signal to the level shifter, and the signal controller puts the gate driver off signal in a high level and transmits the gate driver off signal to the level shifter when the signal exchange between the data driver and the signal controller has the abnormality, wherein the level shifter comprises: a logic gate for receiving the gate driver off signal, the vertical synchronization start signal and the vertical clock signals, putting a gate blocking signal in the high level and outputting the gate blocking signal to a controller of the level shifter when the vertical synchronization start signal and the vertical clock signals are in a low level and the gate driver off signal is in the high level; the controller of the level shifter for receiving the vertical synchronization start signal, the vertical clock signals and the gate blocking signal; and a charge share unit for amplifying voltages of the vertical synchronization start signal and the vertical clock signals to generate a gate pulse start signal and a pair of gate clock signals and outputting the gate pulse start signal and the pair of gate clock signals to the gate driver when the gate blocking signal is in the low level, or giving the gate pulse start signal and the pair of gate clock signals an off voltage and outputting the gate pulse start signal and the pair of gate clock signals to the gate driver when the gate blocking signal is in the high level.