Patent ID: 8626480
Filing Date: 2014-01-07
Classification: G01R,G06F

Abstract:
1. A method for simulating an integrated circuit (IC) design in a circuit design simulator, the method comprising: receiving data representing a circuit design, said data configured for input to and processing by said circuit design simulator; when simulating said circuit design, accessing an integrated circuit quiescent current (IDDQ) prediction macro to model leakage current prediction for said circuit design, said leakage current prediction determinable at a single device, cell, circuit, or IC chip level of said design, specifying in said IDDQ prediction macro an uplift switch value corresponding to one of: said device, cell, circuit, or IC chip level of design being simulated; automatically calculating one or more uplift factors used in said leakage current prediction at one of said single device, cell, circuit, or IC chip level of design based on said switch value, said uplift factor(s) calculated based on device variations effects and implemented in said leakage current prediction model to simulate the leakage current calculations according to the level of design, wherein an uplift factor is a function of a statistical quantity σ wherein for a specified uplift factor switch value modeling a transistor device, σ wherein a processor device performs at least one of said receiving, accessing, modeling and uplift factor calculating.