Patent ID: 7796652
Filing Date: 2010-09-14
Classification: H04L

Abstract:
1. A first-in-first-out (FIFO) circuit for buffering of a high speed input bit stream of data bits (din_s), including: a 1:M demultiplexer for generating M lower speed serial input data streams (din_p a first plurality M of 1:N demultiplexers, each for generating N first data bit streams each first data bit stream carrying a distinct second subset of the first subset of the data bits; a second plurality of M times N bit slices, each bit slice forwarding the first data bit streams into second data bit streams; a third plurality M of N:1 multiplexers, each for combining N second data bit streams of the second subset into a (lower speed) serial output bit stream (dop_p an M:1 multiplexer for combining the (lower speed) serial output bit streams into a high speed output bit stream (dop_s).