Patent ID: 9082867
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A CMOS integrated circuit (IC) comprising: a semiconductor substrate: a cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell including: means disposed on the substrate for applying respective programming voltages to the source and drain regions and to the polysilicon gate structure such that channel hot electrons are generated in the channel region that become trapped in a portion of the nitride layer located over the channel region, wherein the source region and the drain region respectively include first and second lightly-doped drain extension diffusion (LDD) implants comprising an n-type dopant material diffused into the substrate such that the channel region is disposed between first and second inside LDD boundaries of said first and second LDD implants, and wherein the source region and the drain region further respectively include first and second pocket implants comprising a p-type dopant material diffused into the substrate such that respective portions of said first and second pocket implants extend from said first and second inside LDD boundaries into said channel region.