Patent ID: 6230262
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A method for managing physical registers in a processor, the method comprising:assigning a first physical register to a destination operand of a first instruction operation, said destination operand identifying a logical register;retiring said first instruction operation;updating an architected renames block with a first physical register number corresponding to said first physical register responsive to said retiring, wherein said first physical register number identifies said first physical register in a register file;reading a second physical register number from said architected renames block responsive to said retiring, said second physical register number being displaced from representing said logical register within said architected renames block by said first physical register number;determining that said second physical register number also represents a second logical register within said architected renames block subsequent to said updating; andinhibiting freeing a second physical register corresponding to said second physical register number responsive to said determining that said second physical register number also represents said second logical register within said architected renames block, wherein said second physical register number identifies said second physical register in said register file.