Patent ID: 6642742
Filing Date: 2003-11-04
Classification: H03K

Abstract:
An input/output (I/O) circuit comprising:a first plurality of resistive elements connected in parallel between a first reference node and an output node and a second plurality of resistive elements connected in parallel between the output node and a second reference node, wherein each of the first plurality of resistive elements and each of the second plurality of resistive elements includes a control terminal, and wherein the output node is coupled to a core circuit and a signal line; and a control circuit coupled to the control terminal of each of the-first plurality of resistive elements and each of the second plurality of resistive elements, wherein the control circuit is configured to activate one or more of the first plurality of resistive elements during a logic high transmission from the core circuit onto the signal line, and wherein the control circuit is configured to activate one or more of the second plurality of resistive elements during a logic low transmission from the core circuit onto the signal line; wherein the first plurality includes first, second, and third resistive elements, wherein each of the first, second, and third resistive elements is of a substantially different resistance with respect to each other; and wherein the second plurality includes fourth, fifth, and sixth resistive elements, wherein each of the fourth, fifth, and sixth resistive elements is of a substantially different resistance with respect to each other.