Patent ID: 7385297
Filing Date: 2008-06-10
Classification: H01L

Abstract:
1. An integrated circuit die comprising: a plurality of active circuits; a multiplicity of vertically separated metallization layers that are separated by dielectric layers, each of the metallization layers being formed from the same material; a plurality of bond pad structures that function as I/O pads for the die, the bond pad structures being formed from a part of a first one of the metallization layers, each bond pad structure being exposed through an associated opening in a passivation layer to define a bond pad, wherein the bond pad structures do not have any dielectric layers formed within the bond pad structures, and wherein at least some of the bond pad structures have active circuits positioned below the associated bond pad and whereby the bond pad defines a wire bonding surface that is suitable for wire bonding and directly supporting a bonding wire; and a plurality of electrically conductive vias, each via being arranged to pass through an associated one of the dielectric layers to electrically interconnect a pair of metallization layers, wherein the vias are arranged so that none of the vias that are coupled to the first metallization layer are positioned below any of the bond pads in a region that overlies any of the active circuits.