Patent ID: 8085074
Filing Date: 2011-12-27
Classification: H03L

Abstract:
1. A delay locked loop (DLL) comprising: a plurality of delay elements, each delay element to provide a delay to an input bit stream, and to generate a plurality of delayed input bit streams; a sampling circuit comprising a plurality of memory cells including a first memory cell, the first memory cell to receive the input bit stream and each of the other memory cells in the plurality of memory cells to receive a corresponding one of the delayed input bit streams, the plurality of memory cells to sample a corresponding one of the plurality of delayed input bit streams and the input bit stream at an active edge of a clock signal to generate corresponding sampled outputs; a plurality of logic gates, each to receive a corresponding pair of outputs comprised in the corresponding sampled outputs to determine a delay between the active edge of the clock signal and a bit boundary of the input bit stream within a time interval equal to an interval between a first transition of the input bit stream and a subsequent active edge of the clock signal, outputs of the logic gates selecting from the input bit stream and the plurality of delayed input bit streams a selected bit stream with the determined delay; and a phase discriminator to compare a phase of the selected bit stream with a phase of the clock signal, and to generate an error signal representing a phase difference between the phase of the selected bit stream and the phase of the clock signal, wherein the error signal is coupled to the sampling circuit to maintain phase lock between the clock signal and the selected bit stream.