Patent ID: 6046693
Filing Date: 2000-04-04
Classification: G09G

Abstract:
A circuit for accurately converting analog video signals output from a VGA card into digital video signals, comprising:a clock signal synthesizer receiving a synchronizing signal and a frequency indicating signal output from a CPU, and outputting a clock signal A/D CLOCK having the same frequency as the pixel frequency;a video signal processor receiving an analog video signal output from a VGA card and a constant signal, and outputting a signal according to the comparison result of the two input signals;a D flip-flop with CLK terminal receiving the signals output from the video signal processor and D terminal receiving the clock signal A/D CLOCK output from the clock signal synthesizer;a D/A converter receiving a phase indicating signal from the CPU, and outputting an analog signal corresponding to the phase indicating signal;a CPU connected to the Q terminal of said D flip-flop outputting said frequency indicating signal and said phase indicating signal, which are sent to said clock signal synthesizer and said D/A converter, respectively according to the Q value of the D flip-flop;a phase delaying circuit receiving a horizontal synchronizing signal output from a VGA card and the output signal of said D/A converter, and delaying the phase of the horizontal synchronizing signal according to the output signal of said D/A converter, this phase-delayed horizontal synchronizing signal then being supplied to said clock signal synthesizer as its synchronizing signal; andan A/D converter receiving an analog video signal output from the VGA card and a clock signal A/D CLOCK output from said clock signal synthesizer, and outputting a digital video signal which is the output signal of the whole circuit,the whole circuit being operated as follows: in the first part, the frequency of the output digital signal being first tuned to be the same as the pixel frequency; in the second part, the frequency of the digital signal being fixed and the phase of said digital signal is tuned,the first part being progressed in accordance with the following steps:(1-1) checking the Q value of said D flip-flop, if Q value being constant, the frequency of the digital video signal output from said A/D converter being the same as the pixel frequency, then the first part being finished, otherwise proceeding to (1-2);(1-2) the CPU emitting said phase indicating signal to said D/A converter, said D/A converter thus outputting an analog signal which causes said phase delaying circuit to delay the phase of the input horizontal synchronizing signal, the phase of the output clock signal of said clock signal synthesizer thus being delayed, then proceeding to (1-3);(1-3) checking if the phase delay of the clock signal has exceeded one period, proceeding to (1-1) if not, proceeding to (1-4) otherwise;(1-4) the CPU emitting the phase indicating signal to said clock signal synthesizer, which changes the frequency of the output clock signal, then returning to (1-1),the second part being progressed as follows:(2-1) the CPU emitting the phase indicating signal to said D/A converter, which causes the phase of the output clock signal of said clock signal synthesizer being delayed, then proceeding to (2-2);(2-2) checking the Q value, if Q value being not constant, the output digital video signal of said A/D converter being desired, the second part being finished, otherwise returning to (2-1).