Patent ID: 6531784
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A semiconductor package, comprising:a substrate having opposite first and second surfaces; a first semiconductor die having a first surface with a plurality of terminal pads in a central portion thereof and an opposite second surface mounted on the first surface of the substrate; a first pair of spacer strips, each comprising a flat, elongated element of an insulative material having a first surface and an opposite second surface mounted on the first surface of the die adjacent to respective opposite edges thereof; a plurality of electrically conductive paths, each path connecting a terminal pad on the die to a terminal pad on the substrate and having an intermediate portion passing transversely across the first surface of one of the spacer strips; a means for enclosing the first semiconductor die, the first pair of spacer strips, the electrically conductive paths, and at least a portion of the first surface of the substrate within said semiconductor package, wherein each of the first surfaces of the spacer strips has a plurality of wire bonding pads thereon, and wherein each of the electrically conductive paths comprises a first metal wire having a first end bonded to one of the terminal pads on the die and a second end bonded to a corresponding one of wire bonding pads; and, a second metal wire having a first end bonded to a terminal pad on the substrate and a second end bonded to the corresponding wire bonding pad.