Patent ID: 6265768
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A chip scale package comprising:a substrate having an upper surface, a lower surface, and a slot defined therein, the substrate is provided with a structure for making external electrical connection;a semiconductor chip having a plurality of bonding pads centrally formed on the active surface thereof, the active surface of the semiconductor chip being attached to the upper surface of the substrate in a manner that the bonding pads thereof are corresponding to the slot of the substrate, the bonding pads of the semiconductor chip being electrically connected to the structure for making external electrical connection; anda package body having a first portion formed on the upper surface of the substrate around the chip and a second portion formed within the slot of the substrate, wherein the package body comprises a resin base material divided into a first region and a second region, and the resin base material contains a plurality of filler particles having the percentage by weight of the filler particles in the first and second regions being different.