Patent ID: 7391647
Filing Date: 2008-06-24
Classification: G11C,H01L

Abstract:
1. A non-volatile memory system including one or more non-volatile memory cells fabricated on a semiconductor substrate, wherein each non-volatile memory cell comprises: a floating gate electrode; a PMOS access transistor located in a first n-type region, wherein the PMOS access transistor is configured to remove negative charge from the floating gate electrode during an erase operation, and is further configured to supply current to be sensed during a read operation; a PMOS control capacitor located in a second n-type region, which is separate from the first n-type region; and an NMOS programming transistor located in a p-type region, wherein the NMOS programming transistor is configured to add negative charge to the floating gate electrode during an program operation, wherein the floating gate electrode extends over active regions of the PMOS access transistor, the PMOS control capacitor and the NMOS programming transistor.