Patent ID: 8310066
Filing Date: 2012-11-13
Classification: H01L

Abstract:
1. A semiconductor apparatus comprising: a semiconductor chip having a multilayered wiring structure; a plurality of electrode pads formed on a top surface of the semiconductor chip and along the outer periphery of said semiconductor chip; and a wiring coupled to two electrode pads selected from said plurality of electrode pads, arranged to encircle by more than a full circle the outer periphery of said semiconductor chip, and a plurality of wirings between said two electrode pads in plan view, wherein said plurality of wirings includes a first wiring formed on an upper layer and a second wiring formed on a lower layer, wherein said first wiring and said second wiring are connected in series by a connection plug, wherein said second wiring is disposed at every corner of said semiconductor chip, and wherein said two electrode pads coupled to said wiring are formed along different edges of said semiconductor chip.