Patent ID: 7541277
Filing Date: 2009-06-02
Classification: H01L

Abstract:
1. Method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of conductors, and chemical-mechanical polishing (CMP), wherein a sacrificial material resides between conductors of the interconnect layer, and wherein the dielectric cap layer is made porous through an oxidation process including RIE, the method comprising: depositing a first insulating material on a substrate having a plurality of logic elements formed thereon; performing a first RIE process using CF forming the dielectric cap layer by depositing a silicon nitride (Si performing a second RIE process using CF evacuating a sacrificial material between the conductors of the interconnect layer; and depositing a second insulating material to seal the Si