Patent ID: 6788120
Filing Date: 2004-09-07
Classification: H03K

Abstract:
A system comprising a duty cycle correction (DCC) circuit, the DCC circuit comprising:an input clock terminal; an output clock terminal; a first counter circuit having a clock terminal coupled to the input clock terminal and a plurality of output terminals; a second counter circuit having a clock terminal coupled to the input clock terminal, a reset terminal, and a plurality of output terminals; a register having a plurality of data input terminals coupled to the output terminals of the first counter circuit, a clock terminal coupled to the input clock terminal, and a plurality of output terminals; a comparator having a first set of input terminals coupled to the output terminals of the second counter circuit, a second set of input terminals coupled to the output terminals of the register, and an output terminal coupled to the reset terminal of the second counter circuit; and an output clock generator having a first input terminal coupled to the input clock terminal, a second input terminal coupled to the output terminal of the comparator, and an output terminal coupled to the output clock terminal.