Patent ID: 6930933
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A semiconductor memory device having memory banks and redundancy circuits for accessing the stored data in the memory banks by row and column operations, the semiconductor memory device comprising: a pair of first and second memory banks, each bank of the pair having a total of 2N number of redundancy lines for accessing the stored data, the N being a positive integer, wherein, only a first set of N number of redundancy lines are utilized to access the stored data during normal operations; a pair of first and second redundancy control blocks, each redundancy control block is electrically connected to both the first and second memory banks, wherein the first redundancy control block provides N number of redundancy signals to the first memory bank for normal operation and the second redundancy control block provides N number of redundancy signals to the second memory bank for normal operation; and an address signal switching unit for receiving a set of input signals indicative of the first or second memory bank failure;