Patent ID: 7269082
Filing Date: 2007-09-11
Classification: G11C

Abstract:
1. A chip enable control circuit comprising: a chip enable signal generating circuit which generates a chip enable signal for controlling a state of a memory, the chip enable signal generating circuit setting the chip enable signal to an enable level when bringing the memory to an operable state in which the memory is operable, the chip enable signal generating circuit setting the chip enable signal to a disable level when bringing the memory to a low power consumption state in which power consumption is lower than in the operable state; and a reference value generating circuit which outputs a reference value corresponding to a period during which the memory is allowed to be continuously in the operable state; wherein when the chip enable signal generating circuit does not receive a startup request signal of the memory for a period during which the chip enable signal is the enable level, the chip enable signal generating circuit elongates the period during which the chip enable signal is the enable level to a period corresponding to the reference value and which is not shorter than a chip enable signal hold time of the memory, and sets the chip enable signal to the disable level after the elongated period passes.