Patent ID: 8981496
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. An integrated circuit (IC) structure comprising: a substrate; a semiconductor strip over and connected to the substrate, wherein a top portion of the semiconductor strip forms a fin; a first inter-layer dielectric (ILD) over the substrate, wherein the fin extends into the first ILD; a second ILD over the first ILD, wherein the fin does not extend into the second ILD; a liner extending from a top surface of the second ILD, into the first ILD, and over a top surface and sidewalls of the fin; a signal metal in the first ILD over the fin, wherein a first portion of the liner is between the signal metal and the fin, and wherein a second portion of the liner is disposed on a top surface of the signal metal; a gate spacer in the first ILD; and a gate contact in the second ILD, wherein the gate contact is over and connected to the signal metal, wherein the gate contact at least partially extends higher than the gate spacer, wherein the liner covers sidewalls of the gate contact, and wherein the gate contact and the signal metal form an uninterrupted metallic region.