Patent ID: 8138054
Filing Date: 2012-03-20
Classification: H01L

Abstract:
1. A method for creating an enhanced FET comprising: creating a gate having a first gate dielectric on a first surface of the gate and a second gate dielectric on a second surface of the gate, the first and second surfaces of the gate being parallel to a semiconductor substrate; creating source/drain regions in the semiconductor substrate; electrically isolating a third surface of the gate and a fourth surface of the gate, the third and fourth surfaces of the gate being perpendicular to the semiconductor substrate; growing a first epitaxial layer from the source/drain regions, the first epitaxial layer being doped similarly to the source/drain regions, the first epitaxial layer grown high enough to extend above the second gate dielectric; growing a second epitaxial layer from the first epitaxial layer, the second epitaxial layer being doped opposite the first epitaxial layer, the second epitaxial layer covering a top surface of the second gate dielectric; growing an oxide over shallow trench isolation regions on the semiconductor substrate and over the second epitaxial layer; and performing a planarization that separates a portion of the second epitaxial layer over the top surface of the second gate dielectric from substantially vertical portions of the second epitaxial layer on distal sides of the first epitaxial layer.