Patent ID: 6069046
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method for forming a transistor, comprising:providing a polysilicon layer dielectrically spaced above a semiconductor substrate;patterning a masking layer above a select portion of said polysilicon layer to define a first pair of opposed sidewalls of said masking layer spaced laterally apart by a first lateral distance;implanting a first impurity distribution in said substrate in which the implanting is self-aligned to said first pair of opposed sidewalls of said masking layer;etching said masking layer to define a second pair of opposed sidewalls of said masking layer spaced laterally apart by a second lateral distance;implanting a second impurity distribution into said substrate in which the implanting is self-aligned to said second pair of opposed sidewalls of said masking layer; andetching away portions of said polysilicon layer unmasked by said masking layer to form a gate conductor, subsequent to said implanting the second impurity distribution.