Patent ID: 6218276
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising:providing a partially-formed semiconductor device including a silicon semiconductor substrate having a gate dielectric and polysilicon gate electrode formed thereon, and doped source and drain active regions on either side of said gate electrode;depositing a first refractory metal layer on said partially-formed semiconductor device;annealing the first refractory metal layer to form a layer of first silicide where the first refractory metal layer contacts silicon or polysilicon on said partially-formed semiconductor device;removing unreacted portions of the first refractory metal layer, first silicide and gate dielectric formed on horizontal surfaces of said substrate and gate electrode, other than at the gate electrode/substrate interface, so that first silicide remains on the vertical sidewall surfaces of said gate electrode;forming a layer of spacer dielectric over said gate electrode, first silicide, and substrate;removing spacer dielectric deposited on horizontal surfaces of the gate electrode, first silicide, and substrate so that vertical dielectric spacers remain on the vertical sidewall surfaces of said gate electrode; andforming a second silicide layer on the top surface of said gate electrode and on said source and drain regions, such that said gate electrode is isolated from said source and drain active regions.