Patent ID: 6349101
Filing Date: 2002-02-19
Classification: H04J,H04L

Abstract:
A cell buffer circuit comprising:a cell data shifting section comprising a series connection of shift registers for sequentially shifting input cell data having a preselected length, said shift registers each delaying said input cell data by an amount corresponding to said preselected length; a selector for selecting either the input cell data or cell data output from any one of said shift registers on a cell data basis; and a controller for controlling said selector such that said selector stops, on receiving a back pressure signal when selecting the input cell data, delivery of cell data once and selects cell data output from a first one of said shift registers thereafter, such that said selector selects, on receiving said back pressure signal when selecting cell data output from an nth one of said shift registers, stops delivery of cell data once and selects cell data output from an n+1th one of said shift registers thereafter, such that said selector stops, if the input cell data being selected by said selector are invalid, outputting the invalid cell data, and such that said selector selects, on receiving invalid input cell data when selecting the cell data output from said nth shift register, cell data output from an nâˆ’1th one of said shift registers after said invalid input cell data have been transferred to said nth shift register.