Patent ID: 6410386
Filing Date: 2002-06-25
Classification: H01L

Abstract:
A method for forming a metal capacitor in a damascene process, comprising:providing a first insulator; forming a first Cu wire and a second Cu wire in the first insulator by executing a damascene process; forming a first sealing layer at least on the first and the second Cu wires; forming a second insulator on the first sealing layer; forming a third insulator acting as an etch stop layer on the second insulator; forming a first Cu plug and a second Cu plug in the first sealing layer, the second insulator and the third insulator; forming a first metal layer on the third insulator and the first and second Cu plugs; forming a fourth insulator on the first metal layer; forming a second metal layer on the fourth insulator; patterning the second metal layer, the fourth insulator and the first metal layer to form a capacitor and a conducting wire with a remaining fourth insulator and a remaining second metal layer thereon, wherein a lower electrode of the capacitor is connected with the first Cu wire through the first Cu plug and the conducting wire is connected with the second Cu wire through the second Cu plug; removing the remaining second metal layer; forming a fifth insulator with a flat surface on the upper electrode, the fourth insulator and the third insulator; forming dual damascene structures including a third plug, a fourth Cu plug, a third Cu wire and a fourth Cu wire in the fifth insulator, wherein an upper electrode of the capacitor is connected with the third Cu wire through the third Cu plug, and the conducting wire is connected with the fourth Cu wire through the fourth Cu plug; and forming a second sealing layer covering at least the third and fourth Cu wires.