Patent ID: 8597999
Filing Date: 2013-12-03
Classification: H01L

Abstract:
1. A method of designing an integrated circuit, the method comprising: designing a first transistor comprising a first threshold voltage, a first gate length and a first width; designing a second transistor comprising a second threshold voltage, a second gate length and a second width, wherein the first gate length is smaller than the second gate length, wherein the first threshold voltage is higher than the second threshold voltage; and designing an asymmetric transistor by combining the first transistor and the second transistor, wherein the combining comprises electrically coupling a drain of the first transistor and a source of the second transistor and electrically coupling a gate of the first transistor with a gate of the second transistors, wherein, under a forward bias, the asymmetric transistor has a voltage gain higher than a symmetric long channel transistor having a gate length longer than a sum of the first and the second gate lengths.