Patent ID: 7352835
Filing Date: 2008-04-01
Classification: H03L,H04L

Abstract:
1. Apparatus for receiving and processing a clock data recovery (CDR) signal comprising: reference clock signal processing circuitry that receives as input a reference clock signal and is operative to produce a recovered clock signal having a phase and frequency which respectively corresponds to a phase and frequency of the reference clock signal; data recovery circuitry that receives as input the recovered clock signal and the CDR signal and is operative to phase align the recovered clock signal to the CDR signal, to use the recovered clock signal to recover clock information embedded in the CDR signal, and to use the clock information to recover data information in the CDR signal; a dynamically adjustable parts per million (PPM) detector that receives as input the reference clock signal, the recovered clock signal, and a PPM control signal operative to output a signal when a frequency difference between the reference clock signal and the recovered clock signal is within a dynamically controllable frequency setting controlled by the PPM control signal; and control circuitry that receives as input a first signal, a second signal, and the output signal of the PPM detector and is operative to control the reference clock signal processing circuitry and the data recovery circuitry.