Patent ID: 6185635
Filing Date: 2001-02-06
Classification: H04L

Abstract:
A data transporting circuit comprises:a data extraction module operably coupled to receive a bit stream of data at a rate of at least a bit per input interval, wherein the bit stream of data corresponds to ingress packetized data having one of a plurality of data packetizing protocols, and wherein the data extraction module extracts data from the bit stream of data to produce extracted data;a data packetizing module operably coupled to receive stored data and to packetize the stored data based on a data packetizing protocol of the plurality of data packetizing protocols to produce egress packetized data, wherein the data packetizing module outputs the egress packetized data in a serial manner at a rate of at least a bit per output interval;input/output control module operably coupled to the data extraction module and the data packetizing module, wherein the input/output module generates time slot synchronizing information based on at least one of a clock signal, an ingress data transport protocol, and an egress data transport protocol, and wherein the input interval and the output interval are based on the time slot synchronizing information; andmemory manager operably coupled to the data extraction module to transport the extracted data as ingress data words to a non-local memory for storage and to transport the stored data as egress data words from the non-local memory, wherein the memory manager transports the ingress data words and the egress data words based, at least in part, on content of ingress data words and the egress data words.