Patent ID: 6365458
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A process for forming a semiconductor memory device which includes a control gate, a floating gate for storage of electrical charge, an inter-gate insulation layer between said control gate and said floating gate, a semiconductor substrate, and a tunnel oxide between said floating gate and said semiconductor substrate, wherein said floating gate is formed over said tunnel oxide by a method comprising:forming a first polysilicon layer over said tunnel oxide, said first polysilicon layer being introduced with a dopant of a first conductivity type; forming an insulative layer over said first polysilicon layer; and forming a second polysilicon layer over said insulative layer, said second polysilicon layer being introduced with a dopant of said first conductivity type, thereby forming said floating gate comprising said first polysilicon layer, said insulative layer, and said second polysilicon layer.