Patent ID: 7715400
Filing Date: 2010-05-11
Classification: H04L

Abstract:
1. A method, comprising: receiving, at a distributed memory logic circuit of a first node, data for a packet destined to a distributed memory logic circuit of a second node, wherein the first and second nodes are connected by a network switch fabric and are parts of a distributed shared memory system, and wherein the data for the packet includes a physical memory address in which one or more bits in the address comprise a destination logical node identifier for the second node; using the destination logical node identifier as an index into a connection control block to locate an entry for a connection between the first and second nodes, wherein the connection control block is stored in a local memory on the first node; building a packet in a format of a connection and communication protocol using the data, the destination logical node identifier, and a logical node identifier for the first node, wherein the logical node identifier for the first node is included in the connection control block entry; adding, to the packet, a header that includes a switch fabric address for the second node, wherein the switch fabric address is identified in the located entry of the connection control block; and transmitting the packet on a link to the switch fabric.