Patent ID: 7796459
Filing Date: 2010-09-14
Classification: G11C

Abstract:
1. A memory voltage control circuit comprising: a first slot arranged for a first type of memory plugged thereinto; a second slot arranged for a second type of memory plugged thereinto; a control circuit receiving memory identification signals from the first slot and the second slot, the control circuit comprising first and second field effect transistors (FETs), the first FET and the second FET respectively having a gate and a drain, the gate of the first FET being connected to a memory identification pin of the first slot and connected to a system standby power source via a first resistor, the drain of the first FET being connected to the gate of the second FET, to a memory identification pin of the second slot, and to the system standby power source via a second resistor, the drain of the second FET being grounded via third and fourth resistors connected in series, an output of the voltage conversion circuit being connected to a node between the serial third and fourth resistors via a fifth resistor; a voltage conversion circuit, the control circuit administering the output voltage of the voltage conversion circuit according to the memory identification signals; and a switch circuit, the memory identification signals determining whether the switch circuit to be turned on or off, the on or off state of the switch circuit controlling whether the output voltage of the voltage conversion circuit is to be supplied to the first or the second slot.