Patent ID: 7521753
Filing Date: 2009-04-21
Classification: H01L

Abstract:
1. An integrated circuit device, comprising: a substrate having a trench formed therein; an isolation layer disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench; a buffer layer disposed between the isolation layer and the substrate in the trench; a channel region that is formed under a surface of the second sidewall portion of the trench and an upper surface of the substrate, wherein the channel region extends in a first direction along the substrate a distance exceeding a maximum depth of the channel region under the surface of the second sidewall portion of the trench and along the second sidewall portion of the trench a distance exceeding a maximum depth of the channel region under the upper surface of the substrate; and a gate insulating layer disposed on the second sidewall portion of the trench and extending onto the substrate adjacent to the trench without extending onto the isolation layer.