Patent ID: 7802124
Filing Date: 2010-09-21
Classification: G06F

Abstract:
1. A method for a microcode configurable frequency clock to control a comparator comprising: an act of a memory receiving microcode generated data; an act of a logic circuit receiving an input clock signal comprising a high pulse and a low pulse; an act of the logic circuit frequency processing the input clock high pulse as directed by the microcode generated data to generate a high pulse of an output clock signal; an act of the logic circuit frequency processing the input clock low pulse as directed by the microcode generated data to generate a low pulse of an output clock signal; an act of varying high pulse widths and low pulse widths of the output clock independently as directed by the microcode generated data, the microcode generated data including a first set of bits defining the high pulse widths and a second set of bits defining the low pulse widths; and an act of the high pulse and the low pulse of the output clock signal controlling the speed of comparison for the comparator.