Patent ID: 6980187
Filing Date: 2005-12-27
Classification: G09G

Abstract:
1. A display driver circuit driving first to Mth (M is an integer of two or more) signal electrodes based on gray-scale values, the display driver circuit comprising: a shift register, in which a plurality of flip-flops are connected in series, outputting shift output signals to be sequentially shifted based on a given clock; a gray-scale value bus to which the gray-scale values are sequentially supplied corresponding to the clock; first and second gray-scale value signal buses; a bus dividing circuit outputting the gray-scale values supplied to the gray-scale value bus to one of the first and second gray-scale value signal buses, based on a given bus dividing signal, the bus dividing circuit having a first input connected to the gray-scale value bus for receiving the gray scale values, a second input for receiving the bus dividing signal, a first output connected to the first gray-scale value signal bus, and a second output connected to the second gray-scale value signal bus; first to kth (2≦k<M, k is an integer) gray-scale value latches being provided corresponding to first to kth signal electrodes among the first to Mth signal electrodes, and holding the gray-scale values supplied to the first gray-scale value signal bus based on the shift output signals from the shift register; (k+1)th to Mth gray-scale value latches being provided corresponding to (k+1)th to Mth signal electrodes among the first to Mth signal electrodes, and holding the gray-scale values supplied to the second gray-scale value signal bus based on the shift output signals from the shift register; and an electrode driver circuit driving the first to Mth signal electrodes based on the gray-scale values held in the first to kth gray-scale value latches and the (k+1)th to Mth gray-scale value latches, wherein the gray-scale values on the first gray-scale value signal bus are fixed when the bus dividing circuit outputs the gray-scale values on the gray-scale bus to the second gray-scale value signal bus, and the gray-scale values on the second gray-scale value signal bus are fixed when the bus dividing circuit outputs the gray-scale values on the gray-scale bus to the first gray-scale value signal bus.