Patent ID: 6316979
Filing Date: 2001-11-13
Classification: G11C,H03K

Abstract:
A synchronous memory pulse generator comprising a pulse generator circuit coupled to receive first and second clock signals, the second clock signal 90 degrees out-of-phase with the first clock signal, the pulse generator circuit comprising:a first symmetrical propagation path for generating a first output signal having corresponding transitions, the first propagation path including a first transfer gate coupled to receive the first clock signal and provide the first output signal on a first output node coupled to a drain of a first transistor, the first transfer gate controlled by the second clock signal; anda second symmetrical propagation path for generating a second output signal having corresponding transitions, the second propagation path including a second transfer gate coupled to receive the second clock signal and provide the second output signal on a second output node coupled to a drain of a second transistor, the second transfer gate controlled by the first clock signal.