Patent ID: 6046478
Filing Date: 2000-04-04
Classification: H01L

Abstract:
A combination field effect transistor (FET) and thin film transistor (TFT) comprising:a semiconductor substrate having a source and drain therein and a gate thereon for the FET;a first level insulation covering the semiconductor substrate and having a contact opening in insulation to the drain, said insulation having a horizontal top surface and said contact opening having vertical sidewalls and a horizontal bottom adjacent the drain;an .alpha.-silicon layer disposed vertically on the sidewalls and horizontally on the bottom of the opening and on the top surface of the insulation, said .alpha.-silicon layer having an end portion on the top surface;an insulating layer having a top surface and disposed on all of the .alpha.-silicon layer except the end portion and functioning as a gate insulator for the TFT;a conductive material filling the remaining portion of the opening to form a upper surface level with the top surface of the insulating layer and functioning as the gate for the TFT; anda conductive contact on the end portion of the .alpha.-silicon layer to serve as an local interconnect to the drains of the FET and TFT and a conductive contact on upper surface of conductive material filling the opening to serve as a local interconnect for the gate of the TFT.