Patent ID: 8257992
Filing Date: 2012-09-04
Classification: H01L

Abstract:
1. A method of fabricating a pixel array, comprising: forming a first metal layer over a substrate and patterning the first metal layer to form a plurality of data lines and a plurality of drain patterns adjacent to the data lines, wherein the data lines are separated from the drain patterns; forming an oxide semiconductor layer over the substrate; forming a first insulation layer over the substrate to cover the oxide semiconductor layer; forming a second metal layer on the first insulation layer and patterning the second metal layer to form a plurality of scan lines intersected with the data lines and the drain patterns; and patterning the oxide semiconductor layer and the first insulation layer by using the scan lines as a mask to faun a plurality of oxide semiconductor channels under each of the scan lines, wherein each of the oxide semiconductor channels is located between one of the data lines and one of the drain patterns respectively.