Patent ID: 6979615
Filing Date: 2005-12-27
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising: forming an oxide layer adjacent a substrate; forming a polysilicon layer disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate; forming a PSG layer disposed outwardly from the polysilicon layer; planarizing the PSG layer; forming a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer; forming a dielectric layer in the capacitor channel disposed outwardly from the polysilicon layer; forming a tungsten plug operable to substantially fill the capacitor channel; and forming a first TEOS layer disposed outwardly from the polysilicon layer and disposed inwardly from the PSG layer; and forming a second TEOS layer disposed outwardly from the planarized PSG layer and disposed inwardly from the dielectric layer.