Patent ID: 8841722
Filing Date: 2014-09-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including a plurality of grooves each extending in a first direction and arranged in parallel with each other, each of the grooves including a bottom surface and first and second side surfaces and having a first width in a second direction substantially perpendicular to the first direction; a plurality of element isolation regions on the semiconductor substrate and extending across the plurality of grooves in a third direction oblique to both the first and second directions and arranged in parallel with each other; a plurality of first gate electrodes each on a corresponding one of the first side surfaces of the grooves and extending in the first direction; a plurality of second gate electrodes each on a corresponding one of the second side surfaces of the grooves and extending in the first direction, in each of the grooves the respective one of the first gate electrodes and the respective one of the second gate electrodes are separated from each other by an insulating film; a plurality of element isolation layers each on the semiconductor substrate between a respective pair of the grooves that are adjacent to each other, each of the element isolation layers extending in the first direction and having a second width in the second direction smaller than the first width; a plurality of first diffusion regions each on the bottom surface of a respective one of the grooves; a plurality of second diffusion regions on a top surface of the semiconductor substrate; a plurality of bit lines over the semiconductor substrate and extending across the plurality of element isolation regions in the second direction, the plurality of bit lines being arranged in parallel with each other so that the bit lines intersect the first and second gate electrodes; and a plurality of conductive layers each on the bottom surface of a respective one of the grooves and separated from the first and second gate electrodes by the insulating film in the respective one of the grooves so as to connect the respective bit lines with the bottom surface of the respective grooves.