Patent ID: 6335721
Filing Date: 2002-01-01
Classification: G09G

Abstract:
An LCD source driver having a plurality of driving channels comprising:a control logic responsive to an internal polarity control signal, a first clock signal and a second clock signal, the control logic being inputted alternately and consecutively with digital video signals of multiple bits including odd channel digital video signals and even channel digital video signals, the control logic generating the odd channel digital video signals and the even channel digital video signals corresponding to a logic value of the internal polarity control signal in one of an inputted order and a reversed order; a shift register being activated successively and outputting a plurality of enabling signals; a latch block having a plurality of latches for receiving the odd channel digital video signals and the even channel digital video signals synchronized by the plurality of enabling signals, the latch block generating simultaneously the odd channel digital video signals and the even channel digital video signals when the enabling signals are activated; a negative polarity video signal processor for converting the odd channel digital video signals outputted from the latch block into negative polarity analog video signals having a voltage lower than a common voltage and increased current driving capacity; a positive polarity video signal processor for converting the even channel digital video signals outputted from the latch block into positive polarity analog video signals having a voltage higher than the common voltage and having a higher current driving capacity; and a switching block having a plurality of switching circuits for receiving the negative polarity analog video signals and the positive polarity analog video signals, wherein odd switching circuits of the switching block generate the positive polarity analog video signals on HIGH of the internal polarity control signal and the negative polarity analog video signals on LOW of the internal polarity control signal, and wherein even switching circuits of the switching block generate the negative polarity analog video signals on HIGH of the internal polarity control signal and the positive polarity analog video signals on LOW of the internal polarity control signal.