Patent ID: 6650155
Filing Date: 2003-11-18
Classification: H03K

Abstract:
A power-on reset circuit comprising:a ground input; a power input having a voltage relative to the ground input; a reset output; a self-initializing latch having first and second latch nodes which are initialized to logic high and low states, respectively, upon initial application of power to the power input, wherein one of the first and second latch nodes is coupled to the reset output; a high voltage trigger circuit coupled to the first latch node and reversing the states of the first and second latch nodes when the voltage rises above a high trigger voltage; and a discharge circuit coupled to the second latch node and comprising a switch circuit, which selectively couples the second latch node to the ground input when the voltage falls below a low trigger voltage and is controlled by first and second switch control nodes that follow the voltage and wherein the first switch control node has a greater rate of change than the second switch control node.