Patent ID: 8895403
Filing Date: 2014-11-25
Classification: H01L

Abstract:
1. A method for fabricating a transistor, comprising: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively; wherein the step of defining a first device area on the first insulating layer comprises: sequentially depositing a first semiconductor layer and a first mask layer on the first insulating layer; patterning the first semiconductor layer and the first mask layer to define the first device area; wherein the step of defining a second device area on the first insulating layer comprises: depositing a second semiconductor layer to cover the exposed portion of the first insulating layer, the spacer, and the first mask layer; depositing a second mask layer to fill in a recess over the second semiconductor layer on the exposed portion of the first insulating layer; polishing the second mask layer and the second semiconductor layer to flush with the top of the spacer and the first mask layer; removing the second semiconductor layer on side surfaces of the spacer by using the first mask layer and the second mask layer as a mask; and removing the first mask layer and the second mask layer.