Patent ID: 8513130
Filing Date: 2013-08-20
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming a first layered structure on a base layer in an element area which is delineated by a non-element area of a wafer, and a second layered structure which includes a same layer structure as the first layered structure in the non-element area simultaneously with the forming the first layered structure; covering the first layered structure and the second layered structure with a first insulating film; removing the first insulating film over the second layered structure with patterning the first insulating film; covering the first layered structure, being covered by the first insulating film, with a second insulating film; forming a first aperture portion in the second insulating film in a manner exposing the first layered structure; forming a conductive plug in the first aperture portion; forming a second aperture portion, having a depth different than the first aperture portion, simultaneously with the forming the first aperture portion in a manner exposing the second layered structure; and forming a conductive pattern simultaneously with the forming the conductive plug in the second aperture portion; wherein the non-element area is a scribe line formed on the wafer wherein the wafer is diced along the scribe line.