Patent ID: 7447833
Filing Date: 2008-11-04
Classification: G06F

Abstract:
1. Data storage equipment, comprising: a first storage processor; a second storage processor; and an interconnect coupled between the first and second storage processors, the first storage processor including a processing circuit and a packaged integrated circuit device which has a first set of ports and a second set of ports, the processing circuit of the first storage processor being adapted to: configure the packaged integrated circuit device of the first storage processor to provide (i) communications to a set of storage devices through the first set of ports of the packaged integrated circuit device and (ii) other communications to the second storage processor through the second set of ports of the packaged integrated circuit device; pass communications between the first storage processor and the set of storage devices through the first set of ports of the packaged integrated circuit device; and pass communications between the first storage processor and the second storage processor through the second set of ports of the packaged integrated circuit device; the packaged integrated circuit device being configured to operate concurrently as a SATA initiator through one port and as a SATA target through another port; the second storage processor including another packaged integrated circuit device; and wherein the first and second storage processors are adapted to perform direct memory access (DMA) operations outside of multiple cache mirroring interface (CMI) links to isolate the packaged integrated circuit devices from DMA operations.