Patent ID: 6407689
Filing Date: 2002-06-18
Classification: H03M

Abstract:
A data conversion circuit comprising:a sigma-delta analog-to-digital converter (&Sgr;&Dgr; ADC) configured to receive an input signal and provide data samples, the &Sgr;&Dgr; ADC including a plurality of LA stages coupled in cascade; and a control circuit coupled to the &Sgr;&Dgr; ADC and configured to provide a control signal that selectively disables zero or more of the plurality of &Sgr;&Dgr; stages, the control circuit including one or more detector stages configured to receive the input signal and provide a detected signal, a conditioning circuit coupled to the one or more detector stages, the conditioning circuit configured to receive the detected signal and provide conditioned samples, and a signal processor coupled to the conditioning circuit, the signal processor configured to receive the conditioned samples and provide the control signal.