Patent ID: 6498516
Filing Date: 2002-12-24
Classification: G11C

Abstract:
A bit line write driver with minimized clock skew effect, comprising:a first set of transistors for producing a first output signal, wherein the first set of transistors comprises: a first p-channel transistor; a second p-channel transistor; and a first n-channel transistor; the first p-channel transistor is connected gate to a clock signal, source to a pull-up voltage, and drain to drain with the second p-channel transistor; the second p-channel transistor is connected source to the pull-up voltage, and gate to gate with the first n-channel transistor; the first n-channel transistor is connected gate to an input signal, and source to drain with a pull-down transistor; the pull-down transistor is connected gate to the clock signal, and source to ground; and a second set of transistors for producing a second output signal, wherein the second set of transistors comprises: a third p-channel transistor; a fourth p-channel transistor; and a second n-channel transistor; the third p-channel transistor is connected gate to the clock signal, source to the pull-up voltage, and drain to drain with the fourth p-channel transistor; the fourth p-channel transistor is connected source to the pull-up voltage, and gate to gate with the second n-channel transistor; the second n-channel transistor is connected gate to an inverted input signal, and source to drain with the pull-down transistor; and a first control circuit for controlling whether the first output signal is output from the bit line write driver based on feedback from the second output signal; and a second control circuit for controlling whether the second output signal is output from the bit line write driver based on feedback from the first output signal, wherein the first set of transistors are operatively coupled to the second set of transistors gate to gate, and the first set of transistors are operatively coupled to the second set of transistors drain to source through the first and second control circuits.