Patent ID: 8954644
Filing Date: 2015-02-10
Classification: G06F,Y02D

Abstract:
1. An apparatus for controlling memory, the apparatus adaptively determining order of execution of a plurality of memory access requests, the apparatus comprising: a memory access request buffer unit configured to determine and store memory access request order so that the plurality of memory access requests is processed in order based on input order of the plurality of memory access requests and bank and row information extracted from memory addresses of the memory access requests; a memory access request control unit configured to read the memory access requests from the memory access request buffer unit in the determined order, to distribute the memory access requests to banks, and to transfer the memory access requests in the banks to memory, thereby executing the memory access requests; and a bank control unit configured to store the memory access requests distributed to the banks within a preset number in each of buffer units for respective banks, and to control an operating state of each bank; wherein the memos access request buffer modifies the memory access request order so that memory access requests attempting to access a same row of same bank are successively processed, and wherein the memory access request control unit, when distributing the memory access requests to the banks, determines whether the buffer units of respective banks are not full, and transfers one or more memory access requests to one or more buffer units, even if the memory access requests are located behind in terms of order in the memory access request buffer unit, which are not full.