Patent ID: 6423593
Filing Date: 2002-07-23
Classification: C23C,H01L

Abstract:
A process for manufacturing a semiconductor integrated circuit device comprising:(a) a step of forming a MISFET for memory cell selection on a main surface of a semiconductor substrate; (b) a step of forming a plug electrically connected to a source/drain region of said MISFET for memory cell selection; (c) a step of forming a silicon oxide film over said plug; (d) a step of forming a hole getting to a surface of said plug in said silicon oxide film; (e) a step of forming an Ru film over a side wall and a bottom of said hole by causing an organic compound of Ru and an oxidizing agent, a gasification flow rate of the organic compound of Ru being not less than 5% of a flow rate of the oxidizing agent; (f) a step of forming a capacity insulating film over said Ru film; and (g) a step of forming an upper electrode on said capacity insulating film.