Patent ID: 9081582
Filing Date: 2015-07-14
Classification: G06F

Abstract:
1. An apparatus comprising: a microcode store having a microcoded instruction implementation; a central processing unit in communication with the microcode store, the central processing unit utilizing transport triggered architecture and configured to execute microcoded instructions that allow a single instruction to be implemented as multiple instructions; a control unit configured to load the microcoded instruction implementation from the microcode store using a number of useful entry points in the microcoded instruction implementation; a program counter of the central processing unit, the program counter configured to receive the number of useful entry points from the control unit to induce the central processing unit to perform a sequence equivalent to a subroutine call into the microcode store; the control unit being further configured to determine whether the microcoded instruction implementation is a microcoded type instruction and, responsive to a determination that the microcoded instruction implementation is the microcoded type instruction, use a branch and link operation to save a state of a current execution point in the microcode instruction implementation, wherein the control unit is further configured to repeat loading the microcoded instruction implementation after using the branch and link operation, and the program counter is further configured to repeat receiving the number of useful entry points after the branch and link operation; and the control unit being further configured to, responsive to a determination that the microcoded instruction implementation is a non-microcoded type instruction, transfer data between a first functional unit and a second functional unit without using the branch and link mechanism, and wherein the control unit is further configured to load a next instruction in the microcoded instruction implementation after transferring the data.