Patent ID: 6247098
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A method of maintaining cache coherency in a multi-processor computer system having a plurality of processing units, each processing unit having at least one cache, comprising the steps of:sourcing a modified value corresponding to a memory block of a system memory device from a first cache line of a first processing unit to a second cache line of a second processing unit;determining whether the second cache line supports a first coherency state to indicate that the second cache line contains the modified value and that the modified value has not been written to the memory block of the system memory device; andassigning the first coherency state to the second cache line if the second cache line supports the first coherency state and, if not, then assigning a second coherency state to the second cache line to indicate that the second cache contains a shared copy of the modified value and that the modified value has been written to the memory block of the system memory device.