Patent ID: 7423453
Filing Date: 2008-09-09
Classification: G06F,H03K

Abstract:
1. A circuit layout in an integrated circuit, the circuit layout comprising: n1 rows of switches, each row of the n1 rows of switches organized along a second dimension, wherein the switches of each row are organized along a first dimension; a first set of conductors comprising i1 conductors organized in proximity along a plurality of tracks in the second dimension distributed over the n1 rows, wherein y number of the first set of conductors are connected to a corresponding y number of the switches in each of the n1 rows for y ranging between (i1−n1+1) to i1; and a second set of conductors comprising i2 conductors organized in n1 sets of non-overlapping conductors, each of the n1 sets of non-overlapping conductors having approximately (i2/n1) number of the second set of conductors along the plurality of tracks in the second dimension distributed over a respective row of the n1 rows, wherein the approximately (i2/n1) number of the second set of conductors are connected to the y number of the switches of the respective row.