Patent ID: 6649934
Filing Date: 2003-11-18
Classification: G02F,H01L

Abstract:
A thin film transistor array panel for a liquid crystal display, comprising:an insulating substrate, a gate wire formed on the insulating substrate, and including a plurality of gate lines, a plurality of gate electrodes connected to the gate lines and a plurality of gate pads connected to the ends of the gate lines; a gate insulating layer covering the gate wire and having contact holes exposing the gate pads; a semiconductor layer formed on the gate insulating layer; a data wire having a double-layered structure including a lower conductor layer and an upper conductor layer and including a plurality of data lines intersecting the gate lines, a plurality of source electrodes connected to the data lines, a plurality of drain electrodes located opposite to the source electrodes with respect to the gate electrodes and separated from the source electrode, and a plurality of data pads connected to the data lines and having a portion of the lower conductor layer that is not covered by the upper conductor layer; a plurality of redundant gate pads covering the gate pad through the contact hole and having a portion of the lower conductor layer that is not covered by the upper conductor layer; a plurality of pixel electrodes connected to the drain electrodes and having a portion of the lower conductor layer that is not covered by the upper conductor layer; and a passivation layer formed on the data wire, the semiconductor layer, the gate insulating layer and the substrate, and having a plurality of first openings to fourth openings exposing the pixel electrodes, portions of the gate insulating layer on the gate lines between the neighboring data lines, the redundant gate pads and the data pads, respectively; wherein the upper conductor layer is interposed only between the passivation layer and the lower conductor layer.