Patent ID: 6246294
Filing Date: 2001-06-12
Classification: H03L

Abstract:
A phase-locked loop system for generating an output signal having low jitter, the system comprising:a phase frequency detector, coupled to receive an input signal having an input frequency and an input phase, for generating an up signal or a down signal;a charge pump, coupled to the phase frequency detector, for generating a charging controlled voltage signal in response to receiving the up signal and for generating a discharging controlled voltage signal in response to receiving the down signal;a voltage controlled oscillator, coupled to the charge pump, for generating an output signal that is rising in response to receiving the voltage charge signal and for generating an output signal that is falling in response to receiving the voltage discharge signal; anda divider, coupled to the voltage controlled oscillator and the phase frequency detector, for generating a feedback signal having a feedback phase, the phase frequency detector generating the up signal in response to the input phase being before the feedback phase and generating the down signal in response to the input phase being after the feedback phase,wherein the voltage controlled oscillator includesa voltage regulator, coupled to receive as input signals a reference voltage and an output signal of the voltage regulator through a feedback loop, for generating a voltage signal matching the input frequency,a low-pass filter, coupled to the voltage regulator, for producing a clean voltage signal, anda ring oscillator, coupled to the low-pass filter, for receiving the clean voltage signal and generating the output signal.