Patent ID: 7956421
Filing Date: 2011-06-07
Classification: G06F,H01L

Abstract:
1. A cross-coupled transistor configuration within a semiconductor chip, comprising: a first P channel transistor including a first gate electrode defined in a gate level of a chip; a first N channel transistor including a second gate electrode defined in the gate level of the chip, wherein the second gate electrode of the first N channel transistor is electrically connected to the first gate electrode of the first P channel transistor; a second P channel transistor including a third gate electrode defined in the gate level of a chip; a second N channel transistor including a fourth gate electrode defined in the gate level of the chip, wherein the fourth gate electrode of the second N channel transistor is electrically connected to the third gate electrode of the second P channel transistor; and wherein each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node, wherein each of the first, second, third, and fourth gate electrodes corresponds to a portion of an associated gate level feature defined within a corresponding gate level feature layout channel, wherein each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel, wherein both the first and second gate electrodes are formed from a single gate level feature, and wherein the third gate electrode is electrically connected to the fourth gate electrode through at least one electrical conductor defined within a chip level other than the gate level.