Patent ID: 6410445
Filing Date: 2002-06-25
Classification: G01N,G03F

Abstract:
A method for fabricating integrated sensor arrays on a common substrate, comprising a first step of developing a resist mask on the surface of the substrate, wherein the resist mask is provided with openings for all areas of the substrate where a deposition is to take place in subsequent steps; a second step in which a first shadow mask is located over the resist mask from the first step and a first deposition of materials takes place in which the first shadow mask screens and protects all openings in the resist mask that are not to be subjected to deposition leaving only those where the deposition is to take place; a third step in which a second shadow mask is located over the resist mask and a second deposition takes place in areas of the openings in the resist mask on the substrate that are not screened by said second deposition; subsequent steps in which additional shadow masks are used to expose the desired openings in the resist mask to a treatment; and a last step in which after all depositions have been carried out at different openings in the resist mask the last shadow mask is removed and then the resist mask is removed.