Patent ID: 7995401
Filing Date: 2011-08-09
Classification: G11C

Abstract:
1. A method of erasing a page in a nonvolatile memory array having plural strings of memory cells on a substrate, wordlines across the strings to pages of memory cells and a pass transistor applying a voltage to each wordline, the method comprising: in each unselected block, disabling each pass transistor; in each selected block: applying a select voltage to the pass transistor; and applying an unselect voltage to the pass transistor; and applying a substrate voltage to the substrate of the selected and unselected blocks; each wordline of each unselected block floating to prevent erasure, a resulting voltage of each selected wordline being substantially the same as the select voltage and causing the page of memory cells of the selected wordline to erase, and a resulting voltage of each unselected wordline being substantially the same as the unselect voltage and preventing erasure of the page of memory cells of the unselected wordline.