Patent ID: 8836708
Filing Date: 2014-09-16
Classification: G06F,G06T

Abstract:
1. A device for processing a data stream comprising matrices of Nl rows by Nc columns of data, said device comprising: K computation tiles; and interconnection means for transferring said data stream between the computation tiles, wherein at least one of the computation tiles comprises: one or more control units to provide instructions to be executed on a subset of Vl rows by (n+Vc−1) columns of said matrix of data, said subset being called a neighborhood; n processing units, each processing unit executing the instructions received from a control unit on the data stored in a neighborhood register when the accesses to neighborhood registers are authorized; a storage unit to arrange the data of the stream in the form of neighborhoods of Vl rows by (n+Vc−1) columns of data, the storage unit comprising a block of shaping memories comprising Vl×Nc memory cells arranged according to a mesh of Vl rows and Nc columns and a block of neighborhood registers having a number equal to Vl×(n+Vc−1) of neighborhood registers, wherein said storage unit is configured in such a way that, at each clock, cycle, a column of Vl data of a block of shaping memories is copied to a block of neighborhood register and the accesses to neighborhood registers for processing units are disabled during the copying of a new column of data; and an input/output unit to convey the data stream between the interconnection means and the storage unit on the one hand, and between the processing units and the interconnection means on the other hand.