Patent ID: 6157587
Filing Date: 2000-12-05
Classification: G11C

Abstract:
In a random access memory having at least one array that includes a plurality of folded bit lines, a data sensing circuit, comprising:a sense amplifier coupled between at least one folded bit line pair for amplifying a differential signal between the bit line pair;a pair of passgate transistors responsive to a passgate clock signal for coupling the amplified differential signal from said sense amplifier to a pair of input/output (I/O) lines;a first latching circuit coupled between the folded bit line pair being responsive to the passgate clock signal arranged to latch at least one of said bit lines to a first voltage in response to the amplified differential signal between the bit lines; anda second latching circuit coupled between the pair of I/O lines arranged to latch at least one of the I/O lines to a second voltage in response to the amplified differential signal between the bit lines.