Patent ID: 6581140
Filing Date: 2003-06-17
Classification: G06F

Abstract:
An apparatus comprising a memory system coupled to provide information responsive to receiving a requested address corresponding to the information, the memory system including:N information way arrays, each information array including a plurality of information entries for storing information; and N tag way arrays corresponding to the N information way arrays, each tag way array including a plurality of tag entries, each tag entry including a predictive hit field for storing predictive hit information based upon previous accesses of the memory system, wherein each tag way array is coupled to provide a first portion of tag information from a tag entry identified by an index portion of the requested address and is coupled to provide indexed predictive hit information of the tag entry identified by the index portion of the requested address; and wherein the apparatus further comprises a cache controller coupled to provide a predictive hit output responsive to receiving a first portion of the requested address, the first portion of tag information, and the indexed predictive hit information.