Patent ID: 6876025
Filing Date: 2005-04-05
Classification: H01L

Abstract:
1. A memory cell, comprising: a substrate formed with a substantially rectangular trench hole defining a lower region and an upper region, and a horizontal bit line extending in a bit line direction; a trench capacitor formed at said lower region of said trench hole, said trench capacitor having: a vertical selection transistor formed at said upper region of said trench hole, said selection transistor having: a horizontally running word line with gate region laterally adjoining said channel region, partially or completely enclosing said channel region, and being electrically insulated therefrom, said horizontally running word line with gate region being formed perpendicular to said bit line running horizontally thereabove, and an extent of said trench hole in a word line direction being at least 1.5 times as large as an extent of the trench hole in the bit line direction; said vertically running channel region of said selection transistor extending through said horizontally running word line with gate region to said bit line above said channel region.