Patent ID: 6066523
Filing Date: 2000-05-23
Classification: H01L

Abstract:
A method for fabricating a semiconductor device having a triple well, comprising steps of:forming an element isolation oxide film on a semiconductor substrate of a first conductive type;forming a first photoresist film pattern on said semiconductor substrate to expose a portion designated as a second conductive type well on said semiconductor substrate;sequentially forming a second conductive type well implantation region, an inter second conductive type well implantation region, and a first conductive type channel deep implantation region upon implanting a second conductive type impurity ions in said exposed portion designated as said second conductive type well of said semiconductor substrate using said first photoresist film pattern as a mask;removing said first photoresist film pattern;forming a second photoresist film pattern on said semiconductor substrate to expose a portion designated as a first conductive type well and a R-well on said semiconductor substrate;sequentially forming a first conductive type well implantation region, an inter first conductive type well implantation region, and a second conductive type channel deep implantation region upon implanting impurity ions of the first conductive type in said exposed portion of said semiconductor substrate using said second photoresist film pattern;removing said second photoresist film pattern; andsequentially forming a first conductive type well, a second conductive type well and a R-well in said semiconductor substrate by activating impurity ions of each implantation region by means of carrying out a thermal process, wherein said first conductive type well is formed in both said second conductive type well and said R-well is said second conductive type well.