Patent ID: 9153958
Filing Date: 2015-10-06
Classification: H01L,H02H,H03K

Abstract:
1. An electrostatic discharge (ESD) protection device for an integrated circuit (IC) device, the ESD protection device comprising: a bigFET configured to conduct an ESD current during an ESD event; and a trigger device configured to trigger the bigFET during the ESD event, the trigger device comprising: that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET; wherein the drain terminal or the source terminal of the bigFET is connected to a supply node to which a power supply voltage of the IC device is applied, wherein the source terminal or the drain terminal of the bigFET is connected to a second node to which a second voltage is applied, and wherein the second voltage is lower than the power supply voltage of the IC device, wherein the keep-on latch comprises: