Patent ID: 8724383
Filing Date: 2014-05-13
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a plurality of memory units each having a memory string which comprises memory transistors and select transistors; a plurality of bit lines, one end of each of the memory units being connected to one of the plurality of bit lines; a plurality of word lines connected to the memory transistors; a plurality of control gate lines connected to the select transistors; and a control circuit configured to control: an erase operation to erase data of the memory transistors; a correction write operation moving an erase threshold level of the memory transistors to a positive threshold level after the erase operation; and a correction write verify operation determining whether or not a threshold level of a result of the correction write operation reaches a first value, in the correction write operation, the control circuit executing the correction write operation with respect to a group of the plurality of memory units connected to a common one of the bit lines and sequentially executing the correction write verify operation with respect to the group of the plurality of memory units in which the correction write operation is executed.