Patent ID: 6819150
Filing Date: 2004-11-16
Classification: G06F,H03L,H04W,Y02D

Abstract:
A device for reducing power consumption, comprising:a first clocking device for generating a first clocking signal, a second clocking device for generating, a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the first select or second control signals, said synchronizing device generates a synchronized signal without a glitch therefrom wherein said synchronized signal corresponds to either the first or second clocking signals, wherein said synchronizer device is divided into a first bi-stable circuit coupled to a second bi-stable circuit wherein said first bi-stable circuit sends a sync signal to prevent a glitch occurring to the second bi-stable circuit which generates the synchronized signal therefrom.