Patent ID: 7154145
Filing Date: 2006-12-26
Classification: H01L

Abstract:
1. An insulated gate transistor comprising: a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface; a first semiconductor layer of a second conductivity type shaped like a well which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first side diffusion region, a second side diffusion region facing said first side diffusion region and a flat region which is interposed between said first side diffusion region and said second side diffusion region and comprises a bottom surface forming a substantially flat surface substantially parallel to said first main surface; a main trench passing from said first main surface through a bottom surface of said first semiconductor layer, said main trench comprising a bottom portion situated just below said first semiconductor layer in said semiconductor substrate; an insulating film formed on said main trench so that each of said bottom portion and a side surface of said main trench is entirely covered with said insulating film; a control gate formed over said insulating film and filled into said main trench; a second semiconductor layer of said first conductivity type extending from said first main surface toward an interior of said flat region of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and are vertically interposed between said top surface and said bottom surface of said second semiconductor layer; a first main electrode formed on said top surface of said second semiconductor layer and said first side diffusion region of said first semiconductor layer; a fourth semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate; and a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said fourth semiconductor layer, wherein said first side surface of said second semiconductor layer is joined to said side surface of said main trench, said first side diffusion region is situated just above said fourth semiconductor layer, a depth of said first side diffusion region between said first main surface and a bottom surface of said first side diffusion region continuously and smoothly changes while gradually decreasing from a position of the largest depth as a distance to a joint on said first main surface between said first main electrode and a top surface of said first side diffusion region decreases, and a depth of said second side diffusion region between said first main surface and a bottom surface of said second side diffusion region continuously and smoothly changes while gradually decreasing from a position of the largest depth as a distance to a joint on said first main surface between said first main electrode and a top surface of said second side diffusion region decreases.