Patent ID: 6839831
Filing Date: 2005-01-04
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a register file comprising a plurality of registers, each of said plurality of registers having a corresponding register number; a first functional unit group connected to said register file and including a plurality of first functional units each having an output and further including an output multiplexer having a plurality of inputs receiving respective outputs of said first functional units and an output, said first functional unit group responsive to an instruction to a second functional unit group connected to said register file and including a plurality of second functional units each having an output and further including an output multiplexer having a plurality of inputs receiving respective outputs of said second functional units and an output, said second functional unit group responsive to an instruction to a first comparator receiving an indication of said first operand register number of a current instruction and an indication of said second destination register number of an immediately preceding instruction, said first comparator indicating whether said first operand register number of said current instruction matches said second destination register number of said immediately preceding instruction; and a first register file bypass multiplexer connected to said register file, said first functional unit group, said second functional unit group and said first comparator, said first register file bypass multiplexer having a first input receiving data from said register corresponding to said first operand register number of said current instruction, a second input connected to said output of said second functional unit group and an output supplying an operand to said operand input of said first functional unit group, said first multiplexer selecting said data from said register corresponding to said first operand number of said current instruction if said first comparator fails to indicate a match and selecting said output of said second functional unit group if said first comparator indicates a match; said first functional units of said first functional unit group and said second functional units of said second functional unit group selected whereby functions often executed simultaneously within the same instruction cycle have corresponding functional units placed in different functional unit groups and functions which are not often executed together within the same instruction cycle have corresponding functional units placed in the same functional unit group.