Patent ID: 6510537
Filing Date: 2003-01-21
Classification: G06F

Abstract:
A semiconductor memory device comprising:a memory cell array for storing a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits, the plurality of data bits being divided into at least a first and second data groups and the plurality of check bits being divided into at least first and second check bit groups; means for reading out the first data group and the first check bit group from the memory cell array; means for reading out the second data group and second check bit group from the memory cell array; means for correcting a first error in the first data group; means for correcting a second error in the second data group; and input/output circuit for outputting the first and second data groups alternatively outputted from the means for correcting the first and second errors; wherein the means for correcting a first error sequentially receives the first data group and the first check bit group; wherein the means for correcting a second error sequentially receives the second data group and the second check bit group simultaneously with the means for correcting a first error sequentially receiving the first data group and the first check bit group; wherein the means for correcting a first and second errors generates first and second syndromes respectively corresponding to the first and the second data group; and wherein the means for correcting a first and second errors corrects the first error in the first data group and the second error in the second data group responsive to the first and the second syndromes, respectively; wherein the means for correcting a first error and the means for correcting a second error comprise: a first syndrome generator for sequentially receiving the first data group and the first check bit group and generating first syndrome bits responsive thereto; a second syndrome generator for sequentially receiving the second data group and the second check bit group and generating second syndrome bits responsive thereto; a detector for alternatively receiving the first and the second syndrome bits from the first and the second syndrome generator, decoding the first syndrome bits to detect the first error in the first data group and the second syndrome bits to detect the second error in the second data group and generating a first signal indicative of the presence or absence of the first error and a second signal indicative of the presence or absence of the second error; and a corrector for alternatively receiving the first and second data groups, the corrector correcting the first error in the first data group responsive to the first signal indicative of the presence or absence of the first error and the second error in the second data group responsive to the second signal indicative of the presence or absence of the second error.