Patent ID: 8907826
Filing Date: 2014-12-09
Classification: H03M

Abstract:
1. A method for estimating capacitance weight errors of a digital to analog converter (DAC) in a successive approximation analog to digital converter (ADC) including a comparator, a capacitor set and a switch set, the capacitor set including a primary capacitor array and a secondary capacitor array, the primary capacitor array including a plurality of first capacitors and an auxiliary capacitor, and the secondary capacitor array including a low-weighted capacitor array having a plurality of known second capacitors, the method comprising: (A) pre-charging at least one of the first and auxiliary capacitors in the primary capacitor array by a first reference voltage, wherein the step (A) comprises: (B) redistributing electric charges to the first and auxiliary capacitors in the primary capacitor array and to the second capacitors in the secondary capacitor array, by using the at least charged one of the first and auxiliary capacitors, wherein the step (B) comprises: (C) using an output of an output terminal of the comparator to generate bit-cycling signals for controlling the second capacitors in the secondary capacitor array and making voltages of the first and auxiliary capacitors in the primary capacitor array successively approximate to the first reference voltage, so as to respectively acquire a digital estimation value of capacitance weight, and to calculate a capacitance weight error estimation value of corresponding one of the first and auxiliary capacitors according to the acquired digital estimation value of the capacitance weight, wherein the digital estimation value of the capacitance weight is acquired by the following function: wherein dc wherein the secondary capacitor array further comprises the attenuation capacitor connected with the low-weighted capacitor array in series, a first terminal of the attenuation capacitor is connected to first terminals of the first and auxiliary capacitors, a second terminal of the attenuation capacitor is connected to first terminals of the second capacitors, the first terminals of the first, auxiliary and attenuation capacitors are connected to a first input terminal of the comparator, a second input terminal of the comparator is supplied with the first reference voltage, the switch set is coupled to the second terminals of the first, second and auxiliary capacitors for controlling the first, second and auxiliary capacitors to be supplied with the first reference voltage or with the second reference voltage, a capacitance weight of the attenuation capacitor is 1, capacitance values of the first and auxiliary capacitors are the same as capacitance values of the second capacitors, capacitance weights of the second capacitors are binary-weighted, and the capacitance value of the auxiliary capacitor is smaller than an equivalent capacitance value of the secondary capacitor array.