Patent ID: 7184321
Filing Date: 2007-02-27
Classification: G06F,G11C,H01L,Y02D

Abstract:
1. A data processor on a semiconductor substrate comprising: a nonvolatile memory; and a central processing unit, wherein the nonvolatile memory array includes a plurality of word lines and a plurality of nonvolatile memory cells, each of which is coupled with a corresponding word line, wherein the central processing unit has a plurality of operation modes including a first operation mode and a second operation mode, wherein the nonvolatile memory is adapted to perform a rewrite operation under control of the central processing unit in the first operation mode, and the nonvolatile memory is adapted to perform a rewrite operation under control of a separate writing apparatus, externally connectable to the data processing unit, in the second operation mode, and wherein in an erase operation performed before the rewrite operation, the nonvolatile memory cells are supplied a negative voltage via the word line.