Patent ID: 6713343
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A process of manufacturing a semiconductor device, comprising:(a) forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of said semiconductor substrate, wherein each of said first and second MISFETs has a gate electrode, and source and drain regions on a main surface of a semiconductor substrate; (b) forming silicide layers having a metal with high melting point over said source and drain regions of said second MISFET; (c) forming a first insulating film over said first and second MISFETs; (d) forming a second insulating film greater than said first insulating film in film thickness over said first insulating film; (e) forming a through hole in said second insulating film, said through hole located on the first MISFET and exposing said surface of said first insulating film; (f) forming a first metal film oriented in a (002) plane over inner walls of said through hole and over said surface of said first insulating film in said through hole, (g) depositing a tantalum oxide film over said first metal film; (h) thermally treating said tantalum oxide film so as to form a polycrystalline dielectric film; and (i) forming a second metal film over the dielectric film.