Patent ID: 7348237
Filing Date: 2008-03-25
Classification: G11C,H01L

Abstract:
1. A method for forming a NOR flash memory array, comprising: forming a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein forming the number of vertical pillars includes forming the number of vertical pillars to serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couples to the sourceline in a shared trench.