Patent ID: 8677047
Filing Date: 2014-03-18
Classification: G06F

Abstract:
1. An interface circuit, comprising: a host controller and a parallel advanced technology attachment (ATA) bus each located on a host side of the interface circuit; a storage device controller and a serial ATA bus each located on a device side of the interface circuit; and a bridge circuit selectively configurable to operate as a host bridge or a device bridge based on a mode select signal, wherein the bridge circuit is configured to i) when configured to operate as a host bridge, convert serial ATA information received via the serial ATA bus to parallel ATA information to be provided to the parallel ATA bus, and ii) when configured to operate as a device bridge, convert parallel information received via the parallel ATA bus to serial ATA information to be provided to the serial ATA bus, wherein the host side of the interface circuit corresponds to a host side of the bridge circuit, the device side of the interface circuit corresponds to a device side of the bridge circuit opposite the host side of the bridge circuit, and the bridge circuit is located between the host controller and the storage device controller.