Patent ID: 7836287
Filing Date: 2010-11-16
Classification: G06F

Abstract:
1. A processor, comprising: an instruction cache configured to store instructions, wherein an instruction is fetched from said instruction cache; a buffer, wherein said buffer comprises a plurality of entries, wherein each of said plurality of entries in said buffer comprises an address of a branch instruction, a plurality of instructions beginning at a target address of said branch instruction, prediction information for any of said plurality of instructions that are branch instructions and an address of a next fetch group, wherein an entry of said plurality of entries in said buffer is indexed using bits from said instruction fetched from said instruction cache; a first selection mechanism coupled to said instruction cache and said buffer, wherein said selection mechanism is configured to select said plurality of instructions beginning at said target address of said branch instruction in said indexed entry if an address of said instruction fetched from said instruction cache matches with said address of said branch instruction in said indexed entry of said buffer; a decode logic unit coupled to said first selection mechanism, wherein said decode logic unit is configured to determine if any of said plurality of instructions selected is a branch instruction if said address of said instruction fetched from said instruction cache matches with said address of said branch instruction in said indexed entry of said buffer; and a second selection mechanism coupled to said decode logic unit, wherein said second selection mechanism is configured to load a displacement and an address of a first of said plurality of instructions selected in a first and a second register, respectively, wherein said first of said plurality of instructions selected is a branch instruction predicted taken.