Patent ID: 6159801
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A method of forming a split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell comprising the steps of:providing a semiconductor substrate;forming a pad oxide layer over said substrate;forming a first nitride layer over said pad oxide layer;forming and patterning a first photoresist layer over said first nitride layer to define active regions in said substrate;forming a trench in said substrate by etching through patterns in said first photoresist layer and through said first nitride layer;removing said first photoresist layer;forming a conformal lining on the inside walls of said trench;depositing isolation oxide inside said trench to form shallow trench isolation (STI);performing chemical-mechanical polishing of said substrate;removing said first nitride layer;removing said pad oxide layer;forming and patterning a second photoresist layer to define a three-dimensional coupling region in said trench;etching back said oxide in said trench, thus forming a three-dimensional coupling source region in the upper portion of said trench to allow three-dimensional flow of electrons from said coupling region into said floating gate of said cell;removing said second photoresist layer;forming sacrificial oxide layer over said substrate;removing said sacrificial oxide layer;growing gate oxide layer over said substrate, including the sidewalls of said three-dimensional coupling region in said trench;forming first polysilicon layer over said substrate filling said three-dimensional coupling region in said upper portion of said trench;forming a second nitride layer over said substrate;forming and patterning a third photoresist layer over said second nitride layer to define cell area and form floating gate region in said substrate;etching through said patterning in said third photoresist layer into said second nitride layer until portions of said first polysilicon layer are exposed;removing said third photoresist layer;using patterned said second nitride layer as a mask, oxidizing said exposed portions of said first polysilicon layer to form poly-oxide;removing said second nitride layer;using said poly-oxide as a hard mask, etching said first polysilicon layer to form floating gate;forming inter-poly oxide over said substrate;forming a second polysilicon layer over said inter-poly oxide;forming and patterning a fourth photoresist layer over said substrate to define control gate region over said substrate;etching through said patterning in said fourth photoresist layer into said second polysilicon layer to form said control gate region;removing said fourth photoresist layer;forming and patterning a fifth photoresist layer over said substrate to define source implant region in said substrate;performing source implantation;removing said fifth photoresist layer;forming spacers on side-walls of said control gate; andforming drains of said split-gate flash memory cell.