Patent ID: 8855242
Filing Date: 2014-10-07
Classification: G11C,H04L

Abstract:
1. A data receiving circuit comprising: a generating unit that generates a reference clock and multiple clocks with phases different from that of the reference clock step by step, the generating unit including; a DLL (Delay Locked Loop) circuit that outputs multiple signals with phases which are changed from a phase of a received clock signal step by step; and a selector that selects the reference clock and the multiple clocks from the multiple signals output from the DLL circuit, and outputs the selected signals, a plurality of acquiring units that acquire data from a received data signal by using different clocks from one another out of the reference clock and the multiple clocks generated by the generating unit; a determining unit that determines whether there is inconsistent data, among data acquired by using the multiple clocks, that is not equal to data acquired by using the reference clock; and a correcting unit that, when the determining unit has determined that there is the inconsistent data, determines a direction of a phase of a clock used in acquisition of the inconsistent data based on the phase of the reference clock, counts a number of inconsistent data existing in the direction, and sends to the generating unit a phase correction signal indicating the number of inconsistent data and the direction, wherein when having received the phase correction signal, the selector selects, as a new reference clock, a signal with a phase shifted from phase of a signal selected as the last reference clock by the same steps as the number indicated by the phase correction signal in a direction opposite to the direction indicated by the phase correction signal, and the multiple clocks.