Patent ID: 7294559
Filing Date: 2007-11-13
Classification: H01L

Abstract:
1. A wafer dicing process of optical electronic packing to establish a backside dicing reference coordinate, said wafer dicing process comprising: providing a first wafer with a first upper surface and a first lower surface, wherein said first wafer is a glass wafer; providing a second wafer with a second upper surface and a second lower surface; etching through part of said second wafer to form a first flat and a second flat perpendicular to each other; laminating said first wafer on said second wafer, wherein said second upper surface of said second wafer faces said first lower surface of said first wafer; providing a third wafer with an active surface; laminating said third wafer under said second wafer, wherein said active surface of said third wafer faces said lower surface of said second wafer; cutting through said first wafer from said first upper surface along said first flat and said second flat of said second wafer by a first dicing saw to reveal said third wafer; and cutting through said third wafer from said active surface along said first flat and said second flat of said second wafer by a second dicing saw to form a first reference axis and a second reference axis perpendicular to each other to establish said backside dicing reference coordinate, whereby said first flat and said second flat of said second wafer serve as a guide for cutting said first wafer and said third wafer.