Patent ID: 8503262
Filing Date: 2013-08-06
Classification: G11C

Abstract:
1. A semiconductor device comprising: a first circuit that generates a refresh command in a predetermined cycle asynchronous with outside; a second circuit that generates a refresh address in response to the refresh command and updates the refresh address and outputs the refresh address; a third circuit that stores a relief address; a fourth circuit that counts number of generation of the refresh command and activates an interrupt signal when a count value thereof reaches a predetermined value; a fifth circuit that selects the refresh address output from the second circuit when the interrupt signal is in an inactive state, and selects the relief address stored in the third circuit when the interrupt signal is in an active state; and a sixth circuit that performs a refresh operation to memory cells specified by the refresh address or the relief address selected by the fifth circuit, wherein the second circuit temporarily stops updating the refresh address in response to activation of the interrupt signal.