Patent ID: 6972429
Filing Date: 2005-12-06
Classification: H01L

Abstract:
1. A chalcogenide random access memory, comprising: a substrate; a first dielectric layer disposed on a surface of the substrate; a bottom electrode disposed within the first dielectric layer; a top electrode disposed on the first dielectric layer and in a position to correspond with the bottom electrode; a second dielectric layer disposed between the first dielectric layer and the top electrode; a chalcogenide block disposed inside the second dielectric layer between the top electrode and the bottom electrode, wherein the chalcogenide block comprising: a non-modified region, wherein the contact area between the non-modified region and the bottom electrode is smaller than the contact area between the non-modified region and the top electrode; and a modified region surrounding the non-modified region, wherein the modified region has a lower conductivity than the non-modified region.