Patent ID: 9001346
Filing Date: 2015-04-07
Classification: H04N

Abstract:
1. A signal processing circuit configured to operate in at least a first mode and a second mode consuming relatively less power than the first mode, the signal processing circuit comprising: a timing controller including, a reference clock generator configured to generate a reference clock signal irrespective of whether the timing controller is operating in the first mode or the second mode, a plurality of first signal generators configured to generate, based on the reference clock, first control signals only if the signal processing circuit is operating in the first mode, a plurality of second signal generators configured to generate, based on the reference clock, second control signals if the signal processing circuit is operating in any one of the first mode and the second mode, and a mode selector to select and shift an operating mode of the signal processing circuit between the first mode and the second mode; and a data transmitter configured to transmit digital image data, a line synchronization signal and a differential clock signal to an image processing unit based on at least one of the second control signals such that the image processing unit receives and processes the line synchronization signal and a differential clock signal irrespective of whether the signal processing circuit is operating in the first mode or the second mode.