Patent ID: 9105617
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A method, comprising: forming a layer of gate electrode material above first and second spaced-apart active regions of a semiconductor substrate that are separated by an isolation region formed in said substrate; performing at least one first etching process on said layer of gate electrode material so as to define an opening positioned above said isolation region, wherein said opening in said layer of gate electrode material defines opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively; forming a line-end protection layer in said opening on at least an entirety of each of said opposing first and second end face surfaces; performing at least one second etching process on said patterned layer of gate electrode material, wherein said at least one second etching process defines opposing sidewall surfaces for each of said first and second spaced-apart gate electrode structures; and with said line-end protection layer in contact with said opposing first and second end face surfaces, forming a sidewall spacer adjacent at least said opposing sidewall surfaces of each of said first and second spaced-apart gate electrode structures but not adjacent said opposing first and second end face surfaces having said line-end protection layer positioned thereon.