Patent ID: 7733697
Filing Date: 2010-06-08
Classification: G11C

Abstract:
1. An electrically programmable memory including: an array of a plurality of memory cells arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks, each memory block including a plurality of memory pages and each memory page including a plurality of columns of memory cells; means for receiving an address corresponding to a respective memory block having a memory page to be read or written; selecting means for selecting an addressed memory block; means for detecting a failure of the addressed memory block; and a page buffer for reading/programming the memory page corresponding to the received address, wherein the means for detecting a failure includes: a plurality of registers, each register corresponding to a respective memory block and storing an indication of the failure of the respective memory block; and means for reading the register corresponding to the addressed memory block in response to the receiving of the address, in that the page buffer includes the means for reading the register corresponding to the addressed memory block, and in that the programmable memory further includes at least one redundant memory block of memory cells including redundant memory columns, the selecting means selecting a single redundant memory block having three or more redundant memory columns of memory cells to replace the addressed memory block in response to the reading of the indication of the failure.