Patent ID: 8508274
Filing Date: 2013-08-13
Classification: H03K

Abstract:
1. A duty correction circuit comprising: a clock buffer configured to buffer an input clock and generate a buffer clock; a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock; a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock; and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the is duty information and the frequency information, wherein the current control block comprises: a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions, wherein a total amount of current flowing through the plurality of first current paths is controlled in response to the frequency information, and a variation in the total amount of current flowing through the plurality of first current paths with respect to a variation in the frequency information is changed according to a frequency domain.