Patent ID: 7729191
Filing Date: 2010-06-01
Classification: G06F,G11C

Abstract:
1. A method of controlling the operation of a memory device, comprising: receiving a write enable signal, a row address strobe signal and column address strobe signal at the memory device regardless of whether either a clock enable signal or a chip select signal is received at the memory device, each of the write enable, row address strobe and column address strobe signals having either a first logic level or a second logic level; decoding the write enable, row address strobe and column address strobe signals to determine memory commands corresponding to a plurality of respective combinations of different logic levels of the write enable, row address strobe and column address strobe signals, at least one of the determined memory commands being a reduced power command and at least one of the determined memory commands being a no operation command, a combination of logic levels of the write enable, row address strobe and column address strobe signals decoded to determine the reduced power command differing from a combination of logic levels of the write enable, row address strobe and a column address strobe signals decoded to determine the no operation command only in a logic level of the write enable signal; and performing an operation in the memory device corresponding to the determined memory command.