Patent ID: 8450168
Filing Date: 2013-05-28
Classification: H01L

Abstract:
1. A method, comprising: forming a barrier layer on an insulator layer of a CMOS structure; forming a top plate and a bottom plate over the barrier layer; forming a ferro-electric material between the top plate and the bottom plate; forming a first encapsulating layer over the top plate, the bottom plate, and the ferro-electric material; etching a portion of the first encapsulating layer and a portion of the bottom plate; forming a second encapsulating layer on the first encapsulating layer and any exposed surfaces of the barrier layer and the bottom plate that become exposed when the first encapsulating layer is etched; and forming at least one first contact to the top plate through the first encapsulating layer and the second encapsulating layer and at least one second contact to the bottom plate through the second encapsulating layer, wherein at least the first contact to the top plate and a third contact to the CMOS structure are in electrical connection through a common wire; and the at least one first contact to the top plate is a first metal and the third contact to the CMOS structure is a second metal, different from the first metal.