Patent ID: 9117826
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a wiring substrate including a first surface, a plurality of bonding leads formed on the first surface, a first alignment mark formed on the first surface, a second surface opposite to the first surface, and a plurality of lands formed on the second surface and electrically connected with the bonding leads, respectively; (b) after the step (a), arranging a first semiconductor chip over the first surface of the wiring substrate such that a first main surface of the first semiconductor chip faces the first surface of the wiring substrate, the first semiconductor chip including the first main surface, a first semiconductor element formed on the first main surface, a plurality of first main surface side pads formed on the first main surface and electrically connected with the first semiconductor element, a second alignment mark formed at the first main surface side, a plurality of first external terminals formed at the first main surface side pads, respectively, a first back surface opposite to the first main surface, a plurality of first back surface side pads formed on the first back surface and electrically connected with the first main surface side pads, and a third alignment mark formed on the first back surface; (c) after the step (b), while the first semiconductor chip being arranged over the wiring substrate, arranging a mark position detector between the wiring substrate and the first semiconductor chip with, and detecting the first alignment mark of the wiring substrate and the second alignment of the first semiconductor chip and thereby align the wiring substrate with the first semiconductor chip; (d) after the step (c), mounting the first semiconductor chip over the first surface of the wiring substrate, and electrically connecting the first external terminals with the bonding leads, respectively; (e) after the step (d), arranging a second semiconductor chip over the first back surface of the first semiconductor chip, the second semiconductor chip including a second main surface, a second semiconductor element formed on the second main surface, a plurality of second main surface side pads formed on the second main surface and electrically connected with the second semiconductor element, a fourth alignment mark formed at the second main surface side, a plurality of second external terminals formed at the second main surface side pads, respectively, and a second back surface opposite to the second main surface; (f) after the step (e), while the second semiconductor chip being arranged over the first semiconductor chip, arranging the mark position detector between the second semiconductor chip and the first semiconductor chip, and detecting the third alignment mark of the first semiconductor chip and the fourth alignment mark of the second semiconductor chip and thereby align the first semiconductor chip with the second semiconductor chip; and (g) after the step (c), mounting the second semiconductor chip over the first semiconductor chip, and electrically connecting the second external terminals with the first back surface side pads, respectively.