Patent ID: 6430088
Filing Date: 2002-08-06
Classification: G06F,G11C

Abstract:
A field programmable gate array architecture comprising:a plurality of routing resources; a plurality of logic modules disposed in a rectangular array on said plurality of routing resources, each of said plurality of logic modules having at least one input and at least one output, said at least one input and at least one output, of at least one of said plurality of logic modules that are programmably coupled to at least one routing resource of said plurality of routing resources; and a plurality of random access memory blocks, each of said plurality of random access memory blocks having a first port and a second port, said first port connected to a first address bus, a first data bus, and at least one first enable signal line that may be programmably coupled to said plurality of routing resources, and said second port connected to a second address bus, a second data bus, and at least one second enable signal line that may be programmably coupled to said plurality of routing resources.