Patent ID: 7406642
Filing Date: 2008-07-29
Classification: G01R,H04L

Abstract:
1. A programmable logic integrated circuit (IC) comprising: a pin configured to operate only as an output pin during a user mode of the programmable logic integrated circuit; an output buffer coupled to the pin; a first input buffer coupled to the pin; a first logic gate that receives a test instruction and an output enable signal, wherein the first logic gate disables the output buffer in response to the test instruction during a boundary scan test, and the first logic gate enables the output buffer in response to the output enable signal and the test instruction; and a second logic gate that receives the test instruction and a first configuration data signal, wherein the second logic gate enables the first input buffer in response to the test instruction during the boundary scan test to capture a board level interconnect test signal applied to the pin, wherein the second logic gate disables the first input buffer in response to the first configuration data signal and the test instruction during the user mode.