Patent ID: 6519711
Filing Date: 2003-02-11
Classification: G06F

Abstract:
A circuit for generating a clock signal, said circuit comprising:a step register having an input and a first, second, and third outputs, wherein said step register comprises: a step bit position for storing a step bit, said step bit position coupled to said first output; at least one burst control bit position, said at least one burst control bit position coupled to said second output; and a mode bit position, said mode bit position coupled to said third output; a burst pulse generator having an input and an output, said input coupled with said second output of said step register to receive said at least one burst control bit, said burst pulse generator adapted to generate a number of stepped half clock pulses, said number specified by said at least one burst control bit; and a first switch having first, second, and third inputs and an output, said first input coupled to said first output of said step register to receive said step bit, said second input coupled to said third output of said step register to receive said mode bit, and said third input coupled to said output of said burst pulse generator to receive said number of stepped half clock pulses, wherein said output of said first switch is controlled by said mode bit to output either said step bit or said number of stepped half clock pulses as said clock signal.