Patent ID: 6214666
Filing Date: 2001-04-10
Classification: G11C,H01L,Y10S

Abstract:
A method for manufacturing an avalanche/Zener breakdown, non-volatile EEPROM memory cell, comprising the sequential steps of:(a) providing a semiconductor substrate having a surface;(b) forming a gate stack on the surface of the substrate;(c) forming a first active region and a second active region into the substrate so that the first and second active regions extend to a depth below the surface of the substrate and have a first impurity type and an impurity concentration; and(d) implanting at an angle non-normal to the surface of the substrate a pocket region of an opposite conductivity type to that of the first or second active region into the surface of the substrate adjacent to the first region, the pocket region being formed such that a P/N junction between said first active region and said pocket region has an avalanche/Zener breakdown in the range of 4-8V between a voltage applied to the substrate and a voltage applied to said first active region.