Patent ID: 6542916
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A data processing apparatus for applying a floating-point multiply-accumulate operation to first, second and third operands, comprising:a multiplier for multiplying the second and third operands and applying rounding to produce a rounded multiplication result; an adder for adding the rounded multiplication result to the first operand to generate a final result, and for applying rounding to generate a rounded final result; and control logic, responsive to a first single instruction, to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the first operand, wherein the control logic includes primitive determination logic responsive to the first single instruction and the sign values of the first, second and third operands to determine whether to cause the adder to perform a like-signed addition (LSA) operation or an unlike-signed addition (USA) operation, and to generate a control signal dependent on the determination.