Patent ID: 6295582
Filing Date: 2001-09-25
Classification: G06F

Abstract:
In a computing system having a cache memory interposed between a system memory and an I/O bus, a method for managing data within the cache memory comprising the steps of:(a) providing a single data storage area in the cache memory in communication with both a system data bus and an I/O data bus;(b) providing a single address storage area configured to store system memory addresses corresponding to data contemporaneously stored in the data storage area;(c) identifying a request for data from the system memory by the device, wherein the data requested is not presently in the single data storage area of the cache memory;(d) reading the data from the system memory into the single data storage area of the cache memory;(e) evaluating the cache memory to determine whether at least a predetermined amount of space within the single data storage area is readily available;(f) flushing a portion of the data within the single data storage area, in response to step (c), if at least the predetermined amount of space is not readily available; and(g) repeating steps (c) through (f).