Patent ID: 9178041
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A method comprising: forming a first trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type; forming an implantation mask extending into the trench and covering edges of the trench; performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, wherein the DD region is of the first conductivity type; etching the semiconductor region and a bottom portion of the DD region to extend the trench further down into the semiconductor region, wherein the etching is anisotropic, with portions of the DD region located on opposite sides of the trench; after the etching, forming a first dielectric layer lining a bottom and sidewalls of the trench; forming a field plate in the trench and over a bottom portion of the first dielectric layer; forming a second dielectric layer over the field plate; forming a main gate in the trench and over the second dielectric layer; and forming a lateral Metal-Oxide-Semiconductor (MOS) device, wherein the lateral MOS device comprises a gate electrode over the semiconductor region.