Patent ID: 6188620
Filing Date: 2001-02-13
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of normal memory cells;a plurality of redundancy memory cells provided for defect relief in the normal memory cells;a main word driver that drives a normal word line to select said plurality normal memory cells, when in an active state;a redundancy word driver that drives a redundancy word line to select said plurality of redundancy memory cells, when in an active state; anda redundancy judgment circuit that judges whether or not an address signal input is of a defect address in said plurality of normal memory cells and, when the address signal is of the defect address, places the redundancy word driver in the active state without placing the main word driver in the active state, while, when the address signal is not of the defect address, placing the main word driver in the active state without placing the redundancy word driver in the active state,wherein, said redundancy judgment circuit places both the redundancy word driver and the main word driver in the respective inactive states in an initial state before the address signal is input to the redundancy judgment circuit, and said main word driver is supplied with said address signal whether said address signal is said defect address or not.