Patent ID: 6911229
Filing Date: 2005-06-28
Classification: H01L,Y10T

Abstract:
1. A method for fabricating an electronic structure which comprises forming an insulating material on a substrate; lithographically defining and forming recesses for lines, or vias or both in the insulating material in which interconnection conductor material will be deposited; depositing in the recesses a barrier layer, wherein the barrier layer is selected from the group consisting of tungsten, alloys of tungsten, titanium, alloys of titanium, titanium nitride, tantalum, tantalum nitride and tantalum silicon nitride; depositing an interlayer of a member selected from the group consisting of palladium, platinum and mixtures thereof, wherein the interlayer is about 50 to about 500 Angstroms thick; and depositing copper or a copper alloy on the interlayer to fill the recesses; and wherein said interlayer is intermediate said coppoer or copper alloy and said barrier layer.