Patent ID: 6535982
Filing Date: 2003-03-18
Classification: G06F,Y02D

Abstract:
A semiconductor integrated circuit comprising:(a) a CPU configured to execute various processes; (b) at least one hardware module configured to receive instructions from the CPU and to execute the instructions; and (c) a power management device configured to control the supply of a clock signal to the CPU so as to stop the clock signal to the CPU when the CPU has an idle time to execute the next substantial process, the power management device comprising: a first storage circuit configured to store data related to a combination of the hardware modules specified by a sleep instruction; a second storage circuit configured to store data indicating whether the hardware modules have completed the execution of instructions; a comparison circuit configured to determine whether data in the first and second storage circuits agree with each other; and a control circuit configured to stop the supply of the clock signal to the CPU when the sleep instruction is executed and to resume the supply of the clock signal to the CPU when the comparison circuit determines that data in the first and second storage circuits agree with each other.