Patent ID: 6760790
Filing Date: 2004-07-06
Classification: G06F,Y02D

Abstract:
A direct memory access controller for transferring data from a transfer source memory region to a transfer destination memory region, comprising:a transfer source address calculation unit which has transfer source address registers corresponding to a plurality of channels and which generates a transfer source address whenever data transfer is performed; a transfer destination address calculation unit which has transfer destination address registers corresponding to said plurality of channels and which generates a transfer destination address whenever data transfer is performed; a transfer count calculation unit which has transfer count registers corresponding to said plurality of channels and which generates a remaining transfer count whenever data transfer is performed; and an address increase/decrease value setting unit which has address increase/decrease value registers corresponding to said plurality of channels, wherein said transfer source address calculation unit and/or said transfer destination address calculation unit comprise a calculation section which calculates upon data transfer a data transfer source address and/or transfer destination address for a subsequent data transfer from an initially set transfer source address and/or transfer destination address, and wherein said transfer source address register and/or said transfer destination address register retain said initially set transfer source address and/or transfer destination address.