Patent ID: 7576382
Filing Date: 2009-08-18
Classification: H01L

Abstract:
1. A semiconductor integrated device comprising: an interconnection pattern to be shielded; a plurality of interconnection layers having respective shield interconnection patterns formed therein; a diffusion formed in the substrate; a first gate oxide film in contact with the diffusion; a first polysilicon layer formed on the first gate oxide film; a second gate oxide film formed on the first polysilicon layer; and a second polysilicon layer formed on the second gate oxide film, wherein a first one of the shield interconnection patterns is formed in a first one of the interconnection layers, and a second one of the shield interconnection patterns is formed in a second one of the interconnection layers, and wherein the second one of the shield interconnection patterns is connected to the first polysilicon layer, and the first one of the shield interconnection patterns is connected to the diffusion and the second polysilicon layer, so that a parasitic capacitance between the first polysilicon layer and the second polysilicon layer is added.