Patent ID: 8094479
Filing Date: 2012-01-10
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines; a plurality of ferroelectric capacitors corresponding to intersecting points between the word lines and the bit lines and configured to store therein data; a plurality of plate lines connected to electrodes of the ferroelectric capacitors; a plurality of sense amplifiers connected to the bit lines, and configured to detect the data in the ferroelectric capacitors connected the bit lines; and a plate controller configured to receive a plate driving signal configured to drive at least one of the plate lines, a write signal indicative of writing of data from an outside to at least one of the sense amplifiers, and an operation end signal indicative of end of an executable period for reading the data from at least one of the sense amplifiers to the outside or for writing the data from the outside to at least one of the sense amplifiers, the plate controller being configured to validate or invalidate the plate driving signal on the basis of the write signal and the operation end signal wherein the plate controller is configured to validate the plate driving signal in the executable period, and the plate controller is configured to invalidate the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and to keep the plate driving signal valid when the write signal is activated at least once in the executable period.