Patent ID: 7629633
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A vertical thin film transistor comprising: a source semiconductor layer doped in a first manner and in communication with a source electrode; a drain semiconductor layer vertically spaced from said source semiconductor layer, doped in said first manner and in communication with a drain electrode; a first intermediate semiconductor layer doped in a second manner counter to said first manner and formed adjacent to said source semiconductor layer, between said source semiconductor layer and said drain semiconductor layer; a second intermediate semiconductor layer doped in said second manner and formed adjacent to said drain semiconductor layer, between said source semiconductor layer and said drain semiconductor layer; a dielectric layer formed between said first intermediate semiconductor layer and said second intermediate semiconductor layer; where said source semiconductor layer, said first intermediate semiconductor layer, said dielectric layer, said second intermediate semiconductor layer and said drain semiconductor layer are arranged to define a surface extending from said source semiconductor layer to said drain semiconductor layer; a channel semiconductor layer formed on said surface, wherein a conducting channel may be established between said source semiconductor layer and said drain semiconductor layer; and a gate electrode proximate said channel semiconductor layer such that a voltage applied to said gate electrode controls a conductivity of said conducting channel.