Patent ID: 6232632
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having a main surface; andfirst and second spaced apart double non-volatile memory cells, each double non-volatile memory cell comprising first and second floating gate electrodes spaced apart from a common control gate electrode by a dielectric layer, wherein:the common control gate of the first double non-volatile memory cell is spaced apart from the common control gate of the second double non-volatile memory cell;the substrate comprises:a first impurity region containing an impurity of the first conductivity type at a first impurity concentration;a common source region, on the first impurity region, comprising an impurity of the second conductivity type, opposite to the first impurity conductivity type; anda mesa region, on the common source region, between the second floating gate of the first double non-volatile memory cell and the first floating gate of the second double non-volatile semiconductor cell and having first and second side surfaces containing an impurity of the first conductivity type at an impurity concentration greater than the first impurity concentration and constituting first and second channel regions separated by a central region comprising an impurity of the first conductivity type at a concentration less than the channel impurity concentration; andeach common control gate terminates in an impurity region of the first conductivity type having an impurity concentration greater than the first impurity concentration.