Patent ID: 6532523
Filing Date: 2003-03-11
Classification: G06F

Abstract:
An apparatus for processing memory access requests, comprising:an arbiter, said arbiter receiving a current memory access request and a next memory access request, and determining whether processing of said next memory access request will interfere with processing of said current memory access request; a first state machine for controlling access to a first memory bank, said first state machine processing said current memory access request to enable the first memory bank to be accessed; a second state machine for controlling access to a second memory bank, said second state machine, in response to a determination by said arbiter that processing of said next memory access request will not interfere with processing of said current memory access request, processing said next memory access request to enable the second memory bank to be accessed, said second state machine beginning processing of said next memory access request prior to completion of processing of said current memory access request by said first state machine, wherein the first state machine and the second state machine output a first set of control signals and a second set of control signals, respectively; and a logic component for performing an NOR operation on the first and second sets of control signals to derive a set of processed control signals and to provide the processed control signals to at least one of the first and second memory banks.