Patent ID: 8068364
Filing Date: 2011-11-29
Classification: G11C,H01L

Abstract:
1. A three dimensional stacked nonvolatile semiconductor memory comprising: a semiconductor substrate; a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side in a first direction; and a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction, wherein each of the first and second blocks is comprised of at least three conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least three conductive layers by being insulated therefrom, and columnar semiconductors passing through the at least three conductive layers, wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in the second direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line, wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively, and memory cells are comprised of the word line and the columnar semiconductor, respectively, and a selected first cell unit and non-selected second cell units are connected to the bit line, and each of the selected first cell unit and the non-selected second cell units is comprised of the memory cells and the select gate transistors, and wherein the first select gate lines in the first block and the first select gate lines in the second block are connected to the first driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.