Patent ID: 8881117
Filing Date: 2014-11-04
Classification: G06F

Abstract:
1. A method executable by a processor, comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by: using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor, and making a modification affecting the timing property in dependence on said estimation, said estimation and said modification being based on the higher-level control flow structure as generated using said predetermined set of structure node patterns and the single execution time allocated to each of the second higher-level nodes; wherein the predetermined set of structure node patterns comprises a conditional-type pattern comprising a plurality of alternate edges resolving to a common exit point, and a loop-type pattern comprising one or more lower level repeating nodes and an associated looping edge; and wherein the single execution time allocated to the first and second higher-level structure nodes matched to each of the structure node patterns is a worst case execution time.