Patent ID: 7126864
Filing Date: 2006-10-24
Classification: G11C

Abstract:
1. A memory device, comprising: an address comparator in which a fail address used to select a fail cell is stored on an 8-bit output mode basis, wherein the address comparator compares an address signal and the fail address, and generates a repair enable signal if the address signal and the fail address coincide with each other; an address signal controller which transfers the address signal in entirety to the address comparator in the 8-bit output mode, and transfers address bits of the address signal that are used only in the 8-bit output mode as a given logic value, so that the transferred address bits are not compared in a 16-bit output mode according to an output mode decision signal and a 8-bit forced decision signal; and a fail bit signal generator that generates fail bit signals that indicate to which bit of output data does fail data of the fail cell correspond according to the repair enable signal, wherein although information on the fail address is stored on the 8-bit output mode basis, the memory device is configured to operate as the 8-bit output mode or the 16-bit output mode according to the output mode decision signal and the 8-bit forced decision signal.