Patent ID: 6642928
Filing Date: 2003-11-04
Classification: G06T,G09G

Abstract:
A graphics accelerator for processing a graphics request stream, the accelerator comprising:a first processor having a first input for receiving a first portion of the graphics request stream, the first processor also having a first output for delivering a first unit output; a second processor having a second input for receiving a second portion of the graphics request stream, the second processor also having a second output for delivering a second unit output; a bus coupled with the first output and the second output, the bus being controlled at a single time by no more than one processor; the first and second processors being arranged in a peer-to-peer configuration to process the graphics request stream on a cyclical basis; after gaining control of the bus, the first processor maintaining exclusive control of the bus until a flag is received at the end of the first portion of the graphics request stream.