Patent ID: 7800196
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. An edge termination structure for a semiconductor device, comprising: a first n-type semiconductor layer having a first dopant concentration and situated on a top surface of a semiconductor substrate; a second n-type semiconductor layer having a second dopant concentration that is higher than the first dopant concentration of the first n-type semiconductor layer, and situated on a top surface of the first n-type semiconductor layer, wherein the first n-type semiconductor layer is sandwiched between the semiconductor substrate and the second n-type semiconductor layer; a mesa extending through the second n-type semiconductor layer and terminating into the first n-type semiconductor layer, wherein the edge termination structure is formed in the first n-type semiconductor layer surrounding a bottom of the mesa; and an n-type electric field semiconductor stop layer formed at a periphery of the semiconductor device having a third dopant concentration higher than the first dopant concentration of the first n-type semiconductor layer and approximately the same as the second dopant concentration of the second n-type semiconductor layer, wherein a top surface of the n-type electric field semiconductor stop layer is at a same elevation as a top surface of the second n-type semiconductor layer.