Patent ID: 6643840
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A designing method of a semiconductor integrated circuit, said integrated circuit comprising a plurality of macro circuits, said designing method comprising:providing a library storing a macro mask pattern for at least one macro circuit, said at least one macro circuit including: an inner circuit outputting an output signal; and a plurality of buffer circuits, each of which comprises: first and second wirings apart from each other; a first semiconductor element selectively supplying said first wiring with a power supply potential in accordance with said output signal; and a second semiconductor element selectively supplying said second wiring with a grounded potential in accordance with said output signal, wherein said macro mask pattern includes a plurality of buffer mask patterns, each of which corresponds to one of said plurality of buffer circuits, and each of said plurality of buffer mask patterns comprises: a first wiring pattern for said first wiring, and a second wiring pattern for said second wiring; selecting one of said plurality of buffer circuits as a selected buffer circuit; and arranging said macro mask pattern and a third wiring pattern for a third wiring to produce an integrated circuit mask pattern based on said library such that said first and second wiring patterns of said selected buffer circuit are connected with each other by said third wiring pattern.