Patent ID: 6635540
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A manufacturing method for a transistor on a substrate, comprising:providing a substrate having a dielectric layer thereon; forming a gate structure on said dielectric layer having a gate oxide layer formed on said dielectric layer and a metal suicide layer formed on said gate oxide layer, said gate structure having a first sidewall and a second sidewall, said first sidewall and said second sidewall defining therebetween within said substrate a first contact region, a channel region and a second contact region; and forming first, second, and third subregions within said second contact region, each subregion having a dopant concentration that differs from that of the other two subregions, said forming of said first, second, and third subregions comprising: depositing a conformal layer of dielectric material over said substrate; anisotropically etching said conformal layer of dielectric material, forming a layer of dielectric material on said first sidewall and said second sidewall; subjecting said layer of dielectric material on said first sidewall and said second sidewall to an annealing/oxidation process; forming a single layer sidewall spacer overlying said first sidewall and said second sidewall; introducing a first dopant into said substrate to form said first subregion; forming another single layer sidewall spacer overlying said single layer sidewall spacer; introducing a second dopant into said substrate to form said second subregion; substantially removing said another single layer sidewall spacer; and introducing a third dopant into said substrate to form said third subregion.