Patent ID: 8036038
Filing Date: 2011-10-11
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of blocks each including a memory cell unit in which current paths of a plurality of memory cells arranged in a matrix at intersections of a plurality of bit lines and a plurality of word lines are connected in series, and a selection transistor which selects the memory cell unit; and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors having current paths whose ends are electrically connected to the plurality of word lines, and which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction, wherein diffusion layers as the ends of the current paths of the transfer transistors are formed to oppose each other in the first block selector and the second block selector, and a floating voltage is applied to the diffusion layers of the first block selector and a ground voltage is applied to the diffusion layers of the second block selector when data is erased from the memory cell.