Patent ID: 8896360
Filing Date: 2014-11-25
Classification: H03K

Abstract:
1. A level-up shifter circuit comprising: a first buffer configured to receive an input signal in a first power domain; first, second and third transistors connected in series between a source rail in a second power domain and a ground rail, gates of the second and third transistors connected to an output of the first buffer, the second power domain being distinct from the first power domain; second and third buffers connected in series, an output of the second buffer being connected to an input of the third buffer, an input of the second buffer being connected to a node between the second and third transistors, the third buffer outputting an output signal in the second power domain; fourth and fifth transistors having respective gates connected to the input signal and respective drains connected to a gate of the first transistor, wherein a node between the second and third buffers is connected to the gate of the first transistor via the fourth transistor; and sixth and seventh transistors connected in series between the ground rail and a node between the second and third buffers.