Patent ID: 8519754
Filing Date: 2013-08-27
Classification: H03L,H05B,Y02B

Abstract:
1. A system for signal synchronization, the system comprising: a first selection component configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal, the first selection signal indicating a first operation mode; a first signal generator configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal, the first input signal including a first input rising edge and being associated with a first input frequency, the first clock signal including a first clock rising edge and being associated with a first clock frequency; a second signal generator configured to, if the first selection signal satisfies one or more second conditions, generate at least a second clock signal, the second clock signal including a second clock rising edge and being associated with a second clock frequency; and a first gate drive component configured to: wherein: