Patent ID: 7249301
Filing Date: 2007-07-24
Classification: G11C

Abstract:
1. A semiconductor circuit having a standard interface for external data, address or command interchange in normal operation and a test interface provided for a test operation, with a semiconductor memory and with a test control unit assigned to the semiconductor memory, comprising: a controller for initialization, testing and application-near setting of the semiconductor memory in the normal operation; a read-only nonvolatile memory, the read-only nonvolatile memory storing a standard program code for configuration and for testing of the semiconductor memory, standard test, and standard boot parameters; a programmable nonvolatile memory, the programmable nonvolatile memory storing at least one further program code for configuration and for testing of the semiconductor memory, functional tests, operating parameters, test and boot parameters; and a volatile memory, the volatile memory being assigned to the controller, and during booting, an execution program code selected from the group including: the standard program code and the at least one further program code being loaded for execution into the volatile memory, the controller performing a configuration during booting and optionally a testing of the semiconductor memory in subsequent normal operation by execution of functional tests and storing the data determined during testing as operating, test or boot parameters in the programmable nonvolatile memory or outputting the data externally via the standard interface or the test interface of the semiconductor circuit.