Patent ID: 8825951
Filing Date: 2014-09-02
Classification: G06F

Abstract:
1. An apparatus for managing a high speed memory, the apparatus comprising: a processor, and a non-transitory computer readable storage medium coupled to the processor, wherein the computer readable storage medium stores instructions which, when executed by the processor, cause the processor to: determine, in response to receipt of a demotion request, margin performance losses corresponding to respective non-free indexes, wherein corresponding non-free indexes are set for different types of low speed memory, wherein each non-free index comprises index entries indicating a storage unit in a high speed memory assigned to a corresponding low speed memory, wherein a storage unit in the high speed memory is recovered by demoting an index entry from a given non-free index, wherein a given margin performance loss represents a change in a processor read operation time caused by performing a demotion operation in a corresponding non-free index; compare the margin performance losses of the respective non-free indexes and select as a demotion index a non-free index whose margin performance loss satisfies a demotion condition; and select an index entry from the demotion index to perform the demotion operation, wherein determining margin performance losses comprises: determining a margin hit rate loss corresponding to the respective non-free index; determining a synthesized response time corresponding to the respective non-free index, wherein the synthesized response time corresponding to the respective non-free index is a weighted average of predicted values of average response times of the low speed memories corresponding to the respective non-free index according to predicted numbers of accesses; and multiplying the margin hit rate loss by the synthesized response time to determine the margin performance loss.