Patent ID: 6574146
Filing Date: 2003-06-03
Classification: G11C

Abstract:
A read timing circuit for regulating reading from a multi-level non-volatile memory by generating and issuing an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, with said dummy wordline being applied a supply voltage and associated with a dummy decoding circuit portion arranged to receive an ATD signal, the read timing circuit comprising:a first MOS transistor having a control terminal coupled to the dummy wordline, a first terminal coupled to a first voltage reference, and a second terminal; and a differential cell comparator having a first input coupled to the second terminal of the first MOS transistor; a second input arranged to receive a reference signal, and an output at which an electric signal is generated upon said dummy wordline attaining a potential that is a predetermined percentage of said supply voltage.