Patent ID: 6643216
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A circuit for queuing asynchronous external memory requests that initiate external RAS cycles of a DRAM, comprising:an address transition circuit that, in response to changes in address input signals for the DRAM, provides an address change detection signal (det_a_buf) and, if an address input signal is stable, provides a stable address signal (addr_stable); a RAS timer circuit that is provided with an input selection trigger signal (sel_xras) to provide a RAS output signal (xras_time1_b or xras1_b) that controls execution of external RAS cycles by the DRAM; a first latch that, when there is no RAS cycle currently underway, is set in response to a stable address signal (addr_stable) to provide an output signal (xr_rq) that initiates an input selection trigger signal (sel_xras)for the RAS timer circuit, and that is reset whenever execution of an external RAS cycle begins; a second queuing latch that is set in response to an address change detection signal (det_a_buf) which is received while a current RAS access cycle is underway to provide a request-queue output signal (xque) so that, when the RAS output signal goes inactive, the input selection trigger signal (sel_xras) for the RAS timer circuit is alternatively initiated; such that when any RAS access cycle is complete and if the second queuing latch is set, a new RAS cycle is initiated and the second queuing latch is reset; whereby any new access requests, as indicated by the address change detection signal (det_a_buf), that are received when a current RAS access cycle is underway are queued in the second queuing latch to await execution of a corresponding RAS cycle.