Patent ID: 7053632
Filing Date: 2006-05-30
Classification: H02M,Y02B

Abstract:
1. A circuit for predicting a dead time, comprising: a first integrator for performing a charging operation during a (N+1) a second integrator for performing a charging operation during a N a first comparator having input terminals coupled to the first integrator and the second integrator respectively, and generating a first comparison result signal when a charging voltage value of the first integrator exceeds the first voltage value; a third integrator for performing a charging operation during the N a fourth integrator for performing a charging operation during a (N−1) a second comparator having input terminals coupled to the third integrator and the fourth integrator respectively, and generating a second comparison result signal when a charging voltage value of the third integrator exceeds the second voltage value; and a logic circuit coupled to an output of the first comparator and an output of the second comparator for receiving the first comparison result signal and the second comparison result signal, and generating a reset signal based on a result of a logical operation on the first comparison result signal and the second comparison result signal, wherein, the charging operation is performed by the first integrator and the third integrator during the N