Patent ID: 6384450
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A Semiconductor memory device comprising:a semiconductor substrate; element isolation regions formed in said semiconductor substrate; active regions between said element isolation regions; buried diffusion layers each constituting at least a drain region or a source region; floating gates each formed on a channel region between said drain region and said source region via an insulating film; sidewall spacers formed of side surfaces of said floating gates and made of insulating material; a first layer formed on said buried diffusion layers and said sidewall spacers and comprising high refractory metal or metal compound, wherein said first layer does not extend vertically beyond the top surface of the floating gate; a second layer formed on said first layer and made of material different from that of said first layer; a third layer formed on said second layer and comprising insulating material; a fourth layer formed on said floating gate and said third layer and comprising insulating material; and a control gate formed on said fourth layer.