Patent ID: 8940598
Filing Date: 2015-01-27
Classification: G06F,H01L,H02J

Abstract:
1. A process of forming an integrated circuit, comprising the steps: providing a substrate; forming a CMOS gate dielectric layer on said substrate; forming a gate polysilicon layer over said substrate and said CMOS gate dielectric; performing an pregate etch implant operation which implants pregate etch dopants into said gate polysilicon layer; forming a gate mask on said gate polysilicon layer; etching said gate polysilicon layer to form: forming an LDD implant mask over said substrate which: performing an LDD implant operation which implants LDD dopants into said substrate adjacent to said CMOS gate to form LDD layers; forming sidewall spacers adjacent said CMOS gate; forming an SD implant mask over said substrate which: performing an SD implant operation which implants SD dopants into said substrate adjacent to said CMOS gate to form SD layers; implanting said resistor layer with at least two of said pregate etch implant operation, said LDD implant operation, and said SD implant operation; forming a resistor silicide block layer over said body region of said resistor layer; forming metal silicide layers on said head regions of said resistor layer, on said CMOS gate, and on said SD layers adjacent to said CMOS gate; forming a PMD layer over said metal silicide layers and over said resistor silicide block layer; and forming contacts through said PMD layer, said contacts making electrical connection to said metal silicide layers on said SD layers.