Patent ID: 8984469
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A method implemented in a programmable system for incorporating in a design description of an integrated circuit a power reduction circuit for a flip-flop (FF) having an enable condition for a clock signal of the FF, the method comprising: adding to the design description at least one of: an observability don't care condition (ODC) controller to strengthen an enable condition of the FF of the design description based on respective ODC of the FF, the ODC controller configured to generate an enable signal to the FF; and, a stability condition (STC) controller to strengthen an enable condition of the FF based on respective STC of the FF and causing the STC controller to generate an enable signal to the FF; performing power saving computations to compare power consumption of the integrated circuit both with and without each added controller; discarding any additional controller from the updated design description whenever power consumption saving achieved is below a predetermined threshold; and storing in a memory of the programmable system an updated description of the integrated circuit; wherein strengthening the enable condition of the FF ensures that a subsequent FF in a fan-out of the FF is enabled only when the FF drives a signal to the subsequent FF.