Patent ID: 7928779
Filing Date: 2011-04-19
Classification: H03L

Abstract:
1. A phase-locked loop, comprising: a phase-frequency detector for comparing a reference clock and a feedback clock to generate a difference signal; a lock detector for comparing the reference clock and the feedback clock and asserting a lock signal when the reference clock and the feedback clock reach substantially a same frequency; a delay circuit for asserting a step notification signal a time delay after the lock signal is asserted; a bandwidth control counter for generating an incremental current indicator after detecting a bandwidth change indicator, wherein a duration of the incremental current indicator is correlated to a number of times the step notification signal is asserted and a predetermined number of bandwidth steps; an adjustable charge pump for generating an adjustment signal responsive to the difference signal and the incremental current indicator; a low-pass filter for generating a frequency adjustment signal responsive to the adjustment signal; and a voltage-controlled oscillator for generating an output clock with a variable frequency responsive to a voltage level of the frequency adjustment signal.