Patent ID: 9136267
Filing Date: 2015-09-15
Classification: G06F,H01L

Abstract:
1. An integrated circuit chip, comprising: a plurality of complementary metal oxide semiconductor (CMOS) integrated circuit cells arranged in a semiconductor layer, wherein each one of the CMOS integrated circuit cells includes first and second active regions disposed in the semiconductor layer, wherein the first active region is doped with dopants having a first polarity, and wherein the second active region is doped with dopants having a second polarity; a first power rail included in metal layers disposed over the semiconductor layer and routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions of the CMOS integrated circuit cells; a second power rail included in the metal layers disposed over the semiconductor layer and routed over second active regions of the CMOS integrated circuit cells; and global routing channels included in the metal layers over the semiconductor layer and routed over the second active regions of the CMOS integrated circuit cells such that the second power rail is disposed the metal layers between the global routing channels and the first power rail, wherein the global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip.