Patent ID: 8803619
Filing Date: 2014-08-12
Classification: H03K

Abstract:
1. A relaxation oscillator for generating an output clock signal, comprising: a resistor-capacitor (RC) circuit for generating first and second comparator input signals and receiving first and second control signals; a self-biased comparator stage connected to the RC circuit for generating first and second comparator output signals, the self-biased comparator stage comprising: a self-biased comparator for receiving the first and second comparator input signals and generating first and second intermediate output signals and the first and second comparator output signals, wherein the self-biased comparator comprises: an eighth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the gate and drain terminals of the first and fifth transistors, respectively; a ninth transistor having a drain terminal connected to a drain terminal of the eighth transistor, a gate terminal connected to the drain terminal thereof and to a gate terminal of the seventh transistor, and a source terminal connected to ground; a tenth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain terminals of the first and second transistors for receiving the first intermediate output signal; an eleventh transistor having a drain terminal connected to a drain terminal of the tenth transistor, a gate terminal connected to the drain terminals of the eighth and ninth transistors, and a source terminal connected to ground, wherein the first comparator output signal is generated at the drain terminals of the tenth and eleventh transistors; a twelfth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain terminals of the third and fourth transistors for receiving the second intermediate output signal; and a thirteenth transistor having a drain terminal connected to a drain terminal of the twelfth transistor, a gate terminal connected to the gate terminals of the seventh and ninth transistors, and a source terminal connected to ground, wherein the second comparator output signal is generated at the drain terminals of the twelfth and thirteenth transistors.