Patent ID: 6418552
Filing Date: 2002-07-09
Classification: G06F,H05K

Abstract:
An apparatus for optimizing traces of a bus of a mounting surface, the mounting surface being adapted for mounting at least first and second integrated circuits (ICs) thereon, each of the integrated circuits having a plurality of pins, each pin of an integrated circuit (IC) corresponding to a particular signal of the integrated circuit, each pin being conductively coupled by a conductive trace to the bus of the mounting surface, the apparatus comprising:first logic configured to determine a pad-to-pad flight time associated with each signal and to determine which pad-to-pad flight time is the greatest pad-to-pad flight time; second logic configured to compute a trace route for the signal associated with the greatest pad-to-pad flight time, the trace route corresponding to a route of a trace of the bus, the trace conductively coupling the pin of the first IC associated with the greatest pad-to-pad flight time to the pin of the second IC associated with the greatest pad-to-pad flight time; third logic configured to compute a trace route for all signals other than the signal associated with the greatest pad-to-pad flight time, the computed trace routes for all of said other signals having lengths that provide said all other signals with pad-to-pad flight times that are equal to the greatest pad-to-pad flight time; and fourth logic configured to calculate an offset to be produced in a clock signal provided to one of the ICs, the offset causing setup margins associated with the first and second ICs to be equal.