Patent ID: 7964461
Filing Date: 2011-06-21
Classification: H01L

Abstract:
1. A method of forming an isolation layer in a semiconductor device, comprising the steps of: forming a tunnel insulating layer and conductive layer patterns on an active area of a semiconductor substrate, an upper portion of the conductive layer patterns having a width narrower than that of a lower portion of the conductive layer patterns; etching the tunnel insulating layer and the semiconductor substrate between the conductive layer patterns to form a trench; forming an insulating layer to fill a portion of the trench with the insulating layer, wherein an overhang of the insulating layer is formed at a sidewall of the upper portion of the conductive layer while the portion of the trench is filled with the insulating layer; and performing an etching process to remove the overhang of the insulating layer formed at the sidewall of the upper portion of the conductive layer, wherein a portion of the insulating layer remains at the sidewall of the upper portion of the conductive layer and in the trench after the etching process, and wherein the step of forming the insulating layer and the step of performing the etching process are repeatedly performed until a space between the conductive layer patterns and the trench are filled with the insulating layer.