Patent ID: 6236615
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A semiconductor memory device fabricated on a semiconductor substrate, comprising:a memory cell array including plural memory cell blocks equal to a multiple of a natural number except powers of two, formed on first areas arranged in a first direction at intervals and a second direction perpendicular to said first direction at intervals and selectively categorized in a first kind of memory cell block having directly addressable regular memory cells and a second kind of memory cell block having other regular memory cells and redundant memory cells,a part of said directly addressable memory cells and a part of said other directly addressable memory cells being replaceable with said redundant memory cells,said first areas having respective first lengths measured in said first direction and approximately equal to one another;plural groups of first selecting signal lines associated with said plural memory cell blocks, respectively, and respectively extending over said first areas assigned to the associated memory cell blocks in said first direction,the first selecting lines of said plural groups being selectively connected to said directly addressable memory cells, said other directly addressable memory cells and said redundant memory cells incorporated in the associated memory cell blocks;a first peripheral circuit formed in second areas between said first areas spaced in said first direction, connected to said plural groups of first selecting signal lines, and responsive to first address signals so as to selectively drive said first selecting signal lines, thereby making said directly addressable memory cells, said other directly addressable memory cells or said redundant memory cells selectively accessible;second selecting signal lines respectively coupled to loads approximately equal to one another;a second peripheral circuit connected to said second selecting signal lines for selectively connecting the directly addressable memory cells, the other directly addressable memory cells or the redundant memory cells selected by said first peripheral circuit to a signal line; anda third peripheral circuit including plural sub-circuits respectively connected to said second selecting signal lines and responsive to second address signals for selectively driving said second selecting signal lines.