Patent ID: 6794914
Filing Date: 2004-09-21
Classification: H01L,H03K

Abstract:
An integrated circuit (IC) including circuits configured to operate in an active mode and a sleep mode, wherein during the sleep mode the IC maintains a data bit, the IC comprising:a first transmission gate comprising an input and an output, the first transmission gate enabled in response to a first control signal; a master register (MR) comprising high threshold voltage (HVT) complementary metal oxide semiconductor (CMOS) circuits, a MR input, and a MR output, the MR input electrically connected to the output of the first transmission gate; a second transmission gate comprising an input and an output, the second transmission gate electrically connected to the MR output, the second transmission gate enabled in response to a second control signal; and a slave register (SR) having an input electrically connected to the output of the second transmission gate, the slave register comprising HVT CMOS circuits, wherein the first transmission gate comprises HVT CMOS circuits, the second transmission gate comprises LVT CMOS circuits, and during the sleep mode, the first transmission gate is disabled, the second transmission gate is enabled, and the data bit is stored in the master register.