Patent ID: 9019773
Filing Date: 2015-04-28
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: a memory cell array including a plurality of memory blocks, each memory block of the plurality of memory blocks comprising memory cells connected to word lines and bit lines; and control logic configured to perform an erase operation in which an erase voltage is applied to a memory block of the plurality of memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line, wherein the control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information, wherein the erase state information indicates the number of on-cells or off-cells of the memory cells connected to the selected word line, wherein the control logic is further configured to decrease the level of the erase verification voltage when the number of on-cells is less than a first reference value, wherein the control logic is further configured to increase the level of the erase verification voltage when the number of on-cells is more than a second reference value, the second reference value being larger than the first reference value, and wherein the control logic is further configured to control the first reference value and the second reference value according to at least one of a measured temperature and a number of erase operations executed.