Patent ID: 6541335
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:forming a diffusion region in a semiconductor substrate and then connecting a conducting plug to said diffusion region, to form a memory-cell selecting transistor; forming a first insulator film so as to cover said conducting plug and then forming a second contact hole in said first insulator film so as to expose said conducting plug and, at the same time, forming a trench so as not to expose said plug; forming a conductive film in said second contact hole and said trench simultaneously, to constitute a lower electrode of a capacitor and a lower electrode of a dummy capacitor; forming capacitive insulator film so as to cover both of said electrodes and then forming an upper electrode made of polycrystalline silicon on said capacitive insulator film to form a capacitor and a dummy capacitor; forming a second insulator film so as to cover said upper electrode of said capacitor and then forming a first contact hole smaller in width than a second trench covered with said capacitive insulator film formed in said trench, in said second insulator film so as to expose said upper electrode of said dummy capacitor and, at the same time, forming a third contact hole which differs in depth from said first contact hole, in an insulator film which includes said first insulator film and said second insulator film; forming a barrier metal film which has an underlying film made of titanium, in such a way that a titanium film which has a film thickness corresponding to a film thickness of a polycrystalline silicon region formed in said trench by polycrystalline silicon of said upper electrode is formed at a bottom of said first contact hole; and conducting heat treatment of reacting titanium of said underlying film of said barrier metal film and polycrystalline silicon of said upper electrode.