Patent ID: 8008185
Filing Date: 2011-08-30
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, comprising: forming line patterns on a substrate along a first direction, the line patterns defining narrow gap regions along the first direction and wide gap regions along the first direction; forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns facing one another in the wide gap regions being formed to be spaced apart from each other to expose an upper surface of the substrate, and spacer patterns facing one another in the narrow gap regions being formed to contact each other to fill the narrow gap regions; forming an insulating interlayer to cover the spacer patterns and the line patterns; forming at least one opening along a second direction through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask; and forming a conductive pattern to fill the opening.