Patent ID: 6087207
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method for forming a gate of a field effect transistor, comprising:(a) providing a structure having:a Ill-V substrate;a channel layer over the substrate;a doped barrier layer over the channel layer;a protective layer disposed on the barrier layer;an etch stop layer disposed over the protective layer; anda source and drain contact layer disposed over the etch stop layer;(b) providing a mask over the surface of the structure to expose a surface portion of the contact layer;(c) subjecting the exposed surface portion of the contact layer to a first etch and etching through the contact layer to expose an underlying surface portion of the etch stop layer, such first etch etching the contact layer at a greater etch rate than the etch rate of such etch to the etch stop layer;(d) subjecting the exposed surface portion of the etch stop layer to a second etch and etching through the etch stop layer to expose an underlying surface portion of the protective layer, such second etch etching the etch stop layer at a greater etch rate than the etch rate of such second etch to the protective layer; and(e) depositing a metal over the mask and through etched portions of the etch stop layer onto the exposed portion of the protective layer.