Patent ID: 8900918
Filing Date: 2014-12-02
Classification: B82Y,H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising the steps of: forming a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; forming a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and contacts to the CMOS device layer that extend through the second oxide layer, the contacts to the CMOS device layer comprising at least one or more first contacts to the CMOS device layer and at least one or more second contacts to the CMOS device layer; and bonding the first wafer and the second wafer together by way of an oxide-to-oxide bond directly between the first and second oxide layers, such that the one or more first contacts to the CMOS device layer are in contact with the source and drain contacts to the graphene channel, and the one or more second contacts to the CMOS device layer are gate contacts for the graphene channel, and wherein the first oxide layer serves as a gate dielectric between the gate contacts and the graphene channel.