Patent ID: 6365833
Filing Date: 2002-04-02
Classification: H01L

Abstract:
An integrated circuit package comprising:a multilayered substrate having a central opening extending therethrough to a pair of spaced apart opposing surfaces and a region exterior to said central opening; a plurality of routing strips disposed within said substrate, extending between said central opening and said region exterior to said central opening and having an exposed surface disposed within said opening; a plurality of pads disposed on one of said surfaces, at least one of said pads being electrically connected to one of said plurality of routing strips; wire bonding electrically connecting said at least one of said bonding pads to at least one of said routing strips; an adhesive material disposed on the other of said surfaces of said substrate; a chip having a pair of opposing major surfaces and a perimeter, said chip being adhered to said substrate by said adhesive material, said chip having at least one bonding pad disposed in said opening, said adhesive material surrounding the perimeter of said chip to provide an hermetic seal between said chip and said substrate to protect said chip; and potting material filling said central opening.