Patent ID: 7836257
Filing Date: 2010-11-16
Classification: G06F

Abstract:
1. A method for managing a cache in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs, the method comprising: determining, by a first PU, that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block; determining, by the first PU, whether the first data block is a victim cache line from another one of the plurality of PUs; in the event the first data block is not a victim cache line from another one of the plurality of PUs, determining, by the first PU, whether the first cache contains a cache line in a coherency state of invalid; in the event the first cache contains a cache line in a coherency state of invalid, storing the first data block in the cache line in a coherency state of invalid and updating the coherency state of the first data block; in the event the first cache does not contain a cache line in a coherency state of invalid, determining, by the first PU, whether the first cache contains a cache line in a coherency state of moved; in the event the first cache contains a cache line in a coherency state of moved, selecting a cache line in a coherency state of moved and storing the first data block in the selected cache line in a coherency state of moved and updating the coherency state of the first data block; in the event the first cache contains a cache line in a coherency state of moved, determining, by the first PU, whether the first cache contains more than one cache line in a coherency state of moved; in the event the first cache contains more than one cache line in a coherency state of moved, selecting as a victim cache line a cache line in a coherency state of moved and tagged before any other coherency state, and selecting as a victim cache line a cache line in a coherency state of moved and exclusive before a cache line in a coherency state of moved and modified; and storing the first data block in the victim cache line and updating the coherency state of the first data block.