Patent ID: 6735688
Filing Date: 2004-05-11
Classification: G06F

Abstract:
A microprocessor comprising:an execution core to perform data speculation in executing a first instruction; a first replay mechanism to replay the first instruction via a first replay path if an error of a first type is detected indicating that the data speculation is erroneous, the first replay mechanism including a first delay unit to make a first copy of the first instruction and to hold the first copy for at least one clock cycle in a first clock domain and a first checker to determine whether the error of the first type has been detected and to send the first copy of the first instruction back to the execution core for replay if the error of the first type has been detected; and a second replay mechanism to replay the first instruction via a second replay path if an error of a second type is detected indicating that the data speculation is erroneous, the second replay mechanism including a second delay unit to make a second copy of the first instruction and to hold the second copy for at least one clock cycle in a second clock domain and a second checker to determine whether the error of the second type has been detected and to send the second copy of the first instruction back to the execution core for replay if the error of the second type has been detected.