Patent ID: 8310878
Filing Date: 2012-11-13
Classification: G11C,H02M

Abstract:
1. A boosting circuit boosting a power supply voltage and outputting a resultant boosted voltage from an output terminal comprises: a first clock terminal supplied with a first clock signal; a second clock terminal supplied with a second clock signal, the second clock signal having a phase inverted with respect to a phase of the first clock signal and having same amplitude and period as those of the first clock signal; a third clock terminal supplied with a third clock signal; a fourth clock terminal supplied with a fourth clock signal, the fourth clock signal having a phase inverted with respect to a phase of the third clock signal and having same amplitude and period as those of the third clock signal; a first rectification element connected at a first end thereof to a first power supply terminal, the power supply voltage being applied to the first power supply terminal; a first MOS transistor which is connected at a first end thereof to a second end of the first rectification element and is diode-connected; a first capacitor connected between a gate of the first MOS transistor and the first clock terminal; a second rectification element connected at a first end thereof to a second power supply terminal, the power supply voltage being applied to the second power supply terminal; a second MOS transistor which is connected at a first end thereof to a second end of the second rectification element and is diode-connected; a second capacitor connected between a gate of the second MOS transistor and the second clock terminal; a third rectification element connected at a first end thereof to a second end of the first MOS transistor; a third MOS transistor which is connected at a first end thereof to a second end of the third rectification element and is diode-connected; a third capacitor connected between a gate of the third MOS transistor and the third clock terminal; a forth rectification element connected at a first end thereof to a second end of the second MOS transistor; a fourth MOS transistor which is connected at a first end thereof to a second end of the fourth rectification element and is diode-connected; a fourth capacitor connected between a gate of the fourth MOS transistor and the fourth clock terminal; and a switch circuit which has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor, the switch circuit conducting changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal.