Patent ID: 6700150
Filing Date: 2004-03-02
Classification: H01L,Y10S

Abstract:
A self-aligned vertical transistor DRAM structure, comprising:a semiconductor substrate of a first conductivity type having an active region and two parallel first-type shallow-trench-isolation (STI) regions, wherein said active region is located between said two parallel first-type STI regions; a DRAM cell comprising a self-aligned trench region and a self-aligned common-drain region being formed on said semiconductor substrate, wherein said self-aligned trench region comprises a deep-trench region and a second-type STI region outside of said deep-trench region being located in said active region and two first-type second or third raised field-oxide layers being formed in said two parallel first-type STI regions; a second-type second or third raised field-oxide layer being formed in said second-type STI region; said deep-trench region being defined by a first sidewall dielectric spacer comprising: a trench capacitor being formed in a lower portion of a deep trench, a collar-oxide layer together with a capacitor-node connector being formed in a central portion of said deep trench, and a vertical transistor region being formed in an upper portion of said deep trench; said trench capacitor comprising an upper capacitor node being formed over a capacitor-dielectric layer and said capacitor-dielectric layer being formed over a lower capacitor node in said semiconductor substrate; said vertical transistor region comprising a gate-dielectric layer over a sidewall of said deep trench together with a conductive-gate node being formed over an isolation silicon-dioxide node, said isolation silicon-dioxide node being formed over a source conductive node, and said source conductive node being formed over said capacitor-node connector and a portion of said collar-oxide layer to act as a dopant diffusion source for forming a common-source diffusion region near its sidewall portion of said semiconductor substrate; and said self-aligned common-drain region being located in an outside portion of said self-aligned trench region comprising a common-drain diffusion region of said second conductivity type being formed in said semiconductor substrate of said active region, a third sidewall dielectric spacer being formed over an outer sidewall of said self-aligned trench region, and a flat bed being located outside of said third sidewall dielectric spacer and formed by a common-drain diffusion region of said second conductivity type in said active region and two first-type fifth raised field-oxide layers in said two parallel first-type STI regions, wherein each of the plurality of active regions under said common-drain diffusion region comprises a deep implant region of said first conductivity type being formed in said semiconductor substrate near a central portion of said gate-dielectric layer in said vertical transistor region, said common-source diffusion region of said second conductivity type being formed in said semiconductor substrate near an outside portion of said source conductive node, and a deeper implant region of said first conductivity type being formed in said semiconductor substrate near a central portion of said collar-oxide layer.