Patent ID: 7332762
Filing Date: 2008-02-19
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array including a cell unit composed of at least one memory cell and at least one select gate transistor; a word line which is connected to the memory cell and extends in a row direction on the memory cell array; a select gate line which is connected to the select gate transistor and extends in the row direction on the memory cell array; a bit line extending in a column direction on the memory cell array; a shunt area which is located in the memory cell array and extends in the column direction, and in which a location of the memory cell is forbidden; a first line, at least a portion of which is located in the shunt area, and which is connected to a first area on which the memory cell is formed; a second line, at least a portion of which is located in the shunt area, which is located above the first line, and which is connected to a source line; and a connection section between the first line and the first areas,