Patent ID: 6457104
Filing Date: 2002-09-24
Classification: G06F

Abstract:
A computer memory system implementing a processing device for enabling indirect storage and retrieval of compressed data in an available address space in a physical memory associated with said computer and issuing real memory addresses for accessing information from said physical memory, said system comprising:a sectored storage region in said physical memory for exclusive storage of information in fixed length storage sectors; a cache memory array device having a plurality of cache lines; a cache directory device, associated with said cache memory array device, comprising entries for storing address tag information and modification state information associated with the data stored in said cache memory array; a cache line replacement mechanism associated with said cache memory array, for performing a cache line fill operation by requesting and removing existing cache line data and replacing removed data with different data via a cache line replacement operation, and updating said directory device with new address tag information and modification state information; and, a cache memory access system for enabling access to said data in said physical memory by said processing device, the cache memory access system including a cache control mechanism for asserting signals associated with said cache line modification state information when a cache line is to be modified; and, a memory control device, responsive to said asserted modified state information signals for reallocating any sectors within said sectored storage region associated with said modified cache line as unused sectors available for subsequent data storage, and maintaining a list comprising addresses of said unused sectors in said physical memory, wherein said memory control device accesses said unused sector list for enabling subsequent data storage in said available unused sectors.