Patent ID: 7752030
Filing Date: 2010-07-06
Classification: G06F

Abstract:
1. A processor based system comprising: a processor and a storage subsystem communicatively coupled with the processor, the processor being one of a plurality of models of a base processor; an operating system stored in the storage subsystem, to schedule instructions for execution on the processor, the scheduled instructions including model-specific instructions wherein a behavior of a model-specific instruction executing on the processor differs depending on which model of the plurality of models is executing the model-specific instruction; an instruction identification, stored in the storage subsystem, the instruction identification identifying a predetermined set of instructions that are model-specific instructions; a driver of the operating system, further comprising a virtual machine monitor and an emulator for a model of the plurality of models of the base processor, the emulated model of the base processor being a different model than the model of the processor on which the instructions are being scheduled; and a virtualization subsystem of the processor based system to generate an event for the virtual machine monitor, at least in partial response to intercepting a model-specific instruction identified as an instruction of the predetermined set of instructions, the intercepted model-specific instruction being scheduled for execution on the processor, wherein the behavior of the intercepted model-specific instruction when executing on the processor is determined to differ from the behavior of the intercepted model-specific instruction when emulating execution on the emulated model of the base processor.