Patent ID: 8191034
Filing Date: 2012-05-29
Classification: G06F

Abstract:
1. A method for measuring terminal compatibility comprising: establishing a plurality of chip layout files corresponding to respective chips to be combined in stacked multi-chip manner, each chip layout file defining at least one interfacing terminal layer including a plurality of terminals for interconnection with another chip to be stacked therewith; forming an intermediate layer disposed between the first and second interfacing terminal layers, the intermediate layer including a plurality of vias passing therethrough, each defined to interconnect selected terminals of the first and second interfacing terminal layers; performing a structural integrity check, the structural integrity check including an interconnection survey between terminals of the first and second interfacing terminal layers; performing a functional integrity check, the functional integrity check including characterization of interconnections between terminals of the first and second interfacing terminal layers with respect to a predetermined signal and power map; and, identifying for a user, any terminals of the first and second interfacing terminal layers failing at least one of the structural and functional integrity checks.