Patent ID: 8258811
Filing Date: 2012-09-04
Classification: H03K

Abstract:
1. An integrated circuit device comprising: at least one field programmable gate array region; at least one region including circuitry other than field programmable gate array circuitry; an I/O system including I/O pads and associated driver circuits; and a user-programmable interconnect architecture for selectively making connections between said at least one field programmable gate array region, at least one mask-programmable gate array region and said I/O system, the user-programmable interconnect architecture including: a plurality of intersecting interconnect conductors, selected ones of the intersecting interconnect conductors programmably connectable to one another by user-programmable interconnect elements; first ones of the I/O pads hardwired to selected ones of the interconnect conductors and second ones of the I/O pads programmably connectable to selected ones of the interconnect conductors by user-programmable interconnect elements; inputs and outputs of individual logic modules in the field programmable gate array region programmably connectable to ones of the interconnect conductors by user-programmable interconnect elements; first inputs and outputs of circuitry other than field programmable gate array circuitry programmably connectable to ones of the interconnect conductors by user-programmable interconnect elements; and second inputs and outputs of circuitry other than field programmable gate array circuitry hardwired to ones of the interconnect conductors.