Patent ID: 6587375
Filing Date: 2003-07-01
Classification: G11C

Abstract:
A semiconductor memory device having electrically erasable and programmable memory cells, comprising:a plurality of memory cell sectors each having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; a plurality of global word lines each electrically connected to at least one of the word lines via connecting means; a plurality of sector selection circuits that select a memory cell sector by controlling the connecting means; a plurality of driver circuits that selectively supply a voltage according to an operation mode to a selected global word line via a pull-up transistor therein; a partial row decoder that selectively enables the voltage according to the operation mode and supplies it to the driver circuits; and a plurality of pre-charging circuits that cause a gate of a pull-up transistor in each driver circuit to be at a predetermined potential before the voltage according to the operation mode is applied to the selected global word line in response to a predetermined selection signal.