Patent ID: 6175139
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A semiconductor device pattern layout, including:a first region coupled to a terminal;a second region coupled to a discharging line;a gate electrode cooperating with said first and second regions, to provide a metal oxide semiconductor (MOS) transistor, said first region forming a source of said MOS transistor and said second region forming a drain of said MOS transistor; anda third region coupled to said terminal and to said discharging line, and provided adjacent to said MOS transistor, said third region including a bipolar transistor,wherein said MOS transistor and said bipolar transistor are electrically connected to said terminal, respectively,wherein a collector region, a base region and an emitter region of said bipolar transistor are adjacent to said gate electrode of said MOS transistor, andwherein said gate electrode is elongated in a direction parallel to a direction in which said collector regions, said base region, and said emitter region are arranged.