Patent ID: 6209086
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A method for controlling interrupts and exceptions in a fast response time pipelined processor, comprising thc following steps;a) if a pipeline processing instruction cycle begins with a branch instruction, and said branch instruction has reached an instruction boundary, said instruction boundary being a memory access stage, and a branch is taken, or if an instruction located at a target address of a branch instruction has not yet reached an instruction boundary, storing said target address of said branch instruction at a first part of a working space,otherwise, storing a first return address of a first interrupt or exception at said first part of said working space,b) fetching a service routine starting address of said first interrupt/exception and executing a first instruction of said service routine at said starting address,c) completing the execution of said first interrupt/exception service routine, andd) returning to either said target address of said branch instruction or said first interrupt/exception starting address, whichever address having been previously stored at said first part of said working space,wherein said fast response time pipelined processor processes said interrupts and exceptions within a pipeline stage at the time said interrupts and exceptions occur.