Patent ID: 7393746
Filing Date: 2008-07-01
Classification: H01L

Abstract:
1. A method of forming an integrated circuit transistor, said method comprising: forming a gate conductor over a substrate; forming spacers on sides of said gate conductor; implanting an impurity into exposed regions of said substrate not protected by said gate conductor and said spacers; forming a silicide on surfaces of said exposed regions of said substrate; forming a protective layer over said silicide, said spacers, and said gate conductor; forming a non-conformal sacrificial layer over said protective layer, wherein said non-conformal sacrificial layer comprises relatively thinner regions that are over said spacers and relatively thicker regions that are over said substrate; partially etching said non-conformal sacrificial layer such that said relatively thinner regions of said non-conformal sacrificial layer that are over said spacers are completely removed and said relatively thicker regions of said non-conformal sacrificial layer that are over said substrate are not removed, wherein said partially etching of said non-conformal sacrificial layer exposes portions of said protective layer that cover said spacers; removing said portions of said protective layer that cover said spacers such that said spacers are exposed and said silicide is not exposed; and removing said spacers without affecting said silicide.