Patent ID: 6100573
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A structure of a bonding pad for a semiconductor device comprising:a substrate;an insulation material, formed over the substrate;a plurality of first metal layers formed in the insulation material, wherein the first metal layers are separated by the dielectric layer for stress release;a plurality of second metal layers formed in the insulation material and above the first metal layers, wherein the second metal layers are separated by the insulation material for stress release;a plurality of plugs, formed between the first metal layers and the second metal layers, wherein the plugs are used for connecting the first metal layers with the second metal layers;a third metal layer, formed over the dielectric layer; anda plurality of second plugs, formed between the second metal layers and the third metal layer, wherein the second plugs are used form connecting the second metal layers with the third metal layer.