Patent ID: 7190755
Filing Date: 2007-03-13
Classification: H03K,H03L

Abstract:
1. A phase-locked loop (PLL) circuit comprising: a phase/frequency detector; a voltage controlled oscillator having a plurality of signal taps, the signal taps being separated from one another by substantially uniform delays; a feedback multiplexer for selecting one of the signal taps, the feedback multiplexer feeding back to the phase/frequency detector a signal from the selected tap; and an output multiplexer for selecting one of the signal taps as an output signal of the phase-locked loop; wherein: when the output multiplexer selects a first one of the signal taps and the feedback multiplexer selects a second one of the signal taps, the output signal has a phase that is one of (a) retarded, and (b) advanced, relative to an input clock signal by an even multiple of the substantially uniform delay.