Patent ID: 6410958
Filing Date: 2002-06-25
Classification: H01L

Abstract:
A semiconductor apparatus comprising:a semiconductor substrate of a first conductivity type having a first main surface and a second main surface; a plurality of element isolation regions each formed to have a predetermined depth DT from said first main surface of said semiconductor substrate, and formed by filling a plurality of trenches with an insulator; a laterally three-layered pillar formed among said plurality of element isolation regions with a width WP and in a meshed planar shape, said three-layered pillar including a first pillar layer and a second pillar layer each being of said first conductivity type which contact two adjacent element isolation regions out of said plurality of element isolation regions over a depth direction, respectively, said three-layered pillar including a third pillar layer of a second conductivity type formed between said first pillar layer and said second pillar layer, and said three-layered pillar having a relation of 3.75&lE;DT/WP&lE;60 between said width WP of said three-layered pillar and said depth DT of each of said plurality of element isolation regions; a base region of said second conductivity type formed on an upper surface of said third pillar layer of said second conductivity type; a source region of said first conductivity type selectively formed on an upper surface of said base region; a gate electrode formed on said base region between said source region and an upper surface of said first pillar layer or said second pillar layer in an insulating manner; and a drain layer of said first conductivity type formed on said second main surface of said semiconductor substrate, and contacting a lower surface of said three-layered pillar.