Patent ID: 6304998
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A method of conducting logic simulation of an integrated circuit device, wherein a macro containing logic circuits formed therein is included in a chip including a plurality of cells, said method comprising:characterizing the macro by determining a first delay parameter of an input terminal of an internal cell of the macro connected to the input terminal of said macro, and a second delay parameter of an output terminal of an internal cell of the macro connected to the output terminal of said macro;determining delay time data for a whole logic circuit including the plurality of cells and the macro, in accordance with: delay parameters determined for said macro, wherein said first delay parameter is taken as an input terminal delay parameter and said second delay parameter is taken as an output terminal delay parameter; delay parameters determined for said plurality of cells; and connection data for said whole logic circuit;merging said determined delay time data for the whole logic circuit and internal delay time data for said macro, said internal delay time data for said macro being read from a library; andsimulating logic for said whole logic circuit in accordance with the merged delay time data.