Patent ID: 7203817
Filing Date: 2007-04-10
Classification: G06F

Abstract:
1. A processor comprising: i. A queue configured to store one or more entries identifying a cache miss, the one or more entries including a destination register field to identify a destination register associated with the cache miss and a tag associated with each destination register field to identify a fill corresponding to a cache miss for an entry; and ii. A control circuit coupled to the queue, wherein the control circuit is configured to detect a load miss of a load instruction in a load/store pipeline, the load/store pipeline being separate from an integer instruction pipeline and a separate floating point instruction pipeline, and wherein the control circuit is configured to enter into a stall state and inhibit issuance of instructions to the integer and floating point instruction pipelines to prevent replay of integer and floating point instructions dependent on the load miss, the control circuit to couple a destination register value to the queue associated with the load miss, in which the queue is to respond with a fill tag associated with the destination register, the control circuit to store the fill tag in a miss tag register and to compare the fill tag in the miss tag register with fill tags of fill data being returned, wherein when a returned fill tag matches the fill tag in the miss tag register, the integer and floating point pipelines exit the stall state.