Patent ID: 8471614
Filing Date: 2013-06-25
Classification: H03L

Abstract:
1. A phase locked loop control system comprising: a reference clock input for receiving a reference clock signal; a digital controlled oscillator configured to output an adjustable clock signal; a digital detector coupled between the reference clock input and an input of the controlled oscillator, the detector coupled to an output of the oscillator and configured for applying control signals to the oscillator for setting output operating signal frequency in accordance with detected frequency of the oscillator output clock signal; and a counter coupled to the oscillator output; wherein: the digital detector comprises a control signal generator configured to generate a plurality of binary control signals respectively output at a plurality of control signal generator output terminals, a comparator having a first comparator input coupled to the reference clock input, a second comparator input coupled to the counter, and a comparator output coupled to the control signal generator; and the oscillator comprises a plurality of decoder logic cells having inputs respectively coupled to the control signal generator output terminals; wherein the phase of the output signal is selectively adjusted by the digital detector control signals during each input clock cycle.