Patent ID: 8053341
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having openings to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has an opening to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming a SNC plug to fill the opening of the second insulation pattern, wherein the buffer layer is formed of polysilicon and the SNC plug is formed of a metallic material having a low specific resistance.