Patent ID: 7609542
Filing Date: 2009-10-27
Classification: G11C

Abstract:
1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a static random access memory (SRAM) cell including a static latch defined by a pair of parallel reverse polarity connected inverters; a pair of access transistors; said pair of access transistors respectively connected between a true side of the static latch and a true bitline input, and a complement side of the static latch and a complement bitline input; independent left and right wordlines providing a respective gate input to said pair of access transistors; one side of the static latch, where the access transistor is coupled to, being connected to voltage supply; a plurality of the SRAM cells being assembled together to define a SRAM base block; and a plurality of said SRAM base blocks being connected together to form the SRAM read PSRO.