Patent ID: 8429355
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. An information processor system comprising: a memory device; a memory control device controlling an operation of the memory device; a plurality of bus masters each capable of giving access to the memory device through the memory control device; and an access arbitrating device capable of arbitrating a plurality of access requests from the plurality of bus masters, wherein the memory control device includes a buffer capable of accepting the plurality of access requests from the plurality of bus masters, wherein the memory control device transmits vacant information which indicates a vacant state of the buffer to the access arbitrating device when an access request can be accepted by the buffer, and in response the access arbitrating device transmits the access request to the memory control device, wherein the memory control device transmits time information to the access arbitrating device, the time information indicating a start time when a data transfer from the memory device or to the memory device will be started when the access request transmitted from the access arbitrating device is accepted by the buffer of the memory control device, and wherein the access arbitrating device transmits the time information to the bus master from which the access request issued.