Patent ID: 8039320
Filing Date: 2011-10-18
Classification: H01L,Y10T

Abstract:
1. A method of manufacturing a packaged integrated circuit comprising: connecting a bond wire from a first trace on a substrate to a first bond pad on a chip to couple a first signal to the chip; the first trace terminating at a first via; connecting a second bond wire from a second trace on the substrate adjacent the first trace with no intervening traces therebetween to a second bond pad on the chip to couple a second signal to the chip; the second trace terminating at a second via up to one ball pitch from the first via; extending the first trace toward the first via parallel to a first line from the first via center to the second via center; connecting a third bond wire from a third trace on the substrate adjacent the second trace with no intervening traces therebetween to a third bond pad on the chip to couple a third signal to the chip; the third trace terminating at a third via; and connecting a fourth bond wire from a fourth trace on the substrate adjacent the third trace with no intervening traces therebetween to a fourth bond pad on the chip to couple a fourth signal to the chip; the fourth trace terminating at a fourth via up to one ball pitch from the third via; extending the third trace toward the third via perpendicular to a second line from the third via center to fourth via center, the second line being perpendicular to the first line; whereby the first and second traces form a first trace pair that is optimized to carry first and second signals that are differential to one another and the third and fourth traces form a the second trace pair that is optimized to carry third and fourth signals that are differential to one another.