Patent ID: 6137130
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A capacitor over bit line, (COB), DRAM structure, on a semiconductor substrate, featuring a straight bit line shape, and a storage node contact hole, through the straight bit line shape, comprising:polycide gate structures, on a gate insulator layer, capped with an overlying silicon nitride layer, and with first silicon nitride spacers on the sides of the polycide gate structures;source and drain regions in said semiconductor substrate, between said polycide gate structures;a first polysilicon contact plug, located between a first group of polycide gate structures, overlying a first source and drain region, and a second polysilicon contact plug, located between a second group of polycide gate structures, overlying a second source and drain region;a first insulator layer, with a bit line contact hole in said first insulator layer, exposing the top surface of said first polysilicon contact plug;a bit line contact structure, in said bit line contact hole, contacting said first polysilicon contact plug;a straight bit line shape, on said first insulator layer, contacting underlying said bit line contact structure, with said straight bit line shape comprised of polysilicon at a thickness between about 800 to 1200 Angstroms, and with said straight bit line shape comprised with a width between about 0.20 to 0.25 um, and with tungsten or tungsten silicide spacers located on the sides of said straight bit line shape, with said spacers at a thickness between about 400 to 800 Angstroms;a second insulator layer on said straight bit line shape, and on said first insulator layer, in regions in which said first insulator layer is not covered by said straight bit line shape;a storage node contact hole, in said second insulator layer, in said straight bit line shape, and in said first insulator layer, exposing the top surface of said second polysilicon contact plug, with the diameter of said storage node contact hole, wider in said straight bit line shape, than in said second insulator layer, and in said first insulator layer;second silicon nitride spacers on the sides of said storage node contact hole, with second silicon nitride spacers thicker on sides of said straight bit line shape, than on sides of said second insulator layer, and the sides of said first insulator layer; anda storage node structure, on the top surface of said second insulator layer, and completely filling said storage node contact hole, overlying and contacting, said second polysilicon contact plug.