Patent ID: 6797612
Filing Date: 2004-09-28
Classification: H01L,Y10S

Abstract:
A method of fabricating a chalcogenide memory cell, comprising:applying a layer of first material onto a conductive substrate material; forming an edge feature in said layer of said first material; applying a layer of an insulative material onto said edge feature of said layer of said first material; applying a layer of a third material onto said layer of said insulative material; removing a portion of said layer of said third material; removing a portion of said layer of said insulative material to define a pore in said layer of said insulative material; applying a layer of first conductive material into said pore to define an electrode in said layer of said insulative material, wherein said first conductive material comprises at least one of Ti, and TiCxNy; applying a layer of a chalcogenide material onto said electrode; and applying a layer of a second conductive material onto said layer of said chalcogenide material.