Patent ID: 6090667
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of;selectively forming a first insulating film for element isolation on a semiconductor substrate having one conductivity type;forming a floating gate electrode on a surface of a portion of said semiconductor substrate, where said first insulating film is not formed, through a first gate insulating film;forming a word line of a memory cell on said floating gate electrode through a second gate insulating film;forming an opening portion in said first insulating film to be self-aligned with an end portion of said word line, with such a depth to expose said surface of said semiconductor substrate;forming a diffusion layer having an opposite conductivity type by introducing an impurity having the opposite conductivity type to a surface of a portion of said semiconductor substrate which is exposed through said opening portion;forming a second insulating film on said diffusion layer, said word line, and said first insulating film;forming a common contact hole in said second insulating film to extend across said end portion of said word line and said diffusion layer, said common contact hole being formed with such a depth to reach said diffusion layer while exposing said end portion of said word line; andfilling said common contact hole with a metal plug which electrically connects said diffusion layer and said end portion of said word line.