Patent ID: 8310860
Filing Date: 2012-11-13
Classification: G11C,H01L

Abstract:
1. An integrated circuit containing an SRAM array, comprising: a substrate of said integrated circuit; an SRAM cell row disposed in said SRAM array, said SRAM cell row area containing a plurality of rows of SRAM cells; a strap row disposed in said SRAM array and located adjacent to said SRAM cell row; a layer of field oxide disposed at a top surface of said SRAM array; a first instance of a first polarity well of a first conductivity type disposed in said substrate, said first instance of said first polarity well extending through said SRAM cell row and said strap row; a second instance of said first polarity well of said first conductivity type disposed in said substrate, said second instance of said first polarity well extending through said SRAM cell row and said strap row; a second polarity well of a second conductivity type disposed in said substrate at a location between said first instance of said first polarity well and said second instance of said first polarity well, said second conductivity type being opposite from said first conductivity type; a well tap active area located in said strap row and disposed within an opening in said layer of field oxide, said well tap active area extending across said second polarity well located within said strap row, said well tap active area also partially overlapping said first instance of said first polarity well located within said strap row and said second instance of said first polarity well located within said strap row; a tap layer having said first conductivity type disposed in said well tap active area, said tap layer partially overlapping said first instance of said first polarity well so as to provide an electrical connection to said first instance of said first polarity well, said tap layer also partially overlapping said second instance of said first polarity well so as to provide an electrical connection to said second instance of said first polarity well; and a well contact plug located on a top surface of said tap layer in said well tap active area, so that a combination of said tap layer and said well contact plug forms a well contact structure.