Patent ID: 6878586
Filing Date: 2005-04-12
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device comprising: forming a gate insulating film on a substrate; forming a gate electrode on said gate insulating film; forming impurity diffusion layers in said substrate for both sides of said gate electrode; forming a first insulating film on said gate electrode and forming a side wall on said gate electrode; forming a contact hole by a self-aligned process using said side wall as a self-align mask; forming conductor layers in said contact hole connecting said impurity diffusion layers, wherein said conductor layers are substantially the same height; forming a bit line on one of said conductor layers connecting one of said impurity diffusion layers; forming a second insulating film on said bit line; forming a lower electrode of a capacitor connecting the other of said impurity diffusion layers through the other of said conductor layers on said second insulating film; and forming a capacitor insulating film and plate electrode on said lower electrode.