Patent ID: 6287948
Filing Date: 2001-09-11
Classification: H01L,Y10S

Abstract:
A semiconductor device having a first region, a second region and a border region between the first region and the second region, the semiconductor device comprising:an interlayer dielectric layer covering at least the first region and the second region;a first wiring layer located in the first region, the first wiring layer defining a relatively small pattern;a second wiring layer located in the second region, the second wiring layer defining a larger pattern larger than the small pattern;a first dummy pattern formed in the first region; anda second dummy pattern formed in the border region,wherein the interlayer dielectric layer includes a planarization silicon oxide film, the thickness of the interlayer dielectric layer located over the first wiring layer is smaller than the thickness of the interlayer dielectric layer located over the second wiring layer such that a global height difference occurs in the border region between the first region and the second region.