Patent ID: 6699763
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A method for fabricating an integrated circuit, comprising the steps of:forming a plurality of gate electrodes over a semiconductor body; forming an etch stopping layer over said gate electrodes and said semiconductor body; forming a layer comprising germanium over said etch stopping layer; forming a first mask layer over said semiconductor body exposing a first region of said semiconductor body and covering a second region of said semiconductor body; anisotropically etching a portion of said of said layer comprising germanium exposed by said first mask layer to form first disposable spacers separated from edges of said gate electrodes by said etch stopping layer; implanting first source/drain regions in said first region using said first mask layer and said first disposable spacers as an implant mask; removing said first disposable spacers; implanting first drain extension regions in said semiconductor body using said first mask layer as an implant mask after removing said first disposable spacers; and removing said first mask layer.