Patent ID: 6376313
Filing Date: 2002-04-23
Classification: H01L

Abstract:
An integrated circuit formed in a substrate of semiconductor material, the integrated circuit having at least two vertical MOS transistors and comprising:a trench formed in the substrate having a sidewall lying opposite a second sidewall wherein the first and second sidewalls are provided with a gate dielectric; a first MOS transistor having a first source/drain region adjacent an upper region of the first sidewall of the trench; a second MOS transistor having a first source/drain region adjacent an upper region of the second sidewall of the trench wherein the second MOS transistor lies opposite the first MOS transistor; a second source/drain region formed partly of both the first MOS transistor and the second MOS transistor, the second source/drain region adjacent a floor of the trench and having a floor insulating material formed thereon; a first gate electrode of the first MOS transistor formed along the first sidewall of the trench, wherein the first gate electrode is insulated from the second source/drain region via the floor insulating material; a second gate electrode of the second MOS transistor formed along the second sidewall of the trench, wherein the second gate electrode is insulated from the second source/drain region via the floor insulating material, and wherein the second and first gate electrodes are not electrically connected; and a conductive layer formed above the first source/drain regions of the first and second MOS transistors, wherein parts of the conductive layer are respectively contacted with the first and second gate electrodes such that the first and second gate electrodes may be individually driven.