Patent ID: 8971139
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A device comprising: a plurality of first lines; a plurality of memory cells each connected to an associated one of the first lines; a plurality of second lines; a plurality of first switches each electrically connected between an associated one of the first lines and an associated one of the second lines; a plurality of first sense amplifiers each electrically connected to an associated one of the second lines; a plurality of second switches each connected between associated two ofthe second lines that are adjacent to each other; a plurality of third switches each inserted between an associated one of the second lines and an associated one of the first sense amplifiers; and a plurality of inverting amplifiers each connected to an associated one of the second lines through an associated one of the third switches and a plurality of fourth switches each connected between an associated one of the inverting amplifiers and an associated one of the second lines.