Patent ID: 6853229
Filing Date: 2005-02-08
Classification: H03K

Abstract:
1. A circuit comprising: a first clocked latch having an input coupled to an input signal, the first clocked latch to capture a value at its input when triggered by a first clock signal; an inverter having an input coupled to an input signal, the inverter to invert the input signal; a second clocked latch having an input coupled to an output of the inverter, the second clocked latch go capture a value at its input when triggered by a second clock signal; and a differential mode circuit having a first input directly connected to an output of the first clocked latch and a second input directly connected to an output of the second clocked latch, the differential mode circuit containing circuitry to convert signals at its inputs into a differential mode signal; wherein the first and second clocked latches share a common design, and each clocked latch comprising: a first clocked inverting buffer having ma input directly connected to a latch input, the first clocked inverting buffer to invert a signal at its input when clocked by a first clock signal; an inverting buffer having an input directly connected to an output of the first clocked inverting buffer, the inverting buffer to invert a signal at its input; and a second clocked inverting buffer having an input directly connected to an output of the inverting buffer and an output directly connected to the input of the inverting buffer and also directly connected to the output of the first clocked inverting buffer, the second clocked inverting buffer to invert a signal at its input when clocked by a second clock signal, wherein the output of the clocked latch consists of a node that is directly connected to the output of the first clocked inverting buffer, the input of the inverting buffer and the output of the second clocked inverting buffer.