Patent ID: 6717224
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A memory cell structure comprising:a gate stack having a tunneling dielectric and a floating gate formed on a substrate, wherein the substrate has a trench to separate the gate stack; a source/drain region formed in the substrate and adjacent to the gate stack; a plurality of spacers formed on sidewalls of the gate stack and on the source/drain regions, wherein a top of the spacers is higher than a top of the gate stack; a plurality of isolation structures filled into the trench in the substrate to isolate the gate stack, wherein the isolation structures is raised up to the spacers but is lower than the top of the spacers; a conductive layer formed on the floating gate of the gate stack, wherein the conductive layer is conformal to a topographic surface of the spacers and extends to a portion of a top surface of the isolation structure; a dielectric layer formed over the substrate; and a control gate formed on the dielectric layer.