Patent ID: 8140742
Filing Date: 2012-03-20
Classification: G06F,G11C,Y02D

Abstract:
1. A system including non-Flash re-writeable non-volatile memory, comprising: a semiconductor substrate including circuitry fabricated on the semiconductor substrate, the circuitry including a processor and a memory controller in electrical communication with each other; a memory plane in direct contact with and fabricated directly above the semiconductor substrate; at least one re-writeable two-terminal non-volatile cross-point memory array embedded in the memory plane and including a plurality of first conductive array lines orthogonally oriented to a plurality of second conductive array lines to form a plurality of cross-points, the plurality of first and second conductive array lines are in electrical communication with the memory controller; and a plurality of re-writeable non-volatile two-terminal memory elements, each memory element is positioned between one of the cross-points and has a first terminal directly electrically coupled with a first conductive array line at its respective cross-point and a second terminal directly electrically coupled with a second conductive array line at its respective cross-point, wherein the memory controller is specifically configured to perform data operations on the at least one re-writeable two-terminal non-volatile cross-point memory array without having to perform an erase operation prior to a write operation and to perform random access data operations on the at least one re-writeable two-terminal non-volatile cross-point memory array at a data granularity ranging from a single bit of data in a single memory element to at least one block of data in a subset of the plurality of re-writeable non-volatile two-terminal memory elements, and the memory controller is configured to perform at least some data operations on the at least one re-writeable two-terminal non-volatile cross-point memory array using a file structure including a header section, a data section, and a footer section, and the footer section includes error correcting code (ECC) and the header section, the footer section, or both are stored in one or more portions of the at least one re-writeable two-terminal non-volatile cross-point memory array other than the data section.