Patent ID: 9184269
Filing Date: 2015-11-10
Classification: B82Y,H01L

Abstract:
1. A method for forming a semiconductor arrangement, comprising: forming a first silicon and silicon germanium stack over a substrate, the first silicon and silicon germanium stack comprising a first silicon layer and a first silicon germanium layer; forming a first source region adjacent to a first side of the first silicon and silicon germanium stack; forming a first drain region adjacent to a second side of the first silicon and silicon germanium stack; oxidizing the first silicon and silicon germanium stack forming a first germanium nanowire channel, the oxidizing comprising transforming the first silicon layer and silicon of the first silicon germanium layer into a silicon oxide region, the first germanium nanowire channel formed between the first source region and the first drain region; removing the silicon oxide region; forming a first gate structure around the first germanium nanowire channel forming a first nanowire transistor; and forming a second nanowire transistor comprising a first silicon nanowire channel.