Patent ID: 6639870
Filing Date: 2003-10-28
Classification: G11C

Abstract:
An address transition detecting circuit, comprising:a first detecting means for detecting a first transition of an address buffer signal and outputting an external address signal having a first phase and a first pulse width; a first control means for controlling a flow of current of the first detecting means so that the output of the first detecting means has a second phase different from the first phase and a second pulse width equal to the first pulse width; a second detecting means for detecting a second transition of the address buffer signal; a second control means for controlling a flow of current of the second detecting means so that an output of the second detecting means has a third phase different from the first phase and a third pulse width equal to the first pulse width; and an output means for inverting one of the output of the first detecting means and the output of the second detecting means to output an address transition detecting signal.