Patent ID: 6518126
Filing Date: 2003-02-11
Classification: G11C,H01L

Abstract:
A method of forming a trench split-gate non-volatile flash memory cell structure, comprising the steps of:forming a P-type substrate; forming a deep N-well layer over the P-type substrate; forming a shallow P-well layer over the deep N-well layer; forming a gate region above the shallow P-well layer and marking out a drain region and an auxiliary gate region on each side of the gate region; forming a spacer on each side of the gate region; forming a trench in the deep N-well layer and the shallow P-well layer within the auxiliary gate region; forming an oxide layer inside the trench; performing a heavy dopant implantation to implant ions into the deep N-well layer and the drain region of the shallow P-well layer underneath the trench, thereby forming a source terminal and a drain terminal; depositing polysilicon material to fill the trench, thereby forming a trench auxiliary gate; forming a first polysilicon layer over the gate region, thereby forming a floating gate; forming an isolation layer over the first polysilicon layer, the drain region and the filled trench region; and forming a second polysilicon layer over the isolation layer, thereby forming a control gate.