Patent ID: 8324059
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; performing an etching process to form at least one recess within the semiconductor substrate beside the gate structure; performing a thermal treatment process on the recess in a gas atmosphere comprising an inert gas at a first temperature; after performing the thermal treatment process, wet-cleaning the recess; after wet-cleaning the recess, performing a pre-bake process on the recess at a second temperature lower than the first temperature; after performing the pre-bake process, performing an epitaxy growth process at a third temperature lower than the first temperature to form a silicon-containing epitaxial layer in the recess; and during or after the epitaxy growth process, incorporating a dopant into the silicon-containing epitaxial layer to form a source/drain region.