Patent ID: 8732385
Filing Date: 2014-05-20
Classification: G06F,G11C

Abstract:
1. A non-volatile memory, comprising: a memory cell array configured to store a plurality of pages of data, respective pages of data including a data portion and a redundant portion, the redundant portion including a respective logical address and a respective physical address corresponding to a next logical address; a page buffer configured to store a respective page of data; a control circuit including an address register; and a data cache, wherein the control circuit is configured transfer a first page of data from the memory cell array to the page buffer with a first access command, configured to output a first physical address directly to the address register before reading out the first page of data, configured to transfer the first page of data from the page buffer to the data cache, configured to transfer a second page of data from the memory cell array to the page buffer while the first page of data is read out from the data cache, and further configured to output the first physical address directly to the address register at the same time that the first page of data is transferred from the page buffer to the data cache.