Patent ID: 6754094
Filing Date: 2004-06-22
Classification: G11C

Abstract:
A random access memory device, comprising:a memory array of memory cells organized into rows and columns, including a plurality of word lines and bit lines, each row of memory cells being coupled to a word line and each column of memory cells being coupled to a bit line; sense amplifier circuitry coupled to the bit lines and being selectively disabled; address decode circuitry for receiving an address value and asserting a row line associated therewith; and test circuitry, coupled to at least one bit line, for placing on an external pad of the integrated circuit chip a current level corresponding to a voltage level appearing on the at least one bit line, the test circuitry comprising: a plurality of pairs of series-connected transistors coupled between the external pad and a reference voltage level, each pair of series-connected transistors including a first transistor having a control terminal coupled to a distinct one of the plurality of bit lines.