Patent ID: 7882411
Filing Date: 2011-02-01
Classification: G06F

Abstract:
1. A shift register comprising: a plurality of blocks, each of the plurality of blocks includes a first shift unit circuit for shifting a first signal in sequence and in synchronization with a clock signal and outputting a second signal, a second shift unit circuit for shifting the second signal in sequence and in synchronization with the clock signal and outputting a third signal, and a unit control circuit that receives the first signal, the second signal, and the third signal for specifying an operation period for which any one of the first shift unit circuit and the second shift unit circuit is operated and for supplying the clock signal to the first shift unit circuit and the second shift unit circuit in the specified period, on the basis of the first signal, the second signal, and the third signal, the unit control circuit has (1) clock control signal generating means for performing a logical sum operation of the periods for which the the first signal, the second signal, and the third signal of the first shift unit circuit and the second shift unit circuit become an active state and for generating a clock control signal for specifying the operation period based on operation results, and (2) supply means for supplying the clock signal to the of the first shift unit circuit and the second shift unit circuit according to the clock control signal, the clock control signal generating means has a plurality of NOR circuits, and a NAND circuit for performing the logical sum operation of output signals output from the plurality of NOR circuits and outputting the result as the clock control signal, and input terminals of the plurality of NOR circuits are supplied with the first signal, the second signal, and the third signal of the first shift unit circuit and the second shift unit circuit, respectively.