Patent ID: 7570517
Filing Date: 2009-08-04
Classification: G11C

Abstract:
1. A NAND flash memory device, comprising: a memory block comprising a plurality of first NAND strings and a second NAND string arranged between a pair of adjacent NAND strings among the plurality of first NAND strings; a plurality of first bit lines respectively electrically connected to the plurality of first NAND strings; a second bit line corresponding to the second NAND string; a common source line electrically connected to the first NAND strings and to the second NAND string; and a strapping line electrically connected to the common source line via the second bit line; wherein the second bit line comprises a first bit line segment electrically connected to the common source line via a first contact, a second bit line segment electrically connected to the second NAND string via a second contact, and a third bit line segment arranged between the first contact and the second contact and electrically separated from the first and second bit line segments.