Patent ID: 8762596
Filing Date: 2014-06-24
Classification: G06F

Abstract:
1. A direct memory access controller comprising: a first programmable register configured to store a first value, wherein the first value defines a start address of a single data transaction; a second programmable register configured to store a second value that is different than the first value, wherein the first value and the second value together define a beginning and an end of a block of data, respectively, to be transferred; a third programmable register configured to store a third value that is different than the first value and the second value, wherein the third value is utilized to determine whether to continue to repeatedly transfer the block of data; first, second, and third temporary registers; restart logic configured to reset values of the first, second, and third temporary registers to the first, second, and third values in the first, second, and third programmable registers, respectively; and transfer control circuitry configured to repeatedly transfer the block of data defined by the first and second temporary registers to a destination address until the third value indicates that the repeated transfer of the block of data should cease.