Patent ID: 6411133
Filing Date: 2002-06-25
Classification: H03K

Abstract:
A semiconductor device circuit comprising:a first MISFET of an n-type which is connected between a node of a signal transmission line and a low-potential source and uses a poly-crystalline silicon layer as an active region, the first MISFET having a poor saturation characteristic, due to use of the poly-crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range; a second MISFET of the n-type which is connected between the node and the first MISFET and uses a poly-crystalline silicon layer as an active region, the second MISFET having a poor saturation characteristic, due to use of poly-crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range, and the second MISFET being configured to suppress variations in voltage at the node caused by the poor saturation characteristic of the first MISFET; and a first bias circuit portion configured to apply a bias voltage to a gate of the second MISFET, wherein a combination of the first and second MISFETs and the first bias circuit portion is arranged to function as an alternative to one MISFET of the n-type using a single-crystalline silicon layer as an active region.