Patent ID: 6133861
Filing Date: 2000-10-17
Classification: G11B,H03K,H03L

Abstract:
A circuit for supplying a selected duration of delay with respect to transitions of a clock signal from a first state to a second state, the circuit comprising:a delay cell having inputs connected to receive the clock signal and a feedback signal, and being disposed to supply a third signal at an output port thereof having third and fourth states, said delay cell delaying transitions from the third state to the fourth state by a selected duration with respect to transitions of the clock signal from the first state to the second state in response to the average voltage of the feedback signal;a charge pump having inputs connected to receive the third signal and a control signal for specifying the selected duration, and having an output connected to supply current in a direction responsive to the state of the third signal and with an amplitude related to the control signal; anda capacitor connected to receive the current from the charge pump for supplying the feedback signal as the voltage across the capacitor.