Patent ID: 6836854
Filing Date: 2004-12-28
Classification: G06F,H03L,H04J

Abstract:
A desynchronizer for a data signal extracted from a synchronous message, the data signal including a gapped clock signal having a first frequency, a gapped data signal including a plurality of data and a plurality of gaps interspersed within the plurality of data and an increment pointer adjustment signal and a decrement pointer adjustment signal, the desynchronizer comprising:a gap regulator module receiving the gapped clock signal, the gapped data signal, and a reference clock signal, the gap regulator module configured and arranged to redistribute the plurality of gaps to a plurality of new gapped positions uniformly distributed throughout the plurality of data forming a plurality of uniformly gapped data, the gapped regulator providing as an output a plurality of new gapped position indicators corresponding to a plurality of determined gapped positions and a stuff bit position indicator corresponding to a stuff opportunity bit position, and a uniformly gapped data signal including the uniformly gapped plurality of data; a pointer leak logic module receiving the plurality of new gap data position indicators, the stuff opportunity bit position indicator, and the uniformly gapped data signal from the gap regulator module and the increment and decrement pointer adjustment signals, the pointer leak logic module configured and arranged to determine a bit leak rate in response to the increment and decrement pointer adjustment signals and to modify the uniformly gapped data signal as a function of the bit leak rate over a predetermined period of time and to provide as an output a bit leak adjusted uniformly gapped data signal; and a phase locked loop receiving the bit leak rate adjusted uniformly gapped data signal from the bit leak logic module and a reference clock signal, the phase locked loop configured and arranged to provide as an output an ungapped smooth data signal and an ungapped smooth data clock signal.