Patent ID: 8466506
Filing Date: 2013-06-18
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a memory cell array region provided on the semiconductor substrate and having memory transistors for storing data arranged therein; a first dummy cell region provided on the semiconductor substrate and having first dummy cells not used for storing data arranged therein; and a second dummy cell region provided on the semiconductor substrate and having second dummy cells not used for storing data arranged therein, the first dummy cell region being provided between the memory cell array region and the second dummy cell region and including: first gate insulation layers provided on the semiconductor substrate; first floating electrode layers provided on the first gate insulation layers and forming the first dummy cells; and a first element isolation insulation layer formed to adjoin the first floating electrode layers and electrically isolating the first dummy cells from each other, a top surface of the first element isolation insulation layer being located at a height lower than top surfaces of the first floating electrode layers, the second dummy cell region including: second gate insulation layers provided on the semiconductor substrate and having a thickness larger than that of the first gate insulation layers; second floating electrode layers provided on the second gate insulation layers and forming the second dummy cells; and a second element isolation insulation layer formed to adjoin the second floating electrode layers and electrically isolating the second dummy cells from each other, a top surface of the second element isolation insulation layer being located at the same height as top surfaces of the second floating electrode layers, or at a height lower than the top surfaces of the second floating electrode layers and higher than the top surface of the first element isolation insulation layer, the first dummy cell region and the second dummy cell region including: a third element isolation insulation layer formed at a boundary between the first dummy cell region and the second dummy cell region and electrically isolating the first dummy cells and the second dummy cells from each other; a block insulation layer formed on the first element isolation insulation layer, the second element isolation insulation layer, the third element isolation insulation layer, the first floating electrode layers, and the second floating electrode layers; and a conductive layer formed on the first element isolation insulation layer, the second element isolation insulation layer, the third element isolation insulation layer, the first floating electrode layer, and the second floating electrode layer via the block insulation layer, and functioning as gates of the memory transistors, the third element isolation insulation layer having a top surface, the end portion of the top surface adjoining the first floating electrode layer being located at a height lower than the top surface of the first floating electrode layer, and the top surface of the third element isolation insulation layer having a gradient ascending from a side surface of the first floating electrode layer toward a side surface of the second floating electrode layer, and a distance between the end portion of the top surface of the third element isolation insulation layer adjoining the first floating electrode layer and the top surface of the first floating electrode layer is substantially larger than a distance between the end portion of the top surface of the third element isolation insulation layer adjoining the second floating electrode and the top surface of the second floating electrode layer.