Patent ID: 6044429
Filing Date: 2000-03-28
Classification: G06F,G11C

Abstract:
An integrated memory device having a read or write latency of N discrete time units where N is a real number greater than 1, comprising:a memory array;a command input terminal;a data bus;address input terminals;an output data path coupled to the memory array;a control circuit coupled to the command input terminal and responsive to a predetermined sequence of command signals at the command input terminal to produce a control signal indicative of either an anticipated data collision or an available read or write interval at the memory array; andan address path between the address input terminals and the memory array, the address path including an at least one interim address register, each of the interim address registers being configured to store a respective input address, each of the interim address registers being operative to retain the stored address in response to the control signal indicative of the anticipated data collision or to apply the address to the array in response to the control signal indicative of the available read or write interval at the memory array.