Patent ID: 7185269
Filing Date: 2007-02-27
Classification: G11B,H03M

Abstract:
1. A Viterbi decoding device with a dual-data input and a dual-data output, comprising: a branch metric calculating circuit performing branch metric calculation operations on two consecutive input data according to two sets of target levels, respectively, to obtain a plurality of branch metric values, wherein said two sets of target levels are obtained via a partial response channel PR(1,1,1,1) and are (−2,−1,0,1,2) and (−1.5,−1,0,1,1.5); an adder-comparator-selector unit coupled to said branch metric calculating circuit, performing accumulative additional operations of said branch metric values to obtain four groups of accumulated values, respectively, comparing said accumulated values in groups, and outputting two control signals and four least accumulated values according to the comparing results; a metric register unit coupled to said adder-comparator-selector unit, receiving and storing said four least accumulated values, and feeding back said four least accumulated values to said adder-comparator-selector unit to perform next accumulative addition operations; a survivor memory unit coupled to said adder-comparator-selector unit, recording a plurality of output-data state transition tracks in response to said two control signals; and a decision unit coupled to said metric register unit and said survivor memory unit, determining the combination of the two probable output-data state transition tracks as said consecutive output data according to said four least accumulated values.