Patent ID: 6255849
Filing Date: 2001-07-03
Classification: H03K

Abstract:
An on-chip method for self-modifying a programmable logic device (PLD), the PLD including a plurality of configurable logic blocks, a plurality of interconnect resources for selectively connecting the plurality of configurable logic blocks, and a memory circuit selectively connected to the interconnect resources, wherein the plurality of logic blocks are configured to implement a reconfigurable functional portion and a configuration control portion, wherein the reconfigurable functional portion is configured with first configuration data to perform an initial logic function, the method comprising:transmitting operation data from the reconfigurable functional portion to the configuration control portion using a first group of the plurality of interconnect resources;transmitting read instructions from the configuration control portion to the memory circuit using a second group of the plurality of interconnect resources; andtransmitting second configuration data from the memory circuit to the reconfigurable functional portion using a third group of the plurality of interconnect resources in response to the read instructions, thereby modifying the reconfigurable functional portion to perform a secondary logic function in accordance with the second configuration data.