Patent ID: 6936515
Filing Date: 2005-08-30
Classification: H01L

Abstract:
1. A reverse LDD method for fabricating a semiconductor device, comprising: a) providing a substrate having a periphery transistor region and a core memory cell region; b) forming a first source region and a first drain region in said substrate of said periphery transistor region exhibiting a channel width between said first source region and said first drain region; c) forming lightly doped drain (LDD) regions adjacent to said first source region and said first drain region in said periphery transistor region; d) concurrently with said forming LDD regions, forming a second source region and a second drain region in said core memory cell region; and e) depositing a sidewall spacer over said LDD regions of said periphery transistor region, and said second source and drain regions of said core memory cell region; and f) limiting formation of said sidewall spacer to allow space for the formation of a drain contact to said second drain region said core memory cell region, thereby isolating said formation of said drain contact to said second source region of said core memory cell region.