Patent ID: 8647969
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A method of manufacturing a memory device, the method comprising: forming a dielectric layer over a substrate; forming a charge storage element over the dielectric layer; etching the charge storage element; forming an inter-gate dielectric over the dielectric layer and the etched charge storage element; depositing a polysilicon layer over the inter-gate dielectric, where depositing the polysilicon control gate layer includes: planarizing the polysilicon layer to form a control gate; forming an interlayer dielectric on the control gate; planarizing the interlayer dielectric; forming, after forming the control gate and planarizing the interlayer dielectric, a contact hole through the planarized interlayer dielectric and the control gate; depositing a metal layer to fill the contact hole, the metal layer including a first type of metal; and forming an interconnect over the planarized interlayer dielectric, the interconnect including a second type of metal.