Patent ID: 8369130
Filing Date: 2013-02-05
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including plural mutually crossing first and second lines and memory cells arranged at intersections of said first and second lines, each memory cell containing a variable resistance element and a rectifier element connected in series; and a data write/erase circuit operative to apply a voltage required for data write/erase to said memory cell via said first and second lines, wherein said data write/erase circuit includes a first current limit circuit operative to limit the current flowing in a cathode-side line provided on a cathode side of said rectifier element, of said first and second lines, when an anode-side line provided on an anode side of said rectifier element, of said first and second lines, is applied with a voltage higher than a voltage applied to the cathode-side line; and a charge limit circuit operative to limit the amount of charge supplied to said memory cell at the time of data write/erase, said charge limit circuit including a capacitor operative to accumulate the certain amount of charge in accordance with a first control signal and discharge the accumulated charge to said memory cell in accordance with a second control signal.