Patent ID: 7739435
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A system for enhancing I2C bus data rate, comprising: a modulus register associable with a slave device and configured to contain a modulus; and data transfer logic associated with said modulus register and configured to transfer data from at least one memory location in said slave device to said I2C bus based on said modulus and a starting address and at least one acknowledgement signal received via said I2C bus; wherein a nonzero positive integer modulus defines the number of memory locations in a closed-ended range of memory locations, said starting address defines a starting address for said close-ended range and said data transfer logic repeatedly loops through said memory locations in said closed-ended range to transfer data from each of the memory locations in said closed-ended range to said I2C bus a plurality of times based on said at least one acknowledgement signal and wherein a modulus of zero defines an open-ended range of memory locations, said starting address defines a starting address for said open-ended range and said data transfer logic transfers data from each of the memory locations in said open-ended range to said I2C bus only a single time based on said at least one acknowledgement signal.