Patent ID: 6798186
Filing Date: 2004-09-28
Classification: G01R

Abstract:
A method of testing programmable delay chains in an integrated circuit, the method comprising:a) successively programming a first delay chain to a first sequence of delay settings; b) for each delay setting in the first sequence, successively programming a second delay chain to a second sequence of delay settings that sweep a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay; c) for each delay setting of the second delay chain in step b), applying a logic transition to inputs of the first and second delay chains and latching an output of one of the first and second delay chains as a function of an output of the other of the first and second delay chains to produce a sample value; and d) for each delay setting in the first sequence, determining whether the logic transition occurs in the sample values produced in step c) within an expected time window.