Patent ID: 8320213
Filing Date: 2012-11-27
Classification: G11C

Abstract:
1. A memory device comprising: a first memory array having a first edge and a second edge opposite to the first edge; a second memory array adjacent to the second edge of the first memory array; a first port pad adjacent to the first edge of the first memory array; a second port pad located opposite to the first edge of the first memory array, but not necessarily adjacent to the first memory array, wherein each of the first and second port pads includes one or more contacts for input and/or output, wherein the second port pad is adjacent to the second memory array, such that the second memory array is interposed between the second port pad and the first memory array; a first local data line configured to carry data for a portion of a first data path, wherein the first data path is between the first memory array and one of the contacts of the first port pad, wherein the first local data line is further configured to carry data for a portion of a third data path, wherein the third data path is between the second memory array and one of the contacts of the first port pad; and a second local data line configured to carry data for a portion of a second data path, wherein the second data path is between the first memory array and one of the contacts of the second port pad, wherein the second local data line is further configured to carry data for a portion of a fourth data path, wherein the fourth data path is between the second memory array and one of the contacts of the second port pad.