Patent ID: 7851859
Filing Date: 2010-12-14
Classification: H01L

Abstract:
1. A single transistor memory cell, comprising: a buried insulating layer on a semiconductor substrate; an active semiconductor pattern comprising a bulk region and an impurity region, stacked in sequence on the buried insulating layer; a recessed region passing through the impurity region, dividing the impurity region into a source region and a drain region, which are separated from each other, the recessed region comprising first and second sidewalls adjacent to the source and drain regions, respectively; a first insulating region positioned between the source region and the bulk region, and separated from the first sidewall of the recessed region; a second insulating region positioned between the drain region and the bulk region, and separated from the second sidewall of the recessed region; a gate electrode positioned within the recessed region, the gate electrode comprising a projecting portion that extends above an upper surface of the impurity region; a spacer covering sidewalls of the projecting portion of the gate electrode, the first and second insulating regions being self-aligned with an outside of the spacer and the gate electrode; and an upper insulating layer covering the active semiconductor pattern and the gate electrode, wherein the upper insulating layer is in direct contact with the buried insulating layer, the first insulating region and the second insulating region, wherein a bottom of the recessed region is disposed lower than the first and second insulating regions.