Patent ID: 7824968
Filing Date: 2010-11-02
Classification: H01L

Abstract:
1. A method of fabrication of a semiconductor transistor comprising the steps of: providing a substrate with a deep well having dopants of a second dopant type; forming a gate over the substrate, the gate having first and second sides and a channel under the gate; forming a first junction region in the substrate on the first side of the gate, the first junction region having dopants of a first dopant type with a first dopant concentration; forming a second junction region in the substrate on a second side of the gate adjacent the channel, the second junction region having dopants of the first type with a second dopant concentration, wherein the deep well comprises a depth deeper than the first and second junction regions, the deep well encompassing the first junction region and overlaps a portion of the second junction region without encompassing the second junction; forming a third junction region in the substrate adjacent the second junction region and spaced apart from the second side of the gate, the third junction region having dopants of the first type with a third dopant concentration, the second dopant concentration of the second junction region is less than the first and third dopant concentration of the first and third junction regions; forming at least one dummy gate over the second junction region; and forming a stress layer over the substrate and over the gate and at least one dummy gate, the stress layer creates a stress in the channel and in the second junction region, wherein the dummy gate is arranged to assist in distributing the stress of the stress layer over the second and third junctions to increase the stress exerted across the second junction region as compared to that without the at least one dummy gate to improve performance of the transistor.