Patent ID: 7423909
Filing Date: 2008-09-09
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device, comprising: a plurality of first word lines; a plurality of second word lines that are extended in parallel with the first word lines and are plurally assigned to the first word lines; a plurality of memory cells respectively connected with the second word lines; a plurality of bit lines that are extended in a direction orthogonal to the second word lines and are electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers that select or deselect the second word lines, wherein the word drivers comprise first MOSFETs of first conductivity type and second MOSFETs of second conductivity type connected in series, the sources of the first MOSFETs are connected with the ground potential of a relevant circuit, the drains of the first MOSFETs and second MOSFETs, connected in common, are connected with the second word lines, the sources of the second MOSFETs are used as first selection terminals, and the gates of the first MOSFETs and the second MOSFETs, connected in common, are used as second selection terminals, wherein the first selection terminals are supplied with first selection signals transmitted through the first word lines, wherein the second selection terminals are supplied with second selection signals formed using address signals for selecting the bit lines, wherein the first selection terminals of a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with voltage corresponding to a level at which second word lines are selected, wherein the first word lines are main word lines, wherein the second word lines are sub-word lines that are divided in the direction of extension of the main word lines and are plurally assigned in the direction of extension of bit lines, wherein the bit lines comprise complementary bit lines, wherein the memory cells comprise static memory cells constructed of: storage portions in which the inputs and outputs of two CMOS inverter circuits are cross-connected; and selection MOSFETs that are provided between the storage portions and the complementary bit lines and whose gates are connected with the sub-word lines, and wherein the second selection signals are selection signals that respectively correspond to a plurality of bit lines corresponding to sub-word lines divided in the direction of extension of the main word lines, wherein the first selection terminals of the word drivers are supplied with the output signals of first CMOS inverter circuits that are plurally connected in common in correspondence with sub-word lines disposed adjacently to one another and receive selection signals corresponding to the first selection signals, and wherein the second selection terminals of a plurality of the word drivers are supplied with drain output signals formed by a plurality of third MOSFETs of first conductivity type that are connected in series with resistance means provided on the power supply voltage side, whose sources are supplied in common with the input signals of the first CMOS inverter circuits, and whose gates are supplied with selection signals corresponding to the second selection signals.