Patent ID: 8078428
Filing Date: 2011-12-13
Classification: G06F

Abstract:
1. A method for analyzing a delay time distribution of an N-stage circuit, the method comprising: calculating, by a processor, maximum deviation delay time of a signal propagating through the circuit and basic delay time of the circuit; calculating, by the processor, a delay variation value of the N-stage circuit by using the mean square of differences between the maximum deviation delay time of the circuit and the basic delay time of the circuit taken over the N stages; generating, by the processor, the delay time distribution of the N-stage circuit as a normal distribution by using the calculated delay variation value; and calculating, by the processor, a sum of signal delay times through the N-stage circuit, wherein the number of stages, N, is obtained by dividing the sum of the signal delay times through the N-stage circuit by the signal delay time of a circuit stage having the longest signal delay time or the signal delay time of a kind of circuit largest in number.