Patent ID: 6016279
Filing Date: 2000-01-18
Classification: G11C

Abstract:
An isolation pre-charge circuit within a DRAM array to pre-charge portions a pair of bit lines within said DRAM array to a voltage level of a reference voltage source and to connect a selected DRAM cell to a latching sense amplifier, comprising:a) a first single pole double throw switch including a common terminal connected to one portion of one of the bit lines of the pair of bit lines, a first pole connect to the reference voltage source, a second pole connected to a first terminal of the latching sense amplifier and a first terminal of a pre-charge and equalization circuit, and a control terminal connected to a control circuit to selectively couple the common terminal to the first pole and the second pole; andb) a second single pole double throw switch including a common terminal connected to one portion of a second of the bit lines of the pair of bit lines, a first pole connect to the reference voltage source, a second pole connected to a second terminal of the latching sense amplifier and a second terminal of a pre-charge and equalization circuit, and a control terminal connected to a control circuit to selectively couple the common terminal to the first pole and the second pole.