Patent ID: 9075948
Filing Date: 2015-07-07
Classification: G06F

Abstract:
1. A method for optimizing circuits with a timing critical placement map comprising: using a computer, determining non-critical circuit components safe to be moved, wherein non-critical circuit components are circuits in which a change to its physical placement will not degrade the timing below an acceptable threshold or introduce a new timing violation; removing all non-critical circuit components from said timing critical placement map to generate a new partial placement map; optimizing critical circuit components in said new partial placement map free of all of said non-critical circuit components wherein said critical circuit components are a set of circuit components that are not non-critical circuit components; inserting new circuit components into said new partial placement map; reinserting all of said non-critical circuit components that were previously removed from said timing critical placement map into said new partial placement map; locking and fixing the critical circuit components, said critical circuit components include the inserted new circuit components; legalizing said non-critical circuit components which are unlocked while the critical circuit components are locked, the locking of the critical components prevents the legalizing step from changing the placements of the critical circuit components; and unlocking and reverse fixing the critical circuit components.