Patent ID: 9043583
Filing Date: 2015-05-26
Classification: G06F

Abstract:
1. A processor comprising: a register to store a source operand; a core coupled with the register, the core in response to an instruction, which indicates the source operand and a destination operand, to store non-adjacent floating point values of the source operand into a first plurality of non-adjacent floating point values of the destination operand and to store duplicates of the non-adjacent floating point values of the source operand into a second plurality of non-adjacent floating point values of the destination operand, each of the first plurality of floating point values of the destination operand being stored adjacent to one of the second plurality of floating point values of the destination operand, wherein the instruction does not explicitly specify that the non-adjacent floating point values of the source operand are to be stored into the first plurality of non-adjacent floating point values of the destination operand.