Patent ID: 7626883
Filing Date: 2009-12-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of sub blocks each having a plurality of memory cells arranged in rows and columns, each memory cell having storage data required for refresh; a power supply circuit for generating at least first and second voltages when activated, and stopping generation of the first and second voltages during a stand-by state subsequent to completion of burst refresh successively performed on said plurality of memory cells for holding the data of the memory cells, in a stand-by mode in which the storage data are held; a first global voltage line for commonly transmitting the first voltage from said power supply circuit to said plurality of sub blocks; a plurality of first local voltage lines, arranged corresponding to said plurality of sub blocks and coupled to said first global voltage line, each for receiving the voltage from said first global voltage line and transmitting the received voltage to a corresponding sub block; a second global voltage line for commonly transmitting the second voltage from said power supply circuit to said plurality of sub blocks; a plurality of second local voltage lines provided corresponding to the respective sub blocks; a plurality of voltage setting circuits, arranged corresponding to the respective sub blocks, each for setting a voltage of the second local voltage line arranged in a corresponding sub block to a voltage level corresponding to the second voltage on said second global voltage line selectively in accordance with a sub block selection signal; a global reference voltage line for commonly transmitting a fixed voltage to said plurality of sub blocks; a plurality of local reference voltage lines arranged corresponding to the respective sub blocks; a plurality of word lines, arranged corresponding to memory cell rows, each connected to the memory cells in a corresponding row in each sub block; a plurality of word line control circuits, arranged corresponding to the respective sub blocks, each including a plurality of word line drivers arranged corresponding to the respective memory cell rows in a corresponding sub block and driving the memory cells in corresponding rows to a selected state in accordance with a row selection signal, each word line driver including a pre-drive stage for generating a signal changing between a voltage on the local reference voltage line and a voltage on a corresponding first local voltage line in accordance with said row selection signal and a drive stage for setting a corresponding word line to a voltage level of one of the voltage on said corresponding first local voltage line and the voltage on a corresponding second local voltage line in accordance with an output signal from said pre-drive stage; and drive power supply control circuitry including a connection control circuit for isolating at least said global reference voltage line and said local reference voltage line from each other while connecting said first global voltage line and said first local voltage line to each other during the stand-by state in said stand-by mode, for suppressing voltage variation on said first local voltage line during said stand-by state.