Patent ID: 6057573
Filing Date: 2000-05-02
Classification: H01L

Abstract:
An integrated circuit memory comprising:(a) an array of memory cells arranged in rows and columns;(b) a plurality of wordlines each connected to plural cells in at least one respective row of said array;(c) a plurality of bitlines each connected to plural cells in at least one respective row of said array;(d) peripheral device circuits comprising wordline decoders located on opposite sides of said array; and(e) metal straps formed over said wordlines on an insulative layer running parallel with said wordlines and connected along their length to said wordlines by a plurality of metal contacts and at their ends to said wordline decoders;wherein said metal straps comprise an alternating sequence of serially interconnected metal line segments in at least two metallization levels, with interconnections formed through openings in an insulative layer separating said metallization levels;wherein said alternating sequence is reversed in phase between next adjacent metal straps such that on each respective metallization level, line segments become line gaps and line gaps become line segments;wherein at least one of said at least two metallization levels is formed over a globally planarized insulation layer; andwherein said metal straps are connected at their ends to said wordline decoders on opposite sides of said array in an alternating sequence by a line segment formed in one of said at least one of said at least two metallization levels formed over said globally planarized insulation layer.