Patent ID: 6096616
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A method for fabricating a transistor, comprising:patterning a gate conductor dielectrically spaced over a channel area within a semiconductor substrate between a source region and a drain region;forming, adjacent opposed sidewall surfaces of the gate conductor, a pair of spacers having a spacer lateral thickness;implanting a plurality of dopant species into said semiconductor substrate, wherein said implanting comprises at least:implanting, at a first energy and a first concentration, a first dopant species into the source and drain regions laterally spaced from the channel area by the spacer lateral thickness; andimplanting, at a second energy and a second concentration, a second dopant species into the source and drain regions laterally spaced from the channel area by the spacer lateral thickness, wherein the second energy is less than the first energy, the second concentration is greater than the first concentration, and implanting the second dopant species comprises forwarding the second dopant species into the semiconductor substrate at an angle greater than 0.degree. with respect to a surface normal of the semiconductor substrate; andannealing the semiconductor substrate following said implanting the plurality of dopant species, wherein said annealing causes lateral migration of said first dopant species by a first lateral distance and lateral migration of said second dopant species by a second lateral distance greater than the first lateral distance.