Patent ID: 6285212
Filing Date: 2001-09-04
Classification: H03K

Abstract:
A logic block in a field programmable gate array, comprising:a plurality of clusters of logic devices, at least one of said logic devices in each of said plurality of clusters having an input or an output;a first set of interconnect conductors entering said logic block from a first side and forming a programmable intersection with said input or said output of said at least one of said logic devices in each of said plurality of clusters;a second set of interconnect conductors entering said logic block from a second side and forming a programmable intersection with said input or said output of said at least one of said logic devices in each of said plurality of clusters, said first set of interconnect conductors forming a pairwise hardwired connection with said second set of interconnect conductors; andan interconnect conductor splitting extension disposed between said first set of interconnect conductors and said second set of interconnect conductors.