Patent ID: 6694449
Filing Date: 2004-02-17
Classification: G06F

Abstract:
A processor device, comprising:a clock generation unit; a processor unit connected to said clock generation unit; a main memory; a processor bus configured as a data and address bus for said processor unit and said main memory; a crossover bus to be connected to at least one further processor device; and a bus control device having an interface for said crossover bus, said bus control device having an operating mode sharing microsynchronism with the at least one further processor device connected through said crossover bus during operation of the processor device, said bus control device configured, when data is interchanged through said processor bus: to process a personal signature for interchanged data; to interchange said personal signature with the at least one further bus control device of at least one further processor device through said crossover bus; to compare a received signature with said personal signature; and to output an error signal triggering error handling in the processor device when said personal signature and said received signature do not correspond.