Patent ID: 8361863
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. A method of forming a DRAM cell having an access transistor and a capacitor structure, the method comprising: forming a field dielectric in a semiconductor substrate having a first conductivity type, wherein the field dielectric extends below an upper surface of the semiconductor substrate; providing a first mask on an upper surface of the semiconductor substrate thereby exposing a capacitor region; ion implanting an impurity into a first portion of the semiconductor substrate; removing the first mask; providing a second mask on the upper surface of the semiconductor substrate to expose the capacitor region and a logic transistor; removing oxide portions of the capacitor region and logic transistor; removing the second mask; and forming an oxide layer on the upper surface of the semiconductor substrate to produce an oxide layer in the capacitor region that is greater in thickness than an oxide of the logic transistor, and less than the thickness of an oxide of the access transistor.