Patent ID: 7027348
Filing Date: 2006-04-11
Classification: G11C

Abstract:
1. A memory device comprising: a plurality of memory cells arranged in a plurality of arrays, each array having a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array, wherein each memory cell in an array is addressable by a column line and a row line; a column address decoder for receiving a column address signal and for selecting one or more column lines of each array; a row address decoder for receiving a row address signal and for selecting a row line of each array; a plurality (k) of sense amplifiers, one sense amplifier associated with each array, connectable to one or more column lines of said array and for receiving a signal therefrom supplied from an addressed memory cell; a register; and a control circuit for receiving a read command, and a clock signal, and in response to the read command for determining a time period sufficient to sense the signal on a connected column line associated with each of a first plurality (j) of said plurality (k) of sense amplifiers (j<k); and for activating said first plurality (j) of sense amplifiers for said time period; and for latching the signal into said register; and for deactivating said first plurality (j) of sense amplifiers; and for serially outputting the signal from said register in response to said clock signal.