Patent ID: 6239020
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell region and a periphery circuit region, wherein semiconductor devices are formed on the memory cell region and the periphery circuit region having a height variation therebetween, comprising the steps of:a) forming a first dielectric layer blanket-covering the semiconductor substrate, wherein a first height variation exists between the memory cell region and the periphery circuit region;b) conformally forming a first stop layer that blanket-covers the first dielectric layer;c) forming a second dielectric layer on the first stop layer;d) executing a chemical mechanical polishing process on the second dielectric layer until the first stop layer on the memory cell region is exposed and a part of the second dielectric layer remains on the periphery circuit region;e) forming a third dielectric layer blanket-covering the exposed first stop layer and the remainder of the second dielectric layer, wherein a second height variation exists between the memory cell region and the periphery circuit region;f) conformally forming a second stop layer that blanket-covers the third dielectric layer;g) forming a fourth dielectric layer on the second stop layer;h) executing a chemical mechanical polishing process on the fourth dielectric layer until the second stop layer on the memory cell region is exposed and a part of the fourth dielectric layer remains on the periphery circuit region; andi) forming a cap layer on the top surface of the exposed second stop layer and the fourth dielectric layer.