Patent ID: 6720199
Filing Date: 2004-04-13
Classification: G02F

Abstract:
A method for manufacturing a TFT array substrate in which at least (a) a gate insulating film, (b) a semiconductor layer and (c) a metal layer are sequentially formed in this order of (a), (b) and (c), and using one resist pattern formed by a photolithography, a part of the metal layer is selectively removed, to form a source line, together with the semiconductor layer beside the source line,wherein a passivation film is formed after the formation of the source line and the removal of the semiconductor layer beside the source line, a resist pattern to selectively remove the passivation film is formed on the passivation film, and using the resist pattern, the passivation film above the source line, the passivation film beside the source line and the gate insulating film beside the source line are removed to, thereby, expose the semiconductor layer under the source line.