Patent ID: 7843050
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A stacked system of microelectronic die packages, comprising: a first die package having a bottom side and including a first microelectronic die, a first dielectric casing at least partially covering the first die and defining at least a portion of the bottom side, and individual first metal leads coupled to the first die and having a first exterior surface; a second die package having a top side attached directly to the bottom side of the first package with an adhesive layer, the second die package including a second microelectronic die, a second dielectric casing at least partially covering the second die and defining at least a portion of the top side and a lateral side, and individual second metal leads coupled to the second die and having a second exterior surface and an interior surface region that generally faces the lateral side, wherein the individual second leads are at least generally aligned with the individual first leads and project, at least in part, towards the first package; and external inter-package connectors coupling a first portion of individual first exterior surfaces with a second portion of individual second exterior surfaces.