Patent ID: 9071252
Filing Date: 2015-06-30
Classification: H03L,H04L

Abstract:
1. A radio communication apparatus comprising: an analog unit configured to perform frequency conversion of a reception signal; a digital unit configured to perform demodulation processing of the reception signal subjected to the frequency conversion by the analog unit; a PLL circuit configured to generate a clock to the digital unit; and a PLL-setting changing unit configured to perform, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control a jitter of the clock, wherein the analog unit includes: an RF reception unit configured to receive the reception signal in a radio frequency band; a demodulation unit configured to down-convert the received reception signal in the radio frequency band to a baseband; an analog baseband (BB) unit configured to subject the down-converted reception signal or a transmission signal to analog processing in the baseband; a modulation unit configured to up-convert the transmission signal in the baseband to the radio frequency band; and an RF transmission unit configured to transmit the transmission signal in the radio frequency band, wherein the digital unit includes an automatic gain control (AGC) unit configured to control a gain of the analog unit based on a signal level of the reception signal, and wherein the AGC unit includes: a signal-level measuring unit configured to measure the signal level of the reception signal; and a reception-power measuring unit configured to measure reception power based on the signal level of the reception signal, and the PLL-setting changing unit performs the setting change of the parameters of the PLL circuit based on the reception power, wherein the PLL circuit includes: a voltage control oscillator configured to control an oscillation frequency of the clock based on voltage control; a frequency divider configured to subject the clock generated by the voltage control oscillator to frequency division; a phase comparator configured to compare a phase of the clock subjected to the frequency division by the frequency divider and a phase of a reference signal; a charge pump circuit configured to generate a voltage corresponding to a phase error between the clock and the reference signal; a loop filter configured to reduce a high-frequency component included in the voltage generated by the charge pump circuit to generate the voltage control; a first selector configured to switch a current setting value of the charge pump circuit based on a setting control signal from the PLL-setting changing unit; and a second selector configured to switch a bandwidth setting value of the loop filter based on the setting control signal from the PLL-setting changing unit.