Patent ID: 6810094
Filing Date: 2004-10-26
Classification: H03M

Abstract:
A Viterbi decoder including:memory means comprising two-port RAM means for storing Viterbi decoder data, said data comprising path metrics and/or path history data; clocked processing means for producing new Viterbi decoder data from Viterbi decoder data, read from the memory means, and a signal being decoded; and addressing means for generating a first address signal for addressing locations in said two-port RAM means in a predetermined sequence so that Viterbi decoder data is read from the two-port RAM means in the same state order during decoding of a signal, and for generating a second address signal for addressing locations in said two-port RAM means in the same sequence as the first address signal, wherein: both the first and second address signals are generated in one clock cycle, new Viterbi data is written to the locations addressed by the second address signal concurrently with Viterbi data being read from the locations addressed by the second address signal, and the second address signal lags the first address signal by the maximum number of control clock cycles required between reading Viterbi data and the resultant new Viterbi data.