Patent ID: 6028446
Filing Date: 2000-02-22
Classification: H03K

Abstract:
A programmable logic device, comprising:a configuration memory having programmable storage locations, the storage locations storing configuration data to configure the programmable logic device;a first package terminal;a second package terminal;a first clock line;a second clock line;a plurality of programmable block clock selectors wherein each programmable block clock selector has a first input terminal coupled to the first package terminal, a second input terminal coupled to the second package terminal, and an output terminal, wherein the output terminal is coupled to at least one of the first input terminal or the second input terminal in response to the configuration data, wherein the output terminal is coupled the first clock line or the second clock line; anda plurality of programmable logic blocks, wherein each programmable logic block includes:programmable logic array; andprogrammable logic macrocell programmably connectable to theprogrammable logic array, wherein the programmable logic macrocell includes:a programmable logic element having a clock input; and a programmable macrocell clock selector having a first macrocell selector input terminal coupled to the first clock line, a second macrocell selector input terminal coupled to the second clock line and a macrocell selector output terminal coupled to the clock input, the programmable clock selector coupling the first macrocell selector clock input or the second macrocell selector clock input to the macrocell selector output terminal in response to the configuration data.