Patent ID: 6401231
Filing Date: 2002-06-04
Classification: G06F

Abstract:
A storage medium containing a computer program for operating a computer to implement a synthesis system that determines time budgeting during integrated circuit design, said computer program comprising a method comprising the steps of:using positive and negative slack budgeting to determine a budgeted arrival time for all sub-modules of a complete netlist during an initial design phase of said integrated circuit, wherein said budgeted arrival time is based upon a changeable delay of a path, which changeable delay comprises a sum of delays of edges of paths within said integrated circuit whose delays are not fixed, determination of said budgeted arrival time comprising the steps of: determining a budget arrival time constraint for each input port of each sub-module of said integrated circuit; and determining a budget required time constraint for each output port of each sub-module of said integrated circuit; wherein a positive slack path never turns into a negative slack path after budget generation; determining a definite required time constraint during a final design phase of said integrated circuit, wherein said definite required time constraint sets an upper bound for an arrival time at each output port of each sub-module within said integrated circuit which requires that arrival at said output port be equal to or greater than than a value produced during a global timing analysis run, said definite required time constraint step further comprising the step of: determining a relaxed arrival time during said final design phase of said integrated circuit, wherein said relaxed arrival time shifts arrival constraints at each input port of each sub-module forward, where the amount of such shift forward depends upon slack of said input port; and wherein said shifted arrival time plus a net delay comprises said definite required time constraint for said output port; and using said budgeted arrival time and said definite required time constraint during a synthesis step in the design of said integrated circuit.