Patent ID: 8817520
Filing Date: 2014-08-26
Classification: G11C

Abstract:
1. A system on chip (SoC) comprising: a memory array of self referencing non-volatile bit cells, wherein each bit cell comprises: wherein the memory array further comprises: a first read capacitor coupled to the bit line via a transfer device controlled by a first control signal; a second read capacitor coupled to the bit line via another transfer device controlled by a second control signal; and a sense amp coupled between the first read capacitor and the second read capacitor, the sense amp being operable to determine a value stored in a selected bit cell by comparing a first sense voltage transferred from the node Q to the first read capacitor by the first transfer device and a second sense voltage transferred from the node Q to the second read capacitor by the second transfer device; wherein each bit cell further comprises a clamping circuit coupled to the node Q, wherein the clamping circuit is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed; wherein the memory array further comprises a pre-charge circuit coupled to the first read capacitor and to the second read capacitor; wherein the memory array further comprises a controller, wherein the controller is configured to read a selected bit cell by releasing the clamp device, pre-charging the first and second read capacitors, placing a second voltage on the first plate line while maintaining the first voltage on the second plate line, enabling the transfer gate, and asserting the first control signal to transfer the first sense voltage from the node Q to the first read capacitor, placing a second voltage on the second plate line while maintaining the first voltage on the first plate line, enabling the transfer gate, and asserting the second control signal to transfer the second sense voltage from the node Q to the second read capacitor; wherein the precharge circuit is operable to precharge the first read capacitor and the second read capacitor to a voltage value approximately midway between the first voltage and the second voltage.