Patent ID: 8443161
Filing Date: 2013-05-14
Classification: G06F

Abstract:
1. A cache memory system, comprising: a processor; a cache memory that comprises a first memory portion and a flexible buffer memory portion, the cache memory being configured to store data therein independent of a data type; and a cache controller that is coupled to the cache memory and is configured to control allocation and/or deallocation of blocks from the first memory portion to and/or from the flexible buffer memory portion based on a mode and/or an index address; wherein a location of a part of the first memory portion corresponds to an index or offset address of the processor stored in a part of the processor; wherein the cache controller is further configured to generate a buffer block allocation control signal and/or a buffer block deallocation control signal responsive to access of the cache memory by the processor; and wherein the cache memory is configured to allocate blocks from the first memory portion to the flexible buffer memory portion responsive to the buffer block allocation control signal and to deallocate blocks from the flexible buffer memory portion to the first memory portion responsive to the buffer block deallocation control signal; wherein the cache controller comprises: a logic circuit that comprises a mode register and an index address register and is configured to generate a buffer block allocation request signal and/or a buffer block deallocation request signal responsive to the mode register being set by the processor and/or the index address being stored in the index address register by the processor; and a control portion that is coupled to the logic circuit that is configured to generate the buffer block allocation control signal responsive to the buffer block allocation request signal and to generate the buffer block deallocation control signal responsive to the buffer block deallocation request signal.