Patent ID: 7522464
Filing Date: 2009-04-21
Classification: G11C

Abstract:
1. A dynamic random access memory circuit (DRAM), comprising: a plurality of memory cells configured for retaining digital cell data in response to the level of stored charge; a plurality of bit-lines and word-lines coupled to said plurality of memory cells for accessing cell data; a refresh circuit configured for grouping refresh cycles into a portion of the data retention period; a power control circuit configured for generating a power control signal for deactivating power when the memory circuit is not being accessed; and said power control circuit is configured for generating an active power level while the grouping of refresh cycles is being performed; wherein each said refresh cycle comprises reading data from a memory cell followed by writing the same data back into the memory cell; wherein said reading and writing is performed in response to modulation of bit-lines and word-lines of said memory circuit; wherein said power control signal is not switched on and off for each refresh cycle within the data retention period; wherein said grouping of refresh cycles are within a portion of the retention period that is less than half of the retention period; and wherein the refresh cycles are not evenly distributed over the data retention period.