Patent ID: 7795105
Filing Date: 2010-09-14
Classification: G03F,H01L

Abstract:
1. A method for producing an integrated circuit arrangement with an auxiliary indentation, the method comprising: producing at least one useful indentation and at least one auxiliary indentation in a substrate; applying a filling layer to the substrate provided with the at least one useful indentation and with the at least one auxiliary indentations; depositing filling material into the at least one useful indentation and into the at least one auxiliary indentation; planarizing the filling layer, with filling material remaining in the at least one useful indentation and filling material remaining in the at least one auxiliary indentation; and selectively removing at least a portion of the filling material in the at least one auxiliary indentation after planarization, with no filling material removed from the at least one useful indentation; applying a covering layer after the selective removal such that at least one secondary auxiliary indentation is produced in the covering layer above the at least one auxiliary indentation.