Patent ID: 8062971
Filing Date: 2011-11-22
Classification: H01L

Abstract:
1. A method of making a semiconductor component, the method comprising: depositing an insulating layer over a metal level; depositing an etch stop layer over the insulating layer; depositing a sacrificial material layer over the etch stop layer; forming trenches for metal lines in the insulating layer by patterning the sacrificial material layer and the insulating layer; depositing a dummy fill material into the metal line trenches, wherein the dummy fill material forms an overfill layer above a surface of the sacrificial material layer; forming dummy fill-plugs by removing the overfill layer; using a via mask to expose a portion of a top surface of the dummy fill material and a portion of the sacrificial material layer; forming via openings by removing the exposed portion of the dummy fill material and the underlying insulating layer, wherein the portion of the sacrificial material layer protects underlying portions of the etch stop layer from being removed when forming the via openings; removing the dummy fill material from the metal line trenches; filling the via openings and the metal line trenches with a conductive material to form vias and metal lines, wherein a bottommost critical dimension (CD) of the metal lines overlying the vias is the same as a topmost CD of the vias; and removing the sacrificial material layer after filling the via openings and the metal line trenches.