Patent ID: 6100750
Filing Date: 2000-08-08
Classification: H03H

Abstract:
A frequency-independent voltage divider comprising a reference terminal (1); an input terminal (2) for receiving an input signal (V.sub.i) with respect to the reference terminal (1); an output terminal (3) for supplying an output signal with respect to the reference terminal (1); and a series arrangement of resistors (R.sub.1, R.sub.2, R.sub.k+) coupled between the input terminal (2) and the reference terminal (1), which resistors are connected to one another in nodes, of which nodes at least two nodes are loaded by at least two respective parasitic capacitors each (CP.sub.1, CP.sub.k) coupled between the reference terminal (1) and a respective one of the at least two nodes, and of which nodes the at least two nodes are coupled directly to the input terminal (2) via respective compensation capacitors (CCMP.sub.1, CCMP.sub.M), wherein the series arrangement of resistors comprises at least three resistors (R.sub.1 -R.sub.M+1), and the number of compensation capacitors (CCMP.sub.1 -CCMP.sub.M) is at least two.