Patent ID: 6079027
Filing Date: 2000-06-20
Classification: G06F

Abstract:
A computer chip set for a computer mother board that has at least a first clock rate and a second clock rate, the chip set comprising:a first interface which is operated at the first clock rate;a second interface which is operated at the second clock rate, wherein the ratio of the first clock rate to the second clock rate is m:n where m and n are minimum positive integers and m>n, the first and second clock rates are in virtual synchronism with each other, the time lag between the start time of the (i)th period of the first clock rate and the start time of the (j)th period of the second clock rate is less than a preset duration, and i, j are positive integer numbers; anda signal conversion circuit, coupled to both the first and the second interfaces, receiving an input signal, and exporting an output signal, so as to perform one function selected from a group consisting of converting the input signal with the first clock rate to the output signal with the second clock rate and converting the input signal with the second clock rate to the output signal with the first clock rate, based on the clock ratio and virtual synchronism between the first clock rate and the second clock rate.