Patent ID: 8325527
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A NAND based non-volatile memory device comprising: a plurality of memory cells vertically arranged as a NAND string; a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string; a plurality of word line contacts each electrically connected to a respective word line plate, the plurality of word line contacts being aligned to a bit line direction in the device; a plurality of contact portions of the plurality of word line plates wherein each one of the plurality of word line contacts is electrically coupled to a respective one of the plurality of word line plates, wherein the plurality of contact portions define a stair-step pattern extending downward in the bit line direction; and wherein the plurality of word line plates define a word line plate side wall thereof that faces in a global word line direction.