Patent ID: 6255178
Filing Date: 2001-07-03
Classification: G03F,H01L

Abstract:
A method for forming a transistor on a substrate, the method comprising the steps of:a) forming an insulating layer on said substrate;b) forming a layer of conductive material on said insulating layer;c) forming at least one pair of proximately located openings through said conductive layer and said insulating layer, said pair of proximately located openings defining said layer of conductive material into a first region between said pair of proximately located openings and a second region adjacent each of said pair of proximately located openings, wherein the first region of said conductive material comprises a gate region of said transistor;d) implanting source and drain implants into said second region of said conductive material; ande) forming associated device contacts to said first region and second regions of said conductive material.