Patent ID: 6420789
Filing Date: 2002-07-16
Classification: G01R,H01L,H05K,Y02P

Abstract:
A computer system comprising:an input device; an output device; a processor, coupled to the input and output devices; a memory module assembly, coupled to the processor comprising: a module board having a first surface, a second surface, and at least one electrical circuit to be placed in electrical contact with at least one ball grid array semiconductor package; and at least one of the first and second surfaces of the module board comprising: at least one first ball grid array semiconductor package attached to the at least one of the first and second surfaces of the module board by a plurality of mutually complementary connective elements in electrical communication with the at least one electrical circuit of the module board, the at least one first ball grid array semiconductor package comprising: a substrate having a first surface, a second surface, and an aperture extending from the first surface through the substrate to the second surface, a plurality of substrate bond pads located on the first surface of the substrate proximate to the aperture; the plurality of connective elements in electrical communication with the module board being attached to and extending from the second surface of the substrate and arranged in a preselected grid array pattern having at least one preselected pitch dimension between adjacent connective elements; a semiconductor device having an active surface and a plurality of bond pads thereon, the semiconductor device attached to the second surface of the substrate and positioned adjacent the module board; a plurality of bond wires extending through the aperture of the substrate, each of the plurality of bond wires connecting one of the plurality of bond pads on the active surface of the semiconductor device with one of the plurality of substrate bond pads on the first surface of the substrate; and the substrate including a plurality of mutually discrete electrically conductive circuit traces, each circuit trace of the plurality of circuit traces selectively extending from one of the plurality of substrate bond pads to one of the plurality of connective elements.