Patent ID: 6492690
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A semiconductor device including first to third types of transistors on a semiconductor substrate, whereina transistor of said first type comprises: a first semiconductor layer of a first conductivity type which is formed in a surface of said semiconductor substrate; a first channel dope layer of the first conductivity type which is formed selectively in said first semiconductor layer; and a first control electrode which is formed at a position which faces said first channel dope layer, on said first semiconductor layer, a transistor of said second type comprises: a second semiconductor layer of the first conductivity type which is formed in the surface of said semiconductor substrate; a second channel dope layer of the first conductivity type which is formed selectively in said second semiconductor layer; and a second control electrode which is formed at a position which faces said second channel dope layer, on said second semiconductor layer, a transistor of said third type comprises: a third semiconductor layer of the first conductivity type which is formed in the surface of said semiconductor substrate; a third channel dope layer of the first conductivity type which is formed selectively in said third semiconductor layer; and a third control electrode which is formed at a position which faces said third channel dope layer, on said third semiconductor layer, said first control electrode internally comprises an impurity layer of a second conductivity type having a concentration distribution in a direction of depth vertical to said semiconductor substrate which is different from an impurity concentration distribution in said second and third control electrodes and said first to said third channel dope layers have a same impurity concentration distribution; and wherein said transistor of said first type comprises: a pair of first semiconductor regions of the second conductivity type formed selectively and independently of each other within said first semiconductor layer; and a first gate oxide film which is formed on said first semiconductor layer between said pair of first semiconductor regions, said first control electrode is formed on said first gate oxide film, said first channel dope layer is formed between said pair of first semiconductor regions within said first semiconductor layer, said transistor of said second type comprises: a pair of second semiconductor regions of the second conductivity type formed selectively and independently of each other within said second semiconductor layer; and a second gate oxide film which is formed on said second semiconductor layer between said pair of second semiconductor regions, said second control electrode is formed on said second gate oxide film, said second channel dope layer is formed between said pair of second semiconductor regions within said second semiconductor layer, said transistor of said third type comprises: a pair of third semiconductor regions of the second conductivity type formed selectively and independently of each other within said third semiconductor layer; and a third gate oxide film which is formed on said third semiconductor layer between said pair of third semiconductor regions, said third control electrode is formed on said third gate oxide film, said third channel dope layer is formed between said pair of third semiconductor regions within said third semiconductor layer, said first, said second and said third control electrodes include a first, a second and a third impurity layer, respectively, which have different impurity concentrations from each other, said first to said third gate oxide films have the same thickness, and said first to said third channel dope layers have the same impurity concentration.