Patent ID: 6071814
Filing Date: 2000-06-06
Classification: C25D,H01L

Abstract:
A method of fabrication of a metal line using a selective deposition process; comprising the steps of:a) providing an insulating layer over a semiconductor structure, said insulating layer having a plurality of trenches arranged in a predetermined pattern therein; each of said plurality of trenches being defined by sidewalls and a bottom; said insulating layer having a top surface;b) forming a seed layer over said insulating layer, said sidewalls, and said bottom of each of said plurality of trenches; said seed layer comprising a trench seed layer portion covering said sidewalls and bottoms of said plurality of trenches, and a top seed layer portion covering said insulating layer top surface;c) patterning said top seed layer portion of said seed layer by removing selected portions of said top seed layer portion forming seed layer lips adjacent said trench seed layer portion for each of said plurality of trenches; said seed layer lips and said trench seed layer portion electrically connecting said trench seed layer portion between said plurality of trenches;d) selectively depositing a metal on said patterned top seed layer, said seed layer lips, and said trench seed layer portion filling said plurality of trenches; ande) chemical-mechanically polishing said metal and said seed layer lips to remove the excess of said metal overlying said seed layer lips and said seed layer lips, forming a metal line pattern filling said plurality of trenches.