Patent ID: 6832038
Filing Date: 2004-12-14
Classification: G11B

Abstract:
A time code arithmetic apparatus comprising:a first selector circuit having first and second input terminals, and supplied with a first time code providing a reference for arithmetic operation at the first input terminal and an arithmetic operation result at the second input terminal, the first selector circuit selecting one of the first and second inputs and outputting the selected input as a second time code; a second selector circuit having first and second input terminals, and supplied with a third time code providing an object of an arithmetic operation at the first input terminal and a second selector input time code o'clock at the second input terminal, the second selector circuit selecting one of the first and second inputs and outputting the selected input as a fourth time code; an arithmetic circuit for adding or subtracting the second and fourth time codes selected in the first and second selector circuits simply as a time code in non-drop mode based on the add/subtract information, and outputting the arithmetic operation result to the first input terminal of the first selector circuit and before/after information indicating which is larger of the absolute value of the time code before and after the arithmetic operation; a first drop frame amount calculation circuit for calculating a first total number of frames in the arithmetic operation result dropped in the process of time lapse one frame each from 00:00:00.00 o'clock and outputting the first total number of frames as a first drop frame amount; a second drop frame amount calculation circuit for calculating a second total number of frames in the second time code dropped one frame each in the process of time lapse from 00:00:00.00 o'clock and outputting the second total number of frames as a second drop frame amount; a difference frame number calculation circuit for determining a difference between the total number of frames dropped based on the first and second drop frame amounts and the before/after information, and in the case where the difference is 0, outputting the second selector input time code o'clock of the non-drop mode corresponding to the difference to the second input terminal of the second selector circuit while at the same time outputting two recalculation arithmetic signals; and a drop frame correction circuit for outputting the arithmetic operation result as a final time code finally in the case where the arithmetic operation is one of an add operation or a subtract operation with the arithmetic operation result failing to correspond to a drop frame, and for correcting the arithmetic result by âˆ’2 frames and outputting the corrected result as a corrected final time code in the case where the arithmetic operation is a subtract operation with the arithmetic operation result corresponding to a drop frame; wherein in the case where the difference is not 0, the first selector circuit and the second selector circuit select the arithmetic operation result input to the first input terminal of the first selector circuit and the second selector input time code o'clock to the second input terminal of the second selector circuit, respectively, based on the two recalculation signals and carrying out a recalculation in the arithmetic circuit.