Patent ID: 6225165
Filing Date: 2001-05-01
Classification: G11C,H01L

Abstract:
A method of forming a memory cell for storing information as one of at least two possible bistable states, the method comprising the following steps:providing a semiconductor substrate;providing doped silicon regions over said substrate in the following doping profile: p, n, p and n, to form a vertical p-n-p-n transistor;forming an oxide layer adjacent to at least two sidewall portions of said doped silicon regions;forming a p-type polysilicon gate adjacent to said oxide layer where said oxide layer is adjacent to the central n-region of said transistor to form a channel region between said p-regions; andforming an n-type polysilicon gate orthogonal to said p-type gate and adjacent to said oxide layer where said oxide layer is adjacent to the central p-region of said transistor to form a channel region between said n-regions.