Patent ID: 6052705
Filing Date: 2000-04-18
Classification: G06F

Abstract:
A multi-parallel digital video signal processor wherein a plurality of bit-wise processor elements are linearly arrayed, comprising:an input serial-access memory unit formed by plural serially accessed memory cells in which data bits are inputted into successive ones of said memory cells by a programmed-controlled pointer;a data memory unit comprising memory cells of three ports or more, for writing-in said data read out from said memory cells of said serial-access memory unit on a bit-wise basis;an arithmetic logic unit array responsive to stored-program control so as to read out said data stored in said data memory unit on a bit-wise basis, perform a program-prescribed arithmetic operation in the arithmetic logic unit, and write-in the arithmetic result of said arithmetic operation to said data memory again;an output serial-access memory unit, formed by plural serial access memory cells and controlled so that said arithmetic result will be outputted from successive ones of said memory cells by a programmed-controlled pointer; anda programmed control unit connected to said input serial-access memory, said data memory unit, said arithmetic logic unit, and said output serial-access memory for effecting control of at least said program-controlled pointer.