Patent ID: 6195757
Filing Date: 2001-02-27
Classification: H03L

Abstract:
A system for improving data paths between a first chip and a second chip with a phased lock look based clock system, wherein said system comprises,a communication circuit for exchanging data between a first chip and a second chip which supports two modes of operation for data transfer therebetween over a range of cycle times which range faster than any delay of a communication network and interface between sending and receiving latches on said first chip and second chip,including a first mode circuit responsive to a first mode select signal for preparing data in said first chip to be sent over said communication network to said second chip enabling the use of late and early clocks to steal time from on-chip paths of said first chip and to give that time to the off first chip path of said exchanging data by a cycle stealing mode occurring when said first mode select signal controls circuit cycle time such that said first chip drives data to said second chip at a first frequency in which mode cycle stealing derives cycles from said first chip and provides them to said second chip, andwherein is provided, a second mode circuit responsive to a second mode select signal for preparing data in said first chip to be sent over said communication network to said second chip enabling a switch from a cycle stealing mode to multi-cycle mode which provides a more than a full cycle time for evaluation of data being exchanged.