Patent ID: 6219720
Filing Date: 2001-04-17
Classification: G06F

Abstract:
An apparatus within a core logic unit of a computer system for updating a status register to indicate changes in a status of peripheral devices in the computer system, comprising:a plurality of address inputs coupled to address lines of a bus;an address detecting circuit coupled to a set of higher order bits in the plurality of address inputs, for detecting an address in a reserved range of addresses specified by the set of higher order bits; anda decoder circuit coupled to a set of lower order bits in the plurality of address inputs, for detecting references to particular addresses in the reserved range of addresses; andthe status register coupled to a set of outputs from the decoder circuit, so that a reference to a particular address in the reserved range of addresses by a peripheral device feeds through the decoder circuit and updates status information for the peripheral device in the status register, the status register including outputs coupled to a central processing unit so that the status register can be read by the central processing unit,wherein the bus includes a processor to memory bus.