Patent ID: 9003341
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. A method for determining an interface timing of an integrated circuit, comprising: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; searching from the first interface port toward inside of the netlist file for the first flip-flop as a specific circuit element, and designating a path coupled between the first interface port and the first flip-flop as a first candidate path; backtracking from the first flip-flop toward the first interface port for finding out a path coupled between the first interface port and the first flip-flop, and designating the path as a second candidate path; cross-comparing the first candidate path with the second candidate path to obtain a common path; designating the common path as a first transmission path, and designating load on the common path as a load on the first transmission path; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and using a computer to calculate a first signal transmission time of the first transmission path according to the interface circuit file.