Patent ID: 6151076
Filing Date: 2000-11-21
Classification: H03L,H04N

Abstract:
A method for phase-locking a clock to a digital audio signal embedded within a digital video signal comprising the steps of:generating a first reference frequency signal from digital audio signal samples embedded within the digital video signal by dividing the frequency of the digital audio signal samples by a divisor such that the period of the first reference frequency is greater or equal to that of phase jitter present in the digital audio signal samples;generating a second reference frequency signal from an output audio sample frequency signal, the frequency of the output audio sample frequency signal being equal to the frequency of the digital audio signal samples so that, when divided by the divisor, the frequency of the second reference frequency signal equals that of the first reference frequency signal;generating from the first and second reference frequency signals a low jitter clock control signal, the low jitter clock control signal been result of rejecting the phase jitter present in the digital audio signal samples; andgenerating the output audio sample frequency signal from the low jitter clock control signal.