Patent ID: 7285817
Filing Date: 2007-10-23
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region, the semiconductor element being a single-layer gate type nonvolatile memory and having a floating electrode constituting a single conductive layer; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric, wherein the first shading layer and the second shading layer are orthogonal when seen from top; wherein the semiconductor layer is divided into a control gate section, a write section and an erase section by an element isolation insulating layer; wherein the floating gate electrode is provided across the control gate section, the write section and the erase section; wherein an insulating layer is provided between the floating gate electrode and the semiconductor layer; wherein the control gate section comprises: wherein the write section comprises: wherein the erase section comprises: wherein the floating gate electrode in the control gate section is at least covered by the first shading layer; and wherein the floating gate electrode in the write section and in the erase section are at least covered by the second shading layer.