Patent ID: 7403747
Filing Date: 2008-07-22
Classification: H03C,H04B,H04L

Abstract:
1. A DC offset compensation circuit configured to output a first test signal to one of an in-phase (I) branch or a quadrature phase (Q) branch of a modulator circuit and to output a second test signal to the same one of the in-phase (I) branch or the quadrature phase (Q) branch of the modulator circuit, the second test signal being of opposite polarity to the first test signal, said DC offset compensation circuit further configured to respond to values of first and second power measurements made at an output of the modulator circuit, said first and second power measurements corresponding to said first and second test signals, respectively, and to modify a DC offset signal of the same one of the in-phase (I) branch or the quadrature phase (Q) branch of the modulator circuit, where the DC offset signal is modified to have a value determined to minimize a difference between said values of said first and second power measurements.