Patent ID: 6801095
Filing Date: 2004-10-05
Classification: H03B

Abstract:
A method for designing an interconnected multi-stage oscillator, the method comprising:(a) specifying a total number â€œNâ€  of a plurality of stages, a minimum relative attenuation â€œ&agr;â€  of undesired modes, and a total transconductance â€œgTâ€  of a plurality of input transistors per stage of the plurality of stages, for the interconnected multi-stage oscillator; (b) determining a normalized transconductance â€œGnâ€  for each nth input transistor of the plurality of input transistors per stage to form a plurality of normalized transconductances (Gn+s); (c) using the plurality of normalized transconductances, determining a relative size â€œgnâ€  for each input transistor of the plurality of input transistors per stage to form a plurality of precise gn values; (d) using the plurality of precise gn values, determining a first frequency, a first relative attenuation, and a first load transconductance, for each oscillation mode of the plurality of oscillation modes, to form a plurality of precise oscillation parameters; (e) using the plurality of precise gn values, determining a plurality of fabrication gn values, and using the plurality of fabrication gn values, determining a second frequency, a second relative attenuation, and a second load transconductance, for each oscillation mode of the plurality of oscillation modes, to form a plurality of fabrication oscillation parameters; and (f) when the plurality of fabrication oscillation parameters are within a predetermined threshold of the plurality of precise oscillation parameters, selecting an oscillator configuration having the plurality of fabrication gn values for the plurality of input transistors per stage.