Patent ID: 6529229
Filing Date: 2003-03-04
Classification: B41J

Abstract:
A driving circuit receiving print data and a pair of differential clock signals, and supplying driving current to an array of recording elements according to the print data, having a cascaded series of driver integrated circuits, and transferring the print data through the cascaded series of driver integrated circuits in synchronization with the differential clock signals, wherein:each driver integrated circuit in the cascaded series has a first clock input terminal and a second clock input terminal; a first driver integrated circuit in the cascaded series receives one of the differential clock signals at its first clock input terminal and receives another one of the differential clock signals at its second clock input terminal; a second driver integrated circuit, following the first driver integrated circuit in the cascaded series, receives said one of the differential clock signals at its second clock input terminal and receives said another one of the differential clock signals at its first clock input terminal; the first clock input terminal of the first driver integrated circuit is connected to the second clock input terminal of the second driver integrated circuit; and the second clock input terminal of the first driver integrated circuit is connected to the first clock input terminal of the second driver integrated circuit.