Patent ID: 7928470
Filing Date: 2011-04-19
Classification: H01L

Abstract:
1. A semiconductor device having a super junction MOS transistor, comprising: a semiconductor substrate having a first conductive type and a high impurity concentration; a first semiconductor layer disposed on the substrate, wherein the first semiconductor layer includes a plurality of first impurity diffusion regions having the first conductive type and a plurality of second impurity diffusion regions having a second conductive type, which are alternately arranged so that the first semiconductor layer provides a drift region; a second semiconductor layer having the first conductive type disposed on the first semiconductor layer, wherein the second semiconductor layer has a low impurity concentration, which is lower than that of the first semiconductor layer; a channel forming region having the second conductive type disposed in a first portion of the second semiconductor layer; a source region having the first conductive type disposed in a first portion of the channel forming region; a source contact region having the second conductive type disposed in a second portion of the channel forming region; a gate electrode disposed on a third portion of the channel forming region through a gate insulation film, the third portion being exposed from the source region and the source contact region; a source electrode disposed on the source region and the source contact region; a drain electrode disposed on a backside of the substrate, which is opposite to the first semiconductor layer; and an anode electrode disposed on a second portion of the second semiconductor layer, the second portion of the second semiconductor layer having a surface exposed from the channel forming region, wherein the anode electrode and a two-layered structure of the first semiconductor layer and the second semiconductor layer provide a Schottky barrier diode so that the super junction MOS transistor and the Schottky barrier diode are integrated in the semiconductor device, the second semiconductor layer is thinner than the first semiconductor layer, each of the plurality of second impurity diffusion regions directly contacts the channel forming region of the second conductivity type without directly contacting the second semiconductor layer of the first conductivity type, each of the plurality of first impurity diffusion regions directly contacts the second semiconductor layer of the first conductivity type without directly contacting the channel forming region of the second conductivity type, none of the plurality of second impurity diffusion regions directly contacts the second semiconductor layer of the first conductivity type, and a forward bias voltage of the Schottky barrier diode is lower than a forward bias voltage of a first built-in PN diode provided by the channel forming region and the second semiconductor layer, and the forward bias voltage of the Schottky barrier diode is lower than a forward bias voltage of a second built-in PN diode provided by one of the plurality of first impurity diffusion regions and an adjacent one of the plurality of second impurity diffusion regions.