Patent ID: 6141744
Filing Date: 2000-10-31
Classification: G06F

Abstract:
An interface device having a data input having a first data width, a data output having a second data width different from the first data width, an address input and an address output, the interface device such as for use as an interface between a first bus including first data connected to the data input and a first address connected to the address input and a first bus clock frequency and a second bus including second data connected to the data output and a second address connected to the address output, said interface device comprising:an integrated circuit includingtwo parallel plural-word FIFOs having a clock input for operation of said FIFOs synchronous to the first bus clock frequency, each parallel plural-word FIFO having an input connected to a corresponding subset of bits of the data input and an output;multiplexer circuitry having a first input connected to the output of a first of the two parallel plural-word FIFOs, a second input connected to the output of a second of the two parallel plural-word FIFOs, an output and a control input, said multiplexer circuitry selectively connecting either the first input or the second input to the output dependent upon the control input; andan address translation circuit connected to the address input and the address output for translating first addresses received at the address input into second addresses supplied to the address output, said address input having a less significant bit (LSB) coupled to said control input of said multiplexer circuitry so that data bytes are multiplexed differently depending on the address input LSB.