Patent ID: 6011735
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock to input and output storage data, said synchronous semiconductor memory device comprising:a plurality of memory cell blocks each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks includinga plurality of regular memory cells,a redundant memory cell row provided in a row direction, anda redundant memory cell column provided in a column direction;an address bus provided common to said plurality of memory cell blocks for transmitting a row address and a column address included in said address signal in a time-divisional manner;a plurality of selecting circuits provided corresponding to said memory cell blocks, each for selectively activating one of said redundant memory cell rows and said memory cell columns,a plurality of redundancy determination circuits provided corresponding to said memory cell blocks, each for controlling a selecting operation of said selecting circuit based on a detection of whether said address signal from said address bus indicates said row address or said column address according to said control signal and a comparison between said address signal and a preset defective address corresponding to a defective memory cell in said plurality of regular memory cells.