Patent ID: 9082965
Filing Date: 2015-07-14
Classification: G11C,H01L

Abstract:
1. A memory device comprising: an inert electrode including an electrically conductive material; a part of at least one electrically insulating material of resistivity higher than that of the material of the inert electrode, positioned around the inert electrode within a layer defined by a thickness of the inert electrode, the thickness of the inert electrode being substantially equal to a thickness of the electrically insulating material, and a coefficient of thermal conductivity of the electrically insulating material being equal to or higher than approximately 10 W·m a solid electrolyte positioned on at least one part of the inert electrode and of the part of electrically insulating material, and including metal ions originating from a separate ionisable metal layer positioned on top of a top surface of the solid electrolyte, wherein the solid electrolyte comprises chalcogenide and a concentration of the ionisable metal layer in the chalcogenide is between approximately 15% and 50%; and an upper electrode including an electrically conductive material positioned at least on top of a top surface of the ionisable metal layer; wherein a ratio between a coefficient of electrical resistivity of the electrically insulating material of resistivity higher than that of the electrically conductive material of the inert electrode and a coefficient of electrical resistivity of the electrically conductive material of the inert electrode is equal to or higher than approximately 100.