Patent ID: 6815278
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of fabricating an integrated semiconductor structure comprising:providing a structure comprising a carrier wafer and at least a film stack of a first semiconductor layer of a first crystallographic orientation and an overlying second semiconductor layer of a second crystallographic orientation, said first crystallographic orientation is different from said second crystallographic orientation; forming at least one opening in the structure that exposes a surface of the first semiconductor layer, forming a semiconductor material in the at least one opening on the exposed surface of the first semiconductor layer, said semiconductor material having the same crystallographic orientation as the first semiconductor layer; forming an insulator layer on the structure and bonding the insulator to a handling wafer; selectively removing the carrier wafer and the first semiconductor layer to expose a surface portion of the semiconductor material; and etching back the surface portion of the semiconductor material to provide a structure in which the etched back semiconductor material having the first crystallographic orientation is substantially coplanar and of substantially the same thickness as that of the second semiconductor layer.