Patent ID: 7105421
Filing Date: 2006-09-12
Classification: H01L

Abstract:
1. A method of controlling the flow of electricity between a source semiconductor region and a drain semiconductor region, both heavily doped with a first impurity element, the method comprising: a) positioning a central channel region consisting of a first semiconductor between the source region and the drain region, the channel region lightly doped with the first impurity element to increase free carriers of a first type; b) positioning a gate adjacent the channel region and extending along a side of the central channel region adjacent the source region and forming a junction with the channel region, the gate comprising the first semiconductor and a second semiconductor with an energy gap greater than the first semiconductor and being doped with a second impurity element to increase free carriers opposite of the first type; and c) varying the potential of the gate region relative to the source region to control depletion within the channel region; d) positioning a backdate adjacent the channel region, and on an opposing side of the channel region from the gate, and forming a junction with the channel region, the backgate comprising a first semiconductor and the second semiconductor and being doped with the second impurity element to increase free carriers opposite of the first type; and e) varying the potential of the backdate relative to the source region to control depletion within the channel region.