Patent ID: 6309961
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method of forming damascene wiring in a semiconductor device, said method comprising:providing a substrate on which an insulating film is formed;forming a large trench having a width equal to or larger than 1 micrometer in said insulating film;depositing a metal on said insulating film and in said trench;selectively removing said metal to expose a surface of said insulating film and form a first metal film having a lower portion which fills said trench and an upper portion projecting at least partially out of said trench, said upper portion having sidewalls which are substantially coplanar with sidewalls of said trench;forming a second metal film on said insulating film such that said first metal film is covered by said second metal film; andpolishing a surface of said semiconductor device using a chemical mechanical polishing (CMP) method.