Patent ID: 8349675
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. A method for forming a gate electrode, comprising: providing a substrate; forming a gate dielectric layer on a surface of the substrate and forming a sacrificial layer on a surface of the gate dielectric layer, the sacrificial layer including doping ions, a density of the doping ions in the sacrificial layer decreasing with increasing distance from the substrate; forming a hard mask layer on a surface of the sacrificial layer; patterning the sacrificial layer and the hard mask layer; removing part of the patterned sacrificial layer by wet etching with the patterned hard mask layer as a mask, to form a dummy gate electrode which has a top width bigger than a bottom width based on a difference between a first etching speed at the top and a second etching speed at the bottom using different densities in the single sacrificial layer at different distances from the substrate, and removing the patterned hard mask layer; forming a dielectric layer covering the gate dielectric layer, an upper surface of the dielectric layer and an upper surface of the dummy gate electrode being on a substantially same level; removing the dummy gate electrode to form a gate trench which has a top width bigger than a bottom width; and filling the gate trench with gate material to form a gate electrode.