Patent ID: 9087916
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method of fabricating a field effect transistor (FET) device, the method comprising the steps of: providing a wafer; forming at least one active area in the wafer; forming a plurality of dummy gates over the active area, wherein the dummy gates cover portions of the active area that serve as channel regions of the device and wherein portions of the active area that extend out from under the dummy gates serve as source and drain regions of the device; filling spaces between the dummy gates with a dielectric gap fill material such that one or more keyholes defined by a gap are formed in the dielectric gap fill material, and wherein the keyholes are present in between the dummy gates and extend parallel to the dummy gates through the dielectric gap fill material; removing the dummy gates to reveal a plurality of gate canyons in the dielectric gap fill material; forming a mask that i) is perpendicular to the gate canyons and divides at least one of the gate canyons, ii) blocks off one or more of the keyholes by filling at least a portion of one or more of the keyholes; and depositing at least one gate stack material onto the wafer filling the gate canyons and the un-blocked keyholes, wherein the gate stack material deposited into the gate canyons serves as replacement gates of the device and the gate stack material deposited into the un-blocked keyholes serves as interconnect structures of the device.