Patent ID: 7170162
Filing Date: 2007-01-30
Classification: H01L

Abstract:
1. A chip embedded package structure, comprising: a tape, having at least a first alignment mark disposed on a surface of the tape and at least a second alignment mark disposed on another surface of the tape, wherein the tape comprises a plurality of conductive vias passing through the tape; a stiffener, disposed on the tape, wherein the stiffener comprises at least a chip opening; at least a chip, disposed on the surface of the tape and inside the chip opening such that an active surface of the chip faces the tape, wherein the first alignment mark is disposed on the surface of the tape on the same side as the chip, the second alignment mark is disposed on the surface of the tape away from the chip, the chip also comprises a plurality of bonding pads disposed on the active surface, and the bonding pads are electrically connected to the conductive vias respectively; and a multi-layered interconnection structure, disposed on the surface of the tape away from the chip, wherein the multi-layered interconnection structure comprises an inner circuit connecting with the conductive vias and comprises a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.