Patent ID: 6713348
Filing Date: 2004-03-30
Classification: H01L,Y10S

Abstract:
A method used during the formation of a semiconductor device comprising:providing a semiconductor wafer substrate assembly comprising a semiconductor wafer; forming a blanket first conductive layer overlying said wafer substrate assembly; forming a blanket first mask layer overlying said blanket first conductive layer; forming a blanket second mask layer overlying said blanket first mask layer; patterning said blanket first and second mask layers to form first and second cross sectional sidewalls in said first and second mask layers and to form a center portion of said first mask layer which lies between said first and second sidewalls of said first mask layer, and leaving said first conductive layer unetched; treating said first and second sidewalls of said first mask layer, said second mask layer protecting said center portion of said first mask layer such that said center portion remains untreated subsequent to treating said first and second sidewalls of said first mask layer; removing said second mask layer; removing said center portion of said first mask layer and leaving said first and second treated sidewalls of said first mask layer; subsequent to removing said center portion of said first mask layer, etching said first conductive layer using said first and second treated sidewalls as a pattern to form first and second sidewalls from said first conductive layer; subsequent to etching said first conductive layer using said first and second sidewalls as a pattern, forming a blanket second conductive layer, wherein said blanket second conductive layer impinges on itself between said first and second sidewalls of said first conductive layer and remains unimpinged in other regions overlying said semiconductor wafer substrate assembly; and removing said second conductive layer in the absence of an etch mask such that a portion of said second conductive layer remains between said first and second sidewalls of said first conductive layer and said second conductive layer is completely removed in said other regions overlying said semiconductor wafer substrate assembly.