Patent ID: 6630860
Filing Date: 2003-10-07
Classification: H03H,H03L

Abstract:
A phase locked-loop (PLL) active filter integrated circuit with selectable bandwidth ranges comprising:an amplifier having an amplifier input and an amplifier output; and a filter network having a first port, a second port, a third port, and a fourth port, the first port for accepting an input signal, the second port connected to the amplifier input, the third port coupled to the amplifier output to provide a filtered signal in a selectable range of bandwidths in response to bandwidth range commands received at the fourth port; wherein: the filter network includes a selectable R1 resistor connected between the first port and the second port, and a selectable parallel R2 resistor/C1 capacitor network connected between the second port and the third port; the selectable R1 resistor includes: a first resistor having a plurality of selectable series resistors, an input connected to the first port, and an output; a second resistor having an input connected to the output of the first resistor, and an output connected to the second port; and a first switch having an input connected to the first port, and an output connected to the output of the first resistor; and the first resistor includes: a third resistor having an input connected to the input of the first switch, and an output; a fourth resistor having an input connected to the output of the third resistor, and an output; a fifth resistor having an input connected to the output of the fourth resistor, and an output; a sixth resistor having an input connected to the output of the fifth resistor, and an output; a seventh resistor having an input connected to the output of the sixth resistor, and an output; an eighth resistor having an input connected to the output of the seventh resistor, and an output; a ninth resistor having an input connected to the output of the eighth resistor, and an output connected to the input of the second resistor; a second switch having an input connected to the input of the fourth resistor, and an output connected to the output of the fourth resistor; a third switch having an input connected to the input of the sixth resistor, and an output connected to the output of the seventh resistor; and a fourth switch having an input connected to the input of the seventh resistor, and an output connected to the output of the eighth resistor.