Patent ID: 6646303
Filing Date: 2003-11-11
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device, comprising:a memory array including, a plurality of nonvolatile memory cells disposed on a semiconductor substrate in matrix form; and wherein source/drain regions of the plurality of nonvolatile memory cells are connected in parallel with one another in respective columns, and word lines respectively extend in a first direction of the nonvolatile memory cells; wherein each of the plurality of nonvolatile memory cells includes a lower conductor film for a floating gate electrode, which is provided on a channel region in the first direction between the source/drain regions with a first insulating film interposed therebetween, an upper conductor film for the floating gate electrode, which is electrically connected to the lower conductor film and is formed so as to extend on the source/drain regions from the lower conductor film with a second insulating film placed on the source/drain regions being interposed therebetween, and a conductor film for a control gate electrode, which is provided on the upper conductor film with a third insulating film interposed therebetween and serves as one of said word lines superimposed on the upper conductor film, and wherein widths taken along a second direction crossing the first direction, of the lower conductor film on each channel region and of the word line thereat are thinner than widths taken along the second direction, of a portion of the upper conductor film placed on the second insulating film and of a corresponding portion of the word line.