Patent ID: 6297114
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A process of fabricating a semiconductor device comprising the steps of:(1) forming a gate electrode on a silicon semiconductor substrate;(2) introducing a second impurity, which will form a second impurity diffusion region, into said silicon semiconductor substrate through an ion implantation, said second impurity diffusion region touching a channel region formed on a surface of said silicon semiconductor substrate beneath said gate electrode;(3) forming a sidewall dielectric film on a sidewall of said gate electrode;(4) introducing a first impurity, which will form a first impurity diffusion region, into said silicon semiconductor substrate through the ion implantation, said first impurity diffusion region being offset to said channel region and deeper than said second impurity diffusion region and having a lower impurity concentration than said second impurity diffusion region;(5) forming a high-melting-point metal silicide film on said gate electrode and said silicon semiconductor substrate outside of said sidewall dielectric film; and(6) introducing a third impurity, which will form a third impurity diffusion region, into said silicon semiconductor substrate through the ion implantation, said third impurity diffusion region being formed in said first impurity diffusion region and shallower than said first impurity diffusion region and touching said second impurity diffusion region at the side surface in the channel region, said third impurity diffusion region having a higher impurity concentration than said first and second impurity diffusion regions.