Patent ID: 6746951
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A bond pad structure of a semiconductor device, comprising:a semiconductor substrate including a lower dielectric layer and a lower copper pattern; a first dielectric layer pattern formed on the semiconductor substrate, in which first contact holes are formed to be vertically connected to the lower copper pattern and a first lattice structure is formed to be horizontally disposed on the first contact holes; a first copper pattern formed by a damascene technique in the first dielectric layer pattern and connected to the lower copper pattern such that the first copper pattern fills the first contact holes and the first lattice structure; a second dielectric layer pattern formed over the first copper pattern, in which second contact holes are formed to be vertically connected to the first copper pattern, and a second lattice structure different from the first lattice structure is formed to be horizontally disposed on the second contact holes; a second copper pattern formed by a damascene technique in the second dielectric layer pattern and connected to the first copper pattern such that the first copper pattern fills the second contact holes and the second lattice structure; a passivation layer formed on the second copper pattern; a bond pad formed by patterning a portion of the passivation layer; and a conductivity improving layer formed over the exposed second copper pattern of the bond pad.