Patent ID: 8316366
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. A method for executing a transaction on a simultaneous speculative threading (SST) processor, comprising: using a primary strand to non-transactionally execute instructions for a software thread and to defer instructions which cannot be executed due to unresolved data dependencies; using a subordinate strand to non-transactionally execute deferred instructions in the deferred instructions as data becomes available for the deferred instructions; when the primary strand or the subordinate strand access a cache line during non-transactional execution, updating a record for the accessed cache line to indicate a first strand ID; upon encountering a transaction with the primary strand, checkpointing the primary strand and executing the transaction with the primary strand while continuing to non-transactionally execute deferred instructions with the subordinate strand; when the subordinate strand non-transactionally accesses a cache line during the transaction, updating a record for the cache line to indicate the first strand ID; and when the primary strand transactionally accesses a cache line during the transaction, updating a record for the cache line to indicate a second strand ID, wherein during the transaction the first strand ID identifies the subordinate strand and the second strand ID identifies the primary strand.