Patent ID: 6760857
Filing Date: 2004-07-06
Classification: G11C

Abstract:
A clock signal driven device, comprising:a first clock pin for receiving a first externally generated clock signal during a normal mode of operation; the first externally generated clock signal having predefined signal characteristics; internal circuitry coupled to the first clock pin and responsive to the externally generated clock signal during said normal mode of operation; a clock source on the device providing a first internal clock signal; and an internal clock generator coupled to the first clock pin and to the clock source, the internal clock generator configured during a test mode of operation to generate from the first internal clock signal and to assert on the first clock pin a first test clock signal, the first test clock signal having substantially similar signal characteristics to the predefined signal characteristics of the first externally generated clock signal; wherein the internal circuitry is responsive to the first test clock signal during said test mode of operation.