Patent ID: 8658467
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A method of manufacturing a stacked wafer level package comprising: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming external connection means on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; filling the contact holes with metal posts to be electrically connected to the solder balls, the metal posts formed by filling the contact holes with a plating layer or a conductive paste; and stacking an electronic component to be electrically connected to the metal posts.