Patent ID: 8902670
Filing Date: 2014-12-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: memory cell arrays each comprising blocks, the block being unit of erase and comprising a plurality of string-groups, each string-group comprising strings, each string comprising a first transistor, memory cell transistors, a second transistor coupled in series, the first transistor being connected to different bit line and the second transistor being connected to same source line, wherein the memory cell arrays are provided with different respective block address signals, the memory cell arrays are provided with different respective string address signals, each of the block address signals specifies one block, each of the string address signals specifies one string-group, a first string group of a first one of the memory cell arrays and a second string group of a second one of the memory cell arrays are accessible in parallel, and an address of the first string group and an address of the second string group are specified separately.