Patent ID: 6274485
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method of forming metal plug metallization in the fabrication of integrated circuits comprising:providing semiconductor device structures in and on a semiconductor substrate;providing an insulating layer covering said semiconductor device structures;depositing a sacrificial layer overlying said insulating layer;etching an opening through said sacrificial layer and said insulating layer to one of said semiconductor device structures;depositing a metal layer over the surface of said sacrificial layer and within said opening;polishing away said metal layer and said sacrificial layer overlying said insulating layer wherein said metal layer has a first polishing rate, said sacrificial layer has a second polishing rate and said insulating layer has a third polishing rate and wherein said second polishing rate is higher than said first polishing rate by a ratio of 5:3 whereby after said sacrificial layer is completely removed, a polished surface of said metal layer remaining within said opening has a convex shape; andover-polishing said insulating layer until endpoint detection is received wherein said first polishing rate is higher than said third polishing rate whereby said convex shape is made substantially planar during said over-polishing to complete said formation of said metal plug metallization in said fabrication of said integrated circuit.