Patent ID: 6734054
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method of manufacturing an ESD protection circuit located under a pad which is to be formed later, the method comprising the steps of:providing a substrate; forming a P-well and an N-well in a substrate wherein an interface is formed between the P-well and the N-well; selecting a pad window in the substrate, wherein the pad window crosses over the interface, wherein the pad window is located under the pad which is to be formed later; forming a first shallow trench isolation structure, a second shallow trench isolation structure and a third isolation structure in the substrate within the pad window, wherein the first shallow trench isolation structure is located over the interface, the second shallow trench isolation structure is located in the P-well, and the third shallow trench isolation structure is located in the N-well, wherein in the P-well, the second shallow trench isolation structure encloses a first inner region that is separated from a first outer region and in the N-well, the third shallow trench isolation structure encloses a second inner region that is separated from a second outer region; respectively forming n-type doped regions in the first inner region of the P-well and in the second inner region of the N-well; respectively forming first p-type doped regions in the first outer region of the P-well and in the second outer region of the N-well; and respectively forming second p-typo doped regions in the outer regions and under the n-type doped regions, wherein one of the second p-type doped regions, which is under the second inner region, has an electrical contact with the n-type doped region in the N-well to form a first zener diode, and another of the second p-type doped regions, which is under the first inner region, has an electrical contact with the n-type doped region in the P-well to form a second zener diode.