Patent ID: 6857524
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A tray for a semiconductors comprising: a tray portion having a top horizontal planar surface and a bottom horizontal planar surface, wherein the top horizontal planar surface has a plurality of chip recesses arranged in a matrix formed therein, said chip recesses positioned above the bottom planar surface; a rail portion extending substantially around the tray portion and offset downwardly from the top tray portion, wherein the rail portion has a top horizontal planar surface and a bottom horizontal planar surface; and an intermediate portion interconnecting the tray portion and the rail portion, wherein the intermediate portion has an outwardly facing surface and an inwardly facing surface, wherein the outwardly facing surface has four planar faces one at each side of the tray, wherein each planar face of the outwardly facing surface extends from the top horizontal planar surface of the tray portion to the top horizontal planar surface of the rail portion, and wherein each of the four planar faces of the outwardly facing surface is oriented at an angle of more than 115° with respect to the rail portion, wherein each of the inwardly facing surfaces has four inward planar faces, each of which extends from the bottom horizontal planar surface of the tray portion to the rail portion and wherein the bottom horizontal surface of the tray portion is generally aligned with the top horizontal surface of the rail portion.