Patent ID: 8349740
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. A method, comprising: forming a first stress-inducing layer above first and second conductive lines formed in a first device region of a semiconductor device and above a second device region comprising a plurality of closely spaced transistor elements; performing an etch process for removing said first stress-inducing layer from above said second conductive lines and said plurality of closely spaced transistor elements while maintaining said first stress-inducing layer above said first conductive lines; forming a second stress-inducing layer on said second conductive lines, on said first stress-inducing layer that is maintained above said first conductive lines, and on said plurality of closely spaced transistor elements; selectively removing said second stress-inducing layer and material of said first stress-inducing layer from above said first conductive lines and selectively removing said second stress-inducing layer from above said plurality of closely spaced transistor elements; and forming at least one further stress-inducing layer above said first and second conductive lines and said plurality of closely spaced transistor elements, said at least one further stress-inducing layer and said first stress-inducing layer inducing the same type of stress.