Patent ID: 6954092
Filing Date: 2005-10-11
Classification: H03L

Abstract:
1. A PLL circuit comprising: a phase comparison circuit generating a phase difference signal in accordance with a phase difference between a reference clock signal and a comparison target clock signal; a charge pump circuit for outputting a current in accordance with said phase difference signal; and an oscillation circuit oscillating at a predetermined oscillation frequency in accordance with the control signal generated in accordance with the output current of said charge pump circuit, generating said comparison target clock signal in accordance with the oscillation signal, and outputting it to said phase comparison circuit; wherein said PLL circuit has a locked state detection circuit for detecting whether said PLL circuit is in a locked state; the charge pump circuit comprises first and second transistors connected in series between a first power supply and an output terminal, a third transistor connected between a connection point of said first and second transistors and a second power supply, and a control signal generation circuit; said control signal generation circuit: said first, second and third control signals are generated by said control generation circuit in accordance with said phase difference signal.