Patent ID: 7888961
Filing Date: 2011-02-15
Classification: G01R

Abstract:
1. A test structure for localizing defects leading to shorts in an integrated circuit, the test structure comprising: a first pair of interleaved sets of fingers in a first region: a second pair of interleaved sets of fingers in a second region; a first busbar coupled to a first set of the first pair of interleaved sets of fingers and a first set of the second pair of interleaved sets of fingers; a second busbar in the first region, wherein the second busbar is coupled connected to a second set of the first pair of interleaved sets of fingers; a third busbar in the second region, wherein the third busbar is coupled to a second set of the second pair of interleaved sets of fingers; a first series of pass gates in the first region, wherein the first series of pass gates selectively coupling one set of the first pair of interleaved sets of fingers; and a second series of pass gates in the second region, wherein the second series of pass gates selectively coupling one set of the second pair of interleaved sets of fingers to one of the first and third busbars, respectively.