Patent ID: 6033957
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A method of forming a semiconductor memory cell comprising the steps of:forming, in a substrates, lower and upper doped regions;forming an array of pillars arranged in rows and columns, wherein said rows of pillars are in the bitline direction of the cell and said columns of pillars are in the wordline direction of the cell, each of said pillars having a body portion separating said lower and upper doped regions, one sidewall of said pillar extending between said lower and upper doped regions, and another sidewall of said pillar extending from said upper doped region to a region which is below said lower doped region thereby separating lower doped regions of adjacent pillars of said memory cell so that said lower doped regions of pillars arranged in said wordline direction are not shared while said lower doped regions of said pillars in said bitline direction are shared.