Patent ID: 6346450
Filing Date: 2002-02-12
Classification: H01L

Abstract:
A process for manufacturing at least one MIS transistor with a low resistivity grid on a semiconductor substrate, comprising the steps of:producing a dummy grid on the substrate, the dummy grid comprising at least one material capable of resisting heat treatment; forming self-aligned source and drain regions in the substrate; depositing a first electrically insulating layer of silicon oxide doped with phosphorus and then a second electrically insulating layer of borophosphosilicate or silicon oxide that is not intentionally doped, the first and second electrically insulating layers coating the dummy grid; polishing the first and second electrically insulating layers stopping on the dummy grid; eliminating the dummy grid to define an opening; partially etching the first and second electrically insulating layers to flare the opening; and forming in the opening a final grid including at least one material with low resistivity and separated from the substrate by a grid insulation layer.