Patent ID: 6541324
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A method of forming a memory device on a semiconductor substrate that has a memory cell array region for containing an array of memory cells and a peripheral region for containing logic devices, the method comprising the steps of:forming a plurality of floating gates of a conductive material that are disposed over and insulated from the memory cell array region of the semiconductor substrate; forming a first insulation material over the floating gates; forming a first conductive material over the semiconductor substrate having first portions disposed over the first insulation material, second portions each disposed laterally adjacent to and insulated from one of the floating gates, and a third portion disposed over and insulated from a peripheral region of the substrate; forming a second insulation material over the first conductive material having first, second and third portions disposed over the first conductive layer first, second and third portions respectively; forming patterned dummy material over the second insulation material third portion; applying a chemical-mechanical polishing process to remove: the first portions of the second insulation material and the first conductive material, the patterned dummy material, and top portions of the first insulation material, of the first conductive material second portions and of second insulation material second and third portions, wherein the first insulation material, the first conductive material second portions and the second insulation material second portions are all left with top surface portions that are exposed and substantially co-planar with each other; forming a plurality of first and second regions in the substrate each having a conductivity type different from that of a portion of the substrate adjacent thereto, wherein each of the second regions is spaced apart from the first regions.