Patent ID: 8904086
Filing Date: 2014-12-02
Classification: G06F,G11C

Abstract:
1. A flash memory storage system, comprising: one single flash memory chip, having a plurality of physical blocks, wherein each of the physical blocks has a plurality of physical addresses, and the physical addresses include a plurality of fast physical addresses and a plurality of slow physical addresses, wherein a speed of writing data into the fast physical addresses is faster than a speed of writing data into the slow physical addresses; and a flash memory controller, coupled to the flash memory chip and configured to perform: receiving a first data from a host system; determining whether a first slow physical address among the slow physical addresses of the flash memory chip or a first fast physical address among the fast physical addresses of the flash memory chip is selected for storing the first data, so as to decide whether the first data is to be programmed to a second fast physical address or the first fast physical address; first temporarily storing the first data in the second fast physical address among the fast physical addresses of the flash memory chip if the first slow physical address among the slow physical addresses of the flash memory chip is selected for storing the first data; writing the first data into the first fast physical address if the first fast physical address among the fast physical addresses of the flash memory chip is selected for storing the first data; and writing the first data temporarily stored in the second fast physical address of the flash memory chip and a second data temporarily stored in a third fast physical address of the flash memory chip into two corresponding slow physical addresses among the slow physical addresses of the flash memory chip from the second fast physical addresses and the third fast physical address in a synchronization mechanism.