Patent ID: 6557084
Filing Date: 2003-04-29
Classification: G06F

Abstract:
A method for controlling direct accesses by at controller to shared memory locations in a computer system during Limes of address conflict, the computer system comprising a plurality of processors, a plurality of caches, a plurality of bus controllers, and at least one main memory comprising a plurality of memory locations, the method comprising the steps of:providing a write list comprising a plurality of writes, each write corresponding to one of the plurality of memory locations; providing a first controller of the plurality of bus controllers that is coupled to a first processor of the plurality of processors and to a first cache of the plurality of caches, the first bus controller able to enter a priority mode for each of the writes in the write list; receiving a direct read request by the controller to read from a memory location of the plurality of memory locations; determining if the memory location is shared; accessing the write list to determine, if the memory location is shared, if there is a write that is scheduled to a cache line associated with the first cache and corresponding to the memory location; determining if the write corresponding to the memory location is in the priority mode; and rejecting the direct read request by the controller by issuing a retry command to the controller if there is the write scheduled for the memory location and the write is in the priority state; requesting to perform the write to the cache line that corresponds to the memory location; and entering the priority mode for the write if the request to perform the write is rejected.