Patent ID: 6919600
Filing Date: 2005-07-19
Classification: H01L,Y10S

Abstract:
1. A process for forming a permanently-ON MOS transistor comprising the steps of: providing a silicon well region of a first conductivity type; depositing a first insulating layer over the silicon well region of the first conductivity type; removing a portion of said deposited first insulating layer; forming a buried silicon region of a second conductivity type within the silicon well region of the first conductivity type, under the removed portion of said deposited first insulating layer; depositing a second insulating layer over the first insulating layer and over the buried silicon region of the second conductivity type; forming a polysilicon gate region over the second insulating layer; and forming a source region of the second conductivity type and a drain region of the second conductivity type within the buried silicon well region, said source region and drain region contacting said buried silicon region of the second conductivity type.