Patent ID: 7067365
Filing Date: 2006-06-27
Classification: H01L

Abstract:
1. A method of fabricating a high-voltage metal-oxide-semiconductor (MOS) device, comprising the steps of: providing a semiconductor substrate comprising a high-voltage device area thereon and shallow trench isolation (STI) structure that further divides said high-voltage device area into a first sub-area and a second sub-area; implanting ions into said semiconductor substrate within said high-voltage device area to form a first doping region and a second doping region with a channel region defined therebetween; forming a pad oxide layer on said semiconductor substrate; depositing a pad nitride layer on said pad oxide layer; forming an opening in said pad nitride layer and said pad oxide layer, wherein said opening merely exposes a portion of said first sub-area of said high-voltage device area including said channel region; growing a first oxide layer on exposed said semiconductor substrate via said opening; stripping off remaining said pad nitride layer and said pad oxide layer; growing a second oxide layer on said first sub-area and on said second sub-area; forming a gate on said first oxide layer; and performing an ion implantation process, using said gate and said first oxide layer as an implant mask, to form a third doping region within said first doping region and a fourth doping region within said second doping region.