Patent ID: 6696870
Filing Date: 2004-02-24
Classification: H03K

Abstract:
A digital frequency divider for dividing a clock frequency and having a variable phase output, comprising:a shift register for storing a bit sequence chosen according to a division factor and operating under control of a clock signal at a first frequency; a tap off circuit arranged to tap the shift register at one or more variable points and arranged to produce two or more signals representative of the bit sequence; a control logic circuit having at least two inputs respectively arranged to receive the two or more signals representative of the bit sequence and arranged to provide at least two output signals; and a multiplexer arranged to receive the two output signals and to select one of the output signals under control of the clock signal at the first frequency to thereby produce a clock output signal at a second frequency being a division of the first frequency; wherein the tap off circuit and shift register are arranged such that the one or more tap off points of the shift register are variable in position along the bit sequence such that the clock output signal is variable in phase.