Patent ID: 6584512
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A communication DMA device, with a CPU having a prescribed data bit width, a communication circuitry, and a memory sharing a data bus, for outputting to outside via said communication circuit transmission data connected to said memory, comprising:a register for storing, by control from said CPU, information indicating an area of said memory in which data to be transmitted is stored, information indicating capacity of the data to be transmitted, and information indicating start of communication; a bus switching requester for requesting said CPU for release of said data bus in order to allow reading of transmission data of said prescribed data bit width from said memory and for connecting said data bus to said CPU immediately after termination of the reading; a temporary storager for temporarily storing data read from said memory via said data bus based on the information stored in said register; and a data outputter for dividing the data of said prescribed data bit width temporarily stored in said temporary storager and outputting the data to outside via said communication circuit several bits at a time.