Patent ID: 7587556
Filing Date: 2009-09-08
Classification: G06F,Y02D

Abstract:
1. A store buffer comprising: reception logic operable to receive a present request to write a data value to an address in memory; buffer logic having a plurality of entries, each entry being selectively configured to store request information indicative of a previous request and to maintain associated cache information indicating whether a cache line in a cache is currently allocated for writing data values to an address associated with that previous request, said associated cache information being maintained after the data value associated with said previous request has been written to said cache; and entry selection logic for determining which one of said plurality of entries to allocate to store said present request using said request information indicative of a previous request and said associated cache information of said plurality of entries to determine whether a cache line in said cache is currently allocated for writing said data value associated with said present request to said address in memory.