Patent ID: 6121107
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method for manufacturing a capacitor applied to a memory unit including a substrate with a dielectric layer formed on the substrate and an etching stop layer formed on the dielectric layer, the method comprising steps of:a) forming a first, single sacrificial layer over said etching stop layer;b) partially removing said first, single sacrificial layer, said etching stop layer, and said dielectric layer to form a contact window;c) forming a first conducting layer over said first, single sacrificial layer and in said contact window;d) forming a second sacrificial layer over said first conducting layer;e) partially removing said second sacrificial layer, said first conducting layer, and said first, single sacrificial layer to expose a portion of said first, single sacrificial layer;f) forming a second conducting layer alongside said second sacrificial layer, said first conducting layer, and said portion of said first, single sacrificial layer;g) removing said first and second sacrificial layers to expose said etching stop layer, wherein said remaining first conducting layer and said second conducting layer serve as a capacitor plate; andh) forming a rugged conducting layer on said remaining first and second conducting layers.