Patent ID: 8421495
Filing Date: 2013-04-16
Classification: H03K

Abstract:
1. A method of optimizing power usage in an integrated circuit design, said method comprising: manufacturing integrated circuit devices according to an integrated circuit design using manufacturing equipment, said integrated circuit design producing integrated circuit devices that are identically designed and perform at different operating speeds caused by manufacturing process variations; sorting said integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify said integrated circuit devices into different voltage bins, said relatively fast integrated circuit devices consuming more power than said relatively slow integrated circuit devices, establishing a bin-specific current leakage limit for each of said voltage bins; testing current leakage amounts of said integrated circuit devices using a tester; identifying as defective ones of said integrated circuit devices that exceed said bin-specific integrated circuit current leakage limit of a corresponding voltage bin into which each of said digital circuits has been classified; removing said defective ones of said integrated circuit devices to allow only non-defective integrated circuit devices to remain; and supplying said non-defective integrated circuit devices to a customer.