Patent ID: 8728846
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: forming a first metal thermal terminal at a top surface of said integrated circuit; forming a second metal thermal terminal at said top surface of said integrated circuit; forming a first vertical thermally conductive conduit in said integrated circuit, by a process further comprising the steps of: forming a second vertical thermally conductive conduit in said integrated circuit, by a process further comprising the steps of: forming a first lateral thermoelectric element in said integrated circuit, such that a first end of said first lateral thermoelectric element is thermally connected to a bottom surface of said second plurality of vertical metal interconnect elements and a second end of said first lateral thermoelectric element is thermally connected to a silicon substrate of said integrated circuit; forming a second lateral thermoelectric element in said integrated circuit, such that a first end of said second lateral thermoelectric element is thermally connected to a bottom surface of said fourth plurality of vertical metal interconnect elements and a second end of said second lateral thermoelectric element is thermally connected to said silicon substrate of said integrated circuit; forming a first region of silicon dioxide thicker than 250 nanometers in said silicon substrate under said first lateral thermoelectric element; forming a second region of silicon dioxide thicker than 250 nanometers in said silicon substrate under said second lateral thermoelectric element; forming a first electrically conducting element between an electrically negative end of said first lateral thermoelectric element and an electrically positive end of said second lateral thermoelectric element; forming a second electrically conducting element between an electrically positive end of said first lateral thermoelectric element and a first transistor contained in said integrated circuit; and forming a third electrically conducting element between an electrically negative end of said second lateral thermoelectric element and a second transistor contained in said integrated circuit.