Patent ID: 6023752
Filing Date: 2000-02-08
Classification: G06F

Abstract:
A processor with operating routines responsive to interrupts of an interrupt table therein for manipulating data to and from a memory in the processor, said processor providing for an exchange of data between at least two devices each with internal accessible registers and each having a software protocol that is different from each other with a first protocol being used to control a Naval Tactical Data System (NTDS) device and a second protocol being used to control at least one device having a bus topology, said processor comprising:(a) a program driver comprising machine instructions and respective means responsive thereto, said machine instructions and means thereof being responsive to said operating routines of said processor and capable of activating said internal accessible registers of said two devices, said machine instructions being locatable in said memory of said processor, said machine instructions and means thereof comprising the following items:(i) command/chain, wherein a chain item specifies a next machine instruction for the operating routines of the processor to go after a current instruction being acted on by the operating routines of the processor is executed;(ii) count that specifies a number of words comprising said data being exchanged between said two devices; and(iii) address that specifies an address of said memory being accessed by the operating routines of the processor.