Patent ID: 6681296
Filing Date: 2004-01-20
Classification: G06F

Abstract:
An information processor, including a decoder for decoding instructions including at least some graphics instructions and at least some cache control instructions, wherein the decoder is operable to decode at least one 32 bit data-cache-block-set-to-zero-locked instruction bit pattern which allocates cache lines for a locked portion of a cache, wherein bits 0 through 5 encode a primary op code of â€œ4â€ , bits 6 through 10 encode a reserved field of â€œ00000â€ , bits 11 through 15 designate a first register, bits 16 through 20 designate a second register, the content of which is to be added to the content of the first register to provide a cache block address to be cleared or allocated, bits 21 through 30 encode a secondary op code of â€œ1014â€ , and bit 31 encodes a reserved field of â€œ0â€ .