Patent ID: 6822259
Filing Date: 2004-11-23
Classification: G11C,H01L

Abstract:
A computer implemented method of testing a semiconductor device comprising a stacked floating gate structure, a source, a drain and a control gate, said method comprising;a) programming said floating gate; b) applying an electrical stress voltage to said control gate with said source in a source condition and said drain in a drain condition; c) measuring a drain current gate voltage relationship for said semiconductor subsequent to said applying; d) repeating a), b) and c) with said source in a second source condition or said drain in a second drain condition; repeating d) until said electrical stress voltage has been applied; while said drain has been grounded while said source has had a negative and a positive bias voltage relative to said drain; and while said source has been grounded and said drain has had a negative and a positive bias voltage relative to said source; and identifying a gate stack defect on a source side if said drain current gate voltage relationship information collected after electrical stress applications with said drain grounded show different behavior between positive bias and negative bias applied to said source.