Patent ID: 8373483
Filing Date: 2013-02-12
Classification: H03K

Abstract:
1. A low-clock-energy and fully-static latch circuit, comprising: a clock signal that is coupled only to a first clock-activated pull-up transistor and a second clock-activated pull-down transistor; a storage sub-circuit configured to capture a level of an input signal when the clock signal transitions from high to low and hold the level to generate an output signal while the clock signal is low, wherein the first clock-activated pull-up transistor is shared by a first isolation transistor and a second isolation transistor and enables the storage sub-circuit when the clock signal is low and disables the storage sub-circuit when the clock signal is high; and a propagation sub-circuit configured to receive the input signal and propagate the level of the input signal to generate the output signal while the clock signal is high, wherein the second clock-activated pull-down transistor activates the propagation sub-circuit when the clock signal is high and deactivates the propagation sub-circuit when the clock signal is low.