Patent ID: 6248630
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented therein at least one matrix of non-volatile memory cells each having a floating gate and a control gate, each floating and control gate being electroconductive and electrically insulated from each other by means of an intermediate dielectric multilayer including a lower dielectric material layer and an upper silicon oxide layer, and the substrate also having implementation in an area peripheral to the matrix of memory cells of at least a first transistor having a first gate dielectric, the process comprising the steps of:(A) forming a gate oxide layer, a polycrystalline silicon layer that forms the floating gate, and the lower dielectric material layer on the substrate;(B) removing the gate oxide layer, the polycrystalline layer, and the lower dielectric material layer from the area including the at least a first transistor;(C) depositing the upper silicon oxide layer over both the lower dielectric material layer and over the substrate in the area including the at least a first transistor; and(D) after step (C) occurs, forming a first silicon oxide layer in the area including the deposited upper silicon oxide layer, wherein the first silicon oxide layer is formed between the substrate and the deposited upper silicon oxide layer, and the first silicon oxide layer and the upper silicon oxide layer forming the gate dielectric of the at least a first transistor.