Patent ID: 8731135
Filing Date: 2014-05-20
Classification: G09G,G11C

Abstract:
1. A shift register including a cascade arrangement of stages for transmitting a shift pulse, each of the stages comprising: a shift pulse input terminal via which the shift pulse is inputted; a first input terminal to which a first direct-current voltage is applied; a second input terminal to which a second direct-current voltage is applied; a third input terminal via which a first clock signal is inputted to each of the stages, the first clock signal having its clock pulse active in a period that is out of overlap with a period of the shift pulse that is inputted via the shift pulse input terminal, a fourth input terminal via which a signal indicating connection and disconnection between a first predetermined point and the second input terminal is inputted; a fifth input terminal via which a signal indicating connection and disconnection between a second predetermined point and the second input terminal is inputted; a first capacitor having one end connected to a gate terminal of a first output transistor; an input gate, connected to the shift pulse input terminal, which becomes conductive in accordance with a conduction control signal to allow passage of a potential during the period of the shift pulse so that the potential is supplied to the one end of the first capacitor, the conduction control signal being the shift pulse that is inputted via the shift pulse input terminal; a first switching element having one end connected to the other end of the first capacitor, the other end connected to the first input terminal, and a conduction and disconnection control terminal connected to the third input terminal; a second switching element having one end connected to the other end of the first capacitor, the other end connected to the second input terminal, and a conduction and disconnection control terminal connected to the shift pulse input terminal; a third switching element having one end connected to the one end of the first capacitor, the other end connected to the second input terminal, and a conduction and disconnection control terminal connected to the fourth input terminal, the one end of the first capacitor serving as the first predetermined point; a fourth switching element having one end connected to a first output terminal, the other end connected to the second input terminal, and a conduction and disconnection control terminal connected to the fifth input terminal, the first output terminal serving as the second predetermined point; and a first circuit, connected between the first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal, wherein: either: the first circuit includes a first transistor, a second resistor, and a third resistor; the first transistor is a field-effect transistor, the first transistor having one drain/source terminal connected to the first output terminal and the other drain/source terminal connected to the second input terminal; the second resistor is a resistance element having one end connected to a gate terminal of the first transistor and the other end to which a first voltage is applied; and the third resistor is a resistance element having one end connected to the gate terminal of the first transistor and the other end to which a second voltage is applied.