Patent ID: 7629638
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of memory cells formed on a semiconductor substrate, electrically connected in series, and each comprising a first gate electrode including, first and second conductor layers, the second conductor layer being provided in an upper part of the first gate electrode; first and second selecting transistors provided at either end of the plurality of memory cells, electrically connected with the memory cells in series, and each comprising a second gate electrode including first and second conductor layers, the second conductor layer being provided in an upper part of the second gate electrode; a first contact region provided in the semiconductor substrate on outer side of the second gate electrode of the first selecting transistor; a second contact region provided in the semiconductor substrate on outer side of the second gate electrode of the second selecting transistor; a first contact electrode connected with the first contact region; a second contact electrode connected with the second contact region; a barrier insulator being in contact with side surfaces alone of the first and second gate electrodes and the first and second contact electrodes; a first insulator disposed on the semiconductor substrate between the plurality of memory cells; a second insulator disposed between the first insulator and the barrier insulator, and being in contact with an upper surface of the first insulator; an interlayer insulator provided in contact with an upper surface of the second conductor layer; a first wiring connected with the first contact electrode; and a second wiring connected with the second contact electrode.