Patent ID: 7392146
Filing Date: 2008-06-24
Classification: G01R

Abstract:
1. A fault list and test pattern generating apparatus comprising: a short information generating module configured to generate an electrical short information representative of a relationship between logical values of input signals of a plurality of (primitive) cells and a voltage at a shorted portion assumed at outputs of the plurality of (primitive) cells; a threshold value information generating module configured to calculate logical threshold values of input terminals of the plurality of (primitive) cells so as to generate a logical threshold value information; an extracting module configured to extract from a layout information of a semiconductor integrated circuit a bridge fault information including a signal information of a pair of adjacent signal wires within a predetermined adjacent space; a wire length of the pair of adjacent signal wires; an information as to driving cells included in the plurality of cells and driving the pair of adjacent signal wires, and an information of receiving cells included in the plurality of cells, and to which signals on the pair of adjacent signal wires is inputted; a fault list generating module configured to generate, based on the bridge fault information, the electrical short information and the logical threshold value information related to the driving cells and the receiving cells, respectively, a bridge fault list including a bridge fault type determined by a relationship between the voltage values at the shorted portion and the logical threshold values of the input terminals of the receiving cells; and a test generating module configured to generate, based on the bridge fault list, a test pattern that detects bridge faults in the pair of adjacent signal wires.