Patent ID: 6548872
Filing Date: 2003-04-15
Classification: H01L

Abstract:
Integrated circuitry comprising:a substrate having a mean global outer surface extending along a plane; a first field effect transistor comprising a first gate, a first gate dielectric layer, a first channel, and a pair of source/drain regions, one of the first transistor source/drain regions being received elevationally inward of the first channel, the other of the first transistor source/drain regions being received elevationally outward of the first channel, the first field effect transistor having a first channel length defined along the first gate dielectric layer and having at least some portion which is substantially straight linear; a second field effect transistor comprising a second gate, a second gate dielectric layer, a second channel, and a pair of source/drain regions, one of the second transistor source/drain regions being received elevationally inward of the second channel, the other of the second transistor source/drain regions being received elevationally outward of the second channel, the second field effect transistor having a second channel length defined along the second gate dielectric layer and having at least some portion which is substantially straight linear; and the first and second channel lengths having different total lengths, both of the straight linear portions of the first and second channel lengths being angled from the plane, at least one of the straight linear portions of the first and second channel lengths being beveled relative to the plane.