Patent ID: 6410990
Filing Date: 2002-06-25
Classification: H01L

Abstract:
An integrated circuit comprising:a first plirality of wire bond pads located along a horizontal axis, said first wire bond pads comprising power connections, ground connections and input/output (I/O) connections; a second plurality of wire bond pads located along a vertical axis, said second wire bond pads comprising power connections, ground connections and I/O connections; and a plurality of C4 pads arranged in a grid array, each grid defined by the intersection of one of said first wire bond pads and one of said second wire bond pads, and wherein the nearest adjoining C4 pads are located diagonal to one another, said C4 pads comprising power connections, ground connections and I/O connections, said C4 power connections being divided into a first set of vertical rows and electrically coupled to form a plurality of power buses, said C4 ground connections being divided into a second set of vertical rows to form a plurality of ground buses, each of said ground buses being located adjacent one of said power buses and at least one of said second wire bond pad power connections being coupled to one of said power buses along a trace coupling two of said C4 power connections.