Patent ID: 6127224
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A process for manufacturing a non-volatile memory cell integrated in a semiconductor substrate, the process comprising:providing a gate transistor having a first source region, first drain region, and first gate region, said first gate region being raised above the substrate between said first source and drain regions;providing a selection transistor having a second source region, second drain region, and second gate region, said second gate region being raised above the substrate between said second source and drain regions;forming a mask element over at least some of the source and drain regions, the mask element extending completely between the first and second gate regions, wherein the first drain region and the second source region coextensively underlie the mask element between the first and second gate regions and the mask element does not overlie the first and second gate regions;depositing a layer of a transition metal; andapplying a thermal treatment for reacting said layer with semiconductor portions not protected by the mask element.