Patent ID: 9152598
Filing Date: 2015-10-06
Classification: G06F,Y02D

Abstract:
1. A device comprising: a bus master including a bi-directional data line and clock line and being configured to produce a select signal output for enabling data transmission on the bi-directional data line to first and second different data buses that support one or more slave devices, each slave device configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input and first and second outputs and a control input, the input being coupled to the bi-directional data line of the bus master, a first output of the de-multiplexer being coupled to the first data bus and a second output of the de-multiplexer being coupled to the second data bus, wherein the control input is configured to receive the select signal from the bus master; wherein the bus master is configured to communicate to a first slave device coupled to the first data bus when the select signal is in a first state, and to communicate to a second different slave device coupled to the second data bus when the select signal is in a second different state.