Patent ID: 6925005
Filing Date: 2005-08-02
Classification: G11C

Abstract:
1. A memory circuit, comprising: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing a potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell, wherein the sense timing differs in accordance with a position of the selected memory cell in the memory cell array, and wherein, when the selected memory cell is positioned at a first distance from the page buffer, the page buffer makes a judgment by means of first sense timing, and when the selected memory cell is positioned at a second distance from the page buffer which is longer than the first distance, the page buffer makes a judgment by means of second sense timing that lags behind the first sense timing.