Patent ID: 7750393
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: at least one first control gate electrode arranged on a semiconductor substrate; a gate insulating layer interposed between the semiconductor substrate and the at least one first control gate electrode; a storage node layer interposed between the gate insulating layer and the at least one first control gate electrode; a blocking insulating layer interposed between the storage node layer and the at least one first control gate electrode; a plurality of first dopant doping regions disposed along a first side of the at least one first control gate electrode; a plurality of second dopant doping regions along a second side of the at least one first control gate electrode opposite to the first side; a plurality of first channel regions adjacent to the first side of the at least one first control gate electrode and defined in portions of the semiconductor substrate between every two adjacent first dopant doping regions; and a plurality of second channel regions adjacent to the second side of the at least one first control gate electrode and defined in portions of the semiconductor substrate between every two adjacent second dopant doping regions.