Patent ID: 8404535
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A method for fabricating metal gate transistor, comprising: providing a substrate having a first transistor region and a second transistor region; forming a stacked film on the substrate, wherein the stacked film comprises at least one high-k dielectric layer and a first metal layer; patterning the stacked film to form a plurality of gates in the first transistor region and the second transistor region; forming a dielectric layer on the gates; planarizing a portion of the dielectric layer until reaching the top of each gate; only removing the first metal layer from the gate of the second transistor region and keeping the first metal layer in the gate of the first transistor region; and depositing a second metal layer over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.