Patent ID: 8937833
Filing Date: 2015-01-20
Classification: G11C

Abstract:
1. A method of operating a semiconductor memory device, the method comprising: supplying a positive source voltage to a source line coupled in common to source select transistors of memory strings, and supplying a precharge voltage to unselected bit lines of a plurality of bit lines respectively coupled to drain select transistors of the memory strings; supplying a pass voltage to unselected memory cells of a plurality of memory cells coupled to and disposed between the source select transistors and the drain select transistors; supplying a read voltage to selected memory cells of the plurality of memory cells; and sensing voltage or current of selected bit lines of the plurality of bit lines, which are coupled to the selected memory cells, wherein the positive source voltage is supplied to the source line so as to increase channel potential of memory strings coupled to the unselected bit lines while the pass voltage is supplied to the unselected memory cells and the read voltage is supplied to the selected memory cells.