Patent ID: 6197660
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A process for filling a shallow trench in an integrated circuit, comprising the sequential steps of:providing a silicon body having an upper surface on which there is a layer of silicon nitride and from which a plurality of shallow trenches of varying lengths, widths, and depths extend downward's into said silicon body;by means of HDPCVD, depositing a layer of silicon oxide onto said surface and into said trenches whereby the trenches are over-filled;by means of a conformal coating method, depositing a layer of a dielectric on said layer of silicon oxide;by means of CMP, removing said dielectric layer and a portion of the silicon oxide whereby all of said upper surface remains coated by an amount of silicon oxide having a thickness; andusing a wet etch, removing an additional amount of the silicon oxide whereby the silicon nitride is fully exposed and said trenches are fully filled.