Patent ID: 8464203
Filing Date: 2013-06-11
Classification: G06F

Abstract:
1. A test system equipped with a CPU and a user break controller integrated with a break address register and configured to generate a break interrupt request when a function corresponding to an address set to the break address register is executed, the test system testing a program to be executed by the CPU, the test system comprising: an address storage configured to store therein an address of each function to be executed by the CPU based on a test target program to be tested, the addresses of the functions being stored together with information of an order in which the addresses of the functions should be set in the break address register; an initial process unit configured to set, to the break address register, a first-ordered address in the addresses stored in the address storage; an address updating unit configured to use the break address register as a function updating counter by updating the address, currently set to the break address register, to the address of a function next to a function corresponding to the address currently set to the break address register when the break interrupt request is generated; and a determining unit configured to determine whether a sequence of instructions based on the test target program is normal based on an operation result of the address updating unit, wherein, when the address updating unit operates in response to execution of a last-ordered function, the determining unit determines that the sequence of the instructions is normal, and, when the address updating unit does not operate in response to execution of the last-ordered function, the determining unit determines that the sequence of the instructions is abnormal.