Patent ID: 6678870
Filing Date: 2004-01-13
Classification: G06F

Abstract:
An optimization system which optimizes a delay of a signal traveling in a logical circuit configured by connecting a plurality of circuit blocks by changing a specification about a primitive device specified for each circuit block for use in configuring the circuit blocks into a specification about another primitive device having the same function and a different driving ability value, comprising:a driving ability value computation unit computing a driving ability value required for each target circuit block based on a delay rate of the circuit block indicating a rate of the delay of a signal traveling in the circuit block by a load capacity value provided for the circuit block, a driving ability value of a prior stage circuit block determined by the device specified for a prior stage circuit block connected at a stage prior to a target circuit block for which the specification is changed, and a load capacity value provided for the target circuit block by connecting another circuit block at a stage subsequent to the target circuit block; and a change unit changing the specification of the device used in the target circuit block based on the driving ability value obtained in the computation.