Patent ID: 8711602
Filing Date: 2014-04-29
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.