Patent ID: 6621284
Filing Date: 2003-09-16
Classification: G01R

Abstract:
A circuit arrangement for post-package trimming, comprising:a test mode input circuit configured to identify a test mode operation and to generate a test mode signal; a register control circuit coupled to said test mode input circuit and configured to generate a data signal and a plurality of control signals during said test mode operation; a register circuit comprising at least one bit circuit including a storage device and a shift register bit latch, said register circuit coupled to said register control circuit to receive said data signal and said control signals and said register circuit configured to supply said data signal and said control signals to said at least one bit circuit to program said storage device and to generate a plurality of trim control signals; a program voltage sense circuit coupled to said register circuit and configured to sense a program voltage; and a trim control circuit coupled to said register circuit and configured to apply said trim control signals.