Patent ID: 6582997
Filing Date: 2003-06-24
Classification: H01L

Abstract:
A method for protecting from electrostatic discharge (ESD) the output of an integrated circuit with resistor loading, comprising the steps of:a) providing a first MOS transistor of a first conductivity type in a region of a second conductivity type of a semiconductor substrate; b) splitting the drain of said first MOS transistor into two regions adjacent to each other, thereby creating two parasitic diodes and two parasitic bipolar transistors; c) providing a second MOS transistor of a second conductivity type in a region of a first conductivity type in the semiconductor substrate; d) splitting the drain of said second MOS transistor into two regions adjacent to each other, thereby creating two parasitic diodes; e) coupling the drain which is adjacent to the gate of each of said MOS transistors, via a resistive means, to an output pad; and f) connecting the other drain of each of said MOS transistors to said output pad.