Patent ID: 8775905
Filing Date: 2014-07-08
Classification: G06F,G11C,H03M

Abstract:
1. A memory system comprising: a first non-volatile memory operable to store data to be accessed in units of blocks, wherein each of said blocks is divided into a first area and a second area; a second non-volatile memory operable to store data to be accessed in word units in random accesses to said second non-volatile memory; and a control section operable to control operations of said first and second non-volatile memories, wherein first error correction codes to be applied to said data stored in said first non-volatile memory are stored in said second area of one or more of said blocks of said first non-volatile memory, wherein second error correction codes to be applied to said data stored in said second non-volatile memory are stored in said first area of said one or more of said blocks, and wherein said second error correction codes are associated with consecutive addresses in said second non-volatile memory.