Patent ID: 8422271
Filing Date: 2013-04-16
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: a plurality of memory cells each comprising a resistive sense element (RSE) in series with a switching device; a conductive word line extending in a first direction adjacent the memory cells and connected to a gate structure of each of the switching devices; and a plurality of conductive bit lines extending in a second direction adjacent the memory cells, each bit line providing a connection node that interconnects a respective pair of the memory cells of said plurality; and a control circuit adapted to sense a programmed state of a selected memory cell of said plurality by setting each of the bit lines on a first side of the selected memory cell to a first voltage level, setting each of the remaining bit lines on an opposing second side of the selected memory cell to a second voltage level, and setting the word line to a third voltage level, the control circuit further adapted to successively sense the programmed state of each of the memory cells of said plurality in turn by successively toggling each of the bit lines between the first and second voltages.