Patent ID: 8971141
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A sense amplifier for a memory circuit, comprising: an intermediate circuit, including a first node selectively connectable to one or more bit lines; bit line selection circuitry connected to the first node, whereby the first node is selectively connectable to one or more bit lines; a pre-charge switch by which the first node is connectable to a first supply level for pre-charging of the first node for a sensing operation; a first latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; a second latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; and first and second switches whereby the values latched in the first and second latch circuits are respectively transferrable to a data bus, wherein, in a sensing operation, after pre-charging the first node and prior to a subsequent pre-charging, the first and second data latch circuits are sequentially connectable to have the value latched therein set according to the level of the first node.