Patent ID: 6833764
Filing Date: 2004-12-21
Classification: H03L

Abstract:
A phase-locked loop (PLL) frequency synthesizer comprising:a first PLL circuit comprising: i) a first feedforward frequency divider capable of receiving an F(in) reference signal having an F(in) frequency and generating an F1 signal having an F1 frequency, where F1âˆ’F(in)/P, ii) a first PLL core capable of receiving said F1 signal and generating an F2 signal having an F2 frequency, where F2=(P+1)F1, and iii) a first feedback frequency divider capable of receiving said F2 signal and generating a first feedback signal having a frequency F2/(P+1); a second PLL circuit comprising: i) a second feedforward frequency divider capable of receiving said F2 signal and generating an F3 signal having an F3 frequency, where F3=F2/(N+1), ii) a second PLL core capable of receiving said F3 signal and generating an F(out) signal having an F(out) frequency, where F(out)=(N)F3, and iii) a second feedback frequency divider capable of receiving said F(out) signal and is generating a second feedback signal having a frequency F(out)/(N); and a clock controller capable of monitoring said F(out) signal and further capable of tuning said F(out) frequency by modifying at least one of N or P.