Patent ID: 6374365
Filing Date: 2002-04-16
Classification: G06F

Abstract:
Device for the operation of two functionally parallel processors (CPU 1, CPU 2) of known manufacturing-related component tolerances of which each is clock-pulse triggered (CPU clock) with both processors (CPU 1, CPU 2) being cycled via a common clock (CGEN) and with both processors (CPU 1, CPU 2) being synchronously cycled and with the output signals of both processor s (bus 1,1 . . . N and bus 2, 1 . . . N) being brought to a functional (I) in which the module-tolerance-caused delay of the output signals (bus 1,1 . . . N) and bus 2,1 . . . N) of the two processors (CPU 1, CPU 2) is compensated for and which are used for a single control function, characterized in that;the two processors (CPU 1, CPU 2) are operated parallel with each other and that for this purpose the signals, which are time delayed for this purpose, are generated from the clock pulse (clock) of a single clock pulse generator (CGEN) for the entire system through parallel conditioning of its clock pulse signals, of which one is the signal CPU-clock, another serves to compensate for differences in the time behavior of like-named signals in bus 1 and bus 2 (signal anti-jitter), and another indicates those points in time at which all like-named signals in bus 1 and bus 2 must be identical (signal time out) and that the functional module (I) in addition to the output signals (bus 1,1 . . . N or bus 2,1 . . . N) of the two processors (CPU 1, CPU 2) is impacted by the parallel but delayed signals anti-jitter and time-out, and that with the compensation of the module-tolerance-caused delayed simultaneously the output signals (bus 1,1 . . . N and bus 2,1 . . . N) are linked into a single output signal (bus, 1 . . . N) which can be used for the peripherals of the computer.