Patent ID: 6734709
Filing Date: 2004-05-11
Classification: G11C,H03K

Abstract:
A system operable to sample on the fly synchronously or asynchronously using minimal clock cycle delay synchronization one or more nodes of an integrated circuit that are coupled to one or more bus domain clocks, comprising:circuitry comprising one or more bus clocks of the one or more bus clock domains; a sample on the fly (SOF) circuit coupled to the one or more nodes, said SOF circuit operable to produce an UPDATE signal to latch the one or more nodes; a set-reset (S-R) circuit coupled to the SOF circuit operable to perform a set and reset of the UPDATE signal; and a metastable rejection circuit coupled to the SOF circuit and coupled to the S-R circuit, said metastable rejection circuit operable to ensure latching of all nodes when a sample on the fly UPDATE signal is received.