Patent ID: 6706554
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method of fabricating an IC chip comprising:laminating a first insulating layer on a board; forming an electrode pad on the board, the electrode pad serving as an input/output terminal; laminating a second insulating layer over the board and the electrode pad; forming a resist pattern on the second insulating layer at a region other than a part of the electrode pad; etching and removing the second insulating layer using the first resist pattern as a mask, thereby defining a first opening in the second insulating layer on the electrode pad; filling the opening with a conductive material layer made of a conductive material; laminating a third insulating layer over the second insulating layer and the conductive material layer; forming a second resist pattern on the third insulating layer at a region other than a region of the conductive material layer; etching and removing the third insulating layer using the second resist pattern as a mask, thereby defining a second opening in the third insulating layer at the region of the conductive material layer; filling the second opening with a metal layer made of an electric connection material; etching and removing the third insulating layer and the second insulating layer after said filling the second opening; and forming a filling insulating material on the first insulating layer and the electrode pad after said etching and removing the third insulating layer and the second insulating layer, to surround sidewalls of the conductive material layer and the metal layer.