Patent ID: 7396716
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A method of fabricating a microelectronics device, comprising: forming a capping layer comprising oxide over gate structures located over a microelectronics substrate, the gate structures including sidewall spacers and having a doped region located therebetween; placing a protective layer comprising nitrogen over the capping layer and the doped region; removing a portion of the protective layer and capping layer located over the gate structures to expose a top surface of the gate structures, a remaining portion of the protective layer and capping layer remaining over the doped region, wherein removing the protective layer comprises removing the protective layer with a first etch to expose the capping layer and removing the capping layer comprises removing the capping layer with a second etch; and performing a silicide process to form silicided gate electrodes, wherein the remaining portion of the protective layer and the capping layer over the doped region blocks formation of a silicide in the doped region.