Patent ID: 7538024
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A method of fabricating a dual-damascene copper structure, the method comprising: providing a semiconductor substrate having at least a dielectric layer thereon and at least a dual-damascene hole positioned in the dielectric layer and directly on the semiconductor substrate, a portion of the semiconductor substrate being exposed in a bottom of the dual-damascene hole, a surface of the exposed portion of the semiconductor substrate further comprising a conductive layer composed of silicide; performing a physical vapor deposition (PVD) process to form a conductive substrate-protecting layer on the exposed portion of the semiconductor substrate and a sidewall of the dual-damascene hole; performing an atomic chemical vapor deposition (CVD) process to form a tantalum nitride (TaN) layer on a surface of the substrate-protecting layer, the TaN layer serving as a barrier layer; and forming a copper layer in the dual-damascene hole.