Patent ID: 6321976
Filing Date: 2001-11-27
Classification: B23K,H01L,Y10T

Abstract:
A method of wire bonding of a connection pad on a chip edge area between two chips of a three dimensional chip package, comprising the steps of:preparing a first chip having at least a connection pad near an edge of said first chip;stacking and positioning a second chip above said first chip, said second chip having an edge located near said connection pad;forming a substantially flat conductive bump with an appropriate thickness on said connection pad, said edge of said second chip and the center location of said conductive bump having a distance which is approximately the size of the radius of a capillary;soldering one end of a wire to said conductive bump using said capillary; andbending said wire near said end to form a reverse loop above said conductive bump;wherein said appropriate thickness of said conductive bump is sufficiently large for avoiding collision between said capillary and said second chip when said wire is soldered to said conductive bump and when said wire is bent to form said reverse loop.