Patent ID: 6562665
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A method for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, the method including the steps of:A. forming a pillar of semiconductor material on a layer of buried insulating material, wherein said pillar has a top surface and first and second side surfaces, and wherein said pillar has a width, a length, and a height; B. forming a recess in said top surface of said pillar along said length of said pillar, wherein said recess has sidewalls and a bottom wall of said semiconductor material of said pillar; C. depositing a gate dielectric material on any exposed surface of said semiconductor material of said pillar including at said top surface and said first and second side surfaces of said pillar and at said sidewalls and said bottom wall of said recess, for a gate length along said length of said pillar, wherein an effective drive current width of said field effect transistor is a total perimeter distance of said gate dielectric material on said top surface and said first and second side surfaces of said pillar and on said sidewalls and said bottom wall of said recess; D. depositing a gate electrode material on said gate dielectric material to surround said pillar at said top surface and said first and second side surfaces of said pillar and to fill said recess, for said gate length of said pillar; and E. implanting a drain and source dopant into exposed regions of said pillar to form a drain of said field effect transistor on a first side of said gate electrode material along said length of said pillar and to form a source of said field effect transistor on a second side of said gate electrode material along said length of said pillar.