Patent ID: 9082640
Filing Date: 2015-07-14
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device, comprising: an SRAM cell formed to a semiconductor layer, the SRAM cell comprising: first and second load transistors each comprising an N-type source region and a P-type drain region; first and second driver transistors each comprising a P-type source region and an N-type drain region; and first and second transfer gates each comprising a pass gate, and each of the pass gate of the first transfer gate and the pass gate of the second transfer gate comprising: a first tunnel transistor comprising a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region, and a gate electrode supplied with a control voltage; and a second tunnel transistor connected to the first tunnel transistor in series, the second tunnel transistor comprising a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region electrically connected to the second diffusion region of the first tunnel transistor, and a gate electrode electrically connected to the gate electrode of the first tunnel transistor, wherein the first and second load transistors, and the first and second driver transistors are tunnel transistors.