Patent ID: 6359307
Filing Date: 2002-03-19
Classification: H01L,Y02P

Abstract:
A semiconductor device, comprising:a first multi-layer structure and a second multi-layer structure formed on an active region on the semiconductor substrate, said first multi-layer structure adjacent said second multi-layer structure; a first sidewall spacer formed around said first multi-layer structure; a second sidewall spacer formed around said second multi-layer structure; a dielectric layer formed over the semiconductor substrate, including said first multilayer structure, said first sidewall spacer, said second multi-layer structure, and said second sidewall spacer; a contact formed in said dielectric layer, said contact being in electrical connection with a portion of said region on the semiconductor substrate adjacent said first sidewall spacer and said second sidewall spacer, wherein said portion of said region is a source/drain region of the semiconductor device; and a channel formed in said dielectric layer atop said contact, said channel being in electrical connection with said contact.