Patent ID: 6790729
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method of manufacturing a NAND flash memory device, comprising the steps of:providing a semiconductor substrate in which a plurality of isolation films are formed in parallel to each other, a source select transistor having a cell source region, a plurality of memory cells having a cell impurity region and a drain select transistor having a cell drain region are serially connected and formed in each of a plurality of strings in a cell region, and a peri-transistor having a source/drain junction is formed in a peripheral circuit region; forming a first interlayer insulating film on the resulting semiconductor substrate; etching a portion of the first interlayer insulating film to expose the cell source regions and the isolation films between the regions, and then etching the exposed portions of the isolation films to form a common source line contact hole through which the semiconductor substrate is exposed; performing an ion implantation process to form an ion implantation region on the exposed semiconductor substrate at the bottom of the common source line contact hole; and burying a conductive material within the common source line contact hole in which the ion implantation region is formed, thus forming a common source line.