Patent ID: 6061296
Filing Date: 2000-05-09
Classification: G11C

Abstract:
A method for accessing data in a memory array, the method comprising:sensing a bit in the memory array;generating a first clock signal, the first clock signal having a first pulse;generating a second clock signal, the second clock signal having a second pulse;generating a third clock signal, the third clock signal having a third pulse and a fourth pulse, the fourth pulse occurring before the third pulse; andpropagating a signal representing a logic level of the bit to an output line through a plurality of stages, the plurality of stages including a first stage and a second stage, the first stage being coupled to a first interconnect and a second interconnect, the second stage being coupled to the second interconnect and the output line, wherein:the first interconnect is configured to receive a first data signal that is dependent on the logic level of the bit;the second pulse causes the first stage to generate on the second interconnect a second data signal as a function of the first data signal; andthe third pulse causes the second stage to generate onto the output line an output signal that is dependent on the second data signal, andwherein, during a first mode, the second pulse is triggered by the first pulse and, during a second mode, the second pulse is triggered by the fourth pulse.