Patent ID: 8546222
Filing Date: 2013-10-01
Classification: H01L

Abstract:
1. A method of fabricating a floating-gate p-type MOSFET comprising: forming a first and a second thick oxide region on a p-type substrate; implanting a first and a second Pwell region below the first and second thick oxide region respectively; implanting an Nwell region between the first and second thick oxide regions and the first and second Pwells; growing a gate insulation on the Nwell region; depositing poly-silicon on the gate insulation; etching the poly-silicon to form a poly-silicon gate; forming oxide side-walls on sides of the poly-silicon gate; forming nitride side-walls on the oxide side-walls; implanting an p-type dopant into the Nwell on both sides of the nitride side-walls forming a source and a drain; forming a silicide-blocking layer over the poly-silicon gate, the oxide side-walls, the nitride walls, a first portion of the source and a first portion of the drain; forming a silicide on a second portion of the source and on a second portion of the drain; forming a nitride layer over the silicide-blocking layer, the poly-silicon gate, the oxide side-walls, the nitride walls, the first portion of the source and the first portion of the drain; forming a conductive layer over the nitride layer; forming metal contacts on the second portion of the source and on the second portion of the drain.