Patent ID: 7168067
Filing Date: 2007-01-23
Classification: G06F

Abstract:
1. A method of implementing a software breakpoint in a multiprocessor system having a plurality of processors each coupled to a main memory, each of the processors having an instruction cache associated therewith, the method comprising the steps of: retrieving an instruction, for which the breakpoint is to be inserted, from a corresponding instruction address in the main memory; inserting a breakpoint code at the instruction address in main memory; and after the breakpoint code is executed by a given one of the processors, storing the retrieved instruction in the corresponding instruction cache for that processor and setting a use-once indicator associated with the instruction as stored in the corresponding instruction cache for that processor, wherein the use-once indicator, when set for the instruction as stored in the instruction cache, is operative via cache control logic to clear a validity indicator associated with the instruction after a single fetch of the instruction from the instruction cache, such that subsequent attempts by the given processor to access the instruction as stored in the instruction cache will cause the processor to retrieve the breakpoint code at the instruction address in main memory.