Patent ID: 6396751
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A semiconductor device formed on a silicon substrate, comprising:a plurality of cells formed on the substrate; a plurality of word lines formed on the substrate, said plurality of word lines being sequentially numbered, the odd-numbered word lines being electrically coupled to a first word line test pad, and the even-numbered word lines being electrically coupled to a second word line test pad; and a plurality of bit lines formed on the substrate, the plurality of bit lines being sequentially numbered, the odd-numbered bit lines being electrically coupled to a first bit line test pad, and the even-numbered bit lines being electrically coupled to a second bit line test pad; wherein said odd-numbered word lines and said odd numbered bit lines access a first group of cells, said odd-numbered word lines and said even-numbered bit lines access a second group of cells, said even-numbered word lines and said odd-numbered bit lines access a third group of cells, and said even-numbered word lines and said even-numbered bit lines access a fourth group of cells; whereby applying a predetermined set of test signals to said first word line test pad, said second word line test pad, said first bit line test pad, and said second bit line test pad, interference among said first, second, third, and fourth group of cells can be measured.