Patent ID: 7765352
Filing Date: 2010-07-27
Classification: G06F,Y02D

Abstract:
1. A method to reduce core wake-up latency in a computer system comprising: detecting arrival of a plurality of interrupts by initiating a cumulative latency counter on arrival of a first interrupt of the plurality of interrupts, wherein the first interrupt is to wake-up a first core of a plurality of cores, allowing the cumulative latency counter to continue counting even after the first interrupt is complete, checking if a second interrupt of the plurality of interrupts has arrived before the cumulative latency counter reaches a credit delay value, waking up remaining cores of the plurality of cores, concurrently, in response to receiving the second interrupt before the cumulative latency counter reaches the credit delay value, and allowing the cumulative latency counter to count through the second interrupt if the second interrupt has arrived before the cumulative latency counter reaches the credit delay value.