Patent ID: 6122705
Filing Date: 2000-09-19
Classification: G11C

Abstract:
A memory device comprisinga plurality of memory blocks (25a to 25d) including respective addressable memory cell arrays (27a to 27d) and respective data buffers (26a to 26d) respectively connected to said addressable memory cell arrays and temporarily storing pieces of first data, anda temporary data storage (29b) connected between said data buffers (26a to 26d) and an external device (24; 30) handling a piece of second data, characterized by further comprisinga controlling means (29a/29c/25f) determining a ratio between component bits of said piece of second data and component bits of the piece of first data stored in each data buffer, selectively enabling said plurality of memory blocks for storing said piece of second data as one or more of said pieces of first data and changing a data transfer rate between said temporary data storage and one or more of said data buffers depending upon said ratio.