Patent ID: 6542983
Filing Date: 2003-04-01
Classification: G06F

Abstract:
In a computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline comprising a CPU decoder pipestage and the FPU execution pipeline comprising an FPU decoder pipestage, the method comprising the steps of;a) sending a first instruction to the CPU decoder pipestage; b) sending the first instruction to the FPU decoder pipestage; c) generating a signal indicating that the first instruction has been accepted by the CPU decoder pipestage; d) generating a signal indicating that the first instruction has been accepted by the FPU decoder pipestage; e) sending a second instruction to the CPU decoder pipestage in response to step d, and f) sending a second instruction to the FPU decoder pipestage in response to step c.