Patent ID: 6172905
Filing Date: 2001-01-09
Classification: G11C,H01L

Abstract:
A method of operating a semiconductor device includinga first memory cell,a second memory cell,a third memory cell, anda fourth memory cell, wherein:each of the second memory cell, the third memory cell, and the fourth memory cell has discontinuous storage elements;each of the first, second, third, and fourth memory cells includes:a first current carrying electrode;a second current carrying electrode spaced apart from the first current carrying electrode;a first dielectric layer, wherein the discontinuous storage elements overlies the first dielectric layer;a second dielectric layer overlying the first dielectric layer and the discontinuous storage elements; anda control electrode overlying the second dielectric layer;the first current carrying electrodes of the first and third memory cells are electrically connected to each other;the second current carrying electrode of the first and third memory cells are electrically connected to each other;the first and third memory cells lie at least partially within a first well region;the control electrodes of the first and second memory cells are electrically connected to each other;the first current carrying electrodes of the second and fourth memory cells are electrically connected to each other;the second current carrying electrodes of the second and fourth memory cells are electrically connected to each other;the second and fourth memory cells lie at least partially within a second well region; andthe control electrodes of the third and fourth memory cells are electrically connected to each other; andthe method comprising:providing the semiconductor device, wherein a first memory cell has discontinuous storage elements; andprogramming the first memory cell to a first state, which is one of at least three different states, wherein programming includes:biasing the first current carrying electrodes of the first and third memory cells to a first potential;biasing the second current carrying electrodes of the first and third memory cells to a second potential;biasing the control electrodes of the first and second memory cells to the first potential;biasing the first well region to the second potential;biasing the first current carrying electrodes of the second and fourth memory cells to the first potential;biasing the second current carrying electrodes of the second and fourth memory cells to the first potential;biasing the control electrodes of the third and fourth memory cells to a second potential; andbiasing the second well region to the fist potential.