Patent ID: 8207770
Filing Date: 2012-06-26
Classification: H03L

Abstract:
1. An apparatus, comprising: a digital phase locked loop circuit (DPLL) having a time-to-digital converter (TDC), the TDC comprising: a first ring comprising a first delay cell and an inverter arranged to receive a reference signal, the reference signal circulating in the reference ring over one or more stages that each comprise a reference delay period 2t a second ring comprising a second delay cell and an inverter arranged to receive from a voltage controlled oscillator (VCO) a VCO signal having a phase delay with respect to the reference signal, the VCO signal circulating in the second ring over one or more stages that each comprise a VCO delay period 2t a flip-flop circuit coupled to outputs of the first and second rings, the flip-flop circuit arranged to periodically sample first and second outputs from the first and the second ring, respectively, wherein the phase delay is determined by an amount N of reference delay periods elapsed between when a first reference signal is detected and when an output of the flip-flop corresponds to a zero to one or one to zero transition.