Patent ID: 9117696
Filing Date: 2015-08-25
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a substrate including, a plurality of cell bit lines formed in the cell block of the substrate; a plurality of cell plugs adjacent to side surfaces of the cell bit lines; cell inner spacers formed between the cell bit lines and the cell plugs, the cell inner spacers being in contact with the side surfaces of the cell bit lines; cell outer spacers formed on the cell inner spacers, the cell outer spacers being in contact with the cell plugs; air spacers disposed between the cell inner spacers and the cell outer spacers; a plurality of balancing bit lines formed in the balancing block of the substrate; a plurality of balancing plugs adjacent to side surfaces of the balancing bit lines; balancing inner spacers formed between the balancing bit lines and the balancing plugs, the balancing inner spacers being in contact with the side surfaces of the balancing bit lines; and balancing outer spacers formed on the balancing inner spacers, the balancing outer spacers being in contact with the balancing plugs, wherein