Patent ID: 7872915
Filing Date: 2011-01-18
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: a plurality of word lines; a plurality of main bit lines intersecting with the plurality of word lines; a plurality of cell blocks each including a plurality of cell strings, each of the cell strings including a first select transistor, a second select transistor, and a plurality of memory cells, the memory cells being selected by the respective word lines, wherein the plurality of cell blocks are grouped into a plurality of groups and the number of groups is identical to or smaller than the number of cell blocks; a plurality of sub bit lines, wherein each group has a set of sub bit lines commonly connected to the respective cell strings of the cell blocks in the same group; a plurality of group selectors configured to selectively connect the main bit lines to the sub bit lines of a selected group; and a plurality of page buffers configured to sense data of the memory cells through the main bit lines, wherein each of the group selectors includes a third select transistor connected in series between the first select transistors in adjacent cell blocks of adjacent groups.