Patent ID: 6066532
Filing Date: 2000-05-23
Classification: H01L

Abstract:
A method of fabricating an embedded gate electrode, comprising the steps of:providing a semiconductor substrate;forming a patterned etch resistant mask layer over said semiconductor substrate, wherein said patterned etch resistant mask layer has a first opening for a location of a trench;anisotropically etching through said patterned etch resistant mask layer and into said semiconductor substrate for a time period, hence forming said trench at said location;removing said patterned etch resistant mask layer;depositing a first insulating layer over said semiconductor substrate and filling up said trench;planarizing said first insulating layer to a height above a surface of said semiconductor substrate;patterning said planarized first insulating layer to define a second opening for said embedded gate electrode at said location, said second opening is smaller than said first opening;forming a second insulating layer at a bottom of said second opening;depositing a conductive layer over said second insulating layer and filling up said second opening, hence forming said embedded gate electrode;ion implanting said semiconductor substrate through a first photo mask to form source/drain regions having a first bottom depth deeper than a second bottom depth of said trench inside said semiconductor substrate;removing and patterning a portion of said planarized first insulating layer as well as said first photo mask, thus leaving a spacer on a sidewall of said embedded gate electrode;depositing a refractory metal layer over an entire exposing surface of a resulting structure;annealing said refractory metal layer to form a silicide layer on said embedded gate electrode and elsewhere on said source/drain regions; andremoving an unreacted refractory metal layer and a refractory metal reaction product other than silicide.