Patent ID: 8028015
Filing Date: 2011-09-27
Classification: G06F

Abstract:
1. A computer implemented method of operating a multiplication circuit to compute the product of two operands (hereby identified as A and B), at least one of which is wider than a width associated with the multiplication circuit, where operand A comprises one or more contiguous ordered word-wide operand segments characterized by weight j and identified as A j , where j is an integer from 0 to k and operand B comprises one or more contiguous ordered word-wide operand segments characterized by weight i and identified as B i , where i is an integer from 0 to m, and a word is a specified number of bits (n), and where the multiplication circuit executes a matrix of word-wide operand segment pair multiplication operations, the matrix comprising m+1 rows and k+m+2 columns, each row having a weight x where x is an integer from 0 to m and each column having a weight y where y is an integer from 0 to (k+m+1), the multiplication circuit having access to a memory, the method comprising: performing multiplication operations on a pair of rows at one time, where for each pair of rows a pair of B