Patent ID: 8339844
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: a number of metal layers having vias formed among and between them; a further metal layer overlying an uppermost metal layer of the number of metal layers; a via layer between the further metal layer and the uppermost metal layer, the via layer comprising one or more programmable vias between one or more segments of the uppermost metal layer and the further metal layer, said one or more programmable vias comprising at least one material having a changeable resistance, wherein the at least one material having a changeable resistance is configured to have its resistance changed by passing an electric signal through the at least one material and at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state.