Patent ID: 6277683
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method of fabricating a salicided CMOS device, and a non-salicided CMOS device, on a semiconductor substrate, comprising the steps of:forming a first gate structure, on an underlying gate insulator layer, on a first region of said semiconductor substrate, to be used for the salicided CMOS device, and forming a second gate structure, on said underlying gate insulator layer, on a second region of said semiconductor substrate, to be used for said non-salicided CMOS device;forming a first lightly doped source/drain region, in an area of said first region of said semiconductor substrate, not covered by said first gate structure, and forming a second lightly doped source/drain region, in an area of said second region of said semiconductor substrate, not covered by said second gate structure;depositing a silicon oxide layer;applying a first organic layer;performing a first anisotropic RIE procedure to create organic spacers, on the sides of said first gate structure, and on the sides of said second gate structure;forming heavily doped source/drain regions, in an area of said first region of said semiconductor substrate, and in an area of said second region of said semiconductor substrate, not covered by gate structures, or by said organic spacers;removing said organic spacers;depositing a silicon nitride layer via low pressure chemical vapor deposition procedures, at a temperature between about 800 to 900.degree. C.;applying a second organic layer;performing a second anisotropic RIE procedure, in said first region of said semiconductor substrate, to form a composite spacer on the sides of said first gate structure, with said composite spacer comprised of an overlying, organic shape, and an underlying, L shape, silicon nitride configuration;removing said second organic layer from the top surface of said silicon nitride layer, in said second region of said semiconductor substrate, and removing said organic shape, from the surface of said L shape, silicon nitride configuration;removing regions of said silicon oxide layer from the top surface of said first gate structure, and from the top surface of said heavily doped source/drain region, located in said first region of said semiconductor substrate;depositing a metal layer;performing an anneal procedure to form a metal silicide layer on the top surface of said first gate structure, and on the top surface of said heavily doped source/drain region located in said first region of said semiconductor substrate, while said metal layer, located on said L shaped, silicon nitride configuration, in said first region of said semiconductor substrate, and said metal layer, overlying said silicon nitride layer, in said second region of said semiconductor substrate, remains unreacted; andremoving unreacted metal from the top surface of said silicon nitride layer in said second region of said semiconductor substrate, resulting in said non-salicided CMOS device, and removing unreacted metal from the surface of said L shaped, silicon nitride configuration, in said first region of said semiconductor substrate, resulting in said salicided CMOS device.