Patent ID: 6831859
Filing Date: 2004-12-14
Classification: G11C

Abstract:
A non-volatile semiconductor memory having at least one floating gate comprising:a memory cell array including a plurality of electrically-rewritable non-volatile memory cells, provided with an initial data setting area, written in which is data initially set for deciding memory operation requirements, the memory cell array including a plurality of blocks, each block having a plurality of word lines, the memory cells being connected to the word lines; a block decoder configured to select a block corresponding to an address signal, a first switch connected in series with the block decoder, configured to activate or deactivate the block decoder, wherein the initial data setting area includes a memory section configured to store an address of a block to be set in an un-selectable state, and a setter provided in each block decoder configured to set the first switch in an off-state according to an address supplied by the memory section, the setter including a latch circuit to maintain the state of the first switch and latch the initially set data, a second switch connected to the first switch in parallel, that is configured to turn on when blocks that have been set in an un-selectable state are detected or selected without reference to the state of the first switch, a plurality of discharge circuits connected to an internal output signal of the block decoder and a node of the latch circuit in the setter, and supplied with an un-selectable block detection control signal, and a detector, which is connected to a common output signal line connected to the discharge circuits, configured to detect the blocks that have been set in the un-selectable state by detecting a voltage on the common output signal line while the block address is being scanned; a sense-amplifier configured to detect and amplify data stored in at least a memory cell selected by the block decoder; latch circuits provided in a peripheral circuit area configured to latch the initially set data; and a controller configured to control the sequence of data transfer from the initial data setting area to the latch circuits.