Patent ID: 7765382
Filing Date: 2010-07-27
Classification: G06F

Abstract:
1. A semiconductor device, comprising: a plurality of processing clusters that each operate synchronously internally and arranged in a M×N matrix, each processing cluster comprising a memory and a plurality of reconfigurable processing elements each formed as an arithmetic logic unit, multiplier, or multiplier/accumulation circuit and clocked buses interconnecting the memory and processing elements within each processing cluster and an asynchronous cluster wrapper as interface circuitry and operative with said processing elements and memory; asynchronous, bidirectional and self-synchronous global and inter cluster local buses interconnecting each asynchronous cluster wrapper through which data, addresses and programs are transferred with the memory and said processing elements; and an input/output circuit interconnecting global and inter cluster local buses and comprising a clocked Boolean logic self-synchronous wrapper circuit coupled to the asynchronous global buses through which address information, programs and data are carried and coupled to the inter cluster local buses through which data is carried and wherein said processing clusters, global and inter cluster local buses and input/output circuit are configured to operate together to propagate single word reconfiguration commands on wavefront array flows.