Patent ID: 9035275
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a conductive line having first and second sides; a plurality of levels of a plurality of conductive pads disposed adjacent the first and second sides of the conductive line, the plurality of conductive pads having proximal sides proximal to a corresponding one of the first and second sides of the conductive line; metal oxide memory elements on the proximal sides of the plurality of conductive pads in the plurality of levels, and in electrical communication with the corresponding ones of the first and second sides of the conductive lines; and an array of vertical connectors, the vertical connectors in electrical communication with respective conductive pads in the plurality of levels and overlying circuitry, wherein the plurality of conductive pads each include a metal layer between one of the metal oxide memory elements and one of the array of vertical connectors, wherein the metal oxide memory elements comprise an oxide of the metal layer, such that the metal oxide memory element is disposed along the proximal side of the metal layers in the conductive pads, and wherein the plurality of conductive pads further include a plurality of barrier metal layers in which the metal layer is disposed between at least two of the barrier metal layers.