Patent ID: 6297759
Filing Date: 2001-10-02
Classification: H03M

Abstract:
A digital-to-analog converter (DAC) for converting a digital input word into a corresponding analog output signal comprising:a capacitive digital-to-analog converter (CDAC) voltage reference source having a plurality of CDAC reference voltages;a CDAC segment including a plurality of CDAC switches, each CDAC switch having a plurality of CDAC switch states, in each of which CDAC switch states the respective CDAC switch connects a respective one of the reference voltages, through a respective CDAC unit output capacitor, to a DAC output;at least one resistive converter (RDAC) segment that includes:an RDAC voltage reference source comprising an equally spaced resistive divider providing a plurality of RDAC reference voltages;a first RDAC output bus;a second RDAC output bus;a first plurality of RDAC switches, each having a conductive state, in which it connects a respective one of the RDAC reference voltages to the first RDAC output bus, and a non-conductive state, in which it isolates the respective RDAC reference voltage from the first RDAC output bus;a second plurality of RDAC switches, each having a conductive state, in which it connects a respective one of the RDAC reference voltages to the second RDAC output bus, and a non-conductive state, in which it isolates the respective RDAC reference voltage from the first RDAC output bus;a bus selector arrangement having a first state, in which the first RDAC output bus is connected, via an RDAC output capacitor, to the DAC output, and a second state, in which the second RDAC output bus is connected, via the RDAC output capacitor, to the DAC output;a switch control arrangement having, as its input, a digital input word that includes a plurality of most significant bits (MSB's) and a plurality of remaining bits that include at least one next-most-significant-bit;the switch control arrangement including:a master clock signal having a predetermined clock cycle;a CDAC switch control portion including an MSB decoder converting the MSB's to corresponding CDAC state control signals according to a predetermined MSB conversion function, the CDAC state control signals being applied, via a CDAC control bus, to the CDAC switches, each state control signal thereby switching each CDAC switch to a corresponding one of the plurality of CDAC switch states;an RDAC switch control portion including an RDAC decoder arrangement converting the next-most-significant bits to corresponding RDAC state control signals according to a predetermined remaining bit conversion function, the RDAC state control signals being applied on alternate clock cycles:via a first RDAC control bus, to the first plurality of RDAC switches, each RDAC state control signal thereby setting each of the first plurality of RDAC switches to a corresponding one of its RDAC switch states; andvia a second RDAC control bus, to the second plurality of RDAC switches, each RDAC state control signal thereby setting each of the second plurality of RDAC switches to a corresponding one of its RDAC switch states; anda bus selection circuit generating bus selection control signals that are applied to the bus selector arrangement for switching the bus selector arrangement between the first and second states on alternate clock cycles and in synchronism with the application of the RDAC state control signals.