Patent ID: 9111854
Filing Date: 2015-08-18
Classification: G11C,H01L

Abstract:
1. A non-volatile memory comprising: a plurality of memory cells arranged in a matrix form; a plurality of first wiring lines each corresponding to memory cells of a common row; a plurality of second wiring lines and a plurality of third wiring lines, each of the plurality of second wiring lines corresponding to memory cells of a common column, each of the plurality of third wiring lines corresponding to memory cells of the common column; and a plurality of fourth wiring lines and fifth wiring lines, each of the plurality of fourth wiring lines and fifth wiring lines corresponding to the memory cells of one of the common row and the common column; each of the memory cells including a plurality of transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the transistors including a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor and the second transistor being connected in series with the first non-volatile element, the third transistor and the fourth transistor being connected in series with the second non-volatile element, the first node being disposed between the first transistor and the second transistor, the second node being disposed between the third transistor and the fourth transistor, gates of the first transistor and the third transistor being connected to one of the first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of the second wiring lines and the first node, the second transistor being connected between the first node and one of the fourth wiring lines, the third transistor being connected between one of the third wiring lines and the second node, the fourth transistor being connected between the second node and the one of the fifth wiring lines, the first non-volatile element being disposed between the one of the second wiring lines and the first transistor, between the first transistor and the first node, between the first node and the second transistor, or between the second transistor and the one of the fourth wiring lines, and the second non-volatile element being disposed at a location corresponding to a location of the first non-volatile element, between the one of the third wiring lines and the third transistor, between the third transistor and the second node, between the second node and the fourth transistor, or between the fourth transistor and the one of the fifth wiring lines.