Patent ID: 9129705
Filing Date: 2015-09-08
Classification: G11C

Abstract:
1. A semiconductor device comprising: an input clock generator suitable for generating an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal; and a data input unit suitable for receiving data and generating first input data in response to the first pulse of the input clock signal and suitable for receiving the data and generating second input data in response to the second pulse of the input clock signal, wherein the write latency signal is for setting a write latency period and the burst length signal is for setting a burst length period, and wherein the write latency period is a time period from when the write signal is received to when input the data and the burst length period is a time period successively input the data.