Patent ID: 6015745
Filing Date: 2000-01-18
Classification: H01L

Abstract:
A method for simplified processing of semiconductor devices having a semiconducting layer formed a top a layer of insulating semiconductor, said method comprising:defining one or more areas capable of forming electrically active semiconductor regions on said layer of insulating semiconductor;forming a shallow trench frame of electrically insulating material around a corresponding defined electrically active semiconductor region, each said shallow trench frame having insulating material connecting said layer of insulating semiconductor and dimensioned to electrically isolate each said electrically active semiconductor region of said semiconducting layer;forming one or more electrically conducting layers interconnecting different electrically active components in a first frame enclosed semiconductor region and a second frame enclosed semiconductor region, each said one or more electrically conducting layers formed on said semiconducting layer extending between said first and second frame regions; and,forming one or more shallow trenches of electrically insulating material in said semiconducting layer between said first and second frame regions, each said shallow trench having insulating material connecting said layer of insulating semiconductor and extending between said first frame and second frame to ensure electrical isolation of each said electrically conducting layers between said first and second frame regions, whereby a process for manufacturing said shallow trenches is simplified.