Patent ID: 6711534
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A method of analysing a circuit, the circuit having at least one structural loop between different channel connected components within the circuit, the method comprising the steps of:at least partly notionally splitting the circuit into its constituent channel connected components; detecting the at least one structural loop; inserting a pair of temporary boolean variables at a break point on a boundary between different channel connected components to notionally break the at least one structural loop; analysing each channel connected component in the at least one structural loop utilising the pair of temporary boolean variables at the break point in order to obtain a pair of boolean functions representing the functionality of the circuit at the break point; analysing the pair of boolean functions, including determining whether the at least one structural loop is sequential in nature; and modifying the pair of boolean functions when the at least one structural loop is sequential in nature in order to remove any dependence in the pair of boolean functions on the pair of boolean variables; wherein the step of analysing the pair of boolean functions comprises: reformulating each of the pair of boolean functions to have at least a first sub-function which is independent of both of the boolean variables, at least a second sub-function dependent on one of the boolean variables, and at least a third sub-function which is dependent on the inverse of said one of the boolean variables, wherein any of the sub-functions may be zero; and determining whether at least one of the second sub-functions is non-zero and all of the third sub-functions are zero, in which case the at least one structural loop is sequential in nature.