Patent ID: 6681235
Filing Date: 2004-01-20
Classification: G06F

Abstract:
A frequency synthesizer comprising:amplitude data output means for, when L-bit data is received, outputting amplitude data with a predetermined periodic function of a phase specified by the data; frequency setting means for setting frequency data of (K+Lâˆ’1) bits obtained by dividing a desired output frequency by a frequency of a predetermined clock signal; a K-bit counter for counting the clock signal; L-set product and sum computation circuits for subjecting frequency data of (K+Lâˆ’1) bits from the frequency setting means into L-set K-bit data in which a start bit is shifted by one bit each other, and computing a logical product between a count output of K bits from the counter and a unit of bits, thereby obtaining a total number of bits in which the calculation result is 1 by each set; and a shifting/adding circuit for adding each total number data obtained by the L-set product and sum computation circuits by shifting bits, and outputting the least significant L bits of the addition result to the amplitude data output means.