Patent ID: 6236115
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A stack of semiconductor chips comprising:a first chip;a second chip; anda first connection which electrically connects said first and second chips,wherein said first chip and said second chip each include:(a) a substrate;(b) a first hole in said substrate;(c) a first metallization layer disposed along an interior surface of said first hole, said first metallization layer being the only metallization layer formed within said first hole; and(d) an interconnect layer disposed on a surface of said substrate adjacent said first hole, said interconnect layer being attached to said first metallization layer in said first hole, said first connection contacting the interconnect layer on said first chip to the interconnect layer on said second chip to establish electrical connection between said first and second chips,wherein said stack further comprises:a second connection for electrically connecting said first chip and said second chip, andwherein said first chip and said second chip each include:another metallization layer disposed in spaced relation to said first metallization layer along a location at a surface of said substrate where a hole is not located, said second connection contacting the another metallization layer of said first chip and the another metallization layer of said second chip to form a pad-to-pad electrical connection between said first and second chips.