Patent ID: 6168977
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising: providing a silicon substrate; forming a fuse conductive pattern on the silicon substrate; forming a first insulation layer on the fuse conductive pattern and the silicon substrate, the first insulation layer having a first etching speed; forming a stopper pattern on a first region of the first insulation layer to cover the fuse conductive pattern, the stopper pattern having a second etching speed; forming a second insulation layer on the stopper pattern and the first insulation layer, the second insulation layer having a third etching speed; etching a second region of the second insulation layer to form an opening, wherein the second region is within the first region and an etching condition is set such that the third etching speed is higher than the second etching speed so that the stopper pattern is exposed at a bottom of the opening; and etching the exposed stopper pattern with an etching condition set such that the second etching speed is faster than the third etching speed so that the exposed stopper pattern is removed and the first insulation layer remains on the fuse conductive pattern.