Patent ID: 8634503
Filing Date: 2014-01-21
Classification: H03L,H04L

Abstract:
1. A clock-data recovery system, comprising: phase alignment circuitry generating an output clock signal in response to an incoming data signal and a feedback clock signal; clock generator circuitry generating a plurality of base phase clock signals in response to the output clock signal, each base phase clock signal of the plurality of base phase clock signals differing in at least one of phase and polarity from all other base phase clock signals of the plurality of base phase clock signals and having a frequency the same as the frequency of all other base phase clock signals of the plurality of base phase clock signals; time-to-digital converter circuitry generating the feedback clock signal in response to the incoming data signal and the plurality of base phase clock signals and in response to assertion of a re-lock signal indicating a large change in phase between the incoming data signal and the output clock signal, the time-to-digital converter circuitry basing the feedback clock signal on one of the plurality of base phase clock signals aligned more closely in phase with the incoming data signal than others of the plurality of base phase clock signals; and sampling circuitry generating a recovered data signal in response to at least one of the plurality of base phase clock signals.