Patent ID: 8441851
Filing Date: 2013-05-14
Classification: G11C

Abstract:
1. A semiconductor storage circuit, comprising: a plurality of word lines disposed in a row direction; a plurality of sub-bit lines disposed in a column direction, the plurality of sub-bit lines intersecting the plurality of word lines; a plurality of main bit lines each provided for a group of adjacent sub-bit lines; a plurality of non-volatile memory cells, each provided at an intersecting portion of the word lines and the sub-bit lines and including a control electrode connected to the word line of the intersecting portion, a first electrode connected to the sub-bit line of the intersecting portion, and a second electrode connected to a sub-bit line adjacent to the sub-bit line connected to the first electrode, wherein one bit of information is read from each of the first electrode and the second electrode of the non-volatile memory cell, by changing a direction of a voltage applied between the first and second electrodes when the non-volatile memory cell is selected by the word line; a plurality of drain selectors that are provided between one end of the sub-bit lines and a common power supply, and that connects the sub-bit lines, that are connected to a non-selection-side electrode of the first and second electrodes of the two memory cells of read objects, to the common power supply, in a case in which drain selection signals corresponding to two memory cells are supplied; a plurality of source selectors, that are provided between the other ends of the sub-bit lines and the main bit lines, and that connects the sub-bit lines, that are connected to the selection-side electrode of the first and second electrodes of the two memory cells, to two adjacent main bit lines, in a case which source selection signals corresponding to the two memory cells are supplied; a first sense amplifier that reads data of one of the two memory cells; a second sense amplifier that reads data of the other of the two memory cells; and a connecting section that connects a main bit line connected to an even-numbered memory cell in a row direction in the two memory cells of the read objects to the first sense amplifier, and that connects a main bit line connected to an odd-numbered memory cell in the row direction in the two memory cells to the second sense amplifier, wherein the connecting section includes: