Patent ID: 6177304
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:forming isolation areas on a semiconductor substrate surrounding and electrically isolating device areas;providing a gate oxide layer overlying said semiconductor substrate in said device areas;depositing a first polysilicon layer overlying said gate oxide layer and said isolation areas;patterning said first polysilicon layer to form gate electrodes;implanting first ions to form lightly doped source and drain regions within said semiconductor substrate associated with said gate electrodes;forming silicon nitride spacers on the sidewalls of said gate electrodes;implanting second ions to form heavily doped source and drain regions within said semiconductor substrate associated with said gate electrodes;depositing a poly-cap layer overlying said substrate including said gate electrodes and source and drain regions;selectively removing said poly-cap layer overlying one of said source and drain regions where a self-aligned contact is to be formed, and overlying another of said source and drain regions and a portion of its associated gate electrode where a butted contact is to be formed;thereafter depositing an insulating layer over the surface of said semiconductor substrate;simultaneously etching said planned self-aligned contact opening and said planned butted contact opening through said insulating layer; andfilling said self-aligned contact opening and said butted contact opening with a conducting layer to complete the fabrication of said integrated circuit device.