Patent ID: 7006161
Filing Date: 2006-02-28
Classification: G06F,H04N

Abstract:
1. A circuit configuration, comprising: a bus coupled to a first power supply; a first integrated circuit coupled to the bus, the first integrated circuit recognizing a first predetermined voltage level as logic HIGH level; a second integrated circuit coupled to the bus, the second integrated circuit recognizing the first predetermined voltage level as logic HIGH level; and a third integrated circuit coupled to the bus, wherein the third integrated circuit recognizes a second predetermined voltage, which differs from the first predetermined voltage level, as logic HIGH level, the third integrated circuit being coupled to the bus via an interface circuit that performs bi-directional level shifting to allow interoperability of the third integrated circuit with the first and second integrated circuits, the third integrated circuit and the interface circuit each being coupled to first and second RUN power supplies, respectively, and wherein upon a fault condition that results in a loss of the RUN power supplies, the loading placed on the bus by the interface circuit and the third integrated circuit is controlled to a level that enables the first integrated circuit and the second integrated circuit to continue to communicate with each other via the bus.