Patent ID: 8964447
Filing Date: 2015-02-24
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a cell array including plural MATs (unit cell arrays) arranged in a matrix, each MAT including a plurality of first lines, a plurality of second lines intersecting said plurality of first lines, and a plurality of memory cells connected at intersections of said first and second lines between both lines, each memory cell including a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; a plurality of access circuits independently connected to said MATs, respectively; and IO pads each provided at Nm1 said MATs (Nm1=an integer of 1 or more), wherein said access circuits are configured to execute data input/output to/from said Nm1 MATs from/to said IO pads, each of Nm access circuits (Nm=an integer of 2 or more) of said plurality of access circuits accesses Nc memory cells (Nc=an integer of 1 or more) of said plurality of memory cells in corresponding MATs, simultaneously, and each of said access circuits includes a latch circuit operative to store information whether said MAT is failed or not.