Patent ID: 6136638
Filing Date: 2000-10-24
Classification: G11C,H01L

Abstract:
A method of forming an application specific integrated circuit containing an array of embedded DRAM cells and a logic core on a semiconductor substrate of a first conductivity type, comprising the steps of:implanting a material of a second conductivity type into the surface of the semiconductor substrate to a lightly doped concentration to form primary wells;implanting the material of the first conductivity type into the surface of the semiconductor substrate to a lightly doped concentration to form secondary wells within the primary wells in locations of said application specific integrated circuit containing the array of embedded DRAM cells;implanting the material of the second conductivity type into the surface of the semiconductor substrate to a highly doped concentration to form sources and drains of transistors of a first channel type including a pass transistor of each embedded DRAM cell;implanting the material of the first conductivity type to a highly doped concentration to form sources and drains of transistors of a second channel type;forming a cell capacitor for each embedded DRAM cell;forming a gate oxide over the channel area between the source and drain of transistors of logic circuits within the logic core;forming a gate oxide over the channel area between the source and drains of transistors of peripheral circuits within the logic core;forming a gate oxide over a channel area between the source and drain of each pass transistor of each embedded DRAM cell whereby a thickness of the gate oxide of the pass transistor of each embedded DRAM cell is equal to the thickness of the transistors of the logic core;forming gate electrodes on the gate oxide of the pass transistors and the transistors of the logic core;connecting a plurality of word line voltage generators to rows of pass transistors within the array of embedded DRAM cells; andconnecting a plurality of bit line voltage generators to columns of pass transistors within the array of embedded DRAM cells.