Patent ID: 6243805
Filing Date: 2001-06-05
Classification: G06F

Abstract:
A microprocessor configured to fetch and execute program instructions stored in memory, comprising:a fetch and predecode stage for fetching instructions from memory at memory addresses specified by a program counter, wherein the instructions received by the fetch and predecode stage include conditional branch instructions and conditional branch calculation instructions, and wherein the fetch and predecode stage is configured to predecode the instructions to detect the conditional branch instructions;a decode stage coupled to the fetch and predecode stage, wherein the decode stage is configured to decode conditional branch calculation instructions fetched by the fetch and predecode stage;an execution stage coupled to the decode stage, wherein the execution stage is configured to execute conditional branch calculation instructions decoded by the decode stage;a branch target circuit coupled to the fetch and predecode stage, wherein the branch target circuit includes a branch FIFO buffer, wherein the branch FIFO buffer is configured to receive and store execution results of executing decoded conditional branch calculation instructions;wherein the fetch and predecode stage is configured to read an execution result from the branch FIFO buffer in response to the fetch and predecode stage predecoding a conditional branch instruction, and;wherein the fetch and predecode stage is configured to dispatch a target address to the program counter in response to the fetch and predecode stage reading the execution result from the branch FIFO buffer.