Patent ID: 6355927
Filing Date: 2002-03-12
Classification: G01D,H03M

Abstract:
An interpolation circuit comprising:a signal generating circuit responsive to input ramp signals that are one quarter cycle out of phase for generating A, Aâ€², B, Bâ€², one or more fractional A or Aâ€² and one or more fractional B or Bâ€² ramp signals; a comparator circuit for comparing selected pairs of said A, Aâ€², B, Bâ€², one or more fractional A or Aâ€² and one or more fractional B or Bâ€² ramp signals and generating intermediate signals; and a logic circuit for combining said intermediate signals and providing first and second output signals each having multiple cycles per cycle of the ramp signals, said first and second output signals being phase shifted relative to each other.