Patent ID: 6777306
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A method of forming a pair of memory cells:forming a first insulative layer on a substrate; patterning the first insulative layer to define future first source/drain regions; forming a pair of first source/drain regions in the substrate; forming a first storage node coupled to a first one of the pair of first source/drain regions and forming an extension coupled to a second one of the pair of first source/drain regions; wherein the extension is isolated from the first storage node; forming a first cell dielectric layer overlying the first storage node and the extension; forming a first cell plate layer overlying the first cell dielectric layer; forming a second insulative layer overlying the first cell plate layer; exposing a portion of the extension; forming a second storage node coupled to the exposed portion of the extension and isolated from the first storage node and the first cell plate layer; forming a second cell dielectric layer overlying the second storage node; forming a second cell plate layer overlying the second cell dielectric layer; forming a third insulative layer overlying the second cell plate layer; cleaving the substrate, thereby exposing a surface of the substrate; planarizing the exposed surface of the substrate to expose the first source/drain regions; forming a first word line overlying at least a portion of the first one of the pair of first source/drain regions; forming a second word line overlying at least a portion of the second one of the pair of first source/drain regions; and forming a second source/drain region in the substrate interposed between the first word line and the second word line.