Patent ID: 7768330
Filing Date: 2010-08-03
Classification: H03K,H03M

Abstract:
1. A logic circuit comprising: a data acquisition part including a transistor pair, the transistor pair operating differentially, the data acquisition part, when a clock signal is a first level, acquiring a data input signal inputted into the transistor pair, and amplifying the acquired data using a first gain and outputting the amplified data to a data output node; a latch part that latches the data outputted to the data output node when the clock signal is a second level; a gain control part provided between the a first common node of a first transistor, the first transistor being one of transistors forming the transistor pair, and a second common node of a second transistor, the second transistor being the other of the transistors forming the transistor pair, the gain control part making the first gain in a high frequency band higher than the first gain in a low frequency band; and a common node control part coupled to the first and second common nodes, the common node control part, when the clock signal is a second level, performing control such that a potential difference between the first and second common nodes is eliminated by providing or drawing electric charge to or from the first and second common nodes.