Patent ID: 7904640
Filing Date: 2011-03-08
Classification: G06F

Abstract:
1. A memory system comprising: a first storing area as a cache memory included in a volatile semiconductor memory; second and third storing areas included in nonvolatile semiconductor memories in which data reading and writing is performed by a page unit and data erasing is performed by a block unit twice or larger natural number times as large as the page unit; a first input buffer included in the nonvolatile semiconductor memories and configured to perform buffering between the first storing area and the second storing area; a second input buffer included in the nonvolatile semiconductor memories and configured to perform buffering between the first storing area and the third storing area; and a controller that allocates storage areas of the nonvolatile semiconductor memories to the second and third storing areas and the first and second input buffers by a logical block unit associated with one or more blocks, wherein the controller executes: