Patent ID: 8076772
Filing Date: 2011-12-13
Classification: H01L,H05K

Abstract:
1. A memory module comprising: a printed circuit board comprising an interconnection substrate in which a plurality of signal lines are arranged, a heat sink disposed adjacent to a first surface of the interconnection substrate and in which no signal lines are arranged, and a bending substrate coupling the interconnection substrate to the heat sink; a plurality of semiconductor packages mounted on the first surface of the interconnection substrate opposite to the heat sink, the semiconductor packages being electrically coupled to the signal lines; and a thermal interface adhesive configured to adhere the semiconductor packages to a first surface of the heat sink opposite to the semiconductor packages, and configured to transmit heat from the semiconductor packages to the heat sink, wherein the interconnection substrate has a first end portion and a second end portion opposite the first end portion of the interconnection substrate, the heat sink has a first end portion and a second end portion opposite the first end portion of the heat sink, and the bending substrate couples the first end portion of the interconnection substrate to the first end portion of the heat sink, wherein the interconnection substrate comprises a first interconnection substrate, wherein the signal lines comprise first signal lines, wherein the bending substrate comprises a first bending substrate, the printed circuit board further comprises a second interconnection substrate disposed adjacent to a second surface of the heat sink opposite to the first surface of the heat sink and having a plurality of second signal lines arranged therein, and a second bending substrate coupling the second interconnection substrate to the first interconnection substrate and formed of a flexible material, the first bending substrate couples a first end portion of the first interconnection substrate to a first end portion of the heat sink, the second bending substrate couples a second end portion of the first interconnection substrate to an end portion of the second interconnection substrate, and the second end portion of the first interconnection substrate is opposite to the first end portion of the first interconnection substrate.