Patent ID: 7376819
Filing Date: 2008-05-20
Classification: G06F

Abstract:
1. A data processor, comprising: an instruction executing unit including an instruction controller and that outputs an address signal; a bus controller that inputs said address signal, and that outputs a bus mode control signal based on one of an internal memory area and an external memory area indicated by said address signal, wherein said bus mode control signal indicates an M bits instruction mode or an N bits instruction mode, wherein a size of said N bits is twice a size of said M bits, wherein said bus mode control signal is changed to said M bits instruction mode when said instruction controller decodes a branch instruction for branching to an address indicating said external memory, wherein said instruction executing unit receives said bus mode control signal, wherein said instruction controller generates a bus control signal, wherein said bus controller receives said bus control signal and said address signal, and controls bus access based on said bus control signal and said address signal, wherein said instruction executing unit is operable to access data in said external memory, said data having a word length of M bits, wherein said instruction controller outputs said bus control signal indicating a M bits instruction fetch mode when said bus mode control signal is said M bits instruction mode.