Patent ID: 7012443
Filing Date: 2006-03-14
Classification: G01R

Abstract:
1. A system which tests a plurality of devices in parallel, the system comprising: a plurality of devices under test, said devices arranged in rows and columns; a plurality of input/output signal channels connected in common to input/output signal pins of the devices under test, all input/output signal pins of devices in each row being connect to the same input/output signal channel, a plurality of chip selection signal channels which provide chip selection signals to the devices under test to specify one output data among output data to be output through the commonly connected input/output signal channels, each chip selection signal channel being connected to all the devices under test in one column; a DC channel connected in common with an inverted clock signal pin and a reference voltage pin of the devices under test; and test equipment which tests the devices under test through the input/output signal channels and the chip selection signal channels.