Patent ID: 6216217
Filing Date: 2001-04-10
Classification: G06F

Abstract:
A data processor, comprising:a CPU capable of performing wait operations by setting wait instructions and wait cancel instructions based on program instructions retrieved by the CPU;a plurality of accessible devices such as a memory and input/output devices which are accessible by said CPU;a wait/wait cancel instruction setting register to which said CPU sets a wait instruction and a wait cancel instruction as programmed by said retrieved program instructions, which place said CPU into sequential program states; anda wait controller for outputting to said CPU a wait signal for a wait operation for permitting wait-based access to all of said accessible devices starting from the next program state after a wait instruction is set in said wait/wait cancel instruction setting register by the CPU, said wait controller further outputting to said CPU a wait signal for canceling the wait operation on all of said accessible devices starting from the next program state after a wait cancel instruction is set in said wait/wait cancel instruction setting register by the CPU.