Patent ID: 6487698
Filing Date: 2002-11-26
Classification: G06F

Abstract:
A process of transforming a program language description of an integrated circuit into an RTL description of the integrated circuit, the program language description functionally describing the integrated circuit in terms of inputs and outputs, the process comprising steps of:a) defining the integrated circuit as a generalized multiplexer having two groups of input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn, and a plurality of outputs Z such that no output depends on more than one variable of the group consisting of Y1, Y2, . . . , Yn; b) fixing each variable X1, X2, . . . , Xs, as X1=a1, X2=a2, . . . , Xs=as, where a1, a2, . . . , as are fixed terms; c) constructing an output vector UU as a function of the input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn and the plurality of outputs Z; d) if output vector UU has two different bits, constructing a vector UU1 as (BIT(0,j), BIT(1,j), . . . , BIT(Kâˆ’1,j)), where K is based on the number of Y input terms; and e) if an index j exists in vector UU1, constructing an RTL description of the integrated circuit as either F(a1, atâˆ’1, 0, Xt+1 . . . , Xs, Y1, Y2, . . . , Yn)(Xt) ORF(a1, atâˆ’1,1, Xt+1 . . . , Xs, Y1, Y2, . . . , Yn)(Xt).