Patent ID: 6492216
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method of fabricating a semiconductor device incorporated with a strained channel, on a semiconductor substrate, comprising the steps of:forming a semiconductor alloy layer on said semiconductor substrate, wherein said semiconductor alloy layer is comprised with a first element, a second element, and a third element; forming a gate insulator layer overlying said semiconductor alloy layer; forming a gate structure on said gate insulator layer forming insulator spacers on sides of said gate structure; forming source/drain regions in area of said semiconductor alloy layer and in an area of said semiconductor substrate not covered by said gate structure or by said insulator spacers; removing portions of said semiconductor alloy not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain region; and forming metal silicide regions on said portions of said semiconductor substrate comprised with said source/drain region.