Patent ID: 8367495
Filing Date: 2013-02-05
Classification: H01L

Abstract:
1. A method, comprising: forming a first gate electrode structure above a first semiconductor region of a semiconductor device and a second gate electrode structure above a second semiconductor region, said first and second gate electrode structures comprising a gate insulation layer including a high-k dielectric material, a metal-containing electrode material and a placeholder material, said first gate electrode structure further comprising an intermediate etch stop liner positioned between said metal-containing electrode material and at least a portion of said placeholder material; removing material of said placeholder material in said first and second gate electrode structures to expose one of said metal-containing electrode material and said gate insulation layer in said second gate electrode structure and expose said etch stop liner in said first gate electrode structure; adjusting a work function in said second gate electrode structure; removing said etch stop liner in said first gate electrode structure; and forming a metal-containing material in said first and second gate electrode structures.