Patent ID: 6628243
Filing Date: 2003-09-30
Classification: G06F,G09G

Abstract:
An apparatus comprising:input-interface circuitry that receives data signals representing a plurality of independent images and associated control signals; memory; memory controller in communication with the input-interface circuitry and the memory to control writing information into and reading information from the memory, wherein the information corresponds to the data signals representing the plurality of independent images; one or more display-pipeline circuits in communication with the memory to receive the information representing the plurality of independent images; and output terminals in communication with the one or more display-pipeline circuits, wherein the output terminals provide a first clock signal and a plurality of output-data signals conveying interleaved components of the plurality of independent images, wherein each component represents a portion of a respective image that is narrower than the respective image, and wherein the output-data signals conveying components for a first of the plurality of independent images are aligned with the first clock signal.