Patent ID: 7404069
Filing Date: 2008-07-22
Classification: G06F

Abstract:
1. A device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of an expanded type, said device comprising: means for receiving a first signal representative of an actually executed instruction; means for receiving a second signal representative of an expanded instruction; means for receiving a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by said microcontroller, microprocessor or data processing unit; means for storing consecutive addresses pointed to by a program counter; means including a state machine for processing said first, second and third signals in order to determine a pair that includes a source address and a destination address for an address branch, when appropriate; and storage means for storing said address pair, wherein said means for storing consecutive addresses pointed to by said program counter includes: