Patent ID: 6265253
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises the sequential steps of:forming first and second conductive gates on a main surface of a semiconductor substrate with a gate dielectric layer therebetween;forming sidewall spacers on side surfaces of the gates and extending onto first portions of the main surface;forming aluminum disposable spacers on the sidewall spacers and extending onto second portions of the main surface onto which the sidewall spacers do not extend;forming a first mask on the first gate and extending onto a third portion of the main surface;ion implanting impurities, using the second gate, sidewall spacers and aluminum disposable spacers thereon as a mask, to form first moderate or heavy source/drain implants;removing the aluminum disposable spacers from the sidewall spacers of the second gate while leaving the first mask in place;ion implanting impurities, using the second gate and sidewall spacers thereon as a mask, to form first lightly or moderately doped source/drain extension implants;removing the first mask;forming a second mask on the second gate and extending onto a fourth portion of the main surface;ion implanting impurities, using the first gate, sidewall spacers and aluminum disposable spacers thereon as a mask, to form second moderate or heavy source/drain implants;removing the aluminum disposable spacers on the sidewall spacers of the first gate while leaving the second mask in place; andion implanting impurities, using the first gate and sidewall spacers thereon as a mask, to form second lightly or moderately doped source/drain extension implants;wherein the sidewall spacers remain as masks to substantially prevent the implantation of impurities into the first portions of the main surface.