Patent ID: 6226771
Filing Date: 2001-05-01
Classification: H03M,H04L

Abstract:
An error detection generator for calculating two or more error detection values or insertion into an encapsulated frame having a plurality of fields, the error detection generator comprising:a first, a second and a third cyclic redundancy check (CRC) engine each configured to receive the encapsulated frame and having means for calculating an error detection value;an output multiplexer configured to receive the encapsulated frame and coupled to each of the CRC engines for inserting the calculated error detection values into respective fields of the encapsulated frame; anda controller operably coupled to the CRC engines and the output multiplexer, the controller selectively enabling and disabling the CRC engines to calculate corresponding error detection values based on different fields of the encapsulated frame and setting the output multiplexer to insert the calculated error detection values into the respective fields of the encapsulated frame.