Patent ID: 6134652
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A single chip integrated circuit device comprising:an on chip CPU comprising fetch and execute circuitry for fetching and executing instructions from a memory, and an instruction pointer register for holding an address in memory of a next instruction to be executed,a bus connected to the CPU for permitting the CPU to access said memory;an on-chip breakpoint unit connected to receive each said address from the instruction pointer register via an address communication path and having a breakpoint register for holding a breakpoint address at which the normal operation of the CPU is to be interrupted for diagnostic purposes, the on-chip breakpoint unit further having a comparator circuit operative to compare the breakpoint address with each said address from the instruction pointer register and to issue a breakpoint signal on a breakpoint signal path when there is a match;on-chip control logic connected to the breakpoint signal path and arranged to interrupt the normal operation of the CPU when the breakpoint signal is received,wherein the on-chip breakpoint unit comprises circuitry for inhibiting generation of the breakpoint signal for said next instruction on resumption of normal operation of the CPU after it has been interrupted.