Patent ID: 8085176
Filing Date: 2011-12-27
Classification: H03M

Abstract:
1. An apparatus for reduction of unwanted idle tones by dithering a digital signal in a multi-bit (M-bit, M>1) sigma-delta digital-to-analog converter (DAC), comprising: a sigma-delta multi-bit modulator having a digital signal input and a variable resolution output, the sigma-delta multi-bit modulator comprising: a digital loop filter, a random sequence generator, and variable resolution quantizer, wherein the digital loop filter receives a digital signal at the digital signal input and converts the digital signal to L-bit digital words, the random sequence generator creates a plurality of random numbers N(n) in a sequence, where N(n) are random integer numbers between 1 and M, and the variable resolution quantizer reduces the L-bit digital words to N(n)-bit digital words and then adds zeros to the N(n)-bit digital words to form M-bit digital words, where M is greater than N(n) and M−N(n) least significant bits of the M-bit digital words are zeros; a multi-bit digital-to-analog converter (DAC) having an analog output and a digital input coupled to the variable resolution output from the sigma-delta multi-bit modulator; and an analog low pass filter having an analog input coupled to the analog output of the multi-bit DAC.