Patent ID: 8217435
Filing Date: 2012-07-10
Classification: H01L,Y10S

Abstract:
1. A memory device comprising: a linear semiconductor fin disposed on a substrate, the linear semiconductor fin having a top surface and a longest direction; a first gate structure disposed on one side of the linear semiconductor fin, the first gate structure having a top surface and a longest direction, the top surface of the first gate structure above the top surface of the linear semiconductor fin with respect to the substrate, and the longest direction of the first gate structure orthogonal to the longest direction of the semiconductor fin; a second gate structure disposed on an opposite side of the linear semiconductor fin, the second gate structure having a top surface and a longest direction, the top surface of the second gate structure above the top surface of the linear semiconductor fin with respect to the substrate, and the longest direction of the second gate structure orthogonal to the longest direction of the semiconductor fin and parallel with the longest direction of the first gate structure; and one of the first or second structures having a more favorable characteristic for retaining charge in the linear semiconductor fin than the other of the gate structures, wherein the first gate structure has a gate dielectric comprising a first dielectric layer and a second, different, dielectric layer, and the second gate structure has a gate dielectric comprising the second dielectric layer but not the first dielectric layer.