Patent ID: 8166218
Filing Date: 2012-04-24
Classification: G06F,G11C

Abstract:
1. An integrated circuit comprising: a serial input/output interface with one or more lanes, each of the one or more lanes including a first parallel-in-serial-output (PISO) shift register having a parallel input coupled to a local data bus, a clock input coupled to a first clock signal, a load/shift-bar input coupled to a load signal, the first PISO shift register to serialize parallel data on the local data bus into serialized local data on a first serial output; a first multiplexer having a first data input coupled to the first serial output, a second data input to receive feed-through data, a select input coupled to a local data select signal, the first multiplexer to merge the serialized local data and the feed-through data into a serial data stream on a multiplexed output responsive to the local data select signal; and a transmitter having an input coupled to the multiplexed output to receive the serial data stream, the transmitter to drive the serial data stream onto a serial data link, wherein each of the one or more lanes further includes a bus multiplexer coupled between the local data bus and the first PISO shift register, the bus multiplexer having a first data input, coupled to the one half of the bits of the local data bus, a second data input coupled to the another half of the bits of the local data bus, a multiplexed output coupled to the parallel input of the first PISO shift register, and a select input coupled to a data bus select signal, the bus multiplexer to couple the one half of the bits of the local data bus or the another half of the bits of the local data bus into the parallel input of the first PISO shift register in response to the data bus select signal, wherein each of the one or more lanes further includes control logic coupled to the first multiplexer and the first PISO shift register, the control logic to receive the first clock signal, a mode select signal, and a merge enable signal, the control logic to generate the local data select signal to merge the serialized local data and the feed-through data into the serial data stream in response to the merge enable signal and the first clock signal, the control logic to further generate the data bus select signal in response to the mode select signal, wherein the load signal is an early load pulse signal that is coupled into the load/shift-bar input of a second PISO shift register having a serial output coupled to a serial input of the first PISO shift register.