Patent ID: 6107129
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method for forming an integrated circuit, comprising:patterning a gate conductor upon a dielectric covered semiconductor substrate, said gate conductor having opposing sidewall surfaces;using the gate conductor as a mask, implanting a first lightly doped drain (LDD) implant species into a first LDD area within the semiconductor substrate;using the gate conductor as a mask, implanting a second LDD implant species into a second LDD area at a greater concentration and at a shallower depth than the first LDD implant species;subsequently forming a spacer upon each of the opposing sidewall surfaces;using the gate conductor and the spacer as a mask, implanting a first source/drain implant species into a first source/drain area laterally spaced from a sidewall surface of the gate conductor and within the semiconductor substrate; andusing the gate conductor and the spacer as a mask, implanting a second source/drain implant species into a second source/drain area laterally spaced from the sidewall surface of the gate conductor at a greater concentration and at a shallower depth than the first source/drain implant species.