Patent ID: 8050376
Filing Date: 2011-11-01
Classification: H03L

Abstract:
1. An All Digital Phase Locked Loop (r46ADPLL), comprising: a first frequency divider dividing a first frequency of a first feedback signal (CKOUT) by a natural number M to generate a first output signal; a phase-frequency detector (PFD) generating a decrement signal and an increment signal based on a phase difference and a frequency difference between a first reference clock (CKIN) signal and the first output signal; a control unit receiving the decrement signal, the increment signal, the natural number M and a second reference clock signal to generate a plurality of digital control signals, wherein the frequencies of the first and the second reference clock signals are identical; a digital controlled oscillator (DCO) generating a clock signal (CKDCO) having a second frequency based upon the digital control signals; and a second frequency divider receiving the digital control signals and the clock signal (CKDCO), and dividing the second frequency of the clock signal by a bit number of the digital control signals to generate the first feedback signal (CKOUT) to the first frequency divider.