Patent ID: 6593815
Filing Date: 2003-07-15
Classification: H03L

Abstract:
A full digital phase locked loop comprising:a first counter for continuously counting pulses of a first clock pulse stream and producing a varying count number of the counted pulses; a second counter for counting pulses of a second clock pulse stream and producing a reference signal when a predetermined number of the pulses is counted; summation circuitry having a plurality of augend input terminals for receiving said varying count number from said first counter, a plurality of addend input terminals and a plurality of output terminals, one of the output terminals producing a comparison signal; an exclusive-OR gate for detecting an interval between said comparison signal and said reference signal; resettable counter circuitry for counting pulses of said second pulse stream during said detected interval and producing a count number of the counted pulses and resetting the count number at periodic intervals; and differentiation circuitry for differentiating count numbers from said resettable counter circuitry and producing a differentiated count number and supplying the differentiated count number to said plurality of addend input terminals of the summation circuitry, whereby an output clock pulse stream of desired frequency can be obtained at one of the output terminals of said summation circuitry.