Patent ID: 8958517
Filing Date: 2015-02-17
Classification: H04L

Abstract:
1. A clock-adjustment circuit, comprising: a first clock signal associated with a first clock domain; a second clock signal associated with a second clock domain; a phase-detection circuit configured to receive the first clock signal and the second clock and to determine a phase relationship between the first clock signal and the second clock signal; and a phase-adjustment circuit configured to adjust a phase of the first clock signal relative to the second clock signal when the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that stores data which is being transferred from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer, wherein the FIFO buffer comprises at least two flip-flops, wherein at least one flip-flop is clocked by the adjusted first clock signal and at least one flip-flop is clocked by the second clock signal.