Patent ID: 6535441
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A static semiconductor memory device comprising:a plurality of static memory cells provided between a first node and a second node; a control terminal for receiving a control signal; a test mode signal generating configured for circuit generating an activated test mode signal when a voltage level of said control signal is equal to or higher than a predetermined level and generating an inactivated test mode signal when said voltage level is lower than said predetermined level; and a voltage setting circuit configured for setting a voltage between said first and second nodes to a level of a test voltage in response to said activated test mode signal and setting a voltage between said first and second nodes to a level of an external source voltage in response to said inactivated test mode signal, said external source voltage being supplied from outside said plurality of static memory cells, wherein said test voltage lies in a range from 0V to a threshold voltage of a MOS transistor as a component of said memory cell.