Patent ID: 9094047
Filing Date: 2015-07-28
Classification: G06F,G11C,H03M

Abstract:
1. A controller for a memory that includes a plurality of multi-bit cells for storing a plurality of data bits and a plurality of parity bits that correspond to the data bits, the controller being operative: (a) to read the cells, thereby obtaining a plurality of read bits; and (b) to correct said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is performed at least in part by decoding said read bits, said decoding using, as initial reliability estimates for at least two of said read bits, a priori estimates of respective probabilities that said at least two read bits are erroneous, wherein said a priori estimates are independent of values of said read bits, and wherein the a priori estimates associated with the at least two read bits are determined based at least in part on a position of respective significances of said at least two read bits relative to a voltage state distribution of respective multi-bit cells storing said read bits, wherein at least one said probability is different from at least one other said probability, and wherein the at least one said probability and the at least one other said probability are associated with different read bits.