Patent ID: 6136717
Filing Date: 2000-10-24
Classification: H01L,Y10S

Abstract:
A method for producing a via hole to a doped region in a semiconductor device, comprising the steps of:providing a substrate;generating in the substrate a doped region that is laterally limited by insulating regions, which insulating regions are positioned at least on a surface of the substrate;depositing an undoped, amorphous silicon layer surface-wide on the substrate;producing a doped region in the amorphous silicon layer that overlies the doped region in the substrate by masked implantation of boron;selectively removing undoped amorphous silicon in the amorphous silicon layer relative to the doped region in the amorphous silicon layer by wet chemical etching with potassium hydroxide solution;producing an insulating layer surface-wide on the substrate; andforming the via hole in the insulating layer by selectively anisotropically etching the insulating layer to remove a portion thereof that overlies the doped region in the amorphous silicon layer, while employing the doped region in the amorphous silicon layer as an etching stop in the formation of the via hole,wherein the doped region of the amorphous silicon layer is formed to have a boron concentration between 10.sup.18 cm.sup.-3 and 10.sup.20 cm.sup.-3.