Patent ID: 6184073
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A process for forming a semiconductor device comprising the steps of:forming a first conductive layer over a primary surface of a substrate;forming a first insulating layer over the first conductive layer;patterning the first conductive layer and the first insulating layer, wherein:this step forms a first conductive member over a first portion of the substrate,from a top view, the first conductive member has a shape; andfrom a top view, the first insulating layer has a shape that is substantially similar to the shape of the first conductive member;forming a first doped region and a second doped region within the substrate near its primary surface, wherein from a top view, the first conductive member lies between the first doped region and the second doped region; andforming a first interconnect that electrically connects the first doped region to the second doped region, wherein the first interconnect:extends over the first conductive member and the first insulating layer; andis electrically insulated from the first conductive member in a vertical direction by the first insulating layer.