Patent ID: 6389516
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A computer system comprising:a first multiprocessor system connected to a system bus and adapted to forward first and second load requests to the system bus, wherein the first load request precedes the second load request; a second multiprocessor system connected to the system bus, the second multiprocessor system including: a memory subsystem comprised of first and second cache levels wherein the first cache level includes a first operation queue for storing operations awaiting arbitration in the first cache level and further wherein the cache levels are arranged wherein an operation that retrieves data from the first cache level is arbitrated through the second cache level before the data becomes available to the system bus; and a snoop control state machine adapted to stall arbitration of a second operation initiated in the second cache level responsive to the second load request until a first operation initiated in the first cache level responsive to the first load request has been arbitrated through the second cache level.