Patent ID: 8352526
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. An integrated circuit (IC) having components for providing a first programmable output, the IC comprising: an accumulator circuit that receives a programmable input N and generates an overflow indication and a remainder R left in the accumulator circuit when an overflow indication is made, wherein the accumulator circuit is coupled to receive a first clock signal having a first frequency; means for computing a quotient (R/N) as the remainder R divided by the programmable input N; and means for providing an output signal driven by a second clock signal, wherein the output signal is determined from the overflow indication of the accumulator circuit as adjusted by an amount determined using the quotient R/N and, wherein a second frequency of the second clock signal is greater than the first frequency to enable desired delay increments, the means for providing an output signal generates a stream of “0s” and “1s” defining the output signal, wherein the means for providing an output signal adds or subtracts “0s” or “1s” to the stream of “0s” and “1s” to adjust a frequency of the output signal; wherein the means for providing an output signal comprises a repetitive structure having incremental delay elements; wherein delay provided by the incremental delay elements of the repetitive structure is calibrated under current temperature and supply voltage conditions during operation of the IC; and wherein a measurement of the number of incremental delay elements equal to one accumulator clock period can be performed under the current temperature and supply voltage conditions.