Patent ID: 8207759
Filing Date: 2012-06-26
Classification: H03K

Abstract:
1. Apparatus connecting two MIPI signal sources, each defining MIPI conforming clock and data lanes to an MIPI interface, the apparatus comprising: an analog switch with two inputs, one connected to each of the two MIPI signal sources, one output connecting to the MIPI interface, and a control signal that defines the state of the analog switch; a controller comprising a first gate having a first gate output with at least one input connected to at least one of the clock lane signals from one signal source, and a second gate having a second gate output with at least one input connected to at least one of the clock lane signals from the other signal source; wherein each gate defines a threshold, wherein the first and the second gates respond when their thresholds are exceeded; the controller further comprising a latch comprising one input connected to the first gate output, and a second input connected to the second gate output, wherein the latch outputs the control signal to the analog switch.