Patent ID: 6233168
Filing Date: 2001-05-15
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a plurality of memory cell rows having a plurality of memory cell transistors each of which has a gate, a source and a drain, the gates of the memory cell transistors being connected to a word line, sources and drains of the memory cell transistors being serially connected;a plurality of column lines electrically connecting connection nodes between sources and drains of said memory cell transistors in a column direction;a power source line supplying a predetermined electrical potential to said column lines;a first sense amplifier and a second sense amplifier detecting an electrical value appeared on said column lines;a sense column line selection circuit selectively connecting two column lines connected to one terminal of each of two selected memory cells that are separated by a predetermined number of memory cells on a given memory cell row to said first and second sense amplifiers, respectively; anda power source supply column line selection circuit selectively connecting two column lines connected to another terminal of said two selected memory cells to said power source line, wherein a resistance value of a conductive path from said selected memory cells to said first and second sense amplifiers is smaller than a total of an ON-resistance value of said predetermined number of memory cells.