Patent ID: 8487795
Filing Date: 2013-07-16
Classification: G11C,H03M

Abstract:
1. A time-interleaved track-and-hold circuit for reducing jitter in an analog-to-digital converter including a plurality of corresponding time-interleaved analog-to-digital converter channels, the track-and-hold circuit comprising: a clock generator operative to receive a global sine-wave input clock signal and to generate therefrom a plurality of square-wave output clock signals, each of the output clock signals having different phases relative to one another; and a switching array operative in one of at least a track mode and a hold mode, the switching array comprising a plurality of switch circuits, each of the switch circuits being adapted to receive an analog input signal supplied to the track-and-hold circuit, a corresponding one of the output clock signals, and the global sine-wave input clock signal, each of the switch circuits being operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and being operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave input clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the plurality of switch circuits.