Patent ID: 9027022
Filing Date: 2015-05-05
Classification: G06F

Abstract:
1. A device comprising: a multi-core hardware processor having a plurality of execution cores; a plurality of virtual machines that each operate in accordance with a virtual instruction set, wherein each of the virtual machines executes on a corresponding one of the execution cores; an in-memory database comprising different portions of data each stored within a different one of a plurality of memory partitions, wherein each of the memory partitions is associated with a different one of the execution cores; and a plurality of tasks that execute on the virtual machines to decompose an incoming transaction for the in-memory database into sub-transactions that each modify respective portions of the data stored by the memory partitions, deploy the sub-transactions to the execution cores associated with the respective memory partitions that store the respective portions of the data to be modified by the sub-transactions, and concurrently execute the sub-transactions of the incoming transaction on the respective execution cores to which the sub-transactions are deployed, wherein each virtual machine of the virtual machines includes, for the corresponding execution core, a scheduler that manages a separate run list data structure that stores references to tasks of the plurality of tasks that are scheduled for execution by the corresponding execution core and also manages a separate cross-queue data structure that stores references to tasks migrated to the virtual machine by tasks executing on other virtual machines of the virtual machines.