Patent ID: 6051456
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A method of manufacturing a semiconductor component comprising:providing a substrate;forming a dielectric structure over a first portion of the substrate;forming an oxide layer over a second portion of the substrate, the second portion of the substrate adjacent to the first portion of the substrate;depositing a first layer over the dielectric structure and over the oxide layer, the first layer comprised of silicon;etching the first layer to expose a portion of the oxide layer;etching the portion of the oxide layer to expose a portion of the second portion of the substrate;depositing a second layer over the first layer after etching the oxide layer, the second layer comprised of silicon; andusing the first and second layers to form each of at least three electrodes for a transistor by etching portions of the first and second layers after depositing the second layer wherein at least one of the portions of the first and second layers is self-aligned to the dielectric structure.