Patent ID: 7445982
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device having a semiconductor substrate, a planar bipolar transistor exhibiting a low breakdown voltage on the semiconductor substrate, and a trench lateral MOSFET exhibiting a high breakdown voltage, the method comprising: forming two or more well regions of a second conductivity type in a surface of the semiconductor substrate; forming an oxide film on the surface of the semiconductor substrate to form a mask; forming a trench in one of the well regions for forming the trench lateral MOSFET using the oxide mask; forming an expanded drain region of the second conductivity type around the trench; forming a thick oxide film on an inner side wall of the trench; etching a bottom of the trench to a level that is deeper than a lower edge of the expanded drain region using the thick oxide film as a mask; removing the oxide film on the surface of the semiconductor substrate; forming a nitride mask on the surface of the semiconductor substrate and an inner surface of the trench, the mask being a nitride film, and a part thereof being selectively removed; forming a selective oxide film using the nitride mask; forming a gate oxide film inside the trench; forming a gate electrode on the gate oxide film; forming a base region of a first conductivity type selectively in the bottom of the trench and forming a base region of the first conductivity type selectively in one of the well regions of the second conductivity type for forming the planar bipolar transistor; forming a source region of the second conductivity type in the bottom of the trench, the base region being deeper than the source region, and forming a drain region of the second conductivity type outside an upper portion of the trench; selectively forming a first diffusion region of the second conductivity type in the well region of the second conductivity type for forming the planar bipolar transistor, the first diffusion region operating as an emitter or a collector of the planar bipolar transistor; selectively forming a second diffusion region of the second conductivity type in the base region of the first conductivity type, which is formed in the well region of the second conductivity type for forming the planar bipolar transistor, the second diffusion region operating as a collector or an emitter of the planar bipolar transistor; selectively forming a third diffusion region of the first conductivity type in the base region of the first conductivity type, which is formed in the well region of the second conductivity type for forming the planar bipolar transistor, the third diffusion region operating as a base of the planar bipolar transistor; forming an interlayer insulation film on the surface of the semiconductor substrate and inside the trench; removing a portion of the interlayer insulation film on the bottom of the trench to expose the source region; filling the trench with a contact electrode; and forming a metal electrode connected to the contact electrode, forming a metal electrode connected to the gate electrode, forming a metal electrode connected to the drain region, and forming metal electrodes connected to the respective diffusion regions.