Patent ID: 6101118
Filing Date: 2000-08-08
Classification: G11C

Abstract:
A voltage regulator for memory circuits, comprising:a booster circuit that supplies a boosted voltage;a differential stage having a non-inverting input terminal receiving a control voltage independent of temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to the booster circuit to receive the boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference based on a comparison of the voltages at the input terminals of the differential stage; anda connecting transistor inserted between the feed terminal and the output terminal of the differential stage, wherein said connecting transistor is configured as source follower and has a control terminal connected to said output terminal of the differential stage, a drain terminal connected to the booster circuit, and a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit a transition of a voltage on said output terminal.