Patent ID: 7404042
Filing Date: 2008-07-22
Classification: G06F

Abstract:
1. A method of fetching an instruction from memory for execution in a programmable processor, in which instructions may cross a memory line boundary, the method comprising: initially fetching a first line of instruction data in response to a first address; determining from the first line of instruction data if an instruction to be fetched crosses a boundary between the first line of instruction data and a second line of instruction data, wherein the fetched first line of instruction data contains a first piece of the instruction to be fetched; upon determining that the instruction to be fetched crosses the boundary, determining whether or not a line of cache memory corresponding to a second address contains a second piece of the instruction to be fetched; upon determining that the cache memory corresponding to the second address does not contain the second piece of the instruction to be fetched: (a) invalidating the initial fetching of the first line of instruction data and recycling the first address; (b) pre-fetching the second line of instruction data from a higher level memory resource; (c) in response to the recycled first address, fetching the first line of instruction data; (d) fetching the pre-fetched second line of instruction data in response to the second address; and (e) compiling the pieces of the instruction to be fetched from the fetched first and second lines of instruction data.