Patent ID: 6274409
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method for making a semiconductor device comprising the steps of:forming a plurality of transistors in a semiconductor substrate;forming a first dielectric layer overlying the semiconductor substrate;selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion;depositing conducting material into the first opening to define a merged contact between the first transistor portion and the second transistor portion;forming a second dielectric layer overlying the first dielectric layer and the merged contact;selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor; anddepositing conducting material into the second opening to define a first via with the merged contact, and while depositing conducting material into the third opening to define a second via with the source/drain region of the third transistor to define a self-aligned contact.