Patent ID: 6804244
Filing Date: 2004-10-12
Classification: H04L

Abstract:
A single-chip integrated circuit comprising:A. processor circuitry; and B. memory circuitry holding instructions defining: i. sending of packets of real-time information from the integrated circuit by initially generating at the integrated circuit the packets of real-time information with a source data rate greater than zero kilobits per second, and a diversity rate, the diversity data rate initially being at least zero kilobits per second; ii. sending the packets, thereby resulting in a quality of service QoS; iii. obtaining at the integrated circuit a measure of the QoS; iv. comparing the QoS with a threshold of acceptability; and v. when the QoS is on an unacceptable side of the threshold, increasing the diversity rate and sending not only additional ones of the packets of real-time information but also sending diversity packets at the diversity rate as increased.