Patent ID: 6118696
Filing Date: 2000-09-12
Classification: G11C,H01L

Abstract:
A non-volatile semiconductor memory cell array comprising:a first group of units strings;a second group of unit strings, wherein the second group of units is arranged substantially in parallel with the first group of units strings such that strings from the first group alternate with strings from the second group;a second common source line arranged substantially orthogonal to the unit strings and coupled to each unit string of the second group of unit strings;a first group of bit lines arranged substantially in parallel with the unit strings, wherein each bit line of the first group of bit lines is coupled to a corresponding unit string of the first group of unit strings;a second group of bit lines arranged substantially in parallel with the unit strings, wherein each bit line of the second group of bit lines is coupled to a corresponding unit string of the second group of unit strings;wherein the bit lines are formed on a different level than the common source lines.