Patent ID: 7049697
Filing Date: 2006-05-23
Classification: H01L

Abstract:
1. A semiconductor device including a plurality of chips, the chips having front surfaces and back surfaces, the device comprising: a support attached to the chips on the back surfaces thereof, the chips being arranged on the support in a planar horizontal structure with a previously formed filling between the chips; a first layer formed of a solid dielectric material and having a first surface and an opposing second surface, the first layer being disposed on the front surfaces of the chips, the first surface being in contact with the front surfaces of the chips so that the chips separate the first layer from the support, the first layer having a plurality of vias formed therein; a plurality of studs corresponding to the vias and disposed therein; and a second layer attached to the first layer on a the second surface of the first layer, the second layer being formed of a solid dielectric material and having conducting pads on a surface thereof in contact with the first layer, the conducting pads being in registration with the vias so that each conducting pad forms an end of the corresponding via, the second layer including electrical wiring connecting to the chips through the studs and the conducting pads, at least a portion of the electrical wiring running within the second layer from one conducting pad to another conducting pad for making electrical connection between the chips, wherein said plurality of chips includes chips with active devices and a chip without active devices.