Patent ID: 8115514
Filing Date: 2012-02-14
Classification: H03K

Abstract:
1. An integrated circuit structure comprising: a first positive power supply node carrying a first positive power supply voltage; a second positive power supply node carrying a second positive power supply voltage higher than the first positive power supply voltage; a signal input node; a latch comprising: a first pre-charge transistor comprising a source-drain path coupled between the second positive power supply node and the first output node; a second pre-charge transistor comprising a source-drain path coupled between the second positive power supply node and the second output node; and a first delay-inverter coupled between the signal input node and inputs of the first NMOS transistor and the second NMOS transistor, wherein the first delay-inverter is configured to allow the first pre-charge transistor to pre-charge the first output node before an input signal at the signal input node arrives at a gate of the second NMOS transistor and the second pre-charge transistor to pre-charge the second output node before the input signal at the signal input node arrives at a gate of the first NMOS transistor.