Patent ID: 6310928
Filing Date: 2001-10-30
Classification: H03L

Abstract:
A PLL circuit comprising:a ring oscillator used as a voltage controlled oscillator;a frequency divider for dividing a frequency of an output signal of the ring oscillator;a phase comparator for comprising a frequency-division output from the frequency divider and a reference signal;a control voltage generating circuit for generating a control signal for controlling the number of stages of delay circuits of the ring oscillator on the basis of a designated PLL output frequency; anda data table for storing information on the number of stages of the delay circuits of the ring oscillator having a lock range including the designated PLL output frequency in a central region thereof;wherein the control circuit controls reading-out the information from the data table with reference to the designated PLL output frequency, and generates a control signal for controlling the number of the stages of the delay circuits of the ring oscillator and a frequency division ratio of the frequency divider on the basis of read-out information.