Patent ID: 6490640
Filing Date: 2002-12-03
Classification: H04L,H04Q

Abstract:
A packet data switch comprising:an input port, having a plurality of input connections thereto, for receiving data cells; means for connection to a plurality of output ports, for transmitting data cells thereto; means for assigning to each incoming data cell a parameter value indicative of a priority to be given to transmission of said data cell, wherein the parameter value assigned to each incoming data cell is determined by a priority level assigned to the input connection on which the data cell is received, and by the number of data cells from that input connection still awaiting transmission; an input buffer memory for storing the incoming data cells at addresses indicated by known pointers; a first memory for storing the pointers allocated to the incoming data cells at known locations; and a second memory for storing the known locations in an array addressable by means of the assigned parameter value, such that, when data cells are to be transmitted, the second memory can be used to retrieve from the first memory the pointer associated with the data cells which are next to be transmitted in terms of their priority; and wherein, when the number of data cells from an input connection still awaiting transmission exceeds a threshold, pointers associated with further incoming data cells on that connection are stored in the first memory at locations which are flagged, and all such further data cells are transmitted in accordance with a first-in, first-out process.