Patent ID: 6433590
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A sense amplifier circuit for semiconductor memory devices, comprising:a first bias circuit for generating a first bias signal in response to a sense amplifier enable signal; a first precharge circuit for supplying precharge current to a first node in response to the first bias signal and a precharge control signal; a second bias circuit for generating a second bias signal in response to the sense amplifier enable signal; a second precharge circuit for supplying precharge current to a second node in response to the second bias signal and the precharge control signal; a current mirror circuit, coupled to the first node, for supplying current to the first node; a differential amplifier having a first input coupled to the first node, a second input coupled to the second node and an output for providing an amplified voltage difference between the first and second nodes; a first switch circuit, coupled to the first precharge circuit and the current mirror circuit, for supplying a voltage in response to a discharge control signal; a second switch circuit, coupled to the second precharge circuit, for supplying the power voltage supply in response to the discharge control signal; a first MOS transistor having a source-drain path coupled between a first data line and the first node, and a gate coupled to the first bias signal; a second MOS transistor having a source-drain path coupled between a second data line and the second node, and a gate coupled to the second bias signal; a first data line discharge circuit, coupled to the first data line, for discharging current in response to the discharge control signal; and a second data line discharge circuit, coupled to the second data line, for discharging current in response to the discharge control signal.