Patent ID: 7047372
Filing Date: 2006-05-16
Classification: G06F,H04L

Abstract:
1. A computer system, comprising a plurality of processing nodes interconnected by a first point-to-point architecture, the processing nodes being configured in a plurality of multiprocessor clusters, the first point-to-point architecture including a plurality of global links and a plurality of local links, the processing nodes within each cluster being interconnected via the local links of the first point-to-point architecture, the clusters being interconnected via the global links of the first point-to-point architecture, the computer system further comprising a system memory comprising a plurality of portions each of which is associated with one of the processing nodes, each processing node comprising a processor, a memory controller for controlling access to the associated portion of the system memory, and a host bridge for facilitating communication with a plurality of I/O devices, the first point-to-point architecture being operable to facilitate first transactions between the processors and the system memory, wherein each cluster further comprises an interconnection controller interconnected with associated ones of the processing nodes in the corresponding cluster via the local links of the first point-to-point architecture, the interconnection controller being configured to facilitate the first transactions, the computer system further comprising at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges, wherein each of the at least one I/O controller is coupled to more than one of the host bridges via the second point-to-point architecture and is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture, the at least one I/O controller further being operable to conduct communications with the host bridges to which it is coupled via the second point-to-point architecture without using the first point-to-point architecture.