Patent ID: 7491607
Filing Date: 2009-02-17
Classification: G11C,H01L

Abstract:
1. A method of fabricating flash memory cells, comprising the steps of: providing a first conductive type substrate; forming a second conductive type deep well in the first conductive type substrate; forming a first conductive type well in the second conductive type deep well; forming a second conductive type shallow doped region in the first conductive type well, wherein the shallow doped region is adjacent to the substrate surface; forming two stacked gate structures over the substrate, wherein each stacked gate structure comprises a tunneling layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the substrate; forming a gate dielectric layer between the stacked gate structures and the substrate surface; forming a select gate on a sidewall of each stacked gate structure; forming a second conductive type deep doped region in the substrate on the other side of each stacked gate structure, wherein the deep doped regions and the shallow doped region are adjacent to each other; forming a common source region in the substrate between the two select gates and a drain region in each deep doped region on one side of the stacked gate structures; forming a dielectric layer over the substrate to cover the stacked gate structures and the substrate, wherein the dielectric layer has a contact opening that exposes a portion of the drain regions and the deep doped regions; and forming a conductive plug inside the contact opening.