Patent ID: 6984566
Filing Date: 2006-01-10
Classification: H01L

Abstract:
1. A damascene gate process, comprising: providing a semiconductor substrate having a pad layer and a etch stop layer formed thereon; forming an insulating layer to cover the etch stop layer; forming an opening by partially removing the insulating layer, the etch stop layer, and the pad layer; forming a protective spacer on the sidewall of the opening, wherein the tops of the protective spacer are lower than the insulating layer; forming a gate conducting layer in the opening; removing the protective spacer and the insulating layer to expose a portion of the semiconductor substrate and the etch stop layer; implanting the exposed semiconductor substrate to form lightly doped drains; forming a gate spacer to cover the gate conducting layer; removing the etch stop layer and the pad layer to expose portions of the semiconductor substrate; and implanting the exposed semiconductor substrate to form source/drain.