Patent ID: 7529367
Filing Date: 2009-05-05
Classification: G06F,H04L

Abstract:
1. An apparatus for performing cryptographic operations, comprising: a cryptographic instruction, received by a pipeline microprocessor as part of an application program executing on said pipeline microprocessor, wherein said cryptographic instruction prescribes one of the cryptographic operations, and wherein said cryptographic instruction is prescribed according to the x86 instruction format, and wherein said one of the cryptographic operations comprises: CFB mode logic, operatively coupled to said cryptographic instruction, configured to direct said pipeline microprocessor to update pointer registers and intermediate results for each of said plurality of CFB block cryptographic operations; execution logic, operatively coupled to said CFB block pointer logic, configured to execute said one of the cryptographic operations; and a bit, coupled to said execution logic, configured to indicate whether said one of the cryptographic operations has been interrupted by an interrupting event.