Patent ID: 6734090
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method of forming an edge seal along a periphery of an integrated circuit device to provide increased corrosion and oxidation resistance to metallization of the integrated circuit device, the method comprising the steps of:a. providing a semiconductor substrate having a metallic feature therein; b. depositing a layer of dielectric material over the semiconductor substrate and metallic feature, the layer of dielectric material comprising a low-k dielectric material; c. selectively removing a portion of the layer of dielectric material to form a cavity and expose a portion of the metallic feature; d. conformally depositing a layer of an insulation material in the cavity and over the layer of dielectric material, wherein the insulation material and dielectric material are different materials; e. removing horizontal portions of the layer of insulation material so as to expose at least the metallic feature in the cavity; f. depositing a barrier metal on the layer of insulation material in the cavity and on the exposed metallic feature; g. depositing a high conductivity metal in the cavity to fill the cavity; and h. planarizing the semiconductor substrate down to the layer of dielectric material to form said edge seal.