Patent ID: 6834334
Filing Date: 2004-12-21
Classification: G11C

Abstract:
A method of accessing a memory array of an integrated circuit through a set of translated address bits translated from a set of initial address bits output by a memory manager of the integrated circuit, the method comprising:receiving a set of row address bits of a set of initial address bits from a memory manager at a first time, said set of row address bits identifying a row memory location; receiving a set of initial column address bits of said set of initial address bits from said memory manager at a second time, said set of initial column address bits arranged to identify a column memory location defined according to a first format; translating at least some of said set of initial column address bits to a set of translated column address bits identifying a column memory location defined according to a second format; and simultaneously presenting said set of row address bits and said set of translated column address bits to access a desired row and column memory location in said memory array.