Patent ID: 7254797
Filing Date: 2007-08-07
Classification: H03K

Abstract:
1. An input/output (I/O) cell for use in combination with a plurality of additional library cells to form a netlist description of an integrated circuit, the (I/O) cell defined by code comprising: a. data specifying a clock input port at a first location within a bounding box of the I/O cell, wherein the bounding box describes a smallest area that encloses the I/O cell; b. data specifying a clock output port at a second location within the bounding box of the I/O cell, wherein the first location in a first instance of the I/O cell abuts the second location in an abutting second instance of the I/O cell; c. data specifying a first clock path adapted to convey a clock signal through the I/O cell from the clock input port to the clock output port; d. data specifying I/O circuitry, including a locked-loop circuit coupled to the clock input port; e. data specifying a second clock path adapted to convey the clock signal from the clock input port to the I/O circuitry; and f. data specifying at least one buffer disposed in at least one of the first and second clock paths.