Patent ID: 7719059
Filing Date: 2010-05-18
Classification: H01L

Abstract:
1. A fin field effect transistor arrangement comprising: a substrate; a first fin field effect transistor on and/or in the substrate, the first fin field effect transistor having a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed; and a second fin field effect transistor on and/or in the substrate, the second fin field effect transistor having a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed, said second fin field effect transistor being arranged laterally alongside the first fin field effect transistor, wherein the first fin field effect transistor and the second fin field effect transistor are set up as a CMOS arrangement, which comprises an n-MOSFET and a p-MOSFET; wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor; wherein the n-MOSFET and the p-MOSFET have different driver current characteristics due to their respective dopings and wherein the different driver current characteristics are compensated for by the different heights of the fins of the n-MOSFET and the p-MOSFET; and wherein the fin of the first fin field effect transistor and/or the fin of the second fin field effect transistor is divided into a plurality of semiconductor partial fins formed laterally alongside one another.