Patent ID: 6657889
Filing Date: 2003-12-02
Classification: G11C

Abstract:
A memory comprising:a plurality of magnetoresistive random access memory cells organized in rows and columns, each of the plurality of magnetoresistive random access memory cells located at intersections of the rows and columns; a first plurality of write bit lines, each of the first plurality of write bit lines having a first end and a second end, wherein a first write current flowing from the first end to the second end is used for placing a data value in a first predetermined memory cell located within a first predetermined column of the plurality of magnetoresistive random access memory cells; a first plurality of write column decode switches, each of the first plurality of write column decode switches having a first terminal connected to the second end of a corresponding one of the first plurality of write bit lines, and a second terminal, the second terminal of each of the first plurality of write column decode switches being commonly connected to a first node for receiving a first write reference current during a first write cycle of the memory; and a second plurality of write bit lines, each of the second plurality of write bit lines having a first end and a second end, wherein a second write current flowing from the first end to the second end is used for placing a data value in a second predetermined memory cell located within a second predetermined column of the plurality of magnetoresistive random access memory cells; a second plurality of write column decode switches, each of the second plurality of write column decode switches having a first terminal connected to the second end of a corresponding one of the second plurality of write bit lines, and a second terminal, the second terminal of each of the second plurality of write column decode switches being commonly connected to a second node for receiving a second write reference current during a second write cycle of the memory; wherein the first write current transitions from a first current value to a second current value within a first predetermined time when the first node is not connected to the second node, and wherein the first write current transitions from the first current value to the second current value within a second predetermined time when the first node is connected to the second node, the second predetermined time being significantly different than the first predetermined time.