Patent ID: 7307323
Filing Date: 2007-12-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having a first gate stack on a surface of the substrate, said first gate stack having a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stacks, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate, wherein the second portion of the surface of the substrate surrounds the first gate stack, wherein the insulative layer does not cover the first gate stack, and wherein a third portion of the surface of the substrate is not covered by the insulative layer or the first liner; a conductive layer comprising a conductive material, wherein the conductive layer is on the top surface of the first gate stack and in direct mechanical contact with the top surface of the first gate stack; a second gate stack on the surface of the substrate, said second gate stack having a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant second liner over the sidewalls of the second gate stack and not over the top surface of the second gate stack; and a second outer spacer over the second liner, wherein the second liner is disposed between the second outer spacer and the sidewalls of the second gate stack, wherein a portion of the second liner covers a fourth portion of the surface of the substrate, wherein the insulative layer covers both the second outer spacer and the top surface of the second gate stack, wherein the insulative layer is direct mechanical contact with both the second outer space and the top surface of the second gate stack, and wherein a maximum thickness of the second outer space in a direction parallel to the surface of the substrate exceeds a maximum thickness of the first outer spacer in the direction parallel to the surface of the substrate.