Patent ID: 9018774
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A chip package comprising: a substrate; a die coupled to said substrate, wherein a first opening through said substrate is coupled to said die, wherein said die comprises a contact pad and a passivation layer having a first surface on said die and an opposing second surface, wherein a second opening in said passivation layer exposes a contact point of said contact pad, and said contact point is within said second opening; an adhesive material directly on and coupled to said second surface of said passivation layer and between said substrate and said die, said passivation layer separating said adhesive layer from said contact pad; a conductive interconnect within an opening of said adhesive material and coupled to said contact point exposed by said first opening; and a molding material coupled to said die, to said substrate and at first and second sides of said die, wherein said molding material has a first sawed sidewall and a second sawed sidewall substantially parallel with said first sawed sidewall.