Patent ID: 6473880
Filing Date: 2002-10-29
Classification: G06F

Abstract:
A system for correcting data errors, comprising:a check bits generation unit for receiving a plurality of data bits, wherein said check bits generation unit is configured to generate a parity bit corresponding to each of a plurality of groupings of said data bits, and wherein said check bits generation unit is configured to generate a global error correction code equivalent to a predetermined combination of a set of error correction codes each individually associated with a corresponding one of said plurality of groupings, wherein the global error correction code is expressed using a smaller number of bits than a total number of bits of said set of error correction codes; an error correction unit coupled to receive said plurality of data bits, said parity bit for each of said plurality of groupings, and said global error correction code, wherein said error correction unit is configured to generate a parity error bit indicating whether a parity error exists for each of said plurality of groupings of said data bits as received, and wherein said error correction unit is configured to generate a syndrome code indicating a position of an error within any of said plurality of groupings, wherein said syndrome code depends upon a difference between said global error correction code and a regenerated global error correction code, and wherein said error correction unit is configured to correct the received data depending upon said parity error bits and said syndrome code.