Patent ID: 7366049
Filing Date: 2008-04-29
Classification: G01R,G06F,G11C

Abstract:
1. An apparatus for updating data in a dual port memory at substantially a same data sampling rate as a clock frequency of the dual port memory, the apparatus comprising: a. an Analog to Digital Converter (ADC) having an input for receiving an input signal and an output, the ADC sampling an input signal at sampling points to provide a stream of data samples, each said data sample having a parameter value; b. the dual port memory for storing data relating to each different parameter value, the memory having at least one input for receiving each parameter value and an output for providing the stored data from an address in the memory corresponding to the received parameter value; c. an updating element having an input coupled to the output of the memory for receiving the stored data, for updating the stored data and for providing the updated data at an output coupled to the at least one input of the dual port memory for writing back into the address corresponding to the received parameter value, a first port of the dual port memory being utilised as the output of the dual port memory coupled to the input of the updating element on a first clock cycle of the dual port memory and a second port of the dual port memory being normally utilised as one of the at least one input of the dual port memory coupled to the output of the updating element on a second clock cycle, a next address being accessed via the first port on the second clock cycle; and d. a comparator having a first input coupled to the output of the ADC for receiving the parameter value on the first clock cycle of the dual port memory and a second input for receiving a next received parameter value on a second clock cycle and an output for providing a match signal if the received parameter value and the next received parameter value are the same, the output of the comparator being coupled to the dual port memory and the match signal being utilised to enable the first port of the dual port memory to be used as the input for the second clock cycle so that the data updated by the updating element on the first clock cycle is provided at the first port rather than the second port and is therefore correctly provided to the input of the updating element on the second clock cycle.