Patent ID: 8090567
Filing Date: 2012-01-03
Classification: G06F

Abstract:
1. A processor-implemented method for managing a simulation model, the method comprising: checking by a simulator for presence of a constraint file to input, the constraint file containing data specifying an assertion test relating to a design of an electronic system and further specifying an associated limit; refusing by the simulator to simulate using the simulation model in response to absence of the constraint file; simulating the electronic system using the simulation model and the constraint file by the simulator; counting a number of times the assertion test is evaluated during simulation by the simulator, the number of times being an evaluation count; determining by the simulator when the evaluation count has reached the limit; and stopping simulation with the simulation model by the simulator in response to the evaluation count reaching the limit, wherein the checking, the refusing, the simulating, the counting, the determining, and the stopping are implemented by the processor.