Patent ID: 7010642
Filing Date: 2006-03-07
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a master device; a first buffer device; a first plurality of integrated circuit memory devices coupled to the first buffer device; a first plurality of signal lines coupled to the master device and the first buffer device, the first plurality of signal lines including signal lines to carry, from the first buffer device to the master device, first data in the form of unidirectional differential signals, and signal lines to carry, from the master device to the first buffer device, second data, control information and address information in the form of unidirectional differential signals; a second plurality of signal lines coupled to the first buffer device; a second buffer device coupled to the second plurality of signal lines, wherein the second buffer device communicates with the first buffer device over the second plurality of signal lines; and a second plurality of integrated circuit memory devices coupled to the second buffer device.