Patent ID: 9003083
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. A buffer circuit comprising: a register array including a plurality of registers in a plurality of stages; and a control circuit configured to rearrange a plurality of pieces of received data in a determined transfer order and to store the rearranged received data in the register array, the control circuit configured to control the register array so that the register array sequentially outputs the plurality of pieces of received data as one piece of transfer data when all the received data is stored, wherein the control circuit controls the register array so that the register array stores a piece of data stored in each register in a register in a preceding stage when the register array outputs the plurality of pieces of received data, and the control circuit determines a write register among the plurality of registers in accordance with the transfer order when the register array newly stores a new piece of the received data and controls the register array so that the register array stores a piece of data stored in the write register in a register in a following stage of the write register and stores the new piece of received data in the write register.