Patent ID: 6181014
Filing Date: 2001-01-30
Classification: H01L,Y10S

Abstract:
An integrated circuit memory device, comprising:an SOI substrate having a semiconductor active layer therein;a first isolation region that extends into and partitions the semiconductor active layer into first and second active regions;first and second access transistors in the first and second active regions, respectively, said first and second access transistors having first and second gate electrodes, respectively;first and second word lines that extend parallel to each and diagonally across said first isolation layer and are electrically coupled to the first and second gate electrodes, respectively;a first electrically insulating layer on the SOI substrate;a first bit line electrically connected to a first source/drain region of said first access transistor by a first bit line contact which extends through said first electrically insulating layer and contacts the first source/drain region of said first access transistor;a second electrically insulating layer on said first bit line, opposite said first electrically insulating layer; anda second bit line electrically connected to a first source/drain region of said second access transistor by a second bit line contact which extends through said first and second electrically insulating layers and contacts the first source/drain region of said second access transistor.