Patent ID: 8946029
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit comprising: forming a plurality of silicon fin structures on a semiconductor substrate; forming disposable spacers on vertical sidewalls of the fin structures; depositing a silicon oxide material over the fins and over the disposable spacers; forming a first patterned masking layer over the silicon oxide material, wherein regions over fins that are desired to have un-merged source/drain regions are left un-masked; subsequent to forming the first patterned masking layer, anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material; forming a second patterned masking layer over the silicon oxide material, wherein regions over fins that are desired to have merged source/drain regions are left un-masked; subsequent to forming the second patterned masking layer, etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched; and epitaxially growing a doped silicon material in the void and on the un-etched fin structure, wherein an un-merged source/drain region is formed in the void and a merged source/drain region is formed on the un-etched fin structure, wherein the method steps, with the exception of forming the plurality of fin structures, are integrated into a conventional FinFET process flow by replacing conventional p-type/n-type epitaxial source/drain formation steps with said method steps.