Patent ID: 6295618
Filing Date: 2001-09-25
Classification: G11C

Abstract:
In a memory device:at least one memory array containing a plurality of memory cells arranged in rows and columns;a DC sense amplifier having first and second inputs and an output coupled to an externally accessible data terminal of the memory device;a pair of I/O lines coupled to the inputs of the DC sense amplifier;a plurality of pairs of complementary digit lines for each column that may be coupled to the pair of I/O lines; anda test circuit for facilitating the testing of the memory device, the testing circuit selectively operating in either a normal mode or a test mode, the testing circuit, when operating in the normal mode, coupling the inputs of the DC sense amplifier to the pair of digit lines for one column of the array, and the testing circuit, when operating in the test mode, coupling one of the inputs of the DC sense amplifier to a first plurality of digit lines of the array and another of the inputs of the DC sense amplifier to a second plurality of digit lines for the array.