Patent ID: 6496446
Filing Date: 2002-12-17
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array having a plurality of memory cells; a plurality of word lines connected to said memory cells; a row decoder connected to said word lines so as to selectively enable one of said word lines; a plurality of digit lines coupled to said memory cells; a sense amplifier circuit having a plurality of sense amplifiers, each of said sense amplifiers being coupled to a respective one of said digit lines; a first latch circuit connected to said sense amplifier circuit so as to latch data of said digit lines; and a control circuit coupled to said row decoder and provided with a chip enable signal which is indicative of an operation mode of said semiconductor memory device so as to inactivate said row decoder when both said first latch circuit finishes latching said data of said digit lines and said chip enable signal is indicative of standby mode of said semiconductor memory device, wherein said sense amplifier circuit is inactivated when said first latch circuit finishes latching said data of said digit lines.