Patent ID: 6239010
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method of manufacturing a capacitor for a mixed-mode circuit, comprising the steps of:providing a substrate;forming an isolation region on the substrate to define an active region in the substrate;forming an oxide layer, a first polysilicon layer and a first silicide layer over the substrate;patterning the oxide layer, the first polysilicon layer and the first silicide layer to form a gate structure on the active region and to form a first polysilicon electrode and a first silicide electrode on the isolation region;forming a dielectric layer over the substrate;forming an opening exposing a portion of the first silicide electrode;forming a second silicide layer on a sidewall and a bottom of the opening and on the dielectric layer;performing a planarization process to remove a portion of the second silicide layer above the dielectric layer, wherein the remaining second silicide layer in the opening, the silicide electrode and the polysilicon electrode together form a bottom electrode of the capacitor;forming a capacitor dielectric layer over the substrate;forming a first metal layer over the substrate; andpatterning the first metal layer to form an upper electrode of the capacitor.