Patent ID: 6180490
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method of fabricating shallow trenches in the manufacture of semiconductor devices with sub-quarter micron technology, whereby the shallow trench is filled by the method comprising:providing a silicon substrate, the silicon having a trench formed therein;forming a special trench liner layer of silicon dioxide film by deposition through the chemical vapor deposition method employing tetraethylorthosilicate silicon source material and ozone (TEOS-ozone);oxidizing thermally the silicon substrate to form within the trench a thermal silicon dioxide layer underneath the smooth TEOS-ozone trench liner layer;depositing an enhanced high density plasma chemical vapor deposition (CVD) silicon dioxide layer over said special trench liner layer of silicon dioxide film;annealing all layers thermally at elevated temperatures, about 1050.degree. C. in nitrogen or oxygen gas ambient for densification;planarizing the excess trench fill material by chemical mechanical polishing (CMP) to form a planar surface on the silicon substrate.