Patent ID: 6798270
Filing Date: 2004-09-28
Classification: H03K

Abstract:
A system controlled by configuration memory cells susceptible to single event upsets, the system comprising:a plurality of programmable logic blocks; a plurality of interconnect lines; and a plurality of multiplexer circuits programmably coupling the interconnect lines to each other and to the logic blocks, each of the multiplexer circuits comprising: a plurality of input terminals; an output node; a plurality of first pass gates coupled between the plurality of input terminals and the output node, each of the first pass gates having a different associated input terminal and further having a gate terminal; a plurality of second pass gates each coupled in series with an associated one of the first pass gates and forming therewith a pass gate pair coupled between the associated input terminal and the output node, each of the second pass gates having a gate terminal; and a plurality of configuration memory cells susceptible to the single event upsets, each configuration memory cell having an output terminal coupled to the gate terminals of an associated one of the first pass gates and an associated one of the second pass gates, wherein each of the pass gate pairs includes their associated first and second pass gates having gate terminals coupled to different ones of the plurality of configuration memory cells, respectively.