Patent ID: 6438182
Filing Date: 2002-08-20
Classification: G06F,H04L

Abstract:
A correlator comprising:a circuit for serially receiving in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels at one input bit time periods and converting the data into blocks of n bit parallel I and n bit parallel Q signal data; a data bus that receives blocks of n bit parallel I and n bit parallel Q signal data and n bit parallel I and n bit parallel Q reference data from respective I and Q signal channels and I and Q reference channels, said data bus having n parallel paths extending therefrom; a multiplexer connected within each of the n parallel paths, each multiplexer receiving the n bit parallel I and Q reference data and a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path, and including I and Q summed outputs based on the value of I and Q reference data on a bit by bit basis; an n bit Wallace Tree Adder connected to each of the I and Q summed outputs for each multiplexer within each of the n parallel paths that computes a count based on the number of bits that are set out of n bits to form partial correlation products; an adder and an accumulator register in feedback with the adder that adds partial correlation products into a single sum; and an output bus for receiving pairs of I and Q component signal outputs from the parallel paths one at a time at one input bit time periods such that there is one correlation product output for every I and Q pair of input bits.