Patent ID: 6552386
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A scalable split-gate flash memory cell structure, comprising:a semiconductor substrate of a first conductivity type having an active region formed between two shallow-trench-isolation (STI) regions: a cell region comprising a common-source region, a scalable split-gate region, and a scalable common-drain region, wherein said scalable split-gate region being formed between said common-source region and said, scalable common-drain region is defined by a third sidewall dielectric spacer being formed over an outer sidewall of said common-source region; said common-source region being formed in a side portion of said scalable split-gate region comprising a common-source diffusion region of a second conductivity type being formed in said semiconductor substrate of said active region, a first sidewall dielectric spacer being formed over a sidewall of said scalable split-gate region, and a first flat bed being formed outside of said first sidewall dielectric spacer, wherein said first flat bed is formed by said common-source diffusion region in said active region and two fifth raised field-oxide layers in said two STI regions; said scalable common-drain region being formed in another side portion of said scalable split-gate region comprising a common-drain diffusion region of said second conductivity type being formed in said semiconductor substrate of said active region, a fourth sidewall dielectric spacer being formed over another sidewall of said scalable split-gate region, and a second flat bed being formed outside of said fourth sidewall dielectric spacer, wherein said second flat bed is formed by said common-drain diffusion region in said active region and two sixth raised field-oxide layers in said two STI regions; said scalable split-gate region comprising a floating-gate region being defined by a second sidewall dielectric spacer formed over an outer sidewall of said common-source region and a select-gate region being formed between said floating-gate region and said scalable common-drain region, wherein said floating-gate region comprises a floating-gate structure being formed over a tunneling-dielectric layer in said active region and a portion of a control-gate conductive layer or a control-gate conductive island being at least formed over said floating-gate structure and said select-gate region comprises another portion of said control-gate conductive layer or said control-gate conductive island being at least formed over a gate-dielectric layer in said active region; and said floating-gate structure comprising a tip-cathode line being formed between a first thermal poly-oxide layer formed over its outer sidewall near said select-gate region and a refilled-oxide layer formed in its upper corner portion near said common-source region, wherein said tip-cathode line has a second poly-oxide layer being formed over its top portion to act as a tunneling-oxide layer.