Patent ID: 7330058
Filing Date: 2008-02-12
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit, comprising: a phase detecting circuit for comparing a phase difference between a data signal and a plurality of clock signals to generate two proportional control signals and two integration control signals; a first charge pump controlled by the proportional control signals to generate a first current; a proportional load circuit for receiving the first current and outputting a proportional voltage in proportion to the first current; a second charge pump controlled by the two integration control signals to generate a second current; an integration load circuit for receiving the second current to output an integration voltage; and a voltage control oscillating circuit for adjusting phases of the clock signals in response to the proportional voltage and the integration voltage, wherein the clock signals have the same frequency but different phases, and the frequency of the data signal is a multiple of the frequency of the clock signals.