Patent ID: 6148375
Filing Date: 2000-11-14
Classification: G06F

Abstract:
In a shared memory system having a plurality of nodes and a hierarchy of cache memories, where each node is a shared memory multiprocessor, a method of maintaining cache coherency in said system in response to read or write access commands, said method comprising:a. maintaining status owner information for each line of a highest level of cache memory in said system, said status owner information indicating which of said nodes, of a read only line, first read said read only line and said status owner information indicating which of said nodes of a read/write line was a last node to have either first read said read/write line or to have last modified said read/write line, wherein each indicated node for each cache line is a node that owns said each cache line; andb. if a cache at one of said nodes at said highest level of cache memory in said system issues a read or write access to a line that misses in the highest level cache of said system then placing, by a node that owns latter said cache line, latter said cache line on a bus directly interconnecting said highest level of cache memories.