Patent ID: 7880782
Filing Date: 2011-02-01
Classification: H01L,H04N

Abstract:
1. A method for reducing dark current within a charge-coupled device, the method comprising: a) providing at least four gate phases separated by an insulating layer from a buried channel of a first conductivity type in a well or substrate of a second conductivity type; b) providing a storage and barrier region under each gate phase for separating charge packets when in an accumulation state; c) clocking the gate phases at only two voltage levels for advancing the charge packets through the charge-coupled device such that a sum of products of capacitances and voltage changes is zero or substantially zero according to where C n is a capacitance of gate phase n to the well or substrate of the second conductivity type and ΔV n is a voltage change on the gate phase n, wherein for a first time period, maintaining a set of first gate phases holding photogenerated charge packets in the accumulated state and maintaining a set of second gate phases not holding photogenerated charge packets in a depleted state; for a second time period, clocking the photogenerated charge packets into a set of third gate phases in the depleted state and clocking the second set of gate phases not holding photogenerated charge packets into the accumulated state; and for a third time period, clocking the third set of gate phases holding the photogenerated charge packets into the accumulated state and clocking a fourth set of gates not holding the photogenerated charge packets into the depletion state; wherein the second time period is shorter or substantially shorter than the first and third time periods.