Patent ID: 8102962
Filing Date: 2012-01-24
Classification: G11C

Abstract:
1. A shift register, comprising: first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node, a second input node and an output node, wherein the first through K-th shift register stages of the plurality of shift register stages is grouped into a first section and the (K+1)-th through M-th shift register stages of the plurality of shift register stages is grouped into a second section such that each of the first and second sections comprises a corresponding number of consecutive shift register stages, wherein K is an integer greater than 1 but less than the number, M, of the plurality of shift register stages, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi