Patent ID: 7669165
Filing Date: 2010-02-23
Classification: G06F

Abstract:
1. A method for conducting equivalence checking of a circuit, comprising: receiving a register-transfer level (RTL) netlist representation of a circuit; receiving a power specification file describing low power requirements of the circuit including, defining isolation cells, defining level shifter cells, defining state retention cells, identifying power logic, and creating power domains; creating using a method implemented on a computer system, a gate netlist using the RTL netlist and the power specification file, wherein the gate netlist represents a design implementation of the circuit; creating using a method implemented on the computer system, a reference low power RTL netlist using the RTL netlist and the power specification file, wherein the reference low power RTL netlist represents a design specification of the circuit; wherein creating a reference low power RTL netlist includes annotating the low power requirements described in the power specification file into the reference low power RTL netlist; wherein creating a reference low power RTL netlist further includes, creating isolation logic in the reference low power RTL netlist, creating level shifter logic in the reference low power RTL netlist, and creating state retention logic in the reference low power RTL netlist; and performing equivalence checking using a method implemented on the computer system, between the gate netlist and the reference low power RTL netlist.