Patent ID: 7084498
Filing Date: 2006-08-01
Classification: H01L

Abstract:
1. A semiconductor device comprising a semiconductor chip having element electrodes which are distributed at selected locations on substantially an entire surface of the semiconductor chip, said element electrodes being spread along a first direction and a second direction transverse to the first direction; an insulating film formed on said semiconductor chip so as to cover a side of each of the element electrodes and to expose at least a partial area of each of said element electrodes; a plurality of the discrete projected stress relaxation materials formed on said insulating film; projected electrodes covering at least portions of tops of said stress relaxation materials, which projected electrodes are positioned at selected locations of substantially the entire surface on the semiconductor chip; wiring lines to electrically connect the projected electrodes to connection electrodes; and solder bumps respectively formed on each of projected electrodes, wherein each of the projected electrodes is shifted to the same position relative to a corresponding one of the element electrodes connected thereto by a corresponding one of the wiring lines in the first and second directions in the surface of the semiconductor chip as each of the other projected electrodes relative to the corresponding element electrode connected thereto so that the each of the projected electrodes, the corresponding element electrodes connected thereto and the corresponding wiring layers are arranged side-by-side to reduce a length of the respective wiring lines connecting the projected electrodes to the corresponding element electrodes.