Patent ID: 6284644
Filing Date: 2001-09-04
Classification: G01V,H01L

Abstract:
A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from said fluorinated silica glass dielectric layer, comprising the steps of:providing a semiconductor structure having a metal structure formed thereover;forming a liner layer over said semiconductor structure, covering said metal structure;forming a fluorinated silica glass dielectric layer over said liner layer; said fluorinated silica glass dielectric layer having an exposed upper surface;treating said fluorinated silica glass dielectric layer with a first nitrogen gas/plasma treatment to form a fluorine depleted upper capping layer from said exposed surface of said fluorinated silica glass dielectric layer;forming a TEOS oxide layer over said upper capping layer;planarizing said TEOS oxide layer to form a planarized TEOS oxide layer;patterning said planarized TEOS oxide layer, said upper capping layer, said treated fluorinated silica glass dielectric layer, and said liner layer to form a via hole therethrough exposing a portion of said metal structure and exposing sidewalls of said patterned treated fluorinated silica glass dielectric layer within said via opening;treating at least said exposed sidewalls of said patterned treated fluorinated silica glass dielectric layer within said via opening with a second nitrogen gas/plasma treatment to form a fluorine depleted sidewall capping layer (34) from said exposed sidewalls of said patterned treated fluorinated silica glass dielectric layer; wherein said upper and sidewall capping layers prevent said outgassing from said patterned fluorinated silica glass dielectric layer; andforming a metal interconnect within said via opening.