Patent ID: 8683183
Filing Date: 2014-03-25
Classification: G06F

Abstract:
1. A processor comprising: a plurality of front end units including a fetch unit to fetch instructions and a decoder to decode fetched instructions; a plurality of execution units, at least one of the execution units including a circuit comprising: a first multiplier to multiply a first reference value with a first coefficient to obtain a first product; a second multiplier to multiply a second reference value with a second coefficient to obtain a second product; a first adder to combine the first and second products to obtain a first sum; a second adder to combine the first sum and a third term to obtain a base value; a third level of adders each to combine the base value with one of a plurality of representations of the first coefficient to obtain a first sum set; and a fourth level of adders each to combine the first sum set with one of a plurality of representations of the second coefficient to obtain a second sum set, wherein the circuit is to populate a vector destination storage having a plurality of locations each to store an output of one of the third and fourth levels of adders.