Patent ID: 8589769
Filing Date: 2013-11-19
Classification: G11C

Abstract:
1. A memory subsystem, the memory subsystem comprising: a memory bus comprising multiple bitlanes; and a memory assembly in communication with the memory bus, the memory assembly including instructions for: creating an error code correction (ECC) word, the ECC word including data bits and ECC bits arranged into multiple multi-bit ECC symbols, wherein each ECC symbols is comprised of four data bits, wherein each of the four data bits is transmitted sequentially on a single bit lane, the ECC symbols sent along each and every utilized bitlanes such that the number of ECC symbols equals the number of utilized bitlanes on the memory bus and the ECC word includes an 88/72 ECC code that will detect errors in the symbols, correct errors in the symbols and detect double symbol errors; and transmitting the ECC word in four transfers via the memory bus.