Patent ID: 6664806
Filing Date: 2003-12-16
Classification: G11C,H01L

Abstract:
A method of forming a logic array for a decoder, the method comprising:forming an array of single crystalline ultra thin vertical transistors that are selectively coupled to implement a logic function that selects a wordline based on a supplied address, wherein forming each single crystalline vertical transistor in the array includes; forming an ultra thin single crystalline vertical first source/drain region; forming an ultra thin single crystalline vertical second source/drain region; and forming an ultra thin single crystalline vertical body region which couples the first and the second source/drain regions; forming a number of address lines in trenches that separate rows of the single crystalline ultra thin vertical transistors; gating selected single crystalline ultra thin vertical transistors with the address lines; forming output lines, orthogonal to the address lines, that each interconnect the second source/drain regions of single crystalline ultra thin vertical transistors in a column of the array so as to implement a selected logic function.