Patent ID: 8437192
Filing Date: 2013-05-07
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a plurality of bit lines over a substrate; a plurality of memory cells over the plurality of bit lines, wherein at least one memory cell of the plurality of memory cells is over another one memory cell of the plurality of memory cells; a source plane over the plurality of memory cells; bottom and top memory cubes including respective arrays of semiconductor pillars, a given semiconductor pillar in each array of semiconductor pillars including a plurality of dielectric charge trapping structures in a NAND string along a side of the given semiconductor pillar, and word lines orthogonal to the semiconductor pillars and adjacent the charge trapping structures of the semiconductor pillars, the bottom memory cube including said plurality of memory cells, the dielectric charge trapping structures in the plurality of dielectric charge trapping structures including a tunneling layer adjacent a corresponding word line in said word lines, and a dielectric charge trapping layer between the tunneling layer and a blocking layer, the blocking layer between the dielectric charge trapping layer and the given semiconductor pillar; the source plane being between the bottom and top memory cubes, the source plane selectively coupled to top ends of each of the semiconductor pillars of the bottom memory cube by a bottom set of source plane select transistors, and selectively coupled to bottom ends of each of the semiconductor body pillars of the top memory cube by a top set of source plane select transistors; a bottom set of pillar select transistors to selectively couple bottom ends of the semiconductor pillars of the bottom memory cube to corresponding bit lines in said plurality of bit lines; and a top set of pillar select transistors to selectively couple top ends of the semiconductor pillars of the top memory cube to corresponding bit lines in a plurality of top bit lines.