Patent ID: 9099392
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: forming an isolation structure in a substrate; defining a first area in the substrate for forming a floating gate transistor; defining a second area in the substrate, wherein the isolation structure is located between the first area and the second area; forming a gate oxide layer of the floating gate transistor, wherein the gate oxide layer covers a portion of the first area, a portion of the isolation structure and a portion of the second area; defining a first portion of the gate oxide layer above the first area, wherein only the first portion of the gate oxide layer is injected by a plurality of carriers during a programmed state; defining a second portion of the gate oxide layer, wherein only the second portion of the gate oxide layer is ejected by the carriers during an erase state; covering a polysilicon gate of the floating gate transistor on the gate oxide layer; and manufacturing a select transistor connected in serial with the floating gate transistor; wherein a gate terminal of the select transistor is connected to a select gate voltage, a first terminal of the select transistor is connected to a source line voltage, a second terminal of the select transistor is connected to a first terminal of the floating gate transistor, and a second terminal of the floating gate transistor is connected to a bit line voltage; and wherein a thickness of the first portion of the gate oxide layer is thicker than a thickness of the second portion of the second gate oxide layer.