Patent ID: 9070786
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A method for forming a transistor comprising: providing a substrate having therein a first well region of a first conductivity type and a second well region of a second, opposite conductivity type, extending substantially to a first surface of the substrate, the first and second well regions forming an NP or PN junction therebetween, and wherein the first and the second well regions have therein an MOS-portion and the second well region has therein a drain or anode (D/A) portion; forming in the MOS-portion, a gate conductor overlying and insulated from the first surface at least over the first well region and having a first lateral end adapted to substantially locate a first edge of a subsequently formed source region within the first well region and a second lateral end extending at least to the NP and PN junction; protecting the MOS-portion while a bipolar transistor is subsequently formed in the D/A portion in the second well region; forming the bipolar transistor in the second well region, wherein the bipolar transistor comprises an emitter region of the second conductivity type, an intrinsic base region of the first conductivity type communicating with the emitter region, and a collector region of the second conductivity type communicating with the intrinsic base region; protecting the D/A portion and, in either order, forming the source region of the second conductivity type in the first well region and having the first edge laterally proximate the first lateral end of the gate conductor, and forming a well contact region of the first conductivity type in the first well region; and forming multiple conductive contacts communicating respectively with the source region, the gate conductor, the intrinsic base region of the bipolar transistor and the emitter region of the bipolar transistor.