Patent ID: 6173358
Filing Date: 2001-01-09
Classification: A63F,G06F

Abstract:
A computer system comprising:(a) a central processing unit (CPU) in circuit communication with an audio/video/CD drive controller/co-processor (A/V/CD controller/co-processor) via a first system bus;(b) a system memory in circuit communication with said A/V/CD controller/co-processor via a second system bus; and(c) an additional memory element in circuit communication with said CPU via said first system bus;(d) said A/V/CD controller/co-processor further including an arbitrator for arbitrating control over said second system bus, an integral memory interface, an integral graphics coprocessor, an integral digital signal processor, an integral compact disk controller, and an integral video controller all in circuit communication with said CPU and said system memory and each configured such that any one of said CPU, said graphics co-processor, said digital signal processor, said compact disk controller, and said video controller may become bus master of said second system bus; and said CPU may directly access said additional memory element while said A/V/CD controller/coprocessor performs functions with said system memory through said second system bus;(e) an interrupt controller for interfacing interrupts to said CPU and said arbitrator responsive to said interrupt controller such that said CPU does not have the highest priority for control over said second system bus until an interrupt occurs and is detected by said interrupt controller.