Patent ID: 7552362
Filing Date: 2009-06-23
Classification: G06F

Abstract:
1. A system including a primary system and a secondary system, wherein said primary system comprises a primary CPU and a primary PCI bus, said secondary system comprises a secondary CPU, a bridge for connecting said primary PCI bus, a local error output unit, a secondary PCI bus connected to said bridge and said secondary CPU, and a local bus, said secondary CPU is connected to said local error output unit via said local bus and accesses said local error output unit periodically, and said local error output unit is connected to said local bus and outputs a local error output signal to said bridge when said secondary CPU hangs up, said bridge having notification means for notifying said primary CPU of a system error in response to the local error output signal from said local error output unit and holding means for holding information representing a cause of the system error in response to the local error output signal from said local error output unit, and wherein said primary CPU resets said secondary CPU in accordance with the system error notification from said bridge and the information representing the cause of the system error which is held in said holding means.