Patent ID: 8918753
Filing Date: 2014-12-23
Classification: G01R,G06F,G11C

Abstract:
1. At a defect metrology computing device, a method for correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location, comprising: receiving data at the metrology computing device that identifies a defect location for the location on the substrate where the defect was detected; generating at the defect metrology computing device a physical representation of the semiconductor device for the defect location by correlating polygons included in a physical layout file of the semiconductor device with logical cells included in a logical design file of the semiconductor device; generating at the defect metrology computing device a significance determination indicating whether the defect is located in an electrically significant region of the device by correlating the defect location to the polygons and logical cells included in the physical representation; and displaying the significance determination at the defect metrology computing device.