Patent ID: 8779959
Filing Date: 2014-07-15
Classification: G06F,H03L,H03M

Abstract:
1. A method for reducing integral nonlinearity (INL) of a digital-to-analog converter (DAC), wherein the DAC comprises a clock for defining a period of said DAC, an input port for receiving an input signal in each period, and N 1-bit DAC for outputting signal, wherein N is a positive integer, the method comprising the step of: A. providing a priority sequence of the N 1-bit DACs, wherein the priority sequence defines the priority of each of the N 1-bit DACs; B. determining a set among the N 1-bit DACs for outputting according to the priority sequence and the input signal in each period; and C. re-assigning the priority sequence after a first number of periods, wherein a second number of current sources with the highest priority is set to be with the lowest priority, and the second number is no less than one.