Patent ID: 7317649
Filing Date: 2008-01-08
Classification: G11C

Abstract:
1. A semiconductor storage device, comprising: one or more unit blocks each including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines; a first row of sense amplifiers which is arranged on one side of said plurality of bit lines and includes a plurality of sense amplifiers for amplifying data of said plurality of memory cells through said plurality of bit lines in each said unit block; a second row of sense amplifiers which is arranged on an other side of said plurality of bit lines and includes a plurality of sense amplifiers for amplifying data of said plurality of memory cells through said plurality of bit lines in each said unit block; first switch means which switches a connection state between said one side of said plurality of bit lines and said first row of sense amplifiers; second switch means which switches a connection state between said other side of said plurality of bit lines and said second row of sense amplifiers; third switch means which is arranged in an approximate center of said plurality of bit lines in an extending direction thereof and switches a connection state in which one side and an other side of said plurality of bit lines is either connected or disconnected; and refresh control means which sets a state in which said plurality of bit lines is disconnected by said third switch means in refresh operation so as to divide said unit block into a first area on said one side of said plurality of bit lines and a second area on said other side thereof, controls said refresh operation using said first switch means and said first row of sense amplifiers when a selected word line to be refreshed is in said first area, and controls said refresh operation using said second switch means and said second row of sense amplifiers when said selected word line to be refreshed is in said second area.