Patent ID: 6205461
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A floating point unit comprising:a register file;a carry propagate adder coupled to said register file, wherein said carry propagate adder generates an incremented result and an unincremented result;an inverter coupled to said carry propagate adder, wherein said inverter generates a complemented unincremented result;a first select unit coupled to said carry propagate adder and said inverter and a second select unit coupled to said carry propagate adder and said inverter, wherein said incremented result, said unincremented result, and said complemented unincremented result are received by both said first select unit and said second select unit;a first rounding unit coupled to said first select unit, wherein said first rounding unit selects between said incremented result, said unincremented result, and said complemented unincremented result from said first select unit;a second rounding unit coupled to said second select unit, wherein said second rounding unit selects between said incremented result, said unincremented result, and said complemented unincremented result from said second select unit;a leading zero count unit coupled to said first select unit; anda shifting unit coupled to said second select unit and controlled by said leading zero count unit.