Patent ID: 7487299
Filing Date: 2009-02-03
Classification: G06F,Y02D

Abstract:
1. A cache memory with a plurality of ways to receive a read request comprising: the cache memory to allow a subset of the plurality of ways to store at least one dirty line; the cache memory to determine whether a cache line of the read request results in a hit condition, if so, the cache memory to forward the cache line of the read request to an agent; the cache memory to determine whether a cache line is to be stored in one of the subset of the plurality of ways, the cache line received in response to the read request that did not result in the hit condition; and the cache memory to write the at least one dirty line of the subset of the plurality of ways to main memory and not write cache lines of a remaining subset of the plurality of ways to main memory, the remaining subset of the plurality of ways to not store dirty lines.