Patent ID: 6831315
Filing Date: 2004-12-14
Classification: H01L,Y10T

Abstract:
An integrated circuit having a plurality of memory cells, each memory cell including a capacitor comprising:a first electrode having a surface conforming to a hemispherical grain morphology; an ALD-deposited capacitor dielectric layer adjacent to the first electrode and conforming to the hemispherical grain morphology, the capacitor dielectric comprising a material selected from the group consisting of aluminum oxide, titanium oxide, zirconium oxide, niobium oxide, hafnium oxide, silicon oxide and mixtures and compounds thereof; and a second electrode adjacent to and conforming to the hemispherical grain morphology, the second electrode including an ALD-deposited layer directly adjacent to the dielectric layer, wherein the capacitor dielectric layer has a maximum thickness of X at all points over the first electrode and at no point over the first electrode does the capacitor dielectric have a thickness of less than 0.95 times X.