Patent ID: 6985374
Filing Date: 2006-01-10
Classification: G11C

Abstract:
1. A ferroelectric memory device comprising: a memory cell array region; a plurality of wordlines arranged in parallel to each other in a first direction within the memory cell array region; a plurality of main bitlines arranged in parallel to each other in a second direction intersecting the first direction within the memory cell array region; a plurality of blocks into which the memory cell array region is divided in the second direction; a plurality of sub-bitlines provided for each of the main bitlines, each of the sub-bitlines being provided within one of the blocks; a plurality of ferroelectric memory cells respectively provided at intersections between the sub-bitlines and the wordlines; a plurality of first sub-bitline select switches respectively provided between the main bitlines and one ends of the sub-bitlines; a common potential supply line which supplies a common potential to the sub-bitlines; a plurality of second sub-bitline select switches respectively provided between the common potential supply line and the other ends of the sub-bitlines; and a plurality of block select sections provided corresponding to the blocks, wherein one of the block select sections selected from among the block select sections turns on the first sub-bitline select switches and turns off the second sub-bitline select switches in corresponding one of the blocks; and wherein unselected block select sections among the block select sections turn off the first sub-bitline select switches and turn on the second sub-bitline select switches in corresponding two or more of the blocks.