Patent ID: 6622283
Filing Date: 2003-09-16
Classification: H03M

Abstract:
A block trellis decoder for decoding a sequence of convolutionally-encoded symbols, the block trellis decoder comprising:a processing unit, the processing unit receiving the sequence of convolutionally-encoded symbols, the processing unit generating transition metrics for each state of a symbol; and a hardware decoder unit responsive to transition metrics for each block including at least B symbols, the hardware decoder unit generating a fixed length table for each block of transition metrics, the fixed length table including a history entry, an index entry, and a path metric entry, the fixed length tables identifying surviving partial paths for the blocks of symbols, the hardware decoder unit transferring the fixed length tables to the processing unit, the processing unit determining surviving paths from the fixed length tables, the hardware decoder unit including an interface apparatus having: a plurality of transition metric registers for receiving from the data processing unit the transition metrics generated as a result of each symbol; a maximum path metric register responsive to signals from the data processing unit for storing a predetermined maximum allowed path metric; a control register responsive to the data processing unit for storing a field resulting in an initialization of the hardware decoder and a number field determining when updating will take place; and a history register for storing a history field and an index field of the fixed length table for retrieval by the data processing unit.