Patent ID: 6613683
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A method of manufacturing a contact hole of a semiconductor device, comprising:forming a spacer on a side wall of a gate electrode formed over a substrate, wherein an active region of a surface of the substrate is exposed adjacent the spacer; forming a dielectric interlayer over the active region of the substrate, the gate electrode and the spacer; masking a region of the dielectric interlayer aligned over the gate electrode, and subjecting a remaining region of the dielectric interlayer aligned over the active region of the substrate to a first etching process using an etching gas to partially form a contact hole in the dielectric interlayer; detecting when an emission amount of a chemical compound emitted during the first etching process has reached a maximum emission intensity, wherein the chemical compound is produced by a chemical combination of the etching gas and the spacer; and subjecting the remaining region of the dielectric interlayer to a second etching process to further form the contact hole in the dielectric interlayer upon detecting that the emission amount of the chemical compound has reached maximum emission intensity.