Patent ID: 8722459
Filing Date: 2014-05-13
Classification: H01L

Abstract:
1. A method for forming a 3-D integrated circuit, comprising: forming an active device (AD) substrate having an AD region thereon with device contacts therein; forming an isolator substrate separately from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate; forming an integrated passive device (IPD) substrate separately from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having a plurality of TSVs formed underlying the IPD zone through the IPD substrate, wherein the TSVs in the IPD substrate are coupled with the IPDs in the IPD zone, and at least some of the TSVs are adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate, and wherein at least some of the TSVs in the isolator substrate are vertically aligned with at least some of the TSVs in the IPD substrate; and forming a further interconnect zone located between the isolator substrate and the IPD substrate, wherein the further interconnect zone includes a lateral conductor between two or more TSVs in a same substrate, thereby providing a connection selected from a group consisting of a cross-under connection between two or more IPDs in the IPD zone, and a cross-over connection between two or more device contacts of the AD substrate, and wherein at least one of the IPDs has a first element located in the IPD zone and a second element located in the further interconnect zone.