Patent ID: 7005898
Filing Date: 2006-02-28
Classification: H03K

Abstract:
1. A method for controlling a divide ratio in a divider circuit, comprising: synchronously counting a first clock input signal and a first data signal to produce N number of respective synchronously counted output signals, the first data signal being produced as an output of a first type logical operation; performing N number of second type logical operations of the respective synchronously counted output signals, the synchronously counted output signals also being representative of corresponding clock output signals, each of the N number of second type logical operations forming a respective intermediate signal; wherein one of the synchronously counted output signals forms one input to the first type logical operation and forms a first of the corresponding output signals; multiplexing a selected number of the N number of respective intermediate signals to form a multiplexed output, the multiplexed output being provided as another input to the first type logical operation; and providing a control signal to determine the selected ones of the N number of respective intermediate signals to be multiplexed.