Patent ID: 9001138
Filing Date: 2015-04-07
Classification: G06F,G06T

Abstract:
1. A processor comprising: a pre-fetch unit to fetch one or more instructions, a decode unit to decode the one or more instructions, wherein the one or more instructions include a two-dimensional (2-D) gather instruction, an execution unit to perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor, and a two-dimensional (2-D) cache to store the one or more sub-blocks of data in multiple cache lines, to support access to more than one cache line in a single processing cycle, to preserve a two-dimensional structure of the 2-D image, and to support mapping of the one or more sub-blocks to avoid read conflict after loading the one or more sub-blocks, wherein the 2-D cache includes