Patent ID: 6542041
Filing Date: 2003-04-01
Classification: G11B,H03L

Abstract:
A phase locked loop (PLL) which performs frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal and adjusts a control current based on the results of the frequency detection and the phase detection, thereby generating the PLL clock signal synchronized with the EFM signal, the PLL comprising:a charge pump for adjusting the control current in response to the results of the frequency detection and the phase detection and outputting the result as a charge pump output; a first low-pass filter for low-pass filtering the charge pump output and outputting the filtered result as a control voltage; a voltage controlled oscillator for receiving the control voltage and a predetermined reference voltage at differential inputs to provide a differential output voltage, converting the differential output voltage into a differential output current, and delaying an oscillation output signal based on the converted differential output current, thereby generating the PLL clock signal; and a static phase error controller for comparing the control voltage with a triangular signal having a predetermined period and a predetermined amplitude to provide a comparison result and changing the reference voltage based on the compared result.