Patent ID: 7663249
Filing Date: 2010-02-16
Classification: H01L,H05K

Abstract:
1. An embedded chip package structure, comprising: a dielectric material layer, formed by a single material layer; a first patterned circuit layer, embedded in one side of the dielectric material layer and comprising at least a first bonding pad and at least a first contact; and a first chip, disposed on the first patterned circuit layer and embedded in the dielectric material layer and electrically connected to the first bonding pad by performing a flip-chip bonding process; a second patterned circuit layer, embedded in the other side of the dielectric material layer and comprising at least a second bonding pad and at least a second contact; a second chip, disposed on the second patterned circuit layer and embedded in the other side of the dielectric material layer and electrically connected to the second bonding pad by performing a flip-chip bonding process, wherein the first chip and the second chip are separated and arranged back to back, and the dielectric material layer has at least a conductive through hole electrically connecting the first contact to the second contact.