Patent ID: 6108234
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell connected to a word line and a digit line for storing data of two bits in correspondence to first through fourth threshold voltages, said first threshold voltage being lower than said second threshold voltage which is lower than said third threshold voltage, said third threshold voltage being lower than said fourth threshold voltage;supplying means for selectively supplying first through third read-out voltages to said word line, said first read-out voltage has a value between said first and said second threshold voltages, said second read-out voltage has a value between said second and said third threshold voltages, said third read-out voltage has a value between said third and said fourth threshold voltages, said supplying means supplying said second read-out voltage to said word line prior to supplying said first read-out voltage to said word line and prior to supplying said third read-out voltage to said word line; andreading means connected to said digit line for reading said data out of said memory cell in accordance with said first through said third read-out voltages.