Patent ID: 6615304
Filing Date: 2003-09-02
Classification: G06F

Abstract:
A processing unit that executes memory access instructions at an interruption level out of a plurality of interruption levels and that carries out a memory access according to a memory access sequencing model prescribing a limitation to a sequence of issuing the memory access instructions and a sequence of executing the memory access instructions, the processing unit comprising:an interruption level monitor that monitors a change in the interruption level; a memory access sequencing model monitor that monitors a change in the memory access sequencing model; and a controller, when a result of monitoring by the interruption level monitor indicates that there has been a change in the interruption level and a result of monitoring by the memory access sequencing model monitor indicates that there has been the change in the memory access sequencing model following the change in the interruption level, restricting the issuing of memory access instructions corresponding to the changed interruption level until an execution of memory access instructions issued before the change in the interruption level has been finished.