Patent ID: 8835936
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method, comprising: providing a semiconductor structure comprising a substrate, an electrically insulating layer formed on said substrate and one or more elongated semiconductor lines formed on said electrically insulating layer; forming a dummy gate structure on said one or more elongated semiconductor lines, said dummy gate structure comprising a dummy gate insulation layer, a dummy gate electrode formed above said dummy gate insulation layer, and a sidewall spacer formed adjacent to said dummy gate electrode, wherein said one or more elongated semiconductor lines extend from a source side of said dummy gate structure to a drain side of said dummy gate structure; depositing an in situ doped semiconductor material on portions of said one or more elongated semiconductor lines formed adjacent to each of said source and drain sides of said dummy gate structure; diffusing dopant from said in situ doped semiconductor material into said portions of said one or more elongated semiconductor lines formed adjacent to each of said source and drain sides of said dummy gate structure, the diffusion of the dopant into said portions of said one or more elongated semiconductor lines formed adjacent to each of said source and drain sides of said dummy gate structure forming doped source and drain regions in said one or more elongated semiconductor lines; forming a dielectric layer on said semiconductor structure and above said dummy gate structure; after forming said dielectric layer, polishing said semiconductor structure so as to expose said dummy gate electrode; removing said exposed dummy gate electrode and said dummy gate insulation layer from said dummy gate structure so as to form a recess in said semiconductor structure, said recess exposing portions of said one or more elongated semiconductor lines at a bottom of said recess; forming a gate insulation layer comprising a material having a greater dielectric constant than silicon dioxide and a gate electrode comprising a metal in said recess.