Patent ID: 8674724
Filing Date: 2014-03-18
Classification: G11C,H03K

Abstract:
1. A method of operating a field programmable gate array (FPGA), comprising: initiating an active mode for the FPGA, the FPGA comprising a signal input contact and a signal output contact; applying a read voltage to a programmable resistive random access memory (RRAM) element of an RRAM configuration cell of the FPGA, wherein the RRAM configuration cell comprises a switching component configured to electrically connect or electrically disconnect the signal input contact and the signal output contact in response to a first configuration state or a second configuration state, respectively, of the RRAM configuration cell, and further wherein the read voltage is insufficient to appreciably modify an existing configuration state of the RRAM configuration cell; deactivating program transistors associated with the RRAM configuration cell thereby isolating a common node of a voltage divider from a voltage source, the voltage divider being configured to control the switching component; and measuring the signal output contact connected to the RRAM configuration cell for existence of a data signal on the signal output contact in response to applying the read voltage.