Patent ID: 7462535
Filing Date: 2008-12-09
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a bottom plate electrode at a predetermined region of a semiconductor substrate; sequentially forming a middle dielectric layer, an oxide layer and a top electrode layer to cover an entire surface of the semiconductor substrate on which the bottom plate electrode is formed, the middle dielectric layer having an etch selectivity with respect to the oxide layer; patterning the top electrode layer and the oxide layer to expose the middle dielectric layer to form an oxide pattern and an upper plate electrode sequentially stacked, the upper plate electrode having an overlap area with the bottom plate electrode; forming an interlayer dielectric layer to cover an entire surface of the semiconductor substrate where the upper plate electrode is formed; and forming a bottom electrode plug and an upper electrode plug to be connected to the bottom plate electrode and the upper plate electrode through the interlayer dielectric layer, respectively, wherein the bottom plate electrode and the upper plate electrode are made of a metal compound; the oxide pattern and the middle dielectric layer between the bottom plate electrode and the upper plate electrode layer are included in a capacitor dielectric layer, and after the interlayer dielectric layer is formed, the middle dielectric layer extends in a region laterally outside the bottom plate electrode under the interlayer dielectric layer.