Patent ID: 9007836
Filing Date: 2015-04-14
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array comprising a plurality of physical blocks, one of the physical blocks comprising a plurality of string units, the string units including a first string unit and a second string unit, the first string unit including a first NAND string, the second string unit including a second NAND string, the first NAND string including a first memory cell and a first select transistor, the second NAND string including a second memory cell and a second select transistor, a gate of the first memory cell being coupled to a gate of the second memory cell, a gate of the first select transistor being coupled to a first line, and a gate of the second select transistor being coupled to a second line, the first line being electrically isolated from the second line, wherein each of the string units configures a first logical block, and when the first logical block has a defect, the information of a first defect logical block is stored in the memory cell array.