Patent ID: 6229733
Filing Date: 2001-05-08
Classification: G11C

Abstract:
A non-volatile memory cell for an integrated circuit, said memory cell comprising a metal oxide semiconductor field effect transistor (MOSFET) fabricated to read back a first logic level and comprising:a substrate,a drain diffused into said substrate,a source diffused into said substrate,a substrate channel disposed between a channel edge of said drain and a channel edge of said source;an insulating oxide layer disposed over said substrate doped with said drain and said source, said insulating layer having a predetermined thickness sufficient to prevent a gate oxide rupture from occurring during cell programming; anda polysilicon gate deposited into said insulating oxide layer over said substrate channel;wherein said drain further includes (i) a contact region connected to a conductor on which a programming voltage is provided during cell programming, and (ii) an elongated section disposed between said drain channel edge and said contact region so as to provide a predetermined ballast resistance effective to regulate the magnitude of programming current to a desired value when said programming voltage is applied to said conductor.