Patent ID: 6569735
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method for manufacturing non-volatile memory, comprising the following steps:forming an isolation region in a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; forming a first polysilicon layer on the first oxide layer; forming a patterned first silicon nitride layer on the first polysilicon layer; forming gate regions by using the patterned first silicon nitride layer as a mask to etch the first polysilicon layer and the first oxide layer; forming sources/drains in the substrate beside the gate region by ion implantation; forming a second oxide layer on the first silicon nitride layer and the substrate; removing a portion of the second oxide layer to expose an upper edge of the first silicon nitride layer; forming a second silicon nitride layer on the second oxide layer; removing portion of the second silicon nitride layer on the first silicon nitride layer, whereby the second silicon oxide layer on the first silicon nitride layer is exposed; removing the second oxide layer on the gate region; removing the first silicon nitride layer and the second silicon nitride layer by etching, whereby a portion of the second oxide layer on the sources/drains is removed; forming a second polysilicon layer on the substrate; removing portions of the second polysilicon layer on the isolation region and the second silicon oxide layer between two gate regions; sequentially forming a first dielectric material layer, a third polysilicon layer and a patterned hard mask layer on the second polysilicon layer and on the second oxide layer, wherein the patterned hard mask layer is in a direction almost perpendicular to that of the first polysilicon layer; etching the third polysilicon layer, the first dielectric material layer, the second polysilicon layer and the first polysilicon layer by using the patterned hard mask layer as a mask to define a gate structure; removing exposed first silicon oxide layer; etching the substrate by using the patterned hard mask layer and the second silicon oxide layer as mask to form recesses; removing exposed second silicon oxide layer; forming a second dielectric material layer to fill the recesses and cover the substrate and the hard mask layer; and etching further the second dielectric material layer until a surface of the substrate is exposed to form a spacer on a sidewall of the gate structure.