Patent ID: 6151244
Filing Date: 2000-11-21
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word lines each arranged extending in a row direction and in parallel to others;a plurality of first bit lines each arranged extending in a column direction and in parallel to others;a plurality of one transistor/one capacitor type memory cells arranged corresponding to crossing of said plurality of word lines and said plurality of first bit lines, units of two memory cells arranged repeatedly in the column direction, two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being periodically positioned differently, and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit, the bit line contacts and the memory capacitors being arranged in alignment in the row direction with the plurality of bit lines being the unit;a plurality of cell plate lines individually provided corresponding to the first bit lines and coupled to cell plate nodes of the memory cells on the corresponding first bit lines for transferring cell plate potentials to the cell plate nodes of the memory cells of corresponding first bit lines, the cell plate node being a capacitor electrode of a memory capacitor of the memory cell facing to a data storage node of the memory cell; andcell plate potential control circuit coupled to the cell plate lines for individually controlling the cell plate potentials on a cell plate line basis.