Patent ID: 7313676
Filing Date: 2007-12-25
Classification: G06F

Abstract:
1. An apparatus comprising: a single integrated register map to store up to M×N values to map M registers for N threads, a set of N values being associated with each of the M registers, wherein M and N are positive integers; a plurality of M sets of state bits, each set of state bits being associated with one of said M registers and to indicate which of any of the set of N values of the register map are valid for the associated one of said M registers for each thread and whether ones of said N sets of values have been written to during execution of a speculative thread; and recovery logic to, responsive to termination of said speculative thread, update one or more of the sets of state bits to indicate one of a plurality of states, such that it is to alter said state bits indicative of a one of the states to indicate another of the states based on which of a first thread and a second thread is determined to be non-speculative.