Patent ID: 6128704
Filing Date: 2000-10-03
Classification: G06F,Y02D

Abstract:
A cache DataRam of superscalar processor having multiple pipelines comprising:a plurality of banks for multiple data access requests from said multiple pipelines, said plurality of banks forming into one port ram cell structure;a bank selection signal generation circuitry for generating a bank selection signal representing on which bank a data requested by said pipeline is located in response to address signals and control signals inputted from each pipeline for data access;an address selection means for selecting an index address out of plurality of index addresses from said pipelines and outputting said selected index address as a valid pipeline index address in response to said bank selection signal;a decoding means for decoding said valid pipeline index address for each bank; anda hitway selection means for selecting a hitway signal out of hitway signals of said pipelines and outputting said selected hitway signal as a valid pipeline hitway signal, said hitway signals being generated by tag block for said each bank in response to said bank selection signal;wherein said control signal represents a size of said data requested by said each pipeline, a lower portion of said address signal of said pipeline and a validity of the pipeline operation.