Patent ID: 6874081
Filing Date: 2005-03-29
Classification: G06F

Abstract:
1. An apparatus for generating a sequential address for a branch instruction, the apparatus comprising: a multiplexor coupled to receive: (i) a most significant N-bit portion of a first program counter (PC), the most significant N-bit portion of the first PC locating a first set of bytes including the branch instruction within a memory, and (ii) a most significant N-bit portion of a second PC, the most significant N-bit portion of the second PC locating a second set of bytes in the memory, the second set of bytes contiguous to the first set of bytes and stored at a numerically higher address; and a circuit coupled to receive at least a first bit of a branch PC locating the branch instruction in the memory, the first bit being a most significant bit of the branch PC exclusive of the most significant N-bit portions of the branch PC, and wherein the first bit is coupled to be used as a selection signal for the multiplexor to select between one of the most significant N-bit portion of the first PC and the most significant N-bit portion of the second PC as an output, the circuit further including an inverter to receive the first bit and to invert the first bit as part of the output.