Patent ID: 8174477
Filing Date: 2012-05-08
Classification: G09G,G11C

Abstract:
1. A gate driver comprising: a shift register provided with a plurality of first output lines; first to second output repairing lines arranged across the plurality of first output lines; at least two clock transmission lines to transmit at least two clock pulses of different phases; first and second clock repairing lines arranged across the at least two clock transmission lines; and a first auxiliary stage connected to the first to second output repairing lines and to the first clock repairing line; a second auxiliary stage connected to the first to second output repairing lines and to the second clock repairing line; wherein the shift register includes a plurality of stages in a sequence that are each supplied with at least one of the at least two clock pulses transmitted through the at least two clock transmission lines and that each outputs the supplied at least one clock pulse as a corresponding scan pulse through a corresponding one of the plurality of first output lines; wherein the first auxiliary stage is connected to one end of the first output repairing line, one end of the second output repairing line, and the first clock repairing line; and wherein the second auxiliary stage is connected to another end of the first output repairing line, another end of the second output repairing line, and the second clock repairing line; wherein the first and second clock repairing lines are disconnected from the at least two clock transmission lines; wherein the first clock repairing line is connected to a clock transmission line when a first predetermined stage among the plurality of the stages is a disabled stage; wherein the first predetermined stage is disconnected from a first clock transmission line that supplies a clock pulse to the first predetermined stage when the first predetermined stage is a disabled stage, wherein the first predetermined stage is disconnected from the first clock transmission line by removing a transmission line which electrically connects the first clock transmission line to the first predetermined stage; wherein the second clock repairing line is connected to a clock transmission line when a second predetermined stage among the plurality of the stages is a disabled stage; wherein the second predetermined stage is disconnected from a second clock transmission line that supplies a clock pulse to the second predetermined stage when the second predetermined stage is a disabled stage, wherein the second predetermined stage is disconnected from the second clock transmission line by removing a transmission line which electrically connects the second clock transmission line to the second predetermined stage; wherein the first auxiliary stage is positioned right above a first stage of the stages; wherein the second auxiliary stage is positioned right under a last stage of the stages; wherein the last stage is a dummy stage which is not connected to gate line; wherein a full-down switching device provided in each of the first and second auxiliary stages is larger in size than a full-up switching device provided in each of the first and second auxiliary stages.