Patent ID: 6731143
Filing Date: 2004-05-04
Classification: H03K

Abstract:
A power-up circuit, comprising:a first PMOS transistor connected between the power supply and a first node, wherein a gate terminal of the first PMOS transistor is connected to a ground; a first voltage divider for dividing power upon a power up; a first NMOS transistor for driving an output of the first voltage divider upon power up and connected between the first node and the ground; an inverter comprising a plurality of PMOS transistors connected between the power supply and a second node, the invention further comprising a second NMOS transistor connected between the second node and the ground, a gate of the second NMOS transistor being connected to the plurality of the PMOS transistors, thereby inverting the potential of the first node; and a third NMOS transistor connected between the first node and the ground, wherein the third NMOS transistor is turned on by an output of the inverter, thereby preventing shifting faster than the potential of the first node.