Patent ID: 7548109
Filing Date: 2009-06-16
Classification: G09G,H02M

Abstract:
1. A voltage converter circuit for converting an input voltage and outputting a converted voltage, comprising first to eighth transistors and first to fifth capacitor elements, wherein: a drain and a gate of said first transistor are connected to a first terminal, and a source of said first transistor is connected to a first node; a drain of said second transistor is connected to said first terminal, a gate of said second transistor is connected to a second node, and a source of said second transistor is connected to said first node; a drain of said third transistor is connected to said first terminal, a gate of said third transistor is connected to said first node, and a source of said third transistor is connected to said second node; a drain of said fourth transistor is connected to said second node, a gate of said fourth transistor is connected to a third node, and a source of said fourth transistor is connected to a fourth node; a drain of said fifth transistor is connected to said second node, a gate of said fifth transistor is connected to a second terminal, and a source of said fifth transistor is connected to said fourth node; a drain of said sixth transistor is connected to said second node, a gate of said sixth transistor is connected to said fourth node, and a source of said sixth transistor is connected to said second terminal; a drain and a gate of said seventh transistor are connected to said second node, and a source of said seventh transistor is connected to said third node; a drain of said eighth transistor is connected to said second node, a gate of said eighth transistor is connected to said fourth node, and a source of said eighth transistor is connected to said third node; said first capacitor element is connected between a first control signal input terminal and said first node; said second capacitor element is connected between a second control signal input terminal and said fourth node; said third capacitor element is connected between a third control signal input terminal and said third node; said fourth capacitor element is connected between a fourth control signal input terminal and said second node; said fifth capacitor element is connected at least either between said second terminal and ground or between said first terminal and ground; and first to fourth control signals having different timings are input to said first to fourth control signal input terminals, respectively.