Patent ID: 6750499
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A self-aligned trench-type DRAM structure, comprising:a semiconductor substrate of a first conductivity type having an active region and two parallel first-type shallow-trench-isolation (STI) regions, wherein said active region is located between said two parallel first-type STI regions; a DRAM cell comprising a self-aligned trench region and a self-aligned transistor region being formed on said semiconductor substrate, wherein said self-aligned trench region comprises a deep-trench region and a second-type STI region being located in said active region outside of said deep-trench region and said self-aligned transistor region comprises a gate-stack region and a common-drain region; said deep-trench region being defined by a first sidewall dielectric spacer comprising: a trench capacitor being formed in a lower portion, a collar-oxide layer together with a capacitor-node connector being formed in a middle portion and a source conductive node acted as a dopant diffusion source being formed in an upper portion, wherein said trench capacitor comprises an upper capacitor node over a capacitor-dielectric layer being formed over a lower capacitor node in said semiconductor substrate; said gate-stack region comprising a gate-stack being defined by a third sidewall dielectric spacer formed over a sidewall of said self-aligned trench region and a common-source diffusion region of a second conductivity type formed by out-diffusion of said dopant diffusion source being formed in said active region under an inner side portion of said gate-stack; and said common-drain region being located outside of said gate-stack comprising a flat bed being formed by a heavily-doped drain diffusion region of said second conductivity type formed within a common-drain diffusion region of said second conductivity type in said active region and two first-type fifth raised field-oxide layers in said two parallel first-type STI regions, and a fourth sidewall dielectric spacer being formed over an outer sidewall of said gate-stack and on a portion of said flat bed.