Patent ID: 8629007
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A method of fabricating a gate in a Field Effect Transistor (FET), comprising: providing a substrate with an isolation area, an active area and a step height between the isolation area and the active area; forming at least one dummy gate above the isolation area and forming at least one dummy gate above the active area; depositing a sacrificial layer; exposing a portion of the dummy gates; removing the dummy gates, and a portion of the sacrificial layer leaving a remaining portion of the sacrificial layer to create a dummy gate opening above the isolation area and a dummy gate opening above the active area; depositing a high dielectric constant (high-k) film and depositing a metal film on the high-k film; planarizing the substrate wherein the metal film, the high-k film, and the remaining portion of the sacrificial layer are co-planar to form a first gate over the isolation area and a second gate over the active area; and removing the remaining portion of the sacrificial layer.