Patent ID: 8648441
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a multi-layered interconnect formed on said substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on said substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in said multi-layered interconnect; and a logic circuit formed in a logic circuit region on said substrate, which is a region different from said memory circuit region in a plan view, said capacitor element being configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect, said upper interconnect and said embedded electrode being configured by the same material in an integrated manner, at least one layer of said interconnect configuring said logic circuit is provided between said upper interconnect and said lower electrode, and the top surface of said upper interconnect, and the top surface of said interconnect configuring said logic circuit formed in the same interconnect layer with said upper interconnect, are aligned to the same plane, wherein said insulating layer of said multi-layered interconnect, having said capacitor element embedded therein, is provided in common with said insulating layer configuring said logic circuit, formed in the same layer with said capacitor element, and said insulating layer has a dielectric constant smaller than that of silicon oxide film.