Patent ID: 7657773
Filing Date: 2010-02-02
Classification: G06F

Abstract:
1. A clock distribution (CD) chip comprising: first and second input pins adapted to receive first and second input clock signals corresponding to either a differential input clock signal or two single-ended (SE) input clock signals; input buffer circuitry adapted to receive and handle the input clock signals from the input pins; clock generation and distribution circuitry adapted to receive a reference clock signal and one or more other clock signals from the input buffer circuitry and programmably generate (i) any of zero, one, or more zero-delay (ZD) clock signals based on the reference clock signal and (ii) any of zero, one, or more non-zero-delay (NZD) clock signals based on the one or more other clock signals, wherein the clock generation and distribution circuitry comprises: fanout circuitry adapted to generate an output clock signal for each of the ZD and NZD clock signals; a plurality of output pins adapted to present the output clock signals; a feedback pin adapted to receive one of the output clock signals presented at one of the output pins; and feedback buffer circuitry adapted to derive a feedback clock signal from the output clock signal presented at the feedback pin and provide the feedback clock signal to the clock generation and distribution circuitry for use in generating each ZD clock signal.