Patent ID: 6314494
Filing Date: 2001-11-06
Classification: G06F

Abstract:
A size configurable data buffer comprising:a controller bus, having address bits corresponding to mask, column, line, and TAG, generating a prefetch signal having a first and a second state;a SRAM circuit including,data cache memory registers,prefetch memory registers; andmasking circuitry, connected to the controller bus and SRAM circuit, outputting modified line address bits, including,a plurality of two-input AND gates, each AND gate receiving a line and a mask address bit, anda plurality of 2:1 multiplexers, receive a prefetch control line, each multiplexer receiving an output from the AND gates and the corresponding line address bit, outputting the modified line address bits when the prefetch signal is in the first state, and unmodified line address bits when the prefetch signal is in the second state.