Patent ID: 9207909
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. Polynomial circuitry for evaluating a polynomial having a plurality of terms, each term having a number of bit positions, said polynomial circuitry comprising: a plurality of groups of partial product generators, each of said groups of partial product generators corresponding to a single term in said plurality of terms and, in each one of said groups of partial product generators, each respective partial product generator in said one of said groups of partial product generators providing an output value for a respective single input bit position of said single term to which said one of said groups of partial product generators corresponds; adder circuitry for providing respective bit-slice sums, said adder circuitry comprising a plurality of respective groups of adders, each respective group of adders in said plurality of respective groups of adders including a number of adders equal in number to said plurality of terms and corresponding to one respective bit position in all of said plurality of terms, and summing output values of multiple ones of said partial product generators for said one respective bit position to provide said respective bit-slice sum having a respective bit-width, wherein resulting bit-slice sums are offset from one another, by less than their respective bit-widths, according to their respective bit positions, said plurality of groups of adders being equal in number to said number of bit positions; and a final adder that adds together said respective offset bit-slice sums to provide a final result.