Patent ID: 6523143
Filing Date: 2003-02-18
Classification: G11C

Abstract:
A memory testing apparatus for testing a memory, comprising:a pattern generator which outputs: an input address signal supplied to an address pin of the memory, an input test signal, including an input data signal, supplied to a data pin of the memory, and an expectation value data signal which is an expectation value data signal that is to be output, based on the input test signal, from the memory , as a response result from a normal memory device; a signal input-output unit which supplies the input test signal to the memory and receives an output data signal from the memory; a comparator which compares the output data signal with the expectation value data and outputs a defect-indicating data indicative of existence of a defective spot in the memory; a defective data storing memory which writes the defect-indicating data output from said comparator, to an address corresponding to the defective spot of the memory; and a failure history storing memory which stores failure history data including the input data signal when the defective spot is detected, wherein said pattern generator includes: an internal address generator which generates an internal address signal specifying an address based on a cell configuration inside the memory; an address converting unit which, based on a correspondence relationship between the cell configuration inside the memory and a pin configuration of the address pin, converts the internal address to the input address signal that is to be input to the address pin; a first address output unit which outputs to said defective data storing memory either the internal address signal or the input address signal; and a second address output unit which outputs to said failure history storing memory either the internal address signal or the input address signal.