Patent ID: 6477205
Filing Date: 2002-11-05
Classification: H04L

Abstract:
A digital communication system, comprising:a first communication device having m data output nodes and a clock output node; a second communication device having m data input nodes and a clock input node, wherein each of the m data input nodes corresponds to a different one of the m data output nodes, and wherein the clock input node corresponds to the clock output node; m data transmission lines coupled between corresponding data output and input nodes, and a clock transmission line coupled between the clock output and input nodes; wherein the second communication device comprises an input section including m+1 termination resistors, wherein each of m of the m+1 termination resistors is coupled between a different one of the m data input nodes and a power supply voltage level, and wherein one of the m+1 termination resistors is coupled between the clock input node and the power supply voltage level; wherein an electrical voltage level existing at a given data input node is substantially dependent upon an amount of electrical current flowing through the termination resistor coupled between the given data input node and the power supply voltage level; wherein an electrical voltage level existing at the clock input node is substantially dependent upon an amount of electrical current flowing through the termination resistor coupled between the clock input node and the power supply voltage level; wherein the first communication device comprises an output section coupled to receive n binary data signals and a binary clock signal, and wherein the output section is configured to: (i) drive each of the m data output nodes in one of p drive states dependent upon the n binary data signals and in response to the binary clock signal, and wherein n>m and p&gE;3, and wherein each of the p drive states used to drive a given data output node causes a different amount of electrical current to flow through the termination resistor coupled to the corresponding data input node such that a different electrical voltage level exists at the corresponding data input node in each of the p drive states, and (ii) drive the clock output node in one of q drive states dependent upon the binary clock signal, and wherein q&gE;2, and wherein each of the q drive states causes a different amount of electrical current to flow through the termination resistor coupled to the clock input node such that a different electrical voltage level exists at the clock input node in each of the q drive states; and wherein the input section is configured to: (i) produce the binary clock signal from the electrical voltage levels existing at the clock input node, and (ii) produce the n binary data signals from the electrical voltage levels existing at the m data input nodes in response to the binary clock signal.