Patent ID: 6848063
Filing Date: 2005-01-25
Classification: G06F

Abstract:
1. A memory system, comprising, a memory bus; a plurality of memory modules coupled to the memory bus, each memory module including: a memory array organized for access into a plurality of memory lines; a code array for storing error codes,including a distinct error code for each of the plurality of memory lines; error logic, coupled to the memory array and code array, for determining whether any specified memory line in the memory array is not consistent with the corresponding error code in the code array and generating a corresponding error detection signal; access logic for accessing memory lines in the memory array, receiving from the error logic the error detection signal, and initiating a remedial action when the error detection signal indicates that a specified memory line is not consistent with the corresponding error code in the code array; and a scheduler, coupled to the access logic, for initiating reading of the memory lines in the memory array in accordance with a memory scrubbing schedule; wherein each said memory module in the plurality of memory modules concurrently performs memory scrubbing in accordance with the memory scrubbing schedule.