Patent ID: 8760957
Filing Date: 2014-06-24
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: an array of memory cells; rows of word lines and columns of bit lines for accessing said array of memory cells; said array of memory cells being partitioned along a column direction into a first array portion and a second array portion; said first array portion having memory cells configured as single-level cells each storing one bit of data; said second portion having memory cells configured as multi-level cells each storing more than one bit of data; a set of switches one for each bit line; said columns of bit lines being partitioned by said set of switches into a first segment of bit lines corresponding to said first array portion and, a second segment of bit lines corresponding to said second array portion; said first segment of bit lines having first and second ends; said first ends being coupled adjacent to a set of read/write circuits for reading and writing in parallel a group of memory cells of said array; and said second ends being switchably connected to said second segment of bit lines via said set of switches for said second segment of bit lines to access said set of read/write circuits via said first segment of bit lines.