Patent ID: 6440826
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising the steps of:forming a silicon gate electrode, having an upper surface and side surfaces, overlying a silicon substrate with a gate dielectric layer therebetween, a sidewall spacer disposed adjacent to each side surfaces of the silicon gate electrode, exposed source/drain regions in the silicon substrate, and field oxide areas in the silicon substrate adjacent to the outer edges of the source/drain regions; implanting silicon (Si) ions into the field oxide areas; depositing a nickel (Ni) layer; heating to react the deposited Ni with underlying Si to form a nickel silicide layer on the silicon gate electrode, nickel suicide layers on the source/drain regions and nickel silicide extensions on the field oxide areas; removing unreacted Ni; and landing a contact on the nickel silicide extensions at a tolerance distance from the silicon gate electrode and a tolerance distance to the end of the nickel silicide extensions.