Patent ID: 7643346
Filing Date: 2010-01-05
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; and a plurality of memory cells on the semiconductor substrate, each of the memory cells has a memory cell transistor; wherein the memory cells form an array including serial connections of a plurality of the memory cell transistors, each of the memory cell transistors has a pair of source and drain regions formed in the semiconductor substrate, a channel region having upper surface and side surfaces laterally interposed between the source and drain regions, a tunnel insulator film on the upper surface of the channel region, a charge storage layer on the tunnel insulator film, a control dielectric film on the charge storage layer, a control electrode on the control dielectric film, a sideface dielectric film on the side surfaces of the channel region, and first and second sideface electrodes provided on the sideface dielectric film to oppose each other with the channel region being laid therebetween, wherein the first sideface electrode is shared between neighboring ones of the memory cell transistors which are serially connected together, and the second sideface electrode is shared between neighboring ones of the memory cell transistors which are serially connected together.