Patent ID: 6366612
Filing Date: 2002-04-02
Classification: H04L

Abstract:
An automatic equalizer comprising:a decision unit that subjects N estimated received signals to a receive code decision and outputs a decision result as a decision output signal; an impulse response arithmetic circuit that outputs impulse response signals in response to received signals; a demodulation point setting circuit that outputs a demodulation point setting signal in response to the impulse response signals, the demodulation point setting signal being operative to shift a demodulation point from a point where the absolute value of the impulse response signals is maximized; a filter coefficient output circuit that outputs a first filter coefficient group and a second filter coefficient group in response to the impulse response signals and the demodulation point setting signal, the first filter coefficient group corresponding to a postcursor component in the impulse response signals, and the second filter coefficient group corresponding to a precursor component in the impulse response signals; a transversal filter that estimates a postcursor component of the received signals in response to the decision output signal and the first filter coefficient group that outputs an estimated postcursor signal; a transmission signal sequence generator that produces N transmission signal sequences; an estimated precursor circuit that estimates a precursor component of the received signals in response to the second filter coefficient group and the N transmission signal sequences and outputs N estimated precursor signals; and an adder for adding the estimated postcursor signal and each of the N estimated precursor signals to output the N estimated received signals.