Patent ID: 7599209
Filing Date: 2009-10-06
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a resistive memory element coupled to a plate potential by a first terminal of the resistive memory element; a selection transistor having a first terminal coupled to a second terminal of the resistive memory element; a bit line coupled to a second terminal of the selection transistor and connectable to the resistive memory element via the selection transistor; a programming circuit operable to provide a programming voltage and to change a resistance of the resistive memory element during a programming operation, the programming circuit being connectable to the bit line and to the second terminal of the selection transistor via the bit line, wherein the programming circuit applies a programming signal via the bit line to the resistive memory element to transfer the resistive memory element into a low resistance state, and wherein the programming signal comprises at least one of a programming voltage and a programming current; and a regulator circuit coupled to the second terminal of the selection transistor and operable to provide a regulating current to or from the bit line to change a potential of the bit line in response to a change of the resistance of the resistive memory element caused by the programming circuit during the programming operation, wherein the regulator circuit and programming circuit are separately connectable to the bit line, wherein the regulator circuit comprises: a switch to selectively couple a regulator potential to the bit line depending on a regulate signal.