Patent ID: 6265911
Filing Date: 2001-07-24
Classification: G11C

Abstract:
A sample and hold circuit, comprising:a semiconductor having a field effect transistor device, such device including,a channel in the semiconductor,a first region in the semiconductor,a second region in the semiconductor,a front-gate disposed over the, channela back-gate in the semiconductor under the channel;said front-gate and said back-gate being configured to control a flow of carriers inthe semiconductor through the channel between said first region and said second region;a capacitor connected to one of said first and second regions, the other one of said first and second regions being configured for coupling to an input signal;a first switch, responsive to a sampling signal, to electrically connect an input signal invariant electrical potential between one of said first and second regions and said back-gate during a tracking phase and to, during a subsequent hold phase, electrically isolate said capacitor from the input signal and said back-gate from said first and second regions; anda second switch to electrically connect an input signal invariant potential between said front-gate and one of said first and second regions during the tracking phase to remove variations in resistance through said channel.