Patent ID: 6140226
Filing Date: 2000-10-31
Classification: H01L,Y10S

Abstract:
A method for forming an interconnect structure on the upper surface of a substrate having conductive regions comprising the steps of:forming over said substrate a first dielectric layer having a thickness corresponding to the thickness of an interconnect via,forming over said first dielectric layer a second dielectric layer having a thickness corresponding to the thickness of an interconnect wiring layer,forming a first hard mask layer over said second layer,forming a layer of resist over said first hard mask layer,patterning said layer of resist with a wiring pattern,patterning said first hard mask layer using said wiring-patterned layer of resist as a mask,transferring said wiring pattern into said second dielectric layer to form wiring cavities corresponding to said wiring pattern, while concurrently removing said wiring-patterned layer of resist,forming a third layer of liner material over said first hard mask layer and on the sidewalls and bottom of said wiring cavities,forming a layer of resist over said third layer,patterning said layer of resist with a via pattern,patterning said third layer using said via-patterned layer of resist as a mask,transferring said via pattern into said first dielectric layer to form via cavities corresponding to said via pattern, andfilling said wiring and via cavities with conductive material to make electrical contact to said conductive regions and to form said vias and said wiring pattern.