Patent ID: 7877651
Filing Date: 2011-01-25
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising: A. functional circuitry having data input leads and data output leads; B. a serial data input lead, a serial data output lead, a select input lead, and a clock input lead; C. test access port circuitry having a test data input lead connected with the serial data input lead, a test data output lead connected with the serial data output lead, a test mode select lead coupled with the select input lead, a test clock lead connected with the clock input lead, scan circuitry control output leads that include a capture select select lead and a capture-DR lead, and a data register connected in series between the test data input lead and the test data output lead; D. scan test port circuitry having a scan input lead connected to the serial data input lead, a scan output lead coupled with the serial data output lead, a scan enable input lead, a capture select input lead, a scan clock input lead, and a scan register connected between the scan input lead and the scan output lead, the scan register having functional data output and input leads connected to the functional circuitry data input and output leads; E. connection circuitry coupling the scan test port circuitry to the test access port circuitry, the connection circuitry having inputs connected to the scan circuitry control output leads, the select input lead, and the clock input lead, the connection circuitry having outputs connected to the scan enable input lead, the capture select input lead, and the scan clock input lead, the connection circuitry including a first multiplexer having a control input connected with the capture select select lead, an input connected with the select input lead, an input connected with the capture-DR lead, and an output connected with the capture select input lead.