Patent ID: 9156673
Filing Date: 2015-10-13
Classification: B81B,B81C,H01L

Abstract:
1. An apparatus, comprising: a via wafer including a main portion and an elongate arm having a first portion extending away from the main portion of the via wafer and a second portion extending about the main portion of the via wafer and separate from the main portion of the via wafer by a gap; and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the via wafer; an application specific integrated circuit (ASIC) having a first surface coupled to the elongate arm of the via wafer using a first electrical interconnect and a second surface opposite to the first surface, the second surface having a second electrical interconnect centrally located on the second surface to couple the ASIC to a substrate, wherein the elongate arm and the location of the second electrical interconnect are configured to protect the microelectromechanical layer from deformation or stress.