Patent ID: 6741491
Filing Date: 2004-05-25
Classification: G11C

Abstract:
An integrated dynamic memory, comprising:bit lines; word lines; a memory cell array having memory cells connected to said word lines for selecting said memory cells and to said bit lines for reading data signals from said memory cells; at least one global bit line running through said memory cell array but does not make direct contact with said memory cells; a voltage amplifier connected to one of said bit lines for amplification of a data signal of a respective memory cell, to be read from, to a first voltage level not sufficient for writing the data signal back to said respective memory cell read from, and said voltage amplifier further connected to said global bit line and outputs the data signal amplified to the first voltage level; and a read amplifier connected to said global bit line, said read amplifier amplifying the data signal from said respective memory cell read from to a second voltage level, the second voltage level being sufficient for writing the data signal back to said respective memory cell.