Patent ID: 8158456
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method of fabricating a stacked integrated circuit (IC) semiconductor die comprising: forming one or more recesses in a first semiconductor wafer, the first semiconductor wafer having CMOS devices formed thereon; filling the one or more recesses with conducting material to form one or more through-silicon vias in the first semiconductor wafer; forming one or more bonding contacts on a front-side of the first semiconductor wafer; attaching the front-side of the first semiconductor wafer to a carrier, exposing a back-side of the first semiconductor wafer, wherein the carrier provides mechanical support to the first semiconductor wafer in a subsequent back-side thinning process; thinning the back-side of the first semiconductor wafer until the one or more through-silicon vias are exposed and slightly protrude the back-side; and aligning and bonding the one or more through-silicon vias with corresponding one or more bonding contacts on one or more bonding surfaces on a second semiconductor die or wafer.