Patent ID: 8102496
Filing Date: 2012-01-24
Classification: G02F,G06F

Abstract:
1. An array substrate comprising: a plurality of gate lines extending in a first direction; a plurality of data lines extending in a second direction substantially perpendicular to the first direction, the intersecting directions of the data lines and gate lines defining a plurality of pixels; a plurality of thin-film transistors electrically connected to the gate lines and the data lines; a pixel electrode electrically connected to a thin-film transistor; a common voltage line extending in the second direction substantially parallel with the data lines; an insulation layer formed on the common voltage line; a common electrode formed in each of the pixels, electrically insulated from the pixel electrode, and electrically connected to the common voltage line, and a horizontal connection electrode disposed between adjacent common electrodes and electrically connecting the adjacent common electrodes to each other, wherein the common electrode is formed from a layer substantially the same as the pixel electrode on the insulation layer, wherein the horizontal connection electrode is formed from the layer substantially the same as the common electrode.