Patent ID: 6047003
Filing Date: 2000-04-04
Classification: H04B,H04J

Abstract:
A framing identification and timing signal extraction apparatus for a very small aperture terminal system, comprising:a clock signal divider for each dividing an input clock signal and an inverted delay clock signal into a predetermined number of signals to generate first and second dividing signals having a different frequency, generating an output enable signal and a write enable signal using the clock signal and a delay clock signal, and generating an output control signal for controlling output of a framing identification and timing (FIT) signal;a first memory for storing input data according to said first dividing signal and the write enable signal of the clock signal divider and outputting the stored data according to the output enable signal of the clock signal divider;a second memory for receiving the output data from the first memory, the control signal of the clock signal divider, and a transmission data as address signals, and outputting a corresponding state value to output a previously stored data according to the output data, the control signal and transmitted data; anda control logic unit for extracting a FIT synchronizing signal, FIT clock signal, and a FIT data in accordance with the output from the second memory and the control signal from the clock signal divider.