Patent ID: 7098094
Filing Date: 2006-08-29
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising the steps of: forming a plurality of CMOS polysilicon gate structures over a semiconductor body; forming a gate dielectric on said semiconductor body prior to forming the plurality of CMOS polysilicon gate structures such that said gate dielectric is located between said semiconductor body and said plurality of CMOS polysilicon gate structures; forming a layer of nickel over said semiconductor body including over said plurality of CMOS polysilicon gate structures; forming a capping layer over said layer of nickel, said capping layer comprising a material with an affinity for boron; then, annealing the semiconductor body to completely convert sold CMOS polysilicon gate structures into NiSi gate electrodes; and removing said capping layer and unreacted portions of said layer of nickel, wherein said capping layer attracts a significant amount of boron away from an interface with said gate dielectric in a PMOS transistor but does not attract a significant amount of arsenic away from an interface with said gate dielectric in an NMOS transistor during sold annealing step.