Patent ID: 7354827
Filing Date: 2008-04-08
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: defining an active region in a semiconductor substrate with an isolation layer; forming at least two channel trenches that cross the active region; covering the active region between the at least two channel trenches with a preliminary gate pattern, the preliminary gate pattern filling the at least two channel trenches and extending over a main surface of the semiconductor substrate; implanting impurity ions of a first conductivity type into the semiconductor substrate to form source regions in the active region at both sides of the preliminary gate pattern; covering the preliminary gate pattern by forming a first interlayer insulating layer on the semiconductor substrate; contacting the source regions through the first interlayer insulating layer with BC plugs; depositing a second interlayer insulating layer on the first interlayer insulating layer and the BC plugs; sequentially patterning the second interlayer insulating layer, the first interlayer insulating layer, and the preliminary gate pattern to form an inter-gate groove that exposes the active region between the at least two channel trenches and gate patterns separated by the inter-gate groove; and implanting impurity ions of the first conductivity into the active region exposed by the inter-gate groove to form a drain region; and implanting impurity ions of a second conductivity into the active region exposed by the inter-gate groove to form a channel impurity region beneath the drain region that is in contact with at least the sidewalls of the at least two channel trenches.