Patent ID: 6812128
Filing Date: 2004-11-02
Classification: H01L,Y10S

Abstract:
A method of manufacturing a multilayered wiring structured semiconductor device, comprising:forming a wiring on a semiconductor substrate; forming a first silicon oxide film on the semiconductor substrate and on the wiring; forming an interlayer insulating film composed of a material bearing a low specific inductive capacity on the first silicon oxide film over the semiconductor substrate, the interlayer insulating film having a thickness so as not to extend beyond a height of the first silicon oxide film formed on the wiring; forming a second silicon oxide film on the interlayer insulating film and on the first silicon oxide film formed on the wiring; planarizing the second silicon oxide film; patterning a resist on the second silicon oxide film by lithography; etching the second silicon oxide film and the first silicon oxide film with the resist as a mask, to form a hole that exposes the wiring; removing the resist by ashing after completion of said etching; and cleaning the semiconductor substrate after said removing the resist, wherein a thickness of the first silicon oxide film is selected dependent on a width of the wiring, a diameter of the hole, and an alignment displacement of said etching.