Patent ID: 7003423
Filing Date: 2006-02-21
Classification: G06F

Abstract:
1. An apparatus for transferring data between two clock domains based on a same clock source and having a predetermined frequency relationship comprising: a phase-locked loop circuit that receives a forwarded clock from a first clock domain and is operative to generate a plurality of clock phases; a dynamic phase alignment circuit that receives a data signal from the first clock domain and the plurality of clock phases, and is operative to generate a recovered clock based on one of the plurality of clock phases, retime the data signal to the recovered clock, and deserialize the retimed data signal for output as parallel data; a data realigner circuit that receives the parallel data and is operative to output the parallel data based on a core clock from a second clock domain; and a register that receives a reset signal and the core clock, and is operative to output the reset signal based on the core clock for input to the dynamic phase alignment circuit and the data realigner circuit.