Patent ID: 6577525
Filing Date: 2003-06-10
Classification: G11C

Abstract:
A resistance memory device, comprising:memory array comprising a plurality of row lines, a plurality of column lines, and a plurality of resistive elements, each resistive element connected to a row line and a column line, said resistive elements having one of a first resistance value which represents a first logical state and a second resistance value which represents a second logical state; a sensing circuit for sensing the resistance value of a selected resistance element, said sensing circuit comprising: a first capacitor and at least one second capacitor; a charging circuit for charging said capacitors to a predetermined voltage value; a reference resistance element; a first discharge circuit for discharging said first capacitor through said selected resistive element and a second discharge circuit for discharging said at least one second capacitor through said reference resistance element; and a comparison circuit for comparing a discharge characteristic of said first capacitor with a discharge characteristic of said at least one second capacitor.