Patent ID: 6747340
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A multi-level shielded multi-conductor interconnect bus comprising:a substrate; a first dielectric layer overlying and supported by at least a portion of said substrate; a plurality of parallel first level electrically conductive lines formed on said first dielectric layer; a first level electrically conductive shield formed in a spaced relation above said first level electrically conductive lines; a plurality of first level electrically conductive walls formed on said first dielectric layer, said first level electrically conductive walls extending parallel with said first level electrically conductive lines, each said first level electrically conductive wall including an upper section in contact along at least a portion thereof with a lower side of said first level electrically conductive shield; a plurality of parallel second level electrically conductive lines formed in a spaced relation above said first level electrically conductive shield; a second level electrically conductive shield formed in a spaced relation above said second level electrically conductive lines; and a plurality of second level electrically conductive walls formed above said first level electrically conductive shield, said second level electrically conductive walls extending parallel with said second level electrically conductive lines, each said second level electrically conductive wall including a lower section in contact along at least a portion thereof with an upper side of said first level electrically conductive shield and an upper section in contact along at least a portion thereof with a lower side of said second level electrically conductive shield; said first level electrically conductive lines and said first level electrically conductive walls being arranged in pattern wherein at least one of said first level electrically conductive walls is located between sets of said first level electrically conductive lines, each said set of first level electrically conductive lines including at least one of said first level electrically conductive lines; said second level electrically conductive lines and said second level electrically conductive walls being arranged in pattern wherein at least one of said second level electrically conductive walls is located between sets of said second level electrically conductive lines, each said set of second level electrically conductive lines including at least one of said second level electrically conductive lines.