Patent ID: 6730553
Filing Date: 2004-05-04
Classification: H01L

Abstract:
A method for strapping a gate structure in a periphery of a semiconductor device, the gate structure includes a polycrystalline silicon layer having a p-type strip abutting an n-type strip, the p-type strip and the n-type strip defining a length of the polycrystalline silicon layer, the method comprising:exposing the polycrystalline silicon layer substantially along the length; forming over the polycrystalline silicon layer a nonconductive stack that includes a stopping layer and a nonconductive layer, the stopping layer having a characteristic to stop an etching process once consumed by the etching process; etching the nonconductive stack to expose the polycrystalline silicon layer substantially along the length to form a trench; and filling the trench with a conductive stack having a silicide layer to reduce the vertical resistance of the gate structure and a conductive layer to reduce the horizontal resistance of the gate structure.