Patent ID: 6797606
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:(a) forming a low dielectric constant interlayer insulating film over a first main surface of a wafer; (b) forming a silicon oxide interlayer insulating film over the low dielectric constant interlayer insulating film constituting a first interlayer insulating film together with the low dielectric constant interlayer insulating film, which silicon oxide interlayer insulating film has a larger dielectric constant as compared with the low dielectric constant interlayer insulating film; (c) forming a first interconnection groove in the first interlayer insulating film; (d) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection groove; (e) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove; (f) removing both the first interconnection metal film and the first barrier metal film outside the first interconnection groove by chemical mechanical polishing; and thereafter (g) performing ammonia plasma treatment over the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film, which are thereby converted to a nitrided silicon oxide surface and a nitrided copper-containing surface, respectively; and thereafter (h) forming a copper diffusion barrier insulating film over the first main surface.