Patent ID: 7515158
Filing Date: 2009-04-07
Classification: G09G,H04N

Abstract:
1. A configurable memory control apparatus in communication with an array of memory devices for selectively writing and reading data from said array of memory devices and in communication with a processing system for receiving said data from and transferring said data to said processing system according to segment pattern definition data; said configurable memory control apparatus comprising: a configurable memory control device in communication with said array of memory devices to generate and transfer to selected blocks of said array of memory devices address, timing, and control signals necessary for selectively writing said data to and reading said data from said selected blocks of said array of memory devices according to segment pattern definition data; a plurality of channel configuration devices in communication with said configurable memory control device and in communication with said processing system via a control path, an arbiter device in communication between the memory control device and the plurality of channel configuration devices to determine a priority for said channel configuration devices at which said defined segments of data are to be selectively written to and read from said array of memory devices according to a priority defined by the segment pattern definition data.