Patent ID: 6097621
Filing Date: 2000-08-01
Classification: G11C,H01L

Abstract:
In a semiconductor memory device having a feature size F, an array architecture of memory cells having an area equivalent to 6F.sup.2, the array architecture comprising:a plurality of active areas defined in a semiconductor substrate, each active area including a first portion and a second portion separated from one another by a central portion,the active areas being arranged in alternating even and odd columns disposed in a column direction, the active areas within each even column and odd column being separated from one another by isolation structures, the central portion of the active areas of the even columns being aligned with the isolation structures of an adjacent odd column;a plurality of word lines disposed in a row direction that is generally perpendicular to the column direction, the word lines being arranged in adjacent word line pairs that include a first word line and a second word line, each first word line overlapping the first portion of active areas in the even columns and the second portion of active areas in the odd column, each second word line overlapping the second portion of active areas in the even columns and the first portion of active areas in the odd columns; anda plurality of first contacts coupled to the central portions of the active areas.