Patent ID: 6374393
Filing Date: 2002-04-16
Classification: G11C,H03K

Abstract:
A logic circuit for outputting logical function evaluation results in synchronization with a synchronization signal, comprising:a dual-rail type logic tree forming a path through which only one rail reaches a reference potential according to an input signal and realizing a desired logical function; a sensing latch unit having a first logic input node and a second logic input node receiving a first logic output and a second logic output of the dual-rail type logic tree, a first logic output node, a second logic output node, a sense amplifier which operates upon receipt of the synchronization signal indicating drive and finally sets the logic potentials of the first logic output and the second logic output at different first level and second level according to a difference of conduction resistances possessed by the first logic input and the second logic input which are input to the first logic input node and the second logic input node, a first switching means for short-circuiting the first logic output node and the second logic output node when receiving a synchronization signal indicating an idle stage, a second switching means for electrically connecting or disconnecting the first logic input node and the first logic output node according to the potential of a control terminal, a third switching means for electrically connecting or disconnecting the second logic input node and the second logic output node according to the potential of the control terminal, and a logic tree disconnection controlling means having a first setting means for setting the potential of the control node connected to the control terminals of the second switching means and the third switching means to a potential that at least enables the connection between two terminals to which the second and third switching means are connected at a stage including the idle stage where the logic has not been finally determined in the sense amplifier, and a second setting means for setting the potential of the control node at a potential that at least enables the disconnection between two terminals to which the second and third switching means are connected according to the first logic output node or the second logic output node at a stage where the logic is finally determined in the sense amplifier; and a set and reset latch unit for receiving the first logic output of the sensing latch unit at its set terminal, receiving the second logic output of the sensing latch unit at its reset terminal, and holding the logic output of the sensing latch unit for a period of one cycle of the synchronization signal.