Patent ID: 7675339
Filing Date: 2010-03-09
Classification: H03K,H03L

Abstract:
1. A system for generating a delayed clock signal of an input clock signal, said system comprising: a duty cycle measuring unit connected to receive said input clock signal, said duty cycle measuring unit being configured to compare the duty cycle of said input clock signal with a reference duty cycle to produce a duty cycle signal; and a delayed signal generating unit connected to said duty cycle measuring unit to receive said duty cycle signal, said delayed signal generating unit being configured to generate a delay polarity signal using said duty cycle signal, said duty cycle of said input clock signal and the duty cycle of a logic signal derived from a logic operation of said input clock signal and said delayed clock signal, said delayed signal generating unit being further configured to adjust the delay of said delayed clock signal using said delay polarity signal, wherein said delayed signal generating unit is configured to generate said delay polarity signal based on one of a first comparison and a second comparison in response to said duty cycle signal.