Patent ID: 9204379
Filing Date: 2015-12-01
Classification: H04J,H04L,H04W

Abstract:
1. An apparatus comprising: at least one processor configured to receive a plurality of pilots in a plurality of time intervals, the plurality of pilots carrying different sets of bits for information sent in the pilots, each set including some or all bits of the information, and to perform detection to recover a set of bits sent in each of the plurality of pilots, wherein a first pilot carries a first set of bits of the information, wherein a second pilot carries a second set of bits of the information, the second set of bits being different from the first set of bits, wherein a third pilot carries all bits of the information, and wherein the first set of bits of the first pilot and the second set of bits of the second pilot are non-overlapping sets of bits of the information; and a memory coupled to the at least one processor.