Patent ID: 7447872
Filing Date: 2008-11-04
Classification: H04L

Abstract:
1. A system adapted to enable any processor in a processing engine having a plurality of processors to communicate directly with any other processor of the processing engine, wherein the system is arranged internal to an intermediate network station, the system comprising: a unidirectional control plane communication path internal to the intermediate network station separate from a unidirectional data plane path internal to the intermediate network station, wherein the unidirectional control plane communication path is configured to accommodate control information flow among the plurality of processors, the control plane further configured to pass the control information flow in a direction opposite the direction of data flow among the processors on the unidirectional data plane path; and at least one inter-chip communication (ICC) interface logic circuit coupled to the unidirectional control plane communication path and associated with the plurality of processors, the ICC interface logic circuit configured to create a multi-bit ICC message in response to an ICC request issued by any source processor and forward the multi-bit ICC message over the unidirectional control plane communication path to any destination processor of the processing engine, wherein the ICC interface logic circuit associated with the plurality of processors is contained on one of an application specific integrated circuit (ASIC) and data feeder device of the processing engine, wherein the plurality of processors are arrayed into multiple rows and columns, and wherein each row of processors is organized as a cluster.