Patent ID: 7339241
Filing Date: 2008-03-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor structure located over a dielectric, wherein the semiconductor structure includes: a gate structure running generally in the first horizontal direction over the plurality of fin portions, wherein the gate structure has a first current electrode side sidewall and a second current electrode side sidewall; wherein each fin portion of the plurality of fin portions includes a first location of a plurality of locations where the first current electrode side sidewall overlies the fin portion; wherein the first current electrode portion includes a plurality of gate adjacent areas, wherein each gate adjacent area is defined as running in a second horizontal direction from a first location of the plurality of first locations, the second horizontal direction being orthogonal to the first horizontal direction; a plurality of contacts electrically contacting the first current electrode portion, each contact of the plurality of contacts has a base, wherein the base of each contact of the plurality of contacts is located over an area of the first current electrode portion between the areas of two adjacent gate adjacent areas of the plurality of gate adjacent areas; each fin portion of the plurality of fin portions includes a second location of a plurality of second locations where the second current electrode side sidewall overlies the fin portion; the second current electrode portion includes a second plurality of gate adjacent areas, wherein each gate adjacent area of the second plurality of gate adjacent areas is defined as running in a second horizontal direction from a second location of the plurality of second locations; and a second plurality of contacts electrically contacting the second current electrode portion, each contact of the second plurality of contacts has a base, wherein the base of each contact of the second plurality of contacts is located over an area of the second current electrode portion between two adjacent gate adjacent areas of the plurality of gate adjacent areas; and the plurality of electrical contacts is horizontally staggered with the second plurality of electrical contacts.