Patent ID: 8234555
Filing Date: 2012-07-31
Classification: H03M

Abstract:
1. A decoding apparatus for decoding an LDPC (Low Density Parity Check) code received in: a first format expressed by a first original parity check matrix having a first structure obtained by combining a plurality of first configuration matrixes including a P×P unit matrix, a P×P semi unit matrix obtained by setting the value of each of one or more matrix elements of said P×P unit matrix from 1 to 0, a P×P shift matrix obtained as a result of carrying out a cyclic shift operation on said P×P unit matrix or said P×P semi unit matrix, a P×P sum matrix obtained by carrying out a matrix addition operation on at least two of said P×P unit matrix, said P×P semi unit matrix and said P×P shift matrix and a P×P zero matrix or expressed by a first post-rearrangement matrix obtained by rearranging at least one row and one column in said first original parity check matrix as a matrix having said first structure where notation P denotes an integer; or a second format expressed by a second original parity check matrix having a second structure obtained by combining a plurality of second configuration matrixes including a Q×Q unit matrix, a Q×Q semi unit matrix obtained by setting the value of each of one or more matrix elements of said Q×Q unit matrix from 1 to 0, a Q×Q shift matrix obtained as a result of carrying out a cyclic shift operation on said Q×Q unit matrix or said Q×Q semi unit matrix, a Q×Q sum matrix obtained by carrying out a matrix addition operation on at least two of said Q×Q unit matrix, said Q×Q semi unit matrix and said Q×Q shift matrix and a Q×Q zero matrix or expressed by a second post-rearrangement matrix obtained by rearranging at least one row and one column in said second original parity check matrix as a matrix having said second structure where notation Q denotes an integer having a non-unity measure F common to said integers Q and P, said apparatus including a computer programmed to decode received values each obtained as a result of receiving said LDPC code in said first or second format, said computer being programmed to perform at least F check-node processes carried out concurrently as processes of F check nodes respectively or F variable-node processes carried out concurrently as processes of F variable nodes respectively.