Patent ID: 7319631
Filing Date: 2008-01-15
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory bank groups, wherein each group includes a plurality of memory banks arranged in a stacked-bank architecture; a pre-decoder unit comprising a plurality of pre-decoders configured to decode a row address signal to generate a pre-decoded row address signal corresponding individually to each of the memory banks associated with the pre-decoded row address signal; and an output buffer unit comprising a plurality of output buffers, each configured to enable the pre-decoded row address signal in response to a corresponding one of a plurality of enable signals to enable a decoded row address signal, wherein each of the memory banks comprises a main decoder unit configured to generate a word line enable signal and a word line boosting signal in response to the decoded row address signal to individually select one of the memory banks associated with the decoded row address signal.