Patent ID: 6020838
Filing Date: 2000-02-01
Classification: H03M

Abstract:
A method for constructing a linear error correction circuit for use in a multi-bit delta-sigma converter, the method comprising:applying an analog waveform to the delta-sigma converter, wherein the delta-sigma converter generates output digital signals representative thereof;recording a plurality of the output digital signals;generating linearity error information from the recorded plurality of output digital signals, wherein said generating linearity error information includes generating specific linearity errors a(m) and generating a net linearity error E from the recorded plurality of output digital signals;calculating linearity error correction coefficients c(m) in response to the linearity error information, wherein said linearity error correction coefficients c(m) are generated by computing the matrix equation:c=(A.sup.T A).sup.-1 (A.sup.T E)where c is a column vector comprising the correction coefficients c(m); A is a 2 dimensional matrix comprising the specific linearity errors a(m); and E is a column vector comprising a net linearity error; andconstructing the linear error correction circuit using said linearity error correction coefficients c(m).