Patent ID: 6818998
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A stacked chip package comprising:a substrate having a mounting surface which includes a plurality of bonding pads; a first semiconductor chip disposed over the mounting surface of the substrate, the first semiconductor chip having an active surface that includes a plurality of first electrode pads; a second semiconductor chip disposed over the active surface of the first semiconductor chip, the second semiconductor chip having an active surface that includes a plurality of second electrode pads; a plurality of first bonding wires that electrically connect the first electrode pads of the first semiconductor chip to the bonding pads of the substrate; and a plurality of second bonding wires that electrically connect the second electrode pads of the second semiconductor chip to the bonding pads of the substrate; wherein the second semiconductor chip includes trenches formed on a lower surface opposite to the active surface of the second semiconductor chip, wherein the trenches provide a space that allows the plurality of first bonding wires to be electrically connected to the plurality of first electrode pads of the first semiconductor chip and further wherein a metal layer is deposited on the entire lower surface of the second semiconductor chip.