Patent ID: 7227255
Filing Date: 2007-06-05
Classification: H01L

Abstract:
1. A semiconductor device having a plurality of interconnect lines arranged in parallel with each other and having adjoining interconnect lines isolated by an insulator, wherein said insulator between the interconnect lines, comprises: a sidewall insulating layer formed at one side surface of two adjoining interconnect lines and having an approximately ¼ circular sectional shape; and an insulating film formed between said sidewall insulating layer and said interconnect line and having a dimension in the direction of separation of said sidewall insulating layer and said interconnect line defined by the film thickness; a plurality of memory transistors arranged in an array; and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, arranged extending in a row direction, and repeating in a column direction, two adjoining word lines being isolated by: a sidewall insulating layer formed at a side surface of one word line and having an approximately ¼ circular sectional shape; and an insulating film formed between said sidewall insulating layer and said word line and having a dimension in the direction of separation of said sidewall insulating layer and said word line defined by the film thickness, wherein said plurality of word lines include: