Patent ID: 6532173
Filing Date: 2003-03-11
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device, comprising:a virtual-ground memory array which includes a plurality of nonvolatile memory cells and sub-bit lines connected to the nonvolatile memory cells; first and second selection lines; first and second selection transistors which become conductive in response to activation of the first selection line; a third selection transistor which become conductive in response to activation of the second selection line; a first main bit line which is coupled to and supplies a drain potential to a sub-bit line situated on a drain side of a selected memory cell through the first selection transistor; a second main bit line which is coupled to and supplies a source potential to a sub-bit line situated on a source side of the selected memory cell through one of the second selection transistor and the third selection transistor; and a third main bit line which is coupled to a sub-bit line adjacent to said sub-bit line situated on the drain side of the selected memory cell through another one of the second selection transistor and the third selection transistor, and is coupled to a potential substantially the same as the drain potential.