Patent ID: 6594809
Filing Date: 2003-07-15
Classification: G06F,H01L

Abstract:
A method of forming an integrated circuit on a chip, comprising the steps of:(A) laying out a plurality of electrical modules on said chip, at least certain of said modules being defined by standard layout cells forming part of a library of said cells; (B) establishing the routing of conductors on said chip connecting said modules; (C) laying out a plurality of filler cells on said chip, at least certain of said cells containing a diode circuit for discharging a residual electrical charge present in an adjacent one of said conductors and constituting an antenna rule violation, each of said diode circuits comprising two diodes unconnected to each other; (D) identifying antenna rule violations based on routing of the conductors performed in step (B); and (E) correcting said antenna rule violations by selectively connecting said diodes in the diode circuits laid out as filler cells in step (C) with each other and with adjacent ones of said conductors violating said antenna rules.