Patent ID: 8526147
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. A triggering circuit for an SCR ESD protection device that includes a gate and defines a PNP structure with a base region, and is operable to protect a protected circuit, comprising an avalanche diode with breakdown voltage above the normal operating voltage of the protected circuit, a first reference voltage node operable to control the voltage on the base region of the PNP structure, and a second reference voltage node operable to control the voltage on the gate of the SCR ESD protection device, wherein the avalanche diode is connected in series with a first resistor between a high voltage pad and ground and the first reference voltage node is defined between the avalanche diode and the resistor, further comprising a transistor that includes an anode, a cathode and a control electrode, wherein the first reference voltage node is connected to the control electrode, wherein the transistor comprises an NMOS transistor connected in series with a current path transistor that is connected to the high voltage pad, wherein the current path transistor comprises a first PMOS transistor connected with its drain to the drain of the NMOS transistor, wherein the gate of the first PMOS transistor is biased to keep the first PMOS transistor on during normal operation, wherein the gate of the first PMOS transistor is connected to the first reference voltage node through a second PMOS transistor that is connected with its source to the gate of the first PMOS transistor and with its drain to a reference voltage.