Patent ID: 7184946
Filing Date: 2007-02-27
Classification: G06F

Abstract:
1. A co-simulation system for design verification of an electronic circuit, comprising: a high-level modeling system (HLMS); wherein the HLMS is a software tool executable on a computing anangement; a boundary-scan interface coupled to the high-level modeling system and configured to translate HLMS-issued commands to signals compliant with a boundary-scan protocol; a re-configurable hardware platform coupled to the boundary-scan interface; a translator coupled to the boundary-scan interface, implemented on the re-configurable hardware platform, and configured to translate input signals compliant with the boundary-scan protocol to signals compliant with a second protocol; a first component instantiated within a wrapper component, wherein the wrapper component is coupled to the translator and is configured to transfer input signals of the second protocol to the first component; and a second component co-simulated by the HLMS in software while the first component is co-simulated on the reconfigurable hardware platform; wherein the HLMS-issued commands include at least one command that forces input co-simulation data from the second component to the first component, and/or at least one command that extracts output co-simulation data from the first component for input to the second component.