Patent ID: 6195762
Filing Date: 2001-02-27
Classification: G11C

Abstract:
An integrated circuit, comprising:an array of memory cells;storage circuits coupled to the array;a write circuit coupled to the memory cells and operable to receive initial test data and mask data;a control circuit coupled to the array and to the write circuit, the control circuit operable to enable the write circuit to write the initial test data to the cells, to receive an address of one of the cells, the addressed cell being a dormant redundant cell, to enable the write circuit if the addressed cell is dormant to write the mask data to the storage circuit coupled to the cell such that the storage circuit stores the mask data, and to allow reading of the cell such that, if the cell is dormant, then the storage circuit provides as a read value the stored mask data, and such that, if the cell is live, then the storage circuit provides as the read value data that is stored in the cell.