Patent ID: 6166969
Filing Date: 2000-12-26
Classification: G11C,H03K

Abstract:
A level shifter circuit comprising:first and second level ascending/descending means for outputting first and second output signals by descending a high logic level of an input signal and an inverse signal and by ascending a low logic level after an input signal and a reverse input signal are respectively inputted; andsense amplifying means for amplifying a level difference between the first and second level ascending/descending means and for generating a third output signal with a regular level,wherein the first level ascending/descending means includes:first means for outputting the first output signal by descending the high logic level of an input signal and by ascending the low level after a voltage of the high logic level of the input signal is applied as the supply voltage,second means for outputting the first output signal by descending the high level of the input signal and by ascending the low level after the voltage of the high logic level of the third output signal is applied as the supply voltage,first pull-up means for generating the first output signal by responding to the input signal of the high logic level after the voltage of the high logic level of the input signal is applied as the supply voltage, andfirst pull-down means connected to a ground voltage and for generating the first output signal by responding to the input signal of the low logic level,wherein the first pull-up means includes a first NMOS transistor with a source connected to a first output voltage generating terminal, a drain in which the voltage of the high logic level of the input signal is applied as the supply voltage, and a gate in which the input signal is applied.