Patent ID: 8816449
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a substrate comprising a well region and a surface region; an isolation region within the well region of the substrate; a gate insulating layer overlying the surface region of the substrate; a first source/drain region and a second source/drain region within the well region of the substrate; a channel region between the first source/drain region and the second source/drain region within the well region of the substrate and within a vicinity of the gate insulating layer; a gate layer overlying the gate insulating layer and coupled to the channel region; sidewall spacers on edges of the gate layer to isolate the gate layer; a local interconnect layer overlying the surface region of the substrate, the local interconnect layer having an edge region extending within a vicinity of the first source/drain region; a contact layer on the first source/drain region and contacting the edge region of the local interconnect layer, the contact layer having a portion abutting a portion of the sidewall spacers; a first silicide layer overlying the contact layer and the local interconnect layer; a second silicide layer overlying the gate layer; and a diffusion junction region extending from the first source/drain region in the substrate, the diffused junction region being derived from at least impurities from the contact layer.