Patent ID: 6344760
Filing Date: 2002-02-05
Classification: G11C

Abstract:
A sense amplifier drive circuit comprising:a sense amplifier that amplifies data carried on a bit line and a bit line bar; a sense amplifier drive unit that selectively applies an overdrive voltage or an internal power supply voltage to the sense amplifier; and a control signal generator that logically combines a sense amplifier enable bar signal and a refresh enable signal, and generates a plurality of control signals to control the sense amplifier drive unit for read, write, and refresh operations, wherein said plurality of control signals prevent application of the overdrive voltage during the refresh operation, wherein the signal generator comprises: first and second inverters, each that inverts the sense amplifier enable bar signal; a delay circuit that delays an output signal from the second inverter for a predetermined time; a third inverter that inverts an output signal from the delay circuit; a first NOR gate that performs a NOR operation to a combination of an output signal from the third inverter and the sense amplifier enable bar signal; a fourth inverter that inverts an output from the second inverter; a fifth inverter that inverts an output signal from the first NOR gate; and a logic circuit that logically combines an output signal from the fourth inverter, an output signal from the fifth inverter and the refresh enable signal, to output the plurality of control signals.