Patent ID: 6108238
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array in which memory cell units having one or more reprogrammable nonvolatile memory cells are arranged in an array;a word line commonly connected to a same row of said one or more memory cells of said memory cell array;a data line commonly connected to a same column of said memory cell units of said memory cell array;a sequence control circuit for controlling a sequence operation which reprogram data of one or more selected memory cells by a first operation for applying a first voltage to reprogram data of said selected memory cells, and a second operation for verifying reprogrammed state of data to said selected memory cells to which said first voltage is applied;a voltage application circuit for applying said first voltage higher than a power supply voltage to a selected word line corresponding to a memory cell to be data reprogrammed in a first period which corresponds to at least partial period during a period of said first operation; andhigh voltage generating circuit for generating said first voltage which is supplied to an output node of said high voltage generating circuit and applied to said selected word line by connecting said output node to said selected word line, whereinboth in said first period and in said second period corresponding to at least a part in periods which exclude said first period during said sequence operation, said high voltage generating circuit supplies said first voltage higher than a power supply voltage to said output node, andin a second period, said output node is not connected to said word line, and a setting voltage of a voltage level of said first voltage which is equal to a voltage level of said output node is set to a voltage different from a setting voltage of a voltage level in said first period.