Patent ID: 8928074
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A vertical junction field effect transistor (JFET) semiconductor device comprising: an n-type semiconductor substrate electrically coupled to a drain electrode of the JFET semiconductor device; a layer of n-type semiconductor material above the substrate; one or more gate regions of p-type semiconductor material on the layer of n-type semiconductor material, each of the one or more gate regions having a graded dopant concentration and being electrically coupled to a gate electrode of the JFET semiconductor device, the gate regions of p-type semiconductor material having a lower surface adjacent the layer of n-type semiconductor material and an upper surface opposite the lower surface, wherein the dopant concentration in a lower portion of the gate regions of p-type semiconductor material adjacent the lower surface is less than the dopant concentration in an upper portion of the gate regions of p-type semiconductor material adjacent the upper surface, wherein the graded dopant concentration varies either in: a) a continuous manner between the lower surface and the upper surface of the gate regions or b) in a stepped manner over a number of discrete doping levels to approximate a continuous doping profile between the lower surface and the upper surface of the gate regions.