Patent ID: 6026055
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A burst page access unit for a semiconductor memory device, said semiconductor memory device having a plurality of memory cell arrays for storing bit data therein and a select circuit for selecting the bit data stored in said memory cell arrays, comprising:row decoder configured to decode a row address signal from an address input line in response to a first strobe signal to select a desired one of said memory cell arrays;internal address generator configured to increment a column address signal from said address input line by one in response to a clock signal to generate an internal column address signal;column decoder coupled to said internal address generator, and configured to decode the internal column address signal to control said select circuit to select a desired one of memory cells in the memory cell array selected by said row decoder; andoutput circuit coupled to said select circuit and configured to output the bit data selected by said select circuit externally.