Patent ID: 6566698
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A ferroelectric-type nonvolatile semiconductor memory comprising;(A) a bit line, (B) a transistor for selection, (C) memory units in the number of N, each memory unit comprising memory cells in the number of M wherein N&gE;2 and M&gE;2, and (D) plate lines in the number of MÃ—N, in which the memory units in the number of N are stacked through an insulating interlayer, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, the first electrodes are in common in each memory unit, and the common first electrode is connected to the bit line through the transistor for selection, and the second electrode of the m-th memory cell in the n-th memory unit is connected to the [(nâˆ’1)M+m]-th plate line wherein m=1, 2 . . . M and n=1, 2 . . N.