Patent ID: 8804454
Filing Date: 2014-08-12
Classification: G11C

Abstract:
1. A word line selection circuit comprising: a final stage row decoder that receives first and second pre-decode signals, generates a decode signal, and has a control output node, first and second power supply nodes, and an inverter circuit that operates with a first power supply voltage, drives a word line, and has an input node connected to the control output node supplied with the decode signal, wherein the final stage row decoder comprises: a variable resistance element coupled between the first power supply node and the control output node, the first power supply node supplied with the first power supply voltage, the variable resistance element responding to the first pre-decode signal, first and second transistors coupled in series between the control output node and the second power supply node, the second power supply node supplied with a second power supply voltage, the first transistor having a gate terminal supplied with the first pre-decode signal, the second transistor having a gate terminal supplied with the second pre-decode signal, wherein each of the first and second pre-decode signals having a voltage range between the second power supply voltage and a third power supply voltage, the third power supply voltage being less than the first power supply voltage.