Patent ID: 9053677
Filing Date: 2015-06-09
Classification: G09G

Abstract:
1. A display panel, comprising: a display area; and a gate driver configured to receive a plurality of clock signals comprising a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage, each of the first stage and the second stage configured to receive only one clock signal of the plurality of clock signals and respectively apply a first gate voltage and a second gate voltage to the display area, the gate driver integrated on a substrate, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock bar signal, the first stage discharges the first gate voltage based on the first clock signal and a first transfer signal, and the second stage outputs the first transfer signal based on the second clock bar signal, and wherein the first stage is configured to receive a first low voltage and a second low voltage lower than the first low voltage and receive a second transfer signal and a third transfer signal from two different stages other than the first stage and the second stage, respectively, and the first gate voltage is the first low voltage.