Patent ID: 9214925
Filing Date: 2015-12-15
Classification: H03K

Abstract:
1. A clock gated circuit comprising: a pulse generator driven by a first power supply voltage and configured to receive a clock signal and to generate a pulse and an inverted pulse with a level of the first power supply voltage; and a pulse level shifter driven by a second power supply voltage higher than the first power supply voltage and configured to receive the pulse and the inverted pulse with the first power supply level and to convert a level of the pulse in response to an enable signal, wherein the pulse level shifter comprises: a first PMOS transistor connected between the second power supply voltage and a current path node and having a gate connected to an inverted conversion node; a second PMOS transistor connected between the second power supply voltage and an inverted current path node and having a gate connected to a conversion node; a first inverter connected between the current path node and a bias node and configured to invert the pulse and to output the inverted result to the conversion node; a second inverter connected between the inverted current path node and a ground terminal and configured to invert the inverted pulse and to output the inverted result to the inverted conversion node; and an NMOS transistor connected between the bias node and the ground terminal and having a gate connected to receive the enable signal, wherein a terminal of the first inverter receives a ground voltage from the ground terminal when the enable signal is activated but does not receive the ground voltage from the ground terminal when the enable signal is deactivated, and wherein a terminal of the second inverter receives the ground voltage regardless of whether the enable signal is deactivated or activated, wherein an active interval of the enable signal is longer than a half period of the clock signal.