Patent ID: 6320964
Filing Date: 2001-11-20
Classification: G06F,H04L

Abstract:
A cryptographic accelerator comprising:a select circuit; anda plurality of buses coupled to the select circuit, of the plurality of buses includea first bus having signal lines arranged to perform an initial permutation operation in accordance with a symmetric key function,a second bus having signal lines arranged to perform a first permuted choice operation in accordance with the symmetric key function in order to modify contents of an original key by producing a first data block and a second data block,a third bus having signal lines arranged to perform a second permuted choice operation in accordance with the symmetric key function in order to modify the first data block and the second data block to produce a key block, the key block being one of a plurality of keys used to iteratively encrypt incoming information, anda fourth bus having signal lines arranged to perform a one-bit right shift on a bit representation of the incoming information.