Patent ID: 6133109
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method of manufacturing a storage electrode for a DRAM cell capacitor, the storage electrode being formed on an interlayer insulating layer and being electrically connected to a pad electrode formed on a semiconductor substrate through a contact hole in the interlayer insulating layer, the method comprising the steps of:forming a conductive layer comprising amorphous silicon over the interlayer insulating layer;forming a photoresist pattern over the conductive layer to define first and second regions on the conductive layer;within the second region, converting the conductive layer into polysilicon;etching the conductive layer to form the storage electrode having sidewalls, an upper surface, and a polysilicon edge portion proximate the joining of the upper surface and sidewalls; andforming an HSG silicon layer over the upper surface and sidewalls of the storage electrode, wherein the HSG silicon layer is not formed over the polysilicon edge portion.