Patent ID: 6125418
Filing Date: 2000-09-26
Classification: G06F

Abstract:
A computer system comprising:at least one processor;a bus bridge coupled to said processor; an input/output bus coupled to said bridge, said bus having a plurality of slots for communicating with input/output devices that may receive configuration cycle signals;a connector adapted to be connected to an intelligent input/output card, said connector being connected to receive interrupt signals from input/output devices connected to said input/output bus;a circuit connected to said connector for disabling the configuration cycle signals for at least some of said input/output devices whose interrupt signals have been connected to said connector, when said card is connected to said connector; andsaid circuit includes a plurality of transistors connected to receive address signals on one terminal, the gate of each transistor being connected to said connector such that signals from said connector can control the conduction of said transistor and thereby determine whether one of said devices in one of said slots receives a configuration cycle signal.