Patent ID: 7469321
Filing Date: 2008-12-23
Classification: G06F

Abstract:
1. A multiprocessor computer system, comprising: a plurality of processing nodes and a plurality of dynamic cache coherency regions using caches associated with said processing nodes, and having a supervisor software and cache controller logic in said processing nodes controlling software-initiated movement of software processes between said plurality of cache coherency regions to delay any need for purging by changing coherency mode bits without immediately requiring a selective purging of cache contents in one or more of said processing nodes that are part of a cache coherency region being changed and when moving a software process between two distinct sets of processing nodes a cache line cannot be marked as shared in two separate coherency regions, and when said supervisor software program is moving a coherency region from one distinct set of old processing nodes to another distinct set of new processing nodes it is leaving behind old cache entries for the coherency region on old nodes and ensures that these old cache entries will be seen by incoming storage requests originating from new processing nodes and that cache entries for main storage addresses in the new processing nodes will not be established until the old entries are invalidated.