Patent ID: 6480422
Filing Date: 2002-11-12
Classification: G11C,H01L

Abstract:
An integrated circuit comprising:a bit line; and a bank of memory cells, wherein the bank of memory cells comprises: a diffused bit line that is continuous between a first end and a second end in a substrate; a diffused source line in the substrate; a plurality of memory cells formed in and on the substrate, wherein portions of the diffused bit line and the diffused source line form drain/source regions of the memory cells; a first bank select device that is between the bit line and the first end of the diffused bit line, wherein when activated, the first bank select device conducts a current between the bit line and the first end of the diffused bit line; and a second bank select device that is between the bit line and the second end of the diffused bit line, wherein when activated, the second bank select device conducts a current between the bit line and the second end of the diffused bit line.