Patent ID: 7916532
Filing Date: 2011-03-29
Classification: G11C

Abstract:
1. A memory array comprising: a plurality of memory cells; and a plurality of array bitlines, each of the plurality of memory cells coupled to a unique one of the plurality of array bitlines, each odd bitline is coupled to a unique recovery transistor which is configured to be coupled to a first voltage and a second voltage, each even bitline is coupled to a unique recovery transistor which is configured to be coupled to the first voltage and a third voltage, the recovery transistors are configured to be coupled to an unselected bitline and are configured to be active during a write operation and a recovery operation, the recovery transistors are configured to be coupled to a selected bitline and are configured to be active during the recovery operation, and the recovery transistors are configured such that unselected bitlines are configured to be coupled to the first voltage during a write operation, the first voltage sufficient to prevent parasitic coupling between the selected bitlines and unselected bitlines during the write operation.