Patent ID: 8629449
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A display, comprising: a substrate including a first region, a second region, and a third region; a plurality of signal wires disposed in the first region on the substrate; a first gate electrode disposed in the second region on the substrate; a second gate electrode disposed in the third region on the substrate; a gate insulating layer disposed on the signal wires, the first gate electrode, and the second gate electrode; a first semiconductor layer disposed in the first region of the gate insulating layer and including a first source/drain region doped with a p-type impurity; a second semiconductor layer disposed in the second region of the gate insulating layer and including a second source/drain region doped with an n-type impurity; a planarization layer disposed on the first semiconductor layer and the second semiconductor layer and having a first contact hole exposing a portion of the first source/drain region, a second contact hole exposing a portion of the second source/drain region, and a third contact hole exposing a portion of any one of the signal wires; a first connection electrode disposed on the planarization layer and connecting one side of the first source/drain region and one side of the second source/drain region through the first contact hole and the second contact hole; a second connection electrode disposed on the planarization layer and connecting the other side of the first source/drain region with any one of the signal wires through the first contact hole and the third contact hole; a lower electrode disposed on the planarization layer and connected with the other side of the second source/drain region through the second contact hole; an organic film layer including one or a plurality of emission layers on the lower electrode; and an upper electrode disposed on the organic film layer, wherein the signal wires, the first gate electrode, and the second gate electrode are made of a same material.