Patent ID: 8630358
Filing Date: 2014-01-14
Classification: H04L

Abstract:
1. Apparatus for processing data comprising: a packet transmitter configured to generate data packets under control of a transmitter clock signal; a packet receiver configured to receive data packets into a buffer circuit within said packet receiver under control of a receiver clock signal, said receiver clock signal being asynchronous from said transmitter clock signal; and communication circuitry coupled to said packet transmitter and to said packet receiver and configured to transfer data packets across an asynchronous clock boundary between a transmitter clock domain containing transmitter domain circuits operating in synchronism with said transmitter clock signal and including said packet transmitter and a receiver clock domain containing receiver domain circuits operating in synchronism with said receiver clock signal and including said packet receiver; wherein said communication circuitry includes: a transmitter counter coupled to said packet transmitter, operating within said transmitter clock domain and configured to change a transmitter count value by a predetermined change value when said packet transmitter outputs a data packet to said communication circuit; a receiver counter coupled to said packet receiver, operating outside said transmitter clock domain and configured to change a receiver count value by said predetermined change value when a data packet is removed from said buffer circuit; and comparison circuitry configured: (i) to receive said transmitter count value from said transmitter counter; (ii) to receive said receiver count value from said receiver counter; (iii) to perform a comparison of said transmitter count value and said receiver count value; and (iv) to generate a credit signal in dependence upon said comparison, said credit signal indicating whether or not said buffer circuit has any free space available for receiving a data packet; and wherein said packet transmitter is configured to gate transmitting of data packets to said packet receiver via said communication circuitry in dependence upon said credit signal.