Patent ID: 7961837
Filing Date: 2011-06-14
Classification: H03K

Abstract:
1. A counter circuit comprising: a first flip-flop that is inactive when any one of a counter enable signal by the numerical value of 2, a counter enable signal by the numerical value of 4, and a counter enable signal by the numerical value of 8 is enabled; a second flip-flop that is inactive when the counter enable signal by the numerical value of 4 or the counter enable signal by the numerical value of 8 is enabled; a third flip-flop that is inactive when the counter enable signal by the numerical value of 8 is enabled; and a control unit that generates first to third control signals that activate the first to third flip-flops in response to the counter enable signal by the numerical value of 2, the counter enable signal by the numerical value of 4, and the counter enable signal by the numerical value of 8 and carries transmitted from the first and second flop-flops, wherein the control unit includes: