Patent ID: 6835983
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A silicon-on-insulator (SOI) integrated circuit (IC) chip comprising:an SOI material having a buried insulating region which is sandwiched between a bottom Si-containing layer and a top Si-containing layer, said top Si-containing layer comprises at least a first region of a first thickness and at least a second region of a second thickness wherein said first thickness is different from said second thickness; fully depleted CMOS devices located in said first region of said top Si-containing layer having source and drain regions in contact with the underlying buried insulating region and no quasi-neutral device substrate region; and partially depleted CMOS devices which arc built located in said second region of the top Si-containing layer having source and drain regions in contact with the underlying buried insulating region and having a quasi-neutral device substrate region.