Patent ID: 6751128
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A semiconductor memory device having a memory portion wherein data read/write is carried out by means of an EVEN/ODD system provided with an EVEN subdata bus and an ODD subdata bus, the semiconductor memory device comprising:a column control circuit that simultaneously activates a plurality of columns which are subject to degenerate substitution in column redundant substitution; a data read-out circuit that simultaneously reads out data from a plurality of memory cells as selected by said plurality of columns, said data read-out circuit reading out data of the memory cells of a first address to said EVEN subdata bus and reading out data of memory cells of a second address to said ODD subdata bus, with regard to simultaneously activated columns of the first and second addresses; and a judgement circuit that judges the data as read out to said EVEN subdata bus and the data as read out to said ODD subdata bus.