Patent ID: 7618861
Filing Date: 2009-11-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: a first step of preparing a semiconductor substrate including a plurality of element isolation regions disposed at substantially equal intervals in a direction perpendicular to a longitudinal direction of said element isolation regions and an element region exposed from said plurality of element isolation regions and doping impurities of a first conductive type into said element region, and forming a first conductive type impurity region in said element region of said semiconductor substrate; a second step of forming a masking film on a portion of said first conductive type impurity region and then doping impurities of a second conductive type whose conductivity is oppose to that of said first conductive type into said first conductive type impurity region and forming a channel region having said first conductive type and first and second main electrode regions having said second conductive type, said first and second main electrode regions sandwiching a channel region; a third step of removing said masking film and then forming a lower oxide film, a charge storage nitride film, and an upper oxide film in sequence so as to cover over an upper surface of said semiconductor substrate, so as to form an ONO film including said lower oxide film, said charge storage nitride film, and said upper oxide film; a fourth step of forming a floating gate material layer on said ONO film, so as to form a layered product including said ONO film and said floating gate material layer; a fifth step of partially etching said layered product so as to form remnant portions of said layered product as first and second remnant regions separated from each other, said first and second remnant regions substantially parallel to each other extending in a direction perpendicular to said longitudinal direction of said plurality of element isolation regions, said first and second remnant regions having respective edges adjacent to boundary lines between said channel region and said first and second main electrode regions, said first and second remnant regions respectively having first and second floating gates which are formed from said floating gate material layer, said first and second remnant regions respectively having first and second ONO films formed from said ONO film; a sixth step of forming an interlayer insulating film with a substantially uniform thickness so as to cover said first and second remnant regions and an upper surface of said semiconductor substrate; a seventh step of forming a control gate so as to fill a space between said first and second remnant regions and cover said interlayer insulating film; and an eighth step of removing said control gate, said interlayer insulating film, said first and second floating gates, and said first and second ONO films formed on said upper surface of said plurality of element isolation regions and upper surfaces of portions of said element region extending in said longitudinal direction of said element isolation region.