Patent ID: 6538941
Filing Date: 2003-03-25
Classification: G11C

Abstract:
A semiconductor memory device having first and second memory regions, comprising:a plurality of I/O sense amplifiers; a plurality of first and second local I/O line pairs respectively arranged in parallel columns on the first and second memory regions; a plurality of first and second pre-charging means for respectively pre-charging the plurality of first and second local I/O line pairs; a plurality of first and second switching means arranged between the first and second memory regions and respectively connected to terminals of the plurality of first and second local I/O line pairs; a plurality of global I/O line pairs arranged between the first and second memory regions and respectively connected to output terminals of the plurality of first and second switching means and the plurality of I/O sense amplifiers; and switching control means for turning on all of the plurality of first and second switching means in a standby mode, turning off the plurality of second switching means in response to a read command or a write command corresponding to the first memory region, and simultaneously pre-charging the plurality of first and second local I/O line pairs and the plurality of global line pairs through the plurality of first and second pre-charging means by turning on any of the plurality of second switching means that have been turned off in response to a command subsequent to the read or the write command.