Patent ID: 7852692
Filing Date: 2010-12-14
Classification: G11C

Abstract:
1. A method for operating a memory wherein the memory includes an array of memory cells, the method comprising: providing a first operating voltage to a first portion of the memory, the first portion including a first set of memory cells of the array, wherein the memory includes a first plurality of sense amplifier circuits coupled to the first set of memory cells; testing a second set of memory cells of the array of the memory to determine if the second set can operate at a lower operating voltage than the first operating voltage, wherein the memory includes a diagnostic sense circuit coupled to at least some of the second set of cells, the diagnostic sense circuit having a delayed sensing characteristic as compared to the first plurality of sense amplifier circuits; wherein the testing is performed while the operating voltage is provided to the first portion of the memory and the first set of memory cells are operable to store data, the testing further includes using the diagnostic sense circuit to sense data from at least one cell of the second set of cells, wherein the testing includes reading a stored value of the at least one cell and determining if valid data is read.