Patent ID: 6674805
Filing Date: 2004-01-06
Classification: H04N

Abstract:
A video processor system comprising:a video rendering engine having an input to receive a reference clock; a multiplexer having a first input, a second input, a third input, a select input, and an output coupled to the rendering engine input; a first reference clock generator having an output coupled to the multiplexer first input, the first reference clock generator including a system time clock counter having an output coupled to an input of a pulse width modulated (PWM) comparator, the PWM comparator having an output to be coupled to a first controlled oscillator to generate the reference clock; a second reference clock generator having an output coupled to the multiplexer second input, the second reference clock generator including a phase accumulator having an output to be coupled to a second controlled oscillator to generate the reference clock; and a third reference clock generator having an output coupled to the multiplexer third input, the third reference clock generator including a digital phase locked loop to generate the reference clock.