Patent ID: 6303962
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A transistor, comprising:an isolating dielectric arranged upon and in contact with a semiconductor substrate;a pair of source/drain regions arranged upon and in contact with the isolating dielectric, wherein the source/drain regions comprise a metal, and wherein an interface between the source/drain regions and the isolating dielectric comprises a metal;a silicon channel layer arranged upon the isolating dielectric, laterally adjacent and between the source/drain regions;a gate conductor dielectrically spaced above the silicon channel layer; anddielectric spacers arranged upon the silicon channel layer, contiguously interposed between opposing lateral surfaces of each of the source/drain regions and the gate conductor.2.The transistor as recited in claim 1, wherein an upper surface of the gate conductor is at substantially the same elevation level as upper surfaces of the source/drain regions.