Patent ID: 7420853
Filing Date: 2008-09-02
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, and data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode and a voltage applied to the semiconductor layer; a first booster supplying a first voltage to the control electrodes when writing data in the memory cells; a second booster supplying a second voltage different from the first voltage to the control electrodes when writing data in the memory cells; a clock generator which outputs a clock signal; a first frequency demultiplier which demultiplies a frequency of the clock signal to one mth (where m≧1) and outputs a first demultiplied clock signal; and a second frequency demultiplier which demultiplies the frequency of the clock signal to one nth (where n≧1) and outputs a second demultiplied clock signal; wherein when erasing data in the memory cells,