Patent ID: 7846787
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A method of manufacturing a transistor, the method comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate having the gate electrode; forming an amorphous silicon layer on the gate insulating layer; implanting impurity ions into a first region and a second region of the amorphous silicon layer to form a first doped region and a second doped region in the amorphous silicon layer; patterning the amorphous silicon layer having the first doped region and the second doped region, the patterned amorphous silicon layer further comprising an undoped region positioned at an edge portion thereof; while crystallizing the patterned amorphous silicon layer to form a polysilicon layer, forming a silicon oxide layer pattern covering a channel region of the polysilicon layer, the channel region being disposed between the first doped region and the second doped region; and forming a source electrode directly connected to the first doped region and the undoped region of the polysilicon layer and a drain electrode directly connected to the second doped region and the undoped region of the polysilicon layer.