Patent ID: 7786596
Filing Date: 2010-08-31
Classification: H01L

Abstract:
1. A sealed microelectronic structure providing mechanical stress endurance, which comprises: at least two chips including and being electrically connected to a semiconductor structure, and the chips comprising outer edges; each chip including a continuous length of bonding material on a planar surface thereof defining a perimeter in spaced adjacency to the outer edge; at least one support column connected to each of the chips and positioned within the perimeter of each chip, and each support column extending outwardly such that when the at least two chips are positioned in overlapping relation to one another such that opposing support columns mate with each other or with an opposing planar surface area on the overlapping chip; and a seal between the at least two chips resulting from the at least two chips being positioned in overlapping relation to one another such that the bonding material on each chip is in mating relation to each other whereby the seal is formed when the at least two chips are mated together resulting in a bonded chip structure.