Patent ID: 7579196
Filing Date: 2009-08-25
Classification: H01L

Abstract:
1. A method of fabricating an interconnect connecting a diffusion metal layer and a power metal layer, comprising: forming a dielectric layer on a diffusion metal layer, which is on a substrate having a peripheral area and a memory area; patterning the dielectric layer to form first openings therein on the peripheral area to expose the diffusion metal layer; forming metal plugs in the first openings to electrically connect the diffusion metal layer; forming a GMR stack layer on the metal plugs and the dielectric layer; patterning the GMR stack layer to format at least a GMR memory bit on the memory area and a GMR pad on the peripheral area, wherein the GMR pad electrically connects the metal plugs; forming a second dielectric layer on the GMR memory bit, the GMR pad, and the first dielectric layer; patterning the second dielectric layer to form a second opening to expose the GMR memory bit and the GMR pad; and forming a power metal layer in the second opening and on the second dielectric layer.