Patent ID: 8942044
Filing Date: 2015-01-27
Classification: G11C

Abstract:
1. A flash memory device, comprising: a memory cell array comprising a plurality of memory cells; and a pre-charge unit, coupled to a plurality of bit lines corresponding to the memory cells, adapted for pre-charging the plurality of bit lines to a predetermined voltage during a pre-charge stage, and comprising a voltage stabilizing unit, a bias unit and a plurality of adjusting transistors, wherein the voltage stabilizing unit provides a substantially stable current to each of the bit lines, and comprises a mirror unit and a current source, wherein each of the adjusting transistors is coupled to a corresponding bit line, and each of the adjusting transistors comprises a first end coupled to the voltage stabilizing unit, a second end coupled to a corresponding bit line and a control end coupled to the bias unit, and the bias unit is adapted for providing a bias voltage necessary to turn on the adjusting transistors, wherein the mirror unit comprises an input PMOS transistor, and a plurality of mirror PMOS transistors each of which corresponds to one of the adjusting transistors, wherein the input PMOS transistor comprises a source coupled to a power supply, a drain and a gate which are coupled to each other and coupled to the current source; and wherein each of the mirror PMOS transistors comprises a source coupled to the power supply, a gate coupled to the gate of the input PMOS transistor and a drain coupled to the first end of a corresponding adjusting transistor.