Patent ID: 8930862
Filing Date: 2015-01-06
Classification: H03K

Abstract:
1. A method, comprising: replacing, by a processor, a representation of an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of non-restoring latches including a first non-restoring latch circuit and a second non-restoring latch circuit, wherein the first non-restoring latch circuit and the second non-restoring latch circuit each comprise a transmission gate that is coupled to a keeper sub-circuit at the output of the non-restoring latch circuit; determining, by the processor, a node between a first portion of the combinational logic circuit and a second portion of the combinational logic circuit based on a propagation delay of a signal through the combinational logic circuit; propagating the second non-restoring latch circuit to the node; and providing two-phase non-overlapping clock signals to the pair of non-restoring latches.