Patent ID: 6171923
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method for fabricating a two dimensional, trench capacitor structure, for a DRAM cell, formed on an SOI layer, on a semiconductor substrate, and using a storage node structure, of the trench capacitor structure, to connect said SOI layer, to said semiconductor substrate, comprising the steps of:creating an insulator layer in said semiconductor substrate, underlying said SOI layer;forming a pad silicon oxide layer on said SOI layer;anisotropic etching to create a vertical trench in said pad silicon oxide layer, in said SOI layer, in said insulator layer, and in a top portion of said semiconductor substrate;isotropic etching of said insulator layer, exposed in said vertical trench, to create a lateral trench;depositing an in situ doped, first polysilicon layer, coating the sides of said vertical trench, and the coating the sides of said lateral trench, and connecting said SOI layer to said semiconductor substrate;forming a dielectric layer on said first polysilicon layer;depositing a second polysilicon layer on said dielectric layer, completely filling said lateral trench, and said vertical trench; andanisotropic etching of said second polysilicon layer, of said dielectric layer, and of said first polysilicon layer, to create said two dimensional, trench capacitor structure, in said vertical trench, and in said lateral trench, with said two dimensional, trench capacitor structure comprised of: a cell plate structure, formed from said second polysilicon layer; a capacitor dielectric layer, formed from said dielectric layer; and said storage node structure, formed from said first polysilicon layer; with said storage node structure connecting said SOI layer, to said semiconductor substrate.