Patent ID: 7161828
Filing Date: 2007-01-09
Classification: G11C

Abstract:
1. A static random access memory (SRAM) comprising a plurality of SRAM state elements and SRAM environment circuitry, the SRAM environment circuitry being operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption relating to bit lines included in the SRAM environment circuitry is met, wherein the external asynchronous circuitry is characterized by an event-driven protocol, and wherein the event-driven protocol between a first sender and a first receiver in the external asynchronous circuitry comprises, (1) the first sender sets a data signal valid when an enable signal from the first receiver goes high, (2) the first receiver lowers the enable signal upon receiving the valid data signal, (3) the first sender sets the data signal neutral upon receiving the low enable signal, and (4) the first receiver raises the enable signal upon receiving the neutral data signal.