Patent ID: 6622290
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A method for verifying proper timing relationships in a very large scale circuit design; the method comprising the steps of:dividing the circuit design into a plurality of blocks; defining a shell path component as a component on a path P where P is from an input pin of a block to an input of a memory element of a block or where P is from an output of a memory element to an output pin of a block; defining a core path component as a component on a core path C where C is from the output of a first memory element to an input of a second memory element, said first and second memory elements being within the same block; determining which of the components in said circuit design are core path components and which are shell path components; verifying timing relationships of the shell path components while ignoring the core path components; and verifying timing relationships of core path components in each said block.