Patent ID: 6181154
Filing Date: 2001-01-30
Classification: G01R,G11C

Abstract:
A method of testing a packaged semiconductor memory device having a plurality of leads and a semiconductor memory circuit formed on a die, the method comprising:providing a packaged semiconductor memory device, the memory device having at least one redundant lead having a free end coupled to a first pad on the die, the first pad being electrically coupled to a second electrode of a plurality of memory cells in the memory circuit;storing a first voltage value to a first electrode of the plurality of memory cells in the memory circuit;providing a second voltage value to the redundant lead;writing the second voltage value via the first pad to the second electrode of the plurality of memory cells in the memory circuit;analyzing voltage values stored to the first electrode of the plurality of memory cells in the memory circuit; anddetermining that the memory device is defective if any of the first electrodes of the plurality of memory cells contains an analyzed voltage value other than the first voltage value.