Patent ID: 8990455
Filing Date: 2015-03-24
Classification: G06F

Abstract:
1. An apparatus comprising: an array of peripheral function engines, wherein each peripheral function engine comprises a plurality of programmable devices and datapaths and each programmable device is coupled to its corresponding datapath and chaining inputs and outputs (IOs), wherein each datapath comprises a programmable arithmetic logic unit, first in first out (FIFO) registers to serve as parallel data interfaces, and memory registers; a central processing unit coupled to the array of peripheral function engines via a bus; a configuration module, which has access to configuration data, to identify at least one task to offload from the central processing unit to the array of peripheral function engines, wherein the array of peripheral function engines is configured by the configuration module utilizing the configuration data to perform the at least one task, wherein the programmable devices are configured to control operation of its corresponding datapath including a sequence of operations; a memory coupled to the array of peripheral function engines and the central processing unit via the bus; and a plurality of input-output (IO) ports coupled to the array of peripheral function engines via a configurable digital interconnect, wherein the configurable digital interconnect is separate from the bus.