Patent ID: 8232595
Filing Date: 2012-07-31
Classification: H01L

Abstract:
1. A semiconductor device including a power MISFET, comprising: a semiconductor substrate; a gate insulating film formed over the semiconductor substrate; a gate electrode formed over the gate insulating film; a first impurity region of a first conductive type formed in the semiconductor substrate and formed at a first side of the gate electrode; a second impurity region of the first conductive type formed in the semiconductor substrate and formed at a second side of the gate electrode; and a well region of a second conductive type opposite to the first conductive type formed in the semiconductor substrate and formed under the gate electrode and the first impurity region; a first insulating film formed over the power MISFET; a first plug formed in the first insulating film and connected with the first impurity region; a second plug formed in the first insulating film and connected with the second impurity region; a first wiring formed over the first insulating film and connected with the first plug; a second wiring formed over the first insulating film and connected with the second plug; a second insulating formed over the first wiring and the second wiring; a first pad formed over the second insulating film and electrically connected with the first wiring; and a second pad formed over the second insulating film and electrically connected with the gate electrode, wherein a third impurity region of the second conductive type is formed in the semiconductor substrate and is formed at the first side of the gate electrode, and wherein a depth of the third impurity region is deeper than a depth of the first impurity region and is shallower than a depth of the well region.