Patent ID: 7707343
Filing Date: 2010-04-27
Classification: G06F

Abstract:
1. An interrupt control circuit, comprising: a priority mask register holding priority mask information being set with respect to each priority level of interrupt requests; a first masking unit comparing a priority level of an interrupt request with a priority level of an interrupt handling executed by a processor, and outputting an interrupt request signal upon the interrupt request having a higher priority level than, or an equal priority level to, the priority level of the interrupt handling executed by the processor; a second masking unit determining whether to mask the interrupt request signal outputted from the first masking unit in response to the priority mask information; a detecting unit determining whether or not there is the masked interrupt request signal in response to a result of the second masking unit; and a priority mask flag indicating whether or not there is the masked interrupt request signal having a higher priority level than, or an equal priority level to, the priority level of the interrupt handling executed by the processor.