Patent ID: 7272042
Filing Date: 2007-09-18
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: first transistor units formed on a semiconductor substrate, first one of the first transistor units including a first select transistor, a second select transistor and first cell transistors whose current paths are connected in series between a source region of the first select transistor and a drain region of the second select transistor; second transistor units formed on the semiconductor substrate, first one of the second transistor units including a third select transistor, a fourth select transistor and second cell transistors whose current paths are connected in series between a source region of the third select transistor and a drain region of the fourth select transistor; a first section select transistor which is formed on the semiconductor substrate and which has a source region electrically connected to a drain region of the first select transistor; a second section select transistor which is formed on the semiconductor substrate and which has a source region electrically connected to a drain region of the third select transistor and has a drain region shared with the first section select transistor; a first contact plug formed on the drain region of the first and second section select transistors; and a first bit line connected to the first contact plug.