Patent ID: 7320901
Filing Date: 2008-01-22
Classification: H01L

Abstract:
1. A fabrication method for a chip packaging structure comprising: providing a carrier plate, wherein a conductive layer is formed on an upper surface of said carrier plate; forming a plurality of trenches penetrating through said conductive layer by utilizing the photolithography process; forming a first patterned photoresist layer on said upper surface and a first photoresist layer on a downward surface of said carrier plate, wherein said trenches are filled by said first patterned photoresist layer; filling at least a metal layer on said conductive layer between said first patterned photoresist layer, wherein said metal layer includes a plurality of conductive joints; performing a metal surface treatment on the surface of said metal layer; removing said first patterned layer and said first photoresist layer; and proceeding a chip packaging process.