Patent ID: 7948297
Filing Date: 2011-05-24
Classification: H03F

Abstract:
1. A circuit to minimize thermally generated offset voltages comprising: a differential pair of transistors comprising a first transistor and a second transistor coupled to a current source; a differential input comprising a first input coupled to the first transistor and a second input coupled to the second transistor; a pair of bypass transistors comprising a first bypass transistor and a second bypass transistor, the first bypass transistor coupled in parallel with the first transistor and the second bypass transistor coupled in parallel with the second transistor, wherein the pair of bypass transistors is coupled to the current source; and control circuitry coupled to the pair of bypass transistors for controlling current through the pair of bypass transistors, the control circuit configured to control the pair of bypass transistors to prevent the pair of bypass transistors from conducting current when a voltage difference between the first input and the second input is small and configured to control the pair of bypass transistors so that at least one of the bypass transistors conducts current when the voltage difference between the first input and the second input is relatively large.