Patent ID: 6188618
Filing Date: 2001-02-13
Classification: G11C

Abstract:
A semiconductor storage device comprising:a memory cell array having memory cells arranged in columns and rows, the memory cell array being divided into a plurality of sub cell arrays;redundancy cell arrays each located adjacent to a corresponding one of the sub cell arrays;row decoders for each selecting a corresponding one of the rows of the memory cell array in accordance with a first input address;column decoders for each selecting a corresponding one of the columns of the memory cell array in accordance with a second input address;a plurality of storage circuits each for storing an address assigned to a defective memory cell included in the memory cell array, and also storing mapping information indicative of the relationship with the redundancy cell arrays, the storage circuits outputting, when an address assigned to one of the defective memory cells stored therein matches the second input address, a replacement control signal for the defective memory cell on the basis of the result of matching, and the mapping information; andspare decoders each to be activated by the replacement control signal supplied from the storage circuits to thereby select a corresponding one of the redundancy cell arrays, andwherein the number of the storage circuits is smaller than the number of the redundant cell arrays.