Patent ID: 6351433
Filing Date: 2002-02-26
Classification: G11C

Abstract:
A synchronous semiconductor memory device performing data input/output according to a control signal and an address signal in synchronization with a clock signal, comprising:a plurality of address terminals for receiving respective bits of said address signal; a data terminal for input/output of data; a memory array circuit for performing reading/writing of said data according to said address signal with respect to a plurality of memory cells arranged in rows and columns; a control circuit responsive to said control signal for designating one of a reading operation and a writing operation to said memory array circuit and for designating one of data input and data output to said data terminal, in synchronization with said clock signal; a data retaining circuit provided between said data terminal and said memory array circuit for taking in write data input into said data terminal at a clock cycle in which said data input is designated, and for temporarily retaining at least one piece of said write data as storage data until it is written into said memory cell; an address retaining circuit receiving said address signal from said plurality of address terminals for retaining at least one storage address signal corresponding to at least one piece of said storage data; an address select circuit receiving a read address signal being an address signal input into said address terminals for data output and said storage address signal, for selectively transmitting one of these address signals to said memory array circuit according to the operation designated to said memory array circuit; an address comparison circuit activated by said control circuit for performing matching of said read address signal with each said storage address signal at a clock cycle in which said reading operation is designated, and inactivated by said control circuit in a clock cycle other than said clock cycle in which said reading operation is designated; a read data select circuit responsive to the matching result of said address comparison circuit for selecting one data out of said write data, said storage data and read data from said memory array circuit that correspond to said read address signal; and a read data latch circuit for latching the data selected by said read data select circuit for transmission to said data terminal at a clock cycle in which said data output is designated.