Patent ID: 8994424
Filing Date: 2015-03-31
Classification: H03K

Abstract:
1. A logic unit, comprising: at least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles, wherein the at least one multiplexor comprises N−1 multiplexors; and at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein the at least two latches comprises N latches, wherein the signal is initially simultaneously distributed both as input to a first latch of the at least two latches positioned in the delay path and as one of the two inputs to each at least one multiplexor, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.