Patent ID: 8447950
Filing Date: 2013-05-21
Classification: H04L

Abstract:
1. An integrated circuit comprising: M sorter blocks, wherein each sorter block has a user-selectable number of entries of one or more entries, each entry comprises a time stamp value and a connection value, there are a total of N entries for all the M sorter blocks, and M is an integer 2 or greater, each sorter block comprises a pointer memory structure, referenced using a first pointer address having a head and a body, wherein the head comprises a bit map field comprising four bits and the body comprises four memory positions, the head comprises a pointer-to-body field, each bit in the bit map field representing one of the four memory positions, when storing a second pointer address in a first memory position of the four memory positions, changing a first bit of the four bits of the head of a first pointer memory structure to a second state from a first state, when storing the second pointer address in a second memory position of the four memory positions, changing a second bit of the four bits of the head of the first pointer memory structure to the second state, and the pointer-to-body field stores a pointer pointing to one of the four memory location positions.