Patent ID: 6686920
Filing Date: 2004-02-03
Classification: G06F,G11C

Abstract:
A system for optimizing the translation of virtual addresses into physical addresses using a pipeline implementation, the system comprising:a main memory device operable to store information for translating a virtual address into a physical address; a translation look-aside buffer cache coupled to the main memory, the translation look-aside buffer cache comprising a plurality of translation look-aside buffer entries, each translation look-aside buffer entry operable to buffer information for use in translating; and a least recently used pointer circuit coupled to the translation look-aside buffer cache, the least recently used pointer circuit operable to generate and store a least recently used pointer, said least recently used pointer configured to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache, said least recently used pointer comprising a plurality of pointer entries, each of said plurality of pointer entries operable to store status information for said plurality of translation look-aside buffer entries of said look-aside buffer cache, said plurality of pointer entries operable to be updated after an access into said translation look-aside buffer cache to reflect said access into said translation look-aside buffer cache.