Patent ID: 6074918
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method of fabricating a dynamic random access memory (DRAM) cell, comprising the steps of:forming a capped gate line on a substrate, the capped gate line including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line;forming spaced apart source/drain regions in the substrate on opposite sides of the gate line;forming a first dielectric layer on the substrate, the first dielectric layer extending from the substrate to at least the gate line cap;forming a second dielectric layer on the first dielectric layer;forming a third dielectric layer on the second dielectric layer;forming a storage electrode plug extending from third dielectric layer and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions; andforming a channel electrode extending from third dielectric layer and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions.