Patent ID: 8334557
Filing Date: 2012-12-18
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array having memory cells arranged therein, the memory cells being configured to store data in a nonvolatile manner; and a plurality of transfer transistors configured to transfer a voltage supplied for writing data in the memory cells, the plurality of transfer transistors including: a gate electrode formed above a semiconductor substrate via a gate insulating film; a first diffused region formed in a surface of the semiconductor substrate located under the gate electrode; a second diffused region formed in a surface of the semiconductor substrate adjoining the first diffused region on a first side of the first diffused region; and a third diffused region formed in a surface of the semiconductor substrate adjoining the first diffused region on a second side of the first diffused region, the first side and the second side being opposite, the third diffused region including an overlapping region overlapping the first diffused region, a first wire being disposed above the overlapping region, the first wire being supplied with at least a predetermined voltage for preventing formation of a depletion region in the third diffused region when the transfer transistor transfers the voltage used for writing, the first wire extending in a direction parallel to the semiconductor substrate.