Patent ID: 6034416
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate, including a memory cell region and a peripheral circuit region;trench isolations, formed so as to respectively surround a first active region in the memory cell region and a second active region in the peripheral circuit region of the semiconductor substrate;a nonvolatile memory cell, disposed in the memory cell region and formed by sequentially stacking a tunnel insulator film, a floating gate electrode, a gate insulator film and a control gate electrode at least in the first active region on the semiconductor substrate; anda field effect transistor, disposed in the peripheral circuit region and formed by sequentially stacking a gate insulator film and a gate electrode at least in the second active region on the semiconductor substrate,wherein a top surface of the semiconductor substrate in the second active region is at a level that is higher than a top surface of the semiconductor substrate in the first active region and that is substantially equal to a top surface of the floating gate electrode.