Patent ID: 6163068
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A multi-chip semiconductor comprising:a leadframe, said leadframe having a center open area and at least two parallel rows of pins disposed at peripheral sides of said leadframe around said center open area;a substrate mounted in said center open area of said leadframe such that said substrate and said leadframe lie in a single plane, said substrate comprising a plurality of chip positioning zones, a window being disposed at a center of each of said chip positioning zones, conductor elements being disposed at a top side wall of each window, and at least two rows of terminals projecting outward from peripheral sides of said substrate, said terminals being connected to said pins of said leadframe;a plurality of chips mounted in said chip positioning zones at a back side wall of said substrate, said chips each having a plurality of solder tips respectively suspended in said windows in said substrate corresponding to respective conductor elements of said substrate; andconductor wires respectively connected between said solder tips of said chips and said conductor elements of said substrate.