Patent ID: 6207999
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A mask ROM (mask read only memory) device on a substrate having a NMOS device region and a NMOS cell region for coding, said mask ROM comprising:an isolation structure formed between said NMOS device region and said NMOS cell region;a gate oxide layer formed on said NMOS device region;a coding oxide layer formed on said NMOS cell region, said coding oxide layer having a thickness of about two to ten times of a thickness of said gate oxide layer;main gates respectively formed on said gate oxide layer and said coding oxide layer, said main gates comprising a material being selected from the group consisting of metal and metal compounds;sidewall spacers formed on side walls of said main gates;first doped regions of source and drain regions formed under said sidewall spacers and adjacent to said main gates;second doped regions of said source and drain regions forming next to and outside said first doped regions, said second doped regions having a heavier dose than said first doped regions; anda p type doped region formed under said coding oxide layer and in adjacent to a surface of said NMOS cell region, said p type doped region being doped with dopants selected from the group consisting of aluminum-containing, gallium-containing, indium-containing, and thallium-containing dopants.