Patent ID: 7555017
Filing Date: 2009-06-30
Classification: H04J,H04L

Abstract:
1. A process of synchronizing events on a packet switched network by: maintaining a master clock at a master node of a packet switched network of interconnected nodes including one or more nodes for converting analog audio input to digital audio packets and also including one or more nodes for converting the digital audio packets to analog audio output; encoding high priority timing packets for transmission from the master node to one or more other nodes on the packet switched network and sending out a multiplicity of said timing packets onto the network at pseudo-random intervals to increase a probability that at least some of the timing packets affive at the one or more other nodes after traversing the packet switched network with a minimum network transit delay time; and at the one or more other nodes, filtering the timing packets received with the least timing error by finding a minimum network transit time from a set N of multiple timing packets sent between the master node and the one or more other nodes, by finding the minimum time offset from the set, of multiple timing packets where N, the size of the set is chosen such that given a probability, P=T T T then choosing N≈1/P so that it is almost certain at least one packet in the set will arrive with minimum network transit delay; and then using only the timing packets received with least timing error to synchronize the local clock maintained at the one or more other nodes, to the clock at said master node.