Patent ID: 6380918
Filing Date: 2002-04-30
Classification: G02F,G09G,H05K

Abstract:
A liquid crystal display device comprising:a liquid crystal panel having a liquid crystal layer held between a first substrate and a second substrate, the first substrate having a first electrode group extending in a first direction, and the second substrate having a second electrode group extending in a second direction transverse to the first direction; a first multilayer printed circuit board being connected to the first electrode group through a tape carrier pad carrying a plurality of segment drive circuits to apply a pixel drive voltage to the first electrode group, the tape carrier pad being connected with an uppermost wiring layer of the first multilayer printed circuit board; and a second multilayer printed circuit board being connected to the second electrode group through a tape carrier pad carrying a plurality of common drive circuits to apply a common voltage to the second electrode group, the second multilayer printed circuit board having a drive circuit to supply an externally applied pixel clock signal to the segment drive circuits; wherein a high-speed clock signal wire is provided on one layer of the first multilayer printed circuit board which is located close to an upper surface of the first multilayer printed circuit board so as to reduce parasitic capacitance therealong, and extends via a through-hole to the upper surface of the first multilayer printed circuit board, and wherein a length of the through-hole is limited based upon the location of the one layer of the first multilayer printed circuit board with respect to the upper surface of the first multilayer printed circuit board so as to reduce parasitic capacitance along the high-speed clock signal wire and to suppress miscounting of clock signals transmitted along the high-speed clock signal wire.