Patent ID: 6175849
Filing Date: 2001-01-16
Classification: H03H

Abstract:
A digital filter comprising:a multiplier;an adder;a first plurality of latches to present latched data samples to said multiplier in each of four multiplier clock cycles;a second plurality of latches to present latched data samples to said adder in each of four adder clock cycles;at least one of said four multiplier clock cycles occurring concurrently overlapping with at least one of said four adder clock cycles;a read-only memory configured for storing coefficients of said digital filter; anda random-access memory configured for storing state variables of data frames,wherein said multiplier and said adder calculate an output for said digital filter based on a transfer function of Y(n)=A.sub.S wherein W(n) is a state variable of a current data frame, W(n-1) is a state variable of a previous data frame, and W(n-2) is a state variable for a data frame two frames previous, A.sub.S is a scaling factor, and A.sub.1 is a constant whereby W(n), W(n-1), and W(n-2) are supplied to said multiplier and said adder from said random-access memory, and A.sub.S and A.sub.1 are supplied to said multiplier and said adder from said read-only memory.