Patent ID: 7593284
Filing Date: 2009-09-22
Classification: G06F,G11C,Y02D

Abstract:
1. A SRAM emulating non-volatile memory, comprising: a static random access memory (SRAM) interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for SRAM data operations, the plurality of signals including an address signal and at least one data signal; and a non-volatile memory array vertically positioned over the logic plane and in contact with the logic plane, the non-volatile memory array is electrically coupled with the SRAM interface circuitry, the non-volatile memory array including a plurality of memory elements, each memory element including two terminals and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the two terminals, the data is retained in the absence of power, the data is written by applying a write voltage across the two terminals, the write voltage is less than the read voltage, and wherein the SRAM interface circuitry is operative to perform data operations on the non-volatile memory array in response to the plurality of signals and the data operations emulate SRAM data operations.