Patent ID: 6764945
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A fabrication method for a semiconductor integrated circuit device, comprising the steps of:(a) forming a first insulating film over a semiconductor substrate; (b) forming a barrier metal film over said first insulating film; (c) forming an aluminum alloy wiring film over said barrier metal film and to a thickness larger than that of said barrier metal film; (d) forming a capping metal film over the aluminum alloy wiring film and to a thickness smaller than that of said aluminum alloy wiring film; (e) dry etching said barrier metal film, said aluminum alloy wiring film, and said capping metal film, thereby forming a first wiring pattern; (f) forming a second insulating film over said first insulating film and over said first wiring pattern; (g) selectively dry etching said second insulating film, thereby forming a connecting hole through the second insulating film; (h) depositing a first electroconductive film over said second insulating film including the inside of said connecting hole by a non-directional sputtering method so as to electrically connect to said first wiring pattern; (i) depositing a second electroconductive film over said first electroconductive film by a directional sputtering method having higher directivity than said non-directional sputtering method; and (j) forming a third electroconductive film of tungsten over said second electroconductive film so as to fill said connecting hole, said third electroconductive film being formed to a thickness larger than that of said first and second electroconductive films, and, thereafter, removing the first, second and third electroconductive films from the outside of said connecting hole, thereby forming a plug.