Patent ID: 6064706
Filing Date: 2000-05-16
Classification: H03L,H04J

Abstract:
A digital desynchronizer, comprising:an elastic store unit operable to receive synchronously mapped asynchronous data on a synchronous data bus;a digitally controlled oscillator operable to generate an output clock signal, the elastic store unit operable to generate asynchronous output data from the synchronously mapped asynchronous data in response to the output clock signal;a programmable jitter accumulator operable to generate a jitter control signal, the jitter control signal operable to adjust a clock rate of the output clock signal such that the asynchronous output data from the elastic store unit has a programmable logarithmic frequency response, wherein the digitally controlled oscillator generates a reset signal after adjusting the clock rate of the output clock signal, the jitter control signal returning to a de-asserted level in response to the reset signal.