Patent ID: 8350554
Filing Date: 2013-01-08
Classification: G05F,G11C

Abstract:
1. A semiconductor device comprising: a bias voltage generator configured to comprise a PMOS transistor and an NMOS transistor coupled in series between a power supply voltage terminal and a ground voltage terminal and generates the bias voltage at a connection node of the PMOS transistor and the NMOS transistor; a first reference voltage generator for generating a first reference voltage in response to the bias voltage; and a second reference voltage generator for generating a second reference voltage in response to the first reference voltage, wherein the second reference voltage generator includes: a second band gap circuit for dividing a voltage at a second reference voltage output node to produce a third band gap voltage having a negative property and a fourth band gap voltage having a positive property relative to the temperature variations; a second comparator for receiving the first reference voltage as a bias input and comparing the third band gap voltage with the fourth band gap voltage; and a second driver for pull-up driving the second reference voltage output node in response to an output signal of the second comparator.