Patent ID: 6794306
Filing Date: 2004-09-21
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor device having a transistor comprising:preparing a SOI substrate including a SOI layer, a buried oxide layer, and a lower substrate layer, the SOI layer having at least one unit dual layer formed of a silicon germanium layer and a silicon layer; patterning the SOI layer to form an active layer pattern in a certain direction; forming an insulation layer covering the surface of the active layer pattern; stacking an etch stop layer on the active layer pattern covered with the insulation layer; patterning and removing the etch stop layer at a gate region crossing the active layer pattern at the channel region to form an etch stop layer pattern; removing the insulation layer at the gate region; isotropically etching and selectively removing the silicon germanium layer to form a cavity at the channel region of the active layer pattern; forming a gate insulation layer to cover the exposed surface of the active layer pattern at the substrate where the silicon germanium layer is selectively removed; and stacking a conductivity material layer at the substrate where the gate insulation layer is formed and thereby forming a gate electrode at the gate region including the cavity.