Patent ID: 6686288
Filing Date: 2004-02-03
Classification: H01L,Y10S

Abstract:
A method for forming a digit line contact in an array of dynamic random access memory cells, said array being constructed on a silicon substrate and having a capacitor for each cell, said array having an interlevel dielectric layer thereover covering each capacitor, each memory cell within said array having a field-effect access transistor having a gate electrode encased on a top and sides thereof in a dielectric material, said interlevel dielectric layer anisotropically and selectively etchable with respect to the dielectric material, each field-effect access transistor having a storage-node junction coupled to said capacitor and an access-node junction having a digit line connected thereto, said method comprising:anisotropically etching a digit line contact opening having a wall and a bottom through the interlevel dielectric layer, the bottom of the contact opening exposing an underlying access-node junction located on said silicon substrate, each digit line contact opening being self-aligned to the dielectric material on a side of at least one transistor gate electrode, said contact opening having a height to width ratio of greater than at least 5 to 1; depositing a titanium metal layer using chemical vapor deposition, said titanium metal layer lining the wall of the digit line contact opening and covering the exposed access-node junction at the bottom of the contact opening; depositing a titanium nitride layer via chemical vapor deposition, said titanium nitride layer covering the titanium metal layer lining the wall of the digit line contact opening and the access-node junction at the bottom of the contact opening; forming a tungsten plug within the contact opening having the titanium nitride layer covering the titanium metal layer; and forming a metal interconnect line on an upper surface of the interlevel dielectric layer, the metal interconnect line contacting the tungsten plug.