Patent ID: 7282976
Filing Date: 2007-10-16
Classification: H03K,H03L

Abstract:
1. An apparatus, included in a delay locked loop, for correcting a duty cycle of a clock signal, comprising: a duty correction block for receiving the clock signal and adjusting the duty cycle of the clock signal in response to duty correction voltages to thereby output a duty corrected clock signal; a duty check block for receiving the duty corrected clock signal and checking a duty cycle error of the duty corrected clock signal to thereby generate the duty correction voltages; a control block for generating a control signal keeping a first logic state during a predetermined time in response to a reset signal resetting the delay locked loop; and a voltage supplier for providing a supply voltage as the duty correction voltages during the predetermined time in response to the control signal, wherein the control block is provided with a pulse generator for generating the control signal in a shape of a pulse by using the reset signal, the pulse generator including: a delay block for delaying the reset signal; and a logic block for receiving the reset signal and an output signal from the delay block to thereby generate the control signal keeping the first logic state during the predetermined time.