Patent ID: 6621749
Filing Date: 2003-09-16
Classification: G11C

Abstract:
An integrated circuit memory device, comprising:a plurality of memory cells arranged as a plurality of blocks, each of the blocks including a plurality of primary memory cells that are coupled and decoupled to and from respective input/output lines responsive to a primary column select line and a plurality of redundant memory cells that are coupled and decoupled to and from respective ones of the input/output lines responsive to a redundant column select line; a column select circuit, coupled to the primary column select lines and to the redundant column select lines, that drives a first primary column select line associated with a primary memory cell in a first block responsive to application of a first column address and that simultaneously drives the first primary column select line and a first redundant column select line associated with a first redundant memory cell in a second block responsive to application of a second column address; a plurality of sense amplifiers; and an input/output control circuit configurable to selectively connect the input/output lines to the sense amplifiers such that the first primary memory cell is coupled to a sense amplifier responsive to application of the first column address and such that the first redundant memory cell is coupled to the sense amplifier responsive to application of the second column address.