Patent ID: 6639417
Filing Date: 2003-10-28
Classification: G01R

Abstract:
A semiconductor parametric testing apparatus comprising:a tester body for performing a test of a wafer comprising a plurality of dice having a module, said tester body comprising a probe for contacting said module and providing an electric signal to said probe, measuring an electric signal from said module by said probe, and outputting measured data; a wafer probe for taking said wafer from a wafer lot and for positioning said probe on said module; a computer, including a display, for processing said measured data and for controlling said tester body and wafer prober; a measuring program executed by said computer having a test shell comprising: a test plan describing an attribute of said test; a framework comprising a program of a process for testing and a user interface displayed at least at a time of performing said test, said user interface including an operation panel for designating a predetermined module for which said test is automatically paused, said operation panel comprising; a die list of at least one die attribute for selection; a wafer map displaying dice for selection, said displayed dice having a die attribute selected from said die list, and a module list of a module of one of said dice selected from said wafer map.