Patent ID: 6310506
Filing Date: 2001-10-30
Classification: G11C,H03K

Abstract:
A signal latching apparatus for an integrated circuit, comprising:an input buffer connected to an input pin of the integrated circuit and operable to receive an externally applied input signal having a setup/hold time window from the input pin;a latching device operable to latch a signal at its input in response to an edge of a latching signal; anda delay network coupled to the input buffer and the latching device and operable to delay the input signal, the delay network comprising:a plurality of delay devices through which the input signal travels; andat least one fuse connected to at least one of the plurality of delay devices such that opening the fuse changes the amount of delay time the input signal experiences through the delay network such that the setup/hold time window of the delayed input signal at the input of the latching device coincides with the edge of the latching signal.