Patent ID: 6591410
Filing Date: 2003-07-08
Classification: G06F,H01L

Abstract:
A method for making a bump and trace layout for an integrated circuit die comprising a step for replicating a routing tile on a flip chip integrated circuit die wherein the routing tile includes a first column of I/O pads arranged above a ground trace of the routing tile and a second column of I/O pads arranged above a ground trace of the routing tile wherein the first column of I/O pads is offset from the second column of I/O pads so that the I/O pads of the first column are interleaved between the I/O pads of the second column of I/O pads and wherein the first column of I/O pads and the second column of I/O pads are arranged substantially perpendicular to an edge of the flip chip integrated circuit die closest to a ground trace of the routing tile.