Patent ID: 8983063
Filing Date: 2015-03-17
Classification: H04L

Abstract:
1. An apparatus comprising: an encryption circuit for encrypting a plurality of data blocks of a data segment, the encryption circuit configured to selectively switch between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride; wherein the encryption circuit comprises a combiner circuit, a block cipher circuit, and a sequence generator circuit; wherein the combiner circuit is configured to combine a plurality of bit vectors with a plurality of data blocks of the data segment to generate a plurality of bit vector data block combinations for encryption by the block cipher circuit; the block cipher circuit comprising a plurality m of pipelined stages for simultaneously processing, in a pipelined fashion, a plurality m of different bit vector-data block combinations corresponding to m data blocks of the data segment to thereby generate a plurality of encrypted data blocks, the encrypted data blocks comprising a first plurality of encrypted data blocks for the data segment that were encrypted according to the BIR encryption mode and a second plurality of encrypted data blocks for the same data segment that were encrypted according to the CBC encryption mode, the value for m being configurable to define the feedback stride; and the sequence generator configured to selectively switch between the BIR encryption mode and the CBC encryption mode based on the feedback stride, wherein the sequence generator is further configured to (1) generate and output a plurality of randomized blockwise independent bit vectors for delivery to the combiner circuit while in the BIR encryption mode, and (2) generate and output a plurality of blockwise dependent bit vectors for delivery to the combiner circuit while in the CBC encryption mode, the blockwise dependent bit vectors being based on a previously encrypted bit vector-data block combination fed back from the block cipher circuit.