Patent ID: 7830999
Filing Date: 2010-11-09
Classification: G06F,H04L

Abstract:
1. An apparatus for generating a clock signal of a semiconductor memory comprising: a first shifting unit configured to output first shifting signals having a phase using at least one of a plurality of periodic signals; a control signal generating unit configured to output multiplexing control signals using an inverted clock signal; a second shifting unit configured to output second shifting signals having a phase using at least one of the periodic signals; a correcting unit configured to output correction signals having an intermediate phase between the phase of the first shifting signals and the phase of the second shifting signals on the basis of first and second bias signals applied thereto; a combination unit configured to combine the first shifting signals and the correction signals, to output combined signals; a multiplexing unit configured to selectively output the combined signals according to multiplexing control signals; and a driving unit configured to drive the clock signal and the inverted clock signal on the basis of the combined signals output of the multiplexing unit.