Patent ID: 7343536
Filing Date: 2008-03-11
Classification: G01R

Abstract:
1. A test circuit adapted for use with a scan based Automatic Test Pattern Generation (ATPG) method, the test circuit comprising: a scan chain group comprising a plurality of scan chains adapted to connect a plurality of sources, the scan chain group receiving test data from a predetermined number of scan input pins and outputting scan chain group output signals; a decoder logic circuit decoding a plurality of scan test point mode signals and outputting a decoder logic circuit output signal; a scan test point group outputting a plurality of scan test point group output signals in relation to the scan chain group output signals and the decoder logic circuit output signal; and, a scan test data compressor compressing the plurality of scan test point group output signals into a scan test data compressor output signal; wherein the plurality of scan test point mode signals comprises signals comprising information regarding a scan chain having an unknown value, the information comprising a number of the scan chain having the unknown value and a location of the unknown value within the scan chain, wherein the scan test point group comprises a plurality of scan test point circuits; and wherein each of the scan test point circuits receives a signal output by a corresponding scan chain and the decoder logic circuit output signal and either outputs the signal output by the corresponding scan chain or outputs a stored output signal received from the corresponding scan chain in a previous clock cycle in response to the decoder logic circuit output signal.