Patent ID: 7084057
Filing Date: 2006-08-01
Classification: H01L

Abstract:
1. A method of fabricating a bit line contact structure, comprising: providing a substrate having a transistor thereon, the transistor having a gate electrode, drain region, and source region; blanketly forming a first dielectric layer on the transistor using spin coating; conformally forming a barrier layer covering the first dielectric layer; blanketly forming a second dielectric layer on the barrier layer; forming a patterned resist layer on the second dielectric layer; etching the second dielectric layer using the patterned resist layer as an etching mask, forming an opening exposing the barrier layer; removing the patterned resist layer; removing the barrier layer in the opening; etching the first dielectric layer using the second dielectric layer as an etching mask, forming a via, wherein a width of a portion of the via above the barrier is substantially the same as a width of another portion of the via lower than the barrier; and filling the via with a conductive layer.