Patent ID: 9117805
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A method for manufacturing a MOS transistor comprising: forming a gate stack having a height, a length, and a width and comprising a lower portion, a middle portion and an upper portion; forming around the gate stack at least one first spacer surrounded with another material; removing the first spacer to form a cavity on each side of the gate stack; decreasing the length of the middle portion of the gate stack in said cavity such that the length of the middle portion is less than the lengths of the lower and upper portions; closing an upper aperture of the cavity by a non-conformal method while depositing a dielectric layer on the walls of the gate stack with the decreased length middle portion so as to provide an air spacer; removing the lower, decreased length middle and upper portions of the gate stack to provide a gate stack opening; and filling the gate stack opening with a conductive metal to form a metal gate having a lower conductive portion, a middle conductive portion and an upper conductive portion, wherein the length of the middle conductive portion is less than the lengths of the lower and upper conductive portions.