Patent ID: 8207560
Filing Date: 2012-06-26
Classification: H01L,Y10S

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate having an upper surface and a surface layer; a gate insulating film formed on the upper surface of the semiconductor substrate; a gate electrode formed on the gate insulating film and having a sidewall; a source/drain region formed at each side of the gate electrode on the surface layer of the semiconductor substrate respectively, the source/drain region including a first region, a second region and a third region located between the first and second regions; a contact plug formed on the second region of the source/drain region; a first silicon oxide film formed on the sidewall of the gate electrode so as to serve as an ion implantation spacer, the first silicon oxide film having a first lower surface in contact with the upper surface of the first region of the source/drain region and located lower than the upper surface of the semiconductor substrate where the gate insulating film is located; a second silicon oxide film formed on the third region of the source/drain region and a side surface of the first silicon oxide film, the second silicon oxide film having a second lower surface in contact with the upper surface of the source/drain region and located lower than the first lower surface of the first silicon oxide film; and a silicon nitride film formed on an upper surface of the second silicon oxide film, wherein the first silicon oxide film, the second oxide film having the silicon nitride film formed thereon, and the contact plug are contiguously arranged on said first, third and second regions of the source/drain region, and the contact plug extends through the second silicon oxide film and the second nitride film to contact the source/drain region.