Patent ID: 6456166
Filing Date: 2002-09-24
Classification: H03K,H03L

Abstract:
A semiconductor integrated circuit, comprising:a first FET connected between a first voltage terminal and a first node; a second FET connected between said first node and a first output terminal; a third FET connected between said first node and a second output terminal; a first variable impedance load connected between said first output terminal and a second voltage terminal; a second variable impedance load connected between said second output terminal and said second voltage terminal; a first bias circuit connected between said first node and said second voltage terminal, said first bias circuit setting said first node to substantially a constant voltage, regardless of impedance values of said first and second variable impedance loads; and a current generator bias circuit configured to supply a bias voltage to a gate terminal of said first FET, wherein a first input terminal is connected to a gate terminal of said second FET, and a second input terminal is connected to a gate terminal of said third FET.