Patent ID: 9064474
Filing Date: 2015-06-23
Classification: G09G

Abstract:
1. An n-th stage driving module with a common control node, producing a plurality of scanning signals sequentially and outputting to a display panel sequentially, receiving a plurality of clock signals and receiving a first input voltage and a second input voltage, respectively, the n-th stage driving module comprising: a plurality of output units, all coupled to a control node, and receiving said plurality of clock signals; a forward input unit, coupled to said control node, receiving said first input voltage and a front forward scanning signal of said output unit of any driving module lower than or equal to the (n−1)th stage, and charging and discharging said control node according to said first input voltage and said front forward scanning signal; a reverse input unit, coupled to said control node, receiving said second input voltage and a back reverse scanning signal of said output unit of any driving module higher than or equal to the (n+1)th stage, and charging and discharging said control node according to said second input voltage and said back reverse scanning signal; and a noise free unit, coupled to said forward input unit, said reverse input unit, and said plurality of output units, receiving a first clock signal, and filtering out the noises at said control node of said plurality of output units, the n-th stage driving module further comprising: wherein said forward input unit charges said control node according to said first input voltage and said front forward scanning signal, and said plurality of output units produce and forward output a plurality of forward scanning signals sequentially according to said plurality of clock signals and said control node, respectively, and said reverse input unit charges said control node according to said second input voltage and said back reverse scanning signal, and said plurality of output units produce and reversely output a plurality of reverse scanning signals sequentially according to said plurality of clock signals and said control node, respectively, and n is an integer greater than one.