Patent ID: 8969938
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: an SOI (semiconductor on insulator) substrate comprising a base substrate, a doped back gate layer on the base substrate, a buried insulating layer on the doped back gate layer and an ETSOI (extra thin SOI) layer on the buried insulating layer, said SOI substrate divided into a transistor region and a capacitor region, the transistor region and the capacitor region each having the doped back gate layer, the buried insulating layer and the ETSOI layer, wherein the doped back gate layer has an uppermost surface directly abutting the buried insulating layer; an ETSOI transistor formed on said SOI substrate having a first contact contacting a first metal gate, the first metal gate also contacting the ETSOI layer, the ETSOI transistor further having a dielectric material surrounding the first metal gate; and a capacitor or varactor in said SOI substrate adjacent to said ETSOI transistor, said capacitor or varactor comprising a second contact contacting a second metal gate; said second metal gate is located above said SOI substrate, and extends into said SOI substrate down to abut the uppermost surface of the doped back gate layer such that the second metal gate does not extend below the uppermost surface of the doped back gate layer, the capacitor or varactor further having a dielectric material surrounding the second metal gate in the ETSOI layer and the buried insulating layer, said first and second contacts abutting at a same level.