Patent ID: 6207991
Filing Date: 2001-03-27
Classification: H01L

Abstract:
An electrically erasable and programmable read-only memory cell comprising:a tunnel dielectric layer formed on a silicon substrate;a non-volatile storage transistor including (i) a floating gate on said tunnel dielectric layer, said floating gate having vertical sidewalls, (ii) an interlayer dielectric layer thereon and (iii) a control gate in contact with said interlayer dielectric layer and said tunnel dielectric layer; anda select transistor including a gate on a gate oxide layer, a protective dielectric layer thereon and a sidewall spacer adjacent to said select transistor gate, said protective dielectric layer and said gate oxide layer, said gate of said select transistor and said gates of said non-volatile storage transistor overlapping a common source/drain implant region in said substrate;wherein said control gate overlaps essentially all of the vertical sidewalls of said floating gate.