Patent ID: 6083800
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method of fabricating for high voltage semiconductor device, comprising the steps of:forming a first impurity regions of a second conductivity type of a low impurity concentration in a predetermined source and drain region formed in a semiconductor substrate, in which a well of a first conductivity type is formed;forming isolation layers on a predetermined portion of the semiconductor substrate;forming a stacked pattern in on order of gate oxide and gate electrode on the substrate between the first impurity regions;forming a side wall spacer on the both side wall of the gate electrode;forming second impurity regions of the first conductivity type of a medium impurity concentration at a predetermined depth in a predetermined portion of the first impurity region adjacent to the drain;forming interlayer dielectric film at a predetermined thickness on the whole surface of the substrate;forming contact holes whereby the contact holes simultaneously exposes predetermined portions of the first and second impurity regions;forming a third impurity regions of the second conductivity type of a high impurity concentration in the exposed portions;forming interconnection lines electrically connecting with the third impurity regions by filling up the contact holes.