Patent ID: 6636945
Filing Date: 2003-10-21
Classification: G06F

Abstract:
A prefetch system in a computer system having a processor, a cache memory, and a main memory, the prefetch system comprising:means for setting a variable indicating a prefetch interval into a register in accordance with a software being executed in said computer system; a load history table adapted to store a plurality of previous transfer request addresses of cache miss load requests issued by said processor; a first comparator for comparing a present transfer request address of a present cache miss load request with said previous transfer request addresses stored in the load history table plus a constant; a second comparator for comparing said present transfer request address with said previous transfer request addresses stored in the load history table minus the constant; and transfer-requesting means for generating a data transfer request which designates a prefetch target address to prefetch data therefrom if any of comparison results of said first and second comparators is true and for sending the data transfer request to the main memory, wherein said prefetch target address is equal to said present transfer request address plus said prefetch interval if a comparison result of said first comparator is true and said prefetch target address is equal to said present transfer request address minus said prefetch interval if a comparison result of said second comparator is true.