Patent ID: 6604179
Filing Date: 2003-08-05
Classification: G06F

Abstract:
An apparatus, comprising:a first-in-first-out buffer containing a plurality of addressable storage locations; a write pointer coupled to the first-in-first-out buffer to point to a first one of the addressable storage locations as an input location; a first read pointer coupled to the first-in-first-out buffer to point to a second one of the addressable storage locations as a first output location; a second read pointer coupled to the first-in-first-out buffer to point to a third one of the addressable storage locations as a second output location; a first clock coupled to the first-in-first-out buffer to clock a destination address for a memory data request into the first-in-first-out buffer at the input location; a second clock coupled to the first-in-first-out buffer to clock the destination address from the first-in-first-out buffer at the first output location; and a third clock coupled to the first-in-first-out buffer to clock the destination address from the first-in-first-out buffer at the second output location; wherein the first output location is to provide advance notice that data requested from a memory device is to be available and the second output location is to subsequently provide notice that the data requested from the memory device is available.