Patent ID: 6041008
Filing Date: 2000-03-21
Classification: G11C

Abstract:
A method for programming at last two SRAM cells located in a SRAM array comprising a plurality of memory cells to function as a ROM cell and permanently store a logic state, each of said plurality of memory cells having a ground connection and a pair of bit lines associated with it, said method comprising the steps of:connecting said pair of bit lines associated with a first of said plurality of memory cells together;connecting said pair of bit lines associated with a second of said plurality of memory cells together;maintaining said ground connection or opening said ground connection of said first of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said first of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection;maintaining said ground connection or opening said ground connection of said second of said plurality of memory cells, wherein a signal at said connection of said pair of bit lines associated with said second of said plurality of memory cells will be produced, said maintaining of said ground connection causing a different signal at said connection of said pair of bit lines than said opening of said ground connection;reading said produced signals at said connection of said pair of bit lines associated with said first of said memory cells and said connection of said pair of bit lines associated with said second of said memory cells; andoutputting a signal based on said read produced signals associated with said stored logic state.