Patent ID: 6363026
Filing Date: 2002-03-26
Classification: H03M

Abstract:
An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k, the device comprising:an row counter responsive to B clock pulses, for outputting a carry signal when the row counter counts to Bâˆ’1, for outputting the 0 value when the first row address is output, for outputting the added value of offset value F and the previous output value of the row counter, and for generating a carry signal when the B clock pulses are completed, wherein the B is the number of rows; a column counter for increasing a count value in increments of one in response to the carry signal; a mapper for permuting the output of the column counter according to a predetermined permutation rule; and an adder for generating a read address by using the output of the row counter as the most significant bits(MSB) of the read address and by using the output of the mapper as the least significant bits(LSB) of the read address.