Patent ID: 7581079
Filing Date: 2009-08-25
Classification: G06F

Abstract:
1. A multiprocessing system operative to execute arithmetic instructions comprising: a first memory node (MN) comprising a first instruction bus that receives only memory read operation type instructions, a second instruction bus that receives only memory write operation type instructions, and a memory, the memory having a memory output coupled to a first MN output and a memory input coupled to a first MN input, the first memory node decodes and executes a memory read instruction which accesses a source operand from the memory and provides it to the first MN output and the first memory node decodes and executes a memory write instruction which stores a result data value available from the first MN input in the memory; and an arithmetic logic unit (ALU) node comprising a third instruction bus that receives only arithmetic operation type instructions and an execute unit (EU), the EU having an EU input coupled to an ALU node input and an EU output coupled to an ALU node output, the ALU node input coupled through a first network to a plurality of memory nodes including the first MN output and the ALU node output coupled through a second network to the plurality of memory nodes including the first MN input, the ALU node decodes and executes an arithmetic instruction that operates on the source operand provided as an input to the execution unit after a latency to fetch the source operand from the memory through the first network by the start of the execution cycle for the arithmetic instruction, the source operand provided in response to the execution of the memory read instruction, and the EU generates a result of the execution of the arithmetic instruction by the start of the execution cycle for the memory write instruction, the result provided through the second network to the first MN input as the result data value to be stored in the memory in response to the execution of the memory write instruction.