Patent ID: 9038076
Filing Date: 2015-05-19
Classification: G06F

Abstract:
1. A controller for a multicore processor architecture comprising a plurality of interconnected processor elements each communicatively coupled to the controller, the controller comprising: an input configured to receive a plurality of thread parameter indicators indicative of a plurality of parameters relating to the function, identity, or execution location of at least one thread within the multicore processor architecture; a plurality of hardware debug machines, each configured to compare at least one received thread parameter indicator with a first plurality of predefined criteria representative of a thread parameter indicator of interest, and to generate a trace enable signal in response to the comparison; and a static events filter communicatively coupled to each of the plurality of debug machines and configured to compare each received thread parameter indicator with a second plurality of predefined criteria based on one or more trace enable signals, and to generate a trace output for a trace buffer based on the plurality of thread parameter indicators and the result of the comparisons with the second plurality of predefined criteria.