Patent ID: 6580637
Filing Date: 2003-06-17
Classification: G11C

Abstract:
A semiconductor memory architecture comprising:two memory banks each containing respective memory locations; for each memory bank, respective circuits for selecting the memory locations in the memory bank and respective circuits for reading the data contained in the selected memory locations in the memory bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, comprising a single data-transfer structure that can be assigned selectively to one memory bank at a time and that comprises storage means for storing the most recent datum read by the reading circuits, and output driver circuits that can be activated selectively in order to transfer the contents of the registers to the data output terminals of the memory; an addressing structure comprising, for each memory bank, a respective circuit for the sequential scanning of the memory locations of the memory bank, operatively connected to the respective circuits for selecting the locations of the memory bank; first circuit means for initializing the sequential scanning circuits by means of an address supplied from outside the memory and corresponding to an origin location, the first circuit means being sensitive to a first control signal from outside the memory and indicative of the presence of the address corresponding to the origin location, second circuit means for bringing about a selective updating of the sequential scanning circuits so as to bring about, starting from the origin location, sequential access to further locations addressed by the addressing structure by accessing the two memory banks alternately, by an interleaved method, third circuit means for managing the reading circuits of the two memory banks in accordance with the interleaved method so that two reading processes are executed contemporaneously, but offset in time, in the two memory banks, fourth circuit means for bringing about the selective assignation of the data-transfer structure to the memory bank currently being accessed, in accordance with the interleaved method, and an internal timing structure for controlling the first, second, third and fourth circuit means, the data-transfer structure, and the addressing structure in accordance with second control signals from outside the memory.