Patent ID: 6534824
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A memory cell array comprising:a plurality of memory cells located in an array portion of a Si-containing substrate which are arranged in rows and columns, each memory cell including a double-gated vertical metal oxide semiconductor field effect transistor (MOSFET) having exposed gate conductor regions and two gates formed on opposing sidewalls of said MOSFETs, wherein one of the opposing sidewalls also includes a confined buried-strap region; a plurality of wordlines overlaying said double-gated vertical MOSFETs and in contact with said exposed gate conductor regions, said wordlines being arranged in said column direction; a plurality of bitlines that are orthogonal to said wordlines; trench isolation regions located adjacent to said rows of memory cells, wherein said trench isolation regions have a depth that is deeper than abutting bitline diffusion regions; and a plurality of punch through stop regions located in said Si-containing substrate, wherein said plurality of punch through stop regions in said column direction overlap each other under said bitlines and serve to electrically isolate adjacent buried-strap regions from each other.