Patent ID: 7511328
Filing Date: 2009-03-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: an isolation layer provided in an area of a semiconductor substrate and defining an active region; a gate electrode traversing the active region; a source region provided in the active region at one side of the gate electrode; a drain region provided in the active region at a second side of the gate electrode; a first interlayer insulating layer covering the semiconductor substrate having the gate electrode; a source landing pad, which passes through the first interlayer insulating layer, that is provided on and electrically connected to the source region; a drain landing pad, which passes through the first interlayer insulating layer, that is provided on and electrically connected to the drain region; and a pad extending part laminated on at least one of the source landing pad and the drain landing pad and having an upper surface which is located above upper surfaces of the source landing pad and the drain landing pad, wherein the pad extending part is laminated on the source landing pad, the pad extending part is misaligned with the source landing pad and wherein the pad extending part overlaps with the upper surface of the source landing pad by at least a half of a maximum contact area of the source landing pad, wherein a distance between the pad extending part and the drain landing pad is greater than a distance between the source landing pad and the drain landing pad.