Patent ID: 6025230
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method for fabricating a MOSFET device supported on a substrate comprising steps of:(a) growing an oxide layer on said substrate and depositing a polysilicon layer followed by forming an oxide cap layer overlying said polysilicon layer;(b) applying a gate mask for anistorpically dry-etching a plurality of polysilicon-with-oxide-cap segments including a plurality of inner gate-segments each having a gate oxideplug opening and a field plate annular segment and an equal potential ring annular segment separated by a termination oxide-plug gap wherein said gate oxide-plug openings and said termination oxide-plug gap having an aspect ratio equal to or greater than 0.5;(c) depositing a NSG layer overlying said top surface followed by applying an anisotropic dry etch for selectively removing said NSG layer, and forming an oxide plug filling said gate oxide-plug openings and filling said termination oxide-plug gap between said field plate and said equal potential ring (EQR) polysilicon segments, and a plurality of side wall spacers around said gate-segments;(d) implanting a body dopant followed by a body diffusion for forming body regions;(e) performing a high energy body dopant implant for forming deep high concentration body dopant regions in said body region;(f) applying a source mask for implanting a source dopant to form a plurality of source regions;(g) forming an overlying insulation layer covering said MOSFET device followed by applying a dry oxide etch with a contact mask to open a plurality of contact openings saidre-through;(h) performing a low energy body dopant implant to form a shallow high concentration body dopant in said body regions then removing said contact mask;(i) performing a high temperature reflow process for said overlying insulation layer and for driving said source regions and said shallow and deep high concentration body dopant regions into designed junction depths;(j) depositing a metal layer followed by applying a metal mask as a third mask for patterning said metal layer to define a plurality of metal segments by employing an anisotropic dry etch thus defining a plurality of deep-and-narrow gaps between said metal segments wherein each gap having an aspect ratio equal to or greater than 0.5;(k) depositing a passivation layer over an entire top surface and filling said deep-and-narrow gaps between said metal segments; and(l) etching away said passivation layer over said entire top surface without applying a mask while leaving said passivation layer inside said deep-and-narrow gaps substantially intact for serving a function of blocking mobile ions from entering into said MOSFET device.