Patent ID: 8611121
Filing Date: 2013-12-17
Classification: G11C

Abstract:
1. A stacked memory device, comprising: a substrate; a plurality of memory groups sequentially stacked on the substrate, each memory group comprising at least one memory layer; a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups; and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups; wherein the plurality of the Y-decoder layers comprises a plurality of pairs of first and second Y-decoder layers that alternate with the plurality of X-decoder layers, or the plurality of X-decoder layers comprises a plurality of pairs of first and second X-decoder layers that alternate with the plurality of Y-decoder layers.