Patent ID: 8943224
Filing Date: 2015-01-27
Classification: G06F,G11C

Abstract:
1. An integrated circuit device for communicating with a plurality of memory devices, the integrated circuit device comprising: a data interface to transfer read data and write data in respective memory access operations via a shared data path coupled in common to each memory device of the plurality of memory devices; control logic to (i) receive identification information from each memory device of the plurality of memory devices concurrently via the data interface, (ii) generate one or more device-select values based on the identification information, and (iii) output the device-select values to the plurality of memory devices via the data interface, the one or more device-select values enabling unique identification of a respective memory device of the plurality of memory devices; and a command interface to output a first command to the plurality of memory devices, the first command instructing each memory device of the plurality of memory devices to output the identification information to the data interface, wherein the first command instructs each memory device of the plurality of memory devices to provide identification information to the data interface, via the shared data path, using a signaling mode in which only a first data state of two possible data states is signaled by each memory device of the plurality of memory devices on respective links of the shared data path.