Patent ID: 6256228
Filing Date: 2001-07-03
Classification: G11C

Abstract:
A method for erasing a nonvolatile semiconductor storage device, said device comprising:a memory cell array divided into blocks in each of which memory cells are arranged in a matrix form on a semiconductor substrate, each of the memory cells being comprised of a floating gate type field-effect transistor that has a control gate, a drain and a source and is able to electrically be programmed and erased by using a Fowler-Nordheim tunneling phenomenon;word lines each connected to control gates of the memory cells arranged in an identical row;sub-bit lines each connected to the drains or the sources of the memory cells arranged in an identical column; andmain bit lines each connected to an associated sub-bit line so as to form a layered structure together with the associated sub-bit line, wherein:in an erase operation of a selected block of the memory cell array, a first negative voltage is applied to the semiconductor substrate, a first positive voltage is applied to the word lines of an unselected block of the memory cell array, and a reference voltage is applied to the sub-bit lines of the unselected block so that memory cells in a low threshold voltage state within the unselected block are turned on, and that a channel layer formed in each of the memory cells which have been turned on comes to have the reference voltage.