Patent ID: 7739634
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. Verification equipment of a semiconductor integrated circuit comprising: a circuit net list extraction section that extracts a net list of a circuit; a circuit simulation execution section that executes a circuit simulation, based on the extracted net list; a finite impedance judgment section that judges the existence or nonexistence of finite impedances in the circuit; a floating error terminal judgment section that judges the existence or nonexistence of floating error terminals by measuring the existence or nonexistence of the finite impedances; a true floating error terminal judgment section that adds any one of a P channel-type transistor and an N channel-type transistor to terminals of the circuit where it is judged that there are floating error terminals by the floating error terminal judgment section and calculates changes in potential at the terminals, and adds the other of the P channel-type transistor and the N channel-type transistor to the terminals and calculates changes in potential at the terminals; and an output section that outputs a judgment result of the floating error terminal judgment section and a judgment result of the true floating error terminal judgment section.