Patent ID: 8017489
Filing Date: 2011-09-13
Classification: H01L

Abstract:
1. A method for fabricating a p-type semiconductor structure comprising: providing a semiconductor substrate that comprises a carbon alloyed semiconductor surface layer with a tensile stress, wherein the carbon alloyed semiconductor surface layer is present in direct contact with an underlying unstrained semiconductor layer of silicon; forming a gate electrode on the carbon alloyed semiconductor surface layer of the semiconductor substrate; etching the carbon alloyed semiconductor surface layer of the semiconductor substrate while using the gate electrode as a mask stopping on the underlying unstrained semiconductor layer of silicon to form a carbon alloyed semiconductor channel aligned beneath the gate electrode; and forming laterally backfilling SiGe regions adjoining a remaining portion of the carbon alloyed semiconductor surface layer, wherein the SiGe regions do not include carbon and provide a source region and a drain region having a dopant of a p-type conductivity, wherein the SiGe regions convert the tensile stress in the remaining portion of the carbon alloyed semiconductor surface layer to a compressively stressed channel in which carbon of the carbon alloy semiconductor surface layer inhibits diffusion of the dopant of the p-type conductivity into the compressively stressed channel.