Patent ID: 6472273
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A method of manufacturing a flash memory device, comprising the steps of:providing a semiconductor substrate in which a device separation film is formed; forming a tunnel oxide film and a first polysilicon layer on said semiconductor device; subsequently patterning said tunnel oxide film and said first polysilicon layer to form a floating gate; forming a mask to expose a portion in which a source region will be formed; removing said device separation film at the exposed portion; forming a dielectric film comprising a lower oxide film, a nitride film and an upper oxide film on the entire structure, performing an annealing process, and then forming a second polysilicon layer on said dielectric film; sequentially removing said polysilicon layer, said upper oxide film, and said nitride film in a portion in which said source region and a drain region will be formed, and injecting impurity ions into said semiconductor substrate at a portion in which said lower oxide film remains to form said source region and said drain region; after removing said remaining lower oxide film, sequentially forming a third polysilicon layer and a tungsten silicide layer on the entire structure and then patterning said third polysilicon layer and said tungsten suicide layer to form a control gate; and performing an annealing process for activating the impurity ions injected into said source region and said drain region.