Patent ID: 6174811
Filing Date: 2001-01-16
Classification: C23C,H01L

Abstract:
A process for forming an interconnect, comprising:positioning a patterned substrate into a first high density physical vapor deposition chamber and depositing a barrier layer on the substrate, wherein the barrier layer is selected from the group of tantalum, tantalum nitride, and combinations thereof;positioning the substrate into a second high density physical vapor deposition chamber and depositing a first copper layer on the barrier layer; anddepositing a second copper layer on the first copper layer;wherein depositing the barrier layer comprises delivering a bias between about 0.5 kW and about 5 kW to a target, delivering RF power between about 0.5 kW and about 3 kW to a source coil, and delivering a bias between about) W and about 500 W to the substrate.