Patent ID: 7872937
Filing Date: 2011-01-18
Classification: G06F

Abstract:
1. A dynamic random access memory (DRAM) controller with a data driver circuit comprising: a first latch having an input for receiving a processor data signal, a clock input for receiving a processor clock signal, and an output; an extension logic circuit having an input coupled to said output of said first latch, a control input for receiving a control signal, and an output, wherein said extension logic circuit delays said input selectively in response to said control signal; a second latch having an input coupled to said output of said extension logic circuit, a clock input for receiving a second clock signal, and an output for providing an output signal: and a data timing, circuit having an input for receiving a first delay line select signal, and an output for providing said control signal, wherein said data timing circuit activates said control signal to cause said extension logic circuit to delay said input by substantially one-half of a period of said processor clock signal when said first delay line select signal is greater than a predetermined value.