Patent ID: 7312503
Filing Date: 2007-12-25
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells each of which includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor which has one end of its current path connected to one end of a current path of the first MOS transistor, the second MOS transistor in a selected one of the memory cells being turned on when data is read from the first MOS transistor in the selected one of the memory cells; a plurality of local bit lines each of which connects other ends of the current paths of the first MOS transistors; a global bit line to which two or more of the local bit lines are connected in common; a first switch element which makes a connection between the local bit lines and the global bit line; and a latch circuit which is connected to the global bit line and holds data to be written into the memory cells.