Patent ID: 7208998
Filing Date: 2007-04-24
Classification: G05F

Abstract:
1. A bias circuit for providing at least first and second bias signals for biasing at least one of a cascode current source and a cascode current sink, the bias circuit comprising: a first transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal being coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal; a first resistive element including first and second ends, the first end of the first resistive element being coupled to the second source/drain terminal of the first transistor; a second transistor including first and second source/drain terminals and a gate terminal, the gate terminal of the second transistor being connected to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor; a third transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal of the third transistor being coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor being coupled to the second end of the first resistive element, and the gate terminal of the third transistor being coupled to the first source/drain terminal of the second transistor; and a compensation circuit operative to subtract at least a portion of current flowing through the first resistive element, such that a net current flowing through the first resistive element is substantially a function of a resistance of a second resistive element which is ratio matched to a resistance of the first resistive element.