Patent ID: 7827463
Filing Date: 2010-11-02
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device having a function of correcting a defective bit by using a code which enables correction of a single-bit error and includes data corresponding to successive addresses in an address range designated for a burst-mode operation, comprising: memory cells; a holding circuit to hold one or both of at least a portion of a first set of data bits and at least a portion of a second set of data bits, wherein the first set of data bits and a set of parity bits constitute at least a portion of the code and are written in the memory cells in one of a plurality of write cycles included in a burst write operation, the set of parity bits is generated on the basis of the first set of data bits, and the second set of data bits is read from the memory cells prior to the burst write operation; and a parity updating circuit to update, in a final write cycle of the plurality of write cycles in the burst write operation, the set of parity bits written in the memory cells in the one of the plurality of write cycles, on the basis of the first set of data bits.