Patent ID: 9076517
Filing Date: 2015-07-07
Classification: G11C

Abstract:
1. A memory apparatus, comprising: a plurality of gated phase-change memory cells having s≧2 programmable cell-states, the cells each having a gate and being arranged in series between a source and drain; a bias voltage generator configured to apply a bias voltage to the gate of each cell; a controller configured to control the bias voltage generator, in a write operation for programming the state of a cell, to apply a first bias voltage to the gate of each cell except a first addressed cell for the write operation, wherein application of the first bias voltage to a cell reduces the cell resistance such that application of a programming signal between the source and drain effects programming only of the addressed cell; wherein the s programmable cell-states include an amorphous RESET state and at least one crystalline state, and further comprising, in the write operation for programming the first addressed cell, reading of the first addressed cell to obtain an indication of cell-state before programming the first addressed cell, and controlling the bias voltage generator by applying a second bias voltage to the gate of the first addressed cell to increase the cell resistance only when programming the first addressed cell from the crystalline state to the RESET state, as determined by indicating the crystalline state from the reading of the first addressed cell, wherein the second bias voltage is not applied when reprogramming the cell from an indicated RESET state to the RESET state.