Patent ID: 6858890
Filing Date: 2005-02-22
Classification: G11C,H01L

Abstract:
1. An integrated circuit (IC) comprising: a first memory cell including a first transistor with first and second diffusion regions and a first capacitor with a capacitor dielectric layer between top and bottom electrodes, the first capacitor coupled to the first diffusion region of the first transistor; a second memory cell including a second transistor with first and second diffusion regions and a second capacitor with a dielectric layer between top and bottom electrodes, the second capacitor coupled to the first diffusion region of the second transistor; the second diffusion regions of the first and second transistors form a common diffusion region; a first contact coupled to the common diffusion region of the transistors, wherein a height of the first contact is substantially planar or below a lower surface bottom electrodes of the capacitors; sidewall dielectric spacers lining sidewalls of the capacitors, when the sidewall dielectric spacers are formed, an upper surface of the first contact plug is exposed; an interlevel dielectric layer covering the substrate and capacitors, including the sidewall dielectric spacers; and a non-planar strap contacting the top electrodes of the first and second capacitors and the first contact, the non-planar strap is isolated from the capacitor dielectric layer and bottom electrode of the capacitors by the sidewall dielectric spacers wherein, then non-planar strap and spacers avoids the use of contact vias associated with the top electrodes and the first contact.