Patent ID: 8943455
Filing Date: 2015-01-27
Classification: G06F,H01L

Abstract:
1. A method, comprising: defining standard cells including at least one transistor and polysilicon dummy structures formed on cell edges; forming a pre-layout schematic netlist from an input gate level netlist using the standard cells, wherein the pre-layout schematic netlist includes a three terminal device corresponding to each of the polysilicon dummy structures; using the gate level netlist, performing an automated place and route process to form a layout netlist for fabricating an integrated circuit using the standard cells; laying out the standard cells and laying out routing connections between the standard cells to form a layout for the integrated circuit, using the layout netlist; extracting using a computer from the layout for the integrated circuit a post-layout schematic netlist the post-layout schematic netlist including a three terminal device for each polysilicon dummy structure in the layout netlist, wherein, for each abutted polysilicon dummy structure in the layout, providing in the post-layout schematic netlist a pair of three terminal devices each having a gate terminal that is coupled one to another and each having a body terminal that is coupled one to another; and comparing the pre-layout schematic netlist to the post-layout schematic netlist.