Patent ID: 7543265
Filing Date: 2009-06-02
Classification: G06F

Abstract:
1. A method of synthesizing a logic design for technology mapping on a target device, said method comprising: performing a high level synthesis of the logic design to generate a net list; performing a multilevel synthesis on the net list to generate a gate implementation of the net list; and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device, wherein, during the performance of the high level synthesis of the logic design into the net list, technology mapping is further performed on a selected portion of the logic design to improve the predictability of the power, area and/or frequency of the logic design without substantially degrading the performance of the power, area and frequency of the logic design, wherein, during the technology mapping performed during the high level synthesis a set of rules is defined for performing the technology mapping, the defined set of rules comprising: (i) performing a first traversal of the logic design; (ii) stopping the first traversal at a set of soft sources in the logic design with only one destination; (iii) performing a second traversal of the logic design; (iv) stopping the second traversal at a set of soft sources in the logic design generated by a gate that has only a set of hard and firm sources; (v) performing a third traversal of the logic design; (vi) stopping the third traversal at any soft source; (vii) performing a fourth traversal of the logic design; and (viii) stopping the fourth traversal at in the logic design any soft sources or firm sources with less than a predetermined threshold number of fan-outs.