Patent ID: 6647470
Filing Date: 2003-11-11
Classification: G11C

Abstract:
A memory circuit comprising:a data buffer coupled to a storage array of said memory circuit; a logic circuit for receiving input data associated with a write command, said logic circuit being coupled to said data buffer and said storage array; a command decoder coupled to said logic circuit and said data buffer, said command decoder providing a first control signal to said logic circuit; wherein when said input data associated with said write command is received by said logic circuit, said logic circuit in response to a first control signal sends said input data directly to said storage array or sends said input data to said data buffer and if said input data is sent to said data buffer, said command decoder sends a second control signal to said data buffer at a predetermined time when input/output gates associated with said storage array are not being used, and said data buffer in response to said third control signal sending said input data from said data buffer to said storage array.