Patent ID: 6148394
Filing Date: 2000-11-14
Classification: G06F

Abstract:
An apparatus for out of order execution of instructions, the apparatus comprising:(a) a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocessor, the instruction data comprising:(i) address information for the instruction, the address information being held in an address information field of the respective entry;(ii) order information for the instruction, the order information being held in an order information field of the respective entry for indicating the order of the corresponding instruction in relation to other instructions;(iii) out of order information, the out of order information being held in an out of order information field of the respective entry for indicating that a newer instruction using data at the address corresponding to the address information field has completed before the current entry;(iv) data modification information for the instruction, for indicating a possibility of modified data at the address corresponding to the address information field;(b) an out of order comparator for setting the out of order information field of an entry in the mis-queue table upon the completion of a completing instruction, the out of order information field of a compared entry being set if the completing instruction comprises a newer instruction which uses data at the address corresponding to the address information field in the compared entry;(c) a modification comparator for comparing address information in the address information field in an entry in the mis-queue table to a possibly modified address, wherein the modification field in the entry is marked to indicate modified data at the address if the possibly modified address is comparable to the address information in the instruction entry being compared.