Patent ID: 6944699
Filing Date: 2005-09-13
Classification: G06F

Abstract:
1. In a computer system that has a hardware processor including an interrupt table pointer register and an operating system (OS), which includes a first interrupt vector table and a first set of state parameters, and a sub-system, which includes a second interrupt table vector, a second set of state parameters, and is contextually separated from the OS, a method for enabling interrupt handling in the sub-system comprising the following steps: in an OS context, accessing the interrupt table pointer register and setting the interrupt table pointer register to point to the first interrupt table vector, and storing the second set of state parameters, whereby interrupts are routed for handling to the OS; and in a sub-system context, accessing the interrupt table pointer register and setting the interrupt table pointer register to point to the second interrupt table vector, and storing the first set of state parameters, whereby the interrupts are routed for handling to the sub-system.