Patent ID: 9117790
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A packaging arrangement comprising: a substrate; a multi-memory die disposed on the substrate, wherein the multi-memory die comprises multiple individual memory dies and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is disposed on the multi-memory die such that the multi-memory die is disposed between the substrate and the semiconductor die, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate; a first plurality of bond pads disposed on the first individual memory die; a second plurality of bond pads disposed on the second individual memory die; a third plurality of bond pads disposed (i) on the semiconductor die and (ii) near a first edge of the semiconductor die, wherein one or more of the first plurality of bond pads is coupled to a corresponding one or more of the third plurality of bond pads; a fourth plurality of bond pads disposed (i) on the semiconductor die and (ii) near a second edge of the semiconductor die, wherein the second edge of the semiconductor die is opposite to the first edge of the semiconductor die, and wherein one or more of the second plurality of bond pads is coupled to a corresponding one or more of the fourth plurality of bond pads; a fifth plurality of bond pads disposed (i) on the semiconductor die and (ii) near a third edge of the semiconductor die, wherein the third edge of the semiconductor die is perpendicular to the first edge of the semiconductor die; and a sixth plurality of bond pads disposed on the substrate, wherein one or more of the fifth plurality of bond pads is coupled to a corresponding one or more of the sixth plurality of bond pads.