Patent ID: 6573548
Filing Date: 2003-06-03
Classification: G11C,H01L

Abstract:
A dynamic random access memory (DRAM) cell comprising:a semiconductor substrate having a first conductivity type; a field dielectric region located below an upper surface of the semiconductor substrate and having a cavity located therein, the cavity extending below the upper surface and exposing a sidewall portion of the semiconductor substrate; a capacitor dielectric layer located over the sidewall portion of the semiconductor substrate and an adjacent upper surface of the semiconductor substrate; a capacitor region located in semiconductor substrate below the capacitor dielectric layer; a capacitor electrode located over the capacitor dielectric layer, wherein a portion of the capacitor electrode extends into the cavity; a gate dielectric layer located over the upper surface of the semiconductor substrate; a gate electrode formed over the gate dielectric layer; and a source region of the second conductivity type located in the semiconductor substrate between the gate electrode and the capacitor electrode, wherein the source region in continuous with the capacitor region.