Patent ID: 8830641
Filing Date: 2014-09-09
Classification: H02H

Abstract:
1. A circuit for use in an electrostatic discharge (ESD) protection device, the circuit comprising: a first NMOS device including a first gate, a first source, and a first drain; a second NMOS device including a second gate, a second source, and a second drain, wherein the first source is coupled to the second drain; a first inverter including a first higher voltage power node, a first lower voltage power node, a first input, and a first output, wherein the first output is coupled to the first gate; a second inverter including a second higher voltage power node, a second lower voltage power node, a second input, and a second output, wherein the second output is coupled to the second gate and wherein the second higher voltage power node is directly connected to the first output; a voltage divider coupled to the first lower voltage power node; and a trigger circuit coupled to the first input and the second input, wherein the trigger circuit is configured to sense an ESD event.