Patent ID: 6480069
Filing Date: 2002-11-12
Classification: H03F

Abstract:
An active load circuit, comprising:first current mirror circuit for inputting input current of the one of differential input current to a first input terminal of current input transistors and for outputting output current of the one of differential output current from a first output terminal of current output transistors; second current mirror circuit for inputting input current of the other of differential input current to a second input terminal of current input transistors and for outputting output current of the other of differential output current from a second output terminal of current output transistors; first impedance circuit having one end connected to a reference potential connection terminal of the current input transistor in the first current mirror circuit and to the reference potential connection terminal of the current output transistor in the second current mirror circuit, and the other end connected to the reference potential; and second impedance circuit having one end connected to the reference potential connection terminal of the current input transistor in the second current mirror circuit and to the reference potential connection terminal of the current output transistor in the first current mirror circuit, and the other end connected to the reference potential, wherein the first and second impedance circuits have first and second MOS transistors, respectively, and wherein the gate terminal of the first MOS transistor is connected to second input terminal of the second current mirror circuit, and the gate terminal of the second MOS transistor is connected to first input terminal of the first current mirror circuit.