Patent ID: 7966589
Filing Date: 2011-06-21
Classification: G11C,H03K

Abstract:
1. A design structure embodied in a format readable by a computer, stored on a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure, when executed by the computer providing elements of a dynamic state-saving latch electrical circuit, comprising: a charge device; an integrated recovery mechanism; and a single supply voltage rail connected to said charge device, wherein when said supply voltage rail is active, said charge device maintains a state of said charge device and wherein when said supply voltage rail is inactive, said integrated recovery mechanism maintains a state of said charge device; a hold signal generator connected to said integrated recovery mechanism, wherein when said supply voltage rail is inactive, said hold signal generator is adapted to generate a hold signal and to provide said hold signal to said integrated recovery mechanism, wherein said hold signal generator provides said hold signal from one of: a voltage domain that does not comprise said latch and is active; and an external source not on said voltage domain.