Patent ID: 7511649
Filing Date: 2009-03-31
Classification: H03K

Abstract:
1. A circuit to convert a first logic signal having a first range to a second logic signal having a second range, comprising: a first metal oxide semiconductor (MOS) transistor to selectively couple an output node to a first reference voltage when the output node is to be in a first state; a second MOS transistor having a source coupled to the output node and a gate coupled to a bias voltage; a current source circuit to selectively bias the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state; a memory circuit having an input coupled to the output node and an output, the memory circuit configured to temporarily store a value indicative of the output node in the first state when the output node transitions from the first state to the second state; and a discharging circuit coupled to the output node and a second reference voltage, the discharging circuit configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state, the discharging circuit having a first input coupled to the output of the memory circuit and a second input coupled to a control signal, the control signal to indicate that the output node is to transition from the first state to the second state.