Patent ID: 6356993
Filing Date: 2002-03-12
Classification: G06F,H04L

Abstract:
A single-instruction multiple-data array processor, comprising:a plurality of processor arrays; and a plurality of data paths for interconnecting the plurality of processor arrays in at least one row and at least one column to form an N-dimensional array, wherein each processor array located at a respective interior point of the N-dimensional array is connectable to 2N dimensionally adjacent processor arrays, and each first processor array located at a first boundary of at least one pair of dimensionally opposite boundaries of the N-dimensional array is connectable to (1) fewer than 2N dimensionally adjacent processor arrays and (2) at least one second processor array located at a second boundary of the at least one pair of dimensionally opposite boundaries, wherein the at least one second processor array is offset from a processor array at the second boundary corresponding to the first processor array by at least one row or column.