Patent ID: 6046950
Filing Date: 2000-04-04
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:at least two memory cell blocks having a plurality of bit line pairs, respectively;a plurality of sense amplifier blocks arranged between the memory cell blocks, wherein each sense amplifier block has two bit line precharge transistors, one equalization, and two bit line isolation transistors; andan unit precharge-isolation region having a) an width in which two bit line pairs are disposed, wherein the transistors are fabricated in the unit precharge-isolation region, b) two active regions arranged in the unit precharge-isolation region, wherein the precharge and equalization transistors are placed in the other of the active regions, and c) five active to bit line contacts arranged in zigzag within the active regions,wherein three gate electrodes of the transistors are disposed at the corresponding active regions in ""h-l-l"" shape.