Patent ID: 8868829
Filing Date: 2014-10-21
Classification: G11C

Abstract:
1. A method comprising: presenting a plurality of physical memory circuits to a system as a virtual memory circuit simulated by an interface circuit, wherein the virtual memory circuit has at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits, the at least one characteristic comprising a memory capacity and a command operation period for performing a particular operation on the virtual memory circuit, wherein the command operation period is longer than a latency associated with performing a power-saving operation on any one physical memory circuit of the plurality of physical memory circuits to hide the latency associated with performing the power-saving operation from the system, and wherein the plurality of memory circuits are positioned on a dual in-line memory module (DIMM); receiving, at the interface circuit, a first command issued from the system to the virtual memory circuit, for performing the particular operation on the virtual memory circuit; and in response to receiving the first command, 1) performing the particular operation on a first physical memory circuit of the plurality of physical memory circuits, and 2) performing, during the particular operation on the first physical memory circuit, a power-saving operation on a portion of the other physical memory circuits of the plurality of physical memory circuits that are identified by the interface circuit as not currently being accessed by the system responsive to a system command issued to the virtual memory circuit.