Patent ID: 6343370
Filing Date: 2002-01-29
Classification: G03F

Abstract:
A pattern distortion detecting method in a semiconductor manufacturing process comprising the steps of:forming a predicted finished layout pattern based on a design layout pattern or an inspection layout pattern; converting an outline of said predicted finished layout pattern into a polygon to generate a polygonized predicted finished layout pattern; detecting a pattern distortion in said predicted finished layout pattern by logical figure operation of input data of said polygonized predicted finished layout pattern or of said polygonized predicted finished layout pattern and said design layout pattern or inspection layout pattern; forming a plurality of polygonized predicted finished patterns corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; forming a plurality of highly-defined predicted finished patterns by performing graphical operations between each of a plurality of said polygonized predicted finished patterns and said design layout patterns or inspection layout patterns; and merging said plurality of highly-defined predicted finished patterns.