Patent ID: 6742098
Filing Date: 2004-05-25
Classification: G06F

Abstract:
A memory system comprising:a primary memory controller; a memory data bus, having an effective bit-width m, coupled to the primary memory controller; and at least one memory module coupled to the memory data bus, the memory module having a module data bus with an effective bit-width N=RÃ—m, where R is an integer value greater than one, the memory module comprising an interface circuit coupled between the memory data bus and the module data bus, the interface circuit capable of performing m-bit-wide data transfers on the memory data bus, the interface circuit capable of performing N-bit-wide data transfers on the module data bus, the memory data bus comprising a point-to-point bus having one data bus segment connecting the primary memory controller and the first of the at least one memory modules, and one additional segment for each additional memory module, the additional segment connecting the additional memory module to the module immediately preceding it, and a ring data bus segment connecting the last of the memory modules in the memory system.