Patent ID: 6111446
Filing Date: 2000-08-29
Classification: G11C,H03K

Abstract:
A synchronous memory pulse generator comprising:a clock signal generator circuit coupled to receive an input clock signal and provide a plurality of phase shifted output signals including a first clock signal and a second clock signal that is 90 degrees out-of-phase with the first clock signal; anda pulse generator circuit coupled to the clock signal generator circuit for providing first and second output signals having corresponding transitions with minimal skew, the pulse generator circuit comprising:a first pass gate coupled to receive the first clock signal and provide the first output signal on a first output node which is coupled to a drain of a first transistor, the first pass gate being controlled by the second clock signal;a second pass gate coupled to receive the second clock signal and provide the second output signal on a second output node which is coupled to a drain of a second transistor, the second pass gate being controlled by the first clock signal.