Patent ID: 6303419
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method of fabricating a BiCMOS device, on a semiconductor substrate, comprising the steps of:forming a first buried layer, of a first conductivity type, in a first region of the semiconductor substrate, to be used as a PFET CMOS region, forming a second buried layer, of said first conductivity type, in a third region of said semiconductor substrate, to be used as bipolar device region, and forming a third buried layer, of a second conductivity type, in a second region of said semiconductor substrate to be used as an NFET CMOS region;growing an epitaxial silicon layer, containing said first conductivity type;forming a first well region, of a first conductivity type, in a region of said epitaxial silicon layer, directly overlying said first buried layer, forming a second well region, of a second conductivity type, in a region of said epitaxial silicon layer, directly overlying said third buried layer, and forming a doped region, of first conductivity type, in a region of said epitaxial silicon layer, overlying a portion of said second buried layer;forming a first insulator isolation region, in region of said semiconductor substrate, located between said first region, and said second region, of said semiconductor substrate, and forming a second insulator isolation region, located between said second region, and said third region, of said semiconductor substrate;growing a first silicon oxide layer on regions of the top surface of said semiconductor substrate, not covered by insulator isolation regions;depositing a first polysilicon layer;forming a base region, of a second conductivity type, in a region of said epitaxial layer, located in said third region of said semiconductor substrate;forming an emitter opening in said first polysilicon layer, in said third region of said semiconductor substrate, and creating a self-aligned collector, (SIC), region, of said first conductivity type, self aligned to said emitter opening, and with said SIC region located underlying said base region, and overlying said second buried layer;removing portion of said first silicon oxide layer, exposed in said emitter opening;depositing a second polysilicon layer, and doping of said second polysilicon layer with a dopant of said first conductivity type;patterning of said second polysilicon layer, and of said first polysilicon layer to create: a first polysilicon gate structure, on said first silicon oxide layer, in said first region of said semiconductor substrate; a second polysilicon gate structure, on said first silicon oxide layer, in said second region of said semiconductor substrate; and a polysilicon emitter structure, contacting a portion of said base region, exposed in said emitter opening, in said third region of said semiconductor substrate;growing a second silicon oxide layer on exposed surfaces: of said first polysilicon gate structure; of said second polysilicon gate structure; and of said polysilicon emitter structure;forming a lightly doped source/drain region, of a first conductivity type, in an area of said second region of said semiconductor substrate, not covered by said second polysilicon gate structure, and forming a lightly doped source/drain region, of a second conductivity type, in an area of said first region of said semiconductor substrate, not covered by said first polysilicon layer;forming insulator spacers on the sides of said first polysilicon gate structure, on the sides of said second polysilicon gate structure, and on the sides of said polysilicon emitter structure;forming a heavily doped source/drain region, of a first conductivity type, in an area of said second region of said semiconductor substrate, not covered by said second polysilicon gate structure, or by said insulator spacers;forming a heavily doped source/drain region, of a second conductivity type, in an area of said first region of said semiconductor substrate, not covered by said first polysilicon gate structure, and not covered by said insulator spacers; andperforming an anneal cycle to create an emitter region, of a first conductivity type, in a top portion of said base region, in said third region of said semiconductor substrate.