Patent ID: 6941485
Filing Date: 2005-09-06
Classification: H03L,H04H,H04J,H04L,Y02D

Abstract:
1. A clock supply circuit supplying a processing clock signal for processing an input signal having a predetermined frequency, said clock supply circuit comprising: a clock generating means generating a intermediate clock signal for processing said input signal, a first clock signal higher in frequency than the intermediate clock signal, and a second clock signal lower in frequency than the intermediate clock signal, a clock switching means selecting any of the intermediate clock signal, the first clock signal or the second clock signal, supplying the selected one as said processing clock signal to the signal processing, and a clock switching control means for processing said input signal with use of the selected processing clock signal, detecting an amount out-of-sync of the processing clock signal with respect to the input signal in accordance with the processing result, and controlling the clock switching in accordance with said detected amount out-of-sync, wherein said clock generating means further comprises: an oscillation means generating a reference clock signal having a predetermined reference frequency, a multiplying means generating a multiplied clock signal obtained by multiplying said reference clock signal, and a frequency division means for dividing said multiplied clock signal by different frequency division ratios to generate said intermediate clock signal, said first clock signal and said second clock signal, respectively, and wherein the clock switching means switches said clock signals using a predetermined time span as a switching time unit wherein at the start and ending time phases of said intermediate clock signal, said first and second clock signals match.