Patent ID: 6377650
Filing Date: 2002-04-23
Classification: G06F

Abstract:
A circuit structure for a counter register in a multi-clock system, including a host data bus having an addressing signal, a host data bus clock, and a data signal comprising:a post write/read buffer comprising at least one data buffer operable to receive data from the host data bus and thereby releasing the host data bus for other functions; a cycle timer coupled to the post write/read buffer to receive data from the post write/read buffer, the cycle timer operable to count the cycle periods of an internal counter clock; a sample and hold circuit coupled to the cycle timer operable to sample a current count value of the cycle timer; and a control circuit coupled to the post write/read buffer, the cycle timer, and the sample and hold circuit operable to generate an addressing scheme to determine which byte of data is stored in the post write/read buffer, the control circuit operable to synchronize the host data bus clock and the internal counter clock, the control circuit operable to control the transfer of data from the post write/read buffer to the cycle timer.