Patent ID: 6605506
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A method of fabricating non-volatile semiconductor memory device array using a shallow-trench-isolation structure for the channel width of non-volatile semiconductor memory devices having highly adjustable coupling ratio for the self-aligned floating gate, said method comprising:providing a semiconductor substrate; forming a multilayer structure of a first thermal silicon-oxide layer, a first polycrystalline-silicon layer and a first masking silicon-nitride layer sequentially; patterning said multilayer structure using a patterned first masking photoresist to define said channel width of said non-volatile semi-conductor memory device array by selectively removing said first masking silicon-nitride layer, said first polycrystalline-silicon layer, said first thermal silicon-oxide layer and then stripping said patterned first masking photoresist; depositing a first conformable silicon-oxide layer over said patterned multilayer structure followed by anisotropically etching said first conformable silicon-oxide layer to form the first silicon-oxide spacers on the etched sidewalls of said first masking silicon-nitride layer, said first polycrystalline-silicon layer and said first thermal silicon-oxide layer; etching said semiconductor substrate to form the shallow trenches in a self-aligned manner; oxidizing the etched trench surface of said semiconductor substrate to form a thin second thermal silicon-oxide layer; implanting boron impurities into the semiconductor surface of said oxidized shallow trenches to form the channel stops; depositing a thick conformable silicon-oxide film over said oxidized multilayer structure to fill said shallow trenches; planarizing the structure surface using chemical-mechanical-polishing (CMP) to remove the filled excess silicon-oxides over said first masking silicon-nitride layer; etching said planarized filling silicon-oxide layers and said first silicon-oxide spacers in a self-aligned manner to a depth of d, wherein d is approximately equal the thickness t of said first masking silicon-nitride layer plus the thickness of said first polycrystalline-silicon layer; depositing a first conformable polycrystalline-silicon layer followed by anisotropically etching said first conformable polycrystalline-silicon layer to form the first polycrystalline-silicon spacers on the exposed sidewalls of said first masking silicon-nitride layer and first polycrystalline-silicon layer; removing said first masking silicon-nitride layer using a wet-chemical solution of hot phosphoric acid or anisotropic etching; depositing a first dielectric layer over said first polycrystalline-silicon layers, said first polycrystalline-silicon spacers and said etched planarized filling silicon-oxide layers; and implanting phosphorous (or boron) impurities across said first dielectric layer into said first polycrystalline-silicon layers and said first polycrystalline-silicon spacers.