Patent ID: 6222753
Filing Date: 2001-04-24
Classification: H01L

Abstract:
An SRAM cell arrangement comprising a plurality of memory cells, wherein each memory cell respectively comprises:a substrate, a first vertical MOS transistor, a second vertical MOS transistor, a third vertical MOS transistor, a fourth vertical MOS transistor, a fifth vertical MOS transistor, a sixth vertical MOS transistor, a word line, a first bit line, a second bit line, a first conductive structure and a second conductive structure; andwherein the third and fourth transistors are complementary to the first, second, fifth and sixth transistors;wherein a first source/drain region of the first transistor is connected to both a first source/drain region of the second transistor and a first voltage terminal;wherein a second source/drain region of the first transistor is connected to each of a first source/drain region of the third transistor, a first source/drain region of the fifth transistor, a gate electrode of the second transistor and a gate electrode of the fourth transistor;wherein a gate electrode of the first transistor is connected to each of a second source/drain region of the second transistor, a first source/drain region of the fourth transistor, a gate electrode of the third transistor and a first source/drain region of the sixth transistor;wherein a second source/drain region of the third transistor is connected to both a second source/drain region of the fourth transistor and a second voltage terminal;wherein a second source/drain region of the fifth transistor is connected to the first bit line;wherein a gate electrode of the fifth transistor is connected to both a gate electrode of the sixth transistor and the word line;wherein a second source/drain region of the sixth transistor is connected to the second bit line;wherein the first and second transistors are arranged at a second side wall of a first trench formed in the substrate;wherein the fifth and sixth transistors are arranged at a second side wall of a second trench formed in the substrate which is parallel to the first trench;wherein the third and fourth transistors are arranged at a first side wall of a fourth trench formed in the substrate which is parallel to the second trench;wherein the word line is arranged along the second side wall of the second trench;wherein the first conductive structure is connected to the first voltage terminal;wherein the second conductive structure is connected to the second voltage terminal;wherein the first conductive structure is arranged along the first trench;wherein the second conductive structure is arranged along the fourth trench;wherein the first bit line and the second bit line are both arranged transversely relative to the word line and are arranged parallel to one another;wherein the first source/drain region of the first transistor and the first source/drain region of the second transistor are both connected to the first conductive structure; andwherein the second source/drain region of the third transistor and the second source/drain region of the fourth transistor are both connected to the second conductive structure.