Patent ID: 7921320
Filing Date: 2011-04-05
Classification: G06F,G09G,H05B

Abstract:
1. A power integrated circuit device having at least one input and at least one output, comprising: a core circuit producing at least one output from the power integrated circuit; and an interface for controlling the core circuit, the interface including, a first circuit for receiving a signal via a single input of the integrated circuit, the first circuit for accumulating a count of clock pulses encoded in the received signal, a second circuit for mapping the count of encoded clock pulses into a corresponding one of a plurality of control states for the core circuit; a third circuit for resetting the count of encoded clock pulses to zero in response to the received signal being low for a period that exceeds a predetermined timeout value, the predetermined timeout value being longer than a width of one of the encoded clock pulses; a fourth circuit including a latch operative to receive the accumulated count from the first circuit; and a fifth circuit responsive to the received signal, the fifth circuit producing a latch signal that is asserted in response to the received signal being maintained high for a period that exceeds a predetermined latch timeout value; and wherein the latch is responsive to the latch signal, and operative to forward the accumulated count to the second circuit in response to the latch signal being asserted.