Patent ID: 7332954
Filing Date: 2008-02-19
Classification: H03K

Abstract:
1. An arrangement to ease restriction upon gate voltage (Vgg) magnitudes for a dynamic threshold MOS (DTMOS) transistor, the arrangement comprising: an MOS transistor including a gate and a body; and a body-bias-voltage (Vbb) governor (Vbb-governor) circuit to provide a governed version of Vgg of the MOS transistor to the body of the MOS transistor as a dynamic body bias-voltage (Vbb); wherein the Vbb-governor circuit includes at least a voltage-divider circuit connected between a gate of the MOS transistor and a system voltage; wherein the voltage-divider circuit includes a first part and a second part connected at a first node, the body of the MOS transistor being connected to the first node; wherein the first part is a buffer circuit; and wherein the second part is a diode circuit.