Patent ID: 8683395
Filing Date: 2014-03-25
Classification: G03F,G06F

Abstract:
1. A method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool, the method comprising: selecting a previously processed wafer having a past integrated circuit design, wherein the past integrated circuit design is different than the new integrated circuit design; selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, the plurality of CD data points having a first average CD; creating a field layout and associated baseline exposure dose map for the new integrated circuit design, each field in the field layout having a second average CD; refining each field in the baseline exposure dose map based on a difference between the first average CD for the previously processed wafer and the second average CD for each field in the field layout; and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.