Patent ID: 7397260
Filing Date: 2008-07-08
Classification: G01R,H01L

Abstract:
1. A method of testing an ability of a microelectronic element having conductive interconnects to withstand thermal stress, comprising: providing an interconnect test structure within said microelectronic element, said interconnect test structure including: i) a conductive metallic plate having an upper surface, a lower surface opposite said upper surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction transverse to said width, and a thickness in a vertical direction extending between said upper surface and said lower surface, ii) a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end, and iii) an upper metallic via in at least substantial vertical alignment with said lower conductive via such that a line extending in said vertical direction through said metallic plate intersects said upper metallic via and said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times smaller than a larger one of said length of said metallic plate and said width of said metallic plate; maintaining said microelectronic element at an elevated temperature for a predetermined period of time; taking a first measurement of at least one electrical characteristic of said interconnect test structure prior to an end of said predetermined period of time; taking a second measurement of said at least one electrical characteristic of said interconnect test structure at a time not prior to an end of said predetermined period of time; and comparing a difference between said first and second measurements to at least one failure criterion to determine whether said microelectronic element passes or fails.