Patent ID: 7091103
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A method of planarizing an integrated circuit wafer containing at least two areas of different structure density comprising the steps of: etching trenches in two areas of said wafer of different density, a first area of higher density and a second area of lower density; filling trenches in both of said areas with a filler material, whereby said first area has a concentration of structures having a first height above a surface of said wafer and said first density and said second area has a concentration of structures having a second height above said surface of said wafer higher than said first height and a second density lower than said first density; depositing a blanket conformal film on said wafer, thereby filling and planarizing said first area; performing a blanket etch on said wafer; performing a block etch on said first area while said second area is protected; and performing a CMP step on said wafer.