Patent ID: 6288936
Filing Date: 2001-09-11
Classification: G11C

Abstract:
Nonvolatile memory, comprising:a plurality of cell transistors that hold a 2.sup.N threshold voltage state (N.gtoreq.2);a plurality of bit lines and word lines to which said cell transistors are connected; anda read buffer circuit, connected to said bit lines, for detecting the threshold voltage state of said cell transistors; andwherein said read buffer circuit comprises a latch circuit that latches read data in accordance with said detected threshold voltage state, and a first and second latch reversal circuit that reverse the latch state of said latch circuit into the first and second states;wherein when a first bit of data held in said cell transistor is to be read, said read buffer circuit uses said first latch reversal circuit to reverses or not reverse the latch circuit having an initial state in accordance with the detected first and second, or third and fourth threshold voltage state, then outputs the latch state as the first bit of data; andwherein when a second bit of data held by the cell transistor is to be read, said read buffer uses said first latch reversal circuit to reverse or not reverse the latch state corresponding to said first data in accordance with the detected first or second threshold voltage state, then uses said second latch reversal circuit to reverse or not reverse the latch state in accordance with the subsequently detected third or fourth threshold voltage states, and then outputs the latch state as the second bit of data.