Patent ID: 6181660
Filing Date: 2001-01-30
Classification: G11B

Abstract:
A digital signal processing circuit comprising an input circuit inputting digitized bit data of 1-bit serial form read out of a recording medium and one or more bit clocks with a period f (where f is a positive integer) generated synchronously with the data, a transfer circuit transferring resultant read data after serial-to-parallel conversion of said input bit data into n bits (where n is a positive number) synchronously with read clocks having a period of (f.times.n); a detection and demodulation circuit performing synchronizing (sync) pattern detection and demodulation with respect to one-frame data comprised of a synchronization pattern of i bits (where i is a positive number) being contained for transmission in the n-bit read data and h (where h is a positive integer) unitary j-bit data (where j is a positive integer) of demodulation processing; anda sync pattern detection circuit detecting a sync pattern upon every occurrence of (i+j.times.h)/n clocks having the period of (f.times.n) and corresponding to a data transfer amount of a single frame to output its detection result.