Patent ID: 7694205
Filing Date: 2010-04-06
Classification: G11B,H03M

Abstract:
1. A post-processor for selecting an error sequence, comprising: memory for storing data therein; and a processor, coupled to the memory, the processor being configured for computing, for each processed bit of a codeword, reliabilities associated with each error event, wherein the reliabilities are based on parity and non-parity error events, computing parity syndromes associated with the codeword bits, maintaining a list of most likely error events along with error event type and location including parity events and non-parity events meeting a predetermined criteria based on the computed reliabilities and parity syndromes and selecting an error event having the highest reliability from the list of most likely error events for use in correcting for detected errors, the processor being configured to correct single and double error events even when there is no parity error in the codeword by prioritizing parity error events and non-parity error events meeting a predetermined criteria.