Patent ID: 9190414
Filing Date: 2015-11-17
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a first memory cell including a first gate electrode constituting a transistor lying in a first direction on a P well and an N well; a second memory cell including a second gate electrode constituting a transistor located symmetrically to the first gate electrode with respect to an axis in the first direction; and a first well voltage supply cell located between the first memory cell and the second memory cell in a direction perpendicular to the first direction and supplying voltages to the P well and the N well, wherein the first well voltage supply cell includes: a third gate electrode located symmetrically to the first gate electrode with respect to a border line with the first memory cell located adjacently; a fourth gate electrode located symmetrically to the second gate electrode with respect to a border line with the second memory cell located adjacently; a P-type impurity diffusion region located on the P well between the third gate electrode and the fourth gate electrode located opposite to each other; a first N-type impurity diffusion region located on a side of the third gate electrode closer to the first memory cell; and a second N-type impurity diffusion region located on a side of the fourth gate electrode closer to the second memory cell.