Patent ID: 6331468
Filing Date: 2001-12-18
Classification: H01L

Abstract:
A process for forming an integrated circuit structure on a semiconductor substrate which comprises:a) forming a gate oxide layer over a single crystal semiconductor substrate;b) forming a dopant-implant barrier layer containing nitrogen and silicon over said single crystal semiconductor substrate;c) forming a polysilicon gate electrode over said barrier layer;d) removing exposed portions of said barrier layer remaining after formation of said gate electrode thereon;e) forming an amorphous silicon layer over said integrated circuit structure;f) implanting said amorphous silicon layer with a first dopant capable of forming source/drain regions in the underlying semiconductor substrate;g) annealing said amorphous silicon layer:1) to crystallize said amorphous silicon layer to form a polysilicon layer;2) to diffuse said implanted dopant from said silicon layer into said substrate to form said source/drain regions in said substrate; and3) to diffuse said dopant into said polysilicon gate electrode;h) then nitridating said polysilicon layer to convert said polysilicon layer into a silicon nitride layer; andi) then anisotropically etching said silicon nitride layer to form silicon nitride spacers on the sidewalls of said polysilicon gate electrode to electrically insulate said gate electrode from said source/drain regions in said substrate.