Patent ID: 8281194
Filing Date: 2012-10-02
Classification: G01R,G11C

Abstract:
1. An integrated circuit comprising: A. a substrate of semiconductor material; B. pads formed on the semiconductor material; C. functional circuits formed on the substrate and having a functional output lead; D. output buffer circuitry formed on the substrate, the buffer circuitry having a buffer input lead connected to the functional output lead and having a buffer output lead coupled to an output pad; E. electrostatic discharge circuitry coupled to the buffer output lead; F. a serial scan path of scan cells formed on the substrate between a test data input lead and a test data output lead, both connected to a pad, some of the scan cells being switch cells; G. test leads formed on the substrate and connected to the pads; H. a first switch cell coupling a first test lead to the buffer output lead between the electrostatic discharge circuitry and the output pad; I. a second switch cell coupling a second test lead to the buffer output lead between the electrostatic discharge circuitry and the output pad; and J. a third switch cell coupling a third test lead to the buffer input lead between the output buffer circuitry and the functional output lead.