Patent ID: 6064593
Filing Date: 2000-05-16
Classification: G06F,G11C,H01L,Y02D

Abstract:
A semiconductor integrated circuit device comprising:an electrically erasable and programmable nonvolatile memory including memory cells each having a floating gate and being disposed for holding information therein as an amount of electric charge in the floating gate thereof so that each memory cell has either a writing condition or an erase condition, and a selection circuit which selects ones of the memory cells;an erase circuit which electrically erases the information held in ones of the memory cells by providing an erase voltage to the corresponding memory cells so as to place the corresponding memory cells in the erase condition;a processing unit;a serial communication circuit; and external terminals,wherein the semiconductor integrated circuit device has(i) a first operation mode in which data supplied from the serial communication circuit is written into ones of the memory cells selected by the selection circuit under control of the processing unit executing a write control operation so that conditions of the corresponding memory cells are placed in the writing condition based on the data supplied from the serial communication circuit, and(ii) a second operation mode in which data supplied from the external terminals is written into ones of the memory cells selected by the selection circuit under control of an external circuit to be coupled to the semiconductor integrated circuit device so that the corresponding memory cells are placed in the writing condition based on the data supplied from the external terminals, andwherein the erase circuit is selectively operated at a time when the information held in the memory cells is to be erased, in either the first operation or the second operation mode.