Patent ID: 6115418
Filing Date: 2000-09-05
Classification: H04L

Abstract:
A detector system comprising an equalizer, the equalizer comprising:an input terminal for receiving an input signal, the input signal suffering from a channel distortion described by a channel function having a denominator polynomial of order L hazing K denominator polynomial coefficients, L being a positive integer greater than 1 and K being a positive integer greater than or equal to 1 and less than or equal to L;an implementation of a transfer function, the transfer function being substantially the inverse of the channel function, the implementation having L delays coupled in series and K multipliers, each of the K multipliers having a multiplier coefficient corresponding to one of the K denominator polynomial coefficients, each of the K multipliers coupled to receive an output signal from one of the L delays, and an adder coupled to receive output signals from each of the K multipliers; andan output terminal coupled to the implementation for outputting a corrected signal in response to the K denominator polynomial coefficients and the input signal, wherein:L=; andthe L delays include a first delay, a second delay, and a third delay coupled in series, each of the first delay, the second delay and the third delay delaying the input signal by one clock, cycle, the first delay receiving the input signal; wherein:K=2;the K multipliers include a first multiplier and a second multiplier, the first multiplier having a first coefficient and the second multiplier having a second coefficient, the first multiplier receiving a first delayed signal from the first delay and outputting at a first output terminal the first delayed signal multiplied by the first coefficient, the second multiplier receiving a third delayed signal from the third delay and outputting at a third output terminal the third delayed signal multiplied by the second coefficient; andthe adder is coupled to the input terminal of the equalizer, the first output terminal and the third output terminal and which outputs the sum of the first delayed signal multiplied by the first coefficient, the third delayed signal multiplied by the second coefficient, and the input signal as the corrected signal of the equalizer.