Patent ID: 6777759
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A semiconductor device comprising:a gate electrode formed on a gate dielectric formed on a substrate surface, the gate electrode having a first thickness; a gate silicon germanium film formed on the gate electrode, the gate silicon germanium film having a second thickness; a gate silicide layer formed on the gate silicon germanium film, the gate silicide layer having a third thickness; a pair of sidewall spacers on opposite sides of the gate electrode, the sidewall spacers having a height of at least 200 Ã¥ above the third thickness of the gate silicide layer and a width of less than 300 Ã¥; a pair of source and drain regions formed on opposite sides of said gate electrode, said source and drain regions having a silicon germanium film formed beneath said substrate surface and a pair of ultra shallow tip regions formed beneath the pair of sidewall spacers.