Patent ID: 7996646
Filing Date: 2011-08-09
Classification: G06F

Abstract:
1. An apparatus comprising: a queue comprising a plurality of entries, wherein each entry is assignable to a respective store memory operation, and wherein each entry is configured to store a first mask, a first offset, a second mask, and a second offset, and wherein a combination of the first mask, the first offset, the second mask, and the second offset identifies which bytes within a group of contiguous bytes in memory are updated by the respective store memory operation, and wherein each entry is further configured to store a first address identifying a first byte of the group of contiguous bytes; and a control unit coupled to the queue, wherein the control unit is configured to receive an input address, a third mask, a fourth mask, a third offset, and a fourth offset that all correspond to a load memory operation, wherein the control unit is configured to detect that the load memory operation accesses at least one byte updated by the respective store memory operation responsive to a comparison of the first address to the input address and further responsive to the first, second, third and fourth masks and the first, second, third, and fourth offsets, and wherein the control unit is configured to signal a hit of the load memory operation on the store memory operation responsive to detecting that the load memory operation accesses the at least one byte updated by the respective store memory operation, and wherein the control unit is configured to detect that the respective store memory operation updates all bytes accessed by the load memory operation, and wherein the control unit is configured to cause the store data corresponding to the respective store memory operation to be forwarded in response to the load memory operation, and wherein the control unit is configured to detect that all bytes accessed by the load memory operation are updated by the respective storage memory operation responsive to inverting the third mask and the fourth mask, bitwise logically ORing the inverted third mask with the first mask, bitwise logically ORing the inverted fourth mask with the second mask, and detecting that a result of the bitwise logical ORing operations are both all ones.