Patent ID: 8045391
Filing Date: 2011-10-25
Classification: G11C

Abstract:
1. A method of sensing a group of nonvolatile memory cells in parallel, comprising: (a) providing access to individual memory cells of the group by associated bit lines and a common word line; (b) selecting a demarcation threshold voltage level relative to which the sensing is to be performed, the demarcation threshold voltage level being one among a set of multiple threshold voltage levels; (c) sensing, in a predetermined number of more than one sensing pass, the group of memory cells in parallel relative to the selected demarcation threshold voltage, wherein whenever in less than all of said predetermined number of more than one sensing pass, a condition for bit-line lockout by grounding the bit-line is enabled, performing (d1) to (d2) before proceeding to (e), otherwise skipping to (e): (d1) identifying any memory cell sensed to have a threshold voltage level less than the selected demarcation threshold voltage level; (d2) locking out the associated bit line of any identified memory cell by setting the associated bit line to a ground potential, said locking out being performed selectively for less than all iterations of the voltage levels from the set of multiple threshold voltage levels, whenever an enabling condition for bit-line lockout is satisfied; and (e) repeating (b) to (e) for a next voltage level from the set of multiple threshold voltage levels until every voltage level from the set has been iterated.