Patent ID: 6838726
Filing Date: 2005-01-04
Classification: H01L,Y10S

Abstract:
1. A memory cell, comprising: a source region in a horizontal substrate; a drain region in the horizontal substrate; a channel region separating the source and the drain regions; an edged defined control gate vertically situated above the channel region and separated from the channel region by a first thickness insulator material; a first edged defined floating gate horizontally situated above the control gate and separated from the control gate by an intergate dielectric; and a second edged defined floating gate vertically situated and parallel to one side of the control gate, wherein the second edge defined floating gate is attached to a first end of the first edged defined floating gate and wherein the second edged defined floating gate is separated from the channel region by a second thickness insulator material, the second edged defined floating gate separated from the edged defined control gate by the intergate dielectric.