Patent ID: 7057938
Filing Date: 2006-06-06
Classification: G11C,H01L

Abstract:
1. An electronic circuit comprising: a nonvolatile memory having at least one bit and further comprising a p type semiconductor substrate, a first isolation layer over the p type semiconductor substrate, a trapping layer over the first isolation layer, a second isolation layer over the trapping layer, a gate over the second isolation layer, two N+ junctions in the p type semiconductor substrate, and a source and a drain respectively formed on the N+ junctions; the trapping layer being operable to retain electrons in an erase state for at least one bit in either side of the trapping layer of the nonvolatile memory, causing the nonvolatile memory to have a threshold voltage, and a read current in a reading operation; and a comparator receiving a first input resulting from the read current and a second input in a form of one of a reference voltage and a reference current.