Patent ID: 6467015
Filing Date: 2002-10-15
Classification: G06F

Abstract:
A memory system for interfacing with an input bus, the input bus having an input bus speed comprising:a plurality of banks of non-volatile storage units, each bank having a number of columns of non-volatile storage units, each non-volatile storage units having an input buffer for storing a page of data, the page having a page size, having an input coupled to the input buffer accepting an input portion of data of a page at a memory speed, the non-volatile storage units storing the data of the page from the input buffer within a memory write time; a plurality of interface buffers coupled to the input bus; a bus system coupling each of the plurality of interface buffers to the non volatile storage units of one of the columns in each of the plurality of banks of non-volatile storage units, supplying data from the plurality of interface buffers to the inputs of the non-volatile storage units at the memory speed; and wherein the plurality of banks include a number of banks of non-volatile storage units, the number being greater than or equal to the memory write time multiplied by the memory speed divided by the page size and the number of columns in each bank being greater than or equal to the input bus speed divided by the memory speed.