Patent ID: 9041116
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. An electrical device comprising: a semiconductor substrate including a first device region and a second device region separated by an isolation region; a first gate stack in the first device region comprised of at least a first portion of a high-k gate dielectric layer and a first portion of a metal nitride layer atop the first portion of the high-k gate dielectric layer, wherein a first source region and a first drain region are present in the first device region on opposing sides of the first gate stack, wherein the first gate stack extends from the first device region onto the isolation region; a second gate stack in the second device region comprised of at least a second portion of the high-k gate dielectric layer and a second portion of the metal nitride layer atop the second portion of the high-k gate dielectric layer, wherein a second source region and a second drain region are present in the second device region on opposing sides of the second gate stack, and wherein the second gate stack extends from the second device region onto the isolation region, and is separated from the first gate stack by a gate stack space, the gate stack space extending through the metal nitride layer and the high-k gate dielectric layer to the upper surface of the isolation region; and a connecting gate layer extending from the first gate stack across the gate stack space to the second gate stack, wherein the connecting gate layer is a single continuous material layer present in direct contact with upper surfaces of the first portion of the metal nitride layer and the second portion of the metal nitride layer, and the gate stack space.