Patent ID: 6137722
Filing Date: 2000-10-24
Classification: G11C,H01L

Abstract:
A memory device formed in a substrate material of a first conductivity type, the device comprising:a plurality of first wells of a second conductivity type formed in the substrate material;a plurality of memory transistors arranged in rows and columns, each memory transistor including a source and a drain of the first conductivity type formed in a first well, a channel region defined between the source and drain, and a floating gate insulatively formed over the channel;a plurality of page lines formed adjacent to the rows of transistors so that each page line is connected to the source of each memory transistor in a row of transistors;a plurality of sense lines formed adjacent to the columns of transistors so that each sense line is connected to each memory transistor in a column of transistors;a row of access transistors connected to the sense lines so that each access transistor is connected to a sense line, each access transistor having a source and a drain of the second conductivity type formed in the substrate material, and a gate, the drain of the access transistor being connected to the sense line; anda plurality of enable lines connected to the gates of the access transistors in the row of access transistors so that an enable line is connected to the gate of each access transistor in the row of access transistors.