Patent ID: 6037247
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:forming two electrodes on a substrate, said two electrodes being positioned side by side at a predetermined interval;forming a spacer layer on each of side walls of said two electrodes;forming three diffusion layers in a surface layer of said substrate, each of said two electrodes being interposed between adjacent diffusion layers in such a way that a diffusion layer formed between said two electrodes is shared with the two electrodes;forming a silicide layer on each of said two electrodes and said three diffusion layers in a self alignment manner,depositing an insulating film over an entire surface, said insulating film deposited on said diffusion layer commonly shared which is present in a depressed space between said two electrodes via the silicide layer being thinner than the insulating film deposited on an open space on said two electrodes via the silicide layer;etching said insulating film, at least one factor of time and pressure during the etching being controlled in such a way that an insulating film deposited on said diffusion layer commonly shared via said silicide layer is removed substantially completely whereas the insulating film deposited on said two electrodes via said silicide layer is not removed completely and left as a thin film;depositing an interlayer insulating film over an entire surface;etching said interlayer insulating film for forming a contact hole for said diffusion layer commonly shared; andburring a conducting member in said contact hole, said conducting member buried being electrically connected to said diffusion layer commonly shared via the silicide layer and insulated from said two electrodes by said remaining insulating film.