Patent ID: 8250254
Filing Date: 2012-08-21
Classification: G06F

Abstract:
1. A method comprising: receiving a request for a direct memory access (DMA) operation in an input/output (I/O) hub from an I/O device coupled to the I/O hub, the request including a device virtual address (DVA) associated with the DMA operation; determining in the I/O hub whether to perform an address translation to translate the DVA into a physical address (PA) in a first translation engine of the I/O hub configured to receive and perform DVA to PA translations; sending the request with the DVA from the I/O hub to a processor coupled to the I/O hub when the I/O hub determines not to perform the address translation on a per mapping and access request basis, and performing the address translation in a second translation engine of the processor configured to receive and perform DVA to PA translations; and receiving a second request for a second DMA operation in the I/O hub from the I/O device, the second request including a second DVA associated with the second DMA operation, translating the second DVA into a second PA in the first translation engine, and sending the request with the second PA from the I/O hub to the processor.