Patent ID: 8248151
Filing Date: 2012-08-21
Classification: H03F,H03K

Abstract:
1. An apparatus comprising: a first circuit configured to contribute to the biasing of a second circuit, the first circuit operatively coupled to a first bias node as a reference for biasing of a second bias node of the second circuit, the first circuit having an output configured to generate a first electrical output; a first current source configured to provide an electrical reference; an error detection circuit configured to generate an error signal based at least partly on the electrical reference and the first electrical output of the first circuit; a first controllable electrical source operatively coupled between the error detection circuit and the first circuit, the first controllable electrical source configured to receive the error signal as a control input and to generate a first bias as an input to the first bias node of the first circuit, wherein the first bias is generated at least partly in response to the error signal; and a second controllable electrical source operatively coupled between the error detection circuit and the second circuit, the second controllable electrical source configured to receive the error signal as a control input and to generate a second electrical output, wherein the second electrical output is generated at least partly in response to the error signal.