Patent ID: 9087790
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method of fabricating a three-dimensional (3D) semiconductor device comprising: forming a stack structure including a plurality of horizontal layers and a plurality of interlayer insulating layers alternately stacked on a substrate, the substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region, the first mask pattern defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure, the second etch-depth being greater than the first etch-depth, after performing the second etching process, repeatedly performing a process of shrinking a planar area of the second mask pattern and performing the second etching process using the shrunk second mask pattern as the etch mask structure.