Patent ID: 8996848
Filing Date: 2015-03-31
Classification: G06F,H01L,H04L

Abstract:
1. An integrated circuit comprising: security monitoring circuitry; and storage including boot code firmware including at least first and second boot code firmware portions, each of the first and second boot code firmware portions establishing a secure mode entry sequence and an exit from secure mode, the entry and exit bracketing configurations for respectively higher security and lower security in the corresponding first and second boot code firmware portions, the security monitoring circuitry coupled to the storage independent of said second boot code firmware portion to protect a space in the storage from access, the space including both the first and second boot code firmware portions; and first non-volatile bits selecting one of the first and second boot code firmware portions for execution, the first nonvolatile bits unprotected by said security monitoring circuitry, and further comprising second non-volatile bits from which a higher security type or lower security type is detectable, the second non-volatile bits protected from access except access in a secure mode.