Patent ID: 6245665
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A method of fabricating a semiconductor device equipped with the dual damascene structure, comprising the steps of:(a) preparing a semiconductor substrate having a lower wiring layer and electronic elements;(b) forming a first interlayer dielectric layer on said substrate;(c) forming a second interlayer dielectric layer on said first interlayer dielectric layer;said second interlayer dielectric layer being made of a carbon-containing SiO.sub.2 ;(d) forming an opening in said second interlayer dielectric layer to overlap with said lower wiring layer or said electronic elements;(e) forming a third interlayer dielectric layer on said second interlayer dielectric layer having said opening;(f) forming a patterned mask layer having a window on said third interlayer dielectric layer;said window being located to overlap with said opening of said second interlayer dielectric layer;(g) patterning said third interlayer dielectric layer to form a wiring recess in said third interlayer dielectric layer using said patterned mask layer while said first interlayer dielectric layer is patterned to form a via hole in said first interlayer dielectric layer using said second interlayer dielectric layer;said via hole communicating with said wiring recess;(h) selectively forming a conductive layer to fill said wiring recess and said via hole after removing said patterned mask layer, thereby forming a wiring layer in said recess and a conductive plug in said hole;said wiring layer being contacted with said conductive plug; and(i) forming a fourth interlayer dielectric layer on said third interlayer dielectric layer to cover said wiring layer;said fourth interlayer dielectric layer being made of carbon-containing SiO.sub.2.