Patent ID: 6052305
Filing Date: 2000-04-18
Classification: G11C

Abstract:
A flash memory device comprising;a first well formed in a substrate;a second well formed in said first well;a plurality of memory cells disposed in said second well and arranged in an array having a multiplicity bit lines and word lines, each of said cell including;(a) a drain;(b) a source spaced apart from said drain so as to define a channel in aid second well intermediate said source and drain;(c) a floating gate disposed over said channel and insulated from said channel; and(d) a control gate disposed over said floating gate and insulated from said floating gate;a charge pump circuit for generating a pumping voltage to program, read and erase said memory cells;means for alternately applying said pumping voltage to said first well and second well with time interval in erasing operation, said means comprising;a first switching means for applying selectively said pumping voltage to said first well in erasing operation;a second switching means for applying selectively said pump voltage to said second well through said second switching means for definite time; anda driving circuit for driving said first and second switching means.