Patent ID: 6295566
Filing Date: 2001-09-25
Classification: G06F

Abstract:
A computer system, comprising:a processor for executing instructions;a memory having a set of instructions that, when executed by the processor, provide a bus power-down signal, the memory further contains:a region for storing configuration information, the configuration information corresponding to a bus in the computer system; anda first set of instructions that, when executed by the processor, overwrites a portion of the configuration information;a first PCI bus, coupled to the processor;a PCI bridge, coupled to the first PCI bus, for receiving the bus power-down signal; anda second PCI bus, coupled to the PCI bridge, the second PCI bus having a PCI slot for receiving a PCI bridge device, the second bus receiving power when the power-down signal is not asserted and not receiving power when the power-down signal is asserted, the second PCI bus further contains:a switch control responsive to the portion of the configuration information, the switch control selectively providing connection between a power supply in the first PCI bus and a power supply in the second PCI bus based on the portion of the configuration information.