Patent ID: 8683405
Filing Date: 2014-03-25
Classification: G06F

Abstract:
1. A test network in an integrated circuit, comprising: a center network constructed in a non-customizable layer of the integrated circuit, wherein the center network branches into each quadrant of the integrated circuit; a quadrant network in each of the quadrants, the quadrant networks constructed in the non-customizable layer of the integrated circuit, the quadrant networks having no connectivity to logic elements of the integrated circuit except through a custom layer of the integrated circuit, wherein the quadrant networks are substantially identical and are each connected to the center network and wherein test signals are transmitted from test pins on the integrated circuit through the center network to each of the quadrant networks for testing of the integrated circuit; and pre-built buffers distributed along the test network, wherein the integrated circuit is divided into a plurality of core regions, and wherein each pre-built buffer is configurable as to routing a signal from the test network to a logic cell of a circuit design and as to tying off in a circuit design that does not use all of the pre-built buffers.