Patent ID: 6125450
Filing Date: 2000-09-26
Classification: G06F,Y02D

Abstract:
In a computer system, a method of conserving power in a processor having a cache memory that maps into a main memory, said method comprising:monitoring a multiple master bus in said computer system to determine when said multiple master bus is idle, said multiple master bus having multiple bus masters that may initiate bus transactions, said monitoring includes an operating system (OS) polling a status bit, said status bit indicating if said bus has been active within a predetermined period of time;in response to said bus having been active within a predetermined period of time, causing said processor to enter a bus snooping low power state;in response to said bus having been inactive within a predetermined period of time, disabling a bus system arbiter coupled to said multiple master bus when said multiple master bus is idle to prevent bus transactions initiated by said bus masters that may write to said main memory thus cause cache incoherency;causing said processor to enter a processor low power state after disabling said bus system arbiter;waking said processor from said processor low power state when a bus master initiates activity on said multiple master bus; andenabling said bus system arbiter from said processor to allow bus transactions after waking said processor.