Patent ID: 6303942
Filing Date: 2001-10-16
Classification: B82Y,H01L

Abstract:
A tunnel barrier for use in semiconductor devices adapted for association with a silicon substrate and a top gate material, said barrier comprising:A. a first thin silicon oxide layer adapted for contact with said silicon substrate, said first thin silicon oxide layer having a tunnel thickness of less than about 5.0 nm;B. an intermediate layer of silicon in contact with said first thin silicon layer;C. a second thin silicon oxide layer comparable in thickness to said first thin silicon oxide layer, in contact with said silicon layer, and adapted for contact with said top gate material; andD. said intermediate silicon layer is a vapor deposited, undoped or lightly doped polycrystalline or nano-crystalline layer and has a thickness of less than about 5.0 nm;wherein said barrier functions to transfer charge across said barrier by tunneling other than resonant tunneling through the oxide layers via a conduction or valence band of the intermediate layer of silicon and exhibits resistance to unwanted charge leakage, dielectric degradation and dielectric failure.