Patent ID: 8852983
Filing Date: 2014-10-07
Classification: B81B,B81C,C23F,G01N,H01L

Abstract:
1. A method of fabricating a capacitive environment sensor integrated into a complementary metal oxide semiconductor (CMOS) comprising: selectively etching a CMOS dielectric of a CMOS stack having an exterior surface, the CMOS stack comprising, in order of decreasing distance from the exterior surface, a first metal layer, a second metal layer and a third metal layer comprising a plurality of first gaps, wherein the CMOS dielectric is disposed between the first, second and third metal layers and within the plurality of first gaps in the third metal layer, and the first and third metal layers are electrically connected to the second metal layer by metal vias, the selective etching of the CMOS dielectric of the CMOS stack producing one or more passages extending from the exterior surface of the CMOS dielectric of the CMOS stack to the second metal layer, through the plurality of first gaps in the third metal layer; and remove the second metal layer, thereby forming a second gap between metal vias electrically connected to the first metal layer and the metal vias electrically connected to the third metal layer.