Patent ID: 7456649
Filing Date: 2008-11-25
Classification: H03K

Abstract:
1. An open drain output circuit including an output terminal, the open drain output circuit comprising: an input unit for receiving an input signal, wherein the input unit includes an output node and performs a first operation and a second operation in accordance with transition of the input signal, the first operation causing potential at the output node to steeply fall and the second operation causing the potential at the output node to gradually rise; and an output transistor having a gate connected to the output node of the input unit and a drain connected to the output terminal, the output transistor being turned OFF in the first operation of the input unit and being turned ON in the second operation; wherein the input unit includes: a first inverter circuit for driving an output signal originating from the input signal at the output node of the input unit; and a delay time adjustment circuit for reducing the difference between a delay time from the transition of the input signal until when the output transistor is turned OFF in the first operation and a delay time from the transition of the input signal until when the output transistor is turned ON in the second operation, wherein the delay time adjustment circuit includes a first transistor having a gate directly connected to an internal node between the output node of the input unit and the gate of the output transistor, and a drain connected to the first inverter circuit.