Patent ID: 7917725
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. A method for managing memory of a processing system comprising: detecting a change in a page table including a plurality of page table entries, where each of the plurality of page table entries includes information for translating a virtual address to a corresponding physical address; responding to the detection by identifying a run of contiguous page table entries having substantially the same access permission information; analyzing the run of contiguous page table entries to determine whether those run may be consolidated using a larger memory page size, Y, and whether the run of contiguous page table entries may be consolidated for caching in an entry of a TLB that caches multiple page table entries, X, in a single TLB entry; and updating an entry of the TLB with information corresponding to the run of contiguous page table entries when the analysis determines that the run of contiguous page table entries may be consolidated for caching in the entry of the TLB, where the updating uses the larger memory page size, Y.