Patent ID: 7191413
Filing Date: 2007-03-13
Classification: G01R

Abstract:
1. A method for performing thermal testing of a semiconductor chip design, the semiconductor chip design including one or more semiconductor devices and one or more interconnects connecting the one or more semiconductor devices, the method comprising: calculating full-chip temperatures over said semiconductor chip design in accordance with a three-dimensional full-chip thermal model that is adaptively partitioned in response to volumes of steep thermal gradients over the semiconductor chip design and that depicts computed temperatures over said semiconductor chip design with a resolution down to a level of individual ones of said one or more semiconductor devices and individual ones of said one or more interconnects; identifying at least one region in said semiconductor chip design that is determined to exhibit a steep thermal gradient relative to other regions of the semiconductor chip design, in accordance with the calculated full-chip temperatures; positioning at least one temperature sensor in a region of interest within a semiconductor chip, the region of interest being determined, at least in part, by the at least one region of the semiconductor chip design that is determined to exhibit a steep thermal gradient relative to other regions of the semiconductor chip design; specifying a maximum temperature not to be exceeded by said semiconductor chip in operation; and determining whether a measured temperature within the region of interest exceeds said maximum temperature.