Patent ID: 6593202
Filing Date: 2003-07-15
Classification: H01L

Abstract:
A method of fabricating a semiconductor memory device, comprising:forming an element-isolating film in a surface of a semiconductor substrate to define an element region; forming a transistor in said element region, the transistor having a gate electrode and source and drain regions, said gate electrode including a gate conductive layer and a gate protecting film formed over said gate conductive layer; forming a first interlayer insulating film on said transistor, said element region and said element-isolating film; planarizing the first interlayer insulating film until said gate protecting film of said gate electrode is exposed; forming a first contact hole in said first interlayer insulating film, said first contact hole opening to at least one of said source and drain regions and a portion of said element-isolating oxide film, a side of the first contact bole being adjacent to said gate electrode of said transistor; forming a first conductive film in said first contact hole contacting said at least one of said source and drain regions and said portion of said element-isolating film, said first conductive film being adjacent to said gate electrode of said transistor; and planarizing said first conductive film until said gate protecting film of said gate electrode is exposed.