Patent ID: 6337244
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method of forming a line of FLASH memory cells comprising:forming a first line of floating gates over a crystalline silicon comprising semiconductor substrate; providing an alternating series of SiO2 comprising isolation regions and active areas in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates, the series of active areas defining discrete transistor source areas separated by isolation regions; forming a masking layer over the floating gates, the regions and the areas; forming a third line mask opening in the masking layer over at least a portion of the second line; and substantially anisotropically etching the SiO2 comprising isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon.