Patent ID: 8102698
Filing Date: 2012-01-24
Classification: G11C,H01L

Abstract:
1. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure within the integrated circuit for writing to the memory cells comprising: a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current; a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and a bit line driver receiving the controlled current and an unselected bit line voltage, the bit line driver selecting between providing to a bit line the controlled current and the unselected bit line voltage in response to a driver control signal, the bit line providing the controlled current to at least one of the memory cells comprising phase change memory elements.