Patent ID: 8962417
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure comprising: providing a structure including a Si substrate, an N- or C-doped Si layer continuously located on an entirety of an upper surface of the Si substrate, and a SiGe channel layer located on an entirety of an upper surface of the N- or C-doped Si layer, wherein said providing the structure includes forming the SiGe layer on an upper surface of the Si substrate and then forming the N- or C-doped Si layer within an upper portion of the Si substrate by implanting N or C into said upper region of the Si substrate; forming a p-FET gate stack on an upper surface of a portion of the SiGe channel layer, wherein said forming the p-FET gate stack occurs after forming the N- or C-doped Si layer, and wherein the portion of the SiGe layer containing the p-FET is entirely spaced apart from the Si substrate by a N- or C doped Si layer portion of said N- or C-doped Si layer; and forming a source region and a drain region into portions of the SiGe layer and portions of the N- or C-doped Si layer that are located at a footprint of, but not directly beneath, the pFET gate stack by ion implantation of a p-type dopant, wherein said source region and said drain region have an abrupt junction profile.