Patent ID: 6434047
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A semiconductor memory system having a plurality of memory cells which is formed in a semiconductor substrate and a decoder that selects one or more memory cells from said plurality of memory cells, wherein;said memory cells each comprise; a channel portion formed in said substrate; a source portion formed in said substrate; a drain portion formed in said substrate; a control gate portion; and a floating gate portion which is in an electrically suspended state between said channel portion and said control gate portion; and a reference voltage is applied to said source portion, a fourth voltage achieving a level higher than said reference voltage is applied to said control gate portion, a fifth voltage achieving a level lower than said reference voltage is applied to said channel portion and a sixth voltage achieving a level lower than said fifth voltage is applied to said drain portion, at each selected memory cell selected from said plurality of cells by said decoder.