Patent ID: 9190147
Filing Date: 2015-11-17
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array configured as an arrangement of memory cells, the memory cells being disposed at intersections of a plurality of first lines that are disposed in parallel and a plurality of second lines that are disposed intersecting the first lines, and the memory cells each including a variable resistance element; a first driver circuit for set operation configured to, when executing on the memory cell a set operation for switching a memory cell from a high-resistance state to a low-resistance state, supply a voltage to the first lines; a first driver circuit for reset operation configured to, when executing on the memory cell a reset operation for switching the memory cell from a low-resistance state to a high-resistance state, supply a voltage to the first lines; a second driver circuit set operation configured to, when executing the set operation on the memory cell, supply a voltage to the second lines; and a second driver circuit for reset operation configured to, when executing the reset operation on the memory cell, supply a voltage to the second lines, a length of a wiring line between the first driver circuit for set operation and the memory cell array being longer compared to a length of a wiring line between the first driver circuit for reset operation and the memory cell array, and a length of a wiring line between the second driver circuit for set operation and the memory cell array is longer compared to a length of a wiring line between the second driver circuit for reset operation and the memory cell array.