Patent ID: 6344386
Filing Date: 2002-02-05
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:a step of forming a semiconductor substrate having a memory cell region in which a memory cell transistor is formed, and a CMOS logic region in which a CMOS transistor is formed, and of forming a gate electrode used by the memory cell transistor in said memory cell region; a first impurity injection step of forming a diffusion layer in said memory cell region, with said gate electrode used by the memory cell transistor as a mask; a step of forming a gate electrode used by the CMOS transistor in said CMOS logic region; a second impurity injection step of forming a lightly doped drain in said CMOS logic region, with said gate electrode used by the CMOS transistor as a mask; an insulating film formation step of forming an insulating film covering said memory cell region and said CMOS logic region; a step of forming a mask layer to cover said memory cell region, excluding said CMOS logic region; a step of selectively etching said insulating film in correspondence with said mask layer, and forming sidewalls in the side faces of said gate electrode used by the CMOS transistor; a third impurity injection step of forming a diffusion layer of said CMOS transistor in said CMOS logic region, with said sidewalls as a mask; a step of depositing a metal on the entire surface after removing said mask layer; and a step of reacting said deposited metal and the exposed diffusion layer of said CMOS transistor to form a metal silicide, wherein the concentration of the impurity injected by said first impurity injection step is higher than the concentration of the impurity injected by said third impurity injection step.