Patent ID: 6650692
Filing Date: 2003-11-18
Classification: H04B

Abstract:
A CDMA receiver, having a plurality of despreading/delay adjustment units, each of which performs despreading processing of a desired signal arriving via an allocated path among multiple paths, adds a delay amount to a despread signal obtained from despreading processing according to the path, and outputs the result, a combining unit which combines the outputs of each despreading/delay adjustment unit, a path search unit which allocates paths to each despreading/delay adjustment unit and a timing control unit which controls timing; characterized in thatsaid path search unit comprises: a correlation detection section, which detects a correlation, in each prescribed time interval, between a received signal and a desired signal; a path selection section, which selects a plurality of paths over which the desired signal arrives based on the peak level of said correlation, and which employs the peak detection time as the desired signal detection time; storage means, which stores, as a reference time, the desired signal detection time over a path when this path is newly allocated to a despreading/delay adjustment unit, and which stores the previous-time desired signal detection time for the path; a path judgment section, which, if the difference between the desired signal detection time in a path selected this time and the previous-time detection time is within an allowable range, judges that the path selected this time is identical to the path previously allocated to the prescribed despreading/delay adjustment unit; and, a path allocation section, which performs allocation of paths to each dispreading/delay adjustment unit such that, if the path selected this time is identical to the previously allocated path, despreading and delay adjustment processing of a desired signal arriving over this identical path is caused to be executed by the same despreading/delay adjustment unit as previously; and, said timing control unit comprises: a calculating section, which calculates the difference between the desired signal detection time this time, over said identical path, and said reference time; and, a timing control circuit, which controls the timing lead/lag based on the total of said detection time differences for each identical path.