Patent ID: 6462602
Filing Date: 2002-10-08
Classification: H03K

Abstract:
A voltage level translator circuit comprising:an input terminal operable to receive an input signal; a capacitor having a first and second terminal, wherein the first terminal is coupled to the input terminal; a clamp circuit coupled to the input terminal and to the second terminal of the capacitor and operable to provide a signal on the second terminal of the capacitor in response to a first voltage level of the input signal; a voltage source circuit coupled to the clamp circuit and to the second terminal of the capacitor and operable to provide a signal on the second terminal of the capacitor in response to a second voltage level of the input signal; and an output buffer having a first and second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the capacitor and the second input terminal is coupled to the second terminal of the capacitor, the output buffer operable to provide an output signal on the output terminal in response to signals on the first and second terminals of the capacitor; wherein the clamp circuit comprises: a first transistor coupled to and operable to provide a translated voltage level signal at the second terminal of the capacitor; a second transistor coupled to the first transistor and to the input terminal; and a third transistor coupled to the first and second transistor, wherein the second and third transistors are operable to control the first transistor in response to voltage levels of the input signal and the second terminal of the capacitor.