Patent ID: 6944041
Filing Date: 2005-09-13
Classification: G11C

Abstract:
1. A random access memory comprising: a memory array having a plurality of subarrays formed by chalcogenide storage elements; a plurality of write circuits, wherein each of said plurality of write circuits includes an independent write 0 circuit and an independent write 1 circuit, wherein each of said plurality of write circuits is associated with a respective one of said plurality of subarrays; a plurality of read circuits, wherein each of said plurality of read circuits includes a sense amplifier circuit, wherein each of said plurality of read circuits is associated with a respective one of said plurality of subarrays; a voltage level control module, coupled to said plurality of read and write circuits, for ensuring that voltages across said chalcogenide storage elements do not exceed a predetermined value during a read or write operation such that data values stored within said chalcogenide storage elements cannot be changed erroneously and that the life of said chalcogenide storage elements can be extended.