Patent ID: 6415364
Filing Date: 2002-07-02
Classification: G06F

Abstract:
A memory system for providing memory storage for multiple processors through cache memories associated with said multiple processors, said memory storage system comprising:at least one memory cluster having at least one data storage arrayâ€”directory storage array pair, wherein both said data storage array and said directory storage array of a said pair are addressed by an address line wherein a single indicated address provided on said address line addresses an associated storage line in both said data storage and said directory storage at a same time, and wherein said data storage array is coupled to store data signals from said processor-associated cache memories, and for providing addressed ones of said stored data signals to a one of the processor-associated cache memories during a data read operation, and coupled to write data signals into indicated addresses within said data storage array when said data signals are received from a one of the processor-associated cache memories during a data write operations, said directory storage arrays for performing a read-modify-write operation for said indicated address in said directory storage array during substantially every read operation and for substantially every write operation performed by said data storage arrays; and a memory cluster control circuit coupled to each said data storage arrayâ€”directory storage array pair in said memory cluster, for providing via a control line, control signals to each said data storage array and each said directory storage array in said memory cluster, and for initiating each of said data read and data write operations wherein said memory cluster comprises a plurality of said data storage arrayâ€”directory storage array pairs, and wherein memory cluster control circuit has interleaving means for providing to each said data storage arrayâ€”directory storage array pair in said memory cluster in a time overlapped manner via said address line, a plurality of addresses, and via said control line, associated control signals for initiating a multiplicity of concurrently performed data read and/or data write operations in the data storage arrays of said data storage arrayâ€”directory storage array pair, while initiating performance of a read-modify-write in the directory storage array of each said data storage arrayâ€”directory storage array pair for each read or write operation.