Patent ID: 9098932
Filing Date: 2015-08-04
Classification: G06F,G06T

Abstract:
1. Graphics data processing logic comprising: a plurality of rows of parallel arithmetic logic units that operate as an array of arithmetic logic units on both pixel data and vertex data, wherein the array of ALUs include a plurality of sets of parallel ALUs, each set of said sets comprising at least two parallel ALUs, and including an ALU load arbiter operatively coupled to each of the sets of parallel ALUs and operative to determine the order in which each set of parallel ALUs gets loaded with pixel data or vertex data; a programmable storage element containing first data to adapt at last one of an ALU of the ALUs in the plurality of rows of parallel ALUs to perform either pixel data processing or vertex data processing; and parallel ALU pixel data and vertex data packing logic operatively coupled to the array of arithmetic logic units and to the programmable storage element and operative to pack pixel and vertex data only for specified arithmetic logic units of the array of arithmetic logic units based on the first data.