Patent ID: 7360024
Filing Date: 2008-04-15
Classification: G06F

Abstract:
1. A multi-port instruction/data integrated cache which is provided between a parallel processor to execute a plurality of types of processing in one clock cycle and a main memory and which stores a part of instructions and data stored in the main memory, comprising: a plurality of memory banks; a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor, and a data port unit consisting of at least one data port used to access data from the parallel processor, and the data port and the instruction ports are connected individually to at least one predetermined memory bank, wherein a number of memory banks connected to the data port is larger than a number of memory banks connected to the instruction ports, and all the memory banks are accessible from either the instruction ports or the data ports, and wherein a data width specified between the memory bank and the instruction port is larger than a data width specified between the memory bank and the data port.