Patent ID: 7743305
Filing Date: 2010-06-22
Classification: G01R

Abstract:
1. A test apparatus that test a device under test, comprising: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit and writes the same to each cache entry different from each other in the cache memory for each test data; and a pattern generating section that sequentially processes the test data stored on each cache entry in the cache memory and generates a test pattern for testing the device under test, wherein the main memory stores at least one of the test data to be stored on each cache entry of the cache memory across at least continuous two words of the main memory, wherein the pattern generation control section includes: a register pipeline having a plurality of registers which are cascade-connected, wherein a first register sequentially stores the memory data for each word which are sequentially read from continuous words of the main memory for each cycle and each subsequent register receives the memory data stored in the preceding register for each cycle and sequentially stores therein the same; and an extracting section that generates the memory data for a plurality of words obtained by connecting the data stored in the plurality of registers included in the register pipeline, and extracts each test data from the connected memory data, wherein the extracting section shifts the connected memory data by the amount of shift corresponding to the location of the test data in the last register when at least a part of test data to be extracted is stored in the last register and aligns the location of the test data in the connected memory data after shifting with a predetermined location, and skips to extract an instruction from memory data for the plurality of words for a cycle for which at least a part of test data to be extracted is not stored in the last register, wherein the pattern generation control section includes: a location register that stores the location of the test data to be extracted in the last register; and a location register updating section that adds the pattern length of the extracted test data to the location register in response to extracting the test data from the memory data for the plurality of words and subtracts the word length of the main memory from the location register for each cycle, and wherein the extracting section shifts the memory data for the plurality of words to a direction to decrease the location of the instruction by the amount of shift corresponding to the value of the location register when at least a part of test data to be extracted is stored in the last register.