Patent ID: 6251717
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method for forming floating gate memory cells in a semiconductor substrate, comprising the steps of:forming areas of field oxide to separate cell regions of a substrate;forming stacked gate structures extending over the field oxide areas;selectively forming doped source and drain regions in the substrate regions corresponding to cells in alignment with the stacked gate structures comprising, performing a self-aligned source etch, to form a self-aligned source mask, through exposed field oxide regions;performing a first rapid thermal anneal of the substrate to prevent transient enhanced diffusion of dopant within the substrate;performing a double diffusion implant comprising implanting a first dopant with the self-aligned source mask in place;removing the self-aligned source mask;performing a second rapid thermal anneal of the substrate to prevent transient enhanced diffusion of dopant within the substrate; andafter the second rapid thermal anneal, performing a shallow second implant with a second dopant.