Patent ID: 8471602
Filing Date: 2013-06-25
Classification: H03K

Abstract:
1. A semiconductor apparatus comprising: a pulse width control block configured to control a pulse width of first data and output a pull-up pre-drive signal and to control a pulse width of second data and output a pull-down pre-drive signal, according to a first impedance calibration signal and a second impedance calibration signal; and a driver block configured to drive an output node in response to the pull-up pre-drive signal, the pull-down pre-drive signal, the first impedance calibration signal and the second impedance calibration signal, wherein the pulse width control block comprises: a delayed signal generation section configured to variably delay the first data and output a first delayed signal and to variably delay the second data and output a second delayed signal, according to the first impedance calibration signal and the second impedance calibration signal; and a pulse control section configured to receive the first data and the first delayed signal and generate the pull-up pre-drive signal and to receive the second data and the second delayed signal and generate the pull-down pre-drive signal.