Patent ID: 8788756
Filing Date: 2014-07-22
Classification: G06F,G11C

Abstract:
1. A circuit for enabling the transfer of data by an integrated circuit device, the circuit comprising: a non-volatile memory array coupled to receive a clock signal and having a plurality of memory elements storing data; a buffer coupled to the non-volatile memory array; and a control circuit coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first, high data rate transfer mode and bi-directional transfer of data on the plurality of signal lines between the non-volatile memory array and the control circuit in a second mode, and enabling dual edge operation of the buffer coupled to the non-volatile memory array during the high data rate transfer of data with the non-volatile memory array; wherein the control circuit controls the transfer of data on the plurality of signal lines between the non-volatile memory array and the control circuit in the first mode on both the rising and falling edges of the clock signal.