Patent ID: 6071773
Filing Date: 2000-06-06
Classification: H01L

Abstract:
A method of fabricating a DRAM capacitor structure, on a semiconductor substrate, comprising the steps of:forming a transfer gate transistor, on said semiconductor substrate, comprised of an insulator capped, gate structure, on an underlying gate insulator layer, with insulator spacers on the sides of said insulator capped, gate structure, and with source/drain regions, in regions of said semiconductor substrate, not covered by said insulator capped, gate structures;forming a first, first level, DRAM metal plug, in a first contact hole, in a first insulator layer, contacting an underlying, first source region, in said semiconductor substrate, with said first, first level, DRAM metal plug, used as, and referred to, as a bit line contact plug;forming a second, first level, DRAM metal plug, in a second contact hole, in said first insulator layer, contacting an underlying, second source region, in said semiconductor substrate, with said second, first level, DRAM metal plug, used as, and referred to, as a storage node contact plug, and said storage node contact plug, fabricated simultaneously with said bit line contact plug;simultaneously forming a bit line metal interconnect structure, overlying, and contacting the top surface of said bit line contact plug, and a first level, DRAM metal interconnect structure, overlying, and contacting, the top surface of said storage node contact plug;forming a second level, DRAM metal plug, in a first via hole, in a second insulator layer, with said second level, DRAM metal plug, overlying, and contacting, the top surface of said first level, DRAM metal interconnect structure;forming a second level, DRAM metal interconnect structure, overlying, and contacting, the top surface of said second level, DRAM plug;forming a third level, DRAM metal plug, in a second via hole, in a third insulator layer, with said third level, DRAM metal plug, overlying, and contacting, the top surface of said second level, DRAM metal interconnect structure;removing said third insulator layer, and a portion of said second insulator layer, exposing said third level, DRAM metal plug, said second level, DRAM metal interconnect structure, and a top portion of said second level, DRAM metal plug, and using said third level, DRAM metal plug, said second level, DRAM metal interconnect structure, and the top portion of said second level, DRAM metal plug, as the top portion of a storage node structure, while a bottom portion of a the storage node structure, is comprised of the bottom portion of said second level, DRAM metal plug, said first level, DRAM metal interconnect structure, and said storage node contact plug, with the bottom portion of said storage node structure, contacting a second source region, in said semiconductor substrate;forming a capacitor dielectric layer on the exposed surfaces of the top portion of said storage node structure; andforming an upper metal plate, on said capacitor dielectric layer, and forming said DRAM capacitor structure, comprised of an overlying, said upper metal plate, said capacitor dielectric layer, and underlying, top portion of said storage node structure.