Patent ID: 6614079
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A complementary metal oxide semiconductor (CMOS) device comprising:a plurality of patterned gate stack regions formed on a surface of semiconductor substrate, wherein said plurality of patterned gate stack regions each includes an L-shaped nitride spacer formed on exposed vertical sidewalk thereof, said L-shaped nitride spacer having a vertical element and a horizontal said horizontal element is formed on a portion of said substrate that abuts the pattered gate stack region, said plurality of patterned gate stacks not containing a second spacer thereon; and suicide contacts formed on other portions of said semiconductor substrate between adjacent patterned gate stack regions not containing said horizontal element of said L-shaped nitride spacer, wherein said silicide contacts are self-aligned to deep junction edges formed in said semiconductor substrate, and said deep junction edges are self-aligned to an edge of said horizontal portion of said L-shaped nitride spacer.