Patent ID: 7084062
Filing Date: 2006-08-01
Classification: H01L

Abstract:
1. A method for improving deposition of memory element films in a semiconductor device comprising: providing a hard mask on an upper surface of a metal line upon which vias are to be placed; etching substantially all upper surfaces of the metal line except the upper surface of the metal line covered by the hard mask; depositing a Ta-containing capping layer material over substantially all upper surfaces of the metal line including the upper surface of the metal line covered by the hard mask; polishing the Ta-containing capping layer and the hard mask to produce a damascene Ta-containing cap while exposing a first portion of the metal line; depositing a dielectric material over the exposed first portion of the metal line and the damascened cap; patterning the dielectric layer to form a via to expose the first portion of the metal line; and depositing the memory element films in the via.