Patent ID: 7254692
Filing Date: 2007-08-07
Classification: G11C

Abstract:
1. A method of testing a memory device for determining operating life with stressing, comprising: cycling through each address of the memory device by generating a respective bit pattern comprised of a predetermined number of bits including row and column address bits for each address; applying stressing signals on a respective at least one cell of the memory device corresponding to each generated address in the cycling; wherein each of all possible row and column addresses of all of the row and column address bits is cycled through for application of the stressing signals; performing the cycling and the applying of the stressing signals for a predetermined stress time period; and minimizing charge gain failure in the memory device after the predetermined stress time period with a transition of less than the predetermined number of bits for sequencing to each subsequent address during the cycling through each of all possible row and column addresses of all of the row and column address bits.