Patent ID: 6462375
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A scalable dual-bit flash memory cell, comprising:a semiconductor substrate of a first conductivity type; a cell region having an active region between two shallow-trench-isolation (STI) regions formed on said semiconductor substrate and being divided into three regions: a first-side region, a gate region, and a second-side region with said gate region being formed between said first-side region and said second-side region, wherein said active region has a first conductive layer formed on a first gate-dielectric layer and each of said STI regions has a raised field-oxide layer; a common-source/drain diffusion region of a second conductivity type being formed by implanting doping impurities into said active region of said first/second-side region in a self-aligned manner with said gate region as an implantation mask; a first sidewall dielectric spacer being formed over each sidewall of said gate region and on a portion of a first/second flat bed being formed by said common-source/drain diffusion region and nearby two etched raised field-oxide layers in said first/second-side region; a second conductive layer being formed over said first/second flat bed outside of said first sidewall dielectric spacer to act as a bit line; a planarized thick-oxide layer being formed over said second conductive layer and said first sidewall dielectric spacer in said first/second-side region; a pair of floating-gate layers being defined and patterned by a pair of second sidewall dielectric spacers formed over each inner sidewall of said gate region and on a flat surface formed by said first conductive layer and nearby said raised field-oxide layers, wherein said first conductive layer and said first gate-dielectric layer between the pair of second sidewall dielectric spacers are sequentially removed to form a select-gate region and an implanted region of said first conductivity type is formed in a self-aligned manner by implanting said doping impurities into said semiconductor substrate of said select-gate region; a second gate-dielectric layer being formed over said planarized thick-oxide layers, a pair of floating-gate structures, said raised field-oxide layers between said pair of second sidewall dielectric spacers, and a semiconductor surface between the pair of floating-gate layers; and a planarized third conductive layer together with a first interconnect-metal layer being formed over said second gate-dielectric layer and simultaneously patterned and etched to form a word line transversely to said bit lines by using a patterned hard masking layer, wherein said patterned hard masking layer comprises a masking dielectric layer being aligned above said active region and two sidewall dielectric spacers being formed over sidewalls of said masking dielectric layer.