Patent ID: 7414459
Filing Date: 2008-08-19
Classification: G11C

Abstract:
1. An architecture for implementing an integrated capacitance, comprising: a capacitive block, inserted between a first voltage reference and a second voltage references, comprising a plurality of elementary capacitive modules; an enable block inserted between said first voltage reference and said capacitive block and comprising a plurality of switches connected to said elementary capacitive modules, the switches being driven on control terminals by a plurality of control signals, each switch of said enable block being inserted between said first voltage reference and a first end of a corresponding elementary capacitive module, a second end of the corresponding elementary capacitive module being connected to said second voltage reference; and a verify and enable circuit connected to said first voltage reference and having inputs connected to said first ends of said elementary capacitive modules and having outputs connected to said control terminals of said switches of said enable block, said verify and enable circuit detecting the presence of leakage current in each elementary capacitive module and, if said leakage current is detected, disabling the leaking elementary capacitive module of said capacitive block by means of said corresponding switch of said enable block, wherein the verify and enable circuit includes a circuit which opens a switch of said enable block and measures for a change in voltage across the open switch indicative of leakage current in the elementary capacitive module connected thereto.