Patent ID: 7609545
Filing Date: 2009-10-27
Classification: G11C

Abstract:
1. A semiconductor device that accesses a memory cell based on a row address and a column address comprising: a memory array including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines, and a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines; a plurality of word drivers connected to each of said plurality of word lines; a column selection circuit connected to said plurality of bit lines and that selects some of said plurality of bit lines to connect to a plurality of read circuits and a plurality of write circuits; an address hold circuit storing a row address and a column address involved with the previous access cycle; and an address compare circuit, wherein said word line is selected by decoding said row address, and said column selection circuit is selected by decoding said column address; wherein said address compare circuit is a circuit that compares a row address and a column address involved with a current access cycle and said row address and said column address held in said address hold circuit; wherein each of said memory cells comprises a selection element and a storage element connected in series to corresponding one line of said plurality of bit lines, a control electrode of said selection element is connected to corresponding one line of said plurality of word lines, wherein said storage element is an element to store data according to variations in resistance; wherein said word line is not turned on when said address compare circuit detects, in successive read cycles, that both of the row address and column address involved with a current access cycle match the row address and column address involved with the previous access cycle respectively.