Patent ID: 8255854
Filing Date: 2012-08-28
Classification: G06F

Abstract:
1. A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprising: creating a timing graph for a circuit having a set of switching output polarities; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing output polarities on the longest path to create a new set of switching output polarities; updating the timing graph using the new set of output polarities; performing timing analysis to determine a new longest path; if there is not at least one feasible delay tuple: determining a longest path and computing minimum delay tuples for the longest path; changing output polarities on the longest path to create a new set of switching output polarities; updating the timing graph using the new set of output polarities; performing timing analysis to determine a new longest path; if the new longest path is shorter than the longest path, accepting the new set of switching output polarities; if the new longest path is not shorter than the prior longest path, accepting the set of switching output polarities; and implementing a user-program bitstream using the one of the set of switching output polarities and the set of new switching output polarities that was accepted; and programming the circuit into a programmable logic device using the user-program bitstream.