Patent ID: 6103612
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method for isolating interconnect studs comprising the steps of:providing a semiconductor device including a first semiconductor structure having an upper surface and a second semiconductor structure having an upper surface, said first semiconductor structure having a sidewall and said second semiconductor structure having a sidewall, said sidewalls of said semiconductor structures defining a trench therebetween;forming a conformal layer of a dielectric spacer material on said first semiconductor structure and said second semiconductor structure including the respective sidewalls thereof;etching said layer of dielectric spacer material to remove said layer of dielectric spacer material from said upper surfaces of said semiconductor structures and to cause said layer of dielectric spacer material to become recessed along said sidewalls of said first semiconductor structure and said second semiconductor structure;forming a blanket layer of an electrically conductive material in said trench; andetching said blanket layer of electrically conductive material to form a stud of said electrically conductive material in said trench so that said stud is recessed below said respective surfaces of said semiconductor structures to electrically isolate said stud from areas of electrical activity on said semiconductor device.