Patent ID: 7476625
Filing Date: 2009-01-13
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a first inter-layer insulation layer on a substrate provided with a plurality of cell contact plugs; selectively etching the first inter-layer insulation layer to form a plurality of first contact holes and a plurality of second contact holes; performing a cleaning process to remove etch residues on lower portions of the first contact holes and the second contact holes; forming insulating fences on inner walls of the first contact holes and the second contact holes; forming a plurality of bit lines in contact with a group of the cell contact plugs through the respective first contact holes; forming a second inter-layer insulation layer over the plurality of bit lines; planarizing the second inter-layer insulation layer until an upper portion of each of the bit lines is exposed; and selectively etching the second inter-layer insulation layer in alignment with the bit lines to expose another group of the cell contact plugs through the second contact holes, in which storage nodes are to be formed.