Patent ID: 7362160
Filing Date: 2008-04-22
Classification: G11C

Abstract:
1. A fuse trimming circuit comprising: a controlling circuit generating a first pulse which is generated by delaying an input pulse, a second pulse which is generated by delaying said first pulse, and a third pulse having a pulse width from a leading edge of said first pulse to a trailing edge which is generated by a trailing edge of said second pulse; a bias circuit connected across a first power supply node and a second power supply node, for generating a bias voltage during a time period of said pulse width in response to said third pulse; a fuse-state determining circuit having a first transistor, a first output node, a second transistor, and a resistive element which are connected in series between said first power supply node and said second power supply node, and said fuse-sate determining circuit having a third transistor, a second output node, a forth transistor, and a fuse element which are connected in series across said first power supply node and said second supply node, said first and third transistors turning on in response to said first pulse, said second and said fourth transistors turning on in response to said bias voltage, a resistance of said resistive element being larger than that of said fuse element in an un-blown state and smaller than that of said fuse element in a blown state; and a latch circuit connected across the said first power supply node and said second power supply node, for amplifying a voltage difference across said first and said second output nodes, for holding said voltage difference as trimming information which represents a blown state or an un-blown state of said fuse element.