Patent ID: 6060749
Filing Date: 2000-05-09
Classification: H01L,Y10S

Abstract:
A structure for forming a transistor with ultra short channel and elevated source and drain on a substrate, said structure comprising:a silicon on insulator (SOI) structure formed in said substrate and said SOI structure keeping a space from a surface of said substrate, thereby creating a silicon layer formed thereon, wherein said substrate has a recessed portion formed in said silicon layer;an oxide layer formed on said surface of said substrate;a field oxide region formed on said recessed portion, said field oxide region having a first opening formed therein thereby exposing a portion of said silicon layer, wherein said opening is used for filling a gate therein, said silicon layer under said field oxide region having a thinner portion and thicker portions, wherein said thicker portion is used to form said elevated source and drain;a mask structure having a second opening wider than said first opening formed on said oxide layer; andspacers formed on said field oxide and attached on side walls of said second opening, wherein said spacers and said mask structure are used in combination to form said first opening.