Patent ID: 7620756
Filing Date: 2009-11-17
Classification: G06F,Y02D

Abstract:
1. An apparatus for transferring wide data over a narrow data bus comprising: an addressable storage means for storing a first portion of said wide data to be accessed from said narrow bus during a first bus transaction, said first bus transaction specifying storage of said first portion at a first address associated with said addressable storage means; an addressable memory storage array means comprising a plurality of wide data storage locations, a location having an associated second address; and control means implementing logic associated with a second bus transaction for effecting an atomic update of a wide data storage location at said associated second address in said addressable memory storage array with a data word created by combining a second portion of said data received from said narrow bus with said stored first portion in said second bus transaction for storage at said addressable wide data storage location, wherein said control means implements control logic for a write mode of operation controlling dataflow to and from said addressable storage means and said addressable memory storage array means, said control logic enabling merging of a first data portion included in said addressable storage means as a result of implementing said first bus transaction with a second data portion provided via said narrow bus, and providing said merged first data and second data portions to said storage array means for storage at an address specified by said bus transaction in said second bus transaction.