Patent ID: 8493119
Filing Date: 2013-07-23
Classification: H03K

Abstract:
1. An apparatus, comprising: a master latch including a multiplexer and a master feedback loop; a slave latch comprising a pass gate and a slave feedback loop including a slave inverter and a slave feedback inverter, wherein the slave feedback inverter includes a data input coupled to the slave inverter and a control input coupled to the clock signal, wherein during the second phase of the clock signal, the pass gate is enabled and the slave feedback inverter is disabled, and wherein during the first phase of the clock signal, the pass gate is disabled, the slave feedback inverter is enabled, and the slave feedback loop stores a value received from the master latch via the pass gate; and a plurality of combinatorial logic circuits coupled to generate the respective control inputs of the plurality of inverters of the multiplexer dependent upon the clock signal and a select signal, such that for each given inverter, assertion of the control input occurs only during the first phase of the clock signal; wherein the plurality of combinatorial logic circuits is further coupled to generate the respective control inputs of the plurality of inverters of the multiplexer dependent on a reset signal, wherein during assertion of the reset signal, all control inputs of the plurality of inverters are deasserted and outputs of the master latch and slave latch are reset.