Patent ID: 7501340
Filing Date: 2009-03-10
Classification: H01L

Abstract:
1. A method of forming an interconnection line in a semiconductor device, comprising: forming an insulating layer on a semiconductor substrate; forming a via hole to partially expose the semiconductor substrate by etching the insulating layer; forming a first copper seed layer on the via hole and a surface of the insulating layer; forming a first photoresist layer on the first copper seed layer, the first photoresist layer filling the via hole; forming a line-shaped trench over the first photoresist layer in the via hole by sequentially etching the first photoresist layer, a portion of the first copper seed layer, and an upper part of the insulating layer; forming a damascene structure including the via hole and the trench by removing the first photoresist layer in the via hole to expose the first copper seed layer in the via hole; forming a first copper layer that fills the via hole and has a top portion protruding into a bottom portion of the trench on the exposed first copper seed layer; removing a remaining portion of the first photoresist layer on the insulating layer; forming a second copper seed layer on an entire surface of the substrate; and forming a second copper layer on the insulating layer and in the trench using the second copper seed layer.