Patent ID: 8134861
Filing Date: 2012-03-13
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array provided with a plurality of blocks each having a plurality of memory cells arranged in a plurality of columns and a plurality of rows; a column selection circuit configured to select a column via bit lines based on a column section signal; a word line driver circuit configured to select a row via a word line based on a row selection signal and the column selection signal; and a write and read circuit configured to write data to and to read data from a selected memory cell, via the bit lines, based on a write and read switching signal, said selected memory cell being arranged at a position determined by the column selected by the column selection circuit and the row selected by the word line driver circuit within one block, wherein rows corresponding to the plurality of blocks are provided in common with the same number of word lines as the plurality of columns, and the memory cells arranged in one row within one block are coupled to mutually different word lines, wherein a half of the number of word lines within one block are provided on a first wiring layer, and a remaining half of the number of word lines within said one block are provided on a second wiring layer different from the first wiring layer, and wherein the memory cell array includes a complementary metal oxide semiconductor static random access memory (CMOS-SRAM) having 6-transistor type memory cells.