Patent ID: 6791147
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A semiconductor memory device having a semiconductor substrate, and a peripheral circuit area and a memory cell area defined on a main surface of the semiconductor substrate, comprising:a first well formed in the peripheral circuit area and having a specified depth; a second well of a first conductivity type, formed in the memory cell area, and having a depth shallower than the depth of the first well; a third well of a second conductivity type, formed in the memory cell area, and being generally equal in depth to the second well; and a device isolation structure, formed in the memory cell area, for isolating a device element formed in the second well from a device element formed in the third well wherein the second and third wells are formed down to a level lower than the device isolation structure, wherein, each of the first, second and third wells comprises, in the order from above, a first-concentration layer, a second-concentration layer and a third-concentration layer, and wherein the first well further comprises a fourth-concentration layer beneath the third-concentration layer.