Patent ID: 8053283
Filing Date: 2011-11-08
Classification: H01L,Y10T

Abstract:
1. A method of producing die level interconnect decals, said method comprising the steps of: (a) providing a plurality of superimposed apertured decals, said plurality of decals including an upper layer having alignment holes and tapered feature holes, a center layer having arrays of through features holes in alignment with said tapered feature holes and in alignment with through feature holes in a bottom layer located on an opposite side of said layer; a plurality of perforations extending through said center layer defining specific areas encompassing said arrays of feature holes; (b) forming alignment holes in said center layer in alignment with alignment holes in said bottom layer arranged about the peripheries of said layers for maintaining said layers in aligned relationship; (c) positioning a carrier stage having a substrate located thereon beneath said bottom layer, said carrier having upstanding pin numbers extending through the alignment holes in said upper, bottom and center layers; (d) filling the feature holes in said decal layers with molten solder and cooling said solder; (e) peeling said upper and bottom layers from said center layer and applying an adhesive layer to the exposed surface of said center layer encompassing solder portions projecting therefrom, (f) mounting semiconductor chips on at least one said exposed surface of the center layer, in alignment with the areas defined by said perforations and in contact with said adhesive and solder portions; (g) separating said semiconductor chips with the adherent solder-filled center layer along the areas bounded by said perforations from the remainder of said center layer, and (h) withdrawing said carrier stage while enabling said substrate to remain adhesively adherent to the adhesive layer in contact with the solder portion projecting from the lower surface of said center layer.