Patent ID: 6728149
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of normal memory cells arranged in rows and columns, a plurality of spare memory cells arranged in rows and columns, said plurality of spare memory cells being arranged, in plural rows, sharing at least the columns with said plurality of normal memory cells; a plurality of normal word lines arranged corresponding to the normal memory cell rows, and connected to normal memory cells in corresponding rows; a plurality of spare word lines arranged corresponding to the spare memory cell rows, and connected to spare memory cells in corresponding rows; defective address program circuitry for programming an address of a defective normal word line, said defective address program circuitry including a circuit for generating an coincidence indicating signal indicating a determination result of coincidence and non-coincidence between an external address and a programmed defective address; word line selection circuitry for selecting a corresponding word line from the normal word lines and the spare word lines in accordance with said external address and said coincidence indicating signal; and address conversion circuitry for changing correspondence relationship between said external address and said plurality of spare word lines.