Patent ID: 7356746
Filing Date: 2008-04-08
Classification: G11C

Abstract:
1. Embedded testing circuit for testing a dual port memory having a memory cell array being accessible through a first port and a second port, said embedded testing circuit comprising: (a) an embedded address generation circuit for generating an internal address consisting of an internal row selection address and an internal column selection address in response to an external address consisting of an external row selection address and an external column selection address, (a1) wherein said internal row selection address for addressing a second row of said memory cell array through said second port is generated by an adder which increments the external row selection address for addressing a first row of said memory cell array through said first port, such that the first row and said second row form adjacent rows within said memory cell array, (a2) wherein said internal column selection address for addressing columns of said memory cell array through said second port is switchable to be identical to said external column selection address; and (b) an embedded data generation circuit for generating an internal test data pattern in response to an external test data pattern, wherein said external test data pattern for accessing said memory cell array through said first port is switchable to be inverted by an inverter when said memory cell array is accessed through said second port.