Patent ID: 7646021
Filing Date: 2010-01-12
Classification: G02F,H01L

Abstract:
1. A thin film transistor array substrate, comprising: a substrate; a patterned first metallic layer disposed on the substrate, the patterned first metallic layer comprising a plurality of common lines, a plurality of scan lines, and a plurality of source patterns, wherein each two adjacent scan lines are orthogonal to two corresponding source patterns adjacent to each other so as to define a pixel area on the substrate, the common lines are configured passing through their corresponding pixel areas and parallel with the scan lines, and a protrusion is extruded from each of the source patterns at a position adjacent to its corresponding scan line, acting as a source electrode; a patterned stack layer composed of a semiconductor layer, a second metallic layer disposed in sequence from bottom to top on the patterned first metallic layer and the substrate, the patterned stack layer comprises a plurality of first stack patterns, a plurality of second stack patterns, and a plurality of third stack patterns, wherein the first stack patterns are correspondingly disposed on a source electrode in each pixel area, the second stack patterns are disposed on the common lines, each second stack pattern having an opening exposing the corresponding common line, and each third stack pattern is disposed at an intersection of an extending direction of each source pattern with the corresponding scan lines and the corresponding common lines; a patterned dielectric layer disposed over the substrate, comprising a plurality of second openings, a plurality of third openings, a plurality of fourth openings, a plurality of fifth openings, and a plurality of sixth openings, wherein the second openings are configured over and corresponding to the first openings in each pixel area, the third openings are configured over the first pattern stacks and exposing a part of the first pattern stacks in each pixel area respectively, the fourth openings are configured over both sides of the second pattern stacks, and exposing a part of the second pattern stacks in each pixel area respectively, the fifth openings are configured over a side of the scan line adjacent to the source electrode and exposing a part of the scan lines in each pixel respectively, and the sixth openings are configured over both sides of the source pattern and both sides of the third pattern stacks and exposing a part of the source patterns and a part of the third pattern stacks in each pixel area respectively; a patterned transparent conductive layer disposed on the patterned dielectric layer and the substrate, to form two pixel electrodes at both sides of the common line in each pixel area, respectively, wherein the pixel electrodes are electrically connected to the second pattern stack via the fourth openings, in which one of the pixel electrodes is electrically connected to the first pattern stack via the third opening, to form a first transparent electrode over the second pattern stack in each pixel area, wherein the first transparent electrode is electrically connected to the common line via the second opening and the first opening, to form a gate electrode over the source electrode in each pixel area, wherein the gate electrode is electrically connected to the scan line via the fifth opening, and to form a second transparent electrode in each pixel area at an intersection of an extending direction of each source pattern and its corresponding scan line and its corresponding common line, wherein the second transparent electrode is electrically connected to the corresponding source pattern and the corresponding third pattern stack via the corresponding sixth opening; and a patterned third metallic layer disposed over the substrate, comprising a plurality of data lines, wherein each data line is configured along the extending direction of the source pattern, and over the source patterns, and electrically connected to a corresponding second transparent electrode.