Patent ID: 6844765
Filing Date: 2005-01-18
Classification: G06F

Abstract:
1. A multi-phase clock generation circuit comprising: reference clock signal generation means for generating 2 first frequency division means for frequency-dividing one of the plurality of reference clock signals from said reference clock signal generation means to generate first and second clock signals out of phase with each other on the basis of frequency division outputs; first clock selection means for selecting one of each of the first and second clock signals from said first frequency division means and one of the reference clock signals and outputting the selected signals as first and second clock pulses; second frequency division means for frequency-dividing one of the clock pulses from said first clock selection means to generate third through sixth clock signals out of phase with each other on the basis of frequency division outputs; second clock selection means for selecting one of each of the third through sixth clock signals from said second frequency division means and one of the reference clock signals to output the selected signals as third through sixth clock pulses; and clock selection control means for controlling said first and second clock selection means in accordance with a set frequency division ratio.