Patent ID: 6175529
Filing Date: 2001-01-16
Classification: G11C

Abstract:
A semiconductor integrated circuit device, comprising:a memory;a memory self-testing address generator for receiving an external clock, generating a memory self-testing address for testing said memory, and providing said address to said memory, while generating a first control signal for generating memory self-testing data and a phase signal for generating a memory control signal;a data generator, coupled to said memory self-testing address generator to receive said first control signal, for generating said memory self-testing data to be written to said memory in a predetermined data pattern corresponding to said first control signal;a memory control signal generator for receiving said phase signal and for generating said memory control signal for controlling the write operation of said memory self-testing data to said memory self-testing address of said memory and the read operation of data from said memory self-testing address of said memory; andan evaluation circuit, coupled to said memory self-testing address generator to receive said first control signal, for evaluating a pass/fail of a memory actual output data read from said memory, and for outputting a pass/fail flag signal as an evaluation result,said evaluation circuit comprising a logic means for receiving said memory actual output data and means for selecting an output from said logic means in response to said first control signal.