Patent ID: 6920058
Filing Date: 2005-07-19
Classification: G11C

Abstract:
1. A semiconductor memory device comprising a memory cell array in which memory cells respectively having one first electrode and a pair of second electrodes and capable of reading stored contents correspondingly to the potential of said first electrode in accordance with a state of the electrical connection between said second electrodes are arranged in the row and the column directions like a matrix, wherein said memory cell array is constituted by connecting the first electrodes of said memory cells in the same row to a common word line, connecting said second electrodes each other between two of said memory cells adjacent to each other in the row direction, connecting one-hand said second electrodes in said memory cells in the same column to a common bit line, and connecting the other-hand said second electrodes in said memory cells in the same column to a common virtual ground line and moreover constituted by being divided into at least a plurality columns of subarrays, memory cell columns at the both ends of said subarrays are constituted so that said second electrodes are not connected each other between two of said memory cells adjacent to each other in the row direction at the both sides of boundaries between said subarrays but they are separated from each other and respectively connected to an independent bit line or virtual ground line, and one of said word lines, one of said bit lines, and one of said virtual ground lines are selected for each of said subarrays and one memory cell from which data will be read is selected.