Patent ID: 6836106
Filing Date: 2004-12-28
Classification: G01R,G11C

Abstract:
A test circuit for testing semiconductors, comprising:a plurality of at least first conductors and second conductors, the first and second conductors being operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors; a plurality of conductive taps, each of the taps being connected at a first end to a corresponding first conductor; and a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps, each of the switching circuits being configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.