Patent ID: 7779222
Filing Date: 2010-08-17
Classification: G06F

Abstract:
1. A computer system, comprising: a plurality of integrated circuits capable of concurrently executing a first process and a second process; and memory storing a deque comprising a doubly-linked list of nodes, wherein each node of the doubly-linked list of nodes comprises an array storing a plurality of references to threads usable by the first process, wherein the array exists before the deque is full, wherein the deque is local to the first process, wherein a bottom variable references a first end of the deque and a top variable references a second end of the deque, and wherein the computer system is configured to: wherein the first end of the deque is only accessible by the first process, wherein a non-blocking operation on a second end of the deque is invocable by the second process, and wherein, on the second end of the deque, only a removal-type operation is possible.