Patent ID: 8460990
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A method of fabricating a CMOS transistor using Ge condensation, the method comprising: providing a substrate having an insulating layer and a silicon layer on the insulating layer; patterning the silicon layer into a p-MOS transistor region and an n-MOS transistor region; forming a mask layer on the substrate using a dielectric material to cover the p-MOS transistor region and the n-MOS transistor region; exposing a source region and a drain region of the p-MOS transistor region and a channel region of the n-MOS transistor region through the mask layer; coating a SiGe layer on the substrate to cover the source region and the drain region of the p-MOS transistor region and the channel region of the n-MOS transistor region; and condensing Ge of the SiGe layer in the source region and the drain region of the p-MOS transistor region and the channel region of the n-MOS transistor region by oxidizing the SiGe layer.