Patent ID: 6878608
Filing Date: 2005-04-12
Classification: H01L

Abstract:
1. A method for fabricating a silicon based package (SBP) in the sequence as follows: starting with a wafer composed of silicon and having a first surface and a reverse surface which are planar as the base for the SBP, then forming an interconnection structure including multilayer conductor patterns over the first surface; then forming a protective overcoat layer over the interconnection structure; then forming a temporary bond between the protective overcoat layer of the SBP and a wafer holder, with the wafer holder being a rigid structure; then thinning the reverse surface of the wafer to a desired thickness to form an ultra thin silicon wafer (UTSW) for the SBP; then forming via holes which extend through the UTSW; then forming metallization in the via holes with the metallization extending through the UTSW; and then removing the temporary bond.