Patent ID: 6452229
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET), comprising:a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate; a source and a drain formed from the layer of semiconductor material; a body formed from the layer of semiconductor material and disposed between the source and the drain, wherein the layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body; and a T-shaped gate having a center region formed at least in part in the recess and a pair of upper arms extending laterally from the center region, the upper arms respectively extending toward a source side of the FET and a drain side of the FET, the arms formed over a configuring layer, the gate defining a channel in the body, and the gate including a gate electrode spaced apart from the body by a gate dielectric made from a high-K material.