Patent ID: 7592226
Filing Date: 2009-09-22
Classification: H01L

Abstract:
1. A method for manufacturing a non-volatile semiconductor memory device having a memory cell and a peripheral circuitry, comprising: forming element isolation structures for isolating active regions in a substrate, wherein an upper surface of the element isolation structure is higher than a surface of the substrate; forming a silicon oxide film on the substrate; forming a polysilicon film on the silicon oxide film; self-aligning the polysilicon film to the element isolation structures by planarizing the polysilicon film by a CMP method using the element isolation structures as a stopper film; forming a first resist pattern covering the peripheral circuitry adjacent to the memory cell; etching the element isolation structures in the memory cell by a predetermined thickness using the first resist pattern as a mask so that the element isolation structures in the memory cell are lower than the element isolation structures in the peripheral circuitry; forming a multilayer insulation film on an entire surface of the substrate; forming a second resist pattern covering the memory cell; removing the multilayer insulation film from the peripheral circuitry using the second resist pattern as a mask; forming a gate insulation film on the substrate of the peripheral circuitry; forming a conductive film on the entire surface of the substrate; patterning the conductive film on the peripheral circuitry and the memory cell to form a patterned conductive film; and patterning the multilayer insulation film and the polysilicon film on the memory cell using the patterned conductive film as a mask.