Patent ID: 6654281
Filing Date: 2003-11-25
Classification: G11C,H01L

Abstract:
A nonvolatile NOR semiconductor memory device, comprising:a semiconductor substrate; a multiplicity of one-transistor memory cells formed in said semiconductor substrate and disposed in a matrix form, said one-transistor memory cells containing mutually spaced-apart drain regions and source regions, a first insulating layer, a charge-storing layer, a second insulating layer, and a control layer; a multiplicity of word lines connected to and row-by-row driving said one-transistor memory cells, said word lines substantially formed by said control layer; and a multiplicity of bit lines connected to and column-by-column driving said one-transistor memory cells, said bit lines each having a source line and a drain line for enabling a selective driving of said drain regions and said source regions in respective columns of said one-transistor memory cells, said source line and said drain line formed in a shape selected from the group consisting of a meandering shape, a zigzag shape and an undulating form.