Patent ID: 7558127
Filing Date: 2009-07-07
Classification: G11C

Abstract:
1. A semiconductor device including a data output circuit to output data read from memory cells, wherein the data output circuit comprises: a first pipeline stage receiving, in parallel, a plurality of data from the memory cells and storing the received plurality of data, in response to a plurality of first control signals; a second pipeline stage receiving, in parallel, at least two data among the plurality of data stored in the first pipeline stage and storing the received at least two data, in response to a plurality of second control signals; and a multiplexer receiving the data stored in the second pipeline stage, and sequentially outputting the received data in response to a third control signal, wherein the first pipeline stage comprises: wherein the second pipeline stage comprises: wherein the plurality of second control signals are commonly provided to the (m+1) wherein the plurality of first control signals comprise n pipeline control signals. and each of the first through m wherein the plurality of second control signals comprise n*m/2 distinct pipeline control signals that are sequentially activated, wherein m*n/2 switches included in the (m+1)