Patent ID: 6166558
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method for measuring the gate length L.sub.g of a transistor gate comprising a gate, a source, and a drain mounted on a substrate and with a known fringe capacitance C.sub.fr and a known unit capacitance C.sub.OX, comprising the steps of:applying a nonzero inversion gate voltage V.sub.g between the gate and the source/drain;applying a zero voltage between source/drain and the substrate;measuring the gate capacitance C.sub.g between the gate and the source/drain with a LCR meter; andcalculating gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX =(C.sub.g -2C.sub.fr)/C.sub.OX.