Patent ID: 7808503
Filing Date: 2010-10-05
Classification: G06T

Abstract:
1. A deferred graphics pipeline processor comprising: a geometry unit configured to receive primitive data related to a vertex on a surface and output a data stream in response thereto; a mode extraction unit configured to receive the data stream from the geometry unit and separate the data stream into spatial data and non-spatial data; a sorting unit configured to receive the spatial data from the mode extraction unit for storage; a multi-buffered polygon memory configured to receive the non-spatial data from the mode extraction unit for storage; and a mode injection unit configured to retrieve at least a portion of the non-spatial data from the polygon memory and output retrieved non-spatial data; wherein the mode injection unit is associated with at least one cache to determine whether the retrieved non-spatial data is cached, and the mode injection unit is operative to read the non-spatial data previously stored in a first frame simultaneously while the mode extraction unit is operative to store the non-spatial data in a second frame.