Patent ID: 6137725
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A method for operating an electrically programmable and erasable semiconductor non-volatile storage device having a matrix of memory cells arranged in rows and columns, the matrix including a sector of cells that are accessible through an associated plurality of rows, wherein an output terminal having a control signal thereon is directly connected to each of the plurality of rows, the method comprising an act of:applying a non-negative voltage to a control terminal of a p-channel depletion transistor disposed between a ground reference terminal having a ground reference signal thereon and the output terminal to enable erasure of the cells of the sector of the matrix wherein the control terminal is a different terminal than the output terminal and the act of applying includes an act of:providing a conduction path between the output terminal and the ground reference terminal such that, in response to the non-negative voltage, a voltage potential of the control signal is controlled to be substantially equal to a voltage potential of the ground reference signal.