Patent ID: 6091639
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a first memory cell array and a second memory cell array, each including memory cells arranged in matrix form and having row lines and column lines;row decoder means for selecting the row line, connected to the row lines of each of the first memory cell array and the second memory cell array;a plurality of first column select transistors and a plurality of second column select transistors for selecting the column line, each of the column select transistors having a drain, a source and a gate, the source of the first column select transistor connected to the column line of the first memory cell array, the source of the second column select transistor connected to the column line of the second memory cell array and the gate of the column select transistor connected to a column decoder;first data detecting means and second data detecting means for detecting data stored in the memory cell, the first data detecting means connected to the drain of the first column select transistor, and second data detecting means connected to the drain of the second column select transistor, wherein the data stored in the memory cell of the first memory cell array is not detected by the first data detecting means when the data stored in the memory cell of the second memory cell array is detected by the second data detecting means, and the data stored in the memory cell of the second memory cell array is not detected by the second data detecting means when the data stored in the memory cell of the first memory cell array is detected by the first data detecting means; anddata discriminating means for discriminating whether the data from the first data detecting means is outputted or the data from the second data detecting means is outputted, an output of the data discriminating means being transferred to an output circuit.