Patent ID: 7588987
Filing Date: 2009-09-15
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming an isolation region by etching a predetermined portion of a semiconductor substrate and filling the predetermined portion with an insulating material; forming a gate by patterning a gate oxide layer and a gate electrode layer on the semiconductor substrate for each of a PMOS transistor and an NMOS transistor; forming lightly doped source/drain regions at both sides of the gate by implanting impurity ions into the semiconductor substrate at a low density, wherein the implanting impurity ions for the PMOS transistor and the NMOS transistor have opposite conductivities; forming heavily doped source/drain regions by implanting impurity ions into the semiconductor substrate adjacent to the lightly doped source/drain regions at a high density; selectively forming a silicide layer on the gate and the source/drain regions; and forming a nitride layer on an entire upper surface of the semiconductor substrate.