Patent ID: 7833842
Filing Date: 2010-11-16
Classification: B82Y,G11C,H01H,H01L

Abstract:
1. A method for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer, the method comprising: selecting a microscale-layer substrate; selecting a number of pins, and a pin type for each of the number of pins, for each fundamental unit of the microscale-layer substrate; selecting a lattice symmetry for the microscale layer; selecting fundamental-unit dimensions and a fundamental-unit shape for the microscale layer; selecting a pin configuration for the fundamental units of microscale layer, selecting orientations and positions for pad-interconnected-nanowire unit (PINU) bundles of one or more nanoscale sub-layers of the predominantly nanoscale layer, each nanoscale layer including PINU bundles oriented in one direction; determining positions, and identities of nanowires to be connected at each position, for nanowire junctions within the nanoscale layer; fabricating the microscale layer by a microelectronics-fabrication technique according to the selected fundamental-unit dimensions, fundamental-unit shape, and fundamental-unit pin configuration; and fabricating, sub-layer-by-sub-layer, the nanoscale sub-layers of the nanoscale/microscale interface according to the selected orientations and positions for PINU bundles and determined positions, and determined identities of nanowires to be connected at each position, for nanowire junctions.