Patent ID: 6677679
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A semiconductor device, comprising:a first metallization level, said first metallization level including a first metal feature; a first diffusion barrier layer, comprising a first material, disposed over said first metallization level; a second etch stop layer, comprising a second material, disposed over said first diffusion barrier layer; a first etch stop layer disposed on said second etch stop layer with a first interface therebetween; a dielectric layer disposed over said first etch stop layer; an opening having side surfaces extending through said dielectric layer, said first and second etch stop layers, and said first diffusion barrier layer to said first metal feature; metal within said opening forming a second metal feature; and a second metallization level above said dielectric layer, wherein said first material is different from said second material, said first diffusion barrier layer, said second etch stop layer, said first etch stop layer and said dielectric layer form a first interlayer level, said first metallization level and said second metallization level form adjacent metallization levels, and said first interlayer level separating said adjacent metallization levels.