Patent ID: 7594223
Filing Date: 2009-09-22
Classification: G06F

Abstract:
1. A computer-implemented method for performing compiler straight-line post-increment (SLPI) optimization for memory access instructions of a computer program executed on a processor, comprising: performing a SLPI preparation on candidate memory access instructions to obtain an intermediate stream of code containing pseudo-memory instructions, each of said candidate memory access instructions representing a non-loop memory access instruction and employing an address that is computed based on the same base register shared by another instruction of said candidate memory access instructions; and performing a SLPI synthesis on said intermediate stream of code to obtain architected memory instructions conforming to a base register auto-incrementing addressing mode, wherein the step of performing the SLPI synthesis includes building post-increment chains of pseudo-memory instructions by placing pseudo-memory instructions that share the same pseudo-memory instruction base into the same post-increment chain, the step of performing the SLPI preparation and the step of performing the SLPI synthesis performed prior to a compiler register allocation phase, the step of performing the SLPI preparation performed prior to a compiler instruction scheduling phase, and the step of performing the SLPI synthesis performed after said compiler instruction scheduling phase.