Patent ID: 6274936
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method used during the formation of a semiconductor device comprising the following steps:providing a semiconductor substrate assembly;forming a conductive layer over said semiconductor substrate assembly;depositing a first dielectric layer overlying said conductive layer;removing a portion of said first dielectric layer to form at least first and second openings therein, wherein said conductive layer is exposed by said openings in said first dielectric layer and provides an electrical path between said first and second openings;subsequent to said step of removing a portion of said first dielectric layer, etching said conductive layer at said openings to recess said conductive layer within said first dielectric layer; andsubsequent to said step of etching said conductive layer, forming a second dielectric layer within said openings in said first dielectric layer to electrically isolate said conductive layer from said openings.