Patent ID: 6720836
Filing Date: 2004-04-13
Classification: H03K

Abstract:
A relaxation oscillator circuit, comprising:a first current source (101) coupling a first voltage source (199) to a first node (VOR); a first transistor (110) having a drain connected to the first voltage source (199), a gate forming a second node, and a source connected to the first node (VOR); a second current source (103) coupling the first voltage source (199) to a third node (VOL); a second transistor (114) having a drain connected to the first voltage source (199), a gate connected to the second node, and a source connected to the third node (VOL); a third transistor (112) having a drain connected to the first node (VOR), a gate connected to the third node (VOL), and a source forming a fourth node (VSR); a fourth transistor (116) having a drain connected to the third node (VOL), a gate connected to the first node (VOR), and a source forming a fifth node (VSL); a first current sink (105) coupling a second voltage source (198) to the fourth node (VSR); a second current sink (107) coupling the second voltage source (198) to the fifth node (VSL); a capacitor (118) coupling the fourth node (VSR) to the fifth node (VSL); a fifth transistor (130) having a drain connected to the first voltage source (199), a gate connected to the second node, and a source forming a sixth node; a third current source (138) coupling the first voltage source (199) to the sixth node; a third current sink (136) coupling the second voltage source (198) to the sixth node; an amplifier (132) having an output connected to the second node, an inverting terminal connected to the sixth node, and a non-inverting terminal; and a third voltage source (134) coupling the non-inverting terminal of the amplifier (132) to the first voltage source (199); said first and third nodes providing an output of the oscillator circuit.