Patent ID: 6667536
Filing Date: 2003-12-23
Classification: H01L,Y10T

Abstract:
An integrated circuit structure comprising:a semiconductor substrate having a plurality of insulating layers and a plurality of conductive layers therebetween; an outer coil; and an inner coil disposed within the interior of said outer coil; said outer coil further comprising: a plurality of parallel first conductive strips overlying said semiconductor substrate and formed within a lower conductive layer of the semiconductor substrate; a first stack of one or more conductive vias in electrical connection with a first end of each one of the plurality of first conductive strips; a second stack of one or more conductive vias in electrical connection with a second end of each one of the plurality of first conductive strips; and a plurality of parallel second conductive strips having a first end in electrical connection with the uppermost via of the first stack of one or more conductive vias, and a second end in electrical connection with the uppermost via of the second stack of one or more conductive vias, such that a second conductive strip is disposed between and interconnects two successive first conductive strips, wherein the plurality of second conductive strips are vertically spaced-apart from the plurality of first conductive strips with at least three intervening conductive layers therebetween; said inner coil further comprising: a plurality of parallel third conductive strips overlying said semiconductor substrate; a third stack of one or more conductive vias in electrical connection with a first end of each one of the plurality of third conductive strips; a fourth stack of one or more conductive vias in electrical connection with a second end of each one of the plurality of third conductive strips; and a plurality of parallel fourth conductive strips having a first end in electrical connection with the uppermost via of the third stack of one or more conductive vias, and a second end in electrical connection with the uppermost via of the fourth stack of one or more conductive vias, such that a fourth conductive strip is disposed between and interconnects two successive third conductive strips , wherein the plurality of second conductive strips are vertically spaced-apart from the plurality of first conductive strips with at least three intervening conductive layers therebetween.