Patent ID: 8877597
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A method, comprising: forming a gate structure for a transistor above an active region formed in a semiconductor substrate; after forming said gate structure, performing an angled ion implantation process and a substantially vertically oriented ion implantation process to form an implanted silicide stop layer within at least in a portion of said active region of said transistor, said implanted silicide stop layer having a length and a thickness when viewed in a cross-section taken along a direction substantially parallel to a channel length of said transistor, wherein substantially the entire length of said implanted silicide stop layer is embedded in said active region and wherein a portion of said implanted silicide stop layer has a maximum depth of penetration relative to an upper surface of said active region; forming a drain/source region in said active region such that said drain/source region has a bottom surface that is positioned below said maximum depth of penetration of said implanted silicide stop layer; and forming a metal silicide region in said drain/source region such that said metal silicide region extends at least from said upper surface of said active region and stops on at least a portion of said implanted silicide stop layer.