Patent ID: 6134675
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A method of testing a multi-core processor comprising the steps of:providing a plurality of processor cores within a single integrated circuit;providing a test input signal to the plurality of processor cores for use when the integrated circuit is in a test mode, the test input signal selected to provide an expected test output signal value at an output pin of the integrated circuit;processing the test input signal with the plurality of processor cores and providing a plurality of core test signals in response thereto;coupling the plurality of core test signals from the plurality of processor cores to testing logic circuitry within the single integrated circuit;using the testing logic circuitry to produce an output signal at the output pin of the integrated circuit, the output signal having a value indicating when at least two of the plurality of core test signals represent different logic values, wherein the output pin of the integrated circuit is the only pin within the integrated circuit used to test the plurality of processor cores and the plurality of processor cores are tested substantially at the same time; andrepeating the steps by providing at least one additional test input signal to the plurality of processor cores.