Patent ID: 9093169
Filing Date: 2015-07-28
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory apparatus comprising: a memory cell block configured to include a plurality of memory cell strings each of which including a plurality of memory cells, a dummy memory cell string which includes a plurality of dummy memory cells, and a plurality of bit lines connected to the plurality of cell strings and the dummy memory cell string; a plurality of page buffers configured to be connected to any one of the plurality of bit lines that are connected to the memory cell strings in response to a sensing signal to sense data stored in the memory cells, latch the data, and apply the latched data to an output node in response to a sensing output signal and including a first capacitor; and a reference page buffer unit configured to be connected to the bit line connected to the dummy memory cell string in response to the sensing signal to sense the dummy memory cells and activate the sensing output signal, wherein the sensing signal is activated after a precharge signal for precharging the bit line and a presensing signal for charging the first capacitor are activated.