Patent ID: 6031779
Filing Date: 2000-02-29
Classification: G11C

Abstract:
A dynamic memory formed on a semiconductor substrate comprising:a pair of bit lines;a plurality of word lines;a plurality of dynamic memory cells, each of which is coupled to one line of said pair of bit lines and one of said plurality of word lines;a sense amplifier including a pair of PMOS transistors and a pair of NMOS transistors, each of said pairs of PMOS and NMOS transistors having their sources coupled in common, their drains coupled to said pair of bit lines, respectively, and their gates cross-coupled to said drains, respectively;a first external terminal for receiving a first external supply voltage;a first NMOS transistor which has a drain coupled to said first external terminal and a gate supplied with a first internal voltage so that a second internal voltage stabilized with respect to said first external supply voltage is derived from a source of said first NMOS transistor; anda first PMOS transistor having a source coupled to said source of said first NMOS transistor and a drain coupled to said sources of said pair of PMOS transistors,wherein said sources and drains of said pair of PMOS transistors and said first PMOS transistor are formed in an N-well in said semiconductor substrate, andwherein said N-well is supplied with said second internal voltage,further comprising:a switch transistor which has a source-drain path provided between said sources of said pair of PMOS transistors and a terminal supplied with a third internal voltage being lower than said second internal voltage,wherein said sense amplifier provides said pair of bit lines with a pair of complementary signals having a high side voltage and a low side voltage on the basis of information stored in a memory cell selected from said plurality of dynamic memory cells,wherein, in a first period, said high side voltage approaches said second internal voltage in response to said first PMOS transistor being enabled, andwherein, in a second period following said first period, said high side voltage approaches said third internal voltage in response to said switch transistor being enabled.