Patent ID: 7190031
Filing Date: 2007-03-13
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell having a first transfer MISFET and a second transfer MISFET disposed at portions where a pair of complementary data lines and a word line intersect, a first drive MISFET and a second drive MISFET, and a first vertical MISFET and a second vertical MISFET, the first drive MISFET and the first vertical MISFET, and the second drive MISFET and the second vertical MISFET being cross-connected, wherein the first and second transfer MISFETs, and the first and second drive MISFETs are formed on a major surface of a semiconductor substrate, wherein the first and second vertical MISFETs are formed over the first and second transfer MISFETs and the first and second drive MISFETs respectively, wherein the first vertical MISFET has a source, a channel region and a drain formed in a first laminated body extending in a direction perpendicular to the major surface of the semiconductor substrate, and a gate electrode formed on sidewall portions of the first laminated body with a gate insulating film interposed therebetween, wherein the second vertical MISFET has a source, a channel region and a drain of a second laminated body extending in a direction perpendicular to the major surface of the semiconductor substrate, and a gate electrode formed on sidewall portions of the second laminated body with a gate insulating film interposed therebetween, and wherein the sources of the first and second vertical MISFETs are electrically connected to a source voltage line formed over the first and second laminated bodies.