Patent ID: 6389526
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A method of operating a multiprocessor computer system comprising a plurality of circuit nodes and a plurality of memories, wherein each circuit node comprises at least one microprocessor coupled to a memory controller, wherein each memory controller is coupled to one of the plurality of memories, wherein the plurality of circuit nodes are in data communication with each other, wherein a first circuit node is coupled to an I/O bridge, the method comprising:the I/O bridge generating a non-coherent memory access command packet, wherein the non-coherent memory access command comprises a first pipe identification; the I/O bridge transmitting the non-coherent memory access command packet to the first circuit node via a non-coherent link connected between the I/O bridge and the first circuit node; the first circuit node receiving the non-coherent memory access command packet and generating a coherent memory access command packet using information in the received non-coherent memory access command packet; the first circuit node transmitting the non-coherent memory access command packet to a second circuit node; the I/O bridge generating a non-coherent interrupt command packet, wherein the non-coherent interrupt command comprises a second pipe identification; the I/O bridge transmitting the non-coherent interrupt command packet to the first circuit node via the non-coherent link connected between the I/O bridge and the first circuit node; the first circuit node receiving the non-coherent interrupt command packet and generating a coherent interrupt command packet using information in the received non-coherent interrupt command packet; comparing the first and second pipe identifications after the first circuit node receives the non-coherent interrupt command packet; the first circuit transmitting the coherent interrupt command packet to a third circuit node if the first and second pipe identifications do not compare equally.