Patent ID: 6287892
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method of producing a stacked semiconductor device having a laminated structure, comprising the steps of:forming plural semiconductor sub-units byforming a metallic bump on a lower surface of each of plural semiconductor devices,coating a pad portion on an upper surface of each of plural substrates, the pad portions and metallic bumps being positioned so as to allow contact-alignment between corresponding ones of the plural semiconductor devices and the plural substrates, andutilizing a flip-chip method, joining the corresponding plural semiconductor devices and plural substrates to form the plural semiconductor sub-units;for each of the plural semiconductor sub-units, injecting a sealing resin into a connecting region defined between the upper surface of each of the substrates and the lower surface of the joined semiconductor device so as to seal the connecting region of each semiconductor sub-unit;providing on the upper surface of the substrates of some of the semiconductor sub-units, in a region apart from the connecting region, a sub-unit connecting bump;vertically stacking the plural semiconductor sub-units on-upon-another so that a second semiconductor unit is stacked atop a first semiconductor unit and so that the connecting bump of the first semiconductor sub-unit is joined to a lower surface of the second semiconductor sub-unit;electrically connecting the first stacked semiconductor sub-unit to other semiconductor sub-units; andinjecting a shock-absorbing material to fill a region between an upper surface of the semiconductor device of the first semiconductor sub-unit and the lower surface of the substrate of the second semiconductor sub-unit.