Patent ID: 6627950
Filing Date: 2003-09-30
Classification: H01L,Y10S

Abstract:
A trench DMOS transistor cell comprising:a substrate of a first conductivity type, said substrate having a surface; an epitaxial layer of said first conductivity type formed on said surface of said substrate, said epitaxial layer having a top surface and a bottom surface, said epitaxial layer having a substantially uniform initial dopant concentration at formation; a body region of a second conductivity type opposite to said first conductivity type formed in said epitaxial layer, said body region extending, as measured from said top surface of said epitaxial layer, to a first depth dmax at a first location and to a depth of d at a second location, where d is less than dmax, said first and second locations being separated by a predetermined horizontal distance; a source region of said first conductivity type formed in said expitaxial layer above a portion of said body region, said portion of said body region being located between said second location and said source region; and a trench formed in said epitaxial layer, having substantially vertical side walls, and extending from said top surface of said epitaxial layer to a depth dtr less than said depth dmax and greater than said depth d, said trench being (i) closer to said second location than to said first location and (ii) horizontally adjacent said source region; wherein breakdown in said trench DMOS transistor cell occurs across said epitaxial layer at a position closer to said first location than to said second location.