Patent ID: 7378703
Filing Date: 2008-05-27
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including a first active region, a second active region having a greater height than that of the first active region, and a device isolation layer in contact with the first active region; a gate pattern composite having a step structure, which is formed on a border region between the first active region and the second active region, wherein the gate pattern composite extends from a predetermined portion of the first active region to a predetermined portion of the second active region; gate spacers formed on both sidewalls of a gate pattern of the gate pattern composite; a first cell junction formed in the first active region at one gate spacer and connected to a storage node contact; and a second cell junction formed in the second active region at the other gate spacer and connected to a bit line contact, wherein a first portion of the gate pattern passes an upper portion of the first active region and is roundly projected toward the first active region, thereby forming a wave pattern, and a second portion of the gate pattern passes an upper portion of the device isolation layer and is not roundly projected.