Patent ID: 8238385
Filing Date: 2012-08-07
Classification: H04L

Abstract:
1. A data processing circuit comprising: a first circuit configured to select one of a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal, the first circuit further configured to select the first digital signal in response to a request to output the first signal from the external controller, and to select the second digital signal except during periods when the first digital signal is selected; a second circuit configured to output the selected one of the first digital signal and the second digital signal to the external controller, the first digital signal output synchronous with the clock and the second digital signal output asynchronous with the clock; and an input circuit configured to input data from the external controller synchronously with the clock signal during a period when the first circuit selects the second digital signal as the-signal output to the external controller; wherein the first circuit is further configured to select the second digital signal during a period when the first digital signal should be output according to a preset schedule, if the request to output the first digital signal is not received from the external controller.