Patent ID: 6225839
Filing Date: 2001-05-01
Classification: H03F,H03K

Abstract:
Buffer circuit comprising: a signal output transistor having a base connected to a signal input terminal, a collector connected to a first power source voltage, and an emitter connected to a signal output terminal;first and second transistors having respective emitters connected to each other, constituting a differential circuit;a voltage-setting transistor having a collector connected to a first voltage source and an emitter connected to the base of the first transistor;a reference voltage source that supplies a reference voltage to the base of the second transistor;a compensation current generation transistor having an emitter connected to the first power source voltage, and a collector connected to the base of the voltage-setting transistor;a compensation current supply transistor having an emitter connected to the first power source voltage, and a collector connected to the base of the signal output transistor;and the base of the compensation current supply transistor and the base of the compensation current generation transistor being connected to the collector of the second transistor.