Patent ID: 6248662
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit, said method comprising:providing a plurality of semiconductor devices in and on a semiconductor substrate;forming a plurality of semiconductor structures overlying a top surface of said semiconductor substrate, wherein a plurality of gaps locate between portions of said semiconductor structures;forming a first dielectric layer over said top surface and covering said semiconductor structures;forming a photoresist over said first dielectric layer, wherein said photoresist does not never cover said gaps;implanting said first dielectric layer with a BF.sub.3 ion source whereby a plurality of implanted ions such as BF.sup.2+, B.sup.3+, F.sup.- are implanted in part of said first dielectric layer that not covered by said photoresist;removing said photoresist;treating said part of said first dielectric layer with rapid thermal process whereby B.sub.2 O.sub.5 molecules and SiOF molecules are formed on said part of said first dielectric layer;forming a second dielectric layer over said first dielectric layer; andcompleting a fabrication of said integrated circuit.