Patent ID: 6119192
Filing Date: 2000-09-12
Classification: G06F

Abstract:
A bus bridge circuit for coordinating data transfers between a first bus and a separate second bus, the bus bridge circuit including:a first interface coupled to the first bus for managing data operations between the bus bridge and first bus devices connected to the first bus, and for receiving first initialization parameters from a system Basic Input/Output System (BIOS) memory; anda second interface coupled to the second bus for managing data operations between the bus bridge and second bus devices connected to the second bus; anda third interface coupled to a third bus capable of receiving second initialization parameters from a supplemental parameter memory, which supplemental parameter memory is separate and distinct from said system BIOS memory; anda controller circuit for configuring initialization registers in the bus bridge circuit associated with said second bus devices, said controller circuit configuring one or more of said initialization registers initially using said second initialization parameters.