Patent ID: 6820189
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A computation core for executing programmed instructions, comprising:a single computation block configured to perform digital signal processor operations in response to digital signal processor instructions, each of which specifies at least two mathematical operations to be executed in parallel, and configured to perform microcontroller operations in response to microcontroller instructions, each of which specifies a single microcontroller operation, wherein the digital signal processor instructions each have a first length and the microcontroller instructions each have a second length that is less than the first length; a register file for storing operands for and results of the digital signal processor operations and the microcontroller operations; and control logic for providing control signals to said computation block and said register file in response to the digital signal processor instructions and the microcontroller instructions for executing the digital signal processor instructions and the microcontroller instructions, wherein said computation block, said register file and said control logic are configured to efficiently execute an application which is characterized by high code density and which includes a relatively small number of the digital signal processor instructions and a relatively large number of the microcontroller instructions without performing operations to switch between the digital signal processor instructions and the microcontroller instructions.