Patent ID: 6347377
Filing Date: 2002-02-12
Classification: G06F

Abstract:
A power management apparatus for a plurality of devices in a processor-based system, comprising:a memory to store instruction sequences by which the processor-based system is processed; and a processor coupled to the memory, wherein the stored instruction sequences cause the processor to, for each of the plurality of devices: (a) determine a system access time of a respective device; (b) determine if the system access time of the respective device is less than a first predetermined value, if so, increasing an inactivity period of the respective device, said inactivity period indicating a time period during which the respective device is inactive before deactivating the respective device, (c) determine if the system access time of the respective device is greater than a second predetermined value, if so, decreasing the inactivity period of the respective device; and (d) determine if the system access time of the respective device is within a range between the first and the second predetermined value, if so, preventing the inactivity period of the circuit from changing.