Patent ID: 6684275
Filing Date: 2004-01-27
Classification: G11C,H03M

Abstract:
Apparatus for converting a serially received data word to a parallel output data word, said apparatus comprising:a serial data input interface that receives the serially received data work, and provides a received data word; a serial-to-parallel mapping circuit that receives said received data word and generates memory write control and write address signals; a memory device having a first port responsive to said memory write control signals and write address signals for writing said received data word into said memory device, and a second port responsive to memory read control and read address signals for reading data from said memory device; said serial-to-parallel mapping circuit comprises means for partitioning said received data word into a plurality of partitioned received data words and for generating said memory write control signals such that said partitioned received data words are written into said memory device at uniquely associated memory addresses; and output interface circuitry that generates said memory read control and read address signals, and receives output data from said memory device and reorders the bits of said output data to provide a parallel output data word, wherein said output interface circuitry comprises an output mapping circuit responsive to said output data and a parallel output interface wherein reordering of the bits of said output data word is performed by mapping interconnects between an output port of said output mapping circuit and an input port parallel output interface, wherein said parallel output interface also includes a parallel output interface output port that provided the parallel output data word.