Patent ID: 6464445
Filing Date: 2002-10-15
Classification: H01L,Y10S

Abstract:
A system for improving throughput of semiconductor wafer processing for wafer carriers from a capacity of N product wafers to a capacity of N+y product wafers without increasing the number of furnaces, comprising:a wafer carrier including a plurality of rails, the rails having a plurality of teeth for forming slots having a slot pitch for holding said semiconductor wafers, the wafer carrier being adapted to carry (N+y) product wafers in a flat zone while maintaining dimensions of the wafer carrier; and a wafer transferring mechanism comprising a plurality of wafer forks of a fork pitch between about 4.61 to 4.81 mm for loading and removing said semiconductor wafers from the wafer carrier; wherein the wafer transferring mechanism includes y/n forks where n is an integer value and y/n is a positive integer value.