Patent ID: 7710501
Filing Date: 2010-05-04
Classification: H04N

Abstract:
1. An apparatus comprising: circuitry to synthesize an output video clock; circuitry to receive an input video synchronization signal; circuitry to change a frequency of the output video clock based on an intended number of video output clock cycles per input vertical period and a period of the input video synchronization signal; wherein the circuitry to change a frequency of the output video clock comprises: circuitry to generate an error signal based on a comparison of the intended number of video output clock cycles per input vertical period and an actual number of video output clock cycles per input vertical period, wherein the period of the input video synchronization signal determines a length of the input vertical period; circuitry that receives the error signal and generates a frequency signal; wherein the circuitry to generate an error signal comprises a counter; wherein the circuitry that receives the error signal and generates a frequency signal comprises one or more of, multiplication circuitry, a serial generator, a trigger generator having an output coupled to the serial generator, and an accumulator; wherein the accumulator comprises: addition circuitry and a latch.