Patent ID: 7792895
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. A system configured to compute partial dot products for a matrix multiplication operation, the system comprising: a global memory configured to store a first source matrix, a second source matrix and a result matrix; a processing unit configured to execute a cooperative thread array, wherein the processing unit includes hardware logic configured to synchronize the threads of the cooperative thread array by pausing one or more of the threads at a specific instruction until all threads in the cooperative thread array reach the specific instruction; a local memory coupled to the processing unit and configured to store at least one tile of the first source matrix and at least one tile of the second source matrix; and a plurality of local registers coupled to the processing unit, wherein the cooperative thread array is configured to: wherein the hardware logic synchronizes the threads of the cooperative thread array after the first tile from the first row of the first source matrix and the first tile from the first column of the second source matrix are copied to the local memory but before the cooperative thread array begins computing the partial dot products for the elements of the first tile of the result matrix.