Patent ID: 6178515
Filing Date: 2001-01-23
Classification: G06F

Abstract:
A multi-CPU device comprising:a master CPU block mounted therein with a general purpose OS;a slave CPU block mounted therein with a realtime OS;a bus arranged for connecting said master CPU block and slave CPU block to each other therethrough;said bus being connected to control function blocks connected to a controlled equipment, so that the controlled equipment may be controlled through said control function blocks based on said realtime OS of said slave CPU block; anda UPS constructed so as to convert an AC current inputted thereto into a DC current and output the DC current to said master CPU block and slave CPU block;said UPS including a battery, a service interruption sensing circuit and a realtime OS interface;said realtime OS including a program of shutting down said general purpose OS;said realtime OS outputting a DC current from said battery to said master CPU block and slave CPU block when said service interruption sensing circuit of said UPS senses service interruption;said realtime OS interface outputting a service interruption sensing signal to said realtime OS, so that said realtime OS which detected service interruption shuts down said general purpose OS.