Patent ID: 6298364
Filing Date: 2001-10-02
Classification: G06F

Abstract:
An operation apparatus for carrying out an instruction specifying a combined operation of an arithmetic operation and a shifting operation using digital data of n bit length, comprising:instruction decoding means for decoding the instruction into an arithmetic instruction indicative of the arithmetic operation of the instruction and a shifting instruction indicative of the shifting operation of the instruction;arithmetic operation means, coupled to said instruction decoder means, for receiving said digital data, carrying out one of a plurality of arithmetic and logical operations according to the arithmetic instruction in response to said digital data, and providing an operation resultant data of 2n bit length over one of a plurality of outputs in which at least precision of said combined operation is guaranteed;selection means, coupled to said arithmetic operation means, for selecting the one of the plurality of outputs on which said operation resultant data is provided in accordance with a selection signal provided by said instruction decoding means;shifting operation means having 2n bit width capacity, operatively coupled to said selection means to receive said selected operation resultant data, for carrying out a shifting operation in response to said selected operation resultant data according to the shifting instruction; androunding processing means, coupled to receive an output value of said shifting operation means, for rounding the output value of said shifting operation means to n-bit length in accordance with a rounding instruction provided by said instruction decoding means, said rounding processing means not rounding the output value of said shifting operation means when the arithmetic instruction is indicative of a logical operation and rounding the output value of said shifting operation means when the arithmetic instruction is indicative of an arithmetic operation,said combined operation specified by the instruction being performed during a single instruction execution period.