Patent ID: 7508233
Filing Date: 2009-03-24
Classification: G06F

Abstract:
1. A full-adder of a complementary carry logic voltage compensation, comprising: a first multiplexer, having two input terminals for inputting a carry input and a carry inverted phase input respectively, and a select terminal for inputting an add signal; a first inverter, having an input terminal connected to an output signal of said first multiplexer; a second multiplexer, having two input terminals for inputting an addend and a summand respectively, and a select terminal for inputting an output signal of said first inverter, and said output terminal of said second multiplexer producing a carry signal; a second inverter, having an input terminal connected to an output signal of said second multiplexer for producing a carry inverted phase signal; and a third multiplexer, having two input terminals for inputting said summand and a carry inverted phase signal produced by said second inverter respectively, and a select terminal for inputting an output signal of said first inverter, and said output terminal of said third multiplexer producing a sum signal.