Patent ID: 7349449
Filing Date: 2008-03-25
Classification: H04J,H04L

Abstract:
1. A multiplexer cell for converting input signals with a data input rate into an output signal with a data output rate which, based on the number of input signals, is higher than the data input rate comprising: a clock input connection for supplying a clock signal; a first data input connection for supplying a first input signal at the data input rate and at least one second data input connection for supplying a second input signal at the data input rate, wherein the data input rate is the same as the frequency of the clock signal; a data output connection for the output of the output signal at the data output rate which is higher than the data input rate; a first register circuit the input of which is connected to the first data input connection and the clock input of which is connected to the clock input connection for the flank-controlled output of the first input signal; a second register circuit the input of which is connected to the at least one second data input connection and the clock input of which is connected to the clock input connection for the flank-controlled output of the second input signal; a delay circuit the input of which is connected to the output of the second register circuit and the clock input of which is connected to the clock input connection for the delayed output of the second input signal; and a logic circuit with a first logic input connected to the output of the first register circuit and with a second logic input connected to the output of the delay circuit, and with a logic output to the data output connection, wherein the logic circuit is configured in such a way that each change in status at one of the first or second logic input leads to a change in status at its logic output.