Patent ID: 8755485
Filing Date: 2014-06-17
Classification: G09G,G11C

Abstract:
1. A shift register comprising a plurality of stages for sequentially outputting scan pulses, wherein each of the stages comprises: a node controller that controls signal states of a set node and a reset node; and an output unit supplied with any one of a plurality of clock pulses having different phases, the output unit outputting the supplied clock pulse as a corresponding one of the scan pulses through an output terminal thereof according to the signal states of the set node and reset node, wherein the node controller of an nth one of the stages comprises: a first discharging switching device turned on or off in response to a scan pulse from a downstream one of the stages, the first discharging switching device being connected between any one of a plurality of clock transfer lines, the clock transfer lines transferring the clock pulses, respectively, and the set node; a second discharging switching device turned on or off in response to a scan pulse from an upstream one of the stages, the second discharging switching device being connected between the clock transfer line and the reset node; a first switching device turned on or off in response to a scan pulse from an (n−2)th one of the stages, the first switching device electrically interconnecting the set node and a charging voltage line when turned on; a second switching device turned on or off in response to a clock pulse supplied to the output unit of an (n−1)th one of the stages, the second switching device electrically interconnecting the output terminal of the (n−1)th stage and the set node when turned on; a third switching device turned on or off in response to a charging voltage from the charging voltage line, the third switching device electrically interconnecting the charging voltage line and the reset node when turned on; and a fourth switching device turned on or off in response to a voltage supplied to the set node, the fourth switching device electrically interconnecting the reset node and a discharging voltage line when turned on, wherein the first discharging switching device of the node controller of the nth stage is turned on or off in response to a scan pulse from an (n+2)th one of the stages, and electrically interconnects the set node and the clock transfer line when turned on, wherein the second discharging switching device of the node controller of the nth stage is turned on or off in response to the scan pulse from the (n−2)th stage, and electrically interconnects the reset node and the clock transfer line when turned on, wherein the discharging voltage line transfers a discharging voltage, the discharging voltage being lower than the charging voltage.