Patent ID: 6358842
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A method to form damascene interconnects in the manufacture of an integrated circuit device comprising:providing copper conductors overlying a semiconductor substrate; providing a first passivation layer overlying said copper conductors; depositing a low dielectric constant layer overlying said first passivation layer; depositing a photoresist layer overlying said low dielectric constant layer; patterning said photoresist layer to form a via mask; thereafter etching through said low dielectric constant layer to form said via openings; simultaneously stripping away said photoresist layer and forming a sidewall passivation layer on the sidewalls of said via openings by using a sulfur-containing gas; etching through said first passivation layer to expose underlying said copper conductors; depositing a barrier metal layer overlying said first passivation layer and filling said via openings; depositing a copper layer overlying said barrier metal layer and filling said via openings; and polishing down said copper layer to complete said damascene interconnects in the manufacture of the integrated circuit device.