Patent ID: 8742839
Filing Date: 2014-06-03
Classification: H01L

Abstract:
1. A double through silicon via structure, comprising; a first die unit, arranged for outputting an input signal; a first signal path, including a first driving unit and a first TSV unit, and the first driving unit including a first end, a second end and a third end, and the first end of the first driving unit being electrically coupled to an output end of the first die unit, and the second end of the first driving unit being electrically coupled to an input end of the first TSV unit; a second signal path, including a second driving unit and a second TSV unit, and the second driving unit including a first end, a second end and a third end, and the first end of the second driving unit being electrically coupled to the output end of the first die unit, and the second end of the second driving unit being electrically coupled to the input end of the second TSV unit; a receiving unit, with an input end electrically coupled to output ends of the first TSV unit and the second TSV unit; and a second die unit, with an input end electrically coupled to an output end of the receiving unit; and an inverter, with an input end electrically coupled to an output end of the first die unit and output ends of the inverter are electrically coupled to both the first signal path and the second signal path, and the inverter receiving the input signal to output a control signal to the first signal path and the second signal path; wherein the first driving unit receives the input signal for outputting a first signal in an opposite direction of the input signal to the first TSV unit and drives the first TSV unit to transmit the first signal; the second driving unit receives the input signal to output a second signal in an opposite direction of the input signal to the second TSV unit and drives the second TSV unit to transmit the second signal; and the receiving unit receives the first signal and the second signal to output a combined signal to the second die unit; wherein the receiving unit includes an OR gate or a NOR gate to reconstruct the first signal and the second signal into the combined signal.