Patent ID: 6061368
Filing Date: 2000-05-09
Classification: H04L

Abstract:
Custom circuitry for reducing an L-bit data unit into an N-bit data unit selectable to include any combination of bits from the L-bit data unit, where L is an integer greater than two, N is an integer greater than one and L is greater than N, comprising:N successive multiplexors, each multiplexor receiving as inputs bits from M bit positions within the L-bit data unit including all but the first bit received as an input by the immediately preceding multiplexor, if any, and all but the last bit received as an input by the immediately succeeding multiplexor, if any, and wherein M is an integer sufficiently great such that each bit within the L-bit data unit is received as an input by at least one of the N successive multiplexors; andmeans for instructing each multiplexor to select for transmission as an output a single bit, if any, from the bits received as inputs by the multiplexor.