Patent ID: 6118699
Filing Date: 2000-09-12
Classification: G11C,H01L

Abstract:
A semiconductor memory having a nonvolatile memory cell array, comprising:a semiconductor substrate of a first conductivity type;a plurality of source regions of a second conductivity type which are formed in said semiconductor substrate at predetermined intervals;a plurality of drain regions of the second conductivity type which are connected to a bit line formed between two adjacent source regions;a first insulation side wall formed in an offset pattern on an edge of each of said source regions which faces said drain region such that a bottom surface of said first side wall covers a surface of said semiconductor substrate;a second insulation side wall formed to have a front edge flush with an edge of said drain region which faces said source region, with a bottom surface of said second side wall covering a surface of said source region;channel regions formed on surface regions of said semiconductor substrate which are located between said source regions and said drain regions;a first insulating film formed on a surface of each of said channel regions;a nitride film formed on said first insulating film;a second insulating film formed on said nitride film; anda gate electrode used as a word line which is commonly formed on said source region, said drain region, and said second insulating film.