Patent ID: 9196343
Filing Date: 2015-11-24
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a memory cell array including first lines, second lines, and memory cells each including a variable resistor and each connected between one of the first lines and one of the second lines; and a control circuit configured to perform a voltage application operation of applying a first voltage to a selected first line connected to a selected memory cell and applying a second voltage having a voltage value lower than the first voltage to a selected second line connected to the selected memory cell, the control circuit being configured to select the voltage value of the second voltage from among a plurality of different voltage values and output the second voltage, wherein the control circuit is configured to perform a resistance value determination operation of reading a resistance value of the selected memory cell, the resistance value determination operation being an operation of applying a first read voltage to the selected first line, applying a second read voltage having a voltage value lower than the first read voltage to the selected second line, and comparing a cell current flowing to the selected memory cell with a certain determination value, and the control circuit is configured to execute the resistance value determination operation a plurality of times, changing either or both of the first read voltage and the second read voltage.