Patent ID: 6917538
Filing Date: 2005-07-12
Classification: G11C

Abstract:
1. A static semiconductor memory device having memory cells each formed from four transistors, comprising: a memory cell array constituted by arraying the memory cells in a matrix; a word line arranged in correspondence with each row of said memory cell array; a pair of bit lines arranged in correspondence with each column of the memory cell array; a word line selecting circuit which decodes an address for specifying the memory cell and outputs a plurality of select signals for selecting or unselecting said word lines; and a plurality of word line control circuits which control a potential of said word lines to one of at least three kinds of potentials on the basis of a control signal that changes in accordance with whether the memory cell is in an access mode or in a non-access mode, and the select signals output from said word line selecting circuit, wherein at least one of the memory cells is accessed in the access mode and any of the memory cells is not accessed in the non-access mode.