Patent ID: 9219066
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A semiconductor storage device, comprising: a semiconductor substrate, an element isolation region comprising a plurality of element isolation trenches formed into the semiconductor substrate so as to extend in a first direction taken along a surface of the semiconductor substrate; a plurality of first element regions and a plurality of second element regions, both disposed adjacent to at least one element isolation trench of the plurality of element isolation trenches in a second direction taken along the surface of the semiconductor substrate, each of the plurality of first element regions and plurality of second element regions extending in the first direction and being isolated from each other by a corresponding one of the plurality of element isolation trenches in the second direction, the second direction intersecting with the first direction; a first select gate electrode formed above a first gate insulating film formed in the plurality of first element regions; a first group of memory-cell gate electrodes formed above the first gate insulating film and being disposed above a single first element region of the plurality of first element regions, the first group of memory-cell gate electrodes being aligned along the first direction with the first select gate electrode; a second select gate electrode formed above a second gate insulating film formed in the plurality of second element regions; a second group of memory-cell gate electrodes formed above the second gate insulating film and being disposed above a single second element region of the plurality of second element regions, the second group of memory-cell gate electrodes being aligned along the first direction with the second select gate electrode and parallel to the first group of memory-cell gate electrodes; an unfilled gap formed in each of the plurality of element isolation trenches located adjacent to at least one first element region of the plurality of first element regions immediately below the first group of memory-cell gate electrodes, and located adjacent to at least one second element region of the plurality of second element regions immediately below the second group of memory-cell gate electrodes; and an insulation wall enclosing the unfilled gap formed in each of the plurality of element isolation trenches located adjacent to said at least one first element region immediately below the first select gate electrode, and located adjacent to said at least one second element region immediately below the second select gate electrode.