Patent ID: 6052000
Filing Date: 2000-04-18
Classification: G11C,H03K

Abstract:
A method for reducing the time-varying effects of overlap capacitance in a sample-and-hold circuit having a time-varying input voltage applied to an input terminal through a MOS transistor switch to charge a hold capacitor, a terminal of the hold capacitor connected to supply an output voltage; the method comprising:connecting a gate of the transistor switch to a first voltage to turn the switch on during a first ""track"" phase of operation, and to a second voltage to turn the switch off during a second ""hold"" phase of operation;providing a dummy MOS transistor having a current path connected to said terminal of said hold capacitor; andconnecting a gate of the dummy MOS transistor to the second voltage during the first phase of operation and to the output voltage during the second phase of operation.