Patent ID: 8484608
Filing Date: 2013-07-09
Classification: G06F

Abstract:
1. A process comprising steps of: a) preparing a verified hardware description of a circuit to be embodied in a base integrated circuit platform and a separate die, wherein the base integrated circuit platform includes a single die that has both ASIC and FPGA modules, wherein the verified hardware description of the circuit comprises a plurality of functions, wherein the separate die is outside of the base integrated circuit platform; b) separating the plurality of functions into standard functions and user-defined functions, wherein the user-defined functions comprise memory programmable functions and non-memory programmable functions; c) assigning the standard functions to the separate die and the user-defined functions to the single die of the base integrated circuit platform; d) for the user-defined functions, grouping the memory programmable functions for assignment to FPGA modules on the single die of the base integrated circuit platform; e) for the user-defined functions, synthesizing the non-memory programmable functions to the ASIC modules and the grouped memory programmable functions to the FPGA modules on the single die of the base integrated circuit platform; f) configuring the single die of the base integrated circuit platform by adding at least one metallization layer to configure the ASIC modules, and creating a configuration memory image to configure the FPGA modules; and g) packaging the separate die with the single die of the configured base integrated circuit platform to form a system-in-package.