Patent ID: 7010444
Filing Date: 2006-03-07
Classification: G01R,H04L

Abstract:
1. A pattern dependent jitter measuring apparatus comprising: a clock generating unit which generates a clock signal having a predetermined frequency; and a pattern generating unit which outputs to a measuring object a data signal, which has a predetermined pattern in which one frame is configured from a predetermined bit length, so as to be synchronized with the clock signal outputted from the clock signal generating unit; a waveform information acquiring unit which receives a data signal to be measured outputted from the measuring object as a data signal to be measured and receives the clock signal outputted from the clock generating unit, and which acquires waveform information in a same time domain of the data signal to be measured and the clock signal; an averaging processing unit which carries out averaging processing on the waveform information acquired by the waveform information acquiring unit; a phase difference detecting unit which determines a per-bit phase difference between the data signal to be measured and the clock signal, based on the waveform information averaged by the averaging processing unit; a frequency band limiting processing unit which carries out predetermined frequency band limiting processing on information of the per-bit phase difference obtained by the phase difference detecting unit; and a measured result outputting unit which outputs as pattern dependent jitter the phase difference information on which the frequency band limiting processing is carried out wherein the pattern generating unit is configured to output to the waveform information acquiring unit a frame synchronization signal synchronized with data output timing at an arbitrary bit position in one frame of the data signal; and wherein the waveform information acquiring unit is configured to acquire a predetermined number of frames of the waveform information of the data signal to be measured and the clock signal by using a timing when the frame synchronization signal is inputted as a standard timing.