Patent ID: 6709894
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A method for fabricating a semiconductor package, comprising the steps of:preparing a substrate plate having a plurality of arrayed substrates; mounting at least one first chip on each of the substrates of the substrate plate, wherein the first chip has an active surface and an inactive surface opposed to the active surface, allowing the inactive surface to be attached to the substrate; forming a plurality of first bonding wires for electrically connecting the active surfaces of the first chips respectively to the substrates; mounting on the substrate plate a shielding structure having a supporting portion adapted to abut against the substrate plate without affecting arrangement of the first chips and the first bonding wires, and a shielding portion attached to the supporting portion for being elevated by the supporting portion to a predetermined height that prevents the shielding portion from interfering with the first bonding wires, wherein the supporting portion is formed with a plurality of arrayed receiving holes for receiving the first chips and the first bonding wires, and the shielding portion is formed with a plurality of openings each connecting a corresponding one of the receiving holes, and wherein the shielding structure is dimensioned sufficiently in surface area to cover the first chips, and each of the openings of the shielding portion is smaller in dimension than each of the receiving holes of the supporting portion; applying an adhesive onto the active surface of each of the first chips via the openings of the shielding portion of the shielding structure in a batch manner, so as to form an adhesive layer on the active surface of each of the first chips; removing the shielding structure from the substrate plate, and stacking at least one second chip on the adhesive layer; electrically connecting the second chips to the substrate plate by wire bonding with a plurality of second bonding wires; and performing molding and singulating processes to form a plurality of individual semiconductor packages.