Patent ID: 6542541
Filing Date: 2003-04-01
Classification: H04N

Abstract:
A decoding system for decoding MPEG video data stream having a core processor and a co-processor with a variable length decoder (VLD), comprising of:a first memory storage device with at least two memory buffers coupled to the co-processor capable of storing at least two macroblock data of the MPEG video data stream; a second memory storage device with a plurality of memory buffers coupled to the core processor; a first data transfer unit coupled to the first memory storage device and the second memory device, wherein in response to a first signal from the core processor selecting one of the first memory storage device buffer (B0) as a source and a buffer from the plurality of buffers in the second memory storage device as a destination buffer (MB_B0â€²), wherein the data transfer unit is adapted to read content from B0 and write the content of B0 to MB_B0â€², and at the same time, also select the other buffer (B1) of the first memory storage device as a second source buffer and a second destination buffer (MB-B1â€²) from the plurality of buffers in the second memory storage device, adapted to read the content of B1 and write the content of B1 to MB_B1â€²; wherein the transfer from B1 to MB_B1â€² occurs after a wait indicating that a transfer from B0 to MB-B0â€² is complete.