Patent ID: 6069384
Filing Date: 2000-05-30
Classification: H01L

Abstract:
An integrated circuit comprising:a substrate wafer including a plurality of doped layers in a series of depths into the substrate wafer, the doped layers including a channel layer having a channel length defined in a vertical dimension, a shallow layer, and a deep layer, the channel layer being formed at a depth between the shallow layer and the deep layer, the deep layer being doped by a deep implant implanted through the channel layer into a deep portion of the channel layer, and the shallow layer being doped by a shallow implant implanted a shallow depth into a shallow portion of the channel layer;a trench etched into the substrate wafer, the trench extending through the doped layers at a plurality of depths and being bounded by vertical sidewalls and a planar horizontal floor;a conductive sidewall spacer adjacent to the vertical sidewalls of the trench so that an endpoint of the conductive sidewall spacer is substantially equal in height to the vertical sidewalls of the trench and wherein the conductive sidewall spacer is operational as a gate electrode of the integrated circuit; anda first lightly-doped drain (LDD) doped into the substrate beneath the trench, the first LDD being implanted into the substrate at an angle toward the conductive sidewall spacer and self-aligned with the conductive sidewall spacer so that the first LDD is positioned beneath the conductive sidewall spacer extending approximately to a vertical plane of the vertical sidewall.