Patent ID: 6816410
Filing Date: 2004-11-09
Classification: B82Y,G11C,H01L

Abstract:
In a multi-level memory array comprising a plurality of conductors on each level of the memory array, forming a memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality in common with cells of at least one adjacent level, a method of writing a selected memory cell comprising the steps of:biasing a first conductor coupled to an anode terminal of the selected memory cell to a first voltage; biasing a second conductor coupled to a cathode terminal of the selected memory cell to a second voltage lower than the first voltage; biasing at least one of a group of unselected conductors on the same level as the first conductor to a third voltage between the first and second voltages and at an offset from the second voltage; and biasing at least one of a group of unselected conductors on the same level as the second conductor to a fourth voltage between the first and second voltages and at an offset from the first voltage.