Patent ID: 6489204
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A process for manufacturing a vertical power MOSFET, comprising:(a) providing a silicon wafer having an N+ bottom layer, an N type middle layer, and a P body top layer having an upper surface; (b) on said P body top layer, forming a layer of pad oxide and depositing thereon a layer of silicon nitride; (c) patterning the silicon nitride and pad oxide layers to form a mask that defines a trench, having a floor and sidewalls, and then etching said trench to a depth sufficient to extend into said N type middle layer; (d) forming a first layer of silicon oxide on said floor and sidewalls; (e) overfilling the trench with polysilicon and then etching back the polysilicon until said polysilicon under-fills the trench; (f) removing from the sidewalls all exposed silicon oxide; (g) forming a second layer of silicon oxide on the polysilicon exposed sidewalls, whereby all polysilicon in the trench is now encapsulated in a layer of silicon oxide; (h) through ion implantation by an ion beam, forming an N+ source area, part of which overlaps and abuts said polysilicon encapsulating oxide layer then removing said layer of silicon nitride; (i) depositing a conformal layer of a dielectric material and then selectively removing all dielectric material on horizontal surfaces whereby insulating spacers on the walls of the trench are formed; (j) implanting acceptor ions to form a P+ region that abuts said N+ source area; and (k) forming a silicide contact to the polysilicon and a single silide contact to both the N+ source area and to said P+ region that is abutted thereto.