Patent ID: 9214207
Filing Date: 2015-12-15
Classification: G06F,G11C

Abstract:
1. A data decoding apparatus comprising: at least one processor block; at least one hardware block; and a memory processor to control the at least one processor block or the at least one hardware block to access a memory to read from the memory and to write data to the memory, wherein the memory processor monitors a current data transmission state of the at least one processor block and the at least one hardware block, and wherein the memory processor comprises: an arbitrator to select a block for reading the data from the at least one processor block or the at least one hardware block based upon the current data transmission state of the at least one processor block and the at least one hardware block and to select a block for writing the data from the at least one processor block or the at least one hardware block based upon the current data transmission state of the at least one processor block and the at least one hardware block, and to set an optimum order of decoding efficiency among the at least one processor block and the at least one hardware block based upon the current data transmission state of the at least one processor block and the at least one hardware block; a memory controller to transmit data of the selected at least one processor block or data of the selected at least one hardware block to an internal buffer and to store tiled data to be read by the selected processor block or hardware block, in an internal buffer or a cache; a tilor to tile the data of the selected at least one processor block or the data of the selected at least one hardware block such that a number of data pieces transmitted from the at least one processor block or the at least one hardware block to the memory is maximized; and an untilor to untile the tiled data such that a number of data pieces transmitted to the at least one processor block or the at least one hardware block is maximized, and wherein the memory controller stores the tiled data in the memory and transmits the untiled data to the selected processor block or hardware block.