Patent ID: 6803315
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of forming an FET device on a doped semiconductor substrate on which a gate electrode stack comprising a gate dielectric and a gate electrode with a top surface have been formed comprising:forming a gate electrode stack on the substrate comprising a thin gate dielectric layer and a gate electrode layer; depositing a first planarizing film blanketing the substrate and the gate electrode stack; planarizing the first planarizing film to form an upper surface of the first planarizing layer thereby exposing the gate electrode; etching back an upper portion of the gate electrode below the level of the upper surface of the first planarizing film; depositing a second planarizing film blanketing the top of the gate electrode and the first planarizing film; planarizing the second planarizing film to expose the first planarizing film while forming a second planarizing film cap covering the top surface of the gate electrode; selectively removing the first planarizing film, thereby opening access for implantation into lateral regions in the surface of the substrate aside from the gate electrode stack whereby the counterdoped regions can be formed; and forming the counterdoped regions by implanting dopant into the substrate using the second planarizing film block to block layer the dopant from implantation into the gate electrode; whereby the second planarizing film cap protects the gate electrode of the FET device from unwanted implanted impurities during implanting of the counterdoped regions.