Patent ID: 6011716
Filing Date: 2000-01-04
Classification: G11C

Abstract:
For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising:settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, andreading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell,wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, andwherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first progranmming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.