Patent ID: 6091278
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A device for processing sampled analog current signals in a digital BiCMOS process using a plurality of NMOS transistors and a plurality of NPN bipolar transistors in the BiCMOS process, comprising:means for generating a voltage corresponding to an input current and temporarily storing the voltage at a gate of a first one of the plurality of NMOS transistors;means for boosting a speed of the device while a transconductance of at least one of the plurality of NPN bipolar transistors is used, wherein;the first one of the plurality of NMOS transistors is provided in a common-drain configuration and a first one of the plurality of NPN bipolar transistors is provided in a common-emitter configuration, and both are used and connected as an input device;a second one of the plurality of NMOS transistors is provided in a common-drain configuration and a second one of the plurality of NPN bipolar transistors is provided in a common-emitter configuration, and both are used and connected as an output device;and the input and output devices are connected together only on one clock phase controlled by a non-overlapping clock.