Patent ID: 6297699
Filing Date: 2001-10-02
Classification: H03F

Abstract:
A bias rail buffer circuit for providing a reference signal, said bias rail buffer circuit comprising:an input reference and an output reference;an input transistor, a collector of which is connected to said input reference and an emitter of which is connected through a biasing resistor to a first voltage supply rail;a first pair of complementary transistors comprising a first transistor and a second transistor, each of said first transistor and said second transistor having an emitter connected to a base of said input transistor, said first transistor having a base connected to said input reference, and said second transistor having a base and a collector connected together; anda second pair of complementary transistors comprising a third transistor and a fourth transistor, each of said third transistor and said fourth transistor having an emitter connected to an output reference, said third transistor having a base connected to said input reference, and said fourth transistor having a base connected to a base of said second transistor; andwherein said bias rail buffer circuit is configured to source current to and to sink current from the output reference to absorb external disturbances imparted onto said output reference to provide a stable reference signal.