Patent ID: 8756469
Filing Date: 2014-06-17
Classification: G01R,G06F,G11C,H04B,H04L

Abstract:
1. An integrated circuit, comprising: circuitry to generate a repeating pattern signal during a test mode; and circuitry to serially transmit a signal to a receiver, the signal comprising a data signal during a normal mode and the repeating pattern signal during the test mode, where the circuitry is to serially transmit the repeating pattern signal to the receiver during the test mode using alternate values of at least one transmission parameter affecting proper reception of the repeating pattern signal by the receiver; and where the integrated circuit is during the normal mode to apply an operating value for the at least one parameter to transmit the data signal, the operating value selected in dependence on the evaluation of the repeating pattern signal serially transmitted during the test mode as received by the receiver.