Patent ID: 6076149
Filing Date: 2000-06-13
Classification: G06F

Abstract:
A data processing device, comprising:a main memory comprising a non-volatile memory for storing data;an auxiliary memory comprising a programmable ROM for storing bit data to control a read from and a write to the main memory, wherein the bit data corresponds to a high or low level of each gate threshold voltage in conductive state of transistors, the transistors comprising memory cells of the programmable ROM, and having their gates connected to a voltage application signal line, wherein the bit data read being ""0"" when a current flows between the drain and source of the transistor, and ""1"" when the current does not flow; anda processing portion for executing a read from and a write to the main memory and the auxiliary memory,wherein the processing portion is implemented to perform in accordance with a combination of bit data read from the auxiliary memory the following:(a) if each of the bit data is all ""0"", a write to the auxiliary memory is permitted, while an external write to and read from the main memory is prohibited;(b) if each of the bit data is all ""1"", a write to the auxiliary memory is prohibited, while an external write to and read from the main memory is prohibited; and(c) for at least one combination of bit data having ""1"" and ""0"", a write to the auxiliary memory is permitted, while an external write to and read from the main memory is also permitted.