Patent ID: 8508250
Filing Date: 2013-08-13
Classification: H03K

Abstract:
1. An asymmetrical bus keeper circuit comprising: a first inverter stage having an input node and an output node; an asymmetrical inverter stage having an input node and an output node; the input node of the asymmetrical inverter stage being connected to the output node of the first inverter stage; and a feedback stage with an input node and an output node, the input node of the feedback stage being connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage being connected to the input node of the first inverter stage, wherein the asymmetrical stage provides an asymmetrical drive towards one logic level and wherein the asymmetrical inverter stage comprises a single transistor when implemented using CMOS transistors or a single half of an output totem pole structure when implemented using BJT transistors.