Patent ID: 6798263
Filing Date: 2004-09-28
Classification: H03K

Abstract:
A differential latch circuit comprising:a positive output voltage (Voutp) node for a positive component of a differential latch output, said Voutp node being connected to a reference voltage through a first resistance; a negative output voltage (Voutn) node for a negative component of said differential latch output, said Voutn node being connected to said reference voltage through a second resistance; a first bias current source configured to generate a first bias current; a first transistor having a first drain node connected to said reference voltage, a first gate node connected to said reference voltage through a third resistance, and a first source node connected to said first bias current source; a second transistor having a second drain node connected to said Voutp node, a second gate node for a positive component of a differential reset signal, and a second source node; a third transistor having a third drain node connected to said first gate node, a third gate node for a negative component of said differential reset signal, and a third source node connected to said second source node; and a second bias current source connected to said second source node and to said third source node, said second bias current source being configured to generate a second bias current.