Patent ID: 7809783
Filing Date: 2010-10-05
Classification: G06F

Abstract:
1. A method for performing Booth multiplication in a digital signal processor, the method comprising: determining, by the digital signal processor, a multiplicand, A, comprising a first plurality of bits and a multiplier, B, comprising a second plurality of bits; performing, by the digital signal processor, radix-m Booth recoding on B to generate a first predetermined number, n, of multiplication factors, the n multiplication factors approximating one half of the number of the second plurality of bits; generating, by the digital signal processor, n partial products using the n multiplication factors as multipliers of A; in the event of a negative multiplication factor, forming, by the digital signal processor, a two's complement of A by inverting the first plurality of bits of A and associating a sticky “1” to complete the two's complementation; and reducing, by the digital signal processor, the partial products in multiple stages of reduction to a set of sum and carry components of a pre-determined length; and generating, based on the set of sum and carry components, by the digital signal processor, a product of A and B.