Patent ID: 6963953
Filing Date: 2005-11-08
Classification: G06F

Abstract:
1. A cache device comprising at least first and second cache controllers each for controlling respective first and second cache memories, said first and second cache memories each provided to respective first and second processors sharing a shared memory with each other, said first and second cache controllers each connected to the shared memory via a bus, said first and second cache memories each comprising a plurality of data regions for temporarily storing information including data read from said shared memory by designating an address and said address designated, wherein said shared memory includes a first space to which at least one predetermined address space of said first processor is pre-assigned and which is for storing data to be accessed most frequently by said first processor, and a second space to which at least one predetermined address space of said second processor is pre-assigned and which is for storing data to be accessed most frequently by said second processor; said first and second cache controllers perform mutual input and output via said bus; when said first cache controller detects that data designated by an address belonging to said predetermined address space of said first processor in said first cache memory is updated, said first cache controller outputs an invalidation request including said address for designating data corresponding to said updated data to said second cache controller via said bus if said data corresponding to said updated data is stored in said second cache memory; and when said second cache controller receives said invalidation request from said first cache controller via said bus, said second cache controller invalidates said data corresponding to said updated data in said second cache memory based on said address in said received invalidation request.