Patent ID: 8473887
Filing Date: 2013-06-25
Classification: G06F

Abstract:
1. A method for accounting for one or more hold time violations of an electrical circuit design, the method comprising: utilizing at least one processing device to perform the following operations: analyzing an electrical circuit design to determine one or more hold time violations; associating a criticality to one or more nodes of the electrical circuit design, the criticality relating to a number of hold time violations determined at the one or more nodes; storing indicators of the one or more nodes and the associated criticality of the one or more nodes in a data set in at least one memory device; generating a change event queue to account for the one or more hold time violations based on the associated criticality of the one or more nodes in the data set; and altering the electrical circuit design based on the change event queue to account for the one or more hold time violations of the electrical circuit design.