Patent ID: 6332187
Filing Date: 2001-12-18
Classification: G06F

Abstract:
A processor comprising:a storage location coupled to a circuit, wherein the storage location is configured to store a cumulative offset indicating a cumulative modification of a first value, wherein the first value is stored into a first register in response to a first non-accelerated operation corresponding to a first prior instruction, and wherein the cumulative modification is due to each instruction between the first prior instruction and a second prior instruction, the second prior instruction processed by the circuit in a first clock cycle; andthe circuit coupled to receive a first instruction in a second clock cycle subsequent to the first clock cycle, wherein the circuit is configured to update the cumulative offset to reflect a modification due to the first instruction if the first instruction includes a first accelerated operation to the first register, and wherein the circuit is configured to update the cumulative offset to an initial value if the first instruction includes a second non-accelerated operation to the first register, wherein the initial value is independent of instructions executed by the processor.