Patent ID: 7444611
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. An automatic designing method for a semiconductor device, which automatically performs processing for equalizing spacing wirings formed in a semiconductor integrated circuit, said method comprising: an area extracting step for extracting an equalized area from layout data of the semiconductor integrated circuit; a wiring extracting step for extracting the wirings from the equalized area extracted in the area extracting step; an equalizing step for extracting line segments extending in a longitudinal direction of the equalized area from the wirings extracted in the wiring extracting step and shifting the extracted line segments to thereby equalize spacing between these line segments; and an expanding/contracting step for extracting other line segments from the wirings extracted in the wiring extracting step and expanding/contracting the extracted line segments to thereby restore states of connections of other line segments to the longitudinally-extending line segments.