Patent ID: 6165841
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method for fabricating a semiconductor device including a lower electrode layer provided at a surface thereof with hemispherical grains, an upper electrode layer, and a dielectric layer interposed between the lower and upper electrode layers, comprising:dry etching a doped amorphous silicon layer by use of a lower electrode layer pattern;processing an exposed surface of the etched amorphous silicon layer using fluorine (F), thereby transforming molecular bonds existing on the exposed surface of the amorphous silicon layer into Si--F bonds while suppressing a growth of oxide films on the exposed surface of the amorphous silicon layer;processing the exposed surface of the amorphous silicon layer using hydrogen, thereby transforming the Si--F bonds on the exposed surface of the amorphous silicon layer into Si--H bonds; anddesorbing hydrogen from the exposed surface of the amorphous silicon layer, and growing hemispherical grains over the desorbed surface of the amorphous silicon layer, thereby forming the lower electrode layer.