Patent ID: 6489203
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A process for manufacturing an LDMOSFET, comprising:providing a P+ silicon substrate and depositing thereon an epitaxial layer of Pâˆ’ silicon having an upper surface; forming a P+ sinker region that extends downwards from said upper surface through the Pâˆ’ epitaxial layer into the P+ substrate, by means of ion implantation through a mask, followed by a drive-in diffusion; growing a layer of gate oxide on said upper surface and then depositing thereon a layer of phosphorus doped polysilicon; patterning and etching said polysilicon layer to form a gate pedestal and then removing all gate oxide not under said gate pedestal; by means of double diffusion through a mask, forming an N+ source region on a first side of said gate pedestal and a Pâˆ’ body under the gate and extending into said source region; by ion implantation through a mask, forming a drain region on an opposing second side of the gate there being a separation region between the gate and the drain region; in said separation region, forming, by ion implantation through an LDD mask, a first N type LDD layer that extends downward from said upper surface to a first interface; in said separation region, forming, by ion implantation through said LDD mask, a P type LDD layer that extends downward from said first interface to a second interface; and in said separation region, forming, by ion implantation through said LDD mask, a second N type LDD layer that extends downward from said second interface to a third interface.