Patent ID: 6519411
Filing Date: 2003-02-11
Classification: G11B,H04N

Abstract:
A digital signal processing apparatus for inputting a digital signal in the form of a plurality of packets each having a predetermined number of bytes and a first time stamp added to each packet for indicating a time of transmission of the packet, and for outputting a digital signal in the form of a plurality of packets each having a predetermined number of bytes and a second time stamp added to each packet, the second time stamp having a different format than the first time stamp, the digital signal processing apparatus comprising:an oscillator generating a clock constituting a reference for operation of the digital signal processing apparatus; a time stamp generator generating a reference time based on the clock generated by the oscillator, the reference time having a same format as the first time stamp added to each packet of the inputted digital signal; a comparator comparing the first time stamp added to each packet of the inputted digital signal with the reference time generated by the time stamp generator; a time stamp converter converting the first time stamp added to each packet of the inputted digital signal into the second time stamp having a different format than the first time stamp; and an output circuit outputting the outputted digital signal in the form of a plurality of packets each having a predetermined number of bytes and the second time stamp converted by the time stamp converter added to each packet when the first time stamp of each packet of the inputted digital signal coincides with the reference time generated by the time stamp generator.