Patent ID: 7550362
Filing Date: 2009-06-23
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate defining an active region and a peripheral region, the substrate having an insulating layer and a lower electrode contact plug provided in the active region, the lower electrode contact plug being defined within the insulating layer; forming a first alignment mark in the peripheral region; forming an amorphous carbon layer over the insulating layer and the lower electrode contact plug in the active region and the first alignment mark in the peripheral region; forming a polysilicon layer over the amorphous carbon layer in the active region and the peripheral region, the polysilicon layer having first and second portions, the first portion being associated with the active region and the second portion being associated with the peripheral region, the second portion defining a second alignment mark corresponding to the first alignment mark; forming a mask pattern over the first portion of the polysilicon layer to define a storage electrode region that is aligned to the lower electrode contact plug; etching the first portion of the polysilicon layer and the amorphous carbon layer using the mask pattern to form a trench over the lower electrode contact plug; forming a lower electrode material within the trench and over the lower electrode contact plug; etching an upper portion of the lower electrode material to form a lower electrode of a capacitor; and removing the amorphous carbon layer in the active region, wherein the lower electrode of the capacitor is in contact with the lower electrode contact plug.