Patent ID: 6246074
Filing Date: 2001-06-12
Classification: G01R,G02F,G09G

Abstract:
A thin film transistor matrix substrate having thin film transistors connected to gate lines and data lines forming a matrix, the thin film transistor matrix substrate comprising:a first shorting bar connected to the gate lines;a second shorting bar connected to the data lines;a first test pad connected to the first shorting bar and responsive to a first test signal;a second test pad connected to the second shorting bar and responsive to the first test signal;a first set of discharge circuits connected to the gate lines;a second set of discharge circuits connected to the data lines;a third shorting bar connected to the first set of discharge circuits coupled to the gate lines;a fourth shorting bar connected to the second set of discharge circuits coupled to the data lines; andcharge preventing means for preventing a voltage from being charged into the third and fourth shorting bars while testing the gate lines and the data lines for breaks.