Patent ID: 6714051
Filing Date: 2004-03-30
Classification: G06F,Y02D

Abstract:
A bus buffer having logic circuitry comprising:a controller, provided between a plurality of two-way data buses through which at least one data signal is transferred, to generate a plurality of different control signals based on an input/output command signal instructing input/output of the data signal and a direction-indicating signal indicating a direction in which the data signal is to be transferred; a first terminal via which a first-directional signal to be transferred from a first bus side to a second bus side is input whereas a second-directional signal to be transferred from the second bus side to the first bus side is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first input buffer, a first internal circuit and a first output buffer; and a second-directional signal processor, provided between the second and first terminals, having a second input buffer, a second internal circuit and a second output buffer, wherein the first input buffer has a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals in accordance with states of the input/output command signal and the direction-indicating signal, and the second input buffer has a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal in accordance with the states.