Patent ID: 8647976
Filing Date: 2014-02-11
Classification: G01R,H01L

Abstract:
1. A method of testing a semiconductor package, wherein the semiconductor package comprises a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising first test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and second test pads disposed on the bottom surface of the substrate, wherein each of the second test pads attaches a solder ball such that a combination of the second test pads and attached solder ball has a second height above the bottom surface which is greater than the first height, wherein the first test pads on the bottom surface of the substrate are classified into a plurality of sub-groups, and wherein the second test pads are disposed on the bottom surface of the substrate in an evenly spaced array except that at least one of the second test pads in the array is replaced by the sub-groups of the first test pads; wherein the method comprises: loading the semiconductor package into a tester; and performing electrical/functional testing of the semiconductor package using a test connector simultaneously connecting to the plurality of test pads.