Patent ID: 8990062
Filing Date: 2015-03-24
Classification: G06F,G06Q

Abstract:
1. A method for evaluating a probability of memory access conflict of different bus masters while a program expressed in a simulation model is in operation, in a heterogeneous system in which the different bus masters include a processor, an accelerator, and a controller that can access a memory, the method comprising the steps of: measuring, for the simulation model, an execution time and a number of memory accesses for each simulation step for each of the different bus masters of the heterogeneous system or preparing measurement values in advance; determining a processor utilization factor for each of the different bus masters of the heterogeneous system; calculating a utilization factor of a memory bandwidth for each of the different bus masters of the heterogeneous system using the execution time and the number of memory accesses; and calculating the probability of memory access conflict among the different bus masters of the heterogeneous system using a formula including the processor utilization factor and the product of the utilization factors of the memory bandwidths of the different bus masters; wherein a UML-based model simulation is used to calculate the utilization factor of the memory bandwidth and the processor utilization factor.