Patent ID: 9064598
Filing Date: 2015-06-23
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array comprising a plurality of NAND strings arranged therein, each NAND string comprising a memory string comprising a plurality of memory cells connected in series, and a dummy transistor connected to at least one of two ends of the memory string; a plurality of word lines connected to respective control gate electrodes of the memory cells; a dummy word line connected to a control gate electrode of the dummy transistor; a plurality of bit lines connected to respective first ends of the NAND strings; a source line connected to second ends of the NAND strings; and a control circuit performing an erase sequence, the erase sequence repeating an erase operation to the memory cells and the dummy transistor and an erase verify operation of confirming whether the memory cells and the dummy transistor are changed to an erased state, the control circuit being configured to be able to perform, when the erase verify operation is unpassed, a dummy transistor erase operation of selectively changing the dummy transistor to the erased state and a dummy transistor erase verify operation of confirming whether the dummy transistor is changed to the erased state.