Patent ID: 6424185
Filing Date: 2002-07-23
Classification: H03L,H04N

Abstract:
A circuit comprising;a processor receiving a local timing signal and an input signal having embedded therein a program timing signal, and providing a first numerical signal representing a time difference between a time represented in said local timing signal and a time represented in said program timing signal; a numerically controlled oscillator comprising an accumulator comprising: a first input line receiving said first numerical signal; a second input line providing a second numerical signal representing a second numerical value at said first time; and an output line coupled to said second input line, wherein said accumulator is configured to add said first and second numerical values and output a resulting signal representing a resulting value on said output line; and a phase-locked loop circuit coupled to said output line, said phase-locked loop including a low-pass filter capable of attenuating a jitter in said numerically controlled oscillator resulting from said first numerical signal.