Patent ID: 7501677
Filing Date: 2009-03-10
Classification: G11C,H01L

Abstract:
1. A method of operating a SONOS memory cell formed on a semiconductor substrate, comprising: applying a respective bit-line gate bias on at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate, wherein the inversion bit-line forms one of drain and source regions of the SONOS memory cell; applying a respective bias voltage on the inversion bit-line for affecting an amount of charge stored within a charge trapping material disposed between a bottom dielectric and a top dielectric during a program/erase of the SONOS memory cell; and applying respective bias voltages on a word-line structure, a substrate, and the other of the drain and source regions of the SONOS memory cell during the program/erase of the SONOS memory cell, wherein the bottom dielectric, the charge trapping material, and the top dielectric are stacked over the word-line structure formed in a region of the semiconductor substrate between the drain and source regions.