Patent ID: 8107580
Filing Date: 2012-01-31
Classification: G11C,H03D,H03K,H03L

Abstract:
1. A phase detector comprising: a first input configured to receive a first clock signal; a second input configured to receive a second clock signal; and a charge pump comprising an output terminal, a first current source, and a second current source, and wherein the charge pump is configured to cause the first and second current sources to bypass the output terminal responsive to the first and second clock signals being substantially in phase, wherein the charge pump comprises a first switching device and a second switching device coupled in series between the first current source and the output terminal, and wherein one of the first and second switching devices is configured to substantially prevent current flow between the first current source and the output terminal responsive to the first and second clock signals being in phase, and wherein the charge pump comprises a third switching device and a fourth switching device coupled in series between the second current source and the output terminal, and wherein one of the third and fourth switching devices is configured to substantially prevent current flow between the second current source and the output terminal responsive to the first and second clock signals being in phase.