Patent ID: 6700148
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A DRAM cell capacitor comprising:a stacked storage node formed on an interlayer insulating layer and electrically connected to a semiconductor substrate through a buried contact plug in the interlayer insulating layer, the stacked storage node defining substantially vertical common sidewalls and a top portion; a dielectric film formed on the stacked storage node; and a plate node formed on the dielectric film; wherein the stacked storage node comprises: a bottom storage node formed on the interlayer insulating layer and a top storage node formed on the bottom storage node, sidewalls of the bottom and top storage nodes defining the common vertical sidewalls of the stacked storage node, the sidewalls of the bottom and top storage nodes being vertically aligned with one another, and a top portion of the top storage node defining the top portion of the stacked storage node, wherein HSG silicon is formed only on the sidewalk and the top portion of the top storage node.