Patent ID: 6816203
Filing Date: 2004-11-09
Classification: H04N

Abstract:
A television signal processing apparatus (100), comprising:a digital bus (104/105); a controller assembly including a processor (101), coupled to the digital bus, for outputting clock signals and first data signals and receiving second data signals over the digital bus (104/105); a front end assembly including a tuner module having a noise intolerant device coupled to a down converter, and a data storage device (112); and a bi-directional buffer (109) coupled between the digital bus (104/105) and the tuner module, wherein, in a first mode of operation the bi-directional buffer (109) isolates the tuner module from the processor, and in a second mode of operation passes the clock signals and the first data signals from the processor to the tuner module and also passes the second data signals from the tuner module to the processor.