Patent ID: 6253276
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A memory controller, comprising:a decoding circuit for decoding a current address received from a processor to produce physical characteristics of a current hardware memory module that is being accessed by the current address, wherein the current address specifies a location within a hardware memory module of either an instruction reference or a data reference;wherein the physical characteristics include a size of the current memory module;a control signal generation circuit, coupled to the decoding circuit, for generating control signals for controlling a memory access to the current address based upon the physical characteristics of the current hardware memory module, including the size of the current memory module;wherein the control signals include a chip select signal for enabling at least one memory chip, and row and column strobes to select a location within a memory chip;a module determining circuit that is configured to determine which hardware memory module the current address falls within;a comparison module for determining which hardware module the current address falls within and whether the current address falls within a previously accessed hardware memory module; anda bypassing circuit, coupled to the decoding circuit and the comparison module, that causes physical characteristics of a previously accessed hardware memory module, obtained from a prior decoding of a previous address, to be used to generate the control signals, if the comparison module indicates that the current address falls within the previously accessed hardware memory module.