Patent ID: 9203395
Filing Date: 2015-12-01
Classification: G09G,H03K

Abstract:
1. A gate driver, comprising a plurality of stages connected to each other, wherein an n-th (n is a natural number) stage among the plurality of stages includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal in response to a signal of a first node; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage in response to an (n+1)-th carry signal; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage in response to a carry signal from at least one stage among stages next to the n-th stage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal in response to the signal of the first node; an inverter unit configured to output a signal in synchronization with the clock signal to a second node in a period other than a period in which the n-th carry signal is output; a first node storage unit configured to maintain the voltage of the first node at the second low voltage in response to the signal of the second node; and a second node storage unit configured to maintain the voltage of the second node at the first low voltage or the second low voltage in response to the signal of the first node, wherein a control terminal of the second node storage unit is directly connected to the first node, and an input terminal of the second node storage unit is connected to the second node.