Patent ID: 8350369
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. A high power semiconductor package comprising: an insulation substrate having first and second surfaces opposite to each other; interconnection patterns formed on the first surface of the insulation substrate, the interconnection patterns including a plurality of first dimples, the plurality of first dimples being separated from each other at predetermined intervals and the plurality of first dimples not being connected between each other and terminating above the second surface of the insulation substrate, and being indentations of the interconnection patterns, said dimples reducing a thermal induced shear stress acting on the interface between the interconnection patterns and the insulation substrate; a power control semiconductor chip mounted on one of the interconnection patterns the power control semiconductor chip electrically connected with the interconnection patterns; and an encapsulation member encapsulating the insulation substrate, the interconnection patterns, and the power control semiconductor chip and exposing at least a portion of the second surface of the insulation substrate.