Patent ID: 6844630
Filing Date: 2005-01-18
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device, comprising: first and second I/O slots arranged on the same wiring level in parallel along a peripheral portion of a chip within an inner region of the chip; a first pad arranged on a wiring level different from said first I/O slot and arranged above the first I/O slot without being connected to the first I/O slot; a second pad arranged on a wiring level different from said first I/O slot and arranged apart from the peripheral portion of the chip as compared with the first pad; a first wiring comprising one end positioned in said first pad and comprising the other end positioned at the peripheral portion of the inner region of the chip above the first I/O slot; a second wiring comprising one end positioned in the second pad and comprising the other end positioned in the peripheral portion of the inner region of the chip above the second I/O slot; and a third wiring arranged in an outermost peripheral region of the chip and serving to connect the other end of the first wiring to an I/O slot different from the first I/O slot.