Patent ID: 6131108
Filing Date: 2000-10-10
Classification: G06F

Abstract:
In synthesized logic apparatus used in data processing, an improvement of circuitry for generating at least a first multi-bit output sequence of a first selected number of bits responsive to an input sequence of a second selected number of bits, the first selected number of bits comprise a multiple of the second selected number of bits, said circuitry comprising:an arithmetic logic unit coupled to receive (i) the input sequence comprising a first iteration and a second iteration and (ii) a data sequence, the data sequence also of the second selected number of bits, said arithmetic logic unit for adding the first iteration of the input sequence together with the data sequence to form a first summed value and a first carry-forward value and thereafter at least for adding the second iteration of the input sequence at least with the first carry-forward value to form a second summed value, the first summed value concatenated to the second summed value to form the first multi-bit output sequence.