Patent ID: 6075727
Filing Date: 2000-06-13
Classification: G11C

Abstract:
An integrated circuit, comprising:a memory array having a plurality of rows, the plurality of rows having a plurality of memory cells;a write latch unit coupled to the memory array, the write latch storing data to be written into the memory array;a comparator coupled to the memory array and to the write latch unit, the comparator comparing data stored in a first row of the plurality of rows to data stored in the write latch unit and in response providing a verify erase signal and a verify program signal;a memory controller coupled to the memory array and the write latch unit, the memory controller initiating application of a programming voltage to a wordline coupled to the first row when the verify program signal is at a first value, the memory controller initiating application of an erase voltage to the wordline coupled to the first row when the verify erase signal is at a second value.