Patent ID: 6266222
Filing Date: 2001-07-24
Classification: H01L

Abstract:
An ESD protection network for a CMOS circuit structure integrated in a semiconductor substrate and comprising discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground, the ESD protection network comprising:a first ESD protection element for an input stage of the circuit structure;a second ESD protection element for an output stage of the circuit structure, said first and second protection elements having in common an input/output terminal of the circuit structure;a third ESD protection element between the primary voltage supply and the primary ground; anda fourth ESD protection element between the secondary voltage supply and the secondary ground, wherein said second protection element is a bipolar transistor fully isolated from the substrate by a first isolation structure that includes a first buried well in the substrate and first and second side wells extending down from a surface of the substrate to contact opposite ends of the buried well, the substrate having a first conductivity type and the buried well and side wells being doped to have a second conductivity type, wherein said second protection element is a lateral npn bipolar transistor having a base region, a collector region and an emitter region, with the collector region being connected to said input/output terminal and the base and emitter regions being biased to the secondary ground.