Patent ID: 8547384
Filing Date: 2013-10-01
Classification: G06T,G09G,G11C,H04N

Abstract:
1. A checkerboard buffer, comprising: a data source, providing data in pairs in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch coupled to the data source and each of the memory devices, where the first data switch controls which data of the pairs is stored to which memory device, wherein the first data switch is configured to swap which data of the pairs is stored in which of the memory devices; and a second data switch coupled to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.