Patent ID: 8965945
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. Apparatus for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each having a significand and an exponent, said apparatus comprising: prediction circuitry configured to generate a shift indication based on a prediction of the number of leading zeros that would be present in an output produced by subjecting the operands A and B to an unlike signed addition; result pre-normalization circuitry configured to perform a shift operation on the significands of both operand A and operand B prior to addition of the significands, the shift operation serving to discard a number of most significant bits of the significands of both operand A and operand B as determined by the shift indication in order to produce modified significands for operands A and B; operand analysis circuitry configured to detect, with reference to the exponents of operands A and B, the presence of a leading bit cancellation condition; and addition circuitry configured, in the presence of said leading bit cancellation condition, to perform an addition of the modified significands for operands A and B, in order to produce the significand of the result R; the addition circuitry being configured, in the absence of said leading bit cancellation condition, to perform an addition of the significands for operands A and B without using the modified significands produced by the result pre-normalization circuitry, in order to produce the significand of the result R; wherein: said operand B is the result of a multiply operation performed on two floating point operands, and is supplied unrounded as an input to the apparatus such that the result R represents the result of a fused multiply-accumulate operation; the significand of the result R has N bits and the significand of the operand B has greater than N bits due to being supplied unrounded; the addition circuitry is configured to perform injection rounding to add a rounding increment value during the addition; the operation of the result pre-normalization circuitry prior to the addition circuitry ensures that the modified significands of operands A and B are correctly aligned for the injection rounding; and the addition circuitry comprises first addition circuitry configured to perform the addition using a first rounding increment value assuming no overflow condition is present and second addition circuitry configured to perform the addition using a second rounding increment value assuming an overflow condition is present.