Patent ID: 7248266
Filing Date: 2007-07-24
Classification: G06T

Abstract:
1. A processing engine, comprising: a processing core for receiving an incoming data stream and converting it to output information in a predetermined format for transfer to an output device, said processing core operable to access memory locations with multiple memory access requests for a Read or a Write operation and operable in a first address space; a plurality of memory blocks, each individually accessible and all of said plurality of memory blocks configured in a virtual address space different than said first address space; a memory mapping device for mapping each of said memory requests to the virtual address space; and a pipeline engine for pipelining said mapped memory access requests for both Read and Write operations in accordance with a predetermined pipelining scheme, said memory access requests received in parallel and processed asynchronously, such that access to more than one of said memory blocks can occur at substantially the same time.