Patent ID: 6738868
Filing Date: 2004-05-18
Classification: G06F

Abstract:
A multiprocessor computer system comprising a plurality of nodes,each node including: an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory, said directory configured to store sharing information concerning a memory line of information stored in the local memory subsystem; a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node; a protocol engine implementing a negative acknowledgment free cache coherence protocol, the protocol engine including a memory transaction array for storing an entry related to a memory transaction, the entry including a memory transaction state, the memory transaction concerning a memory line of information; logic for processing the memory transaction, including advancing the memory transaction when predefined criteria are satisfied and storing a state of the memory transaction in the memory transaction array; a first subset of nodes comprising one or more nodes from said plurality of nodes, each node in said first subset including an interface to one or more I/O devices; the protocol engine included in each node from said first subset of nodes is configured to limit to a predefined period of time, any sharing of a memory line of information stored in the remote memory subsystem that is local to a home node from said plurality of nodes; and the protocol engine included in the home node is configured to identify only nodes other than nodes in the first subset that are sharing the memory line of information.