Patent ID: 6697992
Filing Date: 2004-02-24
Classification: G06F,G11C

Abstract:
A semiconductor integrated circuit device comprising:a memory circuit including dynamic memory cells which have a storage capacitor and an address selection MOSFET, and having an information retaining mode during which data is not read from or written to other circuits; and a data retention control circuit, said data retention control circuit including an ECC circuit and a refresh cycle setting circuit, wherein said ECC circuit is activated when said memory circuit enters said information retaining mode from a normal operation mode, in which data is read from or written to other circuits, to perform a first operation of reading plural data stored in said memory circuit and generating and storing a check bit for error detection and correction, and is activated when said memory circuit returns from said information retaining mode to said normal operation mode to perform a second operation of reading the plural data and the stored check bit, correcting an error bit in the data, and writing corrected data into a corresponding memory cell, wherein said refresh cycle setting circuit is controlled to perform a refresh operation in every refresh cycle in said information retaining mode, and wherein information indicative of said refresh cycle is held in a non-volatile manner, and wherein in at least one refresh cycle of said refresh operation in said information retaining mode, memory cells are refreshed but an operation of error detection and correction is not performed.