Patent ID: 6472911
Filing Date: 2002-10-29
Classification: H03K

Abstract:
An output buffer circuit of a semiconductor integrated circuit comprising:a main driver having a first transistor that increases and decreases current flowing between a signal output terminal and a first power supply line inversely depending on a first control potential, and a second transistor that increases and decreases current flowing between said signal output terminal and a second power supply line depending on a second control potential; and a predriver that generates said first control potential and said second control potential by employing an input logic signal, and that reduces a speed of increase of the current flowing through said first transistor or said second transistor by prolonging a fall time of said first control potential or a rise time of said second control potential, said predriver comprising a first inverter having a first transistor of a first conductivity type having one end connected to a third power supply line, an other end connected to a first node, and a control terminal connected to said logic signal, a second transistor of a second conductivity type having one end connected to a fourth power supply line, an other end connected to a second node, and a control terminal connected to said logic signal, a third transistor of the second conductivity type having one end connected to said second node, an other end connected to said first node, and a control terminal connected to said logic signal, and a fourth transistor of the second conductivity type having one end connected to said third power supply line, an other end connected to said second node, and a control terminal connected to said first node, wherein said first node supplies said first control potential to said first transistor.