Patent ID: 7381645
Filing Date: 2008-06-03
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit arrangement comprising: providing an initial metallization stratum covered by and in contact with an intermediate layer; forming an insulating layer on the intermediate layer; patterning the insulating layer to form at least one cutout using a dry etching process; extending the cutout using a wet chemical etching process, wherein the intermediate layer is removed in a region exposed by the cutout and a surface region of the initial metallization stratum is exposed; producing at least one further metalization stratum by filling the cutout with one of a metal or a metal alloy; wherein the initial metallization stratum comprises a metal layer which comprises one of aluminum or an aluminum alloy, and wherein a liquid used for the wet chemical etching process comprises an oxidizing agent that oxidizes the metal layer.