Patent ID: 6171891
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method of forming a semiconductor memory device on a semiconductor substrate within which are formed an N-well and a P-well within which source/drain sites are formed comprising the steps as follows:forming a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over the semiconductor substrate with an N-well and a P-well,forming P- lightly doped source/drain regions in the N-well,forming N- lightly doped source/drain regions in the P-well,forming spacers on the gate electrode sidewalls,forming N++ type regions below respective source/drain sites and forming P++ type regions below respective source/drain sites,forming the N+ type source/drain regions in the P-well in the source/drain sites above the N++ type regions,forming the P+ type source/drain regions in the N-well in the source/drain sites above the P++ type regions, andforming additional, deep, lightly doped N- regions in the N-well self-aligned with the spacers below the P++ type regions, andforming additional, deep, lightly doped P- regions in the N-well self-aligned with the spacers below the N++ type regions.