Patent ID: 8321719
Filing Date: 2012-11-27
Classification: G06F,G11C

Abstract:
1. A method comprising: exchanging a first clock signal from a first interface of a memory device to a second interface of a processing unit, the first clock signal generated by a phase-locked loop (PLL) of the first interface based on a reference clock signal provided to the memory device independent of the processing unit, wherein the second interface is an analog front end of the processing unit; wherein a first latching and a second latching are each performed at the second interface based on the exchanged first clock signal; and wherein the first latching for the processing unit to read data from the memory device via a bidirectional data link coupled directly to the first interface and further coupled directly to the second interface, and wherein the second latching is for the processing unit to write data to the memory device via the bidirectional data link.