Patent ID: 6356974
Filing Date: 2002-03-12
Classification: G11C

Abstract:
A flash memory comprising:an array of non-volatile memory cells; and a state machine for controlling operation of the memory in response to program and erase instructions by executing a program operation or an erase operation on the non-volatile memory cells, wherein the erase operation includes a plurality of erase sub-operations, wherein the erase sub-operations and the program operation include common sub-operation functions, and wherein the state machine comprises: a sequencer for controlling the order and the timing of the programming operation and the erase sub-operations by providing sequencer output signals defining the operations and sub-operations to be executed, and providing a sub-operation start signal to initiate execution of the defined sub-operations, and a single loop controller for controlling the order and the timing of the sub-operation functions, wherein the single loop controller is coupled to receive both the sequencer output signals and the start signal from the sequencer, wherein the loop controller provides a loop control output signal for controlling a voltage level of a voltage source which supplies a voltage pulse used for both programming and erasing operations, and wherein the sequencer controls operating settings of an address counter, a pulse counter and a timer using the sequencer output signals.