Patent ID: 9047945
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A system comprising: a resistive random access memory cell connected to a word line and a bit line; a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected; a driver circuit configured to select the word line at a first time subsequent to the bit line being charged to the first voltage; a comparator configured to compare a second voltage on the bit line to a third voltage supplied to the comparator and generate an output based on the comparison; a latch configured to latch the output of the comparator and generate a latched output; and a pulse generator configured to generate a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output, wherein the latched output indicates a state of the resistive random access memory cell.