Patent ID: 6954400
Filing Date: 2005-10-11
Classification: G11C

Abstract:
1. A predecoder circuit for selecting at least one main block, comprising: a first input stage receptive to first, second, and third control signals; a second input stage receptive to multiple multibit data signals; an output stage to produce a multibit selection signal, wherein the multibit selection signal is adapted to select a main block when the first and the second control signals are at a first predetermined level and the third control signal is at a second predetermined level, wherein the multibit selection signal is adapted to select at least one main block when the first control signal is at a second predetermined level, wherein the multibit selection signal is adapted to select all main blocks when the second control signal is at the second predetermined level, and wherein the multibit selection signal is adapted to inhibit the selection of any of the main blocks when the first, second, and third control signals are at the first predetermined level.