Patent ID: 7868795
Filing Date: 2011-01-11
Classification: H03M

Abstract:
1. A method, comprising: providing a J-bit analog to digital converter which receives an analog input signal and produces a corresponding uncalibrated digital result, the uncalibrated digital result having bit providing an extra capacitive element in addition to the plurality of capacitive elements; providing an extra result bit, wherein the extra result bit is generated by performing an operation using the plurality of capacitive elements and the extra capacitive element; providing an analog input voltage at a first input of a comparator; using a first portion of the plurality of capacitive elements and the extra capacitive element to produce a voltage step at a second input of the comparator; if a resulting output of the comparator is a first voltage, asserting the extra result bit and negating bit K through the most significant bit of the uncalibrated digital result, and performing successive approximations to determine bits K−1 to if the resulting output of the comparator is a second voltage, negating the extra result bit and performing successive approximations to determine bits J−1 to