Patent ID: 8493775
Filing Date: 2013-07-23
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array including memory cells arranged in a matrix; a plurality of word lines respectively provided for rows of the matrix; and bit line pairs respectively provided for columns of the matrix, each of the memory cells including a plurality of word driver units coupled to the word lines, respectively, each activating a corresponding coupled word line; a word-line-timing generator configured to generate a word-line timing signal for determining a word-line activation time of the word lines; a comparator operable to make a comparison between the word-line timing signal and a reference signal to detect whether the word-line activation time is shorter or not than a pulse width of the reference signal; and a back-gate voltage control circuit which controls to change respective voltages of back-gates of the first to fourth N-channel transistors based on a detecting result of the comparator.