Patent ID: 6693820
Filing Date: 2004-02-17
Classification: G11C,Y10S

Abstract:
A semiconductor memory device comprising:a first inverter of which output point is a first memory node and input point is a second memory node, said first inverter including a first MOS transistor of a first conductive type; and a second MOS transistor of a second conductive type being different from the first conductive type; a second inverter of which output point is connected to said second memory node and input point is connected to said first memory node, said second inverter including a third MOS transistor of the first conductive type; and a fourth MOS transistor of the second conductive type; a fifth MOS transistor of the second conductive type of which drain is connected to said first memory node, source is connected to one of a pair of bit lines, and gate is connected to a word line; and a sixth MOS transistor of the second conductive type of which drain is connected to said second memory node, source is connected to other one of the pair of bit lines, and gate is connected to the word line, wherein dielectric constant of a gate insulating film of said first and third MOS transistors is higher than dielectric constant of a gate insulating film of said fifth and sixth MOS transistors.