Patent ID: 6260133
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A processor comprising:a first pipeline having a first operating unit for executing a first operation;a second pipeline having a second operating unit separated from said first operating unit and for executing the same type of operation as that of said first operation, and a third operating unit for executing an operation of a type different from that of said first operation;an instruction fetch unit which issues to said first pipeline a first operating instruction to be executed by using one of said operating units in said first pipeline and said second pipeline and a second operating instruction to be executed by using said first operating unit in said first pipeline and one of said operating units in said second pipeline, and issues said first operating instruction to said second pipeline; anda control circuit activated when said instruction fetch unit issues to said first pipeline said second operating instruction to be executed by using said first operating unit and said second operating unit, and simultaneously issues to said second pipeline said first operating instruction to be executed by using said second operating unit to make control such that said first operating instruction is executed preferentially while holding said second operating instruction in wait if said first operating instruction is issued earlier than said second operating instruction, or said second operating instruction is executed preferentially while holding said first operating instruction in wait if said second operating instruction is issued earlier than said first operating instruction, said control circuit including an instruction system control circuit for controlling instruction system in said first operation instruction and said second operating instruction, and said instruction system control circuit including:an interlock signal generating circuit for outputting a first interlock signal when holding said first operating instruction or said second operating instruction issued to said first pipeline in wait, and for outputting a second interlock signal when holding said first operating instruction issued to said second pipeline in wait;a first instruction hold/output circuit responsive to said first interlock signal to hold or output said first operating instruction or said second operating instruction issued to said first pipeline; anda second instruction hold/output circuit responsive to said second interlock signal to hold or output said first operating instruction issued to said second pipeline.