Patent ID: 6671210
Filing Date: 2003-12-30
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of DRAM memory cells each having first, second, and third MOS transistors; a plurality of first word lines coupled to gates of said first MOS transistors; a plurality of second word lines coupled to gates of said second MOS transistors; a plurality of first bit lines coupled to source/drain paths of said first MOS transistors; a plurality of second bit lines coupled to source/drain paths of said second MOS transistors, wherein the plurality of DRAM memory cells includes a series of such memory cells defining a plurality of groups of k memory cells in sequence, and the plurality of first word lines includes a group of k first word lines, each of which is coupled to a gate of only one first MOS transistor in each group of k memory cells, wherein k is greater than one, and wherein the number of data inputted for writing data when one of said plurality of first word lines is selected is the number of said DRAM memory cells provided to said one of said plurality of first word lines.