Patent ID: 7511548
Filing Date: 2009-03-31
Classification: G06F

Abstract:
1. A method of integrating a clock distribution network and a logic design in an integrated circuit, the clock distribution network having a number of distribution levels from a clock source and a plurality of logic leaf connection nodes, each distribution level including at least one distribution segment, the method comprising: providing a logic design having a plurality of clocked logic elements; determining a desired load value for each of the plurality of logic leaf connection nodes; grouping one or more of said plurality of clocked logic elements together in a corresponding respective one of a plurality of register structures, each of said plurality of clocked logic elements being grouped in one of said plurality of register structures, each of said plurality of register structures having a load on said clock distribution network that is substantially the same as said desired load value; assigning each of said plurality of register structures to a corresponding respective one of said plurality of logic leaf connection nodes; and connecting a dummy register to a corresponding respective one of said plurality of logic leaf connection nodes that is not connected to one of said plurality of registers, said dummy register having a load on said clock distribution network that is substantially the same as said desired load value.