Patent ID: 8966180
Filing Date: 2015-02-24
Classification: G06F,G11C,Y02D

Abstract:
1. A processor comprising: a core including a computation processor and a scatter/gather engine coupled to the computation processor, the scatter/gather engine to generate sub-cache line sized non-sequential data accesses to a system memory based on a data access pattern to the system memory, and to communicate sub-cache line sized data with the system memory, the data access pattern comprising a program defined access pattern, wherein the scatter/gather engine includes an access pattern generator to generate the sub-cache line sized non-sequential data accesses to the system memory based on the program defined access pattern comprising a stride-based access pattern; a cache coupled to the core, data to be transferred between the cache and the system memory using full-cache line sized transfers; and a memory controller coupled between the cache and the system memory.