Patent ID: 7941714
Filing Date: 2011-05-10
Classification: G11C

Abstract:
1. A parallel bit test (PBT) apparatus included in memory chips that are stacked in a multi-chip package (MCP) and share a set of data signal lines, the PBT apparatus comprising: a comparing unit configured to output a representative data signal that is representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit configured to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal wherein a plurality of the memory chips simultaneously output respective representative data using the respective non-overlapping subsets of the shared data signal lines.