Patent ID: 6782512
Filing Date: 2004-08-24
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor device on a semiconductor substrate, comprising:designing a conductive pattern to be formed on the semiconductor substrate; performing a sizing adjustment by plotting an imaginary periphery of the conductive pattern, the imaginary periphery being enlarged, with respect to the conductive pattern, if the conductive pattern will be formed by parallel-plate plasma chemical vapor deposition, and narrowed, with respect to the conductive pattern, if the conductive pattern will be formed by high-density plasma chemical vapor deposition; deciding, for a given region on the semiconductor substrate, whether to add a dummy pattern to the conductive pattern in the given region, by selecting a prescribed region including the given region and determining what proportion of the prescribed region is disposed within the imaginary periphery; forming the conductive pattern and dummy pattern on the semiconductor substrate; depositing a dielectric layer on the semiconductor substrate, covering the conductive pattern and the dummy pattern; and planarizing the dielectric layer by chemical mechanical polishing.