Patent ID: 6759874
Filing Date: 2004-07-06
Classification: H03K

Abstract:
An electronic circuit, comprising:a first supply voltage terminal; a second supply voltage terminal; a driver circuit for driving a signal onto a signal line having a specific characteristic impedance, said driver circuit having a first switching device with a first forward resistance between said first supply voltage terminal end the signal line, and a second switching device with a second forward resistance between said second supply voltage terminal and the signal line; said first switching device containing a plurality of parallel-connected first transistors having control inputs and a second transistor having a control input and being connected in series with said plurality of parallel-connected first transistors; a control circuit connected to said driver circuit and generating a first control signal and a second control signal controlling said first switching device and said second switching device in a first operating mode such that, depending on the signal to be driven, either said first switching device or said second switching device being through-connected so that the signal will be driven onto the signal line, said control circuit activating said first switching device and said second switching device substantially simultaneously in a second operating mode with an aid of the first and second control signals so that said first and second forward resistances together form a terminating resistance; and said second switching device containing a plurality of parallel-connected third transistors having control inputs and a fourth transistor having a control input and being connected in series with said plurality of parallel-connected third transistors, said control input of said second transistor receiving the first control signal and said control input of said fourth transistor receiving the second control signal, said control inputs of said first transistors receiving first selection signals and said control inputs of said third transistors receiving second selection signals, the first forward resistance being set by forward resistances of said first transistors activated with an aid of the first selection signals and said second transistor, and the second forward resistance being set by forward resistances of said third transistors activated with an aid of the second selection signals and said fourth transistor.