Patent ID: 6924173
Filing Date: 2005-08-02
Classification: H01L

Abstract:
1. A method for the fabrication of a semiconductor device comprising the steps of: preparing a first semiconductor element having a major surface on which a plurality of first element electrodes are disposed and a second semiconductor element having a major surface on which a plurality of second element electrodes are disposed; placing said first and second semiconductor elements such that their said major surfaces face each other, and thereafter electrically connecting together at least a portion of said plural first element electrodes of said first semiconductor element and at least a portion of said plural second element electrodes of said second semiconductor element by a connection member; forming an insulation layer coating a backside surface of said second semiconductor element and said major surface of said first semiconductor element; forming in said insulation layer an opening portion exposing at least a portion of said plural first element electrodes; and forming on said insulation layer a wiring layer which is electrically connected to said first element electrode exposed in said opening portion, a portion of said wiring layer functioning as an external electrode electrically connectable to external equipment.