Patent ID: 7330387
Filing Date: 2008-02-12
Classification: G11C

Abstract:
1. An integrated semiconductor memory device comprising: a first bit line and a second bit line; at least one memory cell that is connected to the first bit line to store a first memory state or a second memory state; a first controllable voltage generator to produce a negative voltage; a second controllable voltage generator to produce a positive voltage; a sense amplifier including a first output connection and a second output connection, wherein the sense amplifier is configured to receive the negative voltage from the first controllable voltage generator via a first controllable switch and to receive the positive voltage from the second controllable voltage generator via a second controllable switch, and the sense amplifier is further configured to produce the negative voltage or the positive voltage at the first output connection and the second output connection; a control circuit configured to switch the first and second controllable switches on when writing a memory state to the memory cell or when reading a memory state from the memory cell; and a register configured to store operating parameters for the memory device including a nominal value of the negative voltage and a nominal value of the positive voltage; wherein: