Patent ID: 6505329
Filing Date: 2003-01-07
Classification: G06F,H01L

Abstract:
A method of designing a semiconductor device by laying out a plurality of macro cells on a semiconductor chip, said semiconductor chip having a plurality of chip pads each being used to perform at least one of signal receiving and signal outputting functions with respect to an outside of said semiconductor chip, comprising:a fit group of chip pads, an interval of adjacent ones of which is varied in accordance with at least one of a size of the semiconductor chip and macro cells to be laid out on the semiconductor chip, and second group of chip pads, an interval of adjacent ones of which is substantially fixed irrespective of the size of the semiconductor chip and the macro cells to be laid out on the semiconductor chip, making up at least one of said macro cells as a hard macro comprising a plurality of circuit elements and at least two macro pads for signal transfer, said bard macro thereby including first layout and interconnective information among said circuit elements and second layout and interconnective information between said at least two macro pads and said circuit elements, and allocating at least two of said second group of chip pads to said at least two macro pads of said hard macro.