Patent ID: 6687178
Filing Date: 2004-02-03
Classification: G11C

Abstract:
A write control circuit for a magnetic tunnel junction MRAM, comprising:a bit line including a first end electrically connected to a first temperature dependent write current source by a first write transistor having a gate controlled by a first write logic gate, and electrically connected to a first write current sink by a first sink transistor having a gate controlled by a second write logic gate, a second end electrically connected to a second temperature dependent write current source by a second write transistor having a gate controlled by the second write logic gate, and electrically connected to a second write current sink by a second sink transistor having a gate controlled by the first write logic gate, and a segment disposed in a first direction proximate to the magnetic tunnel junction MRAM; and a digit line including a third temperature dependent write current source electrically connected to a first end by a third write transistor, a third write current sink electrically connected to a second end by a third sink transistor, and a segment, disposed in a second direction oriented approximately 90Â° to the first direction, proximate to the magnetic tunnel junction MRAM.