Patent ID: 6058060
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A method for operating a selected memory cell in an array of memory cells, comprising:during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell; andapplying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the selected memory cell; andduring a programming operation, applying the first negative voltage to a third word-line, wherein the third word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in an erased state;applying a non-negative voltage to a fourth word-line, wherein the fourth word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in a programmed state; andapplying a programming voltage to a fifth word-line, wherein the fifth word-line is coupled to the memory cell selected for programming.