Patent ID: 7696974
Filing Date: 2010-04-13
Classification: G09G,G11C

Abstract:
1. A shift register including a plurality of stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of scan line driving signals for selecting a plurality of scan lines, each of the stages comprising: a carry buffer configured to provide one of next stages with a carry signal corresponding to the first clock signal or the second clock signal, the second clock signal having a phase different from a phase of the first clock signal; a pull-up part configured to provide an output terminal electrically connected to one of the plurality of scan lines with a first scan line driving signal corresponding to the first clock signal or the second clock signal, wherein the carry signal is provided to one of the next stages through a different node from the output terminal; a pull-down part configured to provide the output terminal with a first power voltage; a pull-up driver part configured to turn on the pull-up part in response to the carry signal provided from one of previous stages and configured to turn off the pull-up part in response to a second scan line driving signal of the one of the next stages; and a pull-down driver part configured to turn off the pull-down part in response to the carry signal provided from the one of the previous stages and configured to turn on the pull-down part in response to the second scan line driving signal of the one of the next stages.