Patent ID: 9165860
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A multi-chip semiconductor chip comprising a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips comprises: a through-silicon via (TSV) formed through the semiconductor chip; a first bump pad exposed to an outside of the semiconductor chip and electrically connected to the TSV through a first conductive path, the first bump being located along a first surface of the semiconductor chip; a second bump pad exposed to an outside of the semiconductor chip, the second bump being located along a second surface of the semiconductor chip opposite the first surface; an internal circuit formed in the semiconductor chip; and a probe pad exposed to the outside of the semiconductor chip, the probe pad being located along the first surface of the semiconductor chip, wherein the probe pad is accessible by a probing test and electrically connected to the internal circuit through a third conductive path, wherein the first conductive path is formed between a first end of the TSV and the first bump pad, a second conductive path is formed between a second end of the TSV and the internal circuit so as to be exposed to the outside of the semiconductor chip, and the third conductive path is formed between the probe pad and the internal circuit.