Patent ID: 6448141
Filing Date: 2002-09-10
Classification: H01L,Y10S

Abstract:
A method for producing an NMOSFET on a semiconductor substrate, said NMOSFET having at least one graded LDD source region and at least one graded LDD drain region separated by a channel, said method comprising:providing a gate structure on said semiconductor substrate, said gate structure including gate sidewalls; implanting said semiconductor substrate with a first dosage N type conductivity-altering material creating a lightly doped source region and a lightly doped drain region; growing an oxide layer on at least a portion of the gate sidewalls of said gate structure and an exposed surface of an area of said semiconductor substrate; forming sidewall spacers abutting said gate structure covering portions of said first dosage implanted semiconductor substrate and said oxide layer on at least a portion of the gate sidewalls of said gate structure and the exposed surface of said area of said semiconductor substrate; implanting said semiconductor substrate with a second dosage N type conductivity-altering material to create a heavily doped source region and a heavily doped drain region flanking said gate structure, said heavily doped source and drain regions supplanting respective uncovered portions of said lightly doped source and drain regions, said second dosage N type conductivity-altering material being a greater dosage than the first dosage N type conductivity-altering material; and implanting said semiconductor substrate with a third dosage N type conductivity-altering material grading said heavily doped source and drain regions and remaining portions of said lightly doped source and drain regions, said third dosage of N type conductivity altering material being a lesser dosage than the second dosage N type conductivity-altering material.