Patent ID: 7580491
Filing Date: 2009-08-25
Classification: H03L,H04L

Abstract:
1. A clock recovery circuit comprising: a clock generator adapted to generate first, second, third, and fourth clocks having a quarter frequency of a data-rate of input data, and the second, third, and fourth clocks with respect to a phase of the first clock having phase differences of 90, 180, and 270 degrees, respectively; a phase interpolation unit adapted to perform a phase interpolation on the first, second, third, and fourth clocks to generate fifth, sixth, seventh, and eighth clocks, respectively, each having a quarter frequency of the data-rate of the input data, wherein the fifth clock tracks a phase of the input data, and the sixth, seventh, and eighth clocks having phase differences of 45, 90, and 135 degrees with respect to a phase of the fifth clock, respectively; a phase detector adapted to output signals corresponding to phase differences between the input data and the fifth, sixth, seventh, and eighth clocks; and a controller adapted to receive the output signals from the phase detector and to generate control signals to control the phase interpolation unit, wherein the phase interpolation unit includes