Patent ID: 6205062
Filing Date: 2001-03-20
Classification: G11C

Abstract:
A latency control circuit comprising:a control circuit adapted to receive a clock signal to regulate data output and a plurality of input signals to provide first, second and third control signals;a first logic gate to logically combine a CAS latency control signal with data;a first latch to pass or latch data from said first logic gate in response to the third control signal from said control circuit unit;a second logic gate to logically combine a second logic gate control signal with data;a second latch to pass or latch data from said first latch or to pass or latch a data from said second logic gate in response to the second control signal from the control circuit unit; anda third latch to pass data from said second latch to a data output buffer or latch the data in response to the first control signal from said control circuit unit.