Patent ID: 7687867
Filing Date: 2010-03-30
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a substrate including a dielectric layer and at least one conductive interconnect, wherein said at least one conductive interconnect is embedded in said dielectric layer and has an upper surface that is located above an upper surface of said dielectric layer; a dielectric stack located on said upper surface of said at least one conductive interconnect and said upper surface of said dielectric layer; a MIM capacitor located on said dielectric stack, wherein said MIM capacitor comprises a bottom plate electrode located on said dielectric stack, a capacitor dielectric located on said bottom plate electrode, and a top plate located on said capacitor dielectric; and an etch stop layer located on a top surface of said top plate electrode, wherein sidewalls of said etch stop layer, sidewalls of said top plate electrode, and first sidewalls of said capacitor dielectric are vertically coincident with one another, and wherein second sidewalls of said capacitor dielectric are located outside a periphery of said first sidewalls of said capacitor dielectric and below said sidewalls of said capacitor dielectric.