Patent ID: 6893908
Filing Date: 2005-05-17
Classification: G02F,H01L

Abstract:
1. A method of fabricating a thin film transistor array substrate, comprising the steps of: forming a gate wire on an insulating substrate through depositing a conductive layer for the gate wire on the substrate and patterning the conductive layer, the gate wire comprising a gate line and a gate electrode; forming a gate insulating layer on the substrate to cover the gate wire; forming a semiconductor layer on the gate insulating layer; depositing a conductive layer for a data wire and a metallic layer on the gate insulating layer sequentially, and then performing an annealing process; forming a data wire by patterning the conductive layer, the data wire comprising a data line, a source and a drain electrode; depositing a protective layer covering the data wire; forming a first contact hole exposing the drain electrode; and forming a pixel electrode electrically connected to the drain electrode.