Patent ID: 7842601
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A method of forming small pitch patterns comprising: forming a material layer on a semiconductor substrate; forming a first hard mask on the material layer, wherein the first mask layer is characterized by a smaller line width for mask elements than a separated distance between adjacent mask elements; forming a first spacer layer on the first hard mask to covering sidewall portions of the first hard mask; forming a second spacer layer on the first spacer layer, the second spacer layer having an etch selectivity with respect to the first spacer layer; forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask by spacer-etching the second spacer layer; selectively removing a portion of the first spacer layer between the first hard mask and the second hard mask; forming a small pitch pattern by selectively etching the material layer using the combination of the first and second hard masks as an etch mask, and forming a third hard mask having a line width or a pitch different from that of the first hard mask concurrently when forming the first hard mask.