Patent ID: 6806141
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A method for forming a field effect transistor comprising the steps of:a) providing a conductive substrate; then b) etching said substrate to form an upstanding pillar adjacent a substantially-planar upper surface of said etched substrate; then c) forming a stack of substantially-planar layers of material adjacent said pillar, said stack of material comprising a first insulator layer adjacent said upper surface of said etched substrate, a gate layer of conductive material overlying said first insulator layer and a second insulator layer overlying said gate layer; then d) etching said pillar to the level of said substantially-planar upper surface of said etched substrate to form a upstanding pore within said stack; then e) forming a gate insulator layer at the interior of said upstanding pore; then f) forming an upstanding channel of semiconductor material having a top region and a bottom region interior of said gate insulator layer; and then g) heavily doping said top region of said upstanding channel of semiconductor material.