Patent ID: 6678749
Filing Date: 2004-01-13
Classification: G06F

Abstract:
An apparatus for facilitating bidirectional communications between a processor, at least one peripheral device, and at least one memory device in an electronic system, comprising:a processor interface for communicating with said processor, wherein said processor interface includes at least one processor command buffer and at least one processor data buffer; at least one peripheral interface for communicating with said at least one peripheral device, wherein said at least one peripheral interface includes at least one peripheral data buffer; and at least one memory interface for communicating with said at least one memory device, wherein said at least one memory interface includes at least one memory command buffer, and wherein said processor interface, said at least one peripheral interface, and said at least one memory interface are electronically coupled to each other to facilitate the transfer of data between said processor, said at least one peripheral device, and said at least one memory device.