Patent ID: 6134633
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A cache memory, the cache memory supporting prefetch operations and cache access operations so as to store information duplicated from a high level memory for use by a processing device, the processing device issuing addresses, including prefetch addresses and cache access addresses, the cache memory comprising:memory resources for storing information; andprefetch resources coupled to the memory resources and to the processing device for storage of prefetch addresses from the processing device and for injection management of the stored prefetch addresses so as to coordinate prefetch operations with cache access operations,wherein the prefetch resources include a prefetch memory, a selector and a multiplexor, the prefetch memory providing for storing prefetch addresses, the selector being coupled to the prefetch memory and to the memory resources, the selector directing prefetch addresses to the prefetch memory and directing cache access addresses to the memory resources, andthe multiplexor being coupled to the selector, to the prefetch memory and to the memory resources, and the multiplexor directing to the memory resources selected prefetch and cache access addresses received from the prefetch memory and the selector.