Patent ID: 6392921
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A driving circuit for a non destructive non volatile ferroelectric random access memory, comprising:a plurality of NDRO-FRAM (Non Destructive Non Volatile Ferroelectric Random Access Memory) cells separately having a drain, a bulk, a source and a gate and arranged as a matrix; a plurality of reading word lines separately connected to the each drain of the NDRO-FRAM cells arranged in columns; a plurality of writing word lines separately connected to the each bulk of the NDRO-FRM cells arranged in columns; a plurality of reading bit lines separately connected to the each source of the NDRO-FRAM cells arranged in rows; a plurality of writing bit lines separately connected to the each gate of the NDRO-FRAM cells arranged in rows; a plurality of word line decoders for generating and transmitting separately a reading word signal and a writing word signal by connecting to the one reading word line and one writing word line connected to the NDRO-FRAM cell in the same column; a plurality of data level transmission circuits for transmitting data level of the NDRO-FRAM cell by connecting to the one reading bit line; a sense amp for detecting the data level of the NDRO-FRAM cell by connecting to the plurality of data level transmission circuits; and a writing driver for generating and transmitting a writing bit signal by connecting to the plurality of the writing bit lines.