Patent ID: 6583017
Filing Date: 2003-06-24
Classification: H01L

Abstract:
A method of forming a semiconductor for use with a gate electrode damascene process, comprising:providing a semiconductor silicon substrate; forming a thin dielectric layer on top of said substrate; depositing a thick layer of oxide on top of said thin dielectric layer; creating a trench pattern, said trench pattern to penetrate and go through said thick layer of oxide furthermore to penetrate and go through said thin dielectric layer furthermore to penetrate the surface of said silicon substrate to form a shallow trench pattern in said substrate; forming a thin layer of oxide at the bottom of said trench pattern; forming spacers on sidewalls of said trench pattern; performing a channel implant in said silicon substrate, said channel implant being self-aligned with said trench pattern, said channel implant penetrating the surface of said substrate to a depth within a range of between 0.02 and 1.5 &mgr;m; removing said thin layer of oxide from the bottom of said trench pattern where said thin layer of oxide is not covered by said spacers; forming a gate dielectric at the bottom of said trench pattern and on said gate dielectric where said thin layer of oxide has been removed; forming a gate electrode in said trench pattern; removing said thick layer of oxide from the top of said thin dielectric layer; removing said thin dielectric layer from the top of said substrate; performing source and drain implant in the surface of said silicon substrate said implant to be substantially self-aligned with said spacers; forming salicide on the surface of said silicon substrate above said source and drain implants and on the top surface of said gate electrode; removing said spacers from sidewalls of said trench pattern; and forming Lightly Doped Drain areas in said silicon substrate, said LDD areas being self-aligned with extreme corners of said bottom of said trench pattern by an angle implantation.