Patent ID: 6984859
Filing Date: 2006-01-10
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor memory device, comprising: a memory cell storing data; and a word line and a pair of bit lines connected to said memory cell; wherein said memory cell includes a first inverter including a first load element and a first driving element having an N channel MOS transistor, a second inverter cross-coupled with said first inverter, including a second load element and a second driving element having another N channel MOS transistor, first and second storage nodes connected respectively to output nodes of said first and second inverters, and first and second gate elements each including a P channel MOS transistor having a gate electrode connected to said word line, connecting said first and second storage nodes to one bit line and the other bit line of said pair of bit lines, respectively; a first metal interconnection forming said first storage node is provided stacked on said first driving element and said first gate element formed on a substrate surface; a second metal interconnection forming said second storage node is provided stacked on said second driving element and said second gate element formed on said substrate surface; and said first and second load elements are provided above said first and second metal interconnections.