Patent ID: 7424050
Filing Date: 2008-09-09
Classification: H04B

Abstract:
1. A matched filter circuit which receives reception data and spreading codes externally and operates according to external oversampling setting, comprising: first data shift register means, for receiving the reception data and for storing and shifting data having a prescribed oversampling phase; first data input route selecting means, for selecting the reception data or a shift output of a final stage of the first data shift register means in accordance with the oversampling setting; second data shift register means, for receiving an output of the first data input route selecting means and for storing and shifting data having a prescribed oversampling phase; second data input route selecting means, for selecting the reception data or a shift output of a final stage of the second data shift register means in accordance with the oversampling setting; third data shift register means, for receiving an output of the second data input route selecting means and for storing and shifting data having a prescribed oversampling phase; third data input route selecting means, for selecting the reception data or a shift output of a final stage of the third data shift register means in accordance with the oversampling setting; and fourth data shift register means, for receiving an output of the third data input route selecting means and for storing and shifting data having a prescribed oversampling phase; first code shift register means, for receiving the spreading codes and for storing and shifting spreading codes corresponding to the first data shift register means; first code input route selecting means, for selecting the spreading codes or a shift output of a final stage of the first code shift register means in accordance with the oversampling setting; second code shift register means, for receiving an output of the first code input route selecting means and for storing and shifting spreading codes corresponding to the second data shift register means; second code input route selecting means, for selecting the spreading codes or a shift output of a final stage of the second code shift register means in accordance with the oversampling setting; third code shift register means, for receiving an output of the second code input route selecting means and for storing and shifting spreading codes corresponding to the third data shift register means; third code input route selecting means, for selecting the spreading codes or a shift output of a final stage of the third code shift register means in accordance with the oversampling setting; and fourth code shift register means, for receiving an output of the third code input route selecting means and for storing and shifting spreading codes corresponding to the fourth data shift register means; first despreading integration calculating means, for performing despreading calculation and integration calculation using outputs of the first data shift register means and outputs of the first code shift register means; second despreading integration calculating means, for performing despreading calculation and integration calculation using outputs of the second data shift register means and outputs of the second code shift register means; third despreading integration calculating means, for performing despreading calculation and integration calculation using outputs of the third data shift register means and outputs of the third code shift register means; and fourth despreading integration calculating means, for performing despreading calculation and integration calculation using outputs of the fourth data shift register means and outputs of the fourth code shift register means; first adding means, for adding together an output of the first despreading integration calculating means and an output of the second despreading integration calculating means; second adding means, for adding together an output of the third despreading integration calculating means and an output of the fourth despreading integration calculating means; and third adding means, for adding together an output of the first adding means and an output of the second adding means; cumulative addition means, for receiving an output of the first despreading integration calculating means, an output of the second despreading integration calculating means, an output of the third despreading integration calculating means, an output of the fourth despreading integration calculating means, an output of the first adding means, an output of the second adding means, and an output of the third adding means, and for performing cumulative addition in accordance with the oversampling setting; and storing means, for temporarily storing cumulative addition data that are output from the cumulative addition means.