Patent ID: 6144225
Filing Date: 2000-11-07
Classification: H01L,H03K

Abstract:
An integrated circuit, comprising:a capacitor comprising a first planar metal plate and a second planar metal plate, the first planar metal plate having a lateral boundary, the second planar metal plate having a lateral boundary, the first planar metal plate extending in a first plane, the second planar metal plate extending in a second plane, the first plane being parallel to the second plane;a power bus extending in a third plane, the third plane being substantially parallel to the first plane and to the second plane, the power bus being coupled to the second planar metal plate of the capacitor;a first logic block comprising a first digital logic element; anda second logic block comprising a second digital logic element, the second digital logic element having an output lead coupled to an input lead of the first digital logic element, the second logic block having a lateral boundary, the lateral boundaries of the first and second planar metal plates being disposed in the lateral dimension within the lateral boundary of the second logic block, during a switching period of a voltage on the output lead from a first digital logic level to a second digital logic level a peak current ICAPpeak flows from the second planar metal plate of the capacitor and to the second digital logic element, during the switching period a peak current ICCpeak flows from the power bus and to the second digital logic element, ICCpeak being smaller than ICAPpeak.