Patent ID: 8327206
Filing Date: 2012-12-04
Classification: G01R,H04L

Abstract:
1. A blanking primitive masking circuit comprising: a memory storing reference data and including a memory controller generating memory addresses to output the reference data; a delay circuit receiving parallel data having blanking primitives and generating delayed parallel data; a pattern detector receiving the delayed parallel data and a selected data pattern and generating a synchronization signal in response to the detection of the selected data pattern in the delayed parallel data and a phase sync signal representative of a phase difference between the delayed parallel data and the selected data pattern; a detector receiving the parallel data and the phase sync signal and detecting occurrences of the blanking primitives in the parallel data with the detector generating a first output signal for suppressing the detected blanking primitives and a second output signal coupled to the memory for suppressing the generation of memory addresses from the memory controller during the occurrence of blanking primitives; and a comparator receiving the reference data from the memory, the delayed parallel data from the delay circuit, the phase sync signal, and the first output signal from the detector and generating bit error outputs when the first output signal from the detector indicates the absence of blanking primitives in the parallel data and suppressing the generation of bit error outputs when the first output signal indicates the presence of blanking primitives in the parallel data.