Patent ID: 8618632
Filing Date: 2013-12-31
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a multi-layered wiring substrate having a main surface, a rear surface, and at least one inner layer; first and second transistors each having first, second, and third transistor electrodes and mounted on the main surface of the multi-layered wiring substrate; and at least one input-side capacitor having first and second capacitor electrodes and mounted on the rear surface of the multi-layered wiring substrate, wherein the multi-layered wiring substrate includes: first wiring layers to be supplied with a first potential formed on at least the main surface and the rear surface; a second wiring layer to be supplied with a second potential formed on at least the main surface; third wiring layers to be supplied with a third potential formed on each of the main surface, the rear surface, and the inner layer; at least one first via conductor for electrically connecting among the first wiring layers in a thickness direction of the multi-layered wiring substrate; and at least one second via conductor for electrically connecting among the third wiring layers in the thickness direction, wherein the first transistor is mounted on the first wiring layer on the main surface so that the first transistor electrode of the first transistor is electrically connected to the first wiring layer on the main surface, and the second transistor electrode of the first transistor is electrically connected to the second wiring layer on the main surface, wherein the second transistor is mounted on the second wiring layer on the main surface so that the first transistor electrode of the second transistor is electrically connected to the second wiring layer on the main surface, and the second transistor electrode of the second transistor is electrically connected to the third wiring layer on the main surface, wherein the first capacitor electrode of the input-side capacitor is electrically connected to the first wiring layer, and the second capacitor electrode of the input-side capacitor is electrically connected to the third wiring layer, and the multi-layered wiring substrate includes: a third via conductor for the input-side capacitor arranged at a position of the first capacitor electrode and for electrically connecting among the first wiring layers in the thickness direction; and a fourth via conductor for the input-side capacitor arranged at a position of the second capacitor electrode and for electrically connecting among the third wiring layers in the thickness direction, and the first via conductor being arranged directly below the first transistor, and a cross-sectional area of the first via conductor being larger than cross-sectional areas of the via conductor for the input-side capacitor and the via conductor for the input-side capacitor.