Patent ID: 6316296
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method of manufacturing a dual gate structure field-effect transistor, comprising the steps of:forming a trench in an SOI substrate comprised of a semiconductor support substrate, a buried insulation layer formed on the support substrate and an SOI semiconductor layer formed on the insulation layer, so as to extend from an upper surface of the SOI substrate through the SOI semiconductor layer and the buried insulation layer to the semiconductor support substrate, thereby dividing the SOI semiconductor layer into two SOI semiconductor layer regions that form a source electrode and a drain electrode,forming a gate electrode constituted of low resistance material in a portion of the trench in contact with the buried insulation layer, thereby self-aligning with the source electrode and drain electrode,forming a gate insulation layer on the gate electrode in contact with the buried insulation layer around the trench,forming a semiconductor conduction channel layer on the gate insulation layer in contact with the two SOI semiconductor layer regions around the trench,forming an upper gate insulation layer on an upper surface of the semiconductor conduction channel layer and a SOI semiconductor layer inside surface defining the trench, andforming an upper gate electrode in the trench so as to have a bottom surface and side surface covered by the upper gate insulation layer, thereby self-aligning with the gate electrode, source electrode and drain electrode.