Patent ID: 6586277
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A method for reducing thermal mismatch stress in a semiconductor device package for a semiconductor die having an integrated circuit and at least one electrically conductive bond pad, the method comprising adhering the semiconductor die to a die attach surface of an interposer by using a plurality of strips of adhesive film disposed therebetween, the strips having respective widths and extending across a portion of a width of the package, a sum of the respective widths of the strips being substantially less than the width of the package, the strips including a compliant carrier layer having a pair of opposing surfaces with a first adhesive layer disposed on a first surface of the opposing surfaces of the carrier layer to adhere the carrier layer to the die attach surface of the interposer, and a second adhesive layer disposed on a second surface of the opposing surfaces of the carrier layer to adhere the carrier layer to the die, the interposer having at least one conductive interconnect electrically coupled to the bond pad, and further having an external surface opposite of the die attach surface and to which an external terminal electrically coupled to the conductive interconnect is adjacent.