Patent ID: 8559223
Filing Date: 2013-10-15
Classification: G11C,H01L

Abstract:
1. A semiconductor memory, comprising: a semiconductor substrate; a first memory cell array formed on the semiconductor substrate by arranging a plurality of NAND cell units, the NAND cell unit of the first memory cell array comprising a non-volatile memory cell including a first transistor and a first and a second selective transistor each including a second transistor, the first transistor having a stacked structure in which a first insulation film, a first gate film, a second insulation film, and a second gate film are stacked on the substrate, and having a two-layer gate structure in which a source region and a drain region are formed on both sides interposing a channel region below the first insulation film, the second transistor having a structure same as the structure of the first transistor except for having a two-layer gate structure in which an opening is provided in the second insulation film and the first gate film and the second gate film are electrically connected, the non-volatile memory cells being connected in series in a source/drain direction and the first and second selective transistors are connected to first and second ends respectively of a serial connection portion connecting the non-volatile memory cells in series; and a second memory cell array formed by arranging a plurality of DRAM cells on the substrate, the DRAM cell of the second memory cell array comprising a cell transistor and a first MOS capacitor, the cell transistor including a third transistor having a structure same as the structure of the second transistor, the first MOS capacitor having a stacked structure same as the structure of the first or second transistor and including a source-corresponding region and a drain-corresponding region, the first gate film being connected to a plate line in the first MOS capacitor, the source-corresponding region of the MOS capacitor is connected to the source region of the cell transistor.