Patent ID: 7735049
Filing Date: 2010-06-08
Classification: G01R

Abstract:
1. A method for synthesizing an output-mask controller for generating a plurality of output-mask enable signals for selectively masking off unknown (‘x’) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an output-mask network embedded on a scan data input path of second selected scan cells, each scan chain comprising multiple scan cells coupled in series; said method comprising computer-implemented steps of: (a) a computer compiling HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database; (b) specifying input constraints on said output-mask controller; (c) synthesizing said output-mask controller and said output-mask network on said design database according to said input constraints; and (d) generating synthesized HDL code for said output-mask controller and said output-mask network in a selected RTL or gate-level format.