Patent ID: 6617984
Filing Date: 2003-09-09
Classification: G11B,H03M

Abstract:
A 16B/20B encoder comprising:a first discrete 8B/10B encoder comprising, first encoder circuitry to encode a first 8-bits of input data into a first 10-bits of output data, and disparity control circuitry to calculate a running disparity of the first 10-bits of output data, the disparity control circuitry provides a running disparity output signal indicating a running disparity of the first 10-bits of output data; and a second discrete 8B/10B encoder comprising, second encoder circuitry to encode a second 8-bits of input data into a second 10-bits of output data, and disparity control circuitry to calculate a running disparity of the second 10-bits of output data using the running disparity output signal from the first discrete 8B/10B encoder; wherein the first 10-bits of output data comprises a first set of bits of the first 10-bits and a second set of bits of the first 10-bits, and wherein the disparity control circuitry of the first discrete 8B/10B encoder uses first disparity information for the first set and second disparity information for the second set to calculate the running disparity output signal from the first discrete 8B/10B encoder.