Patent ID: 6366127
Filing Date: 2002-04-02
Classification: H03K

Abstract:
A CMOS voltage interface circuit having an input node which provides an input signal to said interface circuit and also an output node, said interface circuit comprising an input signal conditioning block connected to said input node and providing first and second output signals corresponding to said input signal, and an interface block responsive to said first and second output signals which provides at least a different output signal having a selected output level, the signal conditioning block has means which cause said first and second outputs to switch states when the input signal is switching state and which provide said first and second output signals in high state and low state when overlapping, and one of said first and second output signals high and the other of said first and second output signals low, when said first and second output signals are not overlapping, where the interface block has two inputs and two outputs between which are connected two NMOS and two PMOS transistors, where the NMOS transistors are driven by the inputs and the PMOS transistors are driven by the outputs.