Patent ID: 6041009
Filing Date: 2000-03-21
Classification: G11C

Abstract:
An antifuse stabilizing apparatus for a memory device including a peripheral circuit, the antifuse stabilizing apparatus, comprising:a first terminal;a second terminal;a serial antifuse block which has a plurality of antifuses being interconnected in series between the first terminal and the second terminal;an antifuse programming block for applying a program voltage to an electrode of a selected antifuse of said plurality of antifuses of the serial antifuse block in accordance with a plurality of antifuse selection signals;a switching means controlled by a programming control signal and for applying selectively a high level voltage to the first terminal; anda detecting means for outputting an antifuse state signal detecting whether or not the selected antifuse is programmed,wherein a low level voltage is applied to the second terminal; andwherein the antifuse programming block is controlled by an inverted signal of the programming control signal.