Patent ID: 8546873
Filing Date: 2013-10-01
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a substrate having first and second device regions on a surface of the substrate; first spacers of a first width on sidewalls of a first gate stack in said first device region; second spacers of a second width on sidewalls of a second gate stack in said second device region, wherein the first width is different from the second width; first source/drain stressor elements having a first proximity to a first channel in the substrate below the first gate stack determined by the first spacers; and second source/drain stressor elements having a second proximity to a second channel in the substrate below the second gate stack determined by the second spacers, wherein at least one of the first source/drain stressor elements is disposed in the substrate and displaced from the sidewall of the first gate stack by the first width of the first spacer.