Patent ID: 8487653
Filing Date: 2013-07-16
Classification: H03B,H03L

Abstract:
1. A Field Programmable System Chip (FPSC) comprising Field Programmable Hybrid Array (FPHA) means being a single chip having hierarchical pipeline structure constitutes of analog/RF front, field programmable pipelining, array means, analog and digital converter means for high speed signal processing, said analog/RF front converting analog/RF signal to be analog signal and forwarding to said analog and digital converter means and receiving analog signal from said analog and digital converter means and converting to be analog/RF signal; said analog and digital converter means making conversion between analog signals and digital signals for said high speed signal processing, said pipelining array means having arrays in pipelined structure to make the faster high-speed signal processing with a pipelining signal flow for said high speed signal processing; said analog and digital converter means transmitting digital signal to said pipelining array means and receiving high speed digital data from said pipelining array means, said pipelining array means, analog and digital converter means having field programmable capabilities to reconfigure circuits; said hierarchical pipeline structure having pipeline structures in architecture, system, connection and circuit levels.