Patent ID: 6979614
Filing Date: 2005-12-27
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, the method comprising: providing a semiconductor substrate having a plurality of active regions defined therein; forming a plurality of gate lines extending across the plurality of active regions on the semiconductor substrate, wherein top surfaces and sidewalls of the gate lines are covered with a capping layer; forming a first interlayer insulating layer pattern to fill spaces between the plurality of gate lines; forming a second interlayer insulating layer pattern overlying the first interlayer insulating layer pattern and the capping layer; forming a first etch stop layer pattern on the second interlayer insulating layer to form openings to expose portions of the second interlayer insulating layer; forming a plurality of contact holes exposing the active regions by etching the second interlayer insulating layer and the first interlayer insulating layer, using the first etch stop layer pattern as an etch mask; forming a plurality of contact pads contacting the active regions by partially filling the plurality of contact holes with a conductive layer; forming a second etch stop layer pattern on the contact pads to cover sidewalls of the second interlayer insulating layer exposed in the contact holes; and forming a plurality of contact plugs to contact top surfaces of the contact pads.