Patent ID: 7682928
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A method of forming an isolation layer of a semiconductor device, comprising: forming a buffer insulating layer on a silicon substrate and patterning the buffer insulating layer; selectively etching the silicon substrate and forming trenches having a relatively large region and a relatively narrow region; depositing a first insulating layer and a second insulating layer sequentially over the silicon substrate; selectively removing the second insulating layer by a photolithography process and forming a chemical mechanical polishing (CMP) stop layer only above the relatively large trench region; planarizing the first insulating layer by a chemical mechanical polishing (CMP) process using the CMP stop layer; and removing all of the CMP stop layer and the buffer insulating layer and completing the isolation layer, wherein the first insulating layer is an oxide layer by a high density plasma chemical vapor deposition (HDP-CVD).