Patent ID: 9077373
Filing Date: 2015-07-07
Classification: H03M

Abstract:
1. An analog-to-digital (A/D) conversion apparatus comprising: a signal processor configured to process an analog input signal and including a plurality of circuit blocks connected in a loop so that an output of a final-stage circuit block of the plurality of circuit blocks is inputted to at least one of the plurality of circuit blocks except the final-stage circuit block; a quantizer configured to generate a quantization value by quantizing an output of at least one of the plurality of circuit blocks including the final-stage circuit block, and a controller configured to generate control signals for causing the signal processor and the quantizer to operate as a delta-sigma modulator in a delta-sigma mode or as a cyclic A/D converter in a cyclic mode by changing a connection condition in each of the plurality of circuit blocks, the controller configured to output an A/D conversion result of the analog input signal according to the quantization value, wherein each of the plurality of circuit blocks of the signal processor includes an operational amplifier, a first capacitor, a second capacitor, a third capacitor, a first switch section, a second switch section, and a third switch section, one end of each of the first capacitor, the second capacitor, the third capacitor is capable of being connected to an input terminal of the operational amplifier, the first switch section changes a connection destination of the first capacitor so that in the delta-sigma mode, the first capacitor forms a first sample circuit to sample and hold a preset first target input or forms an integrator circuit with the operational amplifier and the third capacitor and so that in the cyclic mode, the first capacitor is disconnected from the input terminal of the operational amplifier, the second switch section changes a connection destination of the second capacitor so that in the delta-sigma mode, the second capacitor is connected between the input terminal and an output terminal of the operational amplifier and so that in the cyclic mode, the second capacitor forms a second sample circuit to sample and hold a preset second target input or forms an amplification circuit with the operational amplifier and the third capacitor, the third switch section changes a connection destination of the third capacitor so that in the delta-sigma mode, the third capacitor forms the integrator circuit with the operational amplifier and the first capacitor and holds an output of the integrator circuit and so that in the cyclic mode, the third capacitor forms the amplifier circuit with the operational amplifier and the second capacitor and holds an output of the amplifier circuit, the one end of each of the second capacitor and the third capacitor is connected directly to the input terminal of the operational amplifier, an output, which is outputted from the operational amplifier of a first one of the plurality of circuit blocks and inputted to a second one of the plurality of circuit blocks connected to an output stage of the first one of the plurality of circuit blocks in the loop, is defined as an input-stage output, the analog input signal is inputted as the first target input to a predetermined one of the plurality of circuit blocks connected to an output stage of the final-stage circuit block in the loop, the input-stage output is inputted as the second target input to the predetermined one of the plurality of circuit blocks, and the input-stage output is inputted as both the first target input and the second target input to each of the plurality of circuit blocks except the predetermined one of the plurality of circuit blocks.