Patent ID: 6496413
Filing Date: 2002-12-17
Classification: G11C

Abstract:
A semiconductor device comprising:first memory blocks each having memory cells arranged in a matrix form; a first decoder for selectively activating said first memory blocks; at least one second memory block of substantially the same construction as said first memory block; a sense amplifier which is connected to, and shared by each of the first memory blocks and said at least one second memory block and which is configured to amplify data read out from a selected memory cell; a second decoder configured to select said second memory block; a defective block address storing section having a memory element configured to store a defective block address, wherein a readout operation of said defective block address storing section is effected at the turn-ON time of a power supply; and a block address comparing section configured to compare the defective block address stored in said defective block address storing section and block address information; wherein said first decoder which selects the first memory block in which a defective cell occurs is set into a non-selected state and said second decoder is set into a selected state when coincidence of the compared addresses is detected in said defective block address comparing section.