Patent ID: 6449681
Filing Date: 2002-09-10
Classification: G06F,G11C

Abstract:
A buffer access control circuit for updating an address when consecutively accessing an upper buffer and a lower buffer which form a buffer as an access destination, where the upper buffer and the lower buffer are assigned the same address, said buffer access control circuit comprising:a detection circuit section detecting whether or not the upper buffer and the lower buffer are consecutively specified as the access destination, by successively storing logic levels when the upper buffer or the lower buffer is specified as the access destination, based on a relationship in which a first logic level indicates a state where the access destination is specified and a second logic level indicates a state where the access destination is not specified, said first and second logic levels being complementary logic levels; and a modifying circuit modifying the relationship into a relationship in which the second logic level indicates the state where the access destination is specified and the first logic level indicates the state where the access destination is not specified, when said detection circuit detects that the upper buffer and the lower buffer are consecutively specified as the access destination.