Patent ID: 6119249
Filing Date: 2000-09-12
Classification: G11C

Abstract:
Method of testing a memory device including a plurality of blocks of memory cells and pre-charged wired-OR differential data line pairs, each of the differential data line pairs being coupled to a respective buffer that includes an output, the method comprising sequentially and recursively carrying out the steps of:simultaneously enabling said plurality of memory cell blocks;selecting a memory location within each of the enabled memory blocks;writing predetermined data to said selected memory location within each of said enabled memory blocks;reading, from said wired-OR differential pairs, said predetermined data from said selected address location from each of said enabled memory blocks in parallel; andtri-stating the output of each respective buffer that is coupled to a differential data line pair for which the read predetermined data indicates that both data lines of the pair have been pulled to an active state, the tri-stated output indicating at least one bad memory cell within at least one of the plurality of enabled blocks.