Patent ID: 8504805
Filing Date: 2013-08-06
Classification: G06F

Abstract:
1. An apparatus, comprising: a processor configured to enter an operating mode in response to receiving an indication of a dependency between a) a first floating-point instruction in a sequence of instructions having as a destination a first portion of a first of a plurality of logical registers, and b) a second, subsequent floating-point instruction in the sequence of instructions having as a source the first portion and a second portion of the first logical register, wherein the processor is configured to enter the operating mode by taking a trap flush, wherein the processor is configured to maintain a counter indicative of a number of single-precision-destination floating-point instructions committed since the processor entered the operating mode, and wherein the processor is configured to exit the operating mode in response to the counter satisfying a threshold; wherein the processor includes a first circuit configured to insert an instruction into the sequence of instructions when the processor is in the operating mode, wherein the first circuit is not configured to insert the instruction into the sequence of instructions when the processor is not in the operating mode, and wherein the inserted instruction is executable by the processor to move an aliased set of floating-point logical registers into a floating-point physical register, wherein the aliased set includes the destination of the first floating-point instruction, wherein the inserted instruction is inserted without modifying either the first floating-point instruction or the second floating-point instruction.