Patent ID: 6300652
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A memory cell configuration, comprising:a multiplicity of individual memory cells each including a selection transistor and a storage capacitor in a semiconductor layer structure;substantially parallel bit lines and substantially parallel word lines, said bit lines and said word lines extending transversely relative to one another;an insulating layer;at least said selection transistors being disposed below said insulating layer;said storage capacitors being disposed on said insulating layer;each of said storage capacitors including a column-shaped first electrode, a storage dielectric and a strip-shaped second electrode;said storage dielectric having ferroelectric or paraelectric material;said first electrode, said storage dielectric and said second electrode each being disposed next to one another above said insulating layer; andneighboring ones of said multiplicity of individual memory cells having neighboring first electrodes along a side of said strip-shaped second electrode, said neighboring first electrodes separated from each other only by said storage dielectric.