Patent ID: 6405296
Filing Date: 2002-06-11
Classification: G06F,G11C,Y02D

Abstract:
A memory device having an array of memory cells, the memory device comprising:a selection circuit, including a register to store a value, wherein the selection circuit generates a mode selection signal based on the value stored the register; a first buffer to receive an external signal and to output a buffered version of the external signal; a second buffer to receive a clock enable signal, wherein in response to the clock enable signal, a control signal enables the first buffer; a multiplexer coupled to the first buffer and the selection circuit, the multiplexer to select one of a plurality of clock signals in response to the mode selection signal, the plurality of clock signals including first and second clock signals; and an output buffer coupled to the multiplexer, and the first buffer, to output data in response to the buffered version of the external signal, wherein, the output buffer outputs data in response to transitions of the first clock signal when the mode selection signal is in a first state and the output buffer outputs the data in response to transitions of the second clock signal when the mode selection signal is in a second state.