Patent ID: 6482726
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method comprising:forming a gate dielectric layer above a substrate layer; forming a gate conductor layer above the gate dielectric layer; forming a first hard mask layer above the gate conductor layer; forming a second hard mask layer above the first hard mask layer; forming a trimmed photoresist mask above the second hard mask layer; forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension; forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension; and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.