Patent ID: 7689878
Filing Date: 2010-03-30
Classification: G11C

Abstract:
1. A method for testing an electronic circuit that includes a matrix of cells for receiving logic data, said matrix of cells being divided into a plurality of Z blocks each comprising n rows of cells, where n is an integer >1, each Z block is divided into a plurality of U sections, each including some of the n rows of the respective Z block, each U section is divided into a plurality of clusters, each including some of the rows of the respective U section, the method comprising: accessing each of said cells in said matrix by consecutively accessing cells in the same Z block until all n rows therein have been accessed, accessing each of said cells in said matrix includes consecutively accessing cells in the same U section until all rows therein have been accessed, accessing each of said cells in said matrix includes consecutively accessing and testing integrity of cells in the same cluster in a non-linear order until all rows therein have been accessed.