Patent ID: 8447929
Filing Date: 2013-05-21
Classification: G06F

Abstract:
1. A method for managing and controlling associativity of a microprocessor cache memory to a logical partition comprising: receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, wherein the unique partition identifiers are each associated with a logical processing partition executing on at least one core of the multi-core processors; responsive to translation of an memory cycle address resulting in a shared cache memory miss, identifying a position in a cache directory for data associated with the address, wherein the shared cache memory is multi-way set associative; responsive to the identifying of a position, associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; responsive to the associating of a new cache line entry, modifying the cache directory to reflect the association; responsive to the modifying the cache directory, caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor; responsive to a cache miss, comparing the registered partition identifiers of cores currently operating upon the shared cache memory; and responsive to the comparison determining that at least N different cores are operating on the shared cache: