Patent ID: 9195622
Filing Date: 2015-11-24
Classification: G06F,G11C

Abstract:
1. A method of performing memory operations, the method comprising: receiving a plurality of data blocks to be written to one or more memory banks among a plurality of memory banks, including receiving at least a first data block and a second data block, the plurality of memory banks including one or more primary memory banks and at least one additional memory bank; determining whether (i) the first data block and the second data block are addressed to respective different primary memory banks among the plurality of memory banks or (ii) the first data block and the second data block are both addressed to of the same primary memory bank in the plurality of memory banks; in response to determining that the first data block and the second data block are addressed to respective different primary memory banks among the plurality of memory banks, writing, in a single clock cycle, the first data block and the second data block to the respective different primary memory banks; and in response to determining that the first data block and the second data block are both addressed to the same primary memory bank in the plurality of memory banks, writing, in the single clock cycle, the first data block to the same primary memory bank and the second data block to the additional memory bank.