Patent ID: 8339830
Filing Date: 2012-12-25
Classification: G11C

Abstract:
1. A nonvolatile semiconductor storage comprising: memory cells, each of which is configured using a field effect transistor and includes n (n is an integer equal to or larger than 2) anti-fuse elements, one ends of which are connected in common; an internal potential generating circuit that generates a program voltage for breaking down a gate insulating film of the field effect transistor; a program voltage selection circuit that selects, out of the n anti-fuse elements, an anti-fuse element to which the program voltage is applied; a sense amplifier that is provided for each of the memory cells and determines, based on data stored in the n anti-fuse elements, three or more readout levels; a barrier transistor that is provided for each of the memory cells and protects the sense amplifier from the voltage for breaking down the gate insulating film; and a selection transistor that is provided for each of the memory cells and selects a memory cell to which the program voltage is applied.