Patent ID: 8456554
Filing Date: 2013-06-04
Classification: H03M,H04N

Abstract:
1. An integrated AD (analog-to-digital) converter comprising: a comparator that compares an input voltage with a reference voltage with a ramp waveform whose voltage value linearly changes with time; a high-bit counter that is triggered by inversion of an output signal of the comparator to start or stop an operation of counting, wherein the counting operation, after being started, counts once for every cycle of a main clock signal until stopped; a time quantizer that latches phase information of a plurality of clock signals, including the main clock signal, each clock signal having the same period as the main clock signal and having non-zero phase differences relative to each of the other clock signals, wherein the time quantizer latches the phase information at a timing at which the output signal of the comparator is inverted, and decodes a value of the latched phase information to thereby output bits with a resolution higher than a clock cycle of the main clock signal; and a regulating unit that synchronizes the output signal of the comparator with the main clock signal, and determines timings of starting and stopping the counting operation of the high-bit counter and a value for latching the phase information of the main clock signal based on a signal resulting from the synchronization.