Patent ID: 6380042
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A self-aligned contact process, comprising the steps of:providing a semiconductor substrate having at least two gate structures and a plurality of first ion-doped regions formed at opposite sides of the gate structures on the semiconductor substrate, each of the gate structures having a gate layer and a cap layer formed on the gate layer; forming a plurality of first sidewall spacers on the sidewalls of the gate structures respectively; forming a plurality of second ion-doped regions on the exposed first ion-doped regions respectively, the depth and concentration of the second ion-doped region being greater than the depth and concentration of the first ion-doped region; forming a first dielectric layer on the entire surface of the semiconductor substrate to fill the gap between adjacent first sidewall spacers; removing the topmost portion of the first sidewall spacers and part of the first dielectric layer to expose each cap layer of the gate structures; forming a plurality of second spacers on the exposed sidewalls of the cap layers respectively; forming a second dielectric layer on the entire surface of the semiconductor substrate to fill the gap between adjacent second sidewall spacers; and performing a dry etching process to remove the second dielectric layer and the first dielectric layer positioned between adjacent gate structures to expose the second ion-doped region so as to form a contact hole.