Patent ID: 6504419
Filing Date: 2003-01-07
Classification: H03K

Abstract:
A circuit for multiplexing a selected one of a plurality of input signals to an output conductor, comprising:(a) a plurality of input buffers each having an input terminal coupled to receive of the input signals, respectively, each input buffer having a low impedance output terminal; (b) switched bias current circuitry coupled to the input buffers for supplying an operating (+) bias current into a first bias terminal of one of the input buffers and sinking an operating (âˆ’) bias current from a second bias terminal of the input buffer to select one of the input buffers in response to a selection control signal and preventing flow of the operating (+) bias current and the operating (âˆ’) bias current in the remaining input buffers which are not presently selected; (c) an output buffer having an output coupled to the output conductor, an input, and first and second bias terminals; (d) a feedback resistor coupled between the output conductor and the low impedance output terminals of the input buffers; and (e) a first current mirror having a control input coupled to a third bias terminal of each of the input buffers, a first output coupled to the input of the output buffer, and a second output coupled to the first bias terminal of the output buffer, and a second current mirror having a control input coupled to a fourth bias terminal of each of the input buffers, a first output coupled to the input of the output buffer, and a second output coupled to the second bias terminal of the output buffer.