Patent ID: 7683434
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first and a second gate structure, each gate structure including a main body and a spacer; a high aspect ratio region, filled with a first dielectric, between the first and second gate structure; a bearing surface adjacent each gate structure within the high aspect ratio region for preventing cavitation of the first dielectric in the high aspect ratio region, wherein the bearing surface is inclined to the spacer of each gate structure and extends continuously upwards from a surface coplanar with the base of each gate structure terminating at a portion along the height of the spacer of each gate structure; a second dielectric located under each gate structure that partially fills an undercut thereof, wherein the second dielectric has a first surface that contacts a bottom surface of the spacer of each gate structure and a second surface that contacts the bearing surface; and a barrier layer deposited over each gate structure including respective bearing surfaces and the high aspect ratio region filled with the first dielectric that is between the gate structures.