Patent ID: 9142564
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A device structure formed on a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate of a first conductivity type, and buried dielectric layer between the semiconductor layer and the bulk substrate, the device structure comprising: a first back gate of the first conductivity type in the bulk substrate, the first back gate electrically coupled with the bulk substrate of the first conductivity type; a second back gate of a second conductivity type in the bulk substrate, the second back gate laterally adjacent to the first back gate; an overlapping region defined by spatial coincidence of a portion of the first back gate and a portion of the second back gate, the overlapping region configured to electrically couple the second back gate with the first back gate so that the second back gate is electrically coupled with the bulk substrate; and a damage region extending laterally across the overlapping region from the first back gate to the second back gate, the damage region cooperating with the overlapping region to provide a leakage current electrically coupling the second back gate with the first back gate.