Patent ID: 6664586
Filing Date: 2003-12-16
Classification: H01L

Abstract:
A memory device comprising:a memory substrate including a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer, wherein the memory cell area and the peripheral circuit area are formed on the substrate, the first dielectric layer is formed on the memory cell area and the peripheral circuit area, and the first metal layer is formed on the first dielectric layer; an insulating layer formed on the first dielectric layer not covered with the first metal layer; a shielding metal layer formed on the insulating layer over the memory cell area; a second dielectric layer formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer, and the first metal layer not covered with the shielding metal layer and the insulating layer; and a second metal layer formed on the second dielectric layer.