Patent ID: 7683692
Filing Date: 2010-03-23
Classification: G06F,H04J,H04L,Y02D

Abstract:
1. An apparatus comprising: a communication bus that comprises a clock conductor a first and second circuit coupled to the bus, each comprising a clock circuit and a driver circuit with an input coupled to the clock circuit and an output coupled to the clock conductor; at least one control circuit arranged to be responsive to a hand-over command from the communication bus for handing over clock control from the first circuit to the second circuit, the control circuit or circuits being arranged to cause the driver circuit of the first circuit to drive the clock conductor to a predetermined voltage level after a last clock period following the start of execution of the handover command and to continue driving the clock conductor to the predetermined voltage level for a first time-interval; cause the second circuit to start driving the clock conductor to the predetermined voltage level after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval, and subsequently to drive the clock conductor under control of the clock circuit of the second circuit; wherein the first time interval contains a first integer number P 1 of periods of a first clock signal of the first circuit and the second and third time interval contain a second and third integer number P 2 , P 3 of periods of a second clock signal of the second circuit, a duration corresponding to the second integer number P 2 equaling at least a pulse duration of the first clock signal, a duration corresponding to the first integer number P 1 equaling at least a duration corresponding to the second integer number P 2 plus one, a duration corresponding to the second plus third integer P 2 , P 3 equaling at least a duration corresponding to the first number P 1 plus one.