Patent ID: 6556498
Filing Date: 2003-04-29
Classification: G11C

Abstract:
An operation method of a static random access memory (SRAM) device, the SRAM device having a plurality of memory cells, each of the memory cells being periodically refreshed to retain valid data, the operation method comprising:receiving an access address and a refresh address for the SRAM device, the access address being used for accessing data stored in the SRAM device and the refresh address being used for periodically refreshing the memory cell in the SRAM; and detecting whether a transition pulse and a refresh pulse being generated, the transition pulse being generated by an address transition detector when a read/write operation is issued, the refresh pulse being generated in response to a refresh clock being in an active state, wherein if the transition pulse being generated before the refresh pulse being generated within a first time period, the access address being used to access data stored in the SRAM device at the time of the rising edge of the transition pulse, the refresh address being not to be used to refresh the memory cell of the SRAM device in accordance with the refresh address until at least the first period later after the rising edge of the transition pulse being issued, wherein the first time period is a time period sufficient enough to accomplish the read/write operation, if the refresh pulse being generated before the transition pulse being generated within a second time period, the refresh address being used to refresh the memory cells of the SRAM device in accordance with the refresh address at the time of the rising edge of the refresh pulse, the access address being not to be used to access data stored in the memory cell of the SRAM device in accordance with the access address until at least the second period later after the rising edge of the refresh pulse being issued, wherein the second time period is a time period sufficient enough to accomplish the refresh operation.