Patent ID: 9099477
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A three-dimensional integrated circuit comprising: a first semiconductor chip; and a second semiconductor chip stacked on the first semiconductor chip, wherein the first semiconductor chip is provided with (i) a transistor layer, (ii) a first layer, which is one of a first power supply wiring layer and a first ground wiring layer, the first power supply wiring layer having a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the first semiconductor chip, and (iii) a second layer, which is the other one of the first power supply wiring layer and the first ground wiring layer, wherein the first layer of the first semiconductor chip is located between (i) the transistor layer of the first semiconductor chip and (ii) the second layer of the first semiconductor chip, wherein the second semiconductor chip is provided with (i) a transistor layer, (ii) a first layer, which is one of a second power supply wiring layer and a second ground wiring layer, the second power supply wiring layer having a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the second semiconductor chip, and (iii) a second layer, which is the other one of the second power supply wiring layer and the second ground wiring layer, wherein the first layer of the second semiconductor chip is located between (i) the transistor layer of the second semiconductor chip and (ii) the second layer of the second semiconductor chip, wherein the first semiconductor chip is further provided with a third layer, which is one of a third power supply wiring layer and a third ground wiring layer, the third layer of the first semiconductor chip being located (i) on a surface of the first semiconductor chip facing the second semiconductor chip and (ii) between the second layer of the first semiconductor chip and second semiconductor chip.