Patent ID: 6358795
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A method of fabricating a capacitor on a memory device, the method comprising:providing a substrate, wherein the substrate has conductive structures with a cap layer on top; forming a dielectric layer over the substrate and the conductive structures; patterning the dielectric layer to form an opening between the conductive structures, wherein the opening exposes a portion of the substrate between the conductive structures and a side surface of the conductive structures; filling a conductive plug into the opening; forming a dielectric block on the conductive plug; forming a conductive spacer on a sidewall of dielectric block, wherein the conductive spacer has electric contact to the conductive plug; removing the dielectric block; forming a hemi-spherical grain (HSG) conductive layer over a topographic surface over the substrate; forming a dielectric spacer on a sidewall of the conductive spacer to cover a portion of the HSG conductive layer, wherein the dielectric spacer includes a material to have different etching selectivity to the dielectric layer; removing the HSG conductive layer using the dielectric spacer as an etching mask, wherein the dielectric layer and the conductive plug are exposed; removing dielectric spacer with an etching ratio to the dielectric layer; forming a capacitor dielectric layer over the substrate; and forming a conductive layer over the substrate.