Patent ID: 7359244
Filing Date: 2008-04-15
Classification: G11C

Abstract:
1. A non-volatile memory device comprising: a first memory bank including a plurality of first memory cells and a first data register; a second memory bank including a plurality of second memory cells and a second data register; and a data buffer to temporarily hold data which is transmitted to the first or second memory bank and which is logically addressed, wherein a capacity of the data buffer is equal to or larger than a sum of capacities of the first and second data registers: an address buffer coupled to the first and second memory banks, wherein data transferred from the data buffer to the first data register is written into the plurality of first memory cells, wherein data transferred from the data buffer to the second data register is written into the plurality of second, wherein, while the plurality of first memory cells are written with data held in the first data register, the non-volatile memory device is adapted so that data inputted from external of the non-volatile memory device to the data buffer is transmitted to the second data register, wherein, while the plurality of second memory cells are written with data held in the second data register, the non-volatile memory device is adapted so that data inputted from external of the non-volatile memory device to the data buffer is transmitted to the first data register, and wherein the first memory bank is adapted to operate independently of the second memory bank.