Patent ID: 6308229
Filing Date: 2001-10-23
Classification: G06F

Abstract:
A First-In-First-Out (FIFO) circuit comprising:a plurality of registers that operate asynchronously aligned to define a data path from a first register of said plurality of registers to a last register of said plurality of registers;said first register capable of connecting to an at least partially synchronous upstream circuit; andsaid last register capable of connecting to an at least partially synchronous downstream circuit;each of said plurality of registers comprising:a plurality of first threshold gates having a first predetermined number of first inputs and a threshold value equal to said first predetermined number;a plurality of second threshold gates having a second predetermined number of second inputs and a threshold value less than said second predetermined number;a third threshold gate having a number of inputs and a threshold number equal to a number of said plurality of second threshold gates;each of said first plurality of threshold gates being configured to receive data on at least one of the first inputs and an acknowledge signal from a downstream circuit element on another of the first inputs, an output of each of the said first threshold gates being connected to an output of the respective asynchronous register and one of the second inputs;each of said second threshold gates configured to receive an output signal from at least two of said first threshold gates, an output of each of the second threshold gates being connected to said third threshold gate; andan output of the third threshold gate representing whether the register is ready to accept a meaningful or non-meaningful signal;wherein said last register will output information in a FIFO format consistent with the input of the information into said first register.