Patent ID: 6265742
Filing Date: 2001-07-24
Classification: H01L

Abstract:
An array of memory cells with each cell having a transistor in series with a capacitor, the array of memory cells comprising:a substrate whose top surface includes a plurality of active areas each separated from one another by a shallow dielectric isolation trench, each active area including a central bulk portion that includes a surface layer of one conductivity type suitable for use as a source of a transistor and a directly underlying portion of an opposite conductivity;separate first and second epitaxial regions of the opposite conductivity type on adjacent opposite sides of the underlying portion of each central bulk portion;separate gate dielectric layers over surface portions of the epitaxial regions spaced from the central bulk portion;polysilicon filled trenches doped to be of the one conductivity type underlying each epitaxially grown regions for providing a drain for the transistor and a portion for use as a storage node of the capacitor; anda dielectric layer suitable for use as a dielectric of the capacitor between the polysilicon fill of each trench and bulk material of the substrate.