Patent ID: 8984043
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A method comprising: decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein the set of vectors comprises a first vector, a second vector, and a third vector, wherein each vector represents an m-by-m matrix of data elements and m is greater than one, wherein the m-by-m matrix operation is a multiply-add operation; issuing the single instruction for execution by an execution unit in the processor device; and responsive to the execution of the single instruction, generating a fourth vector, wherein the fourth vector is stored separately from the first, second, and third vectors, wherein the fourth vector represents an m-by-m matrix of data elements, wherein the execution of the single instruction is performed by m sub-circuits, wherein each of the sub-circuits includes a plurality of multipliers and adders connected in a series, output of the last of the series connecting to a plurality of delay lines to generate respective portion of the fourth vector.