Patent ID: 6961260
Filing Date: 2005-11-01
Classification: G11C

Abstract:
1. A semiconductor storage circuit comprising: a memory cell array in which memory cell sub arrays each including a plurality of memory cells are arranged in an array along a bit line direction corresponding to a column direction and a word line direction corresponding to a row direction, data access circuit sections each of which is provided correspondingly to a column of said memory cell sub arrays arranged along the bit line direction and includes a data access circuit for making data accesses to memory cells of one or more of said memory cell sub arrays belonging to said column and a first driver circuit for driving said data access circuit, and a control circuit section for controlling said data access circuit through said first driver circuit, wherein said data access circuit sections are disposed along the word line direction at a pitch equal to a pitch at which one or more of said memory cell sub arrays are disposed along the word line direction.