Patent ID: 7765342
Filing Date: 2010-07-27
Classification: G06F

Abstract:
1. A computer-implemented method of optimizing processors, comprising: providing at least one instruction register file; identifying a plurality of frequently-used instructions; storing at least a portion of the identified frequently-used instructions as register instructions in the instruction register file; specifying a respective first identifier for identifying each of the register instructions stored within the instruction register file; and retrieving at least one packed instruction from an instruction cache storing packed instructions and non-packed instructions, wherein each packed instruction includes respective one or more first identifiers identifying a respective one of the register instructions stored in the instruction register file, wherein the respective one or more first identifiers are sequenced in each packed instruction according to a desired scheduling order, wherein at least one of the packed instructions includes a plurality of respective first identifiers, wherein the stored packed instructions and the non-packed instructions in the instruction cache are all of a same bit size.