Patent ID: 9015508
Filing Date: 2015-04-21
Classification: G06F,H03L

Abstract:
1. A semiconductor device comprising: a first region which receives power from a first power supply source line only during a power-supply state and which is configured to return to the power-supply state after having transited from the power-supply state to a power-down state; a second region which receives power from a second power supply source line during both the power-supply state and the power-down state of the first region; and an oscillator which generates a first clock signal supplied to the first region, wherein the first region includes a PLL circuit having a PLL normal-oscillation mode for generating a second clock signal which synchronizes with the first clock signal generated in the oscillator, and a PLL self-oscillation mode for generating a third clock signal which is asynchronous with the first clock signal, and the second region includes an information holding unit configured to store information which can distinguish whether the operation mode of the PLL circuit when the first region transits from the power-supply state to the power-down state is the PLL normal-oscillation mode or the PLL self-oscillation mode, wherein the second region includes a control unit which determines, according to the information held in the information holding unit, the operation mode of the PLL circuit when the first region has returned from the power-down state to the power-supply state, wherein the control unit determines the operation mode of the PLL circuit so that the operation mode of the PLL circuit when the first region transits from the power-supply state to the power-down state is the same as that of the PLL circuit when the first region returns from the power-down state to the power-supply state, wherein the control unit stops the oscillator when the PLL circuit is regarded to be in the PLL self-oscillation mode, wherein the oscillator include as oscillation stop detection circuit which can detect the stop of oscillation, and wherein the second region includes a register in which whether of not to enable an oscillation stop detection function by the oscillation stop detection circuit can be set, and a logic gate for disabling, regardless of the setting in the register, the oscillation stop detection function by the oscillation stop detection circuit when the PLL circuit is regards to be in the PLL self-oscillation mode by the control unit.