Patent ID: 9146868
Filing Date: 2015-09-29
Classification: G06F

Abstract:
1. A computer-implemented method for eliminating inconsistencies between backing stores and caches, at least a portion of the method being performed by a computing device comprising at least one processor, the method comprising: superimposing a synchronization marker on at least one write operation in a cache that queues write operations destined for a backing store, the synchronization marker bifurcating the write operations queued in the cache into: superimposing a corresponding synchronization marker on copies, in the backing store, of write operations from the at least one write operation, the synchronization marker and the corresponding synchronization marker representing a most recent synchronization point between the backing store and the cache; detecting at least one inconsistency between the backing store and the cache that queues write operations destined for the backing store; in response to detecting the inconsistency between the backing store and the cache that queues the write operations destined for the backing store: in response to identifying the additional subset of additional write operations based at least in part on the synchronization marker: