Patent ID: 9224484
Filing Date: 2015-12-29
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array having memory strings arranged therein, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines connected to control gates of the memory cells; and a control circuit operative to execute a write operation, during the write operation, the control circuit being operative to apply a program voltage to a selected word line connected to a selected memory cell, and apply a first write pass voltage to a first non-selected word line including a word line adjacent to the selected word line, the control circuit being operative to raise the program voltage to a first program voltage value at a first timing, and then raise the program voltage to a second program voltage value at a second timing later than the first timing, the control circuit being operative to raise the first write pass voltage to a first pass voltage value at a third timing, and then raise the first write pass voltage to a second pass voltage value at a fourth timing later than the third timing, the first program voltage value is higher than the second pass voltage value, the second timing and the fourth timing being set at substantially the same, and difference between the first program voltage value and the second program voltage value being smaller than difference between the first pass voltage value and the second pass voltage value.