Patent ID: 6351427
Filing Date: 2002-02-26
Classification: G11C

Abstract:
A random access memory, comprising:a plurality of memory banks; a plurality of local input/output (I/O) buses, each local I/O bus being associated with one of the memory banks; a global read bus; a global write bus; a plurality of local read/write circuits, each local read/write circuit being associated with one of the local I/O buses, and including: a plurality of write paths coupling the global write bus to the associated local I/O bus, each write path including an input data latch, and a plurality of read paths coupling the associated local I/O bus to the global read bus; and control circuitry for issuing a plurality of control signals, wherein in response to the plurality of control signals write data is written into a first one of the plurality of memory banks while at a same time read data is read out from a second one of the plurality of memory banks, wherein the first one of the plurality of memory banks is different than the second one of the plurality of memory banks.