Patent ID: 6967161
Filing Date: 2005-11-22
Classification: H01L

Abstract:
1. A method for forming bit line and storage node contacts for a dynamic random access device, the method comprising: providing a substrate, the substrate having a bit line region and a capacitor contact region; forming at least a first gate structure and a second gate structure overlying the substrate, the first gate structure including an overlying first cap, the second gate structure including an overlying second cap, the first gate structure being spaced by the bit line region to the second gate structure, the capacitor contact region being coupled to the first gate structure; forming a conformal dielectric layer overlying the first gate structure, the second gate structure, the bit line region, and the capacitor contact region; forming an interlayer dielectric material overlying the conformal dielectric layer; planarizing the interlayer dielectric material; forming a masking layer overlying the planarized interlayer dielectric material; exposing a continuous common region within a portion of the planarized interlayer dielectric material overlying a portion of the first gate structure, a portion of the second gate structure, a portion of the bit line region, and a portion of the capacitor contact region; performing a first etching process to remove the exposed portion of the planarized interlayer dielectric layer; performing a second etching process to remove a portion of the conformal dielectric layer on the bit line region, a portion of the conformal dielectric layer on the capacitor contact region; using other portions of the conformal dielectric layer as a mask to prevent a portion of the first gate structure and a portion of the second gate structure from being exposed during the second etching process; depositing a polysilicon fill material within the continuous common region and overlying the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to cover portions of the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to a predetermined thickness; planarizing the polysilicon fill material to reduce the predetermined thickness and to simultaneously reduce a thickness of a portion of the interlayer dielectric material; continuing the planarization of the polysilicon fill material and the interlayer dielectric material; and exposing a portion of the first gate structure and a portion of the second gate structure while leaving portions of the polysilicon fill material on the portion of the capacitor contact region and the portion of the bit line region; whereupon the other portion of the conformal dielectric layer prevent the polysilicon fill material from coming in physical contact with either at least the first gate structure or at least the second gate structure; and whereupon the polysilicon fill material on the portion of the capacitor contact region is isolated from the polysilicon fill material on the portion of the bit line region.