Patent ID: 6908844
Filing Date: 2005-06-21
Classification: H01L

Abstract:
1. A method for fabricating a metallization arrangement for a semiconductor structure, said method comprising: providing a first metallization plane on said semiconductor structure; providing a first intermediate dielectric on said first metallization plane, said first intermediate dielectric having a first dielectric constant; providing a liner layer made of a dielectric material on said first intermediate dielectric, said liner having a second dielectric constant that is greater than the first dielectric constant; providing via holes in said first intermediate dielectric and said liner layer, said via holes being filled with a conductive material, thereby completing a first resulting structure; providing a second metallization plane on said first resulting structure, said liner layer acting as a diffusion barrier for the second metallization plane; patterning first and second interconnects in said second metallization plane thereby forming an interspace between said first and second interconnects; and completely interrupting said liner layer in said interspace between said first interconnect and said second interconnect such that said liner layer is removed everywhere that the second metallization plane is removed, in order to prevent capacitive coupling between said first and second interconnects.