Patent ID: 7960233
Filing Date: 2011-06-14
Classification: H01L,H03K

Abstract:
1. A method for fabricating a trenched vertical semiconductor power device comprising: forming a plurality of trenched gates by opening a plurality of trenches and filling the trenches with a first gate-conductive layer; depositing an inter-dielectric layer on top of said first gate-conductive layer; depositing a second gate-conductive layer on top of said inter-dielectric layer and patterning said second gate-conductive layer as a plurality of discrete segments each having a segment width approximately the same as a width of each of said trenched gates and having a cap shape with a top segment extending over substantially the width of each of said trenched gates above said inter-dielectric layer above said trenched gate and each of said conductive segments extends downwardly from both ends of the top segments and then outwardly to a horizontal location slightly beyond edges of each of said trenched gates on both ends; whereby forming said discrete segments to couple with said first gate-conductive layer over said inter-dielectric layer to constitute a capacitor.