Patent ID: 7017101
Filing Date: 2006-03-21
Classification: G11B,G11C,H04N

Abstract:
1. A method for generating a sync code of ECC blocks, comprising: generating two small ECC blocks, each one of small ECC blocks having a plurality of sectors, each one of the sectors having a plurality of rows, one of the rows in each one of the sectors being parity of outer-code information, other rows in each one of the sectors having data portion and parity of inner-code information, and each of the small ECC blocks including data which are to be interleaved between the small ECC blocks, modulating the small ECC blocks and adding the sync code to a header portion of each one of the sync frames corresponding to the rows; arranging a fixed code and a variable code in the sync code of 24 bit numbers; setting the fixed code to sync position detecting code, such that the fixed code includes a part having twelve consecutive “0”s continue and a part having the bit sequence “1001”; setting the variable code to have a bit for depressing a DC component, wherein the variable code is set to a variable code pattern selected from “00100*”, “00010*” and “00*010”, where * is a bit for depressing DC component.