Patent ID: 6292915
Filing Date: 2001-09-18
Classification: G01R

Abstract:
A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising:a first step of specifying as an easily testable circuit structure, an n-fold line-up structure in which paths between an arbitrary pair of a register of the circuit and a primary output or a pseudo-primary output have n or less sorts of sequential depths, where n is a natural number, and specifying a value of n; anda second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.