Patent ID: 7299399
Filing Date: 2007-11-20
Classification: G06F

Abstract:
1. An apparatus for parallelly processing data and ECC, said apparatus being adapted to be coupled to an external memory, said apparatus comprising: a microprocessor; an auxiliary control circuit coupled to said microprocessor; a direct memory access unit, coupled to said microprocessor for accessing said external memory; a first-in-first-out (FIFO) memory, coupled to said direct memory access unit; a first ECC calculation unit, coupled to said direct memory access unit and said auxiliary control circuit for calculating a first syndrome based on a first data and an associated first ECC; a second ECC calculation unit, coupled to said direct memory access unit and said auxiliary control circuit; and an error correction unit, coupled to said first ECC calculation unit, said auxiliary control circuit, said second ECC calculation unit, and said FIFO memory; wherein said FIFO memory receives a second data, and said second ECC calculation unit calculates a second syndrome based on said second data and an associated second ECC, while said error correction unit is correcting said first data in said FIFO memory according to said first syndrome.