Patent ID: 7999833
Filing Date: 2011-08-16
Classification: G09G

Abstract:
1. A system comprising: a data processing unit receiving a series of pixel data streams, each pixel data stream comprising multiple data bits representing an image pixel, the data processing unit receiving the series of pixel data streams and outputting a series of bit plane data streams, each bit plane data stream representing a data bit of a common significance from a plurality of image pixels; a memory cell array receiving the bit plane data, wherein a row of said array comprises a first and second subset, each subset having one or more memory cells; a first wordline and a second wordline, wherein the first wordline is connected to the first subset memory cells, and the second wordline is connected to the second subset memory cells; a first set of data to be loaded into the first subset of memory cells that are activated through the first wordline, wherein the first set of data is consecutively stored in a first region of a storage medium; and a second set of data to be loaded into the second subset of memory cells that are activated through the second wordline, wherein the second set of data is consecutively stored in a second region of the storage medium.