Patent ID: 7609083
Filing Date: 2009-10-27
Classification: G06F

Abstract:
1. A semiconductor integrated circuit device, comprising: a first large scale integrated circuit including a plurality of first logical blocks; a programmable second large scale integrated circuit connected with the first large scale integrated circuit and including a plurality of second logical blocks; a memory storing data for achieving the purposes of the first logical blocks; and a control unit that, when an error is detected in any of the first logical blocks during an operation of the first large scale integrated circuit, writes the data for the faulty first logical block stored in the memory to one of the second logical blocks in operating status, in which the control unit continues to operate, and uses the one of the second logical blocks in place of the faulty first logical block in the operating status, in which the control unit continues to operate, wherein the first large scale integrated circuit checks for an error in the first logical blocks, and, if the error is detected, issues an interruption request to the control unit, the control unit receives the interruption request, and obtains error information from a register in the first large scale integrated circuit, and analyzes the error information, the error information including an identifier (ID) of a faulty first logical block as well as content of the error, the control unit, if the faulty first logical block cannot be replaced with the programmable second large scale integrated circuit, sends a normal error handling command to the first large scale integrated circuit for closing a relevant path of the faulty first logical block, the first large scale integrated circuit, if receives the normal error handling command, closes the relevant path of the faulty first logical block, the control unit, if the faulty first logical block can be replaced with the programmable second large scale integrated circuit, finds out which logical block has the error, based on analyzing the error information, and sends an address of the faulty first logical block in a location in the memory and a command for causing the programmable second large scale integrated circuit to read implementation data from the memory, the programmable second large scale integrated circuit, if receives the address of the faulty first logical block in the location in the memory, and the command, reads the implementation data from the address of the location in the memory, and implements functions of the faulty first logical block in the one of the second logical blocks in the programmable second large scale integrated circuit, and reports completion of the implementation, the control unit, if receives the completion of the implementation, issues to the first large scale integrated circuit a command for causing the first large scale integrated circuit to replace the faulty first logical block with the one of the second logical blocks in the programmable second large scale integrated circuit and to switch the relevant path of the faulty first logical block to the one of the second logical blocks in the programmable second large scale integrated circuit, the first large scale integrated circuit, if receives the command for causing to replace and switch, replaces the faulty first logical block with the one of the second logical blocks in the programmable second large scale integrated circuit and switches the relevant path of the faulty first logical block to the one of the second logical blocks in the programmable second large scale integrated circuit, the control unit, after the replacing and the switching, issues a command to the first large scale integrated circuit for causing the first large scale integrated circuit to conduct a self-test, the self-test checks whether the error is a hard error or a soft error, which corrupts data, and the first large scale integrated circuit executes the self-test and, if the error is the soft error, stops using the one of the second logical blocks in the programmable second large scale integrated circuit and adapting using the fault first logical block, and, if the error is the hard error, continues using the one of the second logical blocks in the programmable second large scale integrated circuit.