Patent ID: 6469337
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A semiconductor memory device comprising:an interlayer insulation film; cylindrical lower electrodes formed within the interlayer insulation; capacitive insulating films formed at the inner surfaces of the lower electrodes; upper electrodes formed so as to oppose the lower electrodes sandwiching the capacitive insulating films; cylindrical grooves formed within the interlayer insulation film; electric conductive layers formed at the inner surfaces of the grooves; upper electrode extending parts connecting the upper electrodes and electric conductive layers; upper electrode contacts formed at the interlayer insulation film and physically connected to the electric conductive layers at only the bottoms of the grooves wherein the upper electrode contacts extending into the grooves more than one half of the depths of the grooves; and upper electrode wiring formed on the insulation film and connected of upper electrode contacts.