Patent ID: 6088763
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A content-addressable memory comprising:address storage for storing each of a plurality of address is association a respective one of a plurality of tags;an input circuit for receiving a first number and a second number, wherein said first and second numbers are utilized to access said address storage;a logic circuit, coupled to said input circuit, for determining whether or not there is a match between one of said plurality of tags and said first and second numbers in accordance with a mismatch expression, wherein said mismatch expression of a bit i isZ.sup.i =(K.sub.i .multidot.X.sub.b.sup.i)V(K.sub.i .multidot.X.sub.a.sup.i)V(K.sub.i .sym.K.sub.i+1).multidot.Y.sub.b.sup.i V(K.sub.i .sym.K.sub.i+1).multidot.Y.sub.a.sup.i,where ##EQU6## where A.sup.i is said first number, B.sup.i is said second number, and K.sup.i is any one of said plurality of tags; andan output circuit, coupled to said logic circuit, for supplying an address associated with a tag which matches said first and second numbers in accordance with said mismatch expression.