Patent ID: 8319873
Filing Date: 2012-11-27
Classification: H04N

Abstract:
1. A solid-state imaging device comprising: a photodiode array having a plurality of photodiodes each making photoelectric conversion, which are arrayed in rows and columns; a plurality of read transistors provided in one-to-one correspondence with the plurality of photodiodes, making a plurality of sets each comprised of four photodiodes of the plurality of photodiodes and four read transistors of the plurality of the read transistors coupled to the four photodiodes, respectively, and placed adjacent to each other in a direction of the rows and in a direction of the columns, and each of plurality of read transistors having one terminal and the other terminal of a current path, and a gate, and the one terminal of the current path being connected to a corresponding one of the photodiodes, the other terminal of the current path of any one of the four read transistors being connected in common to a first node, the first node being in a floating-state; a plurality of read control lines extended in the direction of the rows to which the four read transistors are respectively and correspondingly connected through the gate of each of the four read transistors, and independently supplied with a read signal; a plurality of vertical signal lines configured to output signals photoelectrically converted by two photodiodes of the plurality of photodiodes included in one of the sets and adjacent in the direction of the rows for an independent period within one horizontal blanking period of image scanning; a plurality of column select circuits connected to the vertical signal lines, respectively, and each selecting signals of a corresponding one of the vertical signal lines to output two signals, each of the column select circuits selecting signals of the corresponding one of the vertical signal lines to output the two signals within the one horizontal blanking period of the image scanning; and a plurality of pairs of correlated double sampling circuits respectively provided for each of the vertical signal lines, the pair of correlated double sampling circuits receiving the two signals from a corresponding one of the column select circuits, each of the correlated double sampling circuits obtaining a difference between a reference signal level which is held first and a read signal level captured later, and holding the obtained difference.