Patent ID: 6557099
Filing Date: 2003-04-29
Classification: G06F

Abstract:
A multiprocessor system in which a plurality of processor systems including processors assigned with unique processor numbers are interconnected by a processor connection facility, each of said plurality of processor systems comprising:first storage means for storing a number of a failing processor among said processors; first notice acceptance means for accepting through said processor connection facility a first notice of the failing processor number of another processor and writing said failing processor number to said first storage means; second notice acceptance means for accepting a second notice of initialization from another processor system through said processor connection facility to initialize own processor; notice means for issuing a third notice of the initialization to all other processor systems through said processor connection facility; system control processor analysis means for determining, on the basis of said failing processor number stored in said first storage means, a system control processor from among the normally operating processors; and system restart control means for instructing said notice means to issue said third notice and initializing own processor if own processor matches said system control processor determined by said system control processor analysis means when system restart has been determined to be performed on the basis of said failing processor number stored in said first storage means.