Patent ID: 8200878
Filing Date: 2012-06-12
Classification: G06F,G11C,Y02D

Abstract:
1. A multi-processor device comprising, over a single semiconductor chip: a plurality of processors including a plurality of a first type of processors and a plurality of a second type of processors, each said first type of processor having a first architecture, and each said second type of processor having a second architecture which is different from the first architecture of said first type of processor; a first bus to which the plurality of the first type of processors is coupled; a second bus to which the plurality of the second type of processors is coupled; a first external bus interface to which the first bus is coupled; a second external bus interface to which the second bus is coupled; and a secondary cache over the single semiconductor chip that couples the first bus and the second bus to each other, wherein said first bus has a first maximum operating frequency, and said second bus has a second maximum operating frequency different from said first maximum operating frequency, wherein, in plan view, the first external bus interface is disposed at a first edge of the single semiconductor chip and the second external bus interface is disposed at a second edge of the single semiconductor chip different from said first edge, wherein said secondary cache is located between the first bus and the first external bus interface, or between the second bus and the second external bus interface, and wherein the plurality of the first type of processors and the plurality of the second type of processors are disposed separately in a layout region which includes the first bus and the plurality of the first type of processors and a layout region which includes the second bus and the plurality of the second type of processors, over the single semiconductor chip in plan view.