Patent ID: 7512205
Filing Date: 2009-03-31
Classification: H03C,H03L

Abstract:
1. A method for providing a clock frequency using a single stage phase locked loop (PLL) circuit, the method comprising: determining a desired rate; determining a granularity value corresponding to a range of clock frequencies that includes the desired rate; determining an unmodulated rate and a modulated rate based on the desired rate and the granularity value; determining a modulation schedule comprising specified output cycles of the single stage PLL circuit, wherein the modulation schedule is based on the granularity value and a difference between the modulated and unmodulated rates; and modulating, by a modulated feedback divider, between the unmodulated rate and the modulated rate as input to the single stage PLL based on the modulation schedule over a period of time, wherein an output rate of the single stage PLL circuit is substantially equal to the desired rate over the period of time.