Patent ID: 7420276
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A semiconductor chip connected to a wirebond interconnect, comprising: a silicon substrate; a transistor in or on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a first contact pad over said silicon substrate, wherein said first contact pad has a top surface with a first region and a second region, wherein said second region surrounds said first region; a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein said passivation layer has a thickness greater than that of said dielectric layer, wherein a first opening in said passivation layer is over said first region and exposes said first region, wherein said first opening has a size between 0.1 and 50 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer; a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region and exposes said first region, and wherein said polymer layer has a thickness between 2 and 50 μm, greater than that of said dielectric layer and greater than that of said passivation layer; a second contact pad connected to said wirebond interconnect, wherein said second contact pad comprises an electroplated gold layer with a thickness between 2 and 100 μm, wherein said second contact pad is connected to said first contact pad through said first and second openings, and wherein the positions of said first and second contact pads from a top perspective view are different; and a signal interconnect on said polymer layer, wherein said second contact pad is connected to said first contact pad through said signal interconnect.