Patent ID: 6240508
Filing Date: 2001-05-29
Classification: G06F

Abstract:
A central processing unit capable of pipelined macroinstruction execution for a computer, comprising:an instruction unit for parsing and decoding instructions, and for generating memory read requests for operands specified in said instructions;an execution unit for executing said instructions, and for generating memory read requests incident to one type of said instructions in which operand reads for microcode branch decisions are not performed at instruction decode;a specifier-queue for temporarily storing said memory read requests generated in said instruction unit, and for issuing the contents of said specifier-queue at an output in sequential order in response to a first command;wherein the instruction unit loads into the specifier-queue a stop-command when said instruction unit parses and decodes an instruction of said one type of said instructions;wherein said execution unit generates a start-command when said execution unit has completed generating said memory requests incident to said instruction of said one type of said instructions; anda specifier-queue synchronization counter coupled to the start-command from the execution unit, and further coupled to the output of the specifier-queue, wherein the specifier-queue synchronization counter blocks assertion of the first command to the specifier-queue when the number of said stop-commands issued by said specifier-queue is greater than the number of the start-commands generated by the execution unit.