Patent ID: 8627174
Filing Date: 2014-01-07
Classification: H04L

Abstract:
1. A memory device, comprising: a plurality of parallel data transmission paths each of which transmit a sequence of unit intervals of data; an error correction (EC) control transmission path which transmits error correction codes; a data driver which is responsive to a read/write command, to drive the data transmitted on the data transmission paths, the data driver operating at a first latency from receipt of the read/write command to transmission of the data on the data transmission paths; an EC driver which drives the error correction codes transmitted on the EC transmission path, the EC driver operating at a second latency defined by a number of the unit intervals of the data transmitted on the data transmission paths prior to transmission of a corresponding error correction code on the EC transmission path; and an EC latency controller which variably controls the second latency based on a transmission frequency of the data on the data transmission paths, wherein the EC latency controller is responsive to at least one of an externally supplied signal or a mode register set (MRS).