Patent ID: 8410556
Filing Date: 2013-04-02
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; an n-type semiconductor region and a p-type semiconductor region provided on the semiconductor substrate to be insulated from each other; a p-channel MIS transistor formed on the n-type semiconductor region; and an n-channel MIS transistor formed on the p-type semiconductor region, the p-channel MIS transistor including: first source/drain regions provided opposite to each other on the n-type semiconductor region; a first gate insulating film formed on the n-type semiconductor region between the first source/drain regions; a first lower metal layer formed on the first gate insulating film and containing a first nonmetallic element; and a first upper metal layer formed on the first lower metal layer and containing at least one metallic element belonging to groups IIA and IIIA, the n-channel MIS transistor including: second source/drain regions provided opposite to each other on the p-type semiconductor region; a second gate insulating film formed on the p-type semiconductor region between the second source/drain regions; a second lower metal layer formed on the second gate insulating film and containing a second nonmetallic element; and a second upper metal layer formed on the second lower metal layer and substantially having the same composition as the first upper metal layer, wherein a first product (N the density of the at least one metallic element contained in the first gate insulating film is lower than the density of the at least one metallic element contained in the second gate insulating film.