Patent ID: 6835615
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A method of manufacturing a capacitor and an MOS transistor comprising:forming an active region, and a device isolation region including a field oxide film, on a semiconductor substrate; forming a trench in the active region; forming a gate oxide film in the trench; depositing a polycrystalline silicon layer on the gate oxide film and the field oxide film; forming a mask on the polycrystalline silicon layer over the field oxide film; etching a part of the polycrystalline silicon layer using the mask so as to simultaneously form a lower electrode of the capacitor on the field oxide film and a buried gate electrode of the MOS transistor in the trench; forming an insulating film to cover the lower electrode and the buried gate electrode; planarizing the insulating film by an etch back method to leave the insulating film on the lower electrode of the capacitor; and forming an upper electrode on the planarized insulating film over the lower electrode.