Patent ID: 6314048
Filing Date: 2001-11-06
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory array having a plurality of memory cells arranged in rows and columns and divided into a plurality of memory blocks in a row direction;a plurality of main word lines each corresponding to the memory cells on a prescribed number of rows of said memory array and shared by said plurality of memory blocks;a plurality of sub word lines arranged corresponding to rows of the memory cells of the memory blocks and each connected to the memory cells of a corresponding row;a main word line selection circuit for selecting a main word line arranged corresponding to an addressed row of said plurality of main word lines in accordance with a first address signal bit;a plurality of sub decode circuits arranged corresponding to said plurality of memory blocks and each decoding a second address signal bit and generating a sub word line designation signal designating a row of a set of said prescribed number of rows in accordance with a decoding result, each of the sub decode circuits including a changing circuit for changing a correspondence relationship between a decode signal representing the decoding result and the sub word line designation signal in accordance with a page geometry designation signal; anda plurality of sub word line drive circuits arranged corresponding to respective sub word lines for driving said respective sub word lines into a selected state in accordance with said sub word line designation signal and signals on corresponding main word lines.