Patent ID: 9166613
Filing Date: 2015-10-20
Classification: H03M,H04N

Abstract:
1. An A/D conversion circuit comprising: a reference signal generation portion that generates a reference signal that increases or decreases with lapse of time from a predetermined start timing; a comparison portion that compares an analog signal with the reference signal, and outputs a comparison signal at an end timing at which the reference signal satisfies a predetermined condition with respect to the analog signal; a delay portion that outputs the comparison signal that is delayed; a phase shift portion that outputs a plurality of clock signals having different phases from one another in response to a time change from the start timing; a latch portion including a plurality of latch units, each of the plurality of latch units latching a corresponding one of the plurality of clock signals at a timing when the comparison signal is outputted from the delay portion; a count portion wherein, any one of the plurality of latch units being defined as a count latch unit and the latch units other than the count latch unit being defined as non-count latch units, the count portion counts a clock signal that is latched by the count latch unit; and an operation portion that generates a digital signal according to a signal held in the latch portion, wherein each of the plurality of latch units includes a first logic element having a first input terminal and a second input terminal, wherein the first input terminal of the first logic element receives the corresponding one of the plurality of clock signals, wherein the second input terminal of the first logic element receives an enable signal, wherein each of the plurality of latch units does not latch the corresponding one of the plurality of clock signals when the enable signal is not received, wherein a second logic element outputs the enable signal at an end timing that is based on the comparison signal; wherein a third logic element outputs the enable signal before the end timing that is based on the comparison signal; wherein the second input terminal of the first logic element of the count latch unit receives the enable signal that is outputted from the third logic element, wherein the second input terminal of the first logic element of the non-count latch unit receives the enable signal that is outputted from the second logic element, and wherein the count latch unit and the non-count latch unit receives output of the delay portion.