Patent ID: 7421643
Filing Date: 2008-09-02
Classification: H03M,H04L

Abstract:
1. A channel detector comprising: estimation logic configured to estimate whether each bit of a code word received in the channel detector is a 1 or a 0, wherein the estimation logic estimates whether each of the bits of the code word is a 1 or a 0 by determining a maximum likelihood (ML) path through a Viterbi trellis and determining respective bit values associated with respective branches along the ML path, wherein the respective bit values associated with the respective branches along the ML path correspond to respective estimates; decision logic configured to decide whether one or more of the estimates is correct based on one or more parity bits contained in the code word, wherein the decision logic is configured to prune branches in the Viterbi trellis based on the one or more parity bits to reduce the number of possible branches through the Viterbi trellis from which to determine the maximum likelihood path; and reliability generation logic configured to produce respective reliability estimates associated with the respective bit estimates, wherein the bit estimates and the reliability estimates are used by a decoder in an iterative process between the channel detector and the decoder to recover original information bits of the code word.