Patent ID: 7197732
Filing Date: 2007-03-27
Classification: G06F

Abstract:
1. Logic for layout-driven, area-constrained design optimization, the logic encoded in one or more media for execution and when executed operable to: access a design and a layout of the design, the design comprising one or more gates and one or more nets coupling the gates to each other, the layout comprising blocks that partition a chip area of the design, each block comprising one or more of the gates, the layout further comprising a global routing of the nets; perform a first timing analysis of the design and the layout; update the design and the layout as follows: perform a second timing analysis of the design and the layout, the second timing analysis taking into account the updates to the design and the layout; if one or more results of the second timing analysis indicate that the design meets all predetermined design goals or indicate no progress toward one or more of the design goals relative to one or more results of the first timing analysis, communicate the design and the layout for analysis; and if one or more results of the second timing analysis indicate that the design does not meet one or more predetermined design goals and indicate at least a predetermined amount of progress toward one or more of the design goals relative to the one or more results of the first timing analysis, further update the design and the layout.