Patent ID: 6842162
Filing Date: 2005-01-11
Classification: G09G

Abstract:
1. A memory controller for a display comprising: a set of first drivers; a set of second drivers, a portion of which can be converted to said first drivers; a RAM memory structured to accept data at an input and output said data to the sets of first and second drivers when a master clock signal is received at said RAM memory; a clock signal generator structured to generate said master clock signal; a control signal generator circuit structured to generate control signals for said RAM memory and said sets of first and second drivers; said clock signal generator circuit is structured to also generate a slave clock signal; and; a set of auxiliary registers structured to temporarily store a first portion of said data received from said RAM memory after receiving said slave clock signal, and said set of auxiliary registers structured to output said first portion of data into said portion of said second drivers converted to said set of first drivers after receiving said master clock signal.