Patent ID: 8693271
Filing Date: 2014-04-08
Classification: G11C

Abstract:
1. A method of stress testing a solid-state static random access memory (SRAM) array comprised of a plurality of memory cells arranged in rows and columns, each memory cell comprised of first and second cross-coupled inverters and first and second pass transistors, each column of memory cells associated with a pair of bit lines coupled to the first and second pass transistors of the memory cells in the column, and each row of memory cells associated with a word line coupled to gates of the pass transistors of the memory cells in the row, the method comprising: applying a nominal power supply voltage level to the array, the nominal power supply voltage level being within a normal operating range of the array; then writing a first data pattern into a plurality of memory cells in the array; then applying an elevated power supply voltage level outside of the normal operating range to the array; during the step of applying the elevated power supply voltage level: reducing the power supply voltage level to the array; and performing a write screen of the plurality of memory cells, the write screen comprising writing a data state into each of the plurality of memory cells following by reading the data state.