Patent ID: 6323684
Filing Date: 2001-11-27
Classification: H03K

Abstract:
A interface circuit comprising:a terminal that supplies a first power source (Vdd) having a first potential;a terminal that supplies a second power source (Vss) having a second potential lower than the first potential;a first driver circuit (P8, N2) that receives a data signal input;a second driver circuit (P1, N1) and a first node (node a) connecting an output from the first driver circuit to an input of the second driver circuit;an input/output pad connected to an output of the second driver circuit;a second node (node b) connected between the terminal for supplying the first power source and the terminal for supplying the second power source; anda first protection circuit (N3) that controls a state of the first driver circuit (P8, N2) by setting the second node (node b) to the second potential when a potential substantially equal to the second power source (Vss) is applied to the input/output pad from an external source.