Patent ID: 6788581
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a plurality of memory cells; a data line arranged to be electrically coupled with a single cell selected from said plurality of memory cells in a data read operation; a sense amplifier circuit for detecting a current of said data line in said data read operation, said sense amplifier circuit including a first current source for supplying said data line with a current in said data read operation, said first current source having a first internal node arranged to be connected to said data line in said data read operation and a first transistor arranged to be electrically coupled between said first internal node and a power supply voltage, said sense amplifier circuit further including a first conversion circuit for comparing a voltage of said first internal node with a first threshold voltage; and a first voltage setting circuit for setting a voltage of a gate of said first transistor to operate said first transistor in a saturation range when said first internal node has a voltage in a range of no more than said first threshold voltage.