Patent ID: 6014094
Filing Date: 2000-01-11
Classification: G11B,H03M

Abstract:
A DSV control system comprising:an address generating circuit generating and outputting addresses in sequence;a first memory storing and outputting codes of a first modulation code sequence, into which a sequence of digital codes is converted using a first modulation table, at the addresses outputted from said address generating circuit;a second memory storing and outputting codes of a second modulation code sequence, into which the sequence of digital codes is converted using a table different from said first modulation table, at the addresses outputted from said address generating circuit;a DSV comparing circuit comparing a first DSV and a second DSV to provide a first select signal and storing the smaller of said first and second DSV, said first DSV calculating a stored DSV and a DSV of a portion of said first modulation code sequence ranging from a DSV control enable code of said first modulation code sequence to the code at a specified one of the addresses outputted from said generating circuit, said second DSV calculating the stored DSV and a DSV of a portion of said second modulation code sequence ranging from a DSV control enable code of said second modulation code sequence to the code at the specified one of the addresses outputted from said address generation circuit, said first select signal indicating the portion of said first modulation code sequence or the portion of said second modulation code sequence showing a smaller DSV:a select signal generating circuit generating second select signals for selecting all codes of the portion of said first or second modulation code sequence indicated by said first select signal and outputting them until the next first select signal: anda selector selecting all the codes of the portion of said first modulation code sequence and the portion of said second modulation code sequence based on said second select signals from said select signal generating circuit.