Patent ID: 7949085
Filing Date: 2011-05-24
Classification: G09G,G11C

Abstract:
1. A shift register, comprising: n register units electrically coupled in cascade, where n is equal to or greater than 3, each register unit outputting an output pulse according to a first clock signal, a second clock signal, and an input pulse, wherein the input pulse of a first one of the n register units comprises a start trigger pulse, and wherein the input pulse of the second to the n a first switch unit for conducting the input pulse to a first node when the first switch unit is turned on; a second switch unit for conducting the first clock signal to an output end to generate the output pulse when the second switch unit is turned on in response to the input pulse; a third switch unit for conducting a supply voltage to the output end when the second switch unit is turned off; a fourth switch unit, electrically coupled to a supply end, for conducting the supply voltage to the first node when the fourth switch unit is turned on in response to a driving pulse; and a driving unit for providing the driving pulse according to the first clock signal, the second clock signal, and the input pulse, the driving unit comprising: