Patent ID: 8841646
Filing Date: 2014-09-23
Classification: H01L

Abstract:
1. A semiconductor storage device comprising: a substrate on which semiconductor elements are formed; a plurality of first selection lines disposed above the substrate; a plurality of second selection lines which are disposed above the first selection lines and which extend in a direction which intersects with the first selection lines, a memory array which comprises a stacked body in which N+1 (N≧1) number of first inter-gate insulator layers and N number of first semiconductor layers are alternately stacked in the height direction of the substrate, a channel layer which is disposed along the side surface of the stacked body, and a variable resistance material layer which is disposed along the side surface of the channel layer and which is disposed between the first selection lines and the second selection lines; and N number of control signal lines connected to the N number of the first semiconductor layers through N number of contacts, wherein the N number of the contacts are formed in a region which is positioned in a first direction of the memory array and which is collaterally disposed in a second direction which intersects the first direction.