Patent ID: 7287115
Filing Date: 2007-10-23
Classification: G11C,H01L

Abstract:
1. A multichip package type memory system comprising: a plurality of types of memory integrated circuits each having memory cells, which are provided in a memory system packaged in a package having an internal bus including a local data bus, a local address bus, and a local control bus, and are connected to the internal bus in common, and which are accessed for a predetermined operation among read, write, and erase operations from exterior of the package, and/or, which are accessed for a predetermined operation among read, write, and erase operations within the package; and a controlling integrated circuit which is provided in the memory system packaged in the package, and when an instruction of data transfer within the memory system is received from exterior of the package, controls an execution of the data transfer to be executed within the memory system such that data of memory cells at continuous addresses of a first readable memory integrated circuit among the plurality of types of memory integrated circuits from a start address up to an end address of the first readable memory integrated circuit are read out, and the readout data are written into memory cells at continuous addresses of a second writable memory integrated circuit among the plurality of types of memory integrated circuits from a start address up to an end address of the second writable memory integrated circuit.