Patent ID: 6528353
Filing Date: 2003-03-04
Classification: H01L

Abstract:
A method for fabricating a chip stack type semiconductor package, comprising the steps of:(1) attaching both surface adhesive insulating apes on a top surface of a lower chip where no center pads are formed therein, the lower chip having a center pad formation surface defined at the bottom thereof; (2) attaching an upper chip on a top surface of the both surface adhesive insulating tape to stack the upper chip on the lower chip; (3) attaching both surface adhesive insulating tapes on regions spaced from, and positioned left and right sides of respective center pads formed in the center pad formation surfaces of the lower chip and the upper chip; (4) attaching a top end portion of a first lead to the both surface adhesive insulating tape attached on the left side of the center pad of the upper chip, attaching a top end portion of a second lead to the both surface adhesive insulating tape attached on the right side of the center pad of the upper chip, attaching a bottom end portion of the first lead to the both surface adhesive insulating tape attached on the left side of the center pad of the lower chip, and attaching a bottom end portion of the second lead to the both surface adhesive insulating tape attached on the right side of the center pad of the lower chip, the first lead being attached opposite the second lead so as to enclose opposite sides of the upper and lower chips, thereby fitting the top end portion of the first lead directly opposing the bottom end portion of the first lead, and the top end portion of the second lead directly opposing the bottom end portion of the second lead; (5) electrically connecting the top and bottom end portions of the leads to the center pads of the lower chip and the upper chip with conductive connection members; (6) conducting a resin encapsulation so as to protect the upper and lower chips and the conductive connection members, to form a molded body; and, (7) attaching solder balls, external power source connection terminals, to bottoms of the lead portions outside of the molded body.