Patent ID: 8296507
Filing Date: 2012-10-23
Classification: G06F

Abstract:
1. A memory management and writing method, for managing a plurality of physical units of a memory chip, the memory management and writing method comprising: configuring a plurality of logical units; grouping the physical units into a first physical unit group and a second physical unit group; grouping a portion of the physical units in the first physical unit group into a first data area and a first spare area corresponding to the first data area; grouping a portion of the physical units in the second physical unit group into a second data area and a second spare area corresponding to the second data area; mapping the logical units to the physical units in the first data area and the second data area; recording erase counts corresponding to a plurality of the physical units in the first physical unit group and the second physical unit group; calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group according to the erase counts, and calculating an erase count difference between the first erase count and the second erase count; and determining whether the erase count difference is larger than an erase count difference threshold when a write command corresponding to a first logical unit among the logical units and new data corresponding to the write command are received, wherein the first logical unit is mapped to a first physical unit among the physical units in the first data area, wherein a switched writing procedure is executed when the erase count difference is larger than the erase count difference threshold, and the switched writing procedure comprises: