Patent ID: 8566776
Filing Date: 2013-10-22
Classification: G06F

Abstract:
1. A method comprising: determining, at a processor, whether less than two system power supply lines but at least one system power supply line having a first voltage level is detected within a channel between at least two macro cells of a circuit layout such that a shortest distance between the at least two macro cells satisfies a threshold value, wherein each power supply line is coupled to provide power to a device within the channel to reduce signal delay between a first macro cell and a second macro cell, and wherein the device is coupled to the first macro cell and to the second macro cell; and automatically adding a power line having a second voltage level to the circuit layout in the channel between the at least two macro cells in response to a determination that the at least one system power supply line is detected within the channel, wherein the second voltage level has an opposite polarity to the first voltage level, and wherein the added power line is coupled to provide power to the device within the channel.