Patent ID: 8058125
Filing Date: 2011-11-15
Classification: H01L

Abstract:
1. A method of forming a poly silicon resistor device, the method comprising: providing a substrate having a first region and a second region; forming a dummy gate stack on the substrate in the first region, wherein the dummy gate stack has a dummy gate stack thickness extending above the substrate; forming a poly silicon resistor on the substrate in the second region, wherein the poly silicon resistor has a poly silicon resistor thickness extending above the substrate less than the dummy gate stack thickness; implanting a dopant into the substrate in the first region thereby forming a source region and a drain region in the first region of the substrate and also implanting the dopant into the poly silicon resistor; forming an inter-level dielectric (ILD) layer on the substrate over the dummy gate stack and over the poly silicon resistor; planarizing the ILD layer, thereby exposing the dummy gate stack and leaving a portion of the ILD layer over the poly silicon resistor; and replacing the dummy gate stack with a high k metal gate while using the portion of the ILD layer over the poly silicon resistor as a mask to protect the poly silicon resistor during replacing the dummy gate stack with the high k metal gate.