Patent ID: 6107204
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains at least one active semiconductor device and at least one conductive structure with a first end contacting an electrode of the at least one active semiconductor device;forming a first layer of an etch stop material on the first layer of interlayer dielectric;forming a second layer of interlayer dielectric on the first layer of an etch stop material;forming a second layer of an etch stop material on the second layer of interlayer dielectric;forming a first layer of photoresist on the second layer of an etch stop material;patterning and etching the first layer of photoresist exposing portions of the second layer of etch stop material;anisotropically etching the exposed portions of the second layer of etch stop material, wherein portions of the second layer of interlayer dielectric are exposed;anisotropically etching the exposed portions of the second layer of interlayer dielectric, wherein portions of the first layer of etch stop material are exposed;anisotropically etching the exposed portions of the first layer of etch stop material, wherein portions of the first layer of interlayer dielectric are exposed;removing remaining portions of the first layer of photoresist;forming a second layer of photoresist on a surface of the semiconductor device;patterning and etching the second layer of photoresist exposing portions of the first interlayer dielectric overlaying the at least one conductive structure;anisotropically etching the exposed portions of the first interlayer dielectric overlaying the at least one conductive structure, wherein portions of the at least one conductive structure are exposed;removing the second layer of photoresist;filling the etched portions of the semiconductor device with a conductive material;planarizing the semiconductor device forming a planarized surface;forming a third layer of photoresist on the planarized surface;patterning and etching the third layer of photoresist exposing portions of the planarized surface of the semiconductor device;anisotropically etching exposed portions of the conductive material;removing the third layer of photoresist; andfilling etched portions of the conductive material with a dielectric material.