Patent ID: 6563320
Filing Date: 2003-05-13
Classification: G01B,G03F,H01L

Abstract:
In an integrated circuit (IC) comprising a first layer and a second layer, an alignment test structure comprising:a first source in the first layer, the first source having a first width in a first direction; a first drain in the first layer, the first drain having a first reduced portion having a second width in the first direction and a first full portion having a third width in the first direction, the second width being less than the first width and the third width being substantially equal to the first width; a first alignment feature in the second layer, the first alignment feature being substantially insulated from the first layer; and a first channel in the first layer between the first source and the first drain, the first channel being formed where the first alignment feature overlies the first layer between the first source and the first drain, wherein a first distance between the first alignment feature and the first reduced portion in a second direction is controlled by the alignment in the second direction of the first layer and the second layer, the second direction being substantially perpendicular to the first direction.