Patent ID: 6289494
Filing Date: 2001-09-11
Classification: G06F,H03K

Abstract:
An integrated circuit comprising:a plurality of logic elements, said plurality of logic elements divided into a plurality of subsets of logic elements;a plurality of first level interconnects, each of said plurality of first level interconnects interconnecting logic elements within one of said plurality of subsets of logic elements, thereby forming a plurality of first level logical units, said plurality of first level logical units divided into a plurality of subsets of first level logical units, each of said plurality of first level interconnects comprising input interconnect structures and output interconnect structures, said input interconnect structures and said output interconnect structures comprising a fully populated crossbar network;a plurality of second level interconnects, each of said second level interconnects interconnecting one of said plurality of subsets of first level logic units, thereby forming a plurality of second level logic units, each of said plurality of second level interconnects comprising a partial crossbar architecture;a third level interconnect, said third level interconnect interconnecting said plurality of second level logic units, thereby forming a third level logic unit, said third level interconnect comprising a partial crossbar architecture;wherein each of said fully populated crossbar networks comprises:a plurality of groups of inputs;a plurality of multiplexers, each of said plurality of multiplexers comprising at least two data inputs, at least one select input and at least one output, each input of one said plurality of groups of inputs electrically communicating with said data inputs of a corresponding one of said plurality of multiplexers, said at least one select input on each of said plurality of multiplexers electrically connected to a decoder, said decoder electrically connected to a programming cell;a programmable crosspoint in electrical communication between said at least one output of each of said plurality of multiplexers and a crossbar output pin, said programmable crosspoint comprising a pass transistor and a programmable memory cell.