Patent ID: 6397362
Filing Date: 2002-05-28
Classification: G01R

Abstract:
A fault diagnosis method for a LSI comprising the steps of:obtaining information of expected values for outputs of each flip-flop in the LSI based on each input vector of the each flip-flop, pass/fail information for each output pin in a test, and a netlist for the LSI; consecutively extracting, based on said netlist, combinational circuits each having a plurality of inputs each connected to an input pin or an output of any flip-flop and a plurality of outputs each connected to an output pin or input of any flip-flop, the combinational circuit including nets and logic elements other than a flip-flop, wherein said tracing starts from a failed output pin by backward tracing to an output of any first flip-flop or an input pin, and said tracing includes forward tracing from an input pin or an output of any flip-flop found by backward tracing to an output pin or an input of any flip-flop and backward tracing from an output pin or input of any flip-flop found by forward tracing to an input pin or an output of any flip-flop; inferring a plurality of input vectors for the inputs of each said combinational circuit based on an output vector of said each combinational circuit or said pass/fail information, said output vector being inferred based on said pass/fail information; reducing said input vectors of said combinational circuit in number by simplification so as to form said output vector of preceding combinational circuit; and inferring a faulty position in one of said combinational circuits when no correct input vector is inferred based on said output vector of said one of said combinational circuits, said correct input vector coinciding with an expected input vector of inputs of said one of said combinational circuits.