Patent ID: 8774337
Filing Date: 2014-07-08
Classification: H03L,H04L

Abstract:
1. An integrated circuit operable to receive an incoming digital signal carrying an embedded clock, comprising: circuitry to detect phase differences between the embedded clock and a recovered clock and to produce an output representing the phase differences; circuitry to receive the output and produce a first register value representing accumulation of the phase differences; circuitry to generate the recovered clock as a first phase-shifted version of a reference clock in dependence on the first register value; circuitry to add a digital offset to the first register value to generate a second register value; and circuitry to, concurrently with generation of the recovered clock, generate a second clock as a second phase-shifted version of the reference clock in dependence on the second register value; wherein the recovered clock is an edge clock, the second clock is a data clock and the digital offset is a first digital offset corresponding to a first data sampling instant, such that the second clock is aligned to the first data sampling instant.