Patent ID: 9063671
Filing Date: 2015-06-23
Classification: G06F,G11C

Abstract:
1. A method of operating a nonvolatile memory array comprising: receiving a first portion of data to be stored in the nonvolatile memory array; buffering the first portion of data in on-chip data latches; writing the first portion of data from the on-chip data latches to the nonvolatile memory array in Single Level Cell (SLC) format; subsequently receiving a second portion of data to be stored in the nonvolatile memory array; buffering the second portion of data in the on-chip data latches with the first portion of data; subsequently, writing the first and second portions of data together in Multi Level Cell (MLC) format in a word line of an MLC block as lower page and upper page data respectively; subsequently, receiving the second portion of data at least partially in parallel with the storing the first and second portions together in MLC format; subsequently storing the second portion of data in SLC format; subsequently comparing the second portion in MLC format with the second portion in SLC format to determine if the second portion in MLC format meets a standard; and discarding the first and second portions in SLC format only if the second portion in MLC format meets the standard.