Patent ID: 9021298
Filing Date: 2015-04-28
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising: first processing circuitry configured to perform processing upon an input signal to generate an output signal; second processing circuitry coupled to said first processing circuitry and configured to perform further processing upon said output signal; error detecting circuitry configured to detect errors in said output signal at a time after said second processing circuitry has started to perform said further processing using said output signal; error repair circuitry configured to respond to an error in said output signal detected by said error detecting circuitry to perform an error repair operation; error tolerance circuitry coupled to said error repair circuitry and configured to respond to a control parameter to selectively disable said error repair circuitry such that said error repair operation is not performed; and storage circuitry configured to store a plurality of output signal values and error status for said plurality of output signal values indicating whether respecetive output signal values are in error; wherein said control parameter is dependent upon at least some of said plurality of said, output signal values and error status for said plurality of output signal values stored within said storage circuitry.