Patent ID: 6434693
Filing Date: 2002-08-13
Classification: G06F

Abstract:
In a microprocessor having an execution unit adapted to execute instructions from a stream of instructions that include load and store operations, a method for managing load and store operations to and from a memory system, the method comprising:(a) issuing an instruction from an instruction window that stores a plurality of instructions; (b) determining whether said instruction includes a store operation and/or a load operation; (c) if said instruction includes a store operation, performing said store operation in order with respect to all instructions in the stream of instructions; and (d) if said instruction includes a load operation, performing said load operation out of order with respect to one or more instructions in said instruction window, wherein said performing said load operation comprises: (i) checking for an address collision and for any write pendings; (ii) making a data request to the memory system when there are no address collisions and write pendings; (iii) receiving requested data from the memory system; and (iv) aligning said requested data if said requested data is unaligned.