Patent ID: 6096609
Filing Date: 2000-08-01
Classification: H01L,Y10S

Abstract:
A method for fabricating an ESD protection circuit comprising the steps of:forming field regions and an active region in a semiconductor substrate;forming isolating films in the field regions;forming a gate insulating film on the active region and a conductive layer on the gate insulating film;selectively removing the conductive layer and the gate insulating film to form a gate electrode;forming a plurality of dummy gate electrodes on one side of the gate electrode and offset from the gate electrode;forming insulating sidewall spacers at both sides of the gate electrode and at sides of each of the plurality of dummy gate electrodes;forming first and second heavily doped impurity regions in a surface of the semiconductor substrate at both sides of the gate electrode and at sides of each of the plurality of dummy gate electrodes;forming salicide films on a surface of the first heavily doped impurity region, on a surface of the gate electrode and on surfaces of each of the plurality of the dummy gate electrodes; andforming metal wirings for electrically connecting to the first and second heavily doped impurity regions.