Patent ID: 8841717
Filing Date: 2014-09-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first single-crystal semiconductor pillar projected from a substrate, the first single-crystal semiconductor pillar including a first top surface and a first side surface extending downwardly from the first top surface; and a bit contact including a topmost surface, a bottommost surface and a second side surface interfacing the topmost and bottommost surfaces with each other, a part of the second side surface of the bit contact being in direct contact with a part of the first side surface of the first single-crystal semiconductor pillar so that the first top surface of the first single-crystal semiconductor pillar is placed between the topmost and bottommost surfaces of the bit contact, a second single-crystal semiconductor pillar projected from the substrate apart from the first single-crystal semiconductor pillar to form a gap between the first and second single-crystal semiconductor pillars, the second single-crystal semiconductor pillar including a second top surface and a third side surface extending downwardly from the second top surface; a word line filling a part of the gap in isolation from each of the first and second single-crystal semiconductor pillars with a gate insulating film; a first diffusion region formed in an upper portion of the first single-crystal semiconductor pillar; and a second diffusion region formed in an upper portion of the second single-crystal semiconductor pillar, wherein the first diffusion region is formed more deeply than the second diffusion region.