Patent ID: 6360355
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A hardware synthesis method comprising the steps of:(a) converting a behavioral description including an execution control branch instruction into a control flow graph; (b) converting the control flow graph into a control data flow graph; (c) performing scheduling according to the control data flow graph; and (d) performing allocation according to a result of scheduling, wherein, in said step (a), a behavioral description including a goto statement to be executed according to a condition is converted into a control flow graph, and wherein said step (a) comprises the steps of: dividing the behavioral description into partial descriptions separated by an if-goto statement or a jump destination label; representing each of the partial descriptions by one partial control flow graph; generating a branch node corresponding to the if-goto statement and branching control flow branches; and generating a merge node corresponding to the jump destination label and merging the control flow branches.