Patent ID: 7724045
Filing Date: 2010-05-25
Classification: H03K

Abstract:
1. An output buffer circuit outputting an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage, the output buffer circuit comprising: an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage; a first driving circuit outputting a first control signal to control the pull-down transistor; a second driving circuit including a latch circuit to latch signals, and outputting a second control signal to control the pull-up transistor based on retained data in that latch circuit; and a level shifter changing the retained data in the latch circuit when logic of the input signal changes, the level shifter comprising: an inverter circuit inputting a pulse signal and outputting the inverted signal; and an n-type MOS transistor having a drain coupled to a data retaining node in the latch circuit, a source to which an output signal from the inverter circuit is input, and a gate to which the first power supply voltage is supplied.