Patent ID: 7214326
Filing Date: 2007-05-08
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor package, comprising the steps of: a) applying first and second photoresist layers to respective ones of opposed first and second surfaces of a metal plate which includes a die paddle and a plurality of leads extending at least partially about the die paddle in spaced relation thereto; b) patterning the first and second photoresist layers to expose the die paddle and prescribed portions of each of the leads; c) applying first and second conductive layers to portions of respective ones of the first and second surfaces which are not covered by the first and second photoresist layers; d) removing the first and second photoresist layers to facilitate the creation of an exposed area in each of leads which is not covered by the first and second conductive layers; e) attaching a semiconductor die to a portion of the first conductive layer covering the die paddle; f) electrically connecting the semiconductor die to portions of the first conductive layer covering the leads; g) at least partially encapsulating the semiconductor die, the die paddle, the leads and the first and second conductive layers with a package body such that portions of the second conductive layer covering the die paddle and the leads, and the exposed area of each of the leads are exposed in a common surface of the package body; and h) etching the exposed area of each of the leads to facilitate the division of the leads into an inner set extending at least partially about the die paddle and an outer set extending at least partially about the inner set.