Patent ID: 6767780
Filing Date: 2004-07-27
Classification: H01L

Abstract:
A method for fabricating a CMOS transistor, comprising:a) forming a n-type well region in a semiconductor substrate; b) forming a first n-type punch stop layer in type n-type well; c) forming a p-type well region in the n-type well region; d) concurrently forming a first n-type LDD region in the p-type well region and a second n-type punch stop layer in the n-type well region by ion-implanting an impurity to a gate electrode as a mask; e) forming a n-type source/drain extension region having higher concentration of the impurity than concentration of the first n-type LDD region in the first n-type LDD region; f) forming a second n-type LDD region, which surrounds the n-type source/drain extension region; g) forming a spacer at a side of the gate electrode; h) forming p-type source/drain region contacting to the first punch stop layer and the second punch stop layer; and i) forming a n-type source/drain region contacting to the source/drain extension region and the first and second LDD region.