Patent ID: 7624237
Filing Date: 2009-11-24
Classification: G06F

Abstract:
1. A method for executing a machine instruction in a central processing unit, the method comprising: fetching a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising an opcode field, a first field comprising a first base field (B1) for identifying a first register and a first displacement field (D1) the content of which is added to the content of the first register to form the address of a first operand in a storage, a second field comprising a second base field (B2) for identifying a second register and a second displacement field (D2) the content of which is added to the content of the second register to form the address of a second operand in the storage, and a third field for identifying a third register (R3) containing a third operand; executing said fetched machine instruction, the execution comprising: wherein the machine instruction can be intermixed with a compare and swap instruction that utilizes an interlocked update operation.