Patent ID: 6745274
Filing Date: 2004-06-01
Classification: G06F

Abstract:
A computer system comprising:a number of cells, each cell including a number of processors, a memory unit, an I/O bridge, and a memory controller unit that interconnects the memory unit, the I/O bridge, and the number of processors; and a non-bus, high-speed interconnect that interconnects the number of cells, the non-bus, high-speed interconnect including a high-speed data transmission medium, a number of resources, a transaction control unit that serializes access requests made by components of the cells, including the processors, for access to the number of resources and the number of control registers, the transaction control unit comprising a number of ports, each port representing a communication medium by which a cell component sends a resource access request, and logic that polls the number of ports to receive and serialize access requests from components of the number of cells, and a semaphore control unit that interoperates with the transaction control unit to provide exclusive access to each resource, the semaphore control unit comprising, for each resource, an associated pair of semaphore registers including a current owner register and a previous owner register, the current owner register containing one of a predefined value indicating that the resource associated with the pair of semaphore registers including the current owner register is available, and an identifier identifying a component of a cell currently holding exclusive access to the resource associated with the pair of semaphore registers including the current owner register.