Patent ID: 7994820
Filing Date: 2011-08-09
Classification: H03K

Abstract:
1. A method, comprising: arranging transistors into a level shifter circuit that includes a shift stage, the shift stage comprising a first plurality of transistors in a first leg of the shift stage and a second plurality of transistors in a second leg of the shift stage, wherein a number of the first plurality of transistors is greater than a number of a second plurality of transistors; inserting one or more additional transistors in the second leg of the shift stage, wherein a number of the additional transistors is a difference between a number of the first plurality of transistors and a number of the second plurality of transistors; and connecting a gate terminal of the one or more additional transistors to a static voltage; and providing a circuit coupled to an output of the shift stage, wherein the circuit is controlled by a first control signal and a second control signal, wherein the first control signal indicates, when asserted, that a power supply voltage corresponding to a source voltage domain is to be powered off, and wherein the second control signal controls whether an output of the level shifter is high or low in response to assertion of the first control signal, wherein the output of the level shifter is high or low in response to the second control signal and assertion of the first control signal, and wherein the output of the level shifter is independent of a state of an input signal to the level shifter in response to assertion of the first control signal.