Patent ID: 7154984
Filing Date: 2006-12-26
Classification: G06F

Abstract:
1. A FIFO-register comprising a sequence of register cells, which register cells comprise a data section and a status section, in which data provided at an input is shifted via the data sections in the register cells to an output, the status section of each cell indicating whether the data section of that cell contains valid data, wherein the status section of the cells comprises a clock input for receiving an input clock signal, a status input for receiving an input status signal, a status output for providing an output status signal, a clock output for providing an output clock signal, a first charge controlling element coupled to the status input, a second charge controlling element coupled to the status output, a control unit coupled to the status input, to the status output and to the clock input, for generating the output clock signal, which output clock signal controls the charge controlling elements and the data section, wherein the status output of a status section shares a node with the status input of its successor for dynamic storage.