Patent ID: 6489182
Filing Date: 2002-12-03
Classification: H01L,Y10T

Abstract:
A method for fabricating a chip size package, comprising the steps of:etching a copper film applied on an insulating film tape, except for longitudinal marginal copper film portions at edges of the copper film, the etching also forming metal pattern units of the copper film which are peripheral to portions of the insulating film tape corresponding to chip pads of a semiconductor chip, and portions of the copper film connect the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the solder mask not covering the copper film at four edge portions of the longitudinal marginal portions, and the solder mask not covering exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; sealing side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound; etching portions of the insulating film tape formed on the chip pads for thereby exposing the chip pads; electrically connecting by wires the metal pattern unit-electrodes and the corresponding chip pads; and eliminating portions of the copper film remaining at the four edge portions of the longitudinal marginal portions thereof and cutting the resultant insulating film tape to be separated into individual units.