Patent ID: 7669034
Filing Date: 2010-02-23
Classification: G06F

Abstract:
1. A computer-implemented method comprising: receiving a first plurality of base address bits and a first plurality of offset address bits; pairing each of the first plurality of base address bits with a corresponding bit from the first plurality of offset address bits; generating a plurality of PGZO values for each of the paired bits wherein a P value results from a logical XOR operation performed on each of the paired bits, a G value results from a logical AND operation performed on each of the paired bits, a Z value results from a logical OR operation performed on each of the paired bits, and an O value results from a logical AND operation performed on the inverse value of each of the paired bits; mapping the resulting P, G, Z, and O values (the PGZO values) to a plurality of wordline functions; evaluating the PGZO values using the plurality of wordline functions, the evaluating resulting in two possible memory array entry matches; and selecting one of the two possible memory array entry matches from a memory array based on whether a carry value results from adding at least the least significant bit of the base address bits with the least significant bit of the offset address bits.