Patent ID: 6246266
Filing Date: 2001-06-12
Classification: H03K

Abstract:
A dynamic logic circuit coupled between an upper supply voltage and a lower supply voltage and operable in an active mode and in a power down mode, wherein the active mode comprises a precharge phase and an evaluate phase, the circuit comprising:a precharge node coupled to be precharged to a precharge voltage during the precharge phase and operable to be discharged during the evaluate phase;a conditional series discharge path connected to the precharge node and comprising a plurality of transistors operable to conditionally couple the precharge node to a voltage different than the precharge voltage;an output inverter having an input connected to the precharge node and comprising a plurality of transistors for providing an output signal representative of a voltage at the precharge node during the evaluate phase; anda precharge transistor to be enabled during the power down mode and having a source/drain conductive path for coupling the precharge voltage to the precharge node during the precharge phase;wherein, during the power down mode, at least one transistor in a first set of selected ones of the precharge transistor, the transistors of the conditional series path, and the transistors of the output inverter has a source/drain node connected to the upper supply voltage;wherein, during the power down mode, at least one transistor in a second set of selected ones of the precharge transistor, the transistors of the conditional series path, and the transistors of the output inverter has a source/drain node connected to the lower supply voltage;wherein, during the power down mode, at least one transistor in a third set of selected ones of the precharge transistor, the transistors of the conditional series path, and the transistors of the output inverter has a source/drain node selectively disabled from either of the upper supply voltage and the lower supply voltage;wherein selected ones of the precharge transistor, the transistors of the conditional series path, and the transistors of the output inverter have a threshold voltage selected based on whether the corresponding transistor is always enabled during the power down mode; andwherein for a group of those transistors that are always enabled during the power down mode each such transistor has a threshold voltage that is relatively lower than another one of the transistors in the dynamic logic circuit having a same conductivity type.