Patent ID: 6976184
Filing Date: 2005-12-13
Classification: G06F

Abstract:
1. A reset apparatus for a clocking subsystem of a data processing system having a clock source, comprising: a phase locked loop (PLL) having a reference clock input for receiving clock signals from the clock source, a reset input for receiving a PLL reset signal that resets the PLL, the PLL further having an output that delivers phase aligned clock signals to logic of the data processing system; a circuit having a clock input to receive the clock signals and a reset input to receive a circuit reset signal, the circuit further having a PLL reset output to deliver the PLL reset signal to the PLL; a first timer having an input that receives the clock signals, the first timer generating a first timer signal in response to receiving the clock signals, and not generating the first timer signal in response to not receiving the clock signals; and a second timer having an input to receive the first timer signal, an output to deliver the circuit reset signal to the circuit in response to detecting an absence of the first timer signal, the circuit rest signal causing the circuit to reset the PLL.