Patent ID: 6463522
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A processor comprising:a memory order buffer (MOB) including a plurality of load buffers to each hold multiple load instructions of one of a group of threads and store buffers to each hold multiple store instructions of one of the threads wherein at times there are dependencies between at least some of the threads, wherein within each of the load buffers load instructions are held in program order and within each of the store buffers store instructions are held in program order, and wherein the MOB orders the load and store instructions so as to maintain data coherency between the load and store instructions in the threads, and wherein the MOB includes match determining logic and replay triggering logic; wherein the match determining logic determines whether there are matches between addresses of certain of the load and store instructions; and wherein under selected conditions when there are matches between the addresses of the load and store instructions, the replay determining logic controls re-execution of selected ones of the load and store instructions without there being a re-execution of entire threads containing the re-executed load and store instructions.