Patent ID: 7539036
Filing Date: 2009-05-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first memory mat and a second memory mat each including a memory cell storing data; at least one first current line arranged for each of said memory mats and connected to one conductive electrode of said memory cell; a sense latch shared between said memory mats, storing electric charges corresponding to write data for said memory cell in said first current line and detecting data stored by said memory cell based on a voltage value or a current value of said first current line; at least one second current line arranged for each of said memory mats; a plurality of first transistors arranged corresponding to said first current line for switching between connection and disconnection between said first current line and said second current line; a plurality of second transistors arranged corresponding to said first current line for switching between connection and disconnection between said first current line and said sense latch; at least one third current line arranged for each of said memory mats; and a plurality of third transistors arranged corresponding to said first current line for switching between connection and disconnection between the other conductive electrode of said memory cell and said third current line, wherein said first memory mat, a drain region, a gate region and a source region of said first transistor corresponding to said first memory mat, said sense latch, a drain region, a gate region and a source region of said first transistor corresponding to said second memory mat, and said second memory mat are arranged in that order in a direction in which said first current line extends.