Patent ID: 6307396
Filing Date: 2001-10-23
Classification: H03K

Abstract:
A low-consumption TTL-CMOS input buffer stage comprising a chain of inverters cascade connected between an input that receives electric signals at a TTL logic level and an output that produces electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference, wherein a first inverter in the chain includes a means of selecting a delivery path to the buffer stage according to an activate signal for a low-consumption operation mode, wherein said first inverter comprises a complementary first pair of transistors, and that said means comprises a complementary second pair of high-voltage transistors connected between the transistors of the first pair; the first pair of transistors having control terminals respectively receiving said activate signal in a straight form and a negated form; the second pair of transistors having control terminals connected to said input.