Patent ID: 8400835
Filing Date: 2013-03-19
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory in which a plurality of non-volatile memory cells can be simultaneously written using a plurality of bit lines, the device comprising: M data lines connected to the plurality of bit lines based on a column address signal, where M is an integer of two or more and is smaller than the number of the bit lines; a drain voltage generation circuit configured to generate a voltage which is a source of a drain voltage of each of the plurality of non-volatile memory cells; a drain voltage supply line connected to an output of the drain voltage generation circuit; and M switch circuits and M switch control circuits provided between the M data lines and the drain voltage supply line, wherein each of the M switch circuits includes N switches, where N is an integer of one or more, each of the M×N switches includes a first and a second terminal, and the first terminals of the N switches of each of the M switch circuits are connected at a common point to a corresponding one of the M data lines, and the second terminals of the N switches of each of the M switch circuits are connected at a common point to the drain voltage supply line, and the drain voltage supply line is connected to the M data lines via the M×N switches, and the M×N switches are controlled by the M switch control circuits.