Patent ID: 8494028
Filing Date: 2013-07-23
Classification: H04B

Abstract:
1. A despreading apparatus supporting a plurality of symbol rates, comprising: a despreading by four assemblies configured to receive a chip stream and to generate a first reduced rate symbol stream therefrom, the first reduced rate symbol stream having a symbol rate which is one fourth the rate of said chip stream; a first rate converter configured to receive the first reduced rate symbol stream and to generate a second reduced rate symbol stream therefrom, the second reduced rate symbol stream having a symbol rate one eighth that of the chip stream; a plurality of five additional rate converters coupled together in sequence, a first of the five additional rate converters having an input for receiving the second reduced rate symbol stream, each individual rate converter in the five additional rate converters producing a reduced rate symbol stream having a data rate one half that of an input symbol stream to the individual rate converter; and wherein said despreading by four assemblies, said first rate converter and said plurality of five additional rate converters, in combination generate a total of seven reduced rate symbol streams.