Patent ID: 6072548
Filing Date: 2000-06-06
Classification: G06T,H04N

Abstract:
A video decoder comprising:a segment register configured to indicate de-allocated memory segments;a bitstream decoder coupled to the segment register to determine target memory segments, configured to receive a bitstream, configured to convert the bitstream into image data, and configured to write said image data into said target memory segments;a FIFO (first-in-first-out) buffer coupled to the bitstream decoder to receive pointers to said target memory segments;a display processor coupled to retrieve said pointers from the FIFO buffer, configured to read said image data from said target memory segments, configured to convert said image data into a stream of pixel data, and coupled to the segment register to de-allocate said target memory segments;wherein the bitstream decoder is configured to provide an EOF (end-of-field) token to the FIFO buffer to mark an end to the image data for a field.