Patent ID: 6247153
Filing Date: 2001-06-12
Classification: G11C

Abstract:
A memory testing method of a semiconductor memory device having a plurality of memory banks, each memory bank having a plurality of memory blocks, each memory block having a plurality of memory cell arrays, each memory cell array having a plurality of memory cells, each memory cell allocated to physical addresses composed of row addresses and column addresses, the method comprising the steps of:(1) selecting one of the memory banks and writing data to all the memory cells formed in the selected memory bank which are allocated to first addresses which are physical;(2) sequentially selecting the memory banks one by one and performing the step (1);(3) generating virtual second addresses, for differentiating the memory cells of the first addresses; and(4) sequentially reading out data from the memory cells of the first addresses while changing the bits of the first and second addresses, to the outside of the semiconductor memory device through data pins, and determining a memory cell array to which a defective memory cell belongs, using the first and second addresses and the numbers of the data pins through which the data are output, if the read data is not the same as the data written in the step (1) or (2).