Patent ID: 8780974
Filing Date: 2014-07-15
Classification: H03L

Abstract:
1. A digital PLL circuit receiving a reference signal and outputting a clock signal with a frequency obtained by multiplying a frequency of the reference signal by a value indicating a predetermined magnification ratio and containing an integer portion and a fractional portion, the circuit comprising: a controlled oscillator configured to receive a control amount and change the frequency of the clock signal output from the digital PLL circuit in accordance with the received control amount; a first counter configured to count the clock signal with the frequency changed by the controlled oscillator; a second counter configured to increment the predetermined magnification ratio in response to a retiming signal obtained by retiming the reference signal with the clock signal from the controlled oscillator; a comparator configured to compare a count value of the first counter to an integer portion of a count value of the second counter and output the difference as a phase error of the integer portion; a minute phase error generator configured to generate a plurality of threshold values close to an amplitude value of the reference signal based on the fractional portion of the count value of the second counter, detect the amplitude value of the reference signal based on the plurality of threshold values, and generate minute phase error information as a phase error of the fractional portion between the reference signal and the output clock signal from the controlled oscillator based on the detected amplitude value; a filter section configured to receive the phase error of the integer portion from the comparator and the minute phase error information as the phase error of the fractional portion from the minute phase error generator, and smooth a sum of the two phase errors; and a control amount generator configured to generate and output the control amount for the controlled oscillator based on an output of the filter section.