Patent ID: 7383630
Filing Date: 2008-06-10
Classification: H01L,H05K,Y10T

Abstract:
1. A method for forming a circuit plate containing conductive traces for electrical connections among electronic components to be mounted on the circuit plate, said method comprising: preparing a substrate having a dielectric portion that has a planar circuit-forming surface; forming an insulating layer on the circuit-forming surface; forming a pattern of first holes in the insulating layer using photolithographic techniques; forming a conductive layer on the insulating layer such that a portion of the conductive layer completely fills the first holes in the insulating layer; grinding the conductive layer such that the portion of the conductive layer, which fills the first holes, remains in the first holes, and that the remainder of the conductive layer is removed therefrom, thereby forming a pattern of conductive traces on the substrate; forming a dielectric protective layer that covers the insulating layer and the conductive traces; forming a pattern of second holes in the protective layer using photolithographic techniques such that a portion of each of the conductive traces is accessible through a respective one of the second holes; and forming a pattern of conductive bumps such that each of the conductive bumps extends into a respective one of the second holes to connect electrically with a respective one of the conductive traces and that each of the conductive bumps protrudes outwardly from the respective one of the second holes.