Patent ID: 8549277
Filing Date: 2013-10-01
Classification: G06F

Abstract:
1. A server system comprising: a baseboard management chip (BMC) comprising a first chip-selecting signal output terminal, a second chip-selecting signal output terminal, at first updating output terminal and a controlling input terminal; a basic input/output system (BIOS) chip comprising a second chip-selecting signal input terminal and an updating input terminal; an intelligent platform management interface (IPMI) comprising a controlling output terminal; and a diplexer comprising a first input terminal and an updating output terminal, the first input terminal of the diplexer electrically coupled to the first updating output terminal of BMC, the updating output terminal of the diplexer electrically coupled to the updating input terminal of the BIOS chip, the controlling output terminal of the IPMI electrically coupled to the controlling input terminal of the BMC, the first chip-selecting signal output terminal electrically coupled to a first chip-selecting signal input terminal of a BMC memory, and the second chip-selecting signal input terminal of the BIOS chip electrically coupled to the second chip-selecting signal output terminal of the BMC.