Patent ID: 7558895
Filing Date: 2009-07-07
Classification: G06F

Abstract:
1. Interconnect logic for coupling master logic units and slave logic units within a data processing apparatus to enable transactions to be performed, each transaction comprising an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit, at least one data transfer being a response transfer from the slave logic unit to the master logic unit, each transaction having a transaction identifier associated therewith, the interconnect logic comprising: a plurality of connection paths operable to provide at least one address channel for carrying address transfers, and at least one data channel for carrying data transfers; and ID aliasing logic associated with at least a subset of said slave logic units, each slave logic unit in said at least a subset being able to issue response transfers for different transactions out of order with respect to the order of receipt by that slave logic unit of the address transfers of those transactions; for at least a subset of transactions, if the slave logic unit involved in that transaction is associated with the ID aliasing logic, the ID aliasing logic being operable: (a) to replace the transaction identifier for that transaction with a predetermined identifier and then to forward the address transfer of that transaction along with the predetermined identifier to the slave logic unit; (b) for any response transfer issued by the slave logic unit with the predetermined identifier, to replace the predetermined identifier with the transaction identifier removed at said step (a) to enable the routing of that response transfer over the connection paths of the interconnect logic to the master logic unit associated with that transaction.