Patent ID: 6646951
Filing Date: 2003-11-11
Classification: G11C

Abstract:
An address decoder for a memory array, comprising:a pre-decode stage comprising logic circuitry adapted to partially decoding an address input; and a final decode stage comprising additional logic circuitry adapted to further decoding the partially decoded address input and selecting an address line within the memory array, wherein the logic circuitry of the pre-decode stage comprises: a first set of logic gates, and a second set of logic gates, wherein the logic gates of the first set input a first combination of one or more bits of the address input, wherein the logic gates of the second set input a second combination of one or more bits of the address input, and wherein the first combination and the second combination are chosen such that lengths of wires from the first set of logic gates to the final decode stage are substantially the same and lengths of wires from the second set of logic gates to the final decode stage are substantially the same.