Patent ID: 7464316
Filing Date: 2008-12-09
Classification: H03M

Abstract:
1. A decoder, comprising: control logic for receiving a symbol block and controlling an iterative decoding process upon the symbol block, the symbol block being characterizable by a trellis representing possible encoding state changes over time; an interleaver comprising interleaving control logic and interleaving memory, the interleaving control logic reading extrinsic values from the interleaving memory calculated during a previous iteration and writing extrinsic values to the interleaving memory newly calculated during another iteration in accordance with a predetermined interleaving pattern; gamma logic for iteratively producing non-normalized branch metric values in response to previously calculated extrinsic values read from the interleaving memory and received symbol information; alpha logic for iteratively producing alpha probabilities of each state in the trellis recursively traversed in a forward time direction; beta logic for iteratively producing beta probabilities of each state in the trellis recursively traversed in a reverse time direction; log-likelihood logic for iteratively calculating a log-likelihood ratio in response to the alpha probabilities, beta probabilities, and non-normalized branch metric values; extrinsic value calculation logic for iteratively providing newly calculated extrinsic values in response to the difference of the log-likelihood ratios and the previously calculated extrinsic values, wherein the inverse of a normalization factor has been applied to the previously calculated extrinsic values before calculating the difference, and wherein the normalization factor is applied to the newly calculated extrinsic values before being written to interleaving memory by the interleaving control logic; and decision logic for deciding bit states in response to corresponding log-likelihood ratios.