Patent ID: 6570916
Filing Date: 2003-05-27
Classification: H03L,H04L

Abstract:
An adaptive equalization circuit, comprising;a digital phase locked loop having an input and an output; a window slicer having an input and a first output; a first timing capture circuit having a first input, a second input, a third input and an output, wherein the second input of the first timing capture circuit is coupled to the first output of the window slicer and the third input of the first timing capture circuit is coupled to the output of the digital phase locked loop; an adaptive control circuit having a first input, a second input and an output, wherein the first input of the adaptive control circuit is coupled to the output of the first timing capture circuit; an equalizer circuit having a first input, a second input and an output, wherein the first input of the equalizer circuit receives a data signal, the second input of the equalizer circuit is coupled to the output of the adaptive control circuit and the output is coupled to the input of the window slicer; a delay line circuit having a first input, a second input and an output, wherein the first input of the delay line circuit serves as the first input of the first timing capture circuit, the second input of the delay line circuit serves as the second input of the first timing capture circuit; and a sampler circuit having a first input, a second input and an output, wherein the first input of the sampler circuit serves as the third input of the first timing capture circuit, the second input of the sampler circuit is coupled to the output of the delay line circuit, and the output of the sampler circuit serves as the output of the first timing capture circuit.