Patent ID: 6278637
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells each for storing a data, said memory cells including a first memory cell for storing a high level signal and a second memory cell for storing a low level signal;a data read section including first through third sense amplifiers, said first and second sense amplifiers reading data from said first and second memory cells, respectively, said third sense amplifier reading data from a memory cell specified by an address signal;an internal clock signal generator for generating first and second clock signals complementary to each other;an echo clock generator including first and second data registers for responding to said first and second clock signals, respectively, to latch data from said first and second sense amplifiers, respectively, and a first output buffer for alternately receiving data from said first and second data registers to output an echo clock signal; anda data output section including a third data register for responding to said first clock signal to latch data from said third sense amplifier and a second output buffer for receiving data from said third data register to output read data.