Patent ID: 8473640
Filing Date: 2013-06-25
Classification: H04B,H04L

Abstract:
1. A single-chip multi-sublayer PHY to support 10 Gigabit digital serial communications, said single-chip comprising: a Physical Media Dependent (PMD) transmit/receive Complementary Metal Oxide Semiconductor (CMOS) sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation, wherein said PMD transmit/receive CMOS sublayer comprises a PMD transmitter and a PMD receiver; and a 10 Gigabit Attachment Unit Interface (XAUI) transmit/receive CMOS sublayer supporting at least 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation, wherein said XAUI transmit/receive CMOS sublayer comprises a XAUI transmitter and a XAUI receiver, wherein said PMD transmitter and said XAUI transmitter are operable to switch between at least one internally generated reference clock and at least one externally generated reference clock to support the 10 Gigabit digital serial communications based upon an asynchronous mode or synchronous mode, wherein said single-chip operates in said synchronous mode using said at least one internally generated reference clock and said single-chip operates in said asynchronous mode using said at least one externally generated reference clock.