Patent ID: 6256256
Filing Date: 2001-07-03
Classification: G11C

Abstract:
A frame buffer memory comprising:an array of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines;a first port for accessing selected ones of said memory cells using said first wordline and said first bitline of corresponding ones of said rows and columns, said first port associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses by a CPU using a time base and access type required by said CPU; anda second port for accessing selected ones of said memory cells using said second wordline and said second bitline of corresponding ones of said rows and columns, said second port associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a display controller using a time base and access type required by said display controller.