Patent ID: 7443033
Filing Date: 2008-10-28
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; an ESD circuit in or on said silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer; a polymer layer over said passivation layer; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and a third interconnecting structure in said polymer layer and over said passivation layer, wherein said ESD circuit is connected to said first internal circuit and to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.