Patent ID: 6346827
Filing Date: 2002-02-12
Classification: G11C

Abstract:
For use in a programmable logic device that programmably accommodates a plurality of logic signalling standards, at least one of said logic signalling standards requiring a reference voltage, a programmable input/output circuit comprising:an input/output terminal; an input/output buffer coupled to said input/output terminal for buffering input/output signals between said input/output terminal and other circuitry of said programmable logic device; and a programmable reference voltage clamp circuit having (a) a first programmable condition in which a reference voltage is passed from said input/output terminal to reference voltage circuitry of said programmable logic device, said input/output buffer being disconnected when said programmable reference voltage clamp is in said first programmable condition, and (b) a second programmable condition in which voltage on said input/output terminal is prevented from being passed through said programmable reference voltage clamp circuit to said reference voltage circuitry regardless of magnitude of said voltage on said input/output terminal, said input/output buffer being connected in an operable condition when said programmable reference voltage clamp circuit is in said second programmable condition, said programmable reference voltage clamp circuit having a selection input for controlling when said programmable reference voltage clamp circuit is in said first programmable condition and when said programmable reference voltage clamp circuit is in said second programmable condition.