Patent ID: 6414726
Filing Date: 2002-07-02
Classification: G09G,H04L,H04N

Abstract:
Packet identification circuitry, comprising:packet header decoder for extracting a portion of data from a packet header, said portion indicating at least a certain packet type; and associative memory coupled to said decoder for storing reference data corresponding to a plurality of packet types, for simultaneously determining if a piece of said portion of data matches any one of said reference data stored in said memory, and for outputting a signal representative of said matching, wherein the associative memory comprises an input port coupled to the packet header decoder to receive the portion of data extracted from a packet header and a network of rows and columns of memory cells each comprising: a set of charge transistors for storing the reference data received on the input port, such that each row stores a byte of reference data corresponding to one of the plurality of packet types; and a set of transistors assembled as a comparator ensuing the simultaneous comparison between the portion of data extracted from a packet header and of the reference data stored in the charge transistors so as to deliver, when a reference byte stored in a memory cell row is identical to a byte present on the input port, a pairing signal to an address coding system for indicating which row contained the identical reference byte.