Patent ID: 6765227
Filing Date: 2004-07-20
Classification: H01L,Y10S

Abstract:
A semiconductor-on-insulator (SOI) wafer having at least one active device formed therefrom comprising:a silicon substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer having an upper silicon layer disposed on a silicon-germanium layer, the silicon-germanium layer disposed on a lower silicon layer, wherein the silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Ã¥ to about 400 Ã¥ thick; and wherein the active device includes a source and a drain formed in the active layer with a body region between the source and the drain, and a gate formed over the body region and having a gate electrode separated from the body by a gate dielectric, the gate controlling a channel interposed between the source and the drain and within the silicon-germanium layer and, wherein the source and the drain include extensions and deep doped regions, the channel being interposed between the extension of the source and the extension of the drain.