Patent ID: 9112752
Filing Date: 2015-08-18
Classification: G06F,H04L

Abstract:
1. An apparatus comprising: a communication interface for providing an interface between a data link and a data processor, the data processor being configured to support an operating system, a virtual address space and one or more logical data ports, the logical data ports existing within the operating system, the communication interface comprising at least one of a processor and circuitry to: apply first data received over the link and addressed to one of said one or more logical data ports to a first queue associated with the said one logical data port, said first queue being located in the virtual address space, analyse said first data to determine whether said first data meets one or more predefined criteria, wherein one of the predefined criteria is that the handling of said first data directed to said one logical data port is blocked, determine, based on said analysis, that the handling of said first data directed to the said one logical data port is blocked, and in response to determining that the handling of said first data directed to the said one logical data port is blocked, i) generate a message indicating the said one logical data port, ii) apply the message to a second queue located in the address space of the operating system and iii) transmit an interrupt to the operating system, said address space of said first queue being different to that of the second queue, and in response to determining that the handling of said first data directed to the said one logical data port is not blocked, handling the first data without the operating system.