Patent ID: 6542392
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A content addressable memory, comprising:ternary cells which are arranged in rows and columns, and each stores therein â€œ0â€ , â€œ1â€ , or invalid data, wherein both â€œ0â€  and â€œ1â€  are valid data; valid data detection circuits, each of which is provided for a corresponding one of said ternary cells; and longest-match detection circuits, each of which is provided for a corresponding one of said ternary cells; wherein a valid data detection circuit provided for a first ternary cell located at a given bit position in a first row informs a second ternary cell located at said given bit position on a second row of presence of valid data if said first ternary cell has valid data stored therein and if entry data of said first row matches an entry key; and a longest-match detection circuit provided for said second ternary cell located at said given bit position on said second row finds entry data of said second row to be invalid if said second ternary cell has invalid data stored therein and if said valid data detection circuit is informing said longest-match detection circuit of the presence of valid data.