Patent ID: 6442627
Filing Date: 2002-08-27
Classification: G06F

Abstract:
An output FIFO data transfer control device comprising:a plurality of intermediate buffers respectively disposed in a plurality of processing units included in an arithmetic core that operates based on an instruction pipeline, each of said plurality of intermediate buffers storing data on an arithmetic result produced by each of said plurality of processing units; output control means including one or more output FIFOs each of which receives data furnished by each of said plurality of processing units and temporarily stores the data therein, said output control means furnishing data stored in said output FIFOs to outside said output FIFO data transfer control device in response to a predetermined signal applied thereto; write/read pointer generating means for, when an instruction of data transfer from at least one of said plurality of processing units to said output FIFOs is issued upon execution of a microcode, generating a write pointer identifying a specific location where data on an arithmetic result produced by said at least one of said plurality of processing units associated with said instruction is to be stored in said intermediate buffer of said at least one of said plurality of processing units, and for generating a read pointer identifying a specific location where data, which is written into said intermediate buffer according to said write pointer, is to be read out of said intermediate buffer of said at least one of said plurality of processing units; transfer mode setting means for setting a transfer mode identifying which at least one of said plurality of processing units is to transfer data on an arithmetic result upon the execution of the microcode, and for sequentially furnishing a read enable signal to said at least one of said plurality of processing units so as to read out the data from said intermediate buffer of said at least one of said plurality of processing units; bus means on which the data is sent out in response to said read enable signal by said at least one of said plurality of processing units; data input means for receiving the data sent out on said bus means and for writing the data into a register thereof; and data output means for furnishing the data written into the register of said data input means to said output FIFOs of said output control means.