Patent ID: 6498366
Filing Date: 2002-12-24
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a semiconductor substrate with an arsenic as an impurity and a first conductive type layer formed on said semiconductor substrate, said semiconductor substrate having a rough surface opposite said first conductive type layer; a MOS structure formed in the first conductive type layer, having a second conductive type region, a channel region provided in the second conductive type region to be a first conductive type channel by a gate electrode formed on the second conductive type region; a first metal electrode contacting said second conductive type region; a second metal electrode directly contacting said rough surface of said semiconductor substrate, said rough surface having an impurity concentration, the impurity concentration being substantially provided with an arsenic concentration inherent in the semiconductor substrate, whereby an electric current flows in said MOS structure in a direction of a thickness of said semiconductor substrate between said first and second metal electrodes, wherein said rough surface is free from ion implantation, whereby the impurity concentration of the rough surface is substantially provided with said arsenic concentration inherent in the semiconductor substrate.