Patent ID: 6057729
Filing Date: 2000-05-02
Classification: G06F,H01L

Abstract:
A parasitic suppression circuit for a power integrated circuit that operates at plural operating frequencies, the parasitic suppression circuit comprising:a resistance and an inductance for suppressing parasitic in the power integrated circuit;plural capacitors selectively connected in parallel to each other and to suppress parasitics in the power integrated circuit, said resistance, inductance, and plural capacitors defining an RLC circuit having a resonance point that varies as a function of a number of said plural capacitors that are selectively connected in said RLC circuit;an operating frequency signal circuit for generating a signal having n-outputs that together are indicative of an operating frequency of the power integrated circuit; andplural first switches selectively connecting said plural capacitors in said RLC circuit, each of said plural first switches being operated by a respective one of said n-outputs and being connected to a respective one of said plural capacitors.