Patent ID: 6660652
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method for fabricating a semiconductor device for forming a metal interconnection contact hole exposing a gate electrode in a peripheral circuit region of a semiconductor substrate and a metal interconnection contact on the semiconductor substrate, a method for fabricating a semiconductor device comprising the steps of:forming a MOSFET having the gate electrode and source/drain regions on the semiconductor substrate, a mask insulating film pattern being provided at the upper portion of the gate electrode, and an insulating film spacer being provided at the side walls of the gate electrode; forming a first interlayer insulating film having therein a contact plug, the contact plug contacting a bit line contact and a storage electrode contact on the semiconductor substrate; forming an etch barrier film over the entire structure; forming a bit line and a capacitor in contact with the contact plug; forming a second interlayer insulating film over the entire structure; forming a photoresist film pattern exposing the intended locations of the metal interconnection contacts on the second interlayer insulating film; and forming the metal interconnection contact hole by etching the stacked structure of the second interlayer insulating film, the etch barrier film and the mask insulating film pattern, and the stacked structure of the etch barrier film and the first interlayer insulating film according to a three-step etching process, by employing the photoresist film pattern as an etching mask, and removing the photoresist film pattern.