Patent ID: 6421698
Filing Date: 2002-07-16
Classification: G06T,H04N

Abstract:
An integrated processor comprising:a processing circuit, wherein the processing circuit comprises: a first adder having input ports coupled to receive operands that are neighboring pixel values in an image array; a line buffer having an input port coupled to the adder; a second adder having a first input port coupled to the first adder and a second input port coupled to the line buffer; and a results bus coupled to write results from the second adder to either of the first memory and the second memory; a first memory coupled the processing circuit; and a second memory coupled to the processing circuit, wherein: the processor is operable in a first mode in which the first memory stores pixel values of a search window and the second memory stores pixel values in a reference block for which a matching block in the search window is sought; and the processor is operable in a second mode in which the second memory operates as a register file having storage locations identified by register numbers in instructions that the processor executes.