Patent ID: 6472903
Filing Date: 2002-10-29
Classification: H03K

Abstract:
An input/output structure for a programmable logic device that accommodates a plurality of logic signalling standards having differing power requirements, said input/output structure comprising:a plurality of input/output terminals; a plurality of input/output circuits associated with said plurality of input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic device; and a plurality of power bus conductors; wherein: when a respective one of said plurality of input/output circuits is operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor provides power compatible with power requirements of said one of said standards in accordance with which said respective circuit is operated.