Patent ID: 7132326
Filing Date: 2006-11-07
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming an interlayer insulating layer on a semiconductor substrate; forming at least two contact plugs that penetrate the interlayer insulating layer and contact the semiconductor substrate, the at least two contact plugs having an upper surface and an upper sidewall that are higher than a top of the interlayer insulating layer; covering the contact plugs and the interlayer insulating layer with an etch stop layer; covering the etch stop layer with a molding layer; etching the molding layer to form a molding pattern having at least two openings, a bottom of the at least two openings including a central region that exposes the etch stop layer on the upper surface of the at least two contact plugs and a peripheral region extending away from the central region and the etch stop layer on the upper sidewall; etching the etch stop layer to expose the upper surface of the contact plugs; forming at least two charge storage electrodes, each of the at least two charge storage electrode in contact with one of the contact plugs inside one of the at least two openings; and removing the molding pattern to expose the at least two charge storage electrodes and to form a space between the at least two charge storage electrodes and the etch stop layer on the interlayer insulating layer.