Patent ID: 6594734
Filing Date: 2003-07-15
Classification: G06F

Abstract:
A microprocessor including:an execution unit to trigger a snoop if a store into a memory occurs; a translation lookaside buffer (TLB) having a content addressable memory (CAM) and receiving a physical address indicating the location where the store occurred in the memory, the TLB to store page translations between a linear page address and a physical page address pointing to a page of memory having contents stored within a cache, the TLB including a CAM input port responsive to the snoop to compare the physical address received by the TLB with the physical page address stored therein, the TLB includes data bits providing an indication as to what portion of a page in memory has its contents stored in the cache; and snoop logic coupled to the TLB, the snoop logic to provide further comparison of the data bits with the physical address received by the TLB after the store into the memory, the comparison provided by the snoop logic indicating if information was modified within a portion of a page of memory correlating to information potentially located within the cache.