Patent ID: 6154073
Filing Date: 2000-11-28
Classification: H03L

Abstract:
A Delay Locked Loop device comprising:delay means for receiving an external clock and generating an internal clock, said delay means having a first to Nth delay elements delaying the received external clock in order to match the phase of the external clock with the phase of the internal clock;phase detector for outputting a detect signal discriminating the difference between the phase of the internal clock and phase of the external clock;counter for receiving the detect signal from the phase detector and outputting a first control signal and a second control signal, said first control signal controlling the phase of the internal clock generated from the delay means; andcharge pump for generating a pump voltage having a desired voltage level in accordance with said second control signal, said pump voltage controlling said first to Nth delay elements of the delay means;wherein the frequency of the external clock is identical with the frequency of the internal clock, and the internal clock generated from the delay means is one of the output signal from the first to Nth delay elements in accordance with the first control signal from the counter.