Patent ID: 6153906
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A flash memory, comprising:a substrate;an oxide layer, on the substrate;a first polysilicon layer on the oxide layer;a first inter-poly dielectric layer, on the first polysilicon layer;a second polysilicon layer, covering the first iner-poly dielectric layer and extending as a polysilicon strip on the substrate;a tunnel diffusion region next to a first side of the first polysilicon layer in the substrate and extending to a portion of the substrate under the first polysilicon laeyr;a doped region, next to a second side of the first polysilicon layer in the substrate;a second inter-poly dielectric layer, covering the tunnel diffusion region, the doped region, and the second polysilicon layer; anda third polysilicon layer, on the second inter-poly dielectric layer and extending perpendicular to the second polysilicon layer.