Patent ID: 7139881
Filing Date: 2006-11-21
Classification: G06F

Abstract:
1. A semiconductor device, comprising: a plurality of systems within the semiconductor device, each system comprising at least one processing device and a local memory structure, wherein each said processing device is electrically coupled to each said local memory structure within each said system, wherein each said local memory structure is electrically coupled to each of the remaining local memory structures, wherein each said local memory structure is adapted to share address space with each of said processing devices, wherein each said processing device is adapted to transmit data and instructions to each said local memory structure, wherein each said processing device is further adapted to retrieve data and instructions from each said local memory structure, wherein each said local memory structure comprises a memory device coupled to a memory control device, wherein each said memory control device is adapted to control a flow of said data and instructions between each processing device and each memory device, wherein each said memory device comprises a decoder and a read queue, wherein a decoder in a first system within the plurality of systems is adapted to accept data and instructions from a second system within the plurality of systems and transmit The data to hot a memory device and a read queue in the first system, and wherein a processing device in the first system is adapted to read the data from the read queue of the first system instead of from the memory device of the first system if the second system is transmitting the data to a memory location in the memory device at same time as the processing device is trying to read the data from the memory location.