Patent ID: 9007858
Filing Date: 2015-04-14
Classification: G11C

Abstract:
1. A method for reading an SRAM cell connected to a local bit line and storing one of a first logical value or a second logical value in a domino SRAM, comprising: precharging a global bit line to a non-zero precharge voltage for a period prior to a non-read operation; charging the global bit line to a boosted voltage that is greater than the precharge voltage for a period prior to a read operation; maintaining the global bit line at the boosted voltage for reading the first logical value stored in the SRAM cell; discharging the global bit line to a discharge voltage that is less than the precharge voltage for reading the second logical value stored in the SRAM cell; sensing the boosted voltage on the global bit line for the first logical value and the discharge voltage on the global bit line for the second logical value; and outputting the first logical value in response to sensing the boosted voltage on the global bit line and outputting the second logical value in response to sensing the discharge voltage on the global bit line.