Patent ID: 6693473
Filing Date: 2004-02-17
Classification: H03L

Abstract:
A delay lock loop circuit receiving a reference clock signal, said delay lock loop (DLL) circuit aligning in time an output clock signal thereof with an internal feedback clock signal, said DLL circuit comprising:a settable voltage regulator configured for receiving an external supply voltage, a settable supply voltage issued by said settable voltage regulator; and a forward delay circuit powered at least in part by said settable supply voltage, said forward delay circuit receiving said reference clock signal, said forward delay circuit issuing said output clock signal, said forward delay circuit adjustable shifting in time said output clock signal relative to said reference clock signal; a feedback delay circuit receiving said output clock signal and issuing a feedback clock signal; a comparator circuit receiving said feedback clock signal and said reference clock signal, said comparator circuit issuing a compare signal indicative of the phase of said reference clock signal relative to said feedback clock signal; and a control circuit receiving said compare signal and issuing a control signal, said control signal being received by said forward delay circuit.