Patent ID: 6195280
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A data processing system comprising:a processor coupled via a bus to a storage system, a memory system, and an input/output system, wherein a memory system is located within one of said processor, storage system, memory system, or input/output system, said memory system further comprising:a plurality of memory cells wherein said plurality of memory cells is partitioned into first and second memory cell groups;a first bitline coupled to said first memory group;a second bitline coupled to said second memory group;a third bitline coupled to said first and second bitlines for communicating read data from said first and second memory cell groups;a data line coupled to said first and second bitlines for communicating write data to said first and second memory cell groups;a first precharge unit coupled to the first and second bitlines for precharging said first and second bitlines in response to a first precharge signal; anda second precharge unit coupled to the third bitline for precharging the third bitline in response to a second precharge signal.