Patent ID: 6563545
Filing Date: 2003-05-13
Classification: H04N

Abstract:
A synchronous processor circuit arranged in a display for reproducing a synchronizing signal from a composite signal provided by a video signal source for stabilizing synchronization in the display, the circuit comprising:a low pass filter for outputting a vertical synchronization separating signal by separating a vertical synchronizing signal from said composite signal; a frequency divider circuit for outputting a vertical phase detection signal obtained by frequency-dividing said vertical synchronization separating signal into 1/n (where n is multiple of 2); a plurality of phase delay circuits for outputting phase-delayed signals each differently delayed in phase with respect to a horizontal synchronizing signal included in said composite signal; and a vertical synchronizing signal reproduction circuit for outputting said synchronizing signal having a phase relationship with said horizontal synchronizing signal determined by receiving said vertical synchronization separating signal, said vertical phase detection signal, and said plurality of phase-delayed signals.