Patent ID: 6724772
Filing Date: 2004-04-20
Classification: H04J

Abstract:
An integrated circuit, the integrated circuit comprising:a bus; a clock coupled to the bus which provides a clock signal to the bus, wherein the clock signal has a clock rate, wherein the bus operates according to the clock rate; a plurality of modules, wherein each of the plurality of modules is coupled to the bus, wherein said each of the plurality of modules is operable to transfer data on the bus and to receive data on the bus; and a bus controller coupled to the bus which controls data transfers on the bus; wherein one or more of the plurality of modules is operable to generate requests to the bus controller to perform data transfers on the bus, wherein each of the requests to perform data transfers comprises: an identifier which identifies one or more receiving modules; a transfer size value which specifies the amount of data to be transferred; and a timing value providing a time frame within which the requested data transfer should occur; and wherein the bus controller receives the requests to perform data transfers from one or more of the plurality of modules, wherein, for each said request, the bus controller examines the timing value provided with said request and selectively allocates bandwidth on the bus based on said timing value.