Patent ID: 6768345
Filing Date: 2004-07-27
Classification: H03K

Abstract:
A method for clock control of a cascaded chain of clocked full-rail differential logic circuits with sense amplifier and shut-off, said method comprising:providing a first supply voltage; providing a second supply voltage; providing a first clocked full-rail differential logic circuit with sense amplifier and shut-off, said first clocked full-rail differential logic circuit with sense amplifier and shut-off comprising: a first clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal; a first clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal; a first clocked full-rail differential logic circuit with sense amplifier and shut-off first node, said first clocked full-rail differential logic circuit with sense amplifier and shut-off first node being coupled to said first supply voltage; a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first clocked full-rail differential logic circuit with sense amplifier and shut-off first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said first clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first clocked full-rail differential logic circuit with sense amplifier and shut-off first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said first clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said first clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; said fourth transistor first flow electrode being coupled to said first clocked full-rail differential logic circuit with sense amplifier and shut-off first node, said fourth transistor second flow electrode being coupled to said first clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal, sad fourth transistor control electrode being couple to a first clock signal; a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; said fifth transistor first flow electrode being coupled to said first clocked full-rail differential logic circuit with sense amplifier and shut-off first node, said fifth transistor second flow electrode being coupled to said first clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal, said fifth transistor control electrode being coupled to said first clock signal; a first clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit coupled between said first clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal and said first clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal, said first clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit having an input terminal coupled to a second clock signal; a first locked full-rail differential logic circuit with sense amplifier and shut-off shut-off device coupled between said first clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal and said first clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal; a logic network, said logic network comprising: at least one logic network input terminal; a logic network out terminal; and a logic network outBar terminal, said logic network out terminal being coupled to said first clocked full-rail differential logic circuit with sense amplifier and shut-off shut-off device and said logic network outBar terminal being couple to said first clocked full-rail differential logic circuit with sense amplifier and shut-off shut-off device; providing a second clocked full-rail differential logic circuit with sense amplifier and shut-off, said second clocked full-rail differential logic circuit with sense amplifier and shut-off comprising: a second clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal; a second clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal; a second clocked full-rail differential logic circuit with sense amplifier and shut-off first node, said second clocked full-rail differential logic circuit with sense amplifier and shut-off first node being coupled to said first supply voltage; a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said second clocked full-rail differential logic circuit with sense amplifier an shut-off first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said second clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second clocked full rail differential logic circuit with sense amplifier and shut-off first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said second clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said second clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said second clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; said fourth transistor first flow electrode being coupled to said second clocked full-rail differential logic circuit with sense amplifier and shut-off first node, said fourth transistor second flow electrode being coupled to said second clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal, said fourth transistor control electrode being couple to said second clock signal; a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; said fifth transistor first flow electrode being coupled to said second clocked full-rail differential logic circuit with sense amplifier and shut-off first node, said fifth transistor second flow electrode being coupled to said second locked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal, said fifth transistor control electrode being couple to said second clock signal; a second clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit coupled between said second clocked full-rail differential logic circuit with sense amplifier an shut-off out terminal and said second clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal, said second clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit having an input terminal coupled to a third clock signal; a second clocked full-rail differential logic circuit with sense amplifier and shut-off shut-off device couple between said second clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal and said second clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal; a logic network, said logic network comprising: at least one logic network input terminal; a logic network out terminal; and a logic network outBar terminal, sad logic network out terminal being coupled to said second clocked full-rail differential logic circuit with sense amplifier and shut-off shut-off device and said logic network outBar terminal being couple to said second clocked full-rail differential logic circuit with sense amplifier and shut-off shut-off device; delaying said second clock signal with respect to said first clock signal by a predetermined delay time; and delaying said third clock signal with respect to said second clock signal by a predetermined delay time.