Patent ID: 7514736
Filing Date: 2009-04-07
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor substrate having a memory cell array region and a peripheral region; a plurality of capacitors in the memory cell array region, each having a storage electrode, a dielectric layer on the storage electrode, and a plate electrode on the dielectric layer, wherein an extended portion of the plate electrode extends in a direction toward the peripheral region; a dummy pattern in the peripheral region having a base that is at an elevation above the semiconductor substrate that is the same as a base of the extended portion of the plate electrode, and spaced apart from the extended portion of the plate electrode; an insulating layer formed on the plurality of capacitors in the cell array region and formed on the dummy pattern in the peripheral region; and a first metal contact through the insulating layer between the extended portion of the plate electrode and the dummy pattern, wherein the first metal contact is isolated from each of the plate electrode and the dummy pattern by the insulating layer.