Patent ID: 6724661
Filing Date: 2004-04-20
Classification: G11C

Abstract:
A method for performing an erase operation in a non-volatile memory device comprising a bulk region of a first conductive type, spaced first and second impurity diffusion regions of a second conductive type formed in the bulk region, a charge storing layer formed between the first and the second impurity diffusion regions, and a conductive electrode formed on the charge storing layer, the method comprising the steps of:applying a bulk voltage to the bulk region for a predetermined erase time; applying a gate voltage to the conductive electrode for the predetermined erase time, the gate voltage being greater than or equal to the bulk voltage; applying a first voltage to the first impurity diffusion region during the predetermined erase time, wherein the first voltage is greater than the gate voltage; applying a second voltage to the second impurity diffusion region during the predetermined erase time, wherein the second voltage is greater than the gate voltage, wherein the first and second voltages are different; and switching the first and second voltages at least one time during the predetermined erase time such that the first voltage is applied to the second impurity region while the second voltage is applied to the first impurity region.