Patent ID: 7486120
Filing Date: 2009-02-03
Classification: H03K,H03L

Abstract:
1. A delay ratio adjusting circuit for adjusting a delay ratio for a basic delay element using a reference clock pulse generated with a ring oscillator composed of a plurality of serially connected basic delay elements, comprising: a first delay element array composed of a first number of the serially connected basic delay elements, the reference clock pulse being input to a first basic delay element of the first delay element array and being output from a last basic delay element of the first delay element array; a second delay element array composed of a second number of serially connected adjustment delay elements, the reference clock pulse being input to a first adjustment delay element of the second delay element array and being output from a last adjustment delay element of the second delay element array; and a PLL control circuit for matching a phase of an output pulse of the first delay element array and a phase of an output pulse of the second delay element array so that a constant delay ratio R of an amount of delay of the adjustment delay element to an amount of delay of the basic delay element is obtained, configured to include a phase comparator having two input terminals, to input an output pulse of the first delay element array to one of the input terminals, to input an output pulse of the second delay element array to the other input terminal, to generate a control voltage in accordance with a phase difference detected by the phase comparator and to apply the control voltage to each of the adjustment delay elements; wherein another control voltage that another PLL control circuit connected to the ring oscillator generates is applied to each of the basic delay elements of both the ring oscillator and the first delay element array.