Patent ID: 6316807
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A MISFET comprising:a substrate of a first conductivity type including a trench and an extended trench;an oxide layer that is formed on the sidewalls of the trench and extends over a top surface of the substrate;a gate oxide layer formed on sidewalls of the extended trench and the oxide layer;a gate layer formed on the gate oxide layer, wherein the gate layer and the gate oxide layer are selectively etched so that the top surface of the substrate is exposed in regions adjacent to the trench;a drain located in the top surface of the substrate in at least one of the regions adjacent to the trench;a base of the first conductivity type and a source of the second conductivity type formed in the substrate under the extended trench;a further oxide layer formed inside the trench, inside the extended trench and over the exposed regions of the substrate, wherein a thickness of the further oxide layer inside the trench and inside the extended trench is less than the thickness of the further oxide layer on the exposed regions of the substrate, and wherein a contact hole is provided through the further oxide layer at the bottom of the extended trench that extends to the substrate;an electrical interconnection material that extends through the trench, the extended trench and the contact hole.