Patent ID: 8916443
Filing Date: 2014-12-23
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: providing an active layer; forming adjacent gate structures on the active layer, wherein the adjacent gate structures each have sidewalls; forming first spacers on the sidewalls of the adjacent gate structures; epitaxially growing a raised region on the active layer between the adjacent gate structures; forming at least one trench that extends through the raised region and through the active region, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor, the at least one trench separating the first and the second raised region prior to a silicide formation process that forms both a first silicide area over the first raised region and a second silicide area over the second raised region, the first silicide area extending between a first controllably formed facet located adjacent one of the adjacent gate structures and a first substantially vertical side wall adjacent the at least one trench, the second silicide area extending between a second controllably formed facet located adjacent another one of the adjacent gate structures and a second substantially vertical side wall adjacent the at least one trench, wherein the first and the second substantially vertical side walls create respective extended surface areas for the silicide formation process relative to forming the first and the second raised region following the formation of the at least one trench; forming second spacers within the at least one trench, wherein vertical sides of the second spacers contact a sidewall of the first and second silicide areas, wherein the first raised region and second raised region are electrically isolated by the at least one trench.