Patent ID: 6762095
Filing Date: 2004-07-13
Classification: H01L

Abstract:
A method of fabricating flash memory, comprising the steps of:providing a substrate divided into a memory cell region and a peripheral circuit region; forming a first conductive layer over the substrate; patterning the first conductive layer in the memory cell region to form a first gate conductive layer; forming a gate dielectric layer over the substrate; forming a second conductive layer over the gate dielectric layer; forming a passivation layer over the second conductive layer; removing the passivation layer, the second conductive layer and the first conductive layer in the peripheral circuit region; forming a third conductive layer over the substrate; removing the third conductive layer and the passivation layer in the memory cell region; and patterning the second conductive layer, the gate dielectric layer and the first gate conductive layer in the memory cell region to form a plurality of memory gates and patterning the third conductive layer in the peripheral circuit region to form a plurality of gates, wherein the second conductive layer, the gate dielectric layer and the first gate conductive layer in the memory cell region, and the third conductive layer in the peripheral circuit region are patterned at the same time.