Patent ID: 7746696
Filing Date: 2010-06-29
Classification: G11C

Abstract:
1. A memory comprising: a first storage cell having a first floating node, a first tunneling transistor, a first coupling capacitor and a first bitline transistor, the first floating node including a first tunneling gate of the first tunneling transistor, a first plate of the first coupling capacitor and a first bitline gate of the first bitline transistor; a second storage cell having a second floating node, a second tunneling transistor, a second coupling capacitor and a second bitline transistor, the second floating node including a second tunneling gate of the second tunneling transistor, a second plate of the second coupling capacitor and a second bitline gate of the second bitline transistor; a first inverter coupled to a first bitline value from the first bitline transistor; a second inverter interlaced with the first inverter and coupled to a second bitline value from the second bitline transistor, the second bitline value being complementary to the first bitline value, so as to sense a charge difference between the first floating node and the second floating node and provide a data output value of the memory when a memory read transistor is turned on.