Patent ID: 6411542
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A ferroelectric memory device, comprising:a plurality of word lines arranged in a column direction; a plurality of bit lines and a plurality of source lines arranged in a row direction and crossed said plurality of word lines; and a plurality of unit memory cells arranged in a matrix, wherein each of said plurality of unit memory cells comprises a single ferroelectric transistor which is coupled between corresponding one of said source lines and corresponding one of said bit lines and whose gate is connected to corresponding one of said word lines; wherein said single ferroelectric transistor comprises a well which is connected to one common well line in the column direction and is electrically isolated from common well lines of adjacent different columns; and wherein said single ferroelectric transistor comprises a source commonly connected to said bit line or said source line in the column direction and comprises a drain commonly connected to said bit line or said source line in the column direction.