Patent ID: 6578179
Filing Date: 2003-06-10
Classification: G06F

Abstract:
An LSI layout design apparatus comprising:a processing migration section conducting process migration for converting a first layout data according to a first design standard into a second layout data according to a second design standard and a designated transistor size; an extraction section extracting transistor sizes and parasitic capacitances from the first layout data and the second layout data, respectively, for each node; a delay time calculation section calculating a first delay time from the transistor size and the parasitic capacitance extracted from the first layout data and a driving current value of a transistor based on the first design standard, and calculating a second delay time from the transistor size and the parasitic capacitance extracted from the second layout data and a driving current value of a transistor based on the second design standard; and an optimum value calculation section calculating an optimum value of the transistor size after the process migration in order that the second delay time becomes equal to the first delay time, wherein: said first delay time is calculated from a formula Tpdr=CLr/(IdrÂ·Wr) â€ƒwhere Tpdr is the first delay time, CLr is the parasitic capacitance extracted from the first layout data, Idr is the driving current per unit width of the transistor based on the first design standard, and Wr is the transistor size extracted from the first layout data; and said second delay time is calculated from a formula Tpdm=CLm/(IdmÂ·Wm) â€ƒwhere Tpdm is the second delay time, CLm is the parasitic capacitance extracted from the second layout data, Idm is the driving current per unit width of the transistor based on the second design standard, and Wm is the transistor size extracted from the second layout data.