Patent ID: 7612599
Filing Date: 2009-11-03
Classification: G06F

Abstract:
1. A semiconductor device including a plurality of metal wiring layers, comprising: a clock distribution circuit including a plurality of main clock lines connected to any of a plurality of buffers forming the final stage clock buffers and a plurality of final stage buffers; and a plurality of flip-flops for receiving a clock from any line of the plurality of main clock lines, wherein the plurality of main clock lines are extended in a first direction, wherein the first direction is identical to the direction where a main power supply line of the lowest layer formed on the metal wiring layer is extended, wherein a cell arrangement allowable row is defined with an adjacent main power supply line, wherein the plurality of main clock lines include a first main clock line and a second main clock line, and wherein the number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where the plurality of first flip-flops for receiving the clock from the second main clock line are located.