Patent ID: 7376686
Filing Date: 2008-05-20
Classification: G06F

Abstract:
1. An apparatus for executing an MMX PSADBW instruction, comprising: subtractors, for generating packed differences of packed operands of the instruction and for generating borrow bits associated with each of the packed differences; inverters, coupled to said subtraction logic, for generating an inverse of each of said packed differences; multiplexers, coupled to said inverters and said subtraction logic, each for selecting as an output said packed difference if said associated borrow bit indicates the packed difference is positive, and for selecting as said output said inverse if said associated borrow bit indicates the packed difference is negative; and a first adder, coupled to said multiplexers, configured to add said outputs of said multiplexers to generate a first sum and a first carry; a second adder, coupled to said subtractors, configured to add said borrow bits to generate a second sum and a second carry in parallel with said first adder generating said first sum and carry; a third adder, coupled to said first and second adders, configured to add said first and second sums and carries to generate a result of the PSADBW instruction.