Patent ID: 6512416
Filing Date: 2003-01-28
Classification: G05F,H03F,H03G

Abstract:
A method of varying the gain of an amplifier,wherein the amplifier is comprised of an amplifier array and an automatic gain control (AGC) logic decoder, wherein the amplifier array is further comprised of â€œnâ€  amplifier circuit assemblies, where â€œnâ€  is a positive integer, wherein an â€œithâ€  amplifier circuit assembly of the â€œnâ€  amplifier circuit assemblies has an information input, a control input and one or more amplifier outputs, and the AGC logic decoder is further comprised of â€œnâ€  AGC amplifiers and â€œnâ€  logic circuits, wherein an ith AGC amplifier of the â€œnâ€  AGC amplifiers has two or more inputs and one or more outputs, each output being an AGC control signal, and an ith logic circuit of the â€œnâ€  logic circuits has one or more logic inputs and one or more logic outputs, wherein a first logic output is an amplifier control signal and a second logic output is a shifting signal; the method comprising the steps of: (1) routing an AGC signal to a first input of the ith AGC amplifier; (2) comparing said AGC signal to an ith scaled reference voltage, said ith scaled reference voltage being received at a second input of the ith AGC amplifier for all i between 1 and (nâˆ’q), inclusive, where q is a positive integer less than n; (3) for all â€œiâ€  between 1 and (nâˆ’q), inclusive, generating an ith AGC control signal from the ith AGC amplifier, wherein the ith AGC control signal is a first logic level if said AGC signal is greater than said ith scaled reference voltage, and is a second logic level if said AGC signal is less than said ith scaled reference voltage; (4) for all â€œiâ€  between (nâˆ’q+1) and â€œnâ€ , inclusive, generating an ith AGC control signal from the ith AGC amplifier, wherein the ith AGC control signal is at said first logic level; (5) routing said ith AGC control signal to a first logic input of the ith logic circuit; (6) generating, in the ith logic circuit, the ith shifting signal; (7) for all â€œiâ€  between 1 and â€œmâ€ , inclusive, where â€œmâ€  is a positive integer less than â€œnâ€ , routing the ith shifting signal to a second logic input of the â€œjthâ€  logic circuit, where j=i+p where p is a positive integer equal to (nâˆ’m); (8) generating, in the ith logic circuit, the ith amplifier control signal, wherein the ith amplifier control signal is a first control level when the ith amplifier circuit assembly is to be turned â€œonâ€ , and is a second control level when the ith amplifier circuit assembly is to be turned â€œoffâ€ ; (9) routing the ith amplifier control signal to the control input of the ith amplifier circuit assembly; (10) for all â€œiâ€  between 1 and â€œpâ€ , inclusive, accepting, at the information input of the ith amplifier circuit, an input signal; (11) for all â€œiâ€  between (p+1) and â€œnâ€ , inclusive, accepting, at the information input of the ith amplifier circuit, an ith attenuated input signal; (12) for all â€œiâ€  between 1 and â€œpâ€ , inclusive, amplifying said input signal when the ith amplifier control signal is at said first control level, thereby creating an ith amplified signal; (13) for all â€œiâ€  between (p+1) and â€œnâ€ , inclusive, amplifying said attenuated input signal when the ith amplifier control signal is at said first control level, thereby creating an ith amplified signal; and (14) outputting, from the amplifier output of the ith amplifier circuit, an ith amplifier output signal, wherein said ith amplifier output signal is said ith amplified signal when the ith amplifier control signal is at said first control level, and is a null signal when the ith amplifier control signal is at said second control level.