Patent ID: 6559725
Filing Date: 2003-05-06
Classification: H03L,Y10S

Abstract:
A phase noise reduction system of a frequency synthesizer comprising:a first variable frequency divider for a voltage controlled oscillator which divides an oscillation frequency signal of said voltage controlled oscillator; a second variable frequency divider for a reference oscillator which divides an oscillation frequency signal of said reference oscillator; a lock detection section which initially sets a common first number of frequency division for said first and second variable frequency dividers, subsequently detects locking of frequency signals between said voltage controlled oscillator and said reference oscillator, and then in response to detecting said locking of frequency signals between said voltage controlled oscillator and said reference oscillator switches the setting of number of frequency division from said common first number of frequency division to a second number of frequency division, said common first number of frequency division being smaller than said second number of frequency division; wherein said lock detection section monitors a polarity of a first output signal from said first variable frequency divider for said voltage controlled oscillator and a polarity of a second output signal from said second variable frequency divider for said reference oscillator, and determines that a frequency is locked when the monitored first and second output signals have the same polarity continuously for a predetermined period of time.