Patent ID: 6779096
Filing Date: 2004-08-17
Classification: G06F

Abstract:
An apparatus comprising:a memory controller; a clock signal generator coupled to the memory controller, the clock signal generator coupled to supply a first clock signal and a second clock signal to the memory controller; a first memory bank coupled to the memory controller and to the clock signal generator, the first memory bank to receive a third clock signal from the clock signal generator; and wherein the clock signal generator to generate the first clock signal, the second clock signal and the third clock signal from a single clock source, the first clock signal having a first predetermined phase offset relative to the third clock signal, the second clock signal having a second predetermined phase offset relative to the third clock signal, the first predetermined phase offset determined base on performance of components of the apparatus as determined by the apparatus, the second predetermined phase offset determined based on performance of components of the apparatus as determined by the apparatus.