Patent ID: 7420793
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A circuit system for protecting a capacitor coupled between a voltage supply node and a ground node from an electrostatic discharge (ESD), the circuit system comprising: at least one grounded-gate NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together connected to the ground node, without being coupled to a negative potential; and at least one PN junction diode chain having one or more diodes serially coupled between the voltage supply node and the ground node, wherein the PN junction diode chain has an anode coupled to the voltage supply node and a cathode coupled to the ground node, wherein a combined voltage drop across the PN junction diode chain is smaller than the trigger-on voltage of the NMOS transistor and a capacitor damage voltage, wherein during an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the ground node, and the PN junction diode chain is designed to be triggered on before the ESD current damages the capacitor, thereby protecting the capacitor from ESD induced damages.