Patent ID: 6073247
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A process for synchronizing a computer system with regard to a date which changes over time, said computer system comprising one or more modules (1, 2, 3, 4), each module (1, 2) comprising several processors (10, 11, 12, 13, 20, 21, 22, 23) regulated by a clock (1', 2') specific to said module (1, 2), each processor (10, 11, 12, 13, 20, 21, 22, 23) comprising a private register (16, 17, 18, 19, 26, 27, 28, 29) adapted to contain a value corresponding to said date and to undergo an incrementation by the clock (1', 2') specific to the module (1, 2) comprising said processor (10, 11, 12, 13, 20, 21, 22, 23), characterized in that it comprises the following steps:selecting a processor (10) to function as a master processor of the system, instructing each of the other processors (11, 12, 13, 20, 21, 22, 23) to place said other processors which function as slaves to declare said other processors in a ready state which consists, for each processor (11, 12, 13, 20, 21, 22, 23), in waiting for an authorization from the master processor (10) of the system, without being able to be interrupted;immediately reading the contents of a register (50, 51) common to all processors 10-17, 20-23) of one and the same module (1, 2) by each processor (10, 11, 12, 13, 20, 21, 22, 23) receiving said authorization from the master processor, and writing the contents read in the private register (16, 17, 18, 19, 26, 27, 28, 29) private register without interruption.