Patent ID: 9165840
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A method, comprising: providing a structure comprising a semiconductor substrate, a semiconductor layer provided above said semiconductor substrate and a dielectric layer provided between said semiconductor substrate and said semiconductor layer; removing portions of said semiconductor layer and said dielectric layer in a first part of said structure so that said semiconductor substrate is exposed in said first part of said structure, wherein portions of said dielectric layer and said semiconductor layer in a second part of said structure remain on said semiconductor substrate; forming a semiconductor region comprising first, second and third layers of semiconductor material above said exposed semiconductor substrate in said first part of said structure, said third semiconductor material comprising an upper surface lying in substantially the same plane as the upper surface of said semiconductor layer; forming a first transistor in said second part of said structure, said first transistor comprising an active region provided in said portion of said semiconductor layer in said second part of said structure; forming a trench isolation region providing electrical isolation between said portion of said semiconductor layer in said second part of said structure and said first part of said structure; and wherein said trench isolation region is formed before said portions of said semiconductor layer and said dielectric layer in said first part of said structure are removed.