Patent ID: 7068528
Filing Date: 2006-06-27
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device that has a layout structure including a memory block structured by a plurality of cells, bit line pairs connected to the cells and a plurality of bit line sense amplifier blocks for sensing data of the cells, wherein each of the bit line sense amplifier blocks comprises: a PMOS sense amplifier including first and second PMOS transistors; an NMOS sense amplifier including first and second NMOS transistors; an IO line pair including an IO line and an IO bar line, which are placed between the PMOS sense amplifier and the NMOS sense amplifier; and a first IO switch and a second IO switch, which are connected to one of the bit line pairs and the IO line pair, wherein a gate region of the first PMOS transistor, a gate region of the first NMOS transistor and the first IO switch are respectively arranged at a gate region of the second PMOS transistor, a gate region of the second NMOS transistor and the second IO switch in one direction only at predetermined spaces ΔP, ΔN and ΔI.