Patent ID: 6589813
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A method of fabricating a chip size stack package, the method comprising:applying an insulating layer to a surface of a wafer which has a plurality of semiconductor chips, etching the insulating layer and thereby exposing bond pads of each semiconductor chip; depositing, a metal layer on the insulating layer, patterning the metal layer and thereby forming metal traces, the metal traces having one end which is connected to the exposed bond pads and other ends which extend toward edges of respective semiconductor chips; cutting the wafer along a scribe line, thereby dividing the wafer into the respective semiconductor chips, and exposing the other ends of the metal traces at sides of the insulating layer; coupling upper and lower semiconductor chips to each other by directly coupling the metal traces to each other, which are cut from the wafer and thereby electrically connecting the metal traces with each other; bonding one end of metal wires to the exposed other ends of the metal traces; and molding both sides of the upper and lower semiconductor chips which are coupled to each other, using an encapsulate, in a manner such that the other ends of the metal wires and semiconductor chips are exposed.