Patent ID: 6301597
Filing Date: 2001-10-09
Classification: G06F

Abstract:
An apparatus that performs an arithmetic operation, comprising:first and second operands, wherein each said operand comprises a plurality of dits that comprise two bits, a plurality of blocks that comprise 4 dits, wherein each said block has a most significant dit (MSD), and at least one partition that comprises one of the following: an 8-bit group, a 16-bit group, a 32-bit group, or a 64-bit group;a first plurality of N-NARY logic circuits that perform an arithmetic operation that produces an intermediate sum of said operands or difference between said operands, wherein said intermediate sum or difference further comprises a plurality of 4-dit blocks wherein each said block has a MSD, and at least one said partition, said first plurality of N-NARY logic circuits also comprises dit-level and block-level carry propagate logic;a second plurality of N-NARY logic circuits that produce a plurality of block-level 1-of-N preliminary saturation signals where N=5 that indicate whether a contingent or definite block-level overflow or underflow will occur, each said block-level 1-of-N preliminary saturation signal corresponds to one said block of said intermediate sum;a third plurality of N-NARY logic circuits that resolve contingent block-level underflows and contingent block-level overflows determined by said second plurality of N-NARY logic circuits and produce a plurality of 1-of-N final saturation signals where N=3 that indicates whether a definite block-level overflow or underflow will occur; anda fourth plurality of N-NARY logic circuits that receive said intermediate sum or difference and one or more said final saturation signals and produce a final sum, difference, constant saturation value for signed or unsigned operation overflows, or constant saturation value for signed or unsigned operation underflows.