Patent ID: 6208570
Filing Date: 2001-03-27
Classification: G11C

Abstract:
A semiconductor memory device, comprising:an array of memory cells arranged in rows and columns, the array of memory cells having a normal section and a redundant section;a test mode circuit that receives at least one input signal and provides a redundant test mode indication;a normal decoder section for selecting the normal section of the array of memory cells;a redundant decoder section for selecting the redundant section of the array of memory cells, the redundant decoder section comprising:programmable address selectors for receiving address bits and coupled to a power up node;a redundancy enable circuit coupled to the power up node;a decode gate having inputs coupled to the programmable address selectors and to the redundancy enable circuit; anda test decode having inputs coupled to the decode gate, coupled to a low order of the address bits, and coupled to the redundant test mode indication; anda test address circuit that receives at least one test address, the test address selecting between the normal section and the redundant section when the redundant test mode indication is active.