Patent ID: 6122696
Filing Date: 2000-09-19
Classification: G06F

Abstract:
In a computer system with a processor (CPU) coupled to system memory over a local bus at least 2N bytes wide, and to peripheral devices over a peripheral bus N bytes wide, the local bus having at least first and second bus lanes each N bytes wide respectively for transferring first and second data blocks of N-bytes each, where the computer system includes byte enable control lines used by the CPU to signal, for each data transfer, a byte enable code uniquely identifying each byte of the first and second data blocks that is involved in the data transfer, a CPU-Peripheral bus interface for transferring data between the CPU and a peripheral device, comprising(a) bus interconnect logic external to the CPU that interconnects the N bit peripheral bus to the first bus lane of the local bus;(b) interface buffer logic coupled to the CPU and to the local bus, including an interface buffer for storing at least a 2N-byte data block in first and second buffer blocks corresponding to the first and second data blocks; and(c) interface control logic external to the CPU, coupled to the byte enable control lines, and coupled to exchange interface protocol signals with the interface buffer logic and the CPU to control the loading and unloading of the interface buffer;(d) the interface protocol signals include byte enable codes and a BE control signal asserted by the interface control logic to cause the CPU to relinquish control of the byte enable control lines, such that the interface control logic is able to drive the BE control lines with byte enable codes;(e) the interface control logic using the interface protocol signals, including the BE control signal and byte enable codes to effect the transfer of data between the CPU and a peripheral device through the bus interface logic;(f) such that transfers of first and second data blocks between the CPU and the peripheral device occur serially over the N-bit first bus lane of the local bus and the N-bit peripheral bus through the bus interface logic circuit.