Patent ID: 7037791
Filing Date: 2006-05-02
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a polysilicon transistor gate in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; forming a gate dielectric layer overlying said semiconductor substrate; depositing a polysilicon layer overlying said gate dielectric layer; etching said polysilicon layer, said gate dielectric layer, and said semiconductor substrate to form trenches for planned shallow trench isolations; depositing a trench oxide layer overlying said polysilicon layer and filling said trenches; polishing down said trench oxide layer to the top surface of said polysilicon layer to complete said shallow trench isolations; depositing a photoresist layer overlying said polysilicon layer; patterning said photoresist layer to form a feature mask for planned polysilicon gates wherein said patterning is by a single exposure through an alternating aperture phase shift mask and wherein unwanted features in said photoresist layer caused by phase conflicts overlie said shallow trench isolations such that a trimming layer at phase transitions is not needed; and etching said polysilicon layer using said feature mask to form said polysilicon gates in the manufacture of the integrated circuit device wherein the presence of said unwanted features overlying said shallow trench isolations eliminates their transfer to said polysilicon layer.