Patent ID: 7901958
Filing Date: 2011-03-08
Classification: G01R,H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) providing a semiconductor wafer which has a plurality of chip regions each having a semiconductor integrated circuit formed thereon and each having a plurality of first electrodes electrically connected to the semiconductor integrated circuit; (b) preparing a first card comprising a wiring substrate having first interconnects formed thereon, a thin film probe sheet having a plurality of contact terminals to be brought into contact with the first electrodes, and a pressing tool arranged over a region of the thin film probe sheet in which the plurality of contact terminals are formed, the thin film probe sheet including a first insulating film, a plurality of second interconnects formed over a upper surface of the first insulating film, and a second insulating film formed over the plurality of second interconnects, a first material formed over the second insulating film and arranged over the region of the thin film probe sheet in which the plurality of contact terminals are formed, the first material having first openings, the plurality of contact terminals being formed at a lower surface of the first insulating film, the plurality of second interconnects being electrically connected to the plurality of contact terminals and to the first interconnects, the pressing tool being arranged over the first material and the elastic materials such that the pressing tool is in contact with the elastic materials, (c) bringing tip portions of the contact terminals into contact with the first electrodes of the semiconductor wafer by pressing the thin film probe sheet with the pressing tool, for performing electrical testing of the semiconductor integrated circuit, wherein each of the tip portions of the contact terminals is disposed over a corresponding one of the first electrodes.