Patent ID: 7467319
Filing Date: 2008-12-16
Classification: H04J,H04L

Abstract:
1. A clock interface for a programmable logic device, comprising: a media access controller having a clock generator and a first clock signal distribution network, the media access controller formed as an application specific integrated circuit within the programmable logic device; the programmable logic device including programmably configurable circuitry, the programmably configurable circuitry having a second clock signal distribution network for incorporation in a user-instantiated design; the clock generator coupled to the second clock signal distribution network to provide an input clock signal thereto; the second clock signal distribution network coupled to the first clock signal distribution network to provide an output clock signal thereto, the output clock signal being a version of the input clock signal having loading responsive to the user-instantiated design; the first clock signal distribution network including at least one delay cell and a clock tree, the clock tree coupled to receive the output clock signal, the at least one delay cell coupled to receive signal input provided from the user-instantiated design and clocked responsive to the output clock signal; and the clock tree configured to provide a clock signal for registering the signal input delayed responsive to the at least one delay cell.