Patent ID: 6295477
Filing Date: 2001-09-25
Classification: G06F

Abstract:
A system for operating a coherence protocol for buffer memories which covers interventions in multiprocessor data processing units, the system comprising:a plurality of processors, each processor having a buffer memory containing a buffer line;at least one local bus connected to the plurality of processors;a system bus;a bus coupler connecting the system bus to the at least one local bus wherein the coherence protocol is mapped from the system bus onto the at least one local bus, the bus coupler including at least one intervention register and at least one write register which are both connected to the at least one local bus for read access, and which are both connected to the system bus for write access, the at least one intervention register further including a device for subblock interchange; andwherein the at least one write register is particularly connected to the at least one local bus such that where an intervention relates to content of the at least one write register, the content can be transferred via the at least one local bus to the at least one intervention register.