Patent ID: 6368958
Filing Date: 2002-04-09
Classification: C23C,C25D,H01L

Abstract:
A method to form damascene interconnects in the manufacture of an integrated circuit device comprising:providing a conductor layer overlying a semiconductor substrate, a passivation layer overlying the conductor layer, and a dielectric layer overlying the passivation layer; patterning said dielectric layer and said passivation layer to form trenches for planned damascene interconnects; depositing a barrier layer overlying said dielectric layer; coating a stabilized simple Cu(I) ion solution overlying said barrier layer wherein said stabilized simple Cu(I) ion solution is stabilized by mixing with a polar organic solvent; adding water to said stabilized simple Cu(I) ion solution to cause disproportionation of said simple Cu(I) ions from said stabilized simple Cu(I) solution; depositing a copper seed layer overlying said barrier layer wherein said copper seed layer comes from said disproportionation of said Cu(I) ions; depositing a thick copper layer overlying said barrier layer and filling said trenches wherein said copper seed layer serves as a catalyst for said depositing; annealing said copper layer; and polishing down said thick copper layer and said barrier layer to complete said damascene interconnects in the manufacture of said integrated circuit device.