Patent ID: 7825698
Filing Date: 2010-11-02
Classification: G11C

Abstract:
1. A differential amplifier comprising: an output transconductance amplifier comprising: a first PMOS transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said first terminal being coupled to a first voltage terminal, said gate being coupled to receive a bias voltage; a second PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal, said gate being coupled to a first input terminal, said first terminal being coupled to the second terminal of the first PMOS transistor, said bulk voltage terminal being coupled to a second voltage terminal to receive a voltage different than the voltage on the first voltage terminal; a first NMOS transistor including first and second terminals spaced apart with a channel therebetween, and including a gate for controlling current in said channel, said second terminal being coupled to a ground terminal, said gate being coupled to said first terminal of the first NMOS transistor and said second terminal of said second PMOS transistor; a third PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal, said second terminal being coupled to a first output terminal, said gate being coupled to a second input terminal, said first terminal being coupled to the second terminal of the first PMOS transistor, said bulk voltage terminal being coupled to the second voltage terminal; a second NMOS transistor including first and second terminals spaced apart with a channel therebetween, and including a gate for controlling current in said channel, said second terminal being coupled to the ground terminal, said gate being coupled to the first terminal of the first NMOS transistor, said first terminal of the second NMOS transistor being coupled to the first output terminal; an output stage coupled to the first output terminal, wherein said output stage comprising: a fourth PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal, said second terminal being coupled to said gate, said first terminal being coupled to the first voltage terminal; a third NMOS transistor including first and second terminals spaced apart with a channel therebetween, and including a gate for controlling current in said channel, said second terminal being coupled to the ground terminal, said gate being coupled to the second terminal of the second PMOS transistor, said first terminal being coupled to the second terminal of the fourth PMOS transistor; a fifth PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal to receive a first adjustable voltage, said second terminal being coupled to a second output terminal, said gate being coupled to the second terminal of the fourth PMOS transistor, said first terminal being coupled to the first voltage terminal; and a fourth NMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal to receive a second adjustable voltage, said second terminal being coupled to the ground terminal, said gate being coupled to the second terminal of the second PMOS transistor, said first terminal being coupled to the second terminal of the fifth PMOS transistor; and a bulk voltage generator coupled to at least one of said PMOS or NMOS transistors to generate a bulk voltage different than a supply voltage of the output transconductance amplifier.