Patent ID: 7468301
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. A method of manufacturing a PMOS transistor, comprising the steps of: providing a semiconductor substrate having an active region, a first mask area, a second mask area and a field region, the field region having a first field area and a second field area; wherein a channel area is formed by the first field area, the second field area, and a predetermined portion of the active region between the first and second field areas, and wherein the first mask area consists of the first field area and a first portion of the active region extending from the first field area, wherein the second mask area consists of the second field area and a second portion of the active region extending from the second field area; forming an isolation layer in the field region of the semiconductor substrate; forming a first hard mask layer on the first mask area only; forming a second hard mask layer on the second mask area only; etching the field region, the active region, and the predetermined portion of the active region between the first and second field areas of the semiconductor substrate to a predetermined depth by using the first and second hard mask layers as an etching barrier, wherein the predetermined depth exists between the surface of the first and second field areas and the rest of the active and field regions of the semiconductor substrate; removing the first and second hard mask layers; forming a gate on the channel area and the first and second field areas after etching the field region, the active region, and the predetermined portion of the active region between the first and second field areas; and forming source and drain regions at both edges of the gate on a surface of the semiconductor substrate.