Patent ID: 6501315
Filing Date: 2002-12-31
Classification: H03K

Abstract:
A flip-flop circuit, comprising:a flip-flop data input terminal; a flip-flop output terminal; a first clock terminal providing a first clock signal; a second clock terminal providing a second clock signal, the second clock signal being an inverse of the first clock signal; first, second, third, and fourth nodes; a first passgate coupled between the data input terminal and the first node, a gate terminal of the first passgate being coupled to the second clock terminal; a first latch comprising a first logic gate having an input terminal coupled to the second node and an output terminal coupled to the first node, and a second logic gate having an input terminal coupled to the first node and an output terminal coupled to the second node; a second passgate coupled between the second node and the third node, a gate terminal of the second passgate being coupled to the first clock terminal; a second latch comprising a third logic gate having an input terminal coupled to the fourth node and an output terminal coupled to the third node, and a fourth logic gate having an input terminal coupled to the third node and an output terminal coupled to the fourth node; a first inverter having an input terminal coupled to the flip-flop data input terminal, and an output terminal; a third passgate coupled between the output terminal of the first inverter and the second node, a gate terminal of the third passgate being coupled to the second clock terminal; a second inverter having an input terminal coupled to the second node, and an output terminal; and a fourth passgate coupled between the output terminal of the second inverter and the fourth node, a gate terminal of the fourth passgate being coupled to the first clock terminal; wherein one of the third and fourth nodes is coupled to the flip-flop output terminal.