Patent ID: 7519746
Filing Date: 2009-04-14
Classification: G06F

Abstract:
1. An elastic buffer for receiving to store data from a first circuit which operates to synchronize a first clock signal, and reading the data out to a second circuit which operates to synchronize a second clock signal whose phase is different from that of the first clock signal, the elastic buffer comprising: a fist storage circuit connected to the first and second circuits; and a detection circuit which receives the first and second clock signals, and detects an overflow state in which unread data has been broken or is going to be broken, and an underflow state in which already-read data or invalid data has been read or is going to be read, wherein the detection circuit has: a first ring counter in which first initial value data composed of a plurality of first bits is set, the first ring counter receiving the first clock signal, and circulating the first initial value data to synchronize the first clock signal; a second ring counter in which second initial value data composed of a plurality of second bits is set, the second ring counter receiving the second clock signal, and circulating the second initial value data to synchronize the second clock signal; a third ring counter in which third initial value data composed of a plurality of third bits is set, the third ring counter receiving the second clock signal, and circulating the third initial value data to synchronize the second clock signal; a second storage circuit which receives an output of the first ring counter and the second clock signal, and fetches and holds the output of the first ring counter to synchronize the second clock signal; a first AND circuit group which has first and second inputs, and comprises a plurality of first AND circuits which receives fourth bits respectively corresponding to an output of the second ring counter and an output of the second storage circuit at the first and second inputs; a second AND circuit group which has third and fourth inputs, and comprises a plurality of second AND circuits which receives fifth bits respectively corresponding to an output of the third ring counter and an output of the second storage circuit at the third and fourth inputs; a first OR circuit which has a plurality of first OR inputs, and receives outputs of the first AND circuit group at said plurality of first OR inputs; a second OR circuit which has a plurality of second OR inputs, and receives outputs of the second AND circuit group at said plurality of second OR inputs; a third storage circuit which receives and stores an output of the first OR circuit; a fourth storage circuit which receives and stores an output of the second OR circuit; and a decode circuit which receives outputs of the first and second OR circuits and outputs of the third and fourth storage circuits, and decodes these outputs to output an overflow signal and an underflow signal.