Patent ID: 8054662
Filing Date: 2011-11-08
Classification: G11C

Abstract:
1. A memory device for storing one or more addresses, the memory device comprising: a match line; a first memory cell, the first memory cell including a first memory element coupled to a second memory element and to the match line, the first memory cell also including a first access device coupled to the first memory element and having a first access line and a second access device coupled to the second memory element and having a second access line, the first memory cell configured to store a first value; and a second memory cell, the second memory cell including a third memory element coupled to a fourth memory element and to the match line, the second memory cell also including a third access device coupled to the third memory element having a third access line and a fourth access device coupled to the fourth memory element and having a fourth access line, the second memory cell configured to store a second value; wherein each of the access lines receives a signal that is a different combination of the first and second values.