Patent ID: 8530287
Filing Date: 2013-09-10
Classification: H01L

Abstract:
1. A method to fabricate a structure, comprising: providing a wafer comprising a semiconductor substrate and a top surface, an insulating layer disposed over the top surface and a semiconductor layer disposed over the insulating layer; implanting through the semiconductor layer and the insulating layer a functional region to be adjacent to the top surface of the substrate, the functional region having a first type of conductivity; implanting through the semiconductor layer and the insulating layer a back gate region to be adjacent to the top surface of the substrate and within the functional region, the back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer at predetermined locations corresponding to locations of subsequently formed first and second transistor devices; forming the first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region, where the implanted back gate region is not connected to an electrical contact so that during operation it is biased by leakage and capacitive coupling to the same potential as a functional region of the substrate in which it is implanted and with which it forms a diode junction; and providing an electrical contact to the functional region for applying a bias voltage.