Patent ID: 7233187
Filing Date: 2007-06-19
Classification: G06F

Abstract:
1. A pulse generator comprising: a clock adapted to generate clock pulses; a phase lock loop (PLL) operably coupled to the clock so that the clock pulses have reduced jitter; a retimer operatively coupled to the clock; first and second delays operatively coupled to an output of the retimer and each having an output; a timing generator operatively coupled to an input of one of the first and second delays; a logic gate coupled to receive the outputs of the first and second delays and adapted to generate an output pulse based on the outputs of the first and second delays; and wherein the timing generator is operatively coupled to the retimer and the retimer retimes clock signals from the timing generator based on the reduced-jitter clock pulses, and wherein the timing generator includes a field-programmable gate array adapted to allow the pulse generator to operate in one of a clock mode and a delay mode.