Patent ID: 6100713
Filing Date: 2000-08-08
Classification: H04L

Abstract:
An active termination circuit for terminating a signal traversing on a transmission line of a memory bus including a plurality of memory devices, the active termination circuit comprising:a bottom clamping transistor having a node coupled to the transmission line, a node coupled to ground, and a gate; anda bottom threshold reference transistor having a first threshold voltage for clamping said signal at about ground, said bottom threshold reference transistor coupled to said gate of said bottom clamping transistor for biasing said gate of said bottom clamping transistor at about said first threshold voltage, said bottom clamping transistor being arranged for clamping said signal at about ground, whereby when the potential difference between the gate and the node coupled to the transmission line exceeds the first threshold voltage, the bottom clamping transistor begins to conduct current, thereby clamping the signal;a top clamping transistor having a node coupled to V.sub.DD, a node couple to the transmission line, and a gate; anda top threshold reference transistor having a second threshold voltage for clamping said signal at about V.sub.DD, said top threshold reference transistor to said gate of said top clamping transistor for biasing said gate of said top clamping transistor at about said second threshold voltage, said top clamping transistor being arranged for clamping said signal at about said V.sub.DD, whereby when the potential difference between the gate and the node coupled to the transmission line exceeds the second threshold voltage, the top clamping transistor begins to conduct current, thereby clamping the signal, whereby the first threshold voltage is different than the second threshold voltage, andwhereby the termination circuit facilitates progression of the signal in a continuous fashion through the plurality of memory devices including in the memory bus.