Patent ID: 6970029
Filing Date: 2005-11-29
Classification: G01R,H03K,H03L

Abstract:
1. A circuit comprising: a delay chain, which is capable of receiving an input signal and producing multiple delayed signals that represent delayed versions of the input signal, wherein the multiple delayed signals are separated by a first phase increment; multiple interpolator blocks, operably coupled to the delay chain, wherein consecutive ones of the multiple interpolator blocks are capable of receiving and interpolating between consecutive ones of the multiple delayed signals to produce an interpolated version of the input signal, wherein the interpolated version is delayed to one of multiple, intermediate delay values that are separated by a second phase increment that is smaller than the first phase increment; and a current source select signal generator circuit, operably coupled to the multiple interpolator blocks, which includes a split current source, and which is capable of providing variable current source select signals to the multiple interpolator blocks to control interpolation between the consecutive ones of the multiple delayed signals; and a differential comparator, operably coupled to the multiple interpolator blocks, which is capable of producing, as an output, the interpolated version of the input signal based on signals received from the multiple interpolator blocks.