Patent ID: 7818488
Filing Date: 2010-10-19
Classification: G11C

Abstract:
1. A memory module comprising: a first pair of registers with each register being disposed on a respective one of front and back surfaces of the memory module with an overlap area between the registers of the first pair; wherein first semiconductor banks are disposed from opposite directions of a first register of said first pair on said front surface of the memory module, and wherein second semiconductor banks are disposed from opposite directions of a second register of said first pair on said back surface of the memory module; and wherein each of said first and second registers receives a respective single signal and transmits respective two signals equivalent to the respective single signal to said first and second semiconductor banks disposed from said opposite directions of said each register on the front or back surfaces of the memory module such that said respective two signals from said each register are transmitted in opposite directions; and a second pair of registers each receiving an input signal transmitted in series through a register of the first pair without a T-shaped divergence of the input signal.