Patent ID: 6550017
Filing Date: 2003-04-15
Classification: G06F

Abstract:
A monitor system for a distributed fault tolerant computer system, the monitor system comprising: a counter mechanism operable to count from a reset value towards a fault value and operable to output a fault signal on reaching said fault value;a counter reset routine implemented in software and operable repeatedly to reset the counter mechanism to its reset value during normal operation of the counter reset routine; a unit connectable to a bus to supply a status signal indicative of the status of the unit, the unit being responsive to a fault signal output from the counter mechanism to provide an OFF status indication to the bus; and a management subsystem, the management subsystem defining a configuration for the distributed fault tolerant computer system, the management subsystem being responsive to status signals on the bus and being operable selectively to redefine the configuration of the distributed fault tolerant system dependent upon the state of the status signals; wherein each unit of respective nodes is connected to a respective channel on the bus and the management subsystem is responsive to respective status signals on respective channels to determine the status of respective nodes.