Patent ID: 6178127
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of data terminals;a plurality of internal data lines provided corresponding to said plurality of data terminals, respectively;a plurality of memory blocks each including memory cells arranged in rows and columns and a redundant cell column for repairing a defective memory cell in at least one column;a plurality of normal column select circuits provided corresponding to said plurality of memory blocks, each normal column select circuit for simultaneously selecting a plurality of memory cells from a corresponding memory block and coupling selected memory cells to said plurality of internal data lines, respectively;a plurality of replacement IO program circuits provided corresponding to said plurality of memory blocks, for storing IO addresses specifying the internal data lines to be connected to the redundant cell columns in corresponding memory blocks;at least one replacement column address program circuit each provided commonly to a predetermined number of memory arrays among said plurality of memory arrays for storing a defective column address indicating a defective memory cell column in said predetermined number of memory blocks; anda plurality of redundant column select circuits provided corresponding to said plurality of memory blocks, each redundant column select circuit coupled to a corresponding replacement IO program circuit and a corresponding replacement column address program circuit for selecting the redundant cell column in a corresponding memory block when an applied address indicates the defective memory cell column in the corresponding memory block.