Patent ID: 6235587
Filing Date: 2001-05-22
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device having a core memory cell region and a peripheral circuitry region, the method comprising the following steps:(a) forming a first gate electrode stack in the memory cell region, the first gate electrode stack comprising, sequentially:a tunnel dielectric layer;a charge storage electrode layer;a dielectric layer;a control gate electrode layer; andan anti-reflective coating (ARC);(b) forming a second gate electrode stack in the peripheral circuitry region, the second gate electrode stack comprising:a dielectric layer;a gate electrode layer; andan ARC;(c) depositing a first layer of photoresist material over the core memory cell and peripheral circuitry regions;(d) forming a first photoresist mask on the first gate electrode stack;(e) etching the first gate electrode stack, while the second gate electrode stack is masked by the first layer of photoresist material, to form at least one stacked gate electrode structure comprising, sequentially:a tunnel dielectric;a charge storage electrode;an intergate dielectric;a control gate electrode; andan ARC;(f) removing the first photoresist mask from the core memory cell region and first layer of photoresist material from the peripheral circuitry region;(g) forming a second layer of photoresist material over the core memory cell and peripheral circuitry regions;(h) forming a second photoresist mask on the second gate electrode stack;(i) etching the second gate electrode stack to form a second gate electrode structure comprising, sequentially:a gate dielectric;a gate electrode; andan ARC.