Patent ID: 9135553
Filing Date: 2015-09-15
Classification: G06F,G06K,G06N,G06T

Abstract:
1. A convolution operation circuit comprising: a plurality of multipliers each of which configured to multiply data received from a first input and a second input of respective multipliers; a first providing unit configured to provide respective data to the first input of the plurality of multipliers; a second providing unit configured to provide common data to the second input of the plurality of multipliers; a plurality of cumulative adders configured to accumulate output from the plurality of multipliers; a memory configured to store data to be provided by the first providing unit and the second providing storage unit and data output from the plurality of cumulative adders; and a control unit configured to control operations of the first providing unit, the second providing unit, the memory, and the plurality of cumulative adders, so that the first providing unit and the second providing unit to provide data to the first input and the second input of each of the multipliers, respectively, in synchronization with operations of the cumulative adders, and the control unit transfers, during multiplications by the multipliers, data stored in the memory to the first providing unit and the second providing unit.