Patent ID: 8518731
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A method for manufacturing a thin film transistor array panel, comprising: depositing a first metal layer on a substrate; depositing a second metal layer on the first metal layer; forming a first photosensitive pattern on the second metal layer; simultaneously etching the first metal layer and the second metal layer with a non-peroxide-based first etchant, using the first photosensitive pattern as a mask; removing a portion of the first photosensitive pattern to form a second photosensitive pattern; and etching the second metal layer with a non-peroxide-based second etchant, using the second photosensitive pattern as a mask, to form a gate conductor and a first electrode on the substrate; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode on the passivation layer.