Patent ID: 6608744
Filing Date: 2003-08-19
Classification: H01L

Abstract:
An input protection circuit in a silicon-on-insulator CMOS integrated circuit in which an input terminal is electrically coupled by an input signal line through a resistive element to gate electrodes of a CMOS inverter, the CMOS inverter also receiving a first power-supply potential from a first internal power-supply line and a second power-supply potential from a second internal power-supply line, comprising:a third internal power-supply line electrically coupled to said first power-supply line; a first protective element coupled between said input signal line and said third internal power-supply line; and a second protective element coupled between said first internal power-supply line and said second internal power-supply line, wherein said CMOS inverter includes a transistor having a source electrode coupled to said second internal power-supply line, and said second protective element is coupled directly to said source electrode.