Patent ID: 8000133
Filing Date: 2011-08-16
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a memory cell storing data with its resistance; a data line electrically connected to said memory cell in a data read operation; and a dummy memory cell producing a read reference voltage for comparison with a voltage on said data line in said data read operation; wherein said memory cell includes a first resistor element having a resistance varied in accordance with the stored data and a select gate for selectively connecting said memory cell to said data line in said data read operation, and said dummy memory cell includes a plurality of second resistor elements each having a resistance characteristic similar to a resistance characteristic of said first resistor element, and a dummy cell select gate having a resistance similar to a resistance of said select gate, and said plurality of second resistor elements are electrically connected with each other so that at least two of said plurality of second resistor elements are connected in series.