Patent ID: 6405354
Filing Date: 2002-06-11
Classification: G06F

Abstract:
A method to optimize power wiring layout in a layout data generating semiconductor integrated circuit comprising modules, each of the modules comprising cells, the method comprising:laying out each of the modules; laying out power supply wirings in each of the modules; acquiring information about a size of each of the cells of each module; temporarily arranging the cells in each module based on the information about the size of each of the cells; laying out power wirings and power supply terminals for each module based on the temporary arrangement of the cells in each module; sampling a power network in a unit of each module based on the cells in the module, the power wirings, and the power supply terminals; analyzing the sampled power network for each module; and determining whether or not each module and the power supply wirings need to be laid out again based on the analysis of the sampled power network.