Patent ID: 7884478
Filing Date: 2011-02-08
Classification: H01L

Abstract:
1. A semiconductor apparatus, comprising: a multilevel wiring structure including an uppermost-level wiring layer, a first lower-level wiring layer that is below and next to the uppermost-level wiring layer, and a first interlayer insulating film intervening between the uppermost-level wiring layer and the first lower-level wiring layer, wherein the uppermost-level wiring layer includes a bonding pad and the first lower-level wiring layer includes a first plug wire; a plurality of first conductive plugs each formed in the first interlayer insulating film to connect the bonding pad to the first plug wire, wherein the first lower-level wiring layer further comprises a plurality of second plug wires, where the first plug wire and the second plug wires are spaced apart from each other, and a plurality of second conductive plugs each formed in the first interlayer insulating film to connect the bonding pad to a corresponding one of the second plug wires; and at least one first pass-through wire formed as the first lower-level wiring layer, the first pass-through wire running between adjacent ones of the first and second plug wires in isolation from each of the first and second plug wires and the bonding pad by the first interlayer insulating film.