Patent ID: 6159815
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A method for the production of a MOS transistor, comprising the steps of:forming a gate dielectric and a gate electrode on a main face of a substrate, said substrate being silicon at least at the main face,depositing a first auxiliary layer with essentially conformal edge coverage,depositing a second auxiliary layer with essentially conformal edge coverage, said second auxiliary layer being of a material which can be etched selectively with respect to the first auxiliary layer,forming spacers at sides of the gate electrode by anisotropically etching back the second auxiliary layer,carrying out implantation to form first subregions for source/drain regions,selectively removing the spacers with respect to the first auxiliary layer,etching a surface of the substrate in the areas where two subregions for the source/drain regions are subsequently formed, andforming second subregions for the source/drain regions by in situ doped selective epitaxy, the second subregions having a lower dopant concentration and a smaller depth than the first subregions.