Patent ID: 8917588
Filing Date: 2014-12-23
Classification: G06F,H04L

Abstract:
1. A fast Fourier transform and inverse fast Fourier transform (FFT/IFFT) operating core, the FFT/IFFT core comprising: a first multiplexer, for multiplexing a first FFT input sequence and a third FFT input sequence; an inputting buffer, for storing and outputting the first FFT input sequence; and an operating module having a zero operating stage, a first operating stage, and a K-th operating stage, wherein the zeroth operating stage, based on a corresponding process indicating signal and a corresponding bypass indicating signal, either for performing one of bypassing an output signal of the first multiplexer and transforming the output signal of the first multiplexer by an FFT operation so as to generate a first output signal wherein the corresponding process indicating signal and the corresponding bypass indicating signal are generated, the corresponding process indicating signal indicates that one of the first FFT input sequence, the second IFFT input sequence, and the third FFT input sequence inputted to the operating module is processed by either a decimation-in-time algorithm or a decimation-in-frequency algorithm, and the corresponding bypass indicating signal indicates whether the one of the first FFT input sequence, the second IFFT input sequence, and the third FFT input sequence inputted to the operating module directly passes the operating module.