Patent ID: 6145032
Filing Date: 2000-11-07
Classification: H04L

Abstract:
In a data processing system, a data recirculation apparatus, comprising:a FIFO output buffer from which data are output onto an interconnect;a plurality of input storage areas from which data are selected for storage within said FIFO output buffer;a multiplexer that selects data from said plurality of input storage areas for storage within said FIFO output buffer in response to a select signal generated by a mux arbitration logic; andbuffer control logic, coupled to said FIFO output buffer, which in response to a determination that a particular datum has stalled in said FIFO output buffer, automatically causes said particular datum to be removed from said FIFO output buffer and stored in one of said plurality of input storage areas, such that a subsequent datum in said FIFO output buffer can be transmitted onto said interconnect.