Patent ID: 8775904
Filing Date: 2014-07-08
Classification: G06F,G11C

Abstract:
1. An apparatus, comprising: a plurality of processor cores; a cache coupled to a first processor core with the plurality of processor cores; and a memory, wherein the cache is configured to receive memory requests from the processor core and store cache lines of data to be accessed by the processor core, wherein the memory stores a cache line in a plurality of data blocks, wherein each data block in the plurality of data blocks has a set of error correction code bits and a single meta-bit, wherein the meta-bits of the plurality of data blocks combine to indicate a local/global state and a special uncorrectable error bit; wherein the cache is configured to issue a request for the cache line locally; wherein the cache is configured to receive a first block of data, of the plurality of blocks of data, in a first cycle; wherein the cache is configured to identify a meta-bit of the first block of data; and wherein the cache is configured to determine a local/global state of the cache line based on the meta-bit of the first block of data.