Patent ID: 6486552
Filing Date: 2002-11-26
Classification: G01R,H05K

Abstract:
A bump substrate for receiving a plurality of contact bumps on a semiconductor die during testing thereof, said bump substrate comprising:a bump substrate having a plurality of contact bump receiving sites formed in said bump substrate corresponding to a pattern of said plurality of contact bumps on said semiconductor die during said testing thereof, at least one of said plurality of contact bump receiving sites having a plurality of side walls and a bottom and having a plurality of conductive traces located on at least portions of said plurality of side walls of said at least one contact bump receiving site for contacting a plurality of conductive traces on said bump substrate and for contacting a corresponding contact bump of said plurality of contact bumps received at said at least one contact bump receiving site, at least one conductive trace of said plurality of conductive traces extending along at least a portion of a side wall of said plurality of side walls of said at least one contact receiving site and at least one other conductive trace of said plurality of conductive traces extending along at least a portion of another side wall of said plurality of side walls and a portion of the bottom of said at least one contact receiving site.