Patent ID: 6251781
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method to form copper interconnects in the fabrication of an integrated circuit device comprising:providing a semiconductor substrate;depositing a dielectric layer overlying said semiconductor substrate;patterning said dielectric layer to form trenches;depositing a barrier layer overlying said dielectric layer and within said trenches;spin-coating a platinum ionic seed solution overlying said barrier layer;depositing a platinum seed layer from said platinum ionic seed solution by exposing said platinum ionic seed solution to light;removing said platinum seed layer except within said trenches;depositing a copper layer overlying said platinum seed layer by electroless plating to thereby form copper interconnects, wherein said copper layer only deposits in said trenches, and wherein said deposition stops before said copper layer fills said trenches;polishing away said barrier layer to the top surface of said dielectric layer so that said barrier layer remains only in said trenches;depositing an encapsulation layer overlying said copper interconnects and said dielectric layer; andcompleting the fabrication of the integrated circuit device.