Patent ID: 7254696
Filing Date: 2007-08-07
Classification: H04L

Abstract:
1. A functional-level instruction-set computing (FLIC) processor comprising: a plurality of processing units for executing functional-level instructions on variable-length operands to produce results that are also variable-length operands; an execution buffer, coupled to the plurality of processing units, for storing the variable-length operands; fixed-length registers that store (1) fixed-length operands, (2) a pointer that indicates a location of a variable-length operand in the execution buffer, and (3) an operand-length that indicates a length of a variable-length operand in the execution buffer; wherein the functional-level instructions identify a fixed-length operand for input to a processing unit in the plurality of processing units by specifying a register number of one of the fixed-length registers that contains the fixed-length operand; wherein the functional-level instructions identify a variable-length operand for input to a processing unit in the plurality of processing units by specifying a register number of one of the fixed-length registers that contains the pointer or the operand-length of the variable-length operand stored in the execution buffer, whereby variable-length operands are stored in the execution buffer and executed by the processing unit when identified by the functional-level instructions; a lookup cache for storing entries that contain variable-length tags; wherein the functional-level instructions include a lookup instruction; a lookup unit in the plurality of processing units that executes the lookup instruction by reading a variable-length operand from the execution buffer and searching for a variable-length tag in the lookup cache that matches the variable-length operand, whereby variable-length operands are matched to variable-length tags by the lookup instruction.