Patent ID: 8181024
Filing Date: 2012-05-15
Classification: G06F,H04L

Abstract:
1. A data processing apparatus configured to perform a predetermined data processing by a hardware processing circuit, the data processing apparatus comprising: an encryption/decryption processing unit configured to perform an encryption and/or decryption type of data processing; a message authentication processing unit configured to perform a message authentication type of data processing; and a checksum processing unit configured to perform a checksum type of data processing; wherein the predetermined data processing includes at least two of the aforementioned types of data processing, executed in parallel and/or sequentially, and subjected to a pipeline processing in multiple divided periods; wherein a plurality of overlapping accesses to a set of data, for use in the predetermined data processing, are consolidated into one access; and wherein a unified data processing unit (M) is determined as a least common multiple of processing capacity, as measured in bytes, of the at least two of the encryption/decryption processing unit, the authentication processing unit, and the checksum processing unit.