Patent ID: 8964497
Filing Date: 2015-02-24
Classification: G11C,H01L

Abstract:
1. A bit line sense amplifier disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block, the bit line sense amplifier comprising: first and third switching elements substantially symmetrically formed in a first direction so that drain terminals of the first and third switching elements face each other; second and fourth switching elements substantially symmetrically formed in the first direction so that drain terminals of the second and fourth switching elements face each other; a first line formed on a first level, configured to electrically couple a gate terminal of the first switching element and the drain terminal of the second switching element; and a second line formed on a second level which is different from a first level, configured to electrically couple a gate terminal of the third switching element and the drain terminal of the fourth switching element, wherein the first and the second switching elements are substantially symmetrically formed in a second direction substantially vertical to the first direction, the third and the fourth switching elements are substantially symmetrically formed in the second direction, and the first line and the second line extend from different memory cell blocks, and the first line and the second line are substantially symmetrically formed.