Patent ID: 8526210
Filing Date: 2013-09-03
Classification: G11C

Abstract:
1. A semiconductor device with a one-time programmable (OTP) memory cell, comprising: a first MOS transistor having a first gate terminal connected to a first line, a first terminal of the first MOS transistor connected to a first node, and a second terminal of the first MOS transistor connected to a bias voltage line; a second MOS transistor having a second gate terminal connected to a second line, a first terminal of the second MOS transistor connected to the first node, and a second terminal of the second MOS transistor connected to a bias voltage line; and a third MOS transistor having a third gate terminal connected to a third line, a first terminal of the third MOS transistor connected to the first node, and a second terminal of the third MOS transistor connected to a ground terminal, wherein a current path is formed in a programming mode by breaking down an insulation film of one of the first gate terminal and the second gate terminal so that a current flows through one of the first gate terminal and the second gate terminal to the first node.