Patent ID: 7781288
Filing Date: 2010-08-24
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor structure comprising: providing a semiconductor substrate including a dummy gate electrode formed within a dielectric layer over a gate dielectric that is present on an upper surface of the semiconductor substrate; removing the dummy gate electrode to form an aperture exposing the gate dielectric; and forming a metal liner of a first work function metal on each sidewall of the aperture, in which the metal liner is in direct contact with first portions of the gate dielectric, and a second portion of the gate dielectric is exposed, wherein the second portion of the gate dielectric is between the first portions of the gate dielectric that the metal liner is in contact with; and forming a second work function metal filling at least a portion of the aperture and in direct contact with the second portion of the gate dielectric, in which the second work function metal has a higher or lower work function than the first work function metal.