Patent ID: 9054793
Filing Date: 2015-06-09
Classification: G01R,G06K,H01L,H04B

Abstract:
1. A test structure comprising: an integrated circuit device comprising multiple terminals comprising at least a first terminal and a second terminal opposite said first terminal; a first ground-signal-ground (GSG) pad set comprising a first signal pad between two first ground pads, said first signal pad being electrically connected to said first terminal; a second ground-signal-ground (GSG) pad set comprising a second signal pad between two second ground pads, said second signal pad being electrically connected to one of said first terminal and said second terminal; multiple direct current (DC) bias pads; and, multiple serial resistors, each serial resistor being electrically connected in series between one of said multiple direct current (DC) bias pads and one of said multiple terminals, said test structure being selectively operable in any one of a stress mode and an analysis mode, wherein, during said stress mode, said first signal pad receives an input radio frequency power signal and said second signal pad outputs an output radio frequency power signal.