Patent ID: 6498084
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A method of forming a memory cell, comprising:providing a substrate having a well; forming a first dielectric layer over said substrate; forming a doped polysilicon layer over said first dielectric layer; forming a second dielectric layer over said doped polysilicon layer; forming a mask layer over said second dielectric layer, wherein a first portion of said mask layer overlies a first region of said well and a second portion of said mask layer overlies a second region of said well, wherein a third region of said well lies between said first and second regions of said well; removing said first dielectric layer and said doped polysilicon layer except under said first and second portions of said mask layer, wherein the remaining polysilicon layer define first and second control gate portions respectively overlying said first and second regions of said well, and wherein the remaining second dielectric layer define first and second dielectrics respectively overlying said first and second control gate portions; removing said mask layer; forming first and second dielectric spacers on respective tunnel sides of said first and second control gate; removing at least a portion of said first dielectric layer overlying said third region of said well; forming a third dielectric over said substrate above said third region of said well; and forming a floating gate having a first portion over said first dielectric, a second portion over said third dielectric, a third portion over said second dielectric, a fourth portion extending generally vertical from said first portion to said second portion of said floating gate, and a fifth portion extending generally vertical from said second portion to said third portion of said floating gate.