Patent ID: 8103464
Filing Date: 2012-01-24
Classification: G01R

Abstract:
1. A test circuit connected between a test target circuit and a plurality of external terminals, and being a drive test circuit for inputting an internal signal pattern into the test target circuit, comprising: N first holding circuits to hold respectively N unit patterns produced by dividing the internal signal pattern to be input to or output from the test target circuit by N, where N is a natural number of two or greater; a control circuit to make the internal signal pattern held in the N first holding circuits be changed selectively on a unit pattern basis based on a value of an identification signal assigned to each of the unit patterns beforehand, or to make the internal signal pattern held in the N first holding circuits be output selectively on a unit pattern basis based on the values of the identification signal; and a second holding circuit connected between the N first holding circuits and the test target circuit to hold the internal signal pattern transferred from the N first holding circuits.