Patent ID: 9117397
Filing Date: 2015-08-25
Classification: G09G,H04N

Abstract:
1. A timing controller for use in a display device including an external memory, the timing controller comprising: a reception unit configured to receive input RGB data from an external device; a converter configured to convert the input RGB data into input WRGB data composed of W, R, G and B data; an aligner configured to convert one of the W, R, G, and B data of the input WRGB data into 0 to generate conversion WRGB data, the conversion WRGB data having bits less than the total number of bits composing the W, R, G, and B data; a controller configured to transfer the conversion WRGB data to the external memory; and a re-aligner configured to receive the conversion WRGB data from the external memory, convert the received conversion WRGB data into digital WRGB data corresponding to the input WRGB data, and to output the digital WRGB data, wherein when each of the W, R, G and B data of the input WRGB data has N bits where N equals a positive integer, the aligner converts the one of the W, R, G, and B data into 0, converts the other remaining data of the W, R, G and B data into new values according to this conversion result, and generates 2-bit location information indicating the one data converted into 0, thereby generating the conversion WRGB data of ((N×3)+2) bits.