Patent ID: 6870411
Filing Date: 2005-03-22
Classification: H03L

Abstract:
1. A phase synchronizing circuit comprising a phase comparator, a charge pump, a loop filter, a variable frequency oscillation circuit, adjust means, and a divider for dividing an output of divides the variable frequency oscillation circuit, wherein the variable frequency oscillation circuit is connected with the loop filter and the divider such that an oscillation frequency and a phase of an output signal from the variable frequency oscillation circuit to the divider synchronized to be predetermined values by inputting a phase difference signal between a reference signal and a feedback signal which is detected by the phase comparator into the variable frequency oscillation circuit through the charge pump and the loop filter, the adjusting means for automatically adjusting the variable frequency oscillation circuit is connected with the variable frequency oscillation circuit to automatically adjust a frequency tuning range of the variable frequency oscillation circuit to a predetermined frequency range before synchronizing the oscillation frequency and the phase of the output signal from the frequency oscillation circuit starts, and the adjusting means includes: an upper limit decision circuit that determines an upper limit of the oscillation frequency of the variable frequency oscillation circuit and outputs an upper limit adjustment signal used for setting the upper limit of the oscillation frequency of the variable frequency oscillation circuit by using the reference frequency and the output signal of the variable frequency oscillation circuit as inputs therein; a lower limit decision circuit that determines a lower limit of the oscillation frequency of the variable frequency oscillation circuit and outputs a lower limit adjustment signal for setting the lower limit of the oscillation frequency by using the reference frequency and the output signal of the variable frequency oscillation circuit as inputs therein; and a control circuit for controlling change-over between the upper limit decision circuit and the lower limit decision circuit.