Patent ID: 7629651
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; an insulation layer provided on the semiconductor substrate; a plurality of Fin-type semiconductor layers provided on the insulation layer, the Fin-type semiconductor layers including source regions, drain regions, and floating body regions in an electrically floating state provided between the source regions and the drain regions; first gate insulation films provided on first side surfaces of the Fin-type semiconductor layers; second gate insulation films provided on second side surfaces of the Fin-type semiconductor layers, the second side surfaces being opposite sides of the first side surfaces of the Fin-type semiconductor layers; front gate electrodes provided on the first side surfaces via the first gate insulation films; and back gate electrodes provided between a second side surface of one of the Fin-type semiconductor layers and a second side surface of the other Fin-type semiconductor layer which is adjacent to the one of the Fin-type semiconductor layers, the second side surface of the one of the Fin-type semiconductor layers and the second side surface of the other Fin-type semiconductor layer are opposed to each other, wherein when a smallest line width which can be formed by lithography is F, widths of the front gate electrodes or widths of the back gate electrodes are smaller than the F in a cross section perpendicular to an extension direction of the Fin-type semiconductor layers.