Patent ID: 8959392
Filing Date: 2015-02-17
Classification: G06F

Abstract:
1. A redundant two-processor controller, comprising: a first processor and a second processor for the synchronous execution of a control program; at least a first multiplexer for optionally connecting at least a first peripheral unit to be actuated to one of the first and second processors, wherein the first processor is a primary processor for the first peripheral unit and the second processor is a secondary processor for the first peripheral unit; at least a second multiplexer for optionally connecting at least one second peripheral unit to be actuated to one of the first and second processors, wherein the second processor is the primary processor for the second peripheral unit and the first processor is the secondary processor for the second peripheral unit; at least a first comparison unit for monitoring the synchronization state of the first and second processors and for detecting a synchronization error; and a restoration control unit which is designed to monitor the execution of at least one test program by the first and second processors after the occurrence of a synchronization error and to evaluate the test results, and which is designed to configure at least the first multiplexer and the second multiplexer.