Patent ID: 6031281
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A semiconductor integrated circuit (IC) device comprising:a quadrilateral semiconductor IC chip having an active surface and a plurality of bonding pads arranged along each of edge portions of the active surface;a substrate having a plurality of leads spaced apart from the chip and extending toward the edge portions of the ship;a plurality of bonding wires for electrically connecting the leads to respective ones of the corresponding bonding pads, the plurality of bonding wires including adjacently-spaced first bonding wires and second bonding wires, the first bonding wires having a greater height than the height of the second bonding wires;a package body for encapsulating the chip, the substrate, and the bonding wires, the package body comprising a fluid molding resin formed in a mold cavity,wherein the first bonding wire is an exposed wire that is directly exposed to a flow front flowing in a direction of the fluid molding resin entering into the mold cavity, whereby the exposed wire undergoes a greater wire sweep than a wire sweep of other bonding wires; anda dummy wire disposed upstream, with reference to the flow front direction of the fluid molding resin, of the exposed wire,wherein the dummy wire is connected at a first end to a selected one of the lead, the selected lead also being connected to the exposed wirewherein the dummy wire has a height that is equal to a height of the exposed wire, andwherein the substrate further comprises a die pad to which the chip is attached and an insulating pad provided on one surface of the die pad, wherein the dummy wire is connected at a second end to the insulating pad.