Patent ID: 8793300
Filing Date: 2014-07-29
Classification: G06F

Abstract:
1. A circuit for calculating a sum of two products, each product having a q-bit binary operand and a k-bit binary operand, where k is a multiple of q, the circuit comprising: a q-input Carry-Save Adder; a multiplexer for each input of the adder, having four k-bit channels respectively receiving the value 0, a first of the k-bit operands, the second k-bit operand, and the sum of the two k-bit operands, wherein the output of a multiplexer of rank t (where t is between 0 and q−1) is taken into account by the adder with a t-bit left shift, and each multiplexer having first and second channel selection inputs, the bits of a first of the q-bit operands being respectively supplied to the first selection inputs, and the bits of the second q-bit operand being respectively supplied to the second selection inputs.