Patent ID: 6025747
Filing Date: 2000-02-15
Classification: H03K

Abstract:
A logic signal selection circuit comprising:a first current input type sense amplifier (320) which is provided with a first threshold value which is an output of a first equivalent center current generator (310) and positive logic input signals through transfer gates;a second current input type sense amplifier (321) which is provided with a second threshold value which is an output of a second equivalent center current generator (311) and negative logic input signals through transfer gates;a first differential amplifier (340) which receives and amplifies an output of the first current input type sense amplifier (320) whose delay times are fine adjusted by a first delay time adjuster (330);a second differential amplifier (341) which receives and amplifies an output of the second current input type sense amplifier (321) whose delay times are fine adjusted by a second delay time adjuster (331); anda logic circuit (350) which receives both outputs of the first and second differential amplifiers (340, 341), and generates an output signal which is a logical sum of the both outputs.