Patent ID: 6190979
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method for selectively counter-doping gate stack conductors on a semiconductor substrate, said method comprising the steps of:providing a substrate comprising narrow space array regions and wide space array regions, said wide and narrow space array regions comprising a plurality of gate stack conductors, and wherein said gate stack conductors in said narrow space array regions are more densely packed than in said wide space array regions;depositing a conformal dopant source on the gate stack conductors so as to provide gap fill between gate stack conductors in the narrow space array regions and under fill between gate stack conductors in the wide space array regions;etching so that the conformal dopant source is removed from the wide space array regions and so that at least a portion of conformal dopant source remains between gate stack conductors in the narrow space array regions;counter-doping gate stack conductors in the narrow space array regions by lateral diffusion of dopant from the conformal dopant source through narrow space array gate stack conductor sidewalls.