Patent ID: 6262376
Filing Date: 2001-07-17
Classification: H01L,H05K

Abstract:
A chip carrier substrate comprising:a lower conductor layer comprising a copper layer having an upper surface and a lower surface and at least one upper conductor layer comprising a copper layer having an upper surface and a lower surface, formed above a base;a plurality of aluminum studs, formed by anodization to be of substantially identical height, interconnecting adjacent conductor layers;a layer of barrier metal beneath each of said aluminum studs, electrically connecting each of said aluminum studs with a copper layer therebelow to prevent direct contact therebetween;said aluminum studs and at least one said conductor layer being embedded in a polymeric dielectric material disposed on said base; anda layer of adhesion/barrier metal covering the lower surface of the copper layer of each said upper conductor layer, thereby being disposed between at least one said upper conductor layer and said dielectric material and thereby connecting each of said aluminum studs with a copper layer thereabove.