Patent ID: 6913977
Filing Date: 2005-07-05
Classification: H01L

Abstract:
1. A method of fabricating a MOSFET comprising: providing a semiconductor chip doped with impurity of a first conductivity type; forming a first mask over the chip, the mask having openings which define the locations of first, second and third trenches, respectively; etching the chip through the openings in the first mask to form the first, second and third trenches, thereby forming a first mesa between the first and second trenches and a second mesa between the second and third trenches; forming an insulating layer on the walls of the trenches; introducing a conductive gate material into the trenches; forming a second mask covering the first mesa but having an opening over the second mesa; introducing a first dopant of the first conductivity type through the opening in the second mask into the second mesa; introducing a second dopant through the opening in the second mask into the second mesa, the second dopant being of a second conductivity type opposite to the first conductivity type and being introduced at a first energy level; removing the second mask; forming a third mask covering the second mesa but having an opening over the first mesa; introducing a third dopant through the opening in the third mask into the first mesa, the third dopant being of the second conductivity type and being introduced with at a second energy level, the second energy level being greater than the first energy level; and subjecting the chip to heat such that and the first, second and third dopants diffuse, the third dopant diffusing under the second trench, a junction between the first and second dopants forming a body-drain junction of the MOSFET.