Patent ID: 7173462
Filing Date: 2007-02-06
Classification: H03L

Abstract:
1. A DLL system for generating a recovered clock CLK based on an input signal and a reference clock CLK ref , the DLL system comprising: a phase detector for receiving the input signal and the recovered clock and generating a phase error signal indicating a phase difference between the input signal and the recovered clock CLK; a first correcting signal generator comprising a sigma-delta modulator, coupled to the phase detector, for generating a first correcting signal based on the phase error signal; a clock index generator, coupled to the first correcting signal generator, for generating a clock index by updating the clock index based on the first correcting signal; a multiphase clock generator, coupled to the reference clock, for delaying the reference clock to generate a plurality of delayed versions of the reference clock as a plurality of candidate clocks; and a multiplexer, coupled to the multiphase clock generator and the clock index generator, for selecting one of the plurality of candidate clocks according to the clock index to form the recovered clock.