Patent ID: 8937351
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A power metal-oxide-semiconductor field effect transistor (MOSFET) comprising: a plurality of transistor cells, each cell comprising a source region and a drain region, the source region and the drain region of each cell disposed to be contacted through a surface of a silicon wafer die; a first dielectric layer disposed on the surface of the silicon wafer die; a plurality of grooves in said first dielectric layer, each groove formed above the source region or the drain region of a respective cell and filled with a conductive material; a second dielectric layer disposed on a surface of the first dielectric layer and comprising openings, wherein each of at least one of the openings exposes a contact area to a respective one of said grooves; a metal layer disposed on a surface of said second dielectric layer and filling said openings, wherein the metal layer is patterned and etched to form at least one drain metal wire and at least one source metal wire, wherein the at least one drain metal wire interconnects at least two drain regions of the plurality of transistor cells through respective grooves formed above the at least two drain regions, and the at least one source metal wire interconnects at least two source regions of the plurality of transistor cells through respective grooves formed above the at least two source regions, and wherein each groove has a length extending substantially under an adjacent pair of the at least one drain metal wire and the at least one source metal wire.