Patent ID: 8134137
Filing Date: 2012-03-13
Classification: G11C,H01L

Abstract:
1. A memory device construction comprising: a first horizontally extending conductive line; a second conductive line extending perpendicular to the first conductive line; a diode; a first vertically extending deposit of memory material laterally adjacent to a first sidewall of the second conductive line, the memory material being disposed to be selectively and reversibly configured in one of two or more different resistive states; a second vertically extending deposit of the memory material laterally adjacent to a second sidewall of the second conductive line, the second sidewall opposing the first sidewall; and wherein when the memory device is configured to simultaneously conduct a first current between the second conductive line and the first conductive line via the diode and the first deposit and to conduct a second current between the second conductive line and the first conductive line via the diode and the second deposit.