Patent ID: 6295316
Filing Date: 2001-09-25
Classification: G11B,H03L,H03M,H04B,H04J,H04L,H04N,H04W,Y10S

Abstract:
An automatic equalization system comprising:an analog-to-digital converter for periodically sampling an analog signal representative of digital information in response to a sampling clock signal, and for converting every sample of the analog signal into a corresponding digital sample to convert the analog signal into a corresponding digital signal;first means for detecting a phase error of the sampling clock signal in response to a correlation between samples of the digital signal generated by the analog-to-digital converter;second means for controlling a frequency of the sampling clock signal in response to the phase error detected by the first means;a variable filter for subjecting the digital signal generated by the analog-to-digital converter to a variable filtering process to convert the digital signal generated by the analog-to-digital converter into a filtering-resultant signal, the filtering process corresponding to a waveform equalization process;third means for detecting an amplitude error of the digital signal generated by the analog-to-digital converter in response to a correlation between samples of the filtering-resultant signal generated by the variable filter; andfourth means for controlling the filtering process implemented by the variable filter in response to the amplitude error detected by the third means;wherein the analog-to-digital converter, the first means, and the second means compose a phase locked loop while the variable filter, the third means, and the fourth means compose an amplitude error correcting loop separate from the phase locked loop.