Patent ID: 7134047
Filing Date: 2006-11-07
Classification: G06F

Abstract:
1. A computer system comprising: a processor having first and second execution cores and a check unit, the first and second execution cores to process instructions independently when the processor is in a split mode and to process identical instructions in lock step when the processor is in a redundant mode, and the check unit to compare results from the first and second execution cores when the processor is in redundant mode, the first execution core comprising a first instruction cache and the second execution core comprising a second instruction cache and a selector to select instructions from the first instruction cache in the redundant mode and to select instructions from the second instruction cache in the split mode; and a non-volatile memory in which is stored a recovery routine that switches the processor to split mode when the check unit detects an error, identifies uncorrupted processor state data from at least one of the execution cores, and initializes the first and second execution cores with the identified processor state data.