Patent ID: 8987869
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a first semiconductor chip comprising a first substrate, a conductive bump and a wiring pattern on the first substrate, and a conductive via structure extending through the first substrate, wherein the wiring pattern on the first substrate electrically connects the conductive bump to the conductive via structure; and a second semiconductor chip comprising a second substrate, an interlayer insulating layer on the second substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end adjacent the interlayer insulating layer and contacting the wire layer, the TSV contact pattern integrally extending from inside of a via hole that penetrates through the interlayer insulating layer and through the second substrate to outside of the via hole, and being electrically connected to the conductive bump of the first semiconductor chip, wherein the TSV contact pattern comprises a unitary member including an internal plug part filling at least a portion of a space within the via hole and an external pad part being integrally connected to the internal plug part, the external pad part extending onto a backside of the second substrate opposite the interlayer insulating layer and having a width that tapers in a direction away from the backside of the second substrate, and wherein at least a portion of the external pad part extends into the conductive bump of the first semiconductor chip and mechanically bonds the second semiconductor chip thereto.