Patent ID: 6812580
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A semiconductor package comprising:a first device having a surface and a plurality of peripheral edges, the device having a plurality of connection pads positioned on the surface and along an axis that is substantially orthogonal to a predetermined one of the plurality of peripheral edges; a plurality of wires, each of the plurality of wires having a first end electrically connected to a predetermined one of the plurality of connection pads, each of the plurality of wires having a diameter; and a second device having a surface with a plurality of connection pads, each of which is connected to a second end of a predetermined one of the plurality of wires and substantially along the axis by maintaining a separation distance from an adjacent one of the plurality of wires of no greater than twice a largest diameter of the plurality of wires along at least fifty percent of a length of a shortest wire of the plurality of wires.