Patent ID: 6141266
Filing Date: 2000-10-31
Classification: G11C,H03K

Abstract:
A dynamic random access memory having an address bus and at least one data bit line, comprising:an array of memory cells having a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digit for each column of memory cells;an addressing circuit coupled to the address bus, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array;a data path buffer circuit coupled between the array and the data bit line; anda delay circuit, comprising:a timer circuit having an input terminal adapted to receive a delay circuit input signal, a control terminal adapted to receive a control voltage, and an output terminal, the timer circuit comprising:a capacitor having a first terminal coupled to the output terminal of the timer circuit;a first switch coupled between the first terminal of the capacitor and the control terminal of the timer circuit, the first switch having a control input that is coupled to the input terminal of the timer circuit, the first switch being constructed to be conductive responsive to the delay circuit input signal having a first logic level and to be non-conductive responsive to the delay circuit input signal having a second logic level;a second switch coupled between a first terminal of the capacitor and a bias voltage, the second switch having a control input that is coupled to the input terminal of the timer circuit, the second switch being constructed to be conductive responsive to the delay circuit input signal having the second logic level and to be non-conductive responsive to the delay circuit input signal having the first logic level; anda level translation circuit having a first input terminal coupled to the output terminal of the timer circuit, an output terminal, and first and second supply terminals adapted to receive first and second supply voltages, respectively, the level translation circuit comprising:a bias circuit coupled to the first supply terminal and the output terminal of the level translation circuit, the bias circuit being constructed to bias the output terminal of the level translation circuit to at least one of the first supply voltage and the second supply voltage;a third switch coupled between the second supply terminal and the bias circuit, the third switch having a control input that is coupled to the output terminal of the timer circuit, the third switch being constructed to be conductive responsive to the timer circuit output signal having a first logic level and to be non-conductive responsive to the timer circuit output signal having a second logic level; andthe output node coupled to the output terminal of the level translation circuit and at least one of the third switch and the bias circuit.