Patent ID: 8843867
Filing Date: 2014-09-23
Classification: G06F

Abstract:
1. A system for checking a set of multi-patterning layout design rules on a region of an integrated circuit layout, the layout including a plurality of islands, comprising: a computer system having access to a design rule data set comprising values for multi- patterning spacing constraints among islands in a particular layer, the computer system further having access to a computer readable storage medium storing computer instructions and data which, when executed by the computer system, perform the steps of: iteratively building one or more graphs, each graph comprising one or more nodes and one or more arcs between nodes, each node representing a different island of the plurality of islands, each arc indicating at least one violation of the multi-patterning spacing constraints between a pair of different islands, the iteratively building one or more graphs comprising, for each graph being built: and reporting to a user one or more of the multi-patterning coloring violations indicated by the graphs.