Patent ID: 9207916
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. A simulation apparatus that executes a simulation of instruction execution of a program for a target processor that controls a pipeline process, the simulation apparatus comprising: a processor configured to: perform a process to divide a code of the program into prescribed blocks, and to set an execution result of an externally dependent instruction that is an instruction among instructions included in the blocks whose execution process depends on an external environment as a prediction result; perform a process to perform a function simulation of the instruction execution of the program assuming the prediction result, to obtain timing information representing an execution timing of each instruction included in the blocks, and to calculate an execution time of the externally dependent instruction in the prediction result, based on a result of the function simulation and the timing information; perform a process to generate, based on the result of the function simulation, a host code to make a host processor that makes the target processor control the pipeline process, and perform a performance simulation of the instruction execution of the program assuming the prediction result; and when, in an execution result of execution of the generated host code by the host processor, an execution result of the externally dependent instruction included in the host code is different from the prediction result, correct the execution time of the externally dependent instruction in the prediction result by a correction value obtained using a prescribed delay time of the externally dependent instruction and an execution time of instructions executed before and after the externally dependent instruction, and set the corrected execution time of the externally dependent instruction as the execution time of the externally dependent instruction in the function simulation.