Patent ID: 6366942
Filing Date: 2002-04-02
Classification: G06F

Abstract:
An apparatus for performing rounded floating point mathematical operations on first and second operands, the apparatus comprising:a low increment adder circuit accepting as input the first and second operands and a low increment bit injected into a first pre-selected low order bit position, the low increment adder circuit adding the first and second operands and the low increment bit, and accounting for any carry bits generated and producing a low increment result; a low increment sum logic circuit performing sum logic functions on the low increment result to produce a final low increment result; a high increment adder circuit accepting as input the first and second operands and a high increment bit injected into a second pre-selected low order bit position, the high increment adder circuit adding the first and second operands and the high increment bit, and accounting for any carry bits generated and producing a high increment result; a high increment sum logic circuit performing sum logic functions on the high increment result to produce a final high increment result; an output selection circuit selecting one of the final low increment result and the final high increment result depending upon a most significant bit of the final low increment result; wherein the first and second pre-selected low order bit positions are selected based upon a function of a rounding mode in effect and upon the desired mathematical operation.