Patent ID: 6713884
Filing Date: 2004-03-30
Classification: H01L

Abstract:
An alignment mark structure for aligning a mask with prior formed features of in a circuit region when an opaque material layer covers the alignment mark structure, comprising:an alignment mark region stud extending from a deep trench filled with gate electrode material located in an alignment mark region, the deep trench being formed in a semiconductor substrate, wherein the alignment mark region stud is formed concurrently with a formation of a circuit region stud for a vertical gate transistor in a circuit region and without requiring additional processing steps solely for the formation of the alignment mark region stud, and wherein the alignment mark region stud has a top area defined by an active area mask; an isolation trench formed adjacent to the deep trench filled with gate electrode material in the alignment mark region, the alignment mark region isolation trench being filled with insulating material, wherein the alignment mark region isolation trench filled with the insulating material is formed concurrently with a formation of an isolation wench filled with the insulating material that is located adjacent to the vertical gate transistor in the circuit region, and without requiring additional processing steps solely for the formation of the alignment mark region isolation trench filled with the insulating material; and a step feature formed between the top of the insulating material in the alignment mark region isolation trench and the top of the alignment mark region stud, wherein the height of the step feature is large enough that the step feature remains visible after the opaque material layer covers the alignment mark structure.