Patent ID: 8599633
Filing Date: 2013-12-03
Classification: G11C

Abstract:
1. A method for reducing a standby current of a semiconductor memory device, wherein the semiconductor memory device has a precharge circuit comprising a NMOS transistor and two PMOS transistors, the NMOS transistor is controlled by a second control signal, the two PMOS transistors are controlled by a first control signal, the first control signal and the second control signal are respectively a logic low level and a second logic low level in a standby mode before the semiconductor memory device enters an active mode, and the method comprising: after the semiconductor memory device enters an active mode from the standby mode, changing the first control signal from the logic low level to a logic high level in the active mode, and changing the second control signal from the second logic low level to a first logic low level in the active mode, wherein the first logic low level is lower than the second logic low level; and before a word line signal changes from the logic low level to the logic high level in the active mode, changing the first control signal from the logic high level to the logic low level in the active mode, and changing the second control signal from the first logic low level to a first logic high level in the active mode.