Patent ID: 8786093
Filing Date: 2014-07-22
Classification: H01L

Abstract:
1. A chip package, comprising: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers entire side edges of the signal conducting layer and partially covers the ground conducting layer such that a side edge of the ground conducting layer is exposed at a side of the substrate; a dummy electrical connection structure disposed on the surface of the substrate; and a conducting layer electrically connected to the dummy electrical connection structure, wherein the protection layer partially covers the conducting layer such that a side edge of the conducting layer is exposed.