Patent ID: 7936183
Filing Date: 2011-05-03
Classification: G01R,H03K

Abstract:
1. An integrated circuit comprising: A. a semiconductor substrate; B. functional circuitry formed on the substrate for performing normal operating functions of the integrated circuit and having an input; C. an input terminal formed on the substrate; D. a test data path formed on the substrate; E. memory circuitry formed on the substrate and having an input and an output; F. test control circuitry formed on the substrate and having a first input coupled with the input terminal, a second input coupled with the test data path, and an output connected with the memory circuitry input; G. an input buffer formed on the substrate having an output connected to the functional circuitry input and an input coupled to the output of the memory circuitry; H. an output buffer formed on the substrate that is connected in parallel with the input buffer, the output buffer being electrically weaker than the input buffer, the input buffer and output buffer forming a latch circuit; and I. a switch having an input connected to the input terminal and an output connected to the input of the input buffer.