Patent ID: 8129791
Filing Date: 2012-03-06
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first gate electrode extending in a first direction; first and second diffusion regions formed in a semiconductor substrate on opposite sides of the first gate electrode, the first gate electrode and the first and second diffusion regions constituting a first transistor; third and fourth diffusion regions formed in the semiconductor substrate on opposite sides of the first gate electrode, the first gate electrode and the third and fourth diffusion regions constituting a second transistor, the first and third diffusion regions being located along the first direction, and the second and fourth diffusion regions being located along the first direction; a first inter-layer insulation film covering the first and second transistors; first and second contact plugs formed penetrating through the first inter-layer insulation film and connected to the first and third diffusion regions, respectively; a second inter-layer insulation film covering the first and second contact plugs and the first inter-layer insulation film, the second inter-layer insulation film having a groove extending in the first direction so as to expose top surfaces of the first and second contact plugs; a first wiring pattern extending in a second direction crossing the first direction formed on the second inter-layer insulation film, the first wiring pattern being electrically connected to the first contact plug via a third contact plug formed in the groove; and a second wiring pattern extending in the second direction formed on the second inter-layer insulation film, the second wiring pattern being electrically connected to the second contact plug via a fourth contact plug formed in the groove, wherein the third contact plug has a side surface that is coplanar with a side surface of the first wiring pattern, and the fourth contact plug has a side surface that is coplanar with a side surface of the second wiring pattern.