Patent ID: 6428641
Filing Date: 2002-08-06
Classification: H01L,Y10T

Abstract:
A method for laminating a circuit pattern tape over a wafer, comprising the steps of:preparing a circuit pattern tape with an adhesive layer thereon, the circuit pattern tape comprising a square or rectangular structure having: a central circular portion having the same size and shape as the wafer over which the circuit pattern tape is to be laminated and a plurality of circuit pattern units therein, a frame portion arranged around the circular portion and formed with a planar metal thin layer, a peripheral portion interposed between the circular portion and the frame portion and formed with a planar metal thin layer, the peripheral portion having no circuit pattern units therein, and at least one bowing prevention portion provided at the peripheral portion between the circular portion and the frame portion in such a fashion that the planar metal thin layer formed at the peripheral portion does not exist therein, and wherein the planar metal thin layer formed at the peripheral portion is electrically connected to the planar metal thin layer formed at the frame portion by bus bars; detecting at least one reference position of the prepared circuit pattern tape and at least one reference position of the wafer using visual detecting means; outputting results obtained at the detecting step in the form of visual images capable of allowing a comparison of the detection results; carrying out a reference position correction involving movements of the wafer in an X-axis and/or a Y-axis direction and/or by a desired angular rotation in an XY plane, thereby allowing the reference position of the circuit pattern tape and the reference position of the wafer to correspond to each other; and laminating the circuit pattern tape over the wafer when the reference positions correspond to each other.