Patent ID: 7145255
Filing Date: 2006-12-05
Classification: G11C,H01L,Y10S

Abstract:
1. A programmable element comprising: a first p-n junction formed in a first portion of a polysilicon layer, the polysilicon layer being formed on the top surface of a dielectric layer, the dielectric layer being formed on the top surface of a semiconductor substrate and electrically isolating the polysilicon layer from the underlying semiconductor substrate, the first p-n junction including a first region of a first conductivity type and a second region of a second conductivity type; a second p-n junction formed in a second portion of the polysilicon layer, the second p-n junction including a third region of the first conductivity type and a fourth region of the second conductivity type, the first region of the first p-n junction and the third region of the second p-n junction being electrically connected, the breakdown voltage of the first p-n junction being about the same as the breakdown voltage of the second p-n junction; and a transistor having a control terminal coupled to receive a programming voltage exceeding the breakdown voltage of the first or second p-n junction, a first current handling terminal coupled to the second region, and a second current handling terminal coupled to a first voltage source, wherein one of the first and second p-n junctions is programmed to a low impedance state when a programming voltage exceeding the breakdown voltage of the first or second p-n junction is applied to the control terminal of the transistor.