Patent ID: 6025248
Filing Date: 2000-02-15
Classification: H01L,Y10S

Abstract:
A method of forming a capacitor for an integrated circuit device, said method comprising, the steps of:forming an electrode on an integrated circuit substrate;forming an etch masking pattern comprising a plurality of islands on a surface of said electrode wherein said etch masking pattern exposes portions of said surface of said electrode wherein said step of forming said etch masking pattern comprises the steps of,forming a masking layer on said surface of said electrode,forming a silicon layer on said masking layer opposite said electrode,forming a plurality of oxide runners along grain boundaries of said silicon layer,selectively removing said oxide runners thereby exposing portions of said masking layer along said grain boundaries, andetching said exposed portions of said masking layer thereby exposing said portions of said surface of said electrode;etching said exposed portions of said surface of said electrode using said etch masking pattern as an etching mask so that recesses are formed in said surface of said electrode thereby increasing a surface area of said electrode;removing said etch masking pattern;forming a dielectric layer on said electrode including said recesses; andforming a conductive layer on said dielectric layer opposite said electrode.