Patent ID: 6034907
Filing Date: 2000-03-07
Classification: G11C

Abstract:
A semiconductor integrated circuit device having a usual mode and a test mode, comprising:a main circuit includinga storage circuit for storing a first device identification code,a signal receiving circuit shared between a test signal supplied from the outside thereof in said test mode and an input signal supplied from the outside thereof in said usual mode and containing at least a data field assigned to a second device identification code,a comparing circuit connected to said storage circuit and said signal receiving circuit, comparing said second device identification code with said first device identification code to see whether or not said input signal is address to said semiconductor integrated circuit device and producing a preliminary hit signal when said second device identification code is consistent with said first device identification code, andan initial stage circuit responsive to a hit signal for starting at least one predetermined control sequence for other circuits; anda test circuit includinga detecting circuit responsive to an instruction signal representative of entry into said test mode for producing a test mode signal, anda logic circuit connected to said comparing circuit and said detecting circuit and producing said hit signal from one of said preliminary hit signal and said test mode signal.