Patent ID: 6432795
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of fabricating a capacitor storage node in a semiconductor device, comprising:sequentially forming a lower insulating layer, an etching stopper layer and an upper insulating layer on a semiconductor substrate; patterning the sequentially formed layers to form a storage opening to a predetermined portion of the semiconductor substrate; forming a conformal first conductive layer on the upper insulating layer and in the storage opening, the first conductive layer being polycrystalline silicon; forming a conformal second conductive layer on the first conductive layer, the second conductive layer being amorphous silicon; etching portions of the second and first conductive layers that are not within the storage opening, to form a storage node in the storage opening, the second conductive layer defining an inner wall of the storage node; removing the upper insulating layer to expose the first conductive layer, the first conductive layer defining an outer wall of the storage node; and forming HSG silicon only on the second conductive layer after said removing.