Patent ID: 8254187
Filing Date: 2012-08-28
Classification: G06F

Abstract:
1. A data transfer apparatus that performs data transfer from a transfer source to a transfer destination comprising: a data pair generation circuit that generates a data pair by making the number of transfer data items even by adding an odd number of dummy data items to the data items and pairing the even number of transfer data items, when the number of data items that are requested to transfer is odd, and outputs the generated data pair in accordance with a communication period of a handshake signal; a multiplexer that outputs one of the data pair in response to the handshake signal; a memory that stores the data output from the multiplexer in response to transitions of both a rising edge and a falling edge of a memory control input signal; a memory control circuit that performs a handshake signal communication based on a four-phase type handshake protocol and outputs a memory control signal to control the memory; a waiting circuit that outputs a request signal on condition that one of the data pair is stored in the memory and the other data is output from the multiplexer; and a data pair receiving circuit that receives the data pair from the multiplexer and the memory in response to the request signal and outputs the received data pair to the transfer destination; wherein the memory includes at least one of a level drive type latch and an edge drive type flip-flop, and the data transfer apparatus further comprises a pulse generation circuit that performs storage operation of the data in the memory by generating a pulse signal having a predetermined duration in response to transitions of both a rising edge and a falling edge of the memory control signal input, and by outputting the pulse signal to the memory.