Patent ID: 8373836
Filing Date: 2013-02-12
Classification: G02F,H01L

Abstract:
1. A gate driver-on-array integrated into a display panel, comprising: a substrate including a peripheral region; and a gate driver-on-array structure disposed in the peripheral region of the substrate, the gate driver-on-array structure comprising a first patterned metal layer, a second patterned metal layer, an insulating layer disposed therebetween, and a thin film transistor, wherein the first patterned metal layer includes a plurality of connection nodes, the insulating layer has a plurality of through holes exposing the connection nodes, and the second patterned metal layer fills into the through holes and contacts the connection nodes of the first patterned metal layer, and wherein the thin film transistor comprises a gate electrode, a source electrode, and a drain electrode disposed in the peripheral region of the substrate, each of the connection nodes of the first patterned metal layer comprises the gate electrode, and the second patterned metal layer in contact with each of the connection nodes comprises the source electrode or the drain electrode.