Patent ID: 7196003
Filing Date: 2007-03-27
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having the step of forming a wiring by a damascene method, comprising the steps of: forming an etching stopper film and an interlayer insulating film in sequence over a conductive layer; forming a silicon carbide film, a silicon nitride film, or a silicon oxynitride film as a first hard mask over the interlayer insulating film; forming a silicon oxide film as a second hard mask over the first hard mask; forming a silicon carbide film or a silicon nitride film as a third hard mask over the second hard mask; forming a silicon oxide film as a fourth hard mask over the third hard mask; forming a pattern over the fourth hard mask; etching the fourth hard mask by using the pattern; etching the third hard mask by using the fourth hard mask; etching the second hard mask by using the third hard mask; etching the first hard mask by using the third hard mask; forming an opening which reaches the etching stopper film in the interlayer insulating film by etching the interlayer insulating film by using the third hard mask; etching a portion of the etching stopper film which is exposed from the opening formed in the interlayer insulating film; and embedding a wiring material in the opening; wherein a thickness of the third hard mask is more than twice that of the first hard mask.