Patent ID: 6117712
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method for manufacturing a transistor on a semiconductor substrate having a silicon on insulator structure, said method comprising the steps of:forming a buried oxide layer in said semiconductor substrate;forming a pad oxide layer on said semiconductor substrate, thereby generating a silicon layer between said buried layer and said pad oxide layer;patterning a silicon nitride layer having a first opening on said pad oxide layer to expose a portion of said pad oxide layer;forming a thermal oxide layer on said exposed pad oxide layer by thermal oxidation to shrink said silicon layer;forming first spacers on side walls of said first opening;etching said thermal oxide layer by using said first spacers as a mask to expose said semiconductor substrate, thereby forming a second opening in said thermal oxide layer, wherein said second opening is deeper than said first opening;forming a dielectric layer having relative high dielectric constant to oxide on a surface of said silicon nitride layer, said first spacers and said second opening;forming a metal or alloy layer on said dielectric layer and in said second opening;performing a chemical mechanical polishing technique to remove a portions of said layers over said thermal oxide layer, thereby forming a gate in said second opening;removing said silicon nitride layer[,] and said first spacers adjacent to said thermal oxide layer;performing a first ion implantation to form source and drain adjacent to said gate;activating the dopants in said source and drain by thermal anneal;removing said thermal oxide layer and said pad oxide layer;performing a second ion implantation to form a LDD structure adjacent to said drain; andforming a second spacers on side walls of said gate.