Patent ID: 7601568
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method for producing a MOS transistor structure having a source region, a gate-region, a drain region, and a drift region in an SOI wafer, the SOI wafer having a carrier layer, which carries an insulating intermediate layer, the insulating intermediate layer carrying an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain-region, the active semiconductor layer at least in a portion of the drift region is thicker than in the source region, the method steps comprising: producing a trench in an SOI wafer, which serves as a starting material with an active layer having a first thickness, the trench cutting through an initially planar insulating intermediate layer, the insulating intermediate layer being applied to walls and a bottom of the trench; removing the insulating intermediate layer at least in a region from the walls, which cut through the active layer; and filling the trench with an active semiconductor layer, which is thicker than the active semiconductor layer in the source region, to form the portion of the drift region.