Patent ID: 6425056
Filing Date: 2002-07-23
Classification: G06F

Abstract:
A method of controlling a cache memory in a computer system, comprising:determining in which of first and second configurations the cache memory is organized during at least one of a plurality of power-on self-test and system initialization operations of the computer system; generating a configuration signal using a configuration control circuit based on a result of the determination, the configuration signal indicating whether the cache memory is in the first or second configuration; receiving a memory address; transmitting the configuration signal to first and second comparators; if the cache memory is of the first configuration, then enabling the first comparator to retrieve first tag data stored in the cache memory, and comparing the first tag data to the memory address using the first comparator; and if the cache memory is of the second configuration, then enabling both the first and second comparators to retrieve first and second tag data, respectively, stored in the cache memory, and comparing the first and second tag data to the memory address using the first and second comparators, respectively.