Patent ID: 8860202
Filing Date: 2014-10-14
Classification: H01L

Abstract:
1. A chip stack structure, comprising: a first chip; a second chip, disposed above the first chip; a vertical conductive line, electrically connected to the first chip and the second chip, wherein the vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip; a first substrate, wherein the first chip is disposed on the first substrate; a first horizontal conductive line, disposed in the first substrate, wherein the first horizontal conductive line connects the first chip and the vertical conductive line; a first insulating layer, covering the first substrate and the first chip; a second substrate, wherein the second chip is disposed on the second substrate; a second horizontal conductive line, disposed in the second substrate, wherein the second horizontal conductive line connects the second chip and the vertical conductive line; and a second insulating layer, covering the second substrate and the second chip.