Patent ID: 6423634
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A method, comprising:forming a gate insulation layer above a surface of a semiconducting substrate; forming a gate electrode above said gate insulation layer; forming a cover layer above said gate electrode; forming source/drain regions in said substrate proximate said gate electrode; forming a first metal layer comprised of a refractory metal above said cover layer and said source/drain regions; converting at least a portion of said first metal layer to metal silicide contacts above said source/drain regions; forming a process layer above said metal silicide contacts and said cover layer above said gate electrode; planarizing a surface of said process layer to expose said cover layer; removing said cover layer from above said gate electrode; forming a second metal layer comprised of a refractory metal above said gate electrode and said process layer; and converting at least a portion of said second metal layer to a metal silicide region above said gate electrode.