Patent ID: 6372577
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of forming a NAND-type flash memory device, comprising the steps of:forming a floating gate region over a tunnel oxide layer on a core region of a substrate; forming an insulating layer over the floating gate region; performing a periphery dual oxide process, thereby forming an oxide region having a first thickness in a high voltage periphery region and an oxide region having a second thickness in both a low voltage periphery region and in a select gate transistor region in the core region, wherein the first thickness is greater than the second thickness; forming a conductive layer over a surface of the device; and patterning the conductive layer to form a gate over the oxide region in the low voltage periphery region and in the select gate transistor region, respectively, to thereby form a low voltage periphery transistor and a select gate transistor, and form a gate over the oxide region in the high voltage periphery region and thereby form a high voltage periphery transistor and form a control gate over the insulating layer to thereby form a stacked gate flash memory cell in the core region.