Patent ID: 6826636
Filing Date: 2004-11-30
Classification: G06F

Abstract:
An architecture capable of programming and controlling access of data and instructions, in which a plurality of data transfer levels are preset and a current data transfer level is used for accessing data and instructions, comprising:a first module capable of effecting a burst transfer for continuously outputting a data string having a fixed burst length for access; a second module for storing data and instructions, wherein each data transfer level corresponds to a length of a continuous data transfer via an interface between the first and the second modules; and a burst mode controller programmed by data format accessed by the first module or a result of instruction decoding performed by the first module, so as to adjust the current data transfer level, wherein the second module is a memory device and the first module comprises: a processor kernel capable of effecting a burst transfer for continuously sending or receiving a data string having a fixed burst length for access; and a high-speed access device for storing a portion of data and instructions sent from the second module, which is available for the processor kernel to access at a high speed, wherein each data transfer level corresponds to a length of a continuous data transfer via an interface between the second module and the high-speed access device, wherein the burst mode controller is programmed by at least one instruction in the instruction set of the processor kernel, and wherein the instruction has a command field for storing a command code of the burst mode controller, a level field for storing a numeral of the level, and a reference value field for storing a numeral associated with the command code.