Patent ID: 7742265
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A circuit for protecting against ESD, the circuit comprising: a plurality of p-channel field effect transistors (FETs) coupled in series and configured in a common n-well to form a switchable current sink, wherein the switchable current sink is coupled to a positive ESD clamp rail voltage; a control circuit coupled to a control connection of the switchable current sink, the control circuit configured to couple the control connection to a negative ESD clamp rail voltage, wherein a voltage drop from the control connection to the negative ESD clamp rail voltage is lower than a threshold voltage of an n-channel field effect transistor when an ESD event occurs on the positive ESD clamp rail voltage; and a voltage divider circuit coupled to the switchable current sink for dividing down the positive ESD clamp rail voltage; wherein the control circuit comprises a gate drive circuit coupled to a respective gate of each of the plurality of p-channel FETs coupled in series, wherein the gate drive circuit is configured to couple each respective gate to the negative ESD clamp rail voltage during the ESD event; and wherein the gate drive circuit comprises: