Patent ID: 6744281
Filing Date: 2004-06-01
Classification: G06F,H03K

Abstract:
A memory device, comprising:an array of memory cells; an address decoder adapted to receive an address and to specify a location in the array of memory cells corresponding thereto; a read/write circuit coupling data to and from the specified location in the array of memory cells; a control logic circuit receiving command signals and generating control signals corresponding thereto; and a clock generator circuit receiving an input clock signal and generating from the input clock signal an output clock signal having a controllable duty cycle, the clock generator circuit comprising: a duty cycle corrector circuit structured to generate the output clock signal from the input clock signal, the duty cycle corrector circuit being structured to transition the output clock signal to a first logic level responsive to a first transition of the input clock signal after a first delay that corresponds to a first control signal, the duty cycle corrector circuit being structured to further transition the output clock signal to a second logic level that is different from the first logic level responsive to a second transition of the input clock signal that is different from the first transition of the input clock signal after a second delay that corresponds to a second control signal; a duty cycle indicating circuit coupled to receive the output clock signal from the duty cycle corrector circuit and to generate a duty cycle feedback signal corresponding thereto; and a control circuit coupled to the duty cycle indicating circuit and the duty cycle corrector circuit, the control circuit being structured to generate the first and second control signals as a function of the duty cycle feedback signal so that the first and second delays are selected to cause the output clock signal to have a predetermined delay.