Patent ID: 6638841
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A method for reducing a gate length bias, said method comprising:providing a substrate having a P well and an N well therein and an undoped conductive layer thereon; performing an N type blanket ion implantation process on said conductive layer to form a lightly doped conductive layer; performing an N type ion implantation process on the portion of said lightly doped conductive layer over said P well to form a heavily doped conductive layer by using an implantation mask covering the portion of said lightly doped conductive layer over said N well, wherein the dosage of said blanket ion implantation process is smaller than the dosage of said ion implantation process; and defining said heavily doped conductive layer and said lightly doped conductive layer separately to form an NMOS gate electrode and a PMOS gate electrode.