Patent ID: 6580296
Filing Date: 2003-06-17
Classification: H03K

Abstract:
A logic gate, comprising:complementary first and second computational blocks having first and second sets of binary inputs, respectively, said first computational block having a first set of transistors for said first set of binary inputs and sized to represent specific discrete weights, said first computation block employing said first set of transistors to develop an output binary digit that is a function of a weighted sum of a first set of input binary digits presented at said first set of binary inputs, said second computational block having a second set of transistors for said second set of binary inputs and sized to represent specific discrete weights, said second computational block employing said second set of transistors to develop a complementary output binary digit that is a function of a weighted sum of a second set of input binary digits presented at said second set of binary inputs; and a cross-coupled differential load, including: a first load circuit comprising a first load transistor sized to represent a threshold value &THgr;(M1), said first load circuit coupled to said first computational block and driven by said complementary output binary digit, and a second load circuit comprising a second load transistor sized to represent a threshold value &THgr;(M2), said second load circuit coupled to said second computational block and driven by said output binary digit, at least one of said first set of transistors being sized differently from a corresponding one of said second set of transistors if said first load transistor is sized substantially identical to said second load transistor, each of said first set of transistors being sized substantially identical to corresponding ones of said second set of transistors if said first load transistor is sized differently from said second load transistor.