Patent ID: 6311264
Filing Date: 2001-10-30
Classification: G01R,G06F

Abstract:
A digital signal processor comprising:A. a first data bus carrying first data signals;B. a first address bus carrying first address signals indicating the address of the first data signals in a first address space;C. a second data bus separate from the first data bus and carrying second data signals;D. a second address bus separate from the first address bus and carrying second address signals indicating the address of the second data signals in a second address space;E. arithmetic and logic circuitry coupled to the first and second data buses, the arithmetic and logic circuitry including multiplier circuitry coupled to an input of an arithmetic and logic unit and an accumulator coupled to an output of the arithmetic and logic unit; andF. a memory wait state register coupled to the first data bus and the first address bus, the wait state register having plural portions.