Patent ID: 6999335
Filing Date: 2006-02-14
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a first, second, third and fourth bit lines to be connected to a first, second, third and fourth ferroelectric memory cells respectively; a fifth, sixth, seventh and eighth bit lines to be connected to sense amplifier circuits forming a pair with said first, second, third and fourth bit lines respectively; a first, second, third and fourth reference cell capacitors to be connected to said fifth, sixth, seventh and eighth bit lines respectively when a reference word line is activated; a first, second, third and fourth reference cell write control lines to be connected to said first, second, third and fourth reference cell capacitors when a reference cell write control line select signal (REFST) is activated; equalization circuits for equalizing the potential of said fifth, sixth, seventh and eighth bit lines when an equalization control signal (REFEQ) is activated; and a potential setting circuit for selectively setting at least one potential of said first, second, third and fourth reference cell write control lines to a first potential or a second potential independently from at least one of the other reference cell write control lines.