Patent ID: 9032354
Filing Date: 2015-05-12
Classification: G01R

Abstract:
1. A circuit, comprising: a plurality of scan chain flip-flops coupled to circuit elements of the circuit, the scan chain flip-flops each comprising an input configured to alternatively configure the scan chain flip-flops in a first mode in which one or more test vectors may be loaded into the flip-flops and a second mode in which a stored vector may be loaded into the flip-flops; a vector memory configured to contain one test vector which, when applied to the circuit elements of the circuit while the flip-flops are in the first mode, results in lower leakage currents of second states, the one test vector determined based on heuristic data associated with the circuit; a multiplexer configured, in response to detecting an operating mode of the circuit, to set the one test vector to be the stored vector; and a clock generator configured, while the scan chain flip-flops are in the second mode, to clock the stored vector into scan chain elements of the circuit for application to the circuit elements when the operating mode is detected.