Patent ID: 7835182
Filing Date: 2010-11-16
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a NAND cell unit including a plurality of electrically rewritable non-volatile memory cells serially connected, the NAND cell unit having one end connected to a bit line via a first selection gate transistor and an other end connected to a source line via a second selection gate transistor; a first dummy cell interposed next to the first selection gate transistor in the NAND cell unit; and a second dummy cell interposed next to the second selection gate transistor in the NAND cell unit, wherein the device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor than the selected memory cell, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both the first and second boost channel being electrically separated from each other in the NAND cell unit, wherein in the data write mode, a first non-selection voltage applied to the first dummy cell is kept constant irrespective of a position of the selected memory cell in the NAND cell unit.