Patent ID: 9075738
Filing Date: 2015-07-07
Classification: G06F,H03M

Abstract:
1. An apparatus, comprising: a check node memory configured to store check nodes; a symbol node memory configured to store symbol nodes; and a control unit coupled to the check node memory and the symbol node memory, wherein the control unit includes circuitry configured to: receive a first Error Correction Code (ECC), wherein the first ECC is defined by a first set of parity equations; receive a plurality of input code words, wherein each input code word of the plurality of input code words is encoded with a second ECC, wherein the second ECC is defined by a second set of parity equations, wherein the second set of parity equations is a proper subset of the first set of parity equations; receive an indication of parity equations included in the first set of parity equations but excluded from the second set of parity equations; and decode, iteratively, each input code word of the received plurality of input code words dependent upon messages transferred between the symbol node memory and the check node memory, wherein the messages transferred between the symbol node memory and the check node memory are controlled such that messages originating from check nodes that correspond to parity check equations excluded from the second set of parity equations are prevented from affecting the symbol nodes by assigning to symbol nodes respective artificial confidence metrics that indicate a zero value with a maximal likelihood based upon the received indication of the parity equations included in the first set of parity equations but excluded from the second set of parity equations.