Patent ID: 6639269
Filing Date: 2003-10-28
Classification: H01L

Abstract:
An electrically programmable memory cell configuration, comprising:a substrate having a surface and depressions each with a bottom and mutually opposite sidewalls formed therein; a plurality of memory cells having planar transistors, each of said memory cells having a planar transistor disposed in said substrate, said planar transistor having: two source/drain regions adjoining two of said sidewalls of said depression and extending from said surface of said substrate to said bottom of said depression; a channel region disposed in said substrate in at least part of said bottom of said depression; a first dielectric layer disposed on said bottom of said depression in a region of said channel region, said dielectric layer having a thickness allowing tunneling of electrons during programming, said channel region having a cross section being parallel to said surface of said substrate and intersects said two source/drain regions; a floating gate electrode adjoining said first dielectric and partially disposed on at least two of said mutually opposite sidewalls of said depression and said depression being constricted but not filled by said floating gate electrode; a second dielectric layer; a control gate electrode disposed above said floating gate electrode and insulated from said floating gate electrode by said second dielectric; and an insulation spacer disposed on two of said sidewalls of said depression and extending from said surface of said substrate to said bottom of said depression for preventing a capacitance between said two source/drain regions and said floating gate electrode, said insulation spacer having a thickness eliminating tunneling during programming, said first dielectric layer extending from said insulation spacer of at least one of said sidewalls to the other of said sidewalls on said bottom of said depression, and parts of said floating gate electrode disposed on said two of said sidewalls of said depression adjoining said insulation spacer.