Patent ID: 6795371
Filing Date: 2004-09-21
Classification: G11C

Abstract:
A semiconductor memory apparatus having a plurality of memory elements and a control circuit controlling each of the memory elements in response to control signals and address data input from an exterior,wherein each of the memory elements comprises: a memory cell array; a first pair of data lines provided to the memory cell array; a plurality of second pairs of data lines provided to each column of the memory cell array, shared by corresponding columns of the other memory elements; a plurality of column gates provided to each column of the memory cell array, connecting, in response to a control signal from the control circuit, a pair of bit lines to the first pair of data lines or the corresponding one of the second pairs of data lines; a first sense amp that outputs, when data are to be retrieved, in response to a control signal from the control circuit, the signal output through the first pair of data lines; a first write buffer that stores, when data are to be stored, in response to a control signal from the control circuit, the data in the memory cells through the first pair of data lines; a second sense amp that outputs, when data are to be retrieved, in response to a control signal from the control circuit, the signal output through the corresponding one of second pairs of data lines; a second write buffer that stores, when data are to be stored, in response to a control signal from the control circuit, the data in desired one of the memory cells through the second pair of data lines.