Patent ID: 8122275
Filing Date: 2012-02-21
Classification: G11C

Abstract:
1. A memory interface comprising: a first delay circuit to receive a first clock signal and to output a plurality of phase-shifted versions of the first clock signal; a first output circuit coupled to receive the plurality of phase-shifted versions of the first clock signal, the first output circuit including a first multiplexer for selecting a first one of the plurality of phase-shifted versions of the first clock signal, wherein the first output circuit clocks a first signal with the selected first one of the plurality of phase-shifted versions of the first clock signal; a second output circuit coupled to receive the plurality of phase-shifted versions of the first clock signal, the second output circuit including a second multiplexer for selecting a second one of the plurality of phase-shifted versions of the first clock signal based on a delay between the first signal and a second signal, wherein the second output circuit clocks the second signal with the selected second one of the plurality of phase-shifted versions of the first clock signal; and receiver circuitry coupled to receive the first signal and the second signal and to sample the first signal on a rising or a falling edge of the second signal.