Patent ID: 9025405
Filing Date: 2015-05-05
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory block comprising a plurality of volatile memory cells; a default refresh controller responsive to a series of refresh commands received externally with respect to the semiconductor memory device, each of the refresh commands targeting a corresponding memory cell group of the volatile memory cells of the memory block to be refreshed, the default refresh controller configured, in response to each of the received refresh commands, to control at least one default refresh operation corresponding to each of the refresh commands for the respective memory cell group targeted by the corresponding refresh command; and a weak cell refresh controller configured to control at least one refresh operation of weak cell memory groups including a first memory cell group, the weak cell refresh controller responsive to a received refresh command that targets a memory cell group different from the first memory cell group and does not target the first memory cell group to control at least one refresh operation of the first memory cell group.