Patent ID: 6624666
Filing Date: 2003-09-23
Classification: H03K

Abstract:
A differential type logic circuit comprising:first and second enhancement type MOSFETs having a conductivity, each of said enhancement type MOSFETs having a source, a drain, and a gate; third and fourth depletion type MOSFETs having said conductivity, each of said depletion type MOSFETs having a source, a drain and a gate; a first input terminal connected to the gates of said first and fourth MOSFETs; a second input terminal connected to the gates of said second and third MOSFETs; a first output terminal connected at a first node to said first and third MOSFETs; and a second output terminal connected at a second node to said second and fourth MOSFETs; wherein said depletion type MOSFETs and said enhancement type MOSFETs have a same polarity; wherein said first and third MOSFETs are connected in series to said first node, one of said first and third MOSFETs being connected to a voltage source and the other of said first and third MOSFETs being connected directly to a ground; wherein said second and fourth MOSFETs are connected in series to said second node, one of said second and fourth MOSFETs being connected to said voltage source and the other of said second and fourth MOSFETs being connected directly to said ground; wherein said first output terminal is connected to the gates of said second and third MOSFETs, and said second output terminal is connected to the gates of said first and fourth MOSFETs.