Patent ID: 6055189
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of bit lines;a plurality of means for storage, each of which is provided in correspondence to one of said plurality of bit lines, outputs latch data stored therein to specific memory cells connected to the same bit line, then compares memory data stored at said specific memory cells connected to said bit line with said latch data and commonly outputs a comparison result signal corresponding to results of comparison to a data verification line; anda means for verification that first sets said one data verification line to a verification voltage to detect a change in voltage at said one data verification line caused by individual comparison result signals output by said plurality of means for storage,wherein said means for verification is provided with a first verification voltage output portion for charging said one data verification line until said verification voltage is achieved.