Patent ID: 7036222
Filing Date: 2006-05-02
Classification: H05K,Y10T

Abstract:
1. A method of making a multi-layer circuit assembly comprising the steps of: providing an inner dielectric element having a first side and a second side opposite from said first side; providing a first metal layer overlying said first side and a second metal layer overlying said second side, said first metal layer having a plurality of first openings exposing portions of said first side within said plurality of first openings, and said second metal layer having a plurality of second openings exposing portions of said second side within said plurality of second openings, said plurality of first and second openings defining edges in said first and second metal layers, each said first opening in said first metal layer being in substantial alignment with one of said plurality of second openings in said second metal layer; coating said inner dielectric element within said plurality of first and second openings, said first and second metal layers and said edges of said first and second metal layers with a dielectric material to thereby form a coated structure having first and second outer dielectric layers covering said first and second metal layers, respectively, having said dielectric material in said plurality of first and second openings of said first and second metal layers, respectively, and covering said edges of said first and second metal layers; forming a plurality of through vias extending through said coated structure, each said through via being in substantial alignment with said aligned plurality of first and second openings in said first and second metal layers; providing first and second outer metal layers covering said outer dielectric layers and providing metallic via liners in said plurality of through vias connecting said first and second outer metal layers, said metallic via liners insulated from said first and second metal layers, wherein said dielectric material extending into said plurality of through vias is disposed between said metallic via liners and said first and second metal layers; and patterning said first and second outer metal layers such that at least some of said metallic via liners are electrically isolated from said first and second metal layers, wherein said patterning of said first and second outer metal layers forms first signal lines overlying said first metal layer and second signal lines overlying said second metal layer.