Patent ID: 7886245
Filing Date: 2011-02-08
Classification: G06F

Abstract:
1. A method in a computer-aided design system for generating a functional design model of an electronic circuit, the method comprising: generating a functional representation of at least one fixed circuit element; generating a functional representation of a first clock tree; said first tree into a second tree and a third tree, wherein said first tree and said third tree comprise no fixed circuit elements, wherein said second tree includes said at least one fixed circuit element, and wherein said second tree and said third tree are coupled to each other via said at least one fixed circuit element; generating a functional representation of one or more alternative versions of said third tree, wherein said alternative versions are Boolean equivalents to said third tree, and wherein a target arrival time windows for at least one sink of said third tree is satisfied for each alternative version of said one or more said alternative versions of said third tree; generating a functional representation of one or more alternative versions of said second tree, wherein said alternative versions of said second tree are Boolean equivalents to said second tree that include said fixed circuit element, and wherein latencies for said at least one fixed circuit element connecting said second tree and said third tree are taken into account in said generating said functional representation of said one or more alternative versions of said second tree, and wherein a target arrival time windows for at least one sink of said second tree are satisfied for each alternative version of said one or more alternative versions of said second tree; selecting a first alternative version of said one or more alternative versions of said second tree having a minimum total signal arrival time at a sink of said at least on sink of said second tree; selecting a second alternative version of said one or more alternative versions of said third tree having a minimum total signal arrival time at a sink of said at least on sink of said third tree; and replacing said second and third trees with said selected first and second alternatives to generate a modified functional design model of said electronic circuit and storing said modified functional design model on a computer readable storage medium.