Patent ID: 7701742
Filing Date: 2010-04-20
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a memory cell array area; a peripheral circuit area provided on a periphery of the memory cell array area; and a boundary area having a specific width provided between the memory cell array area and the peripheral circuit area; the memory cell array area comprising a cell area including a plurality of nonvolatile semiconductor memory cells, a plurality of linear wirings extending from inside of the cell area to an area outside the cell area, and a plurality of lower layer wirings which are provided in a lower layer than the plurality of linear wirings in the boundary area and electrically connected to the plurality of linear wirings, and wiring widths of the plurality of lower layer wirings being larger than widths of the plurality of linear wirings; the peripheral circuit area including a plurality of patterns electrically connected to the plurality of linear wirings via the plurality of the lower layer wirings; the boundary area failing to be provided with the plurality of linear wirings and a wiring which is in same layer as the plurality of linear wirings.