Patent ID: 7366829
Filing Date: 2008-04-29
Classification: G06F

Abstract:
1. A single chip multithreaded processor comprising: at least one processor core that generates memory requests using a first addressing scheme; a cache memory coupled to said processor core for servicing the memory requests using a second addressing scheme; a translation lookaside buffer for translating the first addressing scheme to the second addressing scheme by performing a lookup operation using an input key value to generate an output value, said translation lookaside buffer comprising at least a first entry formed of a tag entry portion stored in a CAM and a data entry portion stored in a RAM, where said data entry portion in the RAM contains a stored tag parity value that is generated based on at least part of the tag entry portion, and where said translation lookaside buffer supports a plurality of types of address translation, and where the data entry portion stored in the RAM contains a stored tag parity value corresponding to the type of address translation of the translation lookaside buffer entry, and where the parity checking unit generates tag parity check values for each type of address translation and selects from among the generated tag parity check values to output the tag parity check value; and a parity checking unit for receiving a first input key value that has matched with the tag entry portion stored in the CAM, generating a first tag parity check value based on at least part of the first input key value, and comparing the first tag parity check value with the stored tag parity value corresponding to the matched tag entry portion to determine if there is a parity error in the matched tag entry portion, during access to the translation lookaside buffer.