Patent ID: 8867303
Filing Date: 2014-10-21
Classification: G11C

Abstract:
1. A dual-port memory having first and second ports comprising: an array of single-port memory elements; a control circuit that is coupled to the array and that is operable to read data from and write data into the array; a first request generator operable to receive a first memory access request from the first port; a second request generator operable to receive a second memory access request from the second port; and an arbitration circuit coupled to the control circuit and the first and second request generators, wherein the arbitration circuit is operable in a synchronous mode in which the first and second request generators are controlled using first and second clock signals having equal frequencies and is operable to direct the control circuit to fulfill a single one of the first and second memory access requests during each clock period of the first clock signal and during each clock period of the second clock signal.