Patent ID: 8518776
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, the method comprising: forming an auxiliary layer over a substrate; forming at least one auxiliary region by patterning the auxiliary layer and removing material of the auxiliary layer; forming a first spacer element in a region in which material of the auxiliary layer has been removed; doping a first connection region having a first conductivity type of a tunnel field effect transistor, the first spacer element and the auxiliary region serving as a mask; covering the first connection region with a covering material; removing material of the auxiliary region; forming a second spacer element in a region in which material of the auxiliary region has been removed; and doping a second connection region having a second conductivity type of the tunnel field effect transistor, the second spacer element and the covering material serving as a mask during the doping of the second connection region, the first conductivity type being opposite to the second conductivity type, wherein the first connection region and the second connection region form input/output nodes of the tunnel field effect transistor, wherein patterning the auxiliary layer comprises forming a projection having two sidewalls facing away from one another.