Patent ID: 6202186
Filing Date: 2001-03-13
Classification: G01R

Abstract:
An apparatus for performing a series of tests on an integrated circuit (12), the tester comprising:a host computer (36);a pattern generator (46);a plurality of tester circuits (40, 44, 50-56); andbus means (32, 34, 38, 41, 47, 60) for interconnecting said host computer, said pattern generator and said plurality of tester circuits,wherein said tester circuits perform said series of tests on said integrated circuit, with characteristics of each test of said series of tests being determined by parameter control data written into said tester circuits, and with actions to be carried out by said tester circuits during each test of said series of tests being controlled by a sequence of pattern data supplied as input to said tester circuits during the test,wherein the pattern generator is programmed to supply a sequence of pattern data to said tester circuits via said bus means during each test of said series of tests and to interrupt said host computer via said bus means when said host computer is to supply a sequence of pattern data to said tester circuits via said bus means during each test of said series of tests,wherein the pattern generator includes means for transmitting an interrupt to said host computer via said bus means at any time during said series of tests, andwherein the host computer responds to said interrupt by writing parameter control data into said tester circuits via said bus means to configure them for carrying out the test.