Patent ID: 8659948
Filing Date: 2014-02-25
Classification: G11C,H01L

Abstract:
1. A method for reading a memory cell, the method comprising: transitioning a first control signal applied to a source region or a drain region of a transistor of the memory cell from a first voltage level to a second voltage level, the memory cell consisting essentially of the transistor, wherein a body region of the transistor is configured to be electrically floating; transitioning a second control signal applied to a gate of the transistor from a third voltage level to a fourth voltage level, wherein initiation of the second control signal follows initiation of the first control signal, wherein the second control signal comprises a voltage pulse of shorter duration than the first control signal, wherein a difference between the first voltage level and the third voltage level is as small as approximately 0.8 volts, and wherein a difference between the second voltage level and the fourth voltage level is as small as approximately 1.0 volts; and sensing a read current released by the transistor for reading both logic high and logic low data states from the memory cell in response to the second control signal.