Patent ID: 6782466
Filing Date: 2004-08-24
Classification: G06F

Abstract:
A computer system, comprising:a digital processing means for digitally processing data; a memory arrangement arranged in a plurality of addressable banks of memory cells and having arrays in the banks addressable via column and row bits for accessing the memory cells; and logic means for directing address and control signals generated by the digital processing means and selecting the addressable column address and row address bits with a lower order group of the address bits directed to select die column address bits, the next highest group of the address bits directed to select bank address bits, and the next highest group of the address bits directed to select the row address bits, wherein the memory mapping circuit is adapted for read-write memory with column address lines corresponding to a memory arrangement page size that is smaller than a virtual page size, wherein the read-write memory is a DRAM and wherein the memory mapping circuit is adapted for read-write memory with column address lines corresponding to a set of contiguous DRAM pages that map entirely into a virtual page.