Patent ID: 7188134
Filing Date: 2007-03-06
Classification: G06F

Abstract:
1. An adder to sum two binary numbers, comprising: a first circuit having a plurality of carry-merge stages connected in a series, the first circuit adapted to generate a group of carries, the group of carries including a final carry generated by a final stage of the series, a first carry generated by a first stage of the series and a second carry generated by one of the plurality of stages of the series located between the first and final stages of the series; a second circuit connected to the first circuit and having a plurality of stages, the second circuit connected to receive the final carry and the second carry and adapted to produce a pair of conditional carry, the second circuit adapted to generate additional carries missing from the group of carries to provide one carry for every group of a predetermined number of bits of the two binary numbers; at least one sum generator connected to the first circuit and the second circuit and connected to receive the first carry and one of the pair of conditional carry, the sum generator adapted to generate a pair of conditional sums; and at least one device adapted to select between the pair of conditional sums in response to one of the group of carries.