Patent ID: 6622186
Filing Date: 2003-09-16
Classification: G06F,H04L,H04Q

Abstract:
A buffer for adapting data flows from input channels to output channels, said buffer comprising:a DRAM organized in blocks, the DRAM containing, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, the DRAM also containing a main queue of free blocks for listing unoccupied blocks; and a memory controller for managing assignment of the blocks to the chains of linked blocks, the memory controller including a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment, wherein when a level of the partial queue reaches a predetermined minimum limit, the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit, the cache memory is at least partially emptied by a burst into the main queue.