Patent ID: 6501296
Filing Date: 2002-12-31
Classification: H03K

Abstract:
A logic/memory circuit, comprising:a logic/memory array having lookup table and product term generator modes, the logic/memory array comprising rows and columns of memory elements associated in pairs within each column, wherein: when the logic/memory array is in the product term generator mode a pair of memory elements representing a variable stores related values, and when the logic/memory array is in the lookup table mode each memory element stores an independent value, and each pair of memory elements has an associated product term generating circuit providing a product term based on the values stored in the associated pair of memory elements when the logic/memory array is in the product term generator mode; a decoder circuit coupled to the logic/memory array and selecting a column of memory elements in the logic/memory array; and a multiplexer circuit coupled to the logic/memory array and selecting a row of memory elements in the logic/memory array.