Patent ID: 6147516
Filing Date: 2000-11-14
Classification: H03K

Abstract:
A power edge detector, comprising:a voltage divider receiving and dividing an input power voltage to generate a divided voltage;said voltage divider comprising:a first PMOS transistor having its source for receiving said input power voltage, and its gate and its drain for outputting said divided voltage;a second PMOS transistor having its source for outputting said divided voltage; anda first NMOS transistor having its gate for receiving a control signal, its drain connected to the drain of said second PMOS transistor, and its source connected to a ground potential;a pull-up circuit receiving said input power voltage and transmitting said input power voltage to an output terminal when said input power voltage is less than a predetermined threshold; anda cut-in pull-down circuit connected to said voltage and said divided pull-up circuit for pulling down a voltage level of said output terminal in response to said divided voltage when said input power voltage exceeds said predetermined threshold.