Patent ID: 6689643
Filing Date: 2004-02-10
Classification: H01G,H01L

Abstract:
A process for forming an adjustable capacitor, comprising:providing a silicon wafer having a topmost layer on which are contact pads connected to a circuit contained in said wafer; depositing a base dielectric layer on said topmost layer, including said contact pads; on said base dielectric layer, depositing an etch stop layer, selected from the group consisting of silicon nitride and silicon carbide, to a thickness between about 20 and 500 microns; depositing a support dielectric layer on said etch stop layer; etching a via hole through said support dielectric layer, said etch stop layer, and said base dielectric layer, thereby exposing said contact pad; depositing a barrier layer in said via hole, then overfilling said via hole with tungsten and then planarizing so as to remove all tungsten not inside said via; etching three trenches that extend through said support dielectric layer as far as said etch stop layer; depositing a first layer of metal on said support dielectric layer, including inside said trenches, and then patterning said first metal layer to form a common capacitor electrode that contacts said tungsten-filled via hole; depositing a layer of high dielectric constant material on said common capacitor electrode and then patterning said high dielectric constant layer whereby it fully overlaps said common capacitor electrode; depositing a second layer of metal on said high dielectric constant layer and then patterning said second metal layer to form four unconnected top electrodes, all of whom are overlapped by said common electrode, said top electrodes having, relative to one another, areas in the ratio 5:2:1:1; depositing a top dielectric layer on said top electrodes and said high dielectric constant layer; etching four via holes through said top dielectric layer whereby a contact area is exposed for each of said top electrodes; depositing a barrier layer in said via holes, then overfilling said via holes with tungsten and then planarizing so as to remove all tungsten not inside said via holes; and then depositing and patterning a third metal layer so as to provide permanent connections between said top electrodes, thereby giving said adjustable capacitor a specific capacitance value.