Patent ID: 8295070
Filing Date: 2012-10-23
Classification: G11C

Abstract:
1. A resistance change memory comprising: a semiconductor substrate; a stacked layer structure stacked on the semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance element and a (n+1)-th conductive line, where n is a natural number equal to or larger than 2; and a first to a n-th drivers which drives the first to the (n+1)-th conductive lines, wherein the odd-numbered conductive lines from the semiconductor substrate among the first to (n+1)-th conductive lines extend in a first direction along a surface of the semiconductor substrate, the even-numbered conductive lines from the semiconductor substrate among the first to (n+1)-th conductive lines extend in a second direction along the surface of the semiconductor substrate, and the first direction intersects with the second direction, wherein a g-th variable resistance element among the first to the n-th variable resistance elements is provided between a g-th conductive line and the (g+1)-th conductive line, where g is one of 1, 2, . . . and n, wherein sizes of the first to (n+1)-th drivers become large gradually from the first driver to the (n+1)-th driver.