Patent ID: 6835627
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A method for forming a body region in a drain region of a DMOS device on a wafer after a gate has been formed with the body region extending partly beneath the gate of the DMOS device and appropriately aligned with the gate, the drain region defining a surface plane, the method comprising the steps of:(a) implanting a suitable dopant in a portion of the drain region adjacent the gate for forming the body region to have a desired drain/source threshold voltage, and (b) implanting a suitable dopant in the said portion of the drain region adjacent the gate for forming the body region to have a desired breakdown voltage through the drain region, steps (a) and (b) being performed in any order, and the dopant being implanted in step (a) by directing the dopant at a first angle to the surface plane of the drain region for directing at least some of the dopant beneath the gate, the first angle to the surface plane at which the dopant is directed in step (a) being less than a second angle to the surface plane at which the dopant is directed in step (b).