Patent ID: 6242354
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A method of forming a semiconductor device, comprising the steps of:providing a gate electrode structure;forming a sidewall spacer adjacent each opposite sidewall of said gate electrode structure, each spacer overlying a portion of a source region or a drain region proximate said gate electrode structure;forming metal silicide regions;subsequent to forming said metal silicide regions, etching said sidewall spacers to remove at least a portion of said sidewall spacers;subsequent to etching said sidewall spacers, forming a conformal etch-stop layer overlying said semiconductor device;forming a dielectric layer overlying said etch-stop layer;etching a first portion of a first contact opening to at least a portion said gate electrode structure and second contact openings to at least a portion of each said silicide regions, wherein said dielectric layer is removed to expose said etch-stop layer; andetching a second portion of said first contact opening and said second contact openings, wherein said etch-stop layer is removed to expose said portions of said gate electrode structure and silicide region.