Patent ID: 8969942
Filing Date: 2015-03-03
Classification: G11C,H01L,Y10S

Abstract:
1. A non-volatile semiconductor memory device comprising: a plurality of memory cell units each including at least one memory cell formed by stacking a charge storing layer and a control gate layer above a first gate insulating film above a semiconductor substrate, the at least one memory cell in which data is programmed and erased by capturing and releasing a charge of the charge storing layer; a plurality of select transistors each connected to the plurality of memory cell units, each of the select transistors having a first gate electrode layer disposed above a second gate insulating film above the semiconductor substrate and a conductive layer disposed above the first gate electrode layer, the conductive layer formed of the same conductive film as the control gate layer; and a plurality of transistors each for driving and for controlling a voltage for controlling the at least one memory cell and the select transistor, wherein the plurality of transistors includes at least a first transistor having a third gate insulating film and a second gate electrode layer disposed above the third gate insulating film and a second transistor having a fourth gate insulating film with a different thickness from the third gate insulating film and a third gate electrode layer disposed above the fourth gate insulating film, the first gate insulating film, the second gate insulating film and the third gate insulating film are films simultaneously formed of the same insulating film, and the charge storing layer, the first gate electrode layer, the second gate electrode layer and the third gate electrode layer are films formed of the same conductive film, and the first gate insulating film, the second gate insulating film and the third gate insulating film have substantially the same thickness.