Patent ID: 6929996
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A double corner rounding process for a partial vertical cell, comprising: providing a substrate comprising a memory cell array region and a supporting region and having a first mask layer thereon, wherein a deep trench is formed in the first mask layer and the substrate in the memory cell region, a capacitor is formed in a lower portion of the deep trench, a first insulating layer is formed in the upper portion of the deep trench, and the surface of the first insulating layer is lower than that of the substrate; filling a second mask layer in the deep trench, wherein the surface of the second mask layer is lower than that of the first mask layer; forming a photoresist layer on the active areas of the substrate, such that a first portion of the substrate, covered by the photoresist layer, and a second portion of the substrate, not covered by the photoresist layer, are defined; removing parts of the first mask layer not covered by the photoresist layer and the second portion of the substrate until the surface of the second portion of the substrate is lower than that of the first mask layer; removing the photoresist layer and the second mask layer; removing the edge of the first mask layer until the corner of the first portion of the substrate is exposed; performing a first rounding process on the corner of the first portion of the substrate; conformally forming a second insulating layer on the first mask layer, the first insulating layer, and the substrate; forming an insulating plug on the second insulating layer, such that the surface of the insulating plug is substantially level with that of the second insulating layer on the substrate; removing the insulating plug, the second insulating layer, and the first mask layer from the memory cell array to expose the corner of the first portion of the substrate; performing a second rounding process on the corner of the substrate in the memory cell array region.