Patent ID: 8086926
Filing Date: 2011-12-27
Classification: G01R

Abstract:
1. A failure diagnostic apparatus for failure-diagnosing a semiconductor integrated circuit device, comprising: a plurality of scan chains, each of the plurality of scan chains including a plurality of scan flip-flops coupled in series and receiving signals from the semiconductor integrated circuit device; and a compression circuit that compresses output signals of the plurality of scan chains to output a first compressed signal, wherein a plurality of virtual compression circuits is provided, each of the plurality of virtual compression circuits compressing output signals of scan flip-flops which are provided at a corresponding stage of the plurality of scan chains to output a second compressed signal, wherein the second compressed signal is compared with the first compressed signal to failure-diagnose the semiconductor integrated circuit device, wherein an assumed failure in the semiconductor integrated circuit device is transmitted via the second compressed signal, and the failure diagnostic apparatus carries out failure simulation based on the assumed failure.