Patent ID: 6265254
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device having an n-channel MIS transistor formed at a first portion and a first conductor layer at a second portion in a p-well region anda p-channel MIS transistor formed at a first portion and a second conductor layer at a second portion in an n-well region, comprising the steps of:(a) forming the p-well region and the n-well region in a semiconductor substrate;(b) forming a first mask covering the first portion in the n-well region and exposing the first portion in the p-well region and the second portion in the n-well region;(c) implanting n-type impurity into the p-well region and the n-well region at a portion exposed from the first mask to form n-type impurity implanted regions;(d) implanting p-type impurity into the p-well region and the n-well region at a portion exposed from the first mask to form p-type impurity implanted regions; and(e) forming a second conductor layer at the second portion in the n-well region;wherein the n-type impurity implanted regions are implanted deeper than the p-type impurity implanted region, and wherein the second conductor layer electrically connects with the n-type impurity implanted region in the n-type well region.