Patent ID: 6061267
Filing Date: 2000-05-09
Classification: G11C

Abstract:
A memory configuration, comprising:a memory array comprising a plurality of memory cells arranged in a plurality of rows and columns;a plurality of wordlines, wherein each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period, wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias;circuitry for providing a first back bias operable to cause the at least one transistor in each of the memory cells in the selected row to have a first threshold voltage;circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some of the non-selected rows to have a second threshold voltage during the period;wherein the first threshold voltage is different than the second threshold voltage; andwherein the at least one transistor coupled to receive the back bias is coupled to receive the back bias from a buried wordline corresponding to the row.