Patent ID: 9202818
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method of manufacturing a 3D stacked semiconductor structure, comprising: forming a multi-layer on a substrate, and the multi-layer comprising a plurality of first dielectric layers and second dielectric layers arranged alternately; patterning the multi-layer to form a plurality of first patterned stacks and spaces between the first patterned stacks, and the spaces exposing a top surface of a bottom layer of the first dielectric layers, wherein one of the first patterned stacks has a width of F removing parts of the second dielectric layers of one of the first patterned stacks, so as to form a plurality of first cavities in said first patterned stack; filling the first cavities in said first patterned stack with first conductors forming a charge-trapping layer as a liner of one of the spaces; and forming a plurality of bit lines on the first patterned stacks and deposited in the spaces for contacting the charge-trapping layer in the spaces, wherein the first patterned stacks extend along a first direction, and the bit lines extend along a second direction perpendicular to the first direction, and wherein the bottom layer of the first dielectric layers of the multi-layer is directly formed on the substrate, and the substrate is completely covered by the bottom layer during formation of the first conductors.