Patent ID: 8749413
Filing Date: 2014-06-10
Classification: H03M

Abstract:
1. A digital correction circuit for a pipelined analog-to-digital converter (ADC), the pipelined ADC including N stages of first sub-circuits, each of which outputting a 2-bit code, the 2-bit code output by the n-th-stage of first sub-circuit being expressed as D 2(N+1-n) and D 2(N+1-n)-1 , where N is an integer greater than 3 and n is an integer satisfying 1≦n≦N, the digital correction circuit comprising N stages of second sub-circuits, among which: the first-stage of second sub-circuit is configured to receive the 2-bit code D 2N and D 2N−1 output by the first-stage of first sub-circuit; the i-th-stage of second sub-circuit is configured to receive both the 2-bit code D 2(N+1-i) and D 2(N+1-i)-1 output by the i-th-stage of first sub-circuit and an output from the (i−1)-th-stage of second sub-circuit, where i is an integer satisfying 2≦i≦N−1; and the N-th-stage of second sub-circuit is configured to receive D 2 ; wherein the digital correction circuit outputs N+1 quantized bits, including a first quantized bit Q the quantized bit Q the quantized bit Q and the quantized bit Q