Patent ID: 8817201
Filing Date: 2014-08-26
Classification: G02F

Abstract:
1. A method of manufacturing an array substrate, comprising: step 1 of forming gate lines, gate electrodes, data lines, source electrodes and drain electrodes on a base substrate, wherein the data lines extend across each of the pixel units, which are defined by intersecting the gate lines and date fines, in the middle of the pixel units, there are formed two gate electrodes, two source electrodes and two drain electrodes in each pixel unit, and wherein, in each pixel unit, one source electrode and one drain electrode are provided on one side of the corresponding data line, and the other source electrode and the other drain electrode are provided on the other side of the corresponding data line, the two source electrodes are connected to a corresponding data line of the pixel unit, and the two gate electrodes are connected to a corresponding gate line of the pixel unit; step 2 of depositing a passivation layer on the base substrate after the step 1 and forming a via hole in the passivation layer on each drain electrode by a patterning process; and step 3 of depositing a transparent conductive layer on the base substrate after the step 2 and forming a pattern comprising pixel electrodes by a patterning process so that the pixel electrode in each pixel unit is connected with both of the two drain electrodes in the pixel unit through the via holes in the passivation layer.