Patent ID: 8769470
Filing Date: 2014-07-01
Classification: G06F

Abstract:
1. A method of improving timing closure in chip design, comprising: identifying a critical timing path in a chip design pattern, wherein a timing window of the critical timing path is smaller than a predetermined timing window; determining a variation of each segment of the critical timing path, wherein the variation indicates uncertainty of delay of a device and/or a wire caused by one or more factors; and changing at least one segment of the critical timing path based on the variation of each segment of the critical timing path to enlarge the timing window of the critical timing path; and wherein determining a variation of each segment of the critical timing path comprises: obtaining an early mode delay value and a late mode delay value of each segment of the critical timing path; and determining a difference between the late mode delay value and the early mode delay value as the variation wherein one or more steps are performed by a computer.