Patent ID: 6084459
Filing Date: 2000-07-04
Classification: H03K

Abstract:
A voltage level shifting circuit, comprising:a first PMOS transistor, a first pull-up PMOS transistor, and a first pull-down NMOS transistor connected in series between a voltage Vpp terminal and a voltage Vss terminal, the first pull-up PMOS transistor and first pull-down NMOS transistor having a common drain which acts as a first voltage terminal;a second PMOS transistor, a second pull-up PMOS transistor, and a second pull-down NMOS transistor connected in series between the voltage Vpp terminal and the voltage Vss terminal and configured symmetrically with respect to the first PMOS transistor, the first pull-up PMOS transistor and the first pull-down NMOS transistor, the second pull-up PMOS transistor and second pull-down NMOS transistor having a common drain which acts as a second voltage terminal;a first MOS transistor, having a drain connected to the Vpp terminal, for increasing a level of the second voltage terminal during a level shifting and decreasing a driving capacity of the first pull-up PMOS transistor;a second MOS transistor, having a drain connected to the Vpp terminal, for increasing a level of the first voltage terminal during a level shifting and decreasing a driving capacity of the second pull-up PMOS transistor.