Patent ID: 7875919
Filing Date: 2011-01-25
Classification: H01L

Abstract:
1. A circuit comprising a FET and a shallow trench capacitor, wherein the FET comprises: a gate stack, the gate stack comprising a high-K dielectric layer and a metal layer, the metal layer disposed on the high-K dielectric layer, and wherein the shallow trench capacitor comprises; a trench extending into a surface of a substrate and having a depth (d) and a width (w), wherein the depth (d) of the trench is less than 5 times the width (w) of the trench; a cell well implanted to have a first polarity encompassing the trench; the trench is filled with an insulating layer followed by a conductive layer, wherein the insulating layer comprises a layer of the same high-K dielectric used in the high-K dielectric layer of the gate stack of the FET, and wherein the conductive layer comprises a layer of the same metal used in the metal layer of the gate stack of the FET and wherein is both the high-K dielectric layer and the metal layer are patterned so as to have a portion located over the trench; and source/drain implantations in the substrate on opposite sides of the trench and having the same polarity as the cell well.