Patent ID: 6713329
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of manufacturing a CMOS inverter comprising:providing a substrate; growing i &mgr;c-Si layer on the substrate; growing p+ &mgr;c-Si on the i &mgr;c-Si layer; patterning the p+ &mgr;c-Si source and drain for p channel TFT; depositing isolation SiO2 over the p channel TFT; forming a window in the isolation SiO2; depositing an n+ &mgr;c-Si layer on the i &mgr;c-Si layer through the window; patterning the n+ &mgr;c-Si source and drain for n channel TFT; removing the isolation SiO2 layer; defining an i &mgr;c-Si island; depositing SiO2 as a gate insulator;, patterning the SiO2 gate; opening contact holes to the n and p channel TFT source and drain; and evaporating and patterning metal to form gate source and drain electrodes of the n and p channel TFTs, and metal interconnects between the gates.