Patent ID: 6147546
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A zero volt/zero current fuse arrangement for use in integrated circuits comprising two latches having inverter circuits coupled to each other and a fuse having a first and second terminal, characterized in that the first latch is formed by a first inverter having its output connected to said first terminal of said fuse and a NOR circuit having one of its inputs connected to the second terminal of said fuse and the second latch is formed by an NFET circuit connected to the second terminal of said fuse and a second inverter connected to the second terminal of said fuse for coupling to said first latch, and apart from power on, the arrangement will not draw any DC current, and the first and second inverters are both formed of a PFET and an NFET, and the PFET of the first inverter has a large Width/Length ratio, and the NFET of the first inverter and the said NFET circuit of the second latch have a small Width/Length ratio and are of the same size such that said large and small Width/Length ratios are determined that, with an intact fuse, the voltage potential at the second inverter's input will also be recognized as a logical ""1"" at said NOR input.