Patent ID: 8659959
Filing Date: 2014-02-25
Classification: G06F,G11C

Abstract:
1. A memory device comprising: an internal clock for generating clock signals; a command receiver for receiving commands; a data strobe driver for generating a data strobe signal, the data strobe signal utilized to capture data on a data bus, the capturing upon completion of a data strobe preamble time, wherein the completion of the data strobe preamble time indicates that the data strobe signal has achieved a steady switching state and is measured from receipt of a command on the command receiver; programmable preamble control circuitry in communication with the data strobe driver for determining when the data strobe preamble is completed, the programmable preamble control circuitry programmed during memory device initialization; a mode register storing a bit decoding table for determining a preamble length, the preamble length utilized by the programmable preamble control circuitry for determining when the preamble is completed, wherein the preamble length is a number of one or more clock cycles selected from the bit decoding table based on a current data rate of the memory device and a bus loading condition of the memory device, wherein the preamble length is further based on: a location of the memory device accessed by a previous command, and based on the location of the memory device accessed by the command.