Patent ID: 6133096
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method of fabricating a flash memory cell, and peripheral devices, on a semiconductor substrate, comprising the steps of:growing a gate insulator layer, and an overlying first polysilicon layer, on a first region of said semiconductor substrate, to be used for said peripheral devices, wherein said first polysilicon layer is an intrinsic layer, obtained via LPCVD procedures at a thickness between 1500 to 3000 Angstroms;growing a tunnel oxide layer on a second region of said semiconductor substrate, to be used for said flash memory cell, and forming said tunnel oxide layer, on the top surface of said first polysilicon layer;depositing a second polysilicon layer, on said tunnel oxide, located in said first region of said semiconductor substrate, while forming a polysilicon floating gate shape, on said tunnel oxide layer, via patterning of said second polysilicon layer, in said second region of said semiconductor substrate;forming stacked gate structures, on said tunnel oxide layer, in said second region of said semiconductor substrate, with each stacked gate structure comprised of: an overlying, first dielectric layer; a polycide layer; an underlying second dielectric layer; and a portion of said polysilicon floating gate shape;forming a first source/drain region, in an area of said second region of said semiconductor substrate, not covered by said stack gate structures;patterning of said tunnel oxide layer, and of said first polysilicon layer to form a gate structure, overlying said gate insulator layer, in said first region of said semiconductor substrate;forming a lightly doped source/drain region, in an area of said first region of said semiconductor substrate, not covered by said gate structure;forming a second source/drain region, in an area of said second region of said semiconductor substrate, not covered by said stack gate structures;forming insulator spacers on the sides of said stacked gate structures, and on the sides of said gate structure;forming a heavily doped source/drain region, in a an area of said first region of said semiconductor substrate, not covered by said gate structure, or by said insulator spacers, and in an area of said second region of said semiconductor substrate, not covered by said stacked gate structures, or by said insulator spacers;removing said tunnel oxide from the top surface of said gate structure, and selectively forming a metal silicide layer on said heavily doped source/drain regions, and on said top surface of said gate structure, wherein said metal silicide layer is a titanium disilicide layer, formed via initially depositing a titanium layer via R.F. sputtering at a thickness between about 200 to 500 Angstroms, followed by an anneal procedure using either RTA or conventional furnace procedures, at a temperature between about 650 to 800.degree. C., selectively forming said metal silicide layer on said heavily doped source/drain region and on the top surface of said gate structures, located in said first region of said semiconductor substrate, and removing unreacted regions of said titanium layer in a solution containing H.sub.2 O.sub.2 --HCl--NH.sub.4 OH--H.sub.2 O, at a temperature between about 25 to 100.degree. C.;depositing a thick interlevel dielectric layer;forming self-aligned contact, (SAC), openings in said thick interlevel dielectric layer, in said second region of said semiconductor substrate, exposing a portion of the top surface of said stacked gate structures, and exposing said second source/drain region, located between the stack gate structures, while also forming contact hole openings in said thick interlevel dielectric layer, in said first region of said semiconductor substrate, exposing said metal silicide layer, located on said heavily doped source/drain regions;opening a word line contact hole in said interlevel dielectric layer, and in said first dielectric layer, in a third region of said semiconductor substrate, to expose a portion of the top surface of said polycide layer;forming conductive SAC structures, in said SAC openings, located in said second region of said semiconductor substrate, forming conductive plug structures in said contact hole openings, located in said first region of said semiconductor substrate, and forming a word line plug structure, in said word line contact hole, located in said third region of said semiconductor substrate; andforming metal interconnect structures, on said thick interlevel dielectric layer, overlying and contacting, said conductive SAC structures, said conductive plug structures, and said word line plug structure.