Patent ID: 7830185
Filing Date: 2010-11-09
Classification: H03L

Abstract:
1. A duty cycle correction (DCC) circuit comprising: a first delay configured to receive a first clock input signal, delay the first clock input signal by a predetermined period, and generate a first internal clock signal; a multiplexer configured to receive the inverting signal of the first clock input signal and a second clock input signal, and output one of the inverting signal of the first clock input signal or the second clock input signal in response to an enable signal, wherein the enable signal is enabled when a delayed locked loop (DLL) unit is locked; a second delay for delaying an output signal of the multiplexer by a predetermined period, and generating a second internal clock signal; and a duty cycle mixing unit for mixing a phase of the first internal clock signal with a phase of the second internal clock signal, wherein the first clock input signal is out of phase with the output signal of the multiplexer.