Patent ID: 8243500
Filing Date: 2012-08-14
Classification: G11C,H01L

Abstract:
1. A semiconductor memory, comprising a memory cell including: a first and a second inverters each including a load transistor and a driver transistor; a latch circuit formed by coupling inputs and outputs of the first and the second inverters with each other, and having a first storage node coupled to the output of the first inverter and a second storage node coupled to the output of the second inverter; a first and a second transfer transistors coupling the first and the second storage nodes to a first bit line pair, respectively; a third and a fourth transfer transistors coupling the first and the second storage nodes to a second bit line pair, respectively; and a first and a second short transistors coupling the first and the second storage nodes with each other, wherein: the first transfer transistor, the first short transistor, and the driver transistor of the second inverter are disposed along one direction; the fourth transfer transistor, the second short transistor, and the driver transistor of the first inverter are disposed along one direction; the first transfer transistor and the first short transistor have a diffusion layer in common coupled to the first storage node; the first short transistor and the driver transistor of the second inverter have a diffusion layer in common coupled to the second storage node; the fourth transfer transistor and the second short transistor have a diffusion layer in common coupled to the second storage node; and the second short transistor and the driver transistor of the first inverter have a diffusion layer in common coupled to the first storage node.