Patent ID: 6148436
Filing Date: 2000-11-14
Classification: G01R,G06F

Abstract:
A computer implemented method for generating a gate-level description of an integrated circuit cell, said method comprising the steps of:a) accessing a simulation library to obtain a table-based description of said integrated circuit cell, said simulation library stored in a memory unit;b) determining whether said table-based description describes a combinational circuit or a sequential circuit;c) if said table-based description describes a combinational circuit, automatically generating a complete combinational ordered ternary decision diagram (OTDD) graph of said table-based description and automatically generating a gate-level description of said table-based description based on said complete combinational OTDD graph;d) if said table-based description describes a sequential circuit, automatically generating a gate-level description of said table-based description based on a clock OTDD graph of said table-based description and also based on a complete sequential OTDD graph of said table-based description; ande) storing said gate-level description of said table-based description in a first library stored in said memory unit.