Patent ID: 7548458
Filing Date: 2009-06-16
Classification: G11C

Abstract:
1. A method of biasing a multi-level-cell (MLC) memory device having a plurality of charge trapping memory cells in a memory array, each charge trapping memory cell in the plurality of charge trapping memory cells having 2 n logic states including a first logic state, a second logic state, a third logic state, a fourth logic state, each charge trapping memory cell having a first charge trapping site for storing a first bit and a second charge trapping site for storing a second bit, comprising: programming the plurality of charge trapping memory cells by simultaneously biasing a respective source terminal and a respective drain terminal in each of the plurality of charge trapping memory cells and applying a gate voltage to a respective terminal in each of the plurality of charge trapping memory cells; determining a bit in each of the plurality of charge trapping memory cells that has been over-programmed by reading a voltage value of the bit and comparing with a reference voltage value, the over-programmed bit having a source terminal, a drain terminal and a gate terminal; erasing the over-programmed bit by biasing simultaneously the source terminal and the drain terminal of the over-programmed bit; and reprogramming the over-programmed bit that is erased during the erasing operation.