Patent ID: 6085334
Filing Date: 2000-07-04
Classification: G06F,G11C

Abstract:
An integrated circuit, comprising:a memory array;a plurality of spare memory elements for repairing defective locations of the memory array;a built-in self-test circuit, coupled to the memory array, for detecting faults in the memory array, and in response to detecting a fault, providing an address corresponding to a failed memory location that caused the fault and producing an output signal indicating when a fault is detected;a built-in self-repair circuit, coupled between the built-in self-test circuit and the memory array, the repair circuit causing the failed memory location of the memory array to be replaced with a spare memory element of the plurality of spare memory elements; anda built-in self-repair monitoring circuit, coupled to the built-in self-test circuit and comprising a signature generator, the built-in self-repair monitoring circuit generating a signature based on a compression of addresses corresponding to failed memory locations, wherein the signature is used to determine that a repair result of the memory array is invariant over different environmental conditions.