Patent ID: 6141700
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A single chip data processor comprising:a central processing unit;a first electrically erasable and programmable memory, assigned to an address space which can be accessed by the central processing unit, and having a first address area storing one or more vector addresses and a second address area storing one or more operation programs, wherein the central processing unit executes the one or more operation programs stored in the second address area in a normal mode;a second memory assigned to the address space which can be accessed by the central processing unit, the second memory having an address area storing the one or more vector addresses;an external terminal, wherein the first electrically erasable and programmable memory is erased or programmed in response to a voltage supplied to the external terminal at a time when the first electrically erasable and programmable memory is in an erasing or programming mode; andan interrupt control circuit supplying an interrupt request to the central processing unit in response to an interrupt event;wherein, if the first electrically erasable and programmable memory is in the erasing or programming mode, and if the interrupt request is supplied from the interrupt control circuit, then the one or more vector addresses stored in the second memory is used to respond to the interrupt request.