Patent ID: 7058840
Filing Date: 2006-06-06
Classification: G06F,H03K,H04L

Abstract:
1. An Apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock, comprising: means for sampling the first signal with the second clock to determine whether the first signal has a predetermined logic state, the means for sampling the first signal with the second clock including a first clock state controlled flip-flop driven by the second clock with an input where the first signal is applied and an output for outputting a first sampling signal indicating a logic state of the first signal sampled with the second clock; means for sampling the first signal with a clock phase shifted to the second clock to determine whether the first signal has the predetermined logic state, the means for sampling the first signal with a clock phase shifted to the second clock including a second clock state controlled flip-flop driven by the clock phase shifted to the second clock with an input where the first signal is applied and an output for outputting a second sampling signal indicating a logic state of the first signal sampled with the clock phase shifted to the second clock; means for generating the second signal based on the second clock beginning with the subsequent clock cycle of the second clock if it has been determined by at least one of the sampling means that the first signal has the predetermined logic state; means for carrying out an OR link having a first input connected to the output of the first clock state controlled flip-flop, a second input connected to the output of the second clock state controlled flip-flop and an output connected to means for generating, wherein said means for generating are responsive to means for carrying out an OR link to begin generating the second signal at the subsequent clock cycle; and said means for generating include: an RS flip-flop with a set input connected to the output of means for carrying out an OR link, a reset input for receiving a reset signal and an output; and a counter having a reset input connected to the output of the RS flip-flop, an input for receiving the second clock and an output for outputting a clock divided by a predetermined power of 2 as the second clock beginning at the subsequent clock cycle.