Patent ID: 6101133
Filing Date: 2000-08-08
Classification: G11C

Abstract:
Circuitry for preventing accidental writes to a memory from occurring due to simultaneous transitions of an address signal and a write enable signal, the circuitry comprising:a. an address buffer for buffering the address signal to generate an internal address signal representing an address within the memory, the address buffer having a first delay of a first duration;b. an address transition detector for generating an address transition signal in response to detection of a transition of the address signal, the address transition detector have a second delay of a second duration; andc. a race detector for generating a write clock signal in response to the write enable signal and the address transition signal, the write clock signal having a read state and a write state, the read state of the write clock signal causing the memory to read data from the address represented by the internal address signal, the write state of the write clock signal causing the memory to write data at the address represented by the internal address signal, the race detector forcing the write clock to the read state in response to an active state of the address transition signal, the race detector having a third delay of a third duration, a combined delay of the second and third duration being less than the first duration.