Patent ID: 6785154
Filing Date: 2004-08-31
Classification: G11C

Abstract:
A magnetic random access memory circuit block, comprising:a memory array in which a plurality of wordlines and a plurality of bitlines are provided in matrix form and a memory element is provided at intersections of the wordlines and the bitlines, said memory elements including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through a respective bitline coupled thereto; a read wordline driver for applying a read voltage to a wordline; a write wordline driver for providing a write current onto said wordline; a bitline driver for providing a write current onto a bitline; a sense amplifier for sensing and amplifying data in a memory element; an input/output pad for inputting and outputting data; a module for sensing a data write current passing through said bitline; and a module for generating a stop signal for stopping the supply of the data write current to said bitline and said wordline after data is written in said memory element.