Patent ID: 6208494
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:a plurality of input/output terminals through which a signal is input/output with respect to an external source;first and second power supply lines to supply a first power supply potential;third and fourth power supply lines to supply a second power supply potential lower than said first power supply potential;a first transistor group formed on a main surface of said semiconductor substrate, and receiving power supply potential from said first and third power supply lines, said first transistor group includinga plurality of transistors forming an internal circuit that carries out a predetermined process according to a signal applied to said input/output terminals to output a corresponding data signal;a second transistor group including a plurality of transistors formed on a main surface of said semiconductor substrate, receiving power supply potential from said second and fourth power supply lines, each transistor having the same transistor size, said second transistor group includinga first transistor subgroup forming an output buffer provided between the input/output terminal from which said data signal is output out of said input/output terminals and said internal circuit, and that applies a buffer process on said data signal,a second transistor subgroup forming a first protection circuit protecting said output buffer and said internal circuit from a surge generated between said input/output terminal and any of said second and fourth power supply lines, anda third transistor subgroup forming a second protection circuit provided between said first power supply line and said second power supply line, and between said third power supply line and said fourth power supply line, to protect said internal circuit from a surge generated between said input/output terminal and any of said first and third power supply lines.