Patent ID: 8232168
Filing Date: 2012-07-31
Classification: G11C,H01L

Abstract:
1. A method for fabricating a microelectronic device with one or plural double-gate transistors, comprising: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form a second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.