Patent ID: 6654838
Filing Date: 2003-11-25
Classification: H04L

Abstract:
A method for performing bit sensitive peer addressing in a communications system including an n-bit parallel bus, a bid/busy line, an ack line and a clock line, together with a plurality of ports attached to said bus, where n is an integer, comprising the steps of:(a) assigning each port on said bus a unique address corresponding to a single bit data line of the n-bit bus; (b) bidding for control of said bus by utilizing a protocol that requires each port seeking control during a given clock cycle to drive its unique address bus bit line to a preassigned state via a single data trace when the bid/busy line is in a predetermined state; (c) utilizing said bid/busy line to address all of said ports in said clock cycle to carry a composition of port address bits corresponding to bus bid requests when the bid/busy line is in said predetermined state; and (d) simultaneously reading the contents of the bus at each port to determine if another port is driving its unique address bus bit line to said preassigned state, thus during a single bid clock cycle allowing multiple ports to drive the data bus simultaneously while reading said bus to determine if any competing bids have been placed for bus control.