Patent ID: 7893462
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A transistor of a semiconductor device, comprising: an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer, wherein material of the source and drain electrodes penetrates to the first Si planar doped layer to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and an upper part of the gate electrode is formed to overlap only the drain electrode.