Patent ID: 8319758
Filing Date: 2012-11-27
Classification: G09G,H04L

Abstract:
1. An interface system, comprising: a serializing unit for receiving first data having a plurality of bits and second data having a plurality of bits, and serially outputting the plurality of bits of the first data and the plurality of bits of the second data as 2 bits; a transmission circuit for generating four voltage levels corresponding to the 2 bits supplied from the serializing unit; a receiving circuit for recovering the 2 bits using the voltage levels supplied from the transmission circuit; and a deserializing unit for recovering the first data and the second data while sequentially storing the 2 bits supplied from the receiving circuit, wherein a bit of the 2 bits comprises one of the bits of the first data, and an other bit of the 2 bits comprises one of the bits of the second data.