Patent ID: 6593786
Filing Date: 2003-07-15
Classification: H03L

Abstract:
A semiconductor device having a register controlled delay locked loop (DLL) and an internal circuit synchronized with a DLL clock signal outputted from the register controlled DLL, the semiconductor device comprising:a clock divider producing a divided clock signal by dividing an internal clock signal generated in response to an external clock signal; a clock generator producing a reference clock signal, wherein the reference clock signal is activated after a half period of the external clock signal; a delay model delaying the divided clock signal to compensate for a delay time in delay paths of the internal clock signal; a comparison unit comparing a phase difference between the reference clock signal and an output signal from the delay model and thereby generating a phase comparison signal; a delay unit having a plurality of unit delayers; and a controller controlling an amount of delay of the internal clock signal and the divided clock signal via the delay unit in response to the phase comparison signal from the comparison unit.