Patent ID: 7698470
Filing Date: 2010-04-13
Classification: G11C,H01L

Abstract:
1. An integrated circuit being configured as a memory chip, the integrated circuit comprising: a first external connection; a second external connection; a third external connection; a memory circuit; and a first buffer between the first external connection and the memory circuit, wherein the integrated circuit is switchable between a master mode of operation, in which the first buffer between the first external connection and the memory circuit is activated and in which data is received via the first external connection and the received data is forwarded to another integrated circuit via the second external connection, and a slave mode of operation, in which the first buffer between the first external connection and the memory circuit is deactivated and in which data exchange with the memory circuit is performed via the third external connection, and wherein the second external connection is geometrically positioned opposite the third external connection on opposing main surfaces of the memory chip such that when two identical memory chips are stacked one on top of the other, the second external connection of one of the two memory chips is in electrical contact with the third external connection of the second one of the two memory chips.