Patent ID: 6788610
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A method for conducting a multiple word line selection test on a semiconductor memory device provided with a plurality of memory cell blocks, which include a first memory cell block and a second memory cell block, each of the memory cell blocks having a plurality of memory cells and a plurality of word lines connected to the memory cells, and a plurality of sense amp groups connected to the first and second memory cell blocks, each of the sense amp groups amplifying cell information read from the plurality of memory cells of an associated one of the memory cell blocks, the method comprising:a first step for activating one of the plurality of word lines in the first memory cell block and activating the sense amp group associated with the first memory cell block after a predetermined time; a second step for activating word lines in the first memory cell block other than the one that has been activated in the first memory cell block; a third step for activating one of the plurality of word lines in the second memory cell block and activating the sense amp group associated with the second memory cell block after a predetermined time; and a fourth step for activating word lines in the second memory cell block other than the one that has been activated in the second memory cell block; wherein the first and second steps are followed by the third and fourth steps or the first and third steps are followed by the second and fourth steps.