Patent ID: 6804150
Filing Date: 2004-10-12
Classification: G11C

Abstract:
A non-volatile integrated circuit memory device comprising:a bit line; a first select line; a first select transistor having a control electrode connected to the first select line and a current path, one end of which is connected to the bit line; a word line disposed adjacent to and in parallel with the first select line; a non-volatile memory cell transistor having a control electrode connected to the word line and a current path, one end of which is connected to the other end of the current path of the first select transistor; a second select line; a second select transistor having a control electrode connected to the second select line and a current path, one end of which is connected to a second end of the current path of the non-volatile memory cell transistor, and a second end of which is connected to a ground reference voltage; a high voltage pump circuit for generating a high voltage above a power supply voltage during a program operation of the non-volatile memory cell transistor; a select line driver for supplying a select voltage limited below the power supply voltage to the first select line while the high voltage is applied to the word line; a word line decoder for receiving the high voltage and the select voltage to apply a program voltage to the word line; and a slope control circuit for controlling a rising slope of the program voltage, the slope control circuit structured to provide an increase in the program voltage for a predetermined time long enough to inhibit a capacitive coupling between the first select line and the word line during the program operation.