Patent ID: 9129814
Filing Date: 2015-09-08
Classification: C23G,H01L

Abstract:
1. A method of forming a target pattern for an integrated circuit, the method comprising: forming a plurality of lines over a substrate with a first mask; forming a spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines; removing at least a portion of the spacer layer to expose the plurality of lines and the substrate; shrinking the spacer layer disposed onto the sidewalls of the plurality of lines, wherein the shrinking of the spacer layer is isotropic and includes a wet process using a solution selectively tuned to remove a portion of the spacer layer while the plurality of lines and the substrate remain substantially unaltered; and after the shrinking of the spacer layer, removing the plurality of lines thereby providing a patterned spacer layer over the substrate.