Patent ID: 8637849
Filing Date: 2014-01-28
Classification: B82Y,H01L

Abstract:
1. A Vertical Field Effect Transistor (VFET) device with a Vertical Semiconductor Nanowire (VSN) having therein an FET channel region between doped source and drain regions with said source and drain regions formed in distal ends of said VSN outside of said channel region, with said device comprising: a bottom conductive layer and an upper conductive layer; said VSN which is columnar formed in a stack of layers extending between said bottom conductive layer and said upper conductive layer; said stack of layers including said bottom conductive layer, a bottom spacer layer, the combination of a gate conductor at least partially surrounded by a gate electrode, an upper spacer layer, and said upper conductive layer; said bottom conductive layer, serving as a source/drain electrode layer formed on a substrate; said bottom spacer layer composed of a dielectric or insulating material formed on said bottom conductive layer having a top surface and surrounding a lower end of said VSN; a gate dielectric which is either ring-shaped or tube-shaped and is located in a recessed notch or pocket in said device surrounding and in direct contact with sidewalls of said VSN and in direct contact with a top surface of said bottom spacer layer and extending thereabove; said gate electrode surrounding and in direct contact with exterior sidewalls of said gate dielectric and extending thereabove; said upper spacer layer composed of a dielectric or insulating material formed above said gate electrode; said upper conductive layer serving as a second source/drain electrode layer formed on top of said upper spacer layer; said VSN extending through said stack of layers from said upper conductive layer to said bottom conductive laver; said VSN having a bottom end formed in electrical and mechanical contact with said bottom conductive layer and said VSN having a top end in electrical and mechanical contact with said upper conductive layer; and said VSN including said FET channel region located between said doped source region and said doped drain region formed at distal ends of said VSN with said bottom conductive layer and said upper conductive layer connected to a respective one of said source region and said drain region, wherein said gate dielectric formed between said bottom spacer layer and said gate electrode.