Patent ID: 7310263
Filing Date: 2007-12-18
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array in which memory cells are arranged in a matrix, each of the memory cells being formed by connecting a current path of a MOS transistor and a resistor in series, and one-bit information being stored by using a pair of memory cells; a word line connected to gates of MOS transistors in memory cells in the same row of the memory cell array; a plurality of bit lines provided so as to correspond to columns in the memory cell array, each of the plurality of bit lines being connected to one terminal of a corresponding one of resistors in memory cells in the same column; and a read circuit configured to determine one-bit stored information stored in the pair of memory cells, the read circuit determining the stored information by comparing two output signals read to two bit lines from the pair of memory cells comprising a memory cell in one column and a memory cell in another column of the memory cell array, wherein the stored information in the pair of memory cells is determined in accordance with whether a difference between resistance values of the resistors in the pair of memory cells is smaller than a predetermined value.