Patent ID: 8405162
Filing Date: 2013-03-26
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends, wherein the gate electrode level region includes a first gate level feature having its first end located at a first position relative to the first direction and its second end located at a second position relative to the first direction, wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a first transistor of a first transistor type, wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type, wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type, wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a second common line of extent in the first direction, wherein the gate electrode level region includes a sixth gate level feature having its first end located at the first position relative to the first direction and its second end located at the second position relative to the first direction, wherein the second, third, fourth, and fifth gate level features are positioned between the first and sixth gate level features in the second direction, wherein the first and second transistors of the first transistor type are separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region, wherein a first pair of the second, third, fourth, and fifth gate level features are electrically connected to each other, and wherein a second pair of the second, third, fourth, and fifth gate level features are electrically connected to each other, the second pair exclusive of the first pair, and wherein each of the first and second transistors of the first transistor type and the first and second transistors of the second transistor type has a corresponding diffusion region electrically connected to a common node; a first gate contact defined to physically contact the second gate level feature; a second gate contact defined to physically contact the third gate level feature; a third gate contact defined to physically contact the fourth gate level feature; and a fourth gate contact defined to physically contact the fifth gate level feature, wherein one of the first, second, third, and fourth gate contacts is positioned over either a first outer portion of the gate electrode level region or a second outer portion of the gate electrode level region, wherein the first outer portion of the gate electrode level region extends in the first direction away from the first and second transistors of the first transistor type and away from the inner portion of the gate electrode level region, and wherein the second outer portion of the gate electrode level region extends in the first direction away from the first and second transistors of the second transistor type and away from the inner portion of the gate electrode level region.