Patent ID: 6459652
Filing Date: 2002-10-01
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a data output circuit for sensing and amplifying data in a memory cell array and for synchronizing the amplified data with a data enable clock signal to output the data; an echo clock generator synchronized with the data enable clock signal and receiving a power source voltage and a ground voltage to generate an echo clock; a delay circuit comprising a plurality of delay paths, wherein each delay path delays the data enable clock by different time, and wherein the delay circuit selects a delay path of the plurality of delay paths in response to a delay path select signal to supply the delayed data enable clock to the data output circuit and the echo clock generator; a test controller for generating a mode select signal and a delay path test signal in response to a test code signal; and a delay signal selection circuit comprising a plurality of fuses for producing a default delay path select signal based on a programmed state of the plurality of fuses, and a multiplexer, responsive to the mode select signal, for selectively providing the default delay path select signal or the delay path test signal to the delay circuit as the delay path select signal.