Patent ID: 8078923
Filing Date: 2011-12-13
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: first memory region including a plurality of memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region configured to temporarily store data read from the first memory region or to temporarily store data to be written to the first memory region; a read counter configured to store a data read count for each memory group; an error-correcting circuit configured to calculate an error bit count of the read data; and a controller configured to: if the error bit count of the read data exceeds a first threshold which is determined based on a maximum error bit count of bits correctable by the error-correcting circuit, perform a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back to the same memory group, wherein the data written back is error bit-corrected data; and if the error bit count of the read data does not exceed a first threshold and the read count stored in the read counter exceeds a second threshold, perform a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back to the same memory group, wherein the data written back is error bit-corrected data.