Patent ID: 6731294
Filing Date: 2004-05-04
Classification: G06T

Abstract:
A circuit, comprising:a first operation unit operably coupled to receive a first set of operands, wherein the first operation unit combines the first set of operands to produce a first operation result, wherein subsequent to receipt of the first set of operands, the first operation unit receives a second set of operands and combines the second set of operands to produce a second operation result; a pre-accumulation register operably coupled to the first operation unit, wherein the pre-accumulation register stores the first operation result to produce a buffered first operation result; a second operation unit operably coupled to receive a third set of operands, wherein the second operation unit combines the third set of operands to produce a third operation result, wherein a first operand of the third set of operands is the second operation result; memory operably coupled to the second operation unit, wherein the memory stores the third operation result in one of a plurality of memory locations; and a selection block operably coupled to the memory, the second operation unit, the pre-accumulation register, and the first operation unit, wherein the selection block selects a second operand of the third set of operands from a set of potential operands, wherein the set of potential operands includes the second operation result, the buffered first operation result stored in the pre-accumulation register, and data stored in at least one of the plurality of memory locations of the memory, wherein the selection block selects the second operand of the third set of operands based on operand selection information included in an operational code received by the circuit.