Patent ID: 8335114
Filing Date: 2012-12-18
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix; a plurality of word lines connected to the plurality of memory cells; a plurality of bit lines connected to each of one end of the memory cells; and a control circuit configured to control the potentials of said plurality of word lines and said plurality of bit lines, wherein the control circuit sets a first voltage to first word lines of k (k is a natural number) of the plurality of word lines in an erase verify operation, sets a second voltage to second word lines of h (h is a natural number) of the plurality of word lines, and carries out the erase verify operation, wherein the memory cells constitute a plurality of blocks as an erase unit, and wherein the memory cells in the blocks are series-connected and which constitutes a series circuit, the second word lines are connected to the memory cells arranged at both ends of the series circuit, and the first word lines are connected to the another memory cells of the series circuit.