Patent ID: 8076709
Filing Date: 2011-12-13
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: an array of a plurality of memory cells, each of the memory cells including: (e) wherein a plurality of first lines and second lines are included, each first line connecting the first conductors of memory cells arranged in a first direction, and each second line connecting the first semiconductor regions positioned on the first conductor side of memory cells arranged in a second direction, which is perpendicular to the first direction, (f) wherein an erase operation is performed by injecting first carriers, which have a first polarity that is either positive or negative and are generated by band-to-band tunneling, into the charge storage section of a selected memory cell while a potential having the first polarity is applied to the first line that is connected to the selected memory cell, and wherein, when the first-carrier injection is performed, second carriers, which flow between the first and second semiconductor regions of the selected memory cell and have a second polarity that is opposite the first polarity, are injected into the charge storage section of the selected memory cell.