Patent ID: 7094671
Filing Date: 2006-08-22
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a transistor, the method comprising: providing a workpiece, the workpiece having a top surface; implanting germanium into the top surface of the workpiece, forming an amorphous germanium-containing region within the top surface of the workpiece, the amorphous germanium-containing region extending about 45 Å or less beneath the workpiece top surface, wherein implanting germanium into the top surface of the workpiece also forms a first crystalline germanium-containing region beneath the amorphous germanium-containing region, the first crystalline germanium-containing region extending about 55 Å or less beneath the amorphous germanium-containing region; depositing a gate dielectric material over the amorphous germanium-containing region, the gate dielectric material having a dielectric constant of about 4.0 or greater; annealing the workpiece at a temperature of about 750° C. or less for about 60 minutes or less, re-crystallizing the amorphous germanium-containing region and forming single second crystalline germanium-containing region within the top surface of the workpiece, the single second crystalline germanium-containing region comprising the re-crystallized amorphous germanium-containing region and the first crystalline germanium-containing region, the second crystalline germanium-containing region extending about 120 Å or less beneath the workpiece top surface; depositing a gate material over the gate dielectric material; patterning the gate material and gate dielectric material to form a gate and a gate dielectric over the second crystalline germanium-containing region; and forming a source region and a drain region in at least the second crystalline germanium-containing region.