Patent ID: 7155643
Filing Date: 2006-12-26
Classification: G11C

Abstract:
1. A semiconductor integrated circuit, comprising: a memory which has a set of redundant lines for repair in a column direction; a test pattern generating section which generates a specific test pattern for said memory; a comparing section which reads an output from said memory to judge whether or not a faulty cell exists in said memory and outputs a signal showing the existence or nonexistence of said faulty cell and including a pass/fail judgment signal for every bit; a first data storage section which, in a first test mode for a test of said memory, retrieves a signal which has branched from all or a part of column address signals which are inputted into said memory from said test pattern generating section and the pass/fail judgment signal for said every bit generated by said comparing section as faulty address data, and which during a test of peripheral logic of said memory, forms a part of a scan chain and is used for observing an input signal into said memory and which, in a second test mode for a scan test, configures a part of the scan chain and is used for observing the failure which is transmitted to the memory; a second data storage section which receives an output signal of said comparing section to store a state of presence or absence of a failure corresponding to the existence or nonexistence of said faulty cell; and a repair judging section which receives an input to said first data storage section and an output of retained contents in said first data storage section and judges that said memory is repairable, wherein: when said second data storage section is in a state where said failure exists, said first data storage section holds the data retained in said first data storage section.