Patent ID: 7535024
Filing Date: 2009-05-19
Classification: H01L

Abstract:
1. A fabrication method of a display device having a thin film transistor comprising a semiconductor layer, a gate electrode which is formed above the semiconductor layer, a gate insulation film which is formed between the semiconductor layer and the gate electrode, and a background layer underneath the semiconductor layer, wherein the method includes the steps of: forming the gate electrode so as to include at least a first gate electrode, and a second gate electrode which overlaps the first gate electrode the second gate electrode having a size thereof in the channel direction which is set smaller than a corresponding size of the first gate electrode; forming the semiconductor layer so as to include a channel region which is overlapped by the second gate electrode, a first impurity region having a first impurity concentration overlapped by the first gate electrode and formed outside of the second gate electrode so that the second pate electrode does not overlap the first impurity region in the channel direction, a second impurity region having a second impurity concentration formed outside of the second gate electrode so that the second gate electrode does not overlap the second impurity region in the channel direction, and a third conductive impurity region having a third impurity concentration formed outside the gate electrode so that the gate electrode does not overlap the first impurity region in the channel direction and the third conductive impurity region is formed outside of the second impurity region in the channel direction; wherein the first impurity region, the second impurity region and the third impurity region are respectively formed of the same semiconductor type; wherein the first impurity concentration is lower than the third impurity concentration, and the second impurity concentration is lower than the first impurity concentration; and wherein impurities are simultaneously implanted into both of the first and second impurity regions using a single process so that the impurities are implanted into the first impurity region through the first gate electrode and the impurities are implanted into the second impurity region so that a peak position of the impurity concentration in a depth direction is located in the background layer underneath the semiconductor layer thus limiting the second impurity concentration below the first impurity concentration.