Patent ID: 7280427
Filing Date: 2007-10-09
Classification: G11C

Abstract:
1. A data access circuit of a semiconductor memory device, comprising: a read/write controller enabled by a write control signal to receive a column cycle signal and to output an input/output driver enable signal; a plurality of ports each to receive serial data to be written, to convert the serial data to parallel data divided into a first portion and a second portion, and to output the parallel data; a plurality of read/write data control units to receive a plurality of port select signals and a port select disable signal to select a relevant port of the plurality of ports, and to output port select buffer enable signals and port select buffer disable signals; a plurality of write buffer units to buffer the parallel data received from each of the plurality of ports to simultaneously output only one of the first portion and the second portion of the parallel data of each of the plurality of ports to data lines in one column latch cycle period in response to the port select buffer enable signals and the port select buffer disable signals from the plurality of read/write data control units; and an input/output driver to receive data inputted from the data lines to output the received data to a plurality of input/output lines in response to the input/output driver enable signal from the read/write controller.