Patent ID: 6014762
Filing Date: 2000-01-11
Classification: G11C

Abstract:
An apparatus for allowing an SRAM array to be tested, the SRAM array having scannable outputs, the apparatus comprising:a first flip-flop having a first flip-flop data input latched high, a first flip-flop scan-in input latched high, a clock input coupled to an externally controlled signal source, a scan enable input coupled to a scan enable signal, and a first flip-flop output, the first flip-flop inverting the first flip-flop data input at the first flip-flop output when the scan enable signal is low, and placing the first flip-flop scan-in input signal at the first flip-flop output when the scan enable signal is high;a second flip-flop having a second flip-flop data input coupled to the first flip-flop output, a second flip-flop scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and a second flip-flop output, the second flip-flop inverting the second flip-flop data input at the second flip-flop output when the scan enable signal is low, and placing the second flip-flop scan-in input signal at the second flip-flop output when the scan enable signal is high;a third flip-flop having a third flip-flop data input coupled to an inversion of the second flip-flop output, a third flip-flop scan-in input, a clock input coupled to the signal source, a scan enable input latched low, and a third flip-flop output, the third flip-flop inverting the third flip-flop data input at the third flip-flop output;a first AND gate having a first input coupled to an inversion of the scan enable signal, a second input coupled to the second flip-flop output, and a first AND gate output; anda second AND gate having a first input coupled to the first AND gate output, a second input coupled to the third flip-flop output, and a second AND gate output coupled to a write enable signal enabling the SRAM array.