Patent ID: 8410590
Filing Date: 2013-04-02
Classification: H01L

Abstract:
1. A device, comprising: a power semiconductor chip comprising a first electrode on a first surface, and a second electrode and a third electrode on a second surface opposite to the first surface; a leadframe comprising a carrier and a first lead and a second lead, the power semiconductor chip placed on the carrier with the first surface of the power semiconductor chip facing the carrier, wherein the first lead is electrically coupled to the first electrode of the power semiconductor chip, and wherein the second lead is electrically separate from the first lead and is laterally offset from the power semiconductor chip such that no portion of the second lead is disposed above the second surface of the power semiconductor chip; and a metallic layer separate from the leadframe and comprising a first surface and a second surface opposite to the first surface, the metallic layer disposed on the second surface of the power semiconductor chip with the first surface of the metallic layer facing the power semiconductor chip, wherein the metallic layer extends between and directly electrically connects the second electrode of the power semiconductor chip to the second lead, wherein the second surface of the metallic layer, a surface of the first lead, and a surface of the second lead lie within a common mounting plane.