Patent ID: 8283753
Filing Date: 2012-10-09
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; an insulating interlayer on said semiconductor substrate; a multiple-layered interconnect embedded in said insulating interlayer; an electrode pad provided so as to be opposite an upper surface of an uppermost layer of said multiple-layered interconnect, said electrode pad having a bump electrode for an external coupling mounted thereon; and a first insulating film interposed between said uppermost layer of said multiple-layered interconnect and said electrode pad, said first insulating film consisting of a single material contacting an entirety of an uppermost surface of said uppermost layer of said multiple-layered interconnect, said first insulating film covering an upper portion of said insulating interlayer and having a concave portion provided in a region opposite said uppermost surface of said uppermost layer of said multiple-layered interconnect, thereby forming a capacitor element with said uppermost layer of said multiple-layered interconnect and said electrode pad, wherein a thickness of said first insulating film is reduced in the region where said concave portion is formed, and a capacitance is formed in the region of said first insulating film having the reduced thickness.