Patent ID: 6191613
Filing Date: 2001-02-20
Classification: H03K

Abstract:
A programmable logic device comprising:a. a plurality of configurable logic blocks, each having a logic-block clock terminal;b. a programmable interconnect matrix adapted to selectively interconnect ones of the configurable logic blocks;c. a delay-locked loop having:i. a clock-input terminal;ii. a clock-output terminal adapted to provide a clock signal; andiii. a lock-signal output terminal;d. a sequencer having a sequencer input terminal connected to the lock-signal output terminal and a sequencer output terminal connected to each of the configurable logic blocks; ande. a clock-distribution network having an input terminal connected to the clock-output terminal and a plurality of distributed clock terminals connected to respective ones of the logic-block clock terminals, the network adapted to distribute the clock signal to the plurality of configurable logic blocks.