Patent ID: 7581150
Filing Date: 2009-08-25
Classification: G01R

Abstract:
1. In scan testing of an integrated circuit with a plurality of scan paths, a method for debugging scan testing failures of the integrated circuit, comprising: (a) identifying a plurality of bad scan paths and at least one good scan path; (b) generating a scan path clock set for each scan path within said plurality of bad scan paths and for at least one good scan path; (c) creating a union of scan path clock sets for said plurality of bad scan paths; (d) removing good clock elements from said union based on clock elements contained within at least one good scan path; (e) for each of the clock elements remaining in said union after step (d), determining a probability of failure of each clock element based on the clock element's clock input count; and (f) analyzing the clock elements remaining in said union after step (d) in an order based on the probabilities of failure determined in step (e).