Patent ID: 6433768
Filing Date: 2002-08-13
Classification: G09G

Abstract:
A liquid crystal display device having a pair of opposing substrates at least one of which is transparent and a liquid crystal layer sandwiched between said pair of opposing substrates comprising:a plurality of video signal lines, a plurality of scanning signal lines perpendicular to said plurality of video signal lines, a plurality of pixels arranged in a matrix and each surrounded by two adjacent video signal lines among said plurality of video signal lines and by two adjacent scanning signal lines among said plurality of scanning signal lines, each of said plurality of video signal lines being connected to pixels among said plurality of pixels arranged in a same column of said matrix via a respective switching element, each of said plurality of scanning signal lines being connected to the switching elements of pixels among said plurality of pixels arranged in a same row of said matrix, a video signal line drive circuit for supplying video signal voltages to each of said plurality of video signal lines, a power supply for supplying 2M gray scale voltages varying with a horizontal scanning period to said video signal line drive circuit, and a display control circuit for controlling said video signal line drive circuit, wherein said display control circuit supplies display data of at least N bits and P kinds of time control signals varying with the horizontal scanning period to said video signal line drive circuit, said video signal line drive circuit includes: memory for storing said display data of at least N bits, a plurality of selector circuits each associated with a respective one of said plurality of video signal lines, for selecting one of the 2M gray scale voltages in accordance with M bits of the display data of at least N bits, a plurality of switching circuits each associated with a respective one of said plurality of video signal lines, and each comprising P switching elements, said P switching elements each being supplied with a respective one of the P kinds of time control signals and a first fixed voltage, for selecting one of the respective one of the P kinds of time control signals and the first fixed voltage in accordance with a corresponding one of Q bits other than the M bits, of the display data of at least N bits, the first fixed voltage being in common for all of said P switching elements, the P kinds of time control signals comprising such pulses as to uniquely determine a time represented by the Q bits of the display data based upon the Q bits of the display data, a plurality of logic circuits each associated with a respective one of said plurality of video signal lines, each being supplied with the selected ones of the respective one of the P kinds of time control signals and the first fixed voltage from said P switching elements, and each being configured so as to change state when all of the selected ones of the respective one of the P kinds of time control signals and the first fixed voltage are the first fixed voltage, and a plurality of output circuits each associated with a respective one of said plurality of video signal lines, each being configured so as to supply a voltage level of the selected one of the 2M gray scale voltages at an instant when a corresponding one of said plurality of logic circuits changes state, to a corresponding one of said plurality of video signal lines.