Patent ID: 6236239
Filing Date: 2001-05-22
Classification: G06F

Abstract:
An output-buffer circuit comprising:a first output transistor connected between a first power line and an output node;a second output transistor connected between the output node and a second power line;an output-transistor control circuit which controls an on/off state of said first and second output transistors; anda capacitor for controlling a through-rate of an output signal output to the output node, wherein said output-transistor control circuit includes:a pull-up circuit connected between the first power line and a given node;a pull-down circuit connected between the given node and a second power line;a first switch device connected between a gate of said first output transistor and the given node and having an on/off state thereof controlled by a first driver input;a second switch device connected between the first power line and the gate of said first output transistor and having an on/off state thereof controlled by the first driver input;a third switch device connected between a gate of said second output transistor and the given node and having an on/off state thereof controlled by a second driver input; anda fourth switch device connected between the gate of said second output transistor and the second power line and having an on/off state thereof controlled by the second driver input, wherein said capacitor is connected between the output and the given node.