Patent ID: 7336099
Filing Date: 2008-02-26
Classification: G06F,H03K

Abstract:
1. A multiplexer, comprising: an addition element, adapted to receive first and second one-bit values and a carry input value, and to supply a carry output value, the carry output value being high every time two or more of the first and second one-bit values and the carry input value are high; and a logic device, for receiving a first data input value and a first select input, wherein the logic device is adapted to route the first data input to the addition element as the first one-bit value; and wherein the logic device is adapted to route the first data input to the addition element as the second one-bit value when the first select input takes a first value, and is adapted to route an inverse of the first data input to the addition element as the second one-bit value when the first select input takes a second value.