Patent ID: 6169695
Filing Date: 2001-01-02
Classification: G11C

Abstract:
A circuit for transferring data in an array of memory cells arranged in rows and columns, comprising: a plurality of row lines; a plurality of pairs of complementary digit lines; each of the memory cells in the array having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell; a plurality of sense amplifiers, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states; a plurality of equilibration circuits, each equilibration circuit coupled between one of the pairs of complementary digit lines operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibrate signal; and a control circuit coupled to the plurality of row lines, and the equilibration circuits, the control circuit operable to: write a pattern of data to an initial row of the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line to which the memory cells in another row are connected; terminate the row enable signal for the another row; and generate the equilibrate signal.