Patent ID: 7548996
Filing Date: 2009-06-16
Classification: G06F

Abstract:
1. In an information processing system, having a plurality of modules including a processor, a cache memory, a main memory and a plurality of I/O devices, a data streamer for performing data transfer operations between said modules comprises: a buffer memory which stores data to be transmitted to said modules; a transfer engine configured to execute memory transfer operations through said buffer memory; a channel state memory, coupled to said transfer engine, configured to have an area to command the data transfer for said cache memory, said channel state memory executing a data transfer to said cache memory as a memory constituent through said buffer memory when data is written into said area, said channel state memory being further configured to transfer information for every channel, wherein said channel state memory stores at least two source descriptors corresponding to a memory transfer operation, said source descriptors including a location of data to be transferred from a source module as well as a designated cache memory and wherein said source descriptors maintain a halt bit configured to store information concerning when the channel serving said data transfer operation will be halted when all of the data is transferred, wherein said transfer engine reads said source descriptors from said channel state memory, said data transfer engine retrieving said data from said source module indicated in said source descriptors and transferring said data to said cache memory designated by said source descriptors; and a priority scheduler for determining an execution order of a channel, wherein said priority scheduler determines an execution schedule of a channel for every one of said descriptors in accordance with a channel priority value pre-designed in said channel state memory.