Patent ID: 8338906
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. An integrated circuit structure, comprising: a semiconductor substrate having a first area and two second areas separated from each other by shallow trench isolation (STI) regions; a well region of a first conductive type formed in the semiconductor substrate; a metal silicide layer formed on the well region within the first area and having an internal portion and an outer portion, wherein a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region; a guard ring of a second conductive type opposite the first conductivity type formed on the well region within the first area and encircling the metal silicide layer, wherein the outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring and the outer edge of the guard ring physically contacts the shallow trench isolation (STI) regions; two diffusion regions of the first conductive type formed in the well region within the two second areas respectively; an inter-dielectric layer formed on the shallow trench isolation region; and a conductive contact structure formed in the inter-dielectric layer and comprising a first conductive contact in physical contact with the internal portion and the outer portion of the metal silicide layer and two second conductive contacts in contact with the two diffusion regions respectively, wherein the conductive contact structure is isolated to the two diffusion regions via the inter-dielectric layer.