Patent ID: 6283131
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method to pattern a polysilicon layer in the manufacture of an integrated circuit device comprising:providing a polysilicon layer overlying a semiconductor substrate;providing a hard mask layer overlying said polysilicon layer;providing a resist layer overlying said hard mask layer;patterning said resist layer to form a resist mask that exposes a part of said hard mask layer;patterning said polysilicon layer wherein said patterning is performed sequentially in a dry plasma etch chamber and wherein said patterning comprises:etching said hard mask layer exposed by said resist mask to form a hard mask that exposes a part of said polysilicon layer;thereafter stripping away said resist mask;thereafter cleaning away polymer residue from said hard mask wherein said cleaning away comprises a chemistry containing CF.sub.4 gas; andthereafter etching said polysilicon layer exposed by said hard mask; andstripping away said hard mask to complete the patterning of said polysilicon layer in the manufacture of the integrated circuit device.