Patent ID: 9059168
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. An apparatus comprising: a substrate comprising a plurality of active regions; a plurality of gate stacks disposed over the substrate wherein each gate stack is formed between two adjacent active regions; a first resistor having a first bottom terminal disposed over and in direct contact with a first active region of the plurality of active regions and a first upper terminal coupled to a first connector, wherein the first resistor is formed by a plurality of first vias connected in series, and wherein two adjacent first vias are in direct contact to each other, and wherein a bottom via of the first resistor and the gate stacks are formed in an interlayer dielectric layer; a second resistor having a second bottom terminal disposed over and in direct contact with a second active region of the plurality of active regions and a second upper terminal coupled to the first connector; a switch formed by the first active region, the second active region and a first gate of the plurality of gate stacks, wherein the first active region, the first resistor, the first connector, the second resistor and the second active region form a U-shaped structure and the first gate is surrounded by the U-shaped structure; and a third resistor having a third bottom terminal disposed over and in direct contact with the second active region, wherein the third bottom terminal of the third resistor is coupled to the second bottom terminal of the second resistor.