Patent ID: 6996662
Filing Date: 2006-02-07
Classification: G11C,H04L

Abstract:
1. A system for processing addresses having variable prefix lengths, the system comprising: a plurality of content addressable memory (CAM) blocks, each configured to provide a hit signal and an index signal in response to an applied address; a plurality of programmable storage elements configured to store a plurality of routing values; a configurable switching circuit coupled to receive the hit signals from the CAM blocks and the routing values from the programmable storage elements, wherein the configurable switching circuit routes the hit signals in a first order in response to the routing values; a priority encoder coupled to receive the hit signals routed by the configurable switching circuit, the priority encoder being configured to provide an output hit signal representative of an asserted hit signal having a highest priority in the first order; a first multiplexer configured to route one of the routing values from the programmable storage elements as an index routing value in response to the output hit signal; and a second multiplexer configured to route an index signal from one of the CAM blocks as an output index value in response to the index routing value.