Patent ID: 8569846
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. A method comprising: forming a gate stack over a semiconductor substrate; forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack, wherein the first SiGe region has a first atomic percentage of germanium to germanium and silicon; forming a second SiGe region over the first SiGe region, wherein the second SiGe region has a second atomic percentage of germanium to germanium and silicon, wherein the second atomic percentage is lower than the first atomic percentage, and wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device; forming an n-type source/drain region in the first and the second SiGe regions; and reacting at least a top portion of the second SiGe region with a metal to form a silicide, wherein a bottom portion of the second SiGe region is not reacted with the metal.