Patent ID: 8953605
Filing Date: 2015-02-10
Classification: H04L

Abstract:
1. An apparatus, comprising: a first switch configured to define a first initialization packet having a first header value associated with a first port from a plurality of ports associated with a link aggregation group (LAG), the first switch configured to send the first initialization packet to a second switch via the first port based on the first header value, the first switch configured to receive an acknowledgement packet including the first header value from the second switch in response to the second switch receiving the first initialization packet, the first switch configured to retrieve the first header value from the acknowledgement packet such that the first switch defines, in response to the first switch receiving the acknowledgement packet, a response packet having the first header value, the first switch configured to send the response packet to the second switch via the first port based on the first header value, the first switch configured to define a second initialization packet having a second header value associated with a second port from the plurality of ports, the first switch configured to send the second initialization packet to a third switch via the second port based on the second header value.