Patent ID: 8254160
Filing Date: 2012-08-28
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor substrate; a plurality of word lines extending in a first direction parallel to a surface of the semiconductor substrate and disposed in parallel in a second direction parallel to the surface of the semiconductor substrate and orthogonal to the first direction; a plurality of bit lines extending in the second direction and disposed in parallel in the first direction to intersect the word lines; an insulating film disposed at each of intersections of the word lines and the bit lines; an interlayer insulating film configured to fill a gap between the word lines and a gap between the bit lines; and a resistance varying material formed to extend in the second direction and configured to be electrically connected to the bit lines and to change between a low resistance state and a high resistance state, the word lines, the bit lines and the insulating film configuring a field-effect transistor at each of the intersections of the word lines and the bit lines, the field-effect transistor having one of the word lines as a control electrode and one of the bit lines as a channel region, the field-effect transistor and the resistance varying material configuring a memory cell having the field-effect transistor and the resistance varying material connected in parallel to the field-effect transistor, and each of the bit lines including a first surface opposing the word lines with the insulating film interposed therebetween, and a second surface on an opposite side to the first surface, the resistance varying material being disposed in contact with the second surface and the resistance varying material having a portion thereof in contact with the interlayer insulating film.