Patent ID: 6294437
Filing Date: 2001-09-25
Classification: H01L

Abstract:
A method of manufacturing a crown-shaped dynamic random access memory (DRAM) capacitor, comprising the steps of:providing a substrate having a first silicon oxide layer thereon;forming a silicon nitride layer over the first silicon oxide layer;forming a conductive plug that passes through the silicon nitride layer and the first silicon oxide layer;forming a second silicon oxide layer over the silicon nitride layer and the conductive plug;forming a borophosphosilicate glass layer over the second silicon oxide layer;patterning the borophosphosilicate glass layer and the second silicon oxide layer to form an opening that exposes the conductive plug and a portion of the silicon nitride layer surrounding the plug;forming a doped amorphous silicon layer conformal to interior sidewalls of the opening and exposed borophosphosilicate glass layer;removing the doped amorphous silicon layer above the borophosphosilicate glass layer;using an agent to remove the borophosphosilicate glass layer, wherein the agent remove the borophosphosilicate glass layer faster than the second silicon oxide layer;growing hemispherical silicon grains on a surface of an exposed doped amorphous silicon layer, wherein the hemispherical silicon grains grow under a temperature of between about 550.degree. C. and 560.degree. C. with silane flowing at a rate less than 49 sccm; andremoving the second silicon oxide layer.