Patent ID: 7752490
Filing Date: 2010-07-06
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a plurality of normal memory modules serially connected by a dedicated signal write line and a dedicated signal read line for transferring read/write data; a backup memory module, the backup module not having an access to the read/write data transferred between the normal memory modules during normal operation of the normal memory modules; and a switch circuit connected to each of said normal memory modules and to said backup module, the switch circuit being operable to remove one of said normal memory modules from being serially connected to other normal memory modules without interrupting transmission between said other normal memory modules and to replace said one of said normal memory modules by said backup memory module by isolating said one of said normal memory modules and inserting said backup memory module to serially connect said backup memory module and said normal memory modules excepting said one of said normal memory modules.