Patent ID: 6344391
Filing Date: 2002-02-05
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising steps of:defining an active area on a semiconductor substrate; forming a transistor having a gate and first and second impurity regions on the active area; forming a first insulating interlayer on the semiconductor substrate; forming first and second contact holes exposing the first and the second impurity regions, respectively; forming a storage electrode in the first contact hole and in contact with the first impurity region, and also forming a bit line contact pad in the second contact hole and in contact with the second impurity region; forming a dielectric film on the storage electrode; forming a plate electrode on the dielectric film; forming a second insulating interlayer on the plate electrode and the bit line contact pad; forming a third contact hole in the second insulating interlayer by removing a portion of the second insulating interlayer to expose the bit line contact pad; and forming a bit line on the second insulating interlayer in contact with the bit line contact pad through the third contact hole.