Patent ID: 8421164
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A memory array comprising: a plurality of memory cells, each with a first and a second electrical contact; a plurality of diode devices, each electrically coupled to a second electrical contact of a corresponding memory cell; a semiconductor material base; a plurality of access devices vertically upstanding from said base, spaced from one another in parallel, and extending linearly along said base, each comprising a lower first doped region, an upper second doped region and a first sidewall gate for controlling current flow between the first and second doped regions, wherein said second doped region of each access device is electrically coupled to more than one diode device, and said first doped region is electrically coupled to the semiconductor material base; and a plurality of first conductive lines, each electrically coupled to said first electrical contacts of one or more memory cells so that no two memory cells are electrically coupled to both a same access device and a same conductive line.