Patent ID: 7735038
Filing Date: 2010-06-08
Classification: H03K

Abstract:
1. A design structure embodied in a machine readable storage device used in a design process, the design structure comprising: a clock gated synchronous circuit said clock gated synchronous circuit comprising at least two successive stages of at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage, said synchronous circuit comprising: a means to derive a local clock activation signal from an external clock activation signal which external clock activation signal if high specifies that a corresponding data signal is valid and has to be propagated through the synchronous circuit and if low specifies that a corresponding data signal is invalid and clock gating can be performed, wherein said local clock activation signal changes its value every cycle the external clock activation signal is high; a means to propagate the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit, wherein the means to propagate the data signal and the local clock activation signal from a particular stage to a succeeding stage does not require using a first clock domain for the data register and a second clock domain for the control register, and wherein that the means to derive a local clock activation signal from an external clock activation signal are arranged within a first stage of said clock gated synchronous circuit, wherein said first stage also comprises means to activate said first stage by said external clock activation signal.