Patent ID: 6067331
Filing Date: 2000-05-23
Classification: G06F

Abstract:
A system for performing binary correlation, comprising:a plurality of reference bit registers, each reference bit register operable to store a reference bit of a reference sequence;a plurality of sequentially coupled data bit registers, each data bit register operable to sequentially receive and store each data element of an input data stream;at least one programmable delay unit coupled between sequential data bit registers, each programmable delay unit operable to delay at least one data element of the input data stream between the sequential data bit registers;a plurality of exclusive OR units, each exclusive OR unit coupled to a corresponding reference bit register and a corresponding data bit register, each exclusive OR unit operable to perform an exclusive OR operation between a reference bit stored in the corresponding reference bit register and a data element stored in the corresponding data bit register in order to generate a resultant bit; anda sum unit coupled to the exclusive OR units, the sum unit operable to sum the resultant bits generated by the exclusive OR units.