Patent ID: 9224656
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: forming a first layer of a dual layer hard mask over a gate of a p-channel metal oxide semiconductor (PMOS) transistor, said first layer being silicon nitride formed by a plasma enhanced chemical vapor deposition (PECVD) process with a first chlorinated silane reagent, a hydrocarbon, and ammonia; subsequently, forming a second layer of said dual layer hard mask on said first layer, said second layer being chlorine-containing silicon nitride formed by a PECVD process with a second chlorinated silane reagent and ammonia and free of a hydrocarbon reagent; removing said second layer and said first layer from horizontal surfaces of said integrated circuit by an anisotropic etch, leaving said second layer and said first layer on lateral surfaces of gate offset spacers disposed on lateral surfaces of said gate of said PMOS transistor; subsequently removing material from a substrate of said integrated circuit to form source/drain cavities adjacent to said gate of said PMOS transistor; subsequently forming silicon-germanium (SiGe) source/drain regions in said source/drain cavities by an epitaxial process; subsequently removing said second layer by a first phase of a wet etch process in which an etch rate of said second layer is at least three times faster than an etch rate of said first layer; and subsequently removing said first layer by a second phase of said wet etch process, so that at least a portion of said gate offset spacers remains after said second phase of said wet etch process is completed.