Patent ID: 8984198
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A digital processor, comprising: a data space arbiter comprising more than two fixed bus access priority schemes, wherein each priority scheme assigns a priority level to a plurality of devices for bus access, wherein in a default priority scheme of said plurality of priority schemes a default bus master has a highest priority level and a priority order of secondary bus masters in said default, priority scheme defines a default, priority order, wherein the data space arbiter grants bus access according to a priority scheme selected from said plurality of priority schemes; wherein in each non-default priority scheme a priority level of at least one of said secondary bus masters is raised to have a priority level higher than the priority level of the default bus master while a priority level order of remaining secondary bus masters remains unchanged, wherein in each non-default priority scheme with more than one of said secondary bus masters having a priority level higher than the priority level of the default bus master the default priority order for those secondary bus masters for which the priority level has been raised above the priority level of the default bus master is maintained.