Patent ID: 8713390
Filing Date: 2014-04-29
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a serial instruction register having a serial data input coupled to a test data input, a serial data output, an instruction register control bus output, and a control bus input; B. a serial data register having a serial data input coupled to the test data input, a serial data output, and a control input connected to the instruction register control bus output; C. first multiplexer circuitry coupling the serial data output of the instruction register and the serial data output of the data register to a test data output, and having a control input; D. TAP control circuitry having a clock input coupled to a test clock input, a mode select input coupled to a test mode select input, and a TAP control bus output connected to the control bus input of the instruction register and the control input of the multiplexer circuitry; E. auxiliary circuitry connected to the serial instruction register, the TAP control circuitry, the test data input, the test data output, and an auxiliary input lead; F. second multiplexer circuitry having a first input connected with the test data input, a second input connected with the auxiliary input lead, and an output connected with the serial data input of the serial instruction register and the serial data register; and G. third multiplexer circuitry having a test clock and test mode select input, a test mode select and test clock input, and an output connected to the test clock input of the TAP control circuitry.