Patent ID: 7106620
Filing Date: 2006-09-12
Classification: G11C,H01L

Abstract:
1. A memory cell for use in a memory array, the memory cell comprising: a storage element for storing a logical state of the memory cell; a write circuit operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell; and a read circuit including a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array, the read circuit being configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit; wherein: (i) the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the at least first write bit line during the read operation; and (ii) a strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in at least one of the write circuit and the read circuit.