Patent ID: 8614926
Filing Date: 2013-12-24
Classification: G11C

Abstract:
1. A memory apparatus, comprising: a plurality of first bit columns, for defining a plurality of byte rows, comprises a plurality of first memory units, each first memory unit records a bit, each first memory unit in the same first bit column corresponds to a first column address, and each first memory unit is also respectively associated with one of the plurality of byte rows; a first latching device, coupled to the first bit columns, for latching a selected byte row of the plurality of byte rows; at least one second bit column, for storing a plurality of bits, comprising a plurality of second memory units, each second memory unit records a bit, each second memory unit in the second bit column corresponds to a second column address, and each second memory unit is also respectively associated with one of the plurality of byte rows; a second latching device, coupled to the at least one second bit column, for latching one of the bits associated with the selected byte row; and a switch circuit, coupled to the first latching device and the second latching device, for selectively outputting the selected byte row and the bit associated with the selected byte row; wherein the switch circuit selects one of the first latching device and the second latching device, and outputs an output bit according to a comparison result of an access column address and at least one predetermined column address.