Patent ID: 6414350
Filing Date: 2002-07-02
Classification: H01L,Y10S

Abstract:
A gate structure for an electrically programmable read-only memory (EPROM) cell, comprising:a substrate; a first oxide region disposed on said substrate; a region of conductive material defining a first gate disposed on said first oxide region and extending coextensive therewith, said region of conductive material structure having a major surface disposed opposite to said first oxide region and two spaced-apart minor surfaces extending transversely to said major surface; a side-wall spacer in abutting relationship with one of said minor surfaces; said side-wall spacer having a first portion and a second portion, said first portion formed from a single layer of material, defining a single-wall portion, and said second portion including two layers of differing materials, defining a double-wall portion; an additional oxide region disposed on said major surface; and a conductive region defining a second gate and disposed adjacent to, but spaced apart from, said region of conductive material.