Patent ID: 7260120
Filing Date: 2007-08-21
Classification: H04L

Abstract:
1. An Ethernet switching apparatus using frame multiplexing and demultiplexing, comprising: a plurality of frame demultiplexers for converting at least one 10 gigabit Ethernet frame received in a 10 Gigabit Media Independent Interface (XGMII) format into a plurality of gigabit Ethernet frames of a Gigabit Media Independent Interface (GMII) format, and outputting the gigabit Ethernet frames; a plurality of frame multiplexers for converting a plurality of gigabit Ethernet frames received in a GMII format into at least one 10 gigabit Ethernet frame of a XGMII format, and outputting the 10 gigabit Ethernet frame; and a switch fabric chip set provided with input and output interfaces using a GMII, and connected to the frame demultiplexers and the frame multiplexers in the GMII format, the switch fabric chip set outputting frames through an arbitrary usable one of a plurality of GMII ports connected to a corresponding frame multiplexer if the frames are transmitted to the corresponding frame multiplexer, the GMII connected to the frame multiplexers and the frame demultiplexers being set to support a full duplex mode; wherein the plurality of frame multiplexers and demultiplexers constitute a plurality of corresponding frame multiplexer/demultiplexer pairs; each of the frame demultiplexers within said plurality of multiplexer/demultiplexer pairs comprising, a buffer conversion unit for storing at least one 10 gigabit Ethernet frame received in the XGMII format, converting the 10 gigabit Ethernet frame into gigabit Ethernet frames, and detecting a PAUSE frame, a port analysis control unit for analyzing reception condition and destination addresses of the gigabit Ethernet frames, and analyzing an output port to output the gigabit Ethernet frames, a port selection unit for selecting an output port analyzed by the port analysis control unit and transmitting the gigabit Ethernet frames which are converted by the buffer conversion unit to the selected output port, a source output unit for transmitting source information of the 10 gigabit Ethernet frame, obtained from the port analysis control unit, to other plural frame multiplexer/demultiplexer pairs, and a plurality of output buffers for storing the gigabit Ethernet frames, received from the port selection unit, outputting the gigabit Ethernet frames through the GMII, receiving PAUSE information of the PAUSE frame detected by the buffer conversion unit and processing the PAUSE frame; each of the frame multiplexers within said plurality of multiplexer/demultiplexer pairs comprising, a plurality of input buffers for storing gigabit Ethernet frames received in the GMII format, detecting PAUSE frames and transmitting the PAUSE frames to corresponding output buffers of each of the frame demultiplexers, a selection control unit for receiving source address information of the Ethernet frames, and generating a control signal to select one of the input buffers, a selection conversion unit for sequentially selecting one of the received gigabit Ethernet frames in response to the control signal outputted from the selection control unit, converting the selected gigabit Ethernet frame into at least one 10 gigabit Ethernet frame for the XGMII, outputting the 10 gigabit Ethernet frame in the XGMII format receiving PAUSE information of the PAUSE frames detected by both the buffer conversion unit and the input buffers, and processing corresponding PAUSE frames, and a source input unit for transmitting source information of 10 gigabit Ethernet frames received from other plural frame multiplexer/demultiplexer pairs to both the selection control unit and the port analysis control unit.