Patent ID: 6832340
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A system for correcting errors detected in a memory device, the system comprising:a memory sub-system comprising a plurality of memory cartridges configured to store data words; a memory controller operably coupled to the memory sub-system and configured to control access to the memory sub-system; and a host controller operably coupled to the memory controller and comprising: an arbiter configured to schedule accesses to the memory sub-system; error detection logic configured to detect errors in a data word which has been read from the memory sub-system; a memory engine configured to correct single-bit and multi-bit errors detected in the data word which has been read from the memory sub-system and configured to produce a corrected data word corresponding to the data word in which an error has been detected; scrubbing control logic configured to request a write-back to each memory location in which the error detection logic has detected an error in a data word which has been read from the memory sub-system; and one or more memory buffers configured to store the corrected data word.