Patent ID: 6075931
Filing Date: 2000-06-13
Classification: G06F

Abstract:
A method for accessing data entries in a memory array having n entry access lines and a plurality of data output lines, said method comprising the steps of:pointing to a single entry position in said memory array with an n-bit word line, the entry position selected by setting a single one of the n-bit word lines to a first logic level and all remaining ones of the n-bit word lines to a second logic level;generating a number of additional entry positions in said memory array based upon said entry position indicated by the selected single one of the n-bit word lines, each additional entry position generated by performing a shift operation, starting with the entry position pointed to during said step of pointing;interleaving entries in said memory array such that a first entry position is located proximately to a last entry position;asserting selected ones of said n entry access lines corresponding to said entry position indicated by the selected single one of the n-bit word lines and said additional entry positions generated during said step of generating; andplacing said data entries corresponding to said entry position and said additional entry positions on said plurality of data output lines.