Patent ID: 6531353
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, comprising the steps of:forming a device baffler region in a semiconductor substrate to form an active region and a field region; forming a plurality of logic gates in a logic region; forming a first plurality of DRAM gates in a DRAM cell region and a second plurality of DRAM gates in a DRAM peripheral region; forming insulating film sidewalls on opposing sidewall portions of the plurality of logic gates and the first and second pluralities of DRAM gates; forming source and drain regions in the semiconductor substrate at both sides of the plurality of logic gates and the first and second pluralities of DRAM gates; depositing a first dielectric film on an entire surface of the semiconductor substrate and upon upper surface portions of the first and second pluralities of DRAM gates; removing a first portion of the first dielectric film within the DRAM cell region at a predetermined depth below the upper surface portions of the first plurality of DRAM gates to expose a second portion of the first dielectric film and to remove voids formed between the first plurality of DRAM gates during the depositing of the first dielectric film; forming a second dielectric film upon the second portion of the first dielectric film to cover the upper surface portions of the first plurality of DRAM gates and to remove a step difference between the DRAM cell region and the logic and DRAM peripheral regions; and forming a plug connected with the semiconductor substrate of the DRAM cell region by nenetratina the first dielectric film.