Patent ID: 6304936
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A one-to-many bus bridge, comprising:a system bus interface;first and second I/O bus interfaces;a dynamically-sized logical FIFO system having a write data input, a read data output, and read and write FIFO number inputs;a demultiplexer; andcontrol circuitry coupled to the read and write FIFO number inputs;wherein:the system bus interface routes write data from a system bus to the write data input;the demultiplexer routes read data from the read data output to one of the I/O bus interfaces; andthe write data are enqueued into a first logical FIFO, the read data are dequeued from a second logical FIFO, and the first and second logical FIFOs are selectable independently and simultaneously by the control circuitry.