Patent ID: 6913949
Filing Date: 2005-07-05
Classification: H01L

Abstract:
1. A method of making a semiconductor chip assembly comprising the steps of: (a) stacking a plurality of units each including at least one semiconductor chip having at least one chip select contact and a plurality of other contacts and a circuit panel having a plurality of chip select terminals, a plurality of other terminals, and traces extending on or in the panel connected to said terminals, at least one trace of each said panel being a multi-branched trace associated with a plurality of chip select terminals, each such multi-branched trace including a common section and a plurality of branches connected to different ones of the chip select terminals, the contacts of the at least one chip in each unit being connected to traces of the circuit panel in that unit so that each chip select contact is connected to the common section of a multi-branched trace; (b) selectively interrupting the branches of said multi-branched traces so that the common section of each multi-branched trace is connected to less than all of the chip select terminals associated with such multi-branched trace; and (c) interconnecting terminals of different units to one another to form vertical buses, said selectively interrupting and interconnecting steps being performed so that the chip select terminals of chips in different units are connected to different ones of said vertical buses.