Patent ID: 9035680
Filing Date: 2015-05-19
Classification: H03K,H03M

Abstract:
1. A comparator, comprising a sampling module, a pre-amplifying module, a coupling module, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch, wherein the first field effect transistor and the second field effect transistor both are P-type field effect transistors; the third field effect transistor and the fourth field effect transistor both are N-type field effect transistors; the sampling module is configured to collect a positive input signal, a negative input signal, a positive reference signal, and a negative reference signal; obtain a first differential voltage signal according to the positive input signal and the negative reference signal that are collected; and obtain a second differential voltage signal according to the negative input signal and the positive reference signal that are collected; the pre-amplifying module is configured to amplify the first differential voltage signal to obtain a third differential voltage signal, and amplify the second differential voltage signal to obtain a fourth differential voltage signal; the coupling module is configured to transmit the third differential voltage signal and the fourth differential voltage signal; a source of the first field effect transistor and a source of the second field effect transistor both receive a device working voltage signal, and a source of the third field effect transistor and a source of the fourth field effect transistor both are grounded; a gate of the first field effect transistor receives the third differential voltage signal and is connected to a gate of the third field effect transistor through the first switch, a drain of the first field effect transistor is connected to a gate of the fourth field effect transistor, a gate of the second field effect transistor receives the fourth differential voltage signal and is connected to the gate of the fourth field effect transistor through the second switch, a drain of the second field effect transistor is connected to the gate of the third field effect transistor, a drain of the third field effect transistor is connected to the gate of the fourth field effect transistor, a drain of the fourth field effect transistor is connected to the gate of the third field effect transistor, the gate of the third field effect transistor is connected to a positive output end of the comparator, and the gate of the fourth field effect transistor is connected to a negative output end of the comparator; or, a gate of the first field effect transistor is separately connected to a drain of the second field effect transistor and a positive output end of the comparator, a gate of the second field effect transistor is separately connected to a drain of the first field effect transistor and a negative output end of the comparator, the gate of the first field effect transistor is connected to a gate of the third field effect transistor through the first switch, the gate of the second field effect transistor is connected to a gate of the fourth field effect transistor through the second switch, a drain of the third field effect transistor is connected to the gate of the second field effect transistor, a drain of the fourth field effect transistor is connected to the gate of the first field effect transistor, the gate of the third field effect transistor receives the third differential voltage signal, and the gate of the fourth field effect transistor receives the fourth differential voltage signal; and the first switch and the second switch are closed when a first clock signal is a first level signal, and are open when a second clock signal is a first level signal, wherein when the first clock signal is a first level signal, the second clock signal is a second level signal, and when the second clock signal is a first level signal, the first clock signal is a second level signal.