Patent ID: 9130053
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A nonvolatile memory device, comprising: a pipe connection gate electrode having a bottom in a groove buried in a substrate; one or more pipe channel layers formed within the pipe connection gate electrode; pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode comprises a metal silicide layer formed within the groove, wherein the nonvolatile memory device includes a three-dimensional (3-D) structure, wherein the pipe connection gate electrode comprises a second conductive layer for a gate electrode configured to be in contact with a top of the pipe channel layer, wherein the pipe connection gate electrode comprises the metal silicide layer over the substrate, a first conductive layer over the metal silicide layer, and the second conductive layer over the first conductive layer.