Patent ID: 6207541
Filing Date: 2001-03-27
Classification: H01L,Y10S

Abstract:
A method for making an integrated circuit device, comprising:presenting a substrate;etching trenches in a surface of the substrate;growing a dielectric layer on a surface of the substrate;depositing a gate material layer on a surface of the dielectric layer;forming a patterning layer on a surface of the gate material;exposing the patterning layer so as to form an oxide layer from the patterning layer having a pattern;developing the oxide layer to remove that portion external to the pattern of the patterning layer so as to expose a dielectric layer top surface;forming from the oxide layer a hard mask having sidewalls;etching the gate material layer according to the pattern defined by the hard mask to form a conducting gate having sidewalls that are complementary to the hard mask side walls;forming spacers along the dielectric layer top surface and the sidewalls of the conducting gate, wherein the spacers are made from silicon nitride;removing the hard mask;forming active regions at each trench by removing material from the gate material layer that is external to each dielectric layer top surface and external to the area underneath each gate; andforming at least one source region and one drain region in the substrate between a gate and two active regions.