Patent ID: 6738056
Filing Date: 2004-05-18
Classification: G09G

Abstract:
A system for handling an input video stream comprising:an internal clock generator generating a first clock; a synchronization unit receiving said input video stream having an associated second clock being slower than said first clock, whereby said synchronization unit samples said second clock with said first clock thereby generating a third clock synchronized with said first clock having no signal in case of a data gap; wherein said synchronization unit comprises: a first flip-flop having a set and a reset input and an output, whereby said set input receives said second clock and said reset input receives said first clock; a first AND gate having two inputs and an output, whereby said first input is coupled with said output of said first flip-flop and said second input receives said first clock; a second flip-flop having a set and a reset input and an output, whereby said set input is coupled with the output of said AND gate and said reset input receives said first clock; and a second AND gate having two inputs and an output, whereby said first input is coupled with said output of said second flip-flop and said second input receives the inverted first clock.