Patent ID: 7348854
Filing Date: 2008-03-25
Classification: H03F

Abstract:
1. An automatic gate bias control circuit for single FET device having at least a gate terminal, a source terminal, a drain terminal with a drain-source current path, and a threshold voltage required for operation thereof, said automatic gate bias control circuit comprising: a current sensor connected in series with said drain-source current path having an output signal; an operational amplifier having at least a pair of input nodes and an output node with one of said pair of input nodes receiving said output signal of said current sensor; a reference voltage electrically connected to the other one of said pair of input nodes of said operational amplifier; an operational amplifier voltage output at said output node of said operational amplifier, said operational amplifier voltage output for gate bias control; a resistive path between said output node of said operational amplifier and said gate terminal of said FET device, said resistive path, in turn, further comprising: said voltage integrator, upon threshold voltage of said FET device being exceeded, enabling initiation of current sensing by said current sensor and the corresponding output signal therefrom; and, said reference voltage, said current sensor and said operational amplifier forming a closed loop control for said gate bias voltage.