Patent ID: 6703272
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A method of forming spaced conductive regions associated with a semiconductor construction, comprising:forming a construction which includes: a first electrically conductive material over a semiconductor substrate, and openings extending through the first electrically conductive material and into the semiconductor substrate; and a second electrically conductive material within the openings and over the first electrically conductive material, the second electrically conductive material being different from the first electrically conductive material and being in electrical connection with the first material; and subjecting the construction to anodic dissolution; the first electrically conductive material being electrically connected to a power source during the anodic dissolution; the second electrically conductive material within the openings becoming electrically isolated from the first electrically conductive material during the anodic dissolution and remaining within the openings as the spaced conductive regions after the anodic dissolution.