Patent ID: 6251778
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:(a) providing a semiconductor substrate having a gate electrode and spaced lightly doped source and drain regions, said gate electrode comprising a gate oxide layer and a conducting gate;(b) forming a hard mask layer on said gate electrode;(c) forming spacers on sidewalls of said hard mask layer and said gate electrode, wherein the material used for said spacers is different from the material used for said hard mask layer;(d) implanting ions into said substrate to form highly doped source and drain regions;(e) removing said hard mask layer such that an opening is formed;(f) conformally forming a metal layer on said source and drain regions, said spacers, and said conducting gate;(g) forming an insulating layer on said metal layer and filling said opening, wherein the material of said insulating layer is different from the material of said spacers;(h) polishing to remove an upper portion of said insulating layer, said metal layer and said spacers, whereby said metal layer becomes discontinuous;(i) removing a portion of said metal layer between said spacers and said insulating layer;(j) removing said insulating layer; and(k) converting said metal layer to a silicide layer.