Patent ID: 6136696
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A fabrication method of a semiconductor device, comprising the steps of:(a) forming a structure including a first dielectric layer formed directly on or indirectly over a semiconductor substrate through a layer; a first patterned conductive layer formed on said first dielectric layer; a second patterned dielectric layer formed on said first patterned conductive layer; and said second dielectric layer having approximately a same plan shape as that of said first patterned conductive layer;(b) forming a third dielectric layer on said first dielectric layer;said third dielectric layer serving as an interlayer dielectric layer covering entirely said first patterned conductive layer and covering partially said second patterned dielectric layer;part of said second patterned dielectric layer being exposed from said third dielectric layer;(c) forming a fourth dielectric layer on said third dielectric layer;said fourth dielectric layer covering said part of said second patterned dielectric layer exposed from said third dielectric layer;(d) patterning said fourth dielectric layer to form sidewall spacers for said part of said second patterned dielectric layer exposed from said third dielectric layer;(e) forming a fifth dielectric layer serving as an interlayer dielectric layer covering said part of said second dielectric layer exposed from said third dielectric layer and said fourth patterned dielectric layer;(f) forming a contact hole to penetrate through at least said fifth and third dielectric layers;(g) forming a conductive plug to fill said contact hole;said plug being contacted with a region of said substrate or a conductive layer located between said substrate and said first dielectric layer;said plug being electrically insulated from said first patterned conductive layer by said third dielectric layer itself in said contact hole; and(h) forming a second conductive layer on said fifth dielectric layer;said second conductive layer being contacted with said conductive plug;said second conductive layer being electrically connected with said region of said substrate or said conductive layer located between said substrate and said first dielectric layer through said conductive plug.