Patent ID: 7179691
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. A method of forming a low input capacitance device structure on a P substrate for the purpose of providing four way electrostatic voltage discharge protection to an input/output (I/O) logic circuit line and including electrostatic discharge (ESD) protection to a power bus system, said power bus system comprising relatively-high and relatively-low power sources, the method comprising: creating first and second N+ regions within said P substrate; creating first and second P+ guard rings respectively surrounding said first and second N+ regions; creating an N+ guard ring around said first N+ region and said first P+ guard ring; and creating a electrical conductor system connecting said first N+ region to a pad, said first and second P+ guard rings to said relatively-low power source, and said N+ guard ring and said second N+ region to said relatively-high power source; wherein there is no diode with two terminals respectively connected to said relatively-high power source and said pad, thereby eliminating a parasitic capacitor of said diode and providing a reduced capacitive load for said pad.