Patent ID: 6329871
Filing Date: 2001-12-11
Classification: G05F,G11C

Abstract:
A reference voltage generation circuit comprising:a current mirror circuit including a first enhancement type p-channel MIS transistor having a source thereof connected to a higher voltage power supply line, and a gate thereof connected to a drain thereof, and a second enhancement type p-channel MIS transistor having a source thereof connected to said higher voltage power supply line, and a gate thereof connected to the gate of said first enhancement type p-channel MIS transistor;an enhancement type n-channel MIS transistor having a drain thereof connected to a drain of said second enhancement type p-channel MIS transistor, and a source thereof connected to a lower voltage power supply line; anda source follower circuit having an input end thereof connected to the drain of said n-channel MIS transistor, and an output end thereof connected to a gate of said n-channel MIS transistor;wherein a reference voltage is obtained at the drain of said n-channel MIS transistor.