Patent ID: 7827431
Filing Date: 2010-11-02
Classification: G06F,G11C

Abstract:
1. A memory card accessed by a host apparatus, the memory card comprising: a clock input/output circuit which receives a first clock signal from the host apparatus via a clock line; a data I/O circuit which receives a second clock signal from the host apparatus via a data line in a write timing adjustment mode executed by the memory card, the data I/O circuit transmitting and receiving data to and from the host apparatus via the data line in a data transfer mode; a delay element which, in the write timing adjustment mode, adjusts a phase of the second clock signal output by the data I/O circuit in accordance with the first clock signal so as to receive the data received in the data transfer mode in response to the first clock signal supplied by the clock input/output circuit; and an adjustment value holding circuit which holds an adjustment value for the phase of the second clock signal adjusted by the delay element, wherein in the data transfer mode, the delay element adjusts a phase of the data output by the data I/O circuit in accordance with the adjustment value held in the adjustment value holding circuit.