Patent ID: 7051159
Filing Date: 2006-05-23
Classification: G06F

Abstract:
1. A cache controller structure for managing cache access for a computer system, comprising: (a) a processor having a direction flag, said processor configured to run a repetitive string operation wherein the string operation is configured to sequentially access a targeted memory block for each repetition depending on the state of the direction flag; (b) a cache interfaced with said processor, said cache comprising a plurality of cache lines for accessing system memory data blocks, wherein each cache line comprises a sequential group of data blocks; (c) a system memory in communication with said cache and said processor, the system memory comprising a plurality of sequentially ordered data blocks; and (d) a cache controller logic element in communication with said processor and said cache, said cache controller logic configured to control access to the cache by said processor; wherein said cache controller logic is configured to manipulate the cache lines in said cache responsive to the direction flag and to a position of a targeted memory block within a cache line by: filling a cache line prior to a cache line containing the targeted memory block from said system memory when the targeted memory block is at the beginning of the targeted memory block cache line and the direction flag indicates decrementing access; and filling a cache line after the targeted memory block cache line when the targeted memory block is at the end of the targeted memory block cache line and said direction flag indicates incrementing access; wherein said cache controller logic is configured to not fill the targeted memory block cache line responsive to either a read miss operation or a write miss operation when the targeted memory block is at the beginning of the targeted memory block cache line and the direction flag indicates decrementing access, or when the targeted memory block is at the end of the targeted memory block cache line and said direction flag indicates incrementing access.