Patent ID: 8108593
Filing Date: 2012-01-31
Classification: G06F

Abstract:
1. A memory system comprising: a first storing area as a cache memory included in a volatile semiconductor memory; second and third storing areas included in a nonvolatile semiconductor memory in which data reading and writing is performed by a page unit and data erasing is performed by a physical block unit that is twice or larger natural number times as large as the page unit; a first input buffer included in the nonvolatile semiconductor memory that functions as an input buffer for the third storing area; a second input buffer included in the nonvolatile semiconductor memory that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area; and a controller that allocates a storage area of the nonvolatile semiconductor memory to the second and third storing areas in logical block unit associated with one or more of physical blocks, wherein the controller executes: