Patent ID: 8441323
Filing Date: 2013-05-14
Classification: H03L

Abstract:
1. A signal processing module, comprising: a timing modulator configured to form a first input signal by imparting jitter to a timing of features of the first input signal; a timing comparator with inputs for the first input signal and a second input signal, configured to generate a timing comparator output signal representing relative timing of features of the first input signal with the imparted jitter and the second input signal, the timing comparator comprising an error cancellation stage with an input coupled to the timing modulator, configured to remove a predicted effect of the imparted jitter from the timing comparator output signal; and a jitter detector configured to detect the jitter from the comparator output signal, the jitter detector having an output coupled to the timing comparator to adjust a calibration factor of the timing comparator dependent on the detected jitter.