Patent ID: 8145883
Filing Date: 2012-03-27
Classification: G06F

Abstract:
1. A method of preloading instructions, the method comprising: at an instruction execution unit of a processor executing in a first instruction set operating mode associated with a first instruction set of a plurality of instruction sets, generating an instruction set preload indicator identifying a second instruction set of the plurality of instruction sets, wherein the first instruction set includes at least one instruction that is not included in the second instruction set; executing, in accordance with the first instruction set operating mode, a preload instruction in the first instruction set operative to preload an instruction into an instruction cache, the preload instruction causing pre-loaded instructions to be pre-decoded according to the second instruction set; and while executing in accordance with the first instruction set operating mode, pre-decoding the pre-loaded instruction in the instruction cache according to a second instruction set operating mode associated with the identified second instruction set.