Patent ID: 7716511
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. A method comprising: providing a bus interface coupled to a processing unit and coupled to a memory and at least one peripheral device via a bus, the bus interface comprising a first latch, a second latch, and a first logic, the first latch receiving a first signal and providing a first latched signal, the second latch receiving a second signal and providing a second latched signal, and the first logic receiving the first latched signal from the first latch and providing the second signal to the second latch; determining an operational characteristic representative of an operational speed of the bus interface; adjusting a latency of a first clock signal that controls a timing of the first latch based on the operational characteristic; and adjusting a latency of a second clock signal that controls a timing of the second latch based on the operational characteristic.