Patent ID: 8972472
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. A method for rounding two's complement represented signed numbers away from zero, the method comprising: providing an M-bit two's complement represented signed number to be rounded to an (M−N) bit two's-complement represented signed number; truncating N bits from the right of the M-bit two's complement represented number, thereby to generate an (M−N) bit truncated number and thereby to define a sequence of N truncated bits; if the M-bit two's complement represented signed number is negative and the sequence of N truncated bits comprises a most significant bit of 1 , followed by zeros, outputting the (M−N) bit truncated number; and otherwise, computing and outputting a sum of (a) a number that has an equivalent value of one followed by (N−1) replicas of zero, the one provided by applying a logical operation on the most significant bit of the sequence of truncated bits and (b) the (M−N) bit truncated number; rounding two's complement represented signed numbers away from zero by a circuit that essentially consists of a (N−1) input NOR gate, a first NAND gate, a first AND gate, an adder, a (M−N) input NAND gate, an inverter; wherein the inverter is arranged to receive the most significant bit of the M-bit two's complement represented signed number and to invert it to provide an inverted signal; wherein the a (M−N) input NAND gate is arranged to receive the inverted signal and the second till (M−N−1)'th most significant bits of the M-bit two's complement represented signed number; wherein the (N−1) input NOR gate is arranged to receive (N−2) least significant bits of the M-bit two's complement represented signed number and having an output that is coupled to a first input of a first NAND gate; wherein the first NAND gate has a second input of the first NAND gate arranged to receive the most significant bit of the M-bit two's complement represented signed number; wherein the first AND gate is arranged to receive an output signal of the first NOR gate, a most significant bit of the sequence of truncated bits and an output signal of the (M−N) input NAND gate; wherein the adder is arranged to add an output signal of the first OR gate to the (M−N) bit truncated number.