Patent ID: 8788553
Filing Date: 2014-07-22
Classification: H03L

Abstract:
1. An integrated circuit, comprising: a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein said phase detector outputs an error signal; and a synthesizer control block, coupled to said phase detector, for receiving said error signal to generate a delay select signal, wherein said synthesizer control block comprises an integral adjustment filter and a proportional adjustment filter, wherein said synthesizer control block further comprises a phase deviation filter, wherein said phase deviation filter is coupled to said integral adjustment filter and said proportional adjustment filter, and wherein said integral adjustment filter and said proportional adjustment filter are configured to provide respective outputs for generating said delay select signal that controls an amount of delay to be applied to said oscillator clock signal; wherein said phase deviation filter employs a counter for counting a number of concurrences of said reference clock signal and said oscillator clock signal to determine whether an overflow condition or an underflow condition exists.