Patent ID: 6762972
Filing Date: 2004-07-13
Classification: G11C

Abstract:
A synchronous semiconductor memory device having a 4-bit prefetch mode, comprising:first to fourth memory cell arrays each having memory cells, the memory cells accessed concurrently in response to a signal generated by decoding a plurality of row addresses and a partial column address except a 2-bit column address; a serial-parallel converting means converting a plurality of 4-bit data serially applied during a write operation into a plurality of 4-bit parallel data; a data location control means location-controlling and outputting each of the plurality of the 4-bit parallel data output from the serial-parallel converting means in response to first to fourth decoding signals generated by decoding the 2-bit column address to the first to fourth memory cell arrays, by a sequential method or by an interleaving method, during the write operation; a sense amplifier amplifying a plurality of 4-bit data output from each of the first to fourth memory cell arrays, and location-controlling and outputting the amplified data in response the first to fourth decoding signals, by a sequential method or by an interleaving method, during a read operation; and a parallel-serial converting means converting and outputting a plurality of 4-bit parallel data output from the sense amplifier during a read operation into a plurality of 4-bit serial data.