Patent ID: 6526484
Filing Date: 2003-02-25
Classification: G06F

Abstract:
In a memory controller for transmitting a plurality of commands received from a system processor to an associated memory having a number of logical banks, reordering circuitry for determining a first order in which the commands are transmitted to the associated memory, comprising:a command queue arranged to, store and reorder the plurality of commands received from the system processor, calculate an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank, issue the commands based upon the calculated earliest issue time, remove the issued commands from the command queue using command issue time constraints associated with commands to the same logical bank in memory as well as data bus usage constraints, and calculate a data occurrence time associated with selected ones of the commands wherein the data occurrence time indicates a delta time in clock cycles between issuance of the memory command from the command queue to transfer of corresponding data; wherein the command queue stores first information for each of the plurality of commands.