Patent ID: 6275015
Filing Date: 2001-08-14
Classification: G01P,H03K

Abstract:
A circuit arrangement for reducing a variable pulsed input voltage (Uein) to an operating voltage (U or b) to be delivered to an evaluation circuit in which the input voltage (U ein) can be reduced, the circuit arrangement comprising at least one voltage divider (R1, R3, T1, R4; R7, R8, R2) including a transistor (T1), the at least one voltage divider providing a division factor according to which the input voltage (U ein) can be reduced so as to obtain the operating voltage (Uarb), the at least one voltage divider being regulated in such a way that the division factor (F) can be increased with an increasing input voltage (U ein) and can be decreased with a decreasing input voltage (U ein), wherein the transistor is a field effect transistor having a control input (G) which can be acted upon by a control voltage derived from one of the operating voltage (Uarb) supplied to the evaluation circuit and an intermediate operating voltage (Us).