Patent ID: 8273642
Filing Date: 2012-09-25
Classification: H01L

Abstract:
1. A method for fabricating an NMOS transistor, comprising: providing a silicon substrate having a gate structure thereon; forming a first spacer on a sidewall of the gate structure; forming a lightly doped drain (LDD) region in the silicon substrate at each of two sides of the gate structure; forming a second spacer on the first spacer; and after forming the second spacer, forming a silicon carbide region and a source/drain region in the silicon substrate at each of two sides of gate structure, wherein the silicon carbide region comprises a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region, and a second concentration of crystalline silicon carbide in the second portion is higher than a first concentration of crystalline silicon carbide in the first portion.