Patent ID: 6094735
Filing Date: 2000-07-25
Classification: G01R

Abstract:
An integrated circuit comprising:(a) digital logic, adapted to process data at two or more different processing speeds and configured to receive differential input data at two or more different data rates, wherein, for each data rate, the differential input data has a data prefix at a different common-mode voltage level;(b) at least one comparator, configured to compare the common-mode voltage level of the data prefix to at least one reference voltage to determine the data rate of the differential input data and to provide a comparator code value to the digital logic, wherein the comparator code value identifies the data rate of the differential input data; and(c) a comparator-by-pass circuit, configured between the comparator and the digital logic, configured to receive a by-pass code value and selectively enabled to by-pass the comparator code value and to provide the by-pass code value to the digital logic.