Patent ID: 6148390
Filing Date: 2000-11-14
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of logic blocks, one or more of said logic blocks capable of being enabled or disabled, wherein enabled ones of said logic blocks are powered on and disabled ones of said logic blocks are powered off;a plurality of routing resources, at least one of said routing resources corresponding to one of said logic blocks, wherein routing resources that correspond to said enabled ones of said logic blocks are capable of being configured to provide data paths for said enabled ones of said logic blocks and routing resources that correspond to said disabled ones of said logic blocks are capable of being configured to bypass said disabled ones of said logic blocks; anda programming circuit coupled to said plurality of routing resources, said programming circuit capable of storing configuration data and of providing said configuration data to those of said routing resources corresponding to said enabled ones of said logic blocks;wherein said plurality of logic blocks comprises a plurality of sets of logic blocks, and wherein said programming circuit is coupled to said plurality of logic blocks, and wherein at least one set of said logic blocks further comprises a power supply enable circuit and a first plurality of logic blocks, said power supply enable circuit having a first input terminal coupled to a first voltage terminal, a second input terminal coupled to a second voltage terminal through said first plurality of logic blocks and a third terminal capable of receiving an enable signal, said power supply enable circuit powering on said first plurality of logic blocks when said first plurality of logic blocks are enabled and said power supply enable circuit powering off said first plurality of logic blocks when said first plurality of logic blocks are disabled.