Patent ID: 6622182
Filing Date: 2003-09-16
Classification: G06F

Abstract:
An apparatus for controlling flow of input/output data comprising:a) a processor for transmitting input/output data; b) a graphics unit coupled to receive said input/output data from said processor, said graphics unit comprising an internal input/output buffer; and c) an input/output system coupled between said processor and said graphics unit for transmitting input/output data from said processor to said graphics unit, said input/output system comprising a plurality of coupled communication devices wherein individual communication devices contain buffers and wherein a first upstream communication device comprises control circuitry for controlling flow of said input/output data from said processor to said graphics unit, said control circuitry comprising: a counter circuit maintaining a count value, said count value updated upon input/output data sent to said graphics unit from said processor and said count value updated upon a credit signal received by said first upstream communication device from said graphics unit; and a variable included in said credit signal for updating said count value in accordance with a value assigned to said variable.