Patent ID: 7403586
Filing Date: 2008-07-22
Classification: G09G,G11C

Abstract:
1. A shift register comprising: an input terminal and an output terminals; first and second clock terminals to which first and second clock signals are input, respectively, said first and second clock signals being shifted in phase from each other; first, second and third voltage terminals to which first, second and third voltages are applied, respectively; a first transistor connected between said output terminal and said first clock terminals; a second transistor connected between said output terminal and said first voltage terminal; a first node to which a control electrode of said first transistor is connected; a second node to which a control electrode of said second transistor is connected; and a driving section for applying said first voltage to said first node and a voltage corresponding to said third voltage to said second node in synchronization with said second clock signal, while applying a voltage corresponding to said second voltage to said first node and said first voltage to said second node in response to an input signal input to said input terminal, wherein said driving section includes third and fourth transistors connected in series between said second node and said first voltage terminal, each of said third and fourth transistors having a control electrode connected to said input terminal, and said driving section is configured such that a predetermined voltage other than said first voltage is applied to a third node which is a connection node between said third and fourth transistors in a period during which said third and fourth transistors are in a cutoff state.