Patent ID: 7808857
Filing Date: 2010-10-05
Classification: G11C

Abstract:
1. An analog memory, comprising: a plurality of memory blocks for charging and discharging electric charges corresponding to an input signal, each of the plurality of memory blocks including a plurality of switched capacitor portions each having a capacitive element, a first switching element with an input terminal and a second switching element with an output terminal; a charge line commonly connected to the input terminals of the plurality of the switched capacitor portions of the plurality of memory blocks; a plurality of discharge lines each commonly connected to the output terminals of the switched capacitor portions in each of the plurality of memory blocks; and a buffer circuit disconnectably connected to each of the plurality of memory blocks via the corresponding discharge line and configured to output an output signal, wherein the plurality of memory blocks are configured to sequentially discharge the electric charges to the buffer circuit via the corresponding discharge line, and wherein discharging of one of the plurality of memory blocks is performed in a state in which a subsequent memory block supposed to perform the subsequent discharging is connected to the buffer circuit with the remaining memory blocks disconnected from the butter circuit.