Patent ID: 6107196
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method for forming an integrated circuit comprising:providing a substrate having a node to which electrical connection is to be made, and wherein the node has lateral edges;providing a layer of electrically insulative material outwardly of the substrate and in covering relation relative to the lateral edges of the node;providing a first layer of material outwardly of the electrically insulative layer;providing a second layer of material outwardly of the first layer of material, and wherein the second layer of material is different from the first layer of material;providing a third layer of material outwardly of the second layer of material;forming a contact opening in the electrically insulative, first, second and third layers;removing material of the second layer relative to the first and third layers to provide a discontinuity in the second layer; andproviding an electrically conductive plug in the contact opening, and which substantially completely fills the contact opening and is substantially coplanar with the third layer, the conductive plug having a projection which matingly interlocks with the discontinuity defined by the second layer and wherein the projection extends laterally outwardly beyond the lateral edges of the node, and wherein the projection and the conductive plug are formed from the same material.