Patent ID: 7239556
Filing Date: 2007-07-03
Classification: G11C

Abstract:
1. A memory comprising: a memory cell array including a plurality of memory strings at least one of the memory cell strings including a plurality of nonvolatile memory cells storable at not less than a quaternary level, the plurality of memory cells having first conducting paths and control gates, respectively, the first conducting paths of the plurality of memory cells being connected in series, a first one of the nonvolatile memory cells in the at least one of the plurality of the memory strings having a function other than an external data storing function; a first selection transistor having a second conducting path, and one end of the second conducting path being connected to one end of the series of the first conducting paths; a bit line connected to the other end of the second conducting path of the first selection transistor; a second selection transistor having a third conducting path, and one end of the third conducting path being connected to the other end of the series of the first conducting paths; and a source line connected to the other end of the third conducting path of the second selection transistor, wherein the first one of the nonvolatile memory cells in the at least one of the memory cell strings is adjacent to one of the first selection transistor and the second selection transistor and operates as an n level cell (n is an integer not less than 2), while another of the plurality of nonvolatile memories in the one of the memory cell strings operates as an n+2 or greater level cell.