Patent ID: 6170053
Filing Date: 2001-01-02
Classification: G06F

Abstract:
A microprocessor, comprising: an execution stage comprising a plurality of execution units; an instruction memory for storing instructions; and circuitry for retrieving instructions from the instruction memory, said circuitry for retrieving instructions operating to retrieve a second instruction simultaneously with the execution of a first instruction by one of said plurality of execution units, said circuitry for retrieving instructions comprising: a branch target memory for storing a plurality of information fields corresponding to a branch instruction, wherein said plurality of information fields comprise: a target instruction address; a prediction field indicating whether or not program flow should pass to said target instruction address; and an accuracy measure indicating accuracy of past ones of said prediction field; wherein said circuitry for retrieving instructions retrieves, as a next instruction to follow said branch instruction, an instruction corresponding to said target instruction address in response to a function responsive to said accuracy measure exceeding a predetermined threshold and said prediction field indicating program flow should pass to said target instruction address; and wherein said circuitry for retrieving instructions retrieves, in response to said function responsive to said accuracy measure not exceeding a predetermined threshold, a first group of instructions, wherein said first group of instructions is sequentially arranged after said branching branch instruction and includes an instruction corresponding to said target instruction address.