Patent ID: 8879323
Filing Date: 2014-11-04
Classification: G11C

Abstract:
1. A multiple-time programmable interconnection matrix, comprising: a plurality of non-volatile memory (NVM) cells organized in rows and columns, each NVM cell having a source, a drain, a floating gate, a control gate and a channel region, the control gates of the NVM cells in a row forming a corresponding control gate line, the drains of the NVM cells in a column forming a corresponding bit line, the NVM cells in a row being arranged in cell pairs, such that each of the cell pairs share a common source and are connected to two adjacent bit lines, the common sources of the NVM cells in a row forming a corresponding source line, the NVM cells being configured into a plurality of erased cells and a plurality of programmed cells after each programming cycle; a plurality of first switches and second switches respectively disposed at first terminals and second terminals of the bit lines; and a plurality of third switches and fourth switches respectively disposed at first terminals and second terminals of the source lines; wherein conductivity states of the erased cells and the programmed cells depend on a conductivity type of the NVM cells when the control gate lines are biased.