Patent ID: 8432409
Filing Date: 2013-04-30
Classification: G06T,G09G

Abstract:
1. A method comprising: receiving, at an execution pipeline of a processing system, a block data transfer instruction; determining, in response to receiving the block data transfer instruction, a first value representative of a source memory location of a source storage component, a second value representative of a destination memory location of a destination storage component, a third value representative of a number of lines of a data block to be transferred from the source storage component to the destination storage component, a fourth value representative of a number of bytes to be transferred per line of the data block, a fifth value representative of a byte width of the source storage component and a sixth value representative of a byte width of the destination storage component; and executing, at the execution pipeline, the block data transfer instruction to transfer the data block from the source storage component to the destination storage component based on the first, second, third, fourth, fifth and sixth values.