Patent ID: 9030836
Filing Date: 2015-05-12
Classification: G06F,H05K

Abstract:
1. A memory apparatus comprising: a printed circuit board (PCB) having embedded thereon a controller; first and second connector pads arranged on edges of top and bottom surfaces of the PCB; a via hole arranged between the controller and the first and second connector pads; a first passive device pad arranged between the via hole and the first connector pads; a second passive device pad arranged between the via hole and the second connector pads; and a passive device coupled to only one of the first passive device pad or the second passive device pad, wherein, when the first connector pads and the second connector pads are asymmetrically disposed on the top and bottom surfaces of the PCB, the first and second passive device pads are formed at a point intermediate between the first connector pads and the second connector pads.