Patent ID: 9213835
Filing Date: 2015-12-15
Classification: G06F

Abstract:
1. A secure cryptographic circuit arrangement, comprising: a cryptographic processing block having a plurality of signal paths, each of the signal paths coupled to a respective input of the cryptographic processing block and each of the signal paths including a respective adjustable delay circuit, each adjustable delay circuit coupled to a respective one of the inputs of the cryptographic processing block; a spreading sequence generator configured to output a sequence of pseudo-random numbers; a delay control circuit having an input coupled to an output of the spreading sequence number generator and having a plurality of outputs coupled to delay adjustment inputs of the adjustable delay circuits, respectively; and wherein the delay control circuit is configured to select ones of the adjustable delay circuits to which the respective delay values are input based on one or more bits of each pseudo-random number, and the delay control circuit is configured to adjust respective delay values of the selected ones of the adjustable delay circuits based on respective subsets of bits of each pseudo-random number.