Patent ID: 6803302
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of forming a semiconductor device, comprising:forming a first interconnect level over a semiconductor substrate; forming an uppermost interconnect level that includes an interconnect portion and a bond pad over the first interconnect level, wherein: the interconnect portion contacts the first interconnect level by way of vias through an interlevel dielectric layer, and wherein all vias interconnecting the interconect portion and the first interconnect level are positioned outside regions directly below the bond pad; forming a passivation layer over the uppermost interconnect level; removing portions of the passivation layer, wherein removing portions of the passivation layer exposes portions of the bond pad and forms a plurality of support structures overlying the uppermost surface of the bond pad; and forming a conductive capping layer overlying the plurality of support structures, wherein the conductive capping layer electrically contacts the bond pad; wherein the plurality of support structures are interconnected with unremoved portions of the passivation layer.