Patent ID: 6477599
Filing Date: 2002-11-05
Classification: G06F

Abstract:
A data processing system, comprising:microcomputer; memory; an input/output device; and at least one bus to which said microcomputer, said memory and said input/output device are connected; said microcomputer including: a central processing unit, direct memory access control means having a plurality of data transfer channels, for performing data transfer control based on data transfer control information supplied from said central processing unit or the outside through said bus, and a bus state controller for arbitrating competition between bus right requests supplied from said central processing unit, said direct memory access control means and said input/output device and controlling a bus cycle for said bus, said input/output device acquiring a bus tight to perform a data transfer request to said direct memory access control means and outputting a data transfer set command for controlling the operation of said direct memory access control means to said bus, and performing the operation of inputting data to or outputting data from said bus in synchronism with a response issued from said microcomputer as a data transfer source for the control of data transfer by said direct memory access control means.