Patent ID: 6650700
Filing Date: 2003-11-18
Classification: H04L

Abstract:
A dual path equalizer for processing blocks of data comprising:a first pre-processor, wherein the first pre-processor applies coefficients b1 to a received signal; a first finite filter, wherein the first finite filter applies coefficients a1 to an output of the first pre-processor in order to substantially eliminate a ghost from the received signal; a first post-processor, wherein the first post-processor applies coefficients c1 to an output of the first finite filter; a second pre-processor, wherein the second pre-processor applies coefficients b2 to the received signal, and wherein the coefficients b2 are substantially the time reverse of the coefficients b1; a second finite filter, wherein the second finite filter applies coefficients a2 to an output of the second pre-processor in order to substantially eliminate a ghost from the received signal, and wherein the coefficients a2 are substantially the time reverse of the coefficients a1; a second post-processor, wherein the second pre-processor applies coefficients c2 to an output of the second finite filter, and wherein the coefficients c2 are substantially the time reverse of the coefficients c1; and, an adder arranged to add outputs from the first and second post-processors.