Patent ID: 6891757
Filing Date: 2005-05-10
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array in which electrically programmable memory cells are arranged in a matrix form, the memory cells being connected to word lines; a first voltage generating circuit which generates a first voltage, a second voltage generating circuit which generates a second voltage using the first voltage, the second voltage being lower than the first voltage; a third voltage generating circuit which generates a third voltage; a word line selecting circuit which selects at least one of the word lines of the memory cells in accordance with an inputted address; a word line voltage supplying circuit which supplies the second voltage to the selected word line and supplies the third voltage to the non-selected word line through the word line selecting circuit; and a transfer voltage supplying circuit which supplies the first voltage to the word line selecting circuit and stops supplying the first voltage so as to be in a floating state before transferring the second voltage from the word supplying circuit to the selected word line, in an operation in which the second voltage is supplied to the selected word line after the first voltage is supplied to the word line selecting circuit.