Patent ID: 6493855
Filing Date: 2002-12-10
Classification: G06F

Abstract:
A method of implementing a flexible memory architecture within an integrated circuit, said method comprising:establishing at least 20 independent sub-arrays of memory within an integrated circuit, wherein each of said independent sub-arrays of memory includes its own decode circuitry for decoding a requested address and its own I/O circuitry; establishing at least one of said independent sub-arrays of memory as a redundant sub-array of memory, wherein said at least one redundant sub-array of memory is usable to effectively repair a defect within at least one other of said independent sub-arrays of memory; and distributing said independent sub-arrays around a core of said integrated circuit that comprises an irregularly shaped boundary, wherein said independent sub-arrays are distributed about said irregularly shaped boundary of said core in a manner that manages white space present on said integrated circuit in a desired manner.