Patent ID: 7444600
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. A method for performing noise analysis of a circuit, comprising: forming a set of noise abstracts for a set of blocks of logic of a circuit, each of the set of noise abstracts corresponding to a block of logic in the set of blocks of logic, wherein each of the set of noise abstracts for the set of blocks of logic of the circuit is formed by performing a transistor level analysis of the block of logic corresponding to the noise abstract, each block of logic in the set of blocks of logic comprises a set of input pins, a set of output pins and a set of bi-directional pins and each of the set of noise abstracts for the set of blocks of logic comprises a noise tolerance for each of the set of input-pins of the corresponding block of logic, a noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and a noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an input of internal logic of the corresponding block of logic and the noise tolerance for each of the set of input-pins of the corresponding block of logic, the noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and the noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an input of internal logic of the corresponding block of logic is a single voltage independent of noise pulse width; and performing a noise analysis of the circuit utilizing the set of noise abstracts.