Patent ID: 6356987
Filing Date: 2002-03-12
Classification: G06F

Abstract:
In a computing device having a first memory and a second memory, the first and second memories coupled to a common data bus, a method of accessing the first and second memories comprising the steps of:associating a first wait state value to the first memory; associating a second wait state value to the second memory; carrying out a first I/O operation on a selected one of the memories; making a determination as to whether to place the computing device in a wait state, said determination being based on a sequence of I/O operations being performed on the memories; placing the computing device in a wait state for a period of time proportional to the wait state value associated with the selected memory when the determination is affirmative; refraining from placing the computing device in a wait state when the determination is negative; and performing a next I/O operation with the other of the first and second memories.