Patent ID: 9214124
Filing Date: 2015-12-15
Classification: G09G

Abstract:
1. A row driving circuit for an array substrate, comprising array substrate row driving units with multi-stage connections, wherein an n-th stage array substrate row driving unit in the row driving circuit for the array substrate comprises: an (n−3)-th stage signal input terminal, an (n−2)-th stage signal input terminal, an (n+2)-th stage signal input terminal, a first output terminal, a second output terminal, a low level input terminal, and a high frequency clock signal input terminal, wherein n is a positive integer greater than 3; wherein the (n−3)-th stage signal input terminal is connected to the second output terminal of an (n−3)-th stage array substrate row driving unit, and the (n−2)-th stage signal input terminal is connected to the first output terminal of an (n−2)-th stage array substrate row driving unit, and the (n+2)-th signal input terminal is connected to the first output terminal of an (n+2)-th stage array substrate row driving unit, and the second output terminal is connected to an (n−3)-th stage signal input terminal of an (n+3)-th stage array substrate row driving unit, and the first output terminal is connected to an (n−2)-th stage signal input terminal of a (n+2)-th stage array substrate row driving unit and an (n+2)-th stage signal input terminal of an (n−2) stage array substrate row driving unit for providing a scanning signal to an n-th stage scanning line of a display area; wherein the n-th stage array substrate row driving unit further comprises: a pull-up controlling unit including a first thin film transistor, wherein the first thin film transistor comprises a first gate electrode, a first source electrode, and a first drain electrode, and the first gate electrode is connected to the (n−3)-th stage signal input terminal, and the first source electrode is connected to the (n−2)-th stage signal input terminal, the first drain electrode is connected to a pull-down controlling unit, and the first drain electrode, a pull-down unit, and a pull-up unit are connected to the second output terminal, and a peak voltage of the (n−3)-th stage signal input terminal is twice a peak voltage of the (n−2)-th stage signal input terminal for pulling up an electric potential of the second output terminal; wherein the pull-up unit includes a capacitor and a second thin film transistor, and the second thin film transistor comprises a second gate electrode, a second source electrode, and a second drain electrode, and the capacitor comprises a first electrode plate and a second electrode plate, and the second gate electrode is connected to the pull-up controlling unit and the first electrode plate of the capacitor through the second output terminal, the second source electrode is connected to the high frequency clock signal input terminal, and the second drain electrode is connected to the first output terminal for charging a signal of the first output terminal, and thereby the second output terminal has a higher electric potential; wherein the low level input terminal, the pull-up controlling unit, and the pull-up unit are connected to the pull-down controlling unit for maintaining a low electric potential of the second output terminal and the first output terminal when the signal of the first output terminal is non-chargeable; wherein the (n+2)-th stage signal input terminal, the low level input terminal, and the pull-down controlling unit are connected to the pull-down unit, and the pull-down unit, the pull-up unit, and the pull-up controlling unit are connected to the second output terminal for pulling down an electric potential of the second output terminal.