Patent ID: 7443193
Filing Date: 2008-10-28
Classification: H03H,H03K,H04L

Abstract:
1. A parallel on-chip termination (OCT) calibration circuit comprising: first transistors coupled in parallel between a first terminal and a supply voltage; second transistors coupled in parallel between the first terminal and ground; and a low voltage; a feedback loop circuit coupled to the first terminal that generates first calibration codes to control conductive states of the first transistors and second calibration codes to control conductive states of the second transistors, wherein the parallel OCT calibration circuit selects one of the first calibration codes and one of the second calibration codes to control a parallel on-chip termination impedance of third and fourth transistors at a pin; fifth transistors coupled in parallel between a second terminal and the supply voltage, wherein the first calibration codes control conductive states of the fifth transistors; and sixth transistors coupled in parallel between the second terminal and a low voltage, wherein the second calibration codes control conductive states of the sixth transistors.