Patent ID: 8860191
Filing Date: 2014-10-14
Classification: H01L,H01P,Y10T

Abstract:
1. A structure comprising: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the plurality of wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric structure extending co-planar with the second portion and having a length that is substantially the same as the second portion, wherein the first signal line has a length that is different than a length of the second signal line; and, the second portion and the secondary dielectric structure are arranged to provide the same phase delay and same characteristic impedance for the first and second signal lines.