Patent ID: 6728121
Filing Date: 2004-04-27
Classification: H02M,Y02B,Y02P

Abstract:
A method for reducing the harmonics contents of an input current drawn from a power line into an electrical system without sensing an input voltage, the method comprising:a) providing an active power factor correction controller with a switch module having a main switch and a timing device that includes a ramp capacitor, wherein said main switch has an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, wherein said timing device is selected from the group consisting from analog timing devices and digital timing devices, b) maintaining a linear relationship between said off-duty cycle duration and the input current by using said timing device, wherein said maintaining includes making said linear relationship dependent on the deviation of an output voltage from a pre-determined reference voltage, and wherein said maintaining step further includes: i. charging and discharging said ramp capacitor, said charging associated with a charge time and said discharging associated with a discharge time; ii. providing linearization means that include a logic gate added to said controller; and iii. using said linearization means to include said discharge time of said ramp capacitor in said on-time of said main switch, and c) providing a feedback to said controller using an output circuit referenced to said output voltage.