Patent ID: 6665348
Filing Date: 2003-12-16
Classification: H04B,H04L

Abstract:
A structure for trellis coding and decoding, of extended memory Bit Rate Agile (BRA), Modulation-Demodulation (Modem) Format Selectable (MFS) and Code Selectable (CS) input port for receiving input data comprising:a trellis encoder; a BRA, MFS and CS splitter having an input coupled to said input port, and serving to split said input data into baseband signal streams; a BRA, MFS and CS baseband signal processing network for receiving said baseband signal streams and providing BRA, MFS and CS in-phase (I) and quadrature (Q) phase baseband signals; means for baseband signal processing for receiving said I and Q phase baseband signals and providing changeable amounts of cross-correlation; means for selectively reducing a cross-correlating factor down to zero between Time Constrained Signal (TCS) response processors combined with TCS and Long Response (LR) processors; means for modulating the cross-correlated signal; means for transmitting the modulated signal; a BRA and MFS quadrature demodulator; a receiver port for connection of the received modulated signal to the BRA and MFS demodulator; and a Mis-Matched (MM) BRA and MFS demodulator filter set coupled to the receiver port for a BRA and MFS demodulation, wherein the demodulator filter set is mis-matched to a BRA and MFS filter set of a modulator.