Patent ID: 8742510
Filing Date: 2014-06-03
Classification: H01L

Abstract:
1. A device, comprising: a plurality of gate structures positioned above a semiconducting substrate, each of said plurality of gate structures comprising a gate electrode; a metal silicide region in a source/drain region formed in said semiconducting substrate, said metal silicide region extending laterally so as to contact a first sidewall spacer positioned proximate a first one of said plurality of gate structures and a second sidewall spacer positioned proximate a second one of said plurality of gate structures; and a conductive contact positioned between said plurality of gate structures, said conductive contact comprising a lower portion that conductively contacts said metal silicide region and an upper portion positioned above said lower portion, wherein said lower portion is laterally wider than said upper portion and extends laterally so as to contact each of said first and second sidewall spacers and at least part of said upper portion is positioned between said first and second sidewall spacers and below an upper surface of said gate electrode of each of said first and second gate structures.