Patent ID: 6037216
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating a dynamic random access memory, (DRAM), device on a semiconductor substrate, comprising the steps of:forming a first level of polycide gate structures, in a first region of said semiconductor substrates, with the polycide gate structures capped with a silicon nitride layer, with silicon nitride spacers on the sides of the polycide gate structures, and with source/drain regions, in said semiconductor substrate, located between polycide gate structures;forming a polycide gate structure, in a second region of said semiconductor substrate, capped with a silicon nitride layer, and with silicon nitride spacers on the sides of said polycide gate structure, with a opening in silicon nitride layer, exposing a portion of the top surface of a metal silicide layer, of said polycide gate structure, in said second region of said semiconductor substrate;forming a first level of self-aligned contact, (SAC), openings, in a first silicon oxide layer, in said first region of said semiconductor substrate, exposing said source/drain, located between polycide gate structures, and exposing a portion of the capping silicon nitride layer, located on said first level of polycide gate structures;forming a contact hole in said first silicon oxide layer, exposing a first portion of said semiconductor substrate, in a second region of said semiconductor substrate;forming SAC structures, in said first level of SAC openings;forming a conductive plug structure in said contact hole, in said first silicon oxide layer, located in second region of said semiconductor substrate;forming a second level of polycide structures, capped with a silicon nitride layer, and with silicon nitride spacers on the sides of said level of polycide structures, on a second silicon oxide layer, with a first polycide gate structure, of said second level of polycide structures, connected to an underlying SAC structure that is used as a bit line contact structure, located in said first region of said semiconductor substrate, via a first opening in said second silicon oxide layer, and with a second polycide gate structure, of said second level of polycide structures, connected to said conductive plug structure, in said second region of said semiconductor substrate, via a second opening in said second silicon oxide layer;forming a silicon nitride masking pattern, on a third silicon oxide layer, with a first set of openings, in said silicon nitride masking pattern, located in said first region of said semiconductor substrate, while a second set of openings, in said silicon nitride masking pattern, is located in said second region of said semiconductor substrate;depositing a fourth silicon oxide layer;forming a second level of SAC openings, in said first region of said semiconductor substrate, with said second level of SAC openings created in said fourth silicon oxide layer, using an opening in a overlying photoresist shape as a mask, and in said third silicon oxide layer, and in said second silicon oxide layer, exposed in said first set of openings in said silicon nitride masking pattern, and with said second level of SAC openings located between polycide structures, of said second level of polycide structures, exposing the top surface of SAC structures, in said first level of SAC openings, to be used as storage node SAC structures;forming a lower interconnect opening, in said second region of said semiconductor substrate, with said lower interconnect opening created in said fourth silicon oxide layer, using an opening in an overlying photoresist shape as a mask, and in said third silicon oxide layer, in said second silicon oxide layer, and in said first silicon oxide layer, using said second set of openings in said silicon nitride masking pattern as a mask, exposing a second portion of said semiconductor substrate, in said second region of said semiconductor substrate, and exposing the metal silicide layer, of said polycide gate structure, located in said second region of said semiconductor substrate;forming storage node capacitor structures, in said second level of SAC openings;forming a lower interconnect structure, in said lower interconnect opening;selectively removing said fourth silicon oxide layer, from the top surface of said silicon nitride masking pattern;forming a capacitor structure, comprised of a cell plate structure, a capacitor dielectric layer, and said storage node capacitor structures, in said first region of said semiconductor substrate;forming metal plug structures, in a openings in a fifth silicon oxide layer, with a first metal plug structure contacting said capacitor structure, with a second metal plug contacting said lower interconnect structure, and with a third metal plug connected to said conductive plug structure, via said second polycide structure, of said second level of polycide structures; andforming upper interconnect structures, with a first upper interconnect structure connected to said capacitor structure, via said first metal plug structure, with a second upper interconnect structure connected to said lower interconnect structure, via said second metal plug structure, and with said third upper interconnect structure connected to said second polycide structure, of said second level of polycide structures, via a third metal plug structure.