Patent ID: 6034965
Filing Date: 2000-03-07
Classification: G06F,H04L

Abstract:
A communications circuit comprising:a first content-addressable memory block having:an address input,a plurality of physical locations each of which comprises an address field responsive to the address input and an output field, andan output responsive to the output fields,a second content-addressable memory block having:an address input,a plurality of physical locations each of which comprises an address field responsive to the address input, and an output field, andan output responsive to the output fields, anda first data memory having an address input responsive to the output of the first content addressable memory block and to the output of the second content-addressable memory block, anda time division multiplexed communications interface circuitry operatively connected to the content-addressable memory blocks for switching time division multiplexed time slot data from a first plurality of data streams onto a second plurality of data streams using the content-addressable memory blocks,wherein the first content-addressable memory block and the second content-addressable memory blocks are constructed and arranged to substantially simultaneously receive and process a same input address.