Patent ID: 6670640
Filing Date: 2003-12-30
Classification: C30B,G02F,H01L

Abstract:
A display system comprising:a CPU formed over a substrate; a correction memory connected to said CPU, formed over said substrate; a memory connected to said CPU, formed over said substrate; an X-Y divider circuit connected to said CPU, formed over said substrate; an X-decoder/driver connected to said X-Y divider circuit, formed over said substrate; a Y-decoder/driver connected to said X-Y divider circuit, formed over said substrate; an active matrix circuit connected to each of said X-decoder/driver and said Y-decoder/driver, formed over said substrate; wherein each of said X-Y divider circuit, said X-decoder/driver, said Y-decoder/driver is constituted by at least one thin film transistor, said thin film transistor comprising: a crystalline semiconductor film on an insulating surface, a channel region formed in said crystalline semiconductor film; and source and drain regions formed in said crystalline semiconductor film, wherein at least said channel region is substantially free of grain boundaries.