Patent ID: 6927121
Filing Date: 2005-08-09
Classification: H01L

Abstract:
1. A method for manufacturing a ferroelectric random access memory (FeRAM) capacitor, the method comprising the steps of: a) preparing an active matrix obtained by a predetermined process, the active matrix including a semiconductor substrate, a transistor, a bit line, a first inter layer dielectric (ILD), a second ILD and a storage node; b) forming a first bottom electrode on the second ILD and the storage node; c) forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; d) planarizing the third ILD until a top face and upper sidewalls of the first bottom electrode are exposed; e) forming a second bottom electrode on the top face of the first bottom electrode, the first bottom electrode and second bottom electrode together being a composite bottom electrode; f) forming conductive oxides on exposed sidewalls of the first bottom electrode by carrying out an oxidation process; g) forming a dielectric layer on exposed surfaces of the composite bottom electrode and the third ILD; and h) forming a top electrode on the dielectric layer.