Patent ID: 6906331
Filing Date: 2005-06-14
Classification: H01L

Abstract:
1. An array substrate for X-ray detector, comprising: a substrate having a switching region and a pixel region; a gate line on a substrate, the gate line having a gate linking line and a gate pad at the end thereof; a gate insulation layer on said gate line; a data line on said gate insulation layer, the data line perpendicularly crossing said gate line to define the pixel region and having a data linking line and a data pad at the end thereof; a thin film transistor in the switching region near the crossing of the said gate and data lines, the thin film transistor including a gate electrode, an active layer, a source electrode, a drain electrode and said gate insulation layer; a ground line crossing said pixel region parallel with the data line and having a ground linking line and a ground pad at the end thereof; a first passivation layer formed of a silicon insulator, the first passivation layer covering said thin film transistor and having a first drain contact hole that exposes the drain electrode and a first ground line contact hole that exposes the ground line; a gate pad electrode formed on the first passivation layer, the gate pad electrode contacting the gate pad through a first gate pad contact hole that penetrates both the gate insulation layer and the first passivation layer; a data pad electrode formed on the first passivation layer, the data pad electrodes contacting the data pad though a first data pad contact hole that penetrates the first passivation layer; a ground pad electrode formed on the first passivation layer, the ground pad electrode contacting the ground pad though a first ground pad contact hole that penetrates the first passivation layer; a second passivation layer formed of an organic material on the first passivation layer, the second passivation layer covering the gate pad electrode, the data pad electrode and the ground pad electrode, and having a second drain contact hole that exposes the drain electrode and a second ground line contact hole that exposes the ground line; a first capacitor electrode on the second passivation layer, the first capacitor electrode contacting the ground line through said first and second ground line contact holes; an auxiliary drain electrode on the second passivation layer, the auxiliary drain electrode contacting the drain electrode through said first and second drain contact holes; a third passivation layer on the second passivation layer, the third passivation layer covering the auxiliary drain electrode and the first capacitor electrode, and having an auxiliary drain contact hole that exposes said auxiliary drain electrode; and a second capacitor electrode on the third passivation layer, the second capacitor electrode electrically contacting the drain electrode and overlapping the first capacitor electrode thereby forming a storage capacitor with the first capacitor electrode and the third passivation layer; wherein the second and third passivation layers have a second gate pad contact hole that exposes the gate pad electrode, a second data pad contact hole that exposes the data pad electrode, and a ground pad contact hole that exposes the ground pad electrode.