Patent ID: 6791166
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A semiconductor die package, comprising:an encapsulant body having opposed top and bottom surfaces and side surfaces vertically between the top and bottom surfaces; inner leads each having an inner first and an outer second end, the first and second ends being within the encapsulant body; outer leads each having an inner portion within the encapsulant body and an outer portion extending outside of the encapsulant body; a die paddle within the encapsulant body, wherein the inner leads and the die paddle are lower in the encapsulant body than the encapsulated inner portions of the outer leads, a bottom surface portion of each of the inner leads and the die paddle is exposed at the bottom surface of the encapsulant body, and the unencapsulated outer portion of each of the outer leads includes a bottom surface portion that is approximately coplanar with the bottom surface of the encapsulant body and the exposed bottom surface portions of the die paddle and inner leads; and a semiconductor die within the encapsulant body, mounted on the inner leads and the die paddle, and electrically coupled to the inner leads and to the inner portion of the outer leads.