Patent ID: 9197130
Filing Date: 2015-11-24
Classification: H02M

Abstract:
1. A regulator device comprising: a power input terminal; a power output terminal; a plurality of regulators each including an operating FET and a monitoring FET to be driven together with the operating FET, the plurality of regulators being arranged in parallel between the power input terminal and the power output terminal; and a controller configured to drive the operating FET and the monitoring FET included in one of the plurality of regulators, the controller being configured to stop driving the operating FET and the monitoring FET included in the one of the plurality of regulators, and being configured to drive the operating FET and the monitoring FET included in another one of the plurality of regulators, in response to the controller determining that the monitoring FET included in the one of the plurality of regulators has degraded by measuring an on-resistance of the monitoring FET included in the one of the plurality of regulators.