Patent ID: 9136283
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A thin film transistor array panel, comprising: a first gate line and a second gate line which extend in a row direction, are between two adjacent pixel rows, and are adjacent to each other; a singular data line which extends in a column direction and transfers a data voltage; a first pixel electrode and a second pixel electrode which are connected to the singular data line and are adjacent to each other in the row direction; a first thin film transistor which is connected to the first pixel electrode and the singular data line, and includes a first source electrode and a first drain electrode; a second thin film transistor which is connected to the second pixel electrode and the singular data line, and includes a second source electrode and a second drain electrode; and a first source connection portion which connects the second source electrode to the singular data line, wherein relative positions of the first source electrode and the first drain electrode are the same as relative positions of the second source electrode and the second drain electrode, and the first pixel electrode and the second pixel electrode are at different sides with respect to the singular data line in the plan view.