Patent ID: 6367071
Filing Date: 2002-04-02
Classification: G06F

Abstract:
A method of processing code in a processing system in accordance with a compiler, the method comprising the steps of:generating a first set of code; and applying optimizations to the first set of code so as to generate a second set of code configured to operate with a zero overhead loop mechanism of a processor of the system, wherein the optimizations are operative to provide: (i) an increase in the number of loops of the first set of code that can be accommodated in the zero overhead loop mechanism via one or more of conditional instructions, loop splitting and function inlining; (ii) a reduction in the overhead associated with one or more loops in the zero overhead loop mechanism via one or more of loop collapsing and loop interchange; and (iii) elimination of a redundant loading of the zero overhead loop mechanism via one or more of data flow analysis and loop peeling.