Patent ID: 7859012
Filing Date: 2010-12-28
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a supporting substrate; dielectric defining a layer on the supporting substrate; semiconductor material disposed as a layer on the layer of dielectric; and a thyristor of a memory cell defined in at least a portion of the semiconductor material layered over the dielectric; a capacitor electrode disposed in insulated relationship over and capacitively coupled to a base region of the thyristor; and a wordline coupled to the capacitor electrode; wherein the supporting substrate on the side of the dielectric opposite the thyristor for the memory cell comprises semiconductor material defined at least in part by a portion against the dielectric, in which the portion against the dielectric has a density of dopants of at least 10 wherein the dielectric between the supporting substrate and the thyristor is sufficiently thin to enable back-gate biasing effects to a side of the semiconductor material of the thyristor that is opposite the capacitor electrode across the dielectric when a voltage bias of magnitude up to 5 volts is applied to the supporting substrate.