Patent ID: 6507592
Filing Date: 2003-01-14
Classification: H04J,H04L,H04N

Abstract:
An apparatus for two-way communication of data in a time division multiplexed system, and comprisingclock generator means for generating first and second clock signals, processor means for receiving the first clock signal and processing received data packets, an interface unit for receiving and intermediately storing incoming data packets from a head-end system and for intermediately storing and transmitting outgoing data packets to the head-end system, the interface unit comprising: time base means for receiving the second clock signal and generating a current time stamp value, input buffer means for receiving data of the incoming data packets, the input buffer means comprising: means for sampling the current time stamp value and associating the value with at least some of the incoming data packets, the time stamp value indicating an arrival time of the respective data packet, and data transfer means adapted to transmit data of the incoming data packets with any associated time stamps to a memory of the interface unit, and output buffer means for transmitting data of the outgoing data packets and comprising: data transfer means adapted to receive data of the outgoing data packets with associated time stamps from the memory of the interface unit, and means for comparing the time stamp value of each outgoing data packet with the current tithe stamp value, and for transmitting an outgoing data packet to the head-end system when said values match a predetermined relationship, the processor means being adapted to generate and associate the output time stamp with each outgoing data packet, the output time stamp indicating a departure time of the data packet, the output time stamp value being related to input time stamp values of selected incoming data packets. thereby permitting correct time-slot alignment of outgoing data packets in the time division multiplexed system.