Patent ID: 8054686
Filing Date: 2011-11-08
Classification: G06F,G11C

Abstract:
1. A flash memory storage apparatus, comprising: at least one multi level cell (MLC) NAND flash memory, having a plurality of blocks for storing data, wherein each of the blocks comprises an upper page and a lower page, and the flash memory is programmed in multiple phases, wherein the lower page is programmed during a first phase, the upper page is programmed during another phase, and the writing speed of the lower page is faster than the writing speed of the upper page; a flash memory controller, electrically connected to the MLC NAND flash memory and configured to switch a storage mode of the flash memory storage apparatus to a performance mode or a space mode; and a host transmission bus, electrically connected to the flash memory controller for communicating with a host, wherein during the flash memory storage apparatus is enabled, the flash memory controller uses one of the performance mode and the space mode to write data in the MLC NAND flash memory, wherein the flash memory controller uses only the lower pages of the blocks for storing data without using the upper pages of the blocks for storing data when the storage mode is the performance mode, wherein the flash memory controller uses both the upper pages and the lower pages of the blocks for storing data when the storage mode is the space mode.