Patent ID: 6058041
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A SEU hardening circuit for use with a storage cell, wherein the storage cell includes a pair of cross-coupled inverters, the SEU hardening circuit having a first terminal and a second terminal, the first terminal connected to an output of one of the cross-coupled inverters, and the second terminal connected to an input of the other one of the cross-coupled inverters, the SEU hardening circuit comprising:a resistive means having a first terminal and a second terminal, the first terminal of the resistive means connected to the first terminal of the SEU hardening circuit;a p-channel transistor with a source terminal, a drain terminal, and a gate terminal;a n-channel transistor with a source terminal, a drain terminal, and a gate terminal;the source terminals of the p-channel transistor and the n-channel transistor being electrically connected to the first terminal of the resistive means;the drain terminals of the p-channel transistor and the n-channel transistor being electrically connected to the second terminal of the resistive means; andthe gate terminals of the p-channel transistor and the n-channel transistor being connected to complementary enable signals.