Patent ID: 6588005
Filing Date: 2003-07-01
Classification: G03F,G06F,H01L

Abstract:
A manufacturing method of semiconductor integrated circuit device, comprising the steps of:dividing a set of signal wiring into a set of long wiring and a set of short wiring by comparison with a reference value; arranging said set of long wiring in parallel to said set of short wiring and in proximity to at least one side of said set of short wiring; forming a set of signal wiring in a wiring region included in a semiconductor chip; making a layout rule of said set of long wiring different from a layout rule of said set of short wiring; and making an interval between a set of long wiring and a set of short wiring provided in parallel and in proximity thereto relatively narrower than an interval between sets of long wiring arranged in parallel to each other, by using a Levenson type phase shifter to expose a pattern of said set of short wiring on a photomask.