Patent ID: 8929148
Filing Date: 2015-01-06
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory blocks configured to comprise memory cells; a voltage supply circuit configured to, when an erase operation and an erase verify operation following the erase operation are repeatedly performed, supply an erase voltage for the erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for the erase verify operation of the memory block selected from the memory blocks; and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed, wherein a soft program operation of the selected memory block and a soft program verify operation of the selected memory block are repeatedly performed after a pass of the erase verify operation, wherein the voltage supply circuit supplies a soft program voltage for the soft program operation and supplies a soft program verify voltage and a soft program pass voltage for the soft program verify operation, wherein the control logic controls the voltage supply circuit so that one or more of the soft program verify voltage and the soft program pass voltage rise whenever the soft program verify operation is performed.