Patent ID: 8576620
Filing Date: 2013-11-05
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a source line; a bit line; a word line; a first signal line; a second signal line; a memory cell connected to the source line, the bit line, the word line, the first signal line, and the second signal line; a driver circuit configured to drive the second signal line and the word line so as to select the memory cell specified by an address signal; a writing circuit configured to output a writing potential to the first signal line; a reading circuit configured to compare a potential of the bit line with a plurality of reading potentials; a control circuit configured to select one of a plurality of voltages for correction on a basis of comparison results between the potential of the bit line and the plurality of reading potentials; and a potential generating circuit configured to generate the writing potential and the plurality of reading potentials to supply to the writing circuit and the reading circuit.