Patent ID: 7902661
Filing Date: 2011-03-08
Classification: H01L

Abstract:
1. An integrated circuit package comprising: a substrate having a top surface and an opposing bottom surface, there being a first cavity in the substrate, the substrate being formed from one selected from a group consisting of a semiconductor wafer, a semiconductor material, glass, steel, silicon, G10-FR4 and quartz; a first integrated circuit positioned within the first cavity; a plurality of layers of cured, photo-imageable epoxy that were deposited sequentially, wherein at least some of the epoxy layers are patterned, the plurality of epoxy layers including a first patterned epoxy layer, a second patterned epoxy layer and a third patterned epoxy layer and a fourth epoxy layer, wherein the first patterned epoxy layer is formed on the top surface of the substrate and the active surface of the first integrated circuit, the first patterned epoxy layer having a substantially planar top surface; a plurality of interconnect layers, including a first interconnect layer and a second interconnect layer, the first interconnect layer including a plurality of interconnect traces, the first interconnect layer formed on the first patterned epoxy layer and embedded in the first patterned epoxy layer, the first interconnect layer being electrically coupled through a via with the active surface of the first integrated circuit, wherein the second patterned epoxy layer is formed on the first patterned epoxy layer, the second patterned epoxy layer having a substantially planar top surface; a second integrated circuit having an active surface, the second integrated circuit being embedded in the second patterned epoxy layer, wherein: a component selected from a group consisting of an I/O pad that is exposed on the exterior of the integrated circuit package, an integrated circuit having an active surface that is covered by one of the epoxy layers and that is positioned in one of the patterned epoxy layers, an integrated circuit having an active surface that is covered by one of the epoxy layers and that is positioned in the substrate, and an electrical device that is embedded in one of the patterned epoxy layers, wherein the second integrated circuit is electrically coupled with the component through one of the interconnect layers; and a multiplicity of external package contacts formed over the fourth epoxy layer, the second integrated circuit being electrically connected to one of the external package contacts at least in part through one of the interconnect layers.