Patent ID: 8115721
Filing Date: 2012-02-14
Classification: G09G

Abstract:
1. A display data receiving circuit, comprising: a clock regeneration circuit which generates an internal clock signal having an integral multiple of a frequency of an external clock signal in response to said external clock signal; and a serial/parallel conversion circuit which receives a serial data signal as display data in synchronization with said internal clock signal, and generates a parallel data signal by executing a serial/parallel conversion for said serial data signal, wherein said serial/parallel conversion circuit is configured to be able selectively to execute either one of a single edge operation, which receives said serial data signal in response to one of a rising edge and a falling edge of said internal clock signal, and a double edge operation, which receives said serial data signal in response to both of said rising edge and said falling edge of said internal clock signal; wherein said clock regeneration circuit is configured to be able selectively to change a frequency of said internal clock signal, wherein, if the display data is supplied at a first transfer rate to the display data receiving circuit, the serial/parallel conversion circuit executes the single edge operation, and the frequency of the internal clock signal is set to be a times as high as the frequency of the external clock signal; and wherein, if the display data is supplied at a second transfer rate which is lower than the first transfer rate to the display data receiving circuit, the serial/parallel conversion circuit executes the double edge operation, and the frequency of the internal clock signal is set to be α/2 times as high as the frequency of the external clock signal.