Patent ID: 8972831
Filing Date: 2015-03-03
Classification: G06F,G06G,H03M

Abstract:
1. An analog processor for error correction of a parity check code, the parity check code having a plurality of parity constraints on input values of an input frame, the processor comprising: an intermediate value memory comprising a plurality of memory elements, each memory element being associated with a different corresponding combination of a constraint and an input value; a plurality of analog computation modules each for performing an analog computation associated with a parity constraint of the code, each input of the computation modules being connectable to a selected plurality of the memory elements and each output of the computation modules being connectable to a selected memory element; and a controller for sequencing operation of the processor in a series of iterations, and in each iteration in a series of cycles, wherein in each cycle the controller configures connections of inputs and outputs of each analog computation module to perform a computation associated with one of the parity constraints of the parity check code, including connecting each output of each analog computation module to a memory element associated with the parity constraint and connecting each input of the analog computation module to a memory element associated with an input value used in the parity constraint, wherein in each cycle, no memory element is connected to both an input and an output of any of the analog computation modules.