Patent ID: 7550768
Filing Date: 2009-06-23
Classification: G02F,H01L,Y10S

Abstract:
1. A thin film transistor array panel, comprising: an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an aluminum (Al) containing metal and a second layer of a Mo-alloy comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti), the gate line having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer; a data line formed on the semiconductor, the data line having a source electrode; a drain electrode formed on the semiconductor, the drain electrode facing the source electrode with a predetermined gap; a passivation layer formed on the data line and the drain electrode, the passivation layer having a contact hole; and, a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole, wherein the data line and the drain electrode have a third layer of a Mo containing metal, a fourth layer of an Al containing metal, and a fifth layer of a Mo containing metal, and at least one of the third and fifth layers comprising a Mo-alloy including molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti), wherein the semiconductor has the same planar pattern as the data line and the drain electrode except an area between the source electrode and the drain electrode.