Patent ID: 6810505
Filing Date: 2004-10-26
Classification: G06F

Abstract:
A method of designing an integrated circuit comprising steps of:(a) receiving as input a representation of a circuit design, a placement multiplier, and a delay multiplier; (b) scaling a capacitance of an interconnect wire in the circuit design by the placement multiplier; (c) performing a placement timing closure before routing to ensure that circuit timing constraints are met during cell placement; (d) performing a routing timing closure to ensure that circuit timing constraints are met for the circuit design during routing of the interconnect wire in the circuit design; (e) performing a parasitic extraction to determine a coupling capacitance of the interconnect wire; (f) scaling the coupling capacitance by the delay multiplier; (g) performing a delay analysis to determine whether a timing violation exists; (h) if a timing violation exists, then transferring control to (i), else transferring control to (j); (i) correcting the timing violation and transferring control back to (d); and (j) generating a timing sign-off report.