Patent ID: 6760389
Filing Date: 2004-07-06
Classification: H03L,H04L

Abstract:
A shared data and clock recovery circuit for processing a data stream generated using a source clock, the circuit comprising:(a) a clock synthesizer adapted to generate a plurality of sampling signals having different phases relative to a local clock; (b) a multiple transition detector adapted to detect edges in the data steam using the plurality of sampling signals; (c) a counter/accumulator adapted to generate (1) a weighted average difference between the local clock and the source clock and (2) the total number of edges detected in the data stream during a decision period; and (d) a decision circuit adapted to select one of the different phases of the plurality of sampling signals, wherein: when the total number of edges is greater than a specified threshold, the decision circuit is adapted to select one of the different phases based on the weighted average difference and update a stored difference based on the weighted average difference; and when the total number of edges is less than the specified threshold, the decision circuit is adapted to select one of the different phases based on the stored difference.