Patent ID: 7709893
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. An SRAM array cell comprising: a first stripe having a MuGFET single fin access device and pull up device; a second stripe having a MuGFET single fin access device and pull up device; a middle stripe having two MuGFET pull down devices with a current ratio compared to the access devices greater than 1, the two MuGFET pull down devices coupled via their corresponding serially-connected double fins to at least one common ground within the middle stripe; wherein the access devices and pull down devices are MOS single fin MuGFET transistors of a first conductivity type and the pull up devices are MOS single fin MuGFET transistors of a second conductivity type; and further comprising multiple cells laid out in an SRAM array in a folded manner such that isolated FET islands of FETs of the second conductivity type are formed.