Patent ID: 6300192
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method for fabricating a DRAM cell capacitor on an integrated circuit substrate, the substrate having an interlayer insulating layer thereon, contact plugs being separately buried in the interlayer insulating layer for electrically contacting the substrate, the method comprising:forming a first conductive layer on the interlayer insulating layer and on the contact plugs;etching selected portions of the first conductive layer between the contact plugs, thereby forming a first conductive pattern electrically connected to the contact plugs;forming a second conductive layer on the interlayer insulating layer and on the first conductive pattern;etching selected portions of the second conductive layer, thereby forming a second conductive pattern, the first and second conductive patterns defining a storage node;selectively forming an HSG silicon layer on the second conductive pattern;forming a dielectric film on the entire surface of the semiconductor substrate; andforming a plate node on the dielectric film.