Patent ID: 6725324
Filing Date: 2004-04-20
Classification: G05B,G06F

Abstract:
A computer system, comprising:a processor complex having a plurality of processors; a system memory accessible by at least one of the plurality of processors; a system BIOS adapted to rendezvous the plurality of processors to a common memory location in the system memory and designate one of the processors as a bootstrap processor; a non-volatile memory device adapted to be accessible to the plurality of processors; wherein the bootstrap processor is adapted to: program the non-volatile memory device by partitioning an image to be programmed into the non-volatile memory device into segments; divide the segments amongst one or more of the plurality of processors, each of the one or more of the plurality of processors being assigned to program a portion of the non-volatile memory device corresponding to its respective segment; and monitor the progress of the one or more of the plurality of processors to determine when the programming of the non-volatile memory device is completed.