Patent ID: 7834388
Filing Date: 2010-11-16
Classification: G11C,H01L

Abstract:
1. An electrically alterable, non-volatile memory array, comprising: a first memory string in a first column of the memory array and a second memory string being placed parallel the first memory string in a second column of the memory array, each memory string having: wherein (i) the first conductor of the first memory string and the first conductor of the second memory string are electrically coupled to each other; (ii) the first select line of the first memory string and the first select line of the second memory string are electrically isolated; (iii) the second select line of the first memory string and the second select line of the second memory string are electrically isolated, and (iv) the second conductor of the first memory string and the second conductor of the second memory string are electrically isolated; and (v) the first and second conductors of each memory string are each coupled to a charging transistor, a discharging transistor and a sense amplifier.