Patent ID: 7655387
Filing Date: 2010-02-02
Classification: H01L,Y10S

Abstract:
1. A method for forming an integrated circuit, comprising: providing a substrate, wherein a temporary layer overlies the substrate and a photodefinable layer overlies the temporary layer; forming a pattern in the photodefinable layer; transferring the pattern to the temporary layer to form a plurality of spaced-apart placeholders in the temporary layer; depositing a blanket layer of spacer material over the plurality of placeholders; selectively removing the spacer material from horizontal surfaces to form a plurality of spacer loops formed of spacer material around sides of the spaced-apart placeholders; selectively removing the placeholders relative to the spacer material to leave the plurality of spacer loops overlying the substrate; etching the spacer loops to form a pattern of separated spacers, each spacer having two opposing sides extending a length of the spacer; forming an other photodefinable layer around and on the same level as the separated spacers; and patterning elongated photodefined features in the other photodefinable layer, wherein the photodefined features and the spacers are aligned such that each of the photodefined features contacts one side of each of the spacers without contacting the opposite side of the spacer.