Patent ID: 6130015
Filing Date: 2000-10-10
Classification: H01L,H05K,Y10S

Abstract:
A method of making a laminated integrated circuit chip package substrate, comprising the steps of:providing a metal core layer having at least one aperture formed therethrough;forming a plurality of fiducials in a surface of the metal core layer;providing a first dielectric layer and a first conductive layer, said first dielectric layer including a fluoropolymer non-woven substrate containing a collection of filler particles;affixing the first dielectric layer to the surface of the metal core layer having the plurality of fiducials;affixing the first conductive layer to the first dielectric layer;laser drilling through the first dielectric layer and the first conductive layer to expose a first fiducial of the metal core layer;while referencing said first fiducial, forming a first opening in a location through the first conductive layer, the first opening being aligned with the at least one aperture of the metal core;providing a second dielectric layer and a second conductive layer, said second dielectric layer including a fluoropolymer non-woven substrate containing a collection of filler particles;affixing the second dielectric layer to the first conductive layer;affixing the second conductive layer to the second dielectric layer;laser drilling through the second conductive layer, the second dielectric layer, the first conductive layer and the first dielectric layer to expose a second fiducial of the metal core; andwhile referencing said second fiducial, forming a via in a location through the second conductive layer, the second dielectric layer, the opening in the first conductive layer and said first dielectric layer, said via extending from said second conductive layer through said at least one opening of the metal core.