Patent ID: 7849431
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A complementary metal oxide semiconductor (CMOS) inverter layout comprising: i first active regions, where i is a natural number equal to or greater than 2; j first conductive MOS transistors formed in the first active regions, where j is a natural number equal to or greater than i; (i−1) first metal lines electrically connecting the i first active regions; m second active regions, m is a natural number equal to or greater than 2, the first active regions and the second active regions are connected in series; n second conductive MOS transistors formed in the second active regions, where n is a natural number equal to or greater than m; (m−1) second metal lines electrically connecting the m second active regions; and at least one gate, at least a portion of the at least one gate intersecting at least two of the first active regions and the second active regions, wherein