Patent ID: 6292006
Filing Date: 2001-09-18
Classification: G01R,H05K

Abstract:
A method for testing semiconductor devices comprising the steps of:assembling a tester mother board having a plurality of spring biased pins a handler board having a top side and a bottom side, and a coplanarity plate between the bottom side of the handler board and the tester mother board such that the spring-biased pins extending from the mother board are compressed against contact pads formed on the handler board, the coplanarity plate forming a tight joint to both the mother board and the bottom side of the handler board, forming a central hollow region, and having at least two openings by which gas can be introduced to the hollow region and be discharged,attaching to a test site located on the top side of the handler board an integrated circuit device to be tested, wherein the handler board includes metallization lines connecting from the contact pads to the test site;cooling the integrated circuit device to a temperature at which the integrated circuit device is to be tested; andapplying a dry gas to one of the openings of the coplanarity plate, thereby introducing the dry gas to the hollow region.