Patent ID: 6709564
Filing Date: 2004-03-23
Classification: C25D,H01L

Abstract:
A process for electroplating copper circuitry in trenches and vias in dielectric material on semiconductor chips, comprising:providing a semiconductor chip which includes dielectric material in which trenches and/or vias have been formed, placing said chip in contact with an electroplating solution, said solution comprising: water as a solvent, copper in either the +1 or +2 oxidation state or a mixture of the two states, anions that form at least one complex ion with said copper so as to significantly increase the overvoltage for copper electrodeposition such that the copper deposition rate at a given cathode voltage is suppressed, and at least one organic additive species which tends to further suppress the copper deposition rate so as to provide the rate differential needed to provide bottom-up filling of said trenches and/or vias, and electrodepositing copper in said trenches and/or vias.