Patent ID: 9202541
Filing Date: 2015-12-01
Classification: G06F,G11C

Abstract:
1. A semiconductor apparatus comprising: first and second bus-interface circuits; a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit; a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal; a second memory core, the second memory core being supplied with a second clock signal; a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information; and a clock generation circuit that generates the first and second clock signals based on at least part of the first and second mode information, wherein the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.