Patent ID: 6288961
Filing Date: 2001-09-11
Classification: G11C

Abstract:
A semiconductor device comprising:a word line;first and second bit lines;a plate line;a memory cell connected to the word line, the plate line and the first bit line, the memory cell having a transistor for transferring charges and a capacitor for storing the charges;a control circuit for generating second and third control signals in response to a first control signal;a decoder circuit connected to the word line, for selecting the word line in accordance with a plurality of address signals, the decoder circuit setting the selected word line in an unselected state in response to the second control signal;a sense amplifier connected to the first and second bit lines and activated in response to the third control signal; anda plate line decoder circuit for selecting the plate line based on the first control signal and the plate line control signal and setting the plate line in an unselected state before transition of the second control signal occurs.