Patent ID: 6831863
Filing Date: 2004-12-14
Classification: G11C,H01L

Abstract:
An array of flash memory cells, comprising:a plurality of flash memory cells arranged in a form of matrix, each of said flash memory cells having a single transistor with a MONOS/SONOS structure, wherein the single transistor includes: a gate formed over a semiconductor substrate; a source and a drain formed in said semiconductor substrate at edges of said gate; and a bottom silicon oxynitride film, a middle silicon oxynitride film and a top silicon oxynitride film stacked between said gate and said semiconductor substrate, wherein nitrogen concentration of said middle silicon oxynitride film is higher than those of the bottom silicon oxynitride film and said top silicon oxynitride film; a plurality of word lines arranged in a one line direction so that said gates of said flash memory cells arranged in a row are commonly connected; a plurality of selection lines arranged in the direction perpendicular to said word lines so that said sources of said flash memory cells arranged in a column are commonly connected; and a plurality of bit lines arranged in a direction parallel to said selection lines so that said drains of said flash memory cells arranged in said column are commonly connected.