Patent ID: 6313709
Filing Date: 2001-11-06
Classification: H03L

Abstract:
A phase-locked loop comprising a phase comparator for comparing a reference signal and a comparison signal to output a signal corresponding to a phase difference, a loop filter for outputting a control voltage corresponding to the signal outputted from the loop filter, a voltage controlled oscillator for outputting a clock corresponding to the control voltage outputted from the loop filter and a loop counter for dividing the frequency of the clock outputted from the voltage controlled oscillator into 1/N, N: an integer for feedback as a comparison signal to the phase comparator, wherein there are further provided a prediction window circuit for outputting a prediction window signal for predicting the point at which the reference signal is generated and an omission compensation circuit for not only detecting the omission of the reference signal at the time of the output of the prediction window signal but also outputting a first correction signal for correcting the omission and a second correction signal for offsetting the phase difference between the comparison signal and the first correction signal, whereby the phase comparator outputs not only a signal corresponding to the phase difference between the comparison signal and the first correction signal but also the signal corresponding to the phase difference between the first correction signal and the second correction signal.