Patent ID: 8018008
Filing Date: 2011-09-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first chip including a first conductivity type channel power MOSFET, the first conductivity type channel power MOSFET including a first semiconductor substrate of the first conductivity type having first and second opposing surfaces, a drift layer of the first conductivity type disposed on the first surface of the first semiconductor substrate and having a cell section, a channel layer of a second conductivity type disposed at a surface portion of the cell section of the drift layer, a source region of the first conductivity type disposed at a surface portion of the channel layer, a gate insulating layer disposed on a channel region provided at a portion of the channel layer located between the source region and the drift layer, a gate electrode disposed on an opposite side of the gate insulating layer from the channel region, a source electrode electrically coupled with the channel layer and the source region, a second-surface drain electrode disposed on the second surface of the first semiconductor substrate; and a second chip including a second conductivity type channel power MOSFET, the second conductivity type channel power MOSFET including a second semiconductor substrate of the second conductivity type having first and second opposing surfaces, a drift layer of the second conductivity type disposed on the first surface of the second semiconductor substrate and having a cell section, a channel layer of the first conductivity type disposed at a surface portion of the cell section of the drift layer, a source region of the second conductivity type disposed at a surface portion of the channel layer, a gate insulating layer disposed on a channel region provided at a portion of the channel layer located between the source region and the drift layer, a gate electrode disposed on an opposite side of the gate insulating layer from the channel region, a source electrode electrically coupled with the channel layer and the source region, a second-surface drain electrode disposed on the second surface of the second semiconductor substrate, wherein the first chip and the second chip are integrated in such a manner that the second-surface drain electrode of the first chip and the second-surface drain electrode of the second chip face to each other and are electrically coupled with each other through a conductive material.