Patent ID: 6208172
Filing Date: 2001-03-27
Classification: G01R

Abstract:
A circuit for monitoring performance of an integrated circuit comprising:a phase delay detection circuit coupled to an output pin of the integrated circuit and to a clock signal, the clock signal being used to clock circuitry within the integrated circuit, the circuitry within the integrated circuit generating an output signal on the output pin of the integrated circuit, wherein the phase delay detection circuit includes:digital signal generating means, coupled to the output pin of the integrated circuit, for generating a digital signal, wherein changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal result in changes in a duty cycle of the digital signal generated by the digital signal generating means, wherein the digital signal generating means comprises:a delay flip-flop having a D input, a clock input and a Q output, the clock signal being coupled to the clock input and the output signal being coupled to the D input, anda gate having a signal input, a control input and an output, the output signal on the output pin of the integrated circuit being coupled to the signal input of the gate, and the Q output being coupled to the control input of the gate; andintegrating means for integrating the digital signal to produce an integrated signal, the integrated means having an input coupled to the output of the gate, wherein a voltage level of the integrated signal indicates relative phase delay between the output signal on the output pin of the integrated circuit and the clock signal.