Patent ID: 6200854
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method of fabricating dynamic random access memory, comprising the steps of:providing a substrate having a plurality of device isolation structures therein;sequentially forming a conductive layer, a metal silicide layer, a first cap layer and a second cap layer;patterning the second cap layer, the first cap layer, the metal silicide layer and the conductive layer to form a gate structure that exposes a portion of the substrate;forming a first oxide layer over the exposed substrate and sidewalls of the metal silicide layer and the conductive layer;forming first spacers on sidewalls of the gate structure;forming a second oxide layer conformal to the substrate profile;forming second spacers over the second oxide layer;forming a third oxide layer over the substrate;removing the second spacers;removing the second oxide layer and a portion of the first oxide layer to expose a portion of the substrate;forming a conformal contact pad over the exposed substrate and the first spacers;forming a dielectric layer over the substrate;forming source/drain regions in the substrate on each side of the third oxide layer;forming a bit line contact opening that exposes a portion of the contact pad in the first dielectric layer;forming a bit line that connects electrically with the exposed contact pad;forming a second dielectric layer over the substrate;forming a storage node contact opening that passes through the second dielectric layer and the first dielectric layer and exposes a portion of the contact pad; andforming a storage node electrode that connects electrically with the contact pad.