Patent ID: 6192160
Filing Date: 2001-02-20
Classification: G06K,G06T

Abstract:
A hardware architecture for a dilation operation, comprising:a plurality of adding means for receiving a plurality of pixel data of an image signal, for receiving a plurality of structuring element data, wherein each of said structuring element data corresponds to one of the pixel data, and for adding the pixel data to the corresponding structuring element data to output an added result;a plurality of storing means for storing the added results from said plurality of adding means;comparing means for receiving the added results from each of said plurality of storing means, for receiving an intermediate feedback data during the dilation operation, and for comparing the added results from each of the plurality of storing means with each other and with the intermediate feedback data to create a maximum data until each of the plurality of added results from each of the storing means have been compared; andoutputting means for feeding back the maximum data from said comparing means as the intermediate feedback data to the comparing means, and, after the dilation operation is completed, for outputting the maximum data.