Patent ID: 7652603
Filing Date: 2010-01-26
Classification: H02M,H03F,H03M

Abstract:
1. A ΔΣ-type AD converter comprising: a subtractor which receives an analogue input signal and a feedback signal and which outputs a signal pertaining to a difference between the analogue input signal and the feedback signal; an integrator which integrates a signal output from the subtractor; a comparator which binarizes a signal output from the integrator by comparing with a predetermined threshold value; a counter which measures respective pulse widths of a signal output from the comparator; a loop filter which phase-compensates and gain-adjusts a count value output from the counter; and a PWM circuit which outputs a pulse signal of a predetermined period having a duty cycle responsive to the phase-compensated and gain-adjusted count value output from the loop filter and which feeds back the pulse signal as the feedback signal to the subtractor, wherein the counter is an up counter, and measures the respective pulse widths in each PWM frame period in synchronism with the PWM circuit, and resets the count value in the each PWM frame period, and the PWM circuit feeds back to the subtractor the pulse signal having a duty cycle which is set in accordance with a value of the measured pulse width in a next PWM frame period; and wherein a count value output from the counter is extracted as a converted digital output value.