Patent ID: 6505304
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A timer apparatus comprising:a plurality of counters; a register, provided in correspondence to each of said counters, for writing an operation command to each of said counters; and a distribution writing circuit for simultaneously writing each of said operation commands at bit positions corresponding to said counters of a bit train into each of said registers corresponding to each of said counters in order to control an operation of each of said counters when receiving said bit train which consists of a plurality of continuous bits to which one address information has been added and in which each of said bits indicates the operation command to said counter corresponding to each of the bit positions, wherein operation commands to the timers can be simultaneously written into the register of each timer, and additionally, operation commands to the counters to which address information peculiar to each timer has been given can be sequentially written into the register of each timer.