Patent ID: 7313051
Filing Date: 2007-12-25
Classification: G11C

Abstract:
1. An output control signal generating circuit that takes in a read command in synchronism with a first clock and that controls an output timing of read data in synchronism with the first clock after n (where n is a natural number) cycles, the output control signal generating circuit comprising: n latch circuits connected in cascade, including a first-stage latch circuit that latches an internal command generated based on the read command and a last-stage latch circuit that outputs an output control signal; and a timing signal generating circuit that generates a timing signal to be supplied to the n latch circuits, based on a second clock of which phase is advanced from a phase of the first clock, wherein the timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits.