Patent ID: 6636454
Filing Date: 2003-10-21
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of unit cells arranged in rows and columns, each of said plurality of unit cells having first and second storage elements, each of said first and second storage elements including a capacitor for storing information and an access transistor; a plurality of bit line pairs provided corresponding to the respective columns, each of the bit line pairs connecting to the unit cells on a corresponding column, each of the bit line pairs including first and second bit lines respectively coupled to said first and second storage elements of the unit cells of the corresponding column; a plurality of row selection lines provided corresponding to the respective rows, each of the row selection lines connecting to the unit cells of a corresponding, each of the row selection lines including a first word line connecting to the first storage elements of the unit cells on a corresponding row, and a second word line connecting to the second storage elements of the unit cells on the corresponding row; a row selection circuit for simultaneously driving the first and second word lines of a row selection line arranged corresponding to an addressed row into a selected state according to an address signal; and a bit-line voltage setting circuit for setting voltages on the first and second bit lines of each of said bit line pairs to a voltage level different from an intermediate voltage level in a standby state, the intermediate voltage level being equal to half a sum of voltages respectively corresponding to high-level and low-level data stored in said first and second storage elements.