Patent ID: 6215701
Filing Date: 2001-04-10
Classification: G11C,H01L

Abstract:
A gate array logic device comprising a plurality of nonvolatile memory cells each connected with one of a plurality of control lines that select the nonvolatile memory cells, and further connected with one of a plurality of bit lines through which data that is stored in the nonvolatile memory cells are read, each of the nonvolatile memory cells further comprising:a first MOS transistor formed in a top surface of a semiconductor substrate, said first MOS transistor having spaced apart first and second impurity regions, and a gate electrode above and between the first and second impurity regions of said first MOS transistor; anda second MOS transistor formed in the top surface of the semiconductor substrate, said second MOS transistor having spaced apart first and second impurity regions, and a gate between the first and second impurity regions of said second MOS transistor, the first impurity region of said second MOS transistor being connected with a voltage supply line,the second impurity region of said first MOS transistor being electrically connected with the second impurity region of said second MOS transistor, one of the plurality of bit lines being connected to the first impurity region of said first MOS transistor, and one of the plurality of control lines being connected to the gate electrode of said first MOS transistor.