Patent ID: 6700424
Filing Date: 2004-03-02
Classification: H03K

Abstract:
A multiple-channel input buffer circuit, comprising:a pair of logic transistors comprising a p-type transistor coupled in series, drain to drain, with an n-type transistor, a pair of voltage offset transistors comprising a p-type transistor having a drain coupled to a source of the p-type logic transistor and a source coupled to a power supply, and an n-type transistor having a drain coupled to a source of the n-type logic transistor and a source coupled to ground, an input terminal coupled to gates of the logic and voltage offset transistors, and a plurality of pairs of feedback transistors, each pair of feedback transistors comprising a p-type transistor having a source coupled to a junction of the p-type logic and voltage offset transistors, a gate coupled to an output terminal and a drain coupled to ground through a switching circuit, and an n-type transistor having a source coupled to a junction of the n-type logic and voltage offset transistors, a gate coupled to the output terminal and a drain coupled to the power supply through the switching circuit, wherein when the switching circuit associated with a pair of feedback transistors is activated, the respective pair of feedback transistors supply a positive feedback to control a conductivity of the logic transistors and vary a voltage level on the output terminal.