Patent ID: 6351177
Filing Date: 2002-02-26
Classification: G05F

Abstract:
A programmable reference voltage generator, comprising:a bandgap generation circuit for providing an operating voltage; a first amplifier having a negative input terminal for receiving the operating voltage; a second amplifier having a positive input terminal for receiving the operating voltage, a negative input terminal connected to a first node point and an output terminal connected to a second node point; a first PMOS transistor having a source terminal and a substrate connected to a source voltage, a gate terminal connected to the output terminal of the first amplifier and a drain terminal connected to the positive input terminal of the first amplifier; a second PMOS transistor having a source terminal and a substrate connected to the voltage source and the gate terminal connected to the output terminal of the first amplifier; a third PMOS transistor having a source terminal and a substrate connected to the voltage source, and a gate terminal and a drain terminal connected to each other; a fourth PMOS transistor having a source terminal and a substrate connected to the voltage source and a gate terminal connected to the gate terminal of the third PMOS transistor; a fifth PMOS transistor having a source terminal and a substrate connected to the source voltage, and a gate terminal and a drain terminal connected to each other; a sixth PMOS transistor having a source terminal and a substrate connected to the source voltage, a gate terminal connected to the drain terminal of the fifth PMOS transistor and a drain terminal connected to a fourth node point; a first NMOS transistor having a source terminal and a substrate connected to a ground voltage, and a gate terminal and a drain terminal connected to each other and to the drain terminal of the second PMOS transistor; a second NMOS transistor having a source terminal and a substrate connected to the ground, a gate terminal connected to the gate terminal of the first NMOS transistor, and a drain terminal connected to the drain terminal of the third PMOS transistor; a third NMOS transistor having a source terminal and a substrate connected to the ground, and a gate terminal and a drain terminal connected to each other and to the drain terminal of the fourth PMOS transistor; a fourth NMOS transistor having a source terminal and a substrate connected to the ground, a gate terminal connected to the gate terminal of the third NMOS transistor and a drain terminal connected to the drain terminal of the fifth PMOS transistor; a fifth NMOS transistor having a source terminal and a substrate connected to the ground, a gate terminal connected to the gate terminal of the fourth PMOS transistor and a drain terminal connected to the third node point; a first variable current source having an input terminal connected to the voltage source and output terminal connected to the drain terminal of the fourth PMOS transistor; a second variable current source having an input terminal connected to the voltage source and an output terminal connected to the fourth node point; a first resistor having a first terminal connected to the positive input terminal of the first amplifier and a second terminal connected to the ground; a second resistor having a first terminal connected to the first node point and a second terminal connected to the second node point; a third resistor having a first terminal connected to the first node point and a second terminal connected to the third node point; a fourth resistor having a first terminal connected to the fourth node point and the second terminal connected to the ground; wherein the first node point, the second node point, the third node point and the fourth node point are used for outputting a first reference voltage, a second reference voltage, a third reference voltage and a fourth reference voltage respectively.