Patent ID: 8138079
Filing Date: 2012-03-20
Classification: H01L

Abstract:
1. A method for fabricating a circuit component, comprising: providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, and a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening; forming a metal pad over said semiconductor substrate, wherein said metal pad is connected to said contact point through said first opening, wherein said forming said metal pad comprises forming a glue layer on said contact point and over said passivation layer, followed by forming a seed layer on said glue layer, followed by forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer exposes a region of said seed layer, followed by electroplating a copper layer on said region, wherein said copper layer has a thickness greater than 1 micrometer, followed by electroplating a nickel layer on said copper layer in said second opening, wherein said nickel layer has a thickness greater than 0.5 micrometers, followed by electroless plating a gold layer on said nickel layer in said second opening, followed by removing said photoresist layer, followed by etching said seed layer and said glue layer; and bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device.