Patent ID: 8253477
Filing Date: 2012-08-28
Classification: G11C,H02M

Abstract:
1. A voltage boost circuit, comprising: a first clock signal which toggles between a first voltage V an output node having an associated output node voltage; a first PMOS FET coupled between said first clock signal and said output node, said first PMOS FET including an nwell in which its drain, source and bulk regions reside; a semiconductor device coupled between said output node and a supply voltage; a capacitance, the first terminal of which is coupled to said output node, said voltage boost circuit arranged such that the voltage applied to the top (clock signal side) of said first PMOS FET toggles between ˜V a first delay circuit which is coupled to the second terminal of said capacitance and arranged to toggle the voltage on said second terminal to ˜V said voltage boost circuit arranged such that: said voltage boost circuit arranged such that the junction subjected to said voltage greater than V