Patent ID: 8237693
Filing Date: 2012-08-07
Classification: G09G

Abstract:
1. An operational amplifier comprising: a first output transistor and a second output transistor connected in series between a first power supply and a second power supply; an output terminal connected to a node between said first output transistor and said second output transistor; a phase-compensating element provided either between the gate of said first output transistor and said output terminal or between the gate of said second output transistor and said output terminal; a floating current source connected between the gate of said first output transistor and the gate of said second output transistor; a third transistor and a fourth transistor constituting a differential pair; a first constant current source connected to a common connection point to which the sources of said third transistor and said fourth transistor are connected in common and to said second power supply, so as to bias said differential pair; a fifth transistor and a sixth transistor constituting a current mirror and functioning as the active load of said differential pair; wherein a common connection point to which the sources of said fifth transistor and said sixth transistor are connected in common is connected to said first power supply, the gates of said fifth transistor and said sixth transistor are connected in common to each other, and one of the outputs of a differential amplifier constituted by said differential pair and said active load from a connection point between said differential pair and said active load is connected to one of the gates of said first output transistor and said second output transistor to which said phase-compensating element is connected; a first switch inserted between the gate and the drain of said fifth transistor; a second switch inserted between the gate and the drain of said sixth transistor; a third switch connected between the drain of said sixth transistor and the gate of said first output transistor; a fourth switch connected between the drain of said fifth transistor and the gate of said first output transistor; a fifth switch connected between said output terminal and the gate of said third transistor; a sixth switch connected between said output terminal and the gate of said fourth transistor; a seventh switch connected between an input terminal and the gate of said fourth transistor; and an eighth switch connected between said input terminal and the gate of said third transistor; wherein all of said first to eighth switches are controlled in conjunction with one another.