Patent ID: 6215433
Filing Date: 2001-04-10
Classification: G11B,H03L

Abstract:
A clock generator for an optical Partial Response Maximum Likelihood (PRML) read channel for producing a clock signal with minimal jitter from an input signal subject to baseline wandering, comprising:a. a Voltage Gain Amplifier (VGA) amplifier for amplifying the input signal to produce a first analog signal;b. a low-pass filter for filtering the first analog signal to produce a second analog signal;c. an Analog-to-Digital Converter (ADC) for converting the second analog signal into a first digital signal, the ADC operating synchronously with the clock signal;d. a baseline wander correction circuit for reducing jitter in the clock signal caused by baseline wandering of the input signal, the baseline wander circuit including a quantizer circuit to reduce noise and a correction circuit executing a predetermined transfer function, the baseline wander correction circuit producing from the first digital signal a second digital signal, the second digital signal experiencing substantially less baseline wandering than the first digital signal, the baseline wander correction circuit operating synchronously with the clock signal;e. a timing offset detector and loop filter circuit for generating from the second digital signal a timing adjust signal representative of an adjustment to the clock signal, the timing offset detector operating synchronously with the clock signal;f. a Digital-to-Analog Converter (DAC) for converting the timing adjust signal into a third analog signal, the DAC operating synchronously with the clock signal; andg. a Voltage Controlled Oscillator (VCO) for generating the clock signal in response to the third analog signal.