Patent ID: 8037285
Filing Date: 2011-10-11
Classification: G06F,Y02D

Abstract:
1. An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequences of operations, based on one or more sequences of instructions, to an execution circuit of the processor, where the instruction processing circuit comprises: a decoder circuit configured to receive a sequence of instructions, to detect a decode time instruction mode that is one of a plurality of instruction modes, and to decode, based in part on the decode time instruction mode, the received sequence of instructions into a first type of sequence of operations, wherein the decode time instruction mode comprises configurable characteristics of the processor during decoding and is included in the sequence of operations of the first type, and the decoder circuit being further configured to associate flag information indicative of the decode time instruction mode with the sequence of operations of the first type; a trace builder circuit configured to receive at least a portion of the sequence of operations of the first type and to generate, based thereon, a second type of sequence of operations, where the at least a portion of the sequence of operations of the first type represents a first portion of the sequence of instructions, where the first portion of the sequence of instructions includes at most one conditional control transfer instruction that, when present, ends the first portion of the sequence of instructions, and where the sequence of operations of the second type also represents the first portion of the sequence of instructions, and the trace builder circuit being further configured to receive a set of at least two sequences of operations and to generate, based thereon, a third type of sequence of operations, where the sequence of operations of the third type represents a second portion of the sequence of instructions, and where the received set of at least two sequences of operations comprises at least one selected from a group consisting of a portion of the sequences of operations of the first type, a portion of the sequences of operations of the second type, and a portion of the sequences of operations of the third type; and a sequencer circuit configured to select a next sequence of operations from among the sequence of operations of the first type and the sequence of operations of the second type, the sequencer circuit being further configured to detect a sequencing time instruction mode and to compare the sequencing time instruction mode with the decode time instruction mode associated with the next sequence of operations to determine validity of the next sequence of operations, and the sequencer circuit being further configured to, if the next sequence of operations is determined to be invalid, invalidate the next sequence of operations, wherein the sequencing time instruction mode comprises configurable characteristics of the processor during operations of the sequencer.