Patent ID: 7788448
Filing Date: 2010-08-31
Classification: G06F

Abstract:
1. A cache system, comprising: a common cache memory dedicated to only service a plurality of sequencers with sequencer code during normal operation of the plurality of sequencers, wherein each of the plurality of sequencers is disposed within a Serial Attached SCSI (SAS) controller and is defined as a processor chip for controlling delivery of data to and from a peripheral device to which the processor chip is connected, and wherein the sequencer code is a set of binary instructions defined to direct operation of each of the plurality of sequencers, wherein each of the plurality of sequencers includes its own on-board cache memory; an external memory defined to store a complete version of the sequencer code; a plurality of cache managers respectively assigned to service a different one of the plurality of sequencers during normal operation of the plurality of sequencers, each of the plurality of cache managers defined to direct placement of sequencer code portions from the external memory into the common cache memory, each of the plurality of cache managers defined to provide requested sequencer code portions from the common cache memory to the on-board cache memory of its respectively assigned sequencer when a request for the sequencer code portions is provided to the cache manager from its respectively assigned sequencer during normal operation of its respectively assigned sequencer; and a direct memory access (DMA) engine defined to write requested sequencer code portions from the external memory to the common cache memory in accordance with direction from any of the plurality of cache managers when the requested sequencer code portions are not already present in the common cache memory.