Patent ID: 7260164
Filing Date: 2007-08-21
Classification: H04L

Abstract:
1. A circuit for filtering a digital signal, comprising: a majority determination circuitry that keeps track of glitches, in the digital signal, the majority determination circuitry divides a period of a clock into n segments and determines a logic level of each of the n segments, wherein if a majority of the n segments is of a first value, a value of the output signal is equal to the first value; a change determination circuitry that issues a first signal if an output of the majority determination circuitry changes from the first value to a second value and issues a second signal if the output of the majority determination circuitry does not change from the first value to the second value; a counter circuitry that is initialized when the first signal is issued; and an output mux circuitry that outputs one of either a third signal or a fourth signal as a output signal based upon a counter circuitry output signal.