Patent ID: 6118150
Filing Date: 2000-09-12
Classification: H01L

Abstract:
An insulated gate semiconductor device comprising a semiconductor base defining a top major surface and a bottom major surface, whereinsaid semiconductor base includes:a first semiconductor layer of a first conductivity type being exposed to said top major surface;a second semiconductor layer of a second conductivity type being formed in a portion of said top major surface within said first semiconductor layer;a third semiconductor layer of the second conductivity type formed in a portion of said top major surface within said first semiconductor layer by selectively diffusing an impurity, said third semiconductor layer being deeper than said second semiconductor layer, said third semiconductor layer being linked to said second semiconductor layer, said third semiconductor layer surrounding said second semiconductor layer; anda fourth semiconductor layer of the first conductivity type being selectively formed in a portion of said top major surface within said second semiconductor layer,in said semiconductor base, a trench is formed which is open in said top major surface, which penetrates said fourth and said second semiconductor layers and which reaches said first semiconductor layer,said device further comprises:a gate insulation film which ensures electric insulation, said gate insulation film covering an inner wall of said trench;a gate electrode which is buried within said trench, with said gate insulation film located between said gate electrode and said semiconductor base;a gate wire line which is disposed on said top major surface through an insulation film so as to extend along said third semiconductor layer, said gate wire line being electrically connected to said gate electrode;a first major electrode which is disposed on said top major surface, said first major electrode being electrically connected to said second and said fourth semiconductor layers; anda second major electrode which is disposed on said bottom major surface, said second major electrode being electrically connected to said bottom major surface,said first major electrode is also electrically connected to a side diffusion region which is adjacent to said second semiconductor layer within said third semiconductor layer and has a convexly sloping diffusion structure on a side of said side diffusion region which is adjacent to said second semiconductor layer, andsaid fourth semiconductor layer is not formed within said side diffusion region.