Patent ID: 6858525
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. An interconnect forming method for forming a stacked local interconnect in a semiconductor substrate having a plurality of features formed thereon, at least one feature of the plurality of features being an electrical contact located on a surface of the semiconductor substrate, having at least one etch stop layer on at least a portion of the surface of the semiconductor substrate, and having a passivation layer covering at least a portion of the at least one etch stop layer and covering at least a portion of the electrical contact, the method comprising: depositing a layer of resist over at least a portion of the at least one etch stop layer; patterning the layer of resist; providing a self-aligned contact etching process; etching through at least a portion of the passivation layer using the self-aligned contact etching process; exposing the electrical contact using the etching through the at least a portion of the passivation layer; forming a second local interconnect electrically connecting a first group of features included within the plurality of features; electrically connecting the second local interconnect to the stacked local interconnect during the forming thereof; and forming a third local interconnect electrically connected to the first local interconnect and at least one feature of the plurality of features.