Patent ID: 7660161
Filing Date: 2010-02-09
Classification: G11C

Abstract:
1. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising: a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal, a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element; and a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load; wherein the load element includes a PMOS transistor; wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor; and wherein the voltage follower circuit comprises: