Patent ID: 8778794
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A method of forming interconnecting wires during fabrication of a semiconductor device, the method comprising: providing a stack of layers comprising a substrate; an etch stop layer formed upon the substrate, and a sacrificial layer formed upon the etch stop layer; forming a plurality of substantially equal-spaced first spacers having a first pitch from the sacrificial layer; forming a plurality of substantially equal-spaced first metal interconnecting wires having a second pitch by utilizing the first spacers, the second pitch being half of the first pitch; removing the first spacers; forming a plurality of substantially equal-spaced polymer-like second spacers in such a way to abut, respectively, the plurality of first metal interconnecting wires and define a plurality of substantially equal-spaced trenches alternatingly located among the first metal interconnecting wires and bounded by the second spacers; forming a plurality of second metal interconnecting wires disposed, respectively, within the trenches; removing the second spacers, thereby defining thereat a plurality of substantially equal-spaced channels interwoven with the alternating first and second metal interconnecting wires; forming an anti-diffusion barrier around each of the first and second metal interconnecting wires; and forming dielectric insulation layers within the channels.