Patent ID: 8698201
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer over the buffer layer and a barrier layer over the channel layer, the method comprising: forming a gate, the gate comprising a first dielectric; forming first sidewalls on either side and adjacent to the gate, the first sidewalls comprising a second dielectric; selectively etching into the buffer layer to form a mesa for the field effect transistor; depositing a dielectric layer over the mesa; planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface; selectively etching and removing the gate to form a vacated region; and depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate.