Patent ID: 6873555
Filing Date: 2005-03-29
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device on a semiconductor substrate, the semiconductor integrated circuit device comprising: a voltage step-down circuit which is coupled to receive a first and a second power supply voltages and which generates an internal power supply voltage having a voltage level between voltage levels of the first and the second power supply voltages; a first volatile storage circuit which is coupled to the voltage step-down circuit and which is capable of storing first information to trim the voltage level of the internal power supply voltage generated from the voltage step-down circuit; an input and output circuit which is coupled between the first and the second power supply voltages and which inputs data from an outside of the semiconductor integrated circuit device or outputs data to the outside of the semiconductor integrated circuit device; a bus which is coupled to the input and output circuit; a central processing unit which is coupled to the bus and which is coupled to receive the internal power supply voltage and the second power supply voltage so that the central processing unit operates at a voltage level between the voltage levels of the internal power supply voltage and the second power supply voltage; an electrically erasable and programmable nonvolatile memory which is coupled to the bus and which is coupled to receive the internal power supply voltage and the second power supply voltage, the electrically erasable and programmable nonvolatile memory including: wherein the first and the second information stored in the third memory elements are read out in response to an initialization of the semiconductor integrated circuit device, wherein the first volatile storage circuit latches the first information read out from the third memory elements in response to the initialization of the semiconductor integrated circuit device so that the internal supply voltage which is trimmed according to the first information is supplied from the voltage step-down circuit to the central processing unit and the electrically erasable and programmable nonvolatile memory, and wherein the second volatile storage circuit latches the second information read out from the third memory elements in response to the initialization of the semiconductor integrated circuit device.