Patent ID: 9209189
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device, comprising a plurality of DRAM cells each comprising a selective MISFET and a capacitive element that are coupled in series to each other, the device comprising: a semiconductor substrate, a first insulator film formed over a main surface of the semiconductor substrate, and having a capacitor-forming trench comprising a side wall and a bottom surface, a lower electrode formed along/over the side wall and the bottom surface comprised in the capacitor-forming trench, a capacitive insulator film formed over the lower electrode to cover the lower electrode, a first upper electrode formed over the capacitive insulator film to cover the capacitive insulator film, a second upper electrode formed over the first upper electrode to cover the first upper electrode, a third upper electrode formed over the second upper electrode to cover the second upper electrode, and having a smaller electric resistivity than the first upper electrode and being allowable to contain an impurity, wherein the capacitive element comprises the lower electrode, the capacitive insulator film, and an upper electrode comprising the first upper electrode, the second upper electrode and the third upper electrode, and wherein the second upper electrode is a bather layer for preventing the possible impurity contained in the third upper electrode from diffusing into the capacitive insulator film.