Patent ID: 6794249
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A method for fabricating a memory cell, which comprises:in a first step, patterning at least one film of an electrically conductive layer to form strip-like sections on a semiconductor material that is selected from the group consisting of a semiconductor body and a semiconductor layer; forming a doped region for a source and a doped region for a drain using a process selected from the group consisting of performing an implantation prior to the first step and diffusing dopant out of a material of the electrically conductive layer after the first step; in a second step, forming a trench having sides between the strip-like sections of the electrically conductive layer such that the doped region for the source remains at one of the sides of the trench and the doped region for the drain remains at another one of the sides of the trench; in a third step, applying a boundary layer, a memory layer and a boundary layer on top of one another over an entire surface of the semiconductor material; and in a fourth step, introducing an electrically conductive material for a gate electrode into the trench and patterning the electrically conductive material to form at least one conductor track that is provided as a word line.