Patent ID: 6119248
Filing Date: 2000-09-12
Classification: G06F

Abstract:
A computer system comprising:a processor;a memory;an error check circuit operably coupled to the memory and to the processor, the error check circuit detecting correctable errors in computer information, the error check circuit providing an error signal indicative of a detected correctable error;a register circuit including:a status register, the status register including a plurality of bit-fields, wherein the value of one of the bit-fields is responsive to the error signal;an enable register including a plurality of bit-fields, each bit-field of the plurality of bit-fields of the enable register corresponds to a bit-field of the plurality of bit-fields of the status register, wherein one of the bit-fields of the enable register is corresponding to the one of the bit-fields of the status register whose value is responsive to the error signal;wherein when the one of the bit-fields of the enable register contains a value indicating enablement, an interrupt to the processor is generated in response to the register circuit receiving the error signal.