Patent ID: 6563167
Filing Date: 2003-05-13
Classification: H01L

Abstract:
An electrically programmable and erasable memory device comprising:a substrate of semiconductor material of a first conductivity-type having a substantially flat surface portion; first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region therebetween; a first insulation layer disposed over said substrate; an electrically conductive floating gate disposed over said first insulation layer and entirely over the substrate flat surface portion, wherein the floating gate extends over a portion of the channel region and over a portion of the first region, and wherein the floating gate includes a pair of opposing raised sharp edges; a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and an electrically conductive control gate having a first portion disposed adjacent to and insulated from the floating gate and a second portion partially extending over the second insulation layer and partially over the floating gate including partially over both of the raised sharp, edges.