Patent ID: 6114747
Filing Date: 2000-09-05
Classification: H01L

Abstract:
An integrated circuit wafer, comprising:an semiconductor wafer having an outer periphery;a layer of first dielectric material formed on said semiconductor wafer wherein said first dielectric material has been removed from the region within a first distance of said outer periphery of said semiconductor wafer;a patterned layer of first conductor material formed on said layer of first dielectric material wherein said first conductor material has been removed from the region within a second distance of said outer periphery of said semiconductor wafer;a patterned layer of second dielectric material having contact holes formed on said semiconductor wafer over said patterned layer of first conductor material wherein said second dielectric material has been removed from the region within a third distance of said outer periphery of said semiconductor wafer;second conductor material filling said contact holes in said patterned layer of second dielectric material, wherein said second conductor material does not extend into the region within said third distance of said outer periphery of said semiconductor wafer; anda layer of third dielectric material formed over said patterned layer of second dielectric material and said patterned layer of second conductor material wherein said third dielectric material has been removed from the region within a fourth distance of said outer periphery of said semiconductor wafer, so that there is no first dielectric material, second dielectric material, third dielectric material, first conductor material, nor second conductor material within the region within the smaller of the first distance, second distance, third distance, or fourth distance of said outer periphery of said semiconductor wafer.