Patent ID: 7615429
Filing Date: 2009-11-10
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit field effect transistor comprising: forming a series of interchannel layers and channel layers stacked alternately upon each other on a surface of a substrate; forming an isolation trench by partially etching the interchannel layers, the channel layers and the substrate; forming a field region in the isolation trench; forming a pre-active pattern on the surface of a substrate by partially etching the remaining interchannel layers and the channel layers, to generate an etched region at opposite sidewalls of the field region; forming source/drain regions on the substrate, at opposite ends of the pre-active pattern; forming an active channel pattern comprising a plurality of tunnels and a plurality of channels from the channel layers by selectively removing the plurality of interchannel layers, to form the plurality of tunnels passing through the pre-active pattern; and forming a gate electrode in the tunnels and surrounding the channels.