Patent ID: 6807097
Filing Date: 2004-10-19
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate, the control gate of a selected memory cell presently selected to be applied an identical voltage during an ordinary read operation and a verify-read operation; a reference current source circuit configured to generate a first reference current adaptable for use during ordinary read operation and a second reference current for use during said verify-read operation for data status verification in one of writing and erasing events, said reference current source circuit including reference cells each having a transistor structure with a control gate, the control gate of a reference cell presently selected to be applied said identical voltage during said ordinary read operation and said verify-read operation; and a sense amplifier configured to compare read currents of a selected memory cell as selected during said ordinary read operation and said verify-read operation with the first and second reference currents respectively to thereby perform data detection.