Patent ID: 8084359
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor package, comprising: forming a first insulation layer pattern defining first and second openings that expose first and second pads of a semiconductor device, respectively, on the semiconductor device having the first and second pads; forming a first conductive layer pattern on the first insulation layer pattern and the first pad; forming a first external terminal on the first conductive layer pattern; forming a second insulation layer pattern defining a third opening in communication with the second opening on the first conductive layer pattern and the first insulation layer pattern, the second insulation layer pattern exposing a portion of the first external terminal; forming a second conductive layer pattern on the second insulation layer pattern and the second pad; and forming a second external terminal on the second conductive layer pattern, wherein forming the second insulation layer pattern includes: