Patent ID: 7366647
Filing Date: 2008-04-29
Classification: G06F

Abstract:
1. A method in a LSI design and development process for creating and evaluating an architecture design for an algorithm design by performing a performance evaluation of at least one bus at a high-level stage of said design and development process, said method comprising: structuring source code describing the algorithm design in a general purpose high-level programming language by isolating elements of said source code into elements representing hardware units and elements representing software units creating the architecture design of an LSI; creating an evaluation function for counting data traffic that occurs on said at least one bus, the bus being a part of the source code realizing the data traffic between said elements representing hardware units and software units; sequentially reading in the source code line by line while effecting syntax analysis; determining whether the source code is to be modified based on whether a line of source code represents writing data to variables that are defined in advance and are loaded onto the bus to be evaluated; modifying at least one element of said source code based on an implementation of said evaluation function; and performing said performance evaluation by simulating said modified source code elements and counting said data traffic on the bus, wherein said performance evaluation is used to modify the architecture design of the LSI.