Patent ID: 6441314
Filing Date: 2002-08-27
Classification: H01L,H05K,Y10T

Abstract:
A substrate of multilayered structure having a plurality of sets of an insulation layer and a patterned wiring line layer, the substrate having one face for mounting a semiconductor element thereon, the face being provided with pads to be bonded to an electrode terminal of the semiconductor element, and the other face provided with pads to be bonded to an external connection terminal, and each insulation layer having vias piercing therethrough so as to connect a patterned wiring line of the wiring line layer on one side of the insulation layer with a patterned wiring line of the wiring line layer, a pad to be bonded to the electrode terminal of the semiconductor element, or a pad to be bonded to the external connection terminal on the other side of the insulation layer, wherein:the wiring line layers and the insulation layers are alternately laminated from the face for mounting a semiconductor element to the face provided with pads to be bonded to an external connection terminal, the surfaces of the pads to be bonded to an electrode terminal of the semiconductor element are in a first plane which is common to the pad surfaces and the surface of the insulation layer, and each via has a bottom and an opening, the bottom being formed from either the pad to be bonded to an electrode terminal of the semiconductor element or the patterned wiring line of the wiring line layer located at one side of the insulation layer through which the via pierces, the side being closer to the pad to be bonded to an electrode terminal of the semiconductor element, and the opening being located at the other side of the insulation layer through which the via pierces, and the via being connected, at the side of the opening, to either a patterned wiring line of the wiring line layer at the other side of the insulation layer or a pad to be bonded to the external connection terminal.