Patent ID: 8723291
Filing Date: 2014-05-13
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device, comprising: a fuse wiring extending to a first direction and cut by passing beyond a predetermined current value; a first electrode pad connected to one side of the fuse wiring; a second electrode pad connected to the other side of the fuse wiring; a first multilayer structure including first vias and first wirings connected with each other, the multilayer structure extending in the first direction of a planar view; a second multilayer structure including second vias and second wirings connected with each other, the second multilayer structure extending in the first direction; a third multilayer structure including third vias and third wirings connected with each other, the third multilayer structure extending in the first direction; and a fourth multilayer structure including fourth vias and fourth wirings connected with each other, the fourth multilayer structure extending in the first direction, wherein the fuse wiring is disposed between the first multilayer structure and the second multilayer structure in a second direction of a planar view perpendicular to the first direction, wherein the fuse wiring, the first multilayer structure and the second multilayer structure are disposed between the third multilayer structure and the fourth multilayer structure in the second direction, wherein a first edge of the first multilayer structure diposed on a side of the first electrode pad and a second edge of the second multilayer structure disposed on the side of the first electrode pad are connected to the first electrode pad, wherein a third edge of the third multilayer structure disposed on a side of the second electrode pad and a fourth edge of the fourth multilayer structure disposed on the side of the second electrode pad are connected to the second electrode pad, wherein a fifth edge of the first multilayer structure disposed on the side of the second electrode pad and a sixth edge of the second multilayer structure disposed on the side of the second electrode pad are not connected to the second electrode pad, and wherein a seventh edge of the third multilayer structure disposed on the side of the first electrode pad and an eighth edge of the fourth multilayer structure disposed on the side of the first electrode pad are not connected to the first electrode pad.