Patent ID: 6512699
Filing Date: 2003-01-28
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of memory cells each comprising a first transistor having a first electrode, a second electrode, a gate electrode and a floating gate electrode located between the gate electrode and a first gate oxide film; a plurality of first data lines each connected to the first electrode of the first transistor; a second data line; a decoder for generating a plurality of selection signals having voltage levels respectively determined in response to address information; and a plurality of second transistors each having a third electrode electrically connected to one of the first data lines, a fourth electrode electrically connected to the second data line, a gate electrode to which one of the selection signals is inputted, and a second gate oxide film, the second transistor being used to access the memory cells; wherein the selection signals have a predetermined voltage level when a high voltage level, which is higher than a power supply voltage level, is applied to a selected gate electrode of the memory cell and wherein the gate electrode of each of the second transistors has a first layer formed with the same material to that of the gate electrode of the first transistor, and a second layer formed with the same material to that of the floating gate electrode of the first transistor, the first layer being electrically connected to the second layer.