Patent ID: 8516185
Filing Date: 2013-08-20
Classification: G06F,G11C

Abstract:
1. A memory module comprising: a plurality of memory devices; a controller configured to receive control information from a system memory controller and to produce module control signals; and a plurality of circuits configured to receive the module control signals, each circuit of the plurality of circuits having a first bit width and operatively coupled to at least two corresponding memory devices of the plurality of memory devices, the at least two corresponding memory devices each having a second bit width smaller than the first bit width, each circuit of the plurality of circuits comprising at least one write buffer and at least one read buffer and configured to selectively allow data transmission between the system memory controller and at least one selected memory device of the at least two corresponding memory devices in response to the module control signals, and to selectively isolate at least one other memory device of the at least two corresponding memory devices from the system memory controller in response to the module control signals, wherein each circuit of the plurality of circuits is operable, in response to the module control signals, to actively drive write data from the system memory controller to the at least one selected memory device of the at least two corresponding memory devices through the at least one write buffer, and to receive and drive read data from the at least one selected memory device of the at least two corresponding memory devices to the system memory controller through the at least one read buffer, wherein the circuits of the plurality of circuits are distributed at corresponding positions separate from one another.