Patent ID: 6487119
Filing Date: 2002-11-26
Classification: G11C,H01L

Abstract:
A non-volatile Read Only Memory, comprising:memory cell transistors each of which is constituted such that the area between the gate electrode and one impurity area and the area between said gate electrode and the other impurity area take offset structure or non-offset structure in accordance with the value of stored data; a row selection line that applies a voltage to said gate electrodes in said memory cell transistors belonging to same row; a first column selection line that applies a voltage to said one impurity area in said memory cell transistors belonging to same column; a second column selection line that applies a voltage to said other impurity area in said memory cell transistors belonging to same column; and a reading circuit which applies a read electric potential to said row selection line selected, and reads said stored data by detecting the on/off status of said memory cell transistors when high electric potential is applied to said first column selection line and low electric potential is applied to said second column selection line, and by detecting the on/off status of said memory cell transistors when low electric potential is applied to said first column selection line and high electric potential is applied to said second column selection line.