Patent ID: 8901955
Filing Date: 2014-12-02
Classification: H03K

Abstract:
1. A circuit comprising: a first buffer configured to receive an incoming signal and to generate a first output signal based on the incoming signal; a second buffer configured to receive the incoming signal and to generate a second output signal based on the incoming signal, the second buffer exhibiting hysteresis with a lower threshold and an upper threshold; and an output block configured to receive the first output signal and the second output signal and to generate a third output signal based on the first and second output signals, the output block being configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal, wherein the first buffer exhibits hysteresis with a lower threshold and an upper threshold, and the upper threshold of the second buffer is more positive than the upper threshold of the first buffer, and wherein the lower threshold of the second buffer is more negative than the lower threshold of the first buffer.