Patent ID: 7148578
Filing Date: 2006-12-12
Classification: H01L

Abstract:
1. A semiconductor multi-chip package comprising: a package substrate including a surface having a plurality of bonding tips formed thereon; and two or more semiconductor chips mounted on the substrate surface, the two or more semiconductor chips each including: a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on the semiconductor substrate; a pad-rearrangement pattern directly contacting the bond pad-wiring pattern, the pad-rearrangement pattern including bond pads disposed over at least a part of the cell region; and an insulating layer formed on the pad-rearrangement pattern, wherein the bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate, wherein the bond pads included with the pad-rearrangement pattern are exposed through the insulating layer, wherein each bonding tip is electrically connected to a corresponding one of the bond pads.