Patent ID: 6442197
Filing Date: 2002-08-27
Classification: G11B

Abstract:
An architecture, using ascertained filter coefficients of an FIR filter, implementing synchronization circuitry used with filtering or equalization of a sampled input signal and a sinusoidal-like preamble, the architecture structured to estimate the phase at the FIR filters output, comprising:a first circuit, having an input and an output, for calculating and outputting an estimate of the phase shift of the FIR filter, and a second circuit connected to said first circuit, having an input and an output, incorporating a phase detector and summing circuitry for determining the phase error of the input signal of said second circuit and summing said phase error with said estimated phase shift from said first circuit as said output of said second circuit, delivering a signal PDB_PHERR from said second circuit to a multiplexer for selection prior to transmission to a feedback circuit.