Patent ID: 6365513
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method for fabricating an electronic device, comprising the steps of:forming a field effect transistor (FET) on a first surface of a substrate; forming a via hole through the first surface of the substrate; forming a conductive layer over the first surface of the substrate and a side face of the via hole, the conductive layer including an extended interconnection in a region where the via hole is formed, for testing electrical characteristics of the FET, the extended interconnection being connected with a drain/source region of the FET; testing electrical characteristics of the FET by using the extended interconnection; and thinning the substrate by removing a second surface portion of the substrate which is opposite to the first surface such that a portion of the conductive layer formed on the side face of the via hole exposes itself, wherein the step of testing electrical characteristics of the FET is performed prior to the step of thinning the substrate.