Patent ID: 7619928
Filing Date: 2009-11-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first memory cell including a floating body comprising a gate connected to a word line, a first electrode connected to a bit line, and a second electrode connected to a common source line to store data; a second memory cell including a floating body comprising a gate connected to the word line, a first electrode connected to an inverted bit line, and a second electrode connected to the common source line to store phase-inverted data of the data; a controller for applying a first voltage to the common source line, applying a negative second voltage to the word line, applying a third voltage as a first sense enable control voltage and applying the first voltage as a second sense enable control voltage during a first write period of a write operation, and for applying a fourth voltage to the common source line and applying the first voltage to the word line during a second write period of the write operation; and a sensing portion for amplifying the bit line and the inverted bit line to the third voltage or the first voltage, respectively, during the first write period in response to the first and second sense enable control voltages wherein the first through fourth voltages being equal to or higher than a ground voltage.