Patent ID: 6281452
Filing Date: 2001-08-28
Classification: H01L,H05K,Y02P,Y10T

Abstract:
A structure for mounting semiconductor chips thereon, the structure comprising:a destination carrier having a top surface with a first array of conductive contacts thereon;a multilayer thin film having a bottom surface connected to the top surface of the destination carrier, the bottom surface having a second array of conductive contacts thereon corresponding to and aligned with the first array of conductive contacts;a spacer of nonconductive, compliant material interposed between and in contact with the bottom surface of the thin film and the top surface of the destination carrier;the spacer having opposite planar surfaces positioned to oppose the thin film and the destination carrier, respectively;the spacer further having a pattern of through-vias extending between the opposite planar surfaces of the spacer to terminate in opposite ends and opposite openings on respective opposite planar surfaces;the pattern of through-vias selected to correspond to the first and second aligned arrays of conductive contacts, the conductive contacts of either of the arrays acting as registration guides for alignment of the spacer with the arrays; andsolder connections extending in the through-vias, each of the solder connections connecting one of the contacts of the first array with a corresponding one of the contacts of the second array, the solder connections being formed by at least one of heat and pressure;whereby the spacer redistributes localized regions of pressure which may form on the thin film during formation of the solder connections.