Patent ID: 7620746
Filing Date: 2009-11-17
Classification: G06F

Abstract:
1. A direct memory access (DMA) controller comprising: a transmit control circuit configured to read first DMA data from an address space in a host and to provide the first DMA data to either an offload engine in the DMA controller or to an interface circuit, dependent on a channel to which the DMA transfer is assigned; and the offload engine coupled to receive the first DMA data from the transmit control circuit, wherein the offload engine is configured to perform at least a first operation on the first DMA data to produce a result, wherein the offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine; and a receive control circuit coupled to the offload engine to receive the result, wherein the receive control circuit is configured to write the result to the address space in the host at a location specified by a DMA descriptor data structure that describes the DMA transfer, and wherein the receive control circuit is further configured to write data received from the interface circuit to the address space.