Patent ID: 6477676
Filing Date: 2002-11-05
Classification: G01R,G11C

Abstract:
An intermediate stage of a multi-stage algorithmic pattern generator, which is composed of:a plurality of input address registers which hold respective input addresses, and a plurality of input data registers which hold respective input data words, a memory address generator, coupled to said input address registers, which generates a series of memory addresses by selecting bits from said input addresses; a memory, coupled to said memory address generator, which sequentially receives each memory address in said series, and in response, sends a corresponding series of translated addresses to a memory output; multiple output address registers, coupled to said memory output, each of which stores a respective translated address in said series; a date modifying circuit, coupled to said input data registers, which generates output data words by performing selectable operations on said input data words; output data registers, coupled to said data modifying circuit, which store said output data words; and, a control register, coupled to both said data modifying circuit and said memory address generator, that store programmable control signals which are specified in a command, and wherein said data modifying circuit performs said selectable operations in response to one subset of said stored control signals while said memory address generator generates said series of memory addresses in response to another subset of said stored control signals.