Patent ID: 6194765
Filing Date: 2001-02-27
Classification: H01L,Y10S

Abstract:
An integrated electrical circuit, comprising:a semiconductor substrate having a surface;a memory cell disposed in a region of said surface of said semiconductor substrate and having inverters electrically connected to one another, said inverters each containing two complementary MOS transistors each having a source, a drain and a channel, and said channel of each of said two complementary MOS transistors having different conductivity types, said memory cell, including:a first doped semiconductor layer disposed on said semiconductor substrate;a second doped semiconductor layer disposed on said first doped semiconductor layer;a third doped semiconductor layer disposed on said second doped semiconductor layer;a fourth doped semiconductor layer disposed on said third doped semiconductor layer;a fifth doped semiconductor layer disposed on said fourth doped semiconductor layer;and a sixth doped semiconductor layer disposed on said fifth doped semiconductor layer, said first doped semiconductor layer, said second doped semiconductor layer, said third doped semiconductor layer, said fourth doped semiconductor layer, said fifth doped semiconductor layer and said sixth doped semiconductor layer defining a layer sequence doped alternately with opposite conductivity types;said layer sequence having a grid of rectangular trenches formed therein, said grid of rectangular trenches reaching down into said semiconductor substrate and said grid of rectangular trenches defining at least two layer assemblies each having side walls;said at least two layer assemblies each having a further trench formed therein, said further trench reaching down into said third doped semiconductor layer and connecting two mutually opposite rectangular trenches of said grid of rectangular trenches to one another in a respective layer assembly;said inverters are disposed on mutually opposite side walls of said side walls of said at least two layer assemblies, said first doped semiconductor layer, said second doped semiconductor layer and said third doped semiconductor layer in each case forming said source, said channel and said drain of one of said two complementary MOS transistors of a respective inverter and said fourth doped semiconductor layer, said fifth doped semiconductor layer and said sixth doped semiconductor layer in each case forming said source, said channel and said drain of another of said two complementary MOS transistors of the respective inverter;two selection transistors each having a source, a channel and a drain and disposed in each case on a side of the respective layer assembly which is remote from said inverters, said source, said channel and said drain of each of said two selection transistors formed by said third doped semiconductor layer, said fourth doped semiconductor layer and said fifth doped semiconductor layer; andsaid further trench disposed in said layer sequence in each case formed between one of said two selection transistors and one of said inverters.