Patent ID: 8671266
Filing Date: 2014-03-11
Classification: G06F

Abstract:
1. A processor comprising: two memories, each comprising a read port, a write port, and each memory separately comprising a first capacity A, wherein the write port of both memories is directly coupled to a direct memory access (DMA) interface for selected loading of data to both memories; two X stage execution units, each coupled to a corresponding read port of the two memories to receive a source operand from a first memory location specified by a program and coupled to the corresponding write port of the two memories to write an X stage result value to a second memory location specified by the program; two staging register files, each comprising a staging read port, a staging write port, and each staging register file separately comprising a second capacity B, B<A, wherein each staging write port is coupled to a corresponding X stage execution unit for selected writing of the X stage result value to a staging register file first location specified by the program; and two Y stage execution units, each coupled to a corresponding staging read port of the two staging register files to receive a source operand from the staging register file first location specified by the program and coupled to the corresponding staging write port of the two staging register files to write a Y stage result value to a staging register file second location specified by the program.