Patent ID: 8119456
Filing Date: 2012-02-21
Classification: H01L

Abstract:
1. A method of having an electronic package including a semiconductor chip having a plurality of electrically connected layers arranged on a substrate and a plurality of bond pads positioned on an upper surface of said semiconductor chip, wherein said method comprises equipping said electronic package with structure extending between said plurality of bond pads and said substrate for protecting electrical connections and components contained therein from an ingress of moisture and contaminants, wherein said protective structure includes an edge seal and a crack stop each forming a continuous ring-shaped arrangement extending in a mutually spaced relationship about the periphery of said plurality of bond pads, wherein said edge seal and said crack stop extend peripherally within the area confined within an array of said plurality of bond pads arranged in spaced relation to each other forming a perimeter of said plurality of bond pads, and said peripheral crack stop extends internally spaced in relation to the ring-shaped edge seal.