Patent ID: 8773890
Filing Date: 2014-07-08
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first cell array comprising first memory cells and first reference cells, each of the first memory cells comprising a variable resistance element; a second cell array located adjacent to the first cell array in a first direction, the second cell array comprising second memory cells and second reference cells, each of the second memory cells comprising a variable resistance element; a third cell array located adjacent to the first cell array in a second direction crossing the first direction, the third cell array comprising third memory cells and third reference cells, each of the third memory cells comprising a variable resistance element; a fourth cell array located adjacent to the third cell array in the first direction, the fourth cell array comprising fourth memory cells and fourth reference cells, each of the fourth memory cells comprising a variable resistance element; a first word line electrically connected to a part of the first memory cells and the second memory cells; a second word line electrically connected to the other part of the first memory cells and the second memory cells; a first reference word line electrically connected to the first reference cells and the second reference cells; a third word line electrically connected to a part of the third memory cells and the fourth memory cells; a fourth word line electrically connected to the other part of the third memory cells and the fourth memory cells; a second reference word line electrically connected to the third reference cells and the fourth reference cells; a first select line electrically connected to a part of the first memory cells and the third memory cells; a second select line electrically connected to the other part of the first memory cells and the third memory cells; a third select line electrically connected to a part of the second memory cells and the fourth memory cells; and a fourth select line electrically connected to the other part of the second memory cells and the fourth memory cells, wherein the first word line, the second reference word line, the first select line, and the third select line are simultaneously selected.