Patent ID: 8201013
Filing Date: 2012-06-12
Classification: G06F,G11C,Y02D

Abstract:
1. A memory controller transmitting and receiving data to and from an external memory in an external region of a system large scale integration (LSI) including the memory controller, the memory controller comprising: a delay control section including a delay holding section, coupled to an external terminal of the system LSI and deciding a set value indicative of a determined delay amount based on a result of a comparison between a test data transmitted to the external memory and test data received from the external memory to output the set value from the external terminal to the external memory in the external region of the system LSI; a taking-in section receiving the set value in the external memory; and a delay adjustment section receiving data from the external memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section, wherein the set value is stored in both the delay holding section of the memory controller and the external memory in the external region of the system LSI including the memory controller.