Patent ID: 6437589
Filing Date: 2002-08-20
Classification: G01R

Abstract:
A semiconductor device test circuit system circuit for testing a system circuit on a semiconductor device, said semiconductor device test circuit comprising:n number of test flip-flop circuits, each including a racing prevention circuit which cause at least one clock delay to output a test signal from a test signal output terminal (SO) as distinguished from an output terminal Q; and an additional flip-flop circuit dedicated for testing, wherein said test flip-flop circuits constitute a portion of said system circuit, a test signal output terminal of a kth (k is 1 through nâˆ’1) test flip-flop circuit is connected to a test signal input terminal of the (k+1)th test flip-flop terminal, and the test signal outputted from the nth test flip-flop circuit is inputted to said additional flip-flop circuit and outputted from an output terminal Q of said additional flip-flop circuit within a testing period of n+1 clocks.