Patent ID: 7032192
Filing Date: 2006-04-18
Classification: G06F

Abstract:
1. A method for performing latch mapping, comprising: receiving an initial circuit model representing a first circuit and a second circuit; generating an initial latch mapping for the initial circuit model; repeating the following until a next latch mapping is at least substantially similar to a current latch mapping to yield a final latch mapping: constructing a current circuit model according to a previous circuit model; establishing one or more current potentially equivalent node sets associated with the current circuit model in accordance with one or more previous potentially equivalent node sets, each potentially equivalent node set comprising one or more potentially equivalent nodes; validating equivalence of the one or more current potentially equivalent node sets; and verifying a current latch mapping in accordance with the validated one or more current potentially equivalent node sets to generate a next latch mapping; and reporting the final latch mapping.