Patent ID: 7683697
Filing Date: 2010-03-23
Classification: H03K

Abstract:
1. A circuit comprising: a circuit input for receiving a power mode control signal to indicate a low power mode of the circuit; a plurality of non-inverting buffers to provide buffering for the power mode control signal, a first of the non-inverting buffers coupled to the circuit input for receiving the power mode control signal and having an output connected to an input of each of two or more of the plurality of non-inverting buffers, each of the two or more of the plurality of non-inverting buffers having an output connected to an input of additional non-inverting buffers to form a fanout signal distribution network; each non-inverting buffer comprising an even number of serial-connected inverting gates, at least a portion of the plurality of non-inverting buffers providing respective outputs of the fanout signal distribution network, each output of the fanout signal distribution network having a valid logic state in the low power mode; a first voltage terminal for receiving a first voltage; and a second voltage terminal for receiving a second voltage, the second voltage having a voltage value different from the first voltage in the low power mode, wherein at least two of the non-inverting buffers each comprises a first inverting gate connected to the second voltage terminal and providing an output thereof and a second inverting gate connected to the first voltage terminal, an input of the first inverting gate is connected to an output of the second inverting gate.