Patent ID: 6756819
Filing Date: 2004-06-29
Classification: H04L

Abstract:
A synchronization circuit comprising;a first flip-flop which has a first clock input terminal inputting an input signal, a first output terminal outputting a first output signal based on the input signal, a second output terminal outputting a second output signal based on the input signal and a first data input terminal inputting the second output signal; a second flip-flop which has a second clock input terminal inputting a clock signal, a reset terminal inputting a reset signal, a third output terminal outputting a third output signal based on the clock signal and the reset signal, a fourth output terminal outputting a fourth output signal based on the clock signal and the reset signal and a second data input terminal inputting the fourth output signal; a third flip-flop which has a third clock input terminal inputting the third output signal of which voltage level is reversed, a fifth output terminal outputting a fifth output signal based on the reversed third output signal, a sixth output terminal outputting a sixth output signal based on the reversed third output signal and a third data input terminal inputting the sixth output signal; and a logical circuit which generates the reset signal using the first output signal and the fifth output signal.