Patent ID: 9092582
Filing Date: 2015-07-28
Classification: G06F

Abstract:
1. A serial interface comprising: a clock node; a first bidirectional data port; a second bidirectional data port; and shift register circuitry coupled to the first bidirectional data port and the second bidirectional data port, the shift register circuitry including a first shift register to load data onto the first bidirectional data port, a second shift register to receive data from the first bidirectional data port, a third shift register to load data onto the second bidirectional data port, and a fourth shift register to receive data from the second bidirectional data port, wherein the shift register circuitry is configured such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift data in each of the first shift register, second shift register, third shift register and fourth shift register.