Patent ID: 9171791
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: a wiring substrate having a first insulating layer having a first main surface and a second main surface opposite the first main surface, a solder resist layer formed over the first main surface of the first insulating layer, a plurality of through-hole wiring portions which penetrate the first main surface to the second main surface of the first insulating layer, and a plurality of wirings formed over the first main surface of the first insulating layer and electrically connected to the plurality of through-hole wiring portions, respectively, wherein parts of the plurality of through-hole wiring portions disposed over the first main surface of the first insulating layer are covered with the solder resist layer; and a semiconductor chip having an obverse surface over which a plurality of electrode pads are formed and a reverse surface opposite the obverse surface, wherein a plurality of openings are formed in the solder resist layer such that a part of each of the plurality of wirings is exposed from each of the plurality of openings, wherein the part of each of the plurality of wirings exposed from each of the plurality of openings is an electrode terminal, wherein the semiconductor chip is mounted over the first main surface of the first insulating layer of the wiring substrate such that the obverse surface thereof faces the first main surface and each of the plurality of electrode pads of the semiconductor chip is electrically connected to each of the plurality of electrode terminals of the wiring substrate via a metal bump, wherein a plurality of first electrode terminals are arranged at a first region corresponding to a peripheral portion of the first main surface of the first insulating layer of the wiring substrate, wherein a plurality of second electrode terminals are arranged at a second region located inside the first region and corresponding to a vicinity of a central portion of the first main surface of the first insulating layer of the wiring substrate, wherein parts of the plurality of through-hole wiring portions electrically connected to parts of the plurality of wirings of which the plurality of the first electrode terminals are composed are disposed in a third region between the first and second regions, and wherein, a number of the plurality of first electrode terminals is larger than a number of the plurality of second electrode terminals.