Patent ID: 6397365
Filing Date: 2002-05-28
Classification: G06F

Abstract:
An apparatus for detection and correction of single and multi-bit memory errors in a memory system comprising:an array of memory modules for storing a plurality of data slices; a redundant memory module for storing a checksum, said redundant memory having at least as much bit storage space as each memory module of said array of memory modules; an array of error correction code generators for generating an error correction code for each of said data slices and for generating an error correction code for said checksum; and an array of exclusive-or operators for forming said checksum from the bits of said data slices, wherein: the checksum comprises space for a number of bits corresponding to a number of bits in each said slice, each bit in each said slice having a position in an order of bits; and each bit in said checksum is determined by performing an ex-or operation on all bits in the same position in the order of bits of each said slice, thereby providing said checksum with sufficient information to enable correction of a data slice with a multi-bit error, wherein said checksum is XOR-ed with the data of all but one of said data slices to reconstruct data stored in the one of said data slices that is not XOR-ed with said checksum.