Patent ID: 6230282
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A computer system comprising:a first computer having a first memory;a second computer having a second memory and a buffer, said first and second memories being updated by a memory update comprising an address specifying a location and data to be written to said first and second memories at said location;an interface for providing said second computer with a copy of each memory update received by said first memory;wherein, upon receiving each of said copies of said memory updates, said second computer (1) generates a recovery memory update corresponding to that copy of said memory update, said recovery memory update comprising the data stored in said second memory at the address specified in said first memory update and the address specified in said received copy, (2) updates said second memory using said copy of said memory update, and (3) writes said recovery memory update into said buffer if, and only if, said buffer does not contain one of said recovery memory updates for said address in said recovery memory update,wherein said second computer empties said buffer upon the receipt of a checkpoint interval signal, andwherein said second computer updates said second memory with said recovery memory updates stored in said buffer in response to the receipt of an error signal, said recovery memory updates being performed in the order said recovery memory updates were stored in said buffer.