Patent ID: 6830972
Filing Date: 2004-12-14
Classification: H01L

Abstract:
A method of forming memory circuitry comprising a memory array having a plurality of memory capacitors and comprising peripheral memory circuitry operatively configured to write to and read from the memory array, comprising:forming a dielectric well forming layer over a semiconductor substrate; removing a portion of the well forming layer effective to form at least one well within the well forming layer, the well having a well base; forming an array of capacitor storage node openings through the well base into the well forming layer over storage node contact locations; supporting an array of storage node capacitor electrodes within the well and base openings therein by the well forming layer, the capacitor storage node electrodes respectively comprising a portion which has a container shape, the container shape portion being formed to be received only partially within the capacitor storage node openings of the well forming layer through and beneath the well base; and forming the peripheral memory circuitry laterally outward of the well forming layer memory array well.