Patent ID: 8015464
Filing Date: 2011-09-06
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. logic circuitry having a certain order of logic stimulus inputs and a certain order of logic response outputs; B. a scan in lead and a scan out lead; and C. a scan path of serially connected scan cells, the scan path having an input connected to the scan in lead, an output connected to the scan out lead, a certain order of scan stimulus parallel outputs connected from the scan cells to the certain order of logic stimulus inputs free of any blocking circuits, and a certain order of scan response parallel inputs connected to the scan cells from the certain order of logic response outputs, the scan path being divided into segments of scan cells, each segment having an equal number of scan cells, stimulus parallel outputs, and response parallel inputs, and each segment maintaining the certain order of stimulus parallel outputs and response parallel inputs, the scan path segments including: