Patent ID: 6574140
Filing Date: 2003-06-03
Classification: G11C,H01L

Abstract:
An EEPROM cell comprising:a bulk region of a first conductivity type; a first region, of a second conductivity type opposite said first conductivity type; formed within said bulk region; a second region, of said second conductivity type, formed within said bulk region; a source select transistor channel region located in said bulk region adjacent to said first region of said second conductivity type; a memory transistor channel region located within said bulk region between said source select transistor channel region and said second region; a source select transistor control gate insulated from said source select transistor channel region; a memory transistor floating gate insulated from said memory transistor channel region; a memory transistor control gate capacitively coupled to said floating gate and formed of the same layer of material and connected to said source select transistor control gate; a thin tunnel dielectric region located between at least a portion of said floating gate and said memory transistor channel region; and circuitry for controlling the operation of the memory array, including: selection circuitry for selecting one or more of source lines with associated ones of said source select transistors; and bias circuitry for biasing a selected one or more of said memory cells associated with said selected source lines in order to cause, for each said selected memory cell, electrons to tunnel between said memory transistor channel region and said floating gate for programming and erasing.