Patent ID: 6147538
Filing Date: 2000-11-14
Classification: H01L,H03K

Abstract:
An integrated circuit, comprising:a semiconductor substrate with a bond pad for a reference supply voltage;a bus for a first supply voltage;a signal bond pad for connecting to an external signal;internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors, wherein a signal line from the internal circuitry is connected to the first signal bond pad;ESD circuitry connected between the signal pad and the reference supply voltage bond pad, wherein the ESD circuitry comprises:a first substrate region in the semiconductor substrate enclosed by a highly doped region;a first MOS transistor of a first conductivity type with a backgate in the first substrate region, a first source/drain connected to the signal bond pad, a second source/drain connected to the reference supply voltage bond pad, and a control gate connected to the highly doped region;a complimentary triggering MOS transistor of a second conductivity type with a first source/drain connected to the signal bond pad, a second source/drain connected to the highly doped region, and a control gate; andcontrol circuitry operable to provide a control signal to the control gate of the complimentary triggering MOS transistor in response to an ESD zap applied to the first signal bond pad, wherein the control circuitry comprises a capacitor with a first plate connected to the reference supply bond pad and a second plate connected to the control gate of the complimentary triggering MOS transistor and a resistor with one end connected to the first signal bond pad and another end connected to the second plate of the capacitor.