Patent ID: 8958231
Filing Date: 2015-02-17
Classification: G09B,G11C

Abstract:
1. A memory device comprising: a memory cell, a first data signal line, and a second data signal line, the memory cell comprising: wherein one of the first source and the first drain is electrically connected to the first data signal line, wherein the first transistor has an off-state current per micrometer of channel width of lower than or equal to 10 aA, wherein one of the second source and the second drain is electrically connected to the first data signal line, wherein the second gate is electrically connected to the other of the first source and the first drain, wherein the third transistor has a conductivity type opposite to that of the second transistor, wherein one of the third source and the third drain is electrically connected to the second data signal line, wherein the other of the third source and the third drain is electrically connected to the other of the second source and the second drain, wherein the third gate is electrically connected to the other of the first source and the first drain, wherein the fourth gate is electrically connected to the other of the second source and the second drain, and the other of the third source and the third drain, wherein one of the fifth source and the fifth drain is electrically connected to the first data signal line, wherein the fifth gate is electrically connected to the other of the first source and the first drain, wherein the sixth transistor has a conductivity type opposite to that of the fifth transistor, wherein one of the sixth source and the sixth drain is electrically connected to the other of the fifth source and the fifth drain, wherein the sixth gate is electrically connected to the other of the first source and the first drain, and wherein the seventh gate is electrically connected to the other of the fifth source and the fifth drain and one of the sixth source and the sixth drain.