Patent ID: 7042251
Filing Date: 2006-05-09
Classification: H03D,H03K,H03L

Abstract:
1. A differential logic gate, comprising: a first power rail and a second power rail for providing power to said differential logic gate; a first input node for receiving a first input signal; a second input node for receiving a second input signal, said second input signal being the logic complement of said first input signal; a third input node for receiving a third input signal; a fourth input node for receiving a fourth input signal, said fourth input signal being the logic complement of said third input signal; a first output node for producing a first output signal; a second output node for producing a second output signal; a first plurality of series connected transistors respectively responsive to said first input node and said third input node; a first pass device responsive to said second input node; a second pass device responsive to said fourth input node, said first and second pass devices being coupled in parallel; a first pull-up device coupling said first plurality of series connected transistors to said first power rail; and a second pull-up device coupling said first and second pass devices to said first power rail; wherein said first output signal is the logical AND of said first and third input signals, and is further the logical NOR of said second and fourth input signals; wherein said second output signal is the logical OR of said second and fourth input signals, and is further the logical NAND of said first and third input signals wherein the junction of said first pull-up device and said first plurality of series connected transistors is said second output node; and wherein the junction of said second pull-up device, first pass device, and second pass device is said first output node.