Patent ID: 7651912
Filing Date: 2010-01-26
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a gate insulating film on a first upper surface of a semiconductor substrate, the gate insulating film having a second upper surface; forming a floating gate electrode layer on the gate insulating film, the floating gate electrode layer having a third upper surface; forming a trench in the floating gate electrode layer, the gate insulating film and the substrate in a predetermined direction, thereby dividing each of the floating gate electrode layer and the gate insulating film into a plurality of first divided regions; forming an element isolation insulating film in the first divided regions so that the element isolation insulating film including a silicon oxide film has a fourth upper surface located lower than the third upper surface of the floating gate electrode layer and higher than the second upper surface of the gate insulating film; forming an intergate insulating film so that the floating gate electrode layer and the element isolation insulating film are covered with the intergate insulating film, the intergate insulating film having a silicon oxide film layer; forming a control gate electrode layer on the intergate insulating film; removing the control gate electrode layer in an intersecting direction intersecting the predetermined direction, thereby dividing the control gate electrode layer into a plurality of second divided regions; etching the intergate insulating film and the element isolation insulating film in the second divided regions when a selectivity between the floating gate electrode layer and the intergate insulating film is in a range of 1:1.5 to 1:2; and removing the floating gate electrode layer located in the second divided regions.