Patent ID: 9160280
Filing Date: 2015-10-13
Classification: H03F,H04B

Abstract:
1. In a memory polynomial (MP) based digital predistorter (DPD) connected to a power amplifier, wherein the power amplifier has a feedback loop for inputting amplifier output parameters to the DPD, an MP based digital predistortion method, comprising the steps of: estimating an optimally small DPD memory length, L, and an optimally low nonlinearity order, K, wherein said estimating step further comprises the step of executing a l where, J i CAT is a complexity-accuracy tradeoff (CAT) cost function, ∥P i ∥ 0 is the zero-norm of a particle's position vector, defined as and, where, d(n) is a desired output signal used to evaluate accuracy of the estimation, e(n) is a difference between an estimated output signal and the desired output signal, α is a regularization parameter used for scaling the zero-norm modifier part of the cost function, and N is a number of samples used for a training block of said LP-PSO procedure; setting said DPD with said optimally small DPD memory length L and said optimally low nonlinearity order K; and wherein said optimally small memory length L and said optimally low nonlinearity order K improves efficiency of the DPD in linearizing an output signal of the power amplifier.