Patent ID: 6697445
Filing Date: 2004-02-24
Classification: H03L

Abstract:
An apparatus for reducing jitter in a phase-locked loop circuit, comprising:(a) a phase detector circuit that is arranged to produce an error signal in response to a phase difference between an input signal and a feedback signal; (b) a composite filter circuit that is arranged to produce a composite signal that is in response to the phase difference, the composite filter circuit further comprising an integrator circuit and a stability filter circuit; (c) a gain circuit that is arranged to produce an output signal in response to the composite signal, wherein the output signal corresponds to a scaled version of the composite signal; and (d) an oscillator circuit that is arranged to produce an oscillator signal in response to the output signal, wherein the oscillator signal includes a corresponding phase that is employed as the feedback signal to the phase detector circuit so that jitter is reduced.