Patent ID: 6950973
Filing Date: 2005-09-27
Classification: G01R

Abstract:
1. An apparatus comprising: a first dynamic logic circuit having an output node on which a scan value to be used for a scan is provided during the scan, the first dynamic logic circuit having its precharge and evaluate operations suspended to receive and retain the scan value during the scan; a second dynamic logic circuit having an input coupled to the output node of the first dynamic logic circuit and precharge and evaluate operations of the second dynamic logic circuit controlled by a first clock, wherein the first dynamic logic circuit and the second dynamic logic circuit are responsive during a first dynamic phase of functional operation; and one or more third dynamic logic circuits, wherein one of the third dynamic logic circuits has an input coupled to receive a dynamic logic signal which is responsive to the second dynamic logic circuit and precharge and evaluate operations of the third dynamic logic circuit or circuits controlled by a second clock, wherein the third dynamic logic circuit or circuits are responsive during a second dynamic phase of functional operation, and wherein the scan value is used to initiate the scan that is propagated through second and third dynamic logic circuits and an output of a final third dynamic circuits is sampled in response to the scan value during scan.