Patent ID: 6342422
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of:forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an first dielectric layer over said first silicon layer; removing a portion of said gate insulator layer, of said first silicon layer, and of said first dielectric layer for defining a gate region; doping said substrate to form an extended source/drain junction in said substrate under a region uncovered by said gate region; forming an undoped spacer structure on sidewalls of said gate region; removing said first dielectric layer; forming a second silicon layer on said semiconductor substrate and on said first silicon layer, said second silicon layer being an undoped silicon layer; and doping said second silicon layer to provide dopants for forming a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; forming a metal layer over said semiconductor substrate; performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and in said second silicon layer to form said source/drain junction, and to form a metal suicide layer on said second silicon layer; and removing unreacted portions of said metal layer.