Patent ID: 6365929
Filing Date: 2002-04-02
Classification: H01L

Abstract:
An EEROM comprising:(a) a semiconductor substrate having a surface: (b) a doped memory diffusion region in the semiconductor substrate; (c) a tunnel oxide on said substrate surface and overlying at least a portion of said memory diffusion; (d) a floating gate structure including an extension overlying at least a portion of the tunnel oxide overlying said memory diffusion; (e) one or more field oxide regions adjacent to said tunnel oxide; and (f) a tunnel window defined within the tunnel oxide and separated from said one or more field oxide regions, said tunnel window defined by the middle of the intersection of the floating gate extension and the tunnel oxide and having two edges defined by the floating gate extension, and two edges redefined by the tunnel oxide, and whereby when a defined voltage is applied to said memory diffusion a tunnel current sufficient to change the state of said EEPROM flows between said memory diffusion and said floating gate structure.