Patent ID: 7873507
Filing Date: 2011-01-18
Classification: G06F

Abstract:
1. A multicore model simulator stored in a computer readable medium, comprising: a plurality of threads; a plurality of processor core models executing a plurality of threads serially, wherein the plurality of threads are divided at each predetermined number of execution instructions or each number of cycles; a main thread that generates the plurality of threads and synchronizes said plurality of processor core models at each thread said plurality of processor core models executes in parallel, wherein the main thread is configured to generate a plurality of thread groups, each of the plurality of thread groups being executed by one of the plurality of processor core models, and wherein each of the thread groups includes threads that are divided every predetermined number of execution instructions, and wherein said plurality of processor core models are synchronized every predetermined number of execution instructions of said thread; and a debugger that alternately debugs said plurality of processor core models.