Patent ID: 9166593
Filing Date: 2015-10-20
Classification: H01L,H03K

Abstract:
1. A metal programmable integrated circuit comprising a core logic portion and an I/O portion, the I/O portion comprising an I/O ring region located around a periphery of the core logic portion and an I/O pad region located outside the I/O ring region, the I/O portion comprising a plurality of repeatable I/O modules of uniform size, each comprising: within the I/O ring region, a first I/O buffer occupying a first I/O slot, and a second I/O buffer occupying a second abutting I/O slot, the first I/O slot and the second abutting I/O slot being located at a specified I/O slot pitch relative to one another; within the I/O pad region, a group of I/O pads located in line with the first I/O slot and the second I/O slot and comprising a first I/O pad coupled to the first I/O buffer, a second I/O pad coupled to the second I/O buffer, and a third I/O pad, wherein I/O pads of the group of I/O pads are staggered in relation to one another; and within the I/O pad region, an ESD protection circuit underlying at least one I/O pad of the group of I/O pads to provide ESD protection for the third I/O pad without increasing said I/O slot pitch.