Patent ID: 7689962
Filing Date: 2010-03-30
Classification: G06F

Abstract:
1. A method, comprising: loading at least a portion of a circuit description, the circuit description being indicative of a layout of at least signal-wire segments, ground-wire segments, and power-wire segments; selecting a signal-wire segment of a signal wire; identifying a predetermined number of return paths for the selected signal-wire segment, the return paths comprising ground-wire segments, power-wire segments, or both ground-wire segments and power-wire segments; further segmenting the selected signal-wire segment and the identified return paths into a plurality of bundles, the bundles comprising signal-wire subsegments and one or more associated return-path subsegments, the associated return-path subsegments being parallel to and having the same length as the signal-wire subsegments; using a computer, determining loop inductance values and loop resistance values for the signal-wire subsegments in the bundles for at least one frequency of operation; and storing the loop inductance values and the loop resistance values for the signal-wire segments in one or more computer-readable media.