Patent ID: 8987743
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A thin film transistor (TFT) array substrate comprising: a base substrate; a common electrode line, a gate line and a gate electrode formed on the base substrate; a gate insulating layer formed above the common electrode line, the gate line and the gate electrode; a semiconductor layer formed above the gate insulating layer located on the gate electrode; a source electrode and a drain electrode formed above the semiconductor layer with a channel defined between the source electrode and the drain electrode; a passivation layer formed above the base substrate including the common electrode line, the gate line, and the gate electrode, the source electrode, the drain electrode, and the channel; a first via hole formed in the passivation layer located above the source electrode; a second via hole formed in the passivation layer located above the drain electrode; a data line which is connected to the source electrode through the first via hole; and a pixel electrode which is connected to the drain electrode through the second via hole, wherein the common electrode line comprise a first common electrode line and a second common electrode line adjacent to each other, and wherein the TFT array substrate further comprises: a third via hole formed in the passivation layer located above the first common electrode line; a fourth via hole formed in the passivation layer located above the second common electrode line; and a common electrode interconnection line, one end of which is connected to the first common electrode line through the third via hole, and the other end of which is connected to the second common electrode line thought the second via hole.