Patent ID: 7398458
Filing Date: 2008-07-08
Classification: G06F,H03M

Abstract:
1. A method of processing trellis state information within a processor, the processor comprising: a storage device configured to store a plurality of path metric data; at least one memory port, said at least one memory port adapted to transfer data and signals to and from said storage device; at least one function port, said at least one function port adapted to transfer data and signals to and from a macro function; a data transfer fabric adapted to transfer data and signals between said at least one memory port and said at least one function port; and an arbitration unit adapted to arbitrate access to various portions of said storage device by said macro function; wherein the method comprises: providing a plurality of path metrics for each of a plurality of states; concatenating at least two of said path metrics for adjacent states to produce a word; generating an address such that a read operation may be performed in a linear fashion during a subsequent decoding cycle; and storing said word at said address in said storage device.