Patent ID: 7461211
Filing Date: 2008-12-02
Classification: G06F

Abstract:
1. A prefetcher for predicting accesses to a memory comprising: a prediction generator configured to generate a plurality of nonsequential predications unpatternable to an address; a target cache including a number of prioritized ways, the target cache coupled to said prediction generator to maintain associations between each trigger address and one or more corresponding target addresses with each association corresponding to a nonsequential prediction, the target cache configured to store a plurality of trigger-target associations for a trigger address in an arrangement that determines a priority wherein a trigger-target association stored in a first way is associated with a higher priority than another trigger-target association stored in a second way; and a priority adjuster to discover trigger-target associations, prioritize the trigger-target associations from the most recent, successful target addresses to the least recent, successful target addresses, and in response to detecting two target addresses with priorities improperly swapped, reprioritize trigger-target associations by inserting a highest priority trigger-target association into a highest priority way and inserting a previous highest priority trigger-target association into a second highest priority way, wherein the priority adjuster receives an indication of success of target addresses in providing data requested from said memory; the prefetcher using the prioritized trigger-target associations to generate a configurable number of predictions in order of priority for a selected address.