Patent ID: 6514848
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A method of forming an interconnection of a semiconductor element, element comprising:forming a groove in a surface of an underlying substrate so as to correspond to a designed pattern; forming a first layer of a refractory metal and a second layer of a nitride of said refractory metal sequentially on said surface of said underlying substrate and within said groove, wherein said first layer is thinner than said second layer, wherein the first and second layers together define an underlayer, and wherein portions of said underlayer formed on sidewalls of said groove are thinner than portions of said underlayer formed on said surface of said underlying substrate and portions of said underlayer formed on a bottom wall of said groove; forming a film of interconnection material over said substrate and in said groove; and polishing film of interconnection material to remove said film of interconnection material other than in said groove.