Patent ID: 6067617
Filing Date: 2000-05-23
Classification: G06F

Abstract:
A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode method for setting and testing conditions with specialized update and branch instructions comprising the steps of: storing in an internal code array milli-mode routines as said set of millicode simple instructions, and when milli-mode detection logic coupled to instruction registers of said processor detects that a macro-instruction, which is being decoded, is of a type that is to be interpreted in said milli-mode architected operating state then said milli-mode architected state is enabled with a milli-mode recognition signal and macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers, whereupon a milli-mode entry point address is generated to address the millicode stored in said internal code array which are fetched from said internal code array and sent to said processor instruction registers whereupon the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode, and whereupon on entry to a milli-mode millicode routine one or more specialized millicode instructions for packed decimal division which make use of the hardware control and dataflow logic designed to support simpler packed decimal operations including Add to provide operand access, checking, preparation, and storing functions, and to generate the quotient digits as needed for the DP instruction are implemented as internal code instructions, rather than implementing the entire DP function in hardware, and control is maintained in internal code allowing simpler handling of unusual and boundary conditions; and whereinone of said specialized millicode instructions for packed decimal division, a Divide Decimal Fetch, fetches the operands from storage, extends them on the left with zero digits as needed, checks the digits and sign for validity, strips off and records the signs, computes the number of significant digits in each operand, and saves its results in general registers and in the condition code.