Patent ID: 6373309
Filing Date: 2002-04-16
Classification: G11C,H03K

Abstract:
A duty cycle compensation circuit of a delay locked loop (DLL) for a Rambus DRAM comprising:a duty cycle compensation means for compensating a duty cycle of an input signal during modes of operation other than a nap mode and providing a compensated input signal, and storing duty information of a compensated input signal into a capacitor so that the information will be stored during nap mode operation; an analog-to-digital conversion means for converting the compensated input signal into a digital signal according to a first control signal, and maintaining the converted digital signal regardless of the input signal when the first control signal is disabled; a digital-to-analog conversion means for converting the digital signal from the analog-to-digital conversion means into an analog signal according to a second control signal, and being turned off when the second control signal is disable; and a control means for respectively generating the first and second control signals depending on whether or not the nap mode operates.