Patent ID: 8091013
Filing Date: 2012-01-03
Classification: H03M,H04L

Abstract:
1. An apparatus, comprising: a plurality of memories including a number of memories corresponding to a plurality of non-null sub-matrices within of a first low density parity check (LDPC) matrix of a first LDPC code and a second LDPC matrix of a second LDPC code; a plurality of bit engines; a plurality of check engines; and a switching module, coupled to the plurality of memories, the plurality of bit engines, and the plurality of check engines, for providing selective connectivity: between a first subset of the plurality of memories and the plurality of bit engines and also between the first subset of the plurality of memories and the plurality of check engines for decoding of the first LDPC coded signal; and between a second subset of the plurality of memories and the plurality of bit engines and also between the second subset of the plurality of memories and the plurality of check engines for decoding of the second LDPC coded signal; and wherein: the first subset of the plurality of memories and the second subset of the plurality of memories including a common memory for storing one of the plurality of non-null sub-matrices having a common row and column location within each of the first LDPC matrix and the second LDPC matrix.