Patent ID: 8957481
Filing Date: 2015-02-17
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a semiconductor substrate; at least one gate formed on the semiconductor substrate; sidewall spacers adjacent to the gate; source/drain regions on both sides of the gate; contacts formed on the source/drain regions; first shallow trench isolations which are embedded in the semiconductor substrate and have a length direction parallel to that of the gate; and second shallow trench isolations which are separated from each other and located on both sides of the outmost source/drain regions and connected with the first shallow isolations to form an isolation region, wherein an upper surface of the second shallow trench isolation is higher than that of the source/drain regions and that of the first shallow trench isolations; wherein a lower surface of the second shallow trench isolation is lower than the upper surface of the first shallow trench isolation; and wherein each of the at least one gate is formed astride, at opposite ends thereof, the first shallow trenches.