Patent ID: 6242297
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A semiconductor device fabrication method for fabricating a semiconductor device having a lead connection structure wherein at least two lead layers are electrically interconnected via contact holes, said semiconductor device fabrication method comprising the steps of:forming a first and a second impurity region on a principal plane of a semiconductor substrate;forming a first insulating film so as to cover a surface of said semiconductor substrate;forming on said first insulating film first through hole reaching a surface of said first impurity region;forming on said first insulating film first lead connected electrically to said first impurity region via said first through hole formed on said first insulating film;forming a second insulating film so as to cover said first lead;forming second through hole penetrating said first insulating film, said first lead and said second insulating film, said second through hole reaching a surface of said second impurity region; andforming on said second insulating film second lead connected electrically to said second impurity region via said second through hole.