Patent ID: 7816728
Filing Date: 2010-10-19
Classification: G11C,H01L

Abstract:
1. A non-volatile random access memory cell comprising: a semiconductor substrate including at least one array region that contains a plurality of trench structures having a depth from about 1 to about 2 μm, each trench structure including a select transistor having a channel located on vertical sidewalls of said trench structure, wherein the select transistor of at least one of the plurality of trench structures is isolated from the select transistor of an adjacent trench structure by a trench isolation region that is present overlying a portion of a gate conductor of the select transistor that is present within the trench structure and extends from a sidewall of a first trench structure of the plurality of trench structures through the semiconductor substrate to a sidewall of the adjacent trench structure; a source diffusion of the select transistor located beneath a bottom wall of each trench structure and a drain diffusion of the select transistor located in an upper sidewall portion of each trench; and a memory transistor comprising an oxide/nitride/oxide gate dielectric abutting a horizontal surface of said semiconductor substrate and adjoining said plurality of trench structures, in which a memory state is represented by a charge stored in the oxide/nitride/oxide gate dielectric.