Patent ID: 6279050
Filing Date: 2001-08-21
Classification: G06F

Abstract:
A data transfer apparatus transferring data between a data transfer element and a buffer memory, and between said buffer memory and a data bus, comprising:a plurality of state machines, said state machines arranged into three functional units: an upper machine, a middle machine and a lower machine;said lower machine being interfaced to said buffer memory and said data transfer element, said lower machine being operable to control transfers between said buffer memory and said data transfer element;said upper machine being interfaced to said buffer memory and said data bus, said upper machine being operable to control data transfers between said buffer memory and said data bus;said middle machine being operable to control data movement to and from said data bus by coordinating control between elements that comprise data transfer channels, and between said upper machine and said lower machine;wherein said plurality of state machines are operable to facilitate movement of user data between said data transfer element and said data bus, through said buffer memory; andwherein said data transfer element is an assembly/disassembly mechanism which is further operable to selectively transmit a request to said middle machine to initiate transfer of data, and wherein said middle machine arbitrates among a plurality of lower side requesters to initiate a grant cycle.