Patent ID: 9202784
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device, comprising: a substrate structure layer including a substrate comprising a well and a diffusion region thereon; an interconnect layer including a pair of power supply lines arranged at a preset spacing from said substrate structure layer, said interconnect layer further including an input side interconnect and an output side interconnect between said pair of power supply lines; a standard cell comprising a logic circuit on said substrate, said logic circuit being electrically connected to said pair of power supply lines, said input side interconnect and said output side interconnect; and one or more capacitances arranged between said substrate structure layer and said interconnect layer, and arranged in a region between said pair of power supply lines, said region being inclusive of a region superposed with said pair of power supply lines, and, in a plan view, said one or more capacitances continuously extending from one of said pair of power supply lines to an other one of said pair of power supply lines, said capacitance being electrically connected to at least one out of areas delimited: