Patent ID: 8847639
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. A waveform generator for providing an analog output signal to a target device, comprising: a look-up table (LUT) for storing a plurality of binary address values; a digital-to-analog converter (DAC), connected to the LUT, for generating the analog output signal based on the plurality of binary address values; a rising-edge detector for receiving an input trigger signal from the target device and detecting a rising edge of the input trigger signal; a LUT address capture module, connected to the LUT and the rising-edge detector, for capturing a binary address value of the plurality of binary address values, wherein the binary address value corresponds to the rising edge of the input trigger signal; a digital comparator, connected to the LUT address capture module, for comparing the captured binary address value with a set of predetermined binary address values and generating a first output signal when the captured binary address value matches a binary address value of the set of predetermined binary address values; and a compensator module, connected to the digital comparator, the rising-edge detector and the LUT, for providing a reload signal to the LUT based on the first output signal, and reloading a first binary address value of the plurality of binary address values in to the LUT, wherein the DAC re-initiates the generation of the analog output signal from the first binary address value, thereby aligning the analog output signal with the input trigger signal.