Patent ID: 8443132
Filing Date: 2013-05-14
Classification: G11C

Abstract:
1. An arrangement for cascading non-volatile memory comprising: a microcontroller having a single chip select pin; a first non-volatile memory device having a first device enable input, a single pin-out-to-chip, a cascade circuit, a memory cell and a memory controller having a memory controller output, the memory controller being operatively connected to the memory cell, the microcontroller being connected to the first non-volatile memory device via a first connection connecting the single chip select pin and the first device enable input, and the microcontroller enables the first non-volatile memory device via the first connection; a second non-volatile memory device having a second device enable input, the first non-volatile memory device being connected to the second non-volatile memory device via a second connection connecting the single pin-out-to-chip and the second device enable input; wherein the cascade circuit is operatively connected to the memory controller for determining if the first non volatile memory device is in the process of writing to, or reading from, the memory cell, the cascade circuit being responsive to the memory controller output for enabling the second non-volatile memory device via the second connection based on the determination; wherein in the arrangement, only the first non-volatile memory device is enabled to be read or written by the microcontroller and only the second non-volatile memory device is enabled to be read or written by the cascade circuit; and wherein at most only one of the first non-volatile memory device or the second non-volatile memory device is enabled to be read or written to at any one time.