Patent ID: 6110753
Filing Date: 2000-08-29
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory in which:bit lines are formed by photolithography of an exposure light having a wavelength of .lambda., and a depth of focus of DOF, and a line width of the bit lines excluding a connection portion with cell transistors and a minimum interval of the bit lines becomes shorter than .lambda. respectively in the bit lines, and an accumulation capacity element is further provided above the bit lines,the method comprising the steps of:forming a P-type region on a surface of a silicon substrate, forming grooves in a cell array region, a peripheral circuit region and a device separation region of a boundary region between the cell array region and the peripheral circuit region and filling in the grooves with a field insulation film, an upper surface of which is generally flush with the surface of the silicon substrate;forming a gate insulation film by heat oxidation on the surface of the silicon substrate in the cell array region and the peripheral circuit region surrounded by the device separation region, forming a first conductive film having a first thickness (=t1) on an overall surface of the silicon substrate, and forming word lines and a gate electrode on the surface of the P-type region of the cell array region and the peripheral circuit region by the patterning of the first conductive film;forming an N.sup.- -type source and drain region and an N.sup.- -type diffusion layer on the surface of the P-type region of the cell array region and the peripheral circuit region surrounded by the device separation region in self-alignment with the word lines and the gate electrode;forming a first silicon oxide film having a second thickness (=t2) which is thicker than the DOF/2-t1 on the overall surface of the silicon substrate by low pressure chemical vapor deposition (LPCVD);etching back the first silicon oxide film by an anisotropic dry etching process to set the thickness of the first silicon oxide film immediately on the word lines and the gate electrode to a third thickness (=t3);etching back again the first silicon oxide film again by anisotropic dry etching using as a mask a first photoresist film pattern which covers the cell array region and the boundary region and which has an opening in the peripheral circuit region to retain and for an insulation film spacer comprising the first silicon oxide film on a side of the gate electrode;forming an N.sup.+ -type diffusion layer on the surface of the P-type region of the peripheral circuit region by using as a mask the gate electrode and the insulation film spacer and forming an LDD-type source and drain region comprising the N.sup.+ -type diffusion layer and the N.sup.- -type diffusion layer;forming a second silicon oxide film on an overall surface of the substrate and forming a BPSG film on the overall surface of the silicon substrate by APCVD and reflowing the BPSG film so that the maximum step of an upper surface of the BPSG film becomes smaller than t1+t3 and DOF/2 and larger than DOF/2-(t2-t3) thereby forming an interlayer insulation film comprising the second silicon oxide film and the BPSG film;forming on the interlayer insulation film bit contact holes and contact holes which reach respectively one of the N-type source and drain region and one of the LDD-type source and drain region;forming a second conductive film on an overall surface of the silicon substrate, forming a positive-type photoresist film on the overall surface of the substrate, forming a second photoresist film pattern by focusing on an upper surface of the photoresist film immediately on the word lines and further performing exposure under the condition that a pattern width in this portion becomes maximum, forming bit lines by anisotropic dry etching using as a mask these photoresist film patterns, and simultaneously forming wiring on the peripheral circuit region; andforming a second interlayer insulation film on the overall surface of the substrate, forming a node contact hole which reaches the other of the N.sup.- -type source and drain region through the second interlayer insulation film and the first interlayer insulation film and forming an accumulation capacity element connected to the other of the N.sup.- -type source and drain region via the node contact hole.