Patent ID: 6684299
Filing Date: 2004-01-27
Classification: G06F

Abstract:
In a processor that executes coded instructions, a method for operation of a multi-level cache memory unit where at least one level is non-blocking, the method comprising:generating multiple cache system accesses simultaneously, each access comprising an address identifying a memory location having data that is a target of the access; inserting each access into an entry in a memory scheduling window; marking each entry as valid when that entry is ready to be applied to a first cache; picking valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache, wherein the picking occurs in a free-running mode regardless of whether the accesses hit in the first cache; in a second cache, receiving accesses that have missed in the first cache; in the second cache, monitoring resources within the second cache to determine when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache; in response to the monitoring, generating a stall signal from the second cache; and in response to the stall signal, stalling the picking process wherein; the stalling process further comprises: resolving one of the accesses that missed in the first cache in the second cache; using the second cache to point to an entry in the scheduling window corresponding to the resolved access; and applying the address within the corresponding entry to the first cache in synchronization with receiving the target data from the second cache.