Patent ID: 8799840
Filing Date: 2014-08-05
Classification: G06F

Abstract:
1. A method of analyzing an electronic circuit design, the method comprising: analyzing a hierarchy of a netlist of a circuit to determine one or more primary inputs (PI) and one or more primary outputs (PO) of the circuit at an upper level, and one or more internal vertices of the circuit at lower levels between the one or more primary inputs (PI) and the one or more primary outputs (PO); forming a plurality of paths in a path space from the one or more primary inputs (PI) to the one or more primary outputs (PO) through the one or more internal vertices, wherein the plurality of paths represent a plurality of timing delays as a function of a plurality of circuit parameters and process corners; dynamically pruning portions of the plurality of paths in the path space using branch and bound techniques on bounds of timing delay to reduce the path space down to one or more critical timing paths of the circuit with a worse case metric of timing delay between the one or more primary inputs (PI) and the one or more primary outputs (PO), wherein the dynamically pruning of portions of the plurality of paths using branch and bound techniques includes searching over all complete paths in the path space that end at each of the one or more primary outputs for the one or more critical timing paths of the circuit; and wherein one or more of the analyzing, the forming, and the dynamically pruning are performed with a processor.