Patent ID: 7608501
Filing Date: 2009-10-27
Classification: H01L,Y10S

Abstract:
1. A method, comprising: selectively forming a first etch stop layer above only one of a first transistor element and a second transistor element; forming a first contact etch stop layer above said first and second transistor elements and said first etch stop layer after selectively forming said first etch stop layer above only one of said first and second transistor elements, said first contact etch stop layer having a first specified intrinsic stress; selectively removing a portion of said first contact etch stop layer formed above said one of said first transistor element and said second transistor element having formed thereabove said first etch stop layer by a selective etch process using said first etch stop layer as an etch stop; and forming a second contact etch stop layer above said first and second transistor elements, said second contact etch stop layer having a second intrinsic stress that differs from said first intrinsic stress.