Patent ID: 6754893
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A method for reducing a code size of a software pipelined loop having a kernel and an epilog, comprising:evaluating at least one stage of the epilog, comprising: selecting a stage of the epilog to evaluate; evaluating at least one instruction in a reference stage, comprising identifying an instruction in the reference stage that is not present in the selected stage of the epilog; determining if the identified instruction can be speculated; noting that the identified instruction can be speculated responsive to a determination that the identified instruction can be speculated; determining if the identified instruction can be predicated responsive to a determination that the identified instruction cannot be speculated; marking the identified instruction as needing predication responsive to a determination that the identified instruction can be predicated; determining if another instruction in the reference stage is not present in the selected stage of the epilog; repeating the instruction evaluation responsive to a determination that there is another instruction in the reference stage not present in the selected stage of the epilog; determining if there is another stage of the epilog to evaluate; repeating the evaluation of the stage responsive to a determination that there is another instruction in the reference stage not present in the selected stage of the epilog; and collapsing the selected stage of the epilog responsive to a determination that there is not another instruction in the reference stage not present in the selected stage of the epilog.