Patent ID: 6567943
Filing Date: 2003-05-20
Classification: G01R

Abstract:
A boundary scan cell comprising:a shift latch, an update latch and a flushable latch that each have at least a respective data input and at least a respective data output, wherein said data output of said shift latch is coupled to said data input of said update latch, said data output of said update latch is selectively coupled to said data input of said flushable latch, and said data output of said flushable latch is selectively coupled to said data input of said shift latch and is non-selectively coupled to an integrated circuit I/O pin, wherein said flushable latch further includes at least one clock input coupled to receive at least one clock signal during at least a non-test mode, wherein during said non-test mode said flushable latch propagates a logic state change at its data input to its data output in response to a logic state change of said at least one clock signal; and control circuitry that controls operation of said flushable latch circuit and, responsive to a mode signal, selects, as input data for said flushable latch, one of a functional logic signal and a boundary scan signal, wherein if said mode sign indicates a test mode, said control circuitry selects said boundary scan signal as said input data and causes said flushable latch to flush through said input data to said data output of said flushable latch and to said integrated circuit I/O pin independently of any logic state change of said at least one clock signal; wherein during both said test mode and said non-test mode, a logic state present at said data output of said flushable latch propagates to the integrated circuit I/O pin independently of any selection logic such that latency is reduced.