Patent ID: 8953357
Filing Date: 2015-02-10
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array that includes a word line extending in a row direction, a bit line group containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group; a read circuit configured to read out data from the memory cells through the bit lines; and a bit line precharge/discharge circuit disposed between the memory cell array and the read circuit, and configured to charge or discharge the bit lines; the memory cell having different connection states including a state in which a first terminal of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the first terminal is electrically connected only to a specific one of the plurality of bit lines, the first terminal being a source or a drain of the transistor, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the plurality of bit lines of the bit line group and spaces between the bit lines, when viewed in a stacking direction that is perpendicular to the row direction and the column direction.