Patent ID: 7504896
Filing Date: 2009-03-17
Classification: H03K

Abstract:
1. A method of inline measurement of switching delay history effects in an integrated circuit device comprising the steps of: launching a pulse down a delay chain, wherein the pulse is substantially synchronized with a signal of a ring oscillator, and the delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain; measuring at least one difference between a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain when the pulse reaches the far end of the delay chain; and determining one or more switching histories in the integrated circuit device in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse; wherein the step of measuring at least one difference comprises the step of determining a fractional difference in a delay of a rising edge of the signal in the ring oscillator and a delay of a rising edge of the pulse in the delay chain; and wherein the method is operative to perform the step of determining one or more switching histories when a first switch delay is greater than a second switch delay, and when the second switch delay is greater than the first switch delay.