Patent ID: 8483579
Filing Date: 2013-07-09
Classification: H03D,H03L,H04B,H04L

Abstract:
1. A phase detector circuit for outputting a phase difference between an input signal and a plurality of clock signals, the plurality of clock signals being N in number, N being an integer of 2 or larger, the clock signals each having a period equaling N times a period of the input signal, and having phases shifted in steps of 1/N times the period, the phase detector circuit comprising: a phase detecting circuit configured to output phase difference signals representing phase differences between the N clock signals in respect to a rising edge of either one of the input signal and an inversion of the input signal; an identification signal output unit configured to output an identification signal identifying either a first clock signal or a second clock signal, the first clock signal being one among the N clock signals whose phase, relative to a rising edge of the input signal, is closest to 0 or an even number multiple of π, and the second clock signal being one among the N clock signals whose phase, relative to a rising edge of the input signal, is closest to an odd number multiple of π; and a signal selection unit configured to select, out of the phase difference signals outputted by the phase detecting circuit, a phase difference signal representing the phase difference between; the rising edge of the respective one of the input signal and the inversion of the input signal, and the respective one of the first clock signal and the second clock signal, according to the identification signal.