Patent ID: 6169770
Filing Date: 2001-01-02
Classification: G01S

Abstract:
A preemptive processor for use in a mode-S receiver system including a message processing circuit, comprising: a signal input; a high-level threshold circuit coupled to the signal input, the high-level threshold circuit providing a high threshold signal at a high output; a low-level threshold circuit coupled to the signal input, the low-level threshold circuit providing a low threshold signal at a low output; a first preamble circuit coupled to the high output, the first preamble circuit providing a first control signal in response to the high threshold signal and including a message preamble at the high output; a second preamble circuit coupled to the low output, the second preamble circuit providing a second control signal in response to the low threshold signal and including the message preamble at the low output; and a signal path control circuit having a message initialization output coupled to the message processing circuit and an end-of-message input coupled to the message processing circuit, the signal path control circuit providing a message initialization signal at the message initialization output in response to the first control signal, and the signal path control circuit providing the message initialization signal at the message initialization output in response to the second control signal if an end-of-message signal has been received at the end-of-message input after a previous message initialization signal.