Patent ID: 6353338
Filing Date: 2002-03-05
Classification: H03K

Abstract:
A differential output buffer comprising:logic high and logic low voltage supply terminals; first and second complementary data inputs; an idle input having an active state and an inactive state; a current-mode differential output stage comprising first and second differential data outputs and first and second output stage control inputs; a first push-pull circuit biased in series between the logic high and logic low voltage supply terminals and having first and second inputs coupled to the first and second data inputs, respectively, and an output coupled to the first output stage control input; a second push-pull circuit biased in series between the logic high and logic low voltage supply terminals and having first and second inputs coupled to the second and first data inputs, respectively, and an output coupled to the second output stage control input; and a voltage supply generator coupled to the idle input and the logic low voltage supply terminal, which generates a logic low voltage on the logic low voltage supply terminal when the idle input is in the inactive state and a logic high voltage on the logic low voltage supply terminal when the idle input is in the active state.