Patent ID: 8639985
Filing Date: 2014-01-28
Classification: G06F

Abstract:
1. A Universal Serial Bus (USB) testing apparatus comprising: a Central Processing Unit (CPU); a Southbridge; a Baseboard Management Controller (BMC), connected with the Southbridge via USB, and configured to monitor working states of the USB testing apparatus; wherein the BMC is further configured to determine if a test starts or finishes, generate a first instruction of creating a virtual control computer when determining the test starts, create a control module and a comparing module in a memory unit which are running to become the virtual control computer, and connect the memory unit with the BMC according to the first instruction; and wherein the control module is configured to send control data to the CPU, and the comparing module is configured to obtain feedback data from the CPU and compare the control data with the obtained data to determine if the control data is consistent with the obtained data, thereby determining whether the USB is working normally.