Patent ID: 8115288
Filing Date: 2012-02-14
Classification: H01L

Abstract:
1. A lead frame for supporting a semiconductor die within a semiconductor package device, the lead frame comprising: a die bond area for receiving a semiconductor die; and a plurality of leads arranged around and spaced apart from the die bond area for being electrically interconnected with the semiconductor die and for providing electrical interconnection for the semiconductor package device, the leads having a top surface and a bottom surface, wherein a first lead in the plurality of leads has a recessed portion from the top surface, and a second lead adjacent to the first lead has a recessed portion from the bottom surface for reducing burr formation effects; wherein the first lead and the second lead are adjacent and are separated by a first distance, and the first lead and a third lead adjacent to the second lead are separated by a second distance, wherein the second distance extends beyond a zone of potential burr formation from the first lead.