Patent ID: 8242502
Filing Date: 2012-08-14
Classification: H01L

Abstract:
1. An array substrate comprising: a substrate; at least one gate line and gate electrode disposed on the substrate, wherein both of the gate line and gate electrode have first and second conductive layers, the first conductive layer is formed on the substrate, the first conductive layer contains a molybdenum nitride, the second conductive layer is formed on the first conductive layer, the second conductive layer is an alloy layer containing copper with a copper content of more than 95% by weight, and the alloy layer further contains at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), neodymium (Nd), indium (In) and aluminum (Al); a gate insulating layer disposed on the gate line, gate electrode and the substrate; at least two semiconductor layers disposed on the gate insulating layer; and at least one source electrode and drain electrode disposed on the semiconductor layers, and at least one data line disposed on the gate insulating layer.