Patent ID: 6099576
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A system for designing a CMOS inverter circuit comprising a p-channel transistor and an n-channel transistor each having a respective polysilicide gate and gate oxide layer, comprising:an input device for receiving as an input at least one parameter of the CMOS inverter circuit relating to a parameter selected from a group comprising .tau..sub.rc, .rho..sub.sn, .rho..sub.sp, .omega..sub.n, .omega..sub.p, and C.sub.ox, where .tau..sub.rc represents a gate RC delay, .rho..sub.sn represents a sheet resistance of the polysilicide gate of the n-channel transistor, .rho..sub.sp represents a sheet resistance of the polysilicide gate of the p-channel transistor, .omega..sub.n represents a channel width of the n-channel transistor, .omega..sub.p represents a channel width of the p-channel transistor, and C.sub.ox represents the capacitance per unit area of the gate oxide layers of the p-channel and n-channel transistors;a computer, operatively coupled to the input device, programmed to estimate at least another of the parameters .tau..sub.rc, .rho..sub.sn, .rho..sub.sp, .omega..sub.n, .omega..sub.p, and C.sub.ox based on the at least one parameter input to the input device using the following relationship,.tau..sub.rc =k.multidot.((.rho..sub.sn .multidot..omega..sub.n.sup.2)+(.rho..sub.sp .multidot..omega..sub.p.sup.2)).multidot.C.sub.oxwhere k represents a predefined constant; andan output which provides indicia of the estimated at least another of the parameters, as determined by the computer.