Patent ID: 6552361
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A thin film transistor (TFT) device, comprising:a substrate; a source region over the substrate; a drain region over the substrate; an active layer over the substrate between the source region and the drain region; a gate insulating layer covering the source region, the drain region and the active layer; a gate on the gate insulating layer; an interlayer over the gate insulating layer, covering the gate; a planarization layer over the interlayer; a source region metal line on the planarization layer, wherein the source region metal line is connected to the source region; a drain region metal line on the planarization layer, wherein the drain region metal line is connected to the drain region; a passivation layer over the planarization layer, covering the source region metal line and the drain region metal line, wherein the gate insulating layer, the interlayer, and the planarization layer are formed between the substrate and the passivation layer; and a conductive layer on the passivation layer, connecting to the source region metal line.