Patent ID: 6888826
Filing Date: 2005-05-03
Classification: H04J,Y10S

Abstract:
1. A SONET multiplexed communications system, comprising: pointer processing circuitry clocked by a first clock, the pointer processing circuitry being configured to process at least one SONET signal comprising data and overhead information; at least one overhead information insertion circuit clocked by a second clock, the insertion circuit being configured to re-generate the overhead information and insert the re-generated overhead information in the SONET signal; and at least one clock domain transfer circuit coupled between the pointer processing circuitry and the insertion circuit, the clock domain transfer circuit including at least one first buffer having a plurality of addressable locations configured to store the data and overhead information of the SONET signal, wherein the clock domain transfer circuit is configured to compensate for timing differences between the first and second clocks by addressing the plurality of first buffer locations for selectively overwriting or skipping at least one location corresponding to the overhead information of the SONET signal.