Patent ID: 7550356
Filing Date: 2009-06-23
Classification: H01L,Y10S

Abstract:
1. A method of fabricating strained-silicon transistors comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a gate, at least a spacer, and a source/drain region; removing the spacer and followed by forming a high tensile stress film over the surface of the gate and the source/drain region; performing a first rapid thermal annealing process after removing the spacer and forming the high tensile stress film to simultaneously activate the dopants within the source/drain region and expand the lattice arrangement of the semiconductor substrate beneath the gate; removing the high tensile stress film from the surface of the gate and the source/drain region after performing the first rapid thermal annealing process; forming a metal layer over the surface of the semiconductor substrate; and performing a second rapid thermal annealing process to form a silicide layer.