Patent ID: 7494895
Filing Date: 2009-02-24
Classification: H01L

Abstract:
1. A method of fabricating a three-dimensional transistor, comprising: forming a hard mask pattern on a semiconductor substrate; etching the semiconductor substrate using the hard mask pattern as an etch mask to form a trench that defines an active region; sequentially forming a trench oxide layer and a liner on the semiconductor substrate having the trench; forming an isolation layer to fill the trench, wherein the isolation layer has an upper surface recessed down from an upper surface of the hard mask pattern; forming a hard mask spacer to cover sidewalls of the hard mask pattern; forming a mask pattern having an opening that crosses the hard mask pattern; and etching the isolation layer using the mask pattern, the hard mask pattern and the hard mask spacer as an etch mask to define a channel region, wherein some portions of the isolation layer where the etching is blocked by the hard mask spacer remain on sidewalls of the channel region.