Patent ID: 6897693
Filing Date: 2005-05-24
Classification: G11C,H03K,H03L

Abstract:
1. A delay locked loop (DLL) comprising: a basic clock generator for generating a plurality of basic clock signals which are each shifted by a predetermined phase in response to an external signal; a mixer for generating a first clock signal and a second clock signal which is 90 degrees out-of-phase with the first clock signal, in response to the plurality of basic clock signals; a clock buffer for generating a first internal clock signal in response to the first clock signal and a second internal clock signal in response to the second clock signal; a first duty corrector for correcting a duty of the first internal clock signal and feeding an output of the first duty corrector back to the clock buffer; a second duty corrector for correcting the duty of the second internal clock signal and feeding an output of the second duty corrector back to the clock buffer; a phase detector for comparing and detecting phases of the external clock signal and the second internal clock signal; and a digital-to-analog converter for controlling phase ranges of the first and second clock signals generated in the mixer in response to an output of the phase detector.