Patent ID: 6420258
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method of fabricating an integrated circuit on a substrate, the method comprising:providing a semiconductor substrate; providing a substrate having a layer of dielectric, interlevel dielectric, or an interconnect line layer; providing a first level of conducting wiring being defined and embedded in a first layer of insulator; providing patterned and etched trenches in deposited insulator; blanket depositing a trench diffusion barrier liner material which is a diffusion barrier layer over the insulator and into the trenches; blanket depositing a seed layer by physical vapor deposition (PVD) over the diffusion barrier liner material; polishing off by chemical mechanical polish only the seed layer that is over the insulator leaving a remaining seed layer only in the trench; depositing metal by electrochemical deposition by a selective method on the remaining seed layer, only in the trench forming excess metal; polishing back the excess metal by chemical mechanical polish, which planarizes the surface; removing the diffusion barrier layer selectively, only over the insulator; thus, repeating the above process steps, interconnects for multilevel conducting layers are fabricated by this integrated method.