Patent ID: 6104222
Filing Date: 2000-08-15
Classification: H03L

Abstract:
A phase locked loop system, comprising:a first phase frequency detector for detecting a difference between an internal clock signal and an external clock signal, said first phase frequency detector generating a first control signal representing the difference;a first voltage controlled oscillator coupled to said first phase frequency detector, for generating a first timing signal based on said first control signal;a first divider circuit coupled to said first voltage controlled oscillator, for dividing said first timing signal by a first predetermined number to provide an output signal;a second phase frequency detector for detecting a difference between the first timing signal and a second timing signal, said second phase frequency detector generating a second control signal representing the difference;a second voltage controlled oscillator coupled to said second phase frequency detector, for generating a third timing signal based on said second control signal;a second divider circuit coupled to said second voltage controlled oscillator, for dividing said third timing signal by a second predetermined number to provide the second timing signal;a third divider circuit coupled to said second voltage controlled oscillator, for dividing said third timing signal by a third predetermined number to provide said internal clock signal.