Patent ID: 9224669
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method for preparing a wafer level packaging structure with large contact area, wherein a plurality of first metal bonding pads are formed at front surfaces of semiconductor chips formed in a semiconductor wafer, the method comprising the steps of: forming at least a second metal bonding pad at the front surface of the semiconductor chip; forming a plurality of top metal interconnecting structures on the first metal bonding pads and the second metal bonding pad; forming a first packaging layer covering the first metal bonding pads, the second metal bonding pad, the plurality of top metal interconnecting structures and the front surface of the semiconductor wafer; etching a back surface of the semiconductor wafer to form a bottom through hole to expose the second metal bonding pad and filling a conductive material in the bottom through hole to form a bottom metal interconnecting structure connected to the second metal bonding pad; forming a metal layer covering the back surface of the semiconductor wafer connected to the bottom metal interconnecting structure; cutting through the semiconductor wafer and the metal layer from the back surface of the semiconductor wafer to form a plurality of cutting grooves extending into the first packaging layer and separating individual semiconductor chips from each other, wherein the metal layer is cut into a plurality of bottom metal layers each of which is formed of at a back surface of a respective semiconductor chip; depositing a packaging material to form a second packaging layer covering the plurality of bottom metal layers and to fill into the plurality of cutting grooves; grinding the first packaging layer until exposing the packaging material filled in the plurality of cutting grooves and the plurality of top metal interconnecting structures, wherein the first packaging layer is cut into a plurality of top packaging layers each of which covers the front surface of the respective semiconductor chip; forming a plurality of contact bonding pads atop the plurality of top packaging layer, wherein each contact bonding pad is electrically connect to one first metal bonding pad or one second metal bonding pad through at least one top metal interconnecting structure of the plurality of top metal interconnecting structures; and cutting through the second packaging layer and the packaging material filled in the plurality of cutting grooves along the plurality of cutting grooves to separate individual wafer level packaging structures from each other, wherein the second packaging layer is cut into a plurality of bottom packaging layers each of which covers the respective bottom metal layer of the respective semiconductor chip.