Patent ID: 8431450
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. A method of fabricating a transistor having a source, drain, and a gate on a substrate, the method comprising: implanting a first impurity region with a first volume and a first surface area, the first region being of a first type; forming a gate insulator between a source region and a drain region of the transistor, the gate insulator covering a portion of the first surface area including aligning a drain-side edge of the gate insulator with a drain-side edge of the first impurity region; covering the gate insulator with a conductive material; and implanting, into the drain region of the transistor, a second impurity region with a second volume and a second surface area with a second impurity type, the second volume in contact with the first volume, the second region being of an opposite second type.