Patent ID: 6714902
Filing Date: 2004-03-30
Classification: G06F

Abstract:
A method for critical and false path verification, the method comprising:creating a Boolean expression F, which captures conditions that could make a potential false path true; performing a satisfiability test on F: if the satisfiability test finishes within a predetermined time period, and if F is not satisfiable, then F is a false path and processing ends; otherwise, if F is satisfiable, then the path is combinationally true, and F is simplified to an Fsimplified expression; if the satisfiability test does not finish within the predetermined time period, then F is simplified to an Fâ€² expression, which may contain register elements; performing a system simulation using either the Fsimplified or Fâ€² expression; and determining whether the Fsimplified or Fâ€² expressions can ever be true from the system simulation.