Patent ID: 7974148
Filing Date: 2011-07-05
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first memory cell array in which memory cells are arranged in a matrix; a first word line; a second word line; a third word line; a fourth word line; a first word line group including a first plurality of word lines, the first plurality of word lines including both the first word line and the third word line, and the first memory cell array including at least a portion of the first word line group; a second word line group including a second plurality of word lines, the second plurality of word lines including both the second word line and the fourth word line, and the first memory cell array including at least a portion of the second word line group; a first transistor of a first conductivity type, a source or a drain of the first transistor being connected to the first word line; a second transistor of the first conductivity type, a source or a drain of the second transistor being connected to the second word line; a third transistor of the first conductivity type, a source or a drain of the third transistor being connected to the third word line; a fourth transistor of the first conductivity type, a source or a drain of the fourth transistor being connected to the fourth word line; a fifth transistor of a second conductivity type opposite to the first conductivity type, a drain of the fifth transistor being connected to both a gate of the first transistor and a gate of the third transistor; a sixth transistor of the second conductivity type, a drain of the sixth transistor being connected to both a gate of the second transistor and a gate of the fourth transistor; a seventh transistor of the first conductivity type, a source of the fifth transistor being connected to a source of the seventh transistor, and a gate of seventh transistor being connected to both the gate of the first transistor and the gate of the third transistor; and an eighth transistor of the first conductivity type, a source of the sixth transistor being connected to a source of the eighth transistor, and a gate of eighth transistor being connected to both the gate of the second transistor and the gate of the fourth transistor.