Patent ID: 7068559
Filing Date: 2006-06-27
Classification: G11C

Abstract:
1. A word line enable timing determination circuit in a memory device adapted to perform a hidden refresh operation, comprising: a detector detecting an address signal and generating a detection pulse (PP) signal in response thereto; a first signal generator generating a delayed detection pulse signal (PUL) having a first pulse width; a second signal generator generating a pulse signal (PULP) based on the state of the PUL; a third signal generator generating a refresh cutting signal (NERFH) in response to a delayed version of at least one of the PUL and PULP; a fourth signal generator generating a refresh pulse signal (SRFHP) in response to an output from an internal refresh oscillator, and cutting off the SRFHP in response to the NERFH; a first circuit generating a word line duration signal (PWL) in response to the PULP and the SRFHP; and a second circuit for extending the first pulse width of the PUL to a second pulse width in response to the PWL.