Patent ID: 6544859
Filing Date: 2003-04-08
Classification: G03F,H01L,Y10S

Abstract:
A semiconductor processing method of determining alignment during semiconductor wafer processing comprising:forming a first layer over a silicon substrate; forming a first pattern within the first layer, said first pattern defining only a single, four-sided geometric figure; forming a second layer over the first layer; forming an alignment pattern over the second layer, said alignment pattern overlapping with the first pattern to define an alignment pattern portion which, when viewed from a point over the substrate, is disposed outwardly of the four sides of the first pattern; and inspecting said first and alignment patterns and ascertaining from said alignment pattern portion whether a misalignment exists between the patterns, and if so, a magnitude of misalignment, wherein one of said first and alignment patterns defines a rectangle and another of said first and alignment patterns defines a parallelogram having non-right angles.