Patent ID: 7290081
Filing Date: 2007-10-30
Classification: G06F

Abstract:
1. For use in a data processing system capable of executing instruction code in a read-only memory (ROM), a ROM patching apparatus for patching code in said ROM comprising: a patch buffer capable of storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of said code in said ROM; a lockable cache; and core processor logic operable to read from an associated memory a patch table containing a first table entry, said first table entry containing 1) said first new instruction and 2) a first patch address identifying a first patched ROM address of said at least a portion of said code in said ROM, wherein said core processor logic is operable to load said first new instruction from said patch table into said patch buffer, to store said first replacement cache line from said patch buffer into said lockable cache, and to lock said first replacement cache line into said lockable cache to prevent the first replacement cache line from being evicted from the lockable cache; wherein the core processor logic is further operable to set a breakpoint associated with at least one of: a ROM address and a patched ROM address by inserting a breakpoint instruction in the lockable cache.