Patent ID: 7069481
Filing Date: 2006-06-27
Classification: G11B,H04L

Abstract:
1. A data recovery circuit comprising: a phase-locked loop for generating a plurality of clock signals, each of which is synchronized to an input clock signal and has a different delay time; an oversampling unit for non-integer times oversampling serial data which is input from the outside, in response to the plurality of clock signals, and outputting the oversampled result as sample data formed of a plurality of bits; a pattern detector for receiving the sample data formed of the plurality of bits, and generating a pattern signal formed of a plurality of bits by detecting level transitions between bits of the sample data; a state accumulator for receiving the pattern signal formed of the plurality of bits, accumulating the frequency of occurrence of the pattern signal, and outputting the pattern signal having the highest frequency of occurrence as a state signal formed of a plurality of bits if the pattern signal having the highest frequency of occurence is accumulated a predetermined number of times; a state selector for receiving the state signal formed of the plurality of bits, and generating a state selection signal formed of a plurality of bits for selecting bits at predetermined positions in the sample data; and a data selector for receiving the sample data, selecting bits of the sample data in response to the state selection signal, where the bits correspond to the state selection signal, and outputting the selected bits as recovered data formed of a plurality of bits.