Patent ID: 7058791
Filing Date: 2006-06-06
Classification: G06F

Abstract:
1. An apparatus comprising: a first storage location configured to store a first indication, the first storage location addressable by a first instruction defined by a processor architecture, wherein the first indication is an enable indication defined in the processor architecture to indicate whether or not a first mode defined in the processor architecture is to be enabled; a second storage location configured to store a second indication, the second storage location addressable by a second instruction defined by the processor architecture, the second instruction being different from the first instruction, and wherein the second indication is a paging indication defined in the processor architecture to indicate whether or not paging is enabled; a third storage location configured to store a mode indication, the mode indication indicative of whether or not the first mode is active, and wherein the first mode permits an address size greater than 32 bits and an operand size greater than 32 bits; and a processor configured to generate the mode indication responsive to the first indication and the second indication.