Patent ID: 6236248
Filing Date: 2001-05-22
Classification: H03K

Abstract:
An output buffer circuit comprising:an input terminal to which a digital input signal is applied;an output terminal from which a digital output signal is derived according to said applied digital input signal;a pair of a first p-channel MOSFET and a first n-channel MOSFET located in an output stage through which said output signal is derived;a first clamp circuit controlled by said input and output signals for clamping a gate voltage of said first p-channel MOSFET at a first clamp level;a second clamp circuit for clamping a gate voltage of said first n-channel MOSFET at a second clamp level;a first resistor connected to said first clamp circuit for suppressing a current flowing through said first clamp circuit;a second resistor connected to said second clamp circuit for suppressing a current flowing through said second clamp circuit;a first capacitor connected to said first clamp circuit for adjusting said gate voltage of said first p-channel MOSFET through its charging or discharging operation; anda second capacitor connected to said second clamp circuit for adjusting said gate voltage of said first n-channel MOSFET through its charging or discharging operation;wherein said first resistor and said first capacitor are connected in parallel for said first clamp circuit, and electric charges stored in said first capacitor are charged or discharge through said first resistor;and wherein said second resistor and said second capacitor are connected in parallel for said second clamp circuit, and electric charges stored in said second capacitor are charged or discharged through said second resistor;wherein said first clamp circuit clamps said gate voltage of said p-channel MOSFET at said first clamp level for a specific period, thereby increasing a rising rate of said output signal;and wherein said second clamp circuit clamps said gate voltage of said first n-channel MOSFET at said second clamp level for a second specific period, thereby increasing a falling rate of said output signal.