Patent ID: 6412029
Filing Date: 2002-06-25
Classification: H04B

Abstract:
A method for transferring data between a digital processor and a receive buffer in a digital communications device, said receive buffer comprising a double buffered register comprising a master register portion and a slave register portion, said method comprising the steps of:(1) said receive buffer receiving data symbols into said master register portion; (2) responsive to said master register receiving a symbol, transferring said symbol from said master register portion to said slave register portion and locking out said slave register portion from further receipt of data; (3) providing a control circuit for controlling data transfers between said processor and said receive buffer; (4) said receive buffer issuing an interrupt to initiate a transfer of data from said receive buffer to a memory associated with said processor upon said receive buffer being unable to accept any further data without overwriting valid data already in said buffer; (5) said control circuit receiving said interrupt and servicing it so as to transfer data between said receive buffer and said memory, wherein the transfer of data between said receive buffer and said memory comprises reading said data out of said slave register portion; and (6) unlocking said slave register portion after said data in said slave register portion is transferred in accordance with step (5); whereby said processor does not need to service said interrupt.