Patent ID: 6143609
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A method for manufacturing a semiconductor memory, comprising:forming source and drain regions on a semiconductor substrate;forming an active region isolated by an element isolation insulating film on said semiconductor substrate;forming a first insulating film on said active region;sequentially laminating a first conductive film, a second insulating film, a second conductive film and a third insulating film on surfaces of said first insulating film and said element isolation insulating film;etching predetermined portions of said second insulating film, said second conductive film and said third insulating film to form a control gate electrode wherein said etching results in said control gate electrode and said second conductive film having side walls;forming a side wall insulating film on said side walls of said control gate electrode and said second insulating film;etching said first conductive film by using said side wall insulating film as a mask to form a floating gate electrode and to expose only a vertical surface of said floating gate electrode;forming a tunneling insulating film as a tunneling medium only on said vertical surface of said floating gate electrode; andforming an erasing gate electrode made of a third conductive film so as to cover said tunneling insulating film and said side wall insulating film.