Patent ID: 6031773
Filing Date: 2000-02-29
Classification: G11C

Abstract:
A method for stress testing a memory cell oxide of a folded bitline DRAM array comprising memory cells each memory cell having a memory cell reference node vplate, said memory cells being arranged in a linear sequence to form bitlines and grouped into pairs where a first set of alternating wordlines connect memory cells to a half bitline bt and a second set of alternating wordlines connect memory cells to a half bitline bc; a precharge device having a precharge voltage node vbeq; an isolation device having an iso node, a sense amplifier; a bitline precharge enable node pblt; an X decoder device; a wordline clock node rclk; and a (Y select) device for generating YS enable/disable signals; the method comprising the steps of:(a) initializing all nodes connected to said memory cells to a ground voltage (GND) so that no bias current flows in said memory array by the steps of: (i) driving said DRAM into a memory cell oxide stress test mode; (ii) initializing the vbeq line to GND in said test mode; (iii) maintaining the pblt line in its active state connecting all half bitlines bt and bc to the vbeq line; (iv) isolating said sense amplifier from said bitlines by initializing all YS signals and an iso signal on the iso node to GND; and (v) driving vplate node to GND by test control circuitry;(b) disabling wordline boost circuitry so that rclk and said wordlines are only driven to a supply voltage (VDD);(c) activating one or more wordlines; and(d) driving vplate node to a predetermined stress test voltage greater than VDD/2 that was calculated to short out any cell that will not meet a specified reliability criteria.