Patent ID: 6774008
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method for fabricating shallow trench isolation (STI) between deep trench capacitors, comprising the steps of:providing a semiconductor substrate having thereon a pad layer, wherein the semiconductor substrate has a logic area and a memory array area and a plurality of deep trench capacitors are formed within the memory array area, and wherein each of the deep trench capacitors comprises a buried plate in the semiconductor substrate serving as one electrode of the deep trench capacitor, a storage node serving as the other electrode of the deep trench capacitor, a node dielectric layer between the buried plate and the storage node, and a collar oxide disposed at an upper portion of the deep trench capacitor; studding a dielectric layer into a capacitor top recess on each of the deep trench capacitors, and the studded dielectric layer having a top surface that is coplanar with the pad layer; depositing a buffer layer over the semiconductor substrate; depositing a bottom anti-reflection coating (BARC) over the buffer layer; forming a photo mask defining memory array trench openings and logic area trench openings over the BARC; through the memory array trench openings and logic area trench openings, dry etching the BARC, the buffer layer, the pad layer, and then etching into the semiconductor substrate selective to the dielectric layer and the collar oxide that both keep the deep trench capacitors intact, thereby forming isolation trenches between the deep trench capacitors within the memory array area and isolation trenches within the logic area; stripping the photo mask and the BARC; and filling the isolation trenches within the memory array area and the logic area with gap filling material.