Patent ID: 6549994
Filing Date: 2003-04-15
Classification: G11C

Abstract:
A semiconductor memory device, comprising:address input control means for receiving an external write or read address and delaying the write address by 1 cycle when the memory device operates in a write after 1 cycle mode or by 2 cycles when the memory device operates in a write after 2 cycles mode; data input control means for receiving external write data and delaying the write data by a first predetermined number of cycles when the memory device operates in the write after 1 cycle mode, delaying the write data by a second predetermined number of cycles when the memory device operates in the write after 1 cycle mode, delaying the write data by a third predetermined number of cycles when the memory device operates in the write after 2 cycles mode, or delaying the write data by a fourth predetermined number of cycles when the memory device operates in the write after 2 cycles mode; and data transmission control means for transmitting the write data delayed by the first predetermined number of cycles responsive to a first predetermined command sequence, transmitting the write data delayed by the second predetermined number of cycles responsive to a second predetermined command sequence, transmitting the write data delayed by the third predetermined number of cycles responsive to a third command sequence, or transmitting the write data delayed by the fourth predetermined number of cycles responsive to a fourth command sequence; wherein the first predetermined number of cycles is 0, the second predetermined number of cycles is 1, and the third predetermined number of cycles is either 0, 1, or 2; and wherein the first command sequence is a write, write command sequence, the second command sequence is a read, write command sequence, the third command sequence is a write, write, write command sequence, and the fourth command sequence is a write, read, write or write, read, read command sequence.