Patent ID: 7769964
Filing Date: 2010-08-03
Classification: G06F

Abstract:
1. An apparatus comprising: a first logic to determine whether a memory access operation is to access one or more memory regions and to cause a yield event in response thereto, the yield event to invoke an interrupt handler to perform one or more functions in response to the memory access operation accessing the one or more memory regions, wherein the memory access operation is to be preceded in program order by an instruction, for which there is no corresponding load destination address, the instruction to indicate to the first logic that instructions subsequent to the instruction, in program order, are to be monitored for the operation that is to access the one or more memory regions; and wherein a plurality of flag storage areas, coupled to the first logic, is to comprise at least one flag to indicate from a first scenario of a plurality of scenarios to a second scenario of the plurality of scenarios whether the second scenario is to monitor the access to the one or more memory regions.