Patent ID: 6309927
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method of forming a flash memory cell, comprising:forming a tunnel oxide on a substrate;forming a first polysilicon layer over the tunnel oxide;forming an insulating layer on the first polysilicon layer, the insulating layer consisting essentially of an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200.degree. C. to about 650.degree. C. using an organic tantalum compound and an oxygen compound, and heating in an N.sub.2 O atmosphere at a temperature from about 700.degree. C. to about 875.degree. C.;forming a second polysilicon layer on the insulating layer;etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; andforming a source region and a drain region in the substrate, thereby forming at least one memory cell.