Patent ID: 8370731
Filing Date: 2013-02-05
Classification: H03M,H04L

Abstract:
1. An apparatus, comprising: an input to receive an LDPC (Low Density Parity Check) coded signal; and an LDPC decoder to decode the LDPC coded signal using an LDPC matrix to make an estimate of an information bit encoded therein; and wherein: the LDPC matrix, including a plurality of sub-matrices each having a common size, being partitioned into a left hand side matrix and a right hand side matrix; each sub-matrix located on a diagonal of the right hand side matrix being a respective CSI (Cyclic Shifted Identity) sub-matrix corresponding to a cyclic shift of a respective value; within the right hand side matrix, in every row between a top row and a next to bottom row, which being above and adjacent to a bottom row, inclusive, each sub-matrix located on a right hand side of the diagonal of the right hand side matrix being a respective zero-valued sub-matrix; and each sub-matrix of the left hand side matrix being either a respective all zero-valued sub-matrix or a respective CSI sub-matrix.