Patent ID: 6468701
Filing Date: 2002-10-22
Classification: G03F

Abstract:
A stencil mask comprising:a mask pattern layer; and a supporting layer underlying the mask pattern layer for supporting the mask pattern layer, wherein the supporting layer has a multi-layered structure including a top layer which is highest in impurity concentration in all layers of the multi-layered structure forming the supporting layer, and an impurity doped in the supporting layer is a first type impurity having a first property which causes an increase in impurity concentration to reduce an etching rate to the supporting layer, and wherein the multi-layered structure of the supporting layer includes: an impurity doped silicon bulk layer; at least one impurity doped silicon thin layer which is higher in impurity concentration than the impurity doped silicon bulk layer and which extends over the impurity doped silicon bulk layer; and a silicon insulative layer extending over the at least one impurity doped silicon thin layer.