Patent ID: 6034551
Filing Date: 2000-03-07
Classification: G06F,H03K,H04L,Y02D

Abstract:
A low-voltage differential dual receiver apparatus for receiving a value over a line of a bus not being terminated by a bias voltage, said dual receiver comprising:a first input signal being received in said dual receiver;a second input signal being received in said dual receiver and being the complement of said first input signal, said first and second input signals being arranged to transmit said value over said bus line to said dual receiver, wherein said first and second input signals are connected to a common mode reference voltage;a high-speed differential receiver having said first and second input signals as inputs and arranged to produce said value as a high-speed output during a data phase of said bus, said high-speed differential receiver arranged to communicate with a symmetrical driver on said bus line; anda low-speed differential receiver having said first and second input signals as inputs and arranged to produce said value as a low-speed output during a protocol phase of said bus, said low-speed differential receiver including a voltage offset such that during said protocol phase said bus line enters a known state.