Patent ID: 6320467
Filing Date: 2001-11-20
Classification: H03F

Abstract:
An amplifier for amplifying an input current to produce an amplifier output current in response to an input current the amplifier comprising:first, second, and third nodes, said input current being received by the first node;a first amplifier stage connected between said first node and said second node such that said input current passes between said first node and said second node via said first amplifier stage, wherein said first amplifier stage amplifies said input current to produce a first portion of said amplifier output current;a second amplifier stage connected between said second node and said third node such that said input current passes between said second node and said third node via said second amplifier stage, wherein said second amplifier stage amplifies said input current to produce a second portion of said amplifier output current, wherein said first and second amplifier stages include amplifier transistors drawing a bias current of a magnitude I.sub.B from said second node;a reference transistor (Q5) sized and biased in relation to at least one amplifier transistor of said first and second amplifier to produce a base current of magnitude I.sub.B' substantially equal to I.sub.B divided by a constant K; andmeans receiving said base current for generating in response thereto with a current gain substantially equal to K a bias current of magnitude I.sub.B, and for supplying said bias current to said second node.