Patent ID: 7375389
Filing Date: 2008-05-20
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a cell array region formed in a semiconductor substrate and including a capacitor having a lower electrode and an upper electrode, the lower electrode having a lower electrode height; a peripheral circuit region formed in the semiconductor substrate and including a first metal wiring, the first metal wiring having a first metal height and having a lower surface in a substantially planar orientation with a lower surface of the lower electrode; a first insulating layer formed on the cell array region and the peripheral circuit region and having openings; and a second insulating layer formed on the first insulating layer, the first metal wiring being arranged entirely in the second insulating layer, wherein the second insulating layer includes a first sub-layer surrounding the first metal wiring and a second sub-layer formed on the capacitor, the first metal wiring and the first sub-layer, the second sub-layer including a lower layer that is formed substantially along the entire substrate and between the upper electrode and the first metal wiring, and an entire upper layer that is formed substantially along the entire substrate and over the upper electrode, and the first sub-layer is distinct from the second sub-layer, and wherein the capacitor extends at least an entire vertical length of the first sub-layer.