Patent ID: 6369744
Filing Date: 2002-04-09
Classification: H03M

Abstract:
A pipeline ADC comprising a plurality of stages including an input stage and a first group of sequentially coupled subsequent stages,the input stage including a unity gain amplifier having an input for receiving an analog input signal, an output, and at least first and second comparators each having a first input coupled to the output of the unity gain amplifier, the first comparator having a second input for receiving a first reference voltage and an output, the second comparator having a second input for receiving a second reference voltage and an output, and a full adder having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output producing MSB bit information; and each subsequent stage including an amplifier having an input and an output, a summer having a first input coupled to the output of the amplifier of gain greater than 2, a second input, and an output, a switching circuit operating in response to outputs of first and second comparators of a previous stage to selectively couple one of a third reference voltage, a fourth reference voltage, and fifth reference voltage to a second input of the summer, at least first and second comparators each having a first input coupled to the output of the summer, the first comparator of the subsequent stage having a second input for receiving the first reference voltage and an output, the second comparator of the subsequent stage having a second input for receiving the second reference voltage and an output, and a full adder having a first input coupled to the output of the first comparator of the subsequent stage, a second input coupled to the output of the second comparator of the subsequent stage, the full adder producing bit information less significant than the MSB bit information.