Patent ID: 6358781
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A method of protecting high voltage n-channel metal oxide (NMOS) semiconductor transistors from electrostatic discharge (ESD) by parasitic silicon controlled rectifiers (SCR):providing a semiconductor wafer with a p-substrate; forming an n-well in said p-substrate, where said n-well is the drain of a first and a second NMOS transistor; implanting first and second n+ diffusions in said n-well; implanting a first p+ diffusion between said first and said second n+ diffusion; implanting a second and a third p+ diffusion in said p-substrate at opposite sides of said n-well; implanting a third n+ diffusion in said p-substrate between said n-well and said second p+ diffusion and adjacent to said second p+ diffusion; implanting a fourth n+ diffusion in said p-substrate between said n-well and said third p+ diffusion and adjacent to said third p+ diffusion; forming a first gate of said first NMOS transistor between said n-well and said third n+ diffusion; forming a second gate of said second NMOS transistor between said n-well and said sixth n+ diffusion; connecting said first, said second n+ diffusion, and said first p+ diffusion by conductive means; and connecting said third, said fourth n+ diffusion and said second and said third p+ diffusion to a reference potential.