Patent ID: 6212623
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A processor comprising:a dependency vector generation unit configured to generate a dependency vector corresponding to an instruction operation;an instruction queue coupled to receive said dependency vector and said instruction operation, wherein said instruction queue is configured to inhibit scheduling of said instruction operation until each dependency indicated within said dependency vector is satisfied, and wherein said dependency vector is capable of indicating dependencies upon an arbitrary number of other instruction operations within said instruction queue; anda second instruction queue coupled to said dependency vector generation unit and to said instruction queue, wherein said dependency vector comprises an indication corresponding to each of a plurality of queue entries within said instruction queue and to each of a second plurality of queue entries within said second instruction queue, and wherein said indication, in a first state, is indicative of a dependency upon a corresponding entry from one of said plurality of queue entries or said second plurality of queue entries, and wherein said indication, in a second state, is indicatives of a lack of dependency upon the corresponding entry.