Patent ID: 7132331
Filing Date: 2006-11-07
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a plurality of field isolation patterns on a semiconductor substrate to define a plurality of active regions in the semiconductor substrate; increasing the density of the field isolation patterns by thermally annealing the field isolation patterns; forming a plurality of gate insulation patterns on respective of the active regions; forming a first conductive layer on the gate insulation patterns and on the field isolation patterns; and planarizing the first conductive layer at least to the depth of the top surfaces of the field isolation patterns to form a plurality of first conductive patterns on respective of the gate insulation patterns; and forming first and second conductive spacers on sidewalls of at least some of the first conductive patterns; planarizing the first conductive layer at least to the depth of the top surfaces of the field isolation patterns to form a plurality of first conductive patterns on respective of the gate insulation patterns; forming first and second conductive spacers on sidewalls of at least some of the first conductive patterns.