Patent ID: 6399430
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method of manufacturing a field effect transistor having a preselected build up resistance with respect to an I-V characteristic of said transistor, comprising the steps of:forming a first GaAs layer on a GaAs substrate; forming an AlGaAs layer on said first GaAs layer, said AlGaAs layer having a predetermined impurity concentration and a preselected Al composition ratio; forming a second GaAs layer on said AlGaAs layer; etching said second GaAs layer to form a recess; forming a gate electrode on said AlGaAs layer and in the recess to form a schottky contact with said AlGaAs layer; and forming source and drain regions on said second GaAs layer; the Al composition ratio of said AlGaAs layer on said first GaAs layer and the impurity concentration falling within the range surrounded by the following lines (a), (b) and (c) and a curve (d) in a graph showing a relation between the Al composition ratio and the impurity concentration, wherein: (a) a line which is specified by the composition ratio of 0.1; (b) a line which is specified by the impurity concentration 5Ã—1017 cmâˆ’3; (c) a line which is specified by the impurity concentration of 1Ã—1016 cmâˆ’3; (d) a curve for smoothly connecting four points of the impurity concentration of 1Ã—1016 cmâˆ’3 at the Al composition ratio of 0.16, the impurity concentration of 5Ã—1016 cmâˆ’3 at the Al composition ratio of 0.17, the impurity concentration of 1Ã—1017 cmâˆ’3 at the Al composition ratio of 0.18, and the impurity concentration of 5Ã—1017 cmâˆ’3 at the Al composition ratio of 0.25.