Patent ID: 7474612
Filing Date: 2009-01-06
Classification: H04J

Abstract:
1. A bypass port comprising: an input multiplexer for receiving an input from a current port input or a bypass input; a clock and data recovery (CDR) unit for receiving a data stream from the input multiplexer, and for extracting a recovered clock from the data stream; a retimer circuit coupled to the CDR unit and for communication with an elastic buffer for retiming data to a local clock; a retransmit multiplexer coupled to the CDR unit for retransmitting data synchronous to the recovered clock in response to data received from the CDR unit, and coupled to the retimer circuit for retransmitting data synchronous to the local clock in response to data received from the retimer circuit; and an output multiplexer coupled to the input multiplexer for performing a bypass function in response to data received from the input multiplexer, and coupled to the retransmit multiplexer for outputting data in response to data received from the retransmit multiplexer, the output multiplexer for outputting data to a current port output or a bypass output.