Patent ID: 6828629
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a gate insulating film and a gate electrode formed on said semiconductor substrate; a pair of first sidewall insulating films formed on the lateral portions of said gate electrode; a pair of second sidewall insulating films formed so as to sandwich said first sidewall insulating films with said gate electrode, and having a width larger than that of said first sidewall insulating films; a pair of first N-type impurity-diffused layers containing phosphorus formed in the surficial portion of said semiconductor substrate at a first depth so as to be self-aligned with respect to said gate electrode and said first sidewall insulating films; a pair of second N-type impurity-diffused layers formed in the surficial portion of said semiconductor substrate at a second depth deeper than said first depth so as to be self-aligned with respect to said gate electrode, said first sidewall insulating films and said second sidewall insulating films; and a pair of P-type impurity-diffused layers formed between said pair of second N-type impurity-diffused layers, and respectively in adjacent to each of said pair of first N-type impurity-diffused layers.