Patent ID: 7237214
Filing Date: 2007-06-26
Classification: G06F

Abstract:
1. A method for circuit partitioning, the method comprising: evaluating a design goal indicator, the design goal indicator being a function of a partitioning solution for a circuit and a function of a trace assignment solution for the circuit, the design goal indicator being evaluated based on a first partitioning solution for the circuit and a first trace assignment solution for the circuit, the circuit being partitioned into a plurality of partitions, the plurality of partitions containing a plurality of first portions of the circuit respectively in the first partitioning solution, first nets of the circuit interconnecting the plurality of the first portions, at least a portion of the first nets being assigned to traces in the first trace assignment solution, the traces being wiring resources available for interconnecting portions of the circuits in the plurality of partitions; and improving the design goal indicator through modifying the first partitioning solution to generate a second partitioning solution and through modifying the first trace assignment solution to generate a second trace assignment solution, the plurality of partitions containing a plurality of second portions of the circuit respectively in the second partitioning solution, second nets of the circuit interconnecting the plurality of the second portions, at least a portion of the second nets being assigned to traces in the second trace assignment solution.