Patent ID: 7344935
Filing Date: 2008-03-18
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device having a semiconductor substrate, a planar MOSFET exhibiting a low breakdown voltage on the semiconductor substrate, and a trench lateral MOSFET exhibiting a high breakdown voltage, the method comprising: forming one or more well regions of a first conductivity type and one or more well regions of a second conductivity type in a surface of the semiconductor substrate; forming an oxide film on the surface of the semiconductor substrate to form a mask; forming a trench, using the oxide mask, in one of the well regions of the second conductivity type for forming the trench lateral MOSFET; forming an expanded drain region of the second conductivity type around the trench; forming a thick oxide film on an inner side wall of the trench; etching a bottom of the trench to a level that is deeper than a lower edge of the expanded drain region using the thick oxide film as a mask; removing the oxide film on the surface of the semiconductor substrate; forming a nitride mask on the surface of the semiconductor substrate and an inner surface of the trench, the mask being a nitride film, and a part thereof being selectively removed; forming a selective oxide film using the nitride mask; forming gate oxide films inside the trench and on the surface of one of the well regions of the first conductivity type for forming the planar MOSFET; forming gate electrodes on the respective gate oxide films; forming a base region of the first conductivity type in the bottom of the trench; forming a source region of the second conductivity type in the bottom of the trench, the base region being deeper than the source region, forming a drain region of the second conductivity type outside an upper portion of the trench, and forming diffusion regions of the second conductivity type selectively in the well region of the first conductivity type for forming the planar MOSFET, one of the diffusion regions operating as a source or a drain of the planar MOSFET and the other one of the diffusion regions operating as a drain or a source of the planar MOSFET; forming an interlayer insulation film on the surface of the semiconductor substrate and inside the trench; removing a portion of the interlayer insulation film on the bottom of the trench to expose the source region; filling the trench with a contact electrode; and forming a metal electrode connected to the contact electrode, forming metal electrodes connected to the respective gate electrodes, forming a metal electrode connected to the drain region, and forming metal electrodes connected to the respective diffusion regions.