Patent ID: 6434640
Filing Date: 2002-08-13
Classification: G06F

Abstract:
An interface logic comprising:a receive buffer coupled to receive data, wherein said receive buffer includes a plurality of storage locations, and wherein each of said plurality of storage locations is capable of storing said data; a load counter coupled to said receive buffer and to receive a first clock signal, wherein said load counter is configured to provide a first pointer which selects one of said plurality of storage locations to store said data, said load counter configured to modify said first pointer responsive to said first clock signal; an unload counter coupled to said receive buffer and to receive a second clock signal, wherein said load counter is configured to provide a second pointer which selects one of said plurality of storage locations to transmit data out of said receive buffer, said unload counter configured to modify said second pointer responsive to said second clock signal; and an unload counter adjust logic coupled to said unload counter and to receive said first clock signal and said second clock signal, wherein said unload counter adjust logic is configured to modify said second pointer responsive to differences between said first and second clock signals.