Patent ID: 7634586
Filing Date: 2009-12-15
Classification: G06F

Abstract:
1. An address check validation circuit in a switching device implemented in a system conforming to PCI Express standards, the system comprising a plurality of communication ports, each of said communication ports being electronically coupled to an external electronic device and each of said communication ports being associated with a base address, a limit address and a port identifier, the address check validation circuit comprising: a base address register array comprising a plurality of base address registers, each base address register having content that includes the base address, the limit address and the port identifier associated with each of the plurality of communication ports, the plurality of base address registers in the base address register array are sorted into either a descending or ascending order; a base address comparator electrically coupled to the base address register array to receive content of a base address register from the sorted base address register array and to receive a communication packet comprising a target address, said base address comparator operable to compare said base address register to said target address following either the descending or ascending order of the sorted base address register array to identify a matching base address in the base address register array; and a limit address comparator electrically coupled to receive said target address and said limit address, said limit address comparator functioning concurrently with said base address comparator for generating output that indicates whether said target address is valid, and if said target address is valid, said limit address comparator for transmitting a port identifier associated with the matching base address to the switching device.