Patent ID: 8803248
Filing Date: 2014-08-12
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate pattern comprising a gate insulation layer and a gate electrode formed on a substrate; a source/drain region formed at substantially opposite sides of the gate pattern; a silicide layer formed on the source/drain region; an insulation layer formed on the gate pattern and the source/drain region; and a contact hole formed through the insulation layer and exposing a predetermined region of the silicide layer, wherein the gate pattern and the source and drain regions have a step difference between a top portion of the gate pattern and a top portion of the source and drain regions of about 250 Å or less from the substrate, wherein the gate pattern and the source/drain region have an aspect ratio of less than about 3:1, and wherein the aspect ratio is a ratio of the step difference between the top portion of the gate pattern and the top portion of the source/drain region to a width of the source/drain region.