Patent ID: 9183022
Filing Date: 2015-11-10
Classification: G06F

Abstract:
1. A method comprising: storing in one or more hardware registers a first value and a second value, wherein the first value is associated with a first virtual machine (VM) and the second value is associated with a second VM, wherein when the first VM and not the second VM runs on a shared processor during the first VM's scheduled regular time interval, a hardware memory controller is to reset a bandwidth counter to the first value associated with the first VM by copying the first value from the one or more hardware registers, and then decrement the bandwidth counter, without involvement of any VM or the hypervisor, each time the first VM accesses a hardware memory over the bus when running on the shared processor, wherein when the second VM and not the first VM runs on the shared processor during the second VM's scheduled regular time interval, the hardware memory controller is to reset the bandwidth counter to the second value associated with the second VM by copying the second value from the one or more hardware registers, and then decrement the bandwidth counter, without involvement of any VM or the hypervisor, each time the second VM accesses the hardware memory over the bus when running on the shared processor, wherein the bandwidth counter tracks usage of the bus for the hardware memory by each VM of the first VM and the second VM on a per-VM basis; and responsive to the bandwidth counter reaching a zero value when the first or second VM running in the shared processor at the first or second VM's respective scheduled regular time interval, issuing an interrupt by the hardware memory controller for handling by the hypervisor to maintain bandwidth quality-of-service (QoS) of bus bandwidth related to the hardware memory, wherein the hardware memory and the hardware memory controller are each hardware different than the processor, wherein the bandwidth counter and the one or more hardware registers are implemented directly in hardware as opposed to being software-implemented and are directly accessible by the hardware memory controller.