Patent ID: 6350695
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A method of fabricating an integrated circuit multilevel interconnection comprising:providing an insulating layer overlying semiconductor device structures in and on a semiconductor substrate; depositing a first conductive layer overlying said insulating layer; depositing a conductive etch stop layer overlying said first conductive layer; patterning said conductive etch stop layer to form openings to said first conductive layer; depositing a via metal layer overlying said conductive etch stop layer and said first conductive layer within said openings; depositing a hard mask layer overlying said via metal layer; patterning said hard mask layer to form openings to said via metal layer; anisotropically etching said via metal layer not covered by said hard mask layer to said conductive etch stop layer and said first conductive layer not protected by said conductive etch stop layer thereby forming pillars in said via metal layer; anisotropically etching said first conductive layer not covered by said conductive etch stop layer to said insulating layer thereby creating a first trench in said first conductive layer; depositing an inter-metal dielectric layer covering said pillars and said hard mask layer and filling said first trench; planarizing said inter-metal dielectric layer; thereafter patterning said inter-metal dielectric layer to form second trenches in said inter-metal dielectric layer wherein each second trench overlies one of said pillars; etching away said hard mask layer within said second trenches thereby exposing the tops of said pillars; thereafter depositing a second conductive layer within said second trenches; and planarizing said second conductive layer to a surface of said inter-metal dielectric layer thereby forming conductive traces comprising said pillars and overlying second conductive layer-filled second trenches to complete fabrication of said integrated circuit multilevel interconnection.