Patent ID: 7894293
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. A memory device a plurality of memory core layers each including a plurality of through electrodes; and an interface chip including a plurality of electrodes; the memory core layers being stacked over the interlace chip with one another such that the through electrodes of a lower one of the memory core layers are connected respectively to the through electrodes of an upper one of the memory core layers and the through electrodes of a lowest one of the memory core layers are connected respectively to the through electrodes of the interface chip; each of the memory core layers further including a plurality of memory banks each containing a plurality of memory cells; the interface chip generating bank address information and supplying the bank address information in common to the memory core layers via the through electrodes to designate memory banks belonging respectively to the memory core layers; the interface chip further generating row address information and supplying the row address information in common to the memory core layers via the through electrodes, the row address information comprising a more significant bit part and a less significant bit part, one or more bits belonging to the more significant bit part being allocated as layer selection information to select one of the memory core layers; and the interface chip performing, in response at least to the less significant bit part of the row address information, a data read/write operation on a memory bank which is contained in the memory banks designated by the bank address information and which belongs to one of the memory core layers that is selected by the one or more bits belonging to the more significant bit part of the row address information.