Patent ID: 6372632
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of forming a planarized metal interconnect, comprising the steps of:providing a semiconductor structure; forming a low K dielectric layer over said semiconductor structure, said low K dielectric layer having an upper surface; forming a sacrificial layer over said low K dielectric layer; said sacrificial layer having an upper surface; patterning said sacrificial layer and said low K dielectric layer to form a trench within said sacrificial layer and said low K dielectric layer; forming a barrier layer over said sacrificial layer and lining said trench side walls and bottom; depositing metal on said barrier layer to form a metal layer filling said lined trench and blanket filling said sacrificial-layer-covered low K dielectric layer; planarizing said metal layer and said barrier layer on said upper surface of said sacrificial layer using a first step chemical mechanical polishing process of a two step chemical mechanical polishing process, exposing said upper surface of said sacrificial layer; and removing said sacrificial layer using a second step chemical mechanical polishing process, having high selectivity to said sacrificial layer, of said two step chemical mechanical polishing process to form a planarized metal interconnect, wherein said sacrificial layer removal is performed by oxide buffing using a slurry including SiO2, Al2O3, or CaO2 solid abrasives; H2O2; a surfactant; and KOH.