Patent ID: 6411141
Filing Date: 2002-06-25
Classification: H03L,Y10S

Abstract:
A phase locked loop circuit comprising:an internal clock generation circuit receiving a reference clock and a comparison clock to produce an internal clock in response to said reference clock and said comparison clock, said comparison clock corresponding to said internal clock; and a phase lock signal generation circuit receiving said reference clock and said comparison clock to produce a phase lock signal and to release said phase lock signal; said phase lock signal generation circuit including a phase difference signal generation circuit outputting a phase matching signal when phases of said reference clock and said comparison clock are matching and a phase mismatching signal when phases of said reference clock and said comparison clock are mismatching, and a phase detection circuit having a plurality of signal paths each for producing a detection clock, each of said detection clocks having an activated level having different timing, at least two activated levels of said detection clocks being overlapped, each signal path detecting a plurality of said phase mismatching signals during a corresponding one of the activated detection clocks to release said phase lock signal.