Patent ID: 6553088
Filing Date: 2003-04-22
Classification: H03K,H03L

Abstract:
A digital delay phase locked loop, used to receive a clock signal and perform a phase lock to output a phase locked clock signal, the digital delay phase locked loop comprising:a delay apparatus, to receive the clock signal to perform a phase lock, and to output a delay data signal; a buffer, to receive the delay data signal and to output the phase locked clock signal; a phase comparing converter, to receive and to obtain a time difference between the clock signal and the phase locked clock signal, and to convert the time difference into a comparison signal in digits for output; an adder-register, to receive and temporary store the comparison signal; a clock divider, to receive the clock signal and to output a data refresh signal to the adder-register, so that a modified signal is output by the adder-register; and a demultiplexer, to receive the modified signal and to output a control signal to the delay apparatus to control the delay function to achieve phase lock.