Patent ID: 6742077
Filing Date: 2004-05-25
Classification: G06F

Abstract:
A memory access controlling system for hierarchically interleaving a memory in a unit of memory module and accessing the memory, comprising:a bank control table having entries corresponding to memory units, each of said entries containing data for a plurality of the memory modules, said data for each of said memory modules having a presence bit and a source address to be converted to a row address of the memory module concerned, said presence bit representing whether or not a memory device is mounted on the memory module concerned; an address bit position table containing information which represents both the number of bits of the row address and the number of bits of the column address of a memory device, if any, mounted on each of said memory modules; a decoder for obtaining the number of the memory unit to be accessed on the basis of a line address which is supplied from an access source; a number determining portion for determining the memory module to be accessed on the basis of said line address and the presence bit in the data contained in an entry of said bank control table having the number obtained by said decoder; and an address determining portion for searching said address bit position table for information that represents both the number of bits of the row address and the number of bits of the column address of the memory device mounted on the memory module determined by said number determining portion, and in addition determining both the row address and the column address of the memory module to be accessed on the basis of said line address, a source address to be converted to the row address of the memory module to be accessed, said source address being included in data contained in the entry having the number obtained by said decoder, and the searched information representing both the number of bits of the row address and the number of bits of the column address; a buffer group for storing a plurality of implementation addresses, each of which is composed of the number of the memory module determined by said number determining portion and the row address and column address determined by said address determining portion; and an arbitrator for arbitrating the plurality of implementation addresses stored in said buffer group.