Patent ID: 8035164
Filing Date: 2011-10-11
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; a plurality of piezoelectric devices disposed on the substrate; a plurality of MOS transistors, a stress of a channel region of one of the plurality of MOS transistors being controlled by one of the plurality of piezoelectric devices, the channel region being included in a semiconductor layer; and a plurality of insulators, one of the plurality of insulators departing the channel region of the one of the plurality of MOS transistors and the one of the plurality of piezoelectric devices, each of the plurality of piezoelectric devices including a first electrode, a piezoelectric body, and a second electrode, a voltage being applied between the first electrode and the second electrode, a plurality of semiconductor layers of the plurality of MOS transistors being separately disposed on a first surface of the substrate, the plurality of piezoelectric bodies each corresponding to a respective one of the plurality of piezoelectric devices being separately disposed on the first surface of the substrate, and when viewed from a normal line of the first surface, a first electrode and a second electrode of the one of the plurality of piezoelectric devices sandwiching a piezoelectric body corresponding to the one of the plurality of piezoelectric devices toward a channel width direction of a P-channel MOS transistor of the plurality of MOS transistors, the one of the plurality of piezoelectric devices controlling the stress of the channel region of the P-channel MOS transistor, and a first electrode and a second electrode of another one of the plurality of piezoelectric devices sandwiching a piezoelectric body corresponding to the another one of the plurality of piezoelectric devices toward a thickness direction of the piezoelectric body corresponding to the another one of the plurality of piezoelectric devices, the another one of the plurality of piezoelectric devices controlling the stress of the channel region of a N-channel MOS transistor of the plurality of MOS transistors.