Patent ID: 8138541
Filing Date: 2012-03-20
Classification: H01L

Abstract:
1. A memory cell, comprising: a floating body containing a doped semiconductor material; a gated diode; the gated diode having a section doped to a same conductivity type as the floating body; said section of the gated diode being electrically connected to the floating body through an electrical connection that extends from said section of the gated diode to the floating body; a gate configured to gate the gated diode; wherein the floating body and the gated diode are supported by a semiconductor base and are laterally spaced from one another; and further comprising an isolation region extending into the base in the space between the floating body and the gated diode; wherein the semiconductor base has a planar upper surface; wherein a layer of dielectric material is over the planar upper surface, with the layer of dielectric material having a planar upper surface; wherein the isolation region comprises electrically insulative material that extends through the layer of dielectric material; wherein the floating body is over and directly against the planar upper surface of the layer of dielectric material; wherein the gate is over and directly against the planar upper surface of the dielectric material; and wherein the electrical connection is comprised by a wire extending over the electrically insulative material of the isolation region, and across the planar upper surface of the dielectric material.