Patent ID: 6480036
Filing Date: 2002-11-12
Classification: G11C

Abstract:
A computer system, comprising:a central processing unit connected to a memory system by a system bus; an I/O system, connected to the system bus by a bus interface device; and at least one sense amplifier, for sensing a first and second logic level of a first data signal and a second data signal contained in said central processing unit and for outputting representations of that logic level on complementary output terminals, said sense amplifier including: a first discharge path, connected to a first one of said output terminals, for allowing a charge stored on said first one of said output terminals to be discharged at a first rate that is proportional to a voltage level developed on said first data signal; a second discharge path, connected to a second one of said output terminals, for allowing a charge stored on said second one of said output terminals to be discharged at a second rate that is proportional to a voltage level developed on a second data signal; a set and reset circuit for overriding said discharge of said first one of said output terminals in response to an assertion of a first control signal and for overriding said discharge of said second one of said output terminals in response to an assertion of a second control signal; a pre-charge unit coupled to said first and second output terminals to pre-charge said first and second output terminals with the charges; and first and second disabling circuits cross-coupled to said output terminals and in said first and second discharge paths, respectively, to disable, as a function of the discharge rates, said first or second output terminal from discharging.