Patent ID: 6693331
Filing Date: 2004-02-17
Classification: H01L

Abstract:
A microelectronic device, comprising:a first NFET and a second NFET, the first NFET having a threshold voltage that is lower than the threshold voltage of the second NFET, each NFET having a channel region; a first PFET and a second PFET, the first PFET having a threshold voltage that is lower than the threshold voltage of the second PFET, each PFET having a channel region; a first NFET channel region having a first concentration of a p-type dopant and a second concentration of a p-type dopant therein; a second NFET channel region having a first concentration of a p-type dopant, a second concentration of a p-type dopant, and a third concentration of a p-type dopant therein; a second PFET channel region having a first concentration of an n-type dopant and a second concentration of an n-type dopant therein; and a first PFET channel region having a first concentration of an n-type dopant, a second concentration of an n-type dopant, and a third concentration of a p-type dopant therein.