Patent ID: 7151034
Filing Date: 2006-12-19
Classification: H01L

Abstract:
1. A method for manufacturing semiconductor device, the method comprising the steps of: (a) forming a device isolation film defining an active region on a semiconductor substrate, the semiconductor substrate having a SiGe epitaxial layer and a first Si epitaxial layer stacked thereon; (b) sequentially forming a gate insulating film, a gate conductive layer and a first CVD insulating film on the first Si epitaxial layer and the device isolation film; (c) patterning the first CVD insulating film and the gate conductive layer to form a gate structure having a first side and a second side; (d) forming an LDD region on the first Si epitaxial layer at both sides of the gate structure; (e) forming a first sidewall spacer and a second sidewall spacer on the first side and the second side respectively; (f) at least etching a portion of the gate insulating film adjacent to the first sidewall spacer and the second sidewall spacer to expose a portion of the first Si epitaxial layer; (g) etching the exposed portion of the first Si epitaxial layer to expose a portion of the SiGe epitaxial layer; (h) etching the SiGe epitaxial layer adjacent to the first side and a predetermined thickness of the semiconductor substrate thereunder, wherein the SiGe epitaxial layer is partially etched so as to form a first undercut under the first Si epitaxial layer; (i) forming a second Si epitaxial layer in a space including the first undercut, wherein the second Si epitaxial layer at least fills up the first undercut; (j) performing an etching process to expose the SiGe epitaxial layer adjacent to the second side; (k) etching the SiGe epitaxial layer exposed in the step (j), wherein the SiGe epitaxial layer is removed so as to form a second undercut under the first Si epitaxial layer; (l) forming a buried oxide film filling up the second undercut in a space formed by removing the SiGe epitaxial layer; (m) forming a polysilicon layer on the buried oxide film filling up a space formed by removing the gate insulating film and the first Si epitaxial layer; and (n) implanting an impurity into the second Si epitaxial layer and the polysilicon layer to form a source/drain region.