Patent ID: 9020064
Filing Date: 2015-04-28
Classification: H04L

Abstract:
1. A multilevel signal transmitting apparatus comprising: a first driver circuit configured to generate a multilevel data signal with a number M of voltage levels, and a second driver circuit configured to generate a multilevel clock signal with a number (M−2) of voltage levels, where M is an even number equal to or more than four, wherein the number M of voltage levels of the multilevel data signal include a number M/2 of first voltage levels larger than a predetermined reference voltage level, and a number M/2 of second voltage levels smaller than the reference voltage level, wherein between each pair of adjacent voltage levels selected among the number M/2 of first voltage levels of the multilevel data signal, one of the number (M−2) of voltage levels of the multilevel clock signal is set, wherein between each pair of adjacent voltage levels selected among the number M/2 of second voltage levels of the multilevel data signal, one of the number (M−2) of voltage levels of the multilevel clock signal is set, and wherein an average of the voltage levels of the multilevel clock signal for a predetermined time has a value between a minimum of the number M/2 of first voltage levels of the multilevel data signal, and a maximum of the number M/2 of second voltage levels of the multilevel data signal.