Patent ID: 7030658
Filing Date: 2006-04-18
Classification: H03K

Abstract:
1. A system comprising: a first logic circuit configured to receive one or more logic circuit input signals and to generate a logic circuit output signal; and a multiplexer configured to receive the logic circuit output signal and one or more additional signals as multiplexer input signals, wherein the multiplexer is configured to receive a select signal that controls the multiplexer to select one of the multiplexer input signals to be provided as a multiplexer output signal; wherein when the select signal controls the multiplexer to select the logic circuit output signal as the multiplexer output signal, the first circuit operates in a first mode, and when the select signal controls the multiplexer to deselect the logic circuit output signal as the multiplexer output signal, the first circuit operates in a second mode wherein the second mode comprises a power-saving mode.