Patent ID: 7424622
Filing Date: 2008-09-09
Classification: G06F

Abstract:
1. A microprocessor, comprising: a task state table configured to assign a task identifier to a task that can take any one of a plurality of states, and store a state of the task in correspondence to the task identifier; a task register configured to store the task identifier of a currently executed task; an interface configured to read a program in units of cache lines, when a request for the task is made, the program being stored in an encrypted form obtained by using a program key at an external memory; an encryption processing unit configured to generate decryption keys that are different for different cache lines according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines, each cache line having a tag, and configured to store the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit configured to compare the task identifier stored in the tag of each cache line with a value of the task register, and discard a content of each cache line when the task identifier in the tag and the value of the task register do not coincide.