Patent ID: 6281115
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A method for forming a via hole in a photosensitive low dielectric constant layer, on a semiconductor substrate, with said via hole formed without the use of photoresist patterning procedures, and with said via hole then protected with silicon oxide spacers, comprising:providing said semiconductor substrate containing active device regions and providing a dielectric layer, overlying active device regions;forming a first interconnect metal structure on said dielectric layer;applying said photosensitive low dielectric constant layer on said first interconnect metal structure and on said dielectric layer, in regions in which said underlying dielectric layer is not covered by said first interconnect metal structure;directly exposing a first portion of said photosensitive low dielectric constant layer to a light source, forming a non-soluble material in said first portion of said low dielectric constant layer, leaving a non-exposed, soluble region in a second portion of said photosensitive low dielectric constant layer, directly overlying said first metal interconnect structure;selectively removing soluble material from said second portion of said photosensitive low dielectric constant layer, creating said via hole in said photosensitive low dielectric constant layer, exposing the top surface of said first interconnect metal structure;depositing a silicon oxide layer, with a thick portion of said silicon oxide layer deposited on the top surface of said photosensitive low dielectric constant layer, and with a thin portion of said silicon oxide layer deposited on the sides of the photosensitive low dielectric constant layer exposed in said via hole, and on the top surface of said first interconnect metal structure exposed in said via hole;planarizing to create a smooth top surface topography in regions in which said silicon oxide layer overlays said photosensitive low dielectric constant layer;performing a blanket, anisotropic dry etching to remove said thin portion of said silicon oxide layer from the top surface of said first interconnect metal structure exposed in said via hole, forming said silicon oxide spacers on the sides of said via hole, while leaving a segment of said thick portion of said silicon oxide layer remaining on the top surface of said photosensitive low dielectric layer, creating a silicon oxide protected via hole, located in said photosensitive low dielectric constant layer; andforming a second interconnect metal structure, with a first portion of said second interconnect metal structure in said silicon oxide protected via hole, and with a second portion of said second interconnect metal structure on said silicon oxide layer, in a region in which said silicon oxide layer overlays the top surface of said photosensitive low dielectric layer.