Patent ID: 8378874
Filing Date: 2013-02-19
Classification: H03K,H03M

Abstract:
1. An analog to digital converter comprising: a reset transistor comprising a first gate, a first drain, and a first source; at least two inverters cascadedly-arranged for amplifying and generating a digital signal, the cascaded inverters comprising a first input coupled to the first drain of the reset transistor, and a first output; a inverter circuit comprising a plurality of inverters, the plurality of inverters are coupled to one another in a parallel relationship, the inverter circuit comprising a first input coupled to the output of the cascaded inverters and a first output; a buffer circuit comprising a plurality of buffers, the plurality of buffers are coupled to one another in a parallel relationship, the buffer circuit comprising a first input coupled to the first output of the inverter circuit and a first output; and a D flip flop circuit comprising a D input, a Q output, a notQ output, and a CLK output, the D input is coupled to the first output of the buffer circuit, and the CLK output is coupled to the gate of the reset transistor.