Patent ID: 6741093
Filing Date: 2004-05-25
Classification: G01R,H01L

Abstract:
A method of determining one or more properties of a semiconductor wafer having a dielectric layer overlaying at least a portion thereof, the method comprising the steps of:(a) providing a semiconductor wafer having a pattern of integrated circuits formed thereon and scribe lines separating the integrated circuits from one another; (b) providing a probe having an elastically deformable, electrically conductive tip; (c) causing the probe tip to contact a dielectric layer overlaying at least a portion of one of the scribe lines of the semiconductor wafer thereby forming a metal-oxide-semiconductor (MOS) structure, the probe tip having a contact area that is received within said scribe line when the probe tip contacts the dielectric layer; (d) applying an electrical stimulus to the MOS structure; (e) measuring a response of the MOS structure to the electrical stimulus; and (f) determining from the response at least one property of at least one of the dielectric layer, the semiconductor wafer and the interface therebetween.