Patent ID: 6448608
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A flash memory device, comprising:a substrate with a surface; at least one periphery stack formed on the substrate surface, said at least one periphery stack being undamaged; at least one core stack formed on the substrate surface, said at least one core stack being undamaged; at least one shallow source region formed within the substrate, said at least one core stack being disposed adjacent to the at least one source region; at least one shallow drain region formed within the substrate, each said at least one core stack being disposed adjacent to the at least one drain region; at least one deep source implant region formed within the substrate, each said at least one deep source region surrounding the at least one shallow source region; a barrier layer formed on the at least one core stack, the at least one periphery stack, and at least one portion of the substrate surface; a protective layer formed on the barrier layer; and an insulating layer formed on the protective layer, wherein an absence of self-aligned source etch eliminates any damage to the at least one periphery stack and the at least one core stack.