Patent ID: 6504218
Filing Date: 2003-01-07
Classification: H01L

Abstract:
An IGFET pair, comprising:an asymmetrical N-channel IGFET, including: a first gate insulator on a first active region of a semiconductor substrate; a first gate on the first gate insulator, wherein the first gate includes opposing sidewalls formed during a single etch step; a first source including a first heavily doped source region adjacent to a first ultra-heavily doped source region, wherein the first heavily doped source region forms a first channel junction and the first ultra-heavily doped source region is spaced from the first channel junction; and a first drain including a first lightly doped drain region adjacent to a first heavily doped drain region, wherein the first lightly doped drain region forms a second channel junction and the first heavily doped drain region is spaced from the second channel junction, and the first ultra-heavily doped source region has a greater doping concentration than any portion of the first drain; and an asymmetrical P-channel IGFET, including: a second gate insulator on a second active region of the semiconductor substrate; a second gate on the second gate insulator, wherein the second gate includes opposing sidewalls formed during a single etch step; a second source including a second heavily doped source region adjacent to a second ultra-heavily doped source region, wherein the second heavily doped source region forms a third channel junction and the second ultra-heavily doped source region is spaced from the third channel junction; and a second drain including a second lightly doped drain region adjacent to a second heavily doped drain region, wherein the second lightly doped drain region forms a fourth channel junction and the second heavily doped drain region is spaced from the fourth channel junction, and the second ultra-heavily doped source region has a greater doping concentration than any portion of the second drain.