Patent ID: 9032346
Filing Date: 2015-05-12
Classification: G06F

Abstract:
1. A method comprising: receiving a plurality of first checksums corresponding to respective first geometric element errors waived on a per geometric element violation basis for each corresponding first checksum where each respective geometric element is part of a block of an integrated circuit design and each respective geometric element relates to edges, polygons, shapes, and/or vertices of a structure defining a portion of a physical integrated circuit, the plurality of first checksums being based on a first version of at least one design verification rule; receiving a second checksum corresponding to a second geometric element error associated with the block, the second checksum being based on a second version of the at least one design verification rule; determining whether the second checksum corresponds to at least one of the plurality of first checksums; and generating, if the second checksum does not correspond to at least one of the plurality of first checksums, a waiver request for the second geometric element error, wherein at least one step of said method is executed by a processor and the processor utilizes one or more parameters associated with waived geometric element violations for generating regression information.