Patent ID: 6420248
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method of manufacturing a double gate oxide layer comprising the steps of:providing a substrate having a plurality of trenches which divide the substrate into a memory circuit region and a logic circuit region; forming a dielectric layer on the substrate to fill the trenches; removing the dielectric layer of the logic region, thereby exposing the substrate; performing an ion implantation step on the substrate of the logic circuit region using a reverse tone mask; forming a conformal barrier layer that completely covers the substrate; forming a spin-on layer over the barrier layer; performing a chemical mechanical polishing step to remove the spin-on layer, the barrier layer, and dielectric layer outside the trenches, thereby exposing the substrate; and performing a thermal oxidation step to form a double gate oxide layer that is thicker in the memory circuit region than it is in the logic circuit region.