Patent ID: 6297127
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A method of forming an integrated circuit having a set of deep isolation trenches aligned with shallow isolation trenches, comprising the steps of:depositing consecutively on a silicon substrate a set of layers comprising a pad oxide layer, a pad nitride layer, a first polish stop layer and a second polish stop layer;etching a set of shallow trenches through said set of layers and into said silicon substrate, said set of shallow trenches having interior sidewalls;forming interior spacers on the interior sidewalls of said shallow trenches;forming an etch-resistant plug within at least some of said set of shallow trenches and between said interior spacers;removing said interior spacers, thereby forming a set of deep trench apertures between said etch-resistant plugs and said interior sidewalls of said shallow trenches;etching a set of deep trenches in said deep trench apertures; andfilling said deep trenches and said shallow trenches with an insulating material.