Patent ID: 7273809
Filing Date: 2007-09-25
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a chalcogenide memory cell, comprising: applying a layer of a first material onto a conductive substrate material; forming an edge feature in said layer of said first material; applying a layer of an insulative material onto said edge feature of said layer of said first material; applying a layer of a third material onto said layer of said insulative material; removing a portion of said layer of said third material; removing a portion of said layer of said insulative material to define a pore in said layer of said insulative material; applying a layer of a first conductive material into said pore to define an electrode in said layer of said insulative material; applying a layer of a chalcogenide material onto said electrode and directly onto said layer of said insulative material; and applying a layer of a second conductive material onto said layer of said chalcogenide material.