Patent ID: 8947290
Filing Date: 2015-02-03
Classification: H03M

Abstract:
1. A successive approximation AD converter configured to convert an analog input voltage to a digital value, comprising: a capacitance DAC including a higher-order DAC having a plurality of capacitive elements having capacitance values weighted with a binary ratio, configured so that a first terminal of each of the capacitive elements is connected to a first common node and a second terminal thereof is connected to either a first or second voltage selectively depending on each bit of an input first digital signal, a lower-order DAC having a plurality of capacitive elements having capacitance values weighted with a binary ratio, configured so that a first terminal of each of the capacitive elements is connected to a second common node and a second terminal thereof is connected to either the first or second voltage selectively depending on each bit of an input second digital signal, and a coupling capacitor configured to connect the first common node and the second common node; a comparator into which a voltage generated by the analog input voltage and the capacitance DAC is input; a successive approximation circuit configured to determine the digital value sequentially starting from its MSB in response to the comparison result of the comparator, and output higher-order bits of the digital value as a third digital signal and lower-order bits thereof as the second digital signal; and a higher-order DAC control circuit configured to output either a correction control signal or the third digital signal selectively to the higher-order DAC as the first digital signal, wherein the lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the second common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the third digital signal.