Patent ID: 6438728
Filing Date: 2002-08-20
Classification: G06F

Abstract:
An error generating circuit for generating a 10-bit error character to test 8-bit/10-bit decoders, said error generating circuit comprising:a source of a two-state disparity control signal; a source of a two-state mode control signal; and a character generator for generating a 10-bit error character of a first type when the disparity control signal is in its first state and the mode control signal is in its first state, generating an 10-bit error character of a second type when the disparity control signal is in its second state and the mode control signal is in its first state, generating a 10-bit error character of a third type when the disparity control signal is in its first state and the mode control signal is in its second state, and generating a 10-bit error character of a fourth type when the disparity control signal is in its second state and the mode control signal is in its second state.