Patent ID: 7329575
Filing Date: 2008-02-12
Classification: H01L

Abstract:
1. A semiconductor device manufacturing method, comprising the steps of: (a) preparing a semiconductor substrate having a memory formation region where a memory device is to be formed and a logic formation region where a logic device is to be formed; (b) forming first and second impurity regions in an upper surface of said semiconductor substrate in said memory formation region and said logic formation region, respectively; (c) forming first and second gate structures spaced apart at a given distance from each other on the upper surface of said semiconductor substrate in said memory formation region, and forming a third impurity region in an upper surface of said first impurity region between said first and second gate structures, said third impurity region having a conductivity type different from that of said first impurity region; (d) forming third and fourth gate structures spaced apart at a given distance from each other on the upper surface of said semiconductor substrate in said logic formation region, and forming a fourth impurity region in an upper surface of said second impurity region between said third and fourth gate structures, said fourth impurity region having a different conductivity type from said second impurity region; (e) applying a nondirectional sputtering method from above the structure obtained by said steps (c) and (d) to deposit a metal material on said third impurity region between said first and second gate structures and on said fourth impurity region between said third and fourth gate structures; (f) causing said metal material and said semiconductor substrate to react with each other to form silicide films in the upper surfaces of said third and fourth impurity regions; and (g) forming a capacitor above said silicide film in the upper surface of said third impurity region, said capacitor being electrically connected to said silicide film in the upper surface of said third impurity region; a first gate aspect ratio that is defined by the distance between said first and second gate structures and a height of said first and second gate structures being larger than a second gate aspect ratio that is defined by the distance between said third and fourth gate structures and a height of said third and fourth gate structures.