Patent ID: 7795112
Filing Date: 2010-09-14
Classification: B82Y,H01L

Abstract:
1. A method of forming a transistor structure on a substrate comprising a supporting Si layer, a buried insulating layer, and a top Si layer, the method comprising: forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer is doped; forming open areas on the top Si layer demarcated by at least one of a demarcating oxide, a resist layer region, and the gate region; exposing the transistor structure comprising the open areas to ion implantation through the gate region wherein the demarcating layer region and the gate region act as an implantation mask, so as to simultaneously form impurity regions below the open areas in the buried insulating layer and an impurity region below the gate region in the top Si layer, wherein the impurity region below the gate region has a higher impurity level than regions below the open areas in the top Si layer to allow a selective removal of the impurity region below the gate region relative to the regions below the open areas in the top Si layer; and removing the impurity region in the top Si layer below the gate region by selective etching using the regions below the open areas in the top Si layer as a stopping layer, thereby creating a gap between the regions below the open areas in the top Si layer.