Patent ID: 6088252
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A semiconductor storage device comprising:a plurality of electrodes arranged in the central portion of a semiconductor chip so as to divide the semiconductor chip into two segments;an address buffer neighboring those electrodes which receive address signals;a memory array that is divided into at least two groups sandwiching said central portion of the chip, and including a plurality of memory cells arranged in the form of a matrix at points where a plurality of word lines intersect a plurality of bit lines;an address decoder provided by a side of the semiconductor chip opposite to the central portion across a corresponding group of said memory array so that said corresponding group of said memory array is sandwiched between said address decoder and electrodes and address buffer in the central portion in order to select said word lines or said bit lines; anda predecoder arranged on an intermediate portion extending from said central portion to a portion where said address decoder is provided.