Patent ID: 6466506
Filing Date: 2002-10-15
Classification: G11C

Abstract:
A semiconductor device formed on a main surface of a semiconductor substrate, comprising a memory cell array including a plurality of memory cells each having a storage node for storing data, which are arranged into a matrix,each of said memory cells including: a first field effect transistor of a second conduction type, formed in a first well of a first conduction type formed in said semiconductor substrate, and having its drain connected to said storage node; a first power supply node receiving a first power supply potential and connected to a source of said first field effect transistor; a second power supply node receiving a second power supply potential and connected to said first well; and a first pad connected to said first power supply node; a second pad connected to said second power supply node; a peripheral circuit for performing a control for transmitting/receiving data to/from said memory cell array; a third power supply node for supplying a third power supply potential to said peripheral circuit; and a third pad connected to said third power supply node, wherein said first and third pads are disposed adjacent to each other.