Patent ID: 7633160
Filing Date: 2009-12-15
Classification: H01L

Abstract:
1. A semiconductor package primarily comprising: a substrate including a substrate core, a first moldflow blocking lump and a second mold flow blocking lump, wherein the substrate core has a top surface, a bottom surface, and a slot penetrating through the top surface and the bottom surface, wherein a die-attaching area is defined on the top surface to make one end of the slot outside the die-attaching area to be a moldflow entrance, wherein the first moldflow blocking lump and the second mold flow blocking lump are protrusively disposed on the top surface of the substrate core and located at the intersections between one edge of the die-attaching area and the two opposing sides of the slot adjacent to the moldflow entrance; a chip having an active surface and a plurality of electrodes disposed on the active surface; a die-attaching layer bonding the active surface of the chip to the top surface of the substrate core of the substrate, wherein the electrodes of the chip are aligned in the slot and the active surface is aligned with the die-attaching area with the moldflow entrance exposed; a plurality of bonding wires passing through the slot and electrically connecting the electrodes of the chip to the substrate; and an encapsulant formed on the top surface of the substrate core and filled in the slot through the moldflow entrance to encapsulate the bonding wires.