Patent ID: 6759876
Filing Date: 2004-07-06
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting said first node at a second logic level different from said first logic level in accordance with an input signal; a second transistor for setting a second node at said first logic level when said first node is at said first logic level; a first resistor device that is connected between said first node and said second node and has a large resistance value when said first node is at said first logic level and has a small resistance value when said first node is at said second logic level; a first driving transistor for receiving, as an input, potential of said second node and controlling whether or not an output node is set at said first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of said first node and controlling whether or not said output node is set at said second logic level.