Patent ID: 7155600
Filing Date: 2006-12-26
Classification: G06F

Abstract:
1. A method for managing transitions between multi-threaded and single-threaded execution in a processor, comprising: receiving an instruction indicating a thread mode switch; in response to said receiving, stopping execution of a first thread running on said processor; further in response to said receiving, determining whether or not said thread mode switch is a switch from a single-threaded to a multi-threaded mode; responsive to determining that said thread mode switch is a switch from single-threaded mode to a multi-threaded mode, setting thread enable signals indicating an enable state of multiple threads, wherein at least said first thread and a second thread are specified for further execution; subsequent to said stopping, starting said first and second threads; and immediately subsequent to and responsive to said starting, sending a interrupt to said second thread that forces execution of said second thread to commence at a predetermined address.