Patent ID: 6927603
Filing Date: 2005-08-09
Classification: G01R

Abstract:
1. A semiconductor integrated circuit comprising: a system bus divided into stages and configured to transfer signals; stage elements configured to connect the stages in series and operate in a divided mode transferring signals from a stage on an input side to a stage on an output side in synchronization with a clock signal and in a through mode that always passes signals from the state on the input side to the stage on the output side; and a plurality of function modules connected to the different stages, wherein each of the stage elements comprises: a storage circuit configured to hold a signal transferred from the stage on the input side, comprising a flip-flop circuit configured to latch and hold the signal in synchronization with the clock signal; and a selector comprising: a first input terminal connected to the stage on the input side; a second input terminal connected to the stage on the input side through the flip-flop circuit; an output terminal connected to the stage on the output side; and a switching terminal configured to receive a through signal switching connections between the first and second input terminals and the output terminal from one to another, wherein: the selector connects the second input terminal to the output terminal in the divided mode and connects the first input terminal to the output terminal in the through mode.