Patent ID: 8659122
Filing Date: 2014-02-25
Classification: H01C,H01L

Abstract:
1. A semiconductor device comprising: a first interlayer insulating film placed over a substrate; a plurality of first dummy layers placed over the first interlayer insulating film, arranged to have a predetermined space between any adjacent two thereof in a first direction, and extending in a second direction perpendicular to the first direction in a planar view; an uppermost level interconnect layer placed over the first interlayer insulating film; a second interlayer insulating film covering therewith the first dummy layers and the uppermost level interconnect layer, and having a planarized surface; a plurality of metal resistor layers placed over the second interlayer insulating film and extending in the first direction in a planar view; and a third interlayer insulating film covering therewith the metal resistor layers; a passivation film placed over the third interlayer insulating film; a plurality of tap layers formed on the first interlayer insulating film; and a plurality of contact plugs formed in the second interlayer insulating film, more than one contact plugs connecting corresponding one of the plurality of tap layers and the plurality of metal resistor layers, the more than one contact plugs being connected to a same surface of the corresponding one of the plurality of tap layers, wherein the plurality of metal resistor layers are formed in a region between the passivation film and the uppermost level interconnect layer.