Patent ID: 8667049
Filing Date: 2014-03-04
Classification: F04D,F24F,G06F,G09G,H04L,H05K,Y02B

Abstract:
1. A massively parallel computer comprising: a plurality of processing nodes interconnected by multiple network interconnect configurations, each node of the plurality of processing nodes including multiple processing elements for performing computation or communication activity as required when performing parallel algorithm operations; a memory; and; a processor in communication with said memory, said processor configured to perform a method to: configure said multiple network interconnects as n-dimensional torus, global tree and global signal networks for enabling point-to-point, global tree communications and asynchronous global barrier and notification operations among said plurality of processing nodes, wherein combinations of said multiple network interconnect configurations interconnecting said plurality of processing nodes are collaboratively utilized according to bandwidth and latency requirements of an algorithm for optimizing algorithm processing performance, and configure each said plurality of processing nodes to run a parallel processing message-passing algorithm using said multiple network interconnects simultaneously such that the multiple processing elements within a node of said plurality of processing nodes simultaneously access and employ each said n-dimensional torus, global tree and global asynchronous signal networks, wherein said asynchronous global barrier and notification operations provide global logical AND and logical OR functionality for enabling respective said global barrier operations and global notification operations.