Patent ID: 6396353
Filing Date: 2002-05-28
Classification: H03L,Y10S

Abstract:
A PLL synthesizer circuit comprising:a programmable divider circuit driven by a controller for selecting a desired output frequency of the PLL synthesizer circuit; an operating mode selector circuit which optionally drives a receive operating mode of the PLL synthesizer circuit having a third settling time constant and at least one further operating mode having a fourth settling time constant reduced with respect to the third settling time constant; and a trigger for detecting the driving of the programmable divider circuit by the controller with the aid of a changed drive value which outputs a detection signal to the operating mode selector circuit causing the operating mode selector to drive the at least one further operating mode, wherein a phase detector and an interlocking detector compare an output signal of the phase detector with a threshold value and output an interlocking signal to the operating mode selector circuit causing the operating mode selector circuit to drive the receive operating mode when the output signal of the phase detector undershoots the threshold value.