Patent ID: 6097685
Filing Date: 2000-08-01
Classification: G11B,H03M

Abstract:
An information reproducing apparatus for causing a PLL (Phase Locked Loop) to be locked with a signal reproduced from a record medium, causing the PLL to generate a clock signal, and operating a reproducing system corresponding to the clock signal, comprising:Viterbi decoding means for decoding the reproduced signal corresponding to the Viterbi decoding method;first timing generating means for generating a first timing signal for detecting a phase error with status data that represents a status transition selected by said Viterbi decoding means;second timing generating means for generating a second timing signal for detecting a phase error at a timing of the inversion of MSB of a reproduced signal with a predetermined number of bits, the reproduced signal being received from an A/D converter disposed on the preceding stage of said Viterbi decoding means;third timing generating means for generating a third timing signal for detecting a phase error corresponding to a predetermined signal pattern recorded or formed on the predetermined area of record medium;switching means for selectively outputting one of the first, second, and third timing signals; andphase error signal generating means for generating a phase error signal for controlling the PLL with the reproduced signal corresponding to the timing signal selected by said switching means.