Patent ID: 8042028
Filing Date: 2011-10-18
Classification: H04B,H04L

Abstract:
1. A HS-PDSCH decoder for processing received data to which both a first rate matching step in which bits are punctured in a base station in accordance with a number of bits storable in an IR buffer of said base station, and a second rate matching step in which bits are repeated or punctured in accordance with a number of bits which can be transmitted through HS-PDSCH were carried out, comprising: a second rate de-matching unit receiving in parallel N (N indicates an integer equal to or greater than 2) data defining said received data, carrying out a second rate de-matching step to said N data in parallel for removing bits having been repeated in said second rate matching step or de-removing bits having been punctured in said second rate matching step, and outputting said N data to which said second rate de-matching step was carried out; N adders carrying out a combining step for adding predetermined data to corresponding single data in parallel among said N data having been output from said second rate de-matching unit, and outputting data to which said combining step was carried out; a first rate de-matching unit carrying out a first rate de-matching step to data having been output from said N adders for de-removing bits having been punctured in said first rate matching step, and outputting data to which said first rate de-matching step was carried out; and a decoder repeatedly carrying out a turbo-decoding step to data having been output from said first rate de-matching unit.