Patent ID: 7822198
Filing Date: 2010-10-26
Classification: H04L

Abstract:
1. An encryption device for selectively encrypting, or decrypting first and second data streams comprising: (a) a first buffer for receiving said first data stream which has a parallel Low Voltage Differential Signaling (LVDS) format and an input enable signal; (b) a second buffer for receiving said second data strewn which has a parallel Transistor-Transistor Logic (TTL) format and said input enable signal; (c) said first buffer passing said first data stream through said first buffer to a first data bus when said input enable signal is at a first logic state and said second buffer passing said second data stream through said second buffer to said first data bus when said input enable signal is at a second logic state; (d) a frequency multiplier for generating a first LVDS clock signal and a second LVDS clock signal which has a frequency n times the frequency of said first LVDS clock signal; (e) a serializer transmitter for receiving said first and second LVDS clock signals from said frequency multiplier, said first data stream from said first data bus and said second data stream from said first data bus, said serializer transmitter, responsive to said first and second LVDS clock signals, converting said first and second data streams to an LVDS serial format; (f) an encryptor for receiving said first and second data streams from said serializer transmitter, and an encryption control signal, said encryptor, responsive to a pair of logic states for said encryption control signal, selectively encrypting or decrypting said first and second data streams; (g) a receiver deserializer for receiving said first LVDS clock signal from said serializer transmitter, said receiver deserializer receiving said second LVDS clock signal, and said first and second data streams from said encryptor after said encryptor selectively encrypts or decrypts said first and second data streams, said receiver deserializer responsive to said first and second LVDS clock signals, reconverting said first and second data streams to said LVDS parallel format and then providing said first and second data streams to a second data bus; (h) a third buffer for receiving an output enable signal and said first data stream from second data bus; (i) a fourth buffer for receiving said output enable signal and second data stream from said second data bus; and (j) said third buffer passing said first data stream through said third buffer to a first data recorder when said output enable signal is at a first logic state and said fourth buffer passing said second data stream through said fourth buffer to a second data recorder when said output enable signal is at a second logic state.