Patent ID: 6339558
Filing Date: 2002-01-15
Classification: G06F

Abstract:
A FIFO memory device comprising:a first input section for inputting first data; a second input section for inputting second data; a memory for storing the first data inputted from the first input section and the second data inputted from the second input section; a first output section for outputting the first data read from the memory; a second output section for outputting the second data read from the memory; first FIFO control section for writing the first data inputted from the first input section into the memory, reading the first data written in the memory in order of the data inputting, and outputting the first data to the first output section; a second FIFO control section for writing the second data inputted from the second input section into the memory, reading the second data written in the memory in order of the data inputting, and outputting the second data to the second output section; and wherein the memory comprises a common memory space, and said first data and said second data share the common memory space when written to the memory by the first FIFO control section and the second FIFO control section, respectively, with first data capacity and second data capacity in the common memory space varying flexibly.