Patent ID: 6303422
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A manufacturing method of semiconductor memory, comprising:making active areas of driving transistors and transferring transistors, isolated by insulation film on a semiconductor substrate by etching;forming word lines and gate electrodes of said driving transistors and gate electrodes of said transferring transistors with a conductive film on a gate oxide film in said transistor active areas;forming a first dielectric interlayer;opening a first contact hole exposing a common source/drain area for said driving transistors and said transferring transistors and exposing the gate electrode of the other driving transistor being a pair of said driving transistors on said first dielectric interlayer;forming a high resistance load, which is electrically connected to said common source/drain area and said gate electrode via said first contact hole, by formed polysilicon into a required pattern;forming a second dielectric interlayer;opening a second contact hole exposing said high resistance load at said second dielectric interlayer and opening third and fourth contact holes exposing the source area of said driving transistors and the drain area of said transferring transistors at said second dielectric interlayer and said first dielectric interlayer;forming a first power supply line connecting electrically to said high resistance load, a second power supply line connecting electrically to the source area of said driving transistor, and an interconnect line connecting electrically to the drain area of said transferring transistor, by forming said first metal film into a required pattern;forming a third dielectric interlayer;opening a fifth contact hole exposing said interconnect line at said third dielectric interlayer; andforming bit lines connecting electrically to said interconnect line by forming said second metal film into a required pattern.