Patent ID: 6645823
Filing Date: 2003-11-11
Classification: G03F

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:(a) forming an optical resist layer on a target layer located over a surface of a semiconductor wafer; (b) irradiating light on said resist layer through a reticle including a first area including a desired circuit pattern and a second area including alignment marks arranged at specific positions; wherein said first area and said second area are irradiated by said light; each of said alignment marks include mark elements arranged to form a first geometric shape; each of said mark elements sub-elements arranged in a specific direction at specific pitches to form a second geometric shape; (c) developing said resist layer exposed to said light to form a resist circuit pattern and resist alignment-mark patterns in said resist layer from said circuit pattern and said alignment marks on said reticle, respectively; wherein each of said resist alignment-mark patterns including resist sub-patterns corresponding to said sub-elements arranged in the specific direction; (d) selectively removing a resist sub-pattern from each end of each of said resist alignment-mark patterns, forming amended resist alignment-mark patterns in said resist layer; (e) measuring alignment accuracy of said resist layer with respect to an underlying layer of said target layer using said amended resist alignment-mark patterns; and, (f) selectively etching said target layer using said resist layer with said amended resist alignment-mark patterns.