Patent ID: 6845026
Filing Date: 2005-01-18
Classification: G11C

Abstract:
1. A content addressable memory (CAM) cell comprising: a memory cell for storing a data value, the memory cell including at least one vertical thyristor with a surrounding gate, the vertical thyristor coupled to an access transistor; and at least one compare circuit coupled among the memory cell and at least one match line to receive first and second signal sets and affect a logical state of the match line in response to a predetermined logical relationship between the first and second signal sets, the compare circuit including a first transistor set and a second transistor set, wherein the first signal set couples to control a conduction state of the first transistor set and the second signal set couples to control a conduction state of the second transistor set, wherein at least one transistor of the first transistor set has an offset difference between a threshold voltage and a voltage of the first signal set relative to transistors of the second transistor set.