Patent ID: 8937291
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A memory device, comprising: a memory layer having opposing first and second surface portions and being connected to a common electrode; and first and second transistor arrays comprising transistors connected to the first and second surface portions of the memory layer, respectively, wherein each transistor in the first transistor array is operable to address a respective memory storage region in the first surface portion of the memory layer, and each transistor in the second transistor array is operable to address a respective memory storage region in the second surface portion of the memory layer; wherein the first transistor array comprises common column structures disposed transversely through a plurality of common base structures; wherein transistors arranged in each column of the first transistor array share one of the common column structures, and transistors arranged in each row of the first transistor array share one of the common base structures; and wherein the transistors of the first transistor array each comprise a connector structure that is spaced apart from a respective common column structure by a respective common base structure and that is connected to the memory layer.