Patent ID: 8473770
Filing Date: 2013-06-25
Classification: G01R

Abstract:
1. A semiconductor device comprising a serial reception circuit for receiving a serial signal in synchronization with a clock signal, wherein the serial reception circuit: samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal; determines, based on sampled signals, an optimum phase of the clock signal which is a sampling phase having little effect of phase variation of the serial signal on a sampling result; and performs a reception operation to determine a reception data by sampling a signal using the optimum phase of the clock signal, wherein the serial reception circuit determines optimum phase of the clock signal by a first and a second determination mode, wherein in the first determination mode, the serial reception circuit determines an optimum phase of the clock signal based on the multiphase sampling clock signals, and wherein in the second determination mode, the serial reception circuit determines an optimum phase of the clock signal based on the optimum phase of the clock signal determined in the first mode and at least a first and a second phase of the clock signal adjacent to the optimum phase of the clock signal determined in the first determination mode, wherein a number of sampling phases used in the second determination mode is less than a number of sampling phases used in the first determination mode.