Patent ID: 9112024
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A lateral semiconductor device comprising: a semiconductor substrate; a buried oxide layer formed on the semiconductor substrate; and an active layer formed on the buried oxide layer, wherein the active layer includes a first conductivity type well region, a second conductivity type well region, a first conductivity type drift region, and a second conductivity type surface layer, the first conductivity type well region and the second conductivity type well region are separated via the first conductivity type drift region, such that the first conductivity type drift region is interposed between the first conductivity type well region and the second conductivity type well region, the first conductivity type well region and the second conductivity type well region having contact with the first conductivity type drift region, the second conductivity type surface layer is formed in a part of a surface of the active layer, between the first conductivity type well region and the second conductivity type well region, the second conductivity type surface layer has, on the second conductivity type well region side thereof, a first portion having contact with the second conductivity type well region and a second portion distanced from the second conductivity type well region by a part, of the first conductivity type drift region, that has contact with the second conductivity type well region being located between the second portion and the second conductivity type well region, the first portion and the second portion being alternately disposed when viewed in a plan view, the first conductivity type well region surrounds a first conductivity type drain region, and the second conductivity type well region surrounds a first conductivity type source region, the lateral semiconductor device further comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer has, in a part of a surface of the active layer, contact with the second conductivity type well region, the first conductivity type drift region, and the second conductivity type surface layer, and the gate electrode faces the second conductivity type well region via the gate dielectric layer.