Patent ID: 7932167
Filing Date: 2011-04-26
Classification: G11C,H01L

Abstract:
1. A method of forming a memory cell in an integrated circuit, the method comprising the steps of: forming a lower electrode feature; forming a silicon film stack on the lower electrode feature; forming a sacrificial layer on the silicon film stack; etching the sacrificial layer to form a sacrificial feature on the silicon film stack; forming an island on the lower electrode feature by etching exposed portions of the film stack down to the lower electrode using the sacrificial feature as a mask, the island having one or more sidewalls and comprising: forming a gate feature along each of the one or more sidewalls of the island, the gate feature overlying at least a portion of the middle doped feature of the island and operative to control an electrical resistance therein; trimming the sacrificial feature above the island to reduce a lateral dimension of the sacrificial feature relative to a lateral dimension of the island; and forming a phase change feature above the island at least in part by replacing the trimmed sacrificial feature with a phase change material, the phase change material being operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.