Patent ID: 6631087
Filing Date: 2003-10-07
Classification: H01L

Abstract:
An EEPROM memory cell, said memory cell comprising:(a) a transistor device formed on a first conductivity type semiconductor substrate, said transistor comprising: an electrically floating gate structure, a source region within a graded diffusion region, and a drain region; (b) a capacitive device formed on a second conductivity type semiconductor substrate, said capacitive device comprising: first and second injector regions of third conductivity type, a channel region of second conductivity type separating said first and second injector regions, and a first electrically floating structure disposed above said channel region, wherein a first edge portion of said floating structure overlaps a portion of said first injector region and a second edge portion of said first floating structure overlaps a portion of said second injector region, and a control gate region of fourth conductivity type located within said second conductivity type semiconductor substrate; (c) said gate structure and said first floating structure being electrically connected together; wherein said transistor device and capacitive device are capable of receiving bias voltages for electrically programming, electrically erasing and electrically reading said memory cell.