Patent ID: 6724666
Filing Date: 2004-04-20
Classification: G06F,G11C

Abstract:
In a memory system having a memory controller coupled to a plurality of memory devices, the memory devices having a common flag signal line and a common read clock signal line, both also coupled to the memory controller, a method for equalizing the system read latency for the memory devices comprising:sending, by the memory controller, a read command to a target memory device selected from one of the plurality of memory devices; sending, by the memory controller, a flag signal on the common flag signal line to the target memory device at a number of read clock cycles after the read command had been sent; outputting data associated with the read command by the target memory device, beginning at a predetermined number of read clock cycles after the target memory device having received the flag signal; wherein the number is the same regardless of which memory device had been selected as the target memory device.