Patent ID: 8743618
Filing Date: 2014-06-03
Classification: G11C

Abstract:
1. A method for compensating for variability in bit line resistance, comprising: determining a gate read voltage for a first set of transistors corresponding with a first bit line read voltage being applied to the first set of transistors, the first set of transistors is associated with a first zone of a memory plane; determining a second bit line read voltage for a second set of transistors corresponding with the gate read voltage being applied to the second set of transistors, the second set of transistors is associated with a second zone of the memory plane; performing a sensing operation on one or more memory cells within the memory plane, the performing a sensing operation includes determining a bit line read voltage based on the second bit line read voltage and applying the bit line read voltage to one or more bit lines associated with the one or more memory cells during sensing of the one or more memory cells; and outputting data stored in the one or more memory cells based on the performing a sensing operation.