Patent ID: 8510616
Filing Date: 2013-08-13
Classification: G01R,G11C

Abstract:
1. A circuit comprising: a first sub-chain containing a first sequence of functional memory elements; a second sub-chain containing a second sequence of functional memory elements; a scan splitter block comprises a first functional memory element, said scan splitter block operable to receive a test vector containing a sequence of bits at a first frequency and to de-multiplex said sequence of bits such that a first subset of bits is sent to said first sub-chain and a second subset of bits is sent to said second sub-chain at a second frequency and a third frequency respectively in a scan mode, said first subset of bits and said second subset of bits being contained in said sequence of bits, wherein said scan splitter block is operable to capture results from said first sub-chain and said second sub-chain and output said results at said first frequency; and a combinational logic to receive at least one input from said first sub-chain and said second sub-chain and to generate an output bit in a functional test mode, wherein said first frequency is greater than each of said second frequency and said third frequency, wherein said first sequence of functional memory elements, said second sequence of functional memory elements, and said first functional memory element are contained in a functional portion of said circuit.