Patent ID: 7321517
Filing Date: 2008-01-22
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells provided at positions where a plurality of word lines and a pair of bit lines intersect with each other; an equalizing circuit connecting said pair of bit lines to each other and connecting said pair of bit lines to a precharge voltage line, in response to activation of an equalizing control signal; an equalizing control circuit deactivating said equalizing control signal in response to activation of a first timing signal; a word line driving circuit activating one of said word lines in response to activation of a second timing signal; and a timing control circuit having a first signal generating circuit which generates said first timing signal and a second signal generating circuit which activates said second timing signal after said equalizing control signal is deactivated in response to activation of said first timing signal, wherein said second signal generating circuit includes a delay control circuit delaying an activation timing of said second timing signal in a test mode from an activation timing of said second timing signal in a normal mode.