Patent ID: 6269466
Filing Date: 2001-07-31
Classification: H01L,Y10S

Abstract:
A method of constructing an integrated circuit utilizing a MACRO, comprising:constucting said integrated circuit from multiple physical layers of interconnect;providing a standard cell array constructed of transistors, said standard cell array having a power bus;embedding a MACRO in said standard cell array after said providing a standard cell array;running a plurality of computer simulations of said MACRO;changing dimensions of at least one of said transistors in different simulations;identifying transistor dimensions which provide superior timing performance;coupling said MACRO to said power bus of said standard cell array;fabricating said MACRO according to said identified transistor dimensions which provide superior timing performance;utilizing a second layer of metallization comprising no local interconnect as part of said integrated circuit so as to provide routing flexibility across said MACRO and so as to allow compaction of interconnect into spaces located over said MACRO.