Patent ID: 6192447
Filing Date: 2001-02-20
Classification: G11C

Abstract:
A resettable memory apparatus including a random access memory having a plurality of memory locations, each of the plurality of memory locations storing a plurality of bits of data, comprising:a register having a plurality of bits, there being one bit for each of the plurality of memory locations;means for resetting all of the bits in the register to invalid;an address recoder for recoding an address of any of the plurality of memory locations to a reset address when accessing the address in the random access memory while a bit of the plurality of bits in the register that corresponds to the address is invalid;a multiplexer having a first input connected to the output of the address recoder and a second input connected to a base address register, the multiplexer selecting by a park signal an input address for the random access memory and a base location of the random access memory storing a base address to read when the second input of the multiplexer is selected; andmeans for generating a reset value when reading a particular one of the memory locations while the corresponding bit in the register is invalid to provide a resettable random access memory.