Patent ID: 7294534
Filing Date: 2007-11-13
Classification: H01L

Abstract:
1. An interconnect layout method for arranging: a first gate pattern and a second gate pattern provided substantially in parallel to each other at a first predetermined distance between said first gate pattern and said second gate pattern; a first dummy pattern that is provided adjacent to said first gate pattern on an opposite side to a side on which said second gate pattern is provided, at a second predetermined distance from said first gate pattern in a direction substantially in parallel to a longitudinal direction of said first gate pattern, and that includes no circuitry functions; and a second dummy pattern that is provided adjacent to said second gate pattern on an opposite side to a side on which said first gate pattern is provided, at a third predetermined distance from said second gate pattern in a direction substantially in parallel to a longitudinal direction of said second gate pattern, and that includes no circuitry functions, wherein said first gate pattern, said second gate pattern, said first dummy pattern, and said second dummy pattern are arranged so that, if a wavelength of a light used to expose said first gate pattern and said second gate pattern is λ, natural numbers are m said second predetermined distance satisfies relationships of: and said third predetermined distance satisfies relationships of: