Patent ID: 6970994
Filing Date: 2005-11-29
Classification: G06F

Abstract:
1. A method comprising: receiving an instruction that specifies memory locations of a first full-width packed data operand having a plurality of data elements and a second full-width packed data operand having a corresponding plurality of data elements; accessing the first full-width packed data operand and the second full-width packed data operand from the memory locations; dividing the first full-width packed data operand into a first subset of data elements and a second subset of data elements; dividing the second full-width packed data operand into a third subset of data elements and a fourth subset of data elements; performing an operation specified by the instruction on the first and third subsets of data elements to generate a first resulting one or more data elements; delaying the second and fourth subsets of data elements; after said delaying, performing an operation specified by the instruction on the second and the fourth subsets of data elements to generate a second resulting one or more data elements, wherein performing the operation specified by the instruction on the second and the fourth subsets comprises setting at least one data element to a predetermined value; and storing the first and the second resulting data elements in a common packed data operand.