Patent ID: 6717415
Filing Date: 2004-04-06
Classification: G01R

Abstract:
A method for testing an integrated circuit (IC) for open defects in a printed wire connected to an IC pin of the IC, said IC having a boundary scan cell associated with each pin of the IC, analog test access buses connected to the boundary scan cells and test bus access pins for accessing said buses, the method comprising:measuring the capacitance between the IC pin and ground; comparing the value of the measured capacitance to an expected IC pin capacitance value between the pin and ground with the pin unconnected, and determining that an open defect exists proximate the pin when the measured capacitance is less than a predetermined value based on said expected IC pin capacitance; said measuring the capacitance of the IC pin including: measuring the capacitance of the access buses via the test bus access pins on said IC while no pins are accessed; enabling switches that access a selected pin by loading enabling bits into the boundary scan cell of the selected pin; measuring the capacitance of said selected pin via the access pins; determining the capacitance of the selected pin by subtracting the effects of the capacitance of the bus to obtain said measured capacitance; and said comparing the value including comparing the measured value to the capacitance value expected for said selected pin if it were unconnected to deduce whether a wire is connected to said selected pin or how much wire is connected to the pin.