Patent ID: 6228766
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A process for fabricating a semiconductor device, comprising the steps of:a) preparing a silicon substrate;b) selectively forming a field insulating layer on a major surface of said silicon substrate so as to define a narrow active area assigned to a circuit component and a wide inactive area not assigned to any circuit component positioned either above or below said field insulating layer, said wide inactive area defined by scribe areas on said silicon substrate andperforming additional process steps without ion-implantation into said wide inactive area, said additional process steps including:c) forming a first ion-implantation mask on said major surface so as to cover said wide inactive area therewith and uncover said narrow active area therewith;d) ion implanting a first dopant impurity into said narrow active area so as to form first doped regions forming parts of said circuit component;e) removing said first ion-implantation mask;f) depositing a metal layer on at least said first doped regions;g) causing said metal layer to react with the silicon of said first doped regions under application of heat for forming conductive metal silicide layers.