Patent ID: 7180772
Filing Date: 2007-02-20
Classification: G11C

Abstract:
1. A high density NVRAM comprising: a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other, each conductive array line having a plurality of bottom memory plug sites; a second layer of conductive array lines, the conductive array lines being arranged so that they cross over the conductive array lines of the first layer without coming into direct contact with each other or any of the conductive array lines of the first layer, each conductive array line having a plurality of top memory plug sites, each top memory plug site being located directly above a corresponding bottom memory plug site, the bottom memory plug site and its associated top memory plug constituting a memory plug site pair; and peripheral circuitry that receives a supply voltage of approximately 1.8 volts or less, generates voltages to conductive array lines of a magnitude not more than approximately 3 volts, senses current that is indicative of a nonvolatile memory state.