Patent ID: 7161832
Filing Date: 2007-01-09
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a plurality of memory cells of storing data, wherein the memory cells are arranged in a matrix and each of the memory cells comprises a first memory transistor and a second memory transistor each having a floating gate; a plurality of first wire lines arranged in a row direction, wherein a first voltage is applied to the first wire line during a data write operation; a plurality of second wire lines paired with the respective first wire lines and extending in the row direction, wherein a second voltage is applied to the second wire line, the second voltage being lower than the first voltage during the data write operation; and a switch section of switching connections of the first memory transistor, the second memory transistor, the first wire line, and the second wire line, wherein, when first type data is to be written into the memory cell, the switch section connects the first wire line to a gate of the first memory transistor and a source of the second memory transistor, and the second wire line to a source of the first memory transistor and a gate of the second memory transistor; and when a second type data is to be written into the memory cell, the switch section connects the first wire line to the source of the first memory transistor and the gate of the second memory transistor, and the second wire line to the gate of the first memory transistor and the source of the second memory transistor.