Patent ID: 6562670
Filing Date: 2003-05-13
Classification: H01L,Y10S

Abstract:
A method of manufacturing a thin film transistor, comprising:providing a substrate having a gate electrode formed thereon; forming a gate dielectric layer, an amorphous silicon layer, a silicon-bond-protection layer and a photoresist layer over the substrate in sequence, wherein the silicon-bond-protection dielectric layer comprises elements for compensating dangling silicon bonds; patterning the photoresist layer by exposing the photoresist layer from the bottom of the substrate using the gate electrode as a mask; processing a thermal reflow process to laterally extend the patterned photoresist layer, wherein the bottom of the softened photoresist layer is larger than the gate electrode; removing a portion of the silicon-bond-protection layer to expose a portion of the amorphous silicon layer by using the patterned photoresist layer as a mask; forming a doped dielectric layer over the substrate; performing a thermal annealing process to convert the amorphous silicon layer into a polysilicon layer, wherein dopants in the doped dielectric layer diffuse into the polysilicon layer to form a doped region and elements in the silicon-bond-protection layer diffuse into the polysilicon layer to form a channel region; and removing the silicon-bond-protection layer and the doped dielectric layer.