Patent ID: 7163826
Filing Date: 2007-01-16
Classification: B81C,H01L

Abstract:
1. A method of fabricating a vertically integrated circuit, the method comprising the steps of: providing a bulk substrate, said bulk substrate including a buried oxide layer; selectively creating strong bond regions and weak bond regions on said substrate; providing a first bonded semiconductor layer vertically supported on said sabstrate; creating semiconductor device portions on said first bonded semiconductor layer, said semiconductor device portions corresponding to said weak bond regions, at least a portion of said semiconductor device portions further including in electrical contact a first conductor region exposed on the side of the layer opposite the buried oxide layer; removing said first semiconductor layer and at least a portion of the thickness of said buried oxide layer from said bulk substrate; removing sufficient oxide of said at least a portion of the thickness of said oxide to form second conductor regions in electrical contact with the side of the semiconductor device portions adjacent the oxide and exposed at the side of the oxide; and bonding said first semiconductor layer to a second semiconductor layer.