Patent ID: 7615425
Filing Date: 2009-11-10
Classification: H01L

Abstract:
1. A method of forming a p type junction field effect transistor and an n type junction field effect transistor in a semiconductor substrate, comprising: forming a first n type buried layer in the substrate; forming a first p type buried layer in the substrate; forming a first n type epitaxial layer over the substrate; forming a second p type buried layer over the first p type buried layer in the first n type epitaxial layer; forming one or more deep n+ type regions over at least some of the first n type buried layer in the first n type epitaxial layer; forming a second n type epitaxial layer over the first n type epitaxial layer; forming a p type surface shield near an upper surface of the second n type epitaxial layer, where the p type surface shield resides over at least some of the second p type buried layer; forming an n type channel in the second n type epitaxial layer, where the n type channel resides over at least some of the second p type buried layer; forming a p type back gate extension near a lower surface of the second n type epitaxial layer, where the p type back gate extension resides over at least some of the second p type buried layer and over less than all of the first n type buried layer; forming an n type surface shield near an upper surface of the second n type epitaxial layer, where the n type surface shield resides over at least some of the first n type buried layer; forming a p type channel in the second n type epitaxial layer, where the p type channel resides over at least some of the first n type buried layer; forming one or more isolation areas that isolate the p type junction field effect transistor from the n type junction field effect transistor; forming one or more n type deep back gate contact regions in the second n type epitaxial layer down to the one or more deep n+ type regions in the p type junction field effect transistor; forming one or more p type deep back gate contact regions in the second n type epitaxial layer down to the second p type buried layer in the n type junction field effect transistor; forming a deep p type region in the second n type epitaxial layer down to the second p type buried layer in the p type junction field effect transistor: forming a layer of silicide block material over the second n type epitaxial layer; patterning the silicide block material to expose areas of the second n type epitaxial layer where gate, source and drain regions are to be formed; forming an n type gate region in the p type channel of the p type junction field effect transistor, and n type source and drain regions in the n type channel of the n type junction field effect transistor; forming p type source and drain regions in the p type channel of the p type junction field effect transistor, and a p type gate region in the n type channel of the n type junction field effect transistor; siliciding the gate, source and drain regions in the p type channel of the p type junction field effect transistor and the n type channel of the n type junction field effect transistor; forming a layer of dielectric material over the silicides and second n type epitaxial layer; forming conductive contacts down through the layer of dielectric material to the silicided gate, source and drain regions in the p type channel of the p type junction field effect transistor and the n type channel of the n type junction field effect transistor; and forming a field plate over at least one of the conductive contacts extending down to the gate regions of the p type junction field effect transistor and the n type junction field effect transistor, where the field plates also extend over at least some of at least one of the source and drain regions of the p type junction field effect transistor and the source and drain regions of the n type junction field effect transistor.