Patent ID: 9190390
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A method for fabricating stacked microelectronic packages, comprising: arranging a plurality of microelectronic device panels in a panel stack, each microelectronic device panel containing plurality of microelectronic devices and a plurality of package edge conductors extending therefrom; creating trenches in the panel stack exposing the plurality of package edge conductors; forming a plurality of sidewall conductors interconnecting different ones of the package edge conductors exposed through the trenches, forming comprising: separating the panel stack into a plurality of stacked microelectronic packages each comprising at least first and second sidewall conductors, the first sidewall conductor electrically isolated from the second sidewall conductor by one of the linearly-spaced vertical openings during removal of selected portions of the electrically-conductive material.