Patent ID: 6479359
Filing Date: 2002-11-12
Classification: G06F

Abstract:
A method for fabricating a low-resistance gate transistor, comprising steps of:forming a gate oxide film on a semiconductor substrate, and forming a gate thereon; forming a lightly doped impurity region in the surface of the semiconductor substrate using the gate as a mask; forming a first layer of a material the same as the gate on an entire surface of the gate oxide film and the gate to a substantially uniform thickness; forming a second layer of a material having a resistivity lower than the gate on an entire surface of the first layer, and patterning the first layer and the second layer to form a first gate sidewall and second gate sidewalls, wherein the first gate sidewall of a material the same as the gate is formed on a top surface and sides of the gate while the second gate sidewalls of a material having a resistivity lower than the gate are formed only at the sides of the gate; and forming a gate protection insulating layer on an entire surface, and injecting impurity ions heavily to form heavily doped impurity regions in the surface of the semiconductor substrate.