Patent ID: 9209185
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method, comprising: providing a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region; forming first fin structures in the NFET region and the PFET region; forming a patterned oxidation-hard-mask (OHM) over the NFET region and PFET region to expose the first fin structure in a first gate region of the NFET region; forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region; forming a second fin structure in the PFET region after covering the NFET with a hard mask layer; forming dummy gates in the first gate region and a second gate region in the second fin structure; forming a first source/drain (S/D) features in a first S/D region in the first fin structure in the NFET region; forming a second S/D feature in a second S/D region in the second fin structure in the PFET region; replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region, including wrapping over an upper portion of the first fin structure in the first gate region; and replacing the dummy gates by a second HK/MG in the PFET region, including wrapping over an upper portion of the second fin structure in the second gate region.