Patent ID: 6972266
Filing Date: 2005-12-06
Classification: H01L

Abstract:
1. A method for processing a semiconductor device in a process for making electronic components comprising the steps of: providing an integrated circuit structure which is in the process of being fabricated into a finished electronic component having an array area and a support area, said array area including an array of trenches containing trench capacitors and vertical transistors separated by isolation trenches having a fill material; depositing a nitride liner entirely over both said array area and said support area, said nitride liner covering said isolation trenches; depositing an array top oxide layer directly and entirely over said nitride liner within both said array and support areas; removing said array top oxide layer and said nitride liner only in said support area using a first mask, leaving remaining portions of said array top oxide and said nitride liner only in said array area such that said nitride liner separates said array top oxide layer from said isolation trenches having said fill; removing said first mask; and subsequently, removing at least a portion of said array top oxide layer and at least a portion of said nitride liner in said array area using a second mask whereby said array top oxide layer is confined by said nitride liner such that said nitride liner separates said array top oxide layer from said isolation trenches during said processing; and removing said second mask.