Patent ID: 8923065
Filing Date: 2014-12-30
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: an I/O channel for transporting data between first and second endpoints in the non-volatile memory device; a driver having a resistance (“Ron”) for driving data from the first endpoint through said I/O channel; and a receiver for receiving the data at the second endpoint through said I/O channel; said receiver further comprising: a termination circuit at the second endpoint having a pseudo open drain (POD) configuration with the second endpoint being shunt only by a first termination resistor (“Rtt”) to the supply voltage (“VDD”) such that a current flow in the I/O channel only when the data is driven by a transistor of said driver to ground; and a buffer circuit for buffering the data at the second endpoint, said buffer circuit being an operational amplifier for amplifying the data at the second endpoint relative to a reference voltage given by VDD/2 but adjusted by a predetermined ΔV, said ΔV being a function of a ratio, (Rtt/Ron) , between the resistance of the first termination resistor and the transistor of said driver.