Patent ID: 7375373
Filing Date: 2008-05-20
Classification: H01L

Abstract:
1. A thin film transistor array panel comprising: an insulating substrate; a first signal line formed on the insulating substrate; a first insulating layer formed on the first signal line; a second signal line formed on the first insulating layer and intersecting the first signal line; a thin film transistor connected to the first and the second signal lines; a second insulating layer formed on the thin film transistor and having a first contact hole exposing an electrode of the thin film transistor; and a pixel electrode formed on the second insulating layer and connected to the electrode of the thin film transistor through the first contact hole, wherein at least one of the first and the second signal lines comprises an Ag alloy containing Ag and an additive, the additive including at least one selected from the group consisting of Zn, In, and Sn, wherein an upper portion of the Ag alloy of the at least one of the first and second signal lines comprises the additive, O and Ag, and a lower portion of the Ag alloy of the first and second signal lines comprises Ag, and a first concentration of the additive at the upper portion of the Ag alloy of the at least one of the first and second signal lines is greater than a second concentration of the additive at the lower portion of the Ag alloy of the first and second signal lines.