Patent ID: 7779284
Filing Date: 2010-08-17
Classification: G06F

Abstract:
1. A method of operating a processor subsystem, comprising: masking interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem; setting a boot vector for the processor of the processor subsystem, the boot vector providing an address associated with a saved processor state; saving a current state of the processor to provide the saved processor state; determining whether one or more first masked interrupts occurred during the saving of the current state of the processor; stopping the processor that is to be powered-down when the one or more first masked interrupts did not occur during the saving of the current state of the processor; determining whether one or more second masked interrupts occurred following the saving of the current state of the processor; and powering-down the processor when the one or more second masked interrupts did not occur following the saving of the current state of the processor.