Patent ID: 7391118
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a silicon dummy chip having a chip-mounting surface and including at least an embedded component, a plurality of redistribution traces and a plurality of flip-chip pads on the chip-mounting surface, the embedded component being electrically connected to one of the flip-chip pads via one of the redistribution traces; a flip chip mounted on the chip-mounting surface of the silicon dummy chip, the flip chip having an active surface and a back surface and including a plurality of bonding pads on the active surface; and a plurality of bumps connecting the bonding pads of the flip chip with the flip-chip pads of the silicon dummy chip; wherein the coefficient of thermal expansion (CTE) of the silicon dummy chip substantially matches the CTE of the flip chip, wherein the chip-mounting surface of the silicon dummy chip is larger than the active surface of the flip chip, wherein the silicon dummy chip includes a plurality of ball pads at the peripheral region of the chip-mounting surface, the ball pads are electrically connected to the corresponding flip-chip pads via the redistribution traces, wherein the device further comprises a plurality of solder balls placed on the ball pads, wherein the solder balls are higher than the back surface of the flip chip, wherein the silicon dummy chip includes a passivation layer on the chip-mounting surface to cover the redistribution traces and the embedded component, the solder balls extending out of the passivation layer.