Patent ID: 8331170
Filing Date: 2012-12-11
Classification: G11C,H03K

Abstract:
1. A data transfer circuit, comprising: a first driver configured to drive a first line with data, wherein the data is a plurality of sequential data that have respective sequential orders in the sequence of data and are consecutively driven on the first line; a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data by inverting at least one of the plurality of sequential data based on the sequential order of the inverted sequential data in the sequence and not inverting at least one of the plurality of sequential data based on the sequential order of the non-inverted sequential data in the sequence; a second driver configured to drive a second line with the pattern-changed data; and a pattern restoration unit configured to receive the pattern-changed data transferred through the second line and re-invert the at least one data inverted by the pattern alteration unit.