Patent ID: 6029252
Filing Date: 2000-02-22
Classification: G06F,G11C,H03K

Abstract:
A clock generator for producing on first and second output terminals respective first and second clock signals, the clock signals being produced responsive to an input clock signal received at an input terminal, the clock generator comprising:a delay circuit having an input coupled to the input terminal, the delay circuit being operable to generate a delayed clock signal at an output, the delay circuit delaying the input clock signal applied to its input by a phase shift corresponding to more than 0 degrees and less than 180 degrees of the input clock signal;a first gate operating according to an AND function, the first gate having a first input coupled to the input terminal and a second input coupled to the output of the delay circuit, the first gate having an output coupled to the first output terminal to apply the first clock signal to the first output terminal; anda second gate operating according to an OR function; the second gate having a first input coupled to the input terminal and a second input coupled to the output of the delay circuit, the second gate having an output coupled to the second output terminal to apply the second clock signal to the second output terminal.