Patent ID: 6715093
Filing Date: 2004-03-30
Classification: G06F

Abstract:
A method of creating repeatability of a system having multiple clock domains created by a plurality of intermediate clocks by causing a system reset function to take effect in all clock domains at the same time comprising:creating a global framing clock signal having a rising edge that corresponds to the rising edges of the plurality of clocks, wherein the global framing clock has a frequency equal to the lowest common denominator of the plurality of intermediate clocks or to some divisor thereof, wherein creating a global framing clock signal comprises: receiving an input of a system clock into a clock divider; dividing the system clock into the global framing clock signal using the clock divider; receiving the global framing clock signal as an input into a flip-flop timed by the system clock; and using an output data stream from the flip-flop as a framing clock to control the release of the system reset signal to the system, wherein the flip-flop is clocked by a delayed version of the system clock; receiving an asynchronous event; waiting for a rising edge of the global framing clock signal; and releasing the asynchronous event to the system when the rising edge of the global framing clock signal occurs.