Patent ID: 7064010
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method of forming chip-scale packages, comprising: providing a semiconductor wafer having an active surface with a plurality of semiconductor die locations separated by at least one street of semiconductor material and having a passive surface opposite the active surface; cutting at least one channel in the active surface of the semiconductor wafer along the at least one street of semiconductor material to expose a plurality of semiconductor die side surface; etching the plurality of semiconductor die side surfaces to remove a layer of semiconductor material containing cutting-induced defects; forming a first protective coating on the semiconductor wafer to cover the active surface and fill the at least one channel; removing a layer of semiconductor material from the passive surface of the semiconductor wafer to a depth sufficient to expose the first protective coating within the at least one channel; etching the passive surface of the semiconductor wafer such that the first protective coating exposed within the at least one channel forms at least one frame element protruding from the passive surface of the semiconductor wafer; forming a second protective coating on the semiconductor wafer to cover the passive surface; such that the second protective coating is anchored to the passive surface of the semiconductor wafer with the at least one frame element; and separating the semiconductor wafer along the at least one channel to form a plurality of individual chip-scale packages.