Patent ID: 6049252
Filing Date: 2000-04-11
Classification: H03F,H03G

Abstract:
A programmable-gain amplifier, comprising:a cascade connection of a plurality of differential amplifiers, each having a pair of bi-polar transistors having emitters which are commonly connected; anda current controller having output terminals for outputting emitter currents each supplied to the commonly connected emitters of the pair of bi-polar transistors of each of the differential amplifiers, a product of the emitter currents being controlled according to logic levels of a set of binary control signals supplied to the current controller; said current controller having a current mirror circuit comprising:an input bi-polar transistor having an emitter which is connected to a ground through an input MOS (Metal Oxide Semiconductor) transistor controlled to be ON, wherein a constant current is supplied through the input bi-polar transistor;output bi-polar transistors, each of the output bi-polar transistors having a collector connected to a corresponding one of the output terminals of the current controller, a base connected to a base of the input bi-polar transistor, and an emitter connected to the ground through a respective MOS transistor controlled to be ON, wherein a relative on-resistance of each of said respective MOS transistors to the input MOS transistor is designed to be in inverse proportion to a relative emitter size of said each of the output bi-polar transistors to the input bi-polar transistor; andcontrol bi-polar transistors, each of the control bi-polar transistors having a collector connected to a corresponding one of the output terminals of the current controller, a base connected to a base of the input bi-polar transistor, and an emitter connected to the ground through a respective control MOS transistor, wherein a relative on-resistance of each of said respective control MOS transistors to the input MOS transistor is designed to be in inverse proportion to a relative emitter size of said each of the control bi-polar transistors to the input bi-polar transistor, and wherein each of said control MOS transistors is switched according to the logic level of one of the binary control signals.