Patent ID: 9146431
Filing Date: 2015-09-29
Classification: G02F,H01L

Abstract:
1. A method for manufacturing an array substrate, comprising procedures of: forming a common electrode line ( 5 ), a common electrode ( 2 ) and a thin film transistor on a substrate ( 1 ), wherein the thin film transistor comprises a gate electrode ( 4 ), a source electrode ( 8 a ) and a drain electrode ( 8 b ); and forming an insulating layer ( 3 ) between the gate electrode ( 4 ) and the common electrode ( 2 ) to isolate the gate electrode ( 4 ) from the common electrode ( 2 ), wherein the method comprises the following steps: step A, forming the common electrode ( 2 ), the insulating layer ( 3 ), the gate electrode ( 4 ) and the common electrode line ( 5 ) on the substrate ( 1 ); step B, forming a gate electrode protection layer ( 6 ), an active layer ( 7 ), the source electrode ( 8 a ) and the drain electrode ( 8 b ) on a resultant structure of the step A; step C, forming a passivation layer ( 9 ) on a resultant structure of the step B, wherein a second through hole ( 12 ) is formed in the passivation layer ( 9 ); and step D, forming a pixel electrode ( 10 ) on a resultant structure of the step C, wherein the pixel electrode ( 10 ) is connected with the drain electrode ( 8 b ) through the second through hole ( 12 ).