Patent ID: 6653871
Filing Date: 2003-11-25
Classification: G06F,Y02D

Abstract:
A clock control circuit, comprising:a low speed clock supply unit which outputs a low speed clock; a high speed clock supply unit which outputs a high speed clock whose frequency is higher than the low speed clock; a selection unit which selects and outputs any one of the low speed clock output from the low speed clock supply unit and the high speed clock output from the high speed clock supply unit; a control unit which controls the selection of the clock by the selection unit; and a sleep control unit which allows at least one circuit, whose clock is to be switched-over from the low speed clock to the high speed clock, to go into a sleep state before the selection unit selects and outputs the high speed clock to the at least one circuit and allows the at least one circuit to go into a normal state after the high speed clock is selected and output from the selection unit.