Patent ID: 6114877
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A timing circuit, comprising:control logic that receives as input a clock signal that transitions from high to low and from low to high at regular intervals and produces from that clock signal a first output signal delayed relative to the input clock signal and a second output signal delayed relative to the input clock signal, said first output signal transitioning from high to low and low to high at regular intervals and said second output signal transitioning from high to low and low to high at regular intervals;said control logic including a first clock tree and a second clock tree, an output of said first clock tree serving as an input to said second clock tree and said first output signal coming from said first clock tree and said second output signal coming from said second clock tree;wherein the delay of said first and second output signals from the input clock signal and the timing relationship of the transitions of the first and second output signals relative to one another are induced substantially by the delay inherent in the respective clock trees from which they are generated; andfurther wherein the configuration of the control logic and the relative relationship of the first and second output signals is such that an active transition of each of the first and second output signals does not occur at the same time.