Patent ID: 7092471
Filing Date: 2006-08-15
Classification: H03K,H03L,H04L

Abstract:
1. A synchronization circuit, comprising: a plurality of samplers, the plurality of samplers sampling an input signal with a plurality of respective clock signals and producing a plurality of respective sampled output signals; at least one delay unit coupled to output of the plurality of samplers, the at least one delay unit providing a predetermined delay to the sampled output signals; at least one phase detector coupled to the output of at least one delay unit, the at least one phase detector determining whether the plurality of sampled output signals are different and producing at least one control signal, the at least one control signal indicating whether the plurality of sampled output signals are different; and an up-down counter coupled to an output of the at least one phase detector, the up-down counter adjusting a delay of the input signal according to the at least one control signal output by the at least one phase detector.