Patent ID: 6083791
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method of fabricating a two-transistor EEPROM cell, the method comprising the steps of:providing a silicon substrate of a first conductivity type;forming a plurality of spaced-apart field oxide (FOX) regions in the silicon substrate, the FOX regions being separated by cell substrate regions;forming an insulating layer on the cell substrate regions;forming a layer of first polysilicon (poly 1) oveylying the insulating layer;masking and patterning poly 1 to define openings in the poly 1 exposing portions of the FOX regions and exposing portions of the insulating layer;forming a layer of interpoly insulator overlying the poly 1, exposed portions of the FOX regions and exposed portions of the insulating layer;forming a plurality of second polysilicon (poly 2) word lines overlying the interpoly insulator;masking the interpoly insulator with a layer of patterned photoresist;performing a self-aligned stacked gate etch wherein the poly 2 word lines are utilized as a self-aligned mask to pattern the poly 1, thereby defining poly 1 floating gates of a two-transistor EEPROM cell, and wherein the layer of patterned photoresist is utilized as a mask to pattern the poly 1 to define poly 1 access transistor lines of a two-transistor EEPROM cell;forming simultaneously, combined drain/source regions of a second conductivity type in the silicon substrate between the poly 1 access transistor lines and the poly 1 floating gates, source regions of the second conductivity type in the silicon substrate adjacent to the poly 1 access transistor lines and drain regions of a second conductivity type adjacent to the poly 1 floating gates; andstripping the layer of patterned photoresist.