Patent ID: 8112590
Filing Date: 2012-02-07
Classification: G06F

Abstract:
1. A method of reducing command processing latency while maintaining memory coherence, comprising: providing a system comprising a plurality of chips, wherein at least one chip comprises a plurality of bus units; providing a memory map including memory addresses available to the system; and arranging the memory addresses into a plurality of groups, wherein a first of the plurality of the groups corresponds to a subset of memory addresses associated with a first chip in the system, wherein a command from a bus unit in the first chip accessing the first group is treated as coherent in the first chip and non-coherent for all other chips in the system, wherein a second of the plurality of the groups corresponds to a subset of memory addresses associated with the first chip in the system, and wherein a command from a bus unit in the first chip accessing the second group is treated as non-coherent with respect to all bus units in the first chip and all other chips in the system.