Patent ID: 6534787
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A N+/P+ Dual Poly Gate CMOS transistor having asymmetric short channel regions, and drain extension regions comprising:isolated silicon regions including a source and a drain; gate electrodes overlying said silicon regions having a length extending from said source to said drain, and including vertical sidewalls adjoining said source and drain; silicon single-channel regions, each single-channel region having a channel length less than said gate length, underlying said gate and extending from underneath said gate electrode vertical sidewall adjoining said source, toward said drain, said channel region formed by implanting ions of dopant at a predetermined angle, defined from said gate electrode vertical sidewall adjacent said source, into said channel region; and silicon drain extension regions, each drain extension region K extending underneath said gate from said drain, toward said channel region, said drain extension regions formed by implanting ions of dopant at a K predetermined angle, defined from said gate electrode vertical sidewall adjacent said drain, into said drain extension region, whereby said short channel region minimizes drain capacitance, and said lightly doped drain extension maximizes drain operation voltage.