Patent ID: 7539041
Filing Date: 2009-05-26
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array comprising a first block and a second block, the first block comprising a first memory cell having a first floating body and the second block comprising a second memory cell having a second floating body, the first memory cell being connected between a first bit line and a source line to which a source voltage is applied and having a first gate connected to a first word line, the second memory cell being connected between a second bit line and the source line and having a second gate connected to a second word line; a bit line isolation portion for transmitting data between the first bit line and a sense bit line, and for transmitting data between the second bit line and an inverted sense bit line; and a sense amplifier for equalizing the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, for pre-charging one of the sense bit line or the inverted sense bit line to a first pre-charge voltage higher than the equalization voltage and the other of the sense bit line or the inverted sense bit line to a second pre-charge voltage higher than the equalization voltage and lower than the first pre-charge voltage during a pre-charge operation, and for sensing and amplifying a voltage difference between the sense bit line and the inverted sense bit line during read and write operations.