Patent ID: 6246300
Filing Date: 2001-06-12
Classification: H01C,H01G

Abstract:
A passive network in the form of a chip, comprising:a chip wafer wherein internal conductors of a plurality of capacitors are led out at a first longitudinal side surface of the first chip wafer as first terminals, and wherein common frame electrodes of the plurality of capacitors are led out at both frontal side surfaces of the chip wafer;a plurality of resistance layer regions that are applied alongside one another on a surface of the chip wafer which correspond to the plurality of capacitors, each of the plurality of resistance layer regions having a respective second terminal connected to an internal conductor of a respective capacitor, and each of the plurality of resistance layer regions having a respective first terminal that is lead out at a second longitudinal side surface of the second chip wafer; anda ferrite wafer applied on a surface of the plurality of resistance layer regions, thereby producing a CCRL array.