Patent ID: 7366943
Filing Date: 2008-04-29
Classification: G06F

Abstract:
1. A synchronous transmission system comprising: a source clock source configured for generating a source clock signal at a corresponding first multiple of a reference clock signal, the source clock signal having a first nominally-aligned edge relative to an edge of the reference clock signal; a target clock source configured for generating a target clock signal at a corresponding second multiple of the reference clock signal, the target clock signal having a second nominally-aligned edge relative to the edge of the reference clock signal, the first and second multiples being unequal and providing a clock ratio between the source and target clock signals; first circuitry configured for outputting data according to a first bandwidth in response to a data accept signal synchronous with the source clock signal, the first circuitry including a sync counter configured for generating a periodic sync signal indicating the first and second nominally-aligned edges are aligned relative to each other; a data buffer configured for storing the output data, synchronous with the source clock signal, at a first location specified by a load pointer and outputting stored data from a second location specified by an unload pointer; an unload pointer counter configured for outputting the unload pointer synchronous with the target clock signal for output of the stored data according to a second bandwidth lower than the first bandwidth, the unload pointer counter enabled in response to deassertion of a first reset signal and configured for incrementing the unload pointer in response to a prescribed edge of the target clock signal that has a same polarity as the first and second nominally-aligned edges; a load circuit configured for outputting the data accept signal at selected instances corresponding to the second multiple relative to the first multiple of the source clock cycles, the load circuit including a load pointer counter configured for outputting the load pointer from a selected initial value and synchronous with the source clock signal, the load pointer counter enabled in response to deassertion of a second reset signal and configured for selectively incrementing the load pointer in response to the corresponding prescribed edge of the source clock signal; and a reset synchronizer circuit including: (1) a first flip-flop configured for outputting the deassertion of the first reset signal, coincident with an inverse-polarity edge of the source clock signal immediately preceding the first and second nominally-aligned edges, in response to a global reset signal deasserted concurrent with assertion of the periodic sync signal during the inverse-polarity edge of the source clock signal that immediately precedes the first nominally-aligned edge, a time interval between the inverse-polarity edge and the first nominally-aligned edge corresponding to one half of a clock cycle of the source clock signal and providing an adequate setup time between the unload pointer counter detecting the deassertion of the first reset signal and a stable state for the unload pointer counter; and (2) a second flip-flop configured for outputting the deassertion of the second reset signal, coincident with the first and second nominally-aligned edges, in response to the global reset signal deasserted concurrent with assertion of the periodic sync signal during the first nominally-aligned edge of the source clock signal.