Patent ID: 6222775
Filing Date: 2001-04-24
Classification: G11C

Abstract:
An integrated circuit to be connected to a first supply voltage and to a reference voltage, comprising:a first matrix of floating gate memory cells organized in a first plurality of subdivision blocks, each subdivision block being organized in a plurality of words of a plurality of bits, all the memory cells belonging to one of the first plurality of subdivision blocks being formed in a first confined region of a semiconductor substrate confined by a first isolating buried region and by a first perimeter isolating region both of a conductivity opposite to a conductivity of the confined region of the semiconductor substrate;a first plurality of wordlines and bitlines for individually selecting the plurality of words and the plurality of bits of each subdivision block of the first matrix;a first hierarchical address decoder for accessing the plurality of wordlines and bitlines, to read, program and erase information in the memory cells of the first matrix;a second matrix of floating gate memory cells organized in a second plurality of subdivision blocks, each block being organized in a plurality of words of a plurality of bits, all the memory cells belonging to one of the second plurality of subdivision blocks being formed in a second confined region of the semiconductor substrate confined by a second isolating buried region and by a second perimeter isolating region both of a conductivity opposite to a conductivity of said second confined region of the semiconductor substrate, information stored in the second matrix being organized in pages, each page being contained in a row of memory cells of one of said second subdivision blocks;a second plurality of wordlines and bitlines for individually selecting the plurality of words and the plurality of bits of each subdivision block of the second matrix;a second hierarchical address decoder for accessing the second plurality of wordlines and bitlines, to read, program and erase information in the memory cells of the second matrix, said second hierarchical address decoder including a row decoder for addressing the wordline of all the memory cells of a selected row of one of said second subdivision blocks, co-operating with a column decoder for selecting single memory cells of the rows;at least one first charge pump circuit generating a first boosted voltage of a same polarity as the first supply voltage, and at least one second charge pump circuit generating a second boosted voltage of an opposite polarity as the first supply voltage, said second boosted voltage being applied during an erasing phase to a single wordline selected by said row decoder, to page-erase information by applying said first boosted voltage to a common source of all the memory cells of one of the second subdivision blocks and to the second confined region of the semiconductor substrate containing all the memory cells of the one of the second subdivision blocks; anda logic circuit for confirming a programmed state of each memory cell containing a logic zero of non-erased rows of the one of the second subdivision blocks after one or more rows or pages have been erased, by applying said first boosted voltage to one wordline at a time and said first supply voltage to one or more bitlines at a time for confirming a preexistent programmed state, while keeping the common source of all the memory cells of the second subdivision block and the second confined region of the semiconductor substrate at the reference voltage.