Patent ID: 7376041
Filing Date: 2008-05-20
Classification: G11C

Abstract:
1. A double data rate (DDR) semiconductor memory device, comprising: a memory cell array to store data; a data input portion to serially receive an i-number of n-bit write data from i input lines and to convert the i-number of n-bit write data to parallel data, and to output the parallel i-number of n-bit write data to the memory cell array in response to a write control signal; a data output portion to convert to serial data an i-number of 2n-bit read data that are inputted in parallel from the memory cell array to i output lines and to generate an i-number of 2n-bit output data in response to a read control signal; a data I/O gate to transmit the parallel i-number of n-bit write data outputted from the data input portion to n times i-number of bit line pairs of the memory cell array in response to the write control signal, and to transmit the i-number of 2n-bit read data outputted from a data I/O controller to generate the read control signal, and to generate the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal.