Patent ID: 6151367
Filing Date: 2000-11-21
Classification: H03D,H03J,H04L,H04N

Abstract:
A digital demodulator comprising local oscillation means, mixing means, A/D conversion means, hilbert transform means, delay means, multiplication means, filter means, frequency error detect means, a loop filter and numerically controlled oscillation means:wherein the hilbert transform means comprises:a first shift register for sequentially shifting a received signal to multiple shift registers;a second shift register for sequentially shifting a last delay output of the first shift register to multiple shift registers;a first adding unit having a number of adders for selectively adding signals output by the first and second shift registers;a multiplication unit having a number of multipliers for respectively multiplying the signals output from the adders in the first adding unit by predetermined tap coefficients; anda second adding unit having a number of adders for performing selective adding of each signal output from the number of multipliers in the multiplication unit, andwherein the frequency error detect means comprises:a first delay circuit for delaying the signal I from the filter means;a second delay circuit for delaying the signal Q from the filter means;a first exclusive OR circuit for performing an exclusive OR operation with respect to the output of the delay circuit and the signal Q;a second exclusive OR circuit for performing the exclusive OR operation with respect to the output of the delay circuit and the signal I; andan adder for summing up the outputs of the two exclusive OR circuits.