Patent ID: 6917387
Filing Date: 2005-07-12
Classification: H04J,H04N

Abstract:
1. An arrangement for time-correct combination of a first, continuous digital data stream (V 1 ), comprising a sync signal (S), with a second, discontinuous digital data stream (V 2 ), the arrangement comprising: a first delay member ( a second delay member ( a memory ( means ( wherein the first period of time is chosen to be such that the output data streams of the first delay member ( 2 ) and the memory ( 4 ) occur at the means ( 6 ) for combining or processing in a desired temporal relation to each other, and wherein the second period of time is chosen to be such that the read pointer (RP) does not catch up with the write pointer (WP) during the process of reading from the memory ( 4 ), also when taking the discontinuities occurring in the second data stream (V 2 ) into account.