Patent ID: 6069393
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A photoelectric converter comprising:a substrate bearing a layered structure comprising in order, a first conductive layer, a first insulating layer, a semiconductor layer, an ohmic contact layer, a second conductive layer, a second insulating layer, and a third conductive layer, said photoelectric converter comprising the following components formed from said layered structure:a plurality of one-dimensionally arranged photoelectric conversion elements, each photoelectric conversion element including a lower electrode formed from said first conductive layer, said first insulating layer, said semiconductor layer, said ohmic contact layer having a first gap therein, a pair of upper electrodes formed from said second conductive layer and separated by said first gap, and said second insulating layer formed over said first gap;a plurality of thin-film transistors (TFT), each TFT having a gate electrode formed from said first conductive layer, said first insulating layer, said semiconductor layer, said ohmic contact layer having a second gap therein, and a drain electrode and a source electrode formed from said second conductive layer and separated by said second gap, and said second insulating layer formed over said second gap;a plurality of output lines formed from said first conductive layer;a first plurality of through holes formed from said second conductive layer, wherein a respective one of said drain and source electrodes is connected to a respective one of said upper electrodes of said photoelectric conversion device, and the other of said drain and source electrodes is connected to a respective one of said output lines through a respective one of said first plurality of through holes;a plurality of common lines formed from said third conductive layer, each common line connecting to at least two of said plurality of output lines respectively through a second plurality of through holes formed from said second and third conductive layers, said second conductive layer being further positioned between one of said common lines and one of said output lines at a respective intersection where said one common line overlaps said one output line and capable of being maintained at a first predetermined potential sufficiently high to substantially eliminate stray capacitance at said intersection.