Patent ID: 7107438
Filing Date: 2006-09-12
Classification: G06F

Abstract:
1. An apparatus for correcting a prediction of a branch instruction in a pipeline microprocessor, the prediction predicting whether a branch condition specified by the branch instruction is satisfied in architected status flags of the microprocessor, the apparatus comprising: early status flags, corresponding to and storing a newer state than the architected status flags, said early status flags having a valid indicator; early branch correction logic, for correcting the prediction of the branch instruction if said valid indicator indicates said early status flags are valid and if said early status flags indicate the prediction is incorrect; and logic, coupled to said early status flags, for invalidating said early status flags if an early result of an instruction that precedes the branch instruction and that specifies modification of the status flags is invalid, wherein said logic copies the architected status flags to said early status flags and validates said early status flags if the microprocessor pipeline is flushed.