Patent ID: 8097512
Filing Date: 2012-01-17
Classification: H01L

Abstract:
1. A method of fabricating a trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising: depositing a first semiconductor layer upon a substrate, wherein the substrate and first semiconductor layer are doped with a first type of impurity, the substrate and the first semiconductor layer comprising a drain of the TMOSFET; doping a first portion of the first semiconductor layer with a second type of impurity to form a first plurality of well regions; doping a second portion of the first semiconductor layer with the second type of impurity to form a second plurality of well regions substantially centered within the first plurality of well regions, the first and second well regions comprising body regions of the TMOSFET and gate regions of a junction field effect transistor (JFET); doping a third portion of the first semiconductor layer with the first type of impurity to form a third plurality of well regions substantially centered within the second plurality of well regions, the third well regions comprising source regions of the TMOSFET; etching a plurality of trenches in the first semiconductor layer substantially centered within the plurality of first, second and third well regions, the trenches having vertical walls that extend beneath the first well regions; forming a dielectric proximate the plurality of trenches; depositing a second semiconductor layer in the plurality of trenches, wherein the second semiconductor layer is doped with the first type of impurity, the second semiconductor layer comprising a trench gate of the TMOSFET; and depositing a metal layer, wherein the metal layer electrically couples the first, second and third plurality of well regions and a fourth portion of the first semiconductor layer disposed between the second plurality of well regions, the fourth portion comprising a conducting channel of the JFET, the metal layer comprising a source contact of the TMOSFET and forming a Schottky junction with the fourth portion of the first semiconductor layer.