Patent ID: 6381680
Filing Date: 2002-04-30
Classification: G06F

Abstract:
A data processing system in which at least two memory address regions are assigned, said data processing system comprising:a main memory for storing data, said main memory being assigned a first memory address region of said memory address regions; an output control circuit including a memory unit for storing data, said memory unit being assigned a second memory address region of said memory address regions; and a microprocessor, said microprocessor comprises: a processing circuit which executes an instruction and generates an address, a cache memory, coupled to said processing circuit, for storing data, and a logical circuit, coupled to said cache memory, for controlling writing of data in said cache memory in accordance with said address corresponding to said first memory address region and not writing of data in said cache memory in accordance with said address corresponding to said second memory address region, wherein said logical circuit includes a plurality of registers which store address values indicating said second memory address region, said address values being used in said logical circuit to control whether data is written in said cache memory or not.