Patent ID: 8581395
Filing Date: 2013-11-12
Classification: H01L,H03G,H05K

Abstract:
1. An electronic device comprising: a) a wiring substrate having a first main surface, a second main surface opposite the first main surface, a plurality of pads formed over the first main surface, a conductive layer formed over the second main surface, and an insulating layer formed over the second main surface; b) a semiconductor chip mounted over the first main surface of the wiring substrate and being electrically connected to a first pad of the plurality of the pads; c) a passive component mounted over the first main surface of the wiring substrate and being electrically connected to a second pad of the plurality of the pads; and d) a sealing body sealing the semiconductor chip and the passive component, wherein the insulating layer is formed to partially cover the conductive layer and has a plurality of first openings to provide a plurality of first conductive patterns formed of the conductive layer and a plurality of second openings to provide a plurality of second conductive patterns formed of the conductive layer, wherein the plurality of second conductive patterns are arranged to surround the plurality of first conductive patterns in a plan view, wherein the plurality of first conductive patterns are arranged in a matrix formation in the plan view, and wherein an each area of the plurality of first conductive patterns is larger than an each area of the plurality of second conductive patterns.