Patent ID: 8193053
Filing Date: 2012-06-05
Classification: G11C,H01L

Abstract:
1. A method for manufacturing an integrated semiconductor nonvolatile storage device, comprising: forming a first semiconductor memory device region in or on a semiconductor substrate, wherein said first semiconductor memory device region includes a plurality of first split-gate memory cells each including a pair of first and second gate members, a first diffusion layer electrode, and a second diffusion layer electrode, wherein said first and second gate members are disposed parallel to each other, and wherein said first and second diffusion layer electrodes are disposed in a direction perpendicular to said first and second gate members; and forming a second semiconductor memory device region in or on said semiconductor substrate, wherein said second semiconductor memory device region includes a plurality of second split-gate memory cells each including a pair of third and fourth gate members, a third diffusion layer electrode, and a fourth diffusion layer electrode, wherein said third and fourth gate members are disposed parallel to each other, and wherein said third and fourth diffusion layer electrodes are disposed in a direction perpendicular to said third and fourth gate members, wherein a first gate insulating film having a charge retention portion is formed between said semiconductor substrate and said second gate members, and a second gate insulating film of a same material as said first gate insulating film is formed between said semiconductor substrate and said fourth gate members, wherein said second diffusion layer electrode of each of said first split-gate memory cells in said first semiconductor memory device region and said fourth diffusion layer electrode of each of said second split-gate memory cells in said second semiconductor memory device region are formed by ion implantation, and wherein said ion implantation includes the following steps: (a) forming said second diffusion layer electrode by ion implantation in a state that a mask layer or a photoresist layer is formed on said second semiconductor memory device region, (b) forming a silicon oxide film on said semiconductor substrate after the step (a), (c) forming a sidewall spacer on said second gate member and said fourth gate member by anisotropically etching the silicon oxide film formed by the step (b), and (d) forming said fourth diffusion layer electrode by ion implantation, after the step (c), in a state that a mask or a photoresist layer is formed on said first semiconductor memory device region.