Patent ID: 6291869
Filing Date: 2001-09-18
Classification: G11C,H03K

Abstract:
A semiconductor circuit device having operation and stand-by modes, comprising:a main power supply line receiving a power supply voltage;a sub power supply line;a first switching element connected between said main and sub power supply lines, turned on in said operation mode, and turned off in said stand-by mode;a main ground line receiving a ground voltage;a sub ground line;a second switching element connected between said main and sub ground lines, turned on in said operation mode, and turned off in said stand-by mode;a first buffer power supply line;a first buffer ground line;a second buffer power supply line;a second buffer ground line;a plurality of first logic circuits each connected between said first buffer power supply and first buffer ground lines for supplying an output signal at a first logic level in said stand-by mode;a plurality of second logic circuits each connected between said second buffer power supply and second buffer ground lines for supplying an output signal at a second logic level complementary to said first logic level in said stand-by mode; anda selecting circuit disposed to connect said first buffer power supply line to said main power supply line, said first buffer ground line to said sub ground line, said second buffer power supply line to said sub power supply line and said second buffer ground line to said main ground line when said plurality of first logic circuits supply output signals at a logic high level as said first logic level and said plurality of second logic circuits supply output signals at a logic low level as said second logic level in said stand-by mode, and disposed to connect said first buffer power supply line to said sub power supply line, said first buffer ground line to said main ground line, said second buffer power supply line to said main power supply line and said second buffer ground line to said sub ground line when said plurality of first logic circuits supply output signals at the logic low level as said first logic level and said plurality of second logic circuits supply output signals at the logic high level as said second logic level in said stand-by mode.