Patent ID: 7250681
Filing Date: 2007-07-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of first level wires; a low-dielectric constant film disposed on the first level wires; a plurality of first flat vias embedded in the low-dielectric constant film and connected to the first level wires, each of the first flat vias being defined by at least four first side walls extending along a longitudinal direction of the first level wires and at least four second side walls extending along an orthogonal direction to the longitudinal direction on a plane where the first level wires are disposed, each of the first flat vias having a first length in the longitudinal direction and a second length in the orthogonal direction, wherein an aspect ratio of at least one of the first and second lengths to a height perpendicular to the plane where the first level wires are disposed is over 1; and a plurality of second level wires disposed in the low-dielectric constant film and connected to the first flat vias.