Patent ID: 7865644
Filing Date: 2011-01-04
Classification: G06F

Abstract:
1. A method for use with a bus and associated bus controller, wherein the bus controller has respective master and slave interfaces for use in selectively interconnecting master devices and slave devices, said method comprising the steps of: connecting one or more of said master devices to one of said master interfaces of said bus controller; connecting each one of said slave devices to the same particular one of said slave interfaces of said bus controller; operating a selected master device to send multiple commands to selected connected slave devices in accordance with a command pipelining procedure; wherein signals from said particular one of said slave interfaces are multi-dropped to each one of said slave devices, and further wherein signals from each one of said slave devices responsive to said commands are received by a logic OR gate that generates an output signal that is received by the bus controller; and wherein each connected slave device responds to each received command at a same fixed number of clock cycles after each received command, wherein responses from each connected slave device always occur at said fixed number.