Patent ID: 8208081
Filing Date: 2012-06-26
Classification: G09G

Abstract:
1. A liquid crystal display device comprising: a plurality of pixels that are arranged in columns and rows so as to form a matrix pattern, each said pixel including a liquid crystal layer and a plurality of electrodes for applying a voltage to the liquid crystal layer, wherein each said pixel includes a first subpixel and a second subpixel, having liquid crystal layers to which mutually different voltages are applicable, and two switching elements that are provided for the first and second subpixels, respectively, and wherein each of the first and second subpixels includes a liquid crystal capacitor formed by a counter electrode and a subpixel electrode that faces the counter electrode through the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer, and a storage capacitor counter electrode that is opposed to the storage capacitor electrode with the insulating layer interposed between them, and wherein the counter electrode is a single electrode provided in common for the first and second subpixels, while the storage capacitor counter electrodes of the first and second subpixels are electrically independent of each other, and wherein a storage capacitor counter voltage to be applied to each said storage capacitor counter electrode by way of its associated storage capacitor line has a first period (A) with a first waveform during one vertical scanning period, the first waveform oscillating between multiple voltage levels in a first cycle time (P wherein while the two switching elements are both ON, a display signal voltage is applied to the respective subpixel electrodes and respective storage capacitor electrodes of the first and second subpixels; after the two switching elements have been turned OFF, voltages at the respective storage capacitor counter electrodes of the first and second subpixels change; and if an interval between a point in time when the two switching elements in ON state have just been turned OFF and a point in time when the storage capacitor counter voltage changes for the first time is βH, the device satisfies the inequality TP/4≦β<3·TP/4, wherein four display states, in which either the luminance ranking of the first and second subpixels or the combination of polarities of the display signal voltages with respect to the counter electrode changes one after another, appear in each series of four vertical scanning periods, and wherein both the interval at which the first and second subpixels reverse their luminance ranking and the interval at which the polarity of the display signal voltage is inverted with respect to the counter electrode are four vertical scanning periods but have a phase difference of one vertical scanning period between them.