Patent ID: 8624630
Filing Date: 2014-01-07
Classification: H03L,H04L

Abstract:
1. A phase discriminator, comprising: a trigger, a delay unit, a latch connected to the trigger, a first XOR gate connected to the trigger and the delay unit, a second XOR gate connected to the trigger and the latch, the phase discriminator being used for receiving a data signal and a clock signal and outputting an error signal representing phase relationship between the clock signal and the data signal and a reference signal related to flip of the data signal, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset current for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset current for controlling amplitude of reference signal output by the second XOR gate.