Patent ID: 6381702
Filing Date: 2002-04-30
Classification: G04G

Abstract:
An electronic timepiece comprising:an oscillation circuit; a system clock generation circuit for receiving an output of the oscillation circuit and generating a system clock based on the output of the oscillation circuit; a frequency division circuit for frequency dividing the output of the oscillation circuit and producing a frequency-divided output signal used for counting time; a ROM for storing program data used for performing processing procedures including a time-measuring operation based on the system clock; a CPU for interpreting the data programmed in the ROM and performing arithmetic processes in accordance therewith; a RAM for storing data; an interrupt signal generation circuit for generating an interrupt signal and supplying the interrupt signal to the CPU; a slowdown/speedup data input port for taking in slowdown/speedup data supplied from outside the timepiece; a logical slowdown/speedup circuit for adjusting the accuracy of the timepiece by varying the frequency division ratio of the frequency division circuit to modify the frequency-divided output signal to adjust time counting accuracy of the timepiece; and a slowdown/speedup data storing circuit for storing slowdown/speedup data that is used to determine the amount of variation of the frequency division ratio performed by the logical slowdown/speedup circuit; wherein the logical slowdown/speedup circuit is responsive to the interrupt signal from the interrupt signal generation circuit to perform accuracy adjustment by varying the frequency dividing ratio of the frequency division circuit in accordance with the program data in the ROM at least at two cycles which are counted in the RAM by the CPU, and causes the slowdown/speedup data to be fetched through the slowdown/speedup data input port and stored in the slowdown/speedup data storing circuit at the two cycles in an arbitrary combination according to the data programmed in the ROM.