Patent ID: 6904579
Filing Date: 2005-06-07
Classification: G06F

Abstract:
1. A method of measuring a constraint parameter of a component in an integrated circuit represented in digital form, said method comprising: measuring a first delay between two nodes forming a portion of a path from an input terminal to an output terminal of said component; determining an approximate value of said constraint parameter based on said first delay; formulating an optimal range around said approximate value for said constraint parameter; applying an input signal to said component based on a possible value for said constraint parameter, wherein said possible value is contained in said optimal range; examining an output signal generated by said component to determine whether said component would be operational with said possible value for said constraint parameter; wherein said component comprises a flip-flop and wherein said two nodes comprise said input terminal and a node connecting two latches forming said flip-flop; measuring a second delay in generating an inverted clock signal from a clock signal, wherein said clock signal and said inverted clock signal are provided as inputs to transistors contained in said flip-flop; and wherein said constraint parameter comprises a pulse width of the clock signal and said approximate value is computed by adding said second delay and said first delay.