Patent ID: 6326257
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A method of fabricating a static random access memory, comprising:forming a stacked gate on a substrate;forming a lightly doped source region and a lightly doped drain region in the substrate at two sides of the stacked gate;forming a first spacer on a sidewall of the stacked gate at the side of the lightly doped source region, wherein the first spacer covers a part of the lightly doped source region and leaves the other part of the lightly doped source region exposed;forming a second spacer on the other sidewall of the stacked gate at the side of the lightly doped drain region, wherein the first spacer is thinner than the second spacer;performing an ion implantation step with the first and second spacers as a mask to form a heavily doped source region and a heavily doped drain region in the substrate, the lightly and heavily doped source region forming a source region, while the lightly and heavily doped drain region forming a drain region;performing a self-aligned silicidation step to form a metal silicide layer on the source region, the drain region and the stacked gate;forming a dielectric layer over the substrate;forming an opening in the dielectric layer to expose the metal silicide layer on the source region; andfilling the opening with a conductive layer to form a ground voltage contact window.