Patent ID: 6430649
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A method for enforcing dependencies between memory references in a load store unit, the load store unit including a load buffer for storing read requests and a store buffer for storing write requests between a processor and a memory, the method comprising:receiving a memory request in the load store unit; if the memory request is a write request, storing the write request in the store buffer, and if the write request is associated with a watch address, storing the watch address in the store buffer, the watch address specifying that a subsequent load from the watch address cannot occur before the associated write request completes, wherein the watch address can refer to a memory location other than a target memory location for the write request; and if the memory request is a read request, storing the read request in the load buffer, and if the read request is directed to the same address as a matching watch address in the store buffer, waiting for a write request associated with the matching watch address to complete before completing the read request, wherein the watch address can refer to a memory location other than a target memory location for the read request.