Patent ID: 8972471
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. An arithmetic module, comprising: a first adder including two input ends for receiving external data signals and an output end for outputting first addition result signals; a first shifter coupled to the output end of the first adder for receiving the first addition result signals generated by the first adder; a multiplier including a first input end coupled to the first shifter, a second input end for receiving an external coefficient, and an output end for outputting multiplication result signals; a digit alignment unit coupled to the output end of the multiplier for receiving the multiplication result signals generated by the multiplier to align digits of the multiplication result signals with those of input signals from an external accumulative register; a second adder including two input ends coupled to the digit alignment unit, and an output end for outputting second addition result signals; and a second shifter coupled to the output end of the second adder for receiving the second addition result signals generated by the second adder and outputting second shift result signals to the external accumulative register.