Patent ID: 6163057
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A diffusion region structure in a semiconductor device wherein said diffusion region is applied with alternating voltages in an operation of said semiconductor device, said structure comprising:at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration, said at least one diffusion region being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration; anda diffusion capacitance reduction layer provided under each said at least one diffusion region so as to be in contact with an entire bottom of said diffusion region, each said diffusion capacitance reduction layer being made of an insulating material to thereby reduce a parasitic capacitance between a respective said diffusion region and said semiconductor bulk region;wherein each said capacitance reduction layer extends only on an entire part of said bottom of a respective said diffusion region so as to true up both edges of each of said diffusion capacitance reduction layer and said diffusion regions.