Patent ID: 6449210
Filing Date: 2002-09-10
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a first sub-array, the first sub-array including a first plurality of memory cells coupled to a first plurality of row lines and a first plurality of column lines, the first plurality of row lines positioned substantially orthogonal to the first plurality of column lines; row address decode circuitry coupled to the first plurality of row lines and adapted to select and activate at least one of the first plurality of row lines; a first plurality of column select lines positioned substantially parallel to the first plurality of row lines; first column address decode circuitry coupled to the first plurality of column select lines and adapted to select a subset of the first plurality of column lines, the first column address decode circuitry being positioned proximate at least one of a first and a second end of the first plurality of column select lines; and a plurality of input/output lines positioned substantially parallel to the first plurality of column lines.