Patent ID: 9165610
Filing Date: 2015-10-20
Classification: G11C,H01L

Abstract:
1. A memory array, comprising: first, second, third, and fourth memory cells each having a first transistor and a second transistor, each of the first transistors and second transistors having a source, a drain, and a gate; a first word-line electrically coupled with the gate of the first transistor of the first memory cell and the gate of the first transistor of the second memory cell; a second word-line electrically coupled with the gate of the second transistor of the first memory cell, the gate of the second transistor of the second memory cell, the gate of the first transistor of the third memory cell, and the gate of the first transistor of the fourth memory cell; and a third word-line electrically coupled with the gate of the second transistor of the third memory cell and the gate of the second transistor of the fourth memory cell.