Patent ID: 6101229
Filing Date: 2000-08-08
Classification: G11B,H04L

Abstract:
A data synchronization circuit comprising:a synchronization timeout counter operable to provide a synchronization timeout counter signal, the synchronization timeout counter signal operable to provide the synchronization timeout counter signal in an enabled state during a predefined synchronization period;a compare circuit operable to receive a digital read signal and to compare the digital read signal to a known reference during the predefined synchronization period, the compare circuit operable to generate a synchronization detect signal in said enabled state if the digital read signal is found to be equivalent to the known reference during the predefined synchronization period; anda header timer circuit operable to generate a header timer signal in said enabled state during a predefined header period in response to receiving a read enable signal, the synchronization timeout counter operable to receive the header timer signal and to provide the synchronization timeout counter signal in said enabled state after the expiration of the predefined header period.