Patent ID: 6052301
Filing Date: 2000-04-18
Classification: G11C,H01L

Abstract:
A semiconductor memory device having a plurality of memory cells and a plurality of conducting layers formed on a semiconductor substrate, comprising:a plurality of main word lines composed of a first conducting layer formed on said semiconductor substrate and arranged in a row direction in the region of said memory cells;a plurality of sub word lines composed of a second conducting layer positioned below said first conducting layer formed on said semiconductor substrate; andsub word decoder circuits for driving said sub word lines, positioned along the path of said main word lines;wherein, in the region in which said sub word decoder circuits are formed, the pattern of said main word lines has a shape whereby said pattern temporarily branches and splits into a plurality of lines and then reconverges, along said row direction, island-shaped patterns which are electrically different from said main word lines being formed within said split region by means of said first conducting layer.