Patent ID: 7602023
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A CMOS arrangement of transistors formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said CMOS arrangement comprising a first CMOS pair, said first CMOS pair comprising a first PMOS and a first NMOS, and a second CMOS pair, said second CMOS pair comprising a second PMOS and a second NMOS: said first PMOS comprising: said first NMOS comprising: said second PMOS comprising: said second NMOS comprising: wherein said second P-type drain region is separated by a first offset distance from said third gate and said channel region underlying said third gate and said first P-type drain region is separated by a second offset distance from said first gate and said channel region underlying said first gate, said first offset distance being greater than said second offset distance; and wherein said second N-type drain region is separated by a third offset distance from said fourth gate and said channel region underlying said fourth gate and said first N-type drain region is separated by a fourth offset distance from said second gate and said channel region underlying said second gate, said third offset distance being greater than said fourth offset distance; said arrangement further comprising an N-type isolation layer underlying said second P well and at least a portion of said first and second N wells, wherein said first N well and said second N well in combination vertically surround said second P well and overlap said N-type isolation layer to isolate said second P well from said substrate.