Patent ID: 6789169
Filing Date: 2004-09-07
Classification: G06F

Abstract:
An integrated circuit for use with a processor based system having a processor and a system memory, the integrated circuit comprising:a system memory controller structured to control the system memory of the processor based system; a processor interface coupled to the system memory controller, the processor interface structured to transmit information between the processor and the system memory; and a cache memory integrated with the system memory controller and the processor interface and coupled to the system memory controller and the processor interface, the cache memory comprising: a dynamic random access memory (â€œDRAMâ€ ) array; a tag memory; and a cache memory controller coupled to the DRAM array, the tag memory, the processor interface and the system memory controller, the cache memory controller being operable to receive a request for access to the cache memory, and, in response thereto, to initiate an access to the tag memory and to initiate an access to the DRAM array, the cache memory controller initiating the access to the DRAM array before receiving a tag from the tag memory, the cache memory controller further being operable to determine based on the tag whether the access to the cache memory will result in a cache hit and, in response to determining that the access will result in a cache hit, to couple data from the DRAM array to the processor, the cache memory controller further being operable to apply to the system memory controller a request for access to the system memory responsive to receiving the request for access to the cache memory and before the cache memory controller receives a tag from the tag memory, the cache memory controller being further operable to couple data accessed from the system memory to the processor responsive to the cache memory controller determining that the access to the cache memory will not result in a cache hit.