Patent ID: 9029922
Filing Date: 2015-05-12
Classification: G11C,H01L

Abstract:
1. A semiconductor memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a first insulating region located above said floating body region; second insulating regions adjacent to said floating body region; a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions, wherein: said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region.