Patent ID: 9032279
Filing Date: 2015-05-12
Classification: G06F

Abstract:
1. A memory device comprising: a parity circuit configured to detect an error using a plurality of command signals and a plurality of address signals, to generate asynchronous error information at the time of the error detection, and to generate synchronous error information by synchronizing the asynchronous error information with parity latency; a command shift circuit configured to shift the plurality of command signals by a delay value corresponding to the parity latency in synchronization with a control clock, to output shifted command signals, and to initialize command signals being shifted when the asynchronous error information indicates generation of an error; a clock control circuit configured to deactivate the control clock when there is no valid command signal among command signals being shifted in the command shift circuit; a decoder circuit configured to decode command signals output from the command shift circuit; a command/address shift circuit configured to shift the plurality of command signals and the plurality of address signals by a delay value corresponding to the parity latency in synchronization with the control clock, to output shifted command signals and address signals; and an error log circuit configured to store command signals and address signals, which has been shifted by the command/address shift circuit, when the synchronous error information is activated.