Patent ID: 9121902
Filing Date: 2015-09-01
Classification: G01R

Abstract:
1. A method that accepts a virtual scan pattern stored in an automatic test equipment (ATE) for generating a broadcast scan pattern to test a scan-based integrated circuit by applying the virtual scan pattern to at least one input pin of the scan-based integrated circuit through a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells, the scan chains coupled to the broadcaster, said method comprising: a) transmitting the virtual scan pattern stored in the ATE to one or more scan inputs of the broadcaster for generating the broadcast scan pattern to test manufacturing faults in the scan-based integrated circuit; and b) comparing a test response of the scan-based integrated circuit with an expected test response, wherein the broadcaster is a solely combinational logic network comprising one or more logic gates, the logic gate further comprising an AND gate, an OR gate, a NAND gate, a NOR gate, a multiplexer, a buffer, or an inverter, and wherein application of the virtual scan pattern to the at least one input pin of the scan-based integrated circuit through the broadcaster decreases a test application time relative to a test application time for a test that does not utilize the broadcaster.