Patent ID: 6060746
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A method for forming a power transistor having vertical field effect transistors, comprising the steps of:providing a substrate;providing a first diffusion layer being of a first conductivity type overlying said substrate;forming a nitride etch stop layer overlying said first diffusion layer;forming a first dielectric layer overlying said nitride etch stop layer;forming a gate conductor layer overlying said first dielectric layer;forming a cap nitride layer overlying said gate conductor layer;sequentially removing portions of each of said cap nitride layer, said gate conductor layer, and said first dielectric layer, to form a plurality of openings exposing surface regions of said nitride etch stop layer to form sidewalls in said gate conductor layer, said sidewalls bounding said openings;forming gate oxide on said sidewalls of said gate conductor layer bounding said openings;forming a plurality of pillars of said first or a second conductivity type, wherein each pillar fills one of said openings and has an exposed pillar surface planar with or extending above said cap nitride layer;removing said cap nitride layer to form holes laterally bounded by said pillars;filling said holes with a doped material providing a second diffusion layer of said first conductivity type;forming (i) drain electrodes of said first conductivity types in said pillars at locations laterally adjacent said first dielectric layer and overlying said first diffusion layer and (ii) source electrodes of said first conductivity type in said pillars at locations laterally adjacent said second diffusion layer, whereby a channel of first or second conductivity type is located in each said pillar between said drain and source electrodes and laterally adjacent said gate oxide on said sidewalls of said gate conductor layer.