Patent ID: 6515759
Filing Date: 2003-02-04
Classification: G06F,G06K

Abstract:
An integrated circuit comprising:a. a processor that provides an address for fetching an executable instruction; and b. a cache that provides the executable instruction in response to the address, the cache comprising: (1) a first memory; and (2) a decompressor that reads a table and an information block from a provided memory, wherein: (a) the table comprises a plurality of rows, each row corresponding to a respective tag value of a series of tag values, each row identifying a respective code block value; (b) the information block comprises a data item; and (c) the decompressor stores in the first memory a copy of the respective code block value of a row of the table, wherein: 1) the respective tag value of the row is identified in response to the data item; 2) the copy comprises the executable instruction; and 3) the code block value comprises more bits than the data item.