Patent ID: 7961535
Filing Date: 2011-06-14
Classification: G11C

Abstract:
1. A test method for use in a semiconductor memory device having a plurality of memory blocks, the method comprising: sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, respective ones of the word lines being sequentially selected from the plurality of respective memory blocks and enabled, wherein applying the stress to the word lines includes applying a voltage to the word lines greater than a voltage associated with a write command during a normal operation of the semiconductor memory device, wherein each of the sequentially applied test addresses comprises a block address to select any one of the plurality of memory blocks, and a line address to select any one of plural word lines within a selected memory block, wherein the selecting of the word lines includes wherein from an enabled time point of the word lines to a precharged time point of the word lines, no data access operation through bit lines corresponding to the word lines may be performed.