Patent ID: 8522060
Filing Date: 2013-08-27
Classification: G06F

Abstract:
1. A computer system, comprising: a plurality of nodes each including one or more Central Processing Units (CPU), said nodes being connected with each other; a main memory device and an input-output device that are shared between said nodes and connect with any of said nodes; and a power control circuit, wherein said plurality of nodes include one or more normal nodes and one or more specific nodes, each one of said one or more normal nodes connects directly with said main memory device and with said input-output device and includes a crossbar switch for switching connections between said main memory device, said input-output device and said one or more specific nodes, and each one of said one or more specific nodes connects with said main memory device and with said input-output device through any one of said one or more normal nodes with no exception, and wherein said power control circuit controls each one of said one or more specific nodes so that said specific node transfers to a power-saving state in which power consumption may be reduced, and does not control said one or more normal nodes.