Patent ID: 6507085
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate of p-type; a semiconductor layer of n-type formed on said semiconductor substrate; a first impurity region of said p-type formed in said semiconductor layer, extending from a surface of said semiconductor layer to an interface of said semiconductor layer and said semiconductor substrate, to define an island region; a buried impurity region of said n-type formed apart from said first impurity region at said interface within said island region, said buried impurity region being of a higher concentration than said semiconductor layer; a semiconductor element formed in the surface of said semiconductor layer above said buried impurity region; and a diode having a second impurity region of said p-type and a third impurity region of said n-type, said second impurity region being formed in the surface of said semiconductor layer above said interface between said first impurity region and said buried impurity region, said third impurity region being formed in the surface of said semiconductor layer apart from and between said second impurity region and said semiconductor element, wherein a potential applied to said semiconductor substrate and said first impurity region is lower than that applied to said second impurity region and said third impurity region.