Patent ID: 6337521
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A semiconductor device, comprising:first and second semiconductor chips laminated so as to oppose backs thereof to each other; fixed potential leads placed in the vicinity of sides of said first and second semiconductor chips; a plurality of signal leads; a plurality of bonding pads formed over a main surface of said first semiconductor chip; a plurality of bonding pads formed over a main surface of said second semiconductor chip; and a plurality of wires; and wherein one surfaces of said plurality of signal leads and said fixed potential lead, and said plurality of bonding pads formed over the main surface of said first semiconductor chip are respectively electrically connected to one another by said plurality of wires, the other surfaces of said plurality of signal leads and said fixed potential lead, and said plurality of bonding pads formed over the main surface of said second semiconductor chip are respectively electrically connected to one another by said plurality of wires, and said first and second semiconductor chips, said plurality of signal leads, said fixed potential leads, and said plurality of wires are sealed with a resin.