Patent ID: 6388929
Filing Date: 2002-05-14
Classification: G11C

Abstract:
A semiconductor memory device for inputting/outputting data in accordance with an input address, comprising:a memory cell array for storing said data by a plurality of regular memory cells and spare memory cells; a self test circuit for conducting an operation test on said memory cell array to detect a defective memory cell, said self test circuit including a self test control unit for activating said operation test at predetermined time, and a redundancy repair analyzing unit for analyzing data outputted from said memory cell array in said operation test and outputting a plurality of redundancy code signals for indicating a defect address corresponding to said defective memory cell; and a decoding circuit for selecting a memory cell as a target of data input and output in accordance with said input address, said decoding circuit including a repair determining circuit for instructing an access to said spare memory cell when said input address and said defect address coincide with each other, said repair determining circuit having a plurality of redundancy code holding circuits provided in correspondence with said plurality of redundancy code signals, and each of said plurality of redundancy code holding circuits taking in a signal level of a corresponding one of said plurality of redundancy code signals outputted from said redundancy repair analyzing unit in said operation test and holding the taken signal level.