Patent ID: 6930008
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A method of fabricating a complementary bipolar junction transistor, comprising: respectively forming an N-type buried layer and a P-type buried layer on an NPN bipolar junction transistor region and a PNP bipolar junction transistor region of a silicon substrate; forming an N-type epitaxial layer on an entire surface of the silicon substrate having the N-type buried layer and the P-type buried layer; forming a P-type collector region in the N-type epitaxial layer of the PNP bipolar junction transistor region; forming an N-type collector region, which is electrically connected to the N-type buried layer, on the N-type epitaxial layer of the NPN bipolar junction transistor region; defining an active region by forming field regions of the N-type epitaxial layer, the N-type collector region and the P-type collector region; respectively forming a P-type base region and an N-type base region on the active regions of the PNP bipolar junction transistor region and the NPN bipolar junction transistor region; forming a first polycrystalline silicon layer pattern having contact holes that partially expose surfaces of the P-type base region and the N-type base region; forming a second polycrystalline silicon layer on an entire surface of the silicon substrate having the first polycrystalline silicon layer pattern, the second polycrystalline silicon layer filling the contact holes; respectively forming an N-type emitter region and a P-type emitter region within the P-type base region and the N-type base region by implanting and diffusing an N-type impurity and a P-type impurity respectively into the second polycrystalline silicon layer of the NPN bipolar junction transistor region and the PNP bipolar junction transistor region; and simultaneously forming an N-type emitter electrode and a P-type emitter electrode by patterning the second polycrystalline silicon layer and the first polycrystalline silicon layer.