Patent ID: 9059159
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A semiconductor die comprising: i) an integrated circuit formed on one surface of a piece of semiconductor wafer; ii) a plurality of input-output (I/O) pads interconnected to said integrated circuit; iii) a routing layer comprising: a dielectric layer formed on said one surface; and a plurality of conductive traces extending from respective ones of said I/O pads; iv) a plurality of under-bump metallizations (UBMs), each comprising a top surface for attaching a respective one of a plurality of solder bumps; and a bottom contact surface smaller than said top surface, in electrical contact with a respective one of said plurality of conductive traces; wherein said routing layer comprises one or more stress-buffering areas, each circumscribing a UBM and larger than a bump pad in contact with said UBM and containing at least one conductive trace passing under said UBM without electrically contacting said UBM, wherein at least one of said one or more stress-buffering areas is between 30% and 100% occupied by said conductive traces.