Patent ID: 6370668
Filing Date: 2002-04-09
Classification: G06F,G11C

Abstract:
A memory system capable of selectively operating in chip-kill mode and non-chip-kill mode, comprising:a memory controller, a plurality of memory devices, a channel including a data bus connecting the memory controller and the plurality of memory devices; the memory system comprising circuitry to determine whether the memory system is operating in non-chip-kill mode or in chip-kill mode; the memory controller comprising circuitry to generate a Read command to the plurality of memory devices via the channel; in response to the Read command, upon a determination that the memory system is operating in non-chip-kill mode, at least one of the plurality of memory devices returns a first data block to the memory controller via the data bus during a first time period; and, in response to the Read command, upon a determination that the memory system is operating in chip-kill mode, each one of the plurality of memory devices returns a second data block, smaller than the first data block, to the memory controller via the data bus during a second time period within the first time period.