Patent ID: 6426259
Filing Date: 2002-07-30
Classification: H01L

Abstract:
A method for fabricating a vertical field effect transistor on a semiconductor substrate, the method including the steps of:A. depositing a first layer of dielectric material on said semiconductor substrate; B. depositing a layer of metal on said first layer of dielectric material; C. depositing a second layer of dielectric material on said layer of metal; D. etching a channel opening through said second layer of dielectric material, said layer of metal, and said first layer of dielectric material; E. implanting a source and drain dopant through said channel opening and into said semiconductor substrate to form a drain region of said vertical field effect transistor in said semiconductor substrate; F. forming a metal oxide at any exposed surface of said layer of metal on sidewalls of said channel opening in a thermal oxidation process, wherein said metal oxide is a gate dielectric of said vertical field effect transistor; G. filling said opening with a semiconductor material by epitaxially growing said semiconductor material from said semiconductor substrate at a bottom wall of said channel opening; H. growing a semiconductor structure from said semiconductor material filling said channel opening, wherein said semiconductor structure extends above said channel opening; I. implanting said source and drain dopant into said semiconductor structure to form a source region of said vertical field effect transistor; and wherein said drain region doped with said source and drain dopant does not extend substantially into said channel opening before performance of a thermal anneal, and wherein said source region doped with said source and drain dopant does not extend substantially into said channel opening before performance of a thermal anneal; J. performing a thermal anneal such that said drain region doped with said source and drain dopant extends into said channel opening to be between said metal oxide at said sidewalls of said channel opening after said thermal anneal and such that said source region doped with said source and drain dopant extends into said channel opening to be between said metal oxide at said sidewalls of said channel opening after said thermal anneal, wherein a portion of said semiconductor material in said channel opening remains undoped without said source and drain dopant between said drain region and said source region to form a channel region of said vertical field effect transistor.