Patent ID: 7593253
Filing Date: 2009-09-22
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of word lines; a plurality of bit lines which are wired in a direction of intersecting with the word lines; and a plurality of memory cells which are arranged at predetermined cross points of the word lines and the bit lines, wherein the plurality of memory cells include a tunnel magneto-resistance element in which a fixed layer, a tunnel film and a free layer are laminated, and a P-type MISFET is connected to the tunnel magneto-resistance element, wherein the fixed layer is arranged adjacent to the tunnel film and a spin direction of electron is fixed to a predetermined direction, wherein the free layer is located adjacent to a surface opposite to a surface adjacent to the fixed layer of the tunnel film and a spin direction of electron is set to either parallel or anti-parallel state with respect to the fixed layer, wherein a gate of the P-type MISFET is connected to the word lines, wherein a drain of the P-type MISFET is connected to a side of the fixed layer of the tunnel magneto-resistance element, and wherein information stored in each of the plurality of memory cells is written by causing a current to flow through the tunnel magneto-resistance element included in each of the plurality of memory cells.