Patent ID: 6026032
Filing Date: 2000-02-15
Classification: G06F,G11C

Abstract:
A high speed data buffer for connecting a data source to a data receiver, the data buffer comprising:a first interface receiving data from the data source;a second interface outputting the data to the data receiver;a dual port random access memory having a first port with first address and first data lines communicating with the first interface, and having a second port with second address and second data lines communicating with the second interface;first address counter circuitry communicating with the first address lines to accept a first starting address and to increment the first starting address applied to the first address lines as data is received from the first interface; andsecond address counter circuitry communicating with the second address lines to accept a second starting address and to increment the second starting address applied to the second address lines as data is transmitted to the second interface;whereby the data source and data receiver may transfer data either by random access of the dual port random access memory with independent control of the address lines or by sequential access of the dual port random access memory with the first and second address counter circuitry controlling the address lines;in which a portion of the dual port random access memory is partitioned as a circular buffer having memory addresses connected in segments with each segment of memory addresses associated with a control block including a valid flag; andincluding in addition address management circuitry operating:(i) upon receipt of new data from the first interface to review control blocks to find a next control block with a enabled valid flag(ii) load the address of the segment associated with the next control block into the first address counter;(iii) upon loading the segment associated with the next control block with data from the first interface, disabling the valid flag in the next control block.