Patent ID: 6105157
Filing Date: 2000-08-15
Classification: G01R

Abstract:
For an integrated circuit tester producing output TEST signals, each following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay T.sub.D and an adjustable drive delay T.sub.TAD, and for sampling input RESPONSE signals following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay T.sub.C and an adjustable compare delay T.sub.TAC, the tester including transmission lines having remote ends for contacting terminals of an integrated circuit device of the transmission lines conveying said TEST signals from the tester to said terminals and conveying said RESPONSE signals from said terminals to said tester, the transmission lines having inherent line delays T.sub.L, a method for measuring at least one of the inherent drive, compare and line delays comprising the steps of:(a) generating a standing wave signal crossing a reference voltage level concurrently at every point within a region of a conductive plane with a fixed delay T.sub.REF after each pulse of the CLOCK signal, and(b) contacting said region with said remote ends of said transmission lines so that said transmission lines convey said standing wave signal to the tester.