Patent ID: 6173366
Filing Date: 2001-01-09
Classification: G06F,H04N

Abstract:
A computer, comprising:an input/output device operably coupled to a microprocessor, wherein the microprocessor includes:an instruction cache configured to store coded first and second sets of instructions obtained from the input/output device, wherein said first set of instructions comprises integer instructions for operating on integer operands and said second set of instructions comprises vector instructions for operating on vector data;a decode unit configured to decode said vector instructions; andwherein said microprocessor is configured to perform a load of data having a first bit size from a first memory location having said first bit size to a register slot having a second bit size, wherein said first bit size is smaller than said second bit size, and wherein said microprocessor is configured to perform an unpacking operation during the load to fill said register slot, wherein said microprocessor is configured to load said data and perform said unpacking operation in response to said decode unit decoding a single vector load instruction.