Patent ID: 6133098
Filing Date: 2000-10-17
Classification: G11C,H01L

Abstract:
A method for fabricating a flash memory device comprising:forming a gate silicon oxide layer on the surface of a semiconductor substrate;depositing a first polysilicon layer overlying said gate silicon oxide layer;depositing a first nitride layer overlying said first polysilicon layer;patterning said first polysilicon layer and said first nitride layer to form word gates wherein a gap is left between two of said word gates;forming a first insulating layer on the sidewalls of said word gates;depositing a second polysilicon layer overlying said word gates and said gate silicon oxide layer;anisotropically etching away said second polysilicon layer to leave disposable polysilicon spacers on the sidewalls of said word gates;implanting ions into said semiconductor substrate to form a lightly doped region wherein said disposable polysilicon spacers act as an implantation mask;thereafter removing said disposable polysilicon spacers;depositing a third polysilicon layer overlying said word gates and said gate silicon oxide layer;anisotropically etching away said third polysilicon layer to leave polysilicon spacers on the sidewalls of said word gates wherein said polysilicon spacers form sidewall floating gates;forming a second insulating layer on said sidewall floating gates;implanting ions into said semiconductor substrate to form a bit diffusion region wherein said floating gates act as an implantation mask;coating a gap filling material over the surface of said substrate wherein said gap-filling material fills said gap between said two of said word gates;planarizing said gap-filling material;patterning said word gates and said floating gates to form a slit cut in the direction of a bit line and a gap wherein said gap-filling material protects said bit diffusion region from overetching;thereafter removing said gap-filling material;forming a third insulating layer on said slit cut sidewalls of said word gates and said floating gates;filling said gap created by said patterning with an oxide layer;depositing a fourth polysilicon layer overlying said substrate and filling said gap between said word gates;polishing said fourth polysilicon layer to said nitride layer and overetching said fourth polysilicon layer;thereafter oxidizing said fourth polysilicon layer wherein said fourth polysilicon layer forms a control gate;thereafter removing said nitride layer; anddepositing a fifth polysilicon layer overlying said substrate wherein said fifth polysilicon layer forms a word line connecting said word gates to complete said fabrication of said flash memory device.