Patent ID: 9165944
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a plurality of gate stacks on a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer; implanting a first dopant at the active semiconductor layer to form an extension implant extending between a first gate stack and a second gate among the plurality of gate stacks; applying a spike anneal after the extension implant; etching the region of the active semiconductor layer to form a trench that extends through the extension implant and exposes trench surfaces of the active semiconductor layer, the trench surfaces including an exposed planar region and opposing sidewalls extending from a respective portion of the extension implant and the exposed planar region; implanting a second dopant at the trench surfaces to form a conformal halo implant that completely surrounds the trench and conforms entirely to each sidewall such that a portion of the conformal halo at each sidewall contacts a respective extension implant; applying a furnace anneal different from the spike anneal to activate and diffuse the conformal halo implant; implanting a third dopant at the exposed planar region through a portion of the halo implant and that extends through a bottom portion of the conformal halo implant and reaches the dielectric layer to form a butting implant that extends between the trench and the dielectric layer; and growing an epitaxial layer at the exposed planar region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.