Patent ID: 8819331
Filing Date: 2014-08-26
Classification: G06F,H03M

Abstract:
1. A memory system that identifies a type of memory controller, comprising: a memory device including a plurality of memory cells operative to store storage data, said storage data containing input data from external to which parity information is added; and a memory controller operative to convert between said input data and output data that is to be said storage data, wherein when two of said input data that are complementarily related are defined as an input data pair, and an exclusive-or of two of said output data that are generated by inputting to said memory controller said two of input data configuring said input data pair is defined as a computed result, said computed result including at least 1 bit of ‘0’ data, and when a plurality of said computed results generated from a differing plurality of said input data pairs are compared on a bit by bit basis, the number of bits in which both ‘0’ data and ‘1’ data appear being greater than one third of a length of said output data, and the memory system determining said type of memory controller based on said computed result and said comparison of said plurality of said computed results.