Patent ID: 6091645
Filing Date: 2000-07-18
Classification: G06F,G11C,H03K

Abstract:
A programmable intercoupling circuit of a programmable memory array having a primary I/O bus and a secondary I/O bus, said programmable intercoupling circuit comprising:a first selective coupler having an output and a plurality of inputs, inputs of said plurality of inputs being coupled to select primary interconnects of said primary I/O bus interconnects, said first selective coupler being programmable for selectively propagating a signal between said output and one input of said plurality of inputs in accordance with a first select signal; anda second selective coupler having an input electrically coupled for receiving a signal associated with the output of said first selective coupler, and a plurality of outputs, outputs of said plurality of outputs being coupled to select secondary interconnects of said secondary I/O bus, said second selective coupler being programmable for selectively propagating a signal between said input and a selectable one output of said plurality of outputs in accordance with a second select signal.