Patent ID: 8497585
Filing Date: 2013-07-30
Classification: H01L

Abstract:
1. A chip package, comprising: a first patterned conductive layer, defining a first space having a pattern complementary to a pattern of the first patterned conductive layer; a second patterned conductive layer, defining a second space having a pattern complementary to a pattern of the second patterned conductive layer, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space; a chip, disposed on the second patterned conductive layer, wherein the second patterned conductive layer is located between the chip and the first patterned conductive layer; a plurality of bonding wires, connected between the chip and the second patterned conductive layer; a molding compound, encapsulating the second patterned conductive layer, the chip and the bonding wires; a second oxidation prevention layer, disposed on the second patterned conductive layer, wherein the second patterned conductive layer is located between the second oxidation prevention layer and the first patterned conductive layer; and a dielectric layer, filled in the first space and overlapping the second space and the part of the second patterned conductive layer surrounding the second space.