Patent ID: 6785804
Filing Date: 2004-08-31
Classification: G06F

Abstract:
A processor comprising,an issue queue configured to store a plurality of instructions and a plurality of tags, each of the plurality of tags corresponding to a respective one of the plurality of instructions, wherein a first instruction of the plurality of instructions is in a branch delay slot of a branch instruction, and wherein a first tag of the plurality of tags corresponding to the first instruction is equal to a second tag corresponding to the branch instruction if the branch delay slot is unconditional, and wherein the first tag is not equal to the second tag if the branch delay slot is conditional; an issue logic coupled to the issue queue, wherein the issue logic is configured to select the first instruction for issue responsive to predetermined issue criteria, and wherein the issue queue is configured to issue the first instruction and the first tag responsive to the issue logic selecting the first instruction for issue; and an execution unit coupled to receive the first instruction and the first tag issued from the issue queue, wherein the execution unit is configured to execute the first instruction in one or more pipeline stages, and wherein the execution unit is further coupled to receive the second tag responsive to a misprediction of the branch instruction, and wherein the execution unit is configured to compare the second tag to tags of instructions in the one or more pipeline stages, and wherein, if a mismatch is detected in the comparison, the execution unit is configured to cancel the corresponding instruction and wherein, if a match is detected in the comparison, the execution unit does not cancel the corresponding instruction, whereby the first instruction is canceled if the branch delay slot is conditional and the first instruction is not canceled if the branch delay slot is unconditional.