Patent ID: 8793628
Filing Date: 2014-07-29
Classification: G06F

Abstract:
1. A method of maintaining coherency in a memory subsystem of an electronic system having hardware and software components modeled in a first design abstraction in a software simulator and a second design abstraction in a hardware emulator in electrical communication with the software simulator during functional verification of the electronic system, wherein a portion of the memory subsystem has a plurality of memory pages modeled in the software simulator using the first design abstraction, wherein a first flag is associated with each memory page of the plurality of memory pages, wherein a shadow memory page is modeled in the hardware emulator using the second design abstraction to store a copy of a contents of a memory page of the plurality of memory pages, and wherein a second flag is associated with the shadow memory page and is to be set to indicate that the memory page is more recently updated than the shadow memory page, comprising: updating the memory page modeled in the first design abstraction in the software simulator by writing data to at least a portion of the memory page; setting the first flag associated with the memory page to indicate that the memory page in the software simulator is more recently updated than the shadow memory page in the hardware emulator; setting the second flag associated with the shadow memory page to indicate that the memory page is more recently updated than the shadow memory page; receiving a request to access the shadow memory page from a portion of the circuit design programmed into the hardware emulator; checking whether the second flag is set after a request to access the shadow memory page is received; writing the contents of the memory page in the software simulator to the shadow memory page in the hardware emulator prior to granting the request to access the shadow memory page; and clearing the first flag and the second flag.