Patent ID: 6307398
Filing Date: 2001-10-23
Classification: H03K

Abstract:
An integrated circuit memory device comprising:a voltage supply connection to receive a first voltage (Vcc);a voltage pump circuit to provide a second voltage (Vbb) on a Vbb node, the second voltage is a negative voltage; anda voltage level translator circuit comprising:an input node;a first P-channel transistor having a source node coupled to the voltage supply connection, a drain node, and a gate node coupled to the input node;a second P-channel transistor having a source node coupled to the voltage supply connection, a drain node, and a gate node coupled to the input node via an inverter circuit;a first N-channel transistor having a source node coupled to the Vbb node, a drain node coupled to the drain node of the first P-channel transistor, and a gate node coupled to the drain node of the second P-channel transistor;a second N-channel transistor having a source node coupled to the Vbb node, a drain node coupled to the drain node of the second P-channel transistor, and a gate node coupled to the drain node of the first P-channel transistor;a third N-channel transistor having a source node coupled to the Vbb node, a drain node, and a gate node coupled to the drain node of the first P-channel transistor; anda fourth N-channel transistor having a source node coupled to the drain node of the third N-channel transistor, a drain node coupled to a ground node, and a gate node coupled to the drain node of the second P-channel transistor.