Patent ID: 7992062
Filing Date: 2011-08-02
Classification: G01R

Abstract:
1. A device comprising: a data input; a scan test input; a clock demultiplexer responsive to a clock input to selectively provide a first clock output and a second clock output, wherein the clock demultiplexer comprises a first logic gate and a second logic gate, and wherein when a mode selection signal is at a logic low level, the first logic gate provides a logical zero output and the second logic gate provides a clock signal that is inverted relative to the clock input; a master latch coupled to the data input and to the scan test input, the master latch including a pair of cross-coupled inverters and a master latch output, the master latch responsive to the first clock output to couple the data input to the master latch output and responsive to the second clock output to couple the scan test input to the master latch output, wherein a first input of a first inverter of the pair of cross-coupled inverters is coupled to the data input and wherein a second input of a second inverter of the pair of cross-coupled inverters is coupled to the scan test input; and a slave latch responsive to the clock input and independent of the first clock output and the second clock output, wherein the slave latch is responsive to the master latch output.