Patent ID: 7366878
Filing Date: 2008-04-29
Classification: G06F

Abstract:
1. A multi-threaded processor, comprising: a plurality of different types of execution units, at least one of each type of execution unit servicing a different class of operations; an instruction buffer buffering a set of current instructions for a plurality of asynchronous threads, each current instruction requiring an operation performed by one of each of said plurality of different types of execution units; a compiler dividing the set of current instructions into phases of executable instructions, each phase having one or more math operations and one or more texture cache access operations; and an instruction scheduler, said instruction scheduler comprising a qualification module configured to qualify said one or more math operations and said one or more texture cache access operations in a current phase for execution based on a qualification rule to produce a set of qualified instructions and a prioritization module configured to prioritize said set of qualified instructions based on a prioritization rule to produce prioritized instructions for issue from said instruction buffer to said plurality of different types of execution units, wherein said instruction scheduler continues to qualify said one or more math operations and said one or more texture cache access operations in said current phase until a boundary between said current phase and a subsequent phase is reached, at which point, no texture cache access operation in said subsequent phase is qualified until all of said one or more texture cache access operations in said current phase have completed.