Patent ID: 6765820
Filing Date: 2004-07-20
Classification: G11C

Abstract:
A memory cell, comprising:a first multi-resistive state bit having a first end and a second end; a first bit line connected to the first end of the first multi-resistive-state bit; a first switch coupled to the second end of the first multi-resistive-state bit which selectively provides a path for a first sense current to flow from the first bit line, through at least part of the first multi-resistive-state bit, and to a first predetermined voltage terminal that is coupled to ground; a second multi-resistive-state bit having a first end and a second end; a second bit line connected to the first end of the second multi-resistive-state bit; and a second switch coupled to the second end of the second multi-resistive-state bit which selectively provides a path for a second sense current to flow from the second bit line, through at least part of the second multi-resistive-state bit, and to a second predetermined voltage terminal.