Patent ID: 7380181
Filing Date: 2008-05-27
Classification: G01R

Abstract:
1. A test wrapper architecture for testing an electronic circuit having one or more hierarchical cores, the test wrapper architecture comprising: a first core having a wrapper input cell and a wrapper output cell, the wrapper input cell and wrapper output cell being configured to receive a primary input signal and a test input signal for the first core, and to output a primary output signal and a test output signal for the first core; a second core having a wrapper input cell and a wrapper output cell, the wrapper input cell and wrapper output cell being configured to receive a primary input signal and a test input signal for the second core, and to output a primary output signal and a test output signal for the second core; wherein the wrapper input cell and the wrapper output cell of the second core are further adapted to receive a test input signal from the first core, and to output a test output signal to the first core, thereby enabling the first core and the second core to be tested in parallel.