Patent ID: 6114209
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method of forming semiconductor circuits having raised doping region comprising the steps of:(a) obtaining a semiconductor substrate having at least one stacked gate structure, a pair of source/drain regions, and a plurality of dielectric side-wall spacers separating said source/drain regions respectively from said gate structure, said side-wall spacers having a predetermined height;(b) depositing a buffer conductive layer above said substrate, said buffer conductive layer being a continuous polysilicon layer in contact with both said source/drain regions and having a raised structure generally conforming to said stacked gate structure;(c) depositing a first dielectric layer on said buffer conductive layer, said first dielectric layer being an oxide layer and having a profile generally conforming to said buffer conductive layer;(d) removing portions of said first dielectric layer and said buffer conductive layer above said stacked gate structure using an oxide chemical-mechanical polishing (CMP) process and a polysilicon CMP process, respectively, to cause said buffer conductive layer to be separated into two regions, each region containing an exposed portion adjacent to said spacers and a covered portion under said first dielectric layer connecting to either said source or drain, respectively; and(e) applying an etching process using said first dielectric layer as mask to remove an upper part of said exposed portions of said buffer conductive layer to cause the height of said side-wall spacers to be higher relative to said buffer conductive layer, whereby said relatively higher height of said side-wall spacers prevent electrons from jumping over said spacers.