Patent ID: 6039851
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A process for fabrication of a semiconductor device, comprising the steps of:providing a semiconductor wafer having a topology formed thereon, said topology having a plurality of recesses;forming an insulating layer over said topology, said insulting layer extending into said recesses and forming bread-loafed openings in said insulating layer formed by converging surfaces of said insulting layer;removing a portion of said converging surfaces to remove at least a portion of a bread-loaf buildup of insulating material about said bread-loafed openings, said step of removing comprises an etch step using a gas combination of an inert gas and a chemically reactive gas that prevents dislodged insulating layer particles from re-sputtering into said gaps; andafter said step of removing, forming a fill layer over said insulating layer to at least partially planarize said semiconductor wafer.