Patent ID: 8350603
Filing Date: 2013-01-08
Classification: H03K

Abstract:
1. A circuit comprising: a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate; a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate; a first second PMOS transistor having a first second PMOS drain, a first second PMOS source, and a first second PMOS gate; a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate; a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate; a second second PMOS transistor having a second second PMOS drain, a second second PMOS source, and a second second PMOS gate; and an inverter having an inverter input and an inverter output; wherein