Patent ID: 7008830
Filing Date: 2006-03-07
Classification: H01L

Abstract:
1. A poly-crystalline thin film transistor fabricating method comprising: forming a poly-crystalline semiconductor layer on a buffer layer on a substrate; forming a gate insulation layer over the poly-crystalline semiconductor, wherein the gate insulation layer is formed with a first thickness at a channel position and at source and drain positions, wherein the gate insulation layer is formed with a second thickness at offset positions, and wherein the thickness of the gate insulation layer tapers in sequential doping positions from the second thickness to the first thickness; forming a gate structure on the gate insulation layer, wherein the gate structure includes a main gate electrode over the channel position and auxiliary gate electrodes over the offset positions; impurity doping the semiconductor layer through exposed portions of the gate insulation layer while using the gate structure as a mask to define sequential doping regions that are aligned with the sequential doping positions, and source and drain regions that are aligned with the source and drain positions.