Patent ID: 6373777
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A semiconductor memory, comprising:a first memory cell region including a plurality of first memory cells; a second memory cell region including a plurality of second memory cells; a first data transfer line; a second data transfer line; a third data transfer line; a set of first sense amplifier circuits coupled to said first data transfer line and provided for a part of said first memory cells; a set of second sense amplifier circuits coupled to said second data transfer line and provided for another part of said first memory cells and part of said second memory cells; a set of third sense amplifier circuits coupled to said third data transfer line and provided for another part of said second memory cells; a first switch circuit coupled between said first and second data transfer lines that electrically connects the first and second data transfer lines when turned on; and a second switch circuit coupled between said second and third data transfer lines that electrically connects the second and third data transfer lines when turned on.