Patent ID: 7394238
Filing Date: 2008-07-01
Classification: G01R,H03K,H03L

Abstract:
1. A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time, comprising: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal, wherein said multiplier comprises: a pulse width extension circuit operable to output logical sum of the delay reference signal and a signal, which is the delay reference signal delayed for a delay time shorter than a pulse width of the delay reference signal, as a pulse width extension signal; and a multiplication circuit operable to output logical product of the pulse width extension signal and a signal, which is an inversion of the pulse width extension signal delayed for a predetermined delay time, as the high frequency signal.