Patent ID: 7732930
Filing Date: 2010-06-08
Classification: H01L,Y10T

Abstract:
1. A semiconductor device, comprising: a circuit substrate including at least n (n is an integer of two or greater) number of terminals; a semiconductor chip provided on the circuit substrate and including at least n number of terminals; and a relay chip including a triangular substrate having a first side, a second side and a third side, the third side being the longest side of the triangular substrate, at least n number of first terminals located along the first side, at least n number of second terminals located along the second side, and a plurality of wires located horizontally parallel to the third side and connecting the first terminals and the second terminals respectively; a first wire connecting each of the at least n number of terminals of the circuit substrate to a corresponding first terminal among the at least n number of first terminals; and a second wire connecting each of the at least n number of terminals of the semiconductor chip to a corresponding second terminal among the at least n number of second terminals, wherein the plurality of wires connecting the first terminals and the second terminals each include a first part drawn from each of the plurality of the first terminals inwardly so as to be horizontally parallel to, or to form an acute angle with, the second side, a second part drawn from each of the second terminals inwardly so as to be horizontally parallel to, or to form an acute angle with, the first side, and a third part connecting the first part and the second part to each other in a straight manner; and the plurality of wires are formed horizontally such that a wiring width of each wire, a wiring interval between each wire and a wire adjacent and outer thereto, and a wiring pitch which is a sum of each wiring width and a corresponding wiring interval are set so as to minimize a difference between wiring capacitances of each adjacent wires among the plurality of wires.