Patent ID: 6878603
Filing Date: 2005-04-12
Classification: H01L

Abstract:
1. A process for manufacturing a DMOS transistor ( 100 ) with a semiconductor body ( 5 ), which features a surface layer with a source region ( 10 ) and a drain region ( 80 ) of a second conductivity type, and a first well region ( 20 ) of a first conductivity type directly adjoining and enclosing the source region ( 10 ), wherein a gate region ( 35 ) is formed on the surface of the surface layer of the semiconductor body ( 5 ), which gate region extends from the source region across at least part of the well region ( 20 ), said method comprising: starting on the surface of the semiconductor body ( producing a doping of the second conductivity type with a first concentration value in the floor region of the trench-shaped structure; producing a doping of the second conductivity type with a second concentration value in the source-end side wall of the trench-shaped structure; and producing a doping of the second conductivity type with a third concentration value in the drain-end side wall of the trench-shaped structure; wherein at least one of said concentration values is different from the others of said concentration values.