Patent ID: 6384630
Filing Date: 2002-05-07
Classification: G06F,H03K

Abstract:
An apparatus to program a plurality of programmable logic devices (PLDS) located on respective integrated circuits, comprising:a source configured to generate programming data, said source being external to said integrated circuits; a second source to generate a clock signal, said second source being external to said integrated circuits; a first PLD device configured to receive said programming data and said clock signal, said first PLD device further configured to use said clock signal to clock said programming data to program said first PLD device to a first logic state, said first PLD device further including a done circuit which is configured to generate a done signal when said first PLD device is programmed to said first logic state; and a second PLD device configured to receive said done signal, and in response thereto, is further configured to receive said clock signal and said programming data to program said second PLD device to a second logic state.