Patent ID: 6117777
Filing Date: 2000-09-12
Classification: B24B,H01L

Abstract:
A method for fabricating a microelectronics fabrication comprising:providing a substrate employed within a microelectronics fabrication;forming over the substrate a planarizable layer, the planarizable layer having a lower residual portion of the planarizable layer closer to the substrate and an upper removable portion of the planarizable layer further spaced from the substrate, where one of the lower residual portion of the planarizable layer and the upper removable portion of the planarizable layer has a colorant incorporated therein, the colorant being positioned at a location which assists in monitoring and controlling an endpoint of a chemical mechanical polish (CMP) planarizing method employed in planarizing the planarizable layer; andplanarizing through the chemical mechanical polish (CMP) planarizing method the planarizable layer while employing the colorant concentration to monitor and control the endpoint of the chemical mechanical polish (CMP) planarizing method.