Patent ID: 8963281
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A process comprising: patterning a portion of a dual oxide-nitride hardmask to define an isolation trench pattern and a handle wafer contact trench pattern over a silicon-on-insulator semiconductor substrate; etching the patterned portion of the dual oxide-nitride hardmask; simultaneously etching silicon below the patterned portion of the dual oxide-nitride hardmask to form an isolation trench and an handle wafer contact trench in the silicon-on-insulator semiconductor substrate, the substrate including a buried insulating layer and a portion of a handle wafer bonded to a bottom surface of the substrate, the substrate further including a nitride layer disposed on a top surface of the substrate, the isolation trench having a first width and the handle wafer contact trench having a second width, the second width being approximately three times greater than the first width and the buried insulating layer defining a trench bottom of the handle wafer contact trench, the isolation trench extending through a silicon-on-insulator layer, the silicon-on-insulator layer disposed directly over a buried oxide layer; depositing an oxide insulating layer in the isolation trench and the handle wafer contact trench, the oxide insulating layer covering a sidewall of the handle wafer contact trench and the trench bottom of the handle wafer contact trench, the oxide insulating layer filling the isolation trench; etching the oxide insulating layer covering the sidewall of the handle wafer contact trench such that the sidewall defines a tapered portion and an untapered portion and the trench bottom of the handle wafer contact trench so that the oxide insulating layer covering the trench bottom is removed; etching the buried insulating layer so that a top surface of the portion of the handle wafer is exposed; filling the handle wafer contact trench with an electrically conductive material; and covering a top of the electrically conductive material with an insulating material, wherein simultaneously forming the isolation trench and the handle wafer contact trench causes formation of three active silicon regions, wherein a first active silicon region of the three active silicon regions comprises a first dopant type and a second active silicon region and a third silicon region of the three active silicon regions comprise a second dopant type, the first dopant type different from the second dopant type.