Patent ID: 9209317
Filing Date: 2015-12-08
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory device comprising: a substrate having a first charge trap region, a second charge trap region, and a selection region between the first and second charge trap regions; a first impurity junction region in a portion of the substrate of the first charge trap region; a second impurity junction region in a portion of the substrate of the second charge trap region; a first insulation layer pattern on the substrate having the first charge trap region, the second charge trap region and the selection region; a gate conductive layer pattern on the first insulation layer pattern in the selection region; a second insulation layer pattern covering the gate conductive layer pattern in the selection region and extending onto the first insulation layer pattern in the first and second charge trap regions; and a charge trap layer pattern, a third insulation layer pattern and a control gate sequentially stacked on the second insulation layer pattern.