Patent ID: 8423935
Filing Date: 2013-04-16
Classification: G06F

Abstract:
1. A method for verifying a functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating, where the design comprises a first plurality of internal state elements and the clock-gated design comprises a second plurality of internal state elements, the method comprising: selecting a first one of the first plurality of internal state elements and a corresponding first one of the second plurality of internal state elements, wherein an input to the first one of the first plurality of internal state elements of the design of the integrated circuit serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements of the corresponding clock-gated design serves as a second comparison point, and the design of the integrated circuit is to be compared against the clock-gated design at the first comparison point and the second comparison point for verifying the functional equivalency between the design of the integrated circuit and the corresponding clock-gated design; and generating, using a processor, a test bench that identifies the input to the first one of the first plurality of internal state elements and the input to the corresponding first one of the second plurality of internal state elements as a set of comparison points.