Patent ID: 7498254
Filing Date: 2009-03-03
Classification: H01L

Abstract:
1. A method of forming an interconnect structure comprising: forming at least one opening in a dielectric material, said forming said at least one opening comprises lithography and etching one of a line opening, a via opening and a line opening or a combination of said openings; forming a first Ru-containing plating seed region at least on exposed wall portions of said dielectric material within said at least one opening; forming an oxygen/nitrogen transition region on said first Ru-containing plating seed region, said oxygen/nitrogen transition region is formed by switching a precursor used in forming said first Ru-containing plating seed region to have a higher combined oxygen and nitrogen content than said first Ru-containing plating seed region; forming a second Ru-containing plating seed region on said oxygen/nitrogen transition region, wherein said first Ru-containing plating seed region, said oxygen/nitrogen transition region, and said second Ru-containing plating seed region define a single Ru-containing plating seed layer having baffler enhancement; forming a Cu interconnect metal within said at least one opening on said single Ru-containing plating seed layer; and planarizing said Cu interconnect metal and said single Ru-containing plating seed layer to provide a structure having upper surfaces of said Cu interconnect metal and said single Ru-containing plating seed layer that are substantially coplanar with an upper surface of the dielectric material.