Patent ID: 7829952
Filing Date: 2010-11-09
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a first MISFET including having a first gate electrode formed over a main surface of a semiconductor substrate, and further including a first semiconductor region and a second semiconductor region formed in the semiconductor substrate; a first interlayer insulating film formed over the first MISFET and having an opening; a conductive film formed within the opening; a first vertical MISFET formed over the conductive films the first vertical MISFET including a source region and a drain region which are formed in a laminate, the laminate extending in a perpendicular direction from the main surface such that the source region and the drain region are perpendicularly laminated, the laminate electrically connected to the first semiconductor region through the conductive film and disposed over the first semiconductor region such that the laminate overlaps, in a plane view, with the first semiconductor region, the first vertical MISFET further including a gate electrode formed via a gate insulating film on a side wall of the laminate; and a word line formed over first interlayer insulating film and electrically connected to the gate electrode of the first vertical MISFET.