Patent ID: 9118451
Filing Date: 2015-08-25
Classification: H04L

Abstract:
1. A receiver circuit comprising: an analog to digital converter (ADC) configured to convert an input data signal into sample data in accordance with a clock; a boundary phase computation circuit configured to determine a boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to: compute an amplitude of an eye pattern of the input data signal, based on the sample data, the boundary phase, and a phase offset from a first memory; determine a maximum amplitude phase of the eye pattern by computing the amplitude of the eye pattern of the input data signal, while obtaining different phase offsets from the first memory; and estimate, as the maximum amplitude phase, a first amplitude phase that exists in a proximity of a phase intermediate between adjacent boundary phases, compute a first amplitude corresponding to the first amplitude phase, a second amplitude corresponding to a second amplitude phase preceding the first amplitude phase, and a third amplitude corresponding to a third amplitude phase succeeding the first amplitude phase, compare the first amplitude with both of the second amplitude and the third amplitude, and determine, as the maximum amplitude phase, the first amplitude phase when the first amplitude is larger than both of the second amplitude and the third amplitude; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.