Patent ID: 8156261
Filing Date: 2012-04-10
Classification: G06F

Abstract:
1. A direct memory access (DMA) system comprising: A first transfer controller in a DMA controller coupled to a first memory by a first DMA bus and to a system data bus (SDB), wherein said first transfer controller is configured to fetch a first transfer DMA instruction and a second transfer DMA instruction to operate the first transfer controller as an SDB master; and a second transfer controller in the DMA controller coupled to a second memory by a second DMA bus and to the SDB, wherein the second transfer controller is configured to fetch a third transfer DMA instruction to operate the second transfer controller as an SDB slave, wherein the SDB master is configured to push data read over the first DMA bus from the first memory over the SDB bus to the SDB slave in response to the first and second transfer DMA instructions and the SDB slave is configured to store the data over the second DMA bus in the second memory in response to the third transfer DMA instruction while the first transfer controller is pushing further data to the SDB slave.