Patent ID: 6272569
Filing Date: 2001-08-07
Classification: G06F,H04M,Y02D

Abstract:
A computer comprising:a host processor configured to execute signal processing code for processing at a first processing rate symbols including digital data indicative of a received analog signal;an analog interface for communicating data with an external communication unit and for converting analog data received from the external communication unit to digital data and converting digital data to analog data for communication with the external communication unit, the conversion being at a sampling rate;a digital signal processor coupled to the analog processor and to the host processor for processing said digital data representative of the analog signal at a second data rate, the second data rate being at a sampling rate of the analog interface, the first data rate being at a symbol rate of the data;a memory configured to be accessed by said host processor; andsaid digital signal processor further coupled to the memory and to the analog interface for processing said digital data and storing said processed data in the memory, and having an output for providing an interrupt to the host processor to communicate data between the memory and the host processor in response to said interrupt.