Patent ID: 8266405
Filing Date: 2012-09-11
Classification: B21C,G11C

Abstract:
1. A method for accessing a memory device that supports both synchronous and asynchronous modes of operation, and comprises a memory interface and a plurality of storage arrays, wherein at least one storage array of the plurality of storage arrays operates within a different clock domain than another storage array of the plurality of storage arrays, the method comprising: receiving an address of data to be accessed, and either a clock signal or an asynchronous control signal, the address being within the at least one storage array; latching the address when operating in the asynchronous mode, the address being latched responsive to the asynchronous control signal; registering the address when operating in the synchronous mode, the registered address to be supplied in synchronization with the clock signal; using an address multiplexer to selectively forward the latched address or the registered address, depending on the mode selected, to access the at least one storage array, access to the at least one storage array during the synchronous mode being controlled by a different clock signal than the clock signal supplied to the memory interface circuit; and generating a signal, which prevents a change that is made to the data while the data is being accessed from propagating out of the memory device while the data is being accessed.