Patent ID: 9224738
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method of forming an array of gated devices, comprising: forming trenches between walls that longitudinally extend in rows and project elevationally from a substrate, the walls comprising semiconductor material; forming gate dielectric within the trenches laterally over side surfaces of the walls and forming conductive gate material within the trenches laterally over side surfaces of the gate dielectric; laterally covering side surfaces of an elevationally inner portion of the gate material within the trenches with masking material and leaving side surfaces of an elevationally outer portion of the gate material within the trenches laterally uncovered by the masking material; and removing the elevationally outer portion of the gate material that is laterally uncovered by the masking material while the side surfaces of the elevationally inner portion of the gate material are laterally covered by the masking material to form gate lines within the trenches laterally over elevationally inner portions of the walls.