Patent ID: 8830720
Filing Date: 2014-09-09
Classification: G11C,H01L

Abstract:
1. A One-Time Programmable (OTP) memory, comprising: a plurality of OTP cells, at least one of the cells comprising: a diode including at least a first active region and a second active region isolated from the first active region, where the first active region having a first type of dopant and a second active region having a second type of dopant, the first active region providing a first terminal of the diode, the second active region providing a second terminal of the diode, both the first and second active regions residing in a common CMOS well or on an isolated substrate, the first active region coupled to the OTP element and the second active region coupled to a second supply voltage line, the first and second active regions being fabricated from sources or drains of CMOS devices; at least one MOS including at least a first active region and a second active region, the first active region and the second active region being separately coupled to the first terminal of the diode, the second terminal of the diode or a fixed supply voltage, and a gate coupled to a third supply voltage line, wherein the OTP element is configured to be programmable by applying voltages to the first and the second supply voltage lines to thereby change its logic state and can be read by applying voltages to the second and/or the third supply voltage lines to sense the resistance through the first supply voltage line.