Patent ID: 6353864
Filing Date: 2002-03-05
Classification: G06F

Abstract:
An integrated circuit device comprising:a buffer for temporarily storing transmitting data and received data; a undivided address setup unit for setting an address for said buffer when said buffer is not divided; a plurality of sub-buffer address setup units, provided for individual sub-buffers obtained by logically dividing said buffer, for setting addresses for said sub-buffers; a size setup unit for setting the sizes of said sub-buffers; and an address setup controller for setting address areas for said sub-buffers in said sub-buffer address setup units in accordance with the sizes of said sub-buffers which is set in said size setup unit, for validating said address in said undivided address setup unit when said buffer is not sub-divided, and for validating said addresses in said sub-buffer address setup unit when said buffer has been sub-divided, wherein said transmitting data and said received data are written in or read from said undivided buffer in accordance with said address in said undivided address setup unit, and said transmitting data and said received data are written in or read from said sub-buffers in accordance with said addresses from said corresponding sub-buffer address setup units.