Patent ID: 7659580
Filing Date: 2010-02-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a crystalline silicon layer on an insulating layer, the crystalline silicon layer including a channel formation region, an impurity region and a silicide layer adjacent to the impurity region; a gate insulating film over the channel formation region; a gate electrode over the channel formation region with the gate insulating film therebetween; and a wiring electrically connected to the impurity region via the silicide layer, wherein the silicide layer includes a first region in which a thickness increases from an edge of a surface of the silicide layer on a channel formation region side and a second region in which a thickness is more uniform than that of the first region, wherein, when the first region and the second region are separated by a first line which is perpendicular to a horizontal line and a point where the first line intersects with an interface between the silicide layer and the impurity region is assumed as a first point, a second line which passes through the first point and the edge forms an angle θ (0°<0<45°) with the horizontal line, and wherein the thickness of the second region to a thickness of the crystalline silicon layer is 0.6 or more in ratio.