Patent ID: 7515653
Filing Date: 2009-04-07
Classification: H04H,H04L

Abstract:
1. A digital broadcasting receiver, comprising: a digital demodulator configured to demodulate a digital broadcasting signal; a lock detector configured to detect a plurality of lock signals output from the digital demodulator along with demodulating operational steps of the digital demodulator; and a lock processor configured to control the demodulating operational steps of the digital demodulator according to the detected lock signals, wherein the plurality of lock signals include at least a NO SIGNAL signal indicating an input signal is present, an AGC LOCK signal indicating a gain control step has been completed, a TR LOCK signal indicating a timing error recovery step has been completed, a CR LOCK signal indicating a carrier signal recovery step has been completed, an SNR (signal-to-noise ratio) lock signal indicating that a measured SNR meets a predetermined SNR, and an FEC (forward error correction) LOCK signal indicating an error correction step has been completed, wherein the lock processor is further configured to examine each of the plurality of lock signals and output information to correct a problem causing a corresponding lock signal not be detected by the lock detector, and wherein the lock processor comprises: a timer configured to count a time starting from a time point at which the receiver is enabled; a memory having respective storage spaces assigned for the plurality of lock signals; and a storage controller configured to receive the lock signals from the lock detector and to control the demodulating operational steps of the digital demodulator using a final lock time of the received lock signals and time information corresponding to the time counted by the timer.