Patent ID: 9148136
Filing Date: 2015-09-29
Classification: H03K

Abstract:
1. A duty cycle correction method of a semiconductor apparatus, comprising: a first duty cycle correction step of adjusting a phase of a rising edge of a duty corrected clock when generating the duty corrected clock by correcting a duty cycle of an external clock; a delay locking step of delaying the external clock by a variable delay amount and generating a locked DLL clock when a first duty cycle correction end signal is enabled; and a second duty cycle correction step of adjusting a phase of a falling edge of the duty corrected clock when a DLL locking signal is enabled, wherein the first duty cycle correction step enables the first duty cycle correction end signal when the adjustment of the phase of the rising edge of the duty corrected clock is completed, and the delay locking step enables the DLL locking signal when a phase of the external clock coincides with a phase of a feedback clock.