Patent ID: 7822899
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A data processor comprising: a central processing unit which executes an instruction; circuit modules used by the central processing unit; an interrupt controller which makes a request for interruption to the central processing unit in response to a generated event signal; and an event link controller which outputs a start-of-operation control signal to each circuit module in response to a generated event signal, wherein each circuit module can produce the event signal, wherein the event link controller has a rewritable memory circuit, wherein the event link controller is directly connected to the circuit modules, wherein the memory circuit is used to store event control information for determining a start control signal to be output in response to the event signal, wherein on receipt of a first event signal from first one of the circuit modules, the event link controller outputs a first start control signal for causing second one of the circuit modules to transfer data to third one of the circuit modules, and wherein on receipt of a second event signal produced in response to completion of the data transfer from the second circuit module, the event link controller outputs a second start control signal for causing third one of the circuit modules to output the data outside of the data processor.