Patent ID: 6756818
Filing Date: 2004-06-29
Classification: H03K,H03L

Abstract:
A clock adjustment circuit comprising:a clock generator for generating a first reference clock signal and a second reference clock signal; and a voltage controlled delay line for delaying the first reference clock signal by a predetermined delay time to generate a first delay clock signal and delaying the second reference clock signal by the predetermined delay time to generate a second delay clock signal, the first reference clock signal and the first delay clock signal being in phase, the second reference clock signal and the second delay clock signal being in phase, the voltage controlled delay line comprising a plurality of delay cells, each delay cell comprising a first input port, a second input port, a first output port, and a second output port, the delay cells comprising: a first delay cell, a first input port of the first delay cell electrically connected to the clock generator for receiving the first reference clock signal; a second delay cell, a first input port of the second delay cell electrically connected to a first output port of the first delay cell through a first input port and a first output port of at least a fifth delay cell, a first output port of the second delay cell electrically connected to a second input port of the first delay cell, a second input port of the second delay cell electrically connected to a second output port of the first delay cell through a first input port and a first output port of at least a sixth delay cell and a second input port and a second output port of at least a fifth delay cell; a third delay cell, a first input port of the third delay cell electrically connected to the clock generator for receiving the second reference clock signal a second input port of the third delay cell electrically connected to a second output port of the second delay cell; and a fourth delay cell, a first input port of the fourth delay cell electrically connected to a first output port of the third delay cell through a second output port and a second input port of at least a fifth delay cell and a first output port and a first input port of at least a sixth delay cell, a second input port of the fourth delay cell electrically connected to a second output port of the third delay cell through a second input port and a second output port of at least a sixth delay cell, a first output port of the fourth delay cell used for outputting the first delay clock signal, a second output port of the fourth delay cell used for outputting the second delay clock signal; wherein a total amount of the fifth delay cells is equal to a total amount of the sixth delay cells.