Patent ID: 6300207
Filing Date: 2001-10-09
Classification: H01L,Y10S

Abstract:
A method of forming a metal oxide semiconductor transistor formed in a semiconductor substrate having a first conductivity including a heavily doped source region, a lightly doped source region, a heavily doped drain region, and a lightly doped drain region, each having a second conductivity opposite said first conductivity, and a channel region in said semiconductor substrate having said first conductivity separating said heavily doped source region and said heavily doped drain region, said lightly doped source region located adjacent said heavily doped source region and extending to said channel region, said lightly doped drain region located adjacent said heavily doped drain region and extending to said channel region, said method comprising the steps of:(a) forming a gate oxide on said semiconductor substrate;(b) depositing and patterning a layer of polysilicon on said gate oxide thereby forming a main gate region over said channel region having two sidewalls;(c) forming a mask on said semiconductor substrate which includes two disposable spacers each of which is adjacent one of said two sidewalls;(d) exposing said main gate region and portions of said semiconductor substrate to a first ion implant and subsequent first anneal, thereby doping said main gate region and forming said heavily doped source region and said heavily doped drain region;(e) removing said two disposable spacers;(f) exposing said semiconductor substrate to a second ion implant and subsequent second anneal, thereby forming said lightly doped source region and said lightly doped drain region below where said two disposable spacers were previous located; and(g) providing a depleted sidewall polysilicon spacer comprising depleted polysilicon adjacent each of said two sidewalls by depositing and patterning undoped polysilicon such that said lightly doped source region and said lightly doped drain region are fully overlapped by the combination of said depleted sidewall polysilicon spacers and said main gate region, said undoped polysilicon covering a portion of said lightly doped source region and said lightly doped drain region.