Patent ID: 9189325
Filing Date: 2015-11-17
Classification: G06F,G11C,H03M

Abstract:
1. A memory controller comprising: one or more processors operable to: control operations of a first non-volatile memory for storing data to be accessed in units of blocks, and a second non-volatile memory for storing data to be accessed in word units in random accesses to said second non-volatile memory, wherein each of said blocks of said first non-volatile memory is divided into a first area and a second area, wherein a first error correction codes to be applied to said data stored in said first non-volatile memory are stored in said second area of one or more of said blocks of said first non-volatile memory, wherein a second error correction codes to be applied to said data stored in said second non-volatile memory are stored in said first area of said one or more of said blocks, and wherein said second error correction codes are associated with consecutive addresses in said second non-volatile memory.