Patent ID: 6483767
Filing Date: 2002-11-19
Classification: G11C

Abstract:
A massively parallel processor device comprising:a sequencer for outputting address signals corresponding to a memory location; an address pipeline connected to said sequencer, said pipeline receiving the address signals and decoding the address signals into a word line address, said address pipeline driving an activation signal on a plurality of word lines corresponding to said word line address; a plurality of register files having a memory array, each register file receiving said activation signal on a respective one of said plurality of word lines and accessing memory cells from its memory array at said memory location; and a plurality of processor elements, each processor element connected to a respective register file, wherein said address pipeline comprises: a decode circuit, said decode circuit decoding the address signals into said word line address and driving said activation signal on said plurality of word lines, and first and second pipeline stages, said first pipeline stage receiving the address signals and outputting them to said second pipeline stage, said second pipeline stage receiving the address signals from said first pipeline stage and outputting them to said decode circuit.