Patent ID: 7961541
Filing Date: 2011-06-14
Classification: G11C

Abstract:
1. A memory circuit for dynamic memories having self-refresh capability, comprising: address and command buffers configured for receiving address and command information for controlling memory operations; a row activation selection (RAS) circuit coupled to said command buffer; a self-refresh circuit coupled to said command buffer; at least one refresh counter coupled to said self-refresh circuit; an address decoder configured for receiving the output from said address buffer, RAS circuit, self-refresh circuit and refresh counter; a block selection circuit coupled to said address decoder and configured for driving bit line equalization (BLEQ) circuits and sense amplifier enable (SAPN) circuits; a circuit for generating isolator control signals (ISO), pre-decoded row address drivers (PXID) and plural word enable (WE) lines selected from one or more of the following, (i) a block iso-selection circuit configured for driving an ISO generation circuit adapted for generating isolator control signals, said block iso-selection circuit configured with separate sequencing and/or timing, than said block selection circuit, in response to self-refresh mode operations of the memory circuit, wherein said block iso-selection circuit can selectively output fewer ISO signal transitions during self-refresh mode operations of the memory circuit than when in normal operating modes, (ii) a pre-decoded row address driver (PXID) circuit coupled to said self-refresh circuit and to a counter of said at least one refresh counter, in addition to being coupled to said address decoder; said PXID circuit configured with separate sequencing and/or timing than if coupled only to said address decoder, wherein said PXID circuit can selectively output fewer PXID signal transitions during self-refresh mode operations of the memory circuit than when in normal operating modes, (iii) a word enable (WE) circuit coupled to said self-refresh circuit and to a counter of said at least one refresh counter, in addition to being coupled to said address decoder, and said WE circuit configured with separate sequencing and/or timing than if it were only coupled to said address decoder, wherein said WE circuit can selectively output fewer WE signal transitions during self-refresh mode operations of the memory circuit than when in normal operating modes.