Patent ID: 9147459
Filing Date: 2015-09-29
Classification: G11C,H01L

Abstract:
1. A dynamic random memory access (DRAM) array, comprising: an isolated p-well; a first DRAM cell comprising an NMOS transistor formed within the isolated p-well and having a drain, a source, and a gate, and a capacitor electrically connected to the source; a second DRAM cell comprising an NMOS transistor formed within the isolated p-well and having a drain, a source, and a gate, and a capacitor electrically connected to the source; a first bit-line electrically connected to the drain of the NMOS transistor of the first DRAM cell; a second bit-line electrically connected to the drain of the NMOS transistor of the second DRAM cell; a word-line electrically connected to the gate of the NMOS transistor of the first DRAM cell and to the gate of the NMOS transistor of the second DRAM cell; and a diode having an anode and a cathode, having the anode electrically connected to the word-line and the cathode electrically connected to the isolated p-well, such that when the anode of the diode is at a first potential applied to the word-line the NMOS transistor has a first threshold value and when the anode of the diode is at a second potential applied to the word-line the NMOS transistor has a second threshold value, the second threshold value being lower than the first threshold value.