Patent ID: 6242805
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A semiconductor wafer for an integrated circuit, said semiconductor wafer comprising:a dielectric layer having a trench formed therein, said trench having a depth;a barrier layer having a thickness, said barrier layer located only in a bottom and along both sides of said trench;a metal layer disposed above said dielectric layer and above said barrier layer in said trench, said metal layer deposited to a thickness that is less than said depth of said trench; anda polish stop layer disposed above said metal layer, said polish stop layer having a thickness, said polish stop layer and said barrier layer effectively encapsulating all sides of said metal layer within said trench, wherein said thickness of said polish stop layer is approximately equal to the quotient of said thickness of said metal layer divided by a polishing selectivity value of said polishing stop layer, wherein a sum of said thickness of said barrier layer, said thickness of said metal layer and said thickness of said polish stop layer is approximately equal to said depth of said trench.