Patent ID: 7479814
Filing Date: 2009-01-20
Classification: H03L

Abstract:
1. A circuit for frequency synthesis in an integrated circuit having a delay line, said circuit comprising: an oscillator circuit having a counter-controlled delay line, said oscillator circuit coupled to receive a reference clock and generate an oscillator clock; a delay register coupled to said counter-controlled delay line, said delay register storing a delay value for said counter-controlled delay line; and a phase synchronizer circuit coupled to said oscillator circuit, said phase synchronizer circuit controlling the starting and stopping of said oscillator circuit to enable locking said oscillator circuit to a desired oscillator clock frequency, wherein said phase synchronizer circuit stops said oscillator circuit after a comparison of a frequency of said oscillator clock and a frequency of said reference clock to enable switching between a low frequency mode and a high frequency mode for locking said oscillator circuit to said desired oscillator clock frequency based upon said comparison, said low frequency mode and said high frequency mode being selected based upon said frequencies of said reference clock and said oscillator clock.