Patent ID: 6197649
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A process for fabricating a semiconductor device, said process comprising the steps of:forming at least one layer of a first insulation material atop an upper surface of a silicon substrate of one conductivity type;introducing a blanket layer of impurities of another conductivity type into said upper surface of said silicon substrate;patterning and etching away, using a single mask, selected regions of said first insulation material and said layer of impurities of another conductivity type to form a plurality of openings which expose underlying regions of said upper surface of said silicon substrate;forming localized oxide regions in said underlying regions of said silicon substrate;removing said layer of first insulation material to expose remaining, unoxidized regions of said silicon substrate;depositing an upper conductive layer;patterning and etching away selected portions of said upper conductive layer to form openings which expose at least a bordering portion of said silicon substrate; andintroducing impurities of said one conductivity type into said openings of said bordering portion to form equipotential rings.