Patent ID: 6146933
Filing Date: 2000-11-14
Classification: H01L

Abstract:
A method of manufacturing an isolated transistor comprising the steps of:(a) forming first and second diffusion layers in a semiconductor substrate extending in first and second directions orthogonal to each other, to arrange said first and second diffusion layers in said first direction, and forming a gate oxide film on said semiconductor substrate between said first diffusion layer and said second diffusion layer;(b) forming a gate electrode including a coupling portion on said gate oxide film and first and second contact pads with a first patterned mask to constitute a MOS transistor with said first and second diffusion layers;(c) forming first and second insulator with a second patterned mask to dispose said first insulator on a first side of said first and second diffusion layers in said second direction and to dispose said second insulator on a second side of said first and second diffusion layers in said second direction, said second side being opposite from said first side,wherein a margin is smaller than a deviation for an alignment of said first and second masks.