Patent ID: 9032252
Filing Date: 2015-05-12
Classification: G01R

Abstract:
1. An integrated circuit comprising: one or more transaction masters configured to generate a plurality of data transactions; debug access port circuitry configured to be coupled via a debug interface to a debug controller external of said integrated circuit; and interconnect circuitry coupled to said one or more transaction masters and said debug access port circuitry and configured to receive a plurality of data transactions from said one or more transaction masters and said debug access port circuitry, wherein said debug access port circuitry is configured to respond to one or more debug commands received from said debug controller via said debug interface to generate a barrier transaction; and said interconnect circuitry is configured to receive said barrier transaction and to respond to said barrier transaction by constraining a relative ordering between a first subset and a second subset of said plurality of data transactions at least through said interconnect circuitry.