Patent ID: 8338887
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. A buried gate transistor device comprising: a semiconductor body including an active region, the active region surrounded by an isolation region; a recess disposed in the active region; a dielectric layer lining sidewalls and a bottom surface of the recess; a gate electrode conductor filling the recess such that the dielectric layer is disposed between the gate electrode conductor and semiconductor material of the active region; a first source/drain region disposed within the active region adjacent at least an upper portion of a first sidewall of the recess, the first source/drain region being heavily doped to a first conductivity type, wherein the first source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess; a second source/drain region disposed within the active region adjacent at least an upper portion of a second sidewall of the recess, the second source/drain region being heavily doped to the first conductivity type, the second source/drain region being spaced from the first source/drain region by the recess, wherein the second source/drain region abuts the dielectric layer at a point on the sidewall, wherein the dielectric layer is thinner at the point than on the bottom surface of the recess, wherein an upper portion of the gate electrode conductor extends above an upper surface of the first and second source/drain regions; a spacer region disposed on a first part of sidewalls of the upper portion of the gate electrode conductor, a bottom surface of the spacer region being disposed over the first and second source/drain regions; a first insulating layer disposed between the spacer region and the first source/drain region, a sidewall of the first insulating layer disposed on a second part of the sidewalls of the upper portion of the gate electrode conductor; a second insulating layer disposed between the spacer region and the second source/drain region, a sidewall of the second insulating layer disposed on a third part of the sidewalls of the upper portion of the gate electrode conductor; a silicide region disposed on a portion of the upper surface of the first active region, the silicide region being laterally separated from the gate electrode conductor by the spacer region; and a channel region disposed within the active region at least beneath the bottom surface of the recess, the channel region being lightly doped to a second conductivity type that is opposite the first conductivity type, wherein the recess, the dielectric layer lining the sidewalls and the bottom surface of the recess, and the gate electrode conductor filling the recess extend into an adjacent active region.