Patent ID: 8386866
Filing Date: 2013-02-26
Classification: G01R

Abstract:
1. A method for performing a scan test for an integrated circuit comprising: generating a first set of test vectors configured to operate at a first test clock frequency; testing the integrated circuit using the first set of test vectors responsive to the first test clock frequency; identifying a first set of outlier cells of the integrated circuit responsive to the testing of the integrated circuit; generating a second set of test vectors responsive to the identified outlier cells, wherein the second set of test vectors is configured to operate at a second test clock frequency; testing the integrated circuit using the second set of test vectors at the second test clock frequency; identifying a second set of outlier cells of the integrated circuit responsive to the testing of the integrated circuit; and generating a third set of test vectors responsive to the second set of identified outlier cells, wherein the third set of test vectors is configured to operate at a third test clock frequency.