Patent ID: 6701140
Filing Date: 2004-03-02
Classification: H03L,H04L

Abstract:
A digital phase lock loop (PLL) having an internal PLL clock for synchronization with a received data signal of pulses having a maximum pulse edge rate, including a preamble and an information-containing data frame, said internal PLL clock having a clock rate about M times said pulse edge rate to define M successive samples of each one of said pulses, said PLL comprising:a state machine having an internal cyclic count of modulus M incremented in synchronism with said internal PLL clock, and a control input for updating said internal cyclic count, each cycle of said internal cyclic count including a center count value and an edge count value; sampling logic connected to receive said data signal and having a sampling control input connected to an output of said state machine, said sampling logic selecting a current one of said M successive samples when said internal count reaches the center count value; an edge detector responsive to said data signal; an error detector for sampling said internal count from said state machine in synchronism with said edge detector whereby to sense a phase error between the time of occurrence of a current one of said successive edges and the time of occurrence of said edge count value of said internal count; a cumulative phase error register; an adder for summing the contents of said cumulative phase error register with each successive phase error sensed by said error detector and inputting the resulting sum into said cumulative phase error register, whereby to store in said cumulative phase error register a cumulative phase error of a plurality of N phase errors summed over N edges of said data signal; a terminal counter having a cyclic count of modulus T for counting by a time base comprising a selected one of: (a) edges sensed by said edge detector and (b) a time-based signal, said terminal counter providing a terminal count signal which is asserted whenever said cyclic count of said terminal counter counts through said modulus T; correction logic for applying a correction signal derived from the contents of said cumulative phase error register to said correction input of said state machine and for enabling said correction input of said state machine upon assertion of said terminal count signal, whereby the period of said terminal count signal determines the number N of said plurality of phase errors., so that successive cumulative phase errors are computed and corresponding corrections made to said internal count periodically; reset logic for resetting said cumulative phase error register upon assertion of said terminal count signal; and a time-base selector for selecting said edges as the time base during said preamble and for selecting said time-based signal as the time base during said data frame.