Patent ID: 6238976
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method of forming a memory array, the method comprising the steps of:forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;forming a plurality of first source/drain regions, of a second conductivity type, each of the first source/drain regions formed proximally to an interface between each pillar and the substrate;forming a plurality of second source/drain regions, of a second conductivity type, each of the second source/drain regions formed within one of the pillars and distal to the substrate and separate from each of the plurality of first source/drain region;forming a gate dielectric on at least a portion of the side surface of the pillars;forming at least two floating gates per pillar, each of the floating gates formed adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;forming a plurality of control gates, each of the control gates formed adjacent to at least one of the floating gates and insulated therefrom;forming a intergate dielectric, interposed between the plurality of floating gates and the plurality of control gates;forming a plurality of first gate lines, each first gate line interconnecting a plurality of the control gates;forming a plurality of second gate lines, each second gate line interconnecting a plurality of the control gates;forming at least one first source/drain interconnection line interconnecting a plurality of the first source/drain regions; andforming a plurality of data lines, each data line interconnecting the plurality of second source/drain regions.