Patent ID: 6021267
Filing Date: 2000-02-01
Classification: G03F

Abstract:
A method of optimizing efficiency of chip shape layout printed on semiconductors by a plurality of lithography tools comprising the steps of:a) providing a plurality of lithography tools for printing different layers or areas of chips on a semiconductor wafer;b) determining, for each of said lithography tools, possible unit cells and unit cell matrices printable by said tool at one exposure and at one chip aspect ratio, wherein a unit cell comprises a matrix of one or more chips to be printed;c) determining, for each of said lithography tools, an overall tool cost based on said possible unit cells and unit cell matrices;d) determining, for each of said lithography tools, a desired unit cell matrix based on cost;e) repeating steps (b)-(d) for a different chip aspect ratio having the same area; andf) selecting a desired chip aspect ratio, based on cost, for printing on different layers or areas on a semiconductor wafer using said plurality of lithography tools, wherein the cost equals any cost factor.