Patent ID: 6399987
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A MOS transistor having a self-aligned well bias region, the MOS transistor comprising:a semiconductor substrate on which a well of a first conductivity type is formed; at least two gate patterns, each of which includes a gate oxide film, a gate electrode and a capping layer which are sequentially stacked on the semiconductor substrate, and a gate spacer formed on the sidewalls of the gate electrode and the capping layer; source/drain regions doped with second conductivity type impurities, the source/drain regions formed in the surface of the semiconductor substrate adjacent to the gate patterns; a trench formed between the gate patterns by etching the semiconductor substrate in a manner of self-alignment using the gate spacer, wherein the trench is formed to a depth so as to pass through the source/drain regions and come in contact with the first conductivity type well of the semiconductor substrate; a well bias area formed at the side of the lower portion and the bottom of the trench; and a contact filling the self-aligned trench.