Patent ID: 8898438
Filing Date: 2014-11-25
Classification: G06F

Abstract:
1. A processor comprising: an execution unit for executing multiple threads and, for each of said multiple threads, respective hardware dedicated to that thread comprising a respective set of registers arranged to store information relating to that thread, each thread comprising a sequence of instructions, and each thread and its respective dedicated hardware being designated to handle respective communication activity from at least one respective specified communications source; and a thread scheduler for scheduling each of a plurality of said threads to be executed by the execution unit, wherein the scheduling of each respective one of said plurality of threads comprises suspending execution of the respective thread having been designated to handle the respective communication activity from the respective specified communications source, and resuming the respective thread based on the respective communication activity from the respective specified communications source designated to be handled by the respective thread; wherein at least a part of said information is accessible by the execution unit for use in executing the respective thread when scheduled; and wherein, for each of said threads, the respective hardware dedicated to that thread remains designated to handle the respective communication activity from the at least one respective specified communications source while that thread is suspended.