Patent ID: 6753242
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method of forming an integrated circuit device comprising:providing a semiconductor substrate; forming a first patterned layer over the semiconductor substrate, wherein the first patterned layer has a first top, a first sidewall and a second sidewall and the first sidewall and the second sidewall are approximately vertical and opposite each other; forming a second patterned layer over the patterned dielectric layer, wherein the second patterned layer has a second top, a third sidewall and a fourth sidewall, the third sidewall and the fourth sidewall are approximately vertical, opposite each other, and approximately co-planar with the first sidewall and the second sidewall, respectively; forming an anti-reflective coating (ARC) over the second patterned layer; forming a first dielectric layer over the first top and the second top and adjacent to the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall; removing a portion of the first dielectric layer, to form a first dielectric region adjacent the first sidewall and the third sidewall and a second dielectric region adjacent the third sidewall and the fourth sidewall, wherein the portion includes regions of the first dielectric layer formed over the first top and the second top; removing the ARC after removing the portion of the first dielectric layer; and forming a channel region within the semiconductor substrate under the first patterned layer and second patterned layer.