Patent ID: 7570539
Filing Date: 2009-08-04
Classification: G11C

Abstract:
1. A computer implemented method for identifying bit cells and connections, the method comprising: receiving a bit cell netlist; defining a reference bit pattern for each bit cell node in at least one memory bit cell, wherein each reference bit pattern comprises a combination of bit values, and wherein each combination of bit values indicates a type of memory bit cell node; receiving a circuit block netlist associated with a circuit block to be analyzed; defining a node pattern for each node in the circuit block; matching the node patterns of the circuit block with the reference bit patterns of the at least one memory bit cell; identifying at least one type of memory bit cell node in the circuit block based on a combination of different matched reference bit patterns, identifying at least one type of memory bit cell in the circuit block based on the at least one identified type of memory bit cell node; and identifying memory bit cells in the circuit block and corresponding bit line connections and word line connections in the circuit block based on the at least one identified type of memory bit cell.