Patent ID: 6215699
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A nonvolatile semiconductor storage device having a memory array in which control gates and drains of a plurality of memory cell transistors that have floating gates and are able to execute electrical writing and erasing of information are connected to word lines and bit lines arranged in a matrix form, the nonvolatile semiconductor storage device comprising:a main block that constitutes part of the memory array and has a specified number of the memory cell transistors of which the control gates are connected to a first specified number of the word lines; anda redundancy block that constitutes the other part of the memory array, has a specified number of the memory cell transistors of which the control gates are connected to a second specified number of the word lines and is used for replacing a defective memory cell transistor in the main block, whereinthe main block and the redundancy block being formed in regions that are electrically insulated from each other on a substrate.