Patent ID: 6185658
Filing Date: 2001-02-06
Classification: G06F

Abstract:
A method of evicting a cache block in a cache used by a computer processor, the method comprising the steps of:defining a congruence class of the cache consisting of a plurality of cache blocks;assigning at least four cache coherency states to the cache blocks, wherein the coherency states include an invalid state, a hover state, a modified state, and a shared state;comparing a requested address with a plurality of addresses respectively associated with the plurality of cache blocks to determine when a requested address is not present in the cache; andselecting one of the cache blocks in the congruence class for eviction, in response to said comparing step, based on the cache coherency states of the cache blocks, wherein said selecting step selects a cache block having an invalid state if present in the congruence class and, if not, selects a cache block having a hover state if present in the congruence class and, if not, selects a cache block having a modified state if present in the congruence class.