Patent ID: 7054477
Filing Date: 2006-05-30
Classification: G06K,H01L

Abstract:
1. An automatic accurate alignment method to be implemented by a semiconductor wafer cutting apparatus for positioning a semiconductor wafer at a required position, the semiconductor wafer being formed with an array of polygonal circuit areas, adjacent ones of the polygonal circuit areas being spaced apart by linear cutting streets, the semiconductor wafer cutting apparatus including a platform for holding the semiconductor wafer, the platform being movable along a first axis and being rotatable about a second axis transverse to the first axis, a camera unit disposed above the platform and operable so as to generate an electrical output corresponding to at least a part of an image of the semiconductor wafer on the platform, the camera unit being movable along a third axis transverse to the first and second axes, a cutter unit movable with the camera unit along the third axis and further movable along the second axis, and a processing unit coupled electrically to the platform, the camera unit and the cutter unit, the processing unit receiving the electrical output of the camera unit and controlling movements of the platform, the camera unit and the cutter unit, the processing unit being configured with a key pattern database that contains a key pattern of a key polygonal circuit area having at least a first dimension along a first cutting direction and a second dimension along a second cutting direction, said automatic accurate alignment method comprising the steps of: (a) placing the semiconductor wafer on the platform, and enabling the processing unit to move the platform and the camera unit to initial positions; (b) enabling the processing unit to match the electrical output of the camera unit with the key pattern to find a plurality of adjacent working patterns in the electrical output of the camera unit, and to record center point coordinates of the working patterns; (c) enabling the processing unit to calculate at least one distance value associated with the center point coordinates of a corresponding adjacent pair of the working patterns; (d) enabling the processing unit to determine whether any one distance value calculated in step (c) complies with one of the first and second dimensions of the key polygonal circuit area; and (e) upon determination that there is one distance value calculated in step (c) that complies with one of the first and second dimensions of the key polygonal circuit area, enabling the processing unit to rotate the platform about the second axis so that an imaginary line interconnecting the center point coordinates that are associated with said one distance value is disposed parallel to one of the first and second cutting directions.