Patent ID: 6134579
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A computer system comprising:a plurality of processes;a system input/output (I/O) coupled to each of said plurality of processes, said system I/O connecting a plurality of devices to said system I/O via interface slots within said system I/O, each of said plurality of devices accessible by each of said plurality of processes;said system I/O further including a plurality of semaphores, one for each of said plurality of devices connected to said system I/O, for indicating the status of corresponding ones of said plurality of devices, each of said plurality of semaphores responsive to a check signal received from one of said plurality of processes and configured to output to said one of said plurality of processes a first value when the semaphore's corresponding device is available and a second value when the semaphore's corresponding device is unavailable; andsaid system I/O further including an ASIC for controlling each of said plurality of semaphores within said system I/O, said ASIC further for changing the value of particular ones of said plurality of semaphores from said first value to said second value in response to both said particular semaphore receiving a check a signal from at least one of said plurality of processes and said particular semaphore having said first value.