Patent ID: 6555409
Filing Date: 2003-04-29
Classification: G02F,H01L

Abstract:
A method for fabricating a thin film transistor array substrate, comprising the steps of:forming a gate line assembly of an aluminum-based conductive layer onto an insulating substrate, the gate line assembly comprising gate lines, and gate electrodes connected to the gate lines; depositing a gate insulating layer over the substrate and the gate line assembly; forming a semiconductor layer on the gate insulating layer; forming a data line assembly of a double-layered conductive film with a first layer and a second layer overlying the first layer, the data line assembly comprising data lines crossing over the gate lines, source electrodes connected to the data lines, and drain electrodes separated from the source electrodes while interposing the gate electrodes; forming a protective layer having first contact holes over the drain electrodes; and forming pixel electrodes on the protective layer such that the pixel electrodes are connected to the drain electrodes through the first contact holes, wherein the first layer of the conductive film is patterned through dry etch.