Patent ID: 7944058
Filing Date: 2011-05-17
Classification: H01L

Abstract:
1. A stacked semiconductor device consisting of a first semiconductor device having outside electrode terminals on a lower surface thereof, a second semiconductor device electrically connected with said first semiconductor device and secured on said first semiconductor device, said first semiconductor device comprising: a first semiconductor substrate; first circuit elements at a first main surface of said first semiconductor substrate; a first multilayer wiring part on said first circuit elements and configured of a first wiring electrically connected with said first circuit elements and a first insulating material layer, the first wiring and the first insulating material layer being stacked alternately with the first insulating material layer being an uppermost layer; a first insulating layer for covering said first insulating material layer of said first multilayer wiring part and provided over the first main surface of said first semiconductor substrate, said first insulating layer is a support member of said first semiconductor substrate; a second insulating layer for covering a second main surface of said first semiconductor substrate that is opposite the first main surface of said first semiconductor substrate, wherein the first insulating layer has greater thickness than the second insulating layer; a plurality of first post electrodes on said first wiring of said first multilayer wiring part and each having a top surface and side surfaces, the top surfaces of said first post electrodes exposed from a surface of said first insulating layer and all the side surfaces of said first post electrodes covered by said first insulating layer; a plurality of first through-type electrodes penetrating from a specified depth of said first multilayer wiring part to a surface of said second insulating layer through said first semiconductor substrate, said first through-type electrodes insulating from said first semiconductor substrate by a first insulating film and connected with said first wiring of said first multilayer wiring part; and said outside electrode terminals connected to said first through-type electrodes, said second semiconductor device comprising a second semiconductor substrate; second circuit elements formed at a first main surface of said second semiconductor substrate; a second multilayer wiring part on said second circuit elements and configured of a second wiring electrically connected with said second circuit elements and a second insulating material layer, the second wiring and the second insulating material layer being stacked alternately with the second insulating material layer being an uppermost layer; a third insulating layer for covering said second insulating material layer of said second multilayer wiring part and provided over the first main surface of said second semiconductor substrate, said third insulating layer is a support member of said second semiconductor substrate; a fourth insulating layer for covering a second main surface of said second semiconductor substrate that is opposite the first main surface of said second semiconductor substrate; wherein the third insulating layer has greater thickness than the fourth insulating layer; and at least second post electrodes on said second wiring of said second multilayer wiring part and each having a top surface and side surfaces, the top surfaces of said second post electrodes exposed from a surface of said third insulating layer and all the side surfaces of the second post electrodes covered by said third insulating layer, or a plurality of second through-type electrodes penetrating from a specified depth of said second multilayer wiring part to a surface of said fourth insulating layer through said second semiconductor substrate, said second through-type electrodes insulated from said second semiconductor substrate by a second insulating film and connected with said second wiring of said second multilayer wiring part, in said first semiconductor device, said first post electrodes or said first through- type electrodes are at the lower surface thereof and are provided with said outside electrode terminals, and said second through-type electrodes or said second post electrodes at a lower surface of said second semiconductor device are electrically connected with said first post electrodes or said first through-type electrodes at an upper surface of said first semiconductor device through joints.