Patent ID: 7491896
Filing Date: 2009-02-17
Classification: H01L,H05K,Y10T

Abstract:
1. An information handling system comprising: a housing; an electrical assembly positioned substantially within said housing and including a circuitized substrate having at least one electrically conductive layer of substantially planar configuration and having first and second opposing surfaces, said at least one electrically conductive layer including at least two separate, electrically isolated portions, each electrically isolated portion including an edge portion substantially facing an edge portion of at least one other electrically isolated portion, each of said edge portions facing each other comprised of a plurality of contiguous formed open segments, a first dielectric layer positioned on said first opposing surface of said at least one electrically conductive layer, a portion of said first dielectric layer being positioned within selected ones of said contiguous formed open segments of each of said facing edge portions, said first dielectric layer including a plurality of openings each aligned above a respective one of the remaining ones of said contiguous formed open segments, and a second dielectric layer positioned on said second opposing surface of said at least one electrically conductive layer, a portion of said second dielectric layer being positioned within said remaining ones of said contiguous formed open segments of each of said facing edge portions and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, only said portion of said first dielectric layer being positioned within said selected ones of said contiguous formed open segments of each of said facing edge portions and substantially only said portion of said second dielectric layer being positioned with said remaining ones of said contiguous formed open segments of each of said facing edge portions and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous formed open segments, said portions of both of said first and second dielectric layers positioned within said contiguous formed open segments of said facing edge portions providing a common, substantially solid dielectric barrier between said facing edge portions; and at least one electrical component positioned on and electrically coupled to said circuitized substrate of said electrical assembly.