Patent ID: 9196625
Filing Date: 2015-11-24
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a memory device comprising: creating a stackup of at least two alternating tier insulating layers and circuit layers, wherein the circuit layers individually comprise a conductive layer sandwiched between sacrificial layers that are differentiated from the tier insulating layer; creating a hole through the stackup; etching the conductive layers back from the hole; etching the sacrificial layers back from the hole; forming a blocking dielectric film inside the hole, wherein the blocking dielectric film is no thicker than an individual sacrificial layer of the sacrificial layers; creating floating gates in the cavities created by the etching of the conductive layers and the sacrificial layers, wherein the floating gates are separated from the conductive layers and the tier insulating layers by the blocking dielectric film; forming a tunneling dielectric film inside the hole; and filling the hole with semiconductor material, wherein the semiconductor material is separated from the floating gates by the tunneling dielectric film; wherein the creating the stackup comprises: treating the sacrificial layers after deposition to differentiate the sacrificial layers from the tier insulating layers; and wherein the sacrificial layers and the tier insulating layers both comprise silicon oxide.