Patent ID: 6434658
Filing Date: 2002-08-13
Classification: G06F

Abstract:
A memory device having a write mode in which data is stored upon reception of an external write address signal and an external write data train from a host system, comprising:(a) a flash memory in which, during data erase operation, data is erased from each unit memory region holding a prescribed number of bits of data, and in said write mode, an internal write data train having a prescribed data length is written according to an internal write address signal; and (b) a data input/output portion for receiving said external write address signal and generating said internal write address signal, for receiving and holding said external write data train, and for outputting said internal write data train based on said external write data train and said external write address signal in said write mode, wherein said data input/output portion includes (b-1) a first interface portion for receiving said external write data train and said external write address signal from said host system in said write mode, (b-2) a buffer memory having a storage capacity corresponding to data elements not smaller in number than data elements contained in said external write data train and smaller in number than data elements contained in said internal write data train, and for receiving said external write data train from said first interface portion in said write mode, and (b-3) a second interface portion for receiving said external write address signal from said first interface portion and generating said internal write address signal, and for generating said internal write data train by adding to said external write data train read from said buffer memory dummy data which preserve storage data from overwriting erasure in said unit memory region according to said external write address signal.