Patent ID: 8558600
Filing Date: 2013-10-15
Classification: G06F

Abstract:
1. A clock signal generation circuit for generating a high speed clock signal having a first frequency and a low speed clock signal having a second frequency lower than the first frequency, comprising: a first oscillation circuit for generating a first oscillation clock signal having the first frequency; a second oscillation circuit for generating a second oscillation clock signal having the second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as the high speed clock signal, wherein said clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and said clock selection circuit is configured to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.