Patent ID: 6194757
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A semiconductor device, comprising:first and second source/drain regions formed spaced apart with a channel region therebetween at a main surface of a semiconductor region;a gate electrode formed on said channel region;a first etch stop layer comprised of an insulating film formed over said gate electrode;a first interlayer insulating film formed on said first etch stop layer;a bit line opening formed in a region of said first interlayer insulating film and said first etch stop layer located on said first source/drain region;a first capacitor opening formed in a region of said first interlayer insulating film and said first etch stop layer located on said second source/drain region;a bit line connected to said first source/drain region through said bit line opening;a plug electrode connected to said second source/drain region through said first capacitor opening and filling said first capacitor opening, and having its top surface area larger than its bottom surface area;a capacitor lower electrode electrically connected to the top surface of said plug electrode and covering top and side surfaces of said bit line with a first insulating film located therebetween;a second insulating film formed only on a portion of said first insulating film and having opposed side edge surfaces in contact with said capacitor lower electrode;a capacitor dielectric film formed on said capacitor lower electrode and extending continuously over an upper surface of said second insulating film; anda capacitor upper electrode formed on said capacitor dielectric film.