Patent ID: 8200882
Filing Date: 2012-06-12
Classification: G06F

Abstract:
1. A memory system comprising: a memory that has plurality of banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plurality of masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors bank information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from among the plurality of masters of the master group based on the queue information and the bank information provided thereto and transmits access control information to the memory controller.