Patent ID: 6229353
Filing Date: 2001-05-08
Classification: G05F,H03K

Abstract:
A method for biasing a source-coupled pair of MOSFET input transistors connected in a logic circuit including a transistor for controlling the bias of the input transistors and including an output source follower MOSFET transistor, the method comprising maximizing the difference between output logic high and output logic low voltages and maximizing the current supplied to the source coupled pair of input transistors by selecting circuit component values so thatV.sub.OH =V.sub.DD -V.sub.T3H -V.sub.DS3SAT andV.sub.OL =V.sub.DS9SAT +V.sub.T1LwhereinV.sub.OH is the high level output voltage of the logic circuit,V.sub.OL is the low level output voltage of the logic circuit,V.sub.DD is a drain supply voltage,V.sub.T3H is the threshold voltage of said output source follower transistor when its output is in a high state,V.sub.T1L is the threshold voltage of said input transistor when its input is in a low state,V.sub.DS3SAT is the saturation voltage across the drain and source terminals of an output source follower transistor, andV.sub.DS9SAT is the saturation voltage across the drain and source terminals of said bias controlling transistor.