Patent ID: 6751138
Filing Date: 2004-06-15
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit device comprising:a first memory matrix including a plurality of dynamic type memory cells, a second memory matrix including a plurality of dynamic type memory cells, a substrate bias generator circuit, a decoder circuit, a redundancy circuit and a pad which are formed on a semiconductor substrate, wherein redundancy address data for converting from an address of said first memory matrix to an address of said second memory matrix are stored in elements included in said redundancy circuit, wherein ones of said dynamic type memory cells of said first memory matrix are selected by said decoder circuit when said redundancy address data is not coincident with an address signal from said decoder circuit, wherein ones of said dynamic type memory cells of said second memory matrix are selected by said decoder circuit when said redundancy address data is coincident with an address signal from said decoder circuit, wherein a voltage used to indicate data for storing said redundancy address into said elements is applied to said pad, and wherein said substrate bias generator circuit is deactivated when said voltage is applied to said pad for storing said redundancy address into said elements.