Patent ID: 6498399
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A microelectronic device which comprises(a) a substrate; (b) a layer of a first dielectric material positioned on the substrate; (c) a layer of a second dielectric material positioned on the first dielectric layer: wherein the first dielectric material and the second dielectric material have substantially different etch resistance properties; (d) an additional layer of the first dielectric material positioned on the second dielectric material; (e) at least one via extending through the first dielectric material layer and the second dielectric material layer and at least one trench through the additional layer of the first dielectric material extending to at least one via; (f) a lining of a barrier metal on inside walls and a floor of the trench and on inside walls and a floor of the via; (g) a fill metal filling the trench and via in contact with the lining of the barrier metal; wherein the first and second dielectric materials each comprise a material selected from the group consisting of a silicon containing polymer, an alkoxysilane polymer, a silsesguioxane polymer, a siloxane polymer, a poly(arylene ether), a fluorinated poly(arylene ether), a nanoporous silica and combinations thereof.