Patent ID: 8309450
Filing Date: 2012-11-13
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device including a memory cell portion and a select gate portion, the method comprising: forming a tunnel insulating film on a semiconductor substrate; forming a charge accumulation layer on the tunnel insulating film; etching the charge accumulation layer, the tunnel insulating film, and the semiconductor substrate to make a trench for isolating elements; burying a first insulating film in the trench to contact with a side surface of the charge accumulation layer; performing heat processing to compress the first insulating film; forming a second insulating film on the charge accumulation layer and the first insulating film; etching the second insulating film in the select gate portion to expose a surface of the charge accumulation layer; forming a silicon layer to contact with the exposed surface of the charge accumulation layer; forming a metal layer on the silicon layer; and performing heat processing to silicide an entire boundary region between the charge accumulation layer and the tunnel insulating film.