Patent ID: 8347019
Filing Date: 2013-01-01
Classification: G06F

Abstract:
1. A design structure including universal peripheral processor architecture embodied in a non-transitory machine readable storage medium for data storage or transmission for designing, manufacturing, or testing an integrated circuit (IC), the design structure comprising: a first data bus and a second data bus wherein the first and second data buses are coupled to a TCAM (ternary content addressable memory) providing communication between the first and second data buses, the TCAM is part of a finite state machine; a processor for managing control functions on the IC being coupled to the TCAM, the TCAM interfacing with the processor using at least one predefined signaling protocol, the TCAM using pattern matching to match a particular state of one or more signals for communicating state information to the processor using a hardware branch vector, the hardware branch vector communicating and receiving an execution thread from the processor, the hardware branch vector defining a point at which the processor acts on a current state of the finite state machine; a data path enabling transfer of data between the first and second data buses, wherein the data path also communicates with a data storage device; a data control path enabling communication between and coupled to the data storage device, the processor, and the TCAM, and the processor using the TCAM for determining next processor operations; and a non-transitory machine readable storage medium for data storage or transmission embodying the features above in a design structure.