Patent ID: 8694703
Filing Date: 2014-04-08
Classification: G06F,H03M

Abstract:
1. A data compression apparatus, comprising: a plurality of hash memories each associated with a different lane of a plurality of lanes, and each lane comprising data bytes of an incoming data stream being received by the data compression apparatus; validity table comprising array elements each comprising a plurality of validity bits, wherein each validity bit within an array element corresponds to a different lane of the plurality of lanes; control logic, coupled to the plurality of hash memories and the validity table, that initiates a read of a hash memory entry if a validity bit that corresponds to the lane associated with the hash memory entry indicates that said hash memory entry is valid; and an encoder, coupled to the plurality of hash memories and the control logic, that compresses at least the data bytes for the lane associated with the hash memory comprising the valid hash entry if said valid hash entry comprises data that matches the data bytes for the lane.