Patent ID: 8959317
Filing Date: 2015-02-17
Classification: G06F

Abstract:
1. A microcomputer comprising: memory that stores a plurality of register lists having a plurality of register patterns, respectively, wherein each of the plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch an instruction code of an interrupt handler from an instruction memory in response to a control signal; a register data saving control circuit configured to acquire, from the memory, one register pattern from one of said plurality of register lists in response to a first pattern number, and issue a microinstruction based on the acquired register pattern; an interrupt processing control circuit that outputs the control signal and the first pattern number in response to an interrupt request issued based on occurrence of an interrupt factor; and an instruction executing section configured to execute said microinstruction prior to the fetched instruction code, to save the data of resisters designated based on the acquired register pattern in the data memory; and an interrupt controller configured to output an interrupt vector and a second pattern number for an interrupt signal supplied on any of a plurality of interrupt signal lines, wherein said interrupt processing control circuit outputs the control signal in response to the interrupt vector and outputs the first pattern number in response to the second pattern number, wherein said interrupt controller comprises a plurality of pattern number registers, one of which is provided for said interrupt factor, wherein a plurality of pattern numbers are stored in said plurality of pattern number registers, and wherein said interrupt controller outputs one of the plurality of pattern numbers corresponding to said interrupt factor as the second pattern number.