Patent ID: 6266792
Filing Date: 2001-07-24
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory blocks each of which has a plurality of memory cells;a data input/output buffer which receives data to be stored in a memory block in said plurality of memory blocks and which outputs data read from a memory block in said plurality of memory blocks;a control circuit which controls a write operation for writing data to a memory block in said plurality of memory blocks, an erase operation for erasing data of a memory block in said plurality of memory blocks and a read operation for reading data from a memory block in said plurality of memory blocks; anda memory circuit designating a defective block in said plurality of memory blocks,wherein said control circuit inhibits said write and said erase operation for a defective block designated by said memory circuit, and wherein said control circuit inhibits outputting of data from said input/output buffer for said defective block in said read operation.