Patent ID: 6826737
Filing Date: 2004-11-30
Classification: G06F,G11B

Abstract:
For an electronic design automation application, a partitioning method of placing circuit modules in a region of an integrated circuit (â€œICâ€ ) layout, wherein said IC layout includes nets and a plurality of circuit elements, each net representing interconnections between a set of circuit elements in the IC layout, the method comprising:a) defining a plurality of partitioning lines that divide the IC region into several sub-regions; b) identifying the set of sub-regions containing the circuit elements of a net, said set of sub-regions representing the net's configuration with respect to the defined partitioning lines; wherein a connection graph models the net's configuration with respect to the defined partitioning lines; said connection graph having an edge that is completely or partially diagonal; and c) identifying an attribute of the connection graph.