Patent ID: 6599787
Filing Date: 2003-07-29
Classification: G02F,H01L

Abstract:
A method of manufacturing an active matrix substrate comprising a row and column array of active elements wherein each element is associated with a thin film transistor (TFT) having a gate electrode connected to a corresponding row conductor and source and drain electrodes connected to corresponding column conductors; andESD protective circuitry connected to at least one of the row conductors for protecting the TFTs against electrostatic discharge (ESD), the method comprising the steps of: forming semiconductor regions of the TFTs and the ESD protective circuitry; depositing gate electrodes of the TFTs and corresponding row conductors; and depositing source and drain electrodes of the TFTs and corresponding column conductors, wherein the ESD protective circuitry is operative to control ESD prior to deposition of the column conductors.