Patent ID: 7692274
Filing Date: 2010-04-06
Classification: H01L

Abstract:
1. A reinforced semiconductor structure, comprising: a semiconductor wafer comprising a plurality of low-k dielectric layers formed thereon; at least one scribe line region defined over the semiconductor wafer, separating at least two active regions formed over the semiconductor wafer; at least one test element formed in the scribe line region, passing through the low-k dielectric layers therein and having a test pad exposed by a topmost low-k layer of the low-k dielectric layers therein; a plurality of first non-dielectric pillars formed in the topmost layer of the low-k dielectric layers in the scribe line region; and a plurality of second non-dielectric pillars and first vias formed in a first low-k dielectric layer underlying the topmost low-k layer in the scribe line region, wherein the second non-dielectric pillars electrically connect the first non-dielectric pillars by the first vias, respectively, wherein the first vias and the first and second non-dielectric pillars surround the test pad from each side thereof.