Patent ID: 7550361
Filing Date: 2009-06-23
Classification: B82Y,G03F,H01J,H01L

Abstract:
1. A method of fabricating an integrated circuit chip, comprising: forming a first pad layer on a top surface of a semiconductor substrate; forming a hardmask layer on a top surface of said pad layer; etching an opening in said hardmask layer, a region of said top surface of said pad layer exposed in a bottom of said opening; etching a first trench through said pad layer exposed in said opening in said hardmask into said substrate, said first trench located in a first position on said substrate relative to a floor plan of said integrated circuit chip; completely removing said hardmask layer and said first pad layer; forming a second pad layer on said top surface of said substrate and on sidewalls and a bottom surface of said first trench; locating one or more second trenches in respective one or more second positions on said substrate relative to said floor plan layout of said integrated circuit chip and etching said one or more second trenches through said second pad layer into said substrate; at least partially filling said first trench and simultaneously completely filling said one or more second trenches with an insulator; and removing said insulator from said first trench.