Patent ID: 7541655
Filing Date: 2009-06-02
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor device comprising: a memory cell; a first bit line and a second bit line each connected to the memory cell; a first gate and a second gate disposed in parallel to each other; a first circuit controlling the memory cell provided with a first diffusion area formed outside of the first gate, a second diffusion area formed between the first gate and the second gate and a third diffusion area formed outside of the second gate; and a second circuit controlling the memory cell provided with a fourth diffusion area formed outside of the first gate, a fifth diffusion area formed between the first gate and the second gate and a sixth diffusion area formed outside of the second gate; wherein the first diffusion area is connected with the sixth diffusion area via the first bit line, the third diffusion area is connected with the fourth diffusion area via the second bit line, and the second diffusion area is connected with the fifth diffusion area via a power supply.