Patent ID: 6269425
Filing Date: 2001-07-31
Classification: G06F

Abstract:
A memory-cache system for use in a multithread processing environment in which memory accesses are associated with a processing thread which generated the memory access, the system comprising:a cache configured for connection to a main memory system and a processing system for receiving from said processing system memory access commands identifying a thread and data to be stored in said main memory system or data to be loaded from said main memory system, said cache loading data from and storing data to said main memory system in response to said memory access commands, said cache further including a plurality of lines each for caching data passed between said processing system and said cache in response to a memory access command, each line associating said data with the thread identified by the memory access command,a cache storage control circuit, the storage control circuit managing loading of data from said main memory system to said cache and storing of data to said main memory system from said cache, said storage control circuit accumulating counts of the number of threads awaiting loading of data to a plurality of cache lines said storage control circuit prioritizing loading of data to the cache system, based on said counts of the number of threads that are awaiting loading of data in cache lines.