Patent ID: 9006103
Filing Date: 2015-04-14
Classification: H01L,H05K

Abstract:
1. A method of manufacturing a wiring substrate, comprising: forming an etching stop layer on a supporting member; forming a build-up intermediate body on the etching stop layer; wherein the build-up intermediate body is formed on the etching stop layer by alternately laminating a wiring layer and an insulating layer, wherein the build-up intermediate body are provided with an uppermost wiring, an uppermost insulating layer, a lowermost wiring layer and a lowermost insulating layer, and wherein the lowermost wiring layer and the lowermost insulating layer are contacted to the etching stop layer opposite to the uppermost wiring layer and the uppermost insulating layer, wherein the uppermost wiring layer is arranged uppermost among the wiring layer of the build-up intermediate body, wherein the uppermost insulating layer is arranged uppermost among the insulating layer of the intermediate body; removing the supporting member so as to expose the etching stop layer; removing the etching stop layer so as to expose the lowermost wiring layer; forming a first insulating layer on the uppermost insulating layer so as to cover the uppermost wiring layer, and forming a second insulating layer on the lowermost insulating layer so as to cover the lowermost wiring layer; forming a first via hole reaching the uppermost wiring layer in the first insulating layer, and forming a second via hole reaching the lowermost wiring layer in the second insulating layer; forming a roughened face to the first insulating layer and the second insulating layer; and forming a first wiring layer connected to the uppermost wiring layer through the first via in the first insulating layer, and forming a second wiring layer connected to the lowermost wiring layer through the second via hole in the second insulating layer.