Patent ID: 9223751
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A method comprising: receiving a user-level rounding instruction of an instruction set architecture (ISA) having a format including a source operand, a destination operand and an immediate value, in a control selector unit of a processor; determining if a rounding mode override indicator of the immediate value is active by decoding the immediate value in the control selector unit; if so, obtaining a rounding mode field of the immediate value, the rounding mode field separate from the override indicator, and dispatching the source operand and information to control a rounding mode to a floating point unit of the processor coupled to the control selector unit, the rounding mode field to indicate one of a plurality of rounding modes; and executing a rounding operation on a source operand in the floating point unit of the processor responsive to the user-level rounding instruction and according to the information, including when a configuration register is set for denormal numbers as zero and the source operand is a denormal number, converting the source operand to zero before executing the rounding operation.