Patent ID: 8320101
Filing Date: 2012-11-27
Classification: C23C,C25D,H01G,Y10T

Abstract:
1. A method for manufacturing a multilayer electronic component, comprising: a step of preparing a laminate including a plurality of stacked insulating layers and a plurality of internal electrodes which are each disposed between the insulating layers and which include end portions exposed at predetermined surfaces of the laminate; and a step of forming external electrodes on the predetermined surfaces of the laminate such that the exposed end portions of the internal electrodes are electrically connected to each other; wherein the external electrode-forming step includes a plating sub-step of forming continuous plating layers on the predetermined surfaces of the laminate such that metal deposits are deposited on the exposed end portions of the internal electrodes and are then grown so as to be in contact with each other and a heat-treating sub-step of heat-treating the laminate having the plating layers, conditions of the heat-treating sub-step are selected such that interdiffusion layers in which a metal component included in the plating layers and a metal component included in the internal electrodes are both included are formed between the internal electrodes and the plating layers, and the interdiffusion layers extend between the internal electrode and the plating layers and have ends which face the internal electrodes and which are each located at a position about 0.5 μm to about 1.9 μm spaced apart from a corresponding one of the predetermined surfaces of the laminate.