Patent ID: 6275415
Filing Date: 2001-08-14
Classification: G11C

Abstract:
A method of programming a memory device comprising multiple banks of memory cells, each bank having multiple memory cells each having a control gate and a floating gate formed over a substrate and each having a source and a drain formed in the substrate, wherein the drains have a common drain terminal and wherein the sources have a common source terminal, the method comprising:selecting at least one bank of memory cells;applying a voltage to the common drain terminal;applying a time varying voltage to the control gates of memory cells that are to be programmed, wherein the voltage applied to the control gates of memory cells that are to be programmed is increased until a predetermined programming voltage is reached at which time the voltage applied to the control gates of memory cells that are to be programmed is removed; andapplying a bias voltage to the common source terminal, wherein the bias voltage applied to the common source terminal in combination with the voltage applied to the control gates of the memory cells that are to be programmed substantially prevents background leakage current during application of the voltage applied to the control gates and maintains programming speed.