Patent ID: 6552583
Filing Date: 2003-04-22
Classification: H01L

Abstract:
An integrated circuit (IC) with an output buffer with integrated electro-static-discharge (ESD) protection comprising:a pad for driving a signal from the IC to an external device; a p-channel driver transistor, having a p-gate node driven by core circuitry inside the IC to indicate when to drive the signal high, the p-channel driver transistor coupled to drive a pull-up current to the pad in response to the p-gate node; a first coupling capacitor for capacitivly coupling to the p-gate node an ESD pulse applied to the pad; a first resistor for discharging the ESD pulse coupled to the p-gate node by the first coupling capacitor; a first switch transistor, coupled to block current through the first resistor, for disconnecting current through the first resistor from the p-gate node when power is applied to the IC, but for enabling current flow through the first resistor from the p-gate node when the power is not applied to the IC; an n-channel driver transistor, having an n-gate node driven by the core circuitry inside the IC to indicate when to drive the signal low, the n-channel driver transistor coupled to drive a pull-down current to the pad in response to the n-gate node; a second coupling capacitor for capacitivly coupling to the n-gate node the ESD pulse applied to the pad; a second resistor for discharging the ESD pulse coupled to the n-gate node by the second coupling capacitor; and a second switch transistor, coupled to block current through the second resistor, for disconnecting current through the second resistor from the n-gate node when the power is applied to the IC, but for enabling current flow through the second resistor from the n-gate node when the power is not applied to the IC, whereby the ESD pulse is coupled to the gate rodes of the driver transistors when the power is not applied to the IC.