Patent ID: 7869343
Filing Date: 2011-01-11
Classification: H04L

Abstract:
1. An integrated circuit comprising: programmable logic device (“PLD”) core circuitry that implements a first-in/first-out (“FIFO”) memory for inputting blocks of user data at a first clock rate that is appropriate for user data without forward error correction (“FEC”) information, and for outputting blocks of user data at a second clock rate that is appropriate for user data with FEC information, the FIFO memory being programmable with respect to the number of blocks of data it can store; and dedicated, high-speed, hard intellectual property (“IP”) circuitry that includes FEC calculation and insertion circuitry for calculating FEC information for each block of user data output by the FIFO memory circuitry at the second clock rate, associating that FEC information with the user data, and outputting the user data and the associated FEC information at the second clock rate.