Patent ID: 6091121
Filing Date: 2000-07-18
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a semiconductor substrate of a first conductivity type;a first insulator film on said semiconductor substrate for confining a device region;a gate insulator film on said semiconductor substrate including said first insulator film;a gate electrode on said gate insulator film within said device region;a source region and a drain region of a second conductivity type opposite to said first conductivity type in said semiconductor substrate within said device region in self-alignment with said gate electrode;a sidewall insulator film on a side wall of said gate electrode;a source lead-out region and a drain lead-out region of said second conductivity type in said semiconductor substrate within said device region in self-alignment with said sidewall insulator film and said gate electrode;a protecting insulating film comprising at least one insulator film on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film; andan interlayer insulator film on the whole surface of said semiconductor substrate including said protecting insulating film for isolating said gate electrode from a metal interconnection on said interlayer insulator film,said protecting insulating film precluding moisture infiltration from an upper interlayer insulator film including at least said interlayer insulator film, and minimizing the stress of said protecting insulating film imparted to said gate insulator film,wherein said protecting insulating film comprises a multilayer film composed of a nitride film having a thickness of 10 nm to 20 nm and an oxide film having a thickness of 40 nm to 60 nm, which are deposited in the named order on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film.