Patent ID: 7589578
Filing Date: 2009-09-15
Classification: H03K

Abstract:
1. A level shift circuit comprising: a shift circuit for converting an input signal, which shifts between a reference voltage and a first voltage, to an output signal, which shifts between the reference voltage and a second voltage that is higher than the first voltage, the shift circuit including; a first N-channel MOS transistor having a drain, a source supplied with the reference voltage, and a gate for receiving the input signal; a second N-channel MOS transistor having a drain, a source supplied with the reference voltage, and a gate for receiving an inverted input signal, which is an inverted version of the input signal; a third N-channel MOS transistor having a drain, a source connected to the drain of the first N-channel MOS transistor, and a gate for receiving a bias voltage, wherein a first node is defined between the source of the third N-channel MOS resistor and the drain of the first N-channel MOS transistor; a fourth N-channel MOS transistor having a drain, a source connected to the drain of the second N-channel MOS transistor, and a gate for receiving the bias voltage, wherein a second node is defined between the source of the fourth N-channel MOS transistor and the drain of the second N-channel MOS transistor; and a voltage generation circuit for generating the bias voltage supplied to the shift circuit, the voltage generation circuit including; a control voltage generation circuit for generating a control voltage having a generally constant level irrespective of the level of the second voltage; and a bias generation circuit, connected to the control voltage generation circuit, for generating the bias voltage based on the comparison between a third voltage that is substantially equal to the voltages at the first and second nodes and the control voltage, wherein the control voltage generation circuit includes: wherein the bias generation circuit includes: wherein the first, second, fifth, and seventh N-channel MOS transistors are low breakdown voltage N-channel MOS transistors, and third, fourth, sixth, and eighth N-channel MOS transistors are high breakdown voltage N-channel MOS transistors.