Patent ID: 8598678
Filing Date: 2013-12-03
Classification: H01L

Abstract:
1. A parasitic vertical PNP bipolar transistor in a BiCMOS process with shallow trench isolation (STI) comprises: a collector being formed by a first active region with p-type ion implantation, which is a P type well of NMOS in the CMOS process; a p-type conductive layer being connected to a bottom of the collector; the p-type conductive layer is a p-type buried layer which is formed by a p-type ion implanting layer in a bottom of the shallow trench isolation (STI) around the collector; the p-type buried layer is connected with an adjacent second active region; the first active region and the second active region is connected through the p-type buried layer in the bottom of the shallow trench isolation (STI); the second active region with a p-type implantation layer is connected with a contact metal to form the collector; a base is formed on the collector by an n-type ion implanting layer and the n-type ion implanting layer is an N-type lightly doped drain (NLDD) implanting of NMOS; an emitter is formed by a p-type epitaxy layer above the base wherein the emitter is a base epitaxy layer of NPN transistor, and the emitter is connected by the contact metal; the base is connected by a heavily doped N-type polysilicon; and the base is connected by the contact metal above the heavily doped N-type poly-silicon.