Patent ID: 7812643
Filing Date: 2010-10-12
Classification: H03K

Abstract:
1. A current mode logic (CML) multiplexer circuit for implementing load balancing comprising: first and second differential transistor pairs; said respective transistors of said first and second differential transistor pairs being connected to respective differential signal first and second outputs; a first differential input signal being applied to a respective gate input of respective transistors of said first differential transistor pair; a second differential input signal being applied to a respective gate input of said second differential transistor pair; a respective select transistor being connected to said first and second differential transistor pairs, each respective select transistor receiving a respective gate select input; load balancing third and fourth differential transistor pairs; said first differential input signal and said second differential input signal being applied to a respective gate input of respective transistors of said load balancing third and fourth differential transistor pairs; said respective transistors of said load balancing third and fourth differential transistor pairs being connected to opposite differential signal first and second outputs as said first and second differential transistor pairs; and a respective load balancing select transistor being connected to said load balancing third and fourth differential transistor pairs; said select devices being turned off, and said load balancing third and fourth differential transistor pairs substantially matching a source impedance of an unselected one of said first and second differential transistor pair.