Patent ID: 7480200
Filing Date: 2009-01-20
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory array having memory cells of a plurality of dynamic random access memories arranged in rows and columns, and having a plurality of banks each forming a unit to be refreshed at a time; a circuit providing a trigger of refreshing; a bank select circuit selecting the bank different from the currently operating bank, and providing an address of the selected bank when the currently operating bank is performing an externally instructed operation at the time of reception of said refresh trigger; and a refresh control circuit refreshing the bank at said received address, wherein said bank select circuit includes: a register holding addresses of the refreshed banks, and erasing all the addresses held in the register when the addresses of all the banks are held, a determining circuit determining the addresses of the unrefreshed banks by referring to said register when said refresh trigger is received, and a comparing circuit comparing said address of the unrefreshed bank with the address of said currently operating bank, and providing the address of said unrefreshed bank when the address of the unrefreshed bank is different from the address of the currently operating bank.