Patent ID: 6671870
Filing Date: 2003-12-30
Classification: G01R

Abstract:
A computer implemented circuit synthesis system, comprising:memory configured to provide a database and operative to store a netlist including nets of an integrated circuit under design; a scan insertion tool to insert scan chains in an intergrated circuit under design, an automatic test pattern generation (ATPG) algorithm operative to test an integrated circuit design having scan chains; and processing circuitry configured to reduce layout area used during scan insertion and operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use a scan insertion tool to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both SI port and D port with a logical register.