Patent ID: 6108181
Filing Date: 2000-08-22
Classification: H01L

Abstract:
An electrostatic discharge (ESD) circuit for receiving a voltage at a node, the electrostatic discharge circuit integrated into an integrated circuit, the integrated circuit protected from ESD events by the ESD circuit, the electrostatic discharge circuit comprising:a first transistor further comprising a first current electrode, a second current electrode, and a control electrode, the first current electrode thereof coupled to receive a first voltage level, the second current electrode thereof coupled to the node;a second transistor further comprising a first current electrode, a second current electrode, and a control electrode, the second current electrode thereof coupled to the control electrode of the first transistor, the control electrode thereof coupled to the node;a third transistor further comprising a first current electrode, a second current electrode, and a control electrode, the first current electrode thereof coupled to the node, the second current electrode thereof coupled to receive a second voltage level, the control electrode thereof coupled to the control electrode of the first transistor; andan impedance device further comprising a first terminal and a second terminal, the first terminal thereof coupled to the node, the second terminal coupled to the integrated circuit to be protected.