Patent ID: 6054346
Filing Date: 2000-04-25
Classification: G11C,H01L

Abstract:
A method of fabricating a DRAM cell, comprising the steps of:forming a field oxide film on an isolation region of a semiconductor substrate to define an active region;sequentially forming a gate insulating film, a polysilicon layer, and a first insulating film on the active region;forming a gate pattern mask by selectively etching the first insulating film using a sensitivity film as a mask;forming first and second gates by selectively etching the polysilicon layer using the gate pattern mask;forming first, second and third impurity diffused regions in the active region using the field oxide film and the first and second gates as a mask;forming a storage electrode on a portion of the second impurity diffused region and the second gate;forming a dielectric layer on the storage electrode;forming an opposing electrode on the dielectric film and the third impurity diffused region;forming a first conductive line connected to the second gate;forming a second conductive line connected to the opposing electrode; andforming a third conductive line connected to the first impurity diffused region.