Patent ID: 6668348
Filing Date: 2003-12-23
Classification: G01R,G11C

Abstract:
A memory-mounting integrated circuit on which at least a built in self test (BIST) circuit and a memory are mounted, said BIST circuit comprising:data storing means for storing data in said memory for a memory test of said memory comparing means for comparing a memory test data signal for a memory region of said memory with corresponding data from said memory region of said memory stored by said data storing means for outputting a first comparing signal; control means for controlling outputting of defective data comprising said corresponding data and an address for said region of said memory outward from the integrated circuit based on said first comparing signal outputted by said comparing means, and halting said memory test until outward outputting of said defective data is complete; and output means for outputting said defective data outward from said integrated circuit as controlled by said control means.