Patent ID: 7996603
Filing Date: 2011-08-09
Classification: G06F

Abstract:
1. A memory controller for controlling a DRAM, comprising: a first generator that generates and transmits a signal indicative of a crowding level of a bus used for a data transfer with said DRAM; a refresh request unit configured to generate a reference signal with a predetermined generation period and to transmit a first refresh request and a second refresh request, said first refresh request being transmitted during said predetermined generation period, and said second refresh request being transmitted in response to the generation of the reference signal when a refresh operation of said DRAM has not been performed during the predetermined generation period; and an arbitrator that adjusts a time to perform the refresh operation of said DRAM based on said signal indicative of said crowding level input from said first generator, wherein said arbitrator instructs said DRAM to perform the refresh operation in response to said arbitrator receiving said second refresh request, and said arbitrator instructs said DRAM to perform the refresh operation when said arbitrator receives said first refresh request and when said signal indicative of said crowding level is not input.