Patent ID: 7843056
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. An integrated circuit package comprising: a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable epoxy, wherein the epoxy layer includes a topmost epoxy layer and at least one patterned epoxy layer; a first integrated circuit positioned within one of the epoxy layers and having an active surface, wherein at least the topmost epoxy layer extends over the active surface of the first integrated circuit; at least one interconnect layer, wherein each interconnect layer is embedded in an associated patterned epoxy layer and includes a plurality of interconnect traces and at least one via, wherein the at least one interconnect layer is sandwiched between layers of epoxy and is unexposed on the exterior of the integrated circuit package, whereby at least the topmost epoxy layer covers the at least one interconnect layer; and a component selected from a group consisting of an I/O pad exposed on the exterior of the integrated circuit package, a second integrated circuit having an active surface that is covered by one of the epoxy layers and that is positioned within one of the epoxy layers, and an electrical device that is embedded in one of the epoxy layers, wherein the first integrated circuit is electrically coupled to the component via the first interconnect layer.