Patent ID: 8305130
Filing Date: 2012-11-06
Classification: H03K

Abstract:
1. A MOS-type semiconductor clamping circuit, comprising: a pmos device coupled to a nmos device in series to form the clamping circuit to selectively clamp a signal to a reference voltage, the signal is configured to transition between a first voltage on a first side of the reference voltage and a second voltage on a second side of the reference voltage; wherein the pmos device and the nmos device each including a source, a drain and a gate, wherein the gate of the nmos device is configured to receive a first control signal and wherein the gate of the pmos device is configured to receive a second control signal and the second control signal is a logic inversion of the first control signal; and wherein when the signal transitions between the first voltage and the second voltage, the pmos device and the nmos device are subjected to a voltage differential that is less than the voltage difference between the first voltage and the second voltage by biasing the gate of the nmos device to be approximately the reference voltage using the first control signal when the signal is at or near the first voltage or by biasing the gate of the pmos device to be approximately the reference voltage using the second control signal when the signal is at or near the second voltage.