Patent ID: 6255848
Filing Date: 2001-07-03
Classification: H03K

Abstract:
A programmable logic device including:a plurality of configurable logic blocks connected by configurable interconnect resources;a configuration memory array including a plurality of configuration memory cells having output terminals coupled to the configurable logic blocks and the configurable interconnect resources such that portions of the configurable logic blocks and the configurable interconnect resources are controlled by configuration data stored in a corresponding configuration memory cell, the plurality of configuration memory cells including a first configuration memory cell;a first register including a first flip-flop for storing a first data bit value read from the first configuration memory cell;a second register including a second flip-flop for storing a second data bit value;a third register including a third flip-flop for storing a mask data bit value; anda multiplexing circuit connected between the first register and the second register, the multiplexing circuit being controlled by the third register such that when the mask data bit value is a first logic level, the second bit value is written into the first flip-flop, and when the mask data bit value is a second logic level, the first flip-flop retains the first data bit value.