Patent ID: 6333886
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A self refresh controlling apparatus comprising;a first buffering means for buffering a clock enable signal received from an external source to generate a self refresh completion control signal;a self refresh logic means for controlling activation of a clock buffer enable control signal by performing a self refresh operation depending on the state of the self refresh completion control signal from the first buffering means;a second buffering means receiving the clock buffer enable control signal for comparing a potential of an external clock signal with a reference potential to generate an internal clock signal;a delaying means for delaying the clock buffer enable control signal by a predetermined time;an internal clock signal activation controlling means for controlling activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delaying means and the internal clock signal; anda latching means for latching, in synchronization with the external clock signal, a command and an address buffered by the internal clock signal of which timing is adjusted at the internal clock signal activation controlling means.