Patent ID: 7548842
Filing Date: 2009-06-16
Classification: G06F

Abstract:
1. A method for verifying electronic circuit designs in anticipation of fabrication by simulation and emulation using a system comprising a host computer, a first evaluation unit and a second evaluation unit, each evaluation unit comprising: a plurality of evaluation processors, a single canvassing processor, one or more circuit signal value transfer circuits, one or more circuit signal value reading circuits, means for transferring circuit signal values among processors and means to transfer deterministically scheduled circuit signal values sent by a transfer circuit in the first evaluation unit to a reading circuit in the second evaluation unit; the method comprising: analyzing, using the host computer, a circuit description for inherent circuit signal value transfer activity among its elements, translating, using the host computer, the circuit description to evaluation processor instructions, assigning, using the host computer, the evaluation processor instructions to certain evaluation processors to optimize circuit signal value transfers, composing, using the host computer, canvassing processor instructions to ensure that results from certain evaluation processors are transferred to certain other evaluation processors according to the circuit description, scheduling, using the host computer, execution of evaluation processor instructions and canvassing processor instructions to avoid deadlock, and executing, using the evaluation units, the scheduled evaluation processor instructions and the scheduled canvassing processor instructions until all scheduled instructions are executed.