Patent ID: 9201655
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A processor implemented method for eliminating or reducing an operand line crossing penalty, the method comprising: performing an initial fetch for an operand from a data cache of a processor by permitting the initial fetch to complete unaligned with reference to a quadword boundary; storing all data from the initial fetch in an operand buffer as an output of the data cache; performing a plurality of subsequent fetches for a corresponding plurality of operands from the data cache wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines of the data cache, and each fetch fetches a number of bytes of data greater than a number of bytes of data returned to the processor in a single cycle; and merging and storing all of the data from the plurality of subsequent fetches with the data from the initial fetch in the operand buffer as an output of the data cache; and returning the stored and merged data in segments to the processor.