Patent ID: 8569822
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. A memory structure, comprising a memory cell comprising: a first dielectric layer, disposed on a substrate; a control gate, comprising: a base portion, disposed on the first dielectric layer; and a protruding portion, disposed on the base portion and exposing a portion of the base portion; a semiconductor layer, conformally disposed on the control gate and comprising: a top portion, disposed over the protruding portion; a bottom portion, disposed over the base portion exposed by the protruding portion; and a side portion, disposed at a sidewall of the protruding portion and connecting the top portion and the bottom portion; a first doped region and a second doped region, respectively disposed in the top portion and the bottom portion, wherein the side portion serves as a channel region; and a charge storage layer, disposed between the control gate and the semiconductor layer.