Patent ID: 9009577
Filing Date: 2015-04-14
Classification: H03M

Abstract:
1. A circuit for forward error correction (FEC) decoding, comprising: a decoding pipeline that includes a plurality of decoding stages and is configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding, a first set of FEC datagrams for correcting respective received words of the plurality of data symbols encoded with the RS FEC coding, and a second set of FEC datagrams for correcting respective received words of the plurality of data symbols encoded with the second FEC coding, each decoding stage configured to: a post-processing circuit coupled to an output of the decoding pipeline and configured to, in response to one of the second set of FEC datagrams indicating one of the respective received words of the plurality of data symbols encoded with the second FEC coding includes data symbols in error, perform bitwise RS decoding of ones of the plurality of data symbols in error by performing operations including: