Patent ID: 6633992
Filing Date: 2003-10-14
Classification: G06F,H03K

Abstract:
A device comprising:a first inverter having an input and an output, the input of the first inverter being coupled to a clock signal; a latch having an input, a control input, and an output, the input of the latch being coupled to an input of the device and the control input of the latch being coupled to the output of the first inverter; a clock circuit having first, second, third inputs and a first, second outputs, the first input of the clock circuit being coupled to the output of the latch, the second input of the clock circuit being coupled to the output of the first inverter, and the third input of the clock circuit being coupled to the clock signal; a second inverter having an input and an output, the input of the second inverter being coupled to the output of the latch; a logic AND-gate having a first input, a second input, and an output, the first input of the logic AND-gate being coupled to the output of the second inverter and the second input of the logic AND-gate being coupled to the first output of the clock circuit; and a circuit having first, second, third inputs and an output, the first input of the circuit being coupled to the output of the logic AND-gate, the second input of the circuit being coupled to a data input, and the third input of the circuit being coupled to the second output of the clock circuit.