Patent ID: 8307325
Filing Date: 2012-11-06
Classification: G06F

Abstract:
1. A design method of a semiconductor integrated circuit including a first wiring layer, a second wiring layer formed on the first wiring layer, and a third wiring layer formed on the second wiring layer, the method using a design apparatus, the method comprising: arranging plural spare wirings on the second wiring layer along a first direction using the design apparatus, and arranging plural spare wirings on the third wiring layer along a second direction orthogonal to the first direction using the design apparatus; arranging cells on the first wiring layer after the arrangement of the spare wirings using the design apparatus; arranging a signal wiring using the design apparatus, signal wirings on at least any one of the first to third wiring layers to connect the cells via the signal wiring, and creating circuit diagram data after the arrangement of the cells; and performing an engineering change order by replacing at least one of the spare wirings on the second wiring layer or the third wiring layer by signal wirings to connect the cells via the signal wirings, and correcting the circuit diagram data wherein the spare wirings are not used before the engineering change order is performed.