Patent ID: 8467263
Filing Date: 2013-06-18
Classification: G11C

Abstract:
1. An apparatus comprising: memory cells on a wordline; and a driver circuit coupled to the wordline to couple the wordline to a ground reference for a de-asserted state and to initially couple the wordline to a supply reference and then to float the wordline to capacitively boost the wordline for a write operation, wherein the driver circuit comprises a P-type and an N-type transistor coupled to the wordline, wherein the P-type transistor is operable to couple the wordline to the supply reference during another state, wherein the N-type transistor is operable to couple the wordline to the ground reference during the de-asserted state, wherein the P-type and N-type transistors are operable to float the wordline, wherein the P-type and N-type transistors have inputs controllably coupled to one another through a switch to cause the wordline to be in a floating state, and wherein the switch is a transfer gate formed from N-type and P-type transistors.