Patent ID: 6147996
Filing Date: 2000-11-14
Classification: H04L

Abstract:
A packet switch comprisinga fetch engine coupled to a source of packet headers;a plurality of fetch caches coupled to said fetch engine, and disposed to store at least portions of packet headers received therefrom;a plurality of switch engines, each coupled to a corresponding one of said fetch caches, and disposed to read said portions of packet headers therefrom;a plurality of reorder/rewrite buffers, each said reorder/rewrite buffer coupled to one of said switch engines, and disposed to store pointers to packet headers received from at least one of said plurality of switch engines;a reorder/rewrite engine coupled to said plurality of reorder/rewrite buffers, and disposed to read pointers to packet headers therefrom in an order said packet headers were originally received;a post-process queue coupled to said reorder/rewrite engine, and disposed to store pointers to packet headers received therefrom; anda post-process engine coupled to said post-process queue, and disposed to process said packet headers.