Patent ID: 7990778
Filing Date: 2011-08-02
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory, comprising: a nonvolatile memory array; a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a trimming code; a control circuit that applies the generated drive voltage to the nonvolatile memory array; and a trimming code output circuit that outputs any one of a plurality of trimming codes to the voltage generator circuit, wherein the plurality of trimming codes includes: wherein, in the test state, the trimming code output circuit outputs the test trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the test trimming code, and wherein, in a case other than the test state, the trimming code output circuit outputs the appropriate trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the appropriate trimming code.