Patent ID: 9086883
Filing Date: 2015-07-21
Classification: G06F,H04L,Y02D

Abstract:
1. A method of performing dynamic clock and voltage scaling on a multiprocessor system having two or more processor cores, the method comprising: receiving a first set of information from a first processor core, the first information set including information regarding at least one of a frequency, time, busy periods, idle periods and wait periods of the first processor core; receiving a second set of information from a second processor core, the second information set including information regarding at least one of a frequency, time, busy periods, idle periods and wait periods of the second processor core; synchronizing the first and second information sets; correlating the synchronized first and second information sets to identify an interdependence relationship between operations of the first processor core and operations of the second processor core; and scaling the frequency or a voltage of the first processor core and scaling the frequency or a voltage of the second processor core according to a correlated information set when an interdependence relationship is identified between the operations of the first processor core and the operations of the second processor core, wherein scaling the frequency or the voltage of the first processor core and scaling the frequency or the voltage of the second processor core according to the correlated information set comprises: