Patent ID: 6993108
Filing Date: 2006-01-31
Classification: H03L,H04J,H04L

Abstract:
1. A digital filter of a DPLL (Digital Phase locked loop) comprising: a first reloadable register portion for storing a TBW (total bandwidth) value, wherein said first reloadable register portion is capable of being coupled to a first port for inputting said TBW value that is programmed into said first reloadable register portion through said first port; a second reloadable register portion for storing a DBW (differential bandwidth) value, wherein said second reloadable register portion is capable of being coupled to a second port for inputting said DBW value that is programmed into said second reloadable register portion through said second port; an up a down an adder for adding said UP a subtractor for generating a DELTA value that is the difference between said UP a delta comparator for asserting a LTP (larger than positive) signal if the magnitude of said DELTA value is greater than said DBW value and if said DOWN a sum comparator for asserting a WE (write enable) signal when said SUM value is greater than said TBW value; and a phase select controller for asserting a FWD (forward) signal if said LTP signal is asserted when said WE signal is asserted or for asserting a BWD (backward) signal if said STN signal is asserted when said WE signal is asserted; wherein said phase selector selects another clock signal having a leading phase from said current ACLK signal as a new ACLK (recovered clock) signal when said FWD signal is asserted; and wherein said phase selector selects another clock signal having a lagging phase from said current ACLK signal as said new ACLK (recovered clock) signal when said BWD signal is asserted; and wherein said phase selector selects said current ACLK signal to remain as said new ACLK (recovered clock) signal if said FWD signal and said BWD signal are not asserted when said WE signal is asserted.