Patent ID: 6414878
Filing Date: 2002-07-02
Classification: G06F,G11C,H01L

Abstract:
A semiconductor integrated circuit device on a semiconductor chip comprising an address bus, a data bus, a central processing unit (CPU) coupled to said address bus and to said data bus and capable of processing data of a plurality of bits, and a flash memory coupled to said address bus and to said data bus and comprising:a plurality of memory cells each comprising a control gate, a drain and a source, wherein said memory cells are arranged to be simultaneously erasable; a plurality of memory arrays, being responsive to accessing from said CPU via said address bus and providing, from a plurality of data stored therein, one data item of a plurality of bits to said CPU via said data bus in a manner in which each memory array outputs one bit of said plurality of bits constituting said one data item; a plurality of sense amplifiers having outputs coupled to said data bus and arranged so that each sense amplifier is coupled to one of said plurality of memory arrays; a plurality of word lines coupled to the control gates of said memory cells and a plurality of data lines coupled to the drains of said memory cells in a manner in which each memory cell is coupled to one word line and to one data line, wherein each word line is used in common for said plurality of memory arrays, and each memory array includes different data lines; a plurality of common data lines coupled to the sense amplifiers, so that one common data line is coupled to one sense amplifier; selection switches coupled between the data lines and the common data lines in a manner in which the data lines included in a memory array are coupled to a corresponding common data line through the corresponding selection switches; a decoder circuit coupled to said selection switches, responsive to the accessing from said CPU and providing one selection signal to ones of said selection switches in a manner in which a selected data line in each of the memory arrays is coupled to the corresponding common data line; a plurality of source lines, wherein the memory cells which are coupled to the same word line have the sources thereof coupled in common to one source line to form one of a plurality of memory blocks for an erasing operation, each memory block including the memory cells corresponding to at least one word line; and a plurality of source voltage control circuits provided for said memory blocks, wherein one source voltage control circuit is coupled to the source line in one memory block and is capable of providing a predetermined potential to the source line in that memory block for effecting the simultaneous erasure of the memory cells included therein, in the erasing operation.