Patent ID: 7296248
Filing Date: 2007-11-13
Classification: G06F

Abstract:
1. A method of generating a parameterized cell of a semiconductor device layout, comprising: performing a compiling interpretation on a structure layout of a semiconductor device, wherein the compiling interpretation includes i) determining and analyzing shape relationships of the structure layout, and ii) mapping shapes and calculating properties of mapped shapes; and generating code in response to the compiling interpretation, wherein the generated code is representative of one or more parameterized cells of a pcell library of an electronic design automation software program and further for semiconductor process development in which a number of device variations are used to test and model new semiconductor processes, wherein determining and analyzing shape relationships of the structure layout includes determining shape relationships and generating an ordered shape tree based upon the determined shape relationships, wherein determining shape relationships includes for each shape, comparing the shape to one or more other shapes within the structure layout and identifying one or more relative relationships between shapes.