Patent ID: 6605969
Filing Date: 2003-08-12
Classification: G11C,H03L

Abstract:
A delay-locked loop, comprising:a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal; a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal; a feedback delay line coupled to the mode delay line and operable to generate a feedback clock signal responsive to the mode delayed clock signal, the feedback clock signal having a model delay relative to the mode delayed clock signal; and a comparison circuit configured to receive the input clock signal and coupled to the feedback delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the input and feedback clock signals.