Patent ID: 8338260
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. A method for fabricating a transistor, the method comprising: forming a gate stack on a silicon layer that is above a buried oxide layer, the gate stack comprising a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer; forming a first nitride layer on the silicon layer and the gate stack; forming an oxide layer on the first nitride layer; forming a second nitride layer on the oxide layer; etching the first nitride layer and the oxide layer so as to form a nitride liner and an oxide liner adjacent to the gate stack; etching the second nitride layer so as to form a first nitride spacer adjacent to the oxide liner; epitaxially forming a faceted raised source/drain region adjacent to the nitride liner, the oxide liner, and first nitride spacer, wherein the faceted raised source/drain region comprises a first faceted side portion and a second faceted side portion wherein each of the first and second faceted side portions is angled with an angle from 5 degrees to 85 degrees relative to a bottom surface of the faceted raised source/drain region, and wherein the epitaxially forming further comprises implanting ions into the faceted raised source/drain region using the first nitride spacer to align the implantation.