Patent ID: 6674679
Filing Date: 2004-01-06
Classification: G11C

Abstract:
A sensing circuit for determining the logic state of a selected memory cell in a Resistive memory array, the logic state of the memory cell being determined relative to a reference cell having a pre-selected logic state, comprising:(a) a memory cell sensing circuit adapted to determine a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and to determine a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell, (b) a reference cell sensing circuit adapted to determine a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and to determine a second reference cell voltage associated with the reference cell when the second bias voltage is impressed on the reference cell, (c) an equi-potential isolation circuit for applying a substantially equal voltage to both sides of each unselected memory cell; (d) an adjusting circuit for modifying at least one of (i) the first memory cell voltage and (ii) the first reference cell voltage to make the first memory cell voltage approximately equal to the first reference cell voltage at the first bias voltage, and (e) a state determining circuit for determining the difference between the second memory cell voltage and the second reference cell voltage in order to determine the logic state of the memory cell at the second bias voltage.