Patent ID: 7533251
Filing Date: 2009-05-12
Classification: G06F

Abstract:
1. A semiconductor integrated circuit, comprising: a CPU which operates such that a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted; a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section, wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein when the fourth signal is asserted, the memory content of the stack memory is initialized, and wherein: