Patent ID: 7757133
Filing Date: 2010-07-13
Classification: G11C

Abstract:
1. An integrated circuit comprising: a plurality of memory arrays implemented on the integrated circuit, wherein one or more of the plurality of memory arrays has a physical organization that is different with respect to other ones of the plurality of memory arrays; a memory built-in self-test (MBIST) controller implemented on the integrated circuit and configured to test each of the plurality of memory arrays, wherein the MBIST controller is configured to generate a first logical address sequence for a test of a first one of the plurality of memory arrays, and wherein the MBIST controller is programmable to permute bits of each logical address of the first logical address sequence to produce a first physical address sequence depending on a type of test conducted and a physical organization of the first memory array; wherein the MBIST controller is further configured to generate a second logical address sequence for a test of a second one of the plurality of memory arrays, and wherein the MBIST controller is programmable to permute bits of each logical address of the second logical address sequence to produce a second physical address sequence depending on a type of test conducted and a physical organization of the second memory array, wherein the physical organization of the second memory array is different from the physical organization of the first memory array.