Patent ID: 8952498
Filing Date: 2015-02-10
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a substrate on which a plurality of substrate terminals including a plurality of substrate power supply terminals are provided; a first semiconductor chip stacked on the substrate, the first semiconductor chip having one surface on which a plurality of first chip terminals each connected to an associated one of the substrate terminals are provided and the other surface on which a plurality of second chip terminals including a plurality of chip power supply terminals and a plurality of chip signal terminals are provided; and a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having one surface on which a plurality of third chip terminals each connected to an associated one of the second chip terminals are provided, wherein the first semiconductor chip has a plurality of power supply penetration electrodes each penetrating through the first semiconductor chip and electrically connecting an associated one of the chip power supply terminals to an associated one of the substrate power supply terminals, each of the power supply penetration electrodes is vertically aligned with the associated one of the chip power supply terminals and the associated one of the substrate power supply terminals, and the chip signal terminals have an arrangement pitch smaller than an arrangement pitch of the chip power supply terminals.