Patent ID: 7475317
Filing Date: 2009-01-06
Classification: G01R

Abstract:
1. A method of generating digital test sets for use with a testing device for testing a number of wiring interconnects, each test set comprising a matrix of bits, which matrix defines a first plurality of test patterns and a second plurality of code words, wherein the bits of each test pattern are for application to respective wiring interconnects in parallel with one another, and the bits of successive test patterns for application to an interconnect form a code word for that interconnect, and wherein each code word has a transition count related to a number of bit value transitions therein, the test set having a total transition count related to the sum of the transition counts of the code words in the test set, the method comprising the steps of: generating a test set of said test sets which has a total transition count which is less than a predetermined threshold value, the predetermined threshold value having a predetermined relationship with the number of test patterns in the test set; the step of generating the test set including, the test set includes at most test patterns, with b being the length of the code words in the test set, τ tot (b) being the total transition count, and s being a simultaneous switching output limit for the wiring interconnects.