Patent ID: 7974030
Filing Date: 2011-07-05
Classification: G11B

Abstract:
1. A dibit correction circuit, the circuit comprising: a dibit sample buffer, wherein the dibit sample buffer is operable to store a plurality of samples of an uncorrected dibit signal; a maximum sample detector circuit, wherein the maximum sample detector circuit is operable to identify a maximum sample of the plurality of samples of the uncorrected dibit signal; a side sample detector circuit, wherein the side sample detector circuit is operable to identify a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal; and a dibit correction circuit, wherein the dibit correction circuit is operable to apply a correction factor calculated based at least in part on the maximum sample, the first side sample and the second side sample to at least a subset of the plurality of samples of the uncorrected dibit signals to yield a plurality of corrected dibit signals.