Patent ID: 7893517
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate having a trench; a well layer having a first conductivity type and formed in the semiconductor substrate; a block layer formed in the trench of the well layer and formed of an insulating layer, the block layer having a linear shape when viewed from a main surface of the semiconductor substrate; a gate electrode formed on the semiconductor substrate apart from the block layer, the block layer extending parallel to the gate electrode; a first diffusion layer having a second conductivity type, formed in a surface of the well layer, and having a high concentration region of an impurity concentration to a first depth from a surface of the semiconductor substrate; a second diffusion layer having the second conductivity type, formed in the surface of the well layer on a side of the block layer away from the gate electrode, having a high concentration region of an impurity concentration to a second depth greater than the first depth from the surface of the semiconductor substrate, and electrically connected to the first diffusion layer in contact therewith, the first diffusion layer is separated from the second diffusion layer by the well layer under a bottom of the block layer; and a contact connected to the second diffusion layer.