Patent ID: 7685372
Filing Date: 2010-03-23
Classification: G06F

Abstract:
1. A digital system that connects to a bus, wherein the bus employs a first address domain, the digital system comprising: a processing core that generates a first cache coherence signal and a second cache coherence signal; a level one (L1) cache that communicates with the processing core and that generates a first signal based on the first cache coherence signal; a level two (L2) cache buffer; a L2 cache that communicates with the L1 cache, wherein each of the processing core, the L1 cache, and the L2 cache employs a second addressing domain, and wherein the processing core directly provides the first cache coherence signal to the L1 cache when the processing core directly provides the second cache coherence signal to the L2 cache; and a bus unit that communicates with the L2 cache and with the bus, wherein the bus unit employs the first addressing domain, wherein the bus unit generates a second signal based on the second cache coherence signal, wherein the L2 cache provides a third signal based on the first cache coherence signal, wherein the L2 cache buffer provides a fourth signal based on the second cache coherence signal, and wherein the processor receives a first logical combination of the first and third signals and receives a second logical combination of the second and fourth signals.