Patent ID: 6239035
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A process for the manufacture of semiconductor integrated circuit wafers comprising the steps of:a. forming a first dielectric layer on a semiconductor substrate,b. depositing a first conductive layer on said first dielectric layer,c. photolithographically masking said first conductive layer using a photomask,d. etching away portions of said first conductive layer exposed by said photomask to pattern said first conductive layer, said portions including a peripheral region of said first conductive layer around the perimeter of the wafer thereby forming a peripheral edge of said first conductive layer spaced from the edge of said wafer, said peripheral region having a dimension S.sub.a, as measured from the edge of the wafer along the diameter of the wafer to the peripheral edge of the first conductive layer,e. depositing a second dielectric layer over the patterned first conductive layer,f. photolithographically masking said second dielectric layer using a photomask,g. etching away portions of said second dielectric layer exposed by said photomask to pattern said second dielectric layer, said portions including a peripheral region of said second dielectric layer around the perimeter of the wafer, said peripheral region having a dimension S.sub.2, as measured from the edge of the wafer along the diameter of the wafer to the peripheral edge of said second dielectric layer,h. depositing a second conductive layer over the patterned second dielectric layer,i. photolithographically masking said second conductive layer using a photomask,j. etching away portions of said second conductive layer exposed by said photomask to pattern said second conductive layer, said portions including a peripheral region of said second conductive layer around the perimeter of the wafer thereby forming a peripheral edge of said second conductive layer spaced from the edge of said wafer, said peripheral region having a dimension S.sub.b, as measured from the edge of the wafer along the diameter of the wafer to the peripheral edge of the second conductive layer,k. depositing a third dielectric layer over the patterned second conductive layer, said third dielectric layer extending over the said peripheral edge of the second conductive layer,said dimensions S.sub.a, S.sub.b, and S.sub.2, being related by S.sub.a >S.sub.b >S.sub.2 so that the step height in the third dielectric layer is no greater than the thickness of the second conductive layer.