Patent ID: 8981457
Filing Date: 2015-03-17
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a substrate; a first contact located over the substrate; a first vertical semiconductor pillar located over the first contact, a first end of the first vertical semiconductor pillar contacting the first contact; a second contact located over the first vertical semiconductor pillar, wherein a second end of the first vertical semiconductor pillar contacts the second contact; a second vertical semiconductor pillar located horizontally adjacent to the first vertical semiconductor pillar in a first row over the substrate; a third vertical semiconductor pillar located horizontally adjacent to the first vertical semiconductor pillar in a second row different from the first row over the substrate; third contacts coupling to the second vertical semiconductor pillar; fourth contacts coupling to the third vertical semiconductor pillar; a first charge storage region located adjacent to a first portion of a first side of the first vertical semiconductor pillar; a second charge storage region located adjacent to a second portion of the first vertical semiconductor pillar above the first portion of the first vertical semiconductor pillar, wherein the first and second charge storage regions are two portions of a single contiguous material layer vertically extending from the first end of the first vertical semiconductor pillar to the second end of the first vertical semiconductor pillar; a first control gate located adjacent to the first charge storage region; a second control gate located adjacent to the second charge storage region; a first tunneling dielectric layer located between the first side of the first vertical semiconductor pillar and the first charge storage region, between a bottom of the first charge storage region and the first contact, and between the first contact and the first control gate; a first blocking dielectric layer located between the first charge storage region and the first control gate, and between the first contact and the first control gate; and driver circuitry associated with the operation of the memory device; wherein the first control gate is located entirely above the first contact; wherein the first vertical semiconductor pillar comprises a first conductivity type semiconductor region in the first end, another first conductivity type region in the second end, and a second conductivity type region between the first conductivity type regions; wherein the first conductivity type regions comprise n-type regions and the second conductivity type region comprises a p-type region; and wherein the first control gate is shared between the first vertical semiconductor pillar, the second vertical semiconductor pillar and the third vertical semiconductor pillar.