Patent ID: 6168998
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A dual gate MOSFET fabrication method comprising the steps of: forming a first insulation layer on a semiconductor substrate; forming a first polysilicon layer on the first insulation layer; forming a first photoresist pattern on the first polysilicon layer; forming a first gate by sequentially etching the first polysilicon layer and the first insulation layer by using the first photoresist pattern as a mask; removing the first photoresist pattern; forming a second insulation layer on the semiconductor substrate and the first gate; forming a second polysilicon layer on the second insulation layer; forming a second photoresist pattern on the second polysilicon layer; and forming a second gate by etching the second polysilicon layer and the second insulation layer by using the second photoresist pattern as a mask,wherein a thickness of the first gate is the same as a thickness of the second gate, and wherein, after the second insulation layer is etched, it covers a top surface of the first gate and sides of the first gate.