Patent ID: 6992935
Filing Date: 2006-01-31
Classification: G11C,H03K

Abstract:
1. A nonvolatile memory device comprising a data latch circuit for holding and outputting program information used for a peripheral circuit, wherein said data latch circuit includes: a plurality of program sections each for receiving a data writing current according to corresponding one of program data constituting said program information to perform nonvolatile data storage; and a latch circuit for holding a data signal generated by a selected program section among said plurality of program sections at the time of data reading, wherein said latch circuit includes: a first current supply section for supplying an operating current in accordance with the voltage level of a first holding node to a second holding node; and a second current supply section for supplying an operating current in accordance with the voltage level of said second holding node to said first holding node, each of said program sections includes first and second storage elements having different electric resistances from each other on the basis of said data writing currents in accordance with said program data, at the time of said data reading, said first and second current supply sections connected to a first voltage are electrically coupled in series to said first and second storage elements connected to a second voltage in said selected program section, respectively, each of said program sections further includes a resistance element, connected in series to one of said first and second storage elements, having a fixed electric resistance, and each of said first and second storage elements has a same resistance value in initial state.