Patent ID: 6185652
Filing Date: 2001-02-06
Classification: G06F

Abstract:
An interrupt handling mechanism for use with a computer-based system in which an interrupt generator issues interrupt requests that are serviced by an interrupt handler, comprising:a group of ordered operations sent by the interrupt handler to the interrupt generator for execution;the interrupt generator being configured to execute the ordered operations and issue an interrupt request following execution of a predetermined number of the ordered operations, the predetermined number ranging from one to all of the operations;an interrupt tabulator including at least one of:an interrupt counter that stores an interrupt count that is incremented by the interrupt handler each time the interrupt request is issued; andan interrupt address register in which the interrupt generator writes an interrupt address associated with a respective operation whose execution caused the interrupt request to be issued; whereinthe interrupt handler is configured, whenever the interrupt handler services the interrupt generator, not necessarily in response to the interrupt request, to read the interrupt tabulator to determine processing status of interrupt generator, including:when the interrupt tabulator incorporates the interrupt counter, reading the interrupt count;when the interrupt tabulator incorporates the interrupt address register, reading the interrupt address; andbased on the processing status of the interrupt generator, the interrupt handler is configured to determine which of the ordered operations are still pending for execution by the interrupt generator and to, as a result, send an additional group of ordered operations to the interrupt generator in order to keep the interrupt generator as busy as possible.