Patent ID: 8643402
Filing Date: 2014-02-04
Classification: H03D,H03L

Abstract:
1. A circuit comprising: an edge detector circuit configured to receive a first signal and a second signal, and provide at least one edge detector output signal; a first phase frequency detector sub-circuit configured to receive the at least one edge detector output signal and provides at least one first phase frequency output signal; a second phase frequency detector sub-circuit configured to receive the at least one edge detector output signal and provide at least one second phase frequency output signal; a decision circuit configured to receive signals of the at least one first phase frequency output signal, signals of the at least one second phase frequency output signal, and signals of the at least one edge detector output signal, and provide at least one decision output signal; and a phase frequency detector output circuit configured to receive the at least one first phase frequency output signal and the at least one second phase frequency output signal, and provide a pair of output signals, wherein