Patent ID: 6252280
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A semiconductor device comprising:an SOI substrate having a multilayer structure with a semiconductor substrate, an insulating layer, and a semiconductor layer stacked in this order;a first element isolation insulation film formed in an upper surface of said semiconductor layer to a predetermined depth that does not reach an upper surface of said insulating layer, in an element isolation region of said SOI substrate;a gate insulation film formed on said upper surface of said semiconductor layer in an element forming region of said SOI substrate;a gate electrode formed on said gate insulation film and said first element isolation insulation film;an interlayer insulation film formed on said gate electrode and said first element isolation insulation film; anda contact hole filled with a conductor, which is selectively formed in an upper surface of said interlayer insulation film, extending through said interlayer insulation film and said first element isolation insulation film to said upper surface of said semiconductor layer in said element isolation region of said SOI substrate, said conductor being in contact with said gate electrode on said first element isolation insulation film.