Patent ID: 8017464
Filing Date: 2011-09-13
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a plurality of gate structures of MISFET including a polysilicon gate electrode over a first main surface of a semiconductor wafer; (b) forming a source/drain region near both sides of respective gate structures of the first main surface of the semiconductor wafer; (c) after the steps of (a) and (b), siliciding an upper surface of the source/drain region; (d) forming an etch stop film over the first main surface of the semiconductor wafer including the silicided upper surface of the source/drain region; (e) forming a first silicon oxide film, which is a part of a pre-metal interlayer insulating film, by thermal CVD using ozone and TEOS over the etch stop film; (f) etching the first silicon oxide film to expose the etch stop film over the respective gate structures; (g) after the step (f), forming a second silicon oxide film, which is a part of the pre-metal interlayer insulating film, by plasma CVD using TEOS at a portion where the etch stop film is exposed and a portion where the first CVD silicon oxide film remains; and (h) performing a first chemical mechanical polishing treatment for the upper surface of the second silicon oxide film.