Patent ID: 7566899
Filing Date: 2009-07-28
Classification: H01L

Abstract:
1. A thin-film transistor backplane circuit comprising: a substrate; a dielectric layer formed on the upper surface of the substrate; a plurality of thin-film transistors formed on the dielectric layer, each of the thin-film transistors including a drain contact structure, a source contact structure, and an organic semiconductor region disposed between the source and drain contact structures; a plurality of readout amplifiers disposed adjacent to said plurality of thin-film transistors; and a plurality of address lines formed on the dielectric layer, each address line connecting the drain contact structures of a column of said plurality of thin-film transistors with an associated readout amplifier of said plurality of readout amplifiers, wherein each of the plurality of address lines extending from said column of said plurality of thin-film transistors to said associated read-out amplifier and the source and drain contact structures of each of the plurality of transistors respectively comprise a multi-layer structure including a base portion and a contact layer,