Patent ID: 6455375
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A method of fabricating a tunnel oxide window for use in an EEPROM memory cell comprising:implanting a PRJ region in a semiconductor substrate; forming a tunnel oxide layer on the top surface of the PRJ region; forming a floating gate electrode over the tunnel oxide on the top surface of the PRJ region; implanting a first type of impurity ions into the PRJ region on a first side of the gate electrode with said gate electrode acting as a mask so as to form an N-type lightly-doped drain region; implanting a second type of impurity ions into the PRJ region on a second side of the gate electrode with said gate electrode acting as a mask so as to form a P-type lightly-doped drain region; forming first and second sidewall spacers on the respective first and second sides of the gate electrode; implanting said first type of impurity ions into the PRJ region on the first side of the gate electrode with said gate electrode and said first sidewall spacer acting as a mask so as to form a highly-doped N+ diffusion region; and implanting said second type of impurity ions into the PRJ region on the second side of the gate electrode with said gate electrode and said second sidewall spacer acting as a mask so as to form a highly-doped P+ contacted inversion layer.