Patent ID: 8874879
Filing Date: 2014-10-28
Classification: G06F

Abstract:
1. A vector processing circuit comprising: a vector register file including a plurality of array elements; a command issuance control circuit configured to issue commands including a preceding command and a subsequent command following the preceding command; and a plurality of pipeline arithmetic units each configured to perform, in response to one of the commands, arithmetic processing of data stored in the array elements indicated as a source by the one of the commands in parts through a plurality of cycles and to store a result of the arithmetic processing in the array elements indicated as a destination by the one of the commands in parts through a plurality of cycles, wherein the command issuance control circuit is further configured to perform operations to: determine, when the data word length of the preceding command is equal to the data word length of the subsequent command, whether the second register interference exists to adjust an issuance timing of the subsequent command based on the determination result of the second register interference.