Patent ID: 6577544
Filing Date: 2003-06-10
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory mat having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; and an address comparing circuit enabled to store high and low logical values and a don't care value, said address comparing circuit being comprised of a first inverter, first and second P-channel MOS transistors, a plurality of first N-channel MOS transistors and a first plurality of bit comparing circuits, wherein said first N-channel MOS transistors are coupled in series via source/drain paths thereof, the series coupling of said first N-channel MOS transistors being between a first node and a reference terminal, wherein said first and second P-channel MOS transistors are coupled in parallel, via source/drain paths thereof, between a voltage terminal and said first node, wherein said first inverter has an input coupled to said first node and an output coupled to a gate of said second P-channel MOS transistor, and wherein each of said first plurality of bit comparing circuits has an output coupled to a gate of a respective one of said first N-channel MOS transistors.