Patent ID: 6265282
Filing Date: 2001-07-24
Classification: H01L,Y10T

Abstract:
A process for forming an isolation structure having quarter (0.25) micron or smaller dimensions for enhanced electrical isolation of devices, the process comprising:providing a semiconductor layer;forming conductive regions in said semiconductor layer;forming a recess in said semiconductor layer between said conductive regions, said recess having a sidewall and a bottom surface, the bottom surface having a width as measured across the bottom surface of less than or equal to 0.25 microns;oxidizing at least a substantial portion of said semiconductor layer adjacent to said recess to provide a first dielectric layer, said first dielectric layer formed using high-pressure oxidation, said first dielectric layer encroaching into said conductive regions; andat least substantially filling said recess with at least a portion of a second dielectric layer,whereby the isolation structure having quarter micron or smaller dimensions is formed, said isolation structure providing enhanced electrical isolation and reducing the probability of subthreshold voltage transistor leakage.