Patent ID: 6160317
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A semiconductor device comprising:a core area having a first plurality of spacers with a first thickness which has been etched, the core area also including at least one gate stack;a peripheral area with a second plurality of spacers which has been etched and at least one electronic sensitive device (ESD) transistor, the second plurality of spacers having a second thickness, wherein the second thickness is not equal to the first thickness, the first plurality of spacers and the second plurality of spacers each including a first spacer layer and a second spacer layer, the first plurality of spacers and the second plurality of spacers being formed by depositing the first spacer layer over the core area and the peripheral area, etching the first spacer layer in the core area to form the first plurality of spacers in the core layer, depositing the second spacer layer over the core area and the peripheral area, etching the second spacer layer in the peripheral area to form the second plurality of spacers without etching the second spacer layer in the core area.