Patent ID: 8268685
Filing Date: 2012-09-18
Classification: H01L

Abstract:
1. A method of manufacturing a NAND flash memory device having a plurality of memory cells connected in series between a drain select transistor and a source select transistor, the method comprising: recessing a gate formation region of a semiconductor substrate to form at least one recess for a recessed gate of at least one of the source select transistor or the drain select transistor; depositing a tunnel oxide film in the at least one recess and over the semiconductor substrate at locations of gates of the plurality of memory cells, wherein the tunnel oxide film formed in the at least one recess extends below the tunnel oxide film formed at the locations of gates of the plurality of memory cells; depositing a polysilicon film for a floating gate over the tunnel oxide film and within the at least one recess for at least one of the drain select transistor or the source select transistor; depositing a hard mask on the polysilicon film; patterning the hard mask and then etching the polysilicon film for the floating gate and the tunnel oxide film using the patterned hard mask as an etch mask, forming trenches for forming isolation films; gap-filling the insides of the trenches with an oxide film and then polishing the entire surface to form the isolation films; and forming a dielectric film and a conductive film for a control gate on the polished surface.