Patent ID: 6388282
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A semiconductor memory device comprising:a transistor having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate; a first interlayer insulating film covering the transistor and having contact holes leading to the source region and the drain region, respectively; a bit line contact formed in one of the contact holes; a storage node electrode contact formed in the other of the contact holes; a bit line contact plug formed on the bit line contact; a storage node electrode contact plug comprising a first barrier metal layer formed on the storage node electrode contact and a first metal lay formed on the first barrier metal layer; a second interlayer insulating film formed on the first interlayer insulating film, the storage node electrode contact plug and a bit line contact plug being provided in the second interlayer insulating film; a first sidewall insulating film surrounding the first metal layer, and a material of the first sidewall insulating film being different from a material of the second interlayer insulating film; a bit line connected to the bit line contact plug; and a storage node electrode of a capacitor, connected to the storage node electrode contact plug, wherein the first barrier metal layer is only formed under the bottom face of the first metal layer.