Patent ID: 8530961
Filing Date: 2013-09-10
Classification: H01L

Abstract:
1. A method for fabricating an LDMOS transistor compatible with a VDMOS transistor comprising: preparing a substrate with an LDMOS transistor area and a VDMOS transistor area; forming an N-buried layer area by injecting ions into the substrate; forming an epitaxial layer in the N-buried layer area, and then injecting ions into the epitaxial layer to form an N-well and a P-well in the LDMOS transistor area and a high voltage N-well in the VDMOS transistor area; forming an isolation area at the interface between the N-well and the P-well in the LDMOS transistor area and at the interface between the LDMOS transistor area and the VDMOS transistor area; forming a drift area in the area of the P-well of the LDMOS transistor area; forming a gate on a part of the epitaxial layer and a part of the drift area in the area of the P-well of the LDMOS transistor area, and in the VDMOS transistor area; forming a PBODY area in the epitaxial layer between the gate and the isolation area in the LDMOS transistor area, and in the epitaxial layer between the gates in the VDMOS transistor area; forming an N-type GRADE area in the epitaxial layer between the drift areas in the LDMOS transistor area; forming an NSINK area in the epitaxial layer between the isolation area and the adjacent gate in the VDMOS transistor area, the NSINK area being communicated with the N-buried layer area; forming a source in the PBODY area and a drain in the N-type GRADE area in the LDMOS transistor area, and forming a source in the PBODY area and a drain in the NSINK area in the VDMOS transistor area; and forming a P+ area in the PBODY area in the LDMOS transistor area, the P+ area being communicated with the source.