Patent ID: 6091100
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A structure of a NAND cell array for nonvolatile memories formed on a substrate, said structure comprising:a plurality of pad oxides formed on said substrate, each of said plurality of pad oxides being separated to keep a space with each other;a plurality of first isolations formed on said plurality of pad oxides for isolation, said plurality of first isolations being separated from each other;a plurality of second isolations formed on said substrate, adjacent to said plurality of pad oxides and between said plurality of pad oxides;a plurality of floating gates formed on said plurality of second isolations, between said plurality of first isolations and adjacent to said plurality of first isolations;a plurality of third isolations formed at a top of said plurality of floating gates for isolation;a word line formed on said plurality of first isolations and on said plurality of third isolations; anda plurality of bit lines formed in said substrate and under said plurality of first isolations.