Patent ID: 6714436
Filing Date: 2004-03-30
Classification: G11C,H01L

Abstract:
A method for writing data to a (1T/0C) memory cell that comprises:(i) a semiconductor substrate; (ii) an insulating layer formed on the substrate; (iii) a body of semiconductor material of a first conductivity type formed on the insulating material and having an upper surface; (iv) a drain region of a second conductivity type formed at a first end of the body of semiconductor material, the drain region extending vertically between the upper surface and the insulating layer; (v) a source region of the second conductivity type formed at a second end of the body of semiconductor material, the source region extending vertically between the upper surface and the insulating layer; (vi) a gate dielectric formed on the upper surface; (vii) a gate conductor formed over the gate dielectric; and (viii) a word line (WL) coupled to the gate conductor, a bit line (BL) coupled to the drain region, and a source line (SL) coupled to the source region, the method comprising: applying a first voltage to the WL; applying a second voltage to the BL; applying a third voltage to the SL; causing electron/hole carrier pairs to appear in the body as a result of a BTBT mechanism; causing carriers of the second conductivity type to flow from the body to the drain and to the source regions; and causing carriers of the first conductivity type to accumulate in the body so as to modulate the threshold voltage of the memory cell.