Patent ID: 7373560
Filing Date: 2008-05-13
Classification: G01R

Abstract:
1. A system for measuring propagation delays in any number of synchronous test circuits, the system comprising a first stage including: an upstream memory element having an asynchronous input terminal, having a clock terminal to receive a test clock, and having an output terminal; a synchronous test circuit having a clock terminal, a synchronous data input terminal, an output terminal, a first asynchronous input terminal coupled to the output terminal of the upstream memory element, and a second asynchronous input terminal, wherein the first and second asynchronous input terminals are configurable to initialize the synchronous test circuit's output terminal to first and second logic states, respectively; and a downstream memory element having an asynchronous input terminal to receive a feedback signal, a clock terminal coupled to the output terminal of the synchronous test circuit, and an output terminal coupled to the asynchronous input terminal of the upstream memory element; wherein the first asynchronous input terminal of the synchronous test circuit comprises one of a clear terminal and a set terminal; wherein the second asynchronous input terminal of the synchronous test circuit is maintained in an asserted state.