Patent ID: 8062932
Filing Date: 2011-11-22
Classification: H01L

Abstract:
1. A method of packaging a semiconductor package having a bypass capacitor plus a number of semiconductor dies interconnected with a plurality of elevation-adaptive intimate interconnection plates and elevation-adaptive stacked interconnection plates, the method comprises: a) providing a circuit substrate having a plurality of terminal leads for external electrical connection; b) providing the semiconductor dies and attaching them atop the circuit substrate; c) providing and attaching the plurality of intimate interconnection plates to the top contact areas of said semiconductor dies and said circuit substrate for electrical connection between said top contact areas and said terminal leads; d) providing and attaching the plurality of stacked interconnection plates atop a selected number of intimate interconnection plates while insuring that a first member of the stacked interconnection plates has a first flat-top area and a second member of the stacked interconnection plates has a second flat-top area in level with the first flat-top area; d1) molding a first encapsulant over the package in progress; d2) removing a top portion of the first encapsulant till the top surfaces of the first flat-top area and the second flat-top area are exposed; e) providing a bypass capacitor having two end capacitor terminals, stacking then bonding the bypass capacitor atop the two stacked interconnection plate members via the first flat-top area and the second flat-top area; and f) molding a second encapsulant over the package in progress with the exception of exposing the top surface of the bypass capacitor.