Patent ID: 6748039
Filing Date: 2004-06-08
Classification: G06F,H04L

Abstract:
In a microprocessor having a clock-skipping buffer for transferring data between a first clock domain having a first clock signal and second clock domain having a second clock signal, a circuit comprising:a first alignment unit, wherein said first alignment unit is configured to detect the alignment of a pulse of said first clock signal with a reference clock pulse; a second alignment unit, wherein said second alignment unit is configured to detect the alignment of a pulse of said second clock signal with said reference clock pulse; a synchronous reset unit coupled to said first and second alignment units and configured to receive an asynchronous reset signal, wherein said synchronous reset unit is configured to generate a first reset signal which is aligned with said clock pulse in said first clock domain and a second reset signal which is aligned with said clock pulse in said second clock domain; and a counter reset unit coupled to said synchronous reset unit to receive said first and second reset signals, wherein said counter reset unit is configured to reset a load counter based on one of said reset signals and to reset an unload counter based on the other of said reset signals.