Patent ID: 8760197
Filing Date: 2014-06-24
Classification: G06F,H03K

Abstract:
1. A clock switching system, comprising: a first re-synchronization circuit configured to receive a first input clock; a first OR gate logic circuit configured to receive the first input clock and an output from the first re-synchronization circuit; a second re-synchronization circuit configured to receive a second input clock; a second OR gate logic circuit configured to receive the second input clock and an output from the second re-synchronization circuit; an input select decoder coupled to the first re-synchronization circuit and the second re-synchronization circuit, configured to dynamically select either the first or the second input clock to be active; a feedback controller configured to: a third OR gate logic circuit configured to receive the output feedback from the second re-synchronization circuit and an output from the input select decoder; and a fourth OR gate logic circuit configured to receive the output feedback from the first re-synchronization circuit and the output from the input select decoder; wherein upon being dynamically selected the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock, wherein both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock, wherein the feedback of the output of the first re-synchronization circuit is synchronized with the feedback of the output of the second re-synchronization circuit, and wherein the first input clock into the first re-synchronization circuit, and the second input clock into the second re-synchronization circuit, are not inverted.