Patent ID: 7562324
Filing Date: 2009-07-14
Classification: G06F

Abstract:
1. A method of designing a digital synchronous VLSI system established from a quadratic equation for Clock Skew scheduling and optimization comprising following steps: (a) constructing a circuit model for the quadratic equation using a digital computer, utilizing the feature of circuit linear dependence and a minimum spanning tree that works with a Depth First Search algorithm to deduce the clock skew matrix;  wherein s=clock skew, R=Register, C=Circuit loop (b) executing “least square error” to optimize the produced clock skew matrix produced in 1 (a); Introducing the Lagrange Multipliers by utilizing the method of quadratic programming, and deduce the Lagrange function Λ(s, λ)  {tilde over (ε)} is a stationary point (fixed point) in the Lagrange function (s, λ), so 0 is given from a first-order partial differentiation, namely ∇(s, λ)=0 Presenting in a manner of matrix  wherein  B  s and g presented as S=[S  Wherein g=optimal clock skew, s=calculated clock skew, λ is the Lagrange Multipliers. And S (c) calculating the Lagrange Multipliers with the use of high precision and calculating speed Conjugate Gradients Algorithm; Output a set of calculated results when the Residual Error is small enough to reach a stop condition of iteration; (d) wherein the value of x computed by Conjugate Gradients Algorithm approaches the correct value of x; (e) wherein the result of clock skew produced in (c) is the optimum clock skew amount for circuit working; and (f) testing by ISCAS'89 benchmark.