Patent ID: 7928513
Filing Date: 2011-04-19
Classification: H01L

Abstract:
1. A chip including a hybrid complementary metal oxide semiconductor (“CMOS”) structure, comprising: a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of said substrate, said first region and said bulk region having a first crystal orientation, said bulk device further including a first gate conductor overlying said first region; a SOI device disposed in a semiconductor-on-insulator (“SOI”) layer separated from said bulk region of said substrate by a buried dielectric layer, said SOI layer having a second crystal orientation different from said first crystal orientation, said SOI device including a second gate conductor overlying said SOI layer of said substrate; a first diode disposed in a second region of said substrate in conductive communication with said bulk region, said first diode having a cathode in conductive communication with at least said first gate conductor and having an anode in conductive communication with said bulk region, said first diode having a breakdown voltage in excess of which said first diode is operable to conduct a discharge current to said bulk region; and a second diode disposed in a third region of said substrate in conductive communication with said bulk region, said second diode having a cathode in conductive communication with at least one of a source region or a drain region of at least said SOI device and an anode in conductive communication with said bulk region, said second diode having a breakdown voltage in excess of which said second diode is operable to conduct a discharge current to said bulk region; a first conductive line in a first metal layer extending at least substantially parallel to the major surface at a first height from the major surface, the first conductive line disposed in a first conductive path between a drain region of the bulk device and a drain region of the SOI device; and a second conductive line in a second metal layer extending at least substantially parallel to the major surface at a second height from the major surface, the second conductive line disposed in a second conductive path between the first gate conductor and the cathode of the first diode, wherein the second height is substantially less than the first height.