Patent ID: 7768829
Filing Date: 2010-08-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said plurality of memory cells storing one of a plurality of threshold levels; and a control circuit which, when writing one of said plurality of threshold levels into a first memory cell of the memory cell array, writes a second memory cell adjacent to the first memory cell consecutively and a write operation and a verify operation are repeated, wherein when a threshold voltage of the first memory cell has not reached a verify level a write voltage is increased by a first step voltage and the write operation and the verify operation are repeated, and when the first memory cell adjacent to the second memory cell is not written consecutively the write operation and the verify operation are repeated, and when a threshold voltage of the first memory cell has not reached the verify level, the write voltage is increased by a second step voltage lower than a first write voltage and written to the first memory cell by repeating the write operation and the verify operation.