Patent ID: 7369439
Filing Date: 2008-05-06
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a memory cell array having a plurality of memory cell transistors arranged in a matrix form, each of the memory cell transistors including a floating gate formed on a gate insulating film, a inter-gate insulating film provided on the floating gate and a control gate provided on the inter-gate insulating film, and a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path which is connected at one end to a selected control gate and a second high-voltage transistor having a current path which is connected at one end to a first non-selected control gate adjacent to the selected control gate and configured to raise voltage applied to the selected control gate to program voltage by use of first capacitive coupling caused between the selected control gate and the first non-selected control gate by applying intermediate voltage approximately equal to voltage which makes the current path of the memory cell transistor conductive to the first non-selected control gate.