Patent ID: 8086801
Filing Date: 2011-12-27
Classification: G06F

Abstract:
1. A method, in a processor, for loading data to a vector register from across multiple cache lines in a data cache, the method comprising: receiving a vector load instruction in a load/store unit, wherein the vector load instruction crosses at least one cache line boundary; accessing a first cache line in the data cache to receive a first data portion associated with the vector load instruction; formatting the first data portion for a partial write to the vector register to form a formatted first data portion and writing the formatted first data portion to the vector register; attempting a second cache line access to access a second cache line in the data cache to receive a second data portion associated with the vector load instruction; responsive to the second cache line resulting in a cache hit, formatting the second data portion for a partial write to the vector register to form a formatted second data portion and writing the formatted second data portion to the vector register thereby loading the data associated with the vector load instruction into the vector register.