Patent ID: 6100126
Filing Date: 2000-08-08
Classification: H01L,Y10S

Abstract:
A method of making a resistor in an integrated circuit, which comprises the steps of:(a) forming an electrical element on a silicon semiconductor substrate;(b) depositing a first insulating layer and etching said first insulating layer to form a bit line contact hole;(c) forming a bit line;(d) forming a second insulating layer and etching said second insulating layer to form a contact hole;(e) depositing a polysilicon layer across said contact hole and overlaying said second insulating layer;(f) removing said polysilicon outside said contact hole to form a polysilicon plug having a high aspect ratio in said contact hole;(g) doping said polysilicon plug to form the resistor;(h) depositing a third insulating layer and etching said third insulating layer to form a metallurgy contact hole; and(i) forming a metal interconnection.