Patent ID: 6670219
Filing Date: 2003-12-30
Classification: H01L

Abstract:
A method of fabricating a CDBGA package, comprising:providing a thermal dissipating substrate having a chip region at the center thereof and a circuit substrate region located at a periphery of the chip region; forming a plurality of conductive bumps on the circuit substrate region; providing a circuit substrate comprising an insulating layer and a patterned trace layer, wherein a plurality of vias are formed on the insulating layer, and the conductive bumps partially fill the vias, wherein the insulating layer is adhered on the circuit substrate region, and a plurality of ground pads, ball pads and nodes are formed on the patterned trace layer, and wherein the ground pads are located on the vias, each ground pad having a hole located at the center thereof; forming a solder mask to cover the patterned trace layer wherein the ground pads, the balls pads and the nodes remain exposed; providing a chip having an active surface and a corresponding back surface, wherein the back surface of the chip is adhered on the chip region, and a plurality of bonding pads are formed on the active surface; electrically connecting the bonding pads to the nodes; performing a molding process encapsulating the chip, the nodes and connecting portions between the bonding pads and the nodes; placing a plurality of solder balls on the ground pads and the ball pads; and performing a reflow process so that the solder balls on the ground pads are softened and fill the vias and electrically connect with the conductive bumps.