Patent ID: 6768130
Filing Date: 2004-07-27
Classification: H01L

Abstract:
An integrated circuit formed by a method comprising the steps of:recessing a first portion of a surface of a monolithic semiconducting substrate without effecting a second portion of the surface of the monolithic semiconducting substrate, by growing a thermal oxide layer on the surface of the substrate, depositing a nitride masking layer on the thermal oxide layer, forming a patterning layer on the nitride masking layer, forming openings in the patterning layer, etching portions of the nitride masking layer and the thermal oxide layer through the openings in the patterning layer, removing the patterning layer, recessing the first portion of the surface of the substrate underlying the etched portions of the nitride masking layer and the thermal oxide layer, and stripping off all material remaining on the surface of the substrate, implanting an insulator precursor species of one of oxygen and nitrogen beneath the surface of the recessed first portion of the monolithic semiconducting substrate, etching a trench around the implanted and recessed first portion of the monolithic semiconducting substrate, activating the insulator precursor species to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate, thereby elevating the surface of the recessed first portion of the substrate to be substantially planar with the second portion of the surface of the substrate, forming a semiconductor on insulator structure in the first portion of the monolithic semiconducting substrate, and forming a bulk semiconductor structure in the second portion of the monolithic semiconducting substrate.