Patent ID: 7160756
Filing Date: 2007-01-09
Classification: H01L

Abstract:
1. A method of packaging semiconductor devices for flip chip and wire bond applications, comprising the steps of: providing a semiconductor substrate comprised with microelectronic elements wherein a first region of the semiconductor substrate is to be used for wire bond applications while a second region of the semiconductor substrate is to be used for flip chip applications: forming a first copper interconnect structure on a portion of said first region of said semiconductor substrate, and forming a second copper interconnect structure on a portion of said second region of said semiconductor substrate; forming a low dielectric constant (low k) layer on said semiconductor substrate, with openings in said low k layer exposing a portion of a top surface of said first copper interconnect structure and exposing a portion of a top surface of said second copper interconnect structure; forming a first polymer layer with openings in said first polymer layer exposing a portion of said top surface of said first copper interconnect structure and a portion of said top surface of said second copper interconnect structure; forming an dicing lane opening in said first polymer layer, in said low k layer and in a top portion of said semiconductor substrate located between copper interconnect structures; forming a first conductive shape on said exposed portion of said first copper interconnect structure and forming a second conductive shape on exposed portion of said second copper interconnect structure; forming a second polymer layer; forming an opening in said second polymer layer exposing a portion of top surface of said second conductive shape; forming a solder ball in said opening in said second polymer layer; and separating said first region of said semiconductor substrate from said second region of said semiconductor substrate.