Patent ID: 6362669
Filing Date: 2002-03-26
Classification: H03K

Abstract:
A power-on reset (POR) circuit for generating a POR control signal in an integrated circuit (IC) device, wherein assertion of the POR control signal initiates a reset operation in which logic elements of the IC device are reset to a non-configured state, and de-assertion of the POR control signal initiates a configuration operation in which logic elements of the IC device are configured in accordance with pre-defined configuration data, the POR circuit comprising:a detector circuit for generating a detection signal having a first voltage level when an internal voltage level of the IC device is less than a pre-defined voltage level, and a second voltage level when the internal voltage level is greater than the pre-defined voltage level; and a POR control circuit including a one-shot delay circuit for detecting a change in the detection signal from the first voltage level to the second voltage level, and for maintaining the POR control signal in an asserted state by generating a one-shot pulse in response to the detection signal change such that the POR signal is maintained in the asserted state at least until the end of the one-shot pulse, the one-shot delay circuit including: a first inverter connected to the detector circuit; a lock circuit having a first input terminal connected to an output terminal of the first inverter; and a one-shot circuit having an input terminal connected to an output terminal of the lock circuit, wherein the lock circuit also has a second input terminal connected to an output terminal of the one-shot circuit.