Patent ID: 6681285
Filing Date: 2004-01-20
Classification: G06F,H04N

Abstract:
A memory controller comprising:an access priority arbiter having a memory address bus and a memory data bus for connection with one or more memories and a plurality of requester buses, each for connection to a memory requester, one or more of a RAM controller for connection with a RAM connected to the memory data and address buses and a ROM controller for connection with a ROM connected to the memory data and address buses, wherein each such one or more of a RAM controller and a ROM controller are connected to the access priority arbiter with one or more control lines, wherein the access priority arbiter receives access requests on one or more of the requester buses and grants access to the memory address and data bus to one requester bus at any one time based on logic internal to the access priority arbiter, and wherein the access requests include burst counts and the access priority arbiter grants access as a function of the burst counts and an aggregated total wait time.