Patent ID: 9214434
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A package comprising: a semiconductor die comprising: a stiffener extending outward from the third surface of the semiconductor die; a conductive via passing through the stiffener, wherein the conductive via comprises a through hole; a first electrically conductive pattern coupled to the first surface of the semiconductor die and to the conductive via; a second electrically conductive pattern coupled to the second surface of the semiconductor die, the second electrically conductive pattern coupling the bond pad to the conductive via; a first passivation layer coupled to the first electrically conductive pattern and extending into the through hole of the conductive via; a second passivation layer coupled to the second electrically conductive pattern and to the first passivation layer; and a barrier layer between the conductive via and the bond pad, wherein the barrier layer extends from the bond pad to an outer perimeter edge of the conductive via.