Patent ID: 7399663
Filing Date: 2008-07-15
Classification: H01L

Abstract:
1. A method, comprising: forming a recess adjacent to a first gate electrode of a first transistor, said first gate electrode formed above a substrate comprising a first crystalline semiconductor layer, a buried insulating layer formed on said first crystalline semiconductor layer and a second crystalline semiconductor layer formed on said buried insulating layer, said recess extending into said first crystalline semiconductor layer; epitaxially growing a strained semiconductor material in said recess; forming a drain and source region in said strained semiconductor material by implanting a dopant species into said strained semiconductor material; and adjusting a dopant profile of said implanted species to define a first channel region and a second channel region, said first channel located at an interface of a gate insulation layer and said second semiconductor layer, said second channel region located at an interface of said buried insulating layer and said second semiconductor layer.