Patent ID: 6037816
Filing Date: 2000-03-14
Classification: H04L

Abstract:
A semiconductor integrated circuit composed of a half latch circuit comprising:a first pair of lines for transmitting a first pair of differential clock signals, one of said pair of lines operative as a power-source line;a second pair of lines for transmitting a second pair of differential clock signals, one of said pair of lines operative as a ground line;two clocked inverting circuits each of which comprises:a first inverting circuit for receiving data and inverting the received data to output the inverted data,a first switch circuit coupled between the first inverting circuit and the power-source line, anda second switch circuit coupled between the first inverting circuit and the grounding line, the two clocked inverting circuits being connected in cascade; anda second inverting circuit for receiving an output from said clocked inverting circuits in the subsequent stage and inverting the output, whereinan output from said second inverting circuit is feedbacked to the cascade connection point between said two clocked inverting circuits.