Patent ID: 8138557
Filing Date: 2012-03-20
Classification: G06F,H01L

Abstract:
1. A layout structure of a metal-oxide-semiconductor field effect transistor (MOSFET), comprising: a plurality of MOSFET cells; a first source/drain metal bus structure electrically connected to first sources/drains of the MOSFET cells, and a width of the first source/drain metal bus structure gradually decreased in a predetermined direction; a second source/drain metal bus structure electrically connected to second sources/drains of the MOSFET cells, and a width of the second source/drain metal bus structure gradually increased in the predetermined direction; a third source/drain metal bus structure electrically connected to the first source/drain metal bus structure, and a width of the third source/drain metal bus structure gradually increased in the predetermined direction; a fourth source/drain metal bus structure electrically connected to the second source/drain metal bus structure, and a width of the fourth source/drain metal bus structure gradually decreased in the predetermined direction; a first source/drain conducting wire structure electrically connected to the first sources/drains of the MOSFET cells and the first source/drain metal bus structure; and a second source/drain conducting wire structure electrically connected to the second sources/drains of the MOSFET cells and the second source/drain metal bus structure, wherein the first source/drain conducting wire structure and the second source/drain conducting wire structure are saw-toothed, and each of the first source/drain conducting wire structure and the second source/drain conducting wire structure respectively have a plural lines, in which the plural lines extend along a direction being non-parallel with the predetermined direction.