Patent ID: 7389383
Filing Date: 2008-06-17
Classification: G06F

Abstract:
1. A method for selectively unmarking load-marked cache lines during transactional execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads, the method comprising: encountering a release instruction during transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution completes without encountering an interfering data access from another thread and wherein the release instruction attempts to selectively release load-marked cache lines from monitoring and wherein the release instruction does not terminate transactional execution; and in response to the release instruction, modifying the state of load-marked cache lines, which are specially load-marked to indicate that they can be released from monitoring, to account for the release instruction being encountered; wherein each specially load-marked cache line contains a release value indicating how many release instructions need to be encountered before the cache line can become unmarked; wherein modifying the specially load-marked cache line involves decrementing the release value; wherein if decrementing the release value causes the release value to become zero, the cache line becomes unmarked; and wherein decrementing release values for all specially load-marked cache lines involves incrementing a global counter, wherein release values are initialized with respect to the global counter.