Patent ID: 7882466
Filing Date: 2011-02-01
Classification: G01R,G06F,H01L

Abstract:
1. A noise checking method executed by a computer, in designing an integrated circuit, performed on a result of cell arrangement of a plurality of cells including a standard cell and a large cell on a chip of the integrated circuit or on a result of inter-cell wiring among the plurality of cells arranged on the chip, said method comprising: extracting, by a processor, terminal information about one or more terminals of the large cell and wiring forbidden information about one or more wiring forbidden areas each formed on or inside of the large cell from a library which provides the terminal information and the wiring forbidden information; spuriously determining, by the processor, one or more internal wires of the large cell based on the terminal information and the wiring forbidden information extracted, and adding the internal wires determined into chip wires to be checked; selecting, by the processor, an object wire to be checked and at least one affecting wire from the chip wires to which the internal wires determined are added; calculating, by the processor, a noise value representing a degree at which the at least one affecting wire induces noise onto the object wire; and carrying out, by the processor, a noise check on the object wire based on the noise value calculated.