Patent ID: 8357999
Filing Date: 2013-01-22
Classification: H01L

Abstract:
1. A semiconductor die assembly, comprising a die stack comprising a first die mounted on a substrate and at least one additional die stacked over said first die mounted on said substrate, said first die and each said additional die having a plurality of peripheral electrical connection arrayed in a row near and generally parallel to a peripheral edge of said die, and a conducting element electrically connected to at least one of said peripheral electrical connection sites on at least one of said die and extending from said at least one peripheral electrical connection site toward said peripheral die edge on said at least one of said die; and the substrate having an electrical connection land at a die mount side thereof, wherein said at least one of said peripheral electrical connection sites is electrically connected to said electrical connection land on said substrate by an electrically conductive polymer element applied to a side of said die stack adjacent said peripheral die edge, said electrically conductive polymer element contacting said conducting element and being electrically connected to said land.