Patent ID: 7517811
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method for forming a floating gate of a flash memory formed on a substrate, the method comprising: sequentially forming a oxide layer and a dielectric layer on the substrate; patterning the dielectric layer; etching the oxide layer and the substrate while using the patterned dielectric layer as a mask to form shallow trenches; removing a portion of the dielectric layer by isotropic etching to expose corners of the shallow trenches; rounding the corners by a thermal process; forming isolation structures in the substrate, the oxide layer and the dielectric layer to define at least one active region; removing the dielectric layer and the oxide layer; forming a tunneling oxide layer on the active region after forming the isolation structures; forming a first conductive layer on the tunneling oxide layer, wherein all top surfaces of the conductive layer and the isolation structures are coplanar; forming a second conductive layer covering the first conductive layer and the isolation structures; and removing a portion of the second conductive layer on the isolation structures to expose the top surfaces of the isolation structures to form the floating gate.