Patent ID: 6532188
Filing Date: 2003-03-11
Classification: G11C

Abstract:
An integrated memory, comprising:a memory cell array having column lines, row lines, and memory cells, each of said memory cells being connected to one of said row lines for selection of one of said memory cells and to one of said column lines for reading out or writing of a data signal; a row access controller connected to said row lines for activating one of said row lines for the selection of one of said memory cells and for controlling a deactivation operation for deactivating one of said row lines; a signal terminal for a signal; a clock terminal for receiving a clock signal; and a control unit having a first input connected to said clock terminal and a second input connected to said signal terminal for receiving the signal, the signal which, in an event of a read access to one of said memory cells, defines a beginning of data outputting to a point outside said memory cell array, the data outputting being synchronized with the clock signal, the signal being adjustable in dependence on an operating frequency of the integrated memory, said control unit having an output coupled to said row access controller and outputting an output signal for triggering the deactivation operation of one of said row lines after a write access to one of said memory cells.