Patent ID: 8059684
Filing Date: 2011-11-15
Classification: H04J

Abstract:
1. An apparatus for splitting an asynchronous signal, comprising: a first module, configured to buffer, according to frame sequence, an asynchronous signal to be split; wherein the asynchronous signal comprises Optical Data Unit (ODU) or Optical Transport Unit (OTU); a second module, configured to manage the first module to buffer the asynchronous signal to be split, and send n frames of data respectively on n channels in parallel whenever n frames of data have been buffered, wherein the rate level of the asynchronous signal before split is n times of the rate level of the asynchronous signal after split; wherein the first module comprises: 2n First In First Out (FIFO) memories in two groups, each group comprising n FIFO memories and each FIFO memory storing one frame of data each time; and the second module comprises: a frequency-divided-by-n module, configured to reduce a frequency of an input clock signal to 1/n of the frequency of the input clock signal, and send an output clock signal with a frequency of 1/n of the frequency of the input clock signal; a write address generation module, configured to manage a write operation of each FIFO memory to buffer the n frames of data of the asynchronous signal according to the frame sequence; and a read address generation module, configured to manage a read operation of each FIFO memory to send n frames of data respectively on n channels in parallel whenever n frames of data have been buffered; wherein the write address generation module is configured to generate a write address control signal and a write enabling control signal according to the frequency of the input clock signal, input the write address control signal and the write enabling control signal to each FIFO memory, and manage the asynchronous signal to be serially written into one group of FIFO memories according to the frame sequence; and the read address generation module is configured to receive the output clock signal from the frequency-divided-by-n module, generate a read address control signal and a read enabling control signal according to the output clock signal and send the read address control signal and the read enabling control signal to each FIFO memory, and manage n frames of data in the other group of FIFO memories to be read in parallel.