Patent ID: 7688129
Filing Date: 2010-03-30
Classification: G11C,H03H

Abstract:
1. A system for generating an output clock signal that has a predetermined phase relative to an input clock signal, comprising: a plurality of first delay circuits coupled in series with each other from an initial first delay circuit that is coupled to receive the input clock signal to a final first delay circuit, each of the first delay circuits operable to provide a first delay to a signal applied to its input, the first delay circuits being responsive to a first transition of the input clock signal to propagate a signal through the first delay circuits from the initial first delay circuit toward the final first delay circuit; and a plurality of second delay circuits coupled in series with each other, each of the second delay circuits being coupled to a respective one of the first delay circuits in reverse order so that signals are coupled through the second delay circuits in a direction that is opposite the direction through which signals are coupled through the first delay circuits, each of the second delay circuits operable to provide a second delay to a signal applied to its input that is less than the first delay, each of the second delay circuits operable to generate an output signal that substantially mirrors an output signal from the respective first delay circuit at a second transition of the input clock signal, the second delay circuits being responsive to the second transition of the input clock signal to propagate the output signals generated by the second delay circuits to a final second delay circuit that is coupled to the initial first delay circuit, the output clock signal being generated by the final second delay circuit.