Patent ID: 8560992
Filing Date: 2013-10-15
Classification: G06F

Abstract:
1. A method for inspecting a chip layout, comprising: providing a chip layout having a plurality of patterns designed according to a design rule; performing a first inspection to the plurality of patterns according to the design rule using a processor of a computer system; determining patterns violating the design rule, as violating patterns, and corresponding violation values; determining violating patterns having a minimum violation value among the violating patterns; classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value by randomly selecting a pattern from the violating patterns having the minimum violation as a reference pattern, comparing the violation patterns having the minimum violation with the reference pattern one by one, obtaining overlapping ratios between the violation patterns having the minimum violation and the reference pattern, and classifying the violation patterns into different sub-categories according to the overlapping ratios, wherein the characteristics of the violating patterns comprise shapes of the violating patterns; and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions.