Patent ID: 6590265
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor wafer; a gate electrode overlying said semiconductor wafer and having a width defined by essentially parallel, opposing sidewalls; a dielectric spacer adjacent each of said opposing sidewalls, said dielectric spacers having an elevation approximately equal to that of the adjacent gate electrode sidewall; an insulating layer overlying said semiconductor wafer, said gate electrode and said spacers; a gate electrode contact opening having a dimension parallel to said width, wherein said gate electrode contact opening is disposed overlying a portion of said gate electrode and a portion of at least one of said spacers, and wherein said dimension is essentially equal to said width; at least one doped region formed in said semiconductor wafer extending into said semiconductor wafer to a uniform depth and extending under said gate electrode, wherein said insulating layer defines a contact opening to said doped region at a surface of said semiconductor wafer.