Patent ID: 7231618
Filing Date: 2007-06-12
Classification: G06F

Abstract:
1. A method for designing an electronic device using one or more resistance, inductance, conductance, capacitance (“RLGC”) coefficients, comprising: defining a plurality of meshes on a surface of an interconnect structure of the electronic device; calculating at least one area RLGC coefficient for each of the plurality of meshes; calculating at least one fringe RLGC coefficient for each mesh of the plurality of meshes that has an outer edge that does not abut an edge of another mesh of the plurality of meshes; simulating the electronic device using the calculated at least one area RLGC coefficient for each of the plurality of meshes and the calculated at least one fringe RLGC coefficient for each of the plurality of meshes that has an outer edge that does not abut an edge of another mesh of the plurality of meshes to generate a simulation result; and outputting the simulation result.