Patent ID: 6778014
Filing Date: 2004-08-17
Classification: H03F

Abstract:
A CMOS differential amplifier comprising a series-connected arrangement consisting of a first PMOS FET, a second PMOS FET, a first NMOS FET and a second NMOS FET, which is connected between a first voltage and a second voltage that is lower than the first voltage, whereby the gate connection of the first PMOS FET and the gate connection of the second NMOS FET are connected to a first circuit node, where the drain connection of the second PMOS FET is connected to the drain of the first NMOS FET, and where a bias voltage is generated;a series-connected arrangement consisting of a third PMOS FET, a fourth PMOS FET, a first NMOS FET and a second NMOS FET, which is connected between the first voltage and the second voltage, whereby the gate connection of the third PMOS FET and the gate connection of the fourth NMOS FET are connected to the first circuit node, the gate connection of the second PMOS FET to the gate connection of the fourth PMOS FET, and the gate connection of the first NMOS FET to the gate connection of the third NMOS FET, and the circuit node, at which the drain connection of the fourth PMOS FET is connected to the drain connection of the third NMOS FET, forming the output of the CMOS differential amplifier; a fifth PMOS FET that is connected between the first voltage and a second circuit node; a fifth NMOS FET that is connected between a third circuit node and the second voltage; a sixth PMOS FET, connected between the second circuit node and the circuit node at which the source connection of the first NMOS FET is connected to the drain connection of the second NMOS FET; a sixth NMOS FET connected between the circuit node at which the drain connection of the first PMOS FET is connected to the source connection of the second PMOS FET, and the third circuit node, whereby the gate connection of the sixth PMOS FET and the gate connection of the sixth NMOS FET are connected to a first differential input of the CMOS differential amplifier; a seventh PMOS FET that is connected between the second circuit node and the circuit node at which the source connection of the third NMOS FET is connected to the drain connection of the fourth NMOS FET; a seventh NMOS FET that is connected between the circuit node at which the drain connection of the third PMOS FET is connected to the source connection of the fourth PMOS FET and the third circuit node, whereby the gate connection of the seventh PMOS FET and the gate connection of the seventh NMOS FET are connected to a second differential input of the CMOS differential amplifier; and a circuit for generating a voltage at the gate connection of the second PMOS FET that is at least as much lower than the gate voltage of the first PMOS FET that this can operate in its saturation range, and to generate a voltage at the gate connection of the first NMOS FET that is at least that much higher than the gate voltage of the second NMOS FET that this can operate in its saturation range.