Patent ID: 6963508
Filing Date: 2005-11-08
Classification: G11C

Abstract:
1. An operation method for non-volatile memory, comprising the steps of: providing a non-volatile memory cell capable of storing at least a first bit and a second bit and having a first region and a second region with a channel therebetween and a gate above the channel but separated therefrom by a charge trapping layer sandwiched between a first dielectric layer and a second dielectric layer, wherein the first bit and the second bit are positioned close to the first and second regions respectively; determining a first programmed voltage for the first bit, a second programmed voltage for the second bit and an erased voltage for the first and second bits, wherein the first programmed voltage is smaller than the second programmed voltage; reading the first bit by applying a voltage to the second region; and reading the second bit by applying a voltage to the second region, wherein the voltage applied to the second region for reading the second bit is smaller than that for reading the first bit.