Patent ID: 6154389
Filing Date: 2000-11-28
Classification: G11C

Abstract:
A semiconductor memory device comprising:a mat having a plurality of sectors for storing information of data; anda redundancy circuit having at least one enable fuse element for indicating whether a defective main column in at least one of the sectors is present, for generating a plurality of redundancy selection signals to be applied in common to the sectors when the enable fuse element is open-circuited, the redundancy selection signals each corresponding to a plurality of input/output pins of the device,wherein each of the sectors has:a) a main memory cell array divided into plural input/output blocks, each of which corresponds to the input/output pins and has two bit segments of main columns of main memory cells;b) a redundancy memory cell array divided into two redundant bit segments, each of which has two redundant columns of redundant memory cells;c) a first column selector for selecting one of the main columns of each bit segment in response to first column address signals;d) a second column selector for selecting one of the two redundant columns of each redundant bit segment in response to one of the first column address signals, the one address signal indicating a least-significant bit of the first column addresses;e) a third column selector for selecting one of the two bit segments in each input/output block and one of the two redundant bit segments in response to second column address signals;f) a first plurality of sense amplifiers each corresponding to the input/output blocks, each for sensing and amplifying stored data in corresponding input/output block through the main column thus selected;g) a second sense amplifier for sensing and amplifying stored data in the selected redundant bit segment through the redundant column thus selected; andh) a plurality of multiplexers each coupled to the input/output pins, each for receiving outputs from a first corresponding sense amplifier and from the second sense amplifier and selecting one of the outputs thus received in response to a corresponding redundancy selection signal,whereby two adjacent main columns short-circuited in one input/output block are replaced with two redundant columns of either of the redundant bit segments only by use of column address information indicating one of the short-circuited main columns.