Patent ID: 7613880
Filing Date: 2009-11-03
Classification: G06F,G11C,H01L

Abstract:
1. A memory module including a non-volatile memory, a dynamic random access memory, a static random access memory, and a first control circuit that accesses the non-volatile memory, the dynamic random access memory, and the static random access memory, the memory module comprising: a dynamic random access memory interface to outside the memory module for accessing the dynamic random access memory from outside the memory module; and a static random access memory interface to outside the memory module for accessing the static random access memory from outside the memory module, wherein the dynamic random access memory interface is arranged to connect to a first memory controller outside the memory module, wherein the static random access memory interface is arranged to connect to a second memory controller outside the memory module, different from the first memory controller, wherein the first control circuit receives a first instruction code, which indicates to transfer data stored in the non-volatile memory to the dynamic random access memory, via the dynamic random access memory interface, wherein the first control circuit receives a second instruction code, which indicates to transfer data stored in the non-volatile memory to the static random access memory, via the static random access memory interface, wherein, when data stored in the non-volatile memory is to be outputted to outside the memory module, data stored in the non-volatile memory is transferred to at least one of the dynamic random access memory based on the first instruction code and the static random access memory based on the second instruction code, and then any portion of said data transferred to the dynamic random access memory is outputted to outside the memory module via the dynamic random access memory interface, and any portion of said data transferred to the static random access memory is outputted to outside the memory module via the static random access memory interface.