Patent ID: 6347393
Filing Date: 2002-02-12
Classification: G06F

Abstract:
A method implemented in a data processing system for optimizing buffer insertion with accurate gate and interconnect delay computations at a node in a circuit, the method comprising:selecting a first buffer from a plurality of buffers, each buffer in the plurality of buffers having unique buffer characteristics; calculating a &pgr;-model of a downstream circuit to a child node; calculating an effective capacitance for the child node using the &pgr;-model and the buffer characteristics of the selected first buffer; calculating a gate delay for the child node using the effective capacitance of the child node; calculating an interconnect delay for the child node using sets of moments associated with gates downstream from the child node; calculating slack at the child node for the selected first buffer using the gate delay for the child node and the interconnect delay for the child node; comparing the slack for the selected buffer with slack for at least one other buffer in the plurality of buffers; determining an optimal buffer at the child node based on comparing slacks; and inserting the optimal buffer at the child node.