Patent ID: 6058068
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A memory device, comprising:a controller having an input terminal adapted to receive commands and an output terminal, the controller being responsive to the commands to produce a set of command signal at the output terminal, the command signals including a write enable signal having a first logic state correspondence to writing data to a memory array and a second logic state correspondence to not writing data to the memory array;the memory array divided into a plurality of memory sections, each memory section including a plurality of complementary digit line pairs;a plurality of digit line drivers each corresponding to a respective memory section, each digit line driver including a write enable input coupled to the controller and adapted to receive the write enable signal, a data input adapted to receive a data signal, and a data output coupled to at least one complementary digit line pair in the memory section, each digit line driver being responsive to the write enable signal of the first logic state at the write enable input terminal and the data signal at the data input to establish respective voltages on the at least one digit line pair corresponding to the data signal; anda plurality of reset pulse generators each corresponding to a respective memory section and each having an output coupled to at least one complementary digit line pair in the memory section, each reset pulse generator having a trigger input coupled to the output terminal of the controller and being responsive to a transition of the write enable signal from the first logic state to the second logic state to drive the at least one complementary digit line pair to predetermined voltages.