Patent ID: 6158022
Filing Date: 2000-12-05
Classification: G06F

Abstract:
A method for generating a gray box model from a circuit for static circuit analysis, said circuit having one or more inputs, said method comprising the steps of:a. ordering said one or more input and selecting the first in order input as the input under analysis;b. initiating a path search from said input under analysis;c. characterizing said input under analysis;d. determining whether a state follows said input under analysis and continuing from said step of initiating with the next in order input, if any, as the input under analysis or continuing at the step of terminating said method if there is no next in order input;e. calculating delay for said stage;f. characterizing said stage, if said stage is an output; and continuing from said step of determining, if said stage is not a latch; andg. incorporating said input characterization, said delay if said stage is an input and said output characterization, if any, into said gray box model.