Patent ID: 6518153
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method for making gate electrodes of low sheet resistance for embedded DRAM devices, said method comprising the steps of:forming isolation regions around active areas on a semiconductor substrate; forming a first insulating film on said active areas; forming an electrode material on said first insulating film; forming a second insulating film on said electrode material; patterning and etching said second insulating film, said electrode material and said first insulating film by lithography leaving predetermined portions over in said active areas; forming lightly doped source/drain regions in said active areas by ion implantation; forming spacers around exposed side walls of said electrode material and said second insulating film; forming source/drain diffusion regions in said lightly doped source/drain regions; depositing a blanket interlayer dielectric on said substrate and etching back said deposited interlayer dielectric to expose said second insulating film; removing said exposed second insulating film to expose said electrode material while leaving said back-etched interlayer dielectric intact; and forming, after said removal of said exposed second insulating film, a metal layer on said exposed electrode material by depositing a metal on said exposed electrode material and etching back said metal.