Patent ID: 7007186
Filing Date: 2006-02-28
Classification: G06F

Abstract:
1. An integrated circuit configured to capture an input signal to produce an output signal, said input signal being synchronized with a first clock signal, said output signal being synchronized with a second clock signal having a second frequency different from a first frequency associated with said first signal, comprising: a first clock domain gating circuit having a first output terminal and a first input terminal, said first clock domain gating circuit being configured to be clocked by said first clock, said first input terminal being coupled to receive said input signal, said first clock domain gating circuit being configured to toggle a state of a signal on said first output terminal from one of a first state and a second state to the other of said first state and said second state every time a pulse is detected in said input signal, thereby producing a latched output at said first output terminal; and a second clock domain gating circuit having a second output terminal and a second input terminal, said second clock domain circuit being clocked by said second clock, said second input terminal being coupled to said first output terminal to receive said latched output, said second clock domain gating circuit being configured to produce a pulse on said output signal at said second output terminal, said pulse on said output signal having a duration at least as long as a period of said second clock every time a state of said latched output changes.