Patent ID: 6376302
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of forming a capacitor in a DRAM cell which comprises a DRAM transistor having a first and second dielectric layer thereover and a first and a second conductive plug through the first dielectric layer comprising:a) forming a first well in the second dielectric layer said well exposing a portion of the first conductive plug and an area adjacent said first conductive plug above a gate of the transistor; b) depositing a first capacitor plate film on the portion of the first conductive plug and said area; c) depositing a high dielectric constant layer over said first capacitor plate film; d) forming a second well in the second dielectric layer, said second well exposing the second conductive plug; e) depositing a second capacitor plate film over the high dielectric constant layer and in the second well to form a capacitor structure in said first well and a barrier layer in the second well over the plug; f) filling the wells with a conductive plug layer; g) removing the conductive plug layer and the second capacitor plate film over the wells to the level of the high dielectric constant layer and the first capacitor plate film to the level of the surface of the second dielectric layer in areas adjacent the well areas; and h) metallizing the surface of the capacitor.