Patent ID: 7947539
Filing Date: 2011-05-24
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, comprising: forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, a semiconductor layer, and an etch stop layer on the gate lines; patterning the etch stop layer and the semiconductor layer at the same time using photolithography; partially removing a photoresist film pattern used in the patterning of the etch stop layer and the semiconductor layer; removing the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members; depositing an ohmic contact layer and a data metal layer onto the etch stop members; etching the ohmic contact layer and the data metal layer at the same time using photolithography to form data lines having source electrodes, drain electrodes facing the source electrodes, and ohmic contact members below the source electrodes and the drain electrodes; forming a passivation layer on the data lines and the drain electrodes; and forming pixel electrodes on the passivation layer.