Patent ID: 6850523
Filing Date: 2005-02-01
Classification: H04L

Abstract:
1. A bus interface for exchanging packets within a communication system between a single link layer device and a physical layer device, comprising: (a) a PHY transmit interface on said physical layer device having a PHY transmit FIFO; (b) a link transmit interface on said link layer device electrically coupled to said PHY transmit interface, said link transmit interface being operative to transmit packets of variable length to said PHY transmit interface; (c) a byte availability indicator on said PHY transmit interface operative to indicate to said link transmit interface when said PHY transmit FIFO has a pre-established minimum number of bytes available for data to be written into; (d) a PHY receive interface on said physical layer device; (e) a link receive interface on said link layer device electrically coupled to said PHY receive interface said link receive interface being operative to receive packets of variable length from said PHY receive interface; and (f) a byte validity indicator on said PHY receive interface operative to indicate to said link receive interface the cessation of transmission of valid data from said PHY receive interface, wherein said link layer device generates clocks to control transmission of data between said physical layer device and said link layer device.