Patent ID: 7890915
Filing Date: 2011-02-15
Classification: G06F

Abstract:
1. A method for determining delay in static timing analysis of an integrated circuit of interest, said integrated circuit comprised of a plurality of logic cells, where said delay as determined is expressed as a parametric function, said parametric function containing statistical manufacturing process variations introduced by the process of manufacturing said logic cells of said integrated circuit, said method comprising the steps of: a) calculating, said calculating performed by means of a computational device said computational device including a CPU, a driving circuit for a first logic cell of said integrated circuit of interest, said driving circuit containing in parametric form manufacturing process variations of said integrated circuit, said calculating said driving circuit including the sub-steps of: b) calculating, said calculating performed by means of said computational device, delay and transition for said driving circuit of step (a), including the substeps of: c) repeating steps a) and b) for each logic cell comprising said integrated circuit of interest, and then outputting results, where said results map manufacturing process variations in logic cells comprising said integrated circuit of interest to performance variations of said integrated circuit of interest.