Patent ID: 6630853
Filing Date: 2003-10-07
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a first latch to pass or store a signal in accordance with a logic value of a first internal clock signal; a second latch connected in series to the first latch, to store or pass a signal in accordance with a logic value of a second internal clock signal, with operational characteristics, regarding a relation between passing or storing operations and logic values of the second internal clock signal, which are an inversion of operational characteristics regarding the same relation of the first latch; a first comparator to compare signal logic values at signal-input and -output nodes of the first latch; a second comparator to compare signal logic values at signal-input and -output nodes of the second latch; a first clock controller to generate a signal as the first internal clock signal having a specific logic value for storing the signal when the signal-input and -output nodes of the first latch have a specific same signal logic value whereas generate a specific clock signal as the first internal clock signal when the signal-input and -output nodes of the first latch have different signal logic values, under a result of comparison by the first comparator; and a second clock controller to generate a signal as the second internal clock signal having a specific logic value for storing the signal as the second internal clock signal when the signal-input and -output nodes of the second latch have a specific same signal logic value whereas generate the specific clock signal when the signal-input and -output nodes of the second latch have different signal logic values, as the second internal clock signal, under a result of comparison by the second comparator.