Patent ID: 6064098
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A semiconductor memory device having complementary metal oxide semiconductor circuitry comprising;a bulk semiconductor substrate having a memory array area and a peripheral area, the peripheral area including a p-well area comprising NMOS peripheral circuitry, the peripheral area further including a first n-well area and a second n-well area comprising respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another, the p-well area being between and adjoining both the first n-well area and the second n-well area; anda buried n-type electron collector layer implant within the p-well area of the bulk substrate, the n-type electron collector layer implant extending into the second n-well area to be in electrical connection therewith, the n-type electron collector layer implant not extending into the first n-well area.