Patent ID: 8878993
Filing Date: 2014-11-04
Classification: G09G,H03L

Abstract:
1. An image data processing apparatus, comprising: a base clock output circuit for outputting a base clock; a plurality of image processors each mutually performing the same image processing; a plurality of synchronization parts provided for each one of said plurality of image processors, said plurality of synchronization parts each synchronizing an output clock given from a corresponding one of said plurality of image processors with said base clock; a plurality of divider circuits provided for each one of said plurality of image processors, said plurality of divider circuits each dividing an output clock given from a corresponding one of said plurality of image processors by a factor of 1/n (where n is an integer), wherein said plurality of image processors each cause said output clock to oscillate at a frequency that is n times the frequency of said base clock, and said plurality of synchronization parts each include a PLL circuit for synchronizing an output from a corresponding one of said plurality of divider circuits with said base clock.