Patent ID: 6442719
Filing Date: 2002-08-27
Classification: G11C

Abstract:
A method of detecting intercell defects in a memory array including a plurality of memory cells coupled to columns of digit lines responsive to rows of word lines, the method compromising:applying a first voltage to a first digit line in each column of the memory array; coupling a first set of memory cells to the first digit line in each column of the memory array, thereby placing the first voltage on the memory cells in the first set; decoupling the first set of memory cells from the first digit line in each column of the memory array; applying a second voltage to a second digit line in each column of the memory array; coupling a second set of memory cells to the second digit line in each column of the memory array, thereby placing the second voltage on the memory cells in the second set being coupled to the second digit line during a test interval during which charge may be transferred through an intercell defect between a memory cell in the first set and a memory cells in the second set; and determining the voltage on the memory cells in the first set.