Patent ID: 7880513
Filing Date: 2011-02-01
Classification: H03K

Abstract:
1. An electronic circuit comprising: a first output stage including a first output circuit and a second output circuit; a second output stage including a third output circuit and a fourth output circuit; an activation stage including a first activation circuit and a second activation circuit, wherein the first activation circuit is configured to activate the first output circuit responsive to an input signal transitioning from a first logic level to a second logic level, and wherein the third output circuit is configured to be activated responsive to and at a first delay time subsequent to the first activation circuit activating the first output circuit, wherein each of the first and third output circuits are configured to drive an output signal to a predetermined state on an output node, wherein the predetermined state is based on the input signal; a deactivation stage including a first deactivation circuit and a second deactivation circuit, wherein the first deactivation circuit is configured to deactivate the first output circuit at a second delay time subsequent to activation of the first output circuit, wherein the third output circuit is configured to be deactivated responsive to and at the first delay time subsequent to the first deactivation circuit deactivating the first output circuit; and a keeper circuit coupled to provide the predetermined state of the output signal on the output node subsequent to deactivation of the first and third output circuits when the second and fourth output circuits are also inactive.