Patent ID: 6022790
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A process for fabricating a termination structure of a semiconductor device which includes a guard ring, said process comprising the steps of:forming a layer of field insulation material atop a silicon substrate;patterning and etching away selected portions of said layer of field insulation material to form at least one opening therein which defines an active area and at least another opening which is substantially ring-shaped and surrounds said active area for forming the guard ring;depositing a layer of polysilicon;patterning and etching away selected portions of said layer of polysilicon to form at least an opening which exposes said ring shaped opening in said layer of field insulation material, a remaining portion of said layer of polysilicon that is atop said layer of field insulation material defining a polysilicon field plate;introducing impurities of a first conductivity type into surface regions of said silicon substrate located beneath said ring shaped opening in said layer of field insulation material to form first diffused regions;introducing impurities of a second conductivity type into said surface regions of said silicon substrate located beneath said ring shaped opening to form second diffused regions, said first diffused regions being deeper and wider than said second diffused regions;depositing an overlaying insulation layer;patterning and etching away selected portions of said overlaying insulation layer to form first openings therein which expose portions of said polysilicon field plate and second openings which expose portions of said surface regions of said silicon substrate;etching depressions in said portions of said surface regions of said silicon substrate to a depth greater than the depth of said second diffused regions;depositing an overlaying conductive layer; andpatterning and etching away portions of said conductive layer to form at least one electrode which connects said polysilicon field plate with said surface regions of said silicon substrate.