Patent ID: 6519199
Filing Date: 2003-02-11
Classification: G11C

Abstract:
A semiconductor memory device designed to operate with reduced self-refresh current consumption having a cross area between a plurality of sense amplifier blocks, the device comprising:a self-refresh and internal address detecting means receiving a multiplicity of internal addresses and a self-refresh signal for generating an output signal determining whether bit line separation signals are to be toggled; a block selecting signal latching means for latching the output signal of the self-refresh and internal address detecting means and a block selecting signal; a bit line separation signal (BISH/BISL) controlling means receiving output signals of the block selecting signal latching means for generating the bit line separation signals; and a bit line separation driver controlled by the bit line separation signals, wherein the bit line separation driver is operably disposed in the cross area between at least two of the sense amplifier blocks.