Patent ID: 7235447
Filing Date: 2007-06-26
Classification: H01L

Abstract:
1. Fabrication method for a semiconductor structure having the following steps: a) providing of a semiconductor substrate with a gate dielectric; b) providing of a plurality of multilayered, elongate gate stacks which essentially run parallel to one another on the gate dielectric, which gate stacks have a bottommost layer made of silicon; c) providing of a first liner layer made of a first material over the gate stacks and the gate dielectric uncovered beside the latter, the thickness of which liner layer is less than a thickness of the bottommost layer made of silicon; d) providing of sidewall spacers made of a second material on the vertical sidewalls of the gate stacks over the first liner layer, a region of the first liner layer over the gate dielectric between the gate stacks remaining free; e) removing selectively of the first liner layer with respect to the sidewall spacers and the gate dielectric for the purpose of laterally uncovering the bottommost layer made of silicon of the gate stacks; and f) oxidizing selectively of the uncovered bottommost layer for the purpose of forming sidewall oxide regions on the gate stacks.