Patent ID: 6211005
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method of fabricating an integrated circuit ferroelectric memory device, comprising the steps of:fabricating a plurality of ferroelectric memory cells in an integrated circuit substrate, the plurality of ferroelectric memory cells including a plurality of ferroelectric capacitors, the ferroelectric capacitors comprising a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode;forming a first material layer on the upper electrodes opposite the ferroelectric layer that is electrically connected to the upper electrodes but is electrically insulated from the lower electrodes, wherein the first material layer has a sheet resistance of between about 5 and 500 .OMEGA./.quadrature.;forming an interlayer insulating layer on the first material layer, including a contact hole; andforming an interconnection layer on the interlayer insulating layer.