Patent ID: 6417521
Filing Date: 2002-07-09
Classification: G06F,G09G,H01L,H03L,H04L

Abstract:
A transmission circuit comprising:a first circuit which is operated in synchronization with a first clock signal; a second circuit which is operated in synchronization with a second clock signal having a same frequency as said first clock signal, said transmission circuit transmitting a digital data from said first circuit to said second circuit, wherein in case that said second clock signal is delayed by a phase more than zero and less than half of a period thereof with respect to said first clock signal, a digital data in synchronization with said first clock signal which is inputted from said first circuit to said transmission circuit is converted into a digital data in synchronization with said second clock signal to be outputted from said transmission circuit, and a digital data outputted from said transmission circuit is sampled and held in synchronization with said second clock signal in said second circuit, and wherein in case that said second clock signal is advanced by a phase more than zero and less than half of a period thereof with respect to said first clock signal, a digital data in synchronization with said first clock signal which is inputted from said first circuit to said transmission circuit is outputted from said transmission circuit as it is or as it is inverted, and a digital data outputted from said transmission circuit is sampled and held in synchronization with said second clock signal in said second circuit.