Patent ID: 9088291
Filing Date: 2015-07-21
Classification: H03L,H04L

Abstract:
1. A Universal Serial Bus (USB) apparatus, comprising: a signal detecting unit, for detecting a packet signal transmitted from a USB host and generating an acknowledgment signal in response to a detection result indicating that the packet signal is a start of frame (SOF) packet signal; an error detecting unit, coupled to the signal detecting unit, for utilizing an output clock signal to count a time interval between two adjacent acknowledgment signals to generate a counting result and generating a control signal according to the counting result, the output clock signal comprising a per interval quantity of clock cycles equal to a product of the time interval and a frequency of the output clock signal; and a frequency generating unit, coupled to the error detecting unit for generating the output clock signal according to the control signal, wherein the frequency generating unit comprises: a reference clock generator, for generating a reference clock signal; and a fractional-N frequency synthesizer, for generating an adjusted clock signal according to the reference clock signal and the control signal, the fractional-N frequency generator comprising a charge pump and a sigma-delta controller.