Patent ID: 6278746
Filing Date: 2001-08-21
Classification: H03D,H03J,H03L,H04L

Abstract:
A receiver circuit having a means for receiving and sampling an analog input signal to generate a digital signal controlled by a voltage controlled oscillator supplying a timing signal, said receiver circuit comprising:a digital matched filter for filtering the digital signal to generate an in-phase signal and a quadrature-phase signal;a phase detector for generating an instantaneous phase error signal based on the in-phase and quadrature-phase signal;a programmable digital loop filter that changes frequency pole and gain settings for signal acquisition and converged mode timing recovery functions by assigning a prescribed value to a gain parameter and a frequency pole parameter, waiting for timing lock, and modifying the parameters by increasing the prescribed value of the gain parameter and the prescribed value of the frequency pole parameter, the programmable digital loop filter averaging the instantaneous phase error signal for adjusting the timing signal supplied by the voltage controlled oscillator to the means for receiving and sampling the analog input signal.