Patent ID: 7355879
Filing Date: 2008-04-08
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of memory cells, each of which comprises a field effect transistor having a semiconductor layer bearing a gate electrode and two main electrodes, and having a two-terminal type nonvolatile memory element, wherein one of the main electrodes of the transistor is connected with one terminal of the nonvolatile memory element, the other main electrode is connected with a bit line, the gate electrode is connected with a word line, and the other terminal of the memory element is connected with a base line; means for detecting a potential on a connecting portion between the bit line and the other main electrode of the transistor; and means capable of supplying voltages having reverse polarities relative to a reference voltage to an input terminal of the bit line and an input terminal of the base line, respectively, wherein the semiconductor layer of the field effect transistor comprises non-crystalline silicon.