Patent ID: 9148148
Filing Date: 2015-09-29
Classification: G09G,H03K

Abstract:
1. A gate driving circuit comprising cascade-connected stages to output gate signals, an n-th (“n” is a natural number) one of the stages comprising: a pull-up part configured to intermittingly output a first clock signal as an output signal of the n-th stage; a pull-up controller configured to selectively apply a first power and a second power to a control electrode of the pull-up part; a first pull-down part configured to pull down a voltage applied to the control electrode of the pull-up part to an off voltage; a second pull-down part configured to pull down a voltage applied to an output electrode of the pull-up part to the off voltage; and a pull-down controller configured to selectively apply the first power and the second power to control electrodes of the first pull-down part and the second pull-down part, wherein: the pull-up controller comprises: levels of the first power and the second power are both different from a level of the off voltage.