Patent ID: 7142028
Filing Date: 2006-11-28
Classification: H03K

Abstract:
1. A clock duty ratio correction circuit comprising: a clock buffer unit for correcting duty ratios of a differential internal clock signals depending on a voltage level difference of duty ratio correcting signals; a charge pump unit for converting the differential internal clock signals into voltage levels corresponding to pulse widths of the differential internal clock signals in response to a pump control signal; a comparison control unit for outputting the pump control signal and a comparison control signal in response to the differential internal clock signals; a voltage comparison unit for comparing the voltage levels converted from the charge pump unit in response to the comparison control signal, and outputting a counting control signal; a counter for increasing or decreasing a plurality of bit counter signals by a predetermined unit in response to the counting control signal; and a D/A converter for dividing a reference voltage at a predetermined ratio in response to the plurality of bit counter signals and outputting the duty ratio correcting signals.