Patent ID: 9171824
Filing Date: 2015-10-27
Classification: G06F,G11C,H01L

Abstract:
1. A stacked semiconductor device assembly comprising: first and second substantially identical integrated circuit (IC) devices, each of the first and second IC devices including: first interface circuits each having a first capacitance; second interface circuits each having a second capacitance that is lower than the first capacitance; a first set of through vias coupled to respective ones of the first interface circuits; and a second set of through vias coupled to respective ones of the second interface circuits; and wherein the first and second IC devices are stacked one on top of another and offset from each other such that the first set of through vias of the first IC device are aligned with and electrically connected to respective ones of the second set of through vias of the second IC device, and the first interface circuits of the first IC device are electrically coupled to the second interface circuits of the second IC device via the first set of through vias of the first IC device and the respective ones of the second set of through vias of the second IC device.