Patent ID: 6635546
Filing Date: 2003-10-21
Classification: G11C,H01L

Abstract:
A method of manufacturing a resistive semiconductor memory device, comprising:forming a plurality of first conductive lines; depositing a first insulating layer over the first conductive lines; patterning the first insulating layer with vias to expose at least some of the first conductive lines; depositing a magnetic stack layer over the first insulating layer and exposed first conductive lines; patterning the magnetic stack layer to form magnetic memory cells and offset conductive lines adapted to couple the exposed first conductive lines to the magnetic memory cells; depositing a second insulating layer over the magnetic memory cells and offset conductive lines; forming vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines within the second insulating layer; and filling the vias and trenches within the second insulating layer with a conductive material, wherein at least one of patterning the magnetic stack layer to form magnetic memory cells and offset conductive lines or forming vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines win the second insulating layer comprise a single etch process.