Patent ID: 6046949
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A semiconductor integrated circuit, comprising:at least one bit line;at least one memory cell connected to said bit line;at least one precharge circuit connected to said bit line for precharging said bit line; andan electric potential converting circuit connected to said bit line for converting an electric potential of said bit line,wherein said electric potential converting circuit includes first to third transistors which are sequentially connected in series between first and second potentials,an output of said electric potential converting circuit is a node of said second and third transistors,said first transistor receives a mode signal at a control electrode and is turned OFF or ON depending on whether said mode signal indicates a predetermined mode,a control electrode of said second transistor is connected to said bit line,said third transistor receives said mode signal at a control electrode and is turned ON or OFF depending on whether said mode signal indicates said predetermined mode, andsaid precharge circuit receives said mode signal and precharges said bit line to an electric potential with which said second transistor is turned OFF only when said mode signal indicates said predetermined mode.