Patent ID: 9116799
Filing Date: 2015-08-25
Classification: G06F

Abstract:
1. A method comprising: determining at a pipeline circuit, a first effective address based a sum of a first value and a second value, the first effective address based upon an actual value of a first carry-in into a bit-wise region of the first and second values, wherein the bit-wise region includes a predefined internal region of bits of the first and second values; determining at the pipeline circuit, a second effective address based a sum of a third value and a fourth value, the second effective address based upon an actual value of a second carry-in into the bit-wise region of the third and fourth values; receiving, at a collision detector circuit, corresponding bits from the bit-wise region of each of the first, second, third, and fourth values; determining a plurality of speculative results based upon the bits of the bit-wise regions of the first, second, third, and fourth values and based upon a plurality of speculative carry-in values, the speculative carry-in values being speculative of the actual first and second carry-in values; and asserting an indicator to indicate a memory access collision, the indicator based on at least one result of the plurality of speculative results, and in response to receiving the actual value of the first carry-in and the actual value of the second carry-in from the pipeline circuit.