Patent ID: 6074429
Filing Date: 2000-06-13
Classification: G06F

Abstract:
A method of providing a circuit structure contained in a circuit layout, said method comprising:a) selecting a gate from an original circuit as a selected gate;b) constructing a window around the selected gate as an original window;c) constructing a set of alternate structures for the original window;d) forming a new window;e) substituting the new window for the original window to form a new circuit; andf) sizing the new circuit by:1) selecting a next gate from the new circuit as a selected gate;2) assigning an equivalent inverter size factor (A.sub.inv) to the selected gate;3) selecting a next transistor stack in the selected gate as a selected stack;4) assigning a stack size factor (A.sub.stack) to the selected stack;5) selecting a next transistor in the selected stack as a selected transistor;6) assigning a transistor size factor (A.sub.t) to the selected transistor;7) calculating a total size factor A.sub.tot =A.sub.inv *A.sub.stack *A.sub.t ;8) repeating substeps (5), (6), and (7) as a first loop selecting a different transistor as the selected transistor;9) repeating steps (3), (4), (5), (6), (7), and (8) as a second loop selecting a different transistor stack as the selected stack;10) repeating steps (1), (2), (3), (4), (5), (6), (7), (8) and (9) as a third loop selecting a different gate as the selected gate; and11) distributing allocated area to transistors in proportion to the total size factor (A.sub.tot).