Patent ID: 8183093
Filing Date: 2012-05-22
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having a laminated structure comprising a first semiconductor element and a wiring circuit layer, wherein the wiring circuit layer comprises a wiring part, an insulating part, and first and second main surfaces, wherein the first semiconductor element is laminated and connected to the first main surface of the wiring circuit layer, and wherein the insulating part has a laminated structure comprising a first adhesive layer, a second adhesive layer, and a base insulating layer between the first and second adhesive layers, wherein the first adhesive layer is disposed on the first main surface of the wiring circuit layer and the second adhesive layer is disposed on the second main surface of the wiring circuit layer, and the first and second main surfaces form a first adhesive surface and a second adhesive surface by the presence of the first adhesive layer and the second adhesive layer, respectively; which method comprises the steps of: (a) laminating the wiring circuit layer on a first metal support substrate, wherein the first adhesive surface is provided on an opposite side of the wiring circuit layer from the first metal support substrate, (b) after the laminating step, bonding the first semiconductor element in a wafer state to the first adhesive surface, and simultaneously connecting an electrode of the first semiconductor element to the first connecting conductor part exposed in at least the first adhesive surface, wherein the first connecting conductor part constitutes a portion of the wiring part of the wiring circuit layer or is connected to the wiring part via a conductive path; and (c) peeling the first metal support substrate from the wiring circuit layer after the bonding step.