Patent ID: 6656777
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A method of manufacturing a solid state imaging device, comprising the steps of:forming a first buried layer of one conductivity type in an interior of a seventh semiconductor layer of opposite conductivity type by introducing one conductivity type impurity into the seventh semiconductor layer by using a first mask; forming a first well region of opposite conductivity type on a surface of the seventh semiconductor layer and over the first buried layer by introducing opposite conductivity type impurity into the seventh semiconductor layer by using the first mask; forming a one conductivity type region connected to the first buried layer and containing the first well region by introducing one conductivity type impurity into the surface of the seventh semiconductor layer; forming a second buried layer of opposite conductivity type, that has higher impurity concentration than the seventh semiconductor layer, under the one conductivity type region, by introducing opposite conductivity type impurity in an interior of the seventh semiconductor layer by using a second mask; forming a second well region of opposite conductivity type that is connected to the first well region, by introducing opposite conductivity type impurity on a surface of the one conductivity type region and over the second buried layer by using the second mask; forming a channel doped layer of one conductivity type by introducing one conductivity type impurity on a surface of the second well region by using the second mask; forming a high concentration buried layer of opposite conductivity type, that has higher impurity concentration than the second well region, in an interior of the second well region under the channel doped layer by introducing opposite conductivity type impurity in the interior of the second well region by using a third mask; forming a gate insulating film on the seventh semiconductor layer by thermal oxidation; forming a gate electrode on the gate insulating film covering the high concentration buried layer and bringing the high concentration buried layer close to a source region side; and forming a source region and a drain region of one conductivity type on the surface of the second well region, on both sides of the gate electrode, and forming an impurity region on a surface of the first well region.