Patent ID: 8669974
Filing Date: 2014-03-11
Classification: G09G

Abstract:
1. A timing controller adapted to a flat display, the timing controller comprising: a voltage detecting circuit for detecting a variation of an operating voltage and thus outputting a reset signal; a clock generator for outputting a start signal and a first clock signal; a first multiplexer, which is controlled by the reset signal and coupled to the start signal and a constant voltage; and a second multiplexer, which is controlled by the reset signal and coupled to the first clock signal and a second clock signal, the second clock signal having a frequency higher than a frequency of the first clock signal, wherein: when the flat display operates normally, the voltage detecting circuit outputs the reset signal having a first level voltage according to existence of the operating voltage to control the first multiplexer to output the start signal to a gate driver of the flat display, and to control the second multiplexer to output the first clock signal to the gate driver; and when the flat display is shut down, the voltage detecting circuit outputs the reset signal having a second level voltage according to the variation of the operating voltage to control the first multiplexer to output the constant voltage to the gate driver, and to control the second multiplexer to output an i