Patent ID: 7808821
Filing Date: 2010-10-05
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a plurality of electrically programmable memory cells; a first latch circuit and a second latch circuit which store the number of times of write to be performed using a write voltage for each memory cell; a third latch circuit which stores data indicating whether to perform write by using an intermediate voltage lower than the write voltage; a fourth latch circuit which stores, for each memory cell, data indicating whether the memory cell has passed predetermined verification; an arithmetic circuit which, whenever write is performed by one of the write voltage and the intermediate voltage, performs a calculation by using the data stored in the first latch circuit, the second latch circuit, the third latch circuit, and the fourth latch circuit, and updates the data stored in the first latch circuit, the second latch circuit, and the third latch circuit; a sense amplifier which performs write by one of the write voltage and the intermediate voltage for each memory cell, in accordance with the data stored in the first latch circuit, the second latch circuit, and the third latch circuit; and a write controller which controls operations of the first latch circuit, the second latch circuit, the third latch circuit, the fourth latch circuit, the arithmetic circuit, and the sense amplifier, wherein the write controller performs predetermined verification for each memory cell, and stores data indicating whether the memory cell has passed the predetermined verification in the fourth latch circuit, stores the number of times of write to be performed by the write voltage after the verification in the first latch circuit and the second latch circuit, and stores data indicating whether to perform write by the intermediate voltage in the third latch circuit, for a memory cell to be written to a voltage level higher than a voltage level of the predetermined verification, updates the number of times of write stored in the first latch circuit and the second latch circuit, whenever write is performed by the write voltage, and determines write by the intermediate voltage in accordance with the data stored in the third latch circuit, after write is performed the number of times of write by the write voltage.