Patent ID: 6475917
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A method for forming upon a substrate employed within a microelectronics fabrication an inter-level metal dielectric (IMD) layer which is planarized with attenuated damage to underlying layers comprising:providing a substrate; forming upon the substrate a patterned microelectronics layer; forming over the substrate an inter-level metal dielectric (IMD) layer further comprising: a first silicon oxide dielectric layer; a second dielectric layer formed employing spin-on-glass (SOG) dielectric material; and planarizing the surface of the inter-level metal dielectric (IMD) layer employing plasma etch back method, wherein the patterned microelectronics layer is formed of material having a greater negative temperature coefficient of etching reaction rate by the plasma etch back method than that of the silicon oxide dielectric material, and wherein the SOG dielectric material is selectively etched at a greater rate than is the silicon oxide dielectric material and the patterned microelectronics layer material.