Patent ID: 8234451
Filing Date: 2012-07-31
Classification: G06F

Abstract:
1. A multicore processor, comprising: a plurality of cache memories configured to store one or more cache lines; and a plurality of processor cores, each associated with one of the cache memories; with each respective cache memory of at least some of the cache memories configured to maintain at least a portion of the respective cache memory in which each cache line is dynamically managed as either local to the associated processor core according to a first level in a cache hierarchy or shared among multiple processor cores according to a second level in the cache hierarchy, with at least some of the shared cache lines assigned as a home location for caching a corresponding portion of the main memory, and with a cache memory associated with a first processor core being configured to retrieve data from a main memory and store the data in a shared cache line in response to memory requests from the first processor core and in response to memory requests from other processor cores.