Patent ID: 6611909
Filing Date: 2003-08-26
Classification: G06F

Abstract:
A digital processor for executing program instructions, the digital processor generating or receiving at least one general state signal for controlling the general state of the digital processor, the digital processor having two pipelining paths, each pipelining path comprising:a translating device for translating sequentially program instructions to microinstructions using the operation codes of the program instructions as an input of or an address to a translating table of microinstruction codes and thereby generating for each program instruction one microinstruction; a buffer connected to the translating device for receiving and storing a plurality of microinstructions generated by the translating device; a selector unit joining the buffers of the two pipelining paths and selecting the correct path for the next instruction depending on the result of executed or predicted program instructions of jump type; and an execution unit connected to the selector unit for receiving microinstructions from the selector unit and executing the microinstructions; wherein the translation device is connected to receive the at least one general state signal and is arranged to translate the program instructions to microinstructions depending on values of the at least one general state signal, and wherein the at least one general state signal comprises a signal indicating whether or not a trace function is enabled in the digital processor, said digital processor executing optimized microinstructions when said trace function is disabled.