Patent ID: 6753700
Filing Date: 2004-06-22
Classification: G06F,H03K,H04L

Abstract:
A communication system, comprising:a transmitter that outputs a differential clock signal via a differential interconnect line and a plurality of data signals via a plurality of single-ended interconnect lines; a receiver that includes a clock buffer, a differential buffer, and a plurality of data buffers; wherein the differential buffer receives the differential clock signal via the differential interconnect line, extracts a DC (Direct Current) voltage level from the differential clock signal, and generates a voltage reference signal using the DC voltage level; wherein the clock buffer receives the differential clock signal via the differential interconnect line, buffers the differential clock signal, and generates an internal clock signal from the differential clock signal wherein a frequency of the internal clock is determined using a voltage bias provided by the voltage reference signal; and wherein each data buffer of the plurality of data buffers receives one data signal of the plurality of data signals via its corresponding single-ended interconnect line of the plurality of single-ended interconnect lines and determines a logic level of its corresponding data signal by comparing a voltage of its corresponding data signal with the voltage reference signal.