Patent ID: 6873670
Filing Date: 2005-03-29
Classification: H03L

Abstract:
1. An apparatus, comprising: a phase-frequency detector circuit that is arranged to produce an UP and DOWN signal in response to a comparison between an input clock signal and a feedback clock signal; a charge pump circuit that is arranged to provide an oscillator control signal, wherein the charge pump circuit is further arranged to increase the oscillator control signal in response to an UP signal, and decrease the oscillator signal in response to a DOWN signal; a voltage-controlled oscillator that is arranged to provide an oscillator signal that has an associated frequency, wherein the voltage-controlled oscillator is configured to change the frequency of the oscillator signal in response to the oscillator control signal; a divider circuit that is configured to provide an output clock signal response to the oscillator signal, wherein the output clock signal is related to the oscillator signal by a divide ratio that corresponds to M, where the divide ratio is adjusted in response to a divider control signal; a window comparator circuit that is configured to provide a count up signal when the oscillator control signal exceeds a first predetermined amount that is associated with a first reference node, and wherein the window comparator is also configured to provide a count down signal when the oscillator control signal is below a second predetermined amount that is associated with a second reference node; and an up-down counter circuit that is configured to provide the divider control signal, wherein the divider control signal increases when the count up signal is evaluated as active, and the divider control signal is decreased when the count down signal is evaluated as active, whereby the window comparator circuit and the up-down counter circuit automatically adjust the divider control signal.