Patent ID: 6295230
Filing Date: 2001-09-25
Classification: G11C,H03K

Abstract:
A memory cell comprising:a tunnel dielectric;a first voltage source;a second voltage source, above the first voltage source during a normal operation state;a floating gate device, coupled between the second voltage source and an output node, wherein a floating gate of the floating gate device is coupled to the tunnel dielectric;a tunnel diode, coupled to the tunnel dielectric, wherein the tunnel dielectric transfers charge between the floating gate and the tunnel diode;a select transistor, coupled between an erase node and the tunnel diode; anda pull-down element, coupled between the first voltage source and the output node, wherein the pull-down element provides a first pull-down current to pull the output node to a voltage level representing a logic low when the floating gate device is programmed, and a second pull-down current that is discharged through the floating gate device to provide a voltage level representing a logic high at the output node when the floating gate device is erased.