Patent ID: 7836282
Filing Date: 2010-11-16
Classification: G06F

Abstract:
1. A computer implemented method for increasing a number of instructions per clock cycle associated with a processor, the computer implemented method comprising: decoding a set of instructions to form a set of decoded instructions; separating within the set of decoded instructions a set of store type instructions from a set of non-store type instructions; folding a store type instruction within the set of store type instructions with a non-store type instruction within the set of non-store type instructions to form a folded instruction, wherein folding the store type instruction within the set of store type instructions with the non-store type instruction within the set of non-store type instructions to form the folded instruction comprises: dispatching the folded instruction to an execution unit for processing; executing the non-store type instruction in the folded instruction during an execution stage of the execution unit to form an executed instruction; performing a store function of the store type instruction during a write back stage of the execution unit; and placing the executed instruction in a reorder buffer.