Patent ID: 7103702
Filing Date: 2006-09-05
Classification: G11C

Abstract:
1. A memory device comprising: a data memory to and from which image data is input and output via a data bus for the data memory; a plurality of buffer circuits for inputting and outputting image data to and from said data memory via a first data bus that has a bus width the same as that of the data bus for said data memory and that is electrically connected to the data bus for said data memory, and inputting and outputting image data to and from a data processing circuit via a second data bus having a bus width smaller than that of the data bus for said data memory; and an arbitration circuit, which is connected between the data processing circuit and said plurality of buffer circuits, for controlling the plurality of buffer circuits in such a manner that image data representing images of different frames is input and output to and from different buffer circuits in a common time period.