Patent ID: 6627502
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A method for forming a MOSFET having shallow, high concentration LDD regions and low source/drain series resistance comprising:(a) providing a semiconductor substrate having an active region enclosed by field isolation; (b) forming a gate electrode stack over said active region; (c) forming rectangular spacers along each side of said gate stack; (d) forming amorphous silicon sidewalls alongside each of said rectangular spacers; (e) implanting dopant ions into exposed portions of said active region and into said amorphous silicon sidewalls; (f) performing a first annealing of said substrate thereby simultaneously diffusing said implanted ions from said amorphous silicon sidewalls into said substrate forming lightly doped drain regions, crystallizing said amorphous silicon sidewalls thereby forming polysilicon sidewalls, and diffusing said implanted ions into said active region thereby forming source/drain regions; (g) depositing a refractory metal layer on said substrate; (h) depositing a refractory metal nitride layer on said refractive metal layer; (i) performing a second annealing of said wafer thereby forming a metal silicide on said exposed active regions and on said polysilicon sidewalls; and (j) removing residual said refractory metal and said refractory metal nitride.