Patent ID: 8617946
Filing Date: 2013-12-31
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, the method comprising: forming a metallic gate electrode of an NMOS transistor and a dummy gate electrode of a PMOS transistor over a substrate; forming a dielectric layer surrounding the metallic gate electrode of the NMOS transistor and the dummy gate electrode of the PMOS transistor after the forming the metallic gate electrode of the NMOS transistor and the dummy gate electrode of the PMOS transistor; removing the dummy gate electrode of the PMOS transistor to form an opening after the formation of the dielectric layer; and forming a gate electrode of the PMOS transistor over the substrate within the opening; wherein the forming the metallic gate electrode of the NMOS transistor comprises: forming a first gate dielectric structure over the substrate; forming a first work function metallic layer over the first gate dielectric structure; forming a first silicon layer over the first work function metallic layer; and forming a silicide layer over the first silicon layer before forming the gate electrode of the PMOS transistor.