Patent ID: 9203604
Filing Date: 2015-12-01
Classification: H03L,H04L

Abstract:
1. A method of operating an integrated circuit that receives incoming data bits, comprising: using a data latch to capture the incoming data bits with a clock signal while the integrated circuit is placed in a first clocking mode; using the data latch to capture the incoming data bits with an inverted version of the clock signal while the integrated circuit is placed in a second clocking mode; using a multiplexer to receive the clock signal and the inverted version of the clock signal, to route the clock signal to the data latch during the first clocking mode, and to route the inverted version of the clock signal to the data latch during the second clocking mode; using an additional multiplexer to receive the clock signal and the inverted version of the clock signal, to route the inverted version of the clock signal to an output of the additional multiplexer during the first clocking mode, and to route the clock signal to the output of the additional multiplexer during the second clocking mode; comparing first data latching performance obtained during the first clocking mode with second data latching performance obtained during the second clocking mode; and selecting only one of the first and second clocking modes for use during normal operation of the integrated circuit as a function of the comparison.