Patent ID: 6362036
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method for making a VDMOS transistor structure comprising:forming a semiconductor layer of first conductivity type on a substrate of second conductivity type; forming a first region of first conductivity type extending into the semiconductor layer from a major surface thereof farther from the substrate; forming a second region of second conductivity type extending from the major surface into the semiconductor layer around the first region and laterally limiting the first region; forming a third region of second conductivity type extending from the major surface into the first region and defining a body region of a VDMOS transistor; forming a fourth region of first conductivity type extending from the major surface into the third region and defining a source region of the VDMOS transistor, the fourth region also defining a first channel with edges of the third region; forming a fifth region of first conductivity type and extending from the major surface into the first region, the first region and the fifth region together defining a drain region of the VDMOS transistor; and forming a sixth region of second conductivity type extending from the major surface into the first region, in contact with the second region, and delimiting a second channel with an edge of the third region, the third region and the sixth region respectively defining source and drain regions of a MOS transistor which acts as a voltage limiter for the VDMOS transistor.