Patent ID: 8071968
Filing Date: 2011-12-06
Classification: H01L

Abstract:
1. A phase change memory device comprising: a silicon substrate having a cell region and a peripheral region; a first insulation layer formed in the cell region of the silicon substrate and having first holes; cell switching elements formed in the first holes; heaters formed on the cell switching elements; a gate formed in the peripheral region of the silicon substrate and having a gate insulation layer, a first conductive layer stacked on the gate insulation layer, a second conductive layer stacked on the first conductive layer and a hard mask layer stacked on the second conductive layer, the gate being formed higher than the cell switching elements formed in the cell region; a second insulation layer having second holes which expose the heaters formed in the cell region, and the second insulation layer exposes the hard mask layer of the gate formed in the peripheral region; a barrier layer formed on sidewalls of the second holes and on the second insulation layer; a phase change layer formed in and over the second holes in which the barrier layer is formed; and top electrodes formed on the phase change layer, wherein the cell switching elements comprise vertical PN diodes having a P-type silicon layer stacked on top of an N-type silicon layer.