Patent ID: 8884262
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A non-volatile memory device, comprising: a lower molding layer formed on a substrate; a first horizontal interconnection formed on the lower molding layer; an upper molding layer formed on the first horizontal interconnection; a first interlayer insulating layer formed on the upper molding layer; a second interlayer insulating layer covering sidewalls of the lower molding layer, the upper molding layer and the first horizontal interconnection; and a pillar connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer, wherein the pillar comprises a lower part disposed on the same level as the first horizontal interconnection and having a first width, and an upper part disposed on a higher level than the first horizontal interconnection and having a second width different from the first width.