Patent ID: 7307890
Filing Date: 2007-12-11
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a memory cell array including a plurality of memory cells; and a plurality of the page buffers coupled to the memory cell array through a sensing line, wherein each page buffer includes: first and second latch circuits configured to store a program data bit; a data transmission module configured to transfer the program data bit to a selected bitline through the sensing line, the program data bit transferred from the second latch circuit and stored in the first latch circuit during a programming operation; and a copy-back programming circuit coupled between the first latch circuit and the sensing line and configured to conduct a copy-back programming operation, wherein the second latch circuit is configured to be activated in the programming operation and not activated in the copy-back programming operation, and the first latch circuit is configured to be activated in both the copy-back programming operation and the programming operation.