Patent ID: 6326852
Filing Date: 2001-12-04
Classification: H03L

Abstract:
A phase lock loop comprising:a detector for comparing a phase or frequency characteristic of an input signal to a phase or frequency characteristic of a timing reference signal;a timing reference signal generator, connected in feedback fashion to provide a timing reference signal to the detector; anda charge pump connected to receive control signals developed by the detector, the charge pump sourcing and sinking a characteristic current in response to the control signals, the charge pump constructed of two parallel current paths, each a mirror image of the other, and both coupled between a pump-up current source and a pump-down current source, wherein the charge pump includes feedback means coupled between an output and an adjustment current source, the adjustment current source providing a compensating current operative to balance currents in the pump-up current source and the pump-down current source so as to minimize DC offsets at the output.