Patent ID: 8013367
Filing Date: 2011-09-06
Classification: H01L

Abstract:
1. A semiconductor structure comprising: at least one field effect transistor located upon and within a surface of a semiconductor substrate, said at least one field effect transistor having a channel within said semiconductor substrate located beneath a patterned gate conductor in which the channel has an ordered, nanosized pattern defined by a plurality of openings presented within the semiconductor substrate in which each opening is separated from another opening by an unetched portion of the semiconductor substrate, wherein each opening and said unetched portion of the semiconductor substrate have a width of less than 50 nm, and wherein a gate dielectric of said at least one field effect transistor is located on sidewalls and a bottom wall of each of said plurality of openings and on an upper surface of the semiconductor substrate between each of said plurality of openings, and said gate dielectric not completely filling each of said plurality of openings, and further wherein said patterned gate conductor includes a lower portion that is present in each of said plurality of openings and an upper portion that extends above each of said plurality of openings.