Patent ID: 7154807
Filing Date: 2006-12-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising; an odd-numbered memory block selected by an odd-numbered column address; an even-numbered memo block selected by an even-numbered column address; a redundant memory block arranged at the regional border of the odd-numbered memory block region and the even-numbered memory block region; and a memory cell array, wherein, when data read out from the odd-numbered memory block and from the even-numbered memory block are outputted alternately and continuously to conduct a burst operation depending on a high-order column address obtained by repeatedly incrementing an address which is an inputted initial column address from which a lowest-order bit is eliminated, the even-numbered memory block is selected by a +1 high-order column address which is the high-order column address to which “1” is added in case the initial column address is an odd-numbered address, and wherein the memory cell array comprises: an odd-numbered memory block region consisting of the odd-numbered memory block arranged on one side in a column direction for the memory cell array; and an even-numbered memory block region consisting of the even-numbered memory block arranged on another side in a column direction for the memory cell array.