Patent ID: 6625719
Filing Date: 2003-09-23
Classification: G06F

Abstract:
A data processing system comprising:A. a memory having a plurality of addressable memory locations containing instructions and operands; and B. a data processing device coupled to the memory, the data processing device including: i. an arithmetic logic unit arranged to obtain a result from an operation on operands applied to said arithmetic logic unit; ii. a register file coupled to the arithmetic logic unit and receiving the result of the operation performed in the arithmetic and logic unit; iii. an address register file; iv. an instruction register coupled to the memory and operative to hold a program instruction; and v. an instruction unit coupled to the register file, the address register file and the arithmetic logic unit, the instruction unit including circuits producing control signals to control the operations of the data processing device in response to decoding a program instruction contained in the instruction register, the instruction unit including operation circuits responsive to an operation field in an instruction, destination circuits responsive to a destination field in the instruction, first operand circuits responsive to a first operand field in the instruction, and second operand circuits responsive to a second operand field in the instruction: a. the operation circuits producing operation control signals to control operation of the arithmetic logic unit; b. the destination circuits producing destination control signals to select a register in the register file to contain a result; c. the first operand circuits producing first operand control signals selecting one of: the contents of a register in the register file, and the contents of a first memory location addressed by a first displacement value combined with an address in a first register in the address register file; and d. the second operand circuits producing second operand control signals selecting one of: immediate data contained in the second operand field, and the contents of a second memory location addressed by a second displacement value to be combined with an address in a second register in the address register file.