Patent ID: 6304483
Filing Date: 2001-10-16
Classification: G11C

Abstract:
A memory cell, comprising;a flip-flop that includes a cross-coupled pair of inverters;wherein the inverters each include a pair of complementary, vertical transistors, each transistor utilizing one of a pair of single pillars of semiconducting material, with a gate contact that interconnects the gates of the inverters and acts as the input of the inverter and a shunt that interconnects a first source/drain region of the complementary transistors and acts as the output of the inverter;a first vertical, access transistor with a gate that is coupled to a word line and a first source/drain region coupled to the output of one of the inverters and a second source/drain region that is coupled to a first bit line; anda second vertical, access transistor with a gate that is coupled to the word line and a first source/drain region coupled to the output of the other inverter and a second source/drain region that is coupled to a second bit line.