Patent ID: 8315078
Filing Date: 2012-11-20
Classification: G06F,G11C,Y02D

Abstract:
1. A content addressable memory comprising: a match line; a compare data line; a valid data line; a memory cell to store a tag data bit; a first inverter having an input connected to the memory cell, and having an output; a first pass gate having an input connected to the output of the first inverter, coupled to the compare data line, and having an output; a second inverter having an input connected to the output of the first inverter, and having an output; a second pass gate having an input connected to the output of the second inverter, coupled to the compare data line, and having an output; a third inverter having an input connected to the outputs of the first and second pass gates, and having an output; a gate to drive the match line, and having an input connected to the output of the third inverter; a first P-channel transistor connected to the valid data line and the first pass gate to pull up high the input of the first pass gate in response to the valid data line going low; a second P-channel transistor connected to the valid data line and the second pass gate to pull up high the input of the second pass gate in response to the valid data line going low.