Patent ID: 7583683
Filing Date: 2009-09-01
Classification: H04J,H04L

Abstract:
1. A router including processors or processing elements in line interface modules and a switching module, wherein the processor or processing element in each line interface module looks up a FIB (Forward Information Base) to determine a output port number for each arriving packet and sends the packet to the switching module after recording the output port number on a temporary packet header and a switching and queuing processor in the switching module sends the packets arriving from the line interface modules to an output queue connected to the destination line interface module according to the output port number field on the temporary packet header, additionally including a clock synchronizer, wherein the clock synchronizer makes the time of each module almost identical by providing common clock and reset signals to the line interface and switching modules; wherein the clock synchronizer relates the period of the reset signal to a maximum packetization period of the real-time traffic.