Patent ID: 8239438
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. A computer-implemented method comprising: providing a computer processor comprising: wherein the computer processor is configured to perform a dot product operation by: by the dot product support unit, aligning and then summing products generated by the plurality of processing lanes of the vector arithmetic unit; by the computer processor, receiving a single, predefined instruction for adding at most a predefined count of floating point addends, wherein the predefined count of floating point addends is equal to a product of: (i) a count of the plurality of processing lanes and (ii) the predefined count of operands; wherein the plurality of processing lanes is fewer in number than the predefined count of floating point addends, wherein the predefined instruction is identifiable by an associated opcode; and responsive to the predefined instruction for adding at most the predefined count of floating point addends, performing, by the vector arithmetic unit and the dot product support unit of the computer processor, a predefined operation to add the at most the predefined count of floating point addends using a single pass through the fewer processing lanes of the computer processor, wherein the predefined operation comprises: wherein the instruction is configured to designate one or more vector arithmetic units to perform vector operations and one or more vector arithmetic units to perform scalar operations; and wherein the scalar operations are configured to perform a combination of both addition and subtraction operations.