Patent ID: 7200829
Filing Date: 2007-04-03
Classification: G06F,Y02E,Y04S

Abstract:
1. A method of floorplanning an integrated circuit chip in a technology, comprising in the following order the steps of: a) routing a plurality of non-grid power routes corresponding to a plurality of integrated circuits using an initial width for each of said plurality of non-grid power routes, each of said non-grid power routes extending between a power distribution network and a corresponding respective one of said plurality of integrated circuits; b) performing at least one electrical check of said plurally of integrated circuits; c) determining whether any one or more of said plurality of non-grid power routes has at least one electrical violation; d) reporting, to a list, a number of integrated circuits that have at least one electrical violation; e) for each one of said plurality of non-grid power routes having at least one electrical violation, assigning that one of said plurality of non-grid power routes a new width greater than said initial width; f) prior to re-routing said plurality of non-grid power routes, repeating steps b), c) and d) at least once using the one or more new widths assigned in step e) and any of said initial widths remaining after step e); and f) re-routing said plurality of non-grid power routes using the one or more new widths assigned in step e).