Patent ID: 8042085
Filing Date: 2011-10-18
Classification: G06F

Abstract:
1. A method for generating a verified circuit design, comprising: receiving a circuit design specification and one or more criteria associated with said circuit design specification; generating at least a design netlist and one or more constraints associated with said design netlist based on said received circuit design specification and criteria; wherein said constraints comprise one or more constraints identifying false paths in said design netlist; performing by a computing apparatus a functional analysis to determine if the generated design netlist and constraints meet the received circuit design specification and criteria; if said generated design netlist and constraints meet the received circuit design specification and criteria in the functional analysis, performing at least one of path compaction and constraint compaction on said generated design netlist and constraints, wherein said path compaction comprises at least one of: if a plurality of paths in said design netlist each include a constant net, identifying all paths through said constant net as false paths with a common constraint; and, if the design netlist includes re-convergent nets, identifying all paths through said re-convergent nets as false paths with a common constraint; performing by a computing apparatus a timing analysis on the compacted design netlist and constraints to determine if the compacted design netlist and constraints meet the received circuit design specification and criteria; and if said generated design netlist and constraints meet the received circuit design specification and criteria in the timing analysis, performing a path optimization on said compacted design netlist to generate a verified circuit design.