Patent ID: 9094333
Filing Date: 2015-07-28
Classification: G06F,H04L

Abstract:
1. An adapter coupled to a host computing device for sending and receiving information, comprising: a port complex having: a processor complex having a plurality of processors for processing frames complying with different protocols and received by any of the plurality of ports; wherein each processor of the processor complex can process frames complying with any of the different protocols and originating from any of the plurality of ports; a message queuing system (MQS) interfacing with the port complex and the processor complex for managing messages for the plurality of processors regarding the received frames complying with different protocols; a general processor for configuring the adapter; and a memory interface module that manages requests from any processor of the processor complex; the general processor and any component of the port complex to access a local adapter memory and a host computing device memory for processing received frames, transmitting frames and configuring the adapter; wherein an arbiter of the memory interface module arbitrates between requests for the local adapter memory and the host computing device memory.