Patent ID: 8854908
Filing Date: 2014-10-07
Classification: G11C

Abstract:
1. A memory module comprising: a circuit board comprising a plurality of contacts, wherein the plurality of contacts are configured to be coupled to an external processor, and configured to receive storage data and register data from the external processor; a register module coupled to a first plurality of contacts on the circuit board, wherein the register module is configured to store the register data; and a plurality of DRAMs coupled to a second plurality of contacts on the circuit board and coupled to the register module, wherein a DRAM of the plurality of DRAMs includes a plurality of memories and a test module; wherein the test module is configured to write a first write data pattern into at least a first portion of the plurality of memories in response to a data pattern value selected from a group consisting: a total error count, an overflow flag; wherein the test module is configured to read a read data pattern from the plurality of memories; wherein the test module is configured to compare the first write data pattern to the read data pattern; wherein the test module is configured to report errors in response to a comparison of the write data pattern to the read data pattern.