Patent ID: 6826691
Filing Date: 2004-11-30
Classification: G06F,H04L

Abstract:
An arrangement for encrypting/decrypting data comprising:random access memory means for holding the data; a processor for processing the data, the processor having a memory map including a first portion mapped onto the random access memory and a second portion; and control means coupled to receive an instruction to write data to an address in the second portion of the memory map and in response thereto to write the data in a predetermined permuted form to an associated address in the random access memory, whereby data read form said associated address in the random access memory is an encrypted/decrypted version of the data written to said address in the second portion of the memory map, wherein the first portion corresponds to a first address range of a physical memory and the second portion corresponds to a second address range not corresponding to the physical memory and the memory map includes a third portion corresponding to a third address range not corresponding to the physical memory and wherein the control means are operable to receive an instruction to write data to an address in the third portion of the memory map and in response thereto to write the data in a different predetermined permuted form than the permutated form of the second portion to an associated address in the random access memory, whereby data read from said associated address in the random access memory is an encrypted/decrypted version of the data written to said address in the third portion of the memory map.