Patent ID: 6738881
Filing Date: 2004-05-18
Classification: G06F

Abstract:
A digital system with a multi-channel direct memory access (DMA) controller, wherein the DMA controller comprises:a plurality of channel circuits each having at least one channel address output node for providing a channel address and at least one request output; and a plurality of port circuits each having a plurality of channel address input nodes connected to a respective channel address output node of the plurality of channel circuits, each port circuit of the plurality of port circuits having a memory address output node for providing a memory address selected from the plurality of address input nodes to a respective associated memory resource; and wherein each port circuit further comprises a scheduler circuit connected to the request outputs on the plurality of channel circuits, the scheduler circuit operable to select the next request that will be served by the port, such that the plurality of port circuits are operable to access the respective associated memory resources simultaneously; and wherein each port circuit further comprises a port control circuit having a channel interface node connected to the respective scheduling circuit to receive a selected channel address and a memory interface node for providing the memory address and an access protocol to the respective associated memory source, such that all of the plurality of port control circuits have identical channel interface nodes.