Patent ID: 7027326
Filing Date: 2006-04-11
Classification: G11C,H01L

Abstract:
1. A memory cell configured to be coupled to a first control line, at least one second control line and at least one bitline for selectively accessing the memory cell, the memory cell comprising: a write switch having a control terminal and first and second terminals, the first terminal of the write switch coupled to the at least one bitline, the control terminal of the write switch coupled to the first control line; a two terminal semiconductor device having first and second input terminals, the first input terminal of the two terminal semiconductor device coupled to the second terminal of the write switch, and the second input terminal of the two terminal semiconductor device coupled to the at least one second control line, wherein the two terminal semiconductor device is adapted to have a capacitance when a voltage on the first input terminal relative to the second input terminal is above a threshold voltage and to have a lower capacitance when the voltage on the first input terminal relative to the second input terminal is less than the threshold voltage; a read select switch having a control terminal and first and second terminals, the control terminal of the read select switch coupled to the at least one second control line, the first terminal of the read select switch coupled to the at least one bitline; and a read switch having a control terminal and first and second terminals, the control terminal of the read switch coupled to the first input terminal of the two terminal semiconductor device and coupled to the second terminal of the write switch, the first terminal of the read switch coupled to the second terminal of the read select switch, and the second terminal of the read switch coupled to ground.