Patent ID: 8692575
Filing Date: 2014-04-08
Classification: G06F

Abstract:
1. An asynchronous logic element, comprising: a plurality of edges providing bit-level asynchronous communication with at least one contiguously neighboring logic element, each edge being configured to be able to contain at least one state token having a value of logical “0” or logical “1”; and self-timed computational circuitry configured to perform a logic operation, the computational circuitry having at least one input and at least one output, each computational circuitry input being configured to pull a state token from an associated edge location and each computational circuitry output being configured to push a state token onto a different associated edge location, the computational circuitry being configured to utilize at least one state token pulled from an edge location associated with a computational circuitry input as at least one logic input to produce an output state token reflecting the result of the logic operation and to push the output state token from at least one computational circuitry output onto at least one edge, wherein the associated edge locations have three possible states, the possible states being an empty state occurring when the edge location does not contain a state token and two non-empty states occurring when the edge location contains a state token having a value of either “0” or “1”, and wherein the computational circuitry is configured to trigger performance of the logic operation when the computational circuitry inputs all contain valid state tokens pulled from the edge locations associated with the inputs, the computational circuitry outputs are all empty, and all edge locations associated with the computational circuitry outputs are in the empty state.