Patent ID: 6278647
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A semiconductor memory device comprising:an even number of banks; each bank including:an odd number, equal to or more than three, of sense amplifier rows:an odd number of local data buses each disposed above and along corresponding sense amplifier row; anda plurality of memory cell blocks interposed between adjacent two of said sense amplifier rows, each memory cell block having memory cells arranged in rows and columns, andfirst and second global data buses, commonly used for said banks, coupled to said local data buses for said banks in such a way that two memory cells in a selected memory cell block are simultaneously accessed through adjacent two of said local data buses sandwiching said selected memory cell block and through said first and second global data buses,wherein the number of local data buses for said banks coupled to said first global data bus is equal to the number of local data buses for said banks coupled to said second global data bus.