Patent ID: 6642100
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising the steps of:preparing an active matrix provided with a transistor and a first insulating layer formed around the transistor; forming a capacitor structure on top of the first insulating layer, wherein the capacitor structure includes a capacitor thin film made of a ferroelectric material between a top electrode and a bottom electrode; forming a second insulating layer on top of the capacitor structure and the transistor; forming a first contact hole exposing the top electrode and forming a second contact hole exposing a drain/source region of the transistor by selectively etching the second insulating layer; forming a TiN adhesion layer on the top electrode for enhancing a connection between the top electrode and a subsequently applied metal interconnection layer; forming the metal interconnection layer on top of said TiN adhesion layer and patterning the metal interconnection layer into a predetermined configuration to electrically connect the transistor to the capacitor structure, wherein the metal interconnection layer is connected to the top electrode via the TiN adhesion layer; forming a hydrogen barrier layer provided with an aluminum oxide (AlxOy) layer on top of the metal interconnection; and forming an inter-metal dielectric (LMD) layer on top of the hydrogen barrier layer, wherein the LIVID layer is a triple layer provided with a SIGN layer, a SOG layer, and SRO layer.