Patent ID: 6693834
Filing Date: 2004-02-17
Classification: G03F,G11C,H01L

Abstract:
A test device for detecting alignment of bit lines and bit line contacts in DRAM devices, wherein the test device is disposed in a scribe line region of a wafer, comprising:an active area disposed in the scribe line area; parallel first and second bar-type bit line contacts, disposed in the active area, wherein the first and second bar-type bit line contacts are shorter than the active area, and each bar-type line contact has an outside surface and two terminals; first and second bit lines disposed in the active area, wherein the first bar-type bit line contact is covered by the first bit line with a first outside surface aligned with the outside surface of the first bar-type contact, and the second bar-type bit line contact is covered by the second bit line with a second outside surface aligned with the outside surface of the second bar-type contact; first and second plugs disposed on the two terminals of the first bit line respectively; and third and fourth plugs disposed on the two terminals of the second bit line respectively.