Patent ID: 9153625
Filing Date: 2015-10-06
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a plurality of memory cells arranged in a matrix, each including a cell transistor and a variable resistance memory element coupled to one end of the cell transistor; a plurality of word lines corresponding to rows of the plurality of memory cells, and coupled in common to gates of the cell transistors included in the plurality of memory cells arranged in the respective rows; a plurality of first data lines corresponding to rows or columns of the plurality of memory cells, and coupled in common to the variable resistance memory elements included in the plurality of memory cells arranged in the respective rows or columns; a plurality of second data lines corresponding to the rows or the columns of the plurality of memory cells, and coupled in common to the other ends of the cell transistors included in the plurality of memory cells arranged in the respective rows or columns; a plurality of fixed resistance elements coupled in series; a plurality of reference cell transistors; a plurality of reference word lines corresponding to the plurality of reference cell transistors, and coupled to gates of the respective reference cell transistors; a first reference data line coupled to one end of a resistance path in which the plurality of fixed resistance elements are arranged; and a second reference data line coupled in common to one ends of the plurality of reference cell transistors, wherein the other end of each of the plurality of reference cell transistors is coupled to any one of coupling points of the fixed resistance elements or the other end of the resistance path.