Patent ID: 8930627
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A computer program product for mitigating conflicts for shared cache lines between an owning core that currently owns a cache line and a requestor core, the computer program product comprising: a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: determining whether the owning core is operating in one of a transactional mode and a non-transactional mode; setting a hardware-based reject threshold at a first value when the owning core is determined to be operating in the transactional mode and a second value when the owning core is determined to be operating in the non-transactional mode; taking a first action to encourage sharing of the cache line between the owning core and the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the first value when the owning core is determined to be operating in the transactional mode; and taking a second action, which is different from the first action, to encourage sharing of the cache line between the owning core and the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the second value when the owning core is determined to be operating in the non-transactional mode.