Patent ID: 9087739
Filing Date: 2015-07-21
Classification: G03F,H01L

Abstract:
1. A method of semiconductor integrated circuit manufacture including patterning of a hard mask for transferring a pattern to a material underlying said hard mask, said method including steps of modeling processes to be used in said patterning of said hard mask and transferring a pattern of said hard mask to said underlying material to create process and lithographic exposure models, each of said process and lithographic exposure models including a process model for etching said material underlying said hard mask and a process model for etching said hard mask, respectively, wherein said process model for etching material underlying said hard mask characterizes observed differences in shape of features of said of said hard mask and shapes of features resulting from etching said material underlying a hard mask, and wherein said process model for etching said hard mask characterizes observed differences in shape between features of a pattern formed in a resist by lithographic exposure and shapes of features formed in said hard mask by said etching a hard mask by a process modeled in said modeling step, creating a model based hard mask pattern for patterning said material underlying said hard mask based on a design pattern and said process model for etching said material underlying said hard mask by a process modeled in said modeling step, creating one or more model based resist patterns based on said hard mask pattern and said process model for etching said hard mask, transferring said one or more resist patterns to said hard mask to form said hard mask pattern, and transferring said hard mask pattern to said material underlying said hard mask to form said design pattern in said material underlying said hard mask.