Patent ID: 6782404
Filing Date: 2004-08-24
Classification: H04L

Abstract:
A method of improving over-sampled timing signal jitter tolerance in a q-times over-sampled architecture, said method comprising:(a) phase sampling said over-sampled timing signal to produce a plurality of input phase samples &phgr;in, where &phgr;in&egr;{&phgr;1, &phgr;2, . . . , &phgr;q}; (b) for each one of said input phase samples &phgr;in: (i) initializing an output phase value put &phgr;out=&phgr;in; (ii) deriving a difference vector di for each one of said input phase samples &phgr;in, where di=Fj(n,k), F denotes a vector operation, n is the number of said input phase samples, k is a pre-defined threshold value, and j represents a filter order value; (iii) applying a predefined scaling coefficient ai to each one of said difference vectors di to produce a scaled difference vector ai di corresponding to each one of said difference vectors; (iv) deriving a sum dj=&Sum;i=1n&it;ai&it;diâ€ƒof said scaled difference vectors; (v) incrementing said output phase value &phgr;out by 1 if dj>k; (vi) decrementing said output phase value &phgr;out by 1 if dj(vii) maintaining said output phase value &phgr;out unchanged if âˆ’k&lE;dj&lE;k; and, (viii) selecting said output phase value &phgr;out to represent said input phase sample &phgr;in.