Patent ID: 6295620
Filing Date: 2001-09-25
Classification: G11C

Abstract:
A test facilitation circuit integrated into a memory device having a main memory circuit with a plurality of memory cells, to facilitate testing of said main memory circuit by external test equipment, comprising:a first auxiliary memory circuit storing test data;an internal data bus coupling said first auxiliary memory circuit to said main memory circuit;an interface circuit receiving address information, a read request signal, and a write request signal from said external test equipment, and transferring said test data to and from said external test equipment;an auxiliary memory controller coupled to said interface circuit, controlling access to said first auxiliary memory circuit; anda main memory controller coupled to said interface circuit, receiving a first test mode signal from said external test equipment, responding to said write request signal when said first test mode signal is in one state by directing said auxiliary memory controller to transfer said test data from said interface circuit to said first auxiliary memory circuit, then by transferring said test data from said first auxiliary memory circuit to said main memory circuit, and responding to said write request signal when said first test mode signal is another state by transferring test data previously stored in said first auxiliary memory circuit immediately from said first auxiliary memory circuit to said main memory circuit.