Patent ID: 8572298
Filing Date: 2013-10-29
Classification: G06F

Abstract:
1. An integrated circuit comprising: a predefined logic area including a microprocessor coupled to a plurality of peripheral devices over a system bus, at least one of the peripheral devices comprising an external bus interface having access to input and output buffers; a customizable logic area accessible by the microprocessor over the system bus, the customizable logic area configured to provide at least one of scrambling and de-scrambling function, wherein the scrambling and de-scrambling function are enabled based on an instruction received through a software interface; a first I/O bus to send data from the integrated circuit; a second I/O bus to receive data into the integrated circuit: a first multiplexer circuitry disposed in the predefined logic area and having a first input coupled to an output of the external bus interface via a first route, a second input coupled to the customizable logic area, wherein the second input of the first multiplexer is configured to receive scrambled data from the customizable logic area, and an output coupled to the first I/O bus, the output of the external bus interface also coupled to the first input of the first multiplexer circuitry and the customizable logic area via a second route to enable routing of data from the output of the external bus interface to the customizable logic area via the second route; a second multiplexer circuitry disposed in the predefined logic area and having a first input coupled to the customizable logic area, wherein the first input of the second multiplexer is configured to receive de-scrambled data from the customizable logic area, a second input coupled to the second I/O bus via a third route and coupled to the customizable logic area via a fourth route, and an output coupled to an input of the external bus interface; and a multiplexer control register coupled to the first multiplexer circuitry and second multiplexer circuitry, wherein the multiplexer control register is configured to select the output of the first multiplexer circuitry and the output of the second multiplexer circuitry based on the instruction received through the software interface.