Patent ID: 6251766
Filing Date: 2001-06-26
Classification: H01L,H05K,Y02P

Abstract:
A process for forming an improved solder interconnection on a semiconductor device and supporting substrate comprising:forming a raised solder wettable pad structure on said supporting substrate by depositing a first layer on said supporting substrate and depositing a second layer over said first layer, said first and second layers are substantially circular, each having a respective diameter, said diameter of said second layer is in the range of 30-70% of said diameter of said first layer, said first layer has a thickness at least 10% of said diameter of said first layer, said thickness of said first layer is in the range of 33-41 .mu.m (0.0013 to 0.0016 inches) and said second layer has a thickness in the range of 63-76 .mu.m (0.0025 to 0.0030 inches);said substrate is one of the group consisting of an organic chip carrier, a ceramic chip carrier, and an organic circuit board;depositing a layer of solder over the resultant pad structure;placing said semiconductor device, provided with a corresponding solder wettable pad, on said supporting substrate; andheating to join said pad on said semiconductor device to said pad structure on said substrate by reflowing said layer of solder.