Patent ID: 8614697
Filing Date: 2013-12-24
Classification: G09G

Abstract:
1. A display apparatus comprising: a timing controller which outputs image data, a data control signal and a first gate control signal; a data driving circuit which receives the image data in synchronization with the data control signal and converts the image data into data voltages to output one line of data voltages in each horizontal scanning period; a control signal converting circuit which delays the first gate control signal by a reference time period to convert the first gate control signal into a second gate control signal based on a reference signal; a gate driving circuit which sequentially outputs gate signals based on the second gate control signal; and a display panel including pixel rows and which displays an image corresponding to the one line of the data voltages based on the gate signals, wherein each gate signal of the gate signals rises at a point in time delayed from a starting point of a corresponding horizontal scanning period by the reference time period and falls before an ending point of the corresponding horizontal scanning period, wherein the first gate control signal comprises a first vertical clock signal and a first output enable signal, and the second control signal comprises a second vertical clock signal delayed from the first vertical clock signal by the reference time period and a second output enable signal delayed from the first output enable signal, wherein the second vertical clock signal determines a rising time point of the each gate signal and the second output signal determines a falling time point of the each gate signal.