Patent ID: 8987110
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device structure, the method comprising: forming one or more isolation recesses in a layer of semiconductor material to define an active region of semiconductor material that is flanked by the one or more isolation recesses, wherein forming the one or more isolation recesses comprises: filling each of the one or more isolation recesses with respective stress-inducing isolation material that imparts mechanical stress to the active region of semiconductor material; after filling the one or more isolation recesses with the stress-inducing isolation material, selectively etching away the oxide material, without etching the semiconductor material, to expose the semiconductor material; such that the stress-inducing isolation material protrudes above the semiconductor material; oxidizing exposed semiconductor material to form an oxide hardmask overlying the semiconductor material; selectively etching a section of the oxide hardmask, without etching the semiconductor material, resulting in an exposed section of the semiconductor material; and selectively growing epitaxial material overlying the exposed section of the semiconductor material.