Patent ID: 8039962
Filing Date: 2011-10-18
Classification: H01L

Abstract:
1. A semiconductor chip comprising: a wafer; a semiconductor device formed on the wafer; a first dielectric layer formed on the wafer and the semiconductor device; a first metal interconnection formed on the first dielectric layer; a second dielectric layer formed on the first dielectric layer and the first metal interconnection; a third dielectric layer formed on the second dielectric layer; a second metal interconnection formed in the third dielectric layer and having an exposed uppermost surface; a first nitride layer formed on the third dielectric layer and the second metal interconnection, the first protective layer having a first hole exposing a portion of the second metal interconnection; a via hole extending through the wafer, the first dielectric layer, the second dielectric layer, the third dielectric layer and the first nitride layer; a via formed in the via hole, the via having an exposed lower end and an exposed upper end; and a third metal interconnection formed on the exposed upper end of the via and the second metal interconnection exposed by the first hole and the second hole.