Patent ID: 8928089
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a semiconductor substrate, and an nMOSFET region and a pMOSFET region formed on the semiconductor substrate, wherein an nMOSFET structure and a pMOSFET structure are formed in the nMOSFET region and pMOSFET region, respectively, and wherein the nMOSFET structure comprises: a first channel region formed in the nMOSFET region, a first source/drain region located between the first channel region and the pMOSFET structure, and a first gate stack formed in the first channel region, wherein the nMOSFET structure is covered with a compressive-stressed material layer to apply a tensile stress to the first channel region; and the pMOSFET structure comprises: a second channel region formed in the pMOSFET region; and a second gate stack formed in the second channel region, wherein the pMOSFET structure is covered with a tensile-stressed material layer to apply a compressive stress to the second channel region, wherein the compressive-stressed material layer contacts the tensile-stressed material layer, the contact interface between the compressive-stressed material layer and the tensile-stressed material layer is farther away from the second gate stack than from the first gate stack, and the contact interface is formed in a region above the first source/drain region.