Patent ID: 6111557
Filing Date: 2000-08-29
Classification: G09G

Abstract:
An active matrix type display device for 2.sup..times. levels of gradation display, comprising an active matrix display portion and a peripheral circuit over a substrate, said peripheral circuit comprising:gate signal lines and source signal lines disposed so as to form a lattice structure over a substrate;at least one thin film transistor disposed around intersections of said gate signal lines and source signal lines; andmeans for selecting gradation voltage to be supplied to said source signal lines provided for each of said source signal lines, said means for selecting gradation voltage comprising a plurality of digital decoder lines, a plurality of first memory circuits, a plurality of second memory circuits, a plurality of D/A converter circuits, and a plurality of gradation voltage lines,wherein the number of said digital decoder lines is defined as .times. and the number of said gradation voltage lines is defined as 2.sup.(.times./2).