Patent ID: 7376810
Filing Date: 2008-05-20
Classification: G11C

Abstract:
1. An integrated device including: a non-volatile memory including a matrix of memory cells that are grouped into a plurality of locations of the memory, each of the locations being selected by providing a corresponding address to the memory, the memory having an addressing parallelism and a data parallelism; and a communication interface for interfacing the memory with an external bus, the external bus having a transfer parallelism lower than the addressing parallelism and the data parallelism, wherein the communication interface includes an address register coupled to the memory, and control means for executing at least one of a plurality of reading operations and a plurality of writing operations on the memory according to different modalities, in response to command codes received from the external bus, and the control means includes means for storing an address that is received from the external bus in chunks corresponding to the transfer parallelism in the address register, at least part of the address stored in the address register being provided to the memory so as to select the corresponding location of the memory.