Patent ID: 6673664
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A method of making a self-aligned ferroelectric memory transistor, comprising:preparing a substrate, including forming a p-well, depositing a first dielectric layer over the p-well, and forming a layer of n+ polysilicon over the first dielectric layer; forming shallow trenches for use in a shallow trench isolation process, wherein the shallow trenches extend through the polysilicon, the first dielectric layer, and about 500 nm of the substrate; depositing silicon oxide in the shallow trenches; removing the polysilicon except in active areas; depositing a bottom electrode on the polysilicon; forming a self-aligned gate stack including: depositing a layer of silicon nitride; patterning and selectively etching the silicon nitride, the bottom electrode and the polysilicon, wherein the patterned and etched bottom electrode has an outer margin; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region, wherein each of the source region and drain region has an edge underlying the outer margin of the bottom electrode and wherein neither of the source region nor the drain region underlies the bottom electrode outer margin; depositing a layer of silicon oxide, wherein the silicon oxide layer is between about 1.5 times to 2.0 times the thickness of the gate stack; planarizing the silicon oxide layer to the level of the silicon nitride; removing to silicon nitride; forming a sidewall barrier layer by depositing a layer of barrier metal in a thickness of between about 5 nm to 30 nm; depositing a layer of ferroelectric material on the bottom electrode in an area bounded by the bottom electrode outer margin; forming a top electrode structure on the ferroelectric material in an area bounded by to bottom electrode outer margin; and finishing the structure, including passivation, oxide depositing and metallization.