Patent ID: 6661735
Filing Date: 2003-12-09
Classification: G11C

Abstract:
A semiconductor memory device for processing internal command signals, addresses, and data input/output by using an internal clock signal inverted by an external clock signal, comprising:a first logic combination circuit receiving and combining the external clock signal and a test node signal which have different states depending on the modes of the external clock and test mode signal, the first logic combination circuit providing a non-inverted and an inverted external clock signal as a first signal and a second signal, respectively, in a test mode, and for outputting the second signal to have a predetermined level in a normal mode; a first clock generator for generating a first clock signal synchronized with the external clock signal at its rising edges by using the first signal; a second clock generator for generating a second clock signal synchronized with the external clock signal at its falling edges by using the second signal in the test mode, and for outputting a third signal having a predetermined level in the normal mode; and a second logic combination circuit for receiving output signals generated from the first clock generator and the second clock generator, and for generating internal clock signals corresponding to the test mode and the normal node.