Patent ID: 9023713
Filing Date: 2015-05-05
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising: providing an ultrathin body fully depleted silicon-on-insulator substrate; forming a PFET temporary gate structure and an NFET temporary gate structure on the substrate; implanting ions to form lightly doped active areas around the gate structures; performing a diffusionless annealing process on the active areas; forming a compressive strain region around the PFET gate structure by growing a boron-doped silicon germanium (SiGe) layer having a germanium content of about 20% to about 30% and a boron concentration of about 1e20 to about 5e20 ions/cm growing a boron-doped germanium-free silicon layer having a boron concentration of about 1e20 to about 5e20 ions/cm forming a tensile strain region around the NFET gate structure.