Patent ID: 6730573
Filing Date: 2004-05-04
Classification: H01L

Abstract:
A method for fabricating metal-insulator-metal capacitors, MIM, metal resistors, and copper back end of line interconnect wiring, comprising:providing a first intermetal dielectric layer overlying a semiconductor substrate; forming bottom MIM trench openings and other metal line openings in the first intermetal dielectric layer patterning using a first mask, photoresist process one; forming a first metal MIM electrode and other metal interconnect wiring lines filling said openings; forming shallow trench openings in a thin second intermetal dielectric layer, over existing first metal MIM electrode and interconnects, patterning using the first mask again, photoresist process two; forming a bottom plate barrier layer in the shallow trench openings and planarizing back the top surface, leaving the bottom plate barrier layer in the trench; forming a high dielectric constant insulator layer over the thin second intermetal dielectric layer and bottom plate barrier layer; forming a second metal MIM electrode, interconnects, and metal resistors over the high dielectric constant insulator layer, patterning using a second mask, photoresist process three, thus completing the MIM capacitors, metal resistors and copper wiring.