Patent ID: 9053066
Filing Date: 2015-06-09
Classification: G06F,G11C,Y02D

Abstract:
1. A configurable-interface NAND flash memory chip comprising: an array of NAND flash memory cells that contain stored data, the array of NAND flash memory cells formed on the NAND flash memory chip; an interface that includes a plurality of physical data Input/Outputs (I/Os), the interface formed on the NAND flash memory chip; and an interface configuration circuit formed on the NAND flash memory chip that selects a mode of operation for the interface in a one-time procedure that reflects permanent hard-wired connections to the plurality of physical I/Os from among at least: (a) a parallel interface mode in which the plurality of physical data I/Os each have permanent hard-wired connections and operate in parallel to transfer stored data, and (b) a serial interface mode in which one of the plurality of physical data I/Os has a permanent hard-wired connection and operates serially to transfer stored data, while other physical data I/Os of the plurality of physical data I/Os are idle and are physically unconnected.