Patent ID: 6614701
Filing Date: 2003-09-02
Classification: G11C

Abstract:
Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising:respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching means, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching means, activatable by the common word line, for coupling the second node to a respective second bit-line; and a respective individual gate arrangement having an output, and inputs connected to the respective first and second bit-lines, and being arranged to provide an output of a first type when the respective first and second bit lines are both within a low potential range, and otherwise provide an output of a second type; and the apparatus comprising a common gate arrangement having an output, and inputs connected to the outputs of the individual gate arrangements, the common gate arrangement being arranged to provide an output of a first type when the respective first and second bit lines are both within a low potential range, and otherwise provide an output of a second type.