Patent ID: 6165880
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method for making improved self-aligned contacts (SAC) to a semiconductor substrate comprising the steps of:providing said semiconductor substrate having device areas;forming a gate oxide on said device areas;depositing a first polysilicon layer on said device areas;depositing a first insulating layer on said first polysilicon layer;patterning by photoresist masking and anigotropic plasma etching said first insulating layer, and said first polysilicon layer, thereby forming gate electrodes having vertical sidewalls over said device areas;forming lightly doped source/drain areas in said device areas adjacent to said gate electrodes;depositing a conformal second insulating layer and blanket etching back to form first sidewall spacers on said gate electrodes;depositing a conformal third insulating layer as an etch-stop layer on said device areas;depositing and planarizing a first interpolysilicon oxide (IPO) layer;forming first self-aligned contact openings in said first IPO layer to said etch-stop layer, where said first self-aligned contact openings are etched over said device areas adjacent to and extending over said gate electrodes to form first said self-aligned contact openings, and concurrently etching first openings in said IPO layer to said etch stop layer over said gate electrodes for making gate electrode contact openings;anisotropically plasma etching said etch-stop layer in said first self-aligned contact openings to said device areas, and thereby forming second sidewall spacers from said etch-stop layer that protect said first sidewall spacers from erosion during buffer etching, and concurrently etching said etch-stop layer in said first contact openings over said gate electrodes;removing native oxide from said device areas in said first self-aligned contact openings using said buffer etching,depositing a conductively doped second polysilicon layer and a refractory metal silicide layer to form a polycide layer on said substrate;patterning said polycide layer leaving portions over said first self-aliged contact openings to form first of said self-aligned contacts in said first self-aligned contact openings;depositing a second interpolysilicon oxide (IPO) layer on said first IPO layer and over said polycide layer;depositing an interlevel dielectric (ILD) layer on said second IPO layer;forming second self-aligned contact openings in said ILD layer, said second IPO layer, and said first IPO layer to said etch-stop layer, where said second self-aligned contact openings are etched to said device areas adjacent to and extending over said gate electrodes to form said second self-aligned contact openings, and concurrently etching second contact openings over said first contact openings and etched in said first insulating layer to said gate electrodes;anisotropically plasma etching said etch-stop layer in said second self-aligned contact openings to said device areas thereby forming second sidewall spacers from said etch-stop layer to protect said first sidewall spacers during a buffer-etcb cleaning;removing native oxide from said devices areas in said second self-aligned contact openings using said buffer-etch cleaning;depositing and etching back a first metal layer to form metal plugs in said second self-aligned contact openings and in said second contact openings over said gate electrodes to form said self-aligned contacts from said first metal layer;depositing and patterning a second metal layer to form a first level of metal interconnections.