Patent ID: 6769007
Filing Date: 2004-07-27
Classification: G06F

Abstract:
An apparatus for facilitating an addition operation between two N-bit numbers, wherein the apparatus has a regular structure, comprising:a carry circuit for generating at least one carry signal for the addition operation, wherein the carry circuit includes a plurality of logic blocks organized into rows that form approximately logN successive stages of logic blocks, wherein each logic block generates the following signals: gâ€”hi:j=gâ€”hi:m+gâ€”h(mâˆ’1):j*kâ€”li:m, gâ€”li:j=kâ€”hi:m+gâ€”l(mâˆ’1):j*gâ€”li:m; kâ€”hi:j=kâ€”hi:m+kâ€”h(mâˆ’1):j*gâ€”li:m,and kâ€”li:j=gâ€”hi:m+kâ€”l(mâˆ’1):j*kâ€”li:m; wherein each logic block provide drive for at most a constant number of inputs in a successive stage of logic blocks, wherein the constant number of inputs is independent of N; wherein within a given stage of logic blocks, outputs from multiple logic blocks are ganged together to drive a signal line that feeds multiple inputs in a successive stage of logic blocks; and wherein there are at most a constant number of lateral tracks in a planar layout of signal lines between the successive stages of logic blocks, wherein the constant number of lateral tracks is independent of N.