Patent ID: 6044063
Filing Date: 2000-03-28
Classification: G06F

Abstract:
An arrangement for comparing a first, currently received n-bit unsigned integer (A) to a second, known n-bit unsigned integer (B), the arrangement also utilizing as an input a select signal (SGEB) indicating whether the comparison is to be ""equal to"" or ""greater than or equal to"", the arrangement comprisinga plurality of comparators, each comparator receiving as separate inputs an x-bit length segment from the received n-bit unsigned integer, an x-bit length segment from the known unsigned integer and the input select signal, the x-bit length segment from the known unsigned integer and the input select signal being combined to form a set of logic control signals that are multiplexed with the x-bit length segment of said received integer to generate a set of at least two output signals, a first output signal (GE) indicative of whether the x bits of said first signal are ""equal-to"" or ""greater-than-equal-to"" the x bits of said second signal, the indication of ""equal"" or ""greater-than-equal"" controlled by the value of said input select signal, and at least a second output signal chosen from the group consisting of: (a) a n ""equal"" signal (E) indicative of whether the x bits of said first signal are equal to the x bits of said second signal and (b) a ""not equal"" signal (NE) indicative of whether the x bits of said first signal are not equal to the x bits of said second signal;a plurality of logic modules responsive to the sets of outputs generated by the plurality of x-bit comparators, each logic module receiving as inputs the output signals from a pair of contiguous comparators, a first comparator of said pair of contiguous comparators defined as the ""least significant bits"" (LSB) comparator and providing as inputs to the associated logic module inputs designated GE.sub.L and E.sub.L and/or NE.sub.L, and a second, remaining comparator of said pair of contiguous comparators defined as the ""most significant bits"" (MSB) comparator and providing as inputs to the associated logic module inputs designated GE.sub.M and E.sub.M and/or NE.sub.M, said logic module generating a set of at least two outputs GE.sub.OUT and E.sub.OUT /NE.sub.OUT as follows:E.sub.OUT =NE.sub.M +NE.sub.LNE.sub.OUT =E.sub.M .multidot.E.sub.LGE.sub.OUT =GE.sub.M, if E.sub.M =1; =GE.sub.L, if E.sub.M =0.