Patent ID: 7472293
Filing Date: 2008-12-30
Classification: G06F

Abstract:
1. A system of managing power consumption of multiple processing elements in a network processor embedded in a semiconductor chip within an NP complex, wherein each of the processing elements has its own characteristic power and performance curve, wherein at least some of the processing elements are clocked, and wherein the performance recovery time that is associated with each of the clocked processing elements, and that specifies the time required to switch between a low power state and a higher power state, is factored into controlling the power state of the respective processing element, said system including a programmable power management state machine and a state control algorithm, and including the following components: a device for providing each of the processing elements with its own usage indication signal and a power control; a device for monitoring the utilization of the processing elements in the network processor using said usage indication signal and for outputting an access density signal to a storage location in a ring buffer; and a device for controlling the power state of each of the processing elements based upon its past usage, predicted future utilization, and performance recovery time, and determining when any of the processing elements is to be set to the higher power state or the lower power state based upon the prior utilization of the respective processing element.