Patent ID: 9141389
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs, the microprocessor comprising: a mode indicator, that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program; and a plurality of hardware registers, wherein when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state, wherein when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state; wherein the microprocessor is configured to execute a reset instruction to reset the microprocessor from a first one of the x86 ISA and the ARM ISA to a second one of the x86 ISA and the ARM ISA, and to respond to the reset instruction by fetching a first instruction of the second ISA from a programmable address defined in one or more of the plurality of hardware registers.