Patent ID: 7919336
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A fabrication method for a semiconductor device having a layered structure, the fabrication method comprising: a preparation step of preparing a support substrate; an interconnection pattern formation step of forming a basic interconnection pattern on said support substrate; a mounting step of mounting a semiconductor chip on said basic interconnection pattern; an inspection step of inspecting, after said mounting step, characteristics of said semiconductor chip via at least a part of said basic interconnection pattern and judging whether said semiconductor chip is defective; an insulation layer formation step of forming an insulation layer on said support substrate for covering said interconnection pattern and said semiconductor chip only when said inspection step determines that said semiconductor chip is non-defective; a conductive element formation step of forming a conductive element which penetrates through said insulation layer and reaches said basic interconnection pattern; an additional pattern formation step of forming an additional interconnection pattern, which is connected with said basic interconnection pattern via said conductive element, on said insulation layer; and a repeat step of repeating said mounting step, said inspection step, said insulation layer formation step, said conductive element formation step and said additional pattern formation step after said additional pattern formation step as long as said inspection step determines that said semiconductor chip is non-defective.