Patent ID: 6288952
Filing Date: 2001-09-11
Classification: G11C

Abstract:
A dynamic random access memory (DRAM) comprising:an array of memory cells;an access transistor connected to one of the memory cells and a digit line, such that the access device has a drain connected to the digit line, and a source connected to the one memory cell;a word line coupled to a gate connection of the access, transistor;an p-channel transistor having a source connection, a drain connection and a gate connection, wherein the source connection is coupled to the digit line, and wherein the drain is selectively coupled to either a write driver circuit or an I/O sense amplifier circuit; anda voltage boot circuit connected to the gate of the p-channel transistor, the voltage boot circuit being configured to produce an internal booted column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor below zero volts.