Patent ID: 7229884
Filing Date: 2007-06-12
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit field effect transistor comprising: forming a pre-active pattern on a surface of a substrate while refraining from doping the pre-active pattern with phosphorous, the pre-active pattern comprising a series of interchannel layers and channel layers stacked alternately upon each other; forming source/drain regions on the substrate, at opposite ends of the pre-active pattern; selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the pre-active pattern, thereby defining an active channel pattern comprising the tunnels and a plurality of channels comprising the channel layers; doping the channels with phosphorous after selectively removing the plurality of interchannel layers; and forming a gate electrode in the tunnels and surrounding the channels; wherein the channel layers comprise single crystalline silicon and wherein the interchannel layers comprise single crystalline silicon-germanium.