Patent ID: 6529030
Filing Date: 2003-03-04
Classification: G01R

Abstract:
An IC testing apparatus for testing a device, said IC testing apparatus comprising:a generating means for generating a pattern signal and a mode signal; a logic means, coupled to the generating means, for outputting either the pattern signal received from the generating means or a predetermined logical level signal, based on the mode signal received from the generating means; a wave-form shaping means, coupled to the logic means, for shaping a waveform of the pattern signal or the predetermined logical level signal received from said logic means; a correcting means, coupled to the wave-from shaping means, for correcting an output time of the pattern signal or the predetermined logical level signal, shaped by said wave-form shaping means; and an amplifying means, coupled to the correcting means, for amplifying an output signal from said correcting means and sending the amplified output signal to said device.