Patent ID: 7889558
Filing Date: 2011-02-15
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively; and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each cell of said plurality of memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, and at the time of programming, the number of said storage states being different in two of said memory cells, one of said two memory cells being arranged in the middle of a series of three memory cells of said plurality of memory cells connected in series to the same bit line, and the other memory cell of said two memory cells being adjacent to the middle memory cell.