Patent ID: 9147481
Filing Date: 2015-09-29
Classification: G11C

Abstract:
1. A semiconductor memory apparatus comprising: a memory cell array including a NAND string, the NAND string including a memory cell; a source connected to the NAND string, a source voltage being supplied to the source; a bit line connected to the NAND string; a sense amplifier including a first transistor, one end of a current path of the first transistor being connected to a first node, another end of the current path of the first transistor being connected to a second node, an internal voltage being supplied to the second node, the internal voltage being smaller than the source voltage; and a current source circuit configured to output a first voltage to a gate of the first transistor, the first voltage being smaller than the internal voltage; wherein when data held by the memory cell is read, the first transistor limits a first current from the source to the sense amplifier based on a threshold voltage of the memory cell to be read while a second voltage is supplied to the source.