Patent ID: 8013632
Filing Date: 2011-09-06
Classification: H03K

Abstract:
1. An integrated circuit comprising: a global hotsocket detector operable to generate a global hotsocket signal based on power supply signals; a power-on-reset circuit operable to generate a power-on-reset signal; a plurality of external pins; a plurality of logic gates, each of which is associated with a respective one of the external pins, wherein each of the logic gates has a first input operable to receive the global hotsocket signal over a global hotsocket signal path and has a second input operable to receive the power-on-reset signal over a global power-on-reset signal path; and a plurality of buffer transistors, wherein each of the buffer transistors is associated with a respective one of the external pins, has a gate terminal coupled to an output of the logic gate associated with that external pin, and has a source-drain terminal coupled to that external pin.