Patent ID: 6459320
Filing Date: 2002-10-01
Classification: G11C

Abstract:
An impedance matching circuit for a semiconductor memory device, comprising:an impedance detecting means for generating a voltage divided by a medium resistance value between a maximum resistance value and a minimum resistance value and an external resistance during a predetermined cycle as a first comparison voltage, and for generating a voltage divided by a resistance value varied in response to a counting output signal and the external resistance after the predetermined cycle as the first comparison voltage; a first comparing means for comparing the first comparison voltage with a reference voltage to generate a first comparing output signal; a second comparing means for comparing the first comparison voltage with the reference voltage to generate a second comparing output signal; a counting means for generating the counting output signal in response to the first comparing output signal; a cycle detector for detecting the predetermined cycle at a beginning state of impedance matching operation to generate an output signal during the predetermined cycle; and a plurality of output drivers for establishing an initial resistance value in each of the output drivers in response to the second comparing output signal and for adjusting a resistance value in each of the output drivers in response to the counting output signal.