Patent ID: 7952926
Filing Date: 2011-05-31
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory array, wherein said memory array comprises a plurality of sub-blocks, each sub-block comprises a plurality of word lines extending in a first direction, a plurality of local bit lines which extend in a second direction crossing the word lines, and a plurality of memory cells each storing information based on a level change of its threshold voltage and each placed so as to correspond to an intersection of one of the word lines and one of the local bit lines, said memory array further comprises a plurality of global bit lines which are provided so as to be shared in each sub-block, each global bit line includes a plurality of divided global bit lines which correspond to said plurality of sub-blocks respectively, each divided global bit line can be selectively connected to a divided global bit line which is adjacent in a direction in which it extends, and can be selectively connected to one local bit line within a corresponding sub-block, when connection means between all of the divided global bit lines are turned on, a first of two adjacent global bit lines is connected to one local bit line within a selected sub-block, the first global bit line is pre-charged to a first voltage prior to a read-out of data from a memory cell, and a second of the two adjacent global bit lines is pre-charged to a second voltage which is different from the first voltage at the time of read-out, and a read-out controlling circuit for reading out memory cell data by comparing a voltage of the first global bit line lines to the second voltage of the other after a certain period of time has passed after a start of the read-out of data from the memory cell, and after the voltage of the first global bit line is changed in accordance with the memory cell data is further provided.