Patent ID: 7968910
Filing Date: 2011-06-28
Classification: H01L

Abstract:
1. Semiconductor devices, comprising: (a) a first semiconductor region on an underlying semiconductor region of a substrate, the first semiconductor region having a lattice constant larger than that of silicon and being laterally adjacent to a second semiconductor region of the substrate, the second semiconductor region having a lattice constant smaller than that of silicon; (b) layers consisting essentially of silicon epitaxially grown onto exposed major surfaces of the first and second semiconductor regions; (c) a first gate overlying the first semiconductor region and a second gate overlying the second semiconductor region; (d) regions consisting essentially of single-crystal silicon epitaxially grown within recesses extending from the gates downwardly into the first and second semiconductor regions of the substrate, the recesses being laterally adjacent to the gates; and (e) source and drain regions extending at least partially in the silicon regions grown epitaxially within the recesses laterally adjacent to the first and second gates, wherein elements (a) through (e) form an n-type field effect transistor (“NFET”)having a tensil stressed channel in the silicon region overlying the first semiconductor region and a p-type field effect transistor (“PFET”) having a compressive stressed channel in the silicon region overlying the second semiconductor region.