Patent ID: 6121807
Filing Date: 2000-09-19
Classification: H03K

Abstract:
A circuit capable of operating in a first phase and a second phase, said circuit comprising:a first stage having a first input lead, a second input lead and an output lead, said first input lead of said first stage coupled to receive a first signal and said second input lead of said first stage coupled to receive a second signal, wherein:during said first phase, said first stage is operative to provide at said output lead of said first stage an output signal as a function of a logic level of said first signal received at said first input lead of said first stage, andduring said second phase, said first stage is operative to provide at said output lead of said first stage an output signal as a function of the logic level of said first signal received at said first input lead of said first stage;a second stage having a first input lead coupled to said output lead of said first stage, a second input lead coupled to said second input lead of said first stage, and an output lead, wherein:during said first phase, said second stage is operative to provide at said output lead of said second stage an output signal of a predetermined logic level in response to said circuit entering said first phase, said second stage providing said output signal of said second stage independently of said output signal provided by said first stage during said first phase, andduring said second phase, said second stage is operative to provide at said output lead of said second stage an output signal as a function of a logic level of said output signal of said first stage; andan unclocked buffer having an input lead coupled to said output lead of said second stage, wherein said buffer is operative to provide at an output lead an output signal as a function only of a logic level of said output signal from said second stage.