Patent ID: 9007291
Filing Date: 2015-04-14
Classification: G09G,H03K

Abstract:
1. An active level shift (ALS) driver comprising a plurality of ALS driving circuits, wherein each of the plurality of ALS driving circuits comprises: an input unit configured to apply a first polarity voltage to a first node, and to apply a second polarity voltage to a second node; a reset unit configured to apply an initial voltage to the first node and the second node, wherein the reset unit is configured to receive a reset signal; a level compensation unit configured to compensate a voltage drop of the first node and the second node; and an output unit configured to output a first power voltage or a second power voltage according to the initial voltage and then to alternately output the first power voltage and the second power voltage according to the first polarity voltage and the second polarity voltage, wherein the ALS driver comprises only N-channel transistors or only P-channel transistors, and wherein the input unit comprises: a first transistor comprising a gate electrode electrically connected to a first input terminal to which a first input signal is applied, and a first electrode electrically connected to a first polarity terminal to which the first polarity voltage is applied; a second transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to a second electrode of the first transistor, and a second electrode electrically connected to a third node; a third transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to the third node, and a second electrode electrically connected to the first node; a fourth transistor comprising a gate electrode electrically connected to the first input terminal, and a first electrode electrically connected to a second polarity terminal to which the second polarity voltage is applied; a fifth transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to a second electrode of the fourth transistor, and a second electrode electrically connected to a fourth node; and a sixth transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the second node, wherein the first polarity voltage and the second polarity voltage have opposite polarities.