Patent ID: 6128752
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A computer system having a mechanism for handling processing errors, comprising:first means for detecting an error occurring during processing of an instruction by said computer system;second means, coupled to said first means, for causing said computer system to retry at least one operation subsumed by said instruction, in response to detection of said error;third means, coupled to said second means, for determining whether said retry was successful; and,fourth means, coupled to said second means and said third means for, in response to an indication by said third means that said retry was not successful, varying an instruction processing cycle time of said computer system and for causing said second means to again retry said at least one operation subsequent to said varying, said fourth means including means for continuing operation of said computer system, responsive to said fourth means, and processing the instructions in a fault tolerant manner during the handling of the processing errors; andfifth means, coupled to said fourth means, for initiating a deferred service call over a communications link in response to said varying, said deferred service call indicating that digital computer system is operating in a degraded performance mode.