Patent ID: 7115938
Filing Date: 2006-10-03
Classification: G11C,H01L

Abstract:
1. A non-volatile memory cell, comprising: a switching device disposed on a substrate; a first plane capacitor having a first heavily doped region coupled to a word line; and a second plane capacitor having a second heavily doped region coupled to an erase pin, wherein the switching device, the first plane capacitor and the second capacitor share a common polysilicon floating gate retaining charge as a result of programming the memory cell; the memory cell is erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell; and the first and second heavily doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within in an operating voltage range.