Patent ID: 6080677
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method for forming an isolation structure on an integrated circuit comprising the following steps:(a) on a substrate, forming a layer of buffer oxide;(b) forming a layer of nitride on the layer of buffer oxide;(c) patterning the layer of nitride and the layer of buffer oxide to form a trench area;(d) cleaning the trench area prior to etching by subjecting the substrate including the trench area to a plasma comprising H.sub.2 O vapor and a gaseous fluorocarbon; and,(e) etching the substrate to form a trench within the trench area;wherein the cleaning in step (d) is performed separately from the etching in step (e) and wherein the cleaning in step (d) is completed before beginning to etch the substrate in step (e).