Patent ID: 6209042
Filing Date: 2001-03-27
Classification: G06F

Abstract:
An information processing system, comprising:a central processing unit (CPU) which controls peripheral devices by employing an I/O access method;a bus defining an interconnection between said CPU and peripheral devices across which handshaking occurs between a command transmitting device activating an initiator ready (IRDY) signal and a command receiving device activating a device select (DEVSEL) signal and a target ready (TRDY) signal,a first DMA controller, connected to said bus, to which a predetermined I/O address is assigned;a second DMA controller, connected to said bus, to which said predetermined I/O address is assigned;a first connection/disconnection switch selectively connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said first DMA controller;a second connection/disconnection switch selectively connecting and disconnecting a device select (DEVSEL) signal and a target ready (TRDY) signal that are output from said second DMA controller; andcontroller logic, connected to said bus, which receives said device select (DEVSEL) signals and said target ready (TRDY) signals that are output by said first and said second DMA controllers, and directs opening and closing of said first and said second connection/disconnection switches in accordance with I/O accesses that occur on said bus, wherein said controller logic disconnects said first and said second connection/disconnection switches during a bus cycle wherein said predetermined I/O address is accessed.