Patent ID: 6693447
Filing Date: 2004-02-17
Classification: G01R

Abstract:
An integrated circuit configuration for identifying contact faults during testing of the integrated circuit configuration, comprising:a semiconductor body; pads disposed on said semiconductor body; input buffers connected to said pads and defining a connection node between each respective pad and a respective input buffer; a housing protecting said semiconductor body; a multiplicity of pins protruding from said housing and connected to said pads; and a pull-up device connected to said connection node between said respective pad and said respective input buffer, said pull-up device holding said respective pad at a high potential by impressing a holding current if contact has not been made with a pin associated with said respective pad during testing resulting in avoiding activating a circuit section connected to said pin associated with said respective pad, said pull-up device having a P-channel MOS transistor with a gate and connected between said connection node and a high potential, said gate receiving a voltage for controlling said P-channel MOS transistor, said pull-up device having a further P-channel MOS transistor with a further gate and connected between said connection node and the high potential said further gate receiving a low potential.