Patent ID: 6504407
Filing Date: 2003-01-07
Classification: H03K

Abstract:
A programmable high speed frequency divider comprising:a counter including a plurality of flip-flops, each flip-flop having a clock terminal, an input terminal, an output terminal, a set terminal, and a reset terminal, and in which a clock signal to be divided is applied to the clock terminal of a first flip-flop of the plurality of flip-flops, representing a least significant bit, wherein the output terminal of the first flip-flop representing the least significant bit is connected to the clock terminal of a second flip-flop of the plurality of flip-flops, representing the next least significant bit; remaining flip-flops are similarly connected through a most significant bit flip-flop; the set terminal and reset terminal of the first flip-flop are open and a logical operation result of control signals and output signals of the flip-flops is applied to the input terminal of the first flip-flop; and the plurality of flip-flops, except the first flip-flop, are initialized by set signals or reset signals corresponding to a dividing ratio; and a control circuit which receives outputs of the plurality of flip-flops, generates control signals corresponding to counting values of the counter with a logic gate circuit, and generates set signals and reset signals for initializing flip-flops of the counter and having frequencies corresponding to the dividing ratio.