Patent ID: 8015537
Filing Date: 2011-09-06
Classification: G06F

Abstract:
1. A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit, the method comprising: comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design; determining which clock domains have data rates that match frequencies of clock sources; for each clock domain that has a data rate matching a frequency of a clock source, clocking loads of the clock domain using a multiple synchronous clock technique with the matching clock source; for each clock domain having a data rate that does not match a frequency of a clock source, clocking loads of the clock domain using a clock enable technique; and outputting the circuit design specifying clock circuitry for each clock domain; wherein clocking loads of the clock domain using a multiple synchronous clock technique comprises, for each clock domain having a data rate that matches a clock source: wherein the comparing, the determining, the clocking loads of the clock domain using a multiple synchronous clock technique, the clocking loads of the clock domain using a clock enable technique, and the outputting are performed by the computer.