Patent ID: 9003159
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. An apparatus, comprising: a flash memory structure; circuitry to receive a command sequence that includes a logical address, wherein the logical address includes (i) information that identifies a data storage device from among two or more separate data storage devices and (ii) a logical page number within the identified data storage device; circuitry to receive data associated with the logical address; circuitry to allocate a physical page in the flash memory structure; circuitry to store a mapping from the logical address to a physical address associated with the physical page; circuitry to write, based on the physical address, the data associated with the logical address to the flash memory structure to cache the data associated with the logical address; and circuitry to (i) invalidate the physical page in the flash memory structure based on the logical address being included in an invalidate command sent by an application to indicate caching of the data associated with the logical address is no longer needed and (ii) allow a garbage collector to directly use the physical page when performing an erasure to make the physical page available for re-allocation; wherein the mapping indicates a cached status of the data associated with the logical address; and wherein the mapping goes from the logical address to the physical address without an intervening reference to a logical page number (LPN) of the flash memory structure.