Patent ID: 7551491
Filing Date: 2009-06-23
Classification: G11C,H01L

Abstract:
1. A unit cell of a non-volatile memory device, comprising: a first memory transistor including a first storage node; a second memory transistor including a second storage node; and a single transistor connected between the first memory transistor and the second memory transistor; first and second bit lines intersecting a string, the string including the first and second memory transistors positioned between the intersections of the first and second bit lines, with the first and second memory transistors including first and second control gates, respectively; a first pass transistor included in the string between the first bit line and the first memory transistor and including a first pass gate; a second pass transistor included in the string between the second memory transistor and the second bit line and including a second pass gate; a third pass transistor included in the string between the first and second memory transistors and including a third pass gate, where the third pass transistor is the single transistor; a third bit line connected to a channel of the third pass transistor; and a word line connected to the control gate of each of the first and second memory transistors in common, wherein the first memory transistor and the second memory transistor are connected to each other in series and further connected in common to the word line, and the first and second storage nodes are configured to execute concurrent memory operations.