Patent ID: 7039782
Filing Date: 2006-05-02
Classification: G06F,Y02D

Abstract:
1. A memory system comprising: at least one channel; a plurality of memory devices coupled to at least the one channel; and a memory controller coupled to at least the one channel, wherein the memory controller provides a command to a first group of memory devices in the plurality of memory devices via at least the one channel, and the first group of memory devices, as a multiplexed group, communicate a first data block to the memory controller via at least the one channel during a first time period in accordance with the command; and wherein during the first time period each memory device in the first group of memory devices has a second transfer rate that is less than a first transfer rate for transferring the first data block during the first time period; and wherein each one of the memory devices in the first group of memory devices is configured to communicate in response to the command a respective second data block, which has a size less than the first data block size, during the first time period.