Patent ID: 7525157
Filing Date: 2009-04-28
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor base material; an insulating layer selectively formed on the semiconductor base material; a first semiconductor layer made of single-crystal and formed on the semiconductor base material that is exposed below the insulating layer, the first semiconductor layer having an opening that exposes the semiconductor base material; a second semiconductor layer made of a single-crystal whose wet-etching selectivity is smaller than a wet-etching selectivity of the first semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having the opening that exposes the semiconductor base material; a polycrystalline layer made of the same composition as the second semiconductor layer, the polycrystalline layer being formed on the insulating layer; a support film formed on a whole upper face of the semiconductor base material and filling the opening; a mask pattern formed on the support film so as to continuously cover at least a part of the opening and a silicon-on-insulator (SOI) forming region, cover the polycrystalline layer and expose other region; an opening plane exposing a side face of the first semiconductor layer and provided below the support film, the opening plane being formed by sequentially dry-etching the support film, the second semiconductor layer and the first semiconductor layer by using the mask pattern as a mask; a portion defining a hollow part between the second semiconductor layer and the semiconductor base material, the hollow part being formed by wet-etching the first semiconductor layer through the opening plane; a first insulating film formed in the hollow part; and a second insulating film formed above the semiconductor base material on which the first insulating film is formed, the second insulating film being treated with chemical mechanical polishing (CMP) so as to expose the polycrystalline layer, wherein the SOI forming region is provided in a plural number, and the insulating layer has a planar shape that encloses the SOI forming regions and separates one of the SOI forming regions from other SOI forming region in the enclosed area.