Patent ID: 8928407
Filing Date: 2015-01-06
Classification: H03F,H03G

Abstract:
1. A circuit comprising: a first transistor comprising a first gate coupled to a first node, a first source coupled to a second node, a first drain coupled to a third node, and a first bulk coupled to a fourth node; a first terminal of a first resistor coupled to the third node, wherein a second terminal of the first resistor is coupled to a fifth node; a second transistor comprising a second gate, a second source, a second drain, and a second bulk, wherein the second drain of the second transistor is coupled to the second node, wherein the second gate of the second transistor is coupled to a sixth node, wherein the second source of the second transistor is coupled to a seventh node, and wherein the second bulk of the second transistor is coupled to an eighth node; a third transistor comprising a third gate, a third source, a third drain, and a third bulk, wherein the third gate of the third transistor is coupled to the first node, wherein the third source is coupled to a ninth node, wherein the third drain of the third transistor is coupled to a tenth node, and wherein the third bulk of the third transistor is coupled to an eleventh node; a third terminal of a second resistor coupled to the tenth node, wherein a fourth terminal of the second resistor is coupled to the fifth node; and a fourth transistor comprising a fourth gate, a fourth source, a fourth drain, and a fourth bulk, wherein the fourth drain of the fourth transistor is coupled to the ninth node, wherein the fourth gate of the fourth transistor is coupled to the sixth node, wherein the fourth bulk of the fourth transistor is coupled to the seventh node, and wherein the fourth source of the fourth transistor is coupled to the eighth node.