Patent ID: 9207277
Filing Date: 2015-12-08
Classification: G01D,G01R,G06M,G06Q,G07C,Y02P

Abstract:
1. A wafer acceptance test (WAT) system for generating a yield forecast based on an WAT of a wafer integrated circuit (IC) batch, comprising: a saturation current WAT subsystem operable to generate a weighted standard deviation based on target NMOS and PMOS saturation currents and saturation current WAT results; a wafer IC speed WAT subsystem operable to generate a speed performance probability distribution of wafer ICs based on said weighted standard deviation and speed WAT results; a wafer IC power WAT subsystem operable to employ said speed WAT results and power WAT results to generate a power performance model of wafer ICs; and a yield calculator operable to generate a power performance variance probability distribution of wafer ICs based on said power performance model and said power WAT results, and to employ said speed performance probability distribution and said power performance variance probability distribution to generate said yield forecast with respect to a target performance profile.