Patent ID: 6098145
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A memory system having memory system output ports comprising:an array of column and rows of memory cells for storing digital data, said array being arranged into groups of M adjacent columns of cells, each column having an associated bitline and complementary bitline;a plurality of column decoders, each being associated with one group of M adjacent columns, wherein in response to an input address signal said one group of M adjacent columns is accessed with a select signal by its associated column decoder when said select signal is in a first logic state during an access cycle, and wherein the remainder of said groups of M adjacent columns in said array are not selected;a plurality of sense amplifiers for sensing said stored digital data from said one group of M adjacent columns when said select signal is in said first logic state, said stored digital data having an associated logic state;a plurality of charging means each coupled to and for charging said associated bitline and complementary bitline of said each column in said one group of M adjacent columns in response to said select signal being in a second logic state during said access cycle such that only said associated bitline and bitline complement of said each column in said one group of M adjacent columns are charged during said access operation; andmeans for outputting said sensed data from said output ports.