Patent ID: 8219757
Filing Date: 2012-07-10
Classification: G06F

Abstract:
1. A processor-based system, comprising: a processor: a system memory coupled to the processor; a mass storage device; a cache memory located between the system memory and the mass storage device wherein the cache memory includes at least a first cache portion having a first selected size of the cache memory, wherein the cache memory is logically divided into at least the first cache portion and a second cache portion; a computer readable storage medium having instructions, which, if executed by a processor, cause the processor-based system to store in the first cache portion cache entries having cache hits greater than or equal to one and less than or equal to a first selected number unless instructed otherwise; computer readable storage medium having instructions, which, if executed by a processor, cause the processor-based system to store in the second cache portion cache entries having cache hits greater than the first selected number—unless instructed otherwise; and computer readable storage medium having instructions, which, if executed by a processor, cause the processor-based system to store in the first cache portion a new cache entry unless instructed otherwise.