Patent ID: 7167017
Filing Date: 2007-01-23
Classification: H03K

Abstract:
1. An integrated circuit comprising: a first module and a second module, said first module is operable in a power-down mode or a power-up mode while said second module is operable in said power-up mode; and an isolation cell provided between said first module and said second module, said isolation cell connecting an output of said first module as an input to said second module if said first module is in said power-up mode, and maintaining the input of the said second module at a desired logic value if said first module is in said power-down mode, wherein said isolation cell is designed to operate using power provided from either said first module or said second module without a floating node of any of the transistors contained in said isolation cell, wherein a transistor forms said floating node if one terminal of the transistor is powered while another terminal of the transistor is open in said power-down mode of said first module.