Patent ID: 6034539
Filing Date: 2000-03-07
Classification: H01L,H03K

Abstract:
A bonding-option architecture for use on an IC package having a plurality of pins and containing an IC chip having an internal circuit and a plurality of bonding points, each of said bonding points being selectively wired to a selected one of said pins, said bonding-option architecture comprising:an option pad; anda plurality of bonding entries connected to said option pad, each of said bonding entries being arranged in immediate proximity to one of said bonding points;whereinat least a first one of said bonding points is connected via a first one of said pins to an external power point and at least a second one of said bonding points is connected via a second one of said pins to an external ground point when said IC package is mounted for use; andwhereinin the case when a high-voltage state logic signal is to be set via said option pad into the internal circuit of said IC chip, said first one of said bonding points is wired to the proximate one of said bonding entries; andin the case when a low-voltage state logic signal is to be set via said option pad into the internal circuit of said IC chip, said second one of said bonding points is wired to the proximate one of said bonding entries.