Patent ID: 6628250
Filing Date: 2003-09-30
Classification: G09G

Abstract:
A method for driving a plasma display panel having a front substrate and a rear substrate facing and spaced apart from each other, and n common electrode lines 1, 2, . . . n, n scan electrode lines, and m address electrode lines arranged between the front and rear substrates (where m and n are integers greater than 1), the common electrode lines and the scan electrode lines being parallel to each other, the address electrode lines being orthogonal to the scan electrode lines, to define pixels at respective intersections of the scan electrode lines and the address electrode lines, the method comprising:grouping the n common electrode lines into k groups of common electrode lines (where k is an integer greater than 1), the common electrode lines in a p-th group of the k groups of the common electrode lines being the (p+kÂ·j) common electrode lines (where p is an integer, at least 1 and up to k, and j is 0, 1 . . . ((n/k)âˆ’1)); dividing a unit frame to be displayed into k subfields; and in a reset period of the p-th subfield, applying an erase discharge voltage to the common electrode lines of the p-th group of common electrode lines only in the p-th subfield of the respective subfields to erase wall charges and establish uniform space charge in all pixels along the common electrode lines of the p-th group of common electrode lines, while applying a sustained discharge voltage, having the same polarity as and lower in magnitude than the erase discharge voltage, to the common electrode lines not in the p-th group of common electrode lines.