Patent ID: 8174277
Filing Date: 2012-05-08
Classification: G01R

Abstract:
1. A method comprising: providing, in an integrated circuit, an internal power bus comprising a Vdd component and a Vss component; providing, in the integrated circuit, internal circuitry; connecting the internal circuitry to the Vdd component; connecting the internal circuitry to the Vss component; connecting one of at least two power connection terminals of the integrated circuit to the Vdd component; connecting another of the at least two power connection terminals to the Vss component; connecting one of another at least two power connection terminals of the integrated circuit to the Vss component; connecting another of the another at least two power connection terminals to the Vdd component; connecting the at least two power connection terminals and the another at least two power connection terminals to a tester; buffering signals that are transmitted between the another at least two power connection terminals and the tester; and monitoring a voltage level at the another at least two power connection terminals, and based on monitoring the voltage level, controlling a power supplied to the at least two power connection terminals.