Patent ID: 6717832
Filing Date: 2004-04-06
Classification: G11C

Abstract:
A method for communicating between a controller module and memory modules, including a first memory module and a second memory module, through a common bus system, which comprises the steps of:outputting from the controller module a command signal and dedicated chip select signals including a first chip select signal and a second chip select signal fed to the memory modules for selecting a respective memory module, the first and second chip select signals being selectively outputted from the controller module independent from the command signal, the first memory module receiving both the first chip select signal and the second chip select signal and the second memory module receiving only the second chip select signal; and activating a bus signal line termination for terminating data to be transmitted from the controller module to both of the memory modules only in the first memory module as soon as the first memory module functioning as a monitoring memory module registers one of the chip select signals.