Patent ID: 6395622
Filing Date: 2002-05-28
Classification: G01R,G11C,H01L

Abstract:
A manufacturing process for semiconductor devices comprising the steps of:(a) providing a silicon substrate having integrated circuits, bonding pads, redundancy circuits and fuses on one surface of the silicon substrate, wherein the fuses are electrically connected with corresponding redundancy circuits; (b) forming conductive redistribution circuits on the surface of the silicon substrate, each conductive redistribution circuit electrically connecting with the corresponding bonding pad and each conductive redistribution circuit forming a redistribution pad and a testing pad; (c) applying in liquid phase, a passivation layer covering the silicon substrate; (d) opening the redistribution pads and the test pads of the conduction redistribution circuits through the passivation layer; (e) forming a plurality of bumps on the redistribution pads for flip-chip mounting; (f) electrically testing the silicon substrate by applying a test probe to the test pads to determine if there are repairable bad chips; and (g) laser repairing the repairable bad chips.