Patent ID: 8415219
Filing Date: 2013-04-09
Classification: H01L

Abstract:
1. A method of manufacturing a DMOS transistor, comprising: providing a substrate; forming in the substrate a drift region and forming, in a trench having a bottom level in the drift region, a gate electrode bounded by a gate insulation layer in the trench, the gate electrode having a first flat top level which adjoins the gate insulation layer; back-etching the substrate with the drift region after having formed said gate electrode and said gate insulation layer to a level below the first flat top level of said gate electrode; forming a body region in the substrate, the body region being provided on the drift region; forming a source region on the body region based on a process of deposition, wherein a second top level of the body region and a third top level of the source region are below the first flat top level of said gate electrode, and wherein the gate insulation layer electrically insulates the gate electrode from the drift region, the body region, and the source region; and disposing a metallization region on the source region and the gate insulation layer, wherein the source region covers the whole surface of the body region opposite to the drift region and prevents a direct electrical contact between the metallization region and the body region.