Patent ID: 6870217
Filing Date: 2005-03-22
Classification: H01L,H03K

Abstract:
1. A circuit for driving a dual-gated MOSFET, said dual-gated MOSFET being switchable between conduction and blocking modes, said dual-gated MOSFET having a shielding gate, a switching gate, a gate-to-drain overlap region, and a drain-to-source resistance when the MOSFET is in the conduction mode, said circuit comprising: means for generating a first voltage signal for driving said shielding gate, said first voltage signal having a first voltage level for charging the gate-to-drain overlap region and a fourth voltage level for reducing the drain-to-source resistance when the MOSFET is in the conduction mode; means for generating a second voltage signal for driving the switching gate, said second voltage signal being switchable between a low and a high voltage level; and control means for controlling each of said means for generating to thereby switch the MOSFET between the conduction and blocking modes.