Patent ID: 7251193
Filing Date: 2007-07-31
Classification: G11C

Abstract:
1. A method comprising: (a) receiving a clock signal, a first address value and a second address value into a pseudo-dual port memory device; (b) using a first transition of the clock signal to latch the first address value and the second address value into the pseudo-dual port memory device; (c) generating first control signals for performing a first memory access operation of the pseudo-dual port memory device and performing the first memory access operation such that first memory cells addressed by the first address value are accessed; and (d) generating second control signals for performing a second memory access operation of the pseudo-dual port memory device and performing the second memory access operation such that second memory cells addressed by the second address value are accessed, wherein both the first memory access operation and the second memory access operation are performed in a single period of the clock signal, and wherein no second transition of the clock signal is used to initiate the second memory access operation.