Patent ID: 8993354
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device in a semiconductor wafer, the semiconductor device comprising a resistor pattern including a plurality of resistors provided in the semiconductor wafer and arranged in matrix of at least two rows and at least two columns, and a connection structure configured to connect the plurality of resistors in series, wherein the plurality of resistors includes a plurality of first resistors provided in a chip of the semiconductor wafer and a plurality of second resistors provided in a dicing area of the semiconductor wafer, the method comprising: heating the resistor pattern by scanning the plurality of resistors with a first beam under a first beam scanning condition, acquiring resistance values of the plurality of second resistors; and determining whether variation of the resistance values of the plurality of first resistors is within an allowable range, based on the acquired resistance values of the plurality of second resistors.