Patent ID: 7631212
Filing Date: 2009-12-08
Classification: H04L

Abstract:
1. A communication system comprising: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves, wherein the master supplies electricity to the bus in a power supply period, the master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period, the power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves, the master includes a frequency dispersion element and a plurality of transistors, the frequency dispersion element in the master finely changes a communication frequency in the data communication, the plurality of transistors are coupled in parallel to each other, and the plurality of transistors in the master changes a drive level of the bus within a predetermined acceptable range in the data communication, wherein the frequency dispersion element includes a state transition sequencer, an adder-subtractor, a register, a counter and a clock circuit, wherein the clock circuit supplies a clock signal to the counter, wherein the sequencer outputs a control signal to switch between adding function and subtracting function of the adder-subtractor, wherein the adder-subtractor adds or subtracts a data corresponding to dispersion of frequency and an output data from the register, and outputs an added or subtracted data to the register, and wherein the register outputs the output data to the counter so that the frequency dispersion element finely changes the communication frequency.