Patent ID: 8048797
Filing Date: 2011-11-01
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit at a high numerical aperture, the method comprising: forming a gate conductor layer above a substrate; forming a first anti-reflective coating layer above the gate conductor layer; forming a second anti-reflective coating layer above the first anti-reflective coating layer; forming a photoresist layer above the second anti-reflective coating layer; patterning the photoresist layer, wherein a first thickness of the first anti-reflective coating layer and a second thickness of the second anti-reflective coating layer are configured to reduce reflections associated with the patterning step to below 1.0 percent; removing the first anti-reflective coating layer and the second anti-reflective coating layer in accordance with a feature defined by the photoresist layer; forming a spacer layer after removing the first and second anti-reflective coating layers; and etching the spacer layer before etching the gate conductor layer.