Patent ID: 6632723
Filing Date: 2003-10-14
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; drain and source regions of a MOS transistor formed in a surface of the semiconductor substrate; a gate electrode formed on a surface of a channel region of the MOS transistor between said drain and source regions of said semiconductor substrate with a gate insulating film between the gate electrode and the channel region; trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of said semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of said element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of said MOS transistor or to voltage-control the semiconductor substrate region.