Patent ID: 6037201
Filing Date: 2000-03-14
Classification: H01L,Y10S

Abstract:
A method for manufacturing mixed-mode devices comprising the steps of:providing a substrate having a plurality of shallow trench isolation structures formed thereon;forming a first gate oxide layer over the substrate and the shallow trench isolation structures;forming a photoresist layer over the first gate oxide layer, then using a photolithographic process to pattern the photoresist layer into a plurality of patches covering thick gate oxide layer regions;etching away a portion of the first gate oxide layer using a wet etching solution;immersing the substrate, the first gate oxide layer and the shallow trench isolation structures in water to rinse away the wet etching solution;removing the photoresist layer using an acid solution, wherein the steps of etching the first gate oxide layer, immersing the substrate, and removing the photoresist layer are all performed in same wet chemical processing environment;forming a second gate oxide layer over the first gate oxide layer and the substrate, creating a plurality of thin gate oxide layer regions covered only by the second gate oxide layer and a plurality of thick gate oxide layer regions covered by the first gate oxide layer and the second gate oxide layer together; andforming a plurality of transistor structures above the thin gate oxide layer region and the thick gate oxide region.