Patent ID: 6057191
Filing Date: 2000-05-02
Classification: H01L

Abstract:
A process for manufacturing an integrated circuit, providing for forming contacts between a conductive material layer and first doped regions of a semiconductor substrate having edges aligned to edges of an opening in an insulating material layer, said edges of the opening in the insulating material layer defining active areas of the integrated circuit wherein said first doped regions are formed, and second doped regions of the same conductivity type as said first doped regions disposed under said first doped regions, said second doped regions extending partially under said edges of the opening in the insulating material layer to prevent short-circuits between the conductive material layer and the semiconductor substrate, wherein said second doped regions are formed by implanting dopants along a direction at a first angle with respect to an orthogonal direction to a surface of the semiconductor substrate and with an energy sufficient to make the dopants penetrate in the semiconductor material deeper than said first doped regions and under said edges of the insulating material layer.