Patent ID: 6943115
Filing Date: 2005-09-13
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with conductor pattern which includes at least one set of conducting portions electrically connected to each other, said at least one set of conducting portions having a surface area of no less than 500 μm 2 , the method comprising: a polishing step for flattening the conducting portions together with the insulating film by chemical mechanical polishing; a chemical cleaning step for cleaning a flattened surface of the insulating film with a cleaning liquid; and a rinsing step for removing the cleaning liquid using a rinsing liquid, wherein the rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid, and wherein the polishing step includes a first polishing treatment using a chemical slurry and a polishing tool, the polishing step further including a second polishing treatment using said polishing tool and water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight.