Patent ID: 6816430
Filing Date: 2004-11-09
Classification: G11C

Abstract:
A data storage device comprising:a plurality of registers that can be addressed by address words; p output ports; and connecting means for connecting the plurality of registers to the p output ports in response to address words of p registers selected to read contents of the registers on the p ports respectively; wherein all address words contain a specific bit and remaining bits, the registers are connected in pairs on each output port, each pair of registers including two registers with address words that only differ in a value of the specific bit, and for each pair of registers and for each output port, the connecting means comprise a pair of first switching means controlled in a complementary manner by the specific bit in the address word of one of the two registers, and a second switching means connected to the corresponding output port and controlled from the remaining bits of the address words of the two registers, the pair of first switching means being connected between the corresponding two registers and between the corresponding second switching means.