Patent ID: 9064719
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. An integrated circuit comprising a capacitor and a non-inductive resistor, comprising: a substrate having a capacitor area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure disposed on the capacitor area and the resistor area, comprising a bottom conductive layer, an insulating layer and a top conductive layer from bottom to top and sandwiched by a first dielectric layer and a second dielectric layer; a first metal plug and a second metal plug disposed on the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the capacitor area respectively, thereby the patterned stacked structure in the capacitor area constituting the capacitor; and a third metal plug and a fourth metal plug disposed on the second dielectric layer and contacting the bottom conductive layer and the top conductive layer of the resistor area respectively, and a fifth metal plug disposed on the second dielectric layer and contacting the bottom conductive layer and the top conductive layer of the resistor area simultaneously, thereby the patterned stacked structure in the resistor area constituting the non-inductive resistor.