Patent ID: 7565516
Filing Date: 2009-07-21
Classification: G06F,Y02D,Y10S

Abstract:
1. Apparatus for processing data, said apparatus comprising: a first device; an N-bit data bus coupled to said first device and configured to transmit N-bit bus transactions; a second device; an M-bit data bus coupled to said second device and configured to transmit M-bit bus transactions, where M is less than N; bus resizing logic coupled to said N-bit data bus and to said M-bit data bus and configured to convert between an N-bit bus transaction upon said N-bit data bus and a plurality of M-bit bus transactions upon said M-bit data bus; and transmission reordering logic configured to reorder data within a sequence of N-bit data words being transmitted between said first device and said second device via said N-bit data bus, said bus resizing logic and said M-bit data bus, such that correlated portions of different N-bit data words are transferred using a common portion of temporally adjacent M-bit data words being transmitted via said M-bit data bus thereby reducing an average Hamming distance between successive M-bit data words transmitted via said M-bit data bus, wherein said correlated portions are portions of said different N-bit data words including a plurality of adjacent bits with the same position within a range extending from a least significant bit to a most significant bit of respective ones of said different N-bit data words.