Patent ID: 6423584
Filing Date: 2002-07-23
Classification: G11C,H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device comprising the steps of;(a) forming an isolation area and an active area in a semiconductor substrate; (b) forming a first insulating film over said semiconductor substrate; (c) forming a conductive film for constituting a first gate electrode over said first insulating film; (d) forming a second insulating film over said first conductive film; (e) opening a hole reaching to said conductive film for constituting said first gate electrode within said second insulating film at a location over a gate electrode formation region of first and second field-effect transistors for the use as peripheral circuits; (f) forming a conductive film for constituting a second gate electrode over said second insulating film; (g) forming a double-level gate electrode of a nonvolatile memory cell by patterning said conductive film for constituting said first gate electrode, said second insulating film and said conductive film for constituting said second gate electrode; (h) forming a pair of semiconductor regions for said nonvolatile memory cell in said semiconductor substrate; (i) forming gate electrodes of said first and second field-effect transistors for the use as peripheral circuits by patterning said conductive film for constituting said first gate electrode, said second insulating film and said conductive film for constituting said second gate electrode; (j) forming a pair of semiconductor regions for said first field-effect transistor for the use as a peripheral circuit in said semiconductor substrate; and (k) forming a pair of semiconductor regions for said second field-effect transistor for the use as a peripheral circuit in said semiconductor substrate; wherein said hole is provided at a location which two-dimensionally overlaps said active area within the plane of said gate electrode formation region when viewed from a plane view of the semiconductor integrated circuit device in the case of said first field-effect transistor, and said hole is provided at a location which two-dimensionally overlaps said isolation area within the plane of said gate electrode formation region when viewed from said plane view in the case of said second field-effect transistor, wherein the gate length of said first field-effect transistor is longer than the gate length of said second field-effect transistor.