Patent ID: 7684279
Filing Date: 2010-03-23
Classification: G11C

Abstract:
1. A semiconductor memory device having a hierarchical input/output line structure, comprising: a first core block among a plurality of core blocks including a first plurality of memory banks sharing a first input/output sense amplifier; a second core block among the plurality of core blocks including a second plurality of memory banks sharing a second input/output sense amplifier; a third core block among the plurality of core blocks including a third plurality of memory banks sharing a third input/output sense amplifier; a fourth core block among the plurality of core blocks including a fourth plurality of memory banks sharing a fourth input/output sense amplifier; first through fourth data input/output lines transmitting data from the first through fourth input/output sense amplifiers, respectively, where the first through fourth data input/output lines are arranged on the corresponding first through fourth core blocks; a first control circuit configured to generate a first plurality of activation signals to activate the first input/output sense amplifier, and a second plurality of activation signals to activate the second input/output sense amplifier, where the first control circuit is located in a region of a first peripheral circuit between the first and second core blocks; a second control circuit configured to generate a third plurality of activation signals to activate the third input/output sense amplifier, and a fourth plurality of activation signals to activate the fourth input/output sense amplifier, where the second control circuit is located in a region of the first peripheral circuit between the third and fourth core blocks; a first output transfer circuit configured to output data received from a first memory bank and a second memory bank and amplified by the first input/output sense amplifier, in response to a first plurality of control signals generated by the first control circuit; a second output transfer circuit configured to output data received from a third memory bank and a fourth memory bank and amplified by the second input/output sense amplifier, in response to a second plurality of control signals generated by the first control circuit; a third output transfer circuit configured to output data received from a fifth memory bank and a sixth memory bank and amplified by the third input/output sense amplifier, in response to a third plurality of control signals generated by the second control circuit; a fourth output transfer circuit configured to output data received from a seventh memory bank and an eighth memory bank and amplified by the fourth input/output sense amplifier, in response to a fourth plurality of control signals generated by the second control circuit; a first ordering circuit configured to change the order of data output from the first and third output transfer circuits; and a second ordering circuit configured to change the order of data output from the second and fourth output transfer circuits, wherein the first and third output transfer circuits and the first ordering circuit are located in a second peripheral circuit region between the first and third core blocks, and the second and fourth output transfer circuits and the second ordering circuit are located in the second peripheral circuit region between the second and fourth core blocks.