Patent ID: 7995659
Filing Date: 2011-08-09
Classification: H04N

Abstract:
1. A prediction module adapted to calculate pixel values of a macroblock to be predicted according to data decoded by an entropy decoder and pixels of a reference block outputted by a frame buffer, said prediction module comprising: a first processing unit which outputs a first output signal; a second processing unit which is connected electrically to said first processing unit and which outputs a second output signal; a third processing unit which is connected electrically to said second processing unit and which outputs a third output signal; a fourth processing unit which is connected electrically to said third processing unit and which outputs a fourth output signal; a fifth processing unit which is connected electrically to said fourth processing unit and which outputs a fifth output signal; a sixth processing unit which is connected electrically to said fifth processing unit and which outputs a sixth output signal; and a computation control unit which is connected electrically to said first to sixth processing units, the frame register, and the entropy decoder, which receives the pixels of the reference block and the data outputted by the entropy decoder, which arranges the pixels of the reference block appropriately according to the data outputted by the entropy decoder into a first pixel signal and a second pixel signal for sequential output in units of cycles, which receives the first, second and fourth output signals outputted respectively by said first, second and fourth processing units, and which computes the first, second and fourth output signals so as to obtain the pixel values of the macroblock to be predicted; said sixth processing unit receiving the first and second pixel signals, and being controlled by said computation control unit to use one of the first and second pixel signals as the value of the sixth output signal to be outputted thereby in a next cycle, said fifth processing unit receiving the first and second pixel signals and the sixth output signal, and being controlled by said computation control unit to execute one of the following two operations and to use the operation result as the value of the fifth output signal to be outputted thereby in a next cycle: said fourth processing unit receiving the first and second pixel signals and the fifth output signal, and being controlled by said computation control unit to calculate a computation result of multiplying one of the first and second pixel signals by an integer value and then adding the fifth output signal, and to use the computation result as the value of the fourth output signal in a next cycle; said third processing unit receiving the first and second pixel signals and the fourth output signal, and being controlled by said computation control unit to execute one of the following two operations, and to use the operation result as the value of the third output signal in a next cycle: said second processing unit receiving the first and second pixel signals, the second output signal and the third output signal, and being controlled by said computation control unit to execute one of the following three operations, and to use the operation result as the value of the second output signal in a next cycle: said first processing unit receiving the value of the first output signal outputted thereby in a previous cycle, the first and second pixel signals, and the second output signal, and being controlled by said computation control unit to execute one of the following two operations and to use the operation result as the value of the first output signal: