Patent ID: 6268260
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method of forming a memory cell capacitor structure, comprising:depositing a first sacrificial layer over a substrate;forming a first opening in said first sacrificial layer;depositing a first electrode material layer over a top surface of said first sacrificial layer completely filling said first opening, wherein said first electrode material layer includes a substantially conductive material that remains substantially conductive upon exposure to oxygen;removing a portion of said first electrode material layer over down to at least about a level of said top surface of said first sacrificial layer to define a top surface of a first memory cell capacitor plate;depositing a second sacrificial layer over the top surface of the first memory cell capacitor plate and the first sacrificial layer;forming a second opening in said second sacrificial layer so that the second opening extends to the first memory cell capacitor plate;depositing a dielectric layer over a top surface of said second sacrificial layer and at least partially filling said second opening, said dielectric layer having electrical contact with said first memory cell capacitor plate;removing a portion of said dielectric layer over down to at least about a level of said top surface of said second sacrificial layer to define a top surface of a memory cell capacitor storage element;removing said second sacrificial layer;removing said first sacrificial layer; andforming a second memory cell capacitor plate over said memory cell capacitor storage element.