Patent ID: 7202134
Filing Date: 2007-04-10
Classification: H01L

Abstract:
1. A method of forming semiconductor transistors, comprising: forming a gate electrode over but insulated from a semiconductor body region for each of first and second transistors; performing a DDD implant to from DDD source and DDD drain regions in the body region for the first transistor; after said DDD implant, forming off-set spacers along side-walls of the gate electrode of each of the first and second transistors; after forming said off-set spacers, performing a LDD implant to from LDD source and LDD drain regions in the body region for the second transistor; after said LDD implant, forming main spacers adjacent the off-set spacers of at least the second transistor; and after forming the main spacers, performing a source/drain (S/D) implant to form a highly doped region within each of the DDD drain and source regions and the LDD drain and source regions, the highly doped regions being of the same conductivity type as and having a doping concentration greater than the DDD and LDD regions.