Patent ID: 6621146
Filing Date: 2003-09-16
Classification: H01L

Abstract:
An integrated circuit fabricated according to a given technology, comprising:a substrate; and a current mirror formed by first and second degenerated transistors and having a current input and a current output, wherein: the first degenerated transistor is electrically coupled to form a diode and comprises: a first control terminal formed on the substrate: a first channel formed in the substrate beneath the first control terminal; first and second heavily-doped regions embedded in the substrate on opposing sides of the first channel; first and second output contacts positioned on the first and second heavily-doped regions, respectively, wherein the second output contact is electrically coupled to the first control terminal and the current input; and a first lightly-doped region extending between the first heavily-doped region and the first channel for a first length that is selected such that the first output contact is spaced from a respective edge of the first control terminal by a first distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the first lightly-doped region has a desired first resistance in series with the first output contact; and the second degenerated transistor comprises: a second control terminal formed on the substrate and electrically coupled to the first control terminal; a second channel formed in the substrate beneath the second control terminal; third and fourth heavily-doped regions embedded in the substrate on opposing sides of the second channel; third and fourth output contacts positioned on the third and fourth heavily-doped regions, respectively, wherein the fourth output contact is electrically coupled to the current output; and a second lightly-doped region extending between the third heavily-doped region and the second channel for a second length that is selected such that the third output contact is spaced from a respective edge of the second control terminal by a second distance that is greater than the minimum distance and the second lightly-doped region has a desired second resistance in series with the third output contact.