Patent ID: 6586793
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A ferroelectric memory comprising:a semiconductor substrate; first, second, and third source/drain regions formed in a surface of the substrate, the first source/drain region being interposed between the second and third source/drain regions; first and second gate electrodes facing, through a gate insulating film, a first channel region between the first and second source/drain regions, and a second channel region between the first and third source/drain regions, respectively; an inter-level insulating film covering the first, second, and third source/drain regions; first, second, and third plugs penetrating the inter-level insulating film, and electrically connected to the first, second, and third source/drain regions, respectively; a first capacitor electrode disposed above the first source/drain region, and electrically connected to the first source/drain region via the first plug; first and second capacitor insulating films each comprising a ferroelectric film, formed on side surfaces of the first capacitor electrode facing the second and third source/drain regions; second and third capacitor electrodes disposed above the second and third source/drain regions, and electrically connected to the second and third source/drain regions via the second and third plugs, respectively, the second and third capacitor electrodes facing the first capacitor electrode through the first and second capacitor insulating films, respectively; a fourth source/drain region formed in the surface of the substrate, the second source/drain region being interposed between the first and fourth source/drain regions; a third gate electrode facing through a gate insulating film a third channel region between the second and fourth source/drain regions; the inter-level insulating film covering the fourth source/drain region; a fourth plug penetrating the inter-level insulating film, and electrically connected to the fourth source/drain region; a fourth capacitor electrode disposed above the fourth source/drain region, and electrically connected to the fourth source/drain region via the fourth plug; and a third capacitor insulating film comprising a ferroelectric film, formed on a side surface of the fourth capacitor electrode facing the second source/drain region, the second capacitor electrode facing the fourth capacitor electrode through the third capacitor insulating film, wherein the first and third capacitor insulating films comprise respective standing portions of a U-shaped insulating film disposed between the first and fourth capacitor electrodes, and the second capacitor electrode is disposed inside the U-shaped insulating film, and is electrically connected to the second plug via an upper plug penetrating a bottom portion of the U-shaped insulating film.