Patent ID: 8674442
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; a first well region formed by being doped in a first location on a surface of the substrate; a second well region formed by being doped in a different type from the first well region in a second location on a surface of the substrate; an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist; a gate insulating layer formed on a surface of the first and the second well regions and on a surface of the overlapping region; a gate electrode formed on the insulating layer; a source region formed on an upper portion of the first well region; and a drain region formed on an upper portion of the second well region, wherein a net doping concentration in the overlapping region gradually decreases from a boundary between the first well region and the overlapping region to a boundary between the second well region and the overlapping region, and a ratio of a length of the gate electrode to a length of the first well region overlapping the gate electrode ranges between 80% and 96%.