Patent ID: 7094646
Filing Date: 2006-08-22
Classification: H01L

Abstract:
1. A method of manufacturing a flash memory device having a split gate, comprising: sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate; forming an isolation layer in a predetermined region of the semiconductor substrate using a mask when the floating gate conductive layer is formed, thereby defining an active region; etching the mask to expose the floating gate conductive layer corresponding to a prearranged floating gate pattern; forming a local oxide layer by oxidizing the exposed floating gate conductive layer in the active region using the mask; forming a floating gate structure by patterning the floating gate conductive layer using the local oxide layer as a mask, sequentially stacking an inter-gate electrode insulating layer, a control gate conductive layer and a hard mask layer on a resultant structure on the semiconductor substrate; etching predetermined parts of the hard mask layer, control gate conductive layer, inter-gate electrode insulating layer and the local oxide layer to expose a predetermined part of the floating gate structure; forming an insulating spacer on a sidewall of the hard mask layer, a sidewall of the control gate conductive layer and a sidewall of the local oxide layer; and etching the floating gate structure using the insulating spacer as a mask, thereby defining a floating gate electrode and a source region.