Patent ID: 7437627
Filing Date: 2008-10-14
Classification: G11C

Abstract:
1. A method for determining a repair solution for a memory module in a test system, the memory module comprising a plurality of word lines and a plurality of bits lines, the method comprising: determining, for each memory area of the memory module, a defect datum; generating defect addresses for all defective memory areas; storing the defect addresses in the test system; and selecting one or more replacement redundant groups based on the defect addresses stored in the test system, wherein the defect addresses are stored in a memory unit which includes, for each of a plurality of word line groups, a first memory segment having a first number of defect address memory locations for storing defect addresses in the respective word line group and, for each of a plurality of bit line groups, a second memory segment having a second number of defect address memory locations for storing defect addresses in the respective bit line group; wherein each word line group comprises one or more of the word lines and each bit line group comprises one or more of the bit lines.