Patent ID: 6743643
Filing Date: 2004-06-01
Classification: C30B,H01L

Abstract:
A method of fabricating a memory cell, comprising steps of:providing a substrate, said substrate comprising a switch, a first insulator layer covering said switch, and a conductive plug, said conductive plug having a bottom end and a top end, said bottom end in electrical connection with said switch; thereafter forming a conductive diffusion barrier layer and a bottom electrode layer on said substrate; then removing a portion of said bottom electrode layer, of said conductive diffusion barrier layer, and of said first insulator layer, thereby forming a bottom electrode, a conductive diffusion barrier, and an over-etched portion of said first insulator layer, said conductive diffusion barrier having a conductive-barrier side edge and being located on said top end of said conductive plug, said bottom electrode having a bottom-electrode side edge and being located on said conductive diffusion barrier; whereby said removing said portion of said first insulator layer forms said over-etched portion of said first insulator layer and a moat space adjacent to said conductive diffusion barrier and said bottom electrode, said moat space being partially defined by a moat bottom and a moat sidewall, whereby said moat sidewall comprises said bottom-electrode side edge, said conductive-barrier side edge, and said over-etched portion of said first insulator layer; then forming a nonconductive oxygen barrier layer over said substrate; wherein said forming said oxygen barrier layer comprises depositing a portion of said oxygen barrier layer on said bottom-electrode side edge, on said conductive-barrier side edge, and on said over-etched portion of said moat sidewall so that said conductive oxygen barrier layer covers the interface between said bottom electrode and said conductive barrier layer and the interface between said barrier layer and said first insulator.