Patent ID: 7446687
Filing Date: 2008-11-04
Classification: H03M

Abstract:
1. A multi-bit delta-sigma modulator comprising: a first summation circuit configured to generate a first intermediate signal based on a summation of a first set of signals including a modulator input signal and a first feedback signal; a first integrator circuit configured to integrate the first intermediate signal to generate a first integrated signal; a second summation circuit configured to generate a second intermediate signal based on a weighted sum of a second set of signals including the first integrated signal and a second feedback signal; a filter circuit configured to process the second intermediate signal to generate a filtered signal, wherein the filter circuit includes a second integrator circuit; a quantizer configured to digitize the filtered signal to generate an N-bit modulator output signal, wherein N is an integer greater than one; and a feedback circuit configured to receive the N-bit modulator output signal and to generate the first feedback signal and the second feedback signal using a ternary digital-to-analog converter and an (N−1)-bit digital-to-analog converter, respectively.