Patent ID: 7816795
Filing Date: 2010-10-19
Classification: H01L,H05K,Y02P

Abstract:
1. A semiconductor device, comprising: a wiring substrate; a data processing device mounted on the wiring substrate; and a plurality of memory devices mounted on the wiring substrate and coupled to the data processing device, wherein the data processing device includes: wherein the wiring substrate includes: wherein the second branch wiring having the number of branches; wherein the number of branches of the second branch wiring is less than or equal to that of the first branch wiring; wherein the memory controller outputs command and address signals as a first frequency from the command and address terminals, and outputs a clock signal as a second frequency from the clock terminal; wherein the second frequency is set to multiple times of the first frequency; and wherein an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.