Patent ID: 6507521
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A semiconductor memory system having a plurality of memory cells which is formed in a semiconductor substrate and a decoder that selects one or more memory cells from said plurality of memory cells, wherein;said memory cells each comprise; a channel portion formed in said substrate; a source portion formed in said substrate; a drain portion formed in said substrate; a control gate portion; and a floating gate portion which is in an electrically suspended state between said channel portion and said control gate portion; and a ninth voltage achieving a level higher than a reference voltage is applied to said control gate portion, a tenth voltage achieving a level lower than said reference voltage is applied to said channel portion, an eleventh voltage achieving a level lower than said tenth voltage and said reference voltage are alternately applied to said source portion and a twelfth voltage achieving a level lower than said tenth voltage and a said reference voltage are alternately applied to said drain portion, at each of one or a plurality of selected memory cell selected from said plurality of memory cells by said decoder.