Patent ID: 6426293
Filing Date: 2002-07-30
Classification: H01L

Abstract:
A method for forming an IC (integrated circuit) interconnect structure by filling an IC (integrated circuit) interconnect opening within an insulating layer on a semiconductor wafer, the method including the steps of:A. forming a plurality of test interconnect structures with each test interconnect structure having a respective test alloy seed layer deposited onto sidewalls and a bottom wall of a respective test interconnect opening within an insulating layer and with a test fill conductive material formed to fill said respective test interconnect opening; wherein said respective test alloy seed layer of each of said test interconnect structures has a respective test thickness and a respective test concentration of a test alloy dopant within a test bulk conductive material; B. performing a respective test thermal anneal process at a respective test thermal anneal temperature for each of said plurality of test interconnect structures; C. measuring a respective test resistance of each of said plurality of test interconnect structures; D. forming said IC interconnect structure by depositing an alloy seed layer onto sidewalls and a bottom wall of said IC interconnect opening, said alloy seed layer within said IC interconnect opening being comprised of a bulk conductive material that is substantially same as said test bulk conductive material doped with an alloy dopant that is substantially same as said test alloy dopant, wherein said alloy seed layer has a desired thickness that is determined by the respective test thickness of the respective test alloy seed layer of one of the test interconnect structures having a respective test resistance that is closest to a desired resistance for said IC interconnect structure, and wherein said alloy seed layer has a concentration of said alloy dopant that is determined by the respective test concentration of the test alloy dopant of the respective test alloy seed layer of one of the test interconnect structures having a respective test resistance that is closest to said desired resistance for said IC interconnect structure; E. filling said IC interconnect opening with a fill conductive material that is substantially same as said test fill conductive material by growing said fill conductive material from said alloy seed layer for forming said IC interconnect structure within said IC interconnect opening; and F. performing a thermal anneal process at a thermal anneal temperature to anneal said alloy seed layer and said fill conductive material within said IC interconnect opening, wherein said thermal anneal temperature is determined by the respective test thermal anneal temperature of one of the test interconnect structures having a respective test resistance that is closest to said desired resistance for said IC interconnect structure.