Patent ID: 6190928
Filing Date: 2001-02-20
Classification: G03F,H01L

Abstract:
A method for actually measuring misalignment of via, comprising:forming field effect transistors on a silicon substrate; forming a metal interconnection line after depositing a metal layer and then patterning through a photolithography process and etching the metal layer; forming an inter metal dielectric layer on said metal interconnection line;coating a photoresist and then patterning said photoresist to form a patterned photoresist layer through a photolithography process with a via mask; forming a plurality of vias after etching the inter metal dielectric layer using the patterned photoresist layer as a mask; stripping the patterned photoresist layer and then etching the metal interconnection line using the inter metal dielectric layer as a mask;stripping the inter metal dielectric layer so as to transfer via pattern to the metal interconnection line; and measuring misalignment of via by measuring the relative distance between the via and the metal interconnection line through SEM.