Patent ID: 6498090
Filing Date: 2002-12-24
Classification: H01L,Y10T

Abstract:
A method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method, the method comprising the steps of:(a) forming a dielectric layer in which an uppermost wiring layer is formed; (b) forming a wiring groove for the wiring layer having a specified pattern and an opening section for a bonding pad section in the dielectric layer; (c) forming a first conduction layer for the wiring layer; (d) forming a second conduction layer over the first conduction layer, the second conduction layer comprising a different material from that of the first conduction layer; and (e) removing excess portions of the second conduction layer, the first conduction layer and the dielectric layer to planarize the second conduction layer, the first conduction layer and the dielectric layer, to thereby form a wiring layer having at least the first conduction layer in the wiring groove and a bonding pad section including a base conduction layer of the first conduction layer and an exposed conduction layer of the second conduction layer in the opening section for the bonding pad section.