Patent ID: 7989228
Filing Date: 2011-08-02
Classification: G01N,H01J

Abstract:
1. A method for manufacturing an integrated circuit device comprising: providing a substrate including a surface region, the surface region having a predetermined planarity; forming a thickness of material overlying the surface region, the thickness of material having a thickness surface region; forming a recessed region having a first depth within a portion of the thickness of material, the recessed region including a bottom portion and an edge region, the bottom portion being an exposed portion of the surface region of the substrate; forming a conformal layer of a uniform thickness overlying the thickness of material including the recessed region, bottom portion, and edge region, and filling a portion of the first depth such that a conformal layer surface is formed below the thickness surface region to cause the recessed region to have a second depth from the thickness surface region to the conformal layer surface region, wherein the conformal layer comprises a polysilicon material; filling an entirety of the recessed region to the second depth from the thickness surface region to the conformal layer surface region with a dielectric fill material overlying the conformal layer to form a resulting surface region, wherein the dielectric fill material directly contacts the conformal layer including the conformal layer surface region formed below the thickness surface region; planarizing the resulting surface region to form a pattern using the conformal layer having the uniform thickness by exposing the thickness surface region and maintaining a portion of the dielectric fill material; selectively removing a portion of the thickness of material and a portion of the dielectric fill material to form an elevated pattern structure from the pattern having the uniform thickness, the elevated pattern having a height above a surface region of the thickness of material, while maintaining the conformal layer substantially intact; calibrating a scanning electron microscope using the elevated pattern structure; and measuring a pattern size using the calibrated scanning electron microscope.