Patent ID: 6026018
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A non-volatile, static random access memory (nvSRAM) with immunity to a store disturb phenomena in which a manufacturing defect can corrupt or render unstable the bit of data resident in the static random access memory (SRAM) portion of the nvSRAM and in some cases, the bit of data resident in the non-volatile (nv) portion of the nvSRAM during the store operation, the non-volatile static random access memory comprising:a memory cell comprising:a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving a bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;wherein the capability of said non-volatile memory to receive a bit of data from said static random access memory is accomplished by store operation;wherein the capability of said non-volatile memory to transmit a bit of data back to said static random access memory is a recall operation;an interface for receiving signals relating to the store and recall operations;a controller for issuing store and recall operation related signals to said interface of said memory cell;wherein said controller is capable of issuing signals during a store operation to address a store disturb problem.