Patent ID: 7668272
Filing Date: 2010-02-23
Classification: G06F,H03K,H04L

Abstract:
1. An apparatus for providing digital data transfer linkage between first and second clock domains, comprising: a data path including a data input, a data output, and a plurality of data storage elements coupled between said data input and said data output; a first state machine operable for receiving a first clock signal and operable synchronously with said first clock domain for executing a cyclic sequence of states, each of said states associated with a different one of said data storage elements, wherein said first clock domain is controlled by said first clock signal; and a second state machine operable for receiving a second clock signal and operable synchronously with said second clock domain for executing said cyclic sequence of states, wherein said second clock domain is controlled by said second clock signal, and wherein said first clock signal and said second clock signal are mesochronous clock signals; said first state machine operable for commencing execution of said cyclic sequence of states in a first state thereof, and said second state machine operable for commencing execution of said cyclic sequence of states in a second state thereof which differs from said first state; said data path including an input controller coupled to said data input, said first state machine and said data storage elements, wherein said input controller is operable for coupling first specified ones of said data storage elements to said data input, each first specified data storage element selected based on a current state of said first state machine; and said data path including an output controller coupled to said data output, said second state machine and said data storage elements, wherein said output controller is operable for coupling second specified ones of said data storage elements to said data output, each second specified data storage element selected based on a current state of said second state machine; wherein the cyclic sequence of states used by both the first and second state machines (i) causes the input controller to couple the first specified data storage elements to the data input in an order of data storage elements defined by the cyclic sequence of states and (ii) causes the output controller to couple the second specified data storage elements to the data output in the order of data storage elements defined by the cyclic sequence of states.