Patent ID: 6180514
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method for forming interconnect, comprising:providing a semiconductor substrate;forming a first metal layer on a portion of said substrate;forming a first dielectric layer on said first metal layer and said substrate;forming a barrier layer on said first dielectric layer;forming a first photoresist layer on said barrier layer, wherein said first photoresist layer has a first pattern defining a trench area located over said first metal layer, and has a second pattern defining an etch stop area;etching said barrier layer by the first photoresist layer;forming a second dielectric layer over the etched barrier layer and the first dielectric layer;forming a second photoresist layer on said second dielectric layer, wherein said second photoresist layer has a first pattern substantially aligned with the first pattern of said first photoresist layer, and has a second pattern substantially aligned with the second pattern of said first photoresist layer;etching the second dielectric layer by the second photoresist layer, portion of said first dielectric layer over said first metal layer being further etched by the first pattern of the first photoresist layer, thereby trenches being formed in the first dielectric layer and the second dielectric layer;depositing said barrier layer into said trenches, wherein said barrier layer being formed on top surface of said trenches;forming a seed layer on sidewalls of the etched first dielectric layer and the second dielectric layer;filling the trenches by a second metal layer, wherein said second metal layer is selected from the group consisting of a copper alloy layer and an aluminium--copper alloy; andplanarizing said second metal layer to expose surface of said second dielectric layer.