Patent ID: 6803893
Filing Date: 2004-10-12
Classification: G09G

Abstract:
A scan rate controller, comprising:a write phase lock loop for receiving a horizontal synchronous signal from a host, and generating a write clock signal according to the horizontal synchronous signal; an analog-to-digital converter for sampling a video signal supplied from the host into a digital video signal, according to the write clock signal from the write phase lock loop; a read timing generator for receiving an oscillation signal from a crystal which oscillates uniformly, and generating a read timing clock signal, a read horizontal synchronous signal and a read vertical synchronous signal in response to the oscillation signal; a write timing generator for receiving the write clock signal from the write phase lock loop, and generating a write timing clock signal according to the write clock signal; a frame memory for storing the digital video signal output from the analog-to-digital converter according to the write clock signal from the write phase lock loop and the write timing clock signal from the write timing generator, and outputting the stored digital video signal according to the read timing clock signal from the read timing generator, said frame memory comprising: first and second R-frame memories for storing and outputting a red color signal of the digital video signal, according to the write and read timing clock signals which are respectively applied from the write timing generator and read timing generator; first and second G-frame memories for storing and outputting a green color signal of the digital video signal, according to the write and read timing clock signals which are respectively applied from the write timing generator and read timing generator; and first and second B-frame memories for storing and outputting a blue color signal of the digital video signal, according to the write and read timing clock signals which are respectively applied from the write timing generator and read timing generator; and a liquid crystal display panel for receiving the video signal from the frame memory according to a read clock signal applied from the read timing generator, and displaying the video signal according to the read horizontal and vertical synchronous signals applied from the read timing generator.