Patent ID: 6372565
Filing Date: 2002-04-16
Classification: G11C,H01L,Y10S

Abstract:
A method of manufacturing SRAM cell, comprising the steps of:providing a semiconductor substrate; forming a first and a second conductivity type wells in the substrate; forming isolating layers to define a first active region in the first conductivity well and a second active region in the second conductivity well; forming a gate insulating layer on the first and second active regions; forming first and second gates on the first active region which has the gate insulating layer formed thereon, and a third gate on the second active region which has the gate insulating layer formed thereon; forming impurity diffusion regions of the second conductivity type in the first active region of both sides of each of the first and second gates so that the one of the impurity diffusion regions is common between the first and second gates; and forming impurity diffusion regions of the first conductivity type in the second active region of both sides of the third gate.