Patent ID: 8319343
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a bond pad layer, comprising aluminum or an alloy thereof and including at least one bond pad segment and at least one interconnect runner segment, wherein the at least one interconnect runner segment and the at least one bond pad segment are located on a same level within the semiconductor device and extend through openings in a first passivation layer located under the bond pad layer to at least one copper runner segment of a final metallization layer located under the passivation layer and to electrically couple the at least one interconnect runner segment and the at least one bond pad segment to different portions of the final metallization layer; a second passivation layer located over the first passivation layer and the bond pad layer the second passivation layer having a solder bump opening located therein that exposes the bond pad segment; and an under bump metallization (UBM) layer located in the solder bump opening and physically, contacting the exposed bond bad segment.