Patent ID: 9040421
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A method for fabricating integrated circuits, the method comprising: providing a semiconductor substrate disposed with a device therein and/or thereon; forming a contact structure in electrical contact with the device, wherein the contact structure includes a barrier layer and a plug metal overlying the barrier layer; forming a hardmask overlying the contact structure; performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal; after performing the etch to form the via opening through the hardmask, forming a contact cap on the fill metal and barrier layer; removing a remaining portion of the hardmask with a wet etchant, wherein the contact cap inhibits the wet etchant from etching the barrier layer; and filling the via opening with a conductive material to form an interconnect to the contact structure.