Patent ID: 8957642
Filing Date: 2015-02-17
Classification: H01L,H03K

Abstract:
1. A power factor correction boost circuit comprising: an E-mode III-N switch coupled across positive and negative outputs of a full-bridge rectifier, said E-mode III-N switch comprising a silicon transistor coupled in series with a D-mode III-nitride device, wherein a gate of said D-mode III-nitride device is connected to a source of said silicon transistor; a normally off switch coupled to said E-mode III-N switch; a controller configured to control an on/off time of said E-mode III-N switch; said E-mode III-N switch and said normally off switch each having reduced charge storage, thereby causing said power factor correction boost circuit to have increased efficiency and operating frequency; said E-mode III-N switch configured as a power switch in said power factor correction boost circuit.