Patent ID: 6029233
Filing Date: 2000-02-22
Classification: G06F

Abstract:
An electrical circuit (5) for moving data blocks from a source memory unit (8, 9, 12) to a target memory unit (9, 12, 8), by means of a data path (5, 6, 7), characterized in that the electrical circuit comprisesfirst sending means (70, 71) for sending, in a given order, read requests to read blocks in the source memory unit, said first sending means including means (RLP, RAC) for generating an end marker in a request to read the last block of the source memory unit,storage means (80) for receiving the blocks read, in the form of response messages, in the order in which the read requests were sent, andsecond sending means (60, 61) for sending write requests to write, in the target memory unit, the blocks received in the storage means (80) during receiving of response messages until a message from the source memory unit with the end marker is received.