Patent ID: 6514792
Filing Date: 2003-02-04
Classification: H01L,H05K,Y02P

Abstract:
A method of mounting an integrated circuit package on a base substrate for electrical connection of an array of conductive surface mount terminations on the package to the base substrate comprising:calculating the area of highest joint strain energy density between the package and the base substrate; applying an adhesive mass to a bottom surface of the package at the area of highest joint strain energy density; aligning and attaching the array of conductive surface mount terminations and the adhesive mass to the base substrate; and fixing the adhesive mass; wherein the calculation of the area of highest joint strain energy density WGi is made using the equations WGi=ki{DNPi(&agr;sâˆ’&agr;pkg)i&Dgr;Ti}2 ki=Â¼ni&Sgr;(1/&Dgr;Kj)j=1,i &Dgr;Kj=(P/&Dgr;DNP)j/{1/(Eh )t+1/(Eh )pkg}j â€ƒwherein &agr;s is a local coefficient of thermal expansion of the base substrate; &agr;pkg is a local coefficient of thermal expansion of the package; i is an ith ring of joints from a neutral point of the package; DNPi is a distance to the neutral point of the package; &Dgr;Ti is a temperature excursion through which an ith ring cycles; ni is a number of joints in the ith ring; P is a joint pitch within the ring; &Dgr;DNP is a change in the distance from the neutral point of the package between successive rings; E is a modulus of elasticity; h is a structural thickness; t is a termination which forms a joint when mounted; pkg is the package; and ki and &Dgr;Kj are intermediary calculations.