Patent ID: 8489864
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. In a computing environment, a method of performing hardware based transactions, the method comprising: at a hardware thread on a processor beginning a hardware based transaction for the thread; without committing or aborting the transaction, suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring for the transaction, an abort for the transaction, or a commit for the transaction, wherein performing one or more operations for the thread comprises incrementing a count of a counter indicating a number of times a set of transactional instructions have been attempted without regard to whether the effects of the set of transactional instructions were eventually successful in that the effects were committed; after performing one or more operations for the thread, non-transactionally, resuming the transaction and performing additional operations transactionally; and after performing the additional operations, aborting the transaction while maintaining the count in the counter such that the count in the counter keeps track of the number of attempts to execute the set of transactional instructions whether the set of transactional instructions were successful or not.