Patent ID: 6574648
Filing Date: 2003-06-03
Classification: G06F,H04N

Abstract:
A DCT processor performing one-dimensional DCT operation or one-dimensional inverse DCT operation on pixel data of image data in unit blocks each comprising NÃ—M pixels (N,M: arbitrary integers from 1 to 8), comprising:bit slice means for receiving the pixel data of the image data in each NÃ—M unit block for each row or column, and slicing, bit by bit, the respective pixel data constituting the input rows or columns, and outputting the sliced pixel data; control means for outputting a control signal which includes the number of input pixel data that is the number of pixel data constituting each input row or column, and a value indicating that either the DCT operation or the inverse DCT operation is to be performed; first butterfly operation means for subjecting the output data from the bit slice means to the butterfly operation and outputting the result of the butterfly operation in the case where the control signal outputted from the control means indicates that the number of input pixel data is a power of 2 and that the DCT operation is to be performed, and in the cases other than mentioned above, said first butterfly operation means performing no butterfly operation and outputting the output data of the bit slice means as it is; address generation means for generating addresses on the basis of bit strings obtained from the output data of the first butterfly operation means, and the number of input pixel data and the value indicating that either the DCT operation or the inverse DCT operation is to be performed, which are included in the control signal; operation means having eight sets of multiplication result output means and accumulation means, said multiplication result output means outputting the results of multiplication to be used for obtaining the results of the one-dimensional DCT and inverse DCT operations, in accordance with the above-described addresses, and said accumulation means accumulating the output data from the multiplication result output means and outputting the accumulated data; and second butterfly operation means for subjecting the output data from the operation means to the butterfly operation and outputting the result of the butterfly operation after rearranging it according to the order of input pixel data in the case where the control signal outputted from the control means indicates that the number of input pixel data is a power of 2 and that the inverse DCT operation is to be performed, and in the cases other than mentioned above, said second butterfly operation means performing no butterfly operation and outputting the output data of the operation means after rearranging it according to the order of input pixel data.