Patent ID: 7974126
Filing Date: 2011-07-05
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the static memory cells, the read bit line including at least a first read bit line and a second read bit line; a write bit line for transmitting data to be written to one of the static memory cells; an input data line for transmitting data which is received from outside of the static memory cells; and a selector physically connected to the first read bit line, the write bit line, and the input data line, wherein the selector selects one of the first read bit line and the input data line, the selector electrically connects the selected one to the write bit line, the second read bit line is not connected to the selector, each of the static memory cells includes a first cell output transistor connected to the first read bit line and a second cell output transistor connected to the second read bit line, and a size of the first cell output transistor is smaller than a size of the second cell output transistor.