Patent ID: 6221697
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method of making a chip scale package comprising the steps of:providing a substrate having an upper surface, a lower surface, and a slot defined therein, the substrate being provided with a plurality of solder pads on the upper surface thereof and a plurality of leads within the slot, wherein the substrate has a plurality of through-holes corresponding to the solder pads, and each of the leads has at least one end electrically connected to the corresponding solder pad;attaching two individual elastomer pads respectively onto the upper surface of the substrate in a manner that each of the two individual elastomer pads flanks the slot of the substrate at a predetermined distance from the slot;providing a semiconductor chip having a plurality of bonding pads centrally formed thereon;attaching the semiconductor chip onto the upper surface of the substrate in a manner that the bonding pads are exposed from the slot of the substrate;electrically coupling the leads of the substrate to the bonding pads of the semiconductor chip in a manner that each of the leads is electrically connected to the corresponding bonding pad; andforming a package body having a first portion on the upper surface of the substrate around the chip and a second portion within the slot of the substrate, wherein the first portion and the second portion are formed substantially at the same time.