Patent ID: 6111449
Filing Date: 2000-08-29
Classification: H03K

Abstract:
A semiconductor device comprising:a signal line;a first transistor having a first conduction node connected to said signal line, a second conduction node receiving a voltage at a first power source node and a control electrode node, said first transistor having a well region of a second conductivity type formed on a surface of a substrate region of a first conductivity type, a first impurity region of said first conductivity type formed in said well region and coupled to said first conduction node a second impurity region of said second conductivity type formed in said well region and connected to said control electrode node, and a third impurity region of said first conductivity type formed in said well region between said first and second impurity regions and spaced apart therefrom and connected to said second conduction node; anda control bias voltage generation circuit coupled to said control electrode node for applying a bias voltage different in level from the voltage of said first power source node to said control electrode node.