Patent ID: 6188272
Filing Date: 2001-02-13
Classification: H03H,H03K

Abstract:
A filter circuit comprising:a first MIS transistor having a first source, a first drain, a first gate, and a channel of one conductivity type;an input terminal connected to the first gate of the first MIS transistor;a first power supply terminal connected to the first source of the first MIS transistor;a second MIS transistor having a second source, a second drain, a second gate, and a channel of the one conductivity type, the second source being connected to the first drain of the first MIS transistor;a first bias supply circuit connected to the second gate of the second MIS transistor;a second power supply terminal connected to the second drain of the second MIS transistor;a third MIS transistor having a third source, a third drain, a third gate, and a channel of the one conductivity type, the third source being connected to the first power supply terminal;a resistor connected between the third gate of the third MIS transistor and the input terminal;a capacitor connected between the third gate of the third MIS transistor and the first power supply terminal;a fourth MIS transistor having a fourth source, a fourth drain, a fourth gate, and a channel of the one conductivity type, the fourth source being connected to the third drain of the third MIS transistor, the fourth drain being connected to the second power supply terminal, and a width/length ratio of the fourth gate being substantially 1/4 of that of the third gate of the third MIS transistor;a second bias supply circuit connected to the fourth gate of the fourth MIS transistor;a fifth MIS transistor having a fifth source, a fifth drain, a fifth gate, and a channel of the one conductivity type, the fifth source being connected to the first power supply terminal, and the fifth gate being connected to the fourth source of the fourth MIS transistor;an output terminal connected to the fifth drain of the fifth transistor; anda sixth MIS transistor having a sixth source, a sixth drain, a sixth gate, and a channel of the one conductivity type, the sixth gate being connected to the second source of the second MIS transistor, the sixth source being connected to the fifth drain of the fifth MIS transistor and the output terminal, and the sixth drain being connected to the second power supply terminal.