Patent ID: 7126407
Filing Date: 2006-10-24
Classification: G06F,H03K,H03L

Abstract:
1. A method for generating at least one desired clock signal having predetermined clock signal properties, comprising the following steps: a) providing a plurality of clock signals having substantially the same frequency and respectively different phase relations each with respect to a master clock signal; (b) providing a control signal, the control signal including an enable signal sequence having a plurality of enable signals, wherein an enable signal for each of the plurality of clock signals is provided, and wherein the enable signal sequence indicates a frequency and a duty cycle of the desired clock signal to be generated; (c) on the basis of the control signal, selecting predetermined clock signals from the plurality of provided clock signals; and (d) combining the selected clock signals to generate the desired clock signal, and wherein each of the enable signals is provided delayed in order to set an alignment of each enable signal and the associated provided clock signal.