Patent ID: 7919986
Filing Date: 2011-04-05
Classification: H03K

Abstract:
1. An input bias control for a module input comprising: an input buffer receiving an external input signal via an input terminal; a clock detect circuit receiving an external clock signal and generating a clock detect signal indicating whether the external clock signal is detected; a pull-up transistor having a source-drain path connected between a positive supply voltage and said input terminal and a gate; a pull-down transistor having a source-drain path connected between ground and said input terminal and a gate; and an operational state detect circuit receiving said clock detect signal and responsive to an operational state of the module, said operational state detect circuit connected to said gate of said pull-up transistor and said gate of said pull-down transistor, said operational state detect circuit enabling one of said pull-up and pull-down transistors corresponding to said operational state of the module when said clock detect signal indicates said external clock signal is detected.