Patent ID: 6835612
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A method for fabricating a MOSFET with a gate channel of a predetermined, very small channel length, the method which comprises the following steps:producing a dielectric on a semiconductor substrate; applying a first gate layer to the dielectric, the first gate layer comprising polysilicon; forming an intermediate layer, to serve as a diffusion barrier, on the first gate layer; applying a second gate layer, the second gate layer comprising tungsten; masking the second gate layer to define a width of the second gate layer to be greater than the predetermined channel length; anisotropically etching the second gate layer, the intermediate layer, and the first gate layer; isotropically laterally undercutting the first gate layer under the second gate layer selectively with respect to the dielectric, with respect to the intermediate layer, and with respect to the second gate layer, thereby utilizing an etching gas containing hydrogen bromide in a dry etching process, and controlling the etching process for forming the first gate layer with a predetermined width less than the width of the second gate layer and corresponding to the predetermined channel length.