Patent ID: 6387768
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method of manufacturing a semiconductor component comprising:providing a substrate, a first electrically insulative layer over the substrate, and a first electrically conductive layer over the first electrically insulative layer; etching a hole into a portion of the first electrically conductive layer and into a portion of the first electrically insulative layer; depositing a second electrically conductive layer in the hole; etching the first and second electrically conductive layers to leave a portion of the second electrically conductive layer in the hole; growing a third electrically conductive layer over the substrate and extending over the portion of the second electrically conductive layer, where the second electrically conductive layer is electrically coupled to the third electrically conductive layer; providing a second electrically insulative layer over the first electrically conductive layer; etching a hole in the second electrically insulative layer; forming a spacer in the hole in the second electrically insulative layer and over the portion of the first electrically conductive layer; forming a third electrically insulative layer over the first electrically conductive layer and adjacent to the spacer; and removing the spacer after forming the third electrically insulative layer.