Patent ID: 7105889
Filing Date: 2006-09-12
Classification: H01L

Abstract:
1. A complementary metal oxide semiconductor (CMOS) structure comprising: a semiconductor substrate having a first device region and a second device region, said first device region is an area for at least one nFET device and said second device region is an area for at least one pFET device; said first device region comprising at least one first gate stack comprising, from bottom to top, a first high k gate dielectric disposed directly on said semiconductor substrate and a first gate conductor disposed on said first high k gate dielectric, said second device region comprising at least one second gate stack comprising, from bottom to top, a second high k gate dielectric disposed directly on said semiconductor substrate, an insulating interlayer atop said high k gate dielectric, and a second gate conductor atop said insulating interlayer, wherein said insulating interlayer stabilizes said second device regions threshold voltage and flatband voltage without shifting said first device region's threshold voltage and flatband voltage.