Patent ID: 6038196
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A semiconductor memory device comprising:a) a control/address input device controlled by address and control signals;b) a row and column address counter operated by an output signal of said control/address input device;c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input;d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; ande) a memory cell array operated by output signals of said row address decoder and column address decoder;wherein said row and column address counter includes:1) a first unit row and column counter for outputting:1a) a first column count signal and1b) a first row count signal; according to:1c) a column control signal and1d) a row control signal;2) a second unit row and column counter for outputting:2a) a second column count signal and2b) a second row count signal; according to:2c) said column control signal,2d) said row control signal,2e) said first column count signal and2f) said first row count signal; and3) at least one gate for logically operating on:3a) said first column count signal and3b) said second column count signal: and for providing an output to a third unit row and column counter.