Patent ID: 7171609
Filing Date: 2007-01-30
Classification: H03M

Abstract:
1. A processor for convolutional decoding, said processor embodying a pipelined superscalar processor core, comprising: an instruction prefetch unit, the instruction prefetch unit configured to simultaneously fetch first and second Viterbi instructions and to partially decode and align the first and second Viterbi instructions; an instruction sequencing unit, the instruction sequencing unit configured to fully decode the partially decoded first and second Viterbi instructions and to group the fully decoded first and second Viterbi instructions for simultaneous execution; a first processing unit for executing a first Viterbi instruction, the instruction sequencing unit issuing the first Viterbi instruction to the first processing unit; a second processing unit for executing a second Viterbi instruction, the instruction sequencing unit issuing the second Viterbi instruction to the second processing unit; a register comprising a plurality of ordered bit positions; and update logic coupled to the register, the first processing unit and the second processing unit, the update logic configured to receive a first signal indicative of a result of a first add-compare-select instruction from the first processing unit and a second signal indicative of a result of a second add-compare-select instruction from the second processing unit, the update logic further configured to update the contents of the register dependent upon the first and second signals; wherein, in the event that: (1) the first signal but not the second signal, or (2) the second signal but not the first signal, is received, the update logic is configured to shift the contents of the register such that one bit position is vacated and to update the vacated bit position dependent on the received signal; and wherein in the event the first and second signals are received substantially simultaneously, the update logic is configured to shift the contents of the register 2 bit positions in order thereby vacating 2 consecutive bit positions, to update one of the vacated bit positions dependent upon the first signal, and to update the other vacated bit position dependent upon the second signal.