Patent ID: 7345500
Filing Date: 2008-03-18
Classification: G01R

Abstract:
1. A system for testing transistors, the system comprising: a plurality of pads; a plurality of transistors including a first transistor, the first transistor including a first terminal, a second terminal, a third terminal, and a fourth terminal; a decoder coupled to the plurality of transistors and configured to receive a plurality of selection signals from the plurality of pads and to select the first transistor from the plurality of transistors based on at least information associated with the plurality of selection signals; a first pad coupled to the first terminal of the first transistor through a second transistor, the first terminal of the first transistor being either a source terminal or a drain terminal of the first transistor; a second pad coupled to the second terminal of the first transistor through a third transistor, the second terminal of the first transistor being a gate terminal of the first transistor; a third pad electrically connected to the third terminal of the first transistor, the third terminal being a substrate terminal of the first transistor; and a fourth pad electrically connected to the fourth terminal of the first transistor, the fourth terminal being the source terminal of the first transistor if the first terminal is the drain terminal of the first transistor, or the drain terminal of the first transistor if the first terminal is the source terminal of the first transistor; wherein: the first pad is electrically connected to at most three of the plurality of the transistors including the first transistor; the second pad is electrically connected to at most three of the plurality of the transistors including the first transistor; the second transistor comprises a fourth terminal, a fifth terminal, and a sixth terminal; the third transistor comprises a seventh terminal, a eighth terminal, and a ninth terminal; the sixth terminal is a gate terminal of the second transistor; the ninth terminal is a gate terminal of the third transistor; the fourth terminal and the fifth terminal of the second transistor are either a source terminal or a drain terminal of the second transistor, the fourth terminal being the drain terminal of the second transistor if the fifth terminal is the source terminal of the second transistor and the fourth terminal being the source terminal of the second transistor if the fifth terminal is the drain terminal of the second transistor; the seventh terminal and the eighth terminal of the third transistor are either a source terminal or drain terminal of the third transistor, the seventh terminal being the drain terminal of the third transistor if the eighth terminal is the source terminal of the third transistor and the seventh terminal being the source terminal of the third transistor if the eighth terminal is the drain terminal of the third transistor; the first pad is coupled to the first terminal of the first transistor further through an electrical connection between the first pad and the fourth terminal of the second transistor and an electrical connection between the fifth terminal of the second transistor and the first terminal of the first transistor; the second pad is coupled to the second terminal of the first transistor further through an electrical connection between the second pad and the seventh terminal of the third transistor and an electrical connection between the eighth terminal of the third transistor and the second terminal of the first transistor; the decoder is further configured to generate a control signal based on at least information associated with the plurality of selection signals; the sixth terminal of the second transistor and the ninth terminal of the third transistor are electrically connected; and the sixth terminal of the second transistor and the ninth terminal of the third transistor are adapted to receive the control signal from the decoder to select the first transistor for testing.