Patent ID: 7409602
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. An apparatus comprising: an analysis block configured to generate debug information post-simulation in response to (i) a command input, (ii) one or more simulation outputs, (iii) one or more compiler outputs and (iv) memory map information; a graphical user interface configured (i) to present said command input in response to one or more user input parameters and (ii) to display said debug information; and a memory circuit configured to store said memory map information, said one or more simulation outputs and said one or more compiler outputs, wherein (i) said one or more simulation outputs comprise one or more tracings selected from the group consisting of a tracing of processor accesses on a memory bus, a tracing of instruction execution and a tracing of processor internal register status and (ii) said one or more compiler outputs comprise one or more outputs selected from the group consisting of a map file and an in-line disassembler.