Patent ID: 6927611
Filing Date: 2005-08-09
Classification: H03L,H04L

Abstract:
1. A semidigital delay-locked loop circuit comprising: a controllable delay element having a clock input and a phase input, and a clock signal output, wherein signals on the clock signal output have a changing phase controlled by phase data received at the phase input; a phase detector, a first input, a second input, an up output, a down output, and a data output, wherein data is received at the first input, the second input is connected to the clock signal output, and wherein the phase detector generates up signals through the up output and down signals through the down output in response to data received at the first input; and an analog based finite state machine having an up input connected to the up output, a down input connected to the down output, and phase output connected to the phase input of the controllable delay element, wherein the analog based finite state machine generates the phase data in response to up signals and down signals received from the phase detector.