Patent ID: 7818619
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A method of testing a system under test (SUT), the method comprising: providing a debugging system with a first processor including a first memory mapping input output (I/O) interface and further providing the debugging system with a first I/O controller; providing the system under test (SUT) with a second processor including a second memory mapping input output (I/O) interface and further providing the SUT with a second I/O controller; configuring the debugging system and the SUT together in a cluster mode wherein the first processor acts as a debugging master that executes debugging software and the second processor acts as a slave that executes application software, the first processor communicating with the second processor via a memory mapping interface bus between the first and second memory mapping I/O interfaces and further configuring the debugging system and the SUT to communicate with one another via an external bus between the first I/O controller and the second I/O controller; and conducting test operations, by the debugging system, on the SUT wherein the test software in the debugging system accesses at least one of memory, registers and nonvolatile storage of the SUT via the memory mapping interface bus and the debugging system controls the test operations on the SUT via the first and second I/O controllers and external bus.