Patent ID: 6284600
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method for minimizing degradation of an interface between a bit line junction and a control dielectric structure during program or erase operations of a flash memory device, the method including the steps of:A. patterning a semiconductor wafer having a control dielectric stack thereon to expose a bit line area and to mask a control gate area of said semiconductor wafer;B. implanting a junction dopant into said exposed bit line area to form said bit line junction in said bit line area of said semiconductor wafer;C. implanting a predetermined species into said exposed bit line area;D. patterning said control dielectric stack such that said control dielectric stack is removed from said exposed bit line area and such that said control dielectric stack remains at said control gate area to form said control dielectric structure; andE. performing a thermal process that heats up said semiconductor wafer;wherein said bit line junction extends under said control dielectric structure from thermal diffusion of said junction dopant to form said interface between said bit line junction and said control dielectric structure;and wherein said predetermined species implanted within said semiconductor wafer thermally drifts to said interface between said bit line junction and said control dielectric structure during said thermal process, and wherein said predetermined species at said interface minimizes formation of interface defects at said interface during hot carrier injection through said interface.