Patent ID: 6725359
Filing Date: 2004-04-20
Classification: G06F

Abstract:
An apparatus in a pipeline microprocessor for providing a speculative address operand associated with a result of a first arithmetic operation, the first arithmetic operation being prescribed by a first preceding micro instruction, the apparatus comprising:speculative operand calculation logic within an address stage of the pipeline microprocessor, configured to perform arithmetic operations to generate interim results prior to when execute logic executes corresponding preceding micro instructions to generate associated results, wherein said first preceding micro instruction is one of said corresponding preceding micro instructions; and an update forwarding cache, coupled to said speculative operand calculation logic, configured to temporarily store said interim results, wherein an address-dependent micro instruction, upon entry into a previous register stage can retrieve the speculative address operand, the speculative address operand being configured from one of more of said interim results, thereby permitting said address-dependent micro instruction to proceed without incurring delay; wherein the speculative address operand is to be obtained from the result that is to be generated when said execute logic executes the first preceding micro instruction, and wherein the result has not yet been generated by said execute logic and written to a register file for access by following micro instructions.