Patent ID: 8688892
Filing Date: 2014-04-01
Classification: G11C

Abstract:
1. A method for optimizing a memory subsystem for energy-efficient operation, the method including having a memory controller and at least one memory module, said at least one memory module containing firmware and a plurality of double data rate memory components, the memory components supporting page mode access, a bank activate command having associated therewith a RAS-to-CAS delay, a read command having associated there with a CAS latency and a precharge command having associated there with a precharge latency, the method comprising: setting the firmware for low voltage operation including: setting the CAS latency to a CAS latency that is greater than a minimum CAS latency value supported at a frequency, setting an operating voltage for the at least one memory module to a lower voltage than that required by the minimum CAS latency at the frequency, and setting at least one of the RAS-to-CAS delay and the precharge latency to a RAS-to-CAS latency value and a precharge value, respectively, lower than the set minimum CAS latency value to minimize access times of consecutive accesses in which a subsequent access is out of page from an immediate access; using said precharge command to close a first page where the immediately previous access occurred; and using said bank activate command to open a second page different than the first page to access data within said second page using the read command.