Patent ID: 6166946
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A memory cell, comprising:a first bit line;a second bit line;an input line;an output line;a storage element having a first port and a second port, said storage element configured to control a value of said first port and a value of said second port, said storage element further configured to maintain said value of said first port as an inverse of said value of said second port;a first switching element coupled to said first port and to said first bit line, said first switching element configured to activate and deactivate in response to a first select signal, said first switching element further configured to electrically connect said first port to said first bit line when activated and to electrically disconnect said first port from said first bit line when deactivated;a second switching element coupled to said second port and to said second bit line, said second switching element configured to activate and deactivate in response to a second select signal, said second switching element configured to electrically connect said second port to said second bit line when activated and to electrically disconnect said second port from said second bit line when deactivated;a multiplexer coupled to said output line, said multiplexer configured to receive a value from said first bit line and to receive a value from said second bit line and to select one of said values received by said multiplexer based on a mode signal, said multiplexer further configured to transmit said one value selected by said multiplexer across said output line; anda switching mechanism coupled to said input line, said switching mechanism configured to receive an input value from said input line and, based on said mode signal, to select one of said bit lines, said switching mechanism further configured to electrically connect said selected one of said bit lines to said input line and to electrically disconnect the other bit line from said input line.