Patent ID: 6532533
Filing Date: 2003-03-11
Classification: G06F

Abstract:
A processing device comprising:a plurality of mask registers, each mask register having a plurality of bits; a plurality of input/output pins corresponding to respective bits of each mask register; one or more data registers coupled to said input/output pins, each of said data registers having a plurality of bits corresponding to respective bits of each mask register, each data register having a memory mapped address corresponding to each mask register; and logic circuitry for accessing said data registers via said memory mapped addresses, whereby upon memory mapped access to one of said data registers access to a bit of said data register is permitted if said corresponding bit of said mask register corresponding to said memory mapped address has a first digital state and access to a bit of said data register is prohibited if said corresponding bit of said mask register corresponding to said memory mapped address has a second digital state opposite to said first digital state.