Patent ID: 7883955
Filing Date: 2011-02-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a layer of insulating material over high voltage PMOS, high voltage NMOS, and low voltage MOS transistor formation regions of a semiconductor substrate; patterning the layer of insulating material to form first isolation structures for the high voltage PMOS and for the high voltage NMOS transistor formation regions; forming and patterning a layer of masking material to cover channel regions of the high voltage NMOS and low voltage MOS transistor formation regions; with the channel regions of the high voltage NMOS and low voltage MOS transistor formation regions covered, conducting a first thermal oxidation to form a first gate dielectric layer over a channel region of the high voltage PMOS transistor formation region and to simultaneously form second isolation structures for the low voltage MOS transistor formation region; following the first thermal oxidation, removing the patterned layer of masking material from the channel regions of the high voltage NMOS and low voltage MOS transistor formation regions; and following removal of the patterned layer of masking material, conducting a second thermal oxidation to form second gate dielectric layers simultaneously over the channel regions of the high voltage NMOS and low voltage MOS transistor formation regions; the second gate dielectric layers being formed to a thickness less than the thickness to which the first gate dielectric layer is formed.