Patent ID: 6541327
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A method of fabrication of an elevated Self-Aligned Source/Drain CMOS device on a staircase shaped insulating layer; comprising the steps of:a) forming gate structure over a substrate; said gate structure comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask; b) forming a first insulating layer over said substrate; c) forming a resist layer having an opening over said gate structure and over a lateral area adjacent to said gate structure; said opening is over at least all of said gate structure; said resist layer is not over said gate structure; d) etching said first insulating layer through said opening in said resist layer; the etching removing a first thickness of said first insulating layer to form a source/drain (S/D) opening; said source/drain contact open defined by said gate and said first insulating layer; e) removing said first spacers and said hardmask to form a source/drain (S/D) contact opening; f) implanting ions into said substrate through said source/drain (S/D) contact opening to form lightly doped drain regions; g) forming second spacers on the sidewalls of said gate electrode and said gate dielectric and on the sidewalls of said first insulating layer in said source/drain (S/D) contact opening and said source/drain (S/D) opening; h) depositing a conductive layer over said gate electrode, said first insulating layer; and i) planarizing said conductive layer to exposed said first insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.