Patent ID: 6337504
Filing Date: 2002-01-08
Classification: H01L,Y10S

Abstract:
An insulated gate transistor, comprising:a gate oxide film formed on a silicon substrate to create an oxidation/silicon interface with a silicon face of the silicon substrate; a gate electrode formed over the silicon substrate with the gate oxide film interposed therebetween, the gate oxide film extending continuously along a gate-length direction under respective side-walls of the gate electrode to form extending portions, the extending portions extending in an outward direction from side walls of said gate electrode; thermal oxide films disposed on the side walls of the gate electrode, each thermal oxide film linking with a respective extending portion of the gate oxide film; a source and a drain disposed in a surface of the silicon substrate, lateral diffusion edges of the source and the drain being positioned horizontally inside respective outward surface positions of the thermal oxide films on the respective side walls of the gate electrode; insulation layers disposed on the side walls of the gate electrode which cover the thermal oxide films and the extending portions of the gate oxide film; and conductive silicide films disposed on respective surfaces of the gate electrode, the source and the drain, wherein: the deposited insulation layers cause electrical separation of the conductive silicide film on the gate electrode from the respective conductive silicide films on the source and the drain; and the extending portions of the gate oxide film defining lateral edges of the conductive silicide films disposed on the respective surfaces of the source and the drain at positions spaced apart from the lateral diffusion edges of the source and the drain respectively, whereby an influence due to an invasion of the conductive silicide films along the oxidation/silicon interface is restrained.