Patent ID: 6717270
Filing Date: 2004-04-06
Classification: H01L

Abstract:
An integrated circuit (IC) die including a plurality of input/output (I/O) cells, each I/O cell of the plurality comprising:active I/O circuitry located in a substrate of the IC die; a plurality of metal interconnect layers formed over the substrate, the plurality of metal interconnect layers including a first power supply conductor, a second power supply conductor, and a signal conductor; an insulating layer formed over the plurality of metal interconnect layers; a first pad formed over the insulating layer and coupled to the signal conductor; and a second pad formed over the insulating layer, the second pad directly over at least two metal structures in a top metal layer of the plurality of metal interconnect layers, wherein the second pad being selectively coupled to one of the at least two metal structures through at least one opening in the insulating layer.