Patent ID: 8144518
Filing Date: 2012-03-27
Classification: G11C

Abstract:
1. A semiconductor device comprising: a central processing unit; a rewritable nonvolatile memory targeted for access by the central processing unit, wherein the nonvolatile memory includes a memory array, and a plurality of electrically rewritable nonvolatile storage devices each having a select terminal connected with a select control line and a data terminal connected with a data line, wherein one pair of the storage devices sharing the select control line can form a twin cell, a first read circuit for differentially amplifying complementary data read out to different data lines from a pair of storage devices of the twin cell selected by the select control line, a second read circuit for amplifying data read out from one storage device of the selected twin cell, a write control circuit, an external interface circuit, wherein the write control circuit has a write mode for forcing a pair of storage devices of the selected twin cell to hold non-inverted data and inverted data of write data of one bit, wherein the external interface circuit has a first read mode for outputting data resulting from differential amplification of non-inverted data and inverted data read out from a pair of storage devices of the selected twin cell by the first read circuit to outside, and a second read mode for outputting data resulting from amplification of data read out from one storage device of the selected twin cell by the second read circuit to the outside.