Patent ID: 9208074
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. A data storage device, comprising: a FLASH memory, providing storage space divided into a plurality of blocks with each block comprising a plurality of pages; a random access memory; and a controller, operating the FLASH memory in accordance with commands issued from a host, wherein: when a master buffer block selected from the plurality of blocks of the FLASH memory to buffer write data from the host is full, the controller updates a logical-to-physical address mapping table for the master buffer block based on a master buffer block physical-to-logical address mapping table in separated update sub-intervals; the logical-to-physical address mapping table is maintained on the FLASH memory; the master buffer block physical-to-logical address mapping table is maintained in the random access memory corresponding to the master buffer block; between the separated update sub-intervals, the controller responds to commands from the host; and the controller further selects a slave buffer block from the plurality of blocks of the FLASH memory to buffer write data between the separated update sub-intervals.