Patent ID: 7601584
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor array, the method comprising the steps of: producing a dielectric on a mono-crystalline semiconductor region having a first conductivity type; depositing a silicide layer and patterning the silicide layer so that the silicide layer is insulated from the mono-crystalline semiconductor region by the dielectric; and applying a semiconductor layer having a second conductivity type to the mono-crystalline semiconductor region and to the silicide layer, to form a base region, in such a way that the second semiconductor layer lies with a first interface on the mono-crystalline semiconductor region and with a second interface on the silicide layer, wherein, substantially the entirety of an upper surface of the silicide layer directly contacts a lower surface of the semiconductor layer, and wherein a plane formed by the upper surface of the silicide layer and a plane formed by the lower surface of the semiconductor layer are substantially parallel to a plane formed along the first interface where the semiconductor layer contacts the mono-crystalline semiconductor region.