Patent ID: 7165128
Filing Date: 2007-01-16
Classification: G06F,H04L

Abstract:
1. A data and communication apparatus communicatively coupled with a multi-processor shared memory multimedia chip system for providing interprocessor communication while enhancing performance of each processor integral with said multi-processor shared memory multimedia chip system, said data and communication apparatus comprising: a data memory to retrievably store data; an instruction memory coupled with said data memory to retrievably store instructions; an incoming buffer coupled with said data memory and said instruction memory which permits transfer of data into said data and communication apparatus, said incoming buffer further adapted to provide fast access to streaming data and perform prefetch operations; an outgoing buffer coupled with said data memory and said instruction memory which monitors and permits transfer of data out of said data and communication apparatus, said outgoing buffer enables said each processor to communicate with other processors disposed within said system; and multiple registers coupled with said data and communication apparatus, said registers adapted to provide enhanced configurability and control of said data memory and said instruction memory, said registers further adapted to provide addressable memory storage locations for said retrievably stored data and said retrievable stored instructions, said registers separate from and in addition to the registers within said multi-processor shared memory multimedia chip system.