Patent ID: 6444554
Filing Date: 2002-09-03
Classification: G11C,H01L

Abstract:
A method of manufacturing a semiconductor device, comprising steps of:(a) forming a first conductive film over a memory cell forming region and a peripheral circuit region of a semiconductor substrate; (b) patterning said first conductive film in said memory cell forming region to form a first conductor pattern; (c) forming an insulating film over said first conductor pattern, said memory cell forming region and said first conductive film of said peripheral circuit region and polishing said insulating film to form a first insulating film on non-patterned portions of said first conductor pattern; (d) forming a second conductor pattern over said first conductor pattern, said first insulating film and said first conductive film of said peripheral circuit region; (e) forming a second insulating film over said second conductor pattern; (f) forming a second conductive film over said second insulating film; and (g) patterning said second conductive film, said second conductor pattern, said first conductor pattern and said first conductive film of said peripheral circuit region at said memory cell forming region and said peripheral circuit region, wherein, in said step (g), said second conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell, wherein, in said step (g), said first conductor pattern and said second conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and wherein, in said step (g), at least said first conductive film and said second conductor pattern of said peripheral circuit region are patterned to form a gate electrode of a MISFET.