Patent ID: 9048217
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A method comprising: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate, the at least one gate structure having: a gate region contacting the substrate; a set of spacers adjacent to the gate region and contacting the substrate; a replacement metal gate (RMG) cap overlying the gate region between the set of spacers; and an interlayer dielectric (ILD) overlying the substrate and substantially surrounding the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of the gate region; and forming a dielectric in the opening in the conductor; further comprising forming a raised source-drain region over the exposed substrate proximate the at least one gate structure after the removing of the ILD and prior to the forming of the silicide layer over the substrate; wherein the forming of the silicide layer over the substrate includes forming the silicide layer over the raised source-drain region.