Patent ID: 8557700
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A method for manufacturing a chip-size double side connection package configured such that a semiconductor chip including a semiconductor substrate on which a LSI region and electrode connection regions are formed is connected to wiring for external connection provided on a first main face and to wiring for external connection provided on a second main face, the first main face and the second main face being located above and below the semiconductor chip, respectively, the method comprising: forming a wiring-added post electrode component having a plurality of post electrodes connected to the electrode connection regions, a plurality of wiring traces respectively connected to the plurality of post electrodes, and an insulation tape of thin film provided on the back side of the plurality of post electrodes and the wiring traces, supported by a support portion; simultaneously fixing and electrically connecting the plurality of post electrodes of the wiring-added post electrode component, which are coupled together by the support portion, to the electrode connection regions; charging resin into a space between the LSI region and the insulation tape, and then separating the support portion so as to expose the insulation tape acting as a protection film, wherein, on the first main face, the plurality of wiring traces connected to the plurality of post electrodes are used as the wiring for external connection and on the second main face, tip ends of through electrodes formed to pass through the semiconductor substrate are used as the wiring for external connection.