Patent ID: 6198328
Filing Date: 2001-03-06
Classification: H03K

Abstract:
A circuit configuration for producing complementary signals, comprising:an input terminal receiving an input signal;a first output terminal connected to said input terminal via a first path carrying the signal;a pass element connected in said first path between said input terminal and said first output terminal;a second output terminal connected to said input terminal via a second path connected in parallel with said first path;an inverter connected in said second path between said input terminal and said second output terminal for inverting the input signal, and in parallel to the pass element;a compensation device connected to said first and second output terminals and having a first output node and a second output node, said compensation device compensating for mutually different time delays in the signals on said first path and said second path;said compensation device including a plurality of further pass elements each having an n-channel MOS transistor and a p-channel MOS transistor connected in parallel with said n-channel MOS transistor.