Patent ID: 7524726
Filing Date: 2009-04-28
Classification: H01L

Abstract:
1. A method of fabricating a power semiconductor device, comprising: covering a surface of a semiconductor body with a mask body; removing portions of said mask body to define openings extending to said semiconductor body; removing a portion of said semiconductor body from bottoms of said openings in said mask body to define a plurality of gate trenches and a termination trench disposed around said gate trenches, said trenches being spaced from one another by mesas; removing said mask body; oxidizing the sidewalls of said gate trenches; depositing gate electrode material; etching back said gate electrode material to leave gate electrodes in said trenches; implanting channel dopants adjacent said gate trenches after said gate trenches are defined; forming a source mask; implanting source dopants through said source mask; activating said source dopants and said channel dopants to form a base region and source regions; depositing a low density oxide over said semiconductor body; depositing a contact mask; etching said low density oxide through said contact mask; depositing a metal layer atop said semiconductor body; forming a front metal mask atop said metal layer; and etching said metal layer to form at least a source contact, and a gate runner.