Patent ID: 8604617
Filing Date: 2013-12-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a transistor formed in a transistor region on a substrate; a multilayer interconnect structure formed over the transistor region; a first conductor pattern formed in the multilayer interconnect structure to overlap the transistor region, said first conductor pattern being coupled to ground or to a power supply; a first dielectric layer formed over the multilayer interconnect structure; a signal line formed over the first dielectric layer in a region in which it overlaps the first conductor pattern in plan view, the signal line being part of a transmission line; and two second conductor patterns formed in a same conductor layer as the signal line and, in a plan view, extending parallel to the signal line with the signal line between them, wherein the second conductor patterns are electrically coupled to the first conductor pattern, wherein a distance from the signal line to the second conductor patterns is greater than a height from the first conductor pattern to the signal line.