Patent ID: 6519177
Filing Date: 2003-02-11
Classification: G11C

Abstract:
A random access memory circuit in which an initialization circuit initializes the memory cells of the random access memory to a predetermined value, the random access memory initialization circuit comprising the following:a first bit line corresponding to a column of memory cells; a second bit line physically isolated from the first bit line that also corresponds to the column of memory cells; the column of memory cells including a plurality of memory cells each having a write terminal for writing a binary value to the corresponding memory cell, the write terminals of a first group of one or more of the plurality of memory cells being physically connected to the first bit line, the write terminals of a second group of one or more of the plurality of memory cells being physically connected to the second bit line; and an initialization circuit having an initialization input, the initialization circuit coupled directly or indirectly to the first bit line and the second bit line such that when the initialization input carries a signal state indicative of an initialization, the initialization circuit causes the first bit line and second bit line to carry predetermined binary opposite values, wherein during initialization, each of the first group of memory cells is initialized to a first binary value while each of the second group of memory cells is initialized to a second binary value that is opposite the first binary value.