Patent ID: 6339821
Filing Date: 2002-01-15
Classification: G06F

Abstract:
A data processor comprising:a decoding portion receiving an instruction of a program in order, said instruction including a plurality of operand fields and an operation code, extracting at least one operand field from a predetermined number of bits of said instruction as a first operand field, and decoding the operation code using remaining number of bits of said instruction, wherein the predetermined number of bits being variable and depending upon said operation code; an operand-field storage portion including a first operand-field storage portion storing said first operand fields received from said decoding portion, and a second operand-field storage portion storing part of said first operand fields as a second operand field based on said first operand field; and a data processing portion with a plurality of registers, receiving said first operand fields and said second operand field from said operand-field storage portion and processing data in registers designated by said first operand fields and said second operand field out of said plurality of registers, wherein the predetermined number of bits being variable and depending upon said operation code.