Patent ID: 6882201
Filing Date: 2005-04-19
Classification: H03K

Abstract:
1. A triple redundant latch for reducing soft errors comprising: a) an input driver, the input driver having an input and an output; b) a first transfer gate, the first transfer gate having an input, a first control input, a second control input and an output; c) a second transfer gate, the second transfer gate having an input, a first control input, a second control input, and an output; d) a first latch, the first latch having an input/output; e) a second latch, the second latch having an input/output; f) a third latch, the third latch having an input/output; g) a tristatable input inverter, the tristatable input inverter having a first input, a second input, and an output; h) an output driver, the output driver having an input and an output; i) wherein the input of the input driver is the input of the triple redundant latch; j) wherein the output of the input driver is connected to the input of the first transfer gate and to the input of the second transfer gate; k) wherein a first control input of the triple redundant latch is connected to the first control input of the first latch and to the first control input of the second latch; l) wherein a second control input of the triple redundant latch is connected to the second control input of the first latch and to the second control input of the second latch; m) wherein the output of the first transfer gate is connected to the input/output of the first latch and to the first input of the tristatable inverter; n) wherein the output of the second transfer gate is connected to the input/output of the second latch and to the second input of the tristatable inverter; o) wherein the output of the tristatable inverter is connected to the input/output of the third latch and to the input of the output driver; p) wherein the output of the output driver is the output of the triple redundant latch.