Patent ID: 8358653
Filing Date: 2013-01-22
Classification: H04L

Abstract:
1. A method of generating a packet processor, comprising: inputting a first specification describing the packet processor, the first specification describing a plurality of actions for processing a plurality of packets; generating a parsing tree from the plurality of actions of the first specification, the parsing tree having a plurality of levels and for each level specifying at least one concurrent set of a plurality of elementary operations and a respective bound on the plurality of elementary operations in the at least one concurrent set; and generating a second specification describing a programmable compute pipeline including a plurality of stages for implementing the plurality of actions, each stage corresponding to one of the plurality of levels of the parsing tree and including a plurality of elementary components with a number of the plurality of elementary components equaling at least the respective bound for the level, and the plurality of elementary components in the stage, when implemented, being programmable to concurrently perform each combination of a plurality of combinations of the plurality of elementary operations, the plurality of elementary operations in each concurrent set for the level included within one of the plurality of combinations.