Patent ID: 8969923
Filing Date: 2015-03-03
Classification: G11C,H01L,Y10S

Abstract:
1. A three-dimensional memory array comprising: a memory array layer including an array and a plurality of memory lines wherein portions of the memory lines extend from the array substantially parallel to each other, wherein a first subset of the memory lines extend from a first side of the array, wherein a second subset of the memory lines extend from a second side of the array, wherein within the first subset of memory lines a first plurality of memory lines terminate proximate an edge of the array, wherein within the first subset of memory lines a second plurality of memory lines extend beyond the edge of the array into a contact region, wherein the contact region includes a plurality of contacts adapted to couple the second plurality of memory lines to support circuitry, wherein the contacts are disposed in two or more rows, the contact rows disposed substantially non-parallel to the memory lines, and wherein adjacent memory lines couple to contacts in different rows.