Patent ID: 6618300
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of banks which are arranged on a semiconductor substrate; a plurality of plates; a plurality of memory array groups which are arranged on the plates; redundant memory cell array groups which replace a memory cell array including a defective memory cell and which are arranged at every plate; and subword selection circuits which switch subword selection lines at every plate; wherein each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundant subword selection line of the redundant memory cell array arranged on an adjacent plate; and wherein the subword selection line is selected by the use of a subword driver, and predetermined redundant subword lines of the memory cell array and the redundant memory cell array are selected after an arbitrary main word line is selected by a row decoder during selecting a word line.