Patent ID: 7583706
Filing Date: 2009-09-01
Classification: G06F

Abstract:
1. A cross bar apparatus that is configured to set frequency of an internal clock thereof at ½ of frequency of an external clock used for transferring packets mutually between a plurality of modules and to configure an internal bus width thereof to be two (2) times as wide as an external bus width, and that reads received packets after storing and classifying the packets by destination, the cross bar apparatus comprising: a packet receiving unit receiving packets transferred word by word synchronizing with the external clock as well as dividing a plurality of words of the packets including headers into those at even-numbered reception timing and those at odd-numbered reception timing of the external clock, and outputting the words and the headers in parallel synchronizing with the internal clock; an even-numbered latch unit latching the words of the packets at even-numbered reception timing outputted from the packet receiving unit; an odd-numbered latch unit latching the words of the packets at odd-numbered reception timing outputted from the packet receiving unit; even-numbered queues respectively for each destination, each even-numbered queue including a plurality of stages of multi-stage packet storage sectors to be written into with, packet by packet, the words of the packet at even-numbered reception timing outputted from the even-numbered latch unit; odd-numbered queues respectively for each destination, each odd-numbered queue including a plurality of stages of multi-stage packet storage sectors to be written into with, packet by packet, the words of the packet at odd-numbered reception timing outputted from the odd-numbered latch unit; a bypass unit bypassing the even-latch unit; a swap circuit unit swapping outputs of the even-numbered latch unit and the bypass unit to the odd-numbered queue unit as well as swapping an output of the odd-numbered latch unit to the even-numbered queue unit; a write control unit, when a plurality of packets are received sequentially, writing words of the packets such that headers of the received packets are respectively arranged alternately in each of the packet storage sectors of the even-numbered queue and the odd-numbered queue between these queues; and a read control unit reading in parallel the words of the packets by two (2) words at each time from the even-numbered queue and the odd-numbered queue.