Patent ID: 7890735
Filing Date: 2011-02-15
Classification: G06F

Abstract:
1. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising: first and second decode pipelines; first and second execute pipelines; coupling circuitry operable in a first mode to couple first and second threads from said first and second decode pipelines to said first and second execute pipelines respectively, and said coupling circuitry operable in a second mode to couple different instructions from the first thread to both said first and second execute pipelines for execution, at a same time, of a first instruction in the different instructions by said first execute pipeline and of a second instruction in the different instructions by said second execute pipeline; and issue circuitry respectively coupled at least to said first and second decode pipelines and to said first and second execute pipelines, wherein said first and second execute pipelines are for executing instructions of threads; and control circuitry having a storage for thread priorities and enabled thread identifications, the control circuitry for selecting from among a plurality of enabled threads at least a first enabled thread having a first respective priority and a second enabled thread having a second respective priority, wherein the selected enabled thread is selected in response to having a respective priority higher than a priority of another thread in the plurality of enabled threads or than of a thread in one of the first or second execute pipelines, and for launching in the first mode the first selected thread into the first decode pipeline and the second selected thread into the second decode pipeline such that the first selected thread is executed by the first execute pipeline at a same time the second selected thread is executed by the second execute pipeline.