Patent ID: 6339029
Filing Date: 2002-01-15
Classification: H01L

Abstract:
A method to form copper interconnects in the manufacture of an integrated circuit device comprising:providing a substrate layer encompassing all underlying layers, devices, junctions, and other features; depositing a first dielectric layer overlying said substrate layer; etching a via through said first dielectric layer; depositing a barrier layer overlying said first dielectric layer and within said via; depositing a copper layer wherein said copper layer overlies said barrier layer and fills said via; annealing said copper layer; depositing a dielectric barrier layer overlying said copper layer after said step of depositing said copper layer; thereafter etching through said dielectric barrier layer to said underlying copper layer to form a dielectric barrier layer hard mask overlying said copper layer; patterning said copper layer and said barrier layer where exposed by said dielectric barrier layer hard mask; forming a passivation layer composed of a copper-germanium alloy on the exposed surfaces of said copper layer wherein said passivation layer forms on sidewalls of said copper layer but does not form on top surface of said copper layer; and depositing a second intermetal dielectric layer overlying said dielectric barrier layer hard mask and said first dielectric layer to complete said copper interconnects in the manufacture of said integrated circuit device.