Patent ID: 6184084
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of forming a flash memory cell, comprising:forming a tunnel oxide on a substrate;forming a first polysilicon layer over the tunnel oxide;forming an insulating layer over the first polysilicon layer;forming a second polysilicon layer over the insulating layer by depositing a second polysilicon layer having a first thickness, the first thickness being at least about 2,000 .ANG., implanting a polishing rate improver into the second polysilicon layer and then using chemical mechanical polishing to form a second polysilicon layer having a second thickness, wherein the second thickness is at least about 25% less than the first thickness;forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF.sub.6 and SiH.sub.4 ;etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; andforming a source region and a drain region in the substrate, thereby forming at least one memory cell.