Patent ID: 6411152
Filing Date: 2002-06-25
Classification: G06F,H03K

Abstract:
A clock buffer circuit comprising:a precharge circuit configured to precharge a first node and a second node; a first transistor having a first terminal coupled to the first node, a second terminal, and a first control terminal coupled to receive a condition signal; a second transistor having a third terminal coupled to the second node, a fourth terminal coupled to the second terminal, and a second control terminal coupled to the first node; and a third transistor having a fifth terminal coupled to the second terminal and the fourth terminal, a sixth terminal, and a third control terminal coupled to receive a clock signal; wherein the first transistor is activated responsive to the condition signal, and wherein the second transistor is prevented from discharging the second node responsive to the first transistor being activated, the second node representing an output clock signal from the clock buffer circuit.