Patent ID: 6448134
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method for fabricating a semiconductor device including a plurality of stacked capacitors on a semiconductor substrate having a logic circuit region and a memory cell region, comprising the steps of:(a) forming gate electrodes, source electrodes, and drain electrodes on a semiconductor substrate, and forming a first interlayer insulating film in a planarized fashion over an upper surface of a structure resulting from the formation of the electrodes; (b) forming, on the first interlayer insulating film at the memory cell region, bit lines connected to the source electrodes while forming, on the first interlayer insulating film at the logic circuit region, first interconnection lines connected to the source, drain, and gate electrodes, and forming a second interlayer insulating film in a planarized fashion over an upper surface of a structure resulting from the formation of the bit lines and the first interconnection lines; (c) forming contact holes at the first interconnection lines in the logic circuit region, forming a conductive material in a planarized fashion over an upper surface of a structure resulting from the formation of the contact holes, and etching back the conductive material, thereby forming contact plugs respectively connected to the first interconnection lines; (d) forming an etch barrier film over an upper surface of a structure resulting from the formation of the contact plugs, forming contact holes exposing the drain electrodes, and forming a conductive material, adapted to form charge storage electrodes, over an upper surface of a structure resulting from the formation of the contact holes exposing the drain electrodes; (e) patterning the conductive material adapted to form the charge storage electrodes using a charge storage electrode mask to form the charge storage electrodes and dummy charge storage electrodes, forming a capacitor dielectric film over an upper surface of a structure resulting from formation of the charge storage electrodes and the dummy charge storage electrodes, and forming, over the capacitor dielectric film, a conductive material adapted to form plate electrodes; (f) patterning the conductive material adapted to form the plate electrodes using a plate electrode mask, thereby forming plate electrodes and dummy plate electrodes, and forming a third interlayer insulating film in a planarized fashion over an upper surface of a structure resulting from the formation of the plate electrodes and dummy plate electrodes; and (g) forming second interconnection lines connected to the contact plugs formed at the first interconnection lines, wherein the dummy plate electrodes and the dummy charge storage electrodes each have a height which is the same as that of the stacked capacitors, and are formed at the logic circuit region when the stacked capacitors are formed at the memory cell region.