Patent ID: 7937700
Filing Date: 2011-05-03
Classification: G06F

Abstract:
1. A processor comprising: a plurality of registers configured to store processor state; and an execution core coupled to the plurality of registers, wherein the execution core is configured to execute instructions defined in an instruction set architecture implemented by the processor, and wherein the execution core is configured, during a switch from processor execution of a guest to processor execution of a virtual machine manager (VMM) that controls the guest, to automatically save a portion of the processor state to a memory, the portion of the processor state corresponding to the guest, wherein the execution core is configured to initiate the switch in response to detecting an intercept event programmed for the guest, and wherein the execution core is configured to execute instructions in the guest during processor execution of the guest, and wherein the execution core is configured to execute instructions forming the VMM during processor execution of the VMM, and wherein the execution core is configured to automatically save the portion of the processor state prior to executing an initial instruction of the VMM in response to the switch, and wherein the execution core is configured to save an additional portion of the processor state subsequent to the switch in response to executing one or more additional instructions after the switch.