Patent ID: 6489202
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A fabricating method of an embedded channel write/erase flash memory on an N-substrate, the N-substrate comprising at least a flash memory cell array region, a first complementary metal oxide semiconductor (CMOS) region, and a second CMOS region, which are isolated from one another by isolation layers, the method comprising:forming a deep P-well in said N-substrate of each of said flash memory cell array region, said first CMOS region, and said second CMOS region; forming a N-well in each of said deep P-wells; forming a P-well in said N-substrate of each of said first CMOS region and said second CMOS region; forming a shallow P-type region on a portion of the surface of said N-well in said flash memory cell array region; growing a tunnel oxide layer on said N-substrate of said flash memory cell array region, said first CMOS region, and said second CMOS region, and depositing a first polysilicon layer on said tunnel oxide layer; removing portions of said tunnel oxide layer and said first polysilicon layer, which are positioned in said first CMOS region and in said second CMOS region; forming an oxide-nitride-oxide (ONO) film on said first polysilicon layer, which is positioned in said flash memory cell array region; growing a thick oxide layer on said N-well and said P-well of said first CMOS region; growing a thin oxide layer on said N-well and said P-well of said second CMOS region; depositing a second polysilicon layer on said ONO film, said thick oxide layer, and said thin oxide layer; removing portions of said second polysilicon layer, said ONO film, said first polysilicon layer, and said tunnel oxide layer within said flash memory cell region, so as to form a rectangular stacked structure comprising said tunnel oxide layer, said first polysilicon layer, said ONO film, and said second polysilicon layer; performing an oxidation process to form a smiling effect oxide layer between said rectangular stacked structure and the surface of said N-well in said flash memory cell array region; forming a deep P-type region in said N-well adjacent to one sidewall of said rectangular stacked structure; forming two N-type regions in said N-well adjacent to both sidewalls of said rectangular stacked structure; removing portions of said second polysilicon layer and said thick oxide layer, which are positioned in said first CMOS region, to form a first stacked structure on each of said N-well and said P-well of said first CMOS region, each of said first stacked structures having said second polysilicon layer and said thick oxide layer; removing portions of said second polysilicon layer and said thin oxide layer, which are positioned in said second CMOS region, to form a second stacked structure on each of said N-well and said P-well of said second CMOS region, each of said second stacked structures having said second polysilicon layer and said thin oxide layer; forming two first lightly doped N-type regions in said P-well adjacent to both sidewalls of said second stacked structure on said P-well of said second CMOS region; forming two first lightly doped P-type regions in said N-well adjacent to both sidewalls of said second stacked structure on said N-well of said second CMOS region; forming two second lightly doped N-type regions in said P-well adjacent to both sidewalls of slid first stacked structure on said P-well of said first CMOS region; forming two second lightly doped P-type regions in said N-well adjacent to both sidewalls of said first stacked structure on said N-well of said first CMOS region; depositing a first insulating layer on said flash memory cell array region, said first CMOS region, and said second CMOS region; etching the first insulating layer so as to form a pair of spacers on both sidewalls of each of said rectangular stacked structure, said first stacked structures, and said second stacked structures; forming two heavily doped N-type regions in said P-well adjacent to both sidewalls of each of said first stacked structure on the P-well of the first CMOS region and said second stacked structure on the P-well of the second CMOS region; forming two heavily doped P-type regions in said N-well adjacent to both sidewalls of each of said first stacked structure on said N-well of said first CMOS region and said second stacked structure on said N-well of said second CMOS region; forming a second insulating layer on said flash memory cell array region, said first CMOS region, and said second CMOS region; forming a plurality of contact holes beside one sidewall of said rectangular stacked structure and beside both sidewalls of each of said first stacked structures and said second stacked structures; and depositing a first metal layer on said second insulating layer and in each of said contact holes, and locally etching said first metal layer to let each of said contact holes have a first metal interconnect.