Patent ID: 7184316
Filing Date: 2007-02-27
Classification: G11C,H01L

Abstract:
1. A method of operating an array of nonvolatile memory cells in which memory cells are arranged in a matrix, each of the memory cells having a semiconductor substrate, a gate formed on the semiconductor substrate, a source and drain formed in the semiconductor substrate at both sides of the gate, and a charge storage region between the gate and the semiconductor substrate, the method comprising: selecting a cell from the array of nonvolatile memory cells; applying a positive voltage to a gate of the selected cell and to gates of first memory cells that share a word line with the selected cell; applying a first voltage to a drain of the selected cell and to drains of second memory cells that share at least a drain line with the selected cell; and applying a second voltage to a source of the selected cell and to sources of third memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program, wherein a third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell, wherein the source includes: a first source region partially overlapped with the gate; and a second source region adjacent to the first source region and having a relatively higher concentration.