Patent ID: 7499337
Filing Date: 2009-03-03
Classification: G11C

Abstract:
1. A method of erasing data in a non-volatile semiconductor memory device, for setting a threshold voltage of a plurality of memory cell transistors arranged in an integrated manner in matrix to a value within a range from at least a first voltage to at most a second voltage, comprising the steps of: performing an erase operation so that the threshold voltage of said memory cell transistors is set to at most said second voltage; and performing a verify write operation, in which verify is performed in such a manner that said first voltage is applied to a control gate of a memory cell transistor corresponding to a selected memory cell row, to carry out threshold voltage determination as to whether the memory cell transistor is to be turned on or remains off, and write is performed based on a result of verify; said step of performing a verify write operation including the steps of performing first verify write, in which verify is performed in such a manner that said first voltage is applied to the control gate of the memory cell transistor corresponding to the selected memory cell row and a third voltage lower than a normal off voltage is applied to a control gate of a memory cell transistor corresponding to a non-selected memory cell row, and write to the memory cell transistor corresponding to the selected memory cell row is repeated based on a result of verify, and performing second verify write, in which verify is performed in such a manner that said first voltage is applied to the control gate of the memory cell transistor corresponding to the selected memory cell row and the normal off voltage is applied to the control gate of the memory cell transistor corresponding to the non-selected memory cell row, and write to the selected memory cell row is repeated based on a result of verify, and said step of performing second verify write including a sub step of performing, once for each row, verify and write based on a result of verify, sequentially from the memory cell transistor corresponding to the selected memory cell row corresponding to a first address to the memory cell transistor corresponding to the selected memory cell row corresponding to a last address, and said sub step being repeated.