Patent ID: 6477620
Filing Date: 2002-11-05
Classification: G06F

Abstract:
For use in a hierarchical memory including a main memory coupled to multiple cache memories, a memory by-pass system, comprising:a first request processing circuit coupled to receive a request from the main memory, said request being initiated by any of the cache memories, said first request processing circuit to provide said request to an addressed one of the cache memories to cause said addressed one of the cache memories to return requested data signals to the main memory; and a first response generation circuit coupled to said first request processing circuit, to at least one associated one of the cache memories and to said addressed one of the cache memories, said first response generation circuit to receive from said addressed one of the cache memories said requested data signals, said first response generation circuit to generate a response including said requested data signals and that is to be provided directly to a cache memory that initiated said request if said cache memory that initiated said request is said at least one associated one of the cache memories.