Patent ID: 7272068
Filing Date: 2007-09-18
Classification: G11C

Abstract:
1. A semiconductor device comprising: a logic circuit; a memory cell array including arrayed SRAM cells; a peripheral circuit for accessing the memory cell array; a first power supply line of which voltage is a first voltage level; a second power supply line of which voltage is a second voltage level; a first MOS transistor; and a second MOS transistor; wherein the first voltage level is higher than the second voltage level; wherein a gate-insulating film thickness of the first MOS transistor is thicker than that of the second MOS transistor; wherein the first and second power lines supply operating voltage differences to the logic circuit, the memory cell array and the peripheral circuit; wherein one of the first power supply line and the second power supply line connects to the logic circuit through a source-drain path of the first MOS transistor; wherein one of the first power supply line and the second power supply line connects to the peripheral circuit through a source-drain path of the second MOS transistor; and wherein the first and second MOS transistors are nonconductive in a standby state when the logic circuit does not operate.