Patent ID: 8775885
Filing Date: 2014-07-08
Classification: G01R,G06F,H04J,H04L

Abstract:
1. An IEEE1588 protocol negative testing method, characterized in that, the method comprises the following steps: (1) connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; (2) taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; (3) obtaining the timing offset or path delay of the slave clock DUT before disturbance through a real-time closed-loop feedback mechanism by the IEEE1588 tester; (4) assembling an abnormal message in a frame by the IEEE1588 tester, and sending it to the slave clock DUT; (5) obtaining the timing offset or path delay of the slave clock DUT after disturbance of the abnormal message through the real-time closed-loop feedback mechanism by the IEEE1588 tester; (6) calculating the timing offset increment or path delay increment after disturbance of the abnormal message; (7) according to the increment calculated in Step (6), determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, it indicates that the logic for the slave clock DUT to process the abnormal message is correct, and the check item in this time passes; otherwise it indicates that the logic for the slave clock DUT to process the abnormal message is not correct, and the check item in this time fails.