Patent ID: 6580131
Filing Date: 2003-06-17
Classification: H01L

Abstract:
An LDMOS device, comprising:a Pâˆ’substrate; on said substrate a first epitaxial layer of Nâˆ’silicon having a first resistivity; on said first epitaxial layer of Nâˆ’silicon a second epitaxial layer of Nâˆ’silicon having an upper surface and a second resistivity that is lower than said first resistivity, whereby said first and second epitaxial layers have a mean resistivity that is approximnately equal to that of an LDMOS device that has only one Nâˆ’epitaxial layer; a Pâˆ’base region in the second epitaxial layer; and a layer of gate oxide covered by a polysilicon gate, an N+source in the base region and an N+drain in the second Nâˆ’epitaxial layer.