Patent ID: 6461951
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A method of forming an electrical connection to a semiconductor device, comprising:forming a gate on a substrate, the gate having a top surface and sidewalls; forming an oxide layer on the sidewalls of the gate; depositing a layer of spacer material over the substrate, the oxide layer, and the gate; etching the layer of spacer material and the oxide layer to form sidewall spacers on the oxide layer, wherein the etching is performed such that: no portion of the oxide layer and no portion of the sidewall spacers extend above the top surface of the gate; portions of the gate sidewalls are free of the oxide layer and the spacer material; and other portions of the gate sidewalls are covered by the oxide layer and the sidewall spacers; forming active regions in the substrate; and forming a silicide on the active regions of the substrate and on the semiconductor device, with silicide forming on the top surface and the portions of the gate sidewalls that are free of the oxide layer and the spacer material, wherein the silicide formed on the gate sidewalls overhangs the oxide layer and the sidewall spacers.