Patent ID: 6967951
Filing Date: 2005-11-22
Classification: H04J,H04L

Abstract:
1. A system for reordering data packets in a packet switch network, wherein a plurality of source processors transmit the data packets to a destination processor via multiple communication fabrics, and wherein the source processors and the destination processor are synchronized, the system comprising: time stamp logic at each source processor that operates to include a time stamp parameter with each of the data packets transmitted from the source processors; a plurality of memory queues located at the destination processor; an Enqueue processor coupled to the plurality of memory queues and located at the destination processor, wherein the Enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the data packets received at the destination processor in a selected memory queue; and a Dequeue processor coupled to the plurality of memory queues and operable to access the plurality of memory queues to determine a selected memory pointer associated with a selected time stamp parameter, and wherein the Dequeue processor operates to process the selected memory pointer to access a selected data packet for output in a reordered packet stream.