Patent ID: 9105313
Filing Date: 2015-08-11
Classification: G09B,G11C

Abstract:
1. A memory device comprising: a memory cell, a first data signal line, a second data signal line, a first selection signal line, a second selection signal line, and a third data signal line, the memory cell comprising: a second transistor comprising a second source, a second drain, and a second gate; a third transistor comprising a third source, a third drain, and a third gate; and wherein one of the first source and the first drain is electrically connected to the first data signal line, wherein the first gate is electrically connected to the first selection signal line, wherein the first transistor has an off-state current per micrometer of channel width of lower than or equal to 10 aA, wherein the second gate is electrically connected to the other of the first source and the first drain, wherein one of the third source and the third drain is electrically connected to the second data signal line, wherein the other of the third source and the third drain is electrically connected to the other of the second source and the second drain, wherein the third gate is electrically connected to the other of the first source and the first drain, wherein one of the fourth source and the fourth drain is electrically connected to the third data signal line, wherein the other of the fourth source and the fourth drain is electrically connected to the other of the second source and the second drain, and the other of the third source and the third drain, and wherein the fourth gate is electrically connected to the second selection signal line.