Patent ID: 6584594
Filing Date: 2003-06-24
Classification: G06F,G11B,H03M

Abstract:
An error correction circuit for a memory device, comprising:(a) a data word byte counter; (b) first and second data encoders capable of receiving first and second pre-read data bytes, respectively; (c) a syndrome accumulator, coupled to the data word byte counter and the first and second data encoders, capable of generating a syndrome comprising first and second pluralities of syndrome bits; (d) a data word byte address generator, coupled to the syndrome generator, capable of generating a plurality of data word byte address bits; (e) a comparator, coupled to the syndrome accumulator and the data word byte address generator, capable of generating an error correction enable signal in response to comparing the first plurality of the syndrome bits with the data word byte address bits; (f) a decoder, coupled to the syndrome accumulator, capable of decoding the second plurality of the syndrome bits to generate a plurality of decoded data input bits; and (g) a correction enable buffer, coupled to the comparator and the decoder, capable of generating a plurality of correction bits in response to receiving the decoded data input bits and the error correction enable signal.