Patent ID: 6594681
Filing Date: 2003-07-15
Classification: G06F

Abstract:
A quotient digit selection circuit that determines a quotient digit in binary division and square root operations based upon a redundant partial remainder input, wherein the redundant partial remainder input includes first, second, third, and fourth sum bits and first, second, third, and fourth carry bits, and wherein the quotient digit chosen is output by asserting one of a minus output corresponding to a negative one quotient digit, a zero output corresponding to a zero quotient digit, and a plus output corresponding to a positive one quotient digit, the quotient digit selection circuit comprising:a three-bit carry-propagate adder that takes the first, second, and third sum bits and the first, second, and third carry bits as inputs and produces first, second, and third estimated partial remainder bits as outputs; a three-bit zero detector that takes the first, second, and third estimated partial remainder bits as inputs, and that produces an all-zero signal that is asserted if and only if the first, second, and third estimated partial remainder bits are all zeros; a three-bit one detector that takes the first, second, and third estimated partial remainder bits as inputs, and produces an all-one signal that is asserted if and only if the first, second, and third estimated partial remainder bits are all ones; a NOR gate that takes the fourth sum bit and the fourth carry bit as inputs and that produces a fourth bit zero signal; and a zero circuit that takes the all-one signal, the fourth bit zero signal, and the all-zero signal as inputs and that produces the zero output, such that the zero output is asserted if and only if either the all-one signal is asserted and the fourth bit zero signal is deasserted or the fourth bit zero signal and the all-zero signal are both asserted.