Patent ID: 7360041
Filing Date: 2008-04-15
Classification: G06F

Abstract:
1. In a data processing system having a processors with a processor core, store queue (STQ) mechanism, read claim (RC) mechanism, and associated processor cache, a method for reducing latency of processing store conditional (STCX) operations, said method comprising: responsive to allocation of a STCX operation to an entry of the store queue, tagging the entry as a higher priority entry relative to a prior entry allocated a regular store operation; and selecting the higher priority entry for dispatch ahead of said prior entry during dispatch selection process, wherein the STCX operation is forwarded to said processor cache ahead of the prior entry, wherein a latency of processing STCX operations is substantially reduced, wherein said selecting step further comprises: first determining that both said higher priority entry and said prior entry are valid for dispatch; evaluating when a dispatch of the higher priority entry ahead of the prior entry does not violate a predefined architectural rule for dispatching entries from the store queue; and dispatching said higher priority entry ahead of said prior entry when a selection of said higher priority entry for dispatch ahead of said prior entry does not violate the predefined architectural rule for dispatching entries from the store queue.