Patent ID: 8927387
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: providing a wafer comprising a pad oxide layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein said first semiconductor layer has a thickness of 10 nm or less; etching a shallow trench isolation (STI) region into said wafer, extending partially into said second semiconductor layer; forming first spacers on sidewalls of said STI region; etching an area directly below and between said first spacers, exposing an underside of said first spacers; forming second spacers covering all exposed portions of said first spacers, wherein said pad oxide layer is removed; and forming a gate structure over said first semiconductor layer; wherein said forming said second spacers comprises: depositing a hydrogen-rich silicon nitride insulating material over said semiconductor device, including spaces below and between said first spacers, and performing an anneal to densify the hydrogen-rich silicon nitride insulating material; depositing an oxide material over said semiconductor device; planarizing said semiconductor device, stopping on said hydrogen-rich silicon nitride insulating material; etching said hydrogen-rich silicon nitride insulating material at and above said pad oxide layer; and etching to remove said pad oxide layer.