Patent ID: 7134059
Filing Date: 2006-11-07
Classification: G11C

Abstract:
1. A pad configuration, comprising a plurality of pads, including first, second, and third common pads; a plurality of embedded memory devices on a common integrated circuit, each embedded memory device having at least one first, second, and third signal lines of first, second, and third similar purposes with at least one first, second, and third signal lines of the other embedded memory devices, respectively, wherein the at least one first signal lines of each memory device are grouped into a first signal line group, the at least one second signal lines of each memory device are grouped into a second signal line group, and the at least one third signal lines of each memory device are grouped into a third signal line group; and an input/output device, including first, second, and third selective coupling devices, wherein in response to a first signal line selection signal, the first selective coupling device selects one first signal line of the first signal line group to form a first conductive path between the first common pad and a first memory device of the plurality of embedded memory devices, wherein, in response to a second signal line selection signal that is generated independently of the first signal line selection signal, the second selective coupling device selects one second signal line of the second signal line group to form a second conductive path between the second common pad and a second memory device of the plurality of embedded memory devices, and wherein, in response to a third signal line selection signal that is generated independently, of the first and second signal line selection signals, the third selective coupling device selects one third signal line of the third signal line group to form a third conductive path between the third common pad and a third memory device of the plurality of embedded memory devices.