Patent ID: 6489825
Filing Date: 2002-12-03
Classification: H03K

Abstract:
A flip flop comprising:a first device having a first input that receives a clock signal, a second input that receives a first data signal, and a first output that outputs a first device signal, the clock signal alternating between a first logic state and a second logic state, the first device outputting the first device signal with a logic state in response to the first data signal when the clock signal is in the first logic state, and holding the logic state of the first device signal to a state that is present when the clock signal transitions from the first logic state to the second logic state when the clock signal is in the second logic state; a second device having a third input that receives the clock signal, a fourth input that receives a second data signal, and a second output that outputs a second device signal, the second device outputting the second device signal with a logic state in response to the second data signal when the clock signal is in the second logic state, and holding the logic state of the second device signal to a state that is present when the clock signal transitions from the second logic state to the first logic state when the clock signal is in the first logic state; and a multiplexer having a fifth input connected to the first output, a sixth input connected to the second output, a seventh input connected to the clock signal, and a flop output that outputs a flop output signal, the multiplexer setting a logic state of the flop output signal in response to the logic state of the first device signal when the clock signal is in the second logic state, and setting the logic state of the flop output signal in response to the logic state of the second device signal when the clock signal is in the first logic state, the multiplexer including: a first transmission gate connected to the first output, the first transmission gate passing the first device signal when the clock signal is in the second logic state, and blocking the first device signal when the clock signal is in the first logic state; and a second transmission gate connected to the second output, the second transmission gate passing the second device signal when the clock signal is in the first logic state, and blocking the second device signal when the clock signal is in the second logic state.