Patent ID: 6886123
Filing Date: 2005-04-26
Classification: G01R

Abstract:
1. An arithmetic circuit with built-in self testing of input-to-output delay for use with a Residue Number System (RNS), said arithmetic circuit comprising: an arithmetic core for performing an RNS arithmetic operation, the arithmetic core having an output and at least two inputs; input-to-output delay test circuitry coupled to the arithmetic core, the input-to-output delay test circuitry selectively feeding the output of the arithmetic core back to at least one of the inputs without latching so as to induce natural oscillation at the output of the arithmetic core during testing of the input-to-output delay; and input-to-output delay logic circuitry coupled to the output of the arithmetic core, the input-to-output delay logic circuitry measuring an oscillation frequency of the output of the arithmetic core during testing of the input-to-output delay, making a determination of whether the oscillation frequency that is measured is at least equal to a minimum threshold value, and producing a pass signal or a fail signal based on the determination that is made in order to indicate whether or not the input-to-output delay of the arithmetic core is within specification.