Patent ID: 7975161
Filing Date: 2011-07-05
Classification: G06F,Y02D

Abstract:
1. A method comprising: receiving a first clock signal having at least a first clock frequency in a processor core; generating and sampling signals on a bus coupled to a bus interface, the bus interface coupled to the processor core, using at least a second clock signal having at least a second clock frequency, the first clock frequency constrained to be no less than a multiple of a lowest one of the second clock frequency; dividing the second clock frequency, so as to maintain a substantially fixed ratio between the first and second clock frequencies regardless of changes in the frequency of the first clock signal or at least the second clock signal; generating and sampling signals on the bus with an interface controller including a second bus interface, wherein the second bus interface receives a plurality of third clock signals having third clock frequencies generated from an intermediate clock signal generated from a system clock signal; generating the at least second clock signal in a first frequency divider and changing a frequency division factor of said first frequency divider; and changing the frequency division factor in response to a change in the first clock frequency.