Patent ID: 8796757
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a silicon layer of a columnar shape on a silicon substrate; a plurality of vertical-transistor-formed layers and a plurality of interlayer insulators alternately laminated on the silicon substrate so as to surround the silicon layer; each of the vertical-transistor-formed layers including, to surround the sidewall surface of the silicon layer in this order: a) a tunnel insulating film, b) a charge storage layer, c) a block insulating film, and d) a gate layer interposed between adjacent ones of the plurality of interlayer insulators; and a plurality of separated insulating films formed between a first insulating film and a second insulating film, the first insulating film and the second insulating film being respectively extended from the tunnel insulating film and the blocking insulating film of an adjacent one of the vertical-transistor layers, to separate the plurality of charge storage layers from each other, the plurality of separated insulating films positioned in line with the plurality of charge storage layers, wherein the charge storage layer and the separated insulating films include silicon nitride, each of the plurality of separated insulating films has a region lower in nitrogen concentration than the charge storage layer, and the plurality of separated insulating films have regions lower in trap level than the charge storage layer.