Patent ID: 9196537
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A method for assembling a wafer level chip scale processed (WLCSP) wafer, the wafer having a front-side surface and a back-side surface, a plurality of device die having electrical contacts on the front-side surface, the method comprising: back-grinding, to a thickness, the back-side surface the wafer; applying a protective layer of a thickness onto the back-side surface of the wafer; mounting the WLCSP wafer onto a sawing foil onto the back-side surface having the protective layer; sawing the WLCSP wafer in saw lanes of the plurality of device die on the front-side surface, the sawing occurring with a blade of a first kerf and to a first depth of the back-ground wafer thickness; again sawing the WLCSP along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer; separating the plurality of device die into individual device die; wherein each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.