Patent ID: 6195731
Filing Date: 2001-02-27
Classification: G06F

Abstract:
A machine with non-uniform memory access, constituted by a plurality of modules (10, 20, 40, 60), each module comprising at least one processor (1, 21, 41, 61), a memory part (5, 25, 45, 65) and a unit (6, 26, 46, 66) having at least a first table (8) for managing local accesses to a memory part (5') local to the module (10) and a second table (9) for managing accesses to a memory part (25', 45', 65') remote from the module (10), by means of a system bus (7), characterized in that the machine comprises:a first counter (81) of hits in the local memory part (5') not requiring a transaction with a remote module;a second counter (82) of misses in the local memory part requiring at least one transaction with a remote module;a third counter (91) of hits in the remote memory part not requiring a transaction with a remote module;a fourth counter (92) of misses in the remote memory part requiring at least one transaction with a remote module.