Patent ID: 7576392
Filing Date: 2009-08-18
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor layer which includes a first semiconductor region of a first conductivity type, a base region of a second conductivity type formed above the first semiconductor region, and a plurality of second semiconductor regions of the first conductivity type formed on the base region; at least one gate electrode which is formed between the first semiconductor region and the second semiconductor regions and which is adjacent to the first semiconductor region and the second semiconductor regions, the gate electrode facing the base region via a gate insulating film; a gate wiring which is formed on the semiconductor layer directly above a first insulating film and which is made of metal, the gate wiring being electrically connected to the gate electrode; a plurality of main electrodes which are electrically connected to the plurality of second semiconductor regions, wherein the gate wiring is arranged between the main electrodes and the gate wiring is separated from the main electrodes by a second insulating film; and a connecting plate which is connected onto upper surfaces of the main electrodes, wherein the main electrodes are in contact with a contact region of the connecting plate, and, in an area under the contact region of the connecting plate, the highest portion of an uppermost surface of the gate wiring is not higher than the upper surfaces of the main electrodes, wherein the connecting plate is connected to a lead frame and the gate wiring is not directly connected to the connecting plate, wherein the first insulating film is formed substantially midway between neighboring gate electrodes on the base region of the second conductivity type.