Patent ID: 9116203
Filing Date: 2015-08-25
Classification: G01R,H01L

Abstract:
1. A test structure comprising: an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm); an interconnect structure connected to the array of microbumps; and an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure, wherein a width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.