Patent ID: 7897879
Filing Date: 2011-03-01
Classification: H01L,H05K,Y10T

Abstract:
1. A structure for providing electrical interconnection for integrated circuit chips, said structure comprising: an insulative substrate; at least one first conductive layer within said insulative substrate, said at least one first conductive layer comprising two sets of parallel conductors non-orthogonally crossing each other and defining non-orthogonal, rhomboid-shaped conductive patterns in said at least one first conductive layer; and at least one second conductive layer within said insulative substrate, said at least one second conductive layer being separate from said at least one first conductive layer and comprising two sets of parallel conductors non-orthogonally crossing each other and defining non-orthogonal, rhomboid-shaped conductive patterns in said at least one second conductive layer, said non-orthogonal, rhomboid-shaped conductive patterns of said at least one second conductive layer being displaced in plan view from said non-orthogonal, rhomboid-shaped conductive patterns of said at least one first conductive layer so that vertices of said non-orthogonal, rhomboid-shaped conductive patterns of said at least one first conductive layer are vertically misaligned from vertices of said non-orthogonal, rhomboid-shaped conductive patterns of said at least one second conductive layer.