Patent ID: 6275064
Filing Date: 2001-08-14
Classification: H03K

Abstract:
A field programmable gate array device comprising:(a) a plurality of variable grain blocks (VGBS) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);wherein the plurality of VGBs includes:(a.1) a first VGB having a top, right, bottom and left side, wherein first and second inputs are located at the top side;(a.2) a second VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;wherein the plurality of interconnect lines further includes a second portion comprising:(b.1) a first direct connect line connecting the first output of the second VGB directly to a respective input of the first VGB; and(b.2) a second direct connect line connecting the second output of the second VGB directly to respective input of the first VGB.