Patent ID: 6770973
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A semiconductor apparatus, comprising:a plurality of device elements formed on a surface of a semiconductor substrate, each device element having a diffusion region; a multi-layer wiring configuration electrically connecting at least two of the diffusion regions, the multi-layer wiring configuration containing a plurality of wiring layers, a first one of the plurality of wiring layers being divided into a first wiring region for providing wiring in a first direction and a second wiring region for providing wiring in a second direction; and predetermined wiring in the first one of the plurality of wiring layers is electrically connected to and disposed in parallel with wiring in a second one of the plurality of wiring layers; wherein the first direction is orthogonal to the second direction; and the second one of the plurality of wiring layers has a higher sheet resistance than the first one of the plurality of wiring layers.