Patent ID: 6141261
Filing Date: 2000-10-31
Classification: G11C

Abstract:
A memory comprising:a plurality of data storage words, each data storage word comprising a plurality of data storage cells and a plurality of reference storage cells, each data storage cell and each reference storage cell having at least 4 states;a plurality of reference lines, one such reference line corresponding to each reference storage cell, said corresponding reference storage cell being connected to that reference line, each reference storage cell comprising a gate for connecting that storage cell to said corresponding reference line, each reference cell assuming one of said states in response to a signal on said corresponding reference line and a write signal, said state being determined by said signal on said corresponding reference line;a plurality of data lines, one such data line corresponding to each data storage cell, said corresponding data storage cell being connected to that data line, each data storage cell comprising a gate for connecting that storage cell to said corresponding data line, each data cell assuming one of said states in response to a signal on said corresponding data line and a write signal, said state being determined by said signal on said corresponding data line;a plurality of reference encoding circuits, one such reference encoding circuit corresponding to each reference line and being connected to that reference line, each reference encoding circuit generating a reference signal on said corresponding reference line in response to said write signal; anda plurality of data encoding circuits, one such data encoding circuit corresponding to each data line and being connected to that data line, each data encoding circuit comprising a circuit for receiving a digital value having at least 4 states and for generating a data programming signal on said corresponding data line in response to said write signal.