Patent ID: 6524876
Filing Date: 2003-02-25
Classification: G02F,H01L,Y10S

Abstract:
A method for manufacturing a thin film transistor array panel for a liquid crystal display, comprising the steps of:depositing a conductive layer of a multi-layered structure on an insulating substrate; forming a gate wire including a gate line and a gate electrode connected to the gate line by patterning the conductive layer; forming a gate insulating layer covering the gate wire; forming a semiconductor layer on the gate insulating layer opposite to the gate electrode; forming a data wire including a data line intersecting the gate line, a source electrode connected to the data line and neighboring the gate electrode, and a drain electrode separated from the source electrode and opposite to the source electrode with respect to the gate electrode; forming a passivation layer to cover the data wire; and forming a pixel electrode connected to the drain electrode, wherein the conductive layer is selectively patterned by partially exposing a lower layer located in the middle of the multi-layered structure.