Patent ID: 7420260
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A power semiconductor device having a first region in which a transistor is formed, a third region in which a control element is formed, and a second region arranged horizontally between the first region and the third region to electrically separate the transistor from the control element, the device comprising: a substrate of the first conductive type; a semiconductor region of the second conductive type arranged on the substrate; a highly-doped buried layer of a second conductive type arranged in the first region and the third region between the substrate and the semiconductor regions, the highly-doped buried layer of the second conductive type extending by a predetermined distance from the first region in the second region; a highly-doped bottom layer of a first conductive type comprising a first highly-doped bottom layer of the first conductive type arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extending by a predetermined distance from the first region in the second region, and a second highly-doped bottom layer of the first conductive type separated by a predetermined distance from the highly-doped buried layer in the second region; an isolation region, comprising a first isolation region having a top surface and a bottom surface, the bottom surface arranged to contact an upper portion of the first highly-doped bottom layer of a first conductive type, and a second isolation region arranged to contact an upper portion of the second highly-doped bottom layer of the first conductive type, the isolation region formed in the semiconductor region of the second region; and a highly-doped region of a second conductive type having a top surface and a bottom surface, the bottom surface arranged to contact an upper portion of the highly-doped buried layer of the second conductive type between the first isolation region and the second isolation region, the highly-doped region of the second conductive type formed in the semiconductor region of the second region; wherein the first isolation region and the highly-doped region of a second conductive type each have an electrical contact terminal at their corresponding top surfaces, formed in the region of the top surfaces closest to the second insulation region.