Patent ID: 7999589
Filing Date: 2011-08-16
Classification: H03K,H03L

Abstract:
1. A duty-cycle correction (DCC) circuit generating a clock signal for distribution over a clock distribution network, the clock distribution network providing differential output clock signals, the DCC circuit comprising: a first adjustable differential-to-single ended (DTS) clock driver configured to generate the clock signal for distribution from input differential clock signals, the first adjustable DTS clock driver having an adjustable electrical characteristic; a second adjustable DTS clock driver configured to generate a complementary single-ended clock signal from the input differential clock signals, the complementary single-ended clock signal complementary to the clock signal for distribution, the second adjustable DTS clock driver having a same adjustable electrical characteristic as the first adjustable DTS; a first adjustable delay having a first delay and configured to provide a first feedback clock signal having the first delay relative to the clock signal for distribution; a second adjustable delay having a second delay and configured to provide a second feedback clock signal having the second delay relative to the complementary single-ended clock signal; and a phase detector configured to determine a phase difference between a first one of the differential output clock signals and the first feedback clock signal and adjust the first and second delays based thereon and further configured to determine a phase difference between a second one of the output differential clock signals and the second feedback clock signal and adjust the electrical characteristics of the first and second adjustable DTS clock drivers based thereon.