Patent ID: 8082118
Filing Date: 2011-12-20
Classification: G01R,G11C

Abstract:
1. A test apparatus that tests a device under test, comprising: a clock recovering section that recovers a clock signal from an output signal output by the device under test; an acquiring section that acquires the output signal at a timing corresponding to the clock signal; an adjusting section that adjusts a phase difference between the clock signal and the output signal received by the acquiring section, according to an adjustment amount supplied thereto; a setting memory that stores an adjustment amount of the phase difference between the clock signal and the output signal in the acquiring section in association with each of a plurality of test conditions; a setting section that supplies the adjusting section with an adjustment amount associated with a test condition for testing the device under test, based on the adjustment amounts stored in the setting memory; a test condition setting section that sets a test condition; an adjusted signal generating section that generates an adjusted signal corresponding to the test condition set by the test condition setting section; and a switching section that receives an output signal of the device under test and the adjusted signal, and outputs either the output signal of the device under test or the adjusted signal, wherein the acquiring section acquires a signal based on the output of the switching section.