Patent ID: 6269354
Filing Date: 2001-07-31
Classification: G06K,G06N

Abstract:
A memory circuit, comprising:a stage-m stage m having k.sub.m stage-m e-cell pairs, each stage-m e-cell pair having k.sub.b stage-m forward input synapses and a stage-m backward output;a stage-b stage b having k.sub.b stage-b e-cell pairs, each stage-b e-cell pair having one or more stage-b forward input synapses, a stage-b forward output, k.sub.m stage-b backward input synapses, and a stage-b backward output; anda stage-r stage r having k.sub.r stage-r e-cell pairs, each stage-r e-cell pair having a stage-r forward input, a stage-r forward output, and one or more stage-r backward input synapses;wherein each of the k.sub.b stage-b forward outputs is coupled to a corresponding stage-m one of the k.sub.b stage-m forward input synapses, each of the k.sub.m stage-m outputs is coupled to a corresponding stage-b one of the k.sub.m stage-b backward input synapses, each of the k.sub.r stage-r forward outputs is coupled to one or more of the stage-b forward input synapses, and each of the k.sub.b stage-b backward outputs is coupled to one or more of the stage-r backward input synapses.