Patent ID: 6376877
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; insulator shallow trench isolations (STIs) having selected surface area profiles and disposed in the semiconductor substrate, the selected surface area profiles including multiple first and second concave curves, the multiple first concave curves having greater radii than the radii of the multiple second concave curves; a tunnel oxide (TOX) layer disposed on the semiconductor substrate between the shallow trench isolations; a first polysilicon (poly) layer disposed over the TOX layer and between the insulator shallow trench isolations to form a floating gate; an oxynitride (ONO) layer disposed over the first poly layer and the shallow trench isolations, the shallow trench isolation having the multiple first concave curves adjacent the ONO layer; and a second poly layer disposed over the ONO layer to form a control gate.