Patent ID: 7462542
Filing Date: 2008-12-09
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a semiconductor device, comprising: a) providing a substrate having a first device area and a second device area; b) forming a plurality of gate structures over the substrate both in the first device area and the second device area; c) forming a source region and a drain region in the substrate and adjacent to sidewalls of each of the gate structures; d) forming a self-aligned salicide block (SAB) layer on the substrate and covering the gate structures; e) performing an anneal process directly after the step d) to make the SAB layer create a tension stress so that the substrate under the gate structures is subjected to the tension stress; f) removing a portion of the SAB layer to expose the gate structures and a portion of the surface of the substrate in the second device area; and g) performing a self-aligned silicide process to form a silicide layer on the gate structures, the source regions, and the drain regions in the second device area, wherein the surface of the gate structures, the source regions, and the drain regions in the first device area is still covered by the SAB layer without silicide layer.