Patent ID: 6266761
Filing Date: 2001-07-24
Classification: G06F

Abstract:
An information processing system, comprising:first circuitry for:processing an execution stage of a first type of instruction which always specifies at least one of a first type of register or a second type of register, and outputting first information in response thereto;processing an execution stage of a second type of instruction which always specifies only a third type of register, and outputting second information in response thereto;a plurality of rename buffers coupled to said execution stage for storing a copy of said output first information, one of said plurality of rename buffers being allocated for each said first type of instruction, wherein at least one of said buffers is for storing said output first information independent of which of said first and second types of registers is specified by said first type of instruction, and wherein said at least one of a first type of register or a second type of register is temporarily renamed as one of said plurality of rename buffers; andsecond circuitry coupled to said buffers for:determining, during a completion stage of each one of a plurality of instructions processed by said information processing system, whether one of said plurality of rename buffers was allocated for each one of said plurality of instructions;processing a completion stage of said first type of instruction, and writing said copy of said first information stored in said one of said plurality of rename buffers into at least one of said first or a second type of register in response thereto;processing a completion stage of said second type of instruction, and writing said second information into only said third type of register in response thereto;deallocating said one of said plurality of rename buffers allocated for said each one of said plurality of instructions in response to a determination that said one of said plurality of rename buffers was allocated.