Patent ID: 6521519
Filing Date: 2003-02-18
Classification: H01L,Y10S

Abstract:
A manufacturing method of a MIS transistor comprises:forming a gate insulation film and a gate electrode, both of a MIS transistor, on a silicon substrate; forming a sidewall spacer including a silicon nitride layer, on both sides of said gate electrode on said silicon substrate in contact with said silicon substrate, and including a buffer nitrided oxide silicon layer on both sides of said gate electrode on said silicon substrate and in contact with said silicon substrate, wherein said buffer nitrided oxide silicon layer has a peak of nitrogen concentration on an interface with said silicon substrate, and the nitrogen concentration in said buffer nitrided oxide silicon layer declines with distance from said silicon substrate; and forming a silicide film outside of said sidewall spacer in said silicon substrate by using a metal to be diffusion species for silicon in silicide reaction.