Patent ID: 8458516
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A processor system comprising: a first processor comprising a first combinational circuit and a first memory circuit that temporarily stores an output value of the first combinational circuit and supplies an input value to the first combinational circuit, the first processor being configured to perform processing in response to a supplied instruction stream; a second processor comprising a second combinational circuit and a second memory circuit that temporarily stores an output value of the second combinational circuit and supplies an input value to the second combinational circuit, the second processor being configured to perform processing in response to a supplied instruction stream; a control unit that switches an operation mode between a lock step mode for the first and second processors to execute a same instruction stream and a free step mode for the first and second processors to execute different instruction streams; a signal line group that includes at least one signal line disposed between the first memory circuit and the second memory circuit and is capable of transferring a storage state of the first memory circuit to the second memory circuit; and a selection circuit capable of switching a connection destination of the second memory circuit between the second combinational circuit and the signal line group.