Patent ID: 7678684
Filing Date: 2010-03-16
Classification: G03F,H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising steps of: forming first interconnections and first dummy interconnections comprised of the same layer as said first interconnections over a principal surface of a semiconductor substrate; forming a first insulating film over said first interconnections and first dummy interconnections; forming a second insulating film over said first insulating film; planarizing said second insulating film by polishing; forming a third insulating film over said second insulating film; and forming second interconnections, second dummy interconnections and markers for lithography, said second dummy interconnections and said marks being comprised of the same layer as said second interconnections, over said third insulating film such that said markers are arranged over said first dummy interconnections and such that said second dummy interconnections comprised of the same layer as said markers are not disposed in a vicinity of said markers.