Patent ID: 7598111
Filing Date: 2009-10-06
Classification: G02F,H01L

Abstract:
1. A method of manufacturing a thin film transistor, comprising: forming a semiconductor layer on a substrate; forming a gate insulating layer on the substrate having the semiconductor layer; forming a gate on the gate insulating layer on the semiconductor layer; ion-implanting impurities into the semiconductor layer to form source/drain areas in the semiconductor layer at both sides of the gate electrode; forming an interlayer insulating layer on the entire surface of the substrate; etching a selected area of the interlayer insulating layer to form a contact hole/via hole that exposes the source/drain areas; forming source/drain electrodes that contact with the source/drain areas through the contact hole/via hole formed on the interlayer insulating layer; sequentially forming an inorganic layer and an organic planarization layer as a passivation layer on the entire surface of the substrate; blanket etching the organic planarization layer to expose a top of the inorganic layer; and etching a selected area of the inorganic layer to form a contact hole or a via hole that exposes one of the source/drain electrodes, where the top of the inorganic layer contacts a pixel electrode, and the organic planarization layer is located on an area of the inorganic layer that does not contact the pixel electrode.