Patent ID: 6159813
Filing Date: 2000-12-12
Classification: H01L,Y10S

Abstract:
A method for producing an NMOSFET on a semiconductor substrate, said NMOSFET having at least one graded LDD source region and at least one graded LDD drain region separated by a channel, comprising the steps of:providing a gate structure on said semiconductor substrate;implanting said semiconductor substrate with a first low dosage N type conductivity-altering material to create a lightly doped source region and a lightly doped drain region;forming sidewall spacers substantially abutting said gate structure to cover portions of said first low dosage implanted semiconductor substrate;implanting said semiconductor substrate with a high dosage N type conductivity-altering material to create a heavily doped source region and a heavily doped drain region flanking said gate structure, wherein said heavily doped source and drain regions supplant respective uncovered portions of said lightly doped source and drain regions; andimplanting said semiconductor substrate with a second low dosage N type conductivity-altering material to grade said heavily doped source and drain regions and remaining portions of said lightly doped source and drain regions.