Patent ID: 7272069
Filing Date: 2007-09-18
Classification: H03K

Abstract:
1. A multiple-clock controlled logic signal generating circuit, which comprises: a first switching module, which has a first input port, a second input port, an output port, and a control port; and whose first input port is connected to receive a first input signal, whose second input port is connected to receive a second input signal, and whose control port is connected to receive a switching control signal for selectively switching the connection of the output port between the first input port and the second input port for the purpose of outputting a selected one of the first input signal and the second input signal; a second switching module, which has a first input port, a second input port, an output port, and a control port; and whose first input port is connected to receive a first clock signal, whose second input port is connected to receive a second clock signal, and whose control port is connected to receive the same switching control signal that is linked to the control port of the first switching module for selectively switching the connection of the output port between the first input port and the second input port for the purpose of outputting a selected one of the first clock signal and the second clock signal; and a flip-flop unit, which has an input port, a triggering port, and an output port; and whose input port is connected to the output port of the first switching module, whose triggering port is connected to the output port of the second switching module, and whose output port is used to output a selected one of the first input signal and the second input signal.