Patent ID: 8712709
Filing Date: 2014-04-29
Classification: G01R,H03M

Abstract:
1. A delta-sigma AD converter circuit, comprising: a modulation unit to produce pulse density modulated data by pulse density modulation of an analog signal; and a filtering unit to convert the pulse density modulated data into pulse code modulated data, wherein the modulation unit includes: a shift register to store and shift the pulse density modulated data in synchronization with a clock, said shift register having a bit width; a counter to generate a register store instruction signal and a read request signal upon a count value reaching a predetermined value responsive to a mode, the count value being a count of a number of shifts of the shift register; and a plurality of conversion result registers to store plural data obtained by dividing data stored in the shift register and to hold the plural data in such a form that each of the plural data is readable independently of the others, wherein each register comprising said plurality of conversion result registers has a bit width that is less than the bit width of said shift register, wherein each register comprising said plurality of conversion result registers stores a portion of the pulse density modulated data stored in the shift register in response to the register store instruction signal, and the filtering unit reads the pulse density modulated data from one or more of the plurality of conversion result registers according to the mode, in response to the read request signal.