Patent ID: 6760204
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A semiconductor integrated circuit device, comprising:a plurality of insulated gate field effect transistors IGFETs coupled to a corresponding input/output (I/O) terminal through a corresponding first resistance; a first clamping device coupled to each I/O terminal; a second clamping circuit corresponding to each IGFET, each second clamping circuit including a second clamping device and the corresponding first resistance, each second clamping device having a first terminal connected to a gate electrode of the corresponding IGFET and a second terminal connected to a source/drain terminal of the corresponding IGFET and a supply potential wiring; each first clamping device being coupled to one second clamping device through a second resistance; and at least two of the second clamping circuits vary from one another wherein the at least two second clamping circuits vary by a first resistance (Rin) of one second clamping circuit having a different value than the first resistance (Rin) of the other second clamping circuit, and a ratio between the second resistance and the first resistance (Rg/Rin) for both clamping circuits having a predetermined maximum value.