Patent ID: 7447090
Filing Date: 2008-11-04
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a first bit line sense amplifier array for amplifying a data input to a first bit line pair coupled to cells; a second bit line sense amplifier array for amplifying a data input to a second bit line pair coupled to the cells; and a control unit for activating one of the first and second bit line sense amplifier arrays and, after a predetermined time, for activating the other bit line sense amplifier array in response to an active signal and a column address information signal, wherein the control unit includes a driving control signal transferring unit having a selection unit and a delay unit, wherein the selection unit generates first and second selection signals in response to the active signal and the column address information signal, and the delay unit outputs driving control signals or delayed driving control signals in response to the first and second selection signals.