Patent ID: 6581132
Filing Date: 2003-06-17
Classification: G06F,G11C

Abstract:
A flash memory system comprising:a memory manager for managing data transmission/reception between a host computer and a flash memory, said memory manager having an address conversion table for converting a logical address given to the flash memory from the host computer and a physical address as an actual address of the flash memory, said address conversion table being defined in accordance with minimum erasing units corresponding to blocks, said memory manager comprising a block status table storing data indicating a state of each block of said flash memory corresponding to a minimum erasing unit of the flash memory, said data indicating at least whether or not each block is good, has a bad sector, or is being used, said memory manager setting a size of an area of a logical address in which the flash memory is accessible from said host computer to be smaller than a size of an area of a physical address as an actual address of the flash memory, and said memory manager having a queue ready for use in a surplus area of the physical address area which is made up of blocks in an erased state not corresponding to the blocks in the logical address area and managing the queue, the physical address, and the physical address per block minimum erasing unit.