Patent ID: 8927370
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method for fabricating a memory, the method comprising: providing a substrate having a memory area and a non-memory area, wherein the non-memory area comprises at least a first voltage region and a second voltage region; forming a first dielectric layer in the non-memory area, wherein a first thickness of the first dielectric layer in the first voltage region is greater than a second thickness of the first dielectric layer in the second voltage region; forming a first conductive layer over the first dielectric layer in the non-memory area; forming thereafter a second dielectric layer in the memory area; forming sequentially a second conductive layer and a third dielectric layer in the memory area; forming a plurality of rows of stack structures in the memory area by patterning the third dielectric layer and the second conductive layer, wherein a space is configured between every two adjacent rows of stack structures; forming a plurality of buried diffusion regions in the substrate adjacent to sides of the rows of the stack structures; forming a fourth dielectric layer filling the space between the rows of stack structures; forming a fifth dielectric layer over the second conductive layer and the fourth dielectric layer in the memory area; forming a third conductive layer over the fifth dielectric layer; and patterning the third conductive layer, the fifth dielectric layer, and the second conductive layer to form a plurality of memory devices in the memory area.