Patent ID: 8522096
Filing Date: 2013-08-27
Classification: G01R

Abstract:
1. A method for time-division demultiplexing a high-speed test stimulus applied on one or more high-speed I/O pads, provided at a selected data-rate R 1 , into a slow-speed test stimulus, driven at a selected data-rate R 2 , for driving selected scan chains in a module of a die in a scan-based three-dimensional (3D) integrated circuit (3DIC) during scan-test mode, the 3DIC containing two or more dies (layers), each die containing one or more modules and comprising selectively one or more said high-speed I/O pads on a bottom layer or one or more high-speed I/O pins on an upper layer provided at said selected data-rate R 1 , each module including one or more scan chains, each scan chain comprising a plurality of scan cells coupled in series, the scan-based 3DIC further containing one or more time-division demultiplexing (TDDM) circuits, one or more time-division multiplexing (TDM) circuits, at least one high-speed clock CK 1 , at least one slow-speed clock CK 2 connected to said selected scan chains in the module of the die; said method comprising: (a) generating, shifting-in, demultiplexing said high-speed test stimulus through a said TDDM circuit to said selected scan chains in the module of the die in an alternate manner that cycles through said two or more dies, during a shift-in operation; (b) capturing a test response to said selected scan chains in the module of the die during a capture operation; and (c) multiplexing and shifting-out said test response through a said TDM circuit to said high-speed I/O pads for analysis in an alternate manner that cycles through said two or more dies, while shifting-in a new high-speed test stimulus to said selected scan chains, during a shift-out operation.