Patent ID: 6856203
Filing Date: 2005-02-15
Classification: H03D,H03L,H04L

Abstract:
1. A phase locked loop (PLL) comprising: a programmable frequency divider network for dividing an input frequency by an integer value; and a frequency multiplier comprising a voltage controlled oscillator (VCO) and having a first input for receiving a reference frequency, a second input connected to an output of said programmable frequency divider network, and an output connected to an input of said programmable frequency divider network, said frequency multiplier generating at the output an output signal having a frequency equal to a product of the reference frequency and the integer value; said VCO comprising a control circuit for adjusting an initial free-running frequency of said VCO in response to changes in the integer value so that a frequency difference between the initial free-running frequency divided by the integer value and the reference frequency is maintained at an approximately constant value, resulting in a controllable lock time that is independent of the integer value.