Patent ID: 8255780
Filing Date: 2012-08-28
Classification: H03M

Abstract:
1. A method of performing a high speed Viterbi and Trellis Coded Modulated (TCM) decoding for a Multi-Standard support in an application specific processor, said application specific processor comprising: a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits; a Branch Metric Compute (BMU) slot that performs at least one of Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; an Add-Compare-Select (ACS) slot that performs at least one of Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation; and specialized register file components, said specialized register file components comprising an optimized number of at least one of read ports and write ports that enables a faster processing of said Viterbi decoding functions, wherein said specialized register file components comprising at least one of a De-puncturing Register File, a General Purpose Register file, Primary and Secondary State Metric Register files, and Primary and Secondary Branch Metric Register files, wherein said method comprising: