Patent ID: 7680129
Filing Date: 2010-03-16
Classification: H04L

Abstract:
1. An apparatus for data transmission comprising: a buffer storing a data item to be transmitted to a receiver, wherein the buffer is configured to be pinned when in use by a hardware device and the buffer is configured to be pinned until a transmission from the hardware device is completed with one of a definite success and a definite failure, wherein when the buffer is pinned virtual memory used for the buffer is forced to remain real; a plurality of hardware resources segregated into a plurality of independent transmission paths; a timer mechanism for timing a predetermined optimum interval for a retransmission of the data item to the receiver, the predetermined optimum interval being less than a round-trip time required for receipt of an error condition from the network, the timer mechanism further signaling an end of the predetermined optimum interval; a memory manager configured to maintain a reference count of concurrent accessors; a first accessor of the buffer to access the data item for a first transmission and to start a first timeout clock set to the predetermined optimum interval; a second accessor of the buffer responsive to the signaling of the end of the predetermined optimum interval by the timer mechanism to access the data item for the retransmission and to start a second timeout clock set to the predetermined optimum interval, the second accessor attempting to select a path for transmission of the data item avoiding use of path elements used by the first accessor, wherein the memory manager is further configured to lock the buffer during write activity, to permit read access to the buffer by the first accessor and the second accessor and to return the buffer to a free buffer pool when the reference count reaches zero; a network monitoring data analyzer configured to analyze data for the apparatus; and an interval tuner configured to tune the predetermined optimum interval timed by the timer mechanism.