Patent ID: 6482715
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method of forming a shallow trench isolation in a semiconductor device, comprising:forming a first trench and a second trench in an area selected from a semiconductor substrate: forming a sidewall oxide layer on the inner surfaces of the first and second trenches; forming an anti-oxidation liner on the surface of the sidewall oxide layer; forming a mask layer on the semiconductor substrate surface including the anti-oxidation liner; forming a photoresist pattern to expose the mask layer in the second trench; patterning the mask layer in the form of the photoresist pattern; removing the photoresist pattern; etching the anti-oxidation liner in the form of the mask layer; forming a dielectric material to completely fill the first and second trenches; and forming a shallow trench isolation layer by chemically and mechanically polishing the dielectric material and layers underneath until the semiconductor substrate surface is exposed.