Patent ID: 7833846
Filing Date: 2010-11-16
Classification: H01L

Abstract:
1. A method of fabricating an array substrate, comprising: forming a buffer layer of inorganic insulating material on a substrate including a pixel region; forming a gate electrode on the buffer layer, a gate insulating layer on the gate electrode and an active layer on the gate insulating layer, the gate electrode including a bottom pattern of impurity-doped polycrystalline silicon, a middle pattern of silicide and a top pattern of a first metallic material and positioned in a switching region in the pixel region; forming an interlayer insulating layer on the active layer and including first and second contact holes, the first and second contact holes respectively exposing both sides of the active layer; forming first and second barrier patterns respectively contacting the both sides of the active layers through the first and second contact holes, first and second ohmic contact patterns respectively on the first and second barrier patterns, a source electrode on the first ohmic contact pattern, a drain electrode on the second ohmic contact pattern, and a data line connecting the source electrode; forming a first passivation layer on the source electrode, the drain electrode and the data line and including a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer and contacting the gate electrode through the gate contact hole, the gate line crossing the data line to define the pixel region; forming a second passivation layer on the gate line and including a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer and contacting the drain electrode through the drain contact hole.