Patent ID: 8981426
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. An electrostatic discharge protection circuit, comprising: a P-type substrate; an N-well formed on the P-type substrate; a first P-doped region formed on the N-well, wherein the first P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, wherein the first N-doped region is electrically connected to a first node, and the first P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; a second P-doped region formed on the N-well, wherein the second P-doped region is electrically connected to a second node; a second N-doped region formed on the N-well and electrically connected to a second node, wherein the first P-doped region and the second N-doped region constitute a parasitic diode; a gate structure formed on the N-well and located between the first and the second P-doped regions, wherein the gate structure is electrically connected to the second node; and the gate structure and the first and the second P-doped region constitute a MOSFET, wherein when an ESD event occurs at the input/output terminal, the silicon controlled rectifier bypasses electrostatic charges to the first node, and the parasitic diode and the MOSFET bypass electrostatic charges to the second node.