Patent ID: 6477108
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A semiconductor device comprising:a memory array including a plurality of memory cells arranged in rows and columns, for conducting data transmission and reception in response to an address signal in synchronization with an internal clock signal; and a clock processing circuit for transmitting a basic clock signal as said internal clock signal to said memory array in response to a command, said command including a row activation command that indicates start of a row selection operation of said plurality of memory cells for data transmission and reception to and from said memory array, and said clock processing circuit including an internal clock control circuit for activating an internal clock enable signal in response to said row activation command, and an internal clock generation circuit for outputting said internal clock signal based on said basic clock signal in response to activation of said internal clock enable signal, and deactivating said internal clock signal in response to deactivation of said internal clock enable signal wherein said internal clock control circuit includes an internal circuit for activating an internal control signal in response to said row activation command and a received clock enable signal, and a selection circuit for selecting said clock enable signal in a first mode and selecting said internal control signal in a second mode so as to output the selected signal as said internal clock enable signal.