Patent ID: 7274060
Filing Date: 2007-09-25
Classification: H01L

Abstract:
1. A memory cell array, comprising: a plurality of memory cells, each memory cell including a storage capacitor and an access transistor; a plurality of bit lines oriented in a first direction; a plurality of word lines oriented in a second direction, the second direction being perpendicular to the first direction; and a semiconductor substrate with a surface and a plurality of active area lines formed therein, a longer side of each active area line extending in the second direction; wherein access transistors of the memory cells are at least partially formed in the active area lines and electrically couple corresponding storage capacitors to corresponding bit lines, each access transistor including: wherein each gate electrode includes a bottom side, each word line includes a bottom side, the bottom side of the gate electrodes being disposed beneath the bottom side of the word lines, and the word lines are disposed above the bit lines.