Patent ID: 6983366
Filing Date: 2006-01-03
Classification: H04L

Abstract:
1. A packet processor comprising: a control unit having a data input; at least one encryption processor; a first authentication processor; a second authentication processor; a local data bus, independent of the data input to the control unit, coupling the control unit to each of the encryption and authentication processors; and a second data bus from the encryption processor to each authentication processor, including a data bus from the first authentication processor to the second authentication processor wherein the control unit is configured to control the at least one encryption processor and the first and second authentication processors such that a first set of data and a second set of data sent from the at least one encryption processor to the first authentication processor and the second authentication processor, respectively, are processed by the first authentication processor and the second authentication processor while the at least one encryption processor processes a third set of data, and wherein the at least one encryption processor, the first authentication processor and the second authentication processor are coupled to the local data bus independent of each other and independent of the control unit.