Patent ID: 6509257
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A process for making a semiconductor device, comprising the steps of:a first step of embedding a conductive material in a via-hole formed in a first interlayer dielectric film to form a conductive plug connected to a lower layer wiring line; a second step of forming an upper layer wiring groove in a second interlayer dielectric film formed on said conductive plug such that a target area of said conductive plug is exposed in said upper layer wiring groove; a third step of forming a first barrier layer on an entire surface of said second interlayer dielectric film including said upper layer wiring groove; a fourth step of selectively removing said first barrier layer formed on said conductive plug; a fifth step of embedding a material to form a seed layer on a surface of said conductive plug expose in said upper layer wiring groove; and a sixth step of embedding a wiring material in said upper layer wiring groove to form an upper layer wiring line, said wiring material being same as said material for said seed layer in said fifth step.