Patent ID: 6764863
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method for fabricating a memory-storage node, comprising:providing a semiconductor substrate; forming a first insulating layer over said substrate; forming a first opening in said first insulating layer; providing a conductive layer in said first opening; forming a barrier layer in said first opening and over said conductive layer, said barrier layer being conductively coupled with said conductive layer, said barrier layer comprising ruthenium, wherein said barrier layer has a recessed top surface; forming a second insulating layer over said first insulating layer and said barrier laver; forming a second opening in said second insulating layer, said second opening exposing a portion of said barrier layer; forming a first electrode in said second opening; forming a dielectric layer on said second insulating layer and said first electrode; and forming a second electrode over said dielectric layer.