Patent ID: 7827427
Filing Date: 2010-11-02
Classification: G06F

Abstract:
1. A system-on-chip comprising: a controller configured to generate a first input/output control signal to determine an input/output state in a normal mode, a second input/output control signal to determine the input/output state in a sleep mode, a normal value, and a sleep value; a first register configured to store the first input/output control signal; a second register configured to store the second input/output control signal; a third register configured to store the normal value; a fourth register configured to store the sleep value; a first selector configured to select an alternative one from the first and second input/output control signals in accordance with an operation mode; an internal logic circuit configured to operate in the normal mode under the control of the controller and configured to generate a signal to be transferred to an external chip in response to the normal value from the third register; a second selector configured to select an alternative one from outputs the fourth register and the internal logic circuit in accordance with the operation mode; a power manager configured to control the first and second selectors; and a retention input/output device configured to store outputs of the first and second selectors in response to the power manager when the normal mode transitions to the sleep mode, wherein the input/output state of the retention input/output device is held by the output of the first selector when the normal mode transitions to the sleep mode.