Patent ID: 6635547
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method of forming a memory cell comprising the steps offorming a transistor including a source and a dram over an active area of a substrate, wherein said source of said transistor is connected to a bit line and a gate of said transistor is connected to a word line; and forming a capacitor connected to said drain of said transistor and to a voltage reference, wherein said step of forming said capacitor further comprises forming a first conductive layer as a double sided electrode having an inner side and an outer side, said outer side being adjacent to at least one insulating layer; forming a first dielectric layer over the inner side of the double sided electrode; exposing at least a portion of the at least one insulating layer on the outer sided electrode to form an exposed portion of said double sided electrode; forming a second dielectric layer over said first dielectric layer and said exposed portion of said double sided electrode; and forming a second conductive layer over said second dielectric layer.