Patent ID: 7676780
Filing Date: 2010-03-09
Classification: G06F

Abstract:
1. A method of determining buffer insertion locations in a net of an integrated circuit design, comprising: defining at least one signal slew constraint for the net by executing first instructions in a computer system; establishing a plurality of candidate locations for inserting one or more buffers into the net by executing second instructions in a computer system; and selecting buffer insertion locations from among the candidate locations by pruning any candidate location whose buffer output slew is greater than the signal slew constraint, the buffer output slew SL(v) of a given candidate location having a buffer b inserted at a node v being computed as wherein C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b by executing third instructions in a computer system.