Patent ID: 8748986
Filing Date: 2014-06-10
Classification: H01L

Abstract:
1. A field effect transistor having a source, drain, and a gate, comprising: a SOI substrate including a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried oxide layer; a low dopant channel region positioned below the gate and between the source and the drain, the low-dopant channel region being further positioned in an upper portion of the semiconductor overlayer; a plurality of doped regions having a predetermined dopant concentration profile in the SOI substrate, the plurality of regions including a threshold voltage set region, a screening region, and a ground plane region; the threshold voltage set region positioned below the low-dopant channel region; the screening region positioned in the semiconductor overlayer below the threshold voltage set region, the screening region extending between the buried insulator layer and the threshold voltage set region; and the ground plane region positioned below the buried insulator layer.