Patent ID: 6633969
Filing Date: 2003-10-14
Classification: G06F

Abstract:
An apparatus, comprising:instruction decompression logic coupled to receive a first portion of an instruction data block, an output signal, and a control signal during a time period, wherein the instruction data block includes a first variable-length instruction, and wherein the instruction decompression logic is configured to produce a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output signal, and the control signal; and caching logic comprising a storage unit and coupled to receive a second portion of the instruction data block and the control signal during the time period, and wherein the storage unit is configured to store the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal, and wherein the caching logic is configured to produce the output signal, wherein during the time period the output signal is either the second portion of the instruction data block or the contents of the storage unit.