Patent ID: 6127255
Filing Date: 2000-10-03
Classification: G03F,H01L,Y10S

Abstract:
A method of fabricating a semiconductor integrated circuit device, comprising:forming wiring lines, including uppermost wiring lines, having a thickness, over a main surface of a semiconductor substrate at a first portion and a second portion of said main surface, said uppermost wiring lines being arranged in parallel with each other with a first gap and a first aspect ratio in said first portion and being arranged in parallel with each other with a second gap and a second aspect ratio in said second portion;forming a first insulating film over said uppermost wiring lines and between adjacent uppermost wiring lines in said first and second portions; andforming a second insulating film over said first insulating film in said first and second portions;wherein said second gap is larger than said first gap,wherein said first aspect ratio is larger than 1 and said second aspect ratio is smaller than 1,wherein said first insulating film is formed to have a thickness of at least one-half of said first gap between adjacent uppermost wiring lines in said first portion, but less than one-half of said second gap between adjacent uppermost wiring lines in said second portion,wherein said first and second insulating films, formed over said uppermost wiring lines, constitute a passivation layer of the semiconductor integrated circuit device, andwherein said second insulating film is thicker than said first insulating film.