Patent ID: 6392944
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A semiconductor memory device comprising:a pair of bit lines; a memory cell connected to either one of said pair of bit lines and storing data; a sense amplifier for sensing and amplifying a potential difference of said pair of bit lines, the potential difference being caused in accordance with the data read from said memory cell; a first power feed line for supplying a driving power to said sense amplifier; a second power feed line for supplying the driving power to said sense amplifier; a first sense amplifier driving transistor connected between said first power feed line and said sense amplifier; a second sense amplifier driving transistor connected between said second power feed line and said sense amplifier; a first decoupling capacitor connected between said first power feed line and a power source providing a power source potential different in logic level from the driving power; a second decoupling capacitor connected between said second power feed line and said power source; a first power feed circuit for precharging said first power feed line and said first decoupling capacitor to a first potential prior to activation of said sense amplifier; and a second power feed circuit for charging said second power feed line and said second decoupling capacitor to a second potential different in level from said first potential.