Patent ID: 6401175
Filing Date: 2002-06-04
Classification: G06F

Abstract:
A computer system comprising:a plurality of processing units; a main memory; a shared write back buffer that stores storage data to be written to said main memory, wherein said shared write back buffer is coupled to receive said storage data from any processing unit included in said plurality of processing units; and a data cache unit, wherein said data cache unit includes said write back buffer, a directory array, and a data array; wherein said shared write back buffer further includes: a plurality of address inputs, wherein each said address input is configured to receive an address data originating from one of said plurality of processing units; a plurality of storage data inputs, wherein each said storage data input is configured to receive storage data originating from one of said plurality of processing units, each said address data being associated with one of said storage data and also being associated with a corresponding address in said main memory; a data bank that includes a plurality of data registers; an address bank that includes a plurality of address registers; and an output port that is configured to provide said storage data from said data bank to said main memory.