Patent ID: 7135746
Filing Date: 2006-11-14
Classification: G11C,H01L,Y10S

Abstract:
1. An SRAM cell having gate patterns vertically stacked on a cell array region comprising: a device isolation layer isolating at least one lower active region in a semiconductor substrate of the cell array region; a body pattern disposed in parallel with the semiconductor substrate and disposed on a vertical line passing through the lower active region so as to confine an upper active region; two lower cell gate patterns disposed on the lower active region, and upper cell gate patterns disposed on the lower cell gate patterns so as to overlap the lower cell gate patterns respectively and disposed in opposite to each other on the body pattern; a landing pad being in contact with one of the upper cell gate patterns and the body pattern, and disposed between the lower cell gate patterns; a node pattern spaced away from the landing pad with a predetermined distance, and disposed in contact with the remaining upper cell gate patterns and the underneath lower cell gate pattern; and a semiconductor buffer layer disposed to surround portions of sidewalls of the node pattern and the landing pad, and to conformally cover the upper active region and the upper cell gate patterns, wherein the node pattern and the landing pad contact the device isolation layer and the semiconductor substrate respectively, and interfaces between sidewalls of the upper cell gate patterns and the semiconductor buffer layer have a predetermined angle with respect to a main surface of the semiconductor substrate.