Patent ID: 7117290
Filing Date: 2006-10-03
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a cache comprising a data memory configured to store a plurality of cache lines and a tag memory configured to store a plurality of tags, each of the plurality of tags corresponding to a respective one of the plurality of cache lines; a first translation lookaside buffer (TLB) configured to store a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB; and a tag circuit coupled to the first TLB, the tag circuit configured to identify one or more of the plurality of cache lines that are stored in the cache and are within the plurality of virtual pages, the tag circuit configured to store an in-page portion of one or more virtual addresses corresponding to the one or more of the plurality of cache lines identified by the tag circuit, and the tag circuit configured to compare the in-page portion of the one or more virtual addresses to a corresponding in-page portion of the first virtual address to detect a hit; wherein, in response to a hit by a first virtual address in the first TLB and the hit by the first virtual address in the tag circuit, the tag circuit is configured to prevent a read of the tag memory in the cache.