Patent ID: 6405288
Filing Date: 2002-06-11
Classification: G06F

Abstract:
A memory access control system for controlling a memory access operation by a CPU to a memory unit, the CPU being capable of issuing a series of read requests each time the CPU intends to read data from the memory unit and being further capable of issuing a level 1 (L1) write-back signal indicative whether the current read request is a hit or a miss to a cache memory after a first delayed period after the current read request is issued, and in the event that the L1 write-back signal of the current read request indicates a cache hit, issuing a cache write-back request to perform a cache write-back operation to write an output cache data from the CPU back into the memory unit after a second delayed period after the L1 write-back signal is issued;the memory access control system comprising: (a) a CPU interface coupled to the CPU, which is capable of being selectively switched to operate between a waiting mode and a non-waiting mode; in the waiting mode, the CPU interface responds to each read request from the CPU in such a manner as to wait until the L1 write-back signal of the current read request is received and then issue a corresponding internal read-request signal if the L1 write-back signal indicates a cache miss, or a corresponding internal cache write-back request signal if the L1 write-back signal indicates a cache hit; and in the non-waiting mode, the CPU interface responds to each read request from the CPU in such a manner that the CPU interface will promptly issue the corresponding internal read-request signal without waiting until the CPU issues the L1 write-back signal of the current read request, and in the event that the subsequently issued L1 write-back signal of the current read request indicates a cache hit, promptly issue a read-stop signal for the current read request; (b) a memory control unit coupled between the CPU interface and the memory unit, which is capable of performing a read operation on the memory unit in response to each internal read-request signal from the CPU interface, and further in response to the read-stop signal, is capable of abandoning the currently retrieved data from the memory unit demanded by the current read request and then performing the cache write-back operation to write back the subsequent output cache data from the CPU back into the memory unit; and (c) a mode-switching unit coupled between the CPU interface and the CPU, which is initially set to switch the CPU interface to operate in the waiting mode, and is further capable of detecting whether each read request from the CPU is a cache hit or a cache miss and counting the number of consecutive cache-miss read requests to thereby switch the CPU interface to the non-waiting mode when the count reaches a preset threshold.