Patent ID: 6066958
Filing Date: 2000-05-23
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a semiconductor substrate;an input/output control circuit formed on the surface of said semiconductor substrate, said input/output control circuit having a signal input terminal, a control terminal, a first output terminal and a second output terminal;a pre-driver circuit having first and second input terminals, third to sixth output terminals, a delay circuit, a two-input NOR gate, a two-input NAND gate and first and second inverters,in said pre-driver circuit, first and second input terminals are connected to first and second output terminals of said input/output control circuit respectively, first and second input terminals are connected to forth and fifth output terminals, first input terminal is connected to said delay circuit and said two-input NOR gate, second input terminal is connected to said two-input NAND gate, remaining input terminals of said two-input NOR gate and said two-input NAND gates are connected to the output terminal of said delay circuit, output terminal of said two-input NOR gate is connected to said first inverter and output of said first inverter is connected to third output terminal, output terminal of said two-input NAND gate is connected to said second inverter and output of said second inverter is connected to sixth output terminal;a main driver circuit having third to sixth input terminals and a seventh output terminal, a pair of transistor groups, each of said transistor group comprising a first conductor-type MOS transistor and a second conductor-type MOS transistor,in said main driver circuit, third to sixth input terminals are connected to said third to sixth output terminals of said pre-driver circuit respectively, seventh output terminal is connected to drain electrodes of the MOS transistors of said transistor groups, source electrode of one of the first conductor type MOS transistors is connected to power supply and gate electrode is connected to forth input terminal, source electrode of one of the second conductor type MOS transistors is connected to ground and gate electrode is connected to fifth input terminal, source electrode of remaining first conductor type MOS transistors is connected to power supply and gate electrode is connected to third input terminal, source electrode of remaining second conductor type MOS transistors is connected to ground and gate electrode is connected to sixth input terminal;a signal output terminal to which seventh output terminal of said main driver circuit is connected.