Patent ID: 6401168
Filing Date: 2002-06-04
Classification: G11B

Abstract:
A data storage device, comprising:a data storage unit; a FIFO memory, having at least sufficient memory capacity to contain three sectors of data associated with said data storage unit; an ECC unit having random access to any sector contained in said FIFO memory, wherein error correction and control is performed on data in said FIFO memory; and a FIFO memory controller to control locations at which data is written into and read from said FIFO memory, wherein said FIFO memory controller controls said locations at which data is written into and read from said FIFO memory, wherein as data is written into a first portion of said memory containing a sector currently being written, said ECC unit concurrently accesses a second portion of said memory containing a sector previously written to correct data therein, and data that has already been corrected by said ECC unit in a third portion of said memory is concurrently being read from said memory.