Patent ID: 6144714
Filing Date: 2000-11-07
Classification: H03K,H03L,H04J,H04L,H04Q

Abstract:
A method of generating a clock signal with a nominal frequency of Fc/(N+K/L) Hz over each successive interval of L periods, where N, K and L are integers, and L>K, and wherein Fc is a system clock, comprising the steps of:(a) organizing each set of L periods, including a first set of K periods and a second set of L-K periods, by interleaving two or more non-null subsequences of periods of the first set with two or more non-null subsequences of periods of the second set,(b) during each period of one of the subsequences of the first set, outputting as the clock, a first signal with a frequency of Fc/(N+1) Hz,(c) during each period of one of the subsequences of the second set, outputting as the clock, a second signal with a frequency of Fc/N Hz,(d) counting the periods of the clock such that periods of the first signal with the frequency Fc/(N+1) Hz are counted only during periods of the subsequences of the first set and periods of the second signal with the frequency of Fc/N Hz are counted only during periods of the subsequences of the second set, and(e) determining to switch between outputting the first signal as the clock and outputting the second signal as the clock based on the count obtained in step (d).