Patent ID: 6144251
Filing Date: 2000-11-07
Classification: G06F,H03K,Y02D

Abstract:
A semiconductor integrated circuit device comprising:a first component circuit selectively entering an active mode and a sleep mode, and includingan input port having plural input nodes supplied with input signals,an output port having output nodes assigned to output signals andfirst transistors connected between a first power supply line and a virtual power supply line different in potential level from said first power supply line, much liable to flow a first leakage current therethrough and responsive to said input signal in said active mode for producing said output signal at said output port;a second transistor connected between said virtual power supply line and a second power supply line different in potential level from said first power supply line, less liable to flow a second leakage current therethrough, and responsive to a mode signal so as to connect said virtual power supply line to said in said sleep mode in said active mode and disconnect said virtual power supply line from said second power supply line;a signal line connectable to said plural output nodes; anda switching circuit connected between said output nodes and said signal line, and responsive to a control signal so as to connect said output nodes to said signal line in said active mode and disconnect said output nodes from said signal line in at least said sleep mode.