Patent ID: 8754697
Filing Date: 2014-06-17
Classification: G01S,H03B

Abstract:
1. A dual mode frequency synthesizer circuit comprising: a direct digital synthesizer (DDS) for receiving an input clock as input and generating an output clock as an output, in a high resolution mode; and an RF switch having an output coupled to the output of the DDS, a first input for receiving a first injection low phase-noise clock, a second input for receiving a second injection low phase-noise clock, and a control input for selecting one of the first or second injection low phase-noise clocks as the RF switch output for a low phase-noise mode, wherein the second injection low phase-noise clock is generated from the first injection low phase noise clock by a divider, wherein the DDS is enabled, the RF switch is disabled and the output of the DDS is selected as the output of the dual mode frequency synthesize when the high resolution mode is activated, and wherein the DDS is disabled, the RF switch is enabled and one of the first or second injection low phase-noise clocks is selected as the output of the dual mode frequency synthesizer when the low phase-noise mode is activated.