Patent ID: 6559687
Filing Date: 2003-05-06
Classification: H03K

Abstract:
A comparator circuit, comprising:a first input to receive a first input signal; a second input to receive second input signal; a gain circuit coupled to the first input and the second input, the gain circuit configured to generate an output signal responsive to the difference between the first input signal and the second input signal, the output signal having a duty cycle, wherein the gain circuit is configured as a dual fully symmetrical folded cascode circuit; and a bias circuit coupled to the first input, the second input, and the gain circuit, the bias circuit configured to monitor a common mode voltage at the first input and the second input and to generate a bias signal correlative to the common mode voltage, wherein, in response to the bias signal, the gain circuit maintains the output signal responsive to the difference between the first and second input signals such that distortion of the duty cycle is minimized regardless of the value of the common mode voltage.