Patent ID: 8743516
Filing Date: 2014-06-03
Classification: H01L,H02H

Abstract:
1. An electrostatic discharge (ESD) protection circuit for a plurality of integrated circuit pins, comprising: a first bipolar junction transistor (BJT) stack having a first terminal connected to a first integrated circuit pin and a second terminal connected to a first node and comprising a first plurality of bipolar transistors connected in series, each formed with a base-to-collector spacing dimension which provides a predetermined trigger voltage and with a collector region that is connected across a shared diode to a reference voltage; a second BJT stack having a first terminal connected to a second integrated circuit pin and a second terminal connected to a second node and comprising a second plurality of bipolar transistors connected in series, each formed with a base-to-collector spacing dimension which provides a predetermined trigger voltage and with a collector region that is connected across a shared diode to a reference voltage; and a third shared BJT stack having a first terminal connected to the first and second BJT stacks at the first and second nodes, respectively, and a second terminal coupled to a shared reference voltage terminal, the third shared BJT stack comprising a third plurality of bipolar transistors connected in series, each formed with a base-to-collector spacing dimension which provides a predetermined trigger voltage and with a collector region that is connected across a shared diode to a reference voltage.