Patent ID: 7969252
Filing Date: 2011-06-28
Classification: G11C,H03L

Abstract:
1. A locked loop having a phase detector including first and second inputs and being configured to compare the phase of a reference clock signal applied to the first input with the phase of a signal applied to the second input and to generate an error signal corresponding thereto, the locked loop further comprising a signal generating device coupled to the phase detector and configured to generate an output clock signal as a function of the error signal and to generate a feedback clock signal in synchronism with the output clock signal, the locked loop comprising a delay circuit coupled along a feedback path of the locked loop between the signal generating device and the second input of the phase detector, the delay circuit configured to delay the feedback clock signal to provide a delayed feedback signal and apply the delayed feedback signal to the second input of the phase detector, the delay circuit being configured so that the phase of the delayed feedback clock signal applied to the phase detector relative to the phase of the output clock signal generated by the signal generating device is between about 20% and about 70% of a period of the reference clock signal.