Patent ID: 6178517
Filing Date: 2001-01-23
Classification: G06F,Y02D

Abstract:
A memory bus system having a low power mode for transferring data between a dynamic random access memory (DRAM) and a processor, comprising:a first, high-speed bus connected to a DRAM;a second, slower bus connected to the DRAM, said second bus requiring less power to operate than said first bus; anda switching circuit, connected to the processor, for alternately switching between a first mode and a second lower power mode,said first mode comprising accessing a plurality of addressable memory locations in said DRAM and transferring data on said first, high-speed bus connected to the processor, andsaid second low power mode comprising segmenting said DRAM and accessing less than all of said plurality of addressable memory locations in said DRAM and transferring data on said second, slower bus connected to the processor.