Patent ID: 7391668
Filing Date: 2008-06-24
Classification: G09G,G11C

Abstract:
1. An integrated circuit device, having a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, and a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, comprising: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction wherein, one of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, a memory cell array block that includes a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines and a control circuit block that controls programming, erasing and reading data from the memory cells; the plurality of word lines extend in the second direction; the memory cell array block and the control block are adjacent to each other in the first direction; the memory cell array block is divided into a first region and a second region at a center region in the second direction and has a plurality of column blocks divided in the second direction; two word line drivers respectively driving the plurality of word lines of the first region and of the second region, and two control gate drivers respectively driving the control gates of each of the plurality of memory cells respectively arranged in the first region and the second region; each of the plurality of word lines is hierarchized into main word lines and a plurality of sub word lines belonging to the main word line, the respective one of the plurality of sub word lines being arranged in each of the plurality of column blocks; a word line driver arranged in the center region is the main word line driver; each of the plurality of column blocks has a memory cell region and a sub word line decoder region, formed in a common well region of a semiconductor substrate, the sub word line decoder region further divided in the second direction, a sub word line decoder being arranged in the sub word line decoder region, the sub word line decoder selectively driving one of the plurality of sub word lines belonging to the main word line based on a state of the main word line; each of the plurality of memory cells has a write/read transistor formed on the semiconductor substrate and a floating gate which is common for each gate of an erase transistor; and the floating gate has a single layer gate structure which is opposed to, via an insulating film, a control gate formed by an impurity layer formed in the semiconductor substrate.