Patent ID: 6373291
Filing Date: 2002-04-16
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a first MOS transistor of a first conductivity type having one of its source and drain connected to a first signal input node, having the other thereof connected to a signal output node, and receiving a select signal at its gate; a second MOS transistor of a second conductivity type in parallel connection with said first MOS transistor, and receiving an inverted signal of said select signal at its gate; a third MOS transistor of the second conductivity type having one of its source and drain connected to a second signal input node, having the other thereof connected to said signal output node, and receiving said select signal at its gate; and a fourth MOS transistor of the first conductivity type in parallel connection with said third MOS transistor and receiving said inverted signal at its gate, wherein said semiconductor integrated circuit being configured to satisfy the relation as expressed by an inequality W1>W2 where W1 and W2 are gate widths of said first and second MOS transistors, respectively, and said semiconductor integrated circuit being configured to satisfy the relation as expressed by an inequality W3>W4 where W3 and W4 are gate widths of said third and fourth MOS transistors, respectively.