Patent ID: 6085274
Filing Date: 2000-07-04
Classification: G06F,Y02D

Abstract:
A bridge for communication between buses in a computer system, the bridge comprising:a first bus interface circuit connected to each of a first delayed completion queue, a first posted write queue, and a first delayed request queue;a second bus interface circuit connected to each of a second delayed completion queue, a second posted write queue, and a second delayed request queue;a first bridge bus connected to communicate read data and write transactions other than memory writes from said first bus interface circuit to said second delayed completion queue, and to communicate memory writes from said first bus interface circuit to said second posted write queue;a second bridge bus connected to communicate read data and write transactions other than memory writes from said second bus interface circuit to said first delayed completion queue, and to communicate memory writes from said second bus interface circuit to said first posted write queue;a third bridge bus connected from said first delayed completion queue to said second delayed request queue to communicate read requests from said first bus interface circuit to said second bus interface circuit;a fourth bridge bus connected from said second delayed completion queue to said first delayed request queue to communicate read requests from said second bus interface circuit to said first bus interface circuit;a first arbiter communicating with and to control transactions between said first bus interface circuit and each of said first delayed completion queue, said first posted write queue, and said first delayed request queue; anda second arbiter communicating with and to control transactions between said second bus interface circuit and each of said second delayed completion queue, said second posted write queue, and said second delayed request queue.