Patent ID: 6424178
Filing Date: 2002-07-23
Classification: G06F,H03K

Abstract:
A system for generating an output clock signal having a controllable duty cycle from an input clock signal, comprising:a duty cycle corrector circuit structured to generate the output clock signal from the input clock signal, the duty cycle corrector circuit being structured to transition the output clock signal to a first logic level responsive to a first transition of the input clock signal after a first delay that corresponds to a first control signal, the duty cycle corrector circuit being structured to further transition the output clock signal to a second logic level that is different from the first logic level responsive to a second transition of the input clock signal that is different from the first transition of the input clock signal after a second delay that corresponds to a second control signal; a duty cycle indicating circuit coupled to receive the output clock signal from the duty cycle corrector circuit and to generate a duty cycle feedback signal corresponding thereto, the duty cycle indicating circuit comprising an integrator circuit coupled to receive the output clock signal from the duty cycle corrector circuit and to generate as the duty cycle feedback signal a signal corresponding to the integral of the output clock signal with respect to time, the integrator circuit comprising: an inverter having an output terminal on which the duty cycle feedback signal is generated and an input terminal coupled to receive the output clock signal, the inverter comprising: a current source; a first transistor coupled to the output terminal, the first transistor being coupled in series with the current source; a current sink; and a second transistor coupled to the output terminal, the second transistor being coupled in series with the current sink; and a capacitor coupled to the output terminal; and a control circuit coupled to the duty cycle indicating circuit and the duty cycle corrector circuit, the control circuit being structured to generate the first and second control signals as a function of the duty cycle feedback signal so that the first and second delays are selected to cause the output clock signal to have a predetermined duty cycle.