Patent ID: 7873823
Filing Date: 2011-01-18
Classification: G06F

Abstract:
1. A method for reducing power dissipation in a reconfigurable computation circuit architecture, comprising the steps of: determining a selected electrical power utilization using one or more factors; determining a selected level of power dissipation reduction using one or more factors; translating tradeoffs between the one or more factors in the step of determining a selected level of power dissipation reduction to a substantially equivalent change in one or more of digital signal processing algorithms, functionalities, rank order, precision, sequencing, or a combination thereof; determining one or more modes of operation that may be used in a system; estimating savings in power dissipation and determining a time period for each of the one or more modes that may be used in the system; using a hardware reconfiguration mechanism having reconfigurable connectors to switch to an appropriate bit-width multiplication and higher order polynomial functions that reduces power dissipation; and dynamically monitor a time period of the energy mode of the system and revert to an original mode or a different mode of power usage as needed.