Patent ID: 7265705
Filing Date: 2007-09-04
Classification: H03M

Abstract:
1. A first stage circuit for a pipeline analog-to-digital converter (ADC), the first stage circuit receiving an analog input voltage and generating a first stage residue value for the pipeline ADC, the first stage circuit comprising: a sampling capacitor have a first plate switchably connected to the analog input voltage and a second plate; an amplifier having a positive input terminal switchably connected to the second plate of the sampling capacitor, a negative input terminal connected to a first power supply voltage and an output terminal; a plurality of feedback capacitors, each of the feedback capacitors having a first plate connected to the positive input terminal of the amplifier and a second plate switchably connected to the first power supply voltage and also switchably connected to the output terminal of the amplifier, the plurality of feedback capacitors except a first one of the feedback capacitors also having the second plates switchably connected to a selected reference voltage; and a comparator having an input terminal coupled to the output terminal of the amplifier, and an output terminal providing a digital control signal, the comparator providing the digital control signal in response to a first signal to select the selected reference voltage from a plurality of reference voltages for each of the plurality of feedback capacitors except the first one, wherein the sampling capacitor, the amplifier and the plurality of feedback capacitors are configured by a plurality of control signals to operate in a first mode to sample the input voltage onto the sampling capacitor and to perform a MDAC (multiplying digital-to-analog converter) function using the plurality of feedback capacitors to provide the first stage residue value at the output terminal of the amplifier, a second mode to discharge the plurality of feedback capacitors, and a third mode to transfer the sampled input voltage from the sampling capacitor to the plurality of feedback capacitors, the first signal causing the comparator to generate the digital control signal during the third mode.