Patent ID: 6066562
Filing Date: 2000-05-23
Classification: B24B,B28D,H01L

Abstract:
A method of fabricating silicon semiconductor discrete wafer of a double-layer structure, said method comprising:cutting a diffused wafer into two pieces at the center of the wafer thickness, each piece having an impurity diffused layer at one side and an impurity non-diffused layer at a cutting surface on the other side thereof, thengrinding both cutting surfaces with an abrasive grain of a count no less than #2000 and no greater than #6000, thenwet etching both ground surfaces, both wet etched surfaces being completed by the wet etching;collecting grinding water including silicon semiconductor chips during the grinding;mixing air into the grinding water, andjetting the mixed grinding water, during the grinding, as a group of minute grinding water drops, to a grinding wheel surface of a grinding wheel with said abrasive grain of a count no less than #2000 and no greater than #6000, thereby dressing the grinding wheel surface.