Patent ID: 6724611
Filing Date: 2004-04-20
Classification: H01G,H01L

Abstract:
A multi layer integrated circuit capacitor comprising:a substrate; a first conductive layer located over and contacting the substrate; a first insulator layer located over and contacting the first conductive layer, the first insulator layer not contacting the substrate; a second conductive layer located over the first insulator layer; a second insulator layer located over the second conductive layer; a third conductive layer located over the second insulator layer; a third insulator layer located over the third conductor layer; a plurality of conductive vias downwardly extending through the third insulator layer to provide electrical interconnection to the first, second and third conductive layers; and a plurality of controlled collapse chip connection (C4) lands fabricated on and contacting the third insulator layer and in electrical contact with the plurality of conductive vias.