Patent ID: 6086678
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A system for equalizing pressure across a gate adapted to selectively block a port connecting a wafer handling chamber to a process chamber of a reactor for depositing an epitaxial layer on a semiconductor wafer positioned in the process chamber by a chemical vapor deposition process, the system comprising:a bypass passage connecting the process chamber to the wafer handling chamber for transporting gas between the process chamber and the wafer handling chamber when the gate is blocking the port connecting the wafer handling chamber to the process chamber of the reactor for equalizing pressure between the process chamber and the wafer handling chamber;a bypass valve positioned along the bypass passage for selectively controlling gas flow through the bypass passage, the bypass valve having an open position in which gas is permitted to flow through the bypass passage to equalize pressure between the process chamber and the wafer handling chamber, and a closed position in which gas is prevented from flowing through the bypass passage to isolate the process chamber from the wafer handling chamber during the chemical vapor deposition process; andto limit pressure change rates in the process chamber and the wafer handling chamber when the bypass valve is in the open position and thereby to limit a maximum velocity of gas flowing through the bypass passage.