Patent ID: 9195470
Filing Date: 2015-11-24
Classification: G06F

Abstract:
1. A method of managing resources of a field-programmable gate array (FPGA), the method comprising the steps of: a computer at a runtime extracting and processing a first set of data; via a very high speed integrated circuit hardware description language (VHDL) interface, the computer at the runtime receiving a change in a size of a next set of data to be processed, a structure of the next set of data to be processed, or a load schedule of the next set of data to be processed, the change determined by a quantitative method analyzing the first set of data, the quantitative method executing external to the FPGA; based on the received change, the computer at the runtime executing a first bootstrap code in the FPGA; in response to the step of executing the first bootstrap code and based on the received change, the computer at the runtime updating at least one bootstrap code included in a plurality of other bootstrap codes in the FPGA, the first bootstrap code configured to dimension the next set of data, the plurality of other bootstrap codes including a second bootstrap code configured to extract the next set of data from a data source, a third bootstrap code configured to process the next set of data extracted by the second bootstrap code, a fourth bootstrap code configured to determine an order in which the next set of data is processed by the third bootstrap code, and a fifth bootstrap code configured to determine a configuration of the next set of data; and based on the received change and the updated at least one bootstrap code, the computer extracting and subsequently processing the next set of data.