Patent ID: 7492659
Filing Date: 2009-02-17
Classification: G11C,H01L

Abstract:
1. An integrated circuit device having a display memory which stores at least part of data displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells, a plurality of first power supply interconnects for supplying a first power supply voltage to the memory cells being provided in a metal interconnect layer in which the bitlines are formed, a second power supply interconnect for supplying a second power supply voltage to the memory cells being provided in a metal interconnect layer in which the wordlines are formed, the second power supply voltage being higher than the first power supply voltage, the bitlines being formed in a layer above the wordlines, a plurality of bitline protection interconnects being formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view, and a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory being provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.