Patent ID: 6567407
Filing Date: 2003-05-20
Classification: H04L

Abstract:
An ATM (Asynchronous Transfer Mode) switch circuit comprising:an ATM cell buffer memory for storing thereinto an ATM cell inputted to said ATM switch circuit; and ATM cell managing means for issuing both a storage request for said ATM cell and destination information indicative of one of a plurality of output ports corresponding to a destination of said ATM cell, and also for issuing both an output request and the destination information when said ATM cell is outputted to said one of said plurality of output ports, wherein said ATM cell is written into said ATM cell buffer memory based upon a buffer address defined by said storage request; said ATM cell is read out from said ATM cell buffer memory based on another buffer address defined by said output request to thereby be transmitted to said ATM cell managing means; and upon receipt of said ATM cell, said ATM cell managing means transmits said ATM cell to said one of said output ports in accordance with said destination information, said ATM switch circuit further comprising: empty address managing means for managing an empty address of said ATM cell buffer memory, and for outputting the empty address as a buffer address to said ATM cell buffer memory upon receipt of said storage request for said ATM cell issued from said ATM cell managing means, said empty address managing means outputting a plurality of buffer addresses corresponding to a plurality of ATM cells to be stored in said ATM cell buffer memory; and buffer address managing means for sequentially chaining said plurality of buffer addresses output by said empty address managing means to each other when said buffer address managing means receives the storage requests issued from said ATM cell managing means and the plurality of buffer addresses output from said empty address managing means, whereby buffer addresses of ATM cells directed to a same output port of said plurality of output ports are formed in a chain structure; and when the output request and the destination information issued from said ATM cell managing means are received, said buffer address managing means reads out the corresponding buffer address from said chain structure corresponding to said destination information to thereby transmit the corresponding buffer address to both said ATM cell buffer memory and said empty address managing means.