Patent ID: 6661059
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A lateral thin film insulated gate bipolar PMOS device comprising:a semiconductor substrate, a buried insulating layer on said substrate, and a lateral PMOS device in an SOI layer on said buried insulating layer and having a source region of p-type conductivity formed in a body region of n-type conductivity, a lateral drift region of n-type conductivity, adjacent said body region is a drain region of n-type conductivity and laterally spaced apart from said body region by said lateral drift region, and a gate electrode over a part of said body region extending over a part of said lateral drift region adjacent said body region, said gate electrode being insulated from said body region by an insulation region, said lateral drift region being provided with a linearly graded charge profile over a major portion of its lateral extent such that the doping level in said lateral drift region increases in a direction from said drain region toward said source region, and wherein said source region, said drift region, and said drain region form a bipolar transistor that operates to provide an additional current path when said PMOS device is in the on state, thereby reducing on resistance of said PMOS device.