Patent ID: 6754542
Filing Date: 2004-06-22
Classification: G05B

Abstract:
A control arithmetic apparatus comprising:first calculation means for calculating an error of a controlled variable on the basis of a controlled variable and set point for a controlled system; detection means for detecting, in control cycles, on the basis of the error output from said first calculation means whether a disturbance is applied; second calculation means for calculating an error correction amount on the basis of a magnitude of the error output from said first calculation means when application of a disturbance is detected; convergence operation means for performing convergence operation such that the error correction amount output from said error correction amount calculation means gradually converges to 0; and control arithmetic means for calculating a manipulated variable on the basis of the error output from said first calculation means and an error correction amount after the convergence operation which is output from said convergence operation means, wherein overshoot suppression processing is performed without depending on an adjustment of a proportional plus integral plus derivation (PID) parameter.