Patent ID: 7291878
Filing Date: 2007-11-06
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction; a plurality of layers, each layer having an array of memory cells; a plurality of tree structures, at least one tree structure corresponding to each bit line, each tree structure having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, the trunk portion of each tree structure extending from the substrate, each branch portion of a tree structure extending from the trunk portion of the tree structure, and each tree structure corresponding to a plurality of layers; and a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one layer, each respective plate line group overlapping branch portions of each tree structure in at least one row of tree structures at a plurality of intersection regions, a memory cell being located at each intersection region in a layer.