Patent ID: 8884291
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor, the source electrode and drain electrode being spaced apart from each other; a first passivation layer formed between the source electrode and the drain electrode on the semiconductor; a second passivation layer disposed on the source electrode and the drain electrode; and a pixel electrode connected to the drain electrode, wherein: the source electrode and the drain electrode each comprise a metallic lower layer and a metallic upper layer; the first passivation layer is disposed directly on an upper surface of an edge portion of each of the lower layers; and the second passivation layer is disposed directly on the upper layers of the source and drain electrodes.