Patent ID: 6399991
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A semiconductor integrated circuit comprising:a macro cell formed on a semiconductor substrate, and a guard ring provided to surround the circumference of said macro cell, said guard ring comprising: an n well disposed so as to surround the macro cell, a p well disposed adjacent to said n well to surround the macro cell, a first n+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a first potential is applied, a second n+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the first potential is applied, a first p+ diffusion region disposed in the surface layer of the n well to surround the macro cell in which a second potential lower than the first potential is applied, and a second p+ diffusion region disposed in the surface layer of the p well to surround the macro cell in which the second potential is applied.