Patent ID: 6178481
Filing Date: 2001-01-23
Classification: G06F

Abstract:
A microprocessor for coupling to an external read/write memory having an addressable storage space for storing cacheable data and non-cacheable data, said microprocessor comprising:a data storage circuit for storing a portion of said non-cacheable data;an address storage circuit for storing an address corresponding to said portion of said non-cacheable data;a counter for advancing a count from an initial value toward a threshold in response to an activity over time;an indicator for indicating said portion of said non-cacheable data in said data storage circuit is expired in response to said count reaching a threshold;a data bus selectively connectable to said data storage circuit enabling data transfers;an address bus carrying an address for data transfer; anda response circuit connected to said data storage circuit, said address storage circuit, said indicator and said address bus, said response circuit generating a hit signal when an address on said address bus matches said address stored in said address storage circuit and said indicator does not indicate said portion of said non-cacheable data in said data storage circuit has expired and otherwise generating a miss signal, said hit signal enabling said data storage circuit to supply data stored therein to said data bus in response to a data read operation.