Patent ID: 8188553
Filing Date: 2012-05-29
Classification: A23D,C11B,H01L

Abstract:
1. A semiconductor device comprising: a first semiconductor layer having an element region in which negative charges are introduced; a second semiconductor layer having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer, and a mobility larger than a mobility of the first semiconductor layer, the second semiconductor layer being strained; a third semiconductor layer having a valence band edge energy larger than the valence band edge energy of the second semiconductor layer, the third semiconductor layer being formed on the second semiconductor layer to form a heterojunction, and an insulating layer, wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the insulating layer are sequentially stacked, wherein a threshold voltage of a MOS transistor on the third semiconductor layer is controlled by an introduction of positive fixed charges introduced into and near an interface between the first semiconductor layer and the second semiconductor layer, an introduction of negative fixed charges into and near an interface between the second semiconductor layer and the third semiconductor layer and introduction of negative fixed charges into and near the interface between the third semiconductor layer and the insulating layer.