Patent ID: 6859028
Filing Date: 2005-02-22
Classification: G01R

Abstract:
1. A Phase-Locked Loop (PLL) integrated with testing apparatus comprising in a loop: i) a Phase-Frequency Detector (PFD), the PFD having first and second signal inputs, a test control input and an output, wherein the test control input is used to switch the PFD between a normal operating mode, in which the output delivers an output signal containing the phase and frequency difference between first and second signals applied respectively to the first and second signal inputs, and a transparent mode, in which only one of the first and second signal inputs is coupled to the output such that the corresponding signal is coupled through to the output unaltered; ii) a Voltage Controlled Oscillator (VCO), the VCO having an input and an output, the input of the VCO connected to the output of the PFD; iii) a frequency divider, the frequency divider having an input and an output, the input of the frequency divider connected to the output of the VCO; and iv) a first multiplexer (MUX), the first MUX having first and second signal inputs, a control input and an output, the output of the first MUX connected to the second signal input of the PFD, the first signal input of the first MUX connected to the output of the frequency divider, the second signal input coupled to receive a bias signal, and the control input coupled to receive a control signal; wherein the control signal coupled to the control input of the first MUX is set to select which one of the first and second signal inputs is coupled to the output of the first MUX.