Patent ID: 7495963
Filing Date: 2009-02-24
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: first and second cell arrays each having electrically rewritable and non-volatile memory cells arranged, memory cells in the main parts of the first and second cell arrays serving as information cells used for storing data, the remaining parts thereof serving as reference cells used for driving a reference current used for sensing data of the information cells; three or more bit line pairs disposed in the first and second cell arrays, each pair being constituted by first and second bit lines disposed in the first and second cell arrays, respectively; a sense amplifier so shared by the bit line pairs as to sequentially detect cell current differences between the information cells and the reference cells coupled to the bit line pairs; and first and second data latches arranged to store write data to be written into the first and second cell arrays, each number of the first and second data latches being equal to that of the bit line pairs, which share the sense amplifier and are simultaneously selected.