Patent ID: 8483344
Filing Date: 2013-07-09
Classification: H03L,H03M,H04L

Abstract:
1. A serializer-deserializer (SERDES) comprising: a clock-data recovery (CDR) block having an input data path sampled on both rising and falling edges of a recovered clock configured to output a relative phase relationship between the recovered clock and input data; a control (CTRL) block having a state machine configured to operate at an unstable point during initial convergence to an in phase condition when the state machine shifts to operating in a stable configuration; a low-pass filter (LPF) coupled between the CDR block and the CTRL block configured to accept single-bit pulses over an interval defined by a divide-by-N clock and output an OR-ed combination of N-bits to accomplish a filtering function; and a phase adjust (PA) block coupled between the CDR block and the CTRL block configured to control a phase adjustment function which aligns an input data sample with a phase controlled clock (sample clock).