Patent ID: 6470459
Filing Date: 2002-10-22
Classification: G06F

Abstract:
An interface circuit to interface data that is transmitted in half-word portions from a controller to a data user, comprising:a first half-word data input register for receiving a data word in sequential half-word portions, clocked by a first clock signal; at least second and third data registers, each clocked by said first clock signal, connected to sequentially receive said portions of said data word from said first data register; first and second data output registers, each clocked by a second clock signal at a frequency half that of said first clock signal, to deliver data therein to said data user; first and second multiplexers having outputs respectively connected to said first and second data output registers, and each having outputs from said first, second, and third registers connected to inputs thereof; and a controller to control said multiplexers to pass selected outputs from said first, second, and third registers, operative to determine in which of said three registers said data word portions are contained based upon the relative phase of said first and second clock signals with respect to the time that said data word was received.