Patent ID: 7626848
Filing Date: 2009-12-01
Classification: G11C

Abstract:
1. A memory device, comprising: a memory cell connecting to a local bit line, wherein the memory cell is composed of a pass transistor and a capacitor for configuring a dynamic random access memory; a tunable gain amp serving as a local sense amp, wherein the tunable gain amp includes a local pre-charge transistor pre-charging the local bit line to a pre-charge voltage, a local amplify transistor whose source is connected to a local amp voltage for tuning gain and whose gate is connected to the local bit line for reading the memory cell, a local amp enable transistor connecting to a drain of the local amplify transistor serially for enabling, and a write transistor connecting to the local bit line for receiving a write data from a global bit line; a global sense amp connecting to the local sense amp through the global bit line, wherein the global sense amp includes a read circuit, a latch circuit, a write circuit, and at least a select circuit, such that the read circuit reads the global bit line through the select circuit when reading, the latch circuit receives and stores an output from the read circuit or a pair of write data bus, the write circuit receives an output from the latch circuit and drives the global bit line through the select circuit when writing, and the global bit line is pre-set to a pre-set voltage by a global pre-set transistor of the select circuit when standby; a pre-charge voltage generator for generating the pre-charge voltage; a local amp voltage generator for generating the local amp voltage; a delay circuit as a locking signal generator for generating a delayed signal for disabling a global amp enable transistor of the read circuit when reading, wherein the delayed signal is generated by an output from the latch circuit.