Patent ID: 7605597
Filing Date: 2009-10-20
Classification: G01R,H01L

Abstract:
1. An arrangement for evaluating a fabrication of at least a partially-fabricated wafer, wherein the arrangement comprises: a circuit element provided within an active region of a die of the wafer; a power receiver provided in the active region of the die and connected to the circuit element, wherein the power receiver is configured to generate a power signal for the circuit element in response to receiving a power input; a test/trigger receiver provided in the active region of the die and connected to the circuit element, wherein the test/trigger receiver is configured to generate a trigger signal for the circuit element in response to receiving a signal input; wherein in response to receiving the power signal and the trigger signal, the circuit element is configured to exhibit an electrical activity that is detectable by a test probe without affecting a usability of a chip that is formed from the die, and wherein the electrical activity is indicative of one or more characteristics that are a result of the fabrication.