Patent ID: 6314015
Filing Date: 2001-11-06
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of bit lines;a plurality of virtual GND lines; anda plurality of memory cell transistors arranged in an array,wherein:the plurality of bit lines includes a selected bit line directly connected to a memory cell transistor to be read among the plurality of memory cell transistors and a plurality of non-selected bit lines,the plurality of virtual GND lines includes a selected virtual GND line directly connected to the memory cell transistor to be read and a plurality of non-selected virtual GND lines,the plurality of non-selected bit lines include a charge non-selected bit line to be charged and a non-selected dummy bit line to be grounded,the plurality of non-selected virtual GND lines include a charge non-selected virtual GND line to be charged, andthe grounded non-selected dummy bit line is connected between the selected virtual GND line and one of the charged charge non-selected bit lines and the charged charge non-selected virtual GND line.