Patent ID: 7665006
Filing Date: 2010-02-16
Classification: G11B

Abstract:
1. A block code error correcting system, which has an error correction code (ECC) block consisting of plural data entries arranged in rows and columns, the system comprising: a data slicer, which receives a radio frequency (RF) signal and samples the RF signal according to a sampling clock to thus produce a data bit to channel bit modulation signal; a data bit to channel bit modulation pulse width determinator, which is connected to the data slicer in order to detect a pulse width of the data bit to channel bit modulation signal to thus produce an erase control signal when the data bit to channel bit modulation signal is in a predefined window or the pulse width of the data bit to channel bit modulation signal is illegal; a demodulator, which is connected to the data bit to channel bit modulation pulse width determinator in order to receive and decode the data bit to channel bit modulation signal to thus produce a codeword; and an erase address detector, which is coupled to the data bit to channel bit modulation pulse width determinator and the demodulator in order to set the code word corresponding to the data bit to channel bit modulation signal as an erasure according to the erase control signal to thus output an erase address.