Patent ID: 6075731
Filing Date: 2000-06-13
Classification: G06F

Abstract:
A memory control circuit comprising:a CPU for executing a predetermined process;a first memory cell array storing data necessary for the predetermined process executed by said CPU;a first sense amplifier reading the data stored in the first memory cell array at a first equilibrium point between a read-""0"" operation and a read-""1"" operation;a write/read/erasure control circuit for controlling a data write operation, a data read operation and a data erasure operation in the first memory cell array;a second memory cell array having the same characteristic as said first memory cell array and storing predetermined data;a second sense amplifier for reading the data stored in said second memory cell at a second equilibrium point higher than the first equilibrium point so as to detect data dissipation;an interrupt control circuit for outputting to said CPU an interrupt signal for suspending the predetermined process executed by said CPU, when said second sense amplifier detects data dissipation;an automatic address generation circuit for successively generating addresses in said first memory cell array; anda memory overwrite control circuit for causing said automatic address generation circuit to generate the addresses in said first memory cell array when said second sense amplifier detects data dissipation, causing said write/read/erasure control circuit to overwrite each of the addresses generated by said automatic address generation circuit using data read from the same addresses by said first sense amplifier, canceling the interrupt signal provided by said interrupt control circuit, and resuming the predetermined process of said CPU.