Patent ID: 6376312
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method for fabricating an array of flash memory cells for a non-volatile memory device, wherein each flash memory cell of said array is comprised of a vertical field effect transistor formed by performing the steps of:A. forming a first drain or source contact structure comprised of a semiconductor material surrounded by shallow trench isolation structures; B. doping said first drain or source contact structure with a first dopant; C. depositing a bottom layer of doped insulating material on said first drain or source contact structure, said bottom layer of doped insulating material being doped with a second dopant; D. depositing a layer of dummy material on said bottom layer of doped insulating material; E. depositing a top layer of doped insulating material on said layer of dummy material, said top layer of doped insulating material being doped with a third dopant; F. etching an opening through said top layer of doped insulating material, said layer of dummy material, and said bottom layer of doped insulating material; wherein said opening is disposed over said first drain or source contact structure such that said opening has a bottom wall of said semiconductor material of said first drain or source contact structure; G. filling said opening with a semiconductor material to form a semiconductor fill contained within said opening; wherein said semiconductor fill has at least one side wall with a top portion of said at least one sidewall abutting said top layer of doped insulating material, and with a middle portion of said at least one sidewall abutting said layer of dummy material, and with a bottom portion of said at least one sidewall abutting said bottom layer of doped insulating material; H. implanting a fourth dopant into a top surface of said semiconductor fill to form a second drain or source contact junction of said vertical field effect transistor; I. etching away said layer of dummy material such that said middle portion of said at least one sidewall of said semiconductor fill is exposed; wherein a gate electrode opening disposed between said top and bottom layers of doped insulating material is formed when said layer of dummy material is etched away; J. forming a tunnel gate dielectric of said vertical field effect transistor on said exposed middle portion of said at least one side wall of said semiconductor fill; wherein said middle portion of said semiconductor fill abutting said tunnel gate dielectric forms a channel region of said vertical field effect transistor; K. filling said gate electrode opening between said top and bottom layers of doped insulating material with a floating gate electrode material, wherein said floating gate electrode material abuts said tunnel gate dielectric to form a floating gate electrode of said vertical field effect transistor; wherein said tunnel gate dielectric and said floating gate electrode formed at said at least one side wall of said semiconductor fill are disposed on a plurality of planes of said channel region of said vertical field effect transistor; L. performing a thermal anneal such that said second dopant diffuses from sail bottom layer of doped insulating material into said bottom portion of said semiconductor fill to form a first drain or source extension junction of said vertical field effect transistor, and such that said third dopant diffuses from said top layer of doped insulating material into said top portion of said semiconductor fill to form a second drain or source extension junction of said vertical field effect transistor; M. depositing a control gate dielectric material on any exposed surfaces of said floating gate electrode of said vertical field effect transistor to form a control gate dielectric on said floating gate electrode; N. depositing a control gate electrode material on said control gate dielectric material to form a control gate electrode on said control gate dielectric; O. patterning said control gate electrode material to be continuous for a row of said array of flash memory cells such that the control gate electrode of each vertical field effect transistor of said row of flash memory cells is coupled together to form a word line of said non-volatile memory device; P. patterning said semiconductor fill to be continuous for a column of said array of flash memory cells such that the second drain or source contact junction of each vertical field effect transistor of said column of flash memory cells is coupled together to form a bit line of said non-volatile memory device when said first drain or source contact structure of each vertical field effect transistor of said column of flash memory cells is electrically isolated; and Q. patterning said first drain or source contact structure to be continuous for a column of flash memory cells such that the first drain or source contact structure of each vertical field effect transistor of said column of flash memory cells is coupled together to form a bit line of said non-volatile memory device when the second drain or source contact junction of the semiconductor fill of each vertical field effect transistor of said column of flash memory cells is electrically isolated.