Patent ID: 8423939
Filing Date: 2013-04-16
Classification: G06F

Abstract:
1. A computer-implemented method of logic synthesis for adjusting a timing model of a circuit, the method comprising: providing the circuit, wherein the circuit includes a plurality of memory elements; determining a first memory element from the plurality of memory elements, wherein the first memory element is connected with a first portion of the circuit and is controlled by at least one first control signal, wherein the at least one first control signal includes at least one clock signal, one reset signal, one enable signal, or one power signal; determining at least one combinational element within the first portion of the circuit, wherein the at least one combinational element includes at least one input or output coupled with a second memory element of the plurality of memory elements, wherein the second memory element is controlled by at least one second control signal, wherein the at least one second control signal includes at least one clock signal, one reset signal, one enable signal, or one power signal and the at least one second control signal is incompatible with the at least one first control signal; inserting at least one first timing element into the circuit at a location connecting the at least one first timing element with the at least one combinational element, wherein timing properties of the at least one first timing element are related to a clock period of a memory element in a direction of a timing propagation, a number of levels of memory elements that lie between the location of the first memory element and the at least one combinational element, a latest arrival time at an input of the at least one first timing element, and an earliest required time at the output of the at least one first timing element; and performing, using a computer, a synthesis optimization of the circuit with the at least one first timing element inserted.