Patent ID: 6515889
Filing Date: 2003-02-04
Classification: G11C,H01L

Abstract:
A memory cell of a non-volatile memory device, the memory cell comprising:a ferroelectric layer formed overlying a substrate; a control gate formed overlying the ferroelectric layer and coupled to a word line; a first source/drain region having a first conductivity type formed in the substrate and coupled to a program line; a second source/drain region having the first conductivity type formed in the substrate; a channel region having the first conductivity type formed in the substrate and interposed between the first and second source/drain regions; and a diode interposed between the second source/drain region and a bit line; wherein another memory cell of the non-volatile memory device having a first source/drain region coupled to the program line further has a second source/drain region coupled to the bit line through an interposing diode.