Patent ID: 6083825
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method of fabricating an unlanded via hole on a semiconductor substrate, wherein a conductive layer, an anti-reflection coating (ARC) layer, and a patterned photoresist layer are sequentially formed on the substrate, the method comprising:defining the anti-reflection coating layer to form a patterned anti-reflection coating layer located at a center position of the conductive layer with a smaller width than that of the patterned photoresist layer using the patterned photoresist layer as a mask;defining the conductive layer to form a conductive line with a width approximately equal to that of the patterned photoresist layer using the patterned photoresist layer as a mask wherein a portion of the substrate is exposed by the conductive line;removing the patterned photoresist layer;forming a planarized dielectric layer over the substrate to cover the patterned anti-reflection coating layer and the conductive line; andforming a via hole in the planarized dielectric layer to expose portions of surfaces and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.