Patent ID: 6781406
Filing Date: 2004-08-24
Classification: G01R

Abstract:
An integrated circuit including logic for testing internal operation of the integrated circuit, the integrated circuit comprising:a plurality of internal functional blocks coupled by a plurality of internal buses, wherein the plurality of internal functional blocks and the plurality of internal buses are comprised in the integrated circuit; a set of test control input pins comprised on the integrated circuit; a set of test output pins comprised on the integrated circuit; and selection logic comprised in the integrated circuit, wherein the selection logic comprises: a plurality of inputs coupled to two or more of the plurality of internal buses; at least one select input coupled to receive select signals from the set of test control input pins; and an output coupled to the set of test output pins; wherein the selection logic is operable to select internal bus signals from one of the two or more internal buses based on the select signals from the test control input pins, wherein the selection logic is configured to output the selected internal bus signals to the set of test output pins; interface logic coupled between at least one of the plurality of inputs of the selection logic and at least one of the plurality of internal buses, wherein the interface logic is configured to buffer data from the at least one internal bus before the data is output to the set of test output pins.