Patent ID: 8073890
Filing Date: 2011-12-06
Classification: G06F,G11C,H03L

Abstract:
1. An event filter, comprising: a Gray code counter configured to increment and decrement through a Gray code sequence in response to the occurrence of an event, the Gray code sequence having a plurality of count values; and detection logic coupled to the Gray code counter and configured to detect a first one of the count values of the Gray code sequence, and in response to detecting the first count value, configured to generate a first active output signal and further configured to switch detection to a second one of the count values of the Gray code sequence, the detection logic further configured to generate a second active output signal and further configured to switch detection to the first one of the count values of the Gray code sequence in response to detecting the second count value, wherein the detection logic comprises a flip-flop configured to receive a detect signal as a clock and further configured to generate detect enable outputs corresponding to the first and second count values of the Gray code sequence, and wherein the detect enable outputs are combined with the Gray code count values at a combination of NAND and inverting gates for generating the detect signal.