Patent ID: 6815268
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of forming a gate in a FinFET device, comprising:forming a resist mask over a portion of a silicon on insulator (SOI) wafer, the SOI wafer comprising a silicon layer on an insulating layer; etching the silicon layer not covered by the resist mask to form a fin, the fin having a plurality of side surfaces and a top surface; forming a gate oxide on the plurality of side surfaces and the top surface of the fin; depositing a gate layer over the fin; depositing a dielectric layer over the gate layer; depositing a bottom anti-reflective coating (BARC) layer over the dielectric layer; forming a gate mask over the BARC layer; etching the BARC layer, the etching terminating on the dielectric layer; and etching the gate layer to form the gate.