Patent ID: 6535157
Filing Date: 2003-03-18
Classification: H03M

Abstract:
A cyclic redundant signed digit (RSD) analog to digital converter, comprising:an input terminal for receiving an analog input signal; a single RSD stage connected to the input terminal for receiving a selected one of the analog input signal and a residual voltage feedback signal and converting the one selected signal to a digital output signal, wherein the RSD stage also generates the residual voltage feedback signal and returns the residual voltage feedback signal directly back to an input of the single RSD stage; a first switch connected between the input terminal and the RSD stage for inputting the analog input signal to the RSD stage; and a feedback switch connected between the input of the single RSD stage and an output of the single RSD stage wherein when the feedback switch is closed, the first switch is open so that the residual voltage feedback signal is input to the single RSD stage, and when the first switch is closed, the feedback switch is open so that the analog input signal is input to the single RSD stage; the RSD stage comprising: a first comparator connected to the first switch for comparing the selected one of the analog input signal and the residual voltage feedback signal to a predetermined high voltage and providing a first comparator output signal; a second comparator connected to the first switch for comparing the selected one of the analog input signal and the residual voltage feedback signal to a predetermined low voltage and providing a second comparator output signal; and a logic circuit connected to the first and second comparator and receiving the first and second comparator output signals and generating the digital output signal based on the first and second comparator output signals.