Patent ID: 7984403
Filing Date: 2011-07-19
Classification: G06F

Abstract:
1. A computer-readable recording non-transitory medium storing a program causing a computer to perform: recording a DIRW matrix containing: possibly occurring state transitions among four states, Declare, Initialize, Read, and Write in a register included in a verification target circuit; and information on validity of paths according to the state transitions; acquiring a control data flow graph (CDFG) in which a dataflow graph (DFG) describing a data flow in a control flow graph (CFG) describing a control flow at implementation of the verification target circuit is written into the CFG; extracting, when an arbitrary register in the verification target circuit is designated as a verification target register, a DFG describing the verification target register from the CDFG; extracting a path indicative of a data flow in relation to the verification target register from the DFG; specifying a state transition of the verification target register included in the path, on the basis of the DFG; determining whether the state transition of the verification target register included in the path is set in the DIRW matrix; and deciding all the state transitions determined to be set in the DIRW matrix, as a coverage standard constituting a parent population in calculating verification coverage of the verification target register.