Patent ID: 8698224
Filing Date: 2014-04-15
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of nonvolatile memory cells each including, a MOS type first transistor section used for information storage, and a MOS type second transistor section which selects the first transistor section, wherein the first transistor section and the second transistor section are formed with an insulating region between gate electrodes thereof and adjacent to each other, wherein a channel region connected to channel regions of the first transistor section and the second transistor section is provided below the insulating region, wherein the second transistor section has a bit line electrode connected to a bit line, and a control gate electrode connected to a control gate control line, wherein the first transistor section has a source line electrode connected to a source line, a memory gate electrode connected to a memory gate control line, and a charge storage region disposed directly below the memory gate electrode, wherein the bit line electrode is electrically coupled to a transfer transistor which controls a connection between a nonvolatile memory cell and a sense amplifier which detects the information of the nonvolatile memory cell, wherein a gate insulating film thickness of the second transistor section is less than that of the first transistor section, and wherein a gate insulating film thickness of the transfer transistor is lower than that of the first transistor section.