Patent ID: 9053264
Filing Date: 2015-06-09
Classification: G06F

Abstract:
1. A method comprising: receiving, at one or more computer systems, a design coding in HDL (Hardware Description Language); receiving, at the one or more computer systems, a simulation result corresponding to a simulation performed with the design, wherein the simulation result comprises signal values of signals, a changed time of the respective signal value, and an event sequence order for the changed time of the respective signal value; receiving, at the one or more computer systems, a what-if design scope and a what-if time window; extracting, with one or more processors associated with the one or more computer systems, a portion of the design according to the what-if design scope to generate a sub-design; determining, with the one or more processors associated with the one or more computer systems, primary input signals of the sub-design; extracting, with the one or more processors associated with the one or more computer systems, what-if simulation data from the simulation result according to the primary input signals and the what-if time window, wherein the what-if simulation data comprises the signal values of the primary input signals within the what-if time window, the changed time of the respective signal value, and the event sequence order for the changed time of the respective signal value; and generating, with the one or more processors associated with the one or more computer systems, a what-if test bench according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are input to a simulator according to the what-if test bench.