Patent ID: 9105336
Filing Date: 2015-08-11
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a cell array including bit lines and source lines intersecting each other, a cell string in which a plurality of memory cells disposed between the bit lines and the source lines is connected in series, each of the memory cells including a control gate and a charge storage layer, and word lines connected respectively to the control gates of the memory cells of the cell string; and a data writing unit that repeatedly executes, during writing of data, a write loop including a programming operation of applying a program voltage to a selected word line of the word lines, and applying a passage voltage to any one of non-selected word lines of the word lines, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ΔVn and when a condition of L<M (L and M are integers) is satisfied, the data writing unit executing the write loop using the passage voltage satisfying ΔV(L−1)<ΔVL, ΔVL ΔV(M−1), and ΔV(M−1)<ΔVM.