Patent ID: 6751159
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode; a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address; a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being coupled to receive the mode select signal and an array select signal, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.