Patent ID: 6415405
Filing Date: 2002-07-02
Classification: H03K

Abstract:
A scannable logic apparatus, comprisinga scan control circuit that generates scan control signals; one or more scan registers; one or more read/write drivers coupled to said scan registers; and a network of clocked precharge logic, said network further comprises a plurality of sequentially clocked precharge logic gates and one or more scan gates, each said clocked precharge logic gate and scan gate further comprises a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers, each said scan gate further comprises a scan circuit that accepts said scan control signals and couples to one or more of said scan registers, each said clocked precharge logic gate and scan gate receives one or more clock signals and one or more input signals and produces one or more output signals, said clocked precharge logic gates and scan gates are coupled together such that an output signal of each said clocked precharge logic gate comprises an input signal to the next clocked precharge logic gate or scan gate, and an output signal of each said scan gate comprises an input signal to the next clocked precharge logic gate.