Patent ID: 8558601
Filing Date: 2013-10-15
Classification: G09G

Abstract:
1. A gate driving circuit comprising: a first clock generator to sequentially output n (n being a natural number equal to or greater than 2) output clock pulses having different phases in a circulating manner; a second clock generator to sequentially output n output control clock pulses having different phases in a circulating manner; and a shift register to receive the n output clock pulses from the first clock generator and the n output control clock pulses from the second clock generator and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th (s being a natural number greater than 1) output clock pulses output during adjacent periods overlap with one another for a predetermined time, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k−a)-th (a being a natural number less than k) output clock pulse, a high section of at least one of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th (b being a natural number) output clock pulse falls during the high section of the at least one of the output control clock pulses not overlapping with that of the k-th output clock pulse.