Patent ID: 7560306
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A manufacturing process for chip package, comprises: providing a conductive layer with a first surface and a second surface; forming a solder resistance layer on the first surface and patterning the solder resistance layer and exposing parts of the conductive layer; forming a film onto the solder resistance layer; patterning the conductive layer and forming a patterned circuit layer; disposing a chip onto the second surface, wherein the chip covers at least parts of the conductive layer, the chip has a plurality of conducting wires, the plurality of conducting wires passes through the patterned circuit layer and contacts to the first surface, and the chip electrically connect to the patterned circuit layer by the plurality of conducting wires; forming a molding compound to cover the patterned circuit layer and fix the chip onto the patterned circuit layer; and removing the film.