Patent ID: 7505345
Filing Date: 2009-03-17
Classification: G11C

Abstract:
1. An SRAM circuit, comprising: a plurality of static memory storage cells arranged in a column and each coupled to a word line from a plurality of word lines arranged in rows; a pair of complementary bit lines coupled to the plurality of static memory storage cells for transmitting differential data signals to and from the static memory storage cells; a differential sensing amplifier having a pair of differential inputs each coupled to one of the pair of complementary bit lines and operable for sensing the differential voltage between the differential inputs; input/output data lines for transmitting and receiving data from the sense amplifier in response to control signals; and word line decoder circuitry for outputting a pulse on a selected one of the word lines in response to decoding an address, the word line decoder circuitry further comprising word line suppression circuitry for selectively lowering the voltage on the word line by a predetermined amount during a first phase of a pulse on the word line, and for releasing the word line allowing the word line to rise to a higher voltage during a second phase of the a pulse on the word line.