Patent ID: 7983103
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a package that includes a first pseudo-SRAM chip and a second pseudo-SRAM chip, wherein each of the first pseudo-SRAM chip and the second pseudo-SRAM chip comprises: a memory array having memory cells of a plurality of dynamic random access memories arranged in rows and columns; a first circuit producing a first signal defining timing of refreshing; an output terminal outputting said first signal; an input terminal receiving a second signal externally defining the timing of the refreshing; a switch receiving said first and second signals, and outputting one of said first and second signals; a second circuit receiving the signal output from said switch, and performing refresh control based on the received signal; and a wait control circuit outputting a wait signal while said second circuit is executing the refresh control; the package further comprising: a wait terminal that provides an external output for the package of at least one of an output of the wait control circuit of the first pseudo-SRAM chip and an output of the wait control circuit of the second pseudo-SRAM chip.