Patent ID: 6209109
Filing Date: 2001-03-27
Classification: H03M

Abstract:
A code synchronization decision circuit of a Viterbi decoder comprising:an error counter for counting a number of errors of symbols over a fixed interval;a symbol counter for counting a number of symbols over the fixed interval;a trigger signal generator for producing a trigger signal every time said symbol counter counts up to a number of symbols which is externally set;a comparator for comparing, in response to the trigger signal supplied from said trigger signal generator, the number of errors counted by said error counter with a predetermined number of errors which is externally set, and for producing one of a synchronization signal indicating that code synchronization is established and a slip signal indicating that the code synchronization is not established; anda masking signal generator for generating a masking signal for suspending operation of said error counter and said symbol counter during a time period in which a code unsuitable as an input for counting said number of errors will be supplied.