Patent ID: 7015727
Filing Date: 2006-03-21
Classification: H03D,H03L

Abstract:
1. A lock detector block for detecting whether an output clock signal is locked to an input reference signal, said lock detector block comprising: a first sampling circuit receiving an up signal as an input and being clocked by a down signal, wherein said up signal indicates that the frequency of said output clock signal is to be increased and said down signal indicates that the frequency of said output clock signal is to be reduced to lock said output clock signal to said input reference clock signal, said first sampling circuit generating a first output indicating whether said output clock signal is out-of-lock; a second sampling circuit receiving said down signal as an input and being clocked by said up signal, said second sampling circuit generating a second output indicating whether said output clock signal is out-of-lock; an examining circuit receiving said first output and said second output, and generating a signal indicating that said output clock signal is locked to said input reference signal if both said first output and said second output indicate that said output clock signal is not out-of-lock; and wherein said examining circuit comprises a NOR gate, said first sampling circuit comprises a first flip-flop and said second sampling circuit comprises a second flip-flop.