Patent ID: 8775492
Filing Date: 2014-07-08
Classification: H03H

Abstract:
1. A decimation filter circuit configured to convert a digital input sequence into a digital output sequence, the decimation filter circuit comprising: an integrator circuit stage comprising a plurality of closed-loop controlled time-delay elements, wherein the integrator circuit stage is arranged on an input side of the decimation filter circuit; and a further circuit stage, wherein the further circuit stage is arranged on an output side of the decimation filter circuit, wherein the integrator circuit stage operates at a higher clock frequency than the further circuit stage, wherein the further circuit stage comprises, on the input side, a weighting network and, on the output side, a time-delay element network comprising at least one time-delay element, wherein output signals from the integrator circuit stage are fed on the input side to the weighting network and output signals of the weighting network are fed on the input side to the time-delay element network, wherein the time-delay of each of the time-delay elements of the integrator circuit stage is equal to the time-delay of each of the at least one time-delay element of the further circuit stage.