Patent ID: 6775171
Filing Date: 2004-08-10
Classification: G11C,H01L

Abstract:
A method for utilizing one or more voltage gradients to guide dielectric breakdown in a non-volatile memory cell integratable with other CMOS circuitry, comprising:providing an antifuse element having a programming node, the antifuse element being configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses, the change in resistivity representing a change in logic state, wherein the antifuse element comprises a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to the one or more voltage pulses; coupling a capacitor element to the programming node of the antifuse element, the capacitor element being configured to provide the one or more voltage pulses to the programming node; and forming the one or more voltage gradients within the antifuse element to guide a location for breakdown to occur within the dielectric layer.