Patent ID: 6031392
Filing Date: 2000-02-29
Classification: H03K

Abstract:
A circuit comprising:a transistor-transistor logic (TTL) stage comprising:a first load having a first terminal and a second terminal, said first load having a first voltage drop across said first terminal and said second terminal when a control voltage is applied to said first terminal;a first transistor having a control terminal electrically coupled to a reference voltage, said first transistor having a first current carrying terminal and a second current carrying terminal, said first current carrying terminal of said first transistor being electrically coupled to said second terminal of said first load;a second load electrically coupled in series between said second current carrying terminal of said first transistor and a negative voltage;a third load having a first terminal, electrically coupled to said reference voltage, and a second terminal, said second current carrying terminal providing an output of said TTL stage; anda second transistor having a control terminal electrically coupled to said second current carrying terminal of said first transistor, said second transistor having a first current carrying terminal electrically coupled to said second terminal of said third load and having a second current carrying terminal electrically coupled to said negative voltage.