Patent ID: 7075333
Filing Date: 2006-07-11
Classification: H03K

Abstract:
1. An integrated circuit, comprising: an interconnect structure; and a plurality of programmable circuits coupled to the interconnect structure, each programmable circuit comprising: a function select memory cell; a plurality of first memory cells; a plurality of function select multiplexers each having a first data input terminal coupled to one of the first memory cells, a second data input terminal coupled to the interconnect structure, a select terminal coupled to the function select memory cell, and an output terminal; a first multiplexer having a plurality of data input terminals coupled to the output terminals of the function select multiplexers, a plurality of select terminals coupled to the interconnect structure, and an output terminal coupled to the interconnect structure; and an input multiplexer coupled between the interconnect structure and the second data input terminals of the function select multiplexers.