Patent ID: 8996953
Filing Date: 2015-03-31
Classification: G06F,H03M

Abstract:
1. A system for monitoring a first Error Correcting Code (ECC) module for failure and replacing a first ECC module with a second ECC module if the first ECC module fails, the system comprising: an ECC system comprised of the first ECC module and the second ECC module that independently perform ECC; logic to count correctable errors detected by the first ECC module and by the second ECC module in data that is read from a memory; logic to detect an uncorrectable error by the first ECC module and by the second ECC module in data that is read from memory; logic to perform a first loopback test that replaces an input to the first ECC module with an output from the first ECC module; logic to perform a second loopback test that replaces an input to the second ECC module with an output from the second ECC module; logic to detect a failed first ECC module with the first loopback test; logic to detect a failed second ECC module with the second loopback test; logic to replace the first ECC module with the second ECC module in the ECC system; wherein the system is operable to: