Patent ID: 8618641
Filing Date: 2013-12-31
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a leadframe comprising a die pad and a plurality of leads surrounding the die pad, the die pad having a top surface and an opposing bottom surface, and an opening being formed in the die pad; a carrier mounted to the bottom surface of the die pad, wherein a plurality of connecting pads are formed on the carrier, and a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on a top surface of the carrier to be exposed from the die pad, wherein the leads are entirely located outside a vertical-forward projected area of the carrier, and the leads are free from being located inside the vertical-forward projected area of the carrier and free from contacting the carrier; at least a semiconductor chip attached to a side of an assembly comprising the die pad and the carrier, and electrically connected to the connecting pads of the carrier and the leads of the leadframe via bonding wires, wherein the semiconductor chip is placed in the opening of the die pad; and a package encapsulant encapsulating the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.