Patent ID: 8402353
Filing Date: 2013-03-19
Classification: H03M,H04L

Abstract:
1. A cyclic code processing circuit which calculates an input data remainder which is a remainder produced when input data are divided by a generator polynomial, said input data comprising a plurality of successive bits arranged in parallel so that a parallel width of said input data is set to a predetermined value, and said input data includes an integral multiple data block, which is made up of bits included in words other than a final word located at a tail end of said input data, and a final word valid data block, which is made up of bits in said final word, and said integral multiple data block comprising a plurality of words that are successively divided by the generator polynomial, from a leading end of said input data with respect to every word which comprises bits represented by said predetermined value, said cyclic code processing circuit comprising: an integral multiple data block remainder calculating unit that calculates an integral multiple data block remainder which is a remainder produced when said integral multiple data block is divided by said generator polynomial for every said word; a final word valid data block remainder calculating unit that calculates a final word valid data block remainder which is a remainder produced when said final word valid data block made up of bits included in said final word of said input data is divided by said generator polynomial; and an input data remainder calculating unit that calculates said input data remainder based on the calculated integral multiple data block remainder and the calculated final word valid data block remainder, wherein said input data remainder calculating unit calculates said input data remainder by adding a product and said final word valid data block remainder, said product being obtained by multiplying, by said integral multiple data block remainder, a remainder computing coefficient which is a remainder produced by dividing, by said generator polynomial, a polynomial that only has terms of powers which have, as an exponent, the number of bits that make up said final word valid data block.