Patent ID: 6127211
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A method of manufacturing a transistor by ionizing at least one impurity element into plural types of impurity ions having different projected ranges and different scatterings before stopping, and different distributions in a direction vertical to a depth direction below a mask after projecting, accelerating the impurity ions with a voltage, and implanting the accelerated impurity ions into a semiconductor region comprising a semiconductor layer formed on a substrate, a gate insulating layer formed over said semiconductor layer, and a gate electrode formed on said gate insulating layer, said method comprising:forming a gate-electrode on the gate insulating layer, the gate electrode having a thickness determined by the projected ranges of the implanted impurity ions, said gate electrode also serving as a mask during ionizing at least one impurity element into plural types of impurity ions, accelerating the impurity ions with a voltage and implanting the accelerated ions;mixing a plurality of compounds of the impurity element to produce a source gas;supplying the source gas to an ionization chamber;ionizing the source gas; andsupplying specific kinetic energy to the impurity ions derived from the source gas and thereby doping the impurity ions into the semiconductor region on the substrate to form a source or drain region and an LDD region near the source or drain region below the mask.