Patent ID: 6683335
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A semiconductor integrated circuit comprising:a semiconductor substrate; at least one n-type region formed in said semiconductor substrate; at least one p-type region formed in said semiconductor substrate; an element separation region disposed in said semiconductor substrate between one of said n-type regions and one of said at least one p-type region; a set of p-type transistors arranged in said n-type region adjacently in a first direction, said set of p-type transistors having gates oriented along a second direction perpendicular to said first direction; a set of n-type transistors adjacently arranged in said p-type region in said first direction, each of said n-type transistors having a gate oriented along said second direction; and a set of contacts formed on said element separation region, each of said contacts being connected to one of the gate of a p-type transistor and the gate of an n-type transistor, wherein said set of contacts includes a set of extended contacts, each of said extended contacts extending along said second direction and thence along said first direction so that a given extended contact connected to a given transistor has a portion disposed between (1) a first contact connected to a transistor adjacent to said given transistor and the like polarity and (2) a second contact connected to a transistor of opposite polarity, said portion, said first contact and said second contact being collinear with respect to the second direction.