Patent ID: 7816712
Filing Date: 2010-10-19
Classification: H01L

Abstract:
1. A thin film transistor array, comprising: a pixel electrode defined as part of a transparent conductive layer disposed on a substrate, where the substrate has plural layers stacked thereon and the transparent conductive layer is one of the plural stacked layers; a gate line having a first portion defined as part of the transparent conductive layer and having a second portion defined as part of an opaque conductive layer disposed on the substrate, where the opaque conductive layer is one of said plural stacked layers; a gate electrode connected to the gate line and having a first portion defined as part of the transparent conductive layer and having a second portion defined as part of an opaque conductive layer disposed on the substrate; a gate insulating layer which covers the gate line and covers the gate electrode but which does not substantially cover the pixel-electrode; a semiconductor layer comprised of an impurity-doped amorphous silicon and formed on the gate insulating layer to overlap the gate electrode; a data line which intersects the gate line; a source electrode connected to the data line to overlap a part of the semiconductor layer; and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.