Patent ID: 6525783
Filing Date: 2003-02-25
Classification: H04N

Abstract:
A video decoding system comprising:a variable length decode (VLD) processing unit receiving and variable length decoding an input bit stream, said VLD processing unit obtaining and outputting discrete cosine transform (DCT) coefficients and information on locations of the DCT coefficients in a DCT block, wherein the DCT coefficients are outputted without performing a run-level decoding by the VLD processing unit; an inverse quantizer (IQ) dequantizing the DCT coefficient according to the location information of the DCT coefficients; an inverse scanner (IS) inverse scanning the dequantized DCT coefficients output from the (IQ); an inverse discrete cosine transform (IDCT) unit inverse discrete cosine transforming of the inverse scanned DCT coefficients output from the IS; a motion compensation unit decoding motion vectors output by the VLD processing unit, performing half pel prediction according to the decoded motion vectors, and interpolating the half pel predicted data; a display unit reconstructing a picture by combining the output from the IDCT unit with the output from the motion compensation unit and outputting the picture; a frame memory storing input bit stream, data for motion compensation, decoded data, and data to be displayed; and a memory controller controlling memory requests from the VLD processing unit, the motion compensation unit, and the display unit for writing to and reading from the frame memory.