Patent ID: 7475374
Filing Date: 2009-01-06
Classification: G06F

Abstract:
1. An integrated circuit, comprising: a clock grid coupled to a plurality of clocked elements, wherein the clock grid comprises a plurality of conductive traces configured to distribute a clock signal to the plurality of clocked elements, wherein operation of the clocked elements is synchronized according to the distributed clock signal; and a clock tree comprising a plurality of tiers of clock buffers, wherein a final tier of the plurality of tiers of clock buffers comprises a plurality of leaf buffers coupled to the clock grid; and wherein the clock tree is configured to distribute the clock signal to the plurality of conductive traces of the clock grid, wherein an output of at least one of the plurality of leaf buffers is split into a plurality of signal paths, wherein each of the plurality of signal paths is coupled to one or more of the plurality of clock grid traces at a respective distinct location, wherein each respective distinct location serves as a virtual driver of the clock signal to the clock grid at that distinct location.