Patent ID: 7642125
Filing Date: 2010-01-05
Classification: H01L

Abstract:
1. A method for manufacturing an array of memory cells, comprising: forming a separation layer on a substrate having an array of contacts; forming an isolation layer on the separation layer over the array of contacts, the isolation layer including material having etching characteristics different than the separation layer; forming an array of memory element openings in the isolation layer over the array of contacts using a patterning process; forming etch masks within the memory element openings in the array of openings; etching through the separation layer using the etch masks to define an array of electrode openings exposing corresponding contacts in the array of contacts; forming electrodes in the electrode openings to form an array of bottom electrodes contacting corresponding contacts in the array of contacts, the bottom electrodes being self-aligned with and centered on respective openings in the array of memory element openings; forming memory elements within the array of memory element openings over the array of bottom electrodes, the memory elements comprising programmable resistive material, wherein said memory elements have bottom surfaces which have bottom surface areas and the bottom electrodes have top surfaces with surface areas substantially smaller than the bottom surface areas of the corresponding memory elements; and forming top electrodes in contact with the memory elements.