Patent ID: 6771532
Filing Date: 2004-08-03
Classification: G06F,G09G

Abstract:
In an integrated circuit having a logic portion having at least 30K logic gates and a memory portion coupled to said logic portion, said memory portion having a capacity of at least 2 megabits, a capacitor comprisinga first dopant-type transistor in a second dopant-type well in a first dopant-type semiconductor substrate, said first dopant-type transistor having a gate, first and second source/drains, said first source/drain connected in common to said second source/drain to form a first terminal of said capacitor, said gate forming a second terminal of said capacitor, said second dopant-type well connected to a first voltage supply line, and said substrate connected to a second voltage supply line, different voltages applied to said first voltage supply line and to said second voltage supply line, such that the semiconductor junction between said second dopant-type well and said substrate is reverse-biased; whereby said capacitor is isolated from electrical noise in said substrate.