Patent ID: 6989602
Filing Date: 2006-01-24
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first metal feature located on a semiconductor surface; a first etch stop layer located on the first metal feature; a first interlevel dielectric layer located on the first etch stop layer; a second etch stop layer located on the first interlevel dielectric layer; a second interlevel dielectric layer located on the second etch stop layer; an unsegmented via located through the first and second etch stop layers and interlevel dielectric layers, the unsegmented via extending to and contacting the first metal feature and being void of a landing pad between the first and second interlevel dielectric layers; a second metal feature located adjacent the unsegmented via and extending through the second interlevel dielectric layer and the second etch stop layer and terminating at the first interlevel dielectric layer; and a dual damascene structure adjacent the second metal feature and having a damascene trench portion extending through the second interlevel dielectric layer and the second etch stop layer and terminating at the first interlevel dielectric layer and further including a damascene via portion extending through the first interlevel dielectric layer and the first etch stop layer and connecting the trench portion to the first metal feature.