Patent ID: 6023751
Filing Date: 2000-02-08
Classification: G06F

Abstract:
A method of evaluating Boolean expressions and predicates in a computer system having a processor with an instruction unit for decoding instructions of an instruction set, a functional unit for executing operations specified in the decoded instructions, and a set of registers, the method comprising the steps of:decoding instructions of a program in the instruction unit, the program's instructions being selected from the instruction set;executing operations specified by the decoded instructions in the functional unit, the executing of a corresponding reduction operation specified by one of the decoded instructions in any one of the at least one functional unit comprising the steps of:retrieving at least one instruction-specified input value for the reduction operation;producing a Boolean result value having a first instruction-specified state;performing an instruction-specified condition function of one or more of the input values of the operation to produce a Boolean condition value, wherein the Boolean condition value is false for at least one combination of the input values; andconditionally writing the result value in an instruction-specified location in the set of registers if the Boolean condition value is a second instruction-specified state.