Patent ID: 7851262
Filing Date: 2010-12-14
Classification: H01L

Abstract:
1. A manufacturing process for a chip package structure, comprising: providing a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer; bonding a plurality of chips onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer; electrically connecting the chips to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer; forming at least one molding compound to encapsulate the patterned conductive layer, the chips and the bonding wires; and separating the molding compound, the patterned conductive layer and the patterned solder resist layer.