Patent ID: 6628560
Filing Date: 2003-09-30
Classification: G11C

Abstract:
A dynamic semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in rows and columns; a memory cell selector circuit selecting a memory cell to be refreshed in said memory cell array; and a refresh control circuit supplying a first address signal to said memory cell selector circuit for a normal operation, said first address signal corresponding to an externally supplied address, and supplying a second address signal to said memory cell selector circuit for a refresh operation, said second address signal generated according to a refresh signal, said refresh control circuit including an oscillator circuit, a first storage circuit storing a first control value, a divider circuit dividing an output frequency from said oscillator circuit based on said first control value to generate said refresh signal, a second storage circuit storing a second control value, a first comparator circuit comparing said second control value with the number of times an output from said divider circuit is activated, and a divisor change circuit increasing said first control value by a predetermined value according to an output from said first comparator circuit.