Patent ID: 7390719
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device having a dual gate structure, the method comprising: providing a semiconductor substrate having a first area and a second area; forming a dielectric layer on the semiconductor substrate; forming a first metallic conductive layer on the dielectric layer to a first thickness; annealing the first metallic conductive layer to reduce an etching rate of the first metallic conductive layer; forming a second metallic conductive layer on the annealed first metallic conductive layer to a second thickness greater than the first thickness, so that the second metallic conductive layer has an etching selectivity relative to the annealed first metallic conductive layer; as a function of the etching selectivity, etching the second metallic conductive layer from the annealed first metallic conductive layer in the second area of the substrate, while maintaining the second metallic conductive layer on the annealed first metallic conductive layer in the first area of the substrate; forming a first gate structure including a first metallic gate on the first area of the substrate and a second gate structure including a second metallic gate on the second area of the substrate, wherein the first metallic gate includes the annealed first metallic conductive layer and the second metallic conductive layer and the second metallic gate includes the annealed first metallic conductive layer.