Patent ID: 6190958
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A fully self-aligned method for fabricating a transistor, comprising the steps of:providing a semiconductor substrate;forming a first dielectric layer on the substrate;simultaneously forming a plurality of source/drain region contact openings and word line trenches on the first dielectric layer by patterning the first dielectric layer;forming a doped conductive layer in the source/drain contact openings and word line trenches to form a plurality of source/drain conduct plugs and first gate conductive layers, respectively;removing the first gate conductive layers to expose the substrate;performing a thermal oxidation to form a gate oxide layer on the exposed substrate and to form a plurality of source/drain regions at the interface between the source/drain contact openings and substrate;forming a second conductive layer in the word line trenches to form a plurality of second gate conductive layers on the gate oxide layer, wherein the second gate conductive layers have a height less than a depth of the word line trenches; andforming an insulation layer on the substrate and filling the word line trenches.