Patent ID: 7791381
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. A semiconductor integrated circuit comprising: a clock tree circuit for delay-adjusting a clock signal transmitted through a clock path using various delay amounts; and a clock synchronizing circuit to which the clock signal delay-adjusted by the clock tree circuit is supplied, wherein the clock tree circuit comprises: a first clock tree cell provided in a poststage of a clock signal introducing terminal in the clock path; a second clock tree cell provided in a prestage of the clock synchronizing circuit and a poststage of the first clock tree cell in the clock path; and a clock ramification point provided in a prestage of the second clock tree cell and a poststage of the first clock tree cell in the clock path, wherein the clock synchronizing circuit comprises: a first clock synchronizing circuit to which the clock signal delay-adjusted by the second clock tree cell and thereafter outputted from the clock tree circuit is supplied; and a second clock synchronizing circuit to which the clock signal not delay-adjusted by the second clock tree cell after delay-adjusted by the first clock tree cell and outputted from the clock tree circuit at the clock ramification point is supplied, wherein the clock ramification point and the second clock synchronizing circuit are connected to each other without the clock tree circuit interposed therebetween.