Patent ID: 8352753
Filing Date: 2013-01-08
Classification: G01R,G06F

Abstract:
1. A microcontroller comprising: a microprocessor, a test interface and an internal non-erasable memory; first control means within the microcontroller to activate and deactivate the test interface, the first control means comprising a register bit memory cell having a write input connected to a control output of the microprocessor and a read output coupled to a control input of the test interface; and second control means within the microcontroller to activate and deactivate the internal non-erasable memory, the second control means comprising a register bit memory cell having a write input connected to another control output of the microprocessor and a read output coupled to a control input of the internal non-erasable memory; wherein the microprocessor comprises control outputs which are coupled to the first and second control means, such that the test interface and the internal non-erasable memory can be activated and deactivated by the microprocessor.