Patent ID: 6970017
Filing Date: 2005-11-29
Classification: H03K

Abstract:
1. A flip-flop circuit comprising: first and second data input ports; first to third nodes; a first transmission gate connected between the first data input port and the first node; a second transmission gate connected between said second data input port and said first node; a first latch circuit having an input node connected to the first node and an output node connected to the second node; and a third transmission gate connected between the second node and the third node; wherein the first to third transmission gates are controlled by a reference signal and inputs to the first and second transmission gates are inhibited complementarily, wherein the first latch circuit includes a first inverter and a second inverter, wherein an input node of the first inverter is connected to the first node and an output node of the second inverter, wherein an output node of the first inverter is connected to an input node of the second inverter, and wherein the second inverter is a tristate inverter.