Patent ID: 8930156
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method for metrology during semiconductor device fabrication, comprising: a) Modeling, with a data processing system, metrology parameters of a first measurement on a first test cell formed in a layer of a partially fabricated device; b) Performing, with a metrology tool, a second measurement on a second test cell in the layer during fabrication of a semiconductor device; c) feeding information obtained from performing the second measurement into the modeling of the metrology parameters of the first measurement, with the data processing system; and d) after a lithography pattern has been formed on the layer with a lithography tool, the lithography pattern including the first and second test cells, modeling, with a data processing, system metrology parameters of a third measurement and metrology parameters of a fourth measurement on the first and second test cells, respectively, using information obtained from performing the first measurement and performing the second measurement, respectively.