Patent ID: 8796098
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A method comprising: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate, a charge-trapping layer on the tunneling dielectric, a cap layer on the charge-trapping layer and a sacrificial oxide on the cap layer; patterning the dielectric stack to form a gate stack of a non-volatile memory (NVM) transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; performing a gate oxidation (GOX) preclean to remove the sacrificial oxide and at least a top portion of the cap layer from the gate stack of the NVM transistor while concurrently removing a pad oxide from the second region of the substrate, wherein the top portion of the cap layer comprises an oxygen rich composition relative to a bottom portion of the cap layer to facilitate removal of the top portion of the cap layer; and performing a gate oxidation process to form a gate oxide of a metal-oxide-semiconductor (MOS) transistor overlying the substrate in the second region while concurrently oxidizing the bottom portion of the cap layer to form a blocking oxide overlying the charge-trapping layer.