Patent ID: 6151282
Filing Date: 2000-11-21
Classification: G11B

Abstract:
A clock matching apparatus which supplies a clock signal to a sampler of a data reproduction system so that a readout signal obtained from a storage medium is sampled periodically at sampling instants synchronized with the clock signal, in order to recover written information in the data reproduction system, including:a phase error detection unit which detects a phase error of the clock signal based on the samples of the readout signal output by the sampler; anda phase-locked loop which supplies a phase-matched clock signal to the sampler by compensating for the phase error detected by the phase error detection unit,the phase error detection unit comprising:an edge detection unit which detects a sampling instant for an edge sample among the samples of the readout signal; anda difference unit which generates a difference in timing phase between the edge sample and a sync level, the sync level being a reference signal level corresponding to a level of the readout signal at the sampling instants thereof and defined based on a partial-response waveform, the difference in the timing phase being output to the phase-locked loop as the detected phase error.