Patent ID: 8357610
Filing Date: 2013-01-22
Classification: H01L

Abstract:
1. A method, comprising: forming a via opening in a low-k dielectric layer formed above a substrate of a semiconductor device; forming a protection layer on exposed surface portions of said low-k dielectric layer, said protection layer covering an upper surface of said low-k dielectric layer and sidewall surfaces of said via opening; forming a planarization material on said protection layer, said planarization material filling said via opening and covering said upper surface of said low-k dielectric layer; forming a trench opening in said planarization material formed above said upper surface of said low-k dielectric layer while removing a first portion of said planarization material from said via opening, wherein said trench opening is positioned above said via opening; and forming a trench in said low-k dielectric layer on the basis of said trench opening in said planarization material.