Patent ID: 6028788
Filing Date: 2000-02-22
Classification: G11C

Abstract:
A flash memory device having a first, a second, and a third string block arranged in a two-dimensional manner for constructing a memory cell array, each string block having a bit line contact and a source line contact, the flash memory device comprising:a plurality of strings within each string block, each string having a first end and a second end;a bit line select transistor having a gate disposed along each string;a plurality of memory cells disposed along each string, each memory cell having a control gate;a plurality of source line select transistors disposed along each string, each source line select transistor having a gate, the bit line select transistor, the unit memory cells and the source line select transistors being connected to each other in series;a bit line select line being connected to the gate of the bit line select transistor;a plurality of word lines, each word line being connected to the control gate of one of the memory cells in each string;a plurality of source line select lines, each source line select line being connected to the gate of one of the source line select transistors in each string;a first dual-mode line being connected to the first end of each of the strings in the first string block through the bit line contact thereof and being further connected to the source line contact of the second string block; anda second dual-mode line being connected to the second end of each of the strings in the first string block through the source line contact thereof and being further connected to the bit line contact of the third string block.