Patent ID: 6448165
Filing Date: 2002-09-10
Classification: H01L,Y10S

Abstract:
A method for fabricating a field effect transistor within an active device area of a semiconductor substrate, the method including the steps of:A. depositing a layer of gate dielectric material on said semiconductor substrate; B. depositing a layer of gate electrode material on said layer of gate dielectric material, said gate electrode material being a semiconductor material; C. implanting one of an N-type dopant or a P-type dopant into said layer of gate electorde material such that said one of an N-type dopant or a P-type dopant has a dopant concentration in said layer of gate electrode material, and adjusting said dopant concentration of said one of N-type or P-type dopant with a dopant dose of said N-type or P-type dopant during said step C of implanting said one of N-type or P-type dopant in said gate electrode material to modify an etch rate of said gate electrode material in an etching reactant for etching BARC (bottom anti-reflective coating) material; D. depositing a layer of BARC (bottom anti-reflective coating) material on said layer of gate electrode material; E. depositing a layer of photo-resist material and patterning said layer of photo-resist material, said layer of BARC (bottom anti-reflective coating) material, and said layer of gate electrode material to form a gate structure of said field effect transistor, said gate structure being comprised of said gate electrode material; wherein said BARC (bottom anti-reflective coating) material remains on said gate structure; F. removing said photo-resist material from said BARC (bottom anti-reflective coating) material remaining on top of said gate structure; G. stripping said BARC (bottom anti-reflective coating) material from said gate structure using said etching reactant that etches both of said BARC (bottom anti-reflective coating) material and said gate electrode material having said one of an N-type dopant or a P-type dopant, wherein said etch rate of said gate electrode material having said one of an N-type dopant or a P-type dopant in said etching reactant increases with an increase of said dopant concentration of said one of an N-type dopant or a P-type dopant in said gate electrode material, and wherein sidewalls of said gate structure are trimmed by a trim length during said step of stripping said BARC (bottom anti-reflective coating) material from said gate structure to reduce the length of the gate structure beyond that achievable with photolithography processes; and increasing said dopant concentration of said one of N-type or P-type dopant in said gate electrode material during said step C of implanting said on of N-type or P-type dopant to increase said trim length of said gate structure, or decreasing said dopant concentration of said one of N-type or P-type dopant in said gate electrode material during said step C of implanting said one of N-type or P-type dopant to decrease said trim length of said gate structure.