Patent ID: 7943458
Filing Date: 2011-05-17
Classification: H01L

Abstract:
1. A method of fabricating a complementary metal oxide semiconductor (CMOS) structure comprising: providing a structure including a high k gate dielectric located atop a semiconductor substrate, said semiconductor substrate including at least two device regions; forming a first block mask on a surface of the high k gate dielectric in one of the device regions, while leaving the high k gate dielectric exposed in another device region; forming a first threshold voltage adjusting material on the first block mask in the one device region and atop the exposed high k gate dielectric in the another device region; removing the first threshold voltage adjusting material and the first block mask from the one device region, while maintaining the first threshold voltage adjusting material in the another device region; forming a second block mask on the first threshold voltage adjusting material, while leaving the high k gate dielectric within the one device region exposed; forming a second threshold voltage adjusting material on the second block mask in the another device region and atop the exposed high k gate dielectric in the one device region; and removing the second threshold voltage adjusting material and the second block mask from the another device region, while maintaining the second threshold voltage adjusting material in the one device region.