Patent ID: 8817529
Filing Date: 2014-08-26
Classification: G11C,H01L

Abstract:
1. A magnetic memory device comprising: a magnetic memory cell which can store multivalued memory information, and whose electric resistance given when memory information of a first value is stored is a first resistance value, whose electric resistance given when memory information of a second value is stored is a second resistance value larger than the first resistance value, whose electric resistance given when memory information of a third value is stored is a third resistance value larger than the second resistance value and whose electric resistance given when memory information of a fourth value is stored is a fourth resistance value larger than the third resistance value; a first reference cell whose electric resistance is set at a fifth resistance value larger than the first resistance value and smaller than the second resistance value; a second reference cell whose electric resistance is set at a sixth resistance value larger than the second resistance value and smaller than the third resistance value; a third reference cell whose electric resistance is set larger than the third resistance value and smaller than the fourth resistance value; and a read circuit for reading the memory information stored in the magnetic memory cell, including a first comparator comparing a signal corresponding to the electric resistance of the magnetic memory cell and a signal corresponding to the electric resistance of the first reference cell with each other, a second comparator comparing a signal corresponding to the electric resistance of the magnetic memory cell and a signal corresponding to the electric resistance of the second reference cell, and a third comparator comparing a signal corresponding to the electric resistance of the magnetic memory cell and a signal corresponding to the electric resistance of the third reference cell, wherein a direction of current flows in the first reference cell when the electric resistance of the first reference cell is set at the fifth resistance value and a direction of a current flows in the first reference cell when the memory information stored in the magnetic memory cell is read by the read circuit are the same, a direction of a current flows in the second reference cell when the electric resistance of the second reference cell is set at the sixth resistance value and a direction of a current flows in the second reference cell when the memory information stored in the magnetic memory cell is read by the read circuit are the same, a direction of a current flows in the third reference cell when the electric resistance of the third reference cell is set at a seventh resistance value and the a direction of a current flows in the third reference cell when the memory information stored in the magnetic memory cell is read by the read circuit are the same, the first reference cell includes a first magnetoresistive effect element including a first magnetization free layer to be electrically connected to a first source line via a first transistor, a first nonmagnetic layer formed on the first magnetization free layer, and a first magnetization fixed layer formed on the first nonmagnetic layer; and a second magnetoresistive effect element including a second magnetization free layer formed on the first magnetoresistive effect element, a second nonmagnetic layer formed on the second magnetization free layer, and a second magnetization fixed layer formed on the second nonmagnetic layer and electrically connected to a first bit line, the second reference cell includes a third magnetoresistive effect element including a third magnetization free layer to be electrically connected to a second source line via a second transistor, a third nonmagnetic layer formed on the third magnetization free layer, and a third magnetization fixed layer formed on the third nonmagnetic layer; and a fourth magnetoresistive effect element including a fourth magnetization free layer formed on the third magnetoresistive effect element, a fourth nonmagnetic layer formed on the fourth magnetization free layer, and a fourth magnetization fixed layer formed on the fourth no nonmagnetic layer and electrically connected to a second bit line, the third reference cell includes a fifth magnetoresistive effect element including a fifth magnetization free layer to be electrically connected to a third source line via a third transistor, a fifth nonmagnetic layer formed on the fifth magnetization free layer, and a fifth magnetization fixed layer formed on the fifth nonmagnetic layer; and a sixth magnetoresistive effect element including a six magnetization free layer formed on the fifth magnetoresistive effect element, a sixth nonmagnetic layer formed on the sixth magnetization free layer, and a sixth magnetization fixed layer formed on the sixth nonmagnetic layer and electrically connected to a third bit line, the electric resistance of the first reference cell is set at the fifth resistance by flowing a current to the first reference cell from the first bit line toward the first source line to put the first magnetoresistive effect element in a high resistance state and the second magnetoresistive effect element in the high resistance state, the electric resistance of the second reference cell is set at the sixth resistance value by flowing a current to the second reference cell from the seed bit line toward the second source line to put the third magnetoresistive effect element in the high resistance state and the fourth magnetoresistive effect element in the high resistance state, and the electric resistance of the third reference cell is set at the seventh resistance value by flowing a current to the third reference cell from the third bit line toward the third source line to put the fifth magnetoresistive effect element in the high resistance state and the sixth magnetoresistive effect element in the high resistance state.