Patent ID: 8570085
Filing Date: 2013-10-29
Classification: H03K

Abstract:
1. A retention cell comprising: a first input terminal configured to receive a first input data; a second input terminal configured to receive a sleep command signal; a third input terminal configured to receive a second input data; a first supply terminal configured to receive a first supply voltage; a second supply terminal configured to receive a second supply voltage that is larger than and independent of the first supply voltage; a first output terminal; a latch circuit electrically coupled with the first supply terminal and the second input terminal, the latch circuit being configured to be powered by the first supply voltage and to memorize a logic state corresponding to a last logic state present on the first input terminal upon receiving an assertion of the sleep command signal; a pass through circuit electrically coupled with the first input terminal, the second input terminal, the second supply terminal, the first output terminal, and the latch circuit, the pass through circuit being configured to: a transmission port electrically coupled with the third input terminal, the second supply terminal, and the first output terminal, the transmission port being configured to: