Patent ID: 9137896
Filing Date: 2015-09-15
Classification: H05K

Abstract:
1. A wiring substrate, comprising: a first insulating layer; an adhesion insulating layer formed under the first insulating layer, and an outer face of the adhesion insulating layer is made to a roughened face; a first wiring layer formed on the first insulating layer; a second insulating layer formed on the first insulating layer, and in which a first via hole reaching the first wiring layer is provided; a second wiring layer formed on the second insulating layer, and connected to the first wiring layer through the first via hole; a second via hole formed in the adhesion insulating layer and the first insulating layer, and reaching the first wiring layer; and a third wiring layer formed on the outer face of the adhesion insulating layer, and connected to the first wiring layer through the second via hole, wherein surface roughness of the outer face of the adhesion insulating layer is set within a range of 100 nm to 500 nm, and set within the same range as surface roughness of an upper face of each of the first insulating layer and the second insulating layer, and wherein the surface roughness of the outer face of the adhesion insulating layer is larger than surface roughness of a lower face of the first insulating layer.