Patent ID: 7631228
Filing Date: 2009-12-08
Classification: G06F

Abstract:
1. A computer-implemented method for altering a memory command stream to a hardware memory, the method comprising: writing data to the hardware memory; receiving error correction code data from the hardware memory in response to writing the data to the hardware memory; in response to receiving the error correction code data, counting a number of bit errors that occur during a period of time for each of a plurality of memory ranks included in the hardware memory, the counting resulting in a plurality of error counts; computing an overall error count for the hardware memory based on a sum of the plurality of error counts; comparing the overall error count to one or more overall thresholds, the comparing resulting in an overall comparison; adjusting an overall memory usage delay for the hardware memory based on the overall comparison; comparing each of the plurality of error counts to one or more memory rank error thresholds, the comparing resulting in a plurality of memory rank comparisons; and adjusting one or more memory rank usage delays, wherein each of the memory rank usage delays corresponds to one of the plurality of memory ranks, and wherein each of the adjusted memory rank usage delays is based on one of the memory rank comparisons.