Patent ID: 6784077
Filing Date: 2004-08-31
Classification: H01L

Abstract:
A method of forming a shallow trench isolation (STI) region, in a semiconductor substrate, comprising the steps of:forming an opening in a composite insulator layer, comprised of an overlying silicon nitride layer and of an underlying first silicon oxide layer, exposing a portion of a top surface of said semiconductor substrate; forming a shallow trench shape in a top portion of said semiconductor substrate, using said opening in said composite insulator layer as a mask; growing a second silicon oxide layer on exposed surfaces of said shallow trench shape; depositing a third silicon oxide layer on said second silicon oxide layer, and on a top surface of said composite insulator layer; depositing a fourth silicon oxide layer, completely filling said shallow trench shape; removing portions of said fourth silicon oxide layer, and portions of said third silicon oxide layer, from the top surface of said composite insulator layer, resulting in a definition of said STI region, with said STI region comprised of a bottom STI shape embedded in said top portion of said semiconductor substrate, featuring a fourth silicon oxide fill located between sidewalls comprised of said third silicon oxide layer on said second silicon oxide layer, and with said STI region comprised with a top STI shape, embedded in said composite insulator layer, and featuring said fourth silicon oxide fill covered by sidewalls of said third silicon oxide layer; selectively removing said silicon nitride layer of said composite insulator layer; and removing said first silicon oxide layer of said composite insulator layer via use of a 10:1 buffered hydrofluoric acid solution which etches said third silicon oxide layer at an etch rate of about 750 to 850 Angstroms/min, allowing removal of said first silicon oxide layer while resulting in sidewalls of said third silicon oxide layer remaining on sides of said top STI shape.