Patent ID: 6927127
Filing Date: 2005-08-09
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, the method comprising: forming a first insulating layer covering a conductive pad contacting an impurity region of a semiconductor substrate; sequentially forming a bit line conductive layer and a second insulating layer on the first insulating layer; patterning the bit line conductive layer and the second insulating layer to form a bit line conductive layer pattern and a second insulating layer pattern that expose a part of the first insulating layer; forming a third insulating layer covering the exposed surface of the first insulating layer, the bit line conductive layer pattern and the second insulating layer pattern; removing a part of the third insulating layer and the second insulating layer pattern to expose an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer; sequentially removing the exposed portion of the third insulating layer and a part of the first insulating layer to expose a portion of the conductive pad; forming a first spacer layer on side walls of the bit line conductive layer pattern and the first insulating layer; removing an upper portion of the bit line conductive layer pattern such that an upper portion of the first spacer layer is protruded; respectively forming an insulating layer pattern on the bit line conductive layer pattern and a second spacer layer on a side wall of the first spacer layer; and forming a conductive plug, which is in contact with the conductive pad between the second spacer layers.