Patent ID: 8216904
Filing Date: 2012-07-10
Classification: H01L

Abstract:
1. A method of forming a plurality of strained silicon transistors comprising: forming a trench in a substrate, the trench having sidewalls and a bottom located in the substrate; forming a dielectric layer over the substrate; forming a conductive gate electrode layer over the dielectric layer; etching the conductive gate electrode layer and the dielectric layer to form a first gate electrode and a second gate electrode overlying the substrate, the trench being positioned between the first and second gate electrodes and being spaced a selected distance from the first and second gate electrodes; implanting dopants into the substrate at a locations between the first and second gate electrodes to form a source/drain regions for the first and second transistors; depositing a compressive stress inducing dielectric layer overlying the first and second gate electrodes, the source/drain regions, the sidewalls and the bottom of the trench in the substrate; filling the trench with a dielectric material prior to forming the compressive stress inducing dielectric layer over the substrate; and etching all of the dielectric material out of the trench after implanting dopants into the substrate to form source and drain regions and prior to depositing the compressive stress inducing dielectric layer overlying the first and second gate electrodes.