Patent ID: 8416638
Filing Date: 2013-04-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of main word lines shared by a plurality of mats, each mat comprising a plurality of sub word lines, wherein the plurality of sub word lines are sequentially arranged; a decoding unit decoding a row address bit to output a word line driving signal, a plurality of sub word line driving units each configured to activate one of the sub word lines in response to the word line driving signal, wherein the neighboring sub word lines of the plurality of sub word lines are non-sequentially activated so as to correspond with the word line driving signal, and wherein neighboring sub word line driving units of the plurality of sub word line driving units are connected to different main word lines, wherein even sub world line driving units of the plurality of sub word line driving units are arranged in the same column, and odd sub word line driving units of the plurality of sub word line driving units are arranged in the same column, wherein a notation of the plurality of sub word line driving units are not matched to a notation of the plurality of sub word lines connected to the plurality of sub word line driving units, respectively.