Patent ID: 8020127
Filing Date: 2011-09-13
Classification: G06F

Abstract:
1. A method of circuit design comprising: receiving clock frequency constraints defining relationships between clock frequencies of a plurality of clock domains of a circuit design specified within a high-level modeling system; receiving a cost function that is dependent upon the clock frequencies of the plurality of clock domains; determining, by a computer, a feasibility result according to the clock frequency constraints and the cost function, wherein the feasibility result indicates whether a clock frequency assignment exists that specifies a clock frequency for each of the plurality of clock domains that does not violate any clock frequency constraint; outputting the feasibility result; in response to the feasibility result indicating that the circuit design is not feasible, performing steps including: responsive to the feasibility result indicating that the circuit design is feasible, determining a clock frequency assignment specifying a clock frequency for each of the plurality of clock domains; performing a timing check on the circuit design; and responsive to determining that the circuit design does not meet at least one timing constraint, generating a new clock frequency constraint according to a result from the timing check.