Patent ID: 6828830
Filing Date: 2004-12-07
Classification: G06F,H03K

Abstract:
A method for controllably asserting a clock signal on a clock signal bus of an integrated circuit comprising the steps of:in the absence of a first clock signal being coupled to a prescribed conductor of said integrated circuit, coupling a second clock signal as a default clock signal to said clock signal bus of said integrated circuit; and in response to said first clock signal being coupled to said prescribed conductor of said integrated circuit, interrupting the coupling of said second clock signal to said clock signal bus of said integrated circuit and, in place thereof, coupling said first clock signal to said clock signal bus of said integrated circuit, further including the steps of: storing electrical energy in an electrical storage device; controlling the energy storage state of said electrical storage device in accordance with whether or not said first clock signal is coupled to said prescribed conductor of said integrated circuit, and controllably coupling one of said first clock signal and said second clock signal to said clock signal bus, in accordance with the energy storage state of said electrical storage device; and wherein said electrical energy storage device comprises a capacitor which stores electrical energy provided by way of a current source coupled thereto, and wherein the step of controlling the energy storage state of said electrical storage device comprises repeatedly discharging said capacitor in accordance with said first clock signal, but otherwise allowing said capacitor to be charged, and wherein the step of interrupting the coupling of said second clock signal to said clock signal bus of said integrated circuit comprises causing said first clock signal to be coupled to said clock signal bus, in response to a voltage developed across said capacitor being less than a predetermined reference voltage, wherein the step of controlling the energy storage state of said electrical storage device comprises generating a delayed version of first external clock signal and controllably discharging said capacitor in accordance with a prescribed logical relationship between said first clock signal and said delayed version of said first clock signal.