Patent ID: 6209083
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A method of operating a processor which includes a floating point unit (FPU) comprising the steps of:programming indicia to select between a first mode of exception handling and a second mode of exception handling;operating said processor in said first mode of exception handling when said indicia so indicates in which said processor delays issuance of a next instruction in a series of pipelined floating point instructions to said FPU until a preceding instruction in said series of pipelined floating point instructions previously issued to said FPU clears; andoperating said processor in said second mode of exception handling when said indica so indicates in which said processor issues said next instruction in said series of pipelined floating point instructions to said FPU without waiting for said preceding instruction in said series of pipelined floating point instructions previously issued to said FPU to clear.