Patent ID: 6548903
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A semiconductor integrated circuit having first and second data lines for transferring data at respective different timings, said semiconductor integrated circuit comprising:first region(s) in which said first data line is formed in a first wiring layer above a semiconductor substrate and said second data line extending over said first data line is formed in a second wiring layer above said first wiring layer; second region(s) in which said second data line is formed in said first wiring layer and said first data line extending over said second data line is formed in said second wiring layer; and switching region(s) formed between said first and second regions for connecting the first data line in said first region with the first data line in said second region, and for connecting the second data line in said first region with the second data line in said second region, wherein in said switching region at least either of said first data lines and said second data lines are connected with each other via a third wiring layer formed above said semiconductor substrate.