Patent ID: 9007799
Filing Date: 2015-04-14
Classification: G11C

Abstract:
1. An apparatus, comprising a first content addressable memory (CAM) cell that includes a first compare circuit implemented to receive a reference bit and operate under control of the reference bit, and a stored bit and a corresponding stored complementary bit stored in the CAM cell, to selectively: provide the reference bit to an output node; pull-up the output node; or pull-down the output node, wherein the compare circuit includes a pass circuit to receive the reference bit and selectively provide the reference bit to the output node under control of the stored complementary bits, wherein the pass circuit is implemented to provide the reference bit to the output node when the stored bit is 0 and the stored complementary bit is 1; a pull-up circuit to selectively pull-up the output node under control of the reference bit and the stored complementary bit, wherein the pull-up circuit is implemented to pull-up the output node when the reference bit is 0 and the stored complementary bit is 0; and a pull-down circuit to selectively pull-down the output node under control of the reference bit and the stored bit, wherein the pull-down circuit is implemented to pull-down the output node when the reference bit is 1 and the stored bit is 1.