Patent ID: 6861874
Filing Date: 2005-03-01
Classification: H03K

Abstract:
1. A feedback control I/O buffer driven by a system voltage, comprising: an input/output circuit comprising a first PMOS transistor and a first NMOS transistor and having an I/O port coupled to an I/O pad, wherein the first PMOS transistor has an N-well region, a gate of the first NMOS transistor receives a first gate control signal, and a drain of the first PMOS transistor serves as the I/O port; a P-gate control circuit receiving a second gate control signal and being output to the gate of the first PMOS transistor, wherein the P-gate control circuit comprises: an N-well control circuit coupled to the I/O pad to control the voltage level at the N-well region of the first PMOS transistor according to a feedback signal output from an inverter, wherein the N-well control circuit comprises: