Patent ID: 7020806
Filing Date: 2006-03-28
Classification: G11C

Abstract:
1. A method for testing a memory unit to be tested in a test device, in which method a data rate is reduced, the method comprising: a) introducing the memory unit to be tested into the test device; b) reading a first data register to be tested from a memory cell array to be tested of the memory unit to be tested; c) buffering the first data register to be tested in a first buffer unit; d) testing the first data register to be tested in a comparator unit of the test device; d) reading, by the comparator unit, the buffer unit via an output unit; e) reading at least one further data register to be tested from the memory cell array to be tested of the memory unit to be tested; f) buffering the at least one further data register to be tested in a second buffer unit; g) testing the at least one further data register to be tested in the comparator unit of the test device wherein the comparator unit reads out the second buffer unit via the output unit; h) steps b) to e) are repeated for the remaining data registers to be tested; i) reading the data registers to be tested sequentially as buffered data registers via the output unit; j) reading a data stream of data registers at a reduced data rate; and k) switching the output unit of the memory unit to be tested to an operating mode, wherein a buffered data register is present at the comparator unit during at least one entire clock period of a clock signal which is output by a clock-generating unit.