Patent ID: 8174290
Filing Date: 2012-05-08
Classification: H03K

Abstract:
1. A noise reduction circuit comprising: a first reset signal generation circuit that generates a first reset signal that is activated when a data input signal goes to a low level, and is deactivated in synchronization with a clock signal when said data input signal is maintained at a high level; a second reset signal generation circuit that generates a second reset signal that is activated when said data input signal goes to a high level, and is deactivated in synchronization with said clock signal when said data input signal is maintained at a low level; a first counter circuit that counts an inverted signal of said clock signal, and is reset by said first reset signal; a second counter circuit that counts an inverted signal of said clock signal, and is reset by said second reset signal; and a data output circuit that comprises a selector circuit and an output flip-flop circuit that outputs a signal selected by said selector circuit in synchronization with said clock signal, wherein said selector circuit selects and outputs any of: a signal fixed at a high level, a signal fixed at a low level, and the output signal of said output flip-flop circuit, according to logic levels of an output signal of said first counter circuit and an output signal of said second counter circuit.