Patent ID: 8324946
Filing Date: 2012-12-04
Classification: G11C,H03K,H03L

Abstract:
1. A closed-loop duty-cycle corrector comprising: a first delay line having a first input terminal, a first output terminal, and a first control terminal, the first delay line configured to receive a first clock signal at the first input terminal and to delay the first clock signal by a first variable delay determined by a first control signal provided to the first control terminal to produce a first output signal at the first output terminal; a second delay line having a second input terminal, a second output terminal, and a second control terminal, the second delay line configured to receive a second clock signal at the second input terminal, wherein the second clock signal is complementary to the first clock signal, the second delay line configured to delay the second clock signal by a second variable delay amount determined by a second control signal provided to the second control terminal to produce a second output signal at the second output terminal; a duty cycle error detector having a third input terminal, a fourth input terminal and a third output terminal, the duty cycle error detection circuit configured to receive the first output signal at the third input terminal and the second output signal at the fourth input terminal, the duty cycle error detector further configured to generate a duty cycle error correction signal at the third output terminal based on a deviation of the first output signal from a desired duty cycle; and control circuitry having a fifth input terminal and a fourth output terminal, the control circuitry coupled to receive the duty cycle error correction signal at the fifth input terminal and modify at least one of the first and second variable delay amounts to compensate for the deviation from the desired duty cycle; wherein the duty cycle error detector further comprises: