Patent ID: 7739451
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A method comprising: buffering data to be written to a memory in at least a first and second buffer, wherein different data destined for the memory is provided on first and second data paths for buffering in each of the first and second buffers respectively; providing a plurality of successive first data pointers to a first memory controller, each of the first data pointers being streamed to the first memory controller without acknowledgement of its respectively preceding first data pointer; providing the first data pointers from the first memory controller to the first buffer and transferring data identified by the first data pointers from the first buffer; stalling one of the data transfers from the first buffer in response to a delay experienced in retrieving preceding data from the first buffer; providing a plurality of successive second data pointers to a second memory controller, each of the second data pointers being streamed to the second memory controller without acknowledgement of its respectively preceding second data pointer; providing the second data pointers from the second memory controller to the second buffer and transferring data identified by the second data pointers from the second buffer in response to the stalled data transfer from the first buffer; providing the data transfers from the first and second buffers comprise retrieving data words from the first and second buffers in any order regardless of an order of receipt and retrieving only a portion of a data block stored within the first and second buffers if a data hold is generated preventing further transfer of the data block; and completing the stalled data transfer from the first buffer in response to completing the data transfer from the second buffer.