Patent ID: 9110342
Filing Date: 2015-08-18
Classification: G02F,H01L

Abstract:
1. A TFT array substrate employing a fringe field mode comprising: a pixel electrode, which is arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate; a switching element, which is disposed at an intersection of the gate wiring and the source wiring; a counter electrode, which is formed on the pixel electrode with an insulating film interposed therebetween; and a silicon film formed on a lower layer so as to face the source wiring, wherein the source wiring and the pixel electrode are formed of the same transparent conductive material layer, and wherein the source wiring and the silicon film are formed so that end faces of the source wiring and the silicon film are overlapped and a width of the source wiring is identical to a width of the silicon film in a plan view; and wherein the end faces of the source wiring and the silicon film are formed to be flush with one another in the plan view outside of a region corresponding to the intersection of the gate wiring and the source wiring.