Patent ID: 6252566
Filing Date: 2001-06-26
Classification: G02F,G09G

Abstract:
A compensation process for a circuit comprising at least one first conductor at a specified potential, at least one second conductor generating disturbances by capacitive coupling to the at least one first conductor and at least one disturbance compensation bus capacitively coupled to the at least one first conductor by a first capacitor, comprising the steps of:measuring a first voltage (V.sub.comp) and a first current (I.sub.comp) on the compensation bus;calculating a second voltage (V.sub.dist) applied on the at least one disturbed conductor, anddetermining a set point voltage to be applied to the same compensation bus used for measurement of the first voltage and the first current in order to compensate for the disturbance; wherein the value of the voltage on the at least one disturbed conductor is given by the following formula; ##EQU6##and wherein the value of integral .intg.I.sub.comp dt is calculated from observation of the value of the voltage across the terminals of a second capacitor which is in series with the compensation bus and through which the same current I.sub.comp flows.