Patent ID: 9112017
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A programmable power semiconductor device comprising: a substrate of a first conductivity type; a first well region of a second conductivity type disposed in the substrate, the second conductivity type being opposite to the first conductivity type; a second well region of the first conductivity type disposed in the substrate, the second well region laterally adjoining the first well region at a boundary; a first region of the second conductivity type disposed in the second well region, the first region being laterally separated from the boundary by a channel region, the first region comprising a source of a MOSFET; a gate of the MOSFET disposed over the channel region, the gate being insulated from the channel region by a gate oxide that laterally extends from the first region to over a first area of the first well region adjacent the boundary; a conductive layer disposed over a second area of the first well region, the conductive layer being insulated from the second area by a first dielectric layer, the conductive layer comprising a capacitive plate, the second area of the first well region comprising a drain of the MOSFET; a second dielectric layer disposed over a third area of the first well region that laterally extends from the first dielectric layer to the gate oxide; and a second region of the second conductivity type disposed in the first well region partially beneath the first dielectric layer and partially beneath the second dielectric layer.