Patent ID: 8283671
Filing Date: 2012-10-09
Classification: H01L

Abstract:
1. A thin film transistor (TFT) comprising: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; a polycrystalline silicon layer comprising a semiconductor layer pattern disposed on the gate insulating layer and including a channel region, a source region and a drain region; an etch stop layer pattern disposed on the channel region of the semiconductor layer pattern and having a thickness of 20 to 60 nm, wherein a size of a grain forming the channel region of the semiconductor layer pattern is 1 to 10 μm, and a size of a grain forming the source and drain regions is 0.5 to 2 μm; an amorphous silicon layer pattern doped with n or p-type impurities disposed on the source and drain regions of the semiconductor layer pattern; and source and drain electrodes disposed on the amorphous silicon layer pattern on the source and drain regions of the semiconductor layer pattern, respectively.