Patent ID: 6560692
Filing Date: 2003-05-06
Classification: G06F

Abstract:
A data processing circuit comprising:a dedicated stack pointer register that is used only for a stack pointer; decoding means for decoding object code of a group of dedicated stack pointer instructions which have object code specifying said dedicated stack pointer register as an implicit operand and which relate to processing based on said dedicated stack pointer register, and for outputting a control signal based on said object code; and execution means for executing said group of dedicated stack pointer instructions based on said control signal and the contents of said dedicated stack pointer register, wherein said group of dedicated stack pointer instructions comprising a load instruction having data for specifying a transfer register within object code, and said load instruction comprising offset data within said object code that is data relating to an offset for specifying the address of a first area in memory; said decoding means decodes said load instruction; and said execution means performs at least one of a transfer of data from a given first area in memory to a given first register and a transfer of data from said given first register to said given first area, based on a memory address specified by said dedicated stack pointer register and a register address specified by said data for specifying a transfer register, when said load instruction is executed, said execution means determining said memory address according to the contents of said dedicated stack pointer register and said offset data.