Patent ID: 8933528
Filing Date: 2015-01-13
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a well trapping layer on, and above, a semiconductor substrate including a first semiconductor material layer containing a first semiconductor material, said well trapping layer is a set of second semiconductor material layers comprising a vertical stack, from bottom to top, of a lower semiconductor alloy layer, a doped semiconductor material layer, and an upper semiconductor alloy layer, each of said lower semiconductor alloy layer, said doped semiconductor material layer, and said upper semiconductor alloy layer including a second semiconductor material different from said first semiconductor material, and said doped semiconductor material layer including a dopant of a first conductivity type at a greater atomic concentration than said lower semiconductor alloy layer and said upper semiconductor alloy layer; forming a third semiconductor material layer comprising a third semiconductor material on, and above, said well trapping layer, wherein said dopant of said first conductivity type has a lesser diffusivity in said second semiconductor material than in said first semiconductor material or in said third semiconductor material; and patterning said third semiconductor material layer, said well trapping layer, and an upper portion of said semiconductor substrate to form a fin stack structure having a pair of substantially vertical parallel sidewalls on an unpatterned portion of said semiconductor substrate.