Patent ID: 6255164
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method for forming an electrically programmable read only memory (EPROM) cell on a semiconductor substrate, said method comprising the steps of:forming a gate insulator layer on said substrate;forming a first conductive layer on said gate insulator layer;forming an inter-gate dielectric layer on said first conductive layer;forming a second conductive layer on said inter-gate dielectric layer;forming a cap dielectric layer on said second conductive layer;patterning said cap dielectric layer, said second conductive layer, said inter-gate dielectric layer, said first conductive layer, and said gate insulator layer to form EPROM gate structures;forming sidewall dielectrics on sidewalls of said EPROM gate structures;forming source junctions and drain junctions in said substrate under regions between said EPROM gate structures which are uncovered by said EPROM gate structures;forming a polysilicon layer over said substrate to conformably cover said dielectric sidewalls, said source junctions, said drain junctions, and said cap dielectric layer;patterning said polysilicon layer to respectively form common source lines on said source junctions and landing pads on said drain junctions;forming a metal-containing layer over said substrate to cover said polysilicon layer;performing a thermal process to react said metal-containing layer and said common source lines and said landing pads, in order to form metal silicide structures respectively on said source junctions and said drain junctions; andremoving unreacted portions of said metal-containing layer.