Patent ID: 8633094
Filing Date: 2014-01-21
Classification: H01L

Abstract:
1. A method of fabricating a multi-layer structure for a power transistor device comprising: (a) loading a wafer having a nitride-based active semiconductor layer into a reaction chamber; (b) exposing, within the reaction chamber, a top surface of the nitride-based active semiconductor layer to a first source; (c) performing, within the reaction chamber, a nitrogen (N) plasma strike, resulting in the formation of a nitride layer directly on the nitride-based active semiconductor layer; (d) exposing, within the reaction chamber, a top surface of the nitride layer to a second source; and (e) performing, within the reaction chamber, a nitrogen-oxygen plasma strike, resulting in the formation of an oxy-nitride layer directly on the nitride layer, wherein the nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.