Patent ID: 6937505
Filing Date: 2005-08-30
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array; wherein the memory cell array is constituted by arranging a plurality of memory cells comprising: the memory cells arranged like a matrix in a row direction and column direction and moreover, a word line is included in each row of the memory cells along the row direction, and bit lines extending alone a column direction in each column and equal to the number of the variable resistive elements in the memory cells are included; and wherein a hierarchical bit line structure is used in which at least a plurality of blocks is arranged in the column direction by using the memory cell array as one block, the bit line of each block is used as a local bit line, a local bit line selection transistor for selecting the local bit line is set, and the local bit line is connected to a global bit line through the local bit line selection transistor.