Patent ID: 8614489
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A device structure comprising: a first region of n-type semiconductor material; a second region of n-type semiconductor material; a first region of p-type semiconductor material, the first region of p-type semiconductor material stacked vertically between the first and second regions of n-type semiconductor material to form a vertical NPN bipolar transistor; a second region of p-type semiconductor material, the first and second regions of p-type semiconductor material stacked vertically relative to the second region of n-type semiconductor material to form a vertical PNP bipolar transistor; an input/output (I/O) pad coupled with the first region of n-type semiconductor material and the first region of p-type semiconductor material; and an interconnect structure including a first wiring path coupling the first region of n-type semiconductor and the first region of p-type semiconductor material with the I/O pad.