Patent ID: 7863112
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A method of protecting a FET from plasma damage during FEOL processing comprising: forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity; when forming gate oxide for the FET, forming oxide on the FET-like structure which is thinner than the gate oxide; and depositing and etching polysilicon having a first portion which will serve as a gate electrode for the FET, and having a second portion which will serve as a gate electrode for the FET-like structure; wherein the first and second portions are connected by a third portion of the polysilicon; performing source and drain implants for the FET; depositing a pre-metal layer (PMD); forming a plurality of contact openings through the PMD to make contact with source (S depositing a first metal layer (M patterning the first metal layer; wherein: a first portion of M a second portion M a third portion of M 1 forms a connection to the source (S 2 ) of the FET-like structure; a fourth portion of M a fifth portion of M