Patent ID: 6207517
Filing Date: 2001-03-27
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor component with a semiconductor insulation layer, which comprises the following steps:providing a semiconductor substrate;forming a whole-area insulation layer on the semiconductor substrate with a predetermined thickness;forming a first mask on the insulation layer and defining a first predetermined zone;selectively implanting impurity ions into the first predetermined zone of the insulation layer defined by the first mask, and thereby selecting an implantation profile in accordance with an etching zone situated on the surface and having a smaller thickness than the predetermined thickness of the insulation layer;selectively etching the insulation layer in the first predetermined zone in accordance with the mask;forming a second mask on the semiconductor substrate and defining a second predetermined zone of the insulation layer;selectively implanting impurity ions into the second predetermined zone of the insulation layer, and selecting an implantation profile in accordance with an etching zone having the same thickness as the thickness of the insulation layer;selectively etching the insulation layer in the first predetermined zone and uncovering the semiconductor substrate;forming a whole-area conductive layer on the structure formed in the selectively etching; andpolishing the conductive layer substantially to the thickness of the insulation layer.