Patent ID: 8072796
Filing Date: 2011-12-06
Classification: G11C

Abstract:
1. A memory circuit, comprising: a plurality of bit lines; a plurality of select lines; a plurality of bit cells; and a controller coupled to the plurality of bit lines and to the plurality of select lines, wherein the controller includes a power supply control circuit adapted to control the power supply voltage applied to the plurality of bit cells, wherein the controller is adapted to read a selected bit cell of the plurality of bit cells by a setting of a select line associated with the selected bit cell to a first level, and to set the selected bit cell by an activation of the select line associated with the selected bit cell to a second level, wherein the first level is lower than the second level, and wherein the power supply control circuit includes: a P transistor comprising a source and a drain, wherein the source of the P transistor is coupled to a power supply and wherein the drain of the P transistor is coupled to the plurality of bit cells; a first N transistor serially coupled to the P transistor, wherein the first N transistor is adapted to operate as a diode; and a second N transistor serially coupled to the first N transistor, wherein a source of the second N transistor is coupled to ground and wherein both the P transistor and second N transistor are driven by a reset signal.