Patent ID: 6763026
Filing Date: 2004-07-13
Classification: G11C

Abstract:
A memory for readably storing data bits of packets therein, comprising:plural addressable data storage regions each having plural memory cells; a data distributing circuit connected to said plural addressable data storage regions, and responsive to an internal address signal selectively specifying the plural memory cells of an addressable data storage region selected from said plural addressable data storage regions for providing a data path to the memory cell specified by said internal bit address signal, and responsive to an external address signal selectively enables said plural addressable data storage regions, wherein said data distributing circuit successively receives data bits of a received packet; an internal address generator for supplying said internal address signal to said data distributing circuit; and a parallel-to-serial converter connected to said plural addressable data storage regions, storing the data bits read out from an addressable data storage region selected from said plural addressable data storage regions, and serially outputting said data bits to the outside, wherein a clock signal makes said data distributing circuit and said internal address generator synchronous with each other, wherein said data distributing circuit includes a temporary data storage circuit responsive to said clock signal for successively storing said data bits of said received packet, and said internal address generator is responsive to said clock signal so as to sequentially changing said internal address signal, wherein said internal address generator includes a counter responsive to said clock signal for incrementing a stored value, and a driver connected between said counter and said data distributing circuit and responsive to said clock signal so as to change the internal address of said internal address signal on the basis of said stored value.