Patent ID: 6765253
Filing Date: 2004-07-20
Classification: G11C,H01L

Abstract:
A semiconductor memory device including a plurality of memory cells arranged in a matrix of rows and columns, whereineach of said plurality of memory cells includes only one transfer gate transistor having a pair of source/drain, a first inverter having an input node electrically connected to one of said pair of source/drain, a second inverter having an output node electrically connected to said input node of said first inverter and an input node electrically connected to an output node of said first inverter, and a capacitor element having first and second electrodes opposing each other to allow storage of charge, said first electrode being electrically connected to said one of said pair of source/drain and said output node of said second inverter, said second electrode being electrically connected to said output node of said first inverter, said semiconductor memory device having a plurality of bit lines provided for the respective columns of the memory cells, each of said bit lines electrically connected to the other of said pair of source/drain of each memory cell of each column, and a plurality of word lines provided for the respective rows of the memory cells, each of said word lines electrically connected to a gate of said transfer gate transistor of each memory cell of each row, wherein data of said memory cell is read based on charge stored in said capacitance element.