Patent ID: 8589602
Filing Date: 2013-11-19
Classification: G06F

Abstract:
1. A circuit comprising: an execution unit; a plurality of addressable devices; a data transfer engine coupled to the execution unit and to said plurality of addressable devices, operable to fetch a plurality of descriptors including an address of a respective first of said addressable devices and a respective second of said addressable devices under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from the first addressable device to the second addressable device; wherein the data transfer engine comprises delay circuitry operable to block, for the duration of a predetermined delay period running from an earlier of said transfers, any later of said transfers involving at least one of the plurality of addressable devices as from the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors being a descriptor of the earlier transfer; wherein the delay circuitry comprises a software-accessible register coupled to the execution unit for storing a value of the delay period, such that the delay period is programmable by software executed on the execution unit, and the indication in said one of the plurality of descriptors comprises one or more delay bits which specify whether or not to use the programmed value of the delay period in said blocking; and wherein the delay circuitry is arranged to retrieve the programmed value of the delay period from the software-accessible register for use in said blocking if the one more delay bits specify use of the programmed value of the delay period.