Patent ID: 6725358
Filing Date: 2004-04-20
Classification: G06F

Abstract:
A processor, comprising:a register set; a load queue containing a plurality of entries that each includes a reservation valid field, a target address field, and an associated hazard flag indicative of a possible data hazard, wherein each of said plurality of entries is associated with a respective one of a corresponding plurality of load instructions executed by the processor and at least one of said plurality of load instructions is a load-reserve instruction; at least one execution unit that executes load instructions to transfer data into said register set; queue management logic that, responsive to execution of said load-reserve instruction, detects by reference to said load queue whether a data hazard exists, and if so, initiates correction of said data hazard, wherein said queue management logic records a reservation for said load-reserve instruction by setting the reservation valid field of an entry in said load queue associated with said load-reserve instruction, and wherein said queue management logic detects that a data hazard exists for said load-reserve instruction if a target address of said load-reserve instruction matches a target address specified in the target address field of an entry in said load queue that has its hazard flag set and that is associated with another load instruction following said load-reserve instruction in program ordering; and wherein each entry in said load queue includes a data field that buffers load data obtained by execution of the associated load instruction, and wherein said queue management logic, responsive to detection of said data hazard, corrects said data hazard by outputting said load data retrieved by said another load instruction from said data field to said register set in accordance with said load-reserve instruction.