Patent ID: 7340564
Filing Date: 2008-03-04
Classification: G06F

Abstract:
1. A method comprising: programming a single bit in a reserved register for a processor by use of op codes, wherein the register is used to defeature at least one function of a processor; gating the bit with a cache hit/miss signal from an instruction cache, in which during normal mode the register is programmed for the bit to have a first state to gate through the cache hit/miss signal from the instruction cache to an instruction fetch unit, but during a defeatured mode, the register is programmed for the bit to have a second state to gate the cache hit/miss signal for coupling to the instruction fetch unit as a cache miss, in order to defeature a cache hit as a cache miss to allow an instruction fetch to be made visible on a bus; and tracing the instruction fetch on the bus to monitor a cache hit transaction within an integrated circuit containing the processor, register and the instruction cache, in which the tracing is performed based on selectable test criteria.