Patent ID: 6522690
Filing Date: 2003-02-18
Classification: G06F

Abstract:
A zero determination signal generating circuit which generates a zero determination signal for determining whether output data of a shifter is zero, the shifter having first to xth left shifters cascaded where x is an integer of 3 or larger, an ith left shifter which is one of the first to xth left shifters having a 2x-bit structure and a shift amount of 2xâˆ’i bits or 0 bit, 2x-bit input data being applied to the first left shifter and 2x-bit output data being outputted from the xth left shifter, said zero determination signal generating circuit comprising:j OR circuits where j=1, 2, . . . , xâˆ’1, a kth OR circuit which is one of the j OR circuits corresponding to the kth left shifter and performing an OR operation on bits of the 2x-bit data inputted to or outputted from the kth left shifter and located between a digit of the (2xâˆ’2xâˆ’k)th power of 2 and a digit of the (2xâˆ’2Â·2xâˆ’k+1)th power of 2; and an OR/buffer circuit which performs, when the shift amount is 0 to 30, an OR operation on an output of a first one of the j OR circuits corresponding to one of the left shifters having a shift amount of zero, a bit of the 2x-bit data located at a digit of the (2xâˆ’1)th power of 2 and outputted from the xth left shifter when not performing a shifting operation, and a bit of the 2x-bit input data at a digit of 2o, and which performs, when the shift amount is 31, a buffering operation on the bit of the 2x-bit input data at a digit of 2o, the OR/buffer circuit outputting the zero determination signal.