Patent ID: 6162723
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A fabrication method of a semiconductor integrated circuit device comprising:(a) preparing a semiconductor substructure with a main surface;(b) forming an insulating layer on the main surface of said substructure;(c) forming a first patterned conductive layer serving as a first-level wiring layer on said insulating layer in such a way that the first-level wiring layer includes a first plurality of wiring lines and a second plurality of wiring lines;said first plurality of wiring lines being located apart from each other at gaps equal to or smaller than a specific value;said second plurality of wiring lines being located apart from each other at gaps larger than the specific value; and(d) forming an interlevel dielectric layer on said insulating layer to cover said first-level wiring layer by a high-density plasma-enhanced CVD process in such a way that said interlevel dielectric layer includes voids selectively located in the gaps of said first plurality of wiring lines;the tops of the voids being lower than the tops of said first-level wiring layer, respectively;whereby a parasitic capacitance between said first plurality of wiring lines is decreased by said voids.