Patent ID: 6649963
Filing Date: 2003-11-18
Classification: G11C,H01L

Abstract:
A ferroelectic memory (FEM) cell comprising:a silicon substrate; a gate junction region located in said substrate; doped to form a conductive channel of a first type; a source junction region and a drain junction region located in said substrate on either side of said gate junction region, doped to form a pair of conductive regions of a second type; a MOS capacitor, including an oxide layer and an upper metal layer located over said gate junction region, said MOS capacitor having a predetermined surface area; a FEM capacitor, including a lower metal layer, a FE layer and an upper metal layer; wherein said FEM capacitor is stacked on and overlays less than said predetermined surface area of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit, wherein said FEM capacitor is offset on said MOS capacitor, extending fore and aft with said MOS capacitor, and extending over less than the lateral extent of said MOS capacitor, thereby increasing the coupling capacitance; an insulating layer, having an upper surface, overlying said junction regions, said stacked gate unit, and said substrate; and a source electrode and a drain electrode, each located on the upper surface of said insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper metal layer of said stacked gate unit.