Patent ID: 9159438
Filing Date: 2015-10-13
Classification: G06F,G11C

Abstract:
1. A NAND flash memory device, comprising: a memory cell array having a plurality of memory blocks; a page buffer configured to store temporally write data to be written to the memory cell array or to store temporally read data from the memory cell array; a data I/O circuit configured to transfer the write data from an external device to the page buffer in response to a clock signal or to output the read data in response to the clock signal; a status register configured to output status data of the NAND flash memory device to the external device in response to the clock signal; and a control logic configured to input command and address from the external device and control the page buffer, the data I/O circuit in response to the command and the address in a program operation, a read operation, or an erase operation, wherein the status data of the NAND flash memory device indicates whether or not to perform an erase, write, or read operation, wherein the write data are inputted and read data are outputted according to a double data rate (DDR) transmission method, and wherein the status data are outputted in accordance with a transmission method that is not the DDR transmission method in association with the erase, write, or read operation, wherein the status register outputs the status data in response to a status read command from the external device.