Patent ID: 6665775
Filing Date: 2003-12-16
Classification: G06F

Abstract:
A cache, comprising:a tag array comprising a first address input to receive an address from a first computing engine, a second address input to receive an address from a second computing engine, a shared mode input to receive a shared mode value, and a plurality of tag array lines arranged into a plurality of sets and ways, wherein a first subdivision of said sets of tag array lines in each of said ways may be dynamically allocated either for exclusive access by the first computing engine or for exclusive access by the second computing engine, wherein said allocation is based upon the shared mode value received at the shared mode input, wherein the plurality of sets of tag array lines in the tag array also includes a second subdivision of said sets, and wherein sets of tag array lines in the second subdivision are allocated for exclusive access by the first computing engine regardless of the shared mode value received at the shared mode input; and a data array electrically coupled to the tag array.