Patent ID: 6373101
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A solid-state relay having a pair of output terminals for connection with a load to be controlled, said solid-state relay comprising:a control means which gives an electrical energy upon receipt of an input signal; a pair of LDMOSFETs, said LDMOSFETs having individual gates connected commonly to receive said electrical energy to be driven thereby, having individual source connected to each other, and having individual drains connected to said output terminals, respectively; at least one supporting plate of electrically conductive material mounting thereon said LDMOSFETs; each of said LDMOSFET comprising: a silicon layer of a first conductive type having top and bottom surfaces, a drain region of said the first conductive type diffused in the top surface of said silicon layer to define said drain of the LDMOSFET; a well region of a second conductive type diffused in said silicon layer in a laterally spaced relation from said drain region; a source region of the first conductive type diffused within said well region to define a channel extending between said source region and a confronting edge of said well region along the top surface of said silicon layer, said source region defining said source of the LDMOSFET; a drain electrode being placed on said drain region and electrically connected thereto; a gate electrode electrically connected to a gate layer of an electrically conductive material which is placed over said channel through a dielectric layer to define said gate; and a source electrode being placed over said source region and electrically connected thereto; wherein each of said LDMOSFET is of an SOI structure which comprises a silicon substrate, a buried oxide layer formed on said silicon substrate, and said silicon layer formed on said buried oxide layer, said silicon substrate being mounted on said supporting plate, and wherein said well region extends the full depth of said silicon layer to have a bottom abutted against said buried oxide layer, wherein said source region is configured to surround said drain region within a plane of said silicon layer, and wherein said silicon layer is formed with a peripheral zone located outwardly of said well region and isolated from said drain region by said well region, said peripheral zone and said drain region being electrically connected commonly to said supporting plate.