Patent ID: 6697285
Filing Date: 2004-02-24
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array; a plurality of data output terminals for outputting data of a plurality of bits in parallel; a latch circuit arranged between said memory cell array and said plurality of data output terminals; a read control circuit for reading data of bits in parallel from said memory cell array, the number of said bits being a plurality of times as large as the number of said plurality of data output terminals; an address transition detecting circuit for detecting the transition of an address signal for outputting a latch control signal; and an output control circuit for performing a switching control of a first mode on the basis of a switching signal such that said data read in parallel from said memory cell array in each read cycle is held by said latch circuit in accordance with said latch control signal, and said data held by said latch circuit is divided by a plural number and one group of the divided data is outputted to said plurality of data output terminals in said read cycle, with the remaining group of divided data being outputted to said plurality of data output terminals in a predetermined period of the next read cycle.