Patent ID: 8325305
Filing Date: 2012-12-04
Classification: G02F,G09G

Abstract:
1. An array substrate comprising: a substrate having a gate line, a data line and a switching element electrically connected to the gate line and the data line; a pixel electrode disposed in a pixel area of the substrate and electrically connected to the switching element, the pixel electrode including a connection part dividing the pixel area into a plurality of domains and slits extending from the connection part; a supplementary electrode corresponding to at least a space between the slits of the pixel electrode; and a first insulation layer formed on the data line and the switching element and a second insulation layer formed on the first insulation layer, wherein the supplementary electrode is formed above the first insulation layer and the pixel electrode is formed on the second insulation layer, the supplementary electrode being electrically disconnected from the first insulation layer.