Patent ID: 7050307
Filing Date: 2006-05-23
Classification: G06F,H05K

Abstract:
1. A computer system comprising: a first array of circuit boards, wherein each of the circuit boards of the first array of circuit boards is substantially parallel to each other, wherein each circuit board of the first array includes a first plurality of connectors mounted on an edge; and a second array of circuit boards, wherein each of the circuit boards of the second array of circuit boards is substantially parallel to each other, wherein each circuit board of the second array includes a second plurality of connectors mounted on an edge; wherein the first array of circuit boards and the second array of circuit boards are detachably mated together by the first and the second plurality of connectors such that the first array of circuit boards and the second array of circuit boards are positioned substantially perpendicular to each other; wherein at least one of said second array of circuit boards is configured to route redundant address information; and wherein at least two of said second array of circuit boards are power distribution circuit boards each coupled to independently provide power to said first array of circuit boards.