Patent ID: 6638824
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A method of fabricating a gate of a semiconductor device comprising:a) patterning a layer of sacrificial gate material on a substrate; b) dosing the substrate with a dopant to form a source region self-aligned to the sacrificial gate material; c) thermally treating the substrate to diffuse a portion of the dopant laterally to form a diffused source region, a portion of the diffused source region underlying a portion of the layer of sacrificial gate material; then d) forming a dielectric layer on the substrate; e) removing a portion of the dielectric layer to expose the layer of sacrificial gate material; f) stripping the sacrificial gate material from the substrate to form a gate region; g) forming a gate dielectric layer in the gate region; and h) forming a metal gate layer on the gate dielectric layer wherein at least a portion of the metal gate layer occupies a volume previously occupied by the sacrificial gate layer.