Patent ID: 8165847
Filing Date: 2012-04-24
Classification: G06F,G11C

Abstract:
1. A system for checking data transferred within a data processing system, said system comprising: a main processor; a processor memory coupled to said main processor; a flexible support processor coupled to said main processor via a data bus; a transfer description mailbox (TDM) associated with said flexible support processor and which stores a plurality of entries, including a status field and a device under test address field, identifying a memory location in said processor memory; a flexible support processor memory coupled to said flexible support processor, wherein said first memory embodies computer program code, said computer program code comprising instructions executable by said flexible support processor and configured for: wherein said flexible support processor with associated TDM and flexible support processor memory provides a controller functionality of a peripheral component interconnect (PCI) direct memory access (DMA) master, which concurrently functions as both a system controller and an input/output (I/O) exerciser, wherein said I/O exerciser functions independently from a system under test (SUT) and does not require utilization of a card specifically designed to execute said I/O exerciser.