Patent ID: 6160433
Filing Date: 2000-12-12
Classification: H03L

Abstract:
A method for generating a clock, comprising the steps of:providing a first clock operating at a first frequency;providing a second clock operating at a second frequency that is different from the first frequency;accumulating the phase difference between the second clock and a second parameter corresponding to a remainder of a division operation in which the first frequency is divided by the second frequency, in accordance with the second clock, a first parameter and the second parameter;producing a time-interval extension signal when the accumulated value reaches a cycle of the first clock;providing a third parameter that is generated by subtracting one from the quotient produced by dividing the first frequency by double of the second frequency;producing a timing signal based on the third parameter when the time-interval extension signal is not supplied, while producing the timing signal based on a sum of the third parameter and the cycle of the first clock when the time-interval extension signal is supplied; andcontrolling the phase of the second clock in response to the timing signal.