Patent ID: 6417074
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A method of providing isolation between adjacent regions of an integrated circuit comprising the steps of:selecting a circuit layout for fabrication of said integrated circuit on a substrate, including defining adjacent substrate locations for a first region and a second region for which leakage current from said second region to said substrate is undesired during operation of said integrated circuit, at least said second region being an active region within which a dopant is to be introduced; forming a guard layer over said substrate such that said guard layer resides over a peripheral portion of said second region, said peripheral portion of said second region extending along an edge of said first region; and introducing said dopant into said second region to establish predetermined electrical characteristics within said second region, said guard layer inhibiting introduction of said dopant into said peripheral portion, thereby leaving a substantially dopant-free transition strip within said second region and along said edge of said first region to provide isolation between said second region and said first region.