Patent ID: 6476640
Filing Date: 2002-11-05
Classification: H03K

Abstract:
A method of buffering first and second input signals, the method comprising:inverting the first and second input signals; isolating an input capacitance associated with the first input signal from a conduction path associated with the second input signal, wherein isolating the input capacitance associated with the first input signal includes propagating the first input signal through a first plurality of series-connected inverters; isolating an input capacitance associated with the second input signal from a conduction path associated with the first input signal, wherein isolating the input capacitance associated with the second input signal includes propagating the second input signal through a second plurality of series-connected inverters; delaying the first and second input signals, wherein delaying the first input signal includes propagating the first input signal through a third plurality of series-connected inverters, and wherein delaying the second input signal includes propagating the second input signal through a fourth plurality of series-connected inverters; producing a first pulse signal using the delayed first input signal; driving the inverted second input signal in response to the first pulse signal to produce the first buffered input signal; producing a second pulse signal using the delayed second input signal; and driving the inverted first input signal in response to the second pulse signal to produce the second buffered input signal.