Patent ID: 7517792
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device having a multilayer interconnection structure, comprising the steps of: forming, on a first insulation film having a first interconnection pattern, a second interlayer insulation film; forming a second interconnection pattern in said second interlayer insulation film by a dual damascene process such that said second interconnection pattern makes a contact with said first interconnection pattern with a plurality of via-plugs forming a first via-plug group; forming a third interlayer insulation film on said second interlayer insulation film; and forming a third interconnection pattern in said third interlayer insulation film by a dual damascene process such that said third interconnection pattern makes a contact with said second interconnection pattern with a plurality of via-plugs forming a second via-plug group; wherein there is provided a step of controlling a density of said via-plugs forming said second via-plug group to be 70% or less in the event said via-plugs are formed with a minimum pitch of 0.4 μm in said first and second via-plug groups.