Patent ID: 7932603
Filing Date: 2011-04-26
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a first metal layer over said silicon substrate; a second metal layer over said first metal layer and said silicon substrate; a dielectric layer between said first and second metal layers; a first conductive pad over said silicon substrate; a passivation layer over said silicon substrate, said first and second metal layers and said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers; a first organic layer on said passivation layer, wherein said first organic layer has a thickness between 1 and 100 micrometers, wherein a second opening in said first organic layer is over said first contact point; and a metallization structure on said first contact point and on a top surface of said first organic layer, wherein said metallization structure is connected to said first contact point through said second opening, wherein said metallization structure comprises a titanium-containing layer on said top surface and an electroplated copper-containing layer over said titanium-containing layer.