Patent ID: 7969813
Filing Date: 2011-06-28
Classification: G11C

Abstract:
1. A write command and write data timing circuit, comprising: a first counter circuit configured to increment a first count in response to a first count clock signal based on a write clock signal; a second counter circuit configured to increment a second count in response to a second count clock signal based on a memory clock signal; a write command latch coupled to the second counter circuit configured to latch internal write commands at a first time in response to the incrementing second count and configured to output the internal write command at a second time later than the first time in response to the incrementing second count having a same value at the first time; a flip-flop (FF) circuit coupled to the write command latch and the first counter circuit and configured to latch the internal write command delayed relative to the second time in response to the incrementing first count having the same value of the second count at the second time, the FF circuit further configured to generate an internal write enable signal in response to latching the internal write command; and a write data register configured to capture write data in accordance with the write clock signal and configured to output captured write data in response to the internal write enable signal.