Patent ID: 8937830
Filing Date: 2015-01-20
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a plurality of first lines disposed on a substrate; a plurality of second lines disposed intersecting the first lines; a memory cell array including memory cells, the memory cells disposed at each of intersections of the first lines and the second lines and each configured having a current rectifier element and a variable resistance element connected in series therein; and a control circuit configured to selectively drive the first lines and the second lines, each of the memory cells having formed on a side surface thereof: a first insulating film including silicon and nitrogen and the first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film including silicon and nitrogen and the second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value, and the first value being smaller than the second value.