Patent ID: 6496972
Filing Date: 2002-12-17
Classification: G06F

Abstract:
A method of optimizing a design of an integrated circuit device comprising the steps of:a) accessing a netlist representing said integrated circuit design, the netlist including a top-level block coupled to at least a first circuit block and a second circuit block; b) creating a first model of the first circuit block and a second model of the second circuit block, the first model and the second model abstracting circuitry of the first circuit block and the second circuit block respectively; and c) optimizing the netlist by optimizing the first circuit block, the second circuit block, and the top-level block to yield an optimized netlist the step c) comprising the steps of: c1) optimizing the first and second circuit blocks; c2) replacing the first and second circuit blocks in the top-level block with the first and second models respectively; c3) optimizing the top-level block with the first and second models included therein; and c4) generating the optimized netlist by combining the optimized first and second circuit blocks from step c1) and the optimized top-level block from step c3), and wherein step c1 and step c3 are performed in parallel.