Patent ID: 7600142
Filing Date: 2009-10-06
Classification: G06F,Y02D

Abstract:
1. An integrated circuit operable in a normal mode and a power-saving mode, the integrated circuit being connected to an external memory device, the integrated circuit comprising: a volatile memory that stores data in the normal mode and loses the stored data in the power-saving mode; a central processing unit that executes logic processing in the normal mode, saves data from the volatile memory to the external memory device during a transition from the normal mode to the power-saving mode, and restores the data from the external memory device to the volatile memory during a transition from the power-saving mode to the normal mode; a data input-output circuit that transfers data between the central processing unit and the external memory device, thereby enabling the central processing unit to save and restore the data; a clock divider that divides the frequency of an external clock signal to obtain a first clock signal and a second clock signal, the first clock signal having a higher frequency than the second clock signal, and supplies the second clock signal to the data input-output circuit as a data transfer clock signal; a first selector controlled by the central processing unit to select the first clock signal in the normal mode, the second clock signal in the power-saving mode, and the second clock signal during the transitions between the power-saving mode and the normal mode; an interrupt detector for detecting an external interrupt; and a clock supply circuit connected between the first selector and the central processing unit, and also between the interrupt detector and the central processing unit, supplying the clock signal selected by the first selector to the central processing unit during the normal mode, halting supply if the selected clock signal to the central processing unit when the central processing unit finishes saving the data from the volatile memory to the external memory unit, and resuming supply of the selected clock signal to the central processing unit when the external interrupt is detected.