Patent ID: 7419871
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A method of forming a semiconductor construction, comprising: providing a semiconductor substrate having a memory array region and a region peripheral to the memory array region; forming paired transistors within the memory array region, the paired transistors sharing a source/drain region, and having two other source/drain regions in addition to the shared source/drain region; forming a peripheral transistor gate within the region peripheral to the memory array region; forming an electrically insulative layer extending over the shared source/drain region and over the peripheral transistor gate; patterning the electrically insulative layer into a protective block over the shared source/drain region and into sidewall spacers along the peripheral transistor gate; the patterning of the layer exposing said two other source/drain regions; forming a bitline in electrically connection with the shared source/drain region; and forming two capacitors in electrical connection with the two other source/drain regions.