Patent ID: 7290261
Filing Date: 2007-10-30
Classification: G06F

Abstract:
1. A method for managing transitions between a first number of threads and a second number of threads executing a simultaneous multi-threaded processor, comprising: receiving an instruction indicating a thread mode switch; setting thread enable signals indicating an enable state of multiple threads, wherein said second number of threads is specified for further execution; and reallocating per-thread fixed entries within a rename resource of said processor in conformity with said thread enable signals, by directing an action at a mapper associated with said rename resource that maps said per-thread fixed entries, wherein said mapper reallocates said per-thread fixed entries so that when a given one of said multiple threads is not specified for further execution, said per-thread fixed entries previously associated with said given thread are separately usable to store distinct values by at least one thread of said second number of threads, wherein said second number of threads is greater than said first number of threads, and wherein said reallocating comprises issuing dummy instruction dispatches implicating a predetermined fixed number of rename registers within said rename resource to an instruction sequencer, whereby said instruction sequencer commands said mapper to allocate said predetermined number of new entries within said rename resource for at least one additional thread specified for further execution.