Patent ID: 6651130
Filing Date: 2003-11-18
Classification: G06F

Abstract:
A system interface comprising:a plurality of first directors; a plurality of second directors; a data transfer section having a cache memory, such cache memory being coupled to the plurality of first and second directors; a messaging network, operative independently of the data transfer section, coupled to the plurality of first directors and the plurality of second directors; and wherein the first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors with such data passing through the cache memory in the data transfer section; wherein each one of the first directors includes: a data pipe coupled between an input of such one of the first directors and the cache memory; a microprocessor; a controller; a common bus, such bus interconnecting the data pipe, the microprocessor, and the controller; and wherein the controller controls the transfer of the messages between the message network and such one of the first directors and the data between the input of such one of the first directors and the cache memory.