Patent ID: 6677680
Filing Date: 2004-01-13
Classification: H01L

Abstract:
An interconnect structure comprising:a substrate comprising a dielectric, a metal region, an adhesion promoter, a semiconductor wafer or any combination thereof having a patterned hybrid low-k dielectric located directly atop a surface thereof, said patterned hybrid low-k dielectric having an effective dielectric constant of about 2.6 or less and comprising a bottom spun-on dielectric and a top spun-on dielectric which are not separated from each other by a buried layer, wherein said bottom and top spun-on dielectrics have different atomic compositions and at least one of said spun-on dielectrics is porous, and said bottom spun-on dielectric serves as an inherent etch stop layer for said top spun-on dielectric; a polish stop layer located atop said patterned hybrid low-k dielectric; and metal conductor regions formed within said patterned hybrid low-k dielectric.