Patent ID: 6057201
Filing Date: 2000-05-02
Classification: H01L

Abstract:
A method of producing a transistor which comprises the following steps:a) providing a semiconductor material with a semiconductor region of a first conductivity type, and forming a first insulation layer on the semiconductor region of the first conductivity type;b) forming a conductive layer on the first insulation layer, and forming a second insulation layer on the conductive layer;c) structuring the conductive layer and the second insulation layer by anisotropic etching;d) implanting a dopant of a second conductivity type and driving the dopant into the semiconductor region of the first conductivity type, and forming a first zone of a second conductivity type in the semiconductor region of the first conductivity type;e) implanting and driving in a further dopant of the second conductivity type, and forming a second zone of the second conductivity type having a higher concentration of dopant as compared with the first zone;f) forming a third insulation layer and anisotropically etching the third insulation layer back to a level of the semiconductor material such that at least one insulation region remains on the semiconductor material;g) anisotropically etching the semiconductor material in self-adjusted fashion, using the insulation region as a mask, down into the semiconductor region of the first conductivity type;h) introducing a dopant of the first conductivity type at high concentration into the semiconductor region of the first conductivity type; andi) forming a metallizing layer.