Patent ID: 8630316
Filing Date: 2014-01-14
Classification: G06F,H04J,H04L,H04N

Abstract:
1. At a device, a method implemented on a processor, said method comprising: identifying a plurality of correlation events having an initiating timestamp and a receiving timestamp, said correlation events occurring between a first device having a first clock and a second device having a second clock, said plurality of correlation events comprising a first correlation event having said initiating timestamp correlated to said first clock and a second correlation event having said initiating timestamp correlated to said second clock; determining that a solution set for an expression of the differences between said first clock and said second clock is not bounded, the solution set defining a linear relationship between said first clock and said second clock based on said first and second correlation events; in response to determining that said solution set is not bounded: identifying a further correlation event between said first device and said second device; calculating a further linear inequality for said further correlation event; and including said further linear inequality in said solution set; determining that said solution set including said further linear inequality is a bounded solution set; identifying a first event not being one of said plurality of correlation events, said first event having a third timestamp being defined by said second clock; and using said bounded solution set to determine a fourth timestamp from said third timestamp, said fourth timestamp being with respect to said first clock.