Patent ID: 8966229
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. A processor, comprising: an instruction unit which provides instructions for execution by the processor; a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions; and a plurality of execution queues coupled to the decode/issue unit, wherein each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein the plurality of queues comprises: a plurality of execution units coupled to receive instructions for execution from the plurality of execution queues, wherein the plurality of execution units comprises: wherein: wherein the decode/issue unit is configured to, in response to receiving a multi-cycle pipelined instruction, decode the multi-cycle pipelined instruction and determine whether an operand of the multi-cycle pipelined instruction includes a dependency on any instruction in the plurality of execution queues, wherein: