Patent ID: 6696998
Filing Date: 2004-02-24
Classification: H03M

Abstract:
An apparatus for generating at least one digital output signal representative of an analog signal; the apparatus comprising:(a) a plurality of conversion units; each respective conversion unit of said plurality of conversion units including a respective input locus, a respective first summing section coupled with said respective input locus, a respective delay section coupled with said respective first summing section, a respective second summing section coupled with said respective delay section and a respective integrator section coupled with said respective second summing section; each said respective conversion unit receiving a respective sampled analog input signal at said respective input locus; said respective sampled analog input signal being a sampling of said analog signal; each said respective sampled analog signal being phase-offset with respect to other said respective sampled analog signals; each said respective conversion unit treating said respective sampled analog input signal using said respective first summing section, said respective delay section, said respective second summing section, and said respective integrator section to generate a respective digital output signal of said at least one digital output signal; a respective integrator output signal from said respective integrator unit being provided to said respective first summing section; (b) a respective error determination unit coupled with each said respective conversion unit; each said respective error determination unit determining an error associated with said respective integrator output signal; and (c) a respective feedback unit coupled with each said respective error determination unit; a first said respective feedback unit in a first said respective conversion unit being coupled with said respective second summing section in a second said respective conversion unit; a second said respective feedback unit in said second respective conversion unit being coupled with said respective second summing section in said first respective conversion unit; each said respective feedback unit asserting a respective predetermined amount of delay to signals handled by said respective feedback unit.