Patent ID: 7146517
Filing Date: 2006-12-05
Classification: G06F

Abstract:
1. A clock for a computing system comprising: a first pulse shaver, wherein the first pulse shaver receives a clock signal; and a first pin connected to the first pulse shaver to selectively direct the first pulse shaver to reduce a first width of enabling pulses in a first signal generated from the clock signal; wherein the first pulse shaver includes a first pulse path, a second pulse path and means for combining signals on the first and second pulse paths, wherein the first pulse path generates a first pulse signal having a first pulse width in response to the clock signal, wherein the second pulse path is connected to the first pin and generates a second pulse signal having a second pulse width in response to the clock signal when enabled by the first pin, and wherein the means for combining generates the first signal generated from the clock signal having a pulse width greater than the first pulse width but less than the second pulse width when enabled by the first pin.