Patent ID: 7471548
Filing Date: 2008-12-30
Classification: H01L,Y10S

Abstract:
1. An integrated circuit (IC) comprising: a first area containing at least one SRAM cell, wherein said at least one SRAM cell includes at least one nFET and at least one pFET; a second area containing at least one logic nFET and at least one logic pFET; and a continuous stressed liner comprising a compressively stressed silicon nitride located above and adjoining each FET, wherein a first portion of said continuous stressed liner located in said second area above and adjoining said at least one logic nFET is relaxed and includes at least one of Xe ions and Ge ions, a second portion of said continuous stressed liner located in said second area above and adjoining said at least one logic pFET is non-relaxed, and a third portion of said continuous stressed liner located in said first area above and adjoining said at least one nFET and said at least one pFET is relaxed and includes at least one of Xe ions and Ge ions.