Patent ID: 6269031
Filing Date: 2001-07-31
Classification: G11C

Abstract:
A semiconductor memory device comprising:a control signal generator circuit for generating a set signal;a delay circuit connected to said control signal generator circuit for receiving said set signal and delaying said set signal with a predetermined delay time to generate a reset signal;a set/reset latch circuit connected to said delay circuit and said control signal generator circuit for receiving said reset signal and said set signal to generate a column address selecting control signal on the basis of said reset signal and said set signal;a column address decoder circuit connected to said set/reset latch circuit for receiving said column address selecting control signal to generate a column address selecting signal with a pulse width depending on said column address selecting control signal; anda memory cell array connected to said column address decoder circuit for receiving said column address selecting signal to execute a data transfer operation within a rise-time period of said column address selecting signal,wherein said delay circuit is capable of varying said delay time of said reset signal.