Patent ID: 7598558
Filing Date: 2009-10-06
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor integrated circuit device comprising: a semiconductor substrate including a first memory cell formed in a first memory cell forming region of the substrate and a second memory cell formed in a second memory cell forming region of the substrate, the first memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed over the memory cell forming region and a source region and a drain region formed in the substrate, the first n-channel MISFET being arranged in a first direction adjacent to the first p-channel MISFET such that the gate electrode of the first n-channel MISFET is integrally formed with the gate electrode of the first p-channel MISFET by a first common gate electrode extending in the first direction, the second n-channel MISFET being arranged in the first direction adjacent to the second p-channel MISFET such that the gate electrode of the second n-channel MISFET is integrally formed with the gate electrode of the second p-channel MISFET by a second common gate electrode extending in the first direction, the second memory cell including a selecting MISFET and a capacitor element electrically coupled to the selecting MISFET, the selecting MISFET having a gate electrode formed over a circuit element forming region and semiconductor regions formed in the substrate, the semiconductor regions serving as a source region and a drain region of the selecting MISFET; a first insulating film including silicon and nitrogen and formed so as to cover the first common gate electrode and the second common gate electrode, the drain regions of the first and second n-channel MISFETs and the first and second p-channel MISFETs, and the selecting MISFET; a second insulating film formed on the first insulating film so as to cover the first insulating film such that after planarizing a surface of the second insulating film, the second insulating film is etched by using said first insulating film as an etching stopper to form a first opening, a second opening and a third opening, and such that the first insulating film within the openings is etched so as to expose the drain region of the second n-channel MISFET in the first opening, to expose the second common gate electrode and the drain region of the first p-channel MISFET in the second opening, and to expose a semiconductor region of the selecting MISFET in the third opening; a first conductive film formed in the first opening so as to electrically connect to the drain region of the second n-channel MISFET; a second conductive film formed in the second opening so as to electrically connect the second common gate electrode and the drain region of the first p-channel MISFET; and a third conductive film formed in the third opening so as to electrically connect the semiconductor region of the selecting MISFET, wherein the first common gate electrode, the drain region of the second n-channel MISFET, the drain region of the second p-channel MISFET and the first conductive film are electrically connected with each other, and wherein the second common gate electrode, the drain region of the first n-channel MISFET, the drain region of the first p-channel MISFET and the second conductive film are electrically connected with each other.