Patent ID: 8762915
Filing Date: 2014-06-24
Classification: G06F

Abstract:
1. A circuit analysis tool, enabled with software instructions stored in a computer-readable medium and executable by a processor, for die size reduction analysis, the instructions comprising: providing a circuit including: a processor determining a first initial output slack time; when the first initial output slack time is greater than zero, where a positive slack time indicates the occurrence of the second data signal prior to the occurrence of the clock signal, wherein the clock signal is associated with the second circuit element setup time delay, modeling a first circuit element in second die area, less than the first die area, where the second die area is associated with a third delay greater than the first delay; modeling the second data signal equal to the first data signal with the third delay; and, if a first modified output slack time is greater than or equal to zero, wherein the first modified output slack time is the third delay output; if the first modified output slack time is a first value less than zero, a first delay is added to the clock signal that is greater than or equal to the first value.