Patent ID: 6647522
Filing Date: 2003-11-11
Classification: G01R,G11C

Abstract:
A semiconductor device comprising:a plurality of memory circuits comprising a first memory circuit and a second memory circuit; wherein the first memory circuit comprises a first memory having a first address width and a first data width, a first address scan chain connected to the first memory to receive serial scan-in addresses and generate a first address signal corresponding to the first address width, a first signal inverting circuit to receive serial scan-in data, invert the scan-in data according to the first address signal and a pattern control signal, and generate first inverted scan-in data comprising a checker pattern used to arrange bits in a checkerboard format in memory cells of the first memory, and a first data scan chain connected to the first memory to receive the first inverted scan-in data from the first signal inverting circuit and generate a first data input signal corresponding to the first data width; and wherein the second memory circuit comprises a second memory having a second address width differing from the first address width and a second data width differing from the first data width, a second address scan chain connected to the second memory to receive the serial scan-in addresses and generate a second address signal corresponding to the second address width, a second signal inverting circuit to invert the scan-in data according to the second address signal and the pattern control signal and generate second inverted scan-in data comprising a checker pattern used to arrange bits in a checkerboard format in memory cells of the second memory, and a second data scan chain connected to the second memory to receive the second inverted scan-in data from the second signal inverting circuit and generate a second data input signal corresponding to the second data width.