Patent ID: 6486009
Filing Date: 2002-11-26
Classification: G02F,H01L

Abstract:
A method of fabricating a thin-film transistor on an insulation substrate, comprising:forming a first conductive layer, a gate dielectric layer, a silicon layer and a doped silicon layer on the insulation substrate; performing a first step of photolithography and etching on the doped silicon layer, the silicon layer, the gate dielectric layer and the first conductive layer to form a gate and a gate line; forming a second conductive layer over the substrate; performing a second step of photolithography and etching on the second conductive layer and the doped silicon layer to form a source/drain conductive layer, a source/drain line structure at both sides of the gate line, and a source/drain region underlying the source/drain conductive layer; forming a protection layer over the insulation substrate; performing a third step of photolithography and etching on the protection layer so that a plurality of openings are formed to expose the source/drain conductive layer and the source/drain line structure; forming a transparent conductive layer on the protection layer and the openings to couple with the source/drain line structure and the source/drain conductive layer; and performing a fourth step of photolithography and etching on the transparent conductive layer to form a pixel electrode connected with a portion of the source/drain conductive layer, and a portion of the patterned transparent layer electrically connects another portion of the source/drain conductive layer with the source/drain conductive layer.