Patent ID: 6627937
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate containing an impurity of a first conductivity type having a first concentration; a semiconductor layer formed on said substrate, having a main surface, and containing an impurity of the first conductivity type having a second concentration lower than said first concentration; a memory region provided on said semiconductor layer; and a logic circuit region provided on said semiconductor layer at a location different from said memory region, said memory region including a first well region of the first conductivity type formed at said semiconductor layer and having a first bottom plane at a first depth as measured from said main surface, a second well region of a second conductivity type formed at said semiconductor layer to surround said first well region and having a second bottom plane at a second depth less deep than said first depth, as measured from said main surface, and a first bottom well region of the second conductivity type provided at said semiconductor layer in contact with said first and second bottom planes, said logic circuit region including a complementary field effect semiconductor element formed on a main surface of said semiconductor layer.