Patent ID: 8314501
Filing Date: 2012-11-20
Classification: H01L

Abstract:
1. A semiconductor chip package structure, comprising: a first semiconductor chip comprising at least a first conductor unit, the first conductor unit having a first bonding surface and a second bonding surface, the first bonding surface and the second bonding surface being exposed from the first semiconductor chip; a second semiconductor chip comprising at least a second conductor unit, the second conductor unit having a third bonding surface and a fourth bonding surface, the third bonding surface and the fourth bonding surface being exposed from the second semiconductor chip, wherein the third bonding surface is contacted with and electrically connected to the first bonding surface; and a supporting substrate comprising a wire unit for electrically connecting to at least one of the second bonding surface and the fourth bonding surface; wherein the first semiconductor chip comprises a first substrate and a first component layer disposed on the first substrate, the first conductor unit is disposed in the first component layer, the second semiconductor chip comprises a second substrate and a second component layer disposed on the second substrate, and the second conductor unit is disposed in the second component layer.