Patent ID: 9136717
Filing Date: 2015-09-15
Classification: H02J

Abstract:
1. A semiconductor integrated circuit, comprising: a plurality of terminals including at least three terminals forming neighboring pairs of terminals; a plurality of switching devices arranged such that there is one switching device connected directly between each neighboring pair of terminals; a battery voltage detection control circuit that detects a voltage between the terminals of each neighboring pair of terminals, wherein in response to the battery voltage detection control circuit detecting that a voltage across a first neighboring pair of terminals is higher than the voltage across a second neighboring pair of terminals, the battery voltage detection control circuit activates the switching device between the first neighboring pair of terminals to reduce the voltage at the first neighboring pair of terminals by discharging the voltage across the pair of terminals; a plurality of first overvoltage protection devices connected in series, each overvoltage protection device being connected between a corresponding neighboring pair of terminals and protecting a corresponding one of the switching devices from an overvoltage applied between the corresponding neighboring pair of the terminals, wherein each overvoltage protection device is a N-type MOS transistor having a gate and a source connected to each other; a plurality of second overvoltage protection devices, each of the second overvoltage protection devices being connected between every other terminal; and a plurality of third overvoltage protection devices or circuits, each of the third overvoltage protection devices or circuits being connected to terminals that are not connected to the plurality of second overvoltage protection devices.