Patent ID: 9141359
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. A parallel-code optimization system comprising: a siloed program reference identifier to identify, in intraprocedural paths of a computer program, siloed references to lvalues that are free of cross-thread interference using a Procedural Concurrency Graph (PCG); a PCG generator executed by a processor, the PCG generator to wherein the refined PCG includes the initial PCG with the edge identified by the concurrency-type refinement removed and with the lvalue identified by the interference-type refinement removed from the immediate interference set, and wherein the refined PCG is used to: determine a union of immediate interference sets for a selected node, determine a set of lvalues that are immediately accessed by the selected node; and subtract the union of immediate interference sets from the set of lvalues to determine the siloed references; and a non-transitory storage device to store the refined PCG.