Patent ID: 6044489
Filing Date: 2000-03-28
Classification: H04L

Abstract:
An apparatus including a data signal level error detector, comprising:a first data signal detection circuit configured to receive and detect an input data signal which includes a plurality of signal levels representing an N-level data signal and in accordance therewith provide a first data level signal which is asserted when said input data signal level is within a predetermined range of values having a maximum value and a minimum value, and is de-asserted otherwise, whereinsaid input data signal includes, associated therewith,a plurality of sequential intermediate signal levels,a first plurality of sequential extended signal levels each of which is positive with respect to a preceding one of said plurality of sequential intermediate signal levels, anda second plurality of sequential extended signal levels each of which is negative with respect to a preceding one of said plurality of sequential intermediate signal levels,said maximum value corresponds to a first value which is between a preceding one of said plurality of sequential intermediate signal levels and a preceding one of said first plurality of sequential extended signal levels, andsaid minimum value corresponds to a second value which is between a preceding one of said plurality of sequential intermediate signal levels and a preceding one of said second plurality of sequential extended signal levels; anda second data signal detection circuit, coupled to said first data signal detection circuit, configured to receive said first data level signal and in accordance therewith provide one or more signal pulses during said assertion of said first data level signal, wherein said one or more signal pulses are provided during a time period between said assertion and said de-assertion of said first data level signal.