Patent ID: 7023722
Filing Date: 2006-04-04
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells arranged in a memory array; and a plurality of assertion transistors, each of the assertion transistors being provided for each of columns consisting of the memory cells in a bit line direction, wherein each of the memory cells includes: wherein a drain of each of the assertion transistors is connected to the common source line for the drive transistors included in the memory cells located in each column, a source of each of the assertion transistors is supplied with a second potential which is different from the first potential, wherein, during a data write operation in which a bit line pair is selected, only one common source line located in a row that corresponds to the selected bit line pair is allowed to float when the one word line is asserted, by controlling the assertion transistor provided for the column that corresponds to the selected bit line pair to be nonconductive, and wherein, while the common source line for the drive transistors included in the memory cells located in one column is allowed to float, data is written into one of the memory cells by providing two bit lines of one pair with two different potentials whose difference is lower than a difference between the first potential and the second potential.