Patent ID: 8023276
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. A circuit arrangement comprising a plurality of half bridges, each half bridge containing a first chip and a second chip, the first chip and the second chip each having a vertical power transistor, wherein the first and second chips of each of the half bridges are different chips than the first and second chips of the remaining half bridges, wherein load paths of the power transistor of the first chip and of the power transistor of the second chip are connected in series and control inputs of the power transistors are configured to be driven individually, wherein the half bridges are jointly accommodated in one semiconductor package, and wherein, for each of the half bridges, the second chip of the half bridge is mounted on the first chip of the half bridge, wherein for each of the half bridges, the load path of the power transistor of the first chip is electrically connected to the load path of the power transistor of the second chip, respectively via an electrically conductive solder or adhesive connection which connects the first chip in a surface-bonded manner to the second chip.