Patent ID: 8930792
Filing Date: 2015-01-06
Classification: G11B,H03M,H04L

Abstract:
1. A data processing system, the data processing system comprising: a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit, wherein the first data decoder engine is operable to perform variable node updating for a first portion of a codeword and to generate a first sub-message corresponding to the first portion, and the second data decoder engine is operable to perform variable node updating for a second portion of the codeword and to generate a second sub-message corresponding to the second portion, and wherein the common circuit is operable to: shift a combination of both the first sub-message and the second sub-message to yield a shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.