Patent ID: 6639428
Filing Date: 2003-10-28
Classification: G06F,H03K,Y02D

Abstract:
A digital circuit run in conjunction with a system clock signal, the digital circuit comprising:a digital logic circuitry regulated by a clock signal and powered by a system current; a clocking circuitry, communicatively coupled to the digital logic circuitry and the system clock signal, for supplying the clock signal to the digital logic circuitry, clocking circuitry comprising: a power supply monitor circuitry, communicatively coupled to the power supply, providing a signal indicative of current or power consumed by the system; a clock regulation circuitry, communicatively coupled to the power supply circuitry, that outputs the clock signal to the digital logic circuitry in response to the signal indicative of current or power consumed by the system; the clock signal comprising the system clock signal when the signal indicative of current or power consumed by the system is in a first state; and the clock signal comprising a modified clock signal when the signal indicative of current or power consumed by the system is in a second state; wherein the clock regulation circuitry is constructed and arranged to continuously vary the modified clock signal in accordance with the level of system current or power consumed by the digital logic circuitry in relation to the current or power consumed by the system while in the second state, and dynamically speed up or slow down the digital logic circuitry or inhibit clock rate so that the digital logic circuitry is run at a clock rate and computational rate that do not breach a total current or power consumption budget of the system.