Patent ID: 6348812
Filing Date: 2002-02-19
Classification: H03K

Abstract:
A dynamic programmable logic array (DPLA) comprising:at least one logic plane; at least one reprogrammable evaluate module within the at least one logic plane, the at least one reprogrammable evaluate module including a first program input, a second program input, a storage element coupled to the first and second program inputs, an input pass transistor coupled to the output of storage element and an evaluate transistor coupled to the input pass transistor, wherein the input pass transistor including a gate, source and drain, wherein the gate is coupled to the output of the storage element and the source and the drain are coupled to a control input and a gate of the evaluate transistor; and an evaluate disable transistor which includes a gate, source and drain, the gate is coupled to the output of the storage element, the source is coupled to the gate of the evaluate transistor, and the drain is coupled to the ground; and the output of the storage element turns on one of the input pass transistor or the evaluate disable transistor at any given time.