Patent ID: 7370168
Filing Date: 2008-05-06
Classification: G06K,G11C

Abstract:
1. A memory card conforming to a first operation standard, a second operation standard, and a third operation standard based on the first operation standard, comprising: a non-volatile semiconductor memory having a plurality of semiconductor memory cells, wherein each said memory cell is capable of storing information, and a controller that executes operation instructions to the non-volatile semiconductor memory based on received commands, wherein the controller controls a first data output timing that satisfies the first operation standard and the second operation standard, in a first operation mode, and controls a second data output timing that satisfies the third operation standard, in a second operation mode; and wherein the controller includes a data timing switching unit that outputs data at a falling edge of a clock signal in the first data output timing, and outputs data at a rising edge of a clock signal in the second data output timing; wherein the data timing switching unit includes: wherein the data timing switching unit outputs: wherein the output buffer outputs the data based on the output data enable signal to output the data at the rising edge of the clock signal, and outputs the data based on the second latch signal in synchronization with the first latch signal to output the data at the falling edge of the clock signal.