Patent ID: 6040724
Filing Date: 2000-03-21
Classification: H03K,H04L

Abstract:
A bus driver circuit for transmitting data onto a bus, comprising:an input terminal for inputting an input signal;a delay circuit for outputting a delayed signal based on said input signal, said delay circuit generating said delayed signal by receiving at least one selection signal which causes said delay circuit to delay said input signal for one of a plurality of preset delay periods;an output circuit for forming an output signal by superimposing the input signal from said input terminal onto said delayed signal from said delay circuit, so that said output signal has a rise time and fall time which defines a waveform shape; andan output terminal for outputting the output signal from said output circuit to said bus,wherein said one of said plurality of preset delay periods used to generate said delayed signal is selected by said at least one selection signal so that said waveform shape causes said driver circuit to achieve a through rate which is faster than a through rate achieved by selection of any of remaining ones of said plurality of preset delay periods.