Patent ID: 6638812
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A method for producing at least two memory cells for a semiconductor memory, each of the memory cells having a vertical selection transistor and a capacitor, the transistor having first and second doped regions and a channel region, and the capacitor having first and second capacitor electrodes and a dielectric, which comprises:providing layers one above another on a substrate, the layers including a first insulation layer, a higher doped semiconductor layer, and a lower doped semiconductor layer; applying a grid-shaped etching mask; etching a trench structure into the semiconductor layers to form a web surrounded by the trench structure, the web having a side wall, an upper area, and a lower area each disposed in the trench structure; forming the capacitor dielectric by providing a dielectric layer on the side wall in the lower area of the web to surround the web, the higher doped layer forming the first capacitor electrode in the lower area of the web, the upper area of the web underneath the lower doped layer forming the first doped region of the transistor; filling the trench structure with a conductive trench filling to form the second capacitor electrode, the second capacitor electrode being a common capacitor electrode for adjacent ones of the memory cells; forming a second insulation layer on the conductive trench filling in the trench structure; forming a gate electrode of the transistor by providing side edge webs on the web in a region of the lower doped layer, and forming the channel region of the transistor with the lower doped layer; introducing dopant into the upper area of the web to form a doped layer, the doped layer being the second doped region of the transistor; forming a bit line on the web on the doped layer; forming a word line above the bit line; and forming a word line contact connecting the word line to the gate electrode.