Patent ID: 9196587
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a processed semiconductor wafer having a first surface and a second surface, where the processed semiconductor wafer includes integrated circuits formed proximate to the first surface of the processed semiconductor wafer and includes a first conductive layer disposed over the first surface of the processed semiconductor wafer; an integrated circuit die coupled to the second surface of the processed semiconductor wafer with an adhesive material, where the integrated circuit die includes a conductive pad disposed proximate to the second surface of the processed semiconductor wafer; and a via formed from the first conductive layer to the conductive pad and through the first surface of the processed semiconductor wafer to the second surface of the processed semiconductor wafer, where the via includes a conductive material configured to electrically couple the conductive pad of the integrated circuit die to the first conductive layer and the first side of the processed semiconductor wafer.