Patent ID: 9070743
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A semiconductor memory comprising: a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator; a transistor region which is provided in the semiconductor substrate and which includes a second active region surrounded by a second isolation insulator; a memory cell in the memory cell array, the memory cell including a first gate insulating film provided on the first active region, a charge storage layer provided on the first gate insulating film, a first insulator provided on the charge storage layer, and a control gate electrode provided on the charge storage layer via the first insulator; and a first transistor in the second active region, the first transistor including a second gate insulating film provided on the second active region, and a first electrode layer provided on the second gate insulating film, wherein the second isolation insulator includes a first film, and a second film between the first film and the second active region, an upper surface of the first film is located closer to a bottom of the semiconductor substrate than an upper surface of the second film, and an air gap is provided between the upper surface of the first film and an interlayer insulating film above the second isolation insulator.