Patent ID: 7233514
Filing Date: 2007-06-19
Classification: G11C

Abstract:
1. A method for reading a memory cell, wherein the memory cell comprises two source/drain regions and a gate, wherein the source/drain regions are each connected to a respective local bitline, and, wherein one of the source/drain regions of a neighboring memory cell is connected to one of the local bitlines, the other source/drain region of the neighboring memory cell is connected to another local bitline, the method comprising: connecting the local bitline that connects the source/drain region of the memory cell and the source/drain region of the neighboring memory cell to a first global bitline; connecting the local bitline that connects the other source/drain region of the memory cell to a second global bitline; connecting the local bitline that connects the other source/drain region of the neighboring memory cell to one of a plurality of local power rails; applying a gate potential to the gate of the memory cell; applying a potential to the first global bitline and applying another potential to the second global bitline; and measuring the current flowing through the first global bitline.