Patent ID: 8514117
Filing Date: 2013-08-20
Classification: H03M

Abstract:
1. An apparatus comprising: an adder having a first input and a second input, wherein the adder determines a difference between the first and second inputs; an integrator having an input and an output, wherein the input of the integrator is coupled to the adder; a first comparator having an input and an output, wherein the input of the first comparator is coupled to the output of the integrator, and wherein the first comparator is clocked by a first clock signal; a second comparator having an input and an output, wherein the input of the second comparator is coupled to the output of the first comparator, and wherein the second comparator is clocked by a second clock signal; a latch having an input and an output, wherein the input of the latch is coupled to the output of the second comparator, wherein the latch is clocked by the first clock signal; a track-and-hold (T/H) circuit having an input and an output, wherein the input of the T/H circuit is coupled to the output of the second comparator, and wherein the output of the T/H circuit is coupled to the input of the first comparator, and wherein the T/H circuit is controlled by the second clock signal; and a digital-to-analog converter (DAC) having an input and an output, wherein the input of the DAC is coupled to the output of the latch, and wherein the output of the DAC is coupled to the second input of the adder.