Patent ID: 8546269
Filing Date: 2013-10-01
Classification: B82Y,H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising the steps of: providing a wafer having a SOI layer over a BOX layer; etching nanowires and pads into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires; undercutting the BOX layer beneath the nanowires and a portion of the pads; forming a mask present only i) on a top of the pads and ii) in regions beneath a portion of the nanowires and the portion of the pads that are exposed by undercutting the BOX layer; unifying an aspect ratio of width to thickness among all of the nanowires, wherein the mask is configured to prohibit reflow of silicon from the nanowires towards the pads during the unifying step; and thinning the nanowires by oxidation of the silicon in the nanowires, wherein the steps of the method are carried out in the order presented.