Patent ID: 9190272
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: providing a substrate including a first region and a second region; forming dummy gate patterns on the substrate, each of the dummy gate patterns comprising a first gate insulating layer, a dummy layer, and a hard mask; forming an interlayer insulating layer on the substrate to expose top surfaces of the dummy gate patterns; removing the hard mask and the dummy layer to form a first trench and a second preliminary trench exposing the first gate insulating layer on the first and second regions, respectively; forming a photoresist pattern on the first region provided with the first trench to expose the second preliminary trench on the second region; removing a portion of the first gate insulating layer from the second preliminary trench to form a second trench exposing a portion of the substrate; cleaning the portion of the substrate exposed by the second trench using an oxide etching solution; removing the photoresist pattern from the first region; forming a second gate insulating layer on the portion of the substrate exposed by the second trench; forming gate electrodes on the first and second gate insulating layers; and forming spacers after the forming the dummy gate patterns and before the forming the interlayer insulating layer, wherein the spacers contact sidewalls of the dummy gate patterns, the removing the portion of the first gate insulating layer from the second preliminary trench includes partially etching a sidewall of the spacers on the second region without etching the spacers on the first region, and the sidewall of the spacers on the second region is tapered compared to a sidewall of the spacers on the first region after the removing the portion of the first gate insulating later from the second preliminary trench.