Patent ID: 6995037
Filing Date: 2006-02-07
Classification: H01L

Abstract:
1. A method for fabricating a high performance, high I/O ball grid array substrate, intended for two patterned metal layers and integrated circuit flip-chip assembly, comprising the steps of: providing an electrically insulating layer having a first and a second surface; forming a plurality of via holes in said insulating layer and filling said holes with electrically conductive material; attaching one of said metal layers to said first surface, said metal layer intended to provide electrical ground potential; forming a plurality of electrically insulated openings in said metal layer, said openings intended for outside electrical contacts; attaching the other of said metal layers to said second surface, said metal layer intended to provide electrical signal and power potentials; configuring portions of said metal layer as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, thereby creating contact between selected signal and power lines and said vias; forming an insulating protective film over the exposed surface of said ground layer, and an insulating film over the exposed surfaces of said signal and power lines; and forming pluralities of openings in both said insulating films, and filling said openings with solderable metal, thereby creating attachment sites for outside solder balls and for chip solder bumps.