Patent ID: 7735036
Filing Date: 2010-06-08
Classification: G06F

Abstract:
1. A computer-implemented method of identifying sub-circuits in circuit designs comprising: receiving a selection of a sub-circuit; generating a graph that specifies a topology for the sub-circuit; specifying a match expression for the sub-circuit, wherein the match expression characterizes matching properties of components of the sub-circuit; using a computer for modifying the match expression to change the matching properties of components of the sub-circuit; using the computer for producing an information structure in a computer-readable medium, wherein the information structure associates the graph with the modified match expression and the information structure includes a constraint group associated with the sub-circuit, the constraint group including one or more constraints for components of the sub-circuit; using the information structure to identify in a circuit design one or more sub-circuit instances having a topology corresponding to the graph and components corresponding to the modified match expression; using a graphical user interface to present one or more of the identified sub-circuit instances; and using the graphical user interface to receive instruction as to application of the constraint group to the one or more presented sub-circuit instances.