Patent ID: 8019985
Filing Date: 2011-09-13
Classification: G06F

Abstract:
1. A data-processing arrangement comprising: a main processor that has been provided with a system-program code that, when an application-program code needs to be replaced, that causes the main processor to write an updated application-program code into a shared memory, and that causes the main processor to write an address indication, which indicates where the application-program code has been written into the shared memory, into a predefined memory location or that causes the main processor, when the application program code does not need to be replaced, to write a jump instruction having a jump address as an address in the application-program code under which the first code of the most recent version of the application-program code has been previously stored; an auxiliary processor that has been provided with a startup-program code that causes the auxiliary processor to retrieve the address indication from the predefined memory location so as to subsequently transfer the application-program code from the shared memory to an application-program memory that belongs to the auxiliary processor, wherein the startup-program code causes the auxiliary processor to jump to the application-program code which is present in the application-program memory according to the jump instruction.