Patent ID: 8048813
Filing Date: 2011-11-01
Classification: H01L

Abstract:
1. A method of forming an integrated circuit structure, the method comprising: providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask, wherein during the step of baking, the hard mask is not covered by any additional layer, and is exposed; after the step of baking, forming a spacer layer comprising a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask; removing the first portion of the spacer layer; removing the hard mask, with the second portion and the third portion of the spacer layer comprising remaining portions un-removed; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.