Patent ID: 6370607
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A data processing device controlled by a CPU and comprising:an interrupt output for producing an interrupt request signal supplied to said CPU, an interrupt register for storing interrupt bits representing interrupt events, an interrupt control register for storing an interrupt output enable bit to enable said interrupt output when said interrupt output enable bit is in a first logic state, and to disable said interrupt output when said interrupt output enable bit is in a second logic state, and an interrupt disabling circuit for automatically setting said interrupt output enable bit into said second state when said CPU performs read access to said interrupt register after receiving said interrupt request signal; wherein said interrupt disabling circuit is responsive to an interrupt register address signal decoded by an address decoder; wherein said interrupt disabling circuit is further responsive to a read signal indicating that the CPU performs a read operation; wherein said interrupt disabling circuit comprises an AND gate for receiving said interrupt register address signal and said read signal and producing an interrupt register read signal indicating that the CPU performs read access to the interrupt register; wherein said interrupt register read signal is supplied to said interrupt control register for setting said interrupt output enable bit into said second state.