Patent ID: 6384624
Filing Date: 2002-05-07
Classification: G06N

Abstract:
A logical operational circuit, comprising three or more neuMOS inverters having a CMOS structure having a floating gate and one or two or more input gates capacitively coupled with said floating gate;wherein the output of a third neuMOS inverter is connected via a capacity with the floating gate of a second neuMOS inverter, and the output of said second neuMOS inverter is connected via a capacity with the floating gate of a first neuMOS inverter; said logical operational circuit having the smallest installation area as chosen from a plurality of installation areas approximated by areas of rectangles on the basis of the layouts of said neuron MOS inverters; and a plurality of input signals are connected to at least one or more of the input gates of said neuMOS inverters within the circuit, predetermined logical operations are conducted with respect to said plurality of input signals in which each neuMOS gives an unequal predetermined weight to at least one input signal and compares an added value of the input signals to a threshold value, and the results thereof are made the output of said first neuMOS inverter.