Patent ID: 7574636
Filing Date: 2009-08-11
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory regions; an address decoding portion for decoding an address applied from an external portion for simultaneously selecting the plurality of memory regions during a test read operation; a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation; a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation; and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.