Patent ID: 6399448
Filing Date: 2002-06-04
Classification: H01L,Y10S

Abstract:
A method for forming a multiple thickness gate oxide layer, comprising the steps of:a. providing a semiconductor substrate having a silicon surface; said semiconductor substrate having a first area, a second area, and a third area; b. forming a sacrificial oxide layer over said semiconductor substrate; c. implanting nitrogen ions into said first area while masking said second area and said third area to form a first region in which thermal oxide growth is retarded; d. implanting argon ions into said second area while masking said first area and said third area to form a second region in which thermal oxide growth is enhanced; e. removing said sacrificial gate oxide layer; f. thermally growing a gate oxide layer over said first area, said second area, and said third area; said gate oxide layer having a first thickness over said first region, a second thickness over said second region, and a third thickness over said third area; wherein said second thickness is greater than said first thickness and said third thickness, and said third thickness is greater than said first thickness; and g. forming gates on the different thickness oxide layers; whereby the gates can be operated at different voltages.