Patent ID: 7286402
Filing Date: 2007-10-23
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix including a plurality of word lines; a first transistor of a first conductivity type, a source or drain of the first transistor being connected to each of the word lines; a second transistor of a second conductivity type, opposite to the first conductivity type, a drain of the second transistor being connected to a gate of the first transistor; and a third transistor of the first conductivity type, a source of the third transistor being connected to the gate of the first transistor, wherein a voltage level of a source of the second transistor is different from a voltage level of a drain of the third transistor in at least one of a data read operation, a data program operation or a data erase operation, and a gate of the second transistor and the drain of the third transistor have different voltage levels, the gate of the second transistor becoming high logic level and low logic level when the drain of the third transistor becomes a low logic level and high logic level, respectively, in at least one of a data read operation, a data program operation or a data erase operation.