Patent ID: 8611379
Filing Date: 2013-12-17
Classification: H03K,H03M,H04L

Abstract:
1. A receiver, comprising: a slicer circuit, configured to latch an input data stream at times determined by a first amplified clock signal, the first amplified clock signal having been produced by a first resonant clock amplifier amplifying a first clock signal at a first frequency; a de-multiplexer circuit, configured to de-multiplex the data stream latched by the slicer circuit at times determined by a second amplified clock signal, the second amplified clock signal having been produced by a second resonant clock amplifier amplifying a second clock signal at a second frequency that is a sub-multiple of the first frequency; and a clock and data recovery (CDR) circuit that adjusts the phase of the first clock signal so that the first amplified clock signal is approximately centered within a data window of the input data stream at the slicer circuit; wherein at least one of the first resonant clock amplifier or the second resonant clock amplifier includes a programmable delay element.