Patent ID: 7216321
Filing Date: 2007-05-08
Classification: G06F

Abstract:
1. A method, for recognizing a pattern in register transfer level (RTL) description of an integrated circuit (IC) design, comprising: a) identifying a pattern correspondence element in a pattern instance; b) building a pattern tree corresponding to the pattern instance; c) defining a list of candidate design correspondence elements in a design instance of the IC, wherein rare design correspondence elements are chosen from the list for comparison at a highest priority; and d) iteratively, for each element in said list of candidate design correspondence elements, comparing each rank in a tree representation of said design instance built around said each design correspondence element with corresponding rank in said pattern tree; wherein the comparing is performed using a sub-process comprising: wherein said child node list comprises terminals of said design instance; wherein, when comparing, nodes in said list of pattern nodes are matched against nodes in said child node list according to said nodes' order in said list of pattern nodes and said child node list; wherein said nodes are considered matched if said nodes have the same identification name; wherein said identification name comprises at least a terminal name; and wherein a report is generated indicating matched nodes.