Patent ID: 8086924
Filing Date: 2011-12-27
Classification: G01R

Abstract:
1. A method for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns comprising the steps of: using a voltage and frequency timing control and determining a passing operating region and a failing operating region for a device under test; applying an LBIST test pattern to the device under test and applying multiple system clock sequences and varying voltage and frequency timing parameters in the passing operating region for the device under test and unloading scan chain data; applying the LBIST test pattern to the device under test and applying multiple system clock sequences and varying voltage and frequency timing parameters in the failing operating region for the device under test and unloading scan chain data; comparing the unload data from the passing operating region and the failing operating region; identifying each latch having different results as a potential AC defective latch; and sending the identified potential AC defective latches to a Physical Failure Analysis system.