Patent ID: 6656768
Filing Date: 2003-12-02
Classification: A43B,B81B,B81C,H01L

Abstract:
A method of fabricating land-grid array devices for semiconductor chips having an integrated circuit including a plurality of micromechanical components configured in a plane in the central portion of said chip and a plurality of metallic terminals disposed in peripheral portions encircling said chip, comprising:providing a wafer having a surface including a plurality of said chips; coating said wafer surface with a protective material; selectively etching said protective coating, exposing said terminals of each of said chips; depositing one solder ball on each of said exposed terminals; separating the resulting composite structure into discrete chips; providing an electrically insulating substrate having first and second surfaces and an opening, said surfaces being substantially parallel to each other, a first plurality of metallic contact pads disposed on said first surface in proximity to said opening, and a second plurality of metallic contact pads disposed on said first surface remote from said opening; mounting one of said discrete chips on said first plurality of substrate contact pads by forming solder joints, spaced apart by a gap; controlling the height of said solder joints to maintain uniformity, thereby positioning said substrate in a plane parallel to said components plane; filling said gap with a polymeric encapsulant, surrounding said opening by a continuous frame of encapsulant; removing said protective material, thereby exposing the surfaces of said components; and attaching a lid to said second substrate surface, thereby positioning said lid in a plane parallel to said plane of said components.