Patent ID: 8624761
Filing Date: 2014-01-07
Classification: H03M

Abstract:
1. A method, comprising: receiving a plurality of digital signals from a detector; successively multiplexing the plurality of digital signals to generate a serialized signal with a data rate approximately 4 Gigabit per second (Gb/s) or greater using integrated circuits with a transistor size of at least 0.1 micrometers (μm); generating a first clock signal for a final multiplexer that generates the serialized signal; generating a complementary clock signal based, at least in part, on the first clock signal; detecting an error in phase between the first clock signal and the complementary clock signal; and generating a phase-shifted complementary clock signal based on the detected error in phase between the first clock signal and the complementary clock signal, wherein the final multiplexer uses the first clock signal and the phase-shifted complementary clock signal to generate the serialized signal with the data rate approximately 4 Gigabit per second (Gb/s) or greater.