Patent ID: 8507373
Filing Date: 2013-08-13
Classification: H01L

Abstract:
1. A semiconductor device comprising a DRAM region and a logic region embedded together therein, said semiconductor comprising: a substrate comprising said DRAM region and said logic region formed therein; a first transistor formed in said DRAM region of said substrate, and comprising a first source/drain region, said first source/drain region comprising: a second transistor formed in said logic region of said substrate, and comprising a second source/drain region, said second source/drain region comprising: wherein each of said first source/drain region and said second source/drain region of said substrate comprises a suicide layer respectively formed in a surficial portion thereof, said first source/drain region has a deepest junction depth which is determined by said first impurity ion contained by said first source/drain region, said second source/drain region has a deepest junction depth which is determined by said first impurity ion contained by said second source/drain region, and said deepest junction depth of said first source/drain region is deeper than said deepest junction depth of said second source/drain region.