Patent ID: 7864570
Filing Date: 2011-01-04
Classification: G11C,H01L

Abstract:
1. An apparatus for programming a memory system, said system comprising strings of charge storage transistors for storing different charge states, said strings including a first and a second string each connected between one of a plurality of bit lines and a source line and controlled by common word lines, said apparatus comprising: a circuit programming the system by applying a program voltage to the word lines, one selected word line at a time, to program all of the transistors in the first string; said circuit coupling first boosting voltage level(s) to at least some of the transistors in the second string between said selected word line and said one bit line to boost electrical potential(s) of channel regions of transistors in the second string to a value or values closer to the program voltage to reduce program disturb; said circuit coupling at least one isolation second voltage level that is less than the first voltage level(s) to at least one isolation charge storage transistor having a source and drain in the second string between the selected word line and the source line, said second voltage level being such that a first channel area of the second string on the source side of the at least one isolation transistor is electrically isolated from a second channel area of the second string on the drain side of the at least one isolation transistor, said at least one isolation charge storage transistor separated from the selected word line by at least two word lines; and said circuit coupling third voltage level(s) to the at least two word lines between the selected word line and the isolation transistor, wherein one of the third voltage level(s) coupled to one of the at least two word lines is less than the first voltage level(s), to reduce program disturb, wherein said circuit programs the system by applying the program voltage to the word lines sequentially from the word lines located near the source line to those located near said one bit line, so that the selected word line is at positions at decreasing distances from said one bit line as the programming progresses, and wherein position of the at least one isolation transistor is substantially stationary when the programming applies the program voltage sequentially to the word lines located between said one bit line and a predetermined location between the source line and said one bit line.