Patent ID: 7669320
Filing Date: 2010-03-02
Classification: H01L,H05K,Y10T

Abstract:
1. A method of fabricating a cavity IC substrate comprising the steps of: selecting a copper base—step (a); (I) applying a barrier metal layer; (II) applying a first feature layer; (III) applying a first layer of vias; (IV) applying a first layer of insulating material around the copper features and vias; (V) applying a second barrier metal layer; (VI) applying a second layer of copper features; (VII) applying a second layer of vias; (VIII) applying a second layer of insulating material around the copper features and vias; (IX) applying a third layer of copper features to form a multilayered structure; (X) applying terminations on upper surface of the multilayered structure; (XI) forming a cavity in the underside of the multilayered structure; (XII) terminating contacts in the cavity; (XIII) etching away the remainder of the copper base; and (XIV) terminating the exposed conduits.