Patent ID: 9015217
Filing Date: 2015-04-21
Classification: G06F

Abstract:
1. A circuit comprising: a first table storing a first plurality of values and a second plurality of values corresponding to a function implemented by the circuit, wherein the first plurality of values comprise a value of the function at a plurality of selected points, and wherein the second plurality of values comprise a value of the first derivative of the function at the plurality of selected points, wherein the first table is coupled to receive at least a portion of an input operand to the function and is configured to output a first value of the first plurality of values and a second value of the second plurality of values; multiply-add circuitry coupled to the first table, and the multiply-add circuitry is configured to multiply the second value by a difference between the input operand and a first selected point of the plurality of selected points that corresponds to the first value and the second value, and wherein the multiply-add circuitry is configured to add a result of the multiplication to the first value; and circuitry configured to compute the difference between the input operand and the first selected point, wherein the first selected point is at a center of an interval of input operand values over which the first value and the second value are used, and wherein the circuitry is configured to provide a plurality of least significant bits of the input operand as the difference if the difference is positive, and wherein the difference is a one's complement of the plurality of least significant bits if the difference is negative.