Patent ID: 8824974
Filing Date: 2014-09-02
Classification: H01L,H03K,H04B

Abstract:
1. A semiconductor integrated circuit device comprising: an antenna node coupled to an antenna; a voltage supply circuit including a first resistive element, a second resistive element and a voltage supply node coupled to the first and second resistive elements; a plurality of signal nodes including a first signal node for a transmission signal and a reception signal, a second signal node for the reception signal and a third signal node for the transmission signal; and a plurality of transistor circuits including a first transistor circuit, a second transistor circuit and a third transistor circuit, each having a triple-gate, two-stage configuration, wherein the first transistor circuit is coupled between the first signal node and the antenna node, includes a first source-drain resistive element coupling between sources and drains, and is configured to switch between coupling/decoupling the first signal node and the antenna node, wherein the second transistor circuit is coupled between the second signal node and the antenna node, includes a second source-drain resistive element coupling between sources and drains, and is configured to switch between coupling/decoupling the second signal node and the antenna node, wherein the third transistor circuit is coupled between the third signal node and the antenna node, includes a third source-drain resistive element coupling between sources and drains, and is configured to switch between coupling/decoupling the third signal node and the antenna node, wherein the voltage supply circuit is coupled between the first signal node and the second signal node, wherein the first signal node is coupled to the first resistive element of the voltage supply circuit, wherein the second signal node is coupled to the second resistive element of the voltage supply circuit, wherein the voltage supply circuit is configured to supply voltage to the first and second signal nodes through the first and second resistive elements, respectively, and wherein the third transistor circuit is turned ON and the first and second transistor circuits are turned OFF, when the transmission signal is transmitted from the third signal node.