Patent ID: 9009415
Filing Date: 2015-04-14
Classification: G06F

Abstract:
1. A memory circuit, comprising: multiple storage elements for storing values; and access circuitry coupled to the multiple storage elements forming at least one information pathway for moving values among the multiple storage elements and supporting a move-to-front network and an ordered push-back network, wherein requested values provided in response to requests containing addresses corresponding to the requested values, wherein the requested values may be stored in and retrieved from any of the multiple storage elements and are moved to a front-most one of the multiple storage elements along the move-to-front network in response to the requests prior to accessing the requested values from an interface coupled to the front-most storage element, wherein the values stored in remaining ones of the multiple storage elements are swapped backward between adjacent ones of the multiple storage elements in order along the at least one information pathway according to the push-back network at each access to locations other than the front-most location so that the values are stored in the multiple storage elements along the at least one information pathway according to most-recent access, wherein a least-recently-accessed value is either stored in a front-most empty one of the storage elements or is pushed out of the memory circuit to a backing store interface, and wherein the requested values are moved according to the move-to-front network in a different order than a reverse order of the push-back network, whereby individual ones of the requested values are not moved through at least some of their adjacent multiple storage elements in the reverse order of the push-back network during their movement to the front-most one of the multiple storage elements.