Patent ID: 6740920
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A vertical transistor formed in well disposed in a semiconductor substrate, said well having a substantially uniform lateral well concentration of implanted well dopant parallel to a surface of said semiconductor, comprising:a upper transistor electrode formed in a top level of said transistor; a lower transistor electrode formed in a lower level of said transistor; a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate; a threshold dopant distribution of dopant disposed in said transistor body, said threshold dopant distribution having a peak adjacent said gate dielectric and a lower value of threshold dopant concentration less than said lateral well concentration away from said gate dielectric; and a transistor gate disposed adjacent said gate dielectric on a side opposite said transistor body.