Patent ID: 7573968
Filing Date: 2009-08-11
Classification: H03L,H04L

Abstract:
1. A data transmission circuit, comprising: a first clock generating circuit that generates a first clock; a second clock generating circuit that generates a second clock, which is different from the first clock; a serial interface circuit that supplies an output signal in synchronization with the first clock; and a latch circuit that latches the output signal, supplied from the serial interface circuit, in synchronization with the second clock, to generate a transmission data to be transmitted, wherein the second clock generating circuit comprises: 1) a clock generating circuit, that generates a plurality of clock signals having a predetermined cycle corresponding to the first clock; and 2) a clock selecting circuit, which selectively supplies one from the plurality of clock signals to the latch circuit as the second clock, wherein the plurality of clock signals are phase-shifted from each other, and wherein the second clock generating circuit further comprises a detecting circuit that detects a condition of the first clock and generates a selecting signal, which is to be used for selecting one of the plurality of clock signals at the clock selecting circuit.