Patent ID: 9184299
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate electrode layer; a gate insulating layer adjacent to the gate electrode layer; and an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, wherein a carrier concentration of the oxide semiconductor layer is less than 1×10 wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less, wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, wherein the oxide semiconductor layer comprises indium and zinc, wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×10 wherein an off current per micrometer in a channel width is 100 aA/μm or less when a drain voltage of 1 V to 10 V is applied.