Patent ID: 6605840
Filing Date: 2003-08-12
Classification: G11C,H01L

Abstract:
A scalable multi-bit flash memory cell, comprising:a semiconductor substrate of a first conductivity type; a cell region including an active region and two shallow-trench-isolation (STI) regions being formed on said semiconductor substrate and dividing into three regions: a gate region being formed between a first-side region and a second-side region, wherein said gate region is defined by a masking photoresist step and is therefore scalable; a common-diffusion region of a second conductivity type being separately formed in said active region of said first-side region and said second-side region using said gate region as an implantation mask; a flat bed being separately formed in said first-side region and said second-side region, wherein said flat bed is formed by said common-diffusion region and etched raised field-oxide layers over said two STI regions; a sidewall-oxide spacer being separately formed over each sidewall of said gate region and on a portion of said flat bed; a conductive layer acting as a bit line being separately formed over said flat bed outside of said sidewall-oxide spacer; a planarized thick-oxide layer being formed over said conductive layer and said sidewall-oxide spacer; two stack-gate transistors being separately formed in the side portions of said gate region and one select-gate transistor being formed between said two stack-gate transistors, wherein each of said two stack-gate transistors comprises from top to bottom a sidewall dielectric spacer formed over a sidewall created by said sidewall-oxide spacer and said planarized thick-oxide layer, an elongated control-gate layer over an intergate dielectric layer, and an integrated floating-gate layer; wherein said integrated floating-gate layer comprises a major floating-gate layer being formed on a thin tunneling-dielectric layer and two extended floating-gate layers being separately formed on a portion of nearby raised field-oxide layer formed on each of said two STI regions; a gate-dielectric layer being formed over a semiconductor surface between said two stack-gate transistors, said two stack-gate transistors and their inner sidewalls, and said planarized thick-oxide layers in said first-side region and said second-side region; and a word line being patterned above said active region and transversely to said elongated control-gate layer, wherein said word line comprises from top to bottom a hard masking layer over a metal layer and a planarized conductive island being formed over said gate-dielectric layer and between said two stack-gate transistors.