Patent ID: 6650565
Filing Date: 2003-11-18
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory cell array which includes a plurality of memory cells arranged in a matrix form on a semiconductor substrate, each of the memory cells including a MISFET which has a source, a drain, a channel body between the source and the drain and a gate electrode formed on the channel body, the channel body being in an electrical floating state, each of memory cells having a first state in which the number of the stored majority carriers is larger in the channel body and a second state in which the number of the stored majority carriers is smaller in the channel body; a plurality of word lines, each of which is connected to the gate electrodes of the memory cells arranged in a first direction: a plurality of first bit lines, each of which is connected to the drains of the memory cells arranged in a second direction which intersects the first direction, the bit lines being formed in a first wiring layer located above the semiconductor substrate; and a second bit line which is formed in a second wiring layer located above the first wiring layer, the second bit line being connected to the first bit lines via bit line switches.