Patent ID: 7869274
Filing Date: 2011-01-11
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cell arrays having a plurality of memory cells two-dimensionally arranged, each of the memory cell comprising a source, a drain, and a gate, including a floating body in an electrically floating state, and storing data based on number of carriers within the floating body; a plurality of word lines connected to the gates of the memory cells and arranged towards a first direction; a plurality of first bit lines and a plurality of second bit lines respectively connected to the sources or the drains of the memory cells, and arranged alternately towards a second direction intersecting with the first direction; first sense amplifiers arranged in a first interval of an arrangement of the memory cell arrays, each first sense amplifier being connected to the first bit lines respectively corresponding to two memory cell arrays provided at both sides of the first sense amplifier, each first sense amplifier detecting data from one of the two memory cell arrays on the basis of reference data from the other of the two memory cell arrays; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each second sense amplifier being connected to the second bit lines respectively corresponding to two memory cell arrays at both sides of the second sense amplifier, each second sense amplifier detecting data from one of the two memory cell arrays on the basis of reference data from the other of the two memory cell arrays; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays.