Patent ID: 8988129
Filing Date: 2015-03-24
Classification: H03K

Abstract:
1. A level shifter comprising: a first transistor comprising a first current electrode coupled to a first voltage reference, a second current electrode coupled to a first output signal node, and a control electrode to receive a control signal responsive to a first clock signal; a second transistor comprising a first current electrode coupled to the first output signal node, a second current electrode, and a control electrode responsive to a second clock signal; a third transistor comprising a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to a second voltage reference, and a control electrode to receive a first data input signal; and wherein the level shifter is configured to precharge the first output signal node to a first voltage during a precharge phase and to selectively, based on a state of the first data input signal, perform one of: maintaining the first output signal node at the first voltage during an evaluate phase and transitioning the first output signal node to a second voltage during the evaluate phase.