Patent ID: 6161120
Filing Date: 2000-12-12
Classification: G06F

Abstract:
An apparatus for performing a division operation, comprisinga first scaling unit having a first input for a K-bit raw divider, and an output for a scaled divider having a reduced bit widtha second scaling unit having a second input for a L-bit raw dividend, and an output for a scaled dividend having a reduced bit width,a division unit having first and second input for a scaled divider and a scaled dividend respectively, and an output for a N-bit division result, wherein N<K and N<L, and N, K and L being positive integers,the scaled divider being a N-bit value comprising the first active most significant bit (MSB) and N-1 subsequent less significant bits (LSB) from the raw divider, the first scaling unit further comprising an output for providing a scaling information indicating the first active MSB bit location in the raw divider,the second scaling unit being arranged to add N in active MSB-bits into the raw dividend in order to provide an extended dividend, and responsive to the scaling information for selecting the most significant bit indicated by the scaling information and 2N subsequent less significant bits from the extended dividend to provide a 2N-bit scaled dividend.