Patent ID: 6574273
Filing Date: 2003-06-03
Classification: H04N

Abstract:
A MPEG video decoding system having a very long instruction word (VLIW) processor in a core processor with a data cache, a data stream decoder having a memory buffer and an output storage device, wherein the decoder and output storage device are each connected to the core processor by respective data transfer units, and the MPEG video decoding system includes microprocessor executable process steps, comprising:a first block of the process steps for controlling the operation of the VLIW having included therein all data transfer waits and all data transfer continues, wherein all execution operations of the executable process steps are contained in a single trace, wherein the VLIW operations trace includes motion vector reconstruction commands for a first macroblock, motion compensation and inverse transformation commands for a third macroblock occurring continually without any waits or data transfer channel operation during the process step execution.