Patent ID: 6415308
Filing Date: 2002-07-02
Classification: G06F,H03M

Abstract:
For use in a processor having integer and floating point execution cores, logic circuitry for converting negative numbers from floating point notation to integer notation, comprising:a shifter that receives a number in floating point notation and shifts a fraction portion of the received number as a function of an exponent portion thereof to yield a shifted fraction portion and rounding data; a one's complementer, coupled to the shifter, that inverts the shifted fraction portion to yield an unincremented inverted shifted fraction portion; an incrementer, coupled to the one's complementer, that increments the unincremented inverted shifted fraction portion to yield an incremented inverted shifted fraction portion; and a multiplexer, coupled to the one's complementer and the incrementer, that selects one of the unincremented inverted shifted fraction portion and the incremented inverted shifted fraction portion based on the rounding data thereby to yield the received number in integer notation.