Patent ID: 7692439
Filing Date: 2010-04-06
Classification: G01R,H01L

Abstract:
1. A structure representative of a conductive interconnect in a microelectronic element for purposes of modeling stress-induced degradation, comprising: a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction transverse to said width, and a thickness in a vertical direction extending between said upper surface and said lower surface; a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end; a lower element consisting essentially of at least one of conductive or semiconductive material in contact with said bottom end of said lower via; an upper metallic via in at least substantial vertical alignment with said lower conductive via such that a line extending in said vertical direction through said metallic plate intersects said upper metallic via and said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times smaller than a larger one of said length of said metallic plate and said width of said metallic plate; and an upper metallic line element in contact with said top end of said upper metallic via.