Patent ID: 6955952
Filing Date: 2005-10-18
Classification: H01L

Abstract:
1. A method of fabricating an N channel metal oxide semiconductor (NMOS) device and a P channel metal oxide semiconductor (PMOS) device on the same semiconductor substrate, featuring channel regions comprised with biaxial strained layers, comprising the steps of: providing a silicon on insulator (SOI) substrate wherein a first silicon layer resides on a silicon oxide layer; performing a bond breaking or relaxation procedure near the interface of said first silicon layer and said silicon oxide layer, forming a freely accommodating interface; forming a silicon-germanium (SiGe) layer on said first silicon layer; forming a second silicon layer on said SiGe layer; selectively growing a third silicon layer on a second portion of said second silicon layer in a region of said semiconductor substrate to be used for said NMOS device, resulting in a fourth silicon layer comprised of said third silicon layer and the underlying second silicon layer, located in said NMOS region; forming a gate insulator layer; and forming a MOSFET device structure comprising of a gate structure and source and drain regions adjacent to said gate structure.