Patent ID: 8203206
Filing Date: 2012-06-19
Classification: H01L,H05K

Abstract:
1. An integrated circuit device, comprising: at least one layer forming a plane and having a plurality of interconnects passing through at least a portion of the layer; the interconnects having a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair with conductors arranged next to each other in a first direction and a second differentially driven signal conductor pair arranged in a second direction substantially perpendicular to the first direction, the arrangement pattern includes the second differentially driven signal conductor pair disposed substantially equidistant from each of the first differentially driven signal conductor pair, a first conductor of the second differentially driven signal conductor pair is spaced by a first distance from each conductor of the first differentially driven signal conductor pair, a second conductor of the second differentially driven signal conductor pair is spaced by a second distance from each conductor of the first differentially driven signal conductor pair such that the first distance and the second distance are different, and a ground structure including at least two lines running parallel to the plane.