Patent ID: 6829179
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A semiconductor storage device comprising:a first reference voltage terminal which supplies a first potential that is a predetermined logic level; a second reference voltage terminal which supplies a second potential that is lower than the first potential, and that is a logic level different from the predetermined logic level; a first node; a first control transistor which is connected between a bit line and said first node, and whose control terminal is connected to a word line; a data retention circuit which includes a first transistor that is connected between said first node and said second reference voltage terminal, and that has its control terminal connected to a second node, and a first inverter that includes a second transistor connected between said second node and said second reference voltage terminal, having its input terminal connected to said first node, having its output terminal connected to the control terminal of said first transistor, and outputting to said output terminal a voltage correspondent to the logic level different from the logic level inputted to said input terminal; and a substrate potential control circuit which selectively alters a substrate potential of said first transistor so as to make a threshold voltage of said first transistor higher as compared with threshold voltages of said first control transistor and said second transistor.