Patent ID: 6661859
Filing Date: 2003-12-09
Classification: H03K

Abstract:
A synchronizer system for providing a source-synchronized clock bus for transferring a signal from a sending chip in a capture clock domain to an internal clock domain, said synchronizer comprising:at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal, wherein the at least one storage latch is coupled to the at least one capture latch, and a multiplexer coupled between an output of the at least one storage latch and an input of an internal latch in the internal clock domain, wherein the multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, a control signal generator receiving strobe signals from the sending chip as inputs and generating first and second groups of control signals as outputs, wherein propagation of the signal from said at least one capture latch to said internal latch via said at least one storage latch is controlled in response to said strobe signals and said first group of control signals, and wherein said control signal generator derives said first group of control signals from said second group of control signals, and wherein said control signal generator derives said second group of control signals from the strobe signals, such that any significant delay variation is eliminated and signal separation is increased.