Patent ID: 6756826
Filing Date: 2004-06-29
Classification: H03K

Abstract:
A buffer circuit comprising:an output drive transistor having a control input, first and second lower value current sources of opposite polarities, a first switch, when on, connects the first lower value current source to the control input, a second switch which, when on, connects the second lower value current source to the control input, first and second higher value pulsed current sources of opposite polarities, both of said pulsed current sources connected to the control input, where the first pulsed current source is of the same polarity as the first lower value current source, and the second pulsed current source is of the same polarity as the second lower value current source, an input signal having a first state where the first switch is turned on and a second state where the second switch is turned on, a timing circuit activated by edge transitions of the input signal, the timing circuit having outputs for activating both said higher value pulsed current sources, wherein the first switch and the first higher value pulsed current source are both turned on substantially simultaneously, and the second switch and the second higher value pulsed current source are both turned on substantially simultaneously.