Patent ID: 8112174
Filing Date: 2012-02-07
Classification: G06F

Abstract:
1. A processor for invalidating a mapping of at least one logical address to at least one absolute address, the processor comprising: a plurality of copies of a translation lookaside buffer (TLB), the TLB configured to store entries that comprise mappings of logical addresses to absolute addresses; logic for independent indexing of each copy of the TLB, the indexing for each copy of the TLB comprising reading and outputting at least a portion of an entry via an output port located on the copy of the TLB; a plurality of comparators configured to operate in parallel with each other, each comparator associated with a respective output port located on one of the copies of the TLB, wherein each of the comparators is configured to identify mappings for invalidation; and logic for invalidating each identified mapping, the invalidating comprising unsetting a valid bit for the mapping between at least one logical address and at least one absolute address as invalid.