Patent ID: 9129669
Filing Date: 2015-09-08
Classification: G11C

Abstract:
1. A semiconductor system comprising: a command generator suitable for generating a command signal having a first logic level combination in a mode register write operation and suitable for generating the command signal having a second logic level combination in a read operation; a first register suitable for generating a input calibration signal having a predetermined logic level in the mode register write operation; a monitoring signal generator suitable for generating a monitoring signal enabled after a predetermined time from a start of the read operation; an input strobe signal generator suitable for comparing times when the monitoring signal transitions logic levels with times an internal calibration signal transitions logic levels, where the internal calibration signal is generated from a output calibration signal to generate an input strobe signal; a data input unit suitable for outputting the output calibration signal as the internal calibration signal and suitable for receiving the input strobe signal to generate an internal data according to a logic level of an output data; and a second semiconductor device suitable for storing the input calibration signal therein during the mode register write operation and suitable for outputting the output calibration signal and the output data during the read operation.