Patent ID: 9148134
Filing Date: 2015-09-29
Classification: G09G,H03K

Abstract:
1. A data driver comprising: a delay unit that sequentially delays a control signal and outputs a plurality of delay control signals; and a plurality of output circuits that start outputting in response to a corresponding delay control signal of the delay control signals, wherein the delay unit generates the delay control signals to be output to the output circuits, respectively, so that a first time difference between a first output start time of a first output circuit coupled to a line with a relatively large load capacitance of the output circuits and a second output start time of a second circuit that is immediately following or immediately previous to the first output circuit is larger than a second time difference between a third output start time of a third output circuit coupled to a line with a relatively small load capacitance of the output circuits and a fourth output start time of a fourth circuit that is immediately following or immediately previous to the third output circuit.