Patent ID: 8964059
Filing Date: 2015-02-24
Classification: G11C,H04N

Abstract:
1. A scanning circuit comprising: a predetermined number of first signal lines; second signal lines in the predetermined number; third signal lines in the predetermined number; a drive unit configured to drive the predetermined number of first signal lines; first buffers in the predetermined number, configured to drive the predetermined number of second signal lines in accordance with signals of the predetermined number of first signal lines; second buffers in the predetermined number, configured to drive the predetermined number of third signal lines in accordance with the signals of the predetermined number of first signal lines; and a shift register having a first part to be driven by signals of the predetermined number of second signal lines and a second part to be driven by signals of the predetermined number of third signal lines, wherein the predetermined number of first signal lines include at least two signal lines arranged in parallel to each other and configured to transmit in-phase signals, the predetermined number of second signal lines include at least two signal lines arranged in parallel to each other and configured to transmit the in-phase signals, and the predetermined number of third signal lines include at least two signal lines arranged in parallel to each other and configured to transmit the in-phase signals.