Patent ID: 6320771
Filing Date: 2001-11-20
Classification: H02J

Abstract:
A circuit for maintaining a balanced output current level among each of a plurality of power supply modules that are connected in parallel to form a parallel power supply that supplies a single load, said circuit comprising:a master reference voltage circuit that provides a master reference voltage level to said plurality of parallel power supply modules at a common load adjustment reference node;a load adjustment amplifier within each of said plurality of parallel power supply modules, wherein each of said load adjustment amplifiers compares an output voltage from its corresponding power supply module with said master reference voltage level and adjusts an output current from its corresponding power supply module in response thereto; andan internal reference circuit within each of said plurality of power supply modules, said internal reference circuit comprising:a first voltage source; andan amplifier that compares said master reference voltage level at said common load adjustment reference node with a voltage level from said first voltage source to generate an internal reference voltage level applicable to said common voltage adjustment node, wherein said internal reference voltage level is maintained lower than said master reference voltage level.