Patent ID: 6949782
Filing Date: 2005-09-27
Classification: G11C,H01L

Abstract:
1. A semiconductor memory element comprised of: a plurality of word lines; a plurality of data lines; and memory cells at the intersections of the word lines and data lines, each memory cell being comprised of a storage transistor with a gate terminal electrically connected to a storage node and one of a source or drain region connected to a predetermined potential, a read transistor with a gate terminal electrically connected to a read word line and a source or drain region connected to the other one of said a source or drain region of the storage transistor and the other one of the source or drain region of the read transistor connected to one of the data lines, and a semiconductor write device with a gate terminal electrically connected to a write word line and one of a source or drain region of the write device connected to a second one of said data lines and the other one of the source or drain region of the write device connected to the storage node, wherein said semiconductor write device source region and drain region are fabricated from metal or a semiconductor material connected by a channel which is formed by a semiconductor material with a thickness of no more than 5 nanometers on top of an insulating film, wherein said one side surface of said channel is substantially located on a same plane as said source region and drain region, and another side surface of said channel is located in a different plane from said source region and drain region.