Patent ID: 7412682
Filing Date: 2008-08-12
Classification: G06F

Abstract:
1. A method of defining global routes in an integrated circuit (“IC”) layout comprising a plurality of layers, the method comprising: a) defining a routing graph that comprises (i) a plurality of edges along a first local preferred direction defined for a first region of a particular layer of the IC layout, and (ii) a plurality of edges along a second local preferred direction defined for a second region of the particular layer, wherein the first and second local preferred directions are different; b) defining the capacities of a plurality of edges based on the different local preferred wiring directions of the two regions; and c) defining a global route by performing at least one path search that uses the defined capacities of the edges to determine whether a particular edge from the plurality of edges comprises sufficient available capacity for a path expansion to use the particular edge, wherein a capacity defined for an edge is based on a maximum number of global routes allowed to use the edge.