Patent ID: 6350635
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A method of forming an integrated circuit, the method comprising:forming a first layer on a substrate, the first layer having a first conductivity type; forming a second layer on the first layer, the second layer having a second conductivity type; forming a third layer on the second layer, the third layer having the first conductivity type; forming a first plurality of substantially parallel trenches extending through the third layer, the second layer, the first layer, and extending at least partially into the substrate, the first plurality of trenches defining a plurality of semiconductor bars; removing an amount of the substrate sufficient to at least partially undercut the plurality of semiconductor bars; forming a first insulating layer between the substrate and the plurality of semiconductor bars, the insulating layer underlying the plurality of semiconductor bars; forming a second plurality of substantially parallel row trenches substantially orthogonally to the first plurality of trenches, the second plurality of substantially parallel row trenches extending through the third layer, the second layer, and extending partially through the first layer such that the first layer serves as a plurality of bit lines; forming a second insulating layer substantially covering a surface of the second plurality of trenches; forming conductors in the second plurality of trenches, each conductor comprising a conductive layer and being disposed in one of the second plurality of trenches; and coupling the bit lines and the conductors to addressing circuitry.