Patent ID: 9057765
Filing Date: 2015-06-16
Classification: G01R

Abstract:
1. A processor-implemented method for determining a scan compression ratio of an integrated circuit based on a fault density of the integrated circuit, the method comprising: identifying, by a processor, a total number of scan-in pins of the integrated circuit; identifying a plurality of partitions of the integrated circuit, wherein the identified plurality of partitions comprises a total number of identified logical and physical partitions of the integrated circuit; determining, by an Automatic Test Pattern Generation Tool (ATPG), a total number of faults for each of the identified plurality of partitions of the integrated circuit; identifying a total number of scan chains and a total number of flip-flops for each of the identified plurality of partitions; calculating the fault density value for each of the identified plurality of partitions of the integrated circuit, wherein the fault density value is computed based on a ratio of the determined total number of faults for each of the identified plurality of partitions to the total number of identified flip-flops for each of the identified plurality of partitions; determining a compression ratio for each of the identified plurality of partitions, wherein the determined compression ratio comprises a ratio between the total number of identified scan-in pins and the total number of identified scan chains; and applying the determined compression ratio for each of the identified plurality of partitions based on the calculated fault density value to each of the identified plurality of partitions of the integrated circuit.