Patent ID: 6451679
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A method of forming salicide electrical lines and contacts in the fabrication of an integrated circuit comprising:providing a semiconductor silicon substrate having polysilicon gates and source/drains therein; exposing said polysilicon gates and said source/drains whereby the silicon is exposed; depositing a thin layer of metal on exposed said polysilicon gates and said source/drains; implanting by ion implantation Si+ at low energy through said metal layer, peaking the maximum Si+ dose to just below the metal/Si interface; depositing another thin layer of said metal on said polysilicon gates and said source/drains; annealing said substrate by rapid thermal annealing in an inert atmosphere forming a metal silicide on said polysilicon gates and said source/drains; etching by selective etching the excess and unreacted said metal deposited above; annealing said substrate again by rapid thermal annealing whereby said metal is further salicidated converting completely to a metal silicide on said polysilicon gates and said source/drains, forming self-aligned low resistance lines and contacts.