Patent ID: 8516223
Filing Date: 2013-08-20
Classification: G06F

Abstract:
1. A priority circuit that is connected to a reservation station that includes a plurality of entries therein and supplies a decoded instruction decoded by an instruction decoder to be operated and executable information outputted from the instruction decoder indicating that a corresponding decoded instruction can be executed only by a specific arithmetic unit of a plurality of arithmetic units or the corresponding decoded instruction can be executed not only by the specific arithmetic unit but by an arithmetic unit different from the specific arithmetic unit of the plurality of arithmetic units, the decoded instruction and corresponding executable information are held in each of the plurality of entries, and the plurality of arithmetic units each have an instruction queue storing the decoded instruction supplied from the reservation station and each execute a different operation based on the decoded instruction stored in the instruction queue, the priority circuit comprising: a dispatching unit that dispatches the decoded instruction to the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed only by the specific arithmetic unit and dispatches the decoded instruction to an arithmetic unit different from the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed not only by the specific arithmetic unit but by the arithmetic unit different from the specific arithmetic unit and of which an instruction queue is vacant.