Patent ID: 7542365
Filing Date: 2009-06-02
Classification: G11C

Abstract:
1. An apparatus comprising: an input terminal for receiving data bits from a serial memory; an output terminal for providing command and address bits to the serial memory; a pull circuit for causing the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory; a data out control circuit coupled to the output terminal, for causing the read command to be provided and for causing a first predetermined number of address bits to be provided to the output terminal; and a transition detector, coupled to the input terminal, for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits; wherein if the transition detector detects a transition of the input terminal, indicating that the first predetermined number of address bits is a correct number of address bits to access the memory, then receiving the data bits at the input terminal; and wherein if the transition detector does not detect a transition of the input terminal, indicating that the first predetermined number of address bits is insufficient for accessing the memory, then providing a second predetermined number of address bits to the output terminal.