Patent ID: 7216202
Filing Date: 2007-05-08
Classification: G06F

Abstract:
1. An apparatus for supporting one or more servers on a single semiconductor chip, comprising: a plurality of first-level translation lookaside buffers on the single semiconductor chip, wherein each first-level translation lookaside buffer is associated with a processor core of a plurality of processor cores on the single semiconductor chip; and a second-level translation lookaside buffer that is coupled to the plurality of first-level translation lookaside buffers, wherein the second-level translation lookaside buffer stores a subset of the entries in the plurality of first-level translation lookaside buffers; wherein an access to a page table entry in main memory by a processor core associated with a first-level translation lookaside buffer can be stored in the second-level translation lookaside buffer before being forwarded to the first-level translation buffer associated with the processor that requested the page table entry; whereby storing the page table entry in the second-level translation lookaside buffer eliminates a need to refer to main memory to access the same page table entry if another processor requests the same page table entry.