Patent ID: 6066548
Filing Date: 2000-05-23
Classification: H01L

Abstract:
A double metal process for forming conductive lines fabricated in a semiconductor device, said process comprising the steps of:forming a first metal layer on a material having a substantially planar surface;forming a hard mask layer over said first metal layer;patterning and etching said hard mask layer and said first metal layer to form a patterned hard mask overlying a first plurality of patterned metal lines, said etching resulting in substantially vertical sidewalls along edges of said hard mask layer and said first plurality of patterned metal lines;forming insulative spacers about said substantially vertical sidewalls;forming trenches into said material along side said insulative spacers;forming a second metal layer that covers said patterned hard mask, said insulative spacers and at least partially fills said trenches;removing a portion of said second metal layer covering said hard mask, thereby forming a second plurality of patterned metal lines wherein each metal line of said second plurality of patterned metal lines is completely recessed within a corresponding trench;wherein said step of forming a first metal layer and said step of forming a second metal layer are separate metal deposition steps and wherein the upper surfaces of said first plurality of patterned metal lines is above the upper surfaces of said second plurality of patterned metal lines.