Patent ID: 6833332
Filing Date: 2004-12-21
Classification: H01L

Abstract:
A method of forming at least one relaxed SiGe buffer layer on a silicon-on-insulator substrate comprising the steps of:(a) forming a layer of self-assembled Ge or SiGe islands atop a Ge wetting layer which is formed atop a Si layer of a silicon-on-insulator substrate; (b) forming a planarizing Si or Si-rich SiGe cap layer which covers the layers of Ge or SiGe islands; and (c) annealing the silicon-on-insulator substrate containing said planarizing Si or Si-rich SiGe cap layer covering said layer of Ge or SiGe islands so as to intermix said planarizing Si or Si-rich cap layer, said layer of Ge or SiGe islands and said top Si layer of the silicon-on-insulator substrate to relieve strain therein, thereby obtaining a homogeneous strain-relaxed SiGe layer having a low density of threading dislocations.