Patent ID: 7043655
Filing Date: 2006-05-09
Classification: G06F

Abstract:
1. A computer system comprising: a side plane board; a first clock board coupled to the side plane board, the first clock board including a first crystal, a first buffer, and a first clock synthesizer circuit, wherein the first clock synthesizer circuit is coupled to receive a first crystal clock signal from the first crystal and provide a first system clock signal to the first buffer; and a second clock board coupled to the side plane board, the second clock board including a second crystal, a second buffer, and a second clock synthesizer circuit, wherein the second clock synthesizer circuit is coupled to receive a second crystal clock signal from the second crystal and provide a second system clock signal to the second buffer; wherein each of the first and second clock synthesizer circuits are implemented on a clock synthesizer chip, the clock synthesizer chip including: wherein the first clock board is configured to operate as a master and the second clock board is configured to operate as a slave, wherein the first clock synthesizer is configured to determine a phase relationship between the first crystal clock signal and a first feedback clock signal, and wherein the first clock synthesizer is configured to inhibit the first crystal clock signal if the phase relationship exceeds a predetermined limit; and wherein the second clock board, responsive to detecting the inhibiting of the first crystal clock signal, is configured to act as the master by enabling the second crystal clock signal, wherein the master is configured to provide a master clock signal to the side plane board, wherein the master clock signal is the first system clock signal or the second system clock signal depending upon which of the first or second clock boards is the master.