Patent ID: 7564268
Filing Date: 2009-07-21
Classification: H03K

Abstract:
1. A low power logic output buffer consisting of: a first logic gate having an input and an output, the input of the first logic gate receiving a first logic signal; a second logic gate having an input and an output, the input of the second logic gate receiving a second logic signal; a first buffer output that outputs a first output signal; a second buffer output that outputs a second output signal; a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between a rail supply voltage (Vdd a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the rail supply voltage (Vdd a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the rail supply voltage (Vdd a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the rail supply voltage (Vdd a first bias switching NMOS having a gate, a source and a drain, the source and the drain of the first bias switching NMOS being electrically coupled between the source of the third NMOS and ground, the gate of the first bias switching NMOS being electrically coupled to the output of the first logic gate; a second bias switching NMOS having a gate, a source and a drain, the source and the drain of the second bias switching NMOS being electrically coupled between the source of the fourth NMOS and ground, the gate of the second bias switching NMOS being electrically coupled to the output of the second logic gate; a first bias NMOS having a gate, a source and a drain, the source and the drain of the first bias NMOS being coupled between the first buffer output and the drain of the first bias switching NMOS, the gate of the first bias NMOS being driven by a bias voltage; and a second bias NMOS having a gate, a source and a drain, the source and the drain of the second bias NMOS being coupled between the second buffer output and the drain of the second bias switching NMOS, the gate of the second bias NMOS being driven by the bias voltage.