Patent ID: 6604166
Filing Date: 2003-08-05
Classification: G06F

Abstract:
An apparatus for providing parallel access to data elements of a data vector of an n-dimensional rectangular array, comprising:an address generation logic module, for receiving an index of a first data element of a data vector to be stored into memory and for receiving a dimension of access, generating addresses to which to store the data elements of the data vector, the address generation logic requiring that each data element of a data vector is stored in a different memory bank to allow parallel access along any dimension of the n-dimensional rectangular array; a permuter, coupled to the address generation logic module, for receiving the addresses, receiving the dimension of access, and receiving the index information of the first data element of the data vector, for carrying out a permutation operation on the addresses by generating a bank number of a memory bank to which to issue the addresses, the permuter requiring that each data element of a data vector is stored in a different memory bank to allow parallel access along any dimension of the n-dimensional rectangular array, and for storing data elements at the generated address and bank number corresponding to the each data element of the data vector; and at least s memory banks, coupled to the permuter to allow parallel access by the permuter to the s memory banks, to receive addresses to store each data element of the data vector, where s is equal to the number of data elements in a data vector.