Patent ID: 7714828
Filing Date: 2010-05-11
Classification: G09G

Abstract:
1. A display comprising a shift register circuit formed by connecting a plurality of first circuit portions each having: a first conductive type first transistor connected to a first potential; a first conductive type second transistor connected to a constant second potential; a first conductive type third transistor with the gate thereof connected to the gate of said second transistor, connected between the gate of said first transistor and said second potential; a first conductive type fourth transistor connected to the gate of said first transistor and turned on in response to a first clock signal; a first conductive type fifth transistor, with the drain thereof connected to the source of said fourth transistor, connected between said fourth transistor and said first potential and turned off in response to a second clock signal when said first clock signal is for turning on said fourth transistor, wherein said second clock signal is an inverted clock signal of said first clock signal; and a first capacitor, in which said first potential is accumulated when said fifth transistor is in on state, is connected between the source of said first transistor and the junction point of the source of said fourth transistor and the drain of said fifth transistor, wherein said second clock signal of a potential for turning off said fifth transistor is input to the gate of said fifth transistor, thereby said fifth transistor is turned off when said fourth transistor is turned on by said first clock signal of a potential for turning on said fourth transistor input to the gate of said fourth transistor, wherein said first clock signal of a potential for turning off said fourth transistor is input to the gate of said fourth transistor, thereby the said fourth transistor is turned off when said fifth transistor is turned on by said second clock signal of a potential for turning on said fifth transistor input to the gate of said fifth transistor, and wherein an output signal of a start signal or a preceding stage of a shift register circuit is input to the gates of said second transistor and said third transistor.