Patent ID: 6834014
Filing Date: 2004-12-21
Classification: G11C

Abstract:
An integrated circuit memory device for use in a memory system that receives predetermined command/address signals from a memory controller and that reads and writes data in response to the command/address signals, the memory device comprising:at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus; at least one termination resistor; an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller; and at least one switch coupled in series with the at least one termination resistor between the at least one input/output terminal and a predetermined voltage wherein the at least one switch is switched on/off in response to the control signal such that the at least one input/output terminal is connected/disconnected to/from the predetermined voltage responsive to the control signal and such that the at least one termination resistor is coupled in series between the predetermined voltage and the at least one input/output terminal when the at least one switch is switched on and such that the at least one input/output terminal is decoupled from the predetermined voltage when the at least one switch is switched off.