Patent ID: 6769055
Filing Date: 2004-07-27
Classification: H04L

Abstract:
A multiport data communication system storing received data packets in a memory having a plurality of storage areas, the data communication system comprising:a plurality of receive ports for receiving the data packets; a queue of start addresses of storage areas in the memory available for storing the received data packets; an address generator for generating memory addresses for storing the received data packets in the plurality of storage areas of the memory, the address generator including: a first register receiving a start address from the queue and providing a first part of the memory address, and a second register counting write cycles to the memory and providing the count result as a second part of the memory address; a plurality of queuing devices corresponding to the plurality of receive ports each queuing groups of data corresponding to a received data packet, each queuing device being separate from the memory; and a logic unit controlling transfer of the groups of data from the corresponding queuing device to the memory, wherein the address generator is part of the logic unit, each storage area in the memory stores a predetermined number of groups of data, and when a number of groups of data representing a received data packet is greater than said predetermined number of groups of data, said number of groups of data are stored in a plurality of storage areas by using the second part of the memory address to write the address of a subsequent storage area storing subsequent groups of data of said received data packet in the storage area storing the immediately preceding groups of data.