Patent ID: 7230470
Filing Date: 2007-06-12
Classification: H03K

Abstract:
1. A power switch having source, drain and gate terminals, the power switch comprising: a first field-effect transistor (FET) having a first drain coupled to the drain terminal, a first source coupled to the source terminal, and a first gate; a second FET having a second drain coupled to the drain terminal, a second source coupled to the source terminal, and a second gate, the second FET having a gate length (L a control circuit coupled to the gate terminal, the first gate, and the second gate, and wherein the control circuit is configured to control the first gate and second gate such that during a turn-on transition, a voltage at the drain terminal falls from a high voltage to a clamping voltage, is clamped at the clamping voltage for a duration, and falls from the clamping voltage to a low voltage.