Patent ID: 6569737
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method of fabricating a transistor in a semiconductor device, comprising:forming a first trench and a second trench in a first conductivity type semiconductor substrate in which an active area and a device isolation area are defined, wherein a gate forming area is defined in the active area, and wherein the first trench is formed to a first depth to define the device isolation area and the second trench is formed having a second depth, less than the first depth to define the gate forming area, the first and second trenches being formed simultaneously by removing predetermined portions of the substrate; forming a device isolation layer by filling up the first trench with an insulator; forming a gate insulating layer on an inner surface of the second trench; filling the second trench having the gate insulating layer with a conductive substance; and forming a pair of impurity diffusion regions of a second conductivity type respectively, in the active area of the substrate between the first and second trenches, without having formed an epitaxial layer.