Patent ID: 7746972
Filing Date: 2010-06-29
Classification: H03L

Abstract:
1. A circuit for providing a clock output synchronized to a timing reference signal supplied to a timing reference input, said circuit comprising: a numerically-controlled oscillator for providing said clock output and having an input for receiving a rational numeric representation of a ratio between a frequency of said clock output and a frequency of a stable clock for controlling said frequency of said clock output; a digital phase-frequency detector for generating a representation of an on-going phase-frequency difference between said timing reference signal and a signal derived from said clock output; a digital loop filter for filtering said representation of said on-going phase-frequency difference to provide said rational numeric representation to said numerically-controlled oscillator; a timing reference characteristic detection circuit for detecting a characteristic of the timing reference signal independent of the on-going phase-frequency difference; and a ratio adjustment circuit for adjusting said rational numeric representation resulting from the filtered representation of the on-going phase-frequency difference in conformity with said detected characteristic.