Patent ID: 6670250
Filing Date: 2003-12-30
Classification: H01L

Abstract:
A method for forming a MOS transistor comprising:(a) forming a gate oxide layer pattern and a gate conductive layer pattern on a semiconductor substrate; (b) forming a mask layer pattern on the semiconductor substrate and the gate conductive layer pattern so that the gate conductive layer pattern is completely covered with the mask layer pattern; (c) making a first region of the semiconductor substrate amorphous using the mask layer pattern such that a second region of the semiconductor substrate is not made amorphous; (d) removing the mask layer pattern and forming a gate poly oxide layer over the entire surface of the semiconductor substrate, the gate poly oxide layer having a first thickness at the second region of the semiconductor substrate and a second thickness at the first region of the semiconductor substrate, the first and second thicknesses being different; (e) depositing a gate spacer layer on the gate poly oxide layer and forming gate spacers by anisotropically etching the gate spacer layer and the gate poly oxide layer; and (f) forming a source/drain region on the semiconductor substrate.