Patent ID: 8835997
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A static random access memory (SRAM) array, comprising: at least one p-type field effect transistor, including: a first gate stack having a first gate dielectric layer having a width, and isolating spacers forming a first gate having a gate length, Lgate and an effective gate length, Leff; and a first source region and first drain region adjacent the first gate stack, wherein the first source and first drain regions are formed from a low extension dose implant performed at a dose between 1×10 at least one n-type field effect transistor, including: a second gate stack having a second gate dielectric layer having the width, and isolating spacers forming a second gate having the gate length, L gate and an second effective gate length; and a second source region and second drain region adjacent the second gate stack, wherein the second source and second drain regions are formed from a high extension dose implant performed at a dose between 1×10 wherein the p-type field effect transistor has a higher resistance than the n-type field effect transistor.