Patent ID: 9140949
Filing Date: 2015-09-22
Classification: G02F

Abstract:
1. An array substrate comprising: gate lines on the array substrate, data lines on the array substrate, pixel TFTs and pixel electrodes on the array substrate, wherein each row of pixel TFTs have gates electrically connected with a gate line, and each column of pixel TFTs have first electrodes electrically connected with a data line, and each pixel TFT has a second electrode connected with a pixel electrode; and the array substrate further comprises compensation capacitors on the array substrate; in every two adjacent rows of gate lines in at least a part of the rows on the array substrate, pixel TFTs connected with one gate line are a first type of TFTs, and pixel TFTs connected with an other gate line are a second type of TFTs; and in the at least a part of the rows, each of the pixel electrodes is arranged correspondingly with one of the compensation capacitors, and each of the compensation capacitors has one end electrically connected to the pixel electrode corresponding thereto and another end electrically connected to a gate line in a next row.