Patent ID: 6350640
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A method of manufacturing a semiconductor architecture comprising the steps of:(a) providing a semiconductor substrate of a first conductivity type having a first surface; (b) forming, to a first depth from said first surface in respective first and second spaced-apart portions of said semiconductor substrate, first and second well regions of second conductivity type; (c) forming first source and drain regions of said first conductivity type of a first channel conductivity type MOS structure in spaced apart surface portions of said first doping and a second depth from said first surface, less than said first depth; and (d) forming an emitter region of said first conductivity type of a bipolar transistor structure in said second well region, said second well region forming the base region of said bipolar transistor structure and said substrate forming the collector region of said bipolar transistor structure, such that said emitter region has a second doping greater than that of said first source and drain regions, and a third depth from said first surface deeper than said second depth of said first source and drain regions said first MOS structure, wherein step (c) comprises selectively masking said first surface of said substrate so as to provide first and second impurity introduction apertures overlying said first well region, and introducing impurities of said first conductivity type at a first dosage energy to said second depth in said first well region, and wherein step (d) comprises selectively masking said first surface of said substrate so as to provide a third impurity introduction aperture overlying said second well region, introducing impurities of said first conductivity type at a third dosage energy to a fourth depth less than said third depth in said second well region.