Patent ID: 8190856
Filing Date: 2012-05-29
Classification: G06F

Abstract:
1. A processor comprising a dual mode single instruction, multiple data stream/multiple instruction stream, multiple data stream (SIMD/MIMD) architecture, the processor comprising: a global control unit; first processing elements configured to operate in a SIMD mode and to execute a same program of the global control unit; second processing elements configured to operate in a MIMD mode and configured to execute their own program independently from other processing elements programs; a pipelined network connecting said first processing elements and said second processing elements sequentially; and an arbitration unit including an access controller comprising access control lines, each access control line being connected to each processing element of said first and second processing elements to control data access timing between each processing element and said network, wherein said data access for said first processing elements comprises a concurrent access so that each of said first processing elements accesses said network at a same timing slot, wherein said data access for said second processing elements is comprises a stand-alone access so that each of said second processing elements accesses said network independently, and wherein said arbitration unit is configured to arbitrate a data transfer request for the first processing elements from the global control unit and data transfer requests for the second processing elements accesses from the second processing elements in such a manner that said access controller assigns a higher priority to one stand-alone access than to a concurrent access or to other stand-alone accesses when assigning the data access timing to each processing element via a respective control line, or said access controller assigns a higher priority to a concurrent access than a stand-alone access when assigning the data access timing to each processing element via the respective access control line.