Patent ID: 6177326
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for fabricating a bottom electrode, comprising the steps of:providing a substrate having a source/drain region;forming a dielectric layer on the substrate;forming via hole in the dielectric layer to expose the source/drain region;forming a doped polysilicon layer on the dielectric layer to fill the via hole;forming a patterned photoresist layer to covered a portion of the doped polysilicon layer;removing the doped polysilicon layer using the patterned photoresist layer as a mask, wherein the patterned photoresist layer is so thin that an edge of the portion of the doped polysilicon layer covered by the patterned photoresist layer is removed to form an arced or polygonal shape of the polysilicon layer;transforming a surface region of the remaining doped polysilicon layer into an amorphous silicon layer; andforming a hemispherical-grain silicon layer on the amorphous silicon layer.