Patent ID: 7674672
Filing Date: 2010-03-09
Classification: H05K

Abstract:
1. A process for fabricating a substrate with an embedded passive component, comprising: providing a substrate comprising a top conductive layer, a bottom conductive layer, and at least an initial dielectric layer having a top surface and a bottom surface opposite to the top surface, the top conductive layer and the bottom conductive layer being respectively disposed on the top surface and the bottom surface; forming a plurality of plating through holes in the substrate; patterning the top conductive layer and the bottom conductive layer to respectively form a patterned top conductive layer comprising a plurality of first traces and a patterned bottom conductive layer comprising a plurality of second traces after the plating through holes are formed, wherein a portion of the first traces forms a plurality of first trenches, a portion of the second traces forms a plurality of second trenches, and the first traces and the second traces partially expose the top surface and the bottom surface respectively; filling a passive component material into the first trenches and the second trenches, wherein the first traces, the second traces, and the passive component material are adapted for forming a passive component; forming a sealing layer on a portion of the patterned bottom conductive layer to seal the passive component material inside the patterned bottom conductive layer after the passive component material is filled into the first trenches and the second trenches; after forming the sealing layer, forming a first dielectric layer to cover the top surface of the initial dielectric layer and the patterned top conductive layer; forming a first conductive layer on the first dielectric layer; forming a plurality of first blind holes extending from the first conductive layer to the patterned top conductive layer; forming a plurality of first conductive pillars in the first blind holes; and patterning the first conductive layer to form a first patterned conductive layer partially exposing the first dielectric layer.