Patent ID: 8278161
Filing Date: 2012-10-02
Classification: G02F,H01L

Abstract:
1. A method of fabricating a thin film transistor array substrate with a thinned protective film over a storage capacitor, the method comprising: forming a first gate line and one of a common line and a second gate line separated from the first gate line on a substrate; forming a source/drain pattern including a data line crossing the first gate line, source and drain electrodes of a thin film transistor provided at the intersection between the first gate line and the data line, and forming a semiconductor pattern including an active layer and an ohmic contact layer of the thin film transistor; forming a protective film covering the thin film transistor; forming a photo-resistive film on the protective film; aligning a diffractive mask including a semi-transmitting part corresponding to a storage capacitor area and a transmitting part corresponding to a contact hole area; forming a photo-resist pattern using the diffractive mask, wherein the photo-resist pattern on the storage capacitor area has a lower height than the photo-resist pattern of an area excluding the storage capacitor area, the photo resist pattern corresponding to the contact hole area being removed to expose the protective film; patterning the protective film using the photo-resist pattern as a mask to remove the protective film corresponding to the contact hole area to define a contact hole to expose the drain electrode, the protective film at the storage capacitor area remaining unaffected when the contact hole is formed; ashing the photo-resist pattern at the storage capacitor area to expose the protective film, the ashed photo-resist pattern remaining at an area excluding the contact hole and the storage capacitor area; partially removing the protective film at the storage capacitor area using the ashed photo-resist pattern as a mask to reduce a height of the protective film at the storage capacitor area, the height of the protective film being based on an etching time; removing the ashed photo-resist pattern; and forming a pixel electrode connected, via the contact hole, to the drain electrode of the thin film transistor, a storage capacitor being formed that includes the pixel electrode and the one of the common line and the second gate line; wherein forming the source/drain pattern and forming the semiconductor pattern comprises: forming an amorphous silicon layer, an n+ amorphous silicon layer and a source/drain metal layer on the substrate; forming a photo-resist pattern having a lower height at a channel portion of the thin film transistor than at regions of the source/drain pattern; etching the source/drain metal layer using the photo-resist pattern to provide the data line, the source electrode, and the drain electrode; etching the amorphous silicon layer and the n+ amorphous silicon layer using the photo-resist pattern to provide the active layer and the ohmic contact layer; ashing the photo-resist pattern; etching the source/drain pattern and the ohmic contact layer at the channel portion using the ashed photo-resist pattern.