Patent ID: 6075391
Filing Date: 2000-06-13
Classification: H03K

Abstract:
A circuit for charging a capacitance and comprising:an LDMOS integrated transistor functioning as a source follower and controlled to emulate a high voltage charging diode for the capacitance;an inverter;a logic control circuit for driving the inverter responsive to a low gate drive signal and a second logic signal, the second logic signal being active during a phase wherein a supply voltage is lower than a minimum switch-on voltage of the circuit;a first zener diode coupled to a gate of the LDMOS transistor;a bootstrap capacitor charged by the first zener diode at the supply voltage by the inverter;a second zener diode connecting a source of the LDMOS integrated transistor to the supply voltage;a plurality (n) of diodes connected together in series between the supply voltage and a body of the LDMOS integrated transistor defining n-diode junctions of a protection chain; andrespective zener voltages of the first and second zener diodes satisfying the following conditions:VTH>VZ1-VZ2 for Vs>VZ1,andVTH>Vs+Vbe-VZ2 for Vs<VZ1wherein VTH is the threshold voltage of the LDMOS integrated transistor, Vs is the supply voltage, VZ1 is the zener voltage of the first zener diode, VZ2 is the zener voltage of the second zener diode, Vbe is the threshold voltage of the n-diode junctions of the protection chain, and with a difference between a source voltage and a body voltage of the LDMOS integrated transistor equal to VZ2+nVbe.