Patent ID: 6256717
Filing Date: 2001-07-03
Classification: G11B

Abstract:
A data access controller comprising:means of memorizing data;means of generating a read address and a write address for making access to said memory means in correspondence to multiple kinds of processes;means of providing the addresses on a time-slice basis for said memory means;means of generating a first clock signal; andmeans of generating a second clock signal which is different in phase from the first clock signal,wherein said address generation means and address providing means operate in accordance with the first and second clock signals, and said memory means is accessed for data input/output by being timed to the rising of the first and second clock signals, andwherein said read address and said write address correspond to overlapping locations of said memory means, andwherein data corresponding to said read address is read from said memory means at a rising of said first clock signal, and data corresponding to said write address is written at a rising of said second clock signal, said rising of said second clock signal lagging said rising of said first clock signal by a predetermined time corresponding to a phase difference between said first and second clock signals, such that said read address data is read out before said write address data is written by said predetermined time.