Patent ID: 7590826
Filing Date: 2009-09-15
Classification: G06F

Abstract:
1. Apparatus for processing data, said apparatus comprising: a physical set of registers; a register renaming circuit for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers to generate physical register specifiers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set; at least one execution circuit, responsive to said instructions and associated physical register specifiers, configured to speculatively execute at least some of said instructions using said physical set of registers based upon respective predicted outcomes of at least one unresolved instruction, said instructions being speculatively executed including load instructions respectively for loading a data value from a memory to a physical register; a register renaming recovery circuit, responsive to detection of a mispredicted speculatively executed instruction as having a mispredicted outcome, configured to return to a mapping from said set of architectural registers to said set of physical registers that reverses changes made in said mapping that are dependent upon said mispredicted speculatively executed instruction such that said physical registers to which said set of architectural registers are mapped correspond to and contain values of said physical registers to which said architectural registers were mapped prior to execution of said mispredicted speculative executed instruction; and an error detecting circuit responsive to load instructions to generate an error signal indicative whether or not an error is detected for said load instructions; wherein a data value loaded from said memory and stored within a physical register in response to a load instruction is made available for use for further processing before said error detecting circuit has been able to generate said error signal; said load instruction is handled by said register renaming recovery circuit as a speculative instruction until at least said error detecting circuit has been able to generate said error signal; and if said error signal indicates an error, then said register renaming recovery circuit reverses any changes in said mapping made that are dependent upon said load instruction such that said physical registers to which said set of architectural registers are mapped correspond to and contain values of said physical registers to which said architectural registers were mapped prior to execution of said load instruction.