Patent ID: 8095825
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. An error correction method, comprising: detecting an error in a CPU bus write instruction in a CPU with a pipeline structure by a CPU bus error detector; restoring, via a rollback control unit, a content of a register file from a delayed register file which holds the content of the register file at a time when an Instruction N was executed correctly before the error; and re-executing, with rollback control, via a rollback control unit, an Instruction N+1 which is the next instruction after the Instruction N, wherein the CPU and the rollback control unit are connected to one another via a bus, wherein the CPU bus error detector decodes the CPU bus write instruction, and obtains an index of a register Ra which holds a write address of the CPU bus write instruction, and an index of a register Rd which holds write data of the CPU bus write instruction and compares the write address and write data outputted to the CPU bus with the value of Ra and Rd in the delayed register file, and wherein instructions for setting the write address and write data to register Ra and register Rd are allocated so that the write address and write data are set to registers Ra and Rd in the delayed register file before the CPU bus write instruction is executed.