Patent ID: 7668039
Filing Date: 2010-02-23
Classification: G11C

Abstract:
1. An address counter comprising: a plurality of FIFO units each of which stores a corresponding bit of an address signal, each FIFO unit including a plurality of parallel connected latch circuits each having an input gate and an output gate; a first command counter that brings any one of the input gates included in each FIFO unit into ON state in response to a first internal command during a first operation mode, and that brings two or more input gates included in each FIFO unit into ON state in response to the first internal command during a second operation mode; and a second command counter that brings any one of the output gates included in each FIFO unit into ON state in response to one of second and third internal commands during the first operation mode, and that brings any one of the output gates included in each FIFO unit into ON state in response to the second internal command and brings any one of the output gates included in each FIFO unit into ON state in response to the third internal command during the second operation mode.