Patent ID: 6779124
Filing Date: 2004-08-17
Classification: G06F,G11C

Abstract:
A synchronous circuit, comprising:a clock input for receiving a first clock signal; a clock signal generator for generating a second clock signal, said clock signal generator being phase-locked with respect to the first clock signal, having an input connected to said clock input and having a clock output for outputting the second clock signal; a data transmission unit for one of outputting data from an integrated circuit and reading data into the integrated circuit substantially in synchronism with the first clock signal; said data transmission unit having a control input connected to said clock output of said clock signal generator; said clock signal generator having at least two control loops connected in series for controlling a phase angle of the second clock signal, said at least two control loops including a first control loop for generating from the first clock signal at least two intermediate clock signals each having a particular phase angle with respect to the first clock signal, and a second control loop for generating the second clock signal from the intermediate clock signals; and a deactivation unit connected to said first control loop for deactivating a control of said first control loop during a transmission of data by said data transmission unit, such that a control of the phase angles of the intermediate clock signals is interrupted and corresponding control signals for setting the phase angles are kept constant.