Patent ID: 7856246
Filing Date: 2010-12-21
Classification: G06F,Y02D

Abstract:
1. A data processor, comprising: a processor engine comprised of a plurality of processor cells, each cell comprising a local instruction memory and an instruction sequencer and being configured for selective connection with at least one adjacent cell enabling communication between cells, said processor engine configured to be interposed between a radio frequency section and a baseband section to process data output from the baseband section prior to inputting the processed data to the radio frequency section, and to process signals output from the radio frequency section prior to inputting processed data to the baseband section, wherein a plurality of functions are mapped into a corresponding plurality of regions of cells, each region comprising at least one cell, and where the local instruction memory of each cell of a region is configured to store program instructions to implement all or a part of the associated function, and where a cell within a region of cells comprises balanced code enabling unique control in the region of cells that does not break synchronization between the cells belonging to the region.