Patent ID: 8027423
Filing Date: 2011-09-27
Classification: G11B,H04L

Abstract:
1. A synchronizing apparatus for controlling, by a Phase Locked Loop (PLL) circuit, a sampling clock to be used to sample input data and synchronizing a phase of said sampling clock with a target phase that is desirable for sampling said input data, said synchronizing apparatus comprising: phase error detection means for detecting a phase error from sampling data and said sampling clock, said sampling data being sampled from said input data at timing of said sampling clock; frequency error detection means for detecting a frequency error based on a differential coefficient obtained as a result of detecting said phase error; and frequency correction means for correcting a frequency of said sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of said PLL circuit, said frequency correction value being calculated based on said frequency error; wherein to bring said frequency error close to zero, said frequency correction means repeatedly performs a process of multiplying the detection result of said frequency error by a predetermined coefficient to obtain said frequency correction value and then correcting the frequency of said sampling clock by adding said frequency correction value to the integral term of the loop filter of said PLL circuit; and wherein while said frequency correction means repeatedly performs a process of correcting the frequency of said sampling clock, a statistical process is performed on the detection result of said phase error to obtain a phase error estimate value, and a phase correction value is calculated by multiplying said phase error estimate value by a second predetermined coefficient, and then said PLL circuit is restarted by applying said phase correction value as an initial phase value of a Voltage Controlled Oscillator (VCO) or Numerical Control Oscillator (NCO) of said PLL circuit.