Patent ID: 7929332
Filing Date: 2011-04-19
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of data hold memory cells having a function of holding data; an initialization memory cell having a function of initializing the plurality of data hold memory cells; a first data line; a second data line; and a word line, wherein each of the plurality of data hold memory cells and the initialization memory cell comprises: a first inverter circuit comprising a first transistor; a second inverter circuit comprising a second transistor; a third transistor; and a fourth transistor, wherein the word line is electrically connected to a gate electrode of the third transistor and a gate electrode of the fourth transistor, wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and the second data line, wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line, and wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell.