Patent ID: 6551870
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A method of fabricating a transistor having a lightly doped drain region, comprising the sequential steps of:(a) forming a gate having side edges in an active region of a substrate, said active region defined by field oxide regions; (b) forming an oxide layer over said gate; (c) forming a nitride layer over said oxide layer; (d) pattering said nitride layer to form nitride sidewall spacers about said side edges of said gate; (e) forming heavily doped source and drain regions in said substrate in a region adjacent to said nitride sidewall spacers; (f) removing said nitride sidewall spacers; (g) pattering said oxide layer to form oxide sidewall spacers; and (h) forming a lightly doped drain region in said substrate between one of said side edges of said gate and said heavily doped drain region.