Patent ID: 6223097
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method of manufacturing semiconductor integrated circuit devices, comprising the step of:fabricating a plurality of types of semiconductor integrated circuit devices each including a static random access memory as a test element;classifying the semiconductor integrated circuit devices into a plurality of groups, each of the groups including a plurality of types of the semiconductor integrated circuit devices, the types in each group having at least one common feature;subjecting a type of the semiconductor integrated circuit devices in each of the groups to an acceleration test, to estimate a failure ratio in the market of the type of the semiconductor integrated circuit devices in said each group, on the basis of the result of the acceleration test;estimating a failure ratio in the market of another type of the semiconductor integrated circuit devices in said each group, on the basis of the first-estimated failure ratio;optimizing a failure ratio in the market of the semiconductor integrated circuit devices of each of the types of said each group, on the basis of the second-estimated failure ratio;determining screening conditions for an initial-failure of the semiconductor integrated circuit devices of each of the types of said each group by optimizing a failure ratio in the market of the semiconductor integrated circuit devices of each of the types of said each group, on the basis of the second-estimated failure ratio; andscreening the semiconductor integrated circuit devices of each of the types of said each group, based on the determined screening conditions.