Patent ID: 8378951
Filing Date: 2013-02-19
Classification: G09G

Abstract:
1. A timing controller with power-saving function, comprising: an interlace scan controlling module, comprising: an odd/even determining circuit, for calculating a number of transmitted pixel data of a video signal, to determine if a first frame transmitted from the video signal is an odd frame or an even frame, and accordingly outputting an odd/even determining signal, the odd/even determining circuit comprising: a first counter, for counting the number of the transmitted pixel data of the video signal and obtaining a first transmitted pixel value accordingly; a first comparator, for comparing a first resolution value and the first transmitted pixel value and accordingly outputting the odd/even determining signal; wherein the first resolution value is a number of pixels of the first frame; wherein when the first transmitted pixel value is smaller than the first resolution value, the odd/even determining signal represents odd, and when the first transmitted pixel value is not smaller than the first resolution value, the odd/even determining signal represents even; and a second comparator, for comparing a second resolution value and the first transmitted pixel value and accordingly outputting a reset signal; wherein the second resolution value is twice the first resolution value; wherein when the first transmitted pixel value equals the second resolution value, the reset signal represents reset; wherein when the first counter receives the reset signal representing reset, the first counter resets the first transmitted pixel value; an odd/even frame generating circuit, for generating an odd frame signal and an even frame signal according to the first frame transmitted from the video signal; wherein the odd frame signal comprises pixel data of odd rows of the first frame, and the even frame signal comprises pixel data of even rows of the first frame; and an interlace scan controlling circuit, for generating an interlace scan controlling signal and an interlace data controlling signal according to the odd/even determining signal, the odd frame signal and the even frame signal, to control a scan driving circuit and a data driving circuit respectively; wherein when the odd/even determining signal represents odd, the interlace scan controlling signal controls the scan driving circuit to generate scan driving signals in odd scan lines of the scan driving circuit, and the interlace data controlling signal controls the data driving circuit to output pixel data of odd scan lines of the first frame; wherein when the odd/even determining signal represents even, the interlace scan controlling signal controls the scan driving circuit to generate scan driving signals in even scan lines of the scan driving circuit, and the interlace data controlling signal controls the data driving circuit to output pixel data of even scan lines of the first frame.