Patent ID: 7759998
Filing Date: 2010-07-20
Classification: H03K,H03L

Abstract:
1. A timing adjustment circuit for controlling timing for latching a data signal based on an external timing signal, said timing adjustment circuit comprising: a variable delay circuit for delaying said external timing signal by a variable delay time to generate a delayed timing signal; a first latch circuit for latching said data signal based on a first clock signal having a specific phase relationship with respect to said delayed timing signal; a second latch circuit for latching said data signal based on a second clock signal having a first delay time with respect to said first clock signal; a third latch circuit for latching said data signal based on a third clock signal having a second delay time with respect to said first clock signal, said second delay time being larger than said first delay time; and a judging circuit for comparing output data of said first through third latch circuits among each other, to control said variable delay time based on a result of comparison.