Patent ID: 8173500
Filing Date: 2012-05-08
Classification: H01L

Abstract:
1. A method comprising: forming buried layers at upper portions of a bipolar transistor region, a CMOS region and a DMOS region of a semiconductor substrate, respectively; forming an epitaxial layer on the semiconductor substrate; forming a collector area connected to the buried layers on the epitaxial layer of the bipolar transistor region; forming an isolation layer that defines a base area and an emitter area; forming a well area on the epitaxial layer of the CMOS region and the DMOS region; forming the base area below the isolation layer in the semiconductor substrate of the bipolar transistor region, and forming the base electrode at an upper portion of the base area; forming gates at the CMOS region and the DMOS region of the semiconductor substrate; and forming a poly-emitter area at an upper portion of the base area, which is spaced apart from the base electrode by the isolation layer, in the bipolar transistor region.