Patent ID: 7394447
Filing Date: 2008-07-01
Classification: G02F,G09G

Abstract:
1. An electro-optical device, comprising: a substrate; a plurality of scanning lines and a plurality of data lines that are arranged so as to cross each other in an image display region on the substrate; and a plurality of pixel portions that are coupled to the plurality of scanning lines and the plurality of data lines, n image signal lines provided on a peripheral area located on a periphery of the image display area on the substrate, n (where n is a natural number equal to or greater than two) serial to parallel converted image signals being supplied to the n image signal lines, a sampling circuit provided on the peripheral area, the sampling circuit including a plurality of thin film transistors, each having (i) a drain that is coupled to a drain wiring line arranged from the data line in a direction in which the data line extends, (ii) a source that is coupled to a source wiring line arranged from the image signal line in a direction in which the data line extends, and (iii) a gate that is arranged to be sandwiched between the drain wiring line and the source wiring line in a direction in which the data line extends, the plurality of thin film transistors being arranged to correspond to the plurality of data lines; and a data line driving circuit that supplies sampling circuit driving signals to the gate of the thin film transistors of the sampling circuit, the data line driving circuit supplying the same sampling circuit driving signal to the gates of all of the thin film transistors within the same group of n thin film transistors that are coupled to n simultaneously driven data lines among the plurality of data lines, and two adjacent thin film transistors of the sampling circuit are located adjacent to each other and on opposite sides of a boundary between thin film transistor groups, the two adjacent thin film transistors having the opposite arrangement of source and drain wiring lines so that the sources of the two adjacent thin film transistors are arranged between the two drains of the two adjacent thin film transistors in plan view.