Patent ID: 6373095
Filing Date: 2002-04-16
Classification: H01L

Abstract:
An NVRAM cell having increased coupling between a control gate and a floating gate comprising:a substrate having two field isolation structures for separating a transistor from an adjacent transistor; a region between said isolation structures forming a conduction channel connecting a source and a drain; an oxide layer disposed over said conduction channel; a layer of polysilicon extending over said oxide layer to each of said isolation structures, and thence extending upwards forming a pair of vertically extending sidewalls parallel to the length of said conduction channel forming a u-shaped floating gate in the form of a channel open at two ends thereof, a second oxide layer disposed within the interior of said u-shaped floating gate, and along the exterior surface of said u-shaped floating gate sidewalls; and a second layer of polysilicon formed over said second oxide layer, which forms a control gate which is coupled to said floating gate exterior sidewall surface and said interior of said u-shaped floating gate through said second oxide layer.