Patent ID: 6324088
Filing Date: 2001-11-27
Classification: G11C,H01L

Abstract:
A dynamic random access memory, comprising:an array of memory cells, each comprised of two storage elements;a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices; andtest mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch circuit responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory elements, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory elements, and wherein said test mode logic is responsive to an all row high test condition.