Patent ID: 7569450
Filing Date: 2009-08-04
Classification: H01L

Abstract:
1. A semiconductor fabrication method, comprising: providing a semiconductor structure which includes: (a) a semiconductor substrate, (b) an electrically insulating region on top of the semiconductor substrate, (c) a first semiconductor region on top of and in direct physical contact with the semiconductor substrate, and (d) a second semiconductor region on top of the insulating region, wherein the first semiconductor region and the second semiconductor region are electrically insulated from each other; forming a spacer region which is sandwiched between, and is in direct physical contact with, both the first semiconductor region and the second semiconductor region, wherein the spacer region electrically insulates the first semiconductor region from the second semiconductor region, and wherein the spacer region is direct physical contact with the semiconductor substrate; after said forming the spacer region, forming a first trench, wherein the first trench is formed in the first semiconductor region and the semiconductor substrate; and after said forming the spacer region, forming a second trench, wherein the second trench is formed in the second semiconductor region.