Patent ID: 6538331
Filing Date: 2003-03-25
Classification: B82Y,G06K,G11C,H01L,H05K

Abstract:
A semiconductor device comprising:a substrate having a main surface and a plurality of electrodes on the main surface; a first semiconductor chip having a main surface and a plurality of bonding pads formed along one side of the main surface, the first semiconductor chip being mounted on the main surface of the substrate; a second semiconductor chip having a main surface and a plurality of bonding pads formed along one side of the main surface, the second semiconductor chip being stacked over the main surface of the first semiconductor chip; first wires electrically connecting respective ones of the bonding pads of the first semiconductor chip with corresponding ones of the plurality of electrodes, the first wires being connected at first connecting portions of the plurality of electrodes, respectively; second wires electrically connecting respective ones of the bonding pads of the second semiconductor chip with corresponding ones of the plurality of electrodes, the second wires being connected at second connecting portions of the plurality of electrodes, respectively; and a resin sealing the first semiconductor chip, the second semiconductor chip, the first wires, the second wires and the plurality of electrodes; wherein the second semiconductor chip is stacked over the main surface of the first semiconductor chip while being offset in a direction parallel to the one side of said first semiconductor chip and in a direction perpendicular thereto; wherein the first semiconductor chip and second semiconductor chip have a circuit of the same function formed thereon and a same arrangement of the bonding pads; wherein the first semiconductor chip and the second semiconductor chip are arranged such that the one sides thereof, along which the bonding pads thereof are formed, are facing towards the plurality of electrodes, respectively; wherein the first connecting portions are electrically connected with the second connecting portions via the electrodes of the substrate; wherein the second connecting portions are arranged farther from the one side of the first semiconductor chip than the first connecting portions; and wherein distances between each of the first connecting portions and corresponding ones of the second connecting portions in a direction perpendicular to the one side of the first semiconductor chip is larger than distances between them in a direction parallel to the one side of the first semiconductor chip.