Patent ID: 8937829
Filing Date: 2015-01-20
Classification: G06F,G11C

Abstract:
1. A method of designing an efficient hybrid non-volatile memory cell and a hybrid memory array architecture, the method comprises: connecting a one or more transistors to a memristor, wherein the memristor is a memory element; providing a word line, wherein the word line is a gate terminal of the one or more transistors; providing a set of two bit lines, wherein a value of a data carried in the set of two bit lines are mutually opposite to each other; creating a control logic circuit, wherein the control logic controls an operation related with an accessing of the hybrid non-volatile memory cells, and wherein the control logic minimizes a state drift during a read operation from the hybrid non-volatile memory cell, wherein the state drift is minimized by reading the data with a decaying voltage, wherein a direction of read is from OFF state to ON state; connecting a pluralities of hybrid non-volatile memory cells and forming a hybrid memory array architecture; and accessing the hybrid memory array architecture for a read and write operation.