Patent ID: 8077525
Filing Date: 2011-12-13
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array configured to have a plurality of blocks arranged thereon, each of said blocks being configured by an assembly of NAND cell units, each of said NAND cell units including a plurality of nonvolatile memory cells connected in series and having a first select gate transistor and a second select gate transistor disposed at respective ends thereof; word lines configured to commonly connect control gates of said memory cells aligned in a first direction; and a first select gate line and a second select gate line configured to commonly connect gates of said first select gate transistors and said second select gate transistors aligned in said first direction, respectively, a data erase operation in said nonvolatile semiconductor memory device being executed by first applying a pre-charge voltage to said word lines, then setting to a floating state said word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to said word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where said memory cell array is formed, thereby altering a threshold voltage of said memory cells in said selected block.