Patent ID: 6369824
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A computer system comprising:an integrated core and graphic controller device including a core logic controller portion and a graphic controller portion; a system memory pool; a stand-alone frame buffer memory pool separate from said system memory pool; a first memory data bus interconnecting said integrated core and graphic controller device and said system memory pool; a second memory data bus interconnecting said integrated core and graphic controller device and said frame buffer memory pool; and a memory address and control signal bus interconnecting said integrated core and graphic controller device, said system memory pool and said frame buffer memory pool; said graphic controller portion of said integrated core and graphic controller device being capable of generating a same set of address signals received by said system memory pool and said frame buffer memory pool via said memory address and control signal bus such that said graphic controller portion is able to access simultaneously first word part display data from said system memory pool via said first memory data bus and second word part display data from said frame buffer memory pool via said second memory data bus.