Patent ID: 9048328
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a plurality of memory cells being provided on the semiconductor substrate in a memory cell region; and a peripheral transistor disposed in a peripheral circuit region different from the memory cell region, wherein each of the plurality of memory cells has a first gate electrode disposed on the semiconductor substrate with a first gate insulating film, the first gate electrode having a first charge storage layer, a first inter-electrode insulating film, and a first control gate electrode film, wherein a first cavity is interposed between an upper surface of the first charge storage layer and the first inter-electrode insulating film, wherein the peripheral transistor has a second gate electrode disposed on the semiconductor substrate in the peripheral circuit region with a second gate insulating film, the second gate electrode having a second charge storage layer, a second inter-electrode insulating film, and a second control gate electrode film, and wherein a second cavity is interposed between an upper surface of the second charge storage layer and the second inter-electrode insulating film.