Patent ID: 7944256
Filing Date: 2011-05-17
Classification: H03D,H03L

Abstract:
1. A semiconductor integrated circuit device comprising: a first frequency comparison circuit having a first signal and a second signal inputted, performing comparison using one of: same edges of both of the first signal and the second signal; and a rising edge of one of the first signal and the second signal and a falling edge of the other one of the first signal and the second signal; as comparison objectives, making judgment that a frequency of the second signal is higher and outputting a first potential level to a second comparison node when a comparison objective edge of the second signal appears at least two times between continuous two comparison objective edges of the first signal, and making judgment that a frequency of the first signal is higher and outputting a first potential level to a first comparison node when an edge of the first signal appears at least two times between continuous two edges of the second signal; a second frequency comparison circuit having the first signal and the second signal inputted, performing comparison using a rising edge of one of the first signal and the second signal and a falling edge of the other one of the first signal and the second signal as comparison objectives when the first frequency comparison circuit uses same edges of both of the first signal and the second signal as comparison objectives, performing comparison using same edges of both of the first signal and the second signal as comparison objectives when the first frequency comparison circuit uses a rising edge of one of the first signal and the second signal and a falling edge of the other one of the first signal and the second signal as comparison objectives, making judgment that a frequency of the second signal is higher and outputting a first potential level to a fourth comparison node when a comparison objective edge of the second signal appears at least two times between continuous two comparison objective edges of the first signal and making judgment that a frequency of the first signal is higher and outputting a first potential level to a third comparison node when an edge of the first signal appears at least two times between continuous two edges of the second signal; a first control circuit transmitting only a first potential level of one of the first comparison node and the second comparison node outputted first after outputting of a first potential level to one of the third comparison node and the fourth comparison node in every time when the first potential level is outputted to one of the third comparison node and the fourth comparison node; and a second control circuit performing a desired processing according to a first potential level of one of the first comparison node and the second comparison node transmitted by the first control circuit, and wherein each of the first frequency comparison circuit and the second frequency comparison circuit comprises: a set reset latch circuit latching a second potential level to a first node and a third potential level to a second node according to one of the first signal and a signal obtained by inverting the first signal and latching a third potential level to the first node and a second potential level to the second node according to one of the second signal and a signal obtained by inverting the second signal; a first flip-flop circuit outputting one of a first potential level and a fourth potential level to one of the first comparison node and the third comparison node by taking in a potential level of the first node using one of the first signal and a signal obtained by inverting the first signal as a clock trigger; and a second flip-flop circuit outputting one of a first potential level and a fourth potential level to one of the second comparison node and the fourth comparison node by taking in a potential level of the second node using one of the second signal and a signal obtained by inverting the second signal as a clock trigger, wherein the first control circuit transits to an active state when a first potential level is outputted to one of the third comparison node and the fourth comparison node, transmits potential levels of the first comparison node and the second comparison node to a first control node and a second control node during the active state and transits to an inactive state when a first potential level is transmitted to one of the first control node and the second control node, and wherein the second control circuit performs a desired processing according to potential levels of the first control node and the second control node.