Patent ID: 7487428
Filing Date: 2009-02-03
Classification: G06F,G11C

Abstract:
1. An error-correcting fully-buffered memory module comprising: a substrate having wiring traces formed thereon for conducting signals; contact pads along a lower edge of the substrate, the contact pads for mating with a memory module socket on a motherboard; a buffer chip mounted to the substrate; a packet interface, in the buffer chip, for receiving incoming serial packets from the motherboard through the contact pads, and for generating outgoing serial packets for transmission through the contact pads to the motherboard; memory chips mounted to the substrate, the memory chips having address, data, and control inputs that are isolated from the contact pads by the buffer chip; a memory controller, in the buffer chip, for generating address, data, and control signals to the memory chips in response to the incoming serial packets received from the motherboard, and for reading read-data and error-correction code (ECC) bits from the memory chips in response to a read command extracted from the incoming serial packets; and an error-correction controller, coupled to the memory controller, for generating the ECC bits from write-data extracted from incoming serial packets by the packet interface, and for checking the ECC bits read from the memory chips by the memory controller; wherein the memory chips store the ECC bits generated by the error-correction controller and the write-data extracted by the packet interface, whereby the ECC bits are locally generated by the error-correction controller and locally checked on the error-correcting fully-buffered memory module.