Patent ID: 7362765
Filing Date: 2008-04-22
Classification: H04L

Abstract:
1. An integrated circuit comprising: M sorter blocks, wherein each sorter block has a user-selectable number of entries of one or more entries, each entry comprises a time stamp value, represented in a floating point format, and a connection value, there are a total of N entries for all the M sorter blocks, and M is an integer 2 or greater, wherein upon receiving a first packet of information on a first port, storing a first time stamp, represented in a floating point format, and a first connection value in a first entry of a first sorter, upon receiving a second packet of information on the first port, storing a second time stamp, represented in a floating point format, and a second connection value in a second entry of the first sorter, upon receiving a third packet of information on a second port, storing a third time stamp, represented in a floating point format, and a third connection value in a first entry of a second sorter, and upon receiving a fourth packet of information on the second port, storing a fourth time stamp, represented in a floating point format, and a fourth connection value in a second entry of the second sorter.