Patent ID: 7446407
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A chip package structure, comprising: a substrate, comprising a first surface, a second surface and a through hole; a chip, arranged on the first surface of the substrate and electrically connected thereto, wherein the through hole of the substrate exposes a portion of the chip; a first B-stage adhesive, arranged between the chip and the first surface of the substrate, wherein the chip is attached to the substrate through the first B-stage adhesive; a plurality of bonding wires, connected between the chip and the second surface of the substrate via the through hole; a heat sink, arranged on the first surface of the substrate and covering the chip; a molding compound, arranged on the second surface of the substrate and covering the bonding wires and a portion of the substrate; and a heat dissipation adhesive layer, arranged between the chip and the heat sink in direct contact and bonding the chip and the heat sink, wherein the heat dissipation adhesive layer is smaller than the chip size and the heat dissipation adhesive layer is a second B-stage adhesive, wherein an area of the heat dissipation adhesive layer from the chip to the heat sink is gradually reducing.