Patent ID: 7392229
Filing Date: 2008-06-24
Classification: G06F,G06K,H04L

Abstract:
1. For use in support of a host device through a host device interface, a general purpose set theoretic processor comprising: a pattern memory including a reaction memory unit for receiving source data from said host device and outputting a potential response based on the source data in accordance with a stored pattern; a recognition network for receiving the potential response from the pattern memory and transforming the potential response into an output response comprising: an aggregation network for receiving and processing the output data comprising: a local clock and sequencer coupled to said pattern memory, said recognition network and said aggregation network for synchronizing and propagating said source data, said potential response, said output response and said transformed data; and a data transfer unit for exchanging the source data and the transformed data between said aggregation network and said host device interface.