Patent ID: 6560663
Filing Date: 2003-05-06
Classification: G01R,G06F

Abstract:
A system for preventing bus contention in a multifunction integrated circuit under testing, comprising:an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit; a bus included in the integrated circuit; at least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block coupled to the bus and coupled to accept the test inputs; and an output enable controller included in the integrated circuit, the output enable controller coupled to the second functional block and operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated such that the test inputs can propagate through the first functional block and the second functional block while contention for the bus between the first functional block and the second functional block is prevented, wherein the first functional block is of a higher priority than the second functional block as implemented by the output enable controller such that the first functional block can preempt the bus from the second functional block during testing.