Patent ID: 7843019
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. An integrated circuit die comprising: substrate means for providing a given electrical potential; on at least one surface of said substrate, epitaxial means for containing circuitry elements; surrounding said die, scribe line means for sawing integrated circuit dice into separate die; between said scribe line means and said blocks of circuitry means, seal ring means for substantially isolating said blocks of circuitry means from said scribe line means such that contaminants are prevented from entering said blocks of circuitry means from said scribe line means, wherein a first region of said seal ring means has a substantial electrical short circuit connection to said substrate and a second region of said seal ring means has a substantially electrical open circuit coupling to said substrate, such that electrical noise from said digital circuitry means is substantially prevented from affecting said analog circuitry means via a path through said substrate and said seal ring means; and in said epitaxial means, surrounding said digital circuitry means and segregating said digital circuitry means from said analog circuitry means, a first depletion region means having a dopant type substantially opposite the dopant type of the epitaxial means regions containing said digital circuitry.