Patent ID: 8803189
Filing Date: 2014-08-12
Classification: H01L

Abstract:
1. A circuit structure comprising: a substrate comprising an upper portion and a lower portion; a patterned mask layer over and in direct contact with the upper portion of the substrate, the patterned mask layer comprising a plurality of gaps; a buffer/nucleation layer disposed over the substrate and within the gaps in the patterned mask layer, wherein the buffer/nucleation layer comprises a silicon-containing material; an intermediate layer disposed below the buffer/nucleation layer within the gaps in the patterned mask layer, the intermediate layer consisting essentially of a metal, a metal-alloy, a metal-carbide, or a metal carbon-nitride; and a group-III group-V (III-V) compound semiconductor layer disposed within the gaps in the patterned mask layer and over the buffer/nucleation layer, and further extending above the gaps to form a continuous layer over the patterned mask layer and the gaps in the patterned mask layer.