Patent ID: 6693297
Filing Date: 2004-02-17
Classification: H01L,Y10S

Abstract:
A thin film transistor structure formed on a substrate comprising:a plurality of transistor elements each including a gate electrod; a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer having lower openings for contact holes located on each of said transistor elements; an interlayer insulator layer having upper openings for the contact holes extending over said passivation layer, each of said upper and lower openings are self-aligned with each other over the substrate; an electrical conductive layer located on inner walls of each of the contact holes, said inner walls are formed by upper and lower openings tapered smoothly and continuously by an anisotropic etching process, and wherein at least one contact hole extends through the interlayer insulator layer and the passivatian layer to contact either the source or drain electrode and at least another contact hole extends through the interlayer insulator layer, the passivation layer and the gate insulating layer to contact the gate electrode.