Patent ID: 8987796
Filing Date: 2015-03-24
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; first, second, third, fourth, and fifth conductive lines embedded in the semiconductor substrate, arranged in a first direction in this order, and extending in a second direction that is perpendicular to the first direction; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a fourth semiconductor pillar located between the fourth and fifth conductive lines; a first information storage element electrically connected to an upper portion of the first semiconductor pillar; a second information storage element electrically connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate, extending in the first direction, and connected to lower portions of the first, second and third semiconductor pillars, at least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars, wherein the second and fourth semiconductor pillars are dummy pillars and are not electrically connected to said first or second information storage elements.