Patent ID: 7849249
Filing Date: 2010-12-07
Classification: G06F

Abstract:
1. A mother-board, comprising: a processing unit having a plurality of lanes, the lanes comprising lanes of a first group and lanes of a second group; a first switch circuit and a second switch circuit receiving a control signal having a digital first state or a digital second state and selectively turning on in response to the control signal; a first graphics interface having M lanes, each of the M lanes comprising a transmitter and a receiver and the M lanes including X and Y lanes, wherein M, X, Y are positive integers, X and Y being smaller than M, wherein a second graphics interface having X1 lanes connected to the second switch circuit and selectively electrically connected to the lanes of the second group of the data processing unit through the second switch circuit when the control signal is in its second state to turn the second switch circuit on, X1 being a positive integer and each of the X1 lanes comprising a transmitter and a receiver.