Patent ID: 6087902
Filing Date: 2000-07-11
Classification: H03L

Abstract:
A method for locking the frequency of an oscillator output signal produced by a phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO), said method comprising the steps of:initializing a control voltage of said VCO to less than a locking voltage;comparing an input signal to said oscillator output signal;generating an error signal corresponding to the difference in phase of said input signal and said oscillator output signal only when there is a difference in said phases, wherein said error signal consists of positive current for positive phase differences and negative current for negative phase differences, wherein an amplitude of said positive current has a larger magnitude than an amplitude of said negative current for substantially all operating conditions; andapplying said error signal to a governable oscillator to generate said oscillator output signal, said error signal causing said oscillator output signal to be substantially phase aligned with the input signal.