Patent ID: 6734522
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A transistor comprising:an NPN transistor provided with an N-type emitter, a P-type base, and N-type collector, an emitter diffusion region and a collector compensation diffusion region around the base and the emitter for decreasing a saturation voltage; and a parasitic PNP transistor in a region where the NPN transistor is formed, the parasitic PNP transistor operating under saturation of the NPN transistor, wherein the collector compensation diffusion region is arranged to encircle the base and the emitter, a buried diffusion region is provided under the base and the emitter, said buried diffusion region having an opening, and a portion of an N-type epitaxial region directly contacts a P-type substrate at the opening, the portion of the epitaxial region directly contacting the P-type substrate is located between the base and the collector compensating diffusion region.