Patent ID: 6560738
Filing Date: 2003-05-06
Classification: G01R

Abstract:
A method of estimating a fault propagation path for extracting a fault propagation path in a combinational logic circuit by repeating decisions and implication operations for a logical state to estimate a logical state inside said combinational logic circuit and comparing the estimated logical state with an expected value which indicates a logical state in a normal operation of said combinational logic circuit, said method comprising the steps of:detecting with said implication operation, as a newly implication-capable gate, a gate connected to an input side of a normal signal line estimated as in a logical state equal to said expected value and a gate connected to input and output sides of a signal line in a fault state estimated as in a logical state different from said expected value; and initializing a signal line on an output side of a gate estimated as in a logical state equal to said expected value with an implication operation for said implication-capable gate to a logical state before said implication operation.