Patent ID: 6687322
Filing Date: 2004-02-03
Classification: G06F,H03L

Abstract:
A dual mode clock alignment device, comprising:a clock buffer cell arranged to receive a first clock, the clock buffer cell delaying the first clock; a PLL arranged to receive the delayed first clock from the clock buffer, the PLL being configured to output a second clock; and a first set and a second set of buffers arranged to receive the delayed first clock from the clock buffer cell for operating in a first clock mode, the first and second sets of buffers being further arranged to receive the second clock from the PLL for operating in a second clock mode, wherein the first set of buffers delays the received clock by a first delay to output a third clock and the second set of buffers delays the delayed clock by a second delay to output a fourth clock, and wherein the first, third, and fourth clocks are all aligned when operating in the second clock mode.