Patent ID: 8772154
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A method for manufacturing an integrated circuit, comprising: depositing an interlayer dielectric (“ILD”) layer over a semiconductor device; depositing a barrier polish stop layer over the ILD layer; depositing a capping layer over the barrier polish stop layer; patterning at least the capping layer, the barrier polish stop layer, and the ILD layer to create a plurality of etch features therein; plating metal over the capping layer, the barrier polish stop layer, and into the plurality of etch features to produce a metal overburden overlying the capping layer and the barrier polish stop layer and to produce a plurality of conductive interconnect features in the ILD layer, the barrier polish stop layer, and the capping layer; and chemical mechanical planarizing the integrated circuit to remove the metal overburden and the capping layer and expose the barrier polish stop layer, wherein chemical mechanical planarizing comprises: