Patent ID: 9170816
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. A Very Long Instruction Word (VLIW) processor, comprising: multiple processing units; an execution pipeline, which comprises at least first and second pipeline stages that are cascaded so that program instructions, specifying operations to be performed by the processing units in successive cycles of the pipeline, are fetched from a memory by the first pipeline stage and conveyed to the second pipeline stage, which causes the processing units to perform the specified operations; and control circuitry, which is coupled to determine when a VLIW program instruction currently being fetched, decoded or executed in a stage of the execution pipeline in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to hold the program instruction in the first pipeline stage for reuse in the subsequent cycle, if the determined instruction is in the first stage of the pipeline, and if the determined instruction is in a subsequent stage of the pipeline, to copy the instruction from the pipeline stage in which it is currently being fetched, decoded or executed, for reuse.