Patent ID: 6445050
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate having a drain region, a source region, and a channel region disposed between the drain region and the source region; a gate structure on the semiconductor substrate, said gate structure including: a gate dielectric on a portion of the channel region; a conductive gate aligned on the gate dielectric, and a cap structure selected from the group consisting of: a silicide layer aligned on the conductive gate and an insulative cap aligned on the silicide layer; and an insulative cap aligned on the conductive gate; a first insulative spacer on a first sidewall of the gate structure; a second insulative spacer on a second sidewall of the gate structure; a first conductive stud in contact with the first insulative spacer, and in electrical contact with the drain region, wherein the first conductive stud includes a first conductive material; and a second conductive stud in contact with the second insulative spacer, and in electrical contact with the source region, wherein the second conductive stud includes a second conductive material, and wherein a top surface of the first conductive stud, a top surface of the second conductive stud, and a top surface of the gate structure are coplanar.