Patent ID: 6108312
Filing Date: 2000-08-22
Classification: H04J,H04L

Abstract:
An apparatus for automatically activating a clock master circuit in a stack of Fast Ethernet repeaters comprising:a first stackable Fast Ethernet repeater including:a first on pin having a first on pin logical state, the first on pin logical state being indicative of whether or not the first stackable Fast Ethernet repeater is configured in the stack of Fast Ethernet repeaters so that no other Fast Ethernet repeater occupying a position in the Fast Ethernet repeater stack that is before the position of the first Fast Ethernet repeater is powered on;a weak pull up voltage source connected to the first on pin, the weak pull up voltage being derived from a switched power supply in the Fast Ethernet repeater so that when the Fast Ethernet repeater is powered on, the weak pull up voltage is present and when the Fast Ethernet repeater is powered off, the weak pull up voltage is not present; anda clock master circuit having an enable input wherein the enable input is controlled by the first on pin logical state;a second stackable Fast Ethernet repeater including a power state output pin, the power state output pin being configured to be connected to ground when the second Fast Ethernet repeater is powered on; anda connector cable running from the first Fast Ethernet repeater to the second Fast Ethernet repeater, the connector cable connecting the first on pin from the first stackable Fast Ethernet Repeater to the power state output pin of the second stackable Fast Ethernet repeater.whereby the clock master circuit in the first stackable Fast Ethernet Repeater is enabled based on whether the second stackable Fast Ethernet repeater is powered on.