Patent ID: 6808965
Filing Date: 2004-10-26
Classification: G02F,G09G,H01L

Abstract:
A method of fabricating a thin film semiconductor CMOS circuit having an n-type polycrystalline silicon TFT and a p-type polycrystalline silicon TFT, at least one of the n-type polycrystalline silicon TFT and the p-type polycrystalline silicon TFT having an LDD structure, the method comprising:depositing an amorphous semiconductor film by a low pressure chemical vapor deposition method using silane at a deposition temperature of approximately 530Â° C. or less with a deposition rate of approximately 6 Ã¥/minute or more; forming a gate insulating film having a thickness of 1,000 Ã¥ or less by thermally oxidizing said semiconductor film at a temperature within a range from 900Â° C. to 1160Â° C.; forming a gate electrode such that a gate length of the p-type polycrystalline silicon TFT is shorter than a gate length of the n-type polycrystalline silicon TFT, the gate length of the n-type polycrstyalline silicon TFT being 5 &mgr;m or less; forming an LDD region so that the length of the LDD region is between 0.3 &mgr;m and 4 &mgr;m, and an impurity dose implanted in the LDD region is between 2Ã—1017 cmâˆ’3 and 1Ã—1019 cmâˆ’3; and forming a source and drain region so that a maximum impurity dose in the source and drain region is between 5Ã—1019 cmâˆ’3 and 1Ã—1021 cmâˆ’3, wherein an LDD length of a drain portion of the thin film semiconductor CMOS circuit is Llddd, a distance from a channel portion side edge of a contact hole in said drain portion in a gate electrode is Lcontd, and 0.8Ã—Llddd<1.2Ã—Llddd.