Patent ID: 6711600
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A method of designing a circuit for providing an efficient simultaneous operation of a plurality of RADIX-2 elements to enable a Fast Fourier Transform (FFT) calculation, the circuit being implemented in a logic device including programmable resources for implementing the circuit, the circuit processing N time samples at P RADIX-2 elements within each of S stages, the method comprising the steps of:selecting N, P, and S for implementation of the circuit in a pre-selected programmable logic device, said selection of N, P, and S designating a total area required for the circuit implementation; calculating a calculation time required to perform the FFT calculation within the circuit having N samples, P elements, and S stages; and modifying either of N, P, and S to change either of the total area required and the calculation time of the circuit implementation, wherein P/2 elements are utilized at stages zero through [log2 Pâˆ’1] and P elements are utilized at stages log2 P through S.