Patent ID: 6993668
Filing Date: 2006-01-31
Classification: G06F,Y02D

Abstract:
1. A system for reducing power consumption in a computing device when the computing device executes instructions in a tight loop, the system comprising: a data cache; a translation look-aside buffer; an effective address generation unit in communication with the data cache and the translation look-aside buffer; a previous effective address register that holds a previous effective address from the effective address generation unit; and an effective address comparator that compares a plurality of higher order bits of the new effective address to a corresponding plurality of higher order bits of the previous effective address and that generates an inhibit signal when the plurality of higher order bits of the new effective address is the same as the corresponding plurality of higher order bits of the previous effective address and when all remaining lower order bits of the new effective address have no carry out, the plurality of higher order bits of the new effective address including fewer bits than the new effective address and the plurality of higher order bits of the previous effective address including fewer bits than the previous effective address the inhibit signal inhibiting a new data fetch operation in the data cache, thereby reducing power consumed by the data cache.