Patent ID: 7186607
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. A method for fabricating semiconductor memory devices, the method comprising: forming a gate oxide on a surface of a semiconductor body: forming shallow trench isolations at said surface, said shallow french isolations providing electrically insulating strips spaced apart and arranged parallel to one another in a region provided for a memory cell array; depositing an SiGe layer on said gate oxide subsequent to forming said shallow trench isolations; depositing a gate electrode layer and a wordline layer on said SiGe layer; applying a hardmask layer on said wordline layer; structuring said wordline, said gate electrode layer, and said SiGe layer to form wordline stacks subsequent to said step of applying said hardmask layer, and further structuring said wordline stacks to run transversely to said shallow trench isolations in said region provided for said memory cell array; etching residual parts of said SiGe layer selectively to said gate oxide and said gate electrode to form underetched recesses beneath said gate electrode layer within said SiGe layer on both sides of said wordline stacks; etching away said gate oxide between said wordline stacks after the etching of said SiGe layer; forming an oxide layer on surfaces of the semiconductor body of remaining parts of said SiGe layer, and of said gate electrode layer; depositing a material for a memory layer; removing said material except for residual parts that form strip like memory layers beneath lower edges of said gate electrode layer; implanting dopant to form source/drain regions in said semiconductor body after the formation of said memory layer; depositing a gap filling between said wordline stacks and planarizing said gap filling to an upper surface level of said bardmask layer; applying a cap layer; removing said cap layer and an upper partial layer of said gap filling in an area provided for contact holes to form recesses within said gap filling; forming spacers on sidewalls of said recesses; further removing said gap filling to form contact holes, thereby leaving gap filling residues on sidewalls of said wordline stacks beneath said spacers; forming local interconnects of an electrically conductive material within said contact holes, said local interconnects being provided for an electric connection of said source/drain regions to bitlines; applying an upper insulating layer; structuring said insulating layer, said cap layer, said hardmask layer, said wordline layer, and said gate electrode layer in a peripheral area to residual stacks to form gate electrodes or gate electrodes and conductor tracks; applying sidewall spacers to said residual stacks; implanting a dopant to form source/drain regions provided for CMOS devices; removing said sidewall spacers; applying a dielectric material to fill free spaces between said stacks and to form a basic dielectric provided for the application of a wiring; forming contact holes to said source/drain regions of said CMOS devices and/or to said gate electrodes of said CMOS devices as well as bitline openings and further contact holes to said local interconnects; applying a first metallization to form contact vias in said contact holes and bitlines in said bitline openings, said bitlines contacting said local interconnects by contact visa in said further contact holes; and applying intermetal dielectric and further metallizations to form said wiring.