Patent ID: 7921149
Filing Date: 2011-04-05
Classification: G06F

Abstract:
1. A division and square root arithmetic unit for carrying out a division operation of a higher radix and a square root extraction operation of a lower radix, comprising: a quotient producer for producing a quotient by referring to upper bits of a partial remainder; a partial remainder register for holding the upper bits of the partial remainder in a two's complement representation and lower bits of the partial remainder in a redundant binary representation except the upper bits of the partial remainder; a divisor-partial square root positive register for holding one of a divisor in the division operation and a partially extracted positive square root in the square root extraction operation; a triple divisor-partial square root negative register for holding one of a triple divisor in the division operation and a partially extracted negative square root in the square root extraction operation; a position register for holding processing bit information for connecting the partially extracted square root and quotient digits produced in the quotient producer in the square root extraction operation; a divisor-partial square root selector for selecting one of the divisor, triple divisor, and one of the negative and positive partially extracted square root from the divisor-partial square root positive register and triple divisor-partial square root negative register on the basis of at least one of the quotient from the quotient producer and processing bit information from the position register; a carry save adder for inputting the lower bits of the partial remainder in the redundant binary representation and an output of the divisor-partial square root selector to add input data; a carry propagation adder for inputting the upper bits of the partial remainder in the two's complement representation, the output of the divisor-partial square root selector and a carry signal from the carry save adder to add input data; and a two's complement conversion and shift device supplied with the output of the carry propagation adder and upper Carry Save Add (CSA) data, which is a first bit number of data bits from the upper bits of the carry save adder, the first bit number being determined on the basis of one of the higher radix in the division operation and the lower radix in the square root extraction operation, converting the upper CSA data into two's complement representation data, and shifting the output of the carry propagation adder and the two's complement representation data by a second bit number, the second bit number determined on the basis of one of the higher radix in the division operation and the lower radix in the square root extraction operation to obtain the upper bits of another partial remainder for a next step, wherein the two's complement conversion and shift device comprises: