Patent ID: 6514827
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A method for fabricating a dual metal gate structure for a semiconductor device, comprising the steps of:providing a semiconductor substrate having a PMOS region and an NMOS region formed therein; sequentially depositing a first gate insulating layer and a first metal layer having a work function value of 4.2 eV or less on the semiconductor substrate; sequentially patterning the first metal layer and the first gate insulating layer, so that a first gate is formed in a first region, the first region being either the PMOS region or the NMOS region, and a dummy gate is formed in a second region, the second region being the other of the PMOS and NMOS regions; forming a spacer on each lateral sidewall of the first gate and the dummy gate; forming a source/drain region in the semiconductor substrate adjacent each side of the first gate and the dummy gate; depositing an interlayer dielectric layer on the resultant structure to a thickness between 4,000 and 6,000 Ã¥, including over the source/drain region; polishing the interlayer dielectric layer so as to expose the patterned first metal layer; removing the dummy gate so as to expose a portion of the semiconductor substrate in the second region; sequentially depositing a second gate insulating layer and a second metal layer having a work function value of 4.8 eV or greater on a portion of the semiconductor substrate exposed due to removal of the dummy gate and the interlayer dielectric layer; and polishing the second metal layer and the second gate insulating layer so as to expose the interlayer dielectric layer, thereby establishing a second gate in the second region.