Patent ID: 6359945
Filing Date: 2002-03-19
Classification: H03L

Abstract:
A phase-locked loop (PLL), comprising:a phase detector coupled to receive an input clock signal from a first one of a plurality of clock sources and a feedback signal, wherein said phase detector outputs a phase error signal indicative of a comparison between said input clock signal and said feedback signal; a loop filter coupled to receive said phase error signal and to output an error correction signal; a voltage controlled oscillator coupled to receive said error correction signal and to generate an output signal of the PLL, wherein said feedback signal is indicative of said output signal of the PLL; and switching logic coupled to monitor said input clock signal from said first one of said plurality of clock sources for a failure, wherein said switching logic is configured to cause a corresponding input clock signal from a second one of said plurality of clock sources to be provided to said phase detector in response to said failure; wherein a supplemental correction signal is provided to said loop filter in response to said failure; and wherein in response to said failure, said supplemental correction signal is provided to said loop filter in addition to said phase error signal.