Patent ID: 9087842
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate including a fuse area and a device area; an insulating layer on the substrate; a fuse structure in the insulating layer of the fuse area, the fuse structure including a fuse via pattern electrically connected to a first portion of the substrate through a first conductive layer, a fuse line pattern electrically connected to a top end of the fuse via pattern and extending in a first direction, and a fuse barrier layer surrounding bottom surfaces and sidewalls of the fuse via pattern and the fuse line pattern; and a wire structure in the insulating layer of the device area, the wire structure including a wire via pattern electrically connected to a second portion of the substrate through a second conductive layer, a wire line pattern electrically connected to a top end of the wire via pattern and extending in the first direction, and a wire barrier layer surrounding bottom surfaces and sidewalls of the wire via pattern and the wire line pattern, wherein a width in the first direction of the fuse via pattern is smaller than a width in the first direction of the wire via pattern, and wherein a thickness of the fuse barrier layer is smaller than a thickness of the wire barrier layer.