Patent ID: 6639321
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A flip chip ball grid array package comprising:a thin die having a die thickness reduced from a wafer thickness wherein the die thickness is selected to reduce mismatch of a coefficient of thermal expansion of the thin die to that of a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate; wherein the plurality of thin film layers comprise a first, a second, and a third thin film layer having successively graduated coefficients of thermal expansion from about 7-10 parts per million per degree Kelvin for the first thin film layer, 10-14 parts per million per degree Kelvin for the second thin film layer, and 15-19 parts-per million per degree Kelvin for the third thin film layer.