Patent ID: 6734472
Filing Date: 2004-05-11
Classification: H01L

Abstract:
An integrated circuit device comprising:a) a plurality of signal lines disposed on a substrate; b) a power grid disposed on said substrate and comprising: a plurality of power lines having a first thickness; and a plurality of ground lines having said first thickness, said power grid for supplying power and ground to circuitry of said substrate; and c) a shield mesh disposed on said substrate and comprising: a plurality of power lines having a second thickness; and a plurality of ground lines having said second thickness, wherein each of said plurality of signal lines is disposed between an adjacent power line of said shield mesh and an adjacent ground line of said shield mesh on a layer of said substrate, said shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of said plurality of signal lines; wherein an average line spacing of said power grid is substantially larger than an average line spacing of said shield mesh.