Patent ID: 7203118
Filing Date: 2007-04-10
Classification: H01L

Abstract:
1. A semiconductor storage device having a memory cell array ( 21 ), which employs a memory element constructed of a gate electrode ( 1104 ) formed on a semiconductor layer ( 1102 ) via a gate insulation film ( 1103 ), a channel region ( 1121 ) arranged under the gate electrode ( 1104 ), diffusion regions ( 1107 a , 1107 b ) that are arranged on both sides of the channel region ( 1121 ) and have a conductive type opposite to that of the channel region ( 1121 ), and memory function bodies ( 1105 a , 1105 b ) that are formed on both sides of the gate electrode ( 1104 ) and have a function to retain electric charges, as a memory cell, the semiconductor storage device comprising: a first switch (SW a second switch (SW a charge pump ( a third switch (SW an input voltage determining circuit ( a control circuit (