Patent ID: 6768681
Filing Date: 2004-07-27
Classification: G11C,H01L

Abstract:
A non-volatile memory device comprising:a silicon substrate of a first conductivity type including first and second channel areas adjacent each other; first and second conductive gates formed on the first and the second channel areas, respectively, facing each other; first and second insulation layers formed on the bottom of the first and the second conductive gates, respectively, and on the silicon substrate between the first and the second conductive gates, wherein the first and second insulation layers include ONO layers, the ONO layers including a nitride layer between oxide layers as an electron trapping layer, wherein a portion of the ONO layers formed in the bottom of the first and the second conductive gates functions as dielectric layers for trapping electrons, and a portion of the ONO layers formed between the first and second conductive sates functions as an insulation layer; and first and second junction areas in the silicon substrate of a second conductivity type overlapping the first and the second conductive gates, respectively, wherein the first and second channel areas are defined as a space between the first and the second junction areas.