Patent ID: 8719806
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A method comprising: identifying a code region in an original binary that is predicted to incur a threshold quantity of performance loss during execution of the code region based on one or more predicted cache misses; identifying one or more spawning pairs that each includes a spawn point and a target point; selecting one of the one or more spawning pairs, the target point of the selected spawning pair being associated with the code region, wherein the selecting is based at least in part on a number of dependent instructions that a speculative thread includes in relation to code between the spawn point and the target point; generating an enhanced binary code from the original binary that includes one or more instructions to cause, during execution of a first thread, spawning of a second thread at the selected spawn point; and speculatively pre-executing an instruction associated with the selected target point on the second thread ahead of a portion of the code that begins at the target point, wherein in response to executing the instruction with the second thread a future instruction for the first thread is prefetched into a cache.