Patent ID: 6342451
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A method of fabricating floating gates in a semiconductor device, comprising:sequentially forming a tunnel oxide layer, a polycrystalline silicon layer, an interlayer oxide layer, and a silicon nitride layer on a semiconductor substrate having isolation regions; etching the silicon nitride layer, thereby forming a plurality of silicon nitride layer patterns which are separated from each other; etching the interlayer oxide layer using the silicon nitride layer patterns as an etch mask, thereby exposing a surface of the polycrystalline silicon layer and forming a plurality of interlayer oxide layer patterns; forming sidewall spacers on sidewalls of the silicon nitride layer patterns and the interlayer oxide layer patterns; forming a mask layer on a region of the exposed surface of the polycrystalline silicon layer; removing the silicon nitride layer patterns and the sidewall spacers; and etching the polycrystalline silicon layer using the interlayer oxide layer patterns and the mask layer as an etch mask, thereby exposing the isolation regions.