Patent ID: 6069827
Filing Date: 2000-05-30
Classification: G06F,Y02D

Abstract:
A memory system comprising:a plurality of memory locations each having a pre-defined physical address, said memory locations being arranged in erasable blocks of memory locations;translation means for translating a logical address to one of said predefined physical addresses,means for storing a first pointer that points to a memory location which is to be written to;means for storing a second pointer that points to one of said erasable blocks which is to be erased, said erasable block which is to be erased being the next unerased erasable block in a predetermined sequence of erasable blocks, the predetermined sequence including said memory location to be written to; andcontrol means being provided to progress the first pointer sequentially through the blocks of memory locations in order of said predetermined sequence, and to ensure that there is always at least one erased erasable block in said predetermined sequence of blocks between the erasable block containing said memory location indicated by the first pointer and the erasable block indicated by the second pointer.