Patent ID: 8037438
Filing Date: 2011-10-11
Classification: G06F

Abstract:
1. A method for determining a plurality of buffer insertion locations in a net for an integrated circuit design, comprising: calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for an addition of a wire segment to the first sub-tree, comprising: updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types, comprising: using a computer or processor to merge the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel.