Patent ID: 7237098
Filing Date: 2007-06-26
Classification: G06F

Abstract:
1. A microprocessor, comprising: a first return stack, for providing a first prediction of a target address of a return instruction; a branch target address cache (BTAC), for providing a second prediction of said target address of said return instruction, and for providing an override indicator, wherein said override indicator indicates a predetermined value if said first prediction mispredicted said target address for a first instance of said return instruction; branch control logic, coupled to said first return stack and said BTAC, for causing the microprocessor to branch to said second prediction of said target address, and not to said first prediction, for a second instance of said return instruction, if said override indicator indicates said predetermined value; and a second return stack, coupled to said branch control logic, for providing a third prediction of said target address of said return instruction.