Patent ID: 6233197
Filing Date: 2001-05-15
Classification: G11C

Abstract:
A multi-port semiconductor memory comprising:first and second data ports;a plurality of memory cells arranged in rows and columns, wherein each of the columns comprises first and second pairs of complementary bit lines, which are coupled to each of the memory cells that are in that column, and wherein the first pair of bit lines cross one another between every N and N+1 of the memory cells that are in that column, where N=2.sup.M and M is an integer variable greater than zero;a plurality of row address input bits for each of the first and second ports, which include a least significant row address, bit and address the plurality of memory cells; anda data inversion circuit coupled between the first pair of bit lines and the first data port, which selectively inverts the first pair of bit lines as a function of the first port's (M+1)th row address input bit only, as measured from the least significant row address input bit.