Patent ID: 6138219
Filing Date: 2000-10-24
Classification: H04L

Abstract:
For use in a system having a master controller such as a central processing unit having parallel data ports and a random access memory (DRAM) each connected to a common systems bus interface, an improved DRAM architecture comprisingan array of multi-port internally cached DRAM banks (AMPIC DRAM) each comprising a plurality of independent serial data interfaces connected between a separate external I/O data write resource port and the corresponding internal DRAM memory through a corresponding data caching multi-cell slot buffer;each DRAM bank being connected to a single multi-cell slot buffer and to a single destination I/O data read resource port, each multi-cell slot buffer dedicated to that DRAM bank for respectively storing buffered data destined for that DRAM bank and for reading out the stored data solely to the dedicated I/O data read resource port;a cross-bar switch interposed between each I/O data write resource port and the corresponding slot buffer, but with all I/O data write resource ports connected to input data to each cross-bar switch, allowing the I/O data write resource port to write to any cell within the multi-cell slot buffer.