Patent ID: 6174782
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A fabrication method for a lower method of the capacitor, the method comprising:providing a substrate with gates and source/drain (S/D) regions;forming landing pads on the substrate for connecting to the S/D regions;forming a first dielectric layer on the substrate;forming in sequence a stop layer, an insulating layer, and a mask layer on the first dielectric layer;patterning the insulating layer and the mask layer, so that a capacitor opening is formed to expose the stop layer;forming a spacer on a sidewall of the capacitor opening;performing a self-aligned etching process to remove the stop layer and the first dielectric layer, with the mask layer and the spacer serving as an etching mask, so that a node contact opening which exposes the landing pad is formed, wherein the capacitor opening and the node contact opening forms a damascene contact opening, and sizes of the spacer and the capacitor opening determine a size of the node contact opening;removing the mask layer and the spacer until the insulating layer is exposed;forming a conformal conducting layer to cover the damascene contact opening;performing chemical mechanical polishing (CMP) to remove the conducting layer on the insulating layer; andremoving the insulating layer so as to complete the manufacture of the lower electrode of the capacitor.