Patent ID: 6617884
Filing Date: 2003-09-09
Classification: H03K,H03L

Abstract:
A circuit comprising:a first register having a first data input, a first clock input coupled to a first clock signal, and a first data output; a second register having a second data input coupled to the first data output, a second clock input coupled to the first clock signal, and a second data output; a third register having a third data input, a third clock input coupled to a second clock signal, and a third data output; a fourth register having a fourth data input coupled to the third data output, a fourth clock input coupled to the second clock signal, and a fourth data output; a first logic gate, coupled to the first and third data outputs, having a first logic output coupled to a first clear input of the first register; and a second logic gate, coupled to the second and third data outputs, having a second logic output coupled to a second clear input of the second register.