Patent ID: 6479339
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of fabricating an embedded integrated circuit, comprising the steps of:providing a semiconductor substrate with a plurality of gate stacks; forming a first dielectric film on said semiconductor substrate and gate stacks; forming a silicon nitride film on said first dielectric film; selectively removing said silicon nitride film from over a first type of NMOS transistor and a first type of PMOS transistor thereby leaving said silicon nitride film over a second type of NMOS transistor and a second type of PMOS transistor; forming a first patterned film such that said first type of NMOS transistor and said second type of PMOS transistor is exposed and said first type of PMOS transistor and said second type of NMOS transistor is covered; implanting said first type of NMOS transistor with a n-type species to form LDD structures in said first type of NMOS transistor wherein said n-type species is blocked by said silicon nitride film and does not enter said second type of PMOS transistor; and implanting said first type of NMOS transistor with a p-type species to form pocket regions in said first type of NMOS transistor wherein said p-type species penetrates said silicon nitride film and simultaneously forms LDD structures in said second type of PMOS transistor.