Patent ID: 6157671
Filing Date: 2000-12-05
Classification: H03K

Abstract:
A circuit for digitally monitoring a duty cycle of a pulse width modulated signal, the circuit comprising:a counter portion, a digital filter, and a storage device;the counter portion connectable to receive the pulse width modulated signal and operable to monitor the received pulse width modulated signal for a predetermined time period during which a count value is established, the established count value corresponding to the portion of the predetermined time period during which the pwm signal is in a predetermined state;the digital filter connected to receive the count value established by the counter portion and connected to receive a stored count value from the storage device, the digital filter operable to establish a filtered count value based upon the count value and the stored count value input thereto;the storage device connected to receive the filtered count value established by the digital filter;wherein the counter portion includes a first counter connected to receive the pulse width modulated signal and operable to count only when the pulse width modulated signal is in the predetermined state, andwherein the counter portion further includes a sampling counter having an output connected to a reset input of the first counter, a predetermined output of the sampling counter effective to reset the first counter, the sampling counter operable to provide the predetermined output to the first counter on a periodic basis.