Patent ID: 8861282
Filing Date: 2014-10-14
Classification: G11C,H01L

Abstract:
1. A method for performing an erase operation in a non-volatile storage device, comprising: determining that an erase command has been made to erase a plurality of non-volatile storage elements of a NAND string; in response to the determining that the erase command has been made, determining whether a condition is met for erasing a first select gate transistor of the NAND string, the NAND string is formed on a substrate; and in response to the determining that the condition is met for erasing the first select gate transistor: performing an erase operation comprising one or more erase-verify iterations, each erase-verify iteration of the one or more erase-verify iterations comprises an erase portion during which an erase voltage is applied to the substrate while a control gate voltage of the first select gate transistor and a control gate voltage of the plurality of non-volatile storage elements are set to allow erasing of the first select gate transistor and the plurality of non-volatile storage elements, respectively, and a verify portion which performs an erase-verify test for the first select gate transistor.