Patent ID: 9064974
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method, comprising: forming a first well in a first region of a substrate, the first well being doped type for a transistor of a first type; forming a second well in a second region of the substrate adjacent to the first well, the second well being doped for first and second transistors of a second type; forming at least one shallow trench isolation structure in the substrate isolating the first region from the second region; forming a barrier trench structure in the substrate between the first transistor and the second transistor, the barrier trench isolating a diffusion region of the first transistor from a diffusion region of the second transistor; and forming a material spanning the barrier trench structure and connecting the diffusion region of the first transistor to the diffusion region of the second transistor, wherein the material spanning the barrier trench structure is on a same level of a device as the first and second transistors, wherein the forming the barrier trench structure comprises: etching a trench into the substrate; and filling the trench with gate material that is used to form gates of the first and second transistors by depositing a gate dielectric and gate electrode material within the trench when forming the gates of the first and second transistors.