Patent ID: 7598142
Filing Date: 2009-10-06
Classification: H01L

Abstract:
1. A method comprising: epitaxially depositing a silicon germanium epi region on a substrate; epitaxially depositing a carbon doped silicon epi region on the substrate; forming an isolation structure on the substrate between the silicon germanium epi region and the carbon doped silicon epi region; forming a first set of spacers on the silicon germanium epi region; forming a second set of spacers on the carbon doped silicon epi region; forming a first high-k gate dielectric layer in a trench between the first set of spacers on the silicon germanium epi region; depositing a first metal gate electrode atop the first high-k gate dielectric layer; depositing a second high-k gate dielectric layer in a trench between the second set of spacers on the carbon doped silicon epi region; depositing a second metal gate electrode atop the second high-k gate dielectric layer; implanting ions within the silicon germanium epi region to form a first source region and a first drain region; implanting ions within the carbon doped silicon epi region to form a second source region and a second drain region; and forming electrical contacts to the first and second source regions and to the first and second drain regions.