Patent ID: 6297667
Filing Date: 2001-10-02
Classification: H03K

Abstract:
A collection of self-dual processing cells, connected according to a regular interconnection topology to form a locally self-reconfigurable processing system, each of said cells possessing a configuration memory for specifying mappings from inputs to outputs, and each of said cells operating at any time in one of two modes, each of said cells having multiple sides, each of said sides having a C input for controlling the mode of said cell, and each of said sides also having a D input for exchanging information between said cell and other cells, said collection comprising:(a) a cell, called a program channel head cell, including within its said configuration memory configuration data which causes information transfer from the D input of one side of said head cell, said side being called a connected input side, to the D output of one side of said head cell, said side being called a connected output side, said configuration data optionally specifying modification of said information transfer, said modification depending upon the value of one or more additional D inputs of said cell, said configuration memory also including configuration data which causes information transfer from the D input of another side of said cell, said side called a secondary connected input side, to the C output of said cell's said connected output side, said configuration data optionally specifying modification of said information transfer, said modification depending upon the value of one or more additional D inputs of said cell,(b) a first plurality of processing cells, called a program channel and including said program channel head cell, each cell of said program channel being adjacent to at least one other cell of said program channel according to said interconnection topology, each cell of said program channel including within its said configuration memory configuration data which causes information transfer from the D input of one side of said cell, said side being called a connected input side, to the D output of one side of said cell, said side being called a connected output side, said configuration data optionally specifying modification of said information transfer, said modification depending upon the value of one or more additional D inputs of said cell, said first plurality of cells situated within said locally self-reconfigurable processing system so that:i) a first cell from said plurality, called an initial program channel cell, has its connected output side adjacent, according to said interconnection topology, to the connected input side of a second cell from said plurality if said plurality contains at least two cells,ii) said second cell's connected output side is adjacent, according to said interconnection topology, to the connected input side of a third cell from said plurality if said plurality contains at least three cells, iii) said third cell's connected output side is adjacent, according to said interconnection topology, to the connected input side of a fourth cell from said plurality if said plurality contains at least four cells,and so on, continuing to a last cell of said plurality, said last cell being said program channel head cell, said first plurality of cells thereby forming a bucket brigade assembly which transfers information from the D output of said initial program channel cell's connected output side through all cells of said plurality to the D output of said program channel head cell's connected output side, and(c) a second plurality of processing cells, called a control channel, each cell of said control channel being adjacent to at least one other cell of said control channel according to said interconnection topology, each cell of said control channel including within its said configuration memory configuration data which causes information transfer from the D input of one side of said cell, said side being called a connected input side, to the D output of one side of said cell, said side being called a connected output side, said configuration data optionally specifying modification of said information transfer, said modification depending upon the value of one or more additional D inputs of said cell, said second plurality of cells situated within said locally self-reconfigurable processing system so that:i) a first cell from said plurality, called an initial control channel cell, has its connected output side adjacent, according to said interconnection topology, to the connected input side of a second cell from said plurality if said plurality contains at least two cells,ii) said second cell's connected output side is adjacent, according to said interconnection topology, to the connected input side of a third cell from said plurality if said plurality contains at least three cells,iii) said third cell's connected output side is adjacent, according to said interconnection topology, to the connected input side of a fourth cell from said plurality if said plurality contains at least four cells,and so on, continuing to a last cell of said plurality, called the control channel head cell, said second plurality of cells thereby forming a bucket brigade assembly which transfers information from the D output of said initial control channel cell's connected output side through all cells of said plurality to the D output of said control channel head cell's connected output side, said control channel head cell also being situated so that said control channel head cell's connected output side is adjacent, according to said interconnection topology, to said program channel head cell's secondary connected input side, whereby said initial control channel cell can control said program channel head cell's C output of said head cell's connected output side, and said initial program channel cell can control said program channel head cell's D output of said head cell's connected output side.