Patent ID: 6813325
Filing Date: 2004-11-02
Classification: H04J,H04L

Abstract:
A system for synchronizing a digital data stream to an external reference clock, comprising:a counter configured to receive a clock reference signal and to provide a first counter output responsive to a predetermined number of periods encountered in the received network clock reference signal; a data frame synchronization detector configured to receive a data stream and generate a data frame reference output responsive to a particular item in each subsequent frame in the data stream; a first comparator coupled to receive the first counter output and the data frame reference output, the first comparator configured to generate an output indicative of which of the first counter output or the data frame reference signal arrived first; a sliding window state table coupled to receive the first comparator output and a sliding window control input indicative of an active sliding window, the sliding window state table configured to generate a predetermined bit-manipulation output responsive to the first comparator output and the sliding window control input, wherein the sliding window state table comprises an array of N windows and a plurality of options associated with each of the N windows; and a frame state recorder coupled to receive the first comparator output and a sliding window sensitivity threshold value, the frame state recorder configured to adjust the active current sliding window in response to receiving the same value from the first comparator output for a number of data frames equal to the sliding window sensitivity threshold.