Patent ID: 6258634
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of protecting an Integrated Circuit against an electro-static discharge (ESD), said method comprising the steps of:forming a first semiconductor region of a first conductivity type;forming a second semiconductor region of a second conductivity type adjacent said first semiconductor region;forming a third semiconductor region of a first conductivity type adjacent said second semiconductor region, said third semiconductor region being an n-well region in a p-type substrate;forming a fourth semiconductor region of a second conductivity type adjacent said third semiconductor region, said second and fourth semiconductor region being two separate and isolated p-type regions in said n-well;forming a fifth semiconductor region of a first conductivity type adjacent said fourth semiconductor region, said first and fifth semiconductor region each being an n-type semiconductor region in each of said p-type regions;forming a first terminal over said first semiconductor region and in electrical contact therewith;forming a second terminal over said fifth semiconductor region and in electrical contact therewith;forming a low impedance conductive path across said two terminals.