Patent ID: 6372626
Filing Date: 2002-04-16
Classification: H01L,Y10S

Abstract:
A method of reducing a step height between first and second conductive lines that are laterally spaced apart on an integrated circuit substrate, but that do not overlap on the integrated circuit substrate, the first conductive line being elevated on the integrated circuit substrate relative to the second conductive line to create the step height, the step height reducing method comprising the step of:forming a dummy conductive line beneath the second conductive line and vertically overlapping with the second conductive line by an amount that is greater than zero but less than one half the width of the second conductive line to further elevate the second conductive line on the integrated circuit substrate and thereby reduce the step height between the first and second conductive lines, wherein the second conductive line and the dummy conductive line vertically overlap by an amount that is greater than zero but less than one half the width of the second conductive line.