Patent ID: 8158475
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, the method comprising: forming a first high-voltage well (HVW) region of a first conductivity type overlying a semiconductor substrate; forming a second HVW region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first HVW region; forming a gate dielectric extending from over the first HVW region to over the second HVW region; forming a gate electrode on the gate dielectric, wherein the gate electrode comprises a first portion directly over the second HVW region, and a second portion directly over the first HVW region, wherein the first portion has a first impurity concentration lower than a second impurity concentration of the second portion; forming a mask to cover the firstportion of the gate electrode, wherein the second portion of the gate electrode is not covered; performing an implantation to form a drain region in the second HVW region and a source region on an opposite side of the gate dielectric than the drain region, wherein the first portion of the gate electrode is not implanted, and wherein the second portion of the gate electrode is implanted; and forming an insulation region in the second HVW region, wherein the gate electrode has an edge directly over the insulation region, and wherein the mask has an edge on the gate electrode and horizontally between an inner edge of the insulation region and an interface between the first and the second HVW regions.