Patent ID: 7872629
Filing Date: 2011-01-18
Classification: G09G,G11C

Abstract:
1. A circuit constructed by connecting a plurality of fundamental circuits each comprising a gate line driving circuit, a timing control circuit, a first holding device control circuit, and a second holding device control circuit, wherein: said gate line driving circuit comprises a gate line charging device, a gate line discharging device, and a gate line holding device; a first terminal of said gate line charging device is connected to a fundamental clock CK a gate terminal of said gate line charging device is connected to an output terminal of said timing control circuit; a second terminal of said gate line charging device is connected to a first terminal of said gate line discharging device and a first terminal of said gate line holding device and becomes an output terminal of said fundamental circuit; a gate terminal of said gate line discharging device is connected to an output terminal of said fundamental circuit of a post stage and connected to a second auxiliary pulse in said fundamental circuit of a final stage; a second terminal of said gate line discharging device is connected to a low-level voltage; a gate terminal of said gate line holding device is connected to an output terminal of said first holding device control circuit; and a second terminal of said gate line holding device is connected to the low-level voltage, wherein: said second holding device control circuit comprises a setting device, a resetting device, and a holding capacitor; a first terminal and a gate terminal of said setting device are connected to a fundamental clock CK a second terminal of said setting device is connected to a first terminal of said resetting device and a first terminal of said holding capacitor and becomes an output terminal of said second holding device control circuit; a gate terminal of said resetting device is connected to a third auxiliary pulse in said fundamental circuit of a first stage, connected to a first auxiliary pulse in said fundamental circuit of a second stage, and connected to an output terminal of said fundamental circuit of two stages before in said fundamental circuits of a third and subsequent stages; a second terminal of said resetting device is connected to the low-level voltage; and a second terminal of said holding capacitor is connected to the low-level voltage.