Patent ID: 6324239
Filing Date: 2001-11-27
Classification: G06F,G11C,H03K

Abstract:
A shifter for N-NARY logic, comprising:an input configured to receive an input numerical value represented as a first plurality of N-NARY 1 of N signals where N is greater than 2, each of the N-NARY 1 of N signals being implemented on a set of physical wires;an output configured to provide an output numerical value represented as a second plurality of N-NARY 1 of N signals where N is greater than 2, each of the N-NARY 1 of N signals being implemented on a set of physical wires;a shift amount input that receives a shift amount and that determines the relationship of the output with respect to the input; anda circuit configured to receive the input and to provide the output upon receiving the input, the output having a relationship with respect to the input defined by a shift operation wherein no one-to-one correspondence exists between the wires of the input and the wires of the output.