Patent ID: 9223912
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A method of providing resistance-inductance-capacitance-mutual inductance (RLCK) parasitic extraction for electronic design of an integrated circuit, the method comprising: receiving a simulator netlist extracted from a schematic data file indicative of a simulated representation of the integrated circuit, the simulator netlist describing nets and devices in the schematic data file; receiving a layout data file indicative of a physical layout of the integrated circuit; determining from the layout data file a connectivity list with a plurality of connectivity points in the integrated circuit for connecting generated RLCK parasitics; determining from the layout data file one or more RLCK netlists for the connectivity points; determining from the layout data file and the connectivity list a cross-reference between the connectivity points and nets and devices in a netlist; determining from the cross-reference, the simulator netlist, and the one or more RLCK netlists an updated simulator netlist which includes RLCK parasitics for the connectivity points in the integrated circuit; and outputting an indication of the updated simulator netlist.