Patent ID: 6307787
Filing Date: 2001-10-23
Classification: G11C

Abstract:
A read redundancy assembly in a flash memory device, the assembly comprising:an array of memory cells, the memory cells comprising a regular memory cell and a redundant memory cell;the regular memory cell comprising a defective memory cell and non-defective memory cell, each regular memory cell having an input/output designator and a storage address;a regular first memory cell comprising one of the regular memory cells;a first address comprising the storage address of the regular first memory cell;a defective first memory cell comprising one of the defective memory cells;a defective address comprising the storage address of the defective first memory cell;decoding circuitry configured to generate a defect decoding signal in response to the input/output designator of the defective first memory cell if said circuitry determines that the first address is the defective address, the defect decoding signal corresponding to said input/output designator;the decoding circuitry being further configured to generate a regular decoding signal if said circuitry determines that the first address is not a defective address, the regular decoding signal corresponding to the input/output designator of the regular first memory cell;a multiplexer stage having multiplex outputs, the multiplexer stage configured to select and apply at a multiplex first output a regular output signal in response to the regular first memory cell and in response to the regular decoding signal corresponding to the input/output designator of the regular first memory cell, the multiplex first output being the multiplex output corresponding to the input/output designator of the regular first memory cell; andthe multiplexer stage being further configured to select and apply at a multiplex second output a redundant output signal in response to the redundant memory cell and in response to the defect decoding signal corresponding to the input/output designator of the defective first memory cell, the multiplex second output being the multiplex output corresponding to the input/output designator of the defective first memory cell.