Patent ID: 6451652
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A method for forming an EEPROM cell together with transistors for peripheral circuits comprising:providing a semiconductor substrate, a gate dielectric layer disposed over said substrate, an electrode disposed over said gate dielectric layer, said electrode further enveloped in an electrode dielectric layer, and a select gate dielectric layer disposed on either side of said electrode dielectric layer; conformally depositing a conductive layer over said electrode dielectric layer and said gate dielectric layers; coating said conductive layer with photoresist; selectively exposing said photoresist to radiation to form a sidewall over said electrode; anisotropically etching said conductive layer, wherein said act of anisotropically etching said conductive layer removes an amount of material equal in thickness to the thickness of said conducting layer+&Dgr;, where &Dgr;whereby said method is characterized in that a predetermined amount of material remains proximate to the edge of said electrode forming a structure that extends a short distance beyond the sides of said electrode.