Patent ID: 6693987
Filing Date: 2004-02-17
Classification: H03L

Abstract:
A dual-loop digitally-tuned clock generator comprising:a reference-clock input, having a reference frequency; a first phase-locked loop, receiving the reference-clock input, for generating a first feedback clock having a first feedback frequency, the first phase-locked loop phase comparing the reference-clock input to the first feedback clock, the first phase-locked loop charging and discharging a first capacitance in response to phase comparison to adjust a first voltage; a second phase-locked loop, receiving the reference-clock input, for generating a second feedback clock having a second feedback frequency, the second phase-locked loop phase comparing the reference-clock input to the second feedback clock, the second phase-locked loop charging and discharging a second capacitance in response to phase comparison to adjust a second voltage; wherein the second voltage differs from the first voltage; a digital-to-analog converter (DAC) coupled between the first voltage and the second voltage, the DAC for generating a selectable voltage, wherein the selectable voltage is a voltage between the first voltage and the second voltage, the selectable voltage being selectable by a digital select input to the DAC; and an output-clock generator, coupled to the DAC by selectable voltage, for generating an output clock having an output frequency, the output frequency determined by the selectable voltage, whereby the output frequency is determined by the selectable voltage of the DAC coupled between the first and second phase-locked loops.