Patent ID: 7900108
Filing Date: 2011-03-01
Classification: G01R

Abstract:
1. Multi-clock system-on-chip comprising at least one core comprising at least two asynchronous clock domains provided for exchanging test data there between, a clock generator unit arranged for delivering primary clock signals for at least some of said clock domains, and at least two clock control modules, arranged respectively for defining said functional clock signals from said primary clock signals and from control signals, intended for setting said clock control modules in a normal mode allowing test data transmission from the corresponding clock domain, acting as an emitter, to at least one receiver clock domain or in a shift mode forcing test clock on said functional clock signals to allow a scan chain shift, characterized in that each clock control module is connected to i) a synchronisation means arranged for switching said clock control module from said shift mode to said normal mode, and ii) a delay means arranged for putting back the emitter launch edge of a functional clock signal intended for the emitter clock domain when said clock control module is set into said normal mode, in order said emitter launch edge be temporally located before each corresponding receiver capture edge of the clock signal(s) intended for the receiver clock domain(s) to which said emitter clock domain must transmit test data.