Patent ID: 6509771
Filing Date: 2003-01-21
Classification: H03K

Abstract:
A programmable circuit for generating an output clock signal having a desired duty cycle, comprising:an operational amplifier for comparing an analog voltage representing the desired duty cycle with an analog feedback voltage, and generating an output control signal in response thereto; a voltage controlled duty cycle generator, responsive to the output control signal of the operational amplifier and having an input clock signal, for generating an output clock signal having the desired duty cycle, wherein the voltage controlled duty cycle generator comprises a plurality of stages, and each stage produces an output tap signal; a multiplexor for receiving an output tap signal from each of the stages and which multiplexor is controlled to select and pass one stage output tap signal having a selected frequency and duty cycle as the output clock signal; a low pass filter, responsive to the output clock signal, for measuring the duty cycle of the output clock signal and for generating the analog feedback voltage for the operational amplifier, thereby providing a closed feedback loop operation.