Patent ID: 6697981
Filing Date: 2004-02-24
Classification: G01R

Abstract:
A failure location evaluating system for evaluating the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, comprising:expected value setting device for obtaining an expected value of a signal line inside a target gate based on an expected value of an input/output terminal of said target gate, with respect to said target gate having a hierarchically defined circuitry composed of basic gates, evaluation processing being defined therein; logical state setting device for obtaining a logical state of the signal line inside said target gate based on a logical state of the input/output terminal of said target gate; temporary decided line retrieving device for retrieving an input/output terminal of a target gate, a temporary logical value being set thereon; and related failure terminal setting device for transmitting information regarding a related failure terminal of the input/output terminal of said target gate to an input side.