Patent ID: 7558357
Filing Date: 2009-07-07
Classification: H04L

Abstract:
1. An apparatus comprising: a digital clock recovery unit configured to receive a data signal and a clock synthesis unit (CSU) clock signal, and configured to generate a recovered clock signal as an output from the data signal and from the CSU clock signal, wherein the digital clock recovery unit is part of a receive channel; a filter operatively coupled to the output of the digital clock recovery unit to receive the recovered clock signal as an input, the filter configured to low-pass filter the recovered clock signal to generate a filtered recovered clock signal; and a clock synthesis unit (CSU) operatively coupled to the output of the filter, the clock synthesis unit (CSU) configured to generate the CSU clock signal at least partially based on the filtered recovered clock signal such that jitter in the CSU clock signal is reduced; a state machine in a signal path between the filter and the CSU, the state machine having a first input operatively coupled to the filtered recovered clock signal and a second input operatively coupled to a local frequency reference signal, wherein the state machine is configured to initially select the second input as an input to the CSU, and then to select the first input as the input to the CSU when filtered recovered signal is within the frequency locking range of the CSU; wherein the digital clock recovery unit, the filter, and the clock synthesis unit (CSU) are arranged in a feedback loop such that filtering of the recovered clock signal by the filter is applied within the feedback loop.