Patent ID: 9166580
Filing Date: 2015-10-20
Classification: H03K

Abstract:
1. A gate signal line drive circuit that supplies a high voltage to gate signal lines in a signal high period periodically repeated, and supplies a low voltage to the gate signal lines in a signal low period which is a period other than the signal high period, the gate signal line drive circuit comprising: a high voltage supply switching element that receives a first basic clock signal which becomes the high voltage in the signal high period at an input terminal thereof, turns on in response to the signal high period, supplies a voltage of the first basic clock signal to the gate signal lines, and turns off in response to the signal low period; a high voltage supply off control circuit that supplies a first low voltage to a switch of the high voltage supply switching element in response to the signal low period to turn off the high voltage supply switching element; and a low voltage supply switching circuit that supplies a second low voltage higher than the first low voltage to the gate signal lines as the low voltage in response to the signal low period, and turns off in response to the signal high period, wherein the high voltage supply off control circuit comprises: wherein the low voltage supply switching circuit comprises: wherein in a first period including two or more signal high periods sequentially coming, and starting from the signal low period, the first low voltage is supplied to the first voltage line, and the second low voltage is supplied to the third voltage line, the first high voltage supply off control element and the first low voltage supply switching element are in a drive on-state to turn on/off, and the second high voltage supply off control element and the second low voltage supply switching element are in a drive off-state to be kept in an off-state.