Patent ID: 7376791
Filing Date: 2008-05-20
Classification: G06F,Y02D

Abstract:
1. A memory system, comprising: a processor providing a data access address; a set of control registers coupled to the processor, storing memory configuration information; a memory device comprising a plurality of entries organized by a first predetermined number of ways, wherein the processor selectively configuring a selected number less than or equal to the first predetermined number of the ways as cache memory belonging to a cacheable region, and configuring remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information in the set of control registers; and a memory controller coupled between the processor and the memory device, determining the data access address corresponding to the cacheable region or the directly addressable region, selecting only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, selecting only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region, and having a cache hit detection circuit comprising: