Patent ID: 8125632
Filing Date: 2012-02-28
Classification: G01N,H01L,H05K

Abstract:
1. A method of fabricating a semiconductor device, comprising the steps of: (a) preparing a wiring substrate having plural wiring patterns, pad patterns, and a solder resist layer on one surface thereof, said plural wiring patterns being covered by said solder resist layer, said pad patterns being exposed from by said solder resist layer; (b) configuring a reference plane over said pad patterns by subjecting said wiring substrate to a three-dimensional measurement, to measure an actual height of solder which is to be formed on each of said pad patterns in a subsequent process; (c) after the step (b), printing solder on said wiring substrate, to form solder patterns on said pad patterns respectively; (d) after the step (c), inspecting height of said solder patterns printed over the substrate with reference to said reference plane; and (e) after the step (d), mounting circuit parts over said one surface of said wiring substrate by using said solder patterns.