Patent ID: 6455369
Filing Date: 2002-09-24
Classification: H01L,Y10S

Abstract:
A method for fabricating a trench capacitor, which comprises:providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; forming a doped layer in the silicon substrate in the lower region of the trench; producing a roughened silicon layer, having silicon grains with a diameter ranging from essentially 10 to 100 nm, in the lower region of the trench by: depositing an amorphous silicon layer on all of the surface of the trench, patterning the amorphous silicon layer by etching such that the amorphous silicon layer is limited to the lower region of the trench, and subsequently nucleating the amorphous silicon layer to form the silicon grains; applying a dielectric intermediate layer on the roughened silicon layer; and filling the trench with a doped layer.