Patent ID: 6553537
Filing Date: 2003-04-22
Classification: H03M

Abstract:
A Reed-Solomon decoding apparatus comprising:a Reed-Solomon decoder operable to perform error correction for input data with a Reed-Solomon code; a correction state monitor operable to detect a process error in the error correction by said Reed-Solomon decoder and monitor a degree of error in the input data; wherein said Reed-Solomon decoder comprises: a syndrome computer operable to compute a syndrome from the input data; an Eucledean algorithm computer operable to compute an error location polynomial and an error evaluation polynomial using the syndrome; an error location computer operable to compute an error location indicating an error byte in the input data from the error location polynomial and the error evaluation polynomial; and an error corrector operable to correct the input data by using the error location and an error magnitude indicating an error bit among bits constituting the error byte indicated by the error location, the error magnitude being computed by either of said Eucledean algorithm computer or said error location computer by using the error location polynomial and the error evaluation polynomial; wherein said correction state monitor is operable to monitor said Eucledean algorithm computer and said error location computer, generate a signal indicating the presence or absence of a process error in each of said Eucledean algorithm computer and said error location computer, and generate a signal indicating the degree of error in the input data from the error location and the error magnitude; wherein said correction state monitor comprises: an error symbol number counter operable to count the number of the error bytes indicated by the error location; and a symbol error rate computer operable to compute a symbol error rate from the total number of symbols in data which is input to said Reed-Solomon decoding apparatus and the number of the error symbols which are counted by said error symbol number counter while a predetermined number of synchronous byte suggestions signals which are output in synchronization with synchronous signals of the input data are counted; wherein the signal indicating the degree of error in the input data includes the symbol error rate; and wherein plural assumable ranges of the error symbol number are previously set, and said symbol error rate computer comprises: a determining unit operable to determine a range including the number of the error symbols which are counted by said error symbol number counter while the predetermined number of synchronous byte suggestion signals are counted in the set ranges; and an error rate output unit operable to previously compute symbol error rates from values, each of which is arbitrarily selected from each of the ranges set in said determining unit, and the total number of symbols in the input data, and output a symbol error rate corresponding to the range determined by said determining unit from the previously computed symbol error rates.