Patent ID: 7586474
Filing Date: 2009-09-08
Classification: G09G

Abstract:
1. A data driving integrated circuit connected to a plurality of data lines of a display, comprising: a plurality of output channels; a selection unit for selecting N data output channels (where N is an integer) from the plurality of output channels, the N data output channels supplying pixel data to a corresponding number of the plurality of data lines in accordance with a desired resolution of the display, wherein a remaining number of output channels is not supplied with pixel data; a shift register portion for sequentially applying sampling signals, wherein the sampling signals is generated by sequentially shifting a source start pulse SSP supplied from a timing controller in response to a source sampling clock signal SSC; and a latch portion for latching the pixel data in response to the sampling signals from the shift register portion, wherein the pixel data is supplied from the timing controller, wherein the pixel data consists of a plurality of bits, wherein the selection unit generates a first to a fourth logical value such that, when the logical value is the fourth logical value, the selection unit selects I data output channels, wherein I is a positive integer smaller than N, when the logical value is the third logical value, the selection part selects J data output channels, wherein J is a positive integer smaller than I; when the logical value is the second logical value, the selection part selects K data output channels, wherein K is a positive integer smaller than J; and when the logical value is the first logical value, the selection part selects M data output channels, wherein M is a positive integer smaller than K.