Patent ID: 6600546
Filing Date: 2003-07-29
Classification: G02F

Abstract:
A method of fabricating an array substrate for an active matrix type liquid crystal display (LCD) device, the method comprising:a) preparing a substrate; b) forming a plurality of gate lines, a plurality of gate pads and gate pad contact holes, and a first insulating layer by depositing a first metal layer and depositing a first insulating layer sequentially on a surface of the substrate and patterning the first metal layer and the first insulating layer to have substantially the same pattern with a first mask such that the plurality of gate lines are parallel with and spaced apart from each other wherein each gate pad is positioned at one end of a corresponding gate line, and wherein each gate pad contact hole has a shape of a through hole passing through the gate pad and the first insulating layer; c) forming a second insulating layer, a semiconductor layer, an ohmic contact layer, and a second metal layer by depositing a second insulating material, a semiconductor material, a doped semiconductor layer, and a second metallic material sequentially over the surface of the substrate; d) forming a plurality of data lines, data pads, source electrodes, drain electrodes, and drain contact holes by patterning the second metal layer with a second mask wherein the data lines cross the gate lines, each data pad is positioned at one end of a corresponding data line, each source electrode is extended from the data lines near the crossing point of the gate line and the data line, the drain electrode is spaced apart from the source electrode, and wherein the drain contact hole is positioned on the drain electrode; e) forming a plurality of back-channels by etching away portions of the ohmic contact layer using the patterned second metal layer as a mask, wherein the channel is positioned between the source and the drain electrodes; f) depositing a third insulating layer on the data lines, the source and the drain electrodes, and the data pads; g) patterning the third insulating layer, the ohmic contact layer, the semiconductor layer and second insulating layer with a third mask to form a passivation layer, wherein the passivation layer has a data pad contact hole having a shape of a through hole positioned over the data pad, and wherein the passivation layer contacts a portion of the second insulating layer and covers the patterned second metal layer and a peripheral portion of the gate line; and h) forming a plurality of pixel electrodes, data pad electrodes, and gate pad electrodes by depositing a transparent conductive layer on the passivation layer, and patterning the transparent conductive layer by a fourth mask, wherein a portion of the pixel electrode overlaps the peripheral portion of the gate line, the pixel electrode is electrically connected with the drain electrode via the drain contact hole, the data pad electrode is electrically connected with the data pad by way of the data pad contact hole, and wherein the gate pad electrode is electrically connected with the gate pad via the gate pad contact hole.