Patent ID: 6026226
Filing Date: 2000-02-15
Classification: G01R,G06F,G06Q,Y10S

Abstract:
A computer-implemented method of compiling an electronic design specifying a plurality of design entities capable of being represented as a plurality of nodes in a design hierarchy tree, said method comprising the following:identifying a node within said design hierarchy tree at which an action point is specified, said action point node specifying a point from which said design may be compiled, simulated and subjected to a timing analysis;automatically applying to said node specified by said action point one or more assignments from one or more nodes located above said action point node; andelaborating lower nodes of said design hierarchy tree from said action point node where said action point is specified down to leaf nodes of said hierarchy tree located below said action point node to produce a netlist for each of said lower nodes, whereby a local compilation, simulation and timing analysis is performed at said action point node where said action point is specified.