Patent ID: 6366941
Filing Date: 2002-04-02
Classification: G06F

Abstract:
A Galois field multiplier, for multiplying first and second operands within a selected Galois field, comprising:a first shiftup circuit for shifting said first operand to a left most bit aligned bit position and presenting the shifted first operand at an output; first AND gate circuitry for ANDing, in a bit-by-bit manner, the second operand with the shifted first operand at the output of said first shiftup circuit, to produce a plurality of intermediate outputs arranged in a sequence; a second shiftup circuit for shifting up a primitive value, corresponding to a primitive polynomial of the selected Galois field, to a left most bit aligned bit position and presenting the shifted primitive value at an output; a plurality of exclusive OR circuits, arranged in a sequence, receiving the plurality of intermediate outputs and the shifted primitive value, wherein a first exclusive OR circuit combines a first two most significant ones of the intermediate outputs, according to the shifted primitive value, to produce a partial sum, wherein each of the others of the plurality of exclusive OR circuits in the sequence combines a partial sum from a previous one of the plurality of exclusive OR circuits in the sequence with a corresponding one of the intermediate outputs, according to the shifted primitive value, to produce a partial sum, and wherein the last of the plurality of exclusive OR circuits in the sequence produces a final partial sum; and a shift down circuit for shifting down the final partial sum to a right most bit aligned bit position, to produce a Galois field product of the first and second operands.