Patent ID: 8310319
Filing Date: 2012-11-13
Classification: H03K

Abstract:
1. A two-way integrator, comprising: a first current source coupled to source a first input current that is representative of an input signal and that varies as a magnitude of the input signal changes; a second current source coupled to sink a second input current that is representative of the input signal and that varies as the magnitude of the input signal changes; a first offset current source coupled to source a first offset current; a second offset current source coupled to sink a second offset current; a capacitor coupled to integrate a sum of the first input current and the first offset current by charging with the first current source and with the first offset current source when a reference signal is at a first logic state, wherein the capacitor is further coupled to integrate a sum of the second input current and the second offset current by discharging with the second current source and with the second offset current source when the reference signal is at a second logic state; a switching reference coupled to receive a pulse signal, wherein the switching reference is adapted to output a first reference voltage responsive to a first pulse of the pulse signal and to output a second reference voltage responsive to a subsequent pulse of the pulse signal; and a comparator coupled to compare the output of the switching reference with a voltage on the capacitor.