Patent ID: 6331947
Filing Date: 2001-12-18
Classification: G11C

Abstract:
An integrated circuit comprising a memory with a non-volatile, random access memory cell comprising first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a MOS RAM cell, the output node of each inverter being selectively connected via the conductor paths of separate access transistors to respective bit lines, the control electrodes of said access transistors being connected to a common word line,the cell being arranged for providing both RAM and programmable Read-Only operation of said memory cell, being characterized in that said cross-coupling means comprising respective capacitor means (C1, C2) each in series with a control electrode of a respective p-type transistor of said first and second inverters, to render both interconnecting nodes between a capacitor and the gate electrode of its associated p-channel transistor floating, and through isolators around these nodes render the cell data-retentive,nodes being transiently and electrically programmable through signals on the bit and word lines of the cell in question,and in that said nodes are radiation-accessible for internal photo-emission inducing short-wave radiation, that renders a non-permanent programmed information in said cell a non-volatile one.