Patent ID: 6023742
Filing Date: 2000-02-08
Classification: G06F,Y02D

Abstract:
A reconfigurable computing architecture for executing a plurality of applications, each application being executed over a plurality of execution cycles, the architecture comprising:a plurality of functional units that are interconnectably arranged to perform a plurality of functions on data, the data comprising a plurality of bits;a plurality of interconnectors that selectably interconnect the functional units to control the flow of data between the functional units;a set of first signals generated to create a state that remains unchanged over the execution cycles of any one of the applications;a set of second signals generated to create a plurality of states that are changeable over the execution cycles; andan input and an output for data, wherein the function being performed on the data by the functional units is selectable by the first signals and the second signals and the interconnectors are arranged in a single dimension to transport the data from the input and to the output and to provide the data to the functional units, the interconnectors interconnect the functional units such that the flow of the data between the functional units is selectable.