Patent ID: 6154829
Filing Date: 2000-11-28
Classification: G06F

Abstract:
A data processor comprising a plurality of processing components which are connected together in a cascade arrangement so as to form a first path and a second path, each of said plurality of processing components comprising:(a) a first input disposed on said first path,(b) a processing unit for:performing, according to a micro instruction, a processing operation on a data signal supplied through said first input, andsending to said first path a data signal representative of a result of said processing operation,(c) a second input disposed on said second path, and(d) a control device for:starting to send said micro instruction to said processing unit upon detection of a processing start request bit of a control signal supplied through said second input, andsending to said second path a signal which lags said control signal by a number of cycles required to complete said processing operation of said processing unit.