Patent ID: 6209087
Filing Date: 2001-03-27
Classification: G06F,H04L

Abstract:
A processor comprising:a first input receiving a first input data, a second input receiving a second input data, a third input receiving a third input data and a fourth input receiving a multiple compare instruction;a logic unit coupled to the first input, the second input, the third input and the fourth input, the logic unit including activatible multiple comparing circuitry which is activated upon receipt of the multiple compare instruction and which performs a comparison between the first input data and a series of predefined characters in the third input data, if the comparison results in the first input data being equal to any character in the series of predefined characters then a character match state is set;a second logic unit coupled to the first input, the second input, the third input and the fourth input, the second logic unit including activatible multiple comparing circuitry which is activated upon receipt of the multiple compare instruction and performs a comparison between the first input data and a predefined boundary, if the first input data is within the predefined boundary then a character boundary state is set if a mask bit in the second input data, at a position equal to the value in the first input data, is set on;an output coupled to both the logic unit and the second logic unit, the output outputting the character match state and the character boundary state information; andwherein the processor can be reprogrammed to execute a different one of many possible instructions.