Patent ID: 6813724
Filing Date: 2004-11-02
Classification: G06F

Abstract:
An interface circuit comprising a plurality of logic circuits including at least a first logic circuit and a second logic circuit operating by receiving a system clock distributed from a common clock signal source, whereinthe first logic circuit includes: data transmission means for transmitting a data signal in synchronization with the system clock and source synchronous clock transmission means for transmitting a source synchronous clock indicating a transmission timing of the data signal, the second logic circuit receiving the transmitted data signal includes: a clock distributor for generating a reception clock based on the received signal of the source synchronous clock; a first reception flip-flop for taking in the data signal transmitted in synchronization with the reception clock; a variable delay circuit connected to an output of the first reception flip-flop; a second flip-flop for taking in the data signal from the variable delay circuit in synchronization with the system clock; and a phase comparator for detecting a phase difference between the reception signal of the source synchronous clock and the system clock and controlling a delay amount of the variable delay circuit to be a value corresponding to the phase difference.