Patent ID: 8365126
Filing Date: 2013-01-29
Classification: G06F

Abstract:
1. An integrated circuit design apparatus, comprising: a layout information storing unit which stores layout information that indicates a layout in an integrated circuit; a scan path connection information storing unit which stores scan path connection information that indicates a connection order of scan path terminals in the integrated circuit; a macro signal terminal position determination unit which determines temporary arrangement positions of a scan-in terminal and a scan-out terminal of each of a plurality of macros with reference to the layout information, and updates the layout information based on said temporary arrangement positions determined; an initial scan path route determination unit which updates the scan path connection information such that, about a scan-in external terminal and the plurality of macros, one of the plurality of macros arranged in a closest distance is connected in turn starting with the scan-in external terminal with reference to the layout information updated by the macro signal terminal position determination unit and the scan path connection information; and a scan path re-routing unit which determines a scan path connection order such that a scan path total wiring length becomes shortest with reference to the layout information updated by the macro signal terminal position determination unit and the scan path connection information updated by the initial scan path route determination unit, and updates the scan path connection information updated by the initial scan path route determination unit based on said determined scan path connection order, wherein a temporary arrangement position of the scan-in terminal and the scan-out terminal of each of the plurality of macros is a centroid position or a center position of said macro.