Patent ID: 6058449
Filing Date: 2000-05-02
Classification: G06F

Abstract:
An arbitration circuit for controlling access through arbitration to a shared data bus shared by a plurality of processors coupled by a corresponding plurality of arbitration lines, said arbitration circuit comprising:a plurality of arbitration registers that register arbitration port traffic, each of the plurality of arbitration registers corresponding to one of the corresponding plurality of arbitration lines;a plurality of ports to communicate data over the shared data bus;a winner detection circuit responsively coupled to each of the plurality of arbitration registers and providing an arbitration acknowledge signal that controls write access to the shared data bus based on a determination of winning an arbitration; anda protocol error detection circuit responsively coupled to each of the plurality of arbitration registers to provide an error detected signal when an error is detected from at least one of the plurality of arbitration registers, wherein:the winner detection circuit is responsively coupled to the error detected signal, andthe winner detection circuit denies write access to the shared data bus in response to receiving the error detected signal from the protocol error detection circuit.