Patent ID: 6037261
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A semiconductor processing method comprising:forming an insulating material over a first node and a second node, the second node being at a different and deeper elevation within the insulating material than the first node, the first node comprising an electrically conductive annular ring formed within the insulating material;first stage etching into the insulating material to form a first opening proximate the first node and to form a second opening proximate the second node, the first stage etching exposing the first node but not exposing the second node;after the first stage etching, second stage etching to extend at least one of the first and second openings, the second stage etching comprising an increased degree of insulating material sidewall polymerization relative to that occurring the first stage etching; andafter the second stage etching, third stage etching to extend at least one of the first and second openings, the third stage etching comprising a degree of insulating material sidewall polymerization which is less than that of the second stage etching.