Patent ID: 6029263
Filing Date: 2000-02-22
Classification: G01R

Abstract:
A method of testing an interconnect that couples first and second digital circuits to one another for communicating data signals therebetween, the first digital circuit being structured to include a scan architecture specified by IEEE Standard 1149.1 that includes a first number of scannable data registers, the second digital circuit employing a scan architecture different from that of the first digital circuit that includes a second number of data registers, the first and second numbers of scannable data registers being coupled to the interconnect for applying data signals thereto and to receive data signals therefrom, the method including the steps of:(a) applying a first test pattern to the second number of scannable data registers;(b) sampling the interconnect with the first number of scannable data registers according to a protocol required by the IEEE Standard 1149.1 that includes the steps of,(i) capturing data signals of the interconnect by the first number of scannable data registers,(ii) shifting into the first number of scannable data registers a second test pattern,(iii) again capturing data signals of the interconnect by the first number of scannable data registers, and(iv) shifting the captured data signals from the first number of scannable data registers;(c) sampling data signals on the interconnect by the second number of scannable data registers;(d) shifting the sampled data signals from the second number of scannable data registers; and(e) comparing the captured data signals and the sampled data signals to first and second standard patterns, respectively, to determine the integrity of the interconnect; and(f) repeating steps (a)-(e) for a plurality of additional test patterns.