Patent ID: 7767525
Filing Date: 2010-08-03
Classification: H01L

Abstract:
1. A method of forming a plurality of vertical transistor structures, comprising: providing a construction having a plurality of vertically-extending pillars over a semiconductor substrate, the pillars having sidewall surfaces and having top surfaces at or below a first elevational height; forming dielectric material along the sidewall surfaces of the pillars; forming gateline material over the substrate and adjacent the pillars, the gateline material being spaced from the pillars by the dielectric material, the gateline material having a top surface at or above the first elevational height; recessing the gateline material so that the top surface of the gateline material is below the first elevational height; implanting a first dopant at an angle that is at least 5° from vertical to form first source/drain implant regions within the pillars, the first source/drain implant regions being aligned relative to the top surface of the recessed gateline material; and implanting a second dopant to form second source/drain implant regions within the pillars, the first and second dopants having opposite conductivity types relative to one another, at least portions of the first source/drain implant regions and the second source/drain implant regions being elevationally higher than the top surface of the recessed gateline material; wherein bottom surfaces of the second source/drain implant regions are elevationally higher than the top surface of the recessed gateline material and are vertically spaced from the top surface of the recessed gateline material.