Patent ID: 7587687
Filing Date: 2009-09-08
Classification: G06F

Abstract:
1. A method of synthesis of a model representing a design of an integrated circuit, the method comprising: inputting to a synthesis tool information representing a modified input model of the design at a particular level of abstraction; inputting user constraints; inputting to the synthesis tool a state file that includes a record of at least one prior soft constraint choice made by the tool, in a prior translation of a prior input model of the design to a prior output model representing the design at a lower level of abstraction, in the absence of a user implementation choice; using the synthesis tool to translate the information to an output model compliant with the inputted user constraints, representing the design at a lower level of abstraction, wherein translating the modified input model includes applying in the same manner the at least one prior soft constraint choice included in the inputted state file if the user constraints do not include a constraint choice selected by the user that conflicts with the at least one prior soft constraint; and producing a record of the information input to the synthesis tool that guided the translation of the modified model, the information including at least one soft constraint choice made by the tool in the course of translating the modified model in the absence of user implementation choice, into an output state file.