Patent ID: 7589993
Filing Date: 2009-09-15
Classification: G11C,Y10S

Abstract:
1. A system LSI semiconductor device comprising: a plurality of static memory cells each comprising N-channel first and second driver MOS transistors, an N-channel first transfer MOS transistor whose source-drain path is coupled between a drain electrode of the first driver MOS transistor and a first bit line, an N-channel second transfer MOS transistor whose source-drain path is coupled between a drain electrode of the second driver MOS transistor and a second bit line, a P-channel first load MOS transistor coupled to the drain electrode of the first driver MOS transistor, a P-channel second load MOS transistor coupled to the drain electrode of the second driver MOS transistor, and being arranged in a memory cell array on a semiconductor substrate; a word line coupled to gate electrodes of the first transfer MOS transistors and gate electrodes of the second transfer MOS transistors, the word line being disposed in a direction perpendicular to the first and second bit lines; a first power voltage line coupled to source electrodes of the first and second driver MOS transistors, arranged along the first and second bit lines, and supplied a first power voltage, a second power voltage line coupled to source electrodes of the first and second load MOS transistors, arranged along the first and second bit lines, and supplied a second power voltage higher than the first power voltage, a memory peripheral circuit coupled to the plurality of static memory cells on the semiconductor substrate; and a logic circuit arranged in a different area from the memory cell area on the semiconductor substrate, wherein during an active operation, a difference power voltage between the first power voltage line and the second power voltage line is larger than a high-level voltage applied to the word line; wherein the first driver MOS transistor and the first transfer MOS transistor are located in a first P-well region on the semiconductor substrate, wherein the second driver MOS transistor and the second transfer MOS transistor are located in a second P-well region on the semiconductor substrate, wherein the first and second load MOS transistors are located in a first N-well region on the semiconductor substrate, the first N-well region being between the first and second P-well regions, wherein the first P-well region includes a first diffusion region having diffusion regions of the first driver MOS transistor and the first transfer MOS transistor, the second P-well region includes a second diffusion region having diffusion regions of the second driver MOS transistor and the second transfer MOS transistor, and the first and second diffusion regions extends along a well boundary between the first P-well region and the first N-well region, wherein gate electrodes patterns of the driver MOS transistors, the transfer MOS transistors and the load MOS transistors are disposed in a direction perpendicular to the well boundary, wherein the gate width size of the first driver MOS transistor is not more than 1.4 times the gate width size of the first transfer MOS transistor and is greater than or equal to the gate width size of the first transfer MOS transistor, wherein the gate width size of the second driver MOS transistor is not more than 1.4 times the gate width size of the second transfer MOS transistor and is greater than or equal to the gate width size of the second transfer MOS transistor, wherein the gate width size of the first load MOS transistor is smaller than the gate width size of the first driver MOS transistor, wherein the gate width size of the second load MOS transistor is smaller than the gate width size of the second driver MOS transistor.