Patent ID: 6723632
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A process for forming an interconnect structure for an integrated circuit, the process comprising:forming a lower interlayer dielectric over a semiconductor workpiece; forming an interconnect metallization layer over the lower interlayer dielectric; patterning a photoresist mask over the interconnect metallization layer, the photoresist including a masked region having a critical dimension and excluding an unmasked region; etching the interconnect metallization layer in the unmasked region to leave a first metal line separated from a second metal line by an inter-line region, a width of the first and second metal lines corresponding to the critical dimension, the first and second metal lines exhibiting a parasitic capacitance; forming a conformal middle interlayer dielectric over the first and second metal lines and over the lower interlayer dielectric in the inter-line region; and forming a third metal line over the conformal middle interlayer dielectric, the third metal line electronically linked with the first metal line and projecting between the first and second metal lines in the inter-line region to elevate the parasitic capacitance and thereby reduce an overall variation in parasitic capacitance; and wherein the interconnect metallization layer has a thickness, and wherein the step of forming the middle interlayer dielectric comprises forming the middle interlayer dielectric with a thickness approximately 20% of the thickness of the interconnect metallization layer.