Patent ID: 7622961
Filing Date: 2009-11-24
Classification: G01R,H03K,H04L

Abstract:
1. A method comprising: latching a plurality of data signals in a corresponding plurality of latches in response to a first transition of a clock signal; latching one of the plurality of data signals in a timing latch in response to the first transition of the clock signal, the one of the plurality of data signals presented to the timing latch after a delay; detecting when the delayed one of the plurality of data signals fails to meet a minimum setup time of the timing latch causing the timing latch to store incorrect data, wherein the minimum setup time of the timing latch is the minimum time lapse during which the delayed one of the plurality of data signals must reach and become stable at the timing latch before the first transition of the clock signal; adjusting an operational parameter of a circuit using feedback logic so that the timing latch stores the one of the data signals incorrectly in a target proportion of clock signal transitions; and forcing, via failsafe-reset logic, the operating parameter to an extreme slow condition.