Patent ID: 7630258
Filing Date: 2009-12-08
Classification: G11C

Abstract:
1. A set associative repair cache system comprising: a main memory comprising identified valid memory locations and identified faulty memory locations; a plurality of repair sets that respectively comprise local repair location addresses arranged and selectable according to a plurality of repair regions; a decoder that receives a repair region address portion of a memory address and decodes the repair region address to select local repair location addresses of the plurality of repair sets; a plurality of comparators associated with the plurality of repair sets that compares selected local repair location addresses with a local repair address portion of the memory address to identify a matching local repair location address by a matching comparator of the plurality of comparators; a plurality of repair register banks associated with the plurality of comparators and the plurality of repair sets that respectively comprise repair registers arranged and selectable according to the plurality of repair regions, wherein a repair register is selected for read/write access from an associated repair register bank of the plurality of repair register banks that is associated with the matching comparator and addressed by the repair region address on identifying the matching local repair location address; and wherein a memory location within the main memory addressed by the memory address is selected for read/write access on a failure to identify the matching local repair location address.