Patent ID: 6374281
Filing Date: 2002-04-16
Classification: G06F

Abstract:
An adder comprising:comparing means for comparing values of n input signals, each of which comprises 1-bit data, with first to n-th predetermined values which are different from each other; a non-volatile memory having first to n+1-th word lines, m (2m&gE;n+1) bit lines which are provided so as to intersect said word lines, and memory cells, each of which is provided at an intersection of each of said word lines and each of said bit lines and each of which has stored 1-bit data; and selecting means for selecting one of said n+1 word lines on the basis of n comparison results of said comparing means to activate the selected word line, wherein said i-th (i=1, . . . , n) predetermined value is greater than iâˆ’1 and less than i, and said comparing means has first to n-th comparators, said i-th (i=1, . . . , n) comparator determining whether the number of input signals having a truth value of 1 out of said n input signals exceeds said first predetermined value, and outputting a i-th comparison result indicative signal, and said selecting means selecting one of said word lines on the basis of said first to n-th comparison result indicative signals, and wherein said selecting means has a first inverting gate for inverting said first comparison result indicative signal to output an inverted signal to said first word line, and a second inverting gate for inverting the inverted signal of said n-th comparison result indicative signal to output an inverted signal to said n+1-th word line, and said i-th (i=1, . . . , nâˆ’1) NOR gate carries out a NOR operation on the basis of said inverted signal of said i-th comparison result indicative signal and said i+1-th comparison result indicative signal to output an operation result to said i+1-th word line.