Patent ID: 7571404
Filing Date: 2009-08-04
Classification: G06F

Abstract:
1. A computer readable storage article of manufacture having computer programming code disposed therein for determining decoupling capacitance (decap) to be added to a semiconductor circuit, said computer programming code when executed by a computer comprising: a) dividing an integrated circuit design layout into a plurality of rectangular tiles such that each of said plurality of tiles is of approximately equal area and includes a plurality of sampling nodes disposed entirely within; b) determining a core violation group of tiles of said plurality of tiles by sampling a voltage level at said plurality of sampling nodes disposed entirely within each of said plurality of tiles, whereby said core violation group of tiles includes less than all of said plurality of tiles of said integrated circuit design layout and includes only tiles of said plurality of tiles having sampling nodes having a sampled voltage waveform which includes a violation voltage level which is less than a specified threshold voltage level during a violation time period, wherein said violation time period begins at a first time instance t c) creating an expanded violation group of tiles which extends outwardly from said core violation group of tiles by a plural number of tiles in a direction away from said core violation group of tiles, and includes said entire core violation group of tiles, and includes tiles of said plurality of tiles of said integrated circuit design layout which are not included in said core violation group of tiles; d) determining a value of decap to be added to said expanded violation group of tiles, including deriving charge transfer equations for said integrated circuit design by integrating modified nodal analysis (MNA) equations over said violation time period [t e) distributing substantially uniformly said decap value among said plurality of sampling nodes within said expanded violation group of tiles to provide a non-violation operating voltage at said plurality of sampling nodes of said expanded group of tiles to eliminate said violation voltage level at said plurality of sampling nodes of said core violation group of tiles, wherein said non-violation operating voltage at said plurality of sampling nodes of said core violation group of tiles is not less than said specified threshold voltage level.