Patent ID: 6266765
Filing Date: 2001-07-24
Classification: G06F

Abstract:
In a data processor, an improved instruction processing system that facilitates processing instructions at a rate of more than one instruction per clock, said system comprising:means for fetching a family of n, n being a predetermined integer, sequential instructions in a program;a pipeline, having a series of pipeline stages, including resources for accepting a family of n instructions at each pipeline stage during a single clock, with said accepted family of the type including multiple nonbranching instructions, with one of said nonbranching instructions being a memory reference type of instruction, so that said pipeline can retire a family of instructions and accept a new family of instructions each clock;a decoder, responsive to a fetched family of instructions, for generating a decode result associated with said fetched family of instructions;means, responsive to said decode result, for issuing said fetched family of instructions during one clock;means, responsive to said decode result, for controlling said pipeline to process said fetched family of instructions and to advance said fetched family through said pipeline stages.