Patent ID: 8778763
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A method for forming a memory cell transistor, comprising: providing a substrate; forming a trench structure in said substrate, said trench structure extends along a first direction; depositing a conductive substance on a surface of said substrate, wherein said conductive substance at least partially occupies an inner space of said trench structure thereby forming a conductive member inside said trench structure; forming one or more dielectric layers on the surface of said substrate, said dielectric layers covering said trench structure and said conductive member therein; forming one or more first conductive layers on top of said dielectric layers; etching said first conductive layers and said dielectric layers to form a hole structure; and forming one or more second conductive layers on top of said first conductive layers, wherein said second conductive layers are deposited into and fill said hole structure thereby forming a plug; performing chemical mechanical polishing process to planarize a surface of said second conductive layers; wherein said first conductive layers and said dielectric layers are etched before said second conductive layers are formed and after said first conductive layers are formed thereby said hole structure only extends through said first conductive layers and said dielectric layers, reaching to the surface of said substrate without extending through said second conductive layers, and said first and second conductive layers function as a bit line structure for said memory cell transistor thereby said hole structure does not extend through said bit line structure completely.