Patent ID: 6584326
Filing Date: 2003-06-24
Classification: G06F,H04B

Abstract:
A circuit for performing serial data protocols and error checking, the circuit comprising:a plurality of external communication ports, including an input/output port wherein said input/output port is coupled to receive serial data output from a subscriber interface module card reader and coupled to transmit parallel data to a central processing unit; a receiver and a transmitter coupled to said input/output port; multiple chip selects for addressing different input sources; multiple data lines for transferring received data characters and for reading and writing to different ones of a plurality of control registers; an address register decodable to obtain different ones of said chip selects, said address register corresponding to a plurality of address lines determining which of said control registers is accessed; a serial-to-parallel data conversion function coupled to receive serial data from different input sources, translate said serial data into parallel data, and transmit said parallel data; an error checking function coupled to perform error checking on said received serial data wherein said error checking function asserts an error signal retransmit request; an error signal/retransmit request detector coupled to receive an asserted one of said error signal/retransmit requests; wherein said transmitter retransmits one of said received data characters in response to a detected one of said asserted error signal/retransmit requests; an extra guard time counter, and wherein an interrupt signal generator coupled to said transmitter and to said extra guard time counter, said interrupt signal generator generating a signal indicative of an end of said retransmission of said data character in response to a detected signal received from said extra guard time counter indicative of an expiration of said extra guard time; and a pollable interrupt line, whereby a source of an interrupt signal is determined.