Patent ID: 6404691
Filing Date: 2002-06-11
Classification: G06F,G11C

Abstract:
A semiconductor memory device comprising:a main memory divided into a plurality of blocks in the unit of a plurality of columns, including a plurality of memory cells each for storing information, arranged in a plurality of rows and a plurality of columns, a cache memory divided into a plurality of blocks in the unit of the same number of columns as said plurality of columns of said each block of said main memory, including a plurality of storage elements each for storing information, arranged in a plurality of columns, said cache memory storing, on the block basis, information read out from said main memory on the block basis, transfer means connected between said main memory and said cache memory for transferring, on the block basis, information read out from said main memory on the block basis to said cache memory, and transfer control means for controlling said transfer means so that said transfer means selectively transfers information read out from said main memory on the block basis to any of said plurality of blocks of said cache memory.