Patent ID: 8446309
Filing Date: 2013-05-21
Classification: G06J,H03M,H04N

Abstract:
1. An analog-to-digital converter for generating an output digital value equivalent to the difference between two analog signal values comprising: at least one input for receiving a first analog signal level and a second analog signal level; an input for receiving a ramp signal; a first counter which is operable to count in a single direction; a second counter which is operable to count in the single direction; a control stage which is arranged to respectively enable the first and second counters based on a comparison of the ramp signal with the first analog signal and the second analog signal; and a subtractor for outputting a difference between a value accumulated by the first counter during a period when it is enabled and a value accumulated by the second counter during a period when it is enabled, wherein the converter is operable over a conversion cycle having two phases, with the ramp signal being reset between phases, and wherein the control stage is operable: during a first phase of the conversion cycle, to compare the ramp signal with the first analog signal level and to enable the first counter during a portion of the time period between the start of the ramp signal and the time at which the ramp signal equals the first analog signal level, and during a second phase of the conversion cycle, to compare the ramp signal with the second analog signal level and to enable the second counter during a portion of the time period between the start of the ramp signal and the time at which the ramp signal equals the second analog signal level; or, during a first phase of the conversion cycle, to compare the ramp signal with the first analog signal level and to enable the first counter during a portion of the time period a time at which the ramp signal equals the first analog signal level and an end of the ramp signal, and during a second phase of the conversion cycle, to compare the ramp signal with the second analog signal level and to enable the second counter during a portion of the time period between a the time at which the ramp signal equals the second analog signal level and an end of the ramp signal.