Patent ID: 9124261
Filing Date: 2015-09-01
Classification: H03K

Abstract:
1. A flip-flop circuit comprising: an evaluation part connected to a first node and a second node to discharge the second node according to a voltage level of the first node, the evaluation part comprising at least two transistors; a conditional delay part connected to the second node to discharge a third node to have a voltage level different from a voltage level of the second node and connected to the first node directly to discharge the third node based on signals from the first and second nodes, the conditional delay part comprising at least two transistors configured to have a stack form; and a keeper logic part connected to the second node and third node to maintain a voltage level of one of the second and third nodes being not discharged, wherein a first discharge path from the second node to a constant ground node is completely separated from a second discharge path from the third node to the constant ground node such that the first and second discharge paths do not share any common path, the evaluation part is triggered according to an edge of a clock signal to perform an evaluation operation, the keeper logic part maintains a logic level of the output signal during half a cycle of the clock signal after the evaluation operation, and a size of each of the at least two transistors included in the conditional delay part is smaller than that of the at least two transistors included in the evaluation part.