Patent ID: 6388332
Filing Date: 2002-05-14
Classification: G06F,H01L

Abstract:
An integrated circuit having a plurality of cells of circuit elements defining a cell layer, conductors disposed in a plurality of layers adjacent the cell layer, and vias connecting conductors in a layer to conductors in other layers, characterized in that:the number of layers of conductors is N, N being four or greater, the first layer being next to the cell level and the Nth layer being remote from the cell level; each cell having a cell border and being connected to a respective power and ground conductor in a first layer adjacent the cell border; power and ground conductors extending across said cells in at least one of the N and N-1 layers; and stacked vias connecting the power and ground conductors of the at least one of N and N-1 layers to respective power and ground conductors of the first layer.