Patent ID: 8270212
Filing Date: 2012-09-18
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a substrate; a plurality of first upper-layer contact members formed over the substrate in a first layer; a plurality of second upper-layer contact members formed over the substrate in the first layer, arranged alternately with the plurality of first upper-layer contact members in a first direction, and shifted from the plurality of first upper-layer contact members in a second direction orthogonal to the first direction; a plurality of plugs formed respectively on the plurality of second upper-layer contact members and made of a metal; a plurality of first metal wirings provided respectively on the plurality of first upper-layer contact members and made of a metal; and a plurality of second metal wirings provided respectively on the plurality plugs and made of a metal, wherein a height of a top surface of each of the plurality of plugs, measured from the substrate, is higher than a height of a top surface of each of the plurality of first metal wirings, measured from the substrate, a width of a bottom surface of each of the plurality of first metal wirings in a shorter-side direction is shorter than a width of a top surface of each of the plurality of first metal wirings in the shorter-side direction, and a width of a bottom surface of each of the plurality of second metal wirings in a shorter-side direction is shorter than a width of a top surface of each of the plurality of second metal wirings in the shorter-side direction.