Patent ID: 7861130
Filing Date: 2010-12-28
Classification: G01R

Abstract:
1. A method for determining a minimum running speed of an integrated circuit containing first logic elements configured to process inputs, and second logic elements configured to determine whether the first logic elements have completed their processing; comprising: identifying at least one critical path in the first logic elements of the integrated circuit; selecting at least one critical test vector for each of said at least one critical path; inputting said at least one critical test vector to the first logic elements of said integrated circuit under ambient conditions; and applying at least one clock speed for each of the at least one critical input vector applied during said inputting; monitoring, during said applying, the integrated circuit for the presence of an error signal, the error signal being based on the at least one clock speed and output of the second logic elements; and identifying the fastest individual clock speed from said at least one clock speed that did not generate the error signal during said monitoring.