Patent ID: 8953391
Filing Date: 2015-02-10
Classification: G11C

Abstract:
1. A semiconductor apparatus comprising: an input buffer configured to be activated during a write operation, and buffer and output inputted data; a data input control unit configured to be activated in the write operation, and transfer data outputted from the input buffer; a data output control unit configured to be activated during a read operation, and transfer data inputted to an output buffer; the output buffer configured to be activated in the read operation, buffer data outputted from the data output control unit, and output the buffered data; a test data input/output unit configured to latch test data inputted from a test data input pad and output test latch data or latch an output of the input buffer and output the test latch data, in response to a test control signal and a test clock; and a test loop control unit configured to transfer data to the data output control unit or transfer the test latch data to the data output control unit, in response to the test control signal, wherein all of the input buffer, the data input control unit, the data output control unit and the output buffer are activated during a test.