Patent ID: 7474546
Filing Date: 2009-01-06
Classification: G06F,G11C

Abstract:
1. A dual match line circuit, comprising: a hit match line coupled to a first plurality of load devices and configured to be precharged to an asserted state; and a miss match line coupled to discharge through a second plurality of load devices and configured to be precharged to said asserted state, wherein each of said second plurality of load devices is activated for discharging by a respective miss signal; wherein said hit match line is additionally coupled to discharge through a first discharge path activated for discharging in response to a hit signal and to discharge through a second discharge path activated for discharging in response to a read/write enable signal; wherein said hit match line and said miss match line are electrically isolated from one another, such that when one or more of said respective miss signals are asserted, current from said hit match line does not discharge through said miss match line.