Patent ID: 6330240
Filing Date: 2001-12-11
Classification: H04J,H04L,H04Q

Abstract:
A switching system, comprising:a plurality of input and output terminals;a buffer memory which switches input cells input through said input terminals to output to said output terminals in accordance with destination information contained in the cells; anda controller including a plurality of address queues, which store write addresses for the cells in said buffer memory in accordance with a destination and a quality class of the cells, and a table which specifies the destination, quality class and the bandwidth of the cells for reading out the cells from said buffer memory,wherein when writing cells to said buffer memory, an address queue is selected from the plurality of address queues based on a destination and quality class of the cells, an address is stored for the cells in said buffer memory, and the cells are written into said buffer memory at the stored address, andwherein when reading out cells from said buffer memory, an address queue is selected from the plurality of address queues corresponding to a destination, quality class and bandwidth of the cells specified by the table, the address stored in the address queue is read out, and the cells stored in said buffer memory is read out using the address read out from the address queue.