Patent ID: 8285765
Filing Date: 2012-10-09
Classification: G06F

Abstract:
1. A fixed-point unit comprising: a control module circuit for providing a first control signal, a second control signal and a third control signal; an arithmetic logic unit (ALU) circuit for selectively performing a logical operation, an arithmetic operation or a value-based operation on a first and second operands based on various combinations of assertions and deassertions of said first and third control signals, wherein said first and second operands are received from a plurality of general purpose registers, wherein said ALU performs a logical operation when said first and third control signals are being asserted, wherein said ALU performs an arithmetic operation when said first and third control signals are being deasserted, wherein said ALU performs a value-based operation when said first control signal is being deasserted while said third control signals are being asserted; and a writeback module circuit for updating a storage location within said plurality of general purpose registers with one of said first and second operands in response to a carry-out signal from said ALU.