Patent ID: 8587999
Filing Date: 2013-11-19
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: semiconductor substrate including a channel formation region and a pair of impurity regions; a first gate insulating layer over the channel formation region; a first gate electrode over the gate insulating layer; a first interlayer insulating layer over the gate electrode; a source electrode and a drain electrode over the first interlayer insulating layer; an oxide semiconductor layer adjacent to the source electrode and the drain electrode; a second gate insulating layer adjacent to the oxide semiconductor layer; a second gate electrode and an electrode adjacent to the second gate insulating layer; and a second interlayer insulating layer over the second gate electrode and the electrode, wherein a capacitor is formed between the electrode and one of the source electrode and the drain electrode, and wherein the source electrode and the drain electrode have a tapered shape with a taper angle from 30° to 60° inclusive.