Patent ID: 6591323
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A controller for a memory partitioned into a plurality of banks and divided into addresses that are accessed by a plurality of row access strobe signals and a plurality of column access strobe signals, the controller comprising:a queue state machine configured to allocate a plurality of memory commands received by said controller among a plurality of transaction state machines; a first of said transaction state machines configured to issue a first strobe request to assert one among said row access strobe signals and said column access strobe signals in response to receiving a first of said memory commands; a second of said transaction state machines configured to issue a second strobe request to assert one among said row access strobe signals and said column access strobe signals in response to receiving a second of said memory commands; and an arbitor configured to arbitrate between said first strobe request and said second strobe request.