Patent ID: 6246089
Filing Date: 2001-06-12
Classification: H01L

Abstract:
An FET semiconductor device including a doped silicon semiconductor substrate having a surface, said substrate being doped with an N type of dopant, including:a tunnel oxide layer over said substrate,a laminated floating gate electrode layer including an intermediate layer of N+ doped polysilicon over said tunnel oxide layer,an interelectrode dielectric layer over said floating gate electrode,a control gate electrode including a layer composed of P+ doped polysilicon over said interelectrode dielectric layer,said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode patterned into a gate electrode stack,a source region and a drain region in said surface of said substrate doped with a P type of dopant, said source region and said drain region being self-aligned with said gate electrode stack.