Patent ID: 8324698
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A STT-MRAM structure formed on a substrate having a CMOS metal layer including a plurality of CMOS landing pads in a device region and a plurality of CMOS connection pads outside the device region that are separated by and coplanar with a first dielectric layer, comprising: (a) a stack of dielectric layers that are formed sequentially from bottom to top on the substrate, comprising; (b) a plurality of intermediate via contacts (VAC) each having a first width that are formed within the first etch stop layer and second dielectric layer in the device region wherein each of said VAC is in electrical contact with an underlying CMOS landing pad, and has a top surface coplanar with said second dielectric layer; (c) a plurality of VAM pads each having a second width greater than said first width, a bottom surface contacting and completely covering a top surface of a VAC, and a top surface that is coplanar with said VAM dielectric layer; (d) a plurality of MTJ elements each having a bottom surface contacting the top surface of a VAM pad, a top surface coplanar with said MTJ ILD layer, and an easy axis dimension and a hard axis dimension; and (e) a BIT line metal layer, comprising;