Patent ID: 6066524
Filing Date: 2000-05-23
Classification: H01L,Y10S

Abstract:
A method for fabricating an SRAM cell, the SRAM cell having first and second access transistors, first and second drive transistors, and first and second load resistors, wherein a first terminal of the first access transistor, a gate terminal of the second drive transistor and a first load resistor terminal are connected to one another to form a first cell node terminal, and a first terminal of the second access transistor, a gate terminal of the first drive transistor and a second load resistor terminal are connected to one another to form a second cell node terminal, the method comprising the steps of:forming the first and second drive transistors each having impurity regions and a gate;forming the first and second access transistors each having impurity regions and a gate overlapping portions of, and in parallel to the gates of the first and second drive transistors;forming an insulating film having contact holes to the impurity regions of the first and second drive transistors; and, forming the first and second load resistors on the insulating film connected to the impurity regions of the first, and second drive transistors.