Patent ID: 6399472
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, said semiconductor device comprising a substrate, a fuse pattern formed on said substrate, an etching stopper layer formed over said fuse pattern so as to cover an area in which said fuse pattern is formed, an interlayer insulation film covering said etching stopper layer, a conductor pattern formed on said interlayer insulation film, a protective film formed on said interlayer insulation film so as to cover said conductor pattern, a bonding contact pad formed in said protective film so as to expose said conductor pattern, and a window formed in said protective film in correspondence to said fuse pattern so as to penetrate through said interlayer insulation film and said etching stopper layer, said method including the step of forming said window, said step of forming said window comprising the steps of:forming a first opening through said protective film and said interlayer insulation film so as to expose said etching stopper layer; and forming a second opening in continuation to said first opening by applying an etching process to said etching stopper layer through said first opening, wherein said exposure of said conductor pattern and said exposure of said etching stopper layer occur simultaneously.