Patent ID: 6323546
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A three-dimensional stacked-type package, comprising:a substrate;a plurality of direct contact through hole type chips stacked with each other as a first stack and a second stack, wherein each chip further comprises:a first silicon substrate, a second silicon substrate and a first insulation layer positioned between the first and second silicon substrates;at least one opening formed in the second silicon substrate and penetrating into the first silicon substrate through the first insulation layer;at least one device positioned on the first silicon substrate;a plurality of contact plugs positioned in the first silicon substrate and exposed by the opening:a plurality of dielectric layers;a plurality of interconnects coupled to the device and the contact plugs, wherein a portion of interconnects are exposed by an uppermost layer of the dielectric layer, thus forming at least one first contact;at least one first bump formed on the first contact;a second insulating layer formed on a surface of the opening with the contact plugs exposed, thus forming a second contact in the opening; andat least one second bump formed on the second contact,wherein each chip is coupled to each other by the bumps, wherein both stacks are attached to the substrate by the bumps, and wherein the first stack is coupled to the second stack.