Patent ID: 8502344
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. A semiconductor device, including a dielectric isolation structure including an insulating film extending in a depth direction, the device having a planar layout and comprising: a compound structure having a plurality of unit structures comprising a first semiconductor region of a first conduction type provided on a supporting substrate with a buried insulating layer intervening, and surrounding a straight-line first electrode, a closed planar-shape gate electrode surrounding the first semiconductor region, and a closed planar-shape second electrode surrounding the gate electrode; a second semiconductor region of a first or second conduction type, provided in a surface region of the first semiconductor region along the first electrode, and electrically connected to the first electrode; a third semiconductor region of a second conduction type, provided in a surface region of the first semiconductor region along the second electrode, separated from the second semiconductor region, and electrically connected to the second electrode, the third semiconductor region having a planar shape which has straight-line portions connected by arc-shaped portions; a fourth semiconductor region of a first conduction type, provided in a surface region of the third semiconductor region along the second electrode, and electrically connected to the second electrode; the gate electrode being provided on the surface of the third semiconductor region between the fourth semiconductor region and the first semiconductor region, with a gate insulating film intervening; a closed planar-shape first dielectric isolation region surrounding the compound structure; a closed planar-shape isolation semiconductor region of a first conduction type, provided on the side opposite the first semiconductor region, with the first dielectric isolation region intervening, the isolation semiconductor region surrounding the first dielectric isolation region; and, a closed planar-shape second dielectric isolation region surrounding the isolation semiconductor region; a local insulating film provided in contact with and on the outside of the third semiconductor region positioned on the outermost side of a compound structure having a plurality of unit structures comprising the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the first electrode, the second electrode, and the gate electrode; the first dielectric isolation region extending from the local insulating film, penetrating the first semiconductor region, and reaching the buried insulating layer; and a third electrode, held at the same potential as the second electrode, and electrically connected to the isolation semiconductor region, wherein a depth of the third semiconductor region positioned on the outermost side of the compound structure is shallower than a depth of other third semiconductor regions, wherein the outermost straight-line portions of the third semiconductor region are shallower in depth than the rest of the straight-line portion of the third semiconductor region which is between the outermost portions.