Patent ID: 8547770
Filing Date: 2013-10-01
Classification: H03K

Abstract:
1. A semiconductor apparatus comprising: a first power supply line and a second power supply line; a first sub power supply line; a first transistor coupled between the first power supply line and the first sub power supply line, and rendered conductive in response to a first signal; a first circuit coupled between the first sub power supply line and the second power supply line, receiving second and third signals and outputting an output signal, the first circuit rendering the output signal one of first and second logic levels designated by a logic level of the second signal during an active state, and fixing the output signal at the first logic level irrespective of the logic level of the second signal during an inactive state; and a first control circuit generating the third signal in response to both of the first signal and a fourth signal that is independent of the first signal, and providing the third signal with the first circuit such that the first circuit is released from the inactive state to the active state in response to the third signal.