Patent ID: 6797564
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A method of forming bit lines and bit line contacts of a memory device, comprising the steps of:providing a substrate having a plurality of gate structures thereon, wherein each gate structure comprises a gate dielectric layer, a gate conductive layer and a cap layer, and wherein a spacer is formed on each sidewall of the gate structure; forming a conductive layer over the substrate to cover the gate structures; planarizing the conductive layer until the cap layer of the gate structures is exposed; removing a portion of the conductive layer but retaining the conductive layer between neighboring gate structures to form a bit line contact; forming a dielectric layer over the substrate to cover the gate structures and the bit line contact; planarizing the dielectric layer until the cap layer of the gate structures and the bit line contact are exposed; forming a stop layer over the dielectric layer such that the bit line contact remains exposed; and forming a bit line over the stop layer, wherein the bit line and the bit line contact are electrically connected.