Patent ID: 6759256
Filing Date: 2004-07-06
Classification: H01L,Y10S

Abstract:
A method of fabricating semiconductors in parallel with the inspection of said semiconductors comprising the steps of:(a) providing a first processing apparatus and a first container containing a number of semiconductor wafers the first container labeled with a first identifier and a second container labeled with a second identifier, and storing said first and second identifiers; (b) while the first processing apparatus is submitting said semiconductor wafers from the first container to a first process, loading selected ones of post-processed semiconductor wafers into said second container as sample wafers for inspection; (c) performing inspection of said sample wafers from the second container; (d) identifying said first and second containers by comparison of identifiers on said containers with identifiers previously stored into memory; and (e) causing a second processing apparatus to submit semiconductor wafers from both containers to a second process, and then returning all semiconductor wafers after submission to said second process back to said first container.