Patent ID: 6696706
Filing Date: 2004-02-24
Classification: H01L,Y10S

Abstract:
A junction field effect transistor (JFET) comprising:a heavily doped n++ substrate forming a drain region; an epitaxial n layer comprising a dopant concentration less than that of said n++ substrate, said epitaxial n layer formed on top of said n++ substrate; a control structure comprising a p-type gate region implanted into said epitaxial n layer; a source region sharing a p-n junction with said p-type gate region; an altered epitaxial region below said p-type gate region for enlarging a depletion region surrounding said p-type gate region; a well region formed below a surface of said epitaxial n layer, said oxide region above said p-type gate region; and an oxide spacer formed on walls of said well region extending from a surface of said epitaxial n layer down into said epitaxial n layer, said oxide spacer for directing implantation of dopants into said altered epitaxial region.