Patent ID: 6710412
Filing Date: 2004-03-23
Classification: G11C,H01L,Y10S

Abstract:
A static semiconductor memory device comprising:first and second bit lines; a word line; first and second access MOS transistors of a first conductivity type, having sources connected to said first and second bit lines, respectively, and having gates connected to said word line in common; and first and second driver MOS transistors of a second conductivity type, different from said first conductivity type, having sources receiving a ground potential, having drains connected to drains of said first and second access MOS transistors, respectively, and having gates connected to the drains of said second and first access MOS transistors, respectively, wherein the drain of said first access MOS transistor is connected to the drain of said first driver MOS transistor using metal wiring without interposing a gate of said second driver MOS transistor therebetween, and the drain of said second access MOS transistor is connected to the drain of said second driver MOS transistor using metal wiring without interposing a gate of said first driver MOS transistor therebetween.