Patent ID: 6342796
Filing Date: 2002-01-29
Classification: G11C,H03L

Abstract:
A delay locked loop (DLL) for use in a synchronous memory device, comprising:a first shift control means for generating a first shift-right signal in response to a first comparison signal; a first shift register for performing only a shift-right operation in response to the first shift-right signal; a first delay line means for controlling each delay amount of internal signals in response to an output of the first shift register, wherein the first delay line means includes a plurality of delay lines, each delay line having a first unit delay; a second shift control means for generating a second shift-right signal and a shift-left signal in response to a second comparison signal; a second shift register for performing a shift-right operation and a shift-left operation in response to the second shift-right signal and the shift-left signal, respectively; and a second delay line means for controlling each delay amount of output signals of the first delay line means, wherein the second delay line means includes a plurality of delay lines, each delay line having a second unit delay smaller than the first unit delay.