Patent ID: 8238192
Filing Date: 2012-08-07
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a memory array having a plurality of memory cells arranged in matrix; first and second ports independent of each other, performing transmission and reception of an input/output signal; a selection circuit capable of selection in accordance with addresses correspondingly input to said first and second ports, with periods of access to said memory array overlapping with each other; said memory array including a plurality of first and second word lines provided in correspondence with memory cell rows respectively, and a plurality of first and second bit lines provided in correspondence with memory cell columns respectively, each said memory cell including a flip-flop circuit for setting first and second storage nodes to one and another of first and second potential levels in accordance with stored data, a first gate transistor having a gate electrically coupled to a corresponding first word line, for electrically coupling a corresponding first bit line to said flip-flop circuit, and a second gate transistor having a gate electrically coupled to a corresponding second word line, for electrically coupling a corresponding second bit line to said flip-flop circuit, said selection circuit including first and second row decoders provided in correspondence with said first and second ports and outputting row selection instructions in accordance with input addresses, respectively, and a plurality of word drivers provided in correspondence with the memory cell rows respectively, each for driving the corresponding first and second word lines in accordance with a result of row selection by said first and second row decoders; a first reading and writing circuit provided in correspondence with said first port and electrically coupled to said plurality of first bit lines, for performing data reading and data writing; a second reading and writing circuit provided in correspondence with said second port and electrically coupled to said plurality of second bit lines, for performing data reading and data writing; and a plurality of switching circuits corresponding to said first reading and writing circuit, provided in correspondence with the memory cell columns respectively, and each of said plurality of switching circuits switching connection of said first reading and writing circuit with the first bit line to electrical connection of said first reading and writing circuit with the second bit line in response to an instruction.