Patent ID: 6960837
Filing Date: 2005-11-01
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit; a semiconductor substrate comprising semiconductor portions of devices; a device level on the semiconductor substrate and in direct mechanical contact with the semiconductor substrate, wherein the device level includes non-semiconductor portions of said devices; a first interconnect level on the device level and in direct mechanical contact with the device level; and a second interconnect level on the first interconnect level and in direct mechanical contact with the first interconnect level, wherein the predefined block is a core comprising comprises a circuit portion and a redistribution portion, wherein the circuit portion includes all functional circuitry of the core, wherein the circuit portion includes a first portion of the substrate, a first portion of the device layer, a first portion of the first interconnect level, and a first portion of the second interconnect level, wherein the redistribution portion includes a second portion of the substrate, a second portion of the device layer, and a second portion of the first interconnect level, wherein the second portion of the substrate and the second portion of the device layer do not include any device, and wherein the plurality of I/O pins are contained in their entirety within the second portion of the first interconnect level in the redistribution portion.