Patent ID: 8492232
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A method for fabricating a microelectronic device comprising: a) forming, from a stack of thin layers on a support, the stack including at least two successive layers based on at least one first semiconductor material, and at least one second semiconductor material different from the first semiconductor material, respectively, at least one first block configured to form at least one transistor source region, at least one second block configured to form at least one transistor drain region, and at least one structure connecting the first block and the second block; b) forming, in a region located between the first block and the second block, at least one first insulating zone against at least one sidewall of the first block and at least one second insulating zone against at least one sidewall of the second block, said first insulating zone and said second insulating zone being arranged to form at least one cavity between them, said cavity forming at least one gate pattern; c) removing, in the cavity, the second material, selective with regard to the first material; and d) depositing in the cavity at least one gate dielectric and at least one gate material so as to form a gate having said pattern.