Patent ID: 6340638
Filing Date: 2002-01-22
Classification: H01L

Abstract:
A method for forming passivation layer on at least one copper conductive element in a semiconductor structure comprising the steps of:providing a semiconductor device having at least one copper conductive element embedded in a first insulating layer; planarizing a top surface to expose said at least one copper conductive element in said first insulating layer; dry etching said top surface of the semiconductor device removing a surface layer of said first insulating layer stopping at an etch-stop layer, said dry etching step forms a first stepped surface between said at least one copper conductive element and said first insulating layer; and depositing conformally a second insulating layer on top of said semiconductor device forming a second stepped surface substantially similar to said first stepped surface, wherein said first and second stepped surfaces provide an interlock between said at least one copper conductive element and said first and second insulating layers thus avoiding peeling of said passivation layer from said top surface of the semiconductor device.