Patent ID: 6020614
Filing Date: 2000-02-01
Classification: H01L

Abstract:
A semiconductor integrated circuit comprising:a semiconductor P type substrate;a plurality of circuit regions formed on said semiconductor substrate wherein each one of said circuit regions is connected to a different power supply;field isolation regions formed on said substrate in the plurality of circuit regions;isolation zones formed between said plurality of circuit regions and separating said plurality of circuit regions wherein a field oxide layer is formed within each one of said isolation zones;field implant regions formed under the field isolation regions in the plurality of circuit regions wherein said field implant regions are formed outside of said isolation zones;deep high energy P+ implant regions formed in the semiconductor substrate under said plurality of circuit regions and each one of said deep high energy P+ implant regions being connected to a power supply terminal of the particular circuit region above said P+ implant region wherein said deep high energy P+ implant regions are absent in said isolation zones.