Patent ID: 6514788
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A method for manufacturing a small contact for a Chalcogenide memory device, said method comprising:forming a via within a first oxide layer on a substrate; depositing a conductive layer on top of said first oxide layer; depositing a second oxide layer on said conductive layer; removing said second oxide layer and said conductive layer such that the remaining portion of conductive layer within said contact is flush with a surface of said first oxide layer; depositing a third oxide layer on said conductive layer, and said first and second oxide layers; removing a portion of said third oxide layer to leave an edge of said third oxide layer essentially perpendicular to said conductive layer; depositing a nitride layer on said third oxide layer, said conductive layer, and said first and second oxide layers, wherein said nitride layer conforms with said third oxide layer; removing said nitride layer to form a spacer at an edge of said third oxide layer; removing said third oxide layer to expose said spacer; etching said conductive layer such that a portion of said conductive layer underneath said spacer is exposed, wherein said portion of said conductive layer underneath said spacer resembles a matchstick; and removing said spacer to expose said matchstick-like conductive layer portion as a small contact.