Patent ID: 6414356
Filing Date: 2002-07-02
Classification: H01L

Abstract:
An inverter, comprising:a first transistor, the first transistor having a source region, a drain region, a pair of opposing sidewall surfaces, a first gate on a first one of the opposing sidewall surfaces, and a second gate on a second one of the opposing sidewall surfaces; a second transistor, the second transistor having a source region a drain region, a pair of opposing sidewall surfaces, a first gate on a first one of the opposing sidewall surfaces, and a second gate on a second one of the opposing sidewall surfaces, the source region of the second transistor being electrically connected to the drain region of the first transistor; a third transistor, the third transistor having a source region, a drain region, a pair of opposing sidewall surfaces, a first gate on a first one of the opposing sidewall surfaces, and a second gate on a second one of the opposing sidewall surfaces; a fourth transistor, the fourth transistor having a source region, a drain region, a pair of opposing sidewall surfaces, a first gate on a first one of the opposing sidewall surfaces, and a second gate on a second one of the opposing sidewall surfaces, the drain region of the fourth transistor being electrically connected to the source region of the third transistor; the first gate being coupled to the second gate for at least one of the first transistor and the fourth transistor; an electrical contact between the drain region of the second and third transistors to provide an output for the inverter; and a gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter.