Patent ID: 7416927
Filing Date: 2008-08-26
Classification: H01L

Abstract:
1. A method for producing a first fully depleted thin film SOI field effect transistor with predetermined transistor properties, comprising the steps of: forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an essentially undored body region having a thickness of less than 20 nm; forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence; and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions adjacent the essentially undored body region, which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into the essentially undoped body region between the two source/drain regions, wherein the predetermined transistor properties of the first fully depleted thin film SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile, wherein a second fully depleted thin film SOI field effect transistor is formed in accordance with the method for producing the first fully depleted thin film SOI field effect transistor on and/or in the essentially undoped body region, the predetermined transistor properties of the second fully depleted thin film SOI field effect transistor being set differently from those of the first fully depleted thin film SOI field effect transistor, wherein the difference in the transistor properties of the first fully depleted thin film SOI field effect transistor and the second fully depleted thin film SOI field effect transistor results solely from the different thicknesses of their spacer layers.