Patent ID: 6232160
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A method of suppressing short channel effect using a single self-aligning delta-channel implant in the fabrication of an integrated circuit device comprising:depositing a silicon nitride layer over a pad oxide layer overlying a semiconductor substrate;patterning said silicon nitride layer and said pad oxide layer to leave an opening where a gate electrode will be formed;forming dielectric spacers on the sidewalls of said opening wherein a portion of said semiconductor substrate not covered by said spacers within said opening corresponds to delta-channel implant width and wherein said width is between 100 and 300 Angstroms;implanting said single self-aligning delta-channel implant into said semiconductor substrate using said silicon nitride layer and said dielectric spacers as a mask;thereafter removing said dielectric spacers;thereafter forming a gate oxide within the opening;thereafter depositing a polysilicon layer over said silicon nitride layer and within said opening and polishing said polysilicon layer to leave said polysilicon layer only within said opening;removing said silicon nitride layer to form said gate electrode wherein said delta-channel implant underlies said gate electrode; andthereafter forming lightly doped regions and source and drain regions within said semiconductor substrate associated with said gate electrode to complete said fabrication of said integrated circuit device.