Patent ID: 9159812
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. An integrated circuit that includes one or more FinFET devices, a FinFET device comprising: a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface; a fin of semiconductor material extending upwards from the substrate through an opening in the dielectric layer, wherein a base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions, and wherein an upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface; a gate electrode straddling the upper channel region and being separated from the upper channel region by a gate dielectric; and first and second epitaxial source/drain regions that meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively, wherein the first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.