Patent ID: 6576553
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A method of forming a circuit element on a semiconductor wafer comprising:forming a dielectric layer on a semiconductor wafer; forming a shield layer on the dielectric layer; forming a sacrificial layer on the shield layer; forming a first cavity in the dielectric layer; depositing conductive material on the wafer so that the conductive material coats the exposed surfaces of the first cavity and so that the conductive material does not completely fill the cavity so as to define a second cavity within the first cavity and so that excess conductive material is positioned on the sacrificial layer; and removing the excess conductive material and the sacrificial layer by chemical mechanical polishing (CMP), wherein the chemical mechanical polishing is continued until the shield layer is reached, and wherein the shield layer inhibits thinning of the dielectric layer during the chemical mechanical polishing, and wherein interposing the sacrificial layer between the excess conductive material and the shield layer reduces the amount of conductive material on the shield layer following chemical mechanical polishing.