Patent ID: 7368778
Filing Date: 2008-05-06
Classification: H01L

Abstract:
1. A dynamic random access memory (DRAM), comprising: a device isolation layer formed in a semiconductor substrate, thereby defining an active region of the substrate; channel holes formed in the active region and surrounded by the device isolation layer; cell gate structures extending upward from the substrate and filling the channel holes; running gate structures formed on the device isolation layer in parallel with the cell gate structures; first impurity regions of first conductivity type formed in the substrate between the cell gate structures, and between the respective cell gate structures and the respective running gate structures, wherein a first impurity region formed between the respective gate structures has a width defined by a separation distance between the channel holes; a second impurity region of first conductivity type having the same width as the first impurity region formed between the cell gate structures and formed in the substrate under the first impurity region formed between the cell gate structures; and, a third impurity region of second conductivity type formed in the substrate under the second impurity region.