Patent ID: 6912012
Filing Date: 2005-06-28
Classification: H03L,H04N

Abstract:
1. A method of achieving lock in a phase-locked loop comprising: counting pixels of digital video data, testing for the occurrence of a sync pulse in the digital data and in connection with detecting a sync pulse, performing the following steps: further adjusting, by a fine amount, the increment value in connection with a phase error, whose computation is based on a demmer window weighting function applied to the sync pixels when the digital video data represents a video cassette recorder signal and a noise-free television signal; adjusting, by a fine amount, the increment value in connection with a phase error, whose computation is based on a flat window weighting function applied to the sync pixels when the digital video data represents a television signal having noise, adjusting by fine amount includes tuning a normalization constant to bring the falling edge of the sync pulse so as to be substantially centered within a flat window of a width corresponding to predetermined number of pixel clock cycles.