Patent ID: 7911003
Filing Date: 2011-03-22
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate, the MOS transistor including a source diffusion region and a drain diffusion region; a well formed in the semiconductor substrate; a back gate diffusion region defined in the vicinity of the source diffusion region or the drain diffusion region, the source diffusion region, the drain diffusion region and the back gate diffusion region being of the same conductivity type having the same impurity concentration and being formed in the same well, and the back gate diffusion region being electrically connected to the source diffusion region or the drain diffusion region via wiring; and a potential control layer, arranged in the semiconductor substrate or under the well, for controlling the potential at the semiconductor substrate or the well, wherein the back gate diffusion region is a dummy back gate diffusion region.