Patent ID: 8130230
Filing Date: 2012-03-06
Classification: G09G

Abstract:
1. A display device, including an image processing circuit that outputs data by making at least four times of read/write accessing to a storage circuit that stores input data, as well as corrected input data, wherein a read/write accessing time that includes a read access time with respect to the output data is within a one-line period inputted from an external CPU, wherein the data to be written to the storage circuit comprises current frame input data and current frame corrected data while the data to be read from the storage circuit comprises preceding frame input data and preceding frame corrected data, and wherein the read/write accesses to a bus of the storage circuit is made in the order of the preceding frame input data and the preceding frame corrected data on the first line and the current frame input data, the preceding frame corrected data, and the current frame corrected data on the second line.