Patent ID: 8885081
Filing Date: 2014-11-11
Classification: H03M,H04N

Abstract:
1. An analog-to-digital (AD) converter comprising: a reference signal generation unit that generates a reference signal that increases or decreases over time; a comparison unit that starts a comparison process of comparing an analog signal to the reference signal at a timing related to input of the analog signal to be subjected to A/D conversion and ends the comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signal; a ring delay circuit that includes a plurality of delay units and starts a transition process at a timing related to the start of the comparison process; a count unit that counts a clock from the ring delay circuit and retains a count value as a high-order logic state at a first timing related to the end of the comparison process; a low-order latch unit that latches a low-order logic state, which is a logic state of the plurality of delay units, at said first timing related to the end of the comparison process; and a calculation unit that calculates a digital signal related to the analog signal based on data of the low-order latch unit and the count unit, wherein the calculation unit rearranges the data of the low-order latch unit, which is output from the plurality of delay units, to signal groups rising in order at a given time interval or falling in order at a given time interval, and wherein the calculation unit detects a state transition position in the signal group at the first timing related to the end of the comparison process.