Patent ID: 7830184
Filing Date: 2010-11-09
Classification: G06F

Abstract:
1. A frequency multiplier comprising: a plurality of voltage regulators connected in parallel between first and second common nodes, each of the voltage regulators regulating levels of voltages at the first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line; an input buffer for charging the first common node or discharging the second common node in response to a feedback signal; an output buffer driven by the voltage level of any one of the first and second common nodes for regulating a level of a voltage at an output node and outputting a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node; a discharge circuit connected to the first common node for discharging the first common node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted; and a charge circuit connected to the second common node for charging the second common node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.