Patent ID: 6191975
Filing Date: 2001-02-20
Classification: G11C,H01L

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, whereineach of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer each of which is of substantially the same dimension as that of the memory cells, andwriting data into the first and second select gate cells is performed prior to writing data into the memory cells.