Patent ID: 6526471
Filing Date: 2003-02-25
Classification: G06F

Abstract:
A method of responding to a memory write request with a memory controller that controls synchronous dynamic random access memory (SDRAM), said method comprising the steps of:latching a memory write address for said memory write request from a processor into an address buffer of said memory controller while simultaneously determining if a memory row of said SDRAM encompassing said memory write address is active using logic in said memory controller, said SDRAM is directly connected to a processor bus; accepting data into a memory location of said SDRAM associated with said memory write address without delay when a memory row containing said memory location associated with said memory write address is active; and signaling from said memory controller to said processor that said memory controller is not ready to accept data when said memory row containing said memory location of said SDRAM associated with said, memory write address is not active.