Patent ID: 6175894
Filing Date: 2001-01-16
Classification: G11C

Abstract:
A command buffer for a memory device adapted to receive a command of N M-bit words on an M-bit bus, the command buffer comprising:M shift registers each having an input terminal, an output terminal, and a clock terminal, the input of each of the shift registers being coupled to a respective bit of the M-bit bus, each of the shift registers having N stages with a respective command bit applied to the input terminal being shifted from one stage to the next responsive to a clock signal adapted to be applied to the clock terminals of the shift registers;a control circuit having a start terminal, a clock terminal, and an output terminal, the control circuit generating a load signal responsive to a predetermined number of clock signals applied to the clock terminal after a start signal has been applied to the start terminal; anda storage register having N*M storage cells each of which has an output terminal, an input terminal coupled to the output of a respective shift register stage, and a load terminal coupled to the output terminal of the control circuit, each of the storage cells storing a signal at the output terminal of the respective shift register stage responsive to the load signal applied to the load terminal of the storage cell, the N*M storage cells collectively outputting a command word.