Patent ID: 7263678
Filing Date: 2007-08-28
Classification: G06F

Abstract:
1. A method comprising: (a) identifying a critical timing path in an integrated circuit layout pattern, which comprises floor-planned objects that are pre-placed in an initial floorplan for the layout pattern and which comprises non-floor-planned objects placed in the layout pattern relative to the floor-planned objects; (b) identifying a start point and one or more end points along the timing path; (c) determining whether any of the one or more end points are floor-planned objects; (d) for each end point that is a floor-planned object, comparing a distance between that end point and the start point with a distance threshold to produce a comparison result; and (e) generating an output that identifies at least one of the endpoints in step (d) for which the distance exceeds the distance threshold as being related to a potential floorplan problem.