Patent ID: 8504781
Filing Date: 2013-08-06
Classification: G06F

Abstract:
1. A method for sending and receiving data between a first processor including a first cache memory and a second processor including a second cache memory via a shared memory, the first and second cache memories having a plurality of cache lines having a fixed length, the method comprising: classifying, by the first processor, a transfer data area that stores data transferred between the first and second processors in the shared memory, as a first area filling a whole of one cache line in the first cache memory and a second area not filling one cache line in the first cache memory; copying, by the first processor, data in the second area into a divided data area in the shared memory, the divided data area being aligned with a cache line in the first cache memory; and processing, by the second processor, while treating data in the divided data area as data in the second area, data in the first area and data in the divided data area as data from the first processor.