Patent ID: 6243429
Filing Date: 2001-06-05
Classification: H04L

Abstract:
A data demodulator, comprising:a first decision circuit for demodulating a received signal to thereby output a first digital signal;a baseband circuit for converting the first digital signal to a baseband signal lying in a same frequency band as the received signal;a code processing signal generating circuit having a data rate which is substantially equal to one-half of a data rate of the received signal, for generating a code processing signal whose transition point is coincident with every two-bit transition point of the received signal;a first mixer for superposing the code processing signal on the baseband signal;a second mixer for superposing an output of said first mixer on the received signal input to said first decision circuit to thereby demodulate the received signal by spreading, whereby a noise component superposed on the received signal is spread;a filter having a pass band narrower than the frequency band of the received signal for separating a signal component corresponding to the code processing signal from an output of said second mixer;a second decision circuit for demodulating an output of said filter to thereby output a signal for bit error decision; anda correction circuit for comparing the code processing signal and the signal output from said second decision circuit to thereby locate a portion of the first digital signal where a bit error exists, and correcting the bit error to thereby output a second digital signal.