Patent ID: 6424005
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A low-side LDMOS device, comprising:a semiconductor layer of a first conductivity type; a second region of a second conductivity type opposite said first conductivity type formed as a well in said semiconductor layer; a third region having a first subregion of said first conductivity type and a second subregion of said second conductivity type, wherein said first subregion is deeper than said second subregion, and wherein said third region is formed as a well in said second region a source region of said second conductivity type formed in said second subregion of said third region; a drain region of said second conductivity type formed in said second region and spaced apart from said source region, such that a channel is formed between said source region and said drain region; a backgate region formed in said third region and adjacent said source region such that said source region separates said backgate region and said channel, said backgate region being of said first conductivity type; a gate oxide layer over said channel; and a gate over at least part of said source region and said channel; wherein said third region is sufficiently sized such that the edge of said second subregion is implanted under said gate and extends laterally past said source region.