Patent ID: 6341079
Filing Date: 2002-01-22
Classification: G11C

Abstract:
A content addressable memory device, comprising:a NAND-NOR chain comprised an alternating sequence of NAND and NOR stages; said NAND stages, each including a first CAM cell comprising a first memory cell that stores a first data bit and a first compare cell that compares the first data bit with a first compare bit and generates a first compare signal indicating whether the first data bit matches the first compare bit and a logical NAND gate that combines the first compare signals of other first CAM cells in said NAND stage; said NOR stages, each including a second CAM cell comprising a second memory cell that stores a second data bit and a second compare cell that compares the second data bit with a second compare bit and generates a second compare signal indicating whether the second data bit matches the second compare bit and a logical NOR gate that combines the second compare signals of other second CAM cells in said NOR stage; and said NAND-NOR chain generating a match signal indicating a match of all the compare bits to all the data bits in said content addressable memory device.