Patent ID: 6055651
Filing Date: 2000-04-25
Classification: G06F

Abstract:
An emulator comprising:a plurality of memory banks which selectively store signals present on a first bus of a system to be evaluated;a trace control unit having a trace condition setting circuit, in which a trace condition is set, and a trace condition agreement detecting circuit which generates data indicating whether or not signals on said first bus meet the trace condition; anda control circuit which controls accessing of the plurality of memory banks so as to store the signals on said first bus and the data from said trace condition agreement detecting circuit alternately and sequentially in the plurality of memory banks,wherein said control circuit includes an address generating circuit which generates addresses for accessing a memory bank in said plurality of memory banks, said address generating circuit generating different addresses when said trace condition agreement detecting circuit generates data indicating that signals on said first bus meet the trace condition stored in said trace condition setting circuit.