Patent ID: 6914838
Filing Date: 2005-07-05
Classification: G11C

Abstract:
1. A method of sensing a logical state of a memory cell comprising: presetting a count value of a counter to a preset count value; charging a capacitor with a charging current during a first plurality of time intervals, each time interval of said first plurality terminated when a periodic test of said capacitor indicates that a first voltage thereon exceeds a threshold voltage; discharging said capacitor with a discharging current during a second plurality of time intervals, each time interval of said second plurality terminated when a periodic test of said capacitor indicates that a second voltage thereon is below said threshold voltage; supplementing said charging and discharging currents with a further current, said further current extending a duration of one or more time intervals of said second plurality of time intervals to form a third plurality of extended time intervals, said further current related to a resistance value of a resistive element of a memory cell, said resistance value corresponding to a logical state of said memory cell; periodically incrementing said counter during said first plurality of time intervals and periodically decrementing said counter during both said second and third of pluralities of time intervals so as to effect a net change in said count value over time; and relating said net change in said count value over time to said logical state of said memory cell.