Patent ID: 9003096
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. An integrated circuit (IC) comprising: an input pin that is adapted to be coupled to a single-wire bus; an output pin that is adapted to be coupled to the single-wire bus; a bus interface that is coupled between the input pin and the output pin, wherein the bus interface has a transparent mode and an operational mode; and a plurality of interface circuitries which are coupled in series from an output of the bus bus interface in a return loop to an input of the bus interface, wherein the bus interface is configured to assign a bus address to a first interface circuitry of the plurality of interface circuitries, and a) increment the value of a received bus address, and then convey that incremented value to a next interface circuitry and assigns that value to the next interface series-coupled interface circuitry, b) wherein each of the serially-coupled individually assigned interfaces is configured to receive communications from the bus in both the transparent mode and the operational mode, wherein the transparent and configurations modes are determined by comparing a communication signal to the incremented values of the received address.