Patent ID: 7504294
Filing Date: 2009-03-17
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device, comprising: forming a first memory cell gate array including a plurality of memory cell gate electrodes, a first selection gate pair formed on opposite ends of the first memory cell gate array, a second memory cell gate array including a plurality of memory cell gate electrodes, and a second selection gate pair formed on opposite ends of the second memory cell gate array such that one gate of the second selection gate pair is disposed adjacent to one gate of the first selection gate pair, while forming a plurality of peripheral gates apart from the first memory cell gate array, the first selection gate pair, the second memory cell gate array, and the second selection gate pair on a semiconductor substrate; by using the first memory cell gate array, the first selection gate pair, the second memory cell gate array, the second selection gate pair, and the plurality of peripheral gates as masks, forming a plurality of diffusion regions in the semiconductor substrate; forming a first insulation film including a main component other than nitrogen over a whole surface of the semiconductor substrate, so as to fill between adjacent ones of the plurality of memory cell gate electrodes, between the opposite ends of the first memory cell gate array and the first selection gate pair, and between the opposite ends of the second memory cell gate array and the second selection gate pair and cover the plurality of memory cell gate electrodes such that the first insulation film plugs at least an upper end portion between the adjacent ones of the plurality of memory cell gate electrodes, and to form the first insulation film on a side surface of one gate of the first selection gate pair disposed adjacent to and opposite to that of one gate of the second selection gate pair, a first region of the semiconductor substrate between the opposite selection gates, side surfaces of the plurality of peripheral gates, and a second region of the semiconductor substrate disposed adjacent to the side surfaces of the peripheral gates; removing the first insulation film on the first region and the second region; forming a second insulation film including nitrogen as the main component over a whole exposed surface; forming an interlayer insulation film having a large etching selectivity to the second insulation film on the second insulation film; selectively etching the interlayer insulation film on the first region and the second region to expose some of the plurality of diffusion regions, leaving portions between adjacent ones of the plurality of memory cell gate electrodes filled with the first insulating film, and to form contact holes; and filling a conductive material in the contact holes to connect the conductive material to the selectively exposed some of the plurality of diffusion regions formed in the first region and the second region, wherein the first insulation film includes silicon oxide, the second insulation film includes nitride, and silicon nitride is not included between the adjacent ones of the plurality of memory cell gate electrodes, and the removing of the first insulating film includes removing the first insulating film formed on the sidewall of each of the opposite selection gates.