Patent ID: 7750701
Filing Date: 2010-07-06
Classification: H03L

Abstract:
1. A phase-locked loop (PLL) circuit, comprising: a digitally controlled oscillator (DCO) circuit to generate a DCO output signal in response to a digital frequency tuning control signal comprising an integer portion and a fractional portion; a dither control circuit that encodes the fractional portion of the digital frequency tuning control signal to generate a dither control signal; and a multiplexer circuit having a plurality of input ports each configured to receive a corresponding one of a plurality of analog control voltages within a fixed voltage range, an output port connected to a fractional frequency control port of the DCO, and a select control port that receives the dither control signal, wherein the multiplexer circuit selectively outputs one of the analog control voltages to the fractional frequency control port of the DCO in response to the dither control signal to drive a fractional frequency tuning element of the DCO using the analog control voltage.