Patent ID: 6356480
Filing Date: 2002-03-12
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device formed on a semiconductor substrate, comprising:an internal power supply circuit receiving an external power supply potential and generating an internal power supply potential; a control circuit controlling an operation of said nonvolatile semiconductor memory device in response to a command signal; a memory cell array having a plurality of floating-gate memory cell transistors arranged in rows and columns, divided into a plurality of memory cell blocks forming units subjected to an erase operation by repeating collective application of an erase pulse to said memory cell transistors and an erase verify operation respectively; a reference potential generation circuit for generating a reference potential for threshold determination of said memory cell transistors; a cell potential supply circuit selecting any said memory cell transistor for selectively supplying said reference potential to said selected memory cell transistor in said erase verify operation and selectively supplying said internal power supply potential to selected said memory cell transistor in a write-back operation performed after completion of said erase verify operation respectively; and a sense amplifier part including a plurality of sense amplifiers for reading data from selected said memory cell transistor and performing threshold determination on the basis of the value of a current flowing through said selected memory cell transistor in said write-back operation, wherein current sensitivity of said sense amplifiers in said threshold determination is so set that the sum of leakage currents in off states of a plurality of said memory cell transistors collectively subjected to said write-back operation is within the range of current drivability of said internal power supply circuit after completion of said erase verify operation.