Patent ID: 7567466
Filing Date: 2009-07-28
Classification: G11C,Y10T

Abstract:
1. A non-volatile memory, comprising: a memory array of non-volatile storage units partitioned into an user array portion and a redundant array portion, the redundant array portion having redundant locations for storing data slated for any defective location in the user array portion as relocated data; a group of access circuits including a first group of data latches for latching data of the user array portion and a second group of data latches for latching data of the redundant array portion; a data bus; a defect map buffer for buffering addresses of defective locations of the user array portion; a redundant data buffer for buffering relocated data from the data latches of the redundant array portion; and redundant data buffer control circuits responsive to a current address of the user array portion that does not correspond to any address of defective locations in the defect map buffer to enable exchange of data between said data bus and said user portion data latches and, responsive to a current address of the user array portion that corresponds to an address of a defective location in said defect map buffer to enable exchange of relocated data of the defective location between said data bus and said redundant data buffer.