Patent ID: 7375710
Filing Date: 2008-05-20
Classification: G09G

Abstract:
1. An image display apparatus, comprising: a pixel array including a plurality of pixel display circuits arranged in a plurality of rows and a plurality of columns and each displaying a pixel in response to a gradation potential, a plurality of gate lines provided corresponding to said plurality of rows, respectively, and a plurality of data lines provided corresponding to said plurality of columns, respectively; a vertical scanning circuit sequentially selecting said plurality of gate lines for a prescribed time period and activating each pixel display circuit corresponding to the selected gate line; a gradation potential generating circuit outputting a plurality of gradation potentials different from each other; and a decode circuit provided corresponding to each data line and selecting one of said plurality of gradation potentials in response to an image data signal to apply the selected gradation potential to the activated pixel display circuit via a corresponding data line while one gate line is selected by said vertical scanning circuit; said gradation potential generating circuit including; a first ladder resistor circuit having a relatively high resistance value and generating said plurality of gradation potentials by dividing a power supply voltage to apply the generated plurality of gradation potentials to a plurality of first nodes, respectively, a second ladder resistor circuit having a relatively low resistance value, activated during an initial predetermined period of a time period during which the gradation potential selected by said decode circuit is applied to the corresponding data line, and generating said plurality of gradation potentials by dividing said power supply voltage, and a switching circuit applying said plurality of gradation potentials generated by said second ladder resistor circuit for said predetermined period to said plurality of first nodes, respectively; the first ladder resistor circuit including first resistors connected together in series and the second ladder resistor circuit including second resistors connected together in series; and said switching circuit including a plurality of switches disposed between respective ones of the first and second resistors.