Patent ID: 7924645
Filing Date: 2011-04-12
Classification: G11C

Abstract:
1. A refreshing method suitable for a memory device comprising a sense amplifier, a first memory cell array and a second memory cell array, the sense amplifier comprising a sense line pair and adapted to amplify signals from a first bit line pair of the first memory cell array and signals from a second bit line pair of the second memory cell array, the refreshing method comprising: setting a sleep mode in which the memory device cannot be read and programmed; and sequentially auto-refreshing the first and the second memory cell arrays during the sleep mode, wherein the step of auto-refreshing each of the first memory cell array and the second memory cell array comprises: during an equalization period, switching a potential of the sense line pair, the first bit line pair and the second bit line pair to a reference voltage wherein the sense line pair and the second bit line pair are not electrically coupled to each other, wherein the step of switching the potential of the sense line pair, the first bit line pair and the second bit line pair to the reference voltage during the equalization period comprises: providing a first and a second equalized control signals to control a conducting state between two bit lines of the first bit line pair and a conducting state between two bit lines of the second bit line pair, respectively; providing a first and a second sense control signals to control a conducting state between the sense line pair and the first bit line pair and a conducting state between the sense line pair and the second bit line pair, respectively; maintaining the level of the first and the second equalized control signals at a first voltage such that the two bit lines of each of the first and the second bit line pairs are conducted to each other and have a potential equal to the reference voltage; maintaining the level of the first sense control signal at the first voltage such that the sense line pair is electrically coupled to the first bit line pair; and switching the level of the second sense control signal to a second voltage such that the sense line pair is not electrically coupled to the second bit line pair; and during a refreshing period, adjusting the potential of the first and the second bit line pairs according to a refresh sequence of the first and the second memory cell arrays, thereby electrically coupling the sense line pair to at least one of the first and the second bit line pairs, wherein the step of in auto-refreshing the second memory cell array, electrically coupling the sense line pair to at least one of the first and the second bit line pairs comprises: switching the level of the first sense control signal to the second voltage such that the sense line pair and the first bit line pair are not electrically coupled to each other; and stepwisely increasing the level of the second sense control signal such that the sense amplifier amplifies the signals from the second bit line pair, wherein the step of stepwisely increasing the level of the second sense control signal comprises: switching the level of the second sense control signal from the second voltage to the first voltage; and switching the level of the second sense control signal from the first voltage to a third voltage wherein the third voltage is higher than the first voltage and the first voltage is higher than the second voltage.