Patent ID: 7787303
Filing Date: 2010-08-31
Classification: G11C

Abstract:
1. A method, comprising: setting a complementary pair of non-volatile trapped-charge memory devices, comprising a P-type SONOS-type memory device having first gate, drain and source terminals and a N-type SONOS-type memory device having second gate, drain and source terminals, to one of a first logic state and a second logic state with a common voltage to control the complementary pair, the complementary pair being set to the first logic state by programming the P-type SONOS-type device with the common voltage and erasing the N-type SONOS-type device with the common voltage and the complementary pair being set to the second logic state by erasing the P-type SONOS-type device with the common voltage and programming the N-type SONOS-type device with the common voltage; coupling the first source terminal to a first logic level voltage and the second source terminal to a second logic level voltage; and reading the logic state of the complementary pair without disturbing the logic state by: