Patent ID: 8134412
Filing Date: 2012-03-13
Classification: G06F,H03K

Abstract:
1. A method of producing an output clock signal for transmission to a device, the method comprising: generating, using an oscillating circuit, a first internal clock signal having a first frequency that is 2 generating, using the oscillating circuit, a second internal clock signal based on the first internal clock signal, wherein the second internal clock signal has a second frequency that is substantially the same as the input frequency; generating, using the oscillating circuit, a first output clock signal based on the second internal clock signal by applying a first time delay to the second internal clock signal such that the first output clock signal is aligned in phase with the input clock signal, wherein the first time delay is based on a phase difference between the input clock signal and the second internal clock signal; and generating, using the oscillating circuit, a second output clock signal configured to be provided to the oscillating circuit as feedback, wherein: