Patent ID: 8495122
Filing Date: 2013-07-23
Classification: H03K

Abstract:
1. An integrated circuit comprising: a plurality of configurable blocks; configurable interconnect resources programmably interconnecting the plurality of configurable blocks; a dedicated signal line that is non-programmable; a plurality of configurable digital signal processing (DSP) elements each having an adder/subtractor circuit, the plurality of DSP elements including a first DSP element and a second DSP element, the second DSP element including: wherein the multiplexing circuitry connects at least one of the feedback port and the cascade input port to the multiplexing-circuitry output port in response to the mode control signals, and wherein the multiplexing circuitry comprises a first multiplexer which enables the coupling of either the product generator port or the feedback port to a first addend port of the adder/subtractor circuit and a second multiplexer which enables the coupling of either the feedback port and the cascade input port to a second addend port of the adder/subtractor circuit, and wherein data output by the adder/subtractor circuit and stored in the register may be coupled to the first addend port of the adder/subtractor circuit and the second addend port of the adder/subtractor circuit.