Patent ID: 7239205
Filing Date: 2007-07-03
Classification: H03F,H03G,H04B

Abstract:
1. A high frequency amplifier circuit comprising: a signal input terminal and a signal output terminal; a first variable resistor circuit connecting said signal input terminal to said signal output terminal; a second variable resistor circuit connected in parallel to said signal input terminal and a first ground terminal; a third variable resistor circuit connected in parallel to said signal output terminal and a second ground terminal; a control terminal connected respectively to said first, second, and third variable resistor circuits; a first reference voltage terminal connected to said first variable resistor circuit; and a second reference voltage terminal connected to said second and third variable resistor circuits; wherein: said first variable resistor circuit comprises a first field effect transistor; said control terminal is connected through at least one or more first resistors to the gate terminal of said first field effect transistor; said first reference voltage terminal is connected through at least one or more second resistors to the source terminal or the drain terminal of said first field effect transistor; a third resistor is connected between the source terminal and the drain terminal of said first field effect transistor; said second variable resistor circuit comprises a second field effect transistor; said control terminal is connected through at least one or more fourth resistors to the source terminal or the drain terminal of said second field effect transistor; said second reference voltage terminal is connected through at least one or more fifth resistors to the gate terminal of said second field effect transistor; a sixth resistor is connected between the source terminal and the drain terminal of said second field effect transistor; seventh resistors are connected at least at one of a position between said signal input terminal and the source terminal or the drain terminal of said second field effect transistor and a position between said first ground terminal and the drain terminal or the source terminal of said second field effect transistor; said third variable resistor circuit comprises a third field effect transistor; said control terminal is connected through at least one or more eighth resistors to the source terminal or the drain terminal of said third field effect transistor; said second reference voltage terminal is connected through at least one or more ninth resistors to the gate terminal of said third field effect transistor; a tenth resistor is connected between the source terminal and the drain terminal of said third field effect transistor; eleventh resistors are connected at least at one of a position between said signal output terminal and the source terminal or the drain terminal of said third field effect transistor and a position between said second ground terminal and the drain terminal or the source terminal of said third field effect transistor; the resistance value of said third resistor connected between the source terminal and the drain terminal of said first field effect transistor is lower than the off resistance value between the source terminal and the drain terminal of said first field effect transistor; the sum of the resistance values of said seventh resistors connected at least at one of a position between said signal input terminal and the source terminal or the drain terminal of said second field effect transistor and a position between said first ground terminal and the drain terminal or the source terminal of said second field effect transistor is higher than the on resistance value between the source terminal and the drain terminal of said second field effect transistor; the sum of the resistance values of said eleventh resistors connected at least at one of a position between said signal output terminal and the source terminal or the drain terminal of said third field effect transistor and a position between said second ground terminal and the drain terminal or the source terminal of said third field effect transistor is higher than the on resistance value between the source terminal or the drain terminal of said third field effect transistor; the DC resistance between said signal input terminal and said signal output terminal is infinity; the DC resistance between said signal input terminal and said first ground terminal is infinity; the DC resistance between said signal output terminal and said second ground terminal is infinity; and on the basis of the relation between the voltage of said control terminal, the voltage of said first reference voltage terminal, and the voltage of said second reference voltage terminal, the resistance values of said first, second, and third variable resistor circuits are adjusted continuously, so that the signal level on said signal output terminal is continuously adjusted relative to the signal level inputted to said signal input terminal.