Patent ID: 7345362
Filing Date: 2008-03-18
Classification: H01L,H03H

Abstract:
1. An electronic component configured for mounting a chip comprising: a package having an inner wall formed circumferentially around the package with a stepped level-difference in the inner wall, the stepped level-difference including upper and lower portions; a plurality of internal contact electrodes provided on an upper end-surface of said stepped level-difference in the inner wall; a shield electrode provided on an inner bottom surface of said package at a side facing said stepped level-difference; a non-electrode portion defined to be adjacent to the shield electrode where the shield electrode is not formed and the non-electrode portion being provided on a part of the inner bottom surface of said package; and an interconnection wire for connecting said chip and a respective internal contact electrode of the plurality of internal contact electrodes; wherein the lower portion of the stepped level-difference and the inner bottom surface form a cavity with an aperture such that a clearance between opposing sides of the lower portion of the stepped level-difference is greater at the inner bottom surface than at the aperture of the cavity.