Patent ID: 8008771
Filing Date: 2011-08-30
Classification: H01L,H05K,Y02P

Abstract:
1. A semiconductor chip package comprising: a semiconductor chip including a first surface having a plurality of bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; a plurality of redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; a plurality of bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls, wherein the molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other, and wherein the molding layer has a thermal expansion coefficient below 50 ppm/° C., in a temperature range below a glass transition temperature.