Patent ID: 7814266
Filing Date: 2010-10-12
Classification: G11C,H04L

Abstract:
1. A content addressable memory (“CAM”) array, comprising: first CAM cells coupled to compare stored CAM entries to a first portion of a key entry and not a second portion of the key entry; second CAM cells coupled to compare stored CAM entries to the second portion of the key entry and not the first portion of the key entry; first logic circuitry, coupled to logically combine multiple first comparison results from first CAM cells, that activates a first match result in response to any one of the CAM entries corresponding to the first CAM cells matching the first portion of the key entry; and second logic circuitry, coupled to logically combine a second comparison result from one of the second CAM cells with the first match result, that activates a match signal in response to the CAM entry of the one second CAM cell matching the second portion of the key entry and the first match result being activated.