Patent ID: 8849644
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. A method for simulating a circuit design, the method comprising: receiving a partition of a plurality of partitions of the circuit design at a kernel in a plurality of kernels that simulate partitions of the circuit design in parallel, the kernels being configured to perform parallel simulation of the circuit design on one or more computing systems; determining a plurality of events in a delta cycle of the parallel simulation to simulate based on the partition, the plurality of events classified in a plurality of event regions that have an ordered priority assigned; determining a first event region of the plurality of event regions to process events based on priorities assigned to the event regions; processing one or more events in the first event region using the kernel and an object shared with at least one other kernel of the plurality of kernels, wherein the plurality of kernels process the events in the first event region; with a data synchronization point determiner, determining one or more data synchronization points at the end of one or more but not all of the plurality of event regions; and synchronizing data with the at least one other kernel of the plurality of kernels at one or more of the data synchronization points, wherein: