Patent ID: 6566267
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A process for producing a multiplicity of semiconductor wafers, comprising the following individual steps:(a) simultaneously polishing a front side of each semiconductor wafer and a back side of each semiconductor wafer between rotating polishing plates with a polishing fluid being supplied to said polishing plates, the semiconductor wafer in each case resting in a cutout of a carrier and being kept on a specific geometric path, the carrier having a carrier thickness t1L, and the semiconductor wafers having a starting thickness t0 prior to polishing and a final thickness t1 after the polishing, the thickness difference t0âˆ’t1L being 15 &mgr;m to 100 &mgr;m, and the thickness difference t1âˆ’t1L being 2 &mgr;m to 20 &mgr;m; (b) assessing each semiconductor wafer in a quality inspection with regard to quality features which are stipulated for further processing; (c) further simultaneously polishing a front side and a back side of each of those semiconductor wafers which, according to said quality inspection (b), do not satisfy the stipulated quality features, these semiconductor wafers resting in a carrier during polishing and having the starting thickness t1 prior to polishing and a final thickness t2 after polishing, and the carrier having a thickness t2L and the thickness difference t1âˆ’t2L being 5 &mgr;m to 30 &mgr;m, and the thickness difference t2âˆ’t2L being 2 &mgr;m to 10 &mgr;m; and (d) further assessing each of those semiconductor wafers which were fed to step (c) with regard to quality features stipulated for further processing.