Patent ID: 6178490
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A device for incremental reading of a memory of a central processing unit of a microcomputer with which there are associated circuits for addressing of memory cells of said memory, comprising an address register, and circuits for the reading of signals read in the memory cells of said memory selected by said addressing circuits, comprising at least a first register called a read register in which the signals read are recorded in binary form, wherein said device comprises:incrementation means for increasing contents of the address register by at least one unit so that memory cells are addressed corresponding to an address that follows a memory cell previously read, andstorage means for recording the contents of the first read register so that it can record the signals read in the memory cells corresponding to the next address,wherein the incrementation means include a sequencing circuit that is controlled by signals from the central processing unit and that provides an increment signal for incrementation of the address register,wherein the storage means include a second register called a data register, and an electronic transfer circuit between the read register and the data register that is controlled by a control signal provided by the incrementation means.