Patent ID: 8811066
Filing Date: 2014-08-19
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a first line; a second line; a third line; a fourth line; and a memory cell comprising: wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the capacitor, wherein a gate of the first transistor is electrically connected to the first line, wherein one of a source and a drain of the second transistor is electrically connected to the third line, wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line, wherein the other of electrodes of the capacitor is electrically connected to the second line, wherein the first transistor comprises a semiconductor layer including an oxide semiconductor, wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor, wherein the semiconductor device is configured to write a plurality of stages of data to the memory cell, wherein the semiconductor device is configured to read the plurality of stages of data from the memory cell, and wherein the plurality of stages of data is larger than or equal to three stages of data.