Patent ID: 7154317
Filing Date: 2006-12-26
Classification: G01R,H03K

Abstract:
1. A latch circuit having a data signal input, a scan signal input, a clock signal input, a reset signal input, a scan enable signal input and a data signal output, said latch circuit comprising: a functional path latch having an active mode in which said functional path latch is operable in response to a clock signal received at said clock signal input to store a data signal value received at said data signal input and to output said data signal value at said data signal output and an inactive mode in which said functional path latch is not able to store said data signal value; and a data retention latch for saving said data signal value from said functional path latch when said functional path latch enters said inactive mode and for restoring said data signal value to said functional path latch when said functional path latch enters said active mode; wherein a reset signal received at said reset signal input and a scan enable signal received at said scan enable signal input, for controlling said functional path latch and said data retention latch: (i) to reset at least said functional path latch; (ii) to restore a data signal value stored in said data retention latch to said functional path latch; (iii) to select a scan signal input value received at said scan signal input for storage in at least one of said functional path latch and said data retention latch; and (iv) to save a data signal value from said functional path latch to said data retention latch.