Patent ID: 9042505
Filing Date: 2015-05-26
Classification: G06F,H04L

Abstract:
1. A data transmission apparatus disposed within two network layers which are operative at different data rates, the data transmission apparatus coupled to a clock generator which provides a reference clock for a lower network layer and coupled to a frequency synthesizer with an integer division factor that generates a divided clock for a upper network layer according to the reference clock and the integer division factor, and the data transmission apparatus comprises: a first processing circuit corresponding to the upper network layer, coupled to the frequency synthesizer, for receiving and transmitting data by using the divided clock as an operation frequency of the first processing circuit; and a second processing circuit corresponding to the lower network layer, coupled to the clock generator and the first processing circuit, for receiving and transmitting data from the first processing circuit by using the reference clock as an operation frequency for encoding data within the second processing circuit; wherein the divided clock is generated from the frequency synthesizer with the integer division factor, and a frequency of the divided clock is higher than a data rate at which the upper network layer is operative; the first processing circuit is arranged to adjust a rate of data outputted by the first processing circuit according to a signal notified by the second processing circuit, to avoid data overflow or underflow.