Patent ID: 7556973
Filing Date: 2009-07-07
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising: examining each of a plurality of semiconductor elements on a semiconductor wafer by an on-wafer test, storing a result of the on-wafer test and coordinate position data of the each of the semiconductor elements on the semiconductor wafer, the result of the on-wafer test and the coordinate position data being associated with each other, dicing the semiconductor wafer into individual pieces of the semiconductor elements, incorporating each of the individual pieces of the semiconductor elements into a package, associating data of a mark on the package with the coordinate position data with respect to each of the semiconductor elements, conducting a final test of each of the semiconductor elements in the package for at least one first test item, and obtaining a result of the on-wafer test with respect to the each of the semiconductor elements in the package by referring to the association data based on the mark of the package for at least one of a second test item.