Patent ID: 8854858
Filing Date: 2014-10-07
Classification: G11C,H03K

Abstract:
1. A system on chip (SoC) comprising: one or more core logic blocks that are configured to operate on a lower supply voltage; a memory array configured to operate on a higher supply voltage, wherein the memory array comprises: n rows by m columns of bit cells; m bit lines each coupled to a corresponding one of the m columns of bit cells; m write drivers each coupled to a corresponding one of the m bit lines, wherein the m write drivers are configured to operate on the lower supply voltage; and wherein each bit cell comprises: two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors; a sense amp coupled to the node Q, wherein the sense amp is configured to operate on the higher supply voltage; and a transfer gate coupled between the node Q and one of the m bit lines; and wherein the memory array further comprises a controller, wherein the controller is operable to perform a write cycle to a selected bit cell by: