Patent ID: 7099278
Filing Date: 2006-08-29
Classification: H04L

Abstract:
1. A circuit for performing a line loop back test, the circuit comprising: a receiver that receives an input signal from a receiver communication line; a deserializer coupled to the receiver that converts high speed serial receiver data derived from an input signal received by the receiver into low speed parallel data, wherein the deserializer further produces a low speed clock output signal; a low speed parallel loop back data multiplexer coupled to the deserializer that selects either the low speed parallel data from the deserializer or low speed parallel input data; a serializer coupled to the low speed parallel loop back data multiplexer that converts low speed parallel output data from the low speed parallel loop back data multiplexer into high speed serial transmitter data; a transmitter coupled to the serializer that converts the high speed serial transmitter data into an output signal for transmission across a transmitter communication line; and a low speed loop back reference clock multiplexer coupled to the deserializer that selects either the low speed clock output signal from the deserializer or a reference clock input signal.