Patent ID: 6054881
Filing Date: 2000-04-25
Classification: H04L

Abstract:
An input/output (I/O) buffer circuit, comprising:a first output driver stage operably coupled to an input/output node and configured to drive the input/output node, wherein the first output driver is enabled when resistive termination of a transmission line connected to the input/output node is not required;a second output driver stage operably coupled to the input/output node and configured to drive the input/output node with an electrical resistance substantially equal to a characteristic impedance of the transmission line, wherein the second output driver stage is enabled when resistive termination of the transmission line is required;an input termination stage operably coupled to the input/output node and configured to:(i) provide resistive termination of the transmission line for a period of time following a transition of an input signal, and (ii) reinforce said input signal following said period of time such that electrical power dissipation within the I/O buffer circuit is reduced; andwherein said period of time is substantially equal to the amount of time it takes the input signal to propagate the length of the transmission line.