Patent ID: 6713342
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of forming an FeRAM integrated circuit, comprising:forming a transistor in a semiconductor substrate; forming an interlayer dielectric layer over the transistor; forming a conductive contact in the dielectric layer down to a portion of the transistor; forming a bottom electrode diffusion barrier layer over the interlayer dielectric layer; forming a bottom electrode layer, a ferroelectric dielectric layer, a top electrode layer, and a hard mask over the bottom electrode diffusion barrier layer; patterning the hard mask layer; selectively etching the top electrode layer, the ferroelectric dielectric layer, and the bottom electrode layer using the hard mask to define a capacitor stack, and exposing a portion of the bottom electrode diffusion barrier layer not covered by the capacitor stack; forming a sidewall diffusion barrier layer over the capacitor stack and sidewalls associated therewith, and over the exposed portion of the bottom electrode diffusion barrier layer; etching the sidewall diffusion barrier layer, thereby removing substantially all of the sidewall diffusion barrier layer over the capacitor stack and the exposed portion of the bottom electrode diffusion barrier layer while leaving at least a portion of the sidewall diffusion barrier layer over the sidewalls of the capacitor stack; and etching the exposed portion of the bottom electrode diffusion barrier layer.