Patent ID: 7742506
Filing Date: 2010-06-22
Classification: H04J

Abstract:
1. A buffer circuit for use in a digital communication system, the buffer circuit comprising: a memory configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system; and a controller coupled to the memory, the controller being operative: (i) to store data from the first data stream into corresponding timeslots in the memory in a first order; (ii) to individually adjust delays of the timeslots in the memory as a function of respective delay control parameters; and (iii) to generate a second data stream by reading the timeslots stored in the memory in a second order; wherein at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the delay control parameters corresponding to the timeslots; and wherein the delay control parameters are functions of one or more characteristics of the respective channels in the digital communication system, such that the at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the one or more characteristics of the respective channels.