Patent ID: 6272601
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A memory subsystem comprising:a load miss block adapted for queuing a load operation issued by a first processor that misses in an L1 cache of the first processor;a store miss block adapted for queuing operations;an arbiter configured to receive queued operations from the load and store miss blocks and further configured to select and initiate one of the received operations; andmeans for forwarding the address associated with the load miss operation to a lower level cache and means for receiving a response from lower level cache, wherein the load miss block is adapted to detect the response from lower level cache and request a bus interface unit to fetch data via a system bus if the lower level cache responds with a miss; andwherein the bus interface unit is configured to signal the load miss block when a first portion of the fetched data is available and further wherein, responsive to the data available signal, the load miss unit is configured to initiate a forwarding operation to satisfy the load operation if the forwarding operation can be initiated without displacing a valid second load miss operation.