Patent ID: 9184948
Filing Date: 2015-11-10
Classification: H04L

Abstract:
1. A Decision Feedback Equalizer (‘DFE’), the DFE comprising: a plurality of summing amplifiers; a plurality of input signal lines comprising a plurality of data signal lines (DSL) and a plurality of power control signal lines (PCSL); at least one output signal line; and a plurality of independently-controlled isolated power domains (ICIPD), wherein a summing amplifier in each ICIPD is coupled to a corresponding one of the PCSL and also coupled to a corresponding one of the DSL, each of the PCSL configured to transmit a power control signal to the ICIPD, wherein each ICIPD selectively consumes power in response to the power control signal, each ICIPD configured to be dynamically powered up or powered down without impacting signal processing operations, wherein a second ICIPD from the plurality of ICIPD is powered up by receiving a positive power control signal and consumes power only when the second ICIPD is powered up, then the second ICIPD receives a negative active input signal indicating that the second ICIPD cannot operate as an active data path and the second ICIPD is not required to process incoming data signals from the respective DSL; then a third ICIPD from the plurality of ICIPD is powered up to operate as an edge path for performing clock alignment operations within the DFE and cannot be powered down so long as it serves as the edge path; then a fourth ICIPD is powered up after receiving the positive power control signal for serving as a calibration path for the DFE and is powered down only when the calibration has finished; then the fourth ICIPD receives a negative power control signal indicating that the fourth ICIPD should powered down by turning off power supplies that provide power to computing components within the fourth ICIPD only when an input clock signal is steady.