Patent ID: 6253306
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A method of operating a processor in response to a prefetch instruction, said method comprising:decoding the prefetch instruction;in response to the decoding,installing a fault handler that ignores at least virtual memory exceptions; andissuing a non-blocking load operation with a register target selected to ensure that no data dependency relation exists between the non-blocking load operation and any other instruction; andexecuting the non-blocking load operation,wherein the prefetch instruction is defined to be non-faulting, non-blocking and non-modifying of architectural register state; andwherein the method allows implementation of the prefetch instruction in a superscalar processor substantially without specialized architectural support therefor except for supply of a completion indication for the non-blocking load operation upon a corresponding cache hit or, in the case of a cache miss, upon posting of a corresponding cache fill request.