Patent ID: 6191603
Filing Date: 2001-02-20
Classification: G01R

Abstract:
An integrated circuit having an embedded testing system, said integrated circuit having a plurality of chip input terminals and a plurality of chip output terminals, said integrated circuit operating in a test mode and a normal mode, said integrated circuit further comprising a plurality of core modules and a test data bus,said test data bus having first and second conductors, said first conductor being accessible from one of said chip input terminals and said second conductor being accessible from one of said chip output conductors, andeach core module comprising:an access register for storing an access word;a plurality of registers connected together as a first scan-chain having an input terminal for receiving data to be shifted into said registers and an output terminal for reading data shifted out of said registers;a scan-in enable circuit for connecting said input terminal of said first scan-chain to said first conductor of said test data bus in response to said access word having a first value; anda scan-out enable circuit for connecting said output terminal of said first scan-chain to an output conductor of said test data bus,wherein said access registers of said core modules are connected together to form an access scan-chain, said access scan-chain having an input terminal accessible from one of said chip input terminals, and wherein one of said core modules has one of said output terminals connected to said second conductor of said test data bus.