Patent ID: 6586682
Filing Date: 2003-07-01
Classification: H05K

Abstract:
A printed wiring substrate comprising:a laminated printed wiring substrate having a patterned metal layer on a surface of the laminated printed wiring substrate, the patterned metal layer including a first pad; a planarized dielectric layer disposed on the surface of the laminated printed wiring substrate and covering at least a portion of the first pad of the patterned metal layer, the planarized dielectric layer comprising a first dielectric layer portion proximate to the laminated printed wiring substrate, and a second dielectric layer portion disposed on the first dielectric layer portion; a first via extending from an upper surface of the second dielectic layer portion of the planarized dielectric layer to the first pad; a patterned thin-film metal layer formed on the planarized layer, a second pad of the patterned thin-film metal layer being electrically coupled to the first pad through the first via; a third pad of the patterned thin-film metal layer, the third pad and the second pad being arranged with a pitch; and a reference plane portion of the patterned thin-film metal layer, the reference plane portion disposed between the second pad and the third pad.