Patent ID: 7561205
Filing Date: 2009-07-14
Classification: H03L,H04N

Abstract:
1. An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL), the apparatus comprising: an input device for inputting a frequency expectation; a pixel clock generator for generating an actual pixel clock having an actual frequency according to the frequency expectation; a division frequency counter for dividing the actual pixel clock into several pixel clocks having different frequency ranges by means of multiplying the actual frequency of the actual pixel clock by a multiplier; a reference frequency counter for dividing the actual pixel clock by means of lowering the actual frequency of the actual pixel clock, and for generating a reference frequency; a reactive frequency counter for dividing the actual pixel clock by means of heightening the actual frequency of the actual pixel clock, and for generating a reactive frequency; a micro-programmed control unit (MCU) for executing corresponding instructions to control the division frequency counter, the reference frequency counter and the reactive frequency counter, and generating respective values sent to the counters for computing the reference frequency and the reactive frequency; and a PLL circuit for integrating the reference frequency and the reactive frequency to generate a required pixel clock having a required frequency.