Patent ID: 8895394
Filing Date: 2014-11-25
Classification: H01L

Abstract:
1. A method for fabricating a vertical field effect transistor, comprising: forming a recessed conductive gate electrode structure in a trench opening of a semiconductor substrate structure, the recessed conductive gate structure having a top surface which is below an elevated surface region of the semiconductor substrate structure; forming an implant block layer over the recessed conductive gate electrode structure in the trench opening by depositing an oxide layer to fill the portion of the trench opening above the recessed conductive gate electrode structure and planarizing the oxide layer to form an oxide implant block layer over the recessed conductive gate electrode structure in the trench opening; implanting dopants of a first conductivity type using one or more angled implants into an upper region of an elevated substrate and trench sidewalls located above the recessed conductive gate electrode structure to form surface implant regions and self-aligned source regions adjacent to the recessed conductive gate electrode structure; implanting dopants of a second opposite conductivity type into the semiconductor substrate structure to form self-aligned body contact regions adjacent to the self-aligned source regions; applying a recess etch to the elevated surface region of the semiconductor substrate structure to remove the surface implant region while retaining the self-aligned source regions adjacent to the recessed conductive gate electrode structure and the self-aligned body contact regions adjacent to the self-aligned source regions; and applying a recess etch to the implant block layer after applying the recess etch to the elevated surface region of the semiconductor substrate structure, thereby forming a recessed implant block layer that is substantially coplanar with the self-aligned body contact regions and self-aligned source regions.