Patent ID: 7185182
Filing Date: 2007-02-27
Classification: G06F

Abstract:
1. An apparatus for improving performance in a pipeline microprocessor having an architected register file, the apparatus comprising: early execution logic, configured to generate early results of instructions prior to generation of final results of said instructions by one or more execution units lower in the microprocessor pipeline than said early execution logic; an early register file, coupled to said early execution logic, comprising registers corresponding to the architected register file for storing said early results, having a valid indicator associated with each of said registers, configured to provide said early results to said early execution logic as operands for generating subsequent said early results; and logic, coupled to receive said valid indicators, configured to stall the pipeline if said early execution logic is generating an address using an operand stored in one of said early register file registers and said valid indicators indicate that said register is invalid, wherein said logic is further configured not to stall the pipeline if said early execution logic is generating a non-memory address early result using an operand stored in one of said early register file registers and said valid indicators indicate that said register is invalid.