Patent ID: 6495399
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method of fabricating a packaged semiconductor chip device, comprising the steps of:providing a semiconductor substrate; forming semiconductor devices on said semiconductor substrate; forming a dielectric layer over said semiconductor substrate; forming at least one layer of interconnects over said semiconductor devices and within said dielectric layer so that at least a portion of said interconnects are separated by voids; forming a passivation layer over the uppermost of said at least one layer of interconnects to form a semiconductor chip; affixing said semiconductor chip to a support structure within an enclosed package frame having gases therein; withdrawing said gases from said enclosed package frame creating a vacuum within said voids of said chip interconnects; and sealing said enclosed package frame to create a semiconductor chip device package while maintaining said vacuum within said voids; wherein said semiconductor chip is vacuum sealed within said semiconductor chip device package and is electrically connected to lead frames extending from said semiconductor chip device package.