Patent ID: 8697511
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method for producing a semiconductor device, comprising: a first step of forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer so that a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer; a second step of implanting an impurity to an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer to form diffusion layers, the second step being performed after the first step; a third step of forming a gate insulating film, a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad so that the gate insulating film covers the periphery and an upper portion of the pillar-shaped silicon layer and the polysilicon gate electrode covers the gate insulating film, that, after the formation of the polysilicon gate electrode, the polysilicon gate line, and the polysilicon gate pad, an upper surface of the polysilicon is located at a position higher than the gate insulating film located on the diffusion layer in the upper portion of the pillar-shaped silicon layer, and that the width of the polysilicon gate electrode and the width of the polysilicon gate pad are larger than the width of the polysilicon gate line, the third step being performed after the second step; a fourth step of forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer, the fourth step being performed after the third step; a fifth step of depositing an interlayer insulating film, exposing the polysilicon gate electrode, polysilicon gate line, and the polysilicon gate pad, and etching the polysilicon gate electrode, polysilicon gate line, and the polysilicon gate pad, and depositing a metal layer so as to form a metal gate electrode, a metal gate line, and a metal gate pad, the metal gate line forming so as to extend in a direction perpendicular to the fin-shaped silicon layer and being connected to the metal gate electrode, the fifth step being performed after the fourth step; and a sixth step of forming a contact directly connected to the diffusion layer in the upper portion of the pillar-shaped silicon layer, the sixth step being performed after the fifth step.