Patent ID: 8589922
Filing Date: 2013-11-19
Classification: G06F

Abstract:
1. A method comprising: setting a number of hypervisor register fields to specify which processor cores are allowed to generate a number of performance events for a particular thread group; configuring a plurality of software threads for an application running in the computing environment into a plurality of thread groups by a plurality of thread group fields in a plurality of control registers; specifying, by a number of additional hypervisor register fields, a number of counter sets that are allowed to count a number of thread group events originating from one of a shared resource and a shared cache; configuring a partition so that a performance event attributed to a particular software thread group is counted only by a counter set assigned to the particular thread group; and configuring a number of hypervisor registers, each hypervisor register comprising a first field and a second field, wherein the first field specifies a processor core allowed to generate a performance event for a thread group, and the second field specifies a counter set allowed to count the performance event of the thread group, wherein the performance event originates from the computing environment.