Patent ID: 7321238
Filing Date: 2008-01-22
Classification: H03K

Abstract:
1. In a semiconductor device, an input stage comprising: a pad for receiving an input signal to said semiconductor device; a buffer coupled to said input pad for buffering said input signal; a pullup circuit coupled to said input pad; a voltage supply coupled to said pullup circuit; a switching circuit coupled to said voltage supply and coupled to said input pad for controlling said pullup circuit, said switching circuit including a set of three inverters electrically coupled so that the output of said set of three inverters is coupled to the gate of a transistor in said pullup circuit, said set of three inverters including a first inverter powered by said input signal, a second inverter powered by said voltage supply and a third inverter powered by said input signal, said switching circuit enabled to cause said pullup circuit to stop current flow between said input signal and said voltage supply in the event of an over-voltage condition at said input pad.