Patent ID: 6832268
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A forward progress module, comprising:an address conflict checking module to compare a first memory address from a first coherent input/output (I/O) transaction with at least one memory address corresponding to at least one processor-issued transaction to determine if an address conflict exists; and a processor module to complete a first processor-issued transaction of the at least one processor-issued transactions that has the address conflict and to reject the first coherent I/O transaction, wherein the processor module waits for the first coherent I/O transaction to reenter the processor module after the forward progress module transmits the first coherent I/O transaction to an external I/O device, rejects remaining processor-issued transactions of the at least one processor-issued transaction other than the first processor-issued transaction that have the address conflict with the first memory address, completes the first coherent I/O transaction utilizing the processor module, and releases the remaining processor-issued transactions of the at least one processor-issued transaction that have the address conflict that were held in the forward progress module, once the first coherent I/O transaction is complete.