Patent ID: 7888796
Filing Date: 2011-02-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of memory chips stacked and each having a plurality of pads formed along two opposed sides of a main surface thereof; a microcomputer chip mounted over the memory chip located at the top stage out of the memory chips; and a plurality of external terminals coupled electrically to the microcomputer chip, wherein each of the memory chips includes: first pads formed over the main surface thereof along one of the two opposed sides of the main surface; lead-out wiring lines coupled electrically to the first pads; second pads formed over the main surface of the memory chip along the other of the two opposed sides of the main surface and coupled electrically to the lead-out wiring lines; and third pads coupled electrically to terminals of the microcomputer chip through wires over the lead-out wiring lines, and wherein, among the stacked memory chips, the second pads of the memory chip located at an upper stage and the second pads of the memory chip located at a lower stage and projected and exposed from the upper-stage memory chip are coupled together electrically using wires.