Patent ID: 6477058
Filing Date: 2002-11-05
Classification: H05K

Abstract:
An integrated circuit device package comprising:a land grid array integrated circuit device; a first circuit board having opposed, parallel, first and second major surfaces, each of the major surfaces of the first circuit board including a land grid array; a second circuit board having opposed, parallel, first and second major surfaces, the first major surface of said-second circuit board including a land grid array; a first land grid array interposer socket sandwiched between the land grid array integrated circuit device and the land grid array on the first major surface of the first circuit board; a second land grid array interposer socket sandwiched between the land grid array on the second major surface of the first circuit board and the land grid array on the first major surface of the second circuit board; and a clamping mechanism for compressively urging into electrical interconnection (i) the land grid array integrated circuit device and the land grid array on the first major surface of the first circuit board through the first land grid array interposer socket, and (ii) the land grid array on the second major surface of the first circuit board and the land grid array on the first major surface of the second circuit board through the second land grid array interposer socket.