Patent ID: 6137723
Filing Date: 2000-10-24
Classification: G11C,H01L

Abstract:
A memory device formed in a substrate material of a first conductivity type, the device comprising:a first well of a second conductivity type formed in the substrate material;a second well of the first conductivity type formed in the first well so that the second well is isolated from the substrate material by the first well;a row of memory cells, each memory cell including:a memory transistor having a source and a drain of the first conductivity type formed in the first well, a channel region defined between the source and drain, and a floating gate insulatively formed over the channel and the second well; andan access transistor having a source and a drain of the second conductivity type formed in the substrate material, and a gate, the drain of the access transistor being connected to the drain of the memory transistor;a page line connected to the source of each memory transistor in the row;an erase line connected to the second well;a well line connected to the first well;a plurality of enable lines connected to the access transistors in the row of memory cells so that each enable line is connected to the gate of an access transistor; anda plurality of sense lines formed so that each sense line is connected to a memory cell.