Patent ID: 8681917
Filing Date: 2014-03-25
Classification: H04J,H04L,H04W

Abstract:
1. A method of generating a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium, the method comprising: receiving a modulated signal that includes the encoded binary data stream via high speed data interface circuitry; extracting the encoded binary data stream from the modulated signal; generating a recovered clock signal that is phase locked to the encoded binary data stream with circuitry having a phase-locked loop that includes a loop filter configured with a bandwidth that does not substantially block the long-term drift in the modulated signal; generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal; integrating the error signal with the loop filter configured with a bandwidth that allows the jitter and drift in the encoded binary data stream to generate a signal to control a voltage controlled oscillator; generating a stable recovered clock signal by filtering the recovered clock signal using a filtering circuit having a bandwidth narrower than the bandwidth of the circuitry that is used for generating the recovered clock signal to remove jitter without substantially affecting the frequency of the stable recovered clock signal to allow the stable recovered clock signal to track drift of the encoded binary data stream; and producing at least one output clock by scaling the stable recovered clock signal frequency.