Patent ID: 6496416
Filing Date: 2002-12-17
Classification: G11C,H01L

Abstract:
A programmable memory cell comprising:a first doped region formed in a well region of a semiconductor substrate, the first doped region being oppositely doped from the well region; a second doped region formed in the well region, the second doped region being oppositely doped from the well region, the second doped region being separated from the first region by a channel region of the well region; an oxide layer, the oxide layer being formed over the channel region; a polysilicon layer formed over the oxide layer, the polysilicon layer having substantially the same outline as the oxide layer; and a metal silicide layer formed over the polysilicon layer, the metal silicide layer having substantially the same outline as the polysilicon layer, the metal silicide layer comprising: a first contact pad; a second contact pad; and a fusible region between the first contact pad and the second contact pad, the fusible region being positioned over the sections of the oxide layer and the polysilicon layer that overlie the channel region, the fusible region being configured to agglomerate under a programming voltage applied across the first contact pad and the second contact pad.