Patent ID: 6683476
Filing Date: 2004-01-27
Classification: H01L

Abstract:
An integrated circuit, the improvement comprising:a VDDio bus line disposed on a first layer of the integrated circuit, the VDDio bus line disposed along a length and having a first width transverse to the length, a VSSio bus line disposed on a second layer of the integrated circuit, the VSSio bus line disposed along the length and having a second width transverse to the length, the second width of the VSSio bus line substantially overlapping the first width of the VDDio bus line, and an input output cell disposed on a third layer of the integrated circuit, where the first layer, the second layer, and the third layer are all different layers of the integrated circuit, the input output cell having a first transistor electrically connected to the VDDio bus line and a second transistor electrically connected to the VSSio bus line, where the first transistor and the second transistor are disposed along the length within the input output cell.