Patent ID: 7610430
Filing Date: 2009-10-27
Classification: G06F,Y10S

Abstract:
1. A memory system, comprising: a memory hub controller; a memory bus coupled to the memory hub controller; a plurality of memory modules each having a memory hub coupled to the memory bus, each of the memory modules further having a plurality of memory devices coupled to the respective memory hub and the memory hub configured to issue memory requests to only the memory devices coupled thereto in response to memory requests from the memory hub controller; and at least one expansion module each having a processor unit coupled to the memory bus, each of the at least one expansion module further having a plurality of memory devices coupled to the respective processor unit, each processor unit configured to provide memory requests to the memory devices of the respective expansion module and at least one of the memory devices of one of the memory modules and receive memory responses from the memory devices to which the memory requests are provided.