Patent ID: 6566706
Filing Date: 2003-05-20
Classification: H01L

Abstract:
An array of electrically programmable and erasable memory devices comprising:a substrate of semiconductor material having a first conductivity type; an array of memory cells formed on the substrate; a first plurality of parallel spaced apart lines of a conductive material formed over the substrate and electrically coupled to the memory cells; a second plurality of parallel spaced apart lines of a conductive material formed over the substrate and electrically connected to the memory cells; and a strap region formed on the substrate and adjacent to the memory cell array, the strap region including: first strap cells through which the first plurality of conductive material lines traverse, wherein the first plurality of conductive material lines completely traverse across the strap region, a first plurality of conductive metal contacts each of which is connected to one of the first plurality of conductive material lines in one of the first strap cells, second strap cells in which the second plurality of conductive material lines terminate without completely traversing across the strap region, and a second plurality of conductive metal contacts each of which is connected to one of the second plurality of conductive material lines in one of the second strap cells.