Patent ID: 6300203
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method of forming a semiconductor device comprising at least one MOS transistor, comprising the steps of:(a) providing a semiconductor substrate including at least a region of a first conductivity type and having a surface;(b) forming in said region of first conductivity type a pair of spaced-apart source and drain regions of a second, opposite conductivity type, said pair of spaced-apart source and drain regions extending to said substrate surface and including a pair of opposed, facing edges with a space therebetween;(c) forming a blanket layer of an insulative material extending over said substrate;(d) exposing a portion of said substrate surface including said pair of facing edges of said pair of spaced-apart source and drain regions and said space therebetween;(e) forming a layer of a gate insulator precursor material on said exposed portion of said substrate surface by electrolytic deposition;(f) converting said layer of electrolytically-deposited gate insulator precursor material into a layer of a gate insulator material; and(g) forming an electrically conductive gate electrode material in contact with said layer of gate insulator material;wherein said steps are performed according to a first sequence (a), (c)-(d), (b), (e)-(g) or according to a second sequence (a)-(g).