Patent ID: 7689640
Filing Date: 2010-03-30
Classification: G06F

Abstract:
1. A method for providing a number formatting operation on an operand to produce a result value in a microprocessor, the method comprising: performing a right shift operation on the operand by a shift amount, the shift amount comprising zero or more bit positions, to produce a shifted result; computing a rounding value on the basis of the shift amount and a most significant bit shifted out of the operand, the method of computing the rounding value further comprising setting the rounding value to one if the shift amount is not equal to zero and the most significant bit shifted out of the operand is equal to one, and setting the rounding value to zero if either of the shift amount and the most significant bit shifted out of the operand equals zero; setting a rounded result value equal to a sum of the rounding value and the shifted result; computing a decremented bit number value by subtracting a value of one from a bit number; computing a masking value equal to one less than a power of two raised to an exponent equal to the bit number; computing a mask application result value on the basis of a signed number flag bit value and a bit position of the rounded result value, the bit position corresponding to the decremented bit number value, the method of computing the mask application result value further comprising: if the signed number flag is zero, setting the mask application result value equal to a bitwise “and” operation on the rounded result and the masking value; if the signed number flag is one and the bit position of the rounded result value corresponding to the decremented bit number value is a one, setting the mask application result value equal to a bitwise “or” operation on the rounded result and a bitwise inversion of the masking value; and if the signed number flag is one and the bit position of the rounded result value corresponding to the decremented bit number value is a zero, setting the mask application result equal value to a bitwise “and” operation on the rounded result and the masking value; computing a saturated result value on the basis of the signed number flag bit value and a most significant bit position of the rounded result value, computing the saturated result value further comprising: if the signed number flag is equal to zero and the most significant bit position of the rounded result value is equal to one, setting the saturated result value equal to zero; if the signed number flag bit value is equal to zero and the most significant bit position of the rounded result value is equal to zero, setting the saturated result value equal to the masking value; and if the signed number flag bit value is equal to one and the most significant bit position of the rounded result value is equal to one, setting the saturated result value equal to a bitwise inversion of a concatenation of a 1-bit zero and a portion of the masking value excluding a least significant bit of the masking value; if the signed number flag bit value is equal to one and the most significant bit position of the rounded result value is not equal to one, setting the saturated result value equal to the concatenation of the 1-bit zero and the portion of the masking value excluding the least significant bit of the masking value; and selecting the result value for the formatted operand, selecting further comprising: if the mask application result value and the rounding result value are equal, setting the result value for the formatted operand equal to the rounding result value; if the bit number is equal to zero, setting the result value for the formatted operand equal to the rounding result value; and if the mask application result value and the rounding result value are not equal and the bit number is not equal to zero, setting the result value for the formatted operand equal to the saturated result value.