Patent ID: 8943379
Filing Date: 2015-01-27
Classification: G06F,H03M,H04L

Abstract:
1. An apparatus, comprising: a processor having a cache, a plurality of processing cores and a network between said cache and said processing cores, said cache to provide cached data to any of said processing cores, wherein, circuitry to send cached data to its respective processing core includes an ECC unit, a buffer and a bypass that circumvents said buffer, said buffer to queue requested cached data and its destination and header information between said cache and said network, said bypass to send said requested cached data's destination and header information to its respective processing core without delay imposed by said buffer, wherein, upon said ECC unit providing an indication that said requested cached data is corrupted after it is too late to prevent said requested cached data's destination and header information from being sent into said network, said circuitry: marks said requested cached data with a retry bit and forwards said requested cached data towards said network; and prevents other requested cached data from being entered into said buffer for a predetermined number of cycles following said indication.