Patent ID: 6396322
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A delay locked loop for use in a semiconductor memory device, the delay locked loop comprising:a first differential amplifier receiving a clock signal at a positive input and an inverted clock signal at a negative input; a second differential amplifier receiving the clock signal at a negative input and the inverted clock signal at a positive input; a delaying circuit receiving an output of each of the first and second differential amplifiers for delaying in time the clock signal by a skew to be compensated; a measurement delay line for adjusting a time delay of an output of the delaying circuit in a first direction; a phase comparator receiving outputs of the measurement delay line and the first differential amplifier; a variation delay line receiving outputs of the phase comparator and the first differential amplifier for adjusting the time delay in a second direction so as to detect a rising edge of the clock signal; a duplicate delay line receiving outputs of the variation delay line and the second differential amplifier so as to detect a falling edge of the clock signal; and an output buffer receiving outputs of the variation delay line and the duplicate delay line to output a delay locked loop clock signal which is substantially in phase with the clock signal.