Patent ID: 7180351
Filing Date: 2007-02-20
Classification: G09G,G11C,H03K

Abstract:
1. A hybrid latch flip-flop, comprising: a negative pulse generating unit; a clock input connected to the negative pulse generating unit for applying clock signals to the negative pulse generating unit; a latch flip-flop connected to the negative pulse generating unit, the latch flip-flop comprising a sample unit and a hold unit, an output of the sample unit connected to the hold unit; a buffer unit connected to the hold unit; a data input unit connected to an input of the sample unit for applying input data signals to the sample unit; and a data output connected to the buffer unit for outputting output data signals; wherein the sample unit comprises four PMOS type transistors; which are a first PMOS transistor, a second PMOS type transistor, a third PMOS type transistor, and a fourth PMOS type transistor; and three NMOS type transistors, which are first NMOS type transistor, a second NMOS type transistors, and a third NMOS type transistor; the source of the first PMOS type transistor and the source of the third PMOS type transistor being connected to a power source VDD; the gate of the first PMOS type transistor, the gate of the first NMOS transistor, and the gate of the third PMOS type transistor all being connected to an output of the negative pulse generating unit; the gate of the second NMOS type transistor and the gate of the second PMOS type transistor being both connected to the data input unit; the drain of the first PMOS type transistor being connected to the source of the second PMOS type transistor; the drain of the third PMOS type transistor being connected to the source of the fourth PMOS type transistor; a node V