Patent ID: 8716102
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A method, comprising; forming a patterned mask layer above a semiconducting substrate, said patterned mask layer comprising a polish stop layer positioned above a protection layer; performing at least one etching process through said patterned mask layer on said substrate to define a trench in said substrate; forming a layer of silicon dioxide above said patterned mask layer such that said layer of silicon dioxide overfills said trench; removing portions of said layer of silicon dioxide positioned outside of said trench and above an upper surface of said polish stop layer to thereby define an isolation structure with an upper surface that is substantially planar with said upper surface of said polish stop layer; performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to said polish stop layer so as to remove portions of said isolation structure and define a reduced height isolation structure having a recessed upper surface that is below a level of said upper surface of said polish stop layer; and after forming said reduced height isolation structure, performing a selective wet etching process to remove said polish stop layer selectively relative to said reduced height isolation region.