Patent ID: 6833594
Filing Date: 2004-12-21
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate; a second well of the first conductivity type formed in the semiconductor substrate, the first and second wells being discrete and spaced apart from each other; a first lateral MOS transistor having a source area, a drain area, and a channel area formed between the source and drain areas thereof, the source, drain, and channel areas thereof being formed in said first well; a second lateral MOS transistor having a source area, a drain area, and a channel area formed between the source and drain areas thereof, the source, drain, and channel areas thereof being formed in said second well; and a punch-trough stopper area surrounding the source area end the drain area of said first lateral MOS transistor in the first well and providing a punch-through voltage resistance between said source area and said drain area of said first lateral MOS transistor, wherein the punch-through stopper area is formed within the first well, wherein said second lateral MOS transistor has a lower threshold voltage than said first lateral MOS transistor, and wherein the length of the channel area of said first lateral MOS transistor is smaller than the length of the channel area of said second lateral MOS transistor.