Patent ID: 6794925
Filing Date: 2004-09-21
Classification: H03K

Abstract:
A redundant system having an output comprising:a first transistor having a gate, a source, and a drain, wherein the gate of the first transistor is controlled by a function of a first chip; a second transistor having a gate, a source, and a drain, wherein the source and drain of the first transistor and the source and drain of the second transistor are connected in series between the output and a first potential terminal; a third transistor having a gate, a source, and a drain, wherein the gate of the third transistor is controlled by a function of a second chip, wherein the first and second chips are redundant chips; a fourth transistor having a gate, a source, and a drain, wherein the source and drain of the third transistor and the source and drain of the fourth transistor are connected in series between the output and a second potential terminal; and, a first control circuit connected to the gate of the second transistor and a second control circuit connected to the gate of the fourth transistor so as to turn on one of the second and fourth transistors at a time.