Patent ID: 8110486
Filing Date: 2012-02-07
Classification: H01L

Abstract:
1. A method of producing a semiconductor wafer by eventually forming a strain-relaxed SiGe layer, including lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer, on an insulating layer in a SOI wafer comprising a Si wafer, the insulating layer and a SOI layer laminated in this order, comprising the steps of: forming a lower portion of the SiGe layer directly on the SOI layer at a gradient of Ge concentration gradually increasing towards the surface thereof away from the SOI layer, thereby forming a graded concentration profile in the lower portion; forming an upper portion of the SiGe layer at a gradient of Ge concentration gradually decreasing toward a surface of the SiGe layer away from the SOI layer thereby forming a reverse graded concentration profile in the upper portion; forming a Si layer on the SiGe layer; and, subjecting the SiGe layer to a heat treatment at a temperature of not lower than 1100 degrees C. in an oxidizing atmosphere, wherein at least a part of the upper portion of the SiGe layer and the Si layer changes into a SiO wherein the reverse graded concentration profile and the graded concentration profile are adjacent to and abut each other to form a single triangular-shaped concentration profile for the SiGE layer, the reverse graded concentration profile forming one side of the single triangular shaped concentration profile, the graded concentration profile forming another side of the single triangular shaped concentration profile; wherein the single triangular shaped concentration profile for the SiGe layer is maintained when forming the Si layer on the SiGe layer.