Patent ID: 6982444
Filing Date: 2006-01-03
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a first insulator film formed on said substrate; a ferroelectric capacitor having a bottom electrode, a ferroelectric film and a top electrode, which are sequentially stacked on said first insulator film, said ferroelectric film being patterned on said bottom electrode having a predetermined pattern so as to have an area smaller than an area of said bottom electrode; a first interlayer insulation layer covering the ferroelectric capacitor; and a first hydrogen barrier film deposited on the first interlayer insulation layer so that at least a top and side of said ferroelectric capacitor are enveloped by said first interlayer insulation layer, and said first hydrogen barrier film, wherein said ferroelectric capacitor further comprises a second insulator film formed only directly on said top electrode, and a third insulator film formed to cover said second insulator film and sides of said top electrode; and wherein said second and third insulator films are formed between the ferroelectric capacitor and the first interlayer insulation layer.