Patent ID: 8859336
Filing Date: 2014-10-14
Classification: H01L

Abstract:
1. A method of assembling semiconductor devices, comprising: placing an array of semiconductor dies on a die support, wherein said die support comprises a first set of alignment holes; providing a cap array structure including a corresponding array of cap elements supported by a cap frame structure, wherein said cap array structure comprises a second set of alignment holes; aligning said cap array structure and said array of semiconductor dies on said die support, wherein said cap elements extend over corresponding semiconductor dies, in a mold chase, wherein said mold chase includes location pins for positioning and aligning said cap array structure and said array of semiconductor dies on said die support using said first and second sets of alignment holes; encapsulating said array of semiconductor dies and said array of cap elements with a molding compound; and singulating encapsulated units of said semiconductor dies and cap elements.