Patent ID: 7472360
Filing Date: 2008-12-30
Classification: H01L,H05K

Abstract:
1. A computer-implemented method for implementing enhanced wiring capability for electronic laminate packages comprising the steps of: receiving electronic package physical design data; identifying instances of line width and space limit violations in the electronic package physical design data; evaluating the identified instances of line width and space limit violations using predefined qualified options and tolerance limitations; modifying shapes of predefined package connection pads and maintaining total connection pad area with predefined sizes of the modified connection pads to provide increased wiring space between the modified connection pads, to enlongate the modified connection pad along a predefined axis of a fatigue strain component, and to maintain solder volume within the tolerance limitations for the electronic laminate package; and modifying the electronic package physical design data to optimize shapes to replace the instances of line width and space limit violations.