Patent ID: 7774461
Filing Date: 2010-08-10
Classification: H04L

Abstract:
1. A method for determining a congestion metric for a particular path in a network, comprising: sending, by a first multi-path load balancing (MPLB) component associated with a first network device, a latency request packet to a second MPLB component associated with a second network device via the particular path, wherein the latency request packet comprises a timestamp provided by a first clock associated with the first MPLB component; receiving, by the first MPLB component, a latency response packet sent by the second MPLB component in response to the latency request packet, wherein the latency response packet comprises a timestamp provided by a second clock associated with the second MPLB component, wherein the first clock and the second clock are not synchronized with each other; determining a clock offset value that represents a difference in time values provided by the first clock and the second clock by sending a second latency request packet from the first MPLB component to the second MPLB component via the particular path, wherein the second latency request packet comprises an initial timestamp provided by the first clock; receiving, by the first MPLB component, a second latency response packet sent by the second MPLB component in response to the second latency request packet, wherein the second latency response packet comprises a second timestamp provided by the second clock; obtaining a received timestamp from the first clock, wherein the received timestamp approximately indicates a time at which the second latency response packet was received by the first MPLB component; determining, based at least partially upon the initial timestamp and the received timestamp, a roundtrip latency value which indicates how much time is needed for a set of information to travel from the first MPLB component to the second MPLB component along the particular path and back to the first MPLB component; determining whether the roundtrip latency value is less than a previously established minimum roundtrip latency value; in response to a determination that the roundtrip latency value is less than the previously established minimum roundtrip latency value, deriving an estimated one-way latency value based upon the roundtrip latency value, wherein the estimated one-way latency value indicates how much time is estimated to be needed for a set of information to travel from the first MPLB component to the second MPLB component along the particular path; computing the clock offset value based at least partially upon the initial timestamp, the second timestamp and the estimated one-way latency value; deriving, by the first MPLB component, a one-way latency value for the particular path based at least partially upon the timestamp provided by the first clock and the timestamp provided by the second clock, wherein the one-way latency value indicates how much time is needed for a set of information to travel from the first MPLB component to the second MPLB component along the particular path and wherein the one one-way latency value for the particular path is derived based at least partially upon the timestamp provided by the first clock, the timestamp provided by the second clock, and the clock offset value; and wherein the first MPLB and the second MPLB are realized using one or more of hardware logic components, one or more Application Specific Integrated Circuit (ASIC) and one or more processors executing a set of instructions.