Patent ID: 6384449
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A nonvolatile memory comprising:a semiconductor substrate having a selection transistor and a cell transistor defined thereon; a line form of a first selection gate line formed on the selection transistor region in one direction and a floating gate formed on the cell transistor region in a fixed pattern; an insulating film and a second gate line formed on the first selection gate line at fixed intervals, and an insulating film and a control gate line over the insulating film including the floating gate in a direction the same with the first gate line; impurity regions formed in one region in the semiconductor substrate on both sides of the control gate line and the first selection gate line; a first planar protection film having first contact holes one each to the first selection gate line and to the impurity region; a contact plug in the first contact hole; a conductive layer pattern in contact with the contact plug; a second planar protection film having a contact hole to the conductive layer pattern over the first selection gate line; and, a wiring line formed on the second contact hole and the second planar protection film in one direction.