Patent ID: 9128151
Filing Date: 2015-09-08
Classification: G01R

Abstract:
1. A circuit structure, comprising: a plurality of scan chains each having a plurality of scan chain elements configured to operate as a shift register in a test mode while an integrated circuit undergoes a test mode of operation, and obtain functional data from circuitry in the integrated circuit during a functional mode of operation; and a scan chain link configured to pair at least one scan chain element from a first scan chain with at least one scan chain element of a second scan chain to form a performance screen ring oscillator (PSRO), wherein the PSRO formed by the scan chain link pairing the at least one scan chain element from the first scan chain with the at least one scan chain element of the second scan chain causes a forward path associated with data flow through the at least one scan chain element of the first scan chain to act as a backward path for data flow through the at least one scan chain element of the second scan chain, and a forward path associated with data flow through the at least one scan chain element of the second scan chain to act as a backward path for data flow through the at least one scan chain element of the first scan chain.