Patent ID: 6566216
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A process for manufacturing a semiconductor device comprising:(a) forming element isolating areas on a semiconductor substrate; (b) forming a source and drain layer of a transistor by an ion implanting process; (c) successively laminating a silicon dioxide layer and a silicon nitride layer in this order; (d) forming a trench having such a depth that it reaches said semiconductor substrate by etching said silicon nitride layer, said silicon oxide layer and said source and drain layer by using a resist pattern as a mask; (e) forming a sidewall on an inner wall of said trench; (f) filling a space surrounded by said sidewall of said trench with a first electrically conductive material designed to become a columnar gate electrode; (g) removing said sidewall; (h) forming a lightly doped drain layer by implanting ions in an area of said trench below said columnar gate electrode in which said sidewall has been removed; (i) forming an interlayer insulator layer over an entirety of said semiconductor substrate; (j) forming a contact hole by etching through said interlayer insulator layer, said silicon nitride layer and said silicon oxide layer; and (k) forming a predetermined wiring after embedding the inside of said contact hole with a second electrically conductive material, wherein a channel area of said transistor is formed at a position deeper than a source and drain area of said source and drain layer.