Patent ID: 6303436
Filing Date: 2001-10-16
Classification: H01L,Y10S

Abstract:
A method for fabricating a type of Trench Mask ROM cell on a substrate, wherein said method comprises the steps in the following sequence:forming a pad oxide layer on said substrate;forming a nitride layer on said pad oxide layer;forming plural trenches on said substrate by etching back said pad oxide layer, said nitride layer and said substrate;removing said nitride layer;forming a gate oxide layer on an outer surface of each said trench;forming plural first doped regions in said substrate, wherein said first doped regions are beneath said pad oxide layer and between two adjacent trenches, with said first doped regions acting as bit lines of said Trench Mask ROM cell;forming a polysilicon layer on an outer surface of said pad oxide layer and said gate oxide layer, wherein said polysilicon layer is a word line of said Trench Mask ROM cell; andforming plural second doped regions in said substrate beneath said gate oxide layer and beneath said gate oxide layer on bottoms of selected trenches to form coding regions of said Trench Mask ROM cell.