Patent ID: 8788563
Filing Date: 2014-07-22
Classification: G06F

Abstract:
1. An addition device for adding a plurality of input binary numbers each represented by a digital signal of N bits, wherein the device comprises: inputs configured to receive the digital signals representing the plurality of input binary numbers; at least one accumulation device configured to carry out, each time that it is activated, one iteration, of index i+1 with i≧0, of an accumulation mechanism, each accumulation device comprising estimation means selected from the group consisting of: first estimation means for generating an estimation signal U and second estimation means for generating an estimation signal U with: U i+1 n : value of the bit of rank n of said estimation signal U i+1 , with 0≦n≦N−1, obtained during said iteration of index i+1; U i n : a value of the bit of rank n of an estimation signal U i , obtained during a preceding iteration of index i if i>0, or a determined initialization value U 0 n of the bit of rank n of an estimation signal U i if i=0; U i n−1 : a value of the bit of rank n−1 of said estimation signal U i , obtained during a preceding iteration of index i if n>0 and if i>0, or a determined initialization value U or a predetermined initialization value of an fictive bit of rank n−1 of said estimation signal U R i n : a value of the bit of rank n of a first correction signal R i , obtained during a preceding iteration of index i if n>0, or a predetermined initialization value of the bit of rank n of said first correction signal R R i+1 n+1 : a value of the bit of rank n+1 of said first correction signal R i+1 , obtained during said iteration of index i+1; H i n : a value of the bit of rank n of a second correction signal H i , obtained during a preceding iteration of index i; H i+1 n+1 : a value of the bit of rank n+1 of said second correction signal H i+1 , obtained during said iteration of index i+1; C n : a value of the bit of rank n of an input binary number C included in said plurality of input binary numbers and taken into account in said addition during said iteration of index i+1, the estimation signal U i and the first correction signal R i or the second correction signal H i representing a sum of at least two binary numbers of the plurality of input binary numbers in redundant form, the estimation signal U i+1 and the first correction signal R i+1 or the second correction signal H i+1 , representing the sum of said at least two binary numbers in redundant form and of the binary number c, wherein the last iteration of U n is the sum S n of the bit of rank n.