Patent ID: 8188768
Filing Date: 2012-05-29
Classification: H03K

Abstract:
1. A comparator circuit for an analog-to-digital converter, comprising: an input stage including a pair of differential input sections having input transistors to gate terminals of which differential input signals are applied and a bias transistor to a gate terminal of which a bias voltage is applied, and PMOS diode loads configured to indirectly transfer the differential input signals to a signal regeneration stage; the signal regeneration stage including PMOS current sources connected to the PMOS diode loads and configured to form current mirrors, a signal regeneration circuit having one terminals which are connected to the PMOS current sources and constituted by connecting inputs and outputs of two inverters with each other, and two NMOS switches having one terminals which are connected to the signal regeneration circuit and the other terminals which are connected to a ground source; and a sensing stage including an input section configured to receive output signals of first and second signal regeneration nodes as outputs of the signal regeneration stage, and first and second transmission gates configured to sense the signals applied to the input section, generate logic signals and transfer the generated logic signals to a latch.