Patent ID: 9082646
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a source region disposed within a semiconductor substrate; a drain region disposed within the semiconductor substrate; a gate region disposed on the semiconductor substrate and positioned between the source region and the drain region; a gate oxide region disposed onto the semiconductor substrate in contact with the gate region; a well region implanted into the semiconductor substrate under the gate region and the gate oxide region, the well region comprising a first well and a second well, and a shallow trench isolation (STI) region disposed above the second well, the STI region disposed adjacent to the source region and separating the second well from the source region, wherein the gate oxide region has a lower outer edge portion that contacts the well region, wherein the gate oxide region comprises a first portion having a first thickness and a second portion having a second thickness, and wherein the first well is disposed under the drain region, the first well is in direct contact with the first portion of the gate oxide region, and the first well is separated from the STI region disposed adjacent to the source region.