Patent ID: 7787316
Filing Date: 2010-08-31
Classification: G11C

Abstract:
1. A semiconductor memory device capable of performing successive write operations synchronized with a clock signal, comprising: a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells arranged at intersections of the word lines and the bit lines, respectively; a row selector selectively activating the word lines; a plurality of write drivers each supplying a write current to an associated at least one of the bit lines; a plurality of write control circuits controlling operations of an associated at least one of the write drivers; and a column selector selecting at least one of the write control circuits, wherein the column selector successively select a predetermined write control circuit per j cycles of the clock signal in a state of activating a predetermined word line, wherein j is a positive number, and the selected write control circuit activates the associated at least one of the write drivers over a period of j or more cycles of the clock signal.