Patent ID: 9086920
Filing Date: 2015-07-21
Classification: G06F

Abstract:
1. A device for managing data buffers in a memory space distributed over a plurality of memory elements, the memory space being allocatable by memory pages, each buffer comprising one or more of the memory pages, the buffers being usable by at least one processing unit for the execution of an application, the application being executed by a plurality of processing units executing tasks in parallel, the memory elements being accessible in parallel by the processing units, said device comprises: a task manager for allocating tasks to the processing units; a memory manager module comprising a buffer allocator configured to allocate buffers to tasks during the execution of the application, said buffer allocator being configured to allocate the buffers to tasks depending on a fill state of the buffers and to minimize a maximum number of buffers allocated to a same memory element; and a manager module configured to manage access rights to the buffers wherein the manager module is configured to manage access rights to the pages in a given buffer by verifying that writing to a given page does not modify data currently being read from said page or that reading from a given page does not access data currently being written to said page, to share said given buffer between unsynchronized tasks, and wherein said buffer allocator includes one or more memory page fill state registers, information in each memory page fill state register characterizing an empty state or a non-empty state of the given memory pages or memory elements, said buffer allocator being further configured to apply one or more bitwise Boolean logic operations to the information in said memory page fill state registers to accelerate an updating of the memory element fill state registers.