Patent ID: 6084283
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A semiconductor device having a low-breakdown-voltage-element area and a high-breakdown-voltage-element area on the same semiconductor substrate, and arranged in a peripheral circuit of a non-volatile memory, comprising:(a) a first transistor in said low-breakdown-voltage-element area, formed of a field effect transistor of a first conductivity channel, and comprisinga first source layer and a first drain layer formed in a common surface of said semiconductor substrate to interpose a first channel region therebetween in a first channel-length direction and have LDD portions of a conductivity type the same as that of said first source and drain layers and having a low carrier-impurity concentration, respectively, on sides facing each other, anda first gate electrode facing said first channel region through an insulating film,wherein said LDD portion of said first drain layer has a carrier-impurity concentration and a length in said first channel-length direction, the same as those of said LDD portion of said first source layer; and(b) a second transistor in said high-breakdown-voltage-element area, formed of a field effect transistor of a first conductivity channel, and comprisinga second source layer and a second drain layer formed in said common surface of said semiconductor substrate to interpose a second channel region therebetween in a second channel-length direction and have LDD portions of a conductivity type the same as that of said second source and drain layers and having a low carrier-impurity concentration, respectively, on sides facing each other, anda second gate electrode facing said second channel region through an insulating film,wherein said LDD portion of said second drain layer has a lower carrier-impurity concentration and a longer length in said second channel-length direction, than those of said LDD portion of said second source layer.