Patent ID: 6421251
Filing Date: 2002-07-16
Classification: G06F

Abstract:
A multi-board interconnect system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:a local bus interconnect separated from the motherboard connector and coupled to the system bus; a first board directly coupled to the motherboard via the motherboard connector and the local bus interconnect, and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements and the first logic bus coupled to the local bus interconnect; and a second board directly coupled to the first board via the local bus interconnect and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements and the second logic bus coupled to the local bus interconnect, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the local bus.