Patent ID: 8796093
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A method comprising: obtaining a structure comprising a substrate including an electrically insulating layer, a plurality of parallel fins comprised of a semiconductor material, each of the plurality of parallel fins having a base portion adjoining the electrically insulating layer, and one or more gate structures extending between the plurality of parallel fins; epitaxially forming a faceted doped layer on the plurality of parallel fins and merging the plurality of parallel fins, the faceted doped layer being comprised of a doped material selective with respect to the plurality of parallel fins; causing dopants from the faceted doped layer to be driven into the plurality of parallel fins, thereby uniformly doping the plurality of parallel fins, including the base portions of the plurality of parallel fins; removing the faceted doped layer, and epitaxially forming doped source/drain regions on the plurality of parallel fins subsequent to removing the faceted doped layer.