Patent ID: 6546507
Filing Date: 2003-04-08
Classification: G06F

Abstract:
A test system for testing communication over a bus between a first electronic device and a second electronic device, each of the first and second electronic devices having a bus interface connected to the bus, the test system being embedded in the electronic devices, the test system comprising:a stress injection module for injecting a set of stimulus patterns on the bus; an error identification module for identifying an error resulting from the set of stimulus patterns, the error identification module comprising a first failure capture module for identifying a first failure in one of the first and second electronic devices resulting from the set of stimulus patterns; a bus tuning module for adjusting one or more bus operating and signaling parameters by varying one or more electronic characteristics of the bus interface in response to a set of digital control signals so that testing can be performed at one or more of a number of different sets of operating and signaling parameters; a programmable control module for providing the digital control signals to the bus tuning module; and a presentation module for presenting a plurality of results of the testing.