Patent ID: 8508265
Filing Date: 2013-08-13
Classification: H03L

Abstract:
1. A phase locked loop (PLL) circuit, comprising: a first phase frequency detector configured to output a first differential control signal in response to a reference signal and a division signal for an oscillation signal; a second phase frequency detector configured to output a second differential control signal in response to an inverted reference signal and an inverted division signal; a first charge pump configured to output a first current that is controlled according to the first differential control signal; a second charge pump configured to output a second current that is controlled according to the second differential control signal; a first loop filter configured to output a first control voltage that corresponds to the first current; a second loop filter configured to output a second control voltage that corresponds to the second current; a voltage controlled oscillator (VCO) configured to output the oscillation signal in response to a difference between the first and second control voltages; a first switch configured to selectively couple the first charge pump and the first loop filter in response to a first switch control signal; and a second switch configured to selectively couple the second charge pump and the second loop filter in response to a second switch control signal.