Patent ID: 6501117
Filing Date: 2002-12-31
Classification: G11C,H01L

Abstract:
A static self-refreshing DRAM cell comprising:a deep trench having sidewalls and a bottom which is formed in a semiconductor substrate having upper, central and lower portions, a plate electrode of a capacitor formed in the substrate surrounding the lower portion of the deep trench, the plate electrode being doped with a first dopant type and being separated by an interface from a well region surrounding the upper and central portions of the deep trench, the well region being doped with an opposite dopant type, and a cap region formed above the well, the cap region being doped with the first dopant type, a node dielectric layer formed covering the sidewalls and bottom of the lower and central portions of the deep trench filled with a node electrode of the capacitor, the node electrode being doped with the first dopant type and being located within the space defined by the node dielectric layer in the lower and central portions of the deep trench, a buried-strap comprising a conductor formed about the upper portion of the node electrode, an outdiffusion region doped with the first dopant type formed in the well region proximate to the buried-strap, the cell including an FET transistor formed above the buried-strap and connected thereto having binary states comprising a first state and an opposite state of operation, and the cell including a punchthrough device formed in the well between the outdiffusion region and the interface, the punchthrough device providing a punchthrough current which provides self-refreshing current in the cell between the well and the plate in the first state of operation of the cell and reverse bias junction leakage in the cell between the buried-strap and the P-well occurs refreshing the opposite state of operation of the cell.