Patent ID: 8671285
Filing Date: 2014-03-11
Classification: G06F,H04L

Abstract:
1. A microprocessor, comprising: an instruction cache; an instruction decode unit; and a fetch unit, configured to: wherein in a first instance the block comprises encrypted instruction data and the data entity is a decryption key; wherein in a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes; wherein the microprocessor is configured to use equal amounts of time to perform feats (a), (b), and (c) in the first and second instances regardless of whether the block of instruction data is encrypted or unencrypted; wherein the plain text instruction data decrypted from the encrypted instruction data is unobservable outside the microprocessor; and wherein the time to perform said feats (a), (b), and (c) is the same independent of whether a branch instruction is present or absent within the fetched block of instruction data.