Patent ID: 6105127
Filing Date: 2000-08-15
Classification: G06F

Abstract:
A multithreaded processor for executing multiple instruction streams, each of said multiple instruction streams may contain a special instruction to change a priority level of the corresponding instruction stream, the multithreaded processor comprising,a plurality of functional units for respectively executing an instruction;a plurality of instruction decode means, corresponding to the multiple instruction streams on a one-to-one basis, for respectively decoding an instruction, and producing an instruction issue request for designating to which functional unit the decoded instruction should be issued and requesting for the issuance of the decoded instruction to the designated functional unit;holding means for holding the priority level of each of the instruction streams, wherein each priority level is independent of the priority levels of the other instruction streams; andcontrol means for deciding which decoded instruction should be issued to a functional unit designated by two or more instruction request at the same time, in accordance with the priority levels stored by the holding means;wherein one of the functional units receives the special instruction from one of the instruction streams for individually and independently changing the priority level of the corresponding instruction stream in the holding means.