Patent ID: 6100202
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method for forming through a doped silicate glass dielectric layer within a microelectronics fabrication a via comprising:positioning within a reactor chamber a substrate employed within a microelectronics fabrication;stabilizing the substrate within the reactor chamber by introducing into the reactor chamber a first flow of a silicon source material absent a flow of a dopant source material;depositing then upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method, the doped silicate glass dielectric layer being formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material;anisotropically patterning the doped silicate glass dielectric layer to form an anisotropically patterned doped silicate glass dielectric layer defining an anisotropically patterned via accessing the substrate; andisotropically etching the anisotropically patterned doped silicate glass dielectric layer to form an isotropically etched anisotropically patterned doped silicate glass dielectric layer defining an isotropically etched anisotropically patterned via accessing the substrate, wherein by stabilizing the substrate within the reactor chamber by introducing into the reactor chamber the first flow of the silicon source material absent the flow of the dopant source material the isotropically etched anisotropically patterned via is formed without a void in the sidewall of the isotropically etched anisotropically patterned via at the juncture of the isotropically etched anisotropically patterned doped silicate glass dielectric layer and the substrate.