Patent ID: 6119215
Filing Date: 2000-09-12
Classification: G06F

Abstract:
A system for synchronously controlling a processing engine adapted to process transient data, the system comprising:a plurality of processing elements symmetrically arrayed as pipeline rows and columns, the processing elements of each row configured as stages of a pipeline that sequentially execute operations on the transient data and the processing elements of each column operating in parallel to perform substantially the same operation on the transient data;an external memory partitioned into a plurality of memory resources, each partitioned resource dedicated to a respective column of processing element stages; andan input header buffer (IHB) configured to load the transient data into an available pipeline for processing, the IHB comprising input sequencing circuitry that controls the processing element stages of each pipeline row by ensuring that each stage completes processing of current transient data prior to loading new transient data into the stages at a new phase, the input sequencing circuitry further controlling the processing element stages of each column to ensure that each stage performs its processing at a shifted phase with respect to the other columned stages, thereby substantially obviating the need for arbitration to access the partitioned memory resource.