Patent ID: 6362659
Filing Date: 2002-03-26
Classification: H03K

Abstract:
A domino logic circuit comprising:an inverter having an input and an output; a logic block having one or more n-channel transistors that provide a desired logic function between the input of the inverter and ground; at least one p-channel transistor for supplying a pre-charging current to the input of the inverter; the at least one p-channel transistor having a source, a drain, and a gate, the source of the at least one p-channel transistor being coupled to a power supply voltage, the drain of the at least one p-channel transistor being coupled to the input of the inverter, and the gate of the at least one p-channel transistor being coupled to the output of the inverter; wherein substantially all of the pre-charging current flows through the at least one p-channel transistor; and an n-channel transistor having a source, a drain and a gate, the source of the n-channel transistor being coupled to ground, the drain of the n-channel transistor being coupled to the output of the inverter, and the gate of the n-channel transistor being coupled to a clock signal.