Patent ID: 6512687
Filing Date: 2003-01-28
Classification: G11C

Abstract:
A non-volatile ferroelectric capacitor memory circuit comprising:a volatile memory cell portion having a flip-flop configuration and having two internal nodes latched into complementary states during operation of said volatile portion; first and second ferroelectric capacitors each having respectively first and second plates, wherein said first plate of said first and second ferroelectric capacitors coupled to said two internal nodes respectively; a first transistor providing a source-drain path for said second plate of said first ferroelectric capacitor to couple with said second plate of said second ferroelectric capacitor; a second transistor having a source/drain electrode to couple with said source/drain electrode of said first transistor; a plate line coupling said second transistor, and through said source-drain path of said second transistor coupling with said source/drain electrode of said first transistor; and first and second signal lines coupling with said first and second transistors, respectively.