Patent ID: 7016237
Filing Date: 2006-03-21
Classification: G11C

Abstract:
1. A circuit for receiving data for a synchronous semiconductor memory device, comprising: a strobe generator having a flip flop and a plurality of logic gates for generating S(n) internal strobes based on an external strobe signal, each of the S(n) internal strobes having a latch-triggering transition occurring one after another in response to the external strobe signal; a plurality of latches for receiving an n-bit data, including at least one set of latches being clocked by the S(n)th internal strobe and another set of latches for receiving the outputs from the one set of latches, the another set of latches being clocked by an internal clock signal having a period longer than that of an external clock signal; and a data write driver for receiving the outputs of the another set of latches and for driving the n-bit data into memory cells of the memory device under clocking control of the external clock.