Patent ID: 6245657
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A method of fabricating a metal interconnect structure, on a semiconductor substrate, self-aligned to an underlying metal plug structure, comprising the steps of:forming a lower level, metal interconnect structure;depositing an interlevel dielectric, (ILD), layer;forming a via hole in said ILD layer, exposing a portion of a top surface of said lower level, metal interconnect structure;forming a recessed metal plug structure in a bottom portion of said via hole;depositing a metal layer;forming a photoresist shape on a portion of said metal layer, located on said ILD layer; and located in an inside edge of said via hole; andpatterning of said metal layer, using said photoresist shape as a mask, to form an upper level, metal interconnect structure comprised of: a metal structure component, defined from said portion of said metal layer protected by overlying said photoresist shape, and comprised of a metal ring component, not protected by said photoresist shape, during said patterning procedure, located in a top portion of said via hole, and with said metal ring component comprised of metal spacers on the sides of a top portion of said via hole, overlying and contacting a portion of said recessed metal plug structure.