Patent ID: 8063658
Filing Date: 2011-11-22
Classification: H01L,H03K,H04L

Abstract:
1. In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the semiconductor device, the termination circuit comprising: a power supply comprising a bias stage, an output stage and a capacitor, the output stage including a complementary pair of MOS transistors, wherein the voltage supplied at an output of the power supply is taken from a junction between the complementary pair of MOS transistors, the capacitor being electrically connected between the junction and a reference potential; a plurality of transistors connected between the terminal and the output of the power supply, the plurality of transistors including at least one NMOS transistor and at least one PMOS transistor; control circuitry for driving a gate of each of the at least one NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each of the at least one PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the plurality of transistors in an ohmic region of operation when on-die termination is enabled; wherein the voltage at the output of the power supply is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.