Patent ID: 9082837
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor fabrication process comprising: forming a plurality of split-gate structures over one or more first substrate areas of a wafer, each split-gate structure comprising a sacrificial poly select gate, a nanocrystal stack, and a recessed control gate formed adjacent to the nanocrystal stack with an upper surface which is recessed below an upper surface of the sacrificial poly select gate; forming a plurality of sacrificial transistor gate structures over one or more second substrate areas of the wafer, each sacrificial transistor gate structure comprising a sacrificial poly gate having an upper surface with is substantially coplanar with the upper surface of the sacrificial poly select gate; forming a planarized dielectric layer over the wafer which protects at least the recessed control gate in each split-gate structure and which exposes at least the upper surface of the sacrificial poly select gate and each sacrificial poly gate; selectively removing at least the sacrificial poly select gates and the sacrificial poly gates to form a plurality of gate electrode openings in the planarized dielectric layer without removing any recessed control gate; and forming a plurality of high-k metal gate electrodes in the plurality of gate electrode openings while protecting each recessed control gate in each split-gate structure with the planarized dielectric layer, thereby forming high-k metal select gates to replace the sacrificial poly select gates in the plurality of split-gate structures.