Patent ID: 6924669
Filing Date: 2005-08-02
Classification: H03K

Abstract:
1. An output buffer circuit comprising: a first drive circuit, connected to an output terminal, for receiving an input signal and generating a first output signal having a first state indicative of one of a high logical level and a low logical level, wherein the first drive circuit includes a first output transistor connected between a first power supply and the output terminal and a second output transistor connected between a second power supply and the output terminal, wherein the first and second output transistors generate the first output signal; a second drive circuit connected to the output terminal, wherein the second drive circuit generates a second output signal, and wherein the second drive circuit includes a third output transistor connected between the first power supply and the output terminal and a fourth output transistor connected between the second power supply and the output terminal, the third and fourth output transistors having lower impedances than the first and second output transistors; a first control circuit, connected to the second drive circuit, for generating a first control signal for driving the second drive circuit on the basis of the input signal and a delay signal which is generated by adding a predetermined delay to the first output signal such that the second drive circuit generates the second output signal having the first state; and a second control circuit, connected to the first drive circuit, for inverting the input signal to generate second and third control signals respectively supplied to the first and second output transistors, wherein the first control circuit generates the first control signal and a fourth control signal that have phases opposite to a phase of the input signal and are respectively supplied to the third and fourth output transistors.