Patent ID: 6934206
Filing Date: 2005-08-23
Classification: H01L

Abstract:
1. A structure for electrical testing during the manufacturing of a DRAM integrated circuit comprising: a first region on a silicon substrate designated for a functional section of said integrated circuit; a second region on a silicon substrate designated for said structure; first semiconductor devices formed in said first region, said semiconductor devices comprising first words lines in addition to first activating bit lines in addition to first non-activating bit lines; second semiconductor devices formed in said second region, said semiconductor devices comprising second word lines in addition to second bit lines, said second word lines patterned over said semiconductor devices in a layout identical to that of first word lines in said first region, said second bit lines provided in a repetitive sequence of four bit lines each sequence comprising an activating bit line, a dummy bit line, a non-activating bit line and a dummy bit line, said second word lines patterned in said second region over said semiconductor devices in a layout identical to that of first word lines in said first region, said second bit lines being exposed bit lines in a pattern that is perpendicular with a pattern of said first bit lines; a first contact pad formed at the ends of a plurality of said first and second word lines; a second contact pad formed at the ends of a plurality of said activating first bit lines of said first semiconductor devices; a first probe pad connected to said non-activating bit lines provided to said first semiconductor devices formed in said first region; and a second probe pad connected to said non-activating bit lines provided to said second semiconductor devices formed in said second region.