Patent ID: 6255855
Filing Date: 2001-07-03
Classification: G11C,H03K,H03M

Abstract:
An integrated circuit, comprising:a decoder having an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal;said decoder having three operating states including a first operating state for generating a first potential at said output terminal, a second operating state for generating a second potential at said output terminal, and a third operating state for generating a third potential at said output terminal; the second potential lying between the first potential and the third potential;said decoder including:a first transistor being of a first conductivity type, having a control terminal connected to said third terminal of said decoder and having a drain-to-source path;a second transistor being of a second conductivity type, having a control terminal connected to said fourth terminal of said decoder and having a drain-to-source path;a third transistor being of the second conductivity type, having a control terminal connected to said fifth terminal of said decoder;a fourth transistor having a control terminal connected to said fourth terminal of said decoder and having a drain-to-source path for connecting said output terminal of said decoder to the second potential; anda series circuit connected between said first terminal of said decoder and said second terminal of said decoder, said series circuit including said first transistor, said second transistor, said third transistor, and a node connected to said output terminal of said decoder and between said first transistor and said second transistor.