Patent ID: 8793095
Filing Date: 2014-07-29
Classification: G01R,G06F

Abstract:
1. A system on a chip (SoC), comprising: a first interconnect fabric; a second interconnect fabric; a fabric-to-fabric bridge coupled to each of the first and second interconnect fabrics; a Test Access Mechanism (TAM), having at least a portion thereof including a test controller implemented in the fabric-to-fabric bridge; a first intellectual property (IP) block, operatively coupled to the first interconnect fabric; and a second IP block, operatively coupled to the second interconnect fabric, wherein the TAM is configured to receive test input from an external tester corresponding to one or more tests to be performed on the first IP block and send corresponding test data and/or test commands for testing the first IP block over the first interconnect fabric via the fabric-to-fabric bridge.