Patent ID: 6242342
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A fabrication method for a borderless via, the method comprising the steps of:providing a substrate with a first dielectric layer;sequentially forming a conductive layer, a barrier layer and a metal layer on the dielectric layer;forming a first photoresist pattern to cover the metal layer to define a pattern for a metal plug;etching the metal layer to form the metal plug while using the barrier layer as an etching end point and the first photoresist pattern as an etching mask;forming a second photoresist on the substrate to define a pattern for a conductive line;etching the barrier layer and the metal layer to form a conductive line while using the first photoresist pattern and the second photoresist pattern as etching masks;removing the first photoresist pattern and the second photoresist pattern; andforming a second dielectric layer to enclose the metal plug, the barrier layer and the conductive line.