Patent ID: 7518925
Filing Date: 2009-04-14
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array including a plurality of word lines arranged in parallel to each other, a plurality of drain lines and source lines arranged alternately across the word lines, and a plurality of nonvolatile memory cells arranged at intersections of the word lines, the drain lines and the source lines, each of the memory cells having a control gate electrode, a drain electrode and a source electrode, each electrode being connected to a corresponding one of the word lines, the drain lines and the source lines, and the drain lines being connected to a first potential; a select circuit which selects source lines designated by a select signal from among the plurality of the source lines and connects the selected source lines to data lines respectively; a charge circuit which charges the selected source lines by connecting the data lines to a second potential for a predetermined length of time when a data read operation is initiated; a data output circuit which reads and holds data from a nonvolatile memory cell corresponding to the selected source lines, based on quantities of current flowing in the data lines after the predetermined length of time has elapsed; and a discharge circuit which discharges charges of the selected source lines by connecting the data lines to the first potential after reading the data from the nonvolatile memory cell.