Patent ID: 8164955
Filing Date: 2012-04-24
Classification: H01L

Abstract:
1. A NOR flash memory device comprising: a gate on a semiconductor substrate, the gate comprising: first polysilicon patterns spaced apart by a predetermined interval, and providing floating gates, a dielectric film on the first polysilicon patterns, and a second polysilicon pattern aligned over the first polysilicon patterns and on the dielectric film, and providing a control gate for the floating gates; a plurality of electrodes in a line form, each electrode provided in the semiconductor substrate at the interval between adjacent first polysilicon patterns; and contacts for the plurality of electrodes, the contacts provided at an end region on each electrode; wherein the dielectric film comprises an oxide-nitride-oxide (ONO) film configured of a stack of a first oxide film, a nitride film, and a second oxide film, wherein a portion of the first oxide film contacting the plurality of electrodes is thicker than a portion of the first oxide film contacting the first polysilicon patterns, wherein the portion of the first oxide film contacting the plurality of electrodes has a thickness of about 250˜300 Å.