Patent ID: 6098164
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A microcomputer comprising:a memory;a peripheral circuit including a data generating circuit for generating data, the data generating circuit latching the data in response to a data latch signal and outputting the latched data therefrom in response to a first read control signal, and a data latch signal generating circuit supplied with the first read control signal so as to generate the data latch signal, said data latch signal having a signal time width which is shorter than that of the first read control signal; anda central processing unit connected to said memory and said peripheral circuit through a common bus, said central processing unit outputting an address signal for specifying said peripheral circuit and the first read control signal to said common bus to access said peripheral circuit, and outputting an address signal for specifying said memory and a second read control signal, having a signal time width which is shorter than the first read control signal, to said common bus to access said memory.