Patent ID: 6709922
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device including a memory cell array in which nonvolatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns, the method comprising the following steps (a) to (k):(a) forming an element isolation region on the surface of a semiconductor layer; (b) forming a first gate insulating layer and a laminate having a first conductive layer for a word gate disposed over the first gate insulating layer on the semiconductor layer, the laminate having a plurality of openings extending in a first direction; (c) forming second gate insulating layers on the semiconductor layer so as to be adjacent to both sides of the first gate insulating layer; (d) forming side insulating layers on both sides of the first conductive layer for the word gate; (e) forming a second conductive layer over the entire surface of a structure formed by the steps (a) to (d) so as to cover the structure; (f) forming a first mask layer on the second conductive layer at least in a region in which a common contact section is formed; (g) forming a control gate and a common contact section which comprises: anisotropically etching the entire surface of the second conductive layer to form first and second control gates in the shape of sidewalls continuous in the first direction on either side of the side insulating layers, and to form a contact conductive layer at least in a region in which the common contact section is formed; and forming the contact conductive layer continuously with a pair of the first and second control gates adjacent in a second direction which intersects the first direction; (h) doping the semiconductor layer located between the first and second control gates with impurities, and forming an impurity diffusion layer which forms a source region or a drain region; (i) forming an insulating layer which covers the first and second control gates; (j) forming a second mask layer in a region in which the common contact section is formed; and (k) patterning the first conductive layer for the word gate.