Patent ID: 8884676
Filing Date: 2014-11-11
Classification: H03K

Abstract:
1. A clock generating circuit arrangement for providing at an output terminal, a square wave signal having the same recurrence frequency as the recurrence frequency of an input signal and wherein said square wave signal exhibits a predetermined duty cycle, said circuit arrangement comprising: an oscillator configured to produce an output having both rising and falling edges sequentially, wherein the output is configured to supply an input clock Fin to the clock generating circuit arrangement; a first one shot having an input coupled to the output of the oscillator, wherein the one shot is comprised of an AND gate and an inverter, wherein the one shot is configured to produce an output pulse on its output in response to the rising edge of the oscillator output, and wherein the width of the output pulse corresponds with the delay provided by the inverter included in the one shot; a second one shot, wherein the one shot is comprised of an AND gate and an inverter, wherein the one shot is configured to produce an output pulse on its output in response to the rising edge of the oscillator output, and wherein the width of the output pulse corresponds with the delay provided by the inverter included in the one shot; a two input OR gate wherein the first input is coupled to the output of the first one shot and the second input of the OR gate is coupled to the output of the second one shot; a bi-stable D type flip-flop having data D, and power on POR clock inputs, Q and inverted Q outputs, wherein the output of the two input OR gate is coupled with the clock input of the D type flip-flop and the inverted Q output of the D type flip-flop is coupled to the data D input of the D type flip-flop; wherein the Q output of the D type flip-flop is configured to supply an output clock Fout, also wherein the D type flop-flop is configured to initialize the Q output Fin to a logical “1” when a power on signal pulse is applied to the POR input of the D type flip-flop; a P type transistor having a source, drain and gate; an first N type transistor having a source, drain and gate, wherein the gates of the P and N type transistors are coupled together and also to the inverted Q output of the D type flip-flop and also wherein, the drains of the P and N type transistors are coupled together; a first current source coupled to the source of the P type transistor; a second current source coupled to the source of the N type transistor, wherein the first and second current sources are equal; the first current source is coupled to the upper supply rail (VDD) and the second current source is couple to the lower supply rail (Ground); a comparator having a positive input, a negative input and an output, wherein the output of the comparator is coupled to the input of the second one shot; a voltage reference coupled between the negative input of the comparator and lower supply rail; a third current source coupled between upper supply rail and the positive input of the comparator and the two drains of the N and P type transistors; a second N type transistor having a source, drain and gate, wherein the gate is coupled to the output of the first one shot, the source is coupled to the lower supply rail and the drain is coupled to the positive input of the comparator; and finally a capacitor which is coupled between the source and the drain of the second N type transistor.