Patent ID: 6469946
Filing Date: 2002-10-22
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory cell block including a plurality of memory cells placed at individual intersection points of a plurality of word lines and a plurality of bit lines that are arranged in a matrix fashion; an inter-bit-line interference suppression circuit connected to the plurality of bit lines, for releasing potentials of bit lines adjacent to a memory cell whose data is to be read among the memory cells of said memory cell block, thereby suppressing electrical interference between the bit lines; means for precharging, before reading data stored in a memory cell to be tested, at least bit lines adjacent to a bit line corresponding to the memory cell to be tested among the plurality of bit lines; test memory cell selector for asserting a word line of the memory cell to be tested that is connected to a bit line between, the bit lines precharged by said means for precharging; and a decision circuit for deciding as to whether said inter-bit-line interference suppression circuit operates normally or not in response to the data stored in the memory cell to be tested or to potential changes of the bit lines precharged.