Patent ID: 7132341
Filing Date: 2006-11-07
Classification: G11C,H01L

Abstract:
1. A method of fabricating a semiconductor integrated circuit device, comprising the steps of: (a) forming an isolating element in a semiconductor substrate; (b) forming a first insulating film on the semiconductor substrate; (c) forming a conductive film on said first insulating film and said isolating element, the conductive film having a width of 0.18 μm or less; (d) forming first semiconductor regions in said semiconductor substrate self-aligned with said conductive film; (e) forming second insulating films on side surfaces of said conductive film; (f) forming second semiconductor regions, having a greater impurity concentration than that of said first semiconductor regions, in said semiconductor substrate, self-aligned with said second insulating films; (g) removing the top of said semiconductor substrate to 1 nm–2 nm below the surface of said semiconductor substrate by Ar sputter-etching, and removing the top of said conductive film to 1 nm–2 nm below the surface of the conductive film by Ar sputter-etching; and h) forming cobalt silicide layers in said surface of said semiconductor regions and said conductive film, wherein said cobalt suicide layers are not in contact with junctions formed by said first semiconductor regions and said semiconductor substrate, and wherein said cobalt silicide layers are positioned such that current leakage between said silicide layers and junctions formed by the first semiconductor regions and said semiconductor substrate is prevented.