Patent ID: 6775749
Filing Date: 2004-08-10
Classification: G06F

Abstract:
A computer system comprising:a plurality of caches; a plurality of cache controllers, wherein each cache controller is coupled to control a respective one of the caches; a memory coupled to provide data to each of the caches; and a cache coherency mechanism coupled to the cache controllers and the memory, wherein the cache coherency mechanism is configured to receive a request to provide a copy of data from the memory to a first cache; wherein in response to receiving the request, the cache coherency mechanism is configured to send a probe to a first set of the cache controllers, wherein each of the first set of cache controllers is configured to determine whether its cache contains the data in response to receiving the probe; wherein if a first number of clock cycles have elapsed after the probe was sent, the cache coherency mechanism is configured to provide a speculative response to the request before all of the first set of cache controllers have responded to the probe.