Patent ID: 7516301
Filing Date: 2009-04-07
Classification: G06F

Abstract:
1. A computing system comprising: a first processor configurable to operate in any one of a plurality of modes including a native mode and a compatible mode, the first processor including a pipemode register configured to store a value indicating which one of the modes is currently selected; and a second processor communicably coupled to the first processor and configurable to operate in any one of a plurality of modes including a native mode and a compatible mode, the second processor including a pipemode register configured to store a value indicating which one of the modes is currently selected, the second processor having a design that differs in at least one respect from a design of the first processor in that a bug fix is present in the design of the second processor but not in the design of the first processor, the bug fix being disabled when the processor is configured to operate in the compatible mode, wherein the computing system is configurable such that the first processor and the second processor cooperate to perform a distributed processing task and wherein: