Patent ID: 9110789
Filing Date: 2015-08-18
Classification: G06F,G11C

Abstract:
1. A method of applying an address space in a non-volatile solid-state storage executed by a processor, comprising: receiving user data for storage in the non-volatile solid-state storage; translating a first address of a portion of the user data in a first address space, to a second address of the portion of the user data in a second address space, wherein addresses in the second address space have a range, the range of the addresses in the second address space is greater than a maximum number of addresses in the second address space expected to be applied during a lifespan of the non-volatile solid-state storage; and storing the portion of the user data in the non-volatile solid-state storage, with the portion of the user data associated with both the first address and the second address, wherein the second address space is one of a logical address space or a virtual address space.