Patent ID: 6334183
Filing Date: 2001-12-25
Classification: G06F

Abstract:
A system having an execution unit for performing instructions upon data, the execution unit configured to read operand data from registers and to provide result data to registers, the system comprising:a register file comprising a first plurality of registers including a first register having a first number of bits, a second register having a second number of bits, and a third register having a third number of bits;a pending file comprising a second plurality of registers, the pending file comprising at least one register corresponding to the first register, at least one register corresponding to the second register, and at least one register corresponding to the third register;a bypass multiplexer configured to select a first operand either from the first register or from one of the at least one register corresponding to the first register in the pending file, and further configured to select a second operand either from the second register or from one of the at least one register corresponding to the second register in the pending file;an execution unit, configured to perform an operation upon a portion of the first operand and upon a portion of the second operand, the execution unit further configured to provide a result having a number of bits no greater than the number of bits of the third register; andan output multiplexer configured to receive all of the bits of the execution unit result, the output multiplexer further configured to select a third operand either from the third register or from one of the at least one register corresponding to the third register in the pending file, the output multiplexer further configured to select a portion of the third operand having a number of bits equal to the difference between the number of bits in the third register and the number of bits in the execution unit result, the output multiplexer further configured to provide an output multiplexer output comprising the selected portion of the third operand and the execution unit result, the multiplexer output configured to provide the output multiplexer output to one register in a group comprising of the third register and the at least one register corresponding to the third register in the pending file.