Patent ID: 8064269
Filing Date: 2011-11-22
Classification: G06F,G11C,H04L

Abstract:
1. A memory device comprising: a majority detection unit to determine, with respect to an operative output of data stored in the memory device, whether a plurality of data bits have more one bits or more zero bits and to generate a data bit inversion signal representative of the determination, the plurality of data bits being a subset of bits representing the data; a driver unit arranged to operatively receive the plurality of data bits and the data bit inversion signal and to operatively provide, based on the data bit inversion signal, the plurality of data bits or an inversion of the data bits to a pre-charging unit prior to output of the data from the memory device; and a data bit inversion node coupled to the majority detection unit to transmit the data bit inversion signal externally from the memory device to another device.