Patent ID: 6627945
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A non-volatile memory device comprising:a semiconductor substrate, wherein the substrate has a pair of trenches therein, and wherein the substrate has a source and a drain therein; a tunnel oxide on a top substrate surface of the substrate; a pair of insulators; a pair of floating gates over the tunnel oxide and between the insulators, wherein the pair of floating gates are not directly electrically coupled to each other, wherein the floating gates are each operatively coupled to the source and the drain, and wherein the floating gates have a gap therebetween; an interpoly dielectric over the floating gate, wherein the interpoly dielectric is in contact with the floating gate; and a control gate over the interpoly dielectric, wherein the control gate is in contact with the interpoly dielectric; wherein a channel gate portion of the control gate is located in the gap between the floating gates.