Patent ID: 8531879
Filing Date: 2013-09-10
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a flash memory including a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors; and a memory controller configured to provide the flash memory with a read address that identifies sectors to be read, wherein the flash memory is configured to determine a sequence of even sensing and odd sensing based on the read address and perform the even sensing and the odd sensing according to the determined sequence; and the flash memory is configured to sense data of at least one identified sector that includes memory cells connected to the even bitlines during the even sensing and sense data of at least one identified sector that includes memory cells connected to the odd bitlines during the odd sensing, wherein the memory cells connected to the even bitlines are included in a first sector group and the memory cells connected to the odd bitlines are included in a second sector group; and the first sector group includes the at least one identified sector that includes memory cells connected to the even bitlines and the second sector group includes the at least one identified sector that includes memory cells connected to the odd bitlines, wherein the flash memory is configured to compare a number of identified sectors included in the first sector group and a number of identified sectors included in the second sector group and determine the sequence of the even sensing and the odd sensing according to a result of the comparison.