Patent ID: 8209565
Filing Date: 2012-06-26
Classification: G06F

Abstract:
1. A data processing device comprising: a computing circuit that accesses a peripheral device connected thereto via an internal bus; an internal bus connection circuit, provided between the computing circuit and the internal bus, that selectively switches an enable state and a disable state of an access from the computing circuit to the internal bus; an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error having occurred in the peripheral device; and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel a disablement of the access from the computing circuit to the internal bus in accordance with a start of an exception processing based on the exception occurrence notification signal, wherein the exception processing is performed by retrieving an exception processing program stored in the peripheral device through the internal bus for the computing circuit and executing the exception processing program.