Patent ID: 6630392
Filing Date: 2003-10-07
Classification: H01L

Abstract:
A method for fabricating a flash memory device, comprising the steps of:forming in sequence a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) layer, a control gate, and a hard mask nitride layer on a silicon substrate; patterning in sequence the hard mask nitride layer, the control gate, the ONO layer, and the floating gate; forming a sealing nitride layer on a lateral side of the patterned structure to obtain a resultant structure; forming a spacer by depositing a first insulating layer on the entire resultant structure and then selectively patterning the first insulating layer; forming in sequence second, third and fourth insulating layers on the entire resultant structure including the spacer; forming a photo resist pattern on the fourth insulating layer in order to define a metal contact area; forming a contact hole exposing a portion of the silicon substrate by selectively patterning the fourth, third and second insulating layers through the photo resist pattern; and performing oxidation on the entire resultant structure including the contact hole.