Patent ID: 6715066
Filing Date: 2004-03-30
Classification: G06F

Abstract:
For producing from input signals representing an input data word and a mask word an output signal representing an output data word, the input and output data words comprising N data units Dn, and Zn, respectively, where n=0, 1, 2, . . . , Nâˆ’1, the mask word comprising, for each data unit Dn in the input word and thereby for the corresponding data unit Zn in the output word, a separate mask bit Mn associated therewith that assumes one of a right-indicating value and a left-indicating value, a centrifuge circuit comprising a control module configured to generate, for each mask bit Mn such that nn of mask bits Mk such that k>n that have the left-indicating value and further comprising a shifter module, responsive to the mask word and the right-sum outputs, to provide, for each n such that mask bit Mn that has the right-indicating value, the input word's data unit Dn as the output word's data unit Zd, where d=n+Rn, wherein:A) the shifter module comprises, for each data unit Zn in the output data word, a respective shift column Cn associated therewith and thereby with the respective mask bit Mn and the respective data unit Dn in the input data word, each shift column Cn generating the respective data unit Zn and including a right series of J shift elements Sj, where 1&lE;j&lE;J, each shift element Sj being connected to receive a respective pass input, providing a respective shift-element output, and being associated with a respective shift value sj such that, for j<J,sj+1>&Sum;k=1J&it;sk;B) in the right series of each shift column Cn: i) shift element S1 receives Dn as its pass input if mask bit Mn has the right-indicating value; ii) each other shift element Sj receives as its pass input the output of shift element Sjâˆ’1 in the same series; C) in the right series of each shift column Cn of at least a plurality of the shift columns, each shift element Sj of a plurality of the shift elements includes a multiplexer that: i) receives as its shift input: a) if j=1, the input word's data unit Dd if mask bit Md has the right-indicating value, where d=nâˆ’sj; and b) if j>1, the shift-element output of the shift element Sjâˆ’1 in the right series of column Cd, where d=nâˆ’sj; ii) makes a choice between its inputs in accordance with the value of Rd, where d=nâˆ’sj; and iii) forwards its input thus chosen as shift element Sj's output; D) for each n, the sum of the shift values sj associated with the multiplexers that choose their shift inputs in response to Rn is Rn; and E) for each n such that n&gE;Nâˆ’RT, where RT is the total number of bits in the mask word having the right-indicating value, the shift module provides as Zn the output of the shift module SJ in the right series of shift column Cn.