Patent ID: 6248675
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method for fabricating a field effect transistor having a gate dielectric with a high dielectric constant and having a gate electrode, the method including the steps of:A. fabricating said field effect transistor to have a drain and a source, and to have a sacrificial gate dielectric and a dummy gate electrode, wherein any fabrication process using relatively high temperature is performed with said field effect transistor having said sacrificial gate dielectric and said dummy gate electrode;B. etching said dummy gate electrode and said sacrificial gate dielectric from said field effect transistor to form a gate opening having a sidewall of insulator material and having a bottom wall of a channel region of said field effect transistor;C. depositing a layer of dielectric with high dielectric constant on said side wall and said bottom wall of said gate opening;D. depositing a crystallization enhancing layer on said layer of dielectric with said high dielectric constant on said bottom wall of said gate opening;E. depositing amorphous gate electrode material into said gate opening to fill said gate opening after said step D;F. doping said amorphous gate electrode material in said gate opening with an N-type dopant using a low energy implantation process when said field effect transistor is an N-channel field effect transistor, and doping said amorphous gate electrode material in said gate opening with a P-type dopant using a low energy implantation process when said field effect transistor is a P-channel field effect transistor; andG. annealing said amorphous gate electrode material in said gate opening after said step F at a relatively low temperature using an enhanced crystallization process to convert said amorphous gate electrode material into polycrystalline gate electrode material;and wherein said crystallization enhancing layer, disposed between said layer of dielectric with said high dielectric constant and said amorphous gate electrode material, promotes crystallization of said amorphous gate electrode material into said polycrystalline gate electrode material such that said enhanced crystallization process is performed at a lower temperature than for a solid phase crystallization process without use of said crystallization enhancing layer.