Patent ID: 6582581
Filing Date: 2003-06-24
Classification: C23C,H05K,Y10S

Abstract:
A method for the formation of a multilayer circuit board using selective electroplating procedures, said method comprising the steps of providing a first layer having segregated metal areas contained within an electrically non-conducting organic coating disposed over a conductive support, said segregated metal areas being in electrical communication with a plating electrode through said conductive support, applying a coating of a poor conductor of electricity over said layer, applying a dielectric coating thereover, forming recesses in said dielectric coating that define areas to be electroplated, at least a portion of each of said recesses being in electrical communication with the metal areas in the first layer, converting said poor conductor to a conductive material, electroplating metal into said recesses and repeating said process to form the desired number of layers in said multilayer board.