Patent ID: 6856176
Filing Date: 2005-02-15
Classification: G11C,H01L,H03K

Abstract:
1. An apparatus for providing an input output from an integrated circuit, the apparatus comprising: an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices coupled between a power supply (V a lower pair of N-channel MOS devices (NMOS), coupled between the I/O pad and a ground potential; a first bias circuit providing a first bias voltage to the first upper PMOS device when the I/O pad is in an output mode and V a second bias circuit providing a second bias voltage to the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit providing a first fixed voltage to the second upper PMOS device when V a fourth bias circuit providing a second fixed voltage when V