Patent ID: 6645866
Filing Date: 2003-11-11
Classification: H01L,Y10S

Abstract:
A trench isolation method comprising:forming a trench in a semiconductor substrate including, forming a pad insulating layer on the semiconductor substrate, forming a photoresist pattern on the pad insulating layer, the photoresist pattern being formed to have a width of the isolation layer, etching the pad insulating layer and the semiconductor substrate using the photoresist pattern as a mask to form the trench in the semiconductor substrate, and removing the photoresist pattern; forming an isolation layer in the trench including, forming a thermal oxide film on the inner wall of the trench, forming a nitride liner on the thermal oxide film, forming a dielectric layer on the semiconductor substrate to fill the trench on which the nitride liner is formed, planarizing the surface of the semiconductor substrate having the dielectric layer using the nitride liner as a planarization stop layer by a chemical mechanical polishing method using a slurry containing abrasives of the ceria family, removing the nitride liner exposed by the planarization, and removing the pad insulating layer; and annealing the semiconductor substrate, having the isolation layer, in a hydrogen atmosphere.