Patent ID: 6242782
Filing Date: 2001-06-05
Classification: H01L

Abstract:
An integrated circuit comprising:a semiconductor substrate having a plurality of field-effect transistors formed directly therein and interconnected into a circuit,a first of the transistors having first and second active areas and a gate forming a first channel and coupled to others of the transistors in the circuit,a second of the transistors having third and fourth active areas and a gate forming a second channel and coupled to others of the transistors in the circuit, the third active area being disposed adjacent the second active area,a third of the transistors sharing the fourth active area with the second transistor and having a fifth active area and a gate forming a third channel and coupled to others of the transistors in the circuit;an isolation gate for forming an isolation channel between the second and third active areas, the isolation gate being coupled to a voltage such that the isolation gate always reverse biases the isolation channel, the isolation channel having the same structure as at least one of the first, second, and third channels.