Patent ID: 8492213
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A method for forming a transistor, comprising: providing a semiconductor substrate having a semiconductor layer being formed thereon the semiconductor layer and the semiconductor substrate having different crystal orientations; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the semiconductor substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, the interlayer dielectric layer being substantially flush with the dummy gate structure; removing the dummy gate structure and a first portion of the semiconductor layer that is beneath the dummy gate structure to form an opening in the interlayer dielectric layer and in the semiconductor layer to expose a second portion of the semiconductor layer on the semiconductor substrate and to expose a surface of the semiconductor substrate at a bottom of the opening, wherein the exposed second portion of the semiconductor layer is between the source region and the drain region and the exposed second portion of the semiconductor layer has the different crystal orientation than the underlying semiconductor substrate; and forming a metal gate structure in the opening.