Patent ID: 6537879
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A process for fabricating non-volatile memory cells on a semiconductor substrate comprising:forming at least one stacked structure comprising a first polysilicon layer isolated from the semiconductor substrate by an oxide layer; cascade etching the first polysilicon layer, the oxide layer, and the semiconductor substrate to define a floating gate for at least one memory cell and to define at least one trench bordering the floating gate; filling the at least one trench with an isolation layer; depositing a second polysilicon layer on the first polysilicon layer and the isolation layer; and etching the second polysilicon layer to expose the floating gate defined by the first polysilicon layer, and to form extensions defined by the second polysilicon layer that are substantially coplanar with and adjacent the floating gate, the extensions having a thickness that is substantially equal to a thickness of the floating gate.