Patent ID: 6433595
Filing Date: 2002-08-13
Classification: G06F,H03K

Abstract:
An electronic circuit system manufacturable with a standard CMOS IC wafer process for high speed data transmission up to 10 Gbit/sec data rate, comprising:a plurality of individually adjustable building blocks wherein each of the building blocks having a similar circuit topology that comprises: at least a first series of differential pair of transistors, a second series of differential pairs of transistors and a third series of differential pairs of transistors with the first series of differential pair of transistors connected to a ground source, the third series of differential pairs of transistors connected to a power source and the second series of differential pairs of transistors connected in-between in a manner typically of a standard CMOS circuitry; each of the first series of differential pair of transistors, the second series of differential pairs of transistors, and the third series of differential pairs of transistors is provided with an value of an electrically equivalent channel geometry (â€œEECGâ€ ), defined as a ratio between a channel width and a channel length of the respective pairs of transistors, in which at least the value of EECG of one pair of the third series of differential pairs of transistors is selected to be different from the value of EECG of another pair of the third series of differential pairs of transistors; and each of the first series of differential pair of transistors, the second series of differential pairs of transistors, and the third series of differential pairs of transistors is further assigned with an value of common factor (â€œCFâ€ ), defined as a ratio between the value of EECG of each of the respective pair of transistors and the value of EECG of said another pair of the third series of differential pairs of transistors; and whereby each of the plurality of individually adjustable building blocks is so adjusted to a manner until at least one selected pair of transistors from each of the first series of differential pair of transistors, the second series of differential pairs of transistors, and the third series of differential pairs of transistors of each of the plurality of individually adjustable building blocks do not share an identical value of CF to achieve a desirable output signal with an improved characteristics as compared to an output signal produced by an electronic circuit system having at least one selected pair of transistors from each of the first series of differential pair of transistors, the second series of differential pairs of transistors, and the third series of differential pairs of transistors share an identical value of CF respectively for each of the plurality of individually adjustable building blocks.