Patent ID: 6117723
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method of fabricating logic devices, and dynamic random access memory, (DRAM), devices, on the same semiconductor chip, using an integrated fabrication process, comprising the steps of:providing a first region, or a DRAM device region, of a semiconductor substrate, to be used for fabrication of said DRAM devices, and providing a second region, or a logic device region, of said semiconductor substrate, to be used for said logic devices;forming isolation regions in said semiconductor substrate;forming an N well region, in a first portion, of said logic device region of said semiconductor substrate, to be used for P channel, or PFET logic devices;growing a first gate insulator layer on said logic device region;growing a second gate insulator layer on said DRAM device region;depositing an undoped polysilicon layer;patterning of said undoped polysilicon layer, in said logic device region, to form undoped polysilicon gate structures, on said second gate insulator layer;forming a P type, lightly doped source/drain region, in an area of said first portion, of said logic device region, not covered by a first group of undoped polysilicon gate structures;forming N type, lightly doped source/drain regions, in an area of a second portion, of said logic device region, not covered by a second set of said of undoped polysilicon gate structures;forming insulator spacers on said undoped polysilicon gate structures;performing a P type, ion implantation procedure: to form a P type, heavily doped source/drain region, in an area of said first portion of said logic device region, not covered by said first group of undoped polysilicon gate structures, and not covered by the insulator spacers, on said first group of undoped polysilicon gate structures; and to convert said first group of undoped polysilicon gate structures, to P type doped, polysilicon gate structures;performing an N type, ion implantation procedure: to form an N type, heavily doped source drain region in an area of said second portion of said logic device region, not covered by said second set of undoped polysilicon gate structures, and not covered by said insulator spacers, on the sides of said second set of undoped polysilicon gate structures; to convert said second group of said undoped polysilicon gate structures, to N type doped, polysilicon gate structures; and to convert the region of undoped polysilicon layer, in said DRAM device region, to a N type doped, polysilicon layer;forming a metal silicide: on said P type, heavily doped source/drain region; on said N type, heavily doped source/drain region; on said P type doped, polysilicon gate structures; on said N type doped, polysilicon gate structures; and on said N type doped, polysilicon layer, in said DRAM device region;depositing a capping insulator layer;patterning of said capping insulator layer, of said metal silicide layer, and of said N type doped, polysilicon layer, to form DRAM gate structures, in said DRAM device region, comprised of said capping insulator layer, said metal silicide layer, and of said N type doped, polysilicon layer;forming DRAM, N type lightly doped source/drain regions, in areas of said DRAM device region not covered by said DRAM gate structures;forming a first planarized insulator layer;forming a first opening in said first planarized insulator layer, exposing a portion of the top surface of a first DRAM, N type, lightly doped source/drain region, and forming a second opening in said first planarized insulator layer, exposing a portion of the top surface of a second DRAM, N type, lightly doped source/drain region;forming a storage node contact structure, in said first opening, in said first planarized insulator layer, and forming a bit line contact structure, in said second opening, in said first planarized insulator layer;forming a capacitor structure on the top surface of said first planarized insulator layer, overlying, and contacting, the top surface of said storage node contact structure;forming a second planarized insulator layer;forming a via hole, in said second planarized insulator layer, exposing the top surface of said bit line contact structure; andforming a bit line structure, in said via hole, with the bit line structure overlying a portion of the top surface of said second planarized insulator layer.