Patent ID: 7619923
Filing Date: 2009-11-17
Classification: G11C

Abstract:
1. A circuit for reducing current leakage in hierarchical bit-line architectures, the circuit comprising: a sense amplifier having a first plurality of transistors, the sense amplifier coupled to bit-lines of a plurality of memory cells in a memory array, the sense amplifier configured for detecting stored data from one of the plurality of memory cells; an output latch having a second plurality of transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the plurality of memory cells through the logical state of the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.