Patent ID: 7124319
Filing Date: 2006-10-17
Classification: H04L

Abstract:
1. A fault tolerant computing system comprising: two or more processing sets configured to operate in synchronism with one another; a bridge coupled to the two or more processing sets via a plurality of communication links; wherein the two or more processing sets are configured to initiate data transmissions to the bridge in synchronism with one another, wherein the data transmissions are subject to variable delays between different ones of said communication links; a buffer included in said bridge configured to store the data transmissions received from the processing sets for specific time periods to compensate for said variable delays; and a comparator configured to determine whether the data transmissions received from the two or more processing sets into said buffer match each other; wherein the data transmissions between the processing sets and the bridge are structured into packets, wherein at least one of the packets includes a sending time; wherein the buffer is configured to transfer the packet to the comparator within a set time period after said sending time.