Patent ID: 6438700
Filing Date: 2002-08-20
Classification: G06F,Y02D

Abstract:
An ARM coprocessor power reduction system comprising:a first logic component adapted to logically analyze input signals and provide a signal that turns on or off a coprocessor clock based upon the state of instructions in an ARM pipeline; a THUMB bit register coupled to said first logic component; said THUMB bit register adapted to store a logical value of a THUMB bit (TBIT) signal that indicates whether an instruction in an ARM pipeline is operating in a THUMB state or ARM state; an execute register coupled to said first logic component, said execute register adapted to store information associated with an execution stage of said ARM pipeline; a second logic component coupled to said execute register, said second logic component adapted to advance said ARM pipeline; a logic OR component coupled to said second logic component, said logic OR component adapted to transmit a logical one value if an input to said logic OR component is a logical 1 and a logical zero if said input to said logic OR component is a logical zero; and a wait register coupled to said second logic component, said wait register adapted to capture a value of a not wait signal adapted to cause an ARM core to wait or stall for an integer number of memory clock input cycles.