Patent ID: 6392918
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A circuit configuration, comprising:a ferroelectric memory having memory locations supplied with a constant plate voltage; a first bit line pair formed of bit lines each connected to one of said memory locations; a selection and evaluation device connected to said bit lines of said first bit line pair; a second bit line pair formed of bit lines; selection transistors each having a first terminal connected to said selection and evaluation device and a second terminal connected to one of said bit lines of said second bit line pair; and a reference voltage device having two reference locations that can be charged with complementary signals and read into said selection and evaluation device simultaneously for generating a reference voltage for reading and evaluating read signals read from said memory locations, each of said two reference locations connected to one of said bit lines of said second bit line pair and can be read to said selection and evaluation device through a corresponding one of said selection transistors.