Patent ID: 9082856
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. An electronic device comprising: an insulator; a local first gate and a local third gate embedded in the insulator; a first dielectric layer formed over the local first gate, the local third gate and the insulator; a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed; a second dielectric layer formed over the bilayer graphene layer; and a local second gate and a local fourth gate formed over the second dielectric layer, each of the local first, second, third and fourth gates configured to be capacitively coupled to the channel of the bilayer graphene layer; wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer and the local third and fourth gates form at least a second pair of gates to locally control a second portion of the bilayer graphene layer; wherein a top surface of the local first gate, a top surface of the local third gate and a surface of the insulator are planarized such that the top surface of the local first gate and the surface of the insulator are substantially coplanar; wherein the first pair of gates operate as gates of a first transistor and the second pair of gates operate as gates of a second transistor; and wherein the first pair of gates and the second pair of gates provide independent control of a threshold voltage of the first transistor and a threshold voltage of the second transistor, respectively.