Patent ID: 7795667
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A semiconductor memory, comprising: a memory cell array constituted by memory cells, each memory cell having a floating electrode, the memory cells being arranged in a matrix on a semiconductor substrate; a plurality of first trenches formed in said semiconductor substrate, each first trench being formed between adjacent ones of said memory cells along a gate width direction; a plurality of isolating fillers filled in said first trenches; a plurality of second trenches formed in said isolating fillers, each second trench being formed between said floating electrodes of adjacent ones of said memory cells along the gate width direction, and said second trenches being in the shape of a U, wherein a width of the second trenches at a first point above a second point is always at least equal to a width of the second trenches at the second point; and a word line connected to said memory cells, buried in said second trenches and extending along the gate width direction.