Patent ID: 6770534
Filing Date: 2004-08-03
Classification: H01L,Y10S

Abstract:
A method for manufacturing an ultra small size vertical MOSFET device, the method comprising the steps of:a) preparing an SOI substrate including a single crystal substrate, an oxide layer formed upon the single crystal substrate and a first single crystal silicon layer formed upon the oxide layer; b) forming a first silicon conductive layer by doping an impurity of a high concentration into the first single crystal silicon layer; c) forming a second single crystal silicon layer and a second silicon conductive layer on the first silicon conductive layer, wherein the second single crystal silicon layer has the impurity of a low concentration and the second silicon conductive layer has the impurity of a high concentration; d) patterning the second silicon conductive layer and the second single crystal silicon layer vertically into a first predetermined configuration; e) forming a gate insulating layer on the first silicon conductive layer, the second single crystal silicon layer and the second silicon conductive layer; f) carrying out an-annealing process to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source contact, a drain contact and a vertical channel; and g) forming a gate electrode on side walls of the vertical channel, wherein the gate electrode encompasses the channel.