Patent ID: 9105747
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a first trench disposed in a substrate; a second trench disposed in the substrate and separated from the first trench by a first interval; a first cavity disposed in the substrate within the first interval, wherein the first cavity is linked to a first sidewall of the first trench and wherein a second sidewall opposite to the first sidewall of the first trench is not linked to any cavity; a second cavity disposed in the substrate within the first interval, wherein the second cavity is linked to a first sidewall of the second trench and wherein a second sidewall opposite to the first sidewall of the second trench is not linked to any cavity; a dielectric material lining sidewalls and a bottom surface of each of the first cavity and the second cavity; polycrystalline silicon overlying the dielectric material within the first cavity and the second cavity, the polycrystalline silicon filling at least a part of the first trench and at least a part of the second trench; and a gate over a portion of the substrate between the first cavity and the second cavity.