Patent ID: 7711988
Filing Date: 2010-05-04
Classification: G06F

Abstract:
1. A hardware architecture for monitoring memory, comprising: flag means for detecting triggering accesses at small memory regions; table means for detecting triggering accesses at large memory regions; and common entry point means for acting as a gateway for monitoring function; wherein said flag means comprises at least two bits stored in a cache memory for each of one or more small memory regions stored in the cache memory, the bits indicating, for each of the small memory regions, whether a read access is a triggering access and/or whether a write access is a triggering access; wherein the hardware architecture further comprises: a table storing, for each of one or more small memory regions that has been previously cleared from the cache memory, an address of the small memory region and bits indicating whether a read and/or write access of the small memory region is a triggering access.