Patent ID: 6700826
Filing Date: 2004-03-02
Classification: G11C,H01L

Abstract:
A semiconductor apparatus comprising on one semiconductor substrate:a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each including a capacitor having first and second electrodes, and a switching device having a control terminal connected to a corresponding word line among the plurality of word lines, and a current channel connected between the first electrode and a corresponding bit line among the plurality of bit lines, wherein, when the semiconductor apparatus is on a first mode, an OFF potential of the word lines is set to be a first potential, when the semiconductor apparatus is on a second mode, an OFF potential of the word lines is set to be a second potential, and the current channel of the switching device is set in a direction vertical to the semiconductor substrate, wherein the first mode is a normal mode for enabling a writing/reading operation to be executed in each of the memory cells, the first potential is a ground potential of a circuit, the second mode is a data holding mode for executing no writing/reading in the memory cell, and the second potential is a negative voltage lower than the ground potential of the circuit, and wherein each of the memory cells includes a PLED transistor, and a capacitor, and a refreshing operation is executed corresponding to respective data holding times of the first and second modes.