Patent ID: 7492000
Filing Date: 2009-02-17
Classification: H01L

Abstract:
1. A semiconductor memory cell including a split gate cell structure comprising: a substrate; a common source region formed in the substrate; a drain region formed in the substrate; the drain region being separated from the source region by a channel region; a dielectric layer formed on the channel region; a floating gate electrode arranged on the dielectric layer above a first portion of the channel region adjacent the source region; a control gate electrode arranged on the dielectric layer above a second portion of the channel region adjacent the drain region, the floating gate and control gate electrodes being operable to control the channel region; wherein a projecting portion of the control gate electrode extends over an adjacent portion of the floating gate electrode, the projecting portion including an upper portion and a lower portion, located below the upper portion in a vertical direction, and the upper portion having a substantially vertical surface and extending a first distance over the floating gate electrode, the lower portion having a substantially non-vertical surface and extending a second distance over the floating gate electrode, the first distance being less than the second distance, and wherein the upper portion does not extend over the lower portion.