Patent ID: 6566911
Filing Date: 2003-05-20
Classification: H03K

Abstract:
An integrated circuit having an output cell comprising:first, second, third, and fourth complementary field-effect transistor pairs, each pair comprising a p-channel transistor and an n-channel transistor connected at their drains to a drain node, each p-channel transistor having a source coupled to a supply voltage, each n-channel transistor having a source coupled to a reference voltage, the first and second transistor pairs connected in a differential configuration; a first conductive pad electrically connected to the drain nodes of the first and third transistor pairs; a second conductive pad electrically connected to the drain nodes of the second and fourth transistor pairs; and a multimode logic circuit connected to the transistor gates of the first, second, and third transistor pairs, the multimode logic circuit having a first output mode that drives the gates of the first and second transistor pairs to create a differential output signal on the first and second conductive pads with the third and fourth transistor pairs disabled, the multimode logic circuit having a second output mode that drives the gates of the third transistor pair to create a single-ended output signal on the first conductive pad with the first and second transistor pairs disabled.