Patent ID: 9217902
Filing Date: 2015-12-22
Classification: G02F,G09G,H01L

Abstract:
1. An array substrate comprising scan lines, data lines, thin film transistors and storage capacitors; wherein: the storage capacitors are formed by pixel electrodes and common electrodes; gates of the thin film transistors are connected with the scan lines, sources of the thin film transistors are connected with the data lines, drains of the thin film transistors are connected with the pixel electrodes of the storage capacitors, and the thin film transistors each have a horseshoe-shaped structure; in the storage capacitors corresponding to one of the scan lines, capacitance values of the storage capacitors are progressively increased from the middle of the scan line to each of two ends of the scan line at intervals of a predetermined distance, the capacitance values of the storage capacitors within a same predetermined distance are equal to each other, and thereby the capacitance value of the storage capacitor(s) corresponding to the middle of the scan line is smaller than the capacitance value of each of the storage capacitors corresponding to the two ends of the scan line, so that when the data lines input voltage signals, a voltage difference between the pixel electrode(s) of the storage capacitor(s) corresponding to the middle of the scan line and the pixel electrodes of the storage capacitors corresponding to the two ends of the scan line is smaller than a threshold value.