Patent ID: 6101573
Filing Date: 2000-08-08
Classification: G06F,G11C,Y02D

Abstract:
A content addressable memory comprising:(i) a plurality of rows of bit storage and comparison cells within an array of bit storage and comparison cells, each row storing a data word; and(ii) a plurality of bits lines running through said array between corresponding bit storage and comparison cells within adjacent rows for transmitting an input data word from a data word input at one point on said bit lines along said bit lines to each row coupled to said bit lines, said input data word being compared with a respective stored data word by each row to detect a match, that is indicated by a match signal upon a match line for that row; wherein(iii) said array is divided into at least two sections by one or more sets of gating circuits that operate to perform one or more of a) selectively blocking said input data word being transmitted along said bit lines beyond said gating circuits and b) selectively blocking generation of said match signals for at least one section; and(iv) said gating circuits being controlled to block or unblock in response to at least one bit of said input data word.