Patent ID: 6757213
Filing Date: 2004-06-29
Classification: G11C

Abstract:
A synchronous DRAM controller comprising:a control sequencer that outputs a start readout signal to synchronize with a system clock signal, when receiving a read request to an SDRAM (Synchronous Dynamic Random Access Memory) from an internal bus, a start readout operation unit that starts transferring a readout clock signal to the SDRAM, when receiving the start readout signal from the control sequencer, a signal delay path that receives the readout clock signal from the start readout operation unit, delays the signal to transfer it to the SDRAM, and further delays a part of the readout clock signal to transfer it to the control sequencer, and a temporary read data retention unit that receives and temporarily retains a read data taken in and outputted by the SDRAM at each cycle of the readout clock signal through the signal delay path, wherein, when receiving a part of the readout clock signal from the signal delay path, the control sequencer sends a read data storage enabling signal to the temporary read data retention unit, makes the read data retention unit temporarily retain the read data taken in to be synchronized with the readout clock signal, and outputs a read data readout enabling signal in order to output the read data to synchronize with the system clock signal.