Patent ID: 6704833
Filing Date: 2004-03-09
Classification: G06F

Abstract:
A method for transferring data between a memory and a processor in a system that includes a cache, said method comprising the steps of:executing, at the processor, an instruction that includes (i) a specifier of a location in a storage resource local to said processor,(ii) a specifier of an address in said memory, and (iii) a specifier of a size of a data block; providing, from said processor to a controller, a set of control signals indicating (i) said address in said memory, and (ii) said size of said data block; and transferring said data block atomically, by said controller in response to receipt of said set of control signals, between said storage resource and said memory, without said processor having to first request a lock on said memory, wherein said size of said data block is less than or equal to one cache-line size, wherein said address in said memory is naturally aligned, and wherein said memory is updated by a cache-line sized operation.