Patent ID: 8921991
Filing Date: 2014-12-30
Classification: G11C,H01L

Abstract:
1. A discrete three-dimensional memory (3D-M), comprising: a memory-array die comprising a plurality of 3D-M arrays, each of said 3D-M arrays comprising a plurality of vertically stacked memory cells; a peripheral-circuit die comprising at least a peripheral-circuit component for said memory-array die, wherein said peripheral-circuit component is selected from a group consisting of a charge-pump circuit, a page register and a trim-bit circuit; and wherein said peripheral-circuit component is absent from said memory-array die; means for coupling said memory-array die and said peripheral-circuit die; wherein said peripheral-circuit die comprises fewer back-end layers than said memory-array die; and wherein said memory-array die and said peripheral-circuit die are two discrete dice.