Patent ID: 6720238
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A method of manufacturing a multi-layered wafer, comprising the steps:a) providing a first initial wafer (110) comprising silicon and including a first substrate (491) and a first surface layer (401, 402) directly or indirectly on said first substrate; b) providing a second initial wafer (410) comprising silicon, and including a second substrate; c) in and/or on said first surface layer of said first initial wafer, forming at least one layer area (414) surrounded laterally by at least one layer region (403), wherein said at least one layer area respectively has a characteristic layer property thereof different from said at least one layer region; d) forming at least one insulating layer (405) on at least one of an exposed surface of said second initial wafer after said step b) and an exposed surface of said first initial wafer after said step c); e) after said step d), bonding together said first initial wafer and said second initial wafer along a new outer surface of said at least one insulating layer (405); f) after said step e), removing said first substrate (491) of said first initial wafer, to leave said multi-layered wafer including said first surface layer (401, 402), said at least one layer area (414) surrounded laterally by said at least one layer region (403), at least one part of said second initial wafer (410), and said at least one insulating layer (405) so between said at least one layer area (414) surrounded laterally by said at least one layer region (403) and said at least one part of said second initial wafer (410).