Patent ID: 7615846
Filing Date: 2009-11-10
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first semiconductor layer; a second semiconductor layer formed above said first semiconductor layer; a plurality of trench regions, each formed extending from said second semiconductor layer to said first semiconductor layer, formed being spaced from each other, the trench regions including an effective gate trench region having a gate electrode layer formed on an inner wall thereof with a gate insulating film interposed in between and electrically connected to a gate electrode, and a dummy trench region isolated from said gate electrode; and third semiconductor layers formed, on a surface of said second semiconductor layer, orthogonally to the plurality of trench regions and being spaced from each other, and electrically connected to a first electrode layer, the third semiconductor layer having a width W along a direction in which the trench regions extend, in a portion contacting said first electrode layer, satisfying the relation of: where K is a constant, Rspb is a sheet resistance of the second semiconductor layer, Wso is a pitch of said trench regions, F( ) is a predetermined function, and m is a decimation ratio representing a ratio of a number of the effective gate trench region to a total number of said plurality of trench regions.