Patent ID: 8473669
Filing Date: 2013-06-25
Classification: G06F

Abstract:
1. A method of operating a memory system having an array of non-volatile memory cells, the method comprising the memory system: receiving data at a front end of the memory system from a host, wherein the data comprises a plurality of host logical block addresses (LBAs); selecting at least one subarray of a plurality of subarrays in the array in which to execute a host write operation for the received data, wherein each of the plurality of subarrays is associated with a unique, fixed region of host LBA addresses and each of the plurality of subarrays is associated with a separate subarray controller; selecting at least one other subarray of the plurality of subarrays in which to execute a second operation on data already residing in the at least one other subarray; executing the host write operation and the second operation substantially concurrently in the at least one subarray and the at least one other subarray; wherein the plurality of subarrays are arranged in a plurality of memory banks, each memory bank comprising at least two subarrays, and wherein the memory system comprises an activity limit, the method further comprising the front end preventing execution of the second operation upon detection that the activity limit will be exceeded; and wherein the activity limit comprises a maximum number of concurrent host write and second operations that is less than a total number of subarrays of the plurality of subarrays.