Patent ID: 6444919
Filing Date: 2002-09-03
Classification: H01L,H05K

Abstract:
A thin film layer wiring scheme on a substrate comprising:at least two chip connection pads with an inter pad space at a first chip site on a thin film layer: a first chip site first directional wiring line interspersed between the first chip site chip connection pads; at least one wiring interconnection line connecting one of the first chip site chip connection pads with the first chip site first directional wiring line at the first chip site; at least a first chip site second directional wiring line interspersed between the chip connection pads at the first chip site, wherein the first chip site first directional wiring lines and first chip site second directional wiring line are overlapping but not electrically contacting at the first chip site; at least two chip connection pads with another inter pad space at a second chip site on the thin film layer, wherein the at least two chip connection pads at the first chip site are separated from the at least two chip connection pads at the second chip site by a space which is greater than any of said inter pad spaces; a second chip site first directional wiring line interspersed between the second chip site chip connection pads; and at least one chip site interconnection line connecting the first chip site first directional wiring line at the first chip site with the second chip site first directional wiring line at the second chip site, wherein the chip connection pads at a first chip site, the chip connection pads at a second chip site, first and second chip site first directional wiring lines, at least one wiring interconnection line and at least one chip site interconnection line all being located on a single sublayer of the thin film layer.