Patent ID: 6437725
Filing Date: 2002-08-20
Classification: H03M

Abstract:
A circuit for serializing parallel data of N bits, comprising:a first register for storing M bits of the parallel data, M being less than N, the first register being clocked by a first clock; at least one second register other than the first register for storing at least N-M bits of the parallel data, the at least one second register being clocked by at least one second clock which is different in phase from the first clock; at least one third register for storing at least the nth and (nâˆ’1)th bits of parallel data output from the at least one second register, the third register being clocked by at least one third clock which is different in phase from the first and the second clocks; and logic gates for receiving as inputs the n bits of parallel data output from the first register and output from one or both of the at least one second register and the third register to form N serial data.