Patent ID: 6130838
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A nonvolatile semiconductor memory cell array comprising a plurality of unit cell-arrays, wherein each of said unit cell-arrays includes:a first plurality of cell transistors, each one of the first plurality of cell transistors having a control gate, a drain and a source;a second plurality of cell transistors, each one of the second plurality of cell transistors having a control gate, a drain and a source;first and second word lines, wherein the first and second word lines are adjacent one another and wherein the first word line is commonly connected to the control gates of the first plurality of cell transistors and the second word line is commonly connected to the control gates of the second-plurality of cell transistors;a bit line commonly connected to the drains of each of the first and second plurality of cell transistors through a bit line contact; andfirst and second source lines arranged in parallel to one another alongside the bit line, wherein the first source line is connected to a first one of the first plurality of cell transistors through a first source line contact and the first source line is connected to a first one of the second plurality of cell transistors through a second source line contact, and wherein the second source line is connected to a second one of the first plurality of cell transistors through a third source line contact and the second source line is connected to a second one of the second plurality of cell transistors through a fourth source line contact.