Patent ID: 6956780
Filing Date: 2005-10-18
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a bitline sense amplifier adapted to sense-amplify data of a pair of bitlines; a pair of complementary local input/output lines; a pair of column select switches connected between the bitline sense amplifier and the pair of complementary local input/output lines, said column select switches being adapted to respond to a column select signal; a pair of complementary global input/output lines; a pair of write control switches connected between the pair of complementary local input/output lines and the pair of complementary global input/output lines, said write control switches being adapted to respond to a write control signal; and a direct sense amplifier connected to the pair of complementary local input/output lines and the pair of complementary global input/output lines, said direct sense amplifier being adapted to generate a voltage difference, corresponding to a voltage difference between the pair of complementary local input/output lines, between the pair of complementary global input/output lines in response to a read control signal, said direct sense amplifier comprising,