Patent ID: 7242230
Filing Date: 2007-07-10
Classification: G06F,H03L,Y02D

Abstract:
1. A semiconductor chip comprising a clock generation circuit, the clock generation circuit comprising: a) a phase locked loop having an output; b) a first programmable frequency scaling circuit having an input and an output, the input being coupled to the output of the phase locked loop, and the output of the first programmable frequency scaling circuit providing a first clock signal, the first programmable frequency scaling circuit comprising a first programmable divider; c) a second programmable frequency scaling circuit having an input and an output, the input being coupled to the output of the phase locked loop, and the output of the second programmable frequency scaling circuit supplying a second clock signal, the second programmable frequency scaling circuit comprising a second programmable divider; d) at least one control register, said at least one control register having a field specifying a scale factor of the first frequency scaling circuit and a field specifying a scale factor of the second frequency scaling circuit; e) internal circuitry clocked by the first clock signal; f) at least one interface circuit clocked by the second clock signal, the interface circuit adapted to interface to external circuitry; and g) control logic providing control signals to the first programmable divider and the second programmable divider.