Patent ID: 8542170
Filing Date: 2013-09-24
Classification: G09G

Abstract:
1. A display device, comprising: a display panel having an adjustable refresh frequency; a timing controller configured to provide a timing control signal, the timing control signal generated according to the refresh frequency of the display panel, the timing controller comprising a timing signal generator configured to detect a refresh frequency of the liquid crystal panel and generate the timing control signal according to the refresh frequency, in which the timing signal generator comprises a control unit and a digital code converter, the control unit configured to select a timing code from a plurality of pre-stored timing codes in accordance with the refresh frequency and output the selected timing code to the digital code converter, wherein the digital converter is configured to convert the timing code to the timing control signal; and a data driver configured to dynamically adjust a setup time and a hold time of the data driver according to the timing control signal, receive and identify display data of the display device based on the adjusted setup time and the adjusted hold time, and provide driving voltages based on the display data directing the display panel to display images, wherein the timing code is a four-bit digital code and the timing control signal is a two-bit digital code, the digital code converter comprises a first transistor, a second transistor, a third transistor, and a four transistor, gate electrodes of the first to fourth transistors are configured to receive the timing code, drain electrodes of the first and third transistors are both electrically coupled to a digital power voltage, source electrodes of the second and fourth transistors are both grounded, a first resistor and a second resistor are electrically coupled in series between a source electrode of the first transistor and a drain electrode of the second transistor, a third resistor and a fourth resistor are electrically coupled in series between a source electrode of the third transistor and a drain electrode of the fourth transistor, and the timing control signal is output from a node between the first and second resistors and a node between the third and fourth resistors.