Patent ID: 6475866
Filing Date: 2002-11-05
Classification: G11C,H01L

Abstract:
A method for production of a memory cell arrangement, comprising the steps of:forming strip-like trenches which essentially run in parallel in a main area of a substrate which includes at least in a region of the main area semiconductor material which is doped by a first conductivity type, forming MOS transistors which are vertical with respect to the main area of the substrate, the MOS transistors being formed on the sides of the trenches, said MOS transistors functioning as memory cells and have respective first, second and third threshold voltage values depending upon stored information of the respective MOS transistors, and a first memory cell of said memory cells possessing said first threshold voltage value depending upon a thickness of a gate dielectric which differs from a gate dielectric thickness of said MOS transistors not having said first threshold value, a second memory cell of said memory cells having said second threshold voltage value depending upon a second gate dielectric thickness and a channel doping, a third memory cell of said memory cells having said third threshold voltage value depending upon a different channel doping than said channel doping of said second memory cell.