Patent ID: 7180350
Filing Date: 2007-02-20
Classification: G09G,G11C,H03K

Abstract:
1. A hybrid latch flip-flop, comprising: a positive pulse generating unit; a clock input connected to the positive pulse generating unit for applying clock signals to the positive pulse generating unit; a latch flip-flop connected to the positive pulse generating unit, the latch flip-flop comprising a sample unit and a hold unit, an output of the sample unit connected to the bold unit; a buffer unit connected to the hold unit; a data input unit connected to an input of the sample unit for applying input data signals to the sample unit; and a data output connected to the buffer unit for outputting output data signals; wherein the sample unit comprises: three PMOS type transistors, which are a first PMOS type transistor, a second PMOS type transistor, and a third PMOS type transistor; and four NMOS type transistors, which are a first NMOS type transistor, a second NMOS type transistor, a third NMOS type transistor, and a fourth NMOS type transistor, the sources of the three PMOS type transistors being connected to a power source, the gate of the first PMOS type transistor, the gate of the second NMOS type transistor, and the gate of the fourth NMOS type transistor all being connected to an output of the positive pulse generating unit, the gate of the first NMOS type transistor the gate of the second PMOS type transistor being both connected to the data input unit, a node being connected to the drain of the first PMOS type transistor, the drain of the second PMOS type transistor, the gate of the third PMOS type transistor, the gate of the third NMOS type transistor, and the drain of the first NMOS type transistor, the source of the first NMOS type transistor being connected to the drain of the second NMOS type transistor, the source of the third NMOS type transistor being connected to the drain of the fourth NMOS type transistor, the source of the second NMOS type transistor and the source of the fourth NMOS type transistor being connected to ground, the drain of the third PMOS type transistor and the drain of the third NMOS type transistor being connected to the hold unit.