Patent ID: 7701744
Filing Date: 2010-04-20
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of sub-array blocks; and at least one fuse box including a plurality of fuse groups, each fuse group having a plurality of fuses and corresponding to one of the plurality of sub-array blocks, wherein the plurality of fuses of the plurality of fuse groups are arranged intermittently such that the plurality of fuses in the same fuse group are not adjacent to each other, wherein each of the plurality of fuse groups further comprises at least one master fuse, wherein the integrity of the at least one master fuse of a fuse group affects the determination of a fuse mode for a repair operation of a sub-array block corresponding to the fuse group, and wherein the fuse box includes a plurality of master fuses, and a pitch size between the plurality of master fuses is greater than a pitch size between the plurality of fuses in the fuse box.