Patent ID: 7257169
Filing Date: 2007-08-14
Classification: H03M,H04L

Abstract:
1. A receiver for deserializing a stream of consecutive data bits having a bit period, comprising: a single clock which is adapted to generate a first plurality of clock phases; a sample generator which is adapted to sample the stream so as to generate initial data values of each of the consecutive data bits at times defined by the first plurality of clock phases; and digital circuitry which is adapted to: group the initial data values into a second plurality of sampling phase sets, according to the clock phases at which the values were sampled, assign each of the sampling phase sets a respective grade responsive to at least some of the initial data values, select a decoding phase set from the sampling phase sets responsive to the respective grades, and decode the stream responsive to the initial data values of the decoding phase set to generate decoded values of the consecutive bits, wherein the single clock comprises a free-running clock driving a phase locked loop (PLL) oscillator having an oscillation period independent of the bit period.