Patent ID: 6768698
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A semiconductor memory device allowing for data input/output in synchronization with a rise and a fall of an external clock, comprising:a memory cell array storing data; an internal clock generation circuit generating first and second internal clocks respectively corresponding to the rise and the fall of said external clock in synchronization with said external clock; at least one operation clock output circuit receiving said first and second internal clocks and outputting said first and second internal clocks respectively as first and second operation clocks in response to an output enabling signal enabling output of said first and second internal clocks; at least one data output circuit receiving said first and second operation clocks and externally outputting data read from said memory cell array in synchronization with said first and second operation clocks, and a data strobe signal output circuit receiving said first and second internal clocks and said first and second operation clocks and generating and externally outputting a data strobe signal indicative of a timing for externally outputting said read data from said data output circuit based on said first and second internal clocks and said first and second operation clocks.