Patent ID: 6770529
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A method of manufacturing an EDMOS device having a lattice type drift region, comprising the steps of:forming a well region in a given region of a silicon substrate; alternately implanting first impurity ions in a given region of said well region to form a lattice type drift region having a first lattice and a second lattice which are alternately arranged, wherein said first lattice is implanted by said first impurity ions; forming a field oxide film on a given region of said silicon substrate; implanting second impurity ions in said well region to control a threshold voltage; forming a gate insulating film and a polysilicon film on said silicon substrate of said well region, and then patterning said polysilicon film to form a gate electrode; implanting third impurity ions in said well region and said drift region to form a source region and a drain region, respectively; implanting fourth impurity ions in said well region to form a source contact region connected to said source region; forming an insulating film on an entire structure, and then forming contact holes in said insulating film to expose said source region, said drain region and said gate electrode; and forming metal wires connected to said source region, said drain region and said gate electrode via said contact holes, respectively.