Patent ID: 6191608
Filing Date: 2001-02-20
Classification: G06F,H03K

Abstract:
An apparatus to program a plurality of programmable logic devices (PLDs), comprising:a source configured to generate programming data;a second source to generate a clock signal;a first PLD device configured to receive the programming data and the clock signal, the first PLD device further configured to use the clock signal to clock in the programming data to program the first PLD device to a first logic state, the first PLD device further including a done circuit which is configured to generate a done signal when the first PLD device is programmed to the first logic state; anda second PLD device configured to receive the done signal, and in response thereto, is further configured to receive the clock signal and the programming data to program the second PLD device to a second logic state, wherein the second PLD device further includes a program enable input circuit that is coupled to receive the done signal from the first PLD device, the program enable input circuit being configured to prevent the second PLD device from being programmed with the programming data when the done signal from the first PLD device is not asserted, and configured to permit the second PLD device to accept the programming data from the data source when the done signal from the first PLD device is asserted.