Patent ID: 8503325
Filing Date: 2013-08-06
Classification: H04L

Abstract:
1. A packet transfer device that transmits input packets by using a redundancy configuration of plural systems, and selects and outputs packets for one transmission path at a reception side in a packet transfer network, comprising: an uninterruptible-switching memory and a low-delay memory that store packets; a delay unit that delays an input packet by a specified time and outputs a delayed packet to the uninterruptible-switching memory; a packet type identifying unit that refers to a tag added to a received packet to identify which one of an uninterruptible-switching desiring packet, a low-delay desiring packet and a marker packet the received packet corresponds to, transmits received uninterruptible-switching desiring packets, low-delay desiring packets and marker packet to the delay unit, transmits only low-delay desiring packets to the low-delay memory, and extracts and outputs a reception time and identification information of a marker packet when the received packet corresponds to the marker packet; a controller that measures a packet arrival time difference between a 0-system and a 1-system on the basis of the reception time and the identification information of the marker packet informed from the packet type identifying unit, instructs the packet arrival time difference to the delay unit to make uninterruptible-switching desiring packets of the 0-system and the 1-system be in phase with each other and transmits the uninterruptible-switching desiring packets from the delay unit to the uninterruptible-switching memory; and a read-out controller that reads out packets from the uninterruptible-switching memory and/or the low-delay memory and controls packets to be transmitted, wherein the read-out controller reads out a packet from the uninterruptible-switching memory, refers to a tag of the packet read out from the uninterruptible-switching memory to identify which one of an uninterruptible-switching desiring packet, a low-delay desiring packet and a marker packet the read-out packet corresponds to, and transmits the read-out packet when the read-out packet is an uninterruptible-switching desiring packet or a marker packet, and discards the packet read out from the uninterruptible-switching memory, when the read-out packet is a low-delay desiring packet, and further reads out and outputs a packet when the packet is stored in the low-delay memory, wherein when the read-out packet is identified as a low-delay desiring packet, the read-out controller discards the packer read out from the uninterruptible-switching memory, reads out and transmits a packet when the packet is stored in the low-delay memory, and further skips a low-delay desiring packet that precedes a next uninterruptible-switching packet.