Patent ID: 7041569
Filing Date: 2006-05-09
Classification: H01L

Abstract:
1. A method for fabricating a composite capacitor in a semiconductor die, said method comprising steps of: depositing a lower interconnect metal layer; forming an upper electrode of a lower capacitor over said lower interconnect metal layer; patterning said lower interconnect metal layer to form a lower electrode of said lower capacitor; depositing an interlayer dielectric layer over said upper electrode and said lower electrode of said lower capacitor; depositing an upper interconnect metal layer over said interlayer dielectric layer; forming an upper electrode of an upper capacitor over said upper interconnect metal layer; patterning said upper interconnect metal layer to form a lower electrode of said upper capacitor; wherein said lower electrode of said lower capacitor is electrically connected to said upper electrode of said upper capacitor so as to couple said lower capacitor and said upper capacitor in a parallel configuration.