Patent ID: 8990582
Filing Date: 2015-03-24
Classification: G06F

Abstract:
1. A method, comprising: identifying a memory address; obtaining a nonce, wherein the nonce is a fixed-bit size random or pseudorandom number generated, by a trust anchor, for each operation writing data corresponding to the memory address to an L3 cache, wherein the trust anchor manages a first key and at least a second key, wherein the first key and the second key each provide a session key associated, respectively, with a first and a second virtual machine executed on the plurality of processing cores of a central processing unit (CPU), and wherein the first and the second virtual machines are each controlled by a distinct user; generating a keystream using the first key, the nonce, and the identified memory address; encrypting, using the generated keystream, data corresponding to the memory address while being written from a L1 cache to the L3 cache, wherein the L1 cache and an L2 cache are local to one of a plurality of processing cores on the CPU, and wherein the L3 cache is disposed on the CPU and shared by the plurality of processing cores; and writing the nonce to the L3 cache.