Patent ID: 9059286
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method of producing a transistor, said method comprising: forming a base layer on a substrate; forming shallow trench isolation regions extending vertically through said base layer to said substrate; forming a recess in said base layer between said shallow trench isolation regions such that a lower portion of said base layer remains between said shallow trench isolation regions; forming a strain-producing layer in said recess on said base layer and extending laterally between and immediately adjacent to said shallow trench isolation regions; removing at least one portion of said strain-producing layer to create an opening in said strain-producing layer and leave first and second portions of said strain-producing layer on said base layer, said first and second portions of said strain-producing layer comprising source and drain stressor regions of said transistor; growing a channel region in said opening of said strain-producing layer from said base layer; forming a gate insulator on and immediately adjacent to co-planar top surfaces of said channel region and said source and drain stressor regions adjacent to said channel region; forming a gate conductor on said gate insulator after forming said source and drain stressor regions, said channel region, and said gate insulator, said gate conductor being formed so as to be on and immediately adjacent to said gate insulator and further above and vertically overlapping with said source and drain stressor regions such that only said gate insulator is stacked between said source and drain stressor regions and said gate conductor.