Patent ID: 6448613
Filing Date: 2002-09-10
Classification: H01L,Y10S

Abstract:
A field effect transistor, with minimized parasitic Miller capacitance, formed within an active device area of a semiconductor substrate, the field effect transistor comprising:a gate structure formed on a gate dielectric on said semiconductor substrate over a portion of said active device area, said gate structure being doped with a first type of dopant; a drain extension formed within an exposed portion of said active device area of said semiconductor substrate on a drain side of said gate structure, said drain extension having a drain overlap that extends under said gate structure; and a depletion region formed from doping a sidewall of said gate structure at said drain side of said gate structure with a second type of dopant that is opposite to said first type of dopant, said second type of dopant forming said depletion region from said sidewall at said drain side of said gate structure into approximately an edge of said drain overlap that extends under said gate structure to reduce a parasitic Miller capacitance formed by said drain overlap.