Patent ID: 6111786
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A semiconductor non-volatile memory device comprising:a memory cell array divided into plural sectors each having plural addressable memory cells respectively storing data bits in the form of accumulated carrier changing said plural memory cells between different threshold levels;a data write-in circuit for producing a write-in potential used for increasing said accumulated carrier;a first addressing circuit selecting sectors from said memory cell array during a multi-write operation for propagating said write-in potential to said sectors;a second addressing circuit selecting at least one memory cell from each of said sectors selected by said first addressing circuit for propagating said write-in potential to the memory cells selected from said sectors during the multi-write operation;a source line controllers respectively associated with said plural sectors and having respective switching elements connected between the plural addressable memory cells of the associated plural sectors and a discharging line; anda controlling circuit causing the switching elements associated with said sectors selected by said first addressing circuit to turn on in said multi-write operation for discharging electric current from said memory cells to said discharging line.