Patent ID: 6627471
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A method of manufacturing an array substrate having drive integrated circuits, comprising:forming first and second semiconductor layers on a substrate; depositing an insulating material on the first and second semiconductor layers; depositing a metal on the insulating material; forming first photoresist patterns on the metal, the first photoresist patterns being over the first and second semiconductors; forming first and second gate electrodes over the first and second semiconductor layers, respectively, by etching the metal, the first and second gate electrodes being narrower than the first photoresist patterns; forming first and second insulator patterns on the first and second semiconductor layers, respectively, by etching the insulating material, the first and second insulator patterns having substantially the same width to the first photoresist patterns; doping n+ ions by using the first photoresist patterns as a first doping mask; ashing the first photoresist patterns, thereby the first photoresist patterns becoming reduced first photoresist patterns, the reduced first photoresist patterns having substantially the same width as the first and second gate electrodes; etching the first and second insulator patterns by using the reduced first photoresist patterns as an etching mask; doping nâˆ’ ions by using the reduced first photoresist patterns as a second doping mask; removing the reduced first photoresist patterns after the doping nâˆ’ ions; forming a second photoresist pattern, the second photoresist pattern covering the first gate electrode and the first semiconductor layer; doping p+ ions by using the second photoresist pattern and the second gate electrode as a third doping mask; and removing the second photoresist pattern after the doping p+ ions.