Patent ID: 7217619
Filing Date: 2007-05-15
Classification: H01L

Abstract:
1. A method for fabricating memory components, in which a semiconductor body or substrate has a memory layer or memory layer sequence applied to it in a memory region provided for a memory cell array, and a gate dielectric layer for transistors is produced in a logic region provided for an actuation or logic circuit, the method comprising: applying a pad oxide layer over said memory region and said logic region of said substrate; applying a separate sacrificial layer on said pad oxide layer; applying a memory layer or a memory layer sequence that includes a memory layer over the memory region and the logic region; dry etching to completely remove the memory layer or the memory layer of the memory layer sequence in the logic region while leaving at least a residual layer portion of said sacrificed layer; and wet etching to remove said at least a residual layer portion of the sacrificial layer.