Patent ID: 8084859
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A semiconductor device comprising a substrate, and a wafer level chip scale package structure having external terminals, wherein a signal wiring forbidden region on a plane parallel to a substrate principal plane, between a line connecting centroids of adjacent external terminals and an edge of the semiconductor device package, and the semiconductor device comprises signal wiring in the signal wiring forbidden region and dummy wiring on a same wiring layer in a periphery of the signal wiring, wherein the signal wiring forbidden region is a region in a range having a fan angle of 140 degrees from the centroid of the external terminal, a center line of the fan angle being perpendicular to the edge of the semiconductor device package and extending to the centroid on the plane parallel to the substrate principal plane, said region overlaps with a range enclosed by an arc whose center is the centroid of the external terminals and whose radius is 4/5 of a minimum distance to an edge of the external terminals and an arc whose center is the centroid of the external terminals and whose radius is 6/5 of a maximum distance to the edge of the external terminals.