Patent ID: 6101586
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A memory access control circuit for inhibiting a fraudulent access by detecting an access to a region to be protected on a memory, the memory access control circuit comprising:a first address holding means for holding an instruction fetch address indicating a memory location where an instruction to be executed is stored;a second address holding means for holding an address for said region to be protected;a third address holding means for holding an instruction fetch address comprising a memory location of an instruction allowed to access to said region to be protected;an access detecting means for comparing an address of an access destination of an instruction read out from the memory, obtained from the result of a decoding of said read-out instruction, with said address held in said second address holding means, for discriminating whether or not said read-out instruction is an instruction accessing to said region to be protected;a comparing means for comparing said instruction fetch address held in said first address holding means with said instruction fetch address held in said third address holding means only when said access detecting means detects that said read-out instruction is the instruction accessing to said region to be protected, said comparing means outputting an inhibiting signal when said read-out instruction is an instruction read out from a memory address not allowed to access to said region to be protected; andan access inhibiting means responding to said inhibiting signal to inhibit a memory access.