Patent ID: 6360346
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A storage unit having flash memory and integrated error correction placed within one package, comprising:an encoding section for encoding data in 512 bit units with an error correcting code of 20 bits for correcting up to 2 errors within each 512 bit unit; a storage section for storing data encoded by said encoding section; an error correcting section for correcting errors in the encoded data read out from said storage section; comprising: a syndrome generator for generating a syndrome signal calculated on the basis of the encoded data read out from said storage section; a polynomial deriving circuit for deriving an error position polynomial based on said syndrome signal; an error position detecting circuit for detecting an error position based on said error position polynomial and outputting an error position signal indicating the position of errors within each 512 bit unit; a counter for counting the number of errors indicated by said error position signal; a delay circuit for delaying a copy of the encoded data read out from said storage section; and an adder for adding said error position signal to the delayed encoded data thereby correcting errors in the data; and a decoding section for decoding the data corrected by said error correction section.