Patent ID: 6489673
Filing Date: 2002-12-03
Classification: G01R,H01L

Abstract:
A package for a semiconductor die which comprises:(a) a header having a cavity with a floor and sidewalls and a plurality of vertically spaced apart rows along the sidewalls of said cavity, each of said rows including a plurality of spaced apart bond fingers; (b) a selectively replaceable electrically insulating membrane disposed over the floor of said cavity, said membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and interconnect from each of said bumps to a said membrane bond pad; (c) bond wires connected between said membrane bond pads and said bond fingers on said plurality of rows; and (d) a semiconductor die having a plurality of bond pads, each of said bond pads on said semiconductor die each containing one of said bumps on said membrane.