Patent ID: 6362995
Filing Date: 2002-03-26
Classification: G11C

Abstract:
An integrated circuit memory device comprising:an integrated circuit substrate; first and second memory core blocks in the integrated circuit substrate, each including a memory cell array and control circuits that control the memory cell array; a pad block in the integrated circuit substrate including a plurality of pads; an input/output and internal clock signal generation block in the integrated circuit substrate, including a data input/output unit that sends and receives data to and from external of the memory device via the pad block, a command input unit that receives a command input from external of the memory device via the pad block and a delay locked loop circuit that receives an external clock signal from external of the memory device via the pad block and generates internal clock signals; a data shift block in the integrated circuit substrate that sends and receives data to and from the data input/output unit and sends and receives data to and from the first and second memory core blocks in synchronization with the internal clock signals; and an interface logic block in the integrated circuit substrate that receives and analyzes the command output from the command input unit to control the first and second memory core blocks the input/output and internal clock signal generation block and the data shift block; wherein the interface logic block is located in the integrated circuit substrate between the first memory core block and the pad block, and the input/output and internal clock signal generation block and the data shift block are located in the integrated circuit substrate between the pad block and the second memory core block.