Patent ID: 6240045
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A synchronous semiconductor memory device comprising:a reference circuit receiving an external reference clock signal and outputting an internal reference clock signal;a command decoder outputting a decode signal instructing a prescribed internal operation in response to an external control signal;a synchronous control circuit receiving said decode signal and said internal reference clock signal and outputting a synchronous control signal activated synchronously with said internal reference clock signal and inactivated in response to an asynchronous control signal;an asynchronous control circuit for outputting said asynchronous control signal activated asynchronously with said internal reference clock signal, said asynchronous control circuit including an asynchronous delay circuit for generating said asynchronous control signal by delaying said synchronous control signal by a prescribed period;an inhibit circuit receiving said asynchronous control signal and said internal reference clock signal and converting said asynchronous control signal to be synchronous with said internal reference clock signal thereby generating an inhibit signal inhibiting activation of said synchronous control signal; anda storage circuit controlled in response to said synchronous control signal and said asynchronous control signal for transmitting/receiving stored data to/from outside said synchronous semiconductor memory device.