Patent ID: 6458655
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A semiconductor device manufacturing method comprising:a first step of forming on a semiconductor substrate an insulation film and a conductive layer successively; a second step of forming a patterned resist on said conductive layer; a third step of dry-etching said conductive layer, with said patterned resist used as a mask; a fourth step of partially removing a surface layer of said patterned resist; and a fifth step of etching said insulation film, with said patterned resist used as a mask; wherein a state random access memory is manufactured, comprising: a first step of forming an isolating oxide film on a surface of a semiconductor substrate; a second step of depositing a gate oxide film on said semiconductor substrate; a third step of depositing a first polysilicon layer on said gate oxide film; a fourth step of forming a patterned resist having an oepning extending from an active region to said isolating oxide film; a fifth step of dry-etching and thus removing said first polysilicon layer, with said patterned resist used as a mask; a sixth step of partially removing a surface layer of said patterned resist; a seventh step of removing said gate oxide film at a bottom of said pattern, again with said patterned resist used a mask; an eighth step of removing said patterned resist; a ninth step of forming a second polysilicon layer; a tenth step of forming of resist a pattern providing a gate electrode of an access transistor, a pattern providing a gate electrode of a driver transistor and a pattern providing a gate electrode of a transistor for peripheral circuity; an eleventh step of dry-etching said first and second polysilicon layers, with said patterned resist used as a mask; a twelfth step of removing said patterned resist; a thirteenth step of doping only an n region with an n dopant; and a fourteenth step of thermally processing a resultant product.