Patent ID: 8115186
Filing Date: 2012-02-14
Classification: H01L

Abstract:
1. An integrated circuit comprising one or more memory cells, at least one of the one or more memory cells comprising: a first electrode; a dielectric layer formed on the first electrode; an opening in the dielectric layer formed down to the first electrode, wherein an average width of the opening in the dielectric layer is less than a prescribed minimum lithographic dimension; a phase change feature formed on the dielectric layer, a portion of the phase change feature filling the opening in the dielectric layer so that the phase change feature is in direct contact with the first electrode through said opening; wherein at least a portion of the patterned dielectric layer remains in the ultimate memory cell; and a support structure comprising at least one of a glass, a metal, and a polymer, and a catalytic material supported by the support structure, wherein the catalytic material is in contact with the dielectric layer in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material to form said opening in the dielectric layer.