Patent ID: 7609551
Filing Date: 2009-10-27
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor layer; a charge trapping film provided on a first surface of the semiconductor layer; a gate insulating film provided on a second surface opposing the first surface of the semiconductor layer; a back gate provided on the charge trapping film; a front gate provided on the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region which is provided between the drain and the source, the body region being in an electrically floating state, wherein the semiconductor memory device includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the semiconductor memory device is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.