Patent ID: 6383884
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:(a) selectively forming a multilayer structure including a gate insulation film and a dummy gate electrode stacked in the order named on an upper surface of a substrate, said dummy gate electrode having an upper part and a lower part; (b) forming a first insulation film in a side surface of said lower part, wherein said first insulation film is formed by thermally oxidizing said dummy gate electrode in said step (b); (c) forming a pair of source/drain regions in said upper surface of said substrate, with part of said upper surface of said substrate which underlies said gate insulation film lying between said pair of source/drain regions; (d) forming a second insulation film on said upper surface of said substrate overlying said pair of source/drain regions, said second insulation film having a thickness greater than the height of said first insulation film from said upper surface of said substrate, said second insulation film being in contact with said dummy gate electrode; (e) removing said dummy gate electrode while leaving said first insulation film, said step (e) being performed after said step (d); and (f) forming a gate electrode filling a recess defined by said gate insulation film and said first and second insulation films.