Patent ID: 8407704
Filing Date: 2013-03-26
Classification: G06F

Abstract:
1. A method for providing multi-level memory protection, the method comprising: defining a hierarchy of one or more parent processes and their respective child processes, wherein at least one of the child processes is a parent process when the at least one child process includes one or more sub-processes; building a data structure defining access rights of each of the parent processes and their respective child processes in the defined hierarchy, the defining of the access rights including defining permitted memory resources of each respective child process and the access rights of the child process relative to the access rights of the parent process of such child process, the data structure further containing a precomputed logical concatenation of translation functions represented by a plurality of individual translation data structures corresponding to processes at respective levels of the defined hierarchy, for performing address translation from the address view of a process of the processes therein to a physical address; registering the data structure with a processor; and using the data structure for memory protection and to perform address translation, such that each child process has access rights to the memory resources only as permitted in accordance with the data structure, so as to translate between an address view of a current process to the corresponding physical address in accordance with the precomputed logical concatenation of translation functions contained in the data structure.