Patent ID: 6010948
Filing Date: 2000-01-04
Classification: H01L

Abstract:
A method of forming a insulator filled, shallow trench isolation region, for a MOSFET device, on a semiconductor substrate, using a deposited, and reflowed, BPSG layer, to fill shallow trench regions, in said semiconductor substrate, comprising the steps of:forming a capping silicon oxide layer on said semiconductor substrate;forming a silicon nitride stop layer, on said capping silicon oxide layer;forming a shallow trench in said silicon nitride stop layer, in said capping silicon oxide layer, and in said semiconductor substrate;growing a silicon oxide liner on the exposed silicon surfaces of said shallow trench;depositing a BPSG layer, containing between about 4.0 to 4.5 weight percent B.sub.2 O.sub.3, and containing between about 4.0 to 4.5 weight percent P.sub.2 O.sub.5, completely filling said shallow trench;reflowing of said BPSG layer, via a temperature anneal procedure, at a temperature between about 800 to 1200.degree. C.;performing a chemical mechanical polishing procedure to remove said BPSG layer, from the top surface of said silicon nitride stop layer, creating a BPSG filled, shallow trench region;removing said silicon nitride stop layer; andremoving said capping silicon oxide layer.