Patent ID: 7342936
Filing Date: 2008-03-11
Classification: H04L

Abstract:
1. A deficit round robin scheduler comprising: a round robin table configured to store a plurality of cycle link lists, including a plurality of active cycle link lists, wherein each active cycle link list identifies one or more flows to be processed during a corresponding cycle of the scheduler, and wherein each active cycle link list includes a head flow identification (FLID) value identifying a first flow of the active cycle link list, and a tail FLID value identifying a last flow of the active cycle link list; a flow table having a plurality of flow table entries, wherein each of the flow table entries corresponds with a flow to be processed, and wherein each of the flow table entries has a corresponding FLID value; and a plurality of packet queues, each associated with a corresponding flow table entry, and each configured to store packets of the flow associated with the corresponding flow table entry, wherein the plurality of cycle link lists further include one or more idle cycle link lists, each identifying a cycle of the scheduler where no flows have been scheduled to be processed, the scheduler further comprising an idle cycle register having an idle cycle entry corresponding with each of the cycle link lists, wherein each idle cycle entry identifies the corresponding cycle link list as active or idle.