Patent ID: 9171593
Filing Date: 2015-10-27
Classification: G06F,G11C

Abstract:
1. A multi-granularity parallel storage system comprising: a plurality of memories; a shift generator configured to generate a shift value Shift based on an externally-input address Addr; an address increment lookup unit configured to generate input data based on a read/write (R/W) granularity g; an address shifter configured to cyclically shift the input data rightward by Shift elements and output the shifted data; a row address generator configured to generate a row address RowAddr based on an externally-input address Addr; and a plurality of address adders each configured to perform a non-sign addition of the shifted data received at one input terminal and the generated row address RowAddr received at another input terminal to obtain a R/W address for one of the memories, and input the R/W address to an address input terminal of the memory.