Patent ID: 8741709
Filing Date: 2014-06-03
Classification: H01L

Abstract:
1. A process for fabrication of a power semiconductor device, comprising: depositing a single photomask on a layer of polysilicon on a wafer; removing the polysilicon layer from first regions of the power semiconductor device where p-conductivity type well regions and n-conductivity type source regions are to be formed; introducing a p-conductivity type dopant into the wafer through the first regions to form the p-conductivity type well regions; removing the single photomask; introducing an n-conductivity type dopant into the wafer through the first regions to form the n-conductivity type source regions; forming a multipurpose photomask on the wafer to overlie regions of the polysilicon layer which remain on the wafer, the polysilicon layer having an upper surface and having sidewalls, the multipurpose photomask overlying both the upper surface and the sidewalls, but leaving portions of the wafer exposed between the sidewalls; implanting p-conductivity type impurity through the portions of the wafer exposed between the sidewalls to form p-conductivity type impurity regions within the p-conductivity type well regions; and etching the wafer at locations where the portions of the wafer are exposed between the sidewalls to form recesses reaching toward the p-conductivity type impurity regions, wherein the etching of the wafer occurs after the implanting of the p-conductivity type impurity.