Patent ID: 6261935
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A method of creating MOS devices with salicided gate and source and drain, comprising the steps of:providing a semiconductor substrate whereby a recessed gate electrode structure has been created on the surface of said substrate whereby said gate electrode is surrounded by a layer of Inter Level Dielectric (ILD);depositing a composite layer of a first layer of Ti followed by a layer of amorphous Si followed by a second layer of Ti over the surface of said substrate thereby including the surface of said recessed gate electrode;patterning and etching said composite layer of Ti/Si/Ti thereby creating a strip of Ti/Si/Ti overlaying said layer of ILD whereby said strip of Ti/Si/Ti contacts the top surface of said gate electrode and extends from said gate electrode by a measurable amount; andsaliciding said layer of Ti/Si/Ti thereby providing a low resistivity contact to said top surface of said gate electrode.