Patent ID: 9058254
Filing Date: 2015-06-16
Classification: G06F

Abstract:
1. A memory device comprising: a nonvolatile memory including a plurality of memory blocks each having a plurality of nonvolatile memory cells, data in the nonvolatile memory being erased by each block; and a controller configured to manage a memory block by dividing the memory block into two or more areas which include first and second areas, the first area corresponding to a first logical address group, the second area corresponding to a second logical address group, and each of the first and second areas including a plurality of pages, wherein the controller is configured to receive a first write request related to a first logical address of a first memory block and to write data to a first page of a first area of a second memory block regardless of the first logical address when data of the first memory block is rewritten by the first write request, the first logical address belonging to the first logical address group and the first page of the first area being the beginning page of the first area, the controller is configured to receive a second write request related to a second logical address of the first memory block and to write data to a first page of a second area of the second memory block regardless of the second logical address when data of the first memory block is rewritten by the second write request, the second logical address belonging to the second logical address group and the first page of the second area being the beginning page of the second area, and the controller is configured to copy data, stored in a first area of the first memory block and not rewritten by the first write request, from the first area of the first memory block to a second page of the first area of the second memory block before the data is written to the second area of the second memory block by the second write request.