Patent ID: 8330529
Filing Date: 2012-12-11
Classification: G05F

Abstract:
1. An electronic arrangement comprising: a subcircuit configured and arranged to generate a stable voltage at a node and compensate for low-frequency changes of the stable voltage, the low-frequency changes being within a bandwidth of the subcircuit; a first field effect transistor (FET) having a gate, a drain and a source; a current source connected to the drain of the first FET; a second FET having a gate and a source, the source of the second FET connected to the source of the first FET by the node; and a low-pass filter circuit having an input connected to the gate of the first FET and an output connected to the gate of the second FET, wherein the second FET is configured and arranged to counteract high-frequency changes of the stable voltage at the node connecting the sources by increasing current drawn in response to increases of the stable voltage at the node and by decreasing current drawn in response to decreases of the stable voltage at the node, the high-frequency changes exceeding the bandwidth of the subcircuit.