Patent ID: 6686802
Filing Date: 2004-02-03
Classification: G06F

Abstract:
A phase-locked loop incorporated microcomputer comprising:an edge detector which receives an externally generated clock signal from outside and detects an edge of the externally generated clock signal and outputs an edge detection signal; a phase-locked loop circuit which generates a clock signal, phase-synchronizes the generated clock signal with the externally generated clock signal and generates a phase-synchronized signal, and multiplies the phase-synchronized signal by n to output as an internal clock signal used in a microcomputer; a counter which is cleared when the edge detector outputs the edge detection signal, performs a count operation utilizing the internal clock signal output from the phase-locked loop circuit as a count source, and outputs a count value; and an externally generated clock signal stop detector which detects that the externally generated clock signal is interrupted when the count value output from the counter has exceeded a threshold value, and outputs an external clock stop detection signal that indicates that the externally generated clock signal has been interrupted.