Patent ID: 7069461
Filing Date: 2006-06-27
Classification: G11C

Abstract:
1. A memory system comprising: a memory connected to a supply voltage, the memory having a clock input that receives a clock signal, a data input that receives to-be-stored data, and a data output that outputs a data output signal that outputs stored memory data; a time slack detector circuit that receives a sample signal and a launch signal, and outputs timing data defined by the sample and launch signals, the timing data having a first value when the clock signal has a first frequency, and a second value when the clock signal has a second frequency; and a control circuit connected to the memory and the time slack detector circuit, the control circuit generating the launch signal in response to the data output signal, and the sample signal in response to the launch signal, the control circuit detecting a change in the timing data and, in response to the change, outputting a signal that adjusts a magnitude of the supply voltage.