Patent ID: 6567310
Filing Date: 2003-05-20
Classification: G11C

Abstract:
Nonvolatile semiconductor memory, comprising:a core-side cell array, having a plurality of word lines, bit lines, and memory cells; a reference-side cell array, having word lines, a bit line, and reference cells; a sense amplifier, which compares a core-side input voltage corresponding to a bit line current of said core-side cell array, and a reference-side input voltage corresponding to a bit line current of said reference-side cell array; an address change detection circuit, which generates an address change detection pulse during a change in input address; a core-side decoder-driver, which selects and drives a word line on said core side; and, a reference-side decoder-driver, which selects and drives a word line on said reference side; and wherein at a first time at the end of said address change detection pulse, said core-side decoder-driver and reference-side decoder driver drive said core-side word line and reference-side word line to a power supply voltage, and at a second time when a prescribed length of time elaspes after the end of said address change detection pulse, said core-side decoder-driver and reference-side decoder-driver drive said core-side word line and reference-side word line to a boost voltage level higher than the power supply voltage.