Patent ID: 6291846
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A DRAM semiconductor device comprising:a semiconductor substrate;a field insulating film formed on said semiconductor substrate;a plurality of active regions, each surrounded by said field insulating film and formed said semiconductor substrate;a gate electrode traversing each of said plurality of active regions;a pair of source/drain regions formed in each of said plurality of active regions on both sides of said gate electrode;a plurality of bit lines disposed along one direction each connected to one region of said pair of source/drain regions;a plurality of word lines disposed along a direction perpendicular to said bit lines, each of said plurality of word lines being connected to said gate electrode; anda plurality of capacitor elements disposed over said gate electrode each connected to the other region of said pair of source/drain regions, wherein each of said plurality of active regions includes an oblique area, formed obliquely relative to said bit and word lines, and a parallel area formed in parallel to said bit line and having a width greater than the width of the oblique area, said word lines have a bent portion intersecting substantially at a right angle with the oblique area of every other one of said active regions, and said word lines extend outside of said active regions adjacent to said every other one of said active regions without overlapping.