Patent ID: 7620862
Filing Date: 2009-11-17
Classification: G01R

Abstract:
1. A method of testing an integrated circuit, said method comprising the steps of: coupling test equipment to said integrated circuit; coupling a test equipment clock signal from said test equipment to said integrated circuit, said test equipment clock signal having a first frequency; generating an internal burst clock signal within said integrated circuit based upon said test equipment clock signal, said internal burst clock signal having a burst frequency; selecting said test equipment clock signal or said internal burst clock signal as an internal test clock signal in response to a switch signal, said switch signal being generated responsive to a count of pulses of said internal test clock signal; testing said integrated circuit using said internal test clock signal in a first test cycle; identifying an error at a predetermined pulse of said internal test clock signal applied during said first test cycle; and testing said integrated circuit in a second test cycle, wherein data associated with said predetermined pulse of said internal test clock signal during said second test cycle is captured by a data strobe associated with said test equipment clock signal for generating output data.