Patent ID: 6627993
Filing Date: 2003-09-30
Classification: H01L,H05K

Abstract:
A semiconductor device comprising:a lower metal layer; a lower dielectric layer on top of said lower metal layer; an upper metal layer on top of said lower dielectric layer; an upper dielectric layer on top of said upper metal layer; a contact region formed as a cavity that extends through said upper dielectric layer, said upper metal layer and said lower dielectric layer for access to said lower metal layer; a dielectric lining layer that lines a peripheral cavity-confining surface of said cavity and that is transverse to a plane of said lower metal layer to isolate said upper metal layer from said lower metal layer while permitting access to said lower metal layer, said dielectric lining layer made of a photoresist material; and an electrical contact that fills said cavity and enables external electrical connection with said lower metal layer.