Patent ID: 6621758
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A low power Read Only Memory bank accessing system with efficient bus muxing for use with a microcontroller, comprising:(a) A Read Only Memory (ROM) Circuit, including at least a first ROM memory bank characterized by a first ROM memory bank address and a second ROM memory bank characterized by a second ROM memory bank address, wherein said first ROM memory bank and said second ROM memory bank further include a plurality of programmable memory cells for use in storing data said memory cell characterized by a logic level; (b) at least a first bit line coupled to at least one of said plurality of programmable memory cells of said first ROM memory bank; (c) at least a second bit line coupled to at least one of said plurality of programmable memory cells of said second ROM memory bank; (d) a first pre-charge circuit coupled to said first bit line for pre-charging said at least one of said plurality of programmable memory cells of said first ROM memory bank; (e) a second pre-charge circuit coupled to said second bit line for pre-charging said at least one of said plurality of programmable memory cells of said second ROM memory bank; (f) a first pre-discharge circuit coupled to said first bit line for pre-discharging said at least one of said plurality of programmable memory cells of said first ROM memory bank; (g) a second pre-discharge circuit coupled to said second bit line for pre-discharging said at least one of said plurality of programmable memory cells of said second ROM memory bank; (h) a central processing unit for providing a desired ROM memory bank address, said desired ROM memory bank address corresponding to at least one of said first ROM memory bank and said second ROM memory bank; (i) a ROM memory bank address decoder for decoding said desired ROM memory bank address and providing at least one of said first ROM memory bank address and said second ROM memory bank address; and (j) a ROM memory bank selection circuit for receiving at least one of said first ROM memory bank address and said second ROM memory bank address, said ROM memory bank selection circuit further providing a first pre-charge signal to at least one of said first pre-charge circuit and said second pre-charge circuit, said ROM memory bank selection circuit further providing a first pre-discharge signal to at least one of said first pre-discharge circuit and said second pre-discharge circuit, said first pre-charge signal and said pre-discharge signal being provided in accordance with said decoded desired ROM memory bank address.