Patent ID: 8467229
Filing Date: 2013-06-18
Classification: G11C,H01L

Abstract:
1. A variable resistance nonvolatile memory device including memory cells each having a variable resistance element, a resistance state of which reversibly changes based on an electrical signal, said device comprising: a substrate; bit lines in a plurality of layers which are stacked in a Z direction, and in which said bit lines extending in an X direction are aligned in a Y direction, the X and Y directions being directions orthogonal to each other on a plane parallel to a main surface of said substrate, and the Z direction being a direction in which the layers are stacked above the main surface of said substrate; word lines in a plurality of layers which are stacked in the Z direction and formed at respective intervals between the layers of said bit lines, and in which said word lines extending in the Y direction are aligned in the X direction; a memory cell array having said memory cells which are formed at respective crosspoints of said bit lines in the layers and said word lines in the layers, and each of which is interposed between a corresponding one of said bit lines and a corresponding one of said word lines, said memory cell array including basic array plane groups arranged in a matrix in the X and Y directions, said basic array plane groups each including a plurality of basic array planes which are aligned in the Y direction and each of which has memory cells included in said memory cells and interposed between, among said bit lines in the layers, bit lines in the layers at the same position in the Y direction and said word lines crossing said bit lines at the same position; selected-bit-line dedicated global bit lines provided in one-to-one correspondence with said basic array planes; an unselected-bit-line dedicated global bit line provided in correspondence with said basic array planes; and sets each including a first selection switch element, a second selection switch element, a third selection switch element, and a fourth selection switch element, said sets being provided in one-to-one correspondence with said basic array planes, wherein each of said basic array planes further includes a first internal wire interconnecting only even-layer bit lines among said bit lines in said basic array plane, and a second internal wire interconnecting only odd-layer bit lines among said bit lines in said basic array plane, and for each of said basic array planes, said first internal wire in said basic array plane is connected to said selected-bit-line dedicated global bit line corresponding to said basic array plane via one of said first selection switch element and said second selection switch element that are included in said set corresponding to said basic array plane, and said second internal wire in said basic array plane is connected to said corresponding selected-bit-line dedicated global bit line via the other of said first selection switch element and said second selection switch element that are included in said corresponding set, and when one of said basic array planes included in said basic array plane groups is a first basic array plane, and a different one of said basic array planes is a second basic array plane, said different one being adjacent to said first basic array plane in the Y direction, said first internal wire in said first basic array plane and said second internal wire in said second basic array plane are adjacent to each other in the Y direction, and said second internal wire in said first basic array plane and said first internal wire in said second basic array plane are adjacent to each other in the Y direction, said first internal wire in said first basic array plane is connected to said selected-bit-line dedicated global bit line corresponding to said first basic array plane via said first selection switch element corresponding to said first basic array plane or is connected to said unselected-bit-line dedicated global bit line via said third selection switch element corresponding to said first basic array plane, and said second internal wire in said first basic array plane is connected to said selected-bit-line dedicated global bit line corresponding to said first basic array plane via said second selection switch element corresponding to said first basic array plane or is connected to said unselected-bit-line dedicated global bit line via said fourth selection switch element corresponding to said first basic array plane, said second internal wire in said second basic array plane is connected to said selected-bit-line dedicated global bit line corresponding to said second basic array plane via said first selection switch element corresponding to said second basic array plane or is connected to said unselected-bit-line dedicated global bit line via said third selection switch element corresponding to said second basic array plane, and said first internal wire in said second basic array plane is connected to said selected-bit-line dedicated global bit line corresponding to said second basic array plane via said second selection switch element corresponding to said second basic array plane or is connected to said unselected-bit-line dedicated global bit line via said fourth selection switch element corresponding to said second basic array plane, and with regard to said first selection switch elements, said second selection switch elements, said third selection switch elements, and said fourth selection switch elements corresponding to said basic array planes, electrical connection and disconnection of said first said selection switch elements are controlled by a common first bit line selection signal, electrical connection and disconnection of said second selection switch elements are controlled by a common second bit line selection signal, electrical connection and disconnection of said third selection switch elements are controlled by a common third bit line selection signal, and electrical connection and disconnection of said fourth selection switch elements are controlled by a common fourth bit line selection signal.