Patent ID: 9035195
Filing Date: 2015-05-19
Classification: H05K

Abstract:
1. A circuit board having a tie bar buried therein, comprising: a dielectric stack, comprising a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer, wherein the first dielectric layer is located on the second dielectric layer, the dielectric stack including a wireline region and a gold finger region; at least a first tie bar, buried in the gold finger region between the first dielectric layer and the second dielectric layer; at least a first gold finger, located only in the gold finger region on the first dielectric layer on the first tie bar; at least a first microvia, located in the gold finger region in the first dielectric layer and electrically connecting the first gold finger to the first tie bar; at least a first patterned conductive layer, located on the first dielectric layer; at least a second microvia, located in the first dielectric layer and electrically connecting the first patterned conductive layer to the first tie bar; a first connecting wire, located on the first dielectric layer and electrically connected to the first patterned conductive layer; at least a second tie bar, buried in the gold finger region between the third dielectric layer and the fourth dielectric layer; at least a second gold finger, located in the gold finger region on the fourth dielectric layer on the second tie bar; at least a third microvia, located in the gold finger region in the fourth dielectric layer and electrically connecting the second gold finger to the second tie bar; at least a second patterned conductive layer, located on the fourth dielectric layer; at least a fourth microvia, located in the fourth dielectric layer and electrically connecting the second patterned conductive layer to the second tie bar; and a second connecting wire, located on the fourth dielectric layer and electrically connected to the second patterned conductive layer.