Patent ID: 8799560
Filing Date: 2014-08-05
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory plane which includes a plurality of bit lines, a plurality of word lines crossing the plurality of bit lines, and a plurality of memory cells arranged at predetermined crossing points of the plurality of bit lines and the plurality of word lines; an input buffer to which an operation setting command, a data, and an address are inputted, the operation setting command setting an operation for the memory plane, the data being stored in the plurality of memory cells, and the address corresponding to the data; a memory area control circuit which controls to write the data into the memory plane in accordance with the address inputted to the input buffer; and a page size register which is set as a first rewrite mode or a second rewrite mode in accordance with the operation setting command inputted to the input buffer; a ready/busy signal line; and a block erase register which is set as a block erase mode in a case that a block erase command is inputted to the input buffer, the memory plane including a first information storage area and a second information storage area, wherein first access cycle time is shorter than second access cycle time, the first access cycle time taken from input of the operation setting command in the case that the page size register is set as the first rewrite mode, followed by end of the rewrite operation into the memory plane, until input of a next operation setting command, and the second access cycle time taken from input of the operation setting command in the case that the page size register is set as the second rewrite mode, followed by end of the rewrite operation into the memory plane, until input of a next operation setting command, the memory area control circuit writes the data into the first information storage area and activates the ready/busy signal line during first busy time in a case that the page size register is set as the first rewrite mode and an address indicating the first information storage area is inputted to the input buffer, the memory area control circuit writes the data into both of the first information storage area and the second information storage area and activates the ready/busy signal line during second busy time in a case that the page size register is set as the second rewrite mode and an address indicating the first information storage area is inputted to the input buffer, the memory area control circuit activates the ready/busy signal line during third busy time in a case that the block erase register is set as the block erase mode, the first busy time is shorter than the second busy time, and the third busy time is shorter than the first busy time.