Patent ID: 9165916
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor package, comprising: stacking a plurality of lower semiconductor chips to form a lower stack; mounting the lower stack on a substrate; forming a lower mold layer on the substrate to enclose a side surface of the lower stack and to expose a top surface of the lower stack; mounting an upper stack including a plurality of upper semiconductor chips on the lower stack having the side surface enclosed by the lower mold layer; wherein the mounting of the lower stack comprises providing lower solder balls on a bottom surface of the lower stack and performing a reflow process to a structure with the lower solder balls to form lower connecting portions that are disposed between the substrate and the lower stack and are electrically connected to the substrate; and wherein the forming of the lower stack comprises preparing a first semiconductor substrate, on which a first semiconductor chip formed with first through vias is provided; mounting a second semiconductor chip with second through vias, on the first semiconductor chip of the first semiconductor substrate; and performing a separation process to the first semiconductor substrate to form the lower stack including the first and second semiconductor chips that are sequentially stacked.