Patent ID: 8305129
Filing Date: 2012-11-06
Classification: G11C,H03K,H04L

Abstract:
1. An internal clock generating circuit for generating a clock signal using a data signal, the internal clock generating circuit comprising: a transition detecting block receiving the data signal at an input, detecting transitions in the data signal, and generating at least one data transition information signal indicative of the timing of the detected transitions in the data signal; and an internal clock generating block receiving the data transition information signal from the transition detecting block, generating a period digital data signal by detecting a unit period of the data signal when operating in a period confirming mode, and generating an internal clock signal in response to the data transition information signal when operating in an internal clock generating mode, wherein the internal clock signal transitions between logic states after a waiting time has elapsed following a transition in the data signal, wherein the waiting time is dependent on the period digital data signal, and wherein the waiting time is equal to half of the unit period of the data signal.