Patent ID: 8405465
Filing Date: 2013-03-26
Classification: H02M,H03F,H03K,H03M

Abstract:
1. A duty cycle translator, comprising: a duty cycle evaluator configured to receive an input duty-cycle-modulated (DCM) signal and generate a first digital number representing a duty cycle of the input DCM signal; a first digital counter configured to generate a second digital number; and a comparator configured to compare the first and second digital numbers and generate an output DCM signal having a higher frequency or higher data rate than a frequency or data rate of the input DCM signal and a duty cycle that is substantially the same as a duty cycle of the input DCM signal wherein said duty cycle evaluator comprises: a second digital counter configured to generate a count representing a portion of a period of the input DCM signal during which the input DCM signal is high; a third digital counter configured to generate a count representing a period of the input DCM signal; and a divider configured to divide the count from said second digital counter by the count from said third digital counter to generate said first digital number.