Patent ID: 7221586
Filing Date: 2007-05-22
Classification: G11C,H01L

Abstract:
1. A memory array, comprising: a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, and wherein the gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers, wherein along columns of the pillars adjacent pillars include a transistor which operates as a multistate cell on one side of a trench and a transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the drain region of each transistor along rows of the memory array; a number of word lines coupled to the gate of each transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that a multistate cell transistor and a reference cell transistor share a common sourceline; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of multistate cell transistors is a programmed transistor having one of a number of charges trapped in the gate insulator adjacent to the source region such that the channel region of that transistor has a first voltage threshold region (Vt