Patent ID: 9041146
Filing Date: 2015-05-26
Classification: G11C,H01L

Abstract:
1. An apparatus comprising: a monolithic substrate; a memory area, comprising (a) a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, located on the substrate; and (b) an additional MTJ, having an additional tunnel barrier directly contacting additional lower and upper MTJ layers; and a logic area located on the substrate; wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ and the additional MTJ, a first Inter-Layer Dielectric (ILD) material included in the memory area, and a second ILD material included in the logic area; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer sidewall by a horizontal offset space that defines a horizontal offset distance; wherein a contiguous etch stop portion directly contacts the MTJ and the additional MTJ.