Patent ID: 7838921
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A memory cell arrangement, comprising: a first memory cell string comprising a plurality of serially source-to-drain-coupled transistors, at least some of the transistors being memory cells; a second memory cell string comprising a plurality of serially source-to-drain-coupled transistors, at least some of the transistors being memory cells; dielectric material between and above the plurality of transistors of the first memory cell string and the plurality of transistors of the second memory cell string; a source/drain line groove in the dielectric material, the source/drain line groove extending from a source/drain region of one transistor of the plurality of transistors of the first memory cell string to a source/drain region of one transistor of the plurality of transistors of the second memory cell string; electrically conductive filling material in the source/drain line groove coupled to the source/drain region of the transistor of the plurality of transistors of the first memory cell string and to the source/drain region of the transistor of the plurality of transistors of the second memory cell string; and dielectric filling material in the source/drain line groove between the source/drain region of the transistor of the plurality of transistors of the first memory cell string and the source/drain region of the transistor of the plurality of transistors of the second memory cell string.