Patent ID: 6555462
Filing Date: 2003-04-29
Classification: H01L,H05K,Y10S

Abstract:
A method tar manufacturing a semiconductor device having a stress reducing laminate, comprising:(a) forming an interlayer dielectric film on a substrate; (b) forming a first conductive layer on the interlayer dielectric film; and (c) forming parallel first elongate grooves and parallel second elongate grooves in an upper surface of the first conductive layer, wherein the first elongate grooves are perpendicular to and cross over the second elongate grooves; (d) subsequently forming a first interlayer dielectric film on the first conductive layer and thereby filling the first and second elongate grooves; (e) forming first via holes in the first interlayer dielectric film, through which regions of the first conductive layer between the first and second elongate grooves are exposed; (f) subsequently forming a second conductive layer on the first interlayer dielectric film and thereby filling the first via holes; (g) forming parallel third elongate grooves and parallel fourth elongate grooves in an upper surface of the second conductive layer at respective locations spaced laterally from locations at which the second conductive layer fills the first via holes, wherein the third elongate grooves are perpendicular to and cross over the fourth elongate grooves; (h) subsequently forming a second interlayer dielectric film on the second conductive layer and thereby filling the third and fourth elongate grooves; (i) forming second via holes in the second interlayer dielectric film, through which regions of the second conductive layer between the third and fourth elongate grooves are exposed; and (j) subsequently forming a third conductive layer on the second interlayer dielectric film and thereby filling the second via holes.