Patent ID: 8395409
Filing Date: 2013-03-12
Classification: G01R

Abstract:
1. An integrated circuit, comprising: a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal; a first gated buffer configured to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal; a second gated buffer configured to receive the first gated buffer output signal and configured to produce a second gated buffer output signal to be provided to a pin; and a receive input buffer configured to be coupled to said pin and configured to receive an input signal from said pin; wherein said integrated circuit operates in a test mode in which the second gated buffer is disabled thereby preventing a test signal provided to an input of the first mux from reaching the pin, the test signal provided instead through the first mux to the first gated buffer and to the receive buffer thereby testing at least the first mux.