Patent ID: 7158426
Filing Date: 2007-01-02
Classification: G11C

Abstract:
1. A method for testing an integrated semiconductor memory, comprising: providing an integrated semiconductor memory which can be operated in a test operating state, the integrated semiconductor memory including a register for reading in a threshold value, a counter, and at least one memory bank with at least one word line with bit lines and memory cells, the memory cells each having a storage capacitor and a selection transistor, the selection transistor being controlled by driving one of the word lines in one of the memory banks with a control voltage, the respective memory bank and the respective word line selected for driving one of the word lines in one of the memory banks, the respective storage capacitors of the memory cells being connected to a respective one of the bit lines by turning on the respective selection transistors of the memory cells; and driving a control circuit in the test operating state synchronously with a clock edge of a control clock with a first control signal, so that a test includes