Patent ID: 8635418
Filing Date: 2014-01-21
Classification: G11C

Abstract:
1. A memory system comprising: first and second sets of dynamic random access memories (DRAMs), each DRAM having at least a first and a second addressable mode register, wherein the binary address of the second mode register is the inverted binary address of the first mode register; and a system register having an input configured to be coupled to a controller, an output coupled to the first set of DRAMs via first address lines and an inverted output coupled to the second set of DRAMs via second address lines, wherein the system register is configured to receive mode register set commands including address bits and configuration bits at the input and to output the mode register set commands non-inverted via the output to the first set of DRAMs and in inverted form via the inverted output to the second set of DRAMs, wherein the system further comprises a controller, wherein the controller is configured to send to the system register each mode register set command followed by an inverted copy of the command, and wherein the DRAMs are configured to ignore any access to the second addressable mode registers.