Patent ID: 6792059
Filing Date: 2004-09-14
Classification: H04L

Abstract:
A bit synchronizer for a digital receiver system, the bit synchronizer comprising:a DC level estimator for converting a sampled digital signal having a bit rate and a sampling rate into a level-adjusted signal; a delay module operable to cumulatively delay the level-adjusted signal by different increments and to generate a first timing signal, a second timing signal, and a third timing signal based on the cumulatively delayed level-adjusted signals, the first timing signal corresponding to a sum of the cumulatively delayed level-adjusted signals over a first bit interval, the second timing signal corresponding to a sum of the cumulatively delayed level-adjusted signals over a second bit interval, and the third timing signal corresponding to a sum of the cumulatively delayed level-adjusted signals over a third bit interval; and a control module for generating an output signal based on the first, second and third timing signals such that the bit rate and the sampling rate are synchronized, wherein the control module includes: an absolute value stage for generating absolute values of the first, second and third timing signals; an integration stage for generating integrated signals, each integrated signal representing average values for a given absolute valued timing signal over a predetermined integration length; a logic module for generating a selection signal based on the integrated signals; a switching module for selecting between the first, second and third timing signals based on the selection signal; and a threshold module coupled to the switching module, the threshold module generating the output signal based on the selected timing signal and a threshold value.