Patent ID: 8513993
Filing Date: 2013-08-20
Classification: G11C,H03L

Abstract:
1. A device comprising a DLL circuit that comprises: a first terminal supplied with a first clock signal; a second terminal supplied with a second clock signal; a clock circuit configured to produce a third clock signal in response to an active level of an enable signal supplied thereto and to stop producing the third clock signal in response to an inactive level of the enable signal irrespective of each of the first and second clock signals; a delay circuit coupled to the first terminal to receive the first clock signal and supplied with delay control data, the delay circuit being configured to delay the first clock signal in repose to the delay control data and produce a fourth clock signal; a buffer circuit producing the second clock signal in response to the fourth clock signal; and a control circuit coupled to receive a DLL initiation signal that is generated to activate the DLL circuit while the first clock signal is being supplied to the first terminal, the control circuit being further coupled to the first terminal, the second terminal, the clock circuit and the delay circuit and configured to respond to generation of the DLL initiation signal and change the enable signal from the inactive level to the active level to allow the clock circuit to produce the third clock signal and configured to generate the delay control data in response to the first, second and third clock signals.