Patent ID: 8700962
Filing Date: 2014-04-15
Classification: G01R

Abstract:
1. An integrated circuit comprising: scan test circuitry; and additional circuitry subject to testing utilizing the scan test circuitry; the scan test circuitry comprising at least one scan chain having a plurality of scan cells; the scan test circuitry being configured to control at least a given one of the scan cells so as to prevent the scan cell from capturing a potentially non-deterministic value from a portion of the additional circuitry, wherein the given scan cell has a clock input and is configured such that its clock input is driven by a clock output of a clock gating latch, and wherein control inputs of the clock gating latch are driven by a shift enable signal and a scan mode signal, and the clock gating latch passes a clock signal from its clock input to its clock output responsive to predetermined logic levels of the shift enable signal and the scan mode signal.