Patent ID: 6691142
Filing Date: 2004-02-10
Classification: G06F,G11C

Abstract:
A pseudo random sequence generator comprising:a first portion configured as a linear feedback shift register (LFSR) having a first update input terminal and a plurality of sequential first memory elements, each said first memory element having a first output terminal; a most significant bits (MSB) second portion interconnected with said first portion, said second portion including: an AND gate having one input terminal connected to said first update input terminal and a different input terminal connected to a first output terminal of one of said plurality of first memory elements, said AND gate having an output terminal; N sequential second memory elements, each said second memory element having a second update input terminal connected to said output terminal of said AND gate, each said second memory element having a data input terminal and a data output terminal, said sequential second memory elements from a second element zero through a second element (Nâˆ’1) being interconnected sequentially such that said data output terminal of said second element (Nâˆ’1) is interconnected with said data input terminal of said second element zero through a feedback logic circuit; and such that said data output terminal of said second element zero is connected to said data input terminal of a next sequential second element.