Patent ID: 6288589
Filing Date: 2001-09-11
Classification: G06F,G11C,H03K

Abstract:
A clock circuit for clocked precharge (CP) logic gates in an Integrated Circuit (IC), comprising:a master global clock signal distributed in a low-skew manner over a relevant clock domain area, a master global clock circuit generates said master global clock signal;a plurality of local clock circuits that generate a plurality of locally generated clock signals in said clock domain area wherein an individual local clock circuit generates an individual locally generated clock signal, said plurality of local clock circuits couple to said master global clock signal, said local clock circuits are tuned to allow for skew and jitter tolerance such that there is one gate delay per clock phase for each of said plurality of locally generated clock signals, said plurality of locally generated clock signals couple to a plurality of clocked precharge (CP) logic gates wherein each said individual locally generated clock signal couples to an individual CP logic gate;one or more of said plurality of locally generated clock signals are derived from the rising edge of said master global clock signal and one or more of said plurality of locally generated clock signals are derived from the falling edge of said master global clock signal; andsaid plurality of locally generated clock signals comprise an approximately 50% duty cycle and overlapping phases where an individual locally generated clock signal overlaps an earlier phase individual locally generated clock signal by an amount approximately equal to the overlap of the next phase individual locally generated clock signal, wherein said plurality of locally generated clock signals overlap in such away that two or more individual locally generated clock signals of said plurality of locally generated clock signals overlap in their evaluate phase at any point in time.