Patent ID: 6436839
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of forming a misalignment immune antifuse, such that a programing voltage is not degraded upon misalignment, comprising:providing a partially processed semiconductor wafer containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where said conducting region is surrounded by a dielectric layer which reaches the wafer surface; depositing a blanket layer of amorphous silicon followed by depositing a thin blanket layer of TiN; patterning and etching said layers down to said dielectric surface except for a cap that more than covers said conducting region; growing a thin oxide over the exposed surface of said amorphous silicon: depositing a thicker blanket TIN layer and of a blanket metallization layer; patterning and etching said thick TiN and metallization layer down to said dielectric layer except for a cap that more than covers said thin TiN and amorphous silicon layers; growing a thin oxide over any said amorphous silicon surface that may have been exposed in said last etching step, whereby a misalignment immune antifuse, such that the programming voltage is not degraded upon misalignment, is formed.