Patent ID: 7209389
Filing Date: 2007-04-24
Classification: G11C,H01L

Abstract:
1. An integrated circuit, comprising: an array of memory cells, the array configured as a NAND array in a plurality of columns and rows of memory cells, the columns comprising one or more sets of memory cells in series couple to a bit line, and the rows comprising sets of memory cells having their respective gate terminals coupled to a word line, memory cells in the array respectively comprising a gate terminal, a first channel terminal, a second channel terminal and a channel region between the first and second channel terminals, a charge trapping structure over the channel region, a tunneling dielectric between the channel region and the charge trapping structure, and a blocking dielectric between the charge trapping structure and the gate terminal; circuitry to program the memory cells in the away by E-field assisted tunneling through the tunneling dielectric by applying a positive voltage to the gate terminal and a low voltage or ground to the first and second channel terminals, while limiting program and erase cycling; and circuitry to read data from the memory cells.