Patent ID: 6165858
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method for forming a transistor in an active region of a substrate, the method comprising:forming a gate structure upon the active region, the gate structure having a gate dielectric and a gate conductor;implanting a first dopant at a first implant depth and at a first implant dose to form first source and drain implants;implanting a second dopant at a second implant depth and at a second implant dose to form second source and drain implants, the second implant depth greater than the first implant depth;wherein implanting the first dopant also forms a first doped gate conductor portion;wherein implanting the second dopant also forms a second doped gate portion;depositing a silicidation metal layer;reacting the silicidation metal layer with the first source and drain implants to form source and drain silicidation regions, the source and drain silicidation regions substantially consuming the first source and drain implants, respectively; andremoving unreacted portions of the silicidation metal layer.