Patent ID: 6101130
Filing Date: 2000-08-08
Classification: G11C

Abstract:
A semiconductor device having an electrically erasable programmable read only memory (EEPROM) array including tows and columns of memory cells comprising:a first word line and a second word line substantially parallel to each other and extending in a first direction;a first drain bit line, a second drain bit line, and a first source line, wherein:each of the first and second drain bit lines and the first source line are substantially parallel to each other; andthe first and second drain bit lines and the first source line extend in a second direction that is substantially perpendicular to the first direction;a first source local interconnect that electrically connects the first source line and source regions of at least two memory cells within the EEPROM array, wherein:the first source local interconnect has a length that extends from the first source line substantially in the first direction;the at least two memory cells lie along a same row or column; andthe first source local interconnect electrically connects only some, but not all,memory cells lying along the same row or column within the EEPROM array.