Patent ID: 7415595
Filing Date: 2008-08-19
Classification: G06F,H04B,Y02D

Abstract:
1. A digital signal processor comprising: a plurality of independently accessible memory units; a plurality of accelerator units, each configured to perform one or more dedicated functions; a processor core including an execution unit configured to execute instructions associated with datapath flow control; and a programmable network configured to selectively provide connectivity between the plurality of independently accessible memory units, the plurality of accelerator units, and the processor core in response to execution of the instructions; wherein in response to execution of a first particular instruction, the programmable network is configured to couple together, in a chain, two or more accelerator units of the plurality of accelerator units and to further selectively couple a first accelerator unit of the chain to a given one of the plurality of memory units, thereby providing a datapath for data to flow from one accelerator unit in the chain to a next accelerator unit in the chain without further processor core intervention.