Patent ID: 7360182
Filing Date: 2008-04-15
Classification: G06F

Abstract:
1. A method for reducing delay noise in an integrated circuit, the integrated circuit comprising a plurality of devices and a plurality of nets, wherein each net having a ground capacitance, a coupling capacitance, and a resistance, the method comprising: generating delay information for each net and each device; computing an effective capacitance for each net is determined based on a coupling multiplier, wherein the coupling multiplier is based on the ground capacitance and the coupling capacitance; computing a scale factor for each net, wherein the scale factor is computed by dividing the effective capacitance by a sum of the ground capacitance and the coupling capacitance; scaling the effective capacitance by the scale factor to determine a delay noise induced load for each net; and incrementally optimizing timing paths using the delay noise induced load, the resistance, and the delay information.