Patent ID: 6819611
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A memory device having a normal mode and a test mode, the memory device comprising:first and second memory arrays, each memory array having memory cells arranged in rows and columns, each column of memory cells having a pair of complementary digit lines; a pair of complementary data lines; column select circuitry to concurrently couple at least one pair of complementary digit lines from the first memory array and at least one pair of complementary digit lines from the second memory array to the pair of complementary data lines in response to the memory device being in the test mode; an amplifier having complementary inputs coupled to the pair of complementary data lines, the complementary inputs of the amplifier coupled to a current source; and an evaluation circuit coupled to the complementary data lines and generating an output signal having a logic value indicative of a pass-fail condition in accordance with logic levels of the complementary inputs of the amplifier.