Patent ID: 6128329
Filing Date: 2000-10-03
Classification: H04B

Abstract:
A spread-spectrum receiver for a code-division multiple access communication system, comprising:a radio circuit for converting a high frequency signal received by an antenna into a base-band signal,a timing control circuit for detecting timings on a plurality of paths through search processing to thereby generate first and second replica code timing indicating signals, a timing pulse, and first and second delay time indicating signals;a first replica code generator for generating a first replica code at a timing indicated by said first replica code timing indicating signal supplied from said timing control circuit;a second replica code generator for generating a second replica code at a timing indicated by said second replica code timing indicating signal supplied from said timing control circuit, said second replica code being the same as said first replica code;a first correlator for determining a correlation value of said base-band signal and said first replica code supplied from said first replica code generator;a second correlator for determining a correlation value of said base-band signal and said second replica code supplied from said second replica code generator;a first synchronous detector for outputting a first symbol signal through synchronous detection of an output signal of said first correlator;a second synchronous detector for outputting a second symbol signal through synchronous detection of an output signal of said second correlator;a first timing adjusting buffer for latching said first symbol signal outputted from said first synchronous detector in response to said timing pulse supplied from said timing control circuit, and outputting said first symbol signal as latched with a delay time indicated by said first delay time indicating signal outputted from said timing control circuit;a second timing adjusting buffer for latching said second symbol signal outputted from said second synchronous detector in response to said timing pulse supplied from said timing control circuit, and outputting said second symbol signal as latched with a delay time indicated by said second delay time indicating signal outputted from said timing control circuit; anda RAKE combining circuit for synthesizing output signals from said first timing adjusting buffer and said second timing adjusting buffer,wherein said first and second delay time indicating signals indicate delay times for said first and second timing adjusting buffers on a chip period basis, respectively,wherein said first timing adjusting buffer includes:plural stages of first latch circuits disposed between said first synchronous detector and said RAKE combining circuit; anda plurality of first switches disposed between output terminals of said plural stages of first latch circuits and said RAKE combining circuit, respectively, and turned on/off under the control of said first delay time indicating signal, andsaid second timing adjusting buffer includes:plural stages of second latch circuits disposed between said second synchronous detector and said RAKE combining circuit; anda plurality of second switches disposed between output terminals of said plural stages of second latch circuits and said RAKE combining circuit, respectively, and turned on/off under the control of said second delay time indicating signal.