Patent ID: 7593971
Filing Date: 2009-09-22
Classification: G06F,Y10S

Abstract:
1. A method for managing state information in a processor, the method comprising: determining, based on information provided by a program executing on the processor, a number of items of state information included in a state version; determining, based on the number of items of state information included in a state version, a maximum number of state versions to be concurrently maintained in a lookup table having a fixed number of entries, each entry being usable to store an item of state information, wherein the lookup table includes: selecting, based on at least one of the number of items of state information included in a state version and the number of state versions to be concurrently maintained in the lookup table, a management scheme to be used to store and update state information in the lookup table, wherein the act of selecting a management scheme includes: selecting a first management scheme in the event that the number of memory circuits exceeds the number of items of state information included in a state version; and selecting a second management scheme in the event that the number of items of state information included in state version exceeds the number of memory circuits; loading a first set of items of state information into the lookup table as a first state version, wherein a number of items included in the first set of items of state information is equal to the number of items of state information included in a state version; receiving an update to one of the first set of items; and in the event that the number of state versions concurrently maintained in the lookup table is at least two and the first state version is in use by at least one executing thread, creating a new state version in the lookup table in accordance with the selected management scheme, wherein the new state version includes the update to the one of the first set of items.