Patent ID: 6924206
Filing Date: 2005-08-02
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor capacitive element which uses wirings buried in an interlayer dielectric on a semiconductor substrate as electrodes, said method comprising: a lower layer wiring trench forming process in which, after a first etching stopper film and a first interlayer dielectric have been sequentially formed on said semiconductor substrate, each of said first interlayer dielectric and said first etching stopper film in a first region corresponding to a multi-layer wiring forming portion and each of said first interlayer dielectric and said first etching stopper film in a second region corresponding to a capacitor forming portion on said semiconductor substrate are selectively etched to form first and second lower layer wiring trenches, a lower layer conductive film forming process of forming a lower layer wiring in said first lower layer wiring trench in said first region corresponding to said multi-layer wiring forming portion and, at a same time, of forming a lower electrode in said second lower layer wiring trench in said second region corresponding to said capacitor forming portion; a via hole forming process in which, after a second etching stopper film and a second interlayer dielectric have been sequentially formed on said first interlayer dielectric, said second interlayer dielectric and said second etching stopper film in said first region corresponding to said multi-layer wiring forming portion are selectively etched to form a first via hole and, at a same time, said second interlayer dielectric in said second region corresponding to said capacitor forming portion is selectively etched to form a second via hole to allow said second etching stopper film to be exposed; and a via plug forming process of forming a first via plug in said first via hole in said first region corresponding to said multi-layer wiring forming portion and, at a same time, of forming a second via plug serving as an upper electrode in said second via hole in said second region corresponding to said capacitor forming portion.