Patent ID: 6812130
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method for forming a dual damascene structure for a semiconductor device comprising the steps of:providing conductive regions on a first layer; forming an interlevel dielectric layer over the first layer; forming an etch stop layer over the interlevel dielectric layer, the etch stop layer including a polymer material having a dielectric constant of less than about 3.0; patterning the etch stop layer to form a via pattern; depositing a trench dielectric layer on the etch stop layer and in holes of the via pattern; forming trenches in the trench dielectric layer by etching the trench layer in accordance with a trench pattern; and forming vias in the interlevel dielectric layer by etching through the trenches using the etch stop layer to self-align the trenches to the vias and expose the conductive regions on the first layer, said etching eroding portions of the etch stop layer such that the etch stop layer forms part of the sidewalls of the trenches, thereby improving dielectric strength of the interlevel dielectric layer.