Patent ID: 6646474
Filing Date: 2003-11-11
Classification: H03K,H04L

Abstract:
A memory system, comprising:at least one memory device for storing data, said memory device having at least one control logic circuit; at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal; at least one precharge transistor coupled to said inverter and configured to precharge said output of said inverter to a first logic state; and at least one clocking transistor coupled to said inverter and configured to selectively enable said output of said inverter.