Patent ID: 7442612
Filing Date: 2008-10-28
Classification: H01L

Abstract:
1. A method of fabricating a double-gate field effect transistor comprising: providing a structure by utilizing a bonding and thinning process, said structure including at least an ion implanted back-plane region, a back-gate dielectric stack including at least a bottom back-gate nitride formed atop said ion implanted back-plane region, a Si-containing layer having edges formed atop said back-gate dielectric stack, a front gate dielectric formed atop said Si-containing layer, and a front gate formed atop said front gate dielectric, said structure having isolation trench regions adjacent to at least said doped back-plane region; forming insulating spacers on exposed vertical sidewalls of said front gate; forming protective spacers on said structure about said insulating spacers and covering said edges of said Si-containing layer; forming isolation regions by oxidation in regions of said structure which are adjacent to, and overlaying a portion of said doped back-plane region, whereby said protective spacers and said bottom back-gate nitride protect said Si-containing layer from oxidizing and said isolation regions are self-aligned to said front gate; removing said protective spacers exposing said edges of said Si-containing layer; forming source/drain regions into said edges of the Si-containing layer by utilizing an angled ion implantation process; selectively growing Si-containing regions above and in contact with said edges utilizing an epitaxial silicon growth process; and forming silicide regions of said Si-containing regions and said front gate.