Patent ID: 6566172
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method for forming a tri-layer thin film transistor on a substrate, said tri-layer thin film transistor including a stack comprising a gate electrode supported by said substrate, followed by a first insulation layer, a semiconductor layer and a second insulation layer, said method comprising the steps of:(a) patterning said second insulation layer into an insulation patch which is aligned with said gate electrode; (b) depositing a doped semiconductor layer, wherein said doped semiconductor layer is deposited on said insulator patch and said semiconductor layer; (c) applying a mask under said substrate; and (d) patterning metallization contacts on said doped semiconductor layer, which are aligned with said insulator patch and said mask, by i.) applying a resist layer on said doped semiconductor layer; ii.) exposing said resist layer by backside illumination that has been masked as shadowed by said gate electrode and said mask; iii.) removing areas of said resist layer exposed to said illumination; iv.) depositing a layer of metallization on said resist layer and said doped semiconductor layer; and v.) removing said resist layer and said metallization layer deposited thereon to form contact to source and drain regions of said tri-layer thin film transistor.