Patent ID: 8150638
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. A computer-implemented method of determining parasitic capacitance for a transistor within an integrated circuit, the method comprising: selecting a first expression to be C2D determining, using a processor, a first set of coefficients for the first expression that calculates parasitic capacitance for a transistor structure according to the first plurality of parasitic capacitances derived from the plurality of two-dimensional transistor structures; inserting the first set of coefficients into the first expression; determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures, wherein the second expression comprises the first expression; inserting the second set of coefficients into the second expression; and solving the second expression to determine parasitic capacitance of the transistor.