Patent ID: 6023266
Filing Date: 2000-02-08
Classification: G09G,H04N

Abstract:
A video controller for receiving and decompressing compressed video data, said compressed video data comprising at least a pixel bit map, wherein each pixel of said pixel bit map is represented by one of a number of pixel values, said video controller comprising:a pixel clock for generating a pixel clock signal;a FIFO for receiving at least said pixel bit map and said number of pixel values;a serializer, coupled to said FIFO and said pixel clock, for storing said pixel bit map and outputting a sequential bit from said pixel bit map synchronized with said pixel clock signal;at least one pixel value register, coupled to said FIFO and said pixel clock, for storing a pixel value and outputting said pixel value synchronized with said pixel clock signal; anda MUX, coupled to said serializer, and said at least one pixel value register, for selectively outputting said pixel value as pixel data in response to the sequential bit output from said pixel luminance bit map.