Patent ID: 9003242
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells and having a plurality of data units, each of the data units being read out collectively; a first register configured to store data of the memory cells for each of the data units; and a sequence control circuit configured to control the memory cell array and the first register, wherein in at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range, determines whether the number of failed bits is in the allowable range based on a state of the readout flag information, when it is determined that the number of failed bits is in the allowable range based on the state of the readout flag information, reads out the data of the memory cell using first address mapping for mapping the data to read out the data in an order of addresses stored in the first register, and when it is determined that the number of failed bits is not in the allowable range based on the state of the readout flag information, reads out the data of the memory cell using second address mapping whose read order is different from that of first address mapping.