Patent ID: 6088290
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A semiconductor memory device comprising:a power-down control circuit for generating first and second power-down signals in accordance with first and second logic levels of a clock enable signal, the power-down control circuit generating the first power-down signal for setting the device in a power-down mode in accordance with the first logic level of the clock enable signal which allows a clock signal to input into the device, and generating the second power-down signal for releasing the power-down mode in accordance with the second logic level of the clock enable signal;a clock controlling section connected to the power-down control circuit, the clock controlling section making an internal clock signal non-activate in accordance with the first power-down signal output from the power-down control circuit, and activating the internal clock signal in accordance with the second power-down signal;a decoder for decoding a plurality of input signal supplied to the decoder; anda latch circuit connected to the decoder, the latch circuit latching an output signal of the decoder in accordance with the internal clock signal activated by the clock controlling section.