Patent ID: 7594058
Filing Date: 2009-09-22
Classification: G06F

Abstract:
1. A chipset supporting a peripheral component interconnection Express (PCI-E) architecture, connected in between a microprocessor and a plurality of PCI-E ports, comprising: a port arbiter, receiving data and arbitrating data priority from said PCI-E ports; a URD (upstream range decoding) logic, decoding the data from said port arbiter; a downstream arbiter, receiving the data and arbitrating data priority from said microprocessor and said URD logic; a DARD (downstream address range decoding) logic, decoding the data from said downstream arbiter; and a device arbiter, receiving the data and arbitrating data priority from said URD logic and said DARD logic and dispatching the data to a corresponding PCI-E port chosen from said PCI-E ports; wherein said URD logic dispatching data to said microprocessor if the data hit an on board range table, to said device arbiter if the data hit an PCI-E device range table, or to said downstream arbiter if the data hit neither said PCI-E device range table nor said onboard range table.