Patent ID: 7068086
Filing Date: 2006-06-27
Classification: H04L

Abstract:
1. A phase correction circuit comprising: a variable delay device to which a data signal in a DDR format is inputted; first fetch means to fetch a delayed data signal outputted from the variable delay device in synchronization with a clock signal; second fetch means to fetch the delayed data signal in synchronization with a reverse clock signal obtained by reversing the clock signal; third fetch means to fetch an output signal from the first fetch means in synchronization with the clock signal; and fourth fetch means to fetch an output signal from the second fetch means in synchronization with the clock signal, the phase correction circuit further comprising: fifth fetch means to fetch a rate signal having the same cycle as that of the data signal in synchronization with the clock signal; and an AND circuit to which an output signal from the third or fourth fetch means and an output signal from the fifth fetch means are inputted.