Patent ID: 8819475
Filing Date: 2014-08-26
Classification: G06F

Abstract:
1. A memory access circuit connected to a memory comprising a parallel interface and a system circuit configured to issue a memory access command to command access to the memory, the memory access circuit comprising: a phase locked loop configured to generate a PLL (Phase Locked Loop) output locked to a reference frequency of a reference signal; a first phy-clock tree configured to delay the PLL output and to generate a reference clock signal; a first delay locked loop configured to correct a clock skew between the reference clock signal and a system clock signal generated by the system circuit, and to generate a source signal of the system clock signal; a second delay locked loop configured to correct a clock skew between the reference clock signal and a phy-clock signal used in the memory access circuit, and to generate a source signal of the phy-clock signal; a first phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a first detection signal corresponding to the phase difference; a second phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a second detection signal corresponding to the phase difference; and a master delay locked loop configured to count the reference clock signal and to generate a delay correction signal, wherein the first delay locked loop determines a correction direction and a correction amount based on the first detection signal and the delay correction signal, respectively; and the second delay locked loop determines a correction direction and a correction amount based on the second detection signal and the delay correction signal, respectively.