Patent ID: 8916403
Filing Date: 2014-12-23
Classification: B28D,H01L

Abstract:
1. A method of producing a plurality of optoelectronic semiconductor chips comprising: a) providing a carrier wafer having a first surface and a second surface opposite the first surface, wherein a plurality of individual component layer sequences spaced apart from one another in a lateral direction are applied on the first surface, said component layer sequences each being separated from one another by separation trenches, and wherein an intermediate layer is arranged between the component layer sequences and the carrier wafer, and the intermediate layer is in direct contact both with the carrier wafer and the component layer sequences; b) introducing at least one crystal imperfection in at least one region of the carrier wafer which at least partly overlaps a separation trench in a vertical direction; c) removing at least portions of the intermediate layer from the first surface of the carrier wafer in a region of at least one separation trench so that the intermediate layer is completely punctuated in the region of the at least one separation trench in which the intermediate layer was removed or embrittling the intermediate layer in a region of at least one separation trench so that the intermediate layer becomes deformable to a lesser extent, wherein the region in which the intermediate layer was removed or embrittled overlaps with the crystal imperfection in a vertical direction at least partially; and d) singulating the carrier wafer along the at least one crystal imperfection into individual semiconductor chips, wherein each semiconductor chip comprises at least one component layer sequence.