Patent ID: 8675397
Filing Date: 2014-03-18
Classification: G11C,H01L

Abstract:
1. A static random access memory (SRAM) cell comprising: first and second inverters cross-coupled for data storage, each inverter including a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices (PGs) configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of PGs for writing, wherein: a first metal layer providing local interconnection to the first and second inverters, the first metal layer including: a second metal layer formed over the first metal layer, the second metal layer including a first word line and a second word line oriented in a second direction that is different from the first direction, wherein the first word line is a write word line and the second word line is a read word line; and a read port for reading, wherein the read port is different than the at least two ports coupled with the plurality of PGs for writing, wherein the read port includes at least two PDs in parallel and at least two PGs in parallel.