Patent ID: 9190369
Filing Date: 2015-11-17
Classification: G11C,H01L,H03K

Abstract:
1. A method of producing an integrated circuit, comprising: providing a semiconductor substrate; providing on said semiconductor substrate an active circuit and interconnect layer including a plurality of constituent metal layers; providing a plurality of vias extending through said semiconductor substrate from said active circuit and interconnect layer to a surface of said semiconductor substrate opposite said active circuit and interconnect layer; providing a plurality of bond pads on said surface and respectively axially aligned with said vias; electrically connecting said bond pads to said vias; providing a plurality of top bond pads on said active circuit and interconnect layer and wherein each is respectively axially aligned with one of said vias; electrically connecting at least one of said top bond pads to the associated vias, and the providing the plurality of top bond pads including providing another at least one of said top bond pads that includes at least one top bond pad that is: electrically isolated relative to the associated axially aligned via; and electrically connected to a via that is offset from the associated axially aligned via.