Patent ID: 6629251
Filing Date: 2003-09-30
Classification: G06F,H04J

Abstract:
An elastic store with programmable delay comprising:a vernier circuit having a first input to receive a reference clock at a first frequency, a second input to accept a fine delay control signal, and an output to provide a delayed reference clock having a phase delay relative to the reference clock, the delayed reference clock being provided in response to the fine delay control signal; and a first in/first out (FIFO) circuit having a first input to receive input data, a second input to accept a write (WR) clock at a second frequency, synchronous to the first frequency, and a third input to accept a read (RD) clock at the second frequency, the RD clock having said phase delay relative to the WR clock, said FIFO having an output to provide the input data at the second frequency, whereby the input data are delayed in response to the WR clock signal and the RD clock signal.