Patent ID: 7043617
Filing Date: 2006-05-09
Classification: G06F,G11C

Abstract:
1. A system, comprising: a bus for transferring information; a memory, coupled to the bus, comprised of a memory device which is interchangeably of a mode selected from the group consisting of burst extended data out mode and fast page mode, the memory having a first set of access control signal timing requirements for the burst extended data out mode and a second set of access control signal timing requirements for the fast page mode; a programmable memory controller, coupled to the bus and to the memory, capable of providing the first set of access control signal timing requirements and the second set of access control signal timing requirements to the memory; and a processor, coupled to the bus and the memory controller, responsive to at least information from the memory to program the memory controller to provide a set of access control signals to the memory in accordance with the memory device mode, wherein the information from the memory includes data read from the memory device, wherein the processor is adapted to indicate an extended data out mode with data read from memory matching data written to the memory at address n using a data pattern in a format selected from a group consisting of single discrete cycles and pane mode cycles, and with the data read from memory matching the data written to the memory at address n+3 in a burst format.