Patent ID: 8912640
Filing Date: 2014-12-16
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first semiconductor chip having a first top surface over which a plurality of first pads are formed, and a first back surface opposite the first top surface; a second semiconductor chip having a second top surface over which a plurality of second pads are formed, and a second back surface opposite the second top surface; a first chip mounting portion having a first upper surface over which the first semiconductor chip is mounted via a first adhesive material, a first lower surface opposite the first upper surface, and a plurality of side surfaces located between the first upper and lower surfaces in a thickness direction of the first chip mounting portion; a second chip mounting portion having a second upper surface over which the second semiconductor chip is mounted via a second adhesive material, a second lower surface opposite the second upper surface, and a plurality of side surfaces located between the second upper and lower surfaces in a thickness direction of the second chip mounting portion; a plurality of leads arranged around the first and second chip mounting portions in plan view; a plurality of conductive materials electrically connecting to the leads and the first and second pads of the first and the second semiconductor chips respectively; and a resin sealing body having a first sealing body side, a second sealing body side opposite the first sealing body side, a third sealing body side, and a fourth sealing body side opposite the third sealing body side, the first and second sealing body sides extending along a first direction, the third and fourth sealing body sides extending along a second direction perpendicular to the first direction, and the resin sealing body sealing the first and second semiconductor chips, a part of each of the first and second chip mounting portions, and a part of each of the leads such that the first and second lower surfaces of the first and second chip mounting portions are exposed from the resin sealing body, wherein the first and second chip mounting portions are located side by side between the first and second sealing body sides, and the second chip mounting portion is located between the first chip mounting portion and second sealing body side in plan view, wherein the first chip mounting portion has a first side surface and the second chip mounting portion has a second side surface which faces the first side surface, and a portion of the resin sealing body is disposed between the first and second side surfaces, wherein the first side surface has a first portion continued to the first lower surface of the first chip mounting portion and a second portion located outwardly of the first portion and continued to the first upper surface of the first chip mounting portion, each of the first and second portions facing in the same direction, wherein the second side surface has a third portion continued to the second lower surface of the second chip mounting portion and a fourth portion located outwardly of the third portion and continued to the second upper surface of the second chip mounting portion, each of the third and fourth portions facing in the same direction, and wherein, in plan view, the first upper surface of the first chip mounting portion overlaps with a first virtual line which connects a center point of the third sealing body side and a center point of the fourth sealing body side in the first direction.