Patent ID: 6185637
Filing Date: 2001-02-06
Classification: G06F

Abstract:
A system for providing adaptive burst lengths of data, comprising:a CPU core coupled to a local bus;a bus interface unit coupled between said local bus and a system bus, wherein said bus interface unit is configured to receive a memory request from the CPU core via the local bus and to perform a memory operation via said system bus in response to said memory request;a memory device coupled to said system bus, wherein said memory device is configured to respond to said memory operation;wherein said bus interface unit is configurable to:use a stored value maintained in the bus interface unit to control a burst length for the memory operation;measure a response time of said memory device during said memory operation; andmodify the stored value used to control the burst length for the memory operation dependent upon the response time maintain information correlating: (i) address ranges of the memory device, (ii) values indicative of responsive times of memory operations comprising memory addresses falling within the address ranges of the memory device, and (iii) burst lengths to be used during memory operations comprising memory addresses falling within the address ranges of the memory device.