Patent ID: 8930869
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A wiring-design aiding method for causing a computer to execute: generating, by using the computer, wiring paths for buses for wiring layers of a circuit, where a bus includes wires as nets, according to wiring rules including a wiring rule so that the buses do not cross each other with respect to a wiring area including at least one wiring layer; and generating a directed graph of wiring cells for components, a wiring cell representing a number of wiring paths as wiring capacity for the buses of the components and a set wiring path bottleneck that limits a wiring capacity corresponding to component pin information in the wiring cell, and of directed edges interconnecting the wiring cells, a directed edge assigned a wire capacity corresponding to the component pin information, thereby modeling a network flow of usable wiring paths searchable for wiring paths of the buses with the set wiring path bottlenecks to verify successful extraction of a bus from a component to which the bus is connected according to the wiring rules, the bus-wire-path generation and verification are re-executed with respect to a bus for which it is determined in the verification that at least one of the buses is not successfully extracted.