Patent ID: 6074904
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method for isolating semiconductor devices, comprising:providing a semiconductor substrate, wherein said semiconductor substrate includes a first pair of source/drain regions laterally displaced on either side of a first channel region and a second pair of source/drain regions laterally displaced on either side of a second channel region, and wherein one of said first pair of source/drain regions is proximal to one of said second pair of source/drain regions;introducing a first well impurity concentration into a first well region of said semiconductor substrate wherein a depth of said first well region is greater than a depth of said first pair of source/drain regions and wherein said first well region encompasses said first pair of source/drain regions;introducing a second well impurity concentration into a second well region of said semiconductor substrate wherein a depth of said second well region is greater than a depth of said second pair of source/drain regions and wherein said second well region encompasses said second pair of source/drain regions;after introducing said first and second well impurity concentrations, forming laterally displaced first and second MOS transistors partially within said semiconductor substrate, wherein a gate of said first MOS transistor is aligned over said first channel region and wherein a gate of second MOS transistor is aligned over said second channel region;forming an isolation trench into said semiconductor substrate, wherein said trench is placed laterally between said proximal source/drain regions, wherein a depth of said trench is greater than a depth of said first and second pairs of source/drain regions; andfilling said trench with a trench dielectric material such that said proximal source/drain regions are electrically isolated from one another whereby said first transistor is electrically isolated from said second transistor.