Patent ID: 6842369
Filing Date: 2005-01-11
Classification: G11C

Abstract:
1. An intermesh memory device, comprising: memory components each configured to have a determinable resistance value, the memory components formed as a first memory array with a first set of the memory components and formed as a second memory array with a second set of the memory components, the first and second memory arrays each having rows of the memory components substantially perpendicular to columns of the memory components such that the first memory array rows and columns of the memory components are interconnected with the second memory array rows and columns of the memory components; electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components; and wherein a first electronic switch is electrically coupled to drive an input of a memory component and a second electronic switch is electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component.