Patent ID: 6747324
Filing Date: 2004-06-08
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit device, comprising:a first n-channel MISFET and a second n-channel MISFET of a memory cell, each having a gate electrode; a first p-channel MISFET and a second p-channel MISFET of said memory cell, each having a gate electrode; a first insulating film formed on the gate electrodes of the first and second n-channel MISFETs and the first and second p-channel MISFETs; a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, the gate electrode of said second n-channel MISFET, and the gate electrode of said second p-channel MISFET; a dielectric film formed on said first conductive film; and a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, the gate electrode of said first n-channel MISFET, and the gate electrode of said first p-channel MISFET, wherein a capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film, and wherein said second conductive film is formed over said first conductive film, the drain regions of the first and second n-channel MISFETs, and the drain regions of the first and second p-channel MISFETs to cover said first conductive film, the drain regions of the first and second n-channel MISFETs, and the drain regions of the first and second p-channel MISFETs.