Patent ID: 9023709
Filing Date: 2015-05-05
Classification: H01L

Abstract:
1. A method, comprising: forming a transistor structure comprising a gate electrode, a source region and a drain region in and above a semiconductor layer; forming an insulating layer above the surface of said semiconductor layer after forming said transistor structure; performing a first etch process in order to form at least one opening in a predetermined portion of said insulating layer; performing an ion implantation so as to implant impurity ions into an upper portion of said insulating layer; and performing a second etch process so as to remove at least a portion of said insulating layer comprising the implanted impurity ions after performing said ion implantation; wherein during said second etch process said upper portion of said insulating layer comprising the implanted impurity ions is etched at a different rate from the remaining portion of said insulating layer.