Patent ID: 6338988
Filing Date: 2002-01-15
Classification: H01L

Abstract:
A method for forming a thin film transistor having source and drain electrodes self-aligned to a gate electrode by employing a single lithographic step, comprising the steps of:forming an opaque gate electrode on a substrate; depositing a first dielectric layer on the gate electrode and the substrate; depositing a semiconductor layer on the first dielectric layer; depositing a second dielectric layer on the semiconductor layer; depositing a first photoresist on the second dielectric layer and patterning the first photoresist by employing the gate electrode as a mask for blocking light used to expose the first photoresist; etching the second dielectric layer to form a top insulator portion of the second dielectric layer in alignment with the gate electrode; removing the first photoresist; depositing a doped semiconductor layer; depositing a conductive layer on the doped semiconductor layer; forming a second photoresist on the conductive layer; patterning the second photoresist to form patterns for components and to form a contiguous transistor electrode pattern covering the top insulator portion; non-selectively etching the second photoresist and the conductive layer to form a gap in the second photoresist for the transistor electrode pattern at the top insulator portion; and etching the conductive layer and the doped semiconductor layer selective to the second photoresist such that a source electrode and a drain electrode are formed which are self-aligned relative to the gate electrode.