Patent ID: 7122417
Filing Date: 2006-10-17
Classification: H01L

Abstract:
1. A method of fabricating a CMOSFET comprising: forming a plurality of gate patterns on a first region and a second region of a semiconductor substrate; then forming gate spacers on both sidewalls of the gate patterns; then forming a first impurity region of a first conductivity type in the first region of the semiconductor substrate; then removing the gate spacers exposed at the first region; then forming a second impurity region of the first conductivity type in the first region from which the gate spacers have been removed, the second impurity region having shallower depth than the first impurity region; forming a third impurity region of a second conductivity type in the second region; then removing the gate spacers exposed at the second region; and then forming a fourth impurity region of the second conductivity type in the second region, the fourth impurity region having shallower depth than the third impurity region; wherein the first impurity region has higher impurity concentration than the second impurity region; and wherein the fourth impurity region has impurity concentration as high as the third impurity region.