Patent ID: 7493538
Filing Date: 2009-02-17
Classification: G01R

Abstract:
1. A process of adapting a synthesized scan path for low power operation, the scan path being arranged specifically for certain functional logic circuitry, the scan path being formed of scan cells having a stimulus path connected with logic circuitry and a response path connected with the logic circuitry, in each cell the stimulus path and the scan path being connected together, comprising: A. partitioning the scan path into multiple separate scan path sections of scan cells, each scan cell having a stimulus path connected to the scan path, each section having a scan input and a scan output; B. forming a connection between the scan inputs of each scan path section; C. forming a selective connection between the scan outputs of each scan path section; D. providing a scan control circuit having a group of scan control inputs and separate groups of scan control outputs; and E. forming separate connections between each of the separate groups of scan control outputs and one of the scan path sections.