Patent ID: 6035315
Filing Date: 2000-03-07
Classification: G06F

Abstract:
In a processor including a plurality of control registers that store flags configured according to various conditions in the processor, an apparatus that controls power consumed by a floating point unit (FPU) in a processor, comprising:instruction issue circuitry that controls issuance of a series of processor instructions;execution pipeline circuitry coupled to the instruction issue circuitry that indicates the various conditions according to which the flags are configured; andserialization logic coupled to the control registers and to the instruction issue circuitry, the serialization logic configuring the flags to indicate that the FPU is not required by a plurality of instructions in the series, wherein when the serialization logic detects an instruction in the series that requires execution of a subsequent instruction that requires the FPU, the serialization logic configures the flags to indicate that the FPU is required, wherein, when the flags are configured to indicate that the FPU is not required, a clock signal to the FPU is disabled by power conservation logic coupled to the instruction issue circuit.