Patent ID: 6147532
Filing Date: 2000-11-14
Classification: H03K,H03L

Abstract:
A PLL circuit including a voltage controlled oscillator that includes an odd number of stages of inverters, said PLL circuit comprising:a first delay circuit connected between two adjacent inverters of said inverters;a first delay control circuit for controlling a delay time of said first delay circuit in response to a first delay control circuit external command;a buffer circuit connected to a last stage of said inverters for producing a first clock signal with a period at which said PLL circuit locks; andan operational circuit for carrying out logic operation between a first input and a second input, and for generating a second clock signal, at least one of a duty and a frequency of said second clock signal being different from that of said first clock signal, said first input being at least one signal selected from among an output signal of said first delay circuit and output signals of said inverters, and said second input being a signal output from said inverters, wherein said signal output from said inverters is also input to said buffer circuit.