Patent ID: 6678860
Filing Date: 2004-01-13
Classification: G06F,G11C,H03M

Abstract:
An integrated circuit memory device, comprising:a memory cell array having a plurality of entries therein that comprise a plurality of data bits and a plurality of parity bits; a first pipeline stage that is configured to latch-in data bits and parity bits read from said memory cell array, in-sync with a first clock signal; a second pipeline stage that is configured to latch-in data bits output from said first pipeline stage, in-sync with a second clock signal; an error check circuit that is configured to receive data bits and parity bits output from said first pipeline stage, said error check circuit configured to operate in parallel with said second pipeline stage by generating syndrome data in-sync with the second clock signal; and an error correction circuit electrically coupled to an output of said second pipeline stage and an output of said error check circuit, said error correction circuit configured to generate corrected read data in response to data bits output from said second pipeline stage and the syndrome data generated by said error check circuit in parallel with the data bits output from said second pipeline stage.