Patent ID: 7472260
Filing Date: 2008-12-30
Classification: G06F

Abstract:
1. A processor comprising: a retire unit configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation, wherein retiring the first store memory operation comprises releasing resources used to track the first store memory operation as a speculative operation; a load/store unit coupled to the retire unit, wherein the load/store unit comprises a queue, and wherein the load/store unit is configured to retain the first store memory operation in a first entry of the queue subsequent to retirement of the first store memory operation if the first store memory operation is not complete, wherein the first entry is assigned to the first store memory operation; and a mapper configured to assign the first entry to the first store memory operation prior to issuance of the first store memory operation for execution.