Patent ID: 6765287
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A three-dimensional stacked semiconductor package, comprising:a first semidconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip and does not extend to the second surface of the first chip and is formed without bending the first conductive trace, and the first surface of the first pillar faces away from the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip and does not extend to the second surface of the second chip and is formed without bending the second conductive trace, and the first surface of the second pillar faces away from the first surface of the second chip; and a conductive bond that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and the first surface of the first pillar is between the first and second surfaces of the second chip.