Patent ID: 7395487
Filing Date: 2008-07-01
Classification: H03M,H04L

Abstract:
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising: a FIFO (First-In First-Out) buffer that is operable to receive and subsequently to provide a plurality of edge messages with respect to a plurality of check nodes; a bit node processing functional block that is operable to receive a bit metric that corresponds to a symbol of the LDPC coded signal, the plurality of edge messages with respect to the plurality of check nodes, and one edge message of the plurality of edge messages with respect to the plurality of check nodes from the FIFO buffer, and that comprises: wherein the FIFO buffer is also operable to receive and subsequently to provide the plurality of updated edge messages with respect to the plurality of bit nodes; and a check node processing functional block that is operable to receive the plurality of updated edge messages with respect to the plurality of bit nodes from the bit node processing functional block and that comprises: