Patent ID: 6744096
Filing Date: 2004-06-01
Classification: H01L

Abstract:
A non-volatile memory device comprising:a plurality of word lines formed on a semiconductor substrate comprising active areas, wherein the active areas are spaced by field areas and extend in a first direction while being repeatedly arranged in a second direction orthogonal to the first direction, wherein the word lines extend in the second direction while being repeatedly arranged in the first direction; a plurality of string select lines that are adjacent to a first word line among the word lines and extend in the second direction and a plurality of ground select lines that are adjacent to a last word line among the word lines and extend in the second direction; a first insulating interlayer formed on the word lines, the string select lines, the ground select lines and the semiconductor substrate, wherein said first insulating interlayer comprises a first opening for partially exposing an active area formed between the ground select lines and a second opening for partially exposing an active area formed between the string select lines; a bit line contact pad formed in the second opening, a sidewall of the bit line contact pad comprising a negative slope in the first direction and a positive slope in the second direction; a hard mask layer pattern formed on the bit line contact pad and the first insulating interlayer, said hard mask pattern comprising a same pattern size as the active area; and a second insulating interlayer formed on the hard mask layer pattern and the first insulating interlayer, said second insulating interlayer comprising a bit line contact hole for exposing the bit line contact pad.