Patent ID: 6515530
Filing Date: 2003-02-04
Classification: G06F,Y02D

Abstract:
A clock generator for a system comprising:a voltage regulator receiving a scalable logic power supply voltage of said system and generating a substantially constant power supply voltage, wherein said power supply voltage is a voltage level lower than a lowest voltage level of said scalable logic power supply voltage used for said system; a phase lock loop circuit, powered by said power supply voltage, receiving a reference clock signal, a feedback clock signal and generating a phase lock loop output signal, said feedback clock signal generated by frequency dividing said phase lock loop output signal; and a first programmable frequency divider receiving said phase lock loop output signal, first control signals and generating a frequency scalable clock signal as a system clock for said system in response to said first control signals, wherein a frequency of said phase lock loop output signal is greater than or equal to a maximum frequency of operation of said system corresponding to a highest voltage level of said scalable logic power supply voltage.