Patent ID: 7974142
Filing Date: 2011-07-05
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal, wherein the control signal is generated by delaying an enable signal by a first delay time; a delay unit configured to delay the enable signal by a second delay time shorter than the first delay time to output a delayed enable signal; a control unit configured to output a pre-control signal in response to the control signal and the delayed enable signal; and a pre-driver configured to, in response to the pre-control signal, decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage.