Patent ID: 6337227
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method of fabricating a multi-level stack of semiconductor substrate elements, each of said elements including integrated circuitry, comprising:providing a first semiconductor substrate element having a first side including integrated circuitry thereon and having a back side; providing at least one second semiconductor substrate element having a first side including a plurality of integrated circuitry thereon and having a backside; stacking said first semiconductor element and said at least one second semiconductor substrate element in a superimposed relationship having the back side of the first semiconductor substrate element facing the back side of the at least one second semiconductor substrate element; aligning vertically said first semiconductor substrate element and the at least one second semiconductor substrate element to vertically align integrated circuitry on said first semiconductor substrate element and at least one of the plurality of integrated circuits on said at least one second semiconductor substrate element; and severing from said stack traversely at least one dice pair comprising a die from said first semiconductor substrate element and an aligned die from said at least one second semiconductor substrate element.