Patent ID: 7563669
Filing Date: 2009-07-21
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, comprising: providing a semiconductor layer having an upper surface; forming a trench in the semiconductor layer upper surface, the trench having a bottom portion and a wall portion extending from the upper surface to the bottom portion; growing by thermal oxidation a layer of silicon oxide on said bottom portion and along the wall portion, depositing a high density plasma silicon oxide over the thermal oxidation layer of silicon oxide and filing the trench with the high density plasma silicon oxide; removing a portion of the high density plasma silicon oxide from the trench to leave a remaining layer of the high density plasma silicon oxide on the bottom portion, the removing including removing the thermal oxidation layer of silicon oxide from the wall portion; implanting ions in the semiconductor layer in the region adjacent said wall portion to form a first capacitor plate; forming a layer of dielectric material on the wall portion; forming an in-situ doped first polysilicon layer along the wall portion to form a second capacitor plate having a substantially uniform dopant concentration along the remaining layer of the high density plasma and along the layer of dielectric material on the wall portion; and depositing a second doped polysilicon layer over the doped first polysilicon layer, wherein the second doped polysilicon layer is formed over the doped first polysilicon layer within the trench and is patterned to form both a conductive layer over the first layer and a gate runner for a transistor.