Patent ID: 6728944
Filing Date: 2004-04-27
Classification: G06F

Abstract:
A method in a data processing system for improving wireability near clock nets in a logic design that includes a plurality of logic blocks, said method comprising the steps of:identifying ones of said plurality of logic blocks that are a particular type of logic block each one of said plurality of logic blocks having an actual physical size; during placement of said plurality of logic blocks and synthesis of said logic design, utilizing an apparent physical size for each of said identified ones of said plurality of logic blocks as a physical size for said identified ones, said apparent physical size being larger than said actual physical size identified ones; and during routing, utilizing said actual physical size for each of said identified ones of said plurality of logic blocks as the physical size for said identified ones; identifying a maximum physical size for each one of said plurality of logic blocks that are a particular type; specifying a perimeter buffer size: and specifying said apparent physical size to be equal to said maximum physical size plus said perimeter buffer size.