Patent ID: 7337154
Filing Date: 2008-02-26
Classification: G06F,G06N,Y10S

Abstract:
1. A method of digital logic circuit design, comprising: a) Storing a complementary pair of truth tables T and F in a computer, said truth tables representing an initial configuration of logic gates to map from logic inputs to a single bit output of a digital logic circuit; b) Iteratively subdividing the T truth table into pairs of sub-tables along branches at progressively lower levels until the remaining sub-tables are smaller than a threshold size; c) Using a genetic algorithm to solve each of the sub-tables at the lowest level independently from respective seed organisms as a sub-solution; d) For each pair of sub-tables at the lowest remaining level, combining their sub-solutions to form the seed organism to seed the genetic algorithm to solve the sub-table at the next higher level up the branch and refine the sub-solution; and e) Repeating step (d) at least once to generate a solution; and f) Storing the solution in the computer, said solution representing a configuration of logic gates for the digital logic circuit to map the logic inputs to the single bit output that requires fewer gates than said initial configuration.