Patent ID: 7130988
Filing Date: 2006-10-31
Classification: G06F

Abstract:
1. A system for optimizing pipeline microprocessor logic for status register updates, comprising: a storage unit for storing instructions; a register file; a fetch unit, forming a portion of a processing pipeline, for fetching a status instruction and then fetching a next instruction from said storage unit and communicating with said register file; and a decode unit, coupled to said fetch unit and forming another portion of said processing pipeline, for decoding said status instruction from said fetch unit, and subsequently decoding said next instruction from said fetch unit, wherein said decoding of said next instruction depends upon a system status, and wherein upon detection of said status instruction by a status change handler within said decode unit, said decode unit causes said system to wait obtaining said next instruction for decoding by assigning a number of clock cycles to said next instruction to allow a status change generated by executing said status instruction to propagate through said processing pipeline.