Patent ID: 6228695
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method of forming split-gate flash memory cell having a self-aligned source as well as a floating gate self-aligned to control gate comprising the steps of:providing a silicon substrate having a plurality of active and field oxide isolation regions defined by shallow trench isolation (STI) regions;forming a first gate oxide layer over said substrate;forming a first polysilicon (poly-1) layer over said first gate oxide layer;forming a silicide layer over said poly-1 layer;forming a tetraethyl orthosilicate (TEOS) layer over said silicide layer;forming a first photoresist layer over said TEOS layer;patterning said first photoresist layer to define a control gate area;etching said TEOS layer and said silicide layer through said patterning in said first photoresist layer and forming opening in said TEOS layer exposing portion of said poly-1 layer;etching said exposed portion of said poly-1 layer and forming a control gate;removing said first photoresist layer;forming a second gate oxide layer over said substrate;forming a partial-depth second polysilicon (poly-2) layer over said second gate oxide layer;etching said partial-depth poly-2 layer to form a drain spacer and a source spacer and a sharp peak therein;forming a second photoresist layer over said substrate to define a self-aligned source (SAS) region;etching partially said field oxide isolation layer through said second photoresist layer in said SAS region;removing said second photoresist layer;forming a third photoresist layer over said substrate with openings exposing said poly-2 drain spacer and said poly-2 covering said STI regions;etching through said openings in said third photoresist layer to remove said poly-2 drain spacer and said poly-2 covering said STI regions to form a floating gate cell;forming a fourth photoresist layer over said substrate to redefine a self-aligned source (SAS) region;etching completely said field oxide isolation layer through said fourth photoresist layer until said silicon substrate is reached in said SAS region;ion implanting said SAS region;removing said fourth photoresist layer;annealing said silicide layer;forming a drain in said substrate; forming an interlevel dielectric layer (ILD) over said substrate; andforming a metal contact in said ILD layer to complete the forming of said split-gate flash memory cell.