Patent ID: 6202168
Filing Date: 2001-03-13
Classification: G01R,H04L

Abstract:
A circuit for regulating delay time of signal transmission of data signal on a signal path between a signal sending circuit included in a first logic circuit and a signal receiving circuit included in a second logic circuit, said circuit comprising:a variable delay circuit inserted in said signal path;a signal generator generating a standard signal;connecting means for providing said standard signal to said signal sending circuit so that said standard signal is transferred to said signal receiving circuit through said signal path, instead of said data signal;a phase comparator comparing a phase of a transferred standard signal which is transferred through said signal path with a phase of a reference signal which originates in said standard signal and is transferred to said phase comparator through an additional signal path; andadjusting means for adjusting delay time of said variable delay circuit in response to an output of said phase comparator so that a difference between the phase of said transferred standard signal and the phase of said reference signal becomes smaller.