Patent ID: 6284585
Filing Date: 2001-09-04
Classification: G11C,H01L

Abstract:
A method of reading an electronic memory device that includes:a block of cells connected in a predetermined circuit configuration, the block including a selected memory cell having first and second conduction terminals and a control terminal;first and second contact regions positioned at opposite ends of a selected block, the first contact region including first and second contacts;parallel continuous conduction lines, referred to as bit lines, that interconnect the first and second contact regions, the conduction lines including first and second bit lines coupled to the first and second contacts, respectively;a plurality of controlled switches respectively situated in the bit lines to function as a block selector and provide interruptions in the bit lines, a selected one of the controlled switches having a control terminal, a first terminal coupled to the first contact, and a second terminal coupled to the first conduction terminal of the selected memory cell; andan address transistor coupling the second bit line to the second conduction terminal of the selected memory cell, the method comprising:applying a read voltage to the second contact and the control terminals of the controlled switch and the selected memory cell;turning ON the address transistor to couple the second conduction terminal of the selected memory cell to the second contact; andcoupling the first contact to ground while performing the applying step.