Patent ID: 6519196
Filing Date: 2003-02-11
Classification: G11C

Abstract:
A high sensitive data signal amplifying circuit comprising:bit line amplifying means for amplifying data stored at a memory cell and loading the amplified data on one of a bit line and a bit bar line; column address selecting means for transferring an output signal of the bit line amplifying means depending on a column address signal; first data signal amplifying means for amplifying a data signal transferred by the column address selecting means, wherein the first data signal amplifying means comprises: sense amplifying means for amplifying the output signal of the column address selecting means by using a first stand-by signal and an equalizing signal as control signals; and precharging means for precharging the sense amplifying means by using the first stand-by signal as a control signal; second data signal amplifying means for amplifying an output signal from the first data signal amplifying means; and data signal transferring means for transferring an output signal of the second data signal amplifying means to output to buffering means.