Patent ID: 6327695
Filing Date: 2001-12-04
Classification: H01L

Abstract:
Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise, the computer readable media comprising:program instructions for designing a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions, the plurality of dummy active regions being separated from the plurality of active regions by at least a bloat distance; andprogram instructions for designing a network of dummy polysilicon lines being configured to overlie selected dummy active regions, the network of dummy polysilicon lines that overlie the selected dummy active regions functioning as dummy gates that interconnect the plurality of dummy active regions;wherein the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions define capacitor structure locations for the network of on-chip capacitive structures.