Patent ID: 7454594
Filing Date: 2008-11-18
Classification: G06F

Abstract:
1. A processor comprising: a plurality of registers, each of said registers comprising only one first part and only one second part, said first part registering high-order bits and said second part registering low-order bits; and an arithmetic unit performing a first arithmetic operation on data from the first parts of said plurality of registers, and a second arithmetic operation on data from the second parts of said plurality of registers according to a SIMD instruction, simultaneously, the arithmetic unit with a data width of (a) bits being used as a plurality of (b)-bit arithmetic units to simultaneously process the SIMD instruction on a plurality of discrete elements in each of the (b)-bit arithmetic units respectively, (a) and (b) being positive integers, and (a) being a multiple of (b), wherein the SIMD instruction comprises an operand that designates, independently and respectively, only the first part of one of the plurality of registers to store a result of the first arithmetic operation and only the second part of another one of the plurality of registers to store a result of the second arithmetic operation, and wherein said processor stores the result of said first arithmetic operation into said only one of the first parts of said plurality of registers according to the operand of the SIMD instruction and the result of the second arithmetic operation into said only one of the second parts of the plurality of registers according to the operand of the SIMD instruction.