Patent ID: 6173490
Filing Date: 2001-01-16
Classification: B29C,H01L,Y10T

Abstract:
A method of forming a panel of packaged integrated circuits, comprising:providing a substrate panel having a plurality of electrically conductive interconnects;attaching a multiplicity of integrated circuits to the substrate panel;placing the substrate panel in a mold having a molding chamber with a two dimensional array of immediately adjacent package recesses flowably interconnected by way of a plurality of molding compound flowgates, each package recess being suitable for receiving an associated one of the integrated circuits; andpassing molding compound into the molding chamber by way of a mold gate, wherein at least some of the molding compound passes through a plurality of different package recesses by way of associated flowgates, thereby substantially encapsulating the plurality of integrated circuits within the molding chamber by substantially filling their associated package recesses, and wherein most of the package recesses directly receive molding compound from at least two immediately adjacent package recesses.