Patent ID: 7467288
Filing Date: 2008-12-16
Classification: G06F

Abstract:
1. A computer processor having a vector register architecture for processing operations that use data vectors each comprising a plurality of data elements, the vector register architecture comprising: a vector data file comprising a plurality of storage elements for storing data elements of the data vectors; a pointer array electrically coupled by a bus to the vector data file, the pointer array including a plurality of entries wherein each entry identifies at least one storage element in the vector data file, wherein the entries are grouped into addressable words corresponding to individual data vectors stored in the vector data file, wherein the words are addressed by a word address decoder coupled to the pointer array; the at least one storage element for storing at least one data element of the data vectors, wherein for at least one particular word in the pointer array, the at least one storage element identified by the particular word has an arbitrary starting address in the vector data file; and wherein the pointer array includes at least one word which is updated based on one of data read out from at least one data element in the vector data file and data generated by performing an increment operation on data read from at least one word of the pointer array, wherein the entries of the at least one word are updated as part of a same logical operation.