Patent ID: 7881130
Filing Date: 2011-02-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a data write circuit which receives a write data; a sense amplifier coupled to a data line; an output data terminal coupled to said data line; a switch coupled between said data write circuit and said data line; a control circuit which turns on said switch based on a write control signal and a sense amplifier activation control signal during a write data through mode; at least one digit line pair coupled to at least one memory cell; a read data line pair; a Y switch coupled between said digit line pair and said read data line pair; a data line separation switch coupled between said read data line pair and said data line pair connected to said sense amplifier; an output circuit coupled to said data line pair connected to said sense amplifier; an output data terminal coupled to said output circuit; a latch circuit which latches write data input into an input data terminal; a write buffer which receives and outputs said write data; and a write data line pair connected to said write buffer; wherein: