Patent ID: 9029956
Filing Date: 2015-05-12
Classification: G11C,H01L,Y10S

Abstract:
1. A static random access memory cell formed on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node, comprising: each of the pull-down transistors of the first and second inverters formed in a silicon layer and over first regions of the substrate having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors; and a pair of passgate transistors having a drain respectively coupled the cell nodes of the first and second inverters and arranged such that the passgate transistor of the first inverter has a gate contact formed to align with the cell node of the second inverter and the passgate transistor of the second inverter has a gate contact formed to align with the cell node of the first inverter, and each passgate transistor being formed in the silicon layer and over second regions of the substrate having a second doping level and applied bias providing a second voltage threshold for the passgate transistors, the first voltage threshold differing from the second voltage threshold providing voltage threshold control between the pull-down transistors and the passgate transistors.