Patent ID: 8125410
Filing Date: 2012-02-28
Classification: G09G

Abstract:
1. A plasma display driven by a subfield system including a plurality of subfields into which each field is temporally divided, each of said plurality of subfields including a write period and a sustain period subsequent to said write period, said plasma display comprising: a plurality of data electrodes arranged in a vertical direction; a plurality of scan electrodes arranged in a horizontal direction; a plurality of sustain electrodes arranged in a horizontal direction so as to correspond to said plurality of scan electrodes, respectively; a plurality of discharge cells provided at intersections of said plurality of data electrodes, said plurality of scan electrodes and said plurality of sustain electrodes; a clock signal generator that generates a clock signal; a serial data generator that generates serial data according to an image to be displayed; a test signal generator that generates a test signal; a data driver that selectively applies a drive pulse to said plurality of data electrodes based on the serial data generated by said serial data generator in synchronization with said clock signal in a write period of each subfield, to cause a selected discharge cell to generate an address discharge; a driver that sequentially applies a drive pulse to said plurality of scan electrodes in said write period and alternately applies a sustain pulse to said plurality of scan electrodes and said plurality of sustain electrodes in said sustain period subsequent to said write period, to cause said selected discharge cell to generate a sustain discharge for display of an image; a latch failure detector that includes a latcher that latches the test signal generated by said test signal generator to detect a presence/absence of a latch failure in said data driver based on an output signal from said latcher in an adjustment period formed of a sustain period of one or a plurality of subfields; a phase adjuster that, when the latch failure is detected by said latch failure detector, adjusts a phase of the clock signal provided from said clock signal generator to said data driver, based on the phase of the clock signal in which the latch failure is detected; and a first storage device that stores the phase of the clock signal adjusted by said phase adjuster as an optimal phase, wherein said phase adjuster varies the phase of said clock signal to detect a phase range where no latch failure occurs, and stores, in said first storage device, a phase in a center of said detected phase range as said optimal phase during said adjustment period, and adjusts the phase of said clock signal to said optimal phase stored in said first storage device in the write period after said optimal phase is stored by said first storage device, and wherein said data driver includes a plurality of data drivers; said latch failure detector includes a plurality of latch failure detectors that detect the presence/absence of the latch failure by respective data drivers based on the test signal output from said test signal generator; and when the latch failure is detected in at least one of said plurality of latch failure detectors, said phase adjuster adjusts the phase of the clock signal provided to said plurality of data drivers from said clock signal generator.