Patent ID: 7337202
Filing Date: 2008-02-26
Classification: G06F

Abstract:
1. A shift-and-negate circuit within a fused multiply-adder circuit, said shift-and-negate circuit comprising: a large shift circuit for receiving a first set of shift signal inputs and a plurality of data signal inputs to generate a plurality of first intermediate signals; a coarse shift circuit for receiving a second set of shift signal inputs and said plurality of first intermediate signals to generate a plurality of second intermediate signals along with their complement signals, wherein said large shift circuit and said coarse shift circuit perform executions within a first processor cycle, wherein said large shift circuit and said coarse shift circuit share a common processor clock cycle; a negate circuit for receiving a complement decision signal input and said plurality of second intermediate signals along with their complement signals to generate a plurality of third intermediate signals, wherein said complement decision signal includes a complement signal and a not complement signal; and a fine shift circuit for receiving a third set of shift signal inputs and said plurality of third intermediate signals to generate a plurality of signal outputs to be utilized by said fused multiply-adder circuit, wherein said negate circuit and said fine shift circuit share a common processor clock cycle, wherein said negate circuit and said fine shift circuit perform executions within a second processor cycle immediately after said first processor cycle, such that a separate inversion circuit is not required for said shift-and-negate circuit.