Patent ID: 6667510
Filing Date: 2003-12-23
Classification: G11C,H01L

Abstract:
A self-aligned split-gate flash memory cell, comprising:a semiconductor substrate of a first conductivity type; a cell region having an active region and two shallow-trench-isolation regions formed on said semiconductor substrate and being divided into three regions: a common-source region, a gate region, and a common-drain region, wherein said gate region is located between said common-source region and said common-drain region with its control-gate length being defined by a fourth sidewall dielectric spacer being formed over a sidewall of said common-source region and said shallow-trench-isolation region is filled with a raised field-oxide layer; a common-source diffusion region of a second conductivity type being formed in said semiconductor substrate by implanting doping impurities in a self-aligned manner into said active region in said common-source region; a first flat bed being formed by said common-source diffusion region and nearby first etched raised field-oxide layers and a first sidewall dielectric spacer being formed over a sidewall of said gate region; a common-source conductive layer being formed over said first flat bed outside of said first sidewall dielectric spacer and a first planarized thick-oxide layer being formed over said common-source conductive layer and said first sidewall dielectric spacer; a common-drain diffusion region of a second conductivity type being formed in said semiconductor substrate by implanting doping impurities in a self-aligned manner into said active region in said common-drain region; a second flat bed being formed by said common-drain diffusion region and nearby second etched raised field-oxide layers and a second sidewall dielectric spacer being formed over another sidewall of said gate region; a common-drain conductive layer being formed over said second flat bed outside of said second sidewall dielectric spacer and a second planarized thick-oxide layer being formed over said common-drain conductive layer and said second sidewall dielectric spacer; and a self-aligned split-gate structure being formed in said gate region with a planarized control-gate being formed on the top and being divided into two subregions: a floating-gate region being formed near said common-source region and a select-gate region being formed near said common-drain region, wherein said floating-gate region comprises a floating-gate transistor being formed on a thin tunneling-dielectric layer with a floating-gate length being defined by a third sidewall dielectric spacer formed over said sidewall of said common-source region and said select-gate region comprises a select-gate transistor being formed over a gate-dielectric layer.