Patent ID: 6275963
Filing Date: 2001-08-14
Classification: G11C

Abstract:
A semiconductor integrated circuit device, comprising:a memory circuit under test which can output in parallel a plurality of output data corresponding to a plurality of bits based on an internally-stored content; anda test circuit having a plurality of scan flip flops (S-FFs) provided correspondingly to said plurality of output data, said plurality of S-FFs receiving serial output data of their respective preceding S-FFs as serial input data to be connected in series to one another,each of said plurality of S-FFs comprising:a comparison circuit for comparing at least one of said plurality of output data with at least one of expected value data corresponding thereto to output a comparison result data indicating whether there is a failure or not; andfailure-information transfer means receiving a group of failure judging data including said comparison result data in a first test mode, for outputting said serial output data indicating a failure when at least one data of said group of failure judging data indicate a failure, andsaid group of failure judging data of said failure-information transfer means in each of one or more serial S-FFs among said plurality of S-FFs further including said serial input data in addition to said comparison result data.