Patent ID: 6078535
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of standard memory cells;a plurality of bit lines;a plurality of standard word line sets, each standard word line set including:a first standard word line coupling to standard memory cells to a first combination of bit lines, the first standard word line being activated in response to a first combination of address bits, anda second standard word line coupling to standard memory cells to a second combination of bit lines, the second combination of bit lines being different than the first combination of bit lines, the second standard word line being activated in response to a second combination of the address bits;a plurality of transfer gates, each transfer gate having an input coupled to at least one of the bit lines and an output coupled to an output node, each transfer gate providing a low impedance path between its input and output when enabled;a plurality of redundant memory cells;a plurality of redundant word lines, each redundant word line coupling to selected redundant memory cells to different redundant combinations of bit lines; anda decoder circuit coupled to the plurality of transfer gates, the decoder circuit havinga standard mode in which the decoder circuit activates the transfer gates coupled to the first combination of bit lines in response to the first combination of the address bits and activates the transfer gates coupled to the second combination of bit lines in response to the second combination of the address bits, anda redundant mode in which the decoder circuit activates the transfer gates coupled to the redundant combination of bit lines of an activated redundant word line.