Patent ID: 6710616
Filing Date: 2004-03-23
Classification: G01R,G11C

Abstract:
A wafer comprising:a plurality of DRAM dies on the wafer, wherein each DRAM die has a test data in pad and a test data out pad; and conductive connections interconnecting the test data out and test data in pads of the DRAM dies, said conductive connection providing that said DRAM's can be burned-in on the wafer, wherein the DRAM dies on the wafer are arranged in rows, wherein each row comprises a plurality of DRAM dies and each DRAM die in a given row is daisy chained to the next DRAM die in the row, wherein the last DRAM die in a row is daisy chained to the first DRAM die in the next row via a metal line on a scribe area of the wafer, wherein the DRAM dies on the wafer are connected to power busses along a scribe area so that the dies can be powered.