Patent ID: 6615378
Filing Date: 2003-09-02
Classification: G01R,G11C

Abstract:
A network interface controller comprising:a testable memory arrangement; a computer bus interface for coupling the network interface controller to an external central processing unit (CPU); a memory built-in self test (MBIST) controller configured to test the memory arrangement with an MBIST and generate MBIST results; and a register coupled to the MBIST controller and the computer bus interface, the register configured to receive and store the MBIST results, and to be readable by a CPU through the computer bus interface, wherein the register includes a plurality of fields, and one of the fields is a data field that contains data read from the memory arrangement during the MBIST, the register includes an address field for storing an address at which the MBIST stopped, and the register includes offset information fields for storing information from which an offset of the address at which the MBIST was stopped is determined.