Patent ID: 7543119
Filing Date: 2009-06-02
Classification: G06F,G11C

Abstract:
1. A system including: a plurality of floating point execution units compatible with operation according to a plurality of execution threads; a plurality of memory channels each configured to access at least one Dynamic Randomly Accessible read/write Memory (DRAM) element; a memory buffer switch unit coupling the floating point execution units to the memory channels; an instruction control unit configured to control the floating point execution units according to a stream of vector instructions, wherein the multiple floating point execution units operate concurrently on parts of the same vector instruction; wherein the parts of multiple vector instructions are executed independently by the separate floating point execution units; wherein the parts of the vector instructions are completed out of order with respect to the parts in other floating point execution units; a processor interface compatible with an x86 processor and configured to receive the stream of vector instructions from the x86 processor, wherein the x86 processor controls the plurality of floating point units through a compatible interface; wherein the x86 processor, and the plurality of floating point units share access to coherent memory; and wherein the memory buffer switch is configured to consolidate at least two memory requests from the floating point execution units into a single memory access operation directed to one of the memory channels and the at least two memory requests are processed according to a coherency domain implemented by the x86 processor.