Patent ID: 9064895
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method of fabricating a vertical memory device, comprising: forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer, wherein the forming of the channel layer comprises: forming an undoped amorphous silicon layer on the tunnel insulating pattern; implanting N-type impurities into the undoped amorphous silicon layer to provide a doped amorphous silicon layer; crystallizing the doped amorphous silicon layer to form a polysilicon layer; and partially etching the polysilicon layer provide the channel layer.