Patent ID: 8248344
Filing Date: 2012-08-21
Classification: G09G

Abstract:
1. A method of driving a liquid crystal display panel of a dot inversion system having liquid crystal cells arranged at intersections between a plurality of data lines and a plurality of gate lines in a matrix array, the method comprising: supplying the data lines with (n-2)th data corresponding to the liquid crystal cells connected to an (n-2)th gate line, wherein n is an integer greater than 2; supplying a first gate start pulse; in response to the first gate start pulse, generating a first gate high pulse; in response to the first gate high pulse, conducting a first data supplying channel for the liquid crystal cells connected to an nth gate line such that the (n-2)th data is supplied to the liquid crystal cells connected to the nth gate line; supplying a second gate start pulse; in response to the second gate start pulse, generating a second gate high pulse; in response to the second gate high pulse, conducting a second data supplying channel for the liquid crystal cells connected to the (n-2)th gate line such that the (n-2)th data is supplied to the liquid crystal cells connected to the (n-2)th gate line, wherein a duration of the first gate high pulse is smaller than a duration of the first gate start pulse; wherein a duration of the second gate high pulse is smaller than a duration of the second gate start pulse; wherein conducting the first data supplying channel and conducting the second data supplying channel are performed substantially simultaneously, wherein the first and second gate start pulses are output from a pre-charging controller; wherein the pre-charging controller includes; a first input line supplied with a pre-gate start pulse and a second input line supplied with a data output enable signal (DOE) for controlling data output of a data driving integrated circuit, wherein the data driving integrated circuit applies data to the data lines in response to the data output enable signal, and wherein the data output enable signal is directly applied to the data driving integrated circuit and the pre-charging controller; first delay means for delaying the pre-gate start pulse from the first input line by one clock interval of the data output enable signal in response to the data output enable signal; second delay means for delaying the delayed pre-gate start pulse from the first delay means by one clock interval of the data output enable signal in response to the data output enable signal; and a gate device for executing an exclusive logical sum operation of the pre-gate start pulse from the first input line and an output signal of the second delay means to continuously output the first and second gate start pulses; wherein the liquid crystal cells connected to first and second gate lines of the plurality of gate lines are supplied with an active data signal after the liquid crystal cells connected to the first and second gate lines were charged in advance with a data signal at every frame with a data signal applied at a blanking interval; wherein the duration of the first gate high pulse is smaller than one clock interval; wherein the duration of the second gate high pulse is smaller than one clock interval; wherein the duration of the first gate high pulse consists of a first time during which a data signal is applied and a first switching time; wherein the duration of the second gate high pulse consists of a second time during which a data signal is applied and a second switching time; wherein the first time during which the data signal is applied is greater than the first switching time; wherein the second time during which the data signal is applied is greater than the second switching time; wherein polarity inversion of the data signals applied to the liquid crystal cells connected to the first and second gate lines is made in at least two clock time intervals prior to an application of the active data signal; wherein gate and data control signals for applying data to the liquid crystal cells connected to the first and second gate lines are applied in at least two clock time intervals before the gate and data control signals become effective data.