Patent ID: 8433838
Filing Date: 2013-04-30
Classification: G06F

Abstract:
1. A serial peripheral interface bus, comprising: a serial peripheral interface master device having a master output slave input pin, a master input slave output pin, a clock output pin, and a slave select output pin, each of the master device pins being coupled in parallel to a serial peripheral interface multiplex slave device and a plurality of serial peripheral interface non-multiplex slave devices, wherein the multiplex slave device includes an independent slave select output pin coupled to each one of the non-multiplex slave devices for sending an activation signal to a selected slave device in response to receiving a command from the master device containing the address of the selected slave; and wherein one of the independent slave select output pins of the multiplex slave and the slave select output pin of the master device are input to an OR circuit having an output coupled to a slave select input pin of one the plurality of non-multiplex slave devices.