Patent ID: 6809987
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A circuit for producing a selection signal to select memory cells, comprising:a first predecoder for selecting at least one erase block, including: a first input stage receptive to first and second control signals; a second input stage receptive to a multiple of multibit data signals; a first output stage to produce a first multibit selection signal according to one of three modes, wherein the first multibit selection signal is adapted to select at least two erase blocks in one of the three modes; a second predecoder for selecting at least one main block, including: a third input stage receptive to third, fourth, and fifth control signals; a fourth input stage receptive to the multiple of multibit data signals; and a second output stage to produce a second multibit selection signal according to one of four modes, wherein the second multibit selection signal is adapted to select at least two main blocks in one of the four modes.