Patent ID: 7321647
Filing Date: 2008-01-22
Classification: H04L

Abstract:
1. A clock extracting circuit for extracting a clock timing signal synchronous with input NRZ (Non-Return-to-Zero) type serial data from the serial data, said clock extracting circuit comprising: oversampling means for oversampling said serial data using a reference clock signal of 2N times a frequency of said serial data, where N is an integer of two or more; first timing detecting means for detecting the timing of 2N periods of said reference clock signal in a period of time in which the level of an output signal from said oversampling means remains unchanged; second timing detecting means for detecting the timing of change in the level of the output signal from said oversampling means; and clock timing signal outputting means for outputting the clock timing signal according to the timings detected by said first timing detecting means and said second timing detecting means.