Patent ID: 6118296
Filing Date: 2000-09-12
Classification: G01R

Abstract:
A semiconductor logic integrated circuit comprising:a macrocell having input and output terminals,a plurality of scan flipflop circuits connected to the input and output terminals of the macrocell, respectively, for supplying input data to the macrocell and receiving output data from the macrocell, the plurality of scan flipflop circuits having a through mode capable of causing data to pass through when the plurality of scan flipflop circuits are connected in cascade, anda plurality of scan-path-testable flipflop circuits operating as a shift register when the plurality of scan-path-testable flipflop circuits are connected in cascade,wherein in a normal operation, said input data and said output data are inputted and outputted by only the plurality of scan flipflop circuits having the through mode, and in a scan path test, the plurality of scan flipflop circuits having the through mode and the pluralitly of scan-path-testable flipflop circuits are connected in cascade for transmitting test data to said logic integrated circuit including said macrocell andwherein when a test pattern for performing the scan path test in the semiconductor logic integrated circuit is prepared, a test pattern having an indefinite signal supplied to an input of the scan flipflop circuits having the through mode, which are connected at an input side of the macrocell is prepared, and a test pattern having an indefinite signal supplied to an output of the scan flipflop circuits having the through mode, which are connected at an output side of the macrocell is prepared and respective values of the test pattern for the scan flipflop circuits having the through mode, which are connected at an input side of the macrocell, are replaced with input values of the test pattern separately prepared for testing the macrocell, and respective values of a test pattern for the scan flipflop circuits having the through mode, which are connected at the output side of the macrocell, are replaced with output values of a test pattern separately prepared for testing the macrocell.