Patent ID: 6806157
Filing Date: 2004-10-19
Classification: H01L,Y10S

Abstract:
A method for fabricating a MOS field effect transistor having a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate, the method comprising the steps of:forming first source/drain extension regions in the semiconductor substrate by implanting impurity ions using the gate electrode as an ion-implantation mask; forming first spacers on the sidewalls of the gate electrode and the gate insulation layer; forming second source/drain extension regions deeper than the first source/drain extension regions by performing impurity ion-implantation using the first spacers and the gate electrode as an ion-implantation mask; forming second spacers on outer walls of the first spacers; forming deep source/drain regions deeper than the second source/drain extension regions by performing impurity ion-implantation using the second spacers and the gate electrode as an ion-implantation mask; forming a first silicide layer portion having a first thickness in the upper portion of each of the deep source/drain regions; removing the second spacers to expose the surfaces of the second source/drain extension regions; and forming a second silicide layer portion having a second thickness less than the first thickness and extending from the first silicide layer portion into the upper portion of each of the exposed second source/drain extension regions.