Patent ID: 8927983
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A thin film transistor array substrate, comprising: a substrate comprising a display area and a non-display area, wherein the display area is surrounded by the non-display area; a thin film transistor located in the display area of the substrate; a first patterned metal layer disposed on the substrate, comprising: a gate electrode of the thin film transistor; a scan line electrically connected to the gate electrode, wherein the scan line is located in the display area and the non-display area; and a connecting line located in the non-display area; and a second patterned metal layer disposed on a gate insulating layer, comprising: a metal contact, a source electrode, and a drain electrode of the thin film transistor; and a signal line electrically connected to the source electrode and the drain electrode, all formed from the same patterned metal layer, wherein the signal line is located in the display area and the non-display area, wherein the gate insulating layer covers at least a portion of the scan line and the connecting line, the connecting line is in contact with the signal line at the non-display area via a first through-hole of the gate insulating layer, and the metal contact is in contact with the connecting line via a second through-hole of the gate insulating layer at the non-display area.