Patent ID: 6721875
Filing Date: 2004-04-13
Classification: G06F

Abstract:
A processor, comprising:a) a register file having a plurality of registers; b) an instruction set including instructions which address the registers, the instructions being encoded in bundles, with each bundle including a plurality of instructions grouped together in an X bit field, the instructions being located in instruction syllables of the X bit field, each instruction being one of a plurality of instruction types including integer, memory, floating-point and branch, wherein the branch instructions comprise: i) a single-syllable IP-relative branch instruction which carries M offset bits; and ii) a long IP-relative branch instruction which occupies multiple syllables of an instruction bundle, wherein a first syllable carries N offset bits and a second syllable carries P offset bits; c) a plurality of execution units, each execution unit being one of a plurality of types, wherein each instruction type is executed on one or more execution unit types, and wherein the plurality of execution units comprise: i) a first branch execution unit, the first branch execution unit comprising an adder for: A) when the first branch execution unit is configured in a first mode, calculating a branch target by adding an instruction pointer value to an addend formed at least in part from the M offset bits carried by a single-syllable IP-relative branch instruction located in a first syllable of an instruction bundle; and B) when the first branch execution unit is configured in a second mode, calculating a branch target by adding an instruction pointer value to an addend formed at least in part from the N and P offset bits carried by a long IP-relative branch instruction located in first syllable and second syllables of an instruction bundle; and ii) a second branch execution unit, placed physically adjacent to the first branch execution unit, for calculating a branch target by adding an instruction pointer value to an addend formed at least in part from the M offset bits carried by a single-syllable IP-relative branch instruction located in a second syllable of an instruction bundle; d) first wires for routing bits in the first syllable of the instruction bundle to the first branch execution unit; e) second wires for routing bits in the second syllable of the instruction bundle to the second branch execution unit, wherein the second wires pass over the first branch execution unit; and f) means for coupling the second wires to the first branch execution unit.