Patent ID: 8418090
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A computer-implemented method of estimating integrated circuit (IC) yield, comprising: identifying, by a computer, layout edges of shape configurations in said IC, said shape configurations being susceptible to systematic defects by a manufacturing process; measuring, by said computer, a sensitivity of said shape configurations to said systematic defects; selecting, by said computer, a size of said shape configurations based on one of pre-expanding and pre-shrinking of said layout edges, which matches a predicted fault density based on said one of said pre-expanding and said pre-shrinking of said layout edges of said shape configurations for said systematic defects from test data for said IC; and calculating, by said computer, a weighted critical area analysis of said one of said pre-expanding and said pre-shrinking of said layout edges of said shape configurations, said calculating of said weighted critical area analysis comprising performing one of dot-throwing, geometric expansion, and using Voronoi diagrams.