Patent ID: 6127838
Filing Date: 2000-10-03
Classification: G01R

Abstract:
An integrated circuit comprising a dynamic CMOS Programmable Logic Array with an AND plane and an OR plane, the AND plane comprising a first matrix of first row lines and first column lines, the first column lines comprising 2n bit lines derived from n inputs, and the first row lines comprising m product lines, each product line being accompanied with a corresponding adjacent first evaluate line, the bit lines controlling first crosspoint transistors connecting product lines to corresponding first evaluate lines, the OR plane comprising a second matrix of second row lines and second column lines, the second row lines comprising m product term lines and the second column lines comprising k sum lines feeding k outputs, each sum line being accompanied with a corresponding adjacent second evaluate line, the product term lines controlling second crosspoint transistors connecting sum lines to corresponding second evaluate lines, each product term line corresponding to a respective product line, the product lines and the sum lines forming a set of precharge lines,characterized in that the circuit includes a test circuit which during a test mode simultaneously drives lines of a plurality of pairs of physically adjacent first row lines and/or second column lines to complementary logic levels and keeps the crosspoint transistors connected to said plurality of pairs in an off state to facilitate a detection of a bridging fault via a measurement of a quiescent power supply current.