Patent ID: 7580321
Filing Date: 2009-08-25
Classification: G11C

Abstract:
1. A synchronous semiconductor memory device comprising: a clock generator for generating a normal phase clock and a reverse phase clock with a phase difference of 180 degree therebetween as internal clocks by dividing an external clock having a predetermined period; a command decoder for decoding an external command and outputting a command signal in accordance with a decoding result; a latency setting circuit capable of selectively setting an even number latency having a period of an even number times the period of said external clock or an odd number latency having a period of an odd number times the period of said external clock within a range of a predetermined number of clock cycles of said external clock; a latency counter which includes a first counter circuit for sequentially shifting said command signal captured using said normal phase clock and being capable of switching a signal path in response to said number of clock cycles and a second counter circuit for sequentially shifting said command signal captured using said reverse phase clock and being capable of switching a signal path in response to said number of clock cycles; a first control circuit which, when said even number latency is set, controls counting of said clock cycles equivalent to said even number latency by forming a signal path such that said command signal captured using said normal phase clock passes only through said first counter circuit and said command signal captured using said reverse phase clock passes only through said second counter circuit; a second control circuit which, when said odd number latency is set, controls counting of said clock cycles equivalent to said odd number latency by forming a signal path such that said command signal captured using said normal phase clock is shifted from said first counter circuit to said second counter circuit and said command signal captured using said reverse phase clock is shifted from said second counter circuit to said first counter circuit.