Patent ID: 6222215
Filing Date: 2001-04-24
Classification: H01L

Abstract:
Dynamic random access memory circuitry comprising:a semiconductive substrate;a first insulating layer disposed over the semiconductive substrate and having an elevational thickness from about 1000 to 20,000 Angstroms;a semiconductive material layer disposed over the first insulating layer and having an elevational thickness from about 200 to 10,000 Angstroms;a pair of laterally spaced apart word lines disposed over the semiconductive material layer,a first source/drain diffusion region received within the semiconductive material layer generally between the word lines, the first source/drain diffusion region extending completely through the semiconductive material layer and connecting with the first insulating layer;second and third source/drain diffusion regions received within the semiconductive material layer and disposed respectively generally laterally outward of the two word lines, the second and third source/drain diffusion regions extending completely through the semiconductive material and connecting with the first insulating layer;a second insulating layer disposed over the word lines and semiconductive material layer, the second insulating layer having a generally planar outer surface which is disposed at an elevational level which is higher than any structure of the word line pair;a pair of capacitor openings received within the second insulating layer and extending elevationally downward therefrom a) through the second insulating layer, b) completely through the semiconductive material layer and associated second and third source/drain diffusion regions therein, and c) into the first insulating layer;a layer of storage node material disposed and isolated within the individual capacitor openings, the storage node material extending elevationally below, but not above, the elevational level of the outer surface of the second insulating layer and in electrical contact with respective second and third source/drain diffusion regions;independent of the first and second insulating layers, first and second sidewall spacers operatively associated respectively with one each of the pair of word lines and over respective second and third source/drain diffusion regions, the storage node layer that contacts respective second and third source/drain diffusion regions also contacting at least a portion of respective first and second sidewall spacers;a capacitor dielectric layer disposed over the storage node material;a cell plate structure operatively disposed relative to the capacitor dielectric layer, the cell plate structure having an uppermost surface, the storage node material, capacitor dielectric layer and cell plate structure constituting respective capacitor constructions which extend both elevationally above and elevationally below the word lines; anda conductive material disposed laterally between at least a portion of the individual capacitor constructions and in ohmic electrical contact with the first source/drain region to define a bit line contact; the bit line contact having an uppermost surface which is elevationally above the uppermost surface of the cell plate structure.