Patent ID: 7299397
Filing Date: 2007-11-20
Classification: H03M

Abstract:
1. A decoding apparatus for decoding Low Density Parity Check (“LDPC”) codes, the LDPC codes being represented by a check matrix, which is composed of a plurality of sub-matrices, the sub-matrices including a (P×P) unit matrix, a quasi-unit matrix, a shift matrix, a sum matrix, and a (P×P) zero matrix, wherein the quasi-unit matrix is a unit matrix having one or more 1s being substituted with 0, the shift matrix is a unit matrix or a quasi-unit matrix which is cyclically shifted, the sum matrix is the sum of two or more of said unit matrix, said quasi-unit matrix, and said shift matrix, the decoding apparatus comprising: first computation means for simultaneously performing P check node computations for decoding said LDPC codes; second computation means for simultaneously performing P variable node computations for decoding said LDPC codes; and message storage means for simultaneously reading and writing message data corresponding to P edges, the message data being obtained as a result of said P check node computations or said P variable node computations; wherein said message storage means stores message data corresponding to the edges, the message data being read during the check node computation in such a manner that the sub-matrices of the check matrix are packed closer in a predetermined direction excluding the zero matrix.