Patent ID: 6100568
Filing Date: 2000-08-08
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a substrate having a primary surface;a memory cell provided on the substrate, the memory cell including a P-channel transistor, the P-channel transistor having an N-type gate, wherein the P-channel transistor of the memory cell has a device region in the primary surface of the substrate, the device region including a surface channel region having a dopant concentration of less than 1E16 atoms per cubic cm at a depth no more than approximately 0.1 microns from the primary surface of the substrate, a punchthrough region having a maximum dopant concentration of 1E17 to 1E18 atoms per cubic cm at a depth within a range of 0.1 to 0.3 microns from the primary surface of the substrate, and a background region having a maximum dopant concentration of approximately 1E16 to 1E17 at a depth within a range of approximately 0.2 to 0.5 microns from the primary surface of the substrate; anda peripheral portion provided on the substrate, the peripheral portion including a P-channel transistor, the P-channel transistor having a P-type gate.