Patent ID: 6351135
Filing Date: 2002-02-26
Classification: G01R

Abstract:
A TDDB test pattern circuit comprising:a plurality of unit test pattern cells having a MOS capacitor, a MOS transistor such that a drain current measuring node (DCMN) is defined at a drain of the MOS transistor, and a fuse for controlling operations of the MOS capacitor and the MOS transistor such that a voltage force node (VFN) is defined at a first end of the fuse opposite to a second end of the fuse connected to the MOS capacitor; a first voltage supplying unit for supplying a stress voltage to the MOS capacitor and the MOS transistor in each unit test pattern cell simultaneously; an ammeter for measuring a total current flow from the plurality of unit test pattern cells to measure a total time to breakdown of the plurality of unit test pattern cells; and a second voltage supplying unit for applying a voltage to the drain terminal of the MOS transistor.