Patent ID: 8304892
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a base substrate; a semiconductor chip mounted on the base substrate and including bonding pads; first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads; a first ball land disposed on the base substrate and electrically connected to the first connection terminal; a second ball land spaced apart from the connection terminals, the first ball land being disposed between the second ball land and at least one of the first and second connection terminals; a first insulating layer covering the first ball land but exposing at least a part of the second ball land; a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land; a third connection terminal spaced apart from the first and second connection terminals; a third ball land spaced apart from the first and second connection terminals, the first and second ball lands being disposed between the third ball land and at least one of the first through third connection terminals; a second insulating layer covering the first insulating layer, the first conductive wire, and the second ball land but exposing a part of the third ball land; and a second conductive wire crossing the second insulating layer to connect the third connection terminal to the third ball land.