Patent ID: 6342450
Filing Date: 2002-01-29
Classification: H01L

Abstract:
An improved method of forming the insulating spacer on the gate conductor sidewall of an IGFET comprising the steps of:a) providing a structure consisting of a silicon substrate having a diffusion region formed therein and gate conductor (GC) lines formed thereon isolated from the substrate by a thin SiO2 gate layer; b) conformally depositing an oxynitride layer and a silicon nitride (Si3N4) layer in sequence onto the structure in the same deposition tool for total clusterization; and, c) anisotropically dry etching the Si3N4 layer with a chemistry which is Si3N4/oxynitride selective to expose the oxynitride layer between the GC lines and the upper portion thereof in a one step process to form the Si3N4 spacers.