Patent ID: 6700421
Filing Date: 2004-03-02
Classification: G06F,Y02D

Abstract:
A phase locked loop circuit, comprising:a first divide-by-N counter adapted to receive a first clock signal and provide a second clock signal, wherein the first divide-by-N counter introduces a first preselected delay between the first and second clock signals; wherein the first divide-by-N counter includes: a first logic gate having a first and second input terminal and an output terminal, the first input terminal of the first logic gate being adapted to receive the first clock signal and the output terminal of the first logic gate being adapted to deliver the second clock signal; a control circuit coupled to deliver a signal to the second input terminal of the first logic gate to permit at least a portion of the first clock signal to pass therethrough; a phase comparator having a first and second input terminal and an output terminal, the phase comparator being adapted to receive clock signals at the first and second input terminals, compare a phase of the clock signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals, said first input terminal being coupled to receive the second clock signal; a voltage controlled oscillator coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto; a second divide-by-N counter coupled to receive the third clock signal and deliver a fourth clock signal; a clock tree coupled to receive the fourth clock signal and deliver at least one fifth clock signal; and a feedback path coupled to deliver the fifth clock signal to the second input terminal of the phase comparator, wherein the feedback path includes a delay element adapted to delay the fifth clock signal by a preselected period of time substantially corresponding to the first preselected delay; wherein the delay element is comprised of a second logic gate adapted to pass the fourth clock signal to the second input terminal of the phase comparator.