Patent ID: 8995170
Filing Date: 2015-03-31
Classification: G11C,H01L

Abstract:
1. A non-volatile memory device comprising: a substrate; a memory cell array including: a plurality of first lines arranged in parallel to each other above the substrate; a plurality of second lines arranged in parallel to each other crossing the plurality of first lines three-dimensionally; and a plurality of memory cells each including a first variable resistance element and a first current steering element and placed at a corresponding one of cross-points of the first lines and the second lines; and a parameter generation circuit including: a third line placed above the substrate; a fourth line placed above the third line; and a current steering characteristic reference cell placed between and connected to the third line and the fourth line and including a second variable resistance element and a second current steering element having a same current density-voltage characteristic as a current density-voltage characteristic of the first current steering element, wherein the second variable resistance element includes: a lower electrode layer; a variable resistance layer formed above the lower electrode layer; and an upper electrode layer formed above the variable resistance layer, and in the current steering characteristic reference cell, the second variable resistance element has a side surface with a conductive shorting layer for short-circuiting the upper electrode layer and the lower electrode layer.