Patent ID: 6492848
Filing Date: 2002-12-10
Classification: H03K

Abstract:
A power-on reset circuit for producing a power-on reset signal in response to a power-on signal which is activated when power is applied to a chip in a semiconductor device, the power-on reset circuit comprising:an input means receiving the power-on signal from an external circuit; a first inverting means connected to the power-on signal, including an output node and an input node connected to an output of the input means, wherein a voltage level at the output node is toggled from a high voltage level signal to a low voltage level signal before an output signal from the input means increases up to a desired voltage level; and a reset signal generating means coupled to the output node for generating the power-on reset signal in response to the voltage level at the output node, wherein the first inverting means is a schmitt trigger inverter and includes: first and second pull-up means which are in series connected to each other, each of which has a source and a drain to transfer the power-on signal to a first node in response to the output signal from the input means, wherein the output node of the first inverting means is coupled between the first and second pull-up means; first and second pull-down means which are in series connected to each other, each of which has a source and a drain to pull down the transferred power-on signal in response to the output signal from the input means, wherein the first and second pull-down means are coupled to a second node; an NMOS transistor having a gate coupled to the first node to provide the power-on signal for the second node; and a PMOS transistor having a gate coupled to the first node to couple the output node to a ground voltage level.