Patent ID: 6288564
Filing Date: 2001-09-11
Classification: H04L

Abstract:
A line receiver circuit, comprisinga buffer section (1) having an input (IN) for connection with a transmission line (TR) and an output (OUT) for providing data signals in accordance with signals received through the transmission line (TR);termination impedance mean (2) connected with the input (IN) of said buffer section (1), for terminating the characteristic impedance of the transmission line (TR), said termination impedance means (2) comprising at least two controllable impedance elements (TZ1 to TZ3) connected to provide termination impedance, each element having an individual impedance control input for receiving an impedance control signal;impedance control means comprisingtwin impedance means (4) comprising at least two controllable impedance elements (NZ1 to NZ3) connected to provide a twin impedance, each having an individual impedance control input and having electrical characteristics in predetermined relation to corresponding electrical characteristics of corresponding impedance elements (TZ1 to TZ3) of said termination impedance means;means (3) for generating individual control signals for each of said twin impedance elements (NZ1 to NZ3) to control the number of twin impedance elements (NZ1 to NZ3) in an active state in which a contribution to the overall twin impedance is made, and to thereby provide a value for said twin impedance which approximates a target value;means (VZ1 to VZ3) for providing a respective control signal for each of said termination impedance elements (TZ1 to TZ3) in a predetermined relation to the control signal for the respectively corresponding twin impedance element (NZ1 to NZ3).