Patent ID: 8362565
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation of the semiconductor layer into a memory element part and a logic element part; a first field-effect transistor formed in the memory element part of the semiconductor layer and having a first gate electrode on a first surface side of the semiconductor layer; a second field-effect transistor formed in the memory element part of the semiconductor layer and having a second gate electrode on a second surface side opposite to the first surface and a source and drain region in common with a source and drain region of the first field-effect transistor; a third field-effect transistor formed in the logic element part of the semiconductor layer and having a third gate electrode on the second surface side; a first insulating film formed on the semiconductor layer to cover the first field-effect transistor; and a second insulating film formed on the semiconductor layer to cover the second field-effect transistor and the third field-effect transistor, wherein the first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors, and the first gate electrode and the second gate electrode are electrically connected; wherein the first gate electrode and the second gate electrode are electrically connected by a contact portion formed through the element isolation region.