Patent ID: 6441757
Filing Date: 2002-08-27
Classification: H03M

Abstract:
A decoding apparatus for variable-length codes wherein input data which consist of a plurality of variable-length codes of at most N bits are decoded successively in a plurality of cycles, comprising:a first logic circuit which receives the input data, and which delivers necessary-length data having the minimum number of bits that is a multiple of k and that exceeds N; decode means connected to said first logic circuit, for delivering a data length of remaining data obtained by removing the first variable-length code contained in the necessary-length data, from said necessary-length data, and for decoding said necessary-length data in accordance with the remaining data in the preceding cycle and then outputting the decoded data; and first control means connected to said decode means, for controlling said first logic circuit so as to receive the input data having the number of bits that is the multiple of k depending upon the data length of said remaining data; wherein symbol N denotes a natural number of at least 2, and symbol k denotes a natural number smaller than the number N.