Patent ID: 7561404
Filing Date: 2009-07-14
Classification: H02J

Abstract:
1. A discrete transistor active bridge circuit connectable between a pair of input lines and a pair of output lines for protecting devices from the effects of battery polarity, said discrete transistor active bridge circuit, comprising: first and second field-effect transistors of a first channel type, a source-drain path of said first field effect transistor connected in series with a source-drain path of said second field effect transistor to form a first series transistor combination connected across said input lines; third and fourth field-effect transistors of a second channel type, a source-drain path of said third field effect transistor connected in series with a source-drain path of said fourth field effect transistor to form a second series transistor combination connected across said input lines; said first, second, third and fourth field-effect transistors connected to automatically provide a predetermined voltage polarity at said pair of output lines regardless of a voltage polarity applied at said pair of input lines coupled to a power supply; a voltage divider provided for each of said field-effect transistors, said voltage divider comprised of a first resistor connected between sources of at least two of said field-effect transistors and a gate of a first one of said at least two field-effect transistors and a second resistor connected in series with said first resistor from said sources of said at least two of said field-effect transistors directly to a first input line of said input lines, wherein said first input line has a first voltage polarity opposite a second voltage polarity of a second input line of said input lines, and said second input line is directly coupled to a drain of said first one of said at least two field-effect transistors; a bias voltage tap defined at a connection point between said first and second resistors connected to said gate of each of said field-effect transistors; and a plurality of voltage clamping devices, each respectively connected between said gate and said source of one of said first, second, third and fourth field-effect transistors, wherein each of said voltage clamping device performs a dual function of providing protection to said gate of each respective one of said field-effect transistors, and allowing an adequate bias voltage level to be developed between said gate and said source of said respective field-effect transistor when a voltage across said input lines is less than a predetermined value; wherein each of said first, second, third, and fourth field-effect transistors is a power MOSFET that is self biased through an intrinsic body diode, said intrinsic body diodes of the field-effect transistors arranged (a) to allow said first and fourth field-effect transistors to turn on at a first polarity state of an input voltage source while blocking bias currents for said second and third field-effect transistors at said first polarity state, and (b) to allow said second and third field-effect transistors to turn on at a second polarity state of said input voltage source while blocking bias currents for said first and fourth field-effect transistors at said second polarity state.