Patent ID: 8755468
Filing Date: 2014-06-17
Classification: H03L,H04B,H04L

Abstract:
1. A pulse-sync demodulator that receives a pulse signal of a first frequency, comprising: a clock signal generation section that generates a clock signal of a second frequency which is one-half of the first frequency; a plurality of AD conversion sections that sample the pulse signal at different sampling timings of the clock signal; a phase determination section that generates a phase control signal in accordance with magnitudes of a plurality of sampled values output from the plurality of AD conversion sections; a variable delay section that changes an amount of delay in the clock signal generated by the clock signal generation section in accordance with the phase control signal; a plurality of sampling timing adjustment sections that are provided in correspondence with the plurality of AD conversion sections, respectively, and that can individually adjust the amount of delay in the clock signal output from the variable delay section; and a level determination section that detects levels of the plurality of sampled values output from the plurality of AD conversion sections and that increases or decreases the amount of delay in the variable delay section by a predetermined amount when the levels of the plurality of sampled values become lower than a preset value, wherein