Patent ID: 8321607
Filing Date: 2012-11-27
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a plurality of pads formed on said semiconductor substrate and configured to permit data input and output; and a memory core block and an input/output block integrated on said semiconductor substrate; wherein, for every two data lines of said memory core block and for every two of said pads to and from which two data items are input and output, said input/output block is configured to switch reciprocally combinations of the interconnected data lines and pads based on an input address signal in such a manner as to determine to which of the two pads the two data items correspond, one of said two data lines being determined to be accessed for the memory address thereof based on information about said combinations, whereby the data items are input and output to and from said plurality of pads at twice a maximum access rate in effect.