Patent ID: 6636074
Filing Date: 2003-10-21
Classification: G06F,Y02D

Abstract:
An integrated circuit comprising:a plurality of CSRs (Control and Status Registers), wherein each CSR includes one or more flip-flops; one or more clock gates, wherein each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs, wherein each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted; and one or more clock gating units, wherein each clock gating unit is configured to generate the clock enable signal for the respective one of the plurality of CSRs, wherein a first clock gating unit is configured to assert the clock enable signal for a first one of the CSRs in response to detecting a software update to the first CSR.