Patent ID: 7747919
Filing Date: 2010-06-29
Classification: G01R

Abstract:
1. A scan BIST circuit within an integrated circuit, comprising: A. scan path circuitry having plural scan path parts, each part having a separate scan input, scan output, clock input and enable input; B. test pattern generator circuitry having a control input and a stimulus data output, the stimulus data output being coupled with the scan input of each scan path part; C. compactor circuitry having a control input and a response data input, the response data input being selectively coupled with the scan output of each scan path part; D. controller circuitry having a clock output, an enable output, a control output coupled to the control input of the test pattern generator circuitry, and a control output coupled to the control input of the compactor circuitry; and E. adapter circuitry having a clock input and an enable input coupled with the respective clock output and enable output of the controller circuitry, and having a separate clock output and an enable output coupled with the separate clock input and enable input of each scan path part.