Patent ID: 7558947
Filing Date: 2009-07-07
Classification: G06F

Abstract:
1. A method for execution by a microprocessor in response to receiving a single instruction, the method comprising: receiving a first vector of numbers from a first entry in a register file and a second vector of numbers from a second entry in the register file; selecting a first plurality of numbers of the first vector from a string-of bits in the first entry and a second plurality of numbers of the second vector from the second entry according to a configuration specified by the single instruction that indicates how to partition the string of bits in the first entry into the first plurality of numbers; and generating simultaneously a third plurality of numbers, each of which is an absolute difference between a number in the first plurality of numbers and a number in the second plurality of numbers; wherein the third plurality of numbers are saved in a third entry in the register file; wherein the above operations are performed in response to the microprocessor receiving the single instruction, wherein the single instruction indicates the first entry for the first plurality of numbers, the second entry for the second plurality of numbers, and the third entry for the third plurality of numbers in the register file.