Patent ID: 6950339
Filing Date: 2005-09-27
Classification: G11C

Abstract:
1. A circuit for generating a trim bit signal in a flash memory device, comprising: a control unit selected by a trim bit select signal and a plurality of control signals, and including a cell that is programmable and erasable; and an output unit for outputting a High level signal or a Low level signal through a trim bit signal output terminal depending on a status of the cell of the control unit, wherein the control unit comprises: a first inverter for inverting the trim bit select signal; a first switching device connected between the output of the first inverter and a first node and turned on by a first control signal; the cell connected between the first node and a second node and driven by a second control signal; a second switching device connected between the second node and the output of the control unit and turned on by a third control signal; and a third switching device connected between the first node and the ground and turned on by a fourth control signal.