Patent ID: 7257802
Filing Date: 2007-08-14
Classification: G01R,G06F

Abstract:
1. A method for verifying a circuit design by mapping a circuit design and an associated testbench onto a reconfigurable hardware platform, said method comprising the steps of: synthesizing the circuit design into a structural model; mapping the structural model of the circuit design onto a reconfigurable hardware platform; transforming a behavioral model of a testbench into a structural model maintaining exact simulation semantics of the behavioral model, said structural model including a plurality of finite state machines (FSMs) corresponding to each time advancing and time non-advancing block of code in said behavioral model; mapping and executing said finite state machines onto the reconfigurable hardware platform, generating a global scheduler for synchronized execution of said finite state machines; automatically partitioning portions of said structural model of the testbench for execution on a sequential computation platform; and automatically synthesizing an interface for interaction between the reconfigurable hardware platform and the sequential computation platform to enable execution of said portions partitioned by the computation platform.