Patent ID: 6157575
Filing Date: 2000-12-05
Classification: G11C,H01L

Abstract:
A nonvolatile memory device comprising:an array of a plurality of memory cells, each cell having a stacked gate structure including a floating gate and a control gate, formed in an area where a plurality of bit lines intersect a plurality of word lines;a plurality of source lines, each being arranged in parallel with said bit lines at an interval of one source line for a predetermined number of bit lines; anda plurality of source select transistors being arranged in series in a direction of said source line, each transistor having a gate in an area where said source line intersects said word line;wherein two cells are connected to a bit line via one bit line contact, two cells symmetrically arranged with respect to each other and connected to the same bit line via respective bit line contacts and sharing one active source region, said active source region being in parallel with said word line and connected to said source line via said source select transistor and a source line contact, and said source line being electrically isolated from another source line.