Patent ID: 6815227
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method for forming a ferroelectric memory device comprising:forming at least two capacitor structures, each of which includes a lower electrode, a ferroelectric layer, and an upper electrode, the structures stacked on a semiconductor substrate, the lower electrode of each of which is connected to a contact plug that penetrates an interlayer insulating layer formed on the substrate; forming an insulating layer pattern covering at least a sidewall of the lower electrode of the structures; exposing a top of the upper electrode; sequentially forming a conductive layer and an oxygen barrier layer on the capacitor structures; patterning the conductive layer and the oxygen barrier layer to form a plate line such that the plate line overlaps with and contacts portions of the upper electrodes of an adjacent pair of capacitor patterns; forming an oxygen barrier spacer on a sidewall of the plate line; and performing a recovery annealing with respect to the substrate having the plate line where the oxygen barrier spacer is formed.