Patent ID: 7042769
Filing Date: 2006-05-09
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: an external clock generating circuit generating an external clock signal in synchronization with a clock signal from outside the device; an external control signal generating circuit taking an external command applied from outside the device in synchronization with said external clock and generating an external control signal in response to said taken external command; a memory circuit including a memory cell array and a read/write circuit reading data from and writing data to said memory cell array; an internal control signal generating circuit taking said external control signal in synchronization with an internal clock signal asynchronous with said external clock signal, and generating an internal control signal controlling said memory circuit in response to said taken external control signal; a mode indicating signal generating unit generating a mode indicating signal that attains to a first logic state in response to said memory circuit entering an internal operation mode and to a second logic state in response to an end of the internal operation mode; and an internal clock generating circuit generating said internal clock signal in response to said mode indicating signal at said second logic state; wherein said external clock signal generating circuit stops generation of said external clock signal in response to said mode indicating signal at said first logic state, and generates said external clock signal, based on a first signal generated based on said mode indicating signal at said second logic state and said clock signal from outside the device and on a second signal provided by delaying said clock signal from outside the device by a prescribed amount of delay.