Patent ID: 6208183
Filing Date: 2001-03-27
Classification: H03L

Abstract:
A gated delay-locked loop that receives a reference clock having a frequency F.sub.REF and generates an output clock having a frequency F.sub.OUT =N.multidot.F.sub.REF that is synchronized in phase with the reference clock, the gated delay-locked loop comprising:a gated oscillator including at least one delay element configured in a feedback loop that introduces a time delay T.sub.del to produce a delayed clock, the delay element having an input, said gated oscillator further including a multiplexer responsive to a gating pulse that selectively applies either a clock derived from the delayed clock or the reference clock to the feedback loop; anda phase comparator for comparing the phase of a clock derived from the output clock to the phase of the reference clock and adjusting the time delay introduced by the at least one delay element to correct any detected phase difference;wherein the gating pulse is applied to the multiplexer once every N cycles of the output clock to cause the multiplexer to select the reference clock for supply to the feedback loop, and wherein the multiplexer selects the output clock for supply to the feedback loop the remaining N-1 cycles.