Patent ID: 8594253
Filing Date: 2013-11-26
Classification: H03D,H03M

Abstract:
1. A circuit for jitter compensation, comprising: a combiner block including a first adder unit adding a radio frequency (RF) reference signal to an input signal of the circuit; a converter stage configured to convert the input signal together with the reference signal, the converter stage comprising an analog-to-digital converter (ADC), the converter stage being clocked by a clock signal; a branch configured to branch the output of the converter stage into a direct output path and a forward path; the forward path comprising: a first mixer unit configured to mix the output signal of the converter stage with a first mixing frequency derived from the reference signal for extracting a jitter content; a weighting stage configured to adjust the jitter content; and a compensation unit configured to compensate jitter in the output signal of the converter stage in the direct output path using the jitter content.