Patent ID: 6404657
Filing Date: 2002-06-11
Classification: H02M,H03K

Abstract:
An electrical apparatus to synchronize multiple switching regulator devices in an out of phase mode comprising:a. a master device, said master device having a CLKIN, DH, LX, and DL pin, said CLKIN pin electrically coupled to a clock bus, said DH pin electrically coupled to a first MOSFET transistor, said LX pin electrically coupled to a first drain-source coupling and said DL pin electrically coupled to a second MOSFET transistor, said DH pin further electrically coupled to a first slave device; b. a first slave device, said first slave device having a CLKIN, DH, LX, DL and PHIN pin, said CLKIN pin electrically coupled to said clock bus, said DH pin electrically coupled to a third MOSFET transistor, said LX pin electrically coupled to a second drain-source coupling and said DL pin electrically coupled to a fourth MOSFET transistor, said DH pin further electrically coupled to a second slave device; c. a second slave device, said second slave device having a CLKIN, DH, LX, DL and PHIN pin, said CLKIN pin electrically coupled to said clock bus, said DH pin electrically coupled to a fifth MOSFET transistor, said LX pin electrically coupled to a third drain-source coupling and said DL pin electrically coupled to a sixth MOSFET transistor, said DH pin further electrically coupled to a third slave device; d. a third slave device, said third slave device having a CLKIN, DH, LX, DL and PHIN pin, said CLKIN pin electrically coupled to said clock bus, said DH pin electrically coupled to a seventh MOSFET transistor, said LX pin electrically coupled to a fourth drain-source coupling and said DL pin electrically coupled to a eighth MOSFET transistor; and e. a clock bus connected to clock input terminals of the master device and plurality of slave devices, said clock bus transmitting a master clock signal.