Patent ID: 7899983
Filing Date: 2011-03-01
Classification: G11C,H05K,Y02P

Abstract:
1. A memory system, comprising: a memory hub device integrated into a memory module; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first memory device data interface is separate from the second memory device data interface, wherein the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices; and a memory hub controller coupled to the first memory device data interface and the second memory device data interface, wherein: