Patent ID: 7993970
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A fabrication method of a semiconductor device, comprising the steps of: providing a semiconductor chip having an inner circuit and a plurality of connection bumps electrically connected to the inner circuit, and a substrate having a plurality of circuit layers formed thereon by wet etching and a plurality of solder pads formed by wet etching a conductive metal layer for being electrically connected to the connection bumps; flipping the semiconductor chip to enable the connection bumps to correspond to the solder pads in position; and compressing the substrate and the semiconductor chip toward each other at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, such that the solder pads are embedded into the connection bumps, wherein the substrate is formed by wet etching a surface of a core board so as to form the solder pads on the surface of the core board, and a top surface of each of the circuit layers is smaller in area than a bottom surface of each of the circuit layers.