Patent ID: 8890245
Filing Date: 2014-11-18
Classification: H01L

Abstract:
1. A transistor comprising: a buried oxide layer above a substrate; a silicon layer above the buried oxide layer; a gate stack on the silicon layer, the gate stack comprising a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer; a nitride liner adjacent to the gate stack; an oxide liner adjacent to the nitride liner; and a raised faceted raised source region and a faceted raised drain region each comprising a part that comprises a portion of the silicon layer, wherein each of the faceted raised source region and the faceted raised drain region comprises a first faceted side portion and a second faceted side portion, wherein each of the second faceted side portions is in contact with the oxide liner and the nitride liner, wherein at least a portion of each second faceted side portion is formed under at least a portion of the oxide liner and a portion of the nitride liner, and wherein the portions of the oxide and nitride liners extend over the portion of each second faceted side portion.