Patent ID: 7002256
Filing Date: 2006-02-21
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate having a first area where an integrated circuit is formed, a second area having a first part and a second part, and a third area where a pad pattern is formed, wherein the second area encompasses the first and third area; wiring patterns formed on the substrate in the first area; a first dummy pattern which is formed of the same material as the wiring patterns, formed in the first part of the second area, wherein the first part is located along an edge of the semiconductor substrate; a second dummy pattern, which is formed of the same material as the wiring patterns, which is formed in the second part of the second area, wherein a second part is located between the first and the third areas, the first and the second dummy patterns being formed as a single integral structure, whereby the pad pattern is encompassed by the first and second dummy patterns; a second insulating layer formed over the wiring patterns and the first and second dummy patterns, an edge of the second insulating layer being located on the pad pattern, which is adjacent the first and second dummy patterns; and a first insulating layer formed above the semiconductor substrate, the first insulating layer being formed outside the first and second dummy patterns but not being formed over the first and second dummy patterns.