Patent ID: 6252177
Filing Date: 2001-06-26
Classification: H05K,Y02P

Abstract:
A low inductance capacitor mounting structure for capacitors of a printed circuit board, comprising:a solder pad layer for mounting a capacitor thereon;an upper electrically conductive layer providing a voltage plane;a lower electrically conductive layer provided closely below said upper electrically conductive layer and providing a voltage plane;a first substrate dielectric layer provided between said solder pad layer and said upper electrically conductive layer;a first set of vias formed through said first substrate dielectric layer and electrically connecting said solder pad layer and said upper electrically conductive layer;a second substrate dielectric layer provided between said upper electrically conductive layer and said lower electrically conductive layer; anda second set of vias formed through said first substrate dielectric layer and said second substrate dielectric layer and electrically connecting said solder pad layer and said lower electrically conductive layer;said lower electrically conductive layer being positioned closely below said upper electrically conductive layer to confine a magnetic field path generated by said second set of vias between said upper electrically conductive layer and said lower electrically conductive layer thereby reducing inductance between said upper electrically conductive layer and said lower electrically conductive layer; andwherein the spacing between said upper electrically conductive layer and said lower electrically conductive layer is substantially less than 15 mils.