Patent ID: 6339238
Filing Date: 2002-01-15
Classification: G11C,H01L

Abstract:
A method of writing to a selected memory cell in a ferroelectric memory, said memory including a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs including the following electrical elements: a substrate, a source, a drain, a channel, a gate, and a layer of ferroelectric material; said ferroelectric FETs arranged in an array comprising a plurality of rows and a plurality of columns of said ferroelectric FETs, said memory further including a plurality of first row lines, each of said first row lines running parallel to one of said rows of said ferroelectric FETs, a plurality of second row lines, each of said second row lines running parallel to one of said rows of said ferroelectric FETs, and a plurality of column lines, each of said column lines running parallel to one of said columns of ferroelectric FETs, said method comprising placing a first voltage on the one of said row lines running parallel to the one of said rows containing said selected memory cell, placing a second voltage on the one of said columns running parallel to said selected memory cell, applying a third voltage on the one of said second row lines running parallel to said row containing said selected memory cell, applying said first voltage to a first one of said electrical elements in each of said ferroelectric FETs in said row containing said selected memory cell, applying said second voltage to a second one of said electrical elements in each of said ferroelectric FETs in said column containing said selected memory cell, and applying said third voltage to a third one of said electrical elements in each of said ferroelectric FETs in said row containing said selected memory cell.