Patent ID: 7185171
Filing Date: 2007-02-27
Classification: G06F,Y02D

Abstract:
1. A semiconductor integrated circuit, comprising: an address conversion memory circuit for converting a logical address of a vertical memory into a physical address of a main memory, wherein the address conversion memory circuit comprises a gated logic circuit, a clock enable generating circuit, a tag memory and a data memory, wherein clocks are supplied to the tag memory and the data memory via the gated logic supplies and cuts off the clocks, wherein the tag memory stores the logical page address as tag information, wherein the data memory stores the physical page address as entry information, wherein the clock enable generating circuit invalidates a clock enable signal when a first logical page address requested as a preceding access is the same as a second logical page address requested as a present access and a first intra-page address requested as the present access is not within the boundary addresses between intra-page addresses, and wherein the gated logic circuit cuts off the clock to the tag memory and the data memory when the clock enable signal is valid.