Patent ID: 6727130
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A method of forming a dual gate type semiconductor device comprising:forming a first gate insulation layer and a first metal-containing layer sequentially on a surface of a substrate in first and second impurity type transistor regions on which an isolation layer is formed, wherein the first metal-containing layer has a work function corresponding to the work function of silicon of the first impurity type; exposing said first gate insulation layer on said surface of said substrate in said second impurity type transistor region by selectively etching said first metal-containing layer anisotropically; removing said first gate insulation layer on said surface of said substrate in said second impurity type transistor region; forming a second gate insulation layer by selectively thermally oxidizing said surface of said substrate in said second impurity type transistor region in which said first gate insulation layer is removed; forming a second metal-containing layer over said surface of said substrate on which said second gate insulation layer is formed, wherein the second metal-containing layer has a work function corresponding to the work function of silicon of the second impurity type; forming a first gate electrode on said surface of said substrate in said first impurity type transistor region by patterning said second metal-containing layer and first metal-containing layer; and forming a second gate electrode on said surface of said substrate in said second impurity type transistor region by patterning said second metal-containing layer.