Patent ID: 7185309
Filing Date: 2007-02-27
Classification: G06F

Abstract:
1. A method of designing a memory system for implementation using an integrated circuit, comprising: receiving specification data including attributes of said memory system; configuring a memory component and a memory interconnection component to store messages of a memory model in response to the specification data to generate a logical view of said memory system said memory component is defined by a memory architecture and a memory interface, and said memory-interconnection component is defined by a memory-interconnection architecture and a memory-interconnection interface; and generating a physical description of said memory system in response to said logical view, said physical description including memory circuitry associated with said integrated circuit defined by said memory component, said memory circuitry having an interconnection topology defined by said memory interconnection component wherein said memory circuitry comprises a plurality of memories, and wherein said memory architecture is configured to store said messages within said plurality of memories.