Patent ID: 7399698
Filing Date: 2008-07-15
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device on a wafer including a scribe lane region and chip region, comprising: forming a first pad including a first metal and an inter-connection line including the first metal in the scribe lane region; forming a second pad including the first metal in the chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.