Patent ID: 7436063
Filing Date: 2008-10-14
Classification: H01L

Abstract:
1. A packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate, comprising: a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings, each being formed in continuation with a respective electrode opening in the wiring protective layer and exposing a part of the wiring, each escape opening having a width greater than a width of the wiring and exposing an entire width of the part of the wiring, each escape opening introducing onto the exposed part of the wiring a part of the connection metal body that escapes into the escape opening when the connection metal body is connected to each of the electrode parts.