Patent ID: 6433376
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a logic circuit area formed on the semiconductor substrate, including transistors for driving bit lines; a ferroelectrics memory area laminated on the logic circuit area and including a transistor area and a capacitor area; interconnection wirings formed on the logic circuit area and electrically connected to the transistors; bit lines formed on the upper part of the interconnection wirings, and electrically connected to the interconnection wirings; silicon film formed on the upper side of the bit lines and defining a cell forming area; a transistor area formed on the silicon film and comprising a gate electrode, a source and a drain, wherein the gate electrode is formed on the silicon film, and the source and drain are formed in the silicon film located under both sides of the gate electrode; and a capacitor formed on each transistor and electrically connected to the drain of the transistor.