Patent ID: 8451202
Filing Date: 2013-05-28
Classification: G09G

Abstract:
1. A computing device comprising: a processing resource; a display assembly comprising a plurality of pixel elements, wherein the plurality of pixel elements each include a display cell, and wherein the plurality of pixel elements include at least a set of pixel elements that are individually provided with one or more pixel-level memory cells; wherein the processing resource is configured to write data to refresh the plurality of pixel elements at multiple instances per second when the display assembly is in a high operational state, so as to provide a first display content on the display assembly when the device is in the high operational state; wherein the set of pixel elements are individually structured to store at least one bit from data written to that pixel element at each of the multiple instances; wherein when the display assembly is switched from the high operational state to a low operational state, the one or more memory cells of each pixel element in the set are configured so as to carry data representing at least the portion of the data written to that pixel element at a last instance before the display assembly is switched from the high operational state to the low operational state.