Patent ID: 6385686
Filing Date: 2002-05-07
Classification: G06F

Abstract:
An apparatus that supports multiple delayed read transactions, comprising:a host bus; a peripheral bus; a receiving mechanism that receives a first request from the host bus that is directed to the peripheral bus; wherein the receiving mechanism is configured to receive a pipelined request from the host bus that is directed to the peripheral bus, the pipelined request being received before the first request is completed; wherein the receiving mechanism is configured to wait a pre-determined amount of time for the pipeline request; a first buffer for storing the first request; a second buffer for storing the pipelined request; a sending mechanism that sends the first request to the peripheral bus, so that the first request will be processed when the peripheral bus becomes available; wherein if the pipelined request is received and if the pipelined request is a read operation, the sending mechanism is configured to send the pipelined request to the peripheral bus, so that the pipelined request will be processed when the peripheral bus becomes available; and a retry mechanism that issues a retry request across the host bus, the retry request causing both the first request and the pipelined request to be retried at a later time on the host bus so that the host bus can be freed up for other transactions.