Patent ID: 7945404
Filing Date: 2011-05-17
Classification: G01R

Abstract:
1. A measurement circuit within an integrated circuit, for measuring an error value of a clock signal under test, the measurement circuit comprising: a first delay element, for delaying the clock signal under test to generate a first delayed clock signal; a second delay element, for delaying the clock signal under test to generate a second delayed clock signal; a condition indication element, coupled to the first and second delay elements, for indicating whether the error value of the clock signal under test is within a window value, the window value being corresponding to delays of the first and second delay elements; and a state machine, coupled to the condition indication element, for generating first and second control signals based on an indication signal from the condition indication element, the first and second control signals being for controlling the first and second delay elements; wherein if the indication signal indicates that the error value of the clock signal under test is not within the window value, the first and second control signals adjust the delayed clock signals of the first and the second delay elements and the window value; wherein the error value of the clock signal under test is measured based on the delayed clock signals of the first and the second delay elements and the window value.