Patent ID: 7701273
Filing Date: 2010-04-20
Classification: H03K,H03L

Abstract:
1. A delay locked loop circuit, comprising: a delay locked loop block that receives external clocks to generate first internal clocks including a reference clock, including: an internal delay unit that delays the first internal clocks to output second internal clocks, which are fed back to the delay locked loop block, which adjusts delay time of the delay unit according to a phase difference between each second internal clock and the reference clock so that the second internal clocks are delay locked; a duty cycle correcting block that corrects a duty cycle of each second internal clock and outputs a duty cycle corrected clock; and an error determining unit that compares each phase of the second internal clocks with the reference clock and, based on the comparison, feeds back the duty cycle corrected clock or one of the second internal clocks as a feedback clock to the delay locked loop block, wherein the delay locked loop block includes: