Patent ID: 6638671
Filing Date: 2003-10-28
Classification: G03F,Y10S

Abstract:
A method of determining alignment error between lithographically produced integrated circuit fields on the same and different lithographic levels comprising:creating a first level field layer having a plurality of first level integrated circuit fields and associated set of first level metrology structures adjacent and outside each integrated circuit field, the first level metrology structures including separate first and second structures, a second structure associated with one first level integrated circuit field being located to nest with a first structure associated with an adjacent, first level integrated circuit field when the both first level integrated circuit fields are properly aligned on the same lithographic level, the first level metrology structures further including overlay metrology structures to determine overlay error between the first level field layer and a field layer on another level; creating a second level field layer having a plurality of second level integrated circuit fields and associated set of second level metrology structures adjacent and outside each integrated circuit field, the second level metrology structures including separate third and fourth structures, a fourth structure associated with one second level integrated circuit field being located to nest with a third structure associated with an adjacent, second level integrated circuit field when the both second level integrated circuit fields are properly aligned on the same lithographic level, and a second level metrology structure of one second level integrated circuit field being located to nest with an overlay metrology structure of the first level integrated circuit field when the first and second level integrated circuit fields are properly aligned on different lithographic levels; determining the locations of common points of reference on the associated first level metrology structures and on the associated second level metrology structures; measuring alignment error of first level integrated circuit fields from the reference point locations of associated first level first and second metrology structures; measuring alignment error of second level integrated circuit fields from the reference point locations of associated second level third and fourth metrology structures; and measuring overlay error between first level and second level integrated circuit fields from the reference point locations of the first level overlay metrology structures and the reference point locations of the second level metrology structures.