Patent ID: 6266731
Filing Date: 2001-07-24
Classification: G06F

Abstract:
A computer system, said system comprising:a central processing unit connected to a host bus;a random access memory connected to a system memory bus;a peripheral component interconnect (PCI) bus, said PCI bus operating on a sequential series of clock cycles, said PCI bus capable of implementing registered PCI bus arbitration rules and bus width rules according to a registered PCI protocol;a core logic chip set connected to said host bus, to said PCI bus, and to said system memory bus;said core logic chip set configured as a first interface bridge between said host bus and said system memory bus, a second interface bridge between said host bus and said PCI bus, and a third interface bridge between said system memory bus and said PCI bus; anda registered PCI device connected to said PCI bus, said registered PCI device having a status register and a control register, said registered PCI device operating according to said registered PCI protocol, said registered PCI device capable of issuing a first command on a first clock cycle of said PCI bus according to said registered PCI protocol and a second command on a second clock cycle of said PCI bus according to said registered PCI protocol, said second command being an extended command to said first command, said second command is issued on a C/BE[3:0]# portion of said PCI bus, said registered PCI device further capable of issuing an attribute during said second clock cycle.