Patent ID: 6128233
Filing Date: 2000-10-03
Classification: G11C

Abstract:
A synchronous memory device comprising:a memory cell array being comprised of a plurality of memory cells;a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals;a first register circuit for storing a plurality of input data bits in response to the internal clock signal and the control signals;a second register circuit for storing the flag signals in response to the internal clock signal and the control signals;a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle;a sense amplifier circuit coupled to the memory cell array,an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; anda switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.