Patent ID: 8099706
Filing Date: 2012-01-17
Classification: G06F

Abstract:
1. A computer-readable software product comprising codes, executed by a computer, for a method of determining parasitic resistance and capacitance from a layout of an LSI, said method comprising: providing a plurality of patterns of a wiring structure which contains a target interconnection; and producing a library configured to store parameters indicating said parasitic resistance and said parasitic capacitance of said target interconnection for each of said plurality of patterns, wherein said producing comprises: calculating said parameters for a plurality of conditions corresponding to deviation in manufacture of said wiring structure for each of said plurality of patterns, wherein said plurality of conditions comprises a 0 a desired width and desired film thickness of said target interconnection are W said 0 said first condition is a case where a delay in said target interconnection is maximized under a condition that α said second condition is when the delay in said target interconnection is minimized under the condition that α