Patent ID: 7500085
Filing Date: 2009-03-03
Classification: G06F,Y02D

Abstract:
1. A processor, comprising: fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions; decode logic coupled to the fetch logic and adapted to process the set of instructions, wherein the decode logic comprises a vector table comprising an entry for each instruction in an instruction set of the processor, each entry in the vector table comprising a first bit that indicates whether or not a micro-sequence corresponding to the instruction is to be executed when the instruction is decoded, and a second bit that indicates whether or not the instruction is to be executed if the micro-sequence is executed; and a clock coupled to the decode logic; wherein when the decode logic processes an instruction from the set of instructions and when the first bit in the entry for the instruction indicates the micro-sequence is to be executed, the micro-sequence corresponding to the instruction is executed to enable a counter external to the processor, wherein enabling the counter causes the clock to increment the counter while the subset is processed, wherein a status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.