Patent ID: 6169684
Filing Date: 2001-01-02
Classification: G06F,G11C

Abstract:
A semiconductor memory device comprising first and second memory arrays integrated together on a single semiconductor chip, the first memory array being made up of memory cells of a first type, the second memory array being made up of memory cells of a second type, wherein each said memory cell of the first type includes: first and second transistors, the sources of which are connected together; and a first data storage capacitor, one of two electrodes of the first capacitor being connected to the source, while each said memory cell of the second type includes: a third transistor; and a second data storage capacitor connected to the source of the third transistor, and wherein the first memory array includes: a first bit line connected to respective drains of the first transistors; and a second bit line connected to respective drains of the second transistors, while the second memory array includes: a third bit line connected to respective drains of the third transistors; and a fourth bit line, which is connected to respective drains of fourth transistors and is paired with the third bit line, each said fourth transistor being adjacent to associated one of the third transistors, and wherein the first and second bit lines are parallel to each other, and wherein the third and fourth bit lines are parallel to each other, and wherein a pitch defined between the first and second bit lines is equal to a pitch defined between the third and fourth bit lines.