Patent ID: 9123783
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, the method comprising: providing a base substrate having an embedded electrical contact disposed therein; forming an interlayer dielectric overlying the base substrate; etching a recess through the interlayer dielectric over the embedded electrical contact with a surface of the embedded electrical contact exposed in the recess; forming a protecting liner in the recess and over the exposed surface of the embedded electrical contact in the recess, the protecting liner comprising at least two liner layers having materially different etch rates in different etchants; removing a portion of the protecting liner over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess; forming an embedded electrical interconnect in the recess, the embedded electrical interconnect overlying the protecting liner on sides of the recess.