Patent ID: 9111592
Filing Date: 2015-08-18
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device, comprising: a plurality of peripheral circuits on a semiconductor substrate; a memory cell array having a plurality of semiconductor layers above the peripheral circuits, the memory cell array including two or more regions; a plurality of upper bit lines disposed in one or more layers above the memory cell array and extending in a first direction, each of the upper bit lines electrically connected to at least one of the peripheral circuits; a plurality of lower bit lines disposed in one or more layers below the memory cell array and extending in the first direction, each of the lower bit lines corresponding to a respective upper bit line; and a plurality of connection parts including contact plugs connecting upper bit lines to corresponding lower bit lines, wherein a first group of the upper bit lines are connected to the peripheral circuits via a first connecting part and respective lower bit lines, the first connecting part disposed between two regions of the memory cell array, and a second group of the upper bit lines are connected to the peripheral circuits via a second connecting part and respective lower bit lines, and wherein the peripheral circuits include sense amplifiers with high-breakdown voltage transistors and low-breakdown voltage transistors, and the high-breakdown voltage transistors are disposed so that a distance between the high-breakdown voltage transistor and the respective connection part is less than a distance between the low-breakdown voltage transistor and the respective connection part.