Patent ID: 6117733
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method of forming a poly tip and a self-aligned source line split-gate flash memory cell comprising the steps of:providing a semiconductor substrate having active and passive regions defined;forming a gate oxide layer over said substrate;forming a first polysilicon layer over said gate oxide layer;forming a first nitride layer over said first polysilicon layer (poly-1);forming a shallow trench ST-photomask over said first nitride layer;forming a shallow trench in said substrate by etching said first nitride layer, first polysilicon layer, gate oxide layer and said substrate;removing said ST-photomask;depositing a first oxide layer over said substrate including said shallow trench;performing chemical mechanical polishing of said first oxide layer;removing said first nitride layer;depositing a second nitride layer;forming a second oxide layer over said second nitride layer;forming a poly-1 photomask over said second oxide layer;forming openings in underlying said second oxide layer, said second nitride layer and first polysilicon layer through patterns in said poly-1 photomask to form a floating gate structure;forming a self-aligned source SAS-photomask over said poly1 photomask;etching through said SAS-photomask;removing said SAS-photomask;partial etching said second nitride layer to form a notch on an edge of said second nitride layer thus exposing a edge portion of said floating gate structure followed by oxidizing said ledge portion and sidewalls of said floating gate structure to form a sharp poly tip therebetween;forming a hot temperature oxide (HTO) layer over said substrate including said floating gate structure;forming a second polysilicon layer (poly-2) over said HTO layer;forming a poly-2 photomask over said second polysilicon layer;etching and patterning said second polysilicon layer through said poly-2 photomask to form a control gate;performing ion implantation through said patterning in said second polysilicon layer to form source regions in said substrate;removing said poly-2 photomask;forming a conformal oxide layer over said substrate;forming oxide spacers;performing ion implantation to form drain regions in said substrate;forming interlevel dielectric layer over said substrate;forming contact holes in said interlevel dielectric layer;forming metal in said contact holes; andetching back excess metal over said substrate in preparation for performing remaining process steps in manufacturing said split-gate flash memory cell.