Patent ID: 8643412
Filing Date: 2014-02-04
Classification: G01R

Abstract:
1. A test apparatus that tests a device under test, comprising: a phase comparing section that compares a phase of an internal clock generated in the test apparatus and a phase of an embedded clock superimposed on a device signal output pill by the device under test; an adjusting section that adjusts a phase shift amount of the internal clock with respect to the device signal output by the device under test, based on the phase comparison result; an acquiring section that acquires the device signal output by the device under test according to the internal clock whose phase shift amount with respect to the device signal output by the device under test is adjusted; and an inhibiting section that detects whether there exists a period during which the embedded clock is not superimposed on the device signal acquired by the acquiring section and inhibits change of the phase shift amount based on the phase comparison result, for at least a portion of the period during which the embedded clock is not superimposed on the device signal acquired by the acquiring section.