Patent ID: 6670832
Filing Date: 2003-12-30
Classification: H03K

Abstract:
An apparatus for preventing a glitch in an input signal from affecting an output signal, comprising:a first one shot pulse circuit arranged to receive the input signal and a second feedback signal and output a first pulse signal (Q1) in response to the input signal and the second feedback signal; a second one shot pulse circuit arranged to receive the input signal and a first feedback signal and output a second pulse signal (Q2) in response to the input signal and the first feedback signal; a third one shot pulse circuit coupled to the first one shot pulse circuit and coupled to the second one shot pulse circuit and arranged to output a third pulse signal (Q3) in response to signals Q1 and Q2; and a memory circuit coupled to the third one shot pulse circuit and arranged to receive the input signal and signal Q3, wherein the memory circuit is configured to load the input signal in response to signal Q3, and output an output signal relating to the loaded input signal.