Patent ID: 7545223
Filing Date: 2009-06-09
Classification: H03L

Abstract:
1. A PLL circuit, comprising: a phase comparator to output an up signal and a down signal each having a pulse width determined based on a phase difference between a reference clock signal and a feedback clock signal; an offset correcting circuit to correct a pulse width of at least one of the up signal and the down signal to output a modified up signal and a modified down signal; a first charge pump circuit to increase or decrease a charge pump output voltage to be output in accordance with the modified up signal and the modified down signal; a loop filter to filter out noise of the charge pump output voltage and generate a filter voltage; and a voltage-controlled oscillation circuit having an oscillation frequency controlled based on a voltage value of the filter voltage and outputting an output clock signal, the offset correcting circuit setting a pulse width of at least one of the modified up signal and the modified down signal such that the charge pump output voltage becomes substantially constant if a phase of the reference clock signal matches with a phase of the feedback clock signal.