Patent ID: 6707850
Filing Date: 2004-03-16
Classification: H04L

Abstract:
A decision feedback equalizer (DFE) comprising:a first summing node having a first input for receiving an input signal, a second input for receiving a second feedback signal, and an output; a maximum likelihood sequence estimator (MLSE) for estimating a symbol sequence and having an input connected to the output of the first summing node, and having an output; a second summing node having a first input connected to the output of the first summing node, a second input for receiving a first feedback signal, and an output; a signal level decoder having an input connected to the output of the second summing node, and having an output; a delay line comprising a first plurality of taps being connected to the output of the signal level decoder, and generating respective first tap signals based upon respective first coefficients, and a second plurality of taps being connected to the output of the MLSE, and generating respective second tap signals based upon respective second coefficients; a first summing circuit for summing the first tap signals to generate the first feedback signal; a second summing circuit for summing the second tap signals to generate the second feedback signal; and an error signal generator having a first input connected to the input of the signal level decoder, and a second input connected to the output of the signal level decoder for adjusting the first and second coefficients.