Patent ID: 7208827
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A semiconductor component package configuration, comprising: a semiconductor chip having wiring terminals; a printed circuit board having said semiconductor component mounted thereon; a substrate configured between said semiconductor chip and said printed circuit board, said substrate for routing said wiring terminals of said semiconductor chip to said printed circuit board; solder joints connecting said substrate to said printed circuit board; a filler configured between said semiconductor chip and said substrate, said filler for mechanically isolating said semiconductor chip and said soldered joints; a metal layer applied to said substrate, said metal layer being connected to at least one of said solder joints; and at least one molded element of heat-dissipating material applied to said metal layer, said molded element connected in a heat-conducting manner to said metal layer, said molded element not directly contacting said semiconductor chip.