Patent ID: 6180529
Filing Date: 2001-01-30
Classification: G02F,H01L

Abstract:
A method of making a PIN diode structure, the method comprising the steps of:providing a substrate;providing a bottom electrode on the substrate;depositing a substantially continuous insulation layer over the bottom electrode;forming a contact hole in the substantially continuous insulation layer at a location where a PIN diode is to be formed;depositing a n+ doped semiconductor layer, an intrinsic semiconductor layer, and a p+ doped semiconductor layer on the substrate over the bottom electrode and over a portion of the insulation layer so that one of (i) the n+ doped semiconductor layer, and (ii) the p+ doped semiconductor layer contacts the bottom electrode through the contact hole;providing a top electrode layer on the substrate over the p+ doped, n+ doped, and intrinsic semiconductor layers;patterning the top electrode layer to form a top electrode for the PIN diode; andetching each of the n+ doped semiconductor layer, the p+ doped semiconductor layer, and the intrinsic semiconductor layer in order to form the PIN diode at the location on the substrate where the contact hole was formed in the insulation layer.