Patent ID: 7552378
Filing Date: 2009-06-23
Classification: G06F

Abstract:
1. A semiconductor device comprising: a memory cell array storing a data group formed of a plurality of data bits and a plurality of parity bits, and an error correcting circuit executing correction on an error bit in said plurality of data bits and said plurality of parity bits constituting said data group output from said memory cell array, wherein said error correcting circuit comprises an XOR circuit group obtaining a syndrome based on a matrix product of a check matrix represented in binary and a matrix formed of data logic values of respective bits in said data group output from said memory cell array, and a correcting circuit correcting an error bit in said plurality of information bits and said plurality of parity bits based on said syndrome output from said XOR circuit group, wherein said XOR circuit group includes a plurality of check circuits receiving inputs of said plurality of data bits and said plurality of parity bits to compute each data of a plurality of bits constituting said syndrome, wherein each of said check circuits includes a plurality of XOR gates, each receiving 2 bits from a group comprising said plurality of data bits and said plurality of parity bits, input thereof determined by corresponding to matrix elements of each row in said check matrix, wherein the number of inputs of each check circuit corresponds with the number of said matrix elements having a first state value, wherein said XOR circuit group includes a plurality of said XOR gate group, wherein at least one of said XOR gate groups in each check circuits, which comprises 2 wherein at least two of said plurality of XOR gate groups are arranged in combination in an inverted manner with respect to each other such that an area of said at least two XOR gate groups is reduced.