Patent ID: 6542015
Filing Date: 2003-04-01
Classification: H03K

Abstract:
A duty cycle correction circuit for receiving at a pair of differential inputs an uncorrected differential clock signal having a sinusoidal characteristic and outputting at a pair of differential outputs a corrected differential square wave clock signal, comprising:a first differential pair of transistors coupled to a first current source at one of their sources and drains, coupled by the other of their sources and drains to a differential comparator, the connection nodes of the first differential pair of transistors and of the comparator comprising a pair of internal nodes, the differential comparator being responsive to crossovers in current at the pair of internal nodes to provide a differential square wave output signal at the pair of differential outputs, and the first differential pair of transistors being coupled by their gates to the pair of differential inputs, a second differential pair of transistors coupled to a second current source at one of their sources and drains, coupled to the pair of internal nodes at the other of their sources and drains, and adapted to receive differential control signals at their gates; and a duty cycle correction feedback circuit having a pair of feedback inputs coupled to the pair of differential outputs and having a pair of feedback outputs, comprising a capacitor coupled across the pair of feedback outputs, and circuitry for adding or subtracting charge to one plate of the capacitor in accordance with the corrected differential clock signal so as to control a differential voltage across the capacitor, the differential voltage across the capacitor being coupled to the pair of feedback outputs; and an amplifier adapted to amplify and invert the differential voltage across the pair of feedback outputs to provide the differential control signals having a level adapted to control current provided to the pair of internal nodes by the amplifier so as to control the timing of the crossover of differential current at the pair of internal nodes to provide duty cycle correction.