Patent ID: 7518844
Filing Date: 2009-04-14
Classification: H02H

Abstract:
1. An ESD protection circuit for an integrated circuit, comprising: a diode circuit electrically coupled to a signal bus pad and an internal circuit of said integrated circuit; a pseudo power supply circuit electrically coupled to said diode circuit, said pseudo power supply circuit including a pseudo first power supply line that is electrically coupled to an actual first power supply line having a first voltage supply level such that said first pseudo power supply line receives said first voltage supply level from said actual first power supply line and a pseudo second power supply line that is electrically coupled to an actual second power supply line having a second voltage supply level such that said pseudo second power supply line receives said second voltage supply level from said actual second power supply line, said pseudo first power supply line and said pseudo second power supply line clamped by an ESD clamping circuit at a third voltage level, wherein said pseudo power supply circuit is operable, upon an occurrence of an ESD event at the signal bus pad to cause said diode circuit to conduct and to provide a discharge path, and wherein said pseudo power supply circuit is operable, upon an occurrence of an over-voltage event at the signal bus pad, to prevent said diode circuit from conducting, wherein said over-voltage event occurs when the voltage at the signal bus pad either exceeds the first voltage supply level or is lower than the second voltage supply level, but is still within a normal operating voltage range of the integrated circuit.