Patent ID: 6667930
Filing Date: 2003-12-23
Classification: G11C

Abstract:
An apparatus for accessing synchronous dynamic random access memory (SDRAM), the SDRAM having four memory banks, where each memory bank can be accessed independently, the apparatus comprising:a rendering engine receiving at least graphics-related information; and an checkerboard optimization circuit, the checkerboard optimization circuit receiving memory location information from the rendering engine and associating the memory location information with the memory banks in the SDRAM, the checkerboard optimization circuit associating the memory location information with the memory banks in the SDRAM by utilizing a checkerboard pattern wherein the checkerboard pattern is divided into 16 squares with each square associated with one memory bank, and the checkerboard formed by a first basic block and a second basic block, the first basic block being a mirror image of the second basic block, and each basic block being further formed by four squares.