Patent ID: 7203557
Filing Date: 2007-04-10
Classification: G10L,H04S

Abstract:
1. An apparatus for delaying an audio signal comprising: a first FIFO register receptive to a digital audio signal, the digital audio signal having an associated clock signal; an audio format detection circuit coupled to the first FIFO register and operative to detect a format of the digital audio signal by analyzing the associated clock signal; a memory controller coupled to the FIFO register; a memory chip coupled to the memory controller; a write address generator coupled to the audio format detection circuit and memory controller; a read address generator coupled to the memory controller; and a second FIFO register coupled to the memory controller and operative to provide a time delay in the digital audio signal the duration of which is related to the detected format of the digital audio signal; wherein the digital audio signal further comprises a serial audio clock signal and a plurality of accompanying signals; wherein the audio format detection circuit comprises a synchronization circuit operative to synchronize the serial audio clock and a reference clock and, an edge detection circuit operative to detect edge transitions in the synchronized serial and reference clock.