Patent ID: 6938131
Filing Date: 2005-08-30
Classification: G06F

Abstract:
1. A method of memory access serialization in a computer having a plurality of CPUs and a memory shared by the plurality of CPUs, each CPU having an out-of-order execution slop mechanism, in which, if address regions on the memory relating to a pair of a store instruction and a load instruction in preceding and subsequent positions, respectively, in written order of a program executed by each of the CPUs have an overlap therebetween, the out-of-order execution stop mechanism stops our-of-order execution of the load instruction and enables data relating to the store instruction to be observed from ether CPUs before execution of the load instruction, said method comprising: a detection step of enabling each CPU to detect the pair of the store instruction and the load instruction, which need to be serialized in a before-after relationship with respect to memory access, which are in the preceding and subsequent positions in written order on the program, and which are placed on the program by being set so that their address regions have an overlap therebetween and respectively include address regions for data which needs to be stored and loaded; and an activation step of activating, with respect to a detected pair of instructions, the out-of-order execution stop mechanism of one of the CPUs executing the program relating to the detected pair of instructions.