Patent ID: 6741112
Filing Date: 2004-05-25
Classification: H03K

Abstract:
A comparator with hysteresis, comprising:an input node and an output node; a first pair of transistors including a first transistor and a second transistor, respective sources of said first pair of transistors connected to a first supply voltage, a gate of said first transistor connected to said input node and a drain of said first transistor connected to said output node; an inverter having an input connected to said gate of said first transistor and an output connected to a gate of said second transistor; a second pair of transistors including a third transistor and a fourth transistor, respective sources of said second pair of transistors connected to a second supply voltage, a gate of said third transistor connected to a drain of said fourth transistor, a gate of said fourth transistor connected to a drain of said third transistor, drains of said second pair of transistors connected respectively to said drains of said first pair of transistors; and a feedback path from said output node to said output of said inverter.