Patent ID: 6661062
Filing Date: 2003-12-09
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit device comprising:a first MISFET for a logic circuit having a first gate insulating film and a first gate electrode formed on said first gate insulating film; a second MISFET having a second gate insulating film which has a thickness larger than that of said first gate insulating film; a third MISFET for a memory cell having a third gate insulating film which has a thickness larger than that of said first gate insulating film; and a first capacitive element having a fourth gate insulating film which has a thickness larger than that of said first gate insulating film and a fourth gate electrode formed on said fourth gate insulating film, wherein said fourth gate insulating film is formed on a first well region formed in a semiconductor substrate such that said first well region serves as one of two electrodes of said first capacitive element and said fourth gate electrode of said first capacitive element serves as the other of said two electrodes of said first capacitive element, and wherein said first capacitive element is provided in a phase-locked loop circuit.