Patent ID: 7157951
Filing Date: 2007-01-02
Classification: G06F,H03K

Abstract:
1. A delay structure for a clock generator generating a plurality of clock outputs, said delay structure comprising: a plurality of delay elements coupled in series for receiving a clock signal, each delay element comprising: a phase detector coupled to compare the output signals of at least two delay elements of the plurality of delay elements, the phase detector providing an error signal representative of a difference between the phases of the output signals of the at least two delay elements; an output generator coupled to receive the third delayed clock signal from each trim unit of the plurality of delay elements and provide an output clock signal of the delay structure; and a control circuit adapted to provide the control signals to the trim units of the plurality of delay elements and to provide output control signals to the output generator, the control signals provided to the trim units being based upon the error signal representative of the difference between the phases of the output signals of the at least two delay elements received from the phase detector.