Patent ID: 7092047
Filing Date: 2006-08-15
Classification: G02F

Abstract:
1. A substrate comprising: a gate pattern formed on a pixel region and a peripheral region, the pixel region and the peripheral region being disposed on the substrate; an active pattern insulated from the gate pattern to be formed on the gate pattern, the active pattern including a semiconductor layer; a data pattern electrically connected to a portion of the active pattern, said data pattern including a data electrode; a first insulating interlayer formed on the data pattern, the first insulating interlayer having a first contact hole for partially exposing the data electrode of the data pattern, a second contact hole for exposing a gate electrode of a first drive transistor of the peripheral region, and a third contact hole for exposing a data electrode of a second drive transistor of the peripheral region; and an electrode pattern part formed on the first insulating interlayer, the electrode pattern part including a first electrode pattern in contact with a data electrode of the pixel region through the first contact hole, and a second electrode pattern connecting the partially exposed gate electrode of the first drive transistor with the exposed data electrode of the second drive transistor through the second and third contact holes.