Patent ID: 6341275
Filing Date: 2002-01-22
Classification: G06K,G06N

Abstract:
A Hamming neural network circuit for finding the matching rates between a to-be-recognized pattern and a plurality of standard patterns, comprising:an I/O circuit enabled by a chip select signal for inputting and outputting said plurality of standard patterns; a bi-directional transmission ate array connected to said I/O circuit and controlled by a programming signal; a plurality of standard pattern memory units for storing said plurality of standard patterns respectively, each connected to said bi-directional transmission gate array; an address decoder connected to said plurality of standard pattern memory units for addressing said plurality of standard pattern memory units; a plurality of pattern matching calculation circuit units respectively connected to said plurality of standard pattern memory units, each receiving said to-be-recognized patterns, and generating a plurality of matching rates between said to-be-recognized pattern and said plurality of standard patterns; and an expandable matching rate comparing circuit having a plurality of inputs respectively connected to said plurality of pattern matching calculation circuits and having a plurality of outputs respectively corresponding to said plurality of inputs for comparing and sorting said plurality of matching rates to sequentially present a plurality of high voltage pulses on said plurality of outputs in order of magnitude of the matching rate.