Patent ID: 7599166
Filing Date: 2009-10-06
Classification: H01G

Abstract:
1. A multilayer chip capacitor comprising: a capacitor body having a plurality of dielectric layers stacked one atop another; a plurality of internal electrode layers separated from each other in the capacitor body by the dielectric layers, wherein each of the internal electrode layers has one or two leads extending to an outer surface of the capacitor body, and includes at least one coplanar electrode plate; and a plurality of external electrodes arranged on the outer surface of the capacitor body and electrically connected to the internal electrode layers via the leads, wherein the internal electrode layers constitute a plurality of blocks stacked repeatedly one atop another, each of the blocks including a plurality of the internal electrode layers which are arranged successively in a stacking direction; each of the electrode plates has one lead extending to a face of the capacitor body; the leads extending to the face of the capacitor body are arranged in a zigzag shape along the stacking direction; and the leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other, wherein the total number of the external electrodes is eight, and wherein each of the blocks includes six of the internal electrode layers which are arranged successively in the stacking direction.