Patent ID: 7777575
Filing Date: 2010-08-17
Classification: H03F

Abstract:
1. An integrated circuit comprising: a single-ended input node; a first differential output node; a second differential output node; an inverting stage coupled between the single-ended input node and the first differential output node, the inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the first differential output node, and the control terminal being coupled to the single-ended input node; and a non-inverting stage coupled between the single-ended input node and the second differential output node, the non-inverting stage comprising at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the second differential output node, and the second current terminal being coupled to the single-ended input node; wherein a bias current of the inverting stage is larger than a bias current of the non-inverting stage.