Patent ID: 6204140
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method, comprising:(a) forming a trench capacitor in a semiconductor body;(b) forming a recess in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body;(c) depositing a first material over the sidewalls and over a bottom of the recess;(d) depositing a second material over the first material;(e) providing a mask over the second material, such mask having: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material;(f) selectively removing portions of the exposed underlying portions of the second material while leaving substantially un-etched exposed underlying portions of the first material;(g) selectively removing the exposed portions of the first material and underlying portions of the semiconductor body;(h) forming an isolation region in the removed portions of the semiconductor body.