Patent ID: 8731025
Filing Date: 2014-05-20
Classification: H03C

Abstract:
1. An offset phase-locked loop (PLL) transmitter, comprising: a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts an operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value, wherein the control circuit comprises: wherein the determining module comprises: