Patent ID: 7508479
Filing Date: 2009-03-24
Classification: G09G,G11C

Abstract:
1. A liquid crystal display apparatus comprising: a first substrate having a display region and a peripheral region adjacent to the display region; a second substrate facing the first substrate; and a liquid crystal interposed between the first and second substrates, wherein the first substrate further comprises: a plurality of switching devices formed in the display region in a matrix; a plurality of pixel electrodes formed in the display region in the matrix, each of the plurality of pixel electrodes being connected to a first current electrode of each switching device of the plurality of switching devices; a plurality of gate lines arranged in a row, each of the plurality of gate lines being commonly connected to control electrodes of switching devices arranged in the row among the plurality of switching devices; a plurality of data lines arranged in a column, each of the plurality of data lines being commonly connected to second current electrodes of switching devices arranged in the column among the plurality of switching devices; a gate driving circuit, formed in a first region of the peripheral region to which first ends of the plurality of gate lines are extended, for sequentially scanning the plurality of gate lines; and an integrated driving chip, directly attached to a second region of the peripheral region to which first ends of the plurality of data lines are extended, for providing a driving control signal to the gate driving circuit in response to an external image data and an external control signal, and providing an analog signal to the plurality of data lines, respectively, each analog signal provided to the plurality of data lines from the integrated driving chip is commonly connected to at least two adjacent data lines of the plurality of data lines, wherein the first region of the peripheral region corresponds to the second substrate, and the second region of the peripheral region does not correspond to the second substrate, the driving control signal comprises a start signal, a first clock signal and a second clock signal, the gate driving circuit comprises a shift register including cascade-connected plural stages, the plural stages having a first stage in which the start signal is applied to an input terminal of the first stage, and wherein the shift register sequentially selects the plural gate lines using an output signal outputted from an output terminal of each stage, each stage further comprises: an input terminal connected to a gate line connected to the output terminal of a previous stage; the output terminal connected to a corresponding gate line; a control terminal connected to a gate line connected to the output terminal of a next stage; a clock terminal into which a corresponding clock signal is inputted; a pull-up unit configured to provide a corresponding clock signal of the first and second clock signals to the output terminal; a pull-down unit configured to provide a first power voltage to the output terminal; a pull-up driving unit, configured to an input node of the pull-up unit, the pull-up driving unit being configured to turn on the pull-up unit by means of charging a capacitor in response to a rising edge of an input signal inputted from the input terminal, turn off the input unit by means of discharging the capacitor in response to a rising edge of a driving signal, which is inputted from the control terminal, and drive the gate line connected to the next stage; and a pull-down driving unit, connected to an input node of the pull-down unit and connected to the input node of the pull-up unit, the pull-down driving unit being configured to turn off the pull-down unit, and turn on the pull-down unit in response to the rising edge of the driving signal for driving the gate line connected to the next stage.