Patent ID: 6842389
Filing Date: 2005-01-11
Classification: G11C

Abstract:
1. A four-conductor MRAM device comprising: an array of memory cells, each of said memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to said first magnetic layer of said array of memory cells; a plurality of local row sense lines wherein one of said local row sense lines is electrically connected to said second magnetic layer of said array of memory cells; a plurality of global column write lines parallel to said plurality of local column sense lines, said plurality of global column write lines electrically insulated from said plurality of local column sense lines; a plurality of global row write lines parallel to said plurality of local row sense lines, said plurality of global row write lines electrically insulated from said plurality of local row sense lines; and wherein (i) said plurality of local column sense lines and said plurality of local row sense lines are connected to read data from said array of memory cells and (ii) said plurality of global column write lines and said plurality of global row write lines are connected to write data to said array of memory cells.