Patent ID: 8729710
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a substrate including opposed first and second conductive patterns disposed thereon and electrically connected to each other; at least one semiconductor die mounted to the substrate and electrically connected to the first conductive pattern thereof; a patterning layer defining a first surface, the patterning layer at least partially encapsulating the semiconductor die and at least partially covering the first conductive pattern the second conductive pattern not being covered by the patterning layer; and a wiring pattern embedded in the patterning layer and including a first via pattern that extends from the first surface directly to the first conductive pattern, the wiring pattern configured to directly electrically connect the semiconductor die to the first conductive pattern of the substrate, a portion of the wiring pattern being exposed in and flush with the first surface of the patterning layer; and a protective layer on the patterning layer and completely covering and insulating the portion of the wiring pattern exposed at the first surface thereof.