Patent ID: 6892263
Filing Date: 2005-05-10
Classification: G06F

Abstract:
1. A computer system comprising: a central processing unit (CPU); a peripheral bus; a bus interface unit coupled to accommodate communications between said CPU and said peripheral bus; a first daughtercard configured to assert a first configuration change signal in response to said first daughtercard being inserted within a first connector associated with said peripheral bus; a second daughtercard configured to assert a second configuration change signal in response to said second daughtercard being inserted within a second connector associated with said peripheral bus; and wherein said bus interface unit includes a storage unit including a first storage location for storing a state of said first configuration change signal and a second storage location for storing a state of said second configuration change signal, and wherein the first storage location is coupled to receive the first configuration change signal via a first signal line and the second storage location is coupled to receive the second configuration change signal over a second signal line that is separate from the first signal line.