Patent ID: 7960244
Filing Date: 2011-06-14
Classification: H01L,Y10S

Abstract:
1. A process for manufacturing an electronic semiconductor device, comprising the steps of: providing a SOI wafer comprising a stack formed by a bottom layer of semiconductor material, an insulating layer and a top layer of semiconductor material; making alignment marks in said top layer; forming an implanted buried region in said top layer, aligned to said alignment marks; forming a hard mask on top of said top layer, the hard mask having an opening exposing the top layer within the alignment marks; using said hard mask, selectively removing a portion exposed in said top layer so as to form a trench extending up to said insulating layer; forming, in said trench, a lateral-insulation region contiguous to said insulating layer and delimiting, with said insulating layer, an insulated well of semiconductor material; and forming electronic components in said top layer.