Patent ID: 6821833
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A method of forming a CMOS semiconductor device with a PFET area and an NFET area formed on a semiconductor substrate, said PFET area being covered with a PFET gate dielectric layer and said NFET area covered with an NFET gate dielectric layer composed if silicon oxide with different degrees of nitridation thereof,providing a silicon substrate with a PFET area and an NFET area, forming a PFET gate oxide layers over said PFET area and an NFET gate oxide layer over said NFET area, providing nitridation of said PFET gate oxide layers over said PFET area and an NFET gate oxide layer over said NFET area, providing nitridation of said PFET gate oxide layer above said PFET area to form said PFET gate dielectric layer above said PFET area with a first optimized concentration level of nitrogen atoms in said PFET gate dielectric layer above said PFET area, providing nitridation of said NFET gate oxide layer to form said NFET gate dielectric layer above said NFET area with a second optimized concentration level of nitrogen atoms in said NFET gate dielectric layer above said NFET area, whereby an NFET concentration level of nitrogen atoms in said NFET gate dielectric layer is different from a PFET concentration level of nitrogen atoms in said PFET gate dielectric layer.