Patent ID: 7060561
Filing Date: 2006-06-13
Classification: H01L

Abstract:
1. A method for fabricating a memory device, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive layer on the first dielectric layer; patterning the first conductive layer and the first dielectric layer to form a plurality of stacked gate lines and simultaneously patterning a plurality of trenches in the substrate, in a same process of photolithography and etching; filling an insulating material into the trenches to form a plurality of strip isolation structures m the substrate, wherein the plurality of strip isolation structures are substantially parallel to one another; forming a second dielectric layer over the substrate covering the stacked gate lines and the strip isolation structures; patterning the second dielectric layer such that portions of second dielectric layer are removed to expose the first conductive layer at predetermined locations; forming a second conductive layer over patterned second dielectric layer; patterning the second conductive layer to form a plurality of select gate lines and a plurality of control gate lines, each said select gate line being disposed on the first conductive layer and each control gate line being disposed on the second dielectric layer, wherein the select gate lines and the control gate lines are disposed in a direction substantially vertical to the strip isolation structures; forming a plurality of source/drain regions in the substrate beside the select gate lines and the control gate lines; forming a third dielectric layer over the substrate covering the select gate lines and the control gate lines, wherein the third dielectric layer includes a plurality of contact openings in the third dielectric layer, exposing at least one of the select gate lines and at least one of the control gate lines; and filling a conductive material into the contact openings to form a plurality of contacts that connects to at least one of the select gate lines and at least one of the control gate lines.