Patent ID: 7208989
Filing Date: 2007-04-24
Classification: G06F,G11C,H03K,H03L

Abstract:
1. A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising: an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal; an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs; a frequency divider circuit having an input coupled to the output of the input buffer and an output, the frequency divider circuit configured to generate a frequency-divided clock signal having a clock frequency less than the input clock signal; an adjustable delay circuit having an input coupled to the output of the frequency divider circuit, an output, a control node, and a half-delay tap, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the frequency-divided clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the frequency-divided clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap; a fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output, the fixed delay circuit configured to generate a delayed clock signal at the output having a fixed delay relative to the full-delayed clock signal; a logic circuit having a first input coupled to the half-delay tap and a second input coupled to the output of the fixed delay circuit, and further having a first output coupled to the first input of the output buffer and a second output coupled to the second input of the output buffer, the logic circuit configured to combine the half-delayed clock signal and the delayed clock signal and generate the first clock signal and the second clock signal, the first and second clock signals having respective frequencies equal to the frequency of the input clock signal; and an adjustable delay circuit controller coupled to the adjustable delay circuit and the output of the input buffer, the adjustable delay circuit controller configured to adjust the adjustable delay to provide a forward delay equal to an odd multiple of a period of the input clock signal, the forward delay including an input buffer delay of the input buffer, the adjustable delay, the first fixed delay, and an output buffer delay of the output buffer.