Patent ID: 6445625
Filing Date: 2002-09-03
Classification: G11C

Abstract:
A redundancy match signal latch circuit, comprising:a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal; a latch input for providing a redundancy match signal to the pair of reverse-coupled inverters; and a latch output for providing a latched match signal from the pair of reverse-coupled inverters; wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either the redundancy match signal or a test input signal; wherein a logic level of the latched match signal is independent of a logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal; and wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal.