Patent ID: 7472370
Filing Date: 2008-12-30
Classification: G06F

Abstract:
1. A processor-implemented method for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design, the method comprising: inputting the netlist that describes the PLD design, the netlist including a plurality of instances of a plurality of modules and the modules including a plurality of tile modules; for each of the tile modules, inputting a respective identification of the tile module; for each of the tile modules, inputting a respective specification of a tile representation that graphically represents the tile module, the respective specification including a plurality of connection representations that terminate at a boundary of the tile representation; inputting a specification of an arrayed placement of occurrences of the tile representations in the graphical representation of the PLD design, wherein each occurrence of one of the tile representations corresponds to one of the instances of the tile module for the tile representation; for each abutting pair of occurrences of the tile representations in the arrayed placement, determining the connection representations of the tile representations of the abutting pair that terminate at a shared portion of the boundaries of the tile representations of the abutting pair; and for each of a plurality of positions within the shared portion of the boundaries of the tile representations of each abutting pair, checking for a match between the connection representations terminating at the position of the shared portion of the boundaries of the tile representations of the abutting pair.