Patent ID: 6011734
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A semiconductor device comprising:a memory array having a plurality of rows;a built-in self test (BIST) portion for detecting a defective row within the memory array, and having an output node for providing a BIST FAIL signal, wherein the BIST FAIL signal is active for indicating the defective row is detected;a first row decoder coupled to the plurality of rows in the memory array;circuitry for latching an address of the defective row, the circuitry having an input node for receiving the BIST FAIL signal, wherein the address of the defective row is latched when the BIST FAIL signal is active;a plurality of redundant rows;a second row decoder coupled to the circuitry for latching and to the plurality of redundant rows; anda control circuit coupled to the plurality of redundant rows and to the first row decoder for preventing the first row decoder from enabling the defective row and replacing the defective row with a redundant row.