Patent ID: 7454576
Filing Date: 2008-11-18
Classification: G06F,Y10S

Abstract:
1. A processor, comprising: a first core with a first cache including a first group of cache locations of a first length and a second group of cache locations of a second length; a second cache at a hierarchy level further from said first core than said first cache, with a third group of cache locations of a third length; a first logic to perform coherency operations, to hold a directory entry of a first cache line in one of said third group of cache locations with fields corresponding to cache lines in said first cache, said directory entry including a vector to represent presence or absence of portions of said first cache line in said first group and said second group of cache locations; and a second core with a third cache including a fourth group of cache locations of said first length and a fifth group of cache locations of said second length; wherein said second cache includes a first register group to track requests made to said first cache and said third cache for portions of said first cache line in said first group, second group, fourth group, and fifth group of cache locations.