Patent ID: 7975211
Filing Date: 2011-07-05
Classification: H03M,H04L

Abstract:
1. A receiver applying High Speed Downlink Packet Access technology, the receiver comprising: a memory for temporarily holding information bits, which are receive data strings, and first check bits and second check bits, which are reliability information of the information bits; a first rate dematch apparatus for performing first rate dematch processing defined by the High-Speed Downlink Packet Access on the first check bits and the second check bits; a memory group including memories each holding the information bits supplied through the first rate dematch apparatus and the first check bits and second check bits having undergone the first rate dematch processing and outputting the information bits, first check bits and second check bits at predetermined times; a decoder for decoding and reconstructing receive data by using the information bits, first check bits and second check bits output from the memory group; and a controller for, in synchronization with the output of the information bits from the memory group to the decoder, outputting the first check bits corresponding to the information bits from the memory group to the decoder, causing the first rate dematch apparatus to perform the first rate dematch processing on the second check bits, storing the first rate dematch processing result to the memory group, and, after the end of an output of the first check bits from the memory group and in synchronization with an output of the information bits from the memory group to the decoder, outputting the second check bits corresponding to the first check bits and the information bits from the memory group to the decoder.