Patent ID: 7955944
Filing Date: 2011-06-07
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a wiring layer in a first insulating layer; forming a second insulating layer over the first insulating layer; forming a first conductive layer over the second insulating layer; forming a dielectric layer on the first conductive layer; forming a second conductive layer on the dielectric layer; selectively removing the second conductive layer to form an upper electrode on the dielectric layer; forming a first layer over the upper electrode and the dielectric layer; selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode; forming a third insulating layer over the second insulating layer and the first layer, the third insulating layer having the etching resistance property smaller than the etching resistance property of the second insulating layer and the first layer against an etchant for etching the third insulating layer; selectively removing the third insulating layer to form a first aperture exposing the second insulating layer above the wiring layer, a second aperture exposing the first layer above the upper electrode, and a third aperture exposing the first layer above the dielectric layer; and performing an etching operation to expose the wiring layer below the first aperture, the upper electrode below the second aperture, and the lower electrode below the third aperture.