Patent ID: 6684267
Filing Date: 2004-01-27
Classification: G06F

Abstract:
A direct memory access controller comprising:a first register which stores the base address of a transfer-source area; a second register which stores the base address of a transfer-destination area; a third register which stores a data read position in the transfer-source area as the offset from the base address stored in said first register; a fourth register which stores a data write position in the transfer-destination area as the offset from the base address stored in said second register; a fifth register which stores a value that indicates a total amount of transferred data; and a control section which provides a control for repeating an operations for reading data from a transfer-destination address decided in accordance with the data stored in said first register and said third register, writing the read data in a transfer-destination address decided in accordance with the data stored in said second register and said fourth register, and updating the data stored in said third register and said fourth register by the transferred amount of data until the data stored in said fourth register coincides with the data stored in said fifth register.