Patent ID: 6774417
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A semiconductor device comprising:a p-type semiconductor substrate; an n-type well formed in said semiconductor substrate; a dielectric layer formed on a surface of said semiconductor substrate, wherein said dielectric layer comprises a portion disposed above said n-type well; a first interface bonding pad formed on a surface of said dielectric layer, wherein said bonding pad comprises a portion disposed above said n-type well; a first enhancement mode junction field effect transistor (JFET) comprising a first threshold voltage formed in said n-type well and disposed beneath said interface bonding pad, said JFET comprising a gate coupled to said interface bonding pad, a drain coupled to said interface bonding pad, and a source coupled to said p-type semiconductor substrate; a source contact formed in said n-type well; and a plurality of contact vias for coupling said gate and said drain to said interface bonding pad.