Patent ID: 6085306
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A VLIW (Very Long Instruction Word) processor that decodes and executes an instruction that has at least three operation fields, of which a first operation field can only include one operation code for specifying an operation type and a second operation field includes a combination of one operation code and at least one operand used in an operation indicated by the second operation field, wherein a number of bits occupied by the first operation field in the instruction is less than a number of bits occupied by the second operation field,a number of bits occupied by the operation code in the first operation field is equal to a number of bits occupied by the operation code in the second operation field; anda third operation field occupies the same number of bits as the second operation field and includes a combination of one operation code and at least one operand,the VLIW processor comprising:first decoding means for decoding the operation code in the first operation field;first execution means for executing an operation indicated by the operation code in the first operation field in accordance with a decoding result of the first decoding means; second decoding means for decoding the operation code in the second operation field;second execution means for executing the operation indicated by the operation code in the second operation field on data which is indicated by the operands in the second operation field, in accordance with a decoding result of the second decoding means;third decoding means which decodes, when an operation code is present in the third operation field, the operation code in the third operation field; andthird executing means for executing an operation indicated by the operation code in the third operation field on data which is indicated by the operands in the third operation field, in accordance with a decoding result of the third decoding means.