Patent ID: 6301183
Filing Date: 2001-10-09
Classification: G11C

Abstract:
A method for operating an integrated circuit memory device having an address bus and a data bus, said method comprising:providing at least one dynamic random access memory array having at least one static register associated therewith;placing address signals on said address bus corresponding to a selected memory location in said at least one dynamic random access memory array;inputting data signals on said data bus corresponding to write data to be written to said selected memory location in said at least one dynamic random access memory array;placing other address signals on said address bus corresponding to read data to be read from another selected memory location in said at least one dynamic random access memory array;storing at least a portion of said read data to said at least one static register;outputting said read data on said data bus from said at least one static register;performing a refresh operation to said at least one dynamic random access memory array during at least a portion of said step of outputting said read data; andproviding a wait signal output from said memory device indicative of said refresh operation.