Patent ID: 9013991
Filing Date: 2015-04-21
Classification: G06F

Abstract:
1. A multicore processor including a plurality of processor cores arranged in multiple collision domain networks, the multicore processor comprising: a first collision domain network comprising a first set of processor cores of the multicore processor that are configured in communication with one another; a second collision domain network comprising a second set of processor cores of the multicore processor that are configured in communication with one another; a domain interconnection network configured to segregate a first plurality of competing communications within the first collision domain network from a second plurality of competing communications within with the second collision domain network, wherein the first collision domain network and the second collision domain network are on a single integrated circuit; and a first traffic management core associated with the domain interconnection network, wherein the first traffic management core is configured to facilitate communications between the domain interconnection network and one or more of the first collision domain network and/or the second collision domain network, wherein the first traffic management core is configured to facilitate communications between the domain interconnection network and the first collision domain network by restriction of the first collision domain network from the domain interconnection network based at least in part on a determination of excessive data requests by the first collision domain network.