Patent ID: 8612728
Filing Date: 2013-12-17
Classification: G06F

Abstract:
1. A method of operating a pipelined computer processor, comprising: identifying instructions dependent upon results of prior instructions in a set of instructions; dividing the set of instructions into a plurality of subsets of instructions, individual ones of the plurality of subsets of instructions comprising a number of instructions from the set of instructions and belonging to only one of the plurality of subsets of instructions; allocating a group of registers, wherein a first set of the group of registers corresponds to a first set of input data and a second set of the group of registers corresponds to a second set of input data; interleaving the plurality of subsets of instructions: processing a first subset of the plurality of subsets of instructions on the first set of input data during a first pass to produce a processed set of data, wherein the processed set of data is stored in the first set of registers; and processing a second subset of the plurality of subsets of instructions on the processed set of data during a second pass different than the first pass and processing the first subset of the plurality of subsets of instructions on the second set of input data during the second pass, wherein the processed set of data is read from the first set of registers and the second set of input data is read from the second set of registers.