Patent ID: 7441109
Filing Date: 2008-10-21
Classification: G06F

Abstract:
1. A computer system on a single chip for executing predicated instructions wherein each instruction includes a guard, the value of which determines whether or not that instruction is executed, the computer system comprising: a fetch unit for fetching instructions to be executed; a decode unit for decoding said instructions; at least one pipelined execution unit for executing decoded instructions and being associated with a guard register file holding values of the guards to allow resolution of the guards to be made to determine whether an instruction is committed; and an emulation unit including control circuitry which cooperates with the decode unit to selectively control the decode unit to implement step-by-step execution of an instruction sequence wherein, for each committed instruction, a divert debug routine is executed by the computer system and for each non-committed instruction the next instruction in the instruction sequence is executed; wherein, for each instruction in the sequence, the decode unit is operable to issue a request to the execution pipeline for guard resolution, the guard resolution being transmitted to the control circuitry of the emulation unit which implements said divert debug routine if the instruction is committed.