Patent ID: 8953669
Filing Date: 2015-02-10
Classification: H04B,H04L

Abstract:
1. A decision feedback equalizer, comprising: a first weighting addition circuit that adds an input signal and weighted versions of first to nth feedback signals together, n being an integer not less than 2; a first decision circuit that decides whether or not the result of addition by the first weighting addition circuit is at least a defined threshold value and that outputs the decision to a shift register, the first decision circuit operating in synchronism with a clock signal; the shift register sequentially holding the decision output by the first decision circuit in synchronism with the clock signal, the shift register outputting contents held by component registers thereof as the second to nth feedback signals, respectively; and a second decision circuit that decides whether or not the result of the addition by the first weighting addition circuit is at least a defined threshold value and that outputs the decision as the first feedback signal, the second decision circuit operating in synchronism with the clock signal.