Patent ID: 7360059
Filing Date: 2008-04-15
Classification: G06F

Abstract:
1. A method of aligning instructions in a processor comprising: storing a plurality of instructions of different widths in a plurality of buffers, each buffer including a plurality of sub-buffers, each sub-buffer storing a unit instruction width, with an instruction of greater than a unit instruction width stored in more than one sub-buffer; aligning a first instruction from the buffers; decoding a width of the first instruction; selecting at least one of the plurality of sub-buffers from which to output the first instruction; determining a beginning of a second instruction from selected ones of the plurality of sub-buffers based on the width of the first instruction, decoding the width of the second instruction, and determining whether processing of the second instruction will deplete at least one of the plurality of buffers based on determining whether the second instruction occupies sub-buffers that include a transition between two of the buffers; and based on determining whether processing of the second instruction will deplete at least one of said plurality of buffers, receiving additional instructions in the plurality of buffers.