Patent ID: 7882294
Filing Date: 2011-02-01
Classification: G06F

Abstract:
1. A system comprising: an on-chip bus, having a plurality of bus topologies, including a register operating on a four clock-cycle minimum arbitration turn-around time to provide top-level register-to-register communication; a plurality of on-chip devices configured to individually communicate via one of said bus topologies so each of said on-chip devices has register-to-register communication with other of said on-chip devices and can communicate with a root collector device, included in an other said bus topology, that is configured to communicate, via a bus topology that is separate from the on-chip bus, with an off-chip device; an off-chip bus configured to transfer data packets, received by the root collector device from one of said on-chip devices via the one and the other said bus topologies, to an off-chip device via the bus topology that is separate from the on-chip bus, wherein the off-chip bus is configured to use a protocol that is different from a protocol implemented by the on-chip bus; an arbiter granting individual on-chip devices non-conflicting on-chip bus access by granting a unique set of accessing time slots; and a forecast cycle configured to identify packets that are less than four clock-cycles to the arbiter, in which a bus request signal and a bus grant signal individually provide a top-level register-to-register communication for said on-chip devices.