Patent ID: 6445046
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A memory cell arrangement in which a number of memory cell lines are arranged in a semiconductor substrate, neighboring memory cell lines being insulated from one another, the memory cell lines comprising:a first doped region corresponding to a source/drain region arranged at a first end of each of the memory cell lines; a second doped region corresponding to a source/drain region arranged at a second end of each of the memory cell lines; a gate dielectric arranged between each of the first and second doped regions on a principle surface of the semiconductor substrate, the gate dielectric containing a material having charge carrier traps; and a plurality of gate electrodes arranged next to one another and on the principle surface of the semiconductor substrate between the first and second doped regions, wherein, a spacing between neighboring gate electrodes is less than the dimensions of the neighboring gate electrodes in a direction parallel to the connecting memory cell lines between the first and second doped regions.