Patent ID: 8990641
Filing Date: 2015-03-24
Classification: G06F

Abstract:
1. A memory subsystem of a data processing system, comprising: an error detection circuit; and control logic coupled to system memory, wherein the control logic selects, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing by the error detection circuit on a target memory block of a memory access request, wherein the control logic, responsive to receipt of the memory access request and selection of the first timing, causes the memory subsystem to transmit data from the target memory block to a requestor prior to completion of error detection processing on the target memory block by the error detection circuit, and wherein the control logic, responsive to receipt of the memory access request and selection of the second timing, causes the memory subsystem to transmit data from the target memory block to the requestor after and in response to completion of error detection processing on the target memory block by the error detection circuit.