Patent ID: 6011409
Filing Date: 2000-01-04
Classification: H03K

Abstract:
An I/O buffer for an IC device driven by a system voltage whose magnitude lies between a high-voltage logic state and a low-voltage logic state that are received via an I/O port, the I/O buffer comprising:a floating N-well;a first NMOS transistor whose gate is connected to receive a first gate control signal whose source is connected to the ground and whose drain is connected to a first node;a second NMOS transistor whose gate is connected to the system voltage; whose source is connected to the first node; and whose drain is connected to a second node connected to the I/O port;a third NMOS transistor whose gate is connected to a first I/O control signal; whose source is connected to the ground; and whose drain is connected to a third node;a fourth NMOS transistor whose gate is connected to the system voltage; whose source is connected to the third node; and whose drain is connected to a fourth node;a fifth NMOS transistor whose gate is connected to a second I/O control signal whose value is the complement of the first I/O control signal connected to the gate of the third NMOS transistor; whose source is connected to the first node; and whose drain is connected to the fourth node;a first PMOS transistor whose gate is connected to the system voltage; whose source is connected to the I/O port; and whose drain is connected to the floating N-well;a second PMOS transistor whose gate is connected to the fourth node; whose source is connected to the system voltage; and whose drain is connected to the floating N-well;a third PMOS transistor whose gate is connected to the system voltage; whose source is connected to the I/O port; and whose drain is connected to a fifth node;a fourth PMOS transistor whose gate is connected to the system voltage; whose source is connected to the I/O port; and whose drain is connected to the fourth node;a fifth PMOS transistor whose gate is connected the fifth node; whose source is connected to the system voltage; and whose drain is connected to the second node connected to the I/O port; anda transmission gate including a sixth NMOS transistor and a sixth PMOS transistor which are connected in such a manner that the gate of the sixth NMOS transistor is connected to the system voltage and the gate of the sixth PMOS transistor is connected to the fourth node, in which the two source/drain ends of the sixth NMOS transistor are respectively connected to the two source/drain ends of the sixth PMOS transistor, with one end connected to receive a second gate control signal and the other end connected to the fifth node;wherein the floating N-well is connected to the substrate on which all the PMOS transistors are formed;wherein when the I/O buffer operates in input mode, the first I/O control signal is switched to a low-voltage logic state, the first gate control signal is switched to a low-voltage logic state, and the second gate control signal is switched to a high-voltage logic state; andwherein when the I/O buffer operates in output mode, the first I/O control signal is switched to a high-voltage logic state.