Patent ID: 7449923
Filing Date: 2008-11-11
Classification: G11C

Abstract:
1. A double sampled multiple-input amplifier circuit comprising: a first differential transistor pair for a first sampled differential input; a second differential transistor pair for a second sampled differential input, said first sampled differential input and said second sampled differential input being sampled at different times; a first tail current bias arrangement coupled to said first differential transistor pair and configured to conduct a first tail current for said differential transistor pair, said first tail current bias arrangement comprising a first bias transistor having a drain, a gate, and a source, and a third bias transistor having a drain, a gate, and a source, said first bias transistor and said third bias transistor being coupled in parallel between the first differential transistor pair and a first common node such that said drain of said first bias transistor and said drain of said third bias transistor are both coupled to a common source node of said first differential transistor pair, and such that said source of said first bias transistor and said source of said third bias transistor are both coupled to said first common node; a second tail current bias arrangement coupled to said second differential transistor pair and configured to conduct a second tail current for said second differential transistor pair; said second tail current bias arrangement comprising a second bias transistor having a drain, a gate, and a source, and a fourth bias transistor having a drain, a gate, and a source, said second bias transistor and said fourth bias transistor being coupled in parallel between the second differential transistor pair and a second common node such that said drain of said second bias transistor and said drain of said fourth bias transistor are both coupled to a common source node of said second differential transistor pair, and such that said source of the second bias transistor and said source of said fourth bias transistor are both coupled to said second common node; and a bias switching architecture coupled to said first tail current bias arrangement and to said second tail current bias arrangement, said bias switching architecture being configured to alternately activate said first tail current bias arrangement and said second tail current bias arrangement using a first bias control signal for said first tail current bias arrangement, a second bias control signal for said second tail current bias arrangement, and a common bias control signal for said first tail current bias arrangement and said second tail current bias arrangement, where said first bias control signal, said second bias control signal, and said common bias control signal are different and distinct signals, and wherein said gate of said third bias transistor receives said first bias control signal, said gate of said fourth bias transistor receives said second bias control signal, said gate of said first bias transistor receives said common bias control signal, and said gate of said second bias transistor receives said common bias control signal.