Patent ID: 6041422
Filing Date: 2000-03-21
Classification: G11C

Abstract:
A semiconductor memory device including at least one memory cell array chip, coupled to an off-chip application specific integrated circuit device (ASIC) (2), said ASIC including a redundancy configuration comprising a redundancy memory cell array (17), a defective memory address storing circuit (3), an address comparing circuit and a redundancy memory cell selecting circuit (21,22,14), said ASIC further including associative storage means (15) having a plurality of storage elements each of which is coupled to a corresponding element in said redundancy memory cell array (17) and control means (16) for enabling or disabling said corresponding element according to whether an associated element in said at least one memory cell array chip is accessed or not, wherein:said redundant memory cell array (17) comprises a plurality of substitute storage locations (25) mapped to corresponding defective locations in said at least one memory cell array chip, and said address comparing circuit comprises a plurality of comparators (21) each of which is arranged to compare a received address signal with a corresponding one of the addresses of the defective locations and which is coupled via a corresponding dedicated line to a corresponding one of the substitute storage locations (25) for enabling a read and/or write access to that substitute location and for disabling said at least one memory cell array chip if the compared addresses match; andeach of the storage elements of the associative storage means comprises a register means (20) for storing as a binary word the address of one of a plurality of defective locations in said at least one memory cell array chip and wherein each of the comparators is arranged individually to compare each of the bits stored in the register means with corresponding bits of the received address and to combine the results of the individual comparisons to provide a comparison result.