Patent ID: 8677122
Filing Date: 2014-03-18
Classification: G06F

Abstract:
1. A secure processing apparatus comprising: a hardware processor, the hardware processor including a non-secure data entity and a secure data entity, the non-secure data entity providing non-secure executable instructions; a communication monitor that works in cooperation with the hardware processor to detect communication between the secure data entity and the non-secure data entity, the communication monitor including secure executable instructions; a first prohibitor that works in cooperation with the hardware processor to prohibit execution of the non-secure executable instructions on the secure data entity unless the non-secure executable instructions are recorded in a permitted instruction record; a second prohibitor that works in cooperation with the hardware processor to prohibit execution of the non-secure executable instructions on the secure data entity if the non-secure executable instructions are recorded in a prohibited instruction record; and a loader that works in cooperation with the hardware processor to instantiate the communication monitor, the permitted instruction record, the first prohibitor, the prohibited instruction record, and the second prohibitor on the hardware processor from the secure executable instructions, and to instantiate the non-secure data entity from the non-secure executable instructions.