Patent ID: 7644247
Filing Date: 2010-01-05
Classification: G06F

Abstract:
1. A system controller to exchange data with a host system and to exchange data with a memory controller that accesses flash memory, the system controller comprising: an interpreting unit interpreting first operation instruction data supplied from the host system; a first instruction data supplying unit generating second operation instruction data based on a result of interpretation by the interpreting unit, the second operation instruction data instructing the memory controller to execute an operation, the first instruction data supplying unit transmitting the second operation instruction data to the memory controller; a second instruction data supplying unit transferring the first operation instruction data provided from the host system to the memory controller; and a controlling unit selectively operating the first instruction data supplying unit and the second instruction data supplying unit, wherein if the interpreting unit interprets the first operation instruction data as data instructing to begin an operation with the second instruction data supplying unit, the controlling unit shifts to a first mode that halts the first instruction data supplying unit and that begins an operation with the second instruction data supplying unit, and if the interpreting unit interprets the first operation instruction data as data instructing to halt the second instruction data supplying unit, the controlling unit shifts to a second mode that halts the second instruction data supplying unit and that begins an operation with the first instruction data supplying unit.