Patent ID: 7045468
Filing Date: 2006-05-16
Classification: H01L

Abstract:
1. A method of forming an isolated junction field effect transistor comprising: a) depositing a layer of trench masking material on a surface of a semiconductor substrate; b) patterning the layer of trench masking material to expose portions of the semiconductor substrate; c) etching the semiconductor substrate to form at least a first trench and a second trench, wherein each of the first and second trenches has a bottom surface and a side surface; d) depositing a conformal layer of spacer material; e) forming spacers adjacent to the side surfaces of the first trench and the second trench by anisotropically etching the spacer material until the semiconductor substrate at the bottom surface of each of the first and second trenches is exposed; f) integrally forming a T-shaped pedestal in the semiconductor substrate by isotropically etching the exposed semiconductor substrate to form a first undercut region subjacent to the first trench and a second undercut region subjacent to the second trench, wherein a top portion of the T-shaped pedestal is disposed between the first trench and the second trench and a stem portion of the T-shaped pedestal is disposed between the first undercut region and the second undercut region; g) filling each of the first and second trenches with at least one dielectric material; h) forming a gate insulator layer; i) forming a gate electrode over the gate insulator layer; and j) implanting impurities to form a source and a drain region.