Patent ID: 6624475
Filing Date: 2003-09-23
Classification: H01L

Abstract:
An FET device comprising:a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET source and drain regions of a second conductivity type formed in the substrate layer, the FET source and drain regions each having edges, the edges of the FET source and drain regions being separated by the channel region whereby the channel region is entirely and directly between said FET source and drain regions; a body contact region of the first conductivity type, the first conductivity type material in said body contact region being thinner than the first conductivity type material in the channel region; and a second dielectric layer formed on the body contact region; wherein the body contact region of the first conductivity type directly abuts only the FET source and drain regions of the second conductivity type and the channel region of the first conductivity type along a first common border so that the first conductivity type of both the channel region and the body contact region is continuous along a portion of the first common border, said channel region extending partially beneath the source, drain and channel regions along the first common border.