Patent ID: 9223656
Filing Date: 2015-12-29
Classification: G06F,G11C

Abstract:
1. An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory, the method comprising: receiving a read request directed to a target memory cell of the NAND flash memory; performing a normal read operation directed to the target memory cell in response to the read request; and then, determining that a read fail has occurred as a result of the normal read operation; and then in response to the read fail, performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell; and then, storing pass information associated with the pass read retry iteration in the NVRAM, wherein the method further comprises: further in response to the read fail and before performing the read retry operation by iterations directed to the target memory cell, reading pass information related to the read request previously stored in the NVRAM, wherein the first read retry scheme is defined at least in part by the pass information read from the NVRAM; determining whether a number of program/erase (P/E) cycles for the target memory cell has reached a reference value; and upon determining that the number of P/E cycles for the target memory cell has not reached the reference value, performing the read retry operation by iterations directed to the target memory cell according to a second read retry scheme different from the first read retry scheme until a pass read retry iteration successfully reads the target memory cell, instead of reading the pass information related to the read request previously stored from the NVRAM and performing the read retry operation by iterations directed to the target memory cell according to the first read retry scheme until the pass read retry iteration successfully reads the target memory cell.