Patent ID: 7821305
Filing Date: 2010-10-26
Classification: H03K

Abstract:
1. A voltage buffer comprising: a current source coupled between a first voltage source and a first output node; first, second, and third transistors coupled in series between the first output node and a second voltage source, wherein a second output node is located between the second and third transistors, and wherein a mid-range node is between the first and second transistors; and first, second, and third amplifiers driving gates of the first, second, and third transistors, respectively, the first amplifier having a first input terminal for receiving a first input voltage and a second input terminal for receiving a first related voltage, the first related voltage being a function of at least a first defined voltage, the second amplifier having a first input terminal for receiving a second input voltage and a second input terminal for receiving a second related voltage, the second related voltage being a function of at least a second defined voltage, and the third amplifier having a first input terminal coupled to the mid-range node and a second input terminal for receiving a third input voltage.