Patent ID: 7289516
Filing Date: 2007-10-30
Classification: H04L

Abstract:
1. An interface apparatus comprising: a processor for receiving at least one network interface signal, and for recognizing a transport mechanism associated with each network interface signal; a bus interface device for generating at least one system interface signal in response to the recognized transport mechanism; wherein: the transport mechanism comprises at least one of Asynchronous Transfer Mode, Internet Protocol, Frame Relay, Integrated Services Digital Network, High bit-rate Digital Subscriber Line, Asymmetric Digital Subscriber Line, Very High Data Rate Digital Subscriber Line, Symmetric Digital Subscriber Line, 10 base T, 100 base T, Gigabit Ethernet and E1/T1; the processor further examines a pattern for each network interface signal to recognize the associated transport mechanism; each system interface signal is coupled with at least one of a circuit switched interface, a packet switched interface, and a combined circuit packet switched interface; the transport mechanism comprises an adaptation layer of Asynchronous Transfer Mode, the processor performs ATM adaptation layer processing on each Network Interface signal in response to the recognized transport mechanism; and at least one of the processor and the bus interface device matches a timing of the circuit switched interface and formats the ATM adaptation layer processed network interface signal to the corresponding system interface signal.