Patent ID: 6047350
Filing Date: 2000-04-04
Classification: G06F,H04N

Abstract:
A computer system which intelligently byte slices different data byte channels of a bus, comprising:a CPU;main memory coupled to the CPU which stores data accessible by the CPU;bridge logic coupled to the CPU and to the main memory, wherein the bridge logic includes a memory controller coupled to the main memory and also includes expansion bus interface logic;an expansion bus coupled to the bridge logic;a multimedia bus coupled to the bridge logic, wherein said multimedia bus includes a plurality of data byte channels for transmitting data;a plurality of multimedia devices coupled to said multimedia bus, wherein each of said multimedia devices perform operations on said multimedia bus, wherein each of said multimedia devices includes multimedia bus interface logic for accessing said multimedia bus and performing data transfers on said multimedia bus, wherein each of said multimedia devices includes byte slicing logic which couples to the multimedia bus, wherein the byte slicing logic for each device operates to selectively assign data streams on selected ones of said data byte channels comprising the multimedia bus;wherein each byte slicing logic comprises a memory for storing data stream bandwidth, data stream source, and data stream destination information for each of said multimedia devices;wherein each byte slicing logic operates to selectively and dynamically assign data streams on selected ones of said data byte channels comprising the multimedia bus using said data stream bandwidth, data stream source, and data stream destination information for said each of said multimedia devices.