Patent ID: 6294810
Filing Date: 2001-09-25
Classification: G11C,H01L

Abstract:
An EEPROM cell, comprising:a semiconductor substrate, said semiconductor substrate having a first conductivity type;a tunneling transistor formed in said semiconductor substrate, said tunneling transistor having a tunneling source, a tunneling drain and a tunneling channel between said tunneling source and said tunneling drain, said tunneling drain and said tunneling source having a second conductivity type that is opposite said first conductivity type;a tunnel oxide layer overlying said tunneling channel, said tunneling source and said tunneling drain;a program junction region formed in said semiconductor substrate, said program junction region separated from said tunneling transistor by a first oxide, said program junction region having said second conductivity type;a program junction oxide layer overlying said program junction region;a sense transistor formed in said semiconductor substrate and separated from said program junction region by a second oxide, said sense transistor having a sense source, a sense drain and a sense channel between said sense source and said sense drain, said sense source and said sense drain having said second conductivity type;a sense tunnel oxide layer overlying said sense channel, said sense source and said sense drain;a read transistor formed in said semiconductor substrate, said read transistor having a read source and a read drain, said read transistor electrically coupled to said sense transistor through said sense drain; anda floating gate overlying said tunnel oxide layer, said program junction oxide layer and said sense tunnel oxide layer, wherein electron tunneling through said tunnel oxide layer overlying an edge of said tunneling drain occurs upon incurrence of a sufficient voltage potential between said floating gate and said tunneling drain, and wherein electron tunneling through said sense tunnel oxide layer overlying said sense channel occurs upon incurrence of a sufficient voltage potential between said floating gate and said sense channel.