Patent ID: 6216225
Filing Date: 2001-04-10
Classification: G06F

Abstract:
An apparatus controlling a memory unit of a computer system, the apparatus comprising:a memory unit storing first predetermined instructions to be executed when said computer system is powered on;a random access memory temporarily storing data;a control unit generating a control signal selected from among a first signal and a second signal, said control signal controlling an enable signal of said memory unit; anda control buffer unit having an input port receiving said enable signal and an output port connected to an enable port of said memory unit, said output port outputting to said memory unit said enable signal not modified when said control signal corresponds to said first signal thereby allowing said first predetermined instructions stored in said memory unit to be revised, and said output port outputting to said memory unit said enable signal modified when said control signal corresponds to said second signal thereby not allowing said first predetermined instructions stored in said memory unit to be revised;when said control signal corresponds to said first signal, second predetermined instructions being recorded in said random access memory and then said first predetermined instructions being deleted from said memory unit and then said second predetermined instructions being copied from said random access memory to said memory unit;when said second predetermined instructions are copied from said random access memory to said memory unit, said control unit generating said control signal corresponding to said second signal to not allow said second predetermined instructions stored in said memory unit to be revised, said second signal being generated after said second predetermined instructions are copied from said random access memory to said memory unit and before said computer system is powered off.