Patent ID: 7132698
Filing Date: 2006-11-07
Classification: H01L

Abstract:
1. A compression assembled semiconductor package comprising: a semiconductor die having a first major surface and a second major surface; first and second electrodes disposed on said first and said second major surfaces, respectively; an insulation ring having an interior wall annularly disposed around and radially spaced from said semiconductor die, said interior wall having at least a first groove in a first end portion of said insulation ring, and said interior wall having a second groove in a second end portion of said insulation ring; a first conductive pole having a body portion which is in surface-to-surface electrical contact with said first electrode and a first pole flange extending radially from said first pole, said first pole flange having a first extending projection; a second conductive pole having a body portion which is in surface-to-surface electrical contact with said second electrode, and a second pole flange extending radially from said second pole, said second pole flange having a second extending projection; a first rib extending from said first pole flange and a second rib extending from said second pole flange; and wherein each of said first extending projection and said second extending projection comprises a squared tab and a semi-circular distal end, wherein said first extending projection is forced into said first groove, and said second extending projection is forced into said second groove; and said semiconductor die being held in place between said first pole and said second pole only as a function of compressing said first and second extending projections into said first and second grooves.