Patent ID: 8969940
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A semiconductor fabrication process comprising: forming a first select gate structure and one or more sacrificial structures over the semiconductor substrate, where the one or more sacrificial structures are spaced apart from the first select gate structure on a first side to form a control gate opening, and where the one or more sacrificial structures are positioned in relation to the first select gate structure to define a control gate contact opening; forming a charge storage layer on at least a top and sidewall surface of the first select gate structure and on a bottom surface of the control gate opening; and simultaneously forming an inlaid control gate in the control gate opening and an inlaid control gate contact layer in the control gate contact opening as a continuous conductive layer by forming a planarized conductive layer on the charge storage layer to fill the control gate opening and control gate contact opening.