Patent ID: 8044513
Filing Date: 2011-10-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including a first transistor region, a second transistor region, and a memory cell region; a first gate insulating film and a second gate insulating film, the first gate insulating film being provided in the first transistor region on the semiconductor substrate, the second gate insulating film being provided in the second transistor region on the semiconductor substrate and being smaller in thickness than the first gate insulating film; a plurality of first metal oxide semiconductor (MOS) transistors formed on the first gate insulating film and each of the first MOS transistors including a first gate electrode; a plurality of second MOS transistors formed on the second gate insulating film and each of the second MOS transistors including a second gate electrode; a plurality of memory cell transistors arranged in the memory cell region; a first element isolation region in the first transistor region, the first element isolation region being provided between the plurality of first MOS transistors; a second element isolation region in the second transistor region, the second element isolation region being provided between the plurality of second MOS transistors; and a third element isolation region provided in the memory cell region, wherein the upper surface of the second element isolation region is lower than the upper surface of the first element isolation region, and the upper surface and lower surface of the second element isolation region are equal in height to the upper surface and lower surface of the third element isolation region.