Patent ID: 6157977
Filing Date: 2000-12-05
Classification: G06F

Abstract:
A bus bridge for ordering write operations mastered from a first bus and destined to a second bus relative to read operations mastered from the second bus and destined for completion on the second bus by way of a coherent cache in said bus bridge, said bus bridge comprising:first means for queueing the write operations from the first bus;second means for counting a number of write operations received in said first means for queueing;third means for counting a number of write operations completed on the second bus;fourth means for measuring an age of data held in a cache line in the coherent cache in units of write operations received in said first means for queueing since said data in said cache line was fetched; andfifth means for delaying completion of said read operations when said age of said data to be read from the coherent cache is less than a difference between said number of write operations received in said first means for queueing and said number of write operations completed on the second bus.