Patent ID: 6144617
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A synchronous semiconductor storage device which accesses a memory cell array consisting of rows and columns with respect to row addresses and column addresses, being sequentially supplied in a time-division manner, in synchronization with cycles of a clock signal being supplied from an external, said synchronous semiconductor storage device comprising:first signal creation means for producing a first control signal consisting of pulses, which are produced in synchronization with the cycles of the clock signal after a lapse of a predetermined delay time, which elapses from a timing to apply an active command to activate a row of the memory cell array designated by an row address;second signal creation means for producing a second control signal consisting of pulses, which are produced in synchronization with the cycles of the clock signal after a timing to apply a read command or a write command to access the memory cell array; andthird signal creation means for producing a third control signal for determining a timing to designate a column address of the memory cell array, wherein the third control signal is produced based on one of the first control signal and the second control signal which is delayed.