Patent ID: 8786334
Filing Date: 2014-07-22
Classification: H03L

Abstract:
1. A phase-locked loop (PLL) circuit comprising: a comparator configured to compare phases of an input clock signal and an output clock signal to generate phase comparison signals; a pulse generator configured to generate a first pulse signal based on the phase comparison signals; a bias circuit configured to generate a first current and a second current proportional to the first current, wherein the first current is stabilized to a predetermined reference current level; a delay circuit configured to draw third and fourth currents proportional to the first and second currents, respectively, and configured to receive the first pulse signal to generate a second pulse signal by delaying the first pulse signal using the third and fourth currents; a charge pump configured to receive the phase comparison signals; a loop filter configured to receive an output from the charge pump; a voltage-controlled oscillator configured to receive an output from the loop filter; a frequency divider configured to receive an output from the voltage-controlled oscillator and to provide the output clock signal to the comparator; and a lock detector comprising the pulse generator and the delay circuit.