Patent ID: 7529865
Filing Date: 2009-05-05
Classification: G06F

Abstract:
1. A process for a controller, the controller having a host data output port and a MAC data output port, said controller coupled to a memory having a plurality of memory slots, each said memory slot having a descriptor status bit having at least one of the values FREE or USED, an associated descriptor memory, and an associated segment memory, said controller also having a first pointer pair host read ptr and MAC write ptr, and a second pointer pair host write ptr and MAC read ptr, the process comprising the steps: a first step of comparing said host_read_ptr and said MAC_write_ptr, and performing a second step while said host_read_ptr and said MAC_write_ptr are not equal; said second step of transferring data from a said memory slot addressed by said host read ptr to said host data output port, getting a next field from said associated second step descriptor memory, setting the value of the associated said second step descriptor status bit to FREE, updating said host read ptr with said next field, and repeating said first and said second steps; concurrent with said first and said second step, performing a third and fourth step: said third step of comparing said MAC read ptr and said host write ptr, and performing said fourth step while said MAC read ptr and said host write ptr are not equal; said fourth step of transferring data from a said memory slot addressed by said MAC read ptr to said MAC data output port, getting a next field from said associated fourth step descriptor memory, setting the value of the associated said fourth step descriptor status to FREE, updating said MAC read ptr with said next field, and repeating said third and said fourth steps.