Patent ID: 8402340
Filing Date: 2013-03-19
Classification: H03M,H04L

Abstract:
1. A parity-check code-decoder adapted for receiving through a channel at least (N) bits that are to be decoded, each of the (N) bits being encoded through parity-check coding, said parity-check-code decoder treating each of the bits as a bit node, and comprising: a verifying device for multiplying the (N) bit nodes by a parity-check-code matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator for generating a reliability index for each of the bit nodes in accordance with the channel; a reliability-updating device coupled to said verifying device and said reliability generator for using the bit nodes and the check nodes to exchange messages iteratively based on the reliability indices, and following each iteration, updating (N) exchange results corresponding to the (N) columns, respectively; and a recording controller coupled to said reliability-updating device, and including