Patent ID: 7713810
Filing Date: 2010-05-11
Classification: H01L

Abstract:
1. A method for fabricating a layer arrangement, comprising: (a) forming at least one first layer sequence, each of which is laterally delimited by a first side wall, at least as part of a logic region of a memory arrangement, on a first surface region of a substrate, and forming at least one second layer sequence, each of which is laterally delimited by a second side wall, at least as part of a memory cell region of the memory arrangement, on a second surface region of the substrate; (b) forming a first side wall layer having a first thickness and comprising a first electrically insulating material in at least one sub-region of the first and second side walls of the first and second layer sequences by means of thermal oxidation of the at least one sub-region of the first and second side walls of the first and second layer sequences, wherein the first side wall layer is formed by thermal oxidation such that a second side wall layer formed thereon has different physical properties than the first side wall layer; (c) forming the second side wall layer having a second thickness and comprising a second electrically insulating material on at least one sub-region of the first side wall layers of the first and second layer sequences; and (d) removing the second side wall layer completely from the at least one first layer sequence; and (e) forming doped regions of the substrate proximate to one of the first surface region or the second surface region.