Patent ID: 6740917
Filing Date: 2004-05-25
Classification: H01L

Abstract:
An integrated semiconductor memory, comprising:a semiconductor substrate having a surface and trenches together forming a common trench; bit lines; word lines; memory cells connected, in a first direction parallel to said surface of said semiconductor substrate, in rows to said word lines and connected, in a second direction parallel to said surface, in rows to said bit lines, said memory cells each having a selection transistor and defining memory cell pairs each having two of said memory cells, said selection transistors of said memory cell pairs being vertical transistors having respective ones of said word lines disposed in said common trench of said trenches; a respective two of said bit lines being disposed as line pairs; each of said line pairs having: a buried line running in said semiconductor substrate; and an upper line disposed above said buried line; and said upper line of a given line pair connected to one of said memory cells and a lower bit line of said given line pair being connected to another different one of said memory cells.