Patent ID: 6365966
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A stacked chip scale package, comprising:a substrate having a first surface and a second surface, wherein the first surface has a plurality of mounting pads positioned along lines close to the four edges of the substrate; a first chip having a pair of long sides and a pair of short sides, wherein the first chip includes a first active surface and a first backside, the first backside of the first chip is attached to the first surface of the substrate so that the mounting pads are located close to the edges of the first chip, and the first active surface includes a plurality of first bonding pads formed close to the pair of short sides; a second chip, wherein both the length and the width of the second chip are smaller than the dimension of the pair of short sides of the first chip, the second chip has a pair of sides having bonding pads nearby and a pair of sides free from bonding pads, the second chip also includes a second active surface and a second backside, the second backside of the chip is attached to the first active surface of the first chip such that the pair of sides having bonding pads nearby is parallel to the pair of long sides of the first chip, and the second active surface includes a plurality of second bonding pads formed close to the pair of sides having bonding pads nearby; a plurality of conductive wires electrically connecting the first bonding pads and corresponding mounting pads next to the pair of short sides and a plurality of conductive wires electrically connecting the second bonding pads and corresponding mounting pads next to the pair of long sides; and a molding compound enclosing the first chip on the first surface, the second chip, the mounting pads and the conductive wires.