Patent ID: 7443224
Filing Date: 2008-10-28
Classification: H01L

Abstract:
1. A multi-threshold MIS integrated circuit design method, comprising the steps of: disposing a first macro including an internal circuit and a virtual power supply line connected to the internal circuit, the internal circuit including a first MIS transistor cell having a first threshold voltage; disposing a leak-current-shielding MIS transistor cell along a side of a macro frame of the first macro, the leak-current-shielding MIS transistor cell having a second threshold voltage higher than the first threshold voltage, the leak-current-shielding MIS transistor cell having a gate line and having a longitudinal direction coincident with the gate line; and connecting one and another ends of a current path of the leak-current-shielding MIS transistor cell to a power supply line and the virtual power supply line, respectively, and connecting the gate line to a power control line.