Patent ID: 7606943
Filing Date: 2009-10-20
Classification: G06F,Y02D

Abstract:
1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising: a plurality of functional units for performing a digital operation; a plurality of data address generators coupled to the memory bus; a configurable data path configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between and among the plurality of data address generators and the plurality of functional units, the configurable data path including the configured or reconfigured interconnections for the data path configuration; and wherein the plurality of data address generators are coupled between the memory bus and the configurable data path, each of the plurality of data address generators is configurable in response to a second, different configuration information to generate and control memory addresses from which data is to be read from or written to the memory consistent with and for the data path configuration.