Patent ID: 6484224
Filing Date: 2002-11-19
Classification: G06F

Abstract:
A symmetric multiprocessor system comprising:a first processor and a second processor for executing a multi-threaded process on packets; a first inbound interface device associated with said first processor, said first inbound interface device receiving incoming packets and having a first input buffer accessible by said first processor, said first input buffer maintaining a queue of the packets received on said first inbound interface device; a first outbound interface device associated with said first processor, said first outbound interface device receiving packets output from said first processor and transmitting said packets therefrom; a first task queue accessible for reading by said first processor, said first task queue receiving packets output from at least said second processor, the packets in said first task queue being transmitted from said first outbound interface device; a second inbound interface device associated with said second processor, said second inbound interface device receiving incoming packets and having a second input buffer accessible for reading by said second processor, said second input buffer maintaining a queue of the packets received on said second inbound interface device; a second outbound interface device associated with said second processor, said second outbound interface receiving packets output from said second processor and transmitting said packets therefrom; and a second task queue accessible for reading by said second processor, said second task queue receiving packets output from at least said first processor. The packets in said second task queue being transmitted from said second outbound interface device.