Patent ID: 6442703
Filing Date: 2002-08-27
Classification: H03L,H04L

Abstract:
A clock regenerator comprising:an oscillating means for outputting a clock signal with a frequency in response to an inputted first or second comparison signal; a first generating means for comparing the frequency of an inputted reference signal with that of said clock signal, and generating said first comparison signal in response to a frequency difference between the frequency of said inputted reference signal and that of said clock signal; a second generating means for comparing the phase of a digital input data with that of said clock signal, and generating said second comparison signal in response to a phase difference between the phase of said digital input data and that of said clock signal; a first changeover means for selecting either said first comparison signal fed from said first generating means or said second comparison signal fed from said second generating means, and outputting a selected signal to said oscillating means; and a controlling means for investigating whether or not a frequency difference between the frequency of said reference signal and that of said clock signal falls within a predetermined range, and controlling said first changeover means, when said frequency difference is outside said predetermined range, such that said first comparison signal generated by said first generating means is selected, while controlling said first changeover means, when said frequency difference falls within said predetermined range, such that said second comparison signal generated by said second generating means is selected.