Patent ID: 6157580
Filing Date: 2000-12-05
Classification: G11C

Abstract:
A semiconductor memory device comprising:plural matrix memory cell banks, a reference cell bank device, a sense circuit, and a virtual ground selector, said matrix memory cell banks and said reference cell bank device having deputy bit lines comprising embedded diffused layers,each of said matrix memory cell banks comprising a set of memory cells for holding data voltages,said reference cell bank device comprising at least three reference cell banks that are connected to each other and that each comprises reference cells for holding reference voltages,said sense circuit being connected to said matrix memory cell banks and, through a main bit line, to a first one of said reference cell banks, for receiving data voltages that are read from said matrix memory cell banks and for receiving reference voltages that are read from said reference cell bank device, to compare the data voltages to the reference voltages,said virtual ground selector being connected through a virtual ground line to a second one of said reference cell banks,a third one of said reference cell banks being directly connected to both said first and second reference cell banks and not directly connected to either said main bit line or said virtual ground line.