Patent ID: 6708890
Filing Date: 2004-03-23
Classification: G06Q,G07F,G11C

Abstract:
A circuit configuration, comprising:at least one nonvolatile, electrically erasable and writable memory area; an addressing circuit associated with said at least one memory area; address lines connected between said at least one memory area and said addressing circuit; a programming voltage source; a programming line connected between said programming voltage source and said at least one memory area, said programming line also connected between said at least one flag memory and said programming voltage source; at least one nonvolatile, electrically writable and erasable flag memory respectively assigned to said at least one memory area; an address line connected between said at least one flag memory and said at least one memory area; a data authentication circuit; a data line connected between said data authentication circuit and said at least one memory area; and an authentication line connected between said at least one flag memory and said data authentication circuit; whereby upon an alteration in a content of said at least one memory area, a state of said flag memory assigned to said at least one memory area is changed and, after authentication of a programmed memory area content, said assigned flag memory is returned to a basic state.