Patent ID: 7836366
Filing Date: 2010-11-16
Classification: G01R

Abstract:
1. A method of detecting defects in a selected cell of an integrated circuit, comprising: determining one or more failing test patterns that produce an indication of one or more defects during testing of the integrated circuit; determining a set of one or more exercising conditions applied to the selected cell during a capture phase of the testing of the integrated circuit for each of the one or more failing test patterns; determining one or more observable passing test patterns that are capable of exciting a defect in the selected cell but that did not produce an indication of one or more defects during the testing; determining a set of one or more exercising conditions applied to the selected cell during the capture phase of the testing of the integrated circuit for each of the one or more observable passing test patterns; classifying the exercising conditions for the failing test patterns and the observable passing test pattern; and analyzing the classified exercising conditions for the failing test patterns and the observable passing test patterns to determine if there is a defect in the selected cell.