Patent ID: 7076706
Filing Date: 2006-07-11
Classification: G06F

Abstract:
1. A method for real time capture of the desired failing chip cell diagnostic information from high speed testing of a semiconductor chip, comprising the steps of: collecting data from scanning the circuits of said semiconductor chip having LSSD diagnostic registers on chip for a failing cell for desired handing of multiple failures on a failing chip for immediate scan-out off-chip at a level of assembly test after scan initialization of the LSSD diagnostic registers on the semiconductor chip, said level of assembly test being selected from any level of a group consisting of: an initial manufacturing wafer test, a module test, a system level test, regardless of the clocking methodology, and for the desired failing chip handling on chip of multiple bit failure detection: providing data collection of a first failing cell in said LSSD diagnostic registers, and then skipping the collection of data up to a programmed amount to skip up to a subsequent failing cell, and recording the failure of a next failing cell recognized after said subsequent failing cell in said LSSD diagnostic registers while making reuse of logic including existing address registers for providing data synchronous with fail determination circuits for data collection used for collection of data of said first failing cell, and then pinpointing an actual failure for said next failing cell using additional data collected by reuse of the logic for data collection used for collection of data of said first failing cell.