Patent ID: 6600186
Filing Date: 2003-07-29
Classification: G11C,H01L

Abstract:
An embedded DRAM cell within a DRAM array of an application specific integrated circuit on a semiconductor substrate comprising:a cell capacitor to retain digital data within said embedded DRAM cell as electrical charge having a first plate connected to a biasing power supply voltage source; and a pass transistor having a drain connected to a second plate of the cell capacitor, a source connected to bit line voltage generator, a gate connected to a word line generator, and a gate oxide that separates said gate from a channel region that separates said drain from said source, whereby said gate oxide has a thickness that is equal to a thickness of gate oxide in a logic core of said application specific integrated circuit; wherein a signal provided by the word line voltage generator has voltage levels equal to voltage levels of signals provided by peripheral circuits within said logic core; and wherein the thickness of the gate oxide is equal to the thickness of the gate oxide of the peripheral circuits within the logic core.