Patent ID: 6700819
Filing Date: 2004-03-02
Classification: G11C

Abstract:
A memory with a differential reading system of a type in which a reference voltage, generated by a reference current that varies with a biasing voltage of at least one first reference cell in a virgin state, as a voltage drop across a first load resistor traversed by said reference current is compared with a measuring voltage, generated by a measuring current that varies with the same selection and biasing voltage of a read memory cell, as a voltage drop across a second load resistor traversed by said measuring current, a resistance of said first load resistor being a fraction of a resistance of said second load resistor, wherein said memory comprises circuit means that come into operation above a predetermined reference voltage to modify one of said reference and measuring currents, with equivalent effect on said load resistors, and to rebalance said reference and measuring currents above said predetermined reference voltage.