Patent ID: 8994085
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. An integrated circuit comprising field effect transistors (FETs) at least some of which comprise a part of random access memory (RAM) and logic devices, comprising: an N+ type layer; a buffer layer arranged on and in contact with the N+ type layer; a P type region formed on and in contact with the buffer layer; an insulator layer overlying the N+ type layer; a silicon layer overlying the insulator layer; an embedded dynamic RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor; a first contact through the silicon layer and the insulator layer and electrically connecting to the N+ type layer; a first logic/static RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic/static RAM FET; and a second contact through the silicon layer and the insulator layer and electrically connecting to the P type region.