Patent ID: 7362624
Filing Date: 2008-04-22
Classification: G09G,G11C

Abstract:
1. A transistor level shifter circuit configured between a first power source and a second power source, the voltage level of the first power source being greater than the voltage level of the second power source, the level shifter circuit being used to amplify the voltage level of a first pair of complementary signals, the first pair of complementary signals comprising a clock signal and an inverse clock signal, the transistor level shifter circuit comprising: a transforming circuit for receiving the first pair of complementary signals and generating a second pair of complementary signals, the voltage level of the second pair of complementary signals being substantially between the voltage level of the first power source and the difference of the voltage level of the first pair of complementary signals and the voltage level of the first power source; a first amplifying circuit for amplifying the second pair of complementary signals and generating a first stage output signal, the voltage level of the first stage output signal being substantially between zero and the voltage level of the first power source; and a second amplifying circuit for amplifying the first stage output signal and generating an output signal, the voltage level of the output signal being substantially between the voltage level of the first power source and the voltage level of the second power source.