Patent ID: 6734071
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method of forming a transistor structure, comprising:forming a transistor gate over a substrate, the transistor gate comprising a sidewall which comprises electrically conductive material; forming an electrically insulative material along the electrically conductive material of the transistor gate sidewall; the electrically insulative material comprising at least two separate layers; a first of the at least two layers comprising AlpOq, wherein p and q are greater than 0 and less than 10; a second of the at least two layers consisting essentially of silicon and nitrogen, the first of the at least two layers being disposed between the transistor gate sidewall and the second of the at least two layers; anisotropically etching the electrically insulative material to form a spacer along the transistor gate sidewall; the anisotropically etching comprising etching both of the first and second of the at least two layers; depositing a dopant barrier layer over the spacer; forming a doped oxide layer over the barrier layer; and etching a contact opening through the doped oxide and through the barrier layer adjacent the spacer utilizing the spacer to align the contact opening, the etching exposing at least a portion of the spacer.