Patent ID: 6747890
Filing Date: 2004-06-08
Classification: G11C,H01L

Abstract:
A memory cell comprising:a first transistor provided with a gate, a source, and a drain respectively coupled to a read wordline of a memory array, a first node, and a read bitline of said memory array; a second transistor having a gate, a source, and a drain respectively coupled to a storage node, to a voltage source, and to said first node; a third transistor having a gate, a source, and a drain respectively coupled to a write wordline of said memory array, to said storage node, and to a write bitline of said memory array; and a capacitor having a first terminal connected to said storage node and a second terminal connected to a voltage source, wherein the coupling of the gate of said second transistor to said storage node, the coupling of the source of said third transistor to said storage node, and the coupling the first terminal of the capacitor to said storage node are implemented by a first conductive strap having a first layer metal contact (482) and a first metal layer (482M) arranged in a first row and a first column of said memory array; and wherein said write bitline is arranged over said first conductive strap (482) in said first column of said memory array with a second metal layer (430) coupled to the drain of said third transistor, staking a first level metal contact (432) and a second metal contact (434) in a second row and said first column of said memory array.