Patent ID: 7447071
Filing Date: 2008-11-04
Classification: G11C

Abstract:
1. A non-volatile memory array having a hierarchical column decoding configuration with two or more levels of column decoding, comprising: a substrate having a p-well region; a plurality of memory sub-arrays that are formed in said p-well region, each of said memory sub-arrays having at least one first-level column decoder for selecting one of said plurality of column output terminals; a last-level decoder that is formed outside of said p-well region and that receives column output signals from the first-level column decoders; wherein said last-level column decoders are formed as high-voltage MOS device outside of said p-well region; a first high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to bias the p-well region; and a plurality of high-voltage switches that are activated during a memory erase mode of operation to provide a high voltage to respective gate terminals of the selector transistors in the first-level column decoders.