Patent ID: 6781239
Filing Date: 2004-08-24
Classification: H01F,H01L

Abstract:
An integrated circuit comprising:a first die having: a substrate with an electrical circuit; an interconnect formed on the substrate and electrically connected to the electrical circuit; a passivation layer formed on the interconnect; a plurality of first bonding pads formed on the passivation layer, the first bonding pads being electrically connected to the interconnect; a plurality of second bonding pads formed on the passivation layer, the second bonding pads being electrically connected to the interconnect; a second die having: a micro-electromechanical structure having an inductance; a plurality of third bonding pads connected to the micro-electromechanical structure, a portion of a third bonding pad being substantially vertically aligned with a portion of a second bonding pad; and a plurality of connectors electrically connected to the second bonding pads and the third bonding pads.