Patent ID: 8199559
Filing Date: 2012-06-12
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell storing data; a bit line connected to the memory cell; a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, the sense amplifier receiving a signal voltage read out to the bit line in response to the data of the memory cell at a sense node connected to a gate of a transistor and amplifying a voltage at the sense node; a transfer control circuit including a transfer transistor controlling an electrical connection between the bit line and the sense node in response to a transfer control voltage inputted to a gate; and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage corresponding to data of high-level of the memory cell, wherein the third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.