Patent ID: 8283961
Filing Date: 2012-10-09
Classification: H03K,H03L

Abstract:
1. A delay locked loop circuit, comprising: serially-coupled delay line circuits, each delay line circuit having a first input node, a second input node and an output node, each delay line circuit configured to propagate a signal received on one of the first input node and the second input node to the output node in a time T; a shift register circuit coupled to the delay line circuits that is configured to select at least one of the serially coupled delay line circuits by enabling a selected one of the first and second input nodes of the delay line circuits; and a phase mixer circuit to provide at least one of a first mixed output signal or a second mixed output signal to the second input node of each delay line circuit of the serially coupled delay line circuits, the phase mixer circuit configured to provide a controllable internal propagation time.