Patent ID: 7395287
Filing Date: 2008-07-01
Classification: H03M

Abstract:
1. A device for performing numerical value conversion, optimizing in speed and size, of an N-bit digital input value in a first unit being an arbitrary unit to a second unit being a natural unit, the second unit expressed in a natural unit of physical measurement and being related to the first unit by a first equation, the N-bit digital input value being a digitized value of a first measurement parameter selected from among a plurality of measurement parameters, the device comprising: a memory having stored thereon a look-up table storing a plurality of coefficients for performing the numerical value conversion from the first unit to the second unit for each of the plurality of measurement parameters, the look-up table being indexed using a first parameter to provide a selected coefficient pair of slope and offset coefficients, the first parameter being indicative of the first measurement parameter; an arithmetic logic unit receiving the N-bit digital input value in the first unit and the selected coefficient pair of slope and offset coefficients from the look-up table, the arithmetic logic unit performing the numerical value conversion based on the first equation and using the N-bit digital input value and the selected coefficient pair to compute a digital output value in the second unit; and a saturation-limit circuit coupled to receive the digital output value in the second unit from the arithmetic logic unit and provide a predetermined final output value when the digital output value exceeds a predetermined minimum or maximum value, wherein the plurality of measurement parameters comprise temperature, voltage, bias current, and transmit power and receive power of an optical transceiver and the first parameter, being indicative of one of the measurement parameters, is selected to operate the device for supporting numerical value conversion of digital input values derived from multiple data sources; and wherein the N-bit digital input value comprises a digital input value with variable bit-lengths, the variable bit-lengths comprising a first bit length and a second bit length different than the first bit length, the arithmetic logic unit generating a final digital output value being expressed in Q bits, the Q bits of the final digital output value comprising the digital output value of the arithmetic logic unit having the first bit length and trailing zeros or the digital output value having the second bit length and trailing zeros.