Patent ID: 6472284
Filing Date: 2002-10-29
Classification: H01L,Y10S

Abstract:
A method for fabricating a MOS transistor, comprising the steps of:forming a gate electrode structure on a semiconductor substrate, the gate electrode structure including a pad oxide film over the substrate, an HLD film over the pad oxide film, the pad oxide film and the HLD oxide film having an opening and nitride wall spacers over side walls of the HLD film within the opening, a gate oxide film being within the opening, the opening being filled with a gate electrode material; etching the HLD film; etching the pad oxide film formed at a lower portion of the HLD film to a predetermined thickness; removing the nitride side wall spacer such that a thick pad oxide film is formed around the gate electrode and a thin pad oxide film is formed at a distance from the gate electrode; forming a LDD region by implanting impurity ions into the semiconductor substrate at both sides of the gate electrode; forming a side wall spacer at both sides of the gate electrode; and forming a source/drain by implanting impurity ions into the semiconductor substrate using the side wall spacer as a mask.