Patent ID: 8928094
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: a silicon substrate; a metal gate formed on a top surface of the substrate; an offset spacer adjacent and physically contacting the gate on the substrate; a dopant implanted in the substrate to form a dopant region having a first type of dopant, wherein the dopant region extends under a portion of the offset spacer on a first side of the gate and does not extend under the offset spacer on a second, opposite side of the gate; a second spacer adjacent the offset spacer on the substrate, wherein the dopant region physically contacts the second spacer and the offset spacer; first and second source/drain (S/D) regions formed in the substrate, such that the first and second S/D regions are asymmetric with respect to the gate, wherein the first and second S/D regions are raised S/D regions having a topmost surface that is above the top surface of the substrate, wherein the first S/D region interfaces with the dopant region, wherein the second S/D region includes an epitaxial semiconductor material that continuously extends from the topmost surface of the raised S/D region of the second S/D region to directly under the offset spacer on the second side of the gate; and another dopant region having a second type of dopant and extending within the silicon substrate from an edge of the dopant region to an edge of the second S/D region, wherein the second type of dopant is opposite the first type of dopant, wherein the another dopant region physically contacts the offset spacer on the second side of the gate and physically contacts the gate stack.