Patent ID: 6197181
Filing Date: 2001-03-06
Classification: H01L,H05K

Abstract:
A process for applying a metal to a microelectronic workpiece, the microelectronic workpiece including an exteriorly disposed surface having a plurality of micro-recessed structures that are defined by sidewalls, the microelectronic workpiece further including a barrier layer deposited on at least a portion of the exteriorly disposed surface of the microelectronic workpiece and on at least substantial portions of the walls of the plurality of micro-recessed structures, the process comprising the steps of:(a) forming an ultra-thin metal seed layer exterior to the barrier layer using a first deposition process, the seed layer having a thickness of less than or equal to about 500 Angstroms;(b) repairing the ultra-thin seed layer by depositing an additional metal using a second deposition process that is different from the first deposition process to provide a repaired seed layer that is suitable for subsequent electroplating, the repaired seed layer having a thickness at all points on sidewalls of substantially all micro-recessed structures distributed within the workpiece that is equal to or greater than about 10% of the nominal thickness of the enhanced seed layer over the exteriorly disposed surface of the workpiece;(c) electroplating a metal onto the repaired seed layer using a third deposition process using processing parameters that are different from processing parameters used in the second deposition process.