Patent ID: 8357967
Filing Date: 2013-01-22
Classification: H01L

Abstract:
1. A method of forming memory cells, comprising: forming a second semiconductor material over a first semiconductor material; patterning the second semiconductor material into a plurality of spaced-apart pedestals, and forming recesses extending into the first semiconductor material adjacent the pedestals; lining the recesses and sidewalls of the pedestals with one or more dielectric materials; forming a third semiconductor material within the lined recesses and along the lined sidewalls of the pedestals; the third semiconductor material being doped to a first conductivity type and forming floating bodies; implanting dopant into the pedestals to form diodes within the pedestals; the diodes having first regions doped to the first conductivity type, and having second regions doped to a second conductivity type that is opposite to the first conductivity type; and forming conductively-doped nodes within the first semiconductor material on opposing sides of the floating bodies from the second regions of the diodes; individual memory cells comprising a channel region extending along a floating body and between one of the nodes and one of the diode second regions.