Patent ID: 9082792
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A fabricating method of a complementary metal oxide semiconductor transistor, comprising: forming a first gate and a second gate on a substrate; forming a gate insulator on the substrate to cover the first gate and the second gate; forming a first channel layer and a mask layer on the gate insulator, wherein the mask layer is located on the first channel layer, and the first channel layer and the mask layer are located above the first gate; forming a second channel layer on the gate insulator, wherein the second channel layer is located above the second gate, wherein the method of forming the second channel layer comprises forming a second channel material layer on the mask layer, the first channel layer and the gate insulator, and patterning the second channel material layer to form the second channel layer; removing the mask layer, wherein the mask layer is removed at the time when the second channel material layer is patterned; and forming a first source, a first drain, a second source, and a second drain, wherein the first source and the first drain are in contact with the first channel layer, and the second source and the second drain are in contact with the second channel layer.