Patent ID: 7141872
Filing Date: 2006-11-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first substrate including an integrated circuit chip; first connection terminals, having a first spacing therebetween, electrically connected to terminals of the integrated circuit chip; and a first connection portion spaced from the first connection terminals at a second spacing greater than the first spacing and not electrically connected to any terminal of the integrated circuit chip; a second substrate stacked on the first substrate and including second connection terminals having the first spacing therebetween and a second connection portion spaced from the second connection terminals at the second spacing; a metal material portion provided between the first connection portion and the second connection portion, bonding the first connection portion to the second connection portion and not electrically connected to any terminal of the integrated circuit chip, the first connection portion being bonded to the second connection portion by thermo compression bonding; and the first connection terminals being electrically connected to the second connection terminals, the electrical connection between the first connection terminals and the second connection terminals not being provided by thermal compression bonding.