Patent ID: 7998876
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A method of producing a semiconductor element, comprising: a wiring portion layer forming step of forming a wiring portion layer on a substrate; an interlayer insulation layer forming step of forming an interlayer insulation layer over the substrate and the wiring portion layer, said interlayer insulation layer including a third insulation film, a second insulation film containing SiN, and a first insulation film formed of a phosphorus containing silicon oxide film laminated in this order from the substrate; a mask pattern forming step of forming a mask pattern on the first insulation film; a first insulation film etching step of removing a first contact hole forming area of the first insulation film through a wet etching process after the mask pattern is formed; a second insulation film etching step of removing a second contact hole forming area of the second insulation film through an etching process including at least an isotropic dry etching process after the first insulation film etching step; a third insulation film etching step of removing a third contact hole forming area of the third insulation film through an etching process after the second insulation film etching step; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.