Patent ID: 6711667
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A method of executing instructions in a microprocessor, comprising:translating a first plurality of instructions from a first instruction set into at least one instruction from a second instruction set, said first plurality of instructions defining an operation which is efficiently performed via execution in said second instruction set; executing a code sequence including said at least one instruction and a second plurality of instructions coded in said first instruction set in a first execution core and a second execution core within said microprocessor, said first execution core being configured to execute instructions from said first instruction set and said second execution core being configured to execute instructions from said second instruction set, wherein said first execution core thereby executes said second plurality of instructions and said second execution core thereby executes said at least one instruction; and storing said at least one instruction via a storage control unit within said microprocessor, such that said at least one instruction is executed in lieu of said first plurality of instructions upon execution of said code sequence.