Patent ID: 6363454
Filing Date: 2002-03-26
Classification: G06F

Abstract:
A memory device, comprising:an array of memory cells; a control register block for storing a plurality of control parameters; control register modification circuitry operably coupled to the control register block and configured to reset at least some of a number of control registers in the control register block, addressing circuitry operably coupled to the array; and memory operation circuity operably coupled to the control register block and to the array, said memory operation circuitry being configured to: initiate memory program operations on the array when a first group of the control parameters are present in the control register block and terminate the memory program operations when a second group of the control parameters are present in the control register block; initiate memory read operations on the array when a third group of the control parameters are present in the control register block and terminate that memory read operations when a fourth group of control parameters are present in the control register block; and initiate an erase operation on the array when a fifth group of control parameters are present in the control register block and terminate the erase operation when a sixth group of control parameters are present in the control register block.