Patent ID: 6240026
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A dynamic random access memory, comprising:an array of memory cells arranged in a plurality of rows and columns of memory cells, including a plurality of word lines with each row of memory cells being connected to a distinct word line and a plurality of bit lines with each column of memory cells being connected to a distinct bit line;a plurality of sense amplifiers, each sense amplifier being coupled to a pair of bit lines;address decode circuitry, having a plurality of inputs coupled to address inputs of the dynamic random access memory device and a plurality of outputs coupled to the word lines, for selecting a word line based upon the value of address inputs of the dynamic random access memory device;boost circuitry for selectively boosting a voltage on a word line selected by the address decode circuitry during at least a portion of a memory access operation;detection circuitry for activating the boost circuitry following the sense amplifiers driving the bit line pairs during a memory operation, the detecting circuitry being triggered to activate the boost circuitry based upon a voltage level of a first bit line of a bit line pair crossing a predetermined voltage level.