Patent ID: 9171618
Filing Date: 2015-10-27
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a first inverter comprising a first input terminal and a first output terminal; a second inverter comprising a second input terminal and a second output terminal, wherein the second input terminal of the second inverter is connected to the first output terminal of the first inverter, and the second output terminal of the second inverter is connected to the first input terminal of the first inverter; a first transistor, wherein a first end of the first transistor is connected to a first bit line and a second end of the first transistor is connected to the first input terminal of the first inverter; a first element group comprising a plurality of second transistors, wherein a first end of the first element group is connected to the first output terminal of the first inverter and a second end of the first element group is connected to a second bit line; and a second element group comprising a plurality of third transistors and a magnetoresistive element whose magnetic resistance is varied, wherein a first end of the second element group is connected to one of the first input terminal of the first inverter and the second input terminal of the second inverter, a second end of the second element group is connected to a ground line, and a given potential is applied to the second element group according to an operation, and wherein a sum of a resistance value of the magnetoresistive element and on-resistance values of the third transistors is smaller than an on-resistance value of the first element group, if the magnetoresistive element is in a small-resistance state, wherein the sum of the resistance value of the magnetoresistive element and the on-resistance values of the third transistors is larger than the on-resistance value of the first element group, if the magnetoresistive element is in a large-resistance state, and wherein no magnetoresistive element is connected to the other of the first input terminal of the first inverter and the second input terminal of the second inverter.