Patent ID: 7897463
Filing Date: 2011-03-01
Classification: H01L

Abstract:
1. A method of fabricating a transistor, the method comprising: forming spaced-apart first and second stacks of interleaved patterns on a substrate, each of the first and second stacks of interleaved patterns comprising at least two semiconductor patterns with at least one sacrificial pattern therebetween; forming respective first and second vertical semiconductor lavers conforming to respective opposing sidewalls of the at least two semiconductor patterns and the at least one sacrificial pattern of respective ones of the first and second stacks of interleaved patterns; forming respective first and second gate insulators on respective ones of the first and second vertical semiconductor layers; forming a conductive gate electrode region extending between the first and second gate insulators; removing the at least one sacrificial pattern from each of the first and second stacks of interleaved patterns to form gaps between the at least two semiconductor patterns of the stacks of interleaved patterns; and forming respective insulation regions in respective ones of the gaps.