Patent ID: 8623730
Filing Date: 2014-01-07
Classification: H01L

Abstract:
1. A method for fabricating a transistor comprising: forming a replacement gate stack on a semiconductor layer; forming a gate spacer on sidewalls of the replacement gate stack; forming a dielectric layer on the semiconductor layer and abutting the gate spacer; after forming the gate spacer and the dielectric layer, removing the dummy gate stack, the removing forming a cavity; after removing the dummy gate stack, forming a gate dielectric in the cavity; forming a work function metal layer in the cavity; after forming the gate dielectric and the work function metal layer, filling a remaining portion of the cavity with a gate conductor; performing a planarization so that an upper surface of the gate dielectric, an upper surface of the work function metal layer, and an upper surface of the gate conductor are all coplanar with an upper surface of the dielectric layer, after performing the planarization, etching one and only one of the gate conductor and the work function metal layer, the etching forming a recess; after etching one and only one of the gate conductor and the work function metal layer, forming an oxide film in the recess, an upper surface of the oxide film being co-planar with the upper surface of the dielectric layer; using the oxide film to selectively grow an oxide cap directly on the upper surface of the gate dielectric, the upper surface of the oxide film, and a portion of the upper surface of the dielectric layer; forming an interlayer dielectric; etching the interlayer dielectric and the dielectric layer to form at least one cavity for a source/drain contact, the etching forming a contact cavity; and forming a source/drain contact in the contact cavity, a portion of the source/drain contact being located directly on the oxide cap.