Patent ID: 8910094
Filing Date: 2014-12-09
Classification: G06F

Abstract:
1. A method, comprising: receiving a design layout file for an integrated circuit device in a computing apparatus, the design layout file specifying dimensions of a plurality of features; decomposing the design layout file to a plurality of colored layout files in the computing apparatus, each colored layout file representing a particular reticle in a multiple patterning process; retargeting each of the colored layout files separately in the computing apparatus to generate a plurality of retargeted colored layout files, wherein retargeting each of the colored layout files comprises increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features; combining the retargeted layout files in the computing apparatus to generate a combined layout file; cleaning the retargeted colored layout files by identifying selected dimension changes that violate design rules and removing the selected dimension changes; and retargeting features in the combined layout file in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features, wherein increasing said dimensions of said first plurality of features comprises applying a first bias table indexing dimension changes by design width and spacing to an adjacent feature.