Patent ID: 7242621
Filing Date: 2007-07-10
Classification: H01L

Abstract:
1. A method for programming a floating-gate transistor, the method comprising: applying electric potentials to a small gate and a large gate of a control gate, wherein the small gate and the large gate are arranged side by side and separated by an electrically insulating material, and to a substrate having a drain region and a source region, to respectively inject electric charges into the floating gate and extract electric charges from the floating gate; choosing the electric potentials such that the injection of electric charges into the floating gate is performed through a tunnel oxide layer separating a floating gate from the substrate and such that the extraction of electric charges trapped in the floating gate is performed through a gate oxide layer separating the small gate of the control gate and the large gate of the control gate from the floating gate, so that stress caused by an electrical erase-program is equitably borne by the tunnel oxide layer and the gate oxide layer; applying a negative electric potential to the large gate, to pull down the electric potential of the floating gate; applying a positive electric potential to the small gate; and applying a negative electric potential to the drain region and to the substrate, wherein electric charges are extracted from the floating gate via the gate oxide.