Patent ID: 6815812
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A packaged circuit, the improvement comprising:an integrated circuit having VDDcore contacts in first known positions and VSScore contacts in second known positions, a VDDcore mesh layer, the VDDcore mesh layer having traces, a VSScore mesh layer, the VSScore mesh layer having traces, and a redistribution layer adjacent the integrated circuit and overlying the VDDcore mesh layer and the VSScore mesh layer, the redistribution layer having; first contacts positioned in alignment with the first known positions to make electrical connections between the redistribution layer and the VDDcore contacts, second contacts positioned in alignment with the second known positions to make electrical connections between the redistribution layer and the VSScore contacts, first electrically conductive vias positioned in alignment with the first known positions to make electrical connections between the first contacts and the VDD core mesh layer without using a VDDcore bus that extends substantially across the redistribution layer and any other layer except the VDD core mesh layer, where the traces of the VDDcore mesh layer are positioned in alignment with the first known positions, and second electrically conductive vias positioned in alignment with the second known positions to make electrical connections between the second contacts and the VSScore mesh layer without using a VSScore bus that extends substantially across the redistribution layer and any other layer except the VSScore mesh layer, where the traces of the VSScore mesh layer are positioned in alignment with the second known positions.