Patent ID: 6643210
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a plurality of memory blocks, each memory block including: a plurality of nonvolatile memory cells arranged in a matrix form, each of the nonvolatile memory cells having a gate region, a source region and a drain region, the memory blocks being arranged in a column direction of the matrix form; word lines, each of which is commonly connected to the gate regions of the nonvolatile memory cells in a corresponding row of the matrix form; a source line commonly connected to the source regions of the nonvolatile memory cells of the corresponding memory block; sub bit lines, each of which is commonly connected to the drain regions of the nonvolatile memory cells in a corresponding column of the matrix form; and first switching elements for selecting the corresponding sub bit lines; main bit lines common to the memory blocks, the sub bit lines in each of the memory blocks being connected to the corresponding main bit lines via the corresponding first switching elements; and at least one second switching element for extracting charges accumulated in drain regions of the nonvolatile memory cells via the first switching elements and the main bit lines, wherein the main bit lines are grounded via the at least one second switching element.