Patent ID: 8433850
Filing Date: 2013-04-30
Classification: G06F,Y02D

Abstract:
1. A method for maintaining inclusion of a processor pipeline, the method comprising: updating a way storage field of a first micro-op cache line to indicate a first instruction-cache way storing a first instruction corresponding to one or more micro-ops, the one or more micro-ops generated by decoding the first instruction and stored in the first micro-op cache line; updating, responsive to a micro-op cache hit at the first micro-op cache line, an instruction-cache in-use indication bit associated with the first instruction-cache way storing the first instruction, said instruction-cache in-use indication bit to indicate that the first instruction stored in the first instruction-cache way is in use, the instruction-cache in-use indication bit being located based on the way storage field of the first micro-op cache line; in response to an eviction of the first instruction from the instruction-cache way, when the instruction-cache in-use indication bit indicates that the first instruction is in use: