Patent ID: 7180887
Filing Date: 2007-02-20
Classification: H04L

Abstract:
1. An interface for enabling communication between a primary and a secondary computing elements of a multiple element computer system, comprising: a multiple element computing system having a primary computing element and a secondary computing element; a configuration and status register (CSR) block having a common section and a port specific section for enabling the exchange of buffer descriptors between said primary and said secondary computing elements wherein said buffer descriptors contain information identifying underlying information packets to be processed on said computer system; wherein said buffer descriptors further comprise receive buffer descriptors sent from said secondary computing element to said primary computing element, and transmit buffer descriptors sent from said primary computing element to said secondary computing element; wherein said common section of said CSR block further comprises a queuing structure that said primary and said secondary computing elements use to receive and transmit said buffer descriptors; wherein said queuing structure further comprises a receive free pull queue wherein said secondary computing element can obtain an available receive buffer descriptor; a receive queue having a head and a tail pointer, wherein said secondary computing element can return receive buffer descriptors to said tail of said receive queue after filling said receive buffer descriptors with data, and wherein said primary computing element can remove filled receive buffer descriptors from said head of said receive queue; a receive free push queue wherein said primary computing element can return buffer descriptors after said primary computing element has finished processing said receive buffer descriptors; a transmit free pull queue wherein said primary computing element can obtain an available transmit buffer descriptor; a transmit queue having a head and a tail pointer, wherein said primary computing element can return transmit buffer descriptors to said tail of said transmit queue after filling said transmit buffer descriptors with data, and wherein said secondary computing element can remove filled transmit buffer descriptors from said head of said transmit queue; a transmit done push queue wherein said secondary computing element can return transmit buffer descriptors after said secondary computing element has finished processing transmit buffer descriptors; a transmit done pull queue wherein said primary computing element can retrieve transmit buffer descriptors; and a transmit free push queue wherein primary computing element can return transmit buffer descriptors.