Patent ID: 6146950
Filing Date: 2000-11-14
Classification: H01L

Abstract:
A method of manufacturing multiple metallic layered embedded read-only-memory (ROM), comprising:providing a substrate having a memory cell region and a peripheral circuit region thereon;forming a first gate and a first source/drain region in the memory cell region;forming a second gate and a second source/drain region in the peripheral circuit region;forming a first dielectric layer over the substrate;forming a first contact in the first dielectric layer in the periphery circuit region;forming a first patterned metallic layer that couple electrically with the first contact in the peripheral circuit region;forming a second dielectric layer over the substrate;removing a portion of the second dielectric layer in the memory cell region to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region;forming a via hole in the second dielectric layer in the peripheral circuit region and a second contact opening in the first dielectric layer in the memory cell region, wherein the via hole exposes the first patterned metallic layer;forming a metallic barrier layer over the substrate;coding by implanting ions into coded regions in the substrate;forming a second patterned metallic layer in the peripheral circuit region to cover the second dielectric layer and fill the via hole to electrically coupled with the first patterned metallic layer;forming a third patterned metallic layer in the memory cell region to fill the contact opening; andforming a passivation layer over the substrate.