Patent ID: 8284150
Filing Date: 2012-10-09
Classification: G09G,G11C

Abstract:
1. A shift register comprising a plurality of serially connected stages, wherein one of the stages is connected to an input line of a start pulse, the shift register being driven by first, second and third clock signals, respectively input to first, second and third input lines, wherein each of the stages comprises: a first transistor coupled between a first power source and an output node, the first transistor having a gate electrode coupled to a first node; a second transistor coupled between the output node and the third input line, the second transistor having a gate electrode coupled to a second node; a third transistor coupled between the first power source and the first node, the third transistor having a gate electrode coupled to an input terminal to which the start pulse or an output signal of a previous stage is input; a fourth transistor coupled between the first power source and the second node, the fourth transistor having a gate electrode coupled to the first node; a fifth transistor coupled between the first node and a second power source, the fifth transistor having a gate electrode coupled to the first input line; a first voltage stabilizer coupled to the first and second power sources, the first input line and the second node, wherein the first voltage stabilizer is configured to stabilize a voltage at the second node; a sixth transistor having one electrode coupled to the second node via the first voltage stabilizer, having another electrode coupled to the second power source, and having a gate electrode coupled to the input terminal; and a second voltage stabilizer coupled between the fourth transistor and the second node, the second voltage stabilizer being further coupled to the first and second power sources and the input terminal, wherein the second voltage stabilizer is configured to stabilize the voltage at the second node.