Patent ID: 8209639
Filing Date: 2012-06-26
Classification: G06F,Y02P

Abstract:
1. A computer-implemented method of matching a range pattern to a block of a layout of a material in a layer in an integrated circuit (IC) chip, the method comprising: at a processor, slicing the range pattern into a plurality of pattern slices oriented parallel to one another, wherein location of presence of the material within each pattern slice differs from an adjacent pattern slice, the range pattern corresponding to a model of a defect; slicing the block of the layout into a plurality of layout slices oriented parallel to one another, wherein location of presence of the material within each layout slice differs from an adjacent layout slice; comparing a plurality of values of a dimension of the layout slices obtained from slicing the block, to a plurality of ranges of a corresponding dimension of the pattern slices obtained from slicing the range pattern, the dimension of the layout slices being a width or a length; and marking in a memory the block of the layout as not matching the range pattern and alternatively marking a match to indicate presence of a defect in the block of the layout, depending on an outcome of said comparing indicating the value of the dimension of any layout slice as falling outside or alternatively within the range of the corresponding dimension of a corresponding pattern slice.