Patent ID: 7359265
Filing Date: 2008-04-15
Classification: G11C

Abstract:
1. A circuit to minimize duration of sensing data from a DRAM and to minimize duration of precharge of data lines during READ operation is comprising: a logical AND-gate having two inputs and one output, wherein a first input is a READ-command and a second input is the output of an inverter stage and the output of said AND-gate is the input of a data sensing tracking circuit and of a delay circuit; said data sensing tracking circuit issuing a signal when a READ-command is completed wherein this signal is a RESET input of a first Flip-flop circuit; said delay circuit wherein its output is a SET input of said Flip-Flop circuit; said first Flip-Flop circuit wherein its Q-output is a first input of an OR-gate and of a SET-input of a second Flip-Flop circuit; said second Flip-Flop circuit wherein its RESET input is a synchronization pulse and its Q-output is a second input of said OR-gate; said OR-gate wherein its third input is said synchronization pulse and its output is the input of said inverter stage; said inverter stage wherein its output is said second input of said AND-gate and a first input of a control circuit controlling a bit switch; and said control circuit controlling a bit switch wherein its second input is said READ-command and its output controls said bit switch wherein precharging of a data line of said RAM is performed during OFF time of said bit switch and sensing of data is performed during ON-time of said bit switch.