Patent ID: 6504775
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A bitline architecture for a ternary content addressable memory, comprising:a first bitline sense amplifier connected to first and second complementary bitlines arranged in an open bitline configuration; a second bitline sense amplifier connected to third and fourth complementary bitlines arranged in an open bitline configuration; ternary content addressable memory cells for storing two bits of data connected to the first and third bitlines; ternary content addressable memory cells for storing two bits of data connected to the second and fourth bitlines; a first bitline overwrite circuit for writing preset complementary logic potential levels onto the first and third bitlines; a second bitline overwrite circuit for writing preset complementary logic potential levels onto the second and fourth bitlines; a first precharge circuit for equalizing the first and third bitlines; and a second precharge circuit for equalizing the second and fourth bitlines.