Patent ID: 6897507
Filing Date: 2005-05-24
Classification: H01L,Y10S

Abstract:
1. A capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising: a semiconductor substrate having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over said at least one interconnect metal layer wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μm of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μm PECVD nitride is deposited and wherein said passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point; a first layer of conductive material deposited over said passivation layer and within said at least one opening in said passivation layer wherein said first layer of conductive material is connected to said at least one top level metal contact point and wherein said first layer of conductive material forms said bottom plate of said capacitor, a layer of dielectric deposited over the surface of said first layer of conductive material, forming said layer of dielectric interspersed between said top plate and said bottom plate; and a second layer of conductive material deposited over the surface of said layer of dielectric forming said top plate of said capacitor.