Patent ID: 8222080
Filing Date: 2012-07-17
Classification: H01L

Abstract:
1. A fabrication method of a package structure, comprising the steps of: providing a full-panel packaging substrate having top-bottom symmetry and two opposing outmost layers each formed thereon with a plurality of metal bumps and an insulating protective layer formed therein with a plurality of openings for exposing the metal bumps, respectively; splitting the full-panel packaging substrate having top-bottom symmetry, followed by cutting the full-panel packaging substrate into a plurality of packaging substrate blocks each comprising a plurality of packaging substrate units arranged in an m×n array, wherein m and n are integers greater than 1; mounting each of the packaging substrate blocks on a respective second carrier board; mounting a semiconductor chip on each of the packaging substrate units, the semiconductor chips each having an active surface provided thereon with a plurality of electrode pads electrically connected to the metal bumps, respectively, through a solder material; forming an encapsulating material on the insulating protective layer and the semiconductor chips, followed by filling the encapsulating material between the insulating protective layer and the semiconductor chips so as to encapsulate the solder material; removing the second carrier board; and cutting each of the packaging substrate blocks mounted thereon with the semiconductor chips so as to separate the packaging substrate units from each other.