Patent ID: 9219065
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A method of fabricating a circuit, the method comprising: providing a substrate; depositing a strain-inducing material comprising germanium over the substrate; depositing a strained material over the strain-inducing material, the strain-inducing material inducing strain in the strained material; integrating a pMOSFET on the substrate, the pMOSFET comprising a first strained channel in the strained material and a first source/drain in the strained material; and integrating an nMOSFET on the substrate, the nMOSFET comprising a second strained channel in the strained material and a second source/drain in the strained material, wherein the first source/drain is electrically coupled to the second source/drain, a first device width of the pMOSFET and a second device width of the nMOSFET being optimized for an operating parameter based on a ratio of the first device width to the second device width being a function of a ratio of an electron mobility of the strained material to a hole mobility of the strained material.