Patent ID: 9117495
Filing Date: 2015-08-25
Classification: G11C

Abstract:
1. A method of operating a cross point memory array comprising a plurality of word lines and a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of local bit lines, each electrically connected to a corresponding one of a plurality of global bit lines by respective corresponding one of a plurality of gain stage transistors, the plurality of gain stage transistors having parameters that vary with respect to at least one of process, voltage, and temperature, the method comprising: precharging a first selected local bit line of the plurality of local bit lines to a first voltage that varies with the transistor parameters of the corresponding gain stage transistor; and after precharging the first selected local bit line, applying a voltage to a selected word line of the cross point memory array to read a memory cell coupled between the selected local bit line and the selected word line.