Patent ID: 7759740
Filing Date: 2010-07-20
Classification: H01L

Abstract:
1. An integrated circuit comprising: one or more wells of a first conductivity type; one or more wells of a second conductivity type; a first plurality of transistors within said one or more wells of a first conductivity type; a second plurality of transistors within said one or more wells of a second conductivity type; a deep well of a second conductivity type disposed between said one or more wells of said first conductivity type and a substrate of said first conductivity type, wherein said deep well includes a plurality of substructures having a plurality of gaps between each of said one or more wells of said first conductivity type and said substrate of said first conductivity type, wherein said one or more wells of said first conductivity type are coupled to said substrate through said plurality of gaps, and wherein said substructures form a depletion region between said deep well and said substrate having a specified amount of decoupling capacitance for a principal operating potential coupled between said deep well and said substrate; and a separation well of said first conductivity type disposed within one or more of said gaps and coupling said one or more wells of said first conductivity type to said substrate.