Patent ID: 7370140
Filing Date: 2008-05-06
Classification: G06F,G11C,Y02D

Abstract:
1. An integrated circuit comprising: a row enable input for receiving a signal indicating that a row address is present at address inputs to the integrated circuit; a row address latch for storing a row address present at address inputs to the integrated circuit; an array of DRAM memory cells organized in rows and columns; a set of sense amplifiers for performing a DRAM row access by accessing the array of DRAM memory cells identified by the stored row address; a set of static registers separate from said set of sense amplifiers, wherein subsets of the static registers are associated with individual rows in said array; a column address input for receiving a signal, during a DRAM row access, indicating that a column address is present at address inputs to the integrated circuit; a column address latch for storing the column address during a DRAM row access in response to the column address input; a write enable input for receiving a signal, during a DRAM row access, indicating that data is present at data inputs to the integrated circuit; a data latch for storing data in response to the write enable input; and a write signal generator for generating an internal write signal, after completion of the DRAM row access, to store the data in the data latch to the array of DRAM memory cells in a location identified by the column address in the column address latch.