Patent ID: 7630585
Filing Date: 2009-12-08
Classification: G06F,H04N,Y10S

Abstract:
1. A computer system comprising: a processor having a set of basic program execution registers, a set of floating point data registers, and a set of single instruction multiple data (SIMD) registers; main memory having data stored therein to be accessed by the processor to implement a block matching algorithm of a video encoder, the main memory having stored therein a current pixel block from an image frame and a search area of another image frame; and a cache accessible by the processor, wherein the data causes the current block to be compared to a first pixel block of said search area, and then the current block is compared to a second pixel block of said search area, the second pixel block being the first pixel block shifted by a pixel, said shift causing a cache line split when loading the second pixel block from the cache into the set of SIMD registers, wherein two different types of processor instructions are used in the data for the block matching algorithm to load pixel blocks from the main memory into the set of SIMD registers, a first type of instruction being used when Loading pixel block data items that are aligned with a cache line boundary of the cache, and a second type of instruction being used when loading pixel block data items that are unaligned with the cache line boundary, the first type of instruction on causes data being loaded from the cache to the set of SIMD registers to be processed by a higher Latency function block than that used by the second type of instruction.