Patent ID: 6055172
Filing Date: 2000-04-25
Classification: G11C,H01L

Abstract:
A memory device comprising a semiconductor die, wherein the semiconductor die has two shorter sides and two longer sides and wherein the semiconductor die includes:a plurality of memory cells, wherein the plurality of memory cells includes at least 2.sup.24 single-bit memory cells;a plurality of row address decoders;a plurality of column address decoders;a plurality of sense amplifiers;a semiconductor interconnect layer interconnecting selected portions of the memory cells, the plurality of row address decoders, the plurality of column address decoders and the plurality of sense amplifiers; andno more than one single deposition layer of highly conductive interconnect material, wherein the single deposition layer forms a plurality of bonding pads on the shorter sides of the semiconductor die and serves to selectively interconnect the bonding pads and portions of the plurality of the memory cells, the plurality of row address decoders, the plurality of column address decoders, and the plurality of sense amplifiers.