Patent ID: 6479859
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A multi-self aligned split-gate flash memory cell comprising:a semiconductor substrate having shallow trench isolation (STI); a gate oxide layer over said substrate; a thin floating gate over said gate oxide layer, wherein said floating gate having a thickness between about 50 to 150 Ã¥ is vertically self-aligned to said STI; a thin sharp poly tip in said floating gate; a high temperature oxide (HTO) layer over said thin floating gate; a thick nitride layer over said HTO layer; an inter-poly oxide layer over said thick nitride layer; a spacer control gate over said inter-poly oxide wherein said spacer control gate is vertically self-aligned to said floating gate; a common source line self-aligned to said floating gate and said control gate; and a drain to complete said split-gate flash memory cell.