Patent ID: 6433581
Filing Date: 2002-08-13
Classification: H03K

Abstract:
A dynamic programmable logic array (DPLA) comprising:at least one logic plane; at least one configurable evaluate module within the at least one logic plane, the at least one configurable evaluate module including a first input, a control input, an input pass transistor coupled to the first control input, and an evaluate transistor coupled to the input pass transistor, wherein each of the input pass transistor and the evaluate transistor including a gate, source and drain, wherein the gate of the input pass transistor is coupled to the first control input, and the source of the input pass transistor is coupled to the first input, the drain of the input pass transistor is coupled to the gate of the evaluate transistor; and an evaluate disable transistor; the evaluate disable transistor, including a gate, source and drain, the gate is coupled to the first control input, the source is coupled to the gate of the evaluate transistor, the drain is coupled to the ground, and the control input enables one of the input pass transistor or the evaluate disable transistor at any given time.