Patent ID: 7675787
Filing Date: 2010-03-09
Classification: G11C

Abstract:
1. A method of programming a non-volatile memory cell in a memory array, the memory array includes a semiconductor substrate, a first source/drain, a second source/drain, a well region between the first source/drain and the second source/drain, a plurality of memory cells disposed on the semiconductor substrate between the first source/drain and the second source/drain, a plurality of wordlines associated with respective ones of the plurality of memory cells, a plurality of current control lines that are each disposed between adjacent pairs of the plurality of wordlines, each memory cell includes a first oxide layer above the well region, a charge storage layer above the first oxide layer and a second oxide layer above the charge storage layer, the method comprising: applying a positive wordline programming voltage to the wordline over the respective memory cell to be programmed; applying a reference voltage to the well region; applying a current control line programming voltage to a current control line closest to the memory cell to be programmed on the side nearest the second source/drain region; and applying a source/drain programming voltage to the first source/drain region and coupling the second source/drain region to the reference voltage, the source/drain programming voltage being sufficient to cause electron tunneling from the second source/drain region through the well region toward the charge storage layer to program a first bit.