Patent ID: 7915728
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A semiconductor assembly comprising: a first subassembly that includes a first heat sink with a first surface and an opposing second surface; solder material disposed on a portion of the first surface of said first heat sink; a power semiconductor die located on the first surface of the first heat sink and thermally coupled thereto by the solder material; a packaging patterned polymer layer disposed only on the first surface of the first heat sink surrounding a central portion of the first surface of the first heat sink that is away from a peripheral portion of the first surface of the first heat sink; a semiconductor package in which the first subassembly, the solder material and the power semiconductor die are located such that the central portion of the first surface of the first heat sink is exposed by the semiconductor package; a first patterned polymer layer of the packaging patterned polymer layer disposed on the peripheral portion of the first surface of the first heat sink and not covering the central portion of the first surface of the said first heat sink, said central portion of the first surface of the first heatsink extending radially inward from the first patterned polymer layer; and a second patterned polymer layer of the packaging patterned polymer layer disposed only on a radially outer portion of the first patterned polymer layer that is parallel to the first surface, said first and second patterned polymer layers defining a cell for accommodating the power semiconductor die.