Patent ID: 6107182
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising a semiconductor substrate including semiconductor elements, and multi-layered wiring regions, wherein at least one layer of the wiring regions above the first wiring region on the semiconductor substrate is fabricated using a process comprising the following steps (a) to (f):(a) a step of forming a via-hole in an interlayer dielectric formed above the first wiring region on a semiconductor substrate;(b) a degassing step for removing gaseous components included within said interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300.degree. C. to 550.degree. C.;(c) a step of forming a wetting layer on the surface of said interlayer dielectric and said via-hole;(d) a step of cooling the substrate to a temperature of no more than 100.degree. C.;(e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on said wetting layer at a temperature of no more than 200.degree. C.; and(f) a step of forming a second aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on said first aluminum layer at a temperature of at least 300.degree. C.