Patent ID: 8049536
Filing Date: 2011-11-01
Classification: H03F

Abstract:
1. A half-power buffer amplifier, comprising: a rail-to-rail differential amplifier; a buffer stage that includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to the rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier; and a switch network configured to control connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier; wherein the first-half buffer stage is coupled to power at one end and coupled to half power plus a predetermined voltage (ΔV) at another end, and the second-half buffer stage is coupled to the half power minus the predetermined voltage (ΔV) at one end and coupled to ground at another end.