Patent ID: 6356315
Filing Date: 2002-03-12
Classification: G06T,H04N

Abstract:
A sampling rate conversion system comprising:an FIR filter that receives a discrete signal to be resampled via a first input and FIR coefficient data via a second input and provides a filtered output; an electronic memory device coupled to said FIR filter that stores said FIR coefficient data; and a DDA controller coupled to said FIR filter and said electronic memory device that receives a desired magnification/reduction ratio, M/L, wherein L and M are integers, and that coordinates shifting of said discrete signal into said FIR filter with selection of coefficients from said electronic memory device so that said filter output achieves said desired magnification/reduction ratio, said DDA controller comprising: a ratio register that stores said magnification/reduction ratio and provides said ratio as an output; an adder that adds a first adder input to a second adder input to provide an adder output, wherein said first adder input is coupled to said output of said ratio register; a status register that receives said adder output as an input and provides said second adder input as an output, wherein said ratio register is summed into said status register by said adder after every calculation by said FIR filter of a sample of said filtered output; and a decoder circuit that receives said output of said status register as an input and provides 1) an input shift control signal to said FIR filter to control shifting of input samples into said FIR filter, and 2) a coefficient selection signal to said electronic memory device to select a group of FIR coefficients to be loaded into said FIR filter.