Patent ID: 9013240
Filing Date: 2015-04-21
Classification: G01R,H03B,H03J,H03K,H03L,H04B

Abstract:
1. A circuit, comprising: a demodulator configured to demodulate a plurality of input signals to form a plurality of demodulated input signals; a resistor-capacitor (RC) oscillator configured to provide a first clock to a frequency discriminator; the frequency discriminator is configured to discriminate frequency ranges of the plurality of demodulated input signals according to the first clock; a controller configured to determine whether at least a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; a crystal oscillator; wherein the controller is further configured to trigger the crystal oscillator to provide a second clock to calibrate the RC oscillator if at least the first predetermined number of consecutive demodulated input signals fall into the first predetermined frequency range.