Patent ID: 8156265
Filing Date: 2012-04-10
Classification: G06F

Abstract:
1. A data processor comprising: a single-token-record memory having a plurality of first storage locations; a sequencer circuit coupled to said single token-record memory, wherein said sequencer circuit, responsive to a request to place a token in a tail-end of a queue, stores said token into one of said plurality of first storage locations if said single-token-record memory stores no greater than a predetermined number of tokens associated with said tail-end of said queue, and stores said token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations if said single-token-record memory stores more than the predetermined number of tokens; and a memory controller coupled to said sequencer circuit, the memory controller to provide a communication path through which the sequencer stores said token with said at least one additional token and said pointer in a location of a multi-token-record memory when said single-token-record memory stores more than the predetermined number of tokens, said multi-token-record memory having said plurality of second storage locations.