Patent ID: 8649231
Filing Date: 2014-02-11
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array configured having memory cells arranged therein, each of the memory cells provided at an intersection of a word line and a bit line; a dummy cell provided at an intersection of a dummy word line and a dummy bit line and configured to retain certain data fixedly; a delay circuit configured to delay a signal read into the dummy bit line to generate a sense amplifier activating signal; and a sense amplifier circuit configured to start an operation based on a change in the sense amplifier activating signal, and detect/amplify a signal read out from the memory cell into the bit line, the delay circuit being configured having a first logical gate circuit and a second logical gate circuit cascade-connected, and the first logical gate circuit and the second logical gate circuit being configured such that a second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and the first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state, wherein the delay circuit is configured having the first logical gate circuit and the second logical gate circuit alternately cascade-connected between an input terminal and an output terminal of the delay circuit.