Patent ID: 6449749
Filing Date: 2002-09-10
Classification: G05B,G06F,H01L

Abstract:
A method for predicting a yield for integrated circuits comprising:a) providing information for fabricating at least one type of characterization vehicle having at least one feature which is representative of at least one type of feature to be incorporated into a final integrated circuit product; b) fabricating a characterization vehicle which embodies layout features representative of the product employing at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product; c) providing a product layout; d) extracting layout characteristics from the product layout, comprising: 1) listing all structures in the characterization vehicle; 2) classifying each structure into families such that all structures in each family form an experiment over a particular attribute; and 3) for each family, determining which attributes are to be extracted for the product layout; and e) using the extracted layout characteristics in connection with a yield model to produce a yield prediction.