Patent ID: 7663193
Filing Date: 2010-02-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a first active region provided in a memory cell region on said substrate; a second active region which is separated from said first active region by an element isolator and provided at a position closer to a center of said memory cell region than said first active region; a first gate electrode which crosses said first active region; a second gate electrode which is separated from said first gate electrode and crosses said first active region and said second active region; a third gate electrode which is separated from said first gate electrode and said second gate electrode, an end of which is opposed to an end of said first gate electrode on said second active region side and retreated from said first gate electrode more than an end of said second active region opposed to said first gate electrode; a first drain section between said first gate electrode and said second gate electrode in said first active region; a second drain section at the position of a same side of said first drain toward said second gate electrode in said second active region; a first wiring which connects said first drain section and said second drain section; and a second wiring which connects said second drain section and said third gate electrode.