Patent ID: 8405774
Filing Date: 2013-03-26
Classification: G09G

Abstract:
1. A synchronization signal control circuit outputting a display vertical synchronization signal used for displaying an input video signal to a display section capable of providing a display based on the input video signal when a vertical synchronization period of the input video signal is within a compensation period range between a minimum vertical synchronization period and a maximum vertical synchronization period, the synchronization signal control circuit comprising: a phase difference detecting section configured to detect a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal; and a vertical synchronization correction control section configured to correct a cycle period of the display vertical synchronization signal within the compensation period range so as to reduce the phase difference, wherein: when a period based on the phase difference is greater than a period equivalent to a difference between a reference vertical synchronization period within the compensation period range and the minimum or maximum vertical synchronization period, the vertical synchronization correction control section sets the cycle period of the display vertical synchronization signal to the minimum vertical synchronization period or the maximum vertical synchronization period.