Patent ID: 7892902
Filing Date: 2011-02-22
Classification: B82Y,H01L

Abstract:
1. A method to form a group III-V material transistor, comprising: forming a lower barrier region comprising InAlAs; forming a quantum well channel region comprising InGaAs on top of the lower barrier region; forming a first spacer region comprising InGaAs on top of the quantum well channel region; forming a second spacer region comprising InAlAs on top of the first spacer region; forming a doped region on top of the second spacer region; forming an upper barrier region comprising InAlAs on top of the doped region; removing a portion of the upper barrier region, a portion of the doped region, and a portion of the second spacer region to expose a portion of the first spacer region; and forming a gate dielectric on the first spacer region after exposing the first spacer region.