Patent ID: 7620799
Filing Date: 2009-11-17
Classification: G06F

Abstract:
1. A microprocessor that speculatively executes instructions and commits results of non speculative instructions to at least one architected facility, said method comprising the steps of: logic that determines the occurrence of a stall condition during the execution of said instructions; at least one functional unit that speculatively executes speculative instructions during said stall condition across multiple pipeline stages; circuitry that determines the validity of speculative data utilized during said speculative execution; and a non-architected facility that maintains said speculative data when said speculative instructions pass a last of said multiple pipeline stages, the non-architected facility having a non-architected facility register for each register of the at least one architected facility; and a modified bit vector, having a plurality of modified bits, associated with the non-architected facility, wherein: the modified bit vector provides a modified bit for each non-architected facility register, and wherein the modified bit for a non-architected facility register is set in response to a result of a speculative instruction being written to a corresponding non-architected facility register in response to the speculative instruction passing the last of the multiple pipeline stages, said at least one functional unit retrieves valid data for use by said non speculative instructions upon removal of said stall condition, the modified bits of the modified bit vector correspond to entries in said architected facility for tracking a modified state of said data for the speculatively executed speculative instructions during their execution in said multiple pipeline stages of said microprocessor, said modified bit vector is provided to said speculatively executing speculative instructions which have a dependency on said speculative data that is determined to be modified, speculative instructions that have a dependency on a prior speculatively executed speculative instruction are speculatively executed using said modified data from said non-architected facility when a corresponding modified bit is a first value, and speculative instructions that have a dependency on a prior speculatively executed speculative instruction are speculatively executed using speculative data from said architected facility when said modified bit is a second value.