Patent ID: 6448814
Filing Date: 2002-09-10
Classification: H03K

Abstract:
A CMOS buffer circuit comprising:a pre-driving stage for receiving an input signal and sequentially increasing an output driving capability of the input signal; an output buffer driving stage for producing first and second signals having the same frequency and a different pulse duty cycle, responding to an output signal of the pre-driving stage, wherein the output buffer driving stage includes: a pull-up PMOS driving stage for outputting the first signal which drives the output stage, responding to the output signal of the pre-driving stage and the second signal; and a pull-down NMOS driving stage for outputting the second signal which drives the output stage, responding to the output signal of the pre-driving stage and the first signal; and an output stage for driving an output terminal, responding to the first and second signals of the output buffer driving stage.