Patent ID: 9048186
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A method for forming an integrated circuit, the method comprising: forming a gate dielectric structure over a substrate; patterning a metallic capping layer over the gate dielectric structure by using a photoresist layer over the metallic capping layer; removing the photoresist layer, thereby leaving carbon-containing organic residues on a patterned metallic capping layer and the gate dielectric structure; forming a titanium-containing sacrificial layer over the patterned metallic capping layer and the gate dielectric structure, the titanium-containing sacrificial layer contacting the carbon-containing organic residues; generating a product by causing an interaction between the titanium-containing sacrificial layer and the carbon-containing organic residues; substantially removing the whole titanium-containing sacrificial layer and the product; and patterning the gate dielectric structure after substantially removing the whole titanium-containing sacrificial layer.