Patent ID: 7899961
Filing Date: 2011-03-01
Classification: G06F,G11C

Abstract:
1. A method of performing bus inversion by an integrated circuit, comprising: determining which of one of a plurality of bus inversion schemes supported by the integrated circuit should implement during operation of the integrated circuit; configuring the integrated circuit to implement the determined bus inversion scheme; storing a count value and a flag type associated with the bus inversion scheme for which the integrated circuit is configured, the count value indicating a number of bits of a data word that must be in a certain logic state for the data word to be inverted, the flag type indicating whether a bit inversion flag for the data word should be set to a logic zero or a logic one to indicate if the data word is inverted, wherein the flag type for a first one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic zero if the data word is inverted and the flag type for a second one of the plurality of bus inversion schemes indicates the bit inversion flag should be set to a logic one if the data word is inverted so that the integrated circuit accommodates bus inversion schemes having different count values and different flag types; and processing information input to and output from the integrated circuit in accordance with the count value and the flag type associated with the bus inversion scheme for which the integrated circuit is configured.