Patent ID: 7519794
Filing Date: 2009-04-14
Classification: G06F

Abstract:
1. An apparatus comprising: a plurality of buffers of a writeback stage of a processor pipeline, wherein a first buffer of the plurality of buffers is capable of only storing a first instruction latency and a second buffer of the plurality of buffers is capable of only storing a second instruction latency, where the first and the second instruction latencies are different, wherein each of the plurality of buffers has a plurality of storage locations each to store result data for an executed instruction of the instruction latency, received via a result channel coupled between an execute stage of the processor pipeline and the writeback stage, resulting from the instruction execution in the processor pipeline having the instruction latency; a pointer storage of the writeback stage to store pointers, wherein each of the result data stored in one of the plurality of buffers has a corresponding pointer stored in the pointer storage; logic of the writeback stage to generate a stall signal to be provided to the processor pipeline to stall the processor pipeline if a number of writes to be written to the plurality of buffers in a next cycle may exceed a capacity of at least one of the plurality of buffers, based on look ahead information received via a look-ahead channel coupled between the execute stage and the writeback stage; and a resource coupled to the plurality of buffers to receive the data therefrom.