Patent ID: 6369614
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A stage in a multi-stage, self-timed datapath circuit that calculates one or more data outputs as a function of one or more data inputs, the stage comprising:digital logic having multiple logical elements that calculate both internal results for use as inputs to other logical elements within the stage and final results for use as inputs to logical elements in a next stage; an internal completion signal generator, coupled with the digital logic, that detects completion by the digital logic of calculation of the internal results, and in response generates completion signals for at least one detected internal result; and a done signal generator that receives the completion signals, and in response, generates a done signal with a predetermined delay after at least one predetermined combination of the completion signals has been received, wherein the predetermined delay is at least as long as a maximum delay until the one or more data outputs are calculated.