Patent ID: 6046926
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A ferroelectric memory comprising:a memory cell array in which a plurality of memory cells are arrayed in rows and columns, each of the plurality of memory cells including an information storage capacitor and a first MOS transistor, which is connected to the information storage capacitor in series, the information storage capacitor having a first and a second electrode opposing each other and a ferroelectric film sandwiched by the first and the second electrode, the first MOS transistor having first source and drain regions and a first gate electrode, and one of the first source and drain regions being connected to the first electrode of the capacitor;a plurality of word lines arrayed in correspondence with the rows, each of the plurality of word lines being connected to the first gate electrode of the first MOS transistor of each of the plurality of memory cells arrayed on a corresponding one of the rows;a row decoder for selectively driving the plurality of word lines;a plurality of plate lines, each of the plate lines being connected to the second electrode of the capacitor of each of the plurality of memory cells arrayed on a corresponding one of the rows;a plurality of bit lines arrayed in correspondence with the columns and arranged to cross the plurality of word lines, each of the plurality of bit lines being connected to the other of the first source and drain regions of the first MOS transistor of each of the plurality of memory cells arrayed on a corresponding one of the columns;a plurality of second MOS transistors for bit line selection, which are coupled to the plurality of bit lines, respectively, each of the second MOS transistors having second source and drain regions and a second gate electrode, and one of the second source and drain regions being connected to a corresponding one of the plurality of bit lines; anda test circuit connected to the second gate electrode of each of the plurality of second MOS transistors, the test circuit transferring data to the plurality of memory cells through the plurality of bit lines and the plurality of second MOS transistors.