Patent ID: 6078983
Filing Date: 2000-06-20
Classification: G06F

Abstract:
A multiprocessor system comprising:a plurality of processors;an address bus coupled to said plurality of processors;a data bus coupled to said plurality of processors;a memory having a plurality of banks, each of which receives an address signal from one of said plurality of processors through said address bus, stores data provided through said data bus when storing of the data is requested, and provides memory data to a corresponding one of said plurality of processors through said data bus when reading out of the memory data is requested, each of said plurality of banks of said memory having a first-in first-out memory to store a plurality of access requests from said plurality of processors;a first arbiter which is connected to said address bus and which serves to decide the ownership of said address bus in response to a request on said address bus from one of said plurality of processors; anda second arbiter which is connected to said data bus and which serves to decide the ownership of said data bus in response to a request on said data bus from one of said plurality of processors or one of said plurality of banks of said memory;wherein said second arbiter makes said first arbiter give the ownership of said address bus to one of said plurality of processors when said second arbiter gives the ownership of said data bus to the one of said plurality of processors.