Patent ID: 6961881
Filing Date: 2005-11-01
Classification: G11C

Abstract:
1. A semiconductor device comprising a logic chip and a memory chip to be accessed by said logic chip mounted in a single package, said logic chip includes: a mode selecting terminal for receiving a mode selecting signal supplied from an exterior of the semiconductor device to select one of a first and second test modes for testing said memory chip; a pattern generator for operating during said first test mode to generate internal test pattern(s) for said memory chip; a test result terminal for outputting, to the exterior of the semiconductor device, a result of a test executed according to said internal test pattern; a first multipurpose terminal serving as a test terminal during said second test mode and serving as a normal terminal during a normal operation, the first multipurpose terminal connected to the exterior of the semiconductor device; and a pattern selector for selecting, during said first test mode, said internal test pattern(s) outputted from said pattern generator, for selecting, during said second test mode, an external test pattern supplied via said test terminal, and for outputting the selected test pattern to said memory chip.