Patent ID: 8593188
Filing Date: 2013-11-26
Classification: H03L

Abstract:
1. A circuit, comprising: a phase frequency detector (PFD); an up current switch coupled to an output of the comparative phase detector; a down current switch coupled to an output of the comparative phase detector; a current source coupled through the up current switch to a node, a down current sourced coupled through the down current switch to a node, wherein the loop filter resistor is employed to create a zero in the circuit to create a zero pole when the first and second bypass switches are not closed, and wherein the first and second bypass switches are a complementary CMOS pair, wherein the loop filter resistor is employed to create a zero in the circuit and create the zero pole when the first and second bypass switches are not closed, and a noise of a loop filter resistor is bypassed when the loop filter resistor is bypassed.