Patent ID: 6987044
Filing Date: 2006-01-17
Classification: H01L

Abstract:
1. A method for forming an asymmetric insulating layer for a volatile memory structure, comprising the steps of: providing a substrate having a pair of neighboring trenches; forming a buried trench capacitor in a lower portion of each trench; forming an asymmetric collar insulating layer, having a high level portion and a low level portion, over an upper portion of the sidewall of each trench, and forming a conductive layer, overlying the buried trench capacitor in each trench, below the upper surface of the substrate with a lower part of the conductive layer surrounded by the asymmetric collar insulating layer, wherein the high level portion of the asymmetric collar insulating layer is adjacent to the substrate between the neighboring trenches and the low level portion is covered by an upper part of the conductive layer, wherein the step of forming the asymmetric collar insulating layer comprises: forming a sacrificial layer in each trench, the sacrificial layer overlying the buried trench capacitor and being surrounded by an insulating spacer protruding the surface of the sacrificial layer; covering portions of the insulating spacers adjacent to the substrate between the neighboring trenches by a masking layer; removing the uncovered insulating spacers to form the asymmetric collar insulating layer; and successively removing the masking layer and the sacrificial layer; forming a dielectric layer overlying the conductive layer in each trench; and forming access transistors on the substrate outside of the pair of the neighboring trenches, respectively, wherein each access transistor has source or drain region electrically connecting to the conductive layer.