Patent ID: 6744323
Filing Date: 2004-06-01
Classification: H03L,Y10S

Abstract:
An apparatus comprising:a phase lock loop (PLL) configured to multiply an input frequency to generate an output frequency in response to a multi-bit lock signal; and a lock circuit configured to generate said multi-bit lock signal, wherein said PLL is configured to (i) (a) select a reference frequency as said input frequency and (b) select a first feedback ratio, when in a first mode and (ii) (a) select one of a plurality of divided frequencies of said reference frequency to be said input frequency and (b) select a second feedback ratio, when in a second mode, wherein (i) said selected divided frequency is selected in response to said multi-bit lock signal, (ii) a first bit of said multi-bit lock signal selects said first feedback ratio, and (iii) a second bit of said multi-bit lock signal selects said second feedback ratio.