Patent ID: 6349364
Filing Date: 2002-02-19
Classification: G06F

Abstract:
A cache memory system wherein a cache memory is provided for temporarily storing data stored in a main memory, and a processor accesses said cache memory, said cache memory system comprising:a block-size information storing means for storing respective sizes of the data to be replaced between the cache memory and the main memory in every storage space of respective predetermined amounts within the cache memory; means for replacing the data between the storage space in which a cache miss occurs within the cache memory and the main memory, when access of the processor to the storage space within the cache memory raises the cache miss, at the block-size corresponding to the storage space in which the cache miss occurs, among the size stored in the block-size information storing means; the processor outputting an access address with individual fields of tag address, index address, bank address and an offset within the bank; the cache memory including at least two cache banks, and each of the cache banks having a data array constituted by an aggregate of elements storing the data in a word number assigned by an offset within the bank, a valid flag array constituted by an aggregate of valid flags storing whether or not the data stored in the individual elements of the data array are valid, and a tag array storing the individual tag addresses of the data stored in the individual elements of the data arrays; the data array, the valid flag array and the tag array respectively outputting the data of the elements assigned by the index address, values of the valid flags of the data, and the tag address of the data; each of the cache banks being provided with a comparator for comparing the tag address outputted by the tag array and the tag address within the access address and indicating the comparison result, when the value of the valid flag indicates the storing of the data valid to the element; a first multiplexer for selecting and outputting the comparison result of the cache bank assigned by the bank address; the block-size information storing means referring the size in each of the storage spaces within the cache memory at the index address; and a memory access control circuit performing control of replacing the data between the cache memory and the main memory, wherein when the processor outputs the access address, the memory access control circuit judges whether or not the cache miss is raised by the output of the first multiplexer, and when the cache miss occurs, the memory access control circuit replaces the data between the storage space in which the cache miss occurs and the main memory space assigned by the access address, at the block-size corresponding to the storage space in which the cache miss occurs, among the size stored in the block-size information storing means.