Patent ID: 6584529
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A circuit arrangement, comprising:(a) a requester interface configured to receive a plurality of data transfer requests from a plurality of requesters, a first data transfer request among the plurality of data transfer requests associated with a first requester among the plurality of requesters; (b) a shared resource interface configured to forward the data transfer requests received by the requester interface to a shared resource; (c) an intermediate buffer configured to receive data associated with the first data transfer request from the first requester in response to the first data transfer request and thereafter forward the data to the shared resource; and (d) intermediate buffer control logic, coupled to the intermediate buffer, the intermediate buffer control logic configured to inhibit a transfer of data associated with the first data transfer request from the first requester to the intermediate buffer until the first data transfer request is ready to be processed at the shared resource and a predetermined amount of space is available in the intermediate buffer.