Patent ID: 7816257
Filing Date: 2010-10-19
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, the method comprising: forming a first insulating layer on a substrate; forming a semiconductor layer comprising single crystalline silicon on the first insulating layer; forming a second insulating layer on the semiconductor layer; forming an opening extending through the first and second insulating layers and through the semiconductor layer between the first insulating layer and the second insulating layer to a surface of the substrate, the opening including a recess between the first and second insulating layers adjacent the semiconductor layer; and forming a conductive plug comprising a plurality of stacked metal layers in the opening to contact the substrate and a side of the semiconductor layer; wherein forming the opening further comprises selectively recessing a portion of the semiconductor layer at a sidewall of the opening to form the recess between the first and second insulating layers and to define a recessed portion of the semiconductor layer, and wherein forming the conductive plug comprises: