Patent ID: 6839279
Filing Date: 2005-01-04
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells and reference cells, the reference cells including a first reference cell and a second reference cell; a data judging control unit generating an average reference current based on a first reference current supplied from the first reference cell and a second reference current supplied from the second reference cell, the data judging control unit determining data of each of the memory cells by comparison of a read-out voltage of each of the memory cells with the average reference current; a control unit performing a program verification operation to each memory cell of the memory cell array; and a compensation current supplying unit supplying a compensation current to a bit line of a target memory cell of the memory cell array when a leak current of a neighboring memory cell adjacent to the target memory cell exceeds a predetermined reference value during the program verification operation of the control unit to the target memory cell, said compensation current compensating the leak current of the neighboring memory cell.