Patent ID: 6417046
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A method of forming a modified nitride spacer in a floating gate memory cell comprising the steps of:providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined; forming a gate oxide layer over said substrate; forming a polysilicon layer doped with a second conductive type of dopant over said gate oxide layer; patterning said polysilicon layer to form a gate electrode having sidewalls over said gate oxide layer; then performing first ion implant on said substrate using said gate electrode as a mask to form lightly doped source/drain regions; then forming an oxide layer over said gate electrode; then forming a nitride layer over said oxide layer; then etching said silicon nitride layer to form nitride spacers on sidewalls of said gate electrode; and performing second ion implant on said substrate using said nitride spacers as a mask to complete the forming of said source/drain regions.