Patent ID: 8198729
Filing Date: 2012-06-12
Classification: H01L

Abstract:
1. A chip package comprising: a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a first dielectric layer between said first and second metal layers, and a separating layer over said silicon substrate, said metallization structure and said first dielectric layer, wherein said separating layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers, wherein a first opening in said separating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening; a ground interconnect on said first and second contact points and said separating layer, wherein no polymer layer is between said separating layer and said ground interconnect and under said ground interconnect, wherein said first contact point is connected to said second contact point through said ground interconnect, wherein said ground interconnect comprises a third metal layer, a copper-containing seed layer on said third metal layer, an electroplated copper layer on said copper-containing seed layer, wherein said electroplated copper layer has a thickness greater than 1 micrometer, and a tin-containing joint over said electroplated copper layer, wherein said tin-containing joint has a thickness greater than 10 micrometers; and a circuit component over said semiconductor chip and in contact with said ground interconnect, wherein said circuit component comprises a fourth metal layer, a fifth metal layer and a second dielectric layer between said fourth and fifth metal layers, wherein said circuit component is connected to said semiconductor chip through said ground interconnect, wherein a contact area between said circuit component and said ground interconnect is vertically over said first and second contact points.