Patent ID: 6452115
Filing Date: 2002-09-17
Classification: H01L,H05K

Abstract:
A multi-layer circuit board comprising:an upper circuit layer and a plurality of subsequent circuit layers successively laminated below the upper circuit layer to form a stack, each circuit layer comprising a substrate having a surface and edges, a plurality of land regions arranged equidistantly in columns and rows in a staggered lattice form where a line connecting lands in a row and in a column is on an angle diagonal to an edge of the substrate, and circuit patterns formed on the surface of the substrate; wherein the plurality of land regions on the upper circuit layer are each occupied by a land and the arrangement of lands corresponds to the arrangement of electrodes on a semiconductor element that is to be mounted on the upper circuit layer and is characterized by a pitch of the lands, a diameter of the lands, a width of patterns, a space between patterns, a parameter &agr; that represents the number of patterns that can pass through adjacent lands, and a parameter n that represents the smallest integer that satisfies the equation m&gE;(k+1) wherein m=â€ƒ&it;{(land&it;â€ƒ&it;pitch)Ã—(n-1)-(land&it;â€ƒ&it;diameter)-â€ƒ&it;(space&it;â€ƒ&it;between&it;â€ƒ&it;patterns)}&div;â€ƒ&it;(pattern&it;â€ƒ&it;width+space&it;â€ƒ&it;between&it;â€ƒ&it;patterns)and&it;â€ƒ&it;k=Î±&af;(n-1)+(n-2);wherein, on the upper circuit layer, all of the lands in the outermost row of lands are connected to circuit patterns that are drawn toward the edges of the substrate, and some of the lands on an inner row are connected to circuit patterns that are drawn toward the edges of the substrate; wherein the plurality of lands on the subsequent circuit layers are arranged to correspond to the arrangement of lands from which circuit patterns are not drawn on the adjacent circuit layer that is higher in the stack; and wherein, on a subsequent circuit layer, all of the lands located in the outermost position of the lands are connected to circuit patterns that are drawn toward the edges of the substrate, some of the lands on selected inner rows which are the same rows as the upper most circuit layer, are connected to circuit patterns that are drawn toward the edges of the substrate; wherein said selected rows are selected as the remaining (nâˆ’2) rows subtracted from both ends of consecutively arranged (n) land sequences; wherein lands from which no circuit patterns are drawn on a subsequent circuit layer are electrically connected through vias to the lands formed on the adjacent circuit layer that is lower in the stack; and wherein regions of a subsequent circuit layer that correspond to regions of the lands from which circuit patterns are drawn on the adjacent circuit pattern that is higher in the stack are utilized as regions for drawing circuit patterns.