Patent ID: 6815768
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device comprising:sequentially forming a gate insulating film, a conductor film containing silicon, and a cap insulating film containing a member capable of selectively etching a silicon nitride film in each of a first silicon semiconductor region and a second silicon semiconductor region; patterning a laminated film constituted of the cap insulating film and the conductor film to form a gate electrode in each of the first and second silicon semiconductor regions; using the laminated film as a mask for introducing impurity to selectively introduce the impurity so as to form source and drain diffusion regions in each of the first and the second silicon semiconductor regions; forming a first silicon nitride film on a sidewall of each of the laminated films; forming a second silicon nitride film on an entire surface; depositing a first insulating film on the entire surface, and then leaving the first insulating film between the gate electrodes in the first silicon semiconductor region; depositing a second insulating film in the second silicon semiconductor region, and then leaving the second insulating film on a sidewall of each of the laminated films in the second silicon semiconductor region; removing the second silicon nitride film on each of the laminated films and the second silicon nitride film left on a surface of the second silicon semiconductor region; removing the cap insulating film left above each of the gate electrodes; forming a metal silicide film on a surface of the conductor film of each of the gate electrodes and forming a metal silicide film on each surface of the source and drain diffusion regions formed in the second silicon semiconductor region; and depositing a third silicon nitride film on the entire surface, and then leaving the third silicon nitride film on each of the gate electrodes.