Patent ID: 7531864
Filing Date: 2009-05-12
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory device, comprising: a first semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a first semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a second semiconductor section of the first conductivity type provided in the second region; a third semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; first impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; second impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and third impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region, wherein an overlapping area of the floating sate electrode and the first semiconductor section is greater than an overlapping area of the floating gate electrode and the second semiconductor section.