Patent ID: 7038934
Filing Date: 2006-05-02
Classification: G11C

Abstract:
1. A method for writing multiple-bit data, which comprises: providing a nonvolatile ferroelectric memory device comprising a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells controlled by a plate line and a wordline, a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column, a plurality of sub bitlines connected with one terminal of the unit cells and arranged along the main bitlines, switching transistors respectively arranged per sub bitline so that a gate is connected to the sub bitlines and a drain is connected to the main bitlines, and a sensing amplifier block consisting of a plurality of sensing amplifiers commonly used in the cell array blocks, transferring voltages corresponding to the data stored in the cells to the main bitlines by current sensing through the switching transistors and sensing the voltages transferred to the main bitlines in a multiple-bit state; writing high data in all the cells; and controlling voltages of the plate line and the sub bitlines to write multiple-bit data of n-bit in the cells.