Patent ID: 8872750
Filing Date: 2014-10-28
Classification: G09G,G11C,H01L

Abstract:
1. A semiconductor device comprising: a first substrate; a second substrate; first to n-th signal lines between the first substrate and the second substrate; a sampling circuit comprising first to n-th analog switches; and a shift register comprising first to n-th register circuits, wherein an i-th register circuit of the first to n-th register circuits comprises: a first inverter circuit comprising a first input terminal and a first output terminal; and a second inverter circuit comprising a second input terminal electrically connected to the first output terminal and a second output terminal electrically connected to an i-th signal line of the first to n-th signal lines, wherein the second output terminal of the i-th register circuit is electrically connected to the first input terminal of an (i+1)-th register circuit, wherein the first inverter circuit is a clocked inverter circuit, wherein an i-th analog switch of the first to n-th analog switches comprising: a video input terminal; a first timing input terminal electrically connected to the second output terminal of the i-th register circuit; a second timing input terminal electrically connected to the second output terminal of the i-th register circuit via a third inverter circuit; and a video output terminal; wherein n is a natural number, wherein i is a natural number larger than 1 and less than n, wherein a gate electrode of an n-channel TFT in the shift register overlaps a part or a whole part of an LDD region of the n-channel TFT, and wherein a gate electrode of n-channel TFT does not overlap an LDD region of the n-channel TFT in a pixel portion, wherein the semiconductor device further comprises a thin film transistor, wherein a gate electrode of the thin film transistor has a tapered shape in an end portion of the gate electrode in cross section, wherein a length of an upper base of the gate electrode is smaller than a length of a lower base of the gate electrode in the cross section, wherein a surface of a gate insulating film over the end portion is flattened, and wherein a semiconductor film is over the surface of the gate insulating film.