Patent ID: 7504306
Filing Date: 2009-03-17
Classification: H01L

Abstract:
1. A method of forming a field effect transistor comprising an active area and a termination region surrounding the active area, the method comprising: forming gate trenches extending into a silicon region of a first conductivity type; forming a well region of a second conductivity type in the silicon region; forming a recessed gate in each gate trench; forming a dielectric cap over each gate; recessing all exposed surfaces of the well region to form a recess in the well region between every two adjacent trenches such that the recess has sloped walls and a bottom located between a top surface of the dielectric cap and a top surface of the recessed gate; and without masking any portion of the active area, performing a zero-degree blanket implant to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches whereby the heavy body region is self-aligned to the gate trenches.