Patent ID: 6570796
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A wafer burn-in test circuit for a semiconductor memory device, comprising:first and second probe pad units having a floating state before blowing a wafer; a first buffer unit for initializing a signal from the first probe pad unit in a power-up operation based on a power-up signal, converting the signal into a CMOS level, and outputting the converted signal; a second buffer unit for initializing a signal from the second probe pad unit in the power-up operation based on the power-up signal, converting the signal into a CMOS level, and outputting the converted signal; a fuse unit for generating a first control signal for selecting a signal generation path for a burn-in test operation of a wafer state before blowing the wafer, and a signal generation path for an operation of a bit line after blowing the wafer; a decoder and multiplexer unit for receiving the first control signal from the fuse unit and the output signals from the first and second buffer units, generating a second control signal for the wafer test operation before blowing the wafer and generating a third control signal for the operation of the bit line after blowing the wafer based on the first control signal; a test mode block unit for generating a fourth control signal in the wafer burn-in test mode based on the second control signal from the decoder and multiplexer unit; an array control unit for controlling bit lines, word lines and plate lines composing an access transistor of a memory cell based on the fourth control signal from the test mode block unit, and applying a stress to the cell, bit line and storage node; and a data multiplexer unit for controlling input/output of a desired data bit based on the third control signal from the decoder and multiplexer unit.