Patent ID: 8302067
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A pin out designation method for package board codesign, the method being performed by a computer and comprising: defining pin characteristics and requirements of a chip; generating multiple pin patterns of the chip; constructing and grouping pin blocks; and floorplanning pin blocks, wherein: in defining the pin characteristics and requirements of the chip, predefined characteristics and requirements for the chip are loaded into the computer, the chip is to be mounted on a printed circuit board (PCB) and surrounded by multiple components on the PCB, and the characteristics and requirements comprise location relationships between the chip and the multiple components on the PCB, signal integrity of pins of the chip, pin names, pin numbers and power pin numbers; in generating multiple pin patterns of the chip, the computer solves loaded characteristics and requirements with an Integer Linear Programming (ILP) problem to generate multiple pin patterns (PAi), each pin pattern is unique and comprises multiple signal pins and shield pins, and the shield pins are power pins or ground pins; in constructing and grouping the pin blocks, the computer constructs multiple pin blocks of the chip using the pin patterns according to a rough pin configuration, wherein each pin block of the chip for connecting to a corresponding component on the PCB is constructed based on the characteristics and requirements and is adapted to be adjacent to the corresponding component of the PCB; wherein the pin blocks of the chip are grouped as four pin block groups respectively located around four sides of the chip using a boundary-constrained pin-block grouping strategy (BCPG) or a congestion-free pin-block grouping strategy (CFPG), the four pin block groups are successively arranged around the four sides of the chip in a clockwise or counterclockwise direction, and the pin blocks are grouped as an integrated pin block until a size of the integrated pin block of the chip is located within a safe range; wherein four size relation factors (Ei, i ε 1,2,3,4) are defined by the computer and each of the four size relation factors represents a size difference between one of the four pin block groups and the size of the integrated pin block; and wherein in floorplanning the pin blocks, the computer generates a linear program related to the four size relation factors and uses the linear program to acquire a size of a minimized integrated pin block; and wherein the pin block groups are floorplanned by the computer to move excessive parts of the pin block groups to neighboring empty areas adjacent to the excessive parts of the pin block group.