Patent ID: 6728254
Filing Date: 2004-04-27
Classification: H04L

Abstract:
A memory architecture comprising a common memory structure having a plurality of data locations for storing data units and an input section for providing a plurality of input ports with access to the common memory stucture, the input section including:at least one memory buffer associated with each input port, each memory buffer capable of storing a number of data units at least equal to the number of input ports; and at least one data bus allowing each of the memory buffers to write a plurality of data units substantially simultaneously to the memory structure at least once during a memory-access cycle, different memory buffers being arranged to write their respective plurality of data units to the memory structure during different phases of the memory access cycle, the common memory structure including a plurality of memory banks, the number of memory banks being equal to or greater than the number of input ports, each memory bank being accessible substantially simultaneously to receive data units from a memory buffer during a phase of the memory access cycle, each data unit received from said memory buffer during said phase of a memory access cycle being written to a different memory bank.