Patent ID: 6493778
Filing Date: 2002-12-10
Classification: G06F

Abstract:
An extensible time-sharing bus structure for transferring data between a master device and at least one slave device, said bus structure comprising:a slave bus interface provided by said slave device; and a master bus interface provided by said master device and connected to said slave bus interface through an address/data bus and at least two control lines, said address/data bus transferring data and addresses in a time-sharing manner between said master device and said slave device, said at least two control lines being driven by said master device to be at a first logic level or at a second logic level, such that said master device and said slave device utilize said address/data bus selectively for transferring an address, reading data, and writing data based on a combination of the logic levels of said at least two control lines, wherein said slave bus interface has an address register for latching an address to access data, and wherein said slave bus interface further has a memory bank register for recording a plurality of memory bank locations provided by said slave device, and a memory bank location is combined with said address register to generate a physical address by memory mapping.