Patent ID: 6566215
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method of forming a short channel MOS transistor in the fabrication of an integrated circuit device comprising:forming a hard mask stack over a substrate; forming a first opening through a top portion of said hard mask stack; forming oxide spacers on sidewalls of said first opening thereby forming a second opening smaller than said first opening; filling said second opening between said spacers with a polysilicon layer; thereafter removing said oxide spacers; implanting first ions into said substrate underlying removed said oxide spacers to form source/drain extensions; thereafter removing said polysilicon layer wherein said first opening remains and wherein said substrate is exposed in a channel region; forming a gate dielectric layer over said channel region; filling said first opening with a gate electrode material and polishing back said gate electrode material to form a gate electrode; thereafter removing said hard mask stack using said gate electrode as a mask; and implanting second ions to form source/drain regions within said substrate adjacent to said gate electrode to complete formation of said short channel MOS transistor in the fabrication of said integrated circuit device.