Patent ID: 7126406
Filing Date: 2006-10-24
Classification: G06F,H03K

Abstract:
1. A system for providing a clock to a programming logic device (PLD) comprising: a clock tree main trunk configured to provide a plurality of differential global clock signals to one or more circuits on the PLD; a plurality of input circuits for receiving a plurality of external differential clock signals; and a plurality of differential multiplexers for selecting an external clock signal of the plurality of external clock signals for sending to the clock tree main trunk, the plurality of differential multiplexers controlled by one or more configuration memory cells of the PLD; and a plurality of 2:1 multiplexers coupled between the plurality of differential the plurality of 2:1 multiplexers and the clock tree main trunk, multiplexer selecting between the the plurality of external clock signals and a plurality of upstream clock signals received from a small signal to rail-to-rail converter.