Patent ID: 7995052
Filing Date: 2011-08-09
Classification: G09G

Abstract:
1. A driving circuit comprising: a plurality of scanning lines; a plurality of data lines; a plurality of common electrodes provided in correspondence with the plurality of scanning lines; pixels arranged at positions corresponding to intersections of the plurality of scanning lines and the plurality of data lines, wherein each of the pixels includes: a pixel switching element, one end of which is connected to a corresponding one of the data lines, wherein the pixel switching element enters an electrical conductive state when a corresponding one of the scanning lines is selected; and a pixel capacitor, one end of which is connected to an end of the pixel switching element, which is not connected to the data line, and the other end of the pixel capacitor, which is not connected to the pixel switching element, is connected to the common electrode, and wherein each of the pixels emits light with a gray-scale level corresponding to a voltage held by the corresponding pixel capacitor; a scanning line driving circuit that sequentially selects the scanning lines in a predetermined order; a common electrode driving circuit that separately drives the plurality of common electrodes; and a data line driving circuit that supplies the pixels, corresponding to the selected scanning line, with data signals of voltages corresponding to gray-scale levels of the pixels through the data lines, wherein when one of odd-numbered scanning lines or a scanning line located a predetermined number of scanning lines away from the one of the odd-numbered scanning lines is selected, the common electrode driving circuit applies one of a low level voltage and a high level voltage to the common electrode corresponding to the one of the odd-numbered scanning lines, and, after the selection of the one of the odd-numbered scanning lines is completed or after the selection of the scanning line located a predetermined number of scanning lines away from the one of the odd-numbered scanning lines is completed, the common electrode driving circuit maintains the common electrode corresponding to the one of the odd-numbered scanning line at the one of the low level voltage and the high level voltage, and wherein when one of even-numbered scanning lines or a scanning line located a predetermined number of scanning lines away from the one of the even-numbered scanning lines is selected, the common electrode driving circuit applies the other of the low level voltage and the high level voltage to the common electrode corresponding to the one of the even-numbered scanning lines, and, after the selection of the one of the even-numbered scanning lines is completed or after the selection of the scanning line located a predetermined number of scanning lines away from the one of the even-numbered scanning lines is completed, the common electrode driving circuit maintains the common electrode corresponding to the one of the even-numbered scanning lines at the other of the low level voltage and the high level voltage, wherein the common electrode driving circuit includes first to fourth transistors provided in correspondence with each of the common electrodes, wherein a gate electrode of each first transistor of the first transistors is connected to a corresponding one of the scanning lines or a scanning line located a predetermined number of scanning lines away from the corresponding one of the scanning lines and a source electrode of each first transistor is connected to a first power feed line that is supplied with a voltage with which the third transistor enters one of an on state and an off state, wherein a gate electrode of each second transistor of the second transistors is connected to a corresponding one of the scanning lines or a scanning line located a predetermined number of scanning lines away from the corresponding one of the scanning lines and a source electrode of each second transistor is connected to a second power feed line that is supplied with a voltage with which the fourth transistor enters the other of an on state and an off state, wherein a gate electrode of each third transistor of the third transistors is connected to a drain electrode of a corresponding one of the first transistors and a source electrode of each third transistor is connected to a third power feed line that is supplied with one of a low level voltage and a high level voltage, wherein a gate electrode of each fourth transistor of the fourth transistors is connected to a drain electrode of a corresponding one of the second transistors and a source electrode of each fourth transistor is connected to a fourth power feed line that is supplied with the other of a low level voltage and a high level voltage, and wherein a drain electrode of each third transistor and a drain electrode of each fourth transistor are commonly connected to the corresponding common electrode.