Patent ID: 8653996
Filing Date: 2014-02-18
Classification: H03M

Abstract:
1. A second order shuffler, comprising: a first set of N accumulators, each first accumulator to receive corresponding digital-to-analog converter (DAC) unit element selection signals, each to accumulate values representing the corresponding selection signals and to generate corresponding first accumulator output values; a first corrector provided for the first accumulators to compress a range of the first accumulator output values for each first accumulator while maintaining context of each first accumulator with reference to the other first accumulators; a second set of N accumulators, each second accumulator to receive corresponding first accumulator output values, each to accumulate the corresponding output values and to generate corresponding second accumulator output values; a second corrector provided for the second accumulators to compress a range of the second accumulator output values for each second accumulator while maintaining context of each second accumulator with reference to the other second accumulators; and a set of N adders to combine each of the first and second accumulator output values.