Patent ID: 6852579
Filing Date: 2005-02-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device having a MISFET including a gate electrode, source and drain region, the method comprising the steps of: (a) depositing a gate electrode material containing a refractory metal film over a reaction preventive film which is formed over a polysilicon film over a semiconductor substrate; (b) depositing a first insulating film on said gate electrode material at a temperature of 500° C. or lower; (c) forming a gate electrode by etching said first insulating film and said gate electrode material; (d) introducing impurities into said semiconductor substrate at both sides of said gate electrode to form a source region and a drain region; (e) depositing a second insulating film over said gate electrode and said semiconductor substrate, and etching said second insulating film to form a sidewall spacer on a sidewall of said gate electrode, (f) depositing a third insulating film over said gate electrode and said semiconductor substrate; (g) etching said third insulating film to form a contact hole exposing the surface of said source region or drain region; and (h) forming a conductor film in said contact hole.