Patent ID: 6584018
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A method for accessing a nonvolatile memory which has a plurality of rows of nonvolatile memory cells, each memory cell having a first semiconductor region, a first gate for controlling a conductivity of the first semiconductor region, a second gate insulated from the first gate, and a first source/drain region through which a current flows to or from the first semiconductor region, the method comprising:driving the first gates of each row being accessed into a first state, the second gates of each row being accessed into a second state, and the first source/drain regions of each row being accessed into a third state; driving the first gates of the rows not being accessed into a state or states different from the first state, the first gates thus selecting a row or rows being accessed; for some row R1 being accessed and some rows R2, R3 which are not being accessed, driving the second gates of the row R2 into the second state, driving the first source/drain regions of the row R3 into the third state, and driving the second gates of the row R3 into a state or states different from the second state, such that: (i) the second gates of the rows R1, R2 are in the same, second, state, (ii) the first source/drain regions of the rows R1, R3 are in the same, third, state but (iii) the second gates of the rows R1, R3 are not in the same state.