Patent ID: 8993991
Filing Date: 2015-03-31
Classification: B82Y,H01L,Y10S

Abstract:
1. A semiconductor device comprising: a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface, the first and second top surfaces connected via the first perpendicular surface; a first region doped with dopants and formed on the first top surface; a first nanowire extended away from the first perpendicular surface in one direction, and being spaced apart from the second top surface, the first nanowire including a channel region touching the first region; a second nanowire extended from the first nanowire in the one direction, being spaced apart from the second top surface, and including a second region doped with dopants and directly contacting the channel region, wherein a gate electrode formed on the first nanowire; and a dielectric layer formed between the first nanowire and the gate electrode.