Patent ID: 6618775
Filing Date: 2003-09-09
Classification: G06F

Abstract:
A system for monitoring the internal operation of a processor, said processor comprising a plurality of external contacts and one or more internal buses, said internal buses not accessible from said contacts, said system comprising:an interface connected to at least one of said plurality of external contacts and providing a trigger condition input and a bus trace output; a bus watching circuit having a monitor input connected to at least one of said buses, said bus watching circuit configured to generate a trigger output when a trigger condition derived from said trigger condition input compares to a trigger event occurring on said monitor input, said bus watching circuit further comprising a plurality of logic elements; a circular buffer having a bus data input connected to at least one of said buses, said circular buffer configured to store data from said bus data input in response to said trigger output and to read data to said bus trace output; and a display device configured to read and display data stored in said circular buffer.