Patent ID: 7858439
Filing Date: 2010-12-28
Classification: H01L

Abstract:
1. A method for manufacturing a stacked semiconductor package, comprising the steps of: preparing a substrate formed with a seed metal layer and a plurality of semiconductor chips, wherein the substrate is made of metal or non-metal material; forming recess parts in a portion of a surface of the respective semiconductor chips; forming pads on bottom surfaces of the recess parts, respectively; forming via holes penetrating a portion of the pads and the semiconductor chips such that the via holes are disposed within the recess parts; laminating semiconductor chips having the via holes aligned with one another on the seed metal layer to form a semiconductor chip module; growing a conductive growth layer inside of the via holes using the seed metal layer to form a conductive growth layer inside of the via holes, wherein an end portion of the conductive growth layer projects to an upper portion of the semiconductor chip module; separating the substrate and the seed metal layer from the semiconductor chip module; electrically connecting the end portion of the conductive growth layer to connection pads of a circuit substrate; and molding the semiconductor chip module with a molding member.