Patent ID: 7538705
Filing Date: 2009-05-26
Classification: H03M

Abstract:
1. An over-sampling analog-to-digital converter (ADC) having improved voltage reference offset cancellation and reduced source induced 1/f noise, said ADC comprising: a sigma-delta modulator having plus and minus analog inputs, plus and minus reference voltage inputs and an output supplying serial digital information therefrom, wherein the sigma-delta modulator comprises: a chopper stabilized voltage reference supplying plus and minus reference voltages to the plus and minus reference voltage inputs of the sigma-delta modulator; and a chopper clock control coupled to the chopper stabilized voltage reference and the output of the sigma-delta modulator, wherein the chopper clock control uses the serial digital information from the output of the sigma-delta modulator to generate chopper clocks that cause the chopper stabilized voltage reference to supply reference voltages to the sigma-delta modulator that comprise an equal number of positive voltage offsets and negative voltage offsets for each level of digital-to-analog conversions, and whereby an average of the positive and negative voltage offsets cancel out voltage offset contribution to the reference voltages supplied to the sigma-delta modulator.