Patent ID: 6429907
Filing Date: 2002-08-06
Classification: G02F

Abstract:
A liquid crystal display comprising:a substrate; a plurality of gate lines on the substrate; a plurality of data lines on the substrate such that the data lines are arranged as a matrix with the plurality of gate lines to define a plurality of pixel areas, wherein a pixel area includes a first data line arranged substantially parallel with a second data line and a first gate line arranged substantially parallel with a second gate line such that the first gate line intersects a first end of the first and second data lines and the second gate line intersects a second end of the first and second data lines; at least one thin film transistor such that at least one thin film transistor is defined substantially at an intersection between one of the gate lines and one of the data lines within the pixel area; an intermediate layer beneath a portion of the data lines; a protective layer covering the data lines; and a pixel electrode overlapped with the data lines and covering a portion of the protective layer in the pixel area, wherein the pixel electrode is overlapped partially with the first data line such that the pixel electrode is overlapped partially with the intermediate layer that is beneath the first data line and the pixel electrode is overlapped partially with the second data line such that the pixel electrode is not substantially overlapped with the intermediate layer that is beneath the second data line, wherein a first parasitic capacitor is defined by an area of overlap between the first data line and the pixel electrode and a second parasitic capacitor is defined by an area of overlap between the second data line and the pixel electrode such that the second parasitic capacitor has a larger overlap area than the overlap area of the first parasitic capacitor, wherein the protective layer that is between the pixel electrode and the first and second data lines defines a dielectric layer of the first and second parasitic capacitors, wherein a thickness of the dielectric layer that is between the pixel electrode and the second data line of the second parasitic capacitor is greater than a thickness between the pixel electrode and the first data line of the first parasitic capacitor, and wherein the capacitance of the first parasitic capacitor is substantially equal to that of the second parasitic capacitor.