Patent ID: 7193604
Filing Date: 2007-03-20
Classification: G09G,G11C

Abstract:
1. A shift register circuit, comprising: a plurality of latch circuits connected in series to sequentially transfer externally generated information pulse signals from one to another; a clock signal line transmitting a clock signal; and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits according to either input externally generated pulse signals or internal pulse signals that are externally generated pulses being transferred between the latch circuits, wherein the shift register circuit has alternate initialization periods and normal operation periods, and during the normal periods the latch circuits sequentially transfer said information pulse signals; the initialization periods are started either by an externally generated power on pulse signal input to the shift register circuit at power on or by externally generated cyclic signals separate from said information pulse signals input to the shift register circuit at regular intervals following the power on pulse signal; a first externally generated clock signal input to the shift register circuit during said initialization periods has a frequency different from a frequency of a second externally generated clock signal input to the shift register circuit during said normal operation periods; and during each of said initialization periods, at least one of the switching circuits electrically disconnects at least one of the plurality of latch circuits from the clock signal line in response to either a first externally generated clock signal or an internal signal that is a first externally generated clock signal being transmitted along the clock signal line.