Patent ID: 6518102
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having at least an NTFT and a PTFT, comprising:disposing a semiconductor film comprising silicon over a substrate; crystallizing said semiconductor film; patterning said semiconductor film into at least first and second semiconductor islands, each including a channel region; forming a gate electrode over each of said first and second semiconductor islands with a gate insulating film interposed therebetween; introducing phosphorus ions into both of said first and second semiconductor islands by using at least in part said gate electrodes as masks, thereby forming a pair of heavily doped regions with a first concentration approximately from 3Ã—1019 to 1Ã—1021 atoms/cm3 and a pair of lightly doped regions with a second concentration approximately from 4Ã—1016 to 7Ã—1017 atoms/cm3, said lightly doped regions being interposed between said channel region and said heavily doped regions, respectively; introducing boron ions into only one of said first and second semiconductor islands by using at least in part said gate electrode as a mask to dope said heavily doped regions with a third concentration larger than said first concentration by a first difference approximately from 3Ã—1019 to 1Ã—1021 atoms/cm3 and to dope said lightly doped regions at a fourth concentration larger than said second concentration by a second difference approximately from 3Ã—1017 to 4Ã—1018 atoms/cm3; and annealing said heavily and lightly doped regions of said first and second semiconductor islands after said introducing of said phosphorus ions, said annealing activating said phosphorus ions to getter a metal material in said each channel region.