Patent ID: 6192451
Filing Date: 2001-02-20
Classification: G06F

Abstract:
A method of maintaining cache coherency in a data processing system including an interconnect, a plurality of caches, and a plurality of processors grouped into at least first and second clusters, each of said first and second clusters being coupled to said interconnect and each of said first and second clusters having at least one upper level cache and at least one lower level cache, said method comprising:in a first upper level cache in said first cluster, storing a first data item in association with an address tag indicating an address and setting a first coherency indicator to a first state that indicates said address tag is valid and said first data item is invalid;in a second upper level cache in said second cluster, while said first upper level cache is storing said first data item in said first state, storing a second data item in association with an address tag indicating said address and setting a second coherency indicator to said first state to indicate that said address tag is valid and said second data item is invalid;in response to either of said first and said second upper level caches detecting a data transfer associated with said address initiated by another device in said data processing system, said data transfer including a third data item, replacing a respective one of said first and second data items in a detecting one of said first and said second upper level caches with said third data item and setting a respective one of said first and second coherency indicators to a second state in which said detecting one of said first and said second upper level caches is responsible, in its cluster, for sourcing said third data item by shared intervention to another cache in response to a request.