Patent ID: 7960245
Filing Date: 2011-06-14
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: forming one or more devices in a silicon-on-insulator substrate, said substrate comprising a buried oxide layer between an upper silicon layer and a lower silicon layer and a pre-metal dielectric layer on a top surface of said upper silicon layer; forming a first set of wiring levels over said pre-metal dielectric layer, each wiring level of said first set of wiring levels comprising electrically conductive wires in a corresponding dielectric layer, a dielectric layer of a lowermost wiring level of said first set of wiring levels in physical contact with a top surface of said pre-metal dielectric layer; removing said lower silicon layer from said substrate to expose a bottom surface of said buried oxide layer; forming electrically conductive first contacts to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of said lowermost wiring level of first set of wiring levels in electrical contact with said first contacts; forming electrically conductive second contacts to said devices, one or more of said second contacts extending from said bottom surface of said buried oxide layer to said devices; and forming a second set of wiring levels over said buried oxide layer, each wiring level of said second set of wiring levels comprising electrically conductive wires in a corresponding dielectric layer, a dielectric layer of a lowermost wiring level of said second set of wiring levels in physical contact with said bottom surface of said buried oxide layer, one or more wires of said lowermost wiring level of said second set of wiring levels in electrical contact with said second contacts.