Patent ID: 9057764
Filing Date: 2015-06-16
Classification: G01R,G06F

Abstract:
1. A computer-implemented method of detecting signals that are not checked in a verification/simulation environment of a circuit design, said method comprising: randomly selecting a simulation test signal in a plurality of simulation tests; generating, on said computer, a constant random value; forcing said simulation test signal to said constant random value for all simulation tests; performing simulation tests with said simulation test signal; after said simulation tests are complete, determining, on said computer, a set of simulation test signals whose corresponding simulation tests pass a number of times that exceeds a threshold, said determining comprising executing the plurality of simulation tests in the verification/simulation environment associated with said circuit design; and declaring, on said computer, one or more circuit verification checkers that correspond to said set of simulation test signals are suspect for being either missing or defective based on determining that the simulation tests that correspond to the set of simulation test signals pass the number of times that exceeds the threshold, the declared one or more circuit verification checkers indicating that the set of simulation test signals do not correspond to the one or more circuit verification checkers, that one or more of the circuit verification checkers is not called, or that one or more of the circuit verification checkers includes errors.