Patent ID: 8957799
Filing Date: 2015-02-17
Classification: G11C,H03M

Abstract:
1. A current memory cell, comprising: an amplifier including a first input terminal, a second input terminal and an output terminal; a transistor including a source electrode coupled to a first node, a drain electrode coupled to a ground, and a gate electrode coupled to a second node; a first capacitor coupled between the second node and the ground; a second capacitor coupled between a third node and the ground; a first switching unit configured to couple a reference current source to to the first node during a first period and couple an output line to the first node during a second period; a second switching unit configured to couple the first node to the second node during the first period; and a. third switching unit configured to couple the first input terminal of the amplifier to the second node and couple the second input terminal of the amplifier and the output terminal of the amplifier to the third node during the first period, and couple the first input terminal of the amplifier to the third node and couple the second input terminal of the amplifier and the output terminal of the amplifier to the second node during the second period.