Patent ID: 6645869
Filing Date: 2003-11-11
Classification: H01L

Abstract:
An etching back process to improve topographic planarization of a polysilicon layer, comprising steps of:providing a semiconductor substrate having two adjacent insulating structures and a contact hole formed between the two insulating structures; forming a polysilicon layer to fill the contact hole and cover the entire surface of the semiconductor substrate to a predetermined height, in which a sunken portion is formed in the polysilicon layer over the contact hole; forming a bottom antireflective coating (BARC) layer to fill the sunken portion and cover the entire surface of the polysilicon layer; performing a first etching step to completely remove the BARC layer outside the sunken portion of the polysilicon layer and retain the BARC layer in the sunken portion of the polysilicon layer to flatten the bottom of the sunken portion; performing a second etching step to decrease the etching rate of the polysilicon and increase the etching rate of the BARC layer to remove a part of the polysilicon layer outside the sunken portion and retain some of the BARC layer inside the sunken portion, in which the BARC layer remaining in the sunken portion protrudes from the polysilicon layer; and etching the polysilicon layer to completely remove the polysilicon layer outside the contact hole.