Patent ID: 6996702
Filing Date: 2006-02-07
Classification: G06F

Abstract:
1. A data processing system enabled to process instructions representing a program operable upon data in a storage device, comprising: a first address generator coupled to an address bus to provide read addresses associated with data stored in the storage device; s a second address generator coupled to the address bus to provide write addresses associated with data stored in the storage device; an arithmetic logic unit (ALU) sub-system capable of executing the instructions the ALU sub-system coupled to the storage device, the first address generator and the second address generator, the ALU sub-system including a constant generator having an input and an output, the input of the constant generator coupled to the first input of the first ALU and to the second input of the second ALU, the constant generator capable of providing feedback data based on data selected from a group of data comprising data read from the storage device and data associated with a previous instruction; a bypass element having an input and an output, the in input of the bypass element coupled to the output of the constant generator, wherein the feedback data is latched in the bypass element for subsequent retrieval; and a select element having a first input, a second input, and an output, the first input of the select element coupled to the storage device, the second it of the select element coupled to the output of the bypass element, and the output of the select element coupled to the input of the constant generator, the select element capable of selecting between data selected from a group of data comprising data read from the storage device and data associated with a previous instruction, wherein the constant generator, the bypass element and the select element are configured to manipulate feedback data to minimize memory contention by reducing a number of memory accesses.