Patent ID: 9154035
Filing Date: 2015-10-06
Classification: H01L,H02M

Abstract:
1. A circuit comprising: a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode; a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode; and a capacitor comprising a first electrode and a second electrode, wherein the first gate electrode is electrically connected to the first electrode of the capacitor, wherein one of the first source electrode and the first drain electrode is electrically connected to the second electrode of the capacitor, wherein the second gate electrode is electrically connected to one of the second source electrode and the second drain electrode, wherein the other of the second source electrode and the second drain electrode is electrically connected to the first gate electrode, wherein one of the third source electrode and the third drain electrode is electrically connected to the one of the first source electrode and the first drain electrode, wherein the other of the third source electrode and the third drain electrode is electrically connected to a power supply line, wherein the third gate electrode is electrically connected to a clock signal line, wherein the one of the second source electrode and the second drain electrode is configured to be input a first signal, wherein the first transistor includes a channel formation region comprising a first oxide semiconductor, wherein the second transistor includes a channel formation region comprising a second oxide semiconductor, and wherein an off-state current density per a channel width of 1 μm at 25° C. is less than or equal to 1×10