Patent ID: 6016276
Filing Date: 2000-01-18
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell in which one threshold value is set out of n (n is an integer of 2 or more) kinds of threshold values;a word line connected to a gate of said memory cell;a decoder for selecting said word line;a sense amplifier for amplifying an output of said memory cell;n-1 reference cells in which n-1 kind of threshold values are respectively set;n-1 reference amplifiers for amplifying each outputs of said reference cells;n-1 differential amplifiers for receiving the respective outputs of said reference amplifiers and an output of said sense amplifier;an encoder for encoding an output of said n-1 differential amplifiers; anda level shift circuit connected to said word line and supplying a voltage to gates of all said reference cells, said voltage being lower than the voltage supplied with said word line by half of adjacent threshold voltage values.