Patent ID: 7870451
Filing Date: 2011-01-11
Classification: G01R,G06F

Abstract:
1. Decode logic circuitry comprising: A. a scan clock input lead; B. select input leads; C. first scan buffer control output leads including a first scan clock output lead and a first enable buffer output lead; D. second scan buffer control output leads including a second scan clock output lead and a second enable buffer output lead; E. decode circuitry connected with the select input leads and having a first clock enable output, a second clock enable output, and the first and second enable buffer output leads; F. a first logic gate having an input connected to the scan clock input lead, an input connected to the first clock enable output, and an output connected to the first scan clock output lead; and G. a second logic gate having an input connected to the scan clock input lead, an input connected to the second clock enable output, and an output connected to the second scan clock output lead.