Patent ID: 8884338
Filing Date: 2014-11-11
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated-circuit device divided into a core region in which a plurality of cells is arranged and a peripheral region that does not include the core region, the device comprising: a plurality of memory cells arranged in a predetermined configuration on the core region; a plurality of logic cells arranged on the core region and configured to perform a variety of logical functions; and a plurality of standard cells arranged on a region excepting other regions of the core region, which are occupied by the memory cells and the logic cells, and between the logic cells and configured to connect the logic cells; wherein the plurality of standard cells each includes a single standard capacitor, wherein each respective single standard capacitor comprises an upper plate including a plurality of first contact portions and a lower plate including a plurality of second contact portions, and a gate dielectric layer interposed between the upper and lower plates; and wherein each respective single standard capacitor is configured to connect to adjacent logic cells through a well layer doped with a corresponding n or p type dopant.