Patent ID: 7795893
Filing Date: 2010-09-14
Classification: G01R

Abstract:
1. A test mode enable circuit for putting a device in a test mode comprising: a serial-to-parallel shift register including a plurality of memory circuits, each of which is initialized to a first voltage level by a reset signal, the shift register receiving and converting a control signal in serial form to control data in parallel form, the control signal comprising a plurality of digital bits, each of which has the first voltage level or a second voltage level and being shifted through the shift register from a first memory circuit of the plurality of memory circuits to a second memory circuit of the plurality of memory circuits to produce the control data, the first memory circuit corresponding to a least significant bit of the control data, the second memory circuit corresponding to a most significant bit of the control data; a decoder circuit for receiving the control data from the shift register and for outputting a test mode enable signal that puts the device in the test mode when the most significant bit of the control data has the second voltage level and at least one of other bits of the control data has a first predetermined voltage level; and a gate circuit for receiving the test mode enable signal from the decoder circuit, wherein the gate circuit passes the test mode enable signal to the device, when at least one of the bits of the control signal and the reset signal has a second predetermined voltage level.