Patent ID: 6608377
Filing Date: 2003-08-19
Classification: H01L

Abstract:
A semiconductor chip package comprising:a semiconductor chip having signal electrode pads, ground electrode pads, and on-chip circuits, with said signal electrode pads for carrying electrical signals to and from the semiconductor chip, and said ground electrode pads for carrying ground and power signals; a first dielectric layer overlying the chip and exposing the signal and the ground electrode pads; a first metal layer formed on the first dielectric layer, the first metal layer including a ground metal layer in electrical communication with the ground electrode pads, said first metal layer comprising a plate structure; a second dielectric layer formed on the first metal layer, the second dielectric layer having a ground contact opening therethrough and a signal contact opening therethrough; and a second metal layer formed on the second dielectric layer, the second metal layer having ground and signal patterns, said ground patterns electrically connected to the ground electrode pads via the ground contact opening, and said signal patterns electrically connected to the signal electrode pads via the signal contact opening.