Patent ID: 6512712
Filing Date: 2003-01-28
Classification: G11C

Abstract:
A circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit comprising:a) a precharge input; b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; c) a first delay element, the input of the first delay element coupled to the precharge input; d) a second delay element, the input of the second delay element coupled to the output of the first delay element; e) a second switch, the gate of the second switch coupled to the output of the first delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline; and f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source.