Patent ID: 8749293
Filing Date: 2014-06-10
Classification: H01L

Abstract:
1. A programmable passive device, comprising: a common bus, a second bus, and a third bus; a plurality of passive device elements comprising at least a first bank of the passive device elements and a second bank of the passive device elements each electrically coupled to the common bus, wherein the plurality of passive device elements are on-chip complimentary metal oxide semiconductor (CMOS) device elements; and a plurality of switches comprising a first subset of switches and a second subset of switches, the first subset of switches being electrically coupled to the second bus and selectively coupled to a number of the plurality of passive device elements of the first bank, the second subset of switches being electrically coupled to the third bus and selectively coupled to a number of the plurality of passive device elements of the second bank, wherein the second bus is directly connected to a first pad, the third bus is directly connected to a second pad, and the common bus is electrically connected to a third pad; the first bank of the passive device elements is connected to the second bus by a respective switch of the first subset of switches, and the second bank of the passive device elements is connected to the third bus by a respective switch of the second subset of switches; the first pad is configured to be grounded while the second pad is biased to create a capacitance configuration of a serial connection; the third pad is configured to be grounded while the first pad and the second pad are biased in order to create the capacitance configuration of a parallel connection; a capacitance value of the passive device is programmable by biasing and grounding respective ones of the first pad, the second pad, and the third pad in order to achieve the capacitance configuration of the serial connection or the parallel connection between the first bank and the second bank of the passive device elements; and the plurality of switches include an e-fuse or an anti-fuse, wherein the e-fuse is programmed to open at a first bias and the anti-fuse is programmed to close at a second bias higher than the first bias such that the plurality of switches offers a second time programmability.