Patent ID: 7443232
Filing Date: 2008-10-28
Classification: G01R,H03F,H03H

Abstract:
1. An Active load arrangement (Z) for providing output DC load to an object (TO) under AC test, the arrangement (Z) including a voltage controlled transistor (MOSFET) having a source (S), a gate (G) and a drain (D), wherein the drain (D) is associated with the gate (G) and connected to an arrangement input (I 2 ) associated with the object (TO), and the source (S) is connected to an arrangement output (O 2 ) associated with the object, the active load arrangement further comprising: a feedback arrangement connected to the source (S) and to the gate (G), for obtaining low impedance at low frequencies and high impedance at high frequencies by varying phase and amplitude of the gate-to-source voltage in accordance with variations in frequency, said feedback arrangement comprising: