Patent ID: 6455887
Filing Date: 2002-09-24
Classification: G11C,H01L

Abstract:
An FET semiconductor device formed on a doped silicon semiconductor substrate having a surface, comprising:the substrate being lightly doped with a P-type of dopant with an N-well and a P-region formed in the substrate with the N-well in side-by-side relationship with the P-region with an interface between the N-well and the P-region and with a pair of P+ doped source/drain regions formed in the N-well and a plurality of N+ doped regions formed in the P-region, a unitary gate electrode stack spanning across the N-well and the P-region over the surface of the substrate with the gate electrode stack bridging between the P+ doped source/drain regions in the N-well and the plurality of N+ doped regions in the P-region, comprising as follows: a) a tunnel oxide layer over the surface of the substrate, b) a floating gate electrode layer over the tunnel oxide layer, c) an interelectrode dielectric layer over the floating gate electrode, d) a control gate electrode over the interelectrode dielectric layer, and e) the gate electrode stack bridging between the P+ doped source/drain regions in the N-well and between the plurality of N+ doped regions in the P-region, the unitary gate electrode stack extending across the N-well between the P+ doped source/drain regions and across the N-well and the P-region between the N+ doped regions in the substrate outside of the N-well, providing a single gate electrode stack spanning across the N-well and the P-region, the plurality of N+ doped regions being formed on opposite sides of the gate electrode stack in the P-region self-aligned with the unitary gate electrode stack, a Channel Hot Electron (CHE) injector is formed including the P+ doped source/drain regions formed in the N-well self-aligned with the unitary gate electrode stack, and the unitary gate electrode stack arranged in a pattern comprising the unitary gate electrode stack being formed into a rake-shaped pattern extending between the set of P+ doped source/drain regions in the N-well and across the substrate and between the parallel array of the plurality of N+ doped regions.