Patent ID: 6430078
Filing Date: 2002-08-06
Classification: G11C

Abstract:
A digital read-only memory circuit capable of storing a plurality of addressable bits, comprising:means for selectively driving exactly one of a first and second complementary logic state signal lines substantially to a voltage reference when one of a plurality of readout signals is active, the first complementary logic state signal line indicating a first logic state, the second complementary logic state signal line indicating a second logic state, the complementary logic state signal line that is being driven indicating the logic state of the bit of the read-only memory circuit addressed by the active readout signal; first means for inverting the logic level on the first complementary logic state signal line to drive the second complementary logic state signal line; and second means for inverting the logic level on the second complementary logic state signal line to drive the first complementary logic state signal line.