Patent ID: 7403521
Filing Date: 2008-07-22
Classification: H04L

Abstract:
1. A switching apparatus comprising: a first port coupled to receive an input data frame; a first logic circuit coupled to receive the input data frame from the first port and configured to determine a number of copies of the input data frame to make and to make the number of copies of the input data frame; a first memory comprising multiple segments, each segment comprising multiple independently addressable channels, the first logic circuit configured to determine a number of channels and segments needed to store the number of copies of the input data frame, the first memory coupled to the first logic circuit and configured to store multiple copies of the input data frame within a single segment of the determined number of segments and to read the multiple copies of the input data frame from the single segment in a single read cycle; and multiple transmitting ports coupled to the first memory and configured to receive copies of the input data frame from the first memory in parallel and to simultaneously transmit the copies of the input data frame, each of the multiple transmitting ports associated with an output control logic circuit coupled to the first memory and configured to determine when to read at least one copy of the input data frame from the first memory; wherein the first logic circuit further comprises a third logic circuit configured to determine one or more empty locations in the first memory to store the copies of the input data frame.