Patent ID: 8853780
Filing Date: 2014-10-07
Classification: H01L

Abstract:
1. A device comprising: a semiconductor substrate not having a silicon-on-insulator (SOI) construction; source and drain regions in the semiconductor substrate; a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region; a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions; and a field isolation region in the semiconductor substrate on the drift region such that the field isolation region defines a field drift portion of the drift region under the field isolation region through which the charge carriers drift toward the drain region, wherein the drift region includes a current pass portion adjacent the field isolation region linking the field drift portion and the drain region; wherein the field drift portion has a lateral length of approximately 5 microns or more, wherein a PN junction along the drift region comprises a first section at the drain region and a second section not at the drain region, and wherein the drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.