Patent ID: 7579914
Filing Date: 2009-08-25
Classification: H03F

Abstract:
1. A bias circuit comprising: a first transistor having an emitter terminal grounded, a base terminal grounded via a first resistor, and a collector terminal connected to a first power supply port via a second resistor; a second transistor having an emitter terminal connected to the base terminal of the first transistor, a base terminal connected to the collector terminal of the first transistor, and a collector terminal provided with power from a second power supply port; a third transistor having an emitter terminal grounded, a base terminal connected to the base terminal of the first transistor, and a collector terminal connected to the first power supply port via a third resistor; and a fourth transistor having a base terminal connected to the collector terminal of the third transistor, and a collector terminal provided with power from a third power supply port, a current being taken out from the emitter terminal of the fourth transistor.