Patent ID: 7897434
Filing Date: 2011-03-01
Classification: H01L,Y02E,Y02P

Abstract:
1. A method, comprising: (a) forming a P-doped layer and an N-doped layer in a silicon substrate, said P-doped layer adjacent to a top surface of said substrate and said N-doped layer adjacent to a bottom surface of said substrate; (b) forming a dielectric top passivation layer on said top surface of said substrate and a dielectric bottom passivation layer on said top surface of said substrate; (c) forming an antireflective coating on said top passivation layer; (d) photolithographically forming a first set of openings through said antireflective coating and through said top passivation layer to said P-doped layer and photolithographically forming a second set of openings through said bottom passivation layer to said N-doped layer; (e) forming first metal silicide contacts to said P-doped layer and second metal silicide contacts to said N-doped layer in said first and second openings respectively; (f) forming metal contact frames on said first metal silicide contacts and metal bus bars on said second metal silicide contacts; and (g) singulating said substrate into a plurality of solar cell chips, each solar cell chip including a contact frame and a bus bar.