Patent ID: 7064453
Filing Date: 2006-06-20
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor memory device, comprising: a first driver transistor having a gate and a drain; a second driver transistor including: a first load transistor connected in series to the first driver transistor, the gate of the first load transistor being an extension of the gate of the first driver transistor; a second load transistor connected in series to the second driver transistor, the gate of the second load transistor being an extension of the gate of the second driver transistor; a first transfer gate including: a second transfer gate including: a read-out transistor connected in series to the second load transistor, the gate of the read-out transistor being a bended extension of the gate of the second load transistor, the gate of the second load transistor being L-shaped; and a recess provided in an inner corner of the gate of the second driver transistor, the second load transistor and the read-out transistor.