Patent ID: 9018745
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a die pad that has a first plane and a second plane located on the opposite side of the first plane; a plurality of leads arranged next to the die pad; a semiconductor chip that has a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface, and is mounted over a chip mounting area of the first plane of the die pad; a plurality of first wires that electrically couple one part of the electrodes of the semiconductor chip and the leads; a second wire that electrically couples the other part of the electrodes of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wires, and the second wire so that a part of each of the leads and the second plane of the die pad may be exposed, wherein an area of the first plane of the die pad is larger than an area of the reverse side of the semiconductor chip, wherein the first plane of the die pad comprises the chip mounting area, a first bonding area that is located between the chip mounting area and the leads and to which the second wire is bonded, and a first hollow part arrangement area that is arranged between the first binding area and the chip mounting area and in which a groove or a plurality of holes are formed, and wherein surface roughness of the first plane in the chip mounting area, the first bonding area, and the first hollow part arrangement area is coarser than surface roughness of the second plane.