Patent ID: 6448171
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method for fabricating a microelectronic fabrication comprising:providing a substrate; forming over the substrate a patterned bond pad layer; forming over the substrate and the patterned bond pad layer a patterned passivation layer which passivates a series of edges of the patterned bond pad layer while leaving exposed a central portion of the patterned bond pad layer, the patterned passivation layer having a series of protrusions within the patterned passivation layer over the series of edges of the patterned bond pad layer; selectively forming upon the central portion of the patterned bond pad layer and bridging over the series of protrusions of the patterned passivation layer a patterned first terminal electrode layer having an upper surface which is concave; and selectively forming directly forming upon the patterned first terminal electrode layer a patterned second terminal electrode layer having an upper surface which is other than concave; Wherein the patterned first terminal electrode layer has a first linewidth greater than a second linewidth of the patterned second terminal electrode layer.