Patent ID: 8557650
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A method for forming a gate stack of a non-volatile memory (NVM) over a semiconductor substrate having an NVM region and a non-NVM region which does not overlap the NVM region, the method comprising: forming an isolation region in the non-NVM region; forming a dummy dielectric in an area of the non-NVM region surrounded by the isolation region and forming a gate dielectric in the NVM region; after forming the dummy dielectric and the gate dielectric, forming a first conductive layer over the substrate in the NVM region and the non-NVM region; patterning the first conductive layer in the non-NVM region; after patterning the first conductive layer, forming an NVM dielectric layer over the NVM region and the non-NVM region; forming a second conductive layer over the NVM dielectric layer; forming a patterned masking layer over the second conductive layer in the NVM region and in the non-NVM region, wherein: performing an etch comprising: