Patent ID: 6784880
Filing Date: 2004-08-31
Classification: G09G,G11C

Abstract:
A method of adjusting a clock signal in an electro-optical device having a display portion, which has a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to intersections between said scanning lines and said data lines, and also having a shift register that sequentially shifts a start pulse according to a clock signal and an inverted clock signal, said electro-optical device structured to generate signals, which are supplied to said plurality of scanning lines or said plurality of data lines, according to each output signal of said shift register, said method being employed to adjust phases of the clock signal and the inverted clock signal, which are supplied to said shift register, said method comprising the steps of:detecting a threshold voltage of a transistor representative of at least one transistor of said shift register; and adjusting relative phases of the clock signal and the inverted clock signal according to the detected threshold voltage.