Patent ID: 6489191
Filing Date: 2002-12-03
Classification: H01L,Y10S

Abstract:
A method for forming a CMOS transistor gate with a self-aligned channel implant, comprising the sequential steps of:a. providing a semiconductor structure having a first active area and a second active area defined and separated by isolation regions; said first active area having a well of a first carrier type implanted therein; said second active area having a well of a second carrier type, opposite said first carrier type implanted therein; b. forming a first insulating layer on the semiconductor structure, and forming a second insulating layer on said first insulating layer; c. forming a poly reverse mask having openings over said first active area and said second active area, and patterning said second insulating layer through said openings in said poly reverse mask to form a first channel implant opening over said first active area and a second channel implant opening over said second active area; d. removing said poly reverse mask, and forming a first channel implant mask covering said second channel implant opening and exposing said first channel implant opening; e. implanting impurity ions of said first carrier type into said semiconductor structure through said first channel implant opening to form a first threshold voltage adjust region; implanting impurity ions of said first carrier type into said semiconductor structure through said first channel implant opening to form a first anti-punchthrough region; f. removing said first channel implant mask and forming a second channel implant mask covering said first channel implant opening and exposing said second channel implant opening; g. implanting impurity ions of said second carrier type into said semiconductor structure through said second channel implant opening to form a second threshold voltage adjust region; implanting impurity ions of said second carrier type into said semiconductor structure through said second channel implant opening to form a second anti-punchthrough region; removing said second channel implant mask h. forming a gate layer over said semiconductor structure and planarizing said gate layer, stopping on said second insulating layer; thereby forming gate electrodes; and i. removing second insulating layer.