Patent ID: 8499188
Filing Date: 2013-07-30
Classification: G06F

Abstract:
1. A processing device comprising: a function unit for receiving input data and performing a specific operation to the input data to generate result data; and a control unit for receiving the result data and generating an output signal; wherein the control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data; wherein the control unit compares the first data with the second data to generate a control signal; wherein when the control unit determines that the first data is not identical to the second data, the control unit provides the second data to serve as data of the output signal according to the control signal; wherein when the control unit determines that the first data is identical to the second data, the control unit confirms the first data to serve as the data of the output signal according to the control signal; wherein the second clock signal is delayed from the first clock signal by a predefined time period; and wherein the sum of the predefined time period and a cycle of the first clock signal is equal to or greater than the difference between the largest latency of the function unit and a cycle of the first clock signal.