Patent ID: 8643443
Filing Date: 2014-02-04
Classification: H03K

Abstract:
1. A comparator, comprising: first, second and third bias current transistors each having a first node coupled to a first power supply rail and each having a gate coupled to a regulating input; first and second input transistors forming a pair of parallel coupled transistors having common nodes coupled to a second node of the first bias current transistor, the first input transistor having a gate providing a comparator first input port and the second input transistor having a gate providing a comparator second input port; a first current mirror control transistor coupling the first input transistor to a second power supply rail; a first current mirror output transistor with a gate coupled to a gate of the first current mirror control transistor, wherein the first current mirror output transistor connects a second node of the second bias current transistor to the second power supply rail; a second current mirror control transistor coupling the second input transistor to the second power supply rail; a second current mirror output transistor with a gate coupled to a gate of the second current mirror control transistor, wherein the second current mirror output transistor connects a second node of the third bias current transistor to the second power supply rail; and a transition time reduction transistor coupled across the third bias current transistor such that a first node of the transition time reduction transistor is coupled to the first power supply rail and a second node of the transition time reduction transistor is coupled to the second node of the third bias current transistor, wherein a gate of the transition time reduction transistor is coupled to the second node of the second bias current transistor, and wherein the second node of the transition time reduction transistor provides an output port for the comparator.