Patent ID: 9054154
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first trench that is provided in a surface layer of a semiconductor layer of a first conductivity type; a second trench that is connected to one side wall of the first trench; a third trench that is connected to the other side wall of the first trench; a base region of a second conductivity type that is selectively formed in the surface layer of the semiconductor layer along the one side wall of the first trench at a depth that is less than the depth of the first trench; an emitter region that is formed in a surface layer of the base region so as to come into contact with the side wall of the first trench; a floating potential region of the second conductivity type that is selectively formed in the surface layer of the semiconductor layer along the other side wall of the first trench; a first insulating film that is provided along the one side wall of the first trench and an inner wall of the second trench; a second insulating film that is provided along the other side wall of the first trench and an inner wall of the third trench; a first gate electrode that is provided on the first insulating film along the one side wall of the first trench and is provided in the second trench; a shield electrode that is provided on the second insulating film along the other side wall of the first trench and is provided in the third trench; a third insulating film that fills a space between the first gate electrode and the shield electrode in the first trench; a gate runner that is an extended portion of the second trench, has a portion which is provided on the first gate electrode, and is connected to the first gate electrode; an emitter polysilicon layer that is an extended portion of the third trench, has a portion which is provided on the shield electrode, and is connected to the shield electrode; an interlayer insulating film that covers the first gate electrode, the shield electrode, the emitter region, the gate runner, and the emitter polysilicon layer; a gate pad that is provided on the interlayer insulating film and is connected to the gate runner; and an emitter electrode that is provided on the interlayer insulating film so as to be separated from the gate pad and is connected to the emitter region, the base region, and the shield electrode.