Patent ID: 6459312
Filing Date: 2002-10-01
Classification: H03K,H03L

Abstract:
A delay-locked loop comprising:a semiconductor integrated circuit comprising a circuit unit, said circuit unit comprising an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal, wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal; a phase comparator to which a reference clock and an output from the output terminal of said semiconductor integrated circuit are input; and a low-pass filter to which a phase difference resulting from comparison in said phase comparator is input; wherein an output of said lower-pass filter is input to the control terminal of said semiconductor integrated circuit.