Patent ID: 6452227
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A semiconductor memory device having a memory cell array area in which a word line and a bit line extend so as to cross each other with an insulating layer being interposed between them, and a memory cell is connected to one bit line and one word line as decided uniquely, and a peripheral circuit area including a selection transistor for said memory cell, said device comprising:a first impurity diffusion region formed under said insulating layer, to serve as said bit line; a second impurity diffusion region in the interconnecting portion between said memory cell array area and said peripheral circuit area, said second impurity diffusion region being connected to said first impurity diffusion region in the manner that said second impurity diffusion region overlaps at its one end portion with said first impurity diffusion region; and silicide layers formed on the surface of said second impurity diffusion region including the overlapping portion, and surfaces of third impurity diffusion regions to serve as the source and drain of said selection transistor.