Patent ID: 6188642
Filing Date: 2001-02-13
Classification: G11C

Abstract:
An integrated memory, comprising:a column decoder for decoding column addresses and for addressing corresponding bit lines;a first column address bus connected to said column decoder for transferring first column addresses to said column decoder;a second column address bus connected to said column decoder for transferring second column addresses to said column decoder;address input lines for receiving the first column addresses, said address input lines connected to said first column address bus for supplying the first column addresses thereto;an address counter for storing and incrementing a starting address to obtain the second column addresses, said address counter connected to said second column address bus for supplying the second column addresses thereto during a specific number of clock cycles of a clock signal applied to said address counter; anda control unit connected to said address input lines and to said address counter for loading one of the first column addresses into said address counter as the starting address;said column decoder for addressing bit lines according to the first and second column addresses received through said first and second column buses respectively.