Patent ID: 7908110
Filing Date: 2011-03-15
Classification: G01R

Abstract:
1. A test apparatus that tests a device under test, comprising: a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of the device under test; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal of the device under test, based on an offset corresponding to the count value and on a reference clock of the test apparatus; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that has an input end connected to the device under test, an input end connected to an output side of the first delay section, and an output end connected to an input side of the storage section, the phase detecting section detecting a phase difference between the first delay clock and a transition point of the output signal of the device under test, and changing the count value in a direction that decreases the phase difference; a timing comparison section that has an input end connected to the device under test and an input end connected to an output end of the clock generating section, the timing comparison section acquiring the output signal of the device under test according to a transition timing of the sampling clock; and a judging section that has an input end connected to an output end of the timing comparison section, and that judges acceptability of the output signal of the device under test by comparing the output signal acquired by the timing comparison section to an expected value.