Patent ID: 7735039
Filing Date: 2010-06-08
Classification: G06F

Abstract:
1. A computer-implemented method, comprising: selecting a first sample area in a tile-based programmable logic device (PLD); constructing a first delay table corresponding to the first sample area, wherein each entry in the first delay table includes a corresponding base delay value and a corresponding description of a route from a source pin in a source tile to a load pin in the first sample area; reading the base delay value and the description of the route from the first delay table for a specified source pin in the source tile and the load pin in the first sample area; calculating one or more delay variants based on the description of the route read from the first delay table; adding the calculated delay variants to the base delay value read from the first delay table to obtain an adjusted delay value; and outputting the adjusted delay value, wherein the reading, calculating, adding, and outputting are performed by a computer.