Patent ID: 6230257
Filing Date: 2001-05-08
Classification: G06F

Abstract:
An arithmetic logic unit that operates on full width data, comprising:full width data lines that input the full width data to the arithmetic logic unit, the data lines each including first and second input lines;a delay element coupled to one of the second input lines and having an output;a global bypass bus including a first global bypass bus and a second global bypass bus;a pair of switches, the first global bypass bus being a first input to the first switch of the pair, and one of the first input lines being a second input to the first switch of the pair, and the second global bypass bus being a first input to the second switch of the pair, and the delay element output being a second input to the second switch of the pair;a selection switch having a plurality of inputs and an output, the outputs of the pairs of switches being a first input to the selection switch, the first switch of the pair coupling the first global bypass bus to the selection switch, and the second switch of the pair coupling the second global bypass bus to the selection switch;a staggered execution logic unit having an input coupled to the output of the selection switch;a local bypass bus including a first local bypass bus and second local bypass bus, the local bypass bus receiving an output of the staggered execution logic unit and coupled as a second input to the selection switch; andsecond and third delay elements, the second delay element coupling the first local bypass bus to the first global bypass bus, the third delay element coupling the second local bypass bus to the second global bypass bus.