Patent ID: 7484079
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A pipeline data processor for performing successive subtasks of a task procedure, the pipeline comprising: a plurality of stages, each stage comprising hardware for performing a corresponding subtask and a memory location pointer being propagated among the stages, a plurality of the stages using the memory location pointer to access information for initializing the corresponding stage for performing its corresponding subtask wherein the memory location pointer points to a task frame stored in memory, the task frame comprising the information for initializing the plurality of the stages that use the memory location pointer with different portions of the task frame having the information for initializing each of the plurality of stages that uses the memory location pointer; and a pipeline timing controller controlling a plurality of predetermined delays, wherein, when one of said predetermined delays has expired, said pipeline timing controller sends a control signal to initiate at least one process within associated ones of said plurality of stages.