Patent ID: 8934310
Filing Date: 2015-01-13
Classification: G11C

Abstract:
1. An apparatus comprising a memory device, the apparatus comprising: a first sub-array of memory cells; a second sub-array of memory cells; a first bitline configured to carry signals to and from the first sub-array of memory cells; a second bitline configured to carry signals to and from the first and second sub-arrays of memory cells; a first sense amplifier configured to amplify signals from the first bitline; a sense amplifier repeater (SAR) circuit configured to amplify signals on the first bitline resulting from a process of reading from the first sub-array, the SAR circuit further comprising a second sense amplifier configured to amplify signals from the second bitline; and an isolation circuit configured to isolate the first and second sense amplifiers during a write access to the first and second sub-arrays of memory cells.