Patent ID: 6173416
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A fault tolerant computer comprising:two or more cpusets,wherein each said cpuset has a microprocessor configured to perform one or more operations,wherein in normal operation, said microprocessors are configured to perform said one or more operations identically and synchronously, andwherein each said microprocessor is configured to generate a signature signal which corresponds to said one or more operations;wherein each said signature signal is representative of a start of said one or more operations; andone or more logic circuits coupled to said cpusets,wherein said one or more logic circuits are configured to receive said signature signals of said microprocessors and to determine when said signature signals differ, andwherein when said one or more logic circuits determine that said signature signals differ, said one or more logic circuits assert one or more error signals that cause one or more of said cpusets to enter an error state.