Patent ID: 6194271
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A method for fabricating a flash memory, comprising the steps of:providing a substrate;forming a gate which is parallel to a column direction on the substrate, wherein the gate is covered by a first mask layer;performing a first doping process by using the gate as a mask to form a source/drain region in the substrate;forming a patterned, second mask layer over the substrate, wherein the second mask layer is parallel to a row direction perpendicular to the column direction, and crosses the gate;forming a block-shaped shallow trench isolation structure in the substrate exposed by the gate and the second mask layer, wherein each block-shaped shallow trench isolation structure is not connected to any other shallow trench isolation structure and wherein a portion of the substrate defined below the gate is a first active region and a portion of the substrate defined below the second mask layer is a second active region;removing the first mask layer and the second mask layer;forming a dielectric layer over the substrate;forming a conductive layer on the dielectric layer;patterning the conductive layer, the dielectric layer and the gate to form a control gate and a floating gate under the control gate, wherein the control gate is parallel to the row direction; andperforming a second doping process to form a common source/drain region in the substrate.