Patent ID: 6115805
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A method for buffering data to increase the execution speed of a plurality of non-aligned double word fetches of sequential n-bit data words from a memory system supporting single word and aligned double word data fetches, said method comprising the steps of:upon an occurrence of a first misaligned double word fetch request, reading a first data word from a designated starting location in the memory system;advancing to a next word location in memory and performing an aligned double word fetch from memory of said next word and the immediately following word;concatenating said next word to said first data word and providing a concatenated word in response to the misaligned double word fetch request;defining said next word as a previous next following word; andif a misaligned double word fetch request follows:(a) advancing two word positions in memory to a new word position;(b) performing an aligned double word fetch from said new word position and the next following word;(c) concatenating said new word to the previous next following word and providing the concatenated word in response to a most recent misaligned double word fetch request; and(d) defining a next following word as the previous next following word and returning to step (a).