Patent ID: 6260123
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A system comprising:a first-stage origin-sensitive memory access request reordering device, wherein said first-stage origin-sensitive memory access request reordering device further includes:one or more reorder and bank select engines, at least one of said one or more reorder and bank select engines associated with at least one origin of one or more memory access requests, wherein the at least one of said one or more reorder and bank select engines associated with at least one origin of one or more memory access requests further includes:one or more reorder buffers, at least one of said one or more reorder buffers associated with the at least one origin of one or more memory access requests, wherein the at least one of said one or more reorder buffers associated with the at least one origin of one or more memory access requests further includes:at least one of said one or more reorder buffers structured to receive source information, wherein said at least one of said one or more reorder buffers structured to receive source information further include:at least one of said one or more reorder buffers structured to receive at least one source informant from a group comprising an indicator of an initiator of a memory access request, an ordinal number delimiter of a memory access request, and a memory access request tag wherein the tag is selected from a group comprising a tag indicative of a speculative nature of a memory access request and a tag indicative of a priority of a memory access request, andat least one of said one or more reorder and bank select engines operably coupled to at least one of said one or more reorder buffers; anda second-stage destination-sensitive memory access request reordering device operably coupled to said first-stage origin-sensitive memory access request reordering device.