Patent ID: 9105699
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A method comprising: forming a plurality of parallel lines in an upper mask layer, the upper mask layer being over and in contact with a lower mask layer, and the lower mask layer being over a layer of conductive material of an integrated circuit, said plurality of parallel lines being separated by trenches, forming an opening dividing at least one of the plurality of parallel lines into first and second line portions separated by a space; forming spacers in said trenches on lateral sides of said first and second line portions and substantially filling at least a bottom part of said opening between the first and second line portions; removing the plurality of parallel lines along with corresponding portions of the lower mask layer below the plurality of parallel lines; removing the spacers to define a corresponding pattern in the lower mask layer, wherein the corresponding pattern in the lower mask includes a connection corresponding to the opening dividing the at least one of the plurality of parallel lines, and the connection extending perpendicularly between two adjacent lines of the corresponding pattern in the lower mask; and forming interconnection lines of said conductive material based on the pattern defined in the lower mask layer.