Patent ID: 6104656
Filing Date: 2000-08-15
Classification: G11C

Abstract:
A sense amplifier control circuit in semiconductor memory comprising:a first logic gate supplied with a pair of sense amplifier enabling bar signals which are applied to the first logic gate in order with time difference, the first logic gate generating a signal of logic value 0 when at least one of the sense amplifier enabling bar signals has logic value 1;a second logic gate generating a first NMOS sense amplifier enabling bar signal of high level when an output of the first logic gate has logic value 0 and a sense amplifier enabling bar signal has logic value 1;a third logic gate generating a first PMOS sense amplifier enabling bar signal of high level when at least one of an output of the first logic gate and a sense amplifier enabling bar signal has logic value 1;a fourth logic gate generating a signal of logic value 1 when at least one of a plurality of MAT selection bar signals has logic value 0;a fifth logic gate generating a signal of logic value 1 when the first NMOS sense amplifier enabling bar signal has logic value 0 and an output of the fourth logic gate has logic value 1;a sixth logic gate generating a signal of logic value 0 when the first PMOS sense amplifier enabling bar signal has logic value 1 and an output of the fourth logic gate has logic value 0; anda seventh logic gate generating a second PMOS sense amplifier control signal of logic value 1 when outputs of the fifth and sixth logic gates both have logic value 1.