Patent ID: 6285587
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array divided into a plurality of memory blocks;a plurality of bit lines arranged through the plurality of memory blocks;a plurality of word lines disposed through each of the memory blocks and arranged to intersect the bit lines; anda plurality of memory cell strings in each of the memory blocks, wherein each memory cell string corresponds to one of the bit lines, and wherein each memory cell string comprises a first string segment having a plurality of EEPROM cells, a second string segment having a plurality of EEPROM cells, a first select transistor configured to connect the first string segment to a corresponding bit line in response to a first select signal, a second select transistor configured to connect the first string segment to the second string segment in response to a second select signal, and a third select transistor configured to connect the second string segment to a common source line in response to a third select signal.