Patent ID: 6310379
Filing Date: 2001-10-30
Classification: H01L

Abstract:
An integrated circuit, comprising:a semiconductor substrate connected to a reference bond pad for a reference supply voltage;a first bus for a first supply voltage;a first signal bond pad for connecting to an external signal, wherein the external signal is operable at approximately a second supply voltage, wherein the second supply voltage is higher than the first supply voltage;internal circuitry connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness having a V.sub.ox-max suitable for the first supply voltage but not for the second supply voltage;ESD circuitry connected between the signal pad and the reference bond pad, wherein the ESD circuitry comprises:a first substrate region in the semiconductor substrate enclosed by a highly doped region;a first string of cascode connected MOS transistors each having gate oxide of the first thickness, each with a backgate in the first substrate region, a first source/drain connected to the signal pond pad, a last source/drain connected to the reference bond pad, and a separate control gate associated with each of the MOS transistors in the first string;a second string of cascode connected MOS transistors each having a gate oxide of the first thickness, with a first source/drain connected to the signal bond pad, a last source/drain connected to the highly doped region, and a separate control gate associated with each of the MOS transistors in the second string; andcontrol circuitry connected to the first signal bond pad and to each of the gates in the first string and the second string operable to provide a voltage pulse to each gate in the first string and to each gate in the second string in response to an ESD zap applied to the first signal bond pad.