Patent ID: 6767777
Filing Date: 2004-07-27
Classification: H01L

Abstract:
A method for manufacturing a transistor, comprising:providing a transistor assembly including a silicon based semiconductor layer with a first surface, a dielectric layer disposed on at least part of the first surface, and a gate electrode disposed on the dielectric layer, the assembly further including an insulation layer adjacent at least part of the gate electrode and a nitride spacer adjacent at least part of the insulation layer; depositing, on a portion of the first surface, a material that will react with the semiconductor layer to form a silicide portion adjacent said nitride spacer; removing the material that does not react with the portion of the first surface; etching the nitride spacer subsequent to the removing of the material that does not react with a portion of the first surface; depositing a pre-metal spacer layer adjacent at least part of the nitride spacer and over at least part of the silicide portion of the first surface; etching and removing a portion of the pre-metal spacer layer above the silicide portion to expose at least part of the silicide portion; and forming a contact with the exposed part of the silicide portion where the pre-metal spacer layer was removed.