Patent ID: 6835611
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A method for fabricating MOSFET for modifying Schottky Barrier and diminishing Carrier Injection Resistance, which comprises the steps of:a.) providing a SOI (Silicon-On-Insulator) device, which has a substrate, an insulation layer formed on said substrate, and a silicon layer formed on said insulation layer; b.) forming a MOS (Metal Oxide Semiconductor) on said SOI device in accordance with a standard process of semiconductors; c.) depositing a metal layer on said SOI device and on said MOS; and d.) reacting with said silicon layer to form a metal-silicide layer by a metal self-aligned process, and to form a high-density source region and a high-density drain region by a implant-to-silicide process for modifying Schottky Barrier and diminishing Carrier Injection Resistance.