Patent ID: 9158363
Filing Date: 2015-10-13
Classification: G06F,Y02D

Abstract:
1. A system-on-chip (SoC) comprising: a plurality of resources formed on a single semiconductor die, at least some of the plurality of resources of an independent power domain; an interconnect of the single semiconductor die having a first fabric to communicate with the plurality of resources; and a power management unit (PMU) of the single semiconductor die to implement a power management protocol across the plurality of resources independent of an operating system (OS), the PMU to send a first link handshake signal to a first resource coupled to the PMU, the first link handshake signal to request entry into an intermediate power saving state for the first resource and receive a second link handshake signal from the first resource to acknowledge the request, wherein the power management protocol is to enable the intermediate power saving state between consecutive device power states of an OS-driven power management system.