Patent ID: 9153434
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A method for forming an integrated circuit comprising: forming a first active layer with a first signal processing circuit in a semiconductor wafer; forming an insulator layer on the semiconductor wafer; planarizing the insulator layer to expose a first metal surface coplanar with the insulator layer; forming a handle wafer comprising a substrate layer, a second active layer, a second metal surface, and a trap rich layer for the integrated circuit; and bonding the handle wafer to the semiconductor wafer to create a bonded structure comprising a metal-to-metal bond between the first and second metal surfaces that provides an electrical connection between the first signal processing circuit and a second signal processing circuit in the second active layer in the handle wafer; wherein, in the bonded structure, the trap rich layer is between the substrate layer of the handle wafer and the first active layer in the semiconductor wafer.