Patent ID: 6621736
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A method of programming a memory array, the memory array having:a plurality of memory cells formed in rows and columns, each memory cell having a source region, a drain region, a floating gate, and a control gate formed over the floating gate, a first row of cells having a to-be-programmed memory cell, a second row of cells having a first not-to-be programmed memory cell; a plurality of source lines formed such that each source line is connected to each source region in two adjacent rows of cells, a source line being connected to each source region in the first and second rows of cells; a plurality of bit lines formed such that each bit line is connected to each drain region in a column of drain regions, a bit line being connected to the drain region of the to-be-programmed memory cell and the drain region of the first not to-be-programmed memory cell; a plurality of word lines formed such that each word line is connected to each control gate in a row of memory cells, a first word line being connected to each control gate in the first row of memory cells, a second word line being connected to each control gate in the second row of memory cells, the method comprising the steps of: placing a source voltage on the source line connected to each source region in the first and second rows of cells; placing a first bit voltage on the bit line connected to the drain region of the to-be-programmed memory cell and the drain region of the first not to-be-programmed memory cell; placing a word voltage on the first word line; and placing an inhibiting voltage on the second word line, the inhibiting voltage being greater than zero and less than the word voltage.