Patent ID: 6330661
Filing Date: 2001-12-11
Classification: G06F

Abstract:
A register content inheriting system in a multi-processor having a plurality of program counters, each said program counter corresponding to a logical register accessible by software, said multi-processor having a plurality of thread execution units simultaneously fetching, decoding and executing a plurality of threads according to said plurality of program counters, said register content inheriting system comprising:a physical common register file common between respective of said plurality of thread execution units and comprising a plurality of physical registers;a conversion mapping table for each of said plurality of thread execution units defining a mapping relationship between each logical register in said thread execution unit and a particular one of said plurality of physical registers in said physical common register file; anda data bus interconnecting said thread execution units for copying information of said conversion table of each of said plurality of thread execution units to an adjacent thread execution unit, whereinsaid plurality of physical registers is categorized into a plurality of groups to define said mapping relationship for each said logical register, and whereininformation indicating said group classification is part of the information of said conversion mapping table for defining said mapping relationship.