Patent ID: 8232554
Filing Date: 2012-07-31
Classification: G02F,H01L

Abstract:
1. A transistor array substrate, comprising: a substrate, having at least one panel region and a peripheral circuit region surrounding the panel region, wherein the panel region has a pair of first edges and a pair of second edges, and the first edges are connected between the second edges; a plurality of pads, disposed in the peripheral circuit region; a plurality of shorting bars, disposed in the peripheral circuit region, and connected to the pads; at least one pixel array, disposed in the panel region; a plurality of first wires, disposed in the panel region, and electrically connected to the pixel array, wherein the first wires are connected to a part of the shorting bars through one first edge; a plurality of second wires, disposed in the panel region, and electrically connected to the pixel array, wherein the second wires are connected to the other shorting bars through at least one second edge; and a plurality of source controllers disposed in the panel region and connected to the first wires, wherein the source controllers are located between the pixel array and one of the first edges.