Patent ID: 7145822
Filing Date: 2006-12-05
Classification: G11C

Abstract:
1. A memory subsystem, comprising: a column comprising: a column select signal line operable to provide a column select signal selecting the column for a write operation; a precharge signal line operable to communicate a precharge signal to the read/write circuit; wherein the write precharge circuit is gated with the column select signal line such that the column select signal is communicated to the write precharge circuit upon selection of the column for the write operation and is further operable to at least partially restore the charge on the at least one bit line upon receipt of the column select signal after the write operation; wherein the read/write precharge circuit is operable to at least partially restore the charge on the at least one bit line upon receipt of the precharge signal after the write operation; a pulse generator in communication with the write precharge circuit, wherein the pulse generator has the column select signal as an only input signal and the pulse generator is operable to convert the column select signal to a pulse having a length such that a charge associated with the write precharge circuit is restored.