Patent ID: 7186605
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. A method of fabricating gates, comprising: forming, on a substrate, a first sacrificial layer having a first gate opening and a second gate opening therein; forming a gate dielectric layer on the substrate exposed by the first sacrificial layer; filling a second sacrificial layer in the first gate opening and the second gate opening; removing the second sacrificial layer in the first gate opening; filling a first conductive layer in the first gate opening as a first gate of a first MOS transistor of a first conductivity type; removing the second sacrificial layer in the second gate opening; filling a second conductive layer in the second gate opening as a second gate of a second MOS transistor of a second conductivity type; and removing the first sacrificial layer to expose the gate dielectric layer on the sidewalls of the first and second gates.