Patent ID: 9032004
Filing Date: 2015-05-12
Classification: G06F

Abstract:
1. A system comprising: a processor comprising a register file including a first packed data register and a second packed data register, a decoder to decode a first instruction, scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution, and execution logic coupled to the decoder and the scheduling logic, wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of first packed signed data elements to a plurality of unsigned results, wherein the plurality of first packed signed data elements from the first packed data register is converted to the plurality of unsigned results, the unsigned results are saturated and stored in the second packed data register, and each of the first packed signed data elements has a first number of bits, each of the unsigned results has a second number of bits, and the second number of bits is one half the first number of bits; a memory controller coupled to the processor, wherein the memory controller is integral with the processor; a communication interface to a wireless network, the communication interface coupled to the processor; and a graphics interface to a display, the graphics interface coupled to the processor.