Patent ID: 7298179
Filing Date: 2007-11-20
Classification: G06F,H04J

Abstract:
1. A digital clock switching circuit operable to deadlock-free switch the source of the digital clock for an integrated circuit, comprising: a first finite state machine associated with a first clock source; a second finite state machine associated with a second clock source, wherein the first and second finite state machines are connected to each other and configured to monitor a current state of the other finite state machine, and wherein each finite state machine comprises an input configured to receive an input select signal that is configured to control which of the first and second clock sources should be active and passed to a clock output of the digital clock switching circuit, and wherein each of the first and second finite state machines comprises a counter with a variable associated therewith, wherein the counter of the finite state machine associated with the active clock source at an instant in time is configured to initialize the variable of its respective counter to a first predetermined value when the input select signal indicates a switching off of the active clock source, and wherein the finite state machine associated with the active clock source is configured to enter a CHECK state in response thereto, wherein the respective counter increments or decrements the variable at each clock cycle, and if the other finite state machine verifies a presence of its clock source before the variable reaches a second predetermined value, the switch of the active clock source is effected, and if the variable reaches the second predetermined value, no switch of the active clock source is effected.