Patent ID: 6128716
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A memory controller with continuous page mode, comprising:an address input terminal adapted to be coupled to an address portion of a pipelined bus;a register having an input terminal coupled to said address input terminal, a control input terminal for receiving a first control signal which when active indicates a start of a transfer, and an output terminal, wherein said register stores a value at said input terminal in response to an activation of said first control signal;a comparator having a first input terminal coupled to said output terminal of said register, a second input terminal coupled to said address portion of said pipelined bus, and an output terminal for providing a page hit signal; anda state machine having a first input terminal for receiving said page hit signal, a second input terminal for receiving a second control signal which when active indicates that a next address is valid on said address portion of said pipelined bus prior to a completion of a first access, and an output terminal coupled to a control portion of an external bus, said state machine controlling said first access on said external bus by activating at least one external control signal, and subsequently initiating a precharge on said external bus by deactivating said at least one external control signal during said first access, either in response to a deactivation of said second control signal during said first access or to a deactivation of said page hit signal when said second control signal is active.