Patent ID: 7505307
Filing Date: 2009-03-17
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a word line extending in a first direction; first, second and third bit lines extending in a second direction crossing the first direction; a first cell unit comprised a first resistance change element and a first switch element connected serially between the first and second bit lines, a control terminal of the first switch element being connected to the word line; a second cell unit comprised a second resistance change element and a second switch element connected serially between the first and third bit lines, a control terminal of the second switch element being connected to the word line; and a controller which executes write to the first resistance change element under the condition that the word line is made active and potentials of the first and third bit lines are equalized, and executes write to the second resistance change element under the condition that the word line is made active and potentials of the first and second bit lines are equalized.