Patent ID: 8124447
Filing Date: 2012-02-28
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor package, comprising: providing a metal carrier plate having an upper surface and a lower surface and a first metal layer on the upper surface of the metal carrier plate and a second metal layer on the lower surface of the metal carrier plate, wherein the upper surface of the metal carrier plate is patterned by a first etching process to form at least an accommodating cavity and a plurality of first openings using the first metal layer as a mask, and the lower surface of the metal carrier plate is patterned by a pre-cutting process to form a plurality of pre-cut openings; providing a chip to the accommodating cavity of the metal carrier plate; forming a plurality of wires between the chip and the first metal layer; forming a package body over the metal carrier plate to encapsulate the chip, the wires, the first metal layer, and filling the accommodating cavity and the first openings; and performing a second etching process to the lower surface of the metal carrier plate using the second metal layer on the lower surface of the metal carrier plate as an etching mask to form a plurality of second openings by etching through the pre-cut openings and further etching through the metal carrier plate until the package body filled inside the first openings is exposed, so as to form a plurality of leads and a die pad.