Patent ID: 6551887
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A method of forming a spacer in a semiconductor device, comprising:forming a gate pattern on a semiconductor substrate; forming a first insulation layer over substantially an entire surface of the semiconductor substrate where the gate pattern is formed; forming a second insulation layer on the first insulation layer under a first pressure; forming a third insulation layer on the second insulation layer under a second pressure higher than the first pressure; sequentially anisotropically etching the third and second insulation layers to form a spacer and a second insulation pattern, and to expose the first insulation layer; removing the spacer by using an etch recipe having an etch selectivity with respect to the second insulation pattern, to expose the second insulation pattern; and etching the first insulation layer until the semiconductor substrate is exposed, to form a first insulation pattern.