Patent ID: 6586921
Filing Date: 2003-07-01
Classification: G01R

Abstract:
A method for testing current flowing through a circuit node of a circuit under test, the circuit under test including drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing, and including a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the method comprising the steps of:(a) driving the circuit node to a known voltage, via the drive circuitry that drives the circuit node; (b) causing a signal transition at the circuit node via the drive circuitry; (c) sampling a logic value of a voltage of the circuit node, via the logic circuit, at a predetermined time interval after the beginning of the signal transition, the time interval being less than an expected signal transition time and being proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node; and (d) passing or failing the test, based on the logic value sampled by the logic circuit during the signal transition.