Patent ID: 7646325
Filing Date: 2010-01-12
Classification: H03M

Abstract:
1. A method of forming an analog to digital converter comprising: coupling an analog input to an input terminal of a cascade of at least one integrator; coupling an output of the cascade of at least one integrator to an input of a quantizer, the quantizer being configured to provide a digital output signal on a quantizer output; coupling an input of a switched capacitor digital to analog converter to the quantizer output; coupling an output of the switched capacitor digital to analog converter to the input terminal of the cascade of at least one integrator; and coupling a charge clock output of a clock generator and a discharge clock output of the clock generator to the switched capacitor digital to analog converter, wherein the clock generator is configured to produce a charge clock signal on the charge clock output and a discharge clock signal on the discharge clock output to charge and discharge the switched capacitor analog to digital converter, the charge clock signal and the discharge clock signal having a same clock cycle but different asymmetric duty cycles such that the charge clock signal has a charging signal that is shorter than 50% of the clock cycle and the discharge clock signal has a discharging signal longer than 50% of the clock cycle.