Patent ID: 6373138
Filing Date: 2002-04-16
Classification: H01L

Abstract:
An integrated circuit comprising:a semiconductor substrate; a plurality of silicon-comprising active areas disposed overlying said semiconductor substrate, each active area having an outer surface; a grid of isolation regions, said grid disposed between and operably isolating at least one active area of said plurality of active areas from another active area of said plurality, said grid of isolation regions having a lower portion disposed within said semiconductor substrate, elevationally below said outer surface; a conductive region disposed within at least one active area, said conductive region having a conductive surface coincident with said outer surface; a first conductive material disposed within the lower portion of at least some of said grid of isolation regions to form a grid of first conductive material, said grid of first conductive material having a conductive upper surface essentially coplanar with said conductive surface; and a second conductive material region disposed elevationally above said grid of first conductive material and said conductive surface, said second conductive material electrically coupling said first conductive material and said conductive region.