Patent ID: 9215106
Filing Date: 2015-12-15
Classification: H03H,H03M,H04L

Abstract:
1. A receiver, comprising: a first set of time-interleaved track-and-hold circuits configured to sample an input signal according to a first set of phase-shifted clock signals; a first estimation module configured to estimate a value held at each of the first set of time-interleaved track-and-hold circuits to produce a first set of estimated data bits; a second set of time-interleaved track-and-hold circuits configured to sample the input signal according to a second set of phase-shifted clock signals, wherein the second set of phase-shifted clock signals is the first set of phase-shifted clock signals shifted by a predetermined phase shift unit; and a second estimation module configured to produce a second set of estimated data bits based on a value held at each of the second set of time-interleaved track-and-hold circuits, the first set of estimated data bits and at least one pre-cursor coefficient.