Patent ID: 8922018
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A semiconductor device manufacturing method comprising: forming a first interlayer insulating film on a semiconductor substrate; forming a high-melting-point conductive layer on the first interlayer insulating film; fabricating the high-melting-point conductive layer to have an interconnect pattern; after fabricating the high-melting-point conductive layer to have the interconnect pattern, subjecting exposed side surfaces of the fabricated high-melting-point conductive layer having the interconnect pattern to a first heat treatment in a reduction atmosphere to remove a native oxide film on the exposed side surfaces of the fabricated high-melting-point conductive layer by a reduction treatment; subjecting the fabricated high-melting-point conductive layer to a second heat treatment in a reactive gas atmosphere to form a barrier film on the exposed side surfaces of the high-melting-point conductive layer, the barrier film including a compound of a contained element in the high-melting-point conductive layer; and forming a second interlayer insulating film covering the high-melting-point conductive layer, wherein a first metal element as the contained element in the high-melting-point conductive layer is at least one element selected from the group including Mo, W, Ru, Ta, Co, and Ni.