Patent ID: 9159919
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A method for fabricating a variable resistance memory device, comprising: alternately stacking a plurality of first interlayer dielectric layers and a plurality of first sacrificial layers on a substrate; defining first trenches which extend across the first interlayer dielectric layers and the first sacrificial layers in one direction; forming a first dielectric layer in the first trenches; defining second trenches which extend across the first interlayer dielectric layers and the first sacrificial layers in the same direction as the first trenches, on both sides of the first trenches; removing the first sacrificial layers which are exposed through the second trenches; forming first horizontal electrodes in spaces generated by removal of the first sacrificial layers; selectively etching the first dielectric layer and defining first holes which expose the first horizontal electrodes and the substrate; and sequentially forming a first variable resistance layer and first vertical electrodes along sidewalls of the first holes.