Patent ID: 8330509
Filing Date: 2012-12-11
Classification: H03L

Abstract:
1. A noise suppression circuit in a phased locked-loop, comprising: a frequency up-converter configured to receive a feedback signal from an output of the phase-locked loop and a reference signal, to selectively perform frequency conversion of a frequency at which a phase difference between the feedback signal and the reference signal changes from a first frequency range to a second frequency range, and to generate a first output signal and a second output signal having the phase difference that varies at the second frequency range; and a phase detector configured to receive the first and second output signals from the up-converter, to measure the phase difference, and to generate an error signal proportional to the measured phase difference, wherein flicker noise, produced by the phase detector during measurement of the phase difference is output in the error signal at the first frequency range, so as to be distinguishable from the phase difference, which is output in the error signal at the second frequency range.