Patent ID: 8952741
Filing Date: 2015-02-10
Classification: H03K

Abstract:
1. A level shifter, comprising: an input stage circuit, receiving a first input signal and a second input signal, wherein the voltage levels of the first input signal and the second input signal are in an input level section, and the first input signal and the second input signal are out-of-phase; a latch circuit, coupled to the input stage circuit through a first output terminal and a second output terminal, the latch circuit and the input stage circuit determining the steady-state levels of the first output terminal and the second output terminal according to the first input signal and the second input signal, wherein the voltage levels of the first output terminal and the second output terminal are in an output level section, which is defined by a voltage on an output reference voltage terminal and a voltage on the ground terminal; and a transient speed-up circuit, coupled to the first output terminal and the second output terminal, when the transient speed-up circuit determines the first output terminal and the second output terminal being at the same logic level, the transient speed-up circuit accelerates the transient speed of the first output terminal or the second output terminal, wherein the transient speed-up circuit comprises: wherein a delay time between the second input terminal of the first OR gate and the output terminal of the first OR gate is larger than that between the first input terminal of the first OR gate and the output terminal of the first OR gate, and a delay time between the second input terminal of the second OR gate and the output terminal of the second OR gate is larger than that between the first input terminal of the second OR gate and the output terminal of the second OR gate.