Patent ID: 7007251
Filing Date: 2006-02-28
Classification: G01R,G06F

Abstract:
1. A system for providing coverage analysis of fractional verification of integrated circuit designs comprising: a) a test specification generator that receives feedback from simulation traces database mining, test program database mining, and coverage database wining modules and generates machine readable test attribute specifications based on said feedback; b) a test generator that creates test programs using machine readable test attribute specifications, wherein the test programs are developed by the test generator based on specifications that are received from said test specification generator; c) a simulator that compares the test programs against design model simulations; d) a database containing traces of simulations generated by a functional verification; e) a program for mining and analyzing the simulation traces database; f) a database of all test programs generated by the test generator, and by designers and verification engineers; g) a program for mining and analyzing the test programs database; h) a database of analysis logs and traces and coverage model results; i) a program for mining and analyzing the functional coverage database; j) a program for analysis and monitoring of coverage models; k) a program for automatic test spec generation from design HDL; l) a program for test spec adjustment and optimization; m) a program for creating architectural and microarchitectural coverage models of the test programs; and n) functional coverage database for storage of the created architectural and microarchitectural coverage models.