Patent ID: 6734494
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A vertical field effect transistor comprising:a drain region including a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on said drain region and located adjacent to said drain region; a source region of a first conductivity type located within said base region and formed in a surface portion of said base region; a trench penetrating said base region and said source region to reach a part of said drain region, and extending in longitudinal and lateral directions in order to divide said base region and said source region into individual base regions and individual source regions; a gate insulating film formed on a surface of said trench; a gate electrode formed within said trench while interposing said gate insulating film between said gate electrode and said surface of said trench; and a base contact region located at a central portion of a region surrounded by said trench and apart from said source region, and formed deeper said base region, and further, having a higher dopant concentration than said base region, wherein said transistor being further constructed such that when assuming a distance between a bottom and a top of said trench in a depth direction of said trench, a distance between a bottom and a top of said base region in a depth direction of said base region, and a distance between a bottom and a top of said base contact region in a depth direction of said base contact region are X.sub.a, X.sub.b and X.sub.c, respectively, said trench, said base region and said base contact region are formed so as to satisfy following mathematical relationships: X.sub.bX.sub.b(2.times.X.sub.aâˆ’X.sub.b).