Patent ID: 9159443
Filing Date: 2015-10-13
Classification: G11C,H01L

Abstract:
1. A method of operating a non-volatile memory device including a plurality of cell strings connected to a bit line, each cell string having at least one ground selection transistor, a plurality of memory cells and at least one string selection transistor stacked sequentially from a substrate in a direction perpendicular to the substrate, ground selection transistors of the plurality of cell strings being connected to a ground selection line in common, string selection transistors of the plurality of cell strings being connected to a plurality of string selection lines respectively, and memory cells having the same height from the substrate being connected to a word line in common, the method comprising: performing an erasing operation to memory cells of the plurality of cell strings; verifying first memory cells associated with a first string selection line of the plurality of string selection lines; and verifying second memory cells associated with a second string selection line of the plurality of string selection lines subsequent to verifying the first memory cells.