Patent ID: 6301655
Filing Date: 2001-10-09
Classification: G06F

Abstract:
An asynchronous system, comprising:a processor, which operates asynchronously, without common clock;an exception handler, handling exceptions without synchronizing to a clock, said exception handler including an asynchronous circuit coupled between a program counter unit and a write-back unit of said processor to inform said write-back unit of an identity of an instruction associated with an exception and to communicate an exception handling command from said write-back unit to said program counter unit to handle said exception;first and second signal wires coupled between said asynchronous circuit and said write-back unit, said first signal wire operable to send a request to said write-back unit in response to a command from said program counter unit and said second signal wire operable to send an acknowledgement from said write-back unit to said program counter unit;a query signal wire coupled between said asynchronous circuit and said program counter unit and operable to transmit a query signal from said program counter unit as to whether an exception value is pending; andfirst and second query response signal wires coupled between said asynchronous circuit and said program counter unit to transmit responses to said query signal to said program counter unit.