Patent ID: 9191243
Filing Date: 2015-11-17
Classification: H03K,H04L

Abstract:
1. An integrated circuit comprising: a reference node operable to receive a first reference; a resistor operable to exhibit an adjustable impedance to current flow responsive to an impedance-control signal; a comparator having a first input coupled to the reference node to receive the first reference, a second input coupled to the resistor, and a comparator output; a transistor disposed in series with the resistor between the second input and a supply terminal, the transistor operable to disable the current flow through the resistor; a counter operatively disposed between the comparator output and the resistor, the counter operable to update the impedance-control signal responsive to the comparator output; wherein the counter is operatively coupled between the comparator and the resistor via a latch, the latch to capture the signal from the comparator output; adjustable termination elements each having a control port coupled to the counter; and a differential amplifier operable to receive a pair of complementary signals via respective first and second signal pads, and wherein each of the signal pads is coupled to a DC voltage via a respective one of the adjustable termination elements.