Patent ID: 7246268
Filing Date: 2007-07-17
Classification: G06F,G11C

Abstract:
1. A memory system for storing information, the memory system comprising: a first plurality of spare units of erase on a first chip; a second plurality of spare units of erase on a second chip; a first storage element on the first chip, the first storage element containing a first counter and a first threshold, the first counter indicating a number of spare units of erase on the first chip which have not yet been reassigned; a second storage element on the second chip; the second storage element containing a second counter and a second threshold, the second counter indicating a number of spare units of erase on the second chip which have not yet been reassigned; a controller, the controller updating the first counter each time a spare unit of erase of the first plurality of spare units of erase is reassigned, the controller comparing the first counter to the first threshold value, the controller updating the second counter each time a spare unit of erase of the second plurality of spare units of erase is reassigned, the controller comparing the second counter to the second threshold value, the controller generating an end-of-life indicator when either the first counter reaches the first threshold or the second counter reaches the second threshold; and wherein the memory system operates in conjunction with a host system and the controller reassigns a spare unit of erase in response to a request from the host system.