Patent ID: 7915055
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device, including: a plurality of processing steps of working a semiconductor device, said plurality of processing steps including at least a step of film depositing and a step of lithography, and a plurality of examining steps of examining results of working at the processing steps, said plurality of examining steps including examining a plurality of layers formed in said plurality of processing steps, the method further comprising: a step of collecting examination data generated at the examining of the plurality of layers; a step of analyzing the examination data for the plurality of layers; a step of generating a prediction model of a parameter from the examination data of the plurality of layers to at least one parameter previous to lithography of discriminating parameters of the semiconductor device; a step of utilizing, as a control process, at least one processing step of the plurality of processing steps to generate a control model for determining at least one set value of a processing condition for the control process in order to stabilize the parameters of the semiconductor device; a step of calculating a set value of the processing condition for the control process from the examination data of the plurality of layers based upon the control model; a step of changing the processing condition for the control process based upon the calculated set value; and a step of examining a wire width, wherein an average value of local line widths, in a lateral direction of the wiring, within a measurement region having a length in a wiring direction set to be 1 μm or more and 6 μm or less, is measured as a measurement result with respect to a wiring having a wiring width of 100 nm or less from an image obtained by a Critical Dimension-Scanning Electron Microscope (CD-SEM) at a magnification of 150,000 times or less in a length direction of the wiring.