Patent ID: 6211711
Filing Date: 2001-04-03
Classification: G01R

Abstract:
An activation signal generating circuit for generating an activation signal from a periodic clock signal the activation signal being selectively supplied as a clock signal to a circuit under test in a normal operating mode based on a normal mode control signal, and being selectively supplied as a scan test signal to clock inputs of flip-flops of the circuit under test in a test mode based on a test mode control signal said activation signal generating circuit comprising:a combinational logic circuit that receives the normal mode control signal and the test mode control signal; anda switch that receives the periodic clock signal, the switch being controlled by the output of the combinational logic circuit,wherein the combinational logic circuit controls the switch such that the switch selectively transfers the periodic clock signal as the activation signal based on the output of the combinational logic circuit, andthe switch is a CMOS change-over switch having two complementary MOS transistors connected in parallel, the two transistors being controlled by complementary signals.