Patent ID: 8072803
Filing Date: 2011-12-06
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a substrate having a plurality of trenches formed therein, wherein the trenches comprise sloped sidewalls; a conductive layer, disposed on the substrate and filling the trenches; a charge storage layer, disposed between the substrate and the conductive layer; a plurality of first doped regions, configured in the substrate adjacent to both sides of an upper portion of each trench respectively, wherein the first doped regions between the neighbouring trenches are separated from each other; a plurality of second doped regions, configured in the substrate under bottoms of the trenches respectively, wherein the second doped regions and the first doped regions are separated from each other, such that each memory cell comprises six physical bits; and a well region, configured in the substrate, wherein a dopant concentration distributed over the well region varies with a depth of the substrate.