Patent ID: 6348821
Filing Date: 2002-02-19
Classification: H03K

Abstract:
A frequency doubler circuit having a 50% duty cycle output comprising:a logic gate including a first input receiving a digital input signal having a first frequency and a 50% duty cycle, and a second input receiving a replica signal of the digital input signal, the replica signal being delayed by a quarter of a period of the digital input signal and having the 50% duty cycle; at least one capacitor; a current generator for charging said at least one capacitor during one of two half periods of the digital input signal; first and second switch circuits controlled in phase opposition for charging and discharging said at least one capacitor during each period of the digital input signal; a voltage dividing circuit dividing in half a voltage present on said at least one capacitor; and at least one comparator having a first input for sensing the halved voltage present on the at least one capacitor and a second input for receiving the digital input signal, and having an output coupled to the second input of said logic gate providing the replica signal.