Patent ID: 6829571
Filing Date: 2004-12-07
Classification: G06F

Abstract:
A method of determining a DC margin of a latch of a circuit, the circuit including one or more circuit elements, and the latch including a plurality of signal paths for gassing signals through the one or more circuit elements, the method comprising:determining a worst case pull-up path and a worst case pull-down path analytically by accumulating a weighted resistance of each circuit element along the plurality of signal paths, wherein weights assigned to the circuit elements are empirically determined based on a topology configuration of each of the circuit elements, and wherein the topology configuration includes one or more of a type of the circuit elements, the signals being passed through the circuit elements, and whether a threshold voltage drop occurs between a drive circuit element and a pass circuit element; performing a first simulation using a first simulation circuit to determine a trip voltage of a forward inverter of said latch; performing a second simulation using a second simulation circuit to determine a one margin of said latch, said second simulation circuit comprising the worst case pull-up signal path; and performing a third simulation using a third simulation circuit to determine a zero margin of said latch, said third simulation circuit comprising the worst case pull-down signal path.