Patent ID: 6458705
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method for forming via-first dual damascene interconnect structure, said method comprising:providing a substrate with a conductive structure and a dielectric layer on said substrate, wherein said dielectric layer having a first opening to expose said conductive structure; filling said first opening with a gap-filling material to form a gap-filling layer on said dielectric layer, wherein said gap-filling material is dissolved in a developer; planarizing said gap-filling layer to expose said dielectric layer; forming a bottom-anti-reflective coating layer on said dielectric layer and said gap-filling layer; forming a patterned photoresist on said bottom-anti-reflective coating layer, wherein said patterned photoresist defines a second opening and said second opening is on said first opening; etching said bottom-anti-reflective coating layer to expose said dielectric layer by using said patterned photoresist as a mask; removing a portion of said gap-filling layer to a first depth; etching said dielectric layer to about said first depth to form said second opening in said dielectric layer by using said patterned photoresist as a mask; removing said patterned photoresist, said bottom-anti-reflective coating layer, and remaining said gap-filling layer; and filling said first opening and said second opening with a conductive material to form a conductive layer.