Patent ID: 6502050
Filing Date: 2002-12-31
Classification: H03L

Abstract:
A method of testing a lock frequency of a delay locked loop (DLL) under test, comprising:configuring a first DLL as a ring oscillator (RO) having an RO output signal; providing the RO output signal to the DLL under test, where the DLL under test has a lock output signal, the lock output signal having a locked state and an unlocked state; keeping a first count of a clock signal; keeping a second count of the RO output signal; monitoring the lock output signal; if the lock output signal is in the unlocked state: resetting the first count and the second count; running the RO for a predetermined period of time; reading the first count and the second count; and computing the lock frequency from the first count and the second count; and if the lock output signal is in the locked state: decrementing a frequency of the RO output signal; and returning to monitoring the lock output signal.