Patent ID: 8330524
Filing Date: 2012-12-11
Classification: H03K

Abstract:
1. A semiconductor integrated circuit comprising: a first I/O port configured to be coupled to a first port of a diplexer coupled to an antenna; a first transmitter port configured to be coupled to a first transmitter that transmits to the antenna a first radio frequency transmission signal having a first frequency band; a first receiver port configured to be coupled to a first receiver that receives from the antenna a first radio frequency reception signal having the first frequency band; a first antenna switch coupled to the first I/O port, the first transmitter port, and the first receiver port, and controlling bi-directional transmission of first radio frequency signals including the first radio frequency transmission signal and the first radio frequency reception signal; a second I/O port configured to be coupled to a second port of the diplexer; a second transmitter port configured to be coupled to a second transmitter that transmits to the antenna a second radio frequency transmission signal having a second frequency band higher than the first frequency band; a second receiver port configured to be coupled to a second receiver that receives from the antenna a second radio frequency reception signal having the second frequency band; and a second antenna switch coupled to the second I/O port, the second transmitter port, and the second receiver port, and controlling bi-directional transmission of second radio frequency signals including the second radio frequency transmission signal and the second radio frequency reception signal, wherein the first antenna switch comprises a first bias generation circuit, a first transmitter switch, and a first receiver switch, wherein the first transmitter switch is coupled between the first transmitter port and the first I/O port, and an on/off state of a first transmitter field effect transistor of the first transmitter switch is controlled according to a level of a first transmitter control bias signal supplied to a first transmitter control port, wherein the first receiver switch is coupled between the first I/O port and the first receiver port, and an on/off state of a first receiver field effect transistor of the first receiver switch is controlled according to a level of a first receiver control bias signal supplied to a first receiver control port, wherein a first radio frequency signal input port of the first bias generation circuit is coupled to the first transmitter port, wherein a part of the first radio frequency transmission signal supplied to the first radio frequency signal input port is rectified by the first bias generation circuit so that a first negative DC output bias signal is generated and output from a first DC output port of the first bias generation circuit, wherein the first negative DC output bias signal output from the first DC output port is supplied to a first gate control port of the first receiver field effect transistor of the first receiver switch, wherein the second antenna switch comprises a second bias generation circuit, a second transmitter switch, and a second receiver switch, wherein the second transmitter switch is coupled between the second transmitter port and the second I/O port, and an on/off state of a second transmitter field effect transistor of the second transmitter switch is controlled according to a level of a second transmitter control bias signal supplied to a second transmitter control port, wherein the second receiver switch is coupled between the second I/O port and the second receiver port, and an on/off state of a second receiver field effect transistor of the second receiver switch is controlled according to a level of a second receiver control bias signal supplied to a second receiver control port, wherein a second radio frequency signal input port of the second bias generation circuit is coupled to the second transmitter port, wherein a part of the second radio frequency transmission signal supplied to the second radio frequency signal input port is rectified by the second bias generation circuit so that a second negative DC output bias signal is generated and output from a second DC output port of the second bias generation circuit, and wherein the second negative DC output bias signal output from the second DC output port is supplied to a second gate control port of the second receiver field effect transistor of the second receiver switch.