Patent ID: 9071230
Filing Date: 2015-06-30
Classification: G09G,G11C,H03K

Abstract:
1. A gate driving circuit comprising: a pull-up control part configured to apply a carry signal of a previous stage to a first node in response to the carry signal of the previous stage; a pull-up part configured to output a clock signal as an N-th gate output signal in response to a signal applied to the first node; a carry part configured to output the clock signal as an N-th carry signal in response to the signal applied to the first node; a first voltage adjusting part configured to output a low clock signal to a second node in response to the signal applied to the first node; a first pull-down part configured to pull down the signal at the first node to a second “off” voltage in response to a carry signal of a subsequent stage; and a second pull-down part configured to pull down the N-th gate output signal to a first “off” voltage in response to the carry signal of the subsequent stage, wherein N is a positive integer.