Patent ID: 7861045
Filing Date: 2010-12-28
Classification: G06F

Abstract:
1. A memory control system, the memory control system comprising: a control unit for generating a microprocessor clock signal according to a base band clock signal, wherein the microprocessor clock signal comprises at least a first duration and at least a second duration that is shorter than the first duration; a serial storage device for storing data corresponding to a plurality of addresses and operating according to the base band clock signal; and a microprocessor for outputting one address during the first duration according to the base band clock signal, fetching the data corresponding to the address from the serial storage device during the first duration according to the base band clock signal, and executing at least an action instructed by the data during the second duration according to the base band clock signal; wherein the operating frequency of the outputting one address, the fetching data and the executing at least an action are the same as the operating frequency of the serial storage device.