Patent ID: 6188633
Filing Date: 2001-02-13
Classification: G11C

Abstract:
A computer processor comprising:a plurality of execution units;a register file comprising:R read ports;W write ports; andN registers, with each register having 1 bit positions, wherein each bit position of each register is accessed by:R read lines, with each read line associated with one of the R read ports;W write lines, with each write line associated with one of the W write ports;a direction line that assumes a write direction state during a write operation and a read direction state during a read operation;C combined read/write word lines, with each combined read/write word line associated with one of the R read ports and one of the W write ports; andR-W read-only word lines if R>W, wherein each read-only word line is associated with one of the R read ports not associated with a combined read/write word line; orW-R write-only word lines if W>R, wherein each write-only word line is associated with one of the W write ports not associated with a combined read/write word line;wherein each of the 1 bit positions includes:a storage element for storing a value associated with the bit position; anda storage element multiplexer that selectively couples one of the R read lines to the storage element to read a value from the storage element when the direction line assumes the read direction state and one of the read-only or combined read/write word lines is asserted, wherein the read line selected is associated with the same read port as the asserted read-only or combined read/write word line, and selectively couples one of the W write lines to the storage element to write a value to the storage element when the direction line assumes the write direction state and one of the write-only or combined read/write word lines is asserted, wherein the write line selected is associated with the same write port as the asserted write-only or combined read/write word line;a bus of write lines coupled between the execution units and the register file;a bus of read lines coupled between the execution units and the register file;a multiplexer;a bus of register index select lines coupled between the execution units and the multiplexer; anda bus of direction lines, combined read/write word lines, and read-only word lines if R>W, or write-only word lines if W>R, coupled between the multiplexer and the register file.