Patent ID: 7714548
Filing Date: 2010-05-11
Classification: H02M,H03K

Abstract:
1. An adaptive gate drive timing circuit for a power mosfet comprising, a capacitance having two terminals with a first terminal connected to a drain terminal of said power mosfet and a second terminal connected to a gate of said power mosfet, a sequencing circuit responsive initially to a discharge current of said capacitance and subsequently to the absence of said discharge current of said capacitance and responsive to a control signal from a modulation circuit for controlling a voltage or a current of an input or an output of a power supply circuit, comprising, a driver circuit for fast charge and fast discharge of a gate of said power mosfet, whereby said adaptive gate drive timing circuit provides optimal turn on timing for said power mosfet for the condition in which sufficient energy is available to drive a zero voltage turn on transition for said power mosfet and for the condition in which insufficient energy is available to drive a zero voltage turn on transition for said power mosfet.