Patent ID: 8879344
Filing Date: 2014-11-04
Classification: G11C

Abstract:
1. A method of operating a processing system comprising a phase change memory unit, a processor which executes programmable instruction sequences, and an input/output unit, comprising: precharging multiple bitlines configured to enable read access to multiple phase change memory cells, and read accessing said cells using said bitlines, said phase change memory cells being configured to store configuration data; discharging said bitlines when charged to approximately a precharge voltage; sending sense amplifier outputs to corresponding ones of multiple output units when ones of multiple sense amplifiers detect that corresponding ones of said bitlines have discharged to a sense threshold voltage; generating a clock signal when ones of one or more vote units detect transition at said vote unit of a majority of sense amplifier outputs corresponding to ones of one or more references stored in multiple ones of said phase change memory cells; outputting binary values depending on the order in which said clock signal, and ones of said sense amplifier outputs corresponding to phase change memory cells storing data, first change state at corresponding ones of said output units; and operating external elements using said processor and/or said input/output unit in accordance with said configuration data.