Patent ID: 8952482
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. An apparatus, comprising: a memory array having alternating levels of semiconductor materials and dielectric materials that are substantially parallel to a substrate on which they are formed, the memory array being at least partially within a cavity of the substrate, the alternating levels being stepped such that an uppermost surface of at least one end of a lower level of each of the semiconductor material levels extends beyond an overlying one of the semiconductor material and the dielectric material levels, the substrate being a semiconducting material, the cavity being sufficiently deep such that an upper surface of the memory array is substantially coplanar with an uppermost surface of the substrate; and peripheral circuitry including one or more devices formed on or in the uppermost surface of the substrate and adjacent to the memory array, an upper surface of the peripheral circuitry being substantially coplanar with the upper surface of the memory array to reduce an overall height and to reduce a resistance of peripheral circuitry contacts to couple the peripheral circuitry contacts from the peripheral circuitry to respective ones of a plurality of interconnects, the plurality of interconnects being formed between the memory array and the peripheral circuitry.