Patent ID: 6188248
Filing Date: 2001-02-13
Classification: G06F,H03K

Abstract:
A method for detecting an all-zero scenario for a n-bit word having a selected bit and (n-1) non-selected bits, the method comprising:generating a pre-charge voltage; andevaluating a logic state of the selected bit using a first convention and logic states of each of the non-selected bits using a second convention, said evaluating step including(a) determine a voltage of the selected bit, and a voltage of each of the non-selected bits,(b) discharging the pre-charge voltage if the selected bit is a first voltage and each of the non-selected bits is a second voltage, whereby the discharge of the pre-charge voltage indicates the all-zero scenario, andmaintaining the pre-charge voltage if at least one of the following conditions is met(I) the selected bit is said second voltage, and(ii) at least one of the non-selected bits is said first voltage.