Patent ID: 6258667
Filing Date: 2001-07-10
Classification: H01L,Y10S

Abstract:
A method of implementing an embedded flash, said method comprising:providing said substrate which is divided into at least a cell region and a peripheral region;forming a gate oxide layer on said peripheral region and forming a tunneling oxide layer on said cell region;forming a plurality of floating gates on said tunneling oxide layer, wherein the top of each of said floating gates is covered by a first dielectric layer and the sidewall of each of said floating gate is covered by a first thermal oxide layer;covering said first dielectric layer, said first thermal oxide layer and said gate oxide layer by a polysilicon layer;covering said entire cell region by a first photo-resist;forming a plurality of first metal oxide semiconductor transistors on said peripheral region;removing said first photo-resist;performing a self-aligned silicide process to form a plurality of silicides, herein said silicides covers source, drain and gate of each said first metal oxide semiconductor transistor, said silicides also covering said entire cell region;covering said entire substrate by an anti-reflection layer;covering said entire peripheral region by a second photo-resist;forming a plurality of second metal oxide semiconductor transistors on said cell region, wherein said silicides only cover the top of each of said second metal oxide semiconductor transistors, and said anti-reflection layer also only covers top of each said second metal oxide semiconductor transistors;forming a second dielectric layer on said substrate, wherein said second dielectric layer totally covers all said first metal oxide semiconductor transistors and all said second metal oxide semiconductor transistors; andforming a plurality of contacts in said second dielectric layer.