Patent ID: 6570800
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A semiconductor device comprising a memory block, said memory block including:a memory cell array having a plurality of memory cells whose selector terminal is connected to a word line and whose data input/output terminal is connected to a bit line; a row select circuit for selecting a word line specified by a row address signal in response to a change in a row address strobe signal in synchronous with a clock signal; a column select circuit for selecting a plurality of bit lines in parallel specified by a column address signal in response to a change in a column address strobe signal in synchronous with a clock signal; a serial/parallel converter circuit for converting serial data from the outside to parallel data in synchronous with a clock signal; a write amplifier for outputting in parallel an output from said serial/parallel converter circuit to said plurality of bit lines selected by said column select circuit; a main amplifier for amplifying said parallel data output in parallel from said plurality of bit lines selected by said column select circuit; and a parallel/serial converter circuit for converting parallel data supplied from said main amplifier to serial data in synchronous with a clock signal, wherein said column address strobe signal which is changed in cycles as many as a plurality of times of a clock signal cycle is input to said memory block.