Patent ID: 6522366
Filing Date: 2003-02-18
Classification: H04N

Abstract:
A dual-loop PLL circuit comprising a clamping circuit for clamping the DC level of a composite chrominance signal or a chrominance signal to a certain fixed level for output, an A/D conversion circuit for sampling the output signal from the clamping circuit by a sampling clock to output a digital signal, a reference color burst output circuit for comparing a color burst having a frequency of Fsc, Fsc: Frequency of a chrominance sub-carrier, out of the output signal of the clamping circuit, with a slice level for outputting a reference color burst having a rectangular waveform, a PLL circuit for generating a signal, having a frequency of NÂ·Fsc, N=integral number of times of 4, and phase-locked with a reference color burst by an oscillation frequency control, for being output as a sampling clock to said A/D conversion circuit, and a phase detection circuit for detecting the phase difference between the sampling clock and the reference color burst on the basis of the difference between the output signal of said A/D conversion circuit and the level of predetermined phase reference value and for outputting the slice level corresponding to the phase difference to said reference color burst output circuit.