Patent ID: 6855581
Filing Date: 2005-02-15
Classification: H01L

Abstract:
1. A method of fabricating a high voltage high power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate, comprising the steps of: sequentially forming an oxide film and a photoresist film on said silicon layer and then performing a photolithography process using a trench mask to pattern said photoresist film; patterning said oxide film using said patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching said silicon layer using the patterned oxide film as a mask until said insulating film is exposed to form a trench; forming a nitride film on the entire surface induding said trench and depositing polysilicon on the entire surface so that said trench is buried; sequentially removing said polysilicon and said nitride film until said silicon layer is exposed to flatten the surface, thereby forming a device isolating film for electrical isolation between devices; then forming at least one of a deep n-well, a deep p-well, a n-well and a p-well in said silicon layer.