Patent ID: 7872317
Filing Date: 2011-01-18
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a semiconductor substrate comprising at least one nFET device region and at least one pFET device region, which are separated by an isolation region; a first metal gate stack within said at least one nFET device region, said first metal gate stack having nFET behavior and comprising a rare earth metal-containing layer and a first metal layer, said rare earth metal-containing layer is an oxide of at least one of La, Ce, Yb, Sm, Er and Tb; and a second metal gate stack within said at least one pFET device region, said second metal gate stack having pFET behavior and comprising a second metal layer that may be the same or different from the first metal layer, wherein said first metal layer and said second metal layer do not include a Si-containing gate electrode thereon.