Patent ID: 6699757
Filing Date: 2004-03-02
Classification: H01L,Y10S

Abstract:
A method for manufacturing an integrated circuit on a substrate, including nonvolatile memory in an array portion of the substrate and other circuitry in a non-array portion of the substrate, comprising:forming gate dielectric layers in the array portion and in the non-array portion of the substrate; covering the gate dielectric layers with a protective layer in the array portion and in the non-array portion of the substrate; patterning lines in a bitline direction in the array portion, and etching said protective layer to form line structures; implanting dopants into the substrate through the gate dielectric layer in the array portion between the line structures; depositing a dielectric material between the line structures to fill gaps between the line structures; planarizing the array portion and the non-array portion to a level exposing said line structures and said dielectric material in the gaps between the line structures; removing said protective layer from said non-array portion and said line structures from said array portion, leaving the gate dielectric layers and the remaining portions of said dielectric material filling the gaps between the line structures; covering portions of the gate dielectric layers and said dielectric material filling the gaps between the line structures with a layer of polysilicon material; etching said layer of polysilicon to form wordlines in the array portion and transistor gate structures in the non-array portion; implanting dopants to form source and drain regions in the non-array portion; forming self aligned silicide in the source and drain regions in the non-array portion; applying a dielectric layer over the array portion and the non-array portion; and applying patterned metallization over the dielectric layer.