Patent ID: 6275550
Filing Date: 2001-08-14
Classification: H04L

Abstract:
A data transmission device comprising:an external interface circuit for outputting, to said data transmission device, data which is input from external to said data transmission device as reception data, and for outputting transmission data which is input from said data transmission device to external to said data transmission device;a transmission circuit for outputting said input transmission data in synchronous with a shift clock, and for storing said input reception data in synchronous with said shift clock;a delay circuit for delaying input reception shift clock, and for outputting the same as a phase collating clock;a phase detecting/collating circuit for determining a transition expecting section of said reception data based on a logic level of said input reception data shift clock and said phase collating clock to collate a phase of said reception data shift clock and a transition point of said input reception data, said phase detecting/collating circuit detecting that it is necessary to shorten said reception data shift clock and outputting a clock shortening timing signal when said reception data transition point is earlier than said phase of said reception data shift clock, and said phase detecting/collating circuit detecting that it is necessary to elongate said reception data shift clock and outputting a clock elongating timing signal when said reception data transition point is slower than said phase of said reception data shift clock;a reception clock frequency divider/corrector circuit for dividing a basic clock input from external to said data transmission device to output said reception data shift clock, said reception clock frequency divider/corrector circuit correcting such as to shorten said reception data shift clock and outputting the same when a clock shortening timing signal is input, and said reception clock frequency divider/corrector circuit correcting such as to elongate said reception data shift clock and outputting the same when a clock elongating timing signal is input; anda transmission clock frequency divider circuit for dividing said basic clock which is input to said data transmission device and for outputting a transmission data shift clock, whereina clock is corrected independently from data transmission rate.