Patent ID: 7155580
Filing Date: 2006-12-26
Classification: G06F

Abstract:
1. A vector information processing apparatus comprising: a CPU comprising a plurality of asynchronously operating units; a main memory for storing data; and a main memory controller for controlling the writing of data in said main memory, said main memory controller including a vector scatter (VSC) address buffer that holds a storage address in said main memory for each element designated by a vector scatter instruction, wherein said main memory controller inhibits the outputting of a writing permission signal that permits writing to said main memory which is generated according to a writing request that requests writing of an element having a smaller element number than at least one other element designated by the vector scatter instruction if the writing request instructs storage of said element at an identical storage address as said at least one other element and the writing request has not been processed in accordance with a sequence of element numbers defined by the vector scatter instruction, wherein writing requests for writing said element and said at least one other element to said storage address in said main memory are issued respectively from said asynchronously operating units of said CPU according to said vector scatter instruction.