Patent ID: 6818475
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method of forming wafer level package for producing a chip size packaging, said method comprising:providing a plurality of dies on the wafer, wherein said wafer has I/O metal pads on a first surface of said wafer; coating a photo sensitive polymer on said first surface of said wafer; removing a portion area of said photo sensitive polymer to expose said metal pad; coating a photoresist on a second surface of said wafer; forming a first conductive layer in said photo sensitive polymer and covering said metal pad; forming a conductive seeding layer on the top of said first conductive layer and said photo sensitive polymer; patterning a photoresist on the top of said seeding layer to define a circuit pattern; forming a second conductive layer on said defined photoresist pattern to serve as the circuit distribution diagram; removing said photoresist pattern, and removing said conductive seeding layer covered by said photoresist pattern; forming trenches in between of the packaging entity; filling a filling material in said trenches and covering said circuit distribution diagrams; grinding said second surface of said wafer until said filling material is exposed; executing an opening step to expose a portion of said circuit distribution diagram to define a reserved area for a conductive bump; executing a solder screen printing step to form a layer of solder on said reserved area; and reflowing said solder to form said conductive bump.