Patent ID: 6649490
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method of forming an integrated circuit device, comprising the steps of:forming a pair of interconnection patterns on a substrate, the substrate having a semiconductor region disposed between the pair of interconnection patterns; forming an etch-stop layer on the pair of interconnection patterns and the substrate; then forming a sacrificial insulation layer comprising a first material on the pair of interconnection patterns and on the semiconductor region; selectively etching the sacrificial insulation layer to expose portions of the etch-stop layer extending on surfaces of the pair of interconnection patterns; forming sidewall insulation spacers that comprise a second material and extend on sidewall portions of the pair of interconnection patterns in an upper gap region between the pair of interconnection patterns and on a portion of the sacrificial insulation layer covering the semiconductor region; and selectively etching the portion of the sacrificial insulation layer covering the semiconductor region to define recesses underneath the sidewall insulation spacers, using the sidewall insulation spacers as an etching mask.