Patent ID: 6191629
Filing Date: 2001-02-20
Classification: H03K

Abstract:
A D flip-flop circuit operating in master-slave configuration at high speed with low power consumption, comprising:a first current source;a second current source;a ground level;a master latch having a switching section and a memory section, a pair of data input terminals and a pair of differential signal output terminals;a slave latch having a switching section, a memory section, and a pair of differential signal input terminals connected to the differential signal output terminals of the master latch;a power supply connected to said first and second latch;said master latch operating with an active high clock signal and transparent while the slave latch is latched, and the slave latch operating with an active low clock signal and transparent while the master latch is latched, said latches clocked in sequence;said first and second current sources being interlaced, wherein at the active high clock signal the master latch switching section uses the current from the first current source while the slave latch memory section uses the current from the second current source, and at the active low clock signal the master latch memory section uses the current from the second current source while the slave latch switching section uses the current from the first current source; andthe switching section of each said latch biased with a higher current than the memory section, thereby resulting in the D flip-flop with low power consumption.