Patent ID: 6434054
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array having a plurality of non-volatile memory cells, the memory cells being divided into a plurality of blocks; a control section controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasing of data from the selected memory cell; and a block erasure control section for simultaneously subjecting a plurality of blocks to block-unit data erasure for simultaneous erasing of all data items in each block, wherein after the block erasure control section performs simultaneous erasure of data from the plurality of blocks, the control section executes verification as to whether or not data in each memory cell is desired one, and writing for making the data in each memory cell desired one, the control section executing writing, under a first writing condition, on a predetermined number of memory cells in each block in which data erasure has been executed, and executing writing, under a second writing condition, on memory cells in said each block other than the predetermined number of memory cells.