Patent ID: 7242613
Filing Date: 2007-07-10
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array having a first NAND type memory cell unit connecting a plurality of 1st memory cell transistors in-series in which a 1st electric charge accumulation layer and control gate are laminated, and a second NAND type memory cell unit connecting in-series a plurality of second memory cell transistors in which a 2nd electric charge accumulation layer and said control gate are laminated, are arranged in the shape of an array: and wherein said 1st memory cell transistors and said 2nd memory cell transistors are formed to face each other along with both side walls of a trench formed on a semiconductor substrate respectively, sharing said one control gate formed by extending in a depth direction of said trench; wherein said control gate is formed between said 1st electric charge accumulation layer of said 1st memory cell transistors and said 2nd electric charge accumulation layer of said 2nd memory cell transistors, and electrically connects with a word line extending continuously; and wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer are respectively formed by laminating silicon oxide film, a silicon nitride film and silicon oxide film in order, and said control gate is made of poly silicon doped with impurities or metal; and wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer are part of the same continuous layer.