Patent ID: 6734491
Filing Date: 2004-05-11
Classification: H01L

Abstract:
An integrated circuit, comprising:transistors formed over or in a semiconductor substrate; memory cells, including: source and drain regions located in said semiconductor substrate and having similar doping profiles; a channel region extending from said source region to said drain region; a dielectric layer located over said channel region and having first and second thicknesses wherein said second thickness is substantially less than said first thickness and is partially located over said channel region; and a gate located over said dielectric layer wherein a portion of said second thickness is located between an end of said gate and one of said source and drain regions; the source and drain regions each include a lightly doped region, wherein said end of gate and said second thickness are located over one of said lightly doped regions; and interconnects connecting said transistors and said memory cells to form an integrated circuit.