Patent ID: 7595232
Filing Date: 2009-09-29
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a semiconductor substrate that comprises at least first and second device regions of different surface crystal orientations, wherein the first and second device regions are separated from each other by a dielectric spacer that is located therebetween in the semiconductor substrate; recessing an upper portion of the dielectric spacer to form a gap between the first and second device regions, wherein a lower portion of the dielectric spacer remains in the gap; filling the gap with a conductive material thereby forming a conductive connector that is located atop said lower portion of the dielectric spacer and between the first and second device regions and embedded in the semiconductor substrate; and forming an n-FET and a p-FET, wherein the n-FET comprises source, drain, and channel regions located in one of the first and second device regions, wherein the p-FET comprises source, drain, and channel regions located in the other of the first and second device regions, and wherein the n-FET and p-FET are electrically connected by the conductive connector.