Patent ID: 6335886
Filing Date: 2002-01-01
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory cells to each of which a unique address signal is allocated in advance; a spare memory cell for replacing a defective memory cell of said plurality of memory cells; a decoder provided corresponding to each memory cell, and activating a corresponding memory cell in response to the address signal allocated to the corresponding memory cell being applied; a redundancy decoder inactivating said decoder and activating said spare memory cell in response to the address signal allocated to said defective memory cell being applied; and a write/read circuit writing and reading data of the memory cell activated by said decoder and the memory cell activated by said redundancy decoder, said redundancy decoder including a precharge circuit activated before said address signal is applied and charging an output node to a first potential, a fuse provided corresponding to each memory cell, having one terminal connected to the output node of said precharge circuit, and blown when a corresponding memory cell is defective, a plurality of transistors provided corresponding to each memory cell, connected in series between another terminal of a corresponding fuse and a line of a second potential, and rendered conductive in response to the address signal allocated to a corresponding memory cell being applied, and a driver activating said spare memory cell when the output node of said precharge circuit has said first potential after said address signal is applied.