Patent ID: 6275067
Filing Date: 2001-08-14
Classification: H04L

Abstract:
A current mode receiver coupled between a high supply voltage source and a low supply voltage source and coupled to a double bit current mode bus to receive a current mode signal, whereby the current mode signal comprises a first positive current, a second positive current, a first negative current and a first positive current, to provide an unextracted form of a two bit digital data signal, wherein said current mode receiver comprises:a) a receiver input terminal coupled to the double bit current mode bus to receive said current mode signal;b) a first and a second receiver output terminal to provide the unextracted form to the two bit digital data signal to external circuitry;c) a first differential amplifier circuit having a first differential amplifier noninverting input coupled to a reference voltage source, an first differential amplifier inverting input coupled to the receiver input terminal, and a first differential amplifier output terminal connected to the first receiver output terminal;d) a first transmission gate comprising a fourth MOS transistor of the first conductivity type having a gate coupled to the high supply voltage source, a source coupled to the first differential amplifier output terminal, a drain coupled to the first differential amplifier inverting input terminal, and a fourth MOS transistor of the second conductivity type having a gate couple to the low supply voltage source, a drain coupled to the first differential amplifier output terminal, and a source coupled to the first differential amplifier inverting input terminal;e) a second transmission gate comprising a fifth MOS transistor of the first conductivity type having a gate coupled to the first differential amplifier output terminal, and a drain coupled to the receiver input terminal, and a fifth MOS transistor of the second conductivity type having a gate couple to the first differential amplifier output terminal, and a source coupled to the receiver input terminal;f) a second differential amplifier having a second differential amplifier noninverting input connected to the reference voltage source, a second differential amplifier inverting input terminal coupled to the source of the fifth MOS transistor of the first conductivity type and to the drain of the fifth MOS transistor of the second conductivity type, and a second differential amplifier output terminal coupled to the second receiver output terminal; andg) a third transmission gate comprising a sixth MOS transistor of the first conductivity type having a gate coupled to the high supply voltage source, a source coupled to the second differential amplifier output terminal, a drain coupled to the second differential amplifier inverting input terminal, and a sixth MOS transistor of the second conductivity type having a gate coupled to the low supply voltage source, a drain coupled to the second differential amplifier output terminal, and a source coupled to the second differential amplifier inverting input terminal.