Patent ID: 6239026
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method for forming vias in a semiconductor device, said semiconductor device having a foundation layer having at least one layer of material, a conductive layer formed above said foundation layer and etched into conductive portions, a low dielectric constant layer formed above said conductive layer, an etch-stop layer formed above said low dielectric constant layer, and an insulating layer formed above said etch-stop layer, said method comprising:first etching a via into said insulating layer with a first non-selective etchant such that said via terminates within said insulating layer;second etching said via into said insulating layer with a second selective etchant such that said via terminates proximate said etch-stop layer; andthird etching said via with a third non-selective etchant through said etch-stop layer and said low dielectric constant layer such that said via terminates proximate said conductive layer.