Patent ID: 7241655
Filing Date: 2007-07-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure containing at least one vertical transistor, the method comprising the acts of: providing a substrate wherein at least a portion of the working surface thereof is polysilicon; depositing a first insulator layer on the substrate; depositing a second insulator layer; depositing a third insulator layer; forming at least one hole through the insulator layers over the polysilicon portion of the substrate surface to thereby expose the polysilicon; epitaxially growing a respective polysilicon pillar from the polysilicon portion of the substrate surface through each of the at least one hole; forming a protective cap layer over each pillar; removing the third insulator layer to thereby expose the sidewall surface of a top portion of each pillar; forming a spacer layer around the top portion of each pillar on the exposed sidewall surface thereof; removing the second insulator layer to thereby expose the sidewall surface of a central portion of each pillar, the central portion being adjacent and beneath the spacer layer; depositing a dielectric layer around the central portion of each pillar on the exposed sidewall surface thereof; and surrounding the dielectric layer of each pillar with a layer of conductive material; wherein the top portion of each pillar forms a first source/drain region of a respective transistor, the central portion of each pillar forms a channel region of the respective transistor, the bottom portion of each pillar forms a second source/drain region of the respective transistor, and a region of the conductive material surrounding each pillar forms a transistor gate of the respective transistor.