Patent ID: 7608489
Filing Date: 2009-10-27
Classification: H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor structure: forming, simultaneously, a layered structure with an underlying stress inducing material, in a p-type field-effect-transistor (PFET) channel region and a n-type field-effect-transistor (NFET) channel region; protecting the NFET channel region while forming a layer over the underlying stress inducing material of the PFET channel region; and etching an island in the NFET channel region and the PFET channel region, creating a higher resultant stress component in the NFET channel region; and forming a stress inducing material in the etched portions of the PFET channel region creating an opposite stress component in the PFET channel region than in the NFET channel region.