Patent ID: 7729897
Filing Date: 2010-06-01
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: an emulator configured to emulate a hardware design; a runtime assist unit comprising a processor configured to work with the emulator to emulate the hardware design, the runtime assist unit further comprising a general purpose register directly accessible by the processor; and a connection allowing communication of emulation data between the emulator and the general purpose register of the runtime assist unit, wherein the emulation data communicated over the connection is time division multiplexed, wherein the circuit arrangement is configured to determine a time associated with at least one of: storing emulation data, loading emulation data and sending emulation data, including sending emulation data over the connection, wherein the determined time is used to time division multiplex the emulation data, wherein the circuit arrangement is configured to disable an external interrupt of the runtime assist unit and, in response to disabling the external interrupt of the runtime assist unit, provide a virtual I/O between the runtime assist unit and the emulator such that the time division multiplexed emulation data may be received by the runtime assist unit at any time, and wherein the circuit arrangement is configured to, in response to providing the virtual I/O between the runtime assist unit and the emulator, communicate over the connection the time division multiplexed emulation data between the emulator and the general purpose register of the runtime assist unit, the time division multiplexed emulation data received by the runtime assist unit being received directly by the general purpose register of the runtime assist unit.