Patent ID: 7414451
Filing Date: 2008-08-19
Classification: G11C,H03K,H03L

Abstract:
1. A clock generator for a semiconductor memory apparatus, comprising: a first divider configured to divide a frequency of a first internal clock generated by using an external clock and produce an output having a phase; a first delay unit configured to delay the output of the first divider by a predetermined amount of time and produce an output having a duty cycle; a second divider configured to divide a frequency of a second internal clock generated by using the external clock and produce an output; a second delay unit configured to delay the output of the second divider by a predetermined amount of time and produces an output having a duty cycle; a duty-cycle corrector configured to correct the duty cycles of the outputs of the first and second delay units and output corrected results as first and second corrected clocks having frequencies; a third divider configured to divide the frequency of the first corrected clock and produce an output; a third delay unit configured to delay the output of the third divider by a predetermined amount of time and produce an output having a phase; a phase comparator configured to compare the phase of the output of the third delay unit with the phase of the output of the first divider and output a result of the comparison; and a delay time setting unit configured to set delay times for the first and second delay units on the basis of the output of the phase comparator.