Patent ID: 6816560
Filing Date: 2004-11-09
Classification: H04L,H04N

Abstract:
Packet synchronization detector for an incoming digital signal which includes a regularly repeated predetermined synchronization pattern which repetition rate defines the length of one transmission packet, comprising:a synchronization pattern detector that outputs a control signal whenever the incoming digital signal carries one predetermined synchronization pattern, a synchronization state machine that determines whether or not one detected synchronization pattern with a first position within the length of one transmission frame has the correct repetition rate to determine whether or not lock has been achieved on basis of said first position of said synchronization pattern within the transmission frame, characterized by at least one further synchronization state machine that respectively determines whether or not one further detected synchronization pattern with a respective further position within the length of one transmission frame has the correct repetition rate to determine whether or not lock has been achieved on basis of said respective further position of said synchronization pattern within the transmission frame.