Patent ID: 6393597
Filing Date: 2002-05-21
Classification: G06F

Abstract:
An apparatus for decoding a global error correction code corresponding to a plurality of data bits, wherein said global error correction code is equivalent to a predetermined combination of a set of error correction codes each individually associated with a corresponding one of said plurality of data groupings, and wherein global error correction code is expressed using a smaller number of bits than a total number of bits of said set of error correction codes, the apparatus comprising:a global syndrome code generation unit configured to generate a global syndrome code representing a difference between the global error correction code and a regenerated global error correction code, wherein the regenerated global error correction code is regenerated using a plurality of received data bits; a first shift register configured to receive a set of parity error bits each indicative of a parity error within a respective group of said received data bits; a second shift register configured to receive said global syndrome code; and a control unit coupled to said first and second shift registers, wherein said control unit is configured to selectively shift and combine said set of parity error bits and said global syndrome code to generate a syndrome code indicative of a location of an error within any of said groups of received data bits.