Patent ID: 6828174
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:(a) providing a wiring substrate with plural wires and plural bonding pads electrically connected to the plural wires, formed on a main surface thereof, a first semiconductor chip having an integrated circuit and a plurality of first terminals formed on a main surface thereof and with plural bump electrodes formed on the plurality of first terminals respectively, and a second semiconductor chip having an integrated circuit and a plurality of second terminals formed on a main surface thereof, the bonding pads of the wiring substrate being arranged in a first pitch, the first terminals of the first semiconductor chip and plural bump electrodes also being arranged in said first pitch in a manner similar to the arrangement of the bonding pads of the wiring substrate respectively; (b) placing the first semiconductor chip on the main surface of the wiring substrate so that the main surface thereof is opposed to the main surface of the wiring substrate, and connecting the plurality of first terminals of the first semiconductor chip and a first set of plural bonding pads of the wiring substrate with each other electrically through the plural bump electrodes; (c) placing the second semiconductor chip on the first semiconductor chip so that a rear surface thereof is opposed to the main surface of the wiring substrate, and connecting the plurality of second terminals of the second semiconductor chip and a second set of the bonding pads of the wiring substrate with each other electrically through plural bonding wires, the second set of bonding pads being different from the first set of bonding pads; and (d) sealing the first and second semiconductor chips with resin, wherein said second terminals of said second semiconductor chip are arranged in a second pitch narrower than said first pitch, and wherein said first pitch is a pitch of adjacent bonding pads and adjacent first terminals, and said second pitch is a pitch of adjacent second terminals.