Patent ID: 7672158
Filing Date: 2010-03-02
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of memory cell units, each of the memory cell units including first and second selection transistors, and data-rewritable non-volatile memory cells connected in series between the first and the second selection transistors; a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array; a first gate line commonly connected to gates of the first selection transistors on the same row in the memory cell array; and a second gate line commonly connected to gates of the second selection transistors on the same row in the memory cell array, wherein a selected memory cell unit is connected to a selected word line, a first word line and a second word line, both of the first word line and the second word line being different from the selected word line, the first word line and the second word line being different from each other, and wherein charging the first word line to a first intermediate voltage for writing is started in a first timing, charging the selected word line to a high voltage for writing is started in a second timing which is later than the first timing, and a voltage level of the second word line changes from a first voltage to a second voltage after the first word line is set to the first intermediate voltage for writing, the first intermediate voltage for writing and the second voltage are respectively applied to the first word line and the second word line when the high voltage for writing is applied to the selected word line, the high voltage for writing being higher than both of the first intermediate voltage for writing and the first voltage, and both the first intermediate voltage for writing and the first voltage being higher than the second voltage.