Patent ID: 9160338
Filing Date: 2015-10-13
Classification: G06F,H03K

Abstract:
1. A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as a corresponding sender side or receiver side, for connection to the FPGA, wherein a serial interface is formed between the at least one FPGA and the at least one I/O module, the method comprising: configuring a maximum number of registers to be transmitted for each FPGA application; configuring a shared and/or fixed register width for all registers; setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted; transmitting an enable signal from the sender side to the receiver side; and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.