Patent ID: 6104774
Filing Date: 2000-08-15
Classification: H03K,H04L

Abstract:
A frequency multiplying circuit comprising:a timing generation circuit for generating, from an input clock signal, timing signals including a signal for defining target measurement periods wherein each target period is to be measured as a length of one cycle of the input clock signal and is within an interval of an integer number of input clock cycles, and a signal for defining actual measurement periods to sustain measurement operations slightly longer than the target measurement periods;a first and second duty determination circuit for determining a timing position for a state transition of the output clock signal corresponding to a duty cycle of 50%, and each outputting a coincidence output indicating the timing position, upon receiving said timing signals;wherein said first and second duty determination circuit operate in operation cycles C1 and C2, respectively;wherein said operation cycles C1 and C2 overlap at at least one input clock cycle and are shifted two input clock cycles from each other;each one of said duty determination circuits including a delay line oscillator, a counter for counting a number of oscillation cycles of the delay line oscillator, a latch for latching a court value of the counter at the end of one of said target measurement periods, an operation circuit for calculating a 1/4 value, 2/4 value, and a 3/4 value of said count value, and a coincidence circuit which uses the output of the corresponding operation circuit as one input, uses the output of said counting as the other input, and outputs a coincidence output whenever the current count value of said counter becomes coincident with any one of said three calculation values;a first flip flop positioned before said duty determination circuit, which is set in synchronization with a front edge of the input clock signal and is reset by the final one of said coincidence outputs of said first duty determination circuit;a second flip flop positioned before said duty determination circuit, which is set in synchronization with a front edge of the input clock signal and is reset by the final one of said coincidence outputs of s aid second duty determination circuit;a first OR gate for inputting the output of said first flip flop and inputting said signal for defining said actual measurement periods wherein the output of the first OR gate is inputted into said first duty determination circuit;a second OR gate for inputting the output of said first flip flop and inputting said signal for defining said actual measurement periods wherein the output of the first OR gate is inputted into said second duty determination circuit;a third flip flop for output which is reset every time in synchronization with the front edge of the input clock signal, and the status of which is changed over by coincidence outputs obtained by said first duty determination circuit and said second duty determination circuit.