Patent ID: 6615341
Filing Date: 2003-09-02
Classification: G06F

Abstract:
A digital signal processor (DSP) comprising:a plurality of processing units for generating result data in response to a first input data and a second input data; a first data bus and a second data bus for transmitting the first and second input data to at least first and second ones, respectively, of the plurality of processing units; a third data bus for transmitting the result data to at least a third one of the plurality of processing units; and a register bank having registers accessible by at least the first and second ones of the plurality of processing units to facilitate multiple data operations to be performed simultaneously by at least two of the plurality of processing units, whereby at least one of the first and second data buses is narrower than the third data bus, and whereby, in response to a single instruction and data in associated registers, the first, second and third data buses are communicably coupled to corresponding ones of the at least first, second, and third ones of the plurality of processing units.