Patent ID: 6125464
Filing Date: 2000-09-26
Classification: G01R

Abstract:
An integrated circuit with boundary scan comprising:core circuitry having at least one system data output line;boundary scan logic having a test data line, a shift signal line, and a mode signal line,at least one output boundary scan cell having a boundary scan multiplexer having a control input coupled to said shift signal line and having a first input coupled to receive a system data signal and having a second input coupled to said test data line, said boundary scan cell further having a first output data register having an input coupled to an output of said boundary scan multiplexer; andat least one output cell including an output data multiplexer having a control input coupled to said mode signal line and having as inputs said system data output line and an output of said first output data register, said output cell further including an output buffer coupling an output of said out put data multiplexer to a pin of said integrated circuit,whereby said at least one output boundary scan cell and said at least one output cell are separate from each other.