Patent ID: 6072345
Filing Date: 2000-06-06
Classification: G06F,H03L,H04L

Abstract:
A semiconductor device, comprising:a comparing circuit having first and second clock signal input nodes, for detecting a difference in at least one of chase and frequency of first and second clock signals applied to said first and second clock signal input nodes and for outputting first and second comparing signals for decreasing said difference;a charge pump circuit receiving said first and second comparing signals for charging a charging/discharging node when said first comparing signal is active, and for discharging said charging/discharging node when said second comparing signal is active;a current control circuit including a transfer gate connected between said charging/discharging node and a first node, receiving a hold designating signal and rendered non-conductive when said hold designating signal is active, for outputting a current control signal in accordance with the potential at said first node; andan internal clock signal generating circuit of which operational current is adjusted in accordance with said current control signal, for outputting said second clock signal; whereinthe hold designating signal is set to said active state when supply of the first clock signal to said first clock signal input mode is stopped.