Patent ID: 6780712
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A method of fabricating a finger-like floating gate structure in flash memory cells comprising:providing a semiconductor region within a substrate extending to a surface containing parallel active regions separated by raised isolation regions that extend from above said surface into said semiconductor region; forming a gate dielectric layer over said active regions; forming a blanket first conductive layer over said active regions and over said isolation regions; forming a blanket insulator layer over said first conductive layer; performing a spacer etch on said insulator layer stopping at said first conductive layer to form insulator spacers; forming a second conductive layer over said first conductive layer and said insulator spacers; removing the parts of said second conductive layer and first conductive layer that are higher than the top of said raised isolation regions; removing said insulator spacers and removing parts of said raised isolation region that are higher than about a first conductive layer above the level of said gate dielectric; forming a blanket interlevel dielectric layer; forming a blanket third conductive layer and patterning said third conductive layer into parallel lines perpendicular to said active regions removing said interlevel dielectric layer, said second conductive layer and said first conductive layer that is not under said third conductive layer lines.