Patent ID: 7214630
Filing Date: 2007-05-08
Classification: C23C,H01L

Abstract:
1. A method of fabricating a dielectric layer having compressive stress on a semiconductor substrate, comprising processes of: (a) providing in a vacuum chamber a deposition reactant mixture comprising A1 atoms of a chemical element A1 and A2 atoms of a chemical element A2, wherein said element A2 is more electronegative than said element A1, and wherein said A1 atoms have a positive oxidation state and said A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms; (b) applying high-frequency (HF) and low-frequency (LF) power to said deposition reactant mixture to generate a deposition plasma containing excited A1-species and excited A2-species; (c) depositing a dielectric sublayer on said substrate using said deposition plasma; (d) providing a post-treatment gas containing peening species to a vacuum chamber, said post-treatment gas being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; (e) applying HF and LF power to said post-treatment gas to generate a post-treatment plasma, said post-treatment plasma comprising excited peening species, and said post-treatment plasma being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; (f) post-treating said dielectric sublayer in said post-treatment plasma; and (g) repeating said processes (c) and (f) of depositing a dielectric sublayer and post-treating said dielectric sublayer until a desired thickness of a dielectric material is achieved.