Patent ID: 8458267
Filing Date: 2013-06-04
Classification: G06F,H04L

Abstract:
1. A method for receiving messages in a parallel computing system having a plurality of nodes, each node having multiple processor units and an associated memory system operatively connected therewith via an interconnect device, said method comprising: receiving, at a network receiver device of a plurality of network receiver devices, a packet associated with a message and storing said packet at a network reception queue; receiving, at a reception control unit, information from a processor at a node for handling of packets associated with messages received over a network, said received information specifying pointers to addresses in said associated memory system where data received from a message packet is to be stored; receiving, at one of a plurality of parallel distributed reception messaging engine units (rMEs) associated with said network reception buffer, a packet header of said received packet, each reception messaging engine unit providing a multi-channel direct memory access (DMA) function and corresponds to a network reception queue operatively connected with the reception control unit; receiving, at said reception messaging engine unit, a pointer address from the reception control unit; aligning received data on a byte alignment value specified in said packet, wherein said packet data is written to the location in memory system using signals to identify valid bytes, transferring the received packet from the network reception buffer directly to a location in the associated memory system specified by the pointer, wherein each associated reception message engine unit is coupled with an interconnect device having ports adapted for providing a connection to said interconnect device, said method further comprising: arbitrating requests between each said rMEs to assign access to an interconnect port; and, writing packet data from said network reception buffer to said location in memory system via said interconnect device, and, wherein a received packet type specifies storage at said location in a memory system associated with said processor device, said method further comprising: calculating, at said rME unit, a destination address in said memory system and moving only payload data of the received packet from a network reception queue at said destination address in the memory system; calculating, at said rME unit, a counter address for storing a byte count value, obtaining, at said rME, a data ID field and a counter ID field from said packet header values and, respective data offset value and counter offset value; and receiving, from a reception control memory, based upon said data ID field and a counter ID field, a respective base address in said memory system, and a counter base address in said memory system, said calculating of a destination address and counter address comprising: adding said specified data offset to said to said base address; and, adding said specified counter offset value to said counter base address, wherein at least two messages may be received and processed simultaneously without intervention of a processor unit.