Patent ID: 7594089
Filing Date: 2009-09-22
Classification: G06F

Abstract:
1. A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access method modifiers with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method modifier for a particular one memory location responsive to a memory access instruction relating to the particular one memory location including an operand identifying an access method, the interface comprising: a request storage for storing a plurality of concurrent memory access instructions for one or more of the particular memory locations, each said memory access instruction issued from an associated independent thread context, wherein instruction issue from said associated independent thread context stops in response to said memory access instruction accessing the gating memory; an arbiter, coupled to said request storage, for selecting a particular one of said memory access instructions to apply to the gating memory; and a controller, coupled to said request storage and to said arbiter, for: wherein said arbiter periodically selects each of said memory access instructions from said request storage using an arbitration policy; wherein the gating memory includes a control flag associated with at least one of the plurality of memory access method modifiers and wherein said controller modifies said arbitration policy responsive to said control flag.