Patent ID: 8030710
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; an isolation trench formed in a surface portion of said semiconductor substrate and defining an NMOSFET active region and a PMOSFET active region; a silicon oxide film burying only a lower portion of said isolation trench and defining a recess above the lower portion; an NMOSFET structure formed in said NMOSFET active region and having an insulated gate electrode structure and n-type source/drain regions; a PMOSFET structure formed in said PMOSFET active region and having an insulated gate electrode structure and p-type source/drain regions; a tensile stress film covering said NMOSFET structure, and extending to said recess surrounding said NMOSFET active region, and to said recess outside said PMOSFET active region, and on a side surface of said PMOSFET active region along a gate width direction; and a compressive stress film covering said PMOSFET structure and extending to said recess outside said PMOSFET active region along a channel length direction.