Patent ID: 6580643
Filing Date: 2003-06-17
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device including a memory cell array composed of a plurality of memory cells, each of which is formed with a gate insulating film, a floating gate electrode, an insulating film between electrode layers, and a control gate formed respectively in a first conductor type semiconductor area, as well as a second conductor type source area and a second conductor type drain area formed respectively in said first conductor type semiconductor area, and programming and erasing data by controlling electrons stored in said floating gate electrode, whereinsaid nonvolatile semiconductor memory device further includes at least; means for applying a predetermined first operation voltage to a memory cell thereby to inject or eject electrons in or from said floating gate electrode; means for applying a second operation voltage to said memory cell after the application of said first operation voltage to give an electric field with a polarity opposite to that of the electric field given with the application of said first operation voltage to an insulating film area around said floating gate through which electrons pass when said first operation voltage is applied; means for verifying the threshold voltage in said memory cell after the application of said second operation voltage; and means for deciding whether to repeat said operations following the application of said first operation voltage again after said verify operation.