Patent ID: 9136135
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a plurality of first gate patterns on a first region of a substrate, the plurality of first gate patterns having a first width therebetween and including a first spacer and a first gate insulating layer; forming a plurality of second gate patterns on a second region of the substrate, the plurality of second gate patterns having a second width therebetween different from the first width and including a second spacer and a second gate insulating layer; and etching sides of the plurality of first and second gate patterns simultaneously using a first wet-etching process, the etching sides of the plurality of first gate patterns forming a first recess, and the etching sides of the plurality of second gate patterns forming a second recess, the first recess having a first distance between an edge of the first recess and a first boundary surface between the first spacer and the first gate insulating layer, and the second recess having a second distance between an edge of the second recess and a second boundary surface between the second spacer and the second gate insulating layer, the first distance being equal to the second distance.