Patent ID: 8183626
Filing Date: 2012-05-22
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a semiconductor substrate; a high-voltage well (HVW) region in the semiconductor substrate; a first double diffusion (DD) region in the HVW region; a second DD region in the HVW region, wherein the first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region; a recess extending from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region; a gate dielectric extending into the recess and covering a bottom of the recess; a gate electrode over the gate dielectric; a first source/drain region in the first DD region; a second source/drain region in the second DD region, wherein the first DD region comprises a first top surface being substantially flat, the second DD region comprises a second top surface being substantially flat, and wherein the gate electrode does not have any portion directly over the first top surface of the first DD region and the second top surface of the second DD region; a first dielectric spacer on a sidewall of the first DD region; and a second dielectric spacer on a sidewall of the second DD region.