Patent ID: 6835981
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A semiconductor chip comprising:a base substrate; a bulk device region having a bulk growth layer on a part of the base substrate, the bulk device region having a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer, the bulk growth layer including a silicon bulk growth layer and a silicon germanium bulk growth layer; a first isolation formed in the bulk device region so as to separate the bulk device; an SOI device region having a buried insulator on the other part of the base substrate and an SOI layer on the buried insulator, the SOI device region having a second device-fabrication surface in which an SOI device is positioned on the SOI layer, the first and second device-fabrication surface being positioned at a substantially uniform level; a second isolation formed in the SOI device region so as to separate the SOI device; and a boundary layer located at a boundary between the bulk device region and the SOI device region.