Patent ID: 6480025
Filing Date: 2002-11-12
Classification: H03K

Abstract:
A programmable logic array integrated circuit organized as a two-dimensional array of cells comprising:a first plurality of conductors extending along a first dimension of said two-dimensional array; a second plurality of conductors extending along a second dimension of said two-dimensional array, said second plurality of conductors programmably coupled to said first plurality of conductors; and a plurality of logic array blocks, wherein a logic array block comprises: a plurality of first-level programmable function blocks configured to implement logic functions, a first second-level programmable function block, programmably coupled to said plurality of first-level programmable function blocks, without passing through said first plurality of conductors and said second plurality of conductors, said first second-level programmable function block configured to implement logic functions of outputs from said plurality of first-level programmable function blocks, a plurality of dedicated inputs programmably coupled to said first second-level programmable function block, and a second second-level programmable function block configured to receive input signals from only at least a subset of said plurality of first-level programmable function blocks.