Patent ID: 7915164
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A method for forming a via structure to connect device levels in a monolithic three dimensional array, the method comprising: providing a substrate; forming a first device level of thin film transistors at a first height above the substrate, the first device level comprising a first polysilicon layer, the first polysilicon layer is a gate electrode of a thin film transistor of the first device level of thin film transistors; forming a polysilicon via above the first polysilicon layer, a bottom surface of the polysilicon via is in contact with the first polysilicon layer; and forming a second device level of thin film transistors at a second height above the substrate, wherein the second height is above the first height, the second device level comprising a second polysilicon layer, wherein the second polysilicon layer is above the polysilicon via, and a top surface of the polysilicon via is in contact with the second polysilicon layer.