Patent ID: 7735037
Filing Date: 2010-06-08
Classification: G06F,G11C,H03K,H04L

Abstract:
1. A circuit comprising: an instruction sequencer to implement control of interface operations by generating one or more opcodes; a bus coupled to the instruction sequencer; a plurality of interface control circuits coupled to the bus and including respective processing elements, the plurality of interface control circuits to receive the one or more opcodes generated by the instruction sequencer, wherein the one or more opcodes are received by the plurality of interface control circuits in parallel, and the respective processing elements perform operations responsive to the one or more opcodes generated by the instruction sequencer in parallel, wherein one or more of the interface control circuits generate one or more interface adjustment signals based on results of the operations performed by the processing elements in parallel; and Means for altering a characteristic of one or more signals coupled to said interface control circuits in response to said one or more interface adjustment signals.