Patent ID: 6097093
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A dual damascene structure, the structure comprising:a provided substrate, wherein the substrate contains a metal-oxide semiconductor transistor, which metal-oxide-semiconductor transistor comprises a conducting layer and has a fabrication linewidth;a plurality of interconnects located on the substrate, wherein a part of the interconnects are electrically connected to the interconnects;a plurality of metal layers located on the interconnects, wherein the metal layers are electrically connected to the interconnects;a first metal spacing region located within the metal layers, wherein a width of the first metal spacing region is about 1 to 10 times the fabrication linewidth, and the first metal spacing region is a first dielectric; anda second metal spacing region located within the metal layers, wherein a width of the second metal spacing region is about 0.8 to 1.2 times of the fabrication linewidth, the second metal spacing region is a second dielectric, and the second dielectric is furthermore a low-permittivity dielectric which has a lower permittivity than the first dielectric.