Patent ID: 6544872
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A method of manufacturing an NMOS transistor or CMOS semiconductor device, which method comprises the steps of:(a) providing a Si semiconductor substrate having a surface; (b) forming a thin gate insulator layer in contact with said substrate surface; (c) forming an electrically conductive gate electrode on a portion of said thin gate insulator layer, said gate electrode comprising first and second opposing side surfaces and a top surface; (d) forming a pair of shallow-depth, n-type source and drain extension regions in portions of said substrate, each of said source and drain extension regions extending laterally to beneath an edge of a respective one of said first and second opposing side surfaces of said gate electrode; (e) forming sidewall spacers composed of an insulating material on each of said first and second opposing side surfaces of said gate electrode; (f) forming, by implantation of As n-type dopant ions utilizing said sidewall spacers as an implantation mask, a pair of deeper, n-type source and drain regions in said source and drain regions formed in step (d), such that the concentration vs. depth profile of the implanted As ions has a peak at a first depth below said substrate surface; (g) implanting B-containing p-type dopant ions into said pair of n-type source and drain regions utilizing said sidewall spacers as an implantation mask, such that the concentration vs. depth profile of the implanted B-containing dopant ions has a peak at a second depth below said substrate surface, said second depth being greater than said first depth, whereby said first depth is limited by said second depth; (h) forming a layer of Ni on said substrate surface overlying at least said pair of source and drain regions; and (i) reacting said Ni layer to form a pair of electrically conductive NiSi layers extending into respective ones of said pair of source and drain regions for a third depth below said substrate surface, said third depth being less than said first depth, thereby eliminating or at least substantially reducing roughness of the interfaces between the NiSi layers and the As-doped source and drain regions by minimizing the concentration of As ions in said NiSi layers.