Patent ID: 6437789
Filing Date: 2002-08-20
Classification: G06F,G09G

Abstract:
In a computer graphics system for developing video images for display on a video display device, a cache control system, comprising:a frame buffer memory having: a first memory for storing pixel data for ultimate supply to the video display device, and a cache memory for storing data received from the first memory, data which is to be written into the first memory, and data received from a cache controller, and a cache controller coupled to the cache memory for controlling access thereto, the cache controller comprising: a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memory and adapted to temporarily store cache commands for supplying to the cache memory, along with any pixel data then stored in the cache FIFO memory, to cause the cache memory to store said any pixel data, to store data received from the first, or write data into the first memory, wherein said cache controller further includes a first command first in, first out (FIFO) memory for temporarily storing first commands for supply to the first memory to cause the first memory to store pixel data received from cache memory or write data into the cache memory.