Patent ID: 8848462
Filing Date: 2014-09-30
Classification: G06F,G11C,Y02D

Abstract:
1. A memory system comprising: a memory controller packaged in a first die and powered by a first power source and a second power source, wherein the memory controller comprises: a first input/output pin; a first driver circuit, coupled to the first input/output pin, for providing to a writing signal to the first input/output pin; a first terminal resistor coupled between the first input/output pin and the first power source; and a first input buffer, coupled to the first input/output pin, for receiving a reading signal from the first input/output pin; wherein the first terminal resistor is disposed on the inside of the first die, no terminal resistor is coupled between the first input/output pin and the second power source; a memory device packaged in a second die and comprising: a second input/output pin coupled to the first input/output pin; a memory array for storing data; a controlling circuit for accessing the memory array; a second driver circuit coupled to the second input/output pin, wherein the controlling circuit reads data from the memory array to generate the reading signal, and the second driver circuit drives the reading signal and provides the driven reading signal to the second input/output pin; and a second input buffer, coupled to the second input/output pin, for receiving the writing signal from the second input/output pin and buffing the writing signal to the controlling circuit, wherein the controlling circuit writes data to the memory array according to the writing signal.