Patent ID: 8467440
Filing Date: 2013-06-18
Classification: H04L

Abstract:
1. A method of generating one or more clock signals in a receiver employing decision-feedback equalization comprising: sampling a received signal, having a period T, using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively; performing a decision-feedback equalization correction on the data sample signal using a decision-feedback equalizer to generate decision-feedback equalization detected data bits, the equalizer having at least one tap and the at least one tap having a coefficient; latching the transition sample signal after it has been sliced using a weighted threshold value to generate transition data bits; and generating one or more phase updates for at least one of the data clock and the transition clock based on the decision-feedback equalization detected data bits and the transition data bits; wherein the weighted threshold value is calculated from at least one delayed bit of the decision-feedback equalization detected data bits multiplied by the coefficient of the at least one tap.