Patent ID: 7039854
Filing Date: 2006-05-02
Classification: H03M

Abstract:
1. An apparatus for performing syndrome computation in a decoder of a forward error correction (FEC) system, the apparatus comprising syndrome computation logic configured to use a partial parity-check matrix to recursively generate intermediate syndrome vectors based on a code word received by the decoder and to modulo-2 add the recursively generated intermediate syndrome vectors together until a final resolved syndrome vector has been generated, wherein said syndrome computation logic comprises: Galois field matrix multiplication logic configured to multiply a plurality of receive vectors of the code word, each having a plurality of receive bits, by the partial parity-check matrix to compute the intermediate syndrome vectors: binary multiplication logic configured to multiply respective constant coefficient values by respective intermediate syndrome vectors computed by the Galois field multiplication logic in an immediately preceding cycle; binary addition logic configured to modulo-2 add respective intermediate syndrome vectors computed in a current cycle by the Galois field multiplication logic to respective intermediate syndrome vectors computed by the Galois field multiplication logic in said immediately preceding cycle; and memory element logic configured to store the intermediate syndrome vectors and results of the recursive modulo-2 addition of the intermediate syndrome vectors, and wherein after a particular number of intermediate syndrome vectors have been recursively generated and modulo-2 added together, the memory element contains a final resolved syndrome vector.