Patent ID: 7539055
Filing Date: 2009-05-26
Classification: G11C,H01L

Abstract:
1. A method for controlling a non-volatile semiconductor memory comprising a plurality of cell columns arranged in a row direction, each of the cell columns comprising an arrangement of memory cell transistors, a first select gate transistor arranged adjacent to an end of the arrangement, and a second select gate transistor arranged adjacent to another end of the arrangement, each of memory cell transistors comprising: a source region in contact with a buried insulating layer on a supporting substrate; a drain region in contact with the buried insulating layer and having a conductivity type that is the same as the source region; and a channel region provided between the source region and the drain region so as to contact the buried insulating layer and having the conductivity type that is the same as the source region, the method comprising: applying a precharge voltage to a selected bit line connected to a selected cell column in a reading operation; applying a select voltage to a selected word line shared by each one of selected memory cell transistors of the cell columns in the reading operation; applying a non-select voltage to a non-selected word line shared by non-selected memory cells of the cell columns in the reading operation; and if the channel region has n-type, applying a substrate voltage less than 0 V or, if the channel region has p-type, applying another substrate voltage more than 0V, to the supporting substrate of the first and second select gate transistors, the supporting substrate of the selected cell column during the reading operation.