Patent ID: 6678849
Filing Date: 2004-01-13
Classification: G01R

Abstract:
A semiconductor integrated circuit comprising:a plurality of m stages, each stage including a plurality of flip flops, and every nth stage of said plurality of m stages being connected to each other to form a scan chain for a scan test, where m and n are integers and m is greater than n; a plurality of combination circuits respectively placed among said plurality of stages, wherein at least one of said plurality of combination circuits includes a feedback or skip path from another of said plurality of combination circuits, and said at least one of said plurality of combination circuits is in one of a plurality of groups as a feedback/skip combination circuit, each of the groups including (1) an nth stage and (2) combination circuits and stages coupled between the nth stage and next nth stage; at least one test path, in the scan test, each test path being connected between an input of the feedback/skip combination circuit and an output of one of the m stages in a group other than the group including said feedback/skip combination circuit, said one of the m stages corresponding, in sequential order in a group, to another of the m stages in said group including the feedback/skip combination circuit, said another of the m stages being connected to inputs of the feedback/skip combination circuit, to compensate for the presence of said feedback or skip path; and at least one test circuit placed on said at least one test path, said at least one test circuit selectively actuating said at least one test path in a scan test.