Patent ID: 6415404
Filing Date: 2002-07-02
Classification: G01R

Abstract:
A method of designing a scan path construction of a test facile semiconductor integrated circuit with scan paths, comprising the steps of:counting the number of flip-flops to be subjected to a scan path test in each-of logic blocks; calculating an average number of flip-flops per scan path from the number of scan paths and the overall number of flip-flops in the semiconductor integrated circuit; reading pin layout information and floor plan information of each of the logic blocks; assigning scan paths to the logic blocks from a selected logic block serving as a start point; repeating the step of assigning the scan paths for all combinations of logic blocks; and determining a scan path assigning arrangement in which the overall length of interconnections between the logic blocks is the shortest, based on the results of the assigning the scan paths for all combinations of logic blocks.