Patent ID: 6684317
Filing Date: 2004-01-27
Classification: H04L

Abstract:
A method of addressing sequential data packets from a plurality of input data line cards to enable their memory storage in successive shared memory block sections of an output-buffered switch fabric, each assigned to a queue dedicated for an output port, that comprises, connecting a plurality of similar subaddress generators successively in a closed ring structure, with each subaddress generator being capable of assigning addresses for predetermined size data byte packets of input data traffic received in a plurality of successive time slots to produce packet composition into super packets that are ordered based on time of arrival; allocating a continuous memory block for a super packet by assigning an initial super packet address in the destination queue from a subaddress generator; thereupon generating the starting address of the next super packet by adding the super packet size to said initial starting address and moving to the next subaddress generator sequentially along the successive subaddress generators of the ring, thereby sequentially allocating memory in the shared memory sections from subaddress generator to subaddress generator along said ring; and, upon the assigning of an address to each super packet, producing packet decomposition at the corresponding subaddress generator by simultaneously assigning addresses for the individual packets in the super-packet, based on their arrival order.