Patent ID: 8759844
Filing Date: 2014-06-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a memory cell region having a memory device and a cell transistor electrically connected to the memory device, and a peripheral circuit region in which a peripheral circuit transistor is formed, wherein the cell transistor comprises, in a first active area of a semiconductor substrate zoned by a shallow trench isolation (STI); a first gate electrode; first source/drain regions formed on both sides of the first gate electrode; and a first selectively epitaxially growth semiconductor layer formed on the first source/drain regions, wherein the peripheral circuit transistor comprises, in a second active area of the semiconductor substrate zoned by a STI; a second gate electrode; second source/drain regions of an LDD structure including a high density impurity diffusion layer formed on both sides of the second gate electrode; and elevated source/drain regions formed from a second selectively epitaxially growth semiconductor layer formed on the second source/drain regions, wherein the first and second selectively epitaxially growth semiconductor layers of the cell transistor and the peripheral circuit transistor, respectively, have a substantially same thickness such that the semiconductor layers provided on the first active areas of adjacent cell transistors opposite to each other do not contact each other, wherein a surface of the STI in the peripheral circuit region is drawn back from a surface of the semiconductor substrate, and the second selectively epitaxially growth semiconductor layer of the peripheral circuit transistor includes a semiconductor layer also epitaxially grown from a side of the semiconductor substrate exposed by the surface of the STI being drawn back so as to position a facet of the semiconductor layer outside the second active area, and wherein a surface of the STI in the memory cell region is not drawn back from a surface of the semiconductor substrate.