Patent ID: 6661292
Filing Date: 2003-12-09
Classification: H04H

Abstract:
A phase-locked loop circuit for demodulating a Radio Data System (RDS) signal superimposed on an ARI signal component of a stereo-multiplex signal, the circuit comprising:an oscillator that generates an in-phase component signal and a quadrature component signal of the carrier of the RDS signal; a first circuit branch comprising a first multiplier having a first input at which a sampled stereo-multiplex signal is received and a second input at which the in-phase component signal is received, a first low-pass filter having an input connected to an output of the first multiplier, a first divider having an input connected to an output of the first low-pass filter, and a first high-pass filter having an input connected to an output of the first divider; a second circuit branch comprising a second multiplier having a first input at which the sampled stereo-multiplex signal is received, and a second input at which the quadrature component signal is received, a second low-pass filter having an input connected to an output of the second multiplier, a second divider having an input connected to an output of the second low-pass filter, and a second high-pass filter having an input connected to an output of the second divider; a feedback branch comprising an arithmetic unit having first and second inputs connected to outputs of the first and second high-pass filters, respectively, a clock input at which an RDS bit clock signal is received, and an output at which the arithmetic unit generates an error signal; a filter having an input at which it receives the error signal, and an output at which it generates a filtered error signal; a control unit having an input connected to the filter output, and an output connected to a control input of the oscillator at which the control unit generates a control signal in response to the filtered error signal; a clock generator having a first control input connected to the output of the first high-pass filter, a second control input connected to an output of the oscillator, and an output at which the clock generator generates the RDS bit clock signal; and an RDS decoder having a first input connected to the output of the first high-pass filter, a clock input at which the RDS bit clock signal is received, and an output from which RDS data is retrievable.