Patent ID: 6617233
Filing Date: 2003-09-09
Classification: H01L,Y10S

Abstract:
A process of fabricating an anti-fuse, comprising:providing a substrate; forming an inter-metal dielectric layer on the substrate; forming a funnel-shaped via in the inter-metal dielectric layer; forming a first conductive layer over the inter-metal dielectric layer and filling the first conductive layer into the funnel-shaped via, wherein a key hole is formed in the bottom side of the funnel-shaped via; removing the first conductive layer outside the funnel-shaped via to form a conductive plug, wherein the key hole in the conductive plug is not exposed; performing an oxide chemical mechanical polishing process to smooth the conductive plug and to make the top side of the conductive plug protrude from the inter-metal dielectric layer; covering a dielectric layer on the top side of the conductive plug; forming a top plate on the dielectric layer; forming an insulating layer over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate; and forming a second conductive layer over the insulating layer and filling the second conductive layer into the via.