Patent ID: 8341499
Filing Date: 2012-12-25
Classification: G06F

Abstract:
1. A method for identifying errors in the memory of a computer system, comprising: generating a set of cyclic redundancy code bits from a set of data bits and respective address bits; saving a first portion of the data bits and the cyclic redundancy bits through a first memory channel; saving a duplicate of the first portion of the data bits and the cyclic redundancy bits through a second memory channel; saving a second portion of the data bits and the cyclic redundancy bits through the second memory channel; saving a duplicate of the second portion of the data bits and the cyclic redundancy bits through the first memory channel; retrieving the first portion of the data bits and the cyclic redundancy code bits through the first memory channel and the second portion of the data bits and the cyclic redundancy code bits through the second memory channel; generating a second set of cyclic redundancy code bits on the basis of the retrieved data bits; and comparing the retrieved cyclic redundancy code bits with the second set of the cyclic redundancy code bits.