Patent ID: 8239612
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. A memory controller for controlling access to a flash memory having physical blocks, in which stored data is erased, based on access instructions supplied from a host system, the memory controller comprising: a block controller which controls a correspondence relation between the physical blocks and logical blocks, which are composed of plural sectors in a logical address space in the host system, and which assigns the logical blocks to the physical blocks; a data writing module which writes data supplied from the host system into the physical blocks corresponding to the logical blocks based on the access instructions; a global counter which serves as a common counter of the plural physicals blocks, and which updates a global count number every time any logical block is newly assigned to a physical block; a count information writing module which writes count information based on the global count number into any physical block to which any logical block is newly assigned; a determining module which determines whether or not to transfer stored data in a specific physical block to another physical block in accordance with the global count number and specific count information stored in the specific physical block; and a data transfer module which transfers the stored data in the specific physical block storing the specific count information to another physical block based on a determination by the determining module to transfer the stored data.