Patent ID: 9077361
Filing Date: 2015-07-07
Classification: H03M,H04L

Abstract:
1. A phase estimator comprising: a first input terminal configured to receive a first analogue input signal; a second input terminal configured to receive a second analogue input signal, wherein the second analogue input signal is 90° out of phase with the first analogue input signal; a register configured to store N bits as a digital word, where N is greater than one, the register comprising a register input terminal that is connectable to each of the bits in accordance with a pointer value, and a register output terminal configured to provide the digital word; a first reference signal generator configured to receive the digital word from the register and the first analogue signal, and provide a first analogue reference signal as the product of the first analogue signal and sin(2π*digital word); a second reference signal generator configured to receive the digital word from the register and the second analogue signal, and provide a second analogue reference signal as the product of the second analogue signal and cos(2π*digital word); a comparator configured to compare the first analogue reference signal with the second analogue reference signal and provide to the input terminal of the register a binary feedback signal in accordance with the result of the comparison; and wherein the output terminal of the register is configured to provide the digital word, wherein the digital word is representative of the phase of the first analogue input signal and the second analogue input signal.