Patent ID: 6689654
Filing Date: 2004-02-10
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit device, comprising:forming a source region and a drain region in a substrate; forming a gate pattern on the substrate between the source region and the drain region; forming a first insulating layer on the substrate and the gate pattern; forming a second insulating layer on the first insulating layer; etching the second insulating layer to form spacers on sidewalls of the gate pattern; etching the first insulating layer using the spacers as a mask to expose at least a portion of at least one of the source region and the drain region; epitaxially growing a lower pad layer on the exposed portion of the at least one of the source region and the drain region; etching the spacers to expose the first insulating layer on sidewalls of the gate pattern and on at least a portion of the at least one of the source region and the drain region; and forming a conductive layer on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern.