Patent ID: 7370127
Filing Date: 2008-05-06
Classification: G06F

Abstract:
1. An internal bus architecture for modules in an integrated circuit (IC), said internal bus architecture comprising: at least two source interface units and at least two destination interface units for interfacing with the modules of said IC; and at least one basic modular unit coupled to said source interface units and to said destination interface units, the at least one basic modular unit comprising an upload unit for transferring upstream data; and a download unit for transferring downstream data; the upload unit and the download unit in each of said basic modular units being mutually independent and being adapted under control of a transaction protocol to simultaneously transfer upstream data and downstream data; the upload unit comprising a buffer having a pair of internal-buffers for temporary storage of data to be transferred from the source interface unit to the destination interface unit, wherein data from either internal buffer can be transferred in a single clock cycle.