Patent ID: 9134373
Filing Date: 2015-09-15
Classification: G06F

Abstract:
1. A computer comprising: a processor; and memory communicatively coupled to the processor, wherein the memory is encoded with instructions for determining a common sequence of statements from one or more sets of ordered statements, and wherein the instruction when executed by the processor include: determining a maximum number of channel mask enable encodes on the semiconductor chip; determining a maximum number of channel mask enable encodes used for a first HTB and a second HTB; sorting a plurality of test patterns used to test the first HTB and the second HTB into one or more mask sets, the sorting dependent on the number of masks each test pattern needs, the mask sets increase in mask number from a zero mask set having zero channel mask enable encodes to a mask set having the maximum number of channel mask enable encodes used for the respective HTBs; and combining test patterns of the mask sets of the first HTB and the second HTB to be performed simultaneously, wherein the number of masks per scan cycle of the combined mask sets is no more than the maximum number of channel mask enable encodes on the semiconductor chip and there is no scan slice overlap.