Patent ID: 7948287
Filing Date: 2011-05-24
Classification: G11C,H03L

Abstract:
1. A DLL circuit for a semiconductor memory apparatus, comprising: a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and receives a reference clock signal, and a plurality of fine delayers, which receive output clock signals of the respective coarse delayers; a delay control section configured to compare phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal thereby generating coarse control signals for controlling the coarse delayers, and to compare phases of a fine feedback clock signal with the reference clock signal thereby generating fine control signals for controlling the fine delayers; and a duty cycle correction section configured to correct duty ratios of clock signals outputted by the fine delayers thereby generating internal clock signals, wherein the fine feedback clock signal is an output clock signal of a fine delayer received with the output clock signals of the final coarse delayer, wherein the delay line receives the coarse control signals and the fine control signals, and outputs, as output signals, the clock signals outputted by the fine delayers that receive the fine control signals, wherein each of the fine delayers delays output clock signals of a corresponding one coarse delayer among the coarse delayers in response to the fine control signals, and wherein each of the fine delayers lacks an input-output relationship with others of the fine delayers.