Patent ID: 9047987
Filing Date: 2015-06-02
Classification: G06F,G11C

Abstract:
1. A system architecture for testing a plurality of memory storage devices comprising: a central processing system; wherein the central processing system comprises at least a first operating system; a plurality of electronic bridges; each of the electronic bridges connected on one side to the central processing system via a standard I/O channel and on the other side to the plurality of memory storage devices through one of a plurality of multiplexers with the plurality of electronic bridges presenting the plurality of memory storage devices to the central processing system as standard memory peripherals; and a second processing system which on one side is connected to the central processing system and on the other side is connected to the plurality of memory storage devices via the plurality of multiplexers thus providing the second processing system direct access to the plurality of memory storage devices, wherein the second processing system comprises at least a second operating system and a mechanism for fully testing the command set of the plurality of memory storage devices, wherein one of the plurality of multiplexers alternatively connects one of the plurality of electronic bridges to one of the plurality of memory storage devices or the second processing system to one of the plurality of memory storage devices.