Patent ID: 6088820
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A static semiconductor memory device having a test mode for detecting a defective memory cell readily allowing inversion of stored data, comprising:a memory array including a plurality of memory cells arranged in rows and columns, a word line provided corresponding to each of said rows and a pair of bit lines provided corresponding to each of said columns;a data input/output circuit for externally inputting/outputting data to and from said memory array;a first power supply line for supplying an external power supply potential for a portion other than said memory cell;a second power supply line connected to a power supply node of each of said memory cells;internal power supply potential generation means connected between said first and second power supply lines and applying said external power supply potential to said second power supply line during normal operation and applying an down-converted potential down-converted from said external power supply potential to said second power supply line during said test mode; anda first transistor connected between said second power supply line and a line for a reference potential lower than said down-converted potential and made conductive with a predetermined resistance value in a conductive state during said test mode.