Patent ID: 6574161
Filing Date: 2003-06-03
Classification: G11C,H03K

Abstract:
A semiconductor integrated circuit device comprising:a memory array having a plurality of memory cells arranged in rows and columns; a plurality of word lines disposed so as to corresponding to the rows respectively and connected with the memory cells on corresponding rows; a plurality of decoders disposed corresponding to respective pairs of two word lines, each the decoder decoding a first address signal specifying a word line pair and outputting a decode signal indicative of the result of decoding therefrom; a global high voltage supply line for transmitting a high voltage generated from a high voltage generating circuit; first and second main high voltage transmission lines coupled to said global high voltage supply line; first and second sub high voltage transmission lines each supplied with the high voltage from said global high voltage supply line, said first and second sub high voltage transmission lines transmitting the supplied high voltage and disposed in parallel to and away from said first and second main high voltage transmission lines; first and second switching transistors respectively connected between said global high voltage supply line and said first sub high voltage transmission line and between said global high voltage supply line and said second sub high voltage transmission line, for connecting said global high voltage supply line and a corresponding sub high voltage transmission line to each other upon conduction thereof; and regions for forming first and second word drivers provided corresponding to said plurality of decoders respectively and disposed in line along a row extending direction.