Patent ID: 6591349
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A computer system, comprising:a processor including a memory controller containing a page table, a precharge queue, a Row-address-select (â€œRASâ€ ) queue, a Column-address-select (â€œCASâ€ ) Read queue, and a CAS Write queue, wherein said page table is organized into a plurality of rows, each row able to store an address of an open memory page; a system memory coupled to said processor, said system memory containing a plurality of memory devices, each of said memory devices containing a plurality of memory banks; said memory controller receiving a plurality of read requests and write requests; and a multiplexer coupled to said CAS Read queue and said CAS Write queue, said multiplexer streaming a group of said read requests and separately streaming a group of said write requests to main memory resulting in fewer bus turnarounds.