Patent ID: 6462579
Filing Date: 2002-10-08
Classification: H03K

Abstract:
A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA, said bus macro comprising:at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over said at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in said first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over said at least one row of bus lines from said second design area to said first design area of the FPGA according to a second routing configuration embedded in said second design area; wherein the first and second design areas are separate and independent areas of the FPGA; wherein the first design comprises frames of columns disposed on one side of a center of the at least one row of bus lines; wherein the second design area comprises frames of columns disposed on the other side of the center of the at least one row of bus lines; and wherein the at least one row of bus lines are disposed transverse to said columns of the first and second design areas.