Patent ID: 8922263
Filing Date: 2014-12-30
Classification: G06F,H04W,Y02D

Abstract:
1. A semiconductor integrated circuit comprising: an input interface externally supplied with an input signal; and an internal core circuit supplied with signal data generated at the input interface as the result of reception of the input signal by the input interface, wherein the input interface comprises a hysteresis circuit and a data sampling unit, wherein the hysteresis circuit of the input interface has a first input threshold and a second input threshold and thus the hysteresis circuit detects as a sleep command the input signal having a predetermined voltage range between the first input threshold and the second input threshold, wherein the data sampling unit of the input interface selects a phase of a sampling clock signal appropriate to sample data according to the data pattern of a synchronizing signal supplied as the input signal and the data sampling unit uses a sampling clock signal having the selected phase to sample payload data contained in the input signal, wherein when the hysteresis circuit of the input interface detects the sleep command, a sleep signal generated at the hysteresis circuit is supplied to the internal core circuit and the internal core circuit is controlled into sleep mode in response to the sleep signal, wherein the sleep signal generated at the hysteresis circuit is also supplied to the data sampling unit of the input interface and as a result the data sampling unit is controlled into sleep mode in response to the sleep signal, wherein the data sampling unit comprises a plurality of data sampling circuits and a clock selection data determination circuit, wherein the data sampling circuits sample the data pattern of the synchronizing signal in parallel by a plurality of clock signals different in phase from one another, wherein the clock selection data determination circuit generates a plurality of clock signal selection signals in response to a plurality of output signals outputted from the data sampling circuits and thereby selects one clock signal as reference clock signal from among the clock signals to generate the sampling clock signal used for sampling the payload data, wherein after selection of the reference clock signal, one data sampling circuit for generating the selected one clock signal is activated among the data sampling circuits and the other data sampling circuits for generating other unselected clock signals are deactivated, wherein the data sampling unit stores into a memory the payload data sampled by the sampling clock, wherein the data sampling unit generates a data end signal in response to the completion of storage of the payload data into the memory, wherein the input interface further comprises a sleep determination circuit that is supplied with the sleep signal generated at the hysteresis circuit and the data end signal generated at the data sampling unit and thereby generates a sleep transition signal, wherein the sleep determination circuit asserts the sleep transition signal in response to both the sleep signal and the data end signal being asserted, wherein the internal core circuit and the data sampling unit are controlled into the sleep mode in response to the sleep transition signal asserted by the sleep determination circuit, and wherein the input interface is configured as a differential signal interface supplied with a differential input signal as the input signal.