Patent ID: 7995392
Filing Date: 2011-08-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines and which, in a first erase operation, erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation at a first verify level, finds the number of cells k (k≦n) (k is a natural number equal to or larger than 1) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out a second erase operation using the second erase voltage.