Patent ID: 8902667
Filing Date: 2014-12-02
Classification: G11C

Abstract:
1. An integrated non-volatile memory (NVM) system, comprising: an array of non-volatile memory (NVM) cells; bias voltage generator circuitry configured to generate bias voltages for the NVM cells; controller circuitry configured to determine performance degradation for the NVM system based upon an interim verify operation relating to at least one of a program operation or an erase operation conducted after a predetermined number of program or erase pulses and before a maximum number of program or erase pulses is reached and to adjust at least one voltage level for the bias voltages generated by the bias voltage generator circuitry based upon results of the interim verify operation, the interim verify level for the interim verify operation being a voltage level between a default erase verify voltage level and a default program verify voltage level; wherein the controller circuitry is further configured to continue the at least one of a program operation or an erase operation for the NVM system using the at least one adjusted voltage level after the interim verify operation.