Patent ID: 6576945
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A compact DRAM cell array which comprises:a plurality of annular memory cells, which are arranged in rows and columns, each annular memory cell positioned within a trench and including a vertical MOSFET and an underlying capacitor surrounded by an annular ring wherein said vertical MOSFET and said underlying capacitor are in electrical contact to each other through a buried-strap outdiffusion region which is present within a portion of said annular ring of each annular memory cell such that said portion partially encircles said annular memory cell, the remaining portions of said annular ring of each annular memory cell have a body contact region which serves to electrically connect said annular memory cell to an adjacent array well region, said annular ring of each annular memory cell is self-aligned to said trench; a plurality of wordlines overlaying said vertical MOSFETS, said plurality of wordlines being arranged in said row direction; and a plurality of bitlines that are orthogonal to said plurality of wordlines.