Patent ID: 6339006
Filing Date: 2002-01-15
Classification: G11C,H01L

Abstract:
A method of manufacturing a flash EEPROM cell, comprising the steps of:sequentially forming a tunnel oxide film, a polysilicon layer for a floating gate and a hard mask layer on a semiconductor substrate; patterning said hard mask layer and then forming a hard mask layer spacer at the etching side of the patterned hard mask layer; removing the exposed portion of the polysilicon layer for the floating gate by etching process using said patterned hard mask layer and said hard mask layer spacer as etching masks thus to form first and second patterns that are separated in two; removing said patterned hard mask layer and said hard mask layer spacer and then depositing a dielectric film and a polysilicon layer for a floating gate on the entire structure, thus forming a first floating gate, a second floating gate and a control gate by self-aligned etching process, wherein the first floating gate and the second floating gate are different in size; and forming a drain junction and a source junction by cell source/drain ion implantation process.