Patent ID: 6404696
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A serial-access semiconductor memory device comprising:an array of memory cells, subdivided into a plurality of sections, including first and second sections each of which includes a plurality of subsections each having a preselected number of memory cells, said first and second sections constituting first and second memory banks, respectively; a first address bus section for said first memory bank, said first address bus section coupled to a first decoder connected to said first memory bank; a second address bus section for said second memory bank, said second address bus section coupled to a second decoder connected to said second memory bank; a first data transmission line associated with said first memory bank and connected to respective memory cells of each subsection in said first memory bank; a second data transmission line associated with said second memory bank and connected to respective memory cells of each subsection in said second memory bank; and latch circuits, coupled to said first and second address bus sections, for independently latching address select signals for said each memory banks; wherein said first and second data transmission lines are coupled to read data latches for receiving data bits and transferring the data bits to a data out buffer according to an internal clock associated with an input clock.