Patent ID: 7213182
Filing Date: 2007-05-01
Classification: G01R

Abstract:
1. A test apparatus for testing a device under test, comprising: an instruction execution unit for sequentially executing instructions included in a test program for said device under test in each instruction cycle; a default pattern memory for storing one or more default pattern sequences to be associated with one or more pieces of default pattern identification information for identifying said default pattern sequences, respectively, said default pattern sequences being preset ones of a plurality of test pattern sequences, each of which is formed by a plurality of test patterns to be sequentially output to a terminal of said device under test during an instruction cycle period; a test pattern memory for storing, for each of said instructions, test pattern sequences that are output in instruction cycle periods in which said instructions are executed or said default pattern identification information for identifying said default pattern sequences that are output in said instruction cycle periods; a test pattern memory read unit for reading, when one of said instructions is executed, said test pattern sequences or said default pattern identification information that are stored to be associated with one of said instructions in said test pattern memory; a default pattern read unit for reading, if said test pattern memory read unit read said default pattern identification information, said default pattern sequences that are stored to be associated with said default pattern identification information in said default pattern memory; and a test pattern output unit for outputting said test pattern sequence read out by said test pattern memory read unit, corresponding to one of said instructions, or said default pattern sequence read out by said default pattern read unit to a terminal of said device under test during an instruction cycle period for executing one of said instructions.