Patent ID: 7536692
Filing Date: 2009-05-19
Classification: G06F,H04L

Abstract:
1. A processor, comprising: an instruction store configured to store instructions of at least a portion of at least one program; and multiple engines coupled to the instruction store, individual ones of the multiple engines providing multiple execution threads, wherein each said multiple engines include an engine instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, different respective portions of the engine instruction cache being allocated to different respective ones of the threads, the engine instruction cache including a shared portion allocated for sharing by the threads, the shared portion storing instructions that are not victimized; wherein the instruction store comprises an L2 instruction cache and the engine instruction store comprises an L1 instruction cache; and wherein the processor further comprising at least one of the following: an interface to a switch fabric, an interface to a media access controller (MAC), and an interface to a physical layer (PHY) device.