Patent ID: 7889538
Filing Date: 2011-02-15
Classification: G11C

Abstract:
1. A three-dimensional memory device comprising: a plurality of mats laminated therein, each having memory cells arranged in a two-dimensional manner; and access signal lines and data lines to select memory cells in each mat being shared between respective adjacent mats, laminated mats being divided into three or more groups, and, when selecting one of these groups, memory cells in some of the remaining groups being biased so that a leakage current flows there through, while memory cells in the rest of the remaining groups being biased so that a leakage current is reduced, wherein each of the mats includes memory cells positioned at cross-points of the access signal lines and the data lines, each of the memory cells having a variable resistance element and a diode connected in series, the variable resistance element being capable of setting a resistance value in a reversible manner by applying voltage, and diodes between the access signal lines and the data lines are set to reverse-biased state in the some of the remaining groups, while diodes between access signal lines and data lines are set to substantially-zero-biased state in the rest of the remaining groups.