Patent ID: 8327119
Filing Date: 2012-12-04
Classification: G06F

Abstract:
1. A hardware apparatus in a microprocessor for executing a bit scan instruction, wherein the bit scan instruction specifies an input operand comprising N bytes, wherein N is at least two, the apparatus comprising: a first encoder, configured to forward bit scan encode each of the N bytes of the input operand to generate N first bit vectors; a zero detector, configured to zero-detect each of the N bytes of the input operand to generate a second bit vector; a second encoder, configured to forward bit scan encode the second bit vector to generate a third bit vector; and an N:1 multiplexor, controlled by the third bit vector to select one of the N first bit vectors to output a fourth bit vector; wherein the apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand.