Patent ID: 9015452
Filing Date: 2015-04-21
Classification: G06F

Abstract:
1. A method for performing an approximate division on a digital signal processor having a plurality of registers, each register storing data of N bits, and a plurality of work units, each work unit performing data processing operations under instruction control, the steps comprising: storing a first numerator operand of N/2 bits in a set of N/2 most significant bits of a first register of the plurality of registers; storing a second numerator operand of N/2 bits in a set of N/2 least significant bits of the first register; storing a first denominator operand of N/2 bits in a set of N/2 most significant bits of a second register of the plurality of registers; storing a second denominator operand of N/2 bits in a set of N/2 least significant bits of the second register; employing one of the work units to separately employing one of the work units to extract the first absolute value from the third register; employing one of the work units to determine a number of unused bits in the first absolute value; employing one of the work units to generate a headroom h employing one of the work units to compute a first shift factor s employing one of the work units to extract the second absolute value from the third register; employing one of the work units to determine a number of unused bits in the second absolute value; employing one of the work units to generate a second headroom h employing one of the work units to compute a second shift factor s employing one to the work units to generate a first intermediate result by left shifting the data in the third register by an amount of the first headroom h employing one of the work units to generate a first division LUT index i employing one to the work units to generating a second intermediate result by left shifting the data in the third register by an amount of the second headroom h employing one of the work units to generating a second division LUT index i employing one of the work units to generate a third intermediate result by performing an exclusive OR of data in the first register and data in the second register; employing one of the work units to extract a most significant bit of the most significant bits of the third intermediate result; employing one of the work units to generate a sign of a first division m employing one of the work units to extract a most significant bit of the least significant bits of the third intermediate result; employing one of the work units to generate a sign of a second division m employing one of the work units to generate a first look-up table value by indexing a look-up table with the first division LUT index i employing one of the work units to generate a second look-up table value by indexing a look-up table with the second division LUT index i employing one of the work units to the store first look-up table value in most significant bits of a fourth register of the plurality of registers and store the second look-up table value in least significant bits of the fourth register; employing one of the work units to generate a first product by multiplying the most significant bits of the fourth register by the most significant bits of the third register; employing one of the work units to generate a first absolute division value by performing a saturated left shift of the first product by the headroom h employing one of the work units to generate a first division value by multiplying the first absolute division value by the sign of a first division m employing one of the work units to generate a second product by multiplying the least significant bits of the fourth register by the least significant bits of the third register; employing one of the work units to generate a second absolute division value by performing a saturated left shift of the second product by the headroom h employing one of the work units to generate a second division value by multiplying the second absolute division value by the sign of a second division m employing one of the work units to generate a packed division by storing the first division value in most significant bits of a fifth register of the plurality of registers and storing the second division value in least significant bits of the fifth register.