Patent ID: 7307315
Filing Date: 2007-12-11
Classification: H01L

Abstract:
1. A scaled planar DMOS transistor structure, comprising: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a lightly-doped epitaxial semiconductor layer being formed on a heavily-doped semiconductor substrate; a scalable source region being defined to be surrounded by a planar gate region, wherein the scalable source region comprises a moderately-doped base diffusion region of a second conductivity type being formed in the lightly-doped epitaxial semiconductor layer through a ring-shaped implantation window, a heavily-doped source diffusion ring of the first conductivity type being formed in a surface portion of the moderately-doped base diffusion region through the ring-shaped implantation window, a heavily-doped base contact diffusion region of the second conductivity type being formed in a middle surface portion of the moderately-doped base diffusion region through a self-aligned implantation window surrounded by a sacrificial dielectric layer being formed to fill a gap in the ring-shaped implantation window, and a self-aligned source contact window being formed on a semiconductor surface formed by the heavily-doped base contact diffusion region surrounded by the heavily-doped source diffusion ring and the heavily-doped source diffusion ring surrounded by a sidewall dielectric spacer; the planar gate region being formed on a gate dielectric layer outside of the scalable source region, wherein the planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on the gate dielectric layer and a patterned capping dielectric layer being formed on the patterned heavily-doped polycrystalline-silicon gate layer; and a source metal layer being at least formed on the self-aligned source contact window.