Patent ID: 6479894
Filing Date: 2002-11-12
Classification: H01L,H05K

Abstract:
A semiconductor package substrate, comprising:(a) a plurality of predefined package sites on the substrate, each neighboring pair of package sites being delimited by a singulation line; each package site including: (a-1) at least one die-mounting area; (a-2) at least one row of via lands alongside the singulation line, with the opposite row of via lands within the neighboring package site across the singulation line being substantially aligned crosswise in line; and (a-3) a plurality of electrically-conductive traces for electrically connecting the chip-mounting area to the via lands; and (b) a plating bus for interconnecting all the via lands on both sides of the singulation line, which includes: (b-1) a plurality of crosswise segments, each being used to interconnect one crosswise-opposite pair of the via lands across the singulation line; and (b-2) a plurality of diagonal segments, each being used to interconnect one neighboring pair of the crosswise segments diagonally to each other across the singulation line.