Patent ID: 6777298
Filing Date: 2004-08-17
Classification: H01L,Y10S

Abstract:
A method for forming spaced apart source and drain regions having areas for contact, said method comprising the steps of:selecting a silicon containing substrate, forming a dielectric layer having a thickness of from about 1 to about 10 nm suitable for the gate insulator of a field effect transistor, forming a gate electrode layer over said dielectric layer, patterning said gate electrode layer to form a gate electrode over said dielectric layer, forming a temporary spacer on the sidewalls of said gate electrode by forming a dielectric liner of a first material and one of a dielectric or silicon containing layer of a second material, anisotropic etching said second material, whereby said second material forms a sidewall spacer of controlled width which is determined by the original thickness of the layer of said second material, performing blanket ion implantation on the resulting structure, whereby ions pass through said dielectric liner of said first material and are substantially absorbed where incident on said sidewall spacer of said second material and whereby said liner of said first material underneath said sidewall spacer is protected, selectively removing said second material with respect to said first material, selectively wet etching said first material where damaged by ion implantation, whereby said first material remains on the sidewalls of said gate electrode and remains where said first material was formerly underneath said second material of said sidewall spacer and protected from ion implantation, and annealing said ion implanted regions in said silicon containing substrate to form source and drain regions electrically contactable through openings in said first material.