Patent ID: 8072837
Filing Date: 2011-12-06
Classification: G06F,G11C,Y02D

Abstract:
1. A circuit configured to be mounted on a memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another in response to a first number of DDR chip-select signals, the first number of ranks comprising a first number of DDR memory circuits, the circuit including at least one configuration in which the circuit is configured to: receive a set of signals comprising address signals and a second number of DDR chip-select signals, the address signals comprising bank address signals, wherein the received set of signals are capable of controlling a memory module having a second number of ranks, each rank of the second number of ranks comprising a second plurality of DDR memory circuits that are configured to be activated concurrently with one another, the second number of ranks comprising a second number of DDR memory circuits, the second number of ranks smaller than the first number of ranks, the second number of DDR chip-select signals smaller than the first number of DDR chip-select signals, and the second number of DDR memory circuits smaller than the first number of DDR memory circuits; monitor command signals received by the memory module; selectively isolate a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system in response to the command signals; and generate and provide the first number of DDR chip-select signals to the DDR memory circuits of the first number of ranks in response at least in part to the received bank address signals and the received second number of DDR chip-select signals.