Patent ID: 8307370
Filing Date: 2012-11-06
Classification: G06F

Abstract:
1. An apparatus to balance a load in a multi-core processor system, the apparatus comprising: a plurality of processing cores configured to process a plurality of threads; a data channel module comprising a queue that stores data that is transmitted between the plurality of threads while the plurality of threads are being processed by the plurality of processing cores, wherein the data channel module generates queue state information each time the queue is full and/or each time the queue is empty; a data channel management module configured to analyze data traffic between the plurality of threads based on the queue state information, and to generate load adjustment information used to adjust a load of the plurality of threads based on the analyzed data traffic between the plurality of threads while the plurality of threads are being processed by the plurality of processing cores; and a scheduler configured to adjust the load of the plurality of processing cores by dynamically adjusting the processing core occupancy of one or more threads after the plurality of threads have been loaded to the plurality of processing cores, based on the load adjustment information generated by the data channel management module, wherein the data channel management module periodically counts a number of times that the queue is empty or the number of times the queue is full, over a predetermined time period, and calculates a state average by averaging a result of the periodic counting, and the scheduler adjusts the load of the plurality of processing cores based on a comparison of the number of times that the queue is empty or the number of times the queue is full, during the predetermined time period, in comparison to the state average.