Patent ID: 8383461
Filing Date: 2013-02-26
Classification: H01L,H05K

Abstract:
1. A method for manufacturing a semiconductor package, comprising the steps of: attaching a first conductive layer on an upper surface of a carrier substrate; defining recesses in the upper surface of the carrier substrate by patterning the first conductive layer and the carrier substrate; forming a metal seed layer on the first conductive layer and on portions of the upper surface of the carrier substrate which define the recesses; forming a plating layer on the metal seed layer such that the plating layer fills the recesses defined on the upper surface of the carrier substrate, the plating layer filling the recesses being bumps; and forming first circuit patterns by patterning the plating layer, the metal seed layer, and the first conductive layer, the first circuit patterns comprise bumps filling the recesses which are defined in the upper surface of the carrier substrate; forming an insulation layer on the upper surface of the carrier substrate including the first circuit patterns to cover the first circuit patterns; forming second circuit patterns on an upper surface of the insulation layer to be electrically connected with the first circuit patterns; and separating the carrier substrate from the insulation layer.