Patent ID: 6319839
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method for forming an inter-polysilicon oxide (IPO) layer between two polysilicon layers (POLY1 and POLY2) deposited on a certain silicon substrate in a microelectronics fabrication in such a manner that the deposition of POLY2 layer does not undercut the previously deposited IPO layer, comprising:providing a silicon substrate on which has been formed an oxide-nitride-oxide (ONO) layer, by a succession of thermal depositions consisting of a deposited high temperature silicon oxide (HTO) layer over which has been deposited a silicon nitride layer over which has been deposited a high temperature silicon oxide (HTO) layer;depositing on said substrate a first polysilicon layer (POLY1) or a topographic distribution of such layers;depositing on said polysilicon layers, using a dry etch, a mask of densified tetraethyl orthosilicate (TEOS);subjecting said fabrication of TEOS-masked polysilicon layers to a wet dip for removal of the outer thermal oxide (HTO) layer on the silicon substrate;depositing on said fabrication a non-densified layer of tetraethyl orthosilicate (TEOS);subjecting said fabrication to a partial dry etch followed by a partial HF wet etch;depositing on said fabrication a high temperature thermal oxide (HTO) anddepositing over said high temperature thermal oxide on said fabrication a second polysilicon layer (POLY2).