Patent ID: 9176929
Filing Date: 2015-11-03
Classification: G06F

Abstract:
1. A multi-granularity parallel FFT computation device comprising: a first memory and a second memory configured to store butterfly group data; a third memory configured to store twiddle factors corresponding to the butterfly group data; a first selector; a butterfly computation device has input terminals connected to output terminals of the third memory and the first selector, and is configured to perform computation of a butterfly group based on the butterfly group data outputted from the first selector and the corresponding twiddle factors outputted from the third memory, and write a computation result back to the first or second memory; a state control unit configured to generate read/write(R/W) addresses and R/W control signals for the first, second and third memories based on current computation node and stage; a data reversing network configured to reversely arrange data within a butterfly group; the first selector configured to receive initial input data and bit-reversed data from the data reversing network at two input terminals, respectively, and select the bit-reversed data if the current computation node is computation node 0, otherwise select the initial data.