Patent ID: 7292653
Filing Date: 2007-11-06
Classification: H04L

Abstract:
1. A carrier lock detector for use with a QPSK or low-level QAM system having a constellation of signal points identified by a plurality of I bits and Q bits respectively representing in-phase and quadrature components in a phasor diagram, the phasor diagram including a plurality of first areas centered on ideal signal points representing nominal states and a plurality of second areas adjacent to the first areas, the detector comprising: a first counter responsive to a plurality of I bits and Q bits, the first counter producing a first output signal when a detected signal has I and Q components that map a signal point onto one of the first areas; a second counter responsive to a plurality of I bits and Q bits, the second counter producing a second output signal when a detected signal has I and Q components that map a signal point onto one of the second areas; and a logic device for generating a carrier lock detection signal using the first and second output signals; wherein the first areas are defined by (I