Patent ID: 8726491
Filing Date: 2014-05-20
Classification: G01R,G11C,H01L,Y10T

Abstract:
1. A method of forming a STT-RAM device on a substrate wherein said substrate has a via stud formed in a first dielectric layer and an overlying bottom electrode layer that contacts said via stud and has a planar top surface, comprising: (a) forming a dual-spin-filter (DSF) stack of layers on said planar top surface and above said via stud, said DSF stack of layers has a top surface and is comprised of: (b) annealing at a sufficient temperature to form a crystalline MgO layer and crystalline CoFeB layers; (c) patterning said DSF stack of layers and the bottom electrode layer to form a DSF structure and a bottom electrode above said via stud, said DSF structure has a top surface and sidewalls and an elliptical shape or another rounded shape in a plane parallel to the top surface of the bottom electrode; (d) depositing a second dielectric layer on the first dielectric layer and on the DSF structure; (e) planarizing the second dielectric layer such that the second dielectric layer becomes coplanar with the capping layer; and (f) forming a bit line on the second dielectric layer and on the capping layer.