Patent ID: 6040687
Filing Date: 2000-03-21
Classification: H02M,Y02B,Y02P

Abstract:
A multiplier circuit for a first signal and a second signal according to a multiplying factor proportional to an amplitude of the second signal, said multipler circuit comprising:a first degenerated differential stage;a second nondegenerated differential stage;an output stage comprising a first current mirror and a resistive load connected thereto;said first degenerated differential stage performing a linear to logarithmic conversion of said first signal for providing an input differential voltage for said second nondegenerated differential stage;said second nondegenerated differential stage performing a logarithmic to linear conversion of said input differential voltage for providing an input current to said first current mirror; andmeans for generating a current proportional to said second signal and forcing said current through said second nondegenerated differential stage, said means for generating a current comprising a second current mirror including a first diode-configured input transistor and a second output transistor, and respective degeneration resistors connecting the first diode-configured input transistor and the second output transistor to a supply node, an emitter area ratio between said first diode-configured input transistor and second output transistor being different from an emitter area ratio of respective degeneration resistors.