Patent ID: 6639283
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A semiconductor device with substrate-triggered electrostatic discharge (ESD) protection, comprising:a guard ring formed in a substrate for surrounding a region; a first metal-oxide-semiconductor (MOS) transistor array formed in said region and having at least one first finger-type gate extending in a first direction; a second MOS transistor array formed in said region and having at least one second finger-type gate extending in said first direction; and a substrate-triggered portion formed in said region and between said first MOS transistor array and said second MOS transistor array, and arranged to extend in a second direction perpendicular to said first direction, for passing a trigger current through said substrate simultaneously to both of said first and second MOS transistor arrays when an ESD event occurs, so as to bias a base of at least one parasitic bipolar junction transistor (BJT) in said first MOS transistor array and a base of at least one parasitic BJT in said second MOS transistor array.