Patent ID: 6329848
Filing Date: 2001-12-11
Classification: G11C

Abstract:
A sampling circuit for sampling a varying input signal comprising:a capacitor having first and second capacitor leads;a MOS transistor having a body with a source, a drain and a gate;the first capacitor lead being coupled to a fixed circuit voltage during sampling of the input signal;the drain of the MOS transistor being coupled to the second lead of the capacitor;the source of the MOS transistor being coupled to the input signal;the gate and body of the MOS transistor being coupled to a control circuit, the control circuit also being coupled to a voltage equal to the voltage of the input signal;during the taking of each of multiple samples of the input signal, the control circuit holding the gate and body of the MOS transistor at voltages which are fixed at the same predetermined values relative to the input signal for all of the multiple samples of the input signal.