Patent ID: 6353253
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A semiconductor isolation structure, comprising:a first field region extending from a first active region to a second active region; a first trench immediately adjacent said first active region and a second trench immediately adjacent said second active region to form a first field mesa within said first field region, wherein said first field mesa extends from said first trench to said second trench, wherein an upper surface of said field mesa is lower than an upper surface of said first and second active regions, and wherein corners of said field mesa curve downward from said upper surface of said field mesa to said first and second trenches respectively; and a field dielectric grown upon said first field mesa and within said first and second trenches, wherein said field dielectric is inhibited from growing on said first and second active regions, and wherein an upper surface of said field dielectric is higher than said upper surface of said first and second active regions.