Patent ID: 9117809
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A preparation method of a semiconductor device comprising the steps of: providing an inner lead frame with a plurality of chip mounting units, wherein each chip mounting unit comprises a plurality of inner pads with a plate arranged at a top surface of each inner pad close to one side edge; flipping and attaching a semiconductor chip on the top surface of each inner pad of the chip mounting unit with a plurality of electrodes on the front of the semiconductor chip electrically connected with the plurality of inner pads one-to-one, wherein the semiconductor chip and the plate are separated from each other; forming an inner plastic packaging layer covering the inner lead frame and plurality of semiconductor chips attached on the inner lead frame; grinding from the top surface of the inner plastic packaging layer and the back surface of the semiconductor chips until the top surface of the plate and the back surfaces of the thinned semiconductor chips exposing out of the inner plastic packaging layer; forming a metal layer to cover the top surface of the inner plastic packaging layer; cutting the metal layer into a plurality of top metal segments, each of which is in electrical contact with the top surface of each plate and the back surface of the thinned semiconductor chip respectively; cutting through the inner lead frame, the inner plastic packaging layer and the metal layer between the adjacent semiconductor chips to form a plurality of individual semiconductor devices; providing an outer lead frame comprising a plurality of interconnected units, wherein each interconnected unit comprises a plurality of outer pads; flipping and mounting the semiconductor device on the interconnected unit, wherein the plurality of top metal segments of each semiconductor device are respectively attached on the plurality of outer pads of each interconnected unit one-to-one; forming an outer plastic packaging process, covering the outer lead frame and the plurality of semiconductor devices attached on the outer lead frame, wherein the bottom surface of each outer pad is exposed out of the bottom surface of the outer plastic packaging layer; and cutting through the outer lead frame and the outer plastic packaging layer between the adjacent semiconductor devices to form a plurality of outer plastic packaging bodies, each of which covers an interconnected unit and a semiconductor device.