Patent ID: 6944731
Filing Date: 2005-09-13
Classification: G06F,Y02D

Abstract:
1. A memory system comprising: a memory controller; and a plurality of memory banks operatively coupled to the memory controller, each of the memory banks configured for storing a plurality of data items, wherein a given data item is stored as multiple copies of the data item with the multiple copies being stored in respective ones of a designated minimum number of the memory banks; the memory controller being adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence configured to prevent bank conflict between the access requests; wherein the memory controller comprises: a set of queues configured for storing the access requests, each of the queues being associated with a corresponding one of the plurality of memory banks; and an arbiter operatively coupled to the set of queues for selecting a given one of the access requests therefrom in accordance with the specified bank access sequence.