Patent ID: 7060559
Filing Date: 2006-06-13
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device having a nonvolatile semiconductor memory element with a two-layered gate structure, comprising the steps of: forming a tunnel insulating film and one of a polysilicon layer and an amorphous silicon layer serving as a floating gate electrode on one major surface of a semiconductor substrate; selectively etching the one of the polysilicon layer and the amorphous silicon layer, the tunnel insulating film, and the semiconductor substrate using a mask having a pattern corresponding to an element isolation trench so as to form the element isolation trench; forming a nitride film on a first sidewall surface, perpendicular to a channel width direction of the floating gate electrode, of the one of the polysilicon layer and the amorphous silicon layer exposed into the element isolation trench and burying an element isolation insulating film in the element isolation trench; stacking an electrode insulating film and a conductive film serving as a control gate electrode on the element isolation insulating film and the one of the polysilicon layer and the amorphous silicon layer; selectively etching the conductive film, the electrode insulating film, and the one of the polysilicon layer and the amorphous silicon layer using a mask having a pattern corresponding to the control gate electrode so as to form the control gate electrode and floating gate electrode; and forming a silicon oxide film on a second sidewall surface perpendicular to a channel length direction of the floating gate electrode, in an atmosphere containing radical oxygen, so that a thickness in the channel length direction of the silicon oxide film is greater at a portion on an element isolation insulating film end of the second sidewall surface than at a center portion of the second sidewall surface.