Patent ID: 7447882
Filing Date: 2008-11-04
Classification: G06F

Abstract:
1. Apparatus for processing data under control of program instructions of variable length, said apparatus comprising: a memory configured to store said program instructions; a fetch unit configured to fetch blocks of program instructions to be added to a sequence of program instructions to be decoded from fetch addresses within said memory; and a branch target buffer configured to store a plurality of entries predicting fetch addresses of respective blocks of program instructions as containing a branch instruction to a branch target address, said branch target buffer being responsive to a fetch address of a block of program instructions being fetched from said memory by said fetch unit to detect a hit for an entry within said branch target buffer predicting that a branch instruction is present within said block of program instructions; wherein said fetch addresses are virtual memory addresses and said apparatus is switchable between a plurality of contexts sharing a common virtual address space such that an entry stored in said branch target buffer indicating a fetch address of a block of program instruction including a branch instruction in one context does not predict whether or not said fetch address corresponds to a block of program instructions containing said branch instruction when said apparatus is switched to a different context; and said branch target buffer entries are maintained across a context switch such that a hit within said branch target buffer following said context switch can be a false hit incorrectly predicting a branch instruction within a fetched block of program instructions and incorrectly resulting in a redirection of program flow; said apparatus further comprising: a false hit detecting circuit configured subsequent to said false hit incorrectly redirecting program flow to detect a false hit program instruction incorrectly predicted to be a taken branch instruction by said false hit and to invalidate an entry within said branch target buffer corresponding to said false hit while other entries in said branch target buffer are not invalidated, wherein said block of program instructions includes a plurality of instructions, said program instructions having a highest virtual address portion and when said branch instruction corresponding to said hit prior to said context switch is stored with a highest virtual address portion different to a highest virtual address portion of said false hit program instruction then said redirection of program flow for said false hit results in an incomplete part of said false hit program instruction being added to said sequence, and wherein said false hit detecting circuit is part of said fetch unit and said false hit detecting circuit is configured to remove from said sequence any portion of said false hit program instruction and any subsequent program instructions added to said sequence after said false hit and to re-fetch said block of program instruction from said memory after said entry within said branch target buffer corresponding to said false hit has been invalidated.