Patent ID: 9111785
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A transistor structure with a channel stack, the transistor structure having a semiconductor substrate with a plurality of pre-formed doped wells formed therein, comprising: a first region having: a first doped well providing a foundation for a PMOS transistor element; a first doped screening layer implanted in the semiconductor substrate in contact with the first doped well; a first doped threshold voltage control layer in contact with the first doped screening layer; a second region having: a second doped well providing a foundation for an NMOS transistor element; a second doped screening layer implanted in the semiconductor substrate in contact with the second well; a second doped threshold voltage control layer in contact with the second doped screening layer; and a third layer formed from undoped epitaxial blanket deposition on the semiconductor substrate, separate from and on top of the first and second doped threshold voltage control layers, the third undoped epitaxial layer allowing establishment of an intrinsic channel for each of the PMOS and NMOS transistor elements; a fourth layer formed from undoped epitaxial blanket deposition on the third layer for only one of the PMOS and NMOS transistor elements so that one of the PMOS and NMOS transistor elements has an overall undoped epitaxial intrinsic channel layer thickness greater than the other one of the PMOS and NMOS transistor elements.