Patent ID: 7528036
Filing Date: 2009-05-05
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising steps of: (a) forming first conductor patterns over a nonvolatile memory cell forming region of a semiconductor substrate and a peripheral circuit region of said semiconductor substrate such that said first conductor patterns define an active region of an MISFET in said peripheral circuit region; (b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said nonvolatile memory cell forming region and at said peripheral circuit region such that said grooves serve as an element isolation region in said nonvolatile memory cell forming region and at said peripheral circuit region; (c) filling a first insulating film in said grooves by polishing an insulating film deposited over said grooves; (d) after said step (c), under a condition that said first conductor patterns remain, forming second conductor patterns over said first conductor patterns; (e) forming a conductive film over said second conductor patterns; and (f) patterning said conductive film, said second conductor patterns and said first conductor patterns in said nonvolatile memory cell forming region and in said peripheral circuit region, wherein, in said step (f), said conductive film of said nonvolatile memory cell forming region is patterned to form a control gate electrode of a nonvolatile memory cell, wherein, in said step (f), said second conductor patterns and said first conductor patterns of said nonvolatile memory cell forming region are patterned to form a floating gate electrode of said nonvolatile memory cell, wherein, in said step (f), said second conductor patterns and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode structure of said MISFET of said peripheral circuit region, wherein, in said step (a), said first conductor patterns include a conductive layer and an insulating layer formed over said conductive layer, wherein, in said step (c), said insulating layer functions as a stopper layer in polishing said insulating film, and wherein before said step (d), said insulating layer is removed.