Patent ID: 7881121
Filing Date: 2011-02-01
Classification: G11C

Abstract:
1. A read operation method for a flash memory array having a plurality of memory cells, a plurality of wordlines, a plurality of even numbered bitlines, a plurality of odd numbered bitlines and a plurality of bitline transistors, wherein each even numbered bitline consists of one single bitline, each odd numbered bitline consists of one single bitline, and each even numbered bitline and each odd numbered bitline are alternately arranged, the method comprising: temporarily pre-charging only the plurality of even numbered bitlines to about Vcc/n, n being greater than 1; temporarily pre-charging only the plurality of odd numbered bitlines to one of a ground and a virtual ground level; and after performing the steps of temporarily pre-charging the plurality of even numbered bitlines and odd numbered bitlines, selectively reading a first bit location in one of the plurality of memory cells, wherein the step of selectively reading the first bit location is performed to the plurality of memory cells one-by-one.