Patent ID: 7692215
Filing Date: 2010-04-06
Classification: B82Y,G11C,H01H,H01L

Abstract:
1. A nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer, the nanoscale/microscale interface comprising: a microscale-layer substrate; microelectronic circuits fabricated on the microscale-layer substrate, the microelectronic circuits connected to a number of pins exposed on a surface microscale-layer, the pins partitioned into groups of pins, each group of pins configured identically within a fundamental unit, the fundamental units arranged to tile the surface microscale-layer according to a lattice symmetry; and a number of nanoscale-layer sub-layers, each nanoscale-layer sub-layer containing regularly spaced, parallel pad-interconnected-nanowire-unit (PINU) bundles.