Patent ID: 7342821
Filing Date: 2008-03-11
Classification: G11C,H01L

Abstract:
1. A memory circuit, comprising: a latch including MIS transistors, said latch having a first node and a second node configured to be bi-stable with a potential of the first node inverse to a potential of the second node; a first MIS transistor operable to electrically couple between the first node of said latch and a predetermined node; a second MIS transistor operable to electrically couple between the second node of said latch and said predetermined node; and a control circuit configured to subject, in a first operation mode, one of said first MIS transistor and said second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, and to cause, in a second operation mode, said latch to store data responsive to the lingering change in the transistor characteristics, wherein at least one of the MIS transistors of the latch that is of a same conductivity type as the first and second MIS transistors has a lightly-doped-drain structure that includes first diffusion regions having a first impurity concentration and second diffusion regions having a second impurity concentration smaller than the first impurity concentration, and each of the first MIS transistor and the second MIS transistor has a doped diffusion region closest to a conduction channel such that the doped diffusion region has an impurity concentration different from the second impurity concentration or a conductivity type opposite to that of the second diffusion regions.