Patent ID: 8043898
Filing Date: 2011-10-25
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor package, comprising: a first step of forming a first pattern layer including pad and lead portions on a carrier frame; a second step of forming a base plating layer on a whole part of the carrier frame except for the pad and lead portions with a same height as the first pattern layer; a third step of removing the first pattern layer and forming first plating laminated portions for forming a metal bump on a part from which the first pattern layer has been removed; a fourth step of laminating a second pattern layer on the base plating layer; a fifth step of laminating second plating laminated portions on the first plating laminated portions; a sixth step of removing the second pattern layer; a seventh step of forming an oxide layer on side surfaces of the second plating laminated portions from which the second pattern layer has been removed; an eighth step of laminating a pad frame on the second plating laminated portions that correspond to the pad portion and attaching a die onto the pad frame; and a ninth step of removing by etching or physical method the carrier frame and the base plating layer after boding the second plating laminated portions that correspond to the die and the lead portion with wires and molding an upper part of the carrier frame with a molding compound.