Patent ID: 6838314
Filing Date: 2005-01-04
Classification: H01L,H05K

Abstract:
1. A method of fabricating a substrate with stacked vias and fine circuits, comprising: preparing a core layer having an upper surface with a patterned circuit layer and an opposing lower surface with a metal layer and having at least one conductive through hole for providing electrical connection between the circuit layer and the metal layer; applying at least one first insulating layer over the circuit layer and selectively forming at least one first opening in the first insulating layer for exposing a portion of the circuit layer underneath the first insulating layer, so as to allow a metal layer to be formed within the first opening by an electroplating process; applying at least one second insulating layer over the first insulating layer and selectively forming a plurality of second openings in the second insulating layer, wherein at least one of the second openings allows the metal layer formed within the first opening to be exposed; forming a selective conductive layer on the second insulting layer and within the second openings; forming a metal layer on the conductive layer in the second openings by an electroplating process; and micro-etching the conductive layer on the second insulting layer to obtain the substrate with stacked vias and fine circuits formed thereof.