Patent ID: 6516363
Filing Date: 2003-02-04
Classification: G11C

Abstract:
A selectable dual data rate/single data rate system for transferring data to an output, comprising:a data unit; an output register coupled to the data unit; a holding register coupled to the data unit and the output register; a clock input connected to the output register and the holding register and operable to receive a clock; a selection mechanism connected to the output register and the holding register and operable for selecting single data rate operation or double data rate operation; an output buffer connected to the output register and the holding register; wherein in double data rate operation, the output buffer receives a first piece of data from the output register on the rising edge of the clock and the output buffer receives a second piece of data from the holding register on the falling edge of the clock; and wherein in single data rate operation, the output buffer receives the first piece of data from the output register on the rising edge of the clock and the output buffer receives the first piece data from the holding register on the falling edge of the clock.