Patent ID: 6954847
Filing Date: 2005-10-11
Classification: G06F

Abstract:
1. A method of translating a stream of complex instruction set computer (CISC) instructions for processing on a host processor, comprising: translating, in a translator circuit, the stream of CISC instructions into reduced instruction set computer system (RISC) instructions, wherein each CISC instruction is translated into less than a predetermined number of RISC instructions; storing in at least two intermediate buckets, at least two groups of said RISC instructions, wherein said at least two intermediate buckets can store up to said predetermined number of RISC instructions; and combining into a final bucket, a subset of said at least two groups of said RISC instructions so as to allow issuing of said subset of said at least two groups of said RISC instructions from said final bucket by the host processor, wherein said final bucket has a maximum capacity of said predetermined number of RISC instructions.