Patent ID: 8751833
Filing Date: 2014-06-10
Classification: G06F,Y02D

Abstract:
1. An apparatus for processing data comprising: first processing circuitry configured to operate in a first power domain; second processing circuitry configured to operate in a second power domain different from said first power domain; shared processing circuitry configured to operate in a shared power domain such that said first processing circuitry and said shared processing circuitry are configurable to operate together to form a first hybrid processing unit having access to an external memory and said second processing circuitry and said shared processing circuitry are configurable to operate together to form a second hybrid processing unit having access to said external memory, wherein said first hybrid processing unit and said second hybrid processing unit together comprise a uni-processing environment for executing a single instruction stream; execution flow transfer circuitry configured to transfer execution of said single instruction stream between said first hybrid processing unit and said second hybrid processing unit at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point; transmission circuitry configured to provide a transmission pathway from said source hybrid processing unit to said destination hybrid processing unit for said at least one bit of processing-state restoration information and wherein said transmission pathway bypasses said external memory, wherein the at least one bit of processing-state restoration information comprises at least one of: branch predictor history information, TLB contents, micro-TLB contents and data prefetcher pattern information; and power control circuitry configured to control said shared processing circuitry to operate at a first level of power consumption when said first hybrid processing unit has control of execution of said single instruction stream and to operate at a second different level of power consumption when said second hybrid processing unit has control of execution of said single instruction stream.