Patent ID: 7626877
Filing Date: 2009-12-01
Classification: G11C

Abstract:
1. A memory device comprising: a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device; a column address circuit operable to receive and decode column address signals applied to the external address terminals; at least one array of memory cells arranged in rows and columns, each of the memory cells having a location determined by the decoded row address signals and the decoded column address signals; a plurality of sense amplifiers coupled to respective columns of memory cells in the at least one array, each of the sense amplifiers comprising a latch circuit coupled to the respective column and configured to latch a data state of a memory cell coupled to the digit line and further configured to generate differential data signals in response to the data state, the differential data signals having first and second voltages; a first voltage supply circuit coupled to the latch circuit of at least one sense amplifier and configured to provide a positive voltage as the first voltage; a second voltage supply circuit coupled to the latch circuit of at least one sense amplifier and configured to provide a negative voltage as the second voltage; a data path circuit operable to couple data signals corresponding to the data states between the sense amplifiers and external data terminals of the memory device; and a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.