Patent ID: 8954681
Filing Date: 2015-02-10
Classification: G06F

Abstract:
1. A command processing pipeline configured to be coupled to a shared cache, the command processing pipeline comprising: a first command processing stage configured to perform a comparison, in a first clock cycle, of an address associated with a first cache command to addresses stored in the cache; a second command processing stage configured to, in a second clock cycle, (i) receive the first cache command from the first command processing stage, and (ii) based on a result of the comparison, process the first cache command by one or more of (A) providing a read access to one or both of a data memory and an error correcting code memory included in the cache, (B) providing a write access to one or both of the data memory and the error correcting code memory included in the cache, and (C) generating an error correcting code associated with data to be written to the data memory; and a third command processing stage configured to, in a third clock cycle, (i) receive the first cache command from the second command processing stage, and (ii) process the first cache command by writing data associated with the first cache command to one of a valid memory and a dirty memory included in the cache, the valid memory and the dirty memory being different from the data memory.