Patent ID: 6864560
Filing Date: 2005-03-08
Classification: H01L

Abstract:
1. A bipolar vertical transistor formed in a silicon semiconductor substrate comprising: said silicon semiconductor substrate having an upper surface, shallow trench isolation (STI) regions composed of a dielectric material formed in said upper surface of said silicon semiconductor substrate, said STI regions having inner sidewalls and top surfaces, a doped collector region formed completely within said substrate between a pair of said STI regions below said top surface of said silicon semiconductor substrate, so that said doped collector region has a top surface which comprises said upper surface of said silicon semiconductor substrate, an intrinsic base pedestal comprising a counterdoped intrinsic base region formed directly on said upper surface of said silicon semiconductor substrate on top of said collector region between said inner ends of said pair of said STI regions with a margin between said intrinsic base region and said pair of said STI regions, said intrinsic base pedestal having edges, a lateral isolation extension recess formed extending to a depth at least between said lateral edges of said intrinsic base pedestal and said inner sidewalls of said pair of STI regions, or extending between said inner sidewalls of said pair of said STI regions and said lateral edges of said intrinsic base pedestal as well as extending between said inner sidewalls of said pair of said STI regions and lateral edges of a top portion of said collector region, said lateral isolation extension recess separating at least said intrinsic base pedestal from said pair of STI regions, a doped emitter region formed above said intrinsic base region spaced away from said edges of said intrinsic base-collector pedestal, and a shallow isolation extension region composed of a dielectric material juxtaposed with said edges of said intrinsic base pedestal formed in said lateral isolation extension recess in said margin between at least said inner ends of said pair of said STI regions and said edges of said intrinsic base pedestal, or said shallow isolation extension region extending between both said inner sidewalls of said pair of STI regions and said lateral edges of said intrinsic base pedestal and said shallow isolation extension region extending between said inner sidewalls of said pair of said STI regions and lateral edges of a top portion of said collector region, whereby said shallow isolation extension region reduces the base-to-collector parasitic capacitance of said bipolar transistor.