Patent ID: 6836816
Filing Date: 2004-12-28
Classification: G06F

Abstract:
A system comprising:a processor; and a memory device coupled to the processor and contained within a single integrated circuit, the memory device including: a main memory, an address latch logic to receive addresses of requested data; a cache memory coupled to the processor and to the main memory to store recently accessed data and addresses associated with the recently accessed data, the cache memory including an address cache memory coupled to the address latch logic and a wait control logic to store the addresses of the recently accessed data and to store the address of the requested data after the requested data has been fetched, and a data cache memory coupled to the address cache memory and the main memory to store the recently accessed data, the data cache memory receiving data from the main memory if the data requested is not in the data cache memory; the wait control logic coupled to the processor, the main memory, and the cache memory to signal the processor whether the data currently requested is ready to be read; a multiplexer coupled to the data cache memory to select the requested data from the data cache memory; and a word count control logic coupled to the address latch logic and the multiplexer to control the multiplexer to selectively output the requested data using the multiplexer.