Patent ID: 8924689
Filing Date: 2014-12-30
Classification: G06F

Abstract:
1. A data processor including a first mode corresponding to a fixed-length instruction, and a second mode corresponding to a variable-length instruction set by applying a prefix to the fixed-length instruction, the data processor comprising: an instruction fetch unit configured to fetch four codes of a plurality of instructions in parallel and having a plurality or decoders comprising first, second, third and fourth predecoders each of which performs predecoding for determining whether a corresponding one of said fetched codes is of a fixed-length instruction in the first mode, a fixed-length instruction corresponding to part of a variable-length instruction in the second mode or a prefix corresponding to part of the variable-length instruction in the second mode; a first pipeline comprising a first prefix code decode unit and a first fixed-length instruction decode unit, and a second pipeline comprising a second prefix code decode unit and a second fixed-length instruction decode unit; a first selector for selecting one of outputs of the first, second, third and fourth predecoders and outputting the same to the first fixed-length instruction decode unit; a second selector for selecting one of the outputs of the first, second, third and fourth predecoders and outputting the same to the second fixed-length instruction decode unit; a third selector for selecting one of the outputs of the first, second, third and fourth predecoders and outputting the same to the first prefix code decode unit; and a fourth selector for selecting one of the outputs of the first, second, third and fourth predecoders and outputting the same to the second prefix code decode unit, wherein in the first mode, a first fixed-length instruction is inputted to the first predecoder, a second fixed-length instruction is inputted to the second predecoder, a third fixed-length instruction is inputted to the third predecoder, and a fourth fixed-length instruction is inputted to the fourth predecoder, wherein the first predecoder predecodes the first fixed-length instruction, the second predecoder predecodes the second fixed-length instruction, the third predecoder predecodes the third fixed-length instruction, and the fourth predecoder predecodes the fourth fixed-length instruction, wherein the first selector selects one of the outputs of the first through fourth predecoders and outputs the same to the first fixed-length instruction decode unit based on results of determination by the plurality of predecoders, wherein the second selector selects one of the outputs of the first through fourth predecoders and outputs the same to the second fixed-length instruction decode unit based on results of determination by the plurality of predecoders, wherein in the second mode, a first prefix corresponding to part of a first variable-length instruction, a third fixed-length instruction corresponding to part of the first variable-length instruction, a second prefix corresponding to part of a second variable-length instruction, or a fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the first predecoder, wherein the first prefix corresponding to part of the first variable-length instruction, the third fixed-length instruction corresponding to part of the first variable-length instruction, the second prefix corresponding to part of a second variable-length instruction, or the fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the second predecoder, wherein the first prefix corresponding to part of the first variable-length instruction, the third fixed-length instruction corresponding to part of the first variable-length instruction, the second prefix corresponding to part of a second variable-length instruction, or the fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the third predecoder, wherein the first prefix corresponding to part of the first variable-length instruction, the third fixed-length instruction corresponding to part of the first variable-length instruction, second prefix corresponding to part of a second variable-length instruction, or the fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the fourth predecoder, wherein the first predecoder predecodes the first prefix, the third fixed-length instruction, the second prefix or the fourth fixed-length instruction, wherein the second predecoder predecodes the first prefix, the third fixed-length instruction, the second prefix or the fourth fixed-length instruction, wherein the third predecoder predecodes the first prefix, the third fixed-length instruction, the second prefix or the fourth fixed-length instruction, wherein the fourth predecoder predecodes the first prefix or the third fixed-length instruction or the second prefix or the fourth fixed-length instruction, wherein the third selector or the fourth selector selects one of the output of the first predecoder, the output of the second predecoder, the output of the third predecoder, or the output of the fourth predecoder, and outputs the same to the first prefix code decode unit or the second prefix code decode unit, based on results of determination by the plurality of predecoders, wherein the first selector or the second selector selects one of the outputs of the first through fourth predecoders and outputs the same to the first fixed-length instruction decode unit or the second fixed-length instruction decode unit, based on results of determination by the plurality of predecoders, wherein in the first prefix corresponding, to part of the first variable-length instruction is supplied to the first prefix code decode unit, followed by supply of the third fixed-length instruction to the first fixed-length instruction decode unit, and the second prefix corresponding to part of the second variable-length instruction is supplied to the second prefix code decode unit, followed by supply of the fourth fixed-length instruction to the second fixed-length instruction decode unit, based on results of determination by the plurality of predecoders, respectively, and wherein the fixed-length instruction in the first mode composes a code of a first length, the variable-length instruction in the second mode composes a code of the fixed-length length instruction of the first length and a code of the prefix of the first length.