Patent ID: 7039149
Filing Date: 2006-05-02
Classification: H03L,H04L

Abstract:
1. A data clock regenerating apparatus comprising: a first phase-locked loop which generates a first clock signal that is synchronous with a frequency of an input data signal and that is also in phase synchronism with a change point of the data signal; a first discriminating unit which regenerates the input data signal by discriminating this input data signal with the first clock signal; a second phase-locked loop which generates a second clock signal of which frequency and phase are synchronous with the first clock signal; and a second discriminating unit that regenerates an output data signal of the first discriminating unit by discriminating this output data signal with the second clock signal, wherein an upper limit value of a jitter transmission frequency in the first phase-locked loop in which a jitter signal superimposed on the input data signal is transmitted to the first clock signal without being suppressed, is not less than an upper limit value of a jitter transmission frequency that is required in the apparatus, and an upper limit value of a jitter transmission frequency from the first phase-locked loop to the second phase-locked loop in which a jitter signal superimposed on the input data signal is transmitted to the second clock signal without being suppressed, is not more than an upper limit value of a jitter transmission frequency that is required in the apparatus.