Patent ID: 6747471
Filing Date: 2004-06-08
Classification: G01R

Abstract:
A method for estimating burn-in time for integrated circuits comprising the steps of:providing a substrate; forming a plurality of testing structures on said substrate, each substrate being formed by the steps of: forming a plurality of evaluation device structures on said substrate, each device structure created to permit evaluation of failure mechanisms of said integrated circuit, forming a first forcing input pad to provide a first forcing stimulus to at least one of said evaluation device structures to provide a first stimulus to stress said evaluation device structure, forming a second forcing input pad to provide a second forcing stimulus to at least one of said evaluation device structures to further stress said evaluation device structure, forming a first sensing output pad connected to sense a first response from at least one of said evaluation device structures, forming a second sensing output pad connected to sense a second response from at least one of said evaluation device structures, and forming a selection circuit connected to selectively communicate the second stimulus to at least one selected evaluation device structure and the second response from the selected evaluation devices structure; activating said first and second stimuli; stressing said substrate; examining each selected evaluation device structure for failure; determining a hazard rate for each failure mechanism of said integrated circuit; and determining a burn-in time for said integrated circuit.