Patent ID: 8587596
Filing Date: 2013-11-19
Classification: G06T

Abstract:
1. A circuit arrangement, comprising: hardware logic configured to host a multithreaded rendering software pipeline using a plurality of parallel threads of execution, the multithreaded rendering software pipeline including a rasterization backend that generates a raster-based image, the plurality of parallel threads of execution including a plurality of raster threads that execute at least a portion of the rasterization backend, wherein each raster thread is allocated at least one region of an image space for the raster-based image; and control logic configured to dynamically reallocate regions allocated to the plurality of raster threads based upon performance data collected from the plurality of raster threads, wherein the control logic is further configured to control an interval at which the dynamic reallocation occurs based on the performance data collected from the plurality of raster threads; wherein each raster thread is configured to collect performance data associated with a workload of such raster thread and return the performance data to the control logic, wherein each raster thread is configured to return at least a portion of the performance data according to a data collection interval, and wherein the control logic is configured to adjust the data collection interval by streaming a command to at least one raster thread via the multithreaded rendering software pipeline.