Patent ID: 7738314
Filing Date: 2010-06-15
Classification: G11C

Abstract:
1. A decoder for decoding an address having a plurality of bits ranging from a first address bit a 1 to a last address bit a N , each address bit being either true or false, comprising: a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a a (n+1)th switch coupling the dynamic OR node to ground, the (n+1)th switch being controlled such that it turns on if the dynamic NOR node is charged, whereby the pre-charged dynamic OR node discharges if the dynamic NOR node remains charged; an odd plurality of inverters coupled in series with the dynamic OR node; and a word line driven by the odd plurality of inverters.