Patent ID: 6020562
Filing Date: 2000-02-01
Classification: H05K,Y02P

Abstract:
A reduced-capacitance component mounting pad suitable for use on 0402-size high frequency printed circuit boards to reduce parasitic capacitance, comprising:a dielectric layer,a metallic ground plane layer on one side of said dielectric layer, anda component mounting pad having an area of about 20 mils.times.20 mils (0.51 mm.times.0.51 mm) on the opposite side of said dielectric layer from said ground plane layer, the area of said mounting pad being substantially less than that of a corresponding conventional mounting pad for an 0402 chip component size such that the parasitic capacitance between said mounting pad and said ground plane layer is less than would be present between said corresponding conventional 0402 pad and said ground plane layer and enabling a higher transmission line impedance to be achieved for a conductive trace attached to said pad than would be possible with said corresponding conventional 0402 mounting pad attached to said trace, said lesser area sufficient to support a mechanically sound solder joint for a component lead soldered to said pad.