Patent ID: 6111267
Filing Date: 2000-08-29
Classification: H01L

Abstract:
An integrated CMOS circuit, comprising a semiconductor substrate including at least a first silicon layer having a thickness of between 30 nm and 70 nm, a stressed Si.sub.1-x Ge.sub.x layer having a thickness of between 5 nm and 10 nm and a germanium content of between 50 atomic percent and 25 atomic percent and a second silicon layer having a thickness of between 5 nm and 12 nm, wherein the stressed Si.sub.1-x Ge.sub.x layer has a lattice constant which is substantially equal to respective lattice constants of both the first silicon layer and the second silicon layer, wherein a p-channel MOS transistor and an n-channel MOS transistor are formed in the semiconductor substrate wherein a conductive channel is formed within the Si.sub.1-x Ge.sub.x layer in the p-channel MOS transistor, and wherein a conductive channel is formed in the second silicon layer in the n-channel MOS transistor.