Patent ID: 6876230
Filing Date: 2005-04-05
Classification: H03K

Abstract:
1. A cascaded chain of synchronous clocked full-rail differential logic circuits with single-rail logic and shut-off comprising: a first supply voltage; a second supply voltage; a first clocked full-rail differential logic circuit with shut-off, said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off comprising: a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; said fourth transistor first flow electrode being coupled to said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node, said fourth transistor second flow electrode being coupled to said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal, said fourth transistor control electrode being coupled to a first clock signal; a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; said fifth transistor first flow electrode being coupled to said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node, said fifth transistor second flow electrode being coupled to said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal, said fifth transistor control electrode being coupled to said first clock signal; a first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off shut-off device coupled between said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal and said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal; a base logic portion, said base logic portion comprising a base logic portion first input terminal, a base logic portion second input terminal, a base logic portion out terminal, and a base logic portion fourth terminal, said base logic portion out terminal being coupled to said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor, said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor comprising a first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor first flow electrode, a first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor second flow electrode and a first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor control electrode, said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor first flow electrode being coupled to said third transistor first flow electrode and said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal, said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor second flow electrode being coupled to a first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off second node, said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor control electrode being coupled to said third transistor second flow electrode and said first synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a second clocked full-rail differential logic circuit with shut-off, said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off comprising: a second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; said fourth transistor first flow electrode being coupled to said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node, said fourth transistor second flow electrode being coupled to said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal, said fourth transistor control electrode being coupled to a second clock signal; a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; said fifth transistor first flow electrode being coupled to said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off first node, said fifth transistor second flow electrode being coupled to said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal, said fifth transistor control electrode being coupled to said second clock signal; a second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off shut-off device coupled between said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal and said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal; a base logic portion, said base logic portion comprising a base logic portion first input terminal, a base logic portion second input terminal, a base logic portion out terminal, and a base logic portion fourth terminal, said base logic portion out terminal being coupled to said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal; a second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor, said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor comprising a second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor first flow electrode, a second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor second flow electrode and a second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor control electrode, said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor first flow electrode being coupled to said third transistor first flow electrode and said second clocked full-rail differential logic circuit with single-rail logic and shut-off outBar terminal, said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor second flow electrode being coupled to a second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off second node, said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off complementary output transistor control electrode being coupled to said third transistor second flow electrode and said second synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off out terminal, wherein; said second clock signal is delayed with respect to said first clock signal by a predetermined delay time.