Patent ID: 6741660
Filing Date: 2004-05-25
Classification: G06F,H03K,H04B

Abstract:
A method for modulation of a basic clock for digital circuits, in which intervals between adjacent switching edges are varied, with the basic clock being split into equidistant sections, and the intervals between adjacent edges being varied as a function of cyclically recurring random numbers, further comprising the step of calculating the position of a switching edge (ai+1) following a switching edge (a1) as follows: ai+1=(a1+p-{N-12-Zi+1})&it;â€ƒ&it;mod&it;â€ƒ&it;pwherep is the number of equidistant sections per half-cycle, N is the number of possible switching edges, with N being an odd number, and Z is the random number; and wherein the basic clock is passed via a changing number of delay units, and the intervals between adjacent switching edges are varied in this way.