Patent ID: 8993452
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A method of fabricating a gate structure, comprising: forming a gate dielectric layer on a semiconductor substrate, wherein the gate dielectric includes a first high-k dielectric; forming a metal layer on the gate dielectric layer; forming a hard mask layer on the metal layer, wherein the hard mask layer includes a second high-k dielectric; patterning the hard mask layer and the metal layer, wherein the patterning defines a first portion and a second portion of the gate dielectric layer, wherein the first portion underlies the hard mask and the second portion is in an open area of the substrate; removing the hard mask layer and the second portion of the gate dielectric layer; and after removing the hard mask layer and the second portion of the gate dielectric layer, forming another metal layer directly on the patterned metal layer and the open area.