Patent ID: 7570266
Filing Date: 2009-08-04
Classification: G06T

Abstract:
1. A graphics processor configured to produce data for multiple output buffers, each output buffer associated with a unique output buffer identifier, comprising: a fragment processing pipeline configured to process graphics data to produce processed graphics data for the multiple output buffers and determine at least two output buffer identifiers associated with the processed graphics data, wherein each output buffer identifier determines an address associated with the processed fragment data, the address corresponding to a specific location within a different one of the multiple output buffers, wherein the fragment processing pipeline includes: wherein the graphics data includes fragment data including at least two fragments within a single surface, wherein a first fragment is stored in a first output buffer, and a second fragment is stored in a second output buffer, wherein the first output buffer is associated with a depth map that includes sorted depth values for fragments at each pixel location associated with the first output buffer, visible fragments within the first output buffer being selected for shading based on the depth values stored in the depth map, and wherein the second output buffer is associated with a second depth map that includes sorted depth values for fragments at each pixel location associated with the second output buffer, visible fragments within the second output buffer being selected for shading based on the depth values stored in the second depth map.