Patent ID: 8125247
Filing Date: 2012-02-28
Classification: B82Y,G11C,H03K

Abstract:
1. A complementary spin transistor logic circuit, comprising: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer that is disposed between the first source and the first drain and transfers electrons to the first drain by injecting spin-polarized electrons from the first source, and a first gate electrode that is disposed on the upper portion of the first channel layer and controls the spin of electrons passing through the first channel layer, the spin of electrons making precession by a spin-orbit coupling induced magnetic field according to voltage applied to the first gate electrode when passing through the first channel layer; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer that is disposed between the second source and the second drain on a second substrate and transfers electrons to the second drain by injecting spin-polarized electrons from the second source, and a second gate electrode that is disposed on the upper portion of the second channel layer and controls the spin of electrons passing through the second channel layer, the spin of electrons making precession by the spin-orbit coupling induced magnetic field according to voltage applied to the second gate electrode when passing through the second channel layer, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.