Patent ID: 8060355
Filing Date: 2011-11-15
Classification: G06F

Abstract:
1. A method of providing simulation results, the method comprising: parsing a netlist of a circuit; detecting any power net and rail in the netlist; partitioning the circuit into net-partitioned blocks connected at channels by cutting at any power net; performing a topological analysis of the net-partitioned blocks to identify cuttable devices, un-cuttable devices, and synchronization requirements; re-partitioning the circuit into rail-partitioned blocks connected at channels by cutting at any rail; applying a sparse solver to a sparse matrix representing the rail-partitioned blocks to identify potential partitions, the sparse matrix eliminating fill-ins as determined by performing topological analysis; applying a cost function to the potential partitions as well as the identified cuttable and un-cuttable devices to determine final cut points in the circuit and dynamic inputs to final blocks, wherein the cost function includes at least one of available memory to perform simulation, a type of simulator to perform the simulation, specific data structures in the circuit, and specific algorithms to be used in the simulation; performing simulation on the final blocks using the dynamic inputs; and outputting simulation results.