Patent ID: 6429057
Filing Date: 2002-08-06
Classification: G02F,H01L,Y10S

Abstract:
A method for manufacturing a thin film transistor array panel for a liquid crystal display, comprising the steps of:forming a gate wire including a plurality of gate lines and a plurality of gate electrodes connected to the gate lines, and a common wire including a plurality of common electrodes on an insulating substrate; forming a gate insulating layer pattern covering the gate wire and the common wire; forming a semiconductor pattern on the gate insulating layer; forming an ohmic contact layer pattern on the semiconductor pattern; forming a data wire on the ohmic contact layer pattern, the data wire including a plurality of data lines, a plurality of source electrodes connected to the data lines, and a plurality of drain electrodes separated from the source electrodes; forming a passivation layer pattern covering the data wire except for a part of the drain electrode; and forming a plurality of pixel electrodes that are connected to the drain electrodes and cooperate with the common electrodes to generate electric fields, wherein the source electrodes and the drain electrodes are separated by a photolithography process using a photoresist layer pattern having portions of different thickness, and wherein the portions include a first portion located between the source electrodes and the drain electrodes, a second portion thicker than the first portion and a third portion thinner than the first portion.