Patent ID: 7032162
Filing Date: 2006-04-18
Classification: H03M

Abstract:
1. A polynomial expander for generating coefficients of an expanded polynomial of a variable, X, from a predetermined number, n, of the roots of the polynomial, the polynomial expander comprising: (n+1) coefficient storage registers coupled in series from a first place at a right most place to a (n+1) place at a left most place, wherein a respective coefficient storage register at a j-th place generates a respective coefficient for a X a temporary register coupled in series with the coefficient storage register at the first place for storing as a temporary coefficient the respective coefficient that was output by said coefficient storage register at said first place in a prior clock cycle; a root register for storing a root of said polynomial; a multiplier having as inputs, an output of said root register and an output of said coefficient storage register at the first place; an adder having as inputs, an output of said multiplier and an output of said temporary register; and a respective multiplexer coupled to each of said coefficient storage registers, said temporary register, and said root register, and a controller for determining a respective input to each of said coefficient storage registers, said temporary register, and said root register through said respective multiplexer; wherein said controller controls said respective multiplexers coupled to said coefficient storage registers for initializing the coefficient storage register at the first place to output a unitary value and all other coefficient storage registers not at the first place to output a null value, and wherein said controller controls said respective multiplexer coupled to said temporary register for initializing said temporary register to output a null value as said temporary coefficient; and wherein each of said predetermined number, n, of the roots of the polynomial are provided serially from a first order to an n and wherein for an i and wherein outputs of the coefficient storage registers at and to the right of an (i+1) place shift toward the right with the output of the coefficient storage register at the first place being shifted into said temporary register, and wherein said i and wherein generation, of said i and wherein said performing, said (i+1) times of generating said it order multiplier output and said in order adder output and shifting of respective outputs of the coefficient storage registers at and to the right of said (i+1) place for said i