Patent ID: 7592210
Filing Date: 2009-09-22
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device comprising: (a) forming a device isolation structure in a semiconductor substrate having a pad insulating film; (b) selectively etching the pad insulating film by a recess gate mask to expose the semiconductor substrate of a recess region; (c) forming a first spacer at a sidewall of the recess region; (d) etching a predetermined thickness of the semiconductor substrate exposed at the lower part of the recess region using the first spacer as an etching mask to form a first recess; (e) forming a second spacer at a sidewall of the first spacer and the first recess; (f) etching the semiconductor substrate exposed at the lower part of the first recess by the second spacer as an etching mask to form a second recess, wherein a recess channel region including vertical silicon-on-insulator (SOI) channel structures is formed in the second recess, wherein the vertical SOT channel structures are fanned at sidewalls of both device isolation structures in the longitudinal direction of a gate region; (g) removing the first spacer, the second spacer, and the pad insulating film to expose the semiconductor substrate; (h) forming a gate insulating film over the exposed semiconductor substrate; and (i) forming a gate structure over the gate insulating film of the gate region, wherein the gate structure includes a stacked structure of a gate electrode filling the recess channel region and a gate hard mask layer pattern.