Patent ID: 7987062
Filing Date: 2011-07-26
Classification: G01R

Abstract:
1. A delay circuit that delays an input signal to output a delayed signal, comprising: a first delay element that delays the input signal by a first delay amount according to a delay setting value that is set; a second delay element that delays the input signal by a second delay amount according to a delay setting value that is set; and an initializing section that measures the first delay amount with respect to each of the delay setting values and initializes the first delay element, the initializing section comprising: a first loop path that inputs an output signal of the first delay element into the first delay element; a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures the first delay amount on the basis of signals transmitted through the first loop path; a second measuring section that measures the second delay amount in synchronization with the first measuring section; and a delay amount computing section that corrects each of the first delay amounts measured by the first measuring section by means of the second delay amount measured by the second measuring section in synchronization with this first delay amount and computes the first delay amount for each of the delay setting values of the first delay element, wherein the initializing section further has a second loop path that inputs an output signal of the second delay element into the second delay element, and the second measuring section measures the second delay amount in synchronization with the first measuring section on the basis of a signal transmitted through the second loop path without changing the delay setting value of the second delay element.