Patent ID: 6546476
Filing Date: 2003-04-08
Classification: G06F,G11C

Abstract:
A method of tansferring data on a data bus to and from multiple memory devices, comprising the steps of:issuing a read instruction to a first memory device during a first time slot; issuing a write instruction to a second memory device during a second time slot immediately following said first time slot; transferring read data on the data bus from the first memory device in response to the read instruction during a third time slot; delaying a transfer of write data on the data bus to the second memory device in response to the write instruction by a number of time slots; transferring said write data on the data bus during a fourth time slot, said fourth time slot immediately following said third time slot; and repeating said previous steps, wherein a next read instruction issuing step occurs during a fifth time slot, said fifth time slot immediately following said second time slot, wherein a next read data tansferring step occurs during a sixth time slot, said sixth time slot immediately following said fourth time slot.