Patent ID: 6030879
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A method of reducing defects during the manufacture of fin or cylinder capacitors on a wafer, said wafer having a semiconducting substrate and a plurality of transistors formed on said substrate, wherein a conducting layer, a first dielectric layer, and a second dielectric layer are formed on said wafer, said method comprising:forming a photoresist layer on an edge of said wafer prior to removing the second dielectric layer, wherein said conducting layer is covered by said second dielectric layer, and said first dielectric layer is under said conducting layer and said second dielectric layer, a first portion of said second dielectric layer at the edge of said wafer being covered by said photoresist layer, said conducting layer being electrically separated from and adherent to said substrate by said first dielectric layer at the edge of said wafer;removing a second portion of said second dielectric layer at the center of said wafer to expose a portion of said conducting layer originally covered by the second portion of said second dielectric layer at said center of said wafer, said exposed portion of said conducting layer forming bottom storage electrodes of said capacitors; andremoving said photoresist layer on the edge of said wafer, said first dielectric layer and said conducting layer being adherent to said wafer after said second portion of said second dielectric layer being removed.