Patent ID: 6303435
Filing Date: 2001-10-16
Classification: H01L,Y10S

Abstract:
A method of fabricating a wide-based, box-structured capacitor containing hemi-spherical grains, wherein a substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening that exposes the source/drain, the method comprising:forming a doped polysilicon layer on the substrate;forming a doped amorphous silicon layer on the doped polysilicon layer;performing a first etching step, wherein a first flow speed of chlorine and a second flow speed of hydrogen bromide are used to etch the doped amorphous silicon layer and the doped polysilicon layer until the first dielectric layer is exposed and a lower electrode is formed thereon in the node contact opening and on the surrounding first dielectric layer;performing a second etching step on the lower electrode, wherein a third flow speed of chlorine and a fourth flow speed of hydrogen bromide are used, and the first flow speed is higher than the third flow speed and the second flow speed is lower than the fourth flow speed;forming hemi-spherical silicon grains on a surface of the doped amorphous silicon layer in the lower electrode;forming a second dielectric layer on a surface of the lower electrode; andforming an upper electrode on the second dielectric layer.