Patent ID: 6198678
Filing Date: 2001-03-06
Classification: G11C

Abstract:
A semiconductor memory, comprising:a) at least one column of memory cells;b) at least one bitline connected to said at least one column of memory cells;c) an addressing circuit for selecting said at least one bitline for a read operation of said at least one column of memory cells;d) a controlled discharge path for ensuring that said selected at least one bitline is substantially discharged at a start of said read operation;e) a controlled charging path for charging said selected at least one bitline from said start of said read operation;f) a sense amplifier for sensing a voltage on said selected at least one bitline during charging of said selected at least one bitline by said controlled charging path;g) said at least one bitline comprising a plurality of bitlines; andh) a multiplexer responsive to said addressing circuit for selecting one at a time said plurality of bitlines, said multiplexer being operative for grounding each unselected one of said plurality of bitlines.