Patent ID: 6271578
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A semiconductor wafer comprising a substrate for fabricating integrated circuits, comprising:a channel disposed between adjacent ones of said integrated circuits, said adjacent ones of said integrated circuits being separated by dicing along said channel;a dielectric layer disposed over said channel, said dielectric layer being formed of a dielectric material and including a region of dielectric thickness discontinuity along a periphery of said channel, said region of dielectric thickness discontinuity being a thickened dielectric region, said thickened dielectric region being thickened due to a presence of said dielectric material in a surface step in a bottom surface bottom surface of the channel, said dielectric thickness discontinuity being configured to reduce propagation of cracks along said dielectric layer, wherein said dielectric layer is protected by a passivation layer formed of a passivation material different from said dielectric material and wherein said surface step is formed in the bottom surface of said wafer as part of the process for forming isolation regions separating active areas within the integrated circuits.