Patent ID: 6300685
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A semiconductor package comprising:a first package substrate having a concave portion;a semiconductor chip, fixed within the concave portion, having a major surface and first pads formed on the major surface;a second package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces and having a step configuration, (c) a first pad forming region provided on the step configuration, (d) second pads formed on the first pad forming region, (e) external electrodes formed on the first major surface of said second package substrate, wherein the second major surface of said second package substrate is fixed to the major surface of said semiconductor chip, and wherein one of the first external electrodes is electrically connected to one of the second pads;a third package substrate stacked on said first package substrate, said third package substrate having (a) an opening defined by an inner surface thereof, the inner surface having a step configuration (b) opposite first and second major surfaces, (c) third pads formed on a second pad forming region provided on the step configuration, and (d) second external electrodes formed on the first major surface of said third package substrate, wherein the second external electrodes are electrically connected to the third pads;bonding wires electrically connecting one of the third pads; anda sealing material covering the bonding wires, the first, second and third pads.