Patent ID: 9183910
Filing Date: 2015-11-10
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a cell array comprising a plurality of non-volatile memory cells; a plurality of bit lines connected to the plurality of non-volatile memory cells; first and second column selectors connected to the plurality of bit lines and configured to be respectively controlled by first and second column selecting signals, wherein each of the plurality of bit lines are connected to respective different pairs of one of the first column selectors and one of the second column selectors; a first local input/output line that is electrically connected to the plurality of bit lines via the first column selectors responsive to activation of the first column selecting signals; and a second local input/output line that is electrically connected to the plurality of bit lines via the second column selectors responsive to activation of the second selecting signals, wherein the first and second selectors are alternately selected responsive to external commands.