Patent ID: 6618302
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A memo circuit in single-port memory structure having a predetermined memory access speed and a memory access period, comprising:a. a memory module having (1) memory cells disposed to store data, the memory cells including a designated group of memory cells being assigned to represent a logical portion of the memory structure; (2) local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells; (3) local an global row decoders, the local row decoders being coupled with the memory cells; and b. a predecoding circuit coupled with selected global row decoders, wherein the predecoding circuit is disposed to provide predecoding at a speed substantially faster than t e predetermined memory structure access speed, and allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality thereby.