Patent ID: 6706619
Filing Date: 2004-03-16
Classification: B81B,H01L

Abstract:
A method for making a chip, comprising the steps of:defining a first configuration for a die that corresponds with an area encompassed by a single exposure field of a photolithographic stepper, wherein said defining step comprises providing a plurality of rows of a plurality of mirror assemblies, a plurality of off-chip electrical contacts for each of said plurality of rows, and an electrical trace bus located between at least some adjacent pairs of rows of said plurality of rows and that is electrically interconnected with at least some of said mirror assemblies of at least one said row of the two said rows between which said electrical trace bus is located, wherein said die comprises a first die dimension that is a distance between first and second sides of said die, as well as a second die dimension that is a distance between third and fourth sides of said die, wherein said first die dimension and said second die dimension are orthogonal to each other, wherein said plurality of rows of said plurality of mirror assemblies extend in said first die dimension, and wherein said plurality of rows of said plurality of mirror assemblies are spaced in said second die dimension; forming a plurality of the same said die on a wafer; and dicing said wafer into a chip, wherein said dicing step comprises the steps of: providing a first chip dimension for said chip that is an integer multiple of said first die dimension; and providing a second chip dimension for said chip that is an integer multiple of one of said plurality of rows of said plurality of mirror assemblies without requiring said second chip dimension to be an integer multiple of said second die dimension, wherein said first and second chip dimensions are orthogonal.