Patent ID: 9099354
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a semi-conducting substrate; a first cell, comprising: a second cell, comprising: a buried oxide layer extending between the first, second, third and fourth transistors, and between the first, second, third and fourth ground planes; wherein the gate metals of the first, third and fourth gate stacks exhibit a first work function, the gate metal of the second gate stack exhibits a second work function which is greater than the first work function; the difference between the first and second work functions being between 55 and 85 meV and the first work function, Wf1, satisfying the relation Wfmg−0.04−0.005*Xge<Wf1<Wfmg−0.03−0.005*Xge, with Xge being the percentage of germanium in the channel of the transistors of the pMOS type and Wfmg being the work function corresponding to the middle of a forbidden band of the silicon; further including one of the following: for a 28 nm technological node: for a 14 nm technological node: for a 10 nm technological node: