Patent ID: 7062728
Filing Date: 2006-06-13
Classification: G06F

Abstract:
1. A method of designing a logic circuit, comprising the steps of: an algorithm C description outputting step for outputting an algorithm C description describing an algorithm of computation of the logic circuit or an algorithm of control of the logic circuit in a C language to an algorithm verification system for verifying the algorithm; an algorithm-functional C conversion step for converting the algorithm C description into a functional C description describing control of hardware of the logic circuit in the C language by splitting the algorithm C description into the functional C description as units of processing; a functional C description outputting step for outputting the functional C description to a function verification system for verifying functions of hardware or the logic circuit without considering the clock; a functional-RTL C conversion step for converting the functional C description generated in the algorithm-functional C conversion step into a register transfer (RT) level C description written in the C language by inserting a clock description into the functional C description; and a RTLC-HDL conversion step for converting the RT level C description generated in the functional-RTLC conversion step into a RT level description in HDL, wherein the algorithm-functional C conversion step comprises the step of splitting the algorithm C description into at least a data input state corresponding to data input processing, a computation state corresponding to computation processing, and a result output state corresponding to data output processing.