Patent ID: 8583858
Filing Date: 2013-11-12
Classification: G06F

Abstract:
1. A nonvolatile memory controller for controlling a nonvolatile memory, wherein the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks includes a plurality of memory cells and is an erase unit for data in the nonvolatile memory, each of the plurality of memory cells records 1 bit, or 2, 3, or 4 bits of information, degradation in characteristics of the plurality of memory cells differs according to an amount of information that is recorded, and wherein the nonvolatile memory controller includes: a control unit for controlling reading, writing and erasure of data to and from the nonvolatile memory; and a stress table for recording a degradation level of the plurality of memory cells in block units, wherein the control unit records, in the stress table, the degradation level of the plurality of memory cells according to a bit count of information stored in the plurality of memory cells for each cycle of data erasure from the plurality of blocks by adding an additional value to a value of a previous degradation level stored in the stress table, and wherein the additional value of a plurality of memory cells that records 1 bit of information is lower than the additional value of memory cells that record 2, 3 or 4 bits of information.