Patent ID: 7202170
Filing Date: 2007-04-10
Classification: H01L

Abstract:
1. A semiconductor process for controlling etching profile, comprising the steps of: providing a plurality of substrates, wherein each substrate comprises a film to be etched and an overlying masking pattern layer thereon; and etching the film to be etched on each substrate in a plasma chamber using the masking pattern layer as an etch mask, a polymer layer being deposited over the inner wall of the plasma chamber during the etching; wherein an intermediary cleaning process is performed in the plasma chamber between the etchings before the deposited polymer layer reaches such a degree as to induce lateral etching on the film to be etched of the next substrate, wherein the intermediary cleaning process is performed for 1˜3 minutes, and wherein the intermediary cleaning process further comprises the steps of: using O using Cl