Patent ID: 6177862
Filing Date: 2001-01-23
Classification: G06F,H03K

Abstract:
A comparator, comprising:a plurality of coincidence detection circuits for comparing first bit data and second bit data and generating a plurality of detection signals that indicate a coincidence detection result for each bit; anda decision circuit, connected to the plurality of coincidence detection circuits, for receiving the plurality of detection signals and generating a decision signal indicating the coincidence decision results of the first and second bit data, the decision circuit including a plurality of switching circuits that operate in parallel in response to the plurality of detection signals, respectively, to generate the decision signal, whereinsaid decision circuit includes a first inverter circuit for receiving a first control signal and outputting an inverse signal of the first control signal from an output terminal thereof, andsaid comparator further comprises a second inverter circuit having an output terminal connected to an input terminal of the first inverter circuit for receiving a second control signal and supplying the first control signal that is an inverse of the second control signal to the first inverter circuit.