Patent ID: 8951848
Filing Date: 2015-02-10
Classification: H01L,H05K

Abstract:
1. A method for manufacturing a chip package, comprising: providing a circuit board, wherein the circuit board comprises an insulation layer, the insulation layer has a first surface, an opposite second surface, and a plurality of through holes passing through the first and second surfaces, a patterned electrically conductive layer is formed on the first surface of the insulation layer, the patterned electrically conductive layer has a plurality of portions exposed in the through holes to serve as a plurality of first conductive pads, a solder mask layer covers the patterned electrically conductive layer, the solder mask defines a plurality of openings to expose parts of the patterned electrically conductive layer, the exposed parts of the patterned electrically conductive layer serves as a plurality of second conductive pads, the second conductive pads are electrically connected to the first conductive pads respectively, a seed layer is formed over the second surface, inner surfaces of the through holes, and the first conductive pads are exposed in the through holes, and a stiffener is attached on the seed layer on the second surface and covers the through holes at the second surface; mounting a chip to the circuit board, and electrically connecting the chip with the second conductive pads of the circuit board; and removing the stiffener and the seed layer, thereby obtaining a chip package.