Patent ID: 6657835
Filing Date: 2003-12-02
Classification: H01L

Abstract:
An ESD protection circuit providing ESD protection for a mixed-voltage I/O circuit using stacked NMOS transistors with the substrate triggering technique comprising:a stacked NMOS with a first NMOS and a second NMOS, wherein the drain of the first NMOS is coupled to an I/O pad, the gate of the first NMOS is coupled to a first working voltage, the source of the first NMOS is coupled to the drain of the second NMOS, the gate of the second NMOS is coupled to an internal circuit, and the source of the second NMOS is coupled to a second working voltage; a lateral bipolar transistor having a collector and an emitter coupled to the drain of the first NMOS and to the source of the second NMOS, respectively; a substrate current generating circuit having a first terminal coupled to the I/O pad, a second terminal coupled to the second working voltage, and a third terminal coupled to the base of the lateral bipolar transistor, so that when the voltage at the I/O pad is over a predetermined threshold, a triggering current is sent out from the third terminal; and a substrate resistor having a first terminal coupled to the base of the bipolar transistor and a second terminal coupled to the second working voltage so that the triggering current produces a bias to the bipolar transistor.