Patent ID: 8546890
Filing Date: 2013-10-01
Classification: H01L

Abstract:
1. A CMOS structure, comprising: a substrate having a shallow trench isolation (STI); an NMOS transistor, comprising a n-type gate electrode and a n-type source/drain region; a PMOS transistor, comprising a p-type gate electrode and a p-type source/drain region, wherein the n-type gate electrode and the p-type gate electrode are physically separated and aligned according to a direction along the channel widths of the n-type gate electrode and the p-type gate electrode; and a single conductive contact being sandwiched in between the n-type gate electrode and the p-type gate electrode, and electrically connecting the n-type gate electrode and the p-type gate electrode, wherein the single conductive contact comprises metal, metal nitride or a combination thereof, the single conductive contact is wider at a top than a bottom thereof, and the bottom of the single conductive contact is in physical contact with the STI.