Patent ID: 8062951
Filing Date: 2011-11-22
Classification: H01L

Abstract:
1. A method of fabricating a shallow trench isolation (STI) region, comprising: providing a silicon substrate having a surface, the substrate having a <100> crystal orientation; providing the substrate with a pad oxide layer on the surface of the substrate and a nitride layer over the pad oxide layer; etching to form STI trenches extending into the silicon substrate from the surface thereof; filling the STI trenches with oxide; forming a notch in the oxide layer extending into the silicon substrate; forming an epitaxial layer selected from the group consisting of silicon and silicon-germanium on a surface of the substrate, and growing the epitaxial layer in a lateral direction such that the epitaxial layer is extending partially over the STI trenches and fills the notch, the epitaxial layer constituting an active silicon region; the method further comprising: prior to etching to form the STI trenches, forming openings through the nitride layer and pad oxide layer, said openings extending to the surface of the substrate; after filling the STI trenches with oxide and filling the notch with the epitaxial layer, performing a chemical mechanical polishing (CMP) step such that the epitaxial layer in the notch is planarized to the level of the oxide in the trench; and fabricating a field effect transistor (FET) device on the epitaxial layer wherein an effective width of the FET device is increased.