Patent ID: 8487680
Filing Date: 2013-07-16
Classification: H03K

Abstract:
1. A full-digital clock duty cycle correction circuit, comprising: a sampling unit, receiving and sampling an input clock signal; a duty cycle correcting module, connected electrically to said sampling unit, and producing a first clock signal according to said input clock signal; a phase-lock module, connected electrically to said sampling unit and said duty cycle correcting module, inverting said first clock signal and producing a second clock signal, said sampling unit transmitting said first clock signal and said second clock signal to said phase-lock module, said phase-lock module detecting a positive-edge phase difference between said first clock signal and said second clock signal for aligning the positive edges of said first clock signal and said second clock signal, said sampling unit transmitting said positive-edge-aligned first clock signal and said positive-edge-aligned second clock signal to said duty cycle correcting module, said duty cycle correcting module comparing a pulse width difference between said first clock signal and said second clock signal for adjusting the pulse widths of said first clock signal and said second clock signal until the pulse widths are identical, and outputting said second clock signal as a third clock signal.