Patent ID: 8724679
Filing Date: 2014-05-13
Classification: H04B

Abstract:
1. A transceiver comprising: a digital block, a transmit chain, a substrate-reactive-coupled (SRC) network, and a receive chain serially coupled to form a closed loop; a plurality of estimation and/or compensation blocks in said digital block; a stimulus signal from said estimation and/or compensation block applied to said transmit chain; and said estimation and/or compensation block receives a resultant signal from said receive chain within said closed loop and estimating and/or compensating said resultant signal to calibrate said transceiver, wherein a first estimation/compensation block disables all transmit LPFs and DACs; a transmit LO leaks an I/Q sinusoidal signal into said transmit chain; an up-converted I/Q sinusoidal signal coupled into said receive chain by said SRC network; said resultant signal of said receive chain coupled into said first estimation/compensation block; and said first estimation/compensation block compensates an I/Q imbalance of said receive chain.