Patent ID: 6889336
Filing Date: 2005-05-03
Classification: G06F

Abstract:
1. A synchronous integrated circuit device, comprising: a clock input buffer configured to receive a system clock signal and to generate a buffered clock signal; a delay line coupled to the clock input buffer, the delay line configured to receive the buffered clock signal and to generate a delayed clock signal; and an output circuit coupled to the delay line, the output circuit including a plurality of output signal paths configured to output the plurality of output signals synchronously with the system clock signal by using the delayed clock signal; wherein at least one of the output signal paths includes a delay circuit and an output buffer coupled to the delay circuit, each delay circuit is connected to a delay control circuit which determines the amount of delay required for the at least one of the output signal paths based upon feedback from the plurality of output signal paths, and each delay circuit is configured to provide a programmable delay to the delayed clock signal to generate a unique delayed clock signal which is used for clocking an output signal into the respective output buffer.