Patent ID: 6711089
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A synchronization cell comprising:a first synchronizer, the first synchronizer having a data input port, D1, and a data output port, Q1, the first synchronizer receiving data at said data input port at a first clock rate corresponding to a first clock, the first synchronizer having a clock port for receiving a clock signal; and a second synchronizer, the second synchronizer having a data input port, D2, and a data output port, Q2, the data input port D2 of the second synchronizer being directly connected to the data output port Q1 of the first synchronizer, the second synchronizer having a clock port for receiving a clock signal, the first and second synchronizers being generally adjacent one another, the synchronizers each receiving a second clock signal at their respective clock ports over respective clock lines, the clock lines being tied together, the second clock signal having logic levels that control the propagation of data through the synchronizers, wherein data received at the data input port of the second synchronizer from the data output port of the first synchronizer is output from the data output port of the second synchronizer at a second clock rate that corresponds to the second clock, the second clock rate being different from the first clock rate.