Patent ID: 7613873
Filing Date: 2009-11-03
Classification: G11C

Abstract:
1. A memory system, comprising: a memory controller, comprising: an input/output cell; and a plurality of dynamic random access memory banks, wherein the memory controller sends commands to the plurality of dynamic random access memory banks through the input/output cell; wherein the memory controller performs calibrations on the plurality of dynamic random access memory banks; wherein the memory controller performs refreshes on the plurality of dynamic random access memory banks; and wherein the memory controller defers refreshes during calibrations, maintains a count of a number of deferred refreshes, decrements the count responsive to a confirmation of a completed refresh, and determines that all deferred refreshes are completed if the count reaches zero; wherein the refresh timer initiates a refresh command to the initialization logic; and wherein the initialization logic determines whether the memory controller is performing calibrations and wherein if the memory controller is performing calibrations, the initialization logic defers the refresh command and increments the count.