Patent ID: 9069925
Filing Date: 2015-06-30
Classification: G06F

Abstract:
1. A method of manufacturing a circuit, the method comprising: receiving a design for an integrated circuit based on a first fabrication process, the design comprising at least a reference to at least one first design library associated with the first fabrication process; scaling, by resizing, physical dimensions of a first part of the integrated circuit comprising scalable circuit elements resizable for fabrication according to a second fabrication process creating devices having a smaller device dimension than the first fabrication process; altering a second part of the integrated circuit comprising un-scalable circuit elements non-amenable to resizing for fabrication according to the second fabrication process, altering comprising changing a design of the second part of the integrated circuit; computing at least one settable scaling factor for the integrated circuit with a power density of the integrated circuit remaining substantially constant or decreasing, the at least one settable scaling factor based on a feature of the integrated circuit fabricated according to the first fabrication process in relation to a feature of the integrated circuit fabricated according to the second fabrication process, the at least one settable scaling factor further based on at least one fixed scaling factor that is based on the fabrication processes and indicating a ratio of a feature of the integrated circuit fabricated according to a first fabrication process to a feature of the integrated circuit fabricated according to a second fabrication process; setting, by using a computer, integrated circuit parameters based on the at least one settable scaling factor; and manufacturing the integrated circuit using the integrated circuit parameters; wherein the at least one fixed scaling factor further comprises an area scaling factor, wherein the at least one fixed scaling factor further comprises at least a delay scaling factor and wherein the at least one settable scaling factor further comprises a voltage level scaling factor, and wherein a relationship between the voltage level scaling factor and the at least one fixed scaling factor is expressible as where k V is the voltage level scaling factor, k A is the area scaling factor, and k t is the delay scaling factor.