Patent ID: 6660608
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method of making a CMOS device having a p-channel transistor and an n-channel transistor, said method comprising the steps of:providing a substrate having an n-type tub in which the p-channel transistor is to be formed and a p-type tub in which the n-channel transistor is to be formed; forming a transistor gate disposed over each tub and each gate including an upper polysilicon level and a lower oxide level; and non-selectively implanting aluminum into: both of the tubs, the aluminum providing dopant species for a source region and a drain region of the p-channel transistor and being present in a source region and a drain region of the n-channel transistor; and both of the upper polysilicon levels of the gates to reduce the resistivity of the upper polysilicon levels of each of the gates.