Patent ID: 9058244
Filing Date: 2015-06-16
Classification: G06F

Abstract:
1. A system for conducting memory transactions, comprising: a non-volatile main memory; and a memory buffer including a plurality of cache lines, each of the cache lines including content stored therein by a write command associated with a single transaction that includes multiple distinct write commands that form the single transaction, each of the cache lines including a first bit signifying whether all of the distinct write commands associated with the transaction, corresponding to the content of the cache line, have been performed to completion and each of the cache lines including a second bit signifying whether the content of the cache line matches content of a corresponding location of the non-volatile main memory, wherein when the first bit of a cache line of the plurality of cache lines signifies that all of the distinct write commands associated with the transaction have not been performed to completion and the second bit of the cache line of the plurality of cache lines signifies that the content of the cache line does not match the content of the corresponding location of the non-volatile main memory, the cache line is set to be unreadable by all transactions except the single transaction, wherein when the first bit of the cache line of the plurality of cache lines signifies that all of the distinct write commands associated with the transaction have been performed to completion and the second bit of the cache line signifies that the content of the cache line does not match the content of the corresponding location of the non-volatile memory, the cache line is set to be in a read-only state, and wherein when the first bit of the cache line of the plurality of cache lines signifies that all of the distinct write commands associated with the transaction have been performed to completion and the second bit of the cache line signifies that the content of the cache line does match the content of the corresponding location of the non-volatile memory, the cache line is set to be in a shared state.