Patent ID: 8198654
Filing Date: 2012-06-12
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first inverter circuit positioned in a first row and a first column in a matrix orientation on a substrate, wherein the first inverter circuit has: a first gate insulating film surrounding the periphery of a first island-shaped semiconductor layer, a first gate electrode surrounding the periphery of the first gate insulating film, a second gate insulating film surrounding the periphery of the first gate electrode, a first columnar semiconductor layer surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of a first conductivity type positioned on the upper part of the first island-shaped semiconductor layer, a second lower part high concentration semiconductor layer of the first conductivity type positioned on the lower part of the first island-shaped semiconductor layer, a first upper part high concentration semiconductor layer of a second conductivity type positioned on the upper part of the first columnar semiconductor layer, and a second lower part high concentration semiconductor layer of the second conductivity type positioned on the lower part of the first columnar semiconductor layer; further comprising a second inverter circuit positioned in a second row and a second column in a matrix orientation on the substrate, wherein the second inverter circuit has: a second island-shaped semiconductor layer, a third gate insulating film surrounding the periphery of the second island-shaped semiconductor layer, a second gate electrode surrounding the periphery of the third gate insulating film, a fourth gate insulating film surrounding the periphery of the second gate electrode, a second columnar semiconductor layer surrounding the periphery of the fourth gate insulating film, a third upper part high concentration semiconductor layer of the first conductivity type positioned on the upper part of the second island-shaped semiconductor layer, a fourth lower part high concentration semiconductor layer of the first conductivity type positioned on the lower part of the second island-shaped semiconductor layer, a third upper part high concentration semiconductor layer of the second conductivity type positioned on the upper part of the second columnar semiconductor layer, and a fourth lower part high concentration semiconductor layer of the second conductivity type positioned on the lower part of the second columnar semiconductor layer; further comprising a first selection transistor positioned in the first row and second column of the matrix orientation on the substrate, wherein this first selection transistor has: a third island-shaped semiconductor layer, a fifth gate insulating film surrounding the periphery of the third island-shaped semiconductor layer, a third gate electrode surrounding the periphery of the fifth gate insulating film, a fifth upper part high concentration semiconductor layer of the first conductivity type positioned on the upper part of the third island-shaped semiconductor layer, and a sixth lower part high concentration semiconductor layer of the first conductivity type positioned on the lower part of the third island-shaped semiconductor layer, and further comprising a second selection transistor positioned in the second row and first column of the matrix orientation on the substrate, wherein the second selection transistor has: a fourth island-shaped semiconductor layer, a sixth gate insulating film surrounding the periphery of the fourth island-shaped semiconductor layer, a fourth gate electrode surrounding the periphery of the sixth gate insulating film, a seventh upper part high concentration semiconductor layer of the first conductivity type positioned on the upper part of the fourth island-shaped semiconductor layer, and an eighth lower part high concentration semiconductor layer of the first conductivity type positioned on the lower part of the fourth island-shaped semiconductor layer; further comprising a ninth lower part high concentration semiconductor layer of the first conductivity type that contacts the second lower part high concentration semiconductor layer of the first conductivity type, the second lower part high concentration semiconductor layer of the second conductivity type and the eighth lower part high concentration semiconductor layer of the first conductivity type; and a tenth lower part high concentration semiconductor layer of the first conductivity type positioned that contacts the fourth lower part high concentration semiconductor layer of the first conductivity type, the fourth lower part high concentration semiconductor layer of the second conductivity type and the sixth lower part high concentration semiconductor layer of the first conductivity type; and having a first compound layer of semiconductor and metal that contacts the first upper part high concentration semiconductor layer of the first conductivity type; a second compound layer of semiconductor and metal that contacts the first lower part high concentration semiconductor layer of the second conductivity type; a third compound layer of semiconductor and metal that contacts the second lower part high concentration semiconductor layer of the second conductivity type, the ninth lower part high concentration semiconductor layer of the first conductivity type and the eighth lower part high concentration semiconductor layer of the first conductivity type; a fourth compound layer of semiconductor and metal that contacts the seventh upper part high concentration semiconductor layer of the first conductivity type; a fifth compound layer of semiconductor and metal that contacts the third upper part high concentration semiconductor layer of the first conductivity type; a sixth compound layer of semiconductor and metal that contacts the third upper part high concentration semiconductor layer of the second conductivity type; a seventh compound layer of semiconductor and metal that contacts the fourth lower part high concentration semiconductor layer of the second conductivity type, the tenth lower part high concentration semiconductor layer of the first conductivity type and the sixth lower part high concentration semiconductor layer of the first conductivity type; an eighth compound layer of semiconductor and metal that contacts the fifth upper part high concentration semiconductor layer of the first conductivity type; a first contact for electrically connecting the first gate electrode and the seventh compound layer; and a second contact for electrically connecting the second gate electrode and the third compound layer.