Patent ID: 6784824
Filing Date: 2004-08-31
Classification: G06G,G06J

Abstract:
An analog-to-digital converter (ADC) stage for use in ADCs, comprising:an amplifier having first and second input terminals, and an output terminal to provide an analog ADC residue signal; first and second capacitances coupled to sample an input voltage signal and a complemented input voltage signal respectively in response to a first clock phase; a level shifting circuit coupled to receive the input voltage signal, and to select one of a plurality of reference voltages in response to a second clock signal; a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to the second clock phase; a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier and to reference the second capacitance to the selected reference voltage in response to the second clock phase; wherein the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the selected reference voltage to create the analog ADC residue signal for use in a subsequent ADC stage.