Patent ID: 6742060
Filing Date: 2004-05-25
Classification: G06F

Abstract:
An apparatus, comprising:a first storage device interface; a second storage device interface; a first controller coupled to the first storage device interface, the first controller including an interrupt signal input; a second controller coupled to the second storage device interface; and an interrupt conditioning logic including a look-up table, the look-up table having a processor access port to receive data from a processor, the look-up table having a first address input to receive an interrupt signal from the first storage device interface, the look-up table further having a second address input to receive an interrupt pending signal from the second controller, the interrupt conditioning logic to produce an output to the first controller interrupt signal input according to the contents of the look-up table identified by the first and second address inputs, the interrupt conditioning logic to mask the interrupt signal from the first storage device interface if no storage device is coupled to the first storage device interface.