Patent ID: 6964893
Filing Date: 2005-11-15
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming a structure comprising a p-well and an n-well formed on a surface of a semiconductor substrate, an n-type source and an n-type drain formed on the surface of the semiconductor substrate and configured to sandwich a channel region on a n-type MIS transistor formed at the p-well, an insulation film having openings, at bottom of which the p-well and the n-well are exposed, the n-type source and n-type drain formed on the p-well and configured to sandwich the associated opening, and a p-type source and a p-type drain formed on the n-well and configured to sandwich the associated opening; forming a gate insulation film on the p-well and the n-well exposed at the bottoms of the openings; forming a first metal-containing film on the p-well and the n-well exposed at the bottoms of the openings, the first metal-containing film having a Fermi level on a conductive band side from a substantial center of a band gap of the semiconductor substrate; removing the first metal-containing film on the n-well; forming a conductive coating film on the first metal-containing film and on the gate insulation film formed on the n-well, the conductive coating film having a Fermi level on a valence band side from a substantial center of the band gap of the semiconductor substrate; and forming a second metal-containing film on the conductive coating film, the second metal-containing film having a lower resistance than the first metal-containing film and the conductive coating film, thus filling the openings.