Patent ID: 6207519
Filing Date: 2001-03-27
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device comprising:forming an insulating layer over a surface of a semiconductor substrate;forming a gate electrode over the insulating layer;forming a buffer oxide layer by oxidizing the gate electrode:forming a first spacer over a sidewall of the gate electrode and over the buffer oxide layer;forming a second spacer over a sidewall of the first spacer;forming a first impurity region doped with a first conductivity type impurity at a first concentration using the buffer oxide layer as a mask, said first impurity region being formed at a first junction depth in a surface of the substrate and being aligned during formation by the buffer oxide layer such that the first impurity region self-aligns at an edge of the gate electrode;forming a second impurity region doped with a second conductivity type impurity at a second concentration, said second impurity region being formed at a second junction depth in the substrate and being aligned during formation by the first spacer such that the second impurity region self-aligns at an edge of the first spacer; andforming a third impurity region doped with the first conductivity type impurity at a third concentration, said third impurity region being formed at a third junction depth in the second impurity region and being aligned during formation by the second spacer such that the third impurity region self-aligns at an edge of the second spacer, the third junction depth being less than the second junction depth.