Patent ID: 8296775
Filing Date: 2012-10-23
Classification: G06F

Abstract:
1. A method of managing register states in a computing machine, the computing machine comprising at least one physical processor, a plurality of virtual processors, a hypervisor, and at least one physical register, the method comprising: associating a data structure with at least one of the virtual processors, said data structure configured to store data representative of a state of at least one physical register; determining whether the physical register has an immediate effect on an operation of a first virtual processor; if the physical register has an immediate effect on the operation of the first virtual processor, then switching an execution context of the physical processor from a first virtual processor to the hypervisor and saving data representative of the state of a physical register in a data structure associated with the first virtual processor; if the physical register does not have an immediate effect on the operation of the first virtual processor and is not capable of being intercepted, then switching the execution context of the physical processor from the first virtual processor to the hypervisor and saving data representative of the state of the physical register in the data structure associated with the first virtual processor; if the physical register does not have an immediate effect on the operation of the first virtual processor and is capable of being intercepted, then switching the execution context of the physical processor from the first virtual processor to the hypervisor and saving data representative of the state of the physical register in the data structure associated with the first virtual processor if the physical register is a hot register; if the physical register does not have an immediate effect on the operation of the first virtual processor and is capable of being intercepted, then switching the execution context of the physical processor from the first virtual processor to the hypervisor without saving data representative of the state of the physical register if the physical register is a cold register; switching the execution context of the physical processor from the hypervisor to a second virtual processor; if the physical register is the cold register, then intercepting, with the hypervisor, an attempt to access the physical register by the second virtual processor by transferring control to the hypervisor when the second virtual processor attempts to access the physical register; and emulating an action in response to the intercept.