Patent ID: 6238961
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A process for manufacturing a semiconductor integrated circuit device having MISFETs each having a gate electrode and a source and drain, comprising the following steps:(a) forming isolation regions on a main surface of a semiconductor substrate;(b) forming active regions in a region surrounded by said isolation regions;(c) forming a first interconnection serving as the gate electrode of said each MISFET over said each active region;(d) forming a pair of semiconductor regions each serving as the source and drain of said each MISFET within said active regions on both sides of said first interconnection;(e) forming a first insulating film over said first interconnection;(f) defining connecting holes in said first insulating film lying over at least one semiconductor region of said pair of semiconductor regions;(g) forming a first connecting member electrically connected to said one of said pair of semiconductor regions within said each connecting hole;(h) successively forming a second insulating film, a third insulating film, a fourth insulating film and a first coating over said connecting member;(i) forming a first resist film having an opening crossing said first interconnection over said first coating;(j) etching said first coating exposed at the bottom of the opening of said first resist film to thereby define an opening therein;(k) etching the fourth insulating film bare in the bottom of the opening of said first coating by a method in which an etching rate for said fourth insulating film is faster than that for each of said first coating and said third insulating film, thereby defining an opening;(l) etching the third insulating film bare in the bottom of the opening defined in said fourth insulating film;(m) forming a second resist film having an opening over the opening defined in said first coating;(n) etching said second insulating film bare in the bottom of the opening defined in said second resist film by a method in which an etching rate for said second insulating film is greater than that for each of said second resist film and said first coating to thereby define an opening therein and expose said connecting member at the bottom of said opening;(o) forming a first conductor film connected to said connecting member over the main surface of said semiconductor substrate including the interiors of the openings defined in said second insulating film, said third insulating film and said fourth insulating film; and(p) removing said first conductor film lying over said fourth insulating film.