Patent ID: 6208092
Filing Date: 2001-03-27
Classification: G09G,H03L

Abstract:
A digital deflection processing apparatus in a cathode ray tube, comprising:synchronous signal and clock signal generating means for selecting, as a selected signal, either a first composite synchronous signal extracted from a composite video broadcasting signal or at least one externally-generated second composite synchronous signals in response to a synchronous control signal and outputting the selected signal as a third composite synchronous signal, and for generating a main clock signal;synchronous signal phase converting means for lagging or leading the phase of the third composite synchronous signal by a first predetermined value and outputting the lagged or led third composite synchronous signal as a deflection composite synchronous signal comprising a deflection horizontal synchronous signal and a deflection vertical synchronous signal;coordinate value generating means for performing counting, synchronized with the deflection composite synchronous signal, processing the counting result with second predetermined values, and outputting the processed result as X and Y beam-axis coordinate values;selection signal generating means for processing the counting result and outputting the logical combination result as selection signals;horizontal drive signal generating means for determining rising and falling edges of a horizontal drive signal, using a phase difference between a fly back pulse and the horizontal drive signal;interpolation value calculating means for calculating subsequent distortion correcting functions in response to the selection signals, calculating the respective interpolation values of the X and Y axis coordinate values using the distortion correcting functions, and outputting calculated interpolation values as output signals; andoutput adjusting means for adjusting the gains of the output signals based on a voltage obtained by monitoring EHT of the cathode ray tube;wherein the third composite synchronous signal comprises a third horizontal synchronous signal and a third vertical synchronous signal and the main clock signal is output to the synchronous signal phase converting means, the coordinate value generating means, the selection signal generating means, the horizontal drive signal generating means, the interpolation value calculating means, and the output adjusting means.