Patent ID: 6130132
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A method of forming split gate electrode MOS FET devices including the steps in the sequence as follows:form a tunnel oxide layer over a semiconductor substrate,form a doped first polysilicon layer, having an upper surface over said tunnel oxide layer, followed by development of a native oxide layer upon said upper surface of said first polysilicon layer,form a mask layer over said native oxide layer,form a cell-defining mask over said mask layer with a opening therethrough where a floating gate electrode stack is to be formed,etch through said opening in said cell-defining mask to form a window through said mask layer and said native oxide down to said upper surface of said first polysilicon layer,form a cap on said upper surface of said first polysilicon layer at the bottom of said window,strip said mask layer from said native oxide layer and said first polysilicon layer,remove portions of said tunnel oxide layer and said first polysilicon layer aside from said cap thereby forming a floating gate electrode stack with a bird's beak peak on the periphery of said upper surface of said first polysilicon layer,form an inter-polysilicon dielectric layer and a control gate layer over exposed portions of said substrate and covering said stack,pattern said inter-polysilicon dielectric layer and said control gate layer into a split gate electrode,form a source region self-aligned with said floating gate electrode stack, and a drain region self-aligned with said split gate electrode.