Patent ID: 8953111
Filing Date: 2015-02-10
Classification: G02F

Abstract:
1. A pixel array comprising: a plurality of data lines and a plurality of scan lines, the data lines and the scan lines being disposed on a substrate; a plurality of sub-pixel units disposed on the substrate in an array, wherein each of the sub-pixel units has at least one active device and at least one pixel electrode electrically connected to the at least one active device, and the at least one active device is electrically connected to a corresponding one of the scan lines and a corresponding one of the data lines; a plurality of capacitor electrode line sets disposed on the substrate, wherein each of the capacitor electrode line sets has N capacitor electrode lines, the N capacitor electrode lines partially overlap with the at least one pixel electrode of each of the sub-pixel units to form a plurality of storage capacitors, and N≧2; and a plurality of connecting structure sets made of a conductive material, the N capacitor electrode lines in each of the capacitor electrode line sets being electrically connected to one another by each of the connecting structure sets which crosses over the corresponding one of the scan lines so as to have the conductive material among the N capacitor electrode lines in each of the capacitor electrode line sets and crossing over the corresponding scan line, wherein there is no connecting structure disposed between the capacitor electrode line sets such that each of the capacitor electrode line sets is not connected to the other capacitor electrode line sets and the corresponding one of the scan lines is not crossed over by any connecting structure set so as to have no conductive material among the capacitor electrode line sets and crossing over the corresponding scan line.