Patent ID: 6092218
Filing Date: 2000-07-18
Classification: G06F

Abstract:
A computer comprising:a master cpuset;a checker cpuset configured to operate in synchronism with said master cpuset; anda data bus coupled to each said cpuset wherein each said cpuset contains a microprocessor and a hardware element coupled to said microprocessor;wherein said master cpuset microprocessor is configured to make a first access to said master cpuset hardware element;wherein, in a self-referential-access mode, if said first access is a read, said master cpuset is configured to convey first data associated with said first access to said data bus, and said checker cpuset is configured to read said first data into said checker cpuset microprocessor; andwherein in an interal-access mode said microprocessor of each said cpuset is configured to access said corresponding hardware element without conveying data associated with said access to said data bus.