Patent ID: 6140180
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method of fabricating storage capacitor for a cell unit of a semiconductor dynamic random-access memory device, the device includes a substrate having a gate structure of the cell unit transistor formed thereon that serves as the bit line for the cell unit of the memory device, and the device further having a polysilicon word line electrically connected to the first of the source/drain regions of the transistor, the method comprising the steps of:blanket-depositing a first insulating layer over the surface of the device substrate and covering the word line and the bit line;forming a first polysilicon layer over the surface of the first insulating layer;patterning the first polysilicon layer to form a first opening therein, the first opening being located substantially above the second of the source/drain regions of the transistor;forming an oxide layer covering the first polysilicon layer as well as filling into the first opening without completely filling the first opening;etching into the oxide layer and the insulating layer in a self-aligned procedure to form a second opening that exposes the surface of the second of the source/drain regions of the transistor;forming a second polysilicon layer over the surface of the first polysilicon layer and filling into the space of the second opening to be in electrical contact with the second of the source/drain regions of the transistor;patterning the first and the second polysilicon layers, and the combination of the first and second polysilicon layers constituting the bottom electrode of the storage capacitor; andforming a dielectric layer, which has a nitride-oxide multiple-layered configuration, over the surface of the second polysilicon layer, and further forming a third polysilicon layer over the surface of the dielectric layer, with the third polysilicon layer being utilized as the top electrode of the storage capacitor.