Patent ID: 7505354
Filing Date: 2009-03-17
Classification: G11C

Abstract:
1. A memory device comprising: at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines, and coupled between a power line and a ground line; a word line decoder coupled to one end of the word line for selecting the word lines in response to input signals; and a voltage control circuit coupled to another end of the word line for connecting the word line to a ground voltage when the memory device is in a sleep mode, wherein the voltage control circuit is supplied by DC (direct current) power, wherein the voltage control circuit comprises an NMOS transistor and a PMOS transistor, the NMOS transistor having a source coupled to ground, a drain coupled to the word line, and a gate coupled to a drain of the PMOS transistor, which has a gate coupled to the drain of the NMOS transistor, and a source coupled to a predetermined DC voltage.