Patent ID: 7958341
Filing Date: 2011-06-07
Classification: G06F

Abstract:
1. An integrated circuit comprising a microprocessor matrix of mesh-interconnected matrix processors, each matrix processor comprising: an instruction processing pipeline configured to execute a set of instructions including a data streaming instruction; and a hardware data switch connected to the instruction processing pipeline and configured to route inter-processor messages through inter-processor matrix links of said each matrix processor, wherein, in response to execution of the data streaming instruction by the instruction processing pipeline, the data switch is configured to transfer a data stream including a plurality of consecutive messages over a corresponding plurality of consecutive clock cycles from a first inter-processor matrix link to a second inter-processor matrix link, wherein on each clock cycle of the plurality of clock cycles, the data switch is configured to receive a message over the first inter-processor matrix link, and send the message to the second inter-processor matrix link for transmission.