Patent ID: 7774393
Filing Date: 2010-08-10
Classification: H03M

Abstract:
1. A processor, comprising: an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, wherein a smaller-exponent one of said floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of said floating-point operands; an alignment shifter coupled to provide an input to said adder and configured, in a first mode of operation that is active during execution of a floating-point addition instruction, to align said floating-point operands prior to said addition by shifting the respective mantissa of said smaller-exponent operand towards a least-significant bit position; and a rounding circuit configured to round said sum and a normalization circuit configured to normalize said sum, wherein said rounding circuit and said normalization circuit are configured such that during execution of any floating-point addition instruction, either said normalization circuit is operable to perform a normalization shift of said sum by more than one bit position, or said rounding circuit is operable to round said sum, but not both; wherein said adder, said alignment shifter, said rounding circuit, and said normalization circuit are included within a floating-point adder pipeline comprising a plurality of pipeline stages, wherein the floating-point adder pipeline is configured to concurrently process multiple floating-point addition instructions that concurrently occupy different pipeline stages; wherein said adder is operable, during execution of an instruction to convert an integer operand to floating-point format, to produce a result of conversion of said integer operand as said sum, wherein for at least some values of said integer operand, conversion of said integer operand to floating-point format requires both a normalization shift by more than one bit position and rounding, and wherein said rounding circuit is configured to round said result of conversion of said integer operand; wherein said alignment shifter is further configured, in a second mode of operation that is active during execution of said instruction to convert said integer operand to floating-point format, to perform said normalization shift required by said conversion prior to said adder producing said result of conversion of said integer operand as said sum, such that execution of said instruction to convert said integer operand to floating-point format does not require additional execution latency relative to execution of said floating-point addition instruction.