Patent ID: 6437624
Filing Date: 2002-08-20
Classification: H03K

Abstract:
An edge-triggered latch providing a balanced complementary output, said edge-triggered latch comprising:a pair of complementary data inputs; a clock input; and a plurality of source-to-drain connected pass-transistor logic (PTL) transistors forming a pair of symmetric data paths from said complementary data inputs to a pair of complementary data outputs, wherein each of said pair of symmetric data paths includes: a first N-type field effect transistor receiving one of said pair of complementary data inputs at its source terminal and receiving at its gate terminal a delayed inverted translation of a clock signal from said clock input; and a second N-type field effect transistor receiving said one of said pair of complementary data inputs at its source terminal from the drain terminal of said first N-type field effect transistor and receiving said clock signal at its gate terminal.