Patent ID: 7870452
Filing Date: 2011-01-11
Classification: G01R

Abstract:
1. A method of testing an integrated circuit, comprising: providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement timed with a first, scan, clock signal, and propagating the test vector bits between adjacent portions of the shift register arrangement timed with the first clock signal; providing the test vector from the shift register arrangement to terminals of the integrated circuit; providing an output response of the integrated circuit to the test vector to the shift register arrangement as parallel output response bits, under the control of an enable signal; propagating the output response bits between adjacent portions of the shift register arrangement timed with the first clock signal and outputting the output response out of the shift register arrangement in series timed with the first clock signal; and analyzing the output response to test the integrated circuit function, wherein the output response of the integrated circuit to the test vector is provided under the further control of a second clock signal which is slower than the first clock signal; and wherein the first and second clock signals comprise a single signal having at least first and second portions with different clock rates, the first and second portions defining the first and second clock signals.