Patent ID: 6560212
Filing Date: 2003-05-06
Classification: H03K,H04B,H04J

Abstract:
A circuit for generating an offset sequence from a reference sequence, the apparatus comprising:a multiplexer adapted to select a value of either the reference sequence or a delayed reference sequence based on a select signal, wherein the reference sequence is a pseudo-noise (PN) sequence having at least one incoming insert-bit and the offset sequence is a cyclic-shifted reference sequence; a mask circuit adapted to apply a multibit mask to the value selected by the multiplexer and at least one previous value selected by the multiplexer to generate a value of the offset sequence; a decision circuit adapted to insert, if necessary, one or more outgoing insert-bits into the offset sequence, wherein the decision circuit generates the select signal based on either the presence of the incoming insert-bit of the reference sequence or the presence of the outgoing insert-bit of the offset sequence.