Patent ID: 6505225
Filing Date: 2003-01-07
Classification: G06F

Abstract:
An adder logic circuit for performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of said first numerical value comprising:an adder element for performing an addition operation of said second numerical value and a third numerical value Composed of a lower bit sequence of said first numerical value, the bit width of said third numerical value being equal to the bit width of said second numerical value; and a higher bit handling logic circuit connected to said adder element for receiving a carry out from the most significant bit of said adder element together with a fourth numerical value composed of a higher bit sequence composed of the remainder of said first numerical value, the most significant bit of said the second numerical value in order to output one of said fourth numerical value, said fourth numerical value as incremented and said fourth numerical value as decremented in accordance with the carry out from the most significant hit of said adder element and the most significant bit of said second numerical value.