Patent ID: 7167035
Filing Date: 2007-01-23
Classification: H03L

Abstract:
1. A delay circuit comprising: a first delay portion for receiving an input signal and delaying the input signal by a first predetermined amount, the first delay portion comprising a first plurality of same-type logic gates within the first plurality comprising transistors for delaying the input signal, the transistors of the first plurality of same-type logic gates having a substantially same transistor threshold voltage and a substantially same transistor gate length; and a second delay portion coupled in series with the first delay portion for delaying the input signal by a second predetermined amount in addition to the first predetermined amount, the second delay portion comprising a second plurality of same-type logic gates within the second plurality comprising transistors for delaying the input signal, the transistors of the second plurality of same-type logic gates having a substantially same transistor threshold voltage and a substantially same transistor gate length, at least one of transistor threshold voltage, transistor gate length and type of logic gate differing between the first delay portion and the second delay portion.