Patent ID: 8053911
Filing Date: 2011-11-08
Classification: H01L,H05K,Y02P

Abstract:
1. An electronic device, comprising: a wiring substrate having a first surface and a second surface opposite to the first surface; a data processing device having a plurality of first data system terminals, a plurality of second data system terminals, a plurality of third data system terminals, a plurality of fourth data system terminals, a first clock terminal, a second clock terminal and a command address terminal, and mounted on the first surface of the wiring substrate; a first memory device having a plurality of data system terminals, a clock terminal and a command address terminal, and mounted on the first surface of the wiring substrate and arranged next to the data processing device in a plan view; a second memory device having a plurality of data system terminals, a clock terminal and a command address terminal, and mounted on the first surface of the wiring substrate and arranged next to the data processing device in the plan view; a third memory device having a plurality of data system terminals, a clock terminal and a command address terminal, and mounted on the second surface of the wiring substrate such that the first memory device is arranged over the third memory device in the plan view; and a fourth memory device having a plurality of data system terminals, a clock terminal and a command address terminal, and mounted on the second surface of the wiring substrate such that the second memory device is arranged over the fourth memory device in the plan view, and arranged next to the third memory device in the plan view; wherein the first data system terminals of the data processing device are coupled to the data system terminals of the first memory device through a plurality of first data wiring of the wiring substrate; wherein the second data system terminals of the data processing device are coupled to the data system terminals of the second memory device through a plurality of second data wiring of the wiring substrate; wherein the third data system terminals of the data processing device are coupled to the data system terminals of the third memory device through a plurality of third data wiring of the wiring substrate; wherein the fourth data system terminals of the data processing device are coupled to the data system terminals of the fourth memory device through a plurality of fourth data wiring of the wiring substrate; wherein the first clock terminal of the data processing device is coupled to the clock terminal of each of two of the first, second, third and fourth memory devices through a first clock wiring of the wiring substrate; and wherein the second clock terminal of the data processing device is coupled to the clock terminal of each of others of the first, second, third and fourth memory devices through a second clock wiring of the wiring substrate.