Patent ID: 6072945
Filing Date: 2000-06-06
Classification: G06F,Y10S

Abstract:
An apparatus for automatically detecting electromigration violations in an integrated circuit design, the integrated circuit design having a functional hierarchy including a plurality of top-most level functional blocks each containing a plurality of functional cells, a plurality of external networks each interconnecting two or more of the top-most level functional blocks and together with the interconnected top-most level functional blocks forming a plurality of top-level nets, and further including a plurality of internal networks each contained within a respective one of the top-most level functional blocks and each interconnecting two or more functional cells within the respective one top-most level functional block, each of the external and internal networks including conductive signal traces and each of the functional cells having a drive strength associated therewith, said apparatus comprising:a layout file containing layout information for the integrated circuit design;a rules table containing electromigration process rules for conductive signal traces of the integrated circuit design; and,processing means for propagating upward within the functional hierarchy parasitic resistance and capacitance values of conductive signal traces of the integrated circuit design; for determining a lumped resistance a lumped capacitance and a lumped drive strength of each of the top-most level functional blocks; for determining a lumped resistance and lumped capacitance of each external network; for calculating at least one current value for each top-level net from the lumped resistance, the lumped capacitance and the lumped drive strength of the external networks and the top-most level functional blocks; for determining minimum electromigration dimensions for the conductive signal traces of the integrated circuit design based on the at least one current value for each of the top-most level nets, indexed to said rules table; for determining design dimensions of the conductive signal traces of the integrated circuit design; for comparing the design dimensions with the minimum electromigration dimensions; and for identifying violations of the fabrication process rules for the conductive signal traces of the integrated circuit design when the design dimensions are less than the minimum electromigration dimensions.