Patent ID: 8487687
Filing Date: 2013-07-16
Classification: G09G,H03F,H03K

Abstract:
1. An output buffer circuit for avoiding voltage overshoot, the output buffer circuit comprising: an input stage comprising a positive input terminal, for receiving an input voltage, and a negative input terminal, —the input stage generating a current signal according to the input voltage; an output bias circuit, coupled to the input stage, for generating a dynamic bias according to the current signal; an output stage, coupled to the input stage and the output bias circuit, comprising: an output terminal, reversely coupled to the negative input terminal; and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage; a clamp circuit, coupled to the input stage, the output bias circuit and the output stage, for drawing currents from the output terminal to help the current signal to return the dynamic bias to a proper level when the output voltage exceeds a predefined range; and a control unit, coupled to the clamp circuit, for activating the clamp circuit when the output buffer circuit receives the input voltage and for deactivating the clamp circuit to prevent a leakage current resulted by the clamp circuit when the output voltage reaches a steady state.