Patent ID: 6787410
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A method for fabricating a semiconductor device having:a semiconductor substrate; a first conductive-type deep well region formed inside the semiconductor substrate; a second conductive-type shallow well region formed in the first conductive-type deep well region; a dynamic threshold transistor formed on the second conductive-type shallow well region, a gate electrode of the dynamic threshold transistor being short-circuited to the second conductive-type shallow well region; a shallow element isolation region formed on the second conductive-type shallow well region and composed of STI with a depth shallower than a depth of an interface between the first conductive-type deep well region and the second conductive-type shallow well region; and a deep element isolation region formed on the first conductive-type deep well region by penetrating through the second conductive-type shallow well region and having an approximately constant width and a depth deeper than the depth of the interface between the first conductive-type deep well region and the second conductive-type shallow well region, the method comprising the steps of: forming a first film on a semiconductor substrate; forming a first open window on the first film; forming a first isolation trench by etching part of the semiconductor substrate with use of the first film as a mask; forming a second film on the first film and the first isolation trench; etching part of the first film with use of the second film as a mask; forming a second isolation trench by partially etching the semiconductor substrate with use of the first film as a mask; and depositing an isolating film on the first film, the first isolation trench and the second isolation trench for filling the first isolation trench and the second isolation trench.