Patent ID: 7713758
Filing Date: 2010-05-11
Classification: H01L

Abstract:
1. A method of processing a substrate using a gate-optimization procedure comprising: creating a patterned masking layer on the substrate; measuring one or more test structures in the patterned masking layer using a first integrated metrology (IM) procedure, the first IM procedure creating first IM procedure data comprising first real-time data for a first test structure, and wherein the first real-time data includes first critical dimension (CD) data, first sidewall angle (SWA) data, first material data, first layer data, first optical data, or first thickness data, or any combination of two or more thereof; etching the substrate using a first gate-etch procedure and the patterned masking layer, the first gate-etch procedure being determined in real-time using the first real-time data; measuring one or more evaluation features on an etched substrate using a second IM procedure, the second IM procedure creating second IM procedure data comprising second real-time data for at least one evaluation feature, wherein the second real-time data includes second CD data, second SWA data, second material data, second layer data, second optical data, or second thickness data, or any combination of two or more thereof; determining first feedback data in real-time using the first real-time data, the second real-time data, or product requirement data, or any combination of two or more thereof; updating the first gate-etch procedure using the first feedback data when the first feedback data is less than or equal to a first limit; and post-processing the etched substrate and storing the data associated with the substrate, when the first feedback data is greater than the first limit.