Patent ID: 6833736
Filing Date: 2004-12-21
Classification: H03K

Abstract:
A pulse generator circuit, comprising:a first logic element having one input for receiving an input clock signal; a first delay element for delaying the input clock signal by a first delay time, the first delay element having one end for receiving the input clock signal and another end coupled to another input of the first logic element; a second logic element having one input for receiving a signal output from the first logic element, the one input of the second logic element coupled to an output of the first logic element, wherein a signal output from the second logic element is held at a fixed level in response to a value of an enable signal to the first delay element; and a second delay element for delaying the signal output from the first logic element by a second delay time, the second delay element coupled at one end to the output of the first logic element and coupled at another end to another input of the second logic element.