Patent ID: 7404129
Filing Date: 2008-07-22
Classification: G01R

Abstract:
1. A circuit comprising: A. test access port having: B. a wrapper serial port having a capture lead, an update lead, a transfer lead, a shift lead, a select lead, a clock lead, a WSI lead, and a WSO lead, the WSI lead being coupled to the TDI input of the data register circuitry, and the WSO lead being coupled to the TDO output of the data register circuitry; C. second gating circuitry having inputs connected to the capture lead, the update lead, the transfer lead, the shift lead, the data register control bus output, and the outputs of the instruction register, and having a first gated wrapper serial port bus output; D. third gating circuitry having inputs connected to the capture lead, the update lead, the transfer lead, the shift lead, the clock lead, and the select lead, and having a second gated wrapper serial port bus output; and E. multiplexer circuitry having a control input connected to the control outputs of the instruction register, a first bus input connected to the data register control bus output and the first gated wrapper serial port bus, a second bus input connected to the second gated wrapper serial port bus, and a bus output connected to the first inputs of the first gating circuitry.