Patent ID: 6798248
Filing Date: 2004-09-28
Classification: H02M,H03K

Abstract:
An apparatus, comprising:a first NAND gate having two input lines and an output line; a first delay path coupled between the output line of the first NAND gate and one of the input lines of the first NAND gate; a second NAND gate having two input lines and an output line; and a second delay path coupled between the output line of the second NAND gate and one of the input lines of the second NAND gate, wherein (i) a first node associated with the first delay path is directly coupled to the other input line of the second NAND gate and a second node associated with the second delay path is directly coupled to the other input line of the first NAND gate and (ii) the first delay path further includes a delay portion between the output of the first NAND gate and the first node and the second delay path includes a delay portion between the output of the second NAND gate and the second node.