Patent ID: 6262910
Filing Date: 2001-07-17
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of bit lines disposed on a substrate;a plurality of word lines disposed on the substrate;a plurality of plate lines disposed on the substrate;a memory cell array including a plurality of memory cells arranged in a matrix having a plurality of columns and rows; each of the memory cells including at least one MOS transistor and at least one memory capacitor; the memory capacitor including a first capacitor electrode, a second capacitor electrode and a ferroelectric film; the MOS transistor including a gate, a first transistor electrode and a second transistor electrode; the gate of each MOS transistor in a same column being connected to a same word line; each of the MOS transistors in a same row being connected to a same bit line at the first transistor electrode; the second transistor electrode being connected to the memory capacitor at the first capacitor electrode; the plate line being connected to the second capacitor electrode so that a plurality of memory capacitors are selected in the plate line in the column direction or in the row direction;a gate voltage supply section for supplying, at a time of power on, a predetermined voltage to the gates of the MOS transistors connected to the word line to activate the MOS transistors and to connect the bit line and the first capacitor electrode so that the bit line and the first capacitor electrode have the same potential via the MOS transistor; anda potential control section which makes the potential of the bit line and the plate line the same so that the first capacitor electrode and the second capacitor electrode have the same potential.