Patent ID: 6362059
Filing Date: 2002-03-26
Classification: H01L,Y10S

Abstract:
A process for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed thereon and a N-channel region formed on the predetermined MOSFET region thereof using indium, the process comprising:(1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed thereon to form a P-well region and thereafter forming a 1st N-channel region made of components other than indium on said P-well region; (2) 2nd step of removing said 1st resist mask and thereafter forming a 1st gate insulation film on the surface of said substrate; (3) 3rd step of forming a 2nd resist mask on said predetermined region except said 1st N-channel region after forming said 1st gate insulation film, and removing partially said 1st gate insulation film; (4) 4th step of forming a P-well region inside the 1st gate insulation film partially removed region and thereafter forming a 2nd N-channel region containing indium on this P-well region; and (5) 5th step of removing said 2nd resist mask and thereafter forming a 2nd gate insulation film on the surface of said 2nd N-channel region.