Patent ID: 9091273
Filing Date: 2015-07-28
Classification: H02P,H03K

Abstract:
1. A controlling circuit for outputting a square wave signal to control a fan rotating speed, comprising: a time-delaying adjustment circuit, comprising a first circuit branch and a second circuit branch in parallel, the first circuit branch comprising a first resistor, the second circuit branch comprising a second resistor, and the time-delaying circuit being grounded through a capacitor; and an outputting unit, for continuously outputting the square wave signal to control the fan rotating speed, an output end of the outputting unit connected to a control end thereof and the capacitor both through the time-delaying adjustment circuit, and the time-delaying adjustment circuit and the grounded capacitor forming a resistor-capacitor time-delaying circuit for the outputting unit, wherein the second circuit branch is unilaterally conducting on and has a first state and a second state, and the first state being a conducting on state and the second state being an open state or the first state being an open state and the second state being a conducting on state; when the output end outputs a high level, the second circuit branch is at the first state and the capacitor is charged through a time delayed by the resistance-capacitance time-delaying circuit, so that a level of the control end increases gradually to the high level to make the output end change to output a low level; when the output end outputs the low level, the second circuit branch is at the second state and the capacitor is discharged through a time delayed by the resistance-capacitance delaying circuit so that the level of the control end decreases gradually to the low level to make the output end change to output the high level; an equivalent resistance of the first and second circuit branches in parallel when the output end outputs the high level is different from an equivalent resistance of the first and second circuit branches in parallel when the output end outputs the low level, leading to a time constant of the resistance-capacitance time-delaying circuit when the output end outputs the high level is different from a time constant of the resistance-capacitance time-delaying circuit when the output end outputs the low level, so that the square signal output by the output end has a duty-ratio being other than 50%.