Patent ID: 7872507
Filing Date: 2011-01-18
Classification: H03K,H03L

Abstract:
1. A delay lock loop, comprising: a delay line comprising a plurality of delay stages each of which consists of a single inverting delay device, one of the delay stages receiving a reference clock signal applied to an input of the delay line, one of the delay stages being selected by a delay control signal, the delay line coupling a first output signal from an input of the selected delay stage and coupling a second output signal from an output of the selected delay stage; a phase inverter having a first input receiving one of the first and second output signals from the delay line and a second input receiving the other of the first and second output signals from the delay line, the phase inverter being operable to couple a signal applied to the first input to a first output without inverting the signal and being operable to couple a signal applied to the second input to a second output while inverting the signal; a phase mixer having first and second inputs coupled to the respective first and second outputs of the phase inverter, the phase mixer to generate a clock output signal having a timing that is interpolated between the timing of the signal applied to the first input and the timing of the signal applied to the second input; and a phase detector having a first input coupled to receive the reference clock signal and a second input coupled to receive the output clock signal, the phase detector generating an output signal corresponding to the difference in timing between the reference clock signal and output clock signal, the output signal from the phase detector being used to generate the delay control signal.