Patent ID: 6205570
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A method for designing an LSI circuit pattern for pattern-designing a plurality of gates and a wiring pattern which connects the plurality of gates on an LSI chip, the method comprising:a first step of estimating a chip area of the LSI chip and a number of the plurality of gates required for achieving a desired function;a second step of estimating an interconnect length of each of the plurality of gates;a third step of designing a wiring pattern associated with the each of the plurality of gates based on a prescribed design rule sequentially from a gate having the shortest interconnect length, and calculating a gate delay time for the design wiring pattern;a fourth step of repeating at least one of the second and third steps after altering the design rule in the case where the calculated gate delay time exceeds a prescribed target value, while calculating a total of areas occupied by the designed wiring patterns in the case where the calculated gate delay time is at or below the prescribed target value; anda fifth step of sequentially performing the third and fourth steps for a gate having a next shortest interconnect length in the case where the calculated total of areas occupied by the designed wiring patterns does not exceed the chip area estimated in the first step, while in the case where the calculated total of areas occupied by the designed wiring patterns exceeds the chip area estimated in the first step, adding one new metal layer and sequentially performing the third and fourth steps for the gate having a next shortest interconnect length on the added metal layer.