Patent ID: 7211494
Filing Date: 2007-05-01
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor structure, the method comprising: forming a first conductive layer of an interconnect stack; depositing a dielectric material layer overlying said first conductive layer; depositing a layer of spin-on-glass overlying said dielectric material layer; removing a portion of said layer of spin-on-glass to form a first insulating layer having a first substantially planar surface; forming a thin film resistor overlying said first insulating layer; depositing a second insulating layer overlying said first insulating layer and said thin film resistor; removing a portion of said second insulating layer to form a second substantially planar surface of said second insulating layer; anisotropically etching said second insulating layer to form a first via to said first conductive layer; depositing a fill material comprising tungsten within said first via to form a conductive plug that is electrically coupled to said first conductive layer; wet etching said second insulating layer to form a second via to said thin film resistor; and depositing a second conductive layer overlying said second insulating layer and within said second via so that said second conductive layer is electrically coupled to said thin film resistor; wherein said second conductive layer is electrically coupled to said first conductive layer through said conductive plug.