Patent ID: 6395645
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A method for anisotropic wet etching, comprising the following steps:preparing a semiconductor substrate; preparing an etching-resistant layer on said semiconductor substrate; forming a pattern of intersecting lines to form a series of corners in said etch-resistant layer wherein said pattern comprises a series of masked and maskless areas wherein at least two sets of the masked lines intersect to surround and define a maskless area in a grid pattern at said corners, whereby the etching rate at the corner area of the substrate is moderated and said etching rate is relatively decided by the width of the masked lines; etching said etch-resistant and semiconductor substrate layers in an etchant, and wherein the widths of the masked areas vary in a sequential manner in which the widths of a masked area in a first zone is 2 &mgr;m, in a second zone is 3 &mgr;m and in a third zone is 4 &mgr;m and the width of intervals is 5 &mgr;m.