Patent ID: 6816922
Filing Date: 2004-11-09
Classification: G06F

Abstract:
A digital signal processor coupled with a byte memory and an external memory through a common data bus, comprising:an internal memory stored with at least one word, each of which consists of a plurality of bytes; an external memory controller coupled with the common data bus; a byte direct memory access (DMA) controller coupled with the external memory controller, including: a byte DMA steal request circuit for outputting a write steal request; a data buffer coupled with the internal memory for receiving in format of a word the at least one word stored in the internal memory during an execution of the write steal request; a byte DMA request circuit for outputting a write request into the external memory controller after the data buffer has received the at least one word stored in the internal memory; and a byte DMA waiting circuit for periodically outputting a waiting end signal into the external memory controller at the end of a programmed period; and a steal request priority scheduler for receiving the write steal request and making a schedule for the execution of the write steal request, wherein: the external memory controller makes a schedule for an execution of the write request, and during the execution of the write request, the external memory controller in response to the waiting end signal transfers in format of a byte the at last one word from the data buffer through the common data bus into the byte memory.