Patent ID: 7211863
Filing Date: 2007-05-01
Classification: H01L

Abstract:
1. A family of transistor devices formed in a semiconductor substrate, the substrate being doped with P-type impurity and not comprising an epitaxial layer, the family of transistor devices comprising at least a PNP bipolar transistor and a CMOS pair, the substrate comprising an isolation structure for electrically isolating transistor devices enclosed within the isolation structure from a portion of the substrate outside the isolation structure, the isolation structure comprising: the PNP bipolar transistor being located in the isolated P region of the substrate and comprising: the CMOS pair comprising a PMOS and an NMOS, the PMOS being located in the second N well and comprising: the NMOS being formed in a second P well, the second P well having a relatively deep central portion and relatively shallow side portions, the relatively shallow side portions underlying the field oxide layer, the relatively deep central portion underlying a second opening in the field oxide layer, the NMOS comprising: