Patent ID: 6998878
Filing Date: 2006-02-14
Classification: G11C

Abstract:
1. A semiconductor integrated circuit, wherein: a buffer circuit from which the true and a complementary signal are output based upon input signals and a decoder circuit for decoding based upon signals output from said buffer circuit are provided; a semiconductor logic circuit in which at least one of said buffer circuit and said decoder circuit is controlled for precharge and evaluation operation according to the polarity of a control signal input to its control terminal and the true and a complementary signal are output based upon input signals input to its input terminals is provided; and said semiconductor logic circuit of said decoder circuit is composed of a set in which an output signal including said true of any of plural said buffer circuits is input to its control terminal and a set to which a complementary output signal is input, and output signals from the other buffer circuits are input to the input terminal of said semiconductor logic circuit of said decoder circuit; and said semiconductor logic circuit comprises: a first load provided between a first power source terminal and a first node and controlled by said control signal and a second load provided between said first power source terminal and a second node and controlled by said control signal; a logic circuit for input provided between said first node and a third node for electrically connecting said first node and said third node according to said input signal; a field effect transistor for reference paths to the source and the drain of which are provided between said second node and said third node and the gate of which is connected to said first node; and an activation circuit provided between said third node and a second power source terminal and controlled by said control signal.