Patent ID: 7492723
Filing Date: 2009-02-17
Classification: G06F

Abstract:
1. A computer implemented method for managing address spaces in shared input/output fabrics, the method comprising: receiving a legacy transaction from a particular device of a plurality of legacy devices in the shared input/output fabric; determining if the legacy transaction is a configuration transaction; in response to the legacy transaction being a configuration transaction, determining if a bus number and a device number associated with the legacy transaction belong to the particular device; in response to the bus number and the device number belonging to another device, passing the legacy transaction on to a next level of the shared input/output fabric; in response to the bus number and the device number belonging to the particular device, determining if the legacy transaction is an access by a unique address plane in a plurality of planes; in response to the legacy transaction being an access from a plane other than the unique address plane, identifying a pointer to an appropriate peripheral component interconnect header to form an identified pointer, wherein the identified pointer is determined using a virtual plane number and function number associated with the legacy transaction, wherein the virtual plane number and function number define the identified pointer in a virtual function number to physical header map; further in response to the legacy transaction being an access from a plane other than the unique address plane, processing the legacy transaction using the identified pointer; in response to the legacy transaction being an access from the unique address plane, providing access to a first eight function numbers; further in response to the legacy transaction being an access from the unique address plane, processing the legacy transaction using the function number from the identification information; in response to the legacy transaction not being a configuration transaction, determining the routing of the legacy transaction, wherein the routing is determined using a virtual plane number and a single or a plurality of base address registers associated with the virtual plane number; further in response to the legacy transaction not being a configuration transaction, processing the legacy transaction using the routing, wherein the legacy transaction is a memory mapped I/O operation or a direct memory access operation; responding to the particular device using a virtual plane number and a requestor identification information from the legacy transaction in a response transaction; routing the response transaction using the virtual plane number and the requestor identification information.