Patent ID: 9093499
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A manufacture comprising an integrated circuit comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on said semiconductor layer, a first portion of a bias circuit electrically connected to first and second via-type interconnections to apply a first bias voltage to said first and second via-type interconnections, a first insulation trench separating said first electronic component from said first and second interconnections in said semiconductor layer, a first ground plane having a first type of doping, placed beneath said buried insulating layer plumb with said first electronic component, and extending beneath said first insulation trench and being in electrical contact with said first interconnection, and a first well having a second type of doping opposite that of said first type, plumb with said first ground plane, and extending beneath said first insulation trench and being in electrical contact with said second interconnection.