Patent ID: 8492814
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; first and second impurity diffusion regions formed on the semiconductor substrate so that a top surface of the semiconductor substrate is defined by a space between the first and second impurity regions; a semiconductor pillar projecting from the top surface of the semiconductor substrate; a third impurity diffusion region formed on a top portion of the semiconductor pillar; a gate insulating film having a first main surface contacting a side surface of the semiconductor pillar and the first and second impurity diffusion regions, the first main surface further contacting a lower portion of a sidewall of the third impurity diffusion region so that an upper portion other than the lower portion of the sidewall of the third impurity diffusion region is not covered with the gate insulating film; a gate electrode formed on a second main surface of a lower portion of the gate insulating film so that an upper portion other than the lower portion of the gate insulating film is not covered with the gate electrode, the second main surface opposing to the first main surface; and a contact plug contacting a top surface and the upper portion of the side wall of the third impurity diffusion region and an end of the gate insulating film.