Patent ID: 6711060
Filing Date: 2004-03-23
Classification: G11C,H01L

Abstract:
A method of driving a non-volatile semiconductor memory arraying a transistor including: first and second diffused layers of a second conductance type in a semiconductor substrate, opposite to each other through a channel region of a first conductance type; and a two-storied gate electrode having a floating gate and a control gate, formed through a gate insulating film on said channel region of the first conductance type, said method comprising the steps of:setting said channel region of the first conductance type and one of said first and second diffused layers at a first voltage level; setting the other of said first and second diffused layers at a second voltage level; setting said control gate at said first or a third voltage level; and injecting into said floating gate a part of charges flowing in said channel region with respect to said transistor flowing a channel current, based on a setting that a voltage difference between said first voltage level and said second voltage level is larger in absolute value than that between said first voltage level and said third voltage level.