Patent ID: 7047385
Filing Date: 2006-05-16
Classification: G06F

Abstract:
1. An external memory IC for use in a networking system having relaxed read latency requirements, said memory IC comprising: a plurality of memory arrays, each memory array including a plurality of embedded memory banks, each memory bank having a data input, a data output, and an address input, and with each memory bank completing a read or write transaction in a cycle time of T a plurality of internal read buses, with each internal read bus coupled in parallel to the data outputs of all the memory banks in a corresponding array; a plurality of internal write buses, with each internal write bus coupled in parallel to the data inputs of all the memory banks in a corresponding array; a plurality of internal address buses, with each internal address bus coupled in parallel to the address inputs all the memory banks in a corresponding array; an address input interface for receiving read address data; an address pipeline, including a plurality of clocked repeaters coupling internal address buses, with the address pipeline coupling the address input interface to the internal address buses; an output data interface outputting read data; a data pipeline, including a plurality of clocked repeaters, with the data pipeline coupling the internal read buses to the output data interface.