Patent ID: 6041387
Filing Date: 2000-03-21
Classification: G06F

Abstract:
A data processing unit comprising:a set of data registers and a set of address registers, each register having a width of n bits, and each set of data and address registers comprising even and odd data and address registers, respectively,first address load and store buffers associated with said even address registers and second address load and store buffers associated with said odd address registers,first data load and store buffers associated with said even data registers and second data load and store buffers associated with said odd data registers,a bus having a plurality of bus lines comprising a width of 4n bits being connected to said first and second store buffers,a data memory unit being connected to said bus, wherein 2n-bit data words and 2n-bit address words can be transferred from or to said memory to or from one of said even, one of said odd data registers, one of said even, and one of said odd address registers in parallel;wherein each register has a plurality of ports and at least one of said bus lines is coupled in parallel to selected registers of said set of data registers;wherein each register comprises a memory cell having an input terminal and an output terminal, a plurality of tri-state buffers with inputs and outputs, said output terminal being connected to the inputs of said plurality of tri-state buffers;wherein each register further comprises a plurality of transfer gates, said input terminal of said memory cell being connected to the outputs of said plurality of transfer gate.