Patent ID: 9064602
Filing Date: 2015-06-23
Classification: G11C

Abstract:
1. A method for implementing memory devices with sub-bank architecture in a computer system comprising: dividing a memory cell array into a plurality of cell sub-blocks located between adjacent bit-line sense amplifier (BLSA) regions and having odd bit lines and even bit lines; alternating the plurality of cell sub-blocks with rows of sense amplifiers disposed in respective adjacent bit-line sense amplifier (BLSA) regions; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines; providing a row decoder receiving a sub-block address including bank/block/row/column addresses sent only for a RD/WR command for enabling more than one word line for a respective sub-block of the plurality of cell sub-blocks to be active at the same time, with a first active word line selecting memory cells connected to even bit lines and a second active word line selecting memory cells connected to odd bit lines.