Patent ID: 6622267
Filing Date: 2003-09-16
Classification: G06F,Y02D

Abstract:
A circuit comprising:a first comparator coupled to a first way of a set in a cache to compare a first cache tag to be stored in the first way to a lookup tag and to generate a first hit signal on a first hit line; a second comparator coupled to a second way of the set to compare a second cache tag to be stored in the second way to the lookup tag and to generate a second hit signal on a second hit line; a third comparator coupled to a third way of the set to compare a third cache tag to be stored in the third way to the lookup tag and to generate a third hit signal on a third hit line; a first pair of pull-down transistors coupled to the first and second hit lines to pull down an output node during a clock cycle if the first and second hit signals both indicate a hit; a second pair of pull-down transistors coupled to the first and third hit lines to pull down the output node during a clock cycle if the first and third hit signals both indicate a hit; a third pair of pull-down transistors coupled to the second and third hit lines to pull down the output node during a clock cycle if the second and third hit signals indicate a hit; and a multiplexer to provide a data during the clock cycle.