Patent ID: 8614474
Filing Date: 2013-12-24
Classification: G02F,H01L

Abstract:
1. A thin film transistor (hereinafter referred to as TFT) memory having a drive TFT and a memory TFT, each having, over an insulating substrate, a gate electrode, a semiconductor layer overlapping with the gate electrode across a common gate insulating film having a capability of charge accumulation interposed therebetween, and a source electrode and a drain electrode, spaced apart from each other, coupled to the semiconductor layer, and each also having a channel region in the semiconductor layer between a position of the semiconductor layer connected to the source electrode and a position of the semiconductor layer connected to the drain electrode, wherein a distance from the position of the semiconductor layer connected to the source electrode to the position of the semiconductor layer connected to the drain electrode is a channel length, and a width between the positions of the semiconductor layer in a direction orthogonal to a direction of the channel length is a channel width, and an area C