Patent ID: 9189424
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. A method of operating an external cache memory comprising: receiving from a first processor having an integrated memory controller and multiple levels of cache memory a clean castout message indicating that a first cache line is not dirty and is no longer being stored by a lowest level cache of the first processor; determining whether the first cache line is stored in the external cache memory; if the first cache line is not stored in the external cache memory, fetching the first cache line into the external cache memory, wherein the external cache memory participates in a cache coherency protocol wherein multiple cache agents can store a shared copy of the first cache line, and only one cache agent can have a forward state associated with its shared copy of the first cache line, and the external cache memory retains the forward state associated with the first cache line as long as the external cache memory stores a shared copy of the first cache line; and selecting a second cache line stored in the external cache for replacement based on a clean castout message history associated with the second cache line.