Patent ID: 8957718
Filing Date: 2015-02-17
Classification: H03K

Abstract:
1. A flip-flop circuit, comprising: a first pMOS transistor connected to a power supply at a source thereof and to a first node at a gate thereof, a first signal based on a data signal being supplied to the first node; a second pMOS transistor connected to the power supply at a source thereof and to a second node at a gate thereof, a second signal based on a clock signal being supplied to the second node; a third pMOS transistor connected to drains of the first and second pMOS transistors at a source thereof and to an intermediate node, at which a master latch and a slave latch are connected to each other, at a drain thereof; a first nMOS transistor connected to the intermediate node and the drain of the third pMOS transistor at a drain thereof and to the first node at a gate thereof; a second nMOS transistor connected to the intermediate node and the drains of the third pMOS transistor and the first nMOS transistor at a drain thereof, to a ground at a source thereof and to a gate of the third pMOS transistor at a gate thereof; a fourth pMOS transistor connected to the gate of the third pMOS transistor and the gate of the second nMOS transistor at a drain thereof and to the second node at a gate thereof; a fifth pMOS transistor connected to the power supply at a source thereof and to the intermediate node at a gate thereof; a sixth pMOS transistor connected to a drain of the fifth pMOS transistor at a source thereof, to a third node at a drain thereof and to the second node at a gate thereof, a third signal of the slave latch being supplied to the third node; a seventh pMOS transistor connected to the power supply at a source thereof and to the third node and the drain of the sixth pMOS transistor at a drain thereof; a third nMOS transistor connected to the third node and the drains of the sixth and seventh pMOS transistors at a drain thereof and to a gate of the seventh pMOS transistor at a gate thereof; a fourth nMOS transistor connected to a source of the third nMOS transistor at a drain thereof, to the ground at a source thereof and to the intermediate node at a gate thereof; a fifth nMOS transistor connected to the source of the third nMOS transistor and the drain of the fourth nMOS transistor at a drain thereof, to the ground at a source thereof and to the second node at a gate thereof; an eighth pMOS transistor connected to the power supply at a source thereof, to the gate of the seventh pMOS transistor and the gate of the third nMOS transistor at a drain thereof and to the second node at a gate thereof; a ninth pMOS transistor connected to the power supply at a source thereof, to the gates of the seventh pMOS transistor and the third nMOS transistor and the drain of the eighth pMOS transistor at a drain thereof and to the third node at a gate thereof; a sixth nMOS transistor connected to the gates of the seventh pMOS transistor and the third nMOS transistor and the drains of the eighth and ninth pMOS transistors at a drain thereof and to the third node at a gate thereof; and a seventh nMOS transistor connected to a source of the sixth nMOS transistor at a drain thereof, to the ground at a source thereof and to the second node at a gate thereof, wherein an output signal is output based on the third signal at the third node, a source of the first nMOS transistor is connected to the source of the sixth nMOS transistor and the drain of the seventh nMOS transistor, a source of the fourth pMOS transistor is connected to the drain of the fifth pMOS transistor and the source of the sixth pMOS transistor, and the drain of the fourth pMOS transistor is connected to the source of the third nMOS transistor and the drains of the fourth and fifth nMOS transistors.