Patent ID: 7356632
Filing Date: 2008-04-08
Classification: G06F,Y02D

Abstract:
1. A data memory controller that supports data bus invert, coupled to a data memory apparatus and a post data processor, the data memory controller comprising: an input data receiver, to receive a memory data from the data memory apparatus, and output a first data selected from the memory data in a way of sampling every sequential even number bit data of the memory data and a second data selected from the memory data in a way of sampling every sequential odd number bit data of the memory data, wherein the input data receiver reduces a frequency of the memory data and increases a bandwidth of the memory data in such a manner that each frequency of the first data and the second data is less than that of the memory data, and bandwidths of the first data and second data are greater than that of the memory data; an invert bit generator, to receive the first data and the second data, and to compare the first data with a previously received second data to obtain a first invert bit, and to compare the second data with a previously received first data to obtain a second invert bit; and a data access apparatus, receiving the first data, the second data, the first invert bit and the second invert bit, and then output the first and second data to the post data processor.