Patent ID: 6130567
Filing Date: 2000-10-10
Classification: H03K

Abstract:
A semiconductor delay circuit comprising:a first invertor circuit having an input node coupled to an input terminal and an output node;a second inverter circuit having an input node coupled to said output node of said first inverter circuit and an output node coupled to an output terminal via a first transfer gate, said second inverter circuit having a first current drive ability;a third inverter circuit having an input node coupled to said output node of said first inverter circuit and an output node coupled to said output terminal via a second transfer gate, said third inverter circuit having a second current drive ability different from that of said first current drive ability;a fourth inverter circuit interposed between said second inverter circuit and said first transfer gate;a fifth inverter circuit interposed between said third inverter circuit and said second transfer gate, each of said fourth and fifth inverter circuits having the same current drive ability;a sixth inverter circuit having an input node coupled to said input terminal and an output node;a seventh inverter circuit having an input node coupled to said output node of said sixth inverter circuit and an output node coupled to said output terminal via a third transfer gate, said seventh inverter circuit having a third current drive ability;an eighth inverter circuit having an input node coupled to said output node of said sixth inverter circuit and an output node coupled to said output terminal via a fourth transfer gate, said eighth inverter circuit having a fourth current drive ability different from that of said third current drive ability; anda ninth inverter circuit having an input node coupled to said output node of said third inverter circuit and an output node, said output node of said ninth inverter circuit floating.