Patent ID: 6629230
Filing Date: 2003-09-30
Classification: G06F,Y02D

Abstract:
A host interface circuit performing data transmission/reception between an external host controller and a device connected to the external host controller in such a manner that each address and data to be transmitted/received is accompanied with a chip selection signal indicating that the external host controller makes access to the device connected to the external host controller, and a read enable signal or a write enable signal, wherein:said external host controller generates, as external addresses to be supplied to the device connected to the external host controller, first addresses corresponding to the respective internal addresses in an internal storage space of the device connected to the external host controller, and a specific second address corresponding to internal addresses of a series of areas in the internal storage space; said host interface circuit includes: a first address conversion circuit for converting the first addresses into the internal addresses in the internal storage space; and a second address conversion circuit for converting the specific second address into the internal addresses in the internal storage space; and the specific second address is used when the external host controller makes continuous access to the serial areas in the internal storage space of the device connected to the external host controller.