Patent ID: 6714957
Filing Date: 2004-03-30
Classification: G06F

Abstract:
For use in a pipelined floating point unit comprising at least one of an addition pipe and a multiplication pipe, a denormal result handling circuit comprising:a denormal condition detection circuit associated with at least one of said addition pipe and said multiplication pipe capable of examining a first operand and a second operand loaded into said at least one of said addition pipe and said multiplication pipe and detecting a potential denormal condition, said potential denormal condition indicating that a calculated result generated from said first and second operands may be a denormal result, wherein said denormal condition detection circuit, in response to said detection of said potential denormal condition, prevents an additional operation from being loaded into said at least one of said addition pipe and said multiplication pipe; and a complex rounding unit capable of receiving said calculated result from said at least one of said addition pipe and said multiplication pipe and, in response to said detection of said potential denormal condition, rounding said calculated result.