Patent ID: 6088046
Filing Date: 2000-07-11
Classification: G06F,G09G

Abstract:
For use in connection with an information processing system including at least one host CPU and a host memory, said host CPU being selectively operable at a first rate, said first rate being related to a first clock signal, said host memory being addressable in a first addressing format, and a subsystem for processing a predetermined aspect of said information processing system, said subsystem including a subsystem processing device and a subsystem memory section addressable in a second addressing format, said subsystem processing device being selectively operable at a second rate, said second rate being related to a second clock signal, said second rate being faster than said first rate, a method for implementing a data storage and retrieval process for managing subsystem requests in said second format to read and write information between said processing system and said subsystem, said method comprising:generating a data transfer request from a requesting unit of the subsystem for a data transfer transaction between the subsystem and the host memory, said request being presented as a requested address in said second addressing format;determining an equivalent host memory target address in said first addressing format equivalent to said request in said second format, said determining being accomplished at said second rate;accessing said the host memory target address; andtransferring data between said host memory target address and said subsystem in response to said data transfer request, said transferring being accomplished at said first rate.