Patent ID: 7797693
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. A mobile electronic device having a plurality of processors, each processor having its own address space, the mobile electronic device comprising: a plurality of NAND memory units communicatively coupled to and associated with the plurality of processors in one-to-one correspondence; an update agent executable on one of the plurality of processors, the update agent capable of updating code in the NAND memory unit corresponding to the one of the plurality of processors; an update package resident in the NAND memory unit corresponding to the one of the plurality of processors; the update agent employing the update package to update the code; a plurality of random access memory (RAM) units communicatively coupled to and associated with the plurality of processors in one-to-one correspondence; and the one of the plurality of processors capable of transferring the update agent from the corresponding NAND memory unit into the corresponding RAM memory unit and of executing the update agent in the corresponding RAM memory unit to update the code to the mobile electronic device using less than full page NAND write blocks in order to be consistent with NOR memory unit updates to mobile electronic devices and to accommodate non-direct access to the plurality of NAND memory units and to accommodate bad blocks within the plurality of NAND memory units.