Patent ID: 7853727
Filing Date: 2010-12-14
Classification: G11C

Abstract:
1. A system comprising: a signal processor for outputting an initial serial input signal including a search device type and an initial device identifier, and receiving a last serial output signal; and a serial interconnection configuration of first to N-th semiconductor memory devices of mixed types, N being an integer greater than one, each of the semiconductor memory devices having a semiconductor memory associated therewith, and a device type, the device type being related to the semiconductor memory; each i-th semiconductor memory device of the first to N-th semiconductor memory devices, where i is one to N, having the serial input connection of the i-th semiconductor memory device being coupled to the signal processor or the serial output connection of an (i−1)-th semiconductor memory device, the serial output connection of the i-th semiconductor memory device being coupled to the serial input connection of an (i+1)-th semiconductor memory device or the signal processor, the initial serial input signal provided to the serial input connection of the first semiconductor memory device of the first to N-th semiconductor memory devices being propagated through the first to N-th semiconductor memory devices with or without the initial device identifier or the propagated device identifier being altered as each i-th semiconductor memory device is configured to determine the device type of the i-th semiconductor memory device by comparing the device type of the i-th semiconductor memory device to the search device type, each i-th semiconductor memory device modifying the initial device identifier to provide the propagated device identifier or the propagated device identifier to provide the last device identifier, in response to the comparison to provide the serial output signal or the last serial output signal, the last serial output signal including the last device identifier.