Patent ID: 8093664
Filing Date: 2012-01-10
Classification: H01L

Abstract:
1. A non-volatile semiconductor memory device, comprising: a memory cell array including memory cell transistors arranged therein, the memory cell transistors being provided with a charge accumulation layer formed on a semiconductor substrate via a gate insulating film; and a peripheral circuit configured to drive the memory cell transistors, the peripheral circuit including at least a first transistor, the first transistor further comprising: a semiconductor layer of a second conductivity type; a first gate electrode formed on a surface of the semiconductor layer via the gate insulating film; a first channel region of a first conductivity type having a first impurity concentration and formed on a surface of the semiconductor layer directly below and in the vicinity of the first gate electrode, the first conductivity type being of the opposite conduction type to the second conductivity type; first source-drain regions of the first conductivity type having a second impurity concentration which is greater than the first impurity concentration and formed on the surface of the semiconductor layer; contact regions of the first conductivity type having a fourth impurity concentration which is greater than the second impurity concentration and formed on at least a portion of a surface of the first source-drain regions; and overlapping regions of the first conductivity type having a third impurity concentration which is greater than the second impurity concentration and formed on the surface of the semiconductor layer directly below and in the vicinity of the gate electrode where the channel region and the source-drain regions overlap, the contact regions each being formed in a position more distant from the first gate electrode than respective one of the overlapping regions, with the respective one of the first source-drain regions interposed therebetween.