Patent ID: 8742965
Filing Date: 2014-06-03
Classification: H03M

Abstract:
1. A N+M bit Digital to Analog Converter (DAC) comprising: an N bit Digital to Analog Converter (DAC) with a true output and a complementary output; wherein the true output and complementary output of the N bit digital to analog converter are offset by substantially a half least significant bit; a first weighting processor producing a true output of the N+M bit Digital to Analog Converter, wherein the true output is a weighted combination of the true and complementary outputs of the N bit Digital to Analog Converter; a second weighting processor producing a complementary output of the N+M bit Digital to Analog Converter, wherein the complementary output of the N+M bit Digital to Analog Converter is a weighted combination of the true and complementary outputs of the N bit Digital to Analog Converter; wherein the first and second weighting processors adjust at each major carry transition of M most significant input bits such that the true output and complementary output are monotonic; and wherein N and M are positive integers.