Patent ID: 9191003
Filing Date: 2015-11-17
Classification: G11C,H03K

Abstract:
1. An integrated circuit of a memory, comprising: a first data driving circuit, coupled to a first node, for outputting a first data voltage to the first node, wherein the voltage level of the first node is a first voltage level or a second voltage level; a transmitting transistor coupled between the first node and a second node, wherein a voltage level of the second node is a third voltage level or a fourth voltage level; and a sensing circuit controlled by the voltage level of the second node and coupled to the second node; wherein when the transmitting transistor receives a bias voltage and the voltage level of the first node is the first voltage level, the transmitting transistor makes the voltage level of the second node to be set as the third voltage level, the third voltage level and the first voltage level are corresponding to a same logic state; when the transmitting transistor receives the bias voltage and the voltage level of the first node is the second voltage level, the voltage level of the second node is independent of the voltage level of the first node, and the transmitting transistor blocks transfer of the first data voltage from the first data driving circuit to the second node; when the voltage level of the second node is the fourth voltage level, the sensing circuit generates a current path so that the voltage level of the first node is set to be the first voltage level, and when the voltage level of the second node is the third voltage level, the sensing circuit interrupts the current path.