Patent ID: 9049004
Filing Date: 2015-06-02
Classification: G09C,H04L

Abstract:
1. A low-power plaintext encryption apparatus comprising: a plaintext input chip configured to receive from a user a plaintext P which is a concatenation of a plurality of sub-plaintexts each having a same length of bits; a mask value generation chip configured to generate a mask value M having a bit length identical to that of input round function values generated from the plurality of sub-plaintexts received from the plaintext input chip; a mask value application chip configured to generate first masking round function values by applying the mask value M to each of the input round function values; a round key application chip configured to generate second masking round function values by applying round key values to the first round function values; a mask operation chip configured to generate third masking round function values by performing a mask addition operation on the second masking round function values; a shift operation chip configured to generate fourth masking round function values by performing a circular shift operation on the third masking round function values; a shift operation correction chip configured to generate output round function values by performing an operation using the mask value M on the fourth masking round function values, and a plaintext output chip configured to output an encrypted plaintext P′ having a same length of bits by concatenating the output round function values, wherein the input round function values are an input round function value X wherein the mask value application chip: generates a first masking round function value X generates a first masking round function value X generates a first masking round function value X generates a first masking round function value X wherein ⊕ is an exclusive OR (XOR) operator, and wherein the round key values are a round key value RK