Patent ID: 7383426
Filing Date: 2008-06-03
Classification: G06F

Abstract:
1. A pipeline system for processing tasks, comprising: (a) a host that controls the processing of tasks and supplies configuration parameters used for processing the tasks; (b) a plurality of configuration register sets in which configuration parameters are selectively loaded by the host; (c) a plurality of stages that employ configuration parameters from the configuration register sets to execute the tasks; (d) a plurality of control signal sources that are separate and distinct from the host, and which track timing events in the pipeline system to produce a plurality of control signals that dynamically control access to the plurality of configuration register sets by both the host and the plurality of stages, so that the configuration registers are setup by the host with the configuration parameters in order to reduce occurrences of setup delays between tasks, and to eliminate a pipeline delay or to reduce a pipeline delay or to both eliminate and reduce a pipeline delay between tasks such that the pipeline delay is substantially incurred prior to processing the initial task in each stage after the initial stage, wherein the pipeline delay is idle time caused by a stage waiting for the output of a different stage to be completed, where such delays would delay processing of the tasks, and so that the processing of the tasks overlap within the plurality of stages, said reduction in setup delay and pipeline delay and said overlapping of the processing of the tasks together resulting in a decrease in a time required to process the tasks; and (e) at least one control signal source selected from the group of control signal sources consisting of: