Patent ID: 9024450
Filing Date: 2015-05-05
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a semiconductor substrate; a plurality of metal interconnects disposed over said substrate in a first plurality of parallel route tracks and a second plurality of route tracks, in which said second plurality of route tracks are alternated with said first plurality of route tracks; a first lead in an instance of said first plurality of parallel route tracks; a second lead in an instance of said second plurality of parallel route tracks, such that said instance of said first plurality of parallel route tracks containing said first lead pattern is immediately adjacent to said instance of said second plurality of parallel route tracks containing said second lead pattern; a stretch crossconnect disposed in exactly one of a dielectric layer disposed above said plurality of metal interconnects and a dielectric layer disposed below said plurality of metal interconnects, said stretch crossconnect being electrically connected said first lead and said second lead, such that said stretch crossconnect is free of electrically connection to other interconnect elements other than said first lead and said second lead, and said stretch crossconnect is formed concurrently with other vertical interconnect elements in said integrated circuit, in which said stretch crossconnect is a contact disposed in a pre-metal dielectric (PMD) layer under said plurality of metal interconnects.