Patent ID: 8987102
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A method of forming a metal silicide region in an integrated circuit, comprising: depositing a mask layer atop a substrate having a first region and a second region; patterning the mask layer to expose the first region; depositing a source element-containing layer atop a first surface of the first region and annealing the source element-containing layer to form a silicide-resistive region in the first region of the substrate; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region and to form either no metal silicide in the first region or a second metal silicide region in the first region that has a thickness less than that of the first metal silicide region.