Patent ID: 7257742
Filing Date: 2007-08-14
Classification: G06F

Abstract:
1. A disk reproducing apparatus for controlling the entire operation by cooperation between two microcomputers, comprising: a first microcomputer for performing control of an operation for reproducing information recorded on a disk which is a disk-shaped record medium, and a second microcomputer for performing control of an operation for outputting information reproduced from the disk, wherein four signal lines for respectively transmitting a control signal BUSY/-RDY which is sent from said first microcomputer to said second microcomputer and indicates whether or not said first microcomputer is in a communicable state, a control signal BUSCLR which is sent from said second microcomputer to said first microcomputer and instructs said first microcomputer on initialization, a clock signal sent from said second microcomputer to said first microcomputer for synchronization in the case that said first microcomputer communicates with said second microcomputer, and a data signal for conducting two-way clock synchronous serial communication between said first microcomputer and said second microcomputer are provided between said first microcomputer and said second microcomputer, and a sending side sends sending target data formed by adding a byte for error detection in which each bit is exclusive OR of a corresponding bit of a byte which is a sending target after a byte which is the original sending target, and when a byte corresponding to the byte for error detection is received, a receiving side performs error detection of received data using said byte, and in the case that said second microcomputer is in the sending side and said first microcomputer is in the receiving side, when the control signal BUSY/-RDY from said first microcomputer is in a state indicating communicability after primary time, which is from time when said second microcomputer sends the byte for error detection until time when the control signal BUSY/-RDY from said first microcomputer is shifted to a state indicating communicability after bytes other than the byte for error detection are sent elapses, it is decided that error detection is not performed by said first microcomputer and a communication error due to byte displacement occurs and the control signal BUSCLR to said first microcomputer is shifted to a state of instructing initialization, and thereafter a communication state is initialized by said first microcomputer to be shifted to a receivable state, and then the control signal BUSY/-RDY to said second microcomputer is shifted to the state indicating communicability, and thereafter the control signal BUSCLR is shifted by said second microcomputer to a state in which initialization is not instructed, and then the sending target data sent immediately before is immediately resent from the first byte, and in the case that said second microcomputer is in the sending side and said first microcomputer is in the receiving side when the control signal BUSY/-RDY from said first microcomputer is in a state in which communicability is not indicated after primary time, which is from time when said second microcomputer sends bytes other than the byte for error detection until time when the control signal BUSY/-RDY from said first microcomputer is shifted to a state indicating communicability after bytes other than the byte for error detection are sent elapses, it is decided that error detection is not performed by said first microcomputer through the use of the bytes other than the byte for error detection and a communication error due to byte displacement occurs, and the control signal BUSCLR to said first microcomputer is shifted to a state of instructing initialization, and thereafter a communication state is initialized by said first microcomputer to be shifted to a receivable state, and then the control signal BUSY/-RDY to said second microcomputer is shifted to the state indicating communicability, and thereafter the control signal BUSCLR is shifted by said second microcomputer to a state in which initialization is not instructed, and then the sending target data sent immediately before is immediately resent from the first byte.