Patent ID: 7244985
Filing Date: 2007-07-17
Classification: G11C,H01L

Abstract:
1. A non-volatile memory array, comprising: a plurality of memory units arranged in a row/column array, and each of the memory units comprising: a plurality of source lines disposed in parallel in a column direction, connecting to the second conductive type source regions of the memory units of the same column; a plurality of bit lines disposed in parallel in a row direction, connecting to the second conductive type drain regions of the memory units of the same row; a plurality of word lines disposed in parallel in the column direction, connecting to the select gates of the memory units of the same column; a plurality of control lines disposed in parallel in the column direction, connecting to the control gates of the memory units of the same column, wherein the control lines are grouped with every n control lines in one group (n is a positive integer which is greater or equal to 2), and are electrically connected to each other.