Patent ID: 6930950
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns, a plurality of word lines respectively arranged correspondingly to a plurality of rows of said plurality of memory cells, and a plurality of pairs of bit lines respectively arranged correspondingly to a plurality of columns of said plurality of memory cells; a plurality of sense amplifier bands provided correspondingly to each of said plurality of memory blocks to sense and amplify data read from said memory cells; a plurality of pairs of read data lines extended commonly from said plurality of sense amplifier bands; and a logic circuit having input terminals connected to one pair of read data lines respectively of said plurality of pairs of read data lines, said logic circuit providing a self-precharge signal when an increased potential difference is generated between the pair of read data lines connected respectively to the input terminals.