Patent ID: 7203632
Filing Date: 2007-04-10
Classification: G06F

Abstract:
1. A method for simulating operations of a circuit design that includes high-level components and one or more HDL components, comprising: simulating the high-level components of the design in a high-level modeling system (HLMS); co-simulating the one or more HDL components of the design with an HDL simulator; converting a data value from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator; converting a logic vector from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator; maintaining an HLMS current time and an HDL simulator current time, wherein each unit of HLMS time corresponds to K units of HDL simulator time, and K satisfies the inequality K*ΔQ>N*Δt scheduling an event for the HDL simulator as a function of ΔQ and Δt