Patent ID: 9053678
Filing Date: 2015-06-09
Classification: G09G,G11C

Abstract:
1. A shift register unit circuit, comprising: input terminals including a start signal input terminal, a first clock signal input terminal and a second clock signal input terminal; a pre-charging circuit for outputting a turn-on level in response to an enable level of a start signal and of a first clock signal, and keeping the turn-on level being output during one clock period of the first clock signal; a first level pulling-down circuit for pulling down the turn-on level output from the pre-charging circuit and outputting a low level, after the turn-on level is input; and for outputting the low level in response to the enable level of the first clock signal and a disable level of a second clock signal, and outputting a high level in response to a disable level of the first clock signal and an enable level of the second clock signal, after the turn-on level is turned off; a second level pulling-down circuit, which is coupled to an output terminal of the first level pulling-down circuit, for pulling down a level at an output terminal of the second level pulling-down circuit and outputting the low level in response to the high level output from the first pulling-down circuit; for pulling down the level at the output terminal of the second level pulling-down circuit and outputting the low level in response to the enable level of the first clock signal; and for outputting the high level in response to the low level output from the first level pulling-down circuit and the disable level of the first clock signal; and a scan signal output terminal, which is coupled to the output terminal of the second level pulling-down circuit, for outputting a scan signal.