Patent ID: 9032112
Filing Date: 2015-05-12
Classification: G06F

Abstract:
1. A system comprising: a processor; a memory; and a direct memory access (DMA) controller configured to: receive an allowable number of data transmissions from the processor, the allowable number of data transmissions indicating a number of data transmissions that the DMA controller is configured to approve or disapprove, the allowed number of data transmissions being greater than an amount of data to be transferred to and from a buffer unit; receive a request to transfer data, the request received after the allowable number is received from the processor; determine, independent of the processor, that a data transfer number associated with the request to transfer data is less than, greater than, or equal to the allowable number; and responsive to the data transfer number being less than or equal to the allowable number, approve, without interrupting the processor, the request to transfer data; or responsive to the data transfer number being greater than the allowable number, disapprove, without interrupting the processor, the request to transfer data.