Patent ID: 7309901
Filing Date: 2007-12-18
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface; (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region; (d) a first shallow contact region in direct physical contact with the first S/D extension region; and (e) a first deep contact region in direct physical contact with the first S/D region and the first shallow contact region, wherein the first shallow contact region is physically isolated from the semiconductor layer by the first S/D region and the first S/D extension region, and wherein the first shallow contact region is thinner than the first deep contact region in the reference direction; and (f) a dielectric cap layer on top of and in direct physical contact with the first deep contact region,