Patent ID: 7585712
Filing Date: 2009-09-08
Classification: C25D,H01L

Abstract:
1. A method of fabricating a thin film transistor array substrate, comprising: providing a substrate; forming a first patterned electroplating seed layer on the substrate; forming an insulating material layer completely over the substrate so as to cover the first patterned electroplating seed layer; forming a photoresist layer on the insulating material layer; performing a backside exposure process to the photoresist layer on a backside surface of the substrate by using the first patterned electroplating seed layer as a first mask; developing the photoresist layer to form an opening in the photoresist layer and above the first patterned electroplating seed layer so that the opening exposes the insulating material layer above the first patterned electroplating seed layer; etching the insulating material layer by using the photoresist layer as a second mask so that the insulating material layer exposes the first patterned electroplating seed layer; forming first patterned metal layer over the substrate by an electroplating method; removing the photoresist layer; forming a gate insulating layer over the substrate, the gate insulating layer covering the first patterned metal layer; forming a semiconductive layer on the gate insulating layer over the first patterned metal layer; and forming a second patterned metal layer over the semiconductive layer, wherein the first patterned metal layer, the second patterned metal layer and the semiconductive layer constitute a plurality of thin film transistors on the substrate, a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are coupled to the thin film transistors.