Patent ID: 7268590
Filing Date: 2007-09-11
Classification: H03K

Abstract:
1. Apparatus for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL) circuit comprising: a static portion including a cross-coupled NAND logic and inverter logic; a dynamic node provides a first input to said NAND logic; a sleep signal provides a second input to said NAND logic; an output of the NAND logic providing an input to said inverter logic, said inverter logic inverting the NAND output and provides a complementary output; said NAND logic including a series connected first sleep transistor receiving said sleep signal; said first sleep transistor being turned OFF during the sleep mode to disable said NAND logic; and a second sleep transistor connected between a voltage supply rail and said NAND output; said second sleep transistor receiving said sleep signal and being turned ON during the sleep mode for forcing said NAND output high and said complementary output low.