Patent ID: 8930867
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A computer-implemented method of assigning computational loads for placement regions of an integrated circuit design to a plurality of host processors in a computer system, comprising: receiving a list of the placement regions and placeable objects associated with the placement regions by executing first instructions in the computer system; calculating an ideal number of placeable objects per processor by executing second instructions in the computer system; successively assigning one or more of the placement regions to a given host processor by executing third instructions in the computer system until either (i) an amortized number of placeable objects in a combination of placement regions assigned to the given host processor exceeds a first limit above the ideal number of objects per processor, or (ii) a next placement region assignment to the given host processor would cause the amortized number of placeable objects, in a combination of placement regions already assigned to the given host processor and the next placement region, to exceed a second limit above the ideal number of objects per processor wherein the second limit is greater than the first limit; and iteratively repeating said successively assigning one or more of the placement regions to each next host processor in the computer system.