Patent ID: 6479389
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of fabricating an integrated circuit on a substrate to form alloyed copper interconnect lines and vias comprising the following:providing a substrate or module with integrated circuits therein; providing an interconnect wiring layer, or device contact regions to P-N junctions on the substrate; providing a first layer of insulator over the interconnect wiring layer, or device contact regions to P-N junctions; providing patterned and etched via holes and trenches in the first layer of insulator; depositing a via hole and trench barrier liner material, selected from the group consisting of TaN, TiN, WN, which is a diffusion barrier; depositing by chemical vapor deposition or electro-chemical deposition of a thick layer of pure copper, over the barrier liner material planarizing the surface; depositing an alloyed planar copper layer, selected from the group consisting of Al, Ti, Zn, copper alloying metals by physical vapor deposition, sputtering from an alloyed target; annealing by a low temperature annealing step between 250 to 450Â° C., to enhance copper alloy formation of all metal layers above; polishing the excess conducting metal back by chemical mechanical polishing and repeating the above process steps to make multilevel conducting layers, which are corrosion/oxidation and electromigration resistant, by this integrated method.