Patent ID: 7996657
Filing Date: 2011-08-09
Classification: G06F

Abstract:
1. A reconfigurable computing circuit comprising: a reconfigurable computing block including configuration registers, data registers, and reconfigurable computing units that are respectively connected to the configuration registers, wherein the configuration registers and the data registers are connected in series, and each time a shift instruction is given at a predetermined cycle, information in each of the configuration registers and each of the data registers shifts to next connected register in the series, with input information being stored into a starting register of the series; a first storage unit storing one or more pieces of configuration information arranged in a predetermined order so as to be stored into the configuration registers; a second storage unit storing a plurality of pieces of group information that correspond one-to-one to a plurality of register groups which are sets of continuous registers of a same type obtained by grouping the series in a connection order from a starting register to an ending register of the series, each register group including one or more registers, each piece of group information indicating (i) a type of one or more registers included in a corresponding register group and (ii) a number of the one or more registers in the corresponding register group; a generating unit operable to generate an initial value; and a control unit operable to read, one by one, the plurality of pieces of group information from the second storage unit, judge a register type from a read piece of group information, and when the judged register type is data register, output the initial value, in synchronization with the shift instruction, to the reconfigurable computing block as many times as the number of registers indicated by the read piece of group information, and when the judged register type is configuration register, read as many pieces of configuration information from the first storage unit one by one as the number of registers indicated by the read piece of group information, and output the pieces of configuration information read from the first storage unit to the reconfigurable computing block one by one in synchronization with the shift instruction.