Patent ID: 7058779
Filing Date: 2006-06-06
Classification: G06F

Abstract:
1. A computer system comprising: a central processor; a system reset generator coupled to said central processor for asserting a reset signal; a system controller coupled to said central processor and said system reset generator, wherein said system controller comprises an SDRAM memory controller and a non-volatile memory controller; addressable non-volatile memory coupled to said system controller, said system reset generator and said central processor, wherein said non-volatile memory comprises a sequential boot logic section; a data bus coupled between said system controller and said non-volatile memory; an SDRAM control signal line coupled between said SDRAM memory controller and said non-volatile memory, said SDRAM control signal line for carrying SDRAM control signals; a first control signal line coupled directly between said non-volatile memory controller and said non-volatile memory for transmitting a chip select signal from said non-volatile memory controller in response to said reset signal, wherein said chip select signal is for initiating a first read operation of a first data word at a first address in a first accessed row of said non-volatile memory; and a second control signal line coupled directly between said non-volatile memory controller and said sequential boot logic section for transmitting a read enable signal to said non-volatile memory, wherein said read enable signal is for causing said non-volatile memory to deliver data words sequentially to said data bus beginning with said first data word, and wherein said sequentially delivered data words are for initializing an SDRAM interface of said non-volatile memory for normal operation with said computer system.