Patent ID: 8426298
Filing Date: 2013-04-23
Classification: H01L

Abstract:
1. A method comprising: forming a first gate stack over and vertically overlapping a silicon layer, wherein the silicon layer is over a silicon germanium layer, and wherein the silicon germanium layer is over a silicon substrate; forming a second gate stack over the silicon substrate, wherein no silicon germanium layer extends to directly under the second gate stack; forming first Schottky source/drain extension regions adjacent the first gate stack, wherein the first Schottky source/drain extension regions contact the silicon germanium layer; forming second Schottky source/drain extension regions adjacent the second gate stack, wherein the second Schottky source/drain extension regions contact the silicon substrate; forming first and second gate spacers on sidewalls of the first and the second gate stacks, respectively; implanting the silicon substrate, the silicon germanium layer, and the silicon layer to form first source/drain regions when the first gate spacers are located over the silicon layer; implanting the silicon substrate to form second source/drain regions when the second gate spacers are located over the silicon substrate; after the first and the second source/drain regions are formed, thinning the first and the second gate spacers to form first and the second thin spacers, respectively; and after the step of thinning, forming first and second silicide regions aligned to sidewalls of the first and the second thin spacers, respectively, wherein the first and second silicide regions form the first and the second Schottky source/drain regions, respectively.