Patent ID: 7981729
Filing Date: 2011-07-19
Classification: H01L

Abstract:
1. A fabrication method of a multi-chip stack structure, comprising: providing a leadframe having a die base and a plurality of leads, a first chip and a second chip being disposed to two opposite surfaces of the die base respectively, wherein a bonding area is formed on an inner end of each of the leads; disposing the leadframe on a heating block having a cavity, the leads being supported by the heating block and the second chip being received in the cavity; performing a first wire bonding process so as to form a plurality of first bonding wires electrically connecting the first chip and the leads with a stitch bond of each of the first bonding wires located in the bonding area of each of the leads, and meanwhile disposing at least a bump at one side of the leads connected with the first bonding wires, wherein the bump is formed in the bonding area of each of the leads and is close to the stitch bond of each of the first bonding wires; disposing the leadframe upside-down on the heating block through the bump, the first chip and the first bonding wires being received in the cavity; and performing a second wire bonding process so as to form a plurality of second bonding wires electrically connecting the second chip and the leads.