Patent ID: 8717833
Filing Date: 2014-05-06
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of non-volatile memory circuits in one chip, wherein each of the non-volatile memory circuits comprises a memory cell section relating to storing data and an individual peripheral circuit for reading relating to the operation of data reading from the memory cell section, wherein each individual peripheral circuit for reading comprises a sense amplifier for data reading from the memory cell section and a switching circuit; a common peripheral circuit, separate from the memory cell section and the individual peripheral circuit for reading in each of the non-volatile memory circuits, being disposed as a common circuit which is used in common by the plurality of non-volatile memory circuits, wherein the common peripheral circuit comprises a write amplifier for data rewriting to the memory cell section in the plurality of non-volatile memory circuits, a control circuit configured to instruct execution of an operation by controlling each circuit in the semiconductor memory device, and a test circuit configured to execute a test function; a first data line for data reading, the first data line being connected between a memory cell and a corresponding sense amplifier; and a second data line for data rewriting, the second data line being connected between the switching circuit and the write amplifier, the first data line and second data line being connected via the switching circuit.