Patent ID: 8652955
Filing Date: 2014-02-18
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) providing a semiconductor wafer having first and second main surfaces, of which the first main surface has a plurality of chip regions including a memory region and a non-memory region; (b) forming, over the first main surface of the semiconductor wafer, a gate stack film having a lower-layer high-k gate insulating film and an upper-layer gate metal electrode film; (c) forming, over the gate stack film, a first resist film for defining a cut region between adjacent gate electrodes in extending directions of gate electrodes in the memory region; (d) performing patterning of the first resist film to form a resist film opening corresponding to the cut region between adjacent gate electrodes; (e) performing etching of the gate stack film in the presence of the patterned first resist film; (f) after the step (e), removing the first resist film; (g) after the step (f), forming, over the first main surface of the semiconductor wafer, a second resist film for defining a line & space pattern corresponding to the gate electrodes in the memory region; (h) performing patterning of the second resist film; (i) performing etching of the gate stack film in the presence of the patterned second resist film; and (j) after the step (i), removing the second resist film.