Patent ID: 6061105
Filing Date: 2000-05-09
Classification: G02F

Abstract:
A liquid crystal display device having electrostatic discharge prevention, said device comprising:an array substrate including a support substrate, a plurality of display electrodes formed on said support substrate, thin-film transistors (TFTs) formed on said support substrate, each TFT having one current-conducting electrode connected to an associated display electrode, a gate line connected to a gate electrode of said TFTs, a data line connected to another current-conducting electrode of said TFTS, and an insulating layer disposed between said gate line and said data line;an opposing substrate, having a common electrode, disposed opposite said array substrate at a predetermined distance;a sealing material, disposed between said array substrate and said opposing substrate, surrounding a display area which includes said display electrodes and said TFTs; anda liquid crystal material disposed in said display area,wherein said insulating layer has a first surface on the side of said sealing material and a second surface on the side of said support substrate, and extends outward beyond the location of said sealing material, one of said gate line and said data line lying on said second surface of said insulating layer extending outward beyond said location of said sealing material for connection with a first terminal of said array substrate, and the other of said gate line and said data line lying on said first surface of said insulating layer in said display area and including a first portion extending toward said sealing material location and terminating prior thereto, and a second portion located beyond said sealing material location and extending outward therefrom for connection with a second terminal of said array substrate, said sealing material including a resin material, and a plate-like or variable-shape inorganic dielectric filler having a dielectric constant greater than that of said resin material; said device further comprising:an associated conducting line formed between said second surface and said support substrate from a location before said sealing material location and extending to a location beyond said sealing material location; andfirst and second via connections for connecting respective said first and second portions of said other of said gate line or data line at said first surface to said associated conducting line at respective locations before and beyond said sealing material location.