Patent ID: 6093602
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of forming contacts between narrowly spaced features in the manufacture of an integrated circuit device comprising:providing features overlying and projecting above a substrate wherein said features are narrowly spaced;depositing a dielectric layer overlying said features and said substrate;patterning said dielectric layer to form openings for planned contacts wherein said openings are formed between some of said features but not formed between other of said features;depositing a first doped polysilicon layer overlying said dielectric layer and filling spaces between said features;etching down said first doped polysilicon layer to the top surface of said features wherein said first doped polysilicon layer remains in and fills said spaces between said features;forming a polycide layer overlying said dielectric layer and said first doped polysilicon layer;patterning said polycide layer and said first doped polysilicon layer to complete said contacts between said features whereby said polycide layer and said first doped polysilicon layer are completely removed between said features where contacts are not to be made; andcompleting the fabrication of the integrated circuit device.