Patent ID: 6232795
Filing Date: 2001-05-15
Classification: H03K

Abstract:
A logic circuit comprising:an n-channel MOS field-effect transistor having a gate receiving a first input signal and a source receiving an inverse signal inverse to a second input signal respectively; andan output stage control transistor means having a drain connected to a drain of said n-channel MOS field-effect transistor,the drains of said n-channel MOS field-effect transistor and said output stage control transistor means being connected as a common node coupled to an inverter for outputting an output signal,said output stage control transistor means comprises a first p-channel MOS field-effect transistor being always held ""on"" with the gate thereof held at a constant potential,said logic circuit further comprising a second p-channel MOS field-effect transistor connected in parallel with said first p-channel MOS field-effect transistor, and structured such that a signal in phase with a signal from the drain of said n-channel MOS field-effect transistor is fed-back to a gate of said second p-channel MOS field-effect transistor.