Patent ID: 6466058
Filing Date: 2002-10-15
Classification: H03L

Abstract:
A lock detection circuit (300) for a phase locked loop, comprising:a cycle slip detector (305) operable to receive a reference clock and a VCO feedback clock, and generate a no cycle slips alarm, wherein the cycle slip detector is operable to detect the frequency difference between the reference clock and the VCO feedback clock that remains for a time period greater than the inverse of the frequency difference of the clocks, whereby the lock detection circuit provides an indication of the lock condition as represented by the no cycle slips alarm, which indicates whether a cycle slip has occurred; and a clock presence detector (310) operable to receive the reference clock and the VCO feedback clock, and generate a no VCO alarm and a no REF alarm, wherein the clock presence detector is operable to detect if the reference clock or the VCO feedback clock is missing for a time greater than a predetermined count of either remaining clock, whereby the lock detection circuit provides an indication for the PLL of the presence of the reference clock and the VCO feedback clock, thereby permitting a large variation of the clock phase or frequency and adequate time for the PLL to react to the disturbance without causing false alarms, while providing an alarm to PLL behavior consistent with a significant deviation from the lock condition in a small, low power and low noise digital solution.