Patent ID: 6284592
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, said method comprising the steps of:forming a field oxide layer on a first conduction type semiconductor substrate having a cell area and a peripheral circuit area, said field oxide layer defining active and field regions in the device;respectively forming first and second gates having capping layers thereon in the cell and peripheral circuit areas after placing a gate insulating layer on said semiconductor substrate;forming first and second impurity regions respectively in said cell and peripheral circuit areas by ion-implantation of a second conduction type impurity using said capping layers as a mask;forming an etching stop layer on said semiconductor substrate to cover said field oxide layer and sides of the first and second gates, forming a sacrificing layer on said etching stop layer, and forming a contact hole exposing said first impurity region;forming a plug contacting with said first impurity region within said contact hole and removing the remaining sacrificing layer to expose a top of said plug and said etching stop layer;forming a third side wall spacer on an exposed side of the top of said plug while forming first and second side wall spacers such that said etching stop layer is respectively interposed between said first and second side wall spacers and the sides of said second and first gates; andforming a third impurity region to be superposed on the second impurity region of said peripheral circuit area, using said capping layer and said first side wall spacer as the mask.