Patent ID: 8307182
Filing Date: 2012-11-06
Classification: H03K

Abstract:
1. An apparatus comprising a circuit that includes: a memory interface that operates using memory access cycles that each include T successive time slots each provided for transfer of B bits of data across the interface, where T and B are positive integers; configurable structure that specifies one of T or B is a selected one of first or second predetermined integers; another interface; and a data transfer portion that facilitates transfer of a quantity of data Q between the memory interface and the other interface, the data transfer portion causing a data transfer sequence on the memory interface to include M of the memory access cycles carried out in succession and thus M·T of the time slots, the data transfer portion automatically determining the value of M as a function of the one of T or B, and automatically determining a subset of the M·T time slots as a function of the one of T or B, where the quantity of data Q will be transferred through the memory interface during the subset of time slots.