Patent ID: 9082651
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A method comprising: forming a control gate structure over a substrate; depositing a charge storage layer over the control gate structure; depositing a memory gate layer over the charge storage layer; depositing a first dielectric layer over the memory gate layer; applying a first etching process to the first dielectric layer and the memory gate layer to form a first memory gate structure and a second memory gate structure, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure; forming first spacers along sidewalls of the first memory gate structure and the second memory gate structure; removing the second memory gate structure; applying a second etching process to the charge storage layer form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure; forming a second spacer over the memory gate structure; and forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure.