Patent ID: 8084342
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A method of manufacturing a device for regulating a flow of electrical current, the method comprising: providing a semiconductor substrate; providing a buried N-well in an NMOS active region, wherein the buried N-well is not electrically contacted via ohmic contacts; providing a P-well in the NMOS active region, the P-well disposed vertically above the buried N-well; providing a buried P-well in a PMOS active region; providing an N-well in the PMOS active region, the N-well disposed vertically above the buried P-well; providing at least a first gate in the PMOS active region; providing at least a second gate in the NMOS active region; exposing the semiconductor substrate in an area proximal to the first gate and the second gate; providing a first Schottky or Schottky-like source electrode and/or drain electrode that is proximal or overlapped with the first date; providing a second Schottky or Schottky-like source electrode and/or drain electrode that is proximal or overlapped with the second gate; and providing a first isolation region to electrically insulate the NMOS active region and the PMOS active region from one another, the first isolation region extending a first distance into the semiconductor substrate, wherein the buried N-well of the NMOS active region forms a first metallurgical junction with the semiconductor substrate, the first metallurgical junction located a second distance into the semiconductor substrate, wherein the buried P-well of the PMOS active region forms a second metallurgical junction with the semiconductor substrate, the second metallurgical junction located a third distance into the semiconductor substrate, wherein the second distance is less than the first distance, and wherein the third distance is less than the first distance.