Patent ID: 9171762
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A method, comprising: forming a dielectric isolation feature in a substrate; forming a gate stack over a surface of the substrate adjacent the dielectric isolation feature; forming a recess cavity in the substrate, wherein the recess cavity extends within the substrate to the dielectric isolation feature; forming a first epitaxial (epi) material in the recess cavity; forming a second epi material over the first epi material and over a top surface of the dielectric isolation feature such that the second epi material physically contacts the top surface of the dielectric isolation feature, wherein the top surface of the dielectric isolation feature faces away from the substrate; and removing a portion of the second epi material, wherein the step of removing completely removes the second epi material to expose the underlying first epi material such that no second epi material is positioned within the recessed cavity.