Patent ID: 6271685
Filing Date: 2001-08-07
Classification: H03K

Abstract:
A semiconductor integrated circuit, comprising:a pass transistor logic circuit; andan output buffer for compensating for an output level of the pass transistor logic circuit,wherein the output buffer includes a bootstrap circuit, and a DC path from a first power source voltage supply via a first transistor and a second transistor to a ground,wherein a capacitor in the bootstrap circuit is connected between a gate of the first transistor and an output terminal,the first transistor has a relatively small channel width and a relatively large channel length in comparison to the second transistor,a first output of the pass transistor logic circuit is applied to a gate of the second transistor,the pass transistor logic circuit, the output buffer including the bootstrap circuit, the first and the second transistors are respectively constituted by NMOS transistors,the output buffer additionally includes a driving force complementary transistor disposed between a second power source voltage and the output terminal, anda second output of the pass transistor logic circuit complementary to the first output is supplied to a gate of the driving force complementary transistor.