Patent ID: 8095903
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. A method comprising: providing a plurality of first signal pins of a layout to be routed together using a first net, wherein the first net conducts a first logical signal between the first signal pins, the first signal varies between at least a first voltage level and a second voltage level, the first voltage level represents a logic 0, and the second voltage level represents a logic 1; providing a plurality of second signal pins of the layout to be routed together using a second net, wherein the second net conducts a second logical signal between the second signal pins and the second signal varies between at least the first voltage level and the second voltage level; performing an automatic routing of the first net using a first nondiagonal conductor track of the layout; performing an automatic routing of the second net using a second nondiagonal conductor track of the layout; and using a computer processor, selecting a spacing between the first and second nondiagonal conductor tracks based on at least a first variable, wherein the first variable is used in a calculation of the spacing, and wherein the first variable comprises a current associated with at least one of the first or second conductor tracks.