Patent ID: 7917878
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. A computer implemented method for placing and routing a multicore chip, comprising: laying out a number of virtual regionalization lines across a chip such that the virtual regionalization lines delineate a plurality of regions on the chip; designating one of the plurality of regions on the chip as a master region and each of a remainder of the plurality of regions on the chip as a duplicate region; placing a number of recurring functional blocks in the master region, wherein each of the number of recurring functional blocks is to be present in each of the plurality of regions on the chip; operating a computer to replicate the number of recurring functional blocks in each duplicate region by placing each recurring functional block in each duplicate region so as to be symmetric with the corresponding recurring functional block in the master region about the virtual regionalization lines; defining a number of horizontal power tracks across the chip such that the horizontal power tracks are symmetrically positioned within each of the plurality of regions on the chip about the virtual regionalization lines; and defining a number of vertical power tracks across the chip such that the vertical power tracks are symmetrically positioned within each of the plurality of regions on the chip about the virtual regionalization lines.