Patent ID: 7977731
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A NOR flash memory, comprising: a semiconductor substrate; device isolation regions that extend in a column direction, are arranged at predetermined intervals in a row direction and separate device forming regions of the semiconductor substrate from each other; a plurality of memory cell transistors comprising a tunnel insulating film formed on the semiconductor substrate, a gate electrode that is formed to extend in the row direction and pass across the tunnel insulating film and the device isolation regions, a drain diffusion layer formed in a device forming region of the semiconductor substrate, and a source diffusion layer formed in the device forming region of the semiconductor substrate on the opposite side of the gate electrode to the drain diffusion layer; a first contact plug formed in a self-aligned manner to be connected to the drain diffusion layer of the memory cell transistor; a bit line that extends in the column direction and is connected to the first contact plug; a local interconnection wiring that is formed in a self-aligned manner to extend in the row direction and to be connected to the source diffusion layer of the memory cell transistor; and a common source line connected to the local interconnection wiring, wherein each memory cell transistor shares the source diffusion layer with another memory cell transistor adjacent thereto on one side thereof in the column direction and shares the drain diffusion layer with another memory cell transistor adjacent thereto on the other side thereof in the column direction, the width of the source diffusion layer in the column direction is narrower than the width of the drain diffusion layer in the column direction, and the common source line is connected to the source diffusion layer via the local interconnection wiring.