Patent ID: 8088647
Filing Date: 2012-01-03
Classification: H01L

Abstract:
1. A method, comprising: receiving a wafer having a surface defined by a plurality of integrated circuit regions, the surface of the wafer having a first passivation layer formed thereon such that a portion of each of a plurality of electrical conductors is accessible through a corresponding opening of a plurality of first openings in the first passivation layer in each integrated circuit region, wherein each integrated circuit region has a second passivation layer and a plurality of terminals on the surface of the wafer accessible through a plurality of second openings in the second passivation layer, each electrical conductor having a first portion in contact with a respective terminal of the plurality of terminals and a second portion that extends over the second passivation layer, the first passivation layer being formed over the second passivation layer and the plurality of electrical conductors, the first passivation layer having the first openings that each expose a second portion of a respective electrical conductor; forming a plurality of solderable metal layer features on the plurality of electrical conductors through the first openings such that each solderable metal layer feature is formed on the accessible portion of a respective electrical conductor of the plurality of electrical conductors; singulating the wafer to form a plurality of flip chip dies that each include at least one integrated circuit region of the plurality of integrated circuit region; and mounting each flip chip die of the plurality of flip chip dies to a corresponding package substrate of a plurality of package substrates, each package substrate having a plurality of solder on pad (SOP) features on a respective surface, each flip chip die mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature.