Patent ID: 6557091
Filing Date: 2003-04-29
Classification: G06F,Y10S

Abstract:
A data processing apparatus for handling multi-thread programs, the apparatus comprising a data processor coupled with a random-access memory containing a plurality of data objects, each said data object being at a respective known location within the memory and being accessed via respective pointers carried by one or more caches associated with respective threads, the apparatus being configured to periodically determine those data objects in the random-access memory having no extant pointers thereto from any source and to delete the same;wherein the apparatus further comprises a plurality of reference buffers, each assigned to a respective cache, each reference buffer holding pointers to each data object referred to by the respective cache, the apparatus being configured to clear, at the conclusion of each thread cache, the associated reference buffer and each referenced data object having no pointers thereto in any other reference buffer.