Patent ID: 6728824
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A memory controller for an incoming multi-channel bitstream, comprising:a computer memory having an address range; a plurality of memory controllers, each memory controller being capable of providing at least one address within the address range of the computer memory; and a selector coupling the plurality of memory controllers to the computer memory, wherein the selector selects a memory controller based on a received data type in said incoming multi-channel bitstream, and wherein the selector provides at least one address to the computer memory that is received from the selected memory controller for the writing of at least a portion of said incoming bitstream, and wherein the selector is capable of receiving a request for data from a second system component, and wherein each memory controller includes controller outputs for providing controller output signals to the selector, and wherein the selector includes selector outputs to the computer memory, and wherein the selector is capable of multiplexing a particular memory controller's controller output signals to the selector for providing output signals to the computer memory.