Patent ID: 8581346
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a first conductive line; a second conductive line crossing over the first conductive line; a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line; a mechanical switch disposed between the resistance variation part and the second conductive line, wherein the mechanical switch includes a nanotube; a conductive pad disposed between the resistance variation part and the second conductive line and having an upper portion on which the nanotube is disposed; and an interlayer dielectric film which is disposed on only a portion of an upper surface of the conductive pad and which covers side walls of the first conductive line, the resistance variation part, and the conductive pad, wherein the interlayer dielectric film has a first opening art partially exposing the upper surface of the conductive pad, and wherein the nanotube is disposed in the first opening part.