Patent ID: 7804176
Filing Date: 2010-09-28
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: (a) a substrate having a front surface, a plurality of electrodes formed on the front surface, and a rear surface opposed to the front surface, wherein the plurality of electrodes include a plurality of first electrodes and a plurality of second electrodes; (b) a memory chip having a first main surface, a plurality of first bonding pads formed on the first main surface, and a first back surface opposed to the first main surface, wherein the first main surface has a pair of first sides mutually opposed and a pair of second sides mutually opposed and intersecting with the first sides, wherein the plurality of first bonding pads are arranged along one of the first sides, and not arranged along either of the second sides, and wherein the memory chip is mounted over the front surface of the substrate such that the first back surface of the memory chip opposes the front surface of the substrate; (c) a control chip having a second main surface, a plurality of second bonding pads formed on the second main surface, and a second back surface opposed to the second main surface, wherein the second main surface has a pair of third sides mutually opposed and a pair of fourth sides mutually opposed and intersecting with the third sides, wherein the plurality of second bonding pads are arranged along one of the fourth sides, and not arranged along either of the third sides and the other of the fourth sides, wherein a size of the control chip is smaller than that of the memory chip in a plan view, wherein the control chip is mounted over the first main surface of the memory chip such that the one of the fourth sides of the control chip is arranged next to one of the second sides of the memory chip, and wherein the control chip is mounted over the first main surface of the memory chip such that a distance between the one of the fourth sides of the control chip and the one of the second sides of the memory chip is smaller than a distance between the other of the fourth sides of the control chip and the other of the second sides of the memory chip; (d) a plurality of first wires coupling the plurality of first bonding pads with the plurality of first electrodes; (e) a plurality of second wires coupling the plurality of second bonding pads with the plurality of second electrodes; (f) a sealing body sealing the memory chip, the control chip, a plurality of first wires and a plurality of second wires; and (g) a plurality of external terminals formed on the rear surface of the substrate, wherein the plurality of first electrodes are arranged along the one of the first sides; and wherein the plurality of second electrodes are arranged along one of the second sides of the memory chip.