Patent ID: 6035371
Filing Date: 2000-03-07
Classification: G06F

Abstract:
In a system comprising:a static random access memory;a data bus coupled with the static random access memory;an address bus, a portion of which is coupled with the static random access memory; anda device coupled with the data bus and generating a row address strobe signal, a column address strobe signal and a write enable signal, wherein a row address and a column address are both applied to the address bus, and the column address strobe signal and the write enable signal are both active low;a method for generating an address to the static random access memory, the method comprising steps of:A) latching, at a time based on the row address strobe, at least a portion of the row address applied on the address bus to form latched address bits;B) concatenating at least a portion of the column address applied on the address bus and the latched address bits to generate the address to the static random access memory; andC) generating an SRAM write enable signal based on the write enable signal and the column address strobe signal, wherein the generating step comprises the steps of:c1) logically ORing the write enable signal and the column address strobe signal to generate an intermediate signal;c2) delaying the intermediate signal to generate a delayed intermediate signal;c3) inverting the intermediate signal to generate an inverted intermediate signal; andc4) logically NANDing the delayed intermediate signal and the inverted intermediate signal to generate the SRAM write enable signal.