Patent ID: 7078241
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A method of forming a ferroelectric memory device comprising: polishing an insulating layer on a plurality of ferroelectric capacitors with a silica slurry to reduce a height of the insulating layer above a surface of the plurality of ferroelectric capacitors so that the surface remains covered by a portion of the insulating layer; polishing the insulating layer further with a ceria slurry to further reduce the height of the insulating layer and to expose a polishing stop layer on the surface of the plurality of ferroelectric capacitors, wherein polishing an insulating layer on a plurality of ferroelectric capacitors with a silica slurry is preceded by: forming a mask that covers the insulating layer on a peripheral circuit region of the ferroelectric memory device and exposes the insulating layer on a cell array region of the ferroelectric memory device; and etching-back the insulating layer on the cell array region to a height that is less than a height of the insulating layer on peripheral circuit region, the method further comprising: