Patent ID: 8339296
Filing Date: 2012-12-25
Classification: H03K

Abstract:
1. An amplifying circuit comprising: a pair of MOS transistors having gate electrodes that receive differential input signals; an amplifier that is electrically coupled to drains of the pair of MOS transistors and a high-potential power-supply line to amplify a difference between potentials of differential output nodes electrically coupled to the corresponding drains of the pair of MOS transistors and to hold the amplified potential at the differential output nodes; offset cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current to the differential output node in accordance with voltages of the drains of the pair of MOS transistors; and a threshold controller that performs setting so that a potential of a first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at the differential output nodes when the difference between the potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.