Patent ID: 8466710
Filing Date: 2013-06-18
Classification: H03K

Abstract:
1. A circuit for restraining a shoot through current, the circuit comprising: a master selecting unit used for receiving an input signal that is at a first logic level or a second logic level and outputting a first master selecting signal and second master selecting signal in response to the input signal; and a logic unit, comprising a first logic element and a second logic element, wherein the first logic element and the second logic element respectively generate a first control signal and a second control signal for controlling two transistor switches connected in series, and change logic states of the first control signal and second control signal respectively according to the first master selecting signal and the second master selecting signal; and the first logic element and the second logic element are NOR gates or the first logic element and the second logic element are NAND gates; wherein when the input signal is at the first logic level, the first logic element changes the logic state of the first control signal to trigger the second logic element to change the logic state of the second control signal; and when the input signal is at the second logic level, the second logic element changes the logic state of the second control signal to trigger the first logic element to change the logic state of the first control signal.