Patent ID: 7099210
Filing Date: 2006-08-29
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells each having a stacked gate including a floating gate and a control gate is arranged in rows and columns; a plurality of word lines each of which connects commonly the control gates of the memory cells arranged in a respective one of the rows; a plurality of bit lines each of which connects commonly drains of the memory cells arranged in a respective one of the columns; a control circuit which performs first control to collectively shift the threshold voltages of the memory cells to within a predetermined range with a first level as an upper limit, second control to shift a lower limit of the threshold voltages shifted to within the predetermined range through the first control toward a second level lower than the first level, and third control to shift the lower limit of the threshold voltages shifted through the second control to a third level between the first and second levels; and a measurement circuit which measures the elapsed time from the start of the second control, the control circuit repeating the second control until the lower limit of the threshold voltages reaches the second level or the elapsed time measured by the measurement circuit reaches a predetermined time, then terminating the second control when the lower limit of the threshold voltages reaches the second level or the elapsed time measured by the measurement circuit reaches the predetermined time and performing the third control.