Patent ID: 8045408
Filing Date: 2011-10-25
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a memory cell array area having a plurality of mats, wherein the plurality of mats are divided into up mats and down mats positioned below the up mats; a multi-mode control signal generating unit configured to control an activation of up and down mat I/O switch control signals, which control I/O switches in the up and down mats, according to a multi-test mode signal and a read/write discriminating signal; a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal; and a mat controller configured to enable word lines and the I/O switches according to the up and down mat I/O switch control signals and the multi-mat select signals, wherein the multi-mode control signal generating unit enables one of the up mat I/O switch control signal and the down mat I/O switch control signal in response to an up and down mat information address signal, when the multi-test mode signal is enabled and the read/write discriminating signal is at a first voltage level, and enables both the up mat I/O switch control signal and the down mat I/O switch control signal regardless of the up and down mat information address signal, when the read/write discriminating signal is at a second voltage level.