Patent ID: 7764532
Filing Date: 2010-07-27
Classification: G11C,H01L

Abstract:
1. A memory array including one-time-programmable (OTP) memory cells, comprising a pair of complementary bitlines, each bitline of the pair of complementary bitlines being connected to diffusion terminals of the OTP memory cells; a precharge circuit for precharging the pair of complementary bitlines to a first voltage level, the precharge circuit including column precharge devices for selectively precharging bitlines adjacent to each bitline of the pair of complementary bitlines to a second voltage level different than the first voltage level; wordlines connected to gate terminals of the OTP memory cells, at least one wordline for driving one bitline of the pair of complementary bitlines to a third voltage level through a programmable conductive link of a corresponding OTP memory cell; a bitline sense amplifier for sensing a voltage differential on the pair of complementary bitlines; and, a reference circuit for selectively providing a reference charge to one bitline of the pair of complementary bitlines.