Patent ID: 6058049
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A reference voltage generating circuit for generating a reference voltage of a memory device having a plurality of bit line pairs and memory cells having a ferroelectric capacitor and a switching transistor, the reference voltage generating circuit, comprising:a first and a second reference word lines;a first dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of said switching transistors are coupled to said first reference word line and drains/sources of said switching transistors are coupled to a bit line of one of said bit line pairs,a second dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of said switching transistors are coupled to said second reference word line and drains/sources of said switching transistors are coupled to the other bit line of one of said bit line pairs; anda reference plate line commonly coupled to said ferroelectric capacitors of both of said dummy blocks.