Patent ID: 6495417
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method for increasing tolerance of contact extension alignment in a capacitor over a bit line of a dynamic random access memory, said method comprising:providing a substrate having a source region, a drain region which are formed therein, a gate electrode which is formed thereon and between said source region, said drain region, and a bit line which is formed thereon; depositing an insulating layer on said gate electrode, said source region, said drain region and said bit line; depositing a dielectric layer on said insulating layer; transferring a hole pattern into said dielectric layer and said insulating layer to form a contact hole in said dielectric layer and said insulating layer to expose a portion of said source/drain region; depositing a conductive layer on said dielectric layer and said contact hole, wherein an etching selectivity of said conductive layer is near an etching selectivity of said dielectric layer; transferring an electrode pattern into said conductive layer to form an electrode of said capacitor.