Patent ID: 6057604
Filing Date: 2000-05-02
Classification: H01L

Abstract:
A contact structure for an integrated circuit device, comprising:a substrate having a surface;a gate electrode on the substrate surface, wherein the gate electrode has a cap layer of a first material;a sidewall alongside the gate electrode comprising:a second material selectively etchable over the first material on a side of the gate electrode and the substrate surface adjacent the gate electrode; andthe first material on the second material alongside the gate electrode and over the substrate surface;a interlevel dielectric layer of the second material over the gate electrode on the capping layer and over the sidewall and the substrate surface, the interlevel dielectric layer having an opening therethrough to expose a portion of the substrate surface adjacent the sidewall, wherein a portion of the sidewall is also exposed in the opening;a conductive plug in the opening in contact with the substrate surface and the exposed portion of the sidewall the conductive plug filling the opening and having an upper surface substantially planar with an upper surface of the interlevel dielectric layer; andan interconnect layer on the interlevel dielectric layer and the conductive plug.