Patent ID: 6559691
Filing Date: 2003-05-06
Classification: G11C,H03K

Abstract:
A semiconductor circuit comprising:an input terminal capable of inputting an input signal of binary logic to be represented by a first voltage or a reference voltage; an output terminal capable of outputting an output signal to be represented by a second voltage or said reference voltage, corresponding to the logic of said input signal; a voltage supply terminal for supplying said second voltage; a first N-channel transistor having a gate connected to said input terminal, a drain connected to said output terminal, and a source connected to a reference voltage supply terminal for supplying said reference voltage; and a second N-channel transistor having a drain connected to said output terminal, a source connected to said reference voltage supply terminal, and a gate connectable to said input terminal and said voltage supply terminal; a third N-channel transistor having a drain connected to said output terminal, and the drains of said first and second N-channel transistors both connected to the source of said third N-channel transistor; said first voltage being applied to the gate of said third N-channel transistor, and said first voltage being applied to the gates of said first and second N-channel transistors before said second voltage is applied to the gate of said second N-channel transistor to output an output signal represented by said second voltage or said reference voltage through said output terminal.