Patent ID: 6846683
Filing Date: 2005-01-25
Classification: B82Y,G11C,H01F,H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: providing a workpiece; forming conductive lines over the workpiece, wherein forming the conductive lines comprises forming a dielectric layer over the workpiece, etching a plurality of trenches in the dielectric layer, depositing a liner on the top surface of the dielectric layer and within the trenches, depositing a metal layer over the liner, and polishing the metal layer until the metal layer is coplanar with the liner on the top surface of the dielectric layer, leaving a portion of the liner exposed; depositing a surface-smoothing conductive material over the conductive lines; polishing the surface-smoothing conductive material; depositing a magnetic material layer over the polished surface-smoothing conductive material; and patterning the magnetic material layer, wherein portion of the magnetic material layer are removed simultaneously with portions of the liner to form magnetic stacks.