Patent ID: 6913984
Filing Date: 2005-07-05
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of fabricating memory with nano dots, the method comprising: (a) sequentially depositing a first insulating layer, a charge storage layer, a sacrificial layer, and a metal layer on a substrate in which source and drain electrodes are formed; (b) forming a plurality of holes on the resultant structure by anodizing the metal layer and oxidizing portions of the sacrificial layer that are exposed through the holes; (c) patterning the charge storage layer to have nano dots by removing the oxidized metal layer, and etching the sacrificial layer and the charge storage layer using the oxidized sacrificial layer as a mask; and (d) removing the oxidized sacrificial layer, depositing a second insulating layer and a gate electrode on the patterned charge storage layer, and patterning the first insulating layer, the patterned charge storage layer, the second insulating layer, and the gate electrode to a predetermined shape.