Patent ID: 6844631
Filing Date: 2005-01-18
Classification: H01L

Abstract:
1. An integrated circuit comprising: a substrate having active circuitry and a perimeter; a plurality of layers of interconnect over the substrate; a final layer of interconnect over the plurality of layers of interconnect having a final layer pad and a plurality of interconnect lines, the final layer pad comprising copper; a layer of passivation over the final layer of interconnect having an opening over the final layer pad; and a bond pad comprising aluminum formed over and electrically contacting the final layer pad having a first region and a second region, wherein the first region is between the second region and the perimeter, the first and second regions are substantially non-overlapping and contiguous, and the first region performs a function of one of a probe region and a wire bond region and the second region performs the function of one of probe region and wire bond region not performed by the first region, wherein the bond pad is positioned directly over the active circuitry and over interconnect lines of the final layer of interconnect lines that are unrelated to the bond pad.