Patent ID: 6362048
Filing Date: 2002-03-26
Classification: H01L,Y10S

Abstract:
A method for manufacturing the floating gate of a flash memory, comprising the steps of:providing a substrate having an active region and an isolation region thereon; forming a tunneling oxide layer over the substrate; forming a polysilicon layer over the tunneling oxide layer; forming a silicon nitride layer over the polysilicon layer; defining a position for forming a floating gate position in the active region; removing the silicon nitride layer above the floating gate position to form an opening; oxidizing the polysilicon layer exposed by the opening to form a floating gate oxide layer; forming a buffer layer over the substrate; forming a first spacer on the sidewall of the buffer layer; removing a portion of the buffer layer not covered by the first spacer to expose a portion of the silicon nitride layer; removing the first spacer, the buffer layer and the silicon nitride layer outside the active region; forming a second spacer on the sidewall of the first spacer, the buffer layer and the silicon nitride layer; removing the floating gate oxide layer not covered by the second spacer; removing the second spacer; removing the buffer layer; and removing the polysilicon layer not covered by the floating gate oxide layer to form the floating gate.