Patent ID: 6812097
Filing Date: 2004-11-02
Classification: H01L,Y10S

Abstract:
A method for manufacturing a non-volatile memory device, the method comprising the steps of:forming a first dielectric layer above a semiconductor layer; forming a first conductive layer above the first dielectric layer; forming a stopper layer above the first conductive layer; patterning the stopper layer and the first conductive layer; forming an ONO film including a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above the semiconductor layer and on both sides of the first conductive layer; forming a second conductive layer above the ONO film; anisotropically etching the second conductive layer, and then isotropically etching the second conductive layer to form sidewall control gates on both side surfaces of the first conductive layer through the ONO film; forming an impurity layer that is to become at least one of a source region and a drain region in the semiconductor layer; forming a second dielectric layer over an entire surface of the substrate; polishing the second dielectric layer such that the stopper layer is exposed; removing the stopper layer; and patterning the first conductive layer to form a word gate.