Patent ID: 6789167
Filing Date: 2004-09-07
Classification: G06F

Abstract:
An integrated circuit comprising:a plurality of processors; a first, second, third, and fourth convertible cache capable of operating in a mode selected from the group of modes consisting of local memory mode and cache mode; a first processor coupled to receive instructions from the first convertible cache and data from the second convertible cache; a second processor coupled to receive instructions from the third convertible cache and data from the fourth convertible cache; a fifth cache operable as a second level cache, the fifth cache coupled to the first, second, third, and fourth caches and capable of being coupled to a main memory external to the integrated circuit; a block transfer engine capable of transferring blocks of data between the second convertible cache and the main memory when the second convertible cache is operated in local memory mode; a peripheral specific apparatus for interfacing the first processor to an external peripheral device; wherein the first and second processor are capable of operating as general purpose processors; and wherein the first processor is capable of operating as a general purpose processor when the convertible cache is operated in the cache mode, and the first processor is capable of operating as a processor of an intelligent peripheral when the convertible cache is operated in the local memory mode.