Patent ID: 6683363
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, said MOS trench structure comprising:a semiconductor substrate; a plurality of non-contiguous parallel trenches formed in the semiconductor substrate, each parallel trench defined by ends, sidewalls and a bottom, and each two adjacent parallel trenches separated by a mesa containing the semiconductor device, said mesas having a mesa width; a peripheral trench formed in the semiconductor substrate and defined by sidewalls and a bottom, said peripheral trench at least partially surrounding the parallel trenches and having a portion that is spaced from ends of the parallel trenches by a parallel trench to peripheral trench spacing; a dielectric material lining the parallel and peripheral trenches; and a conductive material substantially filling the dielectric-lined trenches.