Patent ID: 6316929
Filing Date: 2001-11-13
Classification: G01R

Abstract:
A frequency measurement test circuit comprising:a frequency divider for frequency-dividing a input signal to be measured; anda detection circuit for outputting a signal of level set on the basis of a relationship in magnitude between the frequency of the input signal frequency-divided by said frequency divider and that of a reference clock signal, said detection circuit comprises a second frequency divider for dividing the frequency of the reference clock signal to 1/n (n is a positive even number), an inverter for inverting a signal output from said second frequency divider, a shift register constructed by (n/2) series-connected flip-flops including a flip-flop at a first stage having a data input terminal connected to an output terminal of said inverter, and an AND circuit for ANDing output signals from said flip-flops.