Patent ID: 8780918
Filing Date: 2014-07-15
Classification: H04B,H04J,H04L

Abstract:
1. A data processing apparatus comprising: a first frame processor that fragments a first input frame into a first sequence of data segments, and outputs the first sequence of data segments along with first position information indicative of a position of a data segment within the first input frame; a second frame processor that fragments a second input frame into a second sequence of data segments, the second input frame being a redundant frame of the first input frame and being input asynchronously with the first input frame, and outputs the second sequence of data segments along with second position information indicative of a position of a data segment within the second input frame; a first storage and a second storage that receive and store data segments output from the first and the second frame processors respectively; and a fragmented data processor that determines which of the first input frame and the second input frame arrives first by comparing the first position information of the first sequence of data segments and the second position information of the second sequence of data segments, switchably reads out data segments from one of the first storage and the second storage based upon the comparing of the first position information and the second position information and outputs the data segments, wherein when a reading of data from one of the first storage and the second storage is switched to the other of the first storage and the second storage, the fragmented data processor combines a first portion of the first sequence of data segments that have been read out from the first storage and a second portion of the second sequence of data segments that have been read out from the second storage into a third sequence of data segments used to reproduce the first input frame without loss or duplication of data, and wherein the third sequence of data segments are output.