Patent ID: 7745298
Filing Date: 2010-06-29
Classification: H01L

Abstract:
1. A method for forming a via, the method comprising: forming a first gate electrode over a semiconductor substrate; forming a second gate electrode over the semiconductor substrate; forming a first spacer along a first side of the first gate electrode and a second spacer along a first side of the second gate and a source/drain region in the semiconductor substrate between the first gate electrode and the second gate electrode, wherein a first portion of the source/drain region underlies the first spacer and a second portion underlies the second spacer; forming a silicide region in the source/drain region; after forming the silicide region, forming a first post-silicide spacer adjacent the first spacer and over the source/drain region and forming a second post silicide spacer adjacent the second spacer, wherein the first and second post-silicide spacers have an etch characteristic and are not greater than 20 nm thick; forming a conformal layer over the first and second post-silicide spacers, the first and second gate electrodes, and the silicide region, wherein the conformal layer has an etch characteristic different from the etch characteristic of the first and second post-silicide spacers; forming an interlayer dielectric layer over the conformal layer, wherein the interlayer dielectric has an etch characteristic different from the etch characteristic of the conformal layer; etching, using a first chemistry, a hole over the silicide region and in the interlayer dielectric, wherein the etching stops without penetrating through the conformal layer and the hole at the conformal layer is exclusively over the silicide layer, and erosion of a portion of the conformal layer occurs laterally to the hole in a region between the hole and the first gate electrode; etching, using a second chemistry, the conformal layer to extend the hole through the conformal layer and exposing the first post silicide spacer in the region between the hole and the first gate electrode and leaving a portion of the conformal layer on the silicide layer between the hole and the first gate; and forming a conductive via in the hole, extending to the silicide region.