Patent ID: 6027999
Filing Date: 2000-02-22
Classification: G02F,H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures are covered by an insulating layer;depositing and patterning a first metal layer overlying said insulating layer to form a metal line and a bonding pad;depositing a dielectric layer overlying said metal line and said bonding pad;opening vias through said dielectric layer to said metal line but not to said bonding pad;depositing a second metal layer overlying said dielectric layer and filling said via openings and etching back said second metal layer to form metal plugs;depositing a third metal layer overlying said dielectric layer and said metal plugs and patterning said third metal layer to form pixels contacting said metal plugs;depositing a passivation layer overlying said pixels;etching a via opening through said passivation layer and said dielectric layer to said bonding pad; andforming a wire bond to contact said bonding pad to complete the fabrication of said integrated circuit device.