Patent ID: 7852666
Filing Date: 2010-12-14
Classification: G11C

Abstract:
1. A nonvolatile memory comprising: first and second memory-cell blocks having different respective block address information and each comprising a plurality of nonvolatile memory cells; a global bitline common to the first and second memory-cell blocks; first and second local bitlines corresponding to the first and second memory-cell blocks, respectively, and coupled to each other; a common bitline selection circuit interposed between the first and second memory-cell blocks and coupled between the first and second local bitlines and the global bitline; a first bitline selection circuit disposed opposite the common bitline selection circuit with respect to the first memory-cell block and coupled between the first local bitline and the global bitline; and a second bitline selection circuit disposed opposite the common bitline selection circuit with respect to the second memory-cell block and coupled between the second local bitline and the global bitline.