Patent ID: 7423314
Filing Date: 2008-09-09
Classification: H01L

Abstract:
1. A semiconductor memory device comprising; a first conductive-type semiconductor substrate including a flat region and a step region having one main surface higher than the other main surface placed higher than said flat region; a gate electrode being formed on one of main surfaces of said semiconductor substrate in said step region through the intermediary of a gate oxide film; A couple of first and second impurity diffusion regions of a second conductive-type different from said first conductive-type being formed in the place clipping said gate electrode of a part of said flat region in the surface layer region on one of main surface sides of said semiconductor substrate; second conductive-type first and second variable resistance regions having lower impurity density than said first and second impurity regions and being formed respectively from the region neighboring said first and second impurity regions of said flat region to a side face of a step unit placed in said step region between the region underneath said gate electrode and said first and second impurity regions in said surface layer region a first and second main electrodes being formed on said first and second impurity region of said semiconductor substrate; a first charge storing unit being formed between and facing said first electrode and said gate said electrode; and a second charge storing unit being formed between and facing said second electrode and gate electrode, wherein said first and second charge storing units have a multi-layer structure in order from a bottom oxide film, to charge storing nitride film, to top oxide film, respectively, the distance between said first main electrode and said charge storing nitride film formed in said first charge storing unit is constant, and the distance between said second main electrode and said charge storing nitride film formed in said second charge storing unit is constant.