Patent ID: 7454677
Filing Date: 2008-11-18
Classification: G01R

Abstract:
1. An integrated circuit, comprising: A. core logic having a system data output; B. a first switch having an input connected to the system data output, a select input connected to a first select lead, and an output; C. an output buffer having an input connected to the output of the first switch and an output; D. a latch buffer having an input connected to the output of the output buffer and an output connected to the input of the output buffer; E. a serial data input lead; F. a multiplexer having a first data input connected to the serial data input lead, a second data input connected to the input of the output buffer, a select input connected to a second select lead, and an output; G. a memory circuit having an input connected to the output of the multiplexer, a control input connected to a first control lead, and an output; H. a serial data output lead connected to the output of the memory circuit; and I. a second switch having an input connected to the output of the memory circuit, a control input connected to a second control lead, and an output connected to the input of the output buffer.