Patent ID: 6480989
Filing Date: 2002-11-12
Classification: G06F,H01L

Abstract:
A method for use in designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer, said method comprising:a component layout step of laying out electronic components on the semiconductor layer; a network layout step of laying out, on the primary metal layer, a primary power distribution network for distributing power to the electronic components; a mesh design step of designing a power mesh that includes horizontal power trunks on the horizontal metal layer and vertical power trunks on the vertical metal layer, by calculating a uniform trunk width for all of the horizontal power trunks and all of the vertical power trunks based on a desired maximum voltage drop for the electronic component layout generated in said component layout step; and a mesh layout step of laying out the horizontal power trunks on the horizontal metal layer and the vertical power trunks on the vertical metal layer using the uniform trunk width calculated in said mesh design step, so as to form the power mesh, and specifying an electrical connection between the power mesh and the primary power distribution network, wherein the uniform trunk width is also based on wirebond resistance and a number of bond pads.