Patent ID: 9065607
Filing Date: 2015-06-23
Classification: H04L

Abstract:
1. A clock data recovery circuit, comprising: an oscillator configured to output a clock signal; a phase comparator configured to output a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider configured to output a feedback clock signal obtained by dividing the clock signal by a predetermined division ratio; a first variable delay circuit configured to output a delay data signal obtained by providing a first predetermined delay time to the reception data signal, the first predetermined delay time being based on a first phase setting information; a second variable delay circuit configured to output a delay feedback clock signal obtained by providing a second predetermined delay time to the feedback clock signal, the second predetermined delay time being based on a second phase setting information; a frequency phase comparator configured to output a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector configured to output a determination signal indicating whether or not the frequency difference and the phase difference between the delay data signal and the delay feedback clock signal are within a predetermined range; and a multiplexer configured to receive the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.