Patent ID: 9224349
Filing Date: 2015-12-29
Classification: G09G

Abstract:
1. A display device, comprising: a display panel having a plurality of data lines and a plurality of gate lines crossing the data lines, the gate lines including a plurality of odd-numbered gate lines and a plurality of even-numbered gate lines; a timing controller to generate a gate output enable signal; a gate output enable signal division circuit to extract odd-numbered high logic periods of the gate output enable signal to output a first gate output enable signal and to extract even-numbered high logic periods of the gate output enable signal to output a second gate output enable signal; and a gate driver to supply a first gate pulse to at least one of the odd-numbered gate lines in response to the first gate output enable signal and a second gate pulse to at least one of the even-numbered gate lines in response to the second gate output enable signal, wherein the timing controller is also configured to generate a gate shift clock signal, and wherein the first and second gate pulses overlap each other for a period shorter than one cycle of the gate shift clock signal.