Patent ID: 6601162
Filing Date: 2003-07-29
Classification: G06F

Abstract:
A processor which executes pipeline processing having a plurality of stages, comprising:an instruction fetch unit for fetching an arithmetic instruction to output a source operand number and a destination operand number of the arithmetic instruction, and when said arithmetic instruction is a conditional branch instruction, said instruction fetch unit predicting whether a condition of said conditional branch instruction will be established or not, and outputting the predicted result as prediction result information; a register file introducing said source operand number outputted from said instruction fetch unit to output a source operand corresponding to said source operand number; a first pipeline having at least a bypass multiplexer and an arithmetic and logic unit, in which said bypass multiplexer is supplied with an arithmetic result operand, which is a result of arithmetic operation of said arithmetic and logic unit, and said source operand outputted from said register file, and said bypass multiplexer selects one of said arithmetic result operand and said source operand in response to a select signal and outputs an operand selected by said bypass multiplexer to said arithmetic and logic unit; a second pipeline including at least a branch unit for judging whether the condition of said branch instruction has been established or not; a bypass select logic circuit for generating said select signal by using at least said prediction result information; and a plurality of prediction registers for storing said prediction result information, and said prediction result information being transferred in order of precedence to said prediction registers in synchronism with respective stages of the pipeline processing, wherein, when said instruction fetch unit outputs said source operand number of the arithmetic instruction located next to said conditional branch instruction in a row of instructions, said instruction fetch unit also outputs branch delay slot information indicating that said arithmetic instruction is next to said conditional branch instruction in the row of instructions.