Patent ID: 8922460
Filing Date: 2014-12-30
Classification: G09G

Abstract:
1. A level shift circuit comprising: an input terminal; a first output terminal; a first node; a first power supply line connected to a first power supply having a first power supply voltage; a second power supply line connected to a second power supply having a second power supply voltage; a first transistor of a first conductivity type connected between said first power supply line and said first node; second and third transistors of a second conductivity type connected in series between said second power supply line and said first node, said first transistor and said second transistor including control terminals supplied with a first control signal in common, said first transistor and said second transistor controlled to be turned on or off complementarily by said first control signal, said third transistor including a control terminal connected to said input terminal to which an input data signal is supplied, an amplitude of said input data signal being lower than a power supply amplitude between said first power supply voltage and said second power supply voltage; a clocked inverter arranged between said first power supply line and said second power supply line, said clocked inverter including an input and an output connected to said first node and said first output terminal, respectively, said clocked inverter controlled to be turned on or off by a second control signal supplied thereto; an inverter arranged between said first power supply line and said second power supply line, said inverter including an input connected to said first output terminal; a switch connected between said first node and an output of said inverter, said switch controlled to be turned on or off by a third control signal supplied thereto; and a control signal generation circuit that generates said first to third control signals and supplies said first to third control signals to one or more level shift circuits, said control signal generation circuit deactivating said clocked inverter by said second control signal at a first timing, turning off said switch by said third control signal at a subsequent second timing, turning on said first transistor by said first control signal at a subsequent third timing to set said first node to said first power supply voltage, turning off said first transistor by said first control signal at a subsequent fourth timing, activating said clocked inverter by said second control signal at a subsequent fifth timing to cause said clocked inverter to invert a signal at said first node and to output said inverted signal to said first output terminal, and turning on said switch by said third control signal at a subsequent sixth timing to cause an output of said inverter to be electrically conducted to said first node, said first to fourth timings being positioned temporally before a data output switch timing, said fifth timing corresponding to said data output switch timing, and said sixth timing being positioned temporally after said data output switch timing.