Patent ID: 8832510
Filing Date: 2014-09-09
Classification: G01R

Abstract:
1. An integrated circuit, comprising: a plurality of flip-flops; at least one clock gating cell for providing a clock signal to the plurality of flip-flops; a functional logic circuit for providing a functional enable signal to an enable port of the at least one clock gating cell during a scan capture operation; and a circuit for reducing peak power during transition fault testing of the integrated circuit, wherein the circuit includes, a programmable register having scan enable (SE) and scan data input (SDI) ports for receiving scan shift and SDI signals respectively, wherein an output port of the programmable register is connected to an input port “D” of the programmable register; and a multiplexer connected to the programmable register and having first and second input ports, a select input port and an output port, wherein the first input port is maintained asserted, the second input port is connected to the output port of the programmable register, and the scan shift signal is input to the select input port, and wherein the output port of the multiplexer is connected to a Test Enable (TE) port of the at least one clock gating cell, wherein the at least one clock gating cell selectively provides the clock signal to the plurality of flip-flops during a scan shift operation and the scan capture operation, based on the scan shift signal and the functional enable signal, thereby reducing the peak power during the transition fault testing.