Patent ID: 6483757
Filing Date: 2002-11-19
Classification: G11C,H03K,H03L

Abstract:
A variable delay circuit for a delay-locked loop, comprising:an input terminal; an output terminal; a reference terminal; a first buffer having a first input coupled to the input terminal and a first buffer output; a second buffer having a second input coupled to the first buffer output, and a second buffer output coupled to the output terminal; a first capacitor coupled between the first buffer output and the reference terminal; a second capacitor; a first isolation switch serially coupled with the second capacitor between the first buffer output and the reference terminal, the first isolation switch having a first switching input and being responsive to a selection signal at the first switching input to selectively couple the second capacitor between the first buffer output and the reference terminal; and a model circuit serially coupled with the first and second buffers having a model circuit delay corresponding to the delay of an input signal.