Patent ID: 7694260
Filing Date: 2010-04-06
Classification: G06F,H01L

Abstract:
1. A semiconductor integrated circuit comprising: a first wiring layer having one pair of wiring traces of first and second potentials that differ from each other; a second wiring layer disposed in a layer different from said first wiring layer and having one pair of wiring traces of the first and second potentials; and one or a plurality of intermediate wiring layers disposed between said first wiring layer and said second wiring layer, wherein the pair of wiring traces of said first wiring layer are disposed in parallel with a prescribed spacing between them, wherein the pair of wiring traces of said second wiring layer are disposed in parallel with a minimum spacing between them for rendering wiring tracks effective, wherein the wiring traces of said first wiring layer are in a direction perpendicular to the wiring traces of said second wiring layer, wherein same-potential wiring traces of said first wiring layer and of said second wiring layer are electrically connected through said intermediate wiring layer and vias, wherein, as seen from a direction normal to the plane, said intermediate wiring layer is disposed within a zone of wiring tracks superposed by wiring of said first wiring layer and wiring of said second wiring layer, wherein a number of first vias that connect the wiring of said intermediate wiring layer and the wiring of said first wiring layer is m where m is an integer equal to or greater than 1, wherein a number of second vias that connect the wiring of said intermediate wiring layer and the wiring of said second wiring layer is m where m is an integer equal to or greater than 1, wherein the first vias are disposed within a zone of wiring tracks superposed by wiring traces of said second wiring layer and of said first wiring layer as seen from the direction normal to the plane and fit within a rectangular shape of j columns and h rows where j, h are integers equal to or greater than 1 and j×h≧m, wherein the second vias are disposed within a zone of wiring tracks superposed by wiring traces of said second wiring layer and of said first wiring layer as seen from the direction normal to the plane and fit within a rectangular shape of n columns and k rows where n, k are integers equal to or greater than 1 and n×k≧m, wherein the first vias are disposed within an area in which same-potential wiring traces of the wiring of said intermediate wiring layer and the wiring of said first wiring layer overlap, wherein the second vias are disposed within an area in which same-potential wiring traces of the wiring of said second wiring layer and of the wiring of said first wiring layer overlap, wherein a center of a via unit for the first potential of via units comprising the second vias, as seen from the direction normal to the plane, is disposed at an intersecting portion of said first wiring layer and said second wiring layer, wherein a via unit for the first potential of via units comprising the first vias is disposed at a position where it is superimposed at least partially upon the via unit for the first potential of via units comprising the second vias, as seen from the direction normal to the plane, and wherein a center of the via unit for the first potential of via units comprising the first vias, as seen from the direction normal to the plane, is offset by a prescribed amount from the center of the via unit for the first potential of via units comprising the second vias, as seen from the direction normal to the plane, toward a side of wiring of the second potential in said second wiring layer.