Patent ID: 8305837
Filing Date: 2012-11-06
Classification: G06F,G11C

Abstract:
1. A semiconductor system, comprising: a memory controller configured to generate and output a system clock corresponding to an address signal and a command signal, and first and second data clocks corresponding to a data signal, wherein the second data clock as received by the data clock input unit is intended to be an inverse of the first data clock, the memory controller shifts a phase of the second data clock to generate the second data clock having the shifted phase according to a training information signal; and a semiconductor memory device configured to receive the address signal and the command signal based on the system clock and input/output the data signal based on the first and second data clocks to perform a predetermined internal operation, detect a logic level of the second data clock based on a phase of the first data clock, and generate and output the training information signal according to the detected logic level at a training operation mode.