Patent ID: 8457943
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A simulating system for simulating a multiprocessor system, comprising: a computer processor; a function simulator said function simulator further comprises an access record extracting module for obtaining a memory access record of an instruction by the computer processor, wherein said memory access record of the instruction includes information for identifying the processor for executing the instruction associated therewith, the instruction, and the access memory location associated therewith; and a parallel cycle-accurate simulator comprising a plurality of parallel simulation units, each of parallel simulation units of said parallel cycle-accurate simulator further comprises a memory access control module for providing information for identifying an instruction causing an access to a memory hierarchy structure; and a synchronization control system, the synchronization control system comprising: a) an identifying unit for identifying sets of instructions, memory accesses of each set being necessary to be synchronized, according to memory access records of instructions provided by said access record extracting module when the execution of an executable program by said multiprocessor system is simulated in said function simulator; and b) a synchronizing unit for determining execution of instructions in one of said sets by said parallel simulation units according to said information provided by said memory access control module, so that the memory accesses of said instructions are performed in the order corresponding to global simulation times of the instructions; wherein said memory access control module is configured to hang up the execution of respective memory accesses before the completion of memory access synchronization, and resume the execution of the hung up memory accesses in response to a control from said synchronizing unit.