Patent ID: 7508025
Filing Date: 2009-03-24
Classification: G11C,H01L

Abstract:
1. A method for forming an array of flash memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates lines are separated from the floating gates by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition, wherein forming the asymmetrical low tunnel barrier intergate insulator includes a forming low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.