Patent ID: 6239627
Filing Date: 2001-05-29
Classification: H03K,H03L

Abstract:
In a system using a reference clock with a reference frequency, a clock multiplier that generates a multiplied clock with a frequency that is a multiple of the reference frequency of the reference clock, comprising:(a) a pulse generator network of N pulse cascaded generators PG1-PGN, with the output of each pulse generator PG1-PG(N-1) being respectively coupled to the input of the next pulse generator PG2-PGN;(b) the pulse generators, when triggered, respectively generating pulses P1-PN, each with a leading edge and a trailing edge, and a pulse width determined by a selectable pulse-width delay signal;(c) the pulse generator PG1 being triggered by a leading edge of the reference clock, and the remaining pulse generators PG2-PGN being triggered by the trailing edge of the pulse P from the previous pulse generator;(d) a synchronization circuit, coupled to the pulse generator PGN, that detects phase deviations between the trailing edge of the pulse PN from pulse generator PGN and the leading edge of the reference clock, and provides a corresponding phase adjustment signal;(e) a pulse-width delay selection circuit coupled to at least one of the pulse generators PG1-PGN and responsive to the phase adjustment signal to correspondingly adjust the pulse-width delay signal for the at least one of the pulse generators PG1-PGN so as to achieve phase locking between the reference clock and the pulse PN generated by the pulse generator PGN;(f) such that, for each period of the reference clock, the pulse generator network generates a sequence of non-overlapping pulses P1-PN; and(g) a waveform generator responsive to selected ones of the pulses P1-PN to generate the multiplied clock with clock edges defined by such selected ones of the pulses P1-PN.