Patent ID: 6650016
Filing Date: 2003-11-18
Classification: H01L,H05K

Abstract:
A substrate for connecting integrated circuits comprising: a substrate top surface with at least one standard-pattern array of contacts formed thereon and a patterned dielectric layer disposed on said top surface, said patterned dielectric layer being patterned to surround and isolate from one another a subset of said standard-pattern array of contacts in which a conductive contact interconnect member is disposed on said top surface and electrically connecting at least some of said array of contacts, said contact interconnect member being displaced from at least one selected location of the contact locations in said at least one array, and said patterned dielectric layer covers said at least one selected location, wherein an integrated circuit contact on a bottom surface of an IC at said selected location of said top surface is insulated from a contact, of said array of contacts, located at said selected location.