Patent ID: 6670229
Filing Date: 2003-12-30
Classification: H01L

Abstract:
A method of manufacturing a bipolar transistor using the same process phases, as those used to produce a CMOS nonvolatile memory devices that include an N-type CMOS device and a P-type CMOS device, the method comprising:forming a semiconductor buried layer, having a second type of conductivity, in a substrate having a first type of conductivity, simultaneously to the formation of a similar layer of buried semiconductor for said N-type CMOS device; forming an isolator semiconductor layer, having a second type of conductivity, in direct contact with said semiconductor buried layer and structured to delimit a portion of said substrate, thereby forming the base region simultaneously to the formation of an N-well area of said P-type CMOS device; forming an emitter region and a collector contact region respectively in said base region and in said isolation semiconductor layer having a second type of conductivity, simultaneously to the formation of a similar semiconductor layer for source and drain regions of said N-type CMOS device; and forming a base contact region of said transistor in said base region having a first type of conductivity, simultaneously to the formation of a similar layer of semiconductor for source and drain regions of said P-type CMOS device.