Patent ID: 6567289
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A semiconductor memory device, comprising:(a) a plurality of large memory sectors having a first physical dimension, the plurality of large memory sectors comprising a first large memory sector and a second large memory sector, wherein each of the large memory sectors are independently lockable; (b) a plurality of small memory sectors having a physical dimension that is smaller than the first physical dimension, the plurality of small memory sectors comprising a first small memory sector and a second small memory sector, wherein each of the large memory sectors are independently lockable; (c) a x-decoder connected with the large and small memory sectors via word-lines comprising a first word-line and a second word-line; and (d) a y-decoder connected with the large and small memory sectors via bit-lines comprising a first bit-line and a second bit-line, wherein the y-decoder is connected with the first small memory sector via the first bit-line and the second small memory sector via the second bit-line, wherein a residual area is formed near a corner of the semiconductor memory device, the residual area being defined by the large and small memory sectors, the-x-decoder, and the y-decoder.