Patent ID: 7409030
Filing Date: 2008-08-05
Classification: G09G

Abstract:
1. An apparatus to recover an optimized clock signal by sampling an analog signal with a synchronization signal, said apparatus comprising: a mode detector for generating a detected value in response to said synchronization signal; a clock recovery device for generating a clock signal in response to said detected value; and an analog-to-digital converter for sampling said analog signal in response to said clock signal and generating sample data; wherein said sample data having at least one turning point n occurring in said sample data subject to a slope polarity change are fed to said clock recovery device for determining whether said sample data are either desirable or undesirable, which is indicated by a detection result according to a sum value of said slope polarity change of said at least one turning point n, and said sum value is defined to be Σ|f′(n+)−f′(n−)| in said sample data for all of said at least one turning point n, where f′(n+)=f(n+1)−f(n), f′(n−)=f(n)−f(n−1), and all of f(n+1), f(n), f(n−1) are selected from said sample data; wherein said clock recovery device regenerates the clock signal to said analog-to-digital converter if said sample data is undesirable, so as to optimize the clock signal.