Patent ID: 7487287
Filing Date: 2009-02-03
Classification: G11C

Abstract:
1. A time-efficient read/write control method for an embedded EEPROM and processor, comprising: providing an EEPROM BUSY signal that is active when the EEPROM is engaged in a write activity; executing program code by the processor when the EEPROM BUSY signal is inactive; blocking write code execution by the processor at the start of a write subroutine when the EEPROM BUSY signal is active; blocking read code execution with a read detection circuit that detects when the EEPROM BUSY signal is active and when a read is requested for an EEPROM address; and continuing program code executing by the processor when the EEPROM BUSY signal is inactive, wherein the EEPROM BUSY signal blocks code execution such that write operations are blocked at the start of a write subroutine and such that read operations are blocked by the read detection circuit only when the read operations result in EEPROM read during an active EEPROM BUSY signal.