Patent ID: 9092591
Filing Date: 2015-07-28
Classification: G06F

Abstract:
1. A method, in a data processing system comprising at least one processor and at least one memory, for pruning a layer trait library for use in wire routing in an integrated circuit design process, comprising the following operations performed by the data processing system: receiving a plurality of wirecodes and a metal stack definition; generating a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition, wherein generating the pruned layer trait library comprises: generating a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library; storing the pruned layer trait library for performing wire routing of an integrated circuit design; and fabricating an integrated circuit device based on the integrated circuit design, including the wire routing performed based on the stored pruned layer trait library.