Patent ID: 8988939
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a substrate; a first set of memory cells which is selected for programming and comprises a channel of an active area, the first set of memory cells is formed above the substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory, the first set of memory cells comprises a selected memory cell which is selected for programming, a plurality of unselected memory cells which are not selected for programming, a drain-side select gate comprising a drain and a control gate, and a source-side select gate; a first bit line coupled to the drain of the drain-side select gate of the first set of memory cells; a second set of memory cells which comprises a channel of an active area, a memory cell which is coupled via a selected word line to the selected memory cell, a plurality of other unselected memory cells which are coupled via a plurality of unselected word lines to the plurality of unselected memory cells, a drain-side select gate comprising a drain and a control gate, and a source-side select gate; a second bit line coupled to the drain of the drain-side select gate of the second set of memory cells; a conductive path which connects the control gate of the drain-side select gate of the second set of memory cells to the control gate of the drain-side select gate of the first set of memory cells; and circuitry coupled with the first and second sets of memory cells, the circuitry is configured to: in a program portion of a program-verify iteration: drive a voltage of the channel of the active area of the first set of memory cells and float a voltage of the channel of the active area of the second set of memory cells, during the float, increase the voltage of the channel of the active area of the second set of memory cells to a pre-charge level using gate-induced drain leakage from the drain-side select gate of the second set of memory cells and increase the voltage of the channel of the active area of the second set of memory cells from the pre-charge level to a program inhibit level using capacitive coupling, and while the voltage of the channel of the active area of the second set of memory cells is at the program inhibit level, increase a voltage of the selected word line to a programming level and maintain the voltage of the selected word line at the programming level to program the selected memory cell.