Patent ID: 6134163
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A semiconductor memory device comprising:N (N is a positive even number) units of memory banks arranged in a line in that order from the first unit in a first direction;a plurality of bit lines each extending in a second direction perpendicular to said first direction, each of bit lines arranged in a corresponding one of said memory banks;a plurality of I/O bus lines each extending in said first direction and connected to the respective bit lines of said N memory banks; anda data amplifier circuit for amplifying and outputting data on said I/O bus lines, said data amplifier circuit arranged between the N/2-th bank and the (N/2+1)-th bank of said memory banks so that said I/O bus lines are divided into first I/O bus lines and second I/O bus lines which are connected respectively to said data amplifier circuit.