Patent ID: 6069639
Filing Date: 2000-05-30
Classification: G11C

Abstract:
A graphic memory circuit having a serial data read/write access operation and a normal data read/write access operation, the serial data read/write access operation including a write data transfer cycle and a read data transfer cycle, said graphic memory circuit comprising:a memory cell array for storing serial data and normal data;a write data register coupled to said memory cell array for outputting the serial data to said memory cell array during the write data transfer cycle;a read data register coupled to said memory cell array for receiving the serial data from said memory cell array during the read data transfer cycle;a memory control signal generator for generating a plurality of internal memory control signals in response to a plurality of external control signals including graphic memory control signals and general purpose memory control signals; anda wait signal generator for generating a wait signal in response to the internal memory control signals, the wait signal being output when the graphic memory circuit is in the write data transfer cycle or the read data transfer cycle.