Patent ID: 6285582
Filing Date: 2001-09-04
Classification: B82Y,G11C

Abstract:
A multiple-valued memory system using a two dimensional memory cells each with a left (L)-terminal and a right (R)-terminal wherein the multiple-valued memory state is determined by the combination of the multiple values from the L-terminal and the R-terminal, comprising:a matrix of said memory cells,a first bank of first word line switches each connected to said L-terminal;a second bank of second word line switches each connected to said R-terminal;a left bit line switch connected to said first bank of said first word line switches;a right bit line switch connected to said second bank of second word line switches;a first set of multiple-valued data fed to said left bit line;a second set of multiple-valued data fed to said right bit line; anda left N-bit digital-to-analog converter (DAC) to provide left multiple-valued data sub-word for said left bit line, and a right N-bit DAC to provide right multiple-valued data sub-word for said right bit line during writing said memory.