Patent ID: 8120095
Filing Date: 2012-02-21
Classification: G11C,H01L

Abstract:
1. A design structure embodied in a machine readable medium, the design structure comprising: a semiconductor substrate including at least one array region that contains a plurality of trench structures having a depth from about 1 to about 2 μm, each trench structure including a select transistor having a channel located on vertical sidewalls of said trench structure, wherein at least one of the plurality of trench structures is isolated from an adjacent trench structure by a trench isolation region, wherein the trench isolation region is present overlying a portion of a conductor fill material of the select transistor that is present within each of the adjacent trench structure; a source diffusion located beneath a bottom wall of each trench structure; and a memory transistor comprising an oxide/nitride/oxide gate dielectric located on a surface of said semiconductor substrate and adjoining said selected trench structures.