Patent ID: 7831005
Filing Date: 2010-11-09
Classification: H04J,H04L

Abstract:
1. A jitter suppression circuit comprising: a data regeneration circuit regenerating input data in order to remove, to some extent, jitter components included in the input data; a pattern detection circuit detecting a predetermined signal pattern from the data regenerated by the data regeneration circuit; a reverse phase deviation generating circuit generating, when the predetermined signal pattern is detected, a reverse phase deviation signal having reverse phase deviations as jitter components corresponding to the predetermined signal pattern; and a phase deviation correcting circuit canceling a phase deviation as a jitter component of an output signal of the data regeneration circuit with the reverse phase deviation signal wherein the predetermined signal pattern comprises patterns in A wherein the pattern detection circuit determines the data regenerated by the data regeneration circuit with data obtained by delaying the regenerated data by a predetermined time and inverted data of the delayed data being made clocks, thereby acquiring two types of determined data and detecting the patterns in the A