Patent ID: 6678790
Filing Date: 2004-01-13
Classification: G06F

Abstract:
A microprocessor chip, comprising:CPU core that generates an address via an address bus and obtains data corresponding to the address via a data bus; on-chip memory that includes a tag array and a data array wherein the data array holds cache data if the on-chip memory is an on-chip cache and holds main memory data if the on-chip memory is an on-chip main memory; register that holds an indication of whether the on-chip memory is the on-chip cache or the on-chip main memory; means for loading a base address for the on-chip main memory under software control; circuit that reads a set of tag bits from the tag array and a set of data bits from the data array in response to the address; circuit that generates a cache hit signal to indicate a cache hit if a tag portion of the address matches the tag bits and generates the cache hit signal to indicate a cache miss otherwise; means for comparing the base address for the on-chip main memory to the tag portion of the address; circuit that drives the data bits from the data array onto the data bus if the on-chip memory is the on-chip cache and the cache hit signal indicates the cache hit or if the on-chip memory is the on-chip main memory and the tag portion matches the base address of the on-chip memory and not otherwise.