Patent ID: 6662306
Filing Date: 2003-12-09
Classification: G06F

Abstract:
A computer system, including:a master device configured to issue a transaction request upon an address bus; a slave device coupled to said address bus and configured to receive said transaction request in response to said master device issuing said transaction request; and a system controller coupled to said master device and said slave device via said address bus and configured to receive said transaction request in response to said master device issuing said transaction request; wherein said system controller is further configured to determine whether said slave device has available space within an associated input request queue to receive said transaction request; wherein said system controller is further configured to determine whether said slave device is an intended destination of said transaction request; and wherein said system controller, in response to determining that said slave device has available space and said slave device is an intended destination of said transaction request, is further configured to provide a signal to said slave device indicative of said transaction request being a valid transaction for said slave device to process.