Patent ID: 8421144
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. An electrically erasable programmable read-only memory, comprising: a device isolation film disposed on a predetermined region of a semiconductor substrate to define active regions; a well layer including implanted ions disposed over a surface of the semiconductor substrate having the device isolation film; a first layer of a control gate comprising a gate oxide film and polysilicon layer disposed over an electrically erasable programmable read-only memory region including the well layer; a second layer of a floating gate horizontally disposed in series on the first layer of the control gate; a third layer of a control gate horizontally disposed on the second layer of the floating gate and connected to the first layer of the control gate to enclose the second layer of the floating gate; a lightly doped drain region formed through low-concentration ion implantation after forming the third layer of the contact gate; sidewalls disposed on sides of the floating gate and the control gates, and a source region and a drain region formed by implanting high-concentration ions in the lightly doped drain region; a Ti/TiN layer formed to reduce resistance of the control gates, the floating gate, the source region and the drain region; and an interlayer insulating oxide film on a surface of the semiconductor substrate where the Ti/TiN layer has been formed.