Patent ID: 6249015
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A semiconductor device comprising:a gate electrode formed on a main surface of a semiconductor substrate;a hard mask insulating layer greater than about 120 nm thick formed on a top surface of said gate electrode;a thin insulating layer formed to cover side surfaces of said gate electrode and side and top surfaces of said hard mask insulating layer;a nitride stopper layer greater than about 40 nm thick but not greater than about 100 nm thick formed directly on said thin insulating layer to cover one side surface of said gate electrode and extend over the top surface of said hard mask insulating layer;a nitride sidewall spacer layer formed directly on said thin insulating layer to cover the other side surface of said gate electrode, the height of said nitride sidewall spacer layer in a direction perpendicular to said main surface being greater than the thickness of said gate electrode in said perpendicular direction by at least 20 nm;an interlayer insulating layer formed to cover said nitride stopper layer, having a contact hole that reaches said main surface and said nitride sidewall spacer layer, andan interconnection layer formed in said contact hole.