Patent ID: 8947135
Filing Date: 2015-02-03
Classification: G05F

Abstract:
1. An output circuit comprising: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power supply and an output node, the first PMOS transistor being connected to the side of the high potential side power supply and the second PMOS transistor being connected to the output node side; a first NMOS transistor and a second NMOS transistor connected in series between a low potential side power supply and the output node, the first NMOS transistor being connected to the side of the low potential side power supply and the second NMOS transistor being connected to the output node side; a bias voltage generation circuit configured to output a first bias voltage to a first bias node connected to a gate terminal of the second PMOS transistor and to output a second bias voltage to a second bias node connected to a gate terminal of the second NMOS transistor; a first bias voltage stabilization circuit connected to the first bias node and configured to suppress fluctuations in the first bias voltage; a second bias voltage stabilization circuit connected to the second bias node and configured to suppress fluctuations in the second bias voltage; and a control circuit configured to detect a change in a signal that fluctuates the first bias voltage and the second bias voltage and to control the operation of the first bias voltage stabilization circuit and the second bias voltage stabilization circuit.