Patent ID: 6067592
Filing Date: 2000-05-23
Classification: G06F,G11C,Y02D

Abstract:
A memory system having a master coupled to a bus to generate a request to provide data, the memory system having a plurality of memory devices, wherein each memory device is coupled to the bus and includes at least one memory section having a plurality of memory cells, the memory system comprises:a first memory device including:clock receiver circuitry, coupled to the bus, to receive a first external clock signal;a register to store a value which is representative of a number of clock cycles of the first external clock to transpire before data is output by the first memory device onto the bus in response to a request to provide data; anda second memory device including:clock receiver circuitry, coupled to the bus, to receive the first external clock signal;a register to store a value which is representative of a number of clock cycles of the first external clock signal to transpire before data is output by the second memory device onto the bus in response to a request to provide data.