Patent ID: 9063804
Filing Date: 2015-06-23
Classification: G06F

Abstract:
1. A processor comprising: one or more execution resources; a plurality of channels coupled to the one or more execution resources to store a plurality of state information corresponding to a plurality of instruction threads, each channel having a different priority and to be programmed to specify a trigger-action mapping for a scenario corresponding to an architecturally-defined event combination of events that occur during execution on the processor and associated with the channel, responsive to which a yield event is to occur to transfer execution to a yield event service routine associated with the channel, wherein the scenario comprises a code profiling scenario to identify one or more frequently executed instructions of at least one of the plurality of instruction threads and the architecturally-defined event combination is user-selected; a scenario detection unit to detect performance characteristics via interpretation of the occurrence of the architecturally-defined event combination within the processor; and a profiling unit to generate a profile of the architecturally-defined event combination, and a profile method generator to translate the profile into a method, wherein user code including the one or more frequently executed instructions of the at least one of the plurality of instruction threads is to be modified during run-time of the at least one instruction thread to optimize the user code.