Patent ID: 6728251
Filing Date: 2004-04-27
Classification: H04L,H04Q

Abstract:
In a switching apparatus comprising a centralized Switch Core (10) comprising a set of n input ports receiving cells which are routed to a set of n output ports, and at least one Switch Core Access Layer (SCAL) element for the attachment of Adapters; said Switch Core and said SCAL communicating via n parallel serial links transmitting corresponding Logical Units (LU);characterized in that each SCAL comprises: at least one input for receiving cells from said Adapter; n FIFO queues (21-25); n RAM storages, with each RAM being associated with one Logical Unit; first multiplexor (31) receiving the contents of a set of parallel busses for performing simultaneously n WRITE operations into said n RAM storages under the control of a first set of n tables (IN_Mapping tables 36-39); and second multiplexor (41) for making READ operations from said n RAM storages under control of a second set of n tables (OUT_Mapping Tables, 46-49), said first and second set of n tables having complementary control words so that the cell being conveyed through said first multiplexor, said RAM and said second multiplexor is being subject to a cell rearrangement enabling introduction of at least one bitmap field, thereby producing said Logical Units.