Patent ID: 6449196
Filing Date: 2002-09-10
Classification: G11C

Abstract:
A memory unit comprising:a plurality of memory cells arranged in the form of a matrix; word lines for selecting memory cells on the same line; bit lines for transmitting the potential levels of the memory cells selected by said word lines; a bit line pre-charge circuit for pre-charging said bit a sense amplifier circuit for amplifying the potentials of the memory cells which are read to said bit lines; bus pre-charge means for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving said bus line on the basis of a gate control signal; and a gate control circuit for transmitting said gate control signal to said tristate buffer so as not to drive said bus line when an enable signal is in an inactive state, and for transmitting said gate control signal to said tristate buffer so as to drive said bus line on the basis of the potential of said bus line and the output data of said sense amplifier circuit when said enable signal is in an active state.