Patent ID: 7719063
Filing Date: 2010-05-18
Classification: G06F,H01L

Abstract:
1. A semiconductor integrated circuit comprising a structure in which source, drain and gate electrodes of transistors included in a circuit are placed in a small-width region having a width determined from the number of routes in a set of routes having the smallest number of routes in sets of routes formed so that passage through any one of the transistors included in the circuit occurs only one time and so that the combination of routes in one set can cover the entire circuit network of the circuit, determined from the widths of source and drain electrodes of each transistor, determined from the width of the region between the source and drain electrodes, determined from the width of the region between the source or drain electrodes of some of the adjacent pairs of the transistors not combined into a common electrode, and determined from the number of the transistors included in the circuit.