Patent ID: 8344798
Filing Date: 2013-01-01
Classification: H03F,H03G

Abstract:
1. A switched-capacitor gain stage circuit having an input node and an output node, the circuit comprising: an operational amplifier having a first amplifier input, a second amplifier input, and an amplifier output coupled to the output node; a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node; an offset storage capacitor having a first terminal coupled to the first amplifier input; and a switching configuration having multiple switches that are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state, wherein, in the sampling state, the multiple switches are configured so that a first charge component representing an input signal on the input node is stored on the sampling capacitors, and a second charge component representing an amplifier offset voltage is stored on the offset storage capacitor, in the gain state, the multiple switches are configured so that a third charge component representing a finite gain of the amplifier is stored on the offset storage capacitor, and in the output state, the multiple switches are configured so that the first, second, and third charge components contribute to an output signal produced at the output node.