Patent ID: 6133131
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method for forming a spacer of a gate on a semiconductor wafer, the gate being protruded over a surface of the semiconductor wafer and having a top end and a side wall, the semiconductor wafer having at least one field oxide region on its surface which is located in proximity to the gate for electrically isolating the gate, the method comprising:forming a first dielectric layer on the semiconductor wafer to cover the gate and the field oxide region wherein the first dielectric layer above the top end of the gate is thicker than the first dielectric layer above the field oxide region;forming a second dielectric layer on the first dielectric layer to create a flat surface on the semiconductor wafer;performing a first etching process to reduce the thickness of the second dielectric layer from the flat surface to a predetermined thickness which also reduces the thickness of the first dielectric layer above the top end of the gate;performing a second etching process to remove the second dielectric layer completely; andperforming an anisotropic etching process to remove the first dielectric layer above the top end of the gate and form a spacer on the side wall of the gate.