Patent ID: 6537885
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A method of manufacturing a transistor from a wafer having gate structures on the wafer, comprising the steps of:depositing a first spacer on the wafer and around the gate structures, and then etching the first spacer from the wafer such that the first spacer remains around the gate structures; growing a first silicon epitaxial layer on the wafer; depositing a second spacer on the first silicon epitaxial layer and around the gate structures, and then etching the second spacer from the first silicon epitaxial layer such that the second spacer remains around the gate structures; growing a second silicon epitaxial layer on the first silicon epitaxial layer; etching the second spacer from around the gate structures; implanting ions to create a first, a second, a third and a fourth junction area; depositing a third spacer on the second silicon epitaxial layer and around the gate structures, and etching the third spacer from the second silicon epitaxial layer such that the third spacer remains around the gate structures; and implanting ions to create a fifth and a sixth junction area.