Patent ID: 6501683
Filing Date: 2002-12-31
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell including a floating gate and a control gate that are formed over a semiconductor substrate; a charge buildup damage reducer connected to the control gate; and damage reducer control means connected to the damage reducer, wherein the damage reducer controls a potential level at the control gate so that the potential level falls within a predetermined voltage range even if charge buildup occurs in the control gate during a metallization process, wherein the control means allows no current to flow through the damage reducer while the memory cell is being written, read or erased, wherein the damage reducer is a diode including first and second electrodes, the first electrode being connected to the control gate, and wherein the control means is connected to the second electrode of the diode and changes a voltage applied to the second electrode depending on whether the memory cell is being written, read or erased.