Patent ID: 6307249
Filing Date: 2001-10-23
Classification: H01L

Abstract:
An integrated circuit, comprising:an anti-fuse formed on a surface of a silicon substrate of a first conductivity type, the anti-fuse having a dielectric layer formed between a first polysilicon layer and a second polysilicon layer, the first polysilicon layer contacted by a first metal layer forming a first terminal of the anti-fuse and the second polysilicon layer including a portion extending beyond the dielectric layer above and substantially parallel to the surface of the substrate to which a second metal layer forming a second terminal of the anti-fuse is contacted, the anti-fuse including a well region of an expected depth formed in the silicon substrate under the portion of the second polysilicon layer to which the second metal layer is contacted, the well region having a second conductivity type opposite the first conductivity type and further having a shallower more lightly doped region of the second conductivity type formed therein; anda programming circuit having first and second input terminals adapted to receive first and second programming voltages, respectively, and having first and second output terminals coupled to the first and second terminals of the anti-fuse, respectively, the programming circuit operable to program the anti-fuse by coupling the first and second input terminals to the first and second output terminals to thereby apply the first and second programming voltages to the first and second polysilicon layers.