Patent ID: 6553557
Filing Date: 2003-04-22
Classification: G06F

Abstract:
An inter-functional-block restriction high-speed extraction method of converting, according to a top restriction describing boundary conditions and optimizing conditions of boundary sections between units for a logic circuit described at a register transfer level, the register-transfer-level logic circuit into a gate-level logic circuit and of optimizing the gate-level logic circuit, comprising the following steps of:extracting boundary sections from the logic circuit described at a register transfer level; conducting logic synthesis only for the boundary sections extracted; extracting a timing restriction according to a design of each of the boundary sections resultant from the logic synthesis; and conducting logic synthesis at a unit level when no timing violation is detected according to the timing restriction extracted and/or conducting logic synthesis at a unit level when a timing violation is detected according to the timing restriction extracted, the logic synthesis using the timing restriction as an input thereto; extracting a timing restriction according to a design of the boundary section resultant from the logic synthesis; and determining whether or not a timing violation is detected according to the timing restriction extracted.