Patent ID: 8243540
Filing Date: 2012-08-14
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array outputting at least one of a first and a second data group at a first data rate; an output circuit, wherein the output circuit, in a normal mode of operation, serially outputs at least one of the first and the second data group at the first data rate, and in a first test mode outputs the first data group at a second data rate, in a second test mode outputs the second data group at the second data rate, and in a third test mode outputs the first data group or the second data group at the second data rate in response to at least one control signal; and a test mode set circuit outputting a first, a second and a third test mode signal for respectively determining the first, second and third test mode of the output circuit, in response to a plurality of input signals, wherein the output circuit includes,