Patent ID: 6349366
Filing Date: 2002-02-19
Classification: G06F

Abstract:
A memory management system coupling a plurality of processors each processor having an associated cache, to each other and to a main memory, comprising:a system port configured to receive a request from a first processor of the plurality of processors to access a block of data from the main memory; a memory manager configured to convert the request into a probe command having a data movement part identifying a condition for movement of the block of data out of a cache of a second processor of the plurality of processors the condition for movement being one of read if hit and read if dirty, and a next coherence state part indicating a next state of the block in the cache, and wherein the memory manager is further configured to present the probe command over the system port to the second processor so that the second processor changes a state of the block of data in the cache of the second processor in accordance with the next coherence state part of the probe command.