Patent ID: 6175851
Filing Date: 2001-01-16
Classification: G06F

Abstract:
A method for performing one from a group of an addition operation and a subtraction operation upon a first floating point number comprising a signal having a first sign portion, a first exponent portion, and a first mantissa portion, and a second floating point number comprising a signal having a second sign portion, a second exponent portion, and a second mantissa portion, the method being implemented in a computer and permitting the computer to increase in efficiency and speed during the addition operation or subtraction operation, the method comprising:generating an exponent portion difference signal;generating a magnitude comparison signal that consistently indicates whether the magnitude of the first floating point number is less than that of the second floating point number;performing a first set of mantissa portion alignment operations in parallel with generation of the exponent portion difference signal, with generating the magnitude comparison signal, and with at least one of a one's complement operation and bit position shift operation on one of the first mantissa portion and the second mantissa portion, wherein the step of performing the first set of mantissa portion alignment operation comprises: receiving a first selector input signal including a one's complement of the first mantissa portion with a logic high value appended to the least significant bit of the first mantissa portion, receiving a second selector input signal including the first mantissa portion with a logic low value inserted before the most significant bit of the first mantissa portion, receiving a third selector input signal including a one's complement of the first mantissa portion with a logic high value inserted before the most significant bit of the first mantissa portion, and receiving a fourth selector input signal including the first mantissa portion with two logic low values inserted before the most significant bit of the first mantissa portion, the fourth selector input signal having the least significant bit of the first mantissa portion truncated;wherein the step of performing the first set of mantissa portion alignment operation further comprises: receiving a fifth selector input signal including a one's complement of the second mantissa portion with a logic high value appended to the least significant bit of the second mantissa portion, receiving a sixth selector input signal including the second mantissa portion with a logic low value inserted before the most significant bit of the second mantissa portion, receiving a seventh selector input signal including a one's complement of the second mantissa portion with a logic high value inserted before the most significant bit of the second mantissa portion, and receiving an eight selector input signal including the second mantissa portion with two logic low values inserted before the most significant bit of the second mantissa portion, the eight selector input signal having the least significant bit of the second mantissa portion truncated;performing an addition operation; andoutputting a resulting floating point signal comprising a resulting sign portion, a resulting exponent portion, and a resulting mantissa portion, the resulting floating point signal corresponding to one from the group of a sum of the first and second floating point numbers and a difference between the first and second floating point numbers.