Patent ID: 8987810
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A semiconductor device including a transistor formation region of a semiconductor substrate and a peripheral region of the semiconductor substrate, comprising: a first semiconductor layer of a first conductive type formed in the semiconductor substrate; a second semiconductor layer of a second conductive type opposite to the first conductive type formed in the first semiconductor layer of the transistor formation region of the semiconductor substrate; a third semiconductor layer of the first conductive type formed in the second semiconductor layer; a first trench formed in the first, second and third semiconductor layers such that a bottom of the first trench is located in the first semiconductor layer; a gate electrode formed inside the first trench; a contact hole formed in the second and third semiconductor layers such that a bottom of the contact hole is located in the second semiconductor layer; a source wiring formed in the contact hole and connected to the second and third semiconductor layers; a field insulating film formed over the peripheral region of the semiconductor substrate; a well region of the second conductive type formed in the peripheral region of the semiconductor substrate; a second trench formed in the well region and the first semiconductor layer such that a bottom of the second trench is located in the first semiconductor layer; and a gate wiring formed inside the second trench, wherein the well region is connected to the second semiconductor layer, wherein at least a part of the well region is formed under the field insulating film, and wherein the well region contacts the second trench.