Patent ID: 8683135
Filing Date: 2014-03-25
Classification: G06F

Abstract:
1. An apparatus, comprising: a data cache; an execution core coupled to the data cache, wherein the execution core is configured to receive an instance of a first type of prefetch instruction that includes information usable to specify a memory address in a memory; an image signal processor coupled to the memory; a camera coupled to the image signal processor, wherein the camera is configured to provide image data to the image signal processor, wherein the image signal processor is configured to process the image data from the camera and is further configured to store the processed image data to the memory; wherein, in response to receiving the instance of the first type of prefetch instruction, the execution core is configured to use the memory address to retrieve the processed image data from the memory and store the retrieved image data in the data cache, whether or not data corresponding to that memory address is already stored in the data cache; wherein the execution core is further configured to further process the retrieved data and store the further processed data back to the memory; and video circuitry configured to: wherein the data cache, the execution core, the image signal processor, the memory, the camera, and the video circuitry are part of a single device.