Patent ID: 6359828
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A column address decoder of a semiconductor memory device for decoding column addresses to enable a corresponding column select line, the column address decoder comprising:a column address pre-decoder for latching combinations of the column addresses when a column select line enable signal is in a first level, and outputting the latched result as pre-decoded column addresses when the column select line enable signal is in a second level; and wherein the column address pre-decoder comprises a first decoding unit through an Nth decoding unit for pre-decoding the input column addresses; and each of the first decoding unit through the Nth decoding unit comprises: a first inverting and logical AND means for inverting and logical ANDs at least two signals of the column addresses and inverted column addresses; a transmission gate for transmitting the output of the first inverting and logical AND means in response to the column select line enable signal; a latch for latching the signal transmitted through the transmission gate and outputting the latched result; a second inverting and logical AND means for inverting and logical AND the output signal of the latch and the column select line enable signal, and outputting the inverted and logical ANDed signal; and an inverter for inverting the output of the second inverting and logical AND means and outputting the inverted result as the pre-decoded column address.