Patent ID: 7467325
Filing Date: 2008-12-16
Classification: G06F

Abstract:
1. A method for recovery of a processor core in a chip of a symmetric multiprocessing system, the chip having a processor core and a host firmware for supervising resource allocation and error recovery, comprising the steps of: providing a clock signal to recovery circuits; blocking checkpointing of the processor core; quiescing a cache functional unit; establishing a coherent checkpoint in response to quiescing the cache functional unit; logically removing the processor core from the symmetric multiprocessing system in response to quiescing the cache functional unit and establishing a coherent checkpoint; resetting the processor core; restoring a nearest checkpoint to the processor core after resetting the processor core; indicating an interrupt in response to restoring a nearest checkpoint; executing a preprogrammed number of instruction groups in a reduced execution mode; and executing at least one instruction group in a normal execution mode.