Patent ID: 6407898
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A protection means for preventing power-on sequence induced latch-up, the protection means being for use in a power supply system having a first power supply and a second power supply wherein the voltage of the first power supply is higher than that of the second power supply, the protection means comprising:a voltage-drop circuit having an input terminal and an output terminal, the input terminal being connected to the first power supply; an inverter having an input terminal and an output terminal, the input terminal being connected to the output terminal of said voltage-drop circuit; a switching NMOS transistor with the gate connected to the output terminal of said inverter and the source connected to ground; and a variable capacitance circuit having a first capacitor and a second capacitor, the capacitance of the first capacitor being much larger than that of the second capacitor, the first terminal and the second terminal of the first capacitor being connected to the second power supply and the first terminal of the second capacitor respectively, the second terminal of the second capacitor being connected to ground, the common node of the second terminal of the first capacitor and the first terminal of the second capacitor being connected to the drain of said switching NMOS transistor, wherein said switching NMOS transistor and said variable capacitance circuit are formed on the same semiconductor substrate.