Patent ID: 6272667
Filing Date: 2001-08-07
Classification: G06F

Abstract:
A computer aided design system for clock gated logic circuits comprising:a circuit information storing section for storing information about a clock gated logic circuit under the design;a halt condition determination section for determining, by the use of said information about the clock gated logic circuit, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied;an enable signal candidate generation section for generating enable signal candidates, from said halt condition, which can be used as enable signals in the clock gated logic circuit;an analysis section provided to analyze the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidate is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design;an enable signal candidate information storing section provided to store enable signal candidate information including the result of the analysis conducted by said analysis section;a design restriction input section provided to input delay time limitations upon a delay time of signal transmission of the clock gated logic circuit under the design;an enable signal selection section provided to select an appropriate one of the enable signal candidates which satisfy the delay time limitations, by the use of said enable signal candidate information and said delay time limitations information; anda clock gating circuit addition section provided to add a clock gating circuit activated with the enable signal as selected by said enable signal selection section to the clock gated logic circuit under the design.