Patent ID: 6323097
Filing Date: 2001-11-27
Classification: G01B,H01L

Abstract:
A method to measure spacing and misalignment comprising:providing a partially processed semiconductor wafer containing a first insulating layer;forming three equally spaced, parallel first level conductive lines on said first insulating layer with staircase patterns projecting both out of and into the inner edges of the outer lines;depositing a second insulating layer;opening step contact vias through said second insulating layer over the steps of said staircase patterns such that for each said step the inner edge of said step contact via coincides with the inner edge of said step;opening contact pad vias through said second insulating layer over said outer lines;filling the step contact vias and the contact pad vias with conductive material;forming a second level conductive line over said second insulating layer parallel to said first level conductive lines and over central of said first level conductive lines;forming resistor ladder patterns projecting from both edges of said second level conductive line the rungs of said ladder patterns being of equal length and being composed of rung conductive sections with a resistor section interposed;forming the center conductor contact pad electrically connected to said second level conductive line;forming the right conductor contact pad over said contact pad via through the second insulator layer to the right said outer first level line;forming the left conductor contact pad over said contact pad via through the second insulator layer to the left said outer first level line;measuring the resistance between the center conductor pad and the right conductor pad, inferring from this the rungs of said resistor ladder pattern projecting from right edge of second level conductive line that make contact with said step contact vias of said outer first level conductive line on the right, and determining the bounds for the distance, SR, from said right outer first level conductive line to said second level conductive line;measuring the resistance between the center conductor pad and the left conductor pad, inferring from this the rungs of said resistor ladder pattern projecting from left edge of second level conductive line that make contact with said step contact vias of said outer first level conductive line on the left, and determining the bounds for the distance, SL, from said left outer first level conductive line to said second level conductive line;calculating the bounds for the spacing of said first level conductive lines from (SR+SL)/2;calculating the misalignment between the central said first level conductive line and said second level conductive line from (SR-SL)/2.