Patent ID: 6247104
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A memory access control circuit for conducting an interleave control that, between an access request and a data transfer for the access request, another access request and data transfer are inserted while said memory access control circuit is disposed between a memory and a master device to issue an access request to the memory, comprising:means for judging whether the access request can be interleaved or not;means for selecting whether to conduct the interleave control or not according to the judgement result of said judging means;means for dividing said access request into a plurality of access requests while extracting data corresponding to said plurality of access requests; andfrequency-difference buffering means for allowing the writing to the memory to synchronize with a first clock frequency with which said master device is operated and allowing the reading from the memory to synchronize with a second clock frequency with which a data transfer of the memory is synchronized,wherein said judging means judges said interleave control to be enabled when at least two access requests exist and are a write or read request to the memory, andwherein said first and second frequencies are different from each other.