Patent ID: 8270192
Filing Date: 2012-09-18
Classification: G11C

Abstract:
1. A circuit arrangement having a memory cell array comprising a plurality of memory circuits, each of the plurality of memory circuits comprising: a non-volatile memory cell which is inserted in a first current path between a supply voltage terminal and a reference potential terminal and comprises a non-volatile memory element; a volatile memory cell which is inserted in a second current path between the supply voltage terminal and the reference potential terminal and comprises a first inverter, a second inverter in feed-back arrangement with the first inverter, and an address transistor inserted between an input of the first inverter and a bit line, the volatile memory cell being coupled to the non-volatile memory cell for reading and programming the non-volatile memory element; a reading transistor coupling the non-volatile memory cell to a measuring line; and a connection line between the volatile memory cell and the non-volatile memory cell such that, in cases of a program instruction, information stored in the volatile memory cell is stored in the non-volatile memory cell; wherein the circuit arrangement further comprises a comparator coupled between the non-volatile memory cell and the volatile memory cell so that an input of the comparator is connected to the measuring line and an output of the comparator is connected to the bit line, the comparator holding several threshold values and being configured to selectively compare a measuring signal of the measuring line with one of the several threshold values.