Patent ID: 6642134
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method of manufacturing a CMOS semiconductor device, which method comprises:forming a dielectric layer on a surface of a semiconductor substrate; forming a conductive layer on the dielectric layer; patterning the conductive layer to form a gate electrode having an upper surface and side surfaces; depositing an insulating layer; etching the insulating layer to form first sidewall spacers on the side surfaces of the gate electrode; depositing a semiconducting layer; etching the semiconducting layer to form second sidewall spacers on the first sidewall spacers; depositing a metal on the first and second sidewall spacers, the gate electrode, and the surface of the semiconductor substrate; and annealing to form silicide on the gate electrode, the second sidewall spacers and the semiconductor substrate, the second sidewall spacers being at least partially consumed during the annealing and substantially preventing silicon consumption in the semiconductor substrate below the second sidewall spacers.