Patent ID: 7584316
Filing Date: 2009-09-01
Classification: G06F

Abstract:
1. In an integrated circuit multiprocessor switching device, an apparatus for mapping a plurality of interrupts and a plurality of virtual channels through a packet manager to route data packets between external devices and a plurality of processors, comprising: an interrupt status register for storing the interrupts; mask registers associated with the virtual channels for selectively masking contents of the interrupt status register for each of the virtual channels, the virtual channels for routing the data packets; a merged interrupt indication register associated with each virtual channel for storing masked interrupt values for the virtual channels that are obtained after masking and merging the contents of the interrupt status register with the mask registers; an interrupt mapping register associated with each virtual channel for storing a processor identification for routing masked interrupt value of a respective virtual channel to a selected processor of the plurality of processors; a demultiplexing circuit coupled to the merged interrupt indication register and the interrupt mapping register for coupling the masked interrupt value for each virtual channel to a corresponding one of the selected processors to selectively route the masked interrupt values in the packet manager.