Patent ID: 7391234
Filing Date: 2008-06-24
Classification: H04L

Abstract:
1. A circuit comprising: one or more operation elements executing numerical value operation or a logical operation for digital data to be inputted and outputting results of the numerical value operation or the logical operation, network output terminals connected to an input side of said operation elements, network input terminals to which the output signals of said operation elements or external signals other than the output signals of said operation elements are inputted, and a network structure connecting said network input terminals to said network output terminals, wherein said network structure configures a blocking network having a constraint against a combination of said network input terminal and said network output terminal, the constraint limiting further connection of, upon connecting a first network input terminal to a first network output terminal, second network input terminal to any one of second network output terminals, and said one or more operation elements and said network output terminals are connected so as to minimize a constraint strength between said plurality of network output terminals for inputting to said same operation element with respect to the constraint strength defined as the number of network input terminals contained in tuples of network input terminals to which two network output terminals in said network output terminals can not be simultaneously connected.