Patent ID: 6310490
Filing Date: 2001-10-30
Classification: H03K,H04L

Abstract:
A CMOS terminator circuit for connection to a network carrying small logic level signals from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said network's first circuit to said network's second circuit, comprising:the terminator circuit (21) including a terminator reference circuit (30) generating logic `1` and logic `0` reference voltage levels and being coupled to a terminator input circuit (31) in said terminator circuit having a first and a second control device, and wherein said terminator circuit has an adjustment section for adjusting the impedance and voltage of the terminator circuit and is switchable from a first state to a second state by a switching control signal (91) supplied to said reference circuit and to said input circuit (31), said terminator input circuit being coupled to said network's input terminal (10) for connecting the network's first circuit to the network's second circuit,said reference circuit being tuned to a voltage level equal to the center of an adjustable incoming voltage swing between said logic `1` and `0` voltage levels of said reference circuit and coupled to one input of said differential receiver circuit (24) to provide to said differential receiver circuit a stable and well centered threshold voltage, said differential receiver having another differential receiver input which is coupled to the network input terminal for connecting the network's first circuit to the network's second circuit.