Patent ID: 6537882
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A method for preparing a semiconductor device comprising the steps of:(a) forming a gate insulation layer and a gate conductive layer in an active region on a surface of one conductivity type semiconductor substrate; (b) selectively removing said gate conductive layer to form a gate electrode for a first MOSFET group of one conductivity type in a peripheral circuit region while leaving a gate conductive layer portion corresponding to a second MOSFET group of one conductivity type in a memory cell region; (c) forming an insulation layer for the formation of sidewalls on a whole surface of said gate conductive layer portion, of said peripheral circuit region, and of said gate electrode; (d) etching back the insulation layer to form a side wall on each side of said gate electrode in the peripheral circuit region while protecting a surface of said semiconductor substrate in the memory cell region by said gate conductive layer portion; and (e) selectively removing the remaining gate conductive layer portion to form a gate electrode for the second MOSFET group of one conductivity type in the memory cell region, said gate electrode for said second MOSFET group having no side walls; wherein the semiconductor device comprises a pattern having a dense region and a sparse region in the same layer, and the pattern formation is carried out separately in the dense region and the sparse region.