Patent ID: 7456087
Filing Date: 2008-11-25
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a gate oxide layer and a gate conductive layer sequentially on a substrate; forming a gate structure by defining the gate conductive layer and the gate oxide layer; forming a spacer on the sidewalls of the gate structure; forming two openings in the substrate beside both sides of the spacer and a portion extending to a region below the spacer; forming a first SiGe layer being boron-doped and a second SiGe layer being boron-doped sequentially on the openings, wherein the top of the second SiGe layer is higher than the surface of the substrate and the boron concentration in the first SiGe layer is lower than that in the second SiGe layer; and wherein the amount of germanium in the first SiGe layer is greater than that in the second SiGe layer, wherein the amount of germanium in the first SiGe layer is greater than that in the second SiGe layer.