Patent ID: 9040832
Filing Date: 2015-05-26
Classification: H01L,H05K

Abstract:
1. A wiring substrate, comprising: a first insulating resin layer; a first coupling agent layer formed on the first insulating resin layer; a first wiring layer including a first copper tin alloy layer formed on the first coupling agent layer, a copper layer formed on the first copper tin alloy layer, a seed layer formed on the copper layer, and a metal plating layer formed on the seed layer; and an underlayer wiring layer formed under the first insulating resin layer, a via hole being formed in the first insulating resin layer to reach the underlayer wiring layer, wherein the first coupling agent layer is formed on the first insulating resin layer except the via hole, and wherein the seed layer is formed to extend from an inner surface of the via hole onto the copper layer, and the first wiring layer is connected to the underlayer wiring layer via the via hole.