Patent ID: 6121109
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method of forming a layer of hemispherical grain polysilicon over the lower electrode of a capacitor, the method comprising the steps of:providing a substrate that has a field effect transistor already formed thereon, wherein the field effect transistor at least includes a source/drain region;forming an insulating layer over the substrate;patterning the insulating layer to form a contact opening that exposes the source/drain region;forming a polysilicon layer over the insulating layer filling the contact opening;forming a thin buffer layer over the polysilicon layer prior to patterning the polysilicon layer;patterning the thin buffer layer so that a portion of the polysilicon layer, which is to become the lower electrode of the capacitor, is covered, while the remaining portion of the polysilicon layer is exposed;performing a plasma etching operation using the patterned thin buffer layer as a buffer so that the thin buffer layer and the exposed portion of the polysilicon layer are removed at the same time; andperforming a heat treatment process to covert the polysilicon on the surface of the polysilicon layer into hemispherical grain polysilicon.