Patent ID: 7355446
Filing Date: 2008-04-08
Classification: H03K

Abstract:
1. A voltage conversion circuit, comprising: an input terminal receiving an input signal of a first voltage; an output terminal generating an output signal of a second voltage; and first and second level-shifting units connected between the input and output terminals, wherein the first and second level-shifting units have different transition delay characteristics from each other so that rising and falling transition delays of the output signal are varied in the same rate when the first and second voltages are changed, wherein when the first voltage is higher than the second voltage and the input signal goes to high level from low level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘FFF’ and the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘FSS’, wherein the ‘F’ represents a fast transition delay of a MOS transistor based on a gate-source voltage and the ‘S’ represents a slow transition delay of a MOS transistor based on a gate-source voltage.