Patent ID: 6724685
Filing Date: 2004-04-20
Classification: G11C

Abstract:
A configuration for transmitting data in a semiconductor memory system, the configuration comprising:at least one semiconductor memory module; a memory controller controlled by a system clock signal, said memory controller having a clock generating device producing a sense clock signal in addition to the system clock signal, the data being transmitted between said memory controller and said semiconductor memory module; a clock line connected between said semiconductor memory module and said memory controller, said clock line transmitting the system clock signal to said memory module; and at least one separate sense clock line extending from said memory controller to said semiconductor memory module and directly back to said memory controller, said separate sense clock line transmitting the sense clock signal to said semiconductor memory module and from said semiconductor memory module back to said memory controller; said memory controller further having a propagation time measuring device connected to said separate sense clock line for measuring a propagation time of the sense clock signal transmitted over said separate sense clock line and a delay time adjusting device connected to said propagation time measuring device, said delay time adjusting device adjusting a delay time corresponding to the propagation time needed by the data transmitted from said semiconductor memory module to said memory controller, said memory controller adjusting the delay time of said delay time adjusting device in accordance with the propagation time, measured by said propagation time measuring device, of the sense clock signal transmitted over said separate sense clock line.