Patent ID: 6753734
Filing Date: 2004-06-22
Classification: G05F,H03F

Abstract:
A circuit for biasing an RF amplifying transistor, the circuit comprising:A. a composite master transistor connected to the RF amplifying transistor in a current-mirror configuration, the composite master transistor comprising at least two transistor elements; B. a buffering transistor having a control terminal connected to a current-sink terminal of the master transistor and providing an output connected to control terminals of the composite master transistor and the RF amplifying transistor and the current-sink terminal of the RF amplifying transistor; and C. a switch connected to at least one of the at least two transistor elements, wherein in a first state, the switch disables one of the at least two transistor elements, thereby rendering the composite master transistor suitable to bias the RF amplifying transistor at a first operating point, and in a second state, the switch enables one of said at least two transistor elements, thereby rendering the master transistor suitable to bias the RF amplifying transistor at a second operating point.