Patent ID: 6720754
Filing Date: 2004-04-13
Classification: G05F

Abstract:
A voltage regulator for controlling a current flowing into an output voltage terminal in accordance with an output voltage, comprising:a first MOS transistor having a first conductivity type in which a source terminal thereof is connected with an input voltage terminal and a drain terminal thereof is connected with the output voltage terminal; a differential amplifying circuit having two input terminals in which an output terminal thereof is connected with a gate terminal of the first MOS transistor; a first reference voltage source which is connected between one of the input terminals of the differential amplifying circuit and a ground terminal and in which an output terminal thereof is connected with the one input terminal of the differential amplifying circuit; a voltage dividing circuit which is connected between the output voltage terminal and the ground terminal and in which an output voltage terminal thereof is connected with the other input terminal of the differential amplifying circuit; a second MOS transistor having the first conductivity type in which a gate terminal and a source terminal thereof are connected with the gate terminal and the source terminal of the first MOS transistor, which are common to each other, respectively; a first resistor connected between the output voltage terminal and a drain terminal of the second MOS transistor; an MOS transistor having a second conductivity type in which a source terminal thereof is connected with the output voltage terminal, a gate terminal thereof is connected with the drain terminal of the second MOS transistor, and a base terminal thereof is connected with the ground terminal; a second resistor connected between the input voltage terminal and a drain terminal of the MOS transistor having the second conductivity type; a third MOS transistor having the first conductivity type in which a source terminal thereof is connected with the input voltage terminal, a gate terminal thereof is connected with the drain terminal of the MOS transistor having the second conductivity type, and a drain terminal thereof is connected with the gate terminal of the first MOS transistor; a third resistor connected between the first resistor and the output voltage terminal; and a fourth MOS transistor having the first conductivity type in which a drain terminal and a source terminal thereof are connected with the third resistor in parallel, wherein a voltage of a gate terminal of the fourth MOS transistor is a voltage lower than a specified output voltage.