Patent ID: 9082717
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a first groove and an insulation layer filling the first groove, wherein the first groove is embedded into a semiconductor substrate and includes a top portion and a bottom portion, wherein the top portion is surrounded by a first sidewall, wherein the bottom portion is surrounded by a second sidewall and includes a bottom surface, wherein the first sidewall, the second sidewall, and the bottom surface are arranged along a thicknesses direction of the semiconductor substrate; and wherein in any cross-sectional plane perpendicular to the semiconductor substrate, the second sidewall has a cross-section view with an arc profile or a fold-line profile, wherein an angle between the first sidewall and a normal line of the semiconductor substrate is larger than an angle between the second sidewall and the normal line of the semiconductor substrate; and a source/drain (S/D) region, wherein the S/D region comprises a second groove and a semiconductor layer filling the second groove, wherein the material of the semiconductor substrate is interposed between the first groove and the second groove in both a length direction and a width direction of a gate.