Patent ID: 9099488
Filing Date: 2015-08-04
Classification: G01N,H01L

Abstract:
1. A method for screening gate stacks, the method comprising providing a semiconductor substrate; forming a first oxide layer on the substrate; defining a plurality of site-isolated regions (SIRs) on the first oxide layer; patterning the first oxide layer in each SIR to form an active area on a surface of the substrate within each SIR; applying a first surface treatment to at least one of the SIRs in a combinatorial manner; forming a second oxide layer on the treated active area within each SIR; etching the second oxide layer within each SIR, forming a high-k dielectric layer on the second oxide layer within each SIR; forming a metal layer on the high-k dielectric layer within each SIR; patterning the metal layer to form metal electrodes, measuring an electrical parameter of the capacitor device formed within each SIR;