Patent ID: 8412891
Filing Date: 2013-04-02
Classification: G06F,Y02D

Abstract:
1. A memory access device for allowing a shared memory to be used both as a buffer for data flows and as a main memory for a processor, the device comprising a memory, a plurality of functional blocks each of which handles a data flow from and to the memory, a processor which uses the memory as a main memory, and an arbiter unit which arbitrates among accesses to the memory from the functional blocks and the processor, wherein the arbiter unit: makes assignment for access requests to the memory from the plurality of functional blocks in units of predetermined transfer lengths sequentially in a round-robin fashion, divides each of data transfers from the functional blocks into transfer blocks of a predetermined transfer length (transfer block length), and transfers the transfer blocks in one round-robin cycle in accordance with bandwidths required for the data transfers from the functional blocks, sets a priority of each of the plurality of transfer blocks of the data transfers in a programmable way so that the transfer blocks from the functional blocks have different priorities and that the bandwidths required for the data transfers from all the functional blocks are met by alternate transfer of the transfer blocks from the different functional blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined processor transfer length exerts less effect on bandwidths for data flow transfers from the functional blocks in predetermined intervals between the transfer blocks.