Patent ID: 6400199
Filing Date: 2002-06-04
Classification: H03K

Abstract:
A fully differential double edge triggered flip-flop, storing and outputting first and second fully differential input values on leading and trailing edges of a clock, comprising:a first fully differential master circuit storing the first fully differential input value on the leading edge of the clock; a second fully differential master circuit storing the second fully differential input value on the trailing edge of the clock; and a fully differential slave circuit electrically connected to outputs of the first and second fully differential master circuits, said fully differential slave circuit including a first repeater as an output end of said fully differential double edge triggered flip-flop; said fully differential slave circuit outputting said first fully differential input value during the period from the leading edge to trailing edge of the clock, and outputting said second fully differential input value during the period from the trailing edge to leading edge of the clock.