Patent ID: 6347360
Filing Date: 2002-02-12
Classification: G06F

Abstract:
An apparatus for protecting cache data from eviction during an atomic operation comprising:a first request queue storing an entry for each cache access request, each entry of the first request queue including a first set of address bits and an atomic bit, the first set of address bits indicating a first cache address associated with the cache access request, the atomic bit indicating whether the cache access request is associated with the atomic operation; a second request queue storing an entry for each cache eviction request, each entry of the second request queue including a second set of address bits indicating a second cache address associated with the cache eviction request; and an atomic address block preventing eviction of a third cache address during the atomic operation on the third cache address, during a first clock cycle the atomic address block receiving a first set of signals representing a first entry of the first request queue, and analyzing the first set of signals to determine whether they represent the atomic operation and, if so, setting a third set of address bits to a value representative of the first cache address, during a second clock cycle during which the atomic operation is being executed the atomic address block receiving and analyzing a second set of signals representing the second set of address bits to determine whether the second set of address bits represent a same cache address as the third set of address bits and, if so, stalling servicing of the second request queue.