Patent ID: 6223432
Filing Date: 2001-05-01
Classification: H01L,Y10T

Abstract:
A method of fabricating conductive plugs in a memory array comprising the steps of:providing a silicon substrate with at least one gate interconnect including a protective cap overlying a gate layer, active areas of a first and a second conductivity type, and at least one word line;forming a protective layer atop said substrate;defining at least one set of first and second plug openings in said protective layer, wherein said first opening outwardly exposes the active area of the first conductivity type, and wherein said second opening outwardly exposes the protective cap of said gate interconnect;forming a first conductive layer on the surface of the protective layer of a depth at least sufficient to fill the first and second plug openings;defining at least one third plug opening in said protective layer and said first conductive layer, wherein said third opening outwardly exposes the active area of the second conductivity type;redefining the second plug opening in said protective layer and said first conductive layer, wherein redefining said second opening outwardly exposes the gate layer of said gate interconnect;forming a barrier film inside the second and third plug openings;forming a second conductive layer on the surface of the first conductive layer and the barrier film of a depth at least sufficient to fill the second and third plug openings; andisolating the first conductive layer in the first plug opening, and the second conductive layer in the second and third plug openings to form isolated conductive plugs in each plug opening.