Patent ID: 6748509
Filing Date: 2004-06-08
Classification: G06F,G11C

Abstract:
A memory component operated as a slave to an external master, the memory component comprising:a random access storage array having a plurality of storage locations; data format logic for the selective formatting of data transfers between the array and the external master in accordance with one of a plurality of transfer-sequence-length formats, the bit values of the data being preserved during the formatting; a plurality of configuration bits in at least one configuration register, the configuration bits specifying one of the plurality of formats; control logic coupled to the storage subsystem, the data format logic, and the configuration bits, the control logic generating the selectively formatted data transfers in accordance with the configuration bits; and wherein the random access storage array, the data format logic, the configuration bits, and the control logic are all embodied on a single integrated circuit having a plurality of pins for coupling to the external master.