Patent ID: 6421534
Filing Date: 2002-07-16
Classification: H03D,H04B

Abstract:
An apparatus for filtering and down-converting, comprising:(1) a first adder that includes a filtered and down-converted signal output port; (2) a frequency translator comprising: (a) a first switch that includes a first port coupled to an input signal and a second port coupled to a first control signal; (b) a first buffer that includes an input port coupled to a third port of said first switch; (c) a first capacitor that includes a first terminal coupled to said input port of said first buffer, wherein said first capacitor includes a second terminal coupled to a voltage reference; (d) a second switch that includes a first port coupled to an output port of said first buffer and a second port coupled to a second control signal; (e) a second buffer that includes an input port coupled to a third port of said second switch and an output port coupled to a first input port of said adder; and (f) a second capacitor that includes a first terminal coupled to said input port of said second buffer, wherein said second capacitor includes a second terminal coupled to a voltage reference, (3) a delay module, comprising: (a) a third switch that includes a first port coupled to said output port of said adder and a second port coupled to said first control signal; (b) a third buffer that includes an input port coupled to a third port of said third switch; (c) a third capacitor that includes a first terminal coupled to said input port of said third buffer, wherein said third capacitor includes a second terminal coupled to a voltage reference; (d) a fourth switch that includes a first port coupled to an output port of said third buffer and a second port coupled to said second control signal; (e) a fourth buffer that includes an input port coupled to a third port of said fourth switch; and (f) a fourth capacitor that includes a first terminal coupled to said input port of said fourth buffer, wherein said fourth capacitor includes a second terminal coupled to a voltage reference, and (4) a first scaling module that includes an input port coupled to an output port of said fourth buffer, wherein said first scaling module includes an output port coupled to a second input port of said, adder.