Patent ID: 6026031
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A method of accessing a memory array of a memory device, the method comprising the steps of:(a) generating a write clock signal in response to a system clock signal and a write signal;(b) generating a write pulse signal in response to the write clock signal;(c) generating an end-of-write signal in response to the write clock signal and the write pulse signal;(d) storing an address in a first address register in response to the system clock signal;(e) transferring the address from the first address register to a second address register in response to the write clock signal;(f) transferring the address from the second address register to a third address register in response to one of the end-of-write signal and the write clock signal;(g) delivering the address from the third address register to the memory array in response to the write pulse signal;(h) storing data in a first data register in response to the write clock signal;(i) transferring the data from the first data register to a second address register in response to one of the end-of-write signal and the write clock signal; and(j) transferring the data from the second address register to a write driver in response to the write pulse signal, the write driver delivering the data to the memory array.