Patent ID: 9136269
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: defining a cell region and a peripheral circuit region in a first direction in a semiconductor substrate and defining a first region and a second region in a second direction substantially orthogonal to the first direction in the peripheral circuit region; forming a gate insulating layer and a first conductive layer sequentially over the semiconductor substrate; forming trenches separating patterns of the gate insulating layer and patterns of the first conductive layer by partially removing the first conductive layer, the gate insulating layer and the semiconductor substrate from the cell region and the peripheral circuit region; forming isolation layers by partially filling the trenches with an insulating material and forming recesses in top portions of the isolation layers to partially expose sidewalls of the patterns of the first conductive layer; forming a dielectric layer along a surface of an entire structure including the isolation layers; forming a second conductive layer over the dielectric layer to fill the recesses; forming gate lines arranged in the second direction in the cell region by partially removing the second conductive layer, the dielectric layer, the patterns of the first conductive layer and the patterns of the gate insulating layer from the cell region; exposing the patterns of the first conductive layer by removing the second conductive layer and the dielectric layer from the first region; and forming a third conductive layer to electrically couple the patterns of the first conductive layer exposed at the first region and forming a capacitor including lower electrodes and an upper electrode, wherein the patterns of the first conductive layer and the third conductive layer become the lower electrodes and the second conductive layer in the second region becomes the upper electrode.