Patent ID: 6952369
Filing Date: 2005-10-04
Classification: G11C

Abstract:
1. A method for writing a memory module comprising: providing a plurality of memory cells, wherein each memory cell stores 2-bit data and comprises a substrate, a first P-type doped region, a second P-type doped region, an oxide-nitride-oxide (ONO) layer, and a gate, the plurality of memory cells being arranged in matrix with the gates of the memory cells on the same row being connected to the same word line, the neighboring memory cells on the same column sharing the same P-type doped region, the first P-type doped region of the first memory cell in each column connected to a first transmission line in the same column, and the second P-type doped region of the last memory cell in each column connected to a second transmission line in the same column; applying a first transmission line voltage to the first transmission line of the column which a memory cell to be written belongs to; turning on a P-type channel of the memory cell between the memory cell to be written and the first transmission line of the column which the memory cell to be written belongs to, in order to transmit the first transmission line voltage to the first P-type doped region of the memory cell to be written; turning off the P-type channel of at least one memory cell between the memory cell to be written and the second transmission line of the column which the memory cell to be written belongs to; applying a word line voltage to a word line connected to the memory cell to be written, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell to be written into a silicon nitride layer of the memory cell to be written by band-to-band tunneling (BTBT) injection; and applying a substrate voltage to the substrates of the plurality of memory cells.