Patent ID: 6391713
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for forming a dual damascene structure having capacitors, comprising:providing a first insulator; forming a first Cu wire and a second Cu wire in the first insulator by executing a damascene process; forming a first sealing layer on the first insulator and the first and the second Cu wires; forming a second insulator on the first sealing layer; forming a third insulator acting as an etch stop layer on the second insulator; forming a first Cu plug and a second Cu plug in the first sealing layer, the second insulator and the third insulator; forming a first metal layer on the third insulator and the first and second Cu plugs; forming a fourth insulator on the first metal layer; forming a second metal layer on the fourth insulator; patterning the second metal layer to form an upper electrode; patterning the fourth insulator and the first metal layer, wherein the first metal layer is transferred into a bottom electrode and a conducting wire, wherein the bottom electrode is connected with the first Cu wire through the first Cu plug and the conducting wire is connected with the second Cu wire through the second Cu plug; forming a fifth insulator with a flat surface on the upper electrode, the fourth insulator and the third insulator; forming dual damascene patterns including trenches and holes in the fifth insulator; forming a third Cu wire and a fourth Cu wire in the trenches and a third Cu plug and a fourth Cu plug in the holes, wherein the upper electrode is connected with the third Cu wire through the third Cu plug, and the conducting wire is connected with the fourth Cu wire through the fourth Cu plug; and forming a second sealing layer on the third and fourth Cu wires and the fifth insulator.