Patent ID: 6462782
Filing Date: 2002-10-08
Classification: H04N

Abstract:
A data extraction circuit comprising:a slice level determination circuit configured to determine a slice level of a data line of character data superimposed on a digital video signal; a line extraction circuit configured to slice the digital video signal by the slice level and extract the data line of the character data from the digital video signal; a sync signal detection circuit configured to detect a sync signal for analyzing the character data, the sync signal being contained in the data line of the character data; a bit detection circuit configured to detect a start bit indicative of a start of the character data, the start bit being contained in the data line of the character data; a clock generation circuit configured to generate a data extracting clock, which is synchronized with a reference signal, based on detection results of the sync signal and the start bit; and a data reproduction section configured to reproduce the character data from the data line of the character data using the data extracting clock, wherein the reference signal is an fsc signal of the digital video signal.