Patent ID: 6117778
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method for planarizing a dielectric layer on a semiconductor wafer or other workpiece comprising the steps of:applying a resist to a dielectric coated wafer to coat the wafer with a layer of the resist;removing the resist from a circumferential peripheral portion of the wafer and leaving the resist on a central portion of the wafer;exposing the partially resist coated wafer to a dry or wet etchant which etches the dielectric layer not covered by the resist;etching the resist coated wafer to remove dielectric material from the circumferential peripheral portion forming a profiled dielectric layer having a thinner dielectric peripheral portion than the remaining central dielectric portion of the wafer;removing the resist from the central portion of the etched wafer; andplanarizing the profiled dielectric layer by chemical-mechanical planarization.