Patent ID: 6140843
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A data processing apparatus comprising:a precharged circuit having at least one input line arranged to be precharged to a first logic value during a precharge phase;a conditional-invert circuit connected to a first said at least one input line and arranged to provide a first data value or the inverted first data value on the first input line during an active phase following the precharge phase, said conditional-invert circuit comprising:a signal line coupled to the first input line and arranged to be precharged to a predetermined logic value during the precharge phase;a first set of logic gates connected between the signal line and a predetermined voltage, and being arranged dependent on a value of a first select signal to cause the first data value to be provided on the first input line;a second set of logic gates connected between the signal line and the predetermined voltage, and being arranged dependent upon a value of a second select signal to cause the inverted first data value to be provided on the first input line;whereby in the active phase, the values of said first and second select signals cause only one of said first and second sets of logic gates to provide its respective data value to said input line.