Patent ID: 7802117
Filing Date: 2010-09-21
Classification: G06F,H04W,Y02D

Abstract:
1. A power management apparatus for devices, comprising: an interface module, including: receivers for receiving input signals from devices; an auto power management unit coupled with the receivers for determining a state of the input signals, and outputting a power management signal based on the determined state of the input signals; and an electronic unit coupled with the auto power management unit for driving driver units, with the power management signal toggling a status of the electronic unit based on the determined state of the input signals to thereby reduce power utilization; the auto power management unit is comprised of: a number of input units that correspond to a number of receivers; the input units respectively receive a corresponding number of input signals from the receivers and respectively generate a corresponding number of time delayed output signals; the generated time delayed output signals provide glitch-free input signals to a sequential logic circuit; the sequential logic circuit forming an electronic latch unit having a corresponding number of first digital logic operators that receive the time delayed output signals and generate a corresponding number of latched signals to maintain respective signal values in their status quo until a new input signal is received from a device; a corresponding number of second digital logic operators are coupled with the electronic latch unit that function to invert the generated latched signals and respectively output a corresponding number of inverted latched signals; a third digital logic operator receives the inverted latched signals and combines the inverted latched signals to output a combined signal; the combined signal is further delayed by a time delay output unit for a predetermined time and output as a glitch-free power management signal.