Patent ID: 8032816
Filing Date: 2011-10-04
Classification: G06F,G11C

Abstract:
1. An apparatus for distinguishing correctable bit errors in memory, the apparatus comprising: a bit error detection module configured to detect a correctable bit error in a data memory in response to a memory READ operation, the correctable bit error correctable using error-correcting code (“ECC”), the memory READ operation generated during normal operation of a processor in communication with the data memory; a comparison module configured to compare an error location indicator with a stored error location indicator, the error location indicator comprising an indication of location in the data memory of the correctable bit error, the stored error location indicator corresponding to at least one previously stored error location indicator of a previously detected correctable bit error; a storage module configured to store the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator; and an error counter module configured to increase an error counter corresponding to the error location indicator in response to the comparison module determining that the error location indicator matches a stored error location indicator.