Patent ID: 6696860
Filing Date: 2004-02-24
Classification: H03K

Abstract:
A data buffer circuit comprising:first and second driver circuits operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to first and second data signals; an output circuit comprising first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective third and fourth voltages responsive to respective ones of the outputs of the first and second driver circuits; and a transition compensation circuit operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal, wherein the transition compensation circuit comprises: a driver circuit coupled in series with an input of one of the first and second driver circuits; and a bias control circuit coupled to a power supply input of the driver circuit and operative to vary an impedance between the power supply input and a power supply node responsive to the transition rate control signal.