Patent ID: 6630856
Filing Date: 2003-10-07
Classification: G11C

Abstract:
A multiplexer circuit comprising:a first subcircuit coupled to receive at least a first signal and a second signal, wherein said first subcircuit is configured to drive a first output node responsive to either of said first signal or said second signal being active; a second subcircuit coupled to receive at least a third signal and a fourth signal and configured to drive a second output node responsive to either of said third signal or said fourth signal being active; a latching circuit coupled to said first output node and said second output node, wherein said latching circuit is configured to capture and retain a first output on said first output node and a second output on said second output node; and a third subcircuit coupled to receive said first, second, third and fourth signals and coupled to said first and second output nodes, wherein said third subcircuit is configured to drive said second output node responsive to either one of said first signal or said second signal being active, wherein said third subcircuit is configured to drive said first output node responsive to either one of said third signal or said fourth signal being active.