Patent ID: 6961824
Filing Date: 2005-11-01
Classification: G06F

Abstract:
1. An apparatus comprising: a cache memory arranged to having a plurality of ways to store data; a replacement circuit having a linear feedback shift register to hold a value to select a way for replacement when a cache miss is to occur, the replacement circuit to receive a predetermined value by a cache direct access transaction which loads the predetermined value into the linear feedback shift register to select a particular way of the cache memory to be evicted with a next cache miss, and the replacement circuit also including a next state circuit coupled to the linear feedback shift register to receive a first of one or more bits from the linear feedback shift register and to use the first of one or more bits to generate an output bit from the next state circuit to shift into the linear feedback shift register to set a new value in the linear feedback shift register to select a way for eviction with the next cache miss; and a control circuit coupled to the replacement circuit to select between replacement by direct access transaction or by shifting in of the output bit.