Patent ID: 7380231
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A method of altering wire spacing of a routed layout of an integrated circuit design, said method comprising: providing a routed layout having a plurality of wire segments, wherein each said wire segment can have a geometrical representation or a topological representation in said routed layout; for each of said wire segments, generating a bottom-up shape (BUS) and a top-down shape (TDS) by altering positions of wire segments having topological representations in said routed layout; wherein said BUS for each of said wire segments is generated by determining a bottom shape (BS) for each of said wire segments and then increasing spacing between said bottom shapes of said wire segments; wherein said TDS for each of said wire segments is generated by determining a top shape (TS) for each of said wire segments and then increasing spacing between said top shapes of said wire segments; merging said BUS and said TDS to form a final middle shape (MS); and removing unnecessary short jogs from said MS.