Patent ID: 8717796
Filing Date: 2014-05-06
Classification: G11C,H01L

Abstract:
1. A method comprising: receiving a select signal by a memory die in a stack of memory dies, the select signal being configured to manage operation of the stack, wherein the memory die has chip-select nodes, wherein the signal is received by an external chip-select node of the memory die; transmitting the select signal from the chip-select nodes to an identification circuit of the memory die, wherein each memory die has the corresponding identification circuit configured to determine an identification of its respective memory die; and identifying the memory die responsive to how the identification circuit of the memory die is coupled to receive the select signal from the chip-select nodes of the memory die, wherein the chip-select nodes on one memory die are routed to the chip-select nodes on another memory die by routing which is separate from a location of the identification circuits.