Patent ID: 8228744
Filing Date: 2012-07-24
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array comprising a plurality of pages in which a plurality of memory cells are arranged; a page buffer formed adjacent to the memory cell array, and comprising a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page; a data line pair arranged in the page buffer and connected to the sense amplifiers; a differential amplifier configured to amplify a potential difference between lines of the data line pair; a precharger configured to precharge the data line pair to a predetermined potential; a plurality of shunt regions arranged between the pages along a first direction in the memory cell array, and extending in a second direction perpendicular to the first direction; and a plurality of shunt extension regions formed in the page buffer by extending the shunt regions in the second direction, wherein at least one of the differential amplifier and the precharger is formed in the page buffer, and said at least one circuit is electrically connected to the data line pair, and is placed in at least one of the shunt extension regions.