Patent ID: 7863146
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A method for forming an integrated device, comprising the steps of: forming a first diffusion well for the device, the first diffusion well including a first channel region for a first transistor, the first transistor being an N-channel transistor, the first channel region defining longitudinal and transverse directions for the first diffusion well; forming a second diffusion well for the device, the second diffusion well including a second channel region for a second transistor, the second transistor being a P-channel transistor, the second channel region defining longitudinal and transverse directions for the second diffusion well; forming a first STI region transversely adjacent to the first diffusion well, such that the first channel region is elevated relative to the first STI region; forming a second STI region longitudinally adjacent to the first diffusion well, such that the first channel region is elevated also relative to the second STI region; forming a third STI region transversely adjacent to the second diffusion well, such that the second channel region is elevated relative to the third STI region; forming a fourth STI region longitudinally adjacent to the second diffusion well, such that the second channel region is not elevated relative to the fourth STI region; forming a first gate conductor overlying the first channel region after the step of forming a first STI region; forming a second gate conductor overlying the second channel region after the step of forming a third STI region; forming first source and drain regions for the first transistor in the first diffusion well on opposite sides of the first channel region longitudinally; and forming second source and drain regions for the second transistor in the second diffusion well on opposite sides of the second channel region longitudinally.