Patent ID: 6724778
Filing Date: 2004-04-20
Classification: H04J

Abstract:
A method for long code generation in synchronous, multi-chip rate communication systems, comprising the steps of:producing a first long code sequence having a first bit rate; producing a second long code sequence having the first bit rate, the second long code sequence being a time delay of the first code sequence; producing a third long code sequence having the first bit rate, the third long code sequence being a time delay of the first long code sequence; and multiplexing the first long code sequence, the second long code sequence, and the third long code sequence, and producing an output code sequence having a desired bit rate, wherein the step of producing the second long code sequence comprises the step of performing modulo-2 addition of the first code sequence and a delayed version of the first code sequence, and wherein the step of producing the third code sequence comprises the step of performing modulo-2 addition of the first code sequence and a second delayed version of the first code sequence.