Patent ID: 6891765
Filing Date: 2005-05-10
Classification: G06F,G11C

Abstract:
1. An apparatus comprising: a memory comprising a first address space configured as read only and a second address space configured as read and write, wherein said memory returns a first data item in response to a first address within said first address space; a logic circuit configured to (i) deassert a command signal in response to said first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert said command signal in response to said first address matching one of said predetermined addresses in response to said matching, wherein said logic circuit is further configured to generate a first branch address within said second address space and assert said command signal in response to a second address (i) immediately following said first address and (ii) having a value one unit of said first address space different than said first address; and a multiplexer configured to select (i) said first data item from said memory or (ii) said first branch instruction from said logic circuit in response to said command signal.