Patent ID: 6317861
Filing Date: 2001-11-13
Classification: G06F

Abstract:
A delay verification device for performing delay verification for a logic circuit having circuit elements, comprising:circuit information storing means for storing circuit information on said logic circuit;first delay information storing means for storing first delay information on a delay time between said circuit elements predicted before layout designing of said logic circuit;second delay information storing means for storing second delay information on a delay time between said circuit elements computed after layout designing of said logic circuit;difference extracting means for comparing said first delay information and said second delay information, and for extracting difference information on a portion of said logic circuit whose delay time of said second delay information is longer than that of said first delay information;extracted circuit information obtaining means for searching paths of said logic circuit based on said circuit information and said difference information, extracting a path including said portion of said logic circuit, and storing the extracted path as extracted circuit information; anddelay analyzing means for analyzing delays of said extracted path using said extracted circuit information.