Patent ID: 6940331
Filing Date: 2005-09-06
Classification: H03H

Abstract:
1. A delayed tap signal generating circuit comprising: a first tap signal generating circuit adapted to receive a first clock signal and a second clock signal, which have a same frequency and a phase difference between them, adapted to receive offset information, and adapted to generate a first tap signal in response to the first and second clock signals and the offset information, wherein the first tap signal is delayed with respect to the first clock signal by a first delay corresponding to the offset information; and a second tap signal generating circuit adapted to receive the first and second clock signals, adapted to receive the offset information, and adapted to generate a second tap signal in response to the first and second clock signals and the offset information, wherein the second tap signal is delayed with respect to the first clock signal by the first delay and a second delay added to the first delay, wherein the second delay corresponds to the offset information, and wherein the first and second tap signals are generated by interpolating the first and second clock signals in response to the offset information.