Patent ID: 6516332
Filing Date: 2003-02-04
Classification: G06F

Abstract:
An apparatus for performing mathematical operations upon numbers in a floating point format having n bits of data where n is substantially smaller than known formats, said apparatus comprising a data processor programmed to perform mathematical operations by means of combinational logic which operates upon said numbers in said floating point format; wherein said data processor hasa gate array which includes a plurality of floating point operator units for performing the mathematical operations of addition, subtraction, multiplication and division; and selection means for selecting an output from the floating point operator units in accordance with a desired mathematical operation; said gate array including two inputs on which two numbers on which the mathematical operations are to be performed are input; said plurality of floating point operator units comprising an adder, a subtractor, a multiplier and a divider, each of said adder, subtractor, multiplier and divider being connected to said two inputs and operable for providing an output; and said selection means comprising a first multiplexer for receiving the outputs from said adder and said subtractor, a second multiplexer for receiving the outputs from said multiplier and said divider, and a third multiplexer for receiving respective outputs from said first and second multiplexers, said outputs from said first, second and third multiplexers being selected in accordance with control signals applied thereto in accordance with the desired mathematical operation.