Patent ID: 6359221
Filing Date: 2002-03-19
Classification: H01L,Y10T

Abstract:
A resin-sealed semiconductor device, comprising:a semiconductor element having a top surface and a bottom surface with terminals formed on said top surface; and plural circuit portions having top surfaces and bottom surfaces with said top surfaces facing said bottom surface of said semiconductor element, wherein said plural circuit portions include, integrally formed inner terminals and outer terminals arranged two-dimensionally along a plane and electrically independent of one another, said top surfaces of said inner terminals of said circuit portions are electrically connected to said terminals of said semiconductor element with wires, said device is completely sealed with a resin in such a manner that said bottom surfaces of said outer terminals are partially exposed, said circuit portions have leads for integrally interconnecting said inner terminals and said outer terminals, said inner terminals and said leads are thinner than said outer terminals, said semiconductor element is mounted on said top surfaces of said circuit portions with an insulating layer disposed therebetween, wherein said device is configured as a chip size package (CSP) having a chip on lead (COL) structure, and wherein said outer terminals, said leads and a portion of said inner terminals of the circuit portions are directly underneath the semiconductor element with the insulating layer disposed therebetween.