Patent ID: 7098478
Filing Date: 2006-08-29
Classification: H01L

Abstract:
1. An SRAM device comprising: a plurality of word lines; a plurality of bit lines; and a plurality of static memory cells each including a first, second, third, fourth, fifth, and sixth transistors, wherein gates of said fifth and sixth transistors are coupled to said word lines, wherein source and drain regions of said fifth and sixth transistors are formed inside a semiconductor substrate, wherein channel regions, source and drain regions of said first and second transistors are formed by depositing three poly-silicon layers above a substrate surface of the semiconductor substrate, wherein vertical sides of said three poly-silicon layers, which surfaces are vertical against said substrate surface, are completely surrounded by a gate layer and having a dioxide layer inbetween, wherein some of said first, second, third, fourth, fifth, and sixth transistors are disposed on different surfaces from each other, and wherein said different surfaces are electrically connected through a vertical interconnect element.