Patent ID: 6145042
Filing Date: 2000-11-07
Classification: G06F

Abstract:
A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface, such interface comprising:(A) a bus having: an bus-select/address/command portion; bus-grant/data/clock-pulse/queue portion;(B) a plurality of addressable memories coupled to the bus;(C) a plurality of controllers coupled to the bus, each one thereof being configured:to assert on the bus-select/command/address portion of the bus during a controller initiated bus select assert interval, a command including: (i) a read operation request; and (ii) an address to address one of the addressable memories selected by the controller to respond to the read operation request; and(D) such addressed memory being configured:(a) to produce on the queue portion of the bus a queue assert signal after a controller initiated bus select assert interval, such queue signal terminating the bus select interval;(b) to produce on the bus-grant/data/clock-pulse portion of the bus a bus grant signal after a queue assert signal is produced on the queue portion of the bus, such bus grant signal initiating a data transfer, bus grant interval;(c) to provide on the bus-grant/data/clock-pulse portion of the bus during the data transfer, bus grant interval: (i) data at the address provided by the controller during the bus assert interval; and (ii) bus read clock pulses; and(d) to remove the bus grant signal from the bus-grant/data/clock-pulse portion of the bus upon completion of the read operation requested by the controller to terminate the bus grant interval; and(E) wherein another one of the controllers is configured to provide on the bus-select/address/command portion of the bus another address and command after the queue signal terminates the bus select assert interval.