Patent ID: 8447007
Filing Date: 2013-05-21
Classification: G06F,H03K

Abstract:
1. A method for generating a counter output of a dual mode counter, comprising: receiving a fast clock signal on a first signal path; receiving a slow clock signal on a second signal path; receiving a clock selection signal on a third signal path, the clock selection signal indicating selection of one of a fast clock mode and a slow clock mode; synchronizing transitions of the clock selection signal with the slow clock signal; increasing the counter output by a first counter increment for each period of the fast clock signal, in response to the clock selection signal indicating the fast clock mode; and increasing the counter output by a second counter increment for each period of the slow clock signal, the second counter increment comprising a ratio of the period of the slow clock signal divided by the period of the fast clock signal in response to the clock selection signal indicating the slow clock mode.