Patent ID: 8266476
Filing Date: 2012-09-11
Classification: G06F

Abstract:
1. A multiprocessor system, comprising: a plurality of processing modules, including a predetermined number, being three or more, of processors, a bus for relaying data transmission among the respective processing modules, a plurality of data transmission paths within the bus, such that the predetermined number of processors carry out data transmission with respect to a predetermined processing module among the plurality of processing modules, respectively, using any of the plurality of data transmission paths, damaged processor specifying means for specifying at least one damaged processor among the predetermined number of processors; communication restricted processor selecting means for selecting as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus such that the at least one processor carries out data transmission with respect to the predetermined processing module, using a data transmission path, among the plurality of data transmission paths, different from a data transmission path to be used in data transmission from the damaged processor to the predetermined processing module; and communication restriction means for restricting data transmission by the communication restricted processor via the bus.