Patent ID: 8656238
Filing Date: 2014-02-18
Classification: G06F

Abstract:
1. A scan flip-flop circuit, comprising: a pulse generator configured to generate a pulse signal that is enabled in synchronization with a rising edge of a clock signal in a normal mode, and is selectively enabled in synchronization with the rising edge of the clock signal in response to a logic level of a scan input signal in a scan mode; a dynamic input unit configured to precharge a first node to a power supply voltage in a first phase of the clock signal, configured to selectively discharge the first node based on input data in a second phase of the clock signal in the normal mode, and configured to discharge the first node in response to the scan signal in the scan mode; and a latch output unit configured to latch an internal signal provided from the first node to provide an output data, and configured to determine whether the output data is toggled based on at least a logic level of the clock signal and a previous state of the output data, wherein the pulse generator is configured to generate at least one pulse during a period of the scan mode in which the output data does not change based on the input data.