Patent ID: 6459127
Filing Date: 2002-10-01
Classification: H01L

Abstract:
An electrostatic discharge (ESD) protection device as part of high voltage n-channel metal oxide semiconductor (NMOS) transistors and protecting same, comprising:a semiconductor wafer with a p-substrate; an n-well formed in said p-substrate, where said n-well is the drain of a first and a second NMOS transistor; first and second n+ diffusions implanted in said n-well; a first p+ diffusion implanted in said n-well between said first and second n+ diffusion; a second and a third p+ diffusion implanted in said p-substrate at opposite sides of said n-well; a third n+ diffusion implanted in said p-substrate between said n-well and said second p+ diffusion, said third n+ diffusion representing the source of said first NMOS transistor; a fourth n+ diffusion implanted in said p-substrate between said n-well and said third p+ diffusion, said fourth n+ diffusion representing the source of said second NMOS transistor; a first gate formed between said n-well and said third n+ diffusion, said first gate representing the gate of said first NMOS transistor; a second gate formed between said n-well and said fourth n+ diffusion, said second gate representing the gate of said second NMOS transistor; said first, said second n+ diffusion and said first p+ diffusion connected together by conductive means; said third and said fourth n+ diffusion, and said second and said third p+ diffusion connected to a reference potential; a first parasitic silicon controlled rectifier (SCR), further comprising: a first parasitic pnp bipolar transistor, having an emitter, a base, and a collector, said emitter, said base, and said collector of said first parasitic pnp bipolar transistor formed by said first p+ diffusion, said n-well, and said p-substrate, respectively; a first parasitic npn bipolar transistor, having an emitter, a base, and a collector, said emitter, said base, and said collector of said first parasitic npn bipolar transistor formed by said third n+ diffusion, said p-substrate, and said n-well, respectively; a first parasitic resistor between said second p+ diffusion and said p-substrate; a second parasitic resistor between said first n+ diffusion and said n-well; a second parasitic silicon controlled rectifier (SCR), further comprising: said first parasitic pnp bipolar transistor; a second parasitic npn bipolar transistor, having an emitter, a base, and a collector, said emitter, said base, and said collector of said second parasitic npn bipolar transistor formed by said fourth n+ diffusion, said p-substrate, and said n-well, respectively; a third parasitic resistor between said third p+ diffusion and said p-substrate; and a fourth parasitic resistor between said second n+ diffusion and said n-well.