Patent ID: 6925027
Filing Date: 2005-08-02
Classification: G11C

Abstract:
1. A semiconductor memory having a memory core for dynamically holding data, the semiconductor memory comprising: a first buffer circuit for inputting an enable signal for controlling a standby state or a nonstandby state; a second buffer circuit for outputting a predetermined logic signal or a read/write signal for controlling the reading of data from or the writing of data to the memory core in accordance with the enable signal; a third buffer circuit for outputting an inverted signal obtained by inverting the logic signal or the read/write signal in accordance with the enable signal; a control circuit for controlling the reading or writing of the data by the logic signal or the read/write signal outputted from the second buffer circuit; and a data output control circuit for controlling the inputting of the data from or the outputting of the data to the outside by the inverted signal or the read/write signal outputted from the third buffer circuit.