Patent ID: 7379359
Filing Date: 2008-05-27
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory, comprising: a regular sector which includes a plurality of nonvolatile regular memory cells, regular bit lines connected to said regular memory cells, a nonvolatile redundancy memory cell to relieve a defective regular memory cell, and a redundancy bit line connected to said nonvolatile redundancy memory cell; a defect-information sector which includes a plurality of nonvolatile defect-information memory cells storing defect information indicating a position of the defective regular memory cell, and which includes defect-information bit lines connected to said defect-information memory cells; a regular sense amplifier which is connected to the regular bit line to read data stored in said regular memory cells; a defect-information sense amplifier which is connected to the defect-information bit line to read said defect information stored in said defect-information memory cells; a write amplifier which is connected to the regular bit line to write data into said regular memory cells; and a defect-information switch which connects the defect-information bit line to the regular bit line in order to write said defect-information into said defect-information memory cells using said write amplifier.