Patent ID: 8111541
Filing Date: 2012-02-07
Classification: G11C,H01L

Abstract:
1. A method of forming a multi-level cell (MLC) resistance random access memory (RRAM) structure, comprising: depositing a first programmable resistive memory member having a thickness t1, the first programmable resistive memory member having a resistance Ra, the resistance Ra correlating with the thickness t1 of the first programmable resistive memory member; forming an insulating member over the first programmable resistive memory member; depositing over the insulating member a second programmable resistive memory member having a thickness t2, the second programmable resistive memory member having a resistance Rb, the resistance Rb correlating with the thickness t2 of the second programmable resistive memory member; and oxidizing the first programmable resistive memory member to form a first metal oxide strip at a first position of the first programmable resistive memory member and form a second metal oxide strip at a second position of the first programmable resistive memory member, the first metal oxide strip having a vertical thickness MLa and a horizontal thickness MLOXa.