Patent ID: 7409658
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. A computer implemented method of designing integrated circuits, comprising: assessing m objects representative of source code for an integrated circuit design, wherein at least a portion of the m objects includes one or more logic objects, each logic object having placement-based performance data characterizing the logic object over a range of different physical implementations, wherein the performance data is created by placing and routing each physical implementation of the logic object; recursively clustering at least a portion of the assessed m objects until the combined number of clustered and unclustered objects is less than n objects, wherein n is a maximum desired number of objects for a floorplanning operation, wherein the clustering includes selecting objects for the clustering so as to reduce the number of interconnections between the clusters; floorplanning the less than n objects in a design area, including positioning the less than n objects within the design area so as to reduce wire lengths between the less than n objects, wherein the one or more logic objects are floorplanned using the placement-based performance data; placing the objects within the design area assigned to the corresponding clusters so as to reduce the wire lengths between the objects; and outputting a list of the objects and their assigned locations.