Patent ID: 6384474
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A housing for accommodating a planar power transistor in which a hermetically sealed chip of the planar power transistor is arranged and with metallized areas on the chip being led out of the housing via electric terminals, comprising:a base forming one of the electric terminals and a bottom of the housing; a sleeve supported on the base and encompassing the chip in an interior space filled with a casting compound that hermetically seals the chip; a head carrier forming another of the electric terminals and serving as a cover of the housing and a shield arranged at a distance away from the sleeve, the head carrier being electroconductively coupled by a first solder to a first metallized area of the chip; a ring element encompassing the head carrier beneath the shield between an outside of the head carrier and the sleeve, the ring element being electroconductively coupled by a second solder to a second metallized area of the chip; an insulating enamel covered with the casting compound and filling a gap between the first metallized area and the second metallized area; and a terminal lug projecting away from the ring element and forming a gate electrode of the planar power transistor, the terminal lug being led through the distance between the shield and the sleeve, wherein the housing is formed by at least one of the electric terminals.