Patent ID: 9202932
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: sequentially forming a dielectric layer structure and a control gate layer sequentially on a substrate; partially etching the control gate layer to form a plurality of control gates; forming a gate spacer and a sacrificial spacer sequentially stacked on a sidewall of the control gate and on a portion of the dielectric layer structure; partially etching the dielectric layer structure using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns; removing the sacrificial spacer; and forming an insulating interlayer on the substrate to form an air gap, the insulating interlayer covering the dielectric layer structure pattern, the gate spacer and the control gate, and the air gap extending between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.