Patent ID: 6740965
Filing Date: 2004-05-25
Classification: H01L,H05K

Abstract:
A flip-chip package substrate, comprising:a plurality of sequentially stacked wiring layers; at least one insulation layers between two neighboring wiring layers so that the insulation layer and the wiring layer are alternately stacked on top of each other; and at least one conductive plugs passing through the insulation layer for electrically connecting the wiring layers; wherein the uppermost wiring layer further includes: a plurality of core bump pads; at least two signal bump pad rings around the core bump pads; at least one power bump pad rings around the core bump pads; and at least one ground bump pad ring around the core bump pads, wherein one of said power bump pad ring and one of said ground bump pad ring are positioned between said two signal bump pad rings; wherein the signal bump pad rings, the power bump pad rings and the ground bump pad rings are distributed concentrically; and the bottommost wiring layer further includes: a plurality of core ball pads; at least one signal ball pad rings around the core ball pads; at least one power ball pad rings around the core ball pads; and at least one ground ball pad rings around the core ball pads; wherein the signal ball pad rings, the power ball pad rings and the ground ball pad rings are distributed concentrically.