Patent ID: 6788091
Filing Date: 2004-09-07
Classification: G01R

Abstract:
A wafer for testing by a testing device, the wafer comprising:a plurality of integrated circuits, wherein each integrated circuit includes testing circuitry; a network of signal paths on the wafer, wherein the network of signal paths connects the plurality of integrated circuits to two or more connection points; a current mirror; and a plurality of transistors, wherein in response to the testing device being connected to the connection points, the testing circuitry performs a test on the plurality of integrated circuits concurrently, wherein each integrated circuit includes at least one visible component having an appearance and wherein the at least one visible component permanently changes its appearance in response to failing the test, wherein the at least one visible component includes at least one diode-connected transistor, wherein the current mirror receives a high current and passes an equal amount of current to each of the plurality of transistors, and wherein the plurality of transistors, responsive to an input signal, pass current to the diode-connected transistor, causing the diode-connected transistor to burn up and leave a visible mark.