Patent ID: 6461907
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A method for fabricating a semiconductor device provided with a partially-depleted SOI MOSFET and a fully-depleted SOI MOSFET on the same substrate, comprising the steps of:forming a fully-depleted SOI MOSFET formation region and a partially-depleted SOI MOSFET formation region by isolating elements in an SOI layer of an SOI substrate that includes, in succession, a buried oxide film and an SOI layer on a silicon substrate; injecting, at a same dosage, same impurities for threshold control into the SOI layer of both said fully-depleted SOI MOSFET formation region and said partially-depleted SOI MOSFET formation region; forming a first gate oxide film on the SOI layer of both said fully-depleted SOI MOSFET formation region and said partially-depleted SOI MOSFET formation region; removing said first gate oxide film on the SOI layer in said fully-depleted SOI MOSFET formation region; and forming, in said fully-depleted SOI MOSFET formation region, a gate oxide film that is thinner than the gate oxide film of said partially-depleted SOI MOSFET formation region.