Patent ID: 6304197
Filing Date: 2001-10-16
Classification: H03M

Abstract:
A machine for concurrently processing digital variable-length codes comprising:(a) a plurality of variable-length encoding processors,(b) a plurality of variable-length decoding processors,(c) a communicator transferring output of said encoding processors to said decoding processors, which will:(1) maintain ordinal correspondence between said encoding processors and said decoding processors, and(2) maintain temporal correspondence among said decoding processors relating to the temporal correspondence among encoding processors,(d) a controller regulating encoding which will assign data to said encoding processors according to a timed relation based on:(1) said encoding processors' ordinal rank, and(2) said encoding processors' processing status,(e) a controller regulating decoding which will:(1) temporally align resultant data from said decoding processors with regard to antecedent input(2) output data resultant from said decoding processors according to a timed relation based on:(i) said decoding processors' ordinal rank, and(ii) said decoding processors' processing status,whereby a plurality of variable-length data elements may be acted upon simultaneously, andwhereby no restriction is placed on the independence of input data.