Patent ID: 6058148
Filing Date: 2000-05-02
Classification: H03G,H04B

Abstract:
A radio reception circuit using digital signal processing (DSP) to digitally process an intermediate frequency (IF) signal, comprising:a circuit means providing a carrier-based signal;a complex mixer coupled to said circuit means and generating a complex I & Q signal in response to said carrier-based signal;a filter processor generating a filtered I & Q signal in response to said complex I & Q signal, said filter processor having an impulse response determined by filter coefficients loaded into said filter processor, said filter coefficients being switchable between a first bank of filter coefficients for a first bandwidth and a second bank of filter coefficients for a second bandwidth narrower than said first bandwidth;a post-filter level detector responsive to said filtered I & Q signal to generate a first level signal;a pre-filter level detector responsive to said carrier-based signal to generate a second level signal; anda compare block coupled to said post-filter level detector, said pre-filter level detector, and said filter processor for selecting one of said banks of filter coefficients in response to a comparison of said first and second signal levels, wherein said compare block determines a difference between said first level signal and said second level signal and compares said difference to a threshold, and wherein said threshold has a first value when said first bank of filter coefficients is selected and has a second value when said second bank of filter coefficients is selected, said first and second values of said threshold providing a predetermined hysteresis to prevent oscillation between said first and second banks of filter coefficients.