Patent ID: 6103594
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of forming shallow trench isolations in the manufacture of an integrated circuit device comprising:forming a first dielectric layer overlying a silicon substrate;depositing a silicon nitride layer overlying said first dielectric layer;patterning said silicon nitride layer, said first dielectric layer, and said silicon substrate to form trenches into said silicon substrate for planned said shallow trench isolations;depositing a second dielectric layer overlying said silicon nitride layer and said trenches;anisotropically etching said second dielectric layer to form sidewall spacers inside said trenches;selectively growing a silicon layer where said silicon substrate is exposed in said trenches wherein said silicon layer does not surpass the top surface of said silicon nitride layer;depositing a third dielectric layer overlying said silicon nitride layer, said sidewall spacers, and said silicon layer; andpolishing down said third dielectric layer to the top surface of said silicon nitride layer wherein said silicon nitride layer acts as a polishing stop to complete said shallow trench isolations in the fabrication of said integrated circuit device.