Patent ID: 9036447
Filing Date: 2015-05-19
Classification: G11C

Abstract:
1. A decoder circuit comprising: a pre-decode stage configured to decode a plurality of address signals into a plurality of decode input signals, wherein the pre-decode stage includes a plurality of two-high, pre-decode NOR gates and a respective pair of inverters for each pre-decode NOR gate; a decode stage configured to decode the plurality of decode input signals into a plurality of word line driver input signals; and a word line driver stage configured to drive a plurality of word lines, wherein the word line driver stage comprises a plurality of two-high, word line NOR gates, wherein each word line NOR gate is configured to receive two respective word line driver input signals and drive a corresponding word line based on the two respective word line driver input signals; wherein each inverter of each respective pair of inverters is configured to receive one address signal of the plurality of address signals and provide a respective inverted address signal to one of the pre-decode NOR gates; and wherein each pre-decode NOR gate of the plurality of pre-decode NOR gates is configured to receive two respective inverted address signals and output a corresponding decode input signal based on the two respective inverted address signals.