Patent ID: 6578104
Filing Date: 2003-06-10
Classification: G11C,H03K

Abstract:
An apparatus comprising:a plurality of programmable logic circuits; a plurality of configurable RAM circuits programmably coupled to said plurality of programmable logic circuits wherein each configurable RAM circuit has a configurable depth of addressable elements and a configurable width of the number of data bits that may be stored in said configurable RAM circuit, wherein each configurable RAM circuit has at least one mode input port for receiving a mode signal indicating the configuration of said configurable depth and said configurable width, and wherein each configurable RAM circuit further comprises: a plurality of address ports; a plurality of data input ports; a plurality of data output ports; wherein said RAM circuit receives address signals on less than all said plurality of address ports when said configurable depth is configured to be less than a maximum, said RAM circuit receives data bits on less than all said plurality of data input ports and produces data bits on less than all said plurality of data output ports when said configurable width is less than a maximum, and wherein each configurable RAM circuit further comprises: an array of memory cells for storing data; a multiplexor circuit electrically coupled to said at least one mode input port, said plurality of address ports, said plurality of data input ports, and said plurality of data output ports, said multiplexor circuit coupled to said array of memory cells, said multiplexor circuit obtaining stored data from said array of memory cells in response to at least a portion of said mode signals and said address signals, and wherein each configurable RAM circuit further comprises a mode decoder electrically coupled between said at least one mode input port and said multiplexor.