Patent ID: 7369425
Filing Date: 2008-05-06
Classification: G11C

Abstract:
1. A dynamic random access memory (DRAM) device comprising: a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors; a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or more pass transistors; and a cell plate connected to both a second terminal of at least one memory cell capacitor and a second terminal of at least one reference cell capacitor, wherein the cell plate is biased at approximately one half of a voltage difference between a positive supply voltage (Vdd) and a complementary lower supply voltage (Vss), and wherein the reference cell capacitor does not store any charge prior to a reading operation, and both the first and second bit-lines are pre-charged to a power supply voltage prior to the reading operation.