Patent ID: 6297545
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor chip including an integrated circuit and a plurality of external terminals formed at a major surface thereof;a plurality of leads each having an inner lead and an outer lead which is formed integrally with said inner lead, each of said inner leads having a first portion which is disposed over said major surface of said semiconductor chip, a second portion which is outside of said semiconductor chip, and a stepped portion between said first and second portions, said plurality of leads having an upper surface and a lower surface which is opposite to said upper surface and is closer to said major surface of said semiconductor chip than said upper surface, said stepped portion being formed at said lower surface such that a thickness of said first portion is thinner than a thickness of said second portion in a thickness direction of said semiconductor chip;an adhesive layer being formed between said first portion of each of said inner leads and said major surface of said semiconductor chip, said first portion of each of said inner leads and said major surface of said semiconductor chip being bonded to one another by said adhesive layer;a plurality of bonding wires electrically connecting said inner leads with the corresponding external terminals of said plurality of external terminals; anda resin member sealing said semiconductor chip, said inner leads of said plurality of leads and said plurality of boding wires,wherein a thickness of said adhesive layer is thinner than the degree of thickness change of said inner leads at said stepped portion in said thickness direction of said semiconductor chip.