Patent ID: 9053798
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A non-volatile memory circuit formed of a P-channel MOS transistor, comprising: a P-channel non-volatile memory element comprising a floating gate and a control gate capacitively coupled to the floating gate; a resistor divider comprising a first resistor and a second resistor for dividing a voltage difference between a power supply voltage and a ground voltage, a divided voltage output of the resistor divider being connected to the control gate of the P-channel non-volatile memory element; a first switch connected in parallel to the first resistor; and a second switch connected in parallel to the second resistor, wherein the first switch and the second switch are controlled so that a voltage of the control gate is set to a voltage of the divided voltage output which maximizes an electric field between a pinch-off point and a drain point of the P-channel MOS transistor in a writing mode, and so that the voltage of the control gate is set to the power supply voltage in a reading mode and in a retention mode.