Patent ID: 8384642
Filing Date: 2013-02-26
Classification: G09G

Abstract:
1. A drive circuit, comprising: a plurality of first output circuits that output signals of one polarity; a plurality of second output circuits that output signals of another polarity; a power source wire that connects power terminals of some of the first output circuits and power terminals of some of the second output circuits, wherein the some of the first output circuits comprise the first output circuits belonging to a first group; wherein the some of the second output circuits comprise the second output circuits belonging to the first group; wherein the power source wire comprises a first power source wire; wherein the plurality of the first output circuits include first output circuits belonging to a second group that is different from the first group, and wherein the plurality of the second output circuits include second output circuits belonging to the second group that is different from the first group; a second power source wire that connects power terminals of the first output circuits of the second group and power terminals of the second output circuits of the second group, and that is different from the first power source wire, wherein the first output circuits of the first group and the second output circuits of the first group are arranged in a first direction to constitute a first array, wherein the first output circuits of the second group and the second output circuits of the second group are arranged in the first direction to constitute a second array, and wherein the first array and the second array are arranged adjacent to each other in a second direction that is different from the first direction; and a plurality of output terminals that respectively receive outputs of the plurality of the first output circuits and outputs of the plurality of the second output circuits, wherein the output terminals are arranged in the first direction to constitute a third array, wherein the first, the second and the third arrays are adjacently arranged to each other in this order in the second direction, wherein when a first, a second, a third and a fourth output circuits are assumed to denote some of the first and the second output circuits respectively corresponding to a first, a second, a third and a fourth output terminals, which are arranged adjacent to each other in this order, out of the output terminals, one even-numbered circuit and one odd-numbered circuit of the first to fourth output circuits are included in the first array, and another even-numbered circuit and another odd-numbered circuit of the first to fourth output circuits are included in the second array.