Patent ID: 7671362
Filing Date: 2010-03-02
Classification: H01L

Abstract:
1. A test structure for integrated circuit (IC) device fabrication, the structure comprising: a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; and each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the deposition process conditions, wherein a top portion of each of the one or more vias has at least one chamfer surface at one side thereof and a substantially straight vertical sidewall profile at an opposing side thereof such that a chamfer angle defined by the at least one chamfer surface of the one or more vias varies from chain to chain so as to produce the variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.