Patent ID: 8384440
Filing Date: 2013-02-26
Classification: G01R,G04F,H03K,H03L

Abstract:
1. A time capture circuit comprising: an input terminal receiving an input signal having a state transition; a synchronization circuit having a first input connected to said input terminal, a second input receiving a sample clock signal and an output, said synchronization circuit producing at said output a synchronized signal having a state transition corresponding to said state transition in said input signal delayed to a corresponding state transition in said sample clock signal; an edge detector having an input connected to said output of said synchronization circuit and an output, said edge detector producing at said output a capture signal upon detection of said state transition in said synchronized signal; a multibit counter having an input receiving said sample clock signal and a plurality of bit outputs, said multibit counter counting said plurality of bit outputs at a rate of said sample clock signal; an integer register having a number of bits at least as great as a number of bits of said multibit counter, said integer register having bit inputs connected to corresponding bit output of said multibit counter and an enable input receiving said capture signal from said edge detector, said register storing said bit outputs of said multibit counter upon receipt of said capture signal; a high resolution capture delay line including a plurality of bit circuits disposed in sequence from a first bit circuit to a last bit circuit, each bit circuit having: an encoder circuit having plural bit inputs, each bit input connected to a bit output of a corresponding one of said bit circuits and an output generating an encoded multibit signal corresponding to said outputs of said plurality of bit circuits; and a fractional register having a number of bits at least as great as a number of bits of said encoded multibit signal, said fractional register having bit inputs connected to said output of said encoder circuit and an enable input receiving said capture signal from said edge detector, said fractional register storing said encoded multibit signal from said encoder circuit upon receipt of said capture signal.