Patent ID: 8661227
Filing Date: 2014-02-25
Classification: G06F

Abstract:
1. A processor, comprising: an instruction fetch unit; an issue queue coupled to the instruction fetch unit that receives instructions dispatched from the instruction fetch unit; an execution unit, coupled to the issue queue, that executes instructions issued from the issue queue, wherein the instructions executed by the execution unit reference a plurality of architected logical registers; a multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency, wherein each of the first and second level register files individually includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of hardware threads; and a mapper including: wherein the issue queue, in response to a signal from the mapper indicating the first operand is present in the first level register file, issues the instruction to the execution unit for execution.