Patent ID: 8490043
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. A standard cell library stored on a computer readable storage, the standard cell library used by a processor to produce a layout for fabricating at least one aspect of a finished semiconductor device, comprising: the standard cell library containing cells wherein at least one transistor in at least one cell is identified by an annotation, and the annotation itself also identifies a gate length biasing to be applied to the at least one transistor of the at least one cell when the processor produces the layout, wherein the gate length biasing is an amount of change to a gate length of the at least one transistor, the amount of change is defined by the annotation; wherein the amount of change is a sign of positive or negative amount of change of the gate length; wherein the amount of change is identified as nanometer values between about 1 nanometer and about 5 nanometers; wherein the amount of change represents design-specific directives that require implementation; and wherein the amount of change is predefined to allow passage by a design rule checker (DRC) tool.