Patent ID: 8949551
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. A data processing system comprising: a memory protection unit (MPU); a plurality of region descriptors associated with the MPU, wherein each region descriptor is associated with one of multiple subsets of the region descriptors and includes an address range, protection settings, and attributes for a respective region of memory, the subsets including a subset of data-only region descriptors, a subset of instruction-only region descriptors, and a subset of shared region descriptors; a first shared region descriptor of the subset of shared region descriptors, the first shared region descriptor including a first indicator to selectively configure the first shared region descriptor to operate as one of a data region descriptor or an instruction region descriptor; first instruction compare logic coupled to an instruction address bus and to the first shared region descriptor, the first instruction compare logic to compare an address at the instruction address bus with a first address range specified at the first region descriptor; and first data compare logic coupled to a data address bus and to the first shared region descriptor, the first data compare logic to compare an address at the data address bus with the first address range; wherein the first instruction compare logic is enabled and the first data compare logic is disabled if the first indicator is in a first state; and wherein the first instruction compare logic is disabled and the first data compare logic is enabled if the first indicator is in a second state.