Patent ID: 6438030
Filing Date: 2002-08-20
Classification: G11C,H01L

Abstract:
A semiconductor device having an electrically erasable programmable read only memory (EEPROM) array including rows and columns of memory cells comprising:a first p-well region and a second p-well region within a semiconductor substrate, wherein the first p-well region and the second p-well region are spaced apart and electrically isolated; a first column of memory cells positioned within the first p-well region; a second column of memory cells positioned within the second p-well region; a first control gate of a first memory cell in the first column of memory cells and a second control gate of a second memory cell in the second column of memory cells, wherein the first control gate and the second control gate are in a same row and electrically coupled via a common wordline; a first bitline electrically coupled to drain regions of each memory cell in the first column of memory cells, a second bitline electrically coupled to drain regions of each memory cell in the second column of memory cells; a first source line electrically coupled to source regions of each memory cell in the first column of memory cells, wherein the first source line and a source region of at least one memory cell in the first column of memory cells is electrically coupled to the first p-well region; and a second source line electrically coupled to source regions of each memory cell in the second column of memory cells, wherein the second source line, and a source region of at least one memory cell in the second column of memory cells is electrically coupled to the second p-well region.