Patent ID: 6403981
Filing Date: 2002-06-11
Classification: H01L

Abstract:
An integrated circuit including a transistor comprised of a first gate conductor disposed above a top surface of a substrate a first dielectric layer below the first gate conductor and above the top surface, a first crystallized silicon layer below the first dielectric layer and above the top surface of the substrate, a crystallized silicon germanium layer above the top surface and below the first crystallized silicon layer, a second crystallized silicon layer above the top surface and below the crystallized silicon germanium layer; and a second dielectric layer below the top surface and below the second crystallized silicon layer and a second gate conductor disposed below the second dielectric layer, wherein a portion of the first crystallized silicon layer, the second crystallized silicon layer, and the crystallized silicon germanium layer form a channel region, the transistor being manufactured by a method comprising:providing a first amorphous semiconductor layer above a top surface of the substrate; annealing the first amorphous semiconductor layer to form the first crystallized silicon layer; providing a second amorphous semiconductor layer including germanium above the first crystallized layer; annealing the second amorphous semiconductor layer to form the crystallized silicon germanium layer; providing a third amorphous semiconductor layer above the crystallized silicon germanium layer; annealing the third amorphous semiconductor layer to form the second crystallized silicon layer; providing a gate structure above the second crystallized silicon layer; and doping the first crystallized silicon layer, the second cystallized silicon germanium layer and the third cystallized silicon layer at a source location and a drain location to form a source region and a drain region.