Patent ID: 7673279
Filing Date: 2010-03-02
Classification: G03F

Abstract:
1. A system for refining an integrated circuit (IC) layout through an iterative procedure, the IC layout having of a plurality edge fragments, the system comprising: means for determining a directional orientation of each edge fragment; means for grouping edge fragments of the same directional orientation to form mutually exclusive directional orientation sets; means for selecting an edge fragment from one of the mutually exclusive sets; means for calculating an edge placement error (EPE) of the selected edge fragments; means for shifting the selected edge fragment based on the calculated EPE to a new position; means for updating the orientation of the shifted edge fragment; means for selecting an edge fragment from another one of the mutually exclusive sets; means for reiterating calculating the EPE of the edge fragment, shifting edge fragment and updating orientation and selecting of an edge of a different directional orientation until a predetermined limit is reached wherein the means for reiterating calculating the EPE of the edge fragment performs the calculating by alternating between mutually exclusive sets; and wherein the mutually exclusive sets contain edge fragments of non-opposing directional orientation.