Patent ID: 7689401
Filing Date: 2010-03-30
Classification: G06F

Abstract:
1. A simulation device that processes a simulation for evaluating delay characteristics of a logical circuit, comprising: a storage section storing a simulation program beforehand; and a control section reading said simulation program from said storage section and executing said simulation program, wherein said control section, by running said simulation program, implements: a model generating section that divides said logical circuit into a plurality of partial circuits; a selection section that selects, from the plurality of partial circuits obtained by said division, a target circuit and a load circuit connected with a subsequent stage of said target circuit, such that each partial circuit becomes, at least once, the target circuit; a simplification section that simplifies said load circuit using a transistor with which a virtual control voltage source is connected to a drain of the transistor, whereby the output potential of the transistor is varied in accordance with a gate potential of the transistor; a simulation section that performs a simulation evaluating the delay characteristics of said target circuit, based on an input pattern to said target circuit with a combination of said target circuit and said simplified load circuit, for each said selected target circuit; and a library generating section that, for each path that connects an input terminal and an output terminal of said logical circuit, obtains the delay characteristics of the each path using the delay characteristics of said partial circuits included in the each path, and wherein said virtual control voltage source supplies a potential corresponding to LOW if the signal level corresponding to said gate potential is HIGH and supplies a potential corresponding to HIGH if the signal level corresponding to said gate potential is LOW.