Patent ID: 6235597
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method for fabricating a semiconductor structure which comprises providing a semiconductor substrate; providing a plurality of gates located on the semiconductor substrate and separated from the semiconductor substrate by a first insulating layer; implanting dopants into the substrate between adjacent gates; then providing insulating spacers on sidewalls of the gates; wherein the insulating spacers are generally L-shaped having a vertical portion and a horizontal portion and wherein spacing exists between adjacent L-shaped insulating spacers; implanting source/drain dopant between adjacent L-shaped insulating spacers and beneath the horizontal portion of the L-shaped insulating spacers;wherein the horizontal portion of the L-shaped spacer partially blocks the source/drain implants andwherein said dopant has a peak within the vicinity of said spacing between the horizontal portion of said insulating spacers; and thenremoving the horizontal portion of the L-shaped insulating spacers by etching; and forming a metallic silicide in the spacing between remaining vertical portions of the insulating spacers.