Patent ID: 7632723
Filing Date: 2009-12-15
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate conductive layer on an insulating substrate; forming a gate insulating layer on the gate conductive layer; forming a semiconductor layer on the gate insulating layer; forming a data conductive layer at least in part on the semiconductor layer, the data conductive layer comprising a data line, a source electrode coupled to the data line and a drain electrode separated from the source electrode, and the data conductive layer also comprising an upper conductive film and a lower conductive film; forming a passivation layer on the data conductive layer and the semiconductor layer, a portion of the passivation layer directly contacting the lower conductive film; and forming a pixel conductive layer contacting the lower conductive film, wherein the formation of the semiconductor layer and the data conductive layer comprises: