Patent ID: 7879727
Filing Date: 2011-02-01
Classification: G03F,H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: depositing a hardmask layer on a layer of the semiconductor device; selectively etching a pattern of continuous lines in the hardmask layer; depositing an antireflective coating over remaining portions of the hardmask layer; depositing a photoresist layer on the antireflective coating; patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, with each isolation trench having an initial width; reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process; etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines; and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.