Patent ID: 7184318
Filing Date: 2007-02-27
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate, a first and a second diffusion layer formed in said semiconductor substrate, an insulator film formed at the surface of said semiconductor substrate between said first and second diffusion layers, a first electrode formed to overlap a part of said first diffusion layer over said insulator film, a second electrode which can be controlled independently from said first electrode, a charge trapping region, which stores charge, formed surrounded by an insulator, in the vicinity of the surface of said semiconductor substrate between said first electrode and said second diffusion layer, wherein the voltage of said charge trapping region is controlled by said second electrode, information are stored in said charge trapping region by using a change of conductance between said first diffusion layer and said second diffusion layer corresponding to the charge stored in said charge trapping region, and said first electrode is controlled to be a negative voltage in the case when said charge trapping region is not the target for programming.