Patent ID: 8405185
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween; a trench in the semiconductor substrate, the trench having first and second opposing sidewalls that define interfaces with a first trench isolation region and a first active region, respectively; a first electrical interconnect at a bottom of the trench; an electrically insulating capping pattern extending between the first electrical interconnect and a top of the trench; an interconnect insulating layer lining the first and second sidewalls and the bottom of the trench, the interconnect insulating layer extending between the first electrical interconnect and the first active region; a recess in the first active region, the recess having a sidewall that defines an interface with the interconnect insulating layer; and a second electrical interconnect extending on an upper surface of the first trench isolation region, the electrically insulating capping pattern and the sidewall of the recess.