Patent ID: 8773936
Filing Date: 2014-07-08
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a plurality of sense amplifiers driving bit lines to which memory cells are connected; a plurality of sense amplifier drivers supplying a power supply to the sense amplifiers, each of sense amplifier drivers having first and second driver transistors, and the first driver transistor having a first diffusion regions in a first well region and the second driver transistor having a second diffusion region in a second well region which is different conductivity type from the first well region, and an element separation region formed between the first and second well region, wherein the first and second driver transistors are arranged in parallel with a first direction so as to be arranged one of second driver transistors between two of the first driver transistors, wherein the first diffusion region comprises first and second sides, the first side is parallel to the first direction and the second side is perpendicular to the first direction, wherein the second diffusion region comprises third and fourth sides, the third side is parallel to the first direction and the fourth side is perpendicular to the first direction, wherein the element separation region extends along the first, second, third and fourth sides.