Patent ID: 7807569
Filing Date: 2010-10-05
Classification: H01L

Abstract:
1. A method of forming a semiconductor device comprising: forming a conductive pad in a non-cell area of a semiconductor substrate in such a manner that the conductive pad is covered with a lower insulation interlayer extending over a cell area and the non-cell area of the semiconductor substrate; forming a first contact pattern and a second contact pattern on the lower insulation interlayer in the non-cell area and the cell area of the semiconductor substrate, respectively, the first contact pattern having a first opening overlying a peripheral region of the conductive pad and exposing an upper surface of the lower insulation interlayer and the second contact pattern having a second opening exposing a conductive plug that extends through a portion of the lower insulation interlayer in the cell area of the semiconductor substrate; forming a first conductive pattern and a second conductive pattern in the first opening and the second opening, respectively, in such a manner that a portion of the first contact pattern is positioned over a central portion of the conductive pad and the first conductive pattern is positioned over a peripheral portion of the conductive pad; forming an upper insulation interlayer on the first and second contact patterns and on the first and the second conductive patterns; sequentially removing a portion of the upper insulation interlayer, a portion of the first contact pattern over the central portion of the contact pad and a portion of the lower insulation interlayer corresponding to the central portion of the contact pad, thereby forming a third opening to expose the central portion of the conductive pad; and forming a conductive contact extending through the third opening and being electrically connected to the conductive pad.