Patent ID: 8256106
Filing Date: 2012-09-04
Classification: H05K,Y10T

Abstract:
1. A method for fabricating a circuit board structure with capacitors embedded therein, comprising: providing a first core layer comprising a dielectric layer having two opposite surfaces, first metal layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the first metal layer at the same side; providing a second core layer and a third core layer individually comprising a dielectric layer having a first surface and a second surface opposite to the first surface, a first metal layer disposed on the first surface of the dielectric layer, and at least one capacitor embedded on the inside of the first surface with the first metal layer disposed on the outside thereof of the dielectric layer and electrically connecting with the first metal layer; patterning the two first metal layers of the first core layer to form circuit layers; laminating the two surfaces of the first core layer with the second surfaces of the dielectric layers of the second core layer and the third core layer, respectively, to form a core structure, wherein the second surfaces of the dielectric layers have no capacitors and metal layers respectively on the inside and the outside thereof; and patterning the first metal layers of the second core layer and the third core layer to form circuit layers; wherein each of the capacitors comprises: a first electrode plate disposed on the outside of one surface of the dielectric layer, and electrically connecting with the circuit layer at the same side; a high dielectric constant material layer embedded on the inside of the surface with the first electrode plate disposed on the outside thereof of the dielectric layer, and plastering the first electrode plate; and a second electrode plate disposed in the inner space of the dielectric layer, plastered with the high dielectric constant material layer, parallel with the first electrode plate, and electrically connecting to the circuit layer but not electrically connecting to the first electrode plate through the circuit layer.