Patent ID: 7281229
Filing Date: 2007-10-09
Classification: G06T

Abstract:
1. A method of preparing a three dimensional view of an integrated circuit (IC) layout including: selecting an initial polygon representing an IC feature from a two dimensional view of the IC layout, the initial polygon including a plurality of points defining a first dimension and a second dimension of the initial polygon; generating a first polygon of the three dimensional view based on at least one of the points of the plurality of points, the first dimension of the initial polygon and a thickness of the IC feature represented by the initial polygon; generating a second polygon of the three dimensional view based at least one point of the first polygon, a second dimension of the initial polygon, and a rendering angle at which the three dimensional view is to be rendered; generating a third polygon of the three dimensional view based on at least one point of the second polygon and the first dimension of the initial polygon such that the three dimensional view of the IC feature including the first, second and third polygon is rendered.