Patent ID: 6516004
Filing Date: 2003-02-04
Classification: H04L

Abstract:
A HDLC digital data transmission protocol controller, the controller including:a data input port from a data stream, said data stream being transmitted asynchronously using time-division multiplexing (TDM) of messages over a number N of channels, said messages constituting N message quantities distributed over said number N of channels, universal synchronous-asynchronous receiver-transmitter means (USART), linked to said input port and enabling, from said transmitted data stream, synchronous transmission of basic messages, each basic message belonging to a respective message quantity, sequential storage means, linked to said universal synchronous-asynchronous receiver-transmitter means, for receiving and sequentially storing said basic messages, means for reading and sequentially processing said sequentially stored basic messages, said sequential storage means being managed as a circular buffer memory comprising at least a first and a second storage area, alternatively and respectively intended to: receive and store said basic messages supplied by said universal synchronous-asynchronous receiver-transmitter means (USART), and act as a working memory by allowing said means of reading and sequentially processing to carry out serial processing of the stored basic messages, according to the HDLC protocol.