Patent ID: 7227769
Filing Date: 2007-06-05
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a memory cell having a capacitor which stores therein a charge corresponding to a logic of data; a bit line connected to said memory cell; a charge transferring circuit connected to said bit line; a charge storing circuit connected to said bit line through said charge transferring circuit, and storing therein a charge read out from said memory cell to said bit line in a read operation and generating a read voltage in accordance with a stored charge; a read circuit generating a logic of the data retained in said memory cell, in accordance with the read voltage generated by said charge storing circuit; a control circuit controlling charge transferability of said charge transferring circuit to transfer the charge read out to said bit line to said charge storing circuit, in accordance with a change in a voltage of said bit line, the change being caused by the read-out charge; and a leakage controlling circuit temporarily lowering the charge transferability of said charge transferring circuit in a read operation before a charge is read out from said memory cell to said bit line.