Patent ID: 6784098
Filing Date: 2004-08-31
Classification: H01L

Abstract:
A method of fabricating field effect transistors having low sheet resistance gate electrodes, comprising the steps of:providing a semiconductor substrate, said substrate having been provided with at least one gate electrode created over an active region of said substrate as defined by regions of Shallow Trench Isolation provided in said substrate, said at least one gate electrode having been provided with gate spacers, impurity implants of source and drain regions in addition to Lightly Doped Diffusion regions having been provided in said substrate self-aligned with said at least one gate electrode, said at least one gate electrode comprising a stack of layers of pad oxide created over said substrate, a layer of polysilicon patterned over the layer of pad oxide and a layer of boronitride patterned over the layer of polysilicon; depositing a thin layer of salicide material over said substrate, including said gate spacers and said layer of polysilicon provided for said at least one gate electrode; performing a first anneal, forming salicided layers comprising reacted salicide material over said source and drain implants; first removing un-reacted salicide material from said substrate; depositing an isolation film over said substrate, including said gate spacers and said layer of boronitride provided for said at least one gate electrode; depositing a layer of filler material over said isolation film to a thickness such that said layer of filler material extends above said isolation film even where said isolation film overlays said at least one gate electrode, said depositing a layer of filler material comprises depositing a layer of photoresist; polishing said layer of filler material and said layer of isolation film down to said layer of boronitride of said at least one gate electrode, using said layer of boronitride as a stop for said process of polishing, advantageously using a polishing rate of filler material that is larger than a polishing rate of boronitride, said layer of boronitride providing a save stop for said polishing the layer of filler material and the layer of isolation film, thereby further preventing corrosion of said at least one gate electrode; removing said layer of boronitride from said at least one gate electrode, exposing said layer of polysilicon forming part of said at least one gate electrode; depositing a thick layer of salicide material over said polished layer of filler material, including the exposed surface of said layer of polysilicon; performing a second anneal of said deposited thick layer of salicide material, a layer of reacted salicide material overlying said layer of polysilicon of said at least one gate electrode; second removing un-reacted salicide material from said layer of dielectric; performing a third anneal, reducing the sheet resistance of said reacted salicide material overlying said layer of polysilicon of said at least one gate electrode.