Patent ID: 9203351
Filing Date: 2015-12-01
Classification: H03F

Abstract:
1. A system comprising: a first gain circuit comprising: a pair of input nodes configured to receive an input signal; a transistor circuit connected to the pair of input nodes and configured to convert the input signal to an output signal, where the output signal has a gain compared with the input signal; and a pair of output nodes configured to receive the output signal from the transistor circuit before the first gain circuit receives a feedback offset correction signal; wherein, in response to the first gain circuit receiving the feedback offset correction signal, the first gain circuit causes a voltage change at one of the output nodes relative to another output node thereby cancelling at least a portion of an offset in the output signal, wherein the first gain circuit comprises an offset cancellation circuit that is configured to receive the feedback offset correction signal from a feedback path independent from receiving the output signal from the transistor circuit, and wherein the pair of input nodes, which are included in the first gain circuit and configured to receive the input signal, are connected to the transistor circuit, which is included in the first gain circuit and configured to convert the input signal to the output signal, where the output signal has a gain compared with the input signal, the pair of output nodes, which are included in the first gain circuit and configured to receive the output signal from the transistor circuit before the first gain circuit receives a feedback offset correction signal, are connected to the transistor circuit, and the offset cancellation circuit, which is included in the first gain circuit and configured to receive the feedback offset correction signal from the feedback path independent from receiving the output signal from the transistor circuit, is connected to the feedback path.