Patent ID: 6040247
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A method for forming a semiconductor device comprising the steps of:providing an insulation layer on a substrate;exposing a portion of said insulation layer by providing a photoresist pattern on said insulation layer;performing a first etching step of said insulation layer, said first etching step including the steps of:introducing into an etching chamber a first gas including CF.sub.4, a second gas including a polymer forming gas, other than CF.sub.4, and a third gas including an inert gas; andcontrolling a first flow rate of said inert gas to have a first flow rate value; andperforming a second etching step of said insulation layer, said second etching step ;including the step of controlling a second flow rate of said inert gas to have a second flow rate value, said second flow rate value being greater than said first flow rate value,wherein said second etching step yields a contact hole in said insulation layer having sloped sidewalls.