Patent ID: 6289295
Filing Date: 2001-09-11
Classification: G01R

Abstract:
An integrated circuit device, comprising:a conductor for receiving a scan data signal;a plurality of storage circuit devices each having a data input and a data output;wherein a first of the plurality of storage circuit devices is coupled to receive the scan data signal at its data input;wherein each of the plurality of storage circuit devices other than the first of the plurality of storage circuit devices is coupled to receive at its data input a scan data bit as output from another one of the plurality of storage circuit devices as part of the scan data signal, thereby forming a clocked scan path through the integrated circuit device;and further comprising scannable multiplexer circuit having an output coupled to a data input of one of the plurality of storage circuits, wherein the scannable multiplexer circuit comprises:a first input for receiving a scan data bit from the scan data signal;a second input for receiving a normal operations data bit;a first transistor device having its source/drain conductive path coupled between the first input and the output of the scannable multiplexer circuit, and having a first threshold voltage;a second transistor device having its source/drain conductive path coupled between the second input and the output of the scannable multiplexer circuit, and having a second threshold voltage; andwherein the first threshold voltage is larger in absolute value than the second threshold voltage.