Patent ID: 8691597
Filing Date: 2014-04-08
Classification: C25D,H01L

Abstract:
1. A method for manufacturing a semiconductor device, the method comprising: preparing a semiconductor wafer including a plug-embedded interlayer insulation film formed thereover; forming an insulation film over the interlayer insulation film; forming a wiring trench in a given region of the insulation film by dry etching; forming a seed film of copper over the insulation film including the wiring trench; forming a copper plating film over the seed film using an electroplating method by an electroplating device; and removing the copper plating film and the seed film in a region except for the wiring trench, and forming a wiring of the copper plating film embedded in the wiring trench, wherein in the forming the copper plating film by the electroplating device, when the semiconductor wafer is immersed in a plating solution to form a copper plating film, a plating voltage applied across an anode and a cathode is detected and a determination is made whether the detected plating voltage falls within a preset set voltage range, wherein in the determination results, when the plating voltage does not fall within the set voltage range, a concentration of an inorganic component in the plating solution is adjusted so that the voltage value of the plating voltage falls within the set voltage range, and wherein when the plating voltage is greater than an upper limit value of the set voltage range, pure water is supplied.