Patent ID: 9029216
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A manufacturing method of a memory, comprising: providing a substrate with a stack of alternate semiconductor layers and first insulating layers thereover; forming a second insulating layer on the stack; forming a first conductive layer on the second insulating layer; patterning the first conductive layer, the second insulating layer and the stack to form a plurality of bit line stacks, a plurality of second insulating layers corresponding to the bit line stacks, and a plurality of first conductive layers corresponding to the bit line stacks; forming a memory layer, the memory layer covering the bit line stacks; removing parts of the memory layer to expose the first conductive layers; and forming a plurality of liners respectively along sidewalls of the bit line stacks, such that the liners are connected with the first conductive layers to form a plurality of string select structures.