Patent ID: 9197197
Filing Date: 2015-11-24
Classification: G06F,H03K

Abstract:
1. A duty cycle protection circuit comprising: a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of said first clock signal; and reset circuitry coupled to said input line and adapted to generate a second clock transition of said second clock signal by resetting said first synchronous device a time delay after said first clock transition of said first clock signal; said reset circuitry comprising a delay element adapted to provide a delayed version of said second clock signal, and pulse generation circuitry coupled to said delay element; said pulse generation circuitry comprising a logic gate having first and second inputs coupled to the delay element; said first input being adapted to directly receive the delayed version of said second clock signal, and said second input being adapted to directly receive an inverted version of the delayed version of said second clock signal; said pulse generation circuitry adapted to generate a pulse for resetting said first synchronous device based on said first clock transition of said first clock signal.