Patent ID: 8170421
Filing Date: 2012-05-01
Classification: H04J

Abstract:
1. A clock recovery apparatus, comprising: a high-order demultiplexing-demapping unit, for demapping and demultiplexing an high-order Optical Transmit Network, OTN, frame into n low-order Optical channel Data Tributary Unit ODTUjk frames in a time-division manner; a plurality of memory units, for receiving and storing Optical Channel Data Unit, ODUj, frames; a low-order demapping unit, for demapping the n low-order ODTUjk frames into n ODUj frames respectively, writing the n ODUj frames into memory units an ODUj frame clock generating unit, for justifying the speed of reading from the memory units n+1 to wherein the high-order demultiplexing-demapping unit comprises: a memory module, for receiving and storing the payload of the high-order OTN frame; a first write-control module, for setting a clock CLKA carrying an enabling signal according to the mapping structure of the high-order OTN frame, the payload of the high-order OTN frame and the clock of the high-order OTN frame, and writing the payload of the high-order OTN frame into the memory module by using the clock CLKA; and a first smooth-control module, for setting a clock CLKB with uniformly-distributed gaps according to the multiplexing structure of the high-order OTN frame, the payload of the high-order OTN frame and the clock CLKA, wherein the clock CLKB is adapted to control the reading speed of reading the n low-order ODTUjk frames from the memory module.