Patent ID: 6451654
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A process for fabricating a self-aligned split gate flash memory, comprising the following steps:successively forming a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer on a semiconductor substrate; forming a first insulating spacer on the sidewalls of the patterned gate oxide layer, the first patterned polysilicon layer, and the first patterned mask layer; forming a trench in the substrate using the first patterned mask layer and the first insulating spacer as a mask; filling an insulator into the trench; removing the first patterned mask layer and a part of the first insulating spacer to expose the first patterned polysilicon layer; forming a second patterned mask layer on the first patterned polysilicon layer while exposing a part of the first polysilicon layer to define a floating gate region; selectively oxidizing the exposed surface of the first polysilicon layer using the second patterned mask layer as a mask to form a polysilicon oxide layer; removing the second patterned mask layer; using the polysilicon oxide layer as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate; and successively forming an intergate insulating layer and a second patterned polysilicon layer as a control gate on the polysilicon oxide layer.