Patent ID: 8067837
Filing Date: 2011-11-29
Classification: H01L

Abstract:
1. A chip package comprising: a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a separating layer over said silicon substrate, said first metallization structure and said dielectric layer, wherein said separating layer comprises silicon nitride, wherein a first opening in said separating layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said first opening, a first polymer layer on said separating layer, wherein a second opening in said first polymer layer is over said contact point, and a second metallization structure on said contact point, on a sidewall of said first opening, on a sidewall of said second opening and on a top surface of said first polymer layer, wherein said second metallization structure contacts said contact point, said sidewall of said first opening, said sidewall of said second opening and said top surface of said first polymer layer, wherein said second metallization structure is connected to said contact point through said first and second openings, wherein said second metallization structure comprises an electroplated copper layer having a thickness greater than 3 micrometers; a circuit substrate; a tin-containing joint between said second metallization structure and a metal contact of said circuit substrate, vertically over said contact point and vertically over said top surface of said first polymer layer, wherein said second metallization structure is connected to said metal contact through said tin-containing joint; and a second polymer layer between said semiconductor chip and said circuit substrate, wherein said second polymer layer contacts said semiconductor chip and said circuit substrate, wherein said second polymer layer covers a sidewall of said tin-containing joint, wherein said second metallization structure has a sidewall with a region not covered by said tin-containing joint but covered by said second polymer layer.