Patent ID: 6180973
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate having a main surface;an element isolation insulating film formed on said main surface of said semiconductor substrate and buried in a first trench;a plurality of element formation regions each defined in an island form surrounded by said element isolation insulating film buried in said first trench;a plurality of second trenches formed in said plurality of element formation regions to be surrounded thereby, respectively;a plurality of capacitors formed in said plurality of second trenches, respectively, each of said capacitors having a plate electrode formed of said semiconductor substrate, a capacitor insulating film formed on an inner wall of each of said second trenches and a storage electrode formed in each of said second trenches with said capacitor insulating film disposed therebetween;a plurality of transistors formed in said plurality of element formation regions, respectively, each of said transistors having,a gate electrode formed having an upper surface and two opposite sides extending from the upper surface toward the semiconductor substrate, said gate electrode extending over said semiconductor substrate and passing over a portion of a corresponding one of said plurality of element formation regions and a corresponding one of said second trenches formed therein, said gate electrode being further disposed to be insulated from said storage electrode, the corresponding one of said plurality of element formation regions, and said semiconductor substrate,a first impurity diffusion layer formed on said corresponding one of said plurality of element formation regions on one of the opposite sides of said gate electrode,a second impurity diffusion layer formed on said corresponding one of said plurality of element formation regions on the other one of the opposite sides of said gate electrode, andchannel regions formed on said corresponding one of said plurality of element formation regions on opposing sides of the corresponding one of said second trenches below said gate electrode and respectively connected to said first and said second impurity diffusion layer;a plurality of connection electrodes each connecting said storage electrode to said first impurity diffusion layer; anda plurality of signal transmission lines each connected to said second impurity diffusion layer.