Patent ID: 7638371
Filing Date: 2009-12-29
Classification: H01L

Abstract:
1. A method for manufacturing a thin film transistor (“TFT”) array, comprising: providing a substrate; forming a patterned first metal layer on the substrate, the patterned first metal layer including forming an insulating layer over the patterned first metal layer; forming a patterned silicon layer; forming a patterned passivation layer over the patterned silicon layer and the patterned first metal layer, exposing portions of the patterned silicon layer and a portion of each one of the first conductive lines, each one of the second conductive lines, and each one of the gate electrodes; and forming a patterned doped silicon layer and a patterned second metal layer over the patterned passivation layer, filling the exposed portions of the patterned silicon layer and the exposed portions of the first conductive lines, the second conductive lines, and the gate electrodes, the patterned second metal layer including a plurality of third conductive lines and a plurality of fourth conductive lines, each of which corresponding respectively to one of the plurality of first conductive lines and one of the plurality of second conductive lines; wherein the first conductive lines are electrically connected to the corresponding third conductive lines through the exposed portions of the first conductive lines; and the third conductive lines form branch lines of a first plurality of dual-layer lines; wherein the second conductive lines are electrically connected to the corresponding fourth conductive lines through the exposed portions of the second conductive lines; and the fourth conductive lines form branch lines of a second plurality of dual-layer lines.