Patent ID: 9053793
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array configured to include a plurality of blocks, wherein each of the blocks has pages and each of the pages includes memory cells; and a peripheral circuit configured to program the memory cells to first to nth target program states, wherein the pages are coupled to different word lines, respectively, wherein the peripheral circuit programs memory cells of a first page selected from the pages to first to nth temporary program states by applying program voltages increasing step-by-step by a first incremental value, and then programs memory cells of a second page selected from the pages to the first to nth temporary program states, wherein the peripheral circuit programs the memory cells of the first page to the first to nth target program states from the first to nth temporary program states, respectively, by applying program voltages increasing step-by-step by a second incremental value after the memory cells of the second page are programmed to the first to nth temporary program states.