Patent ID: 7205227
Filing Date: 2007-04-17
Classification: A61P,H01L

Abstract:
1. A method of forming a CMOS construction, comprising: providing a semiconductor substrate having: a semiconductor base with an NMOS region and a PMOS region defined therein, a first conductive line over the NMOS region and a second conductive line over the PMOS region, a plurality of NMOS source/drain diffusion regions within the base and along a side of the first conductive line, and a plurality of PMOS source/drain diffusion regions within the base and along a side of the second conductive line; forming a patterned etch stop over the NMOS and PMOS source/drain diffusion regions, the patterned etch stop having a plurality of openings extending therethrough, a first set of the openings being in one-to-one correspondence with the NMOS source/drain diffusion regions and a second set of the openings being in one-to-one correspondence with the PMOS source/drain diffusion regions; forming an electrically insulative material over the patterned etch stop; utilizing an etch to form a trench extending through the electrically insulative material to the patterned etch stop and to extend the first and second sets of the openings to at least proximate the NMOS source/drain diffusion regions and the PMOS source/drain diffusion regions, respectively; the trench having a first portion directly over the first set of the openings and a second portion directly over the second set of the openings; and forming an electrically conductive material within the first and second sets of the openings and within the trench, the electrically conductive material being in electrical connection with the PMOS and NMOS source/drain diffusion regions.