Patent ID: 9082877
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A method of forming a CMOS device, said method comprising: forming at least one isolation region in a semiconductor substrate to provide at least one first active region and at least one second active region; forming a gate structure extending across said at least one isolation region and spanning from said at least one first active region to said at least one second active region, wherein said gate structure includes at least one gate dielectric layer, at least one gate conductor layer, and at least one dielectric cap layer; forming a first source region and a first drain region of a first conductivity type on opposing sides of said gate structure in said at least one first active region, and a second source region and a second drain region of a second conductivity type on opposing sides of said gate structure in said at least one second active region; forming an opening in a portion of said at least one dielectric cap layer to expose a contact portion of said at least one gate conductor layer over said at least one isolation region, wherein a remaining portion of said at least one dielectric cap layer is present over said at least one first active region and said at least one second active region; and forming an interconnect in direct contact with said contact portion of said at least one gate conductor layer.