Patent ID: 8271226
Filing Date: 2012-09-18
Classification: G01R

Abstract:
1. A method of testing an Integrated Circuit (IC), comprising: loading a sequence of data into a serial chain of circuit elements that includes scan flip flops or latches coupled in a serial scan chain such that the sequence of data is loaded into the serial scan chain of scan flip flops or latches that hold the data values, wherein outputs of at least some scan flip flops or latches are connected to inputs of adjacent scan flip flops or latches so values move sequentially through the serial scan chain between a scan chain input for loading values and a scan chain output for unloading values, and a first circuit element in the serial chain includes a retention flip flop or latch for saving a value during a power variation related to the IC that had been held in a scan flip flop or latch of the first circuit element prior to the power variation; saving a value from the data sequence in the retention flip flop or latch; accessing the retention flip flop or latch for verifying an accuracy of the saved value from the data sequence.