Patent ID: 7426144
Filing Date: 2008-09-16
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits which is a transfer unit of said prefetched data in parallel to an internal bus in synchronization with an internal clock; and an output buffer circuit which includes L FIFO buffers each for latching each bit of said L bits input from said internal bus and extracts stored data from each of said L FIFO buffers in accordance with an input sequence in synchronization with an external clock so as to transfer said data serially to outside, wherein each of said L FIFO buffers includes an M-bit latch circuit for latching M bits of data input sequentially and an N-bit latch circuit for latching N (N>M) bits of data input sequentially, and a path of said M-bit latch circuit and a path of said N-bit latch circuit can be selectively switched.