Patent ID: 8962406
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A process for forming an integrated circuit, comprising the steps: forming a first polysilicon gate of a MOS transistor; forming an extended drain of a DEMOS transistor; forming a second polysilicon gate of said DEMOS transistor where a portion of said second polysilicon gate overlies an edge of said extended drain; forming a source and drain extension photoresist pattern that opens a source side and drain side of said MOS transistor and opens a source side of said DEMOS transistor and opens a major portion of said second polysilicon gate that overlies a channel of said DEMOS transistor but covers a drain side of said DEMOS transistor; and implanting said first polysilicon gate and said major portion with at least one dopant selected from the group indium, carbon, nitrogen, and halogen that raises a threshold voltage of said DEMOS transistor.