Patent ID: 8021971
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, the method comprising the steps of: providing a wafer comprising a semiconductor substrate, a gate stack formed atop the substrate, including a semiconductor gate conductor, having a width less than or equal to 65 nm, and dielectric spacers covering the sidewalls of the gate conductor while leaving the top surface of the gate conductor exposed; pulling down the dielectric spacers to expose an upper portion of the sidewalls of the semiconductor gate conductor to a pulldown spacer height; forming a thin metal layer over the wafer at least atop the exposed top surface and upper portion of the sidewalls of the semiconductor gate conductor, the thin metal layer comprising Ni and Pt; performing a formation anneal so that the thin metal layer reacts with the gate conductor to form a monosilicide layer; removing unreacted portions of the thin metal layer; and after removing said unreacted portions of the thin metal layer, performing a segregation anneal at a higher temperature than the formation anneal so that at least 50% of the Pt is located in a segregated region in a lower half of said monosilicide layer between a top surface of said monosilicide layer and said pulldown spacer height.