Patent ID: 6629214
Filing Date: 2003-09-30
Classification: G06F

Abstract:
A method, in a data processing system including a plurality of processors and a multiple-level memory hierarchy maintaining coherency using a coherency protocol, said method comprising:setting a reservation indicator associated with a particular processor among the plurality of processors which specifies a selected address for which the particular processor holds a reservation; maintaining the reservation address of the particular processor only within memory units that are at or above a specified level within the memory hierarchy, wherein the specified level is a highest level within the memory hierarchy at which memory units associated with the processor store data associated with the selected address; said particular processor modifying contents of a memory unit corresponding to the selected address by executing a store-conditional instruction targeting the selected address while the particular processor holds the reservation; and after modification of the contents of the memory unit corresponding to the selected address by the particular processor, allowing other ones of the plurality of processors to read the modified contents of the memory unit corresponding to the selected address, while retaining the reservation of the particular processor for the selected address.