Patent ID: 9106860
Filing Date: 2015-08-11
Classification: H04N

Abstract:
1. An AD conversion circuit comprising: a reference signal generation unit configured to generate a reference signal increasing or decreasing over time; a comparison unit configured to compare an analog signal that is a target of an AD conversion with the reference signal, the comparison unit being configured to terminate a comparison process at a timing at which the reference signal meets a predetermined condition for the analog signal; a clock generation unit that includes a delay circuit including a plurality of delay units connected to each other, the clock generation unit being configured to output a plurality of lower phase signals based on output signals of the delay circuit; a latch unit configured to latch the plurality of lower phase signals at a timing according to a termination of the comparison process; a counting unit including a counter circuit configured to perform counting by using a signal based on any one of the plurality of lower phase signals as a count clock so as to acquire an upper count value; and an encoding unit including a detection circuit and an encoding circuit, the detection circuit being configured to perform a first detection operation of detecting logic states of n lower phase signals (n is a natural number equal to or greater than 2) in a signal group that the plurality of lower phase signals, which has been latched in the latch unit, are arranged in the same order as those of the signal group when the plurality of lower phase signals, which are output from the clock generation unit during the comparison process, are arranged to be the signal group in which the lower phase signals rise or fall sequentially at predetermined time intervals according to on which of a rising edge and a falling edge of the count clock counting performed by the counter circuit is based, while selecting the n lower phase signals in a predetermined order, the detection circuit being configured to output a state detection signal when the logic state of the n lower phase signals is detected to be a predetermined logic state in the first detection operation, the encoding circuit being configured to perform encoding based on the state detection signal output from the detection circuit, wherein the detection circuit is configured to perform, at least once, a second detection operation of detecting the logic states of the n lower phase signals that are not n-consecutive in the first detection operation.