Patent ID: 6649472
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method to form flash memory devices in the manufacture of an integrated circuit device comprising:providing a substrate; forming STI regions in said substrate wherein said STI regions protrude substantially above the top surface of said substrate; forming a first film overlying said substrate and said STI regions wherein said first film comprises a floating gate layer overlying a first oxide layer; etching down said first film to expose said STI regions; thereafter forming a second film comprising a second oxide layer overlying said first film, a control gate layer overlying said second oxide layer, and an insulating layer overlying said control gate layer; patterning said first and second films to form stacked gates comprising floating gates and control gates; implanting ions into said substrate between said stacked gates to form source and drain regions; thereafter forming a third oxide layer on the sidewalls of said stacked gates; thereafter depositing a plug layer overlying said substrate and said stacked gates and filling spaces between said stacked gates; and etching down said plug layer to below the top surface of said stacked gates to form conductive plugs contacting said source and drain regions and to complete said flash memory devices.