Patent ID: 9041054
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. An electrostatic discharge (ESD) protection circuit comprising: a first well, wherein the first well is lowly-doped and has an N-type conductivity; a second well, wherein the second well is lowly-doped and has a P-type conductivity; a first region formed within the first well, wherein the first region has the P-type conductivity and functions as an anode of the ESD protection circuit; a second region formed within the second well, wherein the second region has the N-type conductivity and functions as a cathode of the ESD protection circuit; a third region formed within the first well, wherein the third region is highly-doped and has the N-type conductivity; a fourth region formed within the second well, wherein the fourth region is highly-doped and has the P-type conductivity; a fifth region formed within the second well between the first well and the second region, wherein the fifth region is highly-doped and has the P-type conductivity; and a sixth region formed within the second well, wherein the sixth region is highly-doped, has the N-type conductivity, and is electrically coupled to the fifth region; wherein a first PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the second well; a first NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the first well; and a second NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the sixth region.