Patent ID: 8553471
Filing Date: 2013-10-08
Classification: G11C

Abstract:
1. A data output buffer of a memory device, comprising: an external pin coupled to a transmission line; a driving unit coupled to the external pin and configured to selectively perform a termination operation that presents a termination impedance to the transmission line via the external pin and a driving operation that presents a drive impedance to the transmission line while read data is output to the transmission line via the external pin, wherein the driving unit comprises; a control unit configured to adjust a value of the termination impedance and a value of the drive impedance based on an output voltage apparent at the external pin during a termination mode of operation for the memory device, and to control the driving unit to selectively perform either the termination operation or the driving operation; a calibration unit configured to respectively generate a pull-up calibration code and a pull-down calibration code by comparing the output voltage with a reference voltage in response to a first calibration signal and a second calibration signal; and a switching unit configured to generate the pull-up driving code and the pull-down driving code based on the pull-up calibration code, the pull-down calibration code, a pull-up ZQ code and a pull-down ZQ code.