Patent ID: 7072236
Filing Date: 2006-07-04
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell for storing information in accordance with a change in a state; a plurality of reference cells each having at least one of a plurality of possible states of the memory cell; a first pre-sense circuit for supplying current to the memory cell and outputting a first output voltage according to a storage state of the memory cell; a plurality of second pre-sense circuits for supplying currents to the plurality of reference cells and outputting second output voltages according to storage states of the plurality of reference cells; and a sense amplifier which is constructed so that one of inputs of a differential amplification circuit is divided in parallel into the same number of pieces as the number of the reference cells, the second output voltages of the plurality of second pre-sense circuits are supplied to the divided pieces, and the first output voltage of the first pre-sense circuit is supplied to the other input of the differential amplification circuit.