Patent ID: 6891258
Filing Date: 2005-05-10
Classification: H01G,H01L,H05K

Abstract:
1. A structure, comprising: a packaged integrated circuit (IC) having a plurality of package pins disposed according to a first pattern; a printed circuit board (PCB) having a plurality of PCB lands disposed thereon according to the first pattern; a body having upper and lower surfaces, the body comprising a plurality of alternating conductive layers and dielectric layers, the outermost layers comprising dielectric layers; a plurality of lands disposed upon the upper surface of the body according to the first pattern and directly coupled to the package pins; a plurality of terminals disposed upon the lower surface of the body according to the first pattern and directly coupled to the PCB lands; and a plurality of vias through the body and orthogonal to the upper and lower surfaces, each via providing an electrically conductive path between an associated land and an associated terminal, wherein; each conductive layer in the body comprises one or more electrically insulating keepouts disposed around at least a subset of the vias.