Patent ID: 6815334
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method for forming a multi-layer metal line of a semiconductor device, comprising the steps of:forming a first insulating film having a low dielectric constant on a semiconductor substrate having a lower metal line thereon; planarizing the first insulating film until a predetermined thickness of the first insulating film remains on the lower metal line; removing the remaining portion of the first insulating film on the lower metal line by plasma etching to expose the lower metal line; forming an etch barrier layer on the entire surface; forming a second insulating film having a low dielectric constant on the etch barrier layer; forming an oxide film on the second insulating film; selectively etching the oxide film, the second insulating film and the etch barrier layer to form a via contact hole exposing the lower metal line, wherein the step of etching the second insulating film is performed under the condition of a pressure ranging from 30 to 50 mTorr, power ranging from 1300 to 1600 watt, C4F8, having a flow rate ranging from 10 to 20 sccm, CO having a flow rate ranging from 150 to 250 sccm and N2 having a flow rate ranging from 100 to 150 sccm so that a protective film is formed on a sidewall of the via contact hole; forming an adhesive film/diffusion barrier film on the entire surface of the resulting structure; and forming a contact plug filling the via contact hole, and forming an upper metal line contacting the contact plug.