Patent ID: 6372551
Filing Date: 2002-04-16
Classification: H01L

Abstract:
An Integrated Circuit packaging method, comprising the steps of:(1) preparing a lead frame having a die-pad portion and a finger portion; (2) preparing an encapsulating mold including a top inserted mold and a bottom inserted mold, wherein the top inserted mold is formed with a first side-wall cavity structure while the bottom inserted mold is formed with a second side-wall cavity structure; (3) clamping the lead frame between the top inserted mold and the bottom inserted mold in such a manner that the die-pad portion and the inner end of the finger portion of the lead frame would be substantially airtightly covered between the top inserted mold and the bottom inserted mold; (4) filling a molding material into the first side-wall cavity structure in the top inserted mold to thereby form a top side-wall structure having a centrally-hollowed portion, and also into the second side-wall cavity structure in the bottom inserted mold to thereby form a bottom side-wall structure having a centrally-hollowed portion; (5) removing the encapsulating mold; (6) performing a die-attachment process to attach at least one Integrated Circuit chip on the die-pad portion of the lead frame; (7) performing a wire-bonding process to electrically couple the Integrated Circuit chip to the inner end of the finger portion of the lead frame, and in which step the bottom side-wall structure is placed on a heat block shaped in such a manner that allows the die-pad portion and the inner end of the finger portion to come in direct thermal contact with the heat block through the centrally-hollowed portion of the bottom side-wall structure; (8) Removing the heat block; and (9) performing a lidding process to cover a lid onto the opening of the top side-wall structure.