Patent ID: 6255695
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A semiconductor device comprising:an n-channel field effect transistor and a p-channel field effect transistor both disposed over a substrate, each of said n-channel and p-channel field effect transistors comprising:a source region, a drain region, and a channel forming region disposed between the source and drain regions;a gate electrode disposed adjacent to the channel forming region through a gate insulating film; anda source electrode connected to the source region,wherein said n-channel and p-channel field effect transistors constitute an inverter circuit having an input terminal and an output terminal and a common drain electrode,wherein said gate electrode of said n-channel field effect transistor is connected with said gate electrode of said p-channel field effect transistor, and said input terminal is connected with both of said gate electrodes of said n-channel and p-channel field effect transistors,wherein said common drain electrode is connected to the drain regions of said n-channel and p-channel field effect transistors, and said output terminal is connected to said common drain electrode,wherein in at least one of the n-channel and p-channel field-effect transistors, a distance between the gate electrode and the common drain electrode is longer than a distance between the gate electrode and the source electrode,wherein said source electrode connected to the source region of said n-channel field effect transistor is connected to a ground potential, andwherein said source electrode connected to the source region of said p-channel field effect transistor is connected to a power supply line.