Patent ID: 8468406
Filing Date: 2013-06-18
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a TDI input lead, TMS input lead, TCK input lead, and TDO output lead; B. a first gate having an input coupled to the TMS input lead, a first enable input, and a first gated TMS output; C. a second gate having an input coupled to the TCK input lead, a first enable input, and a first gated TCK output; D. a first access port having an input connected to the TDI input lead, an input connected to the first gated TMS output, an input connected to the first gated TCK output, and a data output coupled to the TDO output lead; E. a third gate having an input coupled to the TMS input lead, a second enable input, and a second gated TMS output; F. a fourth gate having an input coupled to the TCK input lead, a second enable input, and a second gated TCK output; G. a second access port having an input connected to the TDI input lead, an input connected to the second gated TMS output, an input connected to the second gated TCK output, and a data output coupled to the TDO output lead; H. an inverter having an input connected to the TCK input lead and an output; and I. an access port selector having a port select register and a state machine controller, the port select register having an input coupled to the TDI input lead, control inputs, a first enable output connected to the first enable inputs of the first and second gates, and a second enable output connected to the second enable inputs of the third and fourth gates, the state machine controller having an input coupled to the TMS input lead, an input coupled to the output of the inverter, and control outputs connected to the control inputs of the port select register.