Patent ID: 6449277
Filing Date: 2002-09-10
Classification: H04L,H04Q

Abstract:
In ATM systems which comprises an AAL layer, an ATM layer, and an ATM physical layer and transmits packet data from a terminal to an ATM switch by using 48 bytes in a cell composed of 53 bytes through wireless environments, an interleaver interposed between a HEC part of the ATM physical layer and the wireless transmitter, comprising:a plurality of D flip-flops for delaying an input signal from the HEC part for 1 clock time period; an ATM cell header buffer for storing an ATM cell header into a cell header buffer according to a control signal output from a write controller, or outputting data by 1 bit at a buffer according to a control signal output from a read controller; a write controller for controlling to separately store a cell header and a payload according to a start signal representative of a beginning of cell input and an interleaver signal, and generating an enabling signal for writing data in an interleaver memory and an address signal for indicating writing positions; a read controller for controlling to sequentially output data which are mixed with the header and the payload in the interleaver memory, and producing a control signal to the ATM cell header buffer for skipping 1 bit every 4 bytes; an interleaver memory for writing ATM cell payload data at a predetermined position according to a control signal output from the write controller, and producing 12 byte data which is mixed with header bits; a multiplexor for multiplexing 12 byte data output from the interleaver memory according to a controller signal from the read controller; and a D flip-flop for delaying data output from the multiplexor for a predetermined time period for accurate timing with clocks.