Patent ID: 9043537
Filing Date: 2015-05-26
Classification: G06F,G11C

Abstract:
1. A method of operating a block-erasable three-dimensional NAND flash memory array comprising: maintaining a plurality of Multi Level Cell (MLC) erase blocks as update blocks that are available to receive data updates of host data for particular host logical address ranges; programming newly-received host data to word lines of an individual update block in a first order in which lower page programming of the word lines of the update block precedes upper page programming of the word lines of the update block by X word lines, where X is equal to the number of word lines in the individual update block subsequent to programming a subset of word lines consisting of fewer than all word lines of the individual update block with lower page data, ceasing programming of newly received host data in the individual update block according to the first order; and subsequently copying data from outside the individual update block to unprogrammed word lines of the individual update block according to a second order in which lower page programming and upper page programming are performed together for a given word line.