Patent ID: 6678739
Filing Date: 2004-01-13
Classification: G06F

Abstract:
A system for compressing a test pattern set including test patterns arranged in a specific order to detect faults in a logic circuit, comprising:(a) a test pattern rearranger subsystem that rearrange the test patterns included in the test pattern set to be in ascending order of a number of undefined values included in each of the patterns; (b) an undefined value sensitizer subsystem that assigns a defined value to the respective undefined values included in each of the patterns, sensitizing the patterns; (c) a test pattern remover subsystem that removes a fault-undetectable pattern or patterns from the patterns to which the defined value or values has/have been assigned by the undefined value sensitizer subsystem; (d) an undefined value setter subsystem that sets undefined values to a parameter in each of the patterns unnecessary to fault detection; and (e) a test pattern merger subsystem that merges fault-detectable patterns included in the set that have not been removed by the test pattern remover subsystem according to a specific rule.