Patent ID: 9092257
Filing Date: 2015-07-28
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: a vector execution unit configured to execute a floating point instruction to perform a floating point operation using at least one operand identified by the instruction, wherein at least one operand of the floating point instruction is a denormal value, the vector execution unit comprising: a dot product adder including a first input that is connected to the first processing lane and a second input that is connected to the second processing lane, and the dot product adder is configured to perform at least a portion of the floating point operation using the prenormalized value, wherein the first processing lane is configured to communicate the prenormalized value through the logic of the first processing lane to the first input of the dot product adder, and the first processing lane prenormalizes the denormal value, communicates the prenormalized value through the logic to the first input of the dot product adder, and the dot product adder performs the at least a portion of the floating point operation in a single pass of an execution pipeline of the vector execution unit, wherein the floating point instruction includes the denormal value operand and a second operand, wherein the vector execution unit further comprises multiplexing logic connected between the first processing lane and the second input of the dot product adder, and the first processing lane is further configured to: