Patent ID: 6154815
Filing Date: 2000-11-28
Classification: G06F

Abstract:
A data cache unit associated with a processor, the data cache unit comprising:a first non-blocking cache level;a second non-blocking cache level coupled to the first non-blocking cache level to service misses in the first non-blocking cache level;a memory scheduling window comprising a plurality of entries holding memory accesses, each access comprising an address identifying a memory location having data that is a target of the access;a picker associated with the memory scheduling window for picking accesses from the memory scheduling window and applying the address within the picked access to the first non-blocking cache, the picker coupled to receive a control signal from the second non-blocking cache to stall the picker;a plurality of resources generating accesses directed at the first cache;an arbiter selecting one or more of the plurality of resources; andan insertion pointer pointing to a selected entry in the memory scheduling window, wherein accesses generated by the arbiter selected resources are placed in entries pointed to by the insertion pointer;the insertion pointer being operable while the picker is stalled.