Patent ID: 8451039
Filing Date: 2013-05-28
Classification: G11C

Abstract:
1. Apparatus for storing a data value, said apparatus comprising: input selecting circuitry having a scan enable input, a scan input and a functional input and configured to select for output as a selected signal in dependence upon a scan enable signal from said scan enable input one of a scan input signal from said scan input or a functional input signal from said functional input; power gated circuitry coupled to said input selecting circuitry to receive said selected signal and configured to generate an intermediate signal in dependence upon said selected signal; state storing circuitry coupled to said power gated circuitry to receive said intermediate signal and configured to store a stored signal with a value dependent upon said intermediate signal; output generating circuitry coupled to said state storing circuitry, said output generating circuitry having a retention mode input and a data value output and being configured to generate an output signal for output from said data value output in dependence upon a retention mode signal received at said retention mode input and indicating operation in one of a retention mode and a functional mode such that: (i) during said functional mode, said output signal is dependent upon said stored signal; and (ii) during said retention mode, said output signal is a predetermined retention signal; and power supply circuitry coupled to said power gated circuitry, a first power supply and a second power supply, wherein said power supply circuitry and said input selecting circuitry are configured such that: (a) during said functional mode, said input selecting circuitry selects said functional signal and said power gating circuitry connects at least a first portion of said power gated circuitry to both said first power supply and said second power supply; (b) during said retention mode, said input selecting circuitry selects said scan input signal and said power supply circuitry isolates at least said first portion of said power gated circuitry from said first power supply and connects at least said first portion of said power gated circuitry to said second power supply; and (c) during both said functional mode and said retention mode said power supply circuitry connects at least a portion of said state storing circuitry to both said first power supply and said second power supply, wherein said power supply circuitry comprises a first virtual power rail coupled to said first power supply by first power switching gates and said first power switching gates are configured to isolate said first virtual power rail from said first power supply during said retention mode.