Patent ID: 7682862
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A method comprising: providing a semiconductor substrate including a pixel array region and a logic circuit region; forming a dielectric layer composed of a first oxide material over the semiconductor substrate; forming a pad electrode over and directly contacting the dielectric layer in the logic circuit region; forming a protective layer composed of a second oxide material over and directly contacting the pad electrode and the dielectric layer; forming a via hole by selectively removing portions of the protective layer to expose a portion of the uppermost surface of the pad electrode; forming a metal layer over and directly contacting the exposed portion of the uppermost surface of the pad electrode such that the thickness of the metal layer is less than the depth of the via hole; forming a color filter over and directly contacting the protective layer in the pixel array region after forming the metal layer; and then forming a plurality of microlenses over the color filter.