Patent ID: 9208036
Filing Date: 2015-12-08
Classification: G06F

Abstract:
1. A method of operating a computational system that includes a plurality of processors each having an associated cache partitioned into lockstep and non-lockstep partitions, the method comprising: dynamically transitioning between a lockstep mode of operation and a non-lockstep mode of operation, wherein in the lockstep mode of operation, the plural processors each execute a same code sequence in temporal correspondence, and wherein in the non-lockstep mode of operation, the plural processors are capable of executing differing code sequences; maintaining for each of the associated caches both (i) a lockstep version of cache replacement state for use in the lockstep mode relative to its lockstep partition and (ii) a non-lockstep version of cache replacement state for use in the non-lockstep mode relative to its non-lockstep partition; and in the non-lockstep mode, satisfying one or more non-lockstep mode access requests based on cache hits in the lockstep partition without affecting the lockstep version of cache replacement state.