Patent ID: 6222846
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A computer system having at least one input-output platform, said input-output platform having an input-output bus, at least one input-output device, and an input-output central processing unit with a non-maskable interrupt, said computer system further having a host node having at least one central processing unit and a host operating system, said host node connected to said input-output bus of said input-output platform, said input-output platform further comprising:a mask register, said mask register capable of receiving a message, said mask register further capable of writing a MASK signal;a status register, said status register capable of receiving said message received by said mask register, said status register further capable of writing an INT signal; andcircuitry for processing said MASK signal from said mask register and said INT signal from said status register to trigger said non-maskable interrupt of said input-output central processing unit;wherein said non-maskable interrupt triggers an interrupt service routine that handles said message.