Patent ID: 6389575
Filing Date: 2002-05-14
Classification: G01R,G11C

Abstract:
A digital processing system including a program instruction store and an apparatus for checking the integrity of data stored in said program instruction store, said apparatus including a clock, an array of n latch circuits, each latch circuit having an input terminal and an output terminal, an array of n exclusive OR (XOR) gates, each XOR gate having two inputs and an output, the output terminals of the XOR gates are connected to the input terminals of respective ones of the latch circuits, the outputs of the latch circuits being connected to the inputs of the XOR gates so as to apply thereto a bit-rotated word, and an address controller connected to the program instruction store so as to cause the program instruction store to output the data stored therein in successive n-bit words to the XOR gate array in synchronism with the clocking of data from the XOR gate array into the latch circuit array.