Patent ID: 6127212
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A method for forming a complementary metal-oxide semiconductor (CMOS) transistor on a semiconductor wafer, the semiconductor wafer comprising a substrate, a first gate positioned on the substrate and used to form a p-type metal-oxide semiconductor (PMOS) transistor of the CMOS transistor, and a second gate positioned on the substrate and used to form an n-type metal-oxide semiconductor (NMOS) transistor of the CMOS transistor, the method comprising:forming first spacers on both lateral surfaces of the first gate and of the second gate;performing a first ion implantation process to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drains (HDD) of the PMOS transistor;reducing the thickness of the first spacers;performing a second ion implantation process to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as heavy doped drains (HDD) of the NMOS transistor;forming a second spacer covering each first spacer; andforming sources and drains for the PMOS transistor and the NMOS transistor, in the substrate oppositely adjacent to the first gate and second gate, respectively.