Patent ID: 9159671
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A method of manufacturing a wire in an integrated circuit, comprising: forming a wire opening in a mask; electroplating a conductive material in the wire opening; forming a cap layer on the conductive material in the wire opening and such that an uppermost surface of the cap layer is at a vertical height lower than an uppermost surface of the mask; removing the mask after the forming the cap layer; forming sidewall spacers on sides of the conductive material by: forming a spacer layer on the cap layer, on sides of the conductive material, and on horizontal upper surfaces of a seed layer; and removing portions of the spacer layer from the cap layer and from the seed layer while leaving other portions of the spacer layer on the sides of the conductive material; and forming a dielectric film on surfaces of the cap layer and the sidewall spacers.