Patent ID: 7103757
Filing Date: 2006-09-05
Classification: G06F

Abstract:
1. A computer system, comprising: a memory comprising a set of sequential instructions having a branch instruction, the branch instruction configured to conditionally or unconditionally redirect program flow to a target code sequence; a prefetch unit coupled to fetch the set of sequential instructions from the memory at a first rate; a circuit coupled between the memory and the prefetch unit for receiving the branch instruction along with the set of sequential instructions, wherein the circuit is adapted to reduce a rate at which instructions within the target code sequence are fetched from the memory, if a probability factor associated with the branch instruction indicates that it is unlikely that program flow will be redirected to the target code sequence, wherein if the rate is reduced, the rate is reduced from the first rate to a second rate, which is greater than zero, and wherein the circuit comprises: a first multiplexer configured to select a mispredict band corresponding to the probability factor; and, an arithmetic unit configured to calculate the second rate by subtracting the selected mispredict band from a first value corresponding to the first rate.