Patent ID: 6249146
Filing Date: 2001-06-19
Classification: H03K

Abstract:
An output circuit comprising:an output terminal;a first power-supply node for receiving either a first power-supply potential or a second power-supply potential;a second power-supply node for receiving the second power-supply potential;a first MOS transistor of a first channel type, having a source, a drain, a gate connected to receive a first control signal, a back gate isolated from the source in terms of potential, and a source-drain path connected between said first power-supply node and said output terminal;a second MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path directly connected between the back gate and gate of said first MOS transistor;a third MOS transistor of the first channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected at a first end to said output terminal;a fourth MOS transistor of a second channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between said second power-supply node and a second end of the source-drain path of said third MOS transistor;a first control signal generating circuit for receiving power-supply voltages which are voltages at said first power-supply node and said second power-supply node and for generating the first control signal from a plurality of input signals and for supplying the first control signal to the gate of said first MOS transistor;a fifth MOS transistor of the second channel type, having a source, a drain, a gate connected to said first power-supply node, and a source-drain path connected between an output node of said first control-signal generating circuit and the gate of said first MOS transistor; anda sixth MOS transistor of the first channel type, having a source, a drain, a gate connected to a node of the source-drain paths of the third and fourth MOS transistors, and a source-drain path connected between an output node of said first control-signal generating circuit and the gate of said first MOS transistor.