Patent ID: 6163498
Filing Date: 2000-12-19
Classification: G11C

Abstract:
A memory device comprising:a memory array having bit line outputs;an interface circuit outputting a column latch signal, a data command signal and an address associated with the memory array;a column selection line circuit configured to decode the address responsive to the column latch signal and to activate a column selection line signal associated with a selected column of the memory array based on the decoded address responsive to a leading edge of the column latch signal and to deactivate the column selection line signal responsive to a leading edge of the data command signal;a sense amplifier coupled to the bit line outputs of the memory array and having an amplified output which outputs amplified bit line data from the memory array;a column selector circuit coupled to the column selection line signal and the amplified output of the sense amplifier and outputting selected amplified bit line data from the sense amplifier associated with the selected column of the memory array responsive to the column selection line signal; anda column address latch configured to latch the address responsive to a leading edge of the column latch signal; andwherein the column selection line circuit decodes the latched address and the column selection line circuit further comprises a delay circuit to delay activation of the column selection line for a selected time after the column address latch latches the address.