Patent ID: 6583466
Filing Date: 2003-06-24
Classification: H01L

Abstract:
A vertical transistor FET memory device comprising:an array of FET cells formed in rows and columns, with the rows being orthogonally arranged with respect to the columns, with a plurality of cells in a single row having a common source region, and with the cells in a column having separate source regions, a set of trenches each having a trench sidewalls and a trench bottom in a semiconductor substrate, threshold implant regions formed within said trench sidewalls, doped drain regions near the surface of said substrate and doped source regions in the base of said device below said trenches with oppositely doped channel regions therebetween, a tunnel oxide layer over said substrate including said trenches, a blanket thick floating gate layer of doped polysilicon over said tunnel oxide layer filling said trenches to below the top of said trenches, an interelectrode dielectric layer over said floating gate layer, and a control gate layer of doped polysilicon over said interelectrode dielectric layer.