Patent ID: 7173456
Filing Date: 2007-02-06
Classification: H03K

Abstract:
1. A dynamic logic return-to-zero (RTZ) latching mechanism, comprising: a complementary pair of evaluation devices responsive to a clock signal; a dynamic evaluator, coupled between said complementary pair of evaluation devices at a pre-charged node, that evaluates a logic function based on at least one input data signal; delayed inversion logic that receives said clock signal and that outputs an evaluation complete signal being a delayed and inverted version of said clock signal; and latching logic, responsive to said evaluation complete signal and the state of said pre-charged node, that asserts the logic state of an output node based on the state of said pre-charged node during an evaluation period between an operative edge of said clock signal and the next edge of said evaluation complete signal, and that returns said output node to zero between evaluation periods, wherein said latching logic comprises: an N-channel pass device having a gate receiving said evaluation complete signal and a drain and source coupled between said pre-charged node and a pull-up control node; a first P-channel pull-up device having a gate receiving said evaluation complete signal and a drain and source coupled between a source voltage and said pull-up control node; a second P-channel pull-up device having a gate coupled to said pull-up control node and a drain and source coupled between said source voltage and said output node; and an N-channel pull-down device having a gate coupled to said pull-up control node and a drain and source coupled between said output node and ground.