Patent ID: 6631419
Filing Date: 2003-10-07
Classification: H04L

Abstract:
A system, comprising:a splitter that separates an input value into at least first, second, and third portions; a first memory addressable by the first portion of the input value and configured to output either first directly encoded output information or first pointer information; a first address generator configured to generate a first output address from the second portion of the input value and the first pointer information; a second memory addressable by the first output address and configured to output either second directly encoded output information or second pointer information; a second address generator configured to generate a second output address from the third portion of the input value, the first pointer information, and the second pointer information; and a third memory addressable by the second output address and configured to output third directly encoded output information, wherein the first pointer information includes first encoded information, first base address information, and second base address information.