Patent ID: 6806740
Filing Date: 2004-10-19
Classification: H03D

Abstract:
A phase detector circuit comprising:first, second and third latches connected in series, each of the latches having a data input, a data output and a clock input, the data output of the first latch being coupled to the data input of the second latch, the data output of the second latch being coupled to the data input of the third latch; reference signal generation circuitry having at least a first input coupled to the data output of the second latch and a second input coupled to the data output of the third latch, the reference signal generation circuitry being configured to generate an output corresponding to a reference signal; and error signal generation circuitry having at least a first input coupled to the data input of the first latch and a second input coupled to the data output of the second latch, the error signal generation circuitry being configured to generate an output that is indicative, relative to the reference signal, of phase error of a clock signal.