Patent ID: 8204731
Filing Date: 2012-06-19
Classification: G06F

Abstract:
1. A signal analyzing method for an electronic device having an on-chip network and an off-chip network, comprising: defining a number X of first power nodes and a number Y of first ground nodes in the on-chip network, wherein X and Y are positive integers; defining a number X of second power nodes and a number Y of second ground nodes in the off-chip network; assigning one of the first ground nodes as a first reference node; assigning one of the second ground nodes as a second reference node; utilizing a full wave electromagnetic simulation to analyze the off-chip network, thereby obtaining a number (X+Y−1) of first resultant nodes in the on-chip network and a number (X+Y−1) of second resultant nodes in the off-chip network, wherein each of the first resultant nodes is derived from a voltage difference between the first reference node and a corresponding node selected from the first power nodes and the first ground nodes except the first reference node, and each of the second resultant nodes is derived from a voltage difference between the second reference node and a corresponding node selected from the second power nodes and the second ground nodes except the second reference node; and mapping the second resultant nodes in the off-chip network with the first resultant nodes in the on-chip network.