Patent ID: 6388850
Filing Date: 2002-05-14
Classification: H01L,H02H

Abstract:
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), wherein said apparatus comprises:an internal circuit coupled with said first power line and said second power line; an input pad coupled to said internal circuit for inputting signals to said internal circuit; a first voltage bias circuit coupled to said first power line for biasing said first voltage bias circuit to said second power line, comprising at least one diode coupled in series, and said at least one diode comprises a first serial diode, wherein an anode of said first serial diode is coupled to said input pad, and a cathode of said first serial diode is coupled to said first power line; a first voltage clamp circuit coupled to said second power line for clamping potential level through said first voltage clamp circuit, comprising a first transistor device, wherein a source of said first transistor device coupled to said second power line, and a drain of said first transistor device coupled to said anode of said first serial diode; a second voltage bias circuit coupled to said second power line for biasing said first voltage bias circuit to said first power line; and a second voltage clamp circuit coupled to said second voltage bias circuit and said first power line for clamping potential level through said second voltage clamp circuit.