Patent ID: 7873961
Filing Date: 2011-01-18
Classification: G06F

Abstract:
1. A method of simultaneously operating multiple operating systems on a single integrated circuit, comprising: a computer system loading a supervisory operating system (SOS) on said single integrated circuit included in said computer system prior to a loading of any other operating system on said single integrated circuit, wherein said SOS manages simultaneous and independent executions of said multiple operating systems without employing task switching or emulation, and wherein said multiple operating systems includes first, second and third operating systems; said computer system providing first, second and third sets of registers in one-to-one correspondence with said first, second and third operating systems, respectively, wherein said first set of registers consists of directly mapped registers that are hardwired on and are dedicated resources of said single integrated circuit and whose access does not require an address lookup, wherein second set of registers resides in a cache storage area on said single integrated circuit and whose access requires a lookup using an identifier or an address, wherein said third set of registers resides in an external memory that is included in said computer system but is external to said single integrated circuit; said SOS assigning first, second and third tags to identify said first, second and third operating systems, respectively, wherein said first tag includes a first value indicating that said first set of registers corresponding to said first operating system consists of said directly mapped registers, wherein said second tag includes a second value indicating that said second set of registers corresponding to said second operating system resides in said cache storage area, and wherein said third tag includes a third value indicating that said third set of registers corresponding to said third operating system resides in said external memory; said SOS loading said first tag and first contents consisting of first data bits into said first set of registers that consist of said directly mapped registers, loading said second tag and second contents consisting of second data bits into said second set of registers residing in said cache storage area, and loading said third tag and third contents consisting of third data bits into said third set of registers residing in said external memory; said SOS intercepting first, second and third instructions being executed under said first, second and third operating systems, respectively, wherein said first, second and third instructions require access of said first, second and third contents, respectively; said SOS adding first, second and third identifiers respectively to said intercepted first, second and third instructions, respectively based on said first operating system being identified by said assigned first tag and executing said first instruction, said second operating system being identified by said assigned second tag and executing said second instruction, and said third operating system being identified by said assigned third tag and executing said third instruction; and said SOS initiating simultaneous access of said first, second and third contents in said first, second and third sets of registers, respectively, by said SOS dispatching and tracking said first, second and third instructions respectively to said directly mapped registers, said cache storage area, and said external memory, and respectively based on said SOS identifying first, second and third matches, wherein said first match is between said first identifier added to said first instruction and said first tag loaded into said first set of registers, wherein said second match is between said second identifier added to said second instruction and said second tag loaded into said second set of registers, and wherein said third match is between said third identifier added to said third instruction and said third tag loaded into said third set of registers.