Patent ID: 6590291
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A semiconductor device, comprising:a wiring substrate, having wiring patterns formed on first and second opposing surfaces thereof, with an insulating layer therebetween, and a solder resist layer formed on each of the first and second surfaces to cover said wiring patterns and said insulating layer, except for terminal formation portions of said wiring patterns, to which external connection terminals of a semiconductor element are connected, which terminal formation portions are exposed through the solder resist layers; at least one semiconductor element imbedded in the wiring substrate; via holes formed in the first surface of the wiring substrate to reach electrode terminals of the semiconductor element; and through holes extending between the first and second surfaces; wherein said wiring patterns on said first and second surfaces include a first conductor layer in the via hole, which first layer connects to a second conductor layer on the first surface of the substrate outside of the via hole, which second conductor layer includes at least one of the terminal formation portions, and to a third conductor layer formed in the through holes, which third conductor layer connects to a fourth conductor layer on the second surface which includes at least one of the terminal formation portions, wherein the semiconductor element and the terminal formation portions on the first and second surfaces are connected by the first through fourth conductor layers, the via holes are directly connected to the semiconductor element via the first conductor layer, and only the terminal formation portions are exposed through the solder resist layers, and wherein the terminal formation portions on a first surface of one of the semiconductor devices contacts and is directly connected to the terminal formation portions on a second surface of another of the semiconductor devices to form a stack of semiconductor devices.