Patent ID: 6209123
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A method of placing a plurality of single transistors for synthesizing a plurality of rows of transistors, each row having a row width, in a layout of a circuit using a simulated annealing algorithm, comprising:A) determining an initial placement of transistors;B) selecting a move of transistors to modify said initial placement of transistors of the layout;C) evaluating said move of transistors based, at least in part on a measure of channel routing density wherein the measure of channel routing density includes determining a maximum column density of a set of columns of transistors of the layout where the set of columns includes less than all columns of the layout, and wherein the measure of channel routing density is an incremental channel routing density that is a function of the previously determined channel routing density of the layout and of the maximum column density;D) selectively performing the move of transistors in response to said step of evaluating;E) selectively adjusting a simulated temperature of a simulated model of the circuit;F) selectively freezing the simulated model depending on the value of said simulated temperature; andG) selecting at least one new move of transistors and repeating steps (C), (D), (E), (F) and (G) until the simulated model is frozen, wherein the at least one new move changes a row width of one of the plurality of rows of transistors.