Patent ID: 6429082
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A method of manufacturing a high voltage device, comprising:providing a P-type substrate; forming an oxide layer on the P-type substrate; performing an ion implantation process through the oxide layer to form a P-well region within the P-type substrate; removing the oxide layer; forming a gate oxide layer over the P-well region; forming a gate on the gate oxide layer; forming an optional cap layer on the gate; covering a patterned implantation mask layer on the substrate, exposing a defined position of a high voltage device region; and performing a large tilt angle Nâˆ’ ion implantation process on the P-well region, thereby forming a lightly doped region within the P-well region; performing a thermal drive-in procedure so that the implanted ions further laterally extend in the P-well region under the gate, forming a spacer on a sidewall of the gate; and using the gate and the spacer as a mask, performing a self-aligned N+ ion implantation process on the P-well region, thereby forming a source/drain region.