Patent ID: 6163169
Filing Date: 2000-12-19
Classification: H03K

Abstract:
A CMOS predriver circuit having first and second outputs, comprising:a pair of NFET's with sources connected to ground and drains connected to said first output;first and second PFET's with drains connected to said drains of said pair of NFET's;first and second resistive elements with one end of each resistive element connected to the source of said first and second PFET's respectively;third and fourth PFET's with sources connected to a positive voltage supply and the drains of said third and fourth PFET's connected to a second end of said first and second resistive elements respectively;first and second cascaded inverters having a data input connected to the input of said first inverter, said data input also connected to the gates of said first PFET and one of said pair of NFET's, the output of said second inverter being connected to the gate of said fourth PFET;a third inverter having its input driven by a tri-state input, said tri-state input also connected to said second and third PFET and the other of said pair of NFET's;third and fourth NFET's having their sources connected to ground with the drain of said fourth NFET connected to said second output and the gate of said fourth NFET driven by an enable input;a fifth NFET having its source connected to the drain of said third NFET, its drain connected to said second output, and its gate driven by said data input;fifth and sixth PFET's having their sources connected to said positive voltage supply, their drains connected to said second output, the gate of said fifth PFET being connected to the output of said third inverter, said output also connected to said third NFET, and the gate of said sixth PFET being connected to said data input; anda sixth NFET with source and drain connected to the drain and source respectively of said sixth PFET and its gate connected to the output of said first inverter.