Patent ID: 7109987
Filing Date: 2006-09-19
Classification: G06T

Abstract:
1. An apparatus for dual pass adaptive tessellation comprising: a vertex grouper tessellator operably coupled to receive primitive information and an index list, wherein the index list is received from a memory device; a shader processing unit coupled to the vertex grouper tessellator, wherein during a first pass, the shader processing unit receives primitive indices and an auto-index value for each of the primitive indices; a plurality of vertex shader input staging registers operably coupled to the shader processing unit, each of the plurality of vertex shaders input staging registers coupled to one of a plurality of vertex shaders such that in response to a shader sequence output, the plurality of vertex shaders generate tessellation factors; and the tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per process vector output, a per primitive output and a per packet output.