Patent ID: 6509582
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A semiconductor apparatus fabricated with bump contacts, comprising:a semiconductor body having a first surface and a second surface; a source contact area on the first surface of the semiconductor body, showing a visible pattern for positioning source test probes; a drain contact area on the second surface of the semiconductor body; a gate contact area on the first surface of the semiconductor body and separate from the source contact area, showing a visible pattern for positioning gate test probes; a source contact metallization layer over the source contact area; a gate contact metallization layer over the gate contact area; one or more source contact probed areas each overlying and partially penetrating an exposed area of the source contact metallization layer; one or more gate contact probed areas each overlying and partially penetrating an exposed area of the gate contact metallization layer; one or more passivating layers overlying the probed areas for covering the probed areas and for electrically insulating the probed areas; solder bumps for contacting the gate and the source contact metallization layers.