Patent ID: 7982263
Filing Date: 2011-07-19
Classification: H01L

Abstract:
1. A semiconductor device having a plurality of MISFETs formed on a main surface of a semiconductor substrate, each MISFET comprising: a drain region and a source region formed in the semiconductor substrate; a channel-forming region between the source region and the drain region; a gate insulation film formed over the channel-forming region; a gate electrode formed over the gate insulation film; a drain offset region formed between the gate electrode and drain region; a well region formed under the channel-forming region and source region; a first insulation film formed over the plurality of MISFETs; a first wiring formed over the first insulation film, which is electrically connected with the source region; and a second wiring formed over the first insulation film, which is electrically connected with the drain region, wherein a second insulation film is formed over the first insulation film, the first wiring and the second wiring, wherein each unit block has a gate pad and a drain pad which are formed over the second insulation film, wherein the gate pad is electrically connected with the gate electrode, and wherein the drain pad is electrically connected with the drain region through the first wiring.