Patent ID: 8951818
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A method for preparing switch transistor, comprising: sequentially forming a control electrode, an insulation layer, an active layer, and a source/drain metal layer of the switch transistor on a glass substrate, the active layer comprising an amorphous silicon layer adjacent to the insulation layer and an n patterning the source/drain metal layer to expose the n proceeding an etching process to the exposed active layer in a way of gradually reducing etching rate to form a channel of the switch transistor, which comprises using a plasma etching with first energy to etch the exposed n wherein, the etching process is a dry plasma etching, the switch transistor is a thin film transistor, the control electrode of the switch transistor is corresponding to a gate of the thin film transistor, and the input electrode and the output electrode are a source and a drain of the thin film transistor, respectively.