Patent ID: 9123736
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a cell region and a peripheral circuit region defined therein; forming gate lines spaced apart from each other over the semiconductor substrate in the cell region; forming an interlayer insulating layer over the semiconductor substrate to cover the entirety of the gate lines; forming first contact holes spaced apart from each other in the cell region and second contact holes arranged in a matrix in the peripheral circuit region by etching a portion of the interlayer insulating layer; forming contact plugs in the cell region and first conductive layers having substantially a pillar-like shape in the peripheral circuit region by filling the first and second contact holes with a conductive material; and forming and coupling second conductive layers having metal wires coming in contact with the contact plugs, respectively, in the cell region and the first conductive layers in the peripheral circuit region in rows or columns, and forming a capacitor having electrodes having each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively.