Patent ID: 7290198
Filing Date: 2007-10-30
Classification: G06F,G11C

Abstract:
1. A memory card having first and second non-volatile memories and a memory controller for controlling operation of said first and second non-volatile memories, wherein said memory controller allocates said first and second non-volatile memories to storage areas of even and odd data of sector data, respectively; each of said first and second non-volatile memories has a plurality of sectors, a first sector of which stores management information used for performing an alternation control thereon, said alternation control being performed individually for each of said first and second non-volatile memories; said memory controller causes said first and second non-volatile memories to operate for parallel access in an access control of said first and second non-volatile memories in response to an external access instruction; and said memory controller substitutes a storage area of the access error-related non-volatile memory with another storage area in said alternation control of said first and second non-volatile memories, and issues addresses, of which a first address is for a first non-volatile memory and a second address is for a second non-volatile memory, wherein said memory controller controls issuing addresses, such that said first address and said second address indicate same location sectors, when both of said sector of said first non-volatile memory indicated by said first address and said sector of said second non-volatile memory indicated by said second address do not include an error memory cell, wherein said memory controller controls issuing addresses, such that said first address and said second address indicate different location sectors, when said sector of said first non-volatile memory does not include an error memory cell and a sector of said second non-volatile memory on same location of said sector of said first non-volatile memory indicated by said first address includes an error memory cell, and further comprising buses for connecting respective non-volatile memories to said memory controller so that said respective non-volatile memories are separately access-controlled.