Patent ID: 8981814
Filing Date: 2015-03-17
Classification: H01L,H03K,Y10T

Abstract:
1. An integrated circuit, comprising: a L-level permutable switching network (L-PSN), wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches: wherein each i-th set of the (L+1) sets of switches comprises (I[i−1]×D[i]) number of switches for i=[1:L+1]; wherein the I[i−1] number of conductors of the (i−1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective I[i−1] number of switches of the i-th set of switches for i=[1:L+1] without requiring traversal of any other conductors; a j-th level of I[j] number of conductors comprising D[j] sets of (I[j]/D[j]) number of conductors for at least one j selected from [1:L+1], a prime number k>1 and D the I[j−1] number of conductors of the (j−1)-th level of conductors are organized into (I[j−1]/D wherein at least one group of the (I[j−1]/D wherein the at least (D[j]+1) number of conductors comprises at least one conductor selected from each of the D[j] sets of conductors.