Patent ID: 7700409
Filing Date: 2010-04-20
Classification: H01L

Abstract:
1. A method comprising: providing a first integrated circuit, a second integrated circuit, a third integrated circuit, and a fourth integrated circuit, wherein the integrated circuits have a substantially similar integrated circuit design, and signal pads in common to the integrated circuits are placed symmetrically about a line through a center of the integrated circuits; creating a first integrated circuit pair by flip chip bonding the first integrated circuit to the second integrated circuit, wherein the first integrated circuit is smaller than the second integrated circuit, and wherein creating the first integrated circuit pair includes removing wire bond pads from the first integrated circuit and positioning active surfaces of the first and second integrated circuits to be facing each other prior to the flip chip bonding; creating a second integrated circuit pair by flip chip bonding the third integrated circuit to the fourth integrated circuit, wherein the third integrated circuit is smaller than the fourth integrated circuit; attaching the first integrated circuit pair to a substrate; stacking the second integrated circuit pair on the first integrated circuit pair; connecting the second integrated circuit to the substrate using wire bonding; and connecting the fourth integrated circuit to the substrate using wire bonding.