Patent ID: 7400327
Filing Date: 2008-07-15
Classification: G06F,G06T,G09G

Abstract:
1. An apparatus for a memory system, comprising: a memory controller to service memory requests issued by a plurality of memory clients to a memory with each memory request having an associated data transfer size, the memory controller providing a non-partitioned view of a memory array to the plurality of memory clients while dividing a memory access bus into individual bus partitions, each of which is a fraction of said memory access bus size, said memory controller partitioning information within said memory array into independently accessible memory partitions, said memory controller routing data between said independently accessible memory partitions and said plurality of memory clients via said individual bus partitions, said memory controller determining which memory requests are to be serviced in particular clock cycles via one or more of said independently accessible memory partitions and said individual memory bus partitions; wherein said plurality of memory clients submit variable data transfer size memory requests to the memory controller and the memory controller identifies memory requests requiring a subset of said independently accessible memory partitions and determines if another memory request can be serviced in parallel via another subset of said independently accessible memory partitions to improve throughput.