Patent ID: 8574987
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising: forming a first dielectric layer over a semiconductor layer in the NVM region and the logic region; forming a charge storage layer over the first dielectric layer in the NVM region and the logic region; patterning the charge storage layer to form a dummy gate in the logic region; patterning the charge storage layer to form a charge storage structure in the NVM region; forming a second dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the second dielectric layer surrounds the charge storage structure in the NVM region and the dummy gate in the logic region; replacing the dummy gate with a logic gate in the logic region; removing the second dielectric layer from the NVM region while protecting the second dielectric layer in the logic region; forming a third dielectric layer over the semiconductor layer and charge storage structure in the NVM region, wherein the third dielectric layer is in contact with a sidewall of the charge storage structure; and forming a control gate layer over the third dielectric layer in the NVM region.