Patent ID: 6381671
Filing Date: 2002-04-30
Classification: G06F,G11C

Abstract:
A semiconductor integrated circuit comprising memory macro structures, and an access controller,wherein each of said memory macro structures includes a plurality of memory banks having bank addresses allocated to said memory banks respectively, each of said memory banks containing a word line to be selected on the basis of a row address signal, a bit line to be selected on the basis of a column address signal so as to be connected to a data line of said memory macro structure, a memory cell provided at a point of intersection between said word line and said bit line, and a sense amplifier for latching storage information read out from said memory cell, and wherein said access controller includes an address/command generating unit for operating for every memory bank, a hit/miss judgment unit for enabling data already latched by said sense amplifier to be output to said data line in response to an access request coming after data latching, and an address self-prefetching unit for self-prefetching an access address having a predetermined offset to an external access address after access control of said memory macro structure is effected with respect to said external access address so that data in said self-prefetched address is preread from said memory cells of said memory macro structure by said sense amplifier.