Patent ID: 6373125
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A chip scale package for housing of semiconductor devices to facilitate handling, testing, and later attachment of the devices to further electrical circuitry, the package comprising:a semiconductor device having a body and an active surface; a lead frame having leads providing direct, in-line electrical contact perpendicular to the active surface of the semiconductor device thereby mininizing parasitic inductance and capacitance; controlled-collapsed-chip-connection bumps connecting the lead frame directly and without intervening structure to the active surface of the semiconductor device; at least one of a thermal slug and a ground slug and the controlled-collapsed-chip-connection bumps for attaching the slug directly and without intervening structure to the center of the active surface of the semiconductor device, and the slug is coextensive in one direction with the lead frame; and an encapsulation sealing the semiconductor device from the surrounding atmosphere.