Patent ID: 6597608
Filing Date: 2003-07-22
Classification: G11C

Abstract:
A column repair circuit of a nonvolatile ferroelectric memory device having a repair logic unit therein, the column repair circuit comprising:a memory test logic block configured to generate a redundancy active pulse (RAP) and a corresponding fail input/output (IO) number FION if a column address including a fail bit to be repaired is found during test; a power-up sensor configured to generate a power-up pulse if a stable power source voltage is sensed; a first redundancy control block configured to generate first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse; a counter configured to generate n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; a redundancy counter decoding control block configured to generate an activated coding signal ENW in response to the counter bit signal of the counter and the sixth control signal ENW; and a redundancy coding block configured to code a fail column address in response to the coding signal ENW, the first to fifth control signals, the first and second address signals ADD and ADDB, and the fail IO number FION, and coding a fail IO bus.