Patent ID: 8779303
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A semiconductor package, comprising: an integrated circuit (IC) die having a plurality of contact pads each located on a surface of the IC die; a first plurality of external leads coupled to a first portion of the plurality of contact pads, located on a first surface of the IC die, by a first wirebond assembly that attaches, at the first surface of the IC die, to the first portion of the plurality of contact pads, wherein a portion of the first plurality of external leads, the first wirebond assembly attaching to the portion of the first plurality of external leads, is coplanar with the first surface of the IC die; and a second plurality of external leads coupled to a second portion of the plurality of contact pads, located on a second surface of the IC die, by a second wirebond assembly coupled to a through silicon via (TSV) assembly, the second wirebond assembly attaching, at the second surface of the IC die, to the through silicon via assembly, wherein the first surface and the second surface are opposing surfaces of the IC die.