Patent ID: 6564312
Filing Date: 2003-05-13
Classification: G06F

Abstract:
A data processor, comprising:an arithmetic logic unit [ALU] for carrying out an arithmetic or logic operation on a first input data [OP1] and a second input data[OP2]; and stack [STCK] for storing data and for applying a data having a certain position [P(1)] in said stack [STCK] to said arithmetic logic unit [ALU] as the first input data [OP1], wherein said data processor is operable to execute an instruction [INSTR] including a first address [ADDR] corresponding to the second input data [OP2] and excluding a second address corresponding to the first input data[OP1], the first address [ADDR] indicating a memory location [REG(i)] among a plurality of memory locations, [REG], the first address [ADDR] causing a data contained in the memory location [REG(i)] to be applied to the arithmetic logic unit [ALU] as the second input data [OP].