Patent ID: 8171448
Filing Date: 2012-05-01
Classification: G06F

Abstract:
1. A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, wherein the machine readable medium, when read by a computing device, causes the computing device to implement the design structure to generate a machine-executable representation of a Booth decoder circuit, the design structure comprising: a design structure representing livelock resolution request logic that, responsive to a timeout condition in at least one of a plurality of bus units, generates a livelock resolution request signal; a first design structure element representing detection logic that detects a livelock condition in response to the generation of the livelock resolution request signal, wherein the detection logic signals an attention to a control processor responsive to presence of a livelock condition, wherein responsive to the attention, the control processor sets status information to perform one ormore actions to attempt to correct a potential livelock condition, and wherein the status information comprises a livelock resolution signal; a second design structure element representing activation logic that engages quiescing of at least a subset of a primary processing element and the plurality of support processing elements responsive to a livelock resolution signal from the control processor or a throttle signal from the control processor; and a third design structure element representing bus mode logic that engages a serialized bus mode at the bus responsive to the control processor setting the bus mode signal to a serialized mode.