Patent ID: 6696339
Filing Date: 2004-02-24
Classification: H01L,Y10T

Abstract:
A method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas, the method comprising:constructing bit line contact openings over a first portion of the active areas and cell plug openings over second portions of the active areas; depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs; forming a trench through an upper portion of a plurality of the bit line contacts and portions of the dielectric layer, the trench having a first sidewall and a second sidewall; fabricating a spacer along at least the first sidewall, the spacer being a dielectric material separate from the dielectric layer; and fabricating a bit line in the trench, the bit line electrically coupling the bit line contacts and being electrically insulated from the cell plugs.