Patent ID: 7071515
Filing Date: 2006-07-04
Classification: H01L

Abstract:
1. A NMOS transistor having an improved narrow width Vt roll-off, comprising: a substrate that includes shallow trench isolation (STI) features which are comprised of a shallow trench with sloped sidewalls and a bottom, an oxide liner formed on said shallow trench sidewalls and bottom, and an insulator layer formed on said oxide liner that fills said shallow trench and extends to a level that is above the top of said substrate, wherein a groove is formed at top corners of said shallow trench; an active area formed between two adjacent shallow trenches in said substrate, said active area having an indium doped region that is adjacent to the groove; a gate dielectric layer formed on said active areas; and a patterned gate layer formed on said gate dielectric layer wherein said gate layer extends over said adjacent shallow trenches.