Patent ID: 6472693
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor base body defining an upper main surface and a lower main surface, wherein said semiconductor base body comprises a first semiconductor layer of a first conductivity type exposed to said lower main surface; a second semiconductor layer of a second conductivity type formed on said first semiconductor layer and exposed to said upper main surface; a third semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively formed in a surface to which said third semiconductor layer is exposed, being shallower than said third semiconductor layer and inside said third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer and away from said third semiconductor layer; a sixth semiconductor layer of the second conductivity type selectively formed in a surface to which said fifth semiconductor layer is exposed, being shallower than said fifth semiconductor layer and inside said fifth semiconductor layer; and a seventh semiconductor layer of the first conductivity type selectively formed in a surface to which said sixth semiconductor layer is exposed, being shallower than said sixth semiconductor layer and inside said sixth semiconductor layer, wherein a surface to which said third semiconductor layer is exposed in said upper surface includes a first region and a second region separated by said fourth semiconductor layer, and at least said second region of them is sandwiched by a surface to which said fourth semiconductor layer is exposed and a surface to which said second semiconductor layer is exposed, said device further comprising: a first gate electrode opposed to said second region with a first insulating film sandwiched therebetween; a second gate electrode opposed to a surface to which said sixth semiconductor layer is exposed in said upper surface with a second insulating film sandwiched therebetween; a first main electrode connected to said first region, said fourth semiconductor layer and said seventh semiconductor layer; and a second main electrode connected to sa id lower main surface, and wherein a transistor including said second semiconductor layer, said fifth semiconductor layer and said sixth semiconductor layer does not operate even when a predetermined voltage is applied to said second gate electrode and said first main electrode, respectively.