Patent ID: 6130554
Filing Date: 2000-10-10
Classification: H03K

Abstract:
A programmable integrated circuit, comprising:a plurality of routing resource structures, each of the routing resource structures extending in a first dimension parallel with each of the other routing resource structures, each of the routing resource structures comprising:a plurality of linearly extending wire segments, the wire segments being substantially collinearly disposed with respect to one another in the first dimension;a plurality of unprogrammed antifuses, a respective one of the antifuses being disposed between each respective pair of adjacent wire segments; anda plurality of transistors, a respective one of the transistors disposed electrically in parallel with a corresponding respective one of the antifuses; anda test circuit having a common node and an output node, the common node being couplable to a selected one of the routing resource structures, a first digital logic value being present on the output node in a test mode if an amount of current is not flowing through the selected one of the routing resource structures, a second digital logic value being present on the output node in the test mode if the amount of current is flowing through the selected one of the routing resource structures.