Patent ID: 8848460
Filing Date: 2014-09-30
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of data buses each extending in a first direction; a memory cell area having a first side extending in a second direction different from the first direction; a buffer area located along the first side of the memory cell area, the buffer area including a plurality of buffer circuits each connected to an associated one of the data buses, wherein each of the data buses has a first portion located over the memory cell area and a second portion located over the buffer area, the first portions of the data buses are arranged at a first pitch in the second direction, the second portions of the data buses are arranged at a second pitch in the second direction, and the second pitch is smaller than the first pitch; and a pad area in which a plurality of external terminals are arranged in the second direction, wherein the buffer area is located between the memory cell area and the pad area.