Patent ID: 8289850
Filing Date: 2012-10-16
Classification: G06F,Y02D

Abstract:
1. An interconnect bandwidth throttler, comprising: a command to be selectively issued to an interconnect, wherein the interconnect couples a central processing unit, operating at a first performance level, to other circuitry of a system such that the central processing unit issued transactions to the other circuitry, the system further comprising an average power; a throttle window parameter specifying a throttle window time period, the throttle window time period being succeeded by one or more successive throttle window time periods, wherein transactions issued on the interconnect are measured during the throttle window time period; and a maximum transactions parameter specifying a maximum number of transactions of the central processing unit sent to the interconnect during the throttle window time period; wherein the command is asserted to the interconnect when transactions to the interconnect exceed the maximum number of transactions during the throttle window time period such that the central processing unit operates at a second performance level and the average power is reduced, the second performance level being lower than the first performance level, the command being also asserted in one or more of the succeeding throttle window time periods if, during the one or more succeeding throttle window time periods, the number of transactions exceeds the maximum number of transactions.