Patent ID: 7886108
Filing Date: 2011-02-08
Classification: G06F,G11C

Abstract:
1. A method of managing memory address of a multi-level cell (MLC) based flash memory device comprising: receiving, in the MLC based flash memory device, a logical sector address (LSA) along with a data transfer request from a host computing device; extracting set, entry, page and sector numbers from the LSA with an indexing scheme; loading a set, corresponding to the set number, of partial logical-to-physical address and page usage information (PLTPPUI) into an address correlation page usage memory (ACPUM); reading a physical block number of flash memory of the MLC based flash memory device, the physical block number corresponds to the entry number in the ACPUM; and when the data transfer request is a read request, reading data from a physical page corresponding to the page number to a page buffer, and sending a requested data sector from the page buffer in accordance with the sector number received from the host computing device; when the data transfer request is a write request, writing page buffer contents to a physical page corresponding to the page number if the page buffer contents have been modified, writing a received data sector to the page buffer in accordance with the sector number received from the host computing device and setting corresponding one of a plurality of sector update flags reflecting the data sector just written into the page buffer.