Patent ID: 7519645
Filing Date: 2009-04-14
Classification: G06F

Abstract:
1. A system for performing a decimal floating point operation, the system comprising: a first register storing a first coefficient and a first exponent; a second register storing a second coefficient and a second exponent; a mechanism including exponent difference circuitry calculating an absolute difference between the first exponent and the second exponent, leading zero detect circuitry connected to the first register and the second register, rotator circuitry connected to the first register, the second register, the exponent difference circuitry and the leading zero detect circuitry, a two cycle adder connected to the first register and the second register, result selector circuitry connected to the two cycle adder, the mechanism: wherein the applying the operation based on the first assumption results in a first result and includes utilizing the two cycle adder; selecting a final result using the result selector circuitry, the selecting from the first result, the second result and the third result.