Patent ID: 6982994
Filing Date: 2006-01-03
Classification: H04J,H04L

Abstract:
1. A synchronization correction circuit comprising: synchronization signal generating section for successively receiving packets generated in accordance with a designated cycle, from an external source, and generating a packet synchronization signal in synchronization with the reception cycle of these packets; and interface control section for generating a transfer clock for each respective data element contained in said packets, on the basis of an internal clock, and making the cycle of said transfer clock corresponding to the last data element of said packet longer than the transfer clocks corresponding to the other data elements, if the actual cycle of said packet synchronization signal is longer than said designated cycle, and making the cycle of said transfer clock corresponding to the last data element of said packet shorter than the transfer clocks corresponding to the other data elements, if the actual cycle of said packet synchronization signal is shorter than said designated cycle.