Patent ID: 9208856
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A method of operating a multiple port static random access memory (SRAM) having an array of bit cells arranged in rows and columns, a first port and a second port, a first row circuit coupled to the first port, a second row circuit coupled to the second port, a first column circuit coupled to the first port, a second column circuit coupled to the second port, a first plurality of word lines along the rows and a first plurality of bit lines along the columns working together to perform accesses to the array, and a second plurality of word lines along the rows and a second plurality of bit lines along the columns working together to perform accesses to the array, wherein each bit cell of the array is coupled to a word line from the first plurality of word lines and a word line from the second plurality of word lines, comprising: during a first period of operation in which the rows being accessed by the first port are different than the rows being accessed by the second port, having a correlation in which the first port accesses the array using the first plurality of word lines and the first plurality of bit lines and the second port accesses the array using the second plurality of word lines and the second plurality of bit lines; in response to the second port switching to a row address that is the same as the row address of the first port, accessing the array for the second port using the first plurality of word lines and the first plurality of bit lines; and if the first port switches to a first different row address prior to the second port switching to a second different row address, performing a correlation swap so that the first port accesses the array using the second plurality of word lines and the second plurality of bit lines and the second port accesses the array using the first plurality of word lines and the first plurality of bit lines.