Patent ID: 7117291
Filing Date: 2006-10-03
Classification: G11C

Abstract:
1. A synchronous bank memory comprising: a plurality of first layer modules, each of which including a bank consisting of a plurality of 1-port memory cells and a port transition circuit between 1 port and N ports; a clock generator which generates an internal clock signal and sends the internal clock signal to said plurality of first layer modules; registers and buffers which receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal; an access conflict management circuit which receives the address signals from said registers and buffers and generates the port block signal when an access conflict to a bank occurs; a bank column selector arranged between said registers and buffers and said plurality of banks, which receives the read/write signal and the address signal from said registers and buffers and the data signal from said registers and buffers or said plurality of banks, generates a bank column selection signal based on the address signal to output it to said plurality of banks; and a bank row selector which receives the address signal from said registers and buffers and generates a bank row selection signal based on the address signal to output it to said plurality of banks selected by the bank row selection signal among said plurality of banks; wherein said port transition circuit activates a bank among said plurality of banks based on the bank column selection signal and bank row selection signal when no port block signal is outputted by said access conflict management circuit.