Patent ID: 6329259
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method for manufacturing a low voltage high frequency silicon power transistor applying epitaxial mesa structure using a minimized number of masks comprising the sequential steps ofselecting a highly doped n+ silicon substrate forming a transistor emitter region;applying a device isolation scheme deciding a general upper structure of transistor base/collector regions;depositing layers for a base/collector structure;masking and forming collector mesas by etching down, at least close, to the layer which will form the base region;depositing an insulating low-temperature oxide layer and creating contact holes to collector and base areas;masking and forming metalization layers down into said contact holes interconnecting the base and collector areas, respectively, anddepositing a passivation layer followed by masking and etching, thereby forming openings for further creation of base and collector contacts and bonding pads for respective base and collector metalization layers.