Patent ID: 8743637
Filing Date: 2014-06-03
Classification: G11C

Abstract:
1. A memory device comprising: a first redundant memory that includes a plurality of normal memory cell blocks and a redundant memory cell block; a second redundant memory that includes a plurality of normal memory cell blocks and a redundant memory cell block; a non-volatile memory that stores a first repair flag, a second repair flag, and repair data; a first repair flag flip-flop that stores the first repair flag stored in the non-volatile memory; a first repair data flip-flop group that stores repair data; a second repair flag flip-flop that is connected in series to the first repair flag flip-flop and that stores the second repair flag stored in the non-volatile memory; a second repair data flip-flop group that can be connected to the first repair flag flip-flop and that stores repair data; and a data transfer control circuit that supplies a clock signal to the first repair flag flip-flop, the second repair flag flip-flop, the first repair data flip-flop group, and the second repair data flip-flop group to serially transfer the second repair flag and the first repair flag stored in the non-volatile memory to the second repair flag flip-flop and the first repair flag flip-flop, and subsequently, serially outputs the repair data stored in the non-volatile memory to the first repair data flip-flop group and serially transfers the repair data of the first repair data flip-flop group and the second repair data flip-flop group, wherein the first redundant memory switches one of the plurality of normal memory cell blocks to the redundant memory cell block according to the repair data stored in the first repair data flip-flop group, and the second redundant memory switches one of the plurality of normal memory cell blocks to the redundant memory cell block according to the repair data stored in the second repair data flip-flop group.