Patent ID: 8816486
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. An I/O pad structure in a three-dimensional stacked integrated circuit (IC) with a top die and a bottom die bonded together, the I/O pad structure of each die comprising: a first vertical region including a first top metal layer and one or more semiconductor devices formed on a semiconductor substrate, the first top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad; a second vertical region disposed next to the first vertical region including a second top metal layer and brie or more through-silicon-vias (TSVs) formed'in said semiconductor substrate, the top die and the bottom die, the second top metal layer in the second vertical region serving as a second pad, wherein the top and bottom dies are bonded together in a face-to-face manner by bonding the second pad of each die together to form the three-dimensional stacked IC; a first metal connection layer electrically coupled to both the TSVs and the second pad of the top die; a second metal connection layer electrically coupled to both the TSVs and the second pad of the bottom die, wherein the first and the second metal connection layers are continuously disposed from the second vertical region to the first vertical region; a back-side metal layer in an electrical contact with the TSVs in the second vertical region, wherein external signals are provided to the semiconductor devices of the first vertical region through the back-side metal layer and the TSVs of the top die; a third pad formed in direct contact with the back-side metal layer for attaching a bonding wire thereto, wherein the external signals are provided to the third pad via the bonding wire; at least one inter-connector connecting the TSVs to the second pad for providing external signals to the second pad; and wherein the first and second metal connection layers extend continuously from the second vertical region to the first vertical region to provide the external signals to each die, and wherein the TSYs are electrically connected to the second pad and no TSV is formed in the first vertical region, thereby the I/O pad structure being used for packaging more than a single IC chip without redesigning a structure of the first vertical region.