Patent ID: 7834449
Filing Date: 2010-11-16
Classification: H01L

Abstract:
1. An integrated circuit (IC) package, comprising: an integrated circuit chip having a plurality of terminals configured in an array on a surface of the integrated circuit chip; an insulating layer on the surface; a plurality of vias through the insulating layer to provide access to the plurality of terminals; a plurality of routing interconnects each having a first portion and a second portion, the first portion of each routing interconnect being in contact with a respective terminal of the plurality of terminals through a respective via and the second portion of each routing interconnect extending over the insulating layer; and a plurality of bump interconnects, wherein each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects; wherein the first portion of each routing interconnect has a rounded shape that surrounds the respective via on a surface of the insulating layer, and the second portion of each routing interconnect has a rounded shape on the surface of the insulating layer; wherein each routing interconnect of the plurality of routing interconnects includes a third portion connected between the first and second portions; and wherein a diameter of the first portion is greater than a width of the third portion, and a diameter of the second portion is greater than the width of the third portion.