Patent ID: 6459299
Filing Date: 2002-10-01
Classification: H03K

Abstract:
A tristate buffer comprising:a logic circuit to output a H (high)-level signal when H-level clock and enable signals are input thereto; a first P-channel MOS transistor having a source connected to a power supply terminal of the tristate buffer and a gate to which the output signal of the logic circuit is supplied; a second P-channel MOS transistor having a source connected to the power supply terminal and a gate to which the output signal of the logic circuit is supplied; a third P-channel MOS transistor having a source connected to the power supply terminal, a gate connected to a drain of the second P-channel MOS transistor, and a drain connected to a drain of the first P-channel MOS transistor; a fourth P-channel MOS transistor having a source connected to the power supply terminal, a gate connected to the drain of the first P-channel MOS transistor, and a drain connected to the drain of the second P-channel MOS transistor; a first N-channel MOS transistor having a drain connected to the drains of the first and the third P-channel MOS transistors and a gate to which the output signal of the logic circuit is supplied; a second N-channel MOS transistor having a drain connected to the drains of the second and the fourth P-channel MOS transistors and a gate to which the output signal of the logic circuit is supplied; a third N-channel MOS transistor connected between a source of the first N-channel MOS transistor and a ground terminal of the tristate buffer, a first input signal being fed to a gate of the third N-channel MOS transistor; a fourth N-channel MOS transistor connected between the source of the second N-channel MOS transistor and the ground terminal, a second input signal being fed to a gate of the fourth N-channel MOS transistor; an inverter having an input terminal connected to the drains of the first and the third P-channel MOS transistors and also the first N-channel MOS transistor; a fifth P-channel MOS transistor connected between the power supply terminal and an signal output terminal of the tristate buffer, a gate of the fifth P-channel MOS transistor being connected to the drains of the second and the fourth P-channel MOS transistors and also the second N-channel MOS transistor; and a fifth N-channel MOS transistor connected between the signal output terminal and the ground termial, an output signal of the inverter being fed to a gate of the fifth N-channel MOS transistor.