Patent ID: 8549210
Filing Date: 2013-10-01
Classification: G06F

Abstract:
1. A data processing system comprising: at least one memory having a set of instructions located therein; one or more processors in communication with the memory, the processors operable to execute the set of instructions which cause the processor to: track changes for each of a plurality of memory pages for one or more primary host virtual machines; track changes to a plurality of processor states for one or more primary host virtual machines; responsive to an occurrence of a checkpoint, stop one or more of the primary host virtual machines; determine for the memory pages, if at least one particular memory page of the plurality of memory pages is a frequently changed memory page; in response to at least one particular memory page being a frequently changed memory page, mark the frequently changed memory page as writeable and copy the frequently changed memory page to a buffer; in response to a memory page being infrequently changed, mark the infrequently changed memory page as read only; resume the one or more primary host virtual machines; transmit a copy of the memory pages, the buffer, and the changes to the processor states to a secondary host; maintain a count of a number of checkpoint windows that each memory page is written to; generate a new checksum for each of the frequently changed memory pages; compare the new checksum to a previous checksum for each of the frequently changed memory pages; and responsive to the new checksum being equal to the previous checksum, decrease the count associated with each of the frequently changed memory pages.