Patent ID: 6800520
Filing Date: 2004-10-05
Classification: H01L,Y10S

Abstract:
A method of forming a memory array of a DRAM device, the method comprising:forming a plurality of cell pairs above a semiconductor substrate such that each cell pair includes first and second valve elements disposed adjacent each other and first and second charge storing elements outwardly disposed with respect to the first and second valve elements; and embedding complementary dopant atoms into the substrate such that a first concentration of complementary dopant atoms is defined within a plurality of valve regions of the substrate and a reduced second concentration of complementary dopant atoms is defined within a plurality of storage regions of the substrate, wherein the first and second valve elements of each cell pair of the plurality of cell pairs overlie corresponding first valve region of the plurality of valve regions, wherein the first and second storage elements of each cell pair of the plurality of cell pairs are electrically coupled to respective first and second storage regions of the plurality of storage regions, said embedding reducing the rate at which charge escapes from the charge storing elements during quiescent periods of operations.