Patent ID: 6199183
Filing Date: 2001-03-06
Classification: G01R

Abstract:
A method of forming a scan path network at a semiconductor integrated circuit having a clock node supplied with a clock signal, a scan-in node supplied with scan data and a scan-out node for receiving scan data outputted from scan flip-flops, said method comprising the steps of:(a) arranging a plurality of scan flip-flops,(b) calculating delay times for said clock signal supplied to said clock node to reach said scan flip-flops,(c) calculating distances between said scan flip-flops,(d) calculating skews between said scan flip-flops,(e) calculating a sum of said calculated distances and said skews,(f) deciding upon the smallest value of calculation results of said step (e), and(g) connecting said scan flip-flops between said scan-in node and said scan-out node based on the value obtained in said step (f).