Patent ID: 6560571
Filing Date: 2003-05-06
Classification: G06F

Abstract:
An apparatus for evaluating nodes of a network of an integrated circuit to determine whether or not the network complies with various design rules, the apparatus comprising:logic configured to perform a rules checker algorithm, wherein when the rules checker algorithm is performed, the rules checker algorithm evaluates at least one of the nodes of the network to determine whether or not the network complies with at least one of the design rules, wherein said at least one of the design rules is comprised of a plurality of checks, each check being capable of being performed by the rules checker algorithm in a particular amount of time, wherein less time is required for the rules checker algorithm to perform a first one of the checks than is required for the rules checker algorithm to perform a second one of the checks, and wherein the rules checker algorithm performs the first check before the rules checker algorithm performs the second check, and wherein the second check is only performed by the rules checker algorithm if performance of the first check does not provide a definitive determination as to whether or not said at least one of the design rules has been complied with by the network comprising the node being evaluated.