Patent ID: 6028453
Filing Date: 2000-02-22
Classification: G06F,G11C,H03K

Abstract:
A circuit operating under a true-single phase clock signal of first and second levels, comprising:a plurality of pipelined stages to perform an arithmetic function, each pipelined stage preforming a prescribed function and having a plurality of function blocks to implement the prescribed function, each of the function blocks having a logic circuit including:a) first and second nodes;b) means for pulling-up said first node to a first potential when the clock signal transits from the first level to said second level;c) means for pulling-down said second node to a second potential when the clock signal transits from the first level to the second level; andd) means for equalizing said first and second nodes to a third potential between said first and second potentials when the clock signal transits from the second level to the first level.