Patent ID: 7046803
Filing Date: 2006-05-16
Classification: H04L

Abstract:
1. An m-bit random keystream generating apparatus for use in an encryption system, comprising: a PS-LFSR (Parallel Shift-Linear Feedback Shift Register) with n storage stages for storing n-bit binary data, said n storage stages each divided into k sub-storages connected in series, each sub-storage having parallel storage stages, each sub-storage storing in said parallel storage stages m-bit parallel binary data received from a previous sub-storage and outputting the m-bit parallel binary data simultaneously in accordance with a system clock signal, wherein k is a minimum integer greater than the quotient of n divided by m; a buffer having m storage stages for storing m-bit parallel data received from a last sub-storage of the PS-LFSR; and m feedback connections for receiving the outputs of the sub-storages and the buffer corresponding to predetermined primitive polynomials, calculating the primitive polynomials with the received data, and outputting the calculation results as the bits of a keystream.