Patent ID: 6756797
Filing Date: 2004-06-29
Classification: G01R

Abstract:
A probe card assembly for testing integrated circuits comprising:a multi-layered dielectric plate interposed between a probe head and a printed circuit board said printed circuit board having arrayed upon its surface a first plurality of electrical contacts arranged in a pattern, said dielectric plate having arrayed upon its surface a second plurality of electrical contacts arranged in a pattern substantially matching said first plurality of electrical contacts; a planarizing interposer interposed between said dielectric plate and said printed circuit board said planarizing interposer having a pattern of holes matching the pattern of electrical contacts on said printed circuit board and said dielectric plate; a mounting ring clamped to said plate and said mounting ring attached to said printed circuit board; and a third plurality of compliant electrical connectors disposed within a multiplicity of said holes arrayed in a pattern upon said planarizing interposer said electrical connectors making electrical contact with said first plurality of electrical contacts and said second plurality of electrical contacts.