Patent ID: 9036406
Filing Date: 2015-05-19
Classification: G11C

Abstract:
1. A magneto-resistive random access memory (MRAM) device comprising: a memory cell array including a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells, the memory cell array being configured to operate in response to a word line driving signal and a column selection signal; an address input buffer configured to generate a row address and a column address based on an external address; a row decoder configured to decode the row address and generate the word line driving signal based on the decoded row address; a column decoder configured to decode the column address and generate the column selection signal based on the decoded column address; and a source line voltage generator configured to generate a source line driving voltage in response to an external power supply voltage and provide the source line driving voltage to the source line, wherein the memory cell array, the row decoder, the column decoder and the source line voltage generator are located on a same semiconductor chip, and wherein the memory cell array includes at least two memory banks on the semiconductor chip, and the source line voltage generator is at least partially located between two of the at least two memory banks.