Patent ID: 7742358
Filing Date: 2010-06-22
Classification: G11C

Abstract:
1. A power supply circuit for outputting different set potentials in response to control signals, comprising: an output terminal that outputs the set potentials; a boosting circuit that boosts, in response to an input of a boosting clock signal, a voltage supplied from a power supply and outputs the voltage to the output terminal; a control circuit that outputs the control signal; a voltage detecting circuit that detects an output potential outputted from the output terminal, compares a first reference potential and the output potential to output a first flag signal including information about a comparison result, and compares a second reference potential level higher than the first reference potential and the output potential to output a second flag signal for instructing activation or deactivation of the boosting circuit; a frequency switching circuit including a frequency dividing circuit that divides a reference clock signal and outputs a plurality of frequency divided clock signals having different frequencies, a first multiplexer that switches the frequency divided clock signals outputted with different frequencies from the frequency dividing circuit and outputs the frequency divided clock signals in response to inputs of the control signals, and a second multiplexer that outputs a reference clock signal in response to an input of the first flag signal when the output potential is lower than the first reference potential, and switches, when the output potential is higher than the first reference potential, an output to the frequency divided clock signal outputted from the first multiplexer; and a logic circuit that performs an operation based on the second flag signal and one of the reference clock signal and the frequency divided clock signal, and outputs the boosting clock signal for activating the boosting circuit; wherein the voltage detecting circuit changes levels of the first reference potential and the second reference potential in response to the inputs of the control signals, and the first multiplexer of the frequency switching circuit switches an output to the frequency divided clock signal having a higher frequency when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.