Patent ID: 6312991
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A method of forming a NAND type flash memory device, comprising the steps of:forming an oxide layer over a substrate;forming a first conductive layer over the oxide layer;patterning the first conductive layer, thereby forming a gate structure in a select gate transistor region and a floating gate structure in a memory cell region;forming a first insulating layer in the memory cell region;forming a polysilicon layer over the first insulating layer;exposing the device to an inert gas after formation of the polysilicon layer, wherein the inert gas prevents substantially the polysilicon layer from oxidizing, thereby preventing a reduction in adhesion between the polysilicon layer and a subsequently formed overlying layer;forming a metal layer over the polysilicon layer;performing an anneal wherein the metal layer and the polysilicon layer react to form a silicide layer;patterning a word line in the memory cell region, thereby forming a control gate region;forming source and drain regions in the substrate in regions adjacent the word lines, respectively;forming a second insulating layer over both the select gate transistor region and the memory cell region; andforming a first contact opening in the second insulating layer down to the gate structure and a second contact opening in the second insulating layer down to the control gate region.