Patent ID: 6720214
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A method for manufacturing a semiconductor integrated circuit that includes a logic circuit having transistors, the method comprising the steps of:forming a field insulating film having a first area in a predetermined region of a semiconductor substrate in order to manufacture a prototype semiconductor integrated circuit, the prototype semiconductor integrated circuit being usable to check whether the designed semiconductor integrated circuit operates accurately; forming transistor gate insulating films and gate electrodes in predetermined regions of the semiconductor substrate for prototyping; forming transistor impurity regions in predetermined regions surrounded by the field insulating film on the semiconductor substrate for prototyping using an impurity diffusion mask; forming an interlayer insulating film so as to cover at least the gate electrodes and the impurity regions; forming openings at predetermined positions of the interlayer insulating film; forming a wiring layer to electrically be connected to the gate electrodes and the impurity regions through the openings; testing the performance of the prototype semiconductor integrated circuit; forming a field insulating film having a second area that is larger than the first area in a predetermined region of a new semiconductor substrate when the prototype semiconductor integrated circuit performs in a desired manner; forming transistor gate insulating films and gate electrodes in predetermined regions of the new semiconductor substrate; forming transistor impurity regions in predetermined regions surrounded by the field insulating film on the new semiconductor substrate using the impurity diffusion mask; forming an interlayer insulating film so as to cover at least the gate electrodes and the impurity regions on the new semiconductor substrate; forming openings at predetermined positions of the interlayer insulating film on the new semiconductor substrate; and forming a wiring layer to electrically be connected to the gate electrodes and the impurity regions through the openings of the new semiconductor substrate.