Patent ID: 7655979
Filing Date: 2010-02-02
Classification: H01L

Abstract:
1. A high voltage gate driver integrated circuit comprising: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; and a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; wherein the level shift transistor is a LDMOS transistor and comprises: a first conductive type well region formed over the epitaxial layer; a second conductive type highly doped source region formed over the well region; a second conductive type highly doped drain region formed over the epitaxial layer to be separated from the well region in a lateral direction; a gate electrode formed on a channel formation region over the well region through a gate insulating layer; a source electrode electrically connected to the highly doped source region; and a drain electrode electrically connected to the highly doped drain region.