Patent ID: 6041089
Filing Date: 2000-03-21
Classification: H03L,H04L

Abstract:
A method for attaining bit phase synchronization, comprising the steps of:generating a control voltage with a control voltage generating circuit that includes a voltage control oscillator, said voltage control oscillator receiving said control voltage,inputting input data into a first delay gate group composed of plural delay gates which are connected in series to one another and which have signal delay quantities, each of the delay gates including a transistor and an inverter connected in series with the transistor between a power source and ground, the transistor having a gate which receives said control voltage,selecting either said input data or delayed data related to said input data and obtained from one of the delay gates in said first delay gate group and outputting the selected data,inputting said selected data into a second delay gate group composed of N delay gates (where N is an integer satisfying N.gtoreq.2),generating a bit change detecting signal for showing whether or not a change in logic level (also called a bit change) of output data from a pth-stage delay gate of said second delay gate group has happened within a specified time before and after a judgement time, by judging at the same time controlled by a reference clock signal whether or not output data of the pth-stage delay gate (where p is an integer satisfying 1.ltoreq.p.ltoreq.N) of said second delay gate group and output data of at least the (p-1)th-stage delay gate (where in case of p=1, the (p-1)th-stage delay gate is considered to be the input point of the second delay gate group) coincide in logic level with each other, and whether or not output data of said pth-stage delay gate and output data of at least the (p+1)th-stage delay gate coincide in logic level with each other,synchronizing said input data in phase with said reference clock signal by changing the selected data that is currently being outputted to another selected data according to said bit change detecting signal, and outputting the changed selected data, andcontrolling the delay gates of said first delay gate group so as to compensate for variations in the signal delay quantities of these delay gates, by varying said control voltage received by the gates of the transistors within a predetermined range to thereby vary the current available to the inverters, the predetermined range being such that the transistors do not come to be off.