Patent ID: 6181625
Filing Date: 2001-01-30
Classification: G11C

Abstract:
A semiconductor storage device comprising:a memory cell array composed of a plurality of memory cell transistors;a plurality of word lines each of which selects one of said plurality of memory cell transistors;an X decoder which activates a predetermined word line out of said plurality of word lines in response to an address signal; andmeans for supplying a reference voltage to said predetermined word line that is activated, wherein said means for supplying the reference voltage comprises:resistor means connected between a first power source end and an output end;first and second dummy cell transistors connected in series between a second power source end and said output end; andmeans for supplying the voltage developed at said output end to said predetermined word line that is activated, and wherein said first dummy cell transistors and said second dummy cell transistors are manufactured in a same manufacturing process, wherein each of said memory cell transistors stores therein data, composed of at least two bits, with a threshold voltage thereof, wherein the threshold voltage of said first dummy cell transistors is substantially equal to the threshold voltage corresponding to predetermined data stored in said memory cell transistors, and wherein the threshold voltage of said second dummy cell transistors is substantially equal to the threshold voltage of data different from said predetermined data.