Patent ID: 8984470
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A method for concurrently performing redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design, the method comprising: performing an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias; specifying a soft rule to facilitate modifying vias into redundant vias, wherein the soft rule reserves a predetermined amount of space around vias, wherein the soft rule is associated with an effort level that specifies an amount of resources that is allowed to be used to satisfy the soft rule; performing a redundant-via-insertion operation on the routing solution using the soft rule, wherein the redundant-via-insertion operation modifies a via within the set of vias into a redundant via; and performing, by computer, a timing optimization on the routing solution by iteratively,