Patent ID: 6560682
Filing Date: 2003-05-06
Classification: G06F

Abstract:
For use in a processing system containing a plurality of processors coupled to a main memory by a first common bus, a control circuit for breaking a lock-step sequence of memory requests received from said processors, said control circuit comprising:a memory request generator coupled to said first common bus for generating an additional memory request separate from the memory requests of the lock-step sequence, the additional memory request having a higher service priority than the memory requests of said lock-step sequence to perturb a timing of said lock-step sequence of memory requests; a plurality of I/O devices coupled to said main memory by a second common bus and said memory request generator is adapted to be coupled to said second common bus and further generates at least one memory request having a higher service priority than memory requests of a lock-step sequence of said I/O devices on said second common bus operable to terminate said lock-step sequence of memory requests received from said I/O devices; and wherein the additional memory request on said first common bus and said at least one memory request on said second common bus are generated at different times.