Patent ID: 6754120
Filing Date: 2004-06-22
Classification: G11C

Abstract:
A memory comprising:a. a memory array, including a plurality of memory cells; b. a plurality of bitlines, each bitline connected to at least one of the memory cells; c. a plurality of bitline sense amplifiers, each of the bitline sense amplifiers having: i. a bitline-sense-amplifier input node connected to one of the bitlines; and ii. a bitline-sense-amplifier output node; d. a plurality of read data lines, each read data line connected to one of the bitline-sense-amplifier output nodes; e. a first read sense amplifier having a first read-sense-amplifier input node connected to a first of the memory read lines, wherein the first read sense amplifier exhibits a first switching speed; and f. a second read sense amplifier having a second read-sense-amplifier input node connected to a second of the memory read lines, wherein the second read-sense amplifier exhibits a second switching speed, and wherein the first switching speed is more than fifteen percent faster than the second switching speed.