Patent ID: 6693008
Filing Date: 2004-02-17
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device comprising steps of:(a) forming a plurality of MISFETs over a semiconductor substrate and forming dummy conductor patterns over a semiconductor substrate and with a same level conductor layer as a gate electrode of said MISFETs for reducing a deposition thickness of the second insulating film formed in step (c); (b) forming a first insulating film over a main surface of said semiconductor substrate including said MISFETs to cover said main surface, said dummy conductor patterns and said MISFETs; (c) forming a second insulating film over said first insulating film; (d) polishing a surface of said second insulating film; (e) after said step (d), forming a third insulating film over said surface of said second insulating film for repairing said surface of said second insulating film; and (f) after said step (e), forming a hole between said MISFETS in said third insulating film, said second insulating film and said first insulating film by etching said third insulating film, said second insulating film and said first insulating film, wherein said first insulating film serves as an etching stopper in etching said second insulating film.