Patent ID: 6392860
Filing Date: 2002-05-21
Classification: H01L

Abstract:
An electrostatic discharge protection circuit, comprising:an NMOS transistor, of which the drain is coupled to a first node, a source is coupled to a ground, and a gate of which is coupled to a second node; a PMOS transistor, of which a source is coupled to a voltage source, a drain is coupled to the first node, and a gate is coupled to the second node; a resistor connected between the voltage source and the second node; a capacitor connected between the second node and the ground; and a gate-modulated field oxide device formed on a substrate, comprising: an isolation structure in the substrate; a gate-electrode formed over the isolation structure, isolated from the substrate by a gate-oxide layer, and coupled to the first node; a drain region in the substrate coupled to the voltage source; a source region in the substrate coupled to the ground; a deep N-well region in a bottom of the substrate; and an n-well region which is formed in the substrate between the source region and the deep N-well region.