Patent ID: 6678756
Filing Date: 2004-01-13
Classification: G06F

Abstract:
In a computer system, a method for controlling a first-in first-out (FIFO) array to facilitate data transmissions between a first device of a lower frequency domain and a second device of a higher frequency domain, wherein the FIFO array uses a write pointer to indicate a write address, a read pointer to indicate a read address, a flag to indicate the status of the write pointer and the read pointer, and a number of status parameters to indicate the status of the FIFO array, and wherein the FIFO array has M addresses, the method comprising the steps of:(a). determining whether a write data operation is performed; if so, pointing the write pointer to the next address from the write address which the write pointer pointed to previously and then proceeding to step (c); otherwise, proceeding to step (c); (b). determining whether a read data operation is performed; if so, pointing the read pointer to the next address from the read address which the read pointer pointed to previously and then proceeding to step (c); otherwise, proceeding to step (c); and (c). setting the status parameters corresponding to the status of the FIFO array currently; wherein the flag is set to a first value indicative of overflow of the FIFO array when the write pointer points to a maximum address of the FIFO array; the flag is set to a second value indicative of non-overflow of the FIFO array when the read pointer points to the maximum address of the FIFO array; and the FIFO array is controlled according to the read pointer, the write pointers, the flag and the status parameters; wherein the write operation is performed when a first control signal of the lower frequency domain is received to indicate that a first data signal from the first device is pushed into the FIFO array; wherein the read operation is performed in response to the first control signal to generate a first output signal of the higher frequency domain according to the first control signal and phase signals of the higher frequency domain, as so to transfer the first data signal to the second device; wherein the write operation is performed when a second control signal of the higher frequency domain is received to indicate that a second data signal from the second device is pushed into the FIFO array; and wherein the read operation is performed in response to the second control signal to generate a second output signal of the lower frequency domain according to the second control signal and phase signals of the higher frequency domain, as so to transfer the second data signal to the first device.