Patent ID: 8812928
Filing Date: 2014-08-19
Classification: G06F,H03M

Abstract:
1. A device, comprising: a mode register configured to store an error detection and correction (EDC) mode data, including pattern information and period information for an EDC pattern; and an EDC pattern generator configured to receive the pattern information and the period information and to generate the EDC pattern signal based on the pattern information and the period information, wherein the EDC pattern signal is a periodic signal comprising a series of signal periods based on the period information, wherein at least one signal period includes an active period and a hold period, wherein the EDC pattern signal includes in the active period a signal pattern based on the pattern information, and wherein the EDC pattern signal is in a disabled state during the hold period, wherein the pattern information comprises a first EDC pattern signal parameter including first EDC pattern signal parameter bits, wherein the signal pattern is obtained by repeating the first EDC pattern signal parameter bits during the active period, and wherein the EDC pattern generator comprises: