Patent ID: 6372521
Filing Date: 2002-04-16
Classification: H01L,Y10S

Abstract:
A method for reducing the size of microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate comprising:sawing semiconductor wafer; polishing the surface of said semiconductor wafer; depositing an epilayer on said polished surface of said semiconductor wafer, wherein microsteps are formed on the exposed surface of said epilayer; thermal oxidizing a top portion of the epitaxial layer including said exposed surface defining said microsteps and thereby forming a boundary surface between said deposited epitaxial layer and said oxidized top portion of said epitaxial layer said boundary layer relatively smoother than said exposed surface of said deposited epitaxial layer; and removing the oxidized top portion of said epitaxial layer so as to remove said microsteps and leave said relatively smoother boundary surface as the exposed top surface of the epitaxial layer.