Patent ID: 8829679
Filing Date: 2014-09-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a chip region which is formed over the semiconductor substrate; a seal ring which surrounds the chip region in plan formed over the semiconductor substrate; an outer region which surrounds an outer periphery of the seal ring in plan formed over the semiconductor substrate; a first insulating layer which is provided in the chip region and the outer region over the semiconductor substrate and includes a first interlayer dielectric film having a first dielectric constant; a second insulating layer which is provided in the chip region and the outer region over the first insulating layer and includes a second interlayer dielectric film having a second dielectric constant larger than the first dielectric constant; a first wire which is provided within the first insulating layer in the chip region; a second wire and a via which are provided within the second insulating layer in the chip region, and the second wire being electrically connected to the first wire by the via; a plurality of first metallic patterns which are provided within the first insulating layer in the outer region; and a plurality of second metallic patterns which are provided within the second insulating layer in the outer region, wherein each of the second metal patterns is provided at a position deviated from each of the first metal patterns, so as to overlap a part of the each of the first metal patterns located under the each of the second metal patterns in a direction perpendicular to a surface of the semiconductor substrate, and is spaced away from the seal ring farther than the overlapped first metal pattern.