Patent ID: 9117738
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having semiconductor elements formed therein, a first multi-layered graphene wire formed above the substrate, the first multi-layered graphene wire including a multi-layered graphene layer having a preset impurity doped therein, a second multi-layered graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate, the second multi-layered graphene wire formed wider than the first multi-layered graphene wire and including a multi-layered graphene layer in an edge portion of which the impurity is selectively doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire; and wherein each of the first and second multi-layered graphene wires includes a sequentially laminated catalytic underlying layer, catalytic metal layer and the multi-layered graphene layer from the lower-layer side.