Patent ID: 6420744
Filing Date: 2002-07-16
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a semiconductor substrate having a cell array region and a dummy cell region provided at a periphery of the cell array region; a first active region formed in the semiconductor substrate at a selected portion of the cell array region; an interlayer insulating layer formed on an entire surface of the semiconductor substrate including the first active region; a first contact plug formed in a selected portion of the interlayer insulating layer and electrically connected to the first active region; a ferroelectric capacitor and a dummy ferroelectric capacitor formed on the interlayer insulating layer, the ferroelectric capacitor being formed over the cell array region and being electrically connected to the first contact plug, and the dummy ferroelectric capacitor being formed over the dummy cell region; a second active region formed in the semiconductor substrate at a selected portion of the dummy cell region; and a second contact plug penetrating a selected portion of the interlayer insulating layer and being electrically connected to the second active region, a lower electrode of the dummy ferroelectric capacitor being electrically connected to the second contact plug to form an electrical path from the dummy ferroelectric capacitor to the second active region.