Patent ID: 9112517
Filing Date: 2015-08-18
Classification: H03L,H04L

Abstract:
1. A clock generator unit to generate a target clock signal having a target frequency, the clock generator unit comprising: a first Fractional-N phase-locked loop (FFNPLL) circuit having first phase detector circuitry, first voltage-controlled oscillator (VCO) circuitry and first Fractional-N divider circuitry, the first phase detector circuitry being operationally connected to the first VCO circuitry, the first phase detector circuitry having a FFNPLL reference input terminal and a FFNPLL feedback input terminal, the FFNPLL reference input terminal to receive a first clock signal, the first clock signal having associated thereto first clock signal Phase Noise, the FNPLL circuit being configured to have a FNPLL bandwidth that filters out the first clock signal Phase Noise, the FFNPLL to generate an intermediate clock signal as a function of the first clock signal and as a function of a FFNPLL feedback signal received at the FFNPLL reference input terminal, the intermediate clock signal being substantially free of the first clock signal Phase Noise; an Integer-N PLL (INPLL) circuit having: a second Fractional-N phase-locked loop (SFNPLL) circuit having third phase detector circuitry and second Fractional-N divider circuitry, the third phase detector circuitry having a SFNPLL reference input terminal and a SFNPLL feedback input terminal, the SFNPLL reference input terminal to receive the FFNPLL feedback signal, the second Fractional-N divider circuitry to receive the output signal from the second VCO circuitry and to generate an additional feedback signal as a function of settings of the SFNPLL, the SFNPLL feedback input terminal to receive the additional feedback signal, the third phase detector circuitry to output a control signal that is a function of the first clock signal and of the additional feedback signal, the first Fractional-N divider circuitry to receive the control signal, the FFNPLL feedback signal being a function of an output from the first VCO circuitry, the FFNPLL feedback signal also being a function of the control signal, the second VCO circuitry to output the target clock signal in accordance with the intermediate signal and in accordance with the INPLL feedback signal.