Patent ID: 6753597
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A semiconductor package, comprising:a semiconductor chip having an upper surface provided with a plurality of input/output pads thereon; a chip paddle adjacent a bottom surface of the semiconductor chip, the chip paddle having an upper surface and a lower surface; a plurality of leads surrounding the chip paddle and having upper and lower surfaces, wherein the chip paddle has a maximum thickness which exceeds a maximum thickness of each of the leads and the upper surfaces of the leads reside on a common plane which extends between the upper and lower surfaces of the chip paddle; conductive wires for electrically connecting the input/output pads of the semiconductor chip to the leads; and a package body comprised of an encapsulation material that encapsulates the semiconductor chip, the conductive wires, the chip paddle and the leads, wherein at least portions of the lower surfaces of the chip paddle and the leads are externally exposed in a common exterior surface of the package body.