Patent ID: 6534873
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A semiconductor package comprising:a flat mount board; a printed wiring board mounted on said mount board; and a semiconductor chip mounted in a cavity of said printed wiring board on said mount board and electrically connected to said printed wiring board, said printed wiring board comprising a wiring pattern formed on a surface of said printed wiring board, the wiring pattern comprising a first wiring pattern arranged to surround the cavity, a second wiring pattern located around said first wiring pattern so as to surround the cavity, and a plurality of signal pins located around said first wiring pattern so as to surround the cavity, a first copper foil forming a first plane internal layer and a second plane internal layer, a second copper foil for forming a third plane internal layer, a third copper foil for forming said first and second wiring patterns and said signal pins, a first bump for electrically connecting said first wiring pattern and said first plane internal layer, and a second bump for electrically connecting said second wiring pattern and said second plane internal layer, said first bump and said second bump formed on one surface of said third copper foil, and having a shape in which a surface contacting said first or second wiring pattern is larger than that contacting said first or second internal layer, a second prepreg formed between the other surface of said first copper foil and said one surface of said third copper foil, said first wiring pattern and said first internal layer connected electrically by said first bump extending through said second prepreg, and said second wiring pattern and said second internal layer connected electrically by said second bump extending through said second prepreg, a third bump formed on one surface of said first copper foil, a first prepreg formed between said one surface of said first copper foil and one surface of said second copper foil, said second and third plane internal layers connected electrically by said third bump extending through said first prepreg, a fourth copper foil, and a third prepreg formed between the other surface of said second copper foil and one surface of said fourth copper foil.