Patent ID: 6750525
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A non-volatile memory device having a cell array area and a peripheral circuit area on a semiconductor substrate, comprising:a selection transistor formed in the cell array area, the selection transistor including a selection gate pattern having a selection gate insulation layer and a selection gate electrode; a cell transistor formed in the cell array area, the cell transistor including a cell gate pattern having a cell gate insulation layer and a cell gate electrode, the cell gate insulation layer having a tunnel oxide layer, a silicon nitride layer and a top oxide layer, which are sequentially stacked; a high-voltage MOS transistor formed on the semiconductor substrate in the peripheral circuit area, the high-voltage MOS transistor including a high-voltage gate pattern having a high-voltage gate insulation layer and a high-voltage gate electrode; and a low-voltage MOS transistor formed on the semiconductor substrate in the peripheral circuit area, the low-voltage MOS transistor including a low-voltage gate pattern having a low-voltage gate insulation layer and a low-voltage gate electrode, wherein the low-voltage gate insulation layer is formed to a thickness less than equivalent oxide thickness of the cell gate insulation layer.