Patent ID: 7336284
Filing Date: 2008-02-26
Classification: G06F,G06T,G09G

Abstract:
1. A memory architecture comprising: a plurality of level one caches each comprising texel information and each associated with a corresponding graphics pipeline of a plurality of graphics pipelines; a common level two cache, operatively coupled to each of the plurality of level one caches, that comprises overlapping fetched texel information resulting from execution of previous memory fetch instructions, wherein the previous memory fetch instructions resulted in storage of requested texel information in at least one corresponding level one cache of the plurality of level one caches; wherein when a particular level one cache of the plurality of level one caches does not comprise overlapping fetched texel information requested by a subsequent memory fetch instruction, the level two cache is operative to transmit the overlapping fetched texel information requested by the subsequent memory fetch instruction to the particular level one cache of the plurality of level one caches; and wherein the subsequent memory fetch instruction results in storage of requested texel information at least in the particular level one cache of the plurality of level one caches.