Patent ID: 6748408
Filing Date: 2004-06-08
Classification: G06F,H03L

Abstract:
A non-integer fractional divider for dividing a clock signal (Fvco) of period (P) by a non-integer ratio (K), comprising:means (301,304) for receiving a plurality (N) of clock signals (Fvco_0 to Fvco_(Nâˆ’1)), each clock signal having a period of (P) and being equally phase shifted by a (P/N) delay one over the other; means (303,306) coupled to the receiving means for selecting a first and a second clock signals between the plurality (N) of clock signals (Fvco_0 to Fvco_(Nâˆ’1)); means (302,305,307,308) responsive to the receiving means for combining the first and the second selected clock signals and for outputting a divided clock signal (Fvco/K), wherein the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio (K) and an enabling time of each selected clock signal is respectively representative of a duration of a low level and a high level of the divided clock signal, the duration of the low level and the duration of the high level being adjustable based at least in part on an adjustable decomposition of the non-integer ratio (K) into a sum (K0+K1).