Patent ID: 6355501
Filing Date: 2002-03-12
Classification: H01L

Abstract:
A method of fabricating a three-dimensional integrated circuit (IC) assembly, the assembly formed by a plurality of individual silicon-on-insulator (SOI) chips, each of the SOI chips comprising a handler making mechanical contact to a first metallization pattern, the first metallization pattern making electrical contact to a semiconductor device, the semiconductor device making an electrical connection to a second metallization pattern positioned on an opposite surface of the semiconductor device, the method of fabricating the three-dimensional IC assembly comprising the steps of:a) providing a substrate having a third metalized pattern on a first surface of the substrate; b) aligning one of the SOI chips on the first surface of the substrate, by having the second metallization pattern of the SOI chip make electrical contact with the third metalized pattern of the substrate; c) removing the handler from the SOI chip, exposing the first metallization pattern of the SOI chip; d) aligning a second one of the SOI chips with the first SOI chip, having the second metallization pattern of the second SOI chip make electrical contact to the exposed first metallization pattern of the first SOI chip; and e) repeating steps c) and d) for mounting subsequent SOI chips one on top of each other.