Patent ID: 8129776
Filing Date: 2012-03-06
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a memory cell array area; a peripheral circuit area provided on a periphery of the memory cell array area; and a boundary area having a specific width provided between the memory cell array area and the peripheral circuit area, the memory cell array area comprising a cell area including a plurality of nonvolatile semiconductor memory cells, a plurality of linear wirings extending from inside of the cell area to outside thereof, the boundary area comprising a plurality of lower layer wirings provided in a lower layer than the plurality of linear wirings and electrically connected to the plurality of linear wirings, and the peripheral circuit area comprising a plurality of upper layer wirings provided in a upper layer than the plurality of lower layer wirings and electrically connected to the plurality of linear wirings via the plurality of the lower layer wirings, and a plurality of peripheral transistors electrically connected to the plurality of linear wirings via the plurality of the lower layer wirings and the upper layer wirings.