Patent ID: 6829154
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A ferroelectric memory device, comprising:a cell array block having a bitline structure including a main bitline and a plurlaity of sub bitlines, the main bitline connected to a column selection controller, and the plurality of sub-bitlines having both terminals connected to the main bitline, respectively, and connected to a plurality of unit cells; a data bus unit connected to the column selection controller; and a control circuit unit including a sense amplifier array connected between a data I/O buffer and a sense amplifier data bus connected to the data bus unit, wherein a plurality of the cell array blocks are arranged like a matrix, the control circuit unit is disposed in a first center line of symmetry wherein the first center line is parallel to the main bitline, and the data bus unit is disposed in a second center line of symmetry wherein the second center line is vertical to the main bitline.