Patent ID: 6718510
Filing Date: 2004-04-06
Classification: G11B,H03M,H04L

Abstract:
A data processing method comprising:processing digital data, in units of bytes to constitute one information data block in (MÃ—N) bytes of M rows and N columns; arranging data, in units of bytes in the information data block, so that data is arranged in a data transmission order from the 0th column to the (Nâˆ’1)-th column for each row while data is arranged in a data transmission order from the 0th row to the (Mâˆ’1)-th row; arranging a (KÃ—M) rows Ã—N columns matrix block which is a set of the information data blocks, and which is constituted of K information data blocks composed of information data blocks from the 0th information data block to the (Kâˆ’1)-th information data block which continue in the data transmission order; creating on each column of(KÃ—M) bytes of the matrix block, an error-correcting word of PO-a (KÃ—Q) or PO-a ((K/2)Ã—Q) bytes at least with respect to only even-number data (KÃ—M/2) bytes, and creating an error-correcting word of PO-b (KÃ—Q) or PO-b ((K/2)Ã—Q) bytes at least with respect to only odd-number data (KÃ—M/2) bytes; scattering and arranging PO-a and PO-b into K information data blocks constituted of (MÃ—N) bytes of M rows and N columns; forming each column of N columns as (KÃ—(M+Q)) or (KÃ—(M+2Q)) bytes of Reed-Solomon code PO (Q is an integer of 1 or more); and adding the-error-correcting word P bytes for each row of N bytes and each row of(KÃ—(M+Q)) or (KÃ—(M+2Q)) rows being formed as (N+P) byte Reed Solomon code PI; whereby as an overall block an error-correcting product code block is realized, which constitutes (KÃ—(M+Q)Ã—(N+P)) or (KÃ—(M+2Q)Ã—(N+P)) bytes Reed-Solomon error-correcting word having K information data block of (KÃ—MÃ—N) bytes as an information portion.