Patent ID: 6301137
Filing Date: 2001-10-09
Classification: H02M

Abstract:
A leg current estimator combination for estimating the load current in each of the legs A, B and C of a three-phase load, each leg being driven by a controlled power driver such as a pulse-width modulated field-effect transistor (FET) pair or insulated gate bipolar transistor (IGBT) pair, comprising:a) a low-resistance leg resistor in each leg of the load and means for deriving the voltage across each said resistor;b) a first differential amplifier receiving as its two inputs the voltage across the resistors for legs A and C of the load and producing a first analog output signal representing the difference between the two inputs thereto;c) a second differential amplifier receiving as its two inputs the voltage across the resistors for legs B and C of the load and producing a second analog output signal representing the difference between the two inputs thereto;d) a first analog/digital converter for converting the output of the first differential amplifier to a digital signal;e) a second analog/digital converter for converting the output of the second differential amplifier to a digital signal;f) a leg A output circuit comprising in series a leg A output combiner receiving as a first input the output of the first analog/digital converter, a leg A integrator for integrating the output of the leg A combiner, and a leg A output amplifier for providing an output signal representing the estimated leg A load current;g) a leg C output circuit comprising in series a leg C output combiner receiving as a first input the output of the second analog/digital converter, a leg C integrator for integrating the output of the leg C combiner, and a leg C output amplifier for providing an output signal representing the estimated leg C load current;h) an intermediate combiner receiving as a first input the output of the first analog/digital converter and receiving as a second input the output of the second analog/digital converter and producing an intermediate output signal representing the difference between the two input signals thereto;i) a leg B output circuit comprising in series a leg B output combiner receiving as a first input the intermediate output signal, a leg B integrator for integrating the output of the combiner, and a leg B output amplifier for providing an output signal representing the estimated leg B load current;j) a leg A feedback loop comprising a leg A multiplier and a leg A feedback combiner connected in series, the leg A multiplier receiving as a first input the output of the leg A output amplifier and as a second input a signal representing the value (M-.alpha.)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg A multiplier, said multiplier output signal being fed as a first input to the leg A feedback combiner;k) a leg B feedback loop comprising a leg B multiplier and a leg B feedback combiner connected in series, the leg B multiplier receiving as a first input the output of the leg B output amplifier and as a second input a signal representing the value (M-.beta.)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg B multiplier, said multiplier output signal being fed as a first input to the leg B feedback combiner;l) a leg C feedback loop comprising a leg C multiplier and a leg C feedback combiner connected in series, the leg C multiplier receiving as a first input the output of the leg C output amplifier and as a second input a signal representing the value (M-.gamma.)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg C multiplier, said multiplier output signal being fed as a first input to the leg C feedback combiner; the leg A feedback combiner receiving as a second input the output of the leg C multiplier, and producing an output signal representing the difference between the two inputs thereto;the leg B feedback combiner receiving as a second input the output of the leg A multiplier, and producing an output signal representing the difference between the two inputs thereto;the leg C feedback combiner receiving as a second input the output of the leg B multiplier, and producing an output signal representing the difference between the two inputs thereto;the leg A output combiner receiving as a second input the output of the leg A feedback combiner with optional amplification and producing as the leg A output combiner signal the difference between the two inputs thereto;the leg B output combiner receiving as a second input the output of the leg B feedback combiner with optional amplification and producing as the leg B output combiner signal the difference between the two inputs thereto;the leg C output combiner receiving as a second input the output of the leg C feedback combiner with optional amplification and producing as the leg C output combiner signal the negative of the sum of the two inputs thereto;whereineach of the leg A, leg B and leg C combiners produces a respective output signal value u.sub.A, u.sub.B, or u.sub.C (each value generically referred to as ""u"");each of the integrators processes its associated input signal value u to produce an output signal value ##EQU6##where s is the Laplace operator;each of the leg A, leg B and leg C output amplifiers has a gain z;M is the half-period of the pulse-width modulation carrier signal;and the values .alpha., .beta. and .gamma. are derived from the equations.alpha.=V.sub.L sin(.omega.t-.PHI.).beta.=V.sub.L sin(.omega.t-.PHI.-2.pi./3).gamma.=V.sub.L sin(.omega.t-.PHI.-4.pi./3)where V.sub.L is the amplitude, .omega. is the load voltage frequency, and .PHI. is the phase angle of the load voltage frequency;and whereby the estimated load currents in the respective legs A, B, C of the load are given by the solutions of the equations ##EQU7##whereI.sub.aE is the estimated current in leg A;I.sub.bE is the estimated current in leg B;I.sub.cE is the estimated current in leg C; andt is time.