Patent ID: 6158026
Filing Date: 2000-12-05
Classification: G11B,H04N

Abstract:
A scrambling apparatus for performing a scrambling process corresponding to a M sequence, comprising:means for squaring a first matrix of a generated polynomial for generating said M sequence of n degrees, obtaining the result as a second matrix, and treating said M sequence as data of 2n bits wide with said second matrix;means for supplying an initial value of said M sequence as input data to said first matrix and said second matrix in an initial stage and then supplying output data of said second matrix to said first matrix and said second matrix;first output means for XORing output data of said first matrix and the low order n bits of the input data and obtaining the result as the low order n bits of the output data of said first output means; andsecond output means for XORing output data of said second matrix and the high order n bits of the input data and obtaining the result as the high order n bits of the output data of said first output means.