Patent ID: 6392272
Filing Date: 2002-05-21
Classification: H01L

Abstract:
An insulating gate type semiconductor device comprising:a semiconductor substrate on which a P-type emitter layer, an N-type base layer and a P-type base layer are formed in sequence from the underside thereof to the surface thereof: a plurality of trenches arranged substantially in parallel and each recessed to a depth extending from the surface of said semiconductor substrate to an upper portion of said N-type base layer; a gate oxide layer provided on an inner surface of each of said trenches and on the surface of said semiconductor substrate; a gate wire for transmitting a voltage applied to a gate; a plurality of sets of trench gate electrodes, with one set of said trench gate electrodes being constituted by a predetermined number of said electrodes arranged in sequence, among said one set of electrodes said two trench gate electrodes disposed at both side ends being structured as channel-forming trench gate electrodes connected to said gate wires, and said remaining electrodes interposed between said two channel-forming trench gate electrodes being structured as thinning-out trench gate electrodes insulated from said gate wires; an N-type emitter layer provided on the surface of said semiconductor substrate of said P-type base layer interposed between said channel-forming trench gate electrode belonging to said one set of electrodes and said channel-forming trench gate electrode belonging to another set of electrodes adjacent to said one set of electrodes, and in the vicinity of said channel-forming trench gate electrode; a polysilicon layer, provided covering some portions or the whole of the upper surfaces of said thinning-out trench gate electrodes for said every set of electrodes, for connecting said thinning-out trench gate electrodes to each other which belong to said one set of electrodes; an insulating oxide layer provided covering a part or whole of said channel-forming trench gate and a part of said polysilicon layer, and holed with contact holes at each of potions provided with said P-type base layer and said N-type emitter layer and at a portion provided with said polysilicon layer; an emitter electrode provided covering said insulating oxide layer and connected to said P-type base layer, said N-type emitter layer and said polysilicon layer; and a collector electrode provided on said P-type emitter layer on the underside of said semiconductor substrate.