Patent ID: 7340359
Filing Date: 2008-03-04
Classification: G01R,G11C

Abstract:
1. A method for augmenting quality or reliability of semiconductor units, comprising: (a) providing at least two populations of semiconductor units that are subject to quality or reliability testing; the at least two populations including at least one quality or reliability fail candidate population and at least one other population; (b) associating test flows to the at least two populations; each test flow including a stress testing sequence; wherein the stress testing sequence for at least one of the quality or reliability fail candidate populations includes a stress test of increased duration as compared to a duration of a stress test in a test flow of at least one of the other populations; wherein the stress testing sequence for at least one of the other populations includes a stress test of increased voltage as compared to a corresponding operating voltage specification for a semiconductor unit of the semiconductor units; and (c) applying, within a sort testing stage, a corresponding test flow to each of the at least two populations and identifying any semiconductor unit which failed the stress testing sequence.