Patent ID: 8359562
Filing Date: 2013-01-22
Classification: B33Y,G03F,G06F

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: using a processor, generating a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure; using a processor, generating a second 3-D resist profile for a second process condition using the layout mask, wherein the first process condition comprises a plurality of process variables, and wherein the second process condition comprises different values of the plurality of process variables than the first process condition; generating a 3-D process variable (PV) band profile, wherein generating the 3-D PV band profile comprises combining the first 3-D resist profile with the second 3-D resist profile; and displaying a 3-D image of the 3-D PV band profile on a display.