Patent ID: 6275059
Filing Date: 2001-08-14
Classification: G01R

Abstract:
A method for predicting the operation-time-to-failure of a metal-oxide-semiconductor transistor (MOST) having a gate terminal, a drain terminal, a source terminal, and a body or substrate terminal, comprising the steps of:(a) forward biasing a first one of said p/n junctions between said base terminal and a first one of said at least two other terminals;(b) applying an operating voltage to a second one of said at least two other p/n junctions at a level not substantially higher than a predetermined operating voltage which can be safely applied to said MOST during normal operation;(c) applying a gate voltage to said gate terminal;(d) measuring a DC base current in said MOST, said MOST experiencing a current accelerated stress responsive to said preceding steps in which said DC base current increases with the interface trap concentration in said MOST; and,(e) predicting said operation-time-to-failure based on said measured DC base current.