Patent ID: 6917105
Filing Date: 2005-07-12
Classification: H01L

Abstract:
1. An integrated circuit structure including chip-scale packaging, the structure comprising: plurality of active elements in a surface of a semiconductor die; at least one conductive-material bus electrically interconnecting said active elements; said chip-scale packaging including at least one, conductive-material, input-output bump extending outwardly from said die for electrically connecting said plurality of active elements to off-die electronics, and a beam of conductive material connecting said bus to said bump; said bus having a construction wherein the conductive material forming said beam is extended to regions of said structure for thickening of said bus such that resistance of said bus is reduced, and said plurality of active elements comprises at least one row of MOSFET drain regions adjacent at least one row of MOSFET source regions, each row of MOSFET drain regions having a first said bus leading to a first input-output pad, said first input-output pad having a first said beam leading to a first said input-output bump, and each row of MOSFET drain regions having second bus leading to a second input-output pad, said second input-output pad having a first said beam leading to a second said input-output bump, wherein said conductive-material of said first beam extends superjacently said first said bus and said conductive-material of said second beam extends superjacently said second said bus and wherein for a predetermined (R