Patent ID: 6400757
Filing Date: 2002-06-04
Classification: H03H

Abstract:
A spread-spectrum-matched filter, for use as part of a spread-spectrum receiver operating on a received-spread-spectrum signal having a plurality of information bits, with the received-spread-spectrum signal generated from spread-spectrum processing each information bit with a chip-sequence signal, said filter comprising:a first plurality of shift registers for storing a first portion of a reference-chip-sequence signal; a second plurality of shift registers for storing a second portion of the reference-chip-sequence signal; a control processor for generating a clock signal having a clock rate with a clock cycle; a multiplexer, coupled to said first plurality of shift registers and to said second plurality of shift registers, responsive to the clock signal, for outputting, from said first plurality of shift registers through said multiplexer, the first portion of the reference-chip-sequence signal during a first portion of a clock cycle, and for outputting, from said second plurality of shift registers through said multiplexer, the second portion of the reference-chip-sequence signal during a second portion of the clock cycle; a plurality of data-shift registers, coupled to said spread-spectrum receiver, for shifting a plurality of input-data samples of the received-spread-spectrum signal at the clock rate; a first plurality of exclusive-OR (XOR) gates, coupled to said plurality of data-shift registers and through said multiplexer to said first plurality of shift registers and through said multiplexer to said second plurality of shift registers, responsive to said multiplexer selecting the first plurality of shift registers during the first portion of the clock cycle, for multiplying the first portion of the reference-chip-sequence signal by the plurality of input-data samples during the first portion of the clock cycle, thereby outputting a first plurality of product-output signals, and responsive to said multiplexer selecting the second plurality of shift registers during the second portion of the clock cycle, for multiplying the second portion of the reference-chip-sequence signal by the plurality of input-data samples during the second portion of the clock cycle, thereby outputting a second plurality of product-output signals; an adder tree, comprising a plurality of adder gates coupled to said first plurality of XOR gates, for summing the first plurality of product-output signals during the first portion of the clock cycle, thereby generating a first sum, and for summing the second plurality of product-output signals during the second portion of the clock cycle thereby generating a second sum; a memory, coupled to said adder tree, for storing the first sum outputted from said adder tree during the first portion of the clock cycle; a third plurality of shift registers for storing a plurality of reference-bit-sequence signals; a second plurality of exclusive-OR (XOR) gates, coupled to said memory, to said adder tree and to said third plurality of shift registers, for multiplying the reference-bit-sequence signals from said third plurality of shift registers by the stored first sum from said memory and by the second sum from said adder tree, thereby outputting a plurality of product sums; and an adder, coupled to said second plurality of exclusive-OR (XOR) gates, for adding the product sums from said second plurality of exclusive-OR (XOR) gates.