Patent ID: 9111867
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A semiconductor fabrication process comprising: forming a plurality of sacrificial gate structures over a wafer, comprising a sacrificial select gate structure formed over a non-volatile memory cell area of the wafer and one or more sacrificial gate structures formed over the wafer outside of the non-volatile memory cell area; forming a charge storage layer on a first sidewall of the sacrificial select gate structure to extend over an adjacent control channel region; depositing a polysilicon layer on the charge storage layer to cover at least top and side surfaces of the sacrificial select gate structure and the adjacent control channel region; forming a patterned etch mask on the polysilicon layer to protect a first portion of the polysilicon layer extending from the first sidewall of the sacrificial select gate structure to the adjacent control channel region; etching the polysilicon layer with the patterned etch mask in place to remove the polysilicon layer except for the first portion of the polysilicon layer; removing the patterned etch mask; anisotropically etching the first portion of the polysilicon layer to form a spacer control gate adjacent to the charge storage layer formed on the first sidewall of the sacrificial select gate structure, where the spacer control gate has an upper surface which is recessed below an upper surface of the sacrificial select gate structure; forming a planarized dielectric layer over the wafer which protects at least the spacer control gate and which exposes at least an upper surface of the plurality of sacrificial gate structures; selectively removing at least part of the plurality of sacrificial gate structures to form a plurality of gate electrode openings in the planarized dielectric layer without removing the spacer control gate, where the plurality of gate electrode openings comprises a select gate electrode opening where the sacrificial select gate structure was formed; and forming a plurality of high-k metal gate electrodes in the gate electrode openings while protecting the spacer control gate with the planarized dielectric layer, thereby forming a split-gate structure over the non-volatile memory cell area comprising the spacer control gate adjacent to the charge storage layer and a high-k metal select gate electrode formed in the select gate electrode opening.