Patent ID: 7557630
Filing Date: 2009-07-07
Classification: G11C

Abstract:
1. A sense amplifier-based flip-flop, comprising: a first current passing unit receiving a first clock signal with a first delay, the first current passing unit configured to pass current from a first node to a ground terminal if the applied first clock signal is set to a first logic level and not to pass current from the first node to the ground terminal if the applied first clock signal is set to a second logic level; a second current passing unit receiving a second clock signal with a second delay, the second delay and the first delay not being the same, the second current passing unit configured to pass current from a second node to the ground terminal if the applied second clock signal is set to the first logic level and not to pass current from the second node to the ground terminal if the applied second clock signal is set to the second logic level; a first latch configured to output the first logic level to a first output terminal if an initial clock signal is set to the second logic level and to output an evaluation signal pair corresponding to an input signal pair to the first output terminal if the initial clock signal is set to the first logic level; a second latch configured to latch the evaluation signal pair output from the first output terminal and to transfer the latched evaluation signal pair to a second output terminal; and first and second clock signal slope controllers for generating the first and second clock signals having the first and second delays, respectively; wherein the first and second current passing units are connected between a current passing node pair of the first latch and the ground terminal, and the first and second current passing units are turned on if the first and second clock signals, respectively, transition from the second logic level to the first logic level so as to pass currents from the first and second nodes, respectively, to the ground terminal.