Patent ID: 7627625
Filing Date: 2009-12-01
Classification: G06F

Abstract:
1. An adder circuit for summing a plurality of addends from multi-bit words comprising: a network of n-input carry-save adder circuits each having a first number of sum outputs and a second number of carry outputs, the adder circuits being arranged in a plurality of columns each column corresponding to a predetermined bit position in the sum, and being arranged in a plurality of levels, the first level receiving a number of addends from corresponding bit positions of selected ones of the plurality of words and the lower levels each receiving addends from one or more of (i) corresponding bit positions of other selected ones of the plurality of words, (ii) sum outputs from a higher level adder circuit in the same column, and (iii) carry outputs from a higher level adder circuit in a column corresponding to a less significant bit position, at least one of the levels receiving addends corresponding to a calculation involving another one of the words, wherein the number of n-input adders in each column varies according to the bit position.