Patent ID: 6147901
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A semiconductor memory having a unit cell, said unit cell comprising a stacked structure including:a first semiconductor layer of a first conductivity type;a second semiconductor layer of an intrinsic type disposed on the first semiconductor layer so that conduction and valance band edges smoothly continue to those of the first semiconductor layer respectively;a third semiconductor layer of a second conductivity type opposite to said first conductivity type, being held in an electrically floating state, disposed on the second semiconductor layer so that conduction and valance band edges smoothly increase from those of the second semiconductor layer respectively so as to have a potential maximum of band diagram in the third semiconductor layer;a fourth semiconductor layer of said intrinsic type disposed on the third semiconductor layer so that conduction and valance band edges smoothly decrease from those of the third semiconductor layer respectively; anda fifth semiconductor layer of said first conductivity type disposed on the fourth semiconductor layer so that conduction and valance band edges smoothly continue to those of the fourth semiconductor layer respectively,wherein a voltage is applied between said first and fifth semiconductor layers so that a potential barrier height defined by the potential maximum varies with a polarity and a level of said voltage, configured such that majority carriers surmount the potential maximum.