Patent ID: 8339838
Filing Date: 2012-12-25
Classification: G11C

Abstract:
1. A memory comprising: a plurality of memory cells arranged in rows and columns; a plurality of word lines running in a row direction; a plurality of bit line pairs running in a column direction for reading and writing memory cell data; and a plurality of write enable lines running in a column direction; where the plurality of memory cells comprises a plurality of static random access memory (SRAM) cells, each comprising: a memory unit comprising two cross-coupled inverters for storing data at first and second internal nodes; two data access devices respectively coupled to the first and second internal nodes and controlling the cross-coupled inverters to enable data to be written from a pair of external nodes under control of a write enable line supplied to the SRAM cell; and two read port devices respectively connected between the first and second internal nodes and a bit line pair supplied to the SRAM cell to enable data to be read from the memory unit under control of a word line supplied to the SRAM cell when the data access devices are turned off, where each read port device comprises a pull up device coupled to an external node, where each read port device comprises: a first transistor which is source-drain coupled between one of the pair of external nodes and one bit line of the bit line pair supplied to the SRAM cell and which is gated by the word line supplied to the SRAM cell; a second transistor which is source-drain coupled between one of the pair of external nodes and a first ground reference voltage and which is gated by one of the first and second internal nodes; a third transistor which is source-drain coupled between one of the pair of external nodes and a pull up node and which is gated by the other of the first and second internal nodes; and a fourth transistor which is source-drain coupled between the pull up node and a second supply reference voltage and which is gated by the write enable line supplied to the SRAM cell.