Patent ID: 9170282
Filing Date: 2015-10-27
Classification: G01R,H02M,Y02B

Abstract:
1. An integrated circuit comprising: voltage generating circuitry configured to receive a supply voltage and to generate an on-chip voltage from the supply voltage in response to clock pulses of a voltage generation clock signal; a circuit block configured to receive the on-chip voltage from the voltage generating circuitry; and clock control circuitry configured to control transmission of the clock pulses of the voltage generation clock signal to the voltage generating circuitry; wherein the clock control circuitry is configured to receive a reference voltage and a digital offset value comprising a binary numeric value identifying an offset; and the clock control circuitry is configured to suppress transmission of the clock pulses of the voltage generation clock signal to the voltage generating circuitry if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value.