Patent ID: 7222273
Filing Date: 2007-05-22
Classification: G11C

Abstract:
1. An apparatus that tests a semiconductor memory device, the apparatus comprising: a main tester, which generates a plurality of first input test pattern signals with a first frequency, a first program control signal, and a second program control signal, receives a plurality of first output test pattern signals with the first frequency, and detects an operating performance of the semiconductor memory device; an input frequency converter, which converts the first input test pattern signals into a plurality of second input test pattern signals with a second frequency in response to the first program control signal, and outputs the second input test pattern signals to the semiconductor memory device; and an output frequency converter, which converts a plurality of second output test pattern signals with the second frequency received from the semiconductor memory device into the first output test pattern signals in response to the second program control signal, and outputs the first output test pattern signals.