Patent ID: 7545228
Filing Date: 2009-06-09
Classification: H03H,H03L

Abstract:
1. A method for generating a temperature-compensated timing signal, the method comprising: generating a first final count of oscillations of a first microelectromechanical (MEMS) resonator, wherein the first final count spans a current update interval; generating a second final count of oscillations of a second MEMS resonator within the current update interval, wherein the first final count and the second final count are used to compute a final target DCO count; generating a third final count of oscillations of a digitally controlled oscillator (DCO) within the current update interval, wherein the third final count and the final target DCO count are used to compute a final loop error signal; generating a first intermediate count of oscillations of the first MEMS resonator, wherein the start of the first intermediate count occurs at or after the start of the first final count, and the end of the first intermediate count occurs before the end of the first final count; generating a second intermediate count of oscillations of the second MEMS resonator, wherein the start of the second intermediate count occurs simultaneously with the start of the first intermediate count, and the end of the second intermediate count occurs simultaneously with the end of the first intermediate count; generating a third intermediate count of oscillations of the DCO, wherein the start of the third intermediate count occurs simultaneously with the start of the first intermediate count, and the end of the third intermediate count occurs simultaneously with the end of the first intermediate count; computing an intermediate target DCO count based on the first intermediate count and the second intermediate count; computing an intermediate loop error signal as a difference between the intermediate target DCO count and the third intermediate count; and modifying an output frequency of a temperature-dependent timing signal generated by the DCO based on either the final loop error signal or the intermediate loop error signal.