Patent ID: 8386714
Filing Date: 2013-02-26
Classification: G06F

Abstract:
1. A cache, comprising: a buffer that: buffers data to be cached from a processor, and buffers data to be destaged from cache to a storage subsystem; at least one flash memory device coupled to the buffer, the at least one flash memory device: comprising a plurality of logical partitions, wherein each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of pages, and caches the data to be cached from the buffer, and wherein the cached data are accessible by the processor from the buffer and a location of the cached data within the plurality of logical partitions is accessible by the processor; and wherein, data to be cached to the flash memory device are written to a single logical partition of the plurality of logical partitions until the single logical partition has reached a pre-determined limit, and data to be cached to the flash memory device are written to the plurality of logical partitions in an order selected from the group consisting of: a sequential order of the plurality of logical partitions, an order that begins from a logical partition having a least amount of modified data and that ends with a logical partition having a most amount of modified data, an order that begins from a logical partition having a least amount of data repeatedly accessed by the processor and that ends with a logical partition with a most amount of data repeatedly accessed by the processor, and an order that begins from a logical partition having a least amount of valid data and that ends with a logical partition with a most amount of valid data.