Patent ID: 6678271
Filing Date: 2004-01-13
Classification: H04L

Abstract:
An apparatus, comprising:a) a local bus and a global bus; b) a memory resource to implement an ingress queue and an egress queue, said ingress queue to queue traffic units directed from said local bus to said global bus, said egress queue to queue traffic units directed from said global bus to said local bus, said memory resource divided into: 1) an ingress queue depth share so as to define a depth of said ingress queue; 2) an egress queue depth share so as to define a depth of said egress queue; and c) a register to store a memory space setting from which a boundary between said ingress queue and said egress queue can be determined within said memory resource, said boundary being dynamically configurable in light of traffic conditions so that said ingress queue depth share and said egress queue depth share can change in response to said traffic conditions.