Patent ID: 6859402
Filing Date: 2005-02-22
Classification: G11C

Abstract:
1. An apparatus comprising: a first transistor disposed between a first node and an output node and having its gate coupled to receive a first dynamic data signal, wherein the first transistor is inactive during a precharge phase, but is to be responsive to the first dynamic data signal during an evaluate phase to pull the output node towards a potential of the first node if a state of the first dynamic data signal activates the first transistor; a second transistor disposed between the first node and the output node and having its gate coupled to receive a second dynamic data signal, wherein the second transistor is inactive during the precharge phase, but is to be responsive to the second dynamic data signal during the evaluate phase to pull the output node towards the potential of the first node if a state of the second dynamic data signal activates the second transistor; and a third transistor disposed between a second node and the output node and having its gate coupled to receive a NOR logic of complements of the first and second dynamic data signals, wherein the third transistor is inactive during the precharge phase, but is to be responsive to complements of the first and second dynamic data signals, in which if one of the first or second transistor is made active during the evaluate phase, the third transistor remains inactive, but if the first and second transistors are inactive during the evaluate phase, the third transistor is made active to pull the output node towards a potential of the second node.