Patent ID: 6138259
Filing Date: 2000-10-24
Classification: G01R,G11C

Abstract:
A semiconductor memory testing apparatus comprising:a timing generation part generating an operation clock;a sequence control part controlling a sequence of pattern generation;a clock/select signal generating part, coupled to the timing generation part and to the sequence control part, generating a 1/2 operation clock having a frequency of 1/2 of that of the operation clock and two select signals each having a 1/2 logical high duration period followed by a 1/2 logical low duration period with a phase difference of 1/2 period of that of the 1/2 operation clock from each other;two pattern generation parts each coupled to said clock/select signal generating part and each coupled to and controlled by said sequence control part and responsive to a respective one of the two select signals supplied from said clock/select signal generating part generating pattern data and expected pattern data, respectively; andhigh-speed conversion means for multiplexing the pattern data and expected pattern data outputted from each of said pattern generation parts to obtain a high-speed pattern signal and a high-speed expected pattern signal.