Patent ID: 8120109
Filing Date: 2012-02-21
Classification: H01L

Abstract:
1. A semiconductor device having reduced junction capacitance, comprising: a substrate; a gate oxide layer provided over said substrate; a polycide gate provided on said gate oxide layer and having an oxide layer formed on a top surface and sidewalls of said polycide gate and nitride spacers formed on said sidewalls, said oxide layer positioned between said polycide gate and said nitride spacers, the polycide gate comprising a polysilicon layer, a polycide layer, and a dielectric layer, the dielectric layer forming the top surface of the polycide gate on which the oxide layer is formed; a first dopant implanted into said substrate, said first dopant having a first dosage sufficient to form a heavily doped source/drain region in said substrate adjacent said nitride spacers; a second dopant comprising the same conductivity type as said first dopant but at a lower dosage than said first dosage and implanted deeper into said substrate to form a lightly doped source/drain region in said substrate below said heavily doped source/drain region; and an amorphous layer of about 50 to 500 Angstroms provided on said gate oxide layer directly above said lightly doped source/drain region.