Patent ID: 8644072
Filing Date: 2014-02-04
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a stacked memory cell array having a laminated plurality of memory cell layers, wherein each of the individual memory cell layers has a plurality of blocks; a layer quality information storing circuit which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify the memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers; and an address converting circuit in which if an externally input address input from outside corresponds to the block in the defective memory cell layer, the externally input address is address-converted so as to correspond to the block in the normal memory cell layer such that the defective memory cell layer is isolated.