Patent ID: 8823187
Filing Date: 2014-09-02
Classification: H01L,H05K

Abstract:
1. A semiconductor package comprising: a semiconductor chip; a first insulating layer formed to cover the semiconductor chip; a wiring structure formed on the first insulating layer, and having an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between one of the wiring layers and another; and the interlayer insulating layers including an outermost interlayer insulating layer located farthest from a surface of the first insulating layer; a groove formed in the outermost interlayer insulating layer and passing through the outermost interlayer insulating layer in a thickness direction; and a buried resin layer formed on the outermost interlayer insulating layer to fill the groove, the buried resin layer having a thermal expansion coefficient closer to that of the semiconductor chip than to that of the interlayer insulating layers.