Patent ID: 6751786
Filing Date: 2004-06-15
Classification: G06F

Abstract:
Computer-readable media containing a program which, when read and executed by a computer, causes the computer to synthesize a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate, wherein the base level partitions comprise syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition, the computer-readable media comprising:first computer instructions for causing the computer to separately synthesize a plurality of independently balanced subtrees, each subtree corresponding to a separate base level partition and comprising a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area; and second computer instructions for causing the computer to synthesize a top level portion of the clock tree for conveying the clock signal from the entry point to the start point of each synthesized subtree.