Patent ID: 6639771
Filing Date: 2003-10-28
Classification: H01L,H02H

Abstract:
An electro-over-stress (EOS) protection circuit comprising:a semiconductor chip having a power pin and a ground pin and input pins; ESD protection structures in the semiconductor chip, each input pin having an ESD protection structure with a terminal connected to the ground pin and another terminal electrically connected to the power pin; an external power bus coupled to the power pin; an external ground bus that is not directly coupled to the ground pin and the external ground bus, the conduction path being enabled to conduct a ground current by a control gate with a time delay; and a transistor-bypass capacitor, having a terminal coupled to the ground pin and a terminal coupled to the external ground bus, whereby the external transistor inhibits the ground current through an internal protection diode during an electro-over-stress (EOS) pulse and prevents burnout of the ESD protection structures.