Patent ID: 6247114
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A microprocessor comprising:an instruction queue configured to receive and store instructions, wherein each instruction has an eligibility signal associated with it, wherein the eligibility signal is indicative of whether the corresponding instruction is eligible for output;a control unit coupled to the instruction queue, wherein the control unit is configured to select the oldest N eligible instructions from the instruction queue in parallel with determining which N eligibility signals correspond to the oldest N eligible instructions, wherein the control unit includes:a hierarchy of multiplexers, wherein the hierarchy has a plurality of levels, wherein the first level of the hierarchy is configured to select a first subset of instructions in the queue, wherein each subsequent level of the hierarchy is configured to select a fractional subset of the previous stage's selected subset, anda plurality of logical OR gates, wherein the OR gates are configured to receive the eligibility signals and generate a control signal for controlling a multiplexer in the hierarchy.