Patent ID: 9000820
Filing Date: 2015-04-07
Classification: H03K

Abstract:
1. A semiconductor device, comprising: an input delay circuit configured to generate a first delay signal by delaying an input signal through a common delay path whose length is determined in response to a delay control code, and generate a second delay signal by delaying the first delay signal through an additional delay path whose length is determined in response to the delay control code; a first output delay circuit configured to delay the first delay signal through a first delay path whose length is determined in response to the delay control code and output a delayed first delay signal; and a second output delay circuit configured to delay either the first delay signal or the second delay signal through a second delay path whose length is determined in response to the delay control code and output a delayed first delay signal or a delayed second delay signal, wherein when one bit among multi-bit delay control codes included in the delay control code is selectively enabled as a highest enabled bit, lower bits of the delay control code are all enabled while higher bits of the delay control code are all disabled.