Patent ID: 8362537
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. An integrated circuit including a memory array, the memory array comprising: a semiconductor body including an array of semiconductor pillars that are arranged in a series of rows and columns separated by column trenches and row trenches, wherein the respective semiconductor pillars comprise respective body regions vertically disposed between respective upper source/drain regions and respective lower source/drain regions; a first column trench disposed between pillars of a first column and pillars of a second column; a pair of parallel bitlines disposed within the first column trench and electrically isolated from one another, a first bitline of the pair coupled to an upper or lower source/drain region of the first column, and a second bitline of the pair coupled to an upper or lower source/drain region of the second column; second and third column trenches disposed, relative to the first column trench, on opposite sides of the respective first and second columns of pillars, respectively, wherein no bitlines are disposed in or adjacent to the second and third column trenches; and body region contacts disposed in the second and third column trenches and coupled to body regions of pillars in the first and second columns, respectively.