Patent ID: 6465260
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device for use in a memory cell, the method comprising steps of:a) preparing an active matrix provided with a transistor and an insulating layer formed around the transistor; b) forming a capacitor structure on top of the insulating layer, wherein the capacitor structure includes a capacitor thin film made of PNZT; and c) forming a first metal layer and patterning the first metal layer into a predetermined configuration to electrically connect the transistor to the capacitor structure, wherein the step b) includes: preparing precursors P1, P2, P3 and P4; dehydrating the P1 and dissolving the vacuum dehydrated P1 in 2-methoxyethanol; mixing the dissolved P1 in vacuum, thereby obtaining a Pbâ€”Nb solution; mixing the P3 and the P4 under inert gas atmosphere, thereby obtaining a Zrâ€”Pb solution; refluxing the Pbâ€”Nb solution and the Zrâ€”Pb solution; adding NH4OH for base-catalyzed condition; adding ethylene glycol as a kind of dry control chemical additive, thereby obtaining a sol-gel coating solution; and spin coating the sol-gel coating solution on top of the first metal layer, thereby forming the capacitor thin film.