Patent ID: 6119194
Filing Date: 2000-09-12
Classification: G06F,Y02D

Abstract:
An apparatus comprising:a transaction type status register for a Universal Serial Bus (USB) host controller indicating a type of transaction on a USB, the status register including status bits corresponding to,a first status bit signal indicative of bulk activity on the USB,a second status bit signal indicative of control activity on the USB,a third status bit signal indicative of isochronous activity on the USB, anda fourth status bit signal indicative of an acknowledged interrupt on the USB,the first, second, third and fourth status bit signals being coupled to the transaction type status register;mask logic including a programmable mask register, said mask register including a mask bit for each of the status bits and wherein the mask logic further includes logic circuits logically combining respective mask bits and status bit signals to provide programmably masked status bits; anda power management circuit coupled to the programmably masked status bits, the power management logic responsive to the programmably masked status bits to generate a wake-up signal, indicating to a computer system to come out of a reduced power state.