Patent ID: 6137733
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A semiconductor memory device with a boosting circuit, comprising:a first power supply line;a second power supply line supplying a power supply potential;first and second boosting capacitors connected to said first power supply line; anda control circuit connecting said second power supply line to said first power supply line for a first time interval such that said first power supply line and said first and second boosting capacitors receive the power supply potential;said control circuit connecting said first boosting capacitor to the power supply potential, creating a series connection between said first and second boosting capacitors, thereby said first boosting capacitor boosts said first power supply line and said second boosting capacitor for a second time interval after said first time interval, andsaid control circuit connecting said second boosting capacitor to the power supply potential, creating a series connection between said first and second boosting capacitors, thereby said second boosting capacitor boosts said first power supply line for a third time interval after said second time interval.