Patent ID: 7595218
Filing Date: 2009-09-29
Classification: H01L

Abstract:
1. A method of forming an integrated circuit with nonvolatile memory cells, comprising: forming conductive rows accessing the nonvolatile memory cells by row; forming one or more dielectric layers above said conductive rows; forming interlayer contacts having a uniform cross-section through the one or more dielectric layers to conductively connect programmable resistive elements with the conductive rows, including: forming the programmable resistive elements of the nonvolatile memory cells, the programmable resistive elements having a cross-section smaller than the cross-section of the interlayer contacts, the programmable resistive elements having a first end adjacent to the interlayer contacts and a second end; and forming conductive columns accessing the nonvolatile memory cells by column, the conductive columns adjacent to the second ends of the programmable resistive elements.