Patent ID: 8566491
Filing Date: 2013-10-22
Classification: G06F,G11C

Abstract:
1. A data transfer subsystem for facilitating data transfer to a memory, wherein the memory is accessible via a non-deterministic bus, wherein the data transfer subsystem comprises control logic configured to: receive a first request that first data be transferred between a first logic subsystem and the memory; receive a second request that second data be transferred between the first logic subsystem and the memory; initiate a first data transfer in response to the first request; initiate a second data transfer in response to the second request, wherein the second data transfer is initiated before the first data transfer is completed; wherein the non-deterministic bus utilizes quality of service (QOS) timers for data transfer requests, wherein the non-deterministic bus is configured to service data transfer requests based on the QOS timers; wherein said initiating the second data transfer before the first data transfer is completed initiates a QOS timer for the second data transfer, wherein said initiating the second data transfer before the first data transfer is completed causes the second data transfer to be performed in immediate succession to the first data transfer; wherein the data transfer subsystem is comprised in a Global Navigational Satellite System (GNSS), wherein the first and second data are GNSS data; and wherein the first data and the second data are associated, wherein said initiating the second data transfer before the first data transfer is completed is based on the association between the first data and the second data.