Patent ID: 6552946
Filing Date: 2003-04-22
Classification: G11C

Abstract:
An address generating circuit, comprising:a first switch transistor having one end connected to a power supply source and the other end connected to a first node; a second switch transistor having one end connected to said first node and the other end connected to a second node; a fuse element having one end connected to said second node and the other end connected to a ground; a power-ON reset circuit for outputting a first reset signal for controlling ON/OFF conditions of said first switch transistor, and a second reset signal for controlling ON/OFF conditions of said second switch transistor, and; a latch circuit having an input terminal connected to said first node, wherein said latch circuit latches and outputs a predetermined potential corresponding to a cut-off or a no cut-off condition of said fuse element, wherein said first reset signal turns ON said first switch transistor during a first period immediately after the power supply is turned ON, and holds said first switch transistor in the OFF condition after said first period is completed, and wherein said second reset signal turns ON said second switch transistor at least during a second period after said first period, and holds said second switch transistor in the OFF condition after said second period is completed.