Patent ID: 6717867
Filing Date: 2004-04-06
Classification: G11C

Abstract:
A computer system, comprising:a processor having a processor bus; at least one input device coupled to the processor through the processor bus; at least one output device coupled to the processor through the processor bus; at least one data storage devices coupled to the processor through the processor bus; a system memory coupled to the processor through the processor bus; and a static random access cache memory coupled to the processor through the processor bus, the static random access cache memory comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; the memory-cell array comprising: an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal; a wordline coupled to the control terminal of each of the access switches in a respective row; a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column; a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines; a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines; and a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines; a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode; and a control circuit operable to control the operation of the SRAM.