Patent ID: 6822888
Filing Date: 2004-11-23
Classification: G11C,H01L

Abstract:
A one-time programmable read only memory cell useful in a memory array comprising:a MOS field effect transistor having a gate, a gate oxide underlying the gate, and first and second doped semiconductor regions underlying both the gate dielectric and the gate in a spaced apart relationship to define a channel region therebetween; a MOS data storage element having a conductive structure, an ultra-thin oxide underlying the conductive structure, and a first doped semiconductor region underlying both the ultra-thin oxide and the conductive structure, the first doped semiconductor region of the MOS data storage element being coupled to the first doped semiconductor region of the MOS field effect transistor, said ultra-thin oxide and said gate oxide formed using the same manufacturing process at the same time; a select line segment coupled to the gate of the MOS field effect transistor; a first access line segment coupled to the second doped semiconductor region of the MOS field effect transistor; and a second access line segment coupled to the conductive structure of the MOS data storage element.