Patent ID: 6867092
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, including a memory array having word lines extending in a first direction, bit lines extending in a second direction and memory cells located at intersections of said word lines and bit lines, said method comprising the steps of: (a) forming on the main surface of a semiconductor substrate a selecting MISFET to select a memory cell in said memory array, which selecting MISFET is provided with a gate electrode coupled to a word line extending in the first direction and then forming a first insulating film over the selecting MISFET; (b) etching the first insulating film to form a second contact hole extending to one of a pair of source and drain of the selecting MISFET and then forming a plug in the second contact hole; (c) forming over the first insulating film a third insulating film which is different in an etching rate from the first insulating film and then forming over the third insulating film a fourth insulating film which is different in an etching rate from the third insulating film; (d) etching the fourth insulating film by using the third insulating film as an etching stopper to form a wiring trench extending in the second direction intersecting the first direction; (e) forming a second insulating film having a thickness smaller than half the width of the wiring trench over the fourth insulating film including the inside of the wiring trench; (f) sequentially etching the second insulating film inside the wiring trench, a part of the fourth insulating film, the third insulating film below it, and the first insulating film and removing a part of the first insulating film on a device isolation region to form a first contact hole extending to the other of the pair of source and drain of the selecting MISFET; and (g) depositing a first conductive film to be the material of the bit lines over the second insulating film including the inside of the first contact hole, and then polishing the first conductive film and the second insulating film over the fourth insulating film to form a bit line in each of the wiring trench and the first contact hole.