Patent ID: 6418525
Filing Date: 2002-07-09
Classification: G06F,Y02D

Abstract:
A method of increasing the access speed of a set-associative memory using data addresses, each of said addresses comprising an offset portion, a congruence class index, and a tag portion, said set associative memory comprising an array and a directory, said array storing data, said array partitioned into a plurality of array congruence classes, said array congruence classes partitioned into array sets, said array sets each comprising a cache line having data, said directory partitioned into plurality of direction congruence classes, said directory congruence classes partitioned into directory sets, said directory sets each comprising a directory entry, said directory entry comprising an address tag, said directory partitioned such that there is a one-to-one correspondence between said directory entries and said cache lines such that said address tags are associated with at least one of said cache lines, said method comprising the steps of:accessing contents of sets of a single array congruence class using said congruence class index, said single array congruence class being specified by said congruence class index; accessing contents of sets of a single directory congruence class using said congruence class index, said single directory congruence class being specified by said congruence class index; generating set selection information; utilizing said set selection information to select said sets of said array congruence class prior to output of said single congruence class specified by the directory; outputting said data from said cache line in said selected set based on said set selection information.