Patent ID: 8138099
Filing Date: 2012-03-20
Classification: B81C,H01L

Abstract:
1. A method for making integrated circuit (IC) chip packages, the method comprising: providing a substrate; etching a via in the substrate; forming a release layer on a portion of a surface of the substrate laterally distanced from the via; depositing a barrier layer metallization (BLM) over a surface of the substrate and the release layer, wherein depositing the BLM includes depositing a first layer over the release layer and the substrate, and depositing a second layer over the first layer; patterning the BLM, such that the BLM is disposed in a first part above the release layer and in a second part on a portion of the substrate including the via, wherein a surface of the substrate is exposed between the first portion and the second portion of the BLM; depositing a solder structure over the first portion of the BLM, the second portion of the BLM, and the exposed substrate surface between the first and second portions of the BLM; etching the release layer; reflowing the solder structure; and annealing the solder structure, joining the substrate to a package.