Patent ID: 6741258
Filing Date: 2004-05-25
Classification: G06F

Abstract:
A system comprising:a main memory device operable to store a plurality of information for translating a virtual address into a physical address in response to one of a plurality of processing devices; and a memory control/interface device coupled to the main memory device, the memory control/interface device operable to access the plurality of information stored in the main memory device, the memory control/interface device having a plurality of interface units, each of the plurality of interface units being associated with a respective one of the plurality of processing devices, each of the plurality of interface units further comprising a separate translation look-aside buffer for each processing device, each translation look-aside buffer operable to buffer at least one of the plurality of information for use in translating in response to the respective processing device, wherein each translation look-aside buffer is capable of receiving at least one of the plurality of information from the main memory device.