Patent ID: 8307416
Filing Date: 2012-11-06
Classification: G06F,H04L

Abstract:
1. A system-on-chip (SOC) comprising: a processing core configured to operate as a master initiator; a plurality of slave initiator components coupled to the processing core, each slave initiator having an initiator firewall comprising programmable region permission check logic; a first target memory component coupled to the slave initiator components and the processing core and having a first target firewall comprising programmable region permission check logic; a second target memory component coupled to the slave initiator components and the processing core and having a second target firewall comprising programmable region permission check logic; and a memory coupled to the processing core and configured to store a first data structure and a second data structure, the first data structure indicating for at least one portion of the first target memory component, distinct access conditions for each slave initiator component and the master initiator and access conditions applicable to all slave initiator components and the second data structure indicating for at least one portion of the second target memory component, distinct access conditions for each slave initiator component and the master initiator and access conditions applicable to all slave initiator components and the master initiator, wherein the processing core programs the region permission check logic of the first target firewall and each slave initiator firewall according to the distinct access conditions and the access conditions applicable to all slave initiator components indicated in the first data structure and the region permission check logic of the second target firewall and each slave initiator firewall according to the distinct access conditions and the access conditions applicable to all slave initiator components indicated in the second data structure.