Patent ID: 6972585
Filing Date: 2005-12-06
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device having a DRAM, the DRAM comprising a memory array and a control portion supplied with external clocks from the outside of the DRAM, the control portion comprising a command decode portion responsive to an external command from the outside of the DRAM for decoding the external command, and a self-refresh control circuit for repeatedly carrying out a self-refresh operation upon the memory array in a self-refresh period when the self-refresh control circuit is activated, wherein: the DRAM further comprises an internal refresh period measuring circuit for measuring the self-refresh period; the command decode portion delivering a test mode signal representative of a test mode to the internal refresh period measuring circuit, supplying the external clocks as reference clocks to the internal refresh period measuring circuit, and then activating the self-refresh control circuit when a test mode command for measuring the self-refresh period is received as the external command; the self-refresh control circuit carrying out the self-refresh operation upon the memory array and delivering an internal oscillation signal having the self-refresh period to the internal refresh period measuring circuit when the self-refresh control circuit is activated; the internal refresh period measuring circuit comprising a counter for counting the number of the reference clocks supplied during the self-refresh period of the internal oscillation signal supplied thereto, and an output circuit for delivering a count result of a count-up operation by the counter to the outside of the internal refresh period measuring circuit in response to the test mode signal.