Patent ID: 6064105
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A shallow trench isolation structure formed between first and second active regions of an EEPROM cell in a semiconductor substrate to electrically isolate the first and second active regions from each other for maintaining sufficient data retention, said shallow trench isolation structure comprising:an epitaxial layer formed on a top surface of said semiconductor substrate;a barrier oxide layer formed on a top surface of said epitaxial layer;a nitride layer being deposited on a top surface of said barrier oxide layer;trenches being formed through said epitaxial layer and said barrier oxide layer to a depth greater than 4000 .ANG. below the top surface of said epitaxial layer so as to create an isolation region in order to electrically isolate active regions in said epitaxial layer;a liner oxide layer formed on sidewalls and bottom of said trenches to a thickness between 750 .ANG. to 1500 .ANG.;a TEOS oxide layer being deposited to fill completely said trenches and up to a thickness of approximately 7200 .ANG.;said TEOS oxide layer being removed and planarized down to the top surface of said nitride layer;said nitride layer being removed by etching; andan EEPROM cell having a programming junction implant being formed in one of said first and second active regions in said epitaxial layer,whereby leakage current in the sidewalls of said trenches is prevented due to less thinning of said liner oxide layer when said EEPROM cell is being formed.