Patent ID: 6495470
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method of forming a via opening to expose a portion of a metal interconnect, said method comprising:a) depositing a first interlayer dielectric (ILD) layer over said portion of said metal interconnect, said first ILD layer comprising BPSG; b) depositing an oxide layer over said first ILD layer, said oxide layer comprising a material selected from the group consisting of undoped oxide, lightly doped BSG, lightly doped PSG, and any combination thereof; c) depositing a second ILD layer over said oxide layer, said second ILD layer comprising BPSG; and d) dry etching said via opening through said second ILD layer, said oxide layer, and said first ILD layer to said portion of said metal interconnect using a single etch chemistry which causes a narrowing of said via opening through said oxide layer such that a width of said via opening in said first ILD layer is narrower than a width of said via opening in said second ILD layer.