Patent ID: 6297999
Filing Date: 2001-10-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word lines including first word lines;pairs of bit lines intersecting the plurality of word lines;a plurality of memory cells located at the intersections between the plurality of word lines and the pairs of bit lines;a plurality of sense amplifiers, each connected to one of the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines; anda burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on a burn-in control signal, wherein the burn-in test control circuit includes a potential difference setting circuit for selecting at least one of the first word lines before selection of the plurality of word lines to generate a potential difference between at least one of the pairs of bit lines based on the burn-in control signal, and wherein each of the sense amplifiers amplifies the potential difference to provide the stress voltage between the plurality of word lines and the associated pair of bit lines and between the associated pair of bit lines.