Patent ID: 6052806
Filing Date: 2000-04-18
Classification: G06F

Abstract:
An integrated circuit device, comprising:operational circuitry to carry out operations of the integrated circuit device, the integrated circuit device having an array of memory cells;at least one peripheral circuit connected to said operational circuitry for carrying out at least one function in respect of said operational circuitry;input means for permitting the input of command data in a normal mode of operation via a plurality of inputs and for permitting the input of test data in a test mode of operation via said plurality of inputs;control circuitry having an input to receive command data from said input means and arranged to generate, in response to said command data, control signals to control said at least one peripheral circuit in the normal mode of operation;a control bus comprising a plurality of lines, said plurality of lines being equal in number to said plurality of inputs, coupled between said control circuitry and the at least one peripheral circuit and arranged to carry said control signals from the control circuitry to the at least one peripheral circuit during the normal mode of operation; andtest circuitry having an input arranged to receive test data from said input means and having an output coupled to said control bus so that in the test mode of operation said test data is supplied to said at least one peripheral circuit from said test circuitry via said control bus and returned from the at least one peripheral circuit without affecting the array.