Patent ID: 6072332
Filing Date: 2000-06-06
Classification: H03K

Abstract:
A programmable logic integrated circuit device comprising:a plurality of regions of memory circuitry, each of which includes a plurality of memory locations addressable by address signals and configured to respectively store a plurality of data signals applied to that region via a plurality of data input conductors, each region being additionally configured to output data signals from its memory locations that are addressed by the address signals applied to that region;a plurality of programmable decoders, each decoder being associated with a respective one of the regions, and each decoder being configured to receive the signals on a multiplicity of the data input conductors of the associated region and being programmable to produce a predetermined decoder output signal in response to a particular logical combination of the signals received from the multiplicity of the data input conductors of the associated region;an inter-region conductor; anda plurality of output connectors, each output connector being associated with a respective one of the regions, and each output connector being configured to apply a data signal output by the associated region to the inter-region conductor in response to the predetermined decoder output signal from the decoder associated with that region.