Patent ID: 6314032
Filing Date: 2001-11-06
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first memory cell array having memory cells arranged in column and rows;a second memory cell array having memory cells arranged in column and rows;a plurality of first redundancy units for replacement of first defective memory cells in the first memory cell array;a plurality of second redundancy units for replacement of second defective memory cells in the second memory cell array;a plurality of storage circuits each for storing an address assigned to a defective memory cell, and also storing mapping information indicative of the relationship with the redundancy units, the storage circuits each outputting, when an address assigned to the defective memory cell stored therein matches an input address, a replacement control signal for the defective memory cell on the basis of the mapping information; andwherein the first memory cell array is included in a first bank, the second memory cell array is included in a second bank, and each of the storage circuits is utilized for replacement of any one of a defective memory cell included in the first memory cell array and a defective memory cell included in the second memory cell array.