Patent ID: 7970998
Filing Date: 2011-06-28
Classification: G06F

Abstract:
1. A data processing system, comprising: a processor a first cache memory, a second cache memory that is operated in parallel with said first cache memory and physically separated from said first cache memory by an address range, a comparator operable, when a cache miss occurs in both said first cache memory and said second cache memory, to make one of a true judgment and a false judgment relating to an access address of memory data for which memory access resulted in the cache misses, and a controller operable to store the memory data in said second cache memory when the true judgment is made, and store the memory data in said first cache memory when the false judgment is made, wherein said processor accesses a data entry in said first cache memory when there is a cache hit in said first cache memory, and accesses a data entry in said second cache memory without any data transfer between said first cache memory and said second cache memory when there is a cache hit in said second cache memory, wherein there is no case in which the memory data of the access address judged to be true and stored in said second cache memory is stored in said first cache memory for physically separating said second cache memory from said first cache memory by the address range.