Patent ID: 6759937
Filing Date: 2004-07-06
Classification: H01F,H01L,Y10T

Abstract:
An on-chip differential multiple layer inductor comprises:first partial winding on a first layer, wherein the first partial winding is operably coupled to receive a first leg of a differential input; second partial winding on the first layer, wherein the second partial winding is operably coupled to receive a second leg of the differential input; third partial winding on a second layer, wherein the third partial winding is operably coupled to a center tap; fourth partial winding on the second layer, wherein the fourth partial winding is operably coupled to the center tap; and interconnecting structure operably coupled to the first, second, third, and fourth partial windings such that the first and third partial windings form a winding that is symmetrical to a winding formed by the second and fourth partial windings.