Patent ID: 8685813
Filing Date: 2014-04-01
Classification: H01L

Abstract:
1. A method comprising: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; removing the second cap layer; and performing an oxidation process to form a gate oxide of a metal-oxide-semiconductor (MOS) device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes substantially all of the first cap layer.