Patent ID: 6195296
Filing Date: 2001-02-27
Classification: G11C

Abstract:
The device, as defined in claim 1, wherein the control circuit comprises:first and second inverters to respectively invert the chip selection control signal and the read/write control signal;first and second CMOS transmission gates to respectively transmit the output signals of the first and second inverters in response to a first transition of the clock signal;first and second latches to respectively latch the output signals of the first and second CMOS transmission gates;a third inverter to invert the output signal of the second CMOS transmission gate;a first AND gate to AND the output signals of the first CMOS transmission gate and the third inverter;a third CMOS transmission gate to transmit the output signal of the first AND gate in response to a second transmission of the clock signal;a third latch to latch the output signal of the third CMOS transmission gate;delay means to delay the output signal of the third CMOS transmission gate by one cycle in response to the clock signal;fourth and fifth inverters to respectively invert the output signals of the third CMOS transmission gate and the delay means;a second AND gate to AND the output signals of the third CMOS transmission gate and the fourth inverter to generate a first state change signal; anda third AND gate to AND the output signals of the delay means and the fifth inverter to generate a second state change signal.