Patent ID: 7250680
Filing Date: 2007-07-31
Classification: H01L

Abstract:
1. A semiconductor circuitry construction, comprising: a first monocrystalline semiconductor substrate; the first monocrystalline semiconductor substrate being n-type background doped; a second monocrystalline semiconductor substrate bonded over the first monocrystalline silicon substrate; the second monocrystalline semiconductor substrate being p-type background doped; an insulative material mass between the first and second monocrystalline semiconductor substrates; an electrically conductive interconnect extending through the second monocrystalline semiconductor substrate and to the first monocrystalline semiconductor substrate, the electrically conductive interconnect extending through the insulative mass between the first and second monocrystalline semiconductor substrates; wherein the electrically conductive interconnect is defined to comprise an upper portion extending within the second monocrystalline substrate and to comprise a lower portion extending between the upper portion and the first monocrystalline substrate; the electrically conductive interconnect comprising a semiconductive material; the upper portion being conductively doped to n-type; and the lower portion being conductively doped to p-type; and wherein the electrically conductive interconnect comprises a metal silicide layer between the upper and lower portions, the metal silicide layer being directly against both the upper portion and the lower portion.