Patent ID: 7251704
Filing Date: 2007-07-31
Classification: H04L

Abstract:
1. A method comprising: receiving a data packet at an ingress port of a switch coupling a plurality of components within a processing platform in a single computer including a processor, a root device, and one or more peripheral devices, the data packet being received at the ingress port from a first component, the first component being one of the processor, the root device, and the one or more peripheral devices; the switch initiating a checksum operation on a portion of the received data packet to validate the data packet, while the data packet is being received and before the data packet is received completely; substantially concurrently with respect to receiving the data packet and the checksum operation, commencing forwarding the received portion of the data packet through a switch fabric of the switch to a transmit queue of an egress port of the switch prior to completion of the checksum operation performed at the ingress port, the egress port coupled to a second component of the processing platform, the second component being one of the processor, the root device, and the one or more peripheral devices and different than the first component, wherein the second component receives a packet invalid symbol inserted at the tail end of the data packet to initiate a first link level retry from the switch for retransmission of the data packet, and wherein the switch initiates a second link level retry on the ingress port for retransmission of the data packet in response to the first link level retry; the switch sending a configuration header to the processor; and in response to the configuration header, the processor allocating communication resources at the processing platform to communicate with a virtual bridge corresponding to a port of the switch.