Patent ID: 6696742
Filing Date: 2004-02-24
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate, positioned along a plane, having a first conductivity type; a plurality of parallel trenches in the substrate extending in a first direction, parallel to the plane of the substrate, each trench being filled with an isolation material and having an adjacent trench separated therefrom by a strip region; a plurality of gate structures, for storing charge in a nonvolatile manner, arranged above the surface of the substrate and electrically isolated therefrom, the gate structures being arranged in parallel strips extending in a second direction parallel to the plane of the substrate, the parallel strips crossing the strip regions; a plurality of word lines, each of which is arranged on a corresponding gate structure from the plurality of gate structures; and a plurality of active regions of a second conductivity type, each of which is arranged at one end of a corresponding strip region and each of which is configured to allow free electrons of the active region to move from the active region to the gate structures of the corresponding strip region when a voltage is applied to the gate structures of the corresponding strip region, wherein the corresponding strip region between at least two gate structures is devoid of any active regions of the second conductivity type.