Patent ID: 6218261
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method of fabricating a bottom electrode, comprising the steps of:forming a semiconductor device in a substrate;forming a dielectric layer on the substrate, wherein the dielectric layer comprises a first opening exposing a portion of the semiconductor device;forming a conductive layer on the dielectric layer to fill the first opening, so as to couple the conductive layer with the semiconductor device;forming a first patterned mask layer comprising a second opening on the conductive layer, wherein the second opening exposes a portion of the conductive layer;performing an isotropic etching step on the conductive layer with the first patterned mask layer serving as a mask, wherein a recess with a non-vertical sidewall is formed in the conductive layer under the second opening, and the planar area of the recess is larger than the planar area of the second opening;removing the first patterned mask layer;patterning the conductive layer to form a bottom electrode having sidewalls and an upper surface with the recess; andforming a hemispherical grained silicon layer on the sidewalls and the upper surface of the bottom electrode.