Patent ID: 6366133
Filing Date: 2002-04-02
Classification: G11C

Abstract:
A CMOS logic circuit having plural inputs and a circuit output, the logic circuit having a first stage and a second stage, the first stage receiving the plural inputs and providing two first stage outputs, the second stage having an output connected to said circuit output and two current paths connected between said output and a reference voltage-receiving node, each of said current paths being substantially identical, and having a first transistor connected to said second stage output and a second transistor connected to said voltage-receiving node, said first and second transistors being connected in series;wherein each of said first stage outputs is coupled to the control gates of a first transistor in a respective one of said current paths and a second transistor in a respective other current path; wherein the first and second transistors of the second stage are N conductivity transistors, and said second stage further comprises at least one P conductivity transistor; and wherein the width of the N conductivity transistors of said second stage is substantially greater than that of the at least one P conductivity transistor of said second stage.