Patent ID: 6498524
Filing Date: 2002-12-24
Classification: G06F,G11C,H03K,H03L

Abstract:
A semiconductor device operating synchronously with an external clock, comprising:a data output circuit for outputting an output data according to an output timing signal so that the data output circuit outputs the output data synchronously with only one of a rising edge and a falling edge of the external clock; a data input circuit for fetching an input data according to an input timing signal so that the data input circuit fetches the input data synchronously with only the other of the rising edge and the falling edge of the external clock; and a timing signal generation circuit including: a delay circuit for delaying the external clock and outputting the output timing signal; and a timing comparison circuit having input nodes, which is coupled to receive the output timing signal and the external clock, for comparing phases at the input nodes, wherein a delay time of the delay circuit, which is changed by a comparison result at the timing comparison circuit, is controlled so that an output timing of the output data from the data output circuit is synchronized with only the one of the rising edge and the falling edge of the external clock.