Patent ID: 6611475
Filing Date: 2003-08-26
Classification: G06F,G11C,H03K,H03L

Abstract:
A memory device, comprising:an array of memory cells arranged in rows and columns; a row address decoder coupled to receive a row address signal and to enable a corresponding row of memory cells in the array; a column address decoder coupled to receive a column address signal and to enable a corresponding column of memory cells in the array; a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands; a data path coupled between the array of memory cells and a data bus terminal, the data path including a latch operable to latch data into or out of the memory device responsive to a clock signal applied to a clock terminal of the latch; a synchronized mirror delay having an output terminal, a measurement delay line input terminal, and a variable delay line input terminal; an input buffer having an input terminal coupled to receive an external clock signal and an output terminal coupled to the variable delay line input terminal of the synchronized mirror delay; and a clock tree coupling the output terminal of the synchronized mirror delay to the clock terminal of the latch, the clock tree having a feedback node coupled to the measurement delay line input terminal to provide a delayed feedback signal corresponding to a signal coupled from the feedback node of the clock tree.