Patent ID: 7528638
Filing Date: 2009-05-05
Classification: G06F,H03L

Abstract:
1. A clock signal distribution circuit comprising: a clock generator operative to output a reference clock signal having a first frequency; a frequency divider operative to receive said reference clock signal and to output a second clock signal having a second frequency lower than said first frequency; a delay-locked loop coupled to said output of said frequency divider, said delay-locked loop operative to output a third clock signal having a third frequency lower than said first frequency for distribution over a trace; a phase-locked loop operative to receive said third clock signal after said third clock signal is distributed over said trace and to output at least one clock signal having a fourth frequency higher than said third frequency; a first delay circuit operative to provide to said delay-locked loop a time delayed version of said third clock signal that is time-delayed by a first delay amount after said third clock signal is distributed over said trace; and a second delay circuit operative to receive said second clock signal and to output a fifth clock signal time delayed relative to said second clock signal by a second delay amount substantially equal to said first delay amount, wherein said delay-locked loop is operative to receive said fifth clock signal.