Patent ID: 7106648
Filing Date: 2006-09-12
Classification: G11C

Abstract:
1. An address extractor for obtaining a row address signal in response to a command signal, address signals including the row address signal and a column address signal, and a clock signal, comprising: a first element for outputting either a rising edge or a falling edge of the clock signal with a delay for a predetermined time; a second element for outputting a selection signal with a logic value variable in accordance with that the command signal is a predetermined command value; a third element for outputting the selection signal or retaining a previous output value, in accordance with a logic value of the clock signal; a fourth element for outputting the address signal or retaining a previous value, in accordance with a logic value of an output signal of the first element; and a fifth element for outputting an output signal of the fourth element as the row address signal or retaining a previous value, in accordance with a logic value of an output signal of the third element.