Patent ID: 8828834
Filing Date: 2014-09-09
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: forming a plurality of layers of material above a semiconducting substrate, wherein at least some of said plurality of layers of material will comprise a gate structure for said transistor, wherein forming the plurality of layers comprises forming a gate insulation layer on the substrate, forming a high-k insulating material layer on the gate insulation layer, forming a layer of metal on the high-k insulating material layer, forming a layer of polysilicon on the layer of metal and forming a gate cap layer on the layer of polysilicon; after forming the gate cap layer, performing a fluorine ion implantation process to form an as-implanted fluorine implant region that is positioned entirely within said layer of high-k insulating material; performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into said substrate to form source/drain regions for said transistor; and after performing both of said fluorine ion implantation process and said at least one ion implantation process, performing an anneal process.