Patent ID: 6751120
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A nonvolatile memory apparatus comprising:a control circuit; a plurality of terminals including a clock terminal; a command terminal and other terminal; a data register; a command register; and a plurality of nonvolatile memory cells, wherein said clock terminal receives a clock signal, wherein said command terminal couples to said command register and receives commands which comprise a read command and a program command, wherein said data register is used for receiving data from outside and outputting data to outside, wherein said control circuit reads out operation steps from a program memory for controlling an operation of said received command by executing said operation steps, wherein in an operation in response to said read command, said control circuit controls, based on operation steps corresponding to said read command, reading data from ones of said nonvolatile memory cells, stores read data to said register, and outputting said read data stored in said data register via said other terminal except said command terminal in response to said clock signal, and wherein in an operation in response to said program command received from said command terminal, said control circuit controls, based on operation steps corresponding to said program command, receiving data via said other terminal except said command terminal in response to said clock signal, stores received data to said data register and writing said received data to ones of said nonvolatile memory cells.