Patent ID: 6466054
Filing Date: 2002-10-15
Classification: H03K

Abstract:
A level converter circuit comprising:a first power supply line configured to receive a first potential level; a second power supply line configured to receive a second potential level different from the first potential level; a third power supply line configured to receive a third potential level different from the first and the second potential level; a first input terminal configured to receive a first logic signal; a second input terminal configured to receive a second logic signal, which is an inverted signal of the first logic signal; a first MISFET of a first conductivity type having a first gate and a first conduction path wherein the first input terminal is connected to one end of the first conduction path and the first gate is connected to the second power supply line; a second MISFET of the first conductivity type having a second gate and a second conduction path wherein the second input terminal is connected to one end of the second conduction path and the second gate is connected to the second power supply line; a third MISFET of a second conductivity type having a third gate and a third conduction path wherein the first power supply line is connected to one end of the third conduction path; a fourth MISFET of the second conductivity type having a fourth gate and a fourth conduction path wherein the first power supply line is connected to one end of the fourth conduction path, the third gate is connected to the other end of the fourth conduction path, the fourth gate is connected to the other end of the third conduction path, the other end of the first conduction path is connected to the other end of the third conduction path, and the other end of the second conduction path is connected to the other end of the fourth conduction path; a first output terminal connected to the other end of the third conduction path; a second output terminal connected to the other end of the fourth conduction path; a fifth FET of the first conductivity type having a fifth gate and a fifth conduction path wherein one end of the fifth conduction path is connected to the first power supply line and the fifth gate is connected to the second output terminal; a sixth FET of the first conductivity type having a sixth gate and a sixth conduction path wherein one end of the sixth conduction path is connected to the other end of the fifth conduction path, the other end of the sixth conduction path is connected to the third power supply line, and the sixth gate is connected to the first output terminal; and a third output terminal connected to the one end of the sixth conduction path.