Patent ID: 6484222
Filing Date: 2002-11-19
Classification: G06F

Abstract:
A computer system, comprising:a CPU connected to a local bus; a peripheral bus capable of operating at a low clock frequency and a high clock frequency; a bus bridge coupled to said local bus and to said peripheral bus for orchestrating the transfer of data and address signals between said local bus and said peripheral bus, said bus bridge including a clock driver that drives a peripheral bus clock signal at either the low clock frequency or the high clock frequency; a plurality of expansion slots coupled to the peripheral bus into which peripheral devices can be installed; an expansion slot controller coupled to the plurality of expansion slots by separate control lines, with each of the plurality of expansion slots providing a signal indicating if a peripheral device has been installed in the slot and whether any installed device can operate at the high clock frequency; wherein said expansion slot controller determines the clock frequency for the peripheral bus based upon the number of expansion slots in which peripheral devices have been installed, and the capability of the installed peripheral devices to operate at the higher clock frequency, and said expansion slot controller transmits a signal to said clock driver indicating the frequency at which said clock driver should drive said peripheral bus clock signal.