Patent ID: 7829917
Filing Date: 2010-11-09
Classification: H01L

Abstract:
1. A layout for a self-aligned semiconductor device, comprising: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having crystal planes, where a portions of the second semiconductor layer are whole, which is not undercut, and where other portions of the second semiconductor layer are undercut; a first conductive material layer on the second semiconductor layer opposite the first semiconductor layer; and a second conductive material layer formed along the portions of the second semiconductor layer that are undercut, the second conductive material layer also being formed such that a gap, which is an absence of conductive material, exists between the two conductive material layers at the whole portions of the second semiconductor layer; and where the first conductive material layer and the second conductive material layer are electrically isolated from each other by virtue of the first conductive material layer being aligned to the second conductive material layer along edges of the portions of the second semiconductor layer that are undercut, and also the first conductive material layer and the second conductive material layer being electrically isolated by virtue of the absence of conductive material between the two conductive material layers along the whole portions of the second semiconductor layer.