Patent ID: 6330646
Filing Date: 2001-12-11
Classification: G06F

Abstract:
A computer system comprising:a memory;a memory controller coupled to the memory, wherein the memory controller includes an arbitration unit that receives a mode select signal, wherein the arbitration unit operates according to a first arbitration mode whenever the mode select signal is in a first state and operates according to a second arbitration mode whenever the mode select signal is in a second state;a first device coupled to the arbitration unit; anda second device coupled to the arbitration unit, wherein the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode, wherein the first device and the second device are assigned an equal priority classification for accessing the memory while the arbitration unit is operating according to the second arbitration mode, and wherein the arbitration unit withholds access of the memory from the second device for a predetermined time interval while the first device has control of the memory whenever operating according to the second arbitration mode.