Patent ID: 8247316
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A method for fabricating a transistor, comprising: forming an amorphous silicon layer on a substrate; forming a capping layer on the amorphous silicon layer; forming a metal catalyst layer on the capping layer; performing a first annealing process to crystallize first regions of amorphous silicon of the amorphous silicon layer into first annealed polycrystalline silicon using metal catalysts of the metal catalyst layer that diffused through the capping layer, some of the metal catalysts forming crystallization seeds at an interface of the amorphous silicon layer and the capping layer; removing the metal catalyst layer and the capping layer; removing the crystallization seeds at the interface; and performing a second annealing process to crystallize second regions of amorphous silicon of the amorphous silicon layer into second annealed polycrystalline silicon using the diffused metal catalysts to form a polycrystalline silicon layer comprising the first annealed polycrystalline silicon and the second annealed polycrystalline silicon, wherein the metal catalyst layer and the crystallization seeds are removed after the first annealing process but before the second annealing process.