Patent ID: 7826266
Filing Date: 2010-11-02
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor device comprising: a first memory mat including a plurality of first non-volatile memory cells, a plurality of first volatile memory cells, of which a storage capacity is smaller than a storage capacity of the plurality of first non-volatile memory cells, and a first local data line coupled to the plurality of first non-volatile memory and the plurality of first volatile memory cells; a second memory mat including a plurality of second non-volatile memory cells, a plurality of second volatile memory cells, of which a storage capacity is smaller than a storage capacity of the plurality of second non-volatile memory cells, and a second local data line coupled to the plurality of second non-volatile memory cells and the plurality of second volatile memory cells; and a global data line coupled to the first local data line via a first switch and to the second local data line via a second switch, wherein, while first information that is transferred from the global data line to the first local data line is written into at least one of the plurality of first non-volatile memory cells, second information is transferred from the global data line to the second local data line by turning off the first switch and turning on the second switch.