Patent ID: 6128767
Filing Date: 2000-10-03
Classification: G06F,H01L

Abstract:
A computer system for generating a data representation of an integrated circuit (IC) layout, the computer system comprising:a) a memory; andb) one or more processors coupled to the memory,wherein the memory contains a set of instructions which, when executed by the one or more processors, cause the one or more processors to perform the steps ofi) generating polygon data associated with a polygon that represents a set of IC devices to be represented by the IC layout, wherein the polygon is represented by one or more wires, each of the one or more wires is represented by one or more wire segments and each of the one or more wire segments is represented by two directed line segments,ii) generating wire data that both represents the one or more wires and contains at least one reference to the polygon data,iii) generating wire segment data that both represents the one or more wire segments and contains at least one reference to the wire data, andiv) generating directed line segment data that represents the two directed line segments for each wire segment and indicates a direction of each directed line segment.