Patent ID: 9154152
Filing Date: 2015-10-06
Classification: H03M

Abstract:
1. An analog-to-digital-converter (ADC), comprising: a first capacitive digital-to-analog-converter (CDAC), comprising n capacitors corresponding to n bits, the CDAC being configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k−1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k−1)th bits that are less significant than the kth bit, wherein k is an integer ranging from 1 to n; and a control circuit, configured to estimate a weight of the kth bit based on the first and second digital code, the control circuit further configured to perform calibration of the CDAC capacitors based on the estimated weight.