Patent ID: 6385238
Filing Date: 2002-05-07
Classification: H04L

Abstract:
An adaptive equalization and baseline wander correction circuit comprising:adaptive filter means for receiving an input signal and for filtering said input signal to generate a first signal in response to a control signal; first half-wave rectifier means for receiving said first signal and for generating a first rectified signal in response thereto; first peak detector means for receiving said first rectified signal and for generating a first peak signal in response thereto; signal level extractor means for receiving said first peak signal and for generating a first level signal in response thereto; low pass filter means for receiving said first level signal and for generating a filtered signal in response thereto; first summing amplifier means for receiving said filtered signal and a reference signal and for generating said control signal, in response thereto; said control signal being the sum of said filtered signal and said reference signal; second summing amplifier means for receiving said first signal and a feedback signal and for generating a second signal in response thereto; said second signal being the sum of said first signal and said feedback signal; second halfwave rectifier means for receiving said second signal and for generating a second rectified signal in response thereto; limiter means for receiving said first and second rectified signals and for generating a third signal in response to said reference signal; second peak detector means for receiving said third signal and for generating a second peak signal in response thereto; signal extractor means for receiving said first and second peak signals and for generating said feedback signal; said feedback signal being a DC offset signal of said first and second peak signals; and slicer means for receiving said second rectified signal and said filtered signal and for generating an output signal in response thereto.