Patent ID: 7910419
Filing Date: 2011-03-22
Classification: H01L

Abstract:
1. Method for making a transistor with self-aligned gate and ground plane, comprising: a) forming a stack, on one face of a substrate based on at least one semi-conductor, comprising at least one layer based on at least one organometallic material and a layer based on at least one dielectric material, b) exposing by electron beams at least one part of the organometallic layer, a portion of the organometallic layer of the exposed part different to the organometallic layer and intended to form a ground plane of the transistor being protected from the electron beams by a mask during this exposure step, a shape and dimensions of a section, in a plane substantially parallel to the face of the substrate, of the gate of the transistor being intended to be substantially equal to the shape and to the dimensions of a section of said portion of organometallic material in said plane, c) removing the exposed part of the organometallic layer, d) forming dielectric portions in empty spaces formed by the removal of said exposed part of the organometallic layer, between the face of the substrate and the dielectric layer, around said portion of the organometallic layer.