Patent ID: 6393591
Filing Date: 2002-05-21
Classification: G06F

Abstract:
A method for testing a programmable logic device operatively coupled to a circuit board, the programmable logic device having boundary scan circuitry, the method comprising:providing a first computer configured to communicate with the programmable logic device while operatively coupled to the circuit board, the first computer having access to design information for programming the programmable logic device; putting the first computer in communication with a network; sending the design information from the first computer over the network to a second computer in communication with the network, the second computer having access to a vector generator and a vector database; the second computer, in response to receipt of the design information from the first computer: accessing the vector database to obtain device vectors associated with the programmable logic device; providing the device vectors and the design information to the vector generator; and generating test vectors in response to the device vectors and the design information, the test vectors for testing the programmable logic device programmed according to the design information; and communicating the test vectors to the first computer for testing the programmable logic device.