Patent ID: 8125087
Filing Date: 2012-02-28
Classification: B82Y,H01L,H05K

Abstract:
1. An apparatus comprising: a structural layer having an upper interconnect layer overlying a side thereof and a lower interconnect layer overlying an opposing side thereof; a plurality of signal connectors formed in the upper interconnect layer and arranged to couple with a plurality of leads of a die, a number of the signal connectors comprising a spline, each signal connector of the spline located adjacent to at least one other signal connector of the spline; a first row of riser vias and a second row of riser vias formed in the structural layer, each riser via of the first and second rows located outward of the plurality of signal connectors, a riser via of the first row and an adjacent riser via of the second row comprising a riser group associated with the spline; a number of other vias formed in the structural layer, each of the other vias located in a region underlying the plurality of signal connectors; a number of signal traces formed in the upper interconnect layer, a first of the upper interconnect layer signal traces coupled with a first signal connector of the spline and a second of the upper interconnect layer signal traces coupled with a second signal connector of the spline, the first and second upper interconnect layer signal traces extending outwardly from the spline and between the riser group and a directly adjacent riser group; and a number of signal traces formed in the lower interconnect layer, a first of the lower interconnect layer signal traces coupled by a first of the other vias with a third signal connector of the spline and further coupled with a first riser via of the riser group, a second of the lower interconnect layer signal traces coupled by a second of the other vias with a fourth signal connector of the spline and further coupled with a second riser via of the riser group; wherein the first and second riser vias of the riser group route the first and second lower interconnect layer signal traces to the upper interconnect layer, and wherein a third and fourth of the upper interconnect layer signal traces are coupled with the first and second riser vias, respectively, and extend outwardly from the riser group and adjacent to the first and second upper interconnect layer signal traces.