Patent ID: 7839713
Filing Date: 2010-11-23
Classification: G11C

Abstract:
1. A memory circuit comprising: a write driver; a memory cell coupled to the write driver; a first write control switch coupled to the write driver and the memory cell, wherein the first write control switch comprises a first complementary metal oxide semiconductor (“CMOS”) pass gate; and a second write control switch coupled to the write driver and the memory cell, wherein the second write control switch comprises a second CMOS pass gate; wherein data is read from the memory cell and data is written to the memory cell in one clock cycle via a port without pre-charging the port between reading data from the memory cell and writing data to the memory cell via the port in the one clock cycle, and wherein the write driver comprises a first driver path including a first inverter, wherein the first inverter is a CMOS inverter that has a P-channel MOS (“PMOS”) transistor and an N-channel MOS (“NMOS”) transistor with a PMOS transistor size and an NMOS transistor size, respectively, wherein the PMOS transistor size is approximately 0.5 times the NMOS transistor size.