Patent ID: 6854040
Filing Date: 2005-02-08
Classification: G11C

Abstract:
1. A read control circuit for an electronic memory device integrated on a semiconductor substrate, the electronic memory device comprising an address counter, a non-volatile memory matrix with row and column decoders connected to respective outputs of the address counter, an address transition detect (ATD) circuit for detecting an input transition as the electronic memory device is being accessed, and read amplifiers and associated registers for transferring data read from the electronic memory device to an output thereof, the read control circuit comprising: a burst read detection circuit including a first input for receiving a clock signal and a second input for receiving a logic signal for enabling reading in a burst mode; and a burst read control logic circuit having an input connected to said burst read detection circuit and having outputs connected to the read amplifiers and the associated registers to activate a parallel reading of a plurality of memory words within a single period of the clock signal with respect to receiving the logic signal.