Patent ID: 7863987
Filing Date: 2011-01-04
Classification: G06F,H03L

Abstract:
1. A clock signal generating and distributing apparatus, comprising: a PLL for generating a voltage control signal; a first LC resonant voltage control oscillator, which is controlled by the voltage control signal, for generating a first oscillation signal at a first oscillation node, the first LC resonant voltage control oscillator having a first input terminal for coupling; a second LC resonant voltage control oscillator, which is controlled by the voltage control signal, for generating a second oscillation signal at a second oscillation node, the second LC resonant voltage control oscillator having a second input terminal for coupling; a first wire for connecting the second oscillation node and the first input terminal for coupling; a first buffer located on the first wire; a second wire for connecting the first oscillation node and the second input terminal for coupling; and a second buffer located on the second wire, wherein a ratio of a resistance of the first wire to an inductance of the first wire is determined such that the first LC resonant voltage control oscillator and the second LC resonant voltage control oscillator are oscillated in the same phase, wherein the first LC resonant voltage control oscillator on an output side of the first buffer is synchronized with the second LC resonant voltage control oscillator on an input side of the first buffer via injection locking, and wherein the second LC resonant voltage control oscillator on an output side of the second buffer is synchronized with the first LC resonant voltage control oscillator on an input side of the second buffer via injection locking.