Patent ID: 9204542
Filing Date: 2015-12-01
Classification: G06F,H01L,H05K

Abstract:
1. An apparatus, comprising: a package substrate having a top surface and a bottom surface, the bottom surface configured to receive a ball grid array, the package substrate for a first stacked silicon interconnect technology (SSIT) product that comprises one or more top dies mounted on an interposer, the first SSIT product having a first top die configuration, wherein the package substrate includes a plurality of exposed pads disposed on the top surface and uncovered by the interposer, the plurality of exposed pads disposed in an arrangement suitable to receive at least one additional die, the exposed pads not soldered to another structure; wherein the package substrate is compatible with a second SSIT product with a second top die configuration; and wherein the first top die configuration is different from the second top die configuration; wherein the first SSIT product is smaller in size than the second SSIT product; and the first SSIT product has bumps along a side of the first SSIT product that are a same type as that of bumps at corresponding locations on the second SSIT product, the corresponding locations being away from a side of the second SSIT product.