Patent ID: 6205075
Filing Date: 2001-03-20
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of main bit lines;a main bit line controller for controlling whether to impress a specific voltage on the main bit lines, connect the main bit lines to a sense amplifier, or place the main bit lines in the OPEN state, based on an address signal;a plurality of virtual main grounding lines; anda virtual main grounding line controller for controlling whether to impress a specific voltage on the virtual main grounding lines, impress a grounding voltage on the virtual main grounding lines, or place the virtual main grounding lines in the OPEN state, based on the address signal;wherein, said main bit line controller and said virtual main grounding line controller control the voltage impression states of the main bit lines and the virtual main grounding lines respectively, so that, when accessing a memory cell, the relative positional relationship of the voltage level states of said virtual main grounding lines and other main bit lines that are adjacent to and at specific intervals of space from said main bit line connecting the selected memory cell and said sense amplifier, will be the same for any memory cell selected.