Patent ID: 7367001
Filing Date: 2008-04-29
Classification: G06F

Abstract:
1. A method of verifying a digital design in a data processing system, said method comprising: generating a reference model for a first digital design; creating a operational model for a second digital design, wherein said first digital design and said second digital design are intended to have a same logical function; creating a plurality of testcase types by constraining one or more internal signals within said operational model, wherein said plurality of testcase types include a plurality of descriptions of simulated inputs to said reference model and said operational model and constraining one or more output signals from a simulated component within said second digital design; producing one or more test scripts representing said plurality of testcase types; verifying said second digital design with a testing simulation program by comparing results of said test scripts from said operational model and said reference model; and outputting a result of said comparing to a log in said data processing system.