Patent ID: 6154828
Filing Date: 2000-11-28
Classification: G06F

Abstract:
An apparatus comprising:a compiler for generating an executable file including compound instructions of varying length, at least one compound instruction including multiple operational instructions, each operational instruction including a corresponding cycle bit indicating which of a set of multiple operational instructions can be logically executed simultaneously;an instruction register including a predetermined number of operational instruction storage slots for storing a predetermined number of operational instructions and corresponding cycle bits;an instruction fetching unit that, during a fetch cycle, fetches the operational instructions of compound instructions in the executable file and transfers the fetched operational instructions and the corresponding cycle bits to the operational instruction storage slots of the instruction register, the instruction fetching unit overwriting previously executed operational instructions in the instruction register with newly fetched operational instructions and corresponding cycle bits, the instruction fetching unit fetching and storing part of a compound instruction to the instruction register when a compound instruction includes more operational instructions than available operational instruction storage slots in the instruction register, such that any operational instructions of a partially fetched compound instruction not fetched on a current fetch cycle are fetched and stored in the instruction register on one or more subsequent fetch cycles; andan instruction executing unit including multiple processors that, after a fetch cycle, simultaneously execute operational instructions in the instruction register in parallel depending on a state of the corresponding cycle bits, each processor executing an operational instruction in a corresponding operational instruction storage slot, such that any subsequently fetched operational instructions of a partially fetched and executed compound instruction being executed on one or more subsequent processing cycles such that the executable file is properly executed by instruction executing units having fewer processors than a number of operational instructions in a maximal length compound instruction.