Patent ID: 8350386
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. A semiconductor chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a contact pad over said silicon substrate, wherein said contact pad has a top surface with a first region, a second region and a third region between said first and second regions; a passivation layer over said metallization structure, over said dielectric layer and on said first and second regions, wherein a first opening in said passivation layer is over said third region, and said third region is at a bottom of said first opening, wherein said passivation layer comprises a nitride; a first polymer layer on a fourth region of a top surface of said passivation layer, wherein a second opening in said first polymer layer is over said third region and over a fifth region of said top surface of said passivation layer, wherein said first polymer layer has a thickness between 2 and 50 micrometers; a third metal layer on said first polymer layer, on said third and fifth regions and in said first and second openings, wherein said third metal layer is connected to said third region through said first and second openings, wherein said third metal layer comprises a titanium-containing layer on said first polymer layer, on said third and fifth regions and in said first and second openings, a gold seed layer on said titanium-containing layer, and an electroplated gold layer with a thickness between 2 and 100 micrometers on said gold seed layer; and a second polymer layer on said third metal layer and on said first polymer layer.