Patent ID: 7873066
Filing Date: 2011-01-18
Classification: G06F

Abstract:
1. A Network On a Chip (NOC), the NOC comprising: a first node comprising an Uncompressed Direct Inter-thread Communication Outbox Buffer (UDICOB) that comprises at least one empty buffer cell between at least two data words that are stored in the UDICOB, and wherein data words from the UDICOB populate a first Compressed Direct Inter-thread Communications Buffer Packet (CDICBP); and a second node that is coupled via an on-chip network to the first node, wherein the second node comprises: an input Compressed Direct Inter-thread Communication Buffer (CDICB) that stores received data from the first CDICBP such that no empty buffer cells are present between any two data words stored therein, and wherein the UDICOB and the input CDICB each contain multiple data word aggregates, each data word aggregate comprising at least two data words; a first set of shadow latches for successively reading rows of data words from the input CDICB; a first set of multiplexers, wherein the first set of multiplexers selectively reads from the first set of shadow latches individual data words from data word aggregates in a manner such that rows of data words aligned as in the UDICOB are provided for processing; a processor that processes each of the provided rows of data words to produce an output of uncompressed rows of data words; and a second set of multiplexers, wherein the second set of multiplexers compresses the output of uncompressed rows of data words from the processor and stores the compressed output in a second CDICB that has no empty buffer cells between any two data words stored therein.