Patent ID: 6510085
Filing Date: 2003-01-21
Classification: G11C

Abstract:
A method of programming a flash memory device having multiple flash memory cells formed in rows and columns with a flash memory cell located at each intersection of a column and a row and each flash memory cell having a control gate and a floating gate formed over a substrate and each flash memory cell having a source and a drain formed in the substrate, wherein the drains in each column have a common terminal and wherein the sources have a common terminal and wherein the substrates have a common terminal, the method comprising:selecting a cell to be programmed; applying a selected programming voltage between 7 and 10 volts to the control gate of the selected cell to be programmed; applying a selected programming voltage between 4 and 6.0 volts to the drain of the selected cell to be programmed via the common terminal to which the drain of the selected cell is connected; applying a selected programming voltage between 0.5 and 2.0 volts to the sources of all the flash memory cells; and applying a selected programming voltage between minus 2 and minus 0.5 volts to the substrates of all the flash memory cells.