Patent ID: 7920409
Filing Date: 2011-04-05
Classification: G11C

Abstract:
1. A Static Random Access Memory (SRAM) cell comprising: a pair of cross-coupled inverters having a first output node and operating to store a data bit at the first output node, the pair of cross-coupled inverters powered by a read control signal to operate in a voltage-collapsed state during standby and in a full-voltage state during read operations; a read transistor comprising a gate coupled to the first output node of the pair of cross-coupled inverters and operating to provide a signal indicative of the data bit on a first bit line during the read operations; and a write transistor comprising a source, a drain, and a gate and having one of the source and the drain connected to the first output node of the pair of cross-coupled inverters and an other of the source and the drain coupled to the first bit line, wherein the write transistor is controlled via the gate of the write transistor such that a desired data bit is written from the first bit line to the pair of cross-coupled inverters via the write transistor during write operations.