Patent ID: 6043543
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A read-only memory cell configuration, comprising:a substrate formed of semiconductor material and having a main area;a cell field having memory cells in the region of said main area;a bit line and a word line;each of said memory cells having at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode, said drain region connected to said bit line and said gate electrode connected to said word line;said at least one MOS transistor being formed by a trench starting at said main area and reaching as far as said source region, said trench defining side walls disposed at an angle of between approximately 45.degree. and approximately 80.degree. relative to said main area and doped with a doping material of a predetermined conductivity for defining a programming of said at least one MOS transistor;a gate insulation layer electrically insulating said gate electrode;an insulation layer adjacent said at least one MOS transistor; anda local interconnection associated with said drain region of said at least one MOS transistor, said local interconnection electrically connecting said drain region, and said local interconnection being disposed at least regionally over said gate insulation layer and said insulation layer.