Patent ID: 7915074
Filing Date: 2011-03-29
Classification: H01L,Y10S

Abstract:
1. A manufacturing method of a thin film transistor array panel, the method comprising: forming a first conductive layer on a substrate; forming a gate insulating layer on the first conductive layer; forming a first insulating layer on the gate insulating layer; forming a first insulating pattern including a first opening by patterning the first insulating layer; forming a gate insulating member and a gate line by etching the gate insulating layer and the first conductive layer using the first insulating pattern as a mask; forming an organic semiconductor in the first opening; sequentially forming a passivation layer and a second insulating layer on the organic semiconductor and the first insulating pattern; forming a second insulating pattern by patterning the second insulating layer; etching the passivation layer using the second insulating pattern as a mask; depositing a second conductive layer on the second insulating pattern, on portions of the substrate that are exposed through second openings in the etched passivation layer, and on portions of the first insulating pattern and the organic semiconductor that are exposed through third openings in the etched passivation layer; forming a pixel electrode by removing the second insulating pattern and first portions of the second conductive layer that are located on the second insulating pattern, leaving behind second portions of the second conductive layer that are on the substrate in the second openings in the etched passivation layer, wherein the second portions of the second conductive layer are used as the pixel electrode; and forming a data line including a source electrode, and a drain electrode facing the source electrode by depositing a third conductive layer and patterning the third conductive layer by photolithography and etching.