Patent ID: 6529480
Filing Date: 2003-03-04
Classification: H04L

Abstract:
An apparatus including a circuit for testing a device for communicating data packets on a data packet transmission medium, comprising:a first bit generator circuit configured to generate at least a first plurality of bits; a first digital interface, coupled to said first bit generator circuit, configured to convey said first plurality of bits to a data packet assembler, said data packet assembler being configured to assemble a data packet which includes said first plurality of bits and in accordance therewith to transmit said data packet on a data packet transmission medium; a second digital interface configured to convey said first plurality of bits from a data packet disassembler, said data packet disassembler being configured to receive said data packet from said data packet transmission medium and in accordance therewith to disassemble said first plurality of bits; a second bit generator circuit configured to generate at least a second plurality of bits; and a comparison circuit, coupled to said second digital interface and said second bit generator circuit, configured to receive and compare said first plurality of bits and said second plurality of bits and in accordance therewith to selectively generate an error signal.