Patent ID: 6368915
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a non-volatile memory element having a floating gate situated between an overlapping control gate and a channel region which is situated in the semiconductor body and extends between a source zone and a drain zone, by which method an active region of a first conductivity type adjoining the surface is defined in the semiconductor body, and a floating gate dielectric is provided, to which floating gate dielectric the floating gate is applied, the floating gate having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and having sidewall portions extending substantially perpendicularly to the surface of the semiconductor body, which floating gate is provided with an inter-gate dielectric, to which inter-gate dielectric the control gate is applied, which control gate is capacitively coupled with the substantially flat surface portion of the floating gate and with at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone, comprising, after defining the active region, applying a patterned layer, which patterned layer acts as a mask during the formation of the source zone and the drain zone of a second conductivity type in the semiconductor body, then providing a dielectric layer in a thickness which is sufficiently large to cover the patterned layer, removing the dielectric layer over part of its thickness by means of a material removing treatment until the patterned layer is exposed, removing the patterned layer, thereby forming a recess in the dielectric layer, applying a first insulating layer in the recess, thereby providing the floating gate dielectric of the memory element, applying a first conductive layer to the first insulating layer, thereby filling the recess in the dielectric layer, shaping first conductive layer into the floating gate by means of masked etching, covering the floating gate by a second insulating layer, thereby providing the inter-gate dielectric of the memory element, and applying a second conductive layer to the second insulating layer, and shaping the second conductive layer into the overlapping control gate.