Patent ID: 7863674
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A multiple-gate transistor comprising: a semiconductor fin formed in a portion of a bulk semiconductor substrate; an isolation layer over the bulk semiconductor substrate; a gate dielectric overlying a portion of the semiconductor fin; a gate electrode overlying the gate dielectric, the gate electrode having a bottom surface in contact with the isolation layer and having at least'one sidewall being substantially planar; a dielectric layer adjacent a portion of the gate electrode and completely covering a top surface of the isolation layer between the semiconductor fin and the gate electrode, the dielectric layer having a substantially planar top surface; and a source region and a drain region formed in the semiconductor fin oppositely adjacent to the gate electrode, the source region having a source-substrate junction, and the drain region having a drain-substrate junction; wherein the bottom surface of the gate electrode is lower than the source-substrate junction or the drain-substrate junction; wherein a top surface of the dielectric layer is substantially aligned with the source-substrate junction.