Patent ID: 8302040
Filing Date: 2012-10-30
Classification: G06F

Abstract:
1. A method for improving accuracy of FET transistor models used in simulating integrated circuit behavior, a FET transistor modeled as including a conductive line feature coupled to a transistor gate and terminating in one or more landing pad features proximate respective opposing edges of an active device area defined by said FET transistor, said method comprising: receiving, at a programmed computer system, for a FET transistor design, a corresponding netlist used in simulating an integrated circuit, and compact transistor models required by said netlist; implementing, a modeling function to model a lithographic rounding effect of said landing pad feature, and determining from said application changes in a width parameter “W” of said active device area as a function of a distance from an edge defined by a said landing pad feature to an opposing edge of said active device area of the transistor device being modeled; adding, to the original netlist for said FET transistor design, values for updating said active device area widths based on said determined changes in width “W” parameter used in a circuit simulation; and generating a new set of model parameters for said FET transistor using the compact transistor models received and changes in said width parameter W, wherein the programmed computer system performs one or more said receiving, determining, and adding.