Patent ID: 8570826
Filing Date: 2013-10-29
Classification: G11C

Abstract:
1. An apparatus comprising: a plurality of memory arrays comprising a first memory array and a second memory array adjacent to each other, the first memory array comprising a first memory cell and a second memory cell, and the second memory array comprising a third memory cell; a first contact configured for input and/or output of data; a second contact configured for input and/or output of data, the first memory array and the second memory array being interposed between the first contact and the second contact; a plurality of master data lines comprising a first master data line and a second master data line, the first master data line being electrically connectable to the first contact, and the second master data line being electrically connectable to the second contact; a first local data line configured to selectively carry data in a first path between the first memory cell and the first master data line, and to selectively carry data in a third path between the third memory cell and the first master data line; and a second local data line configured to selectively carry data in a second path between the second memory cell and the second master data line.