Patent ID: 6185138
Filing Date: 2001-02-06
Classification: G11C

Abstract:
A method of testing a random access memory device having a memory array of memory cells, a plurality of bit lines to which a plurality of columns of memory cells in said memory array are connected, the bit lines being grouped into pairs of bit lines, a plurality of word lines to which rows of memory cells in said memory array are connected, a control line, at least one data line, and a plurality of transistors connected to said data line, each transistor being connected to a distinct bit line and having a control electrode connected to said control line, said method comprising the steps of:selectively driving said data line to a voltage representative of a logic level;driving said control line to turn on said transistors and connect said bit lines to said data line so that each bit line pair includes a bit line connected to said data line;driving one of said word lines to a voltage level to store data representing the voltage placed on said bit lines during said step of driving said control line, in each memory cell in a row of memory cells associated with said driven word line; andretrieving data stored in the row of memory cells.