Patent ID: 7184337
Filing Date: 2007-02-27
Classification: G11C

Abstract:
1. A method for testing an integrated semiconductor memory, comprising: writing a first memory state to memory cells of a memory cell array of the integrated semiconductor memory; writing a second memory state to memory cells connected to a first word line; generating a disturbance signal for disturbing a memory state of memory cells connected to the first word line; low-impedance connecting the memory cells connected to the first word line to the bit line, a potential state forming on each bit line connected to one of the memory cells connected to the first word line; simultaneously connecting the bit lines connected to one of the memory cells connected to the first word line to the common data line so that the respective potential states of the bit lines connected to one of the memory cells connected to the first word line experience a disturbance brought about by a capacitive load of a common data line; refreshing the disturbed memory state of the memory cells connected to the first word line by assessing the respectively disturbed potential states of the bit lines; electrically disconnecting the bit lines connected to one of the memory cells connected to the first word line from the common data line, thereby avoiding a charge equalization between the bit lines connected to one of the memory cells connected to the first word line; and successively reading-out the respective memory state of the memory cells connected to the first word line.