Patent ID: 6061511
Filing Date: 2000-05-09
Classification: G01R,G06F

Abstract:
A method for providing visibility into state nets of a design under emulation, comprising:running said emulation for said design in an emulator and, during emulation, (a) providing at predetermined intervals snapshots of said emulation, each snapshot including output values of state elements of said design; and (b) providing at each transition of a clock signal within said design, a set of sample signals, each set of sample signals including primary input signals of said design and output values of memory circuits of said design;at a subsequent time, re-running said emulation by loading into an emulator the values of said state elements using a selected one of said snapshots and, at each clock transition subsequent to said snapshot, (a) applying said sample signals corresponding to said clock transition to said design, and (b) providing as output a state vector corresponding to said clock signal transition, said state vector including values of said state elements at said clock signal transition; andreceiving said state vectors and said sample signals into a reconstruction engine, and evaluating waveforms of said nets of said design using said state vectors and said sample signals.