Patent ID: 7655962
Filing Date: 2010-02-02
Classification: H01L

Abstract:
1. A circuit comprising: an enhancement mode heterostructure field-effect transistor (E-mode HFET) including: top and bottom barrier layers; a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer; a gate electrode; source and drain electrodes coupled with the channel layer; a first electrode, distinct from the gate electrode and the source and drain electrodes, capacitively coupled with the channel layer, and isolated from the source electrode, the gate electrode, and the drain electrode; and a second electrode, distinct from the first electrode, the gate electrode and the source and drain electrodes, capacitively coupled with the channel layer and coupled to the drain electrode and isolated from the first electrode; a first positive bias coupled to the first electrode; and a second positive bias coupled to the second electrode and the drain, wherein the first electrode and the first positive bias lower an access resistance of a gate-source access region, and wherein the second electrode and the second positive bias lower an access resistance of a gate-drain access region.