Patent ID: 6794242
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A process for forming an oxide layer (Top Oxide) over an array of vertical transistors in a silicon substrate and conducting lines used to connect the vertical transistors with self-aligned gate contacts of the vertical transistors comprising the steps of:depositing a Trench Top Oxide (TTO)with a pad nitride in place using a high density plasma (HDP) process; forming a gate oxide and gate amorphous silicon or polycrystalline silicon within recesses of the silicon substrate followed by removing the HDP oxide on the top of the pad nitride, with the gate amorphous silicon or polycrystalline silicon protecting structures inside the vertical device; planarizing the gate amorphous silicon or polycrysatlline silicon back to the pad nitride; then etching the pad nitride away selective to the gate amorphous silicon or polycrystalline silicon and oxide on the silicon substrate surface to form self-aligned gate amorphous silicon or polycrystalline silicon plugs projecting above the silicon substrate surface; and depositing a top oxide filling spaces in between the amorphous silicon or polycrystalline silicon plugs.