Patent ID: 6581171
Filing Date: 2003-06-17
Classification: G01R

Abstract:
A circuit configuration for burn-in testing of a semiconductor module, comprising:a plurality of memory elements each having an input for receiving and storing therein respective burn-in test signals; a plurality of terminals for receiving the burn-in test signals from a burn-in test device, the signals having active and inactive states, each of said terminals being connected to an input of said memory elements for storing the respective burn-in test signal present at said terminal; each of said memory elements having an output outputting an output signal having an active state as soon as an active signal is present at said input of said memory element; and a functional unit connected to each of said memory elements, said functional unit having an output signal with a first state if all said memory elements output an active state output signal, and with a second state if at least one of said memory elements outputs an inactive state output signal.