Patent ID: 8680606
Filing Date: 2014-03-25
Classification: H01L

Abstract:
1. A power semiconductor device comprising: a first semiconductor layer of a first conductivity type; a plurality of mutually separated second semiconductor layers of a second conductivity type, each extending within the first semiconductor layer from a surface of the first semiconductor layer; a plurality of third semiconductor layers of the second conductivity type, each provided on a top end of a corresponding one of the plurality of second semiconductor layers and having an impurity concentration of the second conductivity type higher than an impurity concentration of the second conductivity type of the second semiconductor layers; a plurality of fourth semiconductor layers of the first conductivity type, each selectively provided on a top surface of a corresponding third semiconductor layer; a plurality of fifth semiconductor layers of the second conductivity type, each provided between two adjacent third semiconductor layer and extending beyond a bottom of each third semiconductor layer, each of the fifth semiconductor layers electrically connecting the two adjacent third semiconductor layers and contacting two adjacent second semiconductor layers provided beneath the two adjacent third semiconductor layers respectively, and having an impurity concentration of the second conductivity type lower than the impurity concentration of the second conductivity type of the third semiconductor layers; a gate electrode provided via a gate insulating film on the first semiconductor layer, the plurality of fifth semiconductor layers, the plurality of third semiconductor layers and the plurality of fourth semiconductor layers, the gate electrode including a plurality of openings over the plurality of third semiconductor layers and the plurality of fourth semiconductor layers; an interlayer insulating film provided on the gate electrode; a first electrode that is in electrical connection with the first semiconductor layer; and a second electrode in electrical connection with the plurality of third semiconductor layers and the plurality of fourth semiconductor layers via the openings in the gate electrode.