Patent ID: 6076160
Filing Date: 2000-06-13
Classification: G06F

Abstract:
A computer system, comprising:a central processing unit (CPU) configured to execute instructions, comprising:a first bus communication circuit having:a first data transfer mode effectuating data transfers on a single transition of a bus clock signal; anda second data transfer mode effectuating data transfers on both transitions of the bus clock signal;a first storage unit, wherein the contents of the first storage unit determine whether the first bus communication circuit operates in the first or second data transfer mode; anda first configuration circuit coupled to the first storage unit; and chip set logic coupled to the CPU, comprising:a second bus communication circuit having the first and second data transfer modes:a second storage unit, wherein the contents of the second storage unit determine whether the second bus communication circuit operates in the first or second data transfer mode; anda second configuration circuit coupled to the second storage unit;wherein a single signal line connects the first configuration circuit to the second configuration circuit, and wherein the first and second bus communications circuits are initially configured to operate in the first data transfer mode, and wherein the first and second configuration circuits participate in a serial exchange of signals over the signal line, and wherein the first configuration circuit modifies the contents of the first storage unit dependent upon an outcome of the serial exchange of signals, and wherein the second configuration circuit modifies the contents of the second storage unit dependent upon the outcome of the serial exchange of signals.