Patent ID: 6128695
Filing Date: 2000-10-03
Classification: G06F,G11C

Abstract:
A storage device comprising:a nonvolatile memory adapted to be coupled to a host processor for storing information identified by a logical block address (LBA) assigned by the host processor, sad nonvolatile memory being organized in blocks of numbered rows of information storage sites, each said block being identified by a physical block address (PBA);a memory device operative to store a table including a plurality of storage sites, each addressable by a particular LBA, and each of which is associated with a particular PBA identifying a particular block within said nonvolatile memory in which information corresponding to a particular LBA is, or is to be, stored in one or more of the rows thereof; anda controller associated with said memory device for accessing a block in said nonvolatile memory identified by a particular PBA in response to receipt from the host of a corresponding LBA, said controller being operative to access at least a portion of a particular PBA to read data from, or to write data into the accessed block, said controller being programmed to write the identifying LBA into two different locations within said accessed block, and upon accessing of any block having data stored therein, said controller being operative to compare the LBAs written into the two different locations within the block, and if the LBAs match, to use the block for information storage, but if the LBAs do not match, then to erase the block prior to re-use.