Patent ID: 6229342
Filing Date: 2001-05-08
Classification: H01L,H03K

Abstract:
An inverter, comprising:a first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/base region, and having a collector/drain region, and wherein the first transistor has a gate on a first one of the opposing sidewall surfaces, the first transistor has a body contact on a second one of the opposing sidewall surfaces, the body contact coupled to the gate;a second transistor extending outwardly from a semiconductor substrate, the second transistor having an upper surface and opposing sidewall surfaces, the second transistor having a source/emitter region, a body/base region, and having a collector/drain region;a third transistor extending outwardly from a semiconductor substrate, the third transistor having an upper surface and opposing sidewall surfaces, the third transistor having a source/emitter region, a body/base region, and having a collector/drain region;a fourth transistor extending outwardly from a semiconductor substrate, the fourth transistor having an upper surface and opposing sidewall surfaces, the fourth transistor having a source/emitter region, a body/base region, and having a collector/drain region, and wherein the fourth transistor has a gate on a first one of the opposing sidewall surfaces, the fourth transistor has a body contact on a second one of the opposing sidewall surfaces, the body contact coupled to the gate, such that the transistor gives both metal-oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction;an electrical contact between the collector/drain regions of the second and third transistors to provide an output for the inverter; anda gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter.