Patent ID: 9070424
Filing Date: 2015-06-30
Classification: G11C

Abstract:
1. A resistive type memory sense amplifier circuit, comprising: a first differential output terminal configured to output a first output signal; a second differential output terminal configured to output a second output signal opposite the first output signal; a first input terminal coupled to a bit line associated with a resistive type memory cell; a second input terminal coupled to a reference line associated with a reference memory cell; a first transistor coupled to the second input terminal and to the first differential output terminal, the first transistor being configured to conduct a reference line current; a second transistor coupled to the first differential output terminal and arranged in series with the first transistor, the second transistor being configured to conduct a bit line current; a pre-charge section coupled to an intermediate power supply voltage node, the intermediate power supply voltage node having a voltage level between a power supply voltage and a ground voltage, the pre-charge section including: a first pre-charge transistor coupled to the first differential output terminal and to the intermediate power supply voltage node; and a second pre-charge transistor coupled to the second differential output terminal and the intermediate power supply voltage node, wherein the pre-charge section is configured to operate during a pre-charge stage of the sense amplifier circuit, and wherein a voltage level of the first differential output terminal is configured to swing responsive to a delta average current between the reference line current and the bit line current.