Patent ID: 6049445
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A receiver circuit in an electrostatic discharge (ESD) environment comprising:a pass transistor having an input side receiving a signal, an output side, and a gate susceptible to damage when an ESD potential is present;a protection circuit having:(a) a first rail providing an operating voltage potential to the gate of the pass transistor;(b) a second rail providing V.sub.CC voltage potential;(c) a third rail providing V.sub.SS voltage potential; and(d) means for electrically decoupling the first rail from the second rail and the third rail;wherein the protection circuit provides (1) the operating voltage potential to the gate when an ESD potential is not present, and (2) a voltage which tracks the ESD potential when the ESD potential is present at the input side of the pass transistor.