Patent ID: 8299566
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A structure, comprising: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of said array of through wafer vias extending from said top surface of said substrate to said bottom surface of said substrate; wherein said at least one electrically conductive through wafer via comprises a first trench filled only with an electrical conductor; and wherein said at least one electrically non-conductive through wafer via comprises a second trench having a filling only consisting of a dielectric liner extending to the top surface of said substrate that surrounds an electrically conductive core and a dielectric plug at one end of said second trench.