Patent ID: 8335906
Filing Date: 2012-12-18
Classification: G06F

Abstract:
1. A computer program product for performing a frame management function in a computer system of a machine architecture, the computer system configured to perform dynamic address translation (DAT) using a hierarchy of DAT translation tables to obtain any one of an absolute address of a large block of main storage or a real address of a small block of main storage, wherein a real address is subject to prefixing to form an absolute address, each block of main storage having an associated storage key separate and distinct from any of said DAT translation tables, the computer program product comprising: a storage medium readable by said computer system, said computer readable medium storing instructions for performing: obtaining a machine instruction comprising an opcode for a perform frame management function instruction, the machine instruction further comprising a first register field identifying a first general register and a second general register field identifying a second general register; and executing a clear-frame operation of said machine instruction comprising: based on said operand address, in response to said indicated storage frame being said small block of main storage, clearing said small block of main storage, wherein said clearing sets all bytes of the small block of main storage to zero; and based on said operand address, in response to said indicated storage frame being said large block of main storage, clearing a range of one or more sub-blocks of said plurality sub-blocks of main storage, said range beginning with said initial sub-block of main storage, wherein said clearing sets all bytes of the range of sub-blocks of main storage to zero.