Patent ID: 7164608
Filing Date: 2007-01-16
Classification: G11C

Abstract:
1. An integrated nonvolatile static random access memory circuit formed on a substrate, said integrated nonvolatile static random access memory circuit comprising: a static random access memory cell comprising: a first nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain said digital signal from said latched memory element; and a second nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain a complementary level of said digital signal from said latched memory element; wherein said first nonvolatile memory element and said second nonvolatile memory element are stacked gate nonvolatile memory elements that have a relatively small coupling ratio of capacitance formed by a control gate placed over a floating gate to a total capacitance of said floating gate and said control gate, such that said control gate of said first nonvolatile memory element and said second nonvolatile memory element require a program signal is from approximately +15V to approximately +22V for programming and a erase signal from approximately −15V to approximately −22V for erasing.