Patent ID: 8461675
Filing Date: 2013-06-11
Classification: H01L,H05K

Abstract:
1. A substrate panel for fabricating semiconductor packages, the substrate panel including first and second adjacent package outlines defining locations for formation of first and second semiconductor packages, the substrate panel comprising: a section of plating bar having a first severed end and a second severed end, the section of plating bar including at least a portion in the first section in the first package outline; and one or more severed electrical trace portions different than the plating bar section, each electrical trace portion having a first end at a point where the electrical trace portion connects to the plating bar section in the first package outline and a second severed end, opposite the first end, extending toward the second package outline; an electrical trace having a first end connected to the section of plating bar and extending into and terminating in the first package outline.