Patent ID: 6236103
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A semiconductor circuit comprising:a body having first, second and third regions;said first region being formed of semiconductor material and having a first and a second major surface;said third region having a first and a second major surface;said second region being comprised of a first dielectric layer and positioned on said second major surface of said first region and on said first major surface of said third region so as to lie between and separate said first and third regions;an integrated circuit, comprised of a plurality of active and passive devices, formed in said first region and a plurality of wiring levels on said first major surface of said first region:respective ones of said wiring levels being coupled to respective ones of said active and passive devices;a layer of isolating material on said second major surface of said third region;a metallic deposit on said layer of isolating material;first conductive means for connecting a first one of said wiring levels to said first region and second conductive means for connecting a second one of said wiring levels to said metallic deposit on said layer of isolating material whereby said third region forms the first plate of a capacitor with respect to said metallic deposit on said layer of isolating material which forms the second plate of the capacitor and thermally dissipates heat from said integrated circuit.