Patent ID: 6168891
Filing Date: 2001-01-02
Classification: G03F

Abstract:
A method for correcting a mask pattern for use in manufacturing of a semiconductor integrated circuit, which comprises the steps of: sorting pattern units based on a shape and/or a relative positional relationship with a proximate pattern unit of said pattern units which includes said mask pattern; performing pattern correction on pattern units selected from among said pattern units sorted at said sorting step; said sorting step is a step for sorting out said pattern units as correction-subject units and subject units; said correction step is a step for selectively performing pattern correction on said pattern units sorted out as said correction-subject units at said sorting step; said sorting step is a step for further sorting pattern units sorted out as said correction-subject units, into groups suited for a plurality of pattern correction types respectively; and said correction step is a step for performing an optimal pattern correction on said correction-subject units which are sorted into said groups suited for said plurality of pattern correction types by said sorting step.