Patent ID: 8299516
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A vertical thin film transistor, applied to a substrate, the vertical thin film transistor comprising: a first electrode layer, formed on the substrate, the first electrode layer comprising a first area and a second area, the first area comprising a plurality of concentric annular sub-areas and at least one linking sub-area, each linking sub-area being positioned to link the adjacent concentric annular sub-areas, the second area including at least one sub-area, each sub-area of the second area being positioned in a region between the adjacent concentric annular sub-areas excluding the linking sub-area of the first area, the first area further comprising a circular sub-area positioned inside the innermost one of the concentric annular sub-areas and an innermost linking sub-area positioned to link the innermost one of the concentric annular sub-areas and the circular sub-area, and the second area further including another sub-area positioned in another region between the circular sub-area and the innermost one of the concentric annular sub-areas excluding the innermost linking sub-area of the first area; a first insulating layer, formed on the first area of the first electrode layer; a gate electrode layer, formed correspondingly on the first insulating layer; a second insulating layer, formed correspondingly on the gate electrode layer; a semiconductor layer, formed on the second area of the first electrode layer; a third insulating layer, formed on side surfaces of the gate electrode layer; and a second electrode layer, formed on the semiconductor layer.