Patent ID: 7803700
Filing Date: 2010-09-28
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure on an insulating substrate covered by a insulating layer patterned to define a plurality of apertures, the method comprising: filling the apertures in the insulating layer with amorphous silicon to define a plurality of amorphous silicon features; contacting each of the amorphous silicon features with a respective one of a plurality of crystal seed regions each having either a first crystal orientation or a second crystal orientation that differs from the first crystal orientation; and crystallizing the amorphous silicon features to form a plurality of crystalline silicon features of the first crystal orientation using the crystal seed regions of the first crystal orientation as crystal growth seeds for the contacted amorphous silicon regions and a plurality of crystalline silicon features of the second crystal orientation using the crystal seed regions of the second crystal orientation as crystal growth seeds for the contacted amorphous silicon regions.