Patent ID: 8938587
Filing Date: 2015-01-20
Classification: G06F

Abstract:
1. A coherent attached processor proxy (CAPP), comprising: transport logic having a first interface configured to support communication with a system fabric of a primary coherent system and a second interface configured to support communication with an attached processor (AP) including a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system; snooper logic that services snooped memory access requests received from the system fabric on behalf of the AP; recovery circuitry including an epoch timer that advances at regular intervals, wherein each of a plurality of values of the epoch timer defines an epoch of operation of the CAPP; and master logic that manages memory access requests within the primary coherent system on behalf of the AP, wherein the master logic includes a data structure having one or more entries that track delivery of data from the attached processor to destinations in the primary coherent system, and wherein each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor; and wherein the recovery circuitry, responsive to initiation of recovery operations for the CAPP, performs data recovery operations for the CAPP by transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.