Patent ID: 7143200
Filing Date: 2006-11-28
Classification: G06F

Abstract:
1. The semiconductor integrated circuit comprising a configuration circuit, to which resource mapping is defined from outside the circuit, said configuration circuit including: a base address register having a low-order multi-bit region with fixed logical values and a high-order multi-bit region with variable logical values, and utilized for address space mapping; and a limiting circuit for limiting writing and read-out with respect to a part of the multi-bit region on a high-order side of said base address register to the fixed logical value, the part capable of being varied in bit number, wherein said limiting circuit is a mask circuit for masking a part of the multi-bit region on the high-order side of said base address register into the fixed logical value based on a piece of mask control information, and further comprising a control circuit for controlling said configuration circuit, said control circuit controlling, in a configuration cycle after release of reset of the semiconductor integrated circuit, the operations of: holding inverted data of the fixed logical values input from outside the circuit in the rewritable high-order multi-bit region in said base address register; outputting outside a value held by said base address register through said mask circuit after the holding; and holding data input from outside the circuit in said base address register after the outputting.