Patent ID: 8237201
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. A semiconductor structure comprising: an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns, wherein each of the unit MOS devices comprises: a first unit MOS device in the array; a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types; a third unit MOS device and a fourth unit MOS device in a same column of the array and next to each other; a first contact electrically connecting sources of the third and the fourth unit MOS devices; a second contact electrically connecting drains of the third and the fourth unit MOS devices, wherein gates of the third and the fourth unit MOS devices are electrically connected; and insulating regions isolating the active region of each of the unit MOS devices in the array from active regions of remaining ones of the MOS devices in the array, wherein substantially no active regions of neighboring unit MOS devices are physically interconnected as an integrated active region.