Patent ID: 6055195
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A DRAM-cell delay circuit, comprising:a plurality of external connecting ports including a first external connecting port for receiving an externally-supplied gate voltage, a second external connecting port for receiving an externally-supplied first system voltage representing a high-voltage logic state, a third external connecting port for receiving an externally-supplied buried-plate voltage representing a low-voltage logic state, a fourth external connecting port for receiving an externally-supplied second system voltage representing a high-voltage logic state, a fifth external connecting port for connecting to a ground reference voltage representing a low-voltage logic state, a sixth external connecting port for receiving an externally-supplied switching signal, and a seventh external connecting port for serving as an output port for the DRAM-cell delay circuit,wherein each the DRAM-cell delay circuit can be connected to a successive identical one of the DRAM-cell delay circuit in series through the first and the seventh external connecting ports, in which after the previous DRAM-cell delay circuit completes its function of charge/discharge, the previous DRAM-cell delay circuit produces an output voltage for the successive DRAM-cell delay circuit as an input voltage, and a delay time depends the number of the DRAM-cell delay circuit being used in series.