Patent ID: 8110875
Filing Date: 2012-02-07
Classification: H01L,Y10S

Abstract:
1. An integrated circuit chip, comprising: a plurality of substrate contacts in a semiconductor substrate; two or more wiring levels over said substrate; a plurality of electrically conductive, vertical or angled columnar, charge dissipation structures, each charge dissipation structure of said plurality of charge dissipation structures extending from a top surface of an uppermost wiring level of said two or more wiring levels through each lower wiring level of said two or more wiring levels to and in electrical contact with a respective substrate contact of said plurality of substrate contact, said charge dissipation structures distributed within a perimeter of said integrated circuit chip; and a plurality of circuit structures in said substrate, said charge dissipation structures interspersed between and not in electrical contact with any of said plurality of circuit structures, and being commonly connected.