Patent ID: 7721052
Filing Date: 2010-05-18
Classification: G06F,Y02D

Abstract:
1. A computer system comprising a control node and a computing node, wherein the control node comprises: a first processor which executes computational processing; a storage unit coupled to the first processor which stores a user program executed by the computing node; and a first interface coupled to another node, and sends a user program to the computing node, wherein the computing node comprises: a second processor which executes computational processing; a memory coupled to the second processor; a second interface coupled to the second processor and to the control node; and a memory controller coupled to the memory, and executes the user program which is sent from the control node, wherein a storage area of the memory is divided into memory ranks which are in units which the memory controller can control power independently, wherein a supplied power state of the memory is controlled, for each of the memory ranks, to one of an active state in which the storage area included in the memory rank can be accessed from the second processor, and an inactive state in which access from the second processor to the storage area is delayed, wherein the first processor sends a message including a memory capacity required to execute the user program, and wherein, in case of which the second processor receives the message sent from the first processor, the second processor puts the memory rank corresponding to the required memory capacity into the active state before the user program is loaded into the memory.