Patent ID: 7238572
Filing Date: 2007-07-03
Classification: H01L

Abstract:
1. A method of manufacturing an EEPROM cell, the method comprising: growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate, wherein the select transistor is spaced apart from the control transistor, wherein the select transistor is formed on the tunneling oxide layer and includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and wherein the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.