Patent ID: 7145819
Filing Date: 2006-12-05
Classification: G11C

Abstract:
1. A dynamic random access memory (DRAM) that comprises a read mode having a pre-charge state, the DRAM comprising: a memory space having a plurality of memory cells, at least a subset of the memory cells being capable of storing signals corresponding to a first logic state or a second logic state, wherein one of the logic states is weaker than the other logic state; a plurality of logic circuits, at least one of which comprises CMOS logic; a plurality of bit lines for reading and writing data to the at least a subset of the memory cells; and a circuit to, in the pre-charge state, pre-charge at least a first one of the bit lines to a predetermined voltage biased toward the weaker logic state, wherein the weaker logic state is a low logic state, and wherein the circuit to pre-charge comprises a pull down transistor coupled between the first one of the bit lines and a first supply voltage, wherein the pull down transistor is a P channel FET.