Patent ID: 7157346
Filing Date: 2007-01-02
Classification: H01L

Abstract:
1. A method for reducing charging damage to integrated circuits during semiconductor manufacturing, comprising: providing a semiconductor substrate comprising thereon a number of integrated circuit dies, said integrated circuit dies being separated from each other by scribe lanes surrounding each said integrated circuit die, wherein each said integrated circuit die comprises thereon at least a first device region, a second device region and at least one non-active region; forming a first implant mask over said semiconductor substrate, said first implant mask covering said second device region and said non-active region, while exposing said first device region; implanting dopant species into exposed said semiconductor substrate within said first device region to form first doping regions therein; stripping said first implant mask; forming a second implant mask over said semiconductor substrate, said second implant mask covering said first device region, while exposing said second device region and a portion of said non-active region; and implanting dopant species into exposed said semiconductor substrate within said second device region to form second doping regions therein.