Patent ID: 7958180
Filing Date: 2011-06-07
Classification: G06F

Abstract:
1. A multiplication apparatus, comprising: a compressor circuit; an accumulator coupled to the compressor circuit; and an adder circuit coupled to the accumulator, wherein: the compressor circuit receives two or more partial products of a multiplication operation as inputs, the two or more partial products having at least one first negate bit fused therein, the compressor circuit adds the two or more partial products with the fused at least one first negate bit to each other to generate a first sum output value and a first carry-out output value that are input to the accumulator, the accumulator receives the first sum output value, the first carry-out output value, and a second negate bit as inputs and generates a second sum output value and second carry-out output value based on the first sum output value, the first carry-out output value, and the second negate bit, and the adder circuit generates a multiplication result based on the second sum output value and the second carry out output value, the at least one first negate bit comprises a first negate bit, a third negate bit, and a fourth negate bit, the first negate bit is provided at a bit zero position of a second partial product input to the compressor circuit, the third negate bit is provided at a bit one position of the second partial product and bits three, two, and one of a third partial product input to the compressor circuit, and the fourth negate bit is provided at a bit zero position of the third partial product and bits five, four, three, two, one, and zero of a fourth partial product input to the compressor circuit.