Patent ID: 7265412
Filing Date: 2007-09-04
Classification: H01L

Abstract:
1. A semiconductor memory device having a word line, a bit line, a charge compensating circuit connected to a node to compensate for charges, and an access transistor connected between said bit line and said charge compensating circuit, wherein said access transistor includes a pair of impurity regions provided in a main surface of a semiconductor substrate and arranged spaced apart from each other by a prescribed distance to define a channel formation region, a first gate electrode provided on said semiconductor substrate, with a gate insulating film interposed therebetween, to face said channel formation region, and a second gate electrode adjacent to said first gate electrode, provided on said semiconductor substrate, with a gate insulating film interposed therebetween, to face said channel formation region, one of the impurity regions of said access transistor is connected to said bit line and the other of the impurity regions of said access transistor is connected to said node, said first gate electrode is connected to said word line, and said second gate electrode is connected to an ON/OFF control electrode of said charge compensating circuit.