Patent ID: 6566918
Filing Date: 2003-05-20
Classification: G06F,H03K

Abstract:
A divide-by-N clock divider circuit, comprising:a clock input terminal; a clock output terminal; a first logical NOR circuit having a first input terminal coupled to the clock input terminal of the clock divider circuit, a second input terminal, and an output terminal coupled to the clock output terminal of the clock divider circuit; and a control circuit comprising Nâˆ’1 flip-flops coupled in series, each flip-flop having a clock terminal coupled to the clock input terminal of the clock divider circuit, each flip-flop having a data input terminal and a data output terminal, the data output terminal of each flip-flop except a last flip-flop being coupled to the data input terminal of a succeeding flip-flop in the series, the last flip-flop in the series having a data output terminal coupled to a data input terminal of a first flip-flop in the series and further coupled to the second input terminal of the first logical NOR circuit.