Patent ID: 6507532
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array divided into a plurality of banks each having a plurality of memory cells, said plurality of banks driven into active state independently of each other; central control circuitry arranged on one side of said memory array, receiving externally supplied external clock signal and external address signal, generating an internal clock signal and an internal address signal asynchronous with said internal clock signal and transmitting, in one direction, said internal clock signal and said internal address signal of multiple bits commonly to said plurality of banks of said memory array; a preprocessing circuit provided corresponding to each of said plurality of banks of said memory array, latching predetermined bits of said internal address signal synchronously with a latch timing signal received from said central control circuitry and predecoding the latched internal address signal bits to generate a predecode signal; and a selection circuit provided corresponding to each of said plurality of banks of said memory array for selecting an addressed memory cell of a corresponding bank according to the predecode signal from a corresponding preprocessing circuit.