Patent ID: 6677226
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A method for forming an integrated circuit comprising the steps of:providing a semiconductor substrate; forming a first conductive layer overlying the semiconductor substrate; removing a portion of the first conductive layer to define a fuse and a conductive interconnect; forming a first dielectric layer overlying the fuse and the conductive interconnect; forming a bonding pad overlying the first dielectric layer, wherein the bonding pad comprises an anti-reflective layer overlying a second conductive layer, and wherein the bonding pad is electrically shorted to the conductive interconnect; forming a second dielectric layer overlying the fuse and the bonding pad; etching the second dielectric layer using a first etch process to form an exposed portion of the first dielectric layer and to form an exposed portion of the anti-reflective layer, wherein the exposed portion of the first dielectric layer overlies the fuse, and wherein the second conductive layer is not exposed by the first etch process; and etching the exposed portion of the anti-reflective layer and the exposed portion of the first dielectric layer using a second etch process to leave a remaining portion of the first dielectric layer overlying the fuse and to expose a portion of the second conductive layer, the exposed portion of the anti-reflective layer having a first etch rate and the exposed portion of the first dielectric layer having a second etch rate, wherein the first etch rate and the second etch rate are substantially the same such that an etch selectivity of approximately 1:1 is achieved between the exposed portion of the anti-reflective layer and the exposed portion of the first dielectric layer.