Patent ID: 8977919
Filing Date: 2015-03-10
Classification: G01R,H01J

Abstract:
1. An integrated circuit die comprising: A. a bottom surface including Parallel Test Input (PTI) contact points, a Test Data input (TDI) contact point, Test Control Input (TCI) contact points, a Test Data Output (TDO) contact point, and Parallel Test Input/Output (PTIO) contact points; B. a top surface including PTO contact points, a TDO contact point, Test Control Output (TCO) contact points, a TDI contact point, and PTIO contact points; C. a Test Control Port (TCP) coupled to the bottom surface TDI, TCI and TDO contact points, to the top surface TDO, TCO and TDI contact points, and having control (CTL) outputs; D. a Parallel Scan Circuit having PTI inputs coupled to the bottom surface PTI contact points, control inputs coupled to some CTL outputs of the TCP and PTO outputs; E. a Test Circuit (TC) having inputs coupled to the PTO outputs of the Parallel Scan Circuit, input/outputs coupled to the bottom and top PTIO contact points and control inputs connected to some CTL outputs of the TCP; F. first coupling means having inputs coupled to the PTO outputs of the Parallel Scan Circuit, a control input coupled to a CTL output of the TCP and outputs coupled to the top surface PTO contact points; and G. second coupling means having inputs coupled to the bottom surface PTI contact points, a control input coupled to a CTL output of the TCP and outputs coupled to the top surface PTO contact points.