Patent ID: 6653695
Filing Date: 2003-11-25
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising a semiconductor substrate and a substantially linear gate electrode pattern which is formed on the semiconductor substrate, the semiconductor substrate having two transistor regions and a sandwiched region formed between the two transistor regions, the gate electrode pattern being formed on the transistor regions and the sandwiched region and having paired first and second long sides and a pair of short sides, a convex portion in which at least a part of the sandwiched region is arranged being included in the first long side, a concave portion facing at least the entire length of the convex portion being included in the second long side and being substantially in the sandwiched region, a length of the concave portion parallel to the second long side being longer than a length of the convex portion parallel to the first long side, a width of the concave portion parallel to the short side being smaller than a diameter of a contact portion formed in the sandwiched region and on the gate electrode pattern.