Patent ID: 7327609
Filing Date: 2008-02-05
Classification: G11C

Abstract:
1. A method of verifying a program state of a non-volatile memory device including a multi-bit memory cell transistor providing more than two different program states, the method including: programming the multi-bit memory cell transistor from a first program state to a second program state; selecting one of a plurality of reference memory cells wherein the selected reference memory cell corresponds to the second program state; after programming the multi-bit memory cell transistor to the second program state and after selecting the reference memory cell corresponding to the second program state, copying a reference current defined by the selected reference memory cell at a selected one of a plurality of current path generating transistors electrically connected in parallel wherein the reference current passes through the selected current path generating transistor without passing through the selected reference memory cell; comparing a current flowing through the multi-bit memory cell transistor programmed to the second memory state and the reference current flowing through the selected current path generating transistor; and verifying programmning the multi-bit memory cell transistor to the second program state responsive to comparing the currents flowing through the multi-bit memory cell and the selected current path generating transistor; and after verifying programming the multi-bit memory cell transistor, reading a program state of the multi-bit memory cell transistor wherein a current path of the reference current flowing through the selected current path generating transistor used to verify programming of the multi-bit memory cell transistor coincides with a current path used to read the program state of the multi-bit memory cell transistor.