Patent ID: 6514807
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A method for fabricating a semiconductor device that can be applied in system on chip (SOC), comprising:providing a substrate having a memory cell region and a peripheral circuit region; forming a plurality of bit-lines in the memory cell region; forming a first and a second dielectric layers respectively in the memory cell region and the peripheral circuit region; forming a plurality of gates in the memory cell region and the peripheral circuit region; performing a ion implantation step to form a plurality of P type lightly doped drains (LDDs) in the substrate besides the gates in a PMOS device region within the peripheral circuit region without forming an anti-punch through region in the substrate of the memory cell region; forming a plurality of spacers on sidewalls of the gates, wherein the spacers formed on the sidewalls of the gates in the memory cell region are connected to one another; and performing a first ion implantation step to form a plurality of P type source/drain regions in the substrate besides the gates in the PMOS device region within the peripheral circuit region.