Patent ID: 7259992
Filing Date: 2007-08-21
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array formed on a well region of a semiconductor substrate, said memory cell array having word lines, bit lines crossing the word lines, and electrically rewritable and non-volatile memory cells disposed at the crossings between the word lines and bit lines, drain and source of each memory cell being coupled to a bit line and a source line, respectively; and a sense amplifier circuit connected to the bit lines for reading data of selected memory cells, wherein said device has such a data read mode as to detect whether cell current flows or not from a selected bit line to the source line in accordance with data of a selected memory cell under the condition of: the well region is set at a base potential; a selected word line is applied with a read voltage, which turns on or off the selected memory cell in accordance with data thereof; the source line is applied with a first positive voltage higher than the base potential; and the selected bit line is applied with a second positive voltage higher than the first positive voltage, wherein said memory cell array is formed of NAND cell units so arranged as to share a source line, each NAND cell unit having memory cells arranged in the direction of the bit line and connected in series, control gates of which are coupled to different word lines, respectively, a first select gate transistor for coupling one end of the NAND cell unit to a bit line, and a second select gate transistor for coupling the other end to the source line, wherein in the data read mode, non-selected word lines in a NAND cell unit including the selected memory cell are applied with a pass voltage, which turns on memory cells without regard to cells' data; and a non-selected bit line disposed adjacent to the selected bit line is applied with the first positive voltage, and wherein in the data read mode, in case the selected memory cell in the NAND cell unit is positioned in a certain region near the bit line, the source line is set at ground potential, while in case the selected memory cell is positioned outside of the certain region, the first positive voltage applied to the source line is changed to be higher as the position of the selected memory cell becomes nearer to the source line.