Patent ID: 8537603
Filing Date: 2013-09-17
Classification: G11C,H01L

Abstract:
1. An SRAM cell, comprising: a single bit line; a pair of control signal lines corresponding to the bit line and including a single write control signal line and a single read control signal line; a feedback control transistor; a write control transistor, a read control transistor, and a buffer transistor having an inverse polarity of the feedback control transistor; a first inverter having an output signal node and an input signal node; and a second inverter having an output signal node and an input signal node; wherein the first and second inverters operate by each connecting with a power supply line and a power feedback line, the output signal node of the first inverter is connected to the input signal node of the second inverter, the output signal node of the second inverter and the input signal node of the first inverter are connected through the feedback control transistor, the input signal node of the first inverter and the bit line are connected through the write control transistor, each gate of the feedback control transistor and the write control transistor is connected to the write control signal line, a gate of the buffer transistor is connected to the output signal node of the second inverter, which is connected to the feedback control transistor, a source of the buffer transistor is connected to the power feedback line, a drain of the buffer transistor and the bit line are connected through the read control transistor, and a gate of the read control transistor is connected to the read control signal line.