Patent ID: 7330924
Filing Date: 2008-02-12
Classification: H04J,H04L

Abstract:
1. A physical layer interface for a network interface, comprising: a plurality of input/output pins, the input/output pins coupled for being multiplexed, the input/output pins multiplexed into a physical layer interface selected, the physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface; the input/output pins internal to a programmable logic device and being for access to and from a processor block located in the programmable logic device; the programmable logic device including tie-off pins; a first portion of the tie-off pins usable for configuring the programmable logic device as a network device, the network device being selected from a group consisting of a network router, a network bridge, and a network hub; a second portion of the tie-off pins usable for disabling an internal processor bridge of the processor block for use of the programmable logic device with an external processor bridge.