Patent ID: 6912172
Filing Date: 2005-06-28
Classification: G11C

Abstract:
1. A memory apparatus comprising: a first memory chip; and a second memory chip; wherein said first memory chip has a first terminal, a second terminal and a voltage circuit, wherein said second memory chip has a third terminal, wherein said first terminal of said first memory chip and said third terminal of said second memory chip are supplied an operation voltage, wherein said second terminal of said first memory chip is supplied one of a first state signal and a second state signal according to a voltage level of said operation voltage supplied to said third terminal of said second memory chip, wherein when said second terminal is supplied said first state signal, said first memory chip is supplied a first voltage as said operation voltage and generates an internal operation voltage from said first voltage by said voltage circuit, wherein when said second terminal is supplied said second state signal, said first memory chip is supplied a second voltage as said operation voltage and generates said internal operation voltage from said second voltage by said voltage circuit, and wherein said first voltage is lower voltage than said second voltage.