Patent ID: 6468099
Filing Date: 2002-10-22
Classification: H01L,Y10S

Abstract:
A semiconductor device fabricating method, comprising the steps of:forming a semiconductor substrate having a first active region and a second active region that are isolated by a shallow trench isolation (STI) structure; forming a buffer oxide film in the first and second active regions on the substrate; forming a nitride film on the buffer oxide film and the STI; forming a first photo-resist pattern on the nitride film to expose a portion of the STI and edges of the adjacent second active region; etching unmasked portions of the buffer oxide film and the nitride film to open the edges of the second active region to a predetermined size, and thereafter removing the first photo-resist pattern; forming a field oxide film in contact with the STI on the opened portion of the second active region by performing an oxidation process using residual nitride film as a mask; performing a CMOS well ion-implantation and a channel ion-implantation; forming a CVD oxide film on the resultant structure; forming a second photo-resist pattern on the CVD oxide film to mask a portion the STI and the adjacent first active region; etching the CVD oxide film that is not masked by the second photo-resist pattern to thereafter remove the second photo-resist pattern; etching the nitride film and buffer oxide film by utilizing the residual CVD oxide film as a mask so that the nitride film and buffer oxide film remain in the first active region and are opened in the second active region; forming a first thermal oxide film for a gate oxide film on the second active region; etching the nitride film and the oxide film that remain in the first active region to thereby open the first active region; and forming a second thermal oxide film for a gate oxide film at a thickness less than the thickness of the first thermal oxide film on the opened portion of the first active region.