Patent ID: 6319784
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include gate electrodes and associated source and drain regions;depositing a resist protective dielectric layer overlying said semiconductor device structures;etching away said resist protective dielectric layer where it is not covered by a mask exposing a top surface of said qate electrode and exposing a surface of said semiconductor substrate overlying said source and drain regions wherein a native oxide layer having a thickness of between 9 and 15 Angstroms forms on said exposed surfaces;annealing said substrate using H2at a high temperature of 800 to 1150.degree. C. and at a low pressure of 6 to 100 Torr whereby said native oxide thickness is reduced to between 3.5 and 7.3 Angstroms and whereby said exposed surface of said semiconductor substrate is recrystallized simultaneously;thereafter depositing a metal layer overlying said resist protective dielectric layer, said exposed surface of said gate electrode, and said exposed surface of said semiconductor substrate;siliciding said metal layer; andremoving said metal layer where it is not transformed to a metal silicide leaving said metal silicide overlying said gate electrode and said source and drain regions to complete fabrication of said integrated circuit device.