Patent ID: 8843538
Filing Date: 2014-09-23
Classification: G01R

Abstract:
1. A circuit comprising: a modulator configured for oversampling a current flow and generating an oversampled signal; a first decimation filter stage coupled to the modulator, the first decimation filter stage configured for decimating the oversampled signal to generate a high resolution signal indicating instantaneous current data; a digital multiplier coupled to the first decimation filter stage, the digital multiplier configured for generating squared current data from the instantaneous current data; a second decimation filter stage coupled to the digital multiplier, the second decimation filter stage configured for decimating the squared current data to generate a sum of squared current data; and a third decimation filter stage coupled to the output of the first decimation filter stage, the third decimation filter stage configured for reducing a data rate of the high resolution signal and generating accumulated current data for charge flow accumulation.