Patent ID: 7372902
Filing Date: 2008-05-13
Classification: H03K,H05B,Y02B

Abstract:
1. A PWM signal generating circuit comprising: a first counter circuit periodically changing a PWM signal output therefrom into an active state; and a second counter circuit changing the PWM signal, which has been changed into the active state by said first counter circuit, into an inactive state within each cycle, wherein said second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state, and wherein said second counter circuit increases or decreases, at a predetermined rate in a predetermined period, the time period between (i) the time when the PWM signal is changed into the active state and (ii) the time when the PWM signal is changed into the inactive state.