Patent ID: 6821860
Filing Date: 2004-11-23
Classification: H01L,H03G

Abstract:
A method for production of an integrated limiter with PIN diodes, comprisinga series of layers of a diode structure (2) is deposited on a highly conductive n+substrate (1), at least one diode is structured by means of a mesa structure, that extends into the n+substrate (1), the diode is electrically connected and the surface is covered with a first planarizing layer (9â€²), on the first planarizing layer (9â€²) there is structured at least one ohmic resistor, there is deposited a first BCB insulating layer, through which the diodes and the resistor are interconnected by means of conductor tracks, a second planarizing layer (16) is structured with a second BCB insulating layer, on the second planarizing layer there is formed at least one capacitor (17, 18, 19), which is interconnected by means of conductor tracks (17) with the diode and resistor via contact holes, a third planarizing layer (20) is structured with a third BCB insulating layer, via contact holes in the third planarizing layer (20), the structure is interconnected by means of conductor tracks (21) and contacted by connecting metallization (22).