Patent ID: 6462385
Filing Date: 2002-10-08
Classification: H01L,Y10S

Abstract:
A semiconductor memory device having a semiconductor substrate defining a principal surface, a peripheral circuit region and memory cell region defined on the principal surface of the semiconductor substrate, comprising:a first well formed in the peripheral circuit region; a first conductivity type second well formed in the memory cell region; a second conductivity type third well formed in the memory cell region and having the same depth as the depth of the second well; and a device element isolator formed in the memory cell region for isolating a transistor formed in the second well from a transistor formed in the third well, wherein the second and third wells extend to a level under a transistor isolator, the second and third wells include a first layer having a depth shallower than the first well, and a second layer having substantially the same depth as the first well, the first layer of the second well overlaps the first layer of the third well under a transistor isolator, and the second layer of the second well and the second layer of the third well are isolated from each other.