Patent ID: 6093584
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of making a semiconductor chip package, comprising the steps of:providing a first sacrificial layer;providing a dieleclric base material on the first sacrificial layer;providing an array of conductive pads on said dielectric base material such that a central region is defined by the pads;attaching a back surface of a semiconductor chip to the sacrificial layer within the central region so that a contact bearing surface of the chip faces away from the sacrificial layer;electrically connecting each contact to a respective pad;depositing curable dielectric material on the pads and chip such that the pads, electrical connections and chip are each encapsulated and curing the dielectric material;providing a second sacrificial layer over the cured dielectric material;forming apertures extending between the first and second sacrificial layers, at least some of said apertures extending through the cured dielectric material, through at least some of said pads and through the dielectric base material;depositing a conductive metal in said apertures so as to form conductive vias extending between the sacrificial layers, at least some of said conductive vias being electrically connected to at least some of said pads; andremoving at least a portion of each said sacrificial layer.