Patent ID: 6225822
Filing Date: 2001-05-01
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas, each of the areas having a plurality of area input signals and being programmable to produce a plurality of area output signals which are any of a plurality of logic functions of the area input signals;a first plurality of fast signal conductors extending substantially parallel to the columns of areas;a plurality of input pins configured to respectively apply device input signals to the conductors in the first plurality;a second plurality of fast signal conductors extending substantially parallel to the columns of areas;a plurality of drivers configured to respectively apply area output signals to the conductors in the second plurality;a third plurality of fast signal conductors associated with each of the rows of areas and extending substantially parallel and adjacent to the associated row;first programmable logic connector circuitry associated with each of the conductors in each of the third pluralities and configured to select a signal from multiple conductors in the first and second pluralities for application to that conductor in that third plurality; andsecond programmable logic connector circuitry associated with each of the areas and configured to select a signal from multiple conductors in the third plurality associated with the row that includes that area for application as an area input signal to that area.