Patent ID: 9164831
Filing Date: 2015-10-20
Classification: G06F,H03M

Abstract:
1. A memory controller that controls a memory unit, comprising: an encoding unit that generates an error detection code for data to be written to the memory unit, and generates an error correction code capable of correcting t (t is an integer of 2 or more) symbols with respect to the data and the error detection code; a memory interface that includes n (n is an integer of 2 or more) number of channels, writes the data, the error detection code, and the error correction code to the memory unit for each of the channels, and reads out the data, the error detection code, and the error correction code from the memory unit as read data for each of the channels; n number of first error correction decoding units that each perform a first error correction decoding process capable of correcting s (s is an integer equal to or greater than 1 and smaller than t) symbols on the read data for each of the channels; n number of error detecting units that perform an error detecting process for each of the channels based on data decoded by the first error correction decoding process and an error detection code; and a second error correction decoding unit, number of which is smaller than n and which performs a second error correction decoding process capable of correcting t symbols on the read data for the channel from which an error is detected by the error detecting unit.