Patent ID: 8703555
Filing Date: 2014-04-22
Classification: H01L

Abstract:
1. A method of asymmetrically forming MOS transistors of an SRAM memory device having a logic region and a core region, the method comprising: forming a gate structure over a first type semiconductor body and defining a channel therebelow in the semiconductor body of the MOS transistors in the logic and core regions of the device; masking only one of a source and drain regions of the MOS transistors in the core region, the masked regions generally corresponding to moat tip regions; forming a recess substantially aligned to the gate structure in the semiconductor body in both of the source and drain regions of the logic region of the device; forming a recess substantially aligned to the gate structure in the semiconductor body in the other unmasked one of the source and drain regions of the core region of the device; epitaxially growing silicon germanium in the recesses; removing the mask; further comprising: forming offset spacers on the lateral edges of the gate structure before forming the recesses, wherein the recesses are aligned in the semiconductor body with respect to the offset spacers; performing a p-type extension region implant after formation of the offset spacers and before forming the recesses; and performing a thermal process after the extension region implant and before forming the recesses, wherein the extension regions slightly diffuse laterally in response thereto such that edges thereof extend below the offset spacers toward the gate structure.