Patent ID: 7149141
Filing Date: 2006-12-12
Classification: G11C

Abstract:
1. In a memory device having a plurality of write receivers for receiving respective data bits from a data bus and a plurality of read transmitters for applying respective data bits to a data bus, a method of operating the write receivers in either a high-power, low write latency mode or a low-power, high write latency mode, comprising: applying power to the write receivers when the read transmitters are not active regardless of whether the write receivers are active when the write receivers are being operated in the high-power, low write latency mode; removing power from the write receivers when the read transmitters are active when the write receivers are being operated in the high-power, low write latency mode; applying power to the write receivers when the write receivers are active and the read receivers are not active when the write receivers are being operated in the low-power, high write latency mode; and removing power to the write receivers when either the write receivers are not active or the read transmitters are active when the write receivers are being operated in the low-power, high write latency mode.