Patent ID: 6218877
Filing Date: 2001-04-17
Classification: G06F,H03L

Abstract:
A semiconductor device comprising:an input terminal through which an input signal is input to the semiconductor device;an output terminal through which an output signal is output from the semiconductor device; anda phase adjusting circuit having a first node which is coupled to said input terminal and through which a first signal is input, and having a second node which outputs a second signal and which is coupled to said output terminal, said phase adjusting circuit adjusts phases of the input signal and the output signal output from said output terminal,the first signal having a first delay time corresponding to a period starting from a time when the input signal is input to said input terminal until a time when the input signal is input to said first node as the first signal, and the output signal having a second delay time corresponding to a period starting from a time when the second signal is output from said second node until a time when the second signal is output from said output terminal as the output signal,said phase adjusting circuit includinga delay selection circuit that adjusts a phase of the first signal based on a control signal to provide the second signal,an internal delay reproduction circuit that delays the second signal by the first and second delay times to provide a third signal,a delay adjusting circuit that adjusts a phase of the third signal to provide a fourth signal,a delay time control section that controls said delay adjusting circuit, anda phase comparator that compares a phase of the first signal with a phase of the fourth signal to provide the control signal.