Patent ID: 7453310
Filing Date: 2008-11-18
Classification: H03K

Abstract:
1. A switching circuit comprising: a first P-channel MOS-FET; a second P-channel MOS-FET, both P-channel MOS-FETs being connected in series so that sources of both P-channel MOS-FETs are connected to a common source junction and cathodes of parasitic diodes of both P-channel MOS-FETs are also connected to the common source junction, gates of both P-channel MOS-FETs being connected to a common gate junction; and a Zener diode for protecting the P-channel MOS-FETs, connected between the common source junction and the common gate junction, wherein: both P-channel MOS-FETs are simultaneously turned on and off by controlling a voltage supplied to the common gate junction; and a third P-channel MOS-FET is connected in the switching circuit in such a manner that its drain and an anode of its parasitic diode are connected to the common gate junction, its source is connected to the drain of the second P-channel MOS-FET, and its gate is connected to the drain of the first P-channel MOS-FET, thereby bringing the switching circuit to a non-conductive state when a gate voltage supplied to the common gate junction becomes indefinite.