Patent ID: 6133107
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A process for manufacturing a DMOS device in an integrated circuit comprising:forming an epitaxial layer of a first conductivity type over a substrate;forming a deep barrier region within adjoining surface portions of the substrate and the epitaxial layer, the deep barrier region having a higher dopant concentration of the first conductivity type than the epitaxial layer;implanting a deep drain region extending from a surface of the epitaxial layer to outer peripheral regions of the deep barrier region to define a well region within the epitaxial layer;implanting a body region of a second conductivity type within the well region;implanting first and second source regions of the first conductivity type at a surface of the well region and within the body region;forming a first insulated gate above an outer portion of the first source region, the body region, and the well region;implanting a guard ring in the well region and surrounded by the body region, the guard ring having a predetermined depth within the well region;forming a second insulated gate above an inner central portion of the second source region, the body region, and the well region;depositing a conductive drain contact over the deep drain region; anddepositing a conductive source contact over the first and second source regions and the central surface area of the well region inside the second insulated gate.