Patent ID: 7586774
Filing Date: 2009-09-08
Classification: G11C

Abstract:
1. A stacked ferroelectric memory device comprising: a plurality of selection transistors on a substrate, wherein each of the selection transistors includes a first gate structure, a first impurity region and a second impurity region; a first insulating interlayer covering the selection transistors; a plurality of bit line structures electrically connected to the first impurity regions; a second insulating interlayer covering the bit line structures; a plurality of plugs disposed through the first and the second insulating interlayers, wherein each of the plugs makes contact with the second impurity region; a plurality of active patterns on the plugs and the second insulating interlayer, wherein each of the active patterns makes contact with the plugs; and a plurality of ferroelectric transistors on the active patterns, wherein each of the ferroelectric transistors includes a second gate structure, a third impurity region and a fourth impurity region, and wherein the second gate structure includes a ferroelectric layer pattern and a conductive pattern.