Patent ID: 6939784
Filing Date: 2005-09-06
Classification: B81B,B81C,H01L

Abstract:
1. A method of making a wafer scale package for electronic circuits, comprising the steps of: placing electronic circuits each having at least one electronic device and associated plurality of signal lines comprised of at least one metal layer at respective circuit locations on a base wafer; forming cavities on an undersurface of a cover wafer at respective circuit locations to accommodate said respective circuit electronic devices, when said wafers are joined; forming and metalizing vias in said cover wafer; applying at least one initial layer of metal in and on an undersurface of said vias and thereby forming via pads; applying at least one initial layer of metal on a top surface of said base wafer around the periphery of each said location; and applying at least one initial layer of metal on an undersurface of said cover wafer around the periphery of each said location; metalizing a periphery of each said circuit location on said base and cover wafers with at least one intermediate layer of metal; metalizing an electric contact between said via pads and said signal lines with at least one intermediate layer of metal; wherein the number and thickness of metal layers at the periphery of each said location is substantially equal to the number and thickness of metal layers at said vias and signal lines for ensuring planar alignment of the base and cover wafers when joined together; joining said base and cover wafers at predetermined pressure, temperature and time conditions to form a peripheral hermetic seal around each said circuit location and a via hermetic seal around each said bottom of said vias; and dicing said joined and sealed wafers along said locations to provide individual die packages.