Patent ID: 7038643
Filing Date: 2006-05-02
Classification: G09G,G11C

Abstract:
1. A driving device of a liquid crystal display (LCD) panel having a plurality of blocks arranged in sequence, each of the plurality of blocks comprising: a first switching element having drain and gate terminals to which one of a start pulse and an output signal of a previous block in the sequence is supplied; a second switching element having a drain terminal connected to a source terminal. of the first switching element, and a gate terminal to which a first clock signal is supplied; a third switching element having a source terminal connected to a source terminal of the second switching element, and a drain terminal connected to a first voltage input terminal; a fourth switching element having a drain terminal connected to a second voltage input terminal, a gate terminal to receive a second clock signal that is not supplied to the second switching element, and a source terminal connected to a gate terminal of the third switching element; a fifth switching element having a drain terminal connected to the source terminal of the fourth switching element, a gate terminal connected to a contact node between the source terminals of the second and third switching elements, and a source terminal connected to the first voltage input terminal; a sixth switching element having a drain terminal to receive a third clock signal that is not supplied to the second and fourth switching elements, a gate terminal connected to the contact node, and a source terminal connected to a corresponding output terminal; a seventh switching element having a drain terminal connected to the corresponding output terminal, a gate terminal connected to the source terminal of the fourth switching element and the gate terminal of the third switching element, and a source terminal connected to the first voltage input terminal; an eighth switching element having drain and gate terminals to which one of the start pulse is supplied and connected to an output terminal of the next block in the sequence; and a ninth switching element having a source terminal connected to the source terminal of the eighth switching element, a gate terminal to receive a fourth clock signal that is not supplied to the second, fourth, and sixth switching elements, and a drain terminal connected to the source terminal of the second switching element and the gate terminal of the sixth switching element.