Patent ID: 7635887
Filing Date: 2009-12-22
Classification: H01L

Abstract:
1. An integrated circuit arrangement comprising: a substrate including a plurality of integrated semiconductor components; a first conductive structure layer containing a plurality of conductive structures; a capacitor comprising a bottom electrode, a capacitor dielectric, and a top electrode comprising a first side that faces away from the capacitor dielectric, the bottom electrode comprising a different material from the conductive structures, the bottom electrode further comprising a vertical section that is substantially vertical relative to an upper surface of the substrate, wherein the vertical section of the bottom electrode projects into and adjoins to a second conductive structure layer that is arranged further away from the substrate than the first conductive structure layer; wherein the plurality of conductive structures and at least one of interspaces between the plurality of conductive structures and a plurality of cutouts included in the conductive structures comprise an uneven area enlarged by at least 30 percent in comparison with an even area having a same contour as the capacitor; wherein the capacitor is arranged at the uneven area, and the bottom electrode is coupled with a second electrically insulating material at a side facing away from the capacitor dielectric between the conductive structures.