Patent ID: 9087036
Filing Date: 2015-07-21
Classification: G06F,H04L

Abstract:
1. A non-transitory machine-readable storage medium having instructions stored thereon, which when executed by a machine, are configured to cause the machine to generate an apparatus, comprising: an initiator module modeled as a first executable behavioral model; a target module modeled as a second executable behavioral model, where information regarding a burst transaction is communicated between the initiator module and the target module of a System on a Chip through a communications channel, where the burst transaction consists of two or more individual transfers and the communications channel is separate and distinct from both the initiator module and the target module; and one or more timing function routines configured to obtain timing variables for the burst transaction that uses a communications protocol that includes distinct fields of a command field and a timing field for the burst transaction communicated between the initiator module and the target module, where the timing field includes 1) timing variables, or 2) derived timing information based on the timing variables, where either the initiator module or the target module use the one or more timing function routines to determine the timing information associated with each of the two or more individual transfers within the burst transaction during a simulation, by either 1) making a direct function call to the communications channel that the burst transaction passes through to retrieve information about the burst transaction including its timing information or 2) basing the timing information on the timing variables or the derived timing information contained in the timing field for the burst transaction, and then using the one or more timing function routines to derive timing information associated with each individual transfer within the burst transaction during the simulation, where the derived timing information associated with each individual transfer within the burst transaction is correlatable to give an accurate correlation to a clock cycle operation of the System on a Chip during the simulation.