Patent ID: 6130131
Filing Date: 2000-10-10
Classification: G11C,H01L

Abstract:
A method for fabricating a flash memory, the method comprising:providing a substrate having an oxide layer;forming a first polysilicon layer over the oxide layer;patterning the first polysilicon layer and the oxide layer to thereby expose the substrate by both sides of a patterned first polysilicon layer, wherein the first polysilicon layer is patterned to form the patterned first polysilicon layer;forming diffusion regions in the substrate at one side of the patterned first polysilicon layer;forming a plurality of implantation regions in the substrate at both sides of the patterned first polysilicon layer, wherein at one side of each patterned first polysilicon layer the implantation regions are enclosed by the diffusion regions, while at another side of each patterned first polysilicon layers there is no diffusion region formed between the patterned first polysilicon layers;forming a dielectric layer over the first polysilicon layer; andforming and patterning a second polysilicon layer to form control gates perpendicular to patterned polysilicon layers and further patterning the dielectric layer and the pattered first polysilicon layer, wherein the patterned first polysilicon layer is further patterned to form floating gates, and no isolation structure is formed between the control gates and between the floating gates.