Patent ID: 6393549
Filing Date: 2002-05-21
Classification: G06F

Abstract:
An instruction alignment unit for routing a plurality of variable byte-length instructions in a processor from a stored line in a buffer to a plurality of issue positions, said instruction alignment unit comprising:a first multiplexer channel configured to route during a given clock cycle a first instruction having a corresponding start byte within a first range of byte locations of said stored line in said buffer to a first issue position, wherein said first issue position is formed by a first dedicated instruction decoder and a first dedicated execution unit; and a second multiplexer channel configured to route during a subsequent clock cycle a portion of a second instruction having a corresponding start byte within a second range of byte locations of said stored line in said buffer to said first issue position, wherein a remainder of said second instruction is contained in a next stored line in said buffer, wherein said remainder of said second instruction is routed to said first issue position to be merged with said portion of said second instruction.