Patent ID: 8259526
Filing Date: 2012-09-04
Classification: G11C

Abstract:
1. A semiconductor device having a first transfer circuit, the first transfer circuit comprising: first to third nodes; a first pipeline circuit including an input node, an output node and a predefined number of delay circuits respectively controlled by a synchronization signal; a second pipeline circuit including an input node, an output node and a larger number of delay circuits than the number of the delay circuits in the first pipeline circuit; and first to fourth switches controlled based on first to fourth control signals, respectively, wherein the first and second nodes receive first and second data, respectively in parallel, the first switch is connected between the first node and the input node of the first pipeline circuit, the second switch is connected between the second node and the input node of the first pipeline circuit, the third switch is connected between the first node and the input node of the second pipeline circuit, the fourth switch is connected between the second node and the input node of the second pipeline circuit, each of the output terminals of the first and second pipeline circuits is connected to the third node, in a first operation mode, either the first and fourth control signals or the second and third control signals are activated by a first address signal, whereby the first and second data are sequentially output to the third node as serial data via the first and second pipeline circuits corresponding thereto, respectively and in a second operation mode, one of the first and second control signals is activated by the first address signal and the third and fourth control signals are fixed to an inactive state, whereby one of the first and second data is output to the third node via the first pipeline circuit.