Patent ID: 8476932
Filing Date: 2013-07-02
Classification: G09G

Abstract:
1. A multiplex gate driving circuit, comprising: m shift registers for receiving a clock signal and sequentially generating m master signals; and n driving stages for respectively receiving n slave signals and sequentially generating n gate driving signals, wherein a duty cycle of each slave signal is equal to 1/n; wherein the m master signals are non-overlapped positive pulses with a first width, and an x-th shift register of the m shift registers generates an x-th master signal, a phase difference between every two adjacent slave signals is equal to 360/n degrees, and each of the n slave signals includes plural positive pulses; wherein an i-th driving stage of the n driving stages comprises an n-type transistor and a p-type transistor, the n-type transistor has a control terminal receiving an i-th slave signal of the n slave signals, a first terminal receiving the x-th master signal and a second terminal generating an i-th gate driving signal of the n gate driving signals, the p-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the n-type transistor and a second terminal receiving an inverted power-off control signal.