Patent ID: 8334560
Filing Date: 2012-12-18
Classification: H01L

Abstract:
1. An apparatus, comprising: a semiconductor substrate; at least one floating gate structure having vertical sidewalls and comprising: a first symmetric vertical sidewall dielectric disposed over a source side sidewall and a drain side sidewall of the vertical sidewalk of the at least one floating gate structure; a second asymmetric vertical sidewall dielectric disposed over the first symmetric vertical sidewall dielectric over the drain side sidewalk but not the source side sidewall of the floating gate structure; an erase gate disposed adjacent the source side sidewall; and a select gate disposed adjacent the drain side sidewall; wherein the erase gate is spaced from the source side sidewall by the first symmetric vertical sidewall dielectric and a tunnel oxide layer overlying the source side sidewall, and the select gate is spaced from the drain side sidewall by the second asymmetric vertical sidewall dielectric and the first symmetric vertical sidewall dielectric and not by the tunnel oxide layer.