Patent ID: 6324102
Filing Date: 2001-11-27
Classification: G11C

Abstract:
In an FPGA, a radiation tolerant flash memory cell switch including:a programming transistor switch coupled between two circuit nodes to be selectively connected to one another, said programming transistor switch having a gate;a floating gate flash memory switch control circuit having a switch-control node coupled to the gate of said programming transistor switch;a sense transistor having a source coupled to said switch-control node, a gate coupled to a word line and a source coupled to a bit line;an addressing circuit coupled to said word line and said bit line to periodically address said sense transistor;a sensing circuit coupled to said bit line, said sensing circuit having a first current trip point and a second current trip point lower than said first current trip point;charge-leakage sensing logic coupled to said sensing circuit and configured to generate a charge-leakage threshold signal when said sense transistor is addressed and said second trip point has been reached but said first trip point has been reached; andFPGA programming circuitry coupled to said floating gate flash memory switch control circuit to reprogram said FPGA in response to said charge-leakage threshold signal.