Patent ID: 6999367
Filing Date: 2006-02-14
Classification: G11C

Abstract:
1. A semiconductor memory device including dummy memory cells, comprising: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells, each disposed at an intersection between one of the plurality of word lines and one of the plurality of bit line pairs; a dummy word line; a dummy bit line pair; a first dummy memory cell disposed at an intersection between the dummy word line and the dummy bit line pair; a plurality of second dummy memory cells, each disposed at an intersection between the dummy word line and one of the plurality of bit line pairs; a plurality of third dummy memory cells, each disposed at an intersection between one of the plurality of word lines and the dummy bit line pair; a plurality of bit line precharge circuits, each corresponding to the dummy bit line pair or one of the plurality of bit line pairs for controlling a precharge state of the respective line pair; at least one write amplifier for driving the dummy bit line pair and one of the plurality of bit line pairs to write data in a selected memory cell and the first dummy cell; and a write completion detection circuit for generating a write completion signal based on a change in a state of a storing node included in the first dummy memory cell.