Patent ID: 6175159
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having a first surface and a second surface opposed to the first surface, said substrate further having an elongate opening defined therethrough from the first surface to the second surface;a plurality of connecting patterns located on the second surface of said substrate, each of the plurality of connecting patterns having a first end;a semiconductor chip having a surface which is mounted to the first surface of the substrate;a plurality of electrodes located on the surface of said semiconductor chip and aligned with said elongate opening of said substrate;a plurality of wires extending within the elongate opening of said substrate and respectively electrically connecting said plurality of electrodes to corresponding ones of said plurality of patterns; anda resin which covers said plurality of electrodes, said plurality of wires, and the first ends of said plurality of connecting patterns;wherein an outer periphery of said substrate is aligned with an outer periphery of said semiconductor chip to define a chip size package.