Patent ID: 6555869
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A non-volatile memory device, comprising:gate insulating films formed on a semiconductor substrate and spaced apart from each other; a tunnel insulating film formed on the semiconductor substrate and interposed between the adjacent gate insulating films; a memory transistor gate formed on the tunnel insulating film and the gate insulating film interposing the tunnel insulating film therebetween; a select transistor gate formed on the gate insulating film spaced apart from the memory transistor gate; a first doped region formed in a portion of the semiconductor substrate under the memory transistor gate and extending to overlap one end of the select transistor gate; a second doped region formed in a portion of the semiconductor substrate spaced apart from the first doped region and overlapping one end of the memory transistor opposite to the select transistor gate; and a third doped region formed in a portion of the semiconductor substrate spaced apart from the first doped region and overlapping the other end of the select transistor gate, wherein the second doped region has an nâˆ’ type low-density doped region and an n+ type high-density doped region, and is a lightly doped drain (LDD) structure shallower in depth than the first and third doped regions.