Patent ID: 9093466
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a gate structure on a semiconductor layer in a semiconductor substrate; forming a pair of first trenches having a first depth around said gate structure in said semiconductor layer; forming disposable spacers on sidewalls of said gate structure to cover proximal portions of said first trenches; forming a pair of second trenches to a second depth greater than the first depth by recessing portions of said pair of first trenches that are not covered by said gate structure and said disposable spacers; removing said disposable spacers, wherein a pair of horizontal-step-including trenches are formed around said gate structure; forming integrated epitaxial diffusion regions by depositing a semiconductor material on surfaces of said semiconductor layer exposed by said pair of horizontal-step-including trenches, wherein portions of said integrated epitaxial diffusion regions protrude above a bottommost surface of said gate structure and laterally contact portions of said sidewalls of said gate structure; forming a planarization dielectric layer over said integrated epitaxial diffusion regions, said planarization dielectric layer laterally contacting remaining portions of said sidewalls of said gate structure; removing said gate structure to form a gate cavity; laterally expanding said gate cavity by removing exposed portions of said integrated epitaxial diffusion regions and said planarization dielectric layer; and filling said laterally expanded gate cavity with a replacement gate structure.