Patent ID: 6828835
Filing Date: 2004-12-07
Classification: H03L,Y10S

Abstract:
A delay locked loop (DLL) circuit, comprising:a clock buffer for receiving an external clock signal, temporarily storing the external clock signal and outputting a buffered clock signal; a first frequency divider for receiving the buffered clock signal and generating a divided clock signal by dividing the buffered clock signal according to a dividing control signal; a phase detector for receiving the divided clock signal from the first frequency divider and a compensation clock signal, detecting phase delay of two signals, generating a first comparison signal and a second comparison signal and generating a sample clock signal in order to perform sampling of the second comparison signal; a DLL controller for receiving and analyzing the sample clock signal and the second comparison signal from the phase detector, and outputting the dividing control signal as a second logic level when an analyzing result is an high speed operation or outputting the dividing control signal as a first logic level when an analyzing result is low speed operation; a delay line for receiving the buffered clock signal from the clock buffer and the first comparison signal and the second comparison signal from the phase detector, performing shifting of the external clock signal to the left or right according to the first comparison signal and the second comparison signal, and outputting an internal clock signal; a second frequency divider for receiving the internal clock signal from the delay line and generating a divided internal signal by dividing the internal clock signal according to the dividing control signal; and a replica unit for receiving the divided internal signal from the second frequency divider, compensating the time delay between the external clock signal the internal clock signal and generating the compensation clock signal.