Patent ID: 8270218
Filing Date: 2012-09-18
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell formed on a well region in a semiconductor substrate and having a stacked gate including a charge accumulation layer and a control gate, the memory cell being configured to hold data of at least two levels; a bit line electrically connected to a drain of the memory cell and transferring data; a source line electrically connected to a source of the memory cell; and a sense amplifier which, during erase verification to determine whether or not a threshold voltage of the memory cell in an erased state is at a threshold level, reads the data from the memory cell and senses the data with a first voltage applied to the control gate of the memory cell, with a positive second voltage higher than the first voltage applied to the well region and the source line, and with a third voltage higher than the second voltage applied to the bit line.