Patent ID: 6696829
Filing Date: 2004-02-24
Classification: H03K,H03L

Abstract:
An integrated circuit device comprising:a phase-locked loop (PLL) circuit to generate an output clock signal having a first frequency in a first operating mode and a second frequency in a second operating mode, the second frequency being determined, at least in part, by a reference clock signal; and a control circuit to output a select signal to the PLL circuit to select either the first operating mode or the second operating mode, wherein the PLL circuit includes, an oscillation circuit; and a select circuit, coupled to the oscillation circuit and the control circuit, the select circuit being responsive to the select signal to select either a fixed-level control signal or a reference-clock-dependent control signal to be output as a selected control signal to the oscillation circuit, the oscillation circuit being responsive to the selected control signal to oscillate at either the first frequency or the second frequency to generate the output clock signal.