Patent ID: 6188640
Filing Date: 2001-02-13
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first output control circuit for receiving a command synchronized with a first input internal clock signal and generating a first output control signal based on the command;a second output control circuit for receiving the command synchronized with a second input internal clock signal having a phase differing from that of the first input internal clock signal and generating a second output control signal based on the command;an output clock generating circuit connected to the first and second output control circuits, wherein the output clock generating circuit receives either the first output control signal or the second output control signal, a first output internal clock signal, and a second output internal clock signal, the first and second output internal clock signals having phases that are advanced from those of the first and second input internal clock signals, and generates a first output clock signal and a second output clock signal delayed from the first output clock signal; andan output buffer connected to the output clock generating circuit, wherein the output buffer receives a first data signal and a second data signal and outputs the first and second data signals in accordance with the first and second output clock signals.