Patent ID: 6559033
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A process for forming an integrated circuit structure on a semiconductor substrate and characterized by reduced horizontal capacitance between closely spaced apart metal lines which comprises:a) forming, on an oxide layer of an integrated circuit structure on a semiconductor substrate, closely spaced apart metal lines with protective caps thereon, said protective caps comprising a material selected from the group consisting of standard k silicon oxide, silicon carbide, and a metal; b) depositing low k silicon oxide dielectric material between said closely spaced apart metal lines and over said protective caps on said metal lines; c) planarizing said low k silicon oxide dielectric material down to the level of a top surface of said protective caps; and d) depositing a layer of standard k silicon oxide over said planarized low k silicon oxide dielectric and said protective caps; including the further step of forming a planarizing layer of standard k dielectric material over said low k silicon oxide dielectric material prior to said planarizing step.