Patent ID: 6378098
Filing Date: 2002-04-23
Classification: G01R

Abstract:
A semiconductor test system for testing a semiconductor device (DUT) having a phase lock loop (PLL) circuit therein by supplying test pattern data divided into a large number of test pattern blocks, comprising:a first clock and waveform generator for supplying a clock signal to the PLL circuit in the DUT through a clock pin of the DUT at a start of the first test pattern block; a second clock and waveform generator for supplying pattern data to a data pin of the DUT during each of the test pattern blocks; a pattern generator for generating test pattern data which is supplied to the second clock and waveform generator based on a test program; and a timing generator for generating a tester rate signal which defines each test cycle in the test system, a clear signal for resetting the data in the first and second clock and waveform generators, and a gate signal for controlling the tester rate signal and the clear signal in the first and second clock and waveform generators; wherein the clock signal is continuously provided to the PLL circuit in the DUT from a predetermined time prior to the start of the first test pattern block until the end of the last test pattern block while the test pattern data to the data pin is reset between the end of one test pattern block and the start of the next test pattern block, thereby continuously maintaining the PLL circuit in the DUT in a phase lock state throughout application of all of the test pattern blocks to the DUT.