Patent ID: 7383403
Filing Date: 2008-06-03
Classification: G06F

Abstract:
1. A processor comprising: a plurality of instruction buffers, wherein each of the plurality of instruction buffers is configured to store instructions fetched from a respective thread of a plurality of threads; an instruction cache coupled to supply instructions to the plurality of instruction buffers; and a cache miss unit coupled to the instruction cache and configured to monitor cache misses in the instruction cache, and wherein the cache miss unit is configured to detect which of the plurality of threads experience a cache miss to a cache line, and wherein the cache miss unit is configured to concurrently cause at least one instruction from the cache line to be stored in each of the plurality of instruction buffers that corresponds to one of the plurality of threads which experienced the cache miss to the cache line responsive to a return of the cache line for storage in the instruction cache, and wherein, if a first thread of the plurality of threads experiences a cache miss to the cache line and the first thread is redirected prior to the return of the cache line for storage in the instruction cache, the cache miss unit is configured to inhibit causing storage of instructions from the cache line in a first instruction buffer of the plurality of instruction buffers that corresponds to the first thread, and wherein the cache miss unit is configured to maintain a plurality of indications corresponding to the cache miss to the cache line, each of the plurality of indications corresponding to a respective thread of the plurality of threads and indicating whether or not the respective thread experiences the cache miss, and wherein the cache miss unit is configured to place a first indication of the plurality of indications in a first state indicating the cache miss responsive to a first thread of the plurality of threads experiencing the cache miss, wherein the first indication corresponds to the first thread, and wherein the cache miss unit is configured to place the first indication in a second state indicating no cache miss responsive to receiving an indication that the first thread is redirected.