Patent ID: 6674304
Filing Date: 2004-01-06
Classification: H03K

Abstract:
An output buffer circuit comprising:a first voltage driver having an output coupled to a pad, the first voltage driver being coupled to receive a first power supply voltage and being coupled to drive the pad to a first voltage that is approximately the first power supply voltage depending upon a data signal and a first output enable signal; a second voltage driver having an output coupled to the pad, the second voltage driver being coupled to receive a second power supply voltage and being coupled to drive the pad to a second voltage that is approximately the second power supply voltage depending upon the data signal and the first output enable signal, the first power supply voltage and the second power supply voltage being different; and wherein the second voltage driver is coupled to drive the pad for a first time period until the second voltage is obtained on the pad, at which time the first voltage driver is used to drive the pad from the second voltage to the first voltage.