Patent ID: 6801053
Filing Date: 2004-10-05
Classification: H03K

Abstract:
A level-shifting circuit, comprising:a first PMOS transistor having a first gate, a first drain, and a first source coupled to a first voltage VDD; a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate, and a second source coupled to the first voltage VDD; a first inverse logic gate having an output terminal and coupled to the first drain; a second inverse logic gate having an inverse output terminal and coupled to the second drain; a first NMOS transistor having a third gate coupled to the first voltage VDD, a third drain coupled to the first drain, and a third source coupled to an inverse input terminal; and a second NMOS transistor having a fourth gate coupled to the first voltage VDD, a fourth drain coupled to the second drain, and a fourth source coupled to an input terminal.