Patent ID: 8520076
Filing Date: 2013-08-27
Classification: G09G

Abstract:
1. A liquid crystal display comprising: a liquid crystal display panel on which liquid crystal cells connected to thin film transistors (TFTs) located at crossings between gate lines and data lines are formed; a data driver that drives the data lines of the liquid crystal display panel; and a gate driver that includes a sequence of first to nth stages of shift registers configured to supply scan signals to first to nth gate lines GL wherein, in the test mode, the first to nth stages generate the test scan signals having a low logic level for turning off the TFTs when a faulty stage is not included in the first to nth stages, and the faulty stage to the nth stage generate the test scan signals having a high logic level for turning on the TFTs when at least one of the faulty stage is included in the first to nth stages, wherein, in the test mode, the first stage of the sequence of first to nth stages of the shift registers outputs the test scan signal to the first gate line in response to a start pulse having a low logic level and a clock signal supplied from test pads located in a peripheral region of the liquid crystal display panel, and the second to nth stages of the shift registers output the test scan signal, to the second to nth gate lines in response to output signals of the previous stages of the shift registers and clock signals, and wherein, in the test mode, a black or white image regardless of a pixel data signal supplied to the data line is displayed in a region of the liquid crystal display panel corresponding to the first stage to the stage previous to the faulty stage in the sequence of stages when a faulty stage is not included in the first to nth stages.