Patent ID: 6670838
Filing Date: 2003-12-30
Classification: H03K

Abstract:
A system to receive an input clock CLKIN of nominal 50% duty cycle and to output a substantially 50% duty cycle signal CLK, the circuit comprising:a duty cycle adjustor unit coupled to receive as input said input clock CLKIN and a control signal VC, and to output said signal CLK whose duty cycle is variable as a function of magnitude of said control signal VC; means for converting said signal CLK to a differential signal pair CLK and CLKB, said means for converting coupled to receive as input said signal CLK from said duty cycle adjustor unit, and coupled to output said signal pair CLK and CLKB; means for extracting DC components VCLK and VCLKB respectively from said signal pair CLK and CLKB, said means for extracting coupled to receive as input said signal pair CLK and CLKB and to output said DC components VCLK and VCLKB; means for comparing said DC components VCLK and VCLKB and outputting said control signal VC proportional to a difference therebetween, wherein said means for comparing receives as input said DC components VCLK and VCLKB and outputs said control signal VC, said control signal VC being fedback to said duty cycle adjustor; wherein duty cycle of said signal pair CLK and CLKB is dynamically maintained at substantially 50%.