Patent ID: 8745567
Filing Date: 2014-06-03
Classification: G06F

Abstract:
1. A method implemented in a computing system for analyzing register-transfer-level structures of a pre-floorplan integrated circuit design to predict routing congestion, comprising: receiving, using a computer, a hardware description of at least a portion of the circuit design; performing, using the computer, a logical congestion metric analysis of the received circuit design to obtain one or more congestion-predicting metric values therefrom, the logical congestion metric analysis including deriving multiple raw metrics from the hardware description and computing one or more derived metrics from the set of raw metrics; accessing by the computer, according to the obtained one or more metric values, a knowledge base containing a statistically sufficient set of empirical routing congestion results for multiple circuit designs in at least one process technology, the accessing of the knowledge base thereby obtaining congestion results for a circuit design of the same processing technology determined to have the closest metric values to the one or more obtained metric values; and reporting, by the computer, the obtained congestion results for the analyzed circuit design.