Patent ID: 6842397
Filing Date: 2005-01-11
Classification: G11C

Abstract:
1. A semiconductor device, comprising: a memory cell array having memory cells arranged in rows and columns, said memory cells storing data and being selected according to address signals; control section configured to receive a clock signal and a control signal, and configured to output a plurality of said data in synchronism with said clock signal after said control signal is asserted, output of said data beginning a number of clock cycles (latency N) of said clock signal (latency N being a positive integer≧2) after said control signal is asserted, a different one of said data being output at each of said clock cycles after said output begins until said plurality of data is output; and latency setting circuit configured to set the latency N, said latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.