Patent ID: 6184105
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of fabricating an integrated circuit in which field effect transistors (FETs) having a source, drain and gate are in and on a silicon substrate comprising the sequential steps of:forming a pair of FETs in and on a silicon substrate and the pair of FETs having a source region of one FET connected to a drain region of the other FET in the silicon substrate and each having a gate above the silicon substrate surface;forming a trench opening in the silicon substrate between the gates of said FETs and in the connected source and drain regions of the FETs to separate the source region of one FET from the drain region of the other FET;filling said trench opening in the silicon substrate to form an insulating trench by depositing insulation in and above the trench opening to a height above the gate so that the insulation is sufficiently thick to serve as the insulating layer for local interconnects to the source, drain and gate; andplanarizing the surface of the deposited insulation prior to forming the local interconnects.