Patent ID: 6477100
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of sense amplifiers for amplifying signals read out of a plurality of memory cells onto a plurality of data lines; a plurality of first MISFETs so arranged that a first potential associated with a high level of an amplification signal for said plurality of sense amplifiers is supplied from a first meshed power line structure, each of said plurality of first MISFETs being disposed for a predetermined number of said plurality of sense amplifiers; and a plurality of second MISFETs so arranged that a second potential associated with a low level of an amplification signal for said plurality of sense amplifiers is supplied from a second meshed power line structure, each of said plurality of second MISFETs being disposed for a predetermined number of said plurality of sense amplifiers; wherein said plurality of first and second MISFETs are of the same conduction type, and each of said first and second MISFETs has a common drive control signal line; said drive control signal line transmits a signal for controlling the conduction state of said plurality of said first and second MISFETs; and an absolute value of the difference between an effective level and an ineffective level of said signal for controlling the conduction state of said plurality of said first and second MISFETs is larger than an absolute value of the difference between said first potential and said second potential.