Patent ID: 7216324
Filing Date: 2007-05-08
Classification: G06F,H01L

Abstract:
1. A method for completing a flip chip package design, the method comprising: analyzing one or more input/out bump locations of a chip; analyzing one or more solder ball locations of a package hosting the chip with regard to a predetermined printed circuit board; assigning an optimized connection relation between the input/output bump locations to the solder ball locations; and designing the package hosting the chip by using a tool library containing one or more existing mask designs for re-use, wherein the tool library is searchable by design parameters including chip size, package size, and bump pitch, and wherein when one or more existing mask designs are used for the package, at least one custom connection layer of the package is redesigned when needed for connecting the chip to the printed circuit board without producing a full set of new masks for the package.