Patent ID: 7445985
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit, the method comprising: forming trench capacitors arranged in cell rows and oriented in each case to hole trenches in a semiconductor substrate; introducing trench insulator structures between the cell rows, wherein semiconductor fins of fin field-effect transistors are formed from the semiconductor substrate between in each case two trench capacitors that are adjacent in a cell row; providing a mask comprising mask sections, wherein each mask section is aligned to one of the hole trenches, such that first trench insulator structures sections which adjoin the hole trenches are covered by the mask sections and second trench insulator structures sections which adjoin central portions of the semiconductor fins are not covered by the mask sections; introducing gate trenches into the trench insulator structures using the mask to form second insulator structures, wherein each second insulator structure emerges from one of the first insulator structure sections.