Patent ID: 7415661
Filing Date: 2008-08-19
Classification: H04L

Abstract:
1. A PHY processor of a node of a wireless network to wirelessly receive packets that exactly or substantially conform to a wireless network standard, each packet including a preamble followed by a modulated part that includes a header, the header including, in the case that the packet exactly conforms to the standard, bits having respective correct values, including one or more reserved bits set to respective known values and specified bits set to one of a plurality of expected combinations, the receiving node including a MAC processor having an input coupled to the output of the PHY processor, the PHY processor comprising: an SOP detector to provide a start-of-packet (SOP) trigger that indicates that a packet may have been received; a receive signal processor to process modulated packet data and provide the processed data to the MAC processor; and a receive controller coupled to the SOP detector and the receive signal processor, the receive controller configured to: such that the checking indicating that the checked bits do not have their respective correct values indicates that the SOP trigger is a false SOP trigger.