Patent ID: 6744684
Filing Date: 2004-06-01
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array including a plurality of memory cells arranged in a matrix; a refresh timer circuit providing a refresh request signal at a time interval required to refresh data held by said plurality of memory cells; a command generation circuit generating an internal command signal in response to an access command; and a row selection control circuit carrying out an operation associated with row selection of said memory array, said row selection control circuit including: a timing control circuit rendered active in response to said internal command signal to output a timing signal of a row selection operation of said memory cell; a refresh control circuit receiving and holding said refresh request signal to output an internal refresh command signal when said timing control circuit attains an inactive state; and a refresh timing control circuit rendered active in response to said internal refresh command signal to output said timing signal instead of said timing control circuit; and a row selection circuit carrying out row selection of said memory cell in response to said timing signal.