Patent ID: 8318547
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A method of packaging an integrated circuit in a packaging structure, the method comprising: thinning a first lead in a lead frame to a first thickness that is thinner than an initial thickness of the lead frame, the lead frame including a first die paddle and a second die paddle; thinning at least a portion of the second die paddle to a second thickness thinner than the initial thickness of the lead frame; mounting a first component on the first die paddle and a second component on at least the portion of the second die paddle, wherein the second component comprises a vertical cavity surface emitting laser (VCSEL); coupling the first component with the second component through an interconnect configured to route electrical signals between the first component and the second component; and forming an electrically insulating packaging material over the lead frame and the interconnect such that: