Patent ID: 7851289
Filing Date: 2010-12-14
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising the steps of: forming a semiconductor substrate in such a manner that a strain effect silicon layer having a strain effect is formed in an upper layer of said semiconductor substrate, a relax layer is formed below the strain effect silicon layer, and a buffer layer below the relax layer; forming a gate electrode of a p-channel type field effect transistor and a gate electrode of a-n channel type field effect transistor on said strain effect silicon layer through a gate insulating film; forming a source and a drain each composed of p-type diffusion layer in only said strain effect silicon layer on both sides of said gate electrode of said p-channel type field effect transistor, wherein the source and drain of the p-type diffusion layers is formed to a depth of less than a depth of the strain effect silicon layer; forming a source and a drain each composed of n-type diffusion layers in only said strain effect silicon layer on both sides of said gate electrode of said n-channel type field effect transistor, wherein the source and drain of the n-type diffusion layers is formed to a depth of less than a depth of the strain effect silicon layer; forming silicon epitaxial layers on the source and on the drain composed of the p-type diffusion layers and the n-type diffusion layers; forming refractory metal silicide layers on the silicon epitaxial layers; forming a isolation region in between the p-channel type field effect transistor and the n-channel type field effect transistor in said strain effect silicon layer; and wherein the buffer layer is constructed of a P