Patent ID: 6146940
Filing Date: 2000-11-14
Classification: H01L

Abstract:
A method of fabricating a dynamic random access memory, comprising:providing a substrate with at least one active region, and at least one field oxide area formed thereon and adjacent to the active region;forming a gate oxide layer on the active region;depositing a polysilicon layer on the active region;forming a cap oxide layer on the polysilicon layer;patterning the cap oxide layers polysilicon layer and gate electrode layer to form a gate electrode structure of a MOS transistor;forming sidewall spacers on sidewalls of the gate electrode structure;performing a self-aligned ion implantation process in the substrate to form a plurality of source/drain regions;forming a photoresist layer on the substrate, covering one of the source/drain regions of the MOS transistor and covering a part of the cap oxide layer of the gate electrode structure;after said forming a photoresist layer, selectively forming an oxide layer on an exposed part of the gate electrode structure and on the substrate using liquid phase deposition; andremoving the photoresist layer to expose the one of the source/drain regions, thereby forming a contact window over the one of the source/drain regions, wherein said forming a photoresist layer, said selectively forming and said removing prevents the oxide layer from forming within the contact window, and wherein said forming a photoresist layer, said selectively forming and said removing are performed without etching the cap oxide layer.