Patent ID: 6821845
Filing Date: 2004-11-23
Classification: C23C,H01L

Abstract:
A method of manufacturing a semiconductor device having a dielectric capacitor including a bottom electrode, a dielectric layer and a top electrode on an underlying substrate having a three-dimensional structure, comprising:providing a substrate having an insulation layer provided thereon, the insulation layer having a hole formed therein; forming a bottom electrode on at least a side wall of the insulation layer in the hole; providing a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer; wherein the bottom electrode and the top electrode are formed by a metalorganic chemical vapor deposition process at 180Â° C. or higher and 250Â° C. or lower using a cyclopentadienyl ruthenium complex as a precursor and a reaction gas selected from the group consisting of O2, H2, N2O, O3, CO and CO2, where a volume ratio of the reaction gas to a carrier gas is 1% or more.