Patent ID: 8772118
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A process of integrated circuit manufacturing comprising: providing a first gate stack and a second gate stack over a substrate; forming a spacer on the sidewalls of the first gate stack and the second gate stack to provide a first horizontal offset over a first channel region under the first gate stack; performing a PLDD implant adjacent the first gate stack having the first horizontal offset provided by said spacer; after performing the PLDD implant, depositing a seal substance over the spacer, the first gate stack and the second gate stack to provide a screen thickness vertically while thereby augmenting the spacer on the second gate stack to provide a second, increased, offset horizontally from the second gate stack; and subsequently providing an NLDD implant dose for NLDD formation using the unetched seal substance as a horizontal screen.