Patent ID: 6292392
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A non-volatile memory device comprising:a plurality of memory cell arrays, each memory cell array including a plurality of blocks, each block comprising a matrix of memory cells coupled to one another via word lines and bit lines such that corresponding ones of the word lines in the plurality of blocks of each memory cell array are coupled to a common, the word lines being commonly driven by decoders respectively provided for the memory cell arrays, where all data stored in each block is subject to erasure in one erase operation, the non-volatile memory device further comprising:a plurality of sense amplifiers for reading data from the memory cells; anda control circuit for simultaneously performing a plurality of operations by using the plurality of sense amplifiers,wherein the sense amplifiers enable the memory device to simultaneously perform any combination of a plurality of the following: a read operation, a write operation including a verification, and an erase operation including a verification.