Patent ID: 7436720
Filing Date: 2008-10-14
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first pair of bit lines including a non-inverted bit line and an inverted bit line that can be selected by a row address in a first range; a second pair of bit lines including a non-inverted bit line and an inverted bit line that can be selected by a row address in a second range that is not overlapping the first range; a sense amplifier provided to be common to the first pair of bit lines and the second pair of bit lines; and an address-data-topology correcting unit supplying write data and outputting read data to/from the first pair of bit lines without inverting and supplying write data and outputting read data to/from the second pair of bit lines with inverting, wherein a positional relationship between the non-inverted bit line and the inverted bit line in the first pair of bit lines is opposite to a positional relationship between the non-inverted bit line and the inverted bit line in the second pair of bit lines.