Patent ID: 9178000
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A resistive random access memory (ReRAM) cell comprising: a first conductive layer; a second conductive layer; and a variable resistance layer; wherein the first conductive layer and the second conductive layer are operable as electrodes of the ReRAM cell, wherein the variable resistance layer is disposed between the first conductive layer and the second conductive layer; wherein the first conductive layer comprises doped silicon; and the first conductive layer being operable as an electrode of at least one other device, wherein the first conductive layer is operable as a source or a drain region of a field effect transistor (FET) configured to control a flow of an electrical current through the ReRAM cell, and wherein the FET is one of the two other devices, and wherein a thickness of the variable resistance layer is substantially the same as a thickness of a gate dielectric of the FET, wherein the first conductive layer is operable as a bottom electrode of one or more additional devices different from the FET, wherein the one or more additional devices comprise at least one of a pinched resistor, a bipolar junction transistor, a junction gate field-effect transistor, a silicon on insulator device, a fully depleted silicon on insulator device, a self-aligned double-gate MOSFET (FinFET) device, a diode, or an additional ReRAM cell.