Patent ID: 7764555
Filing Date: 2010-07-27
Classification: G11C

Abstract:
1. A leakage testing method for a dynamic random access memory having a recess gate adapted for applying for a memory array, wherein the memory array comprises a plurality of memory cells, sequentially and parallel arranged word lines, and a plurality of sequentially and parallel arranged bit lines, the word lines are substantially perpendicular with the bit lines, the bit lines include a first bit line and a second bit line, the first bit line and the second bit line are connected with a first memory cell and a second memory cell of the plurality of memory cells, respectively, the first memory cell and the second memory cell comprise a first storage unit and a second storage unit, respectively, each first storage unit and each second storage unit are at a first storage status and a second storage status, respectively, a storage electrical potential of the first storage status is lower than a storage electrical potential of the second storage status, the word lines comprises a first word line, a second word line, a third word line, and a fourth word line, the first word line and the second word line are extending between the first storage unit and the second storage unit of the first memory cell, the third word line and the fourth word line are extending between the first storage unit and the second storage unit of the second memory cell, and the second storage unit of the first memory cell is adjacent to the first storage unit of the second memory cell, the leakage testing method comprising: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; disturbing one of the word lines extending through each of the memory cells; and determining whether the DRAM is acceptable or not, wherein when another one of the word lines extending through each of the memory cells is caused with a reading error by disturbing the one of the word lines extending through each of the memory cells, a failure is determined as occurred, and the failure is attributed to a leakage type of extended depletion region, and when the another one of the word lines extending through each of the memory cells is not caused with a reading error by disturbing the one of the word lines extending through each of the memory cells, the DRAM is determined as acceptable.