Patent ID: 7289592
Filing Date: 2007-10-30
Classification: H03K

Abstract:
1. An apparatus for multiple-divisor prescaler, comprising: an odd/even core divider, having an input clock and generating an divider output; an n-order divided-by-2 divider with changeable trigger edge, further including a cascade of n divided-by-2 dividers, called first-order, second-order, . . . , nth-order divided-by-2 divider, respectively, each said order divider receiving an output signal from previous said order divider, and generating an output signal, n being greater than 1; a divisor control logic unit, for receiving an input divisor instruction, generating a signal to each said order divided-by-2 divider of said n-order divided-by-2 divider with changeable trigger edge requiring changing trigger edge, and generating a plurality of auxiliary signals; and an odd number inserted mechanism, for receiving two or more auxiliary signals, and performing combinational logic operation with said output signals from each said order divided-by-2 divider to determine a time slot for division by odd number and provide to said odd/even core divider.