Patent ID: 6232641
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed, comprising:a silicon substrate;a gate electrode formed on the surface of the silicon substrate through an insulating film;an elevated source film and an elevated drain film formed in a source region and a drain region of the surface of the silicon substrate and each having at least a surface made of a metal silicide film and conductivity such that the elevated source film and the elevated drain film are elevated over the surface of the silicon substrate and the MOS transistor having a structure that the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate owning to the formation of the elevated source film and the elevated drain film;a first gate-side-wall insulating film formed on the side wall of a gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate; anda second gate-side-wall insulating film formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film, made of a material which can be etched at an etching rate lower than that permitted for a material of the first gate-side-wall insulating film and having the portion which is formed on the bottom surface of the first gate-side-wall insulating film and which exists in an inner bottom surface portion adjacent to the gate electrode.