Patent ID: 6069030
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method for fabricating a CMOSFET, comprising the steps of:forming a semiconductor layer on an insulating substrate;selectively patterning the semiconductor layer to form first and second semiconductor layers having first and second trenches, respectively, opposite to each other and spaced apart from each other by a predetermined distance;selectively implanting first conductivity type impurity ions into the first semiconductor layer;selectively implanting second conductivity type impurity ions into the second semiconductor layer;forming a gate insulating layer on the entire surfaces of the first and second semiconductor layers;forming a gate electrode over the insulating substrate from the first trench of the first semiconductor layer to the second trench of the second semiconductor layer;implanting second conductivity type impurity ions into the first semiconductor layer at both sides of the first trench of the first semiconductor layer to a depth equal to the depth of the first trench so as to form a third semiconductor layer of a second conductivity type; andimplanting first conductivity type impurity type into the second semiconductor type at both sides of the second trench of the second semiconductor layer to a depth equal to the depth of the second trench so as to form a fourth semiconductor layer of a first conductivity type.