Patent ID: 8203869
Filing Date: 2012-06-19
Classification: G11C

Abstract:
1. A memory array comprising: a plurality of resistive changing memory cells, each resistive changing memory cell electrically between a source line and a bit line and a transistor electrically coupled to the resistive changing memory cell and the bit line, the transistor having a gate electrically between a source region and a drain region and the source region being electrically between the resistive changing memory cell and the gate, a word line is electrically coupled to the gate; wherein the resistive changing memory cells comprise spin-transfer torque memory cells; and a plurality of high resistance state resistive changing memory cells, each high resistance state resistive changing memory cell is electrically coupled to a high resistance state transistor, and the high resistance state transistor is electrically coupled to a reference voltage word line; and a plurality of low resistance state resistive changing memory cells, each low resistance state resistive changing memory cell is electrically connected to a low resistance state transistor, and the low resistance state transistor is electrically coupled to the reference voltage word line; wherein one high resistance state resistive changing memory cell and one low resistance state resistive changing memory cell provide an average voltage reference value when a read operation is applied across a selected resistive changing memory cell along a same word line row connecting the transistor, the high resistance state transistor, and the low resistance state transistor.