Patent ID: 6640309
Filing Date: 2003-10-28
Classification: G11C

Abstract:
A computer system, comprising:a processor for executing instructions; a memory module for storing instructions and data, wherein the memory module comprises a plurality of memory devices coupled to a clock buffer; a memory controller coupled between the processor and the memory module, wherein the memory controller is configured to provide a differential clock signal and to produce memory access signals; a fanout buffer coupled to receive the differential clock signal from the memory controller, wherein the fanout buffer includes at least one differential-pair amplifier for receiving the differential clock signal and at least one ECL (emitter coupled logic) amplifier pair for providing the differential signal to the clock buffer at ECL signal levels; wherein the clock buffer produces a regenerated clock signal, and wherein the clock buffer comprises: an input buffer circuit coupled to receive the differential clock signal and configured to produce a single-ended clock signal from the differential clock signal; and a phase-locked loop (PLL) for producing the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended clock signal; and wherein each of the plurality of memory devices is coupled to receive the regenerated clock signal, and wherein the operations of the plurality of memory devices are synchronized to the regenerated clock signal.