Patent ID: 7482790
Filing Date: 2009-01-27
Classification: G05F

Abstract:
1. A circuit of an output stage of an LDO voltage regulator, implemented with low-voltage devices and still allowing higher voltage levels is comprising: a first low-voltage PMOS pass device having its source connected to VDD voltage and to its bulk, its gate is controlled by said LDO voltage regulator, its drain is connected to a means of controllable resistance; said means of controllable resistance protecting actively a voltage level at the drain of said PMOS pass device being implemented between the drain of said first PMOS pass device and an output port of the LDO voltage regulator; a first voltage limiting means implemented in parallel to said first PMOS pass device wherein said first voltage limiting means is a serial arrangement of one or more diodes wherein an addition of their individual threshold voltages corresponds to a maximal tolerable voltage level of said pass device; and a second voltage limiting means implemented in parallel to said means of controllable resistance wherein said second voltage limiting means is a serial arrangement of one or more diodes.