Patent ID: 8981813
Filing Date: 2015-03-17
Classification: H03K

Abstract:
1. A data processing device, comprising: an application specific integrated circuit (“ASIC”) configured to perform a specific function in accordance with a first clock domain; a configurable logic circuit (“CLC”) coupled to the ASIC and configured to perform a programmable logic function in accordance with a second clock domain, wherein the CLC is a semiconductor based custom field programmable gate array (“cFPGA”) having a plurality of lookup tables (“LUTs”) and a plurality of nonvolatile programmable bits wherein the cFPGA is an integrated circuit able to be configured to one of user selected logic functions; and a phase adjustment circuit coupled with the CLC, and able to facilitate communication between the ASIC and the CLC in accordance with the first clock domain and the second clock domain, wherein the phase adjustment circuit is configured to detect the first clock domain and the second clock domain and provides a calibration pattern to compensate phase difference to improve reliability of data capture travelling between the ASIC and the CLC in response to the first clock domain and the second clock domain.