Patent ID: 6096610
Filing Date: 2000-08-01
Classification: H01L,H03K

Abstract:
A method for forming a transistor suitable for a high voltage circuit, the method comprising:forming a first diffusion region and a second diffusion region in a substrate of a complementary metal oxide semiconductor (CMOS) integrated circuit, wherein one of the first and second diffusion regions is a source region, the other one of the diffusion regions is a drain region and a channel is defined between the first and second diffusion regions;defining a well implant block region wherein one of the first and second diffusion regions is disposed within the well implant block region and at least a portion of the other one of the first and second diffusion regions is disposed outside of the well implant block region;implanting a well in the substrate outside of the well implant block region;blocking a well implant in the substrate inside the well implant block region; andforming a gate above the channel.