Patent ID: 6381715
Filing Date: 2002-04-30
Classification: G11C

Abstract:
A memory test and initialization circuit for testing and initializing a memory and memory interfaces in a data processing system wherein the memory is logically partitioned into a plurality of memory banks, comprising:(a) a plurality of exerciser testers, one for each of the plurality of memory banks, each of the plurality of exerciser testers comprising: (i) an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, wherein each of the address generators concurrently addresses a different one of the memory banks; (ii) a data pattern generator coupled to a corresponding one of the address generators to receive a data pattern control signal upon an output of each of the memory bank addresses generated by its corresponding one of the address generators, and to output a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal; and (b) a plurality of address initialization registers, one for each of the plurality of exerciser testers, wherein each of the plurality of address initialization registers stores an initial one of the memory bank addresses for one of the memory banks such that each of the address generators is preset to initially address a different one of the memory banks.