Patent ID: 8735975
Filing Date: 2014-05-27
Classification: H01L

Abstract:
1. A back-end-of-line (BEOL) structure for implementing stacked vertical transistors comprising: a pair of stacked vertical field effect transistors (FETs) including a series connected N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET) being formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire; a channel length of each of said pair of stacked vertical FETs being delineated by said polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; said sequential source deposition, channel deposition and drain deposition of said N-channel FET (NFET) including a sequential deposition of an N+ doped polysilicon defining a N source, a P− doped polysilicon defining a N body, and an N+ doped polysilicon defining a N drain; and said sequential source deposition, channel deposition and drain deposition of said P-channel FET (PFET) including a sequential deposition of a P+ doped polysilicon defining a P source, an N− doped polysilicon defining a P body, and a P+ doped polysilicon defining a P drain; an ohmic contact deposited on said NFET N+ doped polysilicon drain deposition; and a wire via being formed defining a gate node of each of said pair of stacked vertical FETs includes forming an etched hole through said source deposition, channel deposition and drain deposition of said NFET and said PFET, and said ohmic contact, and a dielectric layer to a signal wire in the BEOL stack; a thin dielectric deposited in said etched opening, and said thin dielectric removed from a bottom of said etched opening, and a metal deposited in said etched opening.