Patent ID: 8331181
Filing Date: 2012-12-11
Classification: G11C

Abstract:
1. A semiconductor memory circuit, comprising: a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction; a plurality of main bit lines for outputting data of the memory cells; a data reading unit for reading data of at least one of the memory cells selected with the row selecting unit and the column selecting unit; a first multiplexer for connecting at least one of the main bit lines connected to the one of the memory cells to the data reading unit; and a second multiplexer for connecting an adjacent main bit line situated adjacently outside the one of the main bit lines to a charging/discharging voltage source for setting at a specific voltage, wherein said data reading unit includes a first sense amplifier and a second sense amplifier, said row selecting unit being arranged to select a pair of the memory cells connected to a pair of the main bit lines arranged adjacently, said first multiplexer being arranged to connect the pair of the main bit lines to the first sense amplifier and the second sense amplifier, respectively.