Patent ID: 6529083
Filing Date: 2003-03-04
Classification: G06F,H03L,Y10S

Abstract:
A clock control circuit comprising:a PLL oscillator which receives a reference clock from an outside and outputs a PLL output clock based on the reference clock; a detector which outputs a state detection signal indicating stableness or unstableness of the PLL output clock; a clock source selector which receives the reference clock and the PLL output clock and selectively outputs either of the reference clock and the PLL output clock as a basic clock; an output circuit which receives the basic clock, generates an operating clock to be output to the outside based on the basic clock, and controls output of the operating clock to the outside; and a clock state controller which receives the state detection signal and controls said clock source selector and said output circuit based on the state detection signal; wherein, when the state detection signal indicates that the PLL output clock is unstable, said clock state controller controls said output circuit so as to stop the output of the operating clock to the outside and controls said clock source selector so as to select the reference clock as the basic clock; and when the state detection signal indicates that the PLL output clock has become stable, said clock state controller controls said clock source selector so as to switch the basic clock from the reference clock to the PLL output clock and controls said output circuit so as to restart the output of the operating clock to the outside.