Patent ID: 6046930
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A memory array column comprising:(a) a plurality of memory cells, each memory cell comprising a cross coupled memory latch having two high side transistor devices coupled continuously to a supply voltage and two low side transistor devices coupled continuously to ground, and further having a first node and a second node interconnected such that a given charge state on one of the first and second nodes produces an opposite charge state on the other of the first and second nodes;(b) each memory cell having a first independent access port connecting the first node of the respective memory cell to a first bit line;(c) each memory cell having a second independent access port connecting the second node of the respective memory cell to a second bit line;(d) a cell clearing arrangement comprising a clearing transistor having its source-drain conduction path coupling the second bit line to ground for producing a preset condition in each selected memory cell in response to a clear input, each selected memory cell comprising a memory cell selected through the independent second access port associated with the respective cell, and the preset condition comprising a low charge state at the second node and a high charge state at the first node of the selected memory cell; and(e) a write driver connected to the first bit line for driving a desired charge state on the first bit line.