Patent ID: 6385117
Filing Date: 2002-05-07
Classification: G11C,H02M

Abstract:
A semiconductor memory device inputting and outputting a storage data in accordance with an address signal, comprising:a memory cell array having a plurality of memory cells arranged in a matrix; a word line provided for every row of said memory cell; a row selecting circuit selectively activating said word line in accordance with said address signal; and a voltage generating circuit generating a negative output voltage used for inactivation of said word line in accordance with a negative reference voltage corresponding to an inactivation state of said word line, said voltage generating circuit including: a voltage converting circuit driven by a first voltage higher than said output voltage and a negative second voltage lower than said output voltage for generating said output voltage following said negative reference voltage; and a sub-voltage generating circuit supplying said second voltage and including first to m-th (m is an integer of at least 2) sub-voltage generators each driven by a corresponding first driving voltage equal to or lower than a ground voltage and equal to or higher than said second voltage and by a corresponding second driving voltage for generating a corresponding internal negative voltage, said first sub-voltage generator receiving the ground voltage as said corresponding first driving voltage and a positive third voltage as said corresponding second driving voltage for generating and controlling a first internal negative voltage so as to maintain a difference between said first internal negative voltage and said third voltage within a prescribed value, said i-th sub-voltage generator (2&lE;i&lE;m) receiving an (iâˆ’1)th internal negative voltage generated by said (iâˆ’1)th sub-voltage generator as said corresponding first driving voltage and a positive (i+2)th voltage as said corresponding second driving voltage for generating and controlling an i-th internal negative voltage so as to maintain a difference between said i-th internal negative voltage and said (i+2)th voltage within said prescribed value, and said m-th sub-voltage generator generating said second voltage as said m-th internal negative voltage.