Patent ID: 7178046
Filing Date: 2007-02-13
Classification: G06F,Y02D

Abstract:
1. A microprocessor comprising: a first cache memory; a first instruction fetch unit coupled to the first cache memory; a first instruction decoder coupled to the first instruction fetch unit; a first processing unit coupled to the first instruction decoder; and a first latch adapted to hold a control signal outputted from the first instruction decoder, wherein, when the first instruction fetch unit is inputted with a first instruction which is performed by the first processing unit, the first instruction fetch unit outputs the first instruction to the first instruction decoder; wherein, when the first instruction fetch unit is inputted with a second instruction which is not performed by the first processing unit, the first instruction fetch unit outputs a specific instruction to the first instruction decoder; wherein the first processing unit has a second latch which stores data for calculation and a third latch which stores the calculation result; and wherein, in the case where the first instruction fetch unit outouts the specific instruction to the first instruction decoder, the supply of the clock pulse to the second latch is halted based on the control signal outputted from the first instruction decoder and the supply of the clock pulse to the third latch is halted based on the control signal outputted from the first latch.