Patent ID: 6041426
Filing Date: 2000-03-21
Classification: G01R,G11C

Abstract:
A built in self test (BIST) method for testing an addressable circuit structure, the BIST method comprising:providing a Johnson counter that provides its data output and its parity bit output as a data input to the addressable circuit structure;initiating an address counter to count from zero to the full address range of the addressable circuit structure;for each address provided by the address counter to the addressable memory structure, writing the data output and parity bit output from the Johnson counter to said address, reading the data and parity bit from said address, and comparing the data read from said address to the data and the parity bit read from the parity bit output of the Johnson counter; and written to said addressin the event there is a mismatch between the read data and the written data or between the read parity bit and the parity bit output, generating an interrupt signal.