Patent ID: 9076681
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. A method comprising: forming a control gate structure over a substrate; depositing a charge storage layer over the control gate structure; depositing a memory gate layer over the charge storage layer, wherein the memory gate layer conforms to the charge storage layer; depositing a first dielectric layer over the memory gate layer; applying a first etching process to the first dielectric layer and the memory gate layer to form a first memory gate structure, wherein: forming a first spacer along a sidewall of the first memory gate structure; applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure; recessing an upper portion of the memory gate structure; and forming a second spacer over the memory gate structure.