Patent ID: 6242315
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A method of manufacturing a mixed mode semiconductor device, the method comprising:providing a substrate having the lower electrode of a capacitor and a first conductive layer formed thereon;forming a first dielectric layer over the lower electrode and the first conductive layer;forming a first opening in the first dielectric layer, wherein the first opening exposes a portion of the lower electrode;forming a second dielectric layer to line the first opening, wherein the second dielectric layer makes contact with the lower electrode;forming a second opening in the first dielectric layer, wherein the second opening exposes a portion of the first conductive layer;forming a second conductive layer over the first dielectric layer, wherein the second conductive layer also completely fills the first and second openings; andpolishing the second conductive layer so that a plug and the upper electrode of the capacitor are simultaneously formed, wherein the plug and the upper electrode are formed directly above the first conductive layer and the lower electrode, respectively.