Patent ID: 6815763
Filing Date: 2004-11-09
Classification: G11C,H01L

Abstract:
A semiconductor memory element, comprising:a source region formed in a semiconductor substrate; a drain region formed in said semiconductor substrates; a channel region formed in said semiconductor substrate between said source region and said drain region; an insulation film arranged on a portion of said semiconductor substrate corresponding to said channel region, wherein a plurality of silicon microcrystal grains are formed in said insulation film; and a gate electrode formed over said insulation film to control electric potential of said channel region, wherein a perimeter of each of said silicon microcrystal grains is covered with said insulation film so that each of said microcrystal grains constitutes an independent and isolated charge storage region such that said plurality of said charge storage regions are electrically disconnected, and wherein an electric potential to be applied to said gate electrode upon writing of data and an electric potential to be applied to said gate electrode upon erasing of data have the same polarity.