Patent ID: 9196570
Filing Date: 2015-11-24
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a first wiring arranged in a first wiring layer; a second wiring arranged in the first wiring layer; a third wiring arranged in the first wiring layer between the first and second wirings; a first projecting portion integrally formed with the first wiring between the first and second wirings in the first wiring layer; a fourth wiring arranged in a second wiring layer, the fourth wiring intersecting with the first wiring and the first projecting portion; a first via coupling between the first wiring and the fourth wiring; and a second via coupling between the first projecting portion and the fourth wiring, wherein the first and second wirings are power supply voltage lines; and wherein a voltage of the first wiring is higher than a voltage of the second wiring.