Patent ID: 6404694
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A method of accessing a memory including a first memory bank and a second memory bank by an access sequence controller, each of the first and second memory banks being coupled to common data lines, the method comprising;receiving a first address indicating a data read operation from the first memory bank and a second address indicating a data read operation from the second memory bank in that successive order to the access sequence controller; issuing a first read command for the first memory bank and then issuing a second read command for the second memory bank by the access sequence controller; and outputting read-out data from the second memory bank to the common data lines first and then outputting read-out data from the first memory bank to the common data lines when the latency of the first memory bank to the first read command is larger than the latency of the second memory bank to the second read command.