Patent ID: 7929843
Filing Date: 2011-04-19
Classification: G11B,H04N

Abstract:
1. A data reproduction system for content reproduction, comprising: a reproducing speed determining section that, based on a content reproducing speed, controls a clock pulse outputted from a system clock, making a clock frequency higher according as the content reproducing speed ascends and making the clock frequency lower according as the content reproducing speed descends; a system clock output section that outputs variable clock signal having a frequency controlled by the reproducing speed determining section; and a content reproduction processing section that receives input of the variable clock signal outputted from the system clock and carries out data processing at a processing speed according to the inputted variable clock signal, wherein the content reproduction processing section is capable at least of acquiring the data of a reproducing object stored in a buffer memory and releasing such acquired data to a display section with processing speed kept variable according to the variable clock signal inputted from the system clock, wherein the content reproduction processing section comprises a data storage section, a decoding section, a buffer control section, an output control section, and an output display section, and wherein the buffer control section, the output control section, and the output display section are capable of receiving the variable clock signal outputted from the system clock and carrying out the processing after the processing of data readout from the buffer memory controlled by the buffer control section, while processing speed being kept variable according to the variable clock signal, and wherein the data storage section, the decoding section, and the buffer control section are capable of receiving a fixed clock signal of a fixed frequency and carrying out the processing before the processing of write data into the buffer memory controlled by the buffer control section at a fixed processing speed according to the fixed clock signal, and the frequency of the fixed clock signal is set at a frequency higher than the frequency of the clock signal that has the frequency highest among the variable clock signals outputted from the system clock.