Patent ID: 6353261
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A modified interconnect having reduced resistance for use in a multilayered Integrated Circuit (IC), said interconnect comprising:an interconnect line, said interconnect line existing in a first circuit layer of said multilayered IC, said interconnect line comprised of a conductive material, said interconnect line having a depth in said multilayered IC; an interconnect well, said interconnect well coupled to said interconnect line, said interconnect well having a depth in said multilayered IC that exceeds said depth of said interconnect line, said interconnect well insulated from other conductive materials in said multilayered IC, said interconnect well located between said interconnect line and a bottom surface of a second circuit layer, said second circuit layer is an insulative material at a location approximately overlaying said interconnect line, wherein a material between said interconnect line and said second circuit layer is also an insulative material, said depth of said interconnect well extends into at least one of a plurality of subsequent adjacent layers in said multilayered IC, said plurality of subsequent adjacent layers located adjacent to said first circuit layer.