Patent ID: 7148538
Filing Date: 2006-12-12
Classification: G11C,H01L

Abstract:
1. A vertical floating gate memory cell string, comprising: a substrate, comprising one or more raised areas, defining trenches therebetween; a plurality of floating gate memory cells, wherein the floating gate memory cells are formed vertically on the sidewalls of one or more raised areas and/or trenches; and wherein the plurality of floating gate memory cells are coupled in a serial string by source/drain regions formed at the top of the one or more raised areas and at the bottom of the one or more trenches; wherein the one or more raised areas and/or trenches of the vertical floating gate memory cell string are formed on a P-well isolation region formed on the substrate and where the vertical floating gate memory cell string is isolated from adjacent structures formed on the substrate by one or more isolation regions formed between the vertical floating gate memory cell string and the adjacent structures, thereby defining one or more sidewalls of the P-well isolation region.