Patent ID: 7795923
Filing Date: 2010-09-14
Classification: H03K

Abstract:
1. A logic circuit comprising: a first transistor being a first type, and having a gate terminal that is adapted for receiving a control signal which is representative of one of NAND and NOR operations of at least first and second signals, a first terminal that is adapted to be coupled to a first power source, and a second terminal serving as an output terminal of the logic circuit; a second transistor being a second type, and having a gate terminal that is coupled to said gate terminal of said first transistor, a first terminal that is adapted for receiving a third signal, and a second terminal that is coupled to said second terminal of said first transistor; and series-connected third and fourth transistors, each being the first type and having a gate terminal, said gate terminals of said third and fourth transistors being respectively adapted for receiving the first and second signals, said series-connected third and fourth transistors being connected in parallel to said second transistor.