Patent ID: 8301678
Filing Date: 2012-10-30
Classification: G01S,G06F,H04B

Abstract:
1. A receiver of a radionavigation signal, comprising a digital component of ASIC or FPGA type able to implement a method for calculating correlations between a first sequence and a plurality of second sequences, said first sequence and one of said second sequences having a duration D Code , the first sequence being extracted from a digital signal comprising a code, said code comprising elementary time divisions, called chips, of a duration D chip , said chips being sampled in samples on pulses delivered by an NCO oscillator at the mean frequency 2/D chip , the second sequence resulting from a sampling at a frequency Fe of an analog signal, the frequency Fe being greater than 2/D chip , said method comprising a step of aggregating the samples of the second sequence, over consecutive integration intervals of duration equal on average to D chip /2, starting at each pulse of the NCO oscillator, so as to determine results of elementary aggregates, the results of elementary aggregates being employed to determine results of calculations of correlations between a first sequence and the plurality of second sequences, the plurality of second sequences being deduced from one another by a time shift of duration D chip /2 comprising the following steps using a logic device: summing two results of consecutive elementary aggregates to obtain double elementary aggregate results; weighting each result of double elementary aggregate of the second sequence by the value of the code of the first sequence to obtain results of weighted double aggregates; and accumulating the results of weighted double aggregates.