Patent ID: 7193903
Filing Date: 2007-03-20
Classification: G11C

Abstract:
1. A method of controlling an integrated circuit (IC) to which inputs and outputs (I/Os) are separately provided and to which a write address and a read address are simultaneously input during one period of a clock signal and which comprises memory blocks, each of the memory blocks comprising sub-memory blocks, data memory blocks corresponding to the memory blocks, and a tag memory, controlling unit, the method comprising: (a) receiving a write address, a read address, and write data; (b) determining, in which sub-memory block of the sub-memory blocks and in which data memory block of the data memory blocks a data read operation and a data write operation are to be performed in response to the write address and the read address by using the tag memory controlling unit; (c) performing the data read operation or the data write operation in the data memory block according to the determination of step (b); and (d) performing the data read operation or the data write operation in the sub-memory block according to the determination of step (b).