Patent ID: 8566931
Filing Date: 2013-10-22
Classification: G04F,G06F,G06Q,G07F,G11C,H01L

Abstract:
1. A method for protecting data contained in an electronic circuit against a disturbance of its operation, wherein a detection of a disturbance conditions the incrementing or the decrementing of a counter over at least one bit, the counter being automatically reset at the end of a time period independent from the fact that the circuit is or not powered, and the counter being made in the form of at least one charge retention circuit comprising at least one first capacitive element exhibiting a leakage through its dielectric space, the leakage discharging the first capacitive element to an inactive state at the end of the time period, wherein a switching of a bit of said counter to an active state is caused by an injection or extraction of charges into or from said first capacitive element, and wherein the at least one charge retention circuit comprises: the at least one first capacitive element having a first electrode connected to a floating node; at least one second capacitive element having a first electrode connected to said floating node, the second capacitive element having a greater capacitance than the first one; and at least one first transistor with an insulated control terminal connected to said floating node.