Patent ID: 8214561
Filing Date: 2012-07-03
Classification: G06F

Abstract:
1. A peripheral interface for connecting a control computer to a peripheral device, wherein the control computer includes a central processing unit (CPU), a system bus connecting the peripheral interface to the CPU, and a working memory, the peripheral interface comprising: a system bus connection for operatively connecting the peripheral interface to the system bus; a peripheral device connection for operatively connecting the peripheral interface to the peripheral device for the transmission of data from the peripheral device to the control computer via the system bus; a direct memory access controller for accessing the working memory of the control computer via the system bus; means for receiving a communication from the control computer identifying an area of the working memory to be used as a write buffer for the data to be transmitted between the peripheral device and the control computer; means for accessing the write buffer via the system bus; a control unit for writing the data into the write buffer via the direct memory access controller; means for accepting information from the control computer on an address boundary of an amount of the data to be transmitted from the peripheral device to the control computer, wherein the information is in the form of a first pointer (RV) after an end of a free buffer zone, and wherein the information is accepted independently of the transmission of the amount of data from the peripheral device to the control computer; and means for preparing a progress report for retrieval by the control computer, wherein the progress report is in the form of a second pointer (RC) at a beginning of data already written to the write buffer; wherein the control unit a) identifies a deviation between the first pointer (RV) and the second pointer (RC), b) thereupon independently without instructions from the control computer, writes data that have arrived in the internal buffer memory from the peripheral device into the write buffer and continues incrementing the second pointer (RC) in correspondence with the number of written data units, and c) repeats the writing of data and incrementing of the second pointer (RC) without synchronization with the control computer until the first pointer (RV) and second pointer (RC) are identical.