Patent ID: 7755875
Filing Date: 2010-07-13
Classification: G02F,G09G,H01L

Abstract:
1. A semiconductor device comprising: a substrate; active elements being formed in a matrix on the substrate, the active elements having four corners; a clock signal terminal; a scanning line driving circuit having scanning line driving unit circuits; a clock signal line being electrically connected to the clock signal terminal and being disposed along the scanning line driving unit circuits, a first corner among the four corners of the active elements being the location of the clock signal terminal and a power terminal; a power line being electrically connected to the power terminal and being disposed along the scanning line driving unit circuits; a first protective circuit electrically connected to a first end of the clock signal line; a second protective circuit electrically connected to a second end of the clock signal line, the second protective circuit being arranged at a second corner among the four corners of the active elements, the second corner being far from the clock signal terminal; a third protective circuit electrically connected to a first end of the power line; and a fourth protective circuit electrically connected to a second end of the power line, wherein a first capacitance of the first protective circuit and a second capacitance of the second protective circuit are configured to be lower than a third capacitance of the third protective circuit and a fourth capacitance of the fourth protective circuit.