Patent ID: 8242589
Filing Date: 2012-08-14
Classification: G01R,G11C,H01L

Abstract:
1. A semiconductor device in which a first LSI and a second LSI are stacked, wherein the first LSI and the second LSI are connected through a first Through Silicon Via; the first LSI has a first transmitting circuit connected to the first Through Silicon Via, and a first test circuit that transmits a test pattern which is a combination of a logic value “0” and a logic value “1” to the first Through Silicon Via through the first transmitting circuit; and the second LSI has a first receiving circuit connected to the first Through Silicon Via, and a second test circuit that retains a test pattern identical with the test pattern transmitted by the first LSI, and compares the test pattern with a test pattern received by the first receiving circuit to check whether or not the first Through Silicon Via is correctly connected.