Patent ID: 7474662
Filing Date: 2009-01-06
Classification: H04L

Abstract:
1. A scheduler in a network processor, comprising: memory to store schedule control blocks in a first, second, and third linked list of schedule control blocks, each schedule control block associated with a queue and a rate limit and comprising a counter; first, second, and third calendar entries associated with the first, second, and third linked lists, respectively, each calendar entry adapted to store an address for a first-out schedule control block in the linked-list of schedule control blocks associated with the calendar entry; and control circuitry to decrement a counter of a first-out schedule control block from one of the first and second linked lists; and to move the first-out schedule control block from the one linked list to the other of the first and second linked lists if the decremented counter is greater than a rate limit of the first-out schedule control block during a specified time interval, and to move the first-out schedule control block from the one linked list to the third linked list if the decremented counter equals or is less than the rate limit during the specified time interval.