Patent ID: 8815718
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a polish stop layer over a substrate, the substrate including a CMOS region and an array region; forming a plurality of patterning layers over the polish stop layer; forming a CMOS cover layer over the patterning layers in the CMOS region; forming a plurality of array pillars over the array region, the array pillars separated by a plurality of array trenches, wherein forming the array pillars includes removing the CMOS cover layer and the patterning layers; planarizing the polish stop layer after forming the array pillars and array trenches; doping portions of the substrate within the array trenches; forming a plurality of vertical surround gates in the array trenches, the vertical surround gates surrounding the array pillars; forming an array filler layer over the polish stop layer, the vertical surround gates, and the substrate; forming a CMOS photoresist pattern over the array filler layer, the CMOS photoresist pattern including a plurality of CMOS trenches in the CMOS region, and a shared trench in the array region; and etching the CMOS trenches in the CMOS region through a portion of the substrate such that the array pillars under the shared trench are also etched to form a plurality of contact holes.