Patent ID: 8015567
Filing Date: 2011-09-06
Classification: G06F,H04L

Abstract:
1. An advanced processor, comprising: a packet distribution engine (PDE) configured to receive a plurality of packets from a networking input and to provide the plurality of packets in a load-balanced distribution to a selected group of multiple threads; a plurality of processor cores configured to execute the multiple threads; a fast messaging network (FMN) having a ring based interconnect configuration, said FMN coupling the PDE to the plurality of processor cores, said FMN configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory; and a data switch interconnect (DSI) separate from said FMN and having a ring based interconnect configuration, said DSI configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory.