Patent ID: 8723249
Filing Date: 2014-05-13
Classification: H01L

Abstract:
1. A non-volatile memory comprising: a substrate; a gate dielectric layer, disposed on the substrate and having a cavity formed on two end sides of the gate dielectric layer; a gate conductive layer, disposed on the gate dielectric layer and having a bottom width greater than a width of the gate dielectric layer, wherein the gate conductive layer, the substrate and the gate dielectric layer cooperatively constitute a symmetrical opening thereamong; a nitride layer, having an L-shape and formed with a vertical part extending along a sidewall of the gate conductive layer and a horizontal part extending into the opening, wherein the vertical part and the horizontal part are formed as an integral structure and a height of the vertical part of the L-shaped nitride layer is below a top surface of the gate conductive layer; a spacer, disposed on the substrate as well as the nitride layer on the side of the gate conductive layer; a first oxide layer, disposed on a sidewall and bottom of the gate conductive layer and among the gate conductive layer, the nitride layer and the gate dielectric layer; and a second oxide layer, disposed on the substrate and among the gate dielectric layer, the nitride layer and the substrate.