Patent ID: 6144538
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A high voltage metal oxide semiconductor (HV MOS) transistor used in an electrostatic discharge (ESD) protection circuit, the ESD protection circuit formed on a semiconductor wafer and comprising an input port, the semiconductor wafer comprising a substrate, an active region formed in a predetermined area on the surface of the substrate, and a first insulation layer formed on the surface of the substrate and surrounding the active region, the active region comprising a doped area, the HV MOS comprising:a gate installed on the active region;a source and a drain installed inside the active region and positioned on opposite sides of the gate, both the source and the drain being double diffuse drains (DDD); anda second insulation layer installed on the active region and positioned between the gate and the source and between the gate and the drain, the second insulation layer used for insulating the gate from the source as well as insulating the gate from the drain wherein a drift region does not exist at the intersection of the doped area of the active region and the second insulation layer, thus enhancing the critical voltage between the source and the drain;wherein the input port of the protection circuit is electrically connected to the source, and the drain and the gate are electrically connected to a voltage source; whereby when an input voltage from the input port is higher than a critical voltage between the source and the drain, the source and the drain will electrically conduct together through the doped area in the active region so as to eliminate the input voltage from the input port.