Patent ID: 6633974
Filing Date: 2003-10-14
Classification: G06F

Abstract:
Instruction branching circuitry comprising:(a) a plurality of logical stacks each having a plurality of entries for storing an address to a corresponding instruction in memory; (b) a counter for generating a pointer to an entry of an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks; (c) circuitry for tracking, stack operations wherein said circuitry determines a current stack operation comprises a Push operation and an immediately preceding stack operation comprises a Pop operation; (d) selector circuitry for selecting an active one of the logical stacks, wherein the selector circuitry changes the active stack from a first stack to a second stack in response to the determination by the circuitry in (c); and (e) stack operation circuitry for performing the Pop operation to the first stack and the Push operation to the second stack after the second stack has been selected as the active stack.