Patent ID: 6724050
Filing Date: 2004-04-20
Classification: H01L

Abstract:
An integrated circuit fabricated in a semiconductor material having a surface of a first conductivity type, said circuit having at least one vertical bipolar transistor surrounded at least in part by a dielectric isolation zone having a lower boundary, said transistor comprising:an emitter region of opposite conductivity type; a base contact region of said first conductivity type; a well of opposite conductivity type surrounding said emitter and base contact regions, extending from said surface deep into said semiconductor material; a collector region of said opposite conductivity type buried in said semiconductor material; a subsurface base region comprising a semiconductor band of said first conductivity type between said collector and said emitter, surrounded by said well and forming a junction with both said emitter and said collector regions, said base region having a high resistivity, thereby enabling said transistor to operate with a low breakdown voltage for low ESD clamping voltage and high beta; said collector extending laterally to said well, thereby electrically isolating the base and emitter of said transistor, and extending vertically below said base and emitter, said collector having an upper boundary above the lower boundary of said dielectric isolation zone, and a lower boundary below the lower boundary of said isolation zone, wherein the depth of the lower boundary of said isolation zone is from 300 to 400 nm.