Patent ID: 8278207
Filing Date: 2012-10-02
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming an insulation layer on a substrate on which a plurality of lower conductive structures is formed in such a manner that the insulation layer includes an opening; forming a barrier layer on a sidewall and a bottom of the opening of the insulation layer in such a manner that the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material used to form the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material used to form the second barrier layer; forming an interconnection in the opening of which the sidewall and the bottom are covered with the barrier layer in such a manner that the interconnection is electrically connected to the lower conductive structure; and forming an upper conductive structure on the insulation layer in such a manner that the upper conductive structure is electrically connected to the interconnection so that the upper conductive structure is electrically connected to the lower conductive structure through the interconnection, wherein forming the first barrier layer comprises forming a first preliminary barrier layer on the sidewall and the bottom of the opening and on a surface of the insulation layer at a first temperature in a range between about 150° C. to less than 200° C.; and wherein forming the second barrier layer comprises forming a second preliminary barrier layer on the first preliminary barrier layer along a profile of the insulation layer including the opening at a second temperature in a range between greater than 200° C. to less than about 400° C.