Patent ID: 7709308
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a fin having first and second sidewalls opposite to each other on a substrate; forming a first gate line on the first sidewall of the fin in the shape of a spacer and along a length of the first sidewall; forming a second gate line on the second sidewall of the fin in the shape of a spacer and along a length of the second sidewall; forming an interlevel insulation pattern to cover the substrate and the first and the second gate lines around the fin; forming a mold insulation layer to cover the substrate; patterning the mold insulation layer to form first and second grooves exposing a top surface of the fin, the first and second grooves intersecting the fin in parallel while being isolated from each other; forming first and second impurity layers in the fin under the first and second grooves, respectively; and forming first and second bit lines in the first and second grooves, respectively, wherein the first and second bit lines are isolated from each other and respectively formed directly on the first and second impurity layers and a channel region is formed between first and second impurity regions.