Patent ID: 6789218
Filing Date: 2004-09-07
Classification: H03M,H04L,H05K

Abstract:
A forward error correction encoder for encoding a frame of information bits of size n*m comprising:first encoder for encoding said information bits in natural order and for generating first final state information; seed ROM for storing a set of n seed values, wherein each seed from said set of seeds has a unique modulo-n value, said set of n seed values having a spread value S greater than 1, and each seed value is a member of a substantially evenly distributed subset of addresses; interleaver for generating an interleaved frame of said information bits using said set of seed values; second encoder for encoding said interleaved frame, and for generating second final state information; first initialization state calculation circuit for calculating a first init state based on said first final state information; second initialization state calculation circuit for calculating a second init state based on said second final state information.