Patent ID: 6274915
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A transistor comprising:a semiconductor substrate;a source region within said substrate;a drain region within said substrate, separated from said source region by a channel region within said substrate, wherein said channel region has an impurity concentration of between 1.times.10.sup.17 and 5.times.10.sup.18 atoms/cm.sup.3 ;an insulating layer formed on an upper surface of said channel region; anda conductive gate formed on said insulating layer, the conductive gate comprising polysilicon with an impurity concentration of between 1.times.10.sup.19 and 5.times..sup.19 atoms/cm.sup.3, wherein when said transistor is conducting, the degree of depletion of the conductive gate is greater than a minimum degree of depletion.