Patent ID: 6208559
Filing Date: 2001-03-27
Classification: G11C,H01L

Abstract:
A process of operating a first memory cell in a memory array, the memory array including the first memory cell and a second memory cell in the same row of the memory array as the first memory cell, each of the memory cells in the array having a write transistor comprising a write gate, a write source, a write drain, and a write gate oxide, each of the memory cells having a sense transistor comprising a sense floating gate and a sense gate oxide, and each of the memory cells having a tunnel diode coupled at its first terminal to the write source and at its second terminal to the sense floating gate, the write transistors in the first memory cell and the second memory cell being coupled at their write drains, the process of operating the first memory cell comprising the acts of:applying a voltage V.sub.pp to the first memory cell write gate and to the first memory cell write drain;programming the first memory cell by removing electrons from the first memory cell's sense floating gate in response to the voltage V.sub.pp ;generating a voltage V.sub.pp -V.sub.max where V.sub.max is a voltage less than or equal to the maximum voltage which can be applied across the second memory cell write gate oxide without causing damage to the second memory cell write gate oxide or causing substantial leakage through the second memory cell write gate oxide;applying the voltage V.sub.pp -V.sub.max to the second memory cell write gate and, in response to the voltage V.sub.pp applied to the first memory cell write transistor, applying the voltage V.sub.pp to the second memory cell write drain;generating across the second memory cell write gate oxide a voltage less than or equal to V.sub.max in response to said applying the voltage V.sub.pp -V.sub.max ; andgenerating a voltage less than the voltage V.sub.pp -V.sub.max at the second terminal of the second memory cell tunnel diode in response to the voltages V.sub.pp and V.sub.pp -V.sub.max applied to the second memory cell write transistor, the voltage generated being insufficient to program or erase the second memory cell sense transistor.