Patent ID: 6744294
Filing Date: 2004-06-01
Classification: H03F,H03K

Abstract:
A method for minimizing harmonic content in a digital signal driver circuit, having a digital input signal applied to an input node associated with said driver circuit and generating a corresponding digital output signal on an output node associated with said driver circuit, said method comprising the steps of:connecting two or more MOS devices in cascode connection with each other and with said input node and said output node, wherein said two or more cascode connected MOS devices each comprise a gate electrode, a source electrode and a drain electrode; and controlling the slew rate of one or more edge transitions associated with said output signal using one or more parasitic capacitance values associated with said two or more cascode connected MOS devices such that said harmonic content is minimized when connecting at least one of said gate electrodes to a fixed potential; and applying a control signal to at least another of said gate electrodes to turn off a leakage current path between said corresponding each of said source and said drain electrodes when said circuit is in idle periods.