Patent ID: 6819614
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array; a pair of input/output (I/O) lines for transferring a pair of differential signals that are read out from the memory cell array; a first precharge circuit for precharging the pair of I/O lines into a first level in response to a first precharge signal; a pair of switch transistors having one electrode for each of the switch transistors connected to the pair of I/O lines; a pair of data lines connected to the other electrodes of the pair of switch transistors; a second precharge circuit for precharging the pair of data lines into a second level in response to a second precharge signal; a sense amplifier for sensing and amplifying the voltages of the pair of data lines; and a control circuit for generating a control signal that turns on one of the pair of switch transistors while turning off the other switch transistors, and for varying the voltage level of the control signal according to variation of the threshold voltage of the pair of switch transistors.