Patent ID: 7669321
Filing Date: 2010-03-02
Classification: H05K,Y10T

Abstract:
1. A method of manufacturing a set of identical multiple-layer circuit boards, comprising: incorporating a test site on each of the set of circuit boards, the test site having a set of test connections passing through a test via on respective test connection layers of each of the set of circuit boards, the set of test connections including a first test connection, a second test connection, and a third test connection, the test connection layers including (1) a first layer adjacent to a target layer, (2) a second layer spaced apart from the target layer with the first layer therebetween, and (3) a third layer spaced apart from the target layer with the first layer and second layer therebetween; back-drilling, on a first circuit board of the set of circuit boards, with a back-drill the test via from the direction of the third layer to remove undesired via metallization, the back-drilling breaking the test connections of all the layers through which it passes; measuring, on the first circuit board, the continuity of the test connections to determine a pattern of broken and non-broken test connections resulting from the back-drilling; and examining, on the first circuit board, the pattern of broken and non-broken test connections to ascertain the actual depth of the back-drilling of the test via in relation to the target layer; wherein the method further comprising: wherein back-drilling, on the first circuit board, with a back-drill the test via from the direction of the third layer to remove undesired via metallization breaks the third test connection of all the third layer, the second test connection of the second layer, and the first test connection of the first layer; wherein measuring, on the first circuit board, the continuity of the test connections to determine a pattern of broken and non-broken test connections resulting from the back-drilling determines that the third test connection, the second test connection, and the first test connection are broken; wherein examining, on the first circuit board, the pattern of broken and non-broken test connections to ascertain the actual depth of the back-drilling of the test via in relation to the target layer determines that undesired via metallization has been removed and that the target layer may have been nicked; and wherein adjusting the back-drill based on the ascertained actual depth of the back drilling of the test via in relation to the target layer includes adjusting the back-drill to drill shallower.