Patent ID: 6577362
Filing Date: 2003-06-10
Classification: G02F

Abstract:
A process for forming a pixel cell comprising the steps of:forming an intermetal dielectric layer; forming a first via and a third via through the intermetal dielectric layer; filling the first via with electrically conducting material to form a first via plug, the first via plug in electrical communication with an underlying capacitor structure; filling the third via with electrically conducting material to form third via plug, the third via plug in electrical communication with a ground; forming a reflective metal layer over the intermetal dielectric layer; etching the reflective metal layer to form a non-grounded metal portion in contact with the first via plug and a grounded reflective metal surface in contact with the third via plug; forming a dielectric layer over the grounded reflective metal surface and the non-grounded metal portion; forming a second via through the dielectric layer; filling the second via with electrically conducting material to form a second via plug, the second via plug in electrical contact with the non-grounded metal portion; and forming an optically transparent electrically conducting pixel electrode on top of the dielectric layer and in electrical contact with the second via plug.