Patent ID: 6441650
Filing Date: 2002-08-27
Classification: H03K

Abstract:
An offset comparator comprising:a differential stage having a first input and a second input; an output stage electrically connected to said differential stage in order that an output of said comparator is zero when said two inputs have therebetween a specific voltage difference; and a biasing stage electrically connected to said differential stage comprising: a first source follower for providing a first biasing voltage for creating a second input voltage to said second input; a second source follower for providing a second biasing voltage for creating a first input voltage to said first input in order that said two input voltages have therebetween said specific voltage difference; a first diode connected transistor electrically connected to said first source follower for providing thereto a first biasing current; and a second diode connected transistor electrically connected to said second source follower for providing thereto a second biasing current.