Patent ID: 7757144
Filing Date: 2010-07-13
Classification: G11C

Abstract:
1. A method of testing an integrated circuit module, the integrated circuit module comprising a plurality of integrated circuit devices, the method comprising: generating a plurality of test vector patterns; generating a first clock signal having a first frequency and a first phase; generating a plurality of second clock signals, each of the plurality of second clock signals having the first frequency and one of a plurality of second phases; for each of the plurality of test vector patterns and for each of the plurality of second clock signals: identifying a data valid window for each of the plurality of integrated circuit devices from at least one of said results determined for the plurality of test vector patterns and the plurality of second clock signals, wherein the data valid window defines a length of time in which a valid sample can be expected to be taken from data signals transmitted by the respective integrated circuit device; verifying that the data valid window for each of the plurality of integrated circuit devices meets specification requirements; determining at least one test outcome for the integrated circuit module, wherein the at least one test outcome is based on at least one result of the verifying; and at least one of recording and outputting the at least one test outcome for the integrated circuit module; wherein each of the plurality of integrated circuit devices, when in operation, utilizes a data strobe signal that accompanies at least one of data signals being transmitted from and data signals received by the respective integrated circuit device; and wherein the determining at least one test outcome is performed after identifying the data valid window for each integrated circuit device of the integrated circuit module without having both computed a common sampling window and verified that the common sampling window meets specification requirements.