Patent ID: 7430641
Filing Date: 2008-09-30
Classification: G06F

Abstract:
1. A circuit for retrieving some or all of the data blocks of a logical unit into a cache from one or more mass data storage devices, said system comprising: a cache memory; and two or more controllers, wherein each of said controllers includes a communication module and is associated with one or more mass data storage devices; wherein a first controller is adapted to cause a second controller to retrieve a data block associated with a logical unit by transmitting a signal to the second controller via their respective communication modules; wherein said first controller is adapted to signal one or more other controllers whether it has received one or more data block requests associated with the logical unit; and wherein at least one prefetch decision module is adapted to trigger the retrieval of data blocks based on data block requests received by a controller with which it is associated and/or based on data block requests received by other controllers.