Patent ID: 6048792
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A method for forming an interconnection structure in a semiconductor device including the steps of:forming a diffused region in a semiconductor substrate;forming on said semiconductor substrate a first dielectric film having a first via-hole exposing said diffused region;forming a barrier layer on an inner surface of said first via-hole including said exposed diffused region;forming on said first dielectric film a second dielectric film having a second via-hole at the location of said first via-hole for exposing said barrier layer;depositing a conductor layer on an exposed surfaces of said second dielectric film and said exposed barrier layer in said second via-hole;forming a first tungsten film on said conductor layer by a first low-pressure CVD process using SiH.sub.4 and WF.sub.6 gases while maintaining a flow rate ratio between WF.sub.6 gas and SiH.sub.4 gas within a range of 1 to 2, the thickness of both said conductor layer and first tungsten film being smaller than the thickness of said second dielectric film;forming a second tungsten film on said first tungsten film by a second low-pressure CVD process using H.sub.2 and WF.sub.6 gases, said second tungsten film filling said second via-hole;patterning said first and second tungsten films to leave a tungsten plug in said second via-hole; andforming an interconnect layer overlying said second dielectric film and in contact with said tungsten plug.