Patent ID: 6190943
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A chip scale packaging method comprising the steps of:(a) providing a substrate with a conductive surface, and a nonconductive surface which is provided with one or more chip-implanting areas whereby the chip-implanting areas are provided with one or more through holes;(b) coating by stenciling the chip-implanting areas with a thermoplastic adhesive layer of a predetermined thickness;(c) implanting a semiconductor chip in each of the chip-implanting areas such that an active surface of the chip is in contact with the thermoplastic adhesive layer, and that a plurality of bonding pads of the active surface are corresponding in location to the through holes;(d) heating the substrate and the implanted chips at a predetermined temperature and under a predetermined pressure for a predetermined period of time;(e) wire bonding the substrate and the implanted chips with a plurality of metal bonding wires whereby the metal bonding wires connect the conductive surface of the substrate with the bonding pads of the implanted chips via the through holes;(f) providing the implanted chips and the through holes with a passivation layer of a nonconducting resin material; and(g) implanting the conductive surface of the substrate with a plurality of spherical bonding points in a grid array fashion.