Patent ID: 9058854
Filing Date: 2015-06-16
Classification: G11C

Abstract:
1. A semiconductor memory apparatus in which a plurality of chips are stacked and are coupled by through vias, comprising: a first chip including a refresh signal generation unit which is configured to generate a refresh signal in response to an external command; a second chip configured to generate a first delayed refresh signal by delaying the refresh signal, and perform a refresh operation in response to the first delayed refresh signal; and a third chip configured to generate a second delayed refresh signal by delaying the first delayed refresh signal, perform a refresh operation in response to the second delayed refresh signal, and output the second delayed refresh signal to the first chip, wherein the first chip includes an output selection unit which is configured to generate a totally delayed refresh signal and to output one of the second delayed refresh signal and the totally delayed refresh signal as a refresh feedback signal in response to an output control signal, wherein the totally delayed refresh signal is obtained by delaying the refresh signal by a time corresponding to a sum of a delaying time for generating the first delayed refresh signal and a delaying time for generating the second delayed refresh signal.