Patent ID: 6483886
Filing Date: 2002-11-19
Classification: H03K,H03L

Abstract:
A phase-locked loop circuit comprising:an input terminal for accepting an input clock signal; a phase/frequency detector having a signal input connected to said input terminal, a phase detection input and a signal output; a charge pump having a pump input connected to said signal output of said phase/frequency detector and having a pump output; a low-pass filter having a filter input connected to said pump output and having a filter output; a voltage-controlled oscillator having an oscillator input connected to said filter output, an oscillator output, and a plurality of signal taps, said signal taps being separated from one another by substantially uniform delays; a feedback loop feeding back to said phase detection input a signal from one of said signal taps, said feedback loop comprising a feedback multiplexer for selecting said one of said signal taps to feed back; and an output multiplexer for selecting one of said signal taps as an output signal of said phase-locked loop; wherein: when said output multiplexer selects a first signal tap and said feedback multiplexer selects a subsequent one of said signal taps separated from said first signal tap by an odd number of signal taps, said output signal has a phase that is advanced relative to said input clock signal by an even multiple of said substantially uniform delay; when said feedback multiplexer selects a first signal tap and said output multiplexer selects a subsequent one of said signal taps separated from said first signal tap by an odd number of signal taps, said output signal has a phase that is retarded relative to said input clock signal by an even multiple of said substantially uniform delay; and said even multiple of said substantially uniform delay is one more than said odd number of signal taps.