Patent ID: 7782675
Filing Date: 2010-08-24
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first select transistors each having a current path with one end connected to one end of a current path of an associated one of the memory cell strings, and a plurality of second select transistors each having a current path with one end connected to the other end of the current path of an associated one of the memory cell strings; a source line which is electrically connected to the other end of the current path of an associated one of the first select transistors; and a bit line which is electrically connected to the other end of the current path of an associated one of the second select transistors, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage.