Patent ID: 9171758
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, comprising: forming a plurality of gates and source/drain regions on a semiconductor substrate; forming an etch stop layer over the plurality of gates; forming a dielectric layer over the etch stop layer; forming a first source/drain contact cavity in the dielectric layer; depositing a first sacrificial fill layer in the first source/drain contact cavity; forming a second source/drain contact cavity in the dielectric layer; removing the first sacrificial fill layer in the first source/drain contact cavity; depositing a second sacrificial fill layer in the first source/drain contact cavity and second source/drain contact cavity; partially recessing the second sacrificial fill layer to a level below a top of the dielectric layer; depositing a capping layer over the dielectric layer and second sacrificial fill layer; forming a plurality of gate contact cavities, wherein each of the plurality of gate contact cavities exposes one of the plurality of gates; removing the second sacrificial fill layer; and depositing a fill metal in the first source/drain contact cavity, second source/drain contact cavity, and the plurality of gate contact cavities.