Patent ID: 6587942
Filing Date: 2003-07-01
Classification: H03M,H04L

Abstract:
A serial to parallel interface, comprising:an input port for receiving at least one set of serial data from at least one data source, and providing a set of input serial data, the input serial data having one of a plurality of possible formats; a register having an input terminal for receiving the set of input serial data, and an output terminal, the register converting the set of input serial data into a set of parallel data, and providing the set of parallel data at an output terminal; and a signal generator coupled to.receive a set of indication information, the indication information comprising information indicating a desired operational mode and a format for the input serial data the signal generator generating coordination signals based upon the indication information, at least a subset of the coordination signals being applied to the register to control the operation of the register to enable the register to properly convert the set of input serial data into the set of parallel data, wherein a data cycle of data processed by the register includes mutually exclusive first and second data half-cycles, each half-cycle having a selected length of L bits, where the first data half-cycle receives the input serial data in a first time interval contemporaneous with a second time interval during which output data are read out of the register from the second half-cycle.