Patent ID: 6515528
Filing Date: 2003-02-04
Classification: H03K

Abstract:
Flip-flop circuithaving a first latch circuit to which a binary input signal and a binary clock signal are applied and which is so designed that it accepts the input signal value applied and switches it through to its output if the clock signal is in a first state, and having a second latch circuit to which the output signal of the first latch circuit and the clock signal are applied and which is so designed that it accepts the output signal value from the first flip-flop circuit and emits it as the output signal value of the flip-flop circuit if the clock signal is in a second state, wherein connected to the output of the second latch circuit is a non-differential output driver circuit from which the output signal value of the flip-flop circuit is emitted, wherein the first and second latch circuits are each bistable CMOS latch circuits having coupled to them controlling field-effect transistors to which the clock signal is applied and comprising switching means for setting and resetting the corresponding latch circuits, wherein the bistable CMOS latch circuits forming the first and second latch circuits each comprise, connected in parallel, two circuits each comprising a p-channel field-effect transistor connected in series with an n-channel field-effect transistor, the control connections of the p-channel field-effect transistors of one series circuit being connected in each case to the node of the other series circuit, wherein the switching means for setting and resetting the second latch circuit comprise a further controlling field-effect transistor which is coupled on the one hand to the n-channel field-effect transistor in the series circuit on the input side of the second latch circuit and on the other to the controlling field-effect transistor and to which a resetting signal is applied, and wherein the switching means for setting and resetting the second latch circuit further comprise a further controlling field-effect transistor which is coupled on the one hand to the n-channel field-effect transistor in the series circuit on the output side of the second latch circuit and on the other to the controlling field-effect transistor and to which a setting signal is applied.