Patent ID: 9027021
Filing Date: 2015-05-05
Classification: G06F

Abstract:
1. A method, in a logically partitioned data processing system, for controlling depth and latency of exit of a virtual processor's idle state, the method comprising: generating, by a virtualization layer, a cede latency settings information (CLSI) data, wherein said CLSI data includes available idle states and wake-up characteristics for virtual processors, and wherein said wake-up characteristics of said CLSI data includes a maximum wake-up latency in time base ticks; responsive to booting a logical partition, communicating, by said virtualization layer, said CLSI data to an operating system (OS) of said logical partition; determining, by said OS based upon said CLSI data, a particular idle state of a virtual processor under a control of said OS; and responsive to said OS calling said virtualization layer, communicating, by said OS, said particular idle state of said virtual processor to said virtualization layer for assigning said particular idle state and wake-up characteristics to said virtual processor.