Patent ID: 8356186
Filing Date: 2013-01-15
Classification: G06F,H04L

Abstract:
1. A decryption system for reducing processing latency of stored, encrypted instructions, said system comprising: a storage device configured to store a plurality of sets of encrypted processor instructions, wherein a processor configured to a controller, operatively coupled to the processor, wherein the controller is configured to the key generator, operatively coupled to the controller, wherein the key generator is configured to a plurality of memory banks, each memory bank operatively coupled to both the key generator through the first bus switch and a combiner through a second bus switch, where the first bus switch, operatively coupled to the controller, wherein the first bus switch is configured to the second bus switch, operatively coupled to the controller, wherein the second bus switch is configured to the combiner, operatively coupled to the second bus switch, the storage device, and the processor, wherein the combiner is configured to