Patent ID: 6707092
Filing Date: 2004-03-16
Classification: H01L,Y10S

Abstract:
A semiconductor dynamic random access memory, wherein:said dynamic random access memory includes memory cells, each of said memory cells comprising: a semiconductor pillar, a capacitor in which a first portion of said semiconductor pillar is used as an electrode of said capacitor, and a longitudinal insulated gate static induction transistor in which a second portion of said semiconductor pillar is used as an active region of said transistor, and said semiconductor pillar being connected to a bit line; and the semiconductor pillar formed of a layer structure comprising: a semiconductor substrate of a first conductive type, a first semiconductor layer of a second conductive type formed on said semiconductor substrate of the first conductive type, and a second semiconductor layer of the second conductive type formed on said first semiconductor layer, said second semiconductor layer having a lower concentration than that of said first semiconductor layer, grooves formed in predetermined regions and trenched down to said semiconductor substrate to thereby form adjacent pillars, said semiconductor pillar mainly comprising said first semiconductor layer, and being formed in a pillar form and disposed between said grooves, a plate electrode of said capacitor embedded within said groove adjacent said first semiconductor layer with a capacitor insulation film therebetween, a word line and a gate electrode of said insulated gate static induction transistor comprising an embedded conductor positioned adjacent to said plate electrode, and said first semiconductor layer and said second semiconductor layer with an insulation film therebetween, a drain region of said insulated gate static induction transistor comprising a semiconductor region of the second conductive type formed at a top of said semiconductor pillar, and a bit line of a memory cell array connected to said drain region.