Patent ID: 7457922
Filing Date: 2008-11-25
Classification: G06F

Abstract:
1. A system for cache line placement prediction for a multiprocessor non-uniform cache architecture, comprising: a plurality of central processing unit (CPU) cores comprising at least first through third CPU cores; a non-uniform cache comprising a plurality of cache portions, the plurality of cache portions comprising at least first through third cache portions; and a cache line placement prediction mechanism for predicting whether a cache line in the first cache portion (a) remains in the first cache portion, (b) migrates from the first cache portion to the second cache portion, or (c) migrates from the first cache portion to the third cache portion; wherein each of the plurality of CPU cores can access data from each of the plurality of cache portions; and wherein the cache line placement prediction mechanism comprises a prediction state for the cache line, the prediction state comprising a x-counter and a y-counter, the x-counter and y-counter indicating two-dimensional coordinates of the non-uniform cache in which the cache line is predicted to be placed.