Patent ID: 9030890
Filing Date: 2015-05-12
Classification: G11C

Abstract:
1. A semiconductor memory apparatus comprising: a sense amplifier driving control unit configured to be applied with a first driving voltage and a second driving voltage which have different voltage levels, and generate a first sense amplifier driving signal, a second sense amplifier driving signal and a third sense amplifier driving signal in response to a mat enable signal, and a sense amplifier enable signal when a power-up signal is disabled; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect a first sense amplifier driving node and a second sense amplifier driving node to cause the first and second sense amplifier driving nodes to have substantially the same voltage level when the third sense amplifier driving signal is enabled, and disconnect the first sense amplifier driving node and the second sense amplifier driving node to apply a first sense amplifier driving voltage to the first sense amplifier driving node and apply a second sense amplifier driving voltage to the second sense amplifier driving node when the first and second sense amplifier driving signals are enabled and the third sense amplifier driving signal is disabled; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages from the first and second sense amplifier driving nodes, and sense and amplify a voltage difference of a bit line and a bit line bar, wherein the sense amplifier driving control unit disables the first and second sense amplifier driving signal and enables the third sense amplifier driving signal when the power-up signal is enabled.