Patent ID: 6136636
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A method for manufacturing a CMOS device on a semiconductor substrate, the method comprising:forming a first oxide layer on said semiconductor substrate to act as a gate oxide;forming an undoped polysilicon layer on said first oxide layer to act as gates of said CMOS;forming a silicon nitride layer on said undoped polysilicon layer to act as an anti-reflective layer;patterning said silicon nitride layer, said undoped polysilicon layer and said first oxide layer to form gate structures on said semiconductor substrate;performing a thermal annealing to recover the etching damage of said semiconductor substrate caused by patterning said gate structures, and simultaneously forming a second oxide layer on the surface of said gate structures and on said semiconductor substrate uncovered by said gate structures;forming a nitrogen doped amorphous silicon layer on said second oxide layer and said gate structures;forming first spacers on sidewalls of said gate structures/said nitrogen doped amorphous silicon layer;removing said nitrogen doped amorphous silicon layer and said second oxide layer that are not covered by said first spacers;removing said first spacers and said silicon nitride layer to expose said residual nitrogen doped amorphous silicon layer and upper surface of said undoped polysilicon layer;performing an ion implantation to dope dopants into said gate structures and said semiconductor substrate, thereby forming source and drain regions in said semiconductor substrate with a spacer separated from said gate structures;performing an oxidation procedure to convert said residual nitrogen doped amorphous silicon layer to a nitrogen doped oxide layer, simultaneously diffusing dopants in said nitrogen doped amorphous silicon layer to said semiconductor substrate, thereby forming extended source and drain junctions adjacent to said gate structures, wherein a third oxide layer is simultaneously formed by said oxidation procedure on exposed surfaces of said substrate and said gate structures;forming second spacers on sidewalls of said gate structures/said nitrogen doped oxide layer;removing said third oxide layer; andforming a self-aligned silicide (SALICIDE) on said semiconductor substrate and a polycide on said gates.