Patent ID: 7979813
Filing Date: 2011-07-12
Classification: G06F,H01L

Abstract:
1. A method for forming an integrated circuit die having bonding pads that are located in positions within a defined grid of candidate positions to form a chip-scale package, the method comprising: providing a die layout, the die layout identifying outer boundaries of the die and areas needed to be electrically connected to bonding pads, the die layout being originally created for other than a chip-scale package, the die using a first set of masks to define all semiconductor regions in the die; providing a grid of candidate positions for the bonding pads; selecting an alignment of the outer boundaries of the die with respect to the grid of candidate positions and identifying positions within the grid of candidate positions for forming bonding pads on the die, where at least portions of the identified positions are within the outer boundaries of the die; producing at least one second mask for patterning the bonding pads on the die corresponding to identified positions within the grid of candidate positions; and fabricating the die using at least the first set of masks, to define all semiconductor regions in the die, and using the at least one second mask, to define the bonding pads, to create a chip-scale package.