Patent ID: 8819322
Filing Date: 2014-08-26
Classification: G06F

Abstract:
1. A system on chip comprising: a plurality of master devices; a plurality of slave devices configured to supply data in response to requests received from the plurality of master devices; and pointer update logic configured to process the requests of the plurality of master devices sequentially in a pipeline manner; wherein the pointer update logic comprises: a flip-flop configured to store a state of a handshake channel and to generate the state of the handshake channel at an output thereof; a temporal register configured to temporarily store a respective payload for each one of the requests; a register slice unit configured to store unique payloads for ones of the outstanding requests; update logic configured to transfer a payload stored in the temporal register to the register slice unit responsive to the state of the handshake channel output from the flip-flop; and a comparator configured to compare a payload corresponding to a currently input request with outstanding payloads stored in the temporal register and the register slice unit.