Patent ID: 6269125
Filing Date: 2001-07-31
Classification: H01Q,H03L,H03M,H04L,H04N

Abstract:
A trellis encoder circuit comprising:receiving means to receive a stream of digital bits;loading means for loading M successive digital bits into a first data register from one of said receiving means and another data register;N successive data registers, each successive data register connected in series with one of said successive data registers and said first data register;means for cycling the digital bits in the last of said N successive data registers into said first data register;first multiplexer means for selecting one of plural sets of digital bits from said last data register;means for trellis encoding said one set of digital bits and providing a trellis encoded set of digital bits; and,logic means for cycling the digital bits in said successive registers until all the digital bits have been trellis encoded and for reloading said successive registers from said stream of digital bits wherein N and M are integers greater than 1.