Patent ID: 6751696
Filing Date: 2004-06-15
Classification: G06F,G11C

Abstract:
A synchronous memory device including an array of memory cells, the synchronous memory device comprises:clock receiver circuitry to receive an external clock signal; input receiver circuitry to sample a first operation code in response to a rising edge transition of the external clock signal; a programmable register to store a value which is representative of an amount of time to transpire before the memory device outputs data, wherein the memory device stores the value in the programmable register in response to the first operation code; and output driver circuitry to output data in response to a second operation code, wherein the data is output after the amount of time transpires, and wherein: the output driver circuitry outputs a first portion of the data synchronously with respect to a rising edge transition of the external clock signal and outputs a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.