Patent ID: 7457992
Filing Date: 2008-11-25
Classification: G01R

Abstract:
1. Delay fault test circuitry for producing a train of two clock pulses in response to two respective clock signals of different frequency associated with logic circuits arranged to run at different speeds, and arranged to align the rising edges of the second clock pulses of the clock signals, the circuitry including: counting means for producing a reference count value; means for initiating the first of the two clock pulses when the said count value reaches a first threshold value; means for ending the first of the two clock pulses when the said count value reaches a second threshold value; means for initiating the second of the two clock pulses when the said count value reaches a third threshold value; means for ending the second of the two clock pulses when the count value reaches a fourth threshold value; wherein the third threshold value is common for both clock signals and the first, second and fourth threshold values are based on the, respective frequencies of the clock signals.