Patent ID: 7349506
Filing Date: 2008-03-25
Classification: G01R

Abstract:
1. A semiconductor integrated circuit comprising a receiver which receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test, the receiver, as a clock data recovery (to be referred to as a CDR hereinafter) circuit, executing control so as to make the phase of the input data coincide with that of the recovery clock by a negative feedback loop having a phase comparator which receives input data and a recovery clock, compares a phase of the input data with that of the recovery clock, and outputs recovery data and a phase comparison result in a serial form, a serial/parallel conversion circuit which receives the phase comparison result, or the phase comparison result and the recovery data from said phase comparator, executes serial/parallel conversion, and outputs the phase comparison result in a parallel form, a digital filter which receives the phase comparison result from said serial/parallel conversion circuit, executes averaging processing for the phase comparison result in a predetermined period, and outputs the phase comparison result, a control circuit which receives the phase comparison result from said digital filter and outputs a control signal to control the phase of the recovery clock, and a phase interpolator which receives the clock signal and generates the recovery clock on the basis of the control signal, and the CDR circuit including a signal output circuit which inputs, to one of said control circuit and said digital filter, a signal to forcibly shift the phase of the recovery data in the negative feedback loop by a predetermined amount, a first counter which counts the number of pulses of the signal output from said signal output circuit in a predetermined period and outputs a first count value, a second counter which counts the number of pulses of the phase comparison result, which has undergone the averaging processing and is output from said digital filter, and outputs a second count value, and a signal processing circuit which receives the first count value and the second count value and compares the first count value with the second count value to determine presence/absence of a capability for absorbing the phase shift generated by the signal.