Patent ID: 6470402
Filing Date: 2002-10-22
Classification: G06F

Abstract:
Process for the transfer of data from N channels, which are sampled in a pre-determined sequence, to a processor by means of a circular FIFO store with n storage stages, while retaining this pre-determined sequence, whereby the output of the last stage is connected to the input of the first stage, comprising the following steps:a) With each write operation of data into the FIFO store, a write pointer (SZ) is set to a value which designates the storage stage into which has been written last; b) with each reading operation of data from the FIFO store (30), a read pointer (LZ) is set to a value which designates the storage stage which is subsequently to be read, whereby the reading process always comprises the reading of data from iÃ—N storage stages, i being an integer and iÃ—Nc) a trigger pointer (TZ) is set to a value jÃ—N, j being an integer, jÃ—Nd) if, after a write process, the value of the write pointer (SZ) is equal to or greater than the value of the trigger pointer (TZ), a read operation is allowed; e) after each read operation the value of the trigger pointer (TZ) is increased by one trigger step (TS) of iÃ—N, and f) when the value of the write pointer (SZ) reaches the value of the read pointer (LZ), the value of the read pointer (LZ) and the value of the trigger pointer (TZ) will be increased by N.