Patent ID: 6091656
Filing Date: 2000-07-18
Classification: G11C,H03K

Abstract:
A semiconductor integrated circuit device comprising:a first main voltage transmission line for transmitting a voltage of a first logic level;a plurality of first sub voltage transmission lines;a plurality of first resistive elements connected between respective ones of said plurality of first sub voltage transmission lines and said first main voltage transmission line;a second main voltage transmission line for transmitting a voltage of a second logic level;a plurality of second sub voltage transmission lines respectively disposed corresponding to said plurality of first sub voltage transmission lines;a plurality of second resistive elements connected between respective ones of said plurality of second sub voltage transmission lines and said second main voltage transmission lines;a plurality of gate circuits divided into a plurality of groups corresponding to respective pairs of said plurality of first sub voltage transmission lines and said plurality of second sub voltage transmission lines, each of the gate circuits operating with both voltages on corresponding first and second sub voltage transmission lines respectively as one operating source voltage and another operating source voltage, each the gate circuit performing a predetermined logic process on a received signal for outputting;a memory array including a plurality of column groups each including a plurality of memory cells arranged in rows and columns, the column groups grouped in correspondence with groups of said sub voltage transmission lines respectively;a plurality of bit line pairs arranged corresponding to the respective columns and connected with memory cells on corresponding columns; anda plurality of equalize/precharge circuits disposed corresponding to the respective bit line pairs, each the equalize/precharge circuit setting each bit line of a corresponding bit line pair to a predetermined voltage level in response to an equalize signal; andwherein each of said plurality of gate circuits is an equalize signal generating circuit for transmitting a voltage of the first logic level on the corresponding first sub voltage transmission line to equalize/precharge circuits in a corresponding column group as an activated equalize signal.