Patent ID: 9118458
Filing Date: 2015-08-25
Classification: G06F,H03K,H04L,H04W,Y02D

Abstract:
1. A method of disabling and enabling clock signals so as to restore a relative phase relationship between them, comprising: receiving a reference clock signal; dividing the reference clock signal by at least a factor of two to generate a master clock signal; generating a first output clock signal from the reference clock signal and synchronously to the master clock signal in a first phase circuit; generating a second output clock signal from the reference clock signal and synchronously to the master clock signal in a second phase circuit, the second output clock signal having a predetermined phase relationship with the first output clock signal; disabling one or more of the first and second phase circuits to suppress generation of the respective output clock signal; and enabling a disabled phase circuit synchronously to the master clock signal, such that after enabling the phase circuit, the predetermined phase relationship between the first and second output clock signals is restored.