Patent ID: 6094381
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of redundancy address program circuits for programming respectively such that a redundancy memory cell in a redundancy memory cell array is selected when an address for selecting a defective memory cell is input, each of said plurality of redundancy address program circuits generating a redundancy selection signal which is made active when an address programmed to each of said plurality of redundancy address program circuits is input; anda control circuit for receiving a redundancy circuit test mode signal for selecting a redundancy memory cell and testing when said test mode signal is made active, thereby determining whether said selected redundancy memory cell is defective before said redundancy address program circuit is programmed, said control circuit generating a portion of an input address as a portion of the address of said redundancy memory cell when said test mode signal is in said active state and generating signals produced from said redundancy selection signals as said portion of the address of a redundancy memory cell when said test mode signal is in an inactive state.