Patent ID: 9058998
Filing Date: 2015-06-16
Classification: H01L,H03K

Abstract:
1. A semiconductor integrated circuit comprising: a pad connected to receive an input signal having a high level or a low level; an internal circuit; a power supply line; a ground line; a filter resistor; a protection resistor; a first line that connects a first terminal of the filter resistor and the pad; a second line that connects a second terminal of the filter resistor and a first terminal of the protection resistor; a third line that connects a second terminal of the protection resistor and the internal circuit; a first protection element including a first transistor configured as an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) designed so as to withstand ESD, wherein the first transistor has its drain connected to the first line, and has its source, its gate, and its back gate connected to the ground line; a second protection element including a second transistor configured as a P-channel MOSFET designed so as to withstand ESD, wherein the second transistor has its drain connected to the first line, and has its source, its gate, and its back gate connected to the power supply line; and a capacitance element coupled to the second line so as to form an RC filter together with the filter resistor, wherein the capacitance element includes at least one of a third transistor and a fourth transistor, and the third transistor is configured as an N-channel MOSFET having the same device structure as that of the first transistor, and the fourth transistor is configured as a P-channel MOSFET having the same device structure as that of the second transistor.