Patent ID: 6613646
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A method for fabricating an isolation structure in a semiconductor wafer, comprising:forming a nitride layer to a thickness of about 100 Ã¥ or more and about 500 Ã¥ or less over a semiconductor substrate; forming at least one trench through the nitride layer and into an isolation region in the semiconductor substrate; forming an electrically isolating material over the semiconductor substrate, the electrically isolating material covering the nitride layer in at least one active region in the semiconductor substrate and filling the at least one trench; planarizing the electrically isolating material using a substantially self-stopping material removal process to expose a portion of the nitride layer in the at least one active region, and to provide a substantially planar top surface comprising the exposed portion of the nitride layer and a remaining portion of the electrically isolating material in the at least one trench, the remaining portion of the electrically isolating material forming an isolation structure in the at least one trench; removing the remaining nitride layer; and removing a portion of the nitride layer after the step of forming the at least one trench and before the step of forming the electrically isolating material.