Patent ID: 7911026
Filing Date: 2011-03-22
Classification: H01L,H05K

Abstract:
1. A carrier for microelectronic devices and/or circuits comprising: a substrate having a first interface with a plurality of first contact holes, a second interface, which essentially lies opposite the first interface, with a plurality of second contact holes, a substrate body, and a plurality of electrically conductive contact channels formed in the substrate body, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole; and at least one front-side wiring layer arranged on the first interface and having formed therein at least one first front-side metallization layer at least partly comprising a first capacitor electrode configured to electrically connect the microelectronic devices and/or circuits to a first pole of a signal or supply voltage; and a rear-side wiring layer arranged at the second interface and having formed therein at least one first rear-side metallization layer which at least partly comprises a second capacitor electrode, wherein the first capacitor electrode and/or the second capacitor electrode comprises a plurality of first and/or second capacitor fingers, respectively, formed by a plurality of the contact channels which are electrically conductively connected to the first front-side metallization layer and/or the first rear-side metallization layer, respectively, wherein the first front-side metallization layer and/or the first rear-side metallization layer are/is spaced apart from the first and/or second interface, respectively, at least in regions by a capacitor dielectric, and wherein the first capacitor electrode, at least partly via the capacitor dielectric formed in the carrier and/or via electrically conductive regions of the substrate, couples capacitively to the second capacitor electrode which electrically connects the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.