Patent ID: 6605843
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A fully depleted field effect transistor with a wide gate cap formed on a silicon on insulator substrate including a thin silicon device layer positioned over an insulating layer, the field effect transistor comprising:an active region formed in the silicon device layer and including a source region and a drain region of a first conductivity type on opposing sides of a central channel region of a second conductivity type, wherein said second conductivity type is opposite to said first conductivity type, and each of said source and drain regions has a lightly doped region and a heavily doped region; a gate oxide layer extending over the top surface of the active region; a base gate layer formed on the gate oxide layer and above the central channel region, wherein the base gate layer being formed of a semiconductor material and having a top surface, a first side surface and a second side surface opposing said first side surface; a first insulating layer formed on the gate oxide layer and over said source and drain regions, wherein said first insulating layer is adjacent to the first and second side surfaces of said base gate layer and has a top surface at a level lower than the top surface of the base gate layer; the wide gate cap is formed on and electrically connected to the base gate layer, wherein the wide gate cap is formed of a metal and has a middle portion covering the top surface of the base gate layer and two side portions in contact with a portion of the top surface of the first insulating layer and respectively covering top portions of the first and second side surfaces of the base gate layer; and contact openings formed in said first insulating layer and extending to said source and drain regions, respectively, wherein the central channel region is of a full-depletion type and has an upper channel region adjacent the base gate layer and a lower channel region beneath the upper channel; said upper channel region is positioned between and abutting the lightly doped regions of the source and drain regions and has a width approximately equal to or less than that of the base gate layer, said lower channel region is positioned between and abutting the heavily doped regions of said source and drain regions and has a width approximately equal to that of the wide gate cap.