Patent ID: 8190954
Filing Date: 2012-05-29
Classification: G01R

Abstract:
1. A semiconductor integrated circuit comprising: A. functional logic formed on a substrate, the functional logic including functional flip-flops; B. a test input bus of leads including a stimulus data input lead, a control input lead, and an enable input lead; C. scan paths, each scan path including functional flip-flops of the functional logic that, in a test mode, are connected in series, each scan path including a stimulus data input coupled to the stimulus data input lead, stimulus connections with the functional logic, response connections with the functional logic, a response data output, and a control input; D. gating circuitry having a first input connected to the control input lead, second inputs, and an output for each second input, each output being connected to the control input of a scan path; and E. control circuitry having an input connected to the control input lead, an input connected to the enable lead, and having scan path control outputs, each scan path control output being connected to one of the second inputs of the gating circuitry, and the control circuitry in response to receiving one enable signal coupling the scan paths in series between the stimulus data input lead and the response data output lead and in response to receiving another enable signal selectively coupling only one of the scan paths between the stimulus data input lead and the response data output lead.