Patent ID: 6323705
Filing Date: 2001-11-27
Classification: G11C,H03L

Abstract:
A delay lock loop circuit for a synchronous memory system comprising:a first path including a first adjustable delay unit circuit for receiving an external clock signal and generating an output clock signal which corresponds to the external clock signal delayed by a delay time provided by a first delay unit circuit;a feedback path including a phase detector and a register, the phase detector for detecting the phase difference between the external clock signal and a feedback clock signal corresponding to the generated output clock signal, the register for storing a delay value for controlling the first delay unit circuit and determining the delay time, the phase detector generating control signals dependent on the detected phase difference, the control signals for controlling the register to adjust the delay value stored in the register to obtain a desired delay value wherein no phase difference is detected;a controller for providing a control signal having a first enable state and a second disable state;a second delay unit circuit including a plurality of individual delay elements each having its enable/disable port coupled to the control signal, a first delay element of the plurality of elements having its input coupled to a fixed voltage corresponding to a first logic state;wherein, upon system start-up and when the control signal is switched from its disable state to its enable state in response to the rising edge of the first cycle of the feedback clock signal, the individual delay elements are enabled causing the fixed voltage to begin to propagate through the plurality of the individual delay elements; andwhen the control signal is switched to its disable state in response to the rising edge of the second cycle of the external clock signal occurring subsequent to the rising edge of the first cycle of the feedback clock signal the plurality of individual delay elements are disabled causing the desired delay value to be established on the output of the second delay unit circuit;wherein, the second delay unit circuit is used to pre-set the register with the desired delay value.