Patent ID: 8785279
Filing Date: 2014-07-22
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: a) providing a semiconductor substrate of a first conductivity type; b) forming an epitaxial layer of the first conductivity type on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped; c) forming body regions of a second conductivity type that is opposite of the first conductivity type near the top surface of the surface shielded region; d) forming source regions of the first conductivity type near the top surface of the surface shielded region; e) forming a plurality of gates on the top surface of the surface shielded region; f) forming a drain on a bottom surface of the semiconductor substrate; g) forming a plurality of trenches in the surface shielded region, wherein the trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material configured to be in electrical contact with a source electrode on top of the surface shielded region and in electrical contact with the source region; h) forming a plurality of buried doped regions of the second conductivity type, whereby each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region; and i) forming one or more charge linking paths of the second conductivity type along one or more trench walls of the plurality of trenches and configured to electrically connect a buried doped region to the body region.