Patent ID: 7183819
Filing Date: 2007-02-27
Classification: G06F

Abstract:
1. A method for synchronous resetting of a multiple clock domain integrated circuit, comprising: forming a clocked reset tree comprising a first synchronous logic element and at least one branched synchronous logic element, each branched synchronous logic element being synchronized using a crock signal of a respective clock domain of the integrated circuit; synchronizing the first synchronous logic element using a first clock signal of the integrated circuit; coupling an output of the first synchronous logic element to a data input of the at least one branched synchronous logic element; and coupling an output of each of the at least one branched synchronous logic element with data inputs of synchronous logic elements of the respective clock domain; the first and the at least one branched synchronous logic elements being reset in response to a reset signal applied to a data input of said first synchronous logic element.