Patent ID: 7221198
Filing Date: 2007-05-22
Classification: G06F

Abstract:
1. An interface circuit comprising: an address register that serially reads in an address code synchronously with a clock signal; an address decoder configured to output a decode output indicative of whether said address code inputted in said address register matches a predetermined address code; a hold circuit that holds decode output of said address decoder due to a control signal changing from one level to the other level; a data output circuit, in response to decode output indicating that said address code inputted in said address register matches the predetermined address code and being held in said hold circuit, outputting data, subsequent to said address code, to a data register that serially reads in said data synchronously with said clock signal; and a clock output circuit, in response to the decode output indicating that said address code inputted in said address register matches the predetermined address code and being held in said hold circuit and to said control signal being at the other level, outputting said clock signal to said data register, said clock output circuit further comprising: