Patent ID: 6310453
Filing Date: 2001-10-30
Classification: F04D,Y02B

Abstract:
A drive circuit for a speed adjustable fan, comprising:a computing integrated circuit (IC2) with a plurality or connecting pins;a Hall integrated circuit (IC1), being connected to the computing integrated circuit (IC2);a signal input terminal of pulse width modulation (PWM), being connected to the computing integrated circuit (IC2);a control circuit (10), being connected to the signal input terminal and being composed of a NPN transistor (Q4) and a resistor (R5);a first coil (V1), being connected to the computing integrated circuit (IC2) via a first transistor (Q1);a second coil (V2), being connecting to the computing integrated circuit (IC2) via a second transistor (Q2);characterized in that the signal input terminal is connected to the computing integrated circuit (IC2) via a third transistor (Q3) and a resistor (R7) such that a base pole of the third transistor (Q3) connecting with the signal input terminal through the resistor (R7), a collector of the third transistor (Q3) is connected to the computing IC (IC2).