Patent ID: 6415401
Filing Date: 2002-07-02
Classification: G01R

Abstract:
An integrated circuit including a first internal circuit using a first internal clock signal whose first edges are active, said first internal circuit comprising:a test cell having an input and an output; a first transmission line connected to the input of the test cell; and a second transmission line connected to the output of the test cell, wherein the test cell includes: a first latch for storing either information on the first transmission line or information received from another test cell; a second latch selectively receiving the information stored in the first latch; a selection circuit that provides to the second transmission line either the information on the first transmission line or the information stored in the second latch, the selection circuit operating based on a state bit; and means for storing the information on the first transmission line in the second latch during second edges of the first internal clock signal when the test cell is not in test mode.