Patent ID: 7915172
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming a first layered structure on a base layer in an element area of a wafer, the element area being delineated by a non-element area, the first layered structure including first upper and lower conductive layers; covering the first layered structure with a first insulating film that exhibits a first etching rate with respect to an etching recipe; covering the first layered structure, being covered by the first insulating film, with a second insulating film that exhibits a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate; forming first aperture portions in the second insulating film in a manner exposing the first upper and lower conductive layers of the first layered structure; forming conductive plugs in the first aperture portions; forming a second layered structure in the non-element area simultaneously with the forming of the first layered structure, the second layered structure including at least a portion of the first layered structure and including second upper and lower conductive layers; forming a second aperture portion simultaneously with the forming of the first aperture portions in a manner exposing the second upper conductive layer of the second layered structure; and forming a conductive pattern, simultaneously with the forming of the conductive plugs, in the second aperture portion; wherein the first insulating film is not formed in the second layered structure, and performing a mask alignment process using the second layered structure as an alignment mark pattern to form the first aperture portion and the second aperture portion simultaneously.