Patent ID: 6584514
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A digital signal processing unit comprising:a core processing unit, the core processing unit processing signal groups; at least one memory unit, the memory unit storing signal groups processed and to be processed by the memory unit; at least one serial port, the serial port exchanging signal groups between the signal processing unit and apparatus external to the digital signal processing unit; and a direct memory access controller, the direct memory access controller controlling the transfer of signal groups between the core processing unit, the memory unit and the serial port, the direct memory access controller including an address unit, the address unit including: a first multiplexer unit responsive to control signals for selecting one of a plurality of offset signal in response to control signals; an index unit responsive to mode determination control signals and to address signals for determining a base address and a previous address index; an adder unit for combining the output signal from multiplex unit and the address index to provide a new address index; a first and a second adder unit responsive to the output signal of the adder unit and a buffer size for determining a positive wrap signal and a negative wrap signal; second multiplexer having the output signals from the adder unit, the first adder unit and the second adder unit applied to input terminals thereof, the second multiplexer selecting an address index; and a combining unit for combining the address index and the base address to form a new address signal group.