Patent ID: 7269712
Filing Date: 2007-09-11
Classification: G06F

Abstract:
1. A multi-threaded processor, comprising: a processing pipeline including a number of stages, each stage processing at least one instruction, each instruction belonging to one of a plurality of threads; and a fetch unit forming one of the stages of the pipeline and determining from which of the plurality of threads to fetch an instruction for processing by the processing pipeline, the fetch unit receiving information from at least one other stage of the processing pipeline and determining a processing time of the processing pipeline occupied by each of the plurality of threads based on the received information, the fetch unit determining from which of the plurality of threads to fetch the instruction for processing by the processing pipeline based on the determined processing time for each of the plurality of threads, wherein the fetch unit generates a weighted instruction count for each of the plurality of threads, the weighted instruction count for each of the plurality of threads is a count of instructions for each of the plurality of threads weighted by cycle counts associated with processing the instructions for each of the plurality of threads.