Patent ID: 6144592
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells;a redundant memory cell array configured to replace a part of the memory cell array, the redundant memory cell array having a plurality of memory cells;an internal address signal generation circuit for generating an internal address signal for accessing the memory cell array, in response to an address signal supplied from outside;a defective address storage circuit for storing a defective address signal for replacing the part of the memory cell array;a first address comparison circuit for comparing the internal address signal generated from the internal address signal generation circuit and the defective address signal stored in the defective address storage circuit; anda redundant memory test circuit for testing the redundant memory cell array, the redundant memory test circuit holding an address signal of the memory cell array, and setting the memory cell array in a nonselective state and setting the redundant memory cell array in a selective state when the address signal held in the redundant memory test circuit and the internal address signal generated from the internal address signal generation circuit coincide with each other.