Patent ID: 8030159
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A method of fabricating, on a semiconductor substrate, an EEPROM for forming a memory cell transistor and a selection transistor that is a component of the memory cell transistor and the EEPROM, the method comprising: forming a first source region and a first drain region of the memory cell transistor on the semiconductor substrate; forming a first gate oxide film on the semiconductor substrate; forming a resist having at least one through hole on the first gate oxide film formed on the first drain region; adding conductivity type impurities to the semiconductor substrate, on which the resist is formed, through the through hole; partially removing the first gate oxide film using the resist as an etching mask to form a tunnel oxide film in a region corresponding to the through hole; forming a floating gate electrode, which covers the tunnel oxide film and parts of the first source region and the first drain region, and a second gate oxide film formed on the floating gate electrode; forming a control gate electrode on the second gate oxide film, and forming a selection transistor gate electrode on the first gate oxide film and at a region in which the selection transistor is formed; and forming a second source region and a second drain region of the selection transistor on the semiconductor substrate, wherein the first drain region is connected to the second source region by partial overlapping.