Patent ID: 6133759
Filing Date: 2000-10-17
Classification: H03K

Abstract:
A dynamic logic circuit comprising:a first N-tree logic circuit adapted for receiving a first plurality of logical input signals and generating an output in response thereto;a first P-tree logic circuit adapted for receiving a second plurality of logical input signals and generating an output in response thereto, said first P-tree logic circuit having an output coupled to said output of said first N-tree logic circuit;a p-type field effect transistor (PFET) device having a gate coupled to said output of said first N-tree and P-tree logic circuits, and a drain coupled to a first voltage supply;an first n-type field effect transistor (NFET) device having a drain coupled to a source of said PFET device, and a source coupled to a second voltage supply;a second N-tree logic circuit adapted for receiving a third plurality of third logical input signals and generating an output in response thereto, said output of said second N-tree logic circuit being coupled to a gate of said first NFET device; anda second P-tree logic circuit adapted for receiving a fourth plurality of logical input signals and generating an output in response thereto, said output being coupled to said gate of said first NFET, and wherein said output of said second N-tree logic circuit and said second P-tree logic circuit are operable for resetting said output of said dynamic logic circuit.