Patent ID: 7028206
Filing Date: 2006-04-11
Classification: G06F

Abstract:
1. A circuit for generating a local clock signal synchronized to an externally generated reference clock signal, comprising: an input node for receiving the reference clock signal, an output node for conveying the local clock signal, a plurality of delay lines in series, forming a signal path for conveying a clock signal from the input node to the output node, each of the delay lines having means including a plurality of delay elements coupled in series, a counter, a count bus, and a plurality of decoders, one of the decoders being disposed with each one of the delay elements, for delaying the clock signal by an individually adjustable line-delay, and at least one of the delay lines has a phase detector for adjusting its line-delay, and at least one of the delay lines is a wrap controller delay line, the wrap controller delay line being directly followed in the signal path by a wrap follower delay line, the wrap follower delay line having means including a phase detector for adjusting the counter of the wrap follower delay line when the counter of the wrap follower delay line is not at an end of counting range, the wrap controller delay line having means including a wrap control for adjusting the counter of the wrap controller delay line and the counter of the wrap follower delay line such that when the counter of the wrap follower delay line is substantially at a minimum end of count range, the wrap control decreases the line-delay of the wrap controller delay line and increases the line-delay of the wrap follower delay line, such that a sum of the line-delays of the wrap controller delay line and the wrap follower delay line is substantially unchanged, and when the counter of the wrap follower delay line is substantially at a maximum end of count range, the wrap control increases the line-delay of the wrap controller delay line and decreases the line-delay of the wrap follower delay line such that the sum of the line-delays of the wrap controller delay line and the wrap follower delay line is substantially unchanged.