Patent ID: 6331492
Filing Date: 2001-12-18
Classification: H01L,Y10S

Abstract:
A method of making gate oxides on a silicon wafer surface for multiple voltage applications, comprising the steps of:forming a first oxide layer on at least first and second exposed areas of a silicon wafer surface to provide first and second exposed oxide areas;converting a top layer of each of said first and second exposed oxide areas into first and second nitrided layer by exposing said first and second oxide areas to a nitrogen ion-containing plasma;patterning a layer of photoresist over said oxide areas and said first nitrided layer on said one of said oxide areas;etching areas of the oxide layer and the nitrided layer thereover which are not beneath the pattern of photoresist in accordance with said pattern;then stripping said photoresist;then etching the remaining oxide from said second area to expose the wafer surface of said second area; andoxidizing said exposed second area to grow a second oxide layer thicker than said first oxide layer.