Patent ID: 8321829
Filing Date: 2012-11-27
Classification: G06F,H01L

Abstract:
1. An interconnection design method for a multilayer interconnection substrate comprising a power supply layer or a ground layer, interconnection layers comprising interconnections, and vias connecting the interconnection layers mutually, the interconnection design method comprising: selecting an interconnection for a predetermined signal by a computer; determining an approximate arrangement of vias by a computer, the vias comprising a first via through an opening provided in the power supply layer or the ground layer, the first via conducting signals; changing positions of the vias and obtaining approximate interconnection routes in respective approximate arrangement of the vias, defining an evaluation region comprising an interconnection, and evaluating respective interconnectivity of the evaluation region by a computer; and obtaining a detailed interconnection route based on a result of the evaluation of the interconnectivity by a computer; wherein the interconnections comprise the selected interconnection between adjacent first vias, the defining the evaluation region comprises setting a position of a side of the evaluation region so as to correspond to a position of an edge of the selected interconnection, and further comprises setting the position of the side of the evaluation region into a position associated with an edge of the opening, and the interconnectivity of the evaluation region is evaluated based on the number of interconnections between the vias and the number of possible interconnections determined based on a design rule.