Patent ID: 6438188
Filing Date: 2002-08-20
Classification: H03L,H04J

Abstract:
An apparatus for matching the phase of an input clock and output clock comprising:a digitally controlled constant current source, a phase lock loop circuit coupled to the digitally controlled constant current source, wherein the digitally controlled constant source outputs an adjustment current proportional to a phase difference of an input clock signal and an output clock signal and the phase look loop circuit is operable to use the adjustment current to match the phase of the input clock signal and the output clock signal; wherein the digitally controlled constant current source comprises: a phase indicator operable to receive a reference clock signal and a delayed clock signal based on the output clock signal and determine a phase difference; a microprocessor operable to output a digital value related to the phase difference; a digital-to-analog converter coupled to the microprocessor and operable to convert the digital value to an analog value; and a voltage controlled constant current source operable to receive the analog value and output the adjustment current proportional to the analog value.