Patent ID: 6316287
Filing Date: 2001-11-13
Classification: H01L,Y10S

Abstract:
A process of fabricating a semiconductor device package comprising:providing a semiconductor wafer having a front side and a back side and comprising a plurality of dice separated by scribe lines, each die comprising a semiconductor device, a surface of a front side of a die comprising a passivation layer and at least one connection pad in electrical contact with the semiconductor device;forming a first metal layer in electrical contact with the at least one connection pad, a portion of the first metal layer extending laterally beyond an edge of the die;attaching a cap to the front side of the wafer;cutting through the semiconductor wafer from the back side of the wafer in the scribe line area to form a first cut, the first cut having a first kerf W1 and exposing a part of the first metal layer;forming a nonconductive layer on at least a portion of the back side of the die;forming a second metal layer, the second metal layer being in electrical contact with the first metal layer and having a first section extending over the nonconductive layer; andcutting through the cap in the scribe line area to form a second cut having a second kerf W2 that is less than the first kerf W1, the second cut leaving in place an area of contact between the first and second metal layers.