Patent ID: 8797424
Filing Date: 2014-08-05
Classification: H04N

Abstract:
1. An image processing apparatus comprising: a memory; a data bus which provides access to the memory; an image conversion unit which receives an image signal and converts the image signal into a frame comprising a plurality of lines; and an image compression/decompression unit which divides the frame into a plurality of line groups, compresses each of the plurality of line groups to generate compressed data, and stores the compressed data in the memory via the data bus, wherein at least one line in at least one line group from the plurality of line groups is omitted from the compression by the image compression/decompression unit, wherein each of the plurality of line groups comprises one first line that maintains an original uncompressed state, and a plurality of second lines that are compressed at a predetermined compression rate by the image compression/decompression unit, wherein the first line is arranged before the second lines in the frame, and wherein the first line maintains the original uncompressed state regardless of the complexity of the first line.