Patent ID: 9136164
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method for forming a semiconductor device, comprising: providing a substrate comprising a first region and a second region; providing first metal layers in the first region and the second region of the substrate, wherein the first metal layers have a top surface coplanar with a top surface of the substrate; forming an interlayer dielectric layer over the substrate, wherein the interlayer dielectric layer comprises a trench in the first region, and the interlayer dielectric layer in the second region has a top surface coplanar with a bottom of the trench in the first region; forming through-holes in the interlayer dielectric layer, each through-hole corresponding to one first metal layer in the first region and the second region; forming a polymer layer to fill the through-holes and the trench in the interlayer dielectric layer and to cover the top surface of the interlayer dielectric layer in the first and second regions, wherein the polymer layer has a different solubility in an exposed area and in a non-exposed area; exposing and developing the polymer layer to form vias, each including an upper via in the polymer layer and a lower via in the interlayer dielectric layer, wherein each via is formed on a corresponding first metal layer in the first and second regions; forming a second metal layer to fill each via and to electrically connect to the corresponding first metal layer; and removing the polymer layer between adjacent second metal layers to form air gaps between the adjacent second metal layers in the second region.