Patent ID: 6172659
Filing Date: 2001-01-09
Classification: G09G,H04N

Abstract:
An apparatus for interfacing L pixel data corresponding to 1 line inputted from a memory section to an upper and a lower address electrode driving section, respectively, in response to a control signal supplied from a timing control section, said apparatus comprising:an upper and a lower data interfacing section, and an input/output control section;wherein each of said upper and said lower data interfacing sections comprises:a couple of temporality storing sections comprising a storing area for temporarily storing L/2 pixel data;an input selecting means for inputting 3N pixel data into said storing area over M (where M is a least integer which is greater than a quotient of L divided by 3N) times in response to M input selecting control signals which are sequentially generated; andan output selecting means for outputting the L/2 pixel data stored in said storing area by P units over Q {=(L/2)/P} times in response to Q output selecting control signals which are sequentially generated;wherein L, M, N, P, and Q are integers;wherein said input/output control section comprises:a first control signal generating section for receiving a first clock signal and a first reference signal from said timing control section and for generating the M input selecting control signals by shifting the first reference signal over M times in response to the first clock signal;a second control signal generating section for receiving a second clock signal and a second reference signal from said timing control section and for generating the Q output selecting control signals by shifting the second reference signal over Q times in response to the second clock signal; andan operation mode control section for supplying the control signal from said first and said second control signal generating sections to said couple of temporality storing sections for a data input/output mode to be alternately executed in said couple of temporality storing sections in response to an input/output mode control signal.