Patent ID: 7715236
Filing Date: 2010-05-11
Classification: G06F,G11C

Abstract:
1. A device comprising a memory circuit operable to store a value for use by another circuit of the device, the memory circuit comprising: a memory block comprising a plurality of sets of NVM memory cells, wherein each set of NVM memory cells comprises a plurality of data NVM cells and a parity NVM cell; a sense amplifier circuit operable to read data stored in the memory block, wherein in reading a first data NVM cell of a first set of NVM memory cells of the memory block the sense amplifier circuit is to obtain first and second values using first and second thresholds, respectively, and wherein the sense amplifier circuit includes a first sense amplifier coupled to receive the first threshold to obtain the first value, and a second sense amplifier coupled to receive the second threshold to obtain the second value; and a logic circuit operable to indicate a fault in the first data NVM cell in response to the first and second values being inconsistent.