Patent ID: 9123627
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A method, comprising: forming a plurality of trenches in a semiconductor substrate to thereby define a fin having an upper surface; forming a layer of insulating material in said trenches such that the upper surface of said fin is exposed; performing at least one etching process to remove at least a portion of said fin and thereby define a fin trench in said layer of insulating material; forming a first layer of semiconductor material in said fin trench, said first layer of semiconductor material having an upper surface that is positioned below an upper surface of said layer of insulating material; forming a second layer of semiconductor material in said fin trench on said upper surface of said first layer of semiconductor material, said second layer of semiconductor material having an upper surface that is positioned below said upper surface of said layer of insulating material; after forming said second layer of semiconductor material, performing an anneal process to induce defect formation in at least said first layer of semiconductor material, wherein, after said anneal process is performed, said upper surface of said second layer of semiconductor material is substantially defect-free; forming a layer of channel semiconductor material on said upper surface of said second layer of semiconductor material; and forming a gate structure around at least a portion of said channel semiconductor material.