Patent ID: 7539033
Filing Date: 2009-05-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first input/output circuit and a second input/output circuit which are disposed adjacent to each other in a first direction and include a pad corresponding to an external terminal; a first memory mat and a second memory mat which correspond to the first and second input/output circuits and are disposed in a second direction perpendicular to the first direction; and a word line selection circuit which is disposed between the first memory mat and the second memory mat, and generates a signal for selecting a word line common to the first memory mat and the second memory mat, wherein the first memory mat and the second memory mat each include first to fourth memory blocks having a common word line selected by the word line selection circuit, wherein memory cells in the first and second memory blocks can be accessed, including a burst operation, by the first input/output circuit, and wherein memory cells in the third and fourth memory blocks can be accessed, including a burst operation, by the second input/output circuit.