Patent ID: 8885409
Filing Date: 2014-11-11
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: an array of nonvolatile memory cells; a plurality of page buffers configured to receive a corresponding plurality of pages of data read from a target page of nonvolatile memory cells in said array using different read voltage conditions for each of the plurality of pages of data being read; a control circuit electrically coupled to said plurality of page buffers, said control circuit configured to perform a test operation by driving said plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits that are derived from at least two of the plurality of pages of data read from the target page of the nonvolatile memory cells using the different read voltage conditions; and an input/output device configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device; and wherein the test operation comprises: