Patent ID: 6968354
Filing Date: 2005-11-22
Classification: G06F

Abstract:
1. A tamper-resistant modular multiplication method for decreasing the relationship between data processing and consumption current therefor in an information-processing device which includes an input/output port communicating with an external device, a memory device for storing both programs and data, a central processing unit executing the data processing in accordance with said programs, and a bus connecting among the input/output port, the memory device and the central processing unit, when calculating a modular multiplication, A*B*R^(−1) mod N, which appears during performing crypto-processing as the data processing, said method comprising the steps of: (1) selecting either of the following steps (2) and (3) at random; (2) calculating S (3) calculating S (4) repeating the above-mentioned steps (1), (2), (3) for each bit block consisting of the data, wherein finally when the step (2) is selected for a last bit block of the data, for a calculation result S (5) using T