Patent ID: 6370125
Filing Date: 2002-04-09
Classification: H04J,H04L

Abstract:
For use with a digitized packet-based transmission network, having a packet buffer into which packets received from said network are buffered and controllably read out for application to a digitized packet signal processor, a method of controlling packet delay through said packet buffer, said method comprising the steps of:(a) establishing a nominal buffer delay through said packet buffer for packets received from said network, and maintaining said nominal buffer delay in the absence of an increase in delay in receipt of packets from said network; (b) in response to an increase in delay in receipt of packets from said network, increasing buffer delay to an increased buffer delay value corresponding to said increase in delay, and thereafter maintaining said increased buffer delay value in the absence of a further increase in delay in receipt of packets from said network; and (c) repeating step (b) as necessary for any further increase in delay in receipt of packets from said network, so as to maintain the value of buffer delay at a value associated with maximum encountered transport delay through said network.