Patent ID: 6628112
Filing Date: 2003-09-30
Classification: H03L,H04L

Abstract:
A phase detection circuit comprising:a first section configured to generate a first output signal from an input signal on a first clock edge and to generate a second output signal from the input signal on a second clock edge; a second section, coupled with the first section, the second section configured to generate a third output signal from the first output signal on the first clock edge and to generate a fourth output signal from the second output signal on the second clock edge; a third section, coupled with the first section and the second section, the third section configured to compare the input signal and the first output signal and to generate a first phase detection signal based on the comparison; and a fourth section, coupled with the second section, the fourth section configured to compare the third output signal and the fourth output signal and to generate a second phase detection signal based on the comparison.