Patent ID: 6253310
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A method of delaying the deallocation an arithmetic flags register, the method comprising: determining if an instruction updates the arithmetic flags register; deallocating a previous physical register assigned to a logical destination register for the instruction if the instruction updates the arithmetic flags register;determining if the instruction deallocates a physical register containing the arithmetic flags when the value of the arithmetic flags is unaffected by the instruction;deallocating a previous physical register assigned to a logical destination register for the instruction if the instruction deallocates a physical register other than the physical register containing the arithmetic flags when the value of the arithmetic flags is unaffected by the instruction; anddelaying deallocation of the physical register containing the arithmetic flags if the value of the arithmetic flags is unaffected by the instruction and the instruction deallocates the physical register containing the arithmetic flags wherein delaying deallocation of the previous physical register preserves the arithmetic flags.