Patent ID: 6087252
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A dual damascene process, comprising:providing a substrate;forming a conductive line on the substrate;forming a dielectric layer over the substrate to cover the conductive line;sequentially forming a first mask layer and a cap oxide layer on the substrate;defining the cap oxide layer to form an opening to expose a part of the first mask layer wherein the opening is positioned over the substrate in an area where a via hole is to be subsequently formed;forming a conformal second mask layer along the opening and on the cap oxide layer;removing a part of the second mask layer to form a spacer on sidewalls of the first opening wherein a part of the first mask layer at a bottom of the opening is simultaneously removed to expose a part of the dielectric layer;forming a photoresist layer with an interconnect pattern on the cap oxide layer;anisotropically etching the cap oxide layer and a part of the dielectric layer to form the via hole in the dielectric to expose a part of the conductive line using the photoresist layer and the spacer as a mask and with the first mask layer serving as an etching end point;removing the photoresist layer;removing the spacer and the first mask layer exposed by the cap oxide layer to form a horizontal trench using the dielectric layer as an end point; andforming a conductive layer in the via hole and the horizontal trench.