Patent ID: 7985697
Filing Date: 2011-07-26
Classification: B81B,B81C,H01L

Abstract:
1. A method of fabricating a wafer level package, comprising: forming a first Input/Output (I/O) pad electrically connected with a first internal device on a first substrate having a cavity in which the first internal device is disposed; forming a hole at a part corresponding to the first I/O pad in a second substrate disposed over the first substrate; forming a solder on the first and second substrates; aligning the first and second substrates; bonding the first and second substrates using the solder; forming a second internal device on an upper region of the second substrate corresponding to a place of the first internal device; forming a second I/O pad on the second internal device; cutting device separation regions of the first and second substrates using a sawing blade and forming a plurality of individual wafer level package devices to be separated from each other; mounting the individual wafer level package device on a Printed Circuit Board (PCB) having an I/O terminal; and connecting the first I/O pad and the second I/O pad with the I/O terminal by wire bonding.