Patent ID: 7037759
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor package, comprising the following steps of: providing a wafer defining an active surface and a backside and having a plurality of semiconductor chips each having a plurality of bonding pads disposed on the active surface, and a plurality of scribe lines disposed between the chips; forming a plurality of metal extension traces on the active surface of the wafer and electrically connecting the metal extension traces to the bonding pads; covering the active surface of the wafer with a lid; forming a plurality of notches along the scribe lines and exposing the metal extension traces; covering the backside of the semiconductor chip with a passivation layer and disposing the passivation layer between the adjacent metal extension traces in the notches, while leaving said metal extension traces exposed in the notches; filling up the notches with conductive pastes being electrically connected to the metal extension traces; and singulating the wafer.