Patent ID: 6733615
Filing Date: 2004-05-11
Classification: B24B,B24D

Abstract:
An apparatus for preparation and use of a polishing substrate comprising:a substrate having a predetermined three-dimensional pattern formed on a surface thereof, with individual patterns of the three-dimensional pattern having a maximum height of about 20 &mgr;m to about 50 &mgr;m and a maximum width of about 100 &mgr;m to about 1000 &mgr;m; a coating layer coated on substantially the entirely of the surface of the substrate; a vacuum deposition chamber, configured to receive the substrate and in which the coating layer is applied to the surface of the substrate; and a chemical-mechanical polishing chamber disposed downstream from the vacuum deposition chamber and configured to receive both the coated substrate and a semiconductor wafer, the chemical-mechanical polishing chamber configured to planarize the semiconductor wafer.