Patent ID: 6624466
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A split-gate flash memory cell pair with rectangular silicon nitride spacers comprising:a substrate having active and field regions defined; said active regions comprising pair wise common source regions, said split-gate flash memory cell pair sharing said common source region; a pair of floating gates overlying but separated from said substrate by a gate oxide, said pair of floating gates having vertical wails; a dielectric layer conforming to said floating gates and said substrate; said dielectric layer having vertical walls corresponding to the vertical walls of said pair of floating gates, said interpoly dielectric layer comprising high temperature oxide; rectangular silicon nitride spacers formed on the vertical walls of the dielectric layer; said rectangular silicon nitride spacers having a width between about 50 to 100 Ã¥: said rectangular silicon nitride spacers having a height between about 200 to 800 Ã¥; and a pair of control gates disposed over said pair of floating gates.