Patent ID: 8751978
Filing Date: 2014-06-10
Classification: G03F

Abstract:
1. A method for balancing mask loading within a semiconductor processing environment, comprising: receiving a mask layout associated with one or more masks, the mask layout comprising one or more polygons, a first polygon of the one or more polygons comprising a mask assignment to a first mask of the one or more masks; creating a first window comprising a first window size less than a mask size of the mask layout, the first window at a first location in the mask layout; creating a first halo comprising a first halo size of at least the first window size, the first halo at the first location in the mask layout; determining a first polygon area corresponding to the first mask based on a portion of the first polygon encompassed by the first halo; assigning a first dummy mask assignment to a first dummy of one or more dummies in the mask layout based on the first polygon area, the first dummy mask assignment comprising at least one of an assignment to at least one of the one or more masks or an undetermined assignment; and inserting at least some of the one or more dummies in the mask layout, thus balancing mask loading within the semiconductor processing environment, at least some of at least one of the receiving, the creating the first window, the creating the first halo, the determining, the assigning, or the inserting implemented at least in part via a processing unit.