Patent ID: 7788551
Filing Date: 2010-08-31
Classification: G11C

Abstract:
1. A memory instance having a plurality (N) of main array column (MAC) portions and a redundancy array column (RAC) portion, wherein each of said MAC portions and said RAC portion is associated with a sense amplifier and write driver (SAWD) circuit block for operably coupling with one of N input/output (I/O) blocks provided for said memory instance, said memory instance comprising: means for detecting that one of said MAC portions is faulty; means for decoupling said faulty MAC portion's SAWD circuit block from an I/O block associated therewith and for shifting said faulty MAC portion's I/O block to a SAWD circuit block associated with a MAC portion adjacent to said faulty MAC portion on a selected side thereof; and means for successively shifting coupling relationships between SAWD circuit blocks and I/O blocks for each MAC portion disposed on said selected side of said faulty MAC portion until an I/O block associated with a MAC portion that is adjacent to said RAC portion is shifted to said RAC portion's SAWD circuit block.