Patent ID: 7884349
Filing Date: 2011-02-08
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a memory cell including a first terminal and a second terminal, the memory cell is positioned above a substrate including active circuitry in electrical communication with the first and second terminals, the active circuitry operative to apply a read voltage across the first and second terminals during a read operation to the memory cell and operative to apply a write voltage across the first and second terminals during a write operation to the memory cell, the memory cell including wherein the first terminal is in electrical communication with only one of a plurality of first conductive array lines in a two-terminal cross-point array, the second terminal is in electrical communication with only one of a plurality of second conductive array lines in the two-terminal cross-point array, the memory cell is positioned at an intersection of its respective first and second conductive array lines, the memory cell is electrically in series with its respective first and second conductive array lines the two-terminal cross-point array is fabricated above and is in contact with the substrate, and the two-terminal cross-point array is positioned over the active circuitry, and the plurality of the first and second conductive array lines are electrically coupled with the active circuitry, wherein data is read from the memory cell by applying the read voltage across its respective first and second conductive array lines, wherein data is written to the memory cell by applying the write voltage across its respective first and second conductive array lines, and wherein the selection device substantially blocks current flow thorough the memory cell when the fractional voltage is applied across its respective first and second conductive array lines.