Patent ID: 7149926
Filing Date: 2006-12-12
Classification: G06F

Abstract:
1. An embedded processor comprising: a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and a trace port circuit including: wherein the configurable filter circuit includes a first trace filter including a switch having input terminals connected to the instruction bus and the data bus, wherein the embedded processor further comprises a on-chip debug support (OCDS) circuit coupled to the instruction bus and the data bus, the OCDS circuit including storage that stores instruction information and data information, and a generator that generates a switch control signal that causes the first switch to pass said portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word matches the stored instruction information and data information, and wherein the OCDS circuit comprises: