Patent ID: 6020636
Filing Date: 2000-02-01
Classification: H01L

Abstract:
High-power high-voltage large chip transistor comprising a thermally and electrically conductive flange having a flat upper surface; a semiconductor die having a flat lower surface with an electrode terminal 3 region formed over a majority of said lower surface, an electrode terminal 1 region and an electrode terminal 2 region formed respectively on portions of said die away from said flat lower surface; a terminal 2 lead isolated from said flange and electrically connected to said electrode terminal 2 region; a terminal 1 lead isolated from said flange and electrically connected to said electrode terminal 1 region; and means for seating said electrode terminal 3 region in direct electrical and thermal contact with said flange, said means for seating including means for protecting said semiconductor die from thermal stresses, said flange serving as a terminal 3 lead for said die; wherein said die has a breakdown voltage between the terminal 2 and terminal 3 regions on the order of one kilovolt or higher; wherein said lower flat surface of said die has an area of approximately one hundred thousand square mils or larger; and wherein said electrode terminal 3 region is metallized over substantially the entire surface thereof.