Patent ID: 8304878
Filing Date: 2012-11-06
Classification: H01L,H05K

Abstract:
1. A semiconductor package structure, comprising: a mounting building block having at least one electronic component mounted thereon, wherein the mounting building block comprises: a first core layer having a first surface and a second surface opposite to the first surface; a first conductive layer, located on the first surface of the first core layer and comprising a plurality of first bonding pads, wherein a first surface finish layer is disposed on at least one of the first bonding pads; and a second conductive layer, located on the second surface of the first core layer and comprising a plurality of second bonding pads, wherein a second surface finish layer is disposed on at least one of the second bonding pads, and the at least one electronic component is electrically connected to the second conductive layer of the mounting building block; a spacing building block, joined with the mounting building block, wherein the spacing building block comprises: a second core layer having a third surface and a fourth surface opposite to the third surface; a third conductive layer, located on the third surface of the second core layer and comprising a plurality of third bonding pads, wherein a third surface finish layer is disposed on at least one of the third bonding pads; and a fourth conductive layer, located on the fourth surface of the second core layer and comprising a plurality of fourth bonding pads, wherein a fourth surface finish layer is disposed on at least one of the fourth bonding pads; a cover building block, joined with the spacing building block, wherein the third surface finish layer of the spacing building block is in direct physical contact with the second surface finish layer of the mounting building block, and the fourth surface finish layer of the spacing building block is in direct physical contact with the cover building block; a plurality of conductive vias, electrically connecting the mounting building block, the spacing building block and the cover building block through a connection of the plurality of the conductive vias and at least the second, third and fourth surface finish layers; and an encapsulant, filling up a cavity enclosed by the mounting building block, the spacing building block and the cover building block, wherein the at least one electronic component is disposed within the cavity and is embedded within the encapsulant.