Patent ID: 6147550
Filing Date: 2000-11-14
Classification: G05F

Abstract:
A transconducting circuit, including:a master cell configured to assert a regulated bias voltage in response to an unregulated supply voltage, wherein the bias voltage has a lower magnitude relative to ground than does the supply voltage; anda transconducting slave cell coupled to receive the bias voltage and configured to operate in subthreshold in response to said bias voltage, wherein the transconducting slave cell includes a CMOS inverter comprising a PMOS transistor having a gate and a drain, and an NMOS transistor having a gate coupled to the gate of the PMOS transistor at a first node coupled to receive an input voltage, the NMOS transistor having a drain coupled to the drain of the PMOS transistor at a second node, and the PMOS transistor having a source coupled to receive the bias voltage.