Patent ID: 9105614
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A semiconductor structure comprising: gate structures including a stack of a gate dielectric and a gate electrode and located on a semiconductor substrate; a dielectric layer located on said semiconductor substrate, wherein top surfaces of said gate structures are coplanar with a top surface of said dielectric layer; a contact-level dielectric layer located over said dielectric layer and said gate structures; a metal semiconductor alloy portion located on a semiconductor material; a substrate contact structure embedded in said contact-level dielectric layer and in contact with said metal semiconductor alloy portion and at least one of said gate spacers; and a gate contact structure embedded in said contact-level dielectric layer and in contact with a top surface of one of said gate electrodes, wherein said gate contact structure is in contact with another of said gate electrodes and overlies a portion of said planarized dielectric layer between said one of said gate electrodes and said another of said gate electrodes.