Patent ID: 6822342
Filing Date: 2004-11-23
Classification: G03F,H01L,Y10S

Abstract:
An overlay target for reducing residue therein from processes for forming semiconductor devices on a wafer comprising:a material surface; at least three rectangular elongated registration features having adjacent sides of unequal length in said material surface, said at least three rectangular elongated registration features each having a bottom surface, a series of substantially vertically extending laterally continuous raised lines originating at said bottom surface of each of said at least three rectangular elongated registration features, substantially all of said raised lines having surfaces which are substantially coplanar with said material surface, and a series of trenches disposed between said raised lines within each of said at least three rectangular elongated registration features, said at least three rectangular elongated registration features defining a perimeter of a geometric shape, said at least three rectangular elongated registration features comprising four rectangular elongated registration features defining said overlay target, each of said four rectangular elongated registration features including said series of substantially vertically extending laterally continuous raised lines originating at said bottom surface of each of said at least three registration features, and said series of trenches disposed between said raised lines within said four rectangular elongated registration features, said four rectangular elongated registration features defining a continuous perimeter of a rectangle.