Patent ID: 6455335
Filing Date: 2002-09-24
Classification: G01R

Abstract:
A semiconductor device manufacturing method, comprising:a step for forming a number of integrated circuits on a wafer; a step for attaching integrated circuit protecting members/external connection terminals to an integrated circuit forming plane of said wafer; a step for implementing a probe test for conductivity on the wafer on which said number of integrated circuits have been formed; a step for implementing a burn-in thermal load test on the wafer on which said number of integrated circuits have been formed; and a step for dicing the wafer into a plurality of chips after completion of said probe test step and said burn-in test step wherein the step for attaching integrated circuit protecting members/external connection terminals is carried out before said step for dicing the wafer, and characterized in that said probe test step/said burn-in test step comprises a pressing step for pressing a plurality of probes provided in a membrane to said wafer by using a plurality of pressure members and that separate pressure loads are respectively applied to said plurality of pressure members on the side opposite said wafer in pressing said plurality of probes.