Patent ID: 8315120
Filing Date: 2012-11-20
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a pair of sense amplifiers configured to be connected between a pair of bit lines and amplify and output a voltage difference between the pair of bit lines; a first driver configured to generate a pair of first sense amplifier driving signals activated based on an active command and block information corresponding to the pair of sense amplifiers; a second driver configured to generate a pair of second sense amplifier driving signals which are activated based on the active command and the block information and have a deactivation period corresponding to a change period of logic values of the pair of bit lines during command execution; a first switching unit configured to apply a first power supply voltage and a second power supply voltage to the pair of sense amplifiers, respectively, in response to the pair of first sense amplifier driving signals; and a second switching unit configured to apply the first power supply voltage and the second power supply voltage to the pair of sense amplifiers, respectively, in response to the pair of second sense amplifier driving signals.