Patent ID: 6201845
Filing Date: 2001-03-13
Classification: G06F,H04L

Abstract:
A data processing apparatus comprising:a first circuit operating with a first clock of a first clock cycle;a second circuit operating with a second clock of a second clock cycle different from the first clock cycle; anda first clock source which generates and outputs a train of pulses in accordance with the first clock cycle,the second circuit including:a sampler circuit which receives the train of pulses output from the first clock source and samples the train of pulses, using the second clock as a sampling signal, and outputs a sampled train of pulses;a delay circuit which receives the sampled train of pulses, output from the sampler circuit, and delays the sampled train of pulses by a predetermined number of clock cycles in response to the second clock and thereby outputs a delayed train of pulses; anda clock converter which receives the sampled train of pulses output from the sampler circuit and the delayed train of pulses output from the delay circuit, and effects a predetermined logic operation with respect to both of the sampled and delayed trains of pulses, and thereby generates and outputs a further train of pulses having a clock cycle approximately equal to the first clock cycle.