Patent ID: 7465970
Filing Date: 2008-12-16
Classification: H01L

Abstract:
1. A common pass gate layout of a D flip-flop comprising: a first n diffusion region; a second n diffusion region; a first poly-silicon conductor extending from the first n diffusion region to the second n diffusion region, for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively; a second poly-silicon conductor extending from the first n diffusion region to the second n diffusion region, for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively; a first p diffusion region adjacent to the second n diffusion region; a second p diffusion region; a third poly-silicon conductor extending from the first p diffusion region to the second p diffusion region, for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively; a fourth poly-silicon conductor extending from the first p diffusion region to the second p diffusion region, for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively; a first clock output pin coupled to the first poly-silicon conductor and the fourth poly-silicon conductor, for outputting a first clock signal; and a second clock output pin coupled to the second poly-silicon conductor and the third poly-silicon conductor, for outputting a second clock signal.