Patent ID: 6103603
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of fabricating on a semiconductor substrate gate electrodes of a twin-well CMOS device, the method comprising the steps of:forming within the substrate an n-well and a p-well adjacent to the n-well;forming on the substrate an insulating film;depositing onto the insulating film an undoped polysilicon layer, the undoped polysilicon layer having a first region over the n-well and a second region, adjacent to the first region, over the p-well;selectively implanting p-type dopants into the first region and n-type dopants into the second region, thereby forming doped first and second polysilicon regions in the undoped polysilicon layer;selectively and anisotropically etching, by plasma etching, upper portions of the doped first and second polysilicon regions, thereby forming first and second gate-precursor features, respectively, on the insulating film, each gate-precursor feature having substantially vertical sidewalls; andselectively etching, by using reactive ion etching, remaining portions of the doped first and second polysilicon regions having the first and second gate-precursor features until regions of the insulating film are exposed to either side of each of the gate-precursor features, thereby fabricating the gate electrodes of the twin-well CMOS device, wherein etch gases of said reactive ion etching include HBr gas and Cl.sub.2 gas, wherein an initial feed rate of said HBr gas is greater than an initial feed rate of said Cl.sub.2 gas, and wherein etch rates of each of the etch gases are changed from initial feed rates to subsequent feed rates.