Patent ID: 6611176
Filing Date: 2003-08-26
Classification: H03L,Y10S

Abstract:
A phase locked loop with two zeros/two poles active compensation comprising:a node for receiving a signal source having a reference frequency; a programmable divider having an input and having an output; a phase detector with a first input coupled to said signal source, a second input coupled to the output of said programmable divider, a first output and a second output; an operational amplifier having a positive input, a minus input and an output; a first resistor and capacitor network coupled between said first phase detector output and the minus input of said operational amplifier, said first resistor and capacitor network comprising a first resistor in parallel with a second resistor and a first capacitor in series; a second resistor and capacitor network coupled between the minus input of said operational amplifier and the output of said operational amplifier, said second resistor and capacitor network comprising a second capacitor in parallel with a third resistor and a third capacitor in series; a third resistor and capacitor network coupled between said second phase detector output and the positive input of said operational amplifier, said third resistor and capacitor network comprising a fourth resistor in parallel with a fifth resistor and a fourth capacitor in series; a fourth resistor and capacitor network coupled between the positive input of said operational amplifier and a circuit ground, said fourth resistor and capacitor network comprising a fifth capacitor in parallel with a sixth resistor and a sixth capacitor in series; and a voltage controlled oscillator having an input connected to the output of said operational amplifier and having an output connected to the input of said programmable divider, said voltage controlled oscillator output also providing an output signal of said phase locked loop, said output signal having an output frequency.