Patent ID: 6304125
Filing Date: 2001-10-16
Classification: H03K

Abstract:
A method of distributing clock signals within a system comprising:providing clock signals in a plurality of phases to an associated circuit, a first clock signal circuit coupled to separate a second clock signal circuit from a third clock signal circuit; andusing the first clock signal circuit to control the second and the third clock signal circuits and the corresponding portions of the associated circuit; whereby the second clock signal circuit is precluded from changing to a new state until the first clock signal circuit has changed to that state, and the first clock signal circuit is precluded from changing back to the first state until the second clock signal circuit has changed to the first state; and wherein in a system the first clock signal circuit includes a first logic element having a first input terminal coupled to a first input node and a second input terminal coupled to a second input node and having an output terminal coupled to a first output node, and having a second logic element having a first input terminal coupled to the second input node and a second input terminal coupled to the first output node, and an output terminal coupled to the associated circuit:detecting a change in state of both of signals applied to the first input terminal and the second input terminal of the first logic element, and in response thereto changing the state of the output terminal; anddetecting a change in the state of either of signals applied to the first input terminal or the second input terminal of the second logic element and in response thereto changing the state of its output terminal.