Patent ID: 9054091
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. A hybrid packaging multi-chip semiconductor device comprising a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the lead frame unit comprises: a first die paddle and a second die paddle arranged side by side each having opposite first and second transverse edges and opposite first and second longitudinal edges, the second longitudinal edge of the first die paddle and the first longitudinal edge of the second die paddle define a gap separating the first and second die paddles; a first pin and a second pin arranged along a straight line and positioned side by side with the first longitudinal edge of the first die paddle; a third pin comprising a strip inner pin arranged along the first transverse edges of the first die paddle and the second die paddle and, extending from the straight line to a position located between the first longitudinal edge and the second longitudinal edge of the second die paddle; a fourth pin comprising a strip inner pin arranged along the second longitudinal edge of the second die paddle; wherein the first semiconductor chip is attached on a top surface of the first die paddle and the second semiconductor chip is flipped and attached on top surfaces of the inner pin of the third pin and the second die paddle, a first electrode and a second electrode formed at a front surface of the second semiconductor chip are electrically connected to the second die paddle and the third pin respectively; the first interconnecting structure comprising a bridge metal clip overlaying both the first semiconductor chip and the second semiconductor chip, the bridge metal clip includes a main plate and a first side wall and a second side wall bent downward and located at the two opposite sides of the main plate, wherein the first side wall is mounted on either one of the first pin and the second pin and the second side wall is mounted on the fourth pin, a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip are electrically connected to each other and to the fourth pin and the first pin or the second pin; wherein the second electrode at the front surface of the first semiconductor chip is electrically connected through a second interconnecting structure to the other one of the first pin and the second pin that is not electrically connected to the first interconnecting structure.