Patent ID: 7568084
Filing Date: 2009-07-28
Classification: H03K

Abstract:
1. A semiconductor integrated circuit comprising: cell arrays comprised of multiple basic cells formed in arrays, wherein each of the basic cells comprises: a first data path including a first data holding circuit and an arithmetic logic circuit between the input switch and output lines that output data only to the immediately adjacent upper/lower/right/left basic cells; a second data path including a second data holding circuit between the input switch and the output lines; and wherein the input lines and the output lines are each connected only to the immediately adjacent upper/lower/right/left basic cells; wherein the configuration memory is adapted to store input switch selection information and arithmetic logic circuit function information; wherein the input switch is adapted to select the input data specified by the input switch selection information from among the input lines; wherein the arithmetic logic circuit is adapted to perform calculations on the input data as specified by the arithmetic logic circuit function information; wherein the first data holding circuit is adapted to store calculated result data from the arithmetic logic circuit, and the second data holding circuit is adapted to hold data input from the input lines, wherein each of the basic cells is adapted to perform an arithmetic calculation by using the first path and to simultaneously transfer data by using the second path in parallel, and wherein the input switch is adapted to select the input data sent from any of the immediately adjacent upper basic cell, lower basic cell, left basic cell and right basic cell, and to output the selected input data to any of the first data path and the second data path, wherein the configuration memory comprises a configuration selector, a first configuration memory device and a second configuration memory device; wherein each of the first configuration memory device and a second configuration memory device is adapted to store the input switch selection information and the arithmetic logic circuit function information, wherein the configuration selector is adapted to output the input switch selection information and the arithmetic logic circuit function information stored in one of the first configuration memory device and the second configuration memory device into the input switch and the arithmetic logic circuit according to an instruction on a configuration select signal line, and wherein the input switch selection information and the arithmetic logic circuit function information stored in the unselected one of the first and second configuration memory devices are rewritten while the configuration selector outputs the input switch selection information and the arithmetic logic circuit function information stored in the selected one of the first and second configuration memories.