Patent ID: 6097775
Filing Date: 2000-08-01
Classification: G06F,H04L

Abstract:
An apparatus for transferring an input event from a source clock domain to a target clock domain, the apparatus comprising:an input unit having a first input, a second input, a third input, and an output, wherein the first input is configured to receive the input event, the second input is configured to receive a source clock signal from the source clock domain, the third input is configured to receive a clear signal, and the output generates a first intermediate signal, the first intermediate signal being present at the output until the clear signal is received at the third input;a first synchronizer unit having a first input, a second input, and an output, wherein the first input is connected to the output of the input unit, the second input is configured to receive the target clock signal, the output generates a second intermediate signal, synchronized to the target clock signal, using the first intermediate signal; anda second synchronizer unit having first input, a second input, and an output, wherein the first input is connected to the output of the first synchronizer unit, the second input is configured to receive a source clock signal from the source clock domain, the output is connected to the third input of the input unit, and wherein the second synchronizer generates the clear signal in response to the second intermediate signal and the source clock signal.