Patent ID: 8983016
Filing Date: 2015-03-17
Classification: H03L

Abstract:
1. A circuit, comprising: a control unit to control loop gain of a PLL (Phase Locked Loop) unit, which regenerates a clock signal of a SDH (Synchronous Digital Hierarchy) signal or an Ethernet signal from an OTN (Optical Transport Network) signal, on the basis of a result of processing a jitter/wander component and a frequency change state on the basis of phase comparison data of the PLL unit, wherein the control unit includes: a Jitter/Wander Detector unit which processes the jitter/wander component and creates jitter/wander information; a Frequency Change Slope Detector unit which processes the frequency change state and creates frequency change information; and a PLL Feed Forward Real-time Actuator unit which controls the loop gain of the PLL unit on the basis of the jitter/wander information and the frequency change information, and wherein the Jitter/Wander Detector unit carries out a dithering process to multiply the phase comparison data by n (n is predetermined number not smaller than two) , and to multiply the multiplied phase comparison data by 1/n after a FFT (Fast Fourier Transform) process.