Patent ID: 6948105
Filing Date: 2005-09-20
Classification: G01R,H01L

Abstract:
1. A method of evaluating a system-on-a-chip IC (SoC), comprising the following steps of: building two or more metal layers to establish a pad frame and internal circuit nodes for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core; and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer; wherein the step of building the metal layers of core includes a step of duplicating the internal circuit node in the core to the top metal layer, thereby enabling to electrically contact with the internal circuit node or the I/O pads by contact probes.