Patent ID: 6125073
Filing Date: 2000-09-26
Classification: G11C

Abstract:
An integrated semiconductor memory, comprising:a plurality of memory banks including a first memory bank and a second memory bank each having memory cells and an address decoder for addressing said memory cells, through said address decoder only said memory cells of a respective memory bank of said plurality of memory banks being addressable;controllable supply voltage sources, each of said controllable supply voltage sources associated with and supplying one of said plurality of memory banks with a respective supply potential; anda decoder generating output signals, a respective output signal of said output signals received by each of said plurality of memory banks, said respective output signal from said decoder activating and deactivating a memory access to said respective memory bank by controlling said respective supply potential provided by an associated one of said controllable supply voltage sources, said respective memory bank being provided with a higher drive capability if said respective memory bank being activated through said respective output signal and provided with a lower drive capability if said respective memory bank being deactivated through said respective output signal.