Patent ID: 6068660
Filing Date: 2000-05-30
Classification: G06F

Abstract:
A method for approximating the parasitic capacitance of a conductor within an integrated circuit of a plurality of integrated circuits, the method comprising the steps of:a) providing the integrated circuit;b) defining a further parasitic capacitance as a function of a data set including physical attributes corresponding to a further conductor within one of the plurality of integrated circuits;c) selecting a first plurality of limiting cases to reduce a plurality of variables used to interpolate a plurality of mathematical formulas to compute the further parasitic capacitance for each of the first plurality of limiting cases;d) performing a first layer interpolation to derive each of the plurality of mathematical formulas;e) deriving a mathematical expression for calculating the further parasitic capacitance based upon the data set, by performing a second layer interpolation between the plurality of mathematical formulas, the second layer interpolation comprising the steps of:selecting a second plurality of limiting cases; andperforming the second layer interpolation using the second plurality of limiting cases to derive the mathematical expression; andf) calculating the parasitic capacitance of the conductor using the mathematical expression.