Patent ID: 6284642
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method of forming a damascene structure over a semiconductor surface, comprising the steps of:providing a semiconductor substrate, the substrate having been provided with points of electrical interconnect in or on the surface thereof;depositing a first layer of dielectric over the surface of the substrate;depositing a first etch stop layer over the surface of the first layer of dielectric;depositing a second layer of dielectric over the surface of said first etch stop layer;depositing a second etch stop layer over the surface of the second layer of dielectric;patterning and etching said second etch stop layer, creating a via pattern having a via width through said second etch stop layer;patterning and etching a layer of etch resistant material over the surface of said second etch stop layer, creating an opening in said layer of etch stop material that aligns with said via pattern having an interconnect line width, further creating al least one opening having an interconnect line width in said layer of etch resistant material that does not align with said via pattern;performing a first etch, said first etch extending said width of said via pattern created in said second etch stop layer to a width of a interconnect line pattern, said first etch etching said via pattern created in said second etch stop layer through said second layer of dielectric, through said first etch stop layer and partially into said first layer of dielectric, said first etch further etching said second etch stop layer in accordance with said at least one opening created in said etch resistant material that does not align with said via pattern; andperforming a second etch, said second etch further etching said via partially etched into said first layer of dielectric through said first layer of dielectric down to the surface of said substrate, said second etch further etching said interconnect line pattern through said second layer of dielectric and partially through said first etch stop layer, completing the creation of said damascene structure, said second etch further etching said second layer of dielectric in accordance with said at least one opening created in said etch resistant material that does not align with said via pattern.