Patent ID: 7411811
Filing Date: 2008-08-12
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a memory cell array in which a plurality of memory cells each of which includes a variable resistor element of which an electric resistance is varied to store data are arranged in a row and column direction, a plurality of data lines are arranged to extend in the row direction, a plurality of bit lines are arranged to extend in the column direction, and the variable resistor elements in the memory cells in the same row are connected at one end to the data line in common while the variable resistor elements in the memory cells in the same column are connected at the other end to the bit line in common, wherein for conducting a writing action to vary an electric resistance of the variable resistor element in the memory cell to be written by supplying a selected data line of the data lines connected to the memory cell to be written and unselected data lines of the data lines other than the selected data line with a row selecting potential and a row unselecting potential respectively through a data line selecting transistor provided for each of the data lines, and supplying a selected bit line of the bit lines connected to the memory cell to be written and unselected bit lines of the bit lines other than the selected bit line with a column selecting potential and a column unselecting potential respectively through a bit line selecting transistor provided for each of the bit lines, the data lines and the bit lines are separately driven so that a write voltage determined by absolute value of a difference between the row selecting potential and the column selecting potential is higher than a level required for conducting the writing action while a first bias voltage determined by absolute value of a difference between the row selecting potential and the column unselecting potential, a second bias voltage determined by absolute value of a difference between the row unselecting potential and the column selecting potential, and a third bias voltage determined by absolute value of a difference between the row unselecting potential and the column unselecting potential are lower than a level required for conducting the writing action, and the second bias voltage is set lower than the first bias voltage when the data line selecting transistors are higher in a current driving capability than the bit line selecting transistors, and the first bias voltage is set lower than the second bias voltage when the data line selecting transistors are lower in the current driving capability than the bit line selecting transistors.