Patent ID: 6615305
Filing Date: 2003-09-02
Classification: G06F

Abstract:
An apparatus for limiting interrupts from a data transfer unit to a central processing unit (CPU) comprising:said data transfer unit generating interrupts at the occurrence of data transfer events, a pacing counter logic for intercepting said generated interrupts, counting the number of generated interrupts, and decreasing the counted number of interrupts in accordance with a number of events acknowledged by the CPU; said pacing counter logic causing an interrupt to the central processing unit if a certain threshold limit of the number of generated interrupts is exceeded, said pacing counter logic generating a special error interrupt if the number of acknowledged interrupt events is greater than the threshold limit; a timer logic, operating with said pacing counter logic, for setting a minimum or maximum time between generated interrupts, wherein an interrupt to the central processing unit is caused based on one of either the counter logic or the timer logic.