Patent ID: 7213221
Filing Date: 2007-05-01
Classification: G06F

Abstract:
1. A method to model a logic stage in a circuit for determining a delay between an input of a driving logic element gate and an input of a driven gate, the method comprising: identifying, in a first logic stage, a drive logic element having an output; identifying, for each stage driven by the drive logic element in the first logic stage, a next stage logic element having an input configured to couple the output of the drive logic element; identifying interconnects between the output of the drive logic element and the input of each stage driven by the drive logic element; representing the drive logic element as a current source model; calculating a value for a current source in the current source model, the value comprising a constant value and an exponential decay value; representing the first stage of the first logic stage with the current source model; and representing each next stage logic element as an equivalent resistor-capacitor circuit, the current source model and each equivalent resistor-capacitor circuit providing a linear circuit representation.