Patent ID: 8705278
Filing Date: 2014-04-22
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: an insulator layer over a substrate; a plurality of semiconductor bodies on the insulator layer; a plurality of pairs of source/drain lines on the insulator layer, wherein the pairs of semiconductor source/drain lines are separated by insulating material from other pairs in the plurality, the pairs in the plurality of pairs including a first source/drain line on one side and a second source/drain line on another side of a corresponding semiconductor body in the plurality of semiconductor bodies; channel regions in the semiconductor bodies between corresponding pairs of source/drain lines, one of said first and second source/drain lines in each of said pairs being electrically connected at a common connection outside of the channel regions, to the corresponding semiconductor body; a source of a bias potential connected to said common connection; a plurality of word lines overlying the plurality of pairs of source/drain lines; and an array of charge storage structures between the plurality of word lines and the channel regions forming memory cells, wherein the memory cells are arranged in a divided bit line architecture; and wherein the plurality of word lines are in direct contact with the array of charge storage structures, wherein: the insulator layer comprises a plurality of recesses extending parallel to one another in a first direction; the source/drain lines and semiconductor bodies therebetween being structures within the recesses, having planar top surfaces, and extending in the first direction; the charge storage structures being structures within the recesses, on the planar top surfaces of the semiconductor bodies and extending in the first direction; and the word lines being spaced apart, parallel structures over the charge storage structures, and extending in a second direction generally perpendicular to the first direction.