Patent ID: 8218388
Filing Date: 2012-07-10
Classification: G11C

Abstract:
1. A read circuit for a semiconductor memory device, for serially reading data from a serial output terminal, comprising: a plurality of byte selectors each for outputting first to eighth data signals from a plurality of predetermined memory cells based on an address; a plurality of sense amplifiers for simultaneously sensing the first data signals from the plurality of byte selectors which are selected to determine the address before the address is determined, and sensing the second to eighth data signals from one of the plurality of byte selectors which corresponds to a determined address when the address is determined; and a selector circuit for selectively reading one of the first data signals which is sensed by the one of the plurality of byte selectors which corresponds to the determined address after the address is determined, and sequentially selectively reading the second to eighth data signals from the one of the plurality of byte selectors; wherein the plurality of sense amplifiers simultaneously sense the first data signals from the plurality of byte selectors which are selected to determine the address before the address is determined, simultaneously sense second to fourth data signals from the one of the plurality of byte selectors which corresponds to the determined address, simultaneously sense fifth and sixth data signals from the one of the plurality of byte selectors which corresponds to the determined address, and simultaneously sense seventh and eighth data signals from the one of the plurality of byte selectors which corresponds to the determined address.