Patent ID: 9070772
Filing Date: 2015-06-30
Classification: G02F,H01L

Abstract:
1. A method for manufacturing an array substrate, comprising: forming a patterned active layer on a gate insulating layer, the active layer covering a part of the gate insulating layer; forming a source/drain electrode material layer on the active layer and the gate insulating layer; forming a patterned insulating layer on the source/drain electrode material layer which is unpatterned, and the patterned insulating layer is formed to have a shape equal to an outline shape of a source electrode, a drain electrode and a channel therebetween to be formed; conducting an etching process by using the insulating layer as a mask, so as to etch the source/drain electrode material layer to form the source electrode and the drain electrode, etch a part of the insulating layer to form a via hole in the insulating layer over the drain electrode, and etch a part of the active layer between the source electrode and the drain electrode to form the channel, wherein the step of forming the patterned insulating layer comprises: applying a layer of insulating material onto the source/drain electrode material layer; patterning the layer of insulating material by using a half-tone mask process, so as to remove the layer of insulating material beyond a region for forming the source electrode and the drain electrode and expose the source/drain electrode material layer corresponding to a position of the channel, and remove a part of the layer of insulating material corresponding to a position of the via hole to form a recess in the layer of insulating material, wherein a part of the layer of insulating material remains in the recess, so that the source/drain electrode material layer underneath the recess is unexposed, wherein the step of conducting the etching process by using the insulating layer as the mask comprises: etching the source/drain electrode material layer by using the patterned insulating layer as the mask to remove the source/drain electrode material layer beyond the region for forming the source electrode and the drain electrode, thereby forming the source electrode and the drain electrode and exposing the active layer corresponding to the position of the channel; etching the insulating layer to thin the insulating layer and remove the remaining insulating layer in the recess, so as to form the via hole; and simultaneously with etching the insulating layer, removing the part of the active layer corresponding to the position of the channel, so as to form the channel.