Patent ID: 7117412
Filing Date: 2006-10-03
Classification: H03K

Abstract:
1. A flip-flop circuit comprising: a first logic gate which executes a logic operation on a first data signal and a first control signal; a second logic gate which executes a logic operation on a second data signal and the first control signal, the operation results of the first and second logic gates being forcibly fixed to a predetermined value irrespective of the first and second data signals, if the first control signal is asserted; a first selection circuit which selects one of the operation results of the first and second logic gates, and outputs the selected operation result as a first selection signal, the first selection circuit selecting the result of the first logic gate when a first enable signal from outside the flip-flop circuit is asserted; a latch circuit which latches the first selection signal; a third logic gate which executes a logic operation on a third data signal and a second control signal; a fourth logic gate which executes a logic operation on a fourth data signal and the second control signal, the operation results of the third and fourth logic gates being forcibly fixed to a predetermined value irrespective of the third and fourth data signals, the second selection circuit selecting the result of the fourth logic gate when a second enable signal from outside the flip-flop circuit is asserted; and a second selection circuit which selects one of the operation results of the third and fourth logic gates, and outputs the selected operation result as a second selection signal, the second selection signal being out of the first and second data signals.