Patent ID: 6204116
Filing Date: 2001-03-20
Classification: H01L,Y10S

Abstract:
A method for fabricating a capacitor in a mixed-mode integrated circuit constructed on a semiconductor substrate having a first area where a gate and a pair of source/drain regions are defined and a second area where a first electrode is defined; the method comprising the steps of:forming a first dielectric layer covering the first electrode;forming a doped polysilicon layer over the first dielectric layer,forming a metal silicide layer over the doped polysilicon layer;forming a second dielectric layer over the metal silicide layer, wherein the first dielectric layer and the second dielectric layer are both formed from a same dielectric material and have a same thickness,performing a selective removal process on the second dielectric layer, the metal silicide layer, and the doped polysilicon layer, with the remaining parts therefor in combination constituting a second electrode, and the second electrode, the first dielectric layer and the first electrode in combination constituting the intended capacitor.