Patent ID: 6073199
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A bus arbiter for devices coupled to a bus, comprising:a history queue for tracking a plurality of previous bus grants to devices selected as bus master in earlier bus cycles;control logic coupled between the bus and the history queue that grants a current bus master to one of a plurality of requesting devices based on a first arbitration according to the plurality of previous bus grants in the history queue and bus request signals received from the requesting devices;the control logic conducting a first hidden arbitration during the current bus cycle that selects a next bus master for conducting a bus transaction on a next available bus cycle after the current bus master completes a current bus cycle; andthe control logic also conducting a second hidden arbitration during that same current bus cycle while the granted next bus master waits for the next available bus cycle, wherein if the second hidden arbitration indicates that a different one of the requesting devices has a higher priority than the granted next bus master, the control logic selectively deasserts its original grant to the next bus master and asserts the grant for the next bus master to the device with higher priority.