Patent ID: 7107471
Filing Date: 2006-09-12
Classification: G06F,Y02D

Abstract:
1. A microprocessor that operates in a manner that conserves power, the microprocessor comprising: an instruction register for temporarily storing a next instruction to be executed; an instruction evaluation unit that is connected to said instruction register such that said instruction evaluation unit receives said next instruction from said instruction register, said instruction evaluation unit being configured to evaluate said next instruction in order to produce activity indicators by reading an operation type from the instruction and providing an associated signal comprising one of a clock marker or a no-clock marker based upon the operation types of said instructions; a functional unit for executing instructions, said functional unit having a plurality of stages, each of said stages capable of being separately activated or deactivated based upon a respective activity indicator, where said stages of said functional unit are arranged in series; a memory unit for receiving and registering outputs from the functional unit wherein the amount of time required to register an output from the functional unit comprises time T a stage activation controller that is connected to said instruction evaluation unit and includes logic gates that utilize said activity indicators in conjunction with a stage activation controller clock pulse C a clock circuit that supplies the stage activation controller clock pulse C