Patent ID: 6745291
Filing Date: 2004-06-01
Classification: G06F

Abstract:
An N-way set associative data cache system where N is greater than two and wherein data and instructions are arranged in pages in said system, said data cache system comprising:a cache controller for receiving requests for accessing data and instructions from a processing unit, a cache buffer register for storing access requests in the form of a page tag address and a line address to be accessed, a plurality of N-ways each having storage capacity for a plurality of lines of data and the same numbered lines in said N-ways being addressable simultaneously by a line address from said cache buffer register, associative directories, one for each of said N-ways, each having storage capacity of the page address entry associated with each of said lines of data in each of said associated ways, programs means in said cache controller for seeking the data or instructions stored in the cache ways, said programs means comprising means for comparing the page tag address at the line address to be accessed with each of said page address entries in order to determine if the requested line of data is stored in said cache system, and LRU ordering means which connects as a pointer to said directories for determining the one line in the number of N-lines in said N-ways to be replaced with a new line of data in the event of a miss, said LRU ordering means also providing a logic-tree based look-up table which indicates how each possible LRU ordering of a line is to be changed in the event of a hit on that line, said LRU ordering means using said table to change the LRU ordering of a line following a hit thereon.