Patent ID: 8645594
Filing Date: 2014-02-04
Classification: G06F

Abstract:
1. A data storage device comprising: a storage aggregation unit that has multiple memory-mapped input/output (I/O) devices interconnected within the storage aggregation unit, each memory-mapped I/O device has multiple Base Address Registers, the storage aggregation unit includes a physical connection interface configured to connect to a computer bus; the storage aggregation unit including a processor and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, causes the storage aggregation unit to perform the operations of: receiving a memory access request at a first memory-mapped I/O device of the storage aggregation unit; in response to the memory access request identifying a physical address within a first Base Address Register of the first memory-mapped I/O device, executing the memory access request on the first memory-mapped I/O device; and in response to the memory access request identifying a physical address within a second Base Address Register of the first memory-mapped I/O device, redirecting the memory access request to a second memory-mapped I/O device, of the multiple interconnected memory-mapped I/O devices, and executing the memory access request on the second memory-mapped I/O device.