Patent ID: 8825923
Filing Date: 2014-09-02
Classification: G06F

Abstract:
1. A host system comprising: a CPU; a host controller; a system memory configured to be accessed by the CPU and the host controller; and a memory device which is connected to the host controller through an interface, wherein the CPU is configured to execute a host driver to control the host controller, each of first, third, and fourth descriptors has an attribute field for identifying a type of the descriptors, and designating a processing method of the descriptors, the first descriptor includes a plurality of pointers with attributes, each of the pointers of the first descriptor indicates a leading region of the third descriptor, the third descriptor includes command issue information and attributes, the fourth descriptor includes a number of DMA execution information and attributes, wherein the DMA unit is configured (1) to load the first descriptor, (2) to acquire the pointer from the loaded first descriptor, (3) to load the third descriptor and the fourth descriptor based on the acquired pointer, (4) to execute a data transfer between the system memory and the memory device, (5) to repeat the process of (2) to (4) until the attribute of the first descriptor indicates the end of descriptor, and (6) to generate an interrupt to the CPU when the data transfer is end or during a DMA data transfer, and wherein the host driver is configured (1) to generate the first, third and fourth descriptors into the system memory according to an data read/write request of an application from/to the memory device, (2) to start the DMA unit when a location of the first descriptor is set to the host controller, and (3) to deal with the interrupts until the DMA unit indicates completion of the data transfer of the first descriptor.