Patent ID: 7668031
Filing Date: 2010-02-23
Classification: G11C

Abstract:
1. A semiconductor memory device including a one-transistor (1-T) field effect transistor (FET) type memory cell where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer, the device comprising: a plurality of word lines arranged in a row direction; a plurality of bit lines arranged in a column direction; a pair of clamp dummy lines arranged in the column direction; a pair of reference dummy lines arranged in the column direction; a cell array including the memory cell and formed in a region where the word line and the bit lines are crossed; a dummy cell array including the memory cell and formed where the word line, the pair of clamp dummy lines and the pair of reference dummy lines are crossed; and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.