Patent ID: 7460989
Filing Date: 2008-12-02
Classification: G06F

Abstract:
1. In a processor comprising a plurality of function units, wherein each function unit is provided with its own unit clock, and said function units are operated concurrently to process a stream of instructions, a method for enabling the processing of said instructions to be modeled using a sequential computer language, said method comprising the steps of; generating a model master clock having a master clock cycle; initializing each of said function units at the beginning of respectively corresponding processing cycles; operating each function unit during its corresponding processing cycle to carry out a task with respect to one of said instructions, in order to produce a task result, wherein said function units are operated concurrently with one another, each according to its own unit clock, and said unit clocks are unsynchronized with one another; completing the processing cycles of all of said function units at the same specified time, as defined by a specified position of one of said master clock cycles, by selectively evaluating the task results respectively produced by each of said function units; and writing each of said evaluated results produced by said function units, together with said specified time defined by said specified master clock cycle position, into registers respectively corresponding to said task results.