Patent ID: 6436725
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A method of manufacturing a semiconductor device having:a memory mat including a plurality of memory cells provided at the intersections of first and second word lines, first and second normal data line and a redundant data line; and a repair decision circuit, when a first defect exists in said memory cells connected to said first normal data line, for replacing said first defect in a first replacement unit, and when a second defect exists in said memory cells connected to said second normal data line, for replacing said second defect in a second replacement unit smaller than said first replacement unit, said repair decision circuit being constructed to select said redundant data line when said second word line and said first normal data line are selected, and to select said first normal data line when said first word line and said first normal data line are selected, in the case when said first replacement unit includes a region of the intersections of said first and second word lines and said first normal data line and when said second replacement unit includes a region of the intersections of said first word line and said second normal data line, said method comprising: a wafer processing step of forming on a semiconductor wafer an integrated circuit including said memory mat and said repair decision circuit; a probing step of examining electric characteristics of each chip on said semiconductor wafer having said integrated circuit formed; and a programming step, when a plurality of defects including said first and second defects are found out, of making a program in said repair decision circuit so as to repair said plurality of defects.