Patent ID: 7671631
Filing Date: 2010-03-02
Classification: G06F

Abstract:
1. A low voltage differential signal receiving device, comprising a first differential receiver, a second differential receiver, a phase locked loop (PLL), and a clock edge and data boundary detection and data extraction logic module; said first differential receiver receiving a data signal from a data signal input, and sequentially outputting said received data signal to a first oversampler; said second differential receiver receiving a clock signal, and sequentially outputting said received clock signal to a second oversampler; said phase locked loop receiving said clock signal output by said second differential receiver, and outputting a sampling clock to both of said first oversampler and said second oversampler; and said clock edge and data boundary detection and data extraction logic module receiving signals output by said first oversampler and said second oversampler, conducting sampling, and outputting a data signal and a clock signal; and wherein said clock signal is treated as another type of data signal; a frequency of sampling input clock and data is increased via asynchronous clock; and said specific clock edge and data boundary detection and data extraction logic module is used to detect clock transition and extract data bytes from clock and data samples.