Patent ID: 6392653
Filing Date: 2002-05-21
Classification: G06T

Abstract:
In a device for processing acquisition data, in particular image data, comprising:a) a first memory area adapted for storing a sequence of acquisition data, in the form of sequence elements, each having at least one bit, b) a second memory area comprising a calculation module for access to the first memory area, which can be addressed in order to access the neighbourhood of a designated current element, c) a third memory area adapted for storing a calculation module, capable of receiving as input a designation of at least one current element, in order to deliver as output to the said neighbourhood of this current element a result word representative of the application of a chosen processing function having a binary decision tree associated therewith, said calculation module comprising a set of instructions, with test instructions, each relating to one bit, and forming, from an input instruction, paths where the test instructions are relayed to reach final instructions defining the result word, bit by bit; d) control means for repetitively implementing said module in cooperation with a working memory, on the basis of successive current elements, in order to obtain a multiplicity of result words, representing an at least partial transform of the sequence by the said processing function; the improvement wherein said calculation module is provided with an instruction set optimized by a technique of reducing said binary decision tree associated with said function, in order jointly to minimize the total number of test instructions accumulated over all the paths defined by the test instruction set and the total number of instructions in this set, which makes it possible to increase the processing speed by a better compromise between the total memory occupancy of the instruction set and its execution speed.