Patent ID: 8148223
Filing Date: 2012-04-03
Classification: H01L

Abstract:
1. A fabrication method of an embedded memory, comprising: providing a substrate comprising a cell array region and a periphery region; forming an isolation structure in contact with and in the substrate to divide the cell array region into a plurality of first active areas isolated by a first isolation area and divide the periphery region into a plurality of second active areas isolated by a second isolation area; recessing the isolation structure in the first isolation area, such that a top surface of the isolation structure in the first isolation area is lower than a top surface of the substrate; forming a plurality of first transistors in the first active area and a plurality of second transistors in the second active region; forming a first dielectric layer overlying the first and second transistors; embedding first and second conductive plugs, electrically connecting the first transistors, into the first dielectric layer; forming an etch stop layer and a second dielectric layer overlying the first dielectric layer, wherein the etch stop layer is in contact with the first dielectric layer and directly below the second dielectric layer; patterning the second dielectric layer and the etch stop layer to form a plurality of capacitor openings therein, exposing the first conductive plugs; conformally forming a first plate layer overlying the second dielectric layer and laterally surrounding the etch stop layer; removing the first plate layer beyond each capacitor opening to self align the first plate layer in each capacitor opening; conformally forming a capacitor dielectric layer overlying the second dielectric layer and the first plate layer in each capacitor opening; conformally forming a second plate layer overlying the capacitor dielectric layer; patterning the second plate layer and the capacitor dielectric layer to form a plurality of capacitors corresponding to the plurality of capacitor openings and form a top plate opening exposing the second dielectric layer and being fully surrounded by the patterned second plate layer as viewed from a top-view perspective, wherein the patterned second plate layer is shared by at least two of the plurality of capacitors; forming a first dielectric spacer on the second plate layer on a sidewall of each capacitor opening dielectric spacer on a sidewall of the top plate opening.