Patent ID: 6593174
Filing Date: 2003-07-15
Classification: H01L,Y10S

Abstract:
A method of fabricating an integrated circuit device on a monolithic semiconductor substrate, comprising the steps of:forming on the substrate patterned dielectric layers having thicker regions and thinner regions, selectively covering portions of the substrate and leaving exposed a portion of the substrate between the thinner regions of the dielectric layers; forming a first semiconductor layer having a thickness of approximately 400 to 2400 angstroms, the first semiconductor layer having a first region and a second region, the first region being a substantially monocrystalline region on the exposed portion of the substrate and the second region being on at least a portion of the thinner regions of the dielectric layer; and doping the second region of the first semiconductor layer to provide a conductivity type opposite to a conductivity type of the first region of the first semiconductor layer.