Patent ID: 7061057
Filing Date: 2006-06-13
Classification: H01L

Abstract:
1. A LDMOS transistor comprising: a) a N-doped substrate, b) a P-doped epitaxial layer on the N-doped substrate with a P+ doped buried layer in the epitaxial layer, c) a gate electrode on a dielectric layer on the surface of the P-doped epitaxial layer and over a P-doped channel region in the P-doped epitaxial layer, d) a N-doped drain region in the P-doped epitaxial layer extending from one side of the gate electrode, e) a N-doped source region in the P-doped epitaxial layer extending from an opposing side of the gate electrode, and f) a source contact extending through the P-doped epitaxial layer and the P+ buried layer into the N-doped substrate and connecting the N-doped source region to the N-doped substrate.