Patent ID: 6717453
Filing Date: 2004-04-06
Classification: H03K

Abstract:
A level shift circuit that is supplied with a first power supply potential, a second power supply potential, and a reference potential and converts an input signal having a first potential swing essentially corresponding to a potential difference between the first power supply potential and the reference potential into an output signal having a second potential swing essentially corresponding to a potential difference between the second power supply potential and the reference potential, comprising:a level shift portion coupled to receive the input signal and generating first and second signals having the second potential swing and complementary logic levels, the second potential awing being greater than the first potential swing; a signal selection portion coupled to receive the first and second signals and providing the output signal having a transition based on the first signal when the first signal transitions from a high logic level to a low logic level and based on the second signal when the second signal transitions from the high logic level to the low logic level; wherein the level shift portion includes; the first signal being received at a first node and the second signal being received at a second node; a first inverter supplied with the first power supply potential and the reference potential the first inverter is coupled to receive the input signal and generating an inverted signal having the first potential swing; a first p-channel transistor having a source coupled to receive the second power supply potential, a gate coupled to the second node, and a drain coupled to the first node; a second p-channel transistor having a source coupled to receive the second power supply potential a gate coupled to the first node, and a drain coupled to the second node; a first n-channel transistor having a drain coupled to die first node, a gate coupled to receive the inverted signal, and a source coupled to the reference potential; and a second n-channel translator having a drain coupled to the second node, a gate coupled to receive the input signal and a source coupled to the reference potential.