Patent ID: 7208409
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A method to form MOS transistors, comprising: forming a dielectric layer over a semiconductor; forming a gate electrode structure over said dielectric layer; forming sidewall structures comprising silicon oxide layers and silicon nitride layers adjacent said gate electrode structure; implanting dopant species into said semiconductor adjacent to said gate electrode structure and said sidewall structures to form source and drain regions; annealing said source and drain regions after said implanting of said dopant species; forming fluorine containing regions in said source and drain regions after said annealing by exposing said source and drain regions to species formed in a fluorine containing plasma; forming a metal layer over said source and drain regions and said fluorine containing regions; and reacting said metal layer with said underlying fluorine containing regions to form metal silicide regions in said source and drain regions.