Patent ID: 8329533
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. A method of forming a stacked capacitor for double-poly flash memory, the method comprising: forming a lower electrode, wherein the lower electrode is a first doped region in a substrate and formed at the same step as a tunneling implant region of a flash cell is formed; forming a lower dielectric layer on the lower electrode, wherein the lower dielectric layer is formed at the same step as a tunneling oxide of the flash cell is formed; forming a central electrode on the lower dielectric layer, wherein the central electrode is formed at the same step as a floating gate of the flash cell is formed; forming an upper dielectric layer on the central electrode, wherein the upper dielectric layer is formed at the same step as a central dielectric layer of the flash cell is formed and covers a portion of the central electrode; and forming an upper electrode on the upper dielectric layer, wherein the upper electrode is formed at the same step as a control gate of the flash cell is formed.