Patent ID: 7450529
Filing Date: 2008-11-11
Classification: G06F,H04L,Y04S

Abstract:
1. A cross link multiplexer bus, comprising: a plurality of cross link multiplexers, said plurality of cross link multiplexers having a destination port configured to receive a data signal and an origin port configured to produce said data signal; and a plurality of interconnects, wherein a set of interconnects of said plurality of interconnects is coupled between a pair of adjacent cross link multiplexers of said plurality of cross link multiplexers; wherein a first interconnect of said set of interconnects has a first length, a second interconnect of said set of interconnects has a second length, and said first length and said second length are substantially equal; wherein said first interconnect is configured to convey a first bit of a number of bits of said data signal and said second interconnect is configured to convey a second bit of said number of bits of said data signal and said first bit remains substantially synchronized with said second bit.