Patent ID: 6812741
Filing Date: 2004-11-02
Classification: G06F,H04L

Abstract:
A bus system for transmitting an address and data between a first LSI (Large Scale Integrated Circuit) that performs an access and a second LSI that is to be accessed, comprising:a first unidirectional bus including a plurality of signal lines, for transmitting an address and data outputted from the first LSI, to the second LSI; and a second unidirectional bus including a plurality of signal lines, for transmitting data outputted from the second LSI, to the first LSI, wherein the plurality of signal lines included in the first unidirectional bus and the plurality of signal lines in the second unidirectional bus are alternately routed, so that each of the plurality of signal lines in the second unidirectional bus is adjacent to a different one of the plurality of signal lines in the first unidirectional bus, and when the first LSI performs a write access, a write address and write data are transmitted through the first unidirectional bus, and when the first LSI performs a read access, a read address is transmitted through the first unidirectional bus and read data is transmitted through the second unidirectional bus.