Patent ID: 8803562
Filing Date: 2014-08-12
Classification: G09G,G11C

Abstract:
1. A stage circuit comprising: an output unit comprising a first transistor coupled between a first power source and an output terminal of the stage circuit, and having a gate electrode coupled to a first node; a second transistor coupled between the output terminal and a third input terminal of the stage circuit, and having a gate electrode coupled to a second node; and a third transistor coupled between the output terminal and a second power source, a gate electrode of the third transistor coupled to a third node; a progressive driver coupled to first, second, and sixth input terminals of the stage circuit, the progressive driver being configured to progressively output a scan signal by controlling voltages at the first, second, and third nodes during a first period; and a concurrent driver coupled to at least one of fourth and fifth input terminals of the stage circuit, the concurrent driver being configured to concurrently supply the scan signal by controlling the voltages at the first, second, and third nodes during a second period, wherein clock signals supplied to the first, second, and third input terminals during the second period are concurrently set to a gate-on or gate-off voltage.