Patent ID: 7876134
Filing Date: 2011-01-25
Classification: G06F,H03K

Abstract:
1. A signal frequency change circuit, comprising: a delay line configured to delay a clock signal by a first delay time in response to a delay control signal to generate a delay signal and to delay the clock signal by a second delay time smaller than a first delay time to generate pre-frequency change clock signals; a detector configured to detect a specific phase of the clock signal using the delay signal to generate a phase locked completion signal; a controller configured to sequentially shift the delay control signal and a multiplexing control signal using the clock signal supplied before an activation timing point of the phase locked completion signal; a multiplexer configured to select and output one of the pre-frequency change clock signals in response to the multiplexing control signal; and an output unit configured to generate a frequency change clock signal having a frequency that is changed differently from the frequency of the clock signal by using the clock signal and an output signal of the multiplexing unit.