Patent ID: 7339275
Filing Date: 2008-03-04
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device assembly, the method comprising: providing a first integrated circuit chip having a first surface, a plurality of conductive contacts disposed at said first surface, and a plurality of integrated circuits, each of said plurality of integrated circuits electrically coupled to at least one of said plurality of conductive contacts, depositing an organic cushioning layer over said first integrated circuit chip; patterning said organic cushioning layer to form a plurality of openings to expose at least the conductive contacts; depositing a robust metal layer overlying said integrated circuits and filling said plurality of openings; patterning said robust metal layer to form a plurality of robust metal portions, at least some of which serve as landing pads, wherein the robust metal portions spatially redistribute at least one of said plurality of conductive contacts, wherein each robust metal portion comprises a single contiguous metal or alloy, and directly contacts at least one of the plurality of conductive contacts and can withstand high current operation therethrough, and wherein at least one of said plurality of robust metal portions at least partially overlies the organic cushioning layer such that the robust metal portion can withstand impact stresses; disposing a first portion of a second integrated circuit chip overlying at least a first portion of said first integrated circuit chip so that a second portion of said second integrated circuit chip extends beyond said first integrated circuit chip, wherein said second integrated circuit chip has a second surface and comprises a plurality of first bonding members disposed at said second surface and said second surface is disposed adjacent said first surface of said first integrated circuit chip; disposing a first portion of a third integrated circuit chip overlying at least a second portion of said first integrated circuit chip so that a second portion of said third integrated circuit chip extends beyond said first integrated circuit chip, wherein said third integrated circuit chip has a third surface and comprises a plurality of second bonding members disposed at said third surface and said third surface is disposed adjacent said first surface of said first integrated circuit chip; bonding each one of a first set of said plurality of bonding members to one of said plurality of robust metal portions; and bonding each of a first set of said plurality of second bonding member to one of said plurality of robust metal portions; depositing an underfill material on said first surface of said first integrated circuit chip; and curing said underfill material.