Patent ID: 6413814
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:defining a memory cell area and a peripheral circuit area on a surface of a semiconductor substrate, forming a first well by implanting first conductivity type impurity ions into the memory cell area a plurality of times and at different acceleration energies, the first well having a first local maximum of a first conductivity type impurity concentration at a first depth position apart from the surface of the semiconductor substrate; and forming a second well by implanting first conductivity type impurity ions into the peripheral circuit area a plurality of times and at different acceleration energies, the second well having a second local maximum of the first conductivity type impurity concentration at a second depth position apart from the surface of the semiconductor substrate, wherein a dose of a highest acceleration energy ion implantation of said different acceleration energies is higher in the peripheral circuit area than in the memory cell area, and the impurity concentration of the second local maximum is larger than the impurity concentration of the first local maximum.