Patent ID: 6150887
Filing Date: 2000-11-21
Classification: H03L

Abstract:
A phase locked loop (PLL) circuit comprising:a first phase comparator for comparing an input signal and a first feed back signal in phase to generate a first phase difference voltage signal;a first loop filter for filtering said first phase difference voltage signal, and for generating a first filter output voltage signal;a bias signal generating section for generating a bias signal;a first voltage controlled oscillating section for generating a first oscillation output signal based on said first filter output voltage signal and said bias signal, wherein said voltage controlled oscillating section generates said first oscillation output signal having a same frequency as that of said input signal based on said bias signal; anda first counter for generating said first feed back signal based on said first oscillation output signal, andwherein said bias signal generating section includes;a second phase comparator for comparing a reference input signal and a second feed back signal in phase to generate a second phase difference voltage signal;a second loop filter for filtering said second phase difference voltage signal, and for generating a second filtered output voltage signal;a second voltage controlled oscillating section for generating a second oscillation output signal and said bias signal based on said second filtered output voltage signal; anda second counter for generating said second feed back signal based on said second oscillation output signal, andwherein said first voltage controlled oscillating section includes;a first voltage/current converter for converting said first filtered output voltage signal into a first phase error current signal;an adder for adding said first phase error current signal and said bias signal to generate a control signal; anda first current controlled oscillator for generating said first oscillation output signal based on said control signal, andwherein said second voltage controlled oscillating section includes;a second voltage/current converter for converting said second filtered output voltage signal into a second phase error current signal and said bias signal and for supplying said bias signal to said adder; anda second current controlled oscillator for generating said second oscillation output signal based on said second phase error current signal.