Patent ID: 7529134
Filing Date: 2009-05-05
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a memory cell array comprising a plurality of memory cells and a plurality of word lines respectively connected thereto; a word line voltage generator including a plurality of program loops therein and configured to generate a plurality of program voltages responsive to activation of corresponding ones of the plurality of program loops; an add-subtract circuit configured to provide a first loop initial value corresponding to a first one of the plurality of program loops responsive to selection of a first one of the plurality of memory cells for programming. and configured to provide a second loop initial value corresponding to a second one of the plurality of program loops responsive to selection of a second one of the plurality of memory cells for programming; and a loop selection circuit configured to activate ones of the plurality of program loops in a first predetermined sequence based on the first loop initial value to generate a first series of program voltages for programming the first one of the plurality of memory cells, and configured to activate ones of the plurality of program loops in a second predetermined sequence different from the first predetermined sequence based on the second loop initial value to generate a second series of program voltages for programming the second one of the plurality of memory cells.