Patent ID: 6148351
Filing Date: 2000-11-14
Classification: G06F

Abstract:
A data transfer method using a direct memory access controller having a plurality of first bus lines having a first bus width and an interface unit having a plurality of second bus lines having a second bus width, the second bus lines including lower data bus lines and upper data bus lines, said method comprising the steps of:connecting said lower data bus lines of said second bus lines to said first bus lines, wherein the lower data bus lines correspond in number to the first bus lines;connecting a predetermined voltage to said upper data bus lines via a resistor element when the second bus width is an integer multiple greater than the first bus width;providing invalid data to said upper data bus lines; andtransferring effective data, having a width which is an integer multiple of the width of data transferrable by the direct memory access controller, between said direct memory access controller and said interface unit using said first bus lines and said lower data bus lines.