Patent ID: 6282662
Filing Date: 2001-08-28
Classification: G06F

Abstract:
A system for managing the power efficiently of a computer having a memory, a processor and one or more power consuming devices, said computer to be operatively connected to a critical input/output (I/O) device requiring said processor to be fully powered when transmitting data to said processor, the system comprising:the critical device coupled to the processor for service of an event by the processor;a power management system stored in said memory for selectively controlling the power consumption of said processor and said power consuming devices between operation in full power and reduced power consumption states; andan override system coupled to determine whether an interrupt request has been issued to request a power up to the processor, the override system being stored in said memory for overriding said power management system to disable power management functions with respect to the processor only, without disabling power management with respect to the power consuming devices.