Patent ID: 6831505
Filing Date: 2004-12-14
Classification: G05F

Abstract:
A reference voltage circuit comprising:first, second, and third MOS transistors being of one conduction type and having drains respectively connected to first, second, and third nodes and gates commonly connected to said second node in order to constitute a current mirror circuit; first, second MOS transistors being of the other conduction type and having drains respectively connected to said first and second nodes and gates commonly connected to said first node in order to constitute apart of a load circuit; a source resistor having one end connected to a source of said second MOS transistor of the other conduction type and constituting another part of said load circuit; and an output resistor having one end connected to said third node used to output a reference voltage and constituting another part of said load circuit, said reference voltage circuit being further constructed such that a dummy diffusion layer of the other conduction type is connected to at least said third node in order to set a ratio of currents leaking, during operation of said reference voltage circuit, through PN junctions of diffusion layers connected to said first, second, and third nodes and being of the other conduction type equal to a ratio of currents leaking, during said operation of said reference voltage circuit, through PN junctions of diffusion layers connected to said first, second, and third nodes and being of the one conduction type.