Patent ID: 7440332
Filing Date: 2008-10-21
Classification: G11C

Abstract:
1. A circuit for determining a programmed state of a memory cell, comprising: a memory cell signal compare circuit generating an output signal; a plurality of reference compare circuits each generating an output signal; a plurality of reference signal generators wherein each reference signal generator generates a reference signal that is coupled to a different reference compare circuit; a ramped time varying signal generator that generates a ramped time varying signal that is coupled to the plurality of reference compare circuits, wherein the output signal of each reference compare circuit toggles when a level of its reference signal is exceeded by a level of the ramped time varying signal; a memory cell signal generator that generates a memory cell signal that is coupled to the memory cell signal compare circuit, wherein the output signal of the memory cell signal compare circuit toggles in response to the memory cell signal; and a plurality of latches, each latch coupled to the memory cell signal compare circuit and a single reference compare circuit, wherein each latch latches the output of the memory cell signal compare circuit in response to the output of its coupled reference compare circuit.