Patent ID: 9208884
Filing Date: 2015-12-08
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a first memory string including a first selection transistor, a first dummy cell, a second dummy cell, a first memory cell, a second memory cell, and a second selection transistor, the second selection transistor being disposed above a semiconductor substrate, the second memory cell being disposed above the second selection transistor, the first memory cell being disposed above the second memory cell, the first selection transistor being disposed above the first memory cell, the first dummy cell and the second dummy cell being disposed between the first selection transistor and the first memory cell; and a controller configured to perform an erase operation on a condition where a first voltage is applied to a gate of the first dummy cell, a second voltage is applied to a gate of the second dummy cell, and the second voltage is different from the first voltage.