Patent ID: 6115242
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A chip chassis for housing a plurality of semiconductor devices having electrical contacts, the chip chassis comprising:a housing, wherein the housing includes a plurality of slots, wherein each of the plurality of slots is configured to receive a particular type of semiconductor device;wherein the housing further comprises a plurality of connectors comprised in each of the slots, wherein each of the plurality of connectors within a respective slot of the housing is configured to physically and electrically contact corresponding electrical contacts of the package of the particular type of semiconductor device when the particular type of semiconductor device is inserted within the respective slot;wherein the housing includes signal traces defining an electrical backplane;wherein each of the plurality of connectors comprised in each of the slots includes an internal bus connector, wherein said internal bus connectors are electrically coupled through the electrical backplane to provide command pathways and data pathways among only the semiconductor devices placed within the housing;wherein each of the plurality of connectors comprised in each of the slots is electrically coupled through the electrical backplane within the housing for electrical communications between each of the slots.