Patent ID: 6753697
Filing Date: 2004-06-22
Classification: H03K

Abstract:
A semiconductor device comprising:an internal circuit receiving a first power supply potential as an operating power supply potential, and outputting a first internal signal; and an interface circuit receiving, as the operating power supply potential, a second power supply potential capable of being maintained in an active state even if said first power supply potential is set in an inactive state, and driving an output node in accordance with said first internal signal, said interface circuit including a first level conversion circuit, said first level conversion circuit having a first holding circuit holding one of a first logical value and a second logical value complementary to said first logical value, a first write circuit writing one of said first and second logical values to said first holding circuit in accordance with said first internal signal, and a second write circuit writing said second logical value to said first holding circuit in accordance with an enable signal, and said interface circuit further including a driving section driving said output node if said first holding circuit holds said first logical value, and turning into a high impedance state with respect to said output node if said first holding circuit holds said second logical value.