Patent ID: 7053677
Filing Date: 2006-05-30
Classification: G06F,H03K

Abstract:
1. An input/output (IO) device comprising: an IO device input node configured to receive an input data bit signal that varies between ground and a first voltage; an IO device output node; and a driver coupled between the IO device input node and the IO device output node, wherein the driver is configured to generate a voltage and current at the IO device output node in response to receiving the input data bit signal, wherein the voltage generated by the driver varies substantially linearly with the current generated by the driver as the voltage generated by the driver varies over a substantially entire driven range, wherein the driver is configured to receive a second voltage, wherein the driver is configured to charge and discharge the IO device output node to the second voltage and ground, respectively, in response to the driver receiving the second voltage and the input data bit signal, and wherein the second voltage is greater than the first voltage; wherein the driver comprises: first and second p-channel FETs each comprising a second, drain, and gate; first and second n-channel FETs each comprising a source, drain, and gate; wherein the gates of the first n-channel FET and the second p-channel FET are coupled to the IO device input node; wherein the drains of the first p-channel FET and the second n-channel FET are coupled to the IO device output node; wherein the source of the second n-channel FET is coupled to the drain of the first n-channel FET; wherein the source of the first p-channel FET is coupled to the drain of the second p-channel device.