Patent ID: 7701778
Filing Date: 2010-04-20
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a plurality of memory blocks, each of the memory blocks having a plurality of memory cells arranged in matrix form, gate electrodes of said memory cells arranged in the same row being connected to corresponding one of word lines and drain electrodes of said memory cells arranged in the same colunm being connected to corresponding one of bit lines; a plurality of block source lines corresponding to said memory blocks, said block source lines arranged in parallel to said word lines, source electrodes of said memory cells being commonly connected to corresponding one of said block source line; a plurality of source line driver circuits corresponding to said block source lines, said plurality of source line driver circuits driving corresponding one of said block source lines; a plurality of global source lines arranged in perpendicular to said block source lines; a plurality of switches for selectively connecting corresponding ones of said block source lines and said global source lines; and a plurality of program verification circuits for verifying in parallel whether program operations to said memory cells are completed or not by flowing current through a corresponding one of said block source lines, said global source lines, and said memory cells.