Patent ID: 8130892
Filing Date: 2012-03-06
Classification: H03L

Abstract:
1. An ADPLL frequency synthesizer comprising: a digital controlled oscillator operable to output a signal having a predetermined oscillatory frequency; a digital phase comparator operable to compare a phase of the oscillatory frequency of the digital controlled oscillator with a reference phase and operable to generate a phase error signal representing a difference between the phase of the oscillatory frequency of the digital controlled oscillator and the reference phase; a loop filter operable to control the oscillatory frequency of the digital controlled oscillator based on the phase error signal generated by the digital phase comparator; and a control sensitivity estimation section operable to estimate a control sensitivity of the digital controlled oscillator, wherein the control sensitivity estimation section calculates two control sensitivities at dummy frequencies which are, respectively, lower and higher than an oscillatory frequency to be set, so as to estimate a mean value of the calculated two control sensitivities as a first control sensitivity, and to estimate a second control sensitivity at the oscillatory frequency to be set, and wherein the loop filter updates a filter coefficient based on the first and second control sensitivities.