Patent ID: 7053634
Filing Date: 2006-05-30
Classification: H01L

Abstract:
1. A test pattern, used for testing a contact resistance of a subject via hole of a semiconductor substrate, comprising: a first conductive pattern connected to the subject via hole and formed on a lower surface of the semiconductor substrate; a second conductive pattern connected to the subject via hole and formed on an upper surface of the semiconductor substrate; first and second electrodes formed on the second conductive pattern, the electrodes for connection to test probes; third and fourth electrodes formed on the upper surface of the semiconductor substrate; a first test via-hole formed through the semiconductor substrate to connect the first conductive pattern and the third electrode electrically to each other; and a second test-via hole formed through the semiconductor substrate to connect the first conductive pattern and the fourth electrode electrically to each other, wherein the first and third electrodes are connected to a current test probe so as that a test current is flowing through the first electrode, the subject via hole, the first test via-hole and the third electrode in this order, and wherein the second and fourth electrodes are connected to a voltage test probe so as that a test voltage is applied through the second electrode, the subject via hole, the second test via-hole and the fourth electrode in this order.