Patent ID: 6888913
Filing Date: 2005-05-03
Classification: H03K,H03L

Abstract:
1. A programmable high speed counter apparatus, comprising: a prescaler having a prescaler clock input, first and second control inputs, and a prescaler output clock having a quad-modulus counter with a divide ratio determined by the first and second control inputs, an integer portion of the divide ratio based in part on the first control input and a fractional portion of the divide ratio based in art on the second control input; and first, second and third programmable counters each having programmable counter inputs to receive data indicative of a respective count value and a clock input coupled to the prescaler output clock, the first control input having a first logic level while the second counter is in a non-zero stale and the second control input having the first logic level while the third counter is in a non-zero state.