Patent ID: 7452801
Filing Date: 2008-11-18
Classification: H01L

Abstract:
1. A method of fabricating a metal interconnection structure of a semiconductor device having a low resistance, comprising: forming a first metal film pattern on an upper part of an insulation film of a semiconductor substrate; forming an intermetallic dielectric film on the insulation film and the first metal film pattern; removing a portion of the intermetallic dielectric film to form a via-hole exposing a partial surface of the first metal film pattern; forming a first metal contact plug having a first specific resistance on the first metal film pattern such that a lower part of the via-hole is embedded; forming a metal film having a second specific resistance lower than the first specific resistance on the intermetallic dielectric film and the first metal contact plug within the via-hole; and patterning the metal film of the upper part of the intermetallic dielectric film to form a second metal contact plug and second metal film pattern embedding the via-hole in conjunction with the first metal contact plug.