Patent ID: 8848416
Filing Date: 2014-09-30
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device comprising: a memory cell array including a plurality of memory cells; a plurality of fuse blocks, each fuse block being connected to a power-supply wire and to a ground wire, each fuse block including a plurality of fuse pieces arranged in a juxtaposed manner and exposed to an outside through a fuse window, each fuse block storing a defective memory address determined by a mode of cutting the fuse pieces, with the power-supply wire and the ground wire extending along a direction in which the fuse pieces are juxtaposed; a selection circuit that selects one of the memory cells based on a comparison of a memory address indicated by an access signal to said one of the memory cells with the defective memory address; a gate array that processes data corresponding to the memory cell selected by the selection circuit upon receiving a power-supply potential and a ground potential, with the plurality of fuse blocks being arranged in a line in the vicinity of the gate array; an additional pattern connected to a same potential as that of one of the power-supply wire and the ground wire which is farther away from the gate array, the additional pattern extending so as to avoid the fuse window; and a supply wire through which a potential of the additional pattern is supplied to the gate array.