Patent ID: 6256234
Filing Date: 2001-07-03
Classification: G11C,H03K

Abstract:
An input buffer comprising:first and second inverter circuits each coupled between a supply node and a reference node, the first and second inverter circuits having respective control nodes coupled to receive respective true and complementary input clock signals and having output nodes for outputting respective true and complementary amplified signals;third and fourth inverter circuits each coupled between the supply node and the reference node, the third and fourth inverter circuits having control nodes coupled to receive the respective true and complementary input clock signals and having mutually coupled output nodes;a first current source having an input node coupled to a supply voltage, a control node coupled to the output nodes of the third and fourth inverter circuits, and an output node coupled to the supply node; anda second current source having an output node coupled to a reference voltage, a control node coupled to the output nodes of the third and fourth inverter circuits, and an input node coupled to the reference node.