Patent ID: 6111809
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A line decoder for a memory device comprising:a first reference line placed at a first reference potential;a second reference line placed at a second reference potential switchable between said first reference potential and at least one programming potential having a value higher than said first reference potential;at least one final decoding circuit comprising an input circuit connected to said first reference line and receiving a predecoding signal, an output biasing circuit generating a biasing signal, and a switch circuit electrically coupled between said input circuit and said output biasing circuit, said switch circuit receiving a driving signal for selectively breaking the electrical connection between said input circuit and said output biasing circuit on the basis of the driving signal;a voltage elevator means connected to said second reference line, receiving a control signal, and generating at an output thereof a third reference potential, switchable on the basis of said control signal, between said first reference potential, said programming potential, and a boosted potential having a value between said first reference potential and said programming potential; anda third reference line connected to said output of said voltage elevator means and to said biasing circuit.