Patent ID: 7218309
Filing Date: 2007-05-15
Classification: G09G

Abstract:
1. A display apparatus for performing plural pixel simultaneous sampling, comprising: a pixel array section including a plurality of gate lines extending in a direction of a row, a plurality of signal lines extending in a direction of a column, and a plurality of pixels arranged in rows and columns at points at which said gate lines and said signal lines intersect with each other; a vertical drive circuit connected to said gate lines for successively selecting said rows of said pixels; n video lines divided into upper and lower side groups of video lines disposed on the upper and lower sides of said pixel array section, respectively, for supplying n video signals separated in a predetermined phase relationship from each other; a sampling switch set including a plurality of switches divided into upper and lower side groups respectively disposed on the upper and lower sides of said pixel array section for said signal lines such that said upper side video lines are connected to corresponding ones of said signal lines through the switches of said upper side group while said lower side video lines are connected to corresponding ones of said signal lines through the switches of said lower side group and such that each signal line is connected to only one of said upper side video lines and said lower side video lines via said sampling switch set; and a pair of upper and lower side horizontal drive circuits for successively driving said switches of said sampling switch set such that each ones of the switches of said upper side group are driven simultaneously to sample the video signals of systems from said upper side video lines to the switches to write the video signals into the pixels of the selected row while each ones of the switches of said lower side group are driven simultaneously to sample the video signals of systems from said lower side video lines to the switches to write the video signals into the pixels of the selected row; and upper and lower side precharge lines disposed on the upper and lower sides of said pixel array section each for supplying a predetermined precharge signal and wherein the upper side precharge line is connected through switches of said upper side group to the corresponding signal lines, while said lower side precharge line is connected through switches of said lower side group to the corresponding signal lines, wherein one of each two adjacent ones of said signal lines is connected to one of said video lines of the upper side group while the other of the two adjacent signal lines is connected to one of said video lines of the lower side group; and wherein each of said gate lines in said pixel array section is disposed for a unit of two rows of said pixels between a pair of adjacent ones of said columns of said pixels, and said upper and lower side horizontal drive circuits write video signals of the opposite polarities to each other to adjacent ones of said pixels connected to a same gate line through the corresponding ones of said signal lines; and wherein said upper side horizontal drive circuit samples the video signals of a same polarity from said video lines of the upper side group to corresponding ones of said signal lines while said lower side horizontal drive circuit samples the video signals of a same polarity from said video lines of the lower side group to corresponding ones of said signal lines thereby to suppress the level of parasitic capacitance to be felt by each of said upper and lower side video lines to raise a margin against ghost.