Patent ID: 6214663
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A method of fabricating an integrated circuit field effect transistor, comprising:forming spaced apart source and drain regions in a semiconductor substrate and a gate electrode on said semiconductor substrate, between said spaced apart source and drain regions, said gate electrode including a gate electrode top, opposite said substrate;forming a first pad, electrically contacting one of said spaced apart source and drain regions, and extending onto said gate electrode top, to define a first pad sidewall on said gate electrode top, and a capping layer on said first pad, opposite said gate electrode top, to define a capping layer sidewall on said first pad; thenforming an insulating sidewall spacer on said first pad sidewall and on said capping layer sidewall; and thenforming a second pad, electrically contacting the other of said spaced apart source and drain regions, extending onto said gate electrode top, and contacting said insulating sidewall spacer and insulated from the first pad by said insulating sidewall spacer.