Patent ID: 6680861
Filing Date: 2004-01-20
Classification: G11C

Abstract:
A ferroelectric memory comprising:a first memory cell which is provided at a point where a first word line and a first or second bit line intersect, and has a first ferroelectric capacitor formed with a ferroelectric material as an insulating film, and a first transistor having a control electrode connected to the first word line, a first electrode connected to the first or second bit line, and a second electrode connected to a first electrode of the first ferroelectric capacitor; a first sense amplifier connected to the first and second bit lines, for amplifying a signal read from the first memory cell; a second memory cell which is provided at a point where a second word line and a third or fourth bit line intersect, and has a second ferroelectric capacitor formed with a ferroelectric material as an insulating film, and a second transistor having a control electrode connected to the second word line, a first electrode connected to the third or fourth bit line, and a second electrode connected to a first electrode of the second ferroelectric capacitor; a second sense amplifier connected to the third and fourth bit lines, for amplifying a signal read from the second memory cell; a first switch for electrically connecting the first bit line and the third bit line; and a second switch for electrically connecting the second bit line and the fourth bit line.