Patent ID: 6153455
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method of fabricating a transistor having a lightly doped drain region, comprising the sequential steps of:(a) forming a gate having side edges in an active region of a substrate, said active region defined by field oxide regions;(b) forming an oxide layer over said gate;(c) forming a nitride layer over said oxide layer;(d) isotropically etching said nitride layer to form nitride sidewall spacers about said side edges of said gate;(e) implanting heavily doped source and drain regions in said substrate in a region adjacent to said nitride sidewall spacers;(f) removing said nitride sidewall spacers;(g) isotropically etching said oxide layer to form oxide sidewall spacers; and(h) implanting a lightly doped drain region in said substrate between one of said side edges of said gate and said heavily doped drain region.