Patent ID: 6738293
Filing Date: 2004-05-18
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising:a memory cell array including memory cells arranged in a matrix form having rows and columns, each of the memory cells having a drain, a source, a floating gate, and a control gate, and being arranged, so as to be stored data by varying a threshold voltage in dependence upon an amount of electrons injected in the floating gate; row lines, to each of which the control gates of the memory cells in the same row are commonly connected; column lines, to each of which the drains of the memory cells in the same column are commonly connected; a row decoder for selecting the row line; a column decoder for selecting the column line; data detecting means for detecting data stored in the memory cell, which is selected by the row decoder and the column decoder; data writing means for injecting electrons to the floating gate of the memory cell, which is selected by the row and column decoders, to set a first predetermined threshold voltage in order to write at least one of binary data items in the memory cell; data erasing means for allowing the floating gates of the memory cells that are commonly connected to the same column line and a plurality of row lines to simultaneously discharge electrons, then injecting electrons to the floating gates of the memory cells, and setting a second predetermined threshold voltage having a positive value which is lower than that of the first predetermined threshold value in order to store at least the other of the binary data items; and current breaking means for disconnecting a current path from the selected column line via the discharged memory cells which are connected to the row lines, to the row lines not the selected memory cell but non-selected memory cells being connected, from the floating gates of the discharged memory cells electrons being discharged by the data erasing means, when electrons are injected to the floating gate of the selected memory cell by the data erasing means, or data is read out from the selected memory cell, electrons are injected to the floating gates of the memory cells by the data erasing means, and thereafter, electrons are selectively injected to the floating gate of the memory cell by the data writing means; a programming voltage is applied to the control gate of the memory cell in order to inject electrons to the floating gate of the memory cell, the value of the programming voltage, to be applied to the control gate thereof, at the time of the injection of electrons performed by the data writing means being higher than the value of the programming voltage, to be applied to the control gate thereof, at the time of the injection of electrons performed by the data erasing means.