Patent ID: 6051984
Filing Date: 2000-04-18
Classification: G01R

Abstract:
A method of hot-carrier reliability testing on a plurality of MOS transistors formed on a substrate of a semiconductor wafer, comprising the steps of:forming a built-in multi-voltage supplier in the semiconductor wafer, the built-in multi-voltage supplier being capable of supplying al least four testing voltages including at least one gate voltage and at least a first drain voltage, a second drain voltage, and a third drain voltage;dividing the MOS transistors undergoing testing into at least three groups, wherein the at least three groups include a first group of MOS transistors, a second group of MOS transistors, and a third group of MOS transistors; connecting the gate voltage to at least one gate of all of the MOS transistors under testing, wherein the MOS transistors are all the same;connecting the first drain voltage to at least one drain of all of the first group of MOS transistors under testing;connecting the second drain voltage to at least one drain of all of the second group of MOS transistors under testing;connecting the third drain voltage to at least one drain of all of the third group of MOS transistors under testing; andmeasuring the electrical characteristics of the MOS transistors undergoing testing based on the application of the gate voltage, the first drain voltage, the second drain voltage, and the third drain voltage thereto.