Patent ID: 7385421
Filing Date: 2008-06-10
Classification: H03K

Abstract:
1. A hierarchical interconnect architecture for a field programmable gate array integrated circuit including a plurality of logic function blocks, the architecture including: a first level including a plurality of first groups of functional logic blocks at a first level, each first group spanning a first length and a first width, the first level including a set of first routing resources; a second level including a plurality of second groups of functional logic blocks at a second level, the number of functional logic blocks in the second groups greater than the number of functional logic blocks in the first groups, each second group spanning a second length and a second width, the second level including a set of second routing resources; a third level including a plurality of third groups of functional logic blocks at a third level, the number of functional logic blocks in the third groups greater than the number of functional logic blocks in the second groups, each third group spanning a third length and a third width, the third level including a set of third routing resources; wherein the set of first routing resources includes: wherein the set of second routing resources includes a plurality of expressway routing channels including a plurality of interconnect conductors configured to make programmable connections between different ones of the functional logic blocks in the second group and to interconnect conductors in the set of third routing resources; wherein the set of third routing resources includes a plurality of freeway routing channels associated with each third group of functional logic blocks, each freeway routing channel associated with one of the third groups including a plurality of interconnect conductors configured to make programmable connections to functional logic blocks in other ones of the third groups; and wherein programmable connections are made using reprogrammable elements.