Patent ID: 7332926
Filing Date: 2008-02-19
Classification: G01R

Abstract:
1. A semiconductor test apparatus, comprising: differential signal timing measurement means for outputting cross point information obtained by measuring a timing of a cross point of one of differential signals output from a device under test (DUT); non-differential signal timing measurement means for outputting data change point information obtained by measuring a timing of transition of a logic of the other non-differential signal output from the DUT; phase difference calculation means for outputting a phase difference ΔT obtained by calculating a relative phase difference between the cross point information and the data change point information which are obtained by simultaneously measuring both of the output signals; and PASS/FAIL determination means for determining PASS/FAIL of a relative positional relation of the DUT based on predetermined upper and lower limit threshold values for executing PASS/FAIL determination upon reception of the phase difference ΔT or one of the threshold values; wherein said differential signal timing measurement means includes cross point calculation means for specifying a position of intersection of both straight lines as the cross point information, the straight lines being a first straight line which passes between the two bits of timing information obtained from the transition waveform of one of the output differential signals, and a second straight line which passes between the two bits of timing information obtained from the transition waveform of the other of the output differential signals.