Patent ID: 9190283
Filing Date: 2015-11-17
Classification: C23C,H01L

Abstract:
1. A method of electroless coating of a silicon substrate, covered with a layer of an electrically insulating material, and having a collection of cavities suitable for forming through-vias useful for the fabrication of integrated circuits in three dimensions, said method comprising coating the insulating surface of said cavities with a metallic layer that forms a barrier to the diffusion of copper and comprises a material based on nickel or cobalt, wherein the method comprises contacting the insulating surface of said cavities with an aqueous solution comprising: at a temperature between 50° C. and 90° C., for a time between 30 s and 30 min, to form a metallic layer having a thickness of at least 6 nanometers at the bottom of the cavities, and subsequent to the step of formation of the barrier layer, filling the cavities with copper without having first formed a copper seed layer on the surface of the barrier layer.