Patent ID: 6018484
Filing Date: 2000-01-25
Classification: G11C

Abstract:
A device for loading data in a random access memory device having a memory array of memory cells arranged in rows, and a plurality of bit line pairs, each bit line of said bit line pairs being connected to a column of memory cells within said memory array, said device comprising:at least one data line;at least one control line;a plurality of transistors, each transistor being connected to said data line and to one of said bit line pairs, each transistor having a control element being connected to said control line;a means for selectively driving said control line to voltage level to turn on said transistors;a dummy transistor connected to at least one bit line of said bit line pairs for balancing the capacitances between said bit line pairs;a means for selectively driving said data line to a first voltage level representative of a high logic level and a second voltage level representative of a low logic level, for loading said voltage levels onto said bit lines when said transistors are turned on; anda means for selectively storing said voltage levels into a row of memory cells following loading of said voltage levels onto said bit lines.