Patent ID: 7502262
Filing Date: 2009-03-10
Classification: G11C,H01L

Abstract:
1. A NAND type flash memory array comprising: one or more bit lines on an SOI substrate; a first selective gate line arranged vertically to the bit lines; a plurality of word lines arranged vertically to the bit lines; a second selective gate line arranged vertically to the bit lines; a common source line arranged vertically to the bit lines; a plurality of memory cells connected in series with a first selective transistor and a second selective transistor along each bit line; and one body biasing contact region, wherein the body biasing contact region is located right next to the second selective gate line and connected to one side of an active region just below the second selective gate line when viewed in plan view, and wherein N-type impurities are injected into a source/drain region (common source/drain region) of the memory cells, which are connected to each bit line in series, the depth of the junction is so shallow that a conduction path can be formed on a lower part of the common source/drain region and within the body biasing contact region.