Patent ID: 7605432
Filing Date: 2009-10-20
Classification: H01L

Abstract:
1. A CMOS arrangement of transistors formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said CMOS arrangement comprising a first CMOS pair, said first CMOS pair comprising a first PMOS and a first NMOS, and a second CMOS pair, said second CMOS pair comprising a second PMOS and a second NMOS: said first PMOS comprising: said first NMOS comprising: said second PMOS comprising: said second NMOS comprising: wherein said second P-type drain region is separated by a first offset distance from said third gate and said channel region underlying said third gate and said first P-type drain region is separated by a second offset distance from said first gate and said channel region underlying said first gate, said first offset distance being greater than said second offset distance; wherein said second N-type drain region is separated by a third offset distance from said fourth gate and said channel region underlying said fourth gate and said first N-type drain region is separated by a fourth offset distance from said second gate and said channel region underlying said second gate, said third offset distance being greater than said fourth offset distance; and wherein said first P well comprises an implanted P layer, said P layer comprising a deep section in said central portion of said first P well, shallow sections in said side portions of said first P well, and transition sections connecting said deep section and said shallow sections of said P layer, said implanted P layer having a doping concentration greater than a doping concentration of a remaining portion of said first P well.