Patent ID: 8316338
Filing Date: 2012-11-20
Classification: G06F,H04L

Abstract:
1. A method of simplifying a combinational circuit, comprising: establishing an initial combinational circuit operable to calculate at least one target signal by using a computer, the initial combinational circuit including multiplication operations corresponding to logical AND gates in the initial combinational circuit and addition operations corresponding to logical XOR gates in the initial combinational circuit; reducing a quantity of multiplication operations performed in a first portion of the initial combinational circuit to create a first, simplified combinational circuit, the first portion including only multiplication operations and addition operations; reducing a quantity of addition operations performed in a second portion of the first, simplified combinational circuit to create a second, simplified combinational circuit, the second portion including only addition operations, wherein the second, simplified combinational circuit is operable to calculate the at least one target signal using fewer multiplication and fewer addition operations than the initial combinational circuit, wherein said reducing a quantity of multiplication operations comprises: a) identifying the first portion of the combinational circuit, the first portion being operable to calculate a first target signal, and the first portion including only a plurality of multiplication and addition operations; b) establishing a set of signals including a plurality of input signals; c) adding randomly, through use of a computer, at least one pair of the input signals together to determine at least one sum; d) expanding the set of signals to include the at least one sum; e) multiplying randomly, through use of the computer, at least two signals in the set of signals to determine at least one product; f) expanding the set of signals to include the at least one product; and g) selectively repeating steps C-F until the first target signal is found or until a quantity of multiplication operations performed in step E reaches a maximum number of desired multiplication operations.