Patent ID: 6605494
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:forming a gate electrode on a first portion of a transparent insulating substrate; forming an insulating layer on said gate electrode and on a second portion of said substrate other than said first portion; forming a first semiconductor layer on said insulating layer in correspondence with said gate electrode during a first deposition process, said first semiconductor layer being undoped; successively forming (a) a second semiconductor layer, (b) an ohmic contact layer that is heavily doped with a first conductivity type impurity, and (c) a conductive metal layer on the insulating layer and said first semiconductor layer; patterning the conductive metal layer to form source and drain electrodes; removing portions of said ohmic contact layer and said second semiconductor layer between said source and drain electrodes so as to expose portions of the first semiconductor layer and removing portions of said ohmic contact layer and said second semiconductor layer between respective edges of the semiconductor device and said source and drain electrodes to expose portions of the insulating layer; forming a blanket passivation layer covering the semiconductor device, including the drain electrode; forming a contact hole in the passivation layer to expose a portion of the drain electrode; and forming a pixel electrode on said passivation layer; said pixel electrode being electrically connected to said drain electrode through the contact hole.