Patent ID: 8196088
Filing Date: 2012-06-05
Classification: H01L

Abstract:
1. A method of measuring PFET-to-NFET device performance offset in a CMOS process, the method comprising: automatedly determining first frequencies of a model of a first complementary ring oscillator design in which all transistors therein are PFETs, the first frequencies corresponding respectively to differing sets of parameter values of the CMOS process; automatedly determining second frequencies of a model of a second complementary ring oscillator design in which all transistors therein are NFETs complementary to the PFETs of the first complementary ring oscillator, the second frequencies corresponding respectively to the differing sets of the parameter values of the CMOS process; and defining test screening limits as a function of the first and second frequencies; wherein said defining of the test screening limits includes: wherein: