Patent ID: 8975948
Filing Date: 2015-03-10
Classification: H03K

Abstract:
1. An apparatus comprising: an analog input line; an analog output line; a first transistor having a first drain electrically connected to the analog input line, a first gate electrically connected to a voltage input node, and a first source electrically connected to an analog signal node; a second transistor; a third transistor; wherein the second transistor and the third transistor are electrically connected between the voltage input node and the analog signal node wherein: the second transistor has a second drain and a second gate electrically connected to the voltage input node, and the third transistor has a third drain and third gate both electrically connected to a second source of the second transistor and a third source electrically connected to the analog signal node; a fourth transistor having a fourth source electrically connected to the analog signal node, a fourth gate electrically connected to the voltage input node, and a fourth drain electrically connected to the analog output line; a current source electrically connected to provide a bias current into the voltage input node; a current sink electrically connected to sink current from the analog signal node.