Patent ID: 9105650
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A method of forming a lateral bipolar transistor, the method comprising: forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer; forming a dummy gate and spacer on top of the silicon on insulator layer; initially doping the SOI layer at opposing sides of the dummy gate and spacer with dopant atoms of a first polarity type so as to define emitter and collector regions of the lateral bipolar transistor; depositing an interlayer dielectric (ILD); planarizing the ILD by chemical mechanical planarization (CMP); removing the dummy gate to form a gate trench which reveals only a base of the dummy gate, the base of the dummy gate comprising a portion of the SOI layer not initially doped; doping the dummy gate base with dopant atoms of a second polarity type opposite the first polarity type so as to define a base region of the lateral bipolar transistor; depositing a layer of polysilicon on top of the SOI layer and into the gate trench after doping the dummy gate base; etching the layer of polysilicon so that it only covers the dummy gate base; and applying a self-aligned silicide process.