Patent ID: 7595525
Filing Date: 2009-09-29
Classification: H01L,Y10S

Abstract:
1. A capacitor formed as part of an integrated circuit (IC) fabrication process, comprising: a bottom conductive electrode formed on a semiconductor substrate; an antireflective nonconductive capacitor dielectric disposed over the bottom conductive electrode and comprising a first layer comprising a dielectric material, a second layer comprising an antireflective material, and a third layer comprising a dielectric material; the antireflective nonconductive capacitor dielectric having a first and a second edge which align with a first and a second edge of the bottom conductive electrode, respectively; and a top conductive electrode formed over the antireflective nonconductive capacitor dielectric, where the antireflective nonconductive capacitor dielectric mitigates adverse effects associated with reflections associated with forming the bottom conductive electrode; wherein at least one of: