Patent ID: 6793123
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A method for forming an electrical structure, comprising:providing a circuitized substrate that comprises a dielectric material and at least one metal layer; coupling a first stiffener to a first surface of the substrate, wherein the first stiffener includes a first stiffener material; coupling a second stiffener to a second surface of the substrate, wherein the second stiffener includes a second stiffener material; electrically coupling N semiconductor logic chips such that N is at least 2 to a memory chip by a direct interconnect path that includes a corresponding conductive member in electrical and mechanical contact with both an electrically conductive pad on a surface of the corresponding logic chip and a corresponding electrically conductive pad on a surface of the memory chip; and electrically coupling at least one chip to the substrate by corresponding solder interconnects, wherein the at least one chip is selected from the group consisting of the memory chip, a first logic chip of the logic chips, a second logic chip of the logic chips, . . . , a Nth logic chip of the N logic chips, and combinations thereof; and wherein each solder interconnect of the corresponding solder interconnects is in electrical and mechanical contact with both an electrically conductive pad on a surface of the substrate and an electrically conductive pad on a surface of the corresponding chip of the at least one chip.