Patent ID: 8612902
Filing Date: 2013-12-17
Classification: G03F,H01L

Abstract:
1. A method, in a data processing system, for performing retargeting in a multiple-pattern integrated circuit device design manufacturing process, comprising: performing, by a processor, for at least one element on at least one exposure of multiple-pattern integrated circuit device design after decomposition, a lithographic simulation analysis for a width and first space combination to generate a two-dimensional width and first space representation of lithographic variation, wherein the first space values are to a nearest element on a same exposure of the decomposed multiple-pattern integrated circuit device design; combining, by a processor, the two-dimensional width and first space representation of lithographic variation with second space of the element to a nearest element on pre-decomposed layout of the multiple-pattern integrated circuit device design to generate a three-dimensional representation of retargeting bias values, wherein the three-dimensional representation of retargeting bias values comprises a three-dimensional table of retargeting bias values for different combinations of width, first space to a nearest feature on a same exposure of the multiple-pattern integrated circuit device design when decomposed, and second space to a nearest feature in the pre-decomposed layout of multiple-pattern integrated circuit device design; responsive to a determination that the element requires a retargeting bias, selecting, by a processor, a retargeting bias for the element based on the three-dimensional representation of retargeting bias values; and controlling, by a processor, fabrication of the integrated circuit device design based on the selected retargeting bias for the element.