Patent ID: 6032082
Filing Date: 2000-02-29
Classification: G06F

Abstract:
A method of calculating a resistance of a selected wiring path in a semiconductor circuit having wiring layers and contact holes that connect wires formed on the wiring layers to each other, comprising the steps of:dividing a resistance of a contact hole into a first resistance in contact with a first wiring layer, a second resistance in contact with a second wiring layer, and an interlayer resistance; andcalculating a resistance of a selected wiring path using, as the resistance of the contact hole, the first resistance when the wires of the selected wiring path are on the first wiring layer, the second resistance when the wires of the selected wiring path are on the second wiring layer, and the sum of the first, second and interlayer resistances when the wires of the selected wiring path are on the first and second wiring layers.