Patent ID: 6781219
Filing Date: 2004-08-24
Classification: H01L,Y10S

Abstract:
An assembly having a semiconductor die having at least one integrated circuit therein having a first active surface having, in turn, at least one contact pad arranged thereon, and having a second surface and having a leadframe, the assembly comprising:an upper conductive planar leadframe member having an upper surface attached to at least a portion of the second surface of the semiconductor die using an electrically insulative adhesive, and having a lower surface, the upper conductive planar leadframe member subdivided into a plurality of portions, at least one portion of the plurality of portions having an exposed tab connected to the at least one integrated circuit of the semiconductor die; a lower conductive planar leadframe member having an upper surface mounted to the upper conductive planar leadframe member using a thin intervening layer of dielectric material for capacitance therebetween, the lower conductive planar leadframe member subdivided into a plurality of portions for matching corresponding portions of the plurality of portions of the upper conductive planar leadframe, the lower conductive planar leadframe member cooperating with the upper conductive planar leadframe member for capacitance purposes; at least one lead of a plurality of leads connecting the at least one contact pad to at least one lead finger; at least one other lead of the plurality of leads connected to the exposed tab of the at least one portion of the upper conductive planar leadframe member, and material encapsulating at least the semiconductor die.