Patent ID: 7397722
Filing Date: 2008-07-08
Classification: G11C

Abstract:
1. A memory, comprising: a first memory block; a second memory block; a data bus; a first sense amplifier coupled to the first memory block; a second sense amplifier coupled to the second memory block; a first circuit, coupled to the data bus and the first sense amplifier, that switches from precharging the data bus to providing data in response to a first sense enable signal when the first memory block is selected and wherein the first circuit is decoupled from the data bus in response to the first memory block being deselected; and a second circuit, coupled to the data bus and the second sense amplifier, that switches from precharging the data bus to providing data in response to a second sense enable signal when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.