Patent ID: 6369619
Filing Date: 2002-04-09
Classification: H03K

Abstract:
A voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage, comprising:an arbiter circuit receiving a predriver input through a passgate, the arbiter being configured to ensure that a gate of a P-driver transistor of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P-driver transistor is tri-stated, the output of the passgate being connected to the gate of the P-driver transistor; a bias circuit logically configured to bias a floating N-well of the P-driver transistor to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver transistor is forward biased; and a driver circuit comprising the P-driver transistor, one terminal of the P-driver transistor being coupled to input/output supply voltage and another terminal being coupled to the input/output voltage, and the passgate having a first gate coupled to the input/output voltage, and a second gate coupled concurrently to the bias circuit and the input/output voltage; wherein the arbiter circuit is logically configured to ensure that there is no DC leakage current between the input/output voltage and the input/output supply voltage, regardless of the difference in magnitude between the input/output voltage and the input/output supply voltage.