Patent ID: 6833316
Filing Date: 2004-12-21
Classification: H01L

Abstract:
A semiconductor device manufacturing method, comprising the steps of:(a) forming pad lower conductor structure over a semiconductor substrate, said pad lower conductor structure comprising a lower insulating layer and lower via conductors embedded in said lower insulating layer; (b) forming an insulating stack layer on said pad lower conductor structure, said insulating stack layer including a first insulating layer having an etching characteristic and a second insulating layer having an etching characteristic different from that of said first insulating layer; (c) forming an etching mask on said insulating stack layer, said etching mask comprising a first portion having an aperture defining a pad region and a second portion disposed in said aperture in the vicinity of at least one of said lower via conductors; (d) etching said insulating stack layer using said etching mask as a mask to form a pad groove in which said lower via conductors are exposed; and (e) embedding a pad conductor in said pad groove.