Patent ID: 6732062
Filing Date: 2004-05-04
Classification: H01L

Abstract:
An apparatus for analyzing a failure of a semiconductor device, which calculates a failure die number/rate, a failure bit map (FBM) yield and a die/sorting (D/S) yield on a test mode of each test wafer, the apparatus comprising:a wafer map memory for storing test result data of said each test wafer; a means for calculating a failure die number/rate, a D/S good die number/yield and a FBM good die number/yield on the test mode of said each test wafer; a means for storing the calculated values; a means for calculating, in case a failure bit mode to be defined is selected from a plurality of failure bit modes, a failure die rate for total dies and a failure die rate for total failure dies based on a total die number and a failure die number of the selected failure bit mode; a means for calculating an expected FBM yield based on the FBM yield and the failure die rate for the total dies and calculating an expected D/S yield based on the expected FBM yield, the FBM yield and the D/S yield; a means for calculating an average D/S yield of the selected failure bit mode based on the expected FBM yield, the FBM yield and the D/S yield of the selected test wafer; a means for calculating a maximum/minimum yield based on the expected FBM yield, and a minimum and a maximum deviation value between the FBM yield and the D/S yield; and a means for displaying the calculated values on a monitor.