Patent ID: 6620659
Filing Date: 2003-09-16
Classification: H01L,Y10S

Abstract:
A method of manufacturing a plurality of transistors in two distinct semiconductor levels in an integrated circuit (IC) chip comprising the steps of:forming n-type metal oxide semiconductor (NMOS) transistors on a bulk silicon (Si) level; depositing thick insulator on the bulk Si level; planarizing the deposited thick insulator; forming a thin film (TF) Si level on the planarized thick insulator; implanting a p-type dopant in the TF Si level; and forming p-type metal oxide semiconductor (PMOS) transistors in the TF Si level, wherein said n-type and said p-type transistors are connectable in selected regions of the IC chip to form either a logic circuit or a memory device, said selected regions being arbitrarily selectable in blocks as small as six transistors, said logic circuits and said memory devices being logically interconnected, and wherein each logic circuit logically interconnected with a memory device is connectable in physical proximity to said memory device.