Patent ID: 9000802
Filing Date: 2015-04-07
Classification: G06F,H03K

Abstract:
1. An integrated device comprising: a combiner circuit; a first multiplexer configured to provide one of a first data signal generated by a hard logic block and a zero value signal to the combiner circuit; and a second multiplexer configured to provide one of a second data signal generated by a soft logic module and the zero value signal to the combiner circuit; wherein the combiner circuit is configured to combine the signals provided by the first and second multiplexers and to output a combined signal; a configurable delay line configured to delay one of the first data signal and the second data signal and to output a delayed data signal; a third multiplexer configured to provide one of the first data signal and the delayed data signal to the first multiplexer; a fourth multiplexer configured to provide one of the second data signal and the delayed data signal to the second multiplexer; and control logic configured to control (i) which of the first data signal and the delayed data signal the third multiplexer provides to the first multiplexer, and (ii) which of the second data signal and the delayed data signal the fourth multiplexer provides to the second multiplexer.