Patent ID: 7439582
Filing Date: 2008-10-21
Classification: H01L,H03K

Abstract:
1. A power semiconductor device, comprising: first and second main terminals, at least one of which is for coupling a load; a control terminal; and a semiconductor body having opposed first and second major surfaces and a plurality of cells arranged as a lattice across the first major surface of the semiconductor body, the cells being divided into main cells and sense cells, each of the cells having a gate or base connected to the control terminal wherein each of the main cells is connected in parallel between the first and second main terminals to couple the first and second main terminals under the control of the control terminal; the power semiconductor device further comprises first and second sense terminals; the sense cells are divided into a plurality of groups of sense cells each arranged across the lattice in a pattern, each group of sense cells being connected in parallel between a respective sense terminal and the second main terminal; and a first group of sense cells is arranged across the lattice in a pattern having a different ratio of edge to inner cells to a second group of sense cells, inner sense cells being cells surrounded by other sense cells of the group and edge sense cells being arranged on the edge of the group of sense cells.