Patent ID: 8854106
Filing Date: 2014-10-07
Classification: H03K

Abstract:
1. A circuit comprising: a current mirror configured to generate a first bias current and a second bias current, said second bias current proportional to the first bias current with a first ratio; a first level shifter having a first input node configured to receive a reference input signal and having a first output node, said first level shifter coupled to the current mirror at said first output node and configured to apply a first voltage variation to the reference input signal in response to the first bias current so as to output a first output signal at said first output node; a second level shifter having a second input node configured to receive a sense input signal and having a second output node, said second level shifter coupled to the current mirror at said second output node and configured to apply a second voltage variation in association with the first voltage variation to the sense input signal in response to the second bias current so as to output a second output signal at said second output node; an output circuit coupled to receive the first and second output signals and generate an output in response thereto; and a first overvoltage protector coupled between the second level shifter and an input of the output circuit and configured to provide overvoltage protection for the output circuit.