Patent ID: 6418073
Filing Date: 2002-07-09
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory cell region formed by a plurality of memory cells; a plurality of word lines that select said memory cells; a word line drive circuit that, based on an externally supplied address signal, activates said word lines connected to the memory designated by that address; a bit line that is connected to a memory cell and reads information stored in said memory cell selected by the activated word line as a voltage change from a specified precharge voltage; a sense amplifier that amplifies the potential difference between bit line pairs, which are two adjacent bit lines combined together, and detects the data stored in said memory cell; a precharge circuit that precharges the potential of said two bit lines of said bit line pair connected to said sense amplifier before said word line selects said memory cell; and a precharge drive circuit that supplies a control signal of a specified H level voltage from a second n-channel type MOS transistor to a gate of an n-channel type first MOS transistor that forms said precharge circuit and supplies the precharge current to said bit line, wherein a voltage of an ON signal turns ON said second MOS transistor and is input into the gate of this second MOS transistor is equal to or greater than the voltage value equal to the sum of the voltage of said control signal and the threshold value voltage of the second MOS transistor.