Patent ID: 7790514
Filing Date: 2010-09-07
Classification: H01L

Abstract:
1. A manufacturing process for a chip package structure, comprising: providing a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer; forming a second patterned solder resist layer on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer; bonding a plurality of chips onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer; electrically connecting the chips to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer; forming at least one molding compound to encapsulate the patterned conductive layer, the first patterned solder resist layer, the second patterned solder resist layer, the chips and the bonding wires; and separating the molding compound, the first patterned solder resist layer and the second patterned solder resist layer.