Patent ID: 7883629
Filing Date: 2011-02-08
Classification: H01L

Abstract:
1. A method, comprising: forming a first stress-inducing layer above a first transistor and a second transistor, said first and second transistors formed above a first substrate; removing a portion of said first stress-inducing layer located above said second transistor; forming a second stress-inducing layer on said first stress-inducing layer and above a measurement site; removing a first portion of said second stress-inducing layer from above said first transistor on the basis of an etch process; forming a test structure including a grating pattern at said measurement site by etching a second portion of said second stress-inducing layer to define said grating pattern; and controlling at least one parameter of said etch process on the basis of optical measurement data collected from said grating pattern at said measurement site, said optical measurement data indicating an etch rate of said etch process.