Patent ID: 7915691
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A circuit, comprising: a first inverter comprising a first PFET and a first NFET, a source of said first PFET coupled to a first terminal of a power supply, a source of said first NFET coupled to a second terminal of said power supply, drains of said first PFET and said first NFET connected to a first storage node, gates of said first PFET and said first NFET connected to a second storage node, said first NFET being a FinFET; a second inverter comprising a second PFET and a second NFET, a source of said second PFET coupled to said first terminal of said power supply, a source of said second NFET coupled to said second terminal of said power supply, drains of said second PFET and said second NFET connected to said second storage node, gates of said second PFET and second NFET connected to said first storage node, said second NFET being a FinFET; a first FET connected between said first storage node and a first bitline, a gate of said first FET connected to a wordline, said first FET being a planar FET; and a second FET connected between said second storage node and a second bitline, a gate of said second FET connected to said wordline, said second FET being a planar FET.