Patent ID: 7885125
Filing Date: 2011-02-08
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a logic circuit supplied with a first supply voltage; a cell array supplied with a second supply voltage higher than said first supply voltage and including plural mutually intersecting word lines and bit lines and plural memory cells connected at intersections thereof; and a word line driver operative to drive said word lines, wherein said word line driver includes plural pull-up circuits connected between a supply terminal of said first supply voltage and a drive terminal of said word line and between a supply terminal of said second supply voltage and the drive terminal of said word line, and a pull-down circuit connected between the drive terminal of said word line and a ground terminal, and drives said word line with an intermediate voltage between said first and second supply voltages in accordance with a driving force ratio between said plural pull-up circuits at a time of driving said word line.