Patent ID: 6083815
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method for forming a gate electrode of a self-aligned gate MOSFET comprising:(a) providing a silicon wafer having:(i) a gate oxide;(ii) a first conductive layer overlying said gate oxide;(iii) second conductive layer overlying said first conductive layer;(iv) a native oxide layer formed on said second conductive layer;(v) a photoresist layer overlying said wafer and patterned to define a gate electrode;(b) providing a parallel plate high density plasma etcher having an anode plate whereupon wafers are placed and a non-erodible cathode plate in an evacuable chamber;(c) placing said wafer on said anode plate and evacuating said chamber;(d) etching said native oxide layer in a first gas flow containing fluorocarbons;(e) etching said second conductive layer in a second gas flow containing Cl.sub.2, He, and O.sub.2 to a first endpoint and continuing beyond said first endpoint for a first time period of between about 30 to 50 percent of the time to reach said first endpoint;(f) etching said first conductive layer in a third gas flow containing Cl.sub.2 and HBr to a second endpoint; and(g) etching said first conductive layer in a fourth gas flow containing HBr, He, and O.sub.2 for a second time period past said second endpoint thereby forming a gate electrode.