Patent ID: 6198379
Filing Date: 2001-03-06
Classification: G01L

Abstract:
A circuit arrangement implemented as an integrated semiconductor component and having a measured value acquisition circuit connectable to an analysis circuit, the circuit arrangement comprising:piezoresistive measuring shunts diffused on a semiconductor substrate, the analysis circuit including the piezoresistive measuring shunts;diffused terminal resistors having a negligible piezoresistive resistance, the diffused terminal resistors including identical, elongated, curved structures; andmetallic terminal contacts connected to the piezoresistive measuring shunts by the diffused terminal resistors,wherein each of the curved structures has a first end for coupling to one of the piezoresistive measuring shunts and a second end, opposite the first end, for coupling to one of the metallic terminal contacts, each of the curved structures tapering toward the first end, andwherein the first end expands from the taper to a rectangular or square shape.