Patent ID: 7936199
Filing Date: 2011-05-03
Classification: G06F

Abstract:
1. A clock generator comprising: a circuit node to provide an internal clock signal; a first clock buffer having an output; a first one-shot pulse generator communicatively coupled to the first clock buffer, the first clock buffer triggering a first signal from the first one-shot pulse generator to cause the internal clock signal to make a transition from a first signal level to a second signal level; a second clock buffer having an output, the second clock buffer substantially identical to the first clock buffer; a second one-shot pulse generator communicatively coupled to the second clock buffer, the second clock buffer triggering a second signal from the second one-shot pulse generator to cause the internal clock signal to make a transition from the second signal level to the first signal level, wherein a phase difference between the output of the first clock buffer and the output of the second clock buffer corresponds to a duty cycle time of an external clock signal; and a circuit for combining an output from the first one-shot pulse generator and an output from the second one-shot pulse generator to produce the internal clock signal, the circuit including a first multiplexer having an output directly coupled to the circuit node and to respond to a signal from the output of the first one-shot pulse generator to cause the internal clock signal to make the transition from the first signal level to the second signal level, and the circuit further including a second multiplexer having an output directly coupled to the circuit node and to respond to a signal from the output of the second one-shot pulse generator to cause the internal clock signal to make the transition from the second signal level to the first signal level, wherein the output of the first multiplexer and the output of the second multiplexer are coupled to the circuit node at the same time.