Patent ID: 8132064
Filing Date: 2012-03-06
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a test clock lead, a test mode select lead, and a select lead; B. a state machine connected to the test clock lead and the test mode select lead and having a select output, a clock output, a shift output, and an update output; C. an inverter having an input connected to the select lead and having an output; D. a first gate having an input connected to the output of the inverter and an input connected to the select output; E. a second gate having an input connected to the output of the inverter and an input connected to the clock output; F. a third gate having an input connected to the select lead and an input connected to the shift output; and G. a fourth gate having an input connected to the select lead and an input connected to the update output.