Patent ID: 6111434
Filing Date: 2000-08-29
Classification: H03K

Abstract:
A circuit, comprising:a dynamic logic circuit having an internal node and a pre-charge node;a first transfer device having a first terminal directly connected without any intervening elements to a first reference value, a second terminal directly connected without any intervening elements to the internal node, and a third terminal; anda second transfer device having a first terminal directly connected without any intervening elements to the third terminal of the first transfer device, a second terminal directly connected without any intervening elements to an enable signal, and a third terminal directly connected without any intervening elements to the pre-charge node, wherein the dynamic logic circuit comprises:a first transistor having a first terminal directly connected without any intervening elements to a second reference value, a second terminal directly connected without any intervening elements to a clock input signal, and a third terminal directly connected without any intervening elements to the internal node;a second transistor having a first terminal directly connected without any intervening elements to the internal node, a second terminal directly connected without any intervening elements to a first input signal, and a third terminal directly connected without any intervening elements to the pre-charge node;a third transistor having a first terminal directly connected without any intervening elements to the pre-charge node, a second terminal directly connected without any intervening elements to a second input signal, and a third terminal; anda fourth transistor having a first terminal directly connected without any intervening elements to the third terminal of the third transistor, a second terminal directly connected without any intervening elements to the clock input signal, and a third terminal directly connected without any intervening elements to a third reference value.