Patent ID: 7495281
Filing Date: 2009-02-24
Classification: G11C,H01L

Abstract:
1. A non-volatile memory device comprising a plurality of memory cell transistors, wherein each of the memory cell transistors comprises: a first gate insulation layer on a semiconductor substrate; a floating gate on the first gate insulation layer; a second gate insulation layer covering a top and sidewalls of the floating gate; a first sidewall selection gate on the second gate insulation layer at a first sidewall of the floating gate; a second sidewall selection gate on the second gate insulation layer at a second sidewall of the floating gate; an inter-gate dielectric layer on the first sidewall selection gate, the second gate insulation layer and the second sidewall selection gate; a control gate overlapping the floating gate on the inter-gate dielectric layer; a source region in the semiconductor substrate adjacent the first sidewall selection gate and spaced apart from the floating gate; and a drain region in the semiconductor substrate adjacent the second sidewall selection gate and spaced apart from the floating gate.