Patent ID: 6083792
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A process for manufacturing a split gate flash memory unit, comprising the steps of:(a) providing a silicon substrate having a first insulating layer, and forming a first conductive layer on said first insulating layer;(b) removing part of the first conductive layer to expose left and right sidewalls of said first conductive layer on said first insulating layer by the steps of:(b1) forming a photoresist layer on said first conductive layer; and(b2) etching part of said first conductive layer by photolithography and etching techniques to expose left and right sidewalls of said first conductive layer as well as part of said first insulating layer;(c) executing a chemical vapor deposition (CVD) process to form a second insulating layer on left and right sidewalls of said first conductive layer;(d) performing thermal oxidation process to form a third insulting layer on said first conductive layer, said second insulating layer, and another part area of said first conductive layer, said second insulating layer, and another part area of said first insulating layer, wherein by an isolation effect provided by said second insulating layer reduces a leaking phenomenon at left and right lower edges of said first conductive layer is reduced; and(e) forming a second conductive layer on said third insulating layer to form said split gage flash memory unit.