Patent ID: 7847344
Filing Date: 2010-12-07
Classification: G11C,H01L

Abstract:
1. A transistor, comprising: a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench, and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor; wherein the gate insulator includes oxide-nitride nanolaminate layers formed using atomic layer deposition techniques; wherein a nitride layer in the nanolaminate layers provides a positive conduction band offset with silicon; and operation circuitry coupled to the transistor to program the transistor in a reverse direction and to read the transistor in a forward direction.