Patent ID: 9201719
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A system for communicating between microprocessors comprising: a plurality of microprocessors configured to communicate commands and responses to the commands over a bus via a plurality of communication channels by time division multiplexing, a plurality of timeout timer devices wherein each one of the plurality of timeout timer devices is a separate physical entity and configured to be assigned to a corresponding one of the plurality of communication channels, via at least one of the microprocessors, and each is configured to measure a time period between a command and a corresponding response to the command over the corresponding channel indicating a successful or erroneous execution of the respective command, wherein at least two timeout timer devices are configured to be concurrently assigned to a particular one of the plurality of communication channels to concurrently detect a successful or erroneous execution of pipelined stream commands transmitted via the particular one of the communication channels, wherein at least one microprocessor of the plurality of microprocessors is further configured to communicate a second stream frame although an acknowledge or timeout to a first stream frame has not been received, and not communicate a third stream frame before the first stream frame is acknowledged.