Patent ID: 6812127
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method of fabricating a semiconductor integrated circuit device, comprising:(a) forming a lower layer dielectric film including a first silicon oxide film containing fluorine over a major surface of a wafer; (b) forming an upper layer dielectric film including a second silicon oxide film substantially without fluorine as compared with the first silicon oxide film over the first silicon oxide film, the upper and lower layer dielectric film constituting an inter-layer dielectric film having an inter-wiring layer portion embedded in the upper layer dielectric film and an inter-via layer portion embedded in the lower layer dielectric film respectively; (c) forming via holes through said upper dielectric film and said lower dielectric film and then forming wiring grooves in the upper dielectric film, wherein at least one of said wiring grooves includes one of said via holes in a grove pattern, said at least one of the wiring grooves and said one of said via holes are connected therethrough, and said at least one of the wiring grooves has an area larger than an area of said one of said via holes in plan view; (d) forming a barrier metal along said wiring grooves and via holes and then filling said at least one of the wiring grooves and said one of said via holes with copper so as to integrally form an embedded wiring and a copper plug electrically connecting the embedded wiring to a lower wiring or electrode, wherein a Young's modular of the lower dielectric film is smaller than that of the upper dielectric film.