Patent ID: 6097632
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A memory comprising:an array of floating gate memory cell transistors;a control circuit coupled to the array of floating gate memory cell transistors, for storing a charge on the floating gate memory cell transistors during a programming operation, and removing the stored charge from the floating gate memory cell transistors during an erase operation; anda source regulation circuit coupled to the array of floating gate memory cell transistors, for applying a ramped voltage signal to sources of the floating gate memory cell transistors during said erase operation,wherein the source regulation circuit comprises:a ramp generator for producing a ramped output voltage signal on an output node;a reference circuit for producing a reference voltage;a comparator circuit for comparing the ramped output voltage signal and the reference voltage, the comparator circuit having an output for providing an output signal in response to the ramped output voltage signal and the reference voltage; andan output circuit for producing the ramped voltage signal applied to the sources of the floating gate memory cell transistors.