Patent ID: 6310504
Filing Date: 2001-10-30
Classification: H03K,H04L

Abstract:
A data transmission circuit comprising:a driver for transmitting data signals;a data line through which a first data signal sent from the driver is transmitted to a second data signal;a compensation circuit for amplifying and developing the second data signal from its first state to its second state when the first data signal sent from the driver is enabled from its first state to its second state and transmitted through the data line to be the second data signal;a reset part for generating a pre-charge control signal by sensing that the first and second data signals are enabled to the second state thereof; anda delay circuit for generating a second precharge control signal by delaying the precharge control signal genersted from the reset part for a predetermined period of time; anda pre-charge circuit for precharging the first and second data signals to the first state thereof by the second pre-charge control signal.