Patent ID: 8835275
Filing Date: 2014-09-16
Classification: C23C,H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming device isolation regions in a substrate to define active regions; forming gate trenches in the substrate, wherein the gate trenches expose the active regions and the device isolation regions; conformally forming a preliminary gate insulating layer including silicon oxide on the exposed active regions in the gate trenches; nitriding the preliminary gate insulating layer by applying a radio-frequency (RF) bias at a frequency of about 13.56 MHz with power between about 100 W and about 300 W to form a nitrided preliminary gate insulating layer including silicon oxynitride; forming a gate barrier material layer on the nitrided preliminary gate insulating layer; forming a gate electrode material layer on the gate barrier material layer; partially removing the nitrided preliminary gate insulating layer, the gate barrier material layer, and the gate electrode material layer to respectively form a gate insulating layer, a gate barrier pattern, and a gate electrode layer; and forming a gate capping layer on the gate electrode layer, wherein the gate capping layer fills the gate trenches.