Patent ID: 6815355
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of forming a complimentary metal oxide semiconductor (CMOS), device on a semiconductor substrate, comprising the steps of:providing a first gate structure on an underlying gate insulator layer, located in a first region of said semiconductor substrate to be used for an N channel metal oxide semiconductor (NMOS), element of said CMOS device, and providing a second gate structure on said underlying gate insulator layer, located in a second region of said semiconductor substrate to be used for a P channel metal oxide semiconductor (PMOS), element of said CMOS device; forming an N type, source/drain extension (SDE), region in a portion of said first region of said semiconductor substrate not covered by said first gate structure; forming a P type, source/drain extension (SDE), region in a portion of said second region of said semiconductor substrate not covered by said second gate structure; depositing a composite insulator layer comprised of an underlying silicon oxide layer, a silicon nitride layer, and an overlying doped oxide layer; performing an anisotropic dry etch procedure to form a first composite insulator spacer comprised of an overlying doped oxide component, an L-shaped silicon nitride component, and an underlying L-shaped silicon oxide component, on the sides of said first gate structure, and to form a second composite insulator shape comprised of an overlying doped oxide component, an L-shaped silicon nitride component, and an underlying L-shaped silicon oxide component, on the sides of said second gate structure; forming a heavily doped P type source/drain region in a portion of said second region of said semiconductor substrate not covered by said second gate structure, or by said second composite insulator spacer; removing said doped oxide components resulting in a first L-shaped composite insulator spacer located on the sides of said first gate structure, and resulting in a second L-shaped composite insulator spacer located on the sides of said second gate structure; forming a first heavily doped N type source/drain region in a portion of said first region of said semiconductor substrate not covered by said first gate structure or by said first L-shaped composite spacer, and forming a second heavily doped N type source/drain region in a portion of said first region of said semiconductor substrate, directly underlying horizontal feature of said L-shaped silicon nitride component of said first L-shaped composite insulator spacer; and forming metal silicide layers on the top surface of said first gate structure, on the top surface of said second gate structure, on the top surface of said first heavily doped N type source/drain region, and on the top surface of said heavily doped P type source/drain region.