Patent ID: 6998877
Filing Date: 2006-02-14
Classification: H03K

Abstract:
1. A high-speed differential signaling logic gate comprises: a first input transistor having an input, a first node, and a second node, wherein the input of the first input transistor is operably coupled to receive a first input logic signal; a second input transistor having an input, a first node, and a second node, wherein the input of the second input transistor is operably coupled to receive a second input logic signal, wherein the first and second input transistors are coupled in parallel; a complimentary transistor having an input, a first node, a second node, wherein the second node of the complimentary transistor is operably coupled to the second nodes of the first and second input transistors, wherein the input of the complimentary transistor is operably coupled to receive a complimentary input signal; a current source operably coupled to the second nodes of the first and second input transistors and to a first potential; a first load operably coupled to the first nodes the first and second input transistors and to a second potential, wherein the coupling of the first load to the first nodes of the first and second input transistors provides a first leg of a differential logic output of the high-speed differential signaling logic gate; a second load operably coupled to the first node of the complimentary transistor and to the second potential, wherein the coupling of the second load to the first node of the complimentary transistor provides a second leg of the differential logic output; and a third load substantially equal to the first and second loads; and a second current source operably coupled to the third load, wherein the second current source provides approximately one-half the current as provided by the current source, and wherein the coupling of the third load to the second current source provides the complimentary input signal; wherein the high-speed differential signaling logic gate implements: