Patent ID: 8461008
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A method for fabricating a FinFET integrated circuit comprising: providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines; etching the semiconductor substrate to form a plurality of fins, each of the plurality of fins extending across the width of the chips substantially to the scribe lines; depositing an oxide to fill between the fins; etching the oxide to recess the oxide; oxidizing the plurality of fins; depositing and patterning an isolation hard mask overlying the plurality of fins; etching the semiconductor substrate using the isolation hard mask as an etch mask to form trenches in the semiconductor substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins; and filling the trenches with an insulating material to isolate between adjacent ones of the plurality of active areas, wherein oxidizing the plurality of fins is performed after etching the oxide and before depositing and patterning an isolation hard mask.