Patent ID: 6115730
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A floating point unit comprising:a bus;an array of registers for holding a series of input operands, said array of registers coupled to said bus;an adder having a first input for receiving a first input operand for a first instruction from said array of registers, a second input for receiving a second input operand for said first instruction and an output for writing a result produced by executing said first instruction to said array of registers, said first input, said second input and said output coupled to said bus;a first latch coupled to said bus and said first input of said adder, said first latch holding a first input operand for said first instruction;a second latch coupled to said bus and said second input of said adder, said second latch holding a second input operand for said first instruction;a first preload register coupled to said bus for holding a first input operand for a next instruction and having an output coupled to said first and second latches;a second preload register coupled to said bus for holding a second input operand for said next instruction and having an output coupled to said first and second latches;wherein said first input operand for said next instruction may be selectively placed in either said first or second latch;wherein said second input operand for said next instruction may be selectively placed in either said first or second latch; and,a multiplier having a first input for receiving a first input operand for a first instruction from said array of registers, a second input for receiving a second input operand for said first instruction and an output for writing a result produced by executing said first instruction to said array of registers, said first input, said second input and said output coupled to said bus;wherein said first operand placed in said first preload register and said second operand placed in said second preload register may be selectively propagated to said adder as said first and second input operands for said next instruction or to said multiplier as first and second input operands for a next instruction.