Patent ID: 6536001
Filing Date: 2003-03-18
Classification: H03M

Abstract:
A rate adaptable memory address pointer for convolutional interleaving of codewords of varying byte lengths comprising:an interface configured to receive an interleaving depth signal, an address increment signal, a base address signal, a codeword length signal, and a pointer initialize signal; a multiplexer configured to receive the pointer initialize signal, the base address signal, and a second input signal, the multiplexer configured to select one of the base address signal and second input signal in response to the pointer initialize signal to create a multiplexer output signal; an adder configured to mathematically combine the multiplexer output signal and the interleaving depth signal to create a first counter input signal; a counter configured to receive the first counter input signal and an address increment signal, the counter configured to generate a counter output signal; and a modulo operator configured to receive the counter output signal and the codeword length signal to generate a memory address pointer control signal.