Patent ID: 7178010
Filing Date: 2007-02-13
Classification: G06F

Abstract:
1. An apparatus for correcting a call/return stack in a pipelined microprocessor, the apparatus comprising: a first stack, comprising a first plurality of entries for storing correction information related to call or return instructions present in a first plurality of stages of the microprocessor pipeline; a second stack, coupled to said first stack, comprising a second plurality of entries for storing correction information related to call or return instructions present in a second plurality of stages of the microprocessor pipeline; control logic, coupled to said first and second stacks, for receiving a first control signal indicating a call or return instruction is passing from said first plurality of stages to said second plurality of stages, wherein said control logic moves said correction information associated with said call or return instruction from said first stack to said second stack in response to said first control signal; a second control signal, received by said control logic, for indicating said call or return instructions present in said first plurality of pipeline stages were speculatively incorrectly executed, wherein said control logic corrects the call/return stack using said correction information stored in said first plurality of entries of said first stack, in response to said second control signal; and a third control signal, received by said control logic, for indicating said call or return instructions present in said first and second plurality of pipeline stages were speculatively incorrectly executed, wherein said third control signal indicates an instruction preceding said call or return instructions present in said first and second plurality of pipeline stages generated a microprocessor exception.