Patent ID: 8072811
Filing Date: 2011-12-06
Classification: G11C,H01L

Abstract:
1. A NOR flash nonvolatile memory circuit comprising: a plurality of charge retaining transistors serially connected such that at least one of the plurality of charge retaining transistors functions as a select gate transistor to prevent leakage current through the plurality of charge retaining transistors when the plurality of charge retaining transistors is not selected for reading; wherein a drain of a topmost charge retaining transistor is connected to a bit line associated with and parallel to the plurality of serially connected charge retaining transistors; wherein a source of a bottommost charge retaining transistor is connected to a source line associated with the plurality of charge retaining transistors and parallel to the associated bit line; and wherein a control gate of each of the plurality of charge retaining transistors is connected to a word line.