Patent ID: 7314793
Filing Date: 2008-01-01
Classification: H01L,Y10S

Abstract:
1. A method, comprising: forming a transistor element in a semiconductor region; forming a first spacer element adjacent sidewalls of a gate electrode structure of said transistor element; forming a metal compound in said gate electrode structure and portions of said semiconductor region not covered by said gate electrode structure and said first spacer element; forming a mask to expose said gate electrode structure and said first spacer element while substantially covering said metal compound disposed in said semiconductor region not covered by said gate electrode structure and said first spacer element; selectively etching said first spacer element exposed by said mask to remove at least a portion of said first spacer element; and forming a first dielectric layer over said transistor element, said first dielectric layer exerting a first specified stress level in a channel region of said transistor element.