Patent ID: 8039319
Filing Date: 2011-10-18
Classification: H01L

Abstract:
1. A method for making a quad flat non-lead (QFN) semiconductor package, comprising: half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed adjacent to the die attach pad, at least one extended, outer terminal lead disposed along periphery of the QFN semiconductor package, and at least one intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead, wherein the intermediary terminal is disposed between the inner terminal lead and the extended, outer terminal lead, wherein the extended, outer terminal lead is disposed beyond a maximum wire length that a wire bonder can provide for a specific minimum pad opening size on the semiconductor die; mounting a semiconductor die on the die attach surface; electrically interconnecting the semiconductor die with the intermediary terminal through a first conductive wire; electrically interconnecting the intermediary terminal with the extended, outer terminal lead through a second conductive wire; encapsulating the semiconductor die, the first and second conductive wires with a mold cap; and half etching a second side of the carrier opposite to the first side to form bottom portions of the lead array and the die attach pad.