Patent ID: 9202553
Filing Date: 2015-12-01
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device comprising: first and second load transistors each having a source connected to a first power supply line; first and second drive transistors each having a source connected to a second power supply line; a first transfer transistor having one terminal connected to a drain of the first drive transistor and another terminal connected to a first bit line; a second transfer transistor having one terminal connected to a drain of the second drive transistor and another terminal connected to a second bit line; a first cell node line that connects a drain of the first load transistor, the drain of the first drive transistor, a gate of the second load transistor, a gate of the second drive transistor, and the one terminal of the first transfer transistor to each other; and a second cell node line that connects a drain of the second load transistor, the drain of the second drive transistor, a gate of the first load transistor, a gate of the first drive transistor, and the one terminal of the second transfer transistor to each other, wherein the first cell node line and the first bit line are formed in different wiring layers, and have a first wide portion at a portion where the first cell node line and the first bit line overlap each other when viewed from above, the second cell node line and the second bit line are formed in different wiring layers, and have a second wide portion at a portion where the second cell node line and the second bit line overlap each other when viewed from above, the first wide portion is formed with a line width greater than that of other portions of the first bit line, and the second wide portion is formed with a line width greater than that of other portions of the second bit line.