Patent ID: 6674119
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A non-volatile semiconductor memory device, comprising:a p-type Si substrate; an n-type well formed in said Si substrate; a control gate formed of a p-type buried diffusion region formed in said n-type well; an active region formed in said Si substrate in the vicinity of said n-type well, said active region being covered by a tunneling insulation film; and a floating gate electrode formed on a surface of said Si subs rate so as to achieve a capacitance coupling with said p-type buried diffusion region, said floating gate electrode extending over said active region in a state that said tunneling insulation film is interposed between said floating gate electrode and said surface of said Si substrate, said active region including a pair of n-type diffusion regions at both sides of said floating gate electrode respectively as a source region and a drain region, said n-type diffusion region forming said source region having an nâˆ’-type diffusion region at the side facing said n-type diffusion region forming said drain region.