Patent ID: 9034681
Filing Date: 2015-05-19
Classification: B81B,B81C,H01L

Abstract:
1. A method for forming a chip package, comprising: providing a substrate having an upper surface and a lower surface; disposing a passivation layer and a package layer overlying the upper surface of the substrate; disposing a spacer layer between the upper surface of the substrate and the package layer; disposing a plurality of conducting pad structures overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; forming a plurality of openings through the passivation layer and extending from the upper surface towards the lower surface of the substrate; and disposing a plurality of movable bulks between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures respectively, and wherein the substrate, the spacer layer, and the package layer together form a cavity, and the openings and the movable bulks are located underlying the cavity.