Patent ID: 6107837
Filing Date: 2000-08-22
Classification: G11C

Abstract:
An address decoding circuit of synchronous type for decoding address signals of n-bit so as to select one of 2.sup.n output selective signals and make the selected one in selective condition, the address decoding circuit comprising:a decoding circuit for decoding the address signals of n-bit so as to select one of 2.sup.n decoded signals preliminarily set to selective condition and keeping its selective condition and then switching the other decoded signals except the selected decoded signal from the selective condition to non-selective condition; anda buffer circuit for detecting by receiving the 2.sup.n decoded signals from the decoding circuit that the other decoded signals different from the decoded signal kept in the selective condition have been switched from the selective condition to the non-selective condition and then selecting an output selective signal corresponding to the decoded signal in the selective condition, out of the 2.sup.n output selective signals corresponding to the 2.sup.n decoded signals, and making the output selective signal in the selective condition.