Patent ID: 8878272
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a cell region and a peripheral region; first storage nodes disposed on the semiconductor substrate in the cell region and second storage nodes stacked on respective ones of the first storage nodes; a dielectric layer and a plate node sequentially stacked to cover the first and second storage nodes; a first interlayer insulation layer on the peripheral region; a first contact penetrating the first interlayer insulation layer to have a same height as the first storage nodes; a first blocking wall disposed in an interfacial region between the cell and peripheral regions to have the same height as the first storage nodes and to separate the first interlayer insulation layer; a second interlayer insulation layer stacked on the first interlayer insulation layer; a second contact penetrating the second interlayer insulation layer to have a same height as the second storage nodes and to be connected to the first contact; a blocking layer between the first interlayer insulation layer and the second interlayer insulation layer to separate the first interlayer insulation layer; a second blocking wall stacked on the first blocking wall to have the same height as the second storage nodes and to separate the second interlayer insulation layer; a floating support layer covering the second interlayer insulation layer, the floating support layer extending to contact a sidewall of the second blocking wall and to contact outer sidewalls of the second storage nodes; a third interlayer insulation layer covering the plate node and extending onto the second blocking wall and the floating support layer; and a third contact penetrating the third interlayer insulation layer to be connected to the second contact.