Patent ID: 9007247
Filing Date: 2015-04-14
Classification: H03M

Abstract:
1. A sigma-delta modulator comprising: a summing stage for generating an error signal as a difference between an input signal and a feedback signal; a loop filter coupled to an output of the summing stage for filtering the error signal; a multi-bit quantiser coupled to an output of the loop filter for quantising the filtered error signal; and a digital filter coupled to an output of the multi-bit quantiser; a feedback path coupling an output of the digital filter to the summing stage for providing the feedback signal to the summing stage, the feedback signal having fewer bits than a number of bits produced by the multi-bit quantiser; wherein the difference in gain of the digital filter inside and outside of a passband of the sigma-delta modulator is greater than or equal to 20 log 10((2y−1)/(2z−1)) dB, where y is the number of bits of the feedback signal and z is the number of bits of the multi-bit quantiser.