Patent ID: 6352920
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A process of manufacturing a semiconductor device, the process comprising:forming a multi-layer interlayer insulating film so as to cover a plurality of semiconductor elements formed on a semiconductor substrate, forming openings in predetermined regions of the interlayer insulating film on the semiconductor elements in a manner of penetrating only part-way through the interlayer insulating film, placing a mask in and over a first group of the openings and forming contact holes in a second group of the openings while the mask is in the first group of openings by removing the interlayer insulating film remaining under the second group of openings, removing the mask from all of the first group of openings; forming a conductive layer on the interlayer insulating film to fill at least the contact holes and the first and second groups of openings for burying a wiring layer, so that the wiring layer fills in both the first and second groups of openings but only contacts corresponding doped diffusion regions through the contact holes at bottoms of the second group of openings; and forming contact plugs and a buried wiring layer by removing the conductive layer from on a top surface of the interlayer insulating film.