Patent ID: 8832326
Filing Date: 2014-09-09
Classification: H03K

Abstract:
1. A circuit for ordering a plurality of data words, comprising: a memory arranged to receive a plurality of keys at an address input port, the memory adapted, responsive to the plurality of keys collectively supplied to the address input port, to provide at a data output port one ordered set of a plurality of ordered sets of identifiers, wherein the memory is configured with the plurality of ordered sets of identifiers, and each ordered set of identifiers is a permutation of a plurality of the identifiers, wherein each key is associated with a respective one of the data words and each identifier of the one ordered set of the plurality of ordered sets identifies a respective one of the data words; and a plurality of multiplexers corresponding to the plurality of data words, respectively, each multiplexer arranged to receive at a select input of the multiplexer, a respective identifier of the one ordered set of the plurality of ordered sets from the memory and to receive the data words at respective inputs of the multiplexer, wherein each multiplexer is adapted to select the respective one of the data words identified by the respective identifier, and wherein the plurality of data words is 8 data words, each data word having 8 bits, the plurality of keys is 8 keys, each key having one bit, the plurality of ordered sets of identifiers is 256 ordered sets of identifiers, each ordered set of identifiers having 8 identifiers, each identifier having 3 bits, and the plurality of multiplexers is 8 multiplexers.