Patent ID: 6711697
Filing Date: 2004-03-23
Classification: G06F,H04L

Abstract:
A serial data transfer method utilizing a clock line and a serial data line, comprising steps of:transferring a predetermined number of serial data bits on said serial data line, with each bit in synchronism with a rise or a fall of a clock signal on said clock line; placing a chip enablement signal in synchronism with a particular fall or rise of the clock signal associated with a particular one of said data bits; and determining the range of said serial data based on said chip enablement signal, wherein said particular one of said data bits, to which said chip enablement signal is associated, is the second bit from the last wherein said serial data bits are sequentially read in and stored by shifting the bits in synchronism with said rise or fall of said clock signal, and wherein after said shifting of said serial data subsequent to the detection of said chip enablement signal, said serial data are retrieved.