Patent ID: 6605865
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A semiconductor package comprising:a chip mounting pad; a semiconductor chip attached to the chip mounting pad; a plurality of leads extending at least partially about the chip mounting pad in spaced relation thereto, each of the leads defining: a generally planar first lead surface; a generally planar second lead surface disposed in opposed relation to the first lead surface; and a generally planar third lead surface disposed in opposed relation to the first lead surface and oriented closer to the chip mounting pad than the second lead surface; each of the leads having a first lead thickness between the first and second lead surfaces which exceeds a second lead thickness between the first and third lead surfaces at least one conductive wire electrically connected to and extending between the semiconductor chip and a respective one of the first lead surfaces of the leads; and a sealing part defining a top surface, a bottom surface disposed in opposed relation to the top surface, and an upper shoulder surface disposed in opposed relation to the bottom surface and recessed relative to the top surface, the sealing part partially encapsulating the chip mounting pad, the leads, the semiconductor chip and the conductive wire such that the second lead surface of each of the leads is exposed in the bottom surface and the first lead surface of each of the leads is completely covered by the sealing part.