Patent ID: 8461060
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming a first layer of adjacent co-planar parallel conductors on a support material with gaps provided between adjacent conductors; depositing a first plurality of insulating material nanoparticles on said first layer of adjacent co-planar parallel conductors, wherein the nanoparticles have a minimum equatorial cross-section that is larger than a maximum width of the gaps; forming an insulating layer over said first plurality of insulating material nanoparticles; forming a second layer of adjacent co-planar parallel conductors on said insulating layer with gaps provided between adjacent conductors; and depositing a second plurality of insulating material nanoparticles on said second layer of adjacent co-planar parallel conductors, wherein the nanoparticles have a minimum equatorial cross-section that is larger than a maximum width of the gaps.