Patent ID: 7442978
Filing Date: 2008-10-28
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a first select transistor formed on a side of an upper surface of a substrate and having a first multi-layer gate; a second select transistor formed on a side of the upper surface of the substrate opposite the side of the first select transistor and having a second multi-layer gate; a first stepped portion formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of said substrate; a second stepped portion formed by etching the substrate adjacent to the second multi-layer gate of the second select transistor such that the second stepped portion forms a cavity in the upper surface of said substrate; a first contact plug formed in the first stepped portion; a second contact plug formed in the second stepped portion; a peripheral circuit region formed on the upper surface of the substrate, including a gate electrode and an impurity diffusion layer; a third stepped portion formed by etching the substrate adjacent to the gate electrode of the peripheral region such that the third stepped portion forms a cavity in the upper surface of said substrate in which at least part of the impurity diffusion layer is located; and a third contact plug formed in the third stepped portion.