Patent ID: 7244676
Filing Date: 2007-07-17
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising the steps of: (a) forming a plurality of plugs contacted to a substrate by passing through a first inter-layer insulation layer; (b) forming a second inter-layer insulation layer on an entire surface of the substrate structure resulted from the step (a); (c) forming a conductive layer being contacted to a first group of the plugs by passing through the second inter-layer insulation layer; (d) forming a hard mask insulation layer on the conductive layer; (e) forming a metal sacrificial layer deposited on the hard mask insulation layer; (f) forming a conductive pattern by selectively etching the conductive layer, the hard mask insulation layer and the metal sacrificial layer until a surface of the second inter-layer insulation layer is exposed; (g) forming a third inter-layer insulation layer on the entire resulting structure from the step (f); (h) performing a chemical mechanical polishing process to get an upper surface of the third inter-layer insulation layer planarized with the an upper surface of hard mask insulation layer; and (i) etching selectively the third inter-layer insulation layer and the second inter-layer insulation layer to form a contact hole exposing each surface of a second group of the plugs.