Patent ID: 8993411
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A method for forming a pad in a wafer with a three-dimensional stacking structure, comprising: bonding a device wafer and a handling wafer, wherein the device wafer comprises an Si substrate; thinning a back side of the Si substrate; depositing an anti-reflective layer on the thinned back side of the Si substrate; depositing a back side dielectric layer on the anti-reflective layer; defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, wherein the defining a space for the pad and forming the vias are performed by a photolithographic process; filling one or more metals in the vias and the defined space for the pad; and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.