Patent ID: 7358201
Filing Date: 2008-04-15
Classification: H01L

Abstract:
1. A method comprising: forming a number of channels over a surface of an integrated circuit die; forming a barrier on the die surface, the barrier extending about a periphery of the die and defining an interior region including the channels; forming an inlet reservoir within the interior region of the barrier, the inlet reservoir in fluid communication with at least some of the channels; and forming an outlet reservoir within the interior region of the barrier, the outlet reservoir in fluid communication with at least some of the channels, wherein forming the number of channels comprises: depositing a seed layer of a metal over the die surface; depositing a layer of a sacrificial material over the seed layer; forming a number of trenches in the sacrificial layer, wherein the seed layer is exposed in each of the trenches; depositing a layer of the metal over the exposed seed layer in the trenches, the metal layer extending over portions of an upper surface of the sacrificial layer, wherein gaps remain between the metal material extending from adjacent trenches and over the upper surface of the sacrificial layer; removing the sacrificial layer, wherein regions from which the sacrificial layer has been removed form the channels in the metal layer; and depositing an additional layer of the metal over upper surfaces of the metal layer to close the gaps over the channels.