Patent ID: 8054685
Filing Date: 2011-11-08
Classification: G11C

Abstract:
1. A method of sequentially performing a least significant bit (LSB) program operation and a most significant bit (MSB) program operation of a nonvolatile memory device, wherein the nonvolatile memory device comprises multi-level memory cells each configured to store two pieces of bit information and page buffers each coupled to a bit line coupled to the memory cells and configured to comprise a first latch coupled to first and second nodes and a second latch coupled to third and fourth nodes, the method comprising: a data setting step of inputting data of MSBs to the second and fourth nodes and setting data of the second and fourth nodes according to a state of data of LSBs stored in the memory cells; and a bit line precharge step of precharging the bit line according to a combination of data stored in the first and second latches and performing the MSB program operation according to a state of a LSB program operation stored in the memory cells.