Patent ID: 8000147
Filing Date: 2011-08-16
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells, a first selection transistor and a second selection transistor, the plurality of memory cells being connected in series, the plurality of memory cells being connected between the first selection transistor and the second selection transistor; a plurality of word lines connected to the plurality of memory cells included in one of the memory cell units, the plurality of word lines each formed by continuously extending control gates of the memory cells; a bit line connected to the first selection transistor; and a source line connected to the second selection transistor; wherein erase verification is performed after an erase operation; and wherein in a read operation, current flows from a first bit line to the source line through a selected memory cell unit when a first data is stored in a selected memory cell included in the selected memory cell unit connected to the first bit line; and wherein in the erase verification, current flows from the source line to the first bit line through the selected memory cell unit when the first data is stored in the selected memory cell included in the selected memory cell unit connected to the first bit line.