Patent ID: 6924200
Filing Date: 2005-08-02
Classification: H01L

Abstract:
1. A method comprising the steps of: a) forming a gate oxide over a substrate of a semiconductor wafer; b) depositing and patterning at least one gate layer to create a gate, the patterning creating two exposed substrate regions of the semiconductor wafer on opposing sides of the gate; and c) forming and patterning a first conforming layer comprising germanium to form sidewall spacers on sidewalls of the gate, wherein the germanium in the sidewall spacers consists of poly-germanium or amorphous germanium; d) implanting the exposed substrate regions of the semiconductor wafer with the dopant of a first type to implant source/drain regions in the substrate; e) heating the substrate sufficiently to anneal and activate the dopant of the first type to further form the source/drain regions in the substrate; f) heating the substrate in a plasma comprising oxygen at a temperature in a range of 500 to 600 degrees centigrade, wherein essentially all of the germanium in the sidewall spacers is converted into water-soluble germanium dioxide; g) removing essentially the entire sidewall spacers by placing the semiconductor wafer in water such that essentially all of the water-soluble germanium dioxide is dissolved in the water; h) forming a second conforming layer over the gate and source/drain regions; and i) doping the second conforming layer with the dopant of the first type to form extensions in the source/drain regions.