Patent ID: 8698225
Filing Date: 2014-04-15
Classification: G11C,H01L,Y10S

Abstract:
1. A non-volatile semiconductor memory device comprising: memory cell units each including memory cell transistors each including a stacked gate structure formed by stacking a charge storing layer and a control gate layer above a cell gate insulating film disposed above a first well having a first conductivity type and opposing diffusion layers disposed on the first well to sandwich the stacked gate structure, wherein data is programmed into and erased from the memory cell transistor by charging and discharging the charge storing layer, and select gate transistors adjacent to one of the memory cell units and having a select gate insulating film and a select gate electrode contacting to the select gate insulating film; a first transistor having a first gate insulating film and disposed above a second well having a second conductivity type which is opposite to the first conductivity type, and a second transistor having a second gate insulating film with a different thickness from the first gate insulating film, wherein the cell gate insulating film and the select gate insulating film are formed of substantially the same film, and the charge storing layer and the select gate electrode are formed of substantially the same film, and the memory cell transistors having the same film thickness with respect to the cell gate insulating film thereof, and a thickness of the first gate insulating film is equal to a thickness of the select gate insulating film.