Patent ID: 8975942
Filing Date: 2015-03-10
Classification: H03K

Abstract:
1. A level-shifter circuit, comprising: a pair of capacitors respectively coupled to opposing clock signal sources at first terminals thereof; a pair of cross-coupled transistor switches, each transistor switch connected between a supply voltage and a second terminal of a respective capacitor along a source-to-drain path and connected to second terminal of the other capacitor at its gate; and an output terminal of the level-shifter circuit taken directly from one of the second terminals of a capacitor, wherein the output terminal is configured to output a clock signal alternating between the supply voltage and a voltage level to a capacitance load, wherein the voltage level is determined based on a difference between the supply voltage and another supply voltage supplying power for the opposing clock signal sources, and wherein the pair of capacitors and the pair of cross-coupled transistor switches are sized proportionally to each other such that the output terminal outputs a startup clock signal alternating between a ground voltage of the supply voltage and a negative of the another supply voltage supplying power for the opposing clock signal sources.