Patent ID: 6275179
Filing Date: 2001-08-14
Classification: H03M

Abstract:
A digital-to-analog converter comprising:a first current cell group having a first plurality of current cells which individually turn on and off in response to respectively input digital signals, wherein the first plurality of currents cells are connected in parallel between a first power supply voltage and a first node;a second current cell group having a second plurality of current cells which respectively correspond to the first plurality of current cells, and which individually turn on and off in response to respectively input digital signals such that an on/off state of each of the first plurality of current cells is opposite an on/off state of each corresponding one of the second plurality of current cells, wherein the second plurality of currents cells are connected in parallel between the first node and a second power supply voltage;an output circuit which converts a current flowing from the first current cell group to the first node, or a current flowing from the first node to the second current cell group, into an analog output voltage;wherein each of the first plurality of current cells includes a first conductive type constant current MOS transistor having a gate electrode which is supplied with a first bias voltage from a second node, and wherein each of the second plurality of current cells includes a second conductive type constant current MOS transistor having a gate electrode which is supplied with a second bias voltage from a third node;wherein the output circuit includes an operational amplifier having a negative input terminal connected with the first node, a positive input terminal connected with a ground potential, and an output terminal connected to the negative input terminal via a feedback resister; andwherein said digital-to-analog converter further comprises:a first dummy current cell group having a first plurality of dummy current cells which are constantly turned on, each of the first plurality of dummy current cells including a first conductive type constant current MOS transistor having a gate electrode connected with the second node, wherein the first plurality of dummy current cells are connected in parallel between the first power supply voltage and a fourth node;a second dummy current cell group having a second plurality of dummy current cells which are constantly turned on, each of the second plurality of dummy current cells including a second conductive type constant current MOS transistor having a gate electrode connected with the third node, wherein the second plurality of dummy current cells are connected in parallel between the fourth node and the second power supply voltage; anda constant current compensating operational amplifier having a negative input terminal connected with the fourth node, a positive input terminal connected with the ground potential, and an output terminal connected with the third node, wherein the constant current compensating operational amplifier supplies the second bias voltage to the third node to equalize a potential of the fourth node and the ground potential.