Patent ID: 8698253
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including a memory cell area and a logic circuit area; an isolation trench formed in the semiconductor substrate, the isolation trench defining a first active region in the memory cell area and a second active region in the logic circuit area; an insulating film formed in the isolation trench and including a step between the first active region and the second active region; a floating gate formed on the first active region and the insulating film in an area nearby the first active region; an inter-gate insulating film formed on the floating gate; a control gate formed on the inter-gate insulating film; and a gate electrode formed on the second active region and the insulating film in an area nearby the second active region, wherein a height from a surface of the first active region to a surface of the insulating film in the memory cell area is smaller than a height from a surface of the second active region to a surface of the insulating film in the logic circuit area, the surface of the insulating film in the logic circuit area is higher than the surface of the second active region, and an edge of the floating gate is located on the insulating film and between the step and the first active region.