Patent ID: 6828837
Filing Date: 2004-12-07
Classification: H03K

Abstract:
A low power flip-flop circuit comprising:a latch that receives and holds an input signal responsive to an internal clock signal; a comparing circuit that compares the input signal with an output signal of the latch to provide a comparison signal indicative thereof; and an internal clock generating circuit that receives an external clock signal and generates the internal clock signal under control of the comparison signal, wherein the internal clock generating circuit controls passing of the external clock signal responsive to the comparison signal, delays the external clock signal for a predetermined time, inverts the delayed external clock signal, and generates the internal clock signal as having a pulse width smaller than a pulse width of the external clock signal by performing a NAND operation on the external clock signal and the inverted delayed external clock signal, the internal clock signal having rising and falling edges which are all synchronized with the external clock signal.