Patent ID: 7977174
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A method for fabricating a FinFET structure, the method comprising the steps of: fabricating a plurality of parallel fins overlying a semiconductor substrate, each of the plurality of parallel fins having sidewalls; fabricating a gate structure overlying a portion of each of the plurality of parallel fins, wherein the gate structure has sidewalls and overlies channels within the plurality of parallel fins; forming stress-inducing sidewall spacers abutting the sidewalls of the plurality of parallel fins and the sidewalls of the gate structure, wherein the stress-inducing sidewall spacers induce a stress within the channels; and implanting first conductivity-determining ions into the plurality of parallel fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the plurality of parallel fins.