Patent ID: 6233182
Filing Date: 2001-05-15
Classification: G11C

Abstract:
A semiconductor integrated circuit, comprising:a memory circuit; anda data processing circuit having a control circuit which generates a signal for checking said memory circuit in accordance with a predetermined algorithm and forms a control signal for reading written data, computing means which forms test data according to the control signal from said control circuit, and data determining means which determines data read from said memory circuit and outputs the result of determination therefrom,wherein said memory circuit and data processing circuit are formed over the same semiconductor chip,wherein a redundant circuit having a spare memory row or a spare memory column replaceable for a defective bit is provided around said memory circuit, and wherein said control circuit has an algorithm for selecting the most suitable spare memory row or spare memory column based on the result of determination from said data determining means, and for replacing a defective bit with the selected spare memory row or spare memory column, and includes a self-repairing circuit which performs address conversion for the replacement of the defective bit according to the algorithm.