Patent ID: 9036440
Filing Date: 2015-05-19
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array configured to include a plurality of word lines; a clock enable buffer configured to receive a clock enable signal; a plurality of command buffers configured to receive a plurality of commands; a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode; a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode; and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode, wherein, in a case in which the refresh control unit performs the word line activation operation in the self-refresh mode, when the refresh control unit exits from the self-refresh mode, the buffer control unit enables the plurality of command buffers regardless of the period in which the word lines are activated.