Patent ID: 7219285
Filing Date: 2007-05-15
Classification: G06F,G11C

Abstract:
1. A flash memory comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having said plurality of memory sectors; a control signal generation circuit, which generates a control signal; a first signal buffer, which receives a read enable signal input from an external device; an address buffer, which receives an address data input from the external device; an address signal generation circuit, which generates an address signal in a predetermined order in synchronization with the control signal, and generates an address signal in a predetermined order based on the address data in synchronization with the read enable signal; read means to select said memory sectors in said memory cell array based on the address data, and to read data from each of said plurality of flash memory cells of selected memory sectors; a plurality of data memory circuits, each of which is provided for each of said plurality of flash memory cells, temporarily memorizes data read from said plurality of flash memory cells corresponding to selected memory sectors and receives an allocated address signal and outputs the data, which is temporarily memorized, read from said plurality of flash memory cells; a data output buffer, which outputs the data, which is read from the said plurality of flash memory cells and output from said plurality of data memory circuits, to the external device in synchronization with the read enable signal; and an error correction circuit, which receives the data, which is read from said plurality of flash memory cells and output from said plurality of data memory circuits, in synchronization with the control signal, judges whether the data output from the data output buffer has an error in synchronization with the read enable signal, and corrects an error if there is the error.