Patent ID: 7787326
Filing Date: 2010-08-31
Classification: G06F

Abstract:
1. Within a programmable logic device (PLD) having an internal clock, a multi-date rate SDRAM interface for multi-date rate SDRAM, the multi-date rate SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface comprising: a DQS clock tree; a slave delay circuit adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, the slave delay circuit responsive to a control signal in providing the amount of phase shift; and a master delay circuit adapted to generate the control signal for the slave delay circuit, the master delay circuit further adapted to compare the internal clock with a delayed version of the internal clock in setting the value of the control signal, the master delay circuit including a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.