Patent ID: 9123429
Filing Date: 2015-09-01
Classification: G11C

Abstract:
1. A non-volatile memory comprising: n data cells for storing an n-bit entry, where a defective data cell of the n data cells is settable to a permanent logic state; at least two inversion status cells, each programmable between two states, where a first combination of logic states indicates that an inversion operation is to be performed on the n data cells and a second combination of logic states indicates that an inversion operation is not to be performed, a defective cell of the at least two inversion status cells being settable to a permanent logic state, and an operational cell of the at least two inversion status cells programmable to one of two logic states to achieve either the first or second combination of logic states; and an inversion processor coupled to the n data cells and the at least two inversion status cells, the inversion processor being configured to output either the n-bit entry or an inverse of the n-bit entry based on the first or the second combination of logic states of the at least two inversion status cells, the inversion processor including: