Patent ID: 6507917
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A data memory, comprising:at least one memory circuit including a plurality of normal memory cells accessed by predetermined addresses and at least one spare memory cell; a plurality of redundancy circuits, each redundancy circuit providing access to a spare memory cell instead of a normal memory cell when activated, and including a signal generating circuit that generates a redundancy signal when the redundancy circuit is activated; a decision and output circuit that detects a redundancy signal generated by a signal generating circuit of at least one redundancy circuit, the decision and output circuit providing the redundancy signal on an external connection; and a plurality of logic gates arranged in series, the signal generating circuits of the redundancy circuits being successively coupled to the decision and output circuit by the series of logic gates, each logic gate including an active element that buffers a received redundancy signal to at least a predetermined potential.