Patent ID: 6377102
Filing Date: 2002-04-23
Classification: H03K,H03L

Abstract:
A digital delay interpolator adapted to receive a first clock signal and a second clock signal, said second clock signal having a transition at a time that is delayed with respect to the time of a transition of said first clock signal, and to provide an output clock signal having a transition at a time intermediate the time of said transition of said first clock signal and the time of said transition of said second clock signal, comprising:a first plurality of selectively enabled delay circuits and a second plurality of selectively enabled delay circuits, said first plurality of delay circuits having an input port being adapted to receive said first clock signal, and said second plurality of delay circuits having an input port being adapted to receive said second clock signal, said first plurality of delay circuits and said second plurality of delay circuits having outputs connected together to form the output of said digital delay interpolator, each of said delay circuits comprising a first delay buffer element adapted to receive one of said first and second clock signals, and being enabled by an enable signal, a second delay buffer element connected to the output of said first delay buffer, and being enabled by said enable signal, and circuit means for providing a predetermined voltage at the common connection point of said first delay buffer and said second delay buffer when said first and second delay buffers are not enabled.