Patent ID: 6425101
Filing Date: 2002-07-23
Classification: G01R

Abstract:
An apparatus for testing a plurality of JTAG compliant integrated circuits, each of the integrated circuits having an associated test protocol, the apparatus comprising:a master controller operable to perform the test protocol associated with each of the integrated circuits, the test protocol including an on-chip debug protocol; a programmable switch for selectively forming test loops between the master controller and selected ones of the integrated circuits as directed by the master controller according to configuration data, the test loops for facilitating execution of selected ones of the test protocols; a data bus for connecting the master controller to each of the integrated circuits, the data bus being configured to transmit data and control signals between the master controller and the integrated circuits, the data bus also being for facilitating execution of the on-chip debug protocol; a JTAG controller connected to the data bus configured to execute a JTAG test protocol corresponding to the selected integrated circuit being tested; an OCDS controller connected to the data bus configured to execute an on-chip debug support (OCDS) test protocol when the integrated circuit being tested is an OCDS integrated circuit; and a programmable switch controller connected to the programmable switch arranged to use the configuration data to provide a switch control signal that directs the programmable switch to connect, as needed, selected ones of the integrated circuits that are to be tested to the JTAG controller.