Patent ID: 6844233
Filing Date: 2005-01-18
Classification: H01L

Abstract:
1. A fabrication method for a semiconductor memory device comprising: forming a plurality of sacrifice gates on a silicon substrate and spaced apart from each other; forming a first conductive layer on an exposed portion of the silicon substrate between the sacrifice gates; forming a first inter-insulation layer on the silicon substrate that exposes the first conductive layer and the sacrifice gates; forming a plurality of openings by removing the sacrifice gates; forming a plurality of gates in the plurality of openings; forming a plurality of capping layers, each capping layer formed on a corresponding one of the plurality of gates, a width of each capping layer greater than a width of the corresponding one of the plurality of gates; forming a second conductive layer on the first conductive layer; forming a second inter-insulation layer on the silicon substrate; and forming a bit-line contact exposing the second conductive layer by etching the second inter-insulation layer.