Patent ID: 6906376
Filing Date: 2005-06-14
Classification: G11C,H01L

Abstract:
1. An EEPROM cell device on a substrate, said device comprising: a selection transistor having gate, drain, source, and channel, wherein said drain is defined as a cell bit line; an isolation transistor having gate, drain, source, and channel, wherein said source is defined as a cell source line; and a floating gate transistor having control gate, floating gate, drain, source, and channel, wherein said drains and sources of each said transistor comprise a diffusion layer in said substrate, wherein said channels of each said transistor comprise said substrate, wherein said floating gate transistor drain is coupled to said selection transistor source, wherein said floating gate transistor source is coupled to said isolation transistor drain, wherein said device is programmed and erased by charge tunneling between said floating gate and said floating gate transistor channel, and wherein the having a floating gate dielectric thickness between the entirety of said floating gate transistor floating gate and channel wherein said floating gate dielectric thickness is less than the gate dielectric thicknesses between said selection transistor gate and channel and between said isolation transistor gate and channel.