Patent ID: 6798277
Filing Date: 2004-09-28
Classification: G05F

Abstract:
A reference voltage circuit comprising:a first voltage terminal; a second voltage terminal; a first reference voltage circuit connected between the first voltage terminal and the second voltage terminal; a first depletion mode MOS transistor connected between the first voltage terminal and the first reference voltage circuit; a second reference voltage circuit connected between the first voltage terminal and the second voltage terminal; and a second depletion mode MOS transistor connected between the first voltage terminal and the second reference voltage circuit; wherein a gate terminal of the first depletion mode MOS transistor is connected with a potential between the second reference voltage circuit and the second depletion mode MOS transistor, and a gate terminal of the second depletion mode MOS transistor is connected with a potential between the first reference voltage circuit and the first depletion mode MOS transistor.