Patent ID: 9129842
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A method comprising: providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the n-type a-Si feature and the p-type a-SiGe feature; and performing a first annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si feature and a p-type a-SiGe feature, wherein during the first annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, a first silicide feature is formed in the nFET region, and a second silicide feature is formed in the pFET region.