Patent ID: 6298103
Filing Date: 2001-10-02
Classification: H04L

Abstract:
A clock data recovery circuit, comprising:a reference clock circuit having a reference clock output for producing at least one reference clock frequency;a receive data circuit havinga receive data input for receiving an input data signal,a delay element having a delay element input and a delay element output, andan exclusive-OR circuit having:a first exclusive-OR input for receiving said input data signal and coupled to said delay element input,a second exclusive-OR input coupled to said delay element output, andan exclusive-OR output for providing a receive data output;a quadrature downconverter having first and second downconverter inputs and first and second downconverter outputs, said first downconverter input coupled to said receive data output and said second downconverter input coupled to said reference clock output;a first filter circuit having a first filter input and a first filter output, said first filter input coupled to said first downconverter output;a second filter circuit having a second filter input and a second filter output, said second filter input coupled to said second downconverter output; anda quadrature modulator havinga first modulator input coupled to said first filter output,a second modulator input coupled to said second filter output,a reference input coupled to said reference clock output, anda data clock output for providing a data clock signal in response to the first and second modulator inputs.