Patent ID: 7126843
Filing Date: 2006-10-24
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which memory cells, each including a magnetoresistive element having first and second magnetic layers and a first insulating layer formed between the first and second magnetic layers, are arranged in the form of a matrix; word lines connected to the first magnetic layers of the memory cells on each row of said memory cell array; sub-sense lines connected to the second magnetic layers of the memory cells on each column of said memory cell array; a main sense line connected to each of said sub-sense lines; a row decoder which selects a word line of said memory cell array; a column decoder which selects a sub-sense line of said memory cell array; a first switch element which connects said sub-sense line selected by said column decoder to said main sense line; a read circuit which reads out data from the memory cell selected by said row decoder and column decoder via said main sense line; and a write circuit which writes data in the memory cell selected by said row decoder and column decoder via said main sense line.