Patent ID: 7714627
Filing Date: 2010-05-11
Classification: H03K

Abstract:
1. A double-triggered logic circuit to connect a clock signal input end and a clock delay signal input end, comprising: a first PMOS transistor which has a first source connecting to of a mode selection signal input and a first gate connecting to the clock delay signal input end; a second PMOS transistor which has a second source connecting to of a first drain of the first PMOS transistor and a second gate of the second PMOS transistor connecting to the clock signal input end; a first NMOS transistor which has a third gate connecting to the first gate of the first PMOS transistor; and a second NMOS transistor which is coupled with a third PMOS transistor and has a fourth gate connecting to the clock signal input end; wherein the second PMOS transistor has a second drain, the first NMOS transistor has a third drain and the second NMOS has a fourth source and the third PMOS has a third source that are connected together to generate an output signal.