Patent ID: 8065542
Filing Date: 2011-11-22
Classification: G06F,Y02D

Abstract:
1. A method for providing the optimal power mode for a system on chip (SoC), comprising: dividing the SOC into hardware blocks comprising power loads having no more than one clock, one Vdd, and one embedded Vdd switch; storing a respective power state of each of the power loads in a transition table, wherein the transition table comprises a plurality of rows and columns, wherein a row denotes the power state and the columns denote power management resources comprising clocks, Vdds and embedded Vdd switches; and selecting a row from the transition table with a predetermined maximum benefit and affordable latency as an optimal power mode, wherein maximum benefit is defined as a largest amount of a predetermined criterion from among all the plurality of rows, and affordable latency is an amount of computer cycles taking to initiate performance of one or more operations in a selected row.