Patent ID: 6613621
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A method of forming a semiconductor device with a reduced gate resistance and a self-aligned contact pad, the method comprising:forming a first dummy gate pattern and a second dummy gate pattern on a semiconductor substrate, each dummy gate pattern having a sidewall spacer, the second dummy gate pattern relatively being wider than the first dummy gate pattern; forming a first insulating layer on an entire surface of the semiconductor substrate, the first insulating layer having a planar top surface and having the same level in height as the dummy gate patterns; removing the first and second dummy gate patterns to form a first and a second grooves exposing the substrate; forming a first and a second gate oxide layers on the first and the second grooves respectively; forming a low resistance material layer on the first insulating layer thereby completely filling the first groove and partially filling the second groove due to width difference therebetween; forming an etching stopper on the conductive material to completely fill the remainder second groove; etching the etching stopper until the conductive material outside of the grooves is exposed; using remainder etching stopper as an etch mask and etching the conductive material layer in the first groove to recess from a top surface of the first insulating layer; and forming an insulator to fill remainder first and second grooves to form a first capping layer and a second capping layer.