Patent ID: 6806786
Filing Date: 2004-10-19
Classification: H03L

Abstract:
A phase-lock loop (PLL) comprising:a detector configured to receive first and second signals and provide a detector output, wherein the first signal is related to a reference signal to be locked to and the second signal is related to a VCO signal; a loop filter configured to received and filter the detector output to provide a control signal; a multi-band voltage controlled oscillator (VCO) configured to receive the control signal and a select signal, select one of a plurality of frequency bands based on the select signal, and provide the VCO signal at a frequency within the selected frequency band based on the control signal; and a control unit configured to receive a third signal and provide the select signal, wherein the third signal is related to the control signal, the control unit comprising: a first comparator configured to receive the third signal and a first threshold value and provide a first status signal indicative of whether or not the frequency of the VCO signal is too high, and a second comparator configured to receive the third signal and a second threshold value and provide a second status signal indicative of whether or not the frequency of the VCO signal is too low, and wherein the select signal is derived based on the first and second status signals.