Patent ID: 7812833
Filing Date: 2010-10-12
Classification: G06F,G09G

Abstract:
1. A liquid crystal display device comprising: a liquid crystal panel having a plurality of data lines and a plurality of gate lines; a timing controller to receive a data enable signal and a data signal, and to output a gate shift clock, a gate output enable signal, and a source output enable signal, wherein at least one of the gate output enable signal and the source output enable signal is maintained at a predetermined level during an abnormal state of the data enable signal; a source driver to supply the data lines with corresponding data voltage signals based on the data signal and the source output enable signal; and a gate driver to supply the gate lines with corresponding gate voltage signals based on the gate output enable signal, wherein the timing controller includes: a state judging portion to determine whether the data enable signal is in a normal state or the abnormal state; and a control signal generating portion to generate the gate and source output enable signals based on the determined state of the data enable signal, wherein the state judging portion includes: a detecting portion to detect an attribute of the data enable signal; a reference portion having a reference attribute of the data enable signal in the normal state; and a comparing portion to compare the detected attribute and the reference attribute and to output a state signal representing either the normal state or the abnormal state, and wherein the attribute of the data enable signal includes a width of the data enable signal.