Patent ID: 7962320
Filing Date: 2011-06-14
Classification: G06F

Abstract:
1. A method of creating a power pin model of a semiconductor integrated circuit, said model comprising a combination of cells that are divided to have a cell size in accordance with a size of the semiconductor integrated circuit, each cell comprising one layer of a power supply circuit network including wires with capacitive components and ground, an internal active section existing between said power supply circuit network and ground and performing an operation in said semiconductor integrated circuit, and an internal capacitive section existing between said power supply circuit network and ground and being inoperative in said semiconductor integrated circuit, said method comprising: calculating λmin  where ηn is the value of a wavelength shortening derived from a dielectric material contained in the wires in a power supply circuit network layer, Cline  determining length lcell creating, from power supply circuit network wiring structure information of the semiconductor integrated circuit and the value of lcell coupling said model of the power supply circuit network, said model of the internal active section, and said model of the internal capacitance section through the respective connection terminals with the adjacent cells to derive a power pin model of an overall semiconductor integrated circuit having only one power supply circuit network layer; and outputting a derived power pin model.