Patent ID: 6245604
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A process for fabricating bipolar-CMOS integrated circuits, comprising:a. forming p-channel and n-channel MOS transistors in a silicon substrate;b. forming a first level of polysilicon on the MOS transistors and connecting the first level of polysilicon to the MOS transistors within the substrate,c. forming a first bipolar transistor base region in the substrate,d. forming a second level of doped polysilicon on the bipolar transistor base region,e. out-diffusing impurities from the second level of polysilicon into the transistor base region, andf. forming a second bipolar transistor base region in the substrate and connecting the second transistor base region to either the first or second level of polysilicon formed thereon to thereby form a second bipolar transistor emitter region by out-diffusion from either the first or second levels of polysilicon.