Patent ID: 6751145
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A volatile semiconductor memory, comprising:a plurality of memory cells arranged on a semiconductor substrate and connected to word lines and to bit lines intersecting said word lines, said memory cells being disposed in a plurality of memory segments, and each word line and each bit line being respectively connected to memory cells of only a single memory segment; a circuit connected to said memory cells for setting a time interval after an expiry of which memory contents of respective memory cells are to be refreshed; said circuit having a subcircuit for each of said memory segments for specifically setting the time interval for each of said memory segments; said subcircuits being connected on said semiconductor substrate such that said subcircuits receive an instruction to refresh the memory contents in a cyclical sequence, and such that a respective said subcircuit wherein a longer time interval is set for refreshing than in other said subcircuits interrupts a passing on of the instruction to the memory segment assigned thereto, if the respective said subcircuit receives the instruction at a time when the longer time interval has not yet expired.