Patent ID: 6912677
Filing Date: 2005-06-28
Classification: G11C

Abstract:
1. A circuit for inspecting a data error, the circuit comprising: a clock buffer configured to receive a clock signal; a buffer unit configured to receive a plurality of operation control signals and an address signal; a latch unit configured to synchronize the plurality of the operation control signals and the address signal from the buffer unit depending on the clock signal from the clock buffer; a decoder configured to receive the plurality of the operation control signals and the address signal from the latch unit to output a data compression signal, a first signal, and a second signal; a compression unit configured to compress the data bus signal based on the data compression signal from the decoder; a counter configured to sequentially generate count pulses based on the clock signal from the clock buffer, and the first signal and the second signal from the decoder; a data bus signal latch unit having a latch configured to store the data bus signal based on the first signal from the decoder, the data bus signal latch unit configured to output a signal stored at the latch based on the count pulses from the counter; and a select unit configured to selectively output one of an output signal of the data bus signal latch unit, a signal from the compression unit and the data bus signal based on the data compression signal and the second signal outputted from the decoder.