Patent ID: 7149136
Filing Date: 2006-12-12
Classification: G11C

Abstract:
1. A memory circuit comprising: a regular memory cell array; a redundant memory cell array which enables to replace a failed portion in the regular memory cell array; and a redundant replacement memory for storing data on the failed portion in the regular memory cell array, wherein the redundant replacement memory includes a redundant cell for holding failed portion data, and a redundant latch circuit for latching the failed portion data held by the redundant cell, depending on the data latched by the redundant latch circuit, the failed portion is replaced with the redundant memory cell array, and the redundant latch circuit latches test data supplied from an external terminal for temporary replacement of the regular memory cell array with the redundant memory cell array during testing, wherein the supply of the failed portion data held by the redundant cell to the redundant latch circuit is prohibited during the testing.