Patent ID: 7921397
Filing Date: 2011-04-05
Classification: G06F

Abstract:
1. A method of designing semiconductor integrated circuit, comprising: preparing a standard cell library in a CAD system, the standard cell library comprising standard cell data including logical function data and layout data for each of a first plurality of types of standard cells and one of a delay-adjusting cell data and load capacitor cell data for a specified type standard cell among the first plurality of types of standard cells, wherein: the specified type standard cell has a plurality of input terminals and an output terminal, the delay-adjusting cell data allows assessing correspondence between the load-capacitor cell data allows assessing correspondence between load capacitances connected to a node and a plurality of load-capacitor cell connection patterns for connecting one or more of the plurality of input terminals to the node; selecting a second plurality of types of standard cells including the specified type standard cell from the first plurality of types of standard cells, using the CAD system; and placing a plurality of standard cells based on the layout data for each of the second plurality of types of standard cells and routing the placed standard cells with each other using the CAD system to design a semiconductor integrated circuit comprising a circuit block, the circuit block including at least one logic circuit having a signal route, wherein the placing and routing includes: