Patent ID: 6528402
Filing Date: 2003-03-04
Classification: H01L

Abstract:
A dual salicidation process, comprising the steps of:(a) providing a semiconductor substrate which comprises a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and LDD areas formed within the substrate at opposed sidewall of the polysilicon gate conductor; (b) performing a thermal oxidization process to form a poly-oxide spacer on the sidewall of the polysilicon gate conductor; (c) performing an implantation process to form source/drain regions within the substrate at the outer lateral surfaces of the poly-oxide spacer; (d) removing the sacrificial layer; (e) depositing a first layer of refractory metal across exposed surfaces of the gate dielectric, the poly-oxide spacer, and the polysilicon gate conductor; (f) heating the first layer of refractory metal to convert the polysilicon gate conductor to a silicide gate conductor, (g) removing the first layer of refractory metal which is not reacted; (h) removing the gate dielectric from the source/drain regions; (i) depositing a second layer of refractory metal across the source/drain regions, the poly-oxide spacer, and the silicide gate conductor; (j) heating the second layer of refractory metal to form silicide structures upon the source/drain regions; and (k) removing the second layer of refractory metal which is not reacted.