Patent ID: 6928512
Filing Date: 2005-08-09
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a first chip including a first memory comprised of a plurality of first memory cells each having a first capacitor and a first MISFET, a plurality of first nodes for receiving first access signals for said first memory, and a first control logic for controlling an operation of the first memory; a second chip including a second memory comprised of a plurality of second memory cells each having a second capacitor and a second MISFET, a plurality of second nodes for receiving second access signals for said second memory, and a second control logic for controlling an operation of the second memory; and a third chip including a memory controller comprised of a plurality of third nodes connected to said plurality of first nodes to supply the first access signals for said first chip, a plurality of fourth nodes connected to said plurality of second nodes to supply the second access signals for said second chip, and a plurality of fifth nodes for receiving external access signals, wherein said memory controller delivers a first access signal so as to access said first memory when receiving the external access signal during a first period, and delivers a second access signal so as to access said second memory when receiving the external access signal during a second period, wherein said memory controller outputs the first access signals indicating a refresh operation command to said plurality of first nodes of said first memory regardless of the external access signals. wherein said memory controller outputs the second access signals indicating the refresh operation command to said plurality of second nodes of said second memory regardless of the external access signals, wherein each of said first memory and said second memory is a dynamic random access memory chip, and wherein said first chip, said second chip and said third chip are different chips.