Patent ID: 8908450
Filing Date: 2014-12-09
Classification: G11C,H01L

Abstract:
1. A memory device comprising: (a) two synchronous dynamic random access memory chips, each chip having a first surface comprising a plurality of chip contact pads, each contact pad corresponding to one signal of the chip, the chip signals including, for each chip, (i) a plurality of data (DQ) signals, (ii) a plurality of address signals, and (iii) a plurality of control signals; (b) a package for mounting the memory chips having interconnection terminals for conducting electrical signals to and from the memory chips; (c) an interconnecting network disposed within the package providing a plurality of conductive paths for electrically connecting (i) for each control signal and for each address signal, the chip contact pad on each chip corresponding to that control or address signal to one interconnection terminal for that signal for both chips so that the control and address signals for the two chips are tied together, and (ii) for each DQ signal, the chip contact pad on each chip corresponding to that DQ signal to a separate interconnection terminal so that half of the interconnection terminals connected to data signals connect to one of the chips and the other half of the interconnection terminals connected to data signals connect to the other chip, wherein each chip signal has a trace length between the chip contact pad and the interconnection terminal to which it connects, and the interconnecting network is configured so that the trace length for each chip signal is substantially the same.