Patent ID: 6795333
Filing Date: 2004-09-21
Classification: G11C

Abstract:
A semiconductor memory device arranged at a crossing of a word line and first and second bit lines, comprising:first and second inverters having output nodes connected to first and second storage nodes, respectively; a first switching circuit rendering conductive a path between the first storage node and an input node of said second inverter and applying a second potential to an input node of said first inverter if first and second potentials are applied to the first and second storage nodes, respectively, and rendering conductive a path between the second storage node and the input node of said first inverter and applying the second potential to the input node of said second inverter if the second and first potentials are applied to the first and second storage nodes, respectively, and applying the second potential to each of the input nodes of said first and second inverters if the first potential is applied to each of the first and second storage nodes; and a second switching circuit rendering conductive a path between the first bit line and the first storage node and between the second bit line and the second storage node, when the word line is set to a selected level.