Patent ID: 6636575
Filing Date: 2003-10-21
Classification: H03L,H04L,H04N

Abstract:
A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication therebetween, comprising:a first device generating a first clock signal Fa; a second device generating a second clock signal Fb2; the second device including a first phase locked loop (PLL) circuit and a second PLL circuit, the first PLL circuit adapted to increase the clock signal Fa by a factor K to produce a clock signal Fak, the second PLL circuit adapted to increase the clock signal Fak by a factor L to produce a clock signal Fbn, the second PLL circuit further adapted to decrease the clock signal Fbn by a factor N to produce the clock signal Fb2; and the first PLL circuit and the second PLL circuit adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2, enabling digital communication between the first device and the second device without requiring a predetermined phase lock between the clock signal Fa and the clock signal Fb2; wherein the first PLL circuit includes a first PLL having a wide tuning range and adapted to achieve a fast frequency lock.