Patent ID: 9035684
Filing Date: 2015-05-19
Classification: H03L

Abstract:
1. A delay locked loop (DLL) comprising: a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal, wherein the RO selects at least one of the reference clock signal and the feedback clock signal as an input clock signal based on the feedback clock signal to input the selected signal to the delay line; wherein after the feedback clock signal circulates, N times, through the RO, the RO selects the reference clock signal as the input clock signal and inputs the selected reference clock signal to the delay line; and wherein in response to a rising edge of the reference clock signal, the RO selects the feedback clock signal as the input clock signal and inputs the selected feedback clock signal to the delay line.