Patent ID: 8232821
Filing Date: 2012-07-31
Classification: H03L,H04L

Abstract:
1. A clock data recovery circuit comprising: a voltage controlled oscillator configured to generate multi-phase clock signals including a plurality of clock signals, each having a frequency that corresponds to an input control voltage, and having phases shifted from one another such that they are positioned at regular intervals; a phase comparator configured to compare the phase of input data with the respective phases of the plurality of clock signals, and to generate a phase difference signal, including an up signal and a down signal, which represents the comparison result; and a charge pump circuit configured to generate the control voltage such that, when the up signal of the phase difference signal is asserted, the frequency of the voltage controlled oscillator is raised, and when the down signal of the phase difference signal is asserted, the frequency of the voltage controlled oscillator is lowered, wherein the phase comparator comprises a third logical gate configured to generate the up signal based upon the plurality of internal up signals generated by the plurality of first logical gates, and a fourth logical gate configured to generate the down signal based upon the plurality of internal down signals generated by the plurality of second logical gates.