Patent ID: 8971138
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A method of testing cell stability in a memory of a metal-oxide-semiconductor (MOS) integrated circuit, the memory including peripheral circuitry, and including an array of memory cells that are each comprised of first and second cross-coupled inverters and first and second pass transistors, each column of memory cells associated with a pair of bit lines coupled to the first and second pass transistors of the memory cells in the column, and each row of memory cells associated with a word line coupled to gates of the pass transistors of the memory cells in the row, the method comprising: writing a first data state to a selected memory cell under normal test vector conditions applied to the cross-coupled inverters of the memory cell; applying a forward body node bias to at least one of the n-channel transistors of the selected memory cell; applying a reverse body node bias to another one of the n-channel transistors of the selected memory cell, each of the n-channel transistors constructed in a p-type well region that is electrically isolated from p-type semiconductor regions in the peripheral circuitry within which n-channel transistors are formed; then performing a disturb operation to the selected memory cell; then applying relaxed test vector conditions; and