Patent ID: 9176908
Filing Date: 2015-11-03
Classification: G06F

Abstract:
1. A memory controller, comprising: clock circuitry configured to provide clock signals having different clock rates for different types of memory devices; and an interface circuit configured to time division multiplex data destined for the different types of memory devices on a shared signal bus such that the data is output at the different clock rates for the different types of memory devices, the interface circuit also configured to provide first write data at a first one of the clock rates for write operations directed to a first type of memory device of the different types of memory devices, wherein the first type of memory device is configured to transmit and receive over the shared signal bus at the first clock rate and to provide second write data at the first clock rate for write operations directed to a second type of memory device of the different types of memory devices, wherein the second type of memory device is configured to transmit and receive over the shared signal bus at a second one of the clock rates that is slower than the first clock rate, and a portion of the second write data comprises dummy data.