Patent ID: 9213358
Filing Date: 2015-12-15
Classification: G06F,H01L

Abstract:
1. A monolithic three dimensional (3D) integrated circuit (IC) (3DIC) clock tree, comprising: at least one first clock branch of a clock tree disposed in a first 3DIC tier, the at least one first clock branch comprising a first single programmable delay cell configured to receive a clock signal and generate a first delay output comprised of a first delayed clock signal based on a first control input; a first plurality of clocked elements disposed in the first 3DIC tier, the first plurality of clocked elements coupled to the first delay output; at least one second clock branch of the clock tree disposed in a second 3DIC tier, the at least one second clock branch comprising a second single programmable delay cell configured to generate a second delay output comprised of a second delayed clock signal based on a second control input; a second plurality of clocked elements disposed in the second 3DIC tier, the second plurality of clocked elements coupled to the second delay output; and a delay sense circuit positioned in at least one of the first 3DIC tier and the second 3DIC tier, the delay sense circuit comprising a first delay input coupled to the first delay output through the first plurality of clocked elements and a second delay input coupled to the second delay output through the second plurality of clocked elements, the delay sense circuit configured to generate a control input based on a difference in time arrival between the first delay input and the second delay output.