Patent ID: 6268242
Filing Date: 2001-07-31
Classification: H01L,H03K

Abstract:
A method of forming a gate voltage-clamped vertical MOSFET device comprising:providing a semiconductor body, said MOSFET device including an active area where a MOSFET is to be formed and a diode area where a gate voltage claimping diode is to be formed;forming a gate oxide layer on a surface of said semiconductor body;forming a polysilicon layer on said gate oxide layer in said active area, said polysilicon layer extending into said diode area;forming a first mask over said polysilicon layer, said first mask defining a gate section of said polysilicon layer in said active area and a diode section of said polysilicon layer in said diode area;removing a portion of the polysilicon layer through said first mask to form said gate section and said diode section of said polysilicon layer; andimplanting a first dopant of a first conductivity type into said semiconductor body and into said diode section to form a first region of said MOSFET and a first region of said diode.