Patent ID: 6569759
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A process for fabricating a semiconductor device, comprising the steps of:a) preparing a semiconductor substrate; b) forming an inter-layered insulating layer over said semiconductor substrate; c) forming a hole in said inter-layered insulating layer; and d) forming a multi-layered conductive structure including a first refractory metal silicide layer and a first refractory metal nitride layer laminated on each other in said hole by using a chemical vapor deposition, wherein said step d) includes the sub-steps of d-1) conformably forming a refractory metal layer on an inner surface defining said hole, d-2) conformably forming said first refractory metal silicide layer on said refractory metal layer, d-3) conformably forming said first refractory metal nitride layer on said first refractory metal silicide layer, d-4) conformably forming a second refractory metal silicide layer on said first refractory metal nitride layer by using a chemical vapor deposition with the unfilled portion of said hole creating a recess, and d-5) filling said recess with a second refractory metal nitride layer by using a chemical vapor deposition.