Patent ID: 9224813
Filing Date: 2015-12-29
Classification: B82Y,H01L

Abstract:
1. An apparatus, comprising: a substrate; a core gate stack on the substrate; a shell gate stack on the substrate, the shell gate stack being disposed around the core gate stack; a ring of semiconductor material disposed between the core gate stack and the shell gate stack, the ring comprising a source region, a drain region, and a channel region, a first ring of insulating material disposed between the ring of semiconductor material and the core gate stack; a second ring of insulating material disposed between the ring of semiconductor material and the shell gate stack, in which each of the core gate stack and the shell gate stack comprise the same layers comprising a stacked first insulating layer, a conducting layer, and a second insulating layer, in which the conducting layer is positioned between the first insulating layer and the second insulating layer and at least partially surrounds the channel region.