Patent ID: 8084309
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: providing a substrate comprising at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10 nm; forming a first gate structure directly on a first portion of the first semiconductor layer and a second gate structure directly on a second portion of the first semiconductor layer; forming a first conductivity in-situ doped first semiconductor material on exposed surfaces of the first portion of the first semiconductor layer adjacent to the first gate structure, and on exposed surfaces of the second portion of the first semiconductor layer adjacent to the second gate structure; forming a mask atop the second portion of the first semiconductor layer leaving the first conductivity in-situ doped first semiconductor material on the first portion of the first semiconductor layer exposed; removing the first conductivity in-situ doped first semiconductor material from the first portion of the first semiconductor layer, wherein the first conductivity in-situ doped first semiconductor material remains on the second portion of the first semiconductor layer; forming a second conductivity in-situ doped second semiconductor material on the first portion of the first semiconductor layer, wherein the mask prohibits the second conductivity in-situ doped semiconductor material from being formed atop the second portion of the second semiconductor layer; and diffusing dopant from the second conductivity in-situ doped second semiconductor material and the first conductivity in-situ doped first semiconductor material into the first semiconductor layer to form extension regions.