Patent ID: 8660152
Filing Date: 2014-02-25
Classification: H04J

Abstract:
1. A network component comprising: a processor configured to: transmit a first frame comprising an Open System Interconnection (OSI) layer two header and a payload to a downstream node, wherein the first frame's OSI layer two header comprises a first timestamp indicating a transmission time of the first frame according to a first clock associated with the network component; and receive a second frame comprising an OSI layer two header and a payload at a reception time according to the first clock, wherein the second frame's OSI layer two header comprises a second timestamp that indicates an internal processing delay associated with the downstream node and a frame count timestamp that differentiates the second frame from the first frame, wherein a second clock is associated with the downstream node, wherein the first clock and the second clock are synchronized using the first timestamp, the second timestamp, or both, wherein the first clock comprises a first localized clock source positioned within the network component, wherein the second clock comprises a second localized clock source positioned within the downstream node, wherein the frame count timestamp indicates a number of synchronization window periods, and wherein the first localized clock source and the second localized clock source are generated independently from one another.