Patent ID: 6117716
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method of forming BiCMOS circuitry comprising the following steps:defining a first area, a second area, and a bipolar transistor area on a first conductivity type semiconductor substrate, the first area comprising a location for formation of a first conductivity type FET and the second area comprising a location for formation of a second conductivity type FET;blanket implanting a first dopant into the substrate, the first dopant being a second conductivity type dopant and being blanket implanted into: a) the first area to form a second conductivity well for a first conductivity FET, and b) the bipolar transistor area to form a bipolar transistor collector region;blanket implanting a second dopant into the substrate, the second dopant being a first conductivity type dopant and being blanket implanted into a) the second area to form a first conductivity type channel stop region, and b) the bipolar area to form a bipolar transistor base region; andimplanting a third dopant into a) the first area to form a halo region, and b) the bipolar area to form a bipolar transistor emitter region; the third dopant being a second conductivity type dopant.