Patent ID: 6731004
Filing Date: 2004-05-04
Classification: H01L,H05K,Y10T

Abstract:
An electronic assembly comprising:a substrate having a first coefficient of thermal expansion (CTE) and a circuit thereon; a first insulating layer on said substrate and covering said circuit, said first insulating layer having a second CTE greater than said first CTE and including a hole therein having access to said circuit; a second insulating layer on said first insulating layer and having a third CTE greater than said second CTE of said first insulating layer, said second insulating layer including an opening therein larger than said hole in said first insulating layer and aligned above said hole; a semiconductor chip having a fourth CTE; a third insulating layer on said semiconductor ship and having a fifth CTE greater than said fourth CTE of said semiconductor chip; a fourth insulating layer on said third insulating layer and having a sixth CTE greater than said fifth CTE of said third insulating layer; and a plurality of solder bumps electrically connecting said semiconductor chip to said substrate, wherein said assembly does not include an underfill resin between said substrate and said semiconductor chip, wherein said second insulating layer on said substrate and said fourth insulating layer on said semiconductor chip face one another and are separated by a gap, and wherein said third CTE of said second insulating layer is about equal to said sixth CTE of said fourth insulating layer.