Patent ID: 6766443
Filing Date: 2004-07-20
Classification: G06F

Abstract:
A method of improving branch prediction accuracy comprising;providing a path history vector using an N bit shift register; shifting a first logic state into said path history vector if a fetched instruction group contains a taken branch instruction and setting a M count compression counter to a logic reset; shifting a second logic state into said path history vector if said fetched instruction group contains no taken branch instructions or contains only not taken branch instructions and said compression counter is reset, increment said compression counter if a compression count of said compression counter is less than M and resetting said compression counter if said compression count is equal to M; incrementing said compression counter if said compression count is greater than zero but less than M and said fetched instruction group does not contain any branch instructions or contains only not-taken branch instructions, and resetting said compression counter if said compression count is equal to M; and accessing a branch history table using an address generated in response to a content of said branch history vector by doing a bitwise exclusive OR (XOR) of said path history vector with an address of a fetched branch instruction in said fetched instruction group.