Patent ID: 8238187
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. An apparatus for processing data in a buffer circuit comprising: a clock generator operable to generate a clock signal having an active phase and an inactive phase; a set of monotonic flip-flops operable to capture a set of incoming data addresses during said active cycle of said clock and to generate therefrom data corresponding to single bits in said addresses that have changed compared to the data addresses received by said set of monotonic flip-flops during an immediately preceding data capture cycle; a set of static flip-flops operable to capture a set of incoming data addresses during said inactive phase of said clock cycle and to generate a set of output data therefrom; a decoder operable to process said set of output data from said set of static flip-flops and to generate a set of old wordlines corresponding to a set of data addresses in said immediately preceding data capture cycle; and combinational logic operable to receive said set of single changed bits and said set of old wordlines and to generate therefrom a set of new wordlines.