Patent ID: 6707700
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A nonvolatile ferroelectric memory device comprising:a plurality of cell array blocks, each of the cell array blocks including a plurality of sub-cell array blocks, each of the sub-cell array blocks including a plurality of unit cells; a plurality of main bitlines formed in the sub-cell array blocks in one direction so as to correspond to each other by column unit; a plurality of sub-bitlines aligned in the sub-cell array blocks in a same direction of the main bitlines so as to be connected to terminals of the unit cells to induce voltages on the unit cells, respectively; a sense amplifier block having a plurality of sense amplifiers shared in common by a plurality of the cell array blocks so as to amplify a signal of each of the main bitlines; and at least one switching transistor formed in at least one of the cell array blocks, the switching transistor having a gate controlled by a corresponding one of the sub-bitlines which receives a voltage value induced from the unit cell, a drain connected to a corresponding one of the main bitlines, and a source connected to a ground voltage terminal, the switching transistor capable of current-sensing a data value of the unit cell by varying a voltage transferred to the corresponding main bitline as a current amount varies in accordance with the voltage induced on the corresponding one of the sub-bitlines.