Patent ID: 8541286
Filing Date: 2013-09-24
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising: forming a first layer of a first semiconductor material overlying a bulk semiconductor substrate that is formed of a second semiconductor material; forming a second layer of a third semiconductor material overlying the first layer; etching a first plurality of trenches into the first and second layers; filling the first plurality of trenches with a structure forming material to form a plurality of support structures; etching a second plurality of trenches into the first and second layers, wherein portions of the second layer disposed between adjacent trenches of the first and second plurality of trenches define a plurality of fins; etching the first layer to form gap spaces between the bulk semiconductor substrate and the plurality of fins, wherein the plurality of fins are supported in position adjacent to the gap spaces by the plurality of support structures; and filling the gap spaces with an insulating material.