Patent ID: 6661066
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A semiconductor device, comprising:a substrate; source/drain regions formed in a main surface of said substrate with a channel region interposed therebetween; a first insulating film formed on said main surface of said substrate in an area in which said source/drain regions are formed; sidewalls composed of a second insulating film and formed on sides of said first insulating film; a gate insulating film composed of a third insulating film and formed on said main surface of said substrate in an area in which said channel region is formed; a gate electrode formed to fill an inversely tapered recessed portion formed by sides of said sidewalls and an upper surface of said gate insulating film; and a fourth insulation film formed on an upper surface of said gate electrode and surrounding said gate electrode with said sidewalls, wherein said gate electrode is inversely tapered such that a gate length continuously gradually diminishes from a top portion to a bottom portion until the bottom reaches the gate insulation film such that the gate length at the bottom portion of the gate electrode is narrower that the gate length at the top portion of the gate electrode, wherein said third insulation film is composed of a material having a dielectric constant higher that that of said first insulating film, and is formed only on said main surface of said substrate and said sides of said sidewalls, and wherein said second and fourth insulation films are composed of a material which is different from that of said first insulation film.