Patent ID: 6219746
Filing Date: 2001-04-17
Classification: G06F,G11C

Abstract:
A synchronous memory, comprising:a row address circuit coupled to receive a row address signal in response to a system clock signal and a binary select signal, the row address circuit arranged to produce a row select signal;a column address circuit coupled to receive an initial column address signal in response to the system clock signal and the binary select signal, the column address circuit arranged to produce a plurality of column select signals in synchronization with the system clock signal;a memory array arranged in rows and columns of memory cells, each memory cell arranged to store a respective data bit, the memory array arranged to produce an integral multiple of M data bits in response to the row select signal and the plurality of column select signals; andan output circuit coupled to receive the system clock signal and the integral multiple of M data bits, the output circuit arranged to produce a first data bit from a first group of M data bits at a first time and a second data bit from a second group of M data bits at a second time after the first time in response to the system clock signal.