Patent ID: 8900932
Filing Date: 2014-12-02
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit package, the method comprising: attaching a first surface of a die to a conductive substrate, the die having at least one side surface that is not the first surface; forming a plurality of die connectors on a second surface of the die, the second surface opposing the first surface; encapsulating the at least one side surface of the die, the plurality of die connectors and at least a portion of the second surface of the die with an encapsulant material; planarizing an area of the encapsulant material over the encapsulated plurality of die connectors to expose a surface of at least one die connector; forming a first-level conductive trace on the planarized area of the encapsulant material to contact an exposed die connector, the first-level conductive trace contacting the exposed die connector to allow electrical communication; forming an insulating layer over the planarized area; and forming at least one second-level conductive trace on the insulating layer to be in communication with a die connector via a communication channel through the insulating layer, wherein the at least one second-level conductive trace is insulated from the first-level conductive trace.