Patent ID: 7443941
Filing Date: 2008-10-28
Classification: H03L

Abstract:
1. A phase offset cancellation circuitry comprising: at least two phase detectors for receiving component clock signals of a multi-phase clock generator, wherein at least some of the clock signals are offset from each other, each of the at least two phase detectors for detecting phase spacings between pairs of component clock signals, wherein each of the at least two phase detectors measures a phase spacing of adjacent component clock signals; at least one summer coupled to the at least two phase detectors for measuring the phase differences between the at least two phase detectors, wherein each of the at least one summer includes: a mirror circuit coupled to two of the at least two phase detectors for detecting a phase difference between the outputs of the at least two phase detectors; and a capacitor coupled to the mirror circuit for charging or discharging based upon the phase difference; and at least one variable delay element for receiving the measured phase differences and for providing a delay which is proportional to an output value of the at least one summer, wherein the delay is used to reduce the phase spacings between pairs of component clock signals.