Patent ID: 8310424
Filing Date: 2012-11-13
Classification: G02F,G09G

Abstract:
1. A liquid crystal display device comprising: an LCD panel including a liquid crystal layer, a plurality of electrodes for applying a voltage to the liquid crystal layer, and a pixel of which the luminance varies according to a display signal voltage supplied through at least one transistor, the pixel including a first subpixel to have a first luminance and a second subpixel to have a second luminance, which is different from the first luminance, in response to at least one display signal voltage supplied; a source driver for supplying the display signal voltage to a source bus line that is connected to the source of the transistor; a gate driver for supplying a scan signal voltage to a gate bus line that is connected to the gate of the transistor; luminance switching circuitry for switching the modes of operation from a first mode, in which the first luminance is higher than the second luminance, into a second mode, in which the first luminance is lower than the second luminance, and vice versa; wherein each of the first and second subpixels further includes: a liquid crystal capacitor formed by a counter electrode and a subpixel electrode that faces the counter electrode through the liquid crystal layer; a storage capacitor formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer, and a storage capacitor counter electrode that is opposed to the storage capacitor electrode with the insulating layer interposed between them; and a storage capacitor counter voltage generator for generating a voltage to be applied to the storage capacitor counter electrode, wherein the counter electrode is a single electrode provided in common for the first and second subpixels, while the storage capacitor counter electrodes of the first and second subpixels are electrically independent of each other, and wherein the device further includes two switching elements that are provided for the first and second subpixels, respectively, wherein the ON/OFF states of the two switching elements are controlled in accordance with a scan signal voltage supplied through a common gate bus line; when the two switching elements are ON, a display signal voltage is applied through a common source bus line to the subpixel electrodes and the storage capacitor electrodes of the first and second subpixels, where the first and second subpixel electrodes of the respective first and second subpixels share the common source bus line and the common gate bus line; after the two switching elements have been turned OFF, the voltages at the storage capacitor counter electrodes of the first and second subpixels vary; and the first and second subpixels have mutually different variations, which are defined by their directions and amplitudes, thus making the first and second luminances different from each other; wherein the luminance switching circuitry includes a circuit for inverting the phases of voltages to be applied to the storage capacitor counter electrodes of the first and second subpixels so that during the first mode a first pattern is applied to the storage capacitor counter electrode of the first subpixel with the first subpixel being a bright subpixel, and during the second mode a second pattern different than the first pattern is applied to the storage capacitor counter electrode of the first subpixel with the first subpixel being a dark subpixel, wherein the first and second patterns applied to the storage capacitor counter electrode in the first and second respective modes have phases inverted relative to each other; and wherein the switching of the mode of operation is performed by inverting the phases of voltages to be applied to the storage capacitor counter electrodes of the first and second subpixels.