Patent ID: 7361552
Filing Date: 2008-04-22
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device having a memory cell region and a peripheral region defined on a substrate, said method comprising the steps of: forming an interlayer insulation film over said substrate so as to cover said memory cell region and said peripheral region; forming a contact hole in said interlayer insulation film so as to expose a diffusion region in said memory cell region; forming a mask pattern over said interlayer insulation film so as to cover said peripheral region; patterning said interlayer insulation film while using said mask pattern as a mask, to reduce a surface level of said interlayer insulation film such that said surface of said interlayer insulation film is lower in said memory cell region than in said peripheral region; and forming a memory cell capacitor over said interlayer insulation film in a part thereof covering said memory cell region, such that said memory cell capacitor makes a contact with said diffusion region via said contact hole.