Patent ID: 8248122
Filing Date: 2012-08-21
Classification: H03L

Abstract:
1. A digital PLL circuit comprising: an oscillator which varies an oscillating frequency by an analog value; a first frequency divider which generates a first frequency signal of 1/m times (m: an optional number) from a reference clock signal; a second frequency divider which generates a second frequency signal of 1/n times (n: an optional number) from an output signal of the oscillator; a quantized phase comparator which compares phases of the first and second frequency signals, and obtains a quantized phase difference corresponding to a shift amount between the first and second frequency signals; a predictive controller which integrates the quantized phase difference for a predetermined period, and predicts a control value for the oscillator based on the integrated value; and a converter which converts the control value into an analog value for the oscillator, wherein the predictive controller performs sequential integration of the quantized phase difference until a polarity of the quantized phase difference is reversed from negative to positive and then from positive to negative again or until the polarity is reversed from positive to negative and then from negative to positive again, generates a predictive weight value by multiplying the integrated value by a predictive coefficient value of optional ratio, and obtains a control value for the oscillator by adding the predictive weight value to the integrated value.