Patent ID: 6434068
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A semiconductor memory circuit comprising:a word line; a bit line; a memory cell transistor having a first terminal applied to a first electrical potential, a second terminal connected to said bit line and a gate connected to said word line; a reference bit line; a reference cell transistor having a first terminal applied to the first electrical potential, a second terminal connected to said reference bit line and a gate connected to said word line; a sense node electrically connected to said bit line; a reference node electrically connected to said reference bit line; a differential amplifier having a first input connected to said sense node, a second input connected to said reference node and an output; a first load circuit connected between said sense node and a second potential source, said first load circuit having a first resistance value; a second load circuit connected between said reference node and the second potential source, said second load circuit having a second resistance value that is lower than the first resistance value; and a test circuit receiving a test signal, said test circuit changing the first and second resistance values in response to the test signal.