Patent ID: 8987828
Filing Date: 2015-03-24
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a substrate; a first set of semiconductor fins aligned in a first direction on the substrate, one or more of the semiconductor fins in the first set including at least one channel region and at least two source/drain regions of finFETs; a second set of semiconductor fins aligned in the first direction on the substrate one or more of the semiconductor fins in the second set including at least one channel region and at least two source/drain regions of finFETs; an inter-block isolation structure on the substrate having a first side and a second side, and wherein semiconductor fins in the first set have ends proximal to the first side of the inter-block isolation structure and semiconductor fins in the second set have ends proximal to the second side of the inter-block isolation structure; and a patterned gate conductor layer including a plurality of gate elements on corresponding fins in the first and second sets of semiconductor fins, the gate elements being disposed over channel regions of the corresponding semiconductor fins; at least one patterned conductor layer overlying the patterned gate conductor layer; and a plurality of interlayer connectors, including interlayer connectors aligned over corresponding semiconductor fins in the first and second sets and connected to the gate elements of particular finFETs on the corresponding fins.