Patent ID: 6359831
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A synchronous dynamic random access memory integrated circuit (DRAM) responsive to a clock signal, comprising:a clock input terminal for receiving the clock signal; a latency select circuit coupled to receive an externally supplied signal, the latency select circuit producing a latency select signal in response to the externally supplied signal; a latency circuit coupled to receive the clock signal and the latency select signal, the latency circuit producing a first set of control signals in response to the clock signal and the latency select signal being indicative of a first latency value, and producing a second set of control signals in response to the clock signal and the latency select signal being indicative of a second latency value; a memory array; a data bus; and an interface circuit coupled between the memory array and the data bus, the interface circuit further being coupled to receive one of the first or second set of control signals, the interface circuit controlling transfer of data between the data bus and the memory array in response to the received set of control signals.