Patent ID: 6178134
Filing Date: 2001-01-23
Classification: G11C,H01L

Abstract:
An integrated circuit having memory cells, comprising:(a) a first array of memory cells arranged in rows and columns;(b) first column support circuitry for the first array;(c) a second array of memory cells arranged in rows and columns; and(d) second column support circuitry for the second array, wherein:each column of the first array is vertically aligned with a corresponding column of the second array;the memory cells in each column of the first and second arrays are connected by a local bit-line, wherein each local bit-line of the first array is distinct from the corresponding local bit-line of the second array;each column of the first array and the corresponding column of the second array share a global bit-line;each global bit-line is connected (1) to the corresponding local bit-line of the first array by the first column support circuitry and (2) to the corresponding local bit-line of the second array by the second column support circuitry; andeach memory cell is an SRAM cell having a layout comprising:(a) a first vertical mesa disposed in a semi-conductor layer along a first vertical axis, the first vertical mesa corresponding to a first N-channel transistor and a second N-channel transistor:(b) a second vertical mesa disposed in the semi-conductor layer along a second vertical axis parallel to the first vertical axis, the second vertical mesa corresponding to a first P-channel transistor;(c) a third vertical mesa disposed in the semi-conductor layer along a third vertical axis parallel to the second vertical axis, the third vertical mesa corresponding to a second P-channel transistor; and(d) a fourth vertical mesa disposed in the semi-conductor layer along a fourth vertical axis parallel to the third vertical axis, the fourth vertical mesa corresponding to a third N-channel transistor and a fourth N-channel transistor.