Patent ID: 8237474
Filing Date: 2012-08-07
Classification: G11C,H03L

Abstract:
1. A delay lock loop comprising: a plurality of delay elements coupled in series, each comprising at least two logic gates coupled in series and configured to delay an input signal; a register coupled to the plurality of delay elements, the register configured to couple a respective control signal to each of the plurality of delay elements to designate the delay element as either a used or an unused delay element; and a first control circuit coupled to at least one logic gate of an upstream delay element, and a second control circuit coupled to at least one logic gate of a downstream delay element, the first and second control circuits coupled to the register and configured to receive a same control signal therefrom, the first control circuit configured to receive a clock signal and couple a gate control signal to the at least one logic gate such that corresponding inputs of the at least two logic gates maintain the same static level over a plurality of cycles of the clock signal.