Patent ID: 8519476
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A method for forming a self-aligned charge balanced semiconductor device comprising: a) forming one or more planar gates over a semiconductor substrate of a first conductivity type; b) forming one or more sidewall spacers at one or more corresponding edges of the one or more planar gates; forming a top gate insulating layer over the one or more planar gates and using the one or more planar gates and top gate insulating layer as a hard mask for etching one or more deep trenches in the semiconductor self-aligned to the planar gates; c) filling said deep trenches with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate; and d) performing source and body implants at a top surface of the semiconductor substrate, adjacent to the planar gates, wherein prior to performing source and body implants, the sidewall spacers are removed.