Patent ID: 7932745
Filing Date: 2011-04-26
Classification: H03K

Abstract:
1. A circuit disposed in a programmable logic integrated circuit device, and coupled to a programmable logic routing fabric, the circuit comprising: a logic function generator element including a plurality of data inputs and an output; a first multiplexer having a first data input, a second data input, a control input, and an output, the output coupled to a first data input of the logic function generator element; a second multiplexer having a first data input coupled to the output of the logic function generator element, a second data input coupled to the second data input of the first multiplexer, a control input, and an output; a clocked data storage element having a clock input, a data input, and a data output, the data output coupled to the first data input of the first multiplexer; and a third multiplexer having a non-inverting first data input coupled to the output of the clocked data storage element, an inverting second data input coupled to the output of the second multiplexer, a control input, and an output coupled to the data input of the clocked data storage element.