Patent ID: 8019973
Filing Date: 2011-09-13
Classification: G06F

Abstract:
1. An information processing apparatus including a plurality of register windows including combinations of registers in order of in registers, local registers, and out registers, for executing Simultaneous MultiThreading, the information processing apparatus comprising: a plurality of register windows each includes a master register and a work register provided for each of plural threads; a data transfer bus shared between the threads and configured to transfer data from the master register to the work register; an instruction analysis unit configured to decode an instruction read from a memory device; an instruction issue control unit configured to perform control to issue the decoded instruction to a computation unit configured to execute the decoded instruction; an instruction completion control unit configured to obtain an instruction execution result of the computation unit and to perform control for updating the register set on the basis of the execution result; and a data transfer control unit configured to control data transfer from the master register to the work register, wherein the data transfer control unit comprises: