Patent ID: 7380112
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A processor for decoding an instruction and executing the decoded instruction, said processor comprising: a flag register in which a plurality of conditional execution flags are stored, the plurality of conditional execution flags being used as predicates for conditional execution instructions; a decoding unit operable to decode an instruction; and an execution unit operable to execute the instruction decoded by said decoding unit, and a loop counter used for determining termination of a loop, wherein when the instruction decoded by said decoding unit is a loop instruction, said execution unit is operable to terminate an iteration of a loop to be executed, based on a value of one of the plurality of conditional execution flags for an epilog phase in the loop in a case where the loop is unrolled into the conditional execution instructions by means of software pipelining, wherein when the instruction, decoded by said decoding unit, is said loop instruction, said execution unit is further operable to set, to a first conditional execution flag of said register, a certain value indicating that an instruction using the first conditional execution flag as a predicate is to be executed, wherein said first conditional execution flag is different from said one of the plurality of conditional execution flags, and wherein said execution unit is operable to perform processing in the epilog phase, without using an epilog counter, by copying the determination result of the loop counter to the predicate of the instruction with a delay necessary for the processing in the epilog phase by executing the loop instruction.