Patent ID: 8314482
Filing Date: 2012-11-20
Classification: H01L

Abstract:
1. A semiconductor package device, comprising: a first wafer-leveled chip package structure; and a second wafer-leveled chip package structure stacked on said first wafer-leveled chip package structure; wherein both said first wafer-leveled chip package structure and said second wafer-leveled chip package structure comprise: a wafer having a first surface, an integrated circuit pattern and a plurality of pads are formed on the first surface, and a plurality of through holes penetrating said wafer, said wafer having a scribe-line region, the through hole positioned in the scribe-line region; a plurality of first chips formed on said first surface of said wafer, wherein each of said plurality of first chips has at least one pad mounted on the surface of said first chip opposite to said wafer; a first insulating layer formed on said first surface of said wafer, said first insulating layer having a plurality of first conductive vias penetrating said first insulating layer, wherein said first insulating layer covers said first chips, said integrated circuit pattern and said first surface of said wafer; a conductive pattern layer formed on a surface of said first insulating layer opposite to said wafer, and said conductive pattern layer is electrically connected with said first conductive vias; wherein a second insulating material is filled in said through holes of said wafer, at least one second conductive via passes through said second insulating material; a plurality of solder balls or needle pins are soldered to said second conductive vias; parts of said first conductive vias are connected with said pads of said wafer, parts of said first conductive vias are connected with said pads of said first chips and part of said first conductive vias are connected with said second conductive vias in said through holes; and a third insulating layer having a pattern formed on a surface of said first conductive pattern layer which is opposite to said first insulating layer; wherein said second conductive via of said second wafer-leveled chip package structure is electrically connected with said conductive pattern layer of said first wafer-leveled chip package structure wherein both of said first wafer-leveled chip package structure and said second wafer-leveled chip package structure are cut into two pieces at the scribe-line region thereof; the through holes located at the scribe-line region are cut into two portions; and the portions of the through holes are located at the terminals of said first wafer-leveled chip package structure and said second wafer-leveled chip package structure, respectively; and two second conductive vias separately placed the portion of the through hole of said first and second wafer-leveled chip package structure.