Patent ID: 6170041
Filing Date: 2001-01-02
Classification: G06F,Y02D

Abstract:
A high speed integrated circuit memory device comprising: a primary port for receiving and transmitting address, data and control signals; a secondary port for receiving and transmitting address, data and control signals; a bus transceiver, coupled to the primary port and to the secondary port, the bus transceiver comprising a plurality of address lines, a plurality of data lines, and a plurality of control lines; an internal memory array coupled to the bus transceiver, wherein within a single clock cycle the bus transceiver receives address and data signals from a receiver port of the primary and secondary ports and broadcasts the address and data signals to the internal memory array, and wherein the bus transceiver further broadcasts the address and data signals to a broadcast port of the primary and secondary ports; and a logic circuit, coupled to the plurality of address lines, the plurality of control lines, and to the internal memory array, for decoding memory control signals and for controlling transmission of data and control signals between the primary port, secondary port and internal memory array in accordance with the memory control signals; wherein the bus transceiver further comprises: an input data bus, coupled to the primary port and the secondary port, for providing data to the internal memory array; an output data bus, coupled to the primary port and the secondary port, for retrieving data from the internal memory array; and an address and control bus, coupled to primary port and the secondary port, for transferring address and control signals between the primary and secondary port; the logic circuit including logic for controlling (A) when the primary port and secondary port are each coupled to the input data bus, (B) when the primary port and secondary port are each coulped to the output data bus, and (C) when the primary port and secondary port are each coupled to the address and control bus.