Patent ID: 7525459
Filing Date: 2009-04-28
Classification: H03M

Abstract:
1. A programmable compute system for executing an h.264 binary decode symbol instruction comprising: a first compute unit including a first range circuit responsive to four possible current range of Least Probable Symbol (rLPS) values for selecting a current rLPS value in accordance with a current range value to define the current rLPS and, in response to said selected current rLPS value and said current range value, calculating a Most Probable Symbol (MPS) range; and a next state rLPS circuit responsive to said MPS range and current values to generate a flag and including a first look-up table responsive to said flag and a state of the current context value to generate the next four possible rLPS values of a current context next state; and a second compute unit including a second range circuit responsive to four possible current rLPS values for selecting the current rLPS value in accordance with the current range value to define the current rLPS and, in response to said selected current rLPS value and said current range value, calculating the MPS range; and in response to said flag selecting one of said MPS range and an LPS range; and a value update circuit, responsive to the current value and a difference between the current range and current rLPS for calculating MPS and LPS value values and responsive to said flag to select one of them; a value normalization circuit, responsive to said selected range value and a selected value value to provide in parallel a normalized next value, a next range; and a current context update circuit responsive to current context MPS and state, for determining MPS and LPS state from a second look-up table and selecting one of them in response to said flag and generating an MPS and negated MPS bit and providing the next context MPS and state and a decode symbol.