Patent ID: 6737901
Filing Date: 2004-05-18
Classification: H03K

Abstract:
An integrable, controllable delay device, comprising:an input terminal for receiving an input signal to be delayed; an output terminal for outputting an output signal delayed with respect to the input signal; a control connection for receiving a control signal controlling a delay time; a multiplicity of multiplexers each having a first input, a second input, and an output connection; said multiplexers forming a series circuit with downstream multiplexers and upstream multiplexers in a signal flow direction, with said second input of a respective downstream multiplexer connected to said output of a respective upstream multiplexer, and said first input of each said multiplexer connected to said input; said second connection of one of said multiplexers being connected to reference potential, and said output of another of said multiplexers being coupled to said output terminal; one of said multiplexers including: first, second, third, and fourth current paths each containing a switch connected to one of said inputs of said multiplexer, and each containing a switch connected to a bit line of said control connection, a current source connected to said current paths, and a plurality of resistance elements, each one of said current paths connected to one of said resistance elements.