Patent ID: 6784078
Filing Date: 2004-08-31
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, the method comprising the steps of:(a) forming a gate dielectric layer; (b) forming a first conductive layer on the gate dielectric layer; (c) forming a first upper layer comprising a material different from the first conductive layer on the first conductive layer; (d) forming a second upper layer comprising a material different from the first upper layer on the first upper layer; (e) forming sidewall spacers on side walls of the first conductive layer, the first upper layer and the second upper layer; (f) forming an insulation layer that covers the second upper layer and the sidewall spacers; (g) planarizing the insulation layer until an upper surface of the second upper layer is exposed; (h) removing the second upper layer; (i) removing the first upper layer to form a recessed section between the sidewall spacers; and (j) forming a second conductive layer in the recessed section to form a gate electrode that includes at least the first conductive layer and the second conductive layer.