Patent ID: 6028790
Filing Date: 2000-02-22
Classification: G11C

Abstract:
Circuitry for providing a controlled rate of programming current through a programmable memory cell device, the memory cell device being selectable for programming from a arranged collection of similar such devices, each memory cell device having a respective drain, source, and gate node, the circuitry comprising:a current mirror device coupled to a current source device, the current mirror device producing a mirror current level defined by an input stimulus applied to the current source device;a voltage biasing device coupled to the current mirror device, the voltage biasing device producing a biasing voltage with a level which is proportional to the mirror current level; anda current limiter device coupled to the source node of the selected memory cell, the current limiter device being driven by the biasing voltage and producing a limiter current which is directly proportional to the mirror current level, wherein the current limiter device is used to pull down the source node of the memory cell device at a controlled rate according to the mirror current.