Patent ID: 7564729
Filing Date: 2009-07-21
Classification: G11C

Abstract:
1. A sense amplifier circuit for use in a memory circuit including multiple pairs of differential bit lines, the sense amplifier circuit comprising: a read and write port for selectively accessing the sense amplifier circuit in response to a first control signal; a differential load connected between a first voltage source supplying a first voltage and a given pair of differential bit lines, the differential load being selectively activated in response to a second control signal; a second stage sense amplifier connected to the given pair of differential bit lines; a half-state reference generator connected to the given pair of differential bit lines, the half-state reference generator generating a reference current which is selectively pulled from one of the bit lines in the given pair of differential bit lines in response to a third control signal; and a pre-charge circuit connected to the given pair of differential bits lines, the pre-charge circuit being operative to set the given pair of differential bit lines to a known voltage level prior to a read or write operation in the memory circuit; wherein the sense amplifier circuit is operative in conjunction with a first stage sense amplifier in the memory circuit, the sense amplifier circuit being configured such that activation of the second stage sense amplifier is delayed relative to activation of the first stage sense amplifier; wherein the pre-charge circuit and the half-state reference generator are incorporated into the differential load.