Patent ID: 7716626
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. A computer-implemented method of designing a circuit layout of a semiconductor integrated circuit, the method being embodied in a data processing apparatus having at least an arithmetic processor and memory, the method comprising: designing a logic function of the integrated circuit; designing a pattern layout of the integrated circuit so that the pattern layout includes a logic cell area and an open area; providing a spare underground cell having no interconnect patterns and contacts; inserting said spare underground cell into the open area, wherein the spare underground cell includes a functional element; designing a mask layout of the integrated circuit, the mask layout including the logic cell and the spare underground cell; wherein the inserting the spare underground cell into the distributed open area comprises: pointing out an open area in an attended block region and an attended spare underground cell; inserting the attended spare underground cell into the open area in the attended block region; renewing the attended block region; and setting a flag when all inserting within the attended block region are finished; and storing the mask layout in the data processing apparatus memory.