Patent ID: 6898678
Filing Date: 2005-05-24
Classification: G06F,Y02D

Abstract:
1. A digital system, comprising: a memory circuit; a first requester circuit with a first memory access node; a second requester circuit with a second memory access node; a scheduling circuit connected to the first memory access node and to the second memory access node and having a request output node, operable to sequentially schedule memory accesses to the memory circuit by the first requestor circuit and by the second request circuit; a selection circuit connected to the first memory access node and to the scheduling circuit request output node with an output node connected to the memory circuit; access mode circuitry for indicating at least a first access mode and a second access mode controllably connected to the selection circuit, such that both the first requester circuit and the second requestor circuit can sequentially access the memory circuit when the access mode circuitry indicates the first access mode and the first requester circuit has exclusive access to the memory circuit when the access mode circuitry indicates the second access mode; and a size register for holding a size parameter coupled to the selection circuit, the selection circuit being operable to select a first portion of the memory circuit in response to the size parameter when the access mode circuitry indicates the second access mode, wherein only the first portion of the memory circuit is operable for exclusive access by the first requestor when the access mode circuitry indicates the second access mode.