Patent ID: 8756391
Filing Date: 2014-06-17
Classification: G06F

Abstract:
1. A computer-implemented system comprising: two or more opto-electrical isolators that couple a corresponding two or more memory devices to a processor, a first of the two or more opto-electrical isolator being disposed between a first of the two or more memory devices and the processor and a second of the two or more opto-electrical isolator being disposed between a second of the two or more memory devices and the processor, the first and second of the two or more memory devices separated by the first and second of the two or more opto-electrical isolators and the processor, the two or more opto-electrical isolators, two or more memory devices, and processor configured in a communication device, each memory device being electrically isolated from each other and operable to store data or instructions executed by the processor, a first memory device of the two or more memory devices has a security level that is more confidential than the security level of a second memory device of the two or more memory devices; the opto-electrical isolator associated with the first memory device operable to: the opto-electrical isolator associated with the second memory device operable to: