Patent ID: 7831805
Filing Date: 2010-11-09
Classification: G06F

Abstract:
1. A method comprising operating a general purpose processor (GPP) coupled via a port of the GPP to an application specific data path of an application specific instruction set processor (ASIP), the step of operating taking place in-between execution pipelines of the GPP and ASIP processors and comprising the steps of: conveying a reserved instruction read by the GPP to a pre-decoder of said ASIP via said GPP port, said reserved instruction being an instruction read from an instruction stream of the GPP, wherein said GPP port comprises an auxiliary coprocessor unit port of said GPP; in said pre-decoder, translating said received GPP reserved instruction to a form compatible with an instruction set architecture (ISA) of said ASIP; storing in said ASIP at least one ASIP compatible instruction for execution; and at, least one step taken from. a group of steps comprising: executing an application specific program in said ASIP independently of said GPP, wherein instructions comprising said application specific program are read by an instruction unit of the ASIP from an instruction memory of the ASIP; detecting in said ASIP a GPP issue signal associated with the reserved GPP instruction conveyed to the pre-decoder of said ASIP from the GPP; in response to detection of said GPP issue signal, scheduling the instruction unit of the ASIP to read instructions translated from the GPP reserved instruction from the pre-decoder; delaying execution of ASIP instructions read from the ASIP instruction memory by one ASIP clock cycle; the step of the ASIP generating a flag signifying that execution of the ASIP ISA compatible instruction has been completed and conveying said flag to the GPP; the step of holding the GPP to prevent it issuing further instructions until the flag signifying that execution of the ASIP ISA compatible instruction has been completed is received by the GPP; and the step of combining test ports of both the GPP and the ASIP to provide a single test port for the coupled GPP/ASIP.