Patent ID: 6037650
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A semiconductor device, comprising:an insulating layer, a first surface and a second surface arranged oppositely to each other, and a free surface of said insulating layer;a conductor area established on said first surface of said insulating layer;a first semiconductor layer featuring a first conductivity type and established on said second surface of said insulating layer, said semiconductor layer having an exterior surface, a dopant profile, a thickness, a permittivity, and x and z coordinates on said exterior surface thereof;a second semiconductor layer featuring a second conductivity type opposite said first conductivity type of said first semiconductor layer, said second semiconductor layer being established on said exterior surface of said first semiconductor layer and having a second ohmic contact;a p-n junction having a built-in junction potential formed by said first and second semiconductor layers, a metallurgical boundary of said p-n junction, and the y coordinate counted off along the thickness of said first semiconductor layer;said first semiconductor layer, wherein said dopant profile and thickness are so selected as to meet the condition of depletion of said first semiconductor layer or part thereof in the majority charge carriers till the breakdown of said p-n junction upon applying an external bias voltage thereto: ##EQU5## where Ui--the breakdown voltage of said first semiconductor layer; q--an elementary charge;N (x,y,z)--said dopant profile;d(x,z)--said thickness;.epsilon..sub.s --said permittivity;Uk--said built-in junction potential.