Patent ID: 7184331
Filing Date: 2007-02-27
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a fuse control circuit for providing with a plurality of fail word line addresses written in its own circuit in advance and outputting a redundancy signal representing that an input address is the same as one of the fail word line addresses, and a normal word line interruption signal; a redundancy word line controller for inputting the redundancy signal and activating a designated redundancy word line; and a normal word line controller, for activating a word line corresponding to the input word line address, which is operated or interrupted in response to the normal word line interruption signal, wherein the normal word line interruption signal has a first logic state at a pre-charge interval or when a same address as one of the fail word line addresses is inputted, and has a second logic state when a normal address is inputted.