Patent ID: 9007811
Filing Date: 2015-04-14
Classification: G11C

Abstract:
1. A memory device comprising: an array of memory cells arranged in rows and columns; a first word line corresponding to a first row of the rows, wherein when the first word line is selected, memory cells included in the first row are accessed; a first word line voltage supply having a first voltage level corresponding to a first selected state of the first word line; a second word line voltage supply isolated from the first word line voltage supply, the second word line voltage supply having a second voltage level corresponding to a second selected state of the first word line, wherein the second voltage level is greater than the first voltage level; a third word line voltage supply isolated from the first and second word line voltage supplies, the third word line voltage supply having a third voltage level corresponding to a deselected state of the first word line; a first transistor having a gate, a drain, and a source, the first transistor coupled between the first word line voltage supply and the first word line; a second transistor having a gate, a drain, and a source, the second transistor coupled between the second word line voltage supply and the first word line; and a first word line deselection transistor having a gate, a drain, and a source, the first word line deselection transistor coupled between the third word line voltage supply and the first word line.