Patent ID: 6161172
Filing Date: 2000-12-12
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache configured to store instructions;an instruction alignment unit coupled to receive a plurality of instructions fetched from said instruction cache, said plurality of instructions including a directly-decoded instruction and a microcode instruction, wherein said instruction alignment unit is configured to select a first dispatch plurality of instructions including said directly-decoded instruction and said microcode instruction, and wherein said instruction alignment unit is configured to select said first dispatch plurality of instructions from said plurality of instructions; anda microcode unit coupled to receive said microcode instruction from said instruction cache, wherein said microcode unit is configured to determine a number of directly-decoded instructions corresponding to said microcode instruction, and wherein said microcode unit is configured to transmit a signal indicative of said number of directly-decoded instructions;wherein said instruction alignment unit is coupled to receive said signal from said microcode unit, and wherein said instruction alignment unit is configured to determine if said first dispatch plurality of instructions is concurrently dispatchable in response to said signal, and wherein said instruction alignment unit is configured to discard one of said microcode instruction and said directly-decoded instruction from said first dispatch plurality of instructions in response to determining that said first dispatch plurality of instructions is not concurrently dispatchable.