Patent ID: 6334170
Filing Date: 2001-12-25
Classification: G06F

Abstract:
An expandable-set cache circuit for use with a data cache memory, comprising:a tag memory divided into a first set and a second set for storing under a single address location first and second tag fields representative of first and second data, respectively, and for storing first and second signals representative of which of the sets is the least recently used; anda logic circuit having an input portion responsive to a portion of an address representative of requested data and responsive to the first and second tag fields from the tag memory and responsive to an external signal, and the logic circuit having an output portion for outputting a signal indicative of the availability of the requested data in the tag memory, wherein the output portion controls the state of the first and second signals;a second tag memory divided into a third set and a fourth set for storing under a single address location third and fourth tag fields representative of third and fourth data, respectively, and for storing third and fourth signals representative of which of the sets is the least recently used; anda second logic circuit having a second input portion responsive to a portion of an address representative of requested data and responsive to the third and fourth tag fields from the second tag memory and responsive to a second external signal, and the second logic circuit having a second output portion for outputting a signal indicative of the availability of the requested data in the second tag memory, wherein the second output portion controls the state of the third and fourth signals.