Patent ID: 7671643
Filing Date: 2010-03-02
Classification: H03K

Abstract:
1. A power-on-reset circuit for use with an integrated circuit, the power-on-reset circuit comprising: a state machine having a plurality of sequential circuits, each of which generates a Boolean output signal corresponding to an operating state of the respective sequential circuit; an oscillation device that is adapted to generate a clock signal to the state machine and to the plurality of sequential circuits that is capable of changing a state of the state machine; and a power-on-reset output circuit that is adapted to generate a power-on-reset signal corresponding to at least one state of said state machine, the oscillation device and state machine being structured and arranged to deliver an initial reset signal to the power-on-reset output circuit during power-up and the power-on-reset circuit having zero or substantially zero static power consumption and entering a zero or a substantially zero current state whenever the oscillation device is not oscillating.