Patent ID: 7814294
Filing Date: 2010-10-12
Classification: G09G,G11C

Abstract:
1. A memory device, comprising: a memory cell array that includes a plurality of page areas, each of the plurality of page areas having a plurality of memory unit areas, each of the plurality of page areas being selected by a row address, each of the plurality of memory unit areas being selected by a column address, each of the memory unit areas storing data; a plurality of input/output terminals; and an input/output unit that is provided between the memory cell array and the plurality of input/output terminals, wherein the input/output unit, in response to a first operation code, accesses first data stored in a first memory unit area of the plurality of memory unit areas and second data stored in a second memory unit area of the plurality of memory unit areas adjacent to the first memory unit based on the row address, a column address for the first memory unit area and combination information including first information indicating a start position for accessing the first memory unit area, and the first data and the second data are assigned to the plurality of input/output terminals, wherein the input/output unit accesses the second data without a column address for the second memory unit area.