Patent ID: 7457323
Filing Date: 2008-11-25
Classification: H04J

Abstract:
1. A demultiplexer circuit comprising: a first serial-to-parallel conversion circuit for receiving input serial data and for performing serial-to-parallel conversion to output resultant data to parallel paths; a code detection circuit for activating and outputting a detection signal on detection of coincidence between output data sent out from said first serial-to-parallel conversion circuit to said parallel paths and a predetermined check code; a circuit for generating recovery clocks of a period corresponding to the length of a predetermined number of bits of said input serial data, and for varying the period of said recovery clocks, in case said detection signal from said code detection circuit is activated, in dependence upon bit deviation of said detection signal, to output resulting recovery clocks; and a second serial-to-parallel conversion circuit for converting data serially transmitted on said parallel paths into parallel data to output resulting parallel data responsive to said recovery clocks.