Patent ID: 6472736
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A stacked structure for memory chips, comprising:a substrate having an upper surface, a lower surface and a slot penetrating through the substrate from the upper surface to the lower surface; a lower memory chip having a central portion formed with a plurality of bonding pads, the lower memory chip being arranged on the upper surface of the substrate, the plurality of bonding pads being exposed via the slot of the substrate, and the bonding pads being electrically connected to the lower surface of the substrate via a plurality of wires; an upper memory chip having a central portion formed with a plurality of bonding pads, the upper memory chip being arranged on the lower memory chip in a back-to-back manner with respect to the lower memory chip so that the plurality of bonding pads of the upper memory chip faces upwards; and an insulation medium having a central portion formed with a slot, the plurality of bonding pads of the upper memory chip being exposed via the slot of the insulation medium, the insulation medium being formed with a plurality of traces electrically connecting to the bonding pads of the upper memory chip and the upper surface of the substrate via a plurality of wires.