Patent ID: 6061775
Filing Date: 2000-05-09
Classification: G06F

Abstract:
A microprocessor comprising:a predecode unit configured to generate predecode data that identifies a location of a speculative instruction within a cache line;an instruction cache coupled to said predecode unit, wherein said instruction cache includes an instruction storage for storing instructions and a predecode storage for storing predecode data;a microcode unit configured to parse a microcode instruction into one or more fastpath instructions and dispatch said fastpath instructions into an instruction processing pipeline;an instruction scan unit coupled between said instruction cache and said microcode unit and configured to convey said speculative instruction identified by said predecode data to said microcode unit and configured to verify that said speculative instruction is a first microcode instruction within said cache line, wherein if said speculative instruction is not a first microcode instruction, said instruction scan unit conveys a signal to said microcode unit to invalidate said speculative instruction.