Patent ID: 6163583
Filing Date: 2000-12-19
Classification: G06F,Y02D

Abstract:
A dynamic clocking apparatus comprising:a clock divider circuit to receive a first clock and to generate a slower second clock and also to output the first clock;a state machine circuit to receive the first and second clocks from the clock divider circuit, the state machine circuit receiving an external access signal indicating which clock between the first and second clocks to supply as an internal clock, the state machine circuit for generating a select signal for selecting the internal clock between the first and second clocks; anda multiplexer coupled to the clock divider circuit for selecting the internal clock from the first and second clocks in response to the select signal and for synchronizing the internal clock with the second clock in response to the select signal when selecting the second clock, the internal clock is provided to the processor and wherein the external access signal selects the second clock as the internal clock during external memory access operations performed by the processor.