Patent ID: 8542004
Filing Date: 2013-09-24
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: first to fifth lines; a first multiplexer; a second multiplexer; and a memory cell, the memory cell comprising: wherein the first gate electrode, the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, wherein the first line, the second source electrode, the first drain electrode, and a first terminal of the first multiplexer are electrically connected to each other, wherein the second line, the first source electrode, and a first terminal of the second multiplexer are electrically connected to each other, wherein the third line is electrically connected to a second terminal of the first multiplexer and a second terminal of the second multiplexer, wherein the forth line is electrically connected to a third terminal of the first multiplexer, and wherein the fifth line is electrically connected to a third terminal of the second multiplexer.