Patent ID: 6445051
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A flash memory device comprising:a plurality of gate stacks including a plurality of floating gates and a plurality of control gates disposed on a semiconductor substrate; a plurality of field insulating regions on the semiconductor substrate adjacent to a portion of the plurality of gate stacks; an insulating layer covering the plurality of gate stacks and the plurality of field insulating regions, the insulating layer having a plurality of contact holes therein, the plurality of contact holes being formed by providing an etch stop layer covering the plurality of field insulating regions, etching the insulating layer to provide the plurality of contact holes, the insulating layer etching step using the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions, the etch stop layer having an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions; and a conductor for filling the plurality of contact holes; wherein a portion of the plurality of contact holes reside partly over a portion of the plurality of field insulating regions.