Patent ID: 6727740
Filing Date: 2004-04-27
Classification: G11C,H03K,H03L

Abstract:
A synchronous mirror delay, comprising:a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a model delay line for receiving an input clock signal and operable to generate a model delayed clock signal in response to the input clock signal, the model delayed clock signal having a model delay relative to the input clock signal; a coarse delay circuit for receiving the input clock signal and coupled to the ring oscillator and the model delay line, the coarse delay circuit operable to generate a coarse delay count responsive to the oscillator, input, and model delayed clock signals, and further operable to activate a coarse delay enable signal responsive to the delay count being equal to a reference count value; a fine delay circuit coupled to the ring oscillator to receive the tap clock signals, coupled to the coarse delay circuit to receive the coarse delay enable signal, and for receiving the input clock signal, the fine delay circuit operable to latch the tap clock signals responsive to the input clock signal and to develop a fine delay from the latched tap clock signals, the fine delay circuit operable to activate a fine delay enable signal in response to the coarse delay enable signal, the fine delay enable signal having the fine delay relative to the coarse delay enable signal; and an output circuit coupled to the coarse and fine delay circuits, the output circuit generating a delayed clock signal responsive to the coarse and fine delay enable signals going active.