Patent ID: 8065639
Filing Date: 2011-11-22
Classification: G06F,H01L

Abstract:
1. A method of designing a semiconductor integrated circuit comprising: planning placement on a semiconductor integrated circuit chip in relation to a first isolated-power supplied region having a circuit which operates between a common ground bus line functioning as a ground potential node and a common power bus line supplied with a common power supply potential during a normal operation, and second and third isolated-power supplied regions so as to sandwich the first isolated-power supplied region, the second and third isolated-power supplied regions having a circuit which operates between the common ground bus line and first and second isolated power lines, respectively, the first and second isolated power lines being isolated from each other and being supplied with power supply potentials different from the common power supply potential; planning placement on the semiconductor integrated circuit chip in relation to a plurality of first electrostatic protection circuits connected between the common ground bus line and the common power bus line as well as between the common ground bus line and the first and second isolated power lines, and a plurality of second electrostatic protection circuits connected between the first and second isolated power lines and the common power bus lines; judging presence of a signal transmission between the second and third isolated-power supplied regions; and amending a circuit configuration on the semiconductor integrated circuit chip to insert a buffer circuit using the common power bus line as a power supply in a transmission path where the signal transmission is carried out when the signal transmission is judged to be present in said judging presence of the signal transmission.