Patent ID: 6535527
Filing Date: 2003-03-18
Classification: H03L,H03M,H04J,H04L,Y10S

Abstract:
An apparatus comprising:a first circuit configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate; a deserializer circuit comprising (a) a parallel register bank configured to generate an output signal in response to (i) said clock signal, (ii) said data signal and (iii) one or more select signals, (b) a state machine configured to generate said one or more select signals in response to one or more control signals and (c) a buffer circuit configured to present a buffered data signal in response to (i) a buffered clock signal and (ii) said output signal; and a framer circuit configured to generate said one or more control signals in response to (i) one or more input control signals and (ii) said output signal.