Patent ID: 7205993
Filing Date: 2007-04-17
Classification: G06T,G09G,G11C,H04N

Abstract:
1. A checkerboard buffer page system, comprising: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; and at least four memory devices, each memory device having a plurality of memory pages including a plurality of memory locations, each memory location having an address, where data elements are stored to at least two memory devices and retrieved from at least two memory devices in parallel, where each data element corresponds to an entry in one of a plurality of buffer pages, each buffer page having a plurality of entries along a first dimension corresponding to the first order and a plurality of entries along a second dimension corresponding to the second order, where data elements are stored to the memory devices in the first order and retrieved from the memory devices in the second order, and where at least one memory page stores data elements in multiple locations according to the first order and stores data elements in multiple locations according to the second order, where at least two data elements that are consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements that are consecutive in the second order are retrieved in parallel from the memory devices, where a data element is pixel data corresponding to a pixel in a frame of pixels, the frame having horizontal rows of pixels and vertical columns of pixels, where the buffer pages are pixel pages, each pixel page having a plurality of pixel page rows and a plurality of pixel page columns, where pixel data is retrieved at twice or more than the rate pixel data is stored.