Patent ID: 8138551
Filing Date: 2012-03-20
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; a first transistor including first gate electrode a first diffusion region, and a second diffusion region respectively formed in the semiconductor substrate; a second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed in the semiconductor substrate; a third transistor including the first gate electrode, a fourth diffusion region, and a fifth diffusion region respectively formed in the semiconductor substrate; and a node electrode formed above the first diffusion layer and coupled thereto, wherein the first gate electrode and the second gate electrode are formed separately at respective side walls of the node electrode, wherein the node electrode is coupled to the fourth diffusion region, wherein a third gate electrode is formed at a side wall of the node electrode, wherein a gate width of the first transistor is wider than that of the second transistor.