Patent ID: 6449751
Filing Date: 2002-09-10
Classification: G01R,G06F

Abstract:
A method of analyzing test vectors for use in measuring static current consumed by an integrated circuit, the method comprising:(a) reading a netlist of interconnected cells to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes; (b) reading cell characteristics for selected ones of the cell types from a technology library to identify pins of the selected cell types to be monitored; (c) generating a list of the nodes in the netlist that correspond to the pins identified in step (b); (d) simulating a response of a functional model of the integrated circuit to a potential test vector with a computer software simulation program; and (e) outputting logic states of the nodes in the list that were generated in step (c) from the simulation program when the functional model is in a substantially steady state.