Patent ID: 6992515
Filing Date: 2006-01-31
Classification: H03K

Abstract:
1. A duty cycle adjust circuit comprising: a first programmable logic circuit to output a plurality of variable incremental high logic signals, the incremental logic signals to increment edges of a high signal of an input clock signal in accordance with a set of first control signals, and to output a plurality of variable decremental high logic signals, the decremental logic signals to decrement edges of the high signal of the input clock signal in accordance with the first control signals; a second programmable logic circuit to output an incremented high logic signal or to output a decremented high logic signal upon receiving a second control signal; a positive variable duty cycle adjust circuit to couple to an input clock terminal (CLK IN) to receive the input clock signal and the incremental high logic signals and to output an incremented duty cycle adjusted clock signal, the clock signal having a high signal incremented from the high signal of the input clock signal as a function of the first control signals; a negative variable duty cycle adjust circuit to couple to couple to the CLK IN to receive the input clock signal and the decremental high logic signals and to output a decremented duty cycle adjusted clock signal, the clock signal having a high signal decremented from the high signal of the input clock signal as a function of the first control signals; and an output module to receive the incremented and decremented high logic signals and the incremented and decremented duty cycle adjusted clock signals, and to couple to an output clock terminal (CLK OUT) to output an adjusted clock signal having an incremented or decremented duty cycle clock signal as a function of the second control signal.