Patent ID: 6407428
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A silicon-on-insulator field effect transistor comprising:a) a channel region of a first conductivity type semiconductor formed in a silicon layer over an insulator layer; b) a source region and a drain region both of a second conductivity type semiconductor formed in the silicon layer on opposing sides of the channel region, i) the source region including a source extension region extending into the channel region adjacent to a top surface of the channel region and having a depth below the top surface that is less than a thickness of the silicon layer; ii) the drain region including a drain extension region extending into the channel region adjacent to the top surface of the channel region and having a depth below the top surface that is less than a thickness of the silicon layer; c) a plate region within a central portion of the channel region extending between the source extension and the drain extension, separated from both the top surface of the channel region and the bottom surface of the channel region, and extending between the source region and the drain region wherein the plate region includes a top surface and a bottom surface both of which are substantially parallel with the top surface of the central channel region and the bottom surface of the plate region is positioned at a depth corresponding to the depth of the source extension region and the drain extension region; and d) a gate positioned above the channel region, separated from the top surface of the channel region by a gate oxide layer, and controlling depletion within a portion of the central channel region between the plate region and the top surface of the central channel region.