Patent ID: 8835262
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method of forming a FinFET device, comprising: forming a patterned hard mask layer above a semiconducting substrate; performing at least one first etching process through said patterned hard mask layer to form a plurality of trenches in said semiconducting substrate that define at least first and second fins; forming liner material adjacent to at least said first fin to a first thickness; forming liner material adjacent to at least said second fin to a second thickness that is different from said first thickness; forming a layer of insulating material in said trenches adjacent said liner materials and above said patterned hard mask layer; performing at least one process operation to remove portions of said layer of insulating material and to expose portions of said liner materials; performing at least one second etching process to remove portions of said liner materials and said patterned hard mask layer, wherein removal of said liner materials results in exposing said first fin to a first height and said second fin to a second height that is different from said first height; performing at least one third etching process on said layer of insulating material to thereby define a reduced-thickness layer of insulating material; and forming a gate structure around a portion of said first fin and said second fin.