Patent ID: 9001607
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A method for enabling higher data bandwidth in resistive type non-volatile random access memory circuits, the method comprising: synchronously latching a first serial burst having a first plurality of bits; storing the first plurality of bits in parallel to a first plurality of non-volatile memory cells; receiving a second plurality of bits in parallel stored in a second plurality of non-volatile memory cells; synchronously providing the second plurality of bits as a second serial burst; receiving a clock signal; receiving an inverted clock signal; generating a first plurality of latch control signals responsive to the clock signal; generating a second plurality of latch control signals responsive to the inverted clock signal; latching, by a first plurality of latches, every other bit starting with the first even bit in the first serial burst; latching, by a second plurality of latches, every other bit starting with the first odd bit in the first serial burst; receiving, by a register, the latched bits in parallel from the first plurality of latches and the second plurality of latches responsive to a register control signal; receiving, by a write switch, the bits in parallel from the register; rearranging the order of the bits based on a predefined burst sequence; and outputting the rearranged bits in parallel to a global write and sense amplifier block.