Patent ID: 6787447
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A method of forming integrated circuitry comprising:providing a semiconductive substrate; providing a first circuit device on the substrate, the first circuit device having a conductive portion and an insulative cap disposed thereon; providing a second circuit device on the substrate, the second circuit device being elevationally displaced from the first circuit device; forming at least three layers over the substrate and through which electrical connection is to be made to the first circuit device and the second circuit device, the three layers comprising first and second layers having an etch stop layer interposed therebetween; in a common step, forming a first contact opening and a second contact opening through the at least three layers, the first contact opening being formed to the insulative cap of the first circuit device and the second contact opening being formed to the second circuit device; after forming the first contact opening and the second contact opening, removing at least a portion of the insulative cap to expose an upper surface of the conductive portion; forming a patterned layer of photoresist over the substrate to define a conductive line pattern, at least some of the layer of patterned photoresist being received over the second circuit device and the conductive portion of the first circuit device; selectively etching an uppermost of the first layer relative to the etch stop layer to define a first trough and a second trough, the first trough joined with the first contact opening and a second trough joined with the second contact opening.