Patent ID: 6872640
Filing Date: 2005-03-29
Classification: H01L

Abstract:
1. A method for creating semiconductor transistor devices on a silicon-on-insulator (SOI) structure including a buried oxide (BOX) layer and an active layer above the BOX layer, the method comprising: implanting n-type or p-type dopants into the active layer to create n-wells or p-wells respectively and so as to form device regions in the active layer; forming gate stacks on the device regions so as to define underlying channel regions; implanting dopants into the n-wells or p-wells so as to form source and drain regions such that the gate stacks substantially inhibit penetration of the dopants into the channel regions; forming a masking layer with openings at least partially over the gate stacks and so as to mask remaining regions of the SOI structure not underlying the gate stacks; implanting first additional dopants through the openings such that the additional dopants come to reside within the BOX layer underlying the channel regions so as to create localized borophosphosilicate glass (BPSG) diffusion sources within the BOX layer; implanting second threshold adjust dopants into the n-wells and p-wells to change a threshold voltage of the resulting transistor devices; and processing the SOI structure so as to induce the diffusion sources to establish retrograde dopant profiles in the channel regions having a peak concentration near the BOX.