Patent ID: 6384451
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A nonvolatile memory device comprising:a plurality of nonvolatile memory elements arranged in an array of rows and columns, each of said plurality of nonvolatile memory elements including: a floating gate MOS transistor having a source region and a drain region formed in a semiconductor body and spaced apart by a channel region, and a floating gate disposed above said channel region; and a tunneling charge injector having a conducting injector electrode, a grid insulator disposed adjacent to said conducting injector electrode, a grid electrode disposed adjacent to said grid insulator, and a retention insulator disposed adjacent to said grid electrode, wherein said floating gate electrode is disposed adjacent to said retention insulator; said memory device further including: a plurality of bit lines, a separate one of said plurality of bit lines coupled to said drain region of each of said plurality of nonvolatile memory cells in a same column; a plurality of injector lines, at least one of said plurality of injector lines coupled to said conducting injector electrode of each of said plurality of nonvolatile memory cells in a same column; and a plurality of grid lines, at least one of said plurality of grid lines coupled to said grid electrode of each of said plurality of nonvolatile memory cells in a same row.