Patent ID: 8766425
Filing Date: 2014-07-01
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first wiring substrate including a first surface, a plurality of first conductive pads formed on the first surface, a plurality of second conductive pads formed on the first surface, a second surface opposite to the first surface, a plurality of external input/output conductive pads formed on the second surface, and a plurality of testing conductive pads formed on the second surface, the second conductive pads of the first wiring substrate being electrically connected with the first conductive pads of the first wiring substrate, respectively, and the testing conductive pads of the first wiring substrate being electrically connected with both the first conductive pads of the first wiring substrate and the second conductive pads of the first wiring substrate, respectively; a first semiconductor chip mounted over the first surface of the first wiring substrate, the first semiconductor chip being electrically connected with the first conductive pads of the first wiring substrate; a second wiring substrate including a third surface, a plurality of third conductive pads formed on the third surface, a fourth surface opposite to the third surface, and a plurality of fourth conductive pads formed on the fourth surface, the fourth conductive pads of the second wiring substrate being electrically connected with the third conductive pads of the second wiring substrate, respectively, and the second wiring substrate being stacked over the first wiring substrate such that the fourth surface of the second wiring substrate faces the first surface of the first wiring substrate; a second semiconductor chip mounted over the third surface of the second wiring substrate, the second semiconductor chip being electrically connected with the third conductive pads of the second wiring substrate; and a plurality of first solder balls formed on the external input/output conductive pads of the first wiring substrate, respectively, and not formed on the testing conductive pads of the first wiring substrate, respectively; wherein the fourth conductive pads of the second wiring substrate are electrically connected with the second conductive pads of the first wiring substrate, respectively; wherein the second conductive pads of the first wiring substrate are arranged around the first semiconductor chip in a plan view, and are arranged closer to the outer edge portion of the first surface of the first wiring substrate than the first conductive pads of the first wiring substrate in the plan view; wherein the second conductive pads of the first wiring substrates and the fourth conductive pads of the second wiring substrates are formed at an outer area of the first and second wiring substrates, respectively, which are located outside the first and second semiconductor chips; and wherein the testing conductive pads of the first wiring substrate are arranged around the external input/output conductive pad in a plan view, and are arranged closer to the outer edge portion of the second surface of the first wiring substrate than the external input/output conductive pads of the first wiring substrate in the plan view.