Patent ID: 6266767
Filing Date: 2001-07-24
Classification: G06F

Abstract:
An apparatus for facilitating out-of-order execution of load instructions in a processor, the apparatus comprising:(a) a preload identifying arrangement for identifying each load instruction which represents a preload;(b) a preload queue having a plurality of queue locations for storing a plurality of preload entries, each preload entry being associated with a preload, being allocated when the respective preload is executed, and including (i) address information defined by the respective preload, and (ii) an identifier associated with the respective preload;(c) a preload queue routing arrangement associated with each execution unit in the processor which executes load instructions, the preload queue routing arrangement for transferring the address information defined by each respective preload and the identifier associated with the respective preload to the preload queue;(d) a comparison unit for identifying each conflicting preload entry, a conflicting preload entry comprising a preload entry which (i) defines an address which matches the address of a store instruction being executed, and (ii) is associated with a preload which is younger than the store instruction being executed; and(e) a flush signal arrangement associated with the preload queue, the flush signal arrangement for providing a flush signal which identifies a target preload, the target preload comprising the oldest preload associated with a conflicting preload entry identified by the comparison unit.