Patent ID: 6857049
Filing Date: 2005-02-15
Classification: G06F

Abstract:
1. In a data processing system having a processor responsively coupled to a store-in cache memory which is responsively coupled to a lower level memory, the improvement comprising: a. a read-only level one instruction cache memory directly coupled to said processor; b. a store-through level one operand cache memory directly coupled to said processor; c. wherein said processor is responsively coupled to said store-in cache memory via said read-only level one instruction cache memory and via said store-through level one operand cache memory; d. a flush buffer directly coupled to said store-in cache memory and said lower level memory; e. a tag memory responsively coupled to said store-in cache memory which indicates whether a particular location within said store-in memory has been modified by said processor; f. a logic circuit which loads said flush buffer with data from said particular location within said store-in cache memory in response to said indication that said particular location within said store-in memory has been modified by said processor; and g. wherein said flush buffer further comprises a first flush buffer store having a first input responsively coupled to said store-in cache memory and a first output directly coupled to said lower level memory and a second flush buffer store having a second input responsively coupled to said store-in cache memory and a second output directly coupled to said lower level memory.