Patent ID: 8232113
Filing Date: 2012-07-31
Classification: G01R,H01L

Abstract:
1. A method for manufacturing and for testing an integrated circuit, comprising the steps of: forming, on the upper portion of the integrated circuit, a passivation layer comprising openings at the level of metal tracks of an interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; depositing a multiple-layer conductive stack, for connection with conductive bumps, on the upper portion of the intergrated circuit; and etching the multiple-layer stack, except above the first pads, said track sections being of a material such that said etching also removes said track sections, whereby the first and second pads are disconnected, and wherein etching disconnects the second pads from the intergrated circuit.