Patent ID: 6954102
Filing Date: 2005-10-11
Classification: G11C

Abstract:
1. A memory-cell sensing circuit comprising: a supply-voltage potential; a reference memory cell; a reference-current bias circuit coupled to said reference memory cell, said reference current bias circuit including a first p-channel MOS transistor having a source coupled to said supply voltage potential, a drain, and a gate, a first cascode n-channel MOS transistor having a drain coupled to said drain and said gate of said first p-channel MOS transistor and a source coupled to said reference memory cell; a reference node; a reference-node biasing circuit including a second p-channel MOS transistor having a source coupled to said supply-voltage potential, a gate coupled to said gate of said first p-channel MOS transistor, and a drain, and a second n-channel MOS transistor having a drain and a gate coupled to said drain of said second p-channel MOS transistor and to said reference node, and a source coupled to ground; an equalization node; an equalization-node biasing circuit including a third p-channel MOS transistor having a source coupled to said supply-voltage potential, a gate coupled to said gate of said first p-channel MOS transistor, and a drain, and a third n-channel MOS transistor having a drain and a gate coupled to said drain of said third p-channel MOS transistor and to said equalization node, and a source coupled to ground a comparison node; a comparison-node biasing circuit including a fourth p-channel MOS transistor having a source coupled to said supply-voltage potential, a gate coupled to said gate of said first p-channel MOS transistor, and a drain, and a fourth n-channel MOS transistor having a drain and a gate coupled to said drain of said fourth p-channel MOS transistor and to said comparison node, and a source coupled to ground; a sense amplifier having a first input and a second input; a first mirror including a fifth p-channel MOS transistor having a source coupled to said supply-voltage potential, a drain, and a gate coupled to said first input of said sense amplifier, and a fifth n-channel MOS transistor having a drain coupled to said first input of said sense amplifier, a gate coupled to said comparison node, and a source coupled to ground; a pass gate having a first terminal, a second terminal coupled to said second input of said sense amplifier, and a control terminal; a second mirror including a sixth p-channel MOS transistor having a source coupled to said supply-voltage potential, a drain, and a gate coupled to said first terminal of said pass gate, and a sixth n-channel MOS transistor having a drain coupled to said first terminal of said pass gate, a gate coupled to said equalization node, and a source coupled to ground; at least one data memory cell coupled to a data-current bias circuit including a seventh p-channel MOS transistor having a source coupled to said supply voltage potential, a drain, and a gate, a second cascode n-channel MOS transistor having a drain coupled to said drain of said seventh p-channel MOS transistor and to said second input of said sense amplifier, and a source coupled to said at least one data-memory cell; and a third mirror including an eighth p-channel MOS transistor having a source coupled to said supply-voltage potential, and a drain and a gate coupled to said gate of said seventh p-channel MOS transistor, and an eighth n-channel MOS transistor having a drain coupled to said drain and said gate of said eighth p-channel MOS transistor, a gate coupled to said reference node, and a source coupled to ground.