Patent ID: 8977910
Filing Date: 2015-03-10
Classification: G06F,G11C

Abstract:
1. A method comprising: correlating different levels of an error-sensitive factor of a chip with errors of respective areas of the chip detected at each of the different levels, the error-sensitive factor comprising a physical trait of the chip such that a likelihood of an error occurring on the chip changes in according with changes in the level of the error-sensitive factor; and using indicia of the detecting of errors to store area-specific error statistics, wherein the area-specific error statistics are able to map, at a given time, for each area, values of the error-sensitive factor to respective error statistics, where for any given one of the areas and any given one of the values, the area-specific error statistics are able to provide, at the given time, a corresponding error statistic that is specific to the given one of the areas and is specific to the given one of the values.