Patent ID: 6618832
Filing Date: 2003-09-09
Classification: H04L

Abstract:
Method for employing a memory in an integrated circuit which is used to link a bus with an application device to be controlled by said bus, including the steps:sending asynchronous or isochronous data packets via said bus to said application device which data packets include header data to which a first error protection code is assigned and payload data to which a second error protection code is assigned, wherein said payload data are intended to be intermediately stored in said memory; evaluating in each case for a received current data packet said first error protection code, wherein, if this evaluation indicates that the header data of the current data packet have been received erroneously, at least payload data of the current data packet are not written into said memory; and overwriting the header data of the current data packet in said memory with the header data of the next data packet to be received, if header data of said current data packet have been written previously into said memory and the evaluation of said first error protection code or said second error protection code, respectively, indicates that the header data resp. payload data of the current data packet have been received erroneously.