Patent ID: 9172563
Filing Date: 2015-10-27
Classification: H04L

Abstract:
1. A circuit, comprising: a first data input port; a first data output port; a second data input port; a second data output port; a first pickoff tee coupled between the first data input port and the first data output port such that the first data output port is connected to a through output of the first pickoff tee; a second pickoff tee coupled between the second data input port and the second data output port such that the second data output port is connected to a through output of the second pickoff tee; a resistive network coupled between a pickoff output of the first pickoff tee and a pickoff output of the second pickoff tee; and a balun coupled with the resistive network, the pickoff output of the first pickoff tee, and the pickoff output of the second pickoff tee, wherein the first pickoff tee and the second pickoff tee each comprise a passive resistive combiner.