Patent ID: 9026959
Filing Date: 2015-05-05
Classification: G03F,G06F,H01L

Abstract:
1. A semiconductor manufacturing method of generating a layout for a device, comprising: defining a first plurality of mandrels in a first active region of a first layout, wherein each mandrel of the first plurality of mandrels extends in a first direction and is spaced apart in a second direction perpendicular to the first direction; defining a second plurality of mandrels in a second active region of the first layout, wherein each mandrel of the second plurality of mandrels extends in the first direction and is spaced apart in the second direction, and an edge of the first active region is spaced from an edge of the second active region by a minimum distance less than a specified minimum spacing; connecting, using a layout generating machine, at least one mandrel of the first plurality of mandrels to a corresponding mandrel of the second plurality of mandrels.