Patent ID: 8390776
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array, the method comprising: forming a gate pattern on a substrate; forming a first gate insulating film on a pixel region of the substrate; forming a second gate insulating film on the substrate; forming a source/drain pattern and a semiconductor pattern on the substrate; forming a passivation film on the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film comprising over-etching the passivation film to form an open region in the passivation film defining an undercut profile beneath the photo-resist pattern above the drain electrode; forming a transparent electrode film on the substrate; removing the photo-resist pattern and a portion of the transparent electrode film disposed thereon; and forming a pixel electrode directly on the first gate insulating layer.