Patent ID: 7962965
Filing Date: 2011-06-14
Classification: G06F,G06K

Abstract:
1. A semiconductor device comprising: a target circuit connected to an input to receive a serial input signal including a bit string; a sub-target circuit having the same circuit configuration as the target circuit; and a dummy bit string generation circuit connected to an input to receive exactly the same serial input signal including exactly the same bit string received by the target circuit and arranged to generate a dummy serial input signal including a dummy bit string based on the bit string of the serial input signal received by the target circuit, the dummy bit string generating circuit being connected to the sub-target circuit so as to supply the generated dummy serial input signal including the dummy bit string to the sub-target circuit, wherein the dummy bit string generation circuit is further arranged to generate the dummy serial input signal including the dummy bit string so that a sum of the number of bit shift times in the serial input signal and the number of bit shift times in the dummy serial input signal remains constant in a series of a plurality of clock cycles, wherein a plurality of the serial input signals are provided for dispatching to the target circuit in parallel, the same number of the dummy bit string generation circuits as the number of the serial input signals are provided corresponding to each of the serial input signals, and each of the dummy bit string generation circuits receives separately the bit string in the corresponding serial input signal and generates a corresponding dummy serial input signal including a corresponding dummy bit string which is received into the sub-target circuit.