Patent ID: 6177821
Filing Date: 2001-01-23
Classification: G06F,H03L

Abstract:
A microcomputer with a frequency multiplication circuit comprising:a frequency multiplication circuit for multiplying an input signal and outputting said input signal multiplied as a clock signal, and for generating and outputting a first control signal indicating a phase difference between said input signal and said clock signal;control means for generating and outputting a second control signal of a first level when said first control signal indicating that said frequency oscillation operation of said frequency multiplication circuit is in an unstable state, and for generating and outputting said second control signal of a second level when said first control signal indicates that said frequency oscillation operation of said frequency multiplication circuit is in a stable state;a stable detection timer for performing counting down operation by receiving said input signal and for refreshing said counting down operation when receiving said second control signal of said first level outputted from said control means; anda register for storing a value based on a third control signal generated by and transferred from said stable detection timer when the overflow happens in said stable detection timer,wherein said microcomputer initiates operation based on said value stored in said register.