Patent ID: 8697524
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method of manufacturing a vertical semiconductor device, comprising: forming a mold structure including a plurality of sacrificial layers and a plurality of insulating interlayers by alternately stacking one of the sacrificial layers and one of the insulating interlayers on a substrate a plurality of times; forming a first opening through the mold structure to expose the substrate; forming a plurality of first blocking layers by oxidizing portions of the sacrificial layers exposed by the first opening; sequentially forming a charge trapping layer, a tunnel insulation layer and a first semiconductor layer on the substrate and a sidewall of the mold structure in the first opening; partially etching portions of the first semiconductor layer, the charge trapping layer and the tunnel insulation layer on the substrate in the first opening to form a first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern on the sidewall of the mold structure; forming a second semiconductor layer on the first semiconductor layer pattern and the substrate to form a second semiconductor layer pattern including the first semiconductor layer pattern and the second semiconductor layer; partially removing the sacrificial layers and the insulating interlayers to form a second opening; removing the sacrificial layers to form grooves between the insulating interlayers; and forming a plurality of control gate electrodes in the grooves.