Patent ID: 7698663
Filing Date: 2010-04-13
Classification: G06F

Abstract:
1. An integrated circuit design apparatus, comprising: a storing unit configured to store design information required for designing an integrated circuit comprises an information representing regular structures found in a layout as a certain rule, a layout graphic information, a net list information, a constraint information and a cost information; an evaluation unit configured to extract a topological regular structure represented by an alignment relation of devices or of a pair of blocks in right and left or up and down directions in the layout including at least one of an array-structure, a row-structure, a slice-structure, a room-structure, and an object, by using the layout graphic information, the net list information and the constraint information with reference to the information representing the layout, and to evaluate the information representing a degree of the regularity of the layout based on the topological regular structures and physical regular structures; and an optimization unit configured to optimize the layout of the integrated circuit based on the design information, wherein the evaluation unit performs an evaluation based on at least one of the regular structures when performing the evaluation of the information representing the layout of the regular structures which is based on the topological regular structure represented by the alignment relation of devices or of the pair of blocks in right and left or up and down directions in the layout, and wherein the optimization unit optimizes the layout of the integrated circuit using the layout graphic information, the net list information, and the cost information while satisfying constraints contained in the constraint information and considering the evaluation of the information representing the layout of the regular structures by the evaluation unit.