Patent ID: 7031209
Filing Date: 2006-04-18
Classification: G11C,H01L

Abstract:
1. An apparatus for testing a memory cell, the memory cell comprising a select transistor and a data storage element, said select transistor having a gate connected to a select wordline, a source connected to a first terminal of said data storage element, and a drain connected to a column bitline, said apparatus comprising: a first column transistor connected to said column bitline; a wordline decoder connected to said gate of said select transistor through said select wordline, said wordline decoder providing an output signal to said select transistor to activate said select transistor, said wordline decoder also providing a test voltage to be applied to a second terminal of said data storage element; a sense amplifier that compares an input voltage to a reference voltage, said sense amplifier indicating that said memory cell tests programmable if said input voltage is higher than said reference voltage, said input voltage indicative of a Fowler-Nordheim current flowing through said data storage element.