Patent ID: 8294648
Filing Date: 2012-10-23
Classification: G09G

Abstract:
1. A display device comprising: a display unit comprising a plurality of data lines for transmitting data currents, a plurality of scan lines for transmitting selection signals, and a plurality of pixel areas defined by the data lines and the scan lines; a data driver for transforming a plurality of grayscale data into the data currents and applying the data currents to respective ones of the data lines; and a scan driver for sequentially applying the selection signals to respective ones of the plurality of scan lines, wherein the data driver comprises: a plurality of digital/analog (D/A) converter groups for receiving a plurality of first currents, the first currents being different from each other, the plurality of D/A converter groups being for outputting a plurality of second currents corresponding to the grayscale data and different ones of the plurality of D/A converter groups receiving the first currents at different times in a sequential manner, wherein a D/A converter group of the plurality of D/A converter groups comprises a first D/A converter comprising a plurality of first sample/hold circuits for receiving the first currents, storing a plurality of first voltages corresponding to the first currents, and outputting a first set of the second currents corresponding to first respective bits of the grayscale data, and a second D/A converter comprising a plurality of second sample/hold circuits for storing a plurality of second voltages corresponding to respective ones of the first voltages and outputting a second set of the second currents corresponding to second respective bits of the grayscale data, wherein each of the plurality of first sample/hold circuits comprises: wherein each of the plurality of second sample/hold circuits comprises: wherein the gate electrode of the first transistor is directly connected to the gate electrode of the second transistor, wherein the gate electrode of the first transistor of one of the plurality of first sample/hold circuits is controlled separately from the gate electrode of the first transistor of another one of the first sample/hold circuits, wherein the gate electrode of the second transistor of one of the plurality of second sample/hold circuits is controlled separately from the gate electrode of the second transistor of another one of the second sample/hold circuits, and wherein the first voltages and the second voltages are concurrently stored in the first sample/hold circuits and the second sample/hold circuits.