Patent ID: 6037219
Filing Date: 2000-03-14
Classification: H01L,Y10S

Abstract:
A method of fabricating a capacitor structure, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, comprising the steps of:providing an underlying transfer gate transistor, comprised of a gate structure, on a gate insulator layer, insulator spacers on the sides of said gate structure, and a source/drain region in an area of said semiconductor substrate, not covered by said gate structure;forming a storage node contact hole, in a composite insulator layer, exposing the top surface of a source region;forming a doped polysilicon plug, in said storage node contact hole;forming an opening in a thick insulator layer, exposing a portion of the top surface of said composite insulator layer, and exposing the top surface of said doped polysilicon plug;depositing a composite amorphous silicon layer on the top surface of said insulator layer, on the sides of the opening in said insulator layer, on said portion of the top surface of said composite insulator layer, and on top surface of said doped polysilicon plug, exposed in the bottom of said opening in said insulator layer; with said composite amorphous silicon layer comprised of: an underlying, undoped, or lightly doped, amorphous silicon layer; a heavily doped amorphous silicon layer; and an overlying, undoped, or lightly doped, amorphous silicon layer;removing said composite amorphous silicon layer from the top surface of said insulator layer;removing said thick insulator layer, resulting in the formation of a crown shaped storage node shape, comprised of vertical shapes of said composite amorphous silicon layer, with said vertical shapes of said composite amorphous silicon layer, connected to a horizontal shape, of said composite amorphous silicon layer, and with said horizontal shape of said composite amorphous silicon layer, overlying and contacting, said doped polysilicon plug, and with both said vertical shapes, and said horizontal shape, of said composite amorphous silicon layers, comprised of said heavily doped amorphous silicon layer, located between said overlying, and said underlying, undoped, or lightly doped, amorphous silicon layers;performing a pre-clean procedure on exposed surfaces of said undoped, or lightly doped, amorphous silicon layer, of said crown shaped storage node shape, in a first chamber of a cluster tool;depositing hemispherical grain, (HSG), silicon seeds, on the surfaces of said undoped, or lightly doped, amorphous silicon layer, of said crown shaped storage node shape, in situ, in a second chamber of said cluster tool;performing a first anneal cycle, in said second chamber of said cluster tool to convert said HSG silicon seeds, to a HSG silicon layer;performing a second anneal cycle, to distribute dopant from said heavily doped amorphous silicon layer, to said overlying, and to said underlying, undoped, or lightly doped, amorphous silicon layer, and to said HSG silicon layer, creating a crown shaped storage node electrode, comprised of said HSG silicon layer, on a doped, composite amorphous silicon layer;forming a capacitor dielectric layer on said crown shaped storage node electrode; andforming an upper plate electrode, for said capacitor structure.