Patent ID: 6546531
Filing Date: 2003-04-08
Classification: G06F

Abstract:
A method for enhancing performance of an electrical circuit, the method comprising:providing a layout for an electrical circuit having at least one storage element hold time deficiency and having a selected circuit path P that passes through the hold-time-deficient storage element; simulating, on a computer, insertion of a selected time delay element, having a time delay value that is at least equal to the hold time deficiency, at a selected location on the circuit path P immediately preceding the hold-time-deficient storage element; determining cycle time, as a result of insertion of the time delay element into the path P, for at least one circuit path Pâ€² that does not coincide with the circuit path P; when the cycle time of the at least one circuit path Pâ€² does not exceed a selected threshold time value, permitting insertion of the time delay element at the selected location; and when the cycle time of the at least one path Pâ€² exceeds the threshold time value: withholding insertion of the time delay element at the selected location; simulating insertion of the selected time delay at a second selected location, preceding at least one logic element that immediately precedes the hold-time-deficient storage element, on a path that passes through the hold-time-deficient storage element; determining a second cycle time, as a result of insertion of the selected time delay element, for at least one circuit path that does not include the hold-time-deficient storage element and the time delay element, at the second selected location; and when the second cycle time does not exceed the threshold value, permitting insertion of the time delay element at the second selected location.