Patent ID: 6965964
Filing Date: 2005-11-15
Classification: G11C

Abstract:
1. A NANID flash memory device including a memory cell array for storing data information, the device comprising: M input/output pins for inputting and outputting M-bit data (M is any natural number); a control logic for receiving external control signals to generate a plurality of address load signals, a command load signal, and a data load signal; a first input buffer circuit for receiving N least significant bits (N is any natural number) of the M-bit data received via the input/output pins, wherein M is larger than N; a second input buffer circuit for receiving N most significant bit signals of the M-bit data received via the input/output pins; an address register for receiving as an address an output of the first input buffer circuit in response to the address load signals, wherein the address load signals are activated serially; a command register for receiving as a command the output of the first address buffer circuit in response to the command load signal; a data input register for simultaneously receiving outputs of the first and second input buffer circuits in response to the data load signal, as data to be programmed; a row decoder and switch circuit for selecting a row of the memory cell array in response to row select information of an output of the address register; a column decoder and switch circuit for selecting columns of the memory cell array in response to column select information of the output of the address register; a first data bus for transferring M-bit data outputted from the data input register; a sense and latch circuit for sensing data from memory cells of the selected row at a read operation and for latching the M-bit data on the first data bus via the column decoder and switch circuit at a program operation; a second data bus for transferring M-bit data outputted from the sense and latch circuit via the column decoder and switch circuit; and a data output buffer circuit for outputting the M-bit data transferred via the second data bus to the M input/output pins, wherein, at each mode of operation where a command, an address and data are received serially, the data is inputted and outputted through all of the M input/output pins while each of the command and the address is inputted through N least significant bit input/output pins, and wherein, when each of the command and the address is inputted, signals on N most significant bit input/output pins are invalid.