Patent ID: 6346838
Filing Date: 2002-02-12
Classification: G06F,H03L

Abstract:
A phase lock loop-based deskew buffer circuit, the deskew buffer circuit comprising:a fixed delay element to delay a feedback signal and to generate a first signal therefrom; and a delay locked loop (DLL) to generate a second signal from a reference signal and to compare a phase of the feedback signal with a phase of the reference signal, the DLL being capable of keeping a relative timing of the first and second signals constant while adjusting the feedback signal to be in phase with the reference signal, wherein the DLL comprises: a first voltage control delay line (VCDL) to receive the reference signal; a second VCDL in a feedback loop to output the feedback signal; a phase detector to compare phases of the reference and feedback signals; and a capacitor circuit to generate a control voltage for the VCDLs to allow the VCDLs to adjust the phase of the feedback signal relative to the reference signal if the phases detected by the phase detector are out of phase.