Patent ID: 7188288
Filing Date: 2007-03-06
Classification: G01R

Abstract:
1. A semiconductor LSI circuit provided with a scan circuit comprising: a plurality of to-be-tested combinational logic circuits; a plurality of scan circuits adjacent to and disposed alternately with the combinational logic circuits; a plurality of scan elements, which form the scan circuits; a first selector inserted in a first scan circuit of the plurality of scan circuits and connects a first group of scan elements and a second group of scan elements in the scan circuit; a second selector inserted in a second scan circuit of the plurality of scan circuits and connects a third group of scan elements and a fourth group of scan elements in the scan circuit; a first route provided in the first group of scan elements and extending from a scanning output terminal of a scan element prior to the first selector to the first selector; and a second route provided in a third group of scan elements, and extending from the scanning output terminal of a scan element prior to the second selector to the first selector, wherein the first selector selects either the first route or the second route and the combinational logic circuits include a buffer, an inverter, a NAND gate, an AND gate, a NOR gate, an OR gate, or an exclusive OR gate.