Patent ID: 7287237
Filing Date: 2007-10-23
Classification: G06F

Abstract:
1. A method for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell, comprising: providing a semiconductor integrated circuit having an initial interconnect and an initial cell grid layout logic cell arrangement, the logic cell comprising transistor components having a minimum transistor width defining a natural transistor pitch, the interconnect layout comprising tracks for interconnecting the transistor components having a track width and track spacing defining an initial routing pitch, the natural transistor pitch and the initial routing pitch in misalignment; resizing the initial routing pitch to a resized routing pitch by scaling the initial routing pitch by a fraction 1/q, wherein q is an integer greater than 1 and wherein q is selected such that the resized routing pitch is scalable on a manufacturing grid; resizing the natural transistor pitch to a resized transistor pitch by scaling the resized routing pitch by an integer k, wherein k is selected such that the resized transistor pitch is greater than or equal to the natural transistor pitch; and aligning the cell grid having the resized transistor pitch with the interconnect layout having the resized routing pitch to form an aligned cell grid and interconnect layout of the logic cell.