Patent ID: 7045412
Filing Date: 2006-05-16
Classification: H01L,H03F,Y10S

Abstract:
1. A method of fabricating a field-effect type semiconductor device, comprising the steps of: forming a first SiGe layer having a first conductivity-type and high impurity concentration on a major surface of an Si substrate having the first conductivity-type; forming a second SiGe layer having the first conductivity-type and low impurity concentration on a major surface of said first SiGe layer; forming an Si layer having low impurity concentration on a major surface of said second SiGe layer, thus completing a semiconductor multi-layer structure; forming a groove for isolating active regions in a major surface of said semiconductor multi-layer structure; embedding an insulating material in said groove; impaling an impurity into said active region; forming a gate insulating film on a surface of said active region; forming a gate electrode on said gate insulating film; forming a drain offset region in said active region in self-alignment with said gate electrode; forming, in said active region, a drain region being separated from the edge of said gate electrode, contacting said drain offset region in self-alignment with said gate electrode and having an impurity concentration higher than that of said offset region, and a source region in self-alignment with said gate electrode; exposing said first SiGe layer or said substrate in a region near said source region; and connecting said exposed portion and said source region by metal or metal silicide.