Patent ID: 7265434
Filing Date: 2007-09-04
Classification: H01L

Abstract:
1. An NPN transistor formed in a semiconductor substrate, the substrate being doped with P-type impurity and not comprising an epitaxial layer, the transistor comprising: an N-type isolation structure extending downward from a surface of the substrate, the N-type isolation structure comprising a deep N layer and an annular N well, the deep N layer overlapping the annular N well so as to enclose an isolated P region of the substrate, the N-type isolation structure also forming a collector of the transistor, the isolated P region forming at least a portion of a base of the transistor; wherein a doping profile in a vertical cross section of the N well is non-monotonic; an N-type region located at the surface of the substrate within the isolated P region, the N-type region forming an emitter of the transistor; a shallow P-type base contact region to facilitate electrical contact to the base of the transistor, the shallow P-type base contact region having a doping concentration higher than a doping concentration of the substrate, and electrical contacts to the emitter, the base and the collector in order to facilitate electrical biasing of the NPN transistor.