Patent ID: 6337810
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array with a plurality of arranged memory cells which are selected by a column address and a row address; a bit line selection circuit for selecting based on said column address a group comprising a predetermined number of bit lines, from bit lines connected with said plurality of memory cells selected by said row address; a sense amplifier section comprised of sense amplifiers for determining data for each bit line output signals from memory cells input through said plurality of bit lines of said selected group, and outputting data from each of said bit lines as an determination result, a first latch group and a second latch group connected in common to said sense amplifier section, for storing said data of each bit line output from said sense amplifier section, and a latch selection circuit for selecting which of said first latch group data and said second latch group data to output, and then outputting a selection result as read data, wherein during burst read operation, in cases where data of said first latch group is being output as read data, said second latch group stores data from said sense amplifier, and in cases where data of said second latch group is being output as read data, said first latch group stores data from said sense amplifier.