Patent ID: 8151173
Filing Date: 2012-04-03
Classification: G06F,G11C

Abstract:
1. A semiconductor storage device comprising: a memory array including a normal array for storing normal data and a parity array for storing parity data for detecting an error in the normal data; a plurality of first data lines for writing and reading the memory array; a plurality of first data latches to which the plurality of first data lines are connected; an ECC circuit section for generating parity data to be stored into the parity array from write data to the normal array, and performing error detection/correction with respect to read data based on normal data and parity data read from the plurality of first data latches; an input/output section for interfacing between the ECC circuit section and an outside; a plurality of second data lines to which outputs of the plurality of first data latches are connected; and a plurality of third data lines to which data that has been error-corrected by the ECC circuit section is connected, wherein the plurality of second data lines are input to the ECC circuit section, the plurality of third data lines output from the ECC circuit section are connected to the input/output section, the plurality of first data latches are arranged in a column, close to the memory array in a direction in which the plurality of first data lines extend, the ECC circuit section is arranged close to the plurality of first data latches, and the plurality of first data latches and the ECC circuit section are provided substantially within a width in which the memory array is provided.