Patent ID: 7821826
Filing Date: 2010-10-26
Classification: G11C

Abstract:
1. A method for operating a memory, comprising: storing analog values in an array of analog memory cells, so that each of the analog memory cells holds an analog value corresponding to at least first and second respective bits, the array comprising word lines and bit lines connected to the analog memory cells; obtaining a first indication of the analog value stored in a given analog memory cell by precharging a bit line connected to the given analog memory cell to a first precharge voltage, and then sampling a first current on the bit line; obtaining a second indication of the analog value stored in the given analog memory cell by precharging the bit line connected to the given analog memory cell to a second precharge voltage, which is dependent upon the first indication, and then sampling a second current on the bit line; and reading out the first and second respective bits from the given analog memory cell responsively to the first and second indications.