Patent ID: 8762812
Filing Date: 2014-06-24
Classification: H03M,H04L

Abstract:
1. A decoding device comprising: a determination unit that determines whether or not a decoding ending condition is satisfied at an interval shorter than an interval of one decoding process in repeated decoding and ends the process in the middle of the one decoding process in a case where the decoding ending condition is satisfied, wherein the decoding ending condition is to satisfy a parity checking equation of a linear block code, and wherein the linear block code is an LDPC code; a bit node calculating unit that divides a bit node calculation into a first plurality of processes and performs the first plurality of processes; a bit determining unit that acquires a partial bit determining value based on a result of the first plurality of processes performed in a divided manner and performs decoding, every time the first plurality of processes divided by the bit node calculating unit are performed, wherein the determination unit determines whether or not the decoding ending condition is satisfied based on the partial bit determining value acquired by the bit determining unit; a syndrome storing unit that stores a syndrome acquired at a time when the determination of whether or not the decoding ending condition is satisfied is performed immediately before by the determination unit; a determining value storing unit that stores the partial bit determining value acquired by the bit determining unit at the time of a previous decoding process, wherein the determination unit updates the syndrome stored in the syndrome storing unit based on a difference between the partial bit determining value acquired by the bit determining unit in the present decoding process and the partial bit determining value stored in the determining value storing unit and determines whether or not the decoding ending condition is satisfied based on the updated syndrome.