Patent ID: 6781200
Filing Date: 2004-08-24
Classification: H01L

Abstract:
An insulated gate semiconductor device comprising:a semiconductor substrate of a first conductivity type; a collector region of a second conductivity type formed on a lower major surface of said semiconductor substrate; a collector electrode connected to said collector region; a base region of the second conductivity type selectively formed on an upper major surface of said semiconductor substrate; an emitter region of the first conductivity type selectively formed in said base region; a plurality of trenches including first, second, and third trenches selectively formed in said base region, each of said trenches having a depth passing through said base region and reaching the semiconductor substrate; first, second, and third gate electrodes buried in said first, second, and third trenches through insulating films, respectively; and an emitter electrode to which said base region, said emitter region, and said second gaze electrode are commonly connected, wherein said third gate electrode is connected to only said first gate electrode, and said emitter electrode is partially connected to said second gate electrode and a part of the base region bordering with the second trench.