Patent ID: 8094046
Filing Date: 2012-01-10
Classification: G10K,G10L,H04R

Abstract:
1. A signal processing apparatus, comprising: a first decimation processing section configured to generate, based on a digital signal in a first form subjected to ΔΣ modulation with a predetermined quantization bit rate of one or more bits, a digital signal in a second form subjected to pulse-code modulation so as to have a sampling frequency of n×fs, where n is a natural number and fs is a predetermined reference sampling frequency; a second decimation processing section configured to generate, based on the digital signal in the second form, a digital signal in a third form subjected to pulse-code modulation so as to have a sampling frequency of m×fs, where m is a natural number less than n; a first signal processing section configured to perform predetermined signal processing based on the digital signal in the third form; an interpolation processing section configured to convert a digital signal in the third form outputted from said first signal processing section into a digital signal in the second form; a second signal processing section configured to perform the predetermined signal processing based on the digital signal in the second form outputted from said first decimation processing section; and a combining section configured to combine the digital signal in the second form outputted from said interpolation processing section and a digital signal in the second form outputted from said second signal processing section, and output a combined digital signal.