Patent ID: 6198313
Filing Date: 2001-03-06
Classification: G11C

Abstract:
An infinite sample-and-hold circuit comprising:a. a digital-to-analog converter (DAC);b. an analog-to-digital converter (ADC), the ADC configured to receive and acquire a sample of an analog input signal and to provide to the digital-to-analog converter a digital code corresponding to a value of the sample, said digital-to-analog converter being connected to receive the digital code and provide a corresponding analog output value; andc. a mode control circuit connected between an analog input node, an output of the DAC and a node from which an output signal may be taken, and havinga comparator/buffer receiving on a first input the analog output value provided by the digital-to-analog converter, receiving on a second input the analog input signal and providing an output, and whereinin a first mode of operation, the comparator/buffer provides as an output of the sample-and-hold circuit a buffered output of the analog output value from the digital-to-analog converter and provides in a second mode of operation a signal representing a comparison between the value of the analog input signal and the analog output value from the digital-to-analog converter, and wherein the comparator/buffer employs a common input circuit for both modes of operation, whereby substantially a same input offset is presented by said input circuit in both modes of operation.