Patent ID: 6303947
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A silicon carbide vertical FET, comprising:a first conductivity type silicon carbide drain layer;a first conductivity type drift layer comprising silicon carbide, which is laminated on the first conductivity type silicon carbide drain layer;a second conductivity type gate region and a first conductivity type source region that are formed in selected portions of a surface layer of the first conductivity type drift layer, such that the gate region and the source region are spaced from each other;a second conductivity type embedded region formed in a selected portion of the first conductivity type drift layer below the second conductivity type gate region and the first conductivity type source region, such that the embedded region is not connected to the gate region and the source region;a gate electrode formed in contact with a surface of the second conductivity type gate region;a source electrode formed in contact with a surface of the first conductivity type source region;a drain electrode formed on a rear surface of the first conductivity type drain layer; anda means for electrically connecting the second conductivity type embedded region and the gate electrode,wherein said second conductivity type embedded region has the same potential as said gate electrode.