Patent ID: 6555450
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A contact forming method for a semiconductor memory device having a cell array region, a peripheral circuit regions, and gate node contact regions in a transistor forming region, comprising the steps of:forming gates at the cell array region, a plurality of active regions, and a field insulating layer of the peripheral circuit region, and forming corresponding sources and drains in the active regions; forming an insulating layer on a whole surface of the peripheral circuit and cell array regions and forming a spacer on the side wall of a gate formed in the cell array region by etching the insulating layer in the cell array region, and thereafter forming conductive impurities-doped poly silicon layer on the cell array and peripheral circuit regions; patterning the poly silicon layer formed in the cell array region, and etching the poly silicon layer and the insulating layer formed in the peripheral circuit region, thereafter forming a spacer insulating layer on the side wall of the peripheral circuit region; thinning a capping insulating layer formed on the gate and on the peripheral circuit region for ion-implantation of conductive impurities; and forming a high doping concentration on the poly silicon layer formed on the cell array region.