Patent ID: 7418675
Filing Date: 2008-08-26
Classification: G06F

Abstract:
1. A method of designing an electronic device comprising: identifying an output of a component to be coupled to a first plurality of synchronous cells; modifying placement of the first plurality of synchronous cells at one or more locations proximate to the output, wherein modifying placement of the first plurality of synchronous cells includes placing a second plurality of synchronous cells at locations proximate to the output that results in a design rule violation for each synchronous cell of the second plurality of synchronous cells; legalizing the second plurality of synchronous cells with respect to the design rule, wherein the second plurality of synchronous cells is a subset of the first plurality of synchronous cells and continues to be coupled to the output of the component after legalizing; and determining if a timing constraint of the electronic device subsequent to legalizing the first plurality of synchronous cells is met.