Patent ID: 6369731
Filing Date: 2002-04-09
Classification: H03M

Abstract:
In an nth-order (n is an integer of 2 or greater) delta sigma D/A converter, the nth-order delta sigma D/A converter comprising:a main adder to be inputted by an input signal; a quantizer having as an input an output of said main adder; a 1-sample delayer having as an input a quantization error by said quantizer; 1st-order differentiators of (nâˆ’1) in number connected continuous to an output side of said 1-sample delayer; switch means of (nâˆ’1) in number for switching each output of said 1st-order differentiators to zero value; and adders of (nâˆ’1) in number connected continuous to add together outputs of said 1st-order differentiators or an output of said 1-sample delayer, characterized in that: a sum of said adder of (nâˆ’1) in number is added with the input signal by said main adder; when the input signal is zero value, said switch means of (nâˆ’1) in number being switched to zero value in the order of from a highest order to a lower order, inputs of said 1st-order differentiators of (nâˆ’1) in number being rendered zero value, and an output value of said nth-order delta sigma D/A converter being rendered finally zero value.