Patent ID: 7093099
Filing Date: 2006-08-15
Classification: H04L

Abstract:
1. A processor comprising: an instruction decoder for decoding instructions in a program being executed by the processor, the instructions including a lookup instruction; a register file containing registers that store operands operated upon by the instructions, the registers being identified by operand fields in the instructions decoded by the instruction decoder; a memory-access unit for accessing first-level entries and second-level entries of a lookup cache, the lookup cache including at least one of: an inode section that contains inode entries and file attributes, a name cache section that stores file-name entries, a page cache section that stores page entries, and an export cache section that stores export entries; an address generator for generating a first-level address and a second-level address to the memory-access unit; a comparator for comparing tags read from the first-level entries to a key derivative and for comparing stored keys read from the second-level entries to an input key; wherein the input key is a variable-length operand while the key derivative is generated from the input key; a hashing engine, receiving the input key, for generating the key derivative from the input key; and a lookup unit, activated by the instruction decoder when the lookup instruction is decoded, for performing a lookup operation indicated by the lookup instruction, the lookup operation searching the lookup cache for a matching second-level entry that has a stored key that matches the input key, whereby the lookup instruction is decoded and executed by the processor.