Patent ID: 9047966
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a row decoder configured to decode row addresses and drive global word line driving signals on global word lines; a column decoder configured to decode column addresses and drive column selection signals on column selection lines; a plurality of sub-cell blocks, each sub-cell block including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines; a plurality of bit line sense amplifier regions, each bit line sense amplifier region including bit line sense amplifiers and disposed between two sub-cell blocks in a first direction, wherein each of the bit line sense amplifiers is configured to sense and amplify data of a corresponding bit line; a plurality of sub-word line drivers, each sub-word line driver disposed between two sub-cell blocks in a second direction perpendicular to the first direction and configured to drive corresponding word lines in response to the global word line driving signals; and a bit line selection circuit including a plurality of bit line connection controllers, and configured to select one or more bit lines in response to the column selection signals, wherein each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively.