Patent ID: 7237220
Filing Date: 2007-06-26
Classification: G06F

Abstract:
1. A high level synthesis method for a semiconductor integrated circuit in consideration of layout, the high level synthesis method comprising: a flow graph generation step of generating a flow graph associating calculations included in a function description of a design target circuit with nodes, and also associating a data flow included in the function description with edges; an initial allocation scheduling step of allocating a usable hardware resource to each of the nodes of the flow graph; allocating each node of the flow graph to a state corresponding to a clock cycle in consideration of the ordering represented by the edges of the flow graph; obtaining a total number of states required for executing processing represented by the flow graph from a result of the state allocation; and generating an allocated resource connection graph which has nodes corresponding to the nodes of the flow graph after the allocation of the hardware resource, and signal edges corresponding to the edges of the flow graph; a sharing edge generation step of adding a sharing edge between a pair of nodes which are included in the allocated resource connection graph and to which sharable hardware resources are allocated, the sharing edge being added for controlling sharing of the nodes; a resource arrangement step of providing a provisional layout of the allocated resource connection graph having the sharing edges added thereto; and a resource sharing step of sharing nodes of the allocated resource connection graph based on a layout result obtained in the resource arrangement step.