Patent ID: 8205110
Filing Date: 2012-06-19
Classification: G06F

Abstract:
1. An electronic system comprising: a set of logic blocks comprising at least a first logic block and a second logic block, wherein each of the first logic block and the second logic block include asynchronous clock domains; a global clock providing a global clock signal; a global clock routing mechanism corresponding to the global clock and overlaying the electronic system, wherein the global clock routing mechanism provides the global clock signal to the first logic block and the second logic block of the electronic system, further wherein the global clock routing mechanism is configured to provide a substantially matched global clock signal to the first logic block and the second logic block of the set of logic blocks; and a first header corresponding to the first logic block receives a first clock signal and the global clock signal and generates a first output clock signal, wherein the first clock signal corresponds to a first asynchronous clock domain; a second header corresponding to the second logic block receives a second clock signal and the global clock signal and generates a second output clock signal, wherein the second output clock signal corresponds to a second asynchronous clock domain, and wherein the first asynchronous clock domain and the second asynchronous clock domain are misaligned; and a synchronizing logic block connected between the first header and the second header, wherein the synchronizing logic block: