Patent ID: 8384145
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. A hot carrier non-volatile memory device comprising: a semiconductor substrate; a gate dielectric located upon the semiconductor substrate; a gate located upon the gate dielectric and aligned above a channel region within the semiconductor substrate; a spacer located upon a sidewall of the gate and contacting the semiconductor substrate, said spacer having a dielectric constant that is greater than 7, wherein the spacer having a dielectric constant that is greater than 7 provides enhanced hot-carrier impact ionized electron capture and retention capabilities in the hot carrier non-volatile memory device that is due to a lower charge carrier injection barrier for the spacer having the dielectric constant that is greater than 7 in comparison to a similarly structured memory device having a silicon oxide spacer; and a source region and a drain region located within the semiconductor substrate and separated by the channel region, wherein the drain region comprises a semiconductor material having a narrower bandgap than a semiconductor material from which is comprised the channel, wherein the semiconductor material having the narrower bandgap is not present in the source region, wherein the drain region having the semiconductor material of the narrow bandgap provides the hot-carrier non-volatile memory device with increased impact ionization for forming charged carrier pairs in comparison to the similarly structured memory device having a channel region and drain region with a same bandgap, said drain region of the hot carrier non-volatile memory device having an enhanced charged carrier pair generation region beneath the spacer when compared to the similarly structured memory device.