Patent ID: 6411984
Filing Date: 2002-06-25
Classification: G06F

Abstract:
A processor integrated circuit comprising:A. external address bus terminals adapted to be connected to an external memory and carry address signals from the integrated circuit; B. external data bus terminals adapted to be connected to the external memory and carry operational data signals and program data signals at least to the integrated circuit; C. a control circuits coupled to the address bus terminals and data bus terminals and producing control signals in response to program data received from the data bus terminals; D. arithmetic and logic unit circuits coupled to the control signals from the control circuits and the data bus terminals for operating on operational data from the data terminals; and E. external multiprocessor interface terminals coupled to at least the control circuits and adapted to be connected directly to another processor and carry interface signals between the processor integrated circuit and the other processor for communicating with the other processor, the external multiprocessor interface terminals include control signal terminals, the control signal terminals include a strobe signal terminal, a ready signal terminal, a request signal terminal that carries a bi-directional signal and an acknowledge signal terminal that carries a bi-directional signal, the bi-directional control signals requesting and acknowledging control by the processor integrated circuit for the transfer of data to and form the integrated circuit.