Patent ID: 8664767
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a first conductive layer disposed on a substrate and providing first electrodes and second electrodes for a distributed transistor in the substrate; a second conductive layer over the first conductive layer, the second conductive layer having a first conductive portion and a second conductive portion electrically isolated from the first conductive portion; a third conductive layer over the second conductive layer, the third conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region, the first conductive region substantially located over the first conductive portion and the second conductive region substantially located over the second conductive portion; a fourth conductive layer over the third conductive layer, the fourth conductive layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region, at least one of the first conductive area or the first conductive region including a first protrusion extending toward the second conductive area or second conductive region, respectively; first conductive vias connecting the first conductive region to the second conductive area and connecting the second conductive region to the first conductive area, the conductive vias including at least one via connected to the first protrusion; second conductive vias connecting the first conductive region to the first conductive portion through apertures in the first conductive area and connecting the second conductive region to the second conductive portion through apertures in the second conductive region; third conductive vias connecting the first conductive area to the first electrodes through apertures in the first conductive portion and connecting the second conductive area to the second electrodes through apertures in the second conductive portion; and fourth conductive vias connecting the first conductive portion to the second electrodes and connecting the second conductive portion to the first electrodes.