Patent ID: 6969655
Filing Date: 2005-11-29
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate having an active region and a non-active region; forming a first gate electrode comprising a dielectric layer pattern, a first conducting layer pattern, and a first insulating layer pattern over the active region, the first gate electrode functioning as a flash memory; forming spacers on sidewalls of the first gate electrode; forming an oxide layer on the semiconductor substrate except the region of the first gate electrode and the spacers; forming a second conducting layer and a second insulating layer over the substrate including the first gate electrode, the spacers and the oxide layer; forming a patterned mask layer on a predetermined region of the second insulating layer; forming a second gate electrode comprising a gate oxide, a second conducting layer pattern, and a second insulating layer pattern by performing a first etching process using the patterned mask layer as an etching mask to remove the second insulating layer and the second conducting layer except under the region of the mask layer, the second gate electrode functioning as a normal gate electrode; and removing a residual conducting layer on one sidewall of the spacers of the first gate electrode by performing a second etching process.