Patent ID: 6611309
Filing Date: 2003-08-26
Classification: G03F,H01L

Abstract:
A thin film transistor array panel for a liquid crystal display, comprising:an insulating substrate; a gate wire formed on the insulating substrate and including a plurality of gate lines extending in a first direction, and gate electrodes connected to the gate line; a common wire formed on the insulating substrate and including a plurality of common signal lines extending in the first direction and a plurality of common electrodes connected to the common signal lines; a pixel wire formed on the insulating substrate and including a plurality of pixel electrodes extending parallel to the common electrodes; a gate insulating layer covering the gate wire, the common wire, and the pixel wire; a semiconductor layer formed on the gate insulating layer and made of semiconductor; a data wire formed on the semiconductor layer and including a plurality of data lines extending in a second direction crossing the gate line, source electrodes and drain electrodes, wherein each source electrode is connected to its corresponding data line, and each drain electrode is separated from its corresponding data line and source electrode and located at an opposite side of the source electrode with respect to the gate electrode; a passivation layer formed on the data wire, and having a first contact hole exposing the pixel wire and the drain electrode along with the gate insulating layer; and a conductive layer formed on the passivation layer and connecting the drain electrode to the pixel wire through the first contact hole.