Patent ID: 7338874
Filing Date: 2008-03-04
Classification: H01L

Abstract:
1. A method of manufacturing a highly integrated semiconductor device, the method comprising: forming a gate electrode on a semiconductor substrate; forming an offset spacer along sidewalls of the gate electrode; growing predetermined portions of the semiconductor substrate on the both sides of the gate electrode to a predetermined thickness to form a selective epitaxial growth layer; forming a source region and a drain region in the predetermined grown portions of the semiconductor substrate on the both sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain region and a heavily doped region; and forming a silicide layer on the gate electrode, the source region, and the drain region, wherein the silicide layer is formed on each of the lightly doped drain region and the heavily doped region, and wherein the forming of the source region and the drain region and the forming of the silicide layer include: