Patent ID: 6199142
Filing Date: 2001-03-06
Classification: G06F

Abstract:
An integrated processor/memory device comprising:a CPU to issue an address;a cache bank;a main memory bank with rows of memory cells and sense amplifiers, the main memory bank being configured to simultaneously read out with the sense amplifiers all bits stored in the memory cells of an addressed row of the rows as a new cache line when a cache miss in the cache bank occurs for the issued address, the issued address specifying the addressed row; andthe cache bank comprising one or more buffers with each of the buffers comprising latches, the cache bank being configured to simultaneously store in the latches of a selected buffer of the one or more buffers all of the bits of the new cache line when the cache miss occurs;wherein the CPU, the main memory bank, and the cache bank are all integrated together on a chip; andfurther wherein the number of the memory cells in each of the rows, the number of the sense amplifiers, the number of the bits of the new cache line, and the number of latches of each of the one or more buffers are all the same number.