Patent ID: 6448120
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method for forming a totally self-aligned transistor with tungsten gate, comprising the steps of:providing an integrated circuit semiconductor structure comprising a substrate layer, a first oxide layer deposited over the substrate, a first nitride layer deposited over the first oxide layer, a second oxide layer deposited over the first nitride layer, and a second nitride layer deposited over the second oxide layer; depositing a photoresist layer in a predetermined pattern over the integrated circuit semiconductor structure; etching the second nitride layer in areas not covered by the photoresist layer to create at least one nitride island; etching the integrated circuit semiconductor structure to create at least one silicon trench; depositing an oxide layer in the silicon trench, the oxide layer deposited to a level of the first nitride layer; etching the first nitride layer, the first oxide layer and the at least one nitride island to form gate, source and drain areas; depositing at least one channel dopant in the gate area, the at least one channel dopant being deposited in the substrate layer; providing a silicide layer over the source and drain areas; and depositing a metal layer in the gate, source and drain areas.