Patent ID: 8031823
Filing Date: 2011-10-04
Classification: G06F,H04L

Abstract:
1. A delay line controller for adding delay to a clock signal and a plurality of data signals, the delay line controller comprising a plurality of skew indicator signal inputs, wherein each skew indicator signal input is capable of receiving a skew indicator signal, wherein each skew indicator signal varies as a function of a phase comparison of the clock signal to one of the data signals; a digital filter connected to each of the plurality of skew indicator signal inputs, wherein each digital filter generates a delay control signal as a function of phase comparison data received via the skew indicator signal; and control logic for controlling delay lines as a function of the delay control signals, wherein the plurality of data signals includes a latest arriving data signal and wherein the control logic includes logic for adding enough delay to the clock signal and the plurality of data signals to line up all the plurality of data signals with the latest arriving data signal and to place the clock signal in the data eye of the plurality of data signals.