Patent ID: 7930673
Filing Date: 2011-04-19
Classification: G06F

Abstract:
1. A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the method comprising: identifying, with one or more processors of one or more computer systems, a plurality of blocks in the synthesized netlist as idle candidate blocks; determining, with the one or more processors of the one or more computer systems, a clock gating structure optimized for power savings based on the idle candidate blocks; identifying, with the one or more processors of the one or more computer systems, inflexible clock gates to be inserted in the netlist; performing, with the one or more processors of the one or more computer systems, global placement of each element of the netlist on a chip; clustering, with the one or more processors of the one or more computer systems, sub-blocks on the chip into a plurality of placement-driven clusters; determining, for each of the plurality of placement-driven clusters, whether to insert a flexible clock gate on the chip with the one or more processors of the one or more computer systems based on an evaluation of each of the plurality of placement-driven clusters; performing, with the one or more processors of the one or more computer systems, detailed placement of each element of the netlist on the chip; and tuning, with the one or more processors of the one or more computer systems, the inserted flexible clock gate based on an analysis of each of the plurality of placement-driven clusters that includes the inserted flexible clock gate.