Patent ID: 8493118
Filing Date: 2013-07-23
Classification: G01R

Abstract:
1. A latch circuit comprising: a master latch having an operational data input, a scan data input, and an internal data node, wherein the master latch is configured to latch data received on the operational data input to the internal data node during operation in a first mode and further configured to latch data received on the scan data input to the internal data node during operation in a second mode; a slave latch having a scan data output, wherein the slave latch is configured to generate a scan data output signal having a state corresponding to a state of the internal data node during operation in the second mode, wherein the master and slave latches are each coupled to receive a clock signal; and a gating circuit, wherein the gating circuit is configured to cause the slave latch hold the scan data output to a constant state, irrespective of the state of the clock signal and the state of the internal data node, during operation in the first mode.