Patent ID: 6704229
Filing Date: 2004-03-09
Classification: G11C

Abstract:
A semiconductor test circuit for testing a semiconductor memory device having a function simultaneously to perform writing/reading of data signals of a plurality of memory cells designated by an address signal and having a write mask function to inhibit rewriting of the data signals of said plurality of memory cells, comprising:a write data generating circuit for generating a plurality of internal write data signals to be written into said plurality of memory cells according to an external write data signal; an internal expected value generating circuit for generating a plurality of internal expected value signals based on a read data signal from a predetermined memory cell among said plurality of memory cells; and a determination circuit for determining whether logic levels of a plurality of read data signals from said plurality of memory cells and logic levels of said plurality of internal expected value signals generated in said internal expected value generating circuit respectively match or not, and outputting a signal of a first level when the logic levels match in all respective pairs, and outputting a signal of a second level when the logic levels do not match at least in one pair.