Patent ID: 7839716
Filing Date: 2010-11-23
Classification: G11C

Abstract:
1. A clock skew control circuit for controlling timing skew between a clock signal (CK) and a first data related signal and between the CK signal and a second data related signal in a double data rate (DDR3) synchronous dynamic random access memory (SDRAM) memory subsystem, the clock skew control circuit comprising: a clock generator coupled to receive a 2× clock signal having a frequency twice that of the CK signal of the DDR3 SDRAM and adapted to generate the CK signal and adapted to generate a 45 degree phase shifted version of the CK signal (CK45) and a 90 degree phase shifted version of the CK signal (CK90) and a 135 degree phase shifted version of the CK signal (CK135); and a delayed data signal generator coupled to receive the first and second data related signals and coupled to receive the CK signal and the CK45 signal and the CK90 signal and the CK135 signal, wherein the delayed data signal generator is adapted to generate a first delayed data signal from the first data related signal selectively aligned with a leading edge of one of the CK signal and the CK45 signal and the CK90 signal and the CK135 signal, and wherein the delayed data signal generator is adapted to generate a second delayed data signal from the second data related signal selectively aligned with a trailing edge of one of the CK signal and the CK45 signal and the CK90 signal and the CK135 signal, wherein the first and second delayed data signals are applied to a DDR3 SDRAM device.