Patent ID: 7307014
Filing Date: 2007-12-11
Classification: H01L

Abstract:
1. A method of forming a via contact structure, the method comprising: forming a lower interconnection on a semiconductor substrate; sequentially forming an etch stop layer, an insulating interlayer, and a first sacrificial layer on the semiconductor substrate; sequentially patterning the first sacrificial layer and the insulating interlayer to form a preliminary via hole exposing a portion of the etch stop layer on the lower interconnection; forming a second sacrificial layer on the semiconductor substrate, the second sacrificial layer filling the preliminary via hole; sequentially patterning the second sacrificial layer, the first sacrificial layer, and the insulating interlayer to form a trench region spanning the preliminary via hole; simultaneously removing the first and second sacrificial layers using a wet etching process after forming the trench region, thereby exposing the portion of the etch stop layer; and, etching the exposed portion of the etch stop layer, thereby exposing the lower interconnection.