Patent ID: 8166337
Filing Date: 2012-04-24
Classification: G06F

Abstract:
1. A failure analysis apparatus that is implemented on an information processing apparatus having a plurality of boards each of which are mounted with a plurality of logic circuits and that analyzes a kind of a failure occurred in a logic circuit, the failure analysis apparatus comprising: storage means for storing analysis information for each logic circuit of the plurality of logic circuits mounted on the plurality of boards, each analysis information being for log information to be collected from a logic circuit and related with a board number of a board on which the logic circuit is mounted and a mounted place of the logic circuit on the board, and each analysis information further describing information to be processed when the log information is collected, information of a first condition for which the log information is to be valid, and information of a second condition for which the log information is to be invalid; collecting means for collecting log information from the plurality of logic circuits using a single logic circuit as a unit of collecting whereby the information of the first and second conditions for determining validity of the log information are correlatable to the board number of the board on which the single logic circuit is mounted and the mounted place of the single logic circuit on the board, and collecting, when a failure occurs in a logic circuit, log information indicating an occurrence of the failure from the failed logic circuit; analysis means for analyzing a kind of the failure occurred in the failed logic circuit based on the log information collected by the collection means and stored analysis information related with a board number of a board on which the failed logic circuit is mounted and a mounted place of the failed logic circuit on the board; and a buffer having a prescribed memory capacity, wherein the analysis means stores, when the log information is to be valid based on the analyzing the information of the first condition described in the analysis information, the log information in the buffer so the log information to be valid of the failed logic circuit is obtainable from the buffer, and wherein the storage means further stores common parts of a plurality of the analysis information for the plurality of logic circuits mounted on the plurality of boards as one common information that is common to the plurality of the analysis information.