Patent ID: 6242942
Filing Date: 2001-06-05
Classification: H03K

Abstract:
An integrated circuit output buffer, comprising:an output signal line;a pull-down circuit electrically coupled to said output signal line, said pull-down circuit including primary and secondary pull-down transistors therein electrically connected in parallel; anda control circuit that activates said pull-down circuit by turning on both the primary and secondary pull-down transistors during a leading portion of a pull-down time interval and by turning off the secondary pull-down transistor during a trailing portion of the pull-down time interval using a first feedback switch that is electrically coupled in series between said output signal line and a control electrode of the secondary pull-down transistor so that an electrical path extending from said output signal line and through the first feedback switch to the control electrode of the secondary pull-down transistor represents an RC network during the trailing portion of the pull-down time interval.