Patent ID: 8431999
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. A low capacitance transient voltage suppressor, comprising: an N-type heavily doped substrate; an epitaxial layer formed on said N-type heavily doped substrate; at least one steering diode structure formed in said epitaxial layer, wherein said steering diode structure comprising: a second P-type lightly doped well formed in said epitaxial layer, wherein a second N-type heavily doped area and a third N-type heavily doped area are formed in said second P-type lightly doped well, and said second N-type heavily doped area is connected with said second P-type heavily doped area; and an N-type heavily doped well formed in said epitaxial layer and connected with said third N-type heavily doped area; and at least one deep isolation trench formed in said epitaxial layer, having a depth greater than or equal to depths of all said doped wells, and separating at least one said doped well.