Patent ID: 6781879
Filing Date: 2004-08-24
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory comprising:a plurality of nonvolatile memory cells, at least one of said plurality of nonvolatile memory cells is addressed by address signals Ai (i=0, . . . , Iâˆ’1), each of said address signals Ai (i=0, . . . , Iâˆ’1) including first address subset Aj (j=0, . . . , Jâˆ’1), second address subset Ak (k=J, . . . , Kâˆ’1), and third address subset Al (l=K, . . . , Lâˆ’1); a plurality of word lines and a plurality of bit lines which are connected to said plurality of nonvolatile memory cells; an address buffer to which said first address subset is inputted as a first column address, said second address subset is inputted as a first row address, and a third address subset is inputted as a second column address; and a decoder to which the output signal of said address buffer is supplied and which is configured to select at least one of said plurality of nonvolatile memory cells, wherein said plurality of bit lines are selected by at least said third address subset, and said plurality of word lines are selected by at least said second address subset.