Patent ID: 8179955
Filing Date: 2012-05-15
Classification: H03M,H04L

Abstract:
1. A data processing apparatus arranged in operation to recover data bits from data symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol and to form an output bit stream, the data processing apparatus comprising: a symbol de-interleaver configured to read-into a symbol interleaver memory the predetermined number of data symbols from the OFDM sub-carrier signals, and to read-out of the symbol interleaver memory the data symbols into an output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals into the output symbol stream, a de-mapping unit configured to generate from the data symbols of the output symbol stream parity interleaved low density parity check (LDPC) encoded data bits by converting each of the data symbols of the output symbol stream representing a modulation symbol of the OFDM sub-carrier signals into data bits corresponding to a modulation scheme, an inverse permuter configured to perform an inverse permutation process to effect a reverse of a permutation process applied to the parity interleaved LDPC encoded data bits to permute the LDPC encoded data bits so that a plurality of the LDPC encoded data bits corresponding to a value of 1 in an arbitrary row of an information matrix corresponding to information bits of an LDPC code, which was used to encode the data bits, is not incorporated into the same symbol; and an LDPC decoder adapted configured to perform LDPC decoding on the LDPC encoded data bits on which the inverse permutation process has been performed to form the output data bits, wherein the symbol de-interleaver includes: an address generator configured to generate the set of addresses, an address being generated for each of the received data symbols to indicate the OFDM sub-carrier signal from which the received data symbol is to be mapped into the output symbol stream, the address generator comprising: a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation code to form an address of one of the OFDM sub-carriers, and a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, and wherein the predetermined maximum valid address is approximately thirty two thousand, the linear feedback shift register has fourteen register stages with a generator polynomial for the linear feedback shift register of R′ i [13]=R′ i-1 [0]⊕R′ i-1 [1]⊕R′ i-1 [2]⊕R′ i-1 [12], and the permutation code forms, with an additional bit, a fifteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] in accordance with the table: