Patent ID: 7418578
Filing Date: 2008-08-26
Classification: G06F

Abstract:
1. A processor, comprising: a plurality of attribute queues, each attribute queue further including a plurality of queue entries, wherein: a corresponding queue entry from each of said plurality of attribute queues are simultaneously assignable to each of a first plurality of conditional execution instruction groups, a second corresponding queue entry from each of said plurality of attribute queues are assignable at a later time to each of a second plurality of conditional execution instruction groups, a link pointer to at least one conditional execution instruction group can also be provided to a same stage with a link pointer to at least one other grouped instruction for simultaneous execution of said one other grouped instruction with said at least one instruction of the conditional instruction group, wherein each conditional execution instruction group has both a conditional execution instruction and a code block, wherein each queue entry of its corresponding attribute queue is configured to store an attribute of the conditional execution instruction of its assigned conditional execution instruction group, wherein the attribute comprises a value indicative of a condition specified by a conditional execution instruction of the assigned conditional execution instruction group, and wherein a result of each of the at least one instruction of the code block of the conditional execution instruction group is saved dependent upon the existence of the specified condition in the processor stored in the queue entry during execution of the conditional execution instruction.