Patent ID: 7184325
Filing Date: 2007-02-27
Classification: G11C

Abstract:
1. An input circuit for a memory device operating in synchronism with a clock signal comprising: data buffer part for receiving data applied from an external of the input circuit; input multiplexer part for receiving the data passed through the data buffer part; data bus writer part receiving the data passed through the input multiplexer part and outputting the data to global input/output lines of the memory device; and input selection signal generation circuit outputting a signal to control the operation of the data bus writer part, wherein the output signal of the input selection signal generation circuit is activated when both a first control signal generated after a write command is applied and then the clock signal is toggled n times and a second control signal generated after a write command is applied and then the clock signal is toggled (n−1) times are enabled, said first control signal being generated in synchronism with a rising edge of the n-th clock signal generated after the write command is applied, and the second control signal is generated in synchronism with a rising edge of the (n−1)-th clock signal generated after the write command is applied.