Patent ID: 6621747
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A data-in sort clock method for a memory device having an on-chip clock, data strobe and write address signals comprising:evaluating a state of said write address signal when said on-chip clock and data strobe signals are both in a first logic state thereof; setting a rising edge data signal to a second logic state if said write address signal is in a first logic state thereof during said step of evaluating; allowing data transmission on an internal write bus of said memory device in response to said second logic state of said rising edge data signal; setting said rising edge data signal to a first logic state if said data strobe and on-chip clock signals are both in a second logic state thereof; disallowing further data transmission on said internal write bus of said memory device in response to said first logic state of said rising edge data signal; and maintaining said rising edge data signal in a previous logic state thereof if said data strobe and on-chip clock signals are in respectively differing logic states thereof.