Patent ID: 6721897
Filing Date: 2004-04-13
Classification: G06F

Abstract:
A bus control circuit for use in a semiconductor device communicating with an external device via a system-to-external bus, for effecting timing control of the system-to-external bus, comprising:cycle registers provided for respective cycles that occur during communication with the system-to-external bus and provided with signal level areas for holding signal levels of respective system-to-external bus control signals; and a default register provided with normal level areas each holding a signal level of the corresponding system-to-external bus control signal in a normal state, wherein the signal levels of the system-to-external bus control signals held in the corresponding signal level areas in said cycle registers are output according to a predetermined schedule demanded by an arrangement of the signal level areas, and the signal levels of the system-to-external bus control signals held in the corresponding normal level areas in the default register are output when the normal state takes over.