Patent ID: 6449204
Filing Date: 2002-09-10
Classification: G11C

Abstract:
A semiconductor memory device including:a plurality of memory cells arranged in rows and columns; a plurality of word lines provided corresponding to the rows and each connected to the memory cells on a corresponding row; a plurality of bit lines provided corresponding to the columns and each connected to the memory cells on a corresponding column, said plurality of bit lines being arranged in pairs and each bit line pair including first and second bit lines; and row select circuitry for generating a select signal selecting a word line among said plurality of word lines according to an address signal and an operating mode instructing signal, said row select circuitry including a mode switch circuit for selecting the word line corresponding to an addressed row according to said address signal when said operating mode instructing signal designates a first operating mode, and selecting said addressed row and a row associated with the addressed row simultaneously when said operating mode instructing signal designates a second operating mode, said addressed row and said row associated with the addressed row being selected such that memory cells are located, in each bit line pair, corresponding to an intersection between one of said first and second bit lines and said word line corresponding to said addressed row and an intersection between another of said first and second bit lines and the word line corresponding to the associated row.