Patent ID: 6487629
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A semiconductor memory for operation in a plurality of operational modes including at least a read, a write and a set up mode, the semiconductor memory comprising:an instruction decoder, receiving an instruction code signal for setting up one of the plurality of operational modes, receiving a mode set-up instruction signal for modifying operational mode information defining a previously set up operational mode, and decoding the instruction code signal and the mode set-up instruction signal; at least one register connected to the instruction decoder for storing the operational mode information corresponding to the decoded instruction code signal; a memory core for storing data, wherein the memory core is accessed in the operational mode which is set up; and a mode set-up control circuit connected to the instruction decoder, wherein the mode set-up control circuit receives the decoded mode set-up instruction signal and loads the operational mode information corresponding to the decoded mode set-up instruction signal into the register in response to the termination of the previously set up operational mode.