Patent ID: 6563743
Filing Date: 2003-05-13
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of first memory cells for storing either one of first information and second information, arranged at points of intersection between a plurality of word lines and a plurality of first data lines; a plurality of first dummy cells for storing said first information, arranged at points of intersection between said plurality of word lines and first dummy data lines; a plurality of second dummy cells for storing said second information, arranged at points of intersection between said plurality of word lines and second dummy data lines; a first multiplexer connected to one of the ends of said plurality of first data lines; a second multiplexer connected to one of the ends of said first and second dummy data lines; a third multiplexer connected to the other end of said plurality of first data lines; a fourth multiplexer connected to the other ends of said first and second dummy data lines; and a read circuit connected to said first and second multiplexers; wherein: when said either of said first and second information is written to any of said plurality of first memory cells, said first multiplexer supplies a second potential smaller than a first potential to one of said plurality of first data lines when said third multiplexer supplies said first potential to one of said plurality of first data lines, and supplies said first potential to one of said plurality of first data lines when said third multiplexer supplies said second potential to one of said plurality of first data lines.