Patent ID: 6897794
Filing Date: 2005-05-24
Classification: H03M

Abstract:
1. A calibrated digital-to-analog converter (DAC), comprising: a main DAC having a digital input and an analog output, the main DAC being configured, in the event a plurality of first digital code values are applied to its digital input, to produce corresponding analog output values at its analog output, wherein the analog output values produced by the main DAC deviate from desired analog output values of the main DAC; a memory having an address input and first and second data outputs, the memory being configured to store a plurality of second digital code values representing respective digital correction values, the memory being configured, in the event a predetermined number of high order bits of the first digital code values are applied to its address input, to provide selected consecutive correction values at its first and second data outputs, respectively; a first calibration DAC having a digital input, an analog output, a positive reference (Vref+) voltage input, and a negative reference (Vref−) voltage input, the first calibration DAC being configured, in the event Vref+ and Vref− voltage levels corresponding to the consecutive correction values provided at the first and second data outputs, respectively, of the memory are applied to its Vref+ and Vref− voltage inputs, and a sequence of low order bits of the first digital code values is applied to its digital input, to produce corresponding analog output values at its analog output; and an analog summing circuit configured to receive the analog outputs produced by the main DAC and the first calibration DAC, and to subtract the analog output of the first calibration DAC from the analog output of the main DAC to generate a calibrated analog output.