Patent ID: 6397241
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A multiplier having a plurality of interconnected multiplier cells, wherein a first one of the multiplier cells comprises:a first adder having a data input coupled for receiving a first data signal, a second input, and an output that supplies a data output signal; and a blocking circuit having an input coupled for receiving a carryin signal, an output coupled to the second input of the first adder, and a control input coupled for receiving a select signal; a second adder having first and second inputs coupled for receiving respective second and third data signals; a third adder having a first input coupled to a first output of the first adder and a second input coupled to a first output of the second adder; and a fourth adder having a first input coupled to a first output of the third adder, a second input coupled to a second output of the first adder, and a third input coupled to a second output of the second adder.