Patent ID: 8133789
Filing Date: 2012-03-13
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a silicon carbide power DMOSFET, comprising: providing a silicon carbide drain region of a first conductivity type; forming a silicon carbide base region of a second conductivity type above said drain region; forming a silicon carbide source region of said first conductivity type adjacent an upper surface of said base region; creating a channel extending from said source region through said base region adjacent a gate interface surface thereof, said channel having a length less than approximately 0.6 μm; and creating self-aligned base and source ohmic contacts; wherein said base region has a doping concentration of said second conductivity type sufficiently high that a potential barrier at the source end of the channel is not lowered by a voltage applied to the drain; and wherein said base region is formed by ion implantation using a polysilicon mask and said source region is subsequently formed in said upper surface of said base region by ion implantation using an implant mask formed by oxidation of the polysilicon mask.