Patent ID: 6798702
Filing Date: 2004-09-28
Classification: G11C

Abstract:
A semiconductor memory device having a test mode and a normal mode as operation modes, comprising:a memory cell array divided into a plurality of areas; a plurality of read data lines provided corresponding to said plurality of areas, respectively, to communicate data; a plurality of write data lines provided corresponding to said plurality of areas, respectively, to communicate data; a replacement control circuit for holding replacement information in a non-volatile manner and outputting a shift control signal in accordance with said replacement information; and a data line shift circuit for selecting a prescribed number of read data lines to be used from said plurality of read data lines and selecting a prescribed number of write data lines to be used from said plurality of write data lines, said data line shift circuit including a first switch circuit for connecting, in said normal mode, either one of first and second write data lines of said plurality of write data lines to a first input node in accordance with said shift control signal and connecting, in said test mode, said first write data line to said first input node, a second switch circuit for connecting, in said normal mode, either one of first and second read data lines of said plurality of read data lines to a first output node in accordance with said shift control signal and connecting, in said test mode, said first read data line to said first output node, and a first data transmission circuit configured to be activated in said test mode and configured for transmitting data of said first write data line to said first read data line.