Patent ID: 6240502
Filing Date: 2001-05-29
Classification: G06F

Abstract:
A processor that executes coded instructions wherein the coded instructions comprise instructions from one or more threads, the processor comprising:a processor create unit coupled to said processor to reconfigure the processor as a uniprocessor or in a multiprocessor configuration by specifying a number of virtual processors in response to a processor create instruction;a fetch unit coupled to the processor create unit and operative to fetch selected bundles of instructions on a thread-by-thread basis from a memory;a marking unit coupled to the fetch unit and operative to receive the instruction bundles from the fetch unit and mark each bundle with a thread identification, wherein each thread has a unique thread identification;a dependency checking unit coupled to the fetch unit and operative to determine-dependency between instructions;a scheduling unit coupled to the dependency checking unit to receive the marked instructions from the dependency checking unit and operative to pick instructions for execution on a thread-by-thread basis based on results from the dependency checking unit;a plurality of architectural register files, each file comprising a plurality of architectural registers;at least one execution unit receiving picked instructions from the scheduling unit and computing instruction results from source values in the architectural registers;a retirement unit responsive to the at least one execution unit for transferring the instruction results to architectural registers; anda data cache unit receiving the instruction results and saving the instruction results to a memory.