Patent ID: 7250796
Filing Date: 2007-07-31
Classification: H03K

Abstract:
1. An output circuit for transmitting a signal of a logic corresponding to a logic of an internal signal on an internal node to an output pad via an output signal line, comprising: a first drive element coupled between said output signal line and a reference voltage supply node, and responsive to said internal signal for being rendered conductive for driving said output signal line to a voltage level on said reference voltage supply node with a first current driving capability; and a second drive element connected between said output signal line and said reference voltage supply node, and arranged at a position closer to said output pad than said first drive element is, and rendered conductive at a timing later than said first drive element in response to said internal signal for driving said output node to a potential level on said reference voltage node with a second driving capability greater than said first current driving capability, wherein: said output pad is coupled to an output terminal, and said internal signal is supplied from a bus amplifier, a time difference between a rendered-conductive timing of said first drive element and a rendered-conductive timing of said second drive element is decreased as a distance between said internal node and said bus amplifier or a sum of a distance between said output pad and said output terminal and a distance between said bus amplifier and said internal node increases.