Patent ID: 7624329
Filing Date: 2009-11-24
Classification: G06F,G11C

Abstract:
1. A method for programming a non-volatile memory array comprising addressable units, wherein each of the addressable units is configured to store at least a main portion and an error correction portion, the method comprising: in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode, wherein in the error correction disabled mode at least one main array bit corresponding to data to be stored in the main portion of at least one addressable unit of the non-volatile memory array is generated and programming at least the main portion of the at least one addressable unit of the non-volatile memory array in the error correction disabled mode; and in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.