Patent ID: 6480917
Filing Date: 2002-11-12
Classification: G06F

Abstract:
An information processing system comprising:a system bus; at least a first processing device coupled to said system bus; a system memory coupled to said system bus; a bridge circuit, said bridge circuit including a primary interface having at least one primary node, said primary interface being coupled to said system bus, said bridge circuit further including a secondary interface having a plurality of secondary nodes; a plurality of adapter busses, said adapter busses being arranged for having adapter devices connected thereto, said plurality of adapter busses being coupled to a secondary side of said bridge circuit; and arbiter means coupled to said adapter busses, said arbiter means being selectively operable for arbitrating access requests from any of said primary and secondary nodes, said arbiter means being further selectively operable for arbitrating peer-to-peer access requests between different ones of said secondary nodes.