Patent ID: 7074685
Filing Date: 2006-07-11
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising an SiGe heterojunction bipolar transistor using a non-selective epitaxial growth including the acts of forming an insulating layer on a substrate and providing a layer structure including a conductive layer on the insulating layer, etching a transistor area opening through the conductive layer, depositing a SiGe base layer inside the transistor area opening and forming an insulator on an upper surface so as to fill the transistor area opening, wherein prior to the filling step, a nitride layer is formed as an inner layer of the transistor area opening, removing an upper portion of said insulator formed on said upper surface, and etching the SiGe base layer whilst employing the nitride layer formed within the transistor area opening as a mask.