Patent ID: 7199623
Filing Date: 2007-04-03
Classification: H03K

Abstract:
1. A power-on reset circuit for outputting a power-on reset signal through an output node, comprising: a reset circuit for generating a reset voltage signal when a power supply voltage reaches a first voltage level; a level detector for generating a detection voltage signal when the power supply voltage reaches a second voltage level greater than the first voltage level; an output node coupled to receive a voltage signal; and a latch circuit for receiving the reset voltage signal from the reset circuit to reset the output node, and receiving the detection voltage signal from the level detector to output a power-on reset signal through the output node, wherein the latch circuit contains a pull-down driver including at least two NMOS transistors, one of which is diode-connected, and resets the voltage signal of the output node when a voltage of the output node reaches a third voltage level that is lower than the second voltage level and higher than the first voltage level.