Patent ID: 7684243
Filing Date: 2010-03-23
Classification: G11C

Abstract:
1. A method for reducing read failure in a memory device having a memory block array with a drain side and a source side, the method comprising: selecting a single word line; determining if the selected word line is closer to the drain side of the memory block array or the source side of the memory block array; if the selected word line is closer to the drain side of the memory block array, biasing all word lines of the memory block array, other than the selected word line, with a first pass voltage during a read operation; and if the selected word line is closer to the source side of the memory block array, biasing all word lines of the memory block array, other than the selected word line, with a second pass voltage during the read operation, wherein the first pass voltage is higher than the second pass voltage and further wherein unselected word lines are all biased at one of either the first pass voltage or the second pass voltage as the selected word line moves between the source side and the drain side.