Patent ID: 6292866
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A processor for controlling execution of instructions stored in a main storage and for performing interruption processing, said processor comprising:interruption execution control means for accepting an interruption request, analyzing an accepted interruption request to obtain a cause of an interruption, and generating information indicating a storage position in the main storage where a procedure for performing processing for the cause of the interruption is stored;specific address holding means for holding first address information obtained from the information generated by said interruption execution control means; andinstruction execution control means for deciding whether or not the first address information held by said specific address holding means is to be used as information indicating a storage position of an instruction to be executed and for controlling execution of the instruction according to a result of the decision;wherein said interruption execution control means outputs information indicating the interruption request to said instruction execution control means; andwherein said instruction execution control means, upon receiving the information indicating the interruption request, generates information indicating a storage position in the main storage of a predetermined procedure and controls execution of the instruction so that the generated information is used as information indicating the storage position of the instruction to be executed.