Patent ID: 8659321
Filing Date: 2014-02-25
Classification: G11C

Abstract:
1. A semiconductor device comprising: a pair of bit lines; a sense amplifier having first and second power supply nodes, the sense amplifier connecting one of the pair of bit lines to the first power supply node and connecting the other of the pair of bit lines to the second power supply node based on a potential difference between the pair of bit lines; a first driver circuit supplying a first potential to the first power supply node of the sense amplifier; a second driver circuit supplying a second potential to the second power supply node of the sense amplifier; a third driver circuit supplying a third potential to the second power supply node of the sense amplifier; and a timing control circuit controlling operations of the first to third driver circuits, wherein a potential difference between the first potential and the third potential is larger than a potential difference between the first potential and the second potential, the timing control circuit turns the first and third driver circuits ON and then turns the third driver circuit OFF and turns the second driver circuit ON, the timing control circuit includes a plurality of delay circuits that decide an ON period of the third driver circuit, the delay circuits include a first delay circuit having a delay amount that depends on an external power supply potential supplied from outside and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.