Patent ID: 7388416
Filing Date: 2008-06-17
Classification: H03K

Abstract:
1. A latch circuit comprising: a data reading unit that reads both a first input data and a second input data, and outputs both a first output data and a second output data based on both the first input data and the second input data, wherein both the first input data and the second input data are differential signals, and both the first output data and the second output data are differential signals that have phases that are inverted; and a data holding unit that holds both the first output data and the second output data, wherein the latch circuit operates based on a clock signal that is supplied from an outside source, both the data reading unit and the data holding unit are voltage driven type, and the data reading unit includes: the data holding unit includes: the fourth inverter circuit reads the third inverter output data while the third inverter circuit reads the fourth inverter output data.