Patent ID: 6914815
Filing Date: 2005-07-05
Classification: G11C

Abstract:
1. A nonvolatile semiconductor device comprising: a memory cell array region in which a plurality of memory cells are arranged in a row direction and a column direction, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates; and a control gate drive section which drives the first and second control gates of each of the memory cells within the memory cell array region, wherein the memory cell array region includes a plurality of sector areas which are formed by dividing the memory cell array region in the row direction, wherein each of the plurality of sector areas includes a plurality of block areas which are formed by dividing each of the sector areas in the column direction, and wherein the control gate drive section includes a plurality of control gate drivers each of which corresponds to each of the plurality of block areas, and each of the plurality of control gate drivers sets potentials of the first and second control gates in corresponding one of the block areas, independently of the other block areas.