Patent ID: 8514602
Filing Date: 2013-08-20
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a substrate provided with a memory cell part and sense amplifiers on a surface of the substrate; first isolation regions and first device regions disposed in the substrate under the memory cell part; second isolation regions and second device regions disposed in the substrate under the sense amplifiers; memory cell transistors placed in the memory cell part, each of which includes a tunnel insulator and a charge storage layer successively disposed on one of the first device regions; peripheral transistors placed in the sense amplifiers, each of which includes a gate insulator and a gate electrode successively disposed on one of the second device regions; a plurality of interconnects disposed on the substrate in the sense amplifiers, extending in a first direction parallel to the surface of the substrate, being adjacent to one another in a second direction perpendicular to the first direction, and arranged in a same interconnect layer; and a plurality of bit lines disposed on the substrate in the memory cell part, extending in the first direction, being adjacent to one another in the second direction, and electrically connecting the memory cell part and the sense amplifiers, at least one of the second device regions comprising: first and second stripe portions extending in the first direction, being adjacent in the second direction, and having stripe shapes; and a connecting portion disposed to connect the first stripe portion and the second stripe portion, the device further comprising a source contact disposed on the connecting portion, and electrically connected to one of the interconnects.