Patent ID: 6197641
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A process for fabricating a vertical transistor comprising:forming a first device region selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate;forming a multilayer stack comprising at least three layers of material over the first device region in the semiconductor substrate wherein the second layer is interposed between the first and the third layers;forming a window in the at least three layers of material, wherein the window terminates at the first device region formed in the semiconductor substrate;filling the window with a semiconductor material thereby forming a semiconductor plug in the at least three layers of material, wherein the plug has a first end and a second end and wherein the first end is in contact with the first device region;chemical mechanical polishing the surface of the substrate after the window is filled with the semiconductor material wherein the chemical mechanical polishing stops at a top layer of the multilayer stack;forming a second device region selected from the group consisting of a source region and a drain region in the second end of the silicon plug, wherein one of the first and second device regions is a source region and the other is a drain region;removing a portion of the third layer, thereby exposing the second layer underlying the removed portion of the third layer;removing the second layer, thereby exposing a portion of the semiconductor plug;forming a layer of dielectric material on the exposed portion of the semiconductor plug;forming a gate in contact with the layer of dielectric material.