Patent ID: 6300654
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A memory array, comprising a plurality of stacked cells, each cell comprising a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above said active region, each of said MOS transistors having a first and a second conductive region and a control electrode and each of said capacitors having a first and a second plate separated by a dielectric material region; said first conductive region of each of said MOS transistors being connected to said first plate of a respective capacitor, said second conductive region of each of said MOS transistors being connected to a respective bit line of a plurality of bit lines, said control electrode of each of said MOS transistors being connected to a respective word line of a plurality of word lines, said second plate of each capacitor being connected to a respective plate line of a plurality of plate lines, said plate lines running perpendicular to said bit lines and parallel to said word lines; wherein at least two cells adjacent to each other in a direction parallel to said bit lines share the same dielectric material region.