Patent ID: 6778529
Filing Date: 2004-08-17
Classification: H04L

Abstract:
A synchronous switch for a telecommunications node, comprising:a switch interface operable to terminate a bus and to receive from the bus a frame having a plurality of time slots that are each operable to transport a traffic cell; a switch controller operable to determine a type for each traffic cell received at the switch interface and to determine based on the type for a traffic cell an address for storing the traffic cell in a switch memory; the switch memory operable to receive the traffic cell from the switch interface and the address for storing the traffic cell from the switch controller and to store the traffic cell at the address; the switch memory comprising a plurality of addressable time division multiplex (TDM) memory slots and a plurality of asynchronous transfer mode (ATM) queues associated with output ports; and the switch controller further operable to determine an ATM queue in the switch memory for storing a traffic cell in response to determining the traffic cell is of an ATM type and to determine an address of one of the plurality of addressable TDM memory slots in the switch memory for storing a traffic cell in response to determining the traffic cell is of a TDM type, the determined address within the addressable TDM memory slots based on a header for the traffic cell.