Patent ID: 8138598
Filing Date: 2012-03-20
Classification: H01L,H02M

Abstract:
1. A semiconductor device including a DC-DC converter, comprising: a first die pad having an input power supply terminal; a second die pad having an output terminal; a third die pad; a lead having a reference potential terminal, which is adjacent to the second die pad; a first semiconductor chip including a high side MOSFET of the DC-DC converter, which is mounted over the first die pad, the first semiconductor chip having a first gate electrode pad, a first source electrode pad and a first drain electrode of the high side MOSFET, the first drain electrode being electrically coupled to the input power supply terminal, the first source electrode pad being electrically coupled to the output terminal; a second semiconductor chip including a low side MOSFET of the DC-DC converter, which is mounted over the second die pad, the second semiconductor chip having a second gate electrode pad, a second source electrode pad and a second drain electrode of the low side MOSFET, the second source electrode pad being electrically coupled to the reference potential terminal, the second drain electrode being electrically coupled to the output terminal; a third semiconductor chip including a first driver circuit driving the high side MOSFET and a second driver circuit driving the low side MOSFET, which is mounted over the third die pad, the third semiconductor chip having a first electrode pad electrically coupled to an output of the first driver circuit and a second electrode pad electrically coupled to an output of the second driver circuit, a first bonding wire for electrically coupling the first electrode pad of the third semiconductor chip and the first gate electrode pad of the first semiconductor chip; a second bonding wire for electrically coupling the second electrode pad of the third semiconductor chip and the second gate electrode pad of the second semiconductor chip; a first metal sheet interconnect coupled to the first source electrode pad of the first semiconductor chip and the second die pad, the first source electrode pad of the first semiconductor chip and the second drain electrode of the second semiconductor chip being electrically coupled via the first metal sheet interconnect and the second die pad; a second metal sheet interconnect coupled to the second source electrode pad of the second semiconductor chip and the lead; and a resin body covering the first, second and third semiconductor chips, the input power supply terminal being exposed from the resin body, the reference potential terminal being exposed from the resin body, the output terminal being exposed from the resin body, wherein a Schottky Barrier Diode is formed in the second semiconductor chip, and an anode and a cathode of the Schottky Barrier Diode are electrically coupled to the second source electrode pad and the second drain electrode of the second semiconductor chip, respectively.