Patent ID: 6584525
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A processing system having an extended bus, the processing system comprising:a central bus for carrying address, data and control signals relating to the address and data on the central bus; having at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus; and at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of an unassigned location in the space causes the activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit for executing instructions and a register set residing in the inexhaustively decoded space, the instruction processing unit executing an instruction that references an unassigned location in the space to cause activation of the select signal; and wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.