Patent ID: 6623987
Filing Date: 2003-09-23
Classification: B82Y,G11C,H01L

Abstract:
A process for passivating a magneto-resistive bit structure characterized by the steps of:providing a GMR stack upon a substrate; providing an etch stop barrier layer upon said GMR stack; providing a first dielectric layer upon said barrier layer; building an ion mill mask upon said barrier layer by reactive ion etching of said first dielectric layer; patterning said GMR stack and said barrier layer by ion milling to provide a patterned GMR stack having side walls and a patterned barrier layer having side walls, and removing said ion mill mask; providing a second dielectric layer upon the patterned barrier layer; planarizing said second dielectric layer; and etching the planarized second dielectric layer to leave dielectric spacers along the side walls of the patterned GMR stack.