Patent ID: 6118823
Filing Date: 2000-09-12
Classification: H04N

Abstract:
A digital video encoder system comprising:a refinement processor for reconstructive processing for I-picture and P-picture encoding, said refinement processor including a frame difference unit;wherein said frame difference unit comprises a predicted error array (PE array), said PE array comprising a shared-use storage structure for holding a macroblock of data, storing both luminance component data and chrominance component data of the macroblock, within a dual-port array for controlling simultaneous reading and writing of the macroblock data from and to the PE array; andsequence control logic for said PE array to provide synchronous writing and reading of both luminance component data and chrominance component data of the macroblock to and from said PE array, wherein said sequence control logic preserves sequencing of transfers of luminance and chrominance component data both into and out of the PE array, and wherein a data transfer sequence of macroblock data written to the PE array is identical to a required data transfer sequence of macroblock data to be read from the PE array, said sequence control logic comprising a single point of control for controlling the simultaneous reading and writing of both luminance component data and chrominance component data of the macroblock into and out of the dual-port, shared-use PE array.