Patent ID: 6714454
Filing Date: 2004-03-30
Classification: G11C,H01L

Abstract:
A method of operating a memory cell having first and second junctions in a body region, the first and second junctions being separated by a channel region, the separation between the first and second junctions defining a cell channel length extending horizontally, each of the first and second junctions having a vertically-extending width, a horizontally-extending length, and a depth, the memory cell further having first and second floating gates extending over the channel region, and a select-gate extending over the first and second floating gates and extending across the entire length of each of the first and second junctions, the select gate being separated from the first and second floating gates only by an insulating layer, the method comprising:storing a first bit of data in the first floating gate; storing a second bit of data in the second floating gate; in a first read operation, reading only the first bit of data; and in a second read operation, reading only the second bit of data.