Patent ID: 8416002
Filing Date: 2013-04-09
Classification: H03K

Abstract:
1. A flip-flop circuit comprising: a pre-charge circuit configured to receive a clock signal and configured to generate a charged signal, wherein the charged signal is HIGH when the clock is LOW; a delayed clocked input circuit configured to connect to the clock signal, and an input signal and configured to selectively generate a delayed clocked input controlled signal with the same value as the input signal when the clock is HIGH; a charge keeper circuit configured to receive the charged signal, and the delayed clocked input controlled signal and configured to generate a charge keeping signal, wherein the charge keeping signal is coupled to the charged signal and the delayed clocked input controlled signal, has the same value as the charged signal when the clock is LOW, and has the same value as the delayed clocked input controlled signal when the clock is HIGH; a separator circuit configured to receive the charge keeping signal, the clock signal, and configured to selectively generate an inverted charge keeping signal; and a storage circuit configured to selectively receive the inverted charge keeping signal, a present state signal, and configured to generate the present state signal.