Patent ID: 6243798
Filing Date: 2001-06-05
Classification: G06F

Abstract:
A computer system comprising, in combination:a linearized program memory for storing instructions to be executed by a processor system;a first address bus coupled to said program memory for sending said address of said instructions to be fetched to said program memory;a pointer coupled to said first address bus for storing a first address location of a first word of a two word jump instruction in said program memory to be fetched and for placing said first address location of said jump instruction in said program memory to be fetched on said first address bus; anda second address bus having one end coupled to an output of said program memory and a second end coupled to said first address bus for placing a second address of an operand of a second word of said two word jump instruction on said first address bus after an address of an operand of said first word of said two word jump instruction has been placed on said first address bus thereby providing a full address value of said two word jump instruction to said program memory;wherein said two word jump instruction is enabled to be executed in the same number of cycles as a single word jump instruction.