Patent ID: 7674660
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A method of fabricating a multilevel semiconductor integrated circuit, comprising: forming on a first active semiconductor structure a first plurality of transistors with respective gate structures disposed on a first substrate and source or drain regions disposed within the first substrate; depositing a first insulation layer on the first substrate and the gate structures; etching the first insulation layer to form a plurality of openings exposing portions of the first substrate contacting the bottoms of the openings; filling the openings with semiconductor material the same as in the first substrate; forming a second active semiconductor layer on the insulation layer and the filled openings; subjecting the second active semiconductor layer to at least one application of laser irradiation to form a protrusion region with a peak at or near the middle of two adjacent openings; forming on a second active semiconductor structure a second plurality of transistors with respective gate structures disposed on the second active semiconductor layer and sources and drains within the second active semiconductor layer; depositing a second insulation layer on the second active semiconductor layer and the gate structures of the second plurality of transistors; etching a portion of the second insulation layer at or near the peak of the protrusion region to form a contact hole extending to the surface of the first substrate; and depositing a conductive layer in the contact hole to form a contact structure to electrically connect a transistor of the first active semiconductor structure to a transistor of the second active semiconductor structure.