Patent ID: 6476450
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A BICMOS semiconductor integrated circuit device comprising a semiconductor substrate having an insulating layer internally and partially embedded therein, an insulating-layer-free portion and a semiconductor layer deposited on said insulating layer, an insulated gate type transistor insulated in said semiconductor layer, a highly-doped collector layer embedded in said insulating-layer-free portion of said semiconductor substrate, and a low-doped collector layer disposed on said highly-doped collector layer of a bipolar transistor, wherein the height level of the lower portion of said low-doped collector layer is below the height level of the lower portion of said insulating layer, andwherein the height level of the upper surface of said low-doped collector layer is formed at a substantially equal level to that of the lower portion of said insulating layer and a base layer is formed in the upper surface of said low-doped collector layer by doping impurities.