Patent ID: 8816728
Filing Date: 2014-08-26
Classification: G09G,G11C,H03K

Abstract:
1. A gate driving circuit, wherein an N-th stage of the gate driving circuit comprises: a pull-up control part configured to apply a previous carry signal to a first node from a stage previous to the N-th stage in response to the previous carry signal; a pull-up part configured to output an N-th gate output signal based on a clock signal in response to a signal applied to the first node; a carry part configured to output an N-th carry signal based on the clock signal in response to the signal applied to the first node; a first pull-down part comprising a plurality of transistors connected to each other in series and configured to pull down a signal at the first node to a second off voltage; and a second pull-down part configured to pull down the N-th gate output signal to a first off voltage, wherein N is a natural number, wherein control terminals of the plurality of transistors of the first-pull-down part are connected to each other.