Patent ID: 9018085
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A method for fabricating a memory device, comprising: forming a tunnel dielectric layer over a substrate; forming a first portion of a conductive layer over the tunnel dielectric layer; forming at least one charge storage layer between the first portion of the conductive layer and the tunnel dielectric layer; forming two doped regions in the substrate beside the first portion of the conductive layer; and forming a second portion of the conductive layer serving as a word line on and electrically connected to the first portion of the conductive layer, wherein the second portion of the conductive layer covers across the two doped regions and connects to a second portion of a conductive layer of another memory device, and the second portion of the conductive layer having a thickness greater than a thickness of the first portion of the conductive layer, wherein a ratio of the thickness of the second portion of the conductive layer to the thickness of the first portion of the conductive layer ranges from 5:1 to 10:1.