Patent ID: 7100137
Filing Date: 2006-08-29
Classification: G06F,G11B

Abstract:
1. For an electronic-design-automation placer that uses a set of partitioning lines, that define a plurality of slots, to partition an integrated-circuit (“IC”) layout region into a plurality of sub-regions corresponding to said slots, wherein a plurality of line paths exist between said slots, a method of pre-computing attributes that are used for placing circuit modules in an IC layout region, the method comprising: a) for each combination of said slots, identifying at least one connection graph that represents a topology of interconnect lines necessary for connecting the combination of said slots; b) for each combination of said slots, identifying the line paths used by the at least one connection graph for that particular combination of slots, wherein a plurality of the identified line paths are diagonal; and c) storing the plurality of identified line paths for each combination of slots in a storage structure, wherein said stored line paths are used by the placer to compute costs associated with different placements of said circuit modules.