Patent ID: 8536647
Filing Date: 2013-09-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor layer of a first-conductivity-type formed on a semiconductor substrate; first and second trench gates provided in an upper surface of the semiconductor layer, the first and second trench gates extending in parallel in a first direction in plan view and being disposed to be spaced from each other in a second direction perpendicular to the first direction in plan view; a base region of a second-conductivity-type formed in an upper surface of the semiconductor layer so that the base region is sandwiched between the first and second trench gates in plan view, a depth of the base region being shallower than that of the first and second trench gates; a source region of the first-conductivity-type formed in an upper surface of the base region so that at least a part of the source region is sandwiched between the first and second trench gates in plan view, a depth of the source region being shallower than that of the base region; a plurality of base contact regions formed in the upper surface of the base region; and a plurality of column regions of the second-conductivity-type formed in the semiconductor layer, each of the plurality of column regions being formed under the corresponding base contact region, respectively, wherein a plurality of combinations, each of which comprises a corresponding one of the base contact region and the column region, are disposed between the first and second trench gates in plan view, the plurality of combinations being spaced from each other in the first direction in plan view, and the plurality of column regions are not disposed directly below the first and second trench gates.