Patent ID: 8898617
Filing Date: 2014-11-25
Classification: G05B,G06F,H01L,Y02P

Abstract:
1. A method comprising: performing a process with at least one computing system including at least one processor, the process comprising: characterizing variation in integrated circuit feature dimensions resulting from interactions between the integrated circuit feature dimensions and one or more fabrication processes; characterizing designed patterns or features on a section of one or more integrated circuit designs using one or more context environments in the one or more integrated circuit designs for the designed patterns of features; examining one or more levels of the one or more designs; determining variability of at least one of the one or more fabrication processes by using at least a relation between at least one integrated circuit feature and one or more modified versions of the at least one integrated circuit feature; evaluating the one or more designs using at least relative sensitivity of shapes to the variability of at least one of the one or more fabrication processes as shapes are defined, added, moved, and/or modified, wherein the relative sensitivity of the shapes to the variability is determined or identified based at least in part upon a result of characterizing the variation; and determining a design option from multiple design options by using at least the relative sensitivity.