Patent ID: 6433385
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A trench MOS-gated device comprising:a substrate including an upper layer, said substrate comprising doped monocrystalline semiconductor material of a first conduction type; an extended trench in said upper layer, said trench comprising two segments having differing widths relative to one another, a bottom segment of lesser width filled with a dielectric material and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, said filled upper segment of said trench forming a gate region; a doped extended zone of a second opposite conduction type extending from an upper surface into said upper layer on only one side of said extended trench; a doped well region of said second conduction type overlying a drain zone of said first conduction type in said upper layer on the opposite side of said trench, said drain zone being substantially insulated from said extended zone by said bottom segment of said trench; a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type disposed at said upper surface in said well region only on the side of said trench opposite said doped extended zone; an interlevel dielectric layer on said upper surface overlying said gate and source regions; and a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.