Patent ID: 6834011
Filing Date: 2004-12-21
Classification: G11C

Abstract:
An operating method to erase, programming and reading data on a flash memory, wherein a wordline voltage, a bitline voltage and a p-type doped well voltage are respectively applied to a control gate, a drain and a p-type doped well, all of which correspond to a selected flash memory cell; a source of the flash memory is a common source, and electrically connected via a deep n-type doped well; the drain is commonly used by the selected flash memory cell and an adjacent flash memory cell; and the p-type doped well is located between adjacent control gates corresponding to the drain, the operating method comprising:applying a high voltage to the p-type doped well, while maintaining the wordline in a ground state, and the bitline and the common source in a floating state, thereby performing an erase operation; applying a high voltage on the wordline while applying a voltage lower than the wordline voltage to the bitline voltage, and maintaining the voltage of the common source and the p-type doped well voltage in the ground state, thereby performing a programming operation; and applying a proper voltage to the wordline while applying a voltage lower than the wordline voltage to the bitline, thereby performing a read operation.