Patent ID: 6362670
Filing Date: 2002-03-26
Classification: H03L,H04J

Abstract:
A circuit for controlling the phase deviation in an output signal from a phase locked loop (PLL) that occurs when a reference signal input to the PLL is switched between a first reference signal and a second reference signal, comprising:a reference signal switch for switching between the first reference signal and the second reference signal to generate the reference signal input; a first selector for routing either the reference signal or a feedback signal to the PLL in response to a control signal, wherein the feedback signal is a frequency divided version of the PLL output signal; and a transfer function generator for generating the control signal, wherein the control signal causes the first selector to switch between the reference clock signal and the feedback signal according to a predetermined transfer function in order to modulate the gain of the PLL and thereby control the phase deviation of the PLL output signal.