Patent ID: 6111286
Filing Date: 2000-08-29
Classification: H01L

Abstract:
A flash memory cell formed on a semiconductor substrate comprising:a p-well formed in said substrate;a gate structure formed atop said p-well, said gate structure including a control gate and a floating gate, said floating gate electrically isolated from said control gate and said semiconductor substrate by a thin dielectric layer;an n- base formed adjacent to a first edge of said gate structure and extending underneath said gate structure;a p+ structure formed within said n- base and adjacent to said first edge of said gate structure; anda n+ structure adjacent a second edge of said gate structure;wherein said p+ structure is connected to a voltage source V.sub.d, said n+ structure is connected to a voltage source V.sub.s, and said control gate is connected to a voltage source V.sub.cg ;further wherein said p-well is formed within a deep n-well formed in a p-type substrate, said deep n-well biased to a voltage V.sub.cc, and said p-type substrate grounded;further wherein in order to perform the write operation: V.sub.d is biased to -V.sub.cc, V.sub.s is floating, V.sub.cg is biased to V.sub.cc.