Patent ID: 8179487
Filing Date: 2012-05-15
Classification: G02F,H01L

Abstract:
1. A pixel structure disposed on a substrate, comprising: a first data line and a second data line disposed on the substrate and substantially in parallel to a column direction; a first scan line and a second scan line disposed substantially in parallel on the substrate, and the first scan line and the second scan line being crossing and substantially perpendicular to the first data line and the second data line; a first thin film transistor electrically connected to the first scan line and the first data line; a first pixel electrode electrically connected to the first thin film transistor; a second thin film transistor electrically connected to the second scan line and the second data line, the second thin film transistor being substantially aligned to the first thin film transistor in the column direction; a second pixel electrode electrically connected to the second thin film transistor; a second extended source electrode electrically connected between the second thin film transistor and the second data line, the second extended source electrode being located adjacent to the second scan line and producing a first parasitic capacitance between the second extended source electrode and the second scan line; and a first capacitance compensating pattern electrically connected with the second data line, the first capacitance compensating pattern extending from the second data line toward the first thin film transistor, the first capacitance compensating pattern being located adjacent to the first scan line and producing a first compensation capacitance between the first capacitance compensating pattern and the first scan line for compensating the first parasitic capacitance produced by the second extended source electrode.