Patent ID: 8908449
Filing Date: 2014-12-09
Classification: G11C,H03K

Abstract:
1. A parallel master-slave flip-flop (“PMSFF”) having an input terminal for receiving a data-in signal and an output terminal for outputting a data-out signal, comprising: a master stage comprising an input terminal for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals (MCLK and MCLKB), the master stage configured to latch data at the master stage and to output the data latched at the master stage based on the first clock signals, wherein the master stage includes: a slave stage comprising an input terminal coupled to the output terminal of the master stage, an output terminal for outputting the data-out signal, and terminals for receiving second clock signals (CLK and CLKB), the slave stage configured to latch data at the slave stage and to output the data latched at the slave stage based on the second clock signals.