Patent ID: 7016222
Filing Date: 2006-03-21
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array constituted by arranging a plurality of nonvolatile memory cells in a row direction and a column direction respectively and arranging the plurality of word lines and the plurality of bit lines in the row direction and the column direction respectively in order to select a predetermined memory cell or a memory cell group out of the arranged nonvolatile memory cells; wherein; the memory cells are respectively constituted by connecting one end of a variable resistive element for storing information in accordance with a change of electrical resistances with the source of a selection transistor, in the memory cell array, the drain of the selection transistor is connected with a common bit line along the column direction, the other end of the variable resistive element is connected with a source line, and the gate of the selection transistor is connected with a common word line along the row direction, and the variable resistive element is a variable resistive element whose electrical resistance is changed due to an electrical stress.