Patent ID: 6163836
Filing Date: 2000-12-19
Classification: G06F

Abstract:
A processor comprising:a data memory for storing data;a set of instructions that are executed by said processor, said instructions including one or more user-defined addressing modes to reference data stored in said data memory;a programmable address arithmetic unit (programmable AAU) providing logic functions, said logic functions specified by data stored in an programmable AAU memory, whereby said logic functions implement said one or more user-defined addressing modes and said programmable AAU is for storing user-defined configuration data that specifies said logic functions;one or more registers, each register configured to hold an address into said data memory, said registers operatively coupled to said programmable AAU such that said programmable AAU can use one of said user-defined addressing modes to modify said address into said data memory held in each of said registers; andan instruction decoder responsive to said instructions and said one or more user-defined addressing modes, wherein output bits of said instruction decoder are coupled as inputs to said programmable AAU to control the modification of an address stored in said one or more registers.