Patent ID: 6167476
Filing Date: 2000-12-26
Classification: G06F

Abstract:
A computer system comprising:a central processing unit;a core logic connected to said central processing unit;system random access memory connected to said core logic;a first AGP bus connected to said core logic, said first AGP bus is a 32-bit bus;an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus, said AGP to AGP bridge further comprising:a first interface target and arbiter connected to said first AGP bus;a first read data return queue connected to said first interface target and arbiter;a first read and write request queue connected to said first interface target and arbiter;a first write data queue connected to said first interface target and arbiter;a second interface target and arbiter connected to a second AGP bus;a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue;a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue;a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue;a third interface target and arbiter connected to a third AGP bus;a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue;a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue;a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to said first write data queue; anda flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second write data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter;wherein said flow control logic regulates the transfer of requests, replies, and data between said first AGP bus, said second AGP bus and said third AGP bus.