Patent ID: 8599615
Filing Date: 2013-12-03
Classification: G11C

Abstract:
1. A semiconductor device comprising: a first decoder circuit including a plurality of first output nodes and producing a plurality of first decoded voltages at the first output nodes, respectively; a second decoder including a plurality of second output nodes and producing a plurality of second decoded voltages at the second output nodes, respectively; a plurality of first terminals coupled to the first output nodes to receive the first decoded voltages, respectively, the first terminals being arranged in line in a first direction; a plurality of second terminals coupled to the second output nodes to receive the second decoded voltages, respectively, the second terminals being arranged in line in the first direction; a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction; a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines; a plurality of first bit lines each arranged to intersect with the first word lines; a plurality of second bit lines each arranged to intersect with the second word lines; a plurality of first memory cell strings and a plurality of second memory cell strings, each of the first memory cell strings being coupled to an associated one of the first bit lines and including a plurality of memory cells coupled in series and connected to the first word lines, respectively, and each of the second memory cell strings being coupled to an associated one of the second bit lines and including a plurality of memory cells coupled in series and connected to the second word lines, respectively; and a first sensing unit and a memory cell array which are disposed to sandwich the first and second word lines, the first and second bit lines and the first and second memory cell strings therebetween,