Patent ID: 7238573
Filing Date: 2007-07-03
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor transistor, comprising: forming a first insulating layer on a substrate; performing an ion implantation for forming a lightly-doped drain (LDD) region in the substrate; patterning the first insulating layer; forming a trench in the substrate, the trench extending through the first insulating layer and the LDD region, and the trench extending into a portion of the substrate; forming a trench gate having sidewalls by depositing and planarizing a second insulating layer and a conductor on the substrate with the trench formed therein, the trench gate comprising the second insulating layer and the conductor, wherein the trench gate is formed after forming the LDD region; anisotropically etching the first insulating layer, except for a portion of the first insulating layer positioned on sidewalls of the trench gate, to form spacers; and forming source/drain regions by performing an ion implantation on the substrate using the spacers and the trench gate as a mask, wherein the source/drain regions are formed after forming the LDD region.