Patent ID: 6353242
Filing Date: 2002-03-05
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory having first and second select gate electrodes formed above the surface of a semiconductor substrate adjacent to each other in the column direction and extending in the row direction, and a diffused layer formed in a region of the semiconductor substrate between regions of the semiconductor substrate that are located below the first and second select gate electrodes, whereineach of the first and second select gate electrodes includes a first conductive layer and a second conductive layer located above the first conductive layer, the first conductive layer of the first select gate electrode having a plurality of first contact areas extending through the second conductive layer of the first select gate electrode, the first conductive layer of the second select gate electrode having a plurality of second contact areas extending through the second conductive layer of the second select gate electrode, the first contact areas and the second contact areas being located so that they are not opposed to each other, and portions of the second select gate electrode opposed to the first contact areas being void of the first and second conductive layers of the second select gate electrode, and portions of the first select gate electrode opposed to the second contact areas being void of the first and second conductive layers of the first select gate electrode.