Patent ID: 6777340
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A method of patterning a silicon based layer for semiconductor devices having ultra-small devices feature size by applying an etch process, comprising the steps of:providing a silicon based layer; depositing a layer of hard mask material over said silicon based layer; depositing a layer of organic Anti Reflective Coating (ARC) material over said layer of hard mask material; coating an ultra-thin layer of photoresist over the layer of organic ARC; patterning and developing the ultra-thin layer of photoresist, creating a ultra-thin photoresist mask having a pattern of openings that aligns with a pattern of openings that are to be created in the underlying silicon based layer, said patterning and developing the layer of photoresist comprising photolithography processing, E-beam lithography processing or X-ray lithography processing, thereby preventing tilting of the patterned layer of ultra-thin photoresist which is further enhanced by the ultra-thin nature of the layer of photoresist; etching the organic layer of ARC in accordance with the pattern of openings created in the layer of photoresist; etching the hard mask layer in accordance with the pattern of openings created in the layer of photoresist; removing the layers of developed ultra-thin photoresist and the etched layer of organic ARC from the hard mask layer; and etching the silicon based layer in accordance with the openings that have been etched through the layer of hard mask material, thereby creating a pattern in said silicon based layer for semiconductor devices having ultra-small devices feature size of 0.07 &mgr;m or less.