Patent ID: 7715222
Filing Date: 2010-05-11
Classification: G11C

Abstract:
1. A method of switching performance modes of a static random access memory (SRAM) circuit, the method comprising: sharing a first memory node of a first SRAM cell with a second memory node of a second SRAM cell during a first mode of operation of the SRAM circuit; sharing a third memory node of the first SRAM cell with a fourth memory node of the second SRAM cell during the first mode of operation; isolating the first memory node from the second memory node during a second mode of operation of the SRAM circuit; isolating the third memory node from the fourth memory node during the second mode of operation; and caching data stored in the memory nodes prior to switching from the first mode of operation to the second mode of operation and/or from the second mode of operation to the first mode of operation.