Patent ID: 8445949
Filing Date: 2013-05-21
Classification: H01L

Abstract:
1. A zero capacitance random access memory cell (ZRAM), comprising: a fin body with a gate dielectric on two sides of the fin body; a gate electrode adjacent two sides of the fin body and separated from the fin body by the gate dielectric; a storage dielectric formed on the gate electrode and remote from the gate dielectric; a storage electrode adjacent two sides of the gate electrode and separated from the gate electrode by the storage dielectric; insulating material in patterned regions between adjacent fin bodies; and an opening in the fin body, which extends through the storage electrode, storage dielectric, gate electrode, and gate dielectric to expose an active silicon layer of the fin body, wherein the insulating material is a low-k dielectric and the insulating material and exposed portions of the storage electrode are planar.