Patent ID: 7356810
Filing Date: 2008-04-08
Classification: G06F

Abstract:
1. A computer apparatus, comprising in combination: a first programmable processor; and an emulation system for executing a register-based program code written for a second processor on said first processor, wherein the program code refers to a set of registers of the second processor including at least one variable size register which is addressable by the program code in a plurality of different widths, the emulation system, when executed by the first processor, being operative to generate an intermediate representation of said program code by a process comprising the steps of: generating a plurality of register objects representing said registers of said second processor as referred by the program code; and generating an associated set of said register objects to represent the at least one variably sized register of said second processor by the associated set of said register objects, one of said register objects being provided for each possible width of the variably sized register as referred to by the program code; wherein said process comprises the further step of generating expression objects, each representing a different operator or operand element of the program code as that element arises in the program, each expression object being referenced by a register object to which it relates either directly, or indirectly via references from other expression objects.