Patent ID: 7026851
Filing Date: 2006-04-11
Classification: H02M,H03K,H04B

Abstract:
1. A PWM controller having frequency jitter, comprising: a modulator, for generating a first jitter current and a second jitter current; wherein said first jitter current is proportional to said second jitter current; an oscillator, for generating a pulse signal to determine a switching frequency in response to the modulation of said first jitter current; wherein said switching frequency increases whenever said first jitter current increases, and vice versa; an attenuator, connected in a voltage feedback loop, for attenuating a feedback signal to an attenuated feedback signal, wherein said attenuated feedback signal is utilized to control an on-time of a switching signal; wherein said on-time of said switching signal and an output power of a power supply are proportional to a magnitude of said feedback signal; a variable-resistance circuit comprising an output connected to said attenuator, for programming an attenuation rate of said attenuator in response to the modulation of said second jitter current; wherein said on-time of said switching signal decreases whenever said second jitter current increases, and vice versa; a first comparator, for generating a first reset signal, wherein a positive input of said first comparator is supplied with said attenuated feedback signal, and a negative input of said first comparator is supplied with a switching-current signal; a second comparator, for generating a second reset signal for over-current protection, wherein a positive input of said second comparator is supplied with a first threshold voltage, wherein a negative input of said second comparator is supplied with said switching-current signal; a first AND gate, having two inputs for receiving said first reset signal and said second reset signal; a D flip-flop, for generating a PWM signal, wherein said D flip-flop is set by said pulse signal and is reset by an output of said first AND gate; a current source, for pulling up said feedback signal; an inverter, having an input supplied with said pulse signal; and a second AND gate, for generating said switching signal, wherein a first input of said second AND gate is supplied with said PWM signal, wherein a second input of said second AND gate is connected to an output of said inverter, wherein said switching signal is utilized to control the switching of the power supply.