Patent ID: 7197101
Filing Date: 2007-03-27
Classification: H03L,H04L

Abstract:
1. An apparatus, comprising: a phase controller to generate interrelated control signals based upon a comparison of a recovered clock signal with a data signal, the phase controller having a plurality of voltage controllers each with its own charge storage circuitry to generate the interrelated control signals, respectively; a phase-frequency detector coupled with said phase controller to sample data of the data signal at a sample rate based on the recovered clock signal and to output a comparison signal based on samples of the data; phase update logic circuitry coupled with the phase-frequency detector to generate charge and discharge signals based upon the comparison signal, to act upon the charge storage circuitry of each of the voltage controllers; and a phase interpolator coupled with said phase controller to change a phase of the recovered clock signal based upon a combination of amplitude contributions from more than one phase of a reference clock signal, wherein the amplitude contributions from the more than one phase are weighted in accordance with the interrelated control signals.