Patent ID: 6028802
Filing Date: 2000-02-22
Classification: G11C

Abstract:
A dynamic random access memory (DRAM) system, comprising:a DRAM cell array having a first bit line connected to a DRAM cell, wherein said DRAM cell stores a first voltage which is less than a second voltage; anda sense amplifier portion having a second bit line and for amplifying data of said second bit line to said first voltage,wherein said sense amplifier portion connects electrically said first bit line and said second bit line, supplies a third voltage which is greater than said second voltage to said second bit line when said first bit line and said second bit line are connected electrically, and stops supplying said third voltage before a voltage of said second bit line reaches said first voltage,wherein said second voltage comprises a break-down voltage of said DRAM cell,wherein said DRAM cell array further comprises a third bit line, and said sense amplifier portion further comprises a fourth bit line, and a sense amplifier connected to said second bit line and said fourth bit line;wherein said sense amplifier portion connects electrically said third bit line and said fourth bit line, supplies said third voltage to said second bit line when said third bit line and said fourth bit line are connected electrically, and stops supplying said third voltage before a voltage of said second bit line reaches said first voltage,wherein said sense amplifier portion connects said first bit line and said second bit line, and said third bit line and said fourth bit line, when said data is stored to said DRAM cell,wherein said sense amplifier comprises:a first metal oxide semiconductor (MOS) transistor having a source-drain path between a first node and a third node, and a gate connected to a fourth node;a second MOS transistor having a source-drain path between said first node and said fourth node, and a gate connected to said third node;a third MOS transistor having a source-drain path between a second node and said third node, and a gate connected to said fourth node; anda fourth MOS transistor having a source-drain path between said second node and said fourth node, and a gate connected to said third node,wherein said second node receives said third voltage, and said first node receives a fourth voltage which is lower than said first voltage.