Patent ID: 8791558
Filing Date: 2014-07-29
Classification: H01L

Abstract:
1. A stacked semiconductor package comprising: a main substrate having an upper surface on which main connection pads are formed and a lower surface which faces away from the upper surface; at least two first semiconductor chips stacked on the upper surface and each having first bonding pads which are connected with the main connection pads; and at least one sub semiconductor chip module stacked on the first semiconductor chips, the sub semiconductor chip module having a sub substrate which has a first surface with sub connection pads formed thereon and connected with the main connection pads, and a second surface facing away from the first surface, and in which a second semiconductor chip with second bonding pads connected with the sub connection pads is embedded, and at least two third semiconductor chips which are stacked on the first surface and have third bonding pads connected with the sub connection pads.