Patent ID: 6716679
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device, comprising:forming a fuse line at a fuse portion of the integrated circuit device; forming a first insulating layer on the fuse line; forming a guard ring pattern on the first insulating layer, the guard ring pattern being formed to enclose the fuse line; forming a second insulating layer on the guard ring pattern and the first insulating layer; partially etching the second insulating layer to remove a portion of the second insulating layer in the fuse portion of the integrated circuit device enclosed by the guard ring pattern exposing a portion of the first insulating layer and to form a via hole outside the fuse portion of the integrated circuit device. forming an etch stop layer between the fuse line and the first insulating layer; and forming a fuse contact hole in the first insulating layer that partially exposes the etch stop layer and encloses the fuse line.