Patent ID: 6538916
Filing Date: 2003-03-25
Classification: G11C,H01L

Abstract:
A semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors comprising:a semiconductor layer; a source region formed in the semiconductor layer; a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a body region in a floating state; and a first gate which forms a channel in the body region; a second gate formed in addition to the first gate, a potential of the second gate being fixed so as to control a potential of the body region by a capacitive coupling; wherein the MIS transistor has a first data state in which the body region has a first potential set by impact ionization generated near a drain junction and a second data state in which the body region has a second potential set by a forward current flowing through the drain junction.