Patent ID: 6429076
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A method of forming a memory cell in a semiconductor material of a first conductivity type, the method comprising:defining a channel region in the semiconductor material, the channel region having a first side, an opposing second side, and a third side; forming a source region in the semiconductor material, the source region contacting the first side of the channel region, and being doped to have a second conductivity type; forming a drain region in the semiconductor material, the drain region contacting the second side of the channel region, and being doped to have the second conductivity type; forming a first dielectric region on the semiconductor material, the first dielectric region contacting the third side of the channel region; forming a first vertical area enhancing structure over the first dielectric region, the first vertical area enhancing structure being totally electrically isolated; forming a layer of dielectric material on the semiconductor material over the channel region; forming a floating gate over the first vertical area enhancing structure and the layer of dielectric material; forming an intergate dielectric on the floating gate; and forming a control gate on the intergate dielectric over the first vertical area enhancing structure.