Patent ID: 9158517
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a computer program residing in the memory, the computer program including a plurality of instructions; and an optimizing compiler residing in the memory and executed by the at least one processor, the optimizing compiler including a strength reduction mechanism that analyzes the computer program in a single pass, determines whether an operation in the computer program that has an unknown stride at compile-time could be improved by substituting at least one alternative instruction for at least one original instruction in the operation, and when the operation in the computer program that has an unknown stride at compile-time could be improved, substituting the at least one alternative instruction for the at least one original instruction, wherein the strength reduction mechanism analyzes the computer program in the single pass by constructing a control flow graph of the instructions in the computer program, building a dominator tree corresponding to the control flow graph that indicates which blocks in the control flow graph dominate other blocks in the control flow graph, determining an order of analyzing the instructions in the control flow graph in the single pass based on the dominator tree, constructing a candidate table of instructions in the computer program in an order determined by the dominator tree, generates at least one increment table by processing the candidate table, computes cost of each increment in the increment table, and determines whether a selected increment in the increment table is profitable based on the computed cost.