Patent ID: 7039832
Filing Date: 2006-05-02
Classification: G06F

Abstract:
1. A method of testing a processor installed within a data processing system, the method comprising: executing a first process on the processor while the processor is in a non-test mode of operation; interrupting execution of the first process; saving soft state data of the first process into a system memory at a lowest level of a volatile memory hierarchy, wherein the soft state data is from a branch history table and an address translation buffer; in response to a memory controller of the system memory receiving a kill operation specifying an address, snooping the kill operation specified address against the soft state data in the system memory; in response to the snooping resulting in a snoop hit, invalidating data associated with the kill operation specified address; executing a manufacturing level test program that tests the processor; and executing a second process on the processor in the non-test mode.