Patent ID: 9165102
Filing Date: 2015-10-20
Classification: G06F,H01L

Abstract:
1. A method of designing an integrated circuit, the method comprising: locating a routing congestion area in response to performing a first route of a plurality of standard cells corresponding to the integrated circuit on a design floorplan, wherein the routing congestion area has an amount of routing violations on the design floorplan that exceed a pre-defined threshold; inserting a multi-height routing cell on the design floorplan in response to locating the routing congestion area, wherein the multi-height routing cell comprises a bypass connection corresponding to a non-routing layer of the integrated circuit that couples a first bypass connector to a second bypass connector; connecting the multi-height routing cell to a first one and second one of the plurality of standard cells, the connecting resulting in the first standard cell coupled to the second standard cell through the multi-height routing cell and a reduction in the amount of routing violations; and generating mask layer data that incorporates the multi-height routing cell, wherein the mask layer data is configured to generate a plurality of masks for construction of the integrated circuit.