Patent ID: 6133610
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A silicon-on-insulator semiconductor chip comprising:a peripheral edge;a substrate;an oxide layer on the substrate;a silicon layer on the oxide layer;a passivation layer on the silicon layer;an active area including a gate deposited above the silicon layer, a gate metal contact deposited above and forming an electrical contact with the gate, and at least one metal contact deposited above and forming an electrical contact with the silicon layer;an isolation barrier including a groove:(a) being disposed slightly inward of the peripheral edge of the chip,(b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and(c) surrounding completely the active area of the chip; anda barrier material deposited (i) over the passivation layer on the silicon layer, and (ii) in the groove presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.