Patent ID: 6255170
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method for fabricating a memory device, comprising the steps of:forming floating gates stacked on tunnel insulating films on a plurality of prescribed regions of a semiconductor substrate;forming a plurality of control gate lines extending in a first direction to cover the floating gates, wherein a distance between adjacent control gate lines varies between first and second prescribed distances;forming sidewall spacers on both sides of the floating gates and the control gate lines;respectively forming source regions and drain regions in the semiconductor substrate on opposite sides of the floating gates and the control gate lines between the sidewall spacers;depositing a first interlayer insulating film on the semiconductor substrate;forming source contact regions that expose the source regions through the first interlayer insulating film;depositing a conductive layer on the first interlayer insulating film coupled to the source contact regions;removing portions of the conductive layer on the drain regions to form a common source;depositing a second interlayer insulating film on the semiconductor substrate;forming drain contact regions that expose the drain regions through the second interlayer insulating film; andforming bit lines extending in a direction perpendicular to the first direction coupled to the drain contact regions, wherein bit line contact regions in adjacent bit lines are offset in the second direction.