Patent ID: 9166053
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A FinFET device comprising: a substrate including a fin structure, the fin structure including a first fin and a second fin, the second fin being disposed adjacent to the first fin; a shallow trench isolation (STI) feature disposed on the substrate in a region between the first fin and the second fin; a gate structure disposed on a gate dielectric, the gate structure traversing the first fin, the second fin, and the STI feature, the gate structure having a first stepped profile at the first fin and a second stepped profile at the second fin, wherein the first stepped profile of the gate structure has a first width at a centerline of the first fin, a second width at a first distance from the centerline of the first fin, and a third width at the first distance from the centerline of the first fin, the second width being measured at a topmost portion of the gate structure and the third width being measured at a bottommost point of the gate structure, the first width being less than the third width, and the second width being less than the third width, wherein the second stepped profile of the gate structure has the first width at a centerline of the second fin; an interfacial layer, the interfacial layer being interposed between the fin structure and the gate dielectric; and gate spacers disposed along sidewalls of the gate structure, the gate dielectric being interposed between the gate spacers and the gate structure.