Patent ID: 7417890
Filing Date: 2008-08-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first SRAM cell which includes a first inverter, a second inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an input terminal of the first inverter, a first transistor having a gate connected to a first write word line, a source connected to the output terminal of the first inverter and a drain connected to a first bit line, a second transistor having a gate connected to the first write word line, a source connected to the input terminal of the first inverter and a drain connected to a second bit line, a third transistor having a gate connected to the input terminal of the first inverter and a source connected to a ground and a fourth transistor having a gate connected to a read word line and a source connected to the third transistor, and a second SRAM cell which includes a third inverter, a fourth inverter having an input terminal connected to an output terminal of the third inverter and an output terminal connected to an input terminal of the third inverter, a fifth transistor having a gate connected to a second write word line, a source connected to the output terminal of the third inverter and a drain connected to the first bit line, a sixth transistor having a gate connected to the second write word line, a source connected to the input terminal of the third inverter and a drain connected to the second bit line, a seventh transistor having a gate connected to the output terminal of the third inverter and a source connected to the ground and an eighth transistor having a source connected to the seventh transistor, wherein the fourth transistor of the first SRAM cell has a drain connected to the first bit line and the eighth transistor of the second SRAM cell has a drain connected to the second bit line.