Patent ID: 7915065
Filing Date: 2011-03-29
Classification: B81B,B81C,H01L

Abstract:
1. A manufacturing process of a wafer level sensing package, comprising: providing a wafer having a plurality of sensing chips, wherein the wafer has a wafer surface, and each sensing chip on the wafer surface further has a sensing area and a plurality of pads that do not overlap the sensing area; forming a stress release layer on the wafer surface, and patterning the stress release layer to expose the sensing area and the pads; cladding a photoresist layer on the stress release layer to shelter the sensing area and the pads; patterning the photoresist layer to expose a plurality of portions of the stress release layer, to thereby define a plurality of re-distributed pad reservation areas, and to expose the pads, each of the plurality of re-distributed pad reservation areas being connected to a corresponding one of the pads; forming a conductive metal layer on the plurality of re-distributed pad reservation areas, to thereby form a plurality of re-distributed pads each corresponding to and being connected to one of the pads, and on the photoresist layer and the pads; removing the photoresist layer, and the conductive metal layer formed thereon; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer to shelter the sensing area and the pads; patterning the re-cladding photoresist layer to form a plurality of holes in the re-cladding photoresist layer above the re-distributed pads; forming a conductive bump in each hole to electrically connect to the conductive metal layer; and removing the re-cladding photoresist layer to thereby expose the sensing area.