Patent ID: 6907443
Filing Date: 2005-06-14
Classification: G06F

Abstract:
1. An apparatus comprising: a first circuit coupled to receive a first operand and a second operand, wherein the first circuit is configured to generate a first vector in response to the first operand and the second operand, and wherein each bit of the first vector is indicative of whether or not the corresponding bits of the first operand and the second operand are equal; a second circuit coupled to receive the first vector and configured to generate an indication of a most significant bit in which the first operand and the second operand are not equal in response to the first vector; and a third circuit coupled to receive the indication from the second circuit and the first operand, wherein the third circuit is configured to generate an output indicative of whether or not the first operand is greater than the second operand responsive to the indication and the first operand.