Patent ID: 7095078
Filing Date: 2006-08-22
Classification: G11C,H01L

Abstract:
1. A charge trapping memory cell, comprising: doped regions for source and drain formed at a distance from one another in a semiconductor body; a channel region formed in the semiconductor body between the source and the drain; a storage layer sequence comprising a lower boundary layer, a storage layer and an upper boundary layer located above the channel region and at least portions of the source and the drain; and a gate electrode arranged above the storage layer sequence wherein the storage layer sequence is formed by selection of the materials and the thicknesses of the lower boundary layer, of the storage layer and of the upper boundary layer such that a programming of the memory cell occurs by trapping of hot charge electron carriers from the channel region in the storage layer and an erasure of the memory cell occurs by removal of charge electron carriers from the storage layer by applying a positive potential to the gate electrode to pull the charge electron carriers into the gate electrode.