Patent ID: 6046942
Filing Date: 2000-04-04
Classification: G11C,H03K

Abstract:
A semiconductor device, including a pair of memory cells in combination with a shared output stage, comprising:a first memory cell that provides a first bit of information at a read data line and a complement of the first bit at an inverted information bit node in response to a first read address signal having a first logical value, wherein the first memory cell comprises:first and second cross-coupled inverters coupled at a first node and a second node for storing a bit of information at the first node and a complement of the bit at the second node;first and second series-connected switching elements for coupling a write data signal to the first node in response to a write address signal and a clock; andthird, fourth and fifth series-connected switching elements for coupling the second node to a power supply terminal in response to the write data signal, the write address signal and the clock;a second memory cell that provides a second bit of information at the read data line and a complement of the second bit at the inverted information bit node in response to a second read address signal having the first logical value; anda shared output stage that includes first and second cross-coupled transistors,wherein the first transistor includes a control terminal coupled to the inverted information bit node, an output terminal coupled to the read data line, and another output terminal coupled to a power supply terminal, and the second transistor includes a control terminal coupled to the read data line, an output terminal coupled to the inverted information bit node, and another output terminal coupled to the power supply terminal,at least one memory cell of the first and second memory cells including a cross-coupled inverter driven by circuitry external to the cross-coupled inverter.