Patent ID: 6765832
Filing Date: 2004-07-20
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in rows and columns and a plurality of spare memory cells arranged so as to form first and second spare rows in respective regions adjacent to said plurality of memory cells; a plurality of word lines provided correspondingly to respective rows of said plurality of memory cells; first and second spare word lines provided correspondingly to said first and second spare rows, respectively; a plurality of word line drivers provided correspondingly to said respective plurality of word lines to each control a voltage on a corresponding one of said plurality of word lines; and first and second spare word line drivers provided correspondingly to said first and second spare word lines, respectively, to control voltages on said first and second spare word lines, wherein said plurality of word line drivers and said first and second spare word line drivers are sequentially disposed in accordance with arrangement of said plurality of word lines and said first and second spare word lines in said memory cell array, each of said plurality of word line drivers and said first and second spare word line drivers includes: an output node; a drive circuit driving a corresponding one of said plurality of word lines and said first and second spare word lines into one of a selected state and a non-selected state according to a voltage at said output node; and a precharge switch precharging said output node to a first voltage prior to a row select operation and, also, disconnecting said output node from said first voltage in said row select operation, each of said plurality of word line drivers further includes: a decode unit connecting a first internal node to a second voltage in said row select operation according to a result of row selection; a control switch provided between a second internal node and said first internal node to connect both to each other in said row select operation and, also, disconnect both from each other prior to said row select operation; a first shift switch connected between one output node adjacent to said output node of a corresponding one of said plurality of word line drivers on a first side along a direction of arrangement of said plurality of word line drivers and said first and second spare word line drivers, and said second internal node of said corresponding one of said plurality of word line drivers; a second shift switch connected between said output node of said corresponding one of said plurality of word line drivers, and said second internal node of said corresponding one of said plurality of word line drivers; and a third shift switch connected between one output node adjacent to said output node of said corresponding one of said plurality of word line drivers on a second side opposite to said first side, and said second internal node of said corresponding one of said plurality of word line drivers, and said semiconductor memory device further comprises a shift control circuit controlling turning-on and -off of said first to third shift switches in each of said plurality of word line drivers in said row selection operation on the basis of an address of a defective memory cell row.