Patent ID: 7005700
Filing Date: 2006-02-28
Classification: B82Y,H01L

Abstract:
1. A double-gate flash memory device, comprising: a bulk silicon substrate; a wall-shape single crystal silicon Fin active region which is vertically formed from a portion of said bulk silicon and is connected to said bulk silicon substrate; a second oxide film which is formed on said bulk silicon substrate and is formed to a certain height of said Fin active region; a tunneling oxide film on said second oxide film which is formed on the both side walls of the Fin active region; a first oxide film which is formed on the upper surface of said Fin active region with nearly same or a thicker thickness value than that of the tunneling oxide film; a storage electrode which is formed on the tunneling oxide, the first and second oxide films in order to store electric charges; an inter-gates oxide film which is formed on said storage electrode; a control electrode which is formed on said inter-gates oxide film; a source/drain which is formed on the both sides of the Fin active region excluding the Fin active region which overlaps with said control electrode; and contact regions and metal layers which are formed at the contact areas of said source, drain, and control electrode.