Patent ID: 7006505
Filing Date: 2006-02-28
Classification: H04L

Abstract:
1. A method to optimally access a memory unit where the memory unit is logically partitioned to form a plurality of memory channels, the plurality of memory channels are further logically partitioned to form a plurality of memory lines, each of the plurality of memory lines includes a plurality of buffers and each of the plurality of buffers corresponds to a separate one of the plurality of memory channels, comprising: determining at least one load value of each of the plurality of memory channels; and based on the determined at least one load value, selecting a particular one of the plurality of memory channels; wherein the step of determining the at least one load value of each of the plurality of memory channels includes determining, for each of the plurality of memory channels, the number of pending read requests; wherein the step of selecting the particular one of the plurality of memory channels includes selecting the particular one of the plurality of memory channels that has a lowest number of pending read requests.