Patent ID: 6532514
Filing Date: 2003-03-11
Classification: G11C

Abstract:
A system for handling a power supply interruption in a non-volatile memory, comprising:a status indicator set for each sector of a non-volatile memory array, the status indicator set operable to indicate a status for the sector and independently erasable from the sector; the status indicator set comprising alternating active indicator and erasable indicator sub-sets, the indicator sub-sets independently erasable from each other, each indicator sub-set comprising a first and second indicators, the state machine operable to mark a first indicator of the active indicator sub-set for a sector prior to performing an operation on the sector to indicate an interruption status, to erase the erasable indicator sub-set, and to mark the second indicator of the active indicator sub-set for the sector after completing the operation to indicate a completed status, the state machine further operable to perform operations on sectors and operable to adjust the status indicator set for a sector prior to performing an operation on the sector to indicate an interruption status and to adjust the status indicator set for the sector after completing the operation to indicate a completed status.