Patent ID: 6635937
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A semiconductor integrated circuit device having a memory cell including a pair of n channel type MISFETs having gate electrodes and drains respectively cross-connected with each other, comprising:an interlayer insulating film formed over the pair of n channel type MISFETs; a pair of conductive layers formed such that one of the pair of the conductive layers electrically connects a gate electrode of one of the pair of n channel type MISFETs and the drain of another of the pair of n channel type MISFETs and such that another one of the pair of the conductive layers electrically connects a gate electrode of another one of the pair of n channel type MISFETs and the drain of one of the pair of n channel type MISFETs; a capacitive insulating film formed on the pair of conductive layers and including an opening provided on one of the pair of conductive layers; and an upper electrode formed on the capacitive insulating film and the opening, wherein the interlayer insulating film includes a first insulating film formed on the pair of n channel type MISFETs and a second insulating film formed on the first insulating film, wherein contact holes are formed in the first insulating film, and wiring trenches are formed in the second insulating film, and wherein said conductive layers respectively include connecting portions embedded in the contact holes and local wirings embedded in the wiring trenches.