Patent ID: 7295938
Filing Date: 2007-11-13
Classification: G01R,G06F

Abstract:
1. A clock jitter calculation device for calculating a magnitude of jitter of a clock signal based on information representing a circuit configuration, comprising: a supply voltage analysis section for calculating a variation over a predetermined period of time in a supply voltage of a power source supplied to each cell along a transmission path of the clock signal; a delay time variation calculation section for calculating a variation in delay time of each cell according to the supply voltage variation; and a jitter calculation section for calculating the magnitude of jitter of the clock signal transmitted via the transmission path based on the delay time variation, wherein said clock jitter calculation device outputs said calculated magnitude of jitter of the clock signal, and wherein the supply voltage analysis section obtains an amount of voltage drop caused by a current flowing through each cell and calculates the supply voltage, which is lower than a predetermined reference supply voltage by the voltage drop amount.