Patent ID: 6188699
Filing Date: 2001-02-13
Classification: H04L

Abstract:
A multi-channel network device for interfacing between a plurality of physical data links and a control processor, said physical data links characterized by respective corresponding data streams of data packets communicated according to a data link control protocol, said multi-channel network device comprising:(a) a plurality of channels;(b) a plurality of receive-side line interfaces, each receive-side line interface corresponding to ones of said channels and operative to: (i) receive incoming data packets arriving from one of said physical data links such that each incoming data packet is received as one or more incoming data segments; and (ii) determine a time-slot number for each incoming data segment arriving on the respective receive-side line interface;(c) a receive-side priority encoder circuit coupled to said receive-side line interfaces and operative to monitor said receive-side line interfaces and to process the incoming data segments arriving thereon according to a predetermined order of service;(d) a receive-side channel assigner circuit coupled to said receive-side priority encoder circuit and operative to: (i) assign each incoming data segment processed by said receive-side priority encoder circuit to one of said channels; and (ii) transmit said incoming data segments downstream in a pipeline;(e) a receive-side time-slice data processor coupled to said receive-side channel assigner circuit and operative to: (i) receive said incoming data segments from said receive-side channel assigner circuit; and (ii) decode said incoming data segments;(f) a receive-side packet buffer processor coupled to said receive-side time-slice data processor and having a plurality of receive-side channel first-in first-out FIFO buffers, each receive-side channel FIFO buffer corresponding to one of said channels, said receive-side packet buffer processor operative to: (i) receive said incoming data segments from said receive-side time-slice data processor; and (ii) buffer said incoming data segments into corresponding ones of said receive-side channel FIFO buffers;(g) a control processor interface; and(h) a receive-side packet management circuit coupled to said packet buffer processor and said control processor interface, said receive-side packet management circuit operative to: (i) maintain a plurality of receive-side data packet descriptors, each receive-side data packet descriptor referencing a first memory block where one of said incoming data segments can be stored; (ii) transfer said incoming data segments stored in said receive-side channel FIFO buffers to the control processor via said control processor interface; and (iii) manage the transfer of incoming data seaments using said receive-side data packet descriptors.