Patent ID: 8819328
Filing Date: 2014-08-26
Classification: G06F,Y02D

Abstract:
1. A controller comprising: a first interface through which to communicate with a host; a second interface through which to communicate with a plurality of flash memory devices, wherein at least one of the flash memory devices comprises a three-dimensional memory, wherein the three-dimensional memory comprises a plurality of layers of memory cells stacked vertically above one another; a memory configured to store a plurality of background commands, wherein the background commands are for operations to be performed in one or more of the plurality of flash memory devices; a processor in communication with the first and second interfaces and the memory, wherein the processor is operative to: an error correction code module configured to correct errors in portions of a page of data as the portions are read from the plurality of flash memory devices instead of waiting for the entire page of data to be read from the plurality of flash memory devices before correcting the errors; wherein a foreground command has a predetermined completion time, whereas a background command does not; wherein at least one of the first and second interfaces comprises a NAND interface configured to transfer data using a NAND interface protocol; and wherein the foreground command or the background command is a command to program a page of data to a block of memory in the plurality of flash memory devices, and wherein in response to a failure in programming the page of data to the block of memory in the plurality of flash memory devices, the processor is further configured to copy that page and preceding pages in the block to a replacement block in the plurality of flash memory devices.