Patent ID: 6014053
Filing Date: 2000-01-11
Classification: G05F,H03F

Abstract:
An apparatus for avoiding latch-up in a PMOS transistor having a source, an N-well, and a parasitic diode formed between the source and the N-well, comprising:an amplifier, coupled to receive a first voltage and a second voltage, for generating an amplified first voltage and an amplified second voltage;a comparator coupled to the amplifier, for comparing the amplified first voltage to the amplified second voltage, and generating a control signal indicating at least one of (i) whether the amplified first voltage exceeds the amplified second voltage by a first predetermined amplified tolerance and (ii) whether the amplified second voltage exceeds the amplified first voltage by a second predetermined amplified tolerance;a switch coupled to the comparator and coupled to receive the first and second voltages, for coupling the greater of the first and second voltages to the N-well in response to the control signal, whereby the parasitic diode is reversed biased.