Patent ID: 6933195
Filing Date: 2005-08-23
Classification: H01L

Abstract:
1. A method of fabricating a flash memory device having a cell array region and a peripheral circuit region, the method comprising: forming a device isolation layer at a predetermined region of a semiconductor substrate to define at least one first active region in the cell array region and a second active region in the peripheral circuit region; forming a floating gate pattern covering the first active region and a gate conductive layer covering the peripheral circuit region; forming a tunnel oxide layer having a first thickness, the tunnel oxide layer interposed between the floating gate pattern and the first active region; forming a gate oxide layer having a second thickness, the gate oxide layer interposed between the gate conductive layer and the second active region, the second thickness different from the first thickness; prior to formation of the tunnel oxide layer and the gate oxide layer, implanting impurity ions into the first and second active regions to adjust a threshold voltage of a MOS transistor; prior to formation of the tunnel oxide layer and the gate oxide layer, implanting impurity ions into the first and second active regions to form a well; sequentially forming an inter-gate dielectric layer and a control gate conductive layer on an entire surface of the substrate having the floating gate pattern and the gate conductive layer; and selectively removing the control gate conductive layer and the inter-gate dielectric layer which are located in the peripheral circuit region, thereby exposing the gate conductive layer in the peripheral circuit region.