Patent ID: 6614068
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A silicon-on-insulator (SOI) device, comprising:a semiconductor layer having a constant thickness and including a cell region and a peripheral region, the semiconductor layer also including a gate surface and another surface parallel to the gate surface; an isolation film of a trench type formed in the gate surface of the semiconductor layer, the isolation film having a lower surface at a level between the gate surface and the another surface parallel to the gate surface of the semiconductor layer, the isolation film defining a first device formation region in the cell region and a second device formation region in the peripheral region; a first gate and a second gate formed over the semiconductor layer in the first and second device formation regions, respectively; a first source region and a first drain region formed in the first device formation region, and a second source region and a second drain region formed in the second device formation region; a first insulating layer formed over the first and the second gates; a capacitor formed over the first insulating layer, the capacitor having contact with the first source region; a second insulating layer formed over the first insulating layer to cover the capacitor; a supporting substrate bonded on the second insulating layer; a first impurity region formed in the another surface of the semiconductor layer over the first drain region, the first impurity region having contact with the first drain region; a second and a third impurity region formed in the another surface of the semiconductor layer over the second source region and the second drain region; a third insulating layer formed on the another surface of the semiconductor layer; a first contact hole formed in the third insulating layer to expose the first impurity region; a bit line formed over the third insulating layer to be contacted with the first impurity region through the first contact hole; a fourth insulating layer formed over the third insulating layer to cover the bit line; a second hole and a third contact hole formed in the third and the fourth insulating layers to respectively expose the second and the third impurity regions; and a first metal interconnection and a second metal interconnection formed over the fourth insulating layer to be connected with the second and the third impurity regions through the second and the third contact holes, respectively.