Patent ID: 6769084
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A semiconductor device for testing a memory having N locations, the device comprising:a linear feedback shift register (LFSR) for creating unilateral pseudo-random (log2N)-bit address patterns, the address patterns being used as addresses of memory locations to be tested; a data generator for generating data patterns based on the address patterns generated by the LFSR, said data patterns are grouped into (log2N)+1 Address Data Background (ADB) groups, each of the ADB groups having N locations, said data patterns for use as data input to the memory for testing; a comparator for comparing the data input to the memory against the data output from the memory for data integrity verification; and a built-in self test (BIST) controller, operatively connected to the LFSR, data generator, and comparator, for controlling testing of the memory.