Patent ID: 7317644
Filing Date: 2008-01-08
Classification: G11C

Abstract:
1. An integrated circuit comprising: a signal selection circuit having at least two data inputs, the signal selection circuit having an output selectively coupled to one of the at least two data inputs in response to a data select input; a first delay circuit having an output coupled to a first input of the at least two data inputs of the signal selection circuit, wherein a first duration of the first delay circuit is related to a numerical value stored in a first memory device connected to the first delay circuit; and a second delay circuit having an output coupled to the data select input of the signal selection circuit, wherein a second duration of the second delay circuit is related to a numerical value stored in a second memory device connected to the second delay circuit, wherein a rising edge in an output signal of the first delay circuit occurs after a corresponding rising edge in an output signal of the second delay circuit.