Patent ID: 8886960
Filing Date: 2014-11-11
Classification: G06F,H04L

Abstract:
1. A microprocessor, comprising: an architected register, having a bit, wherein the microprocessor is configured to set the bit; and a fetch unit, configured to fetch encrypted instructions from an instruction cache and decrypt them prior to executing them, in response to the microprocessor setting the bit; wherein the microprocessor is configured to save the value of the bit to a stack in memory and then clear the bit, in response to receiving an interrupt; wherein the fetch unit is configured to fetch unencrypted instructions from the instruction cache and execute them without decrypting them, after the microprocessor clears the bit; wherein the microprocessor is configured to restore the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction; and wherein the fetch unit is configured to resume fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set; and wherein the architected register further has index bits that specify a location of storage space in the microprocessor for holding decryption keys used by the fetch unit to decrypt the encrypted instructions.