Patent ID: 6256617
Filing Date: 2001-07-03
Classification: G06N,Y10S

Abstract:
A processor operating in a fuzzy logic mode comprising: a fuzzyfication unit for receiving a plurality of input variables on an input and for computing a membership value of such variables in a membership function; a processing unit connected downstream to the fuzzyfication unit for producing a fuzzy set; a defuzzyfication unit for translating inference results into a crisp value; a first memory device connected to the fuzzyfication unit for storing a set of membership functions, wherein a sum of the membership functions through a universe of discourse is unity and at any point of the universe of discourse, there are only two membership functions with a non-zero degree of membership; a second memory device connected to the defuzzyfication unit and containing a set of crisp values which appear in a THEN part of a fuzzy rule; and a further memory device connected to the defuzzyfication unit.