Patent ID: 7538995
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A semiconductor IC device in which an electrostatic protective circuit is connected to an internal circuit connected between two pads including a power-supply pad and a signal input/output pad, the internal circuit comprising a matching circuit for adjusting the impedance between the two pads, said matching circuit comprising: n (n is a positive number of 2 or more) resistance elements connected in parallel between the two pads, the resistance of each of the resistance elements being set to a larger value than a required impedance between the two pads; n×m (m is a positive number of 2 or more) transistors, wherein the m transistors in each set of m transistors are connected in parallel to each other, and wherein each said set of m transistors is connected in series to a respective one of the n resistance elements; and an adjustor for selectively allowing the transistors to perform an ON-operation, wherein the transistors comprise MOS transistors and the sources and drains thereof are connected in series to the resistance elements, respectively, wherein the n×m MOS transistors are laid out in the same diffusion-layer region, and wherein each of the m MOS transistors has a same gate width and the gate width satisfies the equations: where Wx is a total gate width of the MOS transistors performing a bipolar operation together when a surge current is applied, W N is the number of MOS transistors performing a bipolar operation (1≦N≦m), Idg is a value of breakdown current for the gate width of each MOS transistor, Rt is an electrical resistance of MOS transistor (total resistance in a path from a source pad to a drain pad of the MOS transistor), Vsp is a snapback voltage in the MOS transistor performing a bipolar operation, and Vesd is a maximum voltage required by an electrostatic protective circuit for dissipating a surge current.