Patent ID: 6420195
Filing Date: 2002-07-16
Classification: G01R,H05K,Y02P

Abstract:
A method of aligning a semiconductor chip package in an alignment position with respect to an alignment fixture, the method comprising:providing a semiconductor chip having an active device and being encapsulated in a compound, said compound having a surface thereon having a first region, said first region defining a first volume that is offset from said surface on said compound, said first volume defining a chip plane; providing an alignment fixture having a second region, said second region defining a second volume that is offset from an alignment surface on said alignment fixture, said second volume defining an alignment plane; and moving said second region into contact with said first region such that said chip plane and said alignment plane are parallel, whereby the semiconductor chip is thereby held in contact engagement with the alignment fixture, and an interface is formed by at least one of: a concave surface in the compound encapsulating said semiconductor chip and a convex surface of said alignment fixture; and a convex surface in the compound encapsulating said semiconductor chip and a concave surface of said alignment fixture.