Patent ID: 6308298
Filing Date: 2001-10-23
Classification: G11B

Abstract:
A clock synchronization reacquisition apparatus for a non-tracking storage device comprising a read channel which generates a read signal based on detection of data from a storage medium in said non-tracking storage device and which reconstructs data packets from said read signal, comprising:a read quality detector which monitors a packet error status associated with each of a respective one of a predetermined number of a plurality of packets reconstructed from said read signal, said packet error status indicative of whether or not an error was detected in said reconstructed packet associated with said packet error status, said read quality detector generating a read quality signal indicative of the quality of said read signal based on the number of said plurality of packets in which an error was detected;a phase locked loop (PLL) which receives an input signal and generates a clock synchronization signal that is locked to said input signal; anda switch which receives said read signal and a reference frequency signal and outputs one or the other of said read signal or said reference frequency signal as said input signal of said PLL in response to said read quality signal.