Patent ID: 6134610
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A buffer room logic for buffering data transferred between a host and a data storage device with a data write verification capability so as to store data on a predetermined recording medium, comprising:first and second buffer counters for counting pulses generated at the end of a data transfer from a host interface and at the end of a data write;first comparator means for comparing the value of the first buffer counter with the value of a maximum buffer counter indicating a maximum size of a buffer memory, and for outputting a pulse to the host interface so as to stop data transfer from the host when the comparison results in a host-no-room condition;second comparator means for comparing the value of the second buffer counter with the value of the maximum buffer counter, and for outputting a pulse to a recording medium interface so as to stop transfer of data read from the recording medium when the comparison results in a disk-no-room condition;first and second switches connected between the first buffer counter and the recording medium interface, and between the second buffer counter and the recording medium interface, respectively, said first and second switches being switched on and off by a predetermined control signal; andcontroller means for generating the predetermined control signal for switching on and off the first and second switches, respectively;wherein said controller means switches on the second switch and switches off the first switch in response to a data write command from the host, whereby the second counter counts in response to each data write to the predetermined recording medium; andwherein said controller means switches on the first switch and switches off the second switch in response to each recording of data in at least one sector of the predetermined recording medium.