Patent ID: 6798700
Filing Date: 2004-09-28
Classification: G11C

Abstract:
A method of writing data to a memory device comprising a plurality of memory cells, wherein each memory cell comprises a latch circuit having first and second complementary latch outputs and first and second write circuits respectively coupled to said first and second latch outputs, the method comprising:selecting a memory cell to which data is to be written; activating a write word line coupled to the first and second write circuits of the selected memory cell to which data is to be written; applying complementary write values to complementary write bit lines of a write bit line pair coupled with the first and second write circuits of the selected memory cell; and responsive to activating the write word line coupled to the first and second write circuits of the selected memory cell to which data is to be written, coupling the first and second latch outputs of the selected memory cell with the complementary write bit lines of the write bit line pair coupled therewith to write the complementary write values to the first and second latch outputs of the selected memory cell, wherein the memory device comprises a plurality of complementary write bit line pairs with bit lines of each pair respectively coupled with first and second write circuits of pluralities of memory cells wherein bit lines of bit line pairs not coupled with the selected memory cell are set at a same value.