Patent ID: 6815338
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of producing a multilayer wiring structure of a semiconductor device, comprising:a step of forming a first opening in a first insulating layer formed on a substrate and forming a lower plug in said first opening; a step of forming a wiring on said first insulating layer and said lower plug; and a step of forming a second insulating layer on said wiring, and forming, in said second insulating layer and said wiring, a second opening opposite to said first opening and with a depth of about &frac13; or more of the thickness of said wiring, and forming an upper plug in said second opening, at said lower plug forming step, a CMP or etching-back method being used such that the distance between top surface of said lower plug and top surface of said first insulating layer, is about &frac13; or less of the diameter of each of said upper and lower plugs.