Patent ID: 6628653
Filing Date: 2003-09-30
Classification: H04L

Abstract:
A method of reconfiguring a packet processor, the packet processor comprising:a programmable hardware discriminator for receiving incoming packets, and selecting bits from any part of the incoming packets; a decision table containing information relating to how the packets are to be processed; and programmable hardware searching logic coupled to the decision table and to the discriminator for accessing the information in the table according to the selected bits, the method comprising the steps of: determining a column structure for the decision table; determining which bits to select from each packet; determining a correspondence between the selected bits and the columns of the table; determining which bits are to be used in the search; deriving a new configuration for the discriminator on the basis of the determination of which bits to select; deriving a new configuration for the searching logic on the basis of the column structure, which bits are to be used in the search, and the correspondence; and loading the new configurations into the searching logic, and the discriminator respectively.