Patent ID: 7550372
Filing Date: 2009-06-23
Classification: H01L

Abstract:
1. A method of fabricating conductive lines, comprising: providing a substrate having a polysilicon layer thereon; forming a mask layer on the polysilicon layer, wherein the mask layer has an opening that exposes a portion of the polysilicon layer; forming spacers on the sidewalls of the opening and above the polysilicon layer; removing a portion of the polysilicon layer using the spacers and the mask layer as a mask; forming an insulating layer over the substrate to fill the opening, wherein the insulating layer has an etching selectivity different from the mask layer; removing the mask layer, and the spacers not being removed so as to expose a portion of the polysilicon layer not covered by the spacers; and forming a silicide layer on the exposed portion of the polysilicon layer.