Patent ID: 7308372
Filing Date: 2007-12-11
Classification: G01R

Abstract:
1. An apparatus, comprising: a phase detector array including a plurality of array delay elements, the phase detector array configured to generate a first feedback signal and a second feedback signal; a clock generator to generate a clock signal with a clock edge; an adjustable delay line coupled to the clock generator and to the phase detector, and configured to generate a reference signal with a reference edge in response to the clock signal, the adjustable delay line adjustable to a first delay time, based at least in part on the first feedback signal, to align the clock and reference edges on one side of an array delay element, and further adjustable to a second delay time, based at least in part on the second feedback signal, to align the clock and reference edges on another side of the array delay element, a difference between the first and the second delay times being substantially equal to an array delay time of the array delay element.