Patent ID: 7471159
Filing Date: 2008-12-30
Classification: H03L,Y10S

Abstract:
1. A phase-locked loop comprising: a basic phase-locked loop circuit comprising a voltage-controlled oscillator (VCO), the basic phase-locked loop circuit generating an output clock signal which is phase-locked with an input clock signal using the VCO which oscillates in response to an oscillation control signal and changes an oscillation frequency band depending on a frequency band selection digital value; and a frequency band controller which generates the frequency band selection digital value in response to the input clock signal and the oscillation control signal, wherein the frequency band controller comprises: a comparator which compares the oscillation control signal with a first reference voltage to generate an up-count signal, and compares the oscillation control signal with a second reference voltage to generate a down-count signal; a stabilization controller which generates an enable signal to update an operating frequency region of the VCO in response to the input clock signal and the oscillation control signal; and a counter which receives the up-count signal and the down-count signal from the comparator, selectively outputs the up-count signal in response to the enable signal so as to increment the frequency band selection digital value, and selectively outputs the down-count signal in response to the enable signal so as to decrement the frequency band selection digital value.