Patent ID: 7315477
Filing Date: 2008-01-01
Classification: G11C

Abstract:
1. A flash memory system, comprising: a set of flash memory elements arranged in columns and rows using a set of bit lines and word lines, each flash memory element in a common column is connected to a common bit line, each flash memory element in a common row is connected to a common word line; one or more write control circuits in communication with said set of flash memory elements, said one or more write control circuits simultaneously program flash memory elements connected to a particular word line on all of said set of bit lines; and read circuits in communication with said bit lines to determine a quantity related to one of two or more adjacent flash memory elements along respective bit lines, said read circuits determine an offset for each flash memory element connected to said particular word line from a predetermined set of offsets based on a charge level stored in an adjacent flash memory element, said read circuits perform a set of read processes for said flash memory element connected to said particular word line, each read process uses a different one of said predetermined set of offsets, each of at least a subset of said flash memory elements connected to said particular word line provides final data from an appropriate one of said read processes associated with the offset determined for the respective flash memory element.