Patent ID: 6667915
Filing Date: 2003-12-23
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory cells; a plurality of redundancy circuits, each of which is used to relieve a defective memory cell that occurred in said plurality of memory cells; and a redundancy control circuit to selectively activate one of said plurality of redundancy circuits when said defective memory cell is designated as an accessing object, said redundancy control circuit including a first redundancy decoder arranged corresponding to one of said plurality of redundancy circuits, and activating the corresponding one redundancy circuit when a defective address stored inside is designated as said accessing object, and a second redundancy decoder arranged corresponding to another one of said plurality of redundancy circuits, and activating the corresponding another one redundancy circuit when a defective address stored inside is designated as said accessing object, except for a case where the defective address stored in said first redundancy decoder is designated as said accessing object, wherein when the defective address stored in said first redundancy decoder is designated as said accessing object, said second redundancy decoder inactivates said corresponding another one redundancy circuit, irrespective of whether or not the defective address stored said inside is designated as said accessing object.