Patent ID: 6211050
Filing Date: 2001-04-03
Classification: G02F,H01L

Abstract:
A method for making an integrated circuit using a patterned fill layer in kerf areas for more uniformly level process layers comprising the steps of:providing a semiconductor substrate having an array of die areas for semiconductor devices, said array of die areas separated by said kerf areas;(a) depositing a conducting layer on said substrate;(b) patterning said conducting layer to form portions of said semiconductor devices in said die areas, and concurrently patterning said conducting layer in said kerf areas to form said patterned fill layer;(c) depositing a spin-on-glass layer on said patterned conducting layer, wherein said patterned fill layer in said kerf areas provides a uniform coating over corners of said array of die areas without buildup of said spin-on-glass;(d) curing said spin-on-glass layer;(e) chemical-mechanical polishing back said spin-on-glass layer, wherein said fill layer prevents dishing in said kerf areas;(f) depositing an insulating layer on said spin-on-glass layer;(g) repeating steps (a) through (f) for each additional patterned conducting layer required to complete said integrated circuit.