Patent ID: 7161842
Filing Date: 2007-01-09
Classification: G11C

Abstract:
1. A flash memory device, comprising: a plurality of cell blocks including a plurality of cell strings to which a plurality of memory cells are serially connected, wherein each of the cell strings is allocated with one bit line, and memory cells which share one word line among the plurality of the memory cells constitute a page; a block select circuit for selecting one of the cell blocks according to a block address; a predecoder including a word line decoder for selectively outputting a plurality of select signals according to a page address, and a plurality of word line switches each for receiving a page erase signal and each of the select signals and applying a predetermined bias depending on the erase of the cell block unit or the page unit through each of a plurality of global word lines; and a switching unit for applying a predetermined bias to the word lines of the cell block through the global word lines according to the output signal of the block select circuit, wherein each of the word line switches comprises: