Patent ID: 6141278
Filing Date: 2000-10-31
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns;mode detecting means coupled to receive an operation mode designating signal and responsive thereto for detecting that said operation mode designation signal designate a predetermined particular operation mode to generate a mode detection signal indicative of the result of detection;clock generation means coupled to receive said mode detection signal, for continuously and repetitively generating a clock signal having a predetermined period when activated in response to said mode detection signal being active to indicate that said predetermined particular operation mode is designated;internal address generating means coupled to receive said clock signal and responsive thereto for generating an internal address signal independent of an externally applied address signal at each application of said clock signal; androw selection means coupled to receive said clock signal and said internal address signal and activated in synchronization with said clock signal for selecting a row of memory cells in said memory array in accordance with said internal address signal.