Patent ID: 7370292
Filing Date: 2008-05-06
Classification: G06F

Abstract:
1. A method of incrementally reducing a circuit design in a data processing system, said method comprising: receiving a circuit design and a property for logical verification with respect to said circuit design; selecting one or more of a plurality of diverse re-encoding or approximation techniques for reducing said circuit design; reducing said circuit design to create a reduced circuit design by re-encoding a portion of said circuit design by replacing the fan-in side of a cut with equivalent logic of reduced size and overapproximating said circuit design by injecting cutpoints in parallel; attempting to generate a valid solution for said property on said reduced circuit design; and determining whether said valid solution is generated, wherein said valid solution is a valid result of combinational logic irrespective of any physical layout of said circuit design; replacing said circuit design with said reduced circuit design; until said valid solution is generated, performing said selecting, reducing, determining and replacing steps; and in response to generating said valid solution, outputting said valid solution from said data processing system.