Patent ID: 6770516
Filing Date: 2004-08-03
Classification: H01L,Y10S

Abstract:
A method of forming a complimentary metal oxide semiconductor (CMOS), device in a silicon on insulator (SOI), layer, comprising the steps of:forming said SOI layer on a semiconductor substrate; forming an insulator layer on said SOI layer; defining a first fin type structure in said insulator layer and in said SOI layer, and forming a second fin type structure in said insulator layer and in said SOI layer; growing a gate insulator layer on sides of said first fin type structure and on the sides of said second fin type structure; forming a gate structure traversing, and normal in direction to, fin type structures; forming an insulator spacer on sides of portions of said fin type structures not covered by said gate structure, and on sides of said gate structure; forming a first doped insulator layer overlying a first SOI shape, and forming a second doped insulator layer overlying a second SOI shape; performing an anneal procedure to create a first source/drain region of a first conductivity type in said first SOI shape, and to create a second source/drain region of a second conductivity shape in said second SOI shape; removing said first doped insulator layer and said second doped insulator layer; and forming metal shapes on said first source/drain region and on said second source/drain region, resulting in said CMOS device comprised of a first metal oxide semiconductor (MOS), device of a first channel type, featuring said first source/drain region, and comprised of a second MOS device of a second channel type, featuring said second source/drain region.