Patent ID: 6794745
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A LOC type semiconductor package, comprising:a semiconductor chip having a chip periphery and a plurality of bonding pads, the bonding pads being arranged within the chip periphery; a plurality of general leads, the general leads having inner and outer portions, the inner portions being spaced from and not crossing the chip periphery; a first plurality of wires extending between corresponding bond pads and inner portions of the general leads, thereby extending across the chip periphery; as many as four stable leads, the stable leads having inner and outer portions, the inner portions extending over the chip periphery and arranged in a generally planar relationship with the inner portions of the general leads; an adhesive composition arranged between the semiconductor chip and an attachment section of the inner portion of each stable lead; a second plurality of wires within the chip periphery extending between corresponding bond pads and inner portions of the stable leads; and a molding resin encapsulating the semiconductor chip, the inner portions of the general leads, the inner portions of the stable leads, the adhesive composition, the first plurality of wires and the second plurality of wires.