Patent ID: 7193309
Filing Date: 2007-03-20
Classification: H01L

Abstract:
1. A semiconductor package with stacked chips, comprising: a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface and a non-active surface, the non-active surface being attached to the plurality of supporting extensions of the lead frame, wherein the preformed package further comprises at least a first chip and a substrate; at least a second chip mounted on the active surface of the preformed package, wherein the active surface of the preformed package is a surface of the substrate free of being mounted with the first chip; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the second chip; and an encapsulant formed on the lead frame, for encapsulating the preformed package, the second chip, the bonding wires and a portion of the lead frame.