Patent ID: 8964476
Filing Date: 2015-02-24
Classification: G11C,H01L

Abstract:
1. A memory system comprising: a controller and a nonvolatile memory device, the controller being configured to control program, read and erase operations of the nonvolatile memory device, the nonvolatile memory device including, a substrate, a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked along a vertical direction to the substrate, each memory cell group including a pillar that extends vertically on a portion of the substrate between an adjacent pair of the doping regions, a plurality of bitlines, a read and write circuit connected to the columns of the plurality of memory cell groups through the plurality of bit lines respectively, and a plurality of word lines connected to the plurality of memory cells of each memory cell group, respectively, and a wordline driver connected to rows of the plurality of memory cell groups through the plurality of word lines, the plurality of word lines being connected to the plurality of memory cells of each memory cell group respectively, the controller being configured to transfer data to the read and write circuit, control the wordline driver and the read and write circuit to program the transferred data into the memory cell array, to control the read and write circuit and the wordline driver to read data from the memory cell array to the read and write circuit and read the data from the read and write circuit, and to control the wordline driver to erase the plurality of memory cells, and the wordline driver is configured, under control of the controller, to apply a first voltage to a first word line among the plurality of word lines and a second voltage to a second word line among the plurality of word lines, the second voltage being different than the first voltage, the second word being closer to the substrate than the first word line.