Patent ID: 6372561
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method for fabricating a field effect transistor in SOI (semiconductor on insulator) technology, the method including the steps of:A. etching an opening through a first surface of a first semiconductor substrate; B. depositing a dielectric material to fill said opening; C. polishing said dielectric material and said first surface of said first semiconductor substrate to form a dielectric island comprised of said dielectric material surrounded by said first surface of said first semiconductor substrate that is exposed; wherein semiconductor material of said first semiconductor substrate remains on said dielectric island toward a second surface of said semiconductor substrate; D. forming a layer of dielectric material on a second semiconductor substrate; E. placing said first surface of said first semiconductor substrate on said layer of dielectric material of said second semiconductor substrate such that said dielectric island and said first surface of said first semiconductor substrate are bonded to said layer of dielectric material; wherein said second surface of said first semiconductor substrate is exposed; F. forming a gate dielectric and a gate electrode over a portion of said semiconductor material disposed on said dielectric island on said second surface of said first semiconductor substrate; and G. implanting a drain and source dopant into said second surface of said first semiconductor substrate that is exposed; wherein a drain extension region and a source extension region are formed by said drain and source dopant being implanted in said semiconductor material disposed on said dielectric island; and wherein a drain contact region and a source contact region are formed by said drain and source dopant being implanted in said semiconductor material of said first semiconductor substrate disposed to sides of said dielectric island.