Patent ID: 7297595
Filing Date: 2007-11-20
Classification: H01L

Abstract:
1. A method of fabricating a non-volatile memory device, comprising the steps of: forming a trench type device isolation layer defining an active area within a semiconductor substrate; forming a tunnel oxide layer only on the active area of the semiconductor substrate; forming a floating gate conductor layer on the tunnel oxide layer and the device isolation layer; forming a floating gate conductor layer pattern exposing a portion of the device isolation layer by patterning the floating gate conductor layer; forming a recess in an upper part of the device isolation layer by removing the exposed portion of the device isolation layer; forming a conductive floating spacer layer on a sidewall of the floating gate conductor layer pattern and a sidewall of the recess of the device isolation layer; anisotropic etching the conductive floating spacer layer to expose an upper conductive surface of the floating gate conductor layer pattern; forming a gate-to-gate insulating layer on the floating gate conductor layer pattern and the conductive floating spacer layer; and forming a control gate conductor layer on the gate-to-gate insulating layer.