Patent ID: 7292475
Filing Date: 2007-11-06
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) of the plurality of memory cell blocks being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) of the plurality of memory cell blocks being arranged in a column direction, and each of the plurality of memory cell blocks including M memory cells (M is an integer equal to or greater than 2); a plurality of wordlines; a plurality of first control gate lines; a plurality of first control gate switches; a plurality of second control gate lines; a plurality of second control gate switches; and a plurality of bitlines, wherein each of the M memory cells includes one nonvolatile memory element and one wordline switch, one end of the nonvolatile memory element being connected to one end of the one wordline switch; wherein each of the plurality of wordlines connects in common gate electrodes of wordline switches of the memory cells in the N memory cell blocks arranged in the row direction; wherein each of the plurality of bitlines connects in common other ends of the plurality of wordline switches of the L memory cells arranged in the column direction; wherein one of the plurality of first control gate lines is disposed in each of the plurality of memory cell blocks and connects in common control gate electrodes of the nonvolatile memory elements of the M memory cells; wherein each of the plurality of first control gate switches is disposed in each of the plurality of memory cell blocks and one end of one of the plurality of first control gate switches in each of the plurality of memory cell blocks is connected to one of the plurality of first control gate lines in each of the plurality of memory cell blocks; wherein each of the plurality of second control gate lines connects in common other ends of the plurality of first control gate switches respectively connected to the L memory cell blocks arranged in the column direction; and wherein, when writing data into the memory cells in a selected memory cell block selected from among the plurality of memory cell blocks, the wordline switches of the memory cells in the selected memory cell block are turned ON by applying a wordline write voltage to wordlines connected to the memory cells in the selected memory cell block, a bitline write voltage is applied to bitlines connected to the memory cells in the selected memory cell block, and a control gate line write voltage is applied to one of the plurality of first control gate lines disposed in the selected memory cell block; wherein one end of one of the plurality of second control gate switches which is ON/OFF-controlled through the plurality of wordlines is connected to one of the plurality of first control gate lines; wherein another end of one of the plurality of second control gate switches is grounded; and wherein, when writing data into the memory cells in the selected memory cell block, one of the plurality of second control gate switches connected to one of the first control gate lines disposed in the selected memory cell block is turned OFF, and a wordline unselect voltage is applied to wordlines not connected to the selected memory cell block so that one of the plurality of second control gate switches connected to one of the plurality of first control gate lines disposed in one of the plurality of memory cell blocks connected to the wordlines to which the wordline unselect voltage is applied is turned ON, thereby causing one of the plurality of first control gate lines disposed in one of the plurality of memory cell blocks disposed in a row other than a row of the selected memory cell block to be grounded.