Patent ID: 7912167
Filing Date: 2011-03-22
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit, comprising: a four-phase clock generation circuit which generates clock signals of four phases equally spaced by 90 degrees; a first interpolator which receives the clock signals with first and third phases of the four phases, performs phase interpolation, and generates a signal obtained by the interpolation and a signal with a phase reverse to a phase of the signal obtained by the interpolation; a second interpolator which receives the clock signals with second and fourth phases of the four phases, performs phase interpolation, and generates a signal obtained by the interpolation and a signal with a phase reverse to a phase of the signal obtained by the interpolation; a control circuit which controls each of phase interpolating amounts of said first and second interpolators separately, a duty ratio correction being separately carried out in a response to respective changes in duty ratios of the even data and the odd data; and a four-phase-to-eight-phase conversion circuit which receives the four-phase clock signals from said first and second interpolators, buffers the four-phase clock signals from said first and second interpolators and delivers the buffered four-phase clock signals without alteration, and generates four-phase clock signals obtained by interpolating two of the clock signals having the mutually adjacent phases among the four-phase clock signals output from said first and second interpolators, thereby providing eight-phase clock signals, a set of the four-phase clock signals among the eight-phase clock signals from said four-phase-to-eight-phase conversion circuit being used for data detection of serial data and the remaining four-phase clock signals being used for edge detection of the serial data, the serial data having even data and odd data multiplexed therein, for transfer.