Patent ID: 6277691
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method to form heavily doped junctions for non-volatile memory cells in the manufacture of an integrated circuit device comprising:providing non-volatile memory gate stacks overlying a semiconductor substrate wherein said non-volatile memory gate stacks comprise control gates overlying an interpoly dielectric layer overlying floating gates overlying a tunneling dielectric layer;depositing a masking layer overlying said non-volatile gate stacks and said semiconductor substrate;patterning said masking layer to form implantation openings in said masking layer for planned heavily doped junctions and to form isolated rings of said masking layer surrounding said implantation openings; andimplanting ions through said implantation openings and into said semiconductor substrate to thereby complete said heavily doped junctions for said non-volatile memory cells in the manufacture of said integrated circuit device wherein said isolated rings of said masking layer do not induce charge flow into said tunneling dielectric layer.