Patent ID: 6462576
Filing Date: 2002-10-08
Classification: H03K

Abstract:
A programmable logic device comprising:a programmable logic array having a plurality of product term output lines, the programmable logic array being operable to generate a respective product term output signal on each product term output line; a first product term summing circuit having a plurality of input terminals and an output terminal, the first product term summing circuit being operable to generate an output signal at the output terminal in response to at least one input signal received at at least one respective input terminal; a first programmable switching circuit operable to couple respective product term output lines of the programmable logic array and respective input terminals of the first product term summing circuit; a second product term summing circuit having a plurality of input terminals and an output terminal, the second product term summing circuit being operable to generate an output signal at the output terminal in response to at least one input signal received at at least one respective input terminal; a second programmable switching circuit operable to couple respective product term output lines of the programmable logic array and respective input terminals of the second product term summing circuit; and a processing and routing circuit connected to the output terminals of the first and second product term summing circuits, the processing and routing circuit being operable to process the output signals of the first and second product term summing circuits, and operable to route the output signals of the first and second product term summing circuits to at least one of a first output line and a second output line, the processing and routing circuit including a register, the processing and routing circuit being operable to couple the output terminals of the first and second product term summing circuits to an input terminal of the register; wherein the first and second programmable switching circuits are operable to simultaneously connect at least one of the product term output lines of the programmable logic array to both the first and second product term summing circuits.