Patent ID: 6504783
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A semiconductor memory device for performing a static random access memory operation interface comprising:a plurality of refresh type memory cells provided in intersections of a plurality of word lines and a plurality of bit lines; a high voltage generator for providing a high voltage to a stand-by high voltage output node in response to a driving control signal activated in a memory cell access operation period, wherein the high voltage is higher than a power source voltage; an internal circuit related to word line driving for selecting a word line among the plurality of word lines using the high voltage in response to command information and address information; and a driving control signal generator generating the driving control signal in response to the command information, wherein a starting point of time for driving the high voltage generator is earlier than a starting point of time of charge consumption at the stand-by high voltage output node in the memory cell access operation period.