Patent ID: 7027940
Filing Date: 2006-04-11
Classification: G01R

Abstract:
1. A network analyzer, couplable to a processing device, for testing a device-under-test (DUT), comprising: a control processor couplable to said processing device via an interface of said processing device; a first signal source in communication with said control processor providing a reference signal of a first frequency; a gain stage in communication with said control processor and receiving said reference signal, providing an output signal to said DUT at at least one predetermined gain value; a second signal source in communication with said control processor, outputting a local oscillation signal of a second frequency, said second frequency being offset from said first frequency by a predetermined fixed amount; a time base oscillator coupled to said first and second signal sources, providing a common time base for said first and second signal sources; and first and second input circuits, each comprising: a programmable attenuator in communication with said control processor measuring signals associated with said DUT; a signal amplifier, connected to said programmable attenuator, amplifying the measured signals associated with said DUT; and a mixer, coupled to said signal amplifier and receiving said local oscillation signal, multiplying the measured signals by the local oscillation signal, thereby providing a signal translated down to a fixed intermediate frequency.