Patent ID: 9213641
Filing Date: 2015-12-15
Classification: G06F

Abstract:
1. A computer implemented method for tracking cache lines, the method comprising: performing an instruction memory access operation by a processor, the processor executing program instructions associated with the memory access operation; fetching a cache line from a memory hierarchy based on the performing the operation, the memory hierarchy comprising at least one cache and a main storage, wherein the cache line is stored at an address in an original level of the memory hierarchy prior to the performing the memory access operation; based on the performing the operation, storing in an instruction address register file, at an entry corresponding to the cache line, a memory location identifier identifying the original level of the memory hierarchy and identifiers of one or more of the program instructions associated with the memory access operation, wherein the memory location identifier is different than the address; and providing access to contents of the instruction address register file for sampling subsequent to completion of the performing, fetching, and storing.