Patent ID: 6766429
Filing Date: 2004-07-20
Classification: G06F

Abstract:
A computer memory system implementing a processing device for enabling indirect storage and retrieval of compressed data in an available address space in a physical memory associated with said computer and issuing real memory addresses for accessing information from said physical memory, and including a compressor mechanism for compressing processor information into compressed information units said compressor mechanism having an associated write back queue for storing data to be compressed for storage into said physical memory, a decompressor mechanism for expanding the compressed information read from said physical memory, said memory system comprising:a sectored storage region for exclusive storage of compressed data received from said compressor mechanism in fixed length storage sectors and having a list of unused sectors and a sector translation table including fixed length entries for mapping said real memory addresses to data storage locations within said physical memory, said compressor mechanism connected to said sectored storage region and said processing device; a memory control device for accessing memory organized as one or two banks, independently addressable as a traditional memory or concurrently addressable for the purpose of managing the bank(s) as a dual redundant storage with means for detecting corrupted read reply data and responsively retrying the read request to another redundant memory bank; and means for configuring the memory as a conventional memory or as a redundant duplex memory by means of dividing the address space of the memory.