Patent ID: 6034960
Filing Date: 2000-03-07
Classification: H04L,H04Q

Abstract:
In an Asynchronous Transfer Mode (ATM) switch, a process of scheduling cell transmissions out over a link for different streams of virtual circuits (VCs) or virtual paths (VPs) by having a link controller that effects such transmissions periodically scan a time-space map, that is comprised of time-slots whose positions within the map correspond to times during which data can be transmitted over an outgoing link and which time-slots are periodically updated with stream-number entries that each correspond to a stream, so that a stream-number entry written into the Nth time-slot of a given map corresponds to the stream that will own the Mth cell transmitted as a result of the link controller scanning the map, where M and N are related by a one-to-one mapping relation wherein each stream is allocated an integer number of time-slots each frame-cycle, a frame-cycle being a single iteration of the periodically repeated process of allowing all the streams a chance to update the time-space map with stream-number entries, according to a process that comprises the steps of:causing each stream to have allocated to it the integer part of the real-number representation of the sum of a guaranteed time-slot allocation for the stream and a carry-over for the stream, the carry-over for the stream being the difference between the total number of time-slots owed to the stream and the total number of time-slots allocated to the stream just prior to the present frame-cycle; and,setting the carry-over for the next frame-cycle equal to the non-integer part of the sum of the guaranteed time-slot allocation for the stream and the carry-over for the stream.