Patent ID: 6346427
Filing Date: 2002-02-12
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit to meet performance specifications for power dissipation, comprising:a) fabricating at least one first prototype integrated circuit with a set of masks including a first mask for defining at least one active area of the integrated circuit; b) testing the at least one prototype integrated circuit to determine whether performance specifications are met; c) determining the size of the at least one active area required to meet the performance specifications based on the test results, if the performance specifications are not met; d) creating a second mask for defining the at least one active area having the determined size; e) replacing the first mask by the second mask to create a second set of masks; f) fabricating at least one second prototype integrated circuit with the second set of masks; g) testing the at least one second prototype integrated circuit to determine whether performance specifications are met; and h) proceeding with manufacture of the integrated circuit with the second set of masks if the performance specifications are met.