Patent ID: 6774707
Filing Date: 2004-08-10
Classification: H02M

Abstract:
A charge pump circuit comprising:a first native transistor; first depletion transistors each having a threshold voltage that is lower that a threshold voltage of the first native transistor at a common source voltage; second depletion transistors each having a threshold voltage that is lower than the threshold voltage of each of the first depletion transistors at a common source voltage; and first capacitors that are each coupled to a drain of one of the first or the second depletion transistors, wherein a first subset of the first capacitors are coupled to receive a first clock signal, and a second subset of the first capacitors are coupled to receive a second clock signal; and wherein the first native transistor, the first depletion transistors, and the second depletion transistors are all coupled together in series between an input and an output of the charge pump circuit.