Patent ID: 6577695
Filing Date: 2003-06-10
Classification: H03L,H04L

Abstract:
A phase-locked loop (PLL), comprising:frequency compare means for detecting a frequency difference between a PLL output signal and a combination of a first and a second reference signal, and for generating a frequency error signal in response thereto; phase error detection means for detecting a phase difference between a received input signal and the PLL output signal, and for generating a phase error signal in response thereto; signal summing means, coupled to the phase error detection means and the frequency compare means, for combining the phase error signal and the frequency error signal to form a combined error signal, wherein the frequency compare means increases the amplitude of the frequency error signal to create a frequency error signal that overdrives the phase error signal when the frequency difference is outside of a predetermined frequency range; and a input-controlled oscillator having an input terminal coupled to receive the combined error signal and an output terminal to output the PLL in response thereto.