Patent ID: 7116604
Filing Date: 2006-10-03
Classification: G11C

Abstract:
1. A method for conducting a multiple word line selection test on a semiconductor memory device provided with a plurality of memory cell blocks, which include a first memory cell block and a second memory cell block, each of the memory cell blocks having a plurality of memory cells and a plurality of word lines connected to the memory cells, and a plurality of sense amp groups connected to the first and second memory cell blocks, each of the sense amp groups amplifying cell information read from the plurality of memory cells of an associated one of the memory cell blocks, and a plurality of block control circuits respectively connected to the plurality of memory cell blocks, which include a first block control circuit and a second block control circuit, wherein when the multiple word line selection test is conducted, the plurality of word lines and the sense amp group in each of the plurality of memory cell blocks are activated, the method comprising: a first step for generating a first reset signal using the first block control circuit; a second step for inactivating multiple word lines in the first memory cell block and the sense amp group associated with the first memory cell block in response to the first reset signal; and a third step for generating a second reset signal using the second block control circuit; a fourth step for inactivating multiple word lines in the second memory cell block and the sense amp group associated with the second memory cell block after performing the first step in response to the second reset signal.