Patent ID: 6434722
Filing Date: 2002-08-13
Classification: G06F

Abstract:
A method of generating a logic circuit formed by using a gated clock and extracted flip-flops for the logic circuit, comprising:(a) selecting a flip-flop represented by g; (b) producing a logic function for determining an input f with respect to the selected flip-flop g, said logic function being represented by the following equation f=eÂ·h+ebÂ·d wherein e and eb are an enable signal and a NOT enable signal respectively while h is an output signal of the selected flip-flop g and d is a data signal;(c) judging whether or not the output signal h is included in the logic function; (d) calculating a first co-factor f e) for the enable signal e if h is included as a result of the judgement; (e) judging whether or not a relation of f(e)=h is satisfied; (f) generating said logic circuit formed by using the gated clock if the relation is satisfied; (g) calculating a second co-factor f(eb) for the NOT enabled signal eb based if the relation is not satisfied; (h) judging whether or not a relation of f(eb)=h is satisfied; (i) generating the logic circuit formed by using the gated clock if the relation is satisfied; and (j) selecting another flip-flop if the relation is not satisfied.