Patent ID: 6262926
Filing Date: 2001-07-17
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array, in which nonvolatile memory cells capable of being electrically rewritable are arranged;a decode circuit for selecting a memory cell of said memory cell array;a sense amplifier circuit for sensing read data of said memory cell array and for latching written data to said memory cell array;a driving voltage generating circuit for generating a boosted driving voltage in accordance with write and erase modes;a defective block detecting circuit for detecting a block including a defective memory cell of said memory cell array by detecting a potential of at least one signal line which is driven by said driving voltage generated by said driving voltage generating circuit; anda test control circuit for controlling a batch erasing test every batch erasing operation unit in said memory cell array and/or a batch writing test every writing operation unit in said memory cell array, and for stopping of the supply of said driving voltage to said defective memory cell during said batch erasing test and/or said batch writing test on the basis of a detected result of said defective block detecting circuit.