Patent ID: 6282244
Filing Date: 2001-08-28
Classification: H04N

Abstract:
An apparatus for decoding a bit stream of compressed digital video data, comprising:(a) a variable length decoding (VLD) circuit, responsive to the compressed digital video data, for generating a first bit sequence of a fixed length by decoding the compressed digital video data;(b) an inverse quantizer, responsive to the generated first bit sequence, for converting the first bit sequence by an inverse quantization method into a second bit sequence;(c) a zig-zag buffer, responsive to the second bit sequence, for storing the second bit sequence at specific addresses and for generating a plurality of parallel frequency-division binary signal bits; and(d) an inverse discrete cosine transfer (IDCT) circuit, responsive to the plurality of parallel frequency-division binary signal bits, for processing the plurality of parallel frequency-division binary signal bits according to an inverse discrete cosine transfer function, to thereby generate a plurality of time-division binary signal bits, and for combining the time-division binary signal bits into a time-division serial binary signal representative of decoded data for the compressed digital video data.