Patent ID: 6673680
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A process for fabricating a power device comprising the steps of:etching multiple gate bus trenches into a top surface of a semiconductor region of a substrate, said semiconductor region surrounds the trenches and comprises dopant impurities of only one type polarity with a concentration selected to form depleted regions from portions of said semiconductor region bordering the trenches at chosen operating voltages so as to merge together the depleted regions beneath a gate bus disposed above the trenches; depositing an oxide layer uniformly over all exposed surfaces of said trenches and said top surface of said substrate; depositing a conductive layer in the trenches and over the surface; patterning the conductive layer by removing selected portions to expose portions of the substrate, to form said gate bus over the trenches and to form one or more gates over other exposed portions of the substrate; implanting the substrate with first and second implants of opposite conductivities to form wells and source regions in the other exposed portions of the substrate; depositing a dielectric layer over the substrate; forming source contact openings in the dielectric layer; depositing a top metal over said dielectric layer to contact the source regions.