Patent ID: 6651114
Filing Date: 2003-11-18
Classification: G06F

Abstract:
A DMA controller arranged to transfer data between a main storage connected to a system bus and an I/O device connected to an I/O bus, said DMA controller comprising:an FIFO memory arranged to buffer a difference in transfer speed between said system bus and said I/O bus; first transfer means for transferring data between said main storage and said FIFO memory through said system bus; request receiving means for receiving from said I/O device a request for transfer by DMA; second transfer means for transferring data of by every one transfer unit between said FIFO memory and said I/O device through said I/O bus when a request for normal transfer by DMA is received by said request receiving means; and third transfer means for continuously transferring data by a predetermined number of transfer units between said FIFO memory and said I/O device through said I/O bus when a request for continuous transfer by DMA is received by said request receiving means, wherein if a remainder of data to be transferred becomes less than the predetermined number of transfer units during a transfer by the predetermined number of transfer units by said third transfer means, the remainder of data is transferred by every one transfer unit by said second transfer means.