Patent ID: 9048827
Filing Date: 2015-06-02
Classification: H03K

Abstract:
1. A flexible logic unit comprising: a first clock and a second clock, the first clock and the second clock being non-recovering clocks; a matrix having a plurality of tiles arranged in columns and rows, each tile having at least one latch bank therein, each latch bank within any one column having an identical number of one or more latches therein, each tile having configurable logic configurable responsive to configuration data stored in the respective latch bank, the latches in each latch bank being clocked in unison for that latch bank, each of the latch banks being arranged to accept configuration data from an immediately previous latch bank in that column, such that one latch bank is clocked by the first clock if an immediately previous latch bank in the same column is clocked by the second clock or by the second clock if an immediately previous latch bank in the same column is clocked by the first clock, each column of the matrix being configured to accept configuration data in a first configuration data flow direction within the column; a plurality of lock flip-flops arranged in columns, each lock flip-flop corresponding to a respective latch bank of a respective column of the matrix, the plurality of lock flip-flops configured to accept a lock bit in a lock bit flow direction that is opposite to the configuration data flow direction, one lock flip-flop being clocked by the first clock if an immediately previous lock flip-flop in the same column is clocked by the second clock or by the second clock if an immediately previous lock flip-flop in the same column is clocked by the first clock; and a control interface to accept at least a configuration word for each latch bank and associated lock flip-flop, the interface configured to separate, for each column, configuration data and lock bits data from the configuration words.