Patent ID: 8619848
Filing Date: 2013-12-31
Classification: H04L

Abstract:
1. An apparatus comprising: a first logic unit to generate decision feedback equalizer (DFE) coefficients for data samples of a data signal; a second logic unit to generate DFE coefficients for edge samples of the data signal, wherein the DFE coefficients for the edge samples of the data signal are based at least in part on the DFE coefficients for the data samples of the data signal; and a third logic unit which comprises: a first DFE summation logic unit to generate a corrected data sample from the DFE coefficients for the data samples of the data signal and previous data samples of the data signal; a second DFE summation logic unit to generate a corrected edge sample signal from the DFE coefficients for the edge samples of the received data signal and the previous data samples of the received data signal; a data sampling unit to sample the corrected data by a first clock signal; and an edge sampling unit to sample the corrected edge sample signals by a second clock signal, wherein the first and second clock signals are delayed with respect to a reference signal.