Patent ID: 6460171
Filing Date: 2002-10-01
Classification: G06F

Abstract:
A method for designing a processor core having a normal operating mode and a test mode, said method comprising the steps of:programing configuration registers of the processor core by providing a cell that is definitively configured at either one or zero in the normal operating mode for each bit of the configuration registers, each cell being a latch with control signal inputs for receiving a direct resetting command and a direct setting command, each cell being definitively configured at either one or zero in the normal operating mode by inhibiting either the direct resetting command or the direct setting command; and providing the latch of each configured cell with a data input such that data can be written into the cells only in the test mode, wherein both the cells definitely configured at one in the normal operating mode and the cells definitely configured at zero in the normal operating mode have the same abstract defining their space requirements and input and output pins.