Patent ID: 7551010
Filing Date: 2009-06-23
Classification: H03L

Abstract:
1. A PLL circuit comprising: a phase comparator for carrying out phase comparison between a reference clock signal and a comparison clock signal at every period of the reference clock signal, and for outputting a rectangular wave signal having a reference level as a middle value, and having a high voltage level or low voltage level corresponding to a phase lead or phase lag, and provided with a pulse width corresponding to a phase difference; an averaging device for averaging the rectangular wave signal output from said phase comparator at every period of the reference clock signal, and for outputting the average value; a voltage latch circuit for reading the voltage value output from said averaging device synchronously with respect to the reference clock signal while simultaneously supplying the voltage value to a voltage controlled oscillator, and for outputting the voltage value upon input of a next period of the reference clock signal; and the voltage controlled oscillator to be used in a range, in which a voltage versus frequency characteristic has a linear characteristic, for generating an output clock signal with a frequency corresponding to a voltage value output from said averaging device, wherein a signal obtained by dividing the output clock signal generated by said voltage controlled oscillator by N (N is a natural number) is fed back to said phase comparator as the comparison clock signal.