Patent ID: 6790756
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method of forming a semiconductor for use with a gate electrode damascene process, comprising:providing a semiconductor silicon substrate; forming a thin dielectric layer on top of said silicon substrate; depositing a thick layer of oxide on said thin dielectric layer; creating a trench pattern, said trench pattern to penetrate and go through said thick layer of oxide, furthermore to penetrate and go through said thin dielectric layer, furthermore to penetrate said silicon substrate to form a shallow trench in said silicon substrate; forming a thin layer of oxide at the bottom of said trench pattern; performing a channel implant in said silicon substrate, said implant to be self-aligned with said trench pattern; forming spacers on sidewalls of said trench pattern; removing said thin layer of oxide from the bottom of said trench pattern where said thin layer of oxide is not covered by said spacers; forming a gate dielectric at the bottom of said trench pattern where said thin layer of oxide has been removed; forming a gate electrode in said trench pattern and on said gate dielectric; removing said thick layer of oxide from said thin dielectric layer; removing said thin dielectric layer from said substrate; performing source and drain implant in said silicon substrate, said source and drain implant to be substantially self-aligned with said spacers, and laterally diffusing impurities to form lightly doped drain areas under said spacers; and forming silicide on said silicon substrate above said source and drain implants and on said gate electrode and on said spacers.