Patent ID: 6211019
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A read-only memory cell device, comprising:a substrate formed of semiconductor material and having a main area;bit lines and word lines;memory cells disposed in matrix form in columns and rows in a cell field in the vicinity of said main area, each of said memory cells having at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode, said MOS transistors of a column connected in series one after the other, each column connected to a bit line and said gate electrodes of said MOS transistors of a row connected to a word line;source/drain webs running substantially parallel to one another at a predetermined spacing, electrically insulated from one another, produced from said semiconductor material of said substrate and having a longitudinal direction and a predetermined web depth starting from said main area of said substrate, said source and drain regions of said MOS transistors of a column formed in said source/drain webs; andsaid word lines for connection of said gate electrodes of said MOS transistors running transversely relative to said longitudinal direction of said source/drain webs.