Patent ID: 6348814
Filing Date: 2002-02-19
Classification: H03K

Abstract:
A buffer circuit connected to an output pad, and comprising:a NAND gate and a pullup transistor having a transistor gate, connected together; a NOR gate and a pulldown transistor having a transistor gate, connected together, with the pulldown and pullup transistors being connected at a common output node; first and second wide and long transistors connected in series with the NAND gate and with the NOR gate, respectively; a source current transistor connected between a VDD potential source and the pullup transistor gate to provide enhanced source current to the pullup transistor; a sinking current transistor connected between a ground potential source and the pulldown transistor gate to provide enhanced sinking current to the pulldown transistor; and analog circuitry for controlling a rate at which at least one of the first and second wide and long transistors turns on.