Patent ID: 6281720
Filing Date: 2001-08-28
Classification: H03K

Abstract:
An electric integrated circuit, comprising:a CMOS output driver stage connected between a high-potential side supply voltage terminal receiving a first voltage and a low-potential side supply voltage terminal receiving a second voltage lower than the first voltage and having a first MOS driver transistor of one channel type and a second MOS driver transistor of the other channel type, by means of which driver pulses can be delivered to a terminal of the integrated circuit;a control signal source delivering switching control pulses;and a switching-on voltage reducing stage for reducing the voltage flowing through the respective first and second driver transistor to be switched on in a switching-on phase, comprising a first parallel connection and a second parallel connection each having one first MOS parallel transistor of the one channel type and one second MOS parallel transistor of the other channel type connected in parallel thereto,wherein the first parallel connection is connected between the control signal source and the gate terminal of the first driver transistor and the second parallel connection is connected between the control source and the gate terminal of the second driver transistor,wherein in each of the first and second parallel connections the gate terminal of each parallel transistor that is of the same channel type as the respective first and second driver MOS transistors belonging to the respective parallel connection, is coupled with the gate terminal of the respective first and second driver MOS transistor belonging to the respective other parallel connection, whereas a gate terminal of each respective first and second parallel transistor that is of a different channel type than the respective first and second driver MOS transistors belonging to the respective parallel connection, is connected to the same supply voltage terminal as the driver MOS transistor belonging to the respective parallel connection, andwherein the parallel transistors whose gate terminals are connected to the supply voltage terminals, in the on-state, display an on-state forward resistance of a first impedance, and the parallel transistors whose gate terminals are connected to the gate terminals of the driver transistors of the respective other parallel circuit are constituted by switching transistors of an on-state forward resistance having a second impedance lower than the first impedance.