Patent ID: 7342945
Filing Date: 2008-03-11
Classification: H04B,H04J,H04N

Abstract:
1. A data time difference absorbing circuit comprising; a first memory in which each part having predetermined data amount of first digital data containing first time reference code data relating to the start and end of active video is stored one by one and from which each stored part of the first digital data is read one by one, a second memory in which each part having predetermined data amount of second digital data containing second time reference code data relating to the start and end of active video is stored one by one and from which each stored part of the second digital data is read one by one, data detecting means for detecting the first time reference code data contained in the first digital data read from the first memory and the second time reference code data contained in the second digital data read from the second memory, phase difference detecting means for detecting a phase difference between the first and second time reference code data detected by the data detecting means, and memory controlling means operative to control at least one of a first timing at which the first digital data are read from the first memory and a second timing at which the second digital data are read from the second memory in response to the phase difference detected by the phase difference detecting means so as to keep a condition in which the phase difference detected by the phase difference detecting means is substantially zero.