Patent ID: 7060549
Filing Date: 2006-06-13
Classification: H01L

Abstract:
1. A method for fabricating a cell of an SRAM device, the method comprising the steps of: fabricating an NFET in and on a substrate, wherein the NFET has a gate region, a source region, a drain region, and a channel region disposed within said substrate below said gate region and between said source and drain regions; fabricating a PFET in and on said substrate, wherein said PFET has a gate region, a source region, a drain region, and a channel region disposed within said substrate below said gate region and between said source and drain regions, and wherein, upon fabrication of said PFET and said NFET, said PFET and said NFET are electrically coupled and are physically isolated; depositing a tensile-strained stress film on said gate region and at least a portion of said source region and said drain region of said PFET to decrease the mobility of carriers through the channel region of said PFET; and completing fabrication of the cell such that, during operation of the cell, the mobility of carriers through said channel region of said PFET is decreased.