Patent ID: 8236650
Filing Date: 2012-08-07
Classification: H01L,Y02E

Abstract:
1. A method of fabricating a semiconductor device comprising: providing a substrate of single-crystal semiconductor material extending in a horizontal direction; providing a plurality of interlayer dielectric layers on the substrate; providing a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer; providing a vertical channel of semiconductor material extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns; providing a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel; and, wherein providing each of the plurality of interlayer dielectric layers comprises providing a multiple-layered structure comprising a lower insulating layer, an intermediate insulating layer and an upper insulating layer, the lower and upper insulating layers comprising a material that has etch selectivity relative to the intermediate insulating layer.