Patent ID: 6505260
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A computer system comprising:a memory device for storing data; a processor coupled to said memory device and which transmits memory requests to said memory device; a first master device coupled to said memory device via a first expansion bus, said first master device being capable of transmitting memory requests to said memory device; and a bridge logic coupled to said memory device, said processor, and said first expansion bus, said bridge logic comprising: a memory arbiter which classifies the memory requests into at least a first request group and a second request group, said memory arbiter being capable of selecting one of the memory requests during an arbitration cycle as a winning request to transact with said memory device, wherein the request group from which the winning request is selected is based on an adaptive arbitration scheme which adapts according to the winning request, and wherein the winning request is selected from one of the first and second request groups after selection of a winning request group; and wherein the adaptive arbitration scheme includes a first adaptive variable having only two states that determines the priority between the first request group and the second request group; a memory controller that receives the memory requests and asserts control, data, and address signals to said memory device to transact the winning request.