Patent ID: 7394161
Filing Date: 2008-07-01
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; a MOS device on a surface of said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first patterned circuit layer and a second patterned circuit layer over said first patterned circuit layer; a dielectric layer between said first and second patterned circuit layers; a passivation layer over said metallization structure, over said first and second patterned circuit layers and over said dielectric layer, wherein an opening in said passivation layer exposes a top surface of said metallization structure, wherein said passivation layer comprises a nitride layer and an oxide layer; and a third patterned circuit layer comprising a first portion connected to said top surface through said opening and used to have a metal bump formed thereover, a second portion used to be in contact with a testing probe, and a third portion used to be wirebonded thereto, wherein said first portion is connected to said second portion.