Patent ID: 7772868
Filing Date: 2010-08-10
Classification: G01R,H01L

Abstract:
1. A method of measuring parasitic capacitance in a semiconductor device, said method comprising: providing a first test structure having a first array of unit cells, each unit cell of said first array comprising a first gate electrode, a first plurality of to-be-measured contacts, and a first plurality of adjacent conductive features; applying a first bias to the first gate electrode and a second bias to the first plurality of to-be-measured contacts and to the first plurality of adjacent conductive features; measuring a first capacitance on said first test structure between said first bias and said second bias; providing a second test structure formed having a second array of unit cells, wherein each unit cell of said second array comprises a second gate electrode and a second plurality of adjacent conductive features, said each unit cell of said second array having no to-be-measured contacts; wherein the second gate electrode is substantially similar to the first gate electrode, and the second plurality of adjacent conductive features is substantially similar to the first plurality of adjacent conductive features; applying the first bias to the second gate electrode and the second bias to the second plurality of adjacent conductive features; measuring a second capacitance on the second test structure between the first bias and the second bias; and calculating a parasitic capacitance C