Patent ID: 8423844
Filing Date: 2013-04-16
Classification: G01R

Abstract:
1. A scannable register array structure, comprising: a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation; the plurality of individual latches further configured to operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches, wherein a test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches; and the L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.