Patent ID: 7584320
Filing Date: 2009-09-01
Classification: G06F,H04L

Abstract:
1. A method of processing memory transactions between a plurality of processors and a plurality of shared memories, wherein a plurality of interconnected crossbar switches in a multi-stage crossbar network provides a communications path between the plurality of processors and plurality of shared memories, the method comprising: receiving a plurality of memory transactions at a crossbar switch, each memory transaction having been divided into a plurality of associated portions, each portion comprising an address corresponding to a target resource, wherein each crossbar switch comprises a plurality of slices for processing the plurality of associated portions of a received memory transaction in parallel; assigning a priority to each received portion in each slice, wherein each slice independently assigns the same priority to each associated portion of a given memory transaction; and forwarding each of the plurality of portions to its corresponding target resource based on the address and the assigned priority, wherein each slice independently forwards each associated portion of a given memory transaction at substantially the same time.