Patent ID: 7345908
Filing Date: 2008-03-18
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a plurality of memory cells that each include a memory element having a memory layer and first and second electrodes that sandwich the memory layer, the memory layer having a high resistance layer and an ion source layer, a state of the memory layer being changed from a high resistance state to a low resistance state due to application of an electric signal equal to or larger than a first threshold signal between the first and second electrodes, the state of the memory layer being changed from a low resistance state to a high resistance state due to application of an electric signal equal to or larger than a second threshold signal between the first and second electrodes, a polarity of the second threshold signal being opposite to a polarity of the first threshold signal, the plurality of memory cells being divided into memory blocks of m columns by n rows (m and n are each an integer of not less than 1, m+n≧3), the memory cells in the same memory block having first electrodes formed of a single layer in common to the memory cells of that memory block; and voltage application means that applies any voltage to the first electrode of the memory block.