Patent ID: 8561060
Filing Date: 2013-10-15
Classification: G06F

Abstract:
1. A processor comprising: one or more registers configured to store an intercept configuration that identifies which of a plurality of intercept events are enabled for intercept during guest execution, and wherein the intercept configuration identifies, for each enabled intercept event, which of at least two exit mechanisms are to be used in response to detection of the enabled intercept event; and an execution core coupled to the one or more registers, wherein the execution core is configured to detect one of the enabled intercept events during execution of a guest and to exit the guest using the exit mechanism identified in the intercept configuration for that detected, enabled intercept event, wherein a first exit mechanism of the at least two exit mechanisms invokes first code that executes in a guest address space associated with the guest, and wherein a second exit mechanism of the at least two exit mechanisms invokes a virtual machine monitor (VMM) that controls the guest, and wherein the intercept configuration comprises a respective first intercept indication for each of the plurality of intercept events that indicates whether or not the intercept event is enabled, and a respective second intercept indication for each of the plurality of intercept events that indicates the exit mechanism to be used if the intercept event is enabled and detected.