Patent ID: 6760743
Filing Date: 2004-07-06
Classification: G06F

Abstract:
A computer instruction memory system for concurrently handling instructions for multiple system processors comprising:a) a plurality of memory arrays operating as independent subsystems corresponding to a number of disjoint tasks to be performed; b) a separate data path and data address for each memory array; c) means for consolidating identical instruction codes for a given disjoint task into at least one memory array; and d) means to share all of the instruction codes from the memory arrays with all of the processors in the system; wherein said number of disjoint tasks include inbound tasks, outbound tasks, and control tasks, and wherein separate arbiters are adapted for receiving and serving separate requests of inbound task instructions, outbound task instructions, and control task instructions, respectively, and controlling multiplexors to pass the address of the instructions on the order of priority to a single memory array.