Patent ID: 7799685
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. In an overall technique for fabricating an integrated circuit on a wafer to include an active device structure which supports an electrical interconnect structure, and during an intermediate step, prior to forming said electrical interconnect structure, a patterned layer of photoresist is used in the overall technique and which patterned layer of photoresist is exposed to a high dose ion implant to form an implant crust as an outermost layer of the photoresist, and to form a junction in a silicon surface of said wafer, said implant crust being supported by an unaltered, bulk portion of the photoresist, a method comprising: prior to forming the electrical interconnect structure, exposing the patterned layer of photoresist and the exposed regions of the active device structure to one or more reactive species that are generated in a plasma using a gas mixture including hydrogen gas, as a predominant source of said reactive species and nitrogen gas without adding oxygen, in a plasma source to at least partially remove the implant crust from said patterned layer of photoresist and to remove at least some portion of the bulk photoresist such that the implant crust of the photoresist is continuously exposed to hydrogen-based reactive species during the removal of said photoresist to limit loss of silicon from said silicon surface of the wafer by oxidation.