Patent ID: 7759726
Filing Date: 2010-07-20
Classification: H01L

Abstract:
1. A structure of non-volatile memory cell, comprising: a substrate having a recess; two dielectric strips separately formed on the substrate, wherein the recess is interposed between two dielectric strips; two conductors respectively formed over the dielectric strips; a dielectrically stacking multi-layer comprising a charge-trapping layer, the dielectrically stacking multi-layer being formed on the conductors and along the recess, the dielectrically stacking multi-layer in contact with two upper surfaces and two lateral surfaces of the two conductors, two lateral surfaces of the two dielectric strips, and an inner surface of the recess; a conductive layer, formed on the dielectrically stacking multi-layer; and wherein when a voltage is applied to the two conductors, two inversion regions are respectively generated in the substrate so as to act as an induced source and an induced drain, the induced source and the induced drain respectively located beneath the two dielectric strips and the two conductors, a part of the dielectrically stacking multi-layer covering the inner surface of the recess being positioned between the induced source and drain.