Patent ID: 7494875
Filing Date: 2009-02-24
Classification: H01L

Abstract:
1. A method comprising: etching a semiconductor material of a first conductivity type to form first and second trenches that define a mesa having first and second sidewalls; forming first and second dielectric layers respectively covering the first and second sidewalls; forming, in a masking layer, first and second openings respectively disposed over the first and second dielectric regions on opposite sides of the mesa, the masking layer having a portion between the first and second openings that covers the mesa and overlaps a distance beyond each edge of the first and second sidewalls coincident with a top surface of the mesa; anisotropically etching the first and second dielectric regions through the respective first and second openings to create first and second gate trenches; isotropically etching the first and second dielectric regions in the first and second gate trenches to remove the first and second sidewall portions; thermally forming a gate oxide on each of the first and second sidewalls of the mesa following the isotropic etching of the first and second dielectric regions; and forming first and second gate members in the first and second gate trenches, respectively, the first and second gate members comprising polysilicon and being respectively insulated from the first and second sidewalk by the gate oxide.