Patent ID: 6662326
Filing Date: 2003-12-09
Classification: G01R,G06F

Abstract:
A method of testing circuit cells in an integrated circuit, wherein a respective circuit cell contains a combinatorial circuit for data processing, a memory unit, and a memory control unit, and wherein the circuit cells, a test pattern generation, and a test pattern evaluation are synchronized in decentralized fashion by the memory control units in the circuit cells, the method which comprises the following steps:initializing one circuit cell as a test pattern transmission circuit cell and initializing one circuit cell as a test pattern reception circuit cell; transmitting an instruction signal from a memory control unit in the test pattern transmission circuit cell to the associated memory unit for generating a test pattern; applying the test pattern to a combinatorial circuit for data processing by the memory unit in the test pattern transmission circuit cell; transmitting a request signal by the memory control unit in the test pattern transmission circuit cell to the memory control unit in the test pattern reception circuit cell; transmitting an instruction for test pattern compression to the memory unit in the test pattern reception circuit cell by the memory control unit in the reception circuit cell; transmitting an acknowledgement signal from the memory control unit in the test pattern reception circuit cell to the memory control unit in the test pattern transmission circuit cell; switching the memory unit in the test pattern reception circuit cell to a test data evaluation mode by the memory control unit in the test pattern reception circuit cell; transmitting a request signal to the test machine for reading-out the compressed test data by the memory control unit in the test pattern reception circuit cell; and reading out the test data of the memory unit in the test pattern reception circuit cell by the test machine.