Patent ID: 6353880
Filing Date: 2002-03-05
Classification: G06F

Abstract:
A pipeline for processing instructions for a microcontroller in four stages, wherein operations in each stage are performed concurrently in a single clock cycle, comprising:data memory for retrieving data in response to receiving a read address and storing data in response to receiving a write address, said data memory comprising: a first port, coupled to a read input of the execution stage, for transmitting retrieved data to the execution stage; and a second port, coupled to a write data output of the write back stage, for receiving the write address and the results of calculations from the write back stage; an instruction fetch stage, for retrieving instruction data from non-volatile memory; an operand fetch stage, coupled to the instruction fetch stage and said data memory, for decoding the instruction data to determine a task to be performed responsive to the instruction data, for generating a read address responsive to the task requiring a read operation, and for transmitting the read address to said data memory; an execution stage, coupled to the operand fetch stage and said data memory, for receiving data specified by the read address from said data memory, for generating a write address responsive to the decoded instruction data requiring a write operation to be performed, for generating control signals from the decoded instruction data, and for performing calculations responsive to the control signals on the received data; a write back stage, coupled to the execution stage for writing results of the calculations to said data memory at a location specified by the write address; a first condition control logic, coupled to the operand fetch stage, the execution stage, the data memory, and the write back stage, for comparing the write address and the read address of consecutive instructions in a first clock cycle and, responsive to the write address and the read address of consecutive instructions being identical, transmitting a disable signal to an enable input of the data memory to disable a read operation, and coupling a write data register to the write data output for storing a copy of the results of the calculations in the first clock cycle; and, coupling the read input of the execution stage to the write data register to transmit the stored copy of the results of the calculations to the execution stage in a second instruction cycle occurring after said first instruction cycle; and a second conditional control logic, coupled to the operand fetch stage, the execution stage, the data memory, and the write back stage, for, responsive to a first instruction modifying a value in the data address pointer and a second instruction performing a read operation, selecting the modified value, generating a read address responsive to the modified value, and transmitting the generated read address to the data memory.