Patent ID: 6385696
Filing Date: 2002-05-07
Classification: G06F

Abstract:
A cache memory comprising:a tag array split into first and second halves each having N ways, the first half of the tag array to store an upper M sets and the second half of the tag array to store a lower M sets, lower order address bits reading the first and second halves in a first phase of a clock cycle; compare circuitry coupled to the first and second halves of the tag array to compare each of the N ways read out of both the first and second halves with higher order address bits; select circuitry coupled to the compare circuitry to select a set of way select signals based on at least one bit of the higher order address bits; and a data array having N ways and 2M sets, the lower order address bits, in combination with the at least one bit, being used to access the data array, the set of way select signals outputting data of a correct way.