Patent ID: 6526112
Filing Date: 2003-02-25
Classification: H03L,H04L

Abstract:
A multiple channel clock and data recovery system comprising:N phase lock loop circuits for receiving in parallel N data channels, each of the N phase lock loop circuits including a digital phase detector and a dual-input VCO in which one VCO input is an analog input for setting the center frequency of the VCO and the other VCO input is a digital input from the respective phase detector for toggling the center frequency and wherein each phase detector compares the phase of the respective incoming data channel with that of the respective VCO output; a first phase lock loop circuit of the N phase lock loop circuits further including an integrator having a single capacitor, the integrator connected between the output of the first phase detector and the analog input of the respective first VCO wherein the output of the first phase detector is input to the integrator, the output of the integrator is also input to the remaining analog inputs of the other VCOs such that the remaining phase lock loop circuits are slaved to the first phase lock loop circuit.