Patent ID: 6643211
Filing Date: 2003-11-04
Classification: G11C

Abstract:
An integrated memory, comprising:a plurality of memory cell arrays having memory cells, word lines for selecting said memory cells, and bit lines for reading out or writing in data signals from/to said memory cells; decoders, including word line decoders and a bit line decoder, connected to said memory cell arrays for selecting said bit lines and said word lines; a control circuit having an input side and connected to said decoders, said control circuit addressing said word lines and said bit lines, and if one of a read command and a write command is present on said input side of said control circuit, at least two of said word lines can be activated simultaneously; and a multiplexer having an input side coupled to said bit line decoder for addressing said bit lines, said multiplexer configured such that in a burst mode read access, in each clock period, a datum assigned to addressed memory cells is output until a burst mode operation advances by a predetermined burst length; the burst length being determined by a number of said word lines simultaneously activated by said control circuit.