Patent ID: 7043466
Filing Date: 2006-05-09
Classification: G06N

Abstract:
1. A semiconductor integrated circuit device, comprising: a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; a processing circuit which carries out an operation using information stored in said memory array; and an input/output circuit; wherein said semiconductor integrated circuit device has a first mode and a second mode, wherein, in said first mode, a read operation and a write operation to said memory array are performed, wherein the information stored in said memory array is read out to said input/output circuit in said read operation of said first mode and information outputted from said input/output circuit is written to said memory array in said write operation of the first mode, wherein, in said second mode, information stored in said memory array is read from said memory array to said processing circuit, wherein said processing circuit has an arithmetic unit and a MOS transistor which has a source/drain path between said arithmetic unit and a power line and a gate inputted with a control signal, and wherein during said first mode said MOS transistor is in an OFF state.