Patent ID: 6975106
Filing Date: 2005-12-13
Classification: G04F,H03L

Abstract:
1. A circuit operable to perform analysis of a time interval between two measurement edges of interest in a data bit stream, said circuit comprising: a plurality of at least three substantially interchangeable oscillators configured to be locked to a common reference frequency, said oscillators comprising digital locked-loop (DLL) circuit architecture; a first oscillator of said plurality of oscillators operable to function in the role of a timebase oscillator; the other oscillators of said plurality of oscillators operable to function in the roles of edge-resettable measurement oscillators; the first oscillator of said plurality of oscillators comprising a switched and physically-immutable parametric variation operable to produce an offset in the frequency of said first oscillator relative to the frequency of said other oscillators; and a plurality of phase detectors, each of said phase detectors coupled to one of said plurality of oscillators.