Patent ID: 8294498
Filing Date: 2012-10-23
Classification: H03L

Abstract:
1. A clock de-skewing delay locked loop circuit comprising: a timing control circuit that generates a first clock signal and a second clock signal according to an internal clock signal and an external clock signal; a clock delay line that delays the first clock signal or the external clock signal to generate a plurality of delay signals; a delay mirror circuit that generates at least one delay selection signal to control the clock delay line, stops receiving the delay signals and converts the delay signals to a delay data according to the second clock signal, obtains a phase difference between the first clock signal and the second clock signal according to the delay data, and controls the clock delay line for synchronizing the internal clock signal with the external clock signal; a phase adjustment circuit that inverts the phase of the internal clock signal CK_int according to the phase difference between the external clock and the internal clock; and an inverting buffer circuit that buffers the external clock signal or the first clock signal to increase an initial delay time and make a duty cycle of the internal clock signal and a duty cycle of the external clock signal complement each other.