Patent ID: 6101143
Filing Date: 2000-08-08
Classification: G11C

Abstract:
A power down circuit for a field programmable gate array integrated circuit, hereafter FPGA, comprising:an external pin on said FPGA for receiving a power down signal supplied from an external source;a distribution network on said FPGA to distribute said power down signal to every static random access memory cell (hereafter SRAM cell) on said FPGA, each memory cell having word lines therein, each word line having a pass transistor with a control input for receiving a control signal which controls whether said pass transistor is turned on or turned off; anda gating circuit having an output coupled to supply said control signal to said control inputs of said pass transistors in the word lines of every SRAM cell and having inputs for receiving address bits from an address decoder on said FPGA and having an input coupled to said distribution network for receiving said power down signal, said gating circuit functioning to generate said control signal in such a way as to turn off said pass transistors when said power down signal is in a logic state indicating power consumption in said SRAM cells is to be minimized.