Patent ID: 8982650
Filing Date: 2015-03-17
Classification: G11C

Abstract:
1. A memory interface circuit that controls capture timing of data provided from a memory in accordance with a strobe signal provided from the memory, the memory interface circuit comprising: a control unit configured to control an activation timing of an internal strobe gate signal, which masks the strobe signal when the internal strobe gate signal is being deactivated, by relatively delaying the internal strobe gate signal by a first period that is shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the internal strobe gate adjustment signal; and a detection unit configured to output a detection signal, wherein the detection unit captures the strobe signal based on the activation timing of the internal strobe gate adjustment signal adjusted by the control unit and outputs the detection signal, when the strobe signal changes from a first potential to a second potential which is higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer; the control unit adjusts the activation timing of the internal strobe gate adjustment signal in accordance with the detection signal.