Patent ID: 8458406
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A memory controller comprising: a table having a plurality of entries, each entry assignable to a respective read memory operation that is outstanding within the memory controller, wherein each entry includes a first indicator indicating whether or not a critical word of a block that is addressed by the respective read memory operation is ready to be forwarded, and wherein each entry includes a second indictor indicating whether or not a plurality of remaining beats of the block are ready to be forwarded; and a read response generator coupled to the table and configured to schedule data transmissions on an interface to the memory controller, wherein the read response generator is configured to schedule a beat of data transmission from a first entry of the plurality of entries in response to: (i) the first indicator in the first entry indicating that the critical word is ready to forward; or (ii) the second indicator indicating that the remaining beats of the block are ready to be forwarded and detecting that no entry of the plurality of entries has a critical word available to forward, and wherein the read response generator is configured to transmit one beat of the remaining words in response to scheduling the first entry to forwarding the remaining words, and wherein the read response generator is configured to re-evaluate the plurality of entries, wherein the read response generator is configured to schedule a different entry having a critical word available to forward during the re-evaluation.