Patent ID: 6424587
Filing Date: 2002-07-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:n (natural number) number of input/output terminals for inputting n number of address signals; a command terminal for inputting a fixing command to fix the address signals to a first or second logic; a plurality of memory cells; a plurality of bit lines corresponding to said plurality of memory cells; a plurality of word lines corresponding to said plurality of memory cells; an inner circuit inputting m number of address signals through m (m: a natural number satisfying nâˆ’m>1) number of input/output terminals among said n number of input/output terminals upon entering a test mode, generating nâˆ’m number of first logical signals fixing each of nâˆ’m number of address signals to a first logic or nâˆ’m number of second logical signals fixing each of said nâˆ’m number of address signals to a second logic based upon said fixing command and outputting n number of inner address signals including said m number of address signals and said nâˆ’m number of first or second logical signals; and a row/column decoder decoding address signals for activating said plurality of bit lines or said plurality of word lines based upon said n number of inner address signals.