Patent ID: 9165646
Filing Date: 2015-10-20
Classification: G11C

Abstract:
1. A resistive memory device, comprising: a memory cell array including a plurality of unit memory cells, and operating in response to a word line driving signal and a column selecting signal, each of the unit memory cells including a resistive device and a compensation resistive device, the resistive device and the compensation resistive device electrically connected in series between a word line to which the word line driving signal is applied and a bit line to which the column selecting signal is applied; an input/output (I/O) sense amplifier unit configured to amplify data output from the memory cell array to generate first data, and to transfer input data to the memory cell array; an address input buffer configured to generate a row address signal and a column address signal based on an external address; a row decoder configured to decode the row address signal and to generate the word line driving signal based on the decoded row address signal; and a column decoder configured to decode the column address signal and to generate the column selecting signal based on the decoded column address signal.