Patent ID: 7288806
Filing Date: 2007-10-30
Classification: H01L,Y10S

Abstract:
1. A DRAM array, comprising: a semiconductor substrate; a plurality of transistor constructions supported by the substrate; each transistor construction including a transistor gate and a pair of source/drain regions, each pair of source/drain regions including a bitline contact source/drain region and a storage node contact source/drain region; a plurality of bitline interconnect stacks over the substrate and electrically connecting to the bitline contact source/drain regions, the bitline interconnect stacks being separated from the storage node contact source/drain regions by at least an electrically insulative layer comprising one or more of aluminum oxide, silicon nitride, silicon oxynitride, and undoped silicon dioxide; the bitline interconnect stacks each comprising: an electrically conductive bitline interconnect line having a first lateral width; the electrically conductive bitline interconnect line having a top surface, a bottom surface, and sidewall surfaces extending between the top and bottom surfaces; an electrically insulative cap over the electrically conductive bitline interconnect line, the electrically insulative cap having a second lateral width which is greater than the first lateral width; and a pair of electrically insulative sidewall spacers covering the sidewalls of the electrically conductive bitline interconnect line; and a plurality of capacitor constructions having storage nodes extending through the electrically insulative layer and in electrical contact with the storage node contact source/drain regions.