Patent ID: 9171518
Filing Date: 2015-10-27
Classification: G09G,H03M

Abstract:
1. A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code, comprising: a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage; and a voltage selector, the voltage selector setting the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code, wherein the one-bit serial charge redistribution digital-to-analog converter includes: an output operational amplifier having a first operational amplifier input coupled to an output of the output operational amplifier and a second operational amplifier input coupled to a charge collection node; a termination capacitor coupled between the charge collection node and the low reference voltage input node; a first capacitor coupled between the low reference voltage input node and a first capacitor charging node; a second capacitor coupled between the low reference voltage input node and a second capacitor charging node; a first switching circuit for coupling the first capacitor charging node to one of the low reference voltage input node and the high reference voltage input node during first capacitor charge cycles in response to instances of a one-bit control code from a sequence of one-bit control codes derived from the M-bit digital input code; a second switching circuit for coupling the second capacitor charging node to one of the low reference voltage input node and the high reference voltage input node during second capacitor charge cycles in response to instances of a one-bit control code from the sequence of one-bit control codes derived from the M-bit digital input code; a third switching circuit for coupling the first capacitor to the charge collection node during the second capacitor charge cycles following the first capacitor charge cycles for charge redistribution with the termination capacitor; and a fourth switching circuit for coupling the second capacitor to the charge collection node during the first capacitor charge cycles following the second capacitor charge cycles for charge redistribution with the termination capacitor.