Patent ID: 6228683
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method for fabricating a high density leaded ball-grid array package for an integrated-circuit die comprising the steps of:laminating top and bottom sides of a non-conductive layer with respective first and second conductive trace patterns so as to form a laminated substrate;directly attaching a leadframe, which has a plurality of conductor leads and a centrally-located open portion, onto the first conductive trace pattern of the laminated substrate by a non-conductive adhesive so that the open portion of the leadframe overlies a central region of the laminated substrate;mounting an integrated-circuit die in the central region of the laminated substrate;interconnecting bonding wires between bonding pads on the integrated-circuit die and bonding fingers formed on the lead frame;molding a plastic material over the top surface of the die, bonding fingers and bonding wires;applying a solder mask on the second conductive trace pattern so as to form selectively solderable areas for attachment of solder balls; andattaching solder balls to the selectively solderable areas.