Patent ID: 8102479
Filing Date: 2012-01-24
Classification: G02F,H01L

Abstract:
1. A thin film transistor display panel comprising: an insulating substrate; gate lines disposed on a first surface of the insulating substrate and extended in a first direction; data lines disposed on the first surface of the insulating substrate and extended in a second direction substantially perpendicular to the first direction, the data lines and the gate lines being electrically insulated from each other; common lines disposed on the insulating substrate and extended substantially in parallel to the gate lines; a gate insulating film disposed on the gate lines and the common lines; contact holes disposed through the gate insulating film and exposing a portion of the common lines; a plurality of common electrodes electrically connected to the common lines through the contact holes, arranged extended in the second direction and disposed substantially in parallel to each other; a plurality of pixel electrodes arranged extended substantially in parallel to the common electrodes; and thin film transistors each including a gate electrode connected to the gate lines, a source electrode connected to the data lines, and a drain electrode connected to the pixel electrodes, wherein a first thickness of the common electrodes and of the pixel electrode, is smaller than a second thickness of the data lines, the first and second thicknesses taken in a third direction substantially perpendicular to the first surface of the insulating substrate, and a third thickness of the drain electrode is smaller than a fourth thickness of the source electrode, the third and fourth thicknesses taken in the third direction substantially perpendicular to the first surface of the insulating substrate.