Patent ID: 6344965
Filing Date: 2002-02-05
Classification: H01L

Abstract:
A capacitor for a semiconductor memory device, comprising:a semiconductor substrate having an impurity layer exposed at a top surface; an interlayer insulation film on the semiconductor substrate having a first contact hole with a first diameter therethrough filled with a conductive material, wherein an inner end portion of the contact hole is coupled to the impurity layer; a patterned first oxide film on the interlayer insulation film; a patterned nitride film on the first oxide film, wherein a second contact hole having a second diameter approximately equal to the first diameter passes through the patterned first oxide film and the patterned nitride film to expose an outer end portion of the conductive material in the first contact hole; a patterned second oxide film on the nitride film having a third contact hole therethrough with a third diameter greater than the second diameter to expose the second contact hole; a diffusion barrier film formed on side portions of the second oxide film, side portions of the nitride film, side portions of the first oxide film, and the outer end portion of the contact hole; a first electrode on the diffusion barrier film; a dielectric film on outer portions of the second oxide film, outer portions of the diffusion barrier film, and the first electrode; and a second electrode on the dielectric film.