Patent ID: 8946884
Filing Date: 2015-02-03
Classification: H01L,H05K

Abstract:
1. A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, comprising: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to at least some of the plurality of metal segments in the bottom most layer; and a passivation layer having one or more openings that correspond spatially with the one or more openings at the dielectric layer, wherein the passivation layer is formed on the dielectric layer.