Patent ID: 6487711
Filing Date: 2002-11-26
Classification: G03F

Abstract:
A method of analyzing factor responsible for errors in a wafer pattern formed on a semiconductor wafer, the method comprising the steps of:placing a first mask in a first position within an etching chamber; forming a mask pattern by etching the first mask; placing a second mask in a second position within the etching chamber such that an overlap region exists between a portion of the first mask and a portion of the second mask, provided that the first mask is set in the first position; forming a mask pattern by etching the second mask; forming a wafer pattern corresponding to a single shot region on the semiconductor wafer by exposing the semiconductor wafer through use of the first mask; forming a wafer pattern corresponding to a single shot region on the semiconductor wafer by exposing the semiconductor wafer through use of the second mask; and detecting a dimensional difference ascribable to a difference between mask patterns and a dimensional difference ascribable to another reason while distinguishing the dimensional differences from each other, by comparison between the size of the wafer pattern which is included in an area (first overlap region) within the single shot region formed through use of the first mask and which corresponds to the overlap region and the size of the wafer pattern which is included in an area (second overlap region) within the single shot region formed through the second mask and which corresponds to the overlap region.