Patent ID: 8110414
Filing Date: 2012-02-07
Classification: H01L

Abstract:
1. A method of forming integrated circuit (IC) devices having at least one Metal Insulator Metal (MIM) capacitor, comprising: providing a substrate having a semiconductor surface; forming a bottom electrode layer on a predetermined region of said semiconductor surface; forming a dielectric stack comprising capping silicon oxide/silicon oxynitride/bottom silicon oxide, wherein a thickness of said dielectric stack is between 150 and 400 angstroms; forming a top electrode layer comprising Ti on said dielectric stack, forming a patterned soft masking layer on said top electrode layer; etching said top electrode layer with exclusively a dry etch process outside said patterned soft masking layer using a first halogen comprising gas comprising Cl 2 , a second halogen comprising gas that comprises fluorine, and a carrier gas comprising a noble gas to reach said dielectric stack, wherein said dry-etching provides an etch selectivity for said top electrode layer to said capping silicon oxide of ≧8:1 and said dry-etching removes ≦75 A of said capping silicon oxide.