Patent ID: 6622103
Filing Date: 2003-09-16
Classification: G01R

Abstract:
A method for calibrating timing of an integrated circuit (IC) tester and an interconnect system for connecting the IC tester to input/output (I/O) terminals of an IC implemented on a semiconductor wafer,wherein the IC tester includes a plurality of tester channels for testing the IC implemented on the semiconductor wafer, wherein the tester also includes a spare channel, wherein the tester includes means for sending a sequence of clock signal edges to the tester channels and to the spare channel, wherein the tester channels and the spare channel each include means for generating an output signal having an edge following receipt of any of said clock signal edges with a drive delay including a programmable drive delay and an adjustable drive calibration delay and for sampling an input signal following any of said clock signal edges with a compare delay including a programmable compare delay and an adjustable compare calibration delay, and wherein the interconnect system contacts said IC to provide a first conductive path between each said I/O terminal and a corresponding one of said tester channels for conveying signals therebetween, the method comprising the steps of: a. adapting said interconnect system to provide a second conductive path; b. providing a plurality of first conductors, each corresponding to a separate one of said tester channels; and c. for each tester channel of said plurality of tester channels: c1. causing said interconnect system to contact the tester channel's corresponding first conductor, wherein the corresponding first conductor and the first and second conductive paths form a first signal path between said tester channel and said spare channel, c2. causing said tester channel to repeatedly send its output signal as an input signal to said spare channel via said first signal path, and c3. concurrent with substep c2, causing said spare channel to sample its input signal with a fixed delay following said clock signal edges.