Patent ID: 6262616
Filing Date: 2001-07-17
Classification: H03F,H03K,H03M

Abstract:
An apparatus comprising:a delay stage to receive an input signal and to generate an output signal which is delayed from the input signal by a predetermined delay;a bias circuit coupled to said delay stage to control a delay stage current in said delay stage, in which a supply voltage to said delay stage and the delay stage current determine the predetermined delay;said bias circuit coupled to the supply voltage to provide a bias current having a fixed component and a variable component, wherein the fixed component of the bias current remains constant when the supply voltage varies, but the variable component of the bias current changes proportionately to the variation in the supply voltage; andthe bias current coupled to control the delay stage current to adjust the delay stage current proportionately to variations in the supply voltage to minimize changes in the predetermined delay when the supply voltage varies.