Patent ID: 7579861
Filing Date: 2009-08-25
Classification: H03K

Abstract:
1. An impedance-controlled pseudo-open drain output driver circuit, comprising: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal having at least one pull-up select signal and at least one pull-down select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal having the at least one pull-up select signal and the at least one pull-down select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.