Patent ID: 9171870
Filing Date: 2015-10-27
Classification: G09G,H01L

Abstract:
1. A semiconductor device comprising: a first transistor comprising a first gate, a first source, and a first drain; a second transistor comprising a second gate, a second source, and a second drain; a third transistor comprising a third gate, a third source, and a third drain; a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain; a fifth transistor comprising a fifth gate, a fifth source, and a fifth drain; a sixth transistor comprising a sixth gate, a sixth source, and a sixth drain; a capacitor comprising a first electrode and a second electrode; a third electrode; an organic insulating layer over the third electrode, the organic insulating layer having an opening; an EL layer over the organic insulating layer; a fourth electrode over the EL layer; and a layer over the fourth electrode, the layer comprising silicon and nitrogen, wherein the first gate is directly connected to a first gate signal line, wherein one of the first source and the first drain is directly connected to the first electrode, wherein one of the first source and the first drain is directly connected to one of the fifth source and the fifth drain, wherein the other of the first source and the first drain is directly connected to a source signal line, wherein one of the second source and the second drain is electrically connected to the second electrode, wherein the one of the second source and the second drain is electrically connected to the third gate, wherein the other of the second source and the second drain is electrically connected to one of the third source and the third drain, wherein the one of the third source and the third drain is directly connected to one of the fourth source and the fourth drain, wherein the other of third source and the third drain is directly connected to a first wiring, wherein the fourth gate is directly connected to a second gate signal line, wherein the other of the fourth source and the fourth drain is directly connected to the third electrode, wherein the sixth gate is directly connected to a third gate signal line, wherein one of the sixth source and the sixth drain is electrically connected to the third electrode, wherein the other of the sixth source and the sixth drain is directly connected to a second wiring, wherein the third electrode is overlapped with a channel formation region of the first transistor, and wherein the layer overlaps with the channel formation region of the first transistor.