Patent ID: 8488374
Filing Date: 2013-07-16
Classification: G01R,G11C,H01L,H05K

Abstract:
1. A memory array, comprising: global bitlines extending along a first horizontal direction; the global bitlines comprising a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level; the global bitlines of the first series alternating with the global bitlines of the second series; vertical local bitlines extending perpendicularly to the global bitlines; wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction; the wordlines being stacked in a two-dimensional array comprising vertical columns and horizontal rows; the vertical columns of the wordline array comprising two or more wordlines; the vertical local bitlines extending through the wordline array so that vertical local bitlines are between adjacent vertical columns of the wordline array; and memory cell material directly between the wordlines and the vertical local bitlines; the memory cell material forming a plurality of memory cells uniquely addressed by wordline/global bitline combinations.