Patent ID: 8673704
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method for manufacturing a FinFET, comprising: forming an etching stop layer on a semiconductor substrate; forming a semiconductor fin on the etching stop layer; forming a gate dielectric layer on the semiconductor fin and on the etching stop layer; removing a portion of the gate dielectric layer and a portion of the etching stop layer to expose the corresponding portion of the surface of the semiconductor substrate; forming an interlayer insulating layer on the exposed surface of the semiconductor substrate and below a portion of the gate dielectric layer so that the interlayer insulating layer adjoins the etching stop layer below the gate dielectric layer; forming a gate conductor on the gate dielectric layer and on the interlayer insulating layer, wherein the gate conductor covers at least two side surfaces of the semiconductor fin; and forming a source region and a drain region by implanting ions at two ends of the semiconductor fin.