Patent ID: 6486706
Filing Date: 2002-11-26
Classification: H03K

Abstract:
A circuit, comprising:a clock transistor coupled between a dynamic output node and a first supply voltage, a gate of the clock transistor coupled to receive a clock signal; an inverter, an input of the inverter connected to the dynamic output node; a level keeper transistor coupled between the dynamic output node and the first supply voltage, a gate of the level keeper transistor coupled to an output of the inverter; a pull-down circuit connected between the dynamic output node and a second supply voltage; a static CMOS circuit, an input of the static CMOS circuit connected to the dynamic output node; a pull-up circuit connected between an output of the static CMOS circuit and the first supply voltage; and an output predischarge transistor coupled between the output of the static CMOS circuit and the second supply voltage, a gate of the output predischarge transistor connected to receive a clock signal.