Patent ID: 8338255
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. A method of making a semiconductor device comprising: forming a first etch mask on an n-type source layer, wherein the n-type source layer is on an n-type isolation layer, wherein the n-type isolation layer is on a p-type buried gate layer, wherein the p-type buried gate layer is on an n-type drift layer, wherein the n-type drift layer is on an n-type buffer layer and wherein the n-type buffer layer is on an n-type substrate; selectively etching through the source and isolation layers and into the buried gate layer using the first etch mask to form raised source regions having upper surfaces and sidewalls and exposing buried gate layer adjacent the raised source regions; positioning a second etch mask on exposed buried gate layer in a peripheral portion of the device; selectively etching through the buried gate layer using the first and second etch masks to expose n-type drift layer adjacent the raised source regions thereby forming trenches adjacent and between the raised source regions and a region of p-type material in the peripheral portion of the device having an upper surface and sidewalls, wherein the p-type material in the raised source regions is in contact with the region of p-type material in the peripheral portion of the device; removing the first and second etch masks; epitaxially growing an n-type channel layer on the upper surfaces and sidewalls of the raised source regions, on the exposed surfaces of the drift layer adjacent the raised source regions and on the region of p-type material in the peripheral portion of the device; selectively etching the n-type channel layer to expose the source layer on the upper surfaces of the raised source regions, the drift layer adjacent the raised source regions and the upper surface of the region of p-type material in the peripheral portion of the device; epitaxially growing a p-type gate layer on the upper surfaces of the raised source regions, on the n-type channel layer on the sidewalls of the raised source regions, on the exposed surfaces of the drift layer and on the region of p-type material in the peripheral portion of the device; depositing a first planarizing material on the p-type gate layer such that the first planarizing material fills the trenches adjacent and between the raised source regions; etching the first planarizing material to remove the epitaxially grown p-type gate layer from the upper surfaces of the raised source regions; removing the first planarizing material; depositing an oxide layer on the sidewalls of the raised source regions; forming ohmic contacts on the upper surfaces of the raised source regions, on the epitaxially grown p-type gate layer adjacent the raised source regions and on the epitaxially grown p-type gate layer in the peripheral region of the device; forming an ohmic contact on the substrate layer opposite the buffer layer; depositing etch mask material on the ohmic contact material on the epitaxially grown p-type gate layer and on the ohmic contact material on the upper surfaces of the raised source regions such that epitaxially grown channel and gate layer on the sidewalls of the raised source regions is not masked; filling the trenches adjacent and between the raised source regions with a second planarizing material; etching the second planarizing material to remove the epitaxially grown p-type gate and n-type channel layers from an upper portion of the sidewalls of the raised source regions; removing the second planarizing material and the etch mask material; filling the trenches adjacent and between the raised source regions with a third planarizing material; etching the third planarizing material to expose ohmic contact material on the upper surfaces of the raised source regions; selectively etching through the third planarizing material in the peripheral portion of the device to expose ohmic contact material on the epitaxially grown p-type gate layer; forming metal contacts on the ohmic contacts on the upper surfaces of the raised source regions; forming a metal contact on the ohmic contact on the epitaxially grown p-type gate layer in the peripheral portion of the device; and forming a metal contact on the ohmic contact on the substrate layer.