Patent ID: 6424279
Filing Date: 2002-07-23
Classification: H03M

Abstract:
A sigma-delta analog-to-digital converter having an optional anti-aliasing filter, an optional sample and hold circuit, a sigma-delta modulator and an optional decimation filter, comprising:an overload estimating unit for judging the saturation or overload of an analog integrator; a mixed mode integrator which has an analog integrator and a digital integrator composed of a digital adder and a digital storing unit and integrates the output of said overload estimating unit in analog or digitally; and a quantization unit for converting the output of said mixed mode integrator to a digital signal, wherein said quantization unit comprises a 1 bit A/D converter for A/D converting 1 bit of the output of said analog integrator and feedback the A/D converted bit in analog to said overload estimating unit; a N bit A/D converter for A/D converting N bits of the output of said analog integrator; a first digital adder for adding the output of said N bit A/D converter to the output of said digital integrator; and a second digital adder for adding the output of said 1 bit A/D converter to the final output of the modulator and digitally feedback the sum to said overload estimating unit, an N-th order sigma-delta modulator having N overload estimating units and N mixed mode integrators.