Patent ID: 6686656
Filing Date: 2004-02-03
Classification: H01L

Abstract:
An integrated chip scale package assembly comprising at least first and second chip scale packages disposed one above the other, wherein the first of said first and second chip scale packages includes an integrated circuit chip,a substrate to which said integrated circuit chip is bonded, said substrate having top and bottom sides and an extension that projects outwardly and beyond the integrated circuit chip, a plurality of solder ball bonding pads located at the bottom side of the substrate, a plurality of perimeter wire bonding pads located on the substrate extension, electrically conductive signal traces located on said substrate and interconnected between said integrated circuit chip and said plurality of perimeter wire bonding pads, and an array of solder ball interconnects attached to respective ones of said plurality of solder ball bonding pads at the bottom side of said substrate by which said first chip scale package is adapted to be attached to a printed wiring board.