Patent ID: 6466067
Filing Date: 2002-10-15
Classification: H03L,Y10S

Abstract:
A PLL circuit comprising:a phase comparator which outputs, as a phase difference signal, a difference in phase between first and second input signals, a loop filter which smoothens said phase difference signal and outputs a smoothened voltage output; VCO (voltage control oscillator) which receives as input the smoothened voltage output from the loop filter and oscillates at a frequency depending upon said smoothened voltages output; a mixer which is provided between said VCO and the phase comparator and generates, as the second input signal, a signal of which a target frequency is the frequency of the first input signal; a detector which detects, based on said phase differential signal output from the phase comparator, whether or not PLL (phase-lock loop) lock is possible, wherein the detector comprises a band pass filter which has a band width corresponding to a difference in frequency between the first and second input signals and receives as input said phase differential signal output from the phase comparator, and a differential pair circuit which receives as input a voltage signal output from the band pass filter and outputs a voltage corresponding to a voltage signal output received from said band pass filter; and switch means which, when the detector has detected that PLL lock is impossible, switches the loop filter so that the response of the loop filter is enhanced.