Patent ID: 8149605
Filing Date: 2012-04-03
Classification: G11C

Abstract:
1. An analog memory circuit comprising: a memory capacitor connected at a first end to a first port, the first port for being connected to a reference potential; a first transistor, a drain of the first transistor being connected to a second end of the memory capacitor, a source of the first transistor being connected to a second port, the second port for being connected to circuitry for providing an input signal for storage in the memory capacitor, and a gate of the first transistor being connected to a third port, the third port for being connected to a first current sink; a second transistor, a source of the second transistor being connected to the source of the first transistor and a drain of the second transistor being connected to the gate of the first transistor; and, a third transistor, a source of the third transistor being connected to the source of the first transistor, a gate and a drain of the third transistor being connected together to a gate of the second transistor and to a fourth port, the fourth port for being connected to a second current sink.