Patent ID: 6608499
Filing Date: 2003-08-19
Classification: G11C

Abstract:
A method for compensating a threshold voltage of a neighbor bit in a flash memory including a plurality of trapping devices wherein each of which has two bits, the method comprising:arbitrating word line voltages of the bits which are to be programmed according to threshold voltages of neighbor bits adjacent to the bits which are to be programmed; first distributing the bits, to which a first word line voltage should be applied, to a first group of bits with a same word line voltage; first applying the first word line voltage to the bits of the first group of bits with the same word line voltage in accordance with the result of the first distribution; second distributing the bits, to which a second word line voltage should be applied, to a second group of bits with a same word line voltage; and second applying the second word line voltage to the bits of the second group of bits with the same word line voltage in accordance with the result of the second distribution.