Patent ID: 6013574
Filing Date: 2000-01-11
Classification: H01L

Abstract:
A method of forming an opening through an interlevel dielectric to an underlying interconnect line, comprising:providing a coated interconnect line extending partially across an upper topography of a silicon substrate, and further providing an interlevel dielectric across said interconnect line and said upper topography;applying a photoresist layer across said interlevel dielectric;selectively removing said photoresist layer and underlying said interlevel dielectric to expose a portion of the coated interconnect line;plasma etch removing an etch byproduct polymer formed upon the exposed said portion of the coated interconnect line; andsputter etch removing a native oxide layer formed upon the exposed said portion of the coated interconnect line for a time period required to remove approximately 200 angstroms or more of said native oxide layer.