Patent ID: 8269530
Filing Date: 2012-09-18
Classification: H03K

Abstract:
1. A frequency doubler, comprising: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and a second non-overlapping signal, each of the first and second non-overlapping signals having a frequency of the first signal, wherein an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal; wherein the non-overlapping signal generation circuit comprises: wherein the input module is further configured to receive the first and second delayed signals and generate the first and second clock signals according to the first signal, the first delayed signals and the second delayed signal; and an output module, configured to receive the first delayed signal and generate the first non-overlapping signal accordingly, receive the second delayed signal and generate the second non-overlapping signal accordingly.