Patent ID: 7467177
Filing Date: 2008-12-16
Classification: G06F

Abstract:
1. A DSP slice in an array of DSP slices comprising: a first operand input port for receiving a first signed operand, the first signed operand including a first sign bit; a second operand input port for receiving a second signed operand, the second signed operand including a second sign bit; wherein the first signed operand is a value selected from a group consisting of an upstream-output-cascade value from another DSP slice upstream from the DSP slice, a concatenated value of another first signed operand and another second signed operand from the other DSP slice upstream from the DSP slice, a partial product value from the other DSP slice upstream from the DSP slice, a product value from the other DSP slice upstream from the DSP slice, and an output value from the other DSP slice upstream from the DSP slice; a third operand input port for receiving a rounding constant; a product generator having: a correction circuit having: