Patent ID: 6114208
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method for fabricating a complementary MOS device having a first and second MOS transistors, comprising:forming well regions of first and second conductivity types on a semiconductor substrate, the first and second MOS transistors respectively formed on the well regions of the first and second conductivity types;forming a field oxide layer on the substrate;forming first and second source/drain electrode structures on the well regions of first and second conductivity types, respectively;forming a first spacer on both side walls of the first source/drain electrode structure, the first spacer being doped with impurity ions of the second conductivity type;forming a second spacer on both side walls of the second source/drain electrode structure, the second spacer being doped with impurity ions of the first conductivity type;forming first and second gate oxide layers on the well regions of first and second conductivity type by oxidizing surfaces of the spacers at a predetermined temperature;forming source/drain electrodes n the first and second source/drain electrode structures; andforming gate electrodes on the first and second gate oxide layers;wherein forming the first and second source/drain electrode structures includes:forming a first insulating layer on the substrate;forming a first conductive layer on the first insulating layer;forming a second conductive layer on the first conductive layer; andforming a second insulating layer on the second conductive layer.