Patent ID: 6512245
Filing Date: 2003-01-28
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit device, comprising:a first n-channel MISFET and a second n-channel MISFET, each formed on a semiconductor substrate and having a gate electrode formed over said substrate and extending over a channel-forming region thereof; a first p-channel MISFET and a second p-channel MISFET, each formed on said substrate and having a gate electrode formed over said substrate and extending over a channel-forming region thereof; a first conductive strip extending over said substrate, a drain region of said first n-channel MISFET, and a drain region of said first p-channel MISFET, said first conductive strip being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second p-channel MISFET; a second conductive strip extending over said substrate, a drain region of said second n-channel MISFET, and a drain region of said second p-channel MISFET, said second conductive strip being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET; a dielectric film extending over said first conductive strip and said second conductive strip, and said gate electrodes of said first and second p-channel MISFETs; and a first power voltage line formed on said dielectric film and extending over said first conductive strip, said second conductive strip, and said gate electrodes of said first and second p-channel MISFETs, wherein a first capacitor element is comprised of said first conductive strip, said dielectric film, and said first power voltage line, and wherein a second capacitor element is comprised of said second conductive strip, said dielectric film, and said first power voltage line.