Patent ID: 6604203
Filing Date: 2003-08-05
Classification: H04L

Abstract:
An apparatus for synchronizing an incoming stream of data, comprising parallel data elements, to a local clock for reading of said parallel data elements by a data read device, said apparatus comprising:a) a data read error detecting device comprising a first error detection circuit for sampling at least one element of said incoming stream of data at a first clock edge of said local clock and for detecting whether a data read error has occurred while sampling at said first clock edge, and a second error detection circuit for sampling said at least one element at a second clock edge of said local clock and for detecting whether a data read error has occurred while sampling at said second clock edge, wherein each said error detection circuit comprises: a first circuit for sampling said at least one element at one said clock edge, said first circuit including a data flip-flop that outputs a first signal value during the sampling by said first circuit; a second circuit coupled to said first circuit for using said first signal value to generate an error signal when said data read error has occurred, said second circuit comprising a first and second comparator circuit for comparing said first signal value to a first and second switch voltage, respectively, and for outputting a first and second comparator output result, respectively, and an exclusive-or logic device for generating said error signal when said first and second comparator output results are different; and b) a decision making device coupled to said data read error detecting device for using said error signal to select one said clock edge, wherein if a data read error is detected while sampling said at least one element using one said clock edge, said decision making device selects the other clock edge for reading of said parallel data elements by said data read device.