Patent ID: 7235437
Filing Date: 2007-06-26
Classification: H01L

Abstract:
1. A method for forming a multi-planar layout thin-film transistor (TFT) inverter circuit, the method comprising: forming a P-channel top drain vertical (TDV)-TFT with a gate having a length, and a width greater than the length, a first source/drain (S/D) region in a first horizontal plane, and a second S/D) region in a second horizontal plane, different than the first horizontal plane, as viewed in a vertical cross-section; forming an N-channel TDV-TFT, adjacent the P-channel TFT, with a gate having a length, and a width greater than the length, a third S/D region in a third horizontal plane, and a fourth S/D region in the second horizontal plane, different than the third plane wherein forming P and N-channel TDV-TFTs includes: