Patent ID: 6320415
Filing Date: 2001-11-20
Classification: H03K

Abstract:
A CMOS input/output control circuit capable of tolerating different input voltages, comprising:a NAND gate, wherein one input terminal of the NAND gate is an output enable signal terminal, and another input terminal of the NAND gate is an output signal terminal;an inverter, wherein an input terminal of the inverter is connected to the output enable signal terminal;a NOR gate, wherein one input terminal of the NOR gate is the output signal terminal, and another terminal of the NOR gate is connected to the output terminal of the inverter;a PMOS transistor, wherein a source terminal of the PMOS transistor is connected to a source voltage, and a drain terminal of the PMOS transistor is connected to an input/output pad;an NMOS transistor, wherein a source terminal of the NMOS transistor is connected to a low potential, a drain terminal of the NMOS transistor is connected to the input/output pad, and a gate terminal of the NMOS transistor is connected to the output terminal of the NOR gate;a first NMOS transistor, wherein a drain terminal and a gate terminal of the first NMOS transistor are connected to the source voltage;a first PMOS transistor, wherein a source terminal of the first PMOS transistor is connected to the drain terminal of the first NMOS transistor, and a drain terminal and a n-well of the first PMOS transistor are connected to a source terminal of the first NMOS transistor as well as a n-well of the PMOS transistor;a second PMOS transistor, wherein a gate terminal of the second PMOS transistor is connected to the source voltage, a source terminal of the second PMOS transistor is connected to the input/output pad, and a drain terminal and a n-well of the second PMOS transistor are connected to the drain terminal of the first PMOS transistor;a third PMOS transistor, wherein a n-well of the third PMOS transistor is connected to the drain terminal of the first PMOS transistor, and a source terminal of the third PMOS transistor is connected to the output signal terminal of the NAND gate;a second NMOS transistor, wherein a drain terminal of the second NMOS transistor is connected to the source terminal of the third PMOS transistor, a source terminal of the second NMOS transistor is connected to a drain terminal of the third PMOS transistor as well as a gate terminal of the PMOS transistor, and a gate terminal of the second NMOS transistor is connected to the source voltage;a fourth PMOS transistor, wherein a n-well of the fourth PMOS transistor is connected to the drain terminal of the first PMOS transistor, a gate terminal of the fourth PMOS transistor is connected to the source voltage, a drain terminal of the fourth PMOS transistor is connected to the drain terminal of the third PMOS transistor, and a source terminal of the fourth PMOS transistor is connected to the input/output pad;a fifth PMOS transistor, wherein a gate terminal of the fifth PMOS transistor is connected to the source voltage, a n-well of the fifth PMOS transistor is connected to the drain terminal of the first PMOS transistor, a drain terminal of the fifth PMOS transistor is connected to a gate terminal of the third PMOS transistor as well as a gate terminal of the first PMOS transistor, and a source terminal of the fifth PMOS transistor is connected to the input/output pad; anda third NMOS transistor, wherein a gate terminal of the third NMOS transistor is connected to the source voltage, a drain terminal of the third NMOS transistor is connected to the gate terminal of the third PMOS transistor, and the source terminal of the third NMOS transistor is connected to the input/output pad.