Patent ID: 6553478
Filing Date: 2003-04-22
Classification: G06F

Abstract:
Memory circuitry for a computer system, comprising:a plurality of memory banks forming at least part of a mapped memory space of the computer system, a first part of said memory space providing an interleaved memory region formed by each of said plurality of memory banks so that data is stored in each of said plurality of memory banks within said interleaved memory region, a second part of said memory space providing an X memory region using at least one of said plurality of memory banks, and a third part of said memory space providing a Y memory region using each memory bank of said plurality of memory banks not used in said X memory region, wherein each of said interleaved memory region, said X memory region and said Y memory region are separately mapped within said memory space; circuitry to generate an access address and an indication of whether a memory access is an interleaved access or an X or Y access, wherein said access address includes a most significant set of bits which indicate which of said interleaved memory region, said X memory region or said Y memory region is to be accessed, and a least significant set of bits which include an indication of an address within a memory bank of the accessed memory region, at least one bit within said least significant set of bits selecting one memory bank within an accessed memory region if the accessed memory region has more than the one memory bank, and one bit within said most significant set of bits indicating selectively said X memory region or said Y memory region during the X or Y access; and memory access circuitry arranged to selectively access said memory space in response to said access address.