Patent ID: 9042157
Filing Date: 2015-05-26
Classification: G11C

Abstract:
1. A memory device comprising at least one memory cell comprising: a first transistor coupled between a first storage node and a first supply line; a second transistor coupled between a second storage node and said first supply line, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; a third transistor coupled between said first storage node and a first access line and controllable via a first control line; a fourth transistor coupled between said second storage node and a second access line and controllable via a second control line; and a first resistance switching element programmable to have one of first and second resistive states, wherein said first resistance switching element and said first and third transistors are coupled in series; and a second resistance switching element programmable to have one of first and second resistive states, wherein said second resistance switching element and said second and fourth transistors are coupled in series.