Patent ID: 9038965
Filing Date: 2015-05-26
Classification: B61L

Abstract:
1. A method of sequentially monitoring a plurality of track circuits for an interlocking logic system and a track circuit system including said track circuits, each of said track circuits having a state, said method comprising: interfacing between said interlocking logic system and said track circuit system; normally passing inputs from said track circuit system to outputs to said interlocking logic system; monitoring the state of each of said track circuits by a processor; validating a sequence of state changes of said track circuits by said processor; interrupting and correcting invalid track circuit state indications by said processor between said track circuit system and said interlocking logic system; and applying a quarantine by said processor to a minimum of three of said track circuits in a quarantined area when an out of sequence event is detected by said processor, wherein said out of sequence event is caused by one of said three of said track circuits changing state from occupied to unoccupied without an adjacent one of said three of said track circuits having an occupied state, wherein said quarantine forces a state of said one said three of said track circuits as received by said interlocking logic system to be occupied, thereby inhibiting use of an unoccupied track circuit in the quarantined area.