Patent ID: 6639920
Filing Date: 2003-10-28
Classification: H04J,H04L,H04Q

Abstract:
A packet switching system comprising:a plurality of first modules, wherein each first module includes a controller and a first memory storing information of a destination of information to be received, wherein a destination of received information is determined by said controller based on content of said first memory, and when said destination is determined to be another first module different from said first module, said first module converts said received information to a fixed-length packet having a header and an information field and outputs said fixed-length packet to said another first module; a second module having a switch which interconnects said plurality of first modules together, wherein said second module outputs said fixed-length packet received from said first module to said another first module which is said destination of said received information; and a collision preventing circuit which controls transmission and reception timings of fixed-length packets among said first modules and said second module so that fixed-length packets transmitted among said first modules and said second module do not collide against each other in said second module.