Patent ID: 6233647
Filing Date: 2001-05-15
Classification: G06F

Abstract:
In a computer system, a method of caching data stored in a first region of memory, the method comprising the steps of:a) mapping said first region of memory to a second region of memory according to a predetermined address-hashing scheme, wherein said first region of memory is addressed in a tiled format by a multi-dimensional index and said second region of memory is addressed by a cache address, and wherein said step (a) includes the steps of:a1) selectively hashing higher order bits of said multi-dimensional index to generate said cache address, said higher order bits comprising higher order bits from a first dimension of said multi-dimensional index and higher order bits from a second dimension of said multi-dimensional index, wherein one dimension of said multi-dimensional index is held constant while another dimension of said multi-dimensional index is varied throughout its entire range; anda2) using lower order bits of said multi-dimensional index to address individual texels within a texel tile in said second region of memory; andb) storing said data within said second region of memory.