Patent ID: 6700155
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A semiconductor structure comprising:a dielectric trapping layer located proximate to a transistor channel, which transistor channel is capable of carrying a current that varies from a first current value associated with a conducting condition for the transistor channel, to a second current value associated with a non-conducting condition for said transistor channel channel, said second current value being substantially less than said first current value; a plurality of carrier trapping sites within said dielectric layer, said carrier trapping sites being configured for trapping carriers that are electrically biased by an electrical control field to move from said channel into said dielectric layer; wherein said said trapping sites have a concentration and arrangement within said dielectric layer so that said current in said transistor channel can be varied between said first current value and said second current value by the action of said trapping sites adjusting said current in accordance with a value of said electrical control field.