Patent ID: 7648872
Filing Date: 2010-01-19
Classification: H01L

Abstract:
1. A method of forming a DRAM array, comprising: providing a semiconductor construction within an etching chamber, the semiconductor construction comprising a plurality of transistors over a semiconductor substrate; individual of the transistors comprising paired source/drain regions; forming silicon oxide-containing material over the transistors; forming a patterned carbon-containing mask over the silicon oxide-containing material; the patterned carbon-containing mask having a plurality of openings extending therethrough; the patterned carbon-containing mask comprising transparent carbon; flowing etching materials into the chamber, the etching materials consisting of helium, carbon monoxide, oxygen, one or more fluorocarbons, and O utilizing the etching materials to extend the openings into the silicon oxide-containing material to form containers in the silicon oxide-containing material having aspect ratios of at least about 20:1; the containers being directly over source/drain regions of the transistors; forming first capacitor electrode material within the openings; forming dielectric material within the openings and over the first capacitor electrode material; forming second capacitor electrode material within the openings and over the dielectric material; the first and second capacitor electrode materials, together with the dielectric material, forming a plurality of capacitors within the plurality of the openings; individual capacitors being electrically coupled with the individual source/drain regions of the transistors; and forming bitlines in electrical connection with source/drain regions of the transistors; individual transistors having one source/drain region of the paired source/drain regions electrically coupled with a bitline of the plurality of bitlines, and having the other source/drain region of the paired source/drain regions electrically coupled with a capacitor of the plurality of capacitors.