Patent ID: 6429110
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A method of forming a transistor, comprising:providing a substrate; covering said substrate by a doped amorphous polysilicon layer and a barrier layer in sequence, and removing part of said barrier layer and part of said doped amorphous polysilicon layer in sequence to form a hole which exposes part of said substrate, wherein said hole is corresponding to a location of a gate of said transistor; forming a dielectric layer on both said barrier layer and said hole, said hole being not totally filled by said dielectric layer, wherein said dielectric layer can be used to form a gate dielectric layer of said transistor; forming a conductor layer on both said dielectric layer, wherein said hole is not totally filled by both said conductor layer and said dielectric layer; forming a metal layer on said conductor layer; performing a planarizing process by using said barrier layer as a stop layer; and removing said barrier layer.