Patent ID: 6470417
Filing Date: 2002-10-22
Classification: G06F

Abstract:
An apparatus for emulating a first DRAM component having a first storage capacity, said first DRAM component being accessed by receiving an address signal from a controller together with DRAM control signals, said address signal including a first number of address bits, said first number of address bits including a first plurality of row address bits and a first plurality of column address bits, said apparatus comprising:an integrated circuit component including a plurality of second DRAMs, each of said plurality of second DRAMs having a second storage capacity, said second storage capacity being lower than the first storage capacity, wherein the cumulative total of said second storage capacities for said plurality of second DRAMs is at least equal to said first storage capacity, and wherein each of said plurality of second DRAMs may be accessed by receiving a second number of address bits from said address signal provided by said controller together with said DRAM control signals, said second number of address bits being less than said first number of address bits; and a decoder having at least one first input for receiving a number of decode bits from said address signal provided by said controller, said number of decode bits including at least one of said first plurality of row address bits and at least one of said first plurality of column address bits, said number of decode bits being equal to the difference between the first number of address bits and the second number of address bits, said decoder further having at least one second input for receiving at least one of said DRAM control signals, said decoder decoding said at least one of said first plurality of row address bits to direct the output of said at least one DRAM control signal to activate a group of second DRAMs within said plurality of second DRAMs, and said decoder decoding said at least one of said first plurality of column address bits to deactivate all but one second DRAM within said group of second DRAMs and permit access to said one second DRAM.