Patent ID: 6493812
Filing Date: 2002-12-10
Classification: G06F

Abstract:
An apparatus to support address aliasing in a computer architecture having a prevalidated tag cache, comprising:a translation lookaside buffer (TLB), comprising: a virtual address content addressable memory (CAM) that receives virtual address information for a new TLB entry; a physical address CAM that receives physical address information for the new TLB entry; and a valid bit module that provides valid bits, wherein the TLB holds physical address information for current TLB entries in one or more TLB slots, wherein the physical address CAM compares the physical address information of the new TLB entry with the physical address information of each of the current TLB entries and provides an output signal, wherein the output signal is input to the valid bit module, and wherein when the compare yields a match between the physical address information of the new TLB entry and the physical address information of one or more of the current TLB entries, the output signal will cause a valid bit associated with a matching current TLB entry to clear making the matching current TLB entry invalid.