Patent ID: 6298397
Filing Date: 2001-10-02
Classification: G06F

Abstract:
A data transfer control system, comprising:a common bus;at least one processor connected to said common bus;at least one direct memory access controller connected to said common bus; anda memory connected to said common bus,wherein said processor determines whether or not a newly requested direct memory access can be performed, using:(i) a present data transfer rate on said bus between all direct memory access controllers, which have already started direct memory access and all processors,(ii) a data transfer rate required by the newly requested direct memory access,(iii) a size of data, which is transferred in one direct memory access operation or a size of data, which said memory can accept,(iv) a latency for accessing said memory, and(v) a latency for bus-right arbitration;said processor starts said newly requested direct memory access when it is determined that said newly requested direct memory access can be performed; andsaid processor waits to start said newly requested direct memory access when it is determined that said newly requested direct memory access cannot be performed and starts said newly requested direct memory access, which has been kept waiting to start, when any direct memory access, which has already been carried out is completed and enough capacity is free in said common bus for carrying out said newly requested direct memory access.