Patent ID: 6282631
Filing Date: 2001-08-28
Classification: G06F

Abstract:
A processor comprising:a bus;a register file coupled to said bus;a memory coupled to said bus comprising at least a first, a second, and a third memory space, wherein said first memory space stores one or more program instructions, said second memory space stores signal processing coefficients, and said third memory space stores dynamic data values received from an input bitstream, wherein said third memory space comprises at least a FIFO buffer having bit extract circuitry, wherein said bit extract circuitry extracts from said input bitstream zero or more bits at a time;an address generation unit coupled to said bus; anda datapath coupled to said bus, the datapath comprising an adder, a shifter, a saturation unit coupled to said shifter, a logic unit, an accumulator, and a multiplier;wherein said program instructions include at least a multiply-accumulate (MAC) instruction; andwherein said program instructions are read from said first memory space over said bus using said address generation unit in response to an edge of a clock signal; andwherein said MAC instruction is executed by said register file and said datapath in a pipelined stream having an execution throughput of one program instruction per cycle of said clock.