Patent ID: 6348390
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A method of fabricating metal oxide semiconductor field effect transistors (MOSFETs) with a recessed self-aligned silicide contact and extended source/drain junctions, said method comprising the steps of:forming isolation regions on a semiconductor substrate, said semiconductor substrate having a first dopant type; forming a gate insulating layer on said substrate; forming a first conductive layer on said gate insulating layer; forming a first dielectric layer on said first conductive layer; removing portions of said gate insulating layer, said first conductive layer and said first dielectric layer to define a gate structure; forming a thermal oxide layer on said substrate and on sidewalls of said first conductive layer; forming sidewall spacers on sidewalls of said gate structure; removing portions of said thermal oxide layer uncovered by said sidewall spacers; isotropically etching said substrate to form recessed regions on said substrate in exposed regions uncovered by said gate structure, said sidewall spacers and said isolation regions; removing said first dielectric layer; forming a first metal layer on said substrate; performing a source/drain/gate implantation with a second dopant type different from said first dopant type to said substrate, thereby forming source/drain regions under said recessed regions; performing a thermal process to convert portions of said first metal layer into a metal silicide layer lying on said recessed regions and on said first conductive layer, thereby forming source/drain junctions beneath said recessed regions; removing unreacted portions of said first metal layer; removing said sidewall spacers; and performing an ion implantation to form said extended source and drain junctions in said substrate under a region covered by said thermal oxide layer.