Patent ID: 9136340
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate having a first doped region and a second doped region; a gate stack formed on the semiconductor substrate; a main spacer layer formed on a sidewall of the gate stack; a protection layer formed between the main spacer layer and the semiconductor substrate, wherein the protection layer is doped with a quadrivalent element, the protection layer has a surface portion and a lower portion, the surface portion is located between the main spacer layer and the lower portion, and the concentration of the doped quadrivalent element in the surface portion is higher than the concentration of the doped quadrivalent element in the lower portion; an insulating layer formed over the semiconductor substrate and the gate stack; and a contact formed in the insulating layer, wherein the contact has a first portion contacting the first doped region, and wherein the contact has a second portion contacting the second doped region, and wherein the first portion extends into the first doped region and extends deeper into the semiconductor substrate than the second portion.