Patent ID: 9048139
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A method for fabricating a non-volatile memory device, comprising: forming a pass gate electrode layer surrounding a sacrificial layer pattern on a substrate; alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over the pass gate electrode layer; forming at least a pair of channel holes that exposes the sacrificial layer pattern by selectively etching the inter-layer dielectric layers and the sacrificial layers; removing the sacrificial layer pattern to form at least a sub-channel hole coupling the pair of the channel holes; forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel holes; sequentially forming a memory layer and a channel layer on the internal walls of the channel holes and the sub-channel hole; forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on the both sides of the channel holes; removing the sacrificial layers that are exposed through the slit holes; removing the protective layer; and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed.