Patent ID: 7068074
Filing Date: 2006-06-27
Classification: H03K

Abstract:
1. A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level, the circuit comprising: an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith; a latch circuit being operative to store a signal representative of a logical state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage; a voltage clamp operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented to the voltage clamp; and a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level, the reference generator circuit being configured to adjust a voltage level of the control signal in response to the input signal.