Patent ID: 6661722
Filing Date: 2003-12-09
Classification: G11C,H01L

Abstract:
A bit line sense amplifier comprising:a sense amplifier block in which a plurality of sense amplifiers for sensing and amplifying data of a memory cell are laid out, each sense amplifier including a pair of transistors; and drivers corresponding to each of the plurality of sense amplifiers which are laid out outside the plurality of sense amplifiers allowing a distance between pates of the pair of transistors for each of the plurality of sense amplifiers to be equalized, for transmitting a first power supply to each of the sense amplifiers in response to a control signal; wherein each of the drivers comprises: a global power supply transmission line for supplying the first power supply, which is laid out in a first direction; a local power supply transmission line which is laid out in a second direction and connected to the global power supply transmission line at 90 degrees; and a via which is connected between the global power supply transmission line and the local power supply transmission line; wherein the first power supply is supplied to each of the sense amplifiers through the global power supply transmission line and the local power supply transmission line.