Patent ID: 7842615
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A method of forming a copper metal line of a semiconductor device, the method comprising the steps of: forming a capping layer and an intermetal dielectric layer in a stacked configuration over a substrate in which lower lines are formed; forming trenches, defining an upper metal line region, on the intermetal dielectric layer through etching employing a first photoresist pattern; forming a spacer on inner sidewalls of the trenches; forming a second photoresist pattern for exposing a first one of the trenches while covering a second one of the trenches and performing etching so as to remove the intermetal dielectric layer exposed by the spacer, thereby forming a via under the exposed first trench; removing the spacer; forming a barrier metal film on inner walls of the trenches and the via; and gap-filling a copper metal line film within the trenches and the via and polishing a surface of the semiconductor device.