Patent ID: 6791112
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A display device comprising:a CMOS circuit including an n-channel TFT and a p-channel TFT over a substrate, the n-channel TFT comprising: a semiconductor layer over the substrate, the semiconductor layer having at least a channel region, a first impurity region in contact with the channel region, and a second impurity region in contact with the first impurity region; a gate insulating film adjacent to the semiconductor layer; a gate electrode adjacent to the gate insulating film, the gate electrode comprising a first gate electrode and a second gate electrode covering an upper surface and a side surface of the first gate electrode, wherein the second gate electrode has a larger width at a first portion overlapping with the semiconductor layer than at a second portion not overlapping with the semiconductor layer, wherein the second gate electrode has a region overlapping with the first impurity region, and wherein the region has a length between 0.1 and 2 &mgr;m.