Patent ID: 7605617
Filing Date: 2009-10-20
Classification: G06F

Abstract:
1. A method for switching a system clock from a first clock signal to a second clock signal, the switching process is triggered by a select control signal and the switching occurs synchronously to the first and/or second clock signal, the method comprising: transferring the clock control from a first predefined edge of the first clock signal to a corresponding first edge of the second clock signal; holding, in accordance with the first clock signal, a system clock signal at a first predefined logic signal level which is the same level as a system clock hold signal, wherein a corresponding first edge of the second clock signal is awaited; and resetting, in accordance with a received first edge of the second clock signal, the system clock hold signal to a second logic state and reactivating, via a second edge of the second clock signal, the system clock signal whereby the second clock functions as the system clock.