Patent ID: 8860205
Filing Date: 2014-10-14
Classification: H01L,H05K

Abstract:
1. A coreless package substrate, comprising: a coreless substrate having a first level interconnect side comprising a plurality of first level interconnect contact pads and a second level interconnect side comprising a plurality of second level interconnect contact pads wherein said coreless substrate comprises a plurality of dielectric layers separating said first level interconnect side from said second level interconnect side and wherein a plurality of levels of conductive vias are utilized to interconnect said first level interconnect contact pads to said second level interconnect contact pads; a stiffener formed from a molding compound on the second level interconnect side, the molded stiffener having a plurality of cavities corresponding to said plurality of second level interconnect contact pads; and wherein said stiffener has a lower coefficient of thermal expansion (CTE) than said coreless substrate, said stiffener is not on any portion of said plurality of second level interconnect pads, said stiffener is not directly laterally adjacent to any portion of said plurality of second level interconnect pads.