Patent ID: 6549043
Filing Date: 2003-04-15
Classification: G11C,H03M

Abstract:
A sample and hold circuit for sampling and holding an input data signal, comprising:switching means for sampling a data voltage which corresponds to the input data signal, and a capacitive element for temporarily holding the sampled voltage; compression means for compressing a voltage range of the data voltage to be sampled, wherein the compression means comprise a first transistor with a main current path that passes a current which is substantially linearly dependent on the input data signal, and wherein a control voltage of the first transistor constitutes the data voltage to be sampled in the operational state; and expansion means for converting the sampled voltage into a sampled output data signal that corresponds approximately linearly to the input data signal, wherein the expansion means comprise a second transistor such that the sampled voltage constitutes a control voltage for the second transistor in the operational state, while the second transistor comprises a main current path for supplying the sampled output data signal.