Patent ID: 8347179
Filing Date: 2013-01-01
Classification: G06F,G11C

Abstract:
1. A data processing apparatus comprising: a non-volatile semiconductor memory in which a storage data including a target data or an inversion data of said target data, as a main storage data and an additional data is stored; and an additional data control circuit configured to generate said additional data and add said additional data to said main storage data, wherein said additional data is different between a first mode and a second mode, which are set in response to a mode specifying signal, wherein said additional data control circuit comprises: a first mode circuit configured to generate said additional data in said first mode; and a second mode circuit configured to generate said additional data in said second mode, wherein said first mode circuit comprises: a data inversion control circuit configured to receive said target data, determine whether each of bits of said target data should be inverted, generate said additional data including an inversion flag indicating the determining result, and generate said storage data by adding said additional data including said inversion flag to said main storage data, and wherein said second mode circuit comprises: an error detection control circuit configured to generate said additional data including an error detection code used for error detection to said target data, and generate said storage data by adding said additional data including said error detection code to said main storage data.