Patent ID: 6362025
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising a vertical-channel MOSFET transistor on a wafer of semiconductor material having a layer with a first conductivity type delimited by a front surface of the wafer, the method comprising the steps of:implanting impurity ions of the first conductivity type and a second conductivity type in an area on the front surface of the wafer and subjecting the wafer to a high-temperature treatment, the impurities of the first conductivity type and of the second conductivity type, implantation doses and energies, and the high-temperature treatment time and temperature being selected such as to form a first region with the second conductivity type which forms a pn junction with the rest of the layer, and a second region with the first conductivity type which forms a pn junction with the first region and is delimited by the front surface; forming isolation trenches in the wafer, for isolating the vertical-channel MOSFET transistor from adjacent components of the semiconductor device, and while simultaneously forming a trench in the wafer which intersects the first region and the second region with at least one lateral surface thereof; forming a dielectric layer on the at least one lateral surface of the trench which intersects the first and second regions; depositing electrically-conductive material in the trench and in contact with the dielectric layer; forming a deep contact region on the front surface of the wafer and reaching the layer with the first conductivity type; and forming contact elements for electrical contact, respectively, with the deep contact region, with the second region, and with the electrically-conductive material inside the trench, to produce drain, source and gate electrodes of the MOSFET, respectively.