Patent ID: 6511906
Filing Date: 2003-01-28
Classification: H01L

Abstract:
An integrated circuit device processing scheme comprising:providing a semiconductor substrate; forming a plurality of semiconductor devices in said substrate; forming a silicon nitride insulating layer over said plurality of semiconductor devices and said semiconductor substrate, wherein said insulating layer defines an upper surface and a lower surface; forming interconnect holes in said insulating layer, wherein said interconnect holes define an uppermost boundary at said upper surface of said insulating layer; filling said interconnect holes with a silver-based conductive material, wherein portions of said silver-based conductive material extend beyond said uppermost boundary of said interconnect holes; and chemically and mechanically planarizing said integrated circuit device with a processing slurry selected to be relatively minimally selective of silicon nitride and relatively highly selective of said silver-based conductive material including said portions of said silver-based conductive material extending beyond said uppermost boundary of said interconnect holes so as to remove portions of said silver-based conductive material extending beyond said uppermost boundary of said interconnect holes, wherein said integrated circuit device is planarized such that said relatively minimal selectivity of silicon nitride and said relatively high selectivity of said silver-based conductive material define a selectivity ratio above about 50.