Patent ID: 8330536
Filing Date: 2012-12-11
Classification: H03F

Abstract:
1. An offset cancellation circuit, the circuit comprising: an amplifier comprising a negative input, a positive input, and a single-ended output; and a capacitor comprising a first terminal and a second terminal, wherein the first terminal is coupled to the negative input of the amplifier, wherein the capacitor is configured to sample an input offset voltage of the amplifier, and wherein the second terminal is selectively coupled to the output of the amplifier; wherein, during a first mode of operation, the second terminal of the capacitor is coupled to a reference voltage, the output of the amplifier is coupled to the negative input of the amplifier forming a unity gain buffer, and the positive input of the amplifier is coupled to the reference voltage; and wherein, during a second mode of operation, the second terminal of the capacitor is uncoupled from the reference voltage and coupled to the output of the amplifier.