Patent ID: 8892853
Filing Date: 2014-11-18
Classification: G06F,G06K,G06T

Abstract:
1. An image processing system comprising: a vector processor ( a memory ( wherein said vector processor ( wherein said address generator ( wherein said address generator ( wherein said parameters are selected from a group of horizontal (X) and vertical (Y) image parameters, the group consisting: a horizontal increment value (Xstep), an initial horizontal value (XStart), a horizontal product of the horizontal increment value (Xstep) and a horizontal count iteration value (Xcount), a vertical increment value (YStep), an initial vertical value (Ystart), a vertical product of said vertical increment value (Ystep) and a vertical count iteration value (Ycount), a number of memory addresses (Width) and a memory size value of said memory ( wherein said address generator ( an output of a comparator ( 74 Y) connected to another input of the vertical counter ( 72 Y), wherein the comparator ( 74 Y) compares the vertical output of Y=Y+Ystep with the vertical product of the vertical increment value (Ystep) and the vertical count iteration value (Ycount); wherein said vector processor ( wherein said address generator (