Patent ID: 9152430
Filing Date: 2015-10-06
Classification: G06F

Abstract:
1. A microcontroller, comprising: a clock generator having an internal reference clock; a system mode controller configured to establish an operating mode of the microcontroller; a flash memory having an internal clock and a non-volatile option register; and a boot mode selection logic circuit coupled to the system mode controller and the flash memory and configured to output a boot mode selection signal designating that the microcontroller is to boot in a very low power run (VLPR) mode or a RUN mode, wherein the system mode controller is configured to enter the VLPR mode or the RUN mode in response to the boot mode selection signal, wherein the flash memory is configured to receive an external flash clock signal based on an output of the internal reference clock, and wherein the flash memory is configured to bypass and disable the internal clock (i) prior to calibration of the flash memory when the boot mode selection signal designates the VLPR mode, such that the flash memory is configured to calibrate, fetch information from the non-volatile option register, and initialize using the external flash clock signal, and (ii) prior to initialization of the flash memory when the boot mode selection signal designates the RUN mode, such that the flash memory is configured to calibrate and fetch information from the non-volatile option register using the internal clock and initialize using the external flash clock signal.