Patent ID: 6894535
Filing Date: 2005-05-17
Classification: G11C

Abstract:
1. An apparatus for ensuring signal integrity of signals output from a latch, the apparatus comprising: a first latch, the first latch having an input, an output and a latch enable; a tri-state buffer having an input, an output and a drive enable; a first conductive line connecting the input of the buffer to the output of the first latch; a second latch, the second latch having an input, an output and a latch enable; a second conductive line, the second conductive line being directly connected to the output of the buffer and to the output of the second latch, wherein when the drive enable is asserted, the buffer drives the output of the first latch such that signal integrity of the output of the first latch is ensured, and wherein when the drive enable is not asserted, the tri-state buffer exhibits high output impedance that isolates the second latch from the first latch.