Patent ID: 8966412
Filing Date: 2015-02-24
Classification: G03F

Abstract:
1. A method, comprising: receiving an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning process (SADP); identifying, in a computing device, a plurality of features within said overall pattern layout that cannot be decomposed using said SADP process, wherein at least a first feature and a second feature, which are adjacent features, are required to be same-color features; decreasing a spacing between said first feature and said second feature which are adjacent to each other in said computing device such that said first feature and said second feature become different-color features so as to render said plurality of features decomposable using said SADP process; decomposing said overall pattern layout with said first feature and said second feature being different-color features and having said decreased spacing therebetween into a mandrel mask pattern and a block mask pattern in said computing device; generating a first set of mask data corresponding to said mandrel mask pattern in said computing device; and generating a second set of mask data corresponding to said block mask pattern in said computing device.