Patent ID: 6333660
Filing Date: 2001-12-25
Classification: G11C,H03K,H03L

Abstract:
A semiconductor device for generating a first internal clock and a second internal clock complementary with each other from an external clock comprising:a first clock input circuit supplied with a first external clock and producing said first internal clock;a second clock input circuit supplied with a second external clock complementary with said first external clock and producing said second clock;a 1/2 phase clock generating circuit for generating a 1/2 phase shift signal 180.degree. out of phase with said first internal clock;a /CLK state detection circuit for judging whether said second external clock is applied to said second clock input buffer; anda switch operated for producing said second clock as said second internal clock when said second external clock is applied and for producing said 1/2 phase shift signal as said second internal clock when said second external clock is not input.