Patent ID: 7772063
Filing Date: 2010-08-10
Classification: H01L

Abstract:
1. A method for CMOS processing of low-cost radio frequency identification (RFID) tag integrated circuits, comprising: forming first-type well regions within a second-type semiconductor substrate; creating second-type MOS transistors within the first-type well regions and first-type MOS transistors within the substrate without utilizing a lightly doped drain (LDD) process; adjusting, separately from the forming and creating steps, threshold voltages for the first-type MOS transistors with a threshold voltage adjust implant processing step directed to the channel of the first-type MOS transistors, and allowing the channels of the second-type MOS transistors to be subjected to the threshold voltage adjust implant processing step as well, thereby allowing threshold voltages for the second-type MOS transistors to also be adjusted by the threshold voltage adjust implant processing step; providing interconnect circuitry utilizing polysilicon layers without utilizing a silicide and utilizing two or fewer metal interconnect layers; and fabricating an integrated radio frequency identification (RFID) tag integrated circuit utilizing the forming, creating, adjusting, and providing steps, the RFID tag integrated circuit including circuitry configured to communicate stored information to an RFID reader; wherein the CMOS process has a minimum device geometry of 1.0 microns or less.