Patent ID: 6784042
Filing Date: 2004-08-31
Classification: H01L

Abstract:
An integration process in a SOI substrate of a semiconductor device including at least a dielectrically insulated well, the process comprising:an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto said oxide layer; and a masking step, carried out onto said nitride layer using a resist layer and directed to define photolithographic openings for forming at least one dielectric trench effective to provide side insulation for said well; an etching step of said nitride layer and said oxide layer, as masked by said resist layer, said nitride layer used as a hardmask; a step of forming said at least one dielectric trench and comprising at least one etching step of said substrate, an oxidizing step of at least sidewalls of said at least one dielectric trench, said oxidizing step producing a plurality of bird's beak structures at the edges of said at least one dielectric trench where said nitride layer is discontinued, and a filling step of said at least one trench with a filling material; a step of forming active areas for components to be integrated in said well, being carried out after said step of forming said at least one dielectric trench; and planarizing the surface of said semiconductor device by removing said plurality of bird's beak structures and etching back said filling material.