Patent ID: 6069849
Filing Date: 2000-05-30
Classification: G01R

Abstract:
A system for determining a maximum signal propagation delay from a node of a test circuit to the node of the test circuit, the system comprising:a. a test oscillator including the test circuit and having an output terminal, wherein the test oscillator is adapted to provide a test signal comprised of a series of alternating high and low logic levels on the oscillator output terminal;b. a phase discriminator having:1. a sample clock adapted to provide on a sample clock terminal a sample clock signal comprised of alternating rising and falling signal transitions, wherein the sample clock signal is asynchronous with the test signal; and2. a phase comparator having a first input terminal connected to the sample clock terminal, a second input terminal connected to the test oscillator output terminal, and a phase comparator output terminal; andc. a counter having an input terminal connected to the phase comparator output terminal.