Patent ID: 6697938
Filing Date: 2004-02-24
Classification: G06F

Abstract:
A microcomputer comprising:a memory; processor connected to the memory for executing a specific area branch instruction, said specific area branch instruction being restricted to jump to only a specific area of said memory, being discriminable from other branch instructions that are each set to jump to any arbitrary address in the memory, and being a single instruction having a minimum instruction length relative to all other instructions, said processor further for allocating a selected subroutine to said specific area of said memory, said selected subroutine being a program stored in said memory and selected from one of a real arithmetic subroutine for executing real arithmetic processing, an integer division subroutine for executing integer division processing, and a bit handling subroutine for executing bit data processing, and said memory storing another program that is configured to jump to said selected subroutine allocated to said specific area in response to said specific area branch instruction.