Patent ID: 6850093
Filing Date: 2005-02-01
Classification: H03K

Abstract:
1. A circuit for improving noise tolerance in multi-threaded memory circuits comprising: (a) a first PFET with a source, drain, and gate; (b) a second PFET with a source, drain, and gate; (c) a first memory cell connected to VDD and GND, with a receiving input, an output, and a control input; (d) a second memory cell connected to VDD and GND, with a receiving input, an output, and a control input; (e) a first transfer gate with an input, a first control input, a second control input and an output; (f) a second transfer gate with an input, a first control input, a second control input and an output; (g) wherein the gate of the first PFET is connected to the output of the first memory cell, the drain of the first PFET is connected to the receiving input of the first memory cell, and the source of the first PFET is connected to the control input of the first memory cell; (h) wherein the gate of the second PFET is connected to the output of the second memory cell, the drain of the second PFET is connected to the receiving input of the second memory cell, and the source of the second PFET is connected to the control input of the second memory cell; (i) wherein the output of the first transfer gate is connected to the receiving input of the first memory cell and the drain of the first PFET, the first control input of the first transfer gate is connected to a first control signal, the second control input of the first transfer gate is connected to a second control signal and the input of the first transfer gate is connected to a dataline and the input of the second transfer gate; (j) wherein the output of the second transfer gate is connected to the receiving input of the second memory cell and the drain of the second PFET, the first control input of the second transfer gate is connected to the second control signal, the second control input of the second transfer gate is connected to the first control signal and the input of the second transfer gate is connected to the dataline and the input of the first transfer gate; (k) such that when the dataline is charged to near GND, the voltage stored on the receiving input of the first memory cell is high, the voltages on the control inputs of the first transfer gate connect the dataline to the receiving input of the first memory cell, and the voltage to the control input of the first and second memory cells is high, the first PFET improves the noise immunity of the first memory cell.