Patent ID: 6085297
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A memory system, comprising:a central processing unit (CPU) for executing a first instruction, and for outputting first, second and third signals;a memory device for storing first data and said first instruction;a first buffer for storing second data;a second buffer for storing third data; anda controller for writing said second data and said third data in order into said memory device when said controller receives said first signal twice, and for reading said first data from said memory device after writing said second data and said third data into said memory device when said controller receives said second signal,said controller for canceling writing said second data or writing said third data when said controller receives said third signal during said writing said second data or writing said third data, reading said first instruction from said memory device, and then, starting said writing said second data or writing said third data again.