Patent ID: 7907433
Filing Date: 2011-03-15
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of package terminals included in a package; a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals; and a plurality of data line control switches disposed between the plurality of package terminals and the plurality of data input/output terminals, the plurality of data line control switches of each of the chips connecting the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode, the plurality of data line control switches connecting different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode, the respective groups of the data input/output terminals belonging to the plurality of data input/output terminals, wherein the respective groups of the package terminals is different between different ones of the chips.