Patent ID: 6171915
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method of fabricating a MOS-type transistor of a LDD (Lightly Doped Drain and Source) structure comprising the steps of:forming a first pattern, said first pattern including a gate electrode made of molybdenum;subjecting the first pattern to a nitriding process so as to form a second pattern, said second pattern being composed of an interior electrode layer and a nitride layer outside of the electrode layer;subjecting said second pattern to an implanting process self-aligned to the second pattern in which impurities are implanted;annealing to diffuse the implanted impurities to form source and drain regions; andsaid step of subjecting the first pattern to the nitriding process and said step of annealing including controlling the nitriding process such that the nitride layer created by the nitriding process has a thickness at a side of said gate electrode which is approximately equal to an amount of overlapping between the second pattern and said source and drain regions by diffusion of said implanted impurities in said annealing process.