Patent ID: 7490305
Filing Date: 2009-02-10
Classification: G06F

Abstract:
1. A method, in a data processing device, for verifying an operation of untimed net segments of an integrated circuit design, comprising: receiving the integrated circuit design; receiving a “don't care” (DC) adjusted list that identifies net segments that do not need to adhere to timing requirements; comparing entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design; driving a value along a pathway to the at least one untimed net segment; monitoring an output state value from the untimed net segment; verifying an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment; determining whether there is a violation in the operation of the untimed net segment; determining whether downstream logic in the integrated circuit design uses the output value; and removing the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.