Patent ID: 6242790
Filing Date: 2001-06-05
Classification: G11C,H01L

Abstract:
A polysilicon fuse structure for implementation within integrated circuit devices so as to permit programming comprising:a first electrical contact region;a second electrical contact region;multiple fuse regions interconnected between said first electrical contact region and said second electrical contact region;said multiple fuse regions being formed of a plurality of strips which are disposed in a spaced-apart relationship so as to form a small opening between adjacent strips;each of said plurality of strips having a different width and/or length;at least two strips of said plurality of strips being disposed at an acute angle relative to each other;a number of said plurality of strips being selectively blown when a predetermined amount current is passed from one of said first and second electrical contact regions through said plurality of strips to said other one of said first and second electrical contact regions so as to limit the current passing to an integrated circuit device connected thereto during normal operating conditions andsaid polysilicon fuse structure including a polysilicon layer and a suicide layer formed on the top surface of said polysilicon layer.