Patent ID: 8576638
Filing Date: 2013-11-05
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a memory cell array including normal memory cells and redundancy memory cells, the normal memory cells and the redundancy memory cells being arranged in rows and in columns and coupled to normal bit lines and redundancy bit lines, respectively; a row decoder configured to select a row including a first set of the normal memory cells and a first set of the redundancy memory cells in response to a first row address; a page buffer configured to load normal data through the corresponding normal bit lines from the selected first set of the normal memory cells, and to load redundancy data through the corresponding redundancy bit lines from the selected first set of redundancy memory cells; a column decoder configured to generate a normal column selection signal and a redundancy column selection signal in response to a first column address; a repair control circuit configured to generate a column repair signal in response to the redundancy column selection signal; a column selection circuit configured to select normal data and redundancy data from the page buffer in response to the normal column selection signal and the redundancy column selection signal, respectively; and a repair circuit configured to receive the selected normal data and selected redundancy data at first and second inputs, respectively, and to output one of the selected normal data and the selected redundancy data during at least two consecutive clock cycles of an internal clock signal in response to the column repair signal, wherein the column decoder, the column selection circuit and the repair circuit are configured to operate simultaneously, each being responsive to a different column address at any one time.