Patent ID: 6583660
Filing Date: 2003-06-24
Classification: H03F

Abstract:
A differential amplifier comprising:a first input stage operative to receive a first input signal of a differential signal pair; a second input stage operative to receive a second input signal of said differential signal pair; an output stage operative to produce first and second differential output signals equal to the amplification of the difference between the first signal and the second signal; and an offset cancellation circuit operative to actively cancel offset voltage in said first and second differential output signals added by said differential amplifier wherein said differential amplifier is responsive to a two-phase clock, wherein said first input stage is further operative to receive said first input signal on a first phase of said two-phase clock and receive a common signal on a second phase of said two-phase clock, said second input stage is further operative to receive said second input signal on said first phase and receive said common signal on said second phase and further wherein said offset cancellation circuit is further operative to compute an adjusted bias current on said second phase and said offset cancellation circuit is further operative apply said adjusted bias current on said first phase to cancel said offset voltage.