Patent ID: 8558391
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a multi-layer interconnect formed over a semiconductor substrate; a first interconnect portion formed in an uppermost layer of the multi-layer interconnect; a first insulating film formed over the first interconnect portion; a second insulating film formed over the first insulating film; a plurality of redistribution interconnects formed over the second insulating film; a third insulating film formed over the second insulating film and the redistribution interconnects; and a bump electrode formed over the third insulating film, wherein the redistribution interconnects include a first pattern and a second pattern which is electrically separated from the first pattern, wherein a first opening portion is formed in the first and second insulating films, and reaches at a part of the first interconnect portion, wherein a second opening portion is formed in the third insulating film and reaches at the first pattern, wherein the first pattern is electrically connected to the first interconnect portion via the first opening portion and is electrically connected to the bump electrode via the second opening portion, wherein the second pattern is electrically separated from the multi-layer interconnect and the bump electrode, and wherein a planar shape of the first pattern in the second opening portion is larger than a planar shape of the second pattern.