Patent ID: 6462692
Filing Date: 2002-10-08
Classification: H03M

Abstract:
A digital-to-analog converter that decreases response delay caused by a filter time constant, comprising:a counter that repeatedly counts a predetermined count value; a modulating section that compares one of a count value output from said counter and a reversed count value in which upper bits and lower bits of said count value are reversed with an actual set value corresponding to a target digital value, said modulating section comprising a comparator, and generating one of a pulse-width modulation signal and pulse-density modulation signal; a low-pass filter that removes a high frequency component of one of said pulse-width modulation signal and said pulse-density modulation signal output from said modulating section to generate an analog signal; and a set value calculator for multiplying a difference between a current target digital value and a previous target digital value by a coefficient determined from a time constant of the low-pass filter and an update cycle of said target digital value, and adding a result of the multiplication to the previous target digital value to calculate said actual set value, whenever said target digital value is updated, wherein the coefficient cancels a decrease in a substantial variation of said target digital value, caused by the low-pass filter time constant.