Patent ID: 7643345
Filing Date: 2010-01-05
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: memory cells each of which includes a stacked gate and a current path, the stacked gate including a charge accumulation layer and a control gate, the charge accumulation layer being formed on a semiconductor substrate with a first insulating film interposed therebetween, the control gate being formed on the charge accumulation layer with a second insulating film interposed therebetween; a memory cell array in which the memory cells are arranged such that the current path of each of the memory cells is provided in the first direction; a contact region which is adjacent to the memory cell array in a second direction orthogonal to the first direction, the contact region including an element insulating region formed on the semiconductor substrate, a terminal portion on one end of the control gate being drawn onto the element insulating region from within the memory cell array; and first contact plugs which are formed on respective ones of the control gates located on the element insulating region in the contact region, the first contact plugs being located so as to alternately sandwich a first axis in the first direction in the contact region.