Patent ID: 7679970
Filing Date: 2010-03-16
Classification: G11C

Abstract:
1. A semiconductor memory device including a unit cell block having a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data accessed to the unit cell block, the semiconductor memory device comprising: a first global sense amplifying unit for sensing and amplifying a plurality of data for write access to the unit cell block and latching the sensed and amplified data; a second global sense amplifying unit for latching a plurality of data read-accessed in the unit cell block; a first global bit line for transmitting data between the first global sense amplifying unit and the bit line sense amplifying unit; a second global bit line for transmitting data between the second global sense amplifying unit and the bit line sense amplifying unit; a control unit for independently controlling a first connection between the bit line sense amplifying unit and the first global bit line and a second connection between the bit line sense amplifying unit and the second global bit line according to an access mode.