Patent ID: 8493397
Filing Date: 2013-07-23
Classification: G06F,G06T,G09G,H04N

Abstract:
1. A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor, comprising: accessing a queue of read requests from a video processor; tracking each of a plurality of cache lines stored within the cache using a least recently used variable, wherein said tracking comprises tracking the number of times a particular cache line has been requested; for each cache line hit out of the plurality of cache lines and corresponding to one of the read requests, adjusting the least recently used variable for a remainder of the plurality of cache lines, wherein said state machine is operable to facilitate the adjustment of the remainder of the plurality of cache lines; determining a replacement cache line by examining the least recently used variables for each of the plurality of cache lines wherein said determining is operable to be based on a least recently used variable having a value larger than each of the other least recently used variables of each of the plurality of cache lines; and for each cache line miss, allocating a cache line slot corresponding to the replacement cache line to store a new cache line responsive to the cache line miss.