Patent ID: 7454685
Filing Date: 2008-11-18
Classification: H03M

Abstract:
1. An apparatus for decoding a low density parity check (LDPC) code that includes a plurality of check nodes and a plurality of variable nodes according to a parity check matrix, the apparatus comprising: a check node selection scheduler for selecting at least one check node for check node processing among the check nodes; a log likelihood ratio (LLR) memory for storing an input LLR value for the variable nodes as an initial LLR value, and storing updated LLR values for variable nodes connected to the selected check node; a check node message memory for storing a check node message indicative of a result value of check node processing on the selected check node; and at least one united node processor for generating a variable node message by subtracting the check node message of the selected check node stored in the check node message memory from corresponding LLR values read from the LLR memory, performing check node processing on the variable node message, calculating an LLR value updated by adding the variable node message to the check node processing result value, and delivering the calculated LLR value to the LLR memory.