Patent ID: 6531727
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A memory cell, comprising:a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer; a single crystalline vertical transistor formed along side of the pillar, wherein the single crystalline vertical transistor includes; an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer; an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer; an ultra thin single crystalline vertical body region formed along side of the oxide layer, wherein the single crystalline vertical body region couples the first source/drain region to the second source/drain region; and a gate opposing the vertical body region and separated therefrom by a gate oxide; a buried bit line formed of single crystalline semiconductor material and disposed below the ultra thin single crystalline vertical body region, wherein the buried bit line is coupled to the first contact layer; a capacitor coupled to the second contact layer; and a word line disposed orthogonally to the buried bit line in a trench below a top surface of the pillar for addressing the gate.