Patent ID: 8357575
Filing Date: 2013-01-22
Classification: H01L

Abstract:
1. A method, comprising: forming a first stress-inducing layer above a first gate electrode structure of a first transistor and a second stress-inducing layer above a second gate electrode structure of a second transistor, said first and second gate electrode structures comprising a gate insulation layer including a high-k dielectric material and a placeholder material formed above said high-k dielectric material, wherein said first stress-inducing layer comprises an internal stress that is different from said second stress-inducing layer; forming a dielectric material above said first and second stress-inducing layers and above said first and second gate electrode structures; planarizing said dielectric material formed above said first stress-inducing layer and said second stress-inducing layer so as to expose a portion of said first stress-inducing layer and a portion of said second stress-inducing layer; implanting an implantation species into said dielectric material and said portions of said first and second stress-inducing layers after planarizing said dielectric material; and removing material of said dielectric material and said first and second stress-inducing layers so as to expose a sacrificial material of said first and second gate electrode structures, said removed material comprising at least a portion of said implantation species.