Patent ID: 6900662
Filing Date: 2005-05-31
Classification: H03K

Abstract:
1. A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit; the translator circuit comprising: a first transistor coupled to the transmitting voltage potential circuit; a clamping mechanism coupled to the first transistor, wherein the clamping mechanism comprises a fifth transistor coupled to the gate of the first transistor and a higher voltage potential; a second transistor coupled to the first transistor, the higher voltage potential and the receiving voltage potential circuit; a third transistor coupled to the receiving voltage potential circuit, the higher voltage potential and the second transistor; and a fourth transistor coupled to the transmitting voltage potential circuit, the receiving voltage potential circuit, and to a ground potential, wherein the clamping mechanism clamps a control node of the translator circuit such that an appropriate logic level is provided to the receiving voltage potential circuit and the leakage current is minimized when the transmitting voltage potential circuit's power supply is disabled.