Patent ID: 6144931
Filing Date: 2000-11-07
Classification: G06F

Abstract:
A computer programmed to perform a wafer expansion-and-contraction simulation method for estimating expansion and contraction of a wafer which is caused when a thin film is formed on the wafer, comprising:calculating on the basis of a thermal stress analysis a first displacement of the wafer from an initial wafer state stored in a first memory location caused when a temperature of the wafer is increased from a room temperature to a film forming temperature of the thin film, and storing the first displacement in a second memory location;calculating on the basis of a thermal stress analysis a second displacement of the wafer from the first displacement stored in the second memory location caused when the temperature of the wafer is decreased to the room temperature after the film is formed thereon, and storing the second displacement in a third memory location; andadding the first displacement and the second displacement to estimate an overall expansion and contraction of the wafer from the initial state stored in the first memory location, and storing in a fourth memory location.