Patent ID: 6426889
Filing Date: 2002-07-30
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit comprising:a first data line and a second data line disposed adjacent to each other; a plurality of word lines crossing said first and second data lines; a plurality of memory cells; first, second, third, and fourth word driver groups coupled to said plurality of word lines; first, second, third, and fourth voltage supply lines, each coupled to corresponding one of said first to fourth word driver groups to supply them a predetermined potential for unselected state; and a sense amplifier connected to said first and second data lines, wherein said plurality of memory cells are arranged at intersections between said plurality of word lines and one of said first and said second data lines, respectively, wherein in eight adjoining word lines out of said plurality of word lines, two of said eight word lines are connected to said first word driver group, two others of said eight word lines are connected to said second word driver group, two still others of said eight word lines are connected to said third word driver group, and the rest two of said eight word lines are connected to said fourth word driver group, and wherein said first and second data lines are disposed between said first and second word driver groups and said third and fourth word driver groups.