Patent ID: 6713398
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of planarizing a polysilicon plug, comprising the steps of:providing an interconnect structure, wherein the interconnect structure includes a dielectric layer with an opening overfilled with a polysilicon layer, wherein a top of the polysilicon layer has a recess above the opening; forming a high molecular weight sacrificial film over the polysilicon layer by chemical vapor deposition using an inductive coupled plasma etcher comprising a high-density difluoromethane plasma in a manner that etching and polymerization reactions occur simultaneously, so that the recess is completely filled; and etching the sacrificial film and the polysilicon layer to remove entirely the sacrificial film and the polysilicon layer above the dielectric layer so that the polysilicon layer remaining inside the opening becomes a planarized polysilicon plug.