Patent ID: 8429569
Filing Date: 2013-04-23
Classification: G03F,G06F

Abstract:
1. A method, comprising: providing a present wafer to be processed by a photolithography tool to form a new integrated circuit design thereon; selecting a processed wafer out of a plurality of previously processed wafers, the processed wafer having a past integrated circuit design different than the new integrated circuit design, the selecting based upon the similarity of the past integrated circuit design to the new integrated circuit design; selecting a plurality of critical dimension (CD) data points extracted from the processed wafer after the processed wafer was etched, wherein the selecting the plurality of CD data points includes: creating an initial exposure dose map for the new integrated circuit design using the plurality of CD data points; and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new integrated circuit design on the present wafer.