Patent ID: 9099444
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a substrate; a bottom semiconductor die having an active side with a surface area and having a bottom side, the bottom semiconductor die disposed above and spaced apart from the substrate with the active side distal from the substrate; a top semiconductor die disposed above the bottom semiconductor die and having an active side with a surface area larger than the surface area of the bottom semiconductor die, the top semiconductor die coupled to the substrate with the active side proximate to the substrate, wherein the active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die, and wherein the top semiconductor die is conductively coupled to the substrate by conductive structures that bypass the bottom side of the bottom semiconductor die; and a molding layer housing the conductive structures and housing the bottom semiconductor die, wherein the molding layer is co-planar with the bottom side of the bottom semiconductor die and with the conductive structures, wherein the conductive structures comprise a plurality of bumps that extend from the active side of the top semiconductor die to a level co-planar with the bottom side of the bottom semiconductor die, the plurality of bumps coupled to a plurality of solder balls coupled to the substrate.