Patent ID: 6327559
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A method for use in a simulation test for creating test results for verification of instruction processing units such as a branch history table, comprising the steps of:creating a first test instruction stream by activating a unit simulation instruction stream generator (1) to provide at least one or more first test instruction streams as a data stream that mimics instructions streams with a psuedo-instruction stream that has full control over the simulations and which supplies the logic of the instruction processing units being tested with such limited data that supplies the behavioral simulus that said logic needs to operate for the test but does not contain specific instructions to the instruction processing unit block of logic under test (5) via an instruction unit pipeline simulation control unit array loader (4), and coupling the test instruction stream with said psuedo-instruction stream that has full control over the simulations for said the block logic under test from said instruction processing unit block of logic under test (5) as results to a shadow array (3) to provide test signal outputs for checking results in said shadow array whereupon shadow logic (3) is used for checking said results.