Patent ID: 9153182
Filing Date: 2015-10-06
Classification: G02F,G09G

Abstract:
1. An electrophoretic display comprising: an electrophoretic panel comprising a plurality of pixels and a common voltage terminal, wherein the plurality of pixels are coupled to the common voltage terminal; a timing control circuit for generating a timing control signal corresponding to a refresh area of an image according to the refresh area of the image to be displayed on the electrophoretic panel; a data driving circuit coupled to the timing control circuit for receiving the timing control signal, and driving data lines corresponding to M data lines of the refresh area coupled to the data driving circuit according to the timing control signal, wherein M is a positive integer; a gate driving circuit coupled to the timing control circuit for outputting scan signals sequentially to N first gate lines coupled to the gate driving circuit, and generating output enable signals corresponding to the refresh area according to the timing control signal; and a gate line enabling circuit coupled to the N first gate lines for transmitting scan signals of the N first gate lines corresponding to the refresh area to second gate lines corresponding to N second gate lines of the refresh area coupled to the gate line enabling circuit according to output enable signals corresponding to the refresh area, the gate line enabling circuit comprising N gate line enabling modules, each gate line enabling module coupled to one first gate line of the N first gate lines and one second gate line of the N second gate lines, and used for receiving a corresponding output enable signal, each gate line enabling module corresponding to the refresh area being used for transmitting a scan signal of a first gate line corresponding to the gate line enabling module to a second gate line corresponding to the gate line enabling module according to a corresponding output enable signal, and the scan signal of the second gate line being used for controlling turning off and turning on of a switch coupled to a pixel, each gate line enabling module of the N gate line enabling modules comprising: a first thin-film transistor having a first terminal for receiving a scan signal of a first gate line corresponding to the gate line enabling module, a second terminal for receiving the corresponding output enable signal, and a third terminal coupled to a second gate line corresponding to the gate line enabling module; an inverter having a first terminal for receiving the corresponding output enable signal, and a second terminal for outputting an inverted corresponding output enable signal; and a second thin-film transistor having a first terminal for receiving a gate low voltage, a second terminal coupled to the second terminal of the inverter, and a third terminal coupled to the third terminal of the first thin-film transistor; wherein N is a positive integer.