Patent ID: 8148226
Filing Date: 2012-04-03
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device in which enhancement-mode and depletion-mode FETs are integrated on a semiconductor substrate, said method comprising: forming a plurality of active regions in a semiconductor substrate, the active regions being located at a main surface of the semiconductor substrate and electrically separated from one another by an isolation structure; forming a plurality of gate electrodes on the plurality of active regions, each gate electrode extending in an extending direction transverse to the plurality of active regions; forming an opening in a gate electrode for the depletion-mode FET of the plurality of gate electrodes, the opening being located in or in the vicinity of one of overlapping regions in which the gate electrodes extend over the active regions; ion-implanting dopant impurities into the active regions at an oblique angle of incidence relative to a normal line perpendicular to the main surface of the semiconductor substrate, using the gate electrodes as a mask, thereby to form first, second and third doped regions simultaneously in the active regions, the first and second doped regions being located on respective opposite sides of each of the gate electrodes along a gate-length direction of a corresponding one of the gate electrodes, and third doped region being located below the opening and continuously extending from one of the opposite sides of a corresponding one of the gate electrodes to the other; and forming source and drain regions in the active regions, the source and drain regions being located on the respective opposite sides of each of the gate electrodes.