Patent ID: 6320397
Filing Date: 2001-11-20
Classification: G01R,H01L,H05K,Y10T

Abstract:
A carrier for testing a semiconductor die comprising:a molded plastic base comprising a first surface, a second surface and a molded plastic rib on the second surface configured for insertion into a socket;a first conductive trace on the rib;a second conductive trace on the first surface;a conductive via in the base electrically connecting the first conductive trace and the second conductive trace;an interconnect on the first surface comprising a substrate and a contact member on the substrate in electrical communication with the first conductive trace and configured to electrically contact a contact location on the die; anda force mechanism on the base configured to bias the interconnect and the die together,the rib configured to stiffen the base and to resist a bending moment applied to the base by the force mechanism.