Patent ID: 6613674
Filing Date: 2003-09-02
Classification: H01L,Y10S

Abstract:
A processing method of forming integrated circuitry comprising:providing a semiconductor wafer having a frontside for supporting integrated circuitry and a backside which faces generally oppositely away from the frontside; at least partially forming integrated circuitry relative to the semiconductor wafer frontside, the at least partially forming integrated circuitry comprising: forming a layer of insulative material over the semiconductor wafer frontside; etching a capacitor container opening into the layer of insulative material; forming a layer of storage node material over the semiconductor wafer frontside and within the capacitor container opening to less than fill the capacitor container opening, the storage node material forming on the wafer backside while forming on the wafer frontside; forming a filler material over at least the storage node material on the wafer frontside to a degree sufficient to fill the remaining capacitor container opening; planarizing the storage node material and the filler material relative to the layer of insulative material; after the planarizing, chemically etching the storage node material to recess it relative to the insulative material and the filler material; after the chemically etching, mechanically scrubbing the storage node material from the semiconductor wafer backside; after mechanically scrubbing of the storage node material from the wafer backside, forming a final passivation layer over the semiconductor wafer frontside; and further comprising after the chemically etching, treating the wafer backside with a solution having at least about 1% by weight tetramethyl ammonium hydroxide without mechanical scrubbing prior to said mechanically scrubbing and while substantially restricting the wafer frontside from such treating.