Patent ID: 9105505
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A memory cell with a recessed gate, comprising: a semiconductor substrate; a shallow trench isolation, disposed in the semiconductor substrate so as to define an active region; a source region, disposed on a side of the active region; a drain region, disposed on another side of the active region, wherein a direction from the source region to the drain region is defined as a first direction; a gate trench, disposed in the semiconductor substrate between the source region and the drain region, wherein the gate trench comprises a sidewall portion and a curved-bottom surface, and the curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction; a gate electrode, disposed in the gate trench; a halogen-doped dielectric layer, disposed between the gate electrode and the semiconductor substrate, wherein the halogen-doped dielectric layer is situated directly on the curved-bottom surface; and at least a capacitor, electrically connected to the drain region.