Patent ID: 6441556
Filing Date: 2002-08-27
Classification: H02H

Abstract:
An integrated fault protection circuit, comprising:a fault switch interposed between an input power source and an electronic subsystem power bus; a power converter in the electronic subsystem power bus and converting power derived therefrom to at least one voltage output to supply power to the electronic subsystem and at least one fault protection output controlling the fault switch; wherein when the out of range current is detected on the electronic subsystem bus, the fault detection circuit instructs the power converter via the at least one fault detection output, to open the fault switch, thereby isolating the input power from the electronic subsystem bus; and a time delayed start switch interposed between the input power source and the power converter to provide power to the power converter for a predetermined time period after the input power in initially activated; wherein during said predetermined time period the power converter controls the fault switch to provide power to the power converter from the input power source via the subsystem power bus, such that when the predetermined time period expires, power is no longer supplied to the power converter via the start switch and power is supplied via the fault switch only.