Patent ID: 6563351
Filing Date: 2003-05-13
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a first MOS transistor having a drain connected to an output terminal, a gate and a source, the gate of said first MOS transistor being applied with voltage not lower than a threshold voltage of said first MOS transistor; a second MOS transistor having a gate supplied with a switching signal used for controlling an output level of the-output terminal, a drain connected to the source of said first MOS transistor and a source, said second MOS transistor having the same conductivity type as said first MOS transistor; a first capacitor having one electrode connected to the gate of said first MOS transistor and the other electrode connected to a first node whose potential changes in a complementary fashion with respect to the drain potential of said first MOS transistor, said first capacitor functioning to cancel out an influence, caused by the coupling of a mirror capacitor existing between the gate and drain of said first MOS transistor, affecting the gate potential of said first MOS transistor; and a first inverter having an input terminal connected to the gate of said second MOS transistor and an output terminal connected to the other electrode of said first capacitor.