Patent ID: 6088715
Filing Date: 2000-07-11
Classification: G06F,H03M

Abstract:
A microprocessor, including:a first execution unit coupled to receive a first pair of floating point input values and a second pair of floating point input values, wherein said first execution unit includes:a first add/subtract pipeline coupled to receive said first pair of floating point input values and a first indication of whether an effective addition or subtraction operation is to be performed on said first pair of floating point input values, wherein said first add/subtract pipeline includes a first far data path and a first close data path each coupled to receive said first pair of floating point input values, and wherein said first far data path is configured to perform effective addition operations and is also configured to perform effective subtract operations on operands having an absolute exponent difference greater than one, and wherein said first close data path is configured to perform effective subtract operations on operands having an absolute exponent difference less than or equal to one, and wherein said first add/subtract pipeline is configured to generate a first output value from said first pair of floating point input values, wherein said first output value is generated either in said first far data path or said first close data path according to said first indication and a first absolute exponent difference of said first pair of floating point input values;a second add/subtract pipeline coupled to receive said second pair of floating point input values and a second indication of whether an effective addition or subtraction operation is to be performed on said second pair of floating point input values, wherein said second add/subtract pipeline includes a second far data path and a second close data path each coupled to receive said second pair of floating point input values, and wherein said second far data path is configured to perform effective addition operations and is also configured to perform effective subtract operations on operands having an absolute exponent difference greater than one, and wherein said second close data path is configured to perform effective subtract operations on operands having an absolute exponent difference less than or equal to one, and wherein said second add/subtract pipeline is configured to generate a second output value from said second pair of floating point input values, wherein said second output value is generated either in said second far data path or said second close data path according to said second indication and a second absolute exponent difference of said second pair of floating point input values;an output register configured to store said first output value and said second output value.