Patent ID: 7971033
Filing Date: 2011-06-28
Classification: G06F

Abstract:
1. A method for reducing the number of entries searched in a load issued prematurely (LIP) part of a load reorder queue (LRQ) to detect bad values retrieved by pending load instructions when load instructions are executed by a processor, comprising: retrieving load instructions from an issue queue (IQ) to begin execution; determining the LIP congruence class based on the effective address of the load instruction; checking an entry in the LIP part of the LRQ for both a store sequence number (SSQN) of the load instruction being older than a store_safe register and a load sequence number (LSQN) of the load instruction being older than a snoop_safe register in the congruence class indicated by the address from which the load instruction is reading data, the store_safe register containing a SSQN of the youngest store, S, for which S and all stores older than S have had their address resolved, the snoop_safe register containing a LSQN of the youngest load, L, for which L and all loads older than L have received their data; replacing checked entry in the LIP part of the LRQ with a newer load instruction entry if the SSQN of the checked entry is older than the store_safe register and the LSQN of the checked entry is older than the snoop_safe register; and clearing a LIP PTR valid bit in a load reorder queue (LRQ) for the checked entry that is replaced.