Patent ID: 6785270
Filing Date: 2004-08-31
Classification: H04Q

Abstract:
An application-specific integrated circuit (ASIC) device for switching data from a first bus to a second bus in a switching system, comprising:a first random access memory (RAM) operable to store a code for each of a plurality of first time slots and to communicate the code for each first time slot; a second RAM operable to store a plurality of operations, the second RAM operable to receive a combination of the code for each first time slot and corresponding data from the first bus, the combination specifying one of the stored operations, the second RAM operable to apply the specified operation for each first time slot to the data for each first time slot to generate modified data for each first time slot, the second RAM operable to communicate the modified data; a third RAM operable to store information specifying one of a plurality of second time slots associated with the second bus to correspond to each first time slot, the third RAM operable to communicate the information specifying the second time slot corresponding to each first time slot as an address; and a fourth RAM operable to: store the modified data for each first time slot of a previous frame; store the modified data for each first time slot of a current frame; receive the address for each first time slot of the previous frame, specifying the second time slot corresponding to the first time slot, from the third RAM; locate the modified data for each first time slot of the previous frame according to the address; and communicate the modified data for each first time slot of the previous frame to the second bus in the corresponding second time slot while the modified data for the current frame is being stored.