Patent ID: 9053009
Filing Date: 2015-06-09
Classification: G06F

Abstract:
1. A memory system, comprising a plurality of separately accessible memory planes including two or more data memory areas and at least one parity memory plane to store parity information, wherein each of the plurality of memory planes is a plane within a NAND flash memory device; a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes according to an atomic operation performed so that at any one time, no more than one data or parity memory area within a parity group is occupied by a write or erase operation; wherein, when any one of the data memory areas is occupied, the controller is adapted to reconstruct data stored in the one occupied data memory area by reading parity information and data stored in at least one data memory area other than the one occupied data memory area, wherein at least some of the plurality of memory planes store both data and parity information, and the memory controller is further adapted to store redundant parity information associated with the data in one or more of the memory planes, and to reconstruct the parity information from the redundant parity information.