Patent ID: 6476643
Filing Date: 2002-11-05
Classification: G06F

Abstract:
An electronic circuit comprising:an asynchronous circuit with a micro-pipeline type instruction execution mode designed to detect and correct soft error in digital integrated circuits, the asynchronous circuit comprising: at least one logic stage, each of the at least one logic stage comprising: a logic calculation unit whose output terminal transmits an output signal; a first recording means a first input terminal of which being coupled to the output terminal of the logic calculation unit; and a control unit one of whose three output terminals transmits a first data capture signal applied to a second input terminal of the first recording means, the other two output terminals of the control unit being respectively coupled to an input terminal of a control unit of a previous logic stage, and to an input terminal of a control unit of a next logic stage by means of a delay line; and wherein the asynchronous circuit also comprises: a second recording means one of whose two input terminals is coupled to the output terminal of the logic calculation unit; means in the control unit for delaying the first data capture signal and providing a second data capture signal that is applied to the second recording means; a comparer circuit one of whose two input terminals is coupled to the output terminal of the first recording means and whose other input terminal is coupled to the output terminal of the second recording means, the comparer circuit supplying an output signal that indicates in a first status that no soft error is present and in a second status that a soft error is present; and a programmable delay line whose first input terminal is coupled to the output terminal of the comparer circuit, a second input terminal being coupled to the output terminal of the delay line via a first delayed path and a last input terminal is coupled to the output terminal of the delay line via a second non-delayed path.