Patent ID: 6377081
Filing Date: 2002-04-23
Classification: G01R,H03D,H03K,H03L,H04L

Abstract:
A phase detection circuit which detects a phase difference between a data signal and a clock signal, said detection circuit comprising:a first D-type flip-flop circuit, to which said data signal and said clock signal are input; a first delay circuit which delays said clock signal by a prescribed amount of time, so as to generate a delayed clock signal; a second D-type flip-flop circuit, to which an output signal of said first D-type flip-flop circuit and said delayed clock signal are input; a second delay circuit which delays said output signal of said second D-type flip-flop circuit so as to generate a first delayed signal; a third delay circuit which delay said an output signal of said first D-type flip-flop circuit so as to generate a second delayed signal; a fourth delay circuit which delays said data signal so as to generate a delayed data signal; a first AND circuit which calculates a logical product of said first delayed signal and said second delayed signal so as to output a DOWN signal; a second AND circuit which calculates a logical product of said second delayed signal and said delayed data signal so as to output and UP signal; and an adder circuit which adds said UP signal and said DOWN signal so as to output a detection signal detecting a phase difference between said data signal and said clock signal.