Patent ID: 6258708
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:(a) forming a first wiring layer having a thickness between 50 nm and 300 nm on a semiconductor substrate, said first wiring layer being covered therearound with an insulating film including a sidewall film at least partially comprised of silicon nitride;(b) forming a first interlayer insulating film over the product resulting from said step (a);(c) simultaneously forming a first contact hole reaching said semiconductor substrate and a second contact hole reaching said first wiring layer;(d) forming a second wiring layer having a thickness between 20 nm and 100 nm disposed upon the product resulting from said step (c), said second wiring layer including a load element, a Vcc element, and a contact pad element, wherein said load element is non-doped with impurities or doped with impurities in a range of 1.times.10.sup.12 cm.sup.-2 -1.times.10.sup.14 cm.sup.-2 and wherein said Vcc element and said contact pad element are doped with impurities in a range of 5.times.10.sup.14 cm.sup.-2 -1.times.10.sup.16 cm.sup.-2 ;(e) forming a second interlayer insulating film over the product resulting from said step (d);(f) forming a patterned photoresist layer upon said second interlayer insulating film and simultaneously forming a third contact hole reaching said semiconductor substrate and a fourth contact hole reaching said second wiring layer; and(g) forming a third wiring layer over said third and fourth contact holes.