Patent ID: 6304989
Filing Date: 2001-10-16
Classification: G11C

Abstract:
An apparatus for generating output configuration data allocating spare rows and columns of cells for replacing I rows and J columns of an array of memory cells in response to incoming cell addresses, each including a row address and a column address of a defective cell of said array, wherein I and J are integers greater than 0, and wherein said array is implemented in an integrated circuit (IC), the apparatus comprising:I row registers implemented in said IC, each corresponding to a separate one of the spare rows, for storing a row address of an array row including at least one defective cell;J column registers implemented in said IC, each corresponding to a separate one of the spare columns, for storing a column address of an array column including at least one defective cell, and for storing a set of I link bits, each corresponding to a separate one of said I row registers; andcontrol means for responding to an incoming cell address by writing its included row address into one of said row registers, by writing its included column address and a link bit into one of said column registers, said link bit corresponding to said one of said row registers.