Patent ID: 6271081
Filing Date: 2001-08-07
Classification: H01L,Y10S

Abstract:
A method for forming a semiconductor memory device, comprising:forming a plurality of trench capacitors on a semiconductor substrate in a form of a matrix at a substantially constant pitch in row directions, wherein said trench capacitors are sequentially shifted between adjacent rows by a predetermined pitch;forming an element isolating insulator film so as to surround active regions, wherein each of said active regions is adjacent to two trench capacitors and said trench capacitors are adjacent to each other in said row directions, and said element isolating insulator film includes a partial region of said two trench capacitors; andforming a plurality of transistors in each of said active regions, wherein each of said transistors has a source diffusion layer and a drain diffusion layer, one of said source diffusion layer and said drain diffusion layer is connected to a capacitor node layer of a corresponding one of said trench capacitors via a connecting conductor formed on said semiconductor substrate, and the other of said source diffusion layer and said drain diffusion layer serves as one of bit line contact layers, said one of bit line contact layers is shared by two transistors of said transistors which are adjacent to each other in said row directions.