Patent ID: 7478292
Filing Date: 2009-01-13
Classification: G06F,G11C

Abstract:
1. An error detection structure for a multilevel memory device including a plurality of memory cells, each memory cell being programmable at more than two levels and, wherein the levels have an associated sequence, each level in the sequence corresponding to a respective threshold voltage of the memory cell and each level representing a logic value consisting of a plurality of bits, wherein the sequence of levels includes a lower range consisting of the first two or more levels in the sequence and an upper range consisting of the last two or more levels in the sequence, wherein the structure further includes means for partitioning the bits of the levels in the lower range and the bits in the upper range into two subsets, wherein the structure includes means for detecting errors in the values of a selected block of memory cells, and the means for detecting errors operating only on the bits of the second least significant bit subset of the block.