Patent ID: 7716266
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. A hardware arithmetic processor method for performing a combined Multiply-Add floating point operation in any of two or more floating point formats using a floating point arithmetic unit, the operation comprising multiplying a multiplicand value A by a multiplier value C to produce a product value and adding an addend value B to the product value according to the formula A*B+C, the method comprising the steps of: determining a common value, the common value useful for any of said two or more floating point formats having different biases, the common value for determining a shift amount; responsive to the combined Multiply-Add floating point operation being a first floating point format having a first bias value (Bias1), performing the steps a) through c) comprising; a) determining a shift amount (SA1), the determination of the shift amount consisting of arithmetically combining each of a first floating point exponent (ExpA1) of the first format, a second floating point exponent (ExpB1) of the first format, a third floating point exponent (ExpC1) of the first format and the common value (Constant1) wherein b) aligning a third floating point fraction of the first format with a multiplication product value of the first format according to the determined shift amount; and c) adding the aligned third floating point fraction of the first format to the multiplication product value of the first format; and responsive to the combined Multiply-Add floating point operation being a second floating point format having a second bias value (Bias2), said second bias value being different than the first bias value, performing the steps d) through f) comprising: d) determining a shift amount (SA2), the determination of the shift amount consisting of arithmetically combining each of a first floating point exponent (ExpA2) of the second format, a second floating point exponent (ExpB2) of the second format, a third floating point exponent (ExpC2) of the second format and the common value (Constant2), wherein e) aligning a third floating point fraction of the second format with a multiplication product value of the second format according to the determined shift amount; and f) adding the aligned third floating point fraction of the second format to the multiplication product value of the second format; wherein wherein db1 is a distance between floating point radix points of a product of the first format A1*C1 and an addend B1 of the first format and osl1 is a shift-left operand of the first format, wherein db2 is a distance between floating point radix points of a product of the second format A2*C2 and an addend B2 of the second format and osl2 is a shift-left operand of the second format.