Patent ID: 8846475
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: providing a substrate having a shallow trench isolation (STI), with a core oxide layer and an input/output (I/O) oxide layer formed on the substrate and an I/O mask layer formed on the I/O oxide layer; forming an I/O dummy gate on the I/O mask layer and a core dummy gate on the core oxide layer; forming Lightly Doped Drain (LDD) regions on opposite sides of the I/O and core dummy gates using the I/O and core dummy gates as a mask; forming spacers on side surfaces of the I/O and core dummy gates; forming source and drain regions using the spacers and the dummy gates as a mask; forming a nickel silicide (NiSi) layer on the substrate on opposite sides of the I/O dummy gate and the core dummy gate; depositing an etch barrier layer on the substrate covering the I/O dummy gate, the core dummy gate, the STI and the NiSi layer; depositing a dielectric layer on the etch barrier layer; planarizing the etch barrier layer and the dielectric layer to expose a top surface of the I/O dummy gate and a top surface of the core dummy gate; simultaneously removing the I/O dummy gate and the core dummy gate to form an I/O gate groove and a core gate groove; removing the core oxide layer; forming a gate dielectric layer on the substrate in the core gate groove; and forming a high-k dielectric layer in the I/O and core gate grooves; and forming a metal gate layer filling the I/O gate groove and the core gate groove.