Patent ID: 7720899
Filing Date: 2010-05-18
Classification: G06F

Abstract:
1. An information processing apparatus comprising: a multiply adder unit executing a multiply-add arithmetic operation; a shift amount calculator calculating a normalizing shift amount for a result of the arithmetic operation by said multiply adder unit; a normalizer normalizing the arithmetic operation result obtained by said multiply adder unit, by using the normalizing shift amount calculated by said shift amount calculator; a logical sum calculator predicting of whether data in a predetermined region (hereinafter referred to as a first region) comprising least significant bits of the arithmetic operation result is to remain in a sticky bit generation region after the normalizing process by said normalizer, and calculating a logical sum of data that is predicted to remain in the sticky bit generation region as an interim sticky bit, in parallel to the normalizing process by said normalizer; a generator generating a sticky bit on the basis of (i) data in a region (hereinafter referred to as a second region) obtained by excepting a region corresponding to the first region from the sticky bit generation region in the arithmetic operation result, which is normalized by said normalizer, and (ii) the interim sticky bit, calculated by said logical sum calculator; and a rounder rounding the arithmetic operation result normalized by said normalizer on the basis of the sticky bit generated by said generator.