Patent ID: 6359808
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A sense pre-amplifier circuit for a flash memory device capable of simultaneous operation, the flash memory device having a first memory bank of flash memory cells and a second memory bank of flash memory cells, the sense pre-amplifier circuit comprising:a first transistor having a gate, drain and source, wherein the gate of said first transistor is coupled to the first memory bank at the input of the sense pre-amplifier, and the source of said first transistor is coupled to ground; a second transistor having a gate, drain and source, wherein the source of said second transistor is coupled to the drain of said first transistor and the drain of said second transistor is selectively coupled to a voltage source with a voltage level Vcc, the first and second transistors together forming a first inverting amplifier providing a feedback; a third transistor having a gate, drain, and source, wherein the gate of said third transistor is coupled to the drain of said first transistor, and the source of said third transistor is selectively coupled to ground and also coupled to the gate of said first transistor, wherein the gate of said third transistor is coupled to the source of said third transistor by said feedback network; a fourth transistor having a gate, drain, and source, wherein the drain of said fourth transistor is selectively coupled to the voltage source, and the source of said fourth transistor is coupled to the drain of said third transistor, thereby forming a second inverting amplifier, and also coupled to the output of said sense pre-amplifier; and a fifth transistor having a gate, drain, and source, wherein the gate of said fifth transistor is coupled to the drain of said first transistor, and the drain of said fifth transistor is selectively coupled to the voltage source, and the source of said fifth transistor is coupled to the drain of said third transistor.