Patent ID: 6631393
Filing Date: 2003-10-07
Classification: G06F

Abstract:
An adder having an adder width N, for calculating an N bit sum S from an N bit augend A and an N bit addend B, said adder having a plurality of bit slices, each bitslice N comprising:a first circuit for speculatively calculating bit SN based only on bit AN, bit BN, and a limited carry bit; a second circuit for calculating said limited carry bit based only on K bits of said augend and K bits of said addend, wherein K is less than Nâˆ’1; and a third circuit for detecting a potential difference between said limited carry bit and an unlimited carry bit; wherein the adder latency is related to the number of bits, K, in the second circuit; so that the adder latency is independent of the adder width N.