Patent ID: 6235586
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method of forming a NAND type flash memory device, comprising:growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area;removing a portion of the first oxide layer in the flash memory cell area of the substrate;growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area;depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 .ANG. to about 1,000 .ANG.;depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer;depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; andforming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.