Patent ID: 7470590
Filing Date: 2008-12-30
Classification: H01L

Abstract:
1. A method of forming a semiconductor construction, comprising: providing a semiconductor substrate having fuses within a fuse region, having a sacrificial cover across the fuse region and over the fuses, having an insulative cap directly over the fuse region, the insulative cap being at least partially covered by and in physical contact with the sacrificial cover, and having an access node peripheral to the fuse region; the access node and sacrificial cover being electrically conductive and being the same in composition as one another; the semiconductor substrate further comprising electrically insulative spacer material extending between the access node and sacrificial cover; the electrically insulative spacer material directly contacting sidewalls of the access node and the sacrificial cover; the electrically insulative spacer material, access node and sacrificial cover together comprising a planarized surface that extends across the electrically insulative spacer material, access node and sacrificial cover; forming a patterned electrically insulative material over the substrate, the patterned material having a first opening extending therethrough to said access node, and having a second opening extending therethrough to the sacrificial cover; forming an electrically conductive material over the patterned material and within the first and second openings; patterning the electrically conductive material into one or more interconnects; during said patterning, removing at least some of the sacrificial cover to form an opening extending entirely through the sacrificial cover thereby exposing a portion of the insulative cap previously covered by the sacrificial cover, the exposed portion forming at least part of a lower surface of the opening; and directing energy through the portion of the insulative cap exposed as a result of the removing of the at least some of the sacrificial cover to break one or more of the fuses.