Patent ID: 9123630
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A stacked chip package, comprising: a package substrate; at least a first chip stacked on the package substrate at a first height above the package substrate and electrically connected to the package substrate; and at least a second chip stacked on the package substrate at a second height above the first height and electrically connected to the package substrate, part of the second chip overlapping part of the first chip in a vertical direction and part of the second chip not overlapping the first chip in the vertical direction; wherein: both the first chip and the second chip are flip chips electrically connected to the package substrate using a flip chip configuration, the first chip is electrically connected to the package substrate using a direct flip chip connection, and the second chip is electrically connected to the package substrate using a flip chip connection to an interposer disposed between the second chip and the package substrate.