Patent ID: 6444509
Filing Date: 2002-09-03
Classification: H01L,Y10S

Abstract:
A method of fabricating a one-gate thin film transistor, having an active region and a gate, wherein said active region comprises a poly-Si1âˆ’xGex alloy material and channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1âˆ’xGex alloy material and the gate, comprising:depositing a gate, depositing an active region comprising a poly-Si1âˆ’xGex alloy material layer and a channel layer of silicon, to form a composite, and treating the composite with at least one method selected from the group consisting of crystallization and excimer laser annealing, wherein said depositing a gate occurs subsequent to said depositing an active region and said treating the composite, wherein x ranges from 0.05 to 0.4 atomic %.