Patent ID: 6337497
Filing Date: 2002-01-08
Classification: H01L

Abstract:
Method for storing a bit in a memory device comprising at least one cell which hasa vertical field effect transistor with a source, drain and gate, said vertical field effect transistor is formed on a semiconductor substrate and further comprising a pillar serving as a gate channel between said source and drain, said gate channel being continuous with said substrate and being composed of the same material as the substrate, and a capacitor with a first and second electrode, said capacitor being situated on top of said pillar and said electrode being interconnected with said drain, said source being connected to a supply voltage, said second electrode being connected to a bitline, and said gate being connected to a word line, said method comprising the steps of: driving said bitline to 0 volts; and selecting said cell by applying a voltage to said word line such that said capacitor is charged and a voltage of about said supply voltage is built up between its first and second electrodes.