Patent ID: 6020901
Filing Date: 2000-02-01
Classification: G09G

Abstract:
A frame buffer system for use with a video display system that is useable with a computer system, comprising:a frame buffer random access memory sub-system (FBRAM) including a source of digital video data, said FBRAM sub-system storing processed said video data to be displayed by said video display system;a controller unit including a video refresh generator and a command unit coupled to said video refresh generator, coupled to said FBRAM sub-system and to said computer system, said command unit and said video refresh generator providing transfer commands to said FBRAM sub-system including at least one command reflecting state of video refresh required for said video display system; anda digital-to-analog converter sub-system, coupled to said controller unit and to said FBRAM sub-system, for format-converting said video data for display by said video display system, said digital-to-analog converter sub-system further including a video timing generator that provides timing signals to said frame buffer system.