Patent ID: 6662443
Filing Date: 2003-12-16
Classification: H05K,Y10T

Abstract:
A method of fabricating a multilayer interconnected substrate, the method comprising:providing a structure comprising a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface, a first conductive layer disposed on the first substantially planar surface of the dielectric substrate, and an interface between the first conductive layer and the dielectric substrate: forming a blind via site in the structure, wherein the blind via site extends through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate; filling the blind via site with a conductive material by an electrolytic plating process which includes making an electrical connection to the first conductive layer; and laminating a second conductive layer substantially across the majority of the second substantially planar surface of the dielectric substrate, wherein the laminated second conductive layer is connected to the filled blind via site.