Patent ID: 6242939
Filing Date: 2001-06-05
Classification: G11C,H03K

Abstract:
A superconducting random access memory comprising:plural memory cell blocks each including plural random access memory cells and a first peripheral circuit used for selectively accessing data stored in said plural random access memory cells,said first peripheral circuit havinga decoder circuit formed by using superconducting single flux quantum devices biased with direct current and producing decoded address signals from an address signal, anda driver circuit formed by using superconducting latching devices biased with alternating current and connected between said decoder circuit and said plural random access memory cells so as to render said plural random access memory cells selectively accessible;a second peripheral circuit associated with said plural random access memory blocks, and includinga block decoder rendering said plural random access memory blocks selectively accessible, andplural block driver circuits formed by using superconducting latching devices and connected at least between said block decoder and said plural random access memory blocks for propagating decoded signals from said block decoder to said plural random access memory blocks; andsignal propagation lines connected between said plural block driver circuits, impedance matching being achieved between said signal propagation lines and said plural block driver circuits.