Patent ID: 6067329
Filing Date: 2000-05-23
Classification: H04L

Abstract:
A Vestigal Sideband (VSB) demodulator for use with a VSB signal, said demodulator comprising:a clock generator for generating a clock signal based on a symbol frequency of the VSB signal,an A/D converter for converting the VSB signal into a digital signal based on the clock signal of the clock generator,a first multiplier for i) multiplying the digital signal by a first value sequence based on the clock signal of the clock generator and ii) generating a first multiplier output signal,a second multiplier for )i multiplying the digital signal by a second value sequence based on the clock signal of the clock generator and ii) generating a second multiplier output signal,a complex type filter for i) shaping and VSB demodulation of the first multiplier output signal and the second multiplier output signal and ii) generating an Inphase data output signal and a Quadrature data output signal,a first decimating circuit for i) decimating the Inphase data output signal and ii) generating a first decimated signal,a second decimating circuit for i) decimating the Quadrature data output signal and ii) generating a second decimated signal,a complex multiplier for i multiplying the first decimated signal and the second decimated signal by a predetermined value and ii) generating a multiplied output signal,an error detector for i) detecting a frequency deviation and a phase deviation from the multiplied output signal of the complex multiplier, and ii) generating the predetermined value for the complex multiplier, andDC offset canceler for removing a DC component from a portion of the multiplied output signal of the complex multiplier.