Patent ID: 8878301
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate with a main surface; an n-channel first transistor and a p-channel second transistor formed over the main surface and adapted to form a logic circuit; and an n-channel third transistor and a p-channel fourth transistor formed over the main surface and adapted to form an input/output circuit, wherein the first and third transistors have n-type source and drain regions, wherein the second and fourth transistors have p-type source and drain regions, wherein a distance from the main surface to a lowermost part of the source and drain regions of the third transistor is longer than that from the main surface to a lowermost part of the source and drain regions of the first transistor, wherein a distance from the main surface to a lowermost part of the source and drain regions of the fourth transistor is longer than that from the main surface to a lowermost part of the source and drain regions of the second transistor, and wherein a distance from the main surface to the lowermost part of the source and drain regions of the third transistor is longer than that from the main surface to the lowermost part of the source and drain regions of the fourth transistor.