Patent ID: 9087921
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method of forming a CMOS structure, the method comprising: providing a silicon-on-insulator substrate having a first substrate surface in a first region and a second substrate surface in a second region, wherein the first substrate surface and the second substrate surface are isolated by a shallow trench isolation; forming a first gate stack on the first substrate surface and a second gate stack on the second substrate surface; forming a first insulating layer on all exposed surfaces in the first and second regions; etching the first insulating layer in the second region to form insulating spacers on sidewalls of the second gate stack; forming raised epitaxial source and drain layers on the second substrate surface; forming a layer of undoped epitaxial silicon on the raised epitaxial source and drain layers on the second substrate surface; oxidizing a top surface of the layer of undoped epitaxial silicon to form a hard mask layer; etching the first insulating layer in the first region to form insulating spacers on sidewalls of the first gate stack and to expose the first substrate surface; forming in-situ doped epitaxial source and drain layers on the first substrate surface; removing the oxidized layer of undoped epitaxial silicon from the raised epitaxial source and drain layers on the second substrate surface; if the source and drain layers on the second substrate surface are undoped, implanting a dopant into the source and drain layers on the second substrate surface; and with the insulating spacers still remaining on the sidewalls of the first and second gate stacks, forming silicide contacts on the source and drain layers in both the first and second regions and on the first and second gate stacks.