Patent ID: 8541306
Filing Date: 2013-09-24
Classification: H01L

Abstract:
1. A method of forming patterns of a semiconductor device, comprising: forming a conductive layer and an insulating layer on a substrate and forming a first patterned mask on the insulating layer; forming a first spacer layer having a thickness equal to a selected target width on the first patterned mask and the insulating layer; etching the first spacer layer to expose at least a top surface of the first patterned mask and form a plurality of first spacers on a sidewall of the first patterned mask; removing the first patterned mask; etching the insulating layer using the plurality of first spacers as an etch mask to form a second patterned mask; forming a second spacer layer to a thickness equal to the target width on the conductive layer and the second patterned mask; etching the second spacer layer to form a plurality of second spacers on a sidewall of the second patterned mask and removing the second patterned mask; and etching the conductive layer using the plurality of second spacers as an etch mask to form conductive lines with the target width, wherein the first patterned mask defines protrusions arranged at a first interval, the first interval being substantially equal to or slightly less than quadruple of the target width and being two target widths larger than the conductive lines of the conductive layer formed in pad regions in which neighboring second spacers are combined together.