Patent ID: 6555464
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising steps of:(a) forming a first interlayer insulating layer on a first stopper insulating layer; (b) forming a second stopper insulating layer on said first interlayer insulating layer; (c) forming a second interlayer insulating layer on said second stopper insulating layer; (d) forming a wiring groove pattern layer on said second interlayer insulating layer; (e) forming a hole pattern layer on said second interlayer insulating layer; (f) etching said second interlayer insulating layer and said second stopper insulating layer, using said hole pattern layer as a mask to form a hole pattern in said second stopper insulating layer; (g) after said step (f), removing said hole pattern layer; (h) after said step (g), etching said second interlayer insulating layer, using said wiring groove pat tern layer as a mask and using said second stopper insulating layer as an etching stopper, to form a wiring groove pattern into said second interlayer insulating layer, and etching said first interlayer insulating layer, using said second stopper insulating layer having said hole pattern layer as a mask and using said first stopper insulating layer as an etching stopper, to form a hole pattern into said first interlayer insulating layer; (i) after said step (h), removing said second stopper insulating layer in said wiring groove pattern; and (j) after said step (i), burying a conductive layer in said wiring groove pattern and in said hole pattern.