Patent ID: 8638850
Filing Date: 2014-01-28
Classification: H04N

Abstract:
1. A digital processor for decoding an input bitstream that has been encoded according to a context adaptive binary arithmetic coding (CABAC) algorithm, the processor comprising: a first execution unit; a second execution unit; and a distribution unit coupled to the first execution unit and the second execution unit, and configured to fetch a stream of instructions, wherein the stream of instructions includes a first instruction and a second instruction, wherein the distribution unit is configured to: wherein, in response to the distribution unit's scheduling of execution of the decoded first instruction, the first execution unit is configured to generate a current output bit, a temporary range value and a temporary offset value based at least on a current range value and a current offset value, wherein the current offset value includes one or more bits of the input bitstream; wherein, in response to the distribution unit's scheduling of execution of the decoded second instruction, the second execution unit is configured to generate an update for the current range value and an update for the current offset value by normalizing respectively the temporary range value and the temporary offset value.