Patent ID: 7239551
Filing Date: 2007-07-03
Classification: G11C

Abstract:
1. A method of programming a plurality of non-volatile memory cells among an array thereof in parallel with reduced error due to perturbing electric fields from neighboring memory cells, comprising: (a) organizing said plurality of memory cells into a page of contiguous memory cells among the array sharing a common word line; (b) providing a corresponding page of read/write circuits for servicing said page of contiguous memory cells; (c) sensing the memory cells of said page in parallel with the page of read/write circuits to verify the memory state of each memory cell relative to respective target states to be programmed; (d) inhibiting each memory cell among said page that has been verified; (e) applying a programming pulse to said page of contiguous memory cells via the common word line; and (f) repeating steps (c)–(e) until all memory cells of said page have been verified.