Patent ID: 7890905
Filing Date: 2011-02-15
Classification: G06F

Abstract:
1. A computer system comprising: one or more processors which process program instructions; a memory device connected to said one or more processors; and program instructions residing in said memory device for providing a buffer tree for a net of an integrated circuit design by building an initial solution set for the buffer tree from initial solutions for sinks of the net wherein solutions have associated cost, slew and capacitance components, generating sets of candidate solutions for wire branches of the net which originate at the sinks and extend toward a source of the net wherein the candidate solutions have associated cost, slew and capacitance components derived by selectively inserting at least one buffer along a given wire branch, setting the slew component of a candidate solution for the given wire branch to zero, incrementing the cost component of the candidate solution based on the inserted buffer, setting the capacitance component of the candidate solution to an intrinsic capacitance of the inserted buffer, increasing the capacitance component of the candidate solution by adding a wire capacitance of any new wire section connected between the source and the inserted buffer, and increasing the slew component of the candidate solution by adding a wire slew of the new wire section, merging candidate solutions for two wire branches by summing the capacitance components of the two wire branches, summing the cost components of the two wire branches, and selecting a maximum slew component from the two wire branches, updating the candidate solution sets by disregarding any candidate solutions whose slew component is greater than a slew constraint, and selecting a final solution which has a smallest cost component from updated candidate solution sets.