Patent ID: 6323523
Filing Date: 2001-11-27
Classification: H01L

Abstract:
An ESD protective circuit formed on a p-type silicon substrate structure for protecting an internal device circuit comprising:a n-type pull-up transistor having a first drain region, a first source region and a first gate, said first drain region connected to a power terminal;a n-well region formed in said p-type silicon substrate, and being adjacent said first drain region, and having a n-type region and a p-type region therein, both of them being connected to said power terminal;a n-type pull-down transistor having a second source region, a second drain region and a second gate, said second source region connected to a voltage ground terminal, said second gate and said first gate being coupled to an I/O terminal of said internal device circuit, said first source region and said second drain region connected to an I/O pad; anda p+ guardring around said pull down transistor connected to said voltage ground terminal.