Patent ID: 7889816
Filing Date: 2011-02-15
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit comprising: a clock output unit configured to output N-phase clocks each of which has a phase shifted from the others by a time T a sampling unit configured to obtain sampling data serially transferred at every time T a first conversion unit configured to convert the sampling data into first N-bit parallel data every period P a second conversion unit configured to convert the first N-bit parallel data into second N-bit parallel data indicating a change point in the sampling data; and a data output unit configured to use the second N-bit parallel data as input of phase information and output third N-bit parallel data indicating substantially a center position of the change point in the sampling data, wherein data of the first N-bit parallel data at a position equal to substantially the center position indicated by the third N-bit parallel data is determined to be recovered data.