Patent ID: 8975125
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: providing a material stack that includes, from bottom to top, of a semiconductor layer, a doped semiconductor layer that is present on a surface of the semiconductor layer, and an undoped silicon germanium layer that is present on the doped semiconductor layer; forming at least one fin structure from the material stack by etching completely through the undoped silicon germanium layer, completely through the doped semiconductor layer, and only partially through the semiconductor layer, wherein the at least one fin structure is located on a non-etched portion of the semiconductor layer and comprises, from bottom to top, a semiconductor layer portion, a doped semiconductor layer portion, and a doped silicon germanium layer portion, wherein sidewall surfaces of the semiconductor layer portion, the doped semiconductor layer portion, and the doped silicon germanium layer portion are vertically coincident with each other; forming a supporting material in contact with at least a portion of at least one fin structure; removing the doped semiconductor layer portion of the at least one fin structure with an anodization process to provide a void between the semiconductor layer portion and the undoped silicon germanium layer portion; depositing a dielectric layer to fill the void that is present between the semiconductor layer portion and the undoped silicon germanium layer portion; and forming a source region and a drain region on a channel portion of the at least one fin structure.