Patent ID: 6294805
Filing Date: 2001-09-25
Classification: H01L,Y10S

Abstract:
An integrated circuit ferroelectric memory device comprising:an integrated circuit substrate including an elongated active region therein;a pair of spaced apart word lines which cross the elongated active region;a drain region in the elongated active region between the pair of word lines;a pair of source regions in the elongated active region, a respective one of which is outside the pair of spaced apart word lines on opposite sides of the drain region;a first interlayer dielectric layer on the integrated circuit substrate and the pair of spaced apart word lines;a pair of ferroelectric capacitors outside the elongated active region, a respective one of which is adjacent a respective one of the pair of source regions, each of the ferroelectric capacitors comprising spaced apart first and second electrode layers that are adjacent to and remote from the integrated circuit substrate, respectively, and a ferroelectric layer therebetween, each ferroelectric layer including first and second opposing faces, the first face being adjacent the first electrode layer and the second face being adjacent the second electrode layer, and a sidewall extending between the first and second opposing faces, the first electrode layers of the pair of ferroelectric capacitors being spaced apart from one another and the second electrode layers of the pair of ferroelectric capacitors being spaced apart from one another;a first diffusion barrier layer directly on each of the ferroelectric layer sidewalls and directly on each of the ferroelectric layer second faces, the first diffusion barrier layer having a first pair of contact holes and a second pair of contact holes therein, the respective one of the second electrode layers extending through a respective one of the first pair of contact holes to directly electrically connect to a respective one of the ferroelectric layers;a second diffusion barrier layer directly on each of the second electrode layers, opposite the ferroelectric layer, and directly on the first diffusion barrier layer, the second diffusion barrier layer having a third pair of contact holes and a fourth pair of contact holes therein;a second interlayer dielectric layer on the second diffusion barrier layer;a bit line that extends from the second interlayer dielectric layer through the second diffusion barrier layer, the first diffusion barrier layer, and the first interlayer dielectric layer to electrically connect to the drain region;a pair of lower electrode wires, a respective one of which electrically connects a respective one of the first electrode layers to a respective one of the pair of source regions, the respective one of the pair of lower electrode wires extending from the second interlayer dielectric layer through a respective one of the second pair of contact holes and a respective one of the fourth pair of contact holes to electrically connect to the respective one of the first electrode layers, and the respective one of the pair of lower electrode wires extending from the second interlayer dielectric layer through the second diffusion barrier layer, the first diffusion barrier layer, and the first interlayer dielectric layer to electrically connect to the respective one of the pair of source regions;a third interlayer dielectric layer on the second interlayer dielectric layer, the pair of lower electrode wires, and the bit line; anda pair of plate lines, a respective one of which extends from the third interlayer dielectric layer through the second interlayer dielectric layer and a respective one of the third pair of contact holes to electrically connect to the respective one of the second electrode layers;wherein the pair of plate lines and the pair of word lines extend parallel to each other and perpendicular to the bit line.