Patent ID: 6125057
Filing Date: 2000-09-26
Classification: G11C

Abstract:
An integrated circuit having a memory array comprising a plurality of rows of memory cells, wherein:each memory cell is in a column of the memory array and is coupled at an output terminal to a prechargeable column output line for the column, wherein each column output line is coupled to a sense amp for detecting discharges of its respective column output line;the rows of the memory array are divided into a plurality of words;each memory cell of a given word is coupled at a source terminal to a local source line for the word, wherein, during an evaluation period of a read cycle during which a given word of a given row is to be read in accordance with an address, the sense amps associated with the word are enabled by a respective sense amp enable signal provided by memory control logic in response to the address; andthe local source line for each word of the memory array is selectively coupleable to ground through a switch which is controlled by the sense amp enable signal for the word to which the local source line belongs.