Patent ID: 6979853
Filing Date: 2005-12-27
Classification: H01L

Abstract:
1. A memory cell, comprising: a substrate formed with a trench hole defining a lower region and an upper region, and a horizontal bit line extending in a bit line direction, said trench hole having broad sides; a trench capacitor formed at said lower region of said trench hole, said trench capacitor having: a vertical selection transistor formed at said upper region of said trench hole, said selection transistor having: a horizontally running word line with gate region laterally adjoining said channel region and electrically insulated therefrom, said word line with gate region extending perpendicularly to said bit line; said vertically running channel region of said selection transistor extending through said horizontally running word line with gate region to said bit line above said channel region; said word line with gate region at least partially or completely enclosing said channel region; and said channel region, in a plan view, being disposed transversely with respect to said word line with gate region and, as seen in the bit line direction, extending substantially along one of said broad sides of said trench hole and approximately corresponding to an extent of said broad side of said trench hole.