Patent ID: 7345906
Filing Date: 2008-03-18
Classification: G11C

Abstract:
1. A method of reading a memory cell in a passive-matrix addressable ferroelectric or electret memory array with memory cells in the form of electret or ferroelectric capacitors, wherein the memory cells are being located at the crossings of a first and second set of respective parallel electrodes, the first set forming word lines and the second set forming bit lines, wherein the word lines and the bit lines are connected to driving means, wherein the bit lines have connection to sensing means for measuring charge flowing in the bit lines, wherein the sensing means in a read operation senses a current response signal corresponding to the data, typically a binary one or a binary zero, wherein the method comprises: a) starting a charge measurement by activating the sensing means connected to the bit line of the memory cell, b) registering a first value from the charge measurement, and c) applying a voltage with switching capability over the memory cell by driving the electrodes using a predefined set of read voltage levels, and d) registering a second value from the charge measurement, deducting the first registered value from the second registered value to form a readout value.