Patent ID: 6064271
Filing Date: 2000-05-16
Classification: G11B,H03L

Abstract:
A voltage controlled oscillator circuit comprising:a first delay cell array including a plurality of delay cells each having a first gate for receiving a first control voltage signal and a second gate, the first delay cell array having an input terminal for receiving a reference clock signal and an output terminal for outputting a delayed clock signal of the reference clock signal;a ring oscillator having a second delay cell array including a plurality of delay cells each having a first gate for receiving a second control voltage signal and a second gate, the second delay cell array having an input terminal and an output terminal, the ring oscillator for outputting from the output terminal of the second delay cell array a signal of a frequency determined by a time delay of the second delay cell array;a selection circuit provided for at least one of the first and second delay cell arrays, for selecting the number of delay cells out of said at least one delay cell array; anda phase detector for comparing in phase the reference clock signal with the delayed clock signal outputted by said first delay cell array to output a comparison signal, and inputting the comparison signal to the second gates of the delay cells of the first delay cell array and the second gates of the delay cells of the second delay cell array.