Patent ID: 7368955
Filing Date: 2008-05-06
Classification: G11C

Abstract:
1. A circuit, comprising: a first sense amplifier; a second sense amplifier; and a current-source transistor to provide bias current to the first and second sense amplifiers, the first and second sense amplifiers being alternately activated by first and second differential clock signals respectively, wherein: the first sense amplifier includes differential output data lines which are driven to a same value when the first differential clock signal assumes a first logical value, the second sense amplifier includes differential output data lines which are driven to a same value when the second differential clock signal assumes the first logical value, the circuit further comprising: a first isolation circuit to drive the differential output data lines of the first sense amplifier to the same value when the first differential clock signal assumes the first logical value; and a second isolation circuit to drive the differential output data lines of the second sense amplifier to the same value when the second differential clock signal assumes the first logical value.