Patent ID: 6535218
Filing Date: 2003-03-18
Classification: G06T,G09G

Abstract:
A frame buffer memory, comprising:a memory array for storing pixel data; a pixel buffer coupled to the memory array; a plurality of pixel arithmetic-logic units coupled to the pixel buffer; an input data formatter coupled to the plurality of pixel arithmetic-logic units and coupled to a rendering bus which is external to the frame buffer memory; an output data formatter coupled to the pixel buffer and to the external rendering bus; a write data formatter coupled to the plurality of pixel arithmetic-logic units and to the pixel buffer; a read data formatter coupled to the pixel buffer and to the plurality of pixel arithmetic-logic units; and an address and control input bus coupled to the memory array, the pixel buffer, the plurality of pixel arithmetic-logic units, the input data formatter, the output data formatter, the write data formatter, the read data formatter and to an address and control bus which is external to the frame buffer memory.