Patent ID: 9026969
Filing Date: 2015-05-05
Classification: G06F

Abstract:
1. A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device, the method comprising: determining, by a grid determining unit, a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in the stacked semiconductor device; creating, by a path graph generating unit, a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining, by a TSV positioning unit, initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining, by a verifying unit, final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks for the signals have routability, wherein at least one of the determining the plurality of TSV candidate grids, the creating the plurality of path graphs, the determining the initial TSV insertion positions, and the determining the final TSV insertion positions is performed by a computer.