Patent ID: 8872262
Filing Date: 2014-10-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate comprising a cell array region including a cell central region and a cell edge region, and a peripheral circuit region; cell gate patterns extending from the cell central region to the cell edge region, each comprising a cell gate capping pattern on a cell gate in the cell central region, wherein an upper surface of a cell gate in the cell edge region is beneath a surface of a device isolation layer; an interlayer insulating layer on the cell edge region and on the peripheral circuit region, having a contact hole extending therethrough into the device isolation layer in the cell edge region, exposing a portion of the upper surface of the cell gate in the cell edge region; and a connection line in the contact hole extending through the interlayer insulating layer and into the device isolation layer to contact an entire width of the portion of the upper surface of the cell gate in the cell edge region, and wherein the connection line contacts the device isolation layer.