Patent ID: 8673716
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit comprising: providing a semiconductor substrate having a core region and a periphery region; implanting a threshold adjustment implant in the semiconductor substrate; depositing a charge-trapping dielectric material in the core region; depositing a gate dielectric material in the periphery region; depositing bitline photoresist layer over the gate dielectric material in the periphery region; forming bitlines in the semiconductor substrate in the core region and not in the periphery region, the bitlines spaced apart with the threshold adjustment implant in between thereof; removing the bitline photoresist layer; forming a wordline-gate material; implanting the wordline-gate material with wordline dopant in the core region and not in the periphery region; forming a wordline and a gate; implanting the semiconductor substrate around the gate with source/drain junctions; and implanting the gate with a gate dopant in the periphery region and not in the core region, the gate dopant the same type dopant as the wordline dopant.