Patent ID: 6309939
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:forming gate electrodes on a semiconductor substrate having a cell region and a peripheral region;forming spacers on both sidewalls of said gate electrodes;implanting impurity into said semiconductor substrate of said peripheral region;forming a growth suppression layer on gate electrodes and surface of said semiconductor substrate in said peripheral region;forming doped epitaxial layers over predetermined portions of said semiconductor substrate in said cell region so that said impurity implanted into said semiconductor substrate in said peripheral region is diffused in said semiconductor substrate to form junction regions and impurity existing in said doped epitaxial layers of said cell region is diffused into said semiconductor substrate, wherein said doped epitaxial layers are formed by performing a baking process for 1 to 5 minutes under temperature of 800 to 900 degrees Celsius and hydrogen environment and by performing a growing process for 3 to 10 minutes in in-situ with supplying of dichlorosilane (DCS) of 30 to 300 sccm, phosphine of 50 to 300 sccm and HCl of 30 to 200 sccm under pressure of 10 to 50 torr and temperature of 750 to 950 degrees Celsius; andremoving said growth suppression layer.