Patent ID: 8674739
Filing Date: 2014-03-18
Classification: H03K

Abstract:
1. An integrated circuit device comprising: a critical evaluation path that inverts a data input and outputs a corresponding state output during a first clock state of a clock signal, wherein the critical evaluation path includes no more than a single inverter; and a storage feedback loop connected in parallel with the critical evaluation path, wherein the storage feedback loop comprises a latch element that latches the data input; wherein the storage feedback loop comprises a latch element connected in parallel to the critical evaluation path by way of two tri-state inverters, wherein one of the tri-state inverters is enabled by the first clock state and the other tri-state inverter is enabled by the opposite clock state; and further wherein the latch element comprises first and second inverter elements connected in a loop, the first inverter being a tri-state inverter enabled by the opposite clock state and having an output coupled to an input of the second inverter, the output of the second inverter being an input to the first inverter and an output of the latch element.