Patent ID: 9153599
Filing Date: 2015-10-06
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate comprising a display area and a peripheral area outside the display area; a gate line disposed in the display area of the substrate; a driver connection line disposed in the peripheral area of the substrate; a gate insulating layer disposed on the gate line and the driver connection line; a data line disposed on the gate insulating layer in the display area of the substrate; a plurality of driving pads disposed on the gate insulating layer in the peripheral area of the substrate; a first insulating layer disposed on the data line and the driving pad; a second insulating layer disposed on the first insulating layer in the display area of the substrate; a first field generating electrode disposed on the second insulating layer in the display area of the substrate; a third insulating layer disposed on the substrate on the first field generating electrode; a second field generating electrode disposed on the third insulating layer in the display area of the substrate; and a first connecting member disposed on the third insulating layer and covering the plurality of driving pads, wherein the gate line and the driver connection lines are formed with the same layer material, the data line and the driving pad are formed with the same layer material, and the second field generating electrode and the first connecting member are formed with the same layer material.