Patent ID: 6306696
Filing Date: 2001-10-23
Classification: H01L,Y10S

Abstract:
A method of fabricating a bottom and top gated thin film transistor, comprising:forming a bottom gate layer on a semiconductor substrate;forming a bottom gate dielectric layer over the bottom gate layer;forming a layer of semiconductive material over the bottom gate dielectric layer;defining source, drain and channel regions within the layer of semiconductive material;forming a top gate dielectric layer over the layer of semiconductive material;forming a top gate layer over the top gate dielectric layer;etching the composite top gate, top gate dielectric, and semiconductive material layers in a pattern which defines a top gate, top gate dielectric and body outline, the bottom gate including a portion extending outwardly beyond the outline, the etching defining an exposed top gate sidewall surface and an exposed sidewall surface of the semiconductive material;forming a layer of insulating dielectric over the etched top gate and exposed sidewall surfaces;anisotropically etching the insulating dielectric layer to define an insulating sidewall spacer, the sidewall spacer leaving the top gate sidewall surface exposed;exposing a portion of the bottom gate extending outwardly beyond the outline;forming a layer of electrically conductive material over the outwardly exposed top gate sidewall surface and exposed portion of the bottom gate; andanisotropically etching the layer of conductive material to define an electrically conductive sidewall link electrically interconnecting the top gate sidewall surface and the bottom gate.