Patent ID: 7921275
Filing Date: 2011-04-05
Classification: G06F

Abstract:
1. A data processing system comprising: a processor; a memory coupled to the processor and including a plurality of physical locations with real addresses that are utilized for storing data; at least one lower level cache that buffers data from memory for utilization during processor execution; processing logic that completes an asynchronous memory move (AMM) operation, wherein: the processor receives an AMM store (ST) instruction and performs a processor-level, effective address move of data from a first effective address to a second effective address and the processor continues processing subsequently received instructions while an address translation followed by a physical move of the data is being completed; and asynchronous memory mover logic then completes the address translation and the physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address; a memory controller having logic that responds to the receipt of the data for the AMM operation by forwarding a first portion of the data to the at least one lower level cache and forwards a remaining portion of the data to the memory, whereby access latency for subsequent processor request for the data is reduced.