Patent ID: 8269203
Filing Date: 2012-09-18
Classification: G11C,H01L,H03K,Y10S

Abstract:
1. A resistive random access memory device formed on a semiconductor substrate and comprising: an interlayer dielectric formed on the semiconductor substrate and having a via formed therethrough; a chemical-mechanical-polishing stop layer formed over the interlayer dielectric, the via formed through the chemical-mechanical-polishing stop layer; a barrier metal liner lining walls of the via; a conductive plug formed in the via; a first barrier metal layer formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug; a dielectric layer formed over the first barrier metal layer; an ion source layer formed over the dielectric layer; edges of the first barrier metal layer, the dielectric layer, and the ion source layer being in substantial alignment with each other to form an aligned stack disposed directly over the conductive plug, edges of the aligned stack extending beyond outer edges of the barrier metal liner; a dielectric barrier layer formed over the aligned stack and at least a portion of the chemical-mechanical-polishing stop layer, the dielectric barrier layer including a via formed therethrough communicating with the ion source layer; a second barrier metal layer formed over the dielectric barrier layer and in electrical contact with the ion source layer, the second barrier metal layer extending over at least a portion of the chemical-mechanical-polishing stop layer; and a metal interconnect layer formed over the barrier metal layer.