Patent ID: 6246064
Filing Date: 2001-06-12
Classification: B82Y,H01J

Abstract:
An electron beam drawing process for drawing a desired pattern superimposed on a pattern previously drawn on a plurality of chips set on a wafer, by scanning said wafer with an electron beam, comprising the steps of:detecting marks, formed by an optical reduction exposure apparatus, in said previously drawn pattern in said chip, for a predetermined number of chips;determining the relation between at least one of a shape distortion and an array error of each chip in a wafer plane and wafer coordinates, obtained from the positions of the detected marks, and the designed positions of said marks, by a statistical processing; anddrawing patterns in all chips while correcting the patterns to be drawn on said individual chips, by using the determined relation between at least one of the chip shape distortion and the array error of each chip and said wafer coordinates.