Patent ID: 6178120
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A memory structure for speeding up data access, said memory structure storing data to be addressed by an address bus including a row address supplied by a row address bus and a column address supplied by a column address bus, said memory structure comprising:a memory unit having a plurality of memory cells for storing data therein;a row decoder for decoding said row address to address said memory cells;a plurality of data latch units, each having at least two latches, for optionally latching the data in said memory cells addressed by said row address into one of said latches of each data latch unit;a logic unit for determining, based on previous addresses supplied by said row address bus, whether the data of said memory cells addressed by said row address is stored in said plurality of data latch units, and, if the data of said memory cells addressed by said row address is not stored in said plurality of data latch units, selecting one of said latches of each data latch unit to latch the data of said memory cells addressed by said row address; anda column decoder for decoding said column address to access data addressed by said address bus from said plurality of data latch units.