Patent ID: 7323383
Filing Date: 2008-01-29
Classification: H01L

Abstract:
1. A method for fabricating an NROM memory cell array, the method comprising: providing a semiconductor body; introducing an implantation of dopant at a top side of the semiconductor body in order to form source/drain regions; etching trenches into the semiconductor material, the trenches being arranged parallel at a distance from one another; forming a plurality of bit lines on the top side of the semiconductor body, the bit lines running parallel to the trenches and each bit line arranged between two adjacent trenches, each bit line being electrically conductively connected to source/drain regions located between the adjacent trenches; providing a covering layer for electrical insulation on the top side of the semiconductor body; implanting a dopant into the semiconductor body at bottoms of the trenches in order to form a doped region that affects electrical properties of a channel region provided there; applying a storage layer at least at walls of the trenches; arranging gate electrodes in the trenches at predetermined distances, the gate electrodes being electrically conductively connected to word lines that are applied in a manner such that they run transversely with respect to the direction of the bit lines, wherein the dopant at the bottoms of the trenches remains between the word lines; and in regions between the word lines, etching away the semiconductor body at the bottoms of the trenches to an extent such that the doped regions between the word lines are at least partially removed.