Patent ID: 7352633
Filing Date: 2008-04-01
Classification: G11C,H01L

Abstract:
1. A memory, comprising: a cell having a plurality of bit subcells, each bit subcell being adapted to store a bit of a common word, wherein said bit subcells are arranged in an array within said cell, said array having a plurality of bit subcells in a longitudinal direction and a plurality of bit subcells in a transverse direction; wherein said longitudinal and transverse directions are orthogonal, said cell has four bit subcells, wherein said array is a 2 by 2 array of bit subcells within said cell, said cell has a word line electrically coupled to each subcell, each subcell has a bit line output and at least one subcell has a transistor having a control input electrically coupled to a word line and an output electrically coupled an associated bit line output of said at least one bit subcell, and said word line comprises a conductive metal strapping line positioned across said cell, and a pair of semiconductor lines, each semiconductor line being positioned across a pair of bit subcells of said 2 by 2 array of bit subcells and electrically coupled to a control input of a transistor if present within a bit subcell of said pair of bit subcells, each semiconductor line further being electrically coupled to said strapping line.