Patent ID: 8839059
Filing Date: 2014-09-16
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. functional logic having parallel stimulus inputs and parallel response outputs; B. serial stimulus data leads, expected data leads, and mask data leads; C. a first serial scan path part having a serial stimulus data input coupled to a first one of the serial stimulus data leads, parallel stimulus outputs coupled to first parallel stimulus inputs, parallel response inputs coupled to first parallel response outputs, and a first serial response data output; D. a second serial scan path part having a serial stimulus data input coupled to a second one of the serial stimulus data leads, parallel stimulus outputs coupled to second parallel stimulus inputs, parallel response inputs coupled to second parallel response outputs, and a second serial response data output; E. first compare and mask circuitry having a first serial response data input coupled to the first serial response data output, a first expected data input coupled to a first expected data lead, a first mask data input coupled to a first mask data lead, and a first fail flag output; and F. second compare and mask circuitry having a second serial response data input coupled to the second serial response data output, a second expected data input coupled to a second expected data lead, a second mask data input coupled to a second mask data lead, and a second fail flag output.