Patent ID: 9129947
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A multi-chip packaging structure, comprising: a) N chips, wherein N is an integer of at least two, and wherein an upper surface of each chip comprises a plurality of pads; b) a lead frame with a chip carrier and a plurality of pins, wherein said N chips are stacked in layers on said chip carrier, and wherein a first chip of said N chips situated in an upper layer comprises a control and driving circuit and partially covers a second chip of said N chips situated in a lower layer such that said plurality of pads of said second chip are exposed, and wherein said second chip comprises a power transistor; c) a plurality of first bonding leads configured to connect pads on said first chip to pads on said second chip, wherein a first of said plurality of pins is configured to withstand a high voltage, and wherein a second of said plurality of pins comprises a no connect pin; and d) a plurality of second bonding leads configured to connect pads on said first and second chips to said plurality of pins for external connection to said multi-chip packaging structure, wherein said first pin is directly connected to said chip carrier without connecting through any of said plurality of second bonding leads, and wherein said first and second pins are adjacent to each other.