Patent ID: 8370606
Filing Date: 2013-02-05
Classification: G06F

Abstract:
1. A device comprising: a first data pointer register operable for storing a first data pointer; a second data pointer register operable for storing a second data pointer; a switch coupled to the first data pointer register and the second data pointer register, the switch operable for selecting either the first data pointer or the second data pointer as an active data pointer; a configuration register operable for providing a first signal indicating which one of the first data pointer or the second data pointer is the active data pointer; an instruction decoder operable for receiving a data pointer instruction and outputting, based on the data pointer instruction, a second signal indicating which one of the first data pointer or the second data pointer is the active data pointer; and a decoding logic circuit coupling the configuration register, the instruction decoder, and the switch, the decoding logic circuit being configured to use the first signal from the configuration register as a first input and the second signal from the instruction decoder as a second input, and to produce an output signal to the switch, wherein during execution of the data pointer instruction, when the first signal from the configuration register indicates that the first data pointer is the active data pointer, the switch selects the second data pointer as the active data pointer based on the output signal from the decoding logic circuit.