Patent ID: 8782656
Filing Date: 2014-07-15
Classification: G06F

Abstract:
1. An apparatus comprising: at least one processor; a memory coupled to the at least one processor; an application residing in the memory; an operator graph residing in the memory that represents the application using a plurality of operators and a plurality of data flows between the plurality of operators; an operator graph analysis mechanism that analyzes the operator graph at runtime when the application runs, detects at least one problem in the operator graph based on at least one data bottleneck in the operator graph, and performs at least one resource reallocation to improve performance of the application represented in the operator graph; and a reallocation policy residing in the memory and specified by a user that specifies a plurality of problems and corresponding potential reallocations to perform to address the plurality of problems, wherein the plurality of problems comprise compute bound and memory bound, wherein the at least one resource reallocation is selected from the potential reallocations in the reallocation policy.