Patent ID: 7282413
Filing Date: 2007-10-16
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming an element isolation area surrounding an element area in a semiconductor substrate; forming a first gate insulating film on the element area; forming a first gate electrode film on the first gate insulating film; removing selectively the first gate electrode film and the first gate insulating film on a nonvolatile memory cell region in the element area; forming a second gate insulating film on the first gate electrode film; removing the second gate insulating film, the first gate electrode film and the first gate insulating film, respectively, on a logic circuit region in the element area; forming a third gate insulating film on the semiconductor substrate in the logic circuit region; forming a second gate electrode film on the second gate insulating film and the third gate insulating film; removing selectively the second gate electrode film, the second gate insulating film and the first gate electrode film in the nonvolatile memory cell region, and removing selectively the second gate electrode film in the logic circuit region; and forming a source and a drain in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the first gate insulating film and the third gate insulating film, by introducing impurities into the semiconductor substrate using the second gate electrode film as a mask.