Patent ID: 7562329
Filing Date: 2009-07-14
Classification: G06F

Abstract:
1. A semiconductor integrated circuit which is a master-slice-type semiconductor integrated circuit, comprising: a bulk layer on which a plurality of bulk patterns to realize specific circuit functions are formed; and a plurality of wiring layers sequentially formed in layers on said bulk layer and including variable wiring layers of which wiring patterns is changeable by a user and fixed wiring layers of which wiring patterns is unchangeable by the user, wherein said bulk layer is filled with the plurality of bulk patterns which are fixed and selected; wherein said bulk patterns and their placement in said bulk layer is unchangeable by the user; wherein each of said bulk patterns controls the circuit function by the wiring pattern formed on each of said variable wiring layers; and wherein said variable wiring layers include a wiring pattern of the wiring for supplying power to the circuit and a wiring pattern of the wiring which connects to or does not connect to the power source to supply logic to the terminal which switches the mode inside the circuit, in accordance with the circuit formed in said bulk layer by said bulk patterns.