Patent ID: 6301553
Filing Date: 2001-10-09
Classification: G06F

Abstract:
An apparatus comprising:an execution unit for executing programs;a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,the program enables the apparatus to identify certain level sensitive storage circuit elements in a circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said potential skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal; andthe program further enables the apparatus to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals with potential skews ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformations for each of said certain level sensitive storage circuit elements employing a Boolean function corresponding to the gating combinatorial logic, and determining at least a first anda second co-factor value of a logical decomposition of the synchronization signal using the corresponding Boolean function.