Patent ID: 7139347
Filing Date: 2006-11-21
Classification: H03L,H04L

Abstract:
1. A parallel signal automatic phase adjusting circuit having a number of data signal channels inputted together with a clock signal and adjusting the clock signal so that each clock signal is synchronized with each of the data signals, the parallel signal automatic phase adjusting circuit comprising: adjusting circuits provided in correspondence to the respective data signal channels for effecting adjustment on the clock signal generated from the oscillating circuit so that the clock signal is synchronized with the corresponding data signal, wherein each of the adjusting circuits is arranged to include a phase comparator for comparing the clock signal and the data signal in phase and outputting a phase difference signal as a result of the comparing, and a trigonometric function calculating unit for performing a phase shift operation of the clock signal by the phase difference thereby effecting adjustment on the clock signal so that the clock signal is synchronized with the data signal, based on trigonometric function calculation using the phase difference signal outputted from the phase comparator as a parameter, wherein when δ represents a phase difference of the clock signal relative to the data signal and V the trigonometric function calculation includes determining an adjusted clock signal Vck by Vck=V