Patent ID: 8239600
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. A data processing system comprising: a plurality of central processing units; a plurality of interrupt controllers assigned to the central processing units in a one-to-one corresponding manner; and a circuit module which can be commonly used by the central processing units, wherein different interrupt request signals are supplied from the circuit module to the interrupt controllers, wherein each of the interrupt controllers notifies the corresponding central processing unit of an interrupt in response to the input interrupt request signal, wherein the circuit module selects an interrupt controller for supplying an interrupt request signal from the interrupt controllers, wherein the circuit module outputs an interrupt request signal toward a single interrupt controller which is preliminarily determined regardless of an interrupt controller corresponding to a central processing unit which issued a start request or regardless of a central processing unit which issued a start request, in accordance with a set value of a first register, wherein a second register designates a single interrupt controller for outputting an interrupt request signal regardless of a central processing unit which issued a start request, and wherein when a second value is set in the first register, an interrupt controller designated by the set value in the second register is set as an output destination of an interrupt request signal.