Patent ID: 6708308
Filing Date: 2004-03-16
Classification: H03M

Abstract:
A method for generating bit reliabilities by means of a simplified Soft Output Viterbi Algorithm (SOVA), the method on a processing unit for fault-tolerant communication comprising the steps of:determining, in a SOVA decoder, a sequence of numbers r communicated over a channel, having a channel impulse response h with coefficients h0, h1, . . . , hv, wherein v+1 is a length of the response; detecting by means of a Viterbi detector candidate symbols x=x1 . . . xk from the received sequence of numbers r, where k is a given length; and generating symbol reliability estimates for each symbol position in r and for each detected candidate symbol x using error filters including the sub-steps of: convolving an error sequence &egr; with hR, a time reversal of h; and processing the convolution (&egr;*hR) with a bank of error filters with taps for each error filter in the bank of error filters determined by error events e, the output of each error filter given by: (&egr;*hR)Â·Sk(e) where Sk(e) is a sequence with the length k representing a translate of e.