Patent ID: 6362053
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A process for producing non-volatile memories on a substrate of silicon having a matrix area comprising a memory cell area and a circuitry area comprising a control logic area, comprising the steps of:(a) growing a layer of sacrificial oxide on said substrate of silicon on said matrix area and on said circuitry area; (b) removing said layer of sacrificial oxide from said matrix area and leaving the sacrificial oxide on the circuitry area; (c) growing a layer of tunnel oxide on said matrix area and said circuitry area; (d) depositing a first layer of polysilicon on said matrix area and on said circuitry area; (e) forming a layer of interpoly dielectric, after said step of depositing said first layer of polysilicon, on said matrix area and said circuitry area; (f) removing said layer of interpoly dielectric from said circuitry area; (g) removing said first layer of polysilicon from said circuitry area; (h) removing said layer of sacrificial oxide and said layer of tunnel oxide from said circuitry area.