Patent ID: 6812075
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method of forming a semiconductor structure comprising the steps of:providing a structure including at least one patterned semiconducting body region, said at least one patterned semiconducting body region is present atop an insulating layer; depositing a planarizing material atop said structure including said at least one patterned semiconducting body region, said planarizing material having a lesser thickness atop said at least one pattemed semiconducting body than a remaining portion of said structure; forming a patterned photoresist atop said planarizing material, wherein during said forming of said pattered photoresist said lesser thickness of said planarizing material creates an overexposed portion of said patterned photoresist atop said at least one semiconducting body; and etching said at least one patterned semiconducting body region to form a first region, a second region and a third region, said first region having a first horizontal width and said second and third regions having a second horizontal width that is greater than said first horizontal width, each of said second and third regions having tapered portions abutting said first region with a horizontal width that varies in a substantially linear manner from said first horizontal width to said second horizontal width, wherein said tapered portions are defined by said overexposed portion of said patterned photoresist.