Patent ID: 6423996
Filing Date: 2002-07-23
Classification: H01L

Abstract:
An integrated circuit comprising:a plurality of lower insulating layers; a plurality of metallization levels, each of the metallization levels being supported by one of the lower insulating layers and forming interconnection tracks of the integrated circuit; a plurality of upper insulating layers, each of the upper insulating layers covering one of the metallization levels; and a metal-metal capacitor comprising: a first metal electrode; a second metal electrode; and a dielectric layer, wherein the first and second metal electrodes are placed one on each side of and in contact with the dielectric layer, the first and second metal electrodes and the dielectric layer lie between the lower insulating layer supporting one of the metallization levels and the upper insulating layer covering said one metallization level, said one metallization level comprises a metal layer including the first metal electrode, and the second metal electrode is thinner than the first metal electrode.