Patent ID: 6442722
Filing Date: 2002-08-27
Classification: G01R

Abstract:
A method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, said circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said method comprising:configuring said memory elements in scan mode; concurrently clocking a test stimulus into each scan chain of each said clock domain including, for each clock domain having a domain test clock signal which is synchronous with respect to said main test clock signal, clocking said test stimulus at a shift clock rate derived from said main test clock signal and, for each clock domain having a domain test clock signal which is asynchronous with respect to said main test clock signal, clocking all but a predetermined number of bits of said test stimulus at a first domain shift clock rate derived from said main test clock signal followed by clocking said predetermined number of bits of said test stimulus at a second domain shift clock rate corresponding to said domain test clock rate; configuring said memory elements of each scan chain in normal mode in which the memory elements of each scan chain are interconnected by said core logic in the normal operational mode; clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle thereof; configuring said memory elements in scan mode; and clocking a test response pattern out of each of the scan chains at its respective domain shift clock rate during a respective scan-out interval, all respective scan-out intervals overlapping in time for a plurality of clock cycles at the highest of the respective clock rates.