Patent ID: 7051310
Filing Date: 2006-05-23
Classification: G06F

Abstract:
1. For an integrated circuit (IC) layout identifying positions within an IC of a plurality of devices (sinks) to be clocked by a clock signal, a clock tree synthesis method for processing the layout to select positions within the IC of buffers forming levels of a multiple-level hierarchy of interconnected buffers for transmitting the clock signal to the sinks, wherein buffers at a lowest level of the hierarchy transmit the clock signal to the sinks, wherein each buffer at any other level of the hierarchy transmits the clock signal to buffers at a next lower level of the hierarchy, wherein the clock tree comprises a plurality of lower intermediate levels of buffers above the lowest level, a plurality of higher intermediate levels of buffers above the lower intermediate levels, and a top level buffer above the higher intermediate levels, the method comprising the steps of: a. identifying clusters of the sinks; b. selecting a position for each buffer at the lowest level of the hierarchy that is proximate to a separate one of the identified clusters of the sinks; c. selecting a position for the top level buffer; d. selecting a position for each buffer of each of the lower intermediate levels, in ascending order according to where the lower intermediate levels appear in the hierarchy starting with a lowest of the lower intermediate levels and ending with a highest of the lower intermediate levels; and e. selecting a position for each buffer of each of the higher intermediate levels, in descending order according to where the higher intermediate levels appear in the hierarchy starting with a highest of the higher intermediate levels and ending with a lowest of the higher intermediate levels; whereby the buffer positions for intermediate levels of the clock tree are selected responsive to a combination of bottom up and top down approaches.