Patent ID: 7499325
Filing Date: 2009-03-03
Classification: G11C

Abstract:
1. A flash memory device comprising: a well in a substrate; a plurality of memory cells coupled to the well; a select transistor coupled between the memory cells and a bit line, the select transistor including a gate; a first circuit to raise a well voltage of the well during an erase operation from a first well voltage level to a second well voltage level, and to hold the well at the second well voltage level for a first time interval during the erase operation; and a second circuit to raise a voltage at the gate during the erase operation from a first gate voltage level to a second gate voltage level lower than the second well voltage level, to hold the gate at the second gate voltage level for a second time interval during the erase operation, and to hold the gate at the first gate voltage level when the first circuit raises the well voltage from the first well voltage level to an intermediate well voltage level lower than the second well voltage level and higher than the first well voltage level.