Patent ID: 6336198
Filing Date: 2002-01-01
Classification: G01R

Abstract:
A chip testing system coupled to a chip for testing said chip's quality, said chip testing system applying an input test data to said chip in an input mode and reading an output test data in an output mode, said input and output test data having a predetermined test cycle, wherein a conflict occurs during a turn-around cycle between said input and output modes, said chip testing system comprising a testing circuit coupled to said chip to receive therefrom an output enable signal indicative of outputting said output test data and a preceding signal output prior to said output enable signal, said testing circuit generating a blanking signal responsive to input of said output enable signal and said preceding signal and supplying said blanking signal to said chip to control reading of said input test data, said blanking signal being output to delay said output mode after said input mode and delay said input mode after said output mode, thereby eliminating any effects from said conflict during said turn-around cycle.