Patent ID: 7152215
Filing Date: 2006-12-19
Classification: G06F,H01L,Y02P

Abstract:
1. A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the use of the model and dimensional characteristics, and the simulation or analysis of the electrical impact analysis being embedded as part of the generation of the strategy for placing dummy fill features.