Patent ID: 9087740
Filing Date: 2015-07-21
Classification: G03F,H01L

Abstract:
1. A method of stitching multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process, the method comprising: exposing a first lithographic field image on the semiconductor layer, the first lithographic field image having a first petal located substantially adjacent a peripheral edge of the first lithographic field image; exposing a second lithographic field image on the semiconductor layer, the second lithographic field image having a second petal located substantially adjacent a peripheral edge of the second lithographic field image; exposing a third lithographic field image on the semiconductor layer, the third lithographic field image having a third petal located substantially adjacent a peripheral edge of the third lithographic field image; and exposing a fourth lithographic field image on the semiconductor layer, the fourth lithographic field image having a fourth petal located substantially adjacent a peripheral edge of the fourth lithographic field image, the peripheral edge of the first, the second, the third, and the fourth lithographic field substantially abutting in a non-overlapping manner based on a predetermined design distance between the first, the second, the third, and the fourth petal, wherein the first, the second, the third, and the fourth petal are captured within a field-of-view (FOV) of a metrology tool for determining a stitching error between the first, the second, the third, and the fourth lithographic field image, wherein the first, the second, the third, and the fourth petal provide a position error indication corresponding to the substantially abutting of the peripheral edge of the first, the second, the third, and the fourth lithographic field, wherein the position error indication comprises measuring a placement error between the first and the second petal based on respective coordinates corresponding to the first and the second petal imaged on the semiconductor layer and a first predetermined design distance between the first and the second petal; and measuring a placement error between the third and the fourth petal based on respective coordinates corresponding to the third and the fourth petal imaged on the semiconductor layer and the first predetermined design distance between the third and the fourth petal.