Patent ID: 6768189
Filing Date: 2004-07-27
Classification: H01L

Abstract:
An integrated circuit packaging assembly comprising:a substrate including a top surface and a bottom surface; an integrated circuit mounted to the top surface of the substrate; a plurality of top-side bond pads deposited on the top surface of the substrate around a perimeter of the integrated circuit, said top-side bond pads being in direct electrical contact with the integrated circuit; a plurality of back-side bond pads deposited on the bottom surface of the substrate; a plurality of signal vias extending through the substrate and being in electrical contact with a top-side pad and a bottom-side pad; a top protective layer formed over the top-side pads and the integrated circuit; a bottom protective layer formed over the bottom surface of the substrate; and a plurality of signal vias extending through the bottom protective layer and being in electrical contact with the back-side pads.