Patent ID: 6901496
Filing Date: 2005-05-31
Classification: H04L

Abstract:
1. A method for enabling line rate throughput of data communicated in a pipeline of processors having single ported memories, comprising: providing three single ported memories in each processor of a pipeline of processors; receiving a plurality of variable-size packets of data associated with a data stream, the data stream associated with a line rate; distributing the variable-size packets of data to the three single ported memories of a first processor of the pipeline of processors, wherein one of the plurality of variable-size packets of data distributed to the three single ported memories of the first processor is a maximum size packet; and sequentially reading the variable-size packets of data, the reading performed by a second processor of the pipeline of processors, wherein the second processor maintains the line rate after reading the one-of the plurality of variable size packets of data having the maximum size.