Patent ID: 6122703
Filing Date: 2000-09-19
Classification: G06F

Abstract:
A data processing apparatus for a data transmission system, said data processing apparatus comprising:an input buffer that stores data samples for a symbol in a sequential manner;a first address transformer, said first address transformer operates to transform the sequential manner of the data samples into a non-sequential manner such that sequential addresses of the data samples for the symbol stored in said input buffer are transformed into non-sequential addresses;a memory system having n-banks of memory, said memory system stores the data samples from said input buffer to said n-bank memory system in accordance with the non-sequential addresses produced by said first address transformer;a processor, said processor operates to compute output samples for the symbol, with said processor producing n-output samples using one of the data samples in each of the n-banks of memory of said memory system;a second address transformer, said second address transformer operates to transform the non-sequential manner of the output samples into a sequential manner; andan output buffer, said output buffer stores the output data samples in the sequential manner,wherein said data processing apparatus can perform either a Fast Fourier Transform (FFT) or an Inverse Fast Fourier Transform (IFFT) on the symbol stored in said input buffer, andwherein said processor is pipelined and thus enables concurrent FFT and IFFT processing on different symbols.