Patent ID: 6308055
Filing Date: 2001-10-23
Classification: H03J,H03L

Abstract:
A frequency synthesizer having a phase locked loop, comprising:a controllable oscillator having an output frequency dependent upon a capacitance amount within an LC tank resonant structure;a plurality of parallel-connected continuously variable capacitor circuits that together provide at least part of the capacitance amount, each capacitor circuit having a control signal configured to determine at least in part an amount of capacitance that is contributed by that capacitor circuit to the capacitance amount;a first clock node coupled to an output of the controllable oscillator;a second clock node coupled to a reference clock; anda plurality of different control signals coupled to inputs of the controllable oscillator to provide said control signals to the plurality of variable capacitor circuits, the control signals being generated from, at least in part, a phase difference between a first clock signal on the first clock node that is related to the output frequency and a second clock signal on the second clock node that is related to the reference frequency, wherein the control signals are continuously variable analog signals.