Patent ID: 8244999
Filing Date: 2012-08-14
Classification: G06F

Abstract:
1. A method comprising: loading a gate bitmap into memory, wherein the gate bitmap comprises a plurality of bits and each bit corresponds to a storage area of a plurality of storage areas within a primary networked storage node; logging, on the primary networked storage node, an intent to write data to a storage area of the primary networked storage node by setting a bit in the gate bitmap corresponding to the storage area; writing the data to the primary networked storage node after logging the intent to write data; relaying a request to a secondary networked storage node to mirror the data after logging the intent to write data; and after a delay period completes, clearing the bit set in the gate bitmap to protect an underlying write-back cache, wherein the gate bitmap has an associated bit vector, and the bit vector has one or more bits that indicate a size of the storage areas corresponding to each bit of the gate bitmap.