Patent ID: 6496431
Filing Date: 2002-12-17
Classification: G11C

Abstract:
A semiconductor integrated circuit device, comprising:a plurality of memory circuits each including: a redundancy circuit to replace a memory cell having a defect with a spare memory cell, a detecting circuit which determines whether a first identification code to be inputted matches with a second identification code, a storing circuit which stores the second identification code, and a latch; a programmable circuit capable of programming the first identification code and repair address information corresponding to the first identification code and serially outputting the information; and a control circuit which sequentially reads the repair address information from the programmable circuit, converts the read repair address information into parallel data, and transfers the parallel data to the plurality of memory circuits, wherein each of the plurality of memory circuits holds the repair address information by the latch when the detecting circuit determines that the first identification code and the second identification code match with each other, and wherein the repair address information held in the latch makes the redundancy circuit valid.