Patent ID: 7129026
Filing Date: 2006-10-31
Classification: G03F,H01L

Abstract:
1. A method for simultaneously forming semiconductor layer and source/drain regions by using a single reticle for multi-etching steps in formation of thin film transistors array, said method comprising: providing a substrate; selectively forming a gate electrode layer on said substrate; subsequently forming a dielectric layer, a semiconductor layer, and a conductive layer on said gate electrode layer and said substrate; forming a photoresist layer on said conductive layer; exposing said photoresist layer by using said reticle; hard baking said photoresist layer; developing said photoresist layer after said hard baking such that a patterned photoresist layer covered by said pattern is formed, a photoresist residue around said patterned photoresist layer is formed, and the other region of said photoresist layer is removed; first etching said conductive layer by using said patterned photoresist layer and said photoresist residue as an etching mask; first etching said semiconductor layer by using said patterned photoresist layer and said photoresist residue as an etching mask and removing said photoresist residue to form an island semiconductor layer; second etching said conductive layer to form a source region and a drain region by using said patterned photoresist layer as an etching mask; second etching said semiconductor layer to form a channel region by using said patterned photoresist layer as an etching mask; and removing said patterned photoresist layer.