Patent ID: 7456689
Filing Date: 2008-11-25
Classification: H03F,H03G

Abstract:
1. An amplifier circuit comprising: a transistor group including a first transistor, a plurality of second transistors and a plurality of third transistors, wherein sources of the first transistor, the plurality of second transistors and the plurality of third transistors are commonly connected, drains of the first transistor and the plurality of second transistors are commonly connected, and drains of the plurality of third transistors are commonly connected; a first voltage generating section connected to the gate of the first transistor, which generates a desired first voltage and supplies the first voltage to the gate of the first transistor; a plurality of first switching elements respectively connected via respective output terminals thereof to the gates of the plurality of second transistors; a plurality of second switching elements respectively connected via respective output terminals thereof to the gates of the plurality of third transistors; a second voltage generating section connected to respective first input terminals of the plurality of first switching elements and the plurality of second switching elements, which generates a second voltage that is either the same as or different from the first voltage; a third voltage generating section connected to respective second input terminals of the plurality of first switching elements and the plurality of second switching elements, which generates a third voltage having a voltage difference with respect to the source voltage of the commonly-connected first to third transistors that is smaller than that of the second voltage; and a control section that respectively selectively supplies either the second voltage or the third voltage to the gates of the plurality of second transistors and the gates of the plurality of third transistors by respectively switching the connection states of the plurality of first switching elements and the plurality of second switching elements to the sides of the first input terminals or to the sides of the second input terminals.