Patent ID: 7291881
Filing Date: 2007-11-06
Classification: H01L

Abstract:
1. A bit line structure having: a surface bit line, which, for connection of a multiplicity of first doping regions, is formed above a substrate surface; and a buried bit line which, for connection of a multiplicity of second doping regions, is formed inside a substrate, in such a manner that a trench in the substrate; a trench insulation layer at a trench surface of the trench; the buried bit line in a lower region of the trench on the trench insulation layer; a covering insulation layer on the buried bit line in a first, upper partial region of the trench; a multiplicity of covering connecting layers on the buried bit line in a second upper partial region of the trench; and a multiplicity of self-aligning terminal layers in the region of the substrate surface are formed, the multiplicity of covering connecting layers being electrically connected via the terminal layers to the multiplicity of second doping regions.