Patent ID: 7745295
Filing Date: 2010-06-29
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of forming a memory cell, comprising: forming a sacrificial construction over a semiconductor substrate; using the sacrificial construction as a mask while implanting dopant into the semiconductor substrate to form implant regions; forming first electrically insulative material laterally outward of the sacrificial construction; removing the sacrificial construction to leave an opening extending through the first electrically insulative material, the opening having a periphery comprising sidewalls extending upwardly from a bottom; forming gate dielectric material along the bottom of the opening periphery; annealing the dopant within the implant regions; after annealing the dopant, distributing nanosize charge trapping units within the opening and over the gate dielectric material; forming second electrically insulative material within the opening, the second electrically insulative material being over and between the nanosize charge trapping units; the second electrically insulative material only partially filling the opening to line the sidewalls and bottom of the periphery of the opening; the lined opening having a trough extending therein; and forming control gate material within said trough.