Patent ID: 7300839
Filing Date: 2007-11-27
Classification: H01L,Y10S

Abstract:
1. A method of manufacturing a memory cell comprising an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact, said method comprising the steps of: forming said charge storage structure so as to be conductively coupled to said bit line via said transistor structure and said bit line contact; forming said transistor structure so as to be conductively coupled to said word line; forming said bit line contact by forming a conductively doped polysilicon plug within a contact hole bounded by insulating side walls; and forming said doped polysilicon plug so as to define an upwardly curved upper plug surface profile in contact with said bit line, wherein said upwardly curved upper plug surface profile extends from an uppermost extent of one insulating side wall to an uppermost extent of an opposing insulating side wall such that said upwardly curved upper plug surface profile is at least partially above the opposing insulating side walls.