Patent ID: 6519672
Filing Date: 2003-02-11
Classification: G06F

Abstract:
A shared memory unit for providing shared memory to a plurality of processor systems, the shared memory unit comprising:a shared memory comprising a plurality of memory banks; a plurality of input/output ports, each input/output port being connectable to a processor system by a dedicated data link; means coupled to the input/output ports for receiving a shared memory access request from a requesting processor; means coupled to the receiving means for determining the memory bank corresponding to the memory access request; connecting means coupled to the receiving means, the determining means, and the memory banks, for providing a data path between the input/output port and the memory bank associated with the memory access request; a memory controller coupled to the connecting paeans and the receiving means, the memory controller performing memory accesses to the shared memory bank through the connecting means in accordance with the memory access request; and means coupled to the memory controller and the input/output ports for generating a shared memory access response for transmission back to the requesting processor system.