Patent ID: 6197682
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A manufacturing method of a semiconductor device, comprising the steps of:forming selectively a first opening in a first insulating layer covering a semiconductor substrate;burying said first opening with a first conductive layer;forming a first wiring layer on said first insulating layer, which stretches contacting the said first conductive layer;covering surfaces of said first wiring layer and said first insulating layer with a second insulating layer;selectively removing said second insulating layer and said first wiring layer thereby exposing a surface of said first conductive layer and forming a second-openings which divides said first wiring layer into first and second portions;forming a conductive layer on an entire surface of the resultant structure, and then etching-back said conductive layer to form a second conductive layer along the said second insulating layer exposed by said second opening, said second conductive layer contacting said first and second portions of said first wiring layer exposed by said second opening;forming a third insulating layer covering a surface of said second conductive layer; andforming a second wiring layer on said second insulating layer, said second wiring layer contacting said first conductive layer and being insulated from said second conductive layer by said third insulating layer.