Patent ID: 7718988
Filing Date: 2010-05-18
Classification: G11C,H01L

Abstract:
1. A phase change memory device including a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node comprises: a lower electrode connected to the substrate; a first phase change layer formed on the lower electrode and having a first minimum resistance and a first maximum resistance based on the application of a first write voltage; a first barrier layer overlying the first phase change layer and constituting an insulating layer; a second phase change layer overlying the first barrier layer and having a second minimum resistance and a second maximum resistance based on the application of a second write voltage, which is different from the first write voltage; and an upper electrode formed on the second phase change layer, wherein the first barrier layer has a lower resistance than the first and second phase change layers and is thin enough to permit the tunneling of electrons.