Patent ID: 6174563
Filing Date: 2001-01-16
Classification: C23C,H01L,Y10T

Abstract:
In a method for forming an integrated circuit which includes a metal film layer for wiring, wherein an insulating film is deposited on a substrate, and a via hole or a groove for wiring is formed in the insulating film and filled with metal, the improvement wherein the metal filling is formed by a two step chemical vapor deposition comprising a first discrete step wherein a first metal film is formed on surfaces defining said via hole or groove for wiring by chemical vapor deposition of a first raw material containing said metal at a first deposition temperature, and a second discrete step wherein a second metal film having a thickness greater than a thickness of said first metal film is formed directly on said first metal film to completely fill said via hole or groove for wiring by chemical vapor deposition of a second raw material containing the same said metal at a second deposition temperature higher than said first deposition temperature wherein said first raw material is different from said second raw material.