Patent ID: 8791846
Filing Date: 2014-07-29
Classification: H03M

Abstract:
1. An apparatus that calibrates an offset voltage in a continuous time delta-sigma modulation apparatus comprising a primary integrator and a secondary integrator, the apparatus comprising: a first logic element that generates a first signal by performing a logic operation of first and second pulse signals representing outputs of the continuous time delta-sigma modulation apparatus and an operation frequency of the continuous time delta-sigma modulation apparatus; a second logic element that generates a switch control signal that resets an integral capacitor of the primary integrator and an integral capacitor of the secondary integrator by performing a logic operation of the first signal and an enable signal representing the start of an offset calibration mode; a first digital to analog converter (DAC) that applies a voltage corresponding to a first output bit to a body of a first transistor of the primary integrator; a second DAC that applies a voltage corresponding to a second output bit to a body of a second transistor of the primary integrator; and a counter that determines up-counting or down-counting according to the first and second pulse signals and that generates the first and second output bits in response to the first signal and that outputs the first and second output bits to the first and second DACs, respectively.