Patent ID: 8289427
Filing Date: 2012-10-16
Classification: G01S,H01L

Abstract:
1. A CMOS imaging device including a plurality of pixels being arrayed, each of the pixels comprising: a semiconductor region of a first conductivity type; a light receiving surface-buried region of a second conductivity type buried in a part of an upper portion of the semiconductor region, to which a light reflected by a target sample is entered; a first charge-accumulation region of the second conductivity type buried in a part of the upper portion of the semiconductor region, a depth of a potential well of the first charge-accumulation region is deeper than the light receiving surface-buried region, and to which signal charges generated by the light are transferred from the light receiving surface-buried region; a first charge read-out region configured to receive the signal charges from the first charge-accumulation region; a first potential control means configured to control a potential of a first channel, the first channel being formed in a part of the upper portion of the semiconductor region between the light receiving surface-buried region and the first charge-accumulation region configured to transfer the signal charges from the light receiving surface-buried region to the first charge-accumulation region; a second potential control means configured to control a potential of a second channel, the second channel being formed in a part of the upper portion of the semiconductor region between the first charge-accumulation region and the first charge read-out region configured to transfer the signal charges from the first charge-accumulation region to the first charge read-out region; a reset transistor having a source electrode connected to the first charge read-out region, configured to extract accumulated charges in the first charge read-out region, before the signal charges are transferred to the first charge read-out region from the first charge-accumulation region; a signal read-out transistor having a gate electrode connected to the first charge read-out region configured to read out a signal level corresponding to an amount of the signal charges accumulated in the first charge read-out region; a first exhausting-drain region configured to extract the charges from the light receiving surface-buried region; and a third potential control means configured to control a potential of a third channel, the third channel being formed in a part of the upper portion of the semiconductor region between the light receiving surface-buried region and the first exhausting-drain region configured to transfer the signal charges from the light receiving surface-buried region to the first exhausting-drain region, wherein the signal charges dependent on a delay time of the reflected light are repeatedly transferred from the light receiving surface-buried region to the first charge-accumulation region so as to be accumulated as a first signal charge in the first charge-accumulation region in a first repetition period, all of the signal charges generated by the reflected light are repeatedly transferred from the light receiving surface-buried region so as to be accumulated as a second signal charge in the first charge-accumulation region in a second repetition period, and a ratio between total quantities of the accumulated first and second signal charges is calculated so as to measure a range to the target sample based upon the signal levels read out by the signal read-out transistor.