Patent ID: 6534393
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity comprising the steps of:providing a substrate; forming field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate; forming a gate oxide on said device areas; depositing a polysilicon layer on said substrate; depositing a first insulating layer on said polysilicon layer; patterning said first insulating layer and said polysilicon layer and leaving portions of said polysilicon layer over said device areas to form said gate electrodes and leaving portions of said polysilicon layer over said field oxide isolation regions for local interconnections; forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation; depositing a conformal second insulating layer over said gate electrodes and elsewhere on said substrate, and anisotropically etching back said second insulating layer thereby forming sidewall spacers on sidewalls of said gate electrodes; forming source/drain contact areas by ion implantation; depositing a third insulating layer on said substrate; polishing back said third insulating layer to said first insulating layer to form a planar surface; selectively removing portions of said first insulating layer over said portions of said polysilicon layer while leaving essentially unetched said second and said third insulating layers and forming recesses in said third insulating layer over said portions of said polysilicon layer; using a photoresist mask and anisotropic etching to etch contact openings in said third insulating layer to said substrate; depositing a unitary blanket metal layer and filling said contact openings and said recesses in said third insulating layer over said portions of said polysilicon layer; patterning said unitary metal layer leaving portions over said contact openings and over and contacting said portions of said polysilicon layer to complete said local metal interconnections while leaving said metal in said recesses to improve the electrical conductivity of said portions of said polysilicon layer.