Patent ID: 6297553
Filing Date: 2001-10-02
Classification: H01L,H05K

Abstract:
A semiconductor device comprising:a semiconductor chip having an electrode terminal carrying surface on which electrode terminals and conductor lands electrically connected to the electrode terminals are formed;an interposing substrate of an insulating material having a front surface and a back surface and disposed with the front surface facing the electrode terminal carrying surface of the semiconductor chip, in which a conductor wiring pattern, including conductor pads, is formed on the front surface, a conductor wiring pattern, including conductor lands having a larger surface area than said conductor pads, is formed on the back surface, external connection terminals are formed on the conductor lands on the back surface, and conductor vias formed by electrolytic plating to fill viaholes with an alloy having a melting point of no more than 300.degree. Celsius, extending through the interposing substrate electrically connecting the conductor wiring pattern on the front surface and the conductor wiring pattern on the back surface, at least one of the conductor wiring pattern on the front surface and the conductor wiring pattern on the back surface being adhered to the interposing substrate by a thermoplastic adhesive agent layer; andbumps electrically connecting the conductor lands of the semiconductor chip to the conductor pads of the interposing substrate.