Patent ID: 7313018
Filing Date: 2007-12-25
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: an array of memory cells comprising drain, source and gate nodes; at least one multiplexer configured to couple signals with the nodes of the memory cells in the array; at least one power source; and a plurality of power control circuits coupled with the source and drain nodes of the memory cells within the array and the at least one power source, the plurality of power control circuits configured to supply voltage signals generated from the at least one power source to the memory cells within the array via the multiplexer, wherein, the plurality of power control circuits are configured to provide a plurality of pre-charging paths to the nodes of memory cells within the array when a target memory cell is to be programmed, and the plurality of power control circuits are comprised of a plurality of transistors configured in a source follower configuration, wherein source nodes of the plurality of transistors comprising the plurality of power control circuits are coupled with the associated source and drain nodes of the memory cells.