Patent ID: 7421633
Filing Date: 2008-09-02
Classification: G01R,G06F

Abstract:
1. An integrated circuit, comprising: A. test access port circuitry having a TDI input lead, a TMS input lead, a TCK input lead, and a TDO output lead; and C. controller circuitry having a TMS/TDI input lead, a clock input lead, and a TDO output lead, the controller circuitry being connected to the test access port circuitry by a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead of the test access port circuitry and to the TDO output lead of the controller circuitry, the controller circuitry including: