Patent ID: 6125074
Filing Date: 2000-09-26
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of memory cell blocks, each of the memory cell blocks including an array of columns and words of memory cells, said device comprising:means for generating a memory cell block selection signal and one of a column and a word selection signal;a driver circuit, connected to said selection signal generating means, for generating a drive signal for driving the memory cells, said driver circuit comprising a transfer gate, controlled by said memory cell block selection signal, for passing said one of a column and a word selection signal to generate said drive signal;an inverter, connected between said transfer gate and the memory cells, for inverting said one of a column and a word selection signal passed through said transfer gate to generate said drive signal; anda switching element, connected between a power supply terminal and an input of said inverter and being controlled by said memory cell block selection signal.