Patent ID: 6172898
Filing Date: 2001-01-09
Classification: H01L,Y10S

Abstract:
A semiconductor memory device comprising:a semiconductor substrate;a plurality of trench capacitors arranged on said semiconductor substrate in the form of a matrix at a substantially constant pitch in row directions and said trench capacitors being sequentially shifted between adjacent rows by a predetermined pitch;an element isolating insulator film formed so as to surround active regions, each of which is adjacent to two trench capacitors of said trench capacitors adjacent to each other in said row directions, said element isolating insulator film including a partial region of said two trench capacitors;a plurality of transistors, each of which is formed in each of said active regions and each of which has source diffusion layer and drain diffusion layer, one of said source diffusion layer and drain diffusion layer being connected to a capacitor node layer of a corresponding one of said trench capacitors via a connecting conductor formed on said semiconductor substrate, and the other of said source diffusion layer and drain diffusion layer serving as one of bit line contact layers, which is shared by two transistors of said transistors adjacent to each other in said row directions;a plurality of word lines, every three of which are arranged between adjacent two of said bit line contact layers arranged in said row directions so as to commonly connect gate electrodes of said transistors arranged in directions intersecting said row directions to each other; anda plurality of bit lines for commonly connecting said bit line contact layers in directions intersecting said word lines.