Patent ID: 9070483
Filing Date: 2015-06-30
Classification: G06F,G11C

Abstract:
1. A data storage system comprising: a memory circuit comprising memory cells; and a control circuit to receive data bits provided for storage in the memory cells, wherein the control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults, wherein the control circuit encodes the first set of redundant bits to generate a second set of redundant bits, and wherein the control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.