Patent ID: 7501904
Filing Date: 2009-03-10
Classification: H03K,H03L

Abstract:
1. A circuit comprising: a chain of delay cells comprising a first delay cell having an input port and a last delay cell comprising an output port connected to the input port of the first delay cell, each delay cell comprising a pull-up pMOSFET to provide a pull-up current when ON and a pull-down nMOSFET to provide a pull-down current when ON; and a feedback loop to bias the pull-up pMOSFETs so that for each delay cell the pull-up current matches the pull-down current, the feedback loop comprising a differential amplifier comprising an output port to bias the pull-up pMOSFETs of the delay cells, and further comprising a pull-up pMOSFET to provide a pull-up current when ON, and a pull-down nMOSFET to provide a pull-down current when ON; wherein the pull-up pMOSFET in the feedback loop is matched to each of the pull-up pMOSFETs in the delay cells, and the pull-down nMOSFET in the feedback loop is matched to each of the pull-down nMOSFETs in the delay cells.