Patent ID: 8561079
Filing Date: 2013-10-15
Classification: G06F

Abstract:
1. An information processing device connected to a memory capable of realizing a simultaneous multi-threading system, the information processing device comprising: an arithmetic unit configured to perform an operation; an instruction input control unit configured to control inputting an instruction from a plurality of threads to the arithmetic unit from the memory; a plurality of commit stack entry units respectively provided for the plurality of threads to hold information obtained by decoding the instruction, the information indicating whether instruction processing of the decoded instruction is being performed; an instruction completion order control unit configured to update the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit configured to detect the information registered in the commit stack entry units and to control the instruction input control unit based on the result of the detection, wherein the instruction input control unit forces to switch inputting an instruction from a first thread of the plurality of threads corresponding to a first commit stack entry unit of the plurality of commit stack entry units to inputting an instruction from a second thread of the plurality of threads corresponding to a second commit stack entry unit of the plurality of commit stack entry units when a period indicating only the second commit stack entry is empty and does not hold information exceeds a designated period.