Patent ID: 7624219
Filing Date: 2009-11-24
Classification: H04L

Abstract:
1. A bus node circuit comprising: a coding circuit that receives a plurality of substantially binary input signals and outputs a first output signal and a plurality of other output signals; and a bus interface circuit having a first data input terminal and a plurality of parameter input terminals, said first data input terminal being connected to said coding circuit to receive said first output signal, and each of said plurality of parameter input terminals being connected to said coding circuit to receive a respective one of said plurality of other output signals, wherein said plurality of substantially binary input signals comprises a first predetermined subset comprising at least two substantially binary input signals, said first output signal having a first binary state if each substantially binary input signal of said first predetermined subset exhibits a respectively predetermined binary state, each of said plurality of other output signals has a binary state indicative of a binary state of a respective one of said substantially binary input signals, said bus interface circuit outputs a plurality of bus signals compliant with European standard EN 50295 or IEC Standard 62026-2, said plurality of bus signals including a data code representative of said first output signal and a parameter code representative of said plurality of other output signals.