Patent ID: 7409504
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. In a data processing system having a memory, a plurality of processors and associated processor caches coupled together via a system bus, a method of maintaining cache coherency comprising: when a first processor having ownership of a cache line snoops a request from a second processor for access to data within said cache line, and said request is snooped prior to a receipt and processing of said data at said first processor's cache, tagging said first processor cache with a first intermediate coherency state indicating that the first processor is to forward said data to said second processor once said data is received and processed at said first processor's cache; and providing a response to said second processor that informs said second processor that said cache line data will be forwarded to said second processor's cache at a later time, wherein said response allocates downstream ownership of the cache line to said second processor, and triggers the second processor to assign a second intermediate coherency state to the cache line within its cache, said second intermediate coherency state indicating that the data is going to be forwarded at a later time from the first processor.