Patent ID: 7084712
Filing Date: 2006-08-01
Classification: H03L

Abstract:
1. A clock generation system for generating at least a first frequency clack, a second frequency clock having a predetermined first frequency ratio relative to said first frequency clock, and a third frequency clock having a predetermined second frequency ratio relative to said first frequency clock, said clock generation system comprising: a first PLL circuit that includes a frequency division factor switching type frequency division circuit having a first phase comparator for comparing the phases of a first reference input clock and a first comparison input clock to generate a first phase comparison output in accord with the comparison, a first low-pass filter for passing said first phase comparison output, a first controllable oscillator receiving the filtered output from said first low-pass filter as a control input far controlling said first controllable oscillator adapted to generate a first oscillation frequency signal having a predetermined frequency ratio relative to said second frequency clock, a first reference input frequency division circuit for frequency-dividing said first frequency clock that is inputted as a reference clock to thereby obtain said first reference input clock, and a first comparison input frequency division circuit for frequency-dividing the first oscillation frequency signal of said first controllable oscillator to obtain said first comparison input clock, wherein one of said first comparison input frequency division circuit and first reference input frequency division circuit is adapted to frequency-divide said first oscillation frequency signal or said first frequency clock, respectively, by a different frequency division factor according to a first frequency division factor control signal; a first frequency division factor control circuit receiving a clack based on said first oscillation frequency signal and one of said first comparison input clock and first reference input clock, generating said first frequency division factor control signal such that said first oscillation frequency signal has a fixed frequency ratio relative to said second frequency clock, and switching the frequency division factor of said first comparison input frequency division circuit or of said first reference input frequency division circuit; a second PLL circuit that includes a frequency division factor switching type frequency division circuit having a second phase comparator for comparing the phases of a second reference input clock and a second comparison input clock to generate a second phase comparison output in accord with the comparison, a second low-pass filter for passing said second phase comparison output, a second controllable oscillator receiving the filtered output from said second low-pass filter as a control input for controlling said second controllable oscillator adapted to generate a second oscillation frequency signal having a predetermined frequency ratio relative to said third frequency clock, a second reference input frequency division circuit for frequency-dividing said first frequency clock that is inputted as a reference clock to thereby obtain said second reference input clock, and a second comparison input frequency division circuit for frequency-dividing the second oscillation frequency signal of said second controllable oscillator to obtain said second comparison input clock, wherein one of said second comparison input frequency division circuit and second reference input frequency division circuit is adapted to frequency-divide said second oscillation frequency signal or said first frequency clock, respectively, by a different frequency division factor according to a second frequency division factor control signal; and a second frequency division factor control circuit receiving a clock based on said second oscillation frequency signal and one of said second comparison input clock and said second reference input clock, generating said second frequency division factor control signal such that said second oscillation frequency signal has a fixed frequency ratio relative to said third frequency clock, and switching the frequency division factor of said second comparison input frequency division circuit or of said second reference input frequency division circuit, wherein: said first frequency division factor control circuit has a first flip-flop circuit receiving as a clock input a clock based on said first oscillation frequency signal and receiving as a data input one of said first comparison input clock and first reference input clock, a first counter for repetitively counting the output of said first flip-flop circuit from the initial to a preset value, a first decoder for generating a first decode output obtained by decoding the count of said first counter, and a second flip-flop circuit receiving as a data input said first decode output and receiving as a clock input the output of said first flip-flop circuit to output said first frequency division factor control signal; and said second frequency division factor control circuit has a third flip-flop circuit receiving as a clock input a clock based on said second oscillation frequency signal and receiving as a data input one of said second comparison input clack and second reference input clock, a second counter for repetitively counting the output of said third flip-flop circuit from the initial thereof to a preset value, a second decoder for generating a second decode output obtained by decoding the count of said second counter, and a forth flip-flop circuit receiving as a data input said second decode output and receiving as a clock input the outwit of said third flip-flop circuit to output said second frequency division factor control signal.