Patent ID: 6253301
Filing Date: 2001-06-26
Classification: G06F

Abstract:
In a multiprocessor system comprising a main memory and a plurality of processors that contend for access to the main memory via a common bus, each of said processors having an associated data caching system a data caching system comprising:a virtually-addressed data store for caching data from the main memory for access by the associated processor;a virtually-addressed primary tag array for holding physical tags associated with data cached in the data store;an address translator that maps virtual page addresses to physical page addresses;a first comparator to compare a physical page address, translated from a virtual address by the address translator, with a physical tag produced by the primary tag array responsive to the virtual address, a match indicating a cache hit;a duplicate tag array, comprising a plurality of secondary tag arrays, for holding copies of the tags held in the primary tag array, each secondary tag array being referenced by a common physical address portion concatenated with a unique value, wherein the secondary tag arrays are simultaneously referenced; anda plurality of second comparators, each second comparator associated with respective secondary tag array, each second comparator comparing the translated physical page address with a physical tag produced by its associated secondary tag array responsive to the concatenated physical address portion and unique value, a match indicating a hit in the data store at a location referenced by the concatenated physical address portion and unique value, whereinthe primary tag array remains available to its associated processor's core while the duplicate tag array is accessed by a physical-address probe sent from another processor of the multiprocessor system.