Patent ID: 7667539
Filing Date: 2010-02-23
Classification: H03F

Abstract:
1. An apparatus comprising: an emitter degenerated input stage coupled to a first signal input terminal, a second signal input terminal, a first signal output terminal, and a second signal output terminal, wherein the the emitter degenerated input stage includes a first resistor, a second transistor, a first resistor, and a second resistor; a Caprio circuit coupled to a first supply voltage terminal, wherein the Caprio circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third resistor, and a fourth resistor, wherein the first, second, third, and fourth resistors have substantially equal resistance values; a compression stage coupled to the first supply voltage terminal, the signal input terminals, and the Caprio circuit, wherein the compression stage includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; and a current biasing circuit coupled to the emitter degenerated input stage and the Caprio circuit, wherein the current biasing circuit includes: