Patent ID: 7826304
Filing Date: 2010-11-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first latch circuit outputting a first clock control signal for controlling internally operating clocks by latching an external clock signal and a first external clock enable signal, wherein the level of the first external clock enable signal is changed by entering a power-down mode; a control circuit outputting a second clock control signal when a power-down mode entry command is received during an read operation in an active mode, wherein the second clock control signal for controlling internally operating clocks employed in the active mode is generated by an off signal which is enabled while all data corresponding the read operation is inputted; a clock enable generation circuit receiving the first and second clock control signals and the external clock signal and outputting clock enable signals including a signal which is enabled after performing an operation related all command corresponding to the read operation, wherein the signal is generated by the first and second clock control signals when the external clock signal is disable.