Patent ID: 9009512
Filing Date: 2015-04-14
Classification: G06F,Y02D

Abstract:
1. A multi-core processor comprising: a plurality of physical processing cores; inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores; wherein the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance; wherein the hierarchical coordination system groups cores into a plurality of domain levels, including at least: for each multi-core domain level, a single core is designated as a master of that domain; each multi-core domain other than the lowest-level multi-core domains defines a kinship group consisting of master cores of constituent domains of the immediately next lower rank; each lowest-level multi-core domain defines a kinship group consisting of all of its cores; each core belongs to at least one kinship group; and each native instance of the synchronization logic is restricted from invoking new instances of the synchronization logic to cores not belonging to a native core kinship group.