Patent ID: 6563759
Filing Date: 2003-05-13
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory-cell array having a plurality of word lines and a plurality of bit lines to which memory cells are connected; a row address latch circuit which latches a row address; a row decoder which decodes the row address to thereby select a word line lying within said memory cell array; a column address latch circuit which latches a column address; a column decoder which decodes the column address to thereby select at least one bit line lying within said memory cell array; an output buffer which outputs data read from said memory cell array; an input buffer which takes in an input data; a first register capable of setting values for specifying a timing provided to take the input data in said input buffer and a timing provided to output the data from said output buffer; a second register capable of setting a value for specifying a timing provided to input a data read command or a data write command; and a timing adjustment circuit provided on a column address signal path between said column address latch circuit and said column decoder and for delaying a signal by a predetermined time according to the value set to said second register, wherein said input buffer and said output buffer are configured so as to determine operating timings according to the values set to said first register.