Patent ID: 6611466
Filing Date: 2003-08-26
Classification: G11C

Abstract:
A semiconductor memory device including memory blocks having a plurality of normal memory cells and a plurality of redundant memory cells for repairing a defective one of the normal memory cells, the semiconductor memory device comprising:a switching circuit for selectively transmitting one of a first address and a second address in response to a control signal; a control circuit for selectively activating one of 2N banks in response to Nâˆ’1 bank selection addresses and to the first address, and 2Nâˆ’1 banks in response to the Nâˆ’1 bank selection addresses, N being a natural number; and a redundant circuit for controlling the repair of the defective normal memory cells, wherein each of the 2N banks comprises one memory block, each of the 2Nâˆ’1 banks comprises 2 memory blocks, each of which is selectively activated in response to the second address, and the defective normal memory cells are repaired in an activated bank in response to an output signal of the redundant circuit.