Patent ID: 6795932
Filing Date: 2004-09-21
Classification: G06F

Abstract:
A clock switchover circuit comprising:a first inverter circuit supplied with a clock switchover signal; a NAND circuit supplied with a signal output from said first inverter circuit; a first flip-flop having a data input terminal, a clock input terminal, a reset terminal, and an output inversion signal terminal, wherein a signal output from said NAND circuit is supplied to said data input terminal, a first clock input signal is supplied to said clock input terminal, and a system reset signal is supplied to said reset terminal; a NOR circuit supplied with a signal output from said first inverter circuit; a second flip-flop having a data input terminal, a clock input terminal, a reset terminal, and an output inversion signal terminal, wherein a signal output from said NOR circuit is supplied to said data input terminal, a second clock input signal is supplied to said clock input terminal, and the system reset signal is supplied to said reset terminal; a second inverter circuit supplied with a signal output from said output inversion signal terminal of said first flip-flop; a clock signal selection section supplied with a signal output from said second inverter circuit, the first clock input signal, a signal output from said output inversion signal terminal of said second flip-flop, and the second clock input signal; and a third inverter circuit supplied with a signal output from said clock signal selection section, said third inverter circuit outputting a clock signal.