Patent ID: 7308552
Filing Date: 2007-12-11
Classification: G06F,G11C

Abstract:
1. A microcontroller, comprising: a mode terminal receiving a mode signal to distinguish a normal operation mode and a rewrite operation mode; an internal nonvolatile memory storing therein a program to be executed during said rewrite operation mode; a CPU core generating address signals sequentially, activating a first chip select signal when the address signals designate a first area, activating a second chip select signal when the address signals designate a second area, receiving, during said rewrite operation mode, rewrite data according to the program stored in said internal nonvolatile memory, and writing the received rewrite data to an electrically rewritable internal volatile memory connected to the microcontroller; a selector circuit receiving the mode signal at a select terminal thereof, transmitting the first chip select signal to an external nonvolatile memory and transmitting the second chip select signal to an external volatile memory connected to the microcontroller when the mode signal indicates said normal operation mode, and receiving the mode signal at a select terminal thereof, transmitting a first chip select signal to an internal nonvolatile memory and transmitting the second chip select signal to said external nonvolatile memory when the mode signal indicates said rewrite operation mode.