Patent ID: 6546517
Filing Date: 2003-04-08
Classification: G06F,G11C

Abstract:
A semiconductor memory comprising:a nonvolatile semiconductor storage section having a plurality of rewritable and individually accessible blocks for individually storing therein a plurality of program codes each corresponding to one of a plurality of processes; a RAM including a first storage region, wherein, said plurality of program codes are individually retrieved from said nonvolatile semiconductor storage section, and a plurality of program codes are individually loaded into said first storage region; an error correcting section connected between said RAM and said nonvolatile semiconductor storage section, wherein said error correcting section performs error correction upon one of said plurality of program codes while said one of said plurality of program codes is transferred to said RAM; and a central processing unit for executing said plurality of program codes, wherein, each of said plurality of program codes corresponds to a processing routine with a respectively assigned number, when an assigned number of a processing routine of a program code already loaded into said first storage region matches an assigned number of a processing routine of a program code to be executed, said program is executed by said central processing unit, and when the assigned number of the processing routine of the program code already loaded into said first storage region does not match the assigned number of the processing routine of the program code to be executed, a new program code to be executed is loaded into said first storage region, the new program code being one of the plurality of program codes.