Patent ID: 6888195
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. A power semiconductor device comprising: a first semiconductor layer of a first conductivity type; a first main electrode electrically connected to the first semiconductor layer; second semiconductor layers of a second conductivity type formed within the first semiconductor layer and periodically arranged in a lateral direction, a profile of an amount of an impurity in a vertical direction of the second semiconductor layers being differ from a profile of an amount of the impurity in the vertical direction of the first semiconductor layer; a third semiconductor layer of the second conductivity type selectively formed in surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively formed in a surface of the third semiconductor layer; a second main electrode formed to be connected to the surface of the third semiconductor layer and a surface of the fourth semiconductor layer; and a control electrode formed on the first semiconductor layer, the third semiconductor layer and the fourth semiconductor layer with a gate insulating film interposed therebetween, wherein the first semiconductor layer has a constant concentration of the impurity in a vertical direction from the second main electrode to the first main electrode; and the second semiconductor layer has a concentration of the impurity distributed such that the impurity concentration is decreased in the vertical direction from the second main electrode to the first main electrode.