Patent ID: 6104224
Filing Date: 2000-08-15
Classification: G11C,H03K

Abstract:
A delay circuit device comprising:a first delay circuit array so constructed that an output is taken from an arbitrary position of a first signal transmission path;a second delay circuit array so constructed that an input is applied to an arbitrary position of a second signal transmission path;at least two discriminating circuits receiving outputs from at least two positions, one position corresponding to each discriminating circuit, said two positions being along said first signal transmission path so as to divide said first delay circuit array into at least three parts; andat least three control circuits, each having a signal input terminal connected to said first delay circuit array, a signal output terminal connected to said second delay circuit array, and an input/output control terminal;wherein said first delay circuit array and said second delay circuit array are so arranged that the direction of said first and second signal transmission paths are opposite to each other,wherein an output of cascaded delay circuits in said first delay circuit array is connected to an input of cascaded delay circuits in said second delay circuit array through said control circuits in the order from the position near to an input of said first delay circuit array and in the order from the position near to an output of said second delay circuit array,wherein an input pulse signal is supplied to said first delay circuit array, and information as to whether or not a first signal of said input pulse signal is propagated to said outputs of said at least two positions which divide said first delay circuit array into said at least three parts, is respectively latched to said discriminating circuits receiving said outputs of said at least two positions,wherein when an arbitrary time has elapsed after said first signal of said input pulse signal is supplied, a second signal of said input pulse signal is selectively supplied to said control circuits, in accordance with information latched in said discriminating circuits, and said first signal on said first delay circuit array is transferred to said second delay circuit array, and said first signal on said first delay circuit array is removed from said first delay circuit array.