Patent ID: 6530040
Filing Date: 2003-03-04
Classification: G11C

Abstract:
An asynchronous memory device comprising parallel test circuitry configured to interface with a single-ended output data path of the memory device and to provide a measure of a slowest cell access time for the memory device;wherein the parallel test circuitry comprises: first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells, wherein the first circuitry comprises one or more circuits, each including an input path from a first number of the plurality of cells and configured to provide at least one of the first output signals; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom, wherein the second circuitry includes an exclusive OR circuit coupled to receive the first output signals and to produce the second output signal.