Patent ID: 8947901
Filing Date: 2015-02-03
Classification: G11C

Abstract:
1. A content addressable memory chip, comprising: a plurality of entries each having a plurality of content addressable memory cells in a memory array; a plurality of match lines, arranged corresponding to the respective entries, each coupled to the plurality of content addressable memory cells in a corresponding one of the entries; and a plurality of match amplifiers, each coupled to an associated one of the match lines and a match amplifier enable signal line, and detecting a voltage on the associated one of the match lines, wherein each of match amplifiers comprises a NAND circuit receiving the voltage on the associated one of the match lines and a voltage on the match amplifier enable signal line, wherein the NAND circuit comprises a first NMOS transistor having a gate coupled to the associated one of the match lines, a source coupled to a ground and a drain, and having a first threshold value higher than a threshold value of a standard NMOS transistor composing the content addressable memory cells.