Patent ID: 6593610
Filing Date: 2003-07-15
Classification: H01L,Y10S

Abstract:
An array of memory cells comprising:a series of capacitor constructions, the capacitor constructions having storage nodes; the capacitor constructions being defined to include a first set of capacitor constructions and a second set of capacitor constructions; a series of transistor gates over the capacitor constructions and in electrical connection with the capacitor constructions; the transistor gates being defined to include a first set that is in electrical connection with the storage nodes of the first set of capacitor constructions, and a second set that is in electrical connection with the storage nodes of the second set of capacitor constructions; a first conductive line over the transistor gates and in electrical connection with the first set of transistor gates, the first conductive line not being in electrical connection with the second set of transistor gates; and a second conductive line over the first conductive line and in electrical connection with the second set of transistor gates, the second conductive line not being in electrical connection with the first set of transistor gates.