Patent ID: 6073149
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A computational circuit for multi-value addition of two multi-value numbers each having a plurality of digits from a lowest digit to a highest digit comprising:i) A plurality of parallel adders corresponding to said digits, each of said parallel adders calculating an intermediate sum of corresponding digit of said two multi-value numbers and a carry, each of said parallel adders comprising a weighted addition circuit which comprises:a) a capacitive coupling having a plurality of capacitances output of which are connected to a common output terminal;b) an inverting amplifier connected to an output of said capacitive coupling; andc) a feedback capacitance connected to said inverting amplifier at its input and output;ii) A plurality of output adders corresponding to said parallel adders except for said parallel adder corresponding to said lowest digit, each of said output adders adding said intermediate sum output from said corresponding parallel adder and said carry output from said parallel adder of neighboring lower digit, each of said output adders comprising a weighted addition circuit which comprises:a) a capacitive coupling having a plurality of capacitances output of which are connected to a common output terminal;b) an inverting amplifier connected to an output of said capacitive coupling; andc) a feedback capacitance connected to said inverting amplifier at its input and output;iii) A plurality of quantizing circuits corresponding to said output adders and said parallel adder of said lowest digit, each of said quantizing circuits converting an output from said corresponding output adder or said parallel adder into a binary number, each said quantizing circuit comprising a plurality of thresholding circuits corresponding to digits of said binary number, each of said thresholding circuits comprising:a) an inverter with a threshold corresponding to a weight of said digit; andb) a capacitive coupling for receiving outputs from all of said thresholding circuits of higher digits for weighting said outputs by weights corresponding to weights of said digits; andiv) A plurality of logic conversion portions corresponding to said quantizing circuits, each of said logic conversion circuits converting an output of said corresponding quantizing circuit into a second intermediates sum and a second carry data.