Patent ID: 6708264
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A synchronous memory device with a prefetch address counter for accessing data items in a single cycle, said address counter comprising:an n number of one-bit counter circuits to each of which a start address supplied simultaneously with a read command, a clock signal for incrementing a count value, a signal for transferring said start address to an inside of the counter, and a signal indicating an addressing mode are supplied, and a first stage of which counts up in each cycle, thereby causing a carry signal to be inputted to following stages; an adder control circuit to which an addressing mode signal indicating a state of the addressing mode and outputs of said n one-bit counter circuits are supplied and which senses that the addressing mode is a sequential mode and said start address is an odd address and generates an even control signal for each bit; and an n number of adders which are provided so as to correspond to said one-bit counter circuits and which, according to a state of the even control signal outputted from said adder control circuit, invert an address outputted from each of said one-bit counter circuits when the addressing mode is the sequential mode and said start address is the odd address, but otherwise output the same signal as the address outputted from each of said one-bit counter circuits, wherein said n one-bit counter circuits and said n adders output n-bit addresses.