Patent ID: 7378714
Filing Date: 2008-05-27
Classification: H01L

Abstract:
1. A semiconductor device comprising a plurality of complete depletion-type SOI (silicon on insulator) transistors, each transistor comprising: a gate electrode; a source region of a first conductivity type; a drain region of the first conductivity type; a channel formation portion of a second conductivity type and disposed between the source region and the drain region; and at least one sidewall formed on a side of the gate electrode; wherein, gate electrodes of said plurality of complete depletion-type SOI transistors have different lengths from each other, the channel formation portion includes impurity concentrations that are implanted not uniformly along a gate length direction, the channel formation portion includes high concentration regions having a higher impurity concentration than at a central portion of said channel formation portion, the high concentration regions have a width that is substantially constant independent of the length of the gate electrode, the width of the high concentration regions and length of the gate electrode being along the gate length direction, and the high concentration regions extend from a region below the at least one sidewall to a region below the gate electrode.