Patent ID: 6614937
Filing Date: 2003-09-02
Classification: G06T,H04N

Abstract:
A compression circuit for a quick compression processing of two-dimensional image data, comprising:a memory having a line buffer and an image buffer for storing the required pixel data of a prediction computation; an address select device for selecting the input address from one of the line buffer or the image buffer; a register for storing a currently scanned pixel data temporarily until the next pixel is input; a divided-by-2 device for providing an output value equal to half of an input value from the register and the line buffer; a computation unit for receiving the pixel currently being scanned, the pixel from the line buffer, and the pixel from the register and divided-by-2 device, then performing the prediction computation using the received the scanned pixel data; a data write select device for selecting the scanned pixel data to be written into the line buffer or the result of the computation unit to be written into image buffer; and a control logic unit for controlling the read/write memory access.