Patent ID: 8581626
Filing Date: 2013-11-12
Classification: H03K

Abstract:
1. A control system, comprising: a logic module substrate that has a plurality of logic FPGAs on each of which logic for deriving a logic output signal from the logic input signals is mounted, and a data buffer FPGA that includes a buffer memory for buffering data to temporarily store the logic output signals from the plurality of logic FPGAs; a transmission module that transmits to the outside of the logic module substrate output logic state signals, which are logic state signals representing interim logic states of processes by the logic FPGAs of deriving logic output signals from the logic input signals; and a logic monitoring device that displays to monitor the logic state signal transmitted from the transmission module, wherein the data buffer FPGA includes an event detection unit that detects a change in the logic state signal, only when a change in the logic state signal is detected by the event detection unit, the logic output state signal being transmitted to the transmission module.