Patent ID: 6253313
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A parallel processor system for processing natural concurriencies in streams of low level instructions contained in a plurality of programs in said system, each of said streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said system comprising:means (160) for statically adding intelligence to each instruction in each of said plurality of basic blocks for each said program, said added intelligence at least having a logical processor number (LPN) and an instruction firing time (IFT)a plurality of contexts (660), each of said contexts being assigned to one of said plurality of programs for processing one of said programs, each of said contexts having at least a plurality of registers and a plurality of condition code storages for containing processing status information,a plurality of logical resource drivers (LRDs) with each logical resource driver being assigned to on eof said plurality of contexts, each of said logical resource drivers being receptive of said basic blocks corresponding to the program instruction stream of said assigned program from said adding means, each of said logical resource drivers comprising:(a) a plurality of queues (1560), and(b) means (630, 6200 operative on said plurality of said basic blocks containing said intelligence from said adding means for delivering said instruction sin each said basic block into said plurality of queues based on said logical processor number, said instruction sin each said queue being entered according to said instruction firing time wherein the earliest instruction firing time is entered first,a plurality of individual processor elements (PEs), each of said processor elements being free of any context information,means (650) connecting said plurality of processor elements to said plurality of logical resource drivers for transferring said instructions with the earliest instruction firing time first in said queues from each of said logical resource drivers, in a predetermined order, to individually assigned processor elements, each said processor element being capable of processing said transferred instruction,first means (670) for connecting each of said processor elements with any one of said plurality of contexts, each of said processor elements being capable of accessing said plurality of registers and condition code storages in a program's context during the processing of the program's instruction,a plurality of memory locations (610), andsecond means (620, 630) for connecting each of said processor elements with any one of said plurality of memory locations, each said processor element being capable of accessing said memory locations during said processing of each said instruction.