Patent ID: 8589768
Filing Date: 2013-11-19
Classification: G06F

Abstract:
1. A memory system comprising: a memory configured to be accessed via a plurality of channels; a memory interface configured to access the memory via the plurality of channels in parallel based on a plurality of access commands; an inter-channel error correction module configured to correct data in a channel where an error that remains uncorrected after use of an error correction code occurs, based on data in channels which are included in the plurality of channels, and which exclude the channel where the error has occurred but include an error correction channel, if the error occurs in an access carried out by the memory interface; an error correction channel determination module configured to determine, for each of a plurality of logical pages, a channel to be allocated to the logical page as the error correction channel so that each of the plurality of channels is allocated to a uniform number of logical pages as the error correction channel when the plurality of logical pages comprised in a logical block are sequentially written to the memory via the plurality of channels in units of pages; a command list generation module configured to generate a list of write commands each specifying that a corresponding logical page is to be written using, in parallel, channels included in the plurality of channels and excluding the error correction channel, based on the determination of the channel to be allocated to the corresponding logical page as the error correction channel; and a command list issue module configured to issue the list of the write commands to the memory interface.