Patent ID: 6829728
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A circuit for testing embedded synchronous memory in an integrated circuit, comprising:a memory having a plurality of memory words for storing data, the memory having an address port used to identify a memory word during a read or write operation of the memory, a data port that receives data to be written to the memory word during a write operation, and an output port to provide the memory word during a read operation; a BIST controller coupled to the memory, the BIST controller having a BIST address port coupled to the address port on the memory, a BIST data port coupled to the data port on the memory, and a finite state machine that controls the state of the BIST controller; compare circuitry coupled to the memory output port; and at least one pipeline register coupled between the compare circuitry and the finite state machine that delays data to the compare circuitry.