Patent ID: 6265252
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method, comprising:(a) providing an integrated circuit workpiece having a polysilicon transistor gate member extending from a generally olanar substrate;(b) forming a pair of spacers from an oxide of silicon on opposing sides of the gate member, the spacers being shaped to define a cross-sectional profike downwardly curving from the sides of the gate member towards the substrate;(c) depositing a metal layer on the workpiece;(d) heating the workpiece after said depositing to form a number of silicide regions from the metal layer; andwherein said forming of the spacers includes plasma etching with a gas mixture including about 80-99 percent fluorocarbon by volume and about 1-20 percent oxygen by volume to steepen a slope of the surface profile of each of the spacers to reduce silicide bridging.