Patent ID: 6380775
Filing Date: 2002-04-30
Classification: G11C,H03K,H03M

Abstract:
A CMOS distribution system with means for efficiently merging two synchronized data signals comprising:a first clocked CMOS signal source having an output; first clock means producing first clock pulses and coupled to said first signal source to activate said first signal source at the times of occurrence of said first clock pulses; a second clocked CMOS signal source and having an output synchronized with the output of said first clocked CMOS signal source; second clock means producing second clock pulses synchronized with and occurring at times complementary to said first clock pulses; means coupling said second clock pulses to said second signal source to activate said second signal source at the times of occurrence of said second clock pulses; first and second transmission gates having inputs and outputs with the inputs coupled to the outputs of said first and second signal sources respectively; first phase-shifting means coupled to said first clock means to produce third clock pulses phase-shifted by at least approximately 90Â°; means to couple said third clock pulses to said first transmission gate to activate said first gate at the times of occurrence of said third clock pulses; second phase-shifting means coupled to said second clock means to produce fourth clock pulses phase-shifted by at least approximately 90Â°; means to couple said fourth clock pulses to said second transmission gate to activate said second gate at the times of occurrence of said fourth clock pulses; means to couple together the outputs of said first and second transmission gates to form a multiplexer for merging the signals produced at the outputs of said first and second transmission gates to develop a stream of signals corresponding to a composite of said synchronized output signals from said first and second clocked CMOS signal sources.