Patent ID: 6247107
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A computer system comprising:a processor;a memory configured to store data for access by said processor; anda chipset coupled between said processor and said memory, wherein said chipset is configured to read first data from said memory responsive to a memory operation received from said processor, and wherein said chipset is further configured to read second data from said memory responsive to a portion of said first data, said portion of said first data comprising an address identifying a location of said second data within said memory, and wherein said chipset is configured to read third data responsive to a portion of said second data, and wherein said portion of said second data is located within said second data identical to a location of said portion of said first data within said first data;and wherein said processor, if said processor accesses said second data, selects said address of said second data from said portion of said first data, and wherein said processor is configured to transmit a second memory operation to said chipset including said address to access said second data.