Patent ID: 6252792
Filing Date: 2001-06-26
Classification: G06F,H03K

Abstract:
An integrated circuit comprising a field programmable circuit region arranged as a generally rectangular array of rows and columns of circuit areas and wherein:some of the circuit areas each provide a respective processing unit for performing operations on data on at least one respective input signal path to provide data on at least one respective output signal path;others of the circuit areas each provide a respective switching section;the processing units and the switching sections are arranged alternately in each row and in each column and at least one of the processing units and a processing unit adjacent thereto each have a first input, a second input and an output; andeach of a substantial proportion of the switching sections provides a programmable connection between at least some of the signal paths of those of the processing units adjacent that switching section in the same column and in the same row, wherein a first type of the connections provided by the switching sections are between such signal paths which are generally collinear or parallel to each other, and wherein the output of one said processing unit is connectable by such a first type of connection to the first or second input of the next processing unit in one direction in the same row, to the first or second input of the next processing unit in the one direction in the same column, to the first or second input of the next processing unit in the opposite direction in the same row, or to the first or second input of the next processing unit in the opposite direction in the same column; and wherein the integrated circuit further comprises a plurality of inter switching section signal paths, each of which extends from a respective first one of the switching sections to a respective second one of the switching sections in the same row in a direction primarily generally parallel to that row, or in the same column in a direction primarily generally parallel to that column, each of the inter switching section signal paths being programmably connectable by the respective first switching section to others of the signal paths at that first switching section, and being programmably connectable by the respective second switching section to others of the signal paths at that second switching section.