Patent ID: 6980460
Filing Date: 2005-12-27
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device includes a series connected TC unit type ferroelectric RAM which includes series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, the device comprising: first and second bit lines; first and second plate lines; a first series connected TC unit type structure which includes series connected memory cells, and has one terminal connected to the first bit line via a first selection transistor and the other terminal connected to the first plate line; a second series connected TC unit type structure which includes series connected memory cells, and has one terminal connected to the second bit line via a second selection transistor and the other terminal connected to the second plate line; word lines connected to gates of the series connected memory cells included in the first series connected TC unit type structure and gates of the series connected memory cells included in the second series connected TC unit type structure; a plate line potential control circuit which controls, in a standby state, potentials of the first and second plate lines to a first potential and, in an active state, the potential of the first plate line from the first potential to a second potential and the potential of the second plate line from the first potential to a third potential when one of the series connected memory cells included in the first series connected TC unit type structure is selected; and a bit line potential control circuit which controls a potential of the second bit line to the third potential, after charges are transferred from one of the ferroelectric capacitor included in the first series connected TC unit type structure to the first bit line.