Patent ID: 9201445
Filing Date: 2015-12-01
Classification: G06F,G09G,G11C

Abstract:
1. A gate driving circuit comprising a plurality of shift register connected in cascade, the shift register comprising: a signal outputting circuit which receives a forward direction clock signal from an external circuit and comprises a clock transistor and a level transistor, wherein the signal outputting circuit outputs the forward direction clock signal when the clock transistor is turned on and outputs a constant-low level signal when the level transistor is turned on; a signal inputting circuit which is connected to a gate of the clock transistor and receives an output signals from a previous shift register, and turns on the clock transistor when the received output signal of the previous shift register is valid; an inverting circuit which is connected to the gate of the clock transistor and a gate of the level transistor, and receives an inverse direction clock signal from the external circuit, wherein the inverting circuit turns off the clock transistor and turns on the level transistor at the same time when the inverse direction clock signal is valid; a logic circuit which is connected to the clock transistor and holds the clock transistor as being turned on before the level transistor is turned on.