Patent ID: 8631205
Filing Date: 2014-01-14
Classification: G06F,H04L

Abstract:
1. An integrated circuit, comprising: a plurality of tiles, each tile comprising: a processor configured to send data resulting from processing an instruction to one of multiple destinations accessible within a register name space of the processor; and switching circuitry including a switch to forward data received over data paths from other tiles to the processor, and to switches of other tiles, and to forward data received from the processor to other tiles, with the switching circuitry further including switch buffers that store data to be forwarded to switches of neighboring tiles, and data paths that transfer data to registers of neighboring tiles, and with at least a first one of destinations accessible within the register name space of the processor comprises a switch buffer addressed by a corresponding register specifier, and at least another one of the destinations comprises a register of a neighboring tile that is addressed by a corresponding register specifier.