Patent ID: 6529403
Filing Date: 2003-03-04
Classification: G11C

Abstract:
A memory circuit, comprising:first and second supply terminals; semiconductor layers including a resistive layer having a first portion with first and second edges; first and second bit lines disposed in one of the semiconductor layers; and a memory cell including, a first transistor disposed in one of the semiconductor layers and having a first terminal coupled to the first bit line, a second terminal coupled to the second supply terminal, and a control terminal, a second transistor disposed in one of the semiconductor layers and having a first terminal coupled to the second bit line, a second terminal coupled to the second supply terminal, and a control terminal coupled to the first bit line, and a first resistor including, a first contact region disposed in the first portion of the resistive layer, contiguous with the first edge of the first portion, having a first resistivity, and coupled to the control terminal of the first transistor, a first intermediate region disposed in the first portion of the resistive layer, contiguous with the first edge of the first portion and with the first contact region, and having a second resistivity that is higher than the first resistivity, a body region disposed in the first portion of the resistive layer, contiguous with the first and second edges of the first portion and with the first intermediate region, and having a third resistivity that is higher than the second resistivity, a second intermediate region disposed in the first portion of the resistive layer, contiguous with the second edge of the first portion and with the body region, separated from the first contact and intermediate regions, and having substantially the second resistivity, and a second contact region disposed in the first portion of the resistive layer, contiguous with the second edge of the first portion and with the second intermediate region, separated from the first contact and intermediate regions, having substantially the first resistivity, and coupled to the second bit line.