Patent ID: 6864810
Filing Date: 2005-03-08
Classification: G11C,H03M

Abstract:
1. A coding circuit comprising: M input lines that receive input signals each including at most one asserted bit, and N output lines that provide binary codes, where M is equal to 2 for each of the input lines, a set of between zero and N transistors with gates connected to the input line, each of the transistors in the set being connected to change a respective code bit on one of the output lines when turned on by an asserted bit on the input line; while an input line receives an asserted bit, the output lines together providing a respective binary code for the input line; the respective binary codes for the input lines all being unique and between zero and (M−1); for k=0 to ((M/2)−1), the respective binary codes provided by the output signals for the (2k)th and (2k+1)th input lines being complementary.