Patent ID: 7848177
Filing Date: 2010-12-07
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device, comprising a non-volatile semiconductor memory accessible for a first CPU and a second CPU different from the first CPU, wherein the non-volatile semiconductor memory includes: a plurality of word lines; a plurality of bit lines laid out to intersect the plurality of word lines; a plurality of non-volatile memory cells connected to the plurality of word and bit lines, and each operable to store data; an X decoder for decoding an X address signal transferred from the first or second CPU to form a word line select signal for selecting one of the plurality of word lines; a word driver for driving, based on the word line select signal from the X decoder, the corresponding word line to a select level; a Y decoder for decoding a Y address signal transferred from the first or second CPU to form a bit line select signal for selecting one of the plurality of bit lines; a sense amplifier for amplifying a signal output from the memory cell to the bit line; a column multiplexer operable to selectively connect, based on the bit line select signal from the Y decoder, the corresponding bit line to the sense amplifier; a output buffer for outputting an output signal of the sense amplifier to the first or second CPU; a first latch placed in a post stage subsequent to the X decoder, and operable to hold an output signal of the X decoder and then transfer the signal to the word driver; a second latch placed in a post stage subsequent to the Y decoder, and operable to hold an output signal of the Y decoder and then transfer the signal to the column multiplexer; and a third latch placed in a post stage subsequent to the sense amplifier, and operable to hold an output signal of the sense amplifier and then transfer the signal to the output buffer.