Patent ID: 6535398
Filing Date: 2003-03-18
Classification: H01L,H05K

Abstract:
A multilayer interconnect module for interconnecting a plurality of integrated circuit chips, said module comprising:a primary substrate having a top surface; a plurality of secondary substrates, each secondary substrate having a top surface, a bottom surface, and at least one side between its top and bottom surfaces, each said bottom surface being attached to the top surface of said primary substrate, at least one of said secondary substrates having a discrete capacitor formed on its top surface, each discrete capacitor having a first terminal and a second terminal disposed at the top surface of its corresponding secondary substrate; a plurality of gaps between the sides of said secondary substrates; a body of polymeric material formed in said gaps and having a top surface above the top surface of said primary substrate; a first dielectric layer formed over the top surfaces of said secondary substrates and said body of polymeric material; a plurality of vias formed through said first dielectric layer, at least two vias being connected to corresponding terminals of one said discrete capacitor; one or more additional dielectric layers formed over said first dielectric layer, each said additional dielectric layer having at least two vias formed therein; a plurality of chip connection pads formed on the uppermost additional dielectric layer for interconnecting to the plurality of integrated circuit chips; a first power supply line formed on at least one of said dielectric layers and connected to one of the terminals of one of said discrete capacitors through one of said vias formed through said first dielectric layer, said first power supply line further connected to one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers; and a second power supply line formed on at least one of said dielectric layers and connected to the other of the terminals of said one of the discrete capacitors through another one of said vias formed through said first dielectric layer, said second power supply line further connected to another one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers.