Patent ID: 6353557
Filing Date: 2002-03-05
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array including memory cells for storing at least a first data or a second data, the memory cells being arranged in matrix form having row lines and column lines, each of the memory cells having a drain, a source, a floating gate and a control gate, and having a threshold voltage varying in dependence upon an amount of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines; a row decoder for selecting at least one of the row lines; data detecting means for detecting data stored in the memory cell; injecting means for electrons to the floating gate of the memory cell; and emitting means for emitting electrons from the floating gate of the memory cell; wherein electrons are emitted from the floating gate of the memory cell by the emitting means, and then a first programming voltage is applied to the control gate of the memory cell in order to inject electrons to the floating gate of the memory cell by the injecting means so that all the memory cells store the first data, and then a second programming voltage is applied to the control gate of the memory cell in order to inject electrons to the floating gate of the memory cell by the injecting means so that the memory cell selectively stores the second data, wherein the first programming voltage is lower than the second programming voltage, and the threshold voltage of the memory cell which stores the first data is lower than the threshold voltage of the memory cell which stores the second data.