Patent ID: 8571299
Filing Date: 2013-10-29
Classification: G01N,H01L

Abstract:
1. A method for identifying systematic defects in wafer processing, comprising: performing defect inspection of a plurality of wafers; identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause; determining a physical location on each wafer where each of the defects occurs; and correlating the physical locations where each of the defects occurs with each one of different cell instances of a same cell respectively defined for those physical locations, the different cell instances having multiple rotational orientations in a hierarchical layout, the correlating comprising: normalizing the respective rotational orientations of the different cell instances into a single rotational orientation relative to layout geometry; and defect mapping to the different cell instances based on the single rotational orientation relative to the layout geometry, wherein the method is performed using a computer or a processor.