Patent ID: 6714057
Filing Date: 2004-03-30
Classification: G06F,H03K

Abstract:
A digital frequency synthesizer (DFS) circuit, comprising:a true clock input terminal; a complement clock input terminal; an output clock terminal; a pulse generator circuit having an input terminal coupled to the true clock input terminal and further having an output terminal; a control circuit having a first input terminal coupled to the output terminal of the pulse generator circuit, a second input terminal coupled to the true clock input terminal, a ground select input terminal, and first and second output terminals; a first passgate coupled between the true clock input terminal and the output clock terminal, the first passgate having a control terminal coupled to the first output terminal of the control circuit; a second passgate coupled between the complement clock input terminal and the output clock terminal, the second passgate having a control terminal coupled to the second output terminal of the control circuit; a keeper circuit having an output terminal coupled to the output clock terminal; and a ground control circuit having a data terminal coupled to the output clock terminal and a control terminal coupled to the ground select input terminal of the control circuit.