Patent ID: 7316973
Filing Date: 2008-01-08
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising the steps of: forming a phosphosilicate glass (PSG) layer over a substrate where elements are already formed; forming a capping layer on the PSG layer; forming a tetraethylorthosilicate (TEOS) layer on the capping layer; selectively etching the TEOS layer, the capping layer and the PSG layer to form a plurality of openings exposing predetermined portions of the substrate; cleaning the openings; forming a conductive layer on the openings; and removing the conductive layer until the TEOS layer is exposed, so that the conductive layer is isolated for each opening, wherein the capping layer is formed to prevent phosphorus from diffusing out from the PSG layer to the TEOS layer due to a difference in a phosphorus concentration gradient.