Patent ID: 8559578
Filing Date: 2013-10-15
Classification: H04L

Abstract:
1. A data reproduction circuit for receiving data and reproducing data and a clock, the data reproduction circuit comprising; a first clock generation circuit for generating a clock with a frequency higher than a data rate of the received data, based on a reference clock; an over-sampling determination circuit for sampling the received data by the clock generated by the first clock generation circuit, so as to convert the received data into digital signals; a data selection circuit having a circuit for reproducing data from the digital signals based on a first reproduced clock and for outputting the data, and having a phase/frequency error detection circuit for detecting a phase error and a frequency error from a timing difference between the first reproduced clock and the digital signals so as to generate and output an adjustment signal based on the phase error and the frequency error; and a second clock generation circuit having a phase/frequency adjustment circuit for adjusting a phase and a frequency of the first reproduced clock by using the adjustment signal, wherein the second clock generation circuit provides the first reproduced clock having an adjusted phase and an adjusted frequency to the data selection circuit.