Patent ID: 7079425
Filing Date: 2006-07-18
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a control code setting unit, wherein the control code setting unit sets one of a plurality of predetermined driver strength control code values as an initial control code value by selective internal programming, and wherein the control code setting unit selectively updates the set initial control code value in response to external control; a driver strength control signal generator, wherein the drive strength control signal generator receives the control code value output from the control code setting unit, and wherein the drive strength control signal generator generates a plurality of driver strength control signals corresponding to the initial control code value; a data output buffer, wherein the data output buffer individually combines sensing output data with the plurality of driver strength control signals, and wherein the data output buffer outputs weighted-data output signals; and a data output driver, wherein the data output driver includes a plurality of output drive units, wherein the plurality of output drive units are independently controlled and share an output terminal, wherein the data output driver outputs data with a controlled driver strength to the output terminal, and wherein the controller driver strength is according to respective selective operations of the plurality of output drive units corresponding to the weighted-data output signals.