Patent ID: 6408381
Filing Date: 2002-06-18
Classification: G06F

Abstract:
A computing system comprising:a memory; a system bus coupled to the memory and providing ports for coupling to additional system components; a processor coupled to the memory through the system bus, the processor comprising: a branch unit configured to handle branch instructions; a plurality of control registers within the branch unit; a decoder having a datapath coupled to the branch unit, the decoder configured to use the datapath to send control register address information to the branch unit during the decode stage in response to receiving a control register access instruction; a general purpose register file having a plurality of entries; a snapshot file having an entry for each pipeline stage, the snapshot file entry, containing an identification of a register that will be modified by an instruction in the associated pipeline stage and an indication of whether the register is a control register; and a pipe control mechanism coupled to read the snapshot file entries and notify the branch unit when a value from a selected one of the general purpose registers is available to be written back to the control register specified in the snapshot file entry.