Patent ID: 7372300
Filing Date: 2008-05-13
Classification: G09G,G11C,H03K

Abstract:
1. A shift register comprising: a clock terminal and an output terminal; a first transistor connected between said output terminal and said clock terminal; a second transistor configured to discharge said output terminal; and a first pull-down driving circuit in which a first node to which a control electrode of said first transistor is connected serves as an input node and a second node to which a control electrode of said second transistor is connected serves as an output node, wherein said first pull-down driving circuit includes: third and fourth transistors connected in series between said second node and a first power terminal; a fifth transistor connected between said second node and a second power terminal; and a sixth transistor controlled to be at a potential at said second node to flow a feedback current to a third node serving as a connection node between said third and fourth transistors.