Patent ID: 7839705
Filing Date: 2010-11-23
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a command decoding circuit configured to decode an external command to output an internal command signal for an internal operation corresponding to the external command; a control circuit configured to generate a strobe signal for controlling the internal operation in response to the internal command signal and generate an internal address signal by decoding an address signal received from an external source in response to the internal command signal wherein the internal address signal is activated earlier than the strobe signal; and a column decoding circuit configured to generate a data access signal when both the internal address signal and the strobe signal are activated, wherein the control circuit includes: a control signal generator configured to output an address latch strobe signal and a column access signal, which signals are activated at different times, in response to the internal command signal; a strobe signal generator configured to output the strobe signal in response to the column access signal; and an internal address signal generator configured to decode the address signal to output the internal address signal in response to the address latch strobe signal.