Patent ID: 6215729
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A circuit for generating a plurality of addresses in a memory array from a single address input comprising:a first control circuit having a first input connected to receive a mode select input signal and a second input connected to receive one bit of said single addressa second control circuit having a first input connected to receive said mode select input signal and a second input connected to receive another bit of said single address input;a first multiplexer having an output, a first control input connected to a first output of said first control circuit, and a second control input connected to a second output of said first control circuit;a second multiplexer having an output, a first control input connected to a first output of said second control circuit, and a second control input connected to a second output of said second control circuit;a burst counter circuit having a first, second, third and fourth output, said first and second output being connected to a first and second input, respectively, of said first multiplexer, said third and fourth outputs being connected to a first and second input, respectively, of said second multiplexer; anda counter circuit having a first input connected to an output of said first multiplexer and a second input connected to receive a signal based on said output of said first multiplexer and an output of said second multiplexer,wherein said burst counter circuit provides signals for use by said counter circuit to generate said plurality of addresses.