Patent ID: 6980033
Filing Date: 2005-12-27
Classification: H03K

Abstract:
1. A CMOS logic circuit, comprising: a NOR logic gate; and a NAND logic gate coupled thereto, wherein each of the NOR logic gate and the NAND logic gate has at least two logic inputs, a logic output, an enable clock input, a pre-charge clock input, an n-channel enable transistor having a gate connected to the enable clock input and a pull-up p-channel pre-charge transistor having a drain connected to the logic output and a gate connected to the pre-charge clock input, wherein an enable clock signal on the enable clock input activates the n-channel enable transistor and allows logic values at the at least two logic inputs to result in a logic value at the logic output, and a pre-charge clock signal on the pre-charge clock input activates the p-channel pre-charge transistor and provides a high logic potential at the logic output in preparation for the enable clock signal, wherein the enable and pre-charge clock signals are separately controlled.