Patent ID: 6259621
Filing Date: 2001-07-10
Classification: G11C

Abstract:
A twist architecture for minimizing the effects of parasitic capacitance in the data lines of a circuit, the circuit including first, second, third, and fourth data lines, comprising:a first portion in which the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line;a second portion in which the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line;a third portion in which the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; anda fourth portion in which the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line.