Patent ID: 6492847
Filing Date: 2002-12-10
Classification: H03K

Abstract:
Digital driver circuit having an input port for receiving a digital signal and an output port, the digital driver circuit comprising:one or more series-connected input stages, each input stage including a CMOS inverter, each of the one or more series-connected input stages having a p-channel MOS FET and a n-channel MOS FET and the p-channel MOS FET at its source terminal is connected to a supply voltage and the n-channel MOS FET at its source terminal is connected to ground, the ratio of the channel width (W) to the channel length (L) (the W/L ratio) of the n-channel and p-channel MOS FETs from stage to stage increase by a pre-determined amount compared to the respective n-channel and p-channel MOS FETs from a previous stage; an intermediate stage with a first CMOS inverter having a p-channel MOS FET and the p-channel MOS FET at its source terminal is connected to the supply voltage, and a second CMOS inverter having an n-channel MOS FET and the n-channel MOS FET at its source terminal is connected to ground, the inputs of both CMOS inverters of the intermediate stage are connected to the last input stage from amongst the one or more series-connected input stages, the source terminal of the n-channel MOS FET of the first CMOS inverter of the intermediate stage is connected to the source terminal of the p-channel MOS FET of the second CMOS inverter of the intermediate stage; a delay stage with a CMOS inverter having a p-channel MOSFET and an n-channel MOS FET, the CMOS inverter is connected between the supply voltage and ground, whose input is connected to the output of the last input stage and whose output is connected to the source terminal of the n-channel MOS FET of the first CMOS inverter of the intermediate stage; an output stage with a p-channel MOS FET whose gate terminal is connected to the output of the first CMOS inverter of the intermediate stage and whose source terminal is connected to the supply voltage, and an n-channel MOS FET whose gate terminal is connected to the output of the second CMOS inverter of the intermediate stage, and whose source terminal is connected to ground, the drain connections of both of the two MOS FETs of the output stage are connected to each other and to the output port, and the W/L ratio of the p-channel MOS FET of the output stage exceeds the W/L ratio of the p-channel MOS FET of the first CMOS inverter of the intermediate stage by a pre-determined value; and the W/L ratios of the p-channel and n-channel MOS FETs of the CMOS inverter of the delay stage are smaller, in comparison to the W/L ratios of the corresponding p-channel and n-channel MOS FETs of the last input stage, and the W/L ratio of the p-channel MOS FET of the CMOS inverter of the delay stage is smaller than the W/L ratio of the p-channel MOS FET of the first CMOS inverter of the intermediate stage and the W/L ratio of the n-channel MOS FET of the CMOS inverter of the delay stage is smaller than the W/L ratio of the n-channel MOS FET of the second CMOS inverter of the intermediate stage, such that the switch-over of the two MOS FETs of the output stage are offset against each other in time when the digital signal at the input port changes.