Patent ID: 6171904
Filing Date: 2001-01-09
Classification: H01L,Y10S

Abstract:
A method for forming rugged capacitance electrode comprising:sending a semiconductor wafer into a reaction chamber;adjusting said reaction chamber to a first temperature;injecting a first gas into said reaction chamber to a first pressure;forming a non-doped or doped amorphous silicon layer on the top surface of said semiconductor wafer within said reaction chamber;ceasing injecting said first gas into said reaction chamber;adjusting said reaction chamber to a second temperature higher than the first temperature;injecting said first gas into said reaction chamber at a second pressure less than the first pressure;forming a rugged polysilicon layer on said non-doped or doped amorphous silicon layer in said reaction chamber, and at the second temperature and the second pressure;forming a doping region inside said rugged polysilicon layer, as well as inside said non-doped or doped amorphous silicon layer;cleaning said semiconductor wafer; andperforming an annealing process to transform said non-doped or doped amorphous silicon layer into a polysilicon layer.