Patent ID: 6080632
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method for fabricating a semiconductor memory device including a substrate, a transfer transistor having source/drain regions formed on the substrate, and a charge storage capacitor electrically coupled to one of the source/drain regions, said method comprising the steps of:(1) forming a first insulating layer over the substrate, the insulating layer covering the transfer transistor;(2) forming a first conductive layer which penetrates through at least the first insulating layer so as to be electrically coupled to one of the source/drain regions;(3) forming an insulating pillar over the first insulating layer, the insulating pillar defining recess areas on either side thereof;(4) forming alternately, a first film of insulating material and a second film of conductive material over the first insulating layer in a recess area and over the insulating pillar;(5) removing a selected part of the second film that lies above the insulating pillar;(6) forming a second conductive layer which penetrates at least through the second film and the first film so as to be electrically coupled to one of the source/drain regions, the first and second conductive layers and the second film in combination forming a storage electrode of the charge storage capacitor;(7) removing the insulating pillar and the first film;(8) forming a dielectric layer over exposed surfaces of the first and second conductive layers and the second film; and(9) forming a third conductive layer over the dielectric layer, the third conductive layer serving as an opposing electrode for the charge storage capacitor.