Patent ID: 8344498
Filing Date: 2013-01-01
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor element; a support substrate arranged on a surface of said semiconductor element opposite to a surface thereof provided with a pad, said support substrate being bigger in area than said semiconductor element; a burying insulating layer on said support substrate for burying said semiconductor element therein; a fan-out interconnection led out from said pad via a basis hole bored through said burying insulating layer to an area on said burying insulating layer lying more peripherally outwardly than said semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of said semiconductor element for augmenting the mechanical strength of said burying insulating layer and said fan-out interconnection, wherein said reinforcement portion is an interconnection width reinforcement portion that augments width of said fan-out interconnection and the interconnection width of said interconnection width reinforcement portion is wider than that of said fan-out interconnection.