Patent ID: 8238504
Filing Date: 2012-08-07
Classification: H03L,H04L

Abstract:
1. A clock generation circuit, comprising: a first determination circuit configured to receive an input signal and detect the input signal at a first phase position based on a first frequency signal; a second determination circuit configured to receive the input signal and detect the input signal at a second phase position based on a second frequency signal; a phase detector configured to compare an output of the first determination circuit and an output of the second determination circuit, and to output a comparison result; a first summing circuit configured to sum the comparison result and a first control signal; a second summing circuit configured to sum the comparison result and a second control signal; a first voltage controlled oscillation circuit configured to receive the output of the first summing circuit, and to output the first frequency signal; a second voltage controlled oscillation circuit configured to receive the output of the second summing circuit, and to outputs the second frequency signal; and a phase adjustment circuit configured to generate the first control signal and the second control signal based on the first frequency signal and the second frequency signal.