Patent ID: 7474557
Filing Date: 2009-01-06
Classification: G11C

Abstract:
1. An access method for accessing a memory circuit block comprising a memory array in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, said respective wordlines consisting of read wordlines and write wordlines, and memory elements are provided at the intersections of the wordlines and the bitlines, each of said memory element including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through respective bitline; a read wordline driver for providing a read signal to said read wordline; and a read circuit for providing a bitline read signal to said bitline, said access method comprising the steps of: providing a first read signal onto a first read wordline to activate said first read wordline; providing said bitline read signal to a first bitline; and thereafter providing a second read signal onto a second read wordline while said first read signal is falling.