Patent ID: 7860152
Filing Date: 2010-12-28
Classification: H04B,H04J

Abstract:
1. A process of generating synchronization code signals comprising: A. providing a primary synchronization code of a generalized hierarchical Golay sequence in a first pattern of 256 bits, the first pattern being formed of 8-bit values A, B, −A and −B, in which the value A represents a pattern of real values A={1, 1, 1, 1, 1, 1, −1, −1}, the value B represents a pattern of real values B={1, −1, 1, −1, 1, −1, −1, 1}, and the first pattern of the primary synchronization code being {A, B, A, B, A, B, −A, −B, −A, −B, A, B, −A, −B, −A, −B, A, B, A, B, A, B, −A, −B, A, B, −A, −B, A, B, A, B}; B. generating a primary synchronization code signal from the primary synchronization code; C. providing a secondary synchronization code of 256 bits by exclusive OR combining a second pattern of bits and a third pattern of bits separate from the first pattern of bits, the first pattern of bits, the second pattern of bits and the third pattern of bits being different from one another, D. generating a secondary synchronization code signal from the secondary synchronization code.