Patent ID: 8796773
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A circuit structure, comprising: a substrate having a Si principal surface; at least one PFET device, comprising: a PFET gate dielectric, which PFET gate dielectric comprises a first high-k dielectric, a PFET gatestack, which PFET gatestack comprises a first metal, a p-source/drain, and a first silicide layer formed over said p-source/drain; at least one NFET device, comprising: an NFET gate dielectric, which NFET gate dielectric comprises a second high-k dielectric, an NFET gatestack, which NFET gatestack comprises a second metal, an n-source/drain, and a second silicide layer formed over said n-source/drain; and an epitaxial SiGe overlaying and in direct contact with said Si principal surface, wherein said epitaxial SiGe is present underneath and in direct contact with said PFET gate dielectric, and wherein said epitaxial SiGe is absent underneath said NFET gate dielectric, wherein both said NFET device and said PFET device comprise sidewall spacers, and said epitaxial SiGe is present underneath, and in direct contact with said sidewall spacers of both said NFET device and said PFET device.