Patent ID: 6900666
Filing Date: 2005-05-31
Classification: H03K

Abstract:
1. A domino logic circuit comprising: a domino logic processing section; an output in communication with the domino logic processing section at a dynamic node; a pull-up switch, in communication with the domino logic processing section at the dynamic node, for selectively connecting the domino logic processing section to a voltage source in accordance with a clock signal; a keeper, in communication with the domino logic processing section at the dynamic node, for selectively connecting the domino logic processing section to the voltage source in accordance with a feedback signal fed back from the output; a feedback loop for supplying the feedback signal from the output to the keeper; and a sleep switch, in communication with the dynamic node, for grounding the dynamic node in accordance with a sleep signal; wherein the output comprises an inverter which comprises a dual-V wherein the dual-V a first transistor having a first V a second transistor having a second V wherein the sleep switch comprises a transistor having the second V