Patent ID: 7539040
Filing Date: 2009-05-26
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a row direction and a column direction, the memory cell including a variable resistance element having a laminated structure comprising a rectifier junction showing rectifying characteristics in current-voltage characteristics and two electrodes for applying a voltage to the rectifier junction, the variable resistance element exhibiting current-voltage characteristics so that a positive bias current flowing when a positive voltage is applied based on one of the two electrodes as a reference electrode to the other electrode is larger than a negative bias current flowing when a negative voltage is applied to the other electrode, the current-voltage characteristics is asymmetric with respect to a voltage polarity applied to the other electrode, the variable resistance element being capable of storing information by a change of an electric resistance due to voltage application between the two electrodes; a memory cell selection circuit for selecting the memory cell from the memory cell array by the row, column or memory cell; a voltage supplying circuit for supplying a predetermined voltage according to a writing operation and reading operation, to one or more selected memory cells selected by the memory cell selection circuit through the memory cell selection circuit; and a readout circuit for reading the information stored in the selected memory cell by detecting the amount of a reading current flowing in accordance with a voltage applied to the variable resistance element of the selected memory cell and a resistance state of the variable resistance element in the reading operation for the selected memory cell, wherein the memory cell selection circuit and the voltage supplying circuit apply a predetermined positive voltage according to the reading operation based on the reference electrode to the other electrode in the variable resistance element of the selected memory cell, and the readout circuit detects the amount of the positive bias current flowing from the other electrode to the reference electrode to read the information stored in the selected memory cell, in the reading operation for the selected memory cell.