Patent ID: 6058042
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device having a plurality of memory cells in each of which an amount of charge stored in a charge storage unit changes according to a voltage supplied to a word line and a bit line, a threshold voltage changes according to the change of the amount of charge stored, and data of a value according to the threshold voltage is stored are connected, memory strings having one end and the other end connected to the bit line and a ground line via selection transistors controlled in conductive state in accordance with a gate voltage are arranged in the form of a matrix, control gates of memory cells of the same row are connected to a common word line, and multi-bit data is written into the memory cells in units of pages by using self boost, comprising:a precharging means for precharging all bit lines to a predetermined voltage before the write operation, anda write control circuit having a latch circuit by which the write data is latched, making a bit line selected in accordance with an address discharge in accordance with the latch data, and performing the write operations in parallel, whereinsaid write operations are accomplished by Fowler-Nordheim tunneling using self boost operation.