Patent ID: 9172362
Filing Date: 2015-10-27
Classification: G01R,H03K

Abstract:
1. A circuit, comprising: a load; a first differential pair coupled to the load and responsive to input data; a second differential pair coupled to the load and responsive to the input data; a third differential pair coupled to the first differential pair and the second differential pair and responsive to a first control signal and a second control signal; a bias circuit configured to pull a node coupled to both the first differential pair and the second differential pair to a predetermined state; a current source coupled to the third differential pair and the bias circuit; and control circuitry configured to generate the first control signal and the second control signal in response to a do-not-care signal and a desired data signal, wherein the control circuitry is configured to generate the first control signal by performing a logical AND operation on an inverse of the do-not-care signal and the desired data signal.