Patent ID: 8811089
Filing Date: 2014-08-19
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including plural memory cells each configured capable of storing data nonvolatilely in accordance with plural different threshold voltage distributions; and a control unit operative to, in data write to said memory cell, execute write loops each including a program operation for changing a threshold voltage of said memory cell and a verify operation for detecting said threshold voltage of said memory cell after said program operation, said control unit, in data write for changing said threshold voltage of said memory cell into an uppermost threshold voltage distribution of said plural threshold voltage distributions, executing said verify operation, using a first verify voltage when the number of write loops is equal to or less than a first number, and using a second verify voltage lower than said first verify voltage when the number of write loops is more than said first number, and said control unit, in data write for changing said threshold voltage of said memory cell into one of said plural threshold voltage distributions except for the uppermost threshold voltage distribution, not changing a verify voltage in accordance with the number of write loops.