Patent ID: 6304911
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A reception indicator circuit for use in an apparatus, wherein the apparatus enables a host system to receive information packets from a medium, said reception indicator circuit comprising:a delay calculator configured to,select and read a reference delay value in one of N number of length-delay data storage elements, wherein a reference length value contained in the one of N number of length-delay data storage elements corresponds to a length value of an information packet (PACKETSIZE) being received by the apparatus, andcalculate an interrupt time for an information packet being received by the apparatus;wherein said delay calculator calculates the interrupt time by performing the following operation:t.sub.SEG1 =A*PACKETSIZE-Bwherein:t.sub.SEG1 is the interrupt time;A is an interrupt time coefficient,B is an interrupt time constant, andPACKETSIZE is a number of bytes in a portion of the information packet;a delay comparator for detecting when the interrupt time has elapsed from an instance at which the apparatus began receiving a specified byte of the information packet; anda signal asserter for asserting a reception signal when said delay comparator detects that the interrupt time has elapsed.