Patent ID: 8024614
Filing Date: 2011-09-20
Classification: G06F

Abstract:
1. A debugger for debugging a system-on-chip device in which a microprocessor core and additional hardware for realizing an additional function are integrated together, the debugger comprising: a break detecting circuit which, when a state of said microprocessor core corresponds to a previously set condition, generates a break request signal for requesting a transition of said microprocessor core to a debug state; a trigger detecting circuit which, when a predetermined signal of said additional hardware corresponds to a previously set condition, generates a trigger request signal for requesting observation of said predetermined signal; and an execution control circuit which, when said break request signal has been transmitted, outputs a trigger signal for observing said predetermined signal by a logic analyzer and which suspends supply of a clock to said microprocessor core and said additional hardware, to cause said microprocessor core and said additional hardware to operate normally, wherein, while supply of said clock to said microprocessor core and said additional hardware is being suspended, said execution control circuit, when receiving an external command to transition said microprocessor core to said debug state, stops output of said trigger signal, outputs a break signal for causing said microprocessor core to transition to said debug state and restarts supply of said clock to said microprocessor core and additional hardware, wherein either when a software mode event has occurred or when a hardware mode event has occurred in the logic analyzer, the microprocessor core transitions to the debu state and the logic analyzer observes the observed signals where there is a break in operation of the microprocessor core.