Patent ID: 6403425
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method of creating dual-gate oxide layers with reduced thermal re-distribution of the thin-gate channel implant caused by thick-gate oxidation, comprising the steps of:providing a substrate, over the surface of said substrate having been designated a first surface area over which a thick layer of gate dielectric must be created and a second surface area over which a thin layer of gate dielectric must be created, required impurity implants having been performed into the first surface area of said substrate, regions of field isolation having been provided in the surface of said substrate; creating a first layer of gate dielectric having a first thickness over the surface of said substrate; creating a first exposure mask over the surface of said first layer of gate dielectric, said first exposure mask comprising at least one opening overlying the second surface of said substrate over which at least one PMOS device is to be created; performing first impurity implants using said first exposure mask as an implant mask; removing said first exposure mask from the surface of said first layer of gate dielectric; creating a second exposure mask over the surface of said first layer of gate dielectric, said second exposure mask comprising at least one opening overlying the second surface of said substrate over which at least one NMOS device is to be created; performing second impurity implants using said second exposure mask as an implant mask; removing said second exposure mask from the surface of said first layer of gate dielectric; creating a third mask over the surface of said first layer of gate dielectric, said third mask exposing the surface of said first layer of gate dielectric where said first layer of gate dielectric overlies the second surface of said substrate; removing said first layer of gate dielectric from the second surface of said substrate, using said third mask as an etch mask, exposing said second surface of said substrate; removing said third mask from the surface of said first layer of gate dielectric; reducing the thickness of said first layer of gate dielectric by a measurable amount; and creating a second layer of gate dielectric having a second thickness over said second surface of said substrate.