Patent ID: 7607048
Filing Date: 2009-10-20
Classification: G06F,H04L

Abstract:
1. A method comprising: determining a translation lookaside buffer (TLB) entry associated with an incoming virtual address, the TLB entry included in a translation lookaside buffer (TLB) within a processor; computing a plurality of computed parity values based on the incoming virtual address, wherein each of the plurality of computed parity values correspond to one of a plurality of possible page sizes associated with the virtual address; selecting a selected computed parity value of the plurality of computed parity values based on a page size value associated with the TLB entry; regenerating a regenerated parity value for the TLB entry based on a payload held in the TLB entry; performing a first logical operation on the regenerated parity value and the selected computed parity value to obtain a first parity value; performing a second logical operation on a stored parity value held in the TLB entry and the first parity value to obtain a second parity value, wherein the second parity error value, when representing an error value, is to indicate an error in the TLB.