Patent ID: 7362136
Filing Date: 2008-04-22
Classification: H03K

Abstract:
1. An I/O output circuit for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage, comprising: an output stage module having one or more PMOS transistors and one or more NMOS transistors for coupling with the second system; a switch module coupled to the output stage module for selectively providing the PMOS and NMOS transistors with various gate biases; and a feedback circuit coupled between an I/O pad that couples the output stage module to the second system and the switch module for controlling the switch module to generate the gate biases in response to a voltage at the I/O pad, thereby ensuring voltages across gates of the PMOS and NMOS transistors to be within a predetermined range, wherein the output stage module comprises a first PMOS transistor and a second PMOS transistor serially coupled between the I/O pad and a third voltage that is higher than the first voltage but lower than the second voltage.