Patent ID: 8140805
Filing Date: 2012-03-20
Classification: G06F,G11C

Abstract:
1. A memory system, comprising: a communication channel coupled to a controller and coupled to a memory device; the controller to generate control information and data information, including at least two write commands to the memory device followed by another command and then followed by a read command to the memory device, wherein respective data information corresponds to respective control information, the other command is between the at least two write commands and the read command; and the memory device to receive the control information and the data information in a same order as generated by the controller and to process the read command prior to completing the processing of one of the at least two write commands; wherein the memory device comprises: a memory core having dynamic random access memory cells: a first interface to receive the two write commands, each specifying a write operation; a first circuit to store a respective write command for a first time period; a second interface to receive data associated with the respective write operation, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the respective write command and the data are separated by a delay time that includes both the first time period and the second time period.