Patent ID: 6138205
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A semiconductor memory device having a burst function, comprising:a memory circuit for input/outputting information corresponding to an external input signal in synchronization with a first internal clock signal; anda burst operation control circuit, connected to said memory circuit, for receiving an external reference clock signal and a first enable signal for switching a burst operation mode and a stand-by mode, suspending supplying of said external input signal in said burst operation mode and suspending generation of said first internal clock signal in said stand-by mode;wherein said burst operation control circuit comprises:a first latch circuit for latching said first enable signal in response to a second internal clock signal and generating a first latch signal;a second latch circuit, connected to said first latch circuit, for latching said first latch signal in response to said second internal clock signal and generating a second latch signal;a first NAND circuit, connected to said first latch circuit, for receiving said first latch signal and a second enable signal for defining a period of said burst operation mode and generating a NAND logic signal;a second NAND circuit, connected between said first NAND circuit and said first and second latch circuits, for receiving said NAND logic signal and said external reference clock signal and generating said second internal clock signal;an inverter, connected to said second NAND circuit, for receiving said second internal clock signal and generating a third internal clock signal; anda burst control circuit, connected to said second latch circuit and said inverter, for receiving said second latch signal and said third internal clock signal and generating said second enable signal.