Patent ID: 7323908
Filing Date: 2008-01-29
Classification: G01R

Abstract:
1. A test circuit, comprising: at least one pass gate at least one drive device including a pull-up output and a pull-down output electrically isolated from each other, and wherein one of said outputs of said at least one drive device is connected to an input of said at least one pass gate and wherein another one of said outputs is connected to an output of said at least one pass gate, whereby a delay through said pass gate can be determined for state changes caused by said one of said outputs of said at least one drive device substantially independent of pass gate delay for an opposite state change; and a load circuit connected to said input of said at least one pass gate for simulating a loading of a transistor of said at least one drive device that provides said one of said outputs of said at least one drive device, wherein said load circuit comprises at least one disabled transistor connected in series between said output of said at least one pass gate and a power supply rail.