Patent ID: 8995666
Filing Date: 2015-03-31
Classification: H04L

Abstract:
1. A key scheduling device configured to output a first key to be used for verification of an arithmetic operation, the key scheduling device comprising: a non-linear transformation circuit that non-linearly transforms at least one of partial keys resulting from dividing an expanded key; a first linear transformer circuit that includes a plurality of sub-circuits, each of which linearly transforms the partial key resulting from dividing the expanded key, wherein a first sub-circuit of the plurality of sub-circuits linearly transforms the partial key resulting from dividing the expanded key, by directly using a transformation result from the non-linear transformation circuit; a first storage that stores the partial key linearly transformed by the first linear transformer circuit; a second linear transformer circuit that linearly transforms, inversely to the first linear transformer circuit, each of partial keys other than the partial key linearly transformed by the first sub-circuit out of partial keys stored in the first storage, and outputs inversely transformed partial keys; a second storage that stores one partial key of the at least one partial keys input to the first sub-circuit; and an outputting unit implemented by circuitry that connects the respective inversely transformed partial keys and the one partial key stored in the second storage to be output as the first key to be used for the verification of the arithmetic operation.