Patent ID: 8838997
Filing Date: 2014-09-16
Classification: G06F,G09C,H04L

Abstract:
1. A processor configured to process a plurality of message schedules, each schedule having a plurality of input words, to create a message digest according to the SHA256 specification, wherein in the processing includes an iteration loop for each of message schedules, wherein (i) is a value indicating the current iteration count of the loop, and wherein w(i−x) indicates one of the input words according to the value of x as determined by the processing, the processor comprising: a first execution unit to receive a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling iteration, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs, and to execute the first instruction based on the first and second set of message inputs to produce an intermediate result; and a second execution unit to receive a second instruction to process a second part of the SHA256 message scheduling iteration, the second instruction having a third operand associated with a third storage location to store the intermediate result and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs, and to execute the second instruction based on the intermediate result and the third and fourth sets of message inputs to produce message inputs for a next iteration of the loop, wherein execution of the first and second instructions complete the current iteration, wherein for a current iteration (i) of the loop, the first storage location stores message inputs w(i−13), w(i−14), w(i−15), and w(i−16), wherein the second storage location stores message inputs w(i−9), w(i−10), w(i−11), and w(i−12), wherein the intermediate result includes w(i−13)+s0(w(i−12)), w(i−14)+s0(w(i−13)), w(i−15)+s0(w(i−14)), and w(i−16)+s0(w(i−15)), wherein the third storage location stores a combination of the intermediate result and message inputs w(i−5), w(i−6), and w(i−7), and wherein the message inputs for the next iteration represent w(i+3), w(i+2), w(i+1), and w(i).