Patent ID: 8271699
Filing Date: 2012-09-18
Classification: G06F

Abstract:
1. A parallel accessible memory system enabling the simultaneous access to bytes of data, comprising: n (where n is an integer greater than or equal to 2) memory arrays for storing data, each memory array having: q (where q is an integer greater than or equal to 1) data interface or data interfaces for transferring data; a decoder for receiving an address A from an address bus and for outputting an n sets of select signals as an access request to the n memory arrays; and (n−1) selector or selectors respectively corresponding to said each memory array other than the n-th memory array, each selector being arranged for receiving an (n−1) set of select signals from the decoder, for receiving the address A from the address bus, and for outputting the (n−1) set of select signals as an access request to its respective memory array, wherein the n-th set of select signals output from the decoder bypasses the selectors and is directly received by the n-th memory array.