Patent ID: 6587367
Filing Date: 2003-07-01
Classification: G11C

Abstract:
A ferroelectric memory device, comprising:an array of FeRAM memory cells associated with a target memory cell, wherein each memory cell in the array is operable to store binary data in a ferroelectric capacitor, which is accessed by a transistor; a bitline decode logic operable to select a bitline associated with the target memory cell during a read operation; a word line decode logic operable to select a word line associated with the target memory cell; a reference circuit comprising a plurality of FeRAM dummy cells wherein each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines, wherein the reference circuit is operable to generate a reference voltage which is a function of a charge shared between the plurality of FeRAM dummy cells, and further operable to apply the reference voltage to a select one of the plurality of bitlines associated with the reference circuit and the target memory cell during a read operation; and a sense amplifier operable to receive the reference voltage on the selected bitline of the plurality of bitlines associated with the reference circuit and the target memory cell, and to receive a cell sense voltage from the target memory cell on another bitline of the plurality of bitlines associated with the sense amplifier and the target memory cell, whereby when the target memory cell is accessed for a read operation, its data are presented in the form of an analog signal to the sense amplifier, where it is compared against the reference voltage to determine a logic state of the target memory cell during a read operation.