Patent ID: 8003505
Filing Date: 2011-08-23
Classification: H01L

Abstract:
1. A method comprising: preparing a substrate including a pixel region and a logic region each having at least one transistor and at least one gate; forming a first interlayer dielectric film over the substrate to cover said at least one gate of said pixel region and said logic region; forming first contact holes over said interlayer dielectric film to expose a region of the substrate corresponding to said pixel region and a part of said at least one gate of said pixel region; forming first contacts by filling said first contact holes with a metal material; forming a second interlayer dielectric film over a surface of said first interlayer dielectric film; simultaneously forming second contact holes over said second interlayer dielectric film to expose said first contacts, and third contact holes over said second interlayer dielectric film and said first interlayer dielectric film to expose a region of the substrate corresponding to said logic region and a part of said at least one gate of said logic region; and forming second contacts by filling said second contact holes and said third contact holes with a metal material.