Patent ID: 6790684
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method of constructing a chip-scale semiconductor package from a wafer-on-wafer package comprising:providing a semiconductor device wafer having at least one active surface and an opposite surface, the semiconductor device wafer comprising a plurality of unsingulated semiconductor dice having die bond pads exposed on the at least one active surface of the semiconductor device wafer; providing a support wafer having a die connect surface and a testing/mounting surface of the support wafer; forming a plurality of vias arranged in a preselected pattern, the plurality of vias extending from the die connect surface of the support wafer to the testing/mounting surface of the support wafer; disposing a plurality of electrically conductive traces on the die connect surface of the support wafer, the plurality of electrically conductive traces having a prepositioned die bond pad connect element end and a via end terminating at one of the plurality of vias; locating a plurality of electrically conductive die bond pad connect elements on the die connect surface of the support wafer; introducing a volume of an electrically conductive material within at least some of the plurality of vias, the volume of the electrically conductive material completing an electrical path between selected ones of the plurality of electrically conductive die bond pad connect elements respectively associated with the at least some of the plurality of vias and terminating in a first meniscus proximate the testing/mounting surface of the support wafer to provide a plurality of test connection/mounting elements; attaching the plurality of electrically conductive die bond pad connect elements to the die bond pads to mechanically and electrically connect the semiconductor device wafer to the support wafer to create the wafer-on-wafer package; contacting at least some of the plurality of test connection/mounting elements of the wafer-on-wafer package with correspondingly positioned test probes; electrically exercising and testing the plurality of unsingulated semiconductor dice by directing electrical signals through the test probes and through the electrical paths provided by the volume of the electrically conductive material introduced within the at least some of the plurality of vias; and singulating portions of the wafer-on-wafer package to render a plurality of chip-scaled semiconductor die packages.