Patent ID: 6248626
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method for producing a floating gate on the back of a transistor channel, comprising:forming a buried oxide on a conducting substrate;forming a back-plane over the buried oxide;forming a back oxide over the back-plane;forming a silicon layer over the back oxide, the silicon layer having a thickness substantially comparable to that of said back-plane, through which charge gets injected into the back-plane; andpatterning a silicon region for the memory to form a source, drain and channel region of the memory and a floating gate region, and filling, with an insulator, said source, drain and channel region and the floating gate region;wherein the back-plane is formed of a conductive high electron affinity material which does not substantially interact with the back-oxide and the buried oxide,wherein said back-plane is formed of any of W, WN, TiN, and alloys thereof.