Patent ID: 7205642
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first circuit layer and the second circuit layer, wherein at least one second opening is formed on the second circuit layer and at least one first opening is formed on the first circuit layer at a position corresponding to the second opening, and wherein a plurality of finger holes are formed in the core layer at positions corresponding to a plurality of bond fingers formed on the first circuit layer, and a through opening is formed in the core layer and communicates with the first and second openings, wherein a Ni/Au layer is formed on the bond fingers respectively; at least one chip mounted on the first circuit layer of the substrate to cover the first opening, allowing an active surface of the chip to be exposed to the first opening; a plurality of bonding wires for electrically connecting the active surface of the chip to the plurality of bond fingers on the first circuit layer through the finger holes; and an encapsulant for filling the first and second openings and the through opening and encapsulating the chip and the bonding wires.