Patent ID: 7086023
Filing Date: 2006-08-01
Classification: G06F

Abstract:
1. A system for determining timing criticality information of an electrical circuit comprising: a. a netlist input for receiving a circuit netlist, the circuit netlist representing a topology of the electrical circuit; b. an assertion input for receiving one or more assertions representing boundary timing conditions; c. a delay variability input for receiving a list of one or more sources of delay variation that contain variability information of one or more of the sources of delay variation; d. a model input for receiving a parameterized delay model, the parameterized delay model containing a model for delay variation of each component of the electrical circuit, each model being a function of one or more of the sources of delay variation; and e. a process that determines and outputs the timing criticality information of the electrical circuit; wherein the timing criticality information is a node criticality probability of each of one or more nodes of the electrical circuit.