Patent ID: 6420261
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A semiconductor device manufacturing method comprising the steps of:forming a first insulating film, a first organic insulating film, a second insulating film, and a metal film in sequence over a semiconductor substrate; forming a first opening having a wiring pattern profile by etching the metal film partially; forming a second opening having a via pattern profile by etching a portion of the second insulating film which overlaps with a part of the first opening; forming a third opening having the via pattern profile in the first organic insulating film by etching the first organic insulating film through the second opening using the second insulating film as a mask; forming a fourth opening having the wiring pattern profile in the second insulating film by etching the second insulating film through the first opening of the metal film, and simultaneously forming a fifth opening having the via pattern profile by etching the first insulating film through the third opening of the first organic insulating film, the fifth opening being applied as the via-hole; forming a sixth opening having the wiring pattern profile in the first organic insulating film by etching the first organic insulating film through the fourth opening of the second insulating film, the sixth opening and the fourth opening being applied to a wiring recess; forming a via in the via-hole and forming a wiring in the wiring recess by burying a conductive material simultaneously into the via-hole and the wiring recess; and removing the metal film.