Patent ID: 7515654
Filing Date: 2009-04-07
Classification: H04L

Abstract:
1. A data slicing circuit for binarizing a demodulated signal including a known data pattern followed by unknown data, comprising: a peak hold circuit for detecting and holding a peak level of the demodulated signal; a bottom hold circuit for detecting and holding a bottom level of the demodulated signal; an intermediate potential generator for generating a plurality of threshold potentials intermediate between the peak level of the demodulated signal and the bottom level of the demodulated signal; a plurality of comparators for comparing the demodulated signal with respective threshold potentials generated by the intermediate potential generator, thereby generating a plurality of binarized signals; and a baseband signal processing circuit for comparing the known data pattern with corresponding parts of the plurality of binarized signals, selecting one of the binarized signals best matching the known data pattern, and using the selected binarized signal to recover the unknown data, wherein the plurality of threshold potentials include a potential offset by a first predetermined amount from the peak level when the peak level differs from the bottom level by at least a second predetermined amount, and set proportionally between the peak level and the bottom level when the peak level differs from the bottom level by less than the second predetermined amount.