Patent ID: 6865638
Filing Date: 2005-03-08
Classification: G06F

Abstract:
1. An apparatus for transferring multi-byte words in a flyby DMA operation, comprising: FIFO coupled to a memory and a PCI-bus such that multi-byte words transferred between said memory and said PCI-bus are buffered by said FIFO; first register storing a first write pointer to a next available byte location to be written to in said FIFO when said multi-byte words are being transferred from said memory to said PCT-bus, and a first read pointer to a next available byte location to be read from in said FIFO when said multi-byte words are being transferred to said memory from said PCI-bus; second register storing a second read pointer to a next available byte location to be read from in said FIFO when said multi-byte words are being transferred from said memory to said PCI-bus, and a second write pointer to a next available byte location to be written to in said FIFO when said multi-byte words are being transferred to said memory from said PCI-bus; and control logic configured to manage transfer of said multi-byte words to and from said buffer, shift said first write pointer and said first read pointer to match a starting byte address of a first multi-byte word at the beginning of a fly-by DMA operation from said memory to said PCI-bus, and shift said second write pointer and said second read pointer to match a starting byte address of a first multi-byte word at the beginning of a fly-by DMA operation to said memory from said PCI-bus.