Patent ID: 7811925
Filing Date: 2010-10-12
Classification: C23C,C25D,H01L,Y10S

Abstract:
1. A method of forming a capping layer on conductive lines in a semiconductor device, the method comprising: (a) providing a semiconductor substrate comprising a dielectric layer having (i) copper lines disposed therein, (ii) a barrier layer on at least field regions of the dielectric layer, and (iii) copper overburden covering the copper lines and barrier layer; (b) removing said copper overburden by a technique other than an isotropic wet etch to a point prior to exposing the barrier layer; (c) isotropically wet etching the remaining overburden to expose the barrier layer and selectively remove material from said copper lines to form recesses in the copper lines while providing an exposed barrier layer on field regions of the dielectric layer; and (d) depositing a capping layer material on at least the recessed copper lines of the semiconductor substrate.