Patent ID: 8843794
Filing Date: 2014-09-23
Classification: G01R,G06F,G11C,H04L

Abstract:
1. An apparatus comprising: test control logic to perform test rounds for a device including I/O buffer circuits which each comprise a respective transmit path and a respective receive path, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits, each of the test rounds corresponding to a different respective delay between a first clock signal and a second clock signal, the first clock signal to regulate communication along the respective transmit paths of each of the I/O buffer circuits, the second clock signal to regulate communication along the respective receive paths of each of the I/O buffer circuits; fail detect logic to determine that a first test round of the test rounds indicates a failure condition for at least one I/O buffer circuit of the I/O buffer circuits, and to determine that a second test round of the test rounds indicates the failure condition for each of the I/O buffer circuits; and evaluation logic to calculate a difference between the delay corresponding to the first test round and the delay corresponding to the second test round, and to generate, based on the difference, a signal indicating whether the device satisfies a test criterion.