Patent ID: 8772922
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A chip structure having a redistribution layer, comprising: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; a first passivation layer formed on the active surface and the electrode pads and having a plurality of first openings for exposing the electrode pads, respectively; the redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units comprises a conductive pad, a conductive via disposed in one of the first openings and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer formed on the first passivation layer and the redistribution layer and filled in the first through opening of the conductive trace of each of the wiring units and having a plurality of second openings for exposing the conductive pad of each of the wiring units, wherein the redistribution layer is comprised of a seed layer and a metal layer disposed in sequence, and the conductive trace has a widened portion and two elongated portions connecting the widened portion to the conductive pad and the conductive via, respectively, the first through opening being formed in the widened portion.