Patent ID: 9064556
Filing Date: 2015-06-23
Classification: G11C

Abstract:
1. A method for accessing a bitcell of a pseudo dual port (PDP) memory, comprising: asserting a word line voltage during a read portion of a memory clock cycle to couple a bitcell to a bit line and a complement bit line for a bit line pair; de-asserting the word line voltage for a write precharge portion of the memory clock cycle; and during the write precharge portion of the memory clock cycle, selectively precharging to a power supply voltage VDD only one of the bit line and the complement bit line in the bit line pair while discharging a remaining one of the bit line and the complement bit line, the selective precharging and discharging being responsive to a bit value to be written into the bitcell; coupling the selectively precharged and discharged bit line pair to the bitcell to write the bit value into the bitcell during a read/write clock cycle.