Patent ID: 7078305
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A process for fabricating a high value polysilicon resistor on a semiconductor wafer, the process comprising the steps of: forming at least one oxide layer; fabricating a first polysilicon layer on the at least one oxide layer; forming an opening in the first polysilicon layer exposing at least one oxide layer, the opening having a periphery defining a vertical edge; fabricating a second polysilicon layer of a thickness of about 1000 A entirely covering the surface of the first polysilicon layer, the vertical edge, and any exposed oxide in the etched opening; patterning and etching the second polysilicon layer on the exposed oxide and the vertical edge to define the outer edges and length of the high value resistor; the single second polysilicon layer forming the body of the high value resistance, patterning and etching the second polysilicon layer on the first polysilicon layer to define ends of the high value resistor, the two layer second and first polysilicon layers so defined forming the two ends of the high value resistance; covering the high value resistor and the ends with a dielectric; and forming metal contacts reaching through the dielectric to each of the ends thereby making electrical connections to the high value resistor.