Patent ID: 8575701
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A semiconductor device having a DRAM region and a logic region embedded therein, comprising: a substrate having said DRAM region and said logic region respectively formed thereon; a first transistor formed in said DRAM region, and having a first gate insulating film; and a second transistor formed in said logic region, and having a second gate insulating film, wherein equivalent oxide thickness T said second transistor formed in said logic region has, at each end of the source/drain regions thereof, a pocket region which contains an impurity ion having a conductivity type different from a conductivity type of an impurity ion composing said source/drain regions, said first transistor formed in said DRAM region has no pocket region formed at each end of the source/drain regions thereof, and at least a part of said pocket region is located in surficial portions of said substrate between the source/drain regions.