Patent ID: 8589465
Filing Date: 2013-11-19
Classification: G06F

Abstract:
1. Digital signal processing (“DSP”) block circuitry comprising: first multiplier circuitry for producing a first plurality of parallel output signals indicative of a first multiplication product of a plurality of parallel multiplicand signals and a plurality of parallel multiplier signals; first systolic delay circuitry for delaying at least one of (1) the plurality of parallel multiplicand signals and (2) the plurality of parallel multiplier signals by at least one systolic delay time interval; second multiplier circuitry for producing a second plurality of parallel output signals indicative of a second multiplication product; adder circuitry for adding the first and second pluralities of output signals and a third plurality of parallel signals indicative of a data value received from a first other instance of said DSP block circuitry; output register circuitry for registering output signals of the adder circuitry; and second systolic delay circuitry for delaying outputs of the output register circuitry by at least one of the systolic delay time interval.