Patent ID: 7541237
Filing Date: 2009-06-02
Classification: G11C,H01L

Abstract:
1. A method of constructing an array of non-volatile memory cells on a substrate, comprising: forming a plurality of trenches in the substrate that are elongated in a first direction across the substrate and spaced apart in a second direction across the substrate, the first and second directions being orthogonal to each other, filling said plurality of trenches with a dielectric material, forming a first layer of gate material in strips having lengths extending in the first direction and spaced apart in the second direction to lie between the dielectric filled trenches and extend a distance over the dielectric material with which the trenches are filled on either side thereof in the second direction, forming over the first layer of gate material a second layer of gate material in strips having lengths extending in the second direction and being spaced apart in the first direction, covering with a first mask a first set of spaces between the second gate material layer strips including every other space across the substrate in the first direction and leaving exposed a second set of spaces between the second gate material layer strips including remaining every other space across the substrate in the first direction and in between the first set of spaces, etching the first gate material layer strips through the exposed second set of spaces, implanting ions into the substrate through the exposed second set of spaces, thereby to form source and drain regions in the substrate, thereafter forming conductive strips within the exposed second set of spaces that are elongated in the second direction and individually electrically contact a plurality of the source and drain regions along their lengths, removing the first mask to expose the first set of spaces, etching the first gate material layer strips through the exposed first set of spaces, thereby exposing edges of the first layer strips, forming layers of tunnel dielectric on the exposed first layer strip edges, and thereafter forming from a third layer of gate material control gates having lengths extending in the first direction over the first and second gate material layers with the conductive strips extending into the first set of spaces in contact with the tunnel dielectric, thereby to serve as erase gates.