Patent ID: 6098163
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A data processing apparatus comprising:an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input signal for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least one combination performing a Boolean function prior to an arithmetic function;a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;a second data source supplying a second multibit digital signal;a shifter having a data input connected to said second data source, a shift control input receiving a shift control signal, and a data output connected to said second data input of the arithmetic logic unit, said shifter shifting said second multibit digital signal an amount corresponding to said shift control signal and supplying said shifted second multibit digital signal to said second data input of said arithmetic logic unit;a third data source supplying a third multibit digital signal to said third data input of said arithmetic logic unit;a data register file includinga plurality of data registers for storing data,a first output connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source,a second output connected to said second data input of said arithmetic logic unit for recalling form a second specified data register data stored therein, thereby forming said second data source,a third output connected to said third data input of said arithmetic logic unit for recalling from a third specified data register data stored therein, thereby forming said third data source,a first input connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals, anda predetermined one of said plurality of data registers being a special function data register storing therein a default shift amount; andsaid shift control input of said shifter receives said default shift amount of said special function data register.