Patent ID: 6463111
Filing Date: 2002-10-08
Classification: H03L,H04J

Abstract:
An apparatus for desynchronizing a DS-3/E3 signal from the demapped data portion of a SONET/SDH signal which includes pointer justifications and bit stuffs, said apparatus comprising:a) a first FIFO having an input and an output, said input receiving the de-mapped data portion of a SONET/SDH signal; b) a write address counter associated with said first FIFO and incremented by said data bits only of said data portion of said SONET/SDH signal, said write address counter indicating a writing location in said FIFO; c) a read address counter associated with said first FIFO, said read address counter indicating a reading location in said FIFO; d) an intermediate address count register which indicates an intermediate location in said FIFO between said reading and writing locations, said intermediate address count register being incremented in part as a function of said pointer justifications and said stuff bits; and e) a first clock for reading data out of said FIFO and for incrementing said read address counter, said first clock having a rate substantially equal to said DS-3/E3 signal, and said first clock derived in part from a difference between a count of said read address counter and a count of said intermediate address count register.