Patent ID: 6677650
Filing Date: 2004-01-13
Classification: G11C,H01L

Abstract:
A system-on-chip comprising:a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM component and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM component and a combination thereof; a layer of an insulative material overlaying the silicon substrate, the first component and the second component, wherein a first silicon plug, in electrical contact with the first component, extends through the layer of insulative material to the silicon substrate, and a second silicon plug, in electrical contact with the second component, extends through the layer of insulative material to the silicon substrate; and an interconnect comprising a salicide located over, and in electrical contact with, the second silicon plug, wherein the second silicon plug is a dual plug comprising one section of N-type doped silicon and one section of P-type doped silicon.