Patent ID: 6308258
Filing Date: 2001-10-23
Classification: G06F

Abstract:
A data processing circuit to which are input a certain target instruction and a prefix instruction for expanding the function of said target instruction, comprising:instruction code analysis means for inputting said prefix instruction, subsequently inputting said target instruction, and analyzing the operation details of instruction code thereof; andinstruction execution means for executing said instructions based on said operational details analyzed by said instruction code analysis means, wherein:said instruction code analysis means comprises immediate-data expansion means for expanding immediate data necessary for the execution of the target instruction which is subjected to function expansion by said prefix instruction based on said prefix instruction,said instruction execution means executes said target instruction based on immediate data expanded by said immediate-data expansion means,said instruction code analysis means comprises target instruction function expansion means for analyzing operational details of a target instruction when said target instruction is input after the input of a prefix instruction, andsaid instruction execution means executes said target instruction in accordance with said operational details expanded by said target instruction function expansion means, wherein said target instruction function expansion means uses two operands of said target instruction and immediate data comprised within said prefix instruction to expand the operational details of said target instruction into a three-operand instruction, when a predetermined target instruction that is a two-operand instruction is input after the input of a prefix instruction.