Patent ID: 6754952
Filing Date: 2004-06-29
Classification: H01L,H05K,Y10T

Abstract:
A process for manufacturing a multiple layer wiring board incorporated therein a thin-film capacitor, the process comprising:forming a metallic film layer consisting of a barrier metal layer and a metal layer possible to be anode oxidized, in this order, on a first conductor pattern formed on an insulating layer; covering a lower electrode forming region of the thin film capacitor in the first conductor pattern attached to the insulating layer with a first resist film; etching to remove a portion of the metallic film layer, where the portion is not covered with the first resist film; removing the first resist film and covering a face of the first conductor pattern, except for a region on the metallic film layer, with a second resist film; forming an anodic oxidation film on the metallic film layer exposed from the second resist film; removing the second resist film and attaching an adherence layer and a metal seed layer, in this order, on the anodic oxidation film and on the first conductor pattern; and forming a second conductor pattern, which becomes an upper electrode, on the anodic oxidation film.