Patent ID: 8848532
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. A method for processing data in a processor that includes multiple cores, the method comprising: storing received packets in a same stream sequentially, comprising: receiving Get_packet commands sent by the cores; selecting among the stored packets, according to a preset scheduling rule, packets for processing by each of the cores, comprising: receiving tag switching commands sent by the cores, wherein each tag switching command indicates that a particular core has finished a current processing stage of a particular packet; and for each packet for which a current processing stage has been finished by a corresponding core, performing tag switching in First In First Out (FIFO) order of the stored packets, to switch the packet to a subsequent processing stage performed by a subsequent core, wherein packets for which a current processing stage has finished are allocated to subsequent cores according to Get_packet commands sent by the subsequent cores after completion of their respective tag switching, so that the packet processing continues until all processing stages are finished, wherein performing tag switching in FIFO order comprises: storing the packets into a bind FIFO queue in FIFO order; transferring the packets in the bind FIFO queue from a current group queue to a new group queue; and updating tags of the packets.