Patent ID: 7846806
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A method of manufacturing a self aligned silicon germanium heterojunction bipolar transistor, the method comprising the steps of: forming a non-selective epitaxial growth (NSEG) collector; forming an NSEG base over the NSEG collector; forming an NSEG monocrystalline silicon emitter over the NSEG base; and performing a first etch process to remove non-central portions of the NSEG monocrystalline silicon emitter and non-central portions of the NSEG base; wherein the step of forming the NSEG base comprises the steps of: wherein performing the first etch process comprises removing the non-central portions of the NSEG monocrystalline silicon emitter and non-central portions of the third layer of the NSEG base down to the second layer of the NSEG base.