Patent ID: 6501171
Filing Date: 2002-12-31
Classification: H01L

Abstract:
An electronic package, comprising:a circuitized substrate having an upper surface; a semiconductor chip mounted on said upper surface of said circuitized substrate and electrically coupled to said substrate, said semiconductor chip having a substantially planar upper surface and at least one edge surface being substantially perpendicular to said substantially planar upper surface; a thermally conductive member being provided with an array of perforations and having upper and lower surfaces, said lower surface of said thermally conductive member being thermally coupled to said substantially planar upper surface of said semiconductor chip, said thermally conductive member further having at least one edge surface extending around a defined perimeter of said thermally conductive member; and a substantially rigid dielectric material positioned on at least a portion of said circuitized substrate, against at least a portion of said at least one edge surface of said thermally conductive member, and against at least a portion of said at least one edge surface of said semiconductor chip, and said dielectric material being at least partially filled into said perforations so as to enhance the mechanical interlocking between said thermally conductive member and said semiconductor chip.