Patent ID: 6998672
Filing Date: 2006-02-14
Classification: H01L

Abstract:
1. A memory cell comprising: a substrate; a source region formed in the substrate; a drain region formed in the substrate; a channel region provided between the source region and the drain region and having a variable electrical conductivity; a source-end control gate extending at least partially over a source-end edge section, which adjoins the source region, and being designed to change the electrical conductivity of the source-end edge section; a drain-end control gate extending at least partially over a drain-end edge section, which adjoins the drain region, and being designed to change the electrical conductivity of the drain-end edge section; an injection gate arranged between the source-end control gate and the drain-end control gate and extending over a central section of the channel region, the injection gate being electrically isolated from the drain-end control gate and designed to change the electrical conductivity of the central section, which extends between the source-end edge section and the drain-end edge section of the channel region; a source-end storage element extending at least between the source-end edge section and the source-end control gate; a drain-end storage element extending at least between the drain-end edge section and the drain-end control gate; and a gate oxide arrangement having at least one gate oxide layer extending between the substrate on the one side and the source-end control gate, the drain-end control gate and the injection gate on the other side, wherein the source-end control gate and the drain-end control gate are electrically connected to one another.