Patent ID: 6115733
Filing Date: 2000-09-05
Classification: G06F,H03M

Abstract:
A processor capable of calculating the reciprocal of an operand B comprising:an initial estimate generator configured to receive said operand B and output an initial estimate X.sub.0 of the reciprocal of the operand;a multiplier coupled to receive said operand and said initial estimate, wherein said multiplier is configured to calculate a product of said initial estimate and said operand;an overflow logic unit coupled to invert and normalize selected bits from said product to form a first approximation of the quantity (2-X.sub.0 .times.B), wherein said first approximation assumes an overflow has occurred in said multiplier;a non-overflow logic unit coupled to receive and invert selected bits from said product to form a second approximation of the quantity (2-X.sub.0 .times.B), wherein said second approximation assumes an overflow has not occurred in said multiplier; anda multiplexer configured to select either said first or second approximations.