Patent ID: 6472288
Filing Date: 2002-10-29
Classification: H01L,Y10S

Abstract:
A method of forming transistors of different designs on a single chip, said method including steps offorming a first protective layer on a substrate including collector regions of respective transistors, forming a second protective layer on said first protective layer, said second protective layer and said first protective layer being selectively etchable with respect to each other, patterning said second protective layer and said first protective layer to a collector region, forming a first base layer, patterning said first base layer and said second protective layer to said first protective layer with a hard mask, forming a further second protective layer, patterning said further second protective layer and said first protective layer to another collector region, forming a second base layer, patterning said second base layer and said further second protective base layer to said first protective layer, and completing transistors including said first base layer and said second base layer, respectively.