Patent ID: 6333566
Filing Date: 2001-12-25
Classification: H01L

Abstract:
A semiconductor device, comprising:a wiring substrate having a first surface and a second surface opposed to the first surface, said wiring substrate having a plurality of conductive lines formed on the first and second surfaces and a through hole extending between the first and second surfaces thereof;a first semiconductor IC chip having a first surface, a second surface opposed to the first surface and a plurality of side surfaces extending between the first and second surfaces, said first IC chip including a plurality of first bond pads formed on the first surface thereof, said first IC chip being disposed in the through hole of said wiring substrate so that the first surface of said wiring substrate is substantially level to the first surface of said first IC chip;a second semiconductor IC chip having a first surface, a second surface opposed to the first surface and a plurality of side surface extending between the first and second surfaces, said second IC chip including a plurality of second bond pads formed on the first surface thereof, said second IC chip being disposed in the through hole of said wiring substrate so that the second surface of said second IC chip is fixed to the second surface of said first IC chip, and a level of the second surface of said wiring substrate is level to the first surface of said second IC chip;a plurality of first conductive wires that connect the bond pads of said first IC chip and the conductive lines formed on the first surface of said wiring substrate, respectively;a plurality of second conductive wires that connect the bond pads of said second IC chip and the conductive lines formed on the second surface of said wiring substrate, respectively;first sealing resin that coats said first conductive wires, the first and side surfaces of said first IC chip and a part of the first surface and the through hole of said wiring substrate; anda second sealing resin that coats said second conductive wires, the first and side surfaces of said second IC chip and a part of the second surface and the through hole of said wiring substrate, wherein said first and second sealing resins are a substantial sole member for physically connecting said first and second IC chip and said wiring substrate.