Patent ID: 6100829
Filing Date: 2000-08-08
Classification: G11B

Abstract:
A digital peak detection system comprising:an analog to digital converter having an input terminal and an output terminal;an absolute value circuit having an input terminal and an output terminal, said absolute value circuit input terminal coupled to said analog to digital converter output terminal;a first AND gate having a plurality of input terminals and an output terminal;a plurality of comparator stages, each of said comparator stages comprising a first delay element and a comparator having a first input terminal, a second input terminal, and an output terminal, said first delay element coupled in series between said second input terminal of said comparator stage and said second input terminal of a preceding comparator stage, said comparator stage output terminal coupled to one of said plurality of inputs of said first AND gate;said absolute value circuit output terminal coupled to said first input terminal of a first comparator stage of said plurality of comparator stages;a plurality of post-comparison stages, each of said post-comparison stages comprising a second delay element having an input terminal and an output terminal, and a second AND gate having a first inverted input terminal, a second input terminal and an output terminal, said second delay element input terminal coupled to said second AND gate output terminal of a preceding post-comparison stage, said second delay element output terminal coupled to said second AND gate second input terminal, said second AND gate first inverted input terminal coupled to said first AND gate output terminal;said first AND gate output terminal coupled to said second delay element input terminal of a first post-comparison stage of said plurality of post-comparison stages; andwherein a signal of a predetermined polarity from said output of said second AND gate of a last post-comparison stage of said plurality of post-comparison stages indicates detection of a local peak.