Patent ID: 6291330
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A method of fabricating a gate structure to reduce a stress production, the method comprising the steps of:providing a substrate with isolation structures formed therein, wherein the isolation structures define an active region on the substrate;forming a first oxide layer on the substrate;forming a mask layer on the first oxide layer;patterning the mask layer to form a gate opening, which gate opening exposes a part of the first oxide layer;removing the exposed part of first oxide layer until the substrate is exposed;forming in sequence a second oxide layer, a conductive layer, and a cap layer on the exposed substrate, wherein the second oxide layer, the conductive layer, and the cap layer form a gate stack having a plurality of sidewalls;partially removing the mask layer;performing a lightly doped drain (LDD) implantation to form a source/drain region in the substrate; andforming a spacer on the sidewalls of the gate stack and on the remaining of the mask layer.