Patent ID: 8429501
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. A log likelihood ratio (LLR) generation method, adaptable to a memory storage device, wherein the memory storage device comprises a flash memory chip having a plurality of memory cells, each of the memory cells has a plurality of storage states, and the storage states are distinguished by at least one bit data read voltage, the method comprising: obtaining a read data from the memory cells by using the at least one bit data read voltage, wherein the read data is corresponding to a first storage state, and the first storage state is one of the storage states; performing an error checking and correcting (ECC) procedure on the read data to obtain a second storage state corresponding to the read data when the read data is written, wherein the second storage state is one of the storage states; obtaining an amount of storage error in the storage states satisfying a statistic number, wherein the storage error means that a corresponding data is in the second storage state when the data is written and is in the first storage state when the data is read; and executing a logarithmic operation according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.