Patent ID: 6717209
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A semiconductor device comprising:a first conductivity-type semiconductor substrate; a gate wire formed over a gate insulating layer on a predetermined portion of the substrate; second conductivity-type source/drain regions formed in the substrate at opposite edges of gate wire; a second conductivity-type junction diode formed in the substrate at a predetermined distance apart from the source/drain regions; an inter-level insulating layer formed over the gate wire, the source/drain regions and the junction diode; first and second contact holes penetrating through the inter-level insulating layer to expose predetermined portions of the gate wire and junction diode; first and second conductivity plugs formed in the respective first and second contact holes; a metal wire formed on a predetermined portion of the inter-level insulating layer and coupled with the gate wire through the first conductivity plug; and a dummy metal pattern formed on the inter-level insulating layer at a predetermined distance apart from the metal wire, and coupled with the junction diode through the second conductivity plug, such that the junction diode and dummy metal pattern are not in direct contact with the metal wire.