Patent ID: 6281536
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A ferroelectric memory device, comprising:a ferroelectric capacitance element formed through an insulating film on a semiconductor substrate,wherein said ferroelectric capacitance element comprises:a lower electrode;a ferroelectric film formed on said lower electrode; andan upper electrode formed on said ferroelectric film, andwherein said upper electrode has a laminate structure which contains a conductive oxide layer of first metal which is connected with said ferroelectric film;said ferroelectric memory device further comprising a wiring layer formed on said ferroelectric capacitance element through an insulating film, and connected with said upper electrode, andwherein a bottom layer of said wiring layer is formed of a tungsten layer or a metal silicide layer, andwherein said metal silicide layer is a tungsten silicide (WSix) layer.