Patent ID: 6686856
Filing Date: 2004-02-03
Classification: H03M

Abstract:
A clocking domain conversion system, comprising:an input operable to simultaneously load N input bits during each load cycle at an average rate RIN, wherein N has an integer value of at least 1; an output operable to simultaneously output M output bits during each output cycle at an average rate ROUT, wherein M has an integer value of at least 1 and Mâ‰ N; a routing circuit operable to route the N input bits from the input to the output at a clocking rate RCLK and with a dividing ratio K of the routing circuit data rate relative to the higher of the input and output data rates, given by K=N&CenterDot;RCLKM&CenterDot;ROUT&it;â€ƒ&it;if&it;â€ƒ&it;RIN<ROUT,â€ƒ&it;and&it;â€ƒ&it;K=M&CenterDot;RCLKN&CenterDot;RIN&it;â€ƒ&it;if&it;â€ƒ&it;RIN>ROUT;anda clock generator operable to generate a clock signal for controlling the routing circuit and characterized by a non-uniform sequence of pulses having an average period T between successive pulses, given by T=KRCLK.