Patent ID: 7233889
Filing Date: 2007-06-19
Classification: G06F

Abstract:
1. A noise immunity evaluation design apparatus for evaluating noise immunity using a software simulation that represents a design of a circuit for a semiconductor device comprising: an acquiring unit, acquiring the software simulation, the software simulation including a simulated external noise source, a simulated external circuit, an impedance of a design power supplying circuit, an impedance of a design logic circuit, and an impedance of a design grounding circuit, the noise immunity evaluation apparatus further comprising: a specifying unit, specifying a first frequency of a voltage generated by the noise source; a calculating unit, calculating a first voltage directly across the design logic circuit impedance when a voltage of the specified first frequency is applied; an outputting unit, outputting the specified first frequency and the calculated first voltage; and an evaluation unit operable to output an evaluation of the noise immunity of the simulation circuit model, for the first frequency of a voltage generated by the noise source in comparison with a predetermined tolerance level for external noise where the evaluation is utilized to modify at least one of the impedances until the calculated first voltage falls within the predetermined tolerance level.