Patent ID: 6839398
Filing Date: 2005-01-04
Classification: G11C

Abstract:
1. A shift-register circuit for a first clock signal, a second clock signal and an input pulse to output a shift-register signal, comprising: an input circuit for receiving the input pulse and outputting a high-voltage level input signal when the input pulse is at high voltage level; a level shifting circuit coupled to the input circuit, comprising: a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD; a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD; a first NMOS transistor having a third gate coupled to the first gate, a third drain coupled to the first drain, and a third source; a second NMOS transistor having a fourth gate coupled to the second gate, a fourth drain coupled to the second drain and a fourth source; a third NMOS transistor having a fifth gate coupled to the fourth source, a fifth drain coupled to the first drain and an output terminal, and a fifth source coupled to a second voltage VSS; a fourth NMOS transistor having a sixth gate coupled to the third source, a sixth drain coupled to the second drain, and a sixth source coupled to the second voltage VSS; a fifth NMOS transistor having a seventh gate coupled to the input circuit, a seventh drain coupled to the third source and a seventh source coupled to the first clock signal; a sixth NMOS transistor having an eighth gate coupled to the input circuit, an eighth drain coupled to the fourth source and an eighth source coupled to the second clock signal; and an output circuit coupled to the output terminal for outputting the shift-register signal.