Patent ID: 6673676
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A method of fabricating a flash memory cell, comprising the steps of:providing a semiconductor substrate; defining an active area on the substrate; forming a first gate insulating layer within the active area; forming a first conductive layer on the first gate insulating layer; forming a first masking layer on the first conductive layer; removing a portion of the first masking to form a first opening and expose the first conductive layer; forming a floating gate insulating layer on the exposed surface of the first conductive layer by an oxidation process; removing a portion of the first masking between the two adjacent floating gate insulating layers to expose the surface of the first conductive layer; removing a portion of the first conductive layer and the first insulating layer between the two adjacent floating gate insulating layers using the floating gate insulating layer as a hard mask, such that a second opening is formed to expose the surface of the substrate; forming a source region by implanting impurity ions through the second opening into the substrate; forming a second insulating layer on the surface of the floating gate insulating layer and the first masking layer and filling the second opening; performing a planarization process using the first masking layer as a stop layer to remove a portion of the second insulating layer on the first masking layer and leaving the portion on the floating gate insulating layer and in the second opening; removing the first masking layer; forming a floatinq gate region using the remaining second insulating layer as a mask and etching portions of the first conductive layer and the first insulating layer to expose the surface of the substrate, such that the first conductive layer remaining under the floating gate insulating layer becomes a floating gate, the remaining first insulating layer becomes a gate insulating layer, and then, the remaining second insulating layer, the gate insulating layer and the floating gate are combined as the floating gate region; forming a third insulating layer to cover the surface of the substrate and the surface and the sidewalls of the floating gate region; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; removing portions of the fourth insulating layer, such that the fourth insulating layer remaining on the sidewalls of the second conductive layer forms first sidewall spacers; forming control gates and a tunneling oxide using the first sidewall spacers as a hard mask and removing portions of the second conductive layer and the third insulating layer to form a third opening on the remaining second insulating layer and a fourth opening on the substrate, such that the remaining second conductive layer becomes the control gates, and then, the remaining third insulating layer becomes a tunneling oxide; forming second sidewall spacers on the sidewalls of the third opening and the fourth opening; and forming a drain region on the substrate within the fourth opening.