Patent ID: 6218251
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method of fabricating an asymmetrical IGFET from a semiconductor device that comprises a substrate, a gate structure disposed on the substrate, a protective layer over the gate structure and at least a portion of the substrate, source/drain regions aligned by the gate structure, and a channel region beneath the gate structure, the method comprising the steps:forming a pair of spacers abutting respective sides of the gate structure and covering portions of the protective layer;etching portions of the spacers concurrently with portions of the protective layer not covered by the spacers;applying a photoresist layer over only a first one of the spacers;etching away the second one of the spacers;removing the photoresist; andsubjecting the semiconductor device to ion implantation so that asymmetrical source/drain regions are formed in the semiconductor device.