Patent ID: 6686618
Filing Date: 2004-02-03
Classification: H01L

Abstract:
Semiconductor memory (1) comprisinga. a plurality of memory-cell arrays (2); b. a plurality of sense-amplifier areas (3); and c. a plurality of driver areas (4) on a semiconductor substrate (7) of a first conductivity type, each of the multiple sense-amplifier areas (3) and multiple driver areas (4) containing at least one first well (9) of the first conductivity type and/or at least one second well (10) of a second conductivity type, and each first well (9) of the driver areas (4) being isolated from the semiconductor substrate (7) by a buried horizontal layer (8) of the second conductivity type, characterized in that the buried horizontal layer (8) extends continuously beneath at least all the memory-cell arrays (2) and the multiple driver areas (4) of the semiconductor memory (1), and the second well (10) is separated from the buried horizontal layer (8) so that the second well (10) is electrically isolated from the buried horizontal layer (8).