Patent ID: 8686507
Filing Date: 2014-04-01
Classification: H01L

Abstract:
1. A system for electrostatic discharge protection, the system comprising: a plurality of transistors, the plurality of transistors including a plurality of gate electrodes formed in parallel, a plurality of source regions, and a plurality of drain regions, the plurality of source regions and the plurality of drain regions being located within an active area in a substrate, the active area being adjacent to at least an isolation region in the substrate; and a polysilicon region, the polysilicon region not being part of the gate regions and completely enclosing the plurality of source and drain regions in a top view, and separated from the substrate by a dielectric layer; wherein a first part of the polysilicon region intersects each of the plurality of gate regions at two distal ends, each of the gate electrodes having a first side associated with one of the source regions extending continuously along the first side between the two distal ends and a second side associated with one of the drain regions extending continuously along the second side between the two distal ends, wherein the plurality of gate electrodes is not mesh-shaped or grid-shaped; wherein each one of the source regions comprises at least a source contact; wherein each one of the drain regions comprises at least a drain contact; wherein a second part of the polysilicon region on the active area is disposed along an inner peripheral edge of the active area, the inner peripheral edge of the active area being adjacent to the at least an isolation region, wherein the second part of the polysilicon region on the active area does not intersect the plurality of gate electrodes.