Patent ID: 6396749
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A memory capable of substituting a second memory cell for an inoperative memory cell, the memory comprising:a primary array of memory cells; a redundant array of memory cells; and redundancy content addressable memory (CAM) circuitry, the circuitry comprising a plurality of dual-ported CAM stages, each CAM stage comprising: a CAM cell to store information regarding a location of an inoperative memory cell in the primary array, the inoperative memory cell requiring a substitution with a second memory cell in the redundant array; a write data bus, coupled to the CAM cell, to produce the information from the CAM cell responsively to a write select signal, the write select signal indicative of a write operation to be performed at memory cell locations in the primary array; and a read data bus, coupled to the CAM cell, to produce the information from the CAM cell responsively to a read select signal, the read select signal indicative of a read operation to be performed at memory cell locations in the primary array.