Patent ID: 7084056
Filing Date: 2006-08-01
Classification: H01L

Abstract:
1. A method of forming an electrical interconnection, comprising: forming a first insulation layer on a semiconductor substrate; forming at least a first recessed portion in the first insulation layer; filling the first recessed portion with metal to form a first metal pattern; forming a metal anti-oxidation layer on the first insulation layer and the first metal pattern, the metal anti-oxidation layer preventing the first metal pattern from being oxidized; forming a first diffusion barrier layer on the metal anti-oxidation layer, the first metal pattern and the first insulation layer, the first diffusion barrier layer including a metal oxide and preventing metal of the first metal pattern from diffusing out of the first metal pattern; forming a second insulation layer on the first diffusion barrier layer; forming at least a second recessed portion in the second insulation layer, the second recessed portion exposing a portion of the first metal pattern; and filling the second recessed portion with metal to form a second metal pattern, wherein the metal anti-oxidation layer is formed before the first diffusion barrier layer to be under the first diffusion barrier layer.