Patent ID: 8497554
Filing Date: 2013-07-30
Classification: H01L

Abstract:
1. A method of forming an electronic fuse of a semiconductor device, the method comprising: forming a high-k dielectric material and a metal-containing cap layer above an isolation region and a semiconductor region of said semiconductor device, and thereafter forming a recess comprising a recessed surface portion in said isolation region; forming a semiconductor electrode material above said semiconductor region and said recessed surface portion of said isolation region; forming a gate electrode structure above said semiconductor region and a semiconductor body of an electronic fuse above said recessed surface portion; forming a dielectric material above and laterally adjacent to said gate electrode structure and said semiconductor body; exposing a surface of said semiconductor electrode material selectively in said gate electrode structure by performing a planarization process; and performing a selective etch process so as to remove said semiconductor electrode material selectively in said gate electrode structure.