Patent ID: 6134701
Filing Date: 2000-10-17
Classification: G06F,H05K,Y02P

Abstract:
A computer motherboard comprising:a rectangular four-layer printed circuit board comprising a top layer and a bottom layer, the top layer comprising top, bottom, left and right sides;a processor socket installed near the bottom-left corner of the top layer of the circuit board, the processor socket comprising an address section having a plurality of address pins positioned at a top-right corner of the processor socket, and a data section having a plurality of data pins positioned at a left side of the processor socket, the data section being divided into a high-order-bit data section having a plurality of high order data pins positioned at a bottom-left corner of the processor socket, and a low-order-bit data section having a plurality of low order data pins positioned at a top-left corner of the processor socket;a cache data RAM installed on the top layer of the circuit board positioned approximately on the right side of the processor socket, the cache data RAM comprising a high-order-bit data section having a plurality of high order data pins, a low-order-bit data section having a plurality of low order data pins, and an address section having a plurality of address pins;a control chip installed on the top layer of the circuit board positioned approximately on the top side of the cache data RAM and on the top-right side of the processor socket, the control chip comprising an address section having a plurality of address pins positioned at a bottom-middle portion of the control chip, a high-order-bit data section having a plurality of high order data pins positioned at a bottom-right corner of the control chip, and a low-order-bit data section having a plurality of low order data pins positioned at a bottom-left corner of the control chip;a cache tag RAM installed on the top layer of the circuit board positioned roughly between the processor socket and the cache data RAM, the cache tag RAM comprising an address section having a plurality of address pins;a high-order-bit data bus comprising a plurality of conductors for connecting the high-order-bit data section of the processor socket, the high-order-bit data section of the cache data RAM, and the high-order-bit data section of the control chip through the top and bottom layers of the circuit board for transmitting high-order-bit data;a low-order-bit data bus comprising a plurality of conductors for connecting the low-order-bit data section of the processor socket, the low-order-bit data section of the cache data RAM, and the low-order-bit data section of the control chip through the top and bottom layers of the circuit board for transmitting low-order-bit data; andan address bus comprising a plurality of conductors for connecting the address section of the processor socket, the address section of the cache tag RAM, the address section of the control chip, and the address section of the cache data RAM through the top and bottom layers of the circuit board for transmitting data addresses.