Patent ID: 6014759
Filing Date: 2000-01-11
Classification: G11C

Abstract:
A memory device, comprising:an output driver circuit having a data output terminal adapted for coupling to a data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal and to produce output data corresponding to input data in the absence of the error signal;a memory array having a plurality of memory cells arranged in rows and columns;an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells in the memory array;a data path coupled between the I/O interface and the data input terminal of the output driver circuit;a comparing circuit coupled to the I/O interface, the comparing circuit comparing the data read from the plurality of memory cells to error criteria and producing the error signal in response to the data meeting the error criteria; andan error line coupled between the comparing circuit and the error input terminal.