Patent ID: 8111827
Filing Date: 2012-02-07
Classification: H04L

Abstract:
1. A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL −1 function in a cryptographic process, comprising: a first arithmetic gate configured to receive a first input bit string and a first extended key bit string, the first input bit string being an upper N-bit string in a 2N-bit input of the cryptographic processing apparatus, the first extended key bit string being based on one of an upper N-bit string and a lower N-bit string of an extended key, the first arithmetic gate being one of an AND gate and an OR gate; a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, the second input bit string being a lower N-bit string in the 2N-bit input of the cryptographic processing apparatus; a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, the second extended key bit string being based on the other of the upper N-bit string and the lower N-bit string of the extended key, the second arithmetic gate being a gate different from the first arithmetic gate and the other of the AND gate and the OR gate; a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string; a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, the third arithmetic gate being a same gate as the first arithmetic gate and the one of the AND gate and the OR gate; and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.