Patent ID: 6643831
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A method for analyzing parasitic impedance in a circuit, comprising:receiving a description of a layout of the circuit; receiving an identification of a conductor to be analyzed in the circuit; tracing the conductor to be analyzed using the description of the layout of the circuit; determining parasitic impedance values including determining an inductance value for the conductor using a parameterized inductance table with pre-computed inductance values, the pre-computed inductance values being computed from a partial inductance matrix including mutual partial inductance values; and creating a circuit description for the conductor using the parasitic impedance values, wherein determining the inductance value for the conductor comprises: analyzing, using the description of the layout of the circuit, structures within a selected distance of the conductor within the circuit; determining a computed distance from the conductor to a current return path for the conductor; and using the computed distance to the current return path and the parameterized inductance table to determine the inductance value for the conductor.