Patent ID: 6049876
Filing Date: 2000-04-11
Classification: G06F

Abstract:
A data processing system which detects an unauthorized memory access, comprising:a processing unit for communicating data and address information which is processed;a memory coupled to the processing unit for communicating data with the processing unit in response to receiving address information from the processing unit, the memory storing data in pages, one or more of said pages each having one or more predetermined address regions which if addressed cause an exception signal to be generated;logic circuitry coupled to the processing unit for generating the exception signal, the logic circuitry receiving the address information and in response identifying: (1) whether the address information is addressing any of the pages having one or more predetermined address regions which cause an exception signal to be generated, and generating a first hit signal which identifies which page of the memory the address information corresponds to; (2) whether the address information is addressing any of the one or more predetermined address regions and generating a second hit signal which identifies, if any, of the one or more predetermined address regions the address information corresponds to; and (3) generating the exception signal in response to occurrence of both the first hit signal and the second hit signal; andsecurity logic coupled to the logic circuitry for affecting what action the processor takes in response to the exception signal being provided.