Patent ID: 6631505
Filing Date: 2003-10-07
Classification: G06F,H01L

Abstract:
A simulation circuit for a MOS (Metal Oxide Semiconductor) transistor for doing simulation testing of said MOS transistor using a netlist showing internal configurations of said MOS transistor, said simulation circuit comprising:a feedback capacitor formed between a gate electrode and a drain electrode of said MOS transistor; and wherein said feedback capacitor includes a diode having a predetermined junction capacitance characteristic and a diode having a predetermined electrostatic capacity characteristic and wherein said junction capacitance characteristic of said diode is chiefly displayed when an absolute value of a voltage of said drain electrode is larger than an absolute value of a voltage of said gate electrode and said electrostatic capacity characteristic of said capacitor is chiefly displayed when said absolute value of a voltage of said drain electrode is smaller than said absolute value of a voltage of said gate electrode and said junction capacitance characteristic of said diode and said electrostatic capacity characteristic of said capacitor are equally displayed when said absolute value of said voltage of said gate electrode is almost same as said absolute value of said voltage of said drain electrode.