Patent ID: 6081444
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A static semiconductor memory, comprising:CMOS memory cells each having two cross-coupled inverters, in each of which an n-channel transistor and a p-channel transistor are connected in series with each other,wherein gate lines each of which connects gates of said n-channel transistor and said p-channel transistor of each said cross-coupled inverter, respectively, have two portions, one of said two portions being a connection line connecting said gates of said n-channel transistor and said p-channel transistor of each said inverter, the other portion being an elongation expanding from said connection line in a substantially perpendicular direction to said connection line,wherein two contacts used to cross-couple said two inverters are located at ends of said elongations, andwherein at least one of said two contacts used to cross-couple said two inverters is located in any region other than a region enclosed by the diffused sources and drains of said n-channel transistor and p-channel transistors included in each memory cell.