Patent ID: 7633322
Filing Date: 2009-12-15
Classification: H03L

Abstract:
1. A digital loop circuit having an input terminal for receiving a reference signal having at least one of (a) a reference frequency and (b) a reference phase, and an output terminal for outputting an output signal that is at least one of (a) frequency-locked, and (b) phase-locked, to said reference signal, said digital loop circuit comprising: digital error-detecting circuitry receiving as inputs said reference signal and said output signal, and outputting a digital signal representing error in at least one of (a) frequency, and (b) phase, between said reference signal and said output signal; digital loop filter circuitry comprising: a first memory that accumulates said error signal and outputs a first control signal when said accumulated error exceeds a first accumulation threshold, a second memory that accumulates said first control signal and outputs a proportional control signal when said accumulated first control signal exceeds a second accumulation threshold, and additional memory that accumulates said proportional control signal and outputs an integral control signal when said accumulated proportional control signal exceeds a third accumulation threshold; and digitally-controlled oscillator circuitry that provides said output signal based on said first control signal and said proportional control signal.