Patent ID: 8490110
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. A network on chip (‘NOC’) comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; and each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox, wherein the IP blocks, routers, memory communications controllers and network interface controllers comprise modules of automated computing machinery; wherein the outbox comprises an array indexed by an outbox write pointer and an outbox read pointer, the outbox further comprising an outbox message controller enabled to set the outbox write pointer, set the outbox read pointer, and send, to the network, message data written into the array by a thread of execution associated with the outbox.