Patent ID: 8174046
Filing Date: 2012-05-08
Classification: H01L

Abstract:
1. An integrated circuit having memory, comprising: thyristor-based memory cells, each of the thyristor-based memory cells including a thyristor-based storage element and an access transistor, the thyristor-based storage element including an anode region and a cathode region in a substrate; a first pair of the thyristor-based memory cells commonly coupled via a bitline region in the substrate associated with the access transistor; the first pair of the thyristor-based memory cells defining a first parasitic bipolar junction transistor therebetween responsive to the bitline region being common; and the bitline region having a first locally thinned region to inhibit charge transfer between the first pair of the thyristor-based memory cells via the first parasitic bipolar junction transistor; wherein the first locally thinned region is approximately 50 to 80 percent in profile thickness of the bitline region prior to etching to form the first locally thinned region; and wherein the bitline region is silicided in the first locally thinned region to provide a first salicide region disposed in the first locally thinned region.