Patent ID: 7930607
Filing Date: 2011-04-19
Classification: G01R

Abstract:
1. A circuit for boosting encoding capabilities of a test stimulus decompressor, comprising: a plurality of scan chains receiving a test pattern from the test stimulus decompressor over a plurality of shift cycles; at least one care bit forming the test pattern; an align-encode circuit for connecting between the test stimulus decompressor and the plurality of scan chains, the align-encode circuit receiving the test pattern and further receiving control data, said control data being computed based on the position of the least one care bit of the test pattern, the align-encode circuit delaying at least one fragment of the test pattern based on the control data to manipulate the test pattern into an encoded test pattern, and sending the manipulated encoded test pattern to the scan chains; a plurality of delay registers with at least one delay register being connected to an input of one of the scan chains, the at least one delay register delaying the scan chain for a selected number of delay cycles based on the at least one control data; and a plurality of multiplexers being driven by the respective delay registers for the scan chain for insertion of the selected number of delay cycles.