Patent ID: 6972995
Filing Date: 2005-12-06
Classification: G11C

Abstract:
1. A semiconductor circuit comprising: a reset transistor having a drain region, a source region, and a gate connected to receive a plurality of reset pulses; a photodiode connected to the reset transistor; and a non-volatile memory device connected to the reset transistor and the photodiode; wherein the non-volatile memory device has a drain region, a source region, a floating gate, and a control gate that is connected to the reset transistor and the photodiode, wherein the plurality of reset pulses occur during a single image capture cycle and wherein when a first number of photons are collected by the photodiode, a first number of electrons are injected onto the floating gate, and when a second number of photons less than the first number are collected by the photodiode, a second number of electrons are injected onto the floating gate that is greater than the first number.