Patent ID: 9026063
Filing Date: 2015-05-05
Classification: H02M

Abstract:
1. A circuit comprising: a first p-type metal oxide semiconductor (PMOS) transistor having a source coupled with a first node, a gate coupled with a second node, and a drain coupled with a first input terminal; a second PMOS transistor having a source coupled with the second node, a gate coupled with the first node, and a drain coupled with a second input terminal; a first n-type metal oxide semiconductor (NMOS) transistor having a drain coupled with the first node, a gate coupled with the second node, and a source coupled with a first output terminal; a second NMOS transistor having a drain coupled with the second node, a gate coupled with the first node, and a source coupled with a second output terminal; a first capacitor coupled with the first node and a third node to receive a first clock signal; and a second capacitor coupled with the second node and a fourth node to receive a second clock signal.