Patent ID: 7742356
Filing Date: 2010-06-22
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells requiring a refresh operation so as to hold stored information; and a refresh circuit performing the refresh operation to memory cells connected to a predetermined number of word lines in a first refresh mode and performing the refresh operation to memory cells connected to less than the predetermined number of word lines in a second fresh mode, wherein the refresh operation in the first refresh mode is performed in response to an external refresh command supplied from outside the semiconductor memory device and the refresh operation in the second refresh mode is performed in response to an internal refresh command generated automatically in the semiconductor memory device, wherein the refresh circuit includes a first refresh cycle changing circuit and a second refresh cycle changing circuit, wherein the first refresh cycle changing circuit performs the refresh operation to the memory cells connected to the predetermined number of word lines in the first refresh mode, and wherein the second refresh cycle changing circuit performs the refresh operation to the memory cells connected to less than the predetermined number of word lines in the second refresh mode.