Patent ID: 6512272
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A FET which comprises:(a) a body region of a first conductivity type; (b) a gate separated from said body region by a gate dielectric ; (c) a pair of source/drain regions of opposite conductivity type on a first pair of opposing sides of said body region; and (d) each of high VT regions and a low VT region, said low VT region and said high VT region extending in said body under said gate dielectric from a region adjacent one source/drain region to a region adjacent to the other source/drain region, said high VT regions being disposed adjacent said low VT region and on opposing sides of said low VT region, the dielectric separating the gate from the high VT regions being more leaky than the dielectric separating the gate from the low VT region, such that said high VT regions contribute substantially to the gate-to-body capacitive coupling.