Patent ID: 7626876
Filing Date: 2009-12-01
Classification: G11C

Abstract:
1. A test method for a memory device comprising steps of: (a) preparing a memory device including: a plurality of memory elements disposed in columns; word lines to which a select signal is applied to allow data to be input to and output from a predetermined one of said plurality of memory elements; and bit lines and inverted bit lines connected to said plurality of memory elements and input with signals having mutually inverted logic levels when data is to be written to the memory element selected by said select signal; (b) selecting a memory element; (c) inputting an input signal for test to said bit line of the memory element selected at said step (b), outputting an output signal corresponding to said test input signal from said inverted bit line, and detecting whether said input and output signals correspond to data having mutually inverted logic levels; (d) repeating said steps (b) and (c) by changing the memory element to be selected by said step (b) to select all of said plurality of memory elements; (e) after said step (d), selecting a memory element; (f) inputting an input signal for test to said inverted bit line of the memory element selected at said step (e), outputting an output signal corresponding to said test input signal from said bit line, and detecting whether said input and output signals correspond to data having mutually inverted logic levels; and (g) repeating said steps (e) and (f) by changing the memory element to be selected by said step (e) to select all of said plurality of memory elements.