Patent ID: 8599641
Filing Date: 2013-12-03
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of core chips each including an output terminal; and an interface chip that includes an input terminal electrically connected to the output terminals in common, and a data input circuit that receives a plurality of read data supplied from the output terminals via the input terminal, the interface chip issuing at least a read command to the core chips, wherein each of the core chips includes a data output circuit that outputs the read data to the output terminal in response to the read command, and an output timing adjustment circuit that adjusts an output period from a first time to a second time, the output period being a period of time from reception of the read command to outputting of the read data from the data output circuit to the output terminal, the second time of each core chips being substantially same as each other.