Patent ID: 6707162
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A chip package structure, at least comprising:at least one chip having an active surface, a plurality of chip pads and a plurality of bonding columns, wherein the chip pads are located on the active surface of the chip and the bonding columns are connected to their corresponding chip pads, respectively; and a substrate having a substrate surface, a plurality of junction pads, a plurality of trace lines and a solder mask layer, wherein the substrate surface includes a chip junction region and a non-chip junction region, the junction pads and a portion of the trace lines are located within the chip junction region on the substrate surface and the remaining trace lines are located within the non-chip junction region on the substrate surface, the solder mask layer covers the non-chip junction region for protecting the trace lines within the non-chip junction region, and the bonding columns are directly connected to the corresponding junction pads without any connection medium between them, respectively; and an underfill layer that completely fills the space within the chip, the bonding columns and the substrate.