Patent ID: 6823411
Filing Date: 2004-11-23
Classification: G06F

Abstract:
A system comprising:a first bus master; a second bus master; a first bus arbiter coupled to the first and the second bus masters; a second bus arbiter coupled to the first and the second bus masters; a first bus slave coupled to the first bus arbiter, the first bus master requesting a first data operation on the first bus slave via the first bus arbiter, the first data operation being performed during a first period; a second bus slave coupled to the second bus arbiter, the second bus master requesting a second data operation on the second bus slave via the second bus arbiter, the second data operation being performed during the first period; a first gating logic coupled to the first master for receiving the first arbitration request and the first address information from the first master, and coupled to the first bus arbiter for providing the first arbitration request to the first bus arbiter; and a second gating logic coupled to the second master for receiving the second arbitration request and the second address information from the second master, and coupled to the second bus arbiter for providing the second arbitration request to the second bus arbiter.