Patent ID: 9012283
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A method of forming Field Effect Transistors (FETs), said method comprising: defining FET locations on a layered semiconductor wafer, said layered semiconductor wafer having semiconductor gate dielectric formed on a surface semiconductor layer, semiconductor gates being formed in all FET locations; identifying semiconductor gate locations, at least one FET location being identified as a semiconductor gate location, remaining FET locations being metal gate locations, a plurality of said FET locations being first type FET locations with said semiconductor gate dielectric having a selected thickness, said plurality of said FET locations including at least one metal gate location and at least one semiconductor gate location; replacing semiconductor gates with metal in said metal gate locations, wherein at least one semiconductor gate FET of said first type has a lower threshold than metal gate FETs of said first type, the metal gate work function being 100 millivolts (100 mV) or more from the band edge of said surface semiconductor layer, said lower threshold voltage (V connecting FETs together, metal gate FETs being connected to semiconductor gate FETs.