Patent ID: 6324664
Filing Date: 2001-11-27
Classification: G01R

Abstract:
A test circuit comprising:a scan path including dynamic logic elements clocked by a continuous system clock signal to maintain data states;an index counter clocked by the system clock for providing an index output for tracking data in said scan path;a control circuit clocked by a test clock signal for receiving scan input data from an external source and for providing scan output data to the external source, said test clock signal being discontinuous or asynchronous relative to said system clock signal;an input memory for receiving scan input data from said control circuit; anda selection circuit controlled by said control circuit and having a first input for receiving the output of said scan path, a second input for receiving scan input data from said input memory, and an output connected to the input of said scan path, the selection circuit controlled by said control circuit to select said first input or said second input to provide the output of the scan path or the scan input data as said input to said scan path.