Patent ID: 7847408
Filing Date: 2010-12-07
Classification: G06F,H01L

Abstract:
1. A semiconductor device comprising: a semiconductor layer; and a plurality of metal layers; wherein a top metal layer and a top-1 metal layer are arranged as a full-dense-mesh distribution network, the top metal layer comprises an integrated clock and power distribution network, the top-1 metal layer comprises a low impedance underpass corresponding to the integrated clock and power distribution network, the integrated clock and power distribution network includes a clock distribution network routed in a cut-out of a power distribution network on the top metal layer, and the low impedance underpass on the top-1 metal layer is arranged such that the clock distribution network is coupled approximately 50% to the power distribution network on the top metal layer and is coupled approximately 50% to a ground potential on the top-1 metal layer.