Patent ID: 8114729
Filing Date: 2012-02-14
Classification: G11C,H01L,Y10S

Abstract:
1. A method of fabricating a CMOS integrated circuit having NMOS and PMOS transistors with polysilicon gates coupled by polysilicon lines in both memory cell and non-memory cell areas, the method comprising: forming a layer of polysilicon gate material over a semiconductor surface of a substrate; implanting n-type dopant in a pre-gate patterning implant into the layer of polysilicon material in NMOS transistor gate regions of non-memory cell areas, while masking the layer of polysilicon material in PMOS transistor gate regions of non-memory cell areas and in NMOS and PMOS transistor gate regions of memory cell areas against implantation; following the pre-gate patterning implant, patterning the layer of polysilicon material to form polysilicon gate electrodes and polysilicon lines connecting polysilicon gate electrodes in the NMOS and PMOS transistor gate regions in both the memory cell and non-memory cell areas; and following the patterning the layer of polysilicon material, implanting n-type dopant into source/drain areas of the semiconductor surface adjacent sides of the polysilicon gate electrodes in the NMOS transistor regions, and implanting p-type dopant into source/drain areas of the semiconductor surface adjacent sides of the polysilicon gate electrode in the PMOS transitor regions.