Patent ID: 6025744
Filing Date: 2000-02-15
Classification: H03K

Abstract:
A glitch free delay line system comprising:a clock signal;a variable delay line comprising a plurality of sequentially coupled delay units, wherein the delay line comprises M output nodes and each of the M output nodes reproduces the clock signal with a varying amount of delay;a select mechanism for choosing a predetermined amount of delay n, and for generating a selection signal in response thereto;an M-to-N multiplexor having:M inputs for receiving each of the delayed clock signals from the M output nodes,a select input for receiving the selection signal from the select mechanism, andN output lines, wherein 3<N<M, and wherein three of the N output lines provide clock signals having delays of n, n-1, and n+1; andan N-to-1 multiplexor having:N inputs coupled to the N output lines of the M-to-N multiplexor,a select input for receiving the selection signal from the select mechanism, andan output line, wherein the output line outputs the clock signal with n delay.