Patent ID: 6649466
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method of forming DRAM circuitry comprising:forming a word line transistor over a semiconductive substrate, the word line transistor having a pair of source/drain regions; forming a capacitor storage node in electrical connection with one of the source/drain regions; forming a capacitor dielectric layer over the storage node, the capacitor dielectric layer comprising substantially amorphous Ta2O5, forming a capacitor cell electrode layer over the capacitor dielectric layer; etching through the capacitor cell electrode layer and the capacitor dielectric layer over the other source/drain region; and after the etching, exposing exposed portions of the capacitor dielectric layer to WE6 under conditions effective to etch the substantially amorphous Ta2O5 to recess the capacitor dielectric layer relative to an overlying layer.