Patent ID: 6396747
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A semiconductor memory device capable of inputting/outputting a plurality of data signals transmitted as a data train in time series by an external data bus in each of one read access operation and one write access operation, comprising:a memory cell array including a plurality of memory cells arranged in a matrix; a control circuit for generating a control command to carry out a read operation and a write operation with respect to said memory cell array; a row selecting circuit and a column selecting circuit for selecting a plurality of memory cells of interest in said one read access operation and said one write access operation; a write data retaining circuit for temporarily retaining said plurality of data signals transmitted from said external data bus, and then transmitting the data signals to said memory cell array in said write operation; a read data retaining circuit for temporarily retaining said plurality of data signals output from said memory cell array to sequentially transmit the data signals to said external data bus in said read operation; and an input/output selecting circuit responsive to said control command for transferring said plurality of data signals between each of the selected memory cells and said write and read data retaining circuits, wherein said control circuit generates a burst length set signal to define a burst length representing the number of said data train as a first number, said semiconductor memory device further comprising: an address input terminal receiving each bit of row address signal and column address signal to designate said memory cells of interest; and an internal column address generation circuit responsive to said column address signal and said burst length set signal to generate internal column address signals to select columns of said memory cells of said first number corresponding to said memory cells of interest respectively; wherein said column selecting circuit renders said columns of memory cells of the first number active according to said internal column address signals, wherein said read data retaining circuit comprises: read data latch circuits of said first number for storing each of said data signals of the first number, read switch circuits of said first number provided between said external data bus and respective read data latch circuits of said first number, and a count circuit sequentially turning on one of said read switch circuits of the first number.