Patent ID: 6566851
Filing Date: 2003-05-20
Classification: G05F

Abstract:
In a MOS integrated circuit, a current mirror circuit comprising:a high-speed current mirror section having a first connection for a first voltage source, a second connection for a second voltage source, an input to accept a reference current, and an output for supplying a load current and a load voltage to a load connected to the second voltage source; and a correction section having an input connected to the high-speed mirror section output to receive the load voltage and an output connected to the high-speed mirror input to supply the reference current; wherein the high-speed current mirror section includes: a first current mirror transistor pair having a first field effect transistor (FET) and a second FET with the first and second FET sources connected to the first voltage source and the second FET drain connected to the high-speed mirror section output to supply the load current and load voltage; and a second current mirror transistor pair having a third and fourth FET with the third and fourth FET sources connected to the second voltage source, the third FET having a drain connected to the drain of the first FET, and the fourth FET drain connected to accept the reference current.