Patent ID: 6759704
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having cell pads formed thereon, the cell pads being separated from each other by insulation material; bit lines disposed on the substrate; a bit line protection layer disposed on an entire surface of the semiconductor device including the bit lines and the substrate, the bit line protection layer having a thickness so that the bit lines are not buried; a first interlevel dielectric (ILD) layer disposed on the bit line protection layer, the first ILD layer having a thickness such that areas between the bit lines are buried and the bit line protection layer on top surfaces of the bit lines is exposed; a second interlevel dielectric (ILD) layer disposed on the first ILD layer and the exposed bit line protection layer; storage node contact holes disposed in between the bit lines through the second and first ILD layers and the bit line protection layer to the cell pads, a lower width of the storage node contact holes through the first ILD layer being greater than an upper width of the storage node contact holes through the second ILD layer; and a conductive material buried within the storage node contact holes.