Patent ID: 8902637
Filing Date: 2014-12-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first bit line and a second bit line; a first word line and a second word line; a first memory cell and a second memory cell; an inverting amplifier circuit configured to supply an inverted and amplified potential of the second bit line to the first bit line or an inverted and amplified potential of the first bit line to the second bit line; a first switch provided between the first bit line and a first input terminal of the inverting amplifier circuit; and a second switch provided between the second bit line and a second input terminal of the inverting amplifier circuit, wherein each of the first memory cell and the second memory cell comprises a writing transistor, a reading transistor, and a capacitor comprising a first electrode and a second electrode, wherein one of a source and a drain of the writing transistor of the first memory cell, a gate of the reading transistor of the first memory cell, and the first electrode of the capacitor of the first memory cell are connected to each other, wherein one of a source and a drain of the writing transistor of the second memory cell, a gate of the reading transistor of the second memory cell, and the first electrode of the capacitor of the second memory cell are connected to each other, wherein the other of the source and the drain of the writing transistor of the first memory cell is connected to the first bit line, wherein the other of the source and the drain of the writing transistor of the second memory cell is connected to the second bit line, wherein a gate of the writing transistor of the first memory cell is connected to the second word line, wherein a gate of the writing transistor of the second memory cell is connected to the first word line, wherein one of a source and a drain of the reading transistor of the first memory cell is connected to the second bit line, wherein one of a source and a drain of the reading transistor of the second memory cell is connected to the first bit line, wherein the second electrode of the capacitor of the first memory cell is connected to the first word line, and wherein the second electrode of the capacitor of the second memory cell is connected to the second word line.