Patent ID: 9134582
Filing Date: 2015-09-15
Classification: G02F

Abstract:
1. An array substrate, comprising a plurality of array substrate units, each of which comprising: gate lines and data lines extending along a first direction and a second direction crossing with each other, respectively, in a plane of a substrate, wherein, each array substrate unit comprises four array substrate sub-units which are arranged in the first direction and the second direction to form sub-unit rows and sub-unit columns, and each of sub-unit rows and sub-unit columns has two array substrate sub-units, each array substrate sub-unit comprises three pixels, and one data line and three gate lines which are electrically connected to the three pixels, the three gate lines comprising a first gate line, a second gate line and a third gate line; and the three gate lines are shared by two array substrate sub-units in each sub-unit row, and the one data line and one of the gate lines are shared by two array substrate sub-units in each sub-unit column, and wherein, within each array substrate sub-unit, the first gate line, the three pixels, the second gate line and the third gate line are arranged sequentially in the second direction; within each array substrate unit, the first sub-unit row and the second sub-unit row are arranged sequentially in the second direction, the third gate line for the first sub-unit row and the first gate line for the second sub-unit row are the same gate line.