Patent ID: 7719339
Filing Date: 2010-05-18
Classification: H03G,H03M

Abstract:
1. A voltage limiting circuit (VL) for limiting a signal voltage upstream of a processing stage (A) of a signal processing device, where, in the case of the value of an input signal (Vin) of the voltage limiting circuit (VL) being less than that of a predetermined maximum voltage (Vmax), an output signal (Vin′) of the voltage limiting circuit (VL) is substantially proportional to the input signal (Vin), and where in an overvoltage case in which the value of the input signal (Vin) exceeds that of the predetermined maximum voltage (Vmax), the output signal (Vin′) is substantially constant, the voltage limiting circuit (VL) comprising: (a) a voltage divider (R (b) the voltage divider (R (c) a differential amplifier (OPAMP