Patent ID: 6249163
Filing Date: 2001-06-19
Classification: H03K

Abstract:
A transparent latch having a signal input (D), an operating mode control signal (C) and an output (Q), the latch comprising four logic gates in which: the control signal (C) and the output from a first gate (6) are connected to the inputs of a second gate (5);the signal input (D) and output from the second gate (5) are connected to the inputs of the first gate;the control signal (C) and the output from a third gate (8) are connected to the inputs of a fourth gate (7);the output of the first gate (6) and the output of the fourth gate (7) are connected to the inputs of the third gate (8),wherein the output (Q) of the latch is taken from the output of the third gate (8) whereby in a first operating mode, dependent upon the logic state of the control signal (C), the logic state of the signal input (D) propagates through to the output Q, and in a second operating mode, dependent upon the logic state of the control signal (C) any logic level change in the signal input (D) is blocked from reaching the output (Q).