Patent ID: 6583030
Filing Date: 2003-06-24
Classification: H01L

Abstract:
A method for producing an integrated circuit wherein a first substrate is first provided with a circuit structure (1) and a first metalization structure (2,3) disposed over a first side thereof and including one or more layers with plated holes extending therethrough and into the circuit structure (1), the plated holes (4) being insulated against the circuit structure (1) and provided with metalized connections (5), a planarizing layer (7) being disposed over the first metalization structure (2,3), the first substrate being rebonded to a handling wafer (8), a second side opposite the first side of the first substrate being thinned so that the plated holes (4) are open and metalized connections (5) are exposed,comprising producing a second metalization structure (10, 11) connected with the first metalization structure (2, 3) and/or the circuit structure (1) by means of the metalized connections (5) on the second side of the circuit structure (1).