Patent ID: 7814299
Filing Date: 2010-10-12
Classification: G06F

Abstract:
1. A computer configured to have a first thread and a second thread, comprising: a register file for storing operands, the register file having a first thread portion to store operands for the first thread and a second thread portion to store operands for the second thread; an execution unit for executing instructions, the execution unit configured to receive a source operand from the register file and write a result back into the register file; a first target address history table for storing a target register address suitable for addressing a register in the first thread portion in the register file and a second target history table for storing a second target register address suitable for addressing a register in the second thread portion in the register file; the execution unit configured to execute a first instruction that writes an output into a selected register within the register file, the selected register being in the first thread portion or the second thread portion depending on whether the instruction is from the first thread or the second thread, and is further configured to write the target register address of the selected register within the register file into the first target address history table or the second target address history table; and the execution unit further configured to execute a second instruction that contains a target address history index into the first target address history table or the second target address history table depending on if the second instruction is from the first thread or the second thread, wherein the index retrieves the selected register address from the first target address history table or the second target address history table, the selected register address then being used to retrieve, from the register file, a source operand needed by the second instruction.