Patent ID: 7773712
Filing Date: 2010-08-10
Classification: G06F,H03K,Y02D

Abstract:
1. A clock switching circuit, in which one clock signal is selected from 2 N -phase input clock signals with the same frequency but with each shifted in phase (where N is an integer equal to or greater than 3), based on an N-bit selection signal, and is output as an output clock signal, the clock switching circuit comprising: a selector group having 2 an operation control circuit which generates 2 wherein said selector group comprises: a first layer, having first to 2 a second layer, having 2 3rd to Nth layers (where in this case N is equal to or greater than 4), in which said Nth layer has the 2 and wherein a first selection signal is supplied to said first layer selectors using positive logic or negative logic, a second selection signal is supplied to said second layer selectors using positive logic or negative logic, third to N−1th selection signals are similarly supplied to the third to N−1th layer selectors using positive logic or negative logic, and an Nth selection signal is supplied to the selector of said Nth layer, and said operation control circuit, according to the state of said N-bit selection signal, generates said operation control signals to set a portion of said 2