Patent ID: 6826180
Filing Date: 2004-11-30
Classification: H04L

Abstract:
Circuitry for processing a first communication packet and a second communication packet, the circuitry comprising:a look-up engine configured, for the first communication packet, to transfer a first selector to a content-addressable memory and receive a corresponding first result from the content-addressable memory, retrieve a first context structure based on the first result, build a summation block using the first context structure, transfer the summation block, receive an installation instruction for the summation block, write a second selector to the content-addressable memory and receive a corresponding second result from the content-addressable memory, write the summation block to a memory location corresponding to the second result, and wherein the look-up engine is configured, for the second communication packet, to transfer the second selector to the content-addressable memory and receive the corresponding second result from the content-addressable memory, retrieve the summation block based on the second result, and transfer the summation block; and a processor configured, for the first communication packet, to receive and process the summation block to control handling of the first communication packet and generate and transfer the installation instruction to the look-up engine, and wherein the processor is configured, for the second communication packet, to receive and process the summation block to control handling of the second communication packet.