Patent ID: 6999340
Filing Date: 2006-02-14
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines formed along a first direction; a plurality of bit lines formed along a second direction crossing at right angles to the first direction; a first memory cell including a magneto-resistive element which has either a first resistance or a second resistance smaller than the first resistance; a second memory cell including a magneto-resistive element which has a resistance between the first and second resistances; a memory cell array including the first and second memory cells disposed at intersections of a word line and bit lines; a row decoder which selects the word line; a row driver including a first current source configured to supply a first write current to the word line selected by the row decoder and a second current source configured to supply a second write current to the word line selected by the row decoder, an absolute value of the second write current being smaller than that of the first write current, the first current source supplying the first write current to the word line such that the magneto-resistive element of the first memory cell has either the first or second resistance to perform a write operation, and the second current source supplying the second write current to the word line such that the magneto-resistive element of the second memory cell has a resistance between the first and second resistances; a column decoder which selects a bit line; a column driver which supplies a third write current to the bit line selected by the column decoder; and a sense amplifier which amplifies data read from the first memory cell selected by the row decoder and column decoder.