Patent ID: 8166213
Filing Date: 2012-04-24
Classification: G06F

Abstract:
1. A controller comprising: an interface having limited addressing capabilities; a buffer memory coupled with said interface, wherein the buffer memory has an address range that cannot be directly addressed by said interface; a first set of registers comprising a first address register coupled with address lines of said buffer memory and configured to address the buffer memory; a second set of registers independent from the first set of registers comprising a second address register coupled with address lines of said buffer memory and configured to address the buffer memory; and a control unit for decoding and executing buffer memory access commands received by the interface, the control unit being configured to access the buffer memory through either said first or second address register of said first or second set of registers, wherein an address stored in said first or second address register is applied to address lines of said buffer memory and wherein associated data is read or written from or to said buffer memory.