Patent ID: 7376875
Filing Date: 2008-05-20
Classification: G01R

Abstract:
1. A method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST), the chip having a plurality of latches for holding data for a plurality of logical cones, the latches being arranged in a plurality of scan chains, the method comprising the steps of: running the LBIST on one scan chain to determine if a first latch fails the LBIST; identifying, if a first latch fails the LBIST, the first latch to isolate a first limiting cone; masking out the data from the first latch by using a counter, a comparator and a storage device, the counter for keeping a running number of times data is shifted out of the scan chain, the storage device for holding a number representing the location of the first latch in the scan chain and the comparator for comparing the number from the counter to the number in the storage device and using a data of a known value instead of the data from the first latch when the number from the storage device is equal to the number from the counter; running the LBIST again on the one scan chain to determine if a second latch fails the LBIST; and identifying, if a second latch fails the LBIST, the second latch to isolate a second limiting cone.