Patent ID: 7102863
Filing Date: 2006-09-05
Classification: H01L

Abstract:
1. An electrostatic breakdown preventing circuit, comprising: an input terminal for receiving an input signal; a first power conductive line connected to a first potential source; a second power conductive line connected to a second potential source; an internal circuit connected between the first and second power conductive lines, the internal circuit operating in response to the input signal; a diode connected between the input terminal and the second power conductive line; a power clamp transistor connected between the first and second power conductive lines, the power clamp transistor having a gate connected to a node, the power clamp transistor electrically connecting the first and second power conductive lines during an ON state; a first capacitor connected between the node and the first power conductive line; and a second capacitor connected between the node and the second power conductive line, wherein the capacitances of the first and second capacitors are set in such a manner that the transistor is brought to an OFF state upon a normal operation and brought to the ON state upon the input of an electrostatic surge.