Patent ID: 8732626
Filing Date: 2014-05-20
Classification: G06F

Abstract:
1. A circuit layout method for forming two masks using double patterning technology, said method comprising: receiving layout data representing a first set of patterns in a first cell, each pattern of the first set of patterns having a plurality of runs, ends, and corners, said first set of patterns separately assigned to a first mask and a second mask and said first cell having no critical G0-space; receiving layout data representing a second set of patterns in a second cell, each pattern of the second set of patterns having a plurality of runs, ends, and corners, said second set of patterns separately assigned to the first mask and the second mask, and said second cell having no critical G0-space, and wherein the cell and the first second cell having a shared edge; for each second cell where a near edge pattern of the first cell and a near edge pattern of the second cell are both assigned to either the first mask or the second mask, re-assigning the first mask patterns to the second mask and re-assigning the second mask patterns to the first mask; adjusting cell edge spacings, using a computer, at the shared edge in the first and second cell according to a minimum spacing rule and a G1-rule, wherein the G1-rule is a distance between a next edge pattern of the first cell and the shared edge or between the next edge pattern of the first cell and the near edge pattern of the second cell, and the next edge pattern of the first cell is different from the near edge pattern of the first cell; and, outputting a representation of layout data representing the first cell and the second cell having adjusted cell edge spacings to an output device.