Patent ID: 7735045
Filing Date: 2010-06-08
Classification: G06F

Abstract:
1. A method of processing flip-flop logic in a circuit design for implementation in an integrated circuit, comprising: identifying a chain of flip-flops in the circuit design, the chain of flip-flops including first and second control signals; instantiating, in a logical description of the circuit design, a shift register for the chain of flip-flops; instantiating, in the logical description, first and second control chains of flip-flops for the first and second control signals, respectively; and instantiating, in the logical description, a multiplexer configured to select among an output of the shift register, an asserted logic state, and a de-asserted logic state based on outputs of the first and second control chains, wherein the instantiating a shift register, the instantiating first and second control chains, and the instantiating the multiplexer are performed by a computer, wherein the shift register includes a data input, a data output, and an address input, and wherein the instantiating the shift register comprises: