Patent ID: 6549448
Filing Date: 2003-04-15
Classification: G11C

Abstract:
A FeRAM device having a first memory cell and a second memory cell sharing a cell plate, wherein the first memory cell and the second memory cell are commonly coupled to a bit line, and wherein the first memory cell is driven by a first word line and the second memory cell is driven by a second word line, the first memory cell comprising:a first ferroelectric capacitor having a first electrode connected to the cell plate, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode; a first transistor having a first gate electrode connected to the first word line, a first source and a first drain, wherein the first source and the first drain of the first transistor are respectively connected to the bit line and the second electrode of the first ferroelectric capacitor; and a second transistor having a second gate electrode connected to the second word line, a second source and a second drain, wherein the second source and the second drain of the second transistor are respectively connected to the second electrode of the first ferroelectric capacitor and the cell plate.