Patent ID: 6333646
Filing Date: 2001-12-25
Classification: G01R,G06F,H03K

Abstract:
An abnormal clock detector which receives a first clock signal and a second clock signal and detects an abnormality in the frequency of any of the first clock signal or the second clock signal, said abnormal clock detector comprising:a first frequency divider circuit which divides the frequency of the first clock signal to output a first frequency division clock signal;a second frequency divider circuit which divides the frequency of the first clock signal to output a first reset signal;a third frequency divider circuit which divides the frequency of the second clock signal to output a second frequency division clock signal;a fourth frequency divider circuit which divides the frequency of the second clock signal to output a second reset signal;a first clock comparison circuit which receives the first frequency division clock signal and the second reset signal, counts the number of pulses of the first frequency division clock signal based on a state of the second reset signal, and outputs a first error signal indicative of abnormal clock when the counted number of pulses exceeds a predetermined value; anda second clock comparison circuit which receives the second frequency division clock signal and the first reset signal, counts the number of pulses of the second frequency division clock signal based on a state of the first reset signal, and outputs a second error signal indicative of abnormal clock when the counted number of pulses exceeds a predetermined value, whereineach of said first clock comparison circuit and said second clock comparison circuit comprises,an inverter gate inverting a state of the first reset signal or the second reset signal;a first shift resister comprising at least two stage flip-flops which receives the first frequency division clock signal or the second frequency division clock signal as a clock input, receives the first reset signal or the second reset signal as a reset input, and outputs a first output signal;a second shift register which receives the first frequency division clock signal or the second frequency division clock signal as a clock input, receives the first reset signal or the second reset signal inverted by said inverter gate as a reset input, and outputs a second output signal; andan OR gate for carrying out logical OR calculation of the first output signal and the second output signal to output the first error signal or the second error signal.