Patent ID: 6580648
Filing Date: 2003-06-17
Classification: G11C

Abstract:
A memory circuit having a plurality of complementary bitlines, providing bitline pairs, each bitline pair holding a logic state, a corresponding plurality of sense amplifiers for evaluating the corresponding logic state of each said bitline pair, each sense amplifier having an output, and a corresponding plurality of data latches for storing data to be written to said bitline pairs, wherein each data latch has an input and output, the circuit further comprising a respective multiplexer connected to each data latch input, a first input of said multiplexer being responsive to the output of a respective other of said plurality of data latches, and a second input of said multiplexer receiving said data to be written said multiplexer selectively having a first and second state whereby in said first state of said multiplexer said data latches are connected to form a test register.