Patent ID: 6900746
Filing Date: 2005-05-31
Classification: H03M

Abstract:
1. A concatenator adapted to receive and process datum segments of varying bit lengths, comprising: an input register having a predetermined bit length and having defined therein an initial input register address; means for receiving within said input register one or more datum segments that may have varying bit lengths; means for determining the full bit length of one or more received datum segments; an output register having a predetermined bit length and having defined therein an initial output register address; transfer means for transferring a first datum segment from said input register to said initial output register address as a first step of a concatenation series; address calculation means for calculating respective addresses for one or more datum segments other than said first datum segment; concatenation means for transferring, as further steps of a concatenation series, one or more additional datum segments from said input register into locations within said output register that are in immediate juxtaposition with respective datum segments just previously transferred thereto; means for determining whether or not a received datum segment can be fit within said predetermined bit length of said output register at locations not occupied by any prior transferred datum segments; and concatenation initiation means for initiating a new concatenation series upon one of said additional datum segments exceeding in length an amount of said predetermined length of said output register not occupied by one or more prior transferred datum segments; whereby said output register can be filled to near said predetermined bit length by concatenating together a series of datum segments.