Patent ID: 6434684
Filing Date: 2002-08-13
Classification: G06F,H04L

Abstract:
A system for coupling data from a first circuit operating in one clock domain defined by a first clock signal to a second circuit operating in a second clock domain defined by a second clock signal, the system comprising:a phase comparator receiving signals indicative of a relative phase of the first and second clock signals, the phase comparator generating a phase signal indicative of whether or not the first clock signal leads the second clock signal; and a state machine receiving the first clock signal and a start signal signifying the start of coupling the data from the first circuit to the second circuit, the state machine generating an output clock signal synchronized to the first clock signal to clock the data out of the first circuit, the state machine being responsive to the phase signal to adjust a time period from the start signal to when the output clock signal is generated so that the time period is longer when the first clock signal leads the second clock signal than when the first clock signal does not lead the second clock signal, the state machine comprising: a series of sequentially coupled latches that are clocked by the first clock signal, a first latch in the series being coupled to receive the start signal, and a final latch in the series outputting an enable signal responsive to the start signal being clocked through the series of latches; a bypass circuit coupled to receive the phase signal, the bypass circuit being coupled between an input terminal and an output terminal of one of the latches, the bypass circuit bypassing the latch responsive to an absence of a phase signal indicative of the first clock signal leading the second clock signal; and a logic circuit coupled to receive the first clock signal and the enable signal, the logic circuit having an output terminal on which the output clock signal is generated, the enable signal causing the logic circuit to couple the first clock signal to the output terminal so that the output clock signal is generated responsive to the enable signal.