Patent ID: 6229372
Filing Date: 2001-05-08
Classification: H03K

Abstract:
A clamping circuit comprising:(a) an input terminal for receiving an input voltage;(b) an upper power supply terminal for connection to at least one upper supply voltage;(c) a lower power supply terminal for connection to at least one lower supply voltage, the at least one lower supply voltage being less than the at least one upper supply voltage;(d) a first clamping MOS field effect transistor having a control lead, the first clamping transistor being serially connected between the upper power supply terminal and the input terminal;(e) a second clamping MOS field effect transistor having a control lead, the second clamping MOS field effect transistor being serially connected between the lower power supply terminal and the input terminal;(f) a reference circuit coupled to the control leads of the first and second clamping MOS field effect transistors for maintaining first and second reference voltages at the control leads of the first and second clamping MOS field effect transistors, respectively, the first reference voltage being less than the second reference voltage; and(g) at least one staging circuit coupled to the control lead of at least one of the first and second clamping MOS field effect transistors to determine a selected reference voltage at the control lead to which the at least one staging circuit is coupled.