Patent ID: 7417321
Filing Date: 2008-08-26
Classification: H01L

Abstract:
1. A via structure for interconnection in a semiconductor product, comprising: a bottom metal layer, representing a connection layer in the semiconductor product; an isolation layer on the bottom metal layer, the isolation layer comprising a via hole exposing a portion of the bottom metal layer, the via hole comprising a sidewall and a bottom; a first barrier metal layer on the sidewall of the via hole and not on the center of the bottom of the via hole; a metal under-layer on the center of the bottom of the via hole and on the first barrier metal layer, wherein the metal under-layer comprises α-phase Ta, W of ( a second barrier metal layer on the metal under-layer; and a metal fill layer within the via hole; wherein a lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.