Patent ID: 8089572
Filing Date: 2012-01-03
Classification: G02F,H01L

Abstract:
1. A pixel structure, comprising: a first scan line; a second scan line, an extending direction of the first scan line being parallel to an extending direction of the second scan line; a data line intersected with the first scan line and the second scan line to define a pixel region; a thin film transistor located inside the pixel region, and the thin film transistor having a gate, a source and a drain, wherein the gate is connected to the first scan line, the source is connected to the data line, and the drain overlaps the gate in an overlapping region in an out-plane direction to form a gate-drain parasitic capacitance; a pixel electrode located in the pixel region and the pixel electrode electrically connected to the drain; and a capacitance compensation portion electrically connected to the pixel electrode and the capacitance compensation portion keeping a gap from the first scan line or the second scan line in an in-plane direction to induce a compensation capacitance, wherein the drain and the capacitance compensation portion are configured that: when the overlapping region is reduced to decrease the gate-drain parasitic capacitance, the gap is reduced correspondingly to increase the compensation capacitance, and when the overlapping region is enlarged to increase the gate-drain parasitic capacitance, the gap is enlarged correspondingly to decrease the compensation capacitance.