Patent ID: 7933141
Filing Date: 2011-04-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell; a local bit line connected to the memory cell; a local sense amplifier including a field effect transistor, which is connected to the local bit line with a first input/output terminal, wherein the local sense amplifier writes data into the memory cell and amplifies data of the memory cell, and the field effect transistor which is used for reading; a global bit line which is connected to the local sense amplifier with a second input/output terminal; a global sense amplifier which is connected to the global bit line, wherein the global sense amplifier writes data into the memory cell via the second input/output terminal and amplifies data of the memory cell; a threshold monitor circuit for monitoring a threshold voltage of the field effect transistor and temperature-dependent variations of the threshold voltage; and a generation circuit for generating a write voltage for the memory cell based on a monitoring result of the threshold voltage, wherein the global sense amplifier applies the write voltage to the memory cell based on write data of the memory cell while applying a read voltage to the memory cell based on output voltage of the local sense amplifier wherein the global sense amplifier reads information of the memory cell based on the output voltage of the local sense amplifier, and then the global sense amplifier applies the write voltage to the memory cell based on the information of the memory cell that the local sense amplifier shows.