Patent ID: 7696801
Filing Date: 2010-04-13
Classification: H03K

Abstract:
1. A method for resetting a clock triggering digital circuit, comprising: providing a clock signal for triggering the clock triggering digital circuit to the clock triggering digital circuit, wherein the clock signal transits between a first logic level and a second logic level; generating a reset signal to the clock triggering digital circuit; before an edge of the reset signal occurs, stopping the transition between the first logic level and the second logic level of the clock signal to keep the clock signal at the first logic level for the first predetermined time period according to a first indicating signal; and after a second predetermined time period since a second indicating signal occurs, recovering the transition between the first logic level and the second logic level of the clock signal which is stopped due to the first indicating signal; wherein the timing between the first and the second indication signals are determined by a counting value.