Patent ID: 8053281
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method of forming a microelectronic package at a wafer level comprising the steps of: (a) providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon; (b) providing an interposer component having a compliant dielectric layer of B-stage polymer and a conductive layer directly adjacent to the B-stage polymer; (c) forming a pattern of holes corresponding to said pattern of electrical contacts through said compliant dielectric layer and said conductive layer; and then (d) contacting said compliant dielectric layer with said semiconductor wafer surface so that said pattern of holes is in an aligned position with said pattern of contacts; (e) bonding said compliant dielectric layer and said semiconductor wafer surface in said aligned position to unite said semiconductor wafer and said interposer component to form a wafer level semiconductor package; and (f) dicing said wafer level semiconductor package to create individual semiconductor chip packages, said dicing including severing said semiconductor wafer into a plurality of chips.