Patent ID: 6925004
Filing Date: 2005-08-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell which stores a plurality of data with an n-valued threshold voltage (n is a natural number equal to or larger than 1); a first data storage circuit which stores at least a first-logic-level or a second-logic-level data read from the memory cell; a second data storage circuit which is connected to a data line and stores at least the first- or second-logic-level data supplied from the data line; a third data storage circuit which stores at least the data read from the memory cell or the first- or second-logic-level data supplied from the first data storage circuit; and a control circuit which manipulates the data in the first, second and third data storage circuits in such a manner that the control circuit does not change the threshold voltage of the memory cell when the logic level of the first data storage circuit is at the second logic level, carries out a first write operation to raise the threshold voltage of the memory cell when the logic level of the first data storage circuit is at the first logic level and the logic level of the third data storage circuit is at the first logic level, and carries out a second write operation to raise the threshold voltage of the memory cell when the logic level of the third data storage circuit is at the second logic level, which, in a first verify operation, does not precharge the memory cell when the logic level of the second data storage circuit is at the first logic level and precharges the memory cell when the logic level of the second data storage circuit is at the second logic level, which sets the logic level of the third data storage circuit to the second logic level when the threshold voltage of the memory cell has exceeded a first verify voltage, does not change the logic level of the third data storage circuit when the threshold voltage of the memory cell has not exceeded the first verify voltage, sets the logic level of the first data storage circuit to the second logic level when the threshold voltage of the memory cell has exceeded a second verify voltage higher than the first verify voltage, and does not change the logic level of the first data storage circuit when the threshold voltage of the memory cell has not exceeded the second verify voltage, which, in a second verify operation, does not precharge the memory cell when the logic level of the third data storage circuit is at the first logic level and precharges the memory cell when the logic level of the second data storage circuit is at the second logic level, which sets the logic level of the first data storage circuit to the second logic level when the threshold voltage of the memory cell has exceeded a third verify voltage higher than the second verify voltage, and does not change the logic level of the first data storage circuit when the threshold voltage of the memory cell has not exceeded the third verify voltage, and which, in a third verify operation, sets the logic level of the first data storage circuit to the second logic level when the threshold voltage of the memory cell has exceeded a fourth verify voltage higher than the third verify voltage, does not change the logic level of the first data storage circuit when the threshold voltage of the memory cell has not exceeded the fourth verify voltage, and repeats the first and second write operations and verify operations until the logic level of the first data storage circuit reaches the second logic level.