Patent ID: 8199157
Filing Date: 2012-06-12
Classification: G06T

Abstract:
1. A system on chip (SoC) comprising: a system bus; a plurality of sub-systems respectively connected to the system bus; an image processing logic block connected to the system bus, the image processing logic block being configured to perform an image processing, the image processing logic block being included in a first power domain; an image memory interface having a first connection to the system bus and a second connection to the system bus via the image processing logic block; an image processing memory block connected to the image memory interface, wherein access to the image processing memory block via the first connection or the second connection is controlled by the image memory interface, the image processing memory block being configured to be used for the image processing, the image memory interface and the image processing memory block being included in a second power domain different from the first power domain; and a control unit configured to receive operation state information of the image processing logic block from the image memory interface for controlling a power supply unit configured to supply power to the first power domain and the second power domain.