Patent ID: 6275920
Filing Date: 2001-08-14
Classification: G06F,G06T

Abstract:
An apparatus for processing data, comprising:at least one processing element for processing data in response to processing element command words, wherein each of said at least one processing element includes a random access memory (RAM) having a plurality of storage locations, and wherein each storage location is capable of storing an n-bit data unit, n being an integer greater than zero; anda controller for generating processing element command words that are supplied to the at least one processing element and which cause the at least one processing element to manipulate an M-bit operand, M being evenly divisible by n,wherein:the controller utilizes an image descriptor that represents the M-bit operand to generate addresses for accessing the M-bits of the operand stored in the RAM; andthe image descriptor includes a map field comprising a plurality of address fields, each for addressing one of the storage locations in the RAM.