Patent ID: 8198633
Filing Date: 2012-06-12
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: forming a first gate electrode material on a gate dielectric material that is formed above a silicon-containing semiconductor layer, said first gate electrode material having a polycrystalline structure and comprising a plurality of first grains; forming a second gate electrode material on said first gate electrode material, said second gate electrode material having a polycrystalline structure and comprising a plurality of second grains, wherein a grain size of at least some of said plurality of second grains is smaller than a grain size of said plurality of first grains; forming a gate electrode from said first and second gate electrode materials; providing at least one strain-inducing mechanism for said transistor; and after providing said at least one strain-inducing mechanism, increasing said grain size of at least some of said plurality of second grains, wherein increasing said grain size comprises annealing said gate electrode.