Patent ID: 9196371
Filing Date: 2015-11-24
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array comprising a plurality of memory cells and having initial setting data stored in the plurality of memory cells; and a control circuit configured to apply a first voltage to gates of the plurality of memory cells to read the initial setting data and, depending on that read result, apply a second voltage different from the first voltage to the gates of the plurality of memory cells to read the initial setting data, the control circuit being operative to store the initial setting data and inverted data of the initial setting data in the plurality of memory cells, depending on whether or not the initial setting data that has been read has a value obtained by inverting the inverted data that has been read, the control circuit being operative to change a voltage applied to the gates of the plurality of memory cells to read the initial setting data, and depending on a read result of the initial setting data, the control circuit being operative to increase the voltage applied to the gates of the plurality of memory cells.