Patent ID: 6356636
Filing Date: 2002-03-12
Classification: G06F

Abstract:
A circuit for reducing a value of a result operand that is represented in modulo form, the circuit comprising:a first latch having an input for receiving a first data bit, the first latch being set when the first data bit has a first logic value; a first logic gate having a first input coupled to an output of the first latch, a second input for receiving a second data bit, and an output, the first logic gate performing a predetermined logic operation on the first and second data bits; a first adder having a first input for receiving the first data bit, a second input for receiving the output of the first logic gate, a carry input, and an output that represents a summed value of the first and second data bits when the first data bit has a first logic value and that represents a value of the first data bit when the first data bit has a second logic value; and a second latch having an input coupled to a carry output of the first adder and an output coupled to the carry input of the first adder.