Patent ID: 6547353
Filing Date: 2003-04-15
Classification: B41J

Abstract:
A thermal ink jet printhead system comprising:a base member having a plurality of ink flow channels that are connected to an ink reservoir and terminate in a nozzle through which ink is expelled in which the base member is part of a thermal ink jet printhead; a plurality of heating elements, each ink flow channel having a corresponding one of said heating elements connected thereto; a monolithically integrated multiple output driver circuit formed as a semiconductor integrated circuit and connected to the thermal ink jet printhead, said multiple output driver circuit further comprising: a plurality power output transistors Q1, Q2 . . . QX and gate driver circuits each formed as a push/pull transistor driver circuit, each power output transistor Q1, Q2 . . . QX connected to a corresponding one of a push/pull transistor driver circuit, wherein a respective one power output transistor and push/pull transistor driver circuit are connected to a corresponding one heating element; a single closed loop reference circuit operatively connected in open loop configuration to each push/pull transistor driver circuit, said reference circuit including only one reference transistor and an associated push/pull transistor driver circuit having a gate, drain and source, and only one reference amplifier that receives as inputs a reference voltage from the reference transistor and a source of current, and having an amplifier output operatively connected to said push/pull transistor gate driver circuits of said respective power output transistors and to one of either the source or drain of said push/pull transistor driver circuit of said reference transistor, wherein said reference amplifier regulates the reference transistor directly and the power output transistors by matching; and a logic circuit and controller operatively connected to the gate driver circuits and power output transistors Q1, Q2 . . . QX to provide logic pulses for turning on and off each power MOS transistor Q1, Q2 . . . QX via an associated push/pull transistor driver circuit.