Patent ID: 6546019
Filing Date: 2003-04-08
Classification: H04L

Abstract:
A duplex memory control apparatus comprising:a first control unit and a second control unit connected to each other through a communication line; the first control unit comprising: a first bus; a first memory connected to the first bus; a central processing unit connected to the first bus and writing a write data in the first memory through the first bus; a transmitter connected to the first bus, obtaining the write data from the first bus and transmitting the write data to the second control unit or when the write data can be produced based on other write data previously obtained from the first bus in order to transmit to the second control unit, transmitting to the second control unit a specific data comprising information for producing the write data based on the other write data; a second bus; a first direct memory access unit connected with the second bus and reading the write data stored in the first memory through the first bus and the second bus; and an access limiter connected with the first bus and the second bus and limiting use of the first bus by the first direct memory access unit when the central processing unit uses the first bus; the second control unit comprising: a data producing section receiving the write data or the specific data from the transmitter, having the other write data, and producing the write data based on the specific data and the other write data when receiving the specific data; and a second memory storing the write data received or produced by the data producing section.