Patent ID: 8343845
Filing Date: 2013-01-01
Classification: H01G,H01L

Abstract:
1. A method of manufacturing a capacitor structure, comprising: forming a mold layer on a substrate; forming a plurality of sacrificial layer patterns in contact with a plurality of supports on the substrate, such that the plurality of sacrificial layer patterns have top surfaces substantially level with top surfaces of the supports and bottom surfaces substantially level with bottom surfaces of the supports, the sacrificial layer patterns and the supports being parallel to each other and being arranged in an alternating stripe pattern on the substrate; partially removing the sacrificial layer patterns, the supports, and the mold layer to form a plurality of holes therethrough exposing top surfaces of the substrate, the holes being arranged in a first direction to define a column, and a plurality of columns being arranged in a second direction perpendicular to the first direction to define a matrix; forming a plurality of lower electrodes in the holes on the exposed top surfaces of the substrate, such that the lower electrodes have planar top surfaces and the plurality of supports are on upper sidewalls of at least two adjacent lower electrodes; removing the sacrificial layer patterns; removing the mold layer to expose sidewalls of the lower electrodes; forming a dielectric layer on the lower electrodes and the supports; and forming an upper electrode on the dielectric layer.