Patent ID: 6348407
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A method of fabricating damascene comprising:providing a semiconductor substrate; providing patterned metal wiring embedded in an insulator over the semiconductor substrate; depositing a passivation layer over said patterned metal wiring; depositing a first low dielectric constant material layer upon said passivation layer; coating a silicon containing adhesion layer on the first low dielectric constant material layer; exposing said silicon containing adhesion layer to UV radiation; exposing said silicon containing adhesion layer to a silylation and oxygen plasma process; depositing a second low dielectric constant material layer upon said silicon containing adhesion layer; providing patterning and etching the second and first low dielectric constant material layers, the silicon containing adhesion layer, and the passivation layer to form trench/via openings extending to the patterned metal wiring; depositing a blanket layer of barrier metal over the semiconductor substrate and into the trench/via opening; depositing a blanket conducting copper seed layer over the barrier metal; depositing by electroplating or electroless plating conducting thick copper upon the copper seed layer.