Patent ID: 6168985
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device having data lines, word lines and memory cells each including a MISFET and a capacitor element, each memory cell being connected to one of the word lines and the data lines, comprising the steps of: (a) forming a gate electrode, a source region and a drain region for said MISFET, on a surface of a semiconductor substrate; (b) forming a first insulating film over said gate electrode; (c) performing a polishing of the surface of said first insulating film; (d) forming a second insulating film over said first insulating film; (e) forming grooves in said second insulating film; and (f) forming a conductive film in said grooves in order to form said data lines, one of said data lines being connnected to one of said source and drain regions of said MISFET.