Patent ID: 6723589
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method of manufacturing a load thin film transistor in a semiconductor device, comprising:forming a plurality of junction regions, a plurality of access transistors and a plurality of driver transistors in a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate including the plurality of access transistors and the plurality of driver transistors; etching regions of the interlayer insulating film to expose the plurality of junction regions and drains of the plurality of driver transistors; forming an amorphous silicon thin film on the top surface and etched portions of the interlayer insulating film, the exposed portions of the plurality of junction regions and the drains of the plurality of driver transistors; solid-phase crystallizing the amorphous silicon thin film by means of an annealing process to form a single crystal silicon thin film; forming a gate oxide film and a gate on the single crystal silicon thin film; and forming source/drain in the single crystal silicon thin film through an impurity ion implantation process using the gate as an ion implantation mask.