Patent ID: 6803286
Filing Date: 2004-10-12
Classification: H01L,Y10S

Abstract:
A method of forming a local interconnect comprising:forming a pair of translator gates having respective opposing sidewalls over a semiconductor substrate; depositing an insulating layer over the substrate and between the pair of transistor gates; etching a first contact opening into the insulating layer to proximate the substrate between the pair of transistor gates and another contact opening through the insulating layer to proximate the substrate proximate an opposing side of one of the pair of transistor gates; forming insulating sidewall spacers over the opposing sidewalls of the one transistor gate, the insulating layer being received between at least one of said sidewalls wherein the insulating layer is not received between the other sidewall and the other sidewall spacer; and one of said sidewall spacers; and forming a local interconnect layer to overlie the one transistor gate and electrically connect with semiconductor substrate material between the pair of transistor gates and semiconductor substrate material proximate the opposing side of the one transistor gate.