Patent ID: 6091352
Filing Date: 2000-07-18
Classification: H03M

Abstract:
An A/D conversion device for converting an analog input voltage into a digital output signal encoded in N bits OUT(0:N-1), in which each bit OUT(i), for i=0 to N-1, must successively assume active and inactive states when the value of the input voltages exceeds (2m+1) and (2m+2) times, respectively, a predetermined value Vi which is associated with said bit OUT(i), wherein m may vary between 0 and 2.sup.(N-1-i) -1, said device comprising:a resistance ladder arranged, in series, between two power supply terminals for generating a series of reference voltages;a series of comparators, each effecting a comparison between the input voltage and a reference voltage;a first decoder for generating, on the basis of the results of said comparisons, the K+1 least significant bits OUT(0:K) of the output signal;a second decoder for generating, on the basis of the results of said comparisons, signals which are representative of the transitions to which the N-K-1 most significant bits OUT(i+1) of the output signal are to be submitted, for i=K to N-2; andan encoder for producing each of said most significant bits OUT(i+1) of the output signal on the basis of the signals generated by the first and second decoders,characterized in that the second decoder comprises signaling means for generating, for each most significant bit OUT(i+1), two signals A(i+1) and P(i+1) referred to as antecedent and subsequent signals, respectively, said antecedent and subsequent signals having transitions framing each transition of the bit OUT(i+1), and in that the encoder comprises means for synchronizing each transition of the bit OUT(i+1), signaled by the antecedent and subsequent signals A(i+1) and P(i+1), with a transition of the bit OUT(i) of the next lower weight.