Patent ID: 6330636
Filing Date: 2001-12-11
Classification: G06F,G11C

Abstract:
A double data rate synchronous dynamic random access memory device having data, bi-directional data strobe and address bus inputs thereto, said device comprising:one or more memory arrays each having an associated sense amplifier, a designated row in a selected one or more of said memory arrays being accessed in accordance with address signals provided to one or more row decoders coupling each of said one or more memory arrays to said address bus;one or more column decoders, each of said column decoders being associated with one or more of said memory arrays and coupled to receive said address signals for accessing a designated column in said selected one of said one or more, memory arrays;a plurality of data latches for storing data to be written to said selected one or more of said memory arrays and said data to be read from said one or more of said caches;a data input and output buffer coupled to the bi-directional data strobe inputs and to the data latches; andone or more caches, each of said caches being interposed between one of said column decoders and one or more of said memory arrays and coupled to the data latches, whereby data buffering is performed as said data to be written to said device on said data input is directed to said selected ones of said memory arrays and data to be read from said device is read from said caches in accordance with said address signals on said address bus;wherein the data input and output buffer is synchronously operated for clocking data on the data inputs on a rising edge and a falling edge of a data strobe signal on the bi-directional data strobe inputs.