Patent ID: 6417049
Filing Date: 2002-07-09
Classification: G11C,H01L

Abstract:
A method for producing a split gate multiple storage flash cell, comprising:a) forming a silicon nitride layer on a semiconductor substrate covering a thin silicon oxide layer, b) patterning and etching said silicon nitride layer to form areas of silicon nitride on the surface of said substrate in rows and columns, c) oxide dipping of said substrate and growing tunnel oxide, d) depositing a first layer of polysilicon over the surface of said substrate, e) etching said first layer of polysilicon to form sidewall spacers on said areas of silicon nitride, f) patterning and ion-implanting buried bit lines in columns between adjacent areas of silicon nitride, wherein said buried bit lines function as sources and drains for split gate flash memory cells, g) removing said silicon nitride, h) depositing ONO (oxide-nitride-oxide) over the surface of said substrate, i) depositing a second layer of polysilicon over the ONO on the surface of said substrate, j) patterning and etching said second layer of polysilicon to form word lines, wherein each said word line connects together control gates in a row of said split gate flash memory cells, k) forming sources and drains for peripheral devices, l) forming inter-layer dielectric, m) patterning and depositing interconnecting metal vias and lines.