Patent ID: 6674319
Filing Date: 2004-01-06
Classification: G06F,Y02D

Abstract:
A power-down circuit comprising:a differential pair of lines that are connected together by a shunt resistor that equalizes a first voltage on a first differential line with a second voltage on a second differential line when a differential transmitter is powered down in a high-impedance state; a first n-channel sensing transistor having a gate driven by the first differential line, a drain coupled to a power supply, and a source coupled to a first source node; a second p-channel sensing transistor having a gate driven by the second differential line, a drain coupled to a sense node, and a source coupled to the first source node; a second n-channel sensing transistor having a gate driven by the second differential line, a drain coupled to the power supply, and a source coupled to a second source node; a first p-channel sensing transistor having a gate driven by the first differential line, a drain coupled to the sense node, and a source coupled to the second source node; an output n-channel transistor, having a gate connected to the sense node, and a drain connected to an output representing a power-down signal; a pull-up connected between the output and the power supply for driving the output high when the output transistor is not conducting current; a pull-down connected between the sense node and a ground for driving the sense node low when the first and second p-channel transistors and the first and second n-channel transistors are turned-off when the first and second differential lines have voltages within a transistor threshold of each other.