Patent ID: 6782445
Filing Date: 2004-08-24
Classification: G06F

Abstract:
A computer system, comprising:a first processor; a second processor for use as a coprocessor to the first processor; a memory; at least one data buffer for buffering data to be written to or read from the memory in data bursts in accordance with burst instructions; a burst controller for executing the burst instructions; a burst instructions element for providing burst instructions in a sequence for execution by the burst controller; and a synchronization mechanism for synchronizing execution of coprocessor instructions and burst instructions with availability of data on which said coprocessor instructions and burst instructions are to execute; whereby burst instructions are provided by the first processor to the burst instructions element, and data is read from the memory as input data to the second processor and written to the memory as output data from the second processor through the at least one data buffer in accordance with burst instructions executed by the burst controller.