Patent ID: 6350687
Filing Date: 2002-02-26
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device on a wafer, which method comprises the steps of:forming a Cu or Cu alloy interconnection pattern comprising a dense array of spaced apart Cu or Cu alloy lines having surfaces bordering an open dielectric field on a surface of the wafer; forming a passivating layer on the surfaces of the Cu or Cu alloy lines by: (a) treating the surfaces of the Cu or Cu alloy lines with a solution of a copper corrosion-inhibiting compound; or (b) electroless plating a metal layer on the surfaces of each of the Cu or Cu alloy lines; or (c) depositing a metallic compound on the surfaces of the Cu or Cu alloy lines by chemical vapor deposition (CVD); and capping the surfaces of the Cu or Cu alloy lines with a nitride compound wherein immediately before capping, the passivation layer is removed to expose the surfaces of the Cu or Cu alloy lines.