Patent ID: 6737305
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A Thin Film Transistor (TFT) manufacture method, comprising:providing a substrate; forming a gate on the substrate; forming a gate isolation layer on the substrate and covering the gate; forming a first a-Si layer on the gate isolation layer that is arranged above the gate by using a Chemical Vapor Deposition (CVD) method, wherein the first a-Si layer is formed under a condition of a flux ratio of H2/SiH4 within a range from 0.40 to 1.00; forming a second a-Si layer on the first a-Si layer by using the CVD method; performing a N-type deposition on a surface of the second a-Si layer to form a N+Mixed a-Si layer; defining the first a-Si layer, the second a-Si layer, and the N+Mixed a-Si layer to form a channel layer; and forming a source/drain on both sides of the channel layer.