Patent ID: 7248243
Filing Date: 2007-07-24
Classification: G09G,H03K

Abstract:
1. A level shifter circuit comprising: two or more level shifters each supplied with a corresponding one of a plurality of clock signals which are out of phase with each other so as to have non-overlapping high level periods and/or non-overlapping low level periods; and level shifting control circuitry, wherein each level shifter level shifts the clock signal supplied thereto so that a high level of the clock signal is shifted to one of a high level and a level of a specified power voltage and a low level of the clock signal is shifted to the other of the high level and the low level of the specified power voltage, each level shifter comprises a level shift section including a constant current source that generates a constant current during a non-active period of the clock signal supplied to the level shifter, and the level shifting control circuitry suspends the level shifting of a respective level shifter during at least a portion of the non-active period of the clock signal supplied to the respective level shifter by preventing flow of the constant current from the constant current source thereof, wherein respective active periods of the clock signals are non-overlapping, wherein the level shifting of each respective level shifter is suspended during portions of the non-active period of the corresponding clock signal that correspond to the active period of one or more other clock signals; and wherein the level shifting control circuitry suspends the level shifting of a respective level shifter based on a logical combination of a first signal indicative of an output of the respective level shifter and a second signal indicative of outputs of all the level shifters.