Patent ID: 6541379
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A method of forming wirings for a semiconductor device, which comprises the steps of forming concaved wiring channels in an insulation film formed on a semiconductor substrate, forming a first conductor layer having a first deposition overvoltage as a deposition overvoltage required for depositing a copper series metal material in a plating solution to the surface of the simulation film at least including the inner surface of the concaved portion of the wiring channels, forming a second conductor layer having a second deposition overvoltage higher than the first deposition overvoltage as the deposition overvoltage to the surface of the insulation film so as to cover a region except for the inner surface of the concaved portion of the wiring channels, subsequently, dipping at least the inner surface of the concaved portion of the wiring channels into the plating solution and applying a plating treatment to the region in which the first conductor layer is exposed at a deposition overvoltage higher than the first deposition overvoltage and lower than the second deposition overvoltage to deposit the copper series metal material, and polishing the deposited metal material thereby forming wirings.