Patent ID: 8946001
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A method for fabricating metal oxide (MOS) transistors, the method comprising: forming an active region, between an area designated for a first array of transistors arranged in parallel in a first block and an area designated for a second array of transistors arranged in parallel in a second block without forming the active region between transistors in the first array of transistors and between transistors within the second array of transistors, wherein the active region resides separately from the first array of transistors and the second array of transistors and is physically isolated from any transistor in the first array of transistors and the second array of transistors, and wherein the active region is a single floating region without metallic connection to any other region, and wherein the active region resides between and is in direct contact with a shallow trench isolation region of the first array of transistors and a shallow trench isolation region of the second array of transistors.