Patent ID: 6813185
Filing Date: 2004-11-02
Classification: G11C

Abstract:
A non-volatile memory device, comprising:a flash memory having a plurality of banks and a bank selection register which can take on states at least equal in number to the number of said banks and which outputs a signal for pointing to one of said banks corresponding to one of said states; and a controller having a plurality of data buffers, each of which corresponds to one of said banks, respectively, wherein each of said banks includes a plurality of word lines, a plurality of bit lines arranged to intersect said word lines, a plurality of memory cells, each of which is located at intersections of one of the word lines and one of the bit lines, and a data register which temporarily holds the data to be written to said memory cells, and wherein said controller transmits the data in said data buffer to said data register of said one bank, while said flash memory writes the data held in said data register of another one of said banks to said memory cells thereof.