Patent ID: 8761326
Filing Date: 2014-06-24
Classification: H04L

Abstract:
1. A compensating device for detecting and compensating for a sampling clock offset in a receiver, comprising: a sampling clock offset detector, comprising: a plurality of calculation paths, each for receiving a time domain signal and a hypothetic offset, calculating a plurality of correlation coefficients between the time domain signal and a delayed version of the time domain signal according to a predetermined delay and the hypothetic offset, calculating a plurality of correlation coefficient sums according to the correlation coefficients, and extracting a maximum correlation coefficient sum for the hypothetic offset from the correlation coefficient sums; and a controller, coupled to the calculation paths, for providing different hypothetic offsets to each calculation path and detecting the sampling clock offset according to the maximum correlation coefficient sums obtained from the calculation paths; and a sampling clock offset compensator, coupled to the sampling clock offset detector for receiving the sampling clock offset therefrom and compensating for the sampling clock offset on a signal generated in a signal processing path of the receiver.