Patent ID: 6868033
Filing Date: 2005-03-15
Classification: G11C

Abstract:
1. A storage cell, comprising: a. a bit storage member capable of storing a data bit and including a true data output, having a true data value corresponding to the data bit, and a complement data output, having a complement data value corresponding to a logical complement of the true data value; b. a first controllable gate electronically coupled to the true data output, the first controllable gate responsive to a first read enable signal so that the true data value is passed through the first controllable gate to a first read port when the first read enable signal is asserted; and c. a second controllable gate electronically coupled to the complement data output, the second controllable gate responsive to a second read enable signal, different from the first read enable signal, so that the complement data value is passed through the second controllable gate to a second read port, different from the first read port, when the second read enable signal is asserted, whereby the complement data value may be accessed independently from the true data value.