Patent ID: 8187947
Filing Date: 2012-05-29
Classification: H01L

Abstract:
1. A method for fabricating a layered capacitor of a semiconductor device, the method comprising: a) isotropically oxidizing and/or nitriding walls of a trench structure to provide wall protection; b) anisotropically depositing a conductive material in the trench structure, a deposition rate at the walls being lower than at a bottom of the trench structure at least by at least a factor of two; c) depositing a dielectric material in the trench structure on the conductive material, such that a deposition rate at the walls is lower than at the bottom of the trench structure; d) producing a selective protective layer on a layer made of the dielectric material at the bottom of the trench structure; e) etching-back a layer sequence deposited on the walls up to the wall protection; and f) repeating b) to e) until the trench structure is filled.