Patent ID: 6124868
Filing Date: 2000-09-26
Classification: G06F

Abstract:
A processing system comprises:a host processor that includes local cache memory, wherein the host processor generates a plurality of data blocks that relates to a particular application, wherein each of the plurality of data blocks includes a plurality of data elements, and wherein each of the plurality of data elements includes at least one of: a command and data;memory operably coupled to the host processor, wherein the memory includes a memory section that stores data elements of the plurality of data elements of one of the plurality of data blocks in a ring buffer manner as instructed by the host processor, wherein the host processor updates a head pointer as the data elements are stored in the memory section and stores the updated head pointer in the local cache memory;a co-processor operably coupled to the host processor and the memory, wherein the co-processor includes local registers, wherein the co-processor receives the updated head pointer and stores the updated head pointer in one of the local registers, wherein the co-processor retrieves the data elements from the memory section to perform at least a portion of the particular application.