Patent ID: 7188215
Filing Date: 2007-03-06
Classification: G06F

Abstract:
1. A microprocessor apparatus, for performing a memory copy operation, the apparatus comprising: translation logic, configured to translate an allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first cache line in an exclusive state and to copy the contents of a second cache line to said first cache line, wherein said allocate and rename instruction comprises a modification to an existing prefetch instruction within an existing instruction set, and wherein said existing prefetch instruction does not otherwise provide for allocation and rename of said first cache line, and wherein said allocate and rename instruction comprises a prefetch opcode field within an extended address specifier entity, and wherein a specific value of said prefetch opcode field directs said microprocessor to allocate said first cache line in said exclusive state and to copy said contents of said second cache line to said first cache line, and wherein other values of said prefetch opcode field direct said microprocessor to execute other types of prefetch operations according to said existing instruction set, and wherein said prefetch opcode field comprises bits execution logic, coupled to said translation logic, configured to receive said micro instruction sequence, and configured to issue transactions over a memory bus that request said first cache line in said exclusive state, and configured to copy said contents of said second cache line to said first cache line.