Patent ID: 7154798
Filing Date: 2006-12-26
Classification: G11C

Abstract:
1. An array of magnetic memory cells, each of the memory cells comprising a stack of a free ferromagnetic layer, a pinned ferromagnetic layer, and an insulating tunneling barrier located therebetween, wherein a combination of a writing signal and a magnetic field may exceed a threshold magnetic field of corresponding select memory cells to alter the resistance of those memory cells, the array comprising: a plurality of magnetic memory cells coupled together; first conductive lines corresponding to each of the plurality of memory cells for applying an adjustable signal proximate to select ones of the memory cells to be read, the adjustable signal creating a magnetic field sufficient to alter a magnetic moment of the select memory cells; a second conductive line perpendicular to the first conductive line for applying a first read signal through the plurality of memory cells, and for applying a second read signal to the plurality of memory cells while the adjustable signal is applied to the select memory cells; and a sensing circuit coupled to the second conductive line and configured to compare the first reading signal to the second reading signal to determine a logic state of each of the select memory cells.