Patent ID: 6331945
Filing Date: 2001-12-18
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a memory cell array having memory cells in a matrix, each of said memory cells having a charge storing layer and a control gate electrode, and storing data corresponding to an amount of charge in said charge storing layer;memory cell selecting means for selecting read cells for data read from the memory cells;data latch circuits for latching data read from said read cells at the same time, said data latch circuits corresponding to said read cells, respectively;a data latch selecting circuit for selecting one of said data latch circuits when said read cells store data of plural bits, and selecting at lcast two of said data latch circuits when said read cells store data of one bit;data lines for receiving output data of said one or more data latch circuits; anda data input/output buffer for transferring the output data of said data lines to a data input/output terminal.