Patent ID: 6460063
Filing Date: 2002-10-01
Classification: G06F

Abstract:
A division circuit that performs a log2 operation on complements of a divided and divisor to calculate indexes for each, shifts said complements by said indexes, then calculates a reciprocal value of the result of shifting of said complement of the divisor by a reciprocal processing means, multiplies the result of shifting of said divided with the calculated reciprocal value, shifts the multiplication result by exactly a shift amount corresponding to the indexes of the divided and divisor, and calculates a result of division in a digital form, said division circuit comprising:a complement processing means for outputting a complement of 1 of the divisor when the divisor is negative; an adding means for adding â€œ1â€  to the output from the complement processing means and making the result of the adding operation an absolute value when the divisor is negative; a logarithm processing means for calculating a logarithm of 2 of an output value of said complement processing means and calculating an integer value of the calculated logarithm; a shift processing means for shifting said absolute value according to said integer value; a MSB replacing means for making a calculation value of the shift processing means a mantissa when the MSB of the calculation value is â€œ1â€ , making the calculation value with a MSB replaced by â€œ1â€  the mantissa when the MSB of the calculation value is â€œ0â€ , and outputting the mantissa to the reciprocal processing means; and a shift amount determining means for subtracting said integer value from said index of said divided when the MSS of the calculation result of said shift processing means is â€œ1â€ , subtracting said integer value plus â€œ1â€  from said index of said divided when the MSB of the calculation result of said shift processing means is â€œ0â€ , and making the result of subtraction said shift amount.