Patent ID: 6743646
Filing Date: 2004-06-01
Classification: G01N,H01L

Abstract:
A method of designing underlying struck in a wafer that balances planarization and optical metrology characteristics, the method comprising:fabricating underlying structures including one or more pads the one or more pads varying in size and/or shape; comparing planarization characteristics of planarized layer or layers of the wafer to preset standard planarization characteristics; fabricating target structures in the target layer of the wafer; measuring a reflected metrology signal off a target structure fabricated above a calibration test area of the target layer of the wafer to obtain a calibration metrology signal, the calibration test area having an unpatterned underlying structure; and selecting the design of pads of the underlying structure that yields a reflected metrology signal off the target structure above a patterned area that is closest to the calibration metrology signal and that meet the preset standard planarization characteristics.