Patent ID: 6124611
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A vertical MOS device arranged on a substrate of a first conductivity type, the vertical MOS device being fabricated according to the following steps:doping a first area of the substrate to form a first doped region having a second conductivity type;after the step of doping in a first area, forming an epitaxial layer of the first conductivity type over the first doped region, a portion of the epitaxial layer providing a channel for the vertical MOS device;doping in a second area to form a second doped region, the second doped region having the second conductivity type and residing above the portion of the epitaxial layer that provides the channel;forming a trench that extends through the first doped region, the epitaxial layer, and the second doped region; andforming a gate electrode in the trench, the gate electrode being separated from the first and second doped regions by an insulating layer.