Patent ID: 6762634
Filing Date: 2004-07-13
Classification: H03L

Abstract:
An offsetting phase-locked loop (PLL) comprising:a primary phase comparator, receiving a reference clock and a primary feedback clock; a primary filter capacitor for generating a primary filter voltage; a primary charge pump, activated by phase differences detected by the primary phase comparator, for charging and discharging the primary filter capacitor; a primary voltage-controlled oscillator (VCO) for generating a primary output clock having an output frequency that is a function of a primary VCO input voltage of a primary VCO input; an op amp having a first input receiving the primary filter voltage, and an output driving the primary VCO input; an offset resistor, coupled between the primary VCO input and a second input to the op amp; a digital-to-analog converter (DAC) receiving a digital value, for generating a DAC current as a function of the digital value, the DAC current being driven through the offset resistor; a secondary phase comparator, receiving the reference clock and a secondary feedback clock; a secondary filter capacitor for generating a secondary filter voltage; a secondary charge pump, activated by phase differences detected by the secondary phase comparator, for charging and discharging the secondary filter capacitor; a secondary voltage-controlled oscillator (VCO) for generating a secondary output clock having an output frequency that is a function of the secondary filter voltage; and a coupling switch, between the secondary VCO and the primary phase comparator, for coupling the secondary output clock to the primary feedback clock after the DAC generates the DAC current, whereby the DAC generates the DAC current to offset a voltage of the primary VCO input.