Patent ID: 9030009
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A method for manufacturing a stacked semiconductor package, comprising the steps of: forming a first through electrode in a first semiconductor chip formed at a first surface of a first wafer; etching a second surface of the wafer opposing to the first surface such that the first through electrode is protruded above the second surface of the wafer; forming a first polymer layer that covers the second surface of the wafer and exposes the first through electrode; attaching a first surface of a second semiconductor chip onto the first semiconductor chip by medium of the first polymer layer, the first surface of the second semiconductor chip being formed with a bonding pad having a through hole which corresponds to the first through electrode; forming a second polymer layer over the first polymer layer including the second semiconductor chip; etching the second polymer layer and the second semiconductor chip to form a via hole which is connected with the through hole and by which the bonding pad and the first through electrode are exposed; forming a second through electrode in the via hole and the through hole, the second through electrode being electrically connected with the bonding pad and the first through electrode; and individualizing a stacked semiconductor package by cutting the first and second polymer layers and the wafer.