Patent ID: 7884748
Filing Date: 2011-02-08
Classification: G04F,H03M

Abstract:
1. An analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator ( 101 ), a clock ( 102 ), a digital counter ( 103 ) timed by the clock ( 102 ), and at least one channel ( 10 1 , . . . , 10 i , . . . , 10 n ) for data processing, the or each channel comprising a comparator ( 20 1 , . . . , 20 i , . . . , 20 n ) having an input connected to the ramp generator ( 101 ) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data, characterized in that the or each channel ( 10 1 , . . . , 10 i , . . . , 10 n ) further comprises a delay-chain time interpolator ( 40 1 , . . . , 40 i , . . . , 40 n , 50 1 , . . . , 50 i , . . . , 50 n ) responsive to the output of the comparator and to the clock ( 102 ), for interpolating time within a clock period (T c ) from the triggering time (t i1 ) of the comparator ( 20 i ), said interpolator delivering a time-interpolation output signal as a fine conversion data which is combined to the coarse conversion data for each conversion cycle.