Patent ID: 7782291
Filing Date: 2010-08-24
Classification: G09G

Abstract:
1. A driving circuit for a liquid crystal display, comprising: a first transistor comprising a source electrode, a drain electrode, and a gate electrode, the source electrode configured for receiving a first voltage signal, and the drain electrode configured for providing the first voltage signal to a first circuit of the liquid crystal display; a first bias resistor connected between the gate electrode and the source electrode of the first transistor; a second transistor comprising an emitter electrode, a collector electrode, and a base electrode, the emitter electrode configured for receiving a second voltage signal, and the collector electrode configured for providing the second voltage signal to a second circuit of the liquid crystal display; a second bias resistor connected between the base electrode and the emitter electrode of the second transistor; a delay circuit, comprising a first control pin connected to the gate electrode of the first transistor, and a second control pin connected to the base electrode of the second transistor, the delay circuit configured for delaying the first voltage signal for a first predetermined time period and the second voltage signal for a second predetermined time period; and a third transistor comprising an emitter electrode, a collector electrode, and a base electrode, the emitter electrode configured for receiving a third voltage signal, and the collector electrode configured for providing the third voltage signal to a third circuit of the liquid crystal display; and a third bias resistor connected between the base electrode and the emitter electrode of the third transistor; wherein the delay circuit further comprises a third control pin connected to the base electrode of the third transistor, and the delay circuit is further configured for delaying the third voltage signal for a third predetermined time period; wherein the delay circuit further comprises a timing controller, a state machine, a fourth transistor, a fifth transistor, and a sixth transistor, the timing controller is configured for providing an oscillatory signal to the state machine, the state machine comprises three control terminals respectively connected to gate electrodes of the fourth, fifth, and sixth transistors, source electrodes of the fifth and sixth transistors are connected to ground, drain electrodes of the fifth and sixth transistors are respectively defined as the second control pin and the third control pin, a source electrode of the fourth transistor is connected to a power supply, and a drain electrode of the fourth transistor is defined as the first control pin.