Patent ID: 6823427
Filing Date: 2004-11-23
Classification: G06F

Abstract:
A computer system comprising:a processor, a system memory; an N-way set-associative cache coupled to the processor, wherein the cache comprises a memory logically divided into at least one set, wherein each set comprises N ways, wherein each set is further partitioned into a plurality of sectors, wherein each sector comprises a plurality of the N ways, and wherein each way is configured to store a line from the system memory; and a plurality of pointer registers each configured to store a pointer value identifying one of the sectors in an associated one of the sets, wherein a least recently used (LRU) pointer register associated with a first set is configured to store a LRU pointer value identifying a LRU sector within the first set, wherein a most recently used (MRU)) pointer register associated with the first set is configured to store a MRU pointer value identifying a MRU sector within the first set; and a cache controller coupled to the pointer registers and configured to perform a fill in the first set by reading the value stored in the LRU pointer register and filling one of the ways within the LRU sector in the first set.