Patent ID: 9177834
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor die; a package casing encapsulating the semiconductor die and lying in a plane defined by first and second orthogonal directions, the package casing having four main side walls each oriented generally parallel with one of the first or second directions; a plurality of signal leads electrically coupled to the semiconductor die and each having an embedded portion located within the package casing and an exposed portion extending from one of the main side walls of the package casing in a direction generally parallel with one of the first or second directions; one or more power bars electrically coupled to the semiconductor die and embedded in the package casing, each of the one or more power bars extending generally parallel to one of the first or second directions, each of the one or more power bars having at least one power bar lead at least partially embedded in the package casing and extending from the power bar at a generally non-zero angle with respect to the first and second directions, the one or more power bars and associated power bar leads being electrically isolated from the plurality of signal leads; and one or more tie bars, each of which is at least partially embedded in the package casing and extends at a generally non-zero angle with respect to the first and second directions, the one or more tie bars being electrically isolated from the plurality of signal leads and the one or more power bars and associated power bar leads.