Patent ID: 7659202
Filing Date: 2010-02-09
Classification: H01L,Y10T

Abstract:
1. A method performed on a chip, wherein the chip includes a doped semiconductor and a substrate, the method comprising: etching an annulus trench from an outer surface of the doped semiconductor, through the doped semiconductor, and partially into the substrate to a total depth of at least 100 microns; metallizing an inner and an outer perimeter side wall of the annulus trench by applying a metal thereto; etching a via trench into the chip between the outer surface and the substrate, wherein the via trench is peripherally bounded within a portion of the doped semiconductor that is within a periphery of the annulus trench, wherein the via trench has a periphery and a bottom, and wherein the via trench is bounded by the doped semiconductor and, at the bottom, by the substrate; making a length of the via trench and at least a portion of the bottom of the via trench electrically conductive by applying an electrically conductive material thereto, wherein the length extends from the substrate to the outer surface; and thinning a surface of the substrate opposite the doped semiconductor to expose both the metal and the electrically conductive material so that the metal on the outer and inner perimeter side walls are electrically separated from each other and from the electrically conductive material.