Patent ID: 6263405
Filing Date: 2001-07-17
Classification: G06F

Abstract:
A multiprocessor system comprising:a plurality of processor units each having at least one processor and at least one cache memory provided corresponding to said processor;at least one memory unit providing a shared memory area shared by said processor units; andan interconnection apparatus which interconnects said processor units and said at least one memory unit, said interconnection apparatus retrieves cache status reports from respective ones of said processor units in response to a memory access request requiring a cache coherency check issued by either one of said processor units, each of said cache status reports indicating caching status of a corresponding one of said processor units as to a caching line in said shared memory area which is an object of said cache coherency check, sums up said cache status reports into a cache status summary which indicates a total caching status of said processor units as to said caching line, and transfers said cache status summary to said one of said processor units which issued said memory access request.