Patent ID: 6411543
Filing Date: 2002-06-25
Classification: G11C,H01L

Abstract:
A semiconductor storage device formed on a semiconductor substrate, the substrate including:a memory array including at least one word line, at least one pair of complementary data lines, and memory cells disposed in association with crosspoints between the word line and the complementary data lines; a sense amplifier coupled with the paired complementary data lines, a first voltage line, and a second voltage line; a word line driver linked with the word line; a first voltage terminal; a second voltage terminal; a first voltage generator circuit; a second voltage generator circuit; and a write circuit, wherein: the memory cell includes a MOSFET and a capacitor including a pair of electrodes, the MOSFET includes a gate connected to the word line and two source-drain routes, one of the source-drain routes being coupled with one of the paired data lines; one of the paired electrodes of the capacitor is linked with a remaining one of the source-drain routes of the MOSFET; the first voltage terminal is supplied with a first voltage from an external device; the second voltage terminal is supplied with a second voltage from an external device; the first voltage generator circuit receives the first and second voltages and outputs to the first voltage line a third voltage higher than the first voltage and lower than the second voltage; the second voltage generator circuit receives the first and second voltages and outputs to the second voltage line a fourth voltage higher than the third voltage and lower than the second voltage; the word line driver supplies the first or second voltage to the word line, and wherein the write circuit provides the complementary data lines with a write signal having a high level corresponding to the fourth voltage and a low level corresponding to the third voltage.