Patent ID: 6191491
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a plurality of input/output circuits arranged to form a row in input/output circuits along each edge of a semiconductor chip; andinput/output pads arranged between the row of input/output circuits and the edge of the semiconductor chip to form a first and a second row of input/output pads, the first row of input/output pads being located beside the edge of the semiconductor chip, the second row of input/output pads being located beside the row of input/output circuits, the input/output pads of the first and second rows of input/output pads being connected to the input/output circuits,wherein, in the first row of input/output pads, the input/output pads are grouped into groups each consisting of a plurality of input/output pads, with those groups arranged with spaces between them so that wires can be arranged through those spaces, and, in the second row of input/output pads, the input/output pads are arranged in such positions where they are connected to the wires arranged through those spaces,wherein, within each group, the input/output pads are arranged at intervals far shorter than a width of the spaces,wherein the device has inner leads that are connected by way of wires to the input/output pads, and wires connecting the input/output pads in the first row to inner leads and wires connecting the input/output pads in the second row to inner leads are all arranged at an identical height.