Patent ID: 8954770
Filing Date: 2015-02-10
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a first domain located on a die and including at least one core to execute instructions; a second domain located on the die and including at least one functional unit to execute a specialized function, wherein the first and second domains can operate at independent frequencies; and a power control unit (PCU) coupled to the first and second domains, the PCU including a thermal logic to cause a reduction in a frequency of the first domain by a frequency bin of the processor based on a value of a counter for the first domain in response to a temperature of the second domain exceeding a sum of a throttle threshold for the second domain and a cross-domain margin, wherein the thermal logic is, for each of a plurality of iterations, to update the counter value for the first domain when the second domain temperature is determined to exceed the sum, wherein the cross-domain margin is a programmable temperature margin parameter stored in a configuration non-volatile storage of the processor accessible to the thermal logic and corresponds to a marginal level above the throttle threshold for the second domain at which a power consumption of the first domain is to be reduced to allow the temperature of the second domain to be reduced, the frequency bin corresponding to a smallest multiple by which the first domain frequency can change.