Patent ID: 6080660
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method for manufacturing a via comprising:providing a semiconductor substrate having a device layer formed thereon;forming a conductive layer over the semiconductor substrate, wherein the conductive layer is electrically connected to the device layer, and then patterning the conductive layer to form a conductive line;forming a dielectric layer over the conductive line;performing a photolithographic operation and a first etching operation to form an opening in the dielectric layer exposing the conductive line surface, wherein the opening is for forming the via, and that the bottom of the opening has a re-entrance structure; andperforming a second etching operation by etching a portion of the conductive line to form a slanting planar surface at the bottom of the opening so that the reentrance structure is eliminated and the bottom of the opening planarized, and hence step coverage of the subsequently deposited material is increased.