Patent ID: 6124625
Filing Date: 2000-09-26
Classification: H01L,H05K

Abstract:
A semiconductor memory device formed on a semiconductor substrate, the device comprising(a) a plurality of active devices;(b) a voltage regulator circuit;(c) at least one regulated conductive line bus extending along the substrate and coupled between at least one of the active circuit devices and the voltage regulator circuit;(d) at least one second conductive line bus extending along the substrate and coupled between at least one of the active circuit devices and external connection points of the semiconductor memory device;(e) a capacitor including a first capacitor node, an active area of the substrate included within the first capacitor node, the capacitor also including a polysilicon layer as a second capacitor node, the capacitor being in electrical communication with at least one regulated conductive line bus and being in electrical communication with at least one second conductive line bus,(f) the first capacitor node including a first heavily doped region and a second heavily doped region, the first and second heavily doped regions being on opposing sides of the polysilicon layer, wherein one of the at least one regulated conductive line bus or the at least one second conductive line bus makes contact to both of the first and second heavily doped regions;(g) the capacitor occupying a space defined by one or more of the at least one second conductive line bus or the at least one regulated conductive line bus; and being located on the substrate in an area which is unoccupied by said active circuit devices; and(h) wherein the capacitor forms an on-chip bus decoupling capacitor, thereby adding filter capacitance to the semiconductor circuit device in order to provide protection from voltage transients.