Patent ID: 6099100
Filing Date: 2000-08-08
Classification: H03K

Abstract:
A CMOS (Complementary Metal Oxide Semiconductor) digital level shift circuit, comprising:an inverter including transistors connected between a first source voltage and a ground voltage, and outputting one of the first source voltage and the ground voltage in accordance with a logic state of an input signal; anda latch circuit outputting one of a second source voltage and the ground voltage in accordance with logic states of the input signal and an output signal of the inverter, wherein the latch circuit includes,a latch unit having first and second PMOS transistor with their sources connected to the second source voltage, and first and second NMOS transistors with their sources connected to the ground voltage, anda voltage distributor disposed between the first and second PMOS transistors and the first and second NMOS transistors and externally outputting one of the second source voltage and the ground voltage, the voltage distributor including,third and fifth PMOS transistors and third and fifth NMOS transistors serially connected between the first PMOS transistor and the first NMOS transistor, andfourth and sixth PMOS transistors and fourth and sixth NMOS transistors serially connected between the second PMOS transistor and the second NMOS transistor.