Patent ID: 6122730
Filing Date: 2000-09-19
Classification: G06F

Abstract:
An arithmetic apparatus for executing a TMH (Test under Mask High) and a TML (Test under Mask Low) instruction, the TMH and TML instructions each comprising a field in which a 2-byte constant used as a test mask is stored, a field in which information specifying a 4-byte general register is stored, a field in which information discriminating between the TMH and TML instructions is stored, the TMH instruction specifying as an operand the most significant 2 bytes of the specified 4-byte general register, the TML instruction specifying as an operand the least significant two bytes of the specified general register, the arithmetic apparatus selecting every bit of the 2-byte operand specified by the input TMH or TML instruction that corresponds to a bit ""1"" of the test mask, and setting a condition code depending on the state of the selected bit, said arithmetic apparatus comprising:a first circuit for detecting that a result of ANDing the test mask included in the input instruction and an operand specified by the input instruction indicates all ""0""'s which is a necessary condition for setting the condition code at ""0"";a second circuit for detecting an operand bit corresponding to a leftmost bit which is ""1"" of the test mask, a necessary condition for setting the condition code at ""1"" or ""2"" being that the operand bit is ""0"" or ""1"";a third circuit for detecting that a result of ORing an inverse of the test mask and the specified operand is all ""1""'s, which is a necessary condition for setting the condition code at ""3""; anda fourth circuit for producing the condition code by combining the results of the detection by said first, second and third circuits.