Patent ID: 6151248
Filing Date: 2000-11-21
Classification: G11C,H01L

Abstract:
An array of non-volatile memory cells on a semiconductor substrate, comprising:a two-dimensional array of floating gates arranged in rows extending in a first direction across the substrate with spaces therebetween and columns extending in a second direction across the substrate with spaces therebetween, said first and second directions being orthogonal with each other, a first set of spaces separating the columns of floating gates including ones of every other space across the substrate in the first direction and a second set of spaces separating the columns of floating gates including remaining ones of every other space across the substrate in the first direction in between the first set of spaces,elongated source and drain diffusions having lengths extending across the substrate in the second direction and spaced apart in the first direction coincident with the first set of spaces between the columns of floating gates,elongated steering gates having lengths extending across the substrate in the second direction, having widths individually extending across two adjacent columns of floating gates and positioned within the first set of spaces therebetween, and being spaced apart in the first direction with the second set of spaces between the columns of floating gates therebetween, andelongated select gates having lengths extending in the first direction along rows of floating gates, over steering gates and extending into said second set of spaces between adjacent columns of floating gates in the second set of spaces, said select gates being spaced apart in the second direction.