Patent ID: 6312996
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A method for fabricating a semiconductor device comprising:a semiconductor layer of a first conductivity type;a source region of a second conductivity type formed within the semiconductor layer;a drain region of the second conductivity type formed within the semiconductor layer;a channel region provided between the source and drain regions;a gate electrode formed over the channel region; anda buried region of the first conductivity type having at least a part included in the drain region, the method comprising the steps of:doping the semiconductor layer with a dopant of the second conductivity type for the drain region; anddoping the semiconductor layer with a dopant of the first conductivity type for the buried region,the step of doping the semiconductor layer with the dopant of the first conductivity type including the steps of:forming, on the semiconductor layer, a multilayer resist mask having an opening configured to correspond to the buried region; andimplanting ions of the dopant of the first conductivity type into the semiconductor layer via the multilayer resist mask by high-energy ion implantation.