Patent ID: 9124420
Filing Date: 2015-09-01
Classification: H04L

Abstract:
1. An encryption processing device, comprising: an F function processing unit that divides (m×k)-bit input data into k blocks (m and k are both even numbers) of m-bit word (referred to as “word” hereinafter) x0, x1, . . . , xk−2, xk−1, and that outputs as a word Yi+1(i =0, 2, . . . , k−2) a word obtained as a result of an operation between the word xi+1 and a result of an operation of an F-function using key data on the word xi, while outputting the word xi as a word Yi; and a transposition processing unit that divides the word Yi (i=0, 1, . . . , k−1) into s blocks (s=2, 4, . . . , m) of sub-words Yi, 0, Yi, 1, . . . , Yi, s−1, transposes a sub-word Yi, w[x] into a sub-word Zpx[i], w[y] with a transposition condition Px (x=1, 2, . . . , s/2−1) and a transposition condition Qx (x=1, 2, . . . , s/2−1), transposes a sub-word Yi, w[y] into a sub-word Zqx[i], w[x], and that outputs a word Zi, 0 Zi, 1...Zi, s−1 as an i-th word, wherein