Patent ID: 8477532
Filing Date: 2013-07-02
Classification: G11C

Abstract:
1. A flash memory device, comprising: a wordline voltage generator generating a plurality of wordline voltages for reading a memory cell, the plurality of wordline voltages including a first wordline voltage having a first voltage level, a second wordline voltage having a second voltage level, and a third wordline voltage having a third voltage level higher than the first and second voltage levels; a plurality of first switches respectively receiving the plurality of wordline voltages from the wordline voltage generator to switch and output each of the plurality of wordline voltages to an output node during one read cycle; a second switch receiving an initialization voltage to switch and output the initialization voltage to the output node; a row decoder connected to the output node of the first and second switches and driving a wordline of the memory cell; and a controller generating a plurality of control signals for controlling the first and second switches, respectively, such that the initialization voltage is provided to the output node immediately after each of the second wordline voltage and the third wordline voltage is provided to the output node within the one read cycle.