Patent ID: 8278710
Filing Date: 2012-10-02
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate of a first conductivity type; a first semiconductor region of a second conductivity type different from the first conductivity type located in the substrate; a first well region of the first conductivity type located in the substrate adjacent to the first semiconductor region; a first source region of the second conductivity type located in a predetermined upper region of the first well region; a drain region of the second conductivity type located in a predetermined upper region of the first semiconductor region, the drain region being spaced a predetermined distance from the first well region; a gate electrode located over a gate insulating layer and having an edge substantially aligned with an edge of the source region, thereby defining a first channel region inside the first well region; and a substrate injection suppression feature of the second conductivity type located in the substrate, wherein the substrate injection suppression feature comprises a buried layer and a conductive vertical portion conductively coupled to the buried layer, wherein the buried layer is disposed below the first well region but not below the drain region.