Patent ID: 8624649
Filing Date: 2014-01-07
Classification: G01R,H03H

Abstract:
1. A delay measuring circuit comprising: a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, in which an input signal and an output signal have a one-to-one correspondence with each other, changes, generates a first trigger signal; a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal; a delay unit that includes a plurality of delay elements, which delay the first trigger signal generated by the first trigger-signal generating unit, connected in series; and a delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit.