Patent ID: 6970035
Filing Date: 2005-11-29
Classification: H02M

Abstract:
1. A charge pump circuit comprising: a plurality of switching transistors connected in series between an output terminal and reference potential terminal of the charge pump circuit, where n the plurality of switching transistors includes a first transistor connected to the reference potential terminal and a second transistor connected to the first transistor, and wherein the first transistor has a control terminal provided with a first clock signal, and the second transistor has a control terminal provided with a second clock signal, the first and second clock signals having inverted phases; a capacitor connected to a node between the first and second transistors and having a first terminal and a second terminal; a delay circuit connected between the second terminal of the capacitor and the control terminal of the first transistor, wherein the delay circuit delays the first clock signal, which is provided to the control terminal of the first transistor, by a predetermined time and provides the delayed first clock signal to the second terminal of the capacitor such that the second transistor changes its state later than the timing at which the first transistor changes its state from an ON state to an OFF state; and a timing adjustment circuit for the first and second clock signals so that a during which the first and second transistors are simultaneously deactivated exists, wherein the timing adjustment circuit generates the second clock signal based on the delayed signal provided to the second terminal of the capacitor.