Patent ID: 6052328
Filing Date: 2000-04-18
Classification: G11C

Abstract:
A semiconductor memory device for storing data, the semiconductor memory device comprising:a memory where data signals are stored;an input/output port for writing and reading data signals to and from the semiconductor memory device;pairs of data lines in series for passing data signals from the memory to the input/output port, the same pairs of data lines that are used during a read operation to pass data signals from the memory to the input/output port also being used during a write operation to pass data signals from the input/output port to the memory;a timing logic circuit, the timing logic circuit controlling the timing cycles of when data signals are passed to and from each of the pairs of data lines during the read operation, the timing logic circuit during the write operation disabling all of the timing cycles for all of the pairs of data lines except the pair closest to the memory so that write data may be overdriven onto the pairs of data lines without concern for the normal timing cycles for those data lines, the write data being transferred during the write operation to the pair of data lines closest to the memory for which the timing cycle is still active at approximately the same point during the timing cycle that the read data is transferred during the read operation.