Patent ID: 7598771
Filing Date: 2009-10-06
Classification: H03K

Abstract:
1. A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, and each stage comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising: a first node and a second node; a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source functioning as the output end outputs an output signal; a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a first low-potential voltage, and the drain is coupled to the first node; a charge/discharge circuit, for receiving an input signal and a control signal, and coupled to the second node; a threshold voltage detector, for receiving the control signal, and coupled to the first node and the source of the driving transistor; and a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor.