Patent ID: 6564237
Filing Date: 2003-05-13
Classification: G06F,H03M

Abstract:
A data processing unit comprising: a control unit which, when executing an instruction, outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison reference data setting signal, and an end flag signal; a first memory to which said memory read control signal is input; a first data register to which said comparison reference data setting signal is input to set comparison reference data therein; a second data register which stores data from said first memory; a number-of-retrievals counter to which said instruction execution signal is input, and which outputs to said control unit a count of the number of data retrievals so far performed on said first memory; an execution unit to which said instruction execution signal and output data from said first data register and said second data register are input, and which outputs a comparison signal and an execution data signal; and a second memory to which said memory write control signal, said execution data signal from said execution unit, and said end flag signal are input, and wherein:when executing a comparison instruction, said output data from said first data register and said second data register are loaded by said instruction execution signal into said execution unit for data comparison and, at the same time, said number-of-retrievals counter is made to count up, wherein said end flag signal is held inactive until the output of said number-of-retrievals counter reaches a predetermined value and, upon the output of said number-of-retrievals counter reaching said predetermined value, said control unit terminates said comparison instruction and sets said end flag signal active, while said comparison signal from said execution unit is output to said control unit to control writing to said second memory so that said end flag signal and said execution data signal, indicating the number of times that said output data matched and data from said first memory that did not match said comparison reference data, are written to said second memory when said end flag signal is held inactive and also when said end flag signal is set active.