Patent ID: 6073246
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A circuit for controlling skew and non-overlapping period between two clocks, including a two-phase non-overlapping clock generator for providing a first output clock and a second output clock and receiving a first input clock; a first clock tree means for buffering said first output clock from said two-phase non-overlapping clock generator; a second clock tree means for buffering said second output clock from said two-phase non-overlapping clock generator; a first latch/flip-flop group for latching data in response to said first output clock from said first clock tree means; and a second latch/flip-flop group for latching data in response to said second output clock from said second clock tree means,wherein said two-phase non-overlapping clock generator comprises a programmable delay block for delaying and receiving said first and said second output clocks in order to control skew and non-overlapping period between said first output clock and said second clock.