Patent ID: 6063670
Filing Date: 2000-05-16
Classification: H01L,Y10S

Abstract:
A method for fabricating an integrated circuit having multiple gate dielectric thicknesses, comprising the steps of:forming a first gate dielectric layer over a semiconductor body;forming a first disposable layer over said first gate dielectric layer, said first disposable layer comprising a material selectively etchable with respect to said first gate dielectric layer and said semiconductor body;forming a pattern over said first disposable layer, said pattern covering a first region of said disposable layer and exposing a second region of said disposable layer;removing at least a portion of said first disposable layer in said second region using said pattern;removing said pattern while said substrate is not exposed;removing at least a portion of said first gate dielectric layer in said second region; andsubsequent to removing said pattern, forming a second gate dielectric layer in said second region, said second gate dielectric layer having a thickness different from said first dielectric layer.