Patent ID: 7971119
Filing Date: 2011-06-28
Classification: G01R

Abstract:
1. A method for defect-based scan analysis comprising: for a node in a first circuit, determining a neighborhood net; injecting defects into the neighborhood net and modeling the defects with stuck-at-0 and stuck-at-1 fault models; generating test patterns and applying the patterns to the neighborhood net with the injected defects; determining whether the injected defects are observable as faults; if the defects are observable as faults, adding the test patterns to a set of effective test patterns; mapping the test patterns in the set of effective test patterns to possible stuck-at-0 faults or stuck-at-1 faults and collecting stuck-at-0 fault test patterns and stuck-at-1 fault test patterns; performing stuck-at-0 fault simulation using the stuck-at-0 fault test patterns and generating a first fault list; performing stuck-at-1 fault simulation using the stuck-at-1 fault test patterns and generating a second fault list; combining the first and second fault lists into combined fault lists and deriving a description of the combined fault lists using a complete set of fault models; filtering the combined fault lists to yield a collection of effective faults, the filtering including removing faults with less effective coverage of the defects than the effective faults; and determining a defect for each fault in the collection of effective faults.