Patent ID: 6157209
Filing Date: 2000-12-05
Classification: G06F,H03K

Abstract:
A loadable up-down counter implemented in an FPGA comprising a plurality of stages, each stage providing one counter bit and comprising:a register providing a counter bit output signal G0;a four-input LUT programmed to generate the functionG=(G1 AND ((G0 XOR G3)) OR (G1 AND G2)and receiving:the counter bit output signal G0,a load signal G1,an up-down signal G3, anda starting data value G2;an AND gate receiving the load signal G1 and the counter bit output signal G0 and providing an AND gate output signal; anda carry multiplexer providing a carry multiplexer output signal, and receiving as input signals the AND gate output signal and a carry multiplexer output signal from another stage.