Patent ID: 6698006
Filing Date: 2004-02-24
Classification: G06F

Abstract:
A method for inserting a clock tree for distributing a clock signal in an integrated circuit design, comprising:providing a physical design representative of said integrated circuit design, said physical design comprising locations for a plurality of clock signal endpoints to which said clock signal connects; specifying a location for placing a root node of said clock tree in said physical design; constructing an array of buffers as said clock tree, said array of buffers connecting said clock signal from said root node to said plurality of clock signal endpoints, wherein insertion delay from said root node to each of said plurality of clock signal endpoints meets a predefined maximum insertion delay constraint, each buffer of said array of buffers being selected according to a capacitive gain of said buffer; identifying locations in said clock tree where clock skew violations occur and correcting said clock skew violations by introducing delay at buffer locations in said clock tree; and identifying locations in said clock tree where minimum insertion delay violations occur and correcting said minimum insertion delay violations by slowing down the arrival times of clock signal endpoints of said clock tree.