Patent ID: 6445017
Filing Date: 2002-09-03
Classification: G11C,H01L,Y10S

Abstract:
A full CMOS SRAM cell comprising:first and second active regions formed on a semiconductor substrate, the first and second active regions being arranged parallel to each other; third and fourth active regions formed on the semiconductor substrate between the first active region and the second active region, the third and fourth active regions being arranged parallel to the first and second active regions, respectively, and being arranged in a region neighboring the first active region and a region neighboring the second active region, respectively; a word line intersecting the first and second active regions; a first common conductive electrode intersecting the first active region and the third active region, the first common conductive electrode being parallel to the word line; and a second common conductive electrode intersecting the second active region 14 and the fourth active region, the second common conductive electrode being parallel to is the word line; a first transfer transistor having the word line as a gate electrode, formed in the first active region; a first driver transistor having the first common conductive electrode as a gate electrode, formed in the first active region; a first load transistor having the first common conductive electrode as a gate electrode, formed in the third active region; a second transfer transistor having the word line as a gate electrode, formed in the second active region; a second driver transistor having the second common conductive electrode as a gate electrode, formed in the second active region; and a second load transistor having the second common conductive electrode as a gate electrode, formed in the fourth active region.