Patent ID: 6552402
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A composite MOS transistor device comprising at least a pair of MOS transistors, the MOS transistor pair having almost equal gate lengths comprising first and second MOS transistors placed in a row to the gate longitudinal direction on the same board,wherein the first and second MOS transistors are made up of first and second groups of divided transistors of almost equal gate lengths, respectively, wherein the divided transistors of the first group are arranged in said row in the gate longitudinal direction and the divided transistors of the second group are aldo arranged in the same one row as the divided transistors of the first group; and wherein the first and second MOS transistors are arranged such that each sum of coordinates of respective gates are zero in the first and second groups of divided transistors when measured from a predetermined reference coordinate along the gate longitudinal direction.