Patent ID: 6852577
Filing Date: 2005-02-08
Classification: H01L

Abstract:
1. A method for forming a low temperature polysilicon complementary metal oxide semiconductor thin film transistor (LTPS CMOS TFT) on a substrate, the substrate surface comprising a first region for forming a first type MOS TFT and a second region for forming a second type MOS TFT, the method comprising the steps of: forming a patterned undoped polysilicon layer on both the first region and the second region of the substrate; forming a gate insulating layer on each patterned undoped polysilicon layer; forming two first type doped areas in the patterned polysilicon layer of the first region that is not covered by the gate insulating layer; forming two second type doped areas in the patterned polysilicon layer of the second region that is not covered by the gate insulating layer; forming a gate electrode on each gate insulating layer, and forming a source layer and a drain layer on both the first type doped areas and both the second type doped areas; forming two first type lightly doped drain (LDD) areas in the patterned undoped polysilicon layer of the first region that is not covered by the gate electrode, the source layer, and the drain layer; forming a patterned interlayer dielectric (ILD) on the substrate, the patterned interlayer dielectric comprising a plurality of via holes formed on each source layer and each drain layer; and filling a transparent conductive layer into the via holes.