Patent ID: 9112056
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A method of forming a semiconductor device in an NVM (non-volatile memory) region and in a logic region using a semiconductor substrate, comprising: forming a gate material layer over the substrate in the NVM region and the logic region; patterning the gate material layer over the NVM region to form a control gate opening, the control gate opening having an exposed surface; forming a charge storage layer over the exposed surface; forming a control gate in the control gate opening over the charge storage layer; removing the gate material layer from the logic region; forming a high-k layer over the substrate in the logic region; forming a dummy gate layer over the high-k layer; patterning the gate material layer over the NVM region to leave a select gate adjacent to the control gate; patterning the dummy gate layer to leave a dummy gate over the high-k layer; forming an interlayer dielectric around the dummy gate and around the control gate and select gate; and replacing the dummy gate with a metallic logic gate.