Patent ID: 7287147
Filing Date: 2007-10-23
Classification: G06F

Abstract:
1. A coprocessor interface between a central processing unit (CPU) and a coprocessor, the interface comprising: an instruction transfer signal group for transferring a plurality of instruction types from the CPU to the coprocessor; and a busy signal group, coupled to said instruction transfer signal group, for signaling said instruction transfer signal group when one or more of said plurality of instruction types cannot be transferred; wherein when said instruction transfer signal group receives said signaling for one or more of said plurality of instruction types, said instruction transfer signal group does not transfer those instruction types, but transfers other ones of said plurality of instruction types; wherein said instruction transfer signal group is configured to transfer two or more of said plurality of instruction types from the CPU to the coprocessor, in parallel; wherein said two or more of said plurality of instruction types that are transferred in parallel are of a same type.