Patent ID: 6160754
Filing Date: 2000-12-12
Classification: G11C

Abstract:
In a synchronous memory device of a wave pipeline structure having a plurality of registers connected in parallel between a global input/output line and an output driver, a synchronous memory device of a wave pipeline structure comprising:an internal clock signal generation means which generates an internal clock signal being a standard of an output data only during a period in which an output enable signal is activated, said internal clock signal generation means including,a delay part which delays an external clock signal by a predetermined time;a clock rising-period sensing part which is connected to an output terminal of the delay part, and senses a rising-period of the external clock signal; anda logic operation part which receives the output enable signal and an output signal of the clock rising-period sensing part, performs a logic operation about them, and generates an internal clock signal having a constant pulse width in the rising period of the external clock signal; anda data transmission means which is connected between an output terminal of the plurality of registers and the output driver, is switched by a control of the internal clock signal, receives data stored in an activated register as an input, and transmits the data to the output driver.