Patent ID: 8539133
Filing Date: 2013-09-17
Classification: G06F

Abstract:
1. An embedded system comprising: an Advanced Reduced Instruction Set Computer Machine (ARM) processor comprising a plurality of pins P a plurality of b-bit peripheral processors, wherein the number of the plurality of b-bit peripheral processors is N, and each team corresponds to one b-bit peripheral processor; and a converting chip connected among the ARM processor and the plurality of b-bit peripheral processors respectively; wherein when an a-bit data from the ARM processor needs to be transferred to the plurality of b-bit peripheral processors, the converting chip reads and stores the a-bit data from the ARM processor, converts the a-bit data into a plurality of b-bit data, and transfers each b-bit data to a corresponding peripheral processor, where the number of the plurality of the b-bit data is N; when a b-bit data from one of the plurality of b-bit peripheral processors needs to be transferred to the ARM processor, the converting chip reads and stores one b-bit data from each peripheral processor in sequence, converts the read plurality of b-bit data into an a-bit data, and transfers the converted a-bit data to the ARM processor; when one peripheral processor does not need to transfer data to the ARM processor, the b-bit data read from the peripheral processor is set as “00000000”.