Patent ID: 6046984
Filing Date: 2000-04-04
Classification: G06F

Abstract:
A method for tracing combinational paths through a network of an integrated circuit to verify proper operation, the method comprising:for nodes on a data path which fanout to downstream clock-controlled circuit elements, identifying subnetworks driven by these driving nodes;determining worst-case data propagation times through the subnetworks and worst-case arrival time information of deskewing clocks at the downstream clock-controlled elements;replacing these subnetworks with pruning records for each of the driving nodes of the subnetworks where each pruning record contains the worst-case data propagation times through the subnetworks, deskewing clocks at the downstream clock-controlled elements, the worst-case arrival time information of the deskewing clocks at the downstream clock-controlled elements, and timing characteristics of the downstream clock-controlled elements;determining worst-case data path delays between upstream nodes and the driving nodes; andusing the pruning records at the driving nodes to identify paths that will operate correctly.