Patent ID: 6539536
Filing Date: 2003-03-25
Classification: G06F

Abstract:
In an electronic design automation system, a method of generating a netlist description comprising the computer implemented steps of:a) accessing an HDL specification representing an integrated circuit to be realized in physical form and accessing constraints applicable to said electronic design; b) compiling said HDL specification with a compiler to produce a netlist description of said integrated circuit wherein said netlist description comprises multi-bit cells, multi-bit components and combinational logic, said step b) comprising the steps of: b1) inserting scannable multi-bit cells and scannable multi-bit components by replacing said multi-bit cells and said multi-bit components with equivalent scannable multi-bit cells and equivalent scannable multi-bit components, respectively; and b2) installing a loopback connection between a scan-out port of a respective scannable multi-bit cell and a scan-in port of said respective scannable multi-bit cell; and b3) installing a loopback connection between a scan-out port of a respective scannable multi-bit component and a scan-in port of said respective scannable multi-bit component; and c) storing said netlist description into computer memory.