Patent ID: 7960237
Filing Date: 2011-06-14
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure comprising: providing a structure that at includes at least one gate region located on a surface of a semiconductor substrate, said at least one gate region comprising source/drain regions and source/drain extension regions in said semiconductor substrate that are separated by a channel region, a gate dielectric and a gate conductor located above said channel region, an offset spacer located on sidewalls of at least said gate conductor and an outer spacer adjacent said offset spacer and silicide contacts located atop the source/drain regions adjacent said outer spacer; removing said outer spacer to expose a surface portion of the semiconductor substrate including said source/drain extension regions; selectively plating a metallic or intermetallic material by electroless plating on said exposed surface portion of said semiconductor substrate including said source/drain extension regions and on and above said silicide contacts, wherein said metallic or intermetallic material does not cover the entirety of said offset spacer during said selective plating; and forming a liner that introduces stress into said channel region, wherein said liner is formed over a portion of said selectively plated metallic or intermetallic material that overlies one of said silicide contacts.