Patent ID: 6703663
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprising:the combination of a gate oxide layer and a gate electrode layer patterned into gate electrode stacks with sidewalls formed over a substrate including an NMOS FET device over a P-well in said substrate and a PMOS FET device over aN-well, Pâˆ’ lightly doped source/drain regions formed in said N-well, Nâˆ’ lightly doped source/drain regions formed in said P-well, spacers formed on said sidewalls of said gate electrode stacks, N+ type source/drain regions in said P-well in said source/drain sites self-aligned with a said gate electrode stack, P+ type source/drain regions in said N-well in said source/drain sites self-aligned with a said gate electrode stack, heavily doped, counterdoped P++ regions formed directly below said P+ source/drain sites self-aligned with said gate electrode and said spacers in said N-well, heavily doped, counterdoped N++ regions formed directly below said N+ source/drain sites self-aligned with said gate electrode and said spacers in said P-well, deep Nâˆ’ lightly doped source/drain regions formed in said N-well directly below said counterdoped P++ regions, and deep Pâˆ’ lightly doped source/drain regions formed in said P-well directly below said counterdoped N++ regions.