Patent ID: 6319727
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method for manufacturing a low stress metallic interconnect line, the method comprising:forming a first layer of dielectric material on a semiconductor substrate;forming a multi-layer stack on the first layer of dielectric material;patterning the multi-layer stack to form at least one multi-layer metallic interconnect line;depositing a second dielectric material layer to cover the multi-layer metallic interconnect line using a deposition temperature that does not exceed a first temperature valve T.sub.1 ; andthermally treating the multi-layer metallic interconnect line and the second dielectric material layer at a thermal treatment temperature valve T.sub.2 that is greater than the first temperature valve T.sub.1,wherein the step of forming a multi-layer stack includes forming at first and second layers, the first adjoining layers being a metal M layer and the second adjoining layer being a material Q layer, where material Q is selected from the group consisting of materials that form an electrically conductive intermetallic layer with metal M when subjected to the thermally treating step and materials that form an electrically conductive solid solution layer with metal M when subjected to the thermally treating step.