Patent ID: 8745548
Filing Date: 2014-06-03
Classification: G03F,G06F

Abstract:
1. A process of generating design rules for an integrated circuit layout by a non-iterative process, comprising the steps of: generating an initial model for an illuminator for a photolithographic process; generating a set of characteristic design rules for layout features of said integrated circuit layout; generating a set of template structures which use said set of design rules; generating a matrix of said template structures with a range of values for said design rules, so that each row of said matrix includes one instance of each of said of said template structures, with a different set of said values of said design rules in each said row; performing, by a computer, a source mask optimization (SMO) operation on each instance of said template structures in each of said matrix rows, starting with said initial model for said illuminator, in which said illuminator model is optimized for all instances of said template structures in said matrix, so that said SMO operation provides a separate optimized mask geometry for each instance of said template structures in each of said matrix rows; and estimating a lithography figure of merit for each said matrix row, for printed patterns of said template structures when printed using an illumination source based on said optimized illumination source model and optimized mask geometries for said matrix row provided by said SMO operation on said matrix row, and noting instances of failing features which are estimated to fail to print correctly.