Patent ID: 6047367
Filing Date: 2000-04-04
Classification: G06F

Abstract:
A computer system having a hierarchical memory with cache storage for instructions and data, comprising,at least one conventional processing element for processing instructions with at least one instruction pipeline of a defined length and defined delay per pipeline stage;and an additional speculative engine processing element for processing instructions, including out-of-order instructions, for instruction sequences which derive finite cache improvement from out-of-order processing, whereinsaid additional speculative engine processing element and said conventional processing element are coupled for action in concert to process a stream of instructions with said conventional processing element maintaining the architectural state of concerted action with its pipeline handles while said speculative engine processing element handles speculative processes whose result may not change the architectural state of the computer system but which improves the finite cache penalty seen by said conventional processing element, and wherein said speculative processing element includesm registers in a central processing area, m being greater than a predetermined n number of instruction addressable GPRs identified by one or more binary fields of an instruction, and provision for out of order instruction execution and for processing a conditional branch instruction based on a branch direction guess,said conventional processing element being coupled to a coprocessor providing said additional speculative engine processing element for independent prefetching and execution of instructions to improve the sequence of storage references as seen by said conventional processing element,said system using a register management process enabling generation of speculative memory references to said storage hierarchy including said instruction and data cache coupled to and shared by both said additional speculative engine processing element and said conventional processing element,and further including,an instruction and data cache coupled to both said conventional out of order processing element and to said coprocessor providing said additional speculative engine processing element for fetching instructions and data, and an independent store buffer for bidirectional transfer of instructions and data in response to store and fetch commands of said additional speculative engine processing element.