Patent ID: 6041002
Filing Date: 2000-03-21
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array structured by a plurality of memory cells disposed in a row and column matrix shape, each memory cell being connected to a bit line and a word line;a row decoder for selecting one word line from said plurality of word lines based on an address signal from outside;a non-selective state setting circuit for setting all of said plurality of word lines to a non-selective state according to test mode signal;a column decoder for selecting a column from which data is to be read and into which data is to be written, from a plurality of columns within said memory cell array based on the address signal from outside;a data input and output line used for data input and output between said memory cell array and an external terminal and for being connected to a bit line of a selected column;a selective-state setting circuit for setting all of said plurality of columns within said memory cell array to a selective-state according to said test mode signal; andtest mode signal generating circuit for generating said test mode signal in test mode for testing a leakage of a charge held in a memory cell.