Patent ID: 6771105
Filing Date: 2004-08-03
Classification: H03K,H03L

Abstract:
A variable delay cell comprising:a plurality of load resistance transistors connectable in parallel with one another; a plurality of bias current transistors connectable in parallel with one another; a switching transistor connected in series between the plurality of load resistance transistors and the plurality of bias current transistors; switching circuitry configured to selectively operatively connect at least a first one of the load resistance transistors in parallel with at least one other of the load resistance transistors; further switching circuitry configured to selectively operatively connect at least a first one of the bias current transistors in parallel with at least one other of the bias current transistors; and other switching circuitry configurable to selectively operatively connect at least a second one of the load resistance transistors in parallel with the at least one other of the load resistance transistors.