Patent ID: 8067968
Filing Date: 2011-11-29
Classification: H03L

Abstract:
1. A DLL circuit, comprising: a phase detecting block configured to compare and detect phases of a reference clock signal and a feedback clock signal to generate a phase detection signal; a locking state detector configured to enable a locking state signal when the phase difference between the reference clock signal and the feedback clock signal is below a first phase difference range, and to disable the locking state signal only when the phase difference between the reference clock signal and the feedback clock signal exceeds a second phase difference range that is wider than the first phase difference range; a delay controlling block configured to generate a delay control signal in response to the phase detection signal and the locking state signal; a delay line configured to delay the reference clock signal in response to the delay control signal to generate a delay clock signal; and a delay compensating block configured to apply a delay to the delay clock signal to generate the feedback clock signal.