Patent ID: 8964477
Filing Date: 2015-02-24
Classification: G11C

Abstract:
1. A nonvolatile memory comprising: a memory cell array having a first bit line connected to N memory cells; a reference cell array having a second bit line connected to M reference cells, the M being smaller than the N; a comparator which compares a first electric current which flows along the first bit line with a second electric current which flows along the second bit line; and a gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in the N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in the M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to the memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to the reference cell array, wherein an electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.