Patent ID: 6591340
Filing Date: 2003-07-08
Classification: G06F

Abstract:
In a data processing system having a cache memory and a translation lookaside buffer, a method comprising the steps of:receiving a logical address and permission information associated with a memory access operation; accessing the cache memory, and determining if there is a match between the logical address of the memory access operation and logical address information stored in the cache memory; if there is a match between the logical address of the memory access operation and logical address information of the cache memory and if the memory access operation is not permitted based on a comparison of the permission information associated with the memory access operation and permission information of the cache memory, then accessing the translation lookaside buffer based on the logical address; if there is a match between the logical address of the memory access operation and logical address information of the translation lookaside buffer and if the memory access operation is permitted by permission information of the translation lookaside buffer, then updating the permission information of the cache memory based on the permission information of the translation lookaside buffer.