Patent ID: 6081022
Filing Date: 2000-06-27
Classification: H01L,H05K

Abstract:
A method for shielding a plurality of signal lines in an integrated circuit having a first conductive layer and a second conductive layer, said method comprising:forming a first signal line and a second signal line in said first conductive layer of said integrated circuit, wherein said first and second signal lines comprise said plurality of signal lines;forming in said first conductive layer a first shield line, wherein said first shield line is substantially parallel to said first signal line and said first shield line is adapted to be electrically connected to a source of ground potential;forming in said first conductive layer a second shield line, wherein said second shield line is substantially parallel to said second signal line, and said second shield line is adapted to be electrically connected to said source of ground potential;forming another plurality of signal lines in said second conductive layer, wherein a first subset of signal lines of said another plurality of signal lines crosses said first signal line in said first conductive layer, and a second subset of signal lines of said another plurality of signal lines crosses said second signal line in said first conductive layer;forming a first plurality of conductive regions in said second conductive layer, said first plurality of conductive regions substantially aligned with the first signal line in said first conductive layer and positioned between signal lines of said first subset of signal lines; andforming a second plurality of conductive regions in said second conductive layer, said second plurality of conductive regions substantially aligned with the second signal line in said first conductive layer and positioned between signal lines in said second subset of signal lines, wherein said first and second pluralities of conductive regions include a substantially equal number of conductive regions.