Patent ID: 7576422
Filing Date: 2009-08-18
Classification: H01L

Abstract:
1. A semiconductor device comprising: a printed wiring board including a first main surface, a second main surface opposing to the first main surface, a plurality of first conductor portions formed over the first main surface, a plurality of second conductor portions formed over the second main surface, a first resist film covering the plurality of first conductor portions such that a part of each of the plurality of first conductor portions is exposed from the first resist film, and a second resist film covering the plurality of second conductor portions such that a part of each of the plurality of second conductor portions is exposed from the second resist film; a first semiconductor chip, including a main surface, a back surface opposing to the main surface of the first semiconductor chip, and a plurality of first electrodes formed over the main surface of the first semiconductor chip, the first semiconductor chip being mounted over the first main surface of the printed wiring board by way of a plurality of bump electrodes such that the main surface of the first semiconductor chip is facing towards the first main surface of the printed wiring board; a resin arranged between the first main surface of the printed wiring board and the main surface of the first semiconductor chip; a second semiconductor chip including a main surface, a back surface opposing to the main surface of the second semiconductor chip, and a plurality of second electrodes formed over the main surface of the second semiconductor chip, the second semiconductor chip being mounted over the first semiconductor chip by way of a die-bonding film such that the back surface of the second semiconductor chip is facing towards the back surface of the first semiconductor chip; a plurality of conductive wires electrically connecting the plurality of second electrodes of the second semiconductor chip with the part of each of the plurality of first conductor portions, respectively; and a sealing body sealing the first semiconductor chip, the second semiconductor chip and the plurality of conductive wires, wherein the part of each of the plurality of first conductor portions is arranged around the first semiconductor chip, and wherein the second semiconductor chip is dimensioned larger than that of the first semiconductor chip.