Patent ID: 6917995
Filing Date: 2005-07-12
Classification: G06F

Abstract:
1. An integrated circuit device which is a first LSI and issues a command to a second LSI to make the second LSI execute a corresponding processing, said first and second LSIs being connected with a bi-directional command bus, comprising: a counter, to count a value, a reset value of the counted value being a number of command stages which said second LSI can simultaneously process, the reset value being decremented or incremented when said command is issued and is incremented or decremented when a ready signal indicating command processing completion is received from said second LSI; a command issuing control circuit which inhibits issuing of a command when said counter value becomes a predetermined value; and a bus arbiter circuit which issues a grant signal for granting access to said command bus to said second LSI responding to a request signal for requesting access to said command bus from said second LSI, wherein said command issuing control circuit inhibits issuing of a command when said grant signal is issued.