Patent ID: 6931476
Filing Date: 2005-08-16
Classification: G06F

Abstract:
1. An electronic apparatus including a CPU core for carrying out pipeline processing according to data read via a data bus from a read-only memory that stores specified fixed data, said electronic apparatus including an instruction correcting circuit in said CPU core, said instruction correcting circuit comprising: a set of memory cells for storing, when initializing said electronic apparatus, a correction address, a correction instruction and a correction enabling bit, which are associated with contents of said read-only memory; a comparator for comparing an instruction address output from an instruction prefetch stage of said CPU core with the correction address stored in said memory cells; and a selector for selecting one of an instruction code read from the instruction address of said read-only memory and the correction instruction stored in said memory cells in response to a compared result of said comparator wherein said instruction correcting circuit is placed between the instruction prefetch stage and an instruction decoding stage in said CPU core.