Patent ID: 8331156
Filing Date: 2012-12-11
Classification: G11C

Abstract:
1. A nonvolatile semiconductor storage device comprising: a first well region of a first conductivity type in which a first cell array including a plurality of memory cells is formed; a second well region of the first conductivity type in which a second cell array including a plurality of memory cells is formed; a third well region of a second conductivity type including the first and second well regions; a bit line connected to the memory cells included in the first cell array and the memory cells included in the second cell array; and a column decoder connected to the bit line, wherein in an erase operation, the first well region and the third well region are set at a first voltage, and the second well region is set at a second voltage lower than the first voltage, when erasing is performed on a memory cell targeted for erasing in the first cell array, and a third voltage lower than the second voltage is applied to a gate of the memory cell targeted for erasing in the first cell array, and a fourth voltage lower than the second voltage and higher than the third voltage is applied to gates of the memory cells other than the memory cell targeted for erasing.