Patent ID: 8019980
Filing Date: 2011-09-13
Classification: G06F

Abstract:
1. A branch target buffer (BTB) method for storing an address variation field of a complete target address of a branch instruction and reconstructing the complete target address in an architecture having a plurality of branch target buffer entries stored in a branch target buffer system, comprising the steps of: dividing said complete target address into said address variation field and an identical field, said address variation field being determined by a maximum address variation range that said complete target address varies from an instruction address of said branch instruction and said identical field covering a number of identical address bits between said complete target address and said instruction address of said branch instruction; storing said address variation field, a carry bit and a sub/add bit in a branch target buffer entry, said carry bit and said sub/add bit being determined based on whether a carry bit is needed, and whether a subtraction/addition operation is needed to generate said complete target address from said identical field and said address variation field; computing a partial address field from a coming instruction address by incrementing, decrementing or unchanging the identical field in said coming instruction address according to said carry bit and said sub/add bit from said branch target buffer entry when said branch instruction needs to jump to said complete target address; and reconstructing said complete target address by combining said partial address field and said address variation field from said branch target buffer entry.