Patent ID: 6189092
Filing Date: 2001-02-13
Classification: G06F

Abstract:
A processor for executing a program loop at a high speed using a register instruction which is set immediately before the program loop and a loop instruction which is set at an end of the program loop, the processor comprising: a fetch unit for fetching code from a memory; a decoding unit for decoding an instruction included in the fetched code; and an execution unit for executing the decoded instruction,the decoding unit includinga decoded instruction counter for storing and updating a pointer specifying an instruction that is being decoded, the pointer being a sum of a fixed shift value and an address of the instruction that is being decoded, andthe execution unit including:storage means for storing, when the decoding unit decodes the register instruction, instruction code at a start of the program loop that has been fetched by the fetch unit into a first buffer and storing the pointer stored in the decoded instruction counter into a second buffer; andhigh-speed branch means for having the fetch unit fetch code, when the loop instruction has been decoded by the decoding unit and a branch condition is satisfied, starting from an address that corresponds to the pointer stored in the second buffer and for having the decoding unit decode the instruction code stored in the first buffer,wherein the fixed shift value is determined so that the pointer in the second buffer corresponds to an address of code that follows the instruction code stored in the first buffer.