Patent ID: 8861280
Filing Date: 2014-10-14
Classification: G11C,H01L

Abstract:
1. A method for performing an erase operation, comprising: pre-charging a channel of a plurality of selected memory cells, the pre-charging of the channel comprises applying a pre-charge voltage to one end of the channel, the plurality of selected memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the channel is in a pillar which extends vertically in the three-dimensional non-volatile memory and the pillar comprises an active area of the plurality of selected memory cells; and subsequently, for each selected memory cell of the plurality of selected memory cells, erasing the memory cell by applying an erase voltage, higher than the pre-charge voltage, to the one end of the channel to charge the channel higher while configuring a control gate voltage of the selected memory cell to encourage erasing of the selected memory cell in an erase period, a timing of the erase period is based on a position of the selected memory cell in the channel.