Patent ID: 8183624
Filing Date: 2012-05-22
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface; a memory cell array formed on the first upper surface, wherein the memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers, the first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction, and the second interconnection layers extend upward and are separated from each other by insulating films; a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array; and a plurality of contacts respectively formed on upper ends of the second interconnection layers, wherein the first interconnection layers and the second interconnection layers comprise continuous layers, respectively, the upper ends of the second interconnection layers are leveled with the second upper surface, and the contacts are laid out obliquely to the first direction.