Patent ID: 6033984
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A method of forming an integrated circuit, said method comprising:providing an insulating layer, the insulating layer overlying a conductive element;forming an opening in the insulating layer by removing a portion of the insulating layer to expose the conductive element;forming a layer of conductive material over an upper surface of said insulating layer, said layer of conductive material substantially simultaneously filling said opening in the insulating layer;forming a layer of polishing resistant material on said layer of conductive material above said conductive element; andremoving portions of said layer of conductive material sufficient to expose said upper surface of said insulating layer wherein a portion of said layer of conductive material beneath said layer of polishing resistant material is removed at a slower rate than a portion of said layer of conductive material that is not beneath said layer of polishing resistant material.