Patent ID: 6403495
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method for forming a dynamic random access memory, said method comprising the steps of:forming a memory cell access transistor on a semiconductor substrate wherein said memory cell access transistor includes a source/drain at the surface of the semiconductor substrate; forming an insulating layer on said semiconductor substrate and said memory cell access transistor wherein said insulating layer has a contact hole therein exposing a portion of said source/drain of said memory cell access transistor; forming a first capacitor electrode on said insulating layer wherein said first capacitor electrode is connected to said source/drain of said memory cell access transistor through said contact hole; forming HSGâ€”silicon seeds on the surface of the first capacitor electrode and on said insulating layer; selectively growing said HSGâ€”silicon seeds on said first capacitor electrode to form enlarged HSG silicon bumps on said first capacitor electrode; removing said HSGâ€”silicon seeds formed on said insulating layer; forming a dielectric layer on said first capacitor electrode and on said HSGâ€”silicon seeds; and forming a second capacitor electrode on said dielectric layer opposite said first capacitor electrode.