Patent ID: 7386819
Filing Date: 2008-06-10
Classification: G06F

Abstract:
1. A method of verifying functional equivalence between a unit of FPGA circuitry that is programmed to perform a particular look-up table logic function and a unit of structured ASIC circuitry that is intended to perform that same function logic comprising: providing a design specification for the unit of structured ASIC circuitry; using the design specification to develop an FPGA design for programming FPGA circuitry; comparing FPGA circuitry programmed in accordance with the FPGA design to the unit of FPGA circuitry that is programmed to perform the particular look-up table logic function; and accepting the design specification for the unit of structured ASIC circuitry as functionally equivalent to the unit of FPGA circuitry only if the FPGA circuitry programmed in accordance with the FPGA design is the same as the unit of FPGA circuitry that is programmed to perform the particular look-up table logic function.