Patent ID: 6309930
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method for manufacturing an SRAM cell arrangement which includes a plurality of memory cells, wherein the manufacture of each memory cell respectively comprises the steps of:forming first, second, third, fourth, fifth and sixth vertical MOS transistors, wherein each transistor includes a gate electrode, a first source/drain region and a second source/drain region, and wherein the third and fourth transistors are complementary to the first, second, fifth and sixth transistors;forming a word line, first bit line and second bit line, wherein the first bit line is formed transversely relative to the word line and the second bit line is formed parallel to the first bit line;connecting the first source/drain region of the first transistor to both the first source/drain region of the second transistor and a first voltage terminal;connecting the second source/drain region of the first transistor to each of the first source/drain region of the first transistor, the first source/drain region of the fifth transistor, the gate electrode of the second transistor and the gate electrode of the fourth transistor;connecting the gate electrode of the first transistor to each of the second source/drain region of the second transistor, the first source/drain region of the fourth transistor, the gate electrode of the third transistor and the first source/drain region of the sixth transistor;connecting the second source/drain region of the third transistor to each of the second source/drain region of the fourth transistor and the a second voltage terminal;connecting the second source/drain region of the fifth transistor to the first bit line;connecting the gate electrode of the fifth transistor to both the gate electrode of the sixth transistor and the word line;connecting the second source/drain region of the sixth transistor to the second bit line;forming first, second and fourth trenches in a substrate, wherein the first, second and fourth trenches are substantially parallel to each other, wherein the first and second transistors are adjacent a second side wall of the first trench wherein the fifth and sixth transistors are adjacent a second side wall of the second trench, wherein the third and fourth transistors are adjacent a first side wall of the fourth trench, and wherein the word line is arranged along the second side wall of the second trench;providing the side walls of each of the first, second and fourth trenches with a gate dielectric;forming a first conductive structure that is connected to the first voltage terminal along the first trench;forming a second conductive structure that is connected to the second voltage terminal along the fourth trench;connecting both the first source/drain region of the first transistor and the first source/drain region of the second transistor to the first conductive structure; andconnecting both the second source/drain region of the third transistor and the second source/drain region of the fourth transistor to the second conductive structure.